Method for providing a power on reset signal with a quadratic current compared to an exponential current

Aspects of the present invention include a method, apparatus and device for generating a power on reset (POR) signal in relation to the crossing point of two currents wherein at least one current is a quadratic function and the other is an exponential function, where each has a mathematical correlation to a function of a predetermined power supply voltage.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to co-pending U.S. application Ser. No. 11/598,372, filed even date herewith, entitled: “Method for Providing a Power on Reset Signal with a Logarithmic Current Compared to an Exponential Current,” which is assigned to the assignee of the present invention and is also incorporated by reference herein.

FIELD OF INVENTION

The present invention relates generally to electrical circuits and more particularly to power on reset (POR) circuits.

BACKGROUND OF THE INVENTION

It is widely known that POR circuits, typically formed on a semiconductor chip or integrated circuit (IC), initially reset the internal circuits of the chip automatically when an operating voltage is first switched on to the chip. POR circuits typically prevent invalid conditions in an electrical circuit by ensuring that the electrical circuit has sufficient power before allowing it to operate at its necessary operating conditions. In an IC, for example, a POR circuit typically may be utilized to ensure that there is a provision for adequate voltage from a power source to the chip before the chip is operationally enabled.

In operation, the POR circuit enables the chip only when the power required to adequately power the chip is known to be available from the power source and is within a predetermined or specified range. If the power requirements are inadequate or where the power to be supplied is not within the acceptable range, the typical POR circuit maintains the chip to be inoperable or operationally disabled. This disabling characteristic may be overcome in typical POR circuits once a POR circuit determines that the needed power is available, usually via a voltage “trip point” of the POR. Once a predetermined voltage is received by the POR circuit, a threshold is met and the POR circuit typically thereafter enables the operation of the chip by a signal. Conversely, a signal may also be sent based on upon a determination that there is a voltage drop below a predetermined value whereafter the chip would be disabled. As used here, the signal used to enable or disable the chip is referred to as a “power on reset signal” or “POR signal.”

FIG. 1is a schematic representation of an exemplary POR circuit100. The POR circuit100is not intended to be the only representation of a POR circuit for use with or in consideration of the present invention as POR circuit100is exemplary of but one type of POR circuit. POR circuit100includes resistors110,120,130,140, and150(which form a resistor ladder), capacitors160and170, transistors180and190, a ground path at185, and an inverter199. POR circuit100is powered by a power source which may be a power supply at115having a voltage supply to the circuit of VSUPPLYand which may also be the same power supply providing power to the chip (not shown) controlled by POR circuit100.

Operationally, the resistor ladder produces a scaled version of VSUPPLYthat appears on node NVat125which controls the voltage on the gate of transistor180. When the scaled version of VSUPPLYreaches the threshold voltage (i.e., predetermine threshold voltage) of transistor180, transistor180will turn ON. Once operational, transistor180pulls the input voltage to inverter199via node NOat198to ground, resulting in a logical HIGH state output197(e.g., POR signal) at node NOUTof the inverter199, thereby enabling the chip (not shown) controlled by the POR circuit100.

In this arrangement, where VSUPPLYrises from ground to its operating level (i.e., in an OFF to ON scenario), the POR circuit100maintains the chip as being disabled until VSUPPLYachieves a value (i.e., voltage amount) sufficient to trip transistor180to an ON state (i.e., trip point threshold).

Conversely, the chip controlled by POR circuit100is disabled when NOUT197is at a logical LOW, as there is no pulling of voltage across NVat125to the inverter199. Instead, when VSUPPLYvoltage is below the trip point threshold, transistor180is disabled (e.g., OFF) and resistor150pulls the input voltage to inverter199to the VSUPPLYvoltage. Inverter199will interpret that VSUPPLYvoltage is at a logical HIGH, causing a logical LOW state output at197. The logical LOW state output at197serves as an active LOW reset signal (e.g., POR signal), which resets the chip and maintains it as remaining disabled.

Sensitivities to noise reduction to the POR circuit100are attempted to be reduced by employing capacitors160and170and transistor190. Capacitors160and170slow down the slew rate of nodes NVand NO. The effect of the slow down of the slew rate requires that VSUPPLYachieve or exceed the trip point threshold for a predetermined period of time before the voltage on NOcrosses the threshold of the inverter199(i.e., time counting).

Because typical ICs function over a range of power-supply voltages, the ICs may also commonly include a POR circuit that resets the IC to a known state upon application of power and holds the known state until the power supply voltages settle at or near some predetermined level. In this scenario, typically, the POR circuit is powered by the same source as the rest of the IC.

FIG. 2is a schematic representation of an exemplary POR circuit200including a voltage comparator210, a voltage divider220and a reference circuit230that provides stable reference voltages that have small variations with regard to process, supply-voltage, and temperature. An example of such a reference circuit may include a Band Gap Reference circuit, such as those discussed U.S. Pat. No. 6,489,835 to Yu et al. and U.S. Pat. No. 6,323,630 to Banba, both of which are incorporated herein by reference.

FromFIG. 2, the reference circuit230provides a signal VSIGat231to the non-inverting input of comparator210at211. The voltage divider220provides a reference voltage VREFat221that is a less than the supply voltage VSUPPat216, to the inverting input of comparator210at212. Comparator210compares the reference current signal VSIGand reference voltage VREFto generate a POR signal, PORSIG, at240.

A problem with typical POR circuits is that POR signals may be inaccurate as trip points may vary widely due to variations in the components, manufacturing or operating environment of resident devices. In part, this issue arises as a result of economical choices in components and operational activities versus highly-tolerant elections. Another issue arising with typical POR circuits is that POR circuits may be especially susceptible to process variations and are dependent on generated signals and voltage comparisons based on voltage-centric dependencies. Often POR circuits generate PORSIGby a simple comparison of voltage values including capacitor charge voltages via basic comparator operations, which are also susceptible to wide variations. Additionally, a further limitation of typical POR circuits is that time counting is employed and power supply sources are not monitored or evaluated.

Unfortunately, these limitations have thus proven to be unavoidable challenges in the field. As can be appreciated, reliable, economical and efficient techniques for generating accurate power on reset signals for various circuit and chip applications are highly desirable.

Accordingly, what is needed is a method and apparatus for generating precise power on reset signals by relating characteristics of typical components or circuits through a novel current architecture which permits voltage threshold monitoring that is cost effective and may be readily implemented.

SUMMARY OF THE INVENTION

The present invention fulfills these needs and has been developed in response to the present state of the art, and in particular, in response to the problems and needs in the art that have not yet been fully solved by currently available security protocols and technologies.

A method of providing a reliable power on reset (POR) signal with in accordance with a current architecture relating characteristics of typical POR attributes that also permits voltage threshold monitoring is disclosed.

A circuit capable of providing a reliable power on reset (POR) signal with in accordance with a current architecture relating characteristics of typical POR attributes that also permits voltage threshold monitoring is also disclosed.

An apparatus having a circuit capable of providing a reliable power on reset (POR) signal with in accordance with a current architecture relating characteristics of typical POR attributes that also permits voltage threshold monitoring is further disclosed.

In one embodiment, a method of providing a reliable power on reset (POR) signal using a current architecture comparing a first quadratic current with a second exponential current in relation to power supply voltage is presented.

In another embodiment of the present invention, a circuit providing a reliable power on reset (POR) signal (i.e., PORSIG) using a current architecture comparing a first quadratic current with a second exponential current in relation to power supply voltage is presented.

In a further embodiment of the present invention, an apparatus having a circuit providing a reliable power on reset (POR) signal (i.e., PORSIG) using a current architecture comparing a first quadratic current with a second exponential current in relation to power supply voltage is presented.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3illustrates one embodiment of the present invention as a method300of providing a reliable power on reset (POR) signal with in accordance with a current architecture relating characteristics of typical POR attributes that also permits voltage threshold.

InFIG. 3, a first current source320is generated using components, circuit devices or software in which the first current generated provides a first quadratic current source proportional to the square of the voltage supply, VSUPP, such as (VSUPP)2. A second current source330is also generated using components, circuit devices or software in which the second current generated provides a second current source preferentially proportional to the exponential of the voltage supply, VSUPP, such as exp(VSUPP). The first current value and the second current value, in a preferred embodiment, increase in value proportionate to their mathematical relations with the voltage supply during power supply ramping at340. The first current value and the second current value are then compared with one another at350as both currents entering a comparing means, such as transistors or a simple comparator, for example, where as a result of comparing the two current values, a determination of whether a crossing point has been reached in relation to the two current values. The crossing point of the two currents corresponds to a desired power supply voltage value and is further explained below. If the crossing point has not been attained at the point of comparison, a logical HIGH results at360with respect to an output POR signal at361. If the crossing point has been attained at the point of comparison, a logical LOW results at370with respect to an output POR signal at371.

In operation, both the first current source and the second current source will increase in value in relation to their mathematical formula. At a particular supply voltage, there will be a value that has an equivalence between the two sources, where this point in time is defined as the “crossing point.” At this supply voltage, the first current source is greater than the second current source, thereby causing a comparator output voltage VOUT to be or indicate HIGH, such as that as361. Subsequent to the crossing point the second current source is greater than the first current source, thereby a comparator output voltage VOUT to be or indicate LOW, such as that at371. In effect, the determination of the crossing point of the two currents corresponds to a desired power supply voltage value (i.e., VSUPPLY), such that the POR circuit provides a reset signal and also is able to function as a voltage supply monitor.

In a preferred embodiment, the first current is a quadratic current versus power supply voltage and the second current is an exponential current versus power supply voltage.

In a further preferred embodiment, the present invention is a method for generating a POR signal using power supply voltage monitoring comprising the steps of: providing power from a voltage power supply, generating a first current source from a first current generator in relation to a first mathematical formulation being a quadratic function of said voltage power supply, generating a second current source from a second current generator in relation to a second mathematical formulation being a function of said voltage power supply, ramping said voltage power supply, comparing said first current source with said second current source at a predetermined supply voltage, and generating a logical signal as an output POR signal in relation to said comparing step.

FIG. 4Adepicts a graphical representation of an exponential current410in accordance with an embodiment of the present invention.FIG. 4Bdepicts a graphical representation of a quadratic current420in accordance with an embodiment of the present invention.

FIG. 5depicts a graphical representation of a crossing point at530of a quadratic current520and an exponential current510in accordance with an embodiment of the present invention.

FIG. 6depicts a general comparison schematic of providing a POR signal at640by comparing at630a quadratic current source610and an exponential current source620in accordance with an embodiment of the present invention.

Another preferred embodiment of the present invention provides a circuit for providing a reliable power on reset (POR) signal (i.e., PORSIG) using a current architecture comparing a first primary current with a second current in relation to power supply voltage.FIG. 7depicts a schematic of a circuit700in accordance with an embodiment of the present invention.

InFIG. 7, a first current source710is generated by a pnp device (generally being a bipolar transistor having an n-type base between a p-type emitter and a p-type collector, wherein the emitter should be positive with respect to the base, and the collector should be negative with respect to the base)720and a current value is defined (i.e., set) by resistor730. The first current value is then copied via transistors740and750.

InFIG. 7, a second current source760is generated by nmos transistor770, wherein the mnos transistor operationally functions as a diode. An nmos transistor is an n-channel metal-oxide semiconductor (nmos) transistor is one in which n-type dopants are used in the gate region (the “channel”). Typically, and as used herein, a positive voltage on the gate of an nmos transistor turns the device on. Resistor780defines the current value for the second current source760. The second current value is then copied via transistors770and782.

InFIG. 7, the first current value is then compared with the second current value by a comparing means such as transistors750and782or a simple comparator means, where as a result of comparing the two current values, voltage at VOUTat790is either logically HIGH or LOW and is switched in accordance with the crossing point of the two currents (where the crossing point of the two currents corresponds to a desired power supply voltage).

For instance, during ramping from the power supply, where VSUPPis at795and circuit grounding is at799, both the first and the second current rise with respect to their mathematical courses. By example, a first current source having a quadratic characteristic will ramp over time in accordance with the current value being equal to that as a function of the square of the VSUPP(i.e., (VSUPP)2). Similarly, a second current source having an exponential characteristic will ramp over time in accordance with the current value being equal to that of exp(VSUPP).

In operation, both the first current source and the second current source will increase in value in relation to their mathematical formula. At one particular supply voltage, there will be a value that has an equivalence between the two sources, where this point in time is defined as the “crossing point.” Prior to the crossing point, the first current source is greater than the second current source, thereby causing a comparator output voltage VOUTat790to be or indicate HIGH. Subsequent to the crossing point the second current source is greater than the first current source, thereby a comparator output voltage VOUTat790to be or indicate LOW. In effect, the determination of the crossing point of the two currents corresponds to a desired power supply voltage value (i.e., VSUPPLY), such that the POR circuit provides a reset signal and also is able to function as a voltage supply monitor.

In a preferred embodiment, a POR circuit that provides a POR signal and is operable as a voltage supply monitor is provided. The circuit includes a voltage supply terminal receiving a voltage power supply, a first current generator providing a first current source in relation to a first mathematical formulation being a quadratic function of said voltage power supply, a second current generator providing a second current source in relation to a second mathematical formulation being a function of said voltage power supply, a current comparator for comparing said first current source with said second current source at a predetermined supply voltage, and a POR signal generator for generating a logical signal as output in relation to said current comparator.

In a preferred embodiment of the present invention the pnp device720is a vertical pnp device. In another preferred embodiment of the present invention means for comparing the two current values may include a logic means, comparator devices, software scripts, and other similar component or component devices capable of measuring and comparing voltage or current values.

In a further preferred embodiment, an inverter buffers the VOUTor POR signal logic.

In a further preferred embodiment of the present invention, a computing device having a POR circuit for providing a POR signal and operable as a voltage supply monitor is provided. The computing device includes: a voltage supply terminal receiving a voltage power supply, a first current generator providing a first current source in relation to a first mathematical formulation being a quadratic function of said voltage power supply, a second current generator providing a second current source in relation to a mathematical formulation of said voltage power supply, a current comparator for comparing said first current source with said second current source at a predetermined supply voltage, and for generating a logical signal as output, wherein, a crossing point is determined where said first current source crosses said second current source and said logical signal is generated in relation to a predetermined power supply voltage in relation to said crossing point.

An apparatus having a circuit capable of providing a reliable POR signal with in accordance with a current architecture relating characteristics of typical POR attributes that also permits voltage threshold monitoring is further disclosed. An apparatus may include any electronic device having an integrated chip, chipset, software means or the like, or any electronic device in which switching integrity in relation to voltage supply values and signals occurs.

Many other embodiments of the present invention are also envisioned. For example, in other embodiments, the present invention is directly applicable for integrated circuits, subsystem components and circuitry, power related devices, software process and programmable chip technology.

As used herein for the purposes of the present invention, the term “comparator” may also include amplification functionality, such as that of a differential amplifier, and may also be functionally deployed via a software means, firmware or program circuitry.

Any theory, mechanism of operation, proof, or finding stated herein is meant to further enhance understanding of the present invention and is not intended to make the present invention in any way dependent upon such theory, mechanism of operation, proof, or finding. It should be understood that while the use of the word preferable, preferably or preferred in the description above indicates that the feature so described may be more desirable, it nonetheless may not be necessary and embodiments lacking the same may be contemplated as within the scope of the invention, that scope being defined by the claims that follow.

In reading the claims it is intended that when words such as “a,” “an,” “at least one,” “at least a portion” are used there is no intention to limit the claim to only one item unless specifically stated to the contrary in the claim. Further, when the language “at least a portion” and/or “a portion” is used the item may include a portion and/or the entire item unless specifically stated to the contrary. While the invention has been illustrated and described in detail in the drawings and foregoing description, the same is to be considered as illustrative and not restrictive in character, it being understood that only the selected embodiments have been shown and described and that all changes, modifications and equivalents that come within the spirit of the invention as defined herein or by any of the following claims are desired to be protected.