Latch with redundancy and circuitry to protect against a soft error

An apparatus is described having a latch circuit. The latch circuit includes redundant data inputs, redundant data outputs, redundant clock inputs and circuitry to self-correct a soft-error.

FIELD OF INVENTION

The field of invention pertains generally to electronic circuitry and, more specifically, to a latch with redundancy and circuitry to protect against a soft error.

BACKGROUND

In the field of electronic circuitry, soft errors are becoming an increasingly problematic issue. Here, with device sizes shrinking and with corresponding reductions in supply voltages and/or logic voltage margins, the probability that a soft error will arise is steadily increasing. Increasing soft errors threaten the viability of a circuit's implementation since important data calculations may be made with the circuit and any error in the circuit's resultant data values are ultimately unacceptable.

DETAILED DESCRIPTION

FIG. 1shows a latch circuit100that employs redundancy along the data path in order to provide built-in protection against a soft-error, such as a particle hit or other corrupting event (e.g., an “inadvertent glitch”), should one occur along either one of the data paths. As observed inFIG. 1the circuit includes a pair of data lines d1and d2which, in the particular embodiment ofFIG. 1, are not logical complements of one another (they carry the same logical signal). Redundant clock signals CLK1and CLK2are also provided to the latch circuit. In an embodiment, both clock lines carry the same clock signal. As such, the latch circuit is also protected against a soft error on either clock line. That is, should a soft error “glitch” occur on one of the data lines or one of the clock lines, the other redundant data line or clock line is sufficient for the latch to hold the correct data.

Inset130ofFIG. 1shows an embodiment of the signaling when a logical “0” is to be latched into the circuit. According to nominal operation, the new data is initially entered into the latch circuit when both clock signals CLK1, CLK2are a logic high. Here, at time131, both clock signals CLK1, CLK2are a logical high and both data inputs d1, d2are a logical low. Inverters101,102invert the received low d1, d2input signals and present logic high signals to switches103,104. Because both clock signals CLK1, CLK2are a logic high in time131, both of switches103,104are in pass mode and a pair of logic high signals are passed to internal nodes105,106respectively.

With both of internal nodes105,106at a logic high level, PMOS transistor Q1will be “off” and NMOS transistor Q2will be “on” which sets output O1to a logical low (Q2pulls O1to ground). Similarly, PMOS transistor Q3will be “off” and NMOS transistor Q4will be “on” setting output O2to a logical low. Thus, the new data appears at the circuit outputs O1, O2during the initial logic high phase of clocks CLK1, CLK2during time131.

Note also that the circuitry120that resides “above” transistors Q1through Q4inFIG. 1is “off” in that no current flows through any of the four current path legs observed therein (a first current leg runs through transistors Q14, Q5, Q6, Q15; a second current leg runs through transistors Q11and Q10; a third current leg runs through transistors Q13, Q7, Q8, Q16; a fourth current leg runs through transistors Q12and Q9). Here, with clk1and clk2being high (and /clk1and /clk2being low), transistors Q5through Q8are “off”. Additionally, with nodes105and106being high, transistors Q11and Q12are “off”. As will be made more clear in the following discussion, transistors Q5through Q8and transistors Q11through Q16form redundant feedback to internal state nodes105and106.

At time132, both clocks CLK1, CLK2transition to a logic low which turns switches103,104“off” but also turns transistors Q5through Q8“on”. The logical high level on internal nodes105,106turns NMOS transistors Q9and Q10“on” and turns PMOS transistors Q11and Q12“off”. With NMOS transistors Q9and Q10being “on”, internal nodes107,108are pulled to a logic low which places PMOS transistors Q13and Q14in an “on” state and places NMOS transistors Q15and Q16in an “off” state. Thus, no current is substantially flowing through any of the four current path legs because at least one transistor in each leg is in the “off” state.

From this circuit state, if a soft error is to occur on one of internal nodes105,106the circuit acts to protect the original, correct data at outputs O1and O2. For instance, if internal node106were to transition to a logical low level either from a direct particle hit or through an inadvertent glitch on the CLK1signal that causes a logical low level to pass through switch103, transistor Q1will transition to an “on” state and transistor Q4will transition to an “off” state.

As such, transistors Q1and Q2will be “on” and transistors Q3and Q4will be “off”. With respect to the turning on of transistor Q1, output node O1will not instantaneously rise from a logical low to a logic high. Here, because internal node105did not suffer a soft error and remains at a logic high level, transistor Q2remains “on” keeping output O1, at least initially, to a logic low. The turning on of transistor Q1might, however, tend to pull output O1up to a higher voltage level over time if not otherwise corrected for (a temporary short-circuit current is also created between transistors Q1and Q2). The corrective action of the latch circuit, as described in more detail further below, substantially eliminates a rise in voltage level at output O1from occurring.

Similarly, the turning off of NMOS transistor Q4causes output node O2to technically “float” as both transistors Q3and Q4are “off”. However, the absence of any immediate current path from output node O2causes output node O2to substantially hold its logic low voltage level until the corrective action of the latch circuit causes output O2to more definitely hold its logic low state.

With internal node106being set low due to the soft error, NMOS transistor Q9will turn “off” and PMOS transistor Q11will turn “on”. The turning “on” of PMOS transistor Q11will cause a substantial current to flow through its current leg. The corresponding current drive through transistor Q10keeps node107low.

Additionally, with transistor Q9now being “off” and transistors Q12and Q16originally being off, internal node108has no active current path and holds its original low voltage. As such PMOS transistor Q14remains “on”. With CLK1being low, transistors Q5and Q6are also “on”. With transistor Q15being “off” and transistors Q14and Q5being “on”, the active mode Q14and Q5transistors, which form a leg tied to the supply voltage, will have the effect of pulling internal node106up to a logic high voltage level thereby counteracting the soft error.

Here, to the extent the soft error might momentarily turn transistor Q1“on”, the cause of the soft error, which is transitory, has to “fight” against the pull-up activity of “on” transistors Q14and Q5. With transistors Q14and Q5being fixed in the “on” state, the temporary soft error essentially fails to permanently set node106to a voltage low. The reactant rise of the voltage on internal node106keeps transistor Q1“off” and keeps transistor Q4“on” which causes outputs O1and O2to keep their original logic low state.

Analogous operation for the case where node105suffers a soft error that causes the voltage on node105to drop to a logic low. Here, transistors Q7, Q8and Q13will be “on” and transistor Q16will be “off” which will cause node105to be pulled back up to a logic high to counteract the soft error.

In the case where a logical “1” is latched into the circuit and a soft error causes either of internal nodes105,106to rise from their proper logic low level to a high level voltage. In this case, the circuit will counteract the soft error to pull the node that suffered the error back to a low level thereby keeping a logical high at outputs O1and O2. For example, if node106suffers a soft error that raises its voltage level to a logic high, transistors Q6and Q15will be “on” and Q14will be “off” which will have the effect of pulling node106back to ground.

Additionally, the circuit will automatically counter-balance a direct internal strike to either of nodes107and108. For example, consider a steady state where nodes107and108are low and node108receives a strike that raises node108high. In the steady state where node108is low, transistor Q12is off and transistor Q9is on. Because the state of these two transistors are not impacted by the strike, node108will be immediately pulled low again.

As described above, the circuitry naturally balances itself to keep nodes105,106to a same value and nodes107,108to a same value. This same property also protects the circuit against external errors to one of the clock lines. For instance, if a glitch occurs on one of the clock lines within time period131well before the transition between times131and132, correct data will eventually be latched in and the circuit itself will naturally drive itself to the holding the correct data. Contra-wise, if a clock glitch occurs approximately at the transition between times131and132, correct data will have already been already latched into the circuit by the time of the glitch and the circuit will naturally hold onto the correct data. Finally if a clock glitch occurs in time132and a new data value is inadvertently passed through one of the switches103/104, the circuit will naturally suppress the error and drive itself to the correct internal state that existed before the glitch.

Note also that the ability of the circuit to keep correct data is enhanced by the existence of redundant clock lines. For instance, if a glitch occurs to the clk1signal during time131, transistors Q5and Q6will be inadvertently turned off. However, nodes105through108will keep their state with the assistance of transistors Q7and Q8remaining on and being driven by the other, non glitched clock clk2.

FIG. 2ashows a higher level depiction200of the latch circuit ofFIG. 1. As with the latch circuit100ofFIG. 1, the latch circuit200ofFIG. 2ahas redundant data inputs d1, d2, redundant clock inputs clk1, clk2and redundant data outputs O1, O2. Also as discussed above with respect toFIG. 1, the latch circuit200ofFIG. 2aideally latches same data presented on both of the d1and d2data inputs according to a particular logic level on both of clock inputs clk1, clk2. If the latch circuit suffers a soft error internally, or if “bad data” is inadvertently latched into the circuit because of a glitch on one of the clock inputs or one of the data inputs, the latch circuit200automatically counteracts the error and keeps correct data at outputs O1and O2.

FIG. 2bshows a master-slave flip-flop210constructed from a pair of the latch circuits200_1,200_2ofFIG. 2a. The first latch200_1may be referred to as the master latch and the second latch200_2may be referred to as the slave latch. Consistent with the traditional operation of a master-slave flip-flop, data can be made to appear at the slave outputs211,212upon a clock edge rather than a clock logic low or logic high level. However, unlike a traditional master-slave flip-flop, the master-slave flip-flop210ofFIG. 2buses redundant data paths and redundant clock signals to internally reject soft errors.

In an embodiment where both latch circuits200_1,200_2are implemented with the design100ofFIG. 1, when the master clock signals (clkm1, clkm2) are a logic low, the front end inverters213,214invert the clock signals to present a logic high at both of the clk1, clk2inputs of latch200_1thereby latching the data on the data inputs d1, d2into the master latch circuit200_1. The values of d1, d2should immediately appear at the O1, O2outputs of the first latch200_1after a propagation delay through the first latch200_1.

When the logic level of the slave clocks (clks1, clks2) rises to a logic high, the data values that are presented at the O1, O2outputs of the first latch200_1will be latched into the second latch200_2and will appear at the flip-flop outputs211,212after a propagation delay through the second latch200_2. If the master and slave clocks are tied together to form a redundant same clock signal (e.g., clkm1is tied to clks1and clkm2is tied to clks2), data in the master is latched when the clock transitions from low to high and the slave202_2becomes transparent (O1and O2of the master200_1flow through to outputs211and212).

FIG. 2cshows a higher level depiction220of the master slave flip-flop ofFIG. 2bconfigured in a finite state machine arrangement230. A finite state machine includes a state holding element220having a feedback path through combinatorial logic221between the state holding element's output and its input. General inputs to the finite state machine, e.g., In_1, In_2, can be provided directly to the combinatorial logic221as well. Here, the master slave flip-flop ofFIG. 2bcorresponds to the state holding element220and combinatorial logic221of the state machine230.

A next input to the state holding element220is a function of the generic inputs In_1, In_2and/or the current state of the state holding element220as submitted to the combinatorial logic221. Here, for instance, if the master and slave clocks are tied together, input values received at the d1, d2inputs of the flip-flop220from the combinatorial logic221can be entered into the device, e.g., when the clock signal is low and will appear at the flip-flop's outputs O1, O2in response to the clock rising to a logic high. The state machine ofFIG. 2cis believed to be unique as a consequence of its redundant clock, internal data and output values and its natural immunity to soft errors.

As is known in the art, state machines are used to implement various different kinds of circuits such as counters, adders, multipliers, custom functions, etc.FIG. 3shows a three bit counter circuit300constructed from three finite state machine circuits that each conform to the general state machine depiction ofFIG. 2c.

Here, each of the flip-flop circuits320_1,320_2,320_3ofFIG. 3are observed to have a feedback path stemming from its output to its input through combinatorial logic and therefore conforms to the state machine model ofFIG. 2c. For instance, the O1output of flip-flop320_1is coupled to the d1input of flip-flop320_1through NOR gate301and the O2output of flip-flop320_1is coupled to the d2input of flip-flop320_1through NOR gate302. The other flip-flops320_2,320_3are similarly configured. As such, the three bit counter ofFIG. 3is implemented with three separate state machine circuits, where each state machine circuit includes one of the flip-flops as its state holding element and the NOR gates between its O1, O2outputs and its d1, d2inputs correspond to its combinatorial logic.

A counter circuit presents a count value across its state holding elements. As such, with the three flip-flops320_1,320_2,320_3ofFIG. 3corresponding to the state holding elements of the counter, the count value of the counter is recognized as (c,b,a) where “c” is the most significant bit provided from flip-flop320_3and “a” is the least significant bit provided from flip-flop320_1. Ideally, the counter increments with each next clock cycle.

After a logic high reset signal is applied to the circuit as the reset input303, a value of 0 will be presented at the d1and d2inputs of all three flip-flops, a value of 0 will be presented at the clkm1and clkm2inputs of all three flip-flops and a value of 1 will be presented at the clks1and clks2inputs of all three flip flops. As such, a (c,b,a) value of 000 will be latched into the counter300. After the reset value is dropped to a logic low, the counter will begin counting on a next clock cycle.

Here, with an initial (c,b,a) value of 000, a value of 1 will be present at both d1and d2inputs of all three first flip-flops. As will become more apparent in the immediately following discussion, each time a flip-flop transitions to an output value of 0, its immediately downstream flip-flop will transition to an output value of 1 (flip-flop320_2is downstream from flip-flop320_1and flip-flop320_3is downstream from flip-flop320_2).

Upon the first clock cycle following the release of the reset, when the input clock signal clk is low, a value 0 will be present at the clkm1and clkm2inputs of the first flip flop320_1and a value of 1 will be present at the clks1and clks2inputs of the first flip flop320_1. As such, the first flop320_1will transition from an output value of 0 to an output value of 1 at both its O1and O2outputs and the (c,b,a) output value of the counter will transition from an output of 000 to an output of 001. Also, with the transition of the output value of the first flop-flop320_1to a value of 1 at its O1and O2outputs, the clkm1and clkm2inputs to the second flip-flop320_2will fall to a logic low which latches a value of 1 into the second flip-flop320_2. However, the output value of the second flip-flop320_1will not transition because its clks1and clks2inputs are set to a value of 0 with the first-flop's O1, O2output values being set to a 1.

Upon the second clock cycle, when the input clock signal clk is low, a value 0 will be present at the clkm1and clkm2inputs of the first flip flop320_1and a value of 1 will be present at the clks1and clks2inputs of the first flip flop320_1. The value of the d1and d2inputs of the first flop-flops320_1are at 0 owing to the output value of 1 at the O1, O2outputs of the first flip-flop320_1. As such, the first flop320_1will transition from an output value of 1 to an output value of 0 at its O1and O2outputs. This transition will also cause the clks1and clks2clock inputs of the second flip-flop320_2to rise to a logic high which will cause the previously internally latched value of 1 within the second flip-flop320_2to be presented at the O1and O2outputs of the second flip-flop320_2. As such, the (c,b,a) output value of the counter will have transitioned to an output value of 010.

Upon the third clock cycle, the O1and O2output values of the first flip-flop320_1will transition to a value of 1 owing to the same process described above when the circuit first came out of reset. A value of 0 will be latched internally at both the d1and d2inputs of the second flip-flop320_2but the value will not be presented at the second flip-flop320_2output because the clks1and clks2inputs of the second flip-flop320_2will be set at a value of 0. As such, the (c,b,a) output value of the counter will correspond to a count value of 011.

Upon the fourth clock cycle, the O1and O2output values of the first flip-flop320_1will transition to a value of 0 according to the process described above for the second clock cycle. In response to the transition, the O1and O2output values of the second flip-flop320_2will also transition to a value of 0. Additionally, the O1and O2output values of the third flip-flop320_3circuit will transition to a value of 1. As such, the (c,b,a) output value of the counter will correspond to a value of 100. The O1and O2output values of the third flip-flop320_3will not transition back to a 0 until the next sequence at which the O1and O2output values of both the first and second flip-flops320_1,320_2are set to a value of 1.

With the flip-flops being designed to internally suppress a soft error, if a soft error occurs within any of the flip-flops, the error will not present itself at the (c,b,a) output of the counter thereby preventing corruption of the count value. Also, owing to the soft error suppression capability of the latch circuits within the flip-flops, it is pertinent to recognize that if a soft error occurs on any of the data lines that feed a flip-flop, the flip-flop will not respond if one data input (e.g., d1) is a first logic value (e.g., a 0) and the other data input (e.g., d2) is a second logic value (e.g., a 1). Here, the analysis will be akin to the discussion ofFIG. 1in which it was shown that if one of nodes105or106flips the circuit will return to its original state where both of nodes105and106were equal.

FIG. 4shows a depiction of an exemplary computing system400such as a personal computing system (e.g., desktop or laptop) or a mobile or handheld computing system such as a tablet device or smartphone.

As observed inFIG. 4, the basic computing system may include a central processing unit401(which may include, e.g., a plurality of general purpose processing cores and a main memory controller disposed on an applications processor or multi-core processor), system memory402, a display403(e.g., touchscreen, flat-panel), a local wired point-to-point link (e.g., USB) interface404, various network I/O functions405(such as an Ethernet interface and/or cellular modem subsystem), a wireless local area network (e.g., WiFi) interface406, a wireless point-to-point link (e.g., Bluetooth) interface407and a Global Positioning System interface408, various sensors409_1through409_N (e.g., one or more of a gyroscope, an accelerometer, a magnetometer, a temperature sensor, a pressure sensor, a humidity sensor, etc.), a camera410, a battery411, a power management control unit412, a speaker and microphone413and an audio coder/decoder414.

An applications processor or multi-core processor450may include one or more general purpose processing cores415within its CPU401, one or more graphical processing units416, a memory management function417(e.g., a memory controller) and an I/O control function418. The general purpose processing cores415typically execute the operating system and application software of the computing system. The graphics processing units416typically execute graphics intensive functions to, e.g., generate graphics information that is presented on the display403. The memory control function417interfaces with the system memory402. The power management control unit412generally controls the power consumption of the system400. The system memory402may be a multi-level system memory having, e.g., a faster higher level and a slower lower level.

Each of the touchscreen display403, the communication interfaces404-407, the GPS interface408, the sensors409, the camera410, and the speaker/microphone codec413,414all can be viewed as various forms of I/O (input and/or output) relative to the overall computing system including, where appropriate, an integrated peripheral device as well (e.g., the camera410). Depending on implementation, various ones of these I/O components may be integrated on the applications processor/multi-core processor450or may be located off the die or outside the package of the applications processor/multi-core processor450.

Any of the circuitry of the computing system may make use of a latch circuit and any associated state machine circuitry that uses a latch structure having internal suppression of soft errors.

Embodiments of the invention may include various processes as set forth above. The processes may be embodied in machine-executable instructions. The instructions can be used to cause a general-purpose or special-purpose processor to perform certain processes. Alternatively, these processes may be performed by specific hardware components that contain hardwired logic for performing the processes, or by any combination of programmed computer components and custom hardware components.