TECHNOLOGIES FOR LOW-LEAKAGE ON-CHIP CAPACITORS

Technologies for low-leakage and low series resistance on-chip capacitors are disclosed. In the illustrative embodiment, each electrode of a capacitor is formed from two metal layers and vias between the metal layers. A high-k dielectric layer is between the metal layers. The electrodes are displaced relative to each other on the plane defined by the high-k dielectric layer. As a result, electric field lines of the capacitor are parallel to the high-k dielectric layer. The electrodes can be displaced from each other by more than the thickness of the high-k dielectric layer, reducing the leakage current through the high-k dielectric layer as compared to a capacitor with field lines perpendicular to the high-k dielectric layer. Such a capacitor may be used to provide power to circuits in a low-power state with little leakage current and/or may be used to absorb radiofrequency (RF) interference.

BACKGROUND

Capacitors formed or connected to semiconductor dies can perform several functions. An on-chip metal-insulator-metal (MIM) capacitor can be used to provide a stable voltage when components change a current draw in a short amount of time. A MIM capacitor may be used to provide a stable voltage source for components in a low-power state, such as a connected standby case. However, a large MIM capacitor may have a relatively large leakage current, dissipating a relatively large amount of power compared to the power needed for the low-power state.

In some cases, a capacitor with a low series resistance may be used to absorb radiofrequency signals. However, MIM capacitors may have too high of a series resistance, and the circuit path to off-chip capacitors may also have a relatively high series resistance.

DETAILED DESCRIPTION

In various embodiments disclosed herein, a capacitor on a die may be formed by electrodes on one or more metal layers and a dielectric layer. Each electrode of the capacitor is formed by part of an upper metal layer, part of a lower metal layer, and one or more vias between the metal layers. The electrodes displaced from each other in a direction parallel to the metal layers. A high-k dielectric is between the metal layers. In use, electric field lines extend from one electrode to the other through the high-k dielectric in a direction parallel to the metal layers. As the gap between the electrodes can be relatively large, such a capacitor has lower leakage current. Additionally, such a capacitor can have a shorter current path, reducing both the series resistance and the series inductance. In some embodiments, a capacitor designed in that manner can be used to absorb radiofrequency (RF) interference. A standard metal-insulator-metal on-die capacitor may have too high of a series resistance to absorb RF interference.

As used herein, the phrase “communicatively coupled” refers to the ability of a component to send a signal to or receive a signal from another component. The signal can be any type of signal, such as an input signal, an output signal, or a power signal. A component can send or receive a signal to another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., conductive traces, conductive contacts, air). Examples of components that are communicatively coupled include integrated circuit dies located in the same package that communicate via an embedded bridge in a package substrate and an integrated circuit component attached to a printed circuit board that send signals to or receives signals from other integrated circuit components or electronic devices attached to the printed circuit board.

In the following description, specific details are set forth, but embodiments of the technologies described herein may be practiced without these specific details. Well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring an understanding of this description. Phrases such as “an embodiment,” “various embodiments,” “some embodiments,” and the like may include features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics.

Some embodiments may have some, all, or none of the features described for other embodiments. “First,” “second,” “third,” and the like describe a common object and indicate different instances of like objects being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally or spatially, in ranking, or any other manner. “Connected” may indicate elements are in direct physical or electrical contact, and “coupled” may indicate elements co-operate or interact, but they may or may not be in direct physical or electrical contact. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. Terms modified by the word “substantially” include arrangements, orientations, spacings, or positions that vary slightly from the meaning of the unmodified term. For example, the central axis of a magnetic plug that is substantially coaxially aligned with a through hole may be misaligned from a central axis of the through hole by several degrees. In another example, a substrate assembly feature, such as a through width, that is described as having substantially a listed dimension can vary within a few percent of the listed dimension.

It will be understood that in the examples shown and described further below, the figures may not be drawn to scale and may not include all possible layers and/or circuit components. In addition, it will be understood that although certain figures illustrate transistor designs with source/drain regions, electrodes, etc. having orthogonal (e.g., perpendicular) boundaries, embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within +/−5 or 10 degrees of orthogonality) due to fabrication methods used to create such devices or for other reasons.

Reference is now made to the drawings, which are not necessarily drawn to scale, wherein similar or same numbers may be used to designate the same or similar parts in different figures. The use of similar or same numbers in different figures does not mean all figures including similar or same numbers constitute a single or same embodiment. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding thereof. It may be evident, however, that the novel embodiments can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate a description thereof. The intention is to cover all modifications, equivalents, and alternatives within the scope of the claims.

As used herein, the phrase “located on” in the context of a first layer or component located on a second layer or component refers to the first layer or component being directly physically attached to the second part or component (no layers or components between the first and second layers or components) or physically attached to the second layer or component with one or more intervening layers or components.

As used herein, the term “adjacent” refers to layers or components that are in physical contact with each other. That is, there is no layer or component between the stated adjacent layers or components. For example, a layer X that is adjacent to a layer Y refers to a layer that is in physical contact with layer Y.

Referring now toFIG.1, in one embodiment, a system100includes a base die102that supports other dies, such as a compute die104and a system-on-a-chip (SoC)106. In the illustrative embodiment, the compute die104and/or the SoC106may draw power from a high-capacitor metal-insulator-metal (MIM) capacitor108with field lines perpendicular to a surface of the die102, as discussed in more detail below in regard toFIGS.2and3. The MIM capacitor108may have a relatively high capacitance and can help provide a stable voltage to the compute die104and the SoC106. The compute die104and/or SoC106may have low-power states, in which they draw a relatively small amount of current. The MIM capacitor108may be able to support the low current state, but with a relatively large leakage current.

In order to support the compute die104and/or the SoC106in low current states, the base die102includes an additional capacitor110with field lines parallel to the surface of the base die102, as discussed in more detail below in regard toFIGS.4and5. The capacitor110may have a relatively low capacitance compared to the capacitor108, but with a relative leakage current that is even lower.

In the illustrative embodiment, the base die102supports additional dies104,106and provides power to the dies104,106through the capacitors108,110. The base die102may be made of any suitable material, such as silicon, other semiconductors, or polymers. In addition to the capacitors108,110described below, the base die102may include additional structure, such as interconnects, compute blocks, memory blocks, etc. It should be appreciated that the configuration shown inFIG.1is merely one possible embodiment and that other configurations are possible. For example, capacitors108and/or110may be on a stand-alone die, may be on the compute die104, may be on the SoC106, etc. In general, the capacitors108and/or110may be integrated into any suitable die.

Referring now toFIG.2, in one embodiment, the capacitor108with field lines perpendicular to the surface of the base die102is shown.FIG.3shows a cross-sectional view of the capacitor108. The capacitor108includes a first electrode200and a second electrode201. The first electrode200includes a large part of a first metal layer202, and the second electrode201includes a large part of a second metal layer206. A high-k dielectric layer204is between the first metal layer202and the second metal layer206. The first electrode200also includes one or more vias208, a pad212that forms part of the second metal layer206, and one or more pads or traces210,302on additional layers below the first metal layer202and/or above the second metal layer206. Similarly, the second electrode201includes one or more vias216, a pad304that forms part of the first metal layer206, and one or more pads or traces218,208on additional layers below the first metal layer202and/or above the second metal layer206. Insulating area214isolates the pad212and the first electrode200from the second electrode201on the second metal layer206. Similarly, insulating area306isolates the pad304and the second electrode201from the first electrode200on the first metal layer202.

In use, the first electrode200is charged to a different voltage than the second electrode201. Field lines extend perpendicularly through the high-k dielectric layer204. The capacitor108can have a relatively high capacitance, such as about 200 nF/mm2. However, the electrical series resistance is relatively high, such as about 400×10−6Ω×mm2, and the leakage current is high as well.

The first electrode200may be at, e.g., 0 volts, and the second electrode201may be at, 1 volt. In general, in use, the first electrode200and the second electrode201may have any suitable voltage level between them, such as 0.5-1.5 volts. In some embodiments, the first electrode200may be at the lower voltage, and, on other embodiments, the second electrode201may be at the lower voltage.

In the illustrative embodiment, the first metal layer202, the second metal layer206, and the vias208,216are made of copper. In other embodiments, the first metal layer202, the second metal layer206, and/or the vias208,216may be made of a different material, such as aluminum, polysilicon, and/or the like. In the illustrative embodiment, the first metal layer202may be supported by a silicon substrate, a silicon oxide layer, or any other suitable substrate or layer. Similarly, a silicon oxide or other suitable layer may be above the second metal layer206. The capacitor108may include additional layers or connections not shown inFIGS.2and3.

The high-k dielectric layer204may be any suitable material. As used herein, a high-k dielectric refers to a material with a relative permittivity of greater than 100, unless explicitly stated otherwise. In the illustrative embodiment, the high-k dielectric layer204has a relative permittivity of over 1,000. The high-k dielectric layer204may be made of or otherwise include barium titanate, lead zirconate titanate, conjugated polymers, calcium copper titanate, etc. The high-k dielectric layer204may have any suitable thickness, such as 0.02-1 micrometers. In the illustrative embodiment, the high-k dielectric layer204has a thickness of about 0.1 micrometers.

Referring now toFIG.4, in one embodiment, the capacitor110with field lines parallel to the surface of the base die102is shown.FIG.5shows a cross-sectional view of the capacitor110taken along line5, perpendicular to a high-k dielectric layer404.FIG.6shows a cross-sectional view of the capacitor110taken along line6, parallel to the high-k dielectric layer404.

The capacitor110includes a first electrode400and a second electrode401. The first electrode400includes a part of a first metal layer402and a second metal layer406. The second electrode also includes part of the first metal layer402and the second metal layer406, with the portions of the second electrode401displaced relative to the first electrode400. A high-k dielectric layer404is between the first metal layer402and the second metal layer406. The first electrode400also includes one or more vias408and one or more pads or traces410,502on additional layers below the first metal layer402and/or above the second metal layer406. Similarly, the second electrode401includes one or more vias412and one or more pads or traces414,504on additional layers below the first metal layer402and/or above the second metal layer406. Between the first electrode400and the second electrode401, the metal layers406,402is removed and replaced with an insulator, such as silicon dioxide.

In use, the first electrode400is charged to a different voltage than the second electrode401. Field lines506extend parallel through the high-k dielectric layer404, as shown inFIG.5. The field lines506may begin and end at the vias408,412, as well as the overhang of the metal layers402,406. The capacitor110can have a relatively lower capacitance compared to the capacitor108, such as about 14 nF/mm2. However, the electrical series resistance is relatively low compared to the capacitor108, such as about 9.6×10−6Ω×mm2, and the leakage current is low as well.

In one embodiment, a distance508between vias408,412may be on the order of a micrometer. A thickness510of the high-k dielectric layer404may be on the order of 0.1 micrometers. A width512of each via408,412may be on the order of a micrometer. A distance514between each via408,412and the edge of the electrode400,401may be on the order of a micrometer. A distance516between the vias408,412may be on the order of a micrometer. In one embodiment with the dimensions as described above, the electrodes400,401with one pair of vias408,412form a capacitor with a capacitance of 20×10−6 nF, a series resistance of 22 mΩ, and a leakage resistance of 6.25Ω. It should be appreciated that other dimensions may be used, such as embodiments in which some, any, or all dimensions508-516may be an order of magnitude smaller or larger.

The first electrode400may be at, e.g., 0 volts, and the second electrode401may be at, e.g., 1 volt. In general, in use, the first electrode400and the second electrode401may have any suitable voltage level between them, such as 0.5-5 volts. It should be appreciated that, as the electrodes400,401are farther apart than electrodes200,201, the voltage across electrodes400,401can be greater than that across200,201. In some embodiments, the first electrode400may be at the lower voltage, and, in other embodiments, the second electrode401may be at the lower voltage.

In some embodiments, metal layer402may be the same layer as metal layer202, high-k dielectric layer404may be the same as high-k dielectric layer204, and metal layer406may be the same layer as metal layer406. As such, in some embodiments, capacitors108,110may be formed contemporaneously on the same die, as discussed below in regard toFIG.15.

In the illustrative embodiment, the structure of the capacitor110offers several advantages. The series resistance, series inductance, and leakage current for the capacitor110are less than for a capacitor108with an equivalent capacitance, although the capacitor110has a lower capacitance as a capacitor108with the same area. The capacitor110can be formed from the same metal layers and high-k dielectric layer as the capacitor108, allowing a die to have both a capacitor110and a capacitor108. The capacitor110may take up a relatively small area of the high-k dielectric layer, with the capacitor108taking up the majority of the area of the high-k dielectric layer.

The capacitor110has the electrodes400,401displaced from each along the plane of the high-k dielectric layer404. As a result, vias passing through the high-k dielectric layer404connected to one electrode400,401do not result in a void in the other electrode401,400. Rather, additional vias408,412can increase the capacitance of the capacitor110. In use, current does not need to flow through large lengths of metal layers202,206, as for the capacitor108, reducing the series parasitic resistance and inductance of the capacitor110. The lower series parasitic resistance and inductance result in a higher corner (or cutoff) frequency for such a capacitor110.

In some embodiments, radiofrequency (RF) interference may be present on voltage support devices of the system100. In order for the RF interference to be absorbed, capacitors with low capacitance and low series parasitic resistance must be used. The capacitor108may not perform well for such a function, but one or more capacitors110can perform such a function. In some embodiments, the system100may include one or more on-die capacitors110to filter out each of several frequencies. For example, the system100may include one or more capacitors110with a capacitance of, e.g., 2.2-560 pF to filter out signals at, e.g., 1.9 GHz, 2.1 GHz, 2.4 GHz, 5.0 GHz, and/or 6.0 GHz. The use of on-die capacitors110to filter out RF interference can save on-board RFI shield cost as well as eliminate off-die capacitors to filter out RF interference.

Referring now toFIGS.7-12, in some embodiments, electrodes400,401may be formed from an array of vias408,412, with unit cells being repeated several times to create a capacitor110with increased capacitance. A pad similar to the pads212,304shown inFIGS.2and3may provide a connection for a via408,412to the metal layers402,406, as appropriate. Unit cells may have vias408,412in any suitable arrangement. For example,FIG.7shows a unit cell700with vias408,412adjacent vias408,412of the same electrode400,401.FIG.8shows a unit cell800with vias408,412opposite vias408,412of the same electrode400,401.FIG.9shows a unit cell900with via412of one electrode401surrounded by vias408of the other electrode400.FIG.10shows a unit cell1000with vias408alternating with vias412.FIG.11shows a unit cell1100with a hexagon shape and vias408,412as shown.FIG.12shows a unit cell12with vias408,412both adjacent and opposite vias408,412of the other electrode400,401.

Referring now toFIG.13, in one embodiment, a capacitor108may be formed using deep trench technology, creating trenches1302that form part of electrode201and trenches1304that form part of electrode200. In the illustrative embodiment, the trenches1302,1304can increase the capacitance of the capacitor108.

Referring now toFIG.14, in one embodiment a capacitor110may be created with deep trench technology, creating trenches1402that form part of electrode400. Unlike for the capacitor108, the capacitance of the capacitor110does not significantly change due to the use of deep trench. However, the capacitor110still operates, allowing deep trench technology to be used on the capacitor108on the same layers as the capacitor110.

Referring now toFIG.15, a flowchart for a method1500creating on-die capacitors is shown. The method1500may be executed by a technician and/or by one or more automated machines. In some embodiments, one or more machines may be programmed to do some or all of the steps of the method1500. Such a machine may include, e.g., a memory, a processor, data storage, etc. The memory and/or data storage may store instructions that, when executed by the machine, causes the machine to perform some or all of the steps of the method1500.

The method1500begins in block1502, a first metal layer is patterned for electrodes of capacitors108and/or110. The metal layer may be made out of copper and may be adjacent a layer of, e.g., silicon dioxide or other insulator. In block1504, part of the metal layer is patterned to form a first electrode of a capacitor108with an electric field perpendicular to the metal layer. In block1506, part of the metal layer is patterned to form a bottom part of two electrodes for a capacitor110with an electric field parallel to the metal layer. In block1508, in some embodiments, pads for vias may be patterned. For example, a via of one electrode may pass through a via of another electrode. In such an embodiment, an area around a pad for a via may be removed and an insulating layer may be added, such as silicon dioxide.

In block1510, a high-k dielectric layer is applied over the first metal layer. In block1512, vias may be formed through the high-k dielectric for one or both electrodes.

In block1514, a second metal layer is patterned for electrodes of capacitors108and/or110. The metal layer may be made out of copper. In block1516, part of the metal layer is patterned to form a second electrode of a capacitor108with an electric field perpendicular to the metal layer. In block1518, part of the metal layer is patterned to form a top part of two electrodes for a capacitor110with an electric field parallel to the metal layer. In block1520, in some embodiments, pads for vias may be patterned. For example, a via of one electrode may pass through a via of another electrode. In such an embodiment, an area around a pad for a via may be removed and an insulating layer may be added, such as silicon dioxide.

It should be appreciated that, in some embodiments, additional layers may be added before and/or after those shown inFIG.15, such as interconnect layers, compute layers, etc.

FIG.16is a top view of a wafer1600and dies1602that may include any of the capacitors108,110disclosed herein. The wafer1600may be composed of semiconductor material and may include one or more dies1602having integrated circuit structures formed on a surface of the wafer1600. The individual dies1602may be a repeating unit of an integrated circuit product that includes any suitable integrated circuit. After the fabrication of the semiconductor product is complete, the wafer1600may undergo a singulation process in which the dies1602are separated from one another to provide discrete “chips” of the integrated circuit product. The die1602may include one or more transistors (e.g., some of the transistors1740ofFIG.17, discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and/or any other integrated circuit components. In some embodiments, the wafer1600or the die1602may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die1602. For example, a memory array formed by multiple memory devices may be formed on a same die1602as a processor unit (e.g., the processor unit2002ofFIG.20) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. Various ones of the microelectronic assemblies disclosed herein may be manufactured using a die-to-wafer assembly technique in which some dies are attached to a wafer1600that include others of the dies, and the wafer1600is subsequently singulated.

FIG.17is a cross-sectional side view of an integrated circuit device1700that may include any of the capacitors108,110disclosed herein. One or more of the integrated circuit devices1700may be included in one or more dies1602(FIG.16). The integrated circuit device1700may be formed on a die substrate1702(e.g., the wafer1600ofFIG.16) and may be included in a die (e.g., the die1602ofFIG.16). The die substrate1702may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The die substrate1702may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate1702may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the die substrate1702. Although a few examples of materials from which the die substrate1702may be formed are described here, any material that may serve as a foundation for an integrated circuit device1700may be used. The die substrate1702may be part of a singulated die (e.g., the dies1602ofFIG.16) or a wafer (e.g., the wafer1600ofFIG.16).

The integrated circuit device1700may include one or more device layers1704disposed on the die substrate1702. The device layer1704may include features of one or more transistors1740(e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate1702. The transistors1740may include, for example, one or more source and/or drain (S/D) regions1720, a gate1722to control current flow between the S/D regions1720, and one or more S/D contacts1724to route electrical signals to/from the S/D regions1720. The transistors1740may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors1740are not limited to the type and configuration depicted inFIG.17and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon, nanosheet, or nanowire transistors.

FIGS.18A-18Dare simplified perspective views of example planar, FinFET, gate-all-around, and stacked gate-all-around transistors. The transistors illustrated inFIGS.18A-18Dare formed on a substrate1816having a surface1808. Isolation regions1814separate the source and drain regions of the transistors from other transistors and from a bulk region1818of the substrate1816.

FIG.18Ais a perspective view of an example planar transistor1800comprising a gate1802that controls current flow between a source region1804and a drain region1806. The transistor1800is planar in that the source region1804and the drain region1806are planar with respect to the substrate surface1808.

FIG.18Bis a perspective view of an example FinFET transistor1820comprising a gate1822that controls current flow between a source region1824and a drain region1826. The transistor1820is non-planar in that the source region1824and the drain region1826comprise “fins” that extend upwards from the substrate surface1828. As the gate1822encompasses three sides of the semiconductor fin that extends from the source region1824to the drain region1826, the transistor1820can be considered a tri-gate transistor.FIG.18Billustrates one S/D fin extending through the gate1822, but multiple S/D fins can extend through the gate of a FinFET transistor.

FIG.18Cis a perspective view of a gate-all-around (GAA) transistor1840comprising a gate1842that controls current flow between a source region1844and a drain region1846. The transistor1840is non-planar in that the source region1844and the drain region1846are elevated from the substrate surface1828.

FIG.18Dis a perspective view of a GAA transistor1860comprising a gate1862that controls current flow between multiple elevated source regions1864and multiple elevated drain regions1866. The transistor1860is a stacked GAA transistor as the gate controls the flow of current between multiple elevated S/D regions stacked on top of each other. The transistors1840and1860are considered gate-all-around transistors as the gates encompass all sides of the semiconductor portions that extends from the source regions to the drain regions. The transistors1840and1860can alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors depending on the width (e.g., widths1848and1868of transistors1840and1860, respectively) of the semiconductor portions extending through the gate.

Returning toFIG.17, a transistor1740may include a gate1722formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material.

The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor1740is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

The S/D regions1720may be formed within the die substrate1702adjacent to the gate1722of individual transistors1740. The S/D regions1720may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate1702to form the S/D regions1720. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate1702may follow the ion-implantation process. In the latter process, the die substrate1702may first be etched to form recesses at the locations of the S/D regions1720. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions1720. In some implementations, the S/D regions1720may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions1720may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions1720.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors1740) of the device layer1704through one or more interconnect layers disposed on the device layer1704(illustrated inFIG.17as interconnect layers1706-1710). For example, electrically conductive features of the device layer1704(e.g., the gate1722and the S/D contacts1724) may be electrically coupled with the interconnect structures1728of the interconnect layers1706-1710. The one or more interconnect layers1706-1710may form a metallization stack (also referred to as an “ILD stack”)1719of the integrated circuit device1700.

The interconnect structures1728may be arranged within the interconnect layers1706-1710to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures1728depicted inFIG.17. Although a particular number of interconnect layers1706-1710is depicted inFIG.17, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures1728may include lines1728aand/or vias1728bfilled with an electrically conductive material such as a metal. The lines1728amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate1702upon which the device layer1704is formed. For example, the lines1728amay route electrical signals in a direction in and out of the page and/or in a direction across the page. The vias1728bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate1702upon which the device layer1704is formed. In some embodiments, the vias1728bmay electrically couple lines1728aof different interconnect layers1706-1710together.

The interconnect layers1706-1710may include a dielectric material1726disposed between the interconnect structures1728, as shown inFIG.17. In some embodiments, dielectric material1726disposed between the interconnect structures1728in different ones of the interconnect layers1706-1710may have different compositions; in other embodiments, the composition of the dielectric material1726between different interconnect layers1706-1710may be the same. The device layer1704may include a dielectric material1726disposed between the transistors1740and a bottom layer of the metallization stack as well. The dielectric material1726included in the device layer1704may have a different composition than the dielectric material1726included in the interconnect layers1706-1710; in other embodiments, the composition of the dielectric material1726in the device layer1704may be the same as a dielectric material1726included in any one of the interconnect layers1706-1710.

A first interconnect layer1706(referred to as Metal 1 or “M1”) may be formed directly on the device layer1704. In some embodiments, the first interconnect layer1706may include lines1728aand/or vias1728b, as shown. The lines1728aof the first interconnect layer1706may be coupled with contacts (e.g., the S/D contacts1724) of the device layer1704. The vias1728bof the first interconnect layer1706may be coupled with the lines1728aof a second interconnect layer1708.

The second interconnect layer1708(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer1706. In some embodiments, the second interconnect layer1708may include via1728bto couple the lines1728of the second interconnect layer1708with the lines1728aof a third interconnect layer1710. Although the lines1728aand the vias1728bare structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines1728aand the vias1728bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

The third interconnect layer1710(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer1708according to similar techniques and configurations described in connection with the second interconnect layer1708or the first interconnect layer1706. In some embodiments, the interconnect layers that are “higher up” in the metallization stack1719in the integrated circuit device1700(i.e., farther away from the device layer1704) may be thicker that the interconnect layers that are lower in the metallization stack1719, with lines1728aand vias1728bin the higher interconnect layers being thicker than those in the lower interconnect layers.

The integrated circuit device1700may include a solder resist material1734(e.g., polyimide or similar material) and one or more conductive contacts1736formed on the interconnect layers1706-1710. InFIG.17, the conductive contacts1736are illustrated as taking the form of bond pads. The conductive contacts1736may be electrically coupled with the interconnect structures1728and configured to route the electrical signals of the transistor(s)1740to external devices. For example, solder bonds may be formed on the one or more conductive contacts1736to mechanically and/or electrically couple an integrated circuit die including the integrated circuit device1700with another component (e.g., a printed circuit board). The integrated circuit device1700may include additional or alternate structures to route the electrical signals from the interconnect layers1706-1710; for example, the conductive contacts1736may include other analogous features (e.g., posts) that route the electrical signals to external components.

In some embodiments in which the integrated circuit device1700is a double-sided die, the integrated circuit device1700may include another metallization stack (not shown) on the opposite side of the device layer(s)1704. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers1706-1710, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s)1704and additional conductive contacts (not shown) on the opposite side of the integrated circuit device1700from the conductive contacts1736.

In other embodiments in which the integrated circuit device1700is a double-sided die, the integrated circuit device1700may include one or more through silicon vias (TSVs) through the die substrate1702; these TSVs may make contact with the device layer(s)1704, and may provide conductive pathways between the device layer(s)1704and additional conductive contacts (not shown) on the opposite side of the integrated circuit device1700from the conductive contacts1736. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device1700from the conductive contacts1736to the transistors1740and any other components integrated into the die1700, and the metallization stack1719can be used to route I/O signals from the conductive contacts1736to transistors1740and any other components integrated into the die1700.

Multiple integrated circuit devices1700may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).

FIG.19is a cross-sectional side view of an integrated circuit device assembly1900that may include any of the capacitors108,110disclosed herein. The integrated circuit device assembly1900includes a number of components disposed on a circuit board1902(which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly1900includes components disposed on a first face1940of the circuit board1902and an opposing second face1942of the circuit board1902; generally, components may be disposed on one or both faces1940and1942.

In some embodiments, the circuit board1902may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board1902. In other embodiments, the circuit board1902may be a non-PCB substrate. In some embodiments the circuit board1902may, for example, support the base die102. The integrated circuit device assembly1900illustrated inFIG.19includes a package-on-interposer structure1936coupled to the first face1940of the circuit board1902by coupling components1916. The coupling components1916may electrically and mechanically couple the package-on-interposer structure1936to the circuit board1902, and may include solder balls (as shown inFIG.19), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure1936may include an integrated circuit component1920coupled to an interposer1904by coupling components1918. The coupling components1918may take any suitable form for the application, such as the forms discussed above with reference to the coupling components1916. Although a single integrated circuit component1920is shown inFIG.19, multiple integrated circuit components may be coupled to the interposer1904; indeed, additional interposers may be coupled to the interposer1904. The interposer1904may provide an intervening substrate used to bridge the circuit board1902and the integrated circuit component1920.

The integrated circuit component1920may be a packaged or unpacked integrated circuit product that includes one or more integrated circuit dies (e.g., the die1602ofFIG.16, the integrated circuit device1700ofFIG.17) and/or one or more other suitable components. A packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate with the integrated circuit dies and package substrate encapsulated in a casing material, such as a metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component1920, a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer1904. The integrated circuit component1920can comprise one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I/O controller, memory, or network interface controller. In some embodiments, the integrated circuit component1920can comprise one or more additional active or passive devices such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

In embodiments where the integrated circuit component1920comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).

In addition to comprising one or more processor units, the integrated circuit component1920can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.

Generally, the interposer1904may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer1904may couple the integrated circuit component1920to a set of ball grid array (BGA) conductive contacts of the coupling components1916for coupling to the circuit board1902. In the embodiment illustrated inFIG.19, the integrated circuit component1920and the circuit board1902are attached to opposing sides of the interposer1904; in other embodiments, the integrated circuit component1920and the circuit board1902may be attached to a same side of the interposer1904. In some embodiments, three or more components may be interconnected by way of the interposer1904.

In some embodiments, the interposer1904may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer1904may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer1904may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer1904may include metal interconnects1908and vias1910, including but not limited to through hole vias1910-1(that extend from a first face1950of the interposer1904to a second face1954of the interposer1904), blind vias1910-2(that extend from the first or second faces1950or1954of the interposer1904to an internal metal layer), and buried vias1910-3(that connect internal metal layers).

In some embodiments, the interposer1904can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer1904comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer1904to an opposing second face of the interposer1904.

The interposer1904may further include embedded devices1914, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer1904. The package-on-interposer structure1936may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board

The integrated circuit device assembly1900may include an integrated circuit component1924coupled to the first face1940of the circuit board1902by coupling components1922. The coupling components1922may take the form of any of the embodiments discussed above with reference to the coupling components1916, and the integrated circuit component1924may take the form of any of the embodiments discussed above with reference to the integrated circuit component1920.

The integrated circuit device assembly1900illustrated inFIG.19includes a package-on-package structure1934coupled to the second face1942of the circuit board1902by coupling components1928. The package-on-package structure1934may include an integrated circuit component1926and an integrated circuit component1932coupled together by coupling components1930such that the integrated circuit component1926is disposed between the circuit board1902and the integrated circuit component1932. The coupling components1928and1930may take the form of any of the embodiments of the coupling components1916discussed above, and the integrated circuit components1926and1932may take the form of any of the embodiments of the integrated circuit component1920discussed above. The package-on-package structure1934may be configured in accordance with any of the package-on-package structures known in the art.

FIG.20is a block diagram of an example electrical device2000that may include one or more of the capacitors108,110disclosed herein. For example, any suitable ones of the components of the electrical device2000may include one or more of the integrated circuit device assemblies1900, integrated circuit components1920, integrated circuit devices1700, or integrated circuit dies1602disclosed herein, and may be arranged in any of the microelectronic assemblies disclosed herein. A number of components are illustrated inFIG.20as included in the electrical device2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device2000may be attached to one or more motherboards mainboards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the electrical device2000may not include one or more of the components illustrated inFIG.20, but the electrical device2000may include interface circuitry for coupling to the one or more components. For example, the electrical device2000may not include a display device2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device2006may be coupled. In another set of examples, the electrical device2000may not include an audio input device2024or an audio output device2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device2024or audio output device2008may be coupled.

The electrical device2000may include a memory2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory2004may include memory that is located on the same integrated circuit die as the processor unit2002. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, the electrical device2000can comprise one or more processor units2002that are heterogeneous or asymmetric to another processor unit2002in the electrical device2000. There can be a variety of differences between the processing units2002in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units2002in the electrical device2000.

In some embodiments, the electrical device2000may include a communication component2012(e.g., one or more communication components). For example, the communication component2012can manage wireless communications for the transfer of data to and from the electrical device2000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

In some embodiments, the communication component2012may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component2012may include multiple communication components. For instance, a first communication component2012may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component2012may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component2012may be dedicated to wireless communications, and a second communication component2012may be dedicated to wired communications.

The electrical device2000may include battery/power circuitry2014. The battery/power circuitry2014may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device2000to an energy source separate from the electrical device2000(e.g., AC line power).

The electrical device2000may include a display device2006(or corresponding interface circuitry, as discussed above). The display device2006may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device2000may include an audio output device2008(or corresponding interface circuitry, as discussed above). The audio output device2008may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.

The electrical device2000may include an audio input device2024(or corresponding interface circuitry, as discussed above). The audio input device2024may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device2000may include a Global Navigation Satellite System (GNSS) device2018(or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device2018may be in communication with a satellite-based system and may determine a geolocation of the electrical device2000based on information received from one or more GNSS satellites, as known in the art.

The electrical device2000may include an other output device2010(or corresponding interface circuitry, as discussed above). Examples of the other output device2010may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The electrical device2000may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device2000may be any other electronic device that processes data. In some embodiments, the electrical device2000may comprise multiple discrete physical components. Given the range of devices that the electrical device2000can be manifested as in various embodiments, in some embodiments, the electrical device2000can be referred to as a computing device or a computing system.

Examples

Example 1 includes a device comprising a capacitor, the capacitor comprising a first metal layer on a substrate; a high-k dielectric layer adjacent the first metal layer; and a second metal layer adjacent the high-k dielectric layer; a first electrode comprising part of the first metal layer and part of the second metal layer; and a second electrode comprising part of the first metal layer and part of the second metal layer, wherein, in use, an electric field of the capacitor is substantially parallel to the high-k dielectric layer.

Example 2 includes the subject matter of Example 1, and further including a second capacitor, the second capacitor comprising a first electrode comprising part of the first metal layer; and a second electrode comprising part of the second metal layer, wherein, in use, an electric field of the second capacitor is substantially perpendicular to the high-k dielectric layer.

Example 3 includes the subject matter of any of Examples 1 and 2, and further including compute circuitry, wherein the compute circuitry in a high-power mode is to use the second capacitor as a voltage support device, wherein the compute circuitry in a low-power mode is to use the capacitor as a voltage support device.

Example 4 includes the subject matter of any of Examples 1-3, and further including a die, wherein the die comprises the capacitor, the second capacitor, and the compute circuitry.

Example 5 includes the subject matter of any of Examples 1-4, and further including a first die and a second die different from the first die, wherein the first die comprises the capacitor and the second capacitor, wherein the second die comprises the compute circuitry.

Example 6 includes the subject matter of any of Examples 1-5, and wherein most of the part of the first electrode of the first metal layer of the second capacitor is directly above the part of the second electrode of the second metal layer of the second capacitor.

Example 7 includes the subject matter of any of Examples 1-6, and wherein the first electrode of the second capacitor comprises deep trenches and the second electrode of the second capacitor comprises deep trenches.

Example 8 includes the subject matter of any of Examples 1-7, and wherein the high-k dielectric layer has a relative permittivity of at least 1,000.

Example 9 includes the subject matter of any of Examples 1-8, and wherein, for the first metal layer and the second metal layer, the first electrode is separated from the second electrode by at least twice a thickness of the high-k dielectric layer.

Example 10 includes the subject matter of any of Examples 1-9, and further including an on-die circuit to absorb radiofrequency (RF) interference, wherein the on-die circuit to absorb RF interference comprises the capacitor.

Example 11 includes the subject matter of any of Examples 1-10, and wherein the capacitor comprises a plurality of unit cells, wherein individual unit cells of the plurality of unit cells comprises a plurality of vias of the first electrode that extend through the high-k dielectric layer and a plurality of vias from the second electrode that extend through the high-k dielectric layer, wherein, in use, for individual unit cells of the plurality of unit cells, an electric field of the capacitor extends from individual vias of the plurality of vias of the first electrode to individual vias of the plurality of vias of the second electrode.

Example 12 includes the subject matter of any of Examples 1-11, and wherein vias connected to the first electrode passing from the first metal layer to the second metal layer do not pass through the second electrode, wherein vias connected to the second electrode passing from the first metal layer to the second metal layer do not pass through the first electrode.

Example 13 includes the subject matter of any of Examples 1-12, and wherein the high-k dielectric layer has a thickness less than 2 micrometers, wherein a voltage across the first electrode and the second electrode is over 3 volts.

Example 14 includes a device comprising a capacitor, the capacitor comprising a first metal layer on a substrate; a high-k dielectric layer adjacent the first metal layer; and a second metal layer adjacent the high-k dielectric layer; a first electrode comprising part of the first metal layer and part of the second metal layer; and a second electrode comprising part of the first metal layer and part of the second metal layer, wherein, for the first metal layer and the second metal layer, the first electrode is separated from the second electrode by at least twice a thickness of the high-k dielectric layer.

Example 15 includes the subject matter of Example 14, and further including a second capacitor, the second capacitor comprising a first electrode comprising part of the first metal layer; and a second electrode comprising part of the second metal layer, wherein, in use, an electric field of the second capacitor is substantially perpendicular to the high-k dielectric layer.

Example 16 includes the subject matter of any of Examples 14 and 15, and further including compute circuitry, wherein the compute circuitry in a high-power mode is to use the second capacitor as a voltage support device, wherein the compute circuitry in a low-power mode is to use the capacitor as a voltage support device.

Example 17 includes the subject matter of any of Examples 14-16, and further including a die, wherein the die comprises the capacitor, the second capacitor, and the compute circuitry.

Example 18 includes the subject matter of any of Examples 14-17, and further including a first die and a second die different from the first die, wherein the first die comprises the capacitor and the second capacitor, wherein the second die comprises the compute circuitry.

Example 19 includes the subject matter of any of Examples 14-18, and wherein most of the part of the first electrode of the first metal layer of the second capacitor is directly above the part of the second electrode of the second metal layer of the second capacitor.

Example 20 includes the subject matter of any of Examples 14-19, and wherein the first electrode of the second capacitor comprises deep trenches and the second electrode of the second capacitor comprises deep trenches.

Example 21 includes the subject matter of any of Examples 14-20, and wherein the high-k dielectric layer has a relative permittivity of at least 1,000.

Example 22 includes the subject matter of any of Examples 14-21, and wherein, for the first metal layer and the second metal layer, the first electrode is separated from the second electrode by at least twice a thickness of the high-k dielectric layer.

Example 23 includes the subject matter of any of Examples 14-22, and further including an on-die circuit to absorb radiofrequency (RF) interference, wherein the on-die circuit to absorb RF interference comprises the capacitor.

Example 24 includes the subject matter of any of Examples 14-23, and wherein the capacitor comprises a plurality of unit cells, wherein individual unit cells of the plurality of unit cells comprises a plurality of vias of the first electrode that extend through the high-k dielectric layer and a plurality of vias from the second electrode that extend through the high-k dielectric layer, wherein, in use, for individual unit cells of the plurality of unit cells, an electric field of the capacitor extends from individual vias of the plurality of vias of the first electrode to individual vias of the plurality of vias of the second electrode.

Example 25 includes the subject matter of any of Examples 14-24, and wherein vias connected to the first electrode passing from the first metal layer to the second metal layer do not pass through the second electrode, wherein vias connected to the second electrode passing from the first metal layer to the second metal layer do not pass through the first electrode.

Example 26 includes the subject matter of any of Examples 14-25, and wherein the high-k dielectric layer has a thickness less than 2 micrometers, wherein a voltage across the first electrode and the second electrode is over 3 volts.

Example 27 includes a device comprising a first metal layer on a substrate; a high-k dielectric layer adjacent the first metal layer; a second metal layer on the substrate; and means for creating a capacitor from the first metal layer, the high-k dielectric layer, and the second metal layer with an electric field substantially parallel to the high-k dielectric layer.

Example 28 includes the subject matter of Example 27, and further including means for creating a second capacitor from the first metal layer, the high-k dielectric layer, and the second metal layer with an electric field substantially perpendicular to the high-k dielectric layer.

Example 29 includes the subject matter of any of Examples 27 and 28, and further including compute circuitry, wherein the compute circuitry in a high-power mode is to use the second capacitor as a voltage support device, wherein the compute circuitry in a low-power mode is to use the capacitor as a voltage support device.

Example 30 includes the subject matter of any of Examples 27-29, and further including a die, wherein the die comprises the capacitor, the second capacitor, and the compute circuitry.

Example 31 includes the subject matter of any of Examples 27-30, and further including a first die and a second die different from the first die, wherein the first die comprises the capacitor and the second capacitor, wherein the second die comprises the compute circuitry.

Example 32 includes the subject matter of any of Examples 27-31, and wherein the means for creating the second capacitor comprises deep trenches.

Example 33 includes the subject matter of any of Examples 27-32, and wherein the high-k dielectric layer has a relative permittivity of at least 1,000.

Example 34 includes the subject matter of any of Examples 27-33, and further including an on-die circuit to absorb radiofrequency (RF) interference, wherein the on-die circuit to absorb RF interference comprises the capacitor.

Example 35 includes the subject matter of any of Examples 27-34, and wherein the capacitor comprises a plurality of unit cells, wherein individual unit cells of the plurality of unit cells comprises a plurality of vias of a first electrode that extend through the high-k dielectric layer and a plurality of vias from a second electrode that extend through the high-k dielectric layer, wherein, in use, for individual unit cells of the plurality of unit cells, an electric field of the capacitor extends from individual vias of the plurality of vias of the first electrode to individual vias of the plurality of vias of the second electrode.