Connector footprints in printed circuit board (PCB)

An electrical connector footprint on a printed circuit board (PCB) can include vias and antipads surrounding those vias. While conventional antipads surrounding vias are large in order to improve impedance of the PCB, the presence of the antipads can compromise the integrity of the ground plane and can permit cross talk to arise between differential pairs on different layers in the PCB. Antipads can be constructed and arranged so as to limit cross talk between layers in a PCB, while also maximizing impedance.

BACKGROUND

Typical electrical connector footprints, such as on printed circuit boards (PCB), contain vias and antipads surrounding those vias. While conventional antipads surrounding vias are large in order to improve impedance of the PCB, the very presence of the antipads compromises the integrity of the ground plane and permits cross talk to arise between differential pairs on different layers in the PCB.

SUMMARY

In accordance with one embodiment, a printed circuit board (PCB) can include a first electrically conductive layer that includes a first electrically conductive region and a first antipad defined by the first electrically conductive region. The first antipad can include a first dielectric region and a portion of a first electrically plated via that extends through the first dielectric region along a first direction. The first antipad can have a first maximum area along a first plane that is normal to the first direction, wherein the first dielectric region is aligned with the first electrically conductive region along the first plane. The PCB can further include a first dielectric layer that is disposed below the first electrically conductive layer along the first direction. The PCB can further include a second electrically conductive layer that is disposed below the first dielectric layer along the first direction. The second electrically conductive layer can include a second electrically conductive region and a second antipad defined by the second electrically conductive region. The second antipad can have a second maximum area along a second plane that is normal to the first direction. The second maximum area can be less than the first maximum area. The PCB can further include a third electrically conductive layer disposed below the second electrically conductive layer along the first direction such that no additional electrically conductive layer is disposed between the second electrically conductive layer and the third electrically conductive layer along the first direction. The third electrically conductive layer can define a third electrically conductive region and a third antipad. The third antipad can have a third maximum area along a third plane that is normal to the first direction. The third maximum area can be substantially equal to the second maximum area, wherein at least a portion of each of the second antipad and the third antipad is aligned with the portion of the first electrically plated via along the first direction.

In accordance with another embodiment, a PCB can include a first differential pair of electrical signal traces that defines a first centerline centrally disposed between the electrical signal traces of the first differential signal pair. The PCB can further include a second differential pair of electrical signal traces spaced from the first differential pair along a first direction, the second differential pair defining a second centerline centrally disposed between the electrical signal traces of the second differential signal pair. The PCB can further include an electrically conductive layer disposed between the first differential signal pair and the second differential signal pair along the first direction. The electrically conductive layer can include an electrically conductive region and first and second antipads that are defined by the electrically conductive region. The first and second antipads can be spaced from each other along a second direction that is perpendicular to the first direction, wherein each of the first and second differential pairs can be disposed between the first and second antipads with respect to the second direction. The first centerline can be disposed closer to the first antipad than the second antipad along the second direction, and the second centerline can be disposed closer to the second antipad than the first antipad along the second direction.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Referring generally toFIGS. 1A-4B, a printed circuit board (PCB) can include one or more electrically conductive layers and one or more dielectric or electrically insulative layers. The electrically conductive layers can be configured as electrically conductive ground layers or electrically conductive signal layers. The electrically conductive ground layers can include a conductive region and an antipad defined by the conductive region.

For convenience, the same or equivalent elements in the various embodiments illustrated in the drawings have been identified with the same reference numerals. Certain terminology is used in the following description for convenience only and is not limiting. The words “left,” “right,” “front,” “rear,” “upper,” and “lower” designate directions in the drawings to which reference is made. The words “forward,” “forwardly,” “rearward,” “inner,” “inward,” “inwardly,” “outer,” “outward,” “outwardly,” “upward,” “upwardly,” “downward,” and “downwardly” refer to directions toward and away from, respectively, the geometric center of the object referred to and designated parts thereof. The terminology intended to be non-limiting includes the above-listed words, derivatives thereof and words of similar import.

Referring initially toFIGS. 1A-2B, a PCB, for instance a PCB100′ shown inFIG. 1A-Bor a PCB100″ shown inFIGS. 2A-B, can include one or more electrically conductive layers102. In accordance with the illustrated embodiments, the PCB100′ and the PCB100″ each include nine conductive layers102a-i, although it will be understood that the PCB can include any number of conductive layers102as desired. The PCB100′ and the PCB100″ each define a top layer, for instance the electrically conductive layer102a, which can also be referred to as the top layer102ain accordance with illustrated embodiment. The PCB100′ and the PCB100″ each further define a bottom layer that is spaced from the top layer along a first or transverse direction T. In accordance with illustrated embodiments, the electrically conductive layer102idefines the bottom layer, and thus the electrically conductive layer can also be referred to as the bottom layer102i. Each of the electrically conductive layers102define a thickness TH as measured along the transverse direction T. The printed circuit boards (PCBs)100′ and100″ can each include a top surface122that supports the electrically conductive layer102a.

Various structures are described herein as extending vertically along the first or transverse direction “T” that is substantially perpendicular to a second or lateral direction “A” and a third or longitudinal direction “L”, and horizontally along the lateral direction A and the longitudinal direction L that is substantially perpendicular to the lateral direction A. As illustrated, the transverse direction “T” extends along an upward/downward direction of the PCBs100′ and100″. For instance, a direction from the top layer102atoward the bottom layer102idefines the downward direction, and a direction from the bottom layer102ito the top layer102adefines the upward direction. Thus, for instance, a first layer that is disposed in the upward direction from a second layer can be referred to as being above the second layer, and the second layer that is disposed in the downward direction from the first layer can be referred to as being below the first layer.

Thus, unless otherwise specified herein, the terms “lateral,” “longitudinal” and “transverse” are used to describe the orthogonal directional components of various components. It should be appreciated that while the longitudinal and lateral directions are illustrated as extending along a horizontal plane, and that while the transverse direction is illustrated as extending along a vertical plane, the planes that encompass the various directions may differ during use, depending, for instance, on the orientation of the various components. Accordingly, the directional terms “vertical” and “horizontal” are used to describe the PCBs and its components as illustrated merely for the purposes of clarity and convenience, it being appreciated that these orientations may change during use.

The PCBs100′ and100″ can further include one or more dielectric or electrically insulative layers104, such as a plurality of dielectric layers or electrically insulative layers104a-h, that are disposed between the conductive layers102a-ialong the transverse direction T. For instance, each dielectric layer104can be disposed between a select two conductive layers102to electrically isolate the select two conductive layers102from each other. Thus, the select two conductive layers102can be referred to as consecutive layers102because only one dielectric layer104is disposed between the consecutive layers102along the transverse direction T. A consecutive conductive layer102may be understood to be the next conductive layer102above or below a given conductive layer102along the transverse direction T. For instance, in accordance with the illustrated embodiment, conductive layers102band102ccan be referred to as consecutive conductive layers with respect to each other because only the dielectric layer104bis disposed between the conductive layers102band102calong the transverse direction T.

The conductive layers102can include electrically conductive ground layers106, electrically conductive signal layers108, and electrically conductive power layers. In accordance with the illustrated embodiments, the conductive layers102a-b,102d-e, and102g-iare configured as electrically conductive ground layers106a-g, respectively. Further, in accordance with the illustrated embodiments, the conductive layers102cand102fare configured as electrically conductive signal layers108a-b, respectively. The signal layers108a-bcan each include one or more conductive regions, such as electrically conductive traces134a-b, which can be made of copper or any other conductive material as desired. The conductive traces134a-bcan each be part of a differential pair of signal traces136. The ground layers106a-gcan include one or more electrically conductive regions107, which can be made of copper or any other electrically conductive material as desired. The dielectric layers104a-gcan include dielectric or electrically nonconductive material, for instance plastic.

It will be appreciated that whileFIGS. 1A-2Bdepict an example configuration of the PCB100′ and the PCB100″, the conductive layers102and the dielectric layers104can be arranged in a variety of sequences along the transverse direction T. Thus, the instant disclosure should not be limited to the example configuration shown inFIGS. 1A-2B.

Referring toFIGS. 1A-2B, the PCB100′ and the PCB100″ can each further include a plurality of signal vias110, such as adjacent electrically conductive vias110a-b, which can also be referred to as electrically plated vias110a-b. In accordance with the illustrated embodiments, the electrically plated vias110a-binclude a respective hole112a-bthat defines a respective open end114a-b. Further, in accordance with the illustrated embodiment, the vias110a-bcan extend into, for instance through, two or more of the conductive layers102and the dielectric layers104along the transverse direction T. The vias110a-bcan further include a conductive surface116. Each hole112a-bcan be at least partially, for instance fully, plated with the conductive surface116. Thus, the holes112a-band the conductive surface116can be collectively referred to as plated, through-holes118a-b. The holes112a-bcan be configured to be at least partially, for instance fully, filled with a conductive metal. The holes112a-bcan receive an electrically conductive insert from another electronic device, such as a press fit connector for instance. In accordance with the illustrated embodiments, the vias110a-bcan be electrically connected to electrically conductive surface pads, for instance a surface pad120that rests on the surface122of the PCB100′ and100″.

The vias110a-bare depicted inFIGS. 1A-2Bas being cylindrical, although it will be appreciated that the vias can define any shape as desired. In accordance with the illustrated embodiment, each hole112a-bof the vias110a-bcan define respective cross-sectional dimensions G and G′ along the lateral direction A or the longitudinal direction L. For instance, the holes112a-b, and thus the vias110a-b, can be cylindrical and thus the respective cross-sectional dimensions G and G′ can be diameters G and G′ that extend in a plane that is normal to the transverse direction T. Thus, each of the cross-sectional dimensions G and G′ can define a cross-sectional area of each via110a-b, respectively.

Still referring toFIGS. 1A-2B, traces134a-bof the signal layer108bare electrically coupled to the vias110a-b, respectively. Thus, the traces134in one or more of the signal layers108can be electrically coupled to one or more of the vias110. In particular, the traces134a-bcan be electrically coupled to the plated, through-holes118a-b, respectively, by contacting the conductive surfaces116of each of the plated, through-holes118a-bso as to establish an electrical connection between the traces134a-band the vias110a-b. The vias110a-bcan be connected to differential traces134a-brespectively, to establish a differential pair of signal traces.

With continuing reference toFIGS. 1A-2B, one or more of the conductive layers102can each include one or more electrically conductive regions107and one or more antipads124that are defined by respective electrically conductive regions107. In accordance with the illustrated embodiments, the conductive layers102a-102iinclude conductive regions107and antipads124a-r. Each of the antipads124can include a dielectric region126and a portion of a select electrically plated via110that extends through the dielectric region126along the transverse direction T. Thus, each of the antipads124can be referred to as an individual void in a respective conductive layer102. Each antipad124can be surrounded by the conductive region107of each respective conductive layer102. The antipads124may contain one or more of: a portion of one or more electrically conductive vias (such as vias110a-b), air, or a dielectric or electrically insulative material. In an example embodiment, individual antipads124may surround one or more of the vias110, such as vias110a-b, and separate respective conductive regions107from the one or more vias110a-b, thereby preventing the conductive regions107from contacting an electrically conductive via110. In accordance with the illustrated embodiments, the conductive layers102can include conductive regions107and dielectric regions126that electrically separate the conductive regions107from the electrically plated vias110. In the electrically conductive ground layer106for instance, the dielectric regions126can be disposed between the conductive regions107and the conductive surfaces116of the vias110along the lateral and longitudinal directions A and L such that the conductive regions107and the vias110are electrically separate. The antipads124can each include a portion of the vias110. For instance, the vias110can define a length along the transverse direction T, and the antipads124can each include a portion of the length of the vias110along the transverse direction T.

The antipads124can each have a cross-sectional area along a respective plane that is normal to the transverse direction T. For instance, a select antipad124of a select conductive layer102can have a maximum cross-sectional area along a select plane that is normal to the transverse direction T. The maximum cross-sectional area can be defined by a select conductive region107of the select conductive layer102, wherein the dielectric region126of the select antipad124is aligned with the select conductive region107along the select plane. Further, each antipad124can have a maximum volume which can be defined by a product of the maximum area and the thickness TH of the respective conductive layer102.

The antipads124may be formed in a variety of ways. For example, each of antipads124a-imay be created by first forming conductive regions107of the respective conductive layers102a-iand then removing sections of the conductive regions107to create the respective dielectric regions126through, for example, etching. As will be explained further below, select ones of the antipads124may also be formed by back drilling.

Referring still toFIGS. 1A-2B, the PCB100′ includes antipads124a-ethat are above the antipads124g-lalong the transverse direction T, and the PCB100″ includes antipads124a-fthat are above the antipads124m-ralong the transverse direction T. In accordance with the illustrated embodiments, the antipads124a-eare depicted as being rectangular although it will be appreciated that the antipads124a-ecan assume a wide variety of shapes as desired. As illustrated, the antipads124a-ecan define a first cross-sectional dimension X defined by a longest straight line that extends from an edge of the conductive region107to an opposed edge of the conductive region107along the lateral direction X. Further, with particular reference toFIGS. 1B, 2B, 3B and 4B, the antipads124a-ecan define a second cross-sectional dimension B defined by a longest straight line that extends from an edge of the conductive region107to an opposed edge of the conductive region107along the longitudinal direction L. Thus, a maximum cross-sectional area, which can be referred to as a maximum area, of the antipads124a-ealong a respective plane that is normal to the transverse direction T can be substantially equal to a product of the first cross-sectional dimension A and the second cross-sectional dimension B. Further, the maximum cross-sectional area of the antipads124a-ecan be rectangular, and each of the antipads124a-ecan have a maximum volume that can be defined by a product of the respective maximum cross-sectional area and the thickness TH of the respective conductive layer102. Select ones of the antipads124, for instance the illustrated antipads124a-e, can include portions of more than one via110, for instance two vias110a-bin accordance with the illustrated embodiments. Thus, the maximum cross-sectional areas of the antipads124a-ealong respective planes that are normal to the transverse direction T can be larger than maximum cross-sectional areas of the vias110a-balong respective planes that are normal to the transverse direction T.

With particular reference toFIGS. 1A-B, the PCB100′ can include conductive layers102g-ithat include the antipads124g-l. For instance, in accordance with the illustrated embodiment, the conductive layer102gincludes the antipads124gand124jspaced from each other along the longitudinal direction L, the conductive layer102hincludes the antipads124hand124kspaced from each other along the longitudinal direction L, and the conductive layer102iincludes the antipads124iand124lspaced from each other along the longitudinal direction L. It will be understood that the conductive layers102can include any number of antipads124as desired and the antipads124can be positioned on the respective conductive layers as desired. The antipads124g-lare depicted as being cylindrical although it will be appreciated that the antipads124g-lcan assume a wide variety of shapes as desired. As illustrated, the antipads124g-ican define a cross-sectional dimension C defined by a longest straight line that extends from an edge of the conductive region107to an opposed edge of the conductive region107along the lateral direction A. The cross-sectional dimension C can be a diameter C, and thus the cross-sectional dimension C can also be defined by a longest straight line that extends from an edge of the conductive region107to an opposed edge of the conductive region along the longitudinal direction L. Similarly, as illustrated, the antipads124j-lcan define a cross-sectional dimension C′ defined by a longest straight line that extends from an edge of the conductive region107to an opposed edge of the conductive region107along the longitudinal direction L. The cross-sectional dimension C′ can be a cross-sectional diameter C′, and thus the cross-sectional dimension C′ of the antipads124j-lcan also be defined by a longest straight line that extends from an edge of the conductive region107to an opposed edge of the conductive region along the lateral direction A.

With continuing reference toFIGS. 1A-B, the antipads124g-iand124j-lcan have maximum cross-sectional areas, which can be referred to as maximum area, along respective planes that are normal to the transverse direction T, and the maximum cross sectional areas of the antipads124g-iand124j-lcan be defined by the cross-sectional dimensions, for instance cross-sectional diameters, C and C′, respectively. In accordance with the illustrated embodiment, the maximum cross-sectional areas of each of the antipads124g-lcan be less than the maximum cross-sectional areas of each of the antipads124a-e. Thus, the cross-sectional dimensions C and C′ of the antipads124g-iand124j-l, respectively, can be less than one or both of the cross-sectional dimensions X and B of the antipads124a-e. Further, the maximum cross-sectional areas of each of the antipads (e.g., antipads124g-l) below the signal layer108can be circular, or otherwise shaped differently than the antipads124a-ethat are disposed above the signal layer108along the transverse direction T. Each antipad124g-lcan have a maximum volume that can be defined by a product of the respective maximum cross-sectional area and the thickness TH of the respective conductive layer102. Select ones of the antipads124, for instance the illustrated antipads124g-l, can include portions of only one via110. For instance, in accordance with the illustrated embodiment, the antipads124g-iinclude a portion of only the via110aand the antipads124j-linclude a portion of only the via110b. The antipads124g-lcan further include dielectric regions126that separate the vias110from the conductive regions107along respective planes that are normal to the transverse direction T. Thus, the maximum cross-sectional areas of the antipads124g-lalong respective planes that are normal to the transverse direction T can be larger than maximum cross-section areas of the vias110a-balong respective planes that are normal to the transverse direction T. For instance, the maximum cross-sectional areas of the antipads124g-lcan include dielectric regions126that electrically separate the conductive regions107from the electrically plated vias110.

Thus, the PCB100′ can include a first electrically conductive layer, for instance a select one of the conductive layers102a-e, that includes a first conductive region, for instance the conductive region107, and a first antipad, for instance a select one of the antipads124a-e. The first antipad can include a first dielectric region, for instance the dielectric region126, and a portion of a first electrically plated via, for instance the via110a, that extends through the first dielectric region along the transverse direction T. The first antipad can have a first maximum area along a first plane that is normal to the transverse direction T, and the first dielectric region can be aligned with the first electrically conductive region along the first plane. The PCB100′ can further include a first dielectric layer, for instance a select one of the dielectric layers104a-f, that is disposed below the first electrically conductive layer along the transverse direction T. The PCB100′ can further include a second electrically conductive layer, for instance a select one of the conductive layers102g-i, that is disposed below the first dielectric layer along the transverse direction T. The second electrically conductive layer can include a second electrically conductive region and a second antipad, for instance a select one of the antipads124g-i, defined by the second electrically conductive region. The second antipad can have a second maximum area along a second plane that is normal to the transverse direction T, and the second maximum area can be less than the first maximum area.

Further, the PCB100′ can include a third electrically conductive layer, for instance a select one of the electrically conductive layers102hand102i, that is disposed below the second electrically conductive layer along the transverse direction T such that that no additional electrically conductive layer is disposed between the second electrically conductive layer and the third electrically conductive layer along the transverse direction T. The third electrically conductive layer can define a third electrically conductive region and a third antipad, for instance a select one of the antipads124hand124i, defined by the third electrically conductive region. The third antipad can have a third maximum area along a third plane that is normal to the transverse direction T. The third maximum area can be substantially equal to the second maximum area. As used herein, two or more values that are substantially equal to each other may refer to values that are within tolerances of a manufacturer. At least a portion of each of the second antipad and the third antipad can be aligned with the portion of the first electrically plated via along the transverse direction T.

The first antipad can further include a portion of a second electrically plated via, for instance the via110b, that extends through the first dielectric region along the transverse direction T. Further, the second electrically conductive layer can include a fourth antipad, for instance a select one of the antipads124j-l, that has a fourth maximum area along the second plane. The fourth maximum area can be substantially equal to the second maximum area. The third electrically conductive layer can further include a fifth antipad, for instance a select one of the antipads124kand124l, that is defined by the third electrically conductive region. The fifth antipad can have a maximum area along the third plane. The fifth maximum area can be substantially equal to the third maximum area.

The PCB100′ can further include a second dielectric layer disposed between the second electrically conductive layer and the third electrically conductive layer such that the second dielectric layer separates the second and third electrically conductive layers from each other and the second dielectric layer abuts each of the second and third electrically conductive layers.

Referring now toFIGS. 2A-B, the PCB100″ can include conductive layers102g-ithat include the antipads124m-r. For instance, in accordance with the illustrated embodiment, the conductive layer102gincludes the antipads124mand124pspaced from each other along the longitudinal direction L, the conductive layer102hincludes the antipads124nand124qspaced from each other along the longitudinal direction L, and the conductive layer102iincludes the antipads124oand124rspaced from each other along the longitudinal direction L. The antipads124m-rare depicted as being cylindrical although it will be appreciated that the antipads124m-rcan assume a wide variety of shapes as desired. As illustrated, the antipads124m-ocan define a cross-sectional dimension F defined by a longest straight line that extends from an edge of the conductive region107to an opposed edge of the conductive region107along the lateral direction A. The cross-section dimension F can be a diameter F, and thus the cross-sectional dimension F can also be defined by a longest straight line that extends from an edge of the conductive region107to an opposed edge of the conductive region along the longitudinal direction L. Similarly, as illustrated, the antipads124p-rcan define a cross-sectional dimension F′ defined by a longest straight line that extends from an edge of the conductive region107to an opposed edge of the conductive region107along the longitudinal direction L. The cross-sectional dimension F′ can be a cross-sectional diameter F′, and thus the cross-sectional dimension F′ of the antipads124p-rcan also be defined by a longest straight line that extends from an edge of the conductive region107to an opposed edge of the conductive region along the lateral direction A.

With continuing reference toFIGS. 2A-B, the antipads124m-oand124p-rcan have maximum cross-sectional areas, which can be referred to as maximum areas, along respective planes that are normal to the transverse direction T, and the maximum cross-sectional areas of the antipads124m-oand124p-rcan be defined by the cross-sectional dimensions, for instance cross-sectional diameters, F and F′, respectively. In accordance with the illustrated embodiment, the maximum cross-sectional areas of each of the antipads124m-rcan be less than the maximum cross-sectional areas of each of the antipads124a-e. Further, the maximum cross-sectional areas of the antipads124m-rbelow the signal layer108can be circular, or otherwise shaped differently than the antipads124a-ethat are disposed above the signal layer108along the transverse direction T. Thus, the cross-sectional dimensions F and F′ of the antipads124m-oand124p-r, respectively, can be less than one or both of the cross-sectional dimensions X and B of the antipads124a-e. In accordance with the illustrated embodiment, for instance before back drilling of the vias110a-b, the cross-section dimensions F and F′ can be substantially equal, for instance slightly larger, to the cross-sectional dimensions G and G′, respectively. Thus, before back drilling for instance, the maximum cross-section areas of the antipads124m-ralong respective planes that are normal to the transverse direction T can be substantially equal to the maximum cross-section areas of the vias110a-balong respective planes that are normal to the transverse direction T. Before back drilling described below, the conductive regions107of the conductive layers102g-ican be electrically coupled to the electrically conductive vias110a-b, as illustrated.

In another example in which the antipads124m-rhave the cross-sectional dimensions F and F′ that are slightly larger than the cross-sectional diameters G and G′, respectively, the conductive regions107of the conductive layers102g-iare not electrically coupled to the electrically conductive vias110a-b. Thus, the maximum cross-section area of antipads124m-rcan include a dielectric or electrically insulative material, such as the dielectric region126, that electrically separates the vias110a-bfrom the conductive regions107of the conductive layers102g-i.

Referring toFIGS. 1A-2B, the vias110a-bcan include an unused portion128, which can be referred to as a resonant stub. The unused portion128may be located above or below the signal layer108along the transverse direction T. In accordance with the illustrated embodiments, the unused portion128is disposed below the signal layers108along the transverse direction T. The unused portion128of the vias110a-bcan be located below the signal layer108bin the conductive layers102g-i. The unused portion128of the vias110a-bcan be disposed in a first group of conductive layers102having antipads124that are smaller than antipads in a second group of conductive layers102. For example, the first group may include the consecutive conductive layers102g-ithat are disposed below the signal layer108along the transverse direction T, and the second group may include consecutive conductive layers102a-ethat are disposed above the signal layer108along the transverse direction T. The first group of conductive layers102g-imay be disposed on a side of signal layer108bopposite the second group of conductive layers102a-ealong the transverse direction T. For example, the first group of conductive layers102g-imay be above or below the second group of conductive layers102a-ealong the transverse direction T. The antipads124g-rof the first group of conductive layers102may be smaller than the antipads124a-econtained in the second group.

The unused portion128of the vias110a-bcan act as a notch filter centered around a frequency that is primarily determined by a length of the unused portion128. The length of the unused portion128can be measured along the transverse direction T. The unused portion128can cause some of the energy of an electrical signal that is transitioning through the plated, through-hole118along the transverse direction T to be reflected back to the source. To mitigate this interference, the unused portions128of each respective via110a-bcan be removed. Referring toFIGS. 3A-4B, the unused portion128can be removed using, for example, a circular drill bit with a diameter H attached to a drill.

Referring toFIGS. 3A-4B, the drill may be used to back drill the PCB100. For instance, the drill may be inserted along the upward direction to a depth such that most, for instance all, of the unused portion128of each respective via110a-bis removed. For example, when inserted along the upward direction, the drill may be stopped at a location below the signal layer108. Referring toFIGS. 2A-Band4A-B, the drill may also remove a portion of each of the conductive regions107of the conductive layers102g-i. Referring also toFIGS. 1A-Band3A-B, the drill may also remove a portion of each of the antipads124g-lof the conductive layers102g-i.

Referring again toFIGS. 3A-4B, the PCB100′ and the PCB100″ can include a single back drilled cavity130that can be created as result of the back drilling described above. The cavity130can have a circular cross section as viewed along the transverse direction. The circular cross section of the cavity130can define a diameter H that is substantially equal to the diameter H of the drill bit. During the back drilling process, a part of the unused portions128of each of the vias110a-band portions of each of the conductive layers102g-imay be removed. In order to avoid damaging the traces134a-bin the signal layer108b, a small section of the unused portion128may remain in the dielectric or electrically insulative layer104fthat is disposed between the conductive layers102fand102galong the transverse direction T. Referring toFIGS. 2A and 4A, enough of the unused portion128may be removed such that the conductive regions107of the conductive layers102g-iare not electrically connected to either of the vias110a-b. After back drilling, in accordance with an example embodiment, at least a portion, for instance all, of the cavity130can be filled, for instance back-filled, with a dielectric material, for instance a dielectric material other than air. The cavity130can be filled with the same dielectric material that is included in the dielectric layers104, such as a plastic or an epoxy for example.

In accordance with the illustrated embodiments, the cavity130can be located below the signal layer108balong the downward direction that extends from the layer102atoward the layer102i. For example, the cavity130may extend between the dielectric or electrically insulative layer104fand the conductive layer102ialong the transverse direction T. The cavity130any be consist of any dielectric or electrically insulative material, for instance air, as desired. For instance, after the cavity130is back-drilled, the cavity can be at least partially filled with a dielectric material other than air.

Thus, in accordance with the an example embodiment, a printed circuit board can include a first electrically conductive layer that includes a first electrically conductive region and a first antipad defined by the first electrically conductive region. The first antipad can include a first dielectric region and a portion of an electrically plated via that extends through the first dielectric region along a first direction. The first dielectric layer can be disposed below the first electrically conductive layer along the first direction. The printed circuit board can further include a second electrically conductive layer disposed below the first dielectric layer along the first direction. The second electrically conductive layer can include at least a portion of a back-drilled cavity that is aligned with the portion of the electrically plated via along the first direction. Further, the back-drilled cavity can be at least partially filled with a dielectric material other than air.

With particular reference toFIGS. 3A-B, after the unused portions128of the vias110a-bare removed and the cavity130is created, in accordance with the illustrated embodiment, the cross-sectional dimensions C and C′ of the antipads124g-lcan be larger than the diameter H of the cavity130. Thus, the size of the antipads124g-lmay remain unchanged after back drilling. Further, select conductive regions107, for instance the second and third electrically conductive regions, of the conductive layers102g-ido not come into contact with the single back drilled cavity130in accordance with the illustrated embodiment shown inFIGS. 3A-B. After back drilling, each of the antipads124g-lcan include respective portions of the cavity130, for instance instead of the vias110a-b. Referring toFIGS. 3A-B, after back drilling, the antipads124g-lcan include respective portions of the dielectric region126and respective portions of the cavity130. Stated another way, the diameter H of the drill bit used to remove the unused portion128may be smaller than the cross-sectional dimensions C and C′ of the antipads124g-l. In an example embodiment, the cross-sectional dimensions C and C′ of the antipads124g-lmay be predetermined to be slightly greater than the diameter H of the drill used to remove the unused portions128. Thus, the second antipad, for instance a select one of the antipads124g-r, and a third antipad, for instance a select one of the antipads124h-i,124k-l,124n-o, and124q-r, can be least partially defined by the single back drilled cavity130that extends at least from the second antipad to the third antipad along the transverse direction T.

Referring toFIGS. 4A-B, the diameter H of the drill may be larger than the cross-section dimensions F and F′ of the antipads124m-r. Thus, when the unused portions128of vias110a-bare removed, the section of the conductive layers102g-iand the dielectric layers104f-hcan be removed to create the cavity130having the diameter H. Due to back drilling the PCB100″, for instance, the antipads124m-rcan have the cross-sectional dimension H that is measured from opposed sides of the cavity130along a direction that is perpendicular to the transverse direction T, and antipads124m-rcan have the cross-section dimension H that is increased from the cross-section dimensions F and F′. Thus, the maximum area of the antipads124m-ralong respective planes that are normal to the transverse direction T can also be increased by back drilling the PCB100″. By removing the unused portion128and the section of conductive layers102g-i, in particular sections of the conductive regions107of the conductive layers102g-i, the conductive regions107of the conductive layers102g-iare electrically separate from the vias110a-b. Further, select conductive regions107, for instance the second and third electrically conductive regions, of the conductive layers102g-icome into contact with the single back drilled cavity130in accordance with the illustrated embodiment shown inFIGS. 4A-B.

Referring toFIGS. 3A-B, a select two conductive regions, for instance the conductive regions107of the conductive layers102g-i, do not come into contact with the single back drilled cavity130. Alternatively, referring toFIGS. 4A-B, another select two conductive regions, for instance the conductive regions107of conductive layers102g-iofFIG. 4A, come into contact with the back drilled cavity130.

Referring generally toFIGS. 1A-4B, the vias110a-bmay be elongate along the transverse direction T and the vias110a-bcan be cylindrical. In accordance with the illustrated embodiments, the via110acan be centered around a first center line132athat extends along the transverse direction T, and the via110bcan be centered around a second centerline132bthat extends along the transverse direction T. For instance, the vias110a-bcan define respective cylinders that define the centerlines132a-b. In accordance with the illustrated embodiment, the centerline132acan extend through respective centers of select antipads124, for instance the second and the third antipads, and the centerline132bcan extend through respective centers of select antipads124, for instance the fourth and the fifth antipads, along the transverse direction T. At least a portion, for instance all, of the antipads124g-rcan be aligned with the respective vias110a-bsuch that the respective centerlines132pass through the antipads124g-ralong the transverse direction T. For instance, the antipads124g-iand124m-ocan be aligned with the via110aalong the transverse direction T such the center line132passes through a respective center of the antipads124g-iand124m-oalong the transverse direction T. Similarly, the antipads124j-land124p-rcan be aligned with the via110balong the transverse direction T such that the center line132bpasses through a respective center of the antipads124j-land124p-ralong the transverse direction T. In accordance with the illustrated embodiments, when the unused portions128of the vias110a-bare removed by back drilling, the drill bit may be inserted along the center lines132a-balong the transverse direction, which can result in at least a portion, for instance all, of the cavities130being aligned with the vias110a-balong the transverse direction T. For instance, the cavity130can be aligned with the respective vias110a-bsuch that the respective center line132a-bpasses through a respective center of the cavity130along the transverse direction T.

Without being bound by theory, by minimizing the size of the antipads124g-r, as depicted inFIGS. 3A-4B, the amount of layer-to-layer cross talk can be reduced. Further, the layer-to-layer cross talk can be reduced by the antipads124g-rassuming cylindrical shapes with circular cross-sectional areas along respective planes that are normal to the transverse direction T, while the antipads124a-ecan be rectangular shaped.

Referring toFIGS. 5A-B, a PCB200can include at least three planar conductive layers202such as electrically conductive layers202a-c. In accordance with the illustrated embodiment, the planar conductive layers202a-ccan each define a thickness in the transverse direction T. The conductive layers202a-ccan be spaced from each other along the transverse direction T. For instance, in accordance with the illustrated embodiment, the conductive layer202bis in between the conductive layers202aand202calong the transverse direction T, and the conductive layers202aand202ccan be referred to as a top layer202aand a bottom layer202c, respectively. Because no other conductive layer is placed between the conductive layers202a-calong the transverse direction T, the conductive layers202a-cmay also be referred to as consecutive conductive layers202a-c. The conductive layer202bcan be configured as a ground layer206band the conductive layers202aand202ccan be configured as signal layers206aand206c, respectively. Thus, the conductive layer202bcan include conductive regions207and one more antipads210. The conductive layers can also be configured as power layers as desired.

The signal layers206aand206ccan each include one or more conductive traces208. In accordance with the illustrated embodiment, the signal layer206aincludes a first differential pair208aof electrical signal traces, and the signal layer206cincludes a second differential pair208bof electrical signal traces. Each of the differential pairs208a-bof signal traces includes two conductive traces208that are elongate in the longitudinal direction L and spaced from each other along the lateral direction A. The conductive traces208can be made of copper or any other electrically conductive material as desired. The first differential pair208aof electrical signal traces can define a first centerline216acentrally disposed between the electrical signal traces208of the first differential signal pair208a. The second differential pair208bof electrical signal traces can define a second centerline216bcentrally disposed between the electrical signal traces208of the second differential signal pair208b.

The PCB200can further include one or more dielectric or electrically insulative layers204, for instance dielectric layers204a-b, that are located between the conductive layers202a-calong the transverse direction T. In accordance with the illustrated embodiment, the dielectric layer204ais located between the signal layer206aand the ground layer206balong the transverse direction T, and the dielectric layer204bis located between the signal layer206cand the ground layer206balong the transverse direction T. The ground layer206bmay include the conductive region207that consists of conductive material such as copper. The dielectric layers204a-bmay include substrate material such as plastic.

The PCB200, and in particular the electrically conductive layer202b, may further include antipads210arranged in a first row R1along the longitudinal direction L. The PCB200may further include antipads210arranged in a second row R2along that longitudinal direction L. The first row R1can be spaced from the second row R2a second distance D2along the lateral direction A. In accordance with the illustrated embodiment, the antipads210can define a rectangular shape, although it will be understood that the antipads can be alternatively shaped as desired. The PCB200can further include ground vias212that are disposed between antipads210along the longitudinal direction L. For instance, in accordance with the illustrated embodiment, one ground via is disposed between each pair of adjacent antipads210along the row R1and one ground via is disposed between each pair of adjacent antipads210along the row R2, although it will be understood that any number of ground vias can be alternatively located as desired. While not shown inFIGS. 5A and 5B, the antipads210can include one or more signal vias.

With continuing reference toFIGS. 5A-B, the differential signal pair208acan define an edge214athat is proximate to the first row R1along the lateral direction A. For instance, the edge214acan be a third distance D3from a select one of the antipads210in the first row R1as measured in a straight line along the lateral direction A. The differential signal pair208acan further define an edge215athat is opposite the edge214aand that is proximate to the second row R2along the lateral direction A. The edge215athat is opposite the edge214acan be a fourth distance from a select one of the antipads210in the second row R2as measured in a straight line along the lateral direction A. The edge214acan be spaced from the opposed edge215aa first distance D1a. The sum of the third distance D3, the first distance D1a, and the fourth distance D4may equal the second distance D2.

The differential signal pair208bcan define an edge214bthat is proximate to the first row R1along the lateral direction A. For instance, the edge214bcan be a fifth distance D5from a select one of the antipads210in the first row R1as measured in a straight line along the lateral direction A. The differential signal pair208bcan further define an edge215bthat is opposite the edge214band that is proximate to the second row R2along the lateral direction A. The edge215bthat is opposite the edge214bcan be a sixth distance D6from a select one of the antipads210in the second row R2as measured in a straight line along the lateral direction A. The edge214bcan be spaced from the opposed edge215ba first distance D1bthat can be substantially equal to the first distance D1a. Thus, the electrical signal traces208of the first differential pair208aof signal traces can be spaced apart from each other a first distance D1aalong the second or lateral direction A, wherein the first distance can be substantially equal to a distance that the electrical signal traces208in the second differential pair208bof signal traces are spaced apart from each other in the lateral direction A. The sum of the fifth distance D5, the first distance D1b, and the sixth distance D6can equal the second distance D2.

In accordance with the illustrated embodiment, the third distance D3may be substantially equal to the sixth distance D6. Thus, the PCB200can include the electrically conductive layer202bdisposed between the first differential signal pair208aand the second differential signal pair208balong the transverse direction T, and the electrically conductive layer202bcan further include the electrically conductive region207and one more antipads210, for instance first and second antipads210, that are defined by the electrically conductive region207. For instance, the first antipad210can be disposed in the first row R1and the second antipad210can be disposed in the second row R2. Thus, the first and second antipads210can be spaced from each other along the lateral direction A that is perpendicular to the transverse direction T. In accordance with the illustrated embodiment, each of the first and second differential pairs208aand208bcan be disposed between the first and second antipads210with respect to the lateral direction A. Further, in accordance with the illustrated embodiment, the first centerline216acan be disposed closer to the first antipad210than the second antipad210along the lateral direction A, and the second centerline216bcan disposed closer to the second antipad210than the first antipad210along the lateral direction A. Thus, the fourth distance D4can be greater than the sixth distance D6. Further, the fifth distance D5can be greater than the third distance D3.

With continuing reference toFIGS. 5A-B, a portion of the first differential pair208aof electrical signal traces can be aligned with a portion of the second differential pair208bof electrical signal traces along the transverse direction T. For instance, the fourth distance D4may be substantially equal to the fifth distance D5such that a portion of the first differential pair208is aligned with a portion of the second differential pair208balong the transverse direction T. Similarly, the third distance D3can be substantially equal to the sixth distance D6such that a portion of the first differential pair208is aligned with a portion of the second differential pair208balong the transverse direction T. For instance, portions of the differential signal pairs208a-bcan aligned along the transverse direction T such that a distance between the edge215aand the edge214bis less than the first distances D1aand D1b.

The first centerline216acan be disposed closer to the antipads210in the first row R1than the antipads210in the second row R2, and the second centerline216bcan be disposed closer to the antipads210in the second row R2than the antipads210in the first row R2by selecting appropriate values for the distances D3, D4, D5, and D6. For example, as depicted inFIG. 5B, the distance D3is less than the distance D5and the distance D4is greater than the distance D6, which can result in the edges214aand214bbeing offset (spaced) from one another along the lateral direction A. WhileFIG. 5Bdepicts one example, it should be appreciated that a wide variety of values can be assigned to the distances D3, D4, D5, and D6to result in the first centerline216abeing disposed closer to the first row R1than the second row R2along the lateral direction A, and the second centerline216bbeing disposed closer to the second row R2than the first row R1along the lateral direction A.

Without being bound by theory, by spacing the centerlines216aand216bwith respect to each other along the lateral direction A, it may be possible to reduce electromagnetic interference, such as cross talk, between the signal pairs208aand208b. This may be accomplished by preventing or reducing the alignment of the magnetic field of the signal pair208awith the magnetic field of the signal pair208b. Additionally, as magnetic fields are circular, the magnetic wave generated by, for example, the edge214awould have to travel in a large circular path in order to reach the edge215a. This may increase the electrical distance magnetic waves would have to travel, thus making those waves reaching the edge215weaker. Further, the larger the circular path becomes, the higher the likelihood magnetic waves impact another ground layer, which may be disposed below the signal pair208aalong the transverse direction T, and become absorbed. The above also applies to the magnetic waves from the signal pair208bto the signal pair208a

In accordance with one embodiment, a method can be provided for reducing layer-to-layer crosstalk. The method can include the step of providing or teaching the use of a PCB, such as either of PCB100′ or PCB100″ as described in connection withFIGS. 1A-2B. The method may further include the teaching the step of back drilling, as described above in connection withFIGS. 3A through 4B, the PCB along an upward direction so as to remove at least a portion of the electrically conductive material. The method may further include selling to the third party the printed circuit board.

In accordance with one embodiment, a method can be provided for reducing layer-to-layer crosstalk. The method can include the step of providing or teaching to a third party the use of a PCB board comprising a first electrically conductive layer that includes a first electrically conductive region and a first antipad defined by the first electrically conductive region, the first antipad including a first dielectric region and a portion of a first electrically plated via that extends through the first dielectric region along a first direction, the first antipad having a first maximum area along a first plane that is normal to the first direction, wherein the first dielectric region is aligned with the first electrically conductive region along the first plane. The method can further include the step of providing or teaching to a third party the use of the PCB board that further includes a second electrically conductive layer disposed below the first dielectric layer along the first direction, the second electrically conductive layer including a second electrically conductive region and a second antipad defined by the second electrically conductive region, the second antipad having a second maximum area along a second plane that is normal to the first direction, the second maximum area less than the first maximum area. The method may further include teaching the step to the third party of applying a first differential pair of electrical signal traces and a second differential pair of electrical signal traces to opposed sides of an electrically conductive ground layer, wherein the first differential pair of electrical signal traces is disposed closer to the first antipad than the second antipad along a second direction that is perpendicular to the first direction, wherein the second differential pair of electrical signal traces is disposed closer to the second antipad than the first antipad along the second direction, and wherein each of the first and second differential pairs is disposed between the first and second antipads. The method may also include selling the PCB board to the third party or purchasing the PCB board, which may include the first and the second differential pairs of signal traces, from the third party.

The embodiments described in connection with the illustrated embodiments have been presented by way of illustration, and the present invention is therefore not intended to be limited to the disclosed embodiments. Furthermore, the structure and features of each of the embodiments described above can be applied to the other embodiments described herein, unless otherwise indicated. Accordingly, the invention is intended to encompass all modifications and alternative arrangements included within the spirit and scope of the invention, for instance as set forth by the appended claims.