Extended protection for embedded erase of non-volatile memory cells

Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (VCHK) level and an additional embedded erase cycle is performed if any NVM cells are found to exceed the threshold voltage (Vt) check voltage (VCHK) level. The threshold voltage (Vt) check voltage (VCHK) level can be, for example, a voltage level that is slightly higher than an erase verify voltage (VEV) level and lower than read voltage level (VR).

TECHNICAL FIELD

This technical field relates to non-volatile memory (NVM) systems and, more particularly, to embedded erase operations for NVM cells within NVM systems.

BACKGROUND

Non-volatile memory (NVM) systems including arrays of NVM cells are used in a variety of electronic systems and devices. During the operation of an NVM system, NVM cells are often erased using an embedded erase process that includes a number of steps. Certain events during embedded erase operations, such as brown-out events and/or cells that are slow to erase, can leave a portion of the NVM cells in charge states that can cause problems in subsequent operations for the NVM system.

FIG. 1(Prior Art) is a flow diagram of an embodiment100for an embedded erase operation for NVM cells within an NVM array for an NVM system. The embedded erase operation starts in block102and proceeds to block104where a determination is made whether column leakage currents for the NVM array are below a predetermined threshold. If “NO,” then flow passes directly to erase verify determination block110. If “YES,” then flow passes to block106where a program verify determination is made. The program verify determination in block106determines whether the threshold voltage levels for the NVM cells exceed a program verify voltage level. If “YES,” then flow passes to block110. If “NO,” then flow passes to block108where a pre-program pulse is applied to the NVM cells that failed program verify. The pre-program pulse adds charge to the charge storage layers within the NVM cells. Flow then passes to block110, or if desired, flow can pass back to determination block106wherein a program verify determination is again made. Once determination block110is reached, an erase verify determination is performed. The erase verify determination in block110determines whether the threshold voltage levels for the NVM cells fall below an erase verify voltage level. If “YES,” then flow passes to determination block114. If “NO,” then flow passes to erase block112where an erase pulse is applied to all the NVM cells in the array. The erase pulse removes charge from the charge storage layers within the NVM cells. Flow then passes back to determination block110wherein an erase verify determination is again made. Once determination block114is reached, a soft program verify operation is performed. The soft program verify determination in block114determines whether the threshold voltage levels for the NVM cells exceed a soft program verify voltage level. If “NO,” then flow passes to soft program block116where a soft program pulse is applied to the NVM cells that failed soft program verify. The soft program pulse adds charge to the charge storage layers within the NVM cells using weaker bias voltage than program pulse. Flow then passes back to determination block114wherein a soft program verify determination is again made. Once all cells pass the soft program verify in determination block114and the determination is “YES,” then flow passes to block118where the embedded erase process finishes.

For the embedded erase embodiment100, therefore, after all the cells pass erase verify in block114, soft program pulses will be applied in block116if any of the cells fall below the soft program verify voltage. If any cell then still fails soft program verify in block114, soft program pulses will again be applied to the failing cells in block116, and this will continue until all cells pass soft program verify in block114. Once all cells pass, embedded erase is done and block118is reached. In some cases, however, a large number of soft program pulses may be required before block118is reached. For example, a large number of over-erased cells can exist that require extensive soft program pulses before all cells are recovered and pass the soft program verify determination in block114. A large number of over-erased cells can occur, for example, when embedded erase operations are interrupted (e.g., by a brown-out) before the soft program operation in blocks114and116completes. Further, a large number of over-erased cells can be generated where intermittent slow erase cells lead to a large number of additional erase pulses being applied to the NVM cells before all cells will pass the erase verify determination in block110. Using large numbers of soft programming pulses to satisfy soft programming verify in block114, however, can lead to disturbed or over-soft-programmed cells that have threshold voltage levels that significantly exceed the erase verify level and hence have less normal read margin. Such disturbed or over-soft-programmed cells can lead to latent read failures and induce potential reliability issues.

FIG. 2(Prior Art) is a probability distribution diagram of an embodiment200for threshold voltages of the NVM cells having a large number of over-erased cells. The x-axis204represents threshold voltage (Vt), and the y-axis202represents numbers of cells at the threshold voltage levels. Curve214represents a probability distribution curve for cells within an NVM cell array where a large portion216of the cells are over-erased and have threshold voltages that fall below the soft program verify voltage (VSPV) level206. It is noted that voltage level206represents a soft-program verify voltage (VSPV) level used during soft-program verify operations. Voltage level208represents an erase verify voltage (VEV) level used during erase verify operations. Voltage level212represents a program verify voltage (VPV) level used during pre-program verify operations. And voltage level210represents a read voltage level (VR) used during read operations. For read operations, if the threshold voltage level of the accessed cell is above the read gate bias voltage (VR)210, the NVM cell is determined to be programmed (e.g., logic 0). If the threshold voltage level of the accessed cell is below the read gate bias voltage (VR)210, the NVM cell is determined to be erased (e.g., logic 1).

FIG. 3(Prior Art) is a probability distribution diagram of an embodiment300for threshold voltages of the NVM cells having disturbed or over-soft-programmed cells after soft program operation has been performed on the cell distribution of embodiment200. In particular, as shown in embodiment300, soft program operations have adjusted the threshold voltages for the NVM cells such that the prior distribution curve214has been adjusted to new distribution curve302. All of the cells now have threshold voltage levels that exceed the soft program verify voltage (VSPV) level206. As such, the cells will pass soft program verify in determination block114described above. However, as also described above, when a large number of soft program pulses are utilized to move the voltage distribution curve214so that all cells will rise above the soft program verify voltage (VSPV) level206, a number of disturbed or over-soft-programmed cells304can be generated that have threshold voltages that exceed the erase verify voltage (VEV) level208. These cells with elevated threshold voltages above the erase verify voltage (VEV) level decrease read margin and induce potential read failures. Further, some of these disturbed or over-soft-programmed cells304can also have threshold voltages that extend above the read voltage (VR) level210thus induce read error, as well.

DETAILED DESCRIPTION

Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operations for embedded erase operations to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (VCHK) level and an additional embedded erase cycle is performed if NVM cells are found to exceed the threshold voltage (Vt) check voltage (VCHK) level. The threshold voltage (Vt) check voltage (VCHK) level can be, for example, a voltage level that is slightly higher than an erase verify voltage (VEV) level. After the additional embedded erase cycle (e.g., one additional pre-program, erase, and soft program operation), the NVM cells are again compared against the threshold voltage (Vt) check voltage (VCHK) level. If a second failure occurs, the embedded erase can be deemed a failure. It is noted, however, that additional embedded erase cycles could also be utilized, if desired, prior to failing the embedded erase. Different features and variations can be implemented, as desired, and modified systems and methods can be utilized, as well.

By applying of the additional threshold voltage (Vt) check during embedded erase operations, the disclosed embodiments provide extended erase protection of NVM cells by addressing potential problems generated by NVM cells having elevated threshold voltages after traditional embedded erase operations have completed. Without the additional threshold voltage (Vt) check, soft programming operations for embedded erase operations can produce NVM cells that exceed the erase verify voltage (VEV) level by a large enough amount that subsequent read failures will occur, thereby degrading the reliability of the NVM system. For example, as described above, where operational conditions have left large numbers of over-erased NVM cells, a large number of soft program pulses can be needed for the NVM cells to pass soft program verify determinations. This large number of soft program pulses can lead to disturbed or over-soft-programmed NVM cells that significantly exceed the erase verify voltage (VEV) level. As also indicated above, large numbers of over-erased NVM cells can occur where brown-out events cause soft program operations within an embedded erase to end prior to completion. In this case, in the following embedded erase operation, the column leakage verify will likely fail and erase verify will pass. Thus the embedded erase operation will proceed directly to the soft program operation with large number of over-erased NVM cells in the array. Further, one or more cells that are slow to erase can also lead to large numbers of other NVM cells becoming over-erased as more erase pulses are applied to all the NVM cells to erase the slow cells as compared to the case which has no slow to erase cells. It is a common design feature that the erase pulse is a bulk operation that is applied to all the NVM cells in the selected NVM array. Other operational events may also produce large numbers of over-erased NVM cells. The additional threshold voltage (Vt) check as described herein helps to alleviate potential reliability problems that would otherwise be created by having NVM cells with elevated threshold voltages after completion of traditional embedded erase operations.

FIG. 4is a flow diagram of an embodiment400including additional threshold voltage check protection scheme for an embedded erase operation for NVM cells within an NVM array for an NVM system. The embedded erase process starts in block102, and then block402is reached where a threshold voltage (Vt) check counter is initialized to zero (N=0). Block104is then reached. From block104to determination block114, the embodiment400is the same as embodiment100ofFIG. 1(Prior Art). However, in contrast to embodiment100, an additional threshold voltage (Vt) check operation420is conducted in embodiment400that helps to protect NVM cells from having threshold voltage levels that are too high after the soft program operation has concluded within the embedded erase steps415.

Looking in more detail to threshold voltage (Vt) check operation420, determination block404is first reached in embodiment400after all NVM cells pass the soft program verify determination in block114. In block404, a determination is made whether the threshold voltage (Vt) check process has been enabled. If “NO,” then flow passes to block118where the embedded erase operation completes. If “YES,” then flow passes to block406where the threshold voltage (Vt) for NVM cells are checked to see if they fall below a threshold voltage (Vt) check voltage (VCHK) level, as described further below. If “YES,” then flow passes to block118where the embedded erase operation ends. If “NO,” then flow passes to block408where a determination is made whether the threshold voltage (Vt) check counter (N) is already set to one (N=1) or is still set to its initial value of zero (N=0). If the threshold voltage (Vt) check counter (N) is already set to one (N=1) and the determination is “YES,” then flow passes to block412where the embedded erase operation is indicated as a failure. If the threshold voltage (Vt) check counter (N) is still set to zero (N=0) and the determination is “NO,” then flow passes to block410where the threshold voltage (Vt) check counter (N) is set to one (N=1). Flow then passes to determination block106to allow the embedded erase operation415to be repeated. It is noted that Fowler-Nordheim (FN) tunneling and hot carrier injection (HCI) techniques can be used to perform the erase and program operations for the NVM cells, respectively, if desired, although other erase and program techniques could also be utilized, if desired.

As indicated above, by applying the additional threshold voltage (Vt) check operation420during embedded erase operations and thereby giving the NVM cells a second chance of repeating the embedded erase steps415if the check fails, the disclosed embodiments provide extended erase protection of NVM cells by addressing potential problems generated by NVM cells having elevated threshold voltages after traditional embedded erase operations have completed.FIGS. 5-8provide probability distribution diagrams that show this result achieved by the additional threshold voltage (Vt) check operation420.

FIG. 5is a probability distribution diagram of an embodiment500for threshold voltages of the NVM cells where a threshold voltage (Vt) check is being applied. The x-axis204represents threshold voltage (Vt), and the y-axis202represents numbers of cells at the threshold voltage levels. As withFIG. 3(Prior Art), curve302represents a probability distribution curve for NVM cells where a number of disturbed or over-programmed cells304exist that exceed the erase verify voltage (VEV) level208and some of which also exceed the read verify voltage (VR)210. Also as withFIG. 3(Prior Art), embodiment500shows the soft-program verify voltage (VSPV) level206, the erase verify voltage (VEV) level208, and the program verify voltage (VPV) level212. In contrast with prior solutions, however, a threshold voltage (Vt) check voltage (VCHK) level502is being used to check the threshold voltage (Vt) levels of the NVM cells after soft program operation has completed. The threshold voltage (Vt) check voltage (VCHK) level502is higher than the erase verify voltage (VEV) level208and lower than the read verify voltage (VR) level210. For example, threshold voltage (Vt) check voltage (VCHK) level502can be about 200 millivolts (mV) or less above the erase verify voltage (VEV) level208. This threshold voltage (Vt) check voltage (VCHK) level502can be adjusted higher or lower, if desired, as represented by arrows504and506.

In operation, as described above with respect to embodiment400ofFIG. 4, if there are NVM cells having a threshold voltage (Vt) above the threshold voltage (Vt) check voltage (VCHK) level502, the additional threshold voltage (Vt) check operation will fail and the embedded erase steps (e.g., pre-program, erase, soft program) will be repeated once (i.e., until N=1) in order to adjust these cell threshold voltage levels. As shown in embodiment500, there are a portion304of the NVM cells with elevated voltages that have threshold voltage (Vt) levels above the threshold voltage (Vt) check voltage level502. As such, the embedded erase steps will be repeated as shown with respect toFIGS. 6-8.

FIG. 6is a probability distribution diagram of an embodiment600for threshold voltages of the NVM cells where pre-program operation has been performed on the cell distribution of embodiment500. In particular, as shown in embodiment600, pre-program operation has adjusted the threshold voltages for the NVM cells such that the prior distribution curve302has been adjusted to new distribution curve602. All of the cells now have threshold voltage levels that exceed the program verify voltage (VPV) level212. As such, the cells will pass the program verify determination step106described above, and erase pulse will then be applied as the voltage levels for the cells exceed the erase verify voltage (VEV) level208.

FIG. 7is a probability distribution diagram of an embodiment700for threshold voltages of the NVM cells where an erase operation has been performed on the cell distribution of embodiment600. In particular, as shown in embodiment700, the erase operation has adjusted the threshold voltages for the NVM cells such that the prior distribution curve602has been adjusted to new distribution curve702. All of the cells now have threshold voltage levels that are below the erase verify voltage (VEV) level208. As such, the cells will pass the erase verify determination step110described above. However, a portion704of the cells have voltage levels below the soft program verify voltage (VSPV) level206. As such, soft program operation will then be performed. It is noted that, as compared to the distribution curve214inFIG. 2(Prior Art) with a large number of over-erased cells, the number of cells on curve702having voltage levels below the soft program verify voltage (VSPV) level206is much less (i.e., a much smaller number of over-erased cells). Thus the number of soft program pulses required to move the over-erased cells above soft program verify voltage (VSPV) level206on curve702will be much less, and the probability of producing disturbed or over-soft-programmed cells with threshold voltage above the erase verify voltage (VEV) level208after soft program operation is much reduced.

FIG. 8is a probability distribution diagram of an embodiment800for threshold voltages of the NVM cells where soft program operation has been performed on the cell distribution of embodiment700. In particular, as shown in embodiment800, soft program operation has adjusted the threshold voltages for the NVM cells such that the prior distribution curve702has been adjusted to new distribution curve802. All of the cells now have threshold voltage levels that are above the soft program verify voltage (VSPV) level206but still below the threshold voltage (Vt) check voltage (VCHK) level502. As such, the NVM cells will pass the soft program verify determination step114, and the NVM cells will also pass the threshold voltage (Vt) check406. The embedded erase process will then pass to finish block118as shown inFIG. 4.

It is noted that resulting distribution curve802does show NVM cells above the erase verify voltage (VEV)208. Preferably, all of the NVM cells will have threshold voltage levels that are below the erase verify voltage (VEV)208. However, if some threshold voltage levels exceed the erase verify voltage (VEV)208by a relatively small amount, subsequent read errors are unlikely to occur. As indicated above, the threshold voltage (Vt) check voltage (VCHK) level502can be set relatively close to the erase verify voltage (VEV)208, such as within about 200 mV. Further, as described above, the threshold voltage (Vt) check voltage (VCHK) level502can be adjusted higher or lower depending upon what voltage level is desired for triggering a failure of the threshold voltage (Vt) check determination in block406. For example, the threshold voltage (Vt) check voltage (VCHK) level502could be set as low as the erase verify voltage (VEV)208, and the threshold voltage (Vt) check voltage (VCHK) level502could be set as high as the read voltage (VR) level, if desired. Other settings could also be utilized, as desired.

FIG. 9is a flow diagram for a further embodiment where a check is made concerning a number of failing cells prior to failing the embedded erase due to a failure of the threshold voltage (Vt) check determination in block406. Looking back to embodiment400ofFIG. 4, it is seen that the process will pass along path409to fail block412if there are still NVM cells having threshold voltages above the threshold voltage (Vt) check voltage (VCHK) level502. However, with embodiment900, path409first passes to block902where a number of failing cells is determined. Next, in block904, this number of failing cells is compared against a predetermined threshold value to see if the number of failing cells exceeds this threshold value. If “NO,” then flow passes to block118where the embedded erase is completed without indicating a failure. If “YES,” then flow passes to block412where a failure is indicated for the embedded erase. The threshold value can be selected, for example, based upon a number of cells that can be corrected using error correction code (ECC) routines or other data correction processing available with respect to the NVM system. The embodiment900thereby allows for NVM system to successfully complete an embedded erase where potential read errors from elevated NVM cells would be correctable through subsequent error correction processing for the NVM system.

As described above, various voltage levels are utilized during NVM operations to compare against threshold voltage levels for NVM cells. For example, an erase verify voltage (VEV) level208, a read verify voltage (VR)210, a program verify voltage (VPV) level212, a soft-program verify voltage (VSPV) level214, and a threshold voltage (Vt) check voltage (VCHK) level502are utilized. TABLE 1 below provides examples voltages that can be utilized for these voltage levels, although different voltage levels could also be utilized, if desired.

Now looking toFIG. 10andFIG. 11, connections to NVM cells and an NVM system are shown, respectively, that can take advantage of the additional threshold voltage (Vt) check operation embodiments described herein.

FIG. 10is a connection diagram of an example embodiment1000for connections to an NVM cell1110. During an operation, the NVM memory cell1110has its body (B)1136connected to a body bias voltage (VB) and has its source (S)1132connect to a source bias voltage (VS), for example, as provided by the bias voltage generator1150as described below. The NVM cell1110has its drain (D)1134coupled to the column logic1116through one of the bit-line connections1128to receive a drain bias voltage (VD). The NVM cell1110has its gate (G)1130coupled to the row decoder1118through one of the connections1126to receive a gate bias voltage (VG). Depending upon the operation to be performed for the NVM memory cells1104, different body, source, drain, and gate bias voltages (VB, VS, VD, VG) are applied to the body (B) nodes1136, source (S) nodes1132, drain (D) nodes1134, and gate (G) nodes1130for selected NVM memory cells1106. For the embodiment depicted, NVM cell1110is a floating gate type NVM memory cell. For a floating gate NVM cell, a control gate, a dielectric layer, a floating gate, and a tunnel dielectric layer will typically be located below the gate (G) node1130(e.g., gate electrode) and above the channel region within the semiconductor substrate upon which the floating gate NVM cell is fabricated. It is noted that other NVM cell types could also be utilized, such as split-gate NVM cells, multi-level NVM cells, and/or other types of NVM cells, if desired.

FIG. 11is a block diagram of an integrated circuit1100including a non-volatile memory (NVM) system1102having an additional threshold voltage (Vt) check operation as described herein. For the embodiment depicted, the NVM controller1120utilizes the threshold voltage (Vt) check block1124to provide additional protection for NVM cells during embedded erase operations. The NVM controller1120utilizes the embedded erase block1122to perform NVM embedded erase operations. As also depicted, the NVM system1102and one or more processor(s)1108are coupled to a communication bus1117through connections1113and1115, respectively. The NVM system1102also includes an NVM controller1120, a row decoder1118, column logic1116, a bias voltage generator1150, and an NVM cell array1104. As further depicted, the NVM cell array1104includes a plurality of NVM cells1106. Memory cell1110represents one of the plurality of NVM memory cells1106.

It is noted that the NVM system1102can be integrated within a single integrated circuit with the one or more processors1108, can be implemented as stand-alone memory integrated circuit, or can be implemented in another desired configuration, as desired. It is further noted that a programmable switch and/or a programmable register can be provided within the NVM system1102to control whether or not the threshold voltage (Vt) check process is enabled or disabled. Further, it is noted that a programmable register can be used to store the check counter (N), and this programmable register can be sized based upon the check counter (N) being used. For example, if a single additional cycle is being used, then a single-bit register can be used to store the check counter (N) that can then be a “1” or a “0” to indicate whether or not an additional cycle has already been done. If further additional embedded erase cycles are being used, then the check counter (N) and the programmable register can be larger respectively.

During operation, the NVM controller1120provides row addresses to the row decoder1118through connections1129. The row decoder1118drives selected wordlines with gate bias voltages (VG)1126applied to gate nodes1130for selected row(s) of NVM cells1106within the NVM cell array1104. The NVM controller1120also provides column addresses to column logic1116through connections1127. The column logic1116drives selected bit-lines with drain bias voltages (VD)1128applied to drain nodes1134for selected column(s) of NVM cells1106within the NVM cell array1104. The column logic1116is also used to access and read stored data values from the selected NVM cells1106within the NVM cell array1104through connections1128.

The bias voltage generator1150is configured to generate a variety of bias voltages that are used for the operation of the NVM system1102. For example, the bias voltage generator1150provides gate bias voltages1151to row decoder1118that are used to apply the gate bias voltages (VG)1126. The bias voltage generator1150also provides drain bias voltages1152to column logic1116that are used to apply the drain bias voltages (VD)1128. Further, the bias voltage generator1150provides body bias voltages (VB)1123to body nodes1136for the NVM cells1106within the NVM cell array1104, and the bias voltage generator1150provides source bias voltages (VS)1125to source nodes1132for the NVM cells1106within the NVM cell array1104. The bias voltage generator1150receives bias control signals1155from the NVM controller1120that control the bias voltages that are provided by the bias voltage generator1150. It is further noted that the bias voltage generator1150can be implemented as a single circuit block or as circuit blocks distributed in different locations throughout the NVM system1102, as desired. Other variations could also be implemented, if desired.

As described herein, a variety of embodiments can be implemented and different features and variations can be implemented, as desired.

In one embodiment, a method is disclosed for erasing non-volatile memory (NVM) cells within an NVM system including performing an embedded erase operation for non-volatile memory (NVM) cells where the embedded erase operation includes erasing the NVM cells until the NVM cells have threshold voltages below an erase verify voltage level and soft programming the NVM cells until the NVM cells have threshold voltages above a soft program verify voltage level, comparing the threshold voltages for the NVM cells to a check voltage level where the check voltage level is higher than an erase verify voltage level, and repeating the performing step based upon results of the comparing step.

In other embodiments, the repeating step can include repeating the performing step if the results of the comparing step indicates that one or more of the NVM cells has a threshold voltage that exceeds the check voltage level. Further, the method can include counting a number of times the performing step is repeated, and indicating an erase failure if a maximum number of times has been reached. Still further, the performing step can be repeated only once before indicated an erase failure.

In further embodiments, before the indicating step, the method can include determining a number of NVM cells having threshold voltages that exceed the check voltage level, and indicating an erase failure if the number of NVM cells exceeds a threshold value. For another embodiment, before the erasing step, the performing step can further include pre-programming the NVM cells until the NVM cells have threshold voltages above a program verify voltage level. Also, before the comparing step, the method can further include determining whether an additional voltage check is enabled for the NVM system and skipping the comparing and repeating steps if the determining step indicates that the additional voltage check is not enabled.

In still further embodiments, the check voltage level can be larger than the erase verify voltage level by 200 millivolts or less. Also, the check voltage level can be lower than a read voltage level for the NVM system. Further, the check voltage level can be adjustable.

In another embodiment, a non-volatile memory (NVM) system is disclosed including an array of non-volatile memory (NVM) cells, and controller circuitry configured to perform an embedded erase operation for the NVM cells, to compare threshold voltages for the NVM cells to a check voltage level after the embedded erase operation, and to repeat the embedded erase operation depending upon results of the comparison, where the embedded erase operation includes an erase operation configured to cause the NVM cells to have threshold voltages below an erase verify voltage level and a soft programming operation configured to cause the NVM cells to have threshold voltages above a soft program verify voltage level, and where the check voltage level is higher than the erase verify voltage level.

In other embodiments, the controller circuitry can be configured to repeat the embedded erase operation if the results of the comparison indicate that one or more of the NVM cells has a threshold voltage that exceeds the check voltage level. Further, the controller circuitry can be further configured to count a number of times the embedded erase operation is repeated and to indicate an erase failure if a maximum number of times is reached. Still further, the maximum number of times can be one.

In further embodiments, the controller circuitry can be further configured to indicate an erase failure only if a number of NVM cells having threshold voltages that exceed the check voltage level exceeds a threshold value. For another embodiment, the embedded erase operation can further include a pre-programming operation configured to cause the NVM cells to have threshold voltages above a program verify voltage level. Also, the controller circuitry can be further configured to determine if an additional voltage check is enabled for the NVM system prior to repeating the embedded erase operation.

In still further embodiments, the check voltage level can be larger than the erase verify voltage level by 200 millivolts or less. Also, the check voltage level can be lower than a read voltage level for the NVM system. Further, the check voltage level can be adjustable.

It is noted that the functional blocks described herein can be implemented using hardware, software, or a combination of hardware and software, as desired. In addition, one or more processors running software and/or firmware can also be used, as desired, to implement the disclosed embodiments. It is further understood that one or more of the operations, tasks, functions, or methodologies described herein may be implemented, for example, as software or firmware and/or other program instructions that are embodied in one or more non-transitory tangible computer readable mediums (e.g., memory) and that are executed by one or more controllers, microcontrollers, microprocessors, hardware accelerators, and/or other processors to perform the operations and functions described herein.

Further modifications and alternative embodiments of the described systems and methods will be apparent to those skilled in the art in view of this description. It will be recognized, therefore, that the described systems and methods are not limited by these example arrangements. It is to be understood that the forms of the systems and methods herein shown and described are to be taken as example embodiments. Various changes may be made in the implementations. Thus, although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and such modifications are intended to be included within the scope of the present invention. Further, any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.