Switching regulator

A control signal generating circuit (1) comprises a comparator (10) for comparing an output voltage VO with a reference voltage outputted from a reference voltage source (11), a flipflop (12) set by the output of the comparator (10), and a pulse control circuit (13) which receives an input voltage VIN, a reference voltage VREF2, and the inverted output of the flipflop (12), sets the on time in accordance with the ratio between the input voltage VIN and the reference voltage VREF2, and resets the flipflop (12) when the on time elapses after the output pulse of the flipflop (12) rises. The output pulse of the flipflop (12) is outputted as a control signal into a driver logic circuit (2). The driver logic circuit (2) performs on/off control of NMOSs (3, 4) according to the control signal. Thus, a switching regulator capable of operating at high speed can be realized.

TECHNICAL FIELD

The present invention relates to a switching regulator.

BACKGROUND ART

In a conventional switching regulator, an error amplifier amplifies the error between a reference voltage and a voltage based on the output voltage of the switching regulator, then a PWM comparator compares the output voltage of the error amplifier with a triangular wave to generate a PWM signal, and then, based on this PWM signal, a switching device included in a DC-DC converter is turned on and off (for example, see patent document 1 listed below). Disadvantageously, however, a switching regulator configured as described above cannot operate at high speed because the error amplifier provided in the feedback section performs an amplifying operation.

A current-mode-control switching regulator is one example of a switching regulator capable of high-speed operation. In a current-mode-control switching regulator, a variable voltage that is offset according to the difference between a reference voltage and a voltage based on the output voltage of the switching regulator is compared with the voltage based on the output current thereof, then a pulse signal is generated that has a duty ratio commensurate with the comparison result, and then, based on this pulse signal, a switching device included in a DC-DC converter is turned on and off (for example, see patent document 2 listed below).Patent document 1: JP-A-2003-219638 (FIG. 1)Patent document 2: JP-A-2003-319643 (FIG. 1)

DISCLOSURE OF THE INVENTION

Problems to be Solved by the Invention

Disadvantageously, however, the current-mode-control regulator involves feedback control to generate the variable voltage that is shifted according to the difference between the reference voltage and the voltage based on the output voltage of the switching regulator, and is thus difficult to operate faster than a certain speed. For example, in the current-mode-control switching regulator disclosed in Patent Document 2, a transconductance amplifier (gm amplifier) offsets the variable voltage according to the difference between the reference voltage and the output voltage of the switching regulator, and then the gm amplifier performs an amplifying operation according to the output voltage of the switching regulator. Thus, the current-mode-control switching regulator disclosed in Patent Document 2 is difficult to operate faster than a certain speed.

In view of the disadvantages described above, it is an object of the present invention to provide a control signal generating circuit, for a switching regulator, that allows it to operate at high speed, and to provide a switching regulator that can operate at high speed.

Means for Solving the Problem

To achieve the above object, according to the present invention, a control signal generating circuit for a switching regulator is provided with: a comparator that compares a voltage based on the output voltage of the switching regulator with a reference voltage; a flipflop that is set with the output of the comparator; and a pulse control circuit that resets the flipflop when a predetermined on-period elapses after a rise of the output pulse of the flipflop. Here, the control signal generating circuit outputs the output pulse of the flipflop as the control signal for a switching device.

In a switching regulator incorporating a control signal generating circuit as described above, feedback section simply performs a comparing operation between the voltage based on the output voltage of the switching regulator and the reference voltage. This allows high-speed operation.

In the control signal generating circuit configured as described above, the pulse control circuit may include an on-period setting comparator that compares with a second reference voltage a voltage (monitored voltage) corresponding both to the period elapsed after the rise of the output pulse of the flipflop and to the input voltage of the switching regulator. In this case, the on-period may be set by resetting the flipflop with the output of the on-period setting comparator.

With this configuration, the pulse control circuit performs a comparing operation between the monitored voltage and the second reference voltage. Thus, in a switching regulator incorporating this control signal generating circuit, the feedback section mainly performs a comparing operation between the voltage based on the output voltage of the switching regulator and the reference voltage, and a comparing operation between the monitored voltage and the second reference voltage. This allows high-speed operation.

In any of the control signal generating circuits configured as described above, a maximum on-period control circuit may be further provided that sets the maximum on-period and that resets the flipflop when the maximum on-period elapses after the rise of the output pulse of the flipflop. In this case, the on-period of the output pulse of the flipflop may be limited so as not to exceed the maximum on-period.

With this configuration, the on-period of the output pulse of the flipflop is limited within the maximum on-period, and thus the on-duty of the control signal outputted from the control signal generating circuit never reaches a level where the operation of switching regulator incorporating the control signal generating circuit becomes unstable. Thus, even when the on-duty of the control signal outputted from the control signal generating circuit is close to 100%, it is possible to stabilize the operation of the switching regulator incorporating the control signal generating circuit.

In the control signal generating circuit configured as described above, which includes a maximum on-period control circuit, a reset-preventing section may be further provided that prevents the output of the pulse control circuit from resetting the flipflop if, when the predetermined on-period has elapsed after the rise of the output pulse of the flipflop, the voltage based on the output voltage of the switching regulator is lower than the reference voltage.

With this configuration, when the output voltage of the switching regulator drops, the output of the pulse control circuit is prevented from resetting the flipflop. Thus, it is possible to reduce the time required for the output voltage of the switching regulator to return to a predetermined value.

In the control signal generating circuit configured as described above, which includes a reset-preventing section, a set-preventing section may be further provided that prevents the output of the comparator from setting the flipflop after the maximum on-period has elapsed after the rise of the output pulse of the flipflop until a predetermined period further elapses.

With this configuration, even when the output voltage of the switching regulator drops, the output of the comparator is prevented from setting the flipflop after the maximum on-period has elapsed after the rise of the output pulse of the flipflop until a predetermined period further elapses. Thus, the on-duty of the control signal outputted from the control signal generating circuit never reaches a level where the operation of the switching regulator incorporating the control signal generating circuit becomes unstable. Thus, even when the on-duty of the control signal outputted from the control signal generating circuit is close to 100%, it is possible to stabilize the operation of switching regulator incorporating the control signal generating circuit.

To achieve the above object, according to the present invention, a switching regulator is provided with: a DC-DC converter; a control signal generating circuit that generates a control signal corresponding to the output voltage of the DC-DC converter; and a driver circuit that drives the switching device included in the DC-DC converter based on the control signal. Here, the control signal generating circuit is one of the control signal generating circuits configured as described above. With this configuration, it is possible to achieve high-speed operation. High-speed operation makes it possible to cope with larger currents.

In the switching regulator configured as described above, a resistor may be provided between the comparator and the output capacitor included in the DC-DC converter; or the reference voltage may vary with the output pulse of the flipflop and may be in substantially opposite phase to the output voltage of the switching regulator.

With the former configuration, even when a capacitor with a low equivalent series resistance (for example, a ceramic capacitor) is used as the output capacitor, it is possible to increase the ripple voltage of the output voltage of the switching regulator. Thus, even when a capacitor with a low equivalent series resistance (for example, a ceramic capacitor) is used as the output capacitor, it is possible to reduce the increase of the switching-delay period in the comparator, and thereby to stabilize the operation of the switching regulator. With the latter configuration, even when a capacitor with a low equivalent series resistance (for example, a ceramic capacitor) is used as the output capacitor, it is possible to stabilize the operation of the switching regulator without degrading the stability of the output voltage of the switching regulator.

Advantages of the Invention

According to the present invention, it is possible to realize a control signal generating circuit, for a switching regulator, that allows it to operate at high speed, and to realize a switching regulator that can operate at high speed.

LIST OF REFERENCE SYMBOLS

1,1′,100,200,300Control signal generating circuit

2Driver logic circuit

11Reference voltage source

13Pulse control circuit

20Off-period control circuit

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. The configuration of the switching regulator of the first embodiment of the present invention is shown inFIG. 1.

The switching regulator shown inFIG. 1is composed of a control signal generating circuit1, a driver logic circuit2, N-channel MOS transistors (hereinafter referred to as “NMOSs” or “NMOS transistors”)3and4, a Zener diode5, a capacitor6, a coil7and an output capacitor8. Here, it is assumed that the input voltage VINis higher than the drive voltage VDDthat drives the circuit included in the control signal generating circuit1. In this embodiment, it is assumed that the input voltage VINis +25V, and the drive voltage VDDis +5V. In this embodiment, the NMOSs3and4, the coil7and the output capacitor together constitute a DC-DC converter, which converts the input voltage VINinto the output voltage VO. The output voltage VOis, therefore, the output voltage of the switching regulator shown inFIG. 1and simultaneously is the output voltage of the DC-DC converter.

The control signal generating circuit1receives the output signal VO, and then generates a pulse signal (control signal) to send it to the driver logic circuit2. The driver logic circuit2turns the NMOSs3and4on and off based on the pulse signal outputted from the control signal generating circuit1.

When the NMOS3is turned off and the NMOS4is complementarily turned on, a charging current flows through a Schottky diode5into the capacitor6via the terminal thereof to which the drive voltage VDDis applied, and thereby the voltage across the capacitor6becomes about +5V. Then, when the NMOS3is turned on and the NMOS4is complementarily turned off, the voltage at the node between the capacitor6and the NMOS3becomes +25V, and the voltage at the node between the capacitor6and the Schottky diode5becomes about +30 V. Here, the voltage of about +30V appearing at the node between the capacitor6and the Schottky diode5is fed to the driver logic circuit2.

The driver logic circuit2shifts the level of the pulse signal outputted from the control signal generating circuit1to a higher potential by use of the voltage of +30V supplied via the node between the capacitor6and the Schottky diode5. Then, the driver logic circuit2feeds a first drive signal based on the level-sifted signal to the gate of the NMOS3; the driver logic circuit2also inverts the pulse signal outputted from the control signal generating circuit1to feed a second drive signal based on the inverted signal to the gate of the NMOS4.

The voltage at the node between the NMOSs3and4is smoothed out by the coil7and the output capacitor8, and thereby becomes the output voltage VO.

Now, the control signal generating circuit1, which characterizes the present invention, will be described in detail. The control signal generating circuit1is composed of a comparator10, a reference voltage source11, a flipflop12and a pulse control circuit13.

The comparator10compares the output voltage VOwith a reference voltage VREFoutputted from the reference voltage source11to feed the comparison output as a set signal to the set terminal of the flipflop12. The pulse control circuit13receives the input voltage VIN, a reference voltage VREF2and the inverted output of the flipflop12, and sets the on-period TONof the pulse signal outputted from the control signal generating circuit1according to the ratio of the input voltage VINto the reference voltage VREF2(VREF2/VIN) so as to satisfy equation (1) below. When the on-period TONelapses after a rise of the pulse signal outputted from the control signal generating circuit1, the pulse control circuit13feeds, as a reset signal for resetting the flipflop12, a signal having a frequency f to the reset terminal of the flipflop12. Then, the pulse output of the flipflop12is fed to the driver logic circuit2. The reference voltage VREF2may be set with a bandgap circuit or the like.

An example of the configuration of the control signal generating circuit1is shown inFIG. 2. It should be noted that, inFIG. 2, such parts as are found also inFIG. 1are identified with common reference numerals, and no detailed description thereof will be repeated. The pulse control circuit13included in the control signal generating circuit1shown inFIG. 2is composed of: resistors R1and R2for dividing the input voltage VIN; an NPN transistor Q3; a resistor R3through which the emitter current of the transistor Q3flows; a high-speed amplifier AMP1that amplifies and then feeds the voltage difference between the divided voltage of the input voltage VINand the voltage across the resistor R3to the base of the transistor Q3; a capacitor C1; a current mirror circuit that are composed of PNP transistors Q1and Q2and that feeds a charging current equal to or predetermined times the emitter current of the transistor Q3to the capacitor C1; an NMOS transistor Q4that switches between the charging and discharging of the capacitor C1according to the inverted output of the flipflop12; resistors R4and R5for dividing the reference voltage VREF2; and a comparator COM1that compares the divided voltage of the reference voltage VREF2with the voltage across the capacitor C1to feed the comparison output to the reset terminal of the flipflop12.

A time chart of the voltages and current observed at relevant points in the switching regulator shown inFIG. 1and in the control signal generating circuit shown inFIG. 2is shown inFIG. 3. Now, with reference toFIG. 3, the operation of the switching regulator shown inFIG. 1and of the control signal generating circuit shown inFIG. 2will be described.

When a pulse signal VQthat is fed to the driver logic circuit2from the output terminal of the flipflop12is at a low level, the NMOS3is off and the NMOS4is complementarily on, and therefore a current ILthat flows through the coil7and the output voltage VOboth gradually decrease. At this time, the inverted output of the flipflop12is at a high level so that the NMOS transistor Q4is on and the voltage VC1across the capacitor C1is zero. Thus, a reset signal VRthat is fed to the reset terminal of the flipflop12from the comparator COM1is at a low level.

Then, when the output voltage VObecomes lower than the reference voltage VREF, a set signal VSthat is fed to the set terminal of the flipflop12from the comparator10turns from low to high. This causes the pulse signal VQto turn from low to high, and thus the NMOS3turns on and the NMOS4complementarily turns off. Thus, the output voltage VObecomes higher than the reference voltage VREFso that the set signal VSreturns to a low level immediately. At this time, the inverted output of the flipflop12turns from high to low, and thus NMOS transistor Q4turns off to start to feed the charging current to the capacitor C1.

While the pulse signal VQserving as the output of the flipflop12is at a high level, the current ILthat flows through the coil7, the output voltage VOand the voltage VC1across the capacitor C1all gradually increase.

Then, when the voltage VC1across the capacitor C1reaches a threshold VTH(a voltage equal to the voltage at the node between resistors R4and R5), the reset signal VRturns from low to high. This causes the pulse signal VQto turn from high to low. When the pulse signal VQbecomes low, the inverted output of the flipflop12becomes high. Thus, the NMOS transistor Q4turns on, and the voltage VC1across the capacitor C1becomes zero so that the reset signal VRreturns to a low level immediately.

Since the switching regulator shown inFIG. 1and the control signal generating circuit shown inFIG. 2operate as described above, the on-period TONof the pulse signal VQcoincides with the charging period of the capacitor C1. Thus, the on-period TONof the pulse signal VQis represented by equation (2) below, where C1represents the capacitance of the capacitor C1, i represents the charge current through the capacitor C1, and R1to R5represent the resistances of the resistors R1to R5respectively. Here, these resistances fulfill R1=R4and R2=R5.

Here, if the switching regulator has a step-down DC-DC converter, the on-period TON(the period during which energy is stored in the coil included in the DC-DC converter) of the pulse signal used for turning on and off the switching device included in the DC-DC converter is represented by equation (1) above. Thus, the arithmetic product of the capacitance C1of the capacitor C1and the resistance value R3of the resistor R3equals the frequency f of the pulse signal VQ. The frequency f of the control signal VQ, therefore, remains constant even if the input voltage VINis changed.

In the switching regulator shown inFIG. 1, the feedback section mainly performs a comparing operation between the output voltage VOand the reference voltage VREF, and a comparing operation between the charging voltage VC1and the reference voltage VREF2. This allows high-speed operation.

Next, a second embodiment of the present invention will be described. The configuration of the switching regulator of the second embodiment of the present invention is shown inFIG. 4. It should be noted that, inFIG. 4, such parts as are found also inFIG. 1are identified with common reference numerals, and no detailed description thereof will be repeated.

The switching regulator shown inFIG. 4differs from that shown inFIG. 1in that the control signal generating circuit1included in the latter is replaced with a control signal generating circuit1′. As compared with the control signal generating circuit1, the control signal generating circuit1′ is additionally provided with a maximum on-period control circuit14and an OR gate15. The outputs of the pulse control circuit13and of the maximum on-period control circuit14are inputted to the OR gate15, and then the output of the OR gate15is fed as a reset signal to the reset terminal of the flipflop12.

The maximum on-period control circuit14receives the inverted output of the flipflop12, and sets a maximum on-period TMAXof the pulse signal outputted from the control signal generating circuit1′. When the maximum on-period TMAXelapses after the rise of the pulse signal outputted from the control signal generating circuit1′, the maximum on-period control circuit14outputs a signal to reset the flipflop12.

The OR gate15calculates the OR between the outputs of the pulse control circuit13and the maximum on-period control circuit14to feed the result as a reset signal to the reset terminal of the flipflop12. Thus, it is possible to limit the on-period TONof the pulse signal outputted from the control signal generating circuit1so that it does not exceed the maximum on-period TMAX.

An example of the configuration of the control signal generating circuit1′ is shown inFIG. 5. It should be noted that, inFIG. 5, such parts as are found also inFIG. 2are identified with common reference numerals, and no detailed description thereof will be repeated. The maximum on-period control circuit14included in the control signal generating circuit1′ shown inFIG. 5is composed of: a first reference voltage source REF1for outputting a first reference voltage VREF1; an NPN transistor Q7; a resistor R6through which the emitter current of the transistor Q7flows; an amplifier AMP2that amplifies and then feeds the voltage difference between the first reference voltage VREF1and the voltage across the resistor R6to the base of the transistor Q7; a capacitor C2; a current mirror circuit that is composed of PNP transistors Q5and Q6and that feeds a charging current equal to or predetermined times the emitter current of the transistor Q7to the capacitor C2; an NMOS transistor Q8that switches between the charging and discharging of the capacitor C2according to the inverted output of the flipflop12; a second reference voltage source REF3for outputting a second reference voltage VREF3; and a comparator COM2that compares the second reference voltage VREF3with the voltage across the capacitor C2to feed its comparison output to one of the input terminals of the OR gate15.

The maximum on-period control circuit14is configured as described above, and therefore the maximum on-period TMAXset by the maximum on-period control circuit14is represented by equation (3) below, where C2represents the capacitance of the capacitor C2and R6represents the resistance value of the resistor R6.

In the switching regulator of the first embodiment of the present invention shown inFIG. 1, when the input voltage VINbecomes so low that the on-duty of the pulse signal outputted from the control signal generating circuit1becomes close to 100%, the period that can be secured for the charging of the bootstrap capacitor6may become so short as to make the operation unstable. In contrast, in the switching regulator of the second embodiment of the present invention described above and shown inFIG. 4, by limiting the on-period TONof the pulse signal outputted from the control signal generating circuit1′ so that it does not exceed the maximum on-period TMAX, it is possible to secure a sufficient period for the charging of the bootstrap capacitor6. This makes it possible to stabilize the operation even when the duty ratio is close to 100%.

Next, a third embodiment of the present invention will be described. In the switching regulator described above and shown inFIG. 1, and also in the switching regulator shown inFIG. 4, the ripple voltage ΔV of the output voltage VOequals the arithmetic product of the fluctuation range ΔI of the current ILflowing through the coil7and the equivalent series resistance (hereinafter, “ESR”) of the output capacitor8. Thus, in a case where a capacitor with a low ESR (for example, a ceramic capacitor) is used as the output capacitor8, the ripple voltage ΔV of the output voltage VOmay become too small, as shown inFIG. 6. As the ripple voltage ΔV of the output voltage VObecomes small, the gradient of the output voltage VObecomes small. Thus, the switching-delay period of the comparator10(the period after the output voltage VOhas so decreased as to become equal to the reference voltage VREFuntil the output of the comparator10turns to a high level) becomes longer. Therefore, when the ripple voltage ΔV of the output voltage VObecomes too small, the operation becomes unstable.

Devised to solve this drawback, the switching regulator of the third embodiment of the present invention is configured as shown inFIG. 7. It should be noted that, inFIG. 7, such parts as are found also inFIG. 4are identified with common reference numerals, and no detailed description thereof will be repeated.

As compared with the switching regulator shown inFIG. 4, the switching regulator shown inFIG. 7is additionally provided with a resistor9. One end of the resistor9is connected to the node between the coil7and the inverting input terminal of the comparator10, and the other end of the resistor9is connected to the node between the terminal via which the output voltage VOis sent out and the output capacitor8. With this configuration, the ripple voltage ΔV of the output voltage VOequals the value calculated by multiplying the sum of the ESR of the output capacitor8and the resistance of the resistor9by the fluctuation range ΔI of the current ILflowing through the coil7. Thus, even when a capacitor with a low ESR (for example, a ceramic capacitor) is used as the output capacitor8, it is possible to increase the ripple voltage ΔV of the output voltage VOto stabilize the operation.

Although the voltage inputted to the inverting input terminal of the comparator10is the sum of the output voltage VOand the voltage across the resistor9, the sum is approximately equal to the output voltage VO. In the present specification, therefore, the output voltage VOis regarded as being inputted to the inverting input terminal of the comparator10.

Since the output current of the switching regulator flows through the resistor9, the resistor9can be used as an output-current detecting resistor.

Instead of the resistor9, an extra resistor may be provided that has one end thereof connected to the node between the coil7, the inverting input terminal of the comparator10, and the terminal via which the output voltage VOis sent out, with the other end of the extra resistor connected to the output capacitor8. Unlike the resistor9, this extra resistor cannot be used as an output-current detecting resistor.

Next, a fourth embodiment of the present invention will be described. The switching regulator of the first embodiment of the present invention described above operates such that the on-period TONof the pulse signal outputted from the control signal generating circuit1satisfies equation (1) noted earlier. Thus, when the output voltage VOdrops, it disadvantageously takes much time for the output voltage VOto return to a predetermined value. The larger the drop of the output voltage VOdrops, the longer the time the output voltage VOneeds to return to the predetermined value.

Devised to overcome this drawback, the switching regulator of the fourth embodiment of the present invention is configured as shown inFIG. 8. It should be noted that, inFIG. 8, such parts as are found also inFIG. 4are identified with common reference numerals, and no detailed description thereof will be repeated.

The switching regulator shown inFIG. 8differs from that shown inFIG. 4in that the control signal generating circuit1′ included in the latter is replaced with a control signal generating circuit100. As compared with the control signal generating circuit1′, the control signal generating circuit100is additionally provided with AND gates16and19, an OR gate17, NOT gates18and21, and an off-period control circuit20. A reset-priority flipflop is used as the flipflop12.

The output terminal of the comparator10is connected to the first input terminal of the AND gate16, and is connected to the first input terminal of the AND gate19via the NOT gate18. The output terminal of the AND gate16is connected to the set terminal of the flipflop12, and is connected to the first input terminal of the OR gate17. The output terminal of the flipflop12is connected to the second input terminal of the OR gate17, and the output terminal of the OR gate17is connected to the driver logic circuit2.

The inverting output terminal of the flipflop12is connected to the input side of the pulse control circuit13, and is connected to the input side of the maximum on-period control circuit14. The output side of the pulse control circuit13is connected to the second input terminal of the AND gate19, and the output terminal of the AND gate19is connected to the first input terminal of the OR gate15. The output side of the maximum on-period control circuit14is connected to the second input terminal of the OR gate15. The output terminal15of the OR gate15is connected to the reset terminal of the flipflop15, and is connected to the input side of the off-period control circuit20. The output side of the off-period control circuit20is connected to the second input terminal of the AND gate16via the NOT gate21.

In normal operation (when there is no drop in the output voltage VO), the control signal generating circuit100outputs a pulse signal similar to that outputted from the control signal generating circuit1′ included in the switching regulator shown inFIG. 4.

Next, how the control signal generating circuit100operates when the output voltage VOdrops will be described. When the output voltage VOdrops, the output of the comparator10becomes high and thus the output of the AND gate19becomes low. At first, the maximum on-period has not yet elapsed, and thus the output of the maximum on-period control circuit14is low. Thus, the output of the OR gate15is low, and the output of the NOT gate is high, so that the output of the AND gate becomes high. As a result, the flipflop12is set, and the pulse signal outputted from the control signal generating circuit100rises.

Then, after the on-period TONelapses after the rise of the pulse signal outputted from the control signal generating circuit100, even when the output of the pulse control circuit13becomes high, the output of the AND gate19remains low. Thus, the flipflop12is not reset. This makes it possible to shorten the time required for the output voltage VOto return to a predetermined value.

When the maximum on-period TMAXelapses after the pulse signal outputted from the control signal generating circuit100has risen, the output of the maximum on-period control circuit14becomes high and then immediately returns to a low level. This temporarily causes the output of the OR gate15to become high. Thus, the flipflop12is reset so that the pulse signal outputted from the control signal generating circuit100falls.

The off-period control circuit20keeps its output high until the minimum off-period TMINelapses after the output of the OR gate15has become high. This keeps the output of the AND gate16low after the maximum on-period TMAXelapses after the rise of the pulse signal outputted from the control signal generating circuit100until the minimum off-period TMINelapses. Thus, the flipflop12is not set. This makes it possible to secure a sufficient period for the charging of the bootstrap capacitor6.

Next, a fifth embodiment of the present invention will be described. In the switching regulator of the third embodiment of the present invention described above, it is possible to stabilize the operation thereof even when a capacitor with a low ESR (for example, a ceramic capacitor) is used as the output capacitor8. However, since the ripple voltage of the output voltage VOis then large, the output voltage VOis disadvantageously unstable.

Devised to solve this drawback, the switching regulator of the fifth embodiment of the present invention is configured as shown inFIG. 9. It should be noted that, inFIG. 9, such parts as are found also inFIG. 7are identified with common reference numerals, and no detailed description thereof will be repeated.

In the switching regulator shown inFIG. 9, as compared with that shown inFIG. 7, the control signal generating circuit1′ is replaced with a control signal generating circuit200, the resistor9is omitted, and a resistor22is added. In the control signal generating circuit200, the reference voltage source11included in the control signal generating circuit1′ is replaced with resistors11aand11b. The resistors11aand11bconstitute a serial circuit that has a constant voltage VCapplied to one end thereof and has the other end thereof grounded. The non-inverting input terminal of the comparator10is connected to the node between the resistors11aand11b, and thus the voltage at the node between the resistors11aand11bis used as the reference voltage VREF. One end of the resistor22also is connected to the node between the resistors11aand11b, and the other end of the resistor22is connected to the gate of the NMOS transistor4.

In the case of the switching regulator of the third embodiment of the present invention shown inFIG. 7, the waveforms of the output voltage VO, the reference voltage VREFand the pulse signal LG outputted to the gate of the NMOS transistor4are as shown inFIG. 10A. Thus, if the ripple voltage of the output voltage VOis not large, it is difficult for the comparator10to perform the comparing operation, leading to unstable operation of the switching regulator.

In contrast, in the case of the switching regulator of the fifth embodiment of the present invention shown inFIG. 9, the waveforms of the output voltage VO, the reference voltage VREFand the pulse signal LG outputted to the gate of the NMOS transistor4are as shown inFIG. 10B. Thus, if the ripple voltage of the output voltage VOis not large, the comparator10easily performs the comparing operation, leading to stable operation of the switching regulator. In the switching regulator of the fifth embodiment of the present invention shown inFIG. 9, therefore, even when a capacitor with a low ESR (for example, a ceramic capacitor) is used as the output capacitor8, it is possible to stabilize the operation thereof without decreasing the stability of the output voltage VO.

It should be noted that although, in the switching regulator shown inFIG. 9, the other end of the resistor22is connected to the gate of the NMOS transistor4, the present invention may be practiced with any other configuration. For example, also when the other end of the resistor22is connected to the non-inverting output terminal of the flipflop12, it is possible to obtain the same advantages as those described above. A capacitor23is provided to eliminate noise.

Next, the switching regulator of a sixth embodiment of the present invention will be described. This switching regulator offers the same advantages as those offered by the switching regulator of the fifth embodiment of the present invention.FIG. 11is a diagram showing the configuration of the switching regulator of the sixth embodiment of the present invention. It should be noted that, inFIG. 11, such parts as are found also inFIG. 9are identified with common reference numerals, and no detailed description thereof will be repeated.

In the switching regulator shown inFIG. 11, as compared with that shown inFIG. 9, the control signal generating circuit200is replaced with a control signal generating circuit300, and the resistor22is omitted. In the control signal generating circuit300, as compared with the control signal generating circuit200, the capacitor23is omitted, and a resistor24and a current source25are additionally provided. One end of the resistor24, which is as a resistance of R24, is connected to the node between the resistors11aand11b, and the other end of the resistor24is connected to the non-inverting input terminal of the comparator10and is connected to one end of the current source25. The other end of the current source25is connected to ground, and the voltage at the node between the resistor24and the current source25is used as the reference voltage VREF. The current source25is a current source that outputs a current according to a control signal. In this embodiment, the pulse signal outputted to the gate of the NMOS transistor3from the driver logic circuit2is used as the control signal of the current source25.

In the case of the switching regulator of the sixth embodiment of the present invention shown inFIG. 11, the waveforms of the voltage V11at the node between the resistors11aand11b, a pulse signal HG outputted to the gate of the NMOS transistor3from the driver logic circuit2, the output voltage VO, the output current I25of the current source25, and the reference voltage VREF(=V11−R24×I25) are as shown inFIG. 12. Thus, even if the ripple voltage of the output voltage VOis not large, the comparator10easily performs the comparing operation, leading to stable operation of the switching regulator. In the switching regulator of the sixth embodiment of the present invention shown inFIG. 11, therefore, even when a capacitor with a low ESR (for example, a ceramic capacitor) is used as the output capacitor8, it is possible to stabilize the operation thereof without decreasing the stability of the output voltage VO.

It should be noted that although, in the switching regulator shown inFIG. 11, the pulse signal HG outputted to the gate of the NMOS transistor3from the driver logic circuit2is used as the control signal for the current source25, the present invention may be practiced with any other configuration. For example, also when the signal outputted from the output terminal of the flipflop12is used as the control signal for the current source25, it is possible to obtain the same advantages as those described above.

The first to the sixth embodiments described above deal with switching regulators with a bootstrap type DC-DC converter. Needless to say, the present invention is applicable to switching regulators with any other type of DC-DC converter. In all embodiments of the present invention, instead of the Zener diode5and the capacitor6, any other configuration may be used to obtain a stepped-up voltage. The comparator10may have hysteresis unless it affects the on-period TON.

INDUSTRIAL APPLICABILITY

Switching regulators according to the present invention may be applied to electric appliances in general.