A method for manufacturing a semiconductor device comprises epitaxially growing a plurality of silicon layers and compressively strained silicon germanium (SiGe) layers on a substrate in a stacked configuration, wherein the silicon layers and compressively strained SiGe layers are alternately stacked on each other starting with a silicon layer on a bottom of the stacked configuration, patterning the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width less than the first width, forming an oxide layer on the compressively strained SiGe layers of the stacked configuration, wherein forming the oxide layer comprises fully oxidizing the silicon layers so that portions of the oxide layer are formed in place of each fully oxidized silicon layer, and removing part of the oxide layer while maintaining at least part of the portions of the oxide layer formed in place of each fully oxidized silicon layer, wherein the compressively strained SiGe layers are anchored to one another and a compressive strain is maintained in each of the compressively strained SiGe layers.

TECHNICAL FIELD

The field generally relates to semiconductor devices including stacked nanowires and methods of manufacturing same and, in particular, to semiconductor devices including compressively strained stacked nanowires.

BACKGROUND

A nanowire is a relatively thin wire, for example, with a diameter or width measured in nanometers (nm). Nanowires can have diameters or widths such as, for example, about 4 nm to 10 nm.

Nanowires can be a viable device option instead of fin field-effect transistors (FinFETs). For example, a nanowire can be used as the fin structure in a dual-gate, tri-gate or gate-all-around (GAA) FET device. Nanowires can have a smaller perimeter than fins, but also larger external resistance due to an under-spacer component.

Complementary metal-oxide semiconductor (CMOS) scaling can be enabled by the use of stacked nanowires, which offer superior electrostatics and higher current density per footprint area than FinFETs.

Techniques for manufacturing nanowire devices can include suspension and deposition. A challenge with nanowires is how to improve nanowire device performance, particularly for p-type FETs (PFETs). Known techniques for manufacturing nanowire devices do not maintain strain in nanowires. Loss in strain causes mobility degradation, resulting in lower performance.

SUMMARY

According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device comprises epitaxially growing a plurality of silicon layers and compressively strained silicon germanium (SiGe) layers on a substrate in a stacked configuration, wherein the silicon layers and compressively strained SiGe layers are alternately stacked on each other starting with a silicon layer on a bottom of the stacked configuration, patterning the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width less than the first width, performing a condensation process, wherein the silicon layers are fully oxidized during the condensation process, and the condensation process results in an oxide layer on the substrate and on remaining portions of the stacked configuration, the oxide layer including portions formed in place of each fully oxidized silicon layer maintaining a compressive strain in each of the compressively strained SiGe layers, and removing part of the oxide layer, wherein remaining portions of the oxide layer are in the stacked configuration and have a smaller width than a width of the compressively strained SiGe layers, the remaining portions of the oxide layer maintaining the compressive strain in each of the compressively strained SiGe layers.

According to an exemplary embodiment of the present invention, a semiconductor device comprises a substrate, a plurality of compressively strained silicon germanium (SiGe) nanowires on the substrate in a stacked configuration, wherein the stacked configuration includes respective dielectric layers alternately stacked on the SiGe nanowires and forming a plurality of anchors, and a gate structure formed on the stacked configuration.

According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device comprises epitaxially growing a plurality of silicon layers and compressively strained silicon germanium (SiGe) layers on a substrate in a stacked configuration, wherein the silicon layers and compressively strained SiGe layers are alternately stacked on each other starting with a silicon layer on a bottom of the stacked configuration, patterning the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width less than the first width, forming an oxide layer on the compressively strained SiGe layers of the stacked configuration, wherein forming the oxide layer comprises fully oxidizing the silicon layers so that portions of the oxide layer are formed in place of each fully oxidized silicon layer, and removing part of the oxide layer while maintaining at least part of the portions of the oxide layer formed in place of each fully oxidized silicon layer, wherein the compressively strained SiGe layers are anchored to one another and a compressive strain is maintained in each of the compressively strained SiGe layers.

These and other exemplary embodiments of the invention will be described in or become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the invention will now be discussed in further detail with regard to semiconductor devices including stacked nanowire FETS and methods of manufacturing same and, in particular, to stacked nanowire CMOS devices that preserve strain in the nanowires.

It is to be understood that the various layers and/or regions shown in the accompanying drawings are not drawn to scale, and that one or more layers and/or regions of a type commonly used in CMOS, fin field-effect transistor (FinFET) and/or other semiconductor devices may not be explicitly shown in a given drawing. This does not imply that the layers and/or regions not explicitly shown are omitted from the actual devices. In addition, certain elements may be left out of particular views for the sake of clarity and/or simplicity when explanations are not necessarily focused on the omitted elements. Moreover, the same or similar reference numbers used throughout the drawings are used to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings.

The stacked nanowire FET devices and methods for forming same in accordance with embodiments of the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the stacked nanowire FET devices are contemplated embodiments of the invention. Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.

The embodiments of the present invention can be used in connection with semiconductor devices that may require stacked nanowire FETs. By way of non-limiting example, the semiconductor devices can include, but are not limited to, CMOS devices, MOSFET devices, FinFET devices, and/or semiconductor devices that do not use FinFET technology.

As used herein, with reference to the drawings, “parallel to a gate extension direction” refers to an extension direction of a gate structure perpendicular to a channel length and to the left and right in these cross-sections, with source/drain regions in front and behind the nanowires in these cross-sections. In other words, left and right in these cross-sections represents a width or diameter direction of the nanowire, and the length of the nanowire and a channel length are going into the page.

As used herein, with reference to the drawings, “perpendicular to a gate extension direction” or “across a channel of a gate structure” refers to a channel length direction of a gate structure and source/drain regions being to the left and right of the nanowires in these cross-sections. In other words, left and right in these cross-sections represents a length direction of the nanowire, and the width or diameter of the nanowire and extension direction of the gate structure are going into the page.

As used herein, “height” refers to a vertical length of an element (e.g., a layer, etc.) in the figures measured from a bottom surface to a top surface of the element, and/or measured with respect to a surface on which the element is directly on.

As used herein, “lateral,” “lateral side,” “lateral surface” refers to a side surface of an element (e.g., a layer, etc.), such as a left or right side surface in the figures.

The processes described in connection withFIGS. 1A-Bto6A-B is applicable to the manufacture of p-type FET (PFET) devices including SiGe channels, which benefit from maintaining compressive strain. Conventional methods of fabricating PFET stacked nanowire devices including SiGe channels involves suspending the channel regions before forming a gate-all-around structure. Suspending the nanowires relaxes the compressive strain which was created during the epitaxial SiGe growth, and therefore negatively affects device performance. Known techniques for the manufacture of stacked nanowire n-type FETs (NFETS) can be used in conjunction with the processes described in connection withFIGS. 1A-Bto6A-B to yield similar short channel effects between resulting PFET and NFET devices. Short channel effects between the resulting PFET and NFET devices will not be identical due to differences between gate structures in resulting NFET and PFET devices. A process for the manufacture of an NFET device including silicon channels, according to an embodiment of the present invention, is described in connection withFIGS. 8-14.

FIGS. 1A and 1Bare cross-sectional views of a semiconductor substrate respectively taken parallel and perpendicular to a gate extension direction and illustrating epitaxial growth of a relaxed silicon and compressively strained SiGe stack, according to an exemplary embodiment of the present invention. A semiconductor substrate105can be, for example, a bulk substrate or a silicon-on-insulator (SOI) substrate including a buried insulating layer, such as, for example, a buried oxide or nitride layer located on an upper surface of the semiconductor substrate. The substrate105may comprise semiconductor material including, but not limited to, Si, SiGe, SiC, SiGeC, III-V, II-V compound semiconductor or other like semiconductor. In addition, multiple layers of the semiconductor materials can be used as the semiconductor material of the substrate. In accordance with an embodiment of the present invention, as can be seen inFIG. 1, relaxed silicon layers110and compressively strained SiGe layers120are epitaxially grown in an alternating and stacked configuration, so that a first silicon layer110is followed a first SiGe layer120on the first silicon layer, which is followed by a second silicon layer110on the first SiGe layer120, and so on. While three silicon layers110and two SiGe layers120are shown, the embodiments of the present invention are not necessarily limited to the shown number of layers110,120, and there may be more or less layers in the same alternating configuration depending on design constraints.

Terms such as “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which it is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface will take on a {100} orientation. In some embodiments, epitaxial growth and/or deposition processes are selective to forming on a semiconductor surface, and do not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

Examples of various epitaxial growth processes include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature for an epitaxial deposition process can range from 550° C. to 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking.

A number of different sources may be used for the epitaxial growth of the relaxed silicon and compressively strained SiGe layers110,120. In some embodiments, a gas source for the deposition of epitaxial semiconductor material includes a silicon containing gas source, a germanium containing gas source, or a combination thereof. For example, an epitaxial silicon layer may be deposited from a silicon gas source that is selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source that is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. While an epitaxial silicon germanium alloy layer can be formed utilizing a combination of such gas sources. Carrier gases like hydrogen, nitrogen, helium and argon can be used.

In accordance with an embodiment of the present invention, the epitaxial growth is performed by growing layers, each of which has a height (in the vertical direction in the figures) of between approximately 5 nm and approximately 20 nm. According to an embodiment, approximately between 3 and 5 pairs of layers110,120are formed. The alternating structure may be formed by in-situ epitaxy of layers110and120in a rapid thermal chemical vapor deposition (RTCVD) chamber, and by controlling the gas flow, pressure, and temperature in the chamber, as well as the duration of the in-situ epitaxy.

FIGS. 2A and 2Bare cross-sectional views of a semiconductor substrate respectively taken parallel and perpendicular to a gate extension direction and illustrating patterning of the silicon and SiGe stack, according to an exemplary embodiment of the present invention. Patterning is performed by, for example, etching, such as, for example, an isotropic etching process, such as reactive ion etching (RIE).

As can be seen inFIGS. 2A and 2B, the patterning decreases a width of the silicon and SiGe layers110and120along an extension direction of a gate structure, and maintains a length along a channel length direction to result in patterned silicon and SiGe layers210and220. The resulting width of silicon and SiGe layers210and220is about 4 nm to about 20 nm.

The etching is performed using a reactive ion etch (RIE) process and a mask including, for example, a nitride, oxide, or an organic resist, covering what is to be a remaining portion of silicon and SiGe layers.

FIGS. 3A and 3Bare cross-sectional views of a semiconductor substrate respectively taken parallel and perpendicular to a gate extension direction and illustrating selective removal of part of the silicon layers from the silicon and SiGe stack, according to an exemplary embodiment of the present invention. Referring toFIGS. 3A and 3B, selective removal of part of the silicon layers210is performed, leaving further patterned silicon layers310to preserve anchoring of SiGe layers220, and, thereby maintain compressive strain on the SiGe layers220. A relaxed unstrained state of SiGe degrades performance of a PFET, which can benefit from compressive strain.

In accordance with an embodiment of the present invention, the selective removal of part of the silicon layers210is performed with respect to the SiGe layers220, and is performed by etching, such as a wet etch, using, for example, tetramethylammonium-hydroxide (TMAH). Other etchants may include, for example, plasma etchants: CF4, SF6, NF3, Cl2, CCl2F2, and wet etchants: hydrochloric acid (HCl), and a mixture of nitric and hydrochloric acid. According to an embodiment, the removal of part of the silicon layers210is performed without removing the SiGe layers220.

As can be seen inFIGS. 3A and 3B, the patterning decreases a width of the silicon layers210along an extension direction of a gate structure, and maintains a length along a channel length direction to result in patterned silicon layers310. The resulting width of silicon layers310is about 2 nm to about 4 nm.

FIGS. 4A and 4Bare cross-sectional views of a semiconductor substrate respectively taken parallel and perpendicular to a gate extension direction and illustrating thermal condensation performed after selective removal of part of the silicon layers from the silicon and SiGe stack as shownFIG. 3A, according to an exemplary embodiment of the present invention. Referring toFIGS. 4A and 4B, a three-dimensional (3D) thermal condensation is performed on the structure ofFIGS. 3A and 3Bto result in the structure shown inFIGS. 4A and 4B. During the thermal condensation process, high-Ge content SiGe layers420are formed, and the silicon layers310are fully consumed by oxidation. The replacement of the silicon layers310with the oxide430maintains the compressive strain in the resulting SiGe layers420. In addition to the other areas covered by oxide layer430including silicon dioxide (SiO2), the oxide layer430is also formed in the areas formerly occupied by the silicon layers310, and in place of outer lateral side portions (seeFIG. 4A) of each of the remaining SiGe layers420to form the SiGe layers420each having a slightly reduced width along an extension direction of a gate structure. As a result, the thermal condensation process thereby condenses the SiGe layers220from lateral side portions inFIG. 3Ainto SiGe layers420, which will be the resulting nanowires. The SiGe layers420remain compressively strained as a result of not being suspended and instead oxidizing the silicon layers310surrounding the SiGe layers420.

By way of further explanation, in accordance with an embodiment of the present invention, referring toFIGS. 4A and 4B, silicon atoms in the Si layers310and in the outer portions of the SiGe layers220bond with oxygen that is available during the condensation process to form the oxide430(e.g., Sift). As a result, because preferably silicon bonds with the oxygen and not germanium, the germanium from the oxidized portions of the SiGe220is driven deeper by diffusion into the remaining portions of the SiGe layers that have not been oxidized to result in the condensed SiGe layers420. In other words, during the thermal condensation process, germanium migrates into the remaining portions of the compressively strained SiGe layers that have not been oxidized. In accordance with an embodiment of the present invention, due to the germanium enrichment from the thermal condensation process, the SiGe layers420each have a germanium concentration that is higher than what the germanium concentration was in each of the SiGe layers220before the thermal condensation process.

The condensation is the result of thermal oxidation that is performed at a temperature sufficient enough to cause oxidation of the silicon in the SiGe layers220. In one embodiment of the present invention, the thermal oxidation is performed at a temperature from about 700° C. to about 1300° C. In another embodiment of the present invention, the thermal oxidation is performed at a temperature from about 1000° C. to about 1200° C.

In accordance with an embodiment of the present invention, the thermal oxidation is performed in an oxidizing ambient which includes at least one oxygen-containing gas such as, for example, O2, NO, N2O, ozone, air and other like oxygen-containing gases. The oxygen-containing gases may be admixed with each other (such as an admixture of O2and NO), or the gas may be diluted with an inert gas such as, for example, He, Ar, N2, Xe, Kr, or Ne.

In accordance with an embodiment of the present invention, the thermal oxidation may be carried out for a variable period of time. In one example, the thermal oxidation is carried out for a time period from about 5 seconds to about 5 hours, depending on thermal oxidation temperature and oxidation species. In another embodiment, the thermal oxidation may be carried out for a time period from about 5 minutes to about 30 minutes. The thermal oxidation may be carried out at a single targeted temperature, or various ramp and soak cycles using various ramp rates and soak times can be employed.

According to an embodiment, the thermal condensation process is performed until the silicon layers310are fully consumed and the resulting SiGe layers420having a desired width and germanium concentration are formed. Even after the silicon layers310are fully consumed, the resulting SiGe layers420are compressively strained because they were not suspended at any point in time during the process.

FIGS. 5A and 5Bare cross-sectional views of a semiconductor substrate respectively taken parallel and perpendicular to a gate extension direction and illustrating removal of part of the oxide layer shown inFIGS. 4A and 4B, according to an exemplary embodiment of the present invention. Referring toFIGS. 5A and 5B, portions of the oxide layer430are removed, by, for example, an RIE process, to result in patterned oxide layer530. As can be seen inFIG. 5A, the oxide layer430is removed from the substrate105, and from side portions and part of top and bottom portions of the SiGe layers420to result in relatively thin oxide layers530, which are the resulting anchor structures for the SiGe layers420. These oxide layers530are anchor structures, which are needed to maintain the compressive strain of the SiGe layers420. The anchor structures prevent the SiGe layers420from being suspended, therefore maintaining the previously held compressive strain. As noted above, the SiGe layers420become the resulting nanowires. Referring toFIG. 5B, the oxide layer430is also removed from lateral ends of the SiGe layers420, and lengths of the oxide layer430are reduced along the left and right direction inFIG. 5Bto result in oxide layer530. According to an embodiment, the RIE process can be performed until the oxide layer530having a desired width is formed. Alternatively, a vertical RIE process can be performed to make the SiO2and SiGe sidewalls coplanar, and then another process, such as, for example, a wet etch process, can be performed to recess the SiO2until the oxide layer530having a desired width is formed. The RIE processes are performed using, for example, fluorocarbon chemistry using CF4, CHF3or a combination thereof. Other processes for removing the portions of oxide layer430can include, for example, dilute hydrofluoric acid etch.

FIGS. 6A and 6Bare cross-sectional views of a semiconductor substrate respectively taken parallel and perpendicular to a gate extension direction and illustrating deposition of the gate structure, including a dielectric and a metal, performed in a process after formation of the structure ofFIGS. 5A and 5B, according to an exemplary embodiment of the present invention. A metal gate structure includes, for example, low resistance metal650, such as, for example, tungsten, zirconium, tantalum, titanium, aluminum, ruthenium, metal carbides, metal nitrides, transition metal aluminides, tantalum carbide, titanium carbide, tantalum magnesium carbide, or combinations thereof, and high-K dielectric640such as, for example, HfO2(hathium oxide). The metal gate structure may be formed using, for example, deposition techniques including, but not limited to, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD), and/or liquid source misted chemical deposition (LSMCD), sputtering, and/or plating. The resulting gate structure is planarized using, for example, chemical mechanical planarization (CMP).

FIG. 7is a cross-sectional view of a semiconductor substrate taken parallel to a gate extension direction and illustrating epitaxial growth of a relaxed silicon and compressively strained SiGe stack, according to an exemplary embodiment of the present invention. In accordance with an embodiment of the present invention, as can be seen inFIG. 7, silicon layers710and compressively strained SiGe layers720are epitaxially grown in an alternating and stacked configuration on a substrate705, so that a first silicon layer710is followed a first SiGe layer720on the first silicon layer, which is followed by a second silicon layer710on the first SiGe layer720, and so on. While three silicon layers710and two compressively strained SiGe layers720are shown, the embodiments of the present invention are not necessarily limited to the shown number of layers710,720, and there may be more or less layers in the same alternating configuration depending on design constraints. Additional descriptions used in connection withFIGS. 1A and 1Bare equally applicable toFIG. 7, and, for the sake of brevity, are not repeated herein.

FIG. 8is a cross-sectional view of a semiconductor substrate taken parallel to a gate extension direction and illustrating patterning of the silicon and compressively strained SiGe stack, according to an exemplary embodiment of the present invention. Like what is discussed in connection withFIGS. 2A and 2B, the patterning decreases a width of the silicon and SiGe layers710and720along an extension direction of a gate structure, and maintains a length along a channel length direction to result in patterned silicon and SiGe layers810and820. The resulting width of the silicon layers810and compressively strained SiGe layers820is about 4 nm to about 10 nm. Additional descriptions used in connection withFIGS. 2A and 2Bare equally applicable toFIG. 8, and, for the sake of brevity, are not repeated herein.

FIG. 9is a cross-sectional view of a semiconductor substrate taken parallel to a gate extension direction and illustrating selective removal of the compressively strained SiGe layers from the silicon and compressively strained SiGe stack, according to an exemplary embodiment of the present invention. Referring toFIG. 9, the compressively strained SiGe layers820are selectively removed with respect to the relaxed silicon layers810. In the case of an NFET device, since there is not a need to maintain compressive strain for an NFET device, the relaxed silicon layers810remaining after the complete removal of the SiGe layers820is satisfactory.

In accordance with an embodiment of the present invention, the removal of the SiGe layers820is performed by etching, such as a wet etch, using, for example, a mixture of hydrogen peroxide, hydrofluoric acid and acetic acid, or using an isotropic dry etch with CF4gas at high pressure in a plasma system.

It is to be understood that elements shown in a stacked configuration, such as, for example, silicon and SiGe layers, are supported in some manner by elements not shown in the figures. For example, with respect toFIG. 9, although silicon layers810are illustrated as suspended or floating in a cross-section with no apparent support, one of ordinary skill in the art will understand that support is provided for these elements in positions that would be in front of and in back of the page in the view ofFIG. 9.

FIGS. 10A and 10Bare cross-sectional views of a semiconductor substrate respectively taken parallel and perpendicular to a gate extension direction and illustrating oxide deposition performed in a process after selective removal of the SiGe layers from the silicon and SiGe stack as shownFIG. 9, according to an exemplary embodiment of the present invention. Referring toFIGS. 10A and 10B, an oxide layer1030such as, for example, SiO2, is formed on the substrate705and the silicon layers810. The oxide deposition process is performed by PECVD or LPCVD of an oxide, for example.

FIGS. 11A and 11Bare cross-sectional views of a semiconductor substrate respectively taken parallel and perpendicular to a gate extension direction and illustrating removal of part of the oxide layer shown inFIG. 11, according to an exemplary embodiment of the present invention. Referring toFIGS. 11A and 11B, portions of the oxide layer1030are removed, by, for example, a vertical etch process, to result in patterned oxide layer1130. As can be seen inFIG. 11A, the oxide layer1030is removed from the substrate705, and from side portions of the silicon layers810to result in patterned oxide layers1130. Referring toFIG. 11B, the oxide layer1030is also removed from lateral ends of the silicon layers810, and lengths of the oxide layer1030are reduced along the left and right direction inFIG. 10Bto result in oxide layer1130. The vertical etch process is performed using, for example, fluorocarbon chemistry using CF4, CHF3or a combination thereof. Other processes for removing the portions of oxide layer1030can include, for example, dilute hydrofluoric acid etch.

FIG. 12is a cross-sectional view of a semiconductor substrate taken parallel to a gate extension direction and illustrating removal of part of the oxide layer shown inFIGS. 11A and 11B, according to an exemplary embodiment of the present invention. Referring toFIG. 12, portions of the oxide layer1130are removed, by, for example, a lateral etch process, to result in patterned oxide layer1230. As can be seen inFIG. 12, the oxide layer1130is recessed horizontally from part of top and bottom portions of the silicon layers810to result in relatively thin oxide layers1230, which are the resulting anchor structures for the silicon layers810. The silicon layers810become the resulting nanowires. The lateral etch process is performed using, for example, dilute hydrofluoric acid.

FIG. 13is a cross-sectional view of a semiconductor substrate taken parallel to a gate extension direction and illustrating deposition of the gate structure, including a dielectric and a metal, performed in a process after formation of the structure ofFIG. 12, according to an exemplary embodiment of the present invention. A metal gate structure includes, for example, low resistance metal1350, such as, for example, tungsten, zirconium, tantalum, titanium, aluminum, ruthenium, metal carbides, metal nitrides, transition metal aluminides, tantalum carbide, titanium carbide, tantalum magnesium carbide, or combinations thereof, and high-K dielectric1340such as, for example, HfO2(hathium oxide). The metal gate structure may be formed using, for example, the same deposition techniques mentioned in connection withFIGS. 6A and 6B. The resulting gate structure is planarized using, for example, CMP.

In accordance with an embodiment, after deposition of the gate structures inFIGS. 6A, 6B and 13, source/drain epitaxy can be performed with proper doping to result in PFET and NFET devices.

In accordance with the embodiments of the present invention, in connection with the manufacture of PFET devices, any compressive strain of the resulting SiGe layers420due to, for example, mismatched lattice structures between SiGe and silicon, is maintained because anchor layers above and below the SiGe layers during processing are not removed. As a result, the SiGe layers420, which become the nanowires, are not relaxed and are maintained in a compressively strained state. Strain energy (e.g., compressive strain) maintains local equilibrium between mismatched lattice structures of two materials (e.g., silicon layer and SiGe on the silicon layer). A relaxed state, for example, in the silicon layers of a stacked configuration, refers to a state without compressive or tensile strain.