Target device providing debugging function and test system comprising the same

A test system for debugging a target device includes a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block supporting a debugging operation at a power saving mode. The switch unit is configured to form a first signal transfer path for transferring the test signal to the first IP block at the normal mode and to form a second signal transfer path for transferring the test signal to the second IP block at the power saving mode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefits, under 35 U.S.C §119, of Korean Patent Application No. 10-2010-0040918 filed Apr. 30, 2010, the entirety of which is incorporated by reference herein.

BACKGROUND

Exemplary embodiments relate to a test system, and more particularly, to a target device supporting a debugging function and a test system including the same.

2. Description of the Related Art

In general, semiconductor integrated circuits may be inevitably debugged during a design process. The debugging means correcting a design circuit of a semiconductor integrated circuit when no design circuit is normally operated. A semiconductor integrated circuit to be debugged is called a target device. The debugging for error correction is inevitably made if a System on Chip (SoC) scheme is applied to the target device.

Recently, there is an increasing need for a low-power semiconductor integrated circuit. Therefore, a power saving mode for reducing power consumption of the semiconductor integrated circuit may be required.

SUMMARY

Embodiments are therefore directed to a target device supporting a debugging function and a test system including the same, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.

At least one of the above and other features and advantages may be realized by providing a test system for debugging a target device, including a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block supporting a debugging operation at a power saving mode, wherein the switch unit may be configured to form a first signal transfer path for transferring the test signal to the first IP block at the normal mode and to form a second signal transfer path for transferring the test signal to the second IP block at the power saving mode.

The first IP block may include at least one processor, the first IP block being configured not to be powered at the power saving mode. The first IP block may further include a first test controller for controlling the debugging operation at the normal mode, the second IP block including a second test controller for controlling the debugging operation at the power saving mode. The switch unit may be within the target device. The target device may include an input/output terminal configured to input and output the test signal, and the switch unit may be configured to form the first signal transfer path between the input/output terminal and the first test controller at the normal mode and to form the second signal transfer path between the input/output terminal and the second test controller at the power saving mode. The test system may further include a test interface connected to the input/output terminal, the test interface being configured to convert an externally provided signal into the test signal. The test signal may be at least one of JTAG signals, I2C signals, and SPI signals. The input/output terminal may be connected to a host which includes a debugging program. The test signal may be an UART signal.

The switch unit may be external to the target device. The target device may include a first input/output terminal connected to the first IP block and to the switch unit at the normal mode to interface the test signal, and a second input/output terminal connected to the second IP block and to the switch unit at the power saving mode to interface the test signal. The first signal transfer path may be formed between the first input/output terminal and the first test controller at the normal mode, and the second signal transfer path is formed between the second input/output terminal and the second test controller at the power saving mode. The test system may further include a test interface connected to the switch unit, the test interface being configured to convert an externally provided signal to the test signal, the switch unit being placed between the test interface and the target device. The test system may further include a test interface connected to the target device, the test interface being configured to convert an externally provided signal to the test signal, the switch unit being placed within the test interface. The switch unit may be connected with a host which includes a debugging program.

At least one of the above and other features and advantages may also be realized by providing a target device for supporting a debug function, including a processor block including at least one processor, the processor block being configured to be powered at a normal mode to support a debugging operation, an alive block configured to be powered at a power saving mode to support a debugging operation, and a switch block configured to form a first signal transfer path into the processor block at the normal mode and to form a second signal transfer path into the alive block at the power saving mode.

The processor block may not be powered at the power saving mode. The processor block may include a first test controller for controlling the debugging operation of the normal mode, and the alive block may include a second test controller for controlling the debugging operation of the power saving mode. The target device may further include an input/output terminal for interfacing a test signal, the first signal transfer path being formed between the input/output terminal and the first test controller and the second signal transfer path being formed between the input/output terminal and the second test controller. The second test controller may be configured to control a state machine analyzing test, a state analyzing test for a system control signal, or a wake-up signal applying test.

DETAILED DESCRIPTION

FIG. 1illustrates a block diagram of a test system according to an exemplary embodiment of the inventive concept. Referring toFIG. 1, a test system100may include a host110, a test interface120, and a target device130.

The host110may include a debugging program111for testing the target device130. For example, the host110may be a computer system, e.g., a personal computer. The host110may issue into the test interface120a test signal TS for testing the target device130. For example, in response to an input of a user to issue the test signal TS including an address, a control signal, a data signal, etc., the host110may respond into the test interface120according to a given protocol. In this case, the protocol may be defined variously by system designers.

The test interface120receives the test signal TS from the host110. The test interface120converts the received test signal TS into a converted test signal CTS, which is sent to the target device130. For example, in the event that JTAG (Joint Test Action Group) signals are used to debug the target device130, the test interface120converts the test signal TS into JTAG signals, e.g., a test mode selection signal TMS, a test clock signal TCK, and a test data input signal TDI, and the JTAG signals are sent to the target device130.

Further, the test interface120may receive a converted test signal CTS from the target device130, and may convert the received signal CTS into a test signal TS to be returned to the host110. For example, in the event that JTAG signals are used to debug the target device130, the test interface120receives the JTAG signal, e.g., a test data output signal TDO, from the target device130and converts the test data output signal TDO, i.e., a converted test signal CTS, into a test signal TS to be send to the host110.

The target device130may receive the converted test signal CTS from the test interface120, and may perform a test operation for debugging in response to the converted test signal CTS. For example, in the event that JTAG signals are used to debug the target device130, the target device130receives the JTAG signals, e.g., the test mode selection signal TMS, the test clock signal TCK, or the test data input signal TDI. Next, the target device130performs a test operation in response to the JTAG signals and outputs the test output signal TDO to the test interface120. The test output signal TDO is converted into a test signal TS by the test interface120, and the test signal TS is sent to the host110.

Continuing to refer toFIG. 1, the target device130may include a plurality of Intellectual Property (IP) blocks. The plurality of IP blocks may include a processor block132, an alive block133, and a switch block131. The processor block132may be formed of at least one processor. For example, the processor block132may be formed of a central processing unit CPU in the ARM family, a digital signal processor DSP in the TEAK family, a combination of the CPU and DSP, or the like.

At a normal mode, the processor block132may support a debugging operation with respect to the target device130. The normal mode indicates a mode where IP blocks, including the processor block132, among the IP blocks in the target device130are powered. At a power saving mode, the processor block132is not powered. The power saving mode indicates a mode where IP blocks, including the processor block132, among the IP blocks in the target device130are not powered.

It is possible to control a power and a clock applied to the plurality of IP blocks in the target device130at need. This is to reduce a power consumed by the target device130. For example, if no command execution is requested from a user during a predetermined time, the processor block132may enter an idle state. In this case, the target device130enters a power saving mode, so that the processor block132is not powered.

The alive block133may be powered even at the power saving mode. The alive block133is capable of being realized variously according to designers so as to consume minimal power during the power saving mode. For example, the alive block133may include registers which store state information of a normal mode upon switching from the normal mode to the power saving mode. The alive block133provides state information of a previous normal mode to the processor block132upon returning to the normal mode from the power saving mode.

In an exemplary embodiment, the alive block133supports a debugging operation during the power saving mode. For this, the alive block133may include a test controller which controls a test operation at the power saving mode. For example, at the power saving mode, the test controller of the alive block133may control the test operation for debugging, e.g., only, the alive block133. In another example, at the power saving mode, the test controller of the alive block133may control the test operation for debugging the IP blocks including the alive block133.

Continuing to refer toFIG. 1, the switch block131may receive the converted test signal CTS from the test interface120, and may selectively transfer the converted test signal CTS to either one of the processor block132and the alive block133in response to a power saving mode signal PSM. For example, when JTAG signals for debugging the target device130are used, the switch block131may transfer JTAG signals from the test interface120, e.g., a test mode selection signal TMS, a test clock signal TCK and a test data input signal TDI, to either one of the processor block132and the alive block133in accordance with an activation state of the power saving mode signal PSM.

In detail, at the normal mode, the power saving mode signal PSM is inactivated. When the power saving mode signal PSM is inactivated, the switch block131transfers the converted test signal CTS from the test interface120to the processor block132. That is, the first signal transfer path is formed by the switch block131. Therefore, when JTAG signals for debugging the target device130are used, e.g., TMS, TCK, and TDI signals, the JTAG signals are transferred from the test interface120to the processor block132through the switch block131.

Then, the processor block132performs a test operation using the received converted test signal CTS, e.g., the JTAG signals TMS, TCK, and TDI. After the test operation, a converted test signal CTS from the processor block132is sent to the test interface120through the switch block131. In the event that JTAG signals for debugging the target device130are used, the processor block132performs a test operation using the JTAG signals TMS, TCK, and TDI. Then, the processor block132outputs as a test result a test data output signal TDO, which is transferred to the test interface120through the switch block131.

Meanwhile, the power saving mode signal PSM is activated during a power saving mode. When the power saving mode signal PSM is activated, the switch block131transfers the converted test signal CTS from the test interface120to the alive block133. That is, the signal transfer path is formed through the switch block131.

In an exemplary embodiment, the power saving mode signal PSM is capable of being activated by the alive block133. Alternatively, the power saving mode signal PSM may be activated by an interrupt controller (not shown).

In the event that JTAG signals for debugging the target device130are used during the power saving mode, e.g., JTAG signals TMS, TCK, and TDI, the JTAG signals may be transferred from the test interface120to the alive block133through the switch block131.

Next, the alive block133performs the test operation in response to the received converted test signal CTS during the power saving mode. For example, the test controller of the alive block133controls, e.g., only, the test operation for debugging the alive block133. In another example, the test controller of the alive block133controls the test operation for debugging IP blocks including the alive block133.

After the test operation is performed, the alive block133outputs a converted test signal CTS, which is sent to the test interface120through the switch block131. Accordingly, the test system100according to an exemplary embodiment of the inventive concept may perform the debugging operation without limitations even during the power saving mode. In particular, as the test system100according to an exemplary embodiment of the inventive concept supports the debugging operation at both the normal mode and the power saving mode, time and a costs required to develop the target device130may be reduced.

FIG. 2illustrates a detailed block diagram of the target device130illustrated inFIG. 1. Referring toFIG. 2, the target device130may include the switch block131, the processor block132, the alive block133, an input/output terminal134, a memory interface135, and a power switch136.

The input/output terminal134transfers the converted test signal CTS from the test interface120to the switch block131. Further, the input/output terminal134transfers the converted test signal CTS from the switch block131to the test interface120. In the event that JTAG signals for debugging the target device130are used, the input/output terminal134includes TMS, TCK, TDI, and TDO terminals.

Herein, the TDI terminal is a test data input terminal, and the TDO terminal is a test data output terminal. The TDI and TDO terminals are used to input and output data for boundary scanning. The TCK terminal transfers a clock signal to the first or second test controller132aor133a, upon testing. The TMS terminal transfers a test mode selection signal to the first or second test controller132aor133a.

The switch block131forms either the first signal transfer path between the input/output terminal134and the processor block132or the second signal transfer path between the input/output terminal134and the alive block133, as discussed previously with reference toFIG. 1. In particular, at a normal mode, the switch block131forms the first signal transfer path between the input/output terminal134and the processor block132in response to an inactivated power saving mode signal PSM. At a power saving mode, the switch block131forms the second signal transfer path between the input/output terminal134and the alive block133in response to an activated power saving mode signal PSM.

The processor block132may include a first test controller132a, a boundary scan cell132b, and a processor132c. The processor block132is powered at the normal mode to perform a test operation for debugging. The first test controller132acontrols an overall test operation at the normal mode.

In detail, in the event that JTAG signals are used for debugging the target device130, the first test controller132areceives the test mode selection signal TMS and the test clock signal TCK through the first signal transfer path. The first test controller132acontrols an overall test operation of the normal mode using the test mode selection signal TMS and the test clock signal TCK. In this case, a control operation of the first test controller132amay be determined by a value of the test mode signal TMS at a low-to-high transition of the test clock signal TCK. Test data is synchronized with a low-to-high transition of the test clock signal TCK and is received from the TDI terminal through the first signal transfer path. Further, test data is synchronized with a high-to-low transition of the test clock signal TCK and is transferred to the TDO terminal through the first signal transfer path.

The boundary scan cell132bmay include scan registers. If JTAG signals are used for debugging the target device130, the scan registers in the boundary scan cell132breceive test data from the TDI terminal and shifts the received test data for boundary scanning. Data from the boundary scan cell132bis transferred to the TDO terminal through the first test controller132a.

The alive block133may include the second test controller133aand a plurality of sub IP blocks, e.g., N sub IP blocks133b_1to133b_n. The alive block133may be powered even at the power saving mode, so the alive block133may perform a test operation for debugging at the power saving mode.

The second test controller133acontrols an overall test operation at the power saving mode. For example, if JTAG signals for debugging the target device130are used, the second test controller133areceives the test mode selection signal TMS, the test clock signal TCK, and the test data input signal TDI through the second signal transfer path.

In this case, the test operation of the power saving mode can be made variously according to configuration of the plurality of sub IP blocks133b_1to133b_n. For example, the second test controller133amay control the test operation for debugging of the alive block133. In another example, the second test controller133amay control the test operation for debugging IP blocks including the alive block133. For example, the second test controller133aresponds to the received JTAG signals to control operations of analyzing a state machine of the target device130, of analyzing a state according to a system control signal, and of testing application of a wake-up signal for switching to a normal mode from a power saving mode.

Continuing to refer toFIG. 2, the memory interface135provides an interface between a memory and the target device130. For example, the memory may be a volatile memory, e.g., a DRAM, a SRAM, or the like. In another example, the memory may be a non-volatile memory, e.g., a flash memory, a PRAM, a RRAM, a FRAM, a MRAM, or the like.

The power switch136may be supplied with an external power. The power switch136may supply powers to the IP blocks of the target device130. In case of the normal mode, e.g., the power switch136supplies power to the processor block132and/or the alive block133. In case of the power saving mode, e.g., the power switch136interrupts the power supply to the processor block132and supplies power only to the alive block133.

As described above, the alive block133according to an exemplary embodiment of the inventive concept may include the second test controller133afor controlling the test operation at the power saving mode. Accordingly, it may be possible to perform the debugging operation even at the power saving mode. Further, as the switch block131enables switching between debugging operations of the normal mode and the power saving mode in response to a state of the power saving mode signal PSM, the test system100(referring toFIG. 1) may perform the debugging operation without limitations, e.g., even when a mode is switched to the power saving mode from the normal mode. As a result, it may be possible to save time and costs during development of the target device130.

FIG. 3illustrates a flow chart for describing a test operation of the target device130illustrated inFIG. 2. For ease of description, a test operation will be described under the assumption that a mode is switched to a power saving mode from a normal mode.

In operation S110, during a normal mode, a debugging operation may be performed through the first signal transfer path. That is, in case of the normal mode, the switch block131forms the first signal transfer path between the input terminal134and the processor block132in response to the inactivated power saving mode signal PSM. In this case, the processor block132may be powered and may perform a test operation for debugging of the normal mode.

In operation S120, the processor block132may not be powered. That is, the mode is switched to the power saving mode from the normal mode when the power of the processor block132is turned off, while the alive block133is powered. For example, the alive block133is capable of being powered at both the normal mode and the power saving mode. In another example, the alive block133is not powered at the normal mode, i.e., the alive block133is powered when the mode is switched to the power saving mode from the normal mode.

In operation S130, the power saving mode signal PSM may be activated. For example, the power saving mode signal PSM may be activated by the alive block133. In another example, the power saving mode signal PSM may be activated by an interrupt controller (not shown). In this case, for example, the interrupt controller may simultaneously cut off power to the processor block132and activate the power saving mode signal PSM.

In operation S140, a signal transfer path of the converted test signal CTS may be switched to the second signal transfer path from the first signal transfer path. That is, the switch block131may form the second signal transfer path between the input/output terminal134and the alive block133in response to the activated power saving mode signal PSM.

In operation S150, a debugging operation of the power saving mode may be carried out through the second signal transfer path. That is, the alive block133may perform a test operation for debugging at the power saving mode. For example, the test controller133aof the alive block133may control the test operation for debugging the alive block133.

FIG. 4illustrates a block diagram of a test system according to another exemplary embodiment of the inventive concept. A test system200inFIG. 4is similar to that inFIG. 1and, therefore, only a difference between the test systems100and200inFIGS. 1 and 4will be more fully described below.

Referring toFIG. 1, a host210may include a debugging program211for testing a target device240. The host210may transfer a test signal TS for testing the target device240through a test interface220.

In detail, the test interface220may receive the test signal TS from the host210and may convert the test signal TS into a converted test signal CTS, which is sent to a switch unit230. Elements210and220inFIG. 4are similar to those inFIG. 1, and description thereof is thus omitted.

Unlike the switch unit131inFIG. 1, the switch unit230may be placed outside the target device240. The switch unit230receives the converted test signal CTS from the test interface220and forms a signal transfer path for sending the converted test signal CTS to the target device240.

For example, at a normal mode, the switch unit230forms the first signal transfer path between the test interface220and a processor block241in response to an inactivated power saving mode signal PSM. At a power saving mode, the switch unit230forms a second signal transfer path between the test interface220and an alive block242in response to an activated power saving mode signal PSM.

The target device240receives the converted test signal CTS from the switch unit230and performs a test operation for debugging in response to the received converted test signal CTS. For example, at the normal mode, the processor block241of the target device240receives the converted test signal CTS from the switch unit230. That is, the converted test signal CTS is sent to the processor block241through the first signal transfer path. The processor block241performs a test operation for debugging of the normal mode using the converted test signal CTS. At the power saving mode, the alive block242of the target device240receives the converted test signal CTS from the switch unit230. That is, the converted test signal CTS is transferred to the alive block242through the second signal transfer path. In this case, the alive block242performs a test operation for debugging of the power saving mode using the converted test signal CTS.

As described above, the switch unit230of the test system200inFIG. 4is placed between the test interface220and the target device240unlike the switch block131inFIG. 1. Further, unlike the target device130inFIG. 1, the target device240inFIG. 4may include two input/output terminals, which will be more fully described with reference toFIG. 5below.

FIG. 5illustrates a detailed block diagram of the target device240illustrated inFIG. 4. The target device240inFIG. 5is similar to that inFIG. 2, and the difference between the target devices130and240in respectiveFIGS. 1 and 5will be more fully described below. Referring toFIG. 5, the target device240may include the processor block241, the alive block242, a first input/output terminal243, a second input/output terminal244, a memory interface245, and a power switch246.

As discussed above, the target device240may include the first and second input/output terminals243and244unlike the target device130inFIG. 1. This is because the target device240receives the converted test signal CTS from the switch unit230placed outside the target device240, i.e., the switch unit230may be external with respect to the target device240.

In particular, the first input/output terminal243receives the converted test signal CTS through the first signal transfer path at a normal mode. That is, at the normal mode, the switch unit230inFIG. 4forms the first signal transfer path between the test interface220and the first input/output terminal243in response to an inactivated power saving mode signal PSM. In this case, the first input/output terminal243transfers the converted test signal CTS from the switch unit230to the processor block241. Further, the first input/output terminal243sends the converted test signal CTS from the processor block241to the switch unit230. If JTAG signals are used to debug the target device240, the first input/output terminal243may include TMS, TCK, TDI, and TDO terminals.

The second input/output terminal244receives the converted test signal CTS through the second signal transfer path at the power saving mode. That is, in case of the power saving mode, the switch unit230forms the second signal transfer path between the test interface220and the second input/output terminal244. In this case, the second input/output terminal244transfers the converted test signal CTS from the switch unit230to the alive block242. Further, the second input/output terminal244transfers the converted test signal CTS from the alive block242to the switch unit230. In the event that JTAG signals are used to debug the target device240, the second input/output terminal244may include TMS, TCK, TDI, and TDO terminals.

The processor block241may include a first test controller241a, a boundary scan cell241b, and a processor241c. The processor block241receives the converted test signal CTS for debugging from the first input/output terminal243at a normal mode. The first test controller241aof the processor block241controls an overall test operation at the normal mode. The processor block241inFIG. 5is similar to that inFIG. 2and description thereof is thus omitted.

The alive block242may include the second test controller242aand a plurality of, for example, N sub IP blocks242b_1to242b_n. The alive block242receives the converted test signal CTS for debugging in case of a power saving mode. The second test controller242aof the alive block242controls an overall test operation at a power saving mode. The alive block242inFIG. 5is similar to that inFIG. 2and description thereof is thus omitted.

As described above, the test system200according to another exemplary embodiment of the inventive concept supports the debugging operation at both the normal mode and the power saving mode. Therefore, time and costs used for developing the target device240may be substantially reduced.

FIG. 6illustrates a block diagram showing a test system according to still another exemplary embodiment of the inventive concept. A test system300inFIG. 6is similar to that inFIG. 4. A difference between the test systems inFIGS. 4 and 6will be more fully described below. Referring toFIG. 6, the test system300may include a host310, a test interface320, and a target device330.

The host310may include a debugging program311for testing the target device330. The host310may transfer a test signal TS for testing the target device330to the test interface320. The host310inFIG. 6is similar to that inFIG. 4and description thereof is thus omitted.

Unlike the test interface220inFIG. 4, the test interface320may include a signal converter321and a switch block322. In other words, as illustrated inFIG. 6, the switch block322may be placed within the test interface320, as opposed to being placed between and external to both the test interface220and the target device240in the configuration illustrated inFIG. 4. The signal converter321receives the test signal TS from the host310. The signal converter321converts the test signal TS into a converted test signal CTS, which is sent to the switch block322. The switch block322transfers the converted test signal CTS to the target device330through either one of the first and second signal transfer paths.

In case of the normal mode, the switch block322forms the first signal transfer path between the signal converter321and a processor block331in response to an inactivated power saving mode signal PSM. In this case, the converted test signal CTS is transferred to the processor block331through the first signal transfer path.

In case of the power saving mode, the switch block322forms the second signal transfer path between the signal converter321and an alive block332in response to an activated power saving mode signal PSM. In this case, the converted test signal CTS is transferred to the alive block332through the second signal transfer path.

The target device330receives the converted test signal CTS from the switch block320. The target device330performs a test operation for debugging in response to the converted test signal CTS. The processor block331and alive block332inFIG. 6are similar to the ones inFIG. 4and, therefore, descriptions thereof are not repeated.

As described above, the test system300according to an exemplary embodiment of the inventive concept supports the debugging operation at both the normal mode and the power saving mode. Therefore, time and costs used to develop the target device330may be substantially reduced.

Meanwhile, a method of debugging a target device using JTAG signals is described as an example inFIGS. 1 to 6. However, a debugging method is not limited to this disclosure. For example, it may be possible to debug a target device using Inter Integrated Circuit (I2C) signals. In this case, the I2C signals include an SDA (serial data) line signal and an SCL (Serial Clock Line) signal. In another example, it may be possible to debug a target device using Serial Peripheral Interface (SPI) signals. That is, inFIGS. 1 to 6, a test interface converts a test signal TS into SPI signals, and a target device is debugged depending upon the SPI signals. In this case, the SPI signals include a Master Input Slave Output (MISO) signal, a Master Output Slave Input (MOSI) signal, a Serial Clock (SCK) signal, and a Select Slave (SS) signal.

InFIGS. 1 to 6, a test signal TS is converted into a converted test signal CTS, and a target device is debugged depending upon the converted test signal CTS. However, a debugging method is not limited to this disclosure. For example, it may be possible to debug a target device using a test signal TS provided from a host, which will be more fully described with reference toFIGS. 7 and 8.

FIG. 7illustrates a block diagram of a test system according to still another exemplary embodiment of the inventive concept. A test system400inFIG. 7is similar to that inFIG. 1, with the exception of not having a test interface. Referring toFIG. 7, the test system400may include a host410and a target device420.

As the test system400does not include a test interface, a test signal TS output from the host410is sent to the target device420, and the target device420is debugged based on the test signal TS. For example, Universal Asynchronous receiver/transmitter (UART) signals can be used to debug the target device420. The host410, e.g., a personal computer, may include an UART device, in general. Accordingly, the host410may be capable of providing the UART signals as the test signal TS. In this case, the target device420may be debugged according to the UART signals. That is, unlike the test system100inFIG. 1, the test system400inFIG. 7does not include a test interface independently. The target device420inFIG. 7is similar to that inFIG. 1, and description thereof is thus omitted.

FIG. 8illustrates a block diagram of a test system according to still another exemplary embodiment of the inventive concept. A test system500inFIG. 8is similar to that inFIG. 4, with the exception of not having a test interface.

In particular, a test signal TS from a host510may be sent to a target device530through a switch unit520. The target device530may be debugged according to the test signal TS, as described previously with reference toFIG. 7. That is, if UART signals are used to debug the target device530, the test system500does not include a test interface independently. Elements520and530inFIG. 8are similar to parallel elements inFIG. 4, and description thereof is thus omitted.

As described above, a test system according to exemplary embodiments of the inventive concept may support a debugging operation at both the normal mode and the power saving mode. Therefore, time and costs to develop the target device may be reduced.