Method and system for switching between subnetwork operation and full network operation

In order further to develop a method for changing over a serially networked system (100), in particular a serial databus system, from subnetwork operation (T), in which at least one node (22, 28) and/or at least one user (32, 38) of the system (100) is in a state of reduced current consumption and is not addressed and/or not activated by the signal level (40, 42, 44) of the data traffic on the system (100), to full network operation (G), in which all the nodes (20, 22, 24, 26, 28) and/or all the users (30, 32, 34, 36, 38) of the system (100) are addressed and/or activated by the signal level (46, 48) of the data traffic on the system (100), together with a corresponding system (100) in such a way that the nodes (22, 28) and/or the users (32, 38) in the network, i.e. on the databus (10), may be simply yet effectively woken, it is proposed that the system (100) be changed over from subnetwork operation (T) to full network operation (G) through the detection of at least one defined, especially continuous and/or especially symmetrical signal level pattern (62, 64) in the data traffic on the system (100).

The present invention relates to a method for changing over a serially networked system, in particular a serial databus system, from subnetwork operation, in which at least one node and/or at least one user of the system is in a state of reduced current consumption and is not addressed and/or not activated by the signal levels of the data traffic on the system, to full network operation, in which all the nodes and/or all the users of the system are addressed and/or activated by the signal levels of the data traffic on the system.

The present invention also relates to a serially networked system, which is intended to be changed over from subnetwork operation, in which at least one node and/or at least one user of the system is in a state of reduced current consumption and cannot be addressed and/or activated by the signal levels of the data traffic on the system, to full network operation, in which all the nodes and/or all the users of the system may be addressed and/or activated by the signal levels of the data traffic on the system.

With increasingly complex serial networking in particular of automobiles, the energy requirement of the electronic components used in serial networking is also constantly on the increase. Added to this is the fact that ever more comfort functions are also active when the motor vehicle is switched off, having then to be operated directly from the vehicle battery.

Due to the serial networking of a large number of functions by means, for example, of the C[ontroller]A[rea]N[etwork] bus, the entire bus system is always activated even when only a few vehicle functions are in operation, since each bus user is “woken” or “kept awake” by data transmission involving a few users; this leads to undesirably high system current consumption, which, in view of the fact that only a few vehicle functions are in operation, is also wholly unnecessary.

According to the prior art, users in a serially networked system are transferred into a low current consumption state in which the normal bus traffic at normal bus levels does not cause waking. These users are thus in a “selective sleep state”, while the remaining users maintain “subnetwork operation”.

In order to be able to wake the sleeping nodes or the sleeping users, in the prior art a second level scheme with a markedly different potential is used on the databus, with which the users may be “globally woken”; only when this second level scheme is used for transmission do all the nodes globally wake up. This known principle is used for example in a “Single Wire C[ontroller]A[rea]N[etwork]”.

However, a disadvantage of this known principle is that the second level scheme used for waking is associated with markedly increased bus system noise emission; in particular, cyclic wake-up events lead for this reason to undesirable disturbances in the motor vehicle, wherein E[lectro]M[agnetic]C[ompatibility] emissions also play a part; moreover, a second driver stage is necessary, to generate the other level scheme.

Taking as basis the above-described disadvantages and shortcomings and acknowledging the outlined prior art, it is an object of the present invention so to develop a method of the above-mentioned type and a system of the above-mentioned type that the nodes and/or users in the network, i.e. on the databus, may be woken simply yet effectively.

This object is achieved by a method having the features indicated in claim1and by a system having the features indicated in claim4. Advantageous embodiments and expedient further developments of the present invention are identified in the respective dependent claims.

It is therefore proposed according to the invention to use a different waking mechanism instead of the second level scheme in a system which finds itself selectively asleep in subnetwork operation, which different waking mechanism does not exhibit the above-described disadvantages of the prior art. This waking mechanism may be implemented both in system chips and in other networking products, such as for instance in simple transceiver modules.

With regard to the present invention, it is first of all assumed that a number of nodes or a number of users are in a state of reduced current consumption and are thus not woken by the ongoing bus traffic.

So that the present system has the option, in such ongoing subnetwork operation, of waking the “sleeping” nodes or the “sleeping” users immediately and without a rest phase, a special waking data packet is used according to the teaching of the present invention.

This “global waking message” or “global waking data packet” uses the same nominal level scheme but is distinguished by a special bit sequence, which appropriately does not arise in normal communication operation and which may be freely defined in the data field of any desired message or any desired data packet.

In this context, the nodes in the low current consumption state and/or the users in the low current consumption state of the serially networked system may examine the ongoing data traffic on the CAN system bus for an in particular continuous and/or in particular symmetrical data pattern and interpret the detection of this data pattern as a waking event.

As a particularly suitable bit sequence, there is provided a symmetrical data pattern which is linked to any identifier (address/header), of which there is at least one, and which may be simply detected by simple hardware, specifically without the need for a protocol controller.

Thus, a decisive advantage consists in the fact that the protocol used does not have to be tracked in bit-accurate manner and that, moreover, it is not essential to use a special message identifier (address/header), but rather any desired message identifier (address/header) may be used; all that is needed is detection of a symmetrical pattern which may be repeated appropriately frequently in the data field of the message or data packet.

The more data bytes are used, the more frequently this pattern may be present therein and the better it may be filtered for. The data patterns used may be of any desired type and are distinguished merely by the frequent repetition of identical bit phases. To filter such data patterns, it is possible to use both per se known analog circuits and per se known digital circuits.

According to a particularly inventive further development of the present method and of the present system, a changeover from subnetwork operation to full network operation may also occur if a signal rest level and/or no change in the signal level is noted on the system for a period which is greater than a critical period of definable or settable length.

The critical period is preferably selected to be greater than the interval between the individual messages or data packets of the data traffic on the system.

According to one advantageous development, messages or data packets are sent by at least one of the nodes participating in subnetwork operation and/or at least one of the users participating in subnetwork operation at cyclic intervals which are smaller than the critical period.

The present invention further relates to a transceiver unit, in particular for carrying out a method of the type described above and/or in particular associated with at least one system of the type described above; the transceiver unit is connected to at least one serial databus, in particular to at least one C[ontroller]A[rea]N[etwork] bus, and is in communication with at least one microcontroller unit which is provided to carry out at least one application.

According to a preferred further development of the present invention, at least one control logic is associated with the transceiver unit and/or at least one control logic is implemented in the transceiver unit.

The present invention further relates to a voltage regulator which is connected to at least one battery unit, and which is in communication with at least one transceiver unit, in particular of the type described above, which voltage regulator is intended to supply a voltage to at least one microcontroller unit, provided to execute at least one application, if at least one defined, in particular continuous and/or in particular symmetrical signal level pattern is detected by the transceiver unit in at least one incoming message associated with at least one application and occurring on at least one serial databus, in particular on at least one C[ontroller]A[rea]N[etwork] bus.

The present invention further relates to a chip unit, in particular a system chip unit, for addressing and/or activating at least one microcontroller unit which is provided to carry out at least one application and which is associated with at least one serial databus, in particular at least one C[ontroller]A[rea]N[etwork] bus; which chip unit comprisesat least one transceiver unit of the type described above, andat least one voltage regulator of the type described above.

The present invention further relates to a microcontroller unit provided to carry out at least one application and associated with at least one serial data bus, in particular at least one C[ontroller]A[rea]N[etwork] bus, which microcontroller unit is to be supplied with a voltage only if at least one defined, in particular continuous and/or in particular symmetrical signal level pattern is detected in at least one incoming message associated with at least one application and occurring on the databus, by at least one transceiver unit, in particular according to the type described above.

According to a preferred further development of the present invention, the microcontroller unit can be activated by the transceiver unit.

The present invention finally relates to the use ofa method of the type described above and/orat least one system of the type described above and/orat least one chip unit of the type described above and/orat least one microcontroller unit of the type described above in automobile electronics, in particular in motor vehicle electronics.

As has already been described above, there are various possible ways in which the teaching of the present invention may advantageously be embodied and refined. On the one hand, reference can be made in this connection to the claims dependent on claims1,4,9and13, and on the other, further aspects, features and advantages of the present invention are apparent from and will be elucidated with reference to the illustrative embodiment shown inFIGS. 1 to 4.

FIG. 1shows an exemplary implementation of a serially networked CAN system100provided for C[ontroller]A[rea]N[etwork] applications in automobile electronics, namely in motor vehicle electronics.

This serially networked system100comprises five users30,32,34,36,38, which are connected to a serial C[ontroller]A[rea]N[etwork] databus10via respective associated nodes20,22,24,26,28and which take the form, for example, of a system chip unit (optionally including transceiver unit) or of a microcontroller unit, for instance of an application controller unit or of a protocol controller unit.

Next, inFIG. 2the build-up, the function and the structure of the users30,32,34,36,38provided to execute applications are explained in an exemplary manner by means of a detailed description of the first user30, which is connected to the node20of the CAN databus10and which can be addressed and/or activated via this CAN databus10. The operating principle is as follows:

If, in the case of a system100change-over (cf.FIG. 1) according to the method from subnetwork operation to full network operation (cf.FIG. 4), a defined, for example continuous and/or for example symmetrical signal level pattern (=so-termed “data pattern” cf.FIG. 3) is detected in the data or message traffic on the CAN data bus line which otherwise does not occur in the data or message traffic, by the node20which is in a state of reduced current consumption and/or by the user30which is in a state of reduced current consumption, and in this regard in particular by a transceiver unit84equipped with a control logic and connected to the data bus10and/or by a system chip unit80which accommodates the transceiver unit84and which is permanently supplied from a battery unit70, then the transceiver unit84switches on a voltage regulator86which is connected to the battery unit70via a supply line76and which is in communication886with the transceiver unit84.

After that, the application is started completely via a connection line984in that the voltage regulator86supplies a voltage to the application user which takes the form of a microcontroller unit90with integrated CAN control unit; as shown inFIG. 2, between the voltage regulator86and the (application) microcontroller unit90there is also a reset line986(“reset”).

If, however, the pattern detector (or transceiver84) does not detect the presence of any message on the CAN databus10, then the voltage regulator86is not switched on.

The system100may be configured and controlled via a mode control interface982between the transceiver unit84(or the system chip unit80) and the microcontroller unit90.

In addition, it is noted in respect of the example of embodiment of the present invention illustrated by means ofFIG. 2that for the change-over it is not important whether use is made of an integrated system chip80or of discrete components such as transceiver84and voltage regulator86.

Of the five users30,32,34,36,38, the first user30of which has been described by way of example hereinabove with reference toFIG. 2, two users32,38, as shown inFIG. 1, are in a low current consumption state, in which these two users32,38are not addressed and thus also not activated by the signal level40,42,44(cf.FIG. 4) of the data traffic on the system100.

The remaining three active users30,34,36define subnetwork operation T, i.e. the three users30,34,36communicate with one another (this is symbolized by the double-headed arrow between the active user30and the active user34and by the double-headed arrow between the active user34and the active user36) and are addressed by the signal level of the data traffic on the system100.

The system100is now changed over immediately and without a rest phase from ongoing subnetwork operation T (=“sleeping” nodes22,28or “sleeping” users32,38) to full network operation G, in which all the nodes20,22,24,26,28or all the users30,32,34,36,38are addressed by the signal level of the data traffic on the system100, by using a special waking data packet (c.f.FIG. 3).

This “global waking message” or “global waking data packet” uses the same nominal level scheme but is distinguished by a special bit sequence, which does not arise in normal communication operation and which may be freely defined in the data field of any desired message or any desired data packet.

In this context, the users32,38in the low current consumption state of the serially networked system100may examine the ongoing data traffic on the CAN system bus10for a continuous symmetrical data pattern and interpret the detection of this symmetrical data pattern as a waking event.

As a particularly suitable bit sequence, there is provided a symmetrical data pattern62or64which is linked to any identifier60(address/header), of which there is at least one, and which may be simply detected by simple hardware, specifically without the need for a protocol controller.

Thus, a decisive advantage consists in the fact that the protocol used does not have to be tracked in bit-accurate manner and that, moreover, it is not essential to use a special message identifier (address/header), but rather any desired message identifier60(address/header) may be used; all that is needed is detection of a symmetrical pattern which may be repeated appropriately frequently in the data field of the message or data packet.

The more data bytes are used, the more frequently this pattern may be present therein and the better it may be filtered for. The data pattern used may be of any desired type and are distinguished merely by the frequent repetition of identical bit phases. To filter such data patterns, it is possible to use both per se known analog circuits and per se known digital circuits.

Alternatively or in addition thereto, the system100may also be changed over from subnetwork operation T to full network operation G in that a signal rest level50is noted on the system100, i.e. in particular no change is noted in the signal level (=so-called rest phase), for a period Δt; this rest phase period Δt is greater than a critical period Δtkof definable and settable length.

On the other hand, this critical period Δtkis in turn set to be greater than the interval Δtdbetween the individual messages and data packets of the data traffic on the system100, such that the normal time gaps Δtdbetween the messages and data packets of subnetwork operation T are insufficient for detecting the end of subnetwork operation T.

Accordingly, the nodes20,24,26or the users30,34,36send messages and data packets during subnetwork operation T at cyclic intervals which are smaller than the critical period Δtk, so as to ensure that the “selectively sleeping” nodes22,28or the “selectively sleeping” users32,38are not woken during subnetwork operation T.

To summarize, it may thus be stated that the method illustrated inFIG. 3allows the implementation of subnetwork operation T within a serial bus system10. Parts (=“selectively sleeping” nodes22,28, or “selectively sleeping” users32,38) of the networked system100shown inFIGS. 1 and 2may remain in a reduced current consumption state, whereas other parts (=“active” nodes20,24,26or “active” users30,34,36) communicate with one another in subnetwork operation T and do not wake the parts in the reduced current consumption state.

In order to wake these “sleeping” nodes22,28or “sleeping” users32,38, an appropriately designed symmetrical data pattern62,64(c.f.FIG. 3) is used within any desired messages or data packets, so as to “wake” the “sleeping” nodes22,28or the “sleeping” users32,38without the need for a time-based bus system rest phase Δt (=no communication).

Alternatively or in addition thereto, a certain time period Δt>Δtkwithout communication on the databus10may be used to allow waking of these “sleeping” nodes22,28or “sleeping” users32,38by a normal message or data packet; the criterion for addressing all the nodes20,22,24,26,28or all the users30,32,34,36,38on the databus10is thus that a bus system rest phase Δt was present beforehand which is greater than the settable critical period Δtk.

LIST OF REFERENCE NUMERALS

100serially networked system, in particular serial databus system10serial databus, in particular C[ontroller]A[rea]N[etwork] bus20first node of the system10022second node of the system10024third node of the system10026fourth node of the system10028fifth node of the system10030first user of the system10032second user of the system10034third user of the system10036fourth user of the system10038fifth user of the system10040first signal level on databus1042second signal level on databus1044third signal level on databus1046fourth signal level on databus1048fifth signal level on databus1050signal rest level on databus1060identifier (address/header)62first symmetrical data pattern64second symmetrical data pattern70battery unit76connection between battery unit70and voltage regulator8680chip unit, in particular system chip unit84transceiver unit of the chip unit8086voltage regulator of the chip unit80886connection between transceiver unit84and voltage regulator8690microcontroller unit982interface between transceiver unit84and microcontroller unit90984connection between voltage regulator86and microcontroller unit90986reset line between voltage regulator86and microcontroller unit90G full network operationT subnetwork operationΔt time periodΔtdintervalΔtkcritical period