MEMORY SYSTEM FOR SECURE READ AND WRITE OPERATIONS BASED ON PREDEFINED DATA PATTERNS

A memory buffer device facilitates secure read and write operations associated with data that includes a predefined data pattern. For read operations, the memory buffer device detects a read data pattern in the read data that matches a predefined data pattern. The memory buffer device may then generate a read response that includes metadata identifying the read data pattern without sending the read data itself. The memory buffer device may also receive Write Request without Data (RwoD) commands from the host that include metadata identifying a write data pattern. The memory buffer device identifies the associated data pattern and writes the data pattern or the metadata to the memory array. The memory buffer device may include encryption and decryption logic for communicating the metadata in encrypted form.

BACKGROUND

In a memory system, a host facilitates read and write operations associated with one or more memory devices. The architecture of the memory system may be designed to meet performance criteria relating to latency, power consumption, and data security associated with such operations.

DETAILED DESCRIPTION

A memory buffer device facilitates secure read and write operations associated with data that may include predefined data patterns. For read operations, the memory buffer device detects when the memory address associated with a read command includes a read data pattern from a set of predefined data patterns. The memory buffer device may then generate a read response that includes metadata identifying the read data pattern without sending the read data itself. The memory buffer device may also receive Write Request without Data (RwoD) commands from the host that include metadata identifying a write data pattern. The memory buffer device identifies the associated data pattern and writes the data pattern or the metadata to the memory array. The memory buffer device may include encryption and decryption logic to enable the memory buffer device to communicate with the host over a secure communication link that transmits the metadata (and optionally, the full commands and responses) in encrypted form.

FIG.1illustrates an embodiment of a memory system100comprising a host device110, a memory buffer device120, and a memory array130. The host device110communicates with the memory buffer device120over a secure communication link112for facilitating various memory operations of the memory array130. In an embodiment, the secure communication link112comprises a serial link that communicates packetized commands and data between a host device110and a remote memory buffer device120. For example, the communication link112may comprise a serial-attached memory interface such as a Compute Express Link (CXL) interface, an Open Memory Interface (OMI), a Coherent Accelerator Processor Interface (CAPI), a Peripheral Component Interconnect Express (PCIe) interface, or other interfaces. In another embodiment, the communication link112may comprise a double data rate (DDR) Dynamic Random-Access Memory (DRAM) interface or other memory interface for communicating between a locally connected host device110(such as a memory controller) and a memory buffer device120that may be integrated with a memory device or memory module. For example, the host device110, memory buffer device120, and memory array130may reside on the same printed circuit board. In an embodiment, at least some of the signals communicated over the communication link112may be optionally encrypted, scrambled, or otherwise obfuscated for security.

The memory buffer device120and the memory array130may comprise separate integrated circuits (e.g., of a memory module) or may be integrated on a single chip. AlthoughFIG.1illustrates only a single memory buffer device120and memory array130, various embodiments may include a memory buffer device120that interoperates with multiple memory arrays130and/or a host device110that interoperates with multiple memory buffer devices120. For example, a host device110in a CXL environment may communicate with multiple CXL modules, each comprising one or more memory buffer devices120, which correspondingly interoperate with one or more memory arrays130. In a local memory system, the host device110may control multiple memory buffer devices120and/or memory arrays130that may be embodied in one or more memory modules (e.g., a dual-inline memory module (DIMM)).

The memory array130may comprise a DRAM (dynamic random-access memory) (or a set of DRAMs) that communicates with the memory buffer device120over at least a command/address (CA) link132and a data (DQ) link134. The DRAM may include various other ports associated with timing and configuration signals that are omitted fromFIG.1. In a memory write operation, the memory array130receives a memory write command including a memory address from the CA link132and receives write data on the DQ link134. The memory array130stores the received write data to the memory address specified in the memory write command. In a memory read operation, the memory array130receives a read command including a memory address via the CA link132, and outputs read data stored at the memory address to the DQ link134. The memory array130may furthermore perform other operations responsive to commands received from the CA link132such as refresh operations, precharge operations, mode register read and write operations, and other memory operations.

The memory buffer device120includes a host-side interface122, a cryptography module124, a command controller126, and a memory-side interface128. The host-side interface122comprises one or more ports for communicating commands, command responses, and data between the host device110and the memory buffer device120. In a CXL-based system, the host-side interface122may packetize outgoing signals for sending to the host device110and depacketize incoming signals received from the host device110. In a local memory system, the host-side interface122may comprise a set of ports for communicating with a memory controller such as a CA port, DQ port, and various timing/control ports.

The cryptography module124performs encryption and decryption operations to decrypt incoming encrypted data for writing to the memory array130in write operations and to encrypt outgoing data read from the memory array130in read operations. The cryptography module124may decrypt and/or encrypt both data and commands communicated over the communication link112or may decrypt and/or encrypt only data and metadata portions of the commands (e.g., command headers), without necessarily decrypting and/or encrypting commands in full. In an embodiment, the cryptography module124may be configurable (e.g., via an internal register or via an external command) to turn encryption/decryption on or off, to control the type of encryption/decryption, and/or to control various encryption/decryption parameters. In an embodiment, the cryptography module124can be optionally omitted.

The command controller126receives and decodes incoming host-side commands from the host device110, facilitates memory operations with the memory array130associated with those commands, and generates command responses associated with commands. The host-side commands may include standard write request with data (RwD) commands, write request without data (RwoD) commands, and read (RD) commands. For a RwD command, the command controller126receives the RwD command (which includes a memory address) and write data for writing to the memory array130. The command controller126generates a memory write command (with the memory address) for issuing to the memory array130.

The host-side RwoD commands may be employed when data for writing to the memory array130includes one or more predefined data patterns. Examples of predefined data patterns include a pattern of all zeros, a pattern of all ones, a pattern of alternating ones and zeros, or any other arbitrary data pattern configured for RwoD operations. To execute an RwoD command, the command controller126receives the RwoD command without expressly receiving write data. The RwoD command specifies a memory address and write pattern metadata that identifies a write data pattern for associating with the memory address. For example, the metadata may comprise a data pattern flag encoded in a command packet header that references a specific write data pattern from a set of predefined data patterns. The metadata may optionally comprise a length flag that specifies a length of the write data pattern. For example, the length flag may specify a range of memory addresses, a number of data blocks, a number of repetitions of the data pattern, or other indicator. Alternatively, the length flag may be omitted and the metadata may instead reference a predefined data pattern of fixed length.

In an embodiment, the command controller126associates the write data pattern with the memory address by generating memory commands to expressly write the write data pattern to the memory address of the memory array130. In another embodiment, the command controller126may instead write the metadata indicative of the write data pattern to the specified memory address, without expressly writing the write data pattern itself. In yet another embodiment, the command controller126may write the memory address and the metadata indicative of the write data pattern to a special memory location in the memory array130or in the memory buffer device120that stores a mapping between the memory address and the metadata.

For a host-side RD command, the command controller126receives the RD command (which includes a memory address) and determines if the memory address is associated with a predefined data pattern. For example, in one embodiment, the command controller126reads from the memory address (e.g., by issuing a memory read command), and then determines if the received data matches a predefined data pattern. Alternatively, the command controller126detects that the memory address is associated with a predefined data pattern by detecting that metadata is stored at the memory address or that metadata is associated with the memory device in a separate mapping. The command controller126may then issue a no data read response (NDRR) that includes the metadata, without expressly outputting the data pattern. For example, the NDRR may comprise a flag for including in a data packet header of a read response sent to the host device110via the communication link112. If the command controller126does not detect any predefined data pattern associated with the memory address, then the command controller126may generate a standard data response (DRS) to the host device110that includes the read data.

The memory-side interface128comprises a set of ports for communicating with the memory array130. For example, the memory-side interface128may include at least a CA port for communicating memory write and memory read commands to the memory array130over the CA link132and a DQ port for communicating write data and read data over the DQ link

FIG.2is a first example embodiment of a command controller126. In this embodiment, the command controller126includes command decoding logic202, a pattern generator204, a pattern register206, a pattern detector208, and a response generator210. The command decoding logic202receives and decodes host-side commands and write data212(that have been decrypted by the cryptography module124) to detect the type of command. When an RwoD command is detected, a pattern generator204identifies metadata in the RwoD indicative of a write data pattern and maps the metadata to a predefined data pattern in the pattern register206. The pattern generator204generates the write data based on the mapped data pattern. For a host-side RD or RwD command, the pattern generator204may be bypassed. The command controller126provides the memory-side command and write data (which may include locally generated write data mapped from metadata) to the memory-side interface128for issuing to the memory array130.

For a host-side RD command212, a pattern detector208receives read data216from the memory array130(via the memory-side interface128) and compares the read data216to the set of predefined data patterns in the pattern register206to detect matches. If a match is detected, the response generator210may issue a NDRR218that includes metadata indicative of the matched data pattern, without expressly outputting the read data pattern. Otherwise, if the pattern detector208does not detect a match, the response generator210may issue a standard DRS read response that includes the read data216.

The command controller126may furthermore include a programming interface220for programming the pattern register206. In some embodiments, the programming interface220may program additional aspects of the command controller126or other aspects of the memory buffer device120such as the type of encryption or various encryption parameters.

FIG.3illustrates another embodiment of the command controller126. In this embodiment, the command controller126does not include the pattern generator204, pattern detector208, or pattern register206and instead read/writes the metadata directly without mapping to or from the data patterns. For example, in response to an RwoD command, a metadata generator304obtain metadata from the RwoD command indicative of a write data pattern and generates a memory write command to write the metadata to the memory array130. For a RD command212, a metadata detector308detects when the read data216includes metadata and a response generator210generates a NDRR including the metadata.

FIG.4is an example embodiment of a host device110that interoperates with the above-described memory buffer device120. In a write path, a pattern detector402receives input data422and identifies patterns in the input data422that correspond to one or more predefined data patterns in the pattern register408. A command generator404generates host-side RwD and/or RwoD commands for sending to the memory buffer device120. Where one or more predefined data patterns are detected in the input data422the command generator404may generate a RwoD command that includes metadata associated with the detected data pattern without including the data pattern itself. If no pattern is detected, the command generator404may instead generate a RwD command and the write data. The encryption logic406optionally encrypts at least the write data and metadata (and optionally the full commands)212for transmitting over the communication link112.

In a read path, decryption logic412decrypts read data and/or metadata from read responses218received over the communication link112(if received in encrypted form). A pattern generator410maps metadata to predefined data patterns in the pattern register408and generates output data424including the read data and detected data patterns. In an embodiment, the encryption logic406and decryption logic412may be optionally omitted.

The host device110may furthermore include a programming controller414that may communicate with the memory buffer device120over the programming interface220to program the pattern register206of the memory buffer device120and/or perform other configuration functions relating to encryption/decryption or memory operations.

FIG.5is a first example configuration of a memory system500that includes the above-described memory buffer device120. In this embodiment, the host device110comprises a system host510that communicates packetized commands and data with a plurality of serial-attached memory modules520over a secure interconnect link512. In an embodiment, the memory system500may comprise a disaggregated memory system in which the serial-attached memory modules520are remote and distributed relative to the system host510. Each serial-attached memory module520includes a serial-attached memory controller522that incorporates the memory buffer device120and controls one or more memory devices524. Here, the memory devices524may comprise conventional DRAM devices that interface with the serial-attached memory controller522using a conventional DRAM interface (e.g., CA and DQ links). The memory buffer device120is capable of receiving encrypted RwoD commands over the secure interconnect link512and writing to the memory devices524using conventional memory write commands as described above. Furthermore, the memory buffer device120may perform standard read operations from the memory devices524and, where appropriate, generate encrypted NDRRs to the system host510over secure interconnect link512.

FIG.6is a second example configuration of a memory system600with the above-described memory buffer device120. In this embodiment, the host device110may comprise a memory controller610that communicates with a memory device620including the memory buffer device120and a memory array524. In an embodiment, the memory buffer device120and memory array524may be integrated on a single chip. Alternatively, the memory buffer device120and the memory array524may be separate chips of a memory module on a printed circuit board.

The memory controller610is capable of performing conventional read and write operations, and processing RwoD commands and NDRR responses. Furthermore, the memory controller610may include encryption and decryption logic to enable encryption and decryption of signals over the CA and DQ links622,624. In this embodiment, RwoD commands may be communicated over the CA link622without sending data over the DQ link624. Furthermore, NDRR responses may be sent over the CA link622without communicating read data over the DQ link624. The DQ link624may be employed to communicate write data and read data associated with conventional read and write operations.

In an embodiment, reads and writes associated with certain data patterns may be implemented using a data copy function of the memory controller610and memory device620. Here, when a predefined data pattern is detected by the memory buffer device120in response to a read operation, the memory buffer device120may output a value (e.g., zero or one) on a single DQ line (e.g., DQ0)624to indicate a selection between two predefined data patterns (e.g., all zeros or all ones) and assert a data masking pin626(e.g., DM=0) to indicate a read copy operation to the memory controller610. The memory controller610detects that the data masking pin626is asserted and copies the value on the single DQ line (DQ0) to all other bits of a byte. In other embodiments, multiple DQ lines624may be to enable selection between different numbers of predefined data patterns.

In another embodiment, the memory buffer device120may toggle one or more DQS (DQ strobe) lines628(which generally operate as a timing signal associated with the DQ signals in conventional memory operations) while asserting the data masking pin626to indicate a predefined data pattern, where different toggle counts map to different predefined data patterns. The memory controller610may detect when the data making pin626is asserted in response to a read operation, count the number of toggles on one or more DQS lines628, and then map the count of edges to a predefined data pattern.

Upon reading this disclosure, those of ordinary skill in the art will appreciate still alternative structural and functional designs and processes for the described embodiments, through the disclosed principles of the present disclosure. Thus, while particular embodiments and applications of the present disclosure have been illustrated and described, it is to be understood that the disclosure is not limited to the precise construction and components disclosed herein. Various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus of the present disclosure herein without departing from the scope of the disclosure as defined in the appended claims.