FLASH MEMORY STORAGE APPARATUS AND A BIASING METHOD THEREOF, WHICH CAN REDUCE A GATE INDUCED DRAIN LEAKAGE (GIDL) AND IMPROVE RELIABILITY OF MEMORY CELLS

A flash memory storage apparatus includes a memory cell array and a voltage generating circuit. The memory cell array includes at least one memory cell string coupled between a bit line and a source line and including memory cells; each memory cell is coupled to a corresponding word line. The voltage generating circuit is coupled to the memory cell array and configured to output a bias voltage to the word line. A first voltage is applied to a selected word line. A second voltage and a third voltage are applied to unselected second and third word lines, respectively. The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage. The second word line and the third word line are located on two sides of the first word line. A biasing method of a flash memory storage apparatus is also provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority of Taiwan patent application serial no. 110104200, filed on Feb. 4, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference and made a part of this specification.

BACKGROUND

Technical Field

The disclosure relates to a memory storage apparatus and an operating method thereof, and particularly relates to a flash memory storage apparatus and a biasing method thereof.

Description of Related Art

With the evolution of electronic technologies, electronic apparatuses have become indispensable tools in people's lives. Flash memories which can perform long-term data storage functions and have large storage capacity have become important data storage media. The flash memory contains a plurality of flash memory cell strings. As the demands for data storage increase, the number of flash memory cells included in the flash memory cell string also increases. However, during programming, gate induced drain leakage (GIDL) affects the state of data stored in the flash memory cells, leading to the reduction of reliability of the flash memory cells.

SUMMARY

The disclosure provides a flash memory storage apparatus and a biasing method thereof, which can reduce a gate induced drain leakage (GIDL) and improve reliability of memory cells.

According to an embodiment of the disclosure, a flash memory storage apparatus includes a memory cell array and a voltage generating circuit. The memory cell array includes at least one memory cell string. The memory cell string is coupled between a bit line and a source line. The memory cell string includes a plurality of memory cells, and each of the memory cells is coupled to a corresponding word line. The voltage generating circuit is coupled to the memory cell array. The voltage generating circuit is configured to output a bias voltage to the word lines. A first voltage is applied to a selected first word line of the word lines. Unselected word lines include a second word line and a third word line, and a second voltage and a third voltage are applied to the second word line and the third word line, respectively. The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage. The second word line and the third word line are respectively located on two sides of the first word line.

In an embodiment of the disclosure, the second word line is located at a source side area between the first word line and the source line. The third word line located at a drain side area between the first word line and the bit line.

In an embodiment of the disclosure, the second word line is the unselected word line located in the source side area and closest to the first word line, and the second voltage is applied to the second word line. A fourth voltage is applied to all the other unselected word lines in the source side area. The fourth voltage is less than the second voltage but greater than the third voltage.

In an embodiment of the disclosure, the third word line is the unselected word line located in the drain side area and closest to the first word line, and the third voltage is applied to the third word line. A fourth voltage is applied to all the other unselected word lines in the drain side area. The fourth voltage is less than the second voltage but greater than the third voltage.

In an embodiment of the disclosure, the third voltage is applied to all other unselected word lines in the drain side area.

In an embodiment of the disclosure, a system voltage is applied to the bit line and source line.

In an embodiment of the disclosure, the flash memory storage apparatus is a NAND gate flash memory.

According to an embodiment of the disclosure, a biasing method of a flash memory storage apparatus includes: applying a first voltage to a selected first word line among word lines; applying a second voltage to an unselected second word line of the word lines and applying a third voltage to an unselected third word line of the word lines. The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage. The second word line and the third word line are located on two sides of the first word line, respectively.

In an embodiment of the disclosure, the second word line is located at a source side area between the first word line and the source line. The third word line is located at a drain side area between the first word line and the bit line.

In an embodiment of the disclosure, the source side area includes a plurality of unselected word lines, and the second voltage is applied to the second word line located in the source side area and closest to the first word line.

In an embodiment of the disclosure, the biasing method of the flash memory storage apparatus further includes: applying a fourth voltage to the unselected word lines other than the second word line in the source side area. The fourth voltage is less than the second voltage but greater than the third voltage.

In an embodiment of the disclosure, the drain side area includes a plurality of unselected word lines, and the third voltage is applied to the third word line located in the drain side area and closest to the first word line.

In an embodiment of the disclosure, the biasing method of the flash memory storage apparatus further includes: applying a fourth voltage to the unselected word lines other than the third word line in the drain side area. The fourth voltage is less than the second voltage but greater than the third voltage.

In an embodiment of the disclosure, the drain side area includes a plurality of unselected word lines, and the third voltage is applied to all other unselected word lines.

In an embodiment of the disclosure, the biasing method of the flash memory storage apparatus further includes: applying a system voltage to the bit line and the source line.

In view of the above, in one or more embodiments of the disclosure, the voltage generating circuit applies bias voltages of different values to the word lines, so as to reduce the GIDL and improve the reliability of the memory cells.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a schematic diagram briefly illustrating a flash memory storage apparatus according to an embodiment of the disclosure.FIG. 2is a schematic diagram briefly illustrating the memory cell string according to the embodiment depicted inFIG. 1. With reference toFIG. 1andFIG. 2, a flash memory storage apparatus100provided in the embodiment includes a memory cell array110and a voltage generating circuit120. The voltage generating circuit120is coupled to the memory cell array110. In this embodiment, the flash memory storage apparatus100is, for instance, a NAND gate flash memory. The voltage generating circuit120may have a circuit design method well known to those skilled in the art.

The memory cell array110includes a bit line BL, a source line SL, and word lines WL0to WL31. The memory cell array110further includes at least one memory cell string122. The memory cell string122is coupled between the bit line BL and the source line SL. The memory cell string122includes a plurality of memory cells M0to M30and M31. The memory cells M0to M30and M31are coupled to the corresponding word lines WL0to WL30and WL31. For instance, the memory cell M31is coupled to the word line WL31, and the memory cell MO is coupled to the word line WL0. The coupling relationship between other memory cells and their corresponding word lines may be deduced fromFIG. 2and thus will not be further described hereinafter. In addition, the number of the memory cell string, the number of the memory cells, and the number of the word lines do not serve to pose any limitation in the disclosure.

In this embodiment, the memory cell array110further includes selection transistors121and123, which are respectively coupled to the corresponding selection lines SGD and SGS. The memory cell string122is coupled between the selection transistors121and123. The selection transistors121and123are configured to select the memory cell string to be programmed during programming. In this embodiment, the memory cell array110further includes dummy memory cells125and127, which are respectively coupled to the corresponding dummy word lines DWL. In an embodiment, the memory cell array110may not include any dummy memory cell nor any dummy word line.

FIG. 3is a schematic diagram briefly illustrating a bias voltage applied to each driver line in a memory cell array according to an embodiment of the disclosure. With reference toFIG. 1toFIG. 3, the voltage generating circuit120is configured to output a bias voltage V to the word lines WL0to WL31during the programming period. The bias voltage V includes a first voltage Vww, a second voltage Vpass_s, a third voltage Vpass_d, and a fourth voltage Vpass. The first voltage Vww is greater than the second voltage Vpass_s, and the second voltage Vpass_s is greater than the third voltage Vpass_d. The fourth voltage Vpass is less than the second voltage Vpass_s but is greater than the third voltage Vpass_d. In this embodiment, the first voltage Vww is applied to the selected word line WL28(the first word line) of the word lines WL0to WL31, and the second voltage Vpass_s and the third voltage Vpass_d are applied to the unselected word lines WL27, WL29to WL31. InFIG. 3, the vertical height of the histogram represents the voltage applied to each driver line.

Specifically, among the word lines WL0to WL31, the word line WL28is, for instance, the selected word line. The other word lines WL0to WL27(the second word lines) and word lines WL29to W31(the third word lines) are unselected word lines. In this embodiment, compared to the first word line WL28, the second word lines WL0to WL27are located closer to the source line SL, wherein the word line WL27is located closest to the first word line WL28. Compared to the first word line WL28, the third word lines WL29to W31are located closer to the bit line BL, wherein the word line WL29is located closest to the first word line WL28.

In this embodiment, the second voltage Vpass_s is applied to the second word line WL27located closest to the first word line WL28, and the fourth voltage Vpass is applied to the other second word lines WL0to WL26; here, the fourth voltage Vpass is less than the second voltage Vpass_s. In this embodiment, since the voltage generating circuit120applies the second voltage Vpass_s to one single second word line WL27located in a source side area and closest to the first word line WL28, and the second voltage Vpass_s is greater than the fourth voltage Vpass, the programming speed may be improved. In this embodiment, the second voltage Vpass_s is applied only to one single second word line WL27located closest to the first word line WL28, which should however not be construed as a limitation in the disclosure. In an embodiment, the voltage generating circuit120may also apply the second voltage Vpass_s to one or more second word lines between the source line SL and the first word line WL28.

On the other hand, in this embodiment, the third voltage Vpass_d is applied to the third word lines WL29to W31between the bit line BL and the first word line WL28. Since the voltage generating circuit120provided in this embodiment applies the third voltage Vpass_d to all the third word lines WL29to W31in a drain side area, the gate induced drain leakage (GIDL) of the drain side area may be reduced.

In addition, in this embodiment, during the programming period, a system voltage VCC is applied to the bit line BL, the source line SL, and the selection line SGD, a ground voltage GND is applied to the selection line SGS, and a dummy voltage VDWL is applied to the dummy word line DWL. According to this embodiment, the system voltage VCC is equal to the dummy voltage VDWL, and the system voltage VCC is less than the third voltage Vpass_d. The system voltage VCC and the dummy voltage VDWL may be supplied by the voltage generating circuit120or other circuits in the apparatus.

In this embodiment, the third voltage Vpass_d is applied to all the third word lines WL29to W31between the bit line BL and the first word line WL28, which should however not be construed as a limitation in the disclosure. In an embodiment, the voltage generating circuit120may also apply the third voltage Vpass_d only to at least one third word line.

FIG. 4is a schematic diagram briefly illustrating a bias voltage applied to each driver line in a memory cell array according to another embodiment of the disclosure. With reference toFIG. 1,FIG. 2, andFIG. 4, in this embodiment, the third voltage Vpass_d is applied to the third word line WL29closest to the first word line WL28, and the fourth voltage Vpass is applied to the other third word lines WL30and WL31to reduce the GIDL of the drain side area.

FIG. 5is a flow chart illustrating steps of a biasing method of a flash memory storage apparatus according to an embodiment of the disclosure. With reference toFIG. 1toFIG. 3andFIG. 5, the operating method provided in this embodiment is at least adapted to the flash memory storage apparatus100depicted inFIG. 1, which should however not be construed as a limitation in the disclosure. The flash memory storage apparatus100depicted inFIG. 1is taken as an example; in step S100, the voltage generating circuit120applies the first voltage Vww to the selected first word line WL28of the word lines. In step S110, the voltage generating circuit120applies the second voltage Vpass_s to at least one unselected second word line WL27and applies the third voltage Vpass_d to at least one unselected third word line WL29. In step S120, the voltage generating circuit120applies the fourth voltage Vpass to all other unselected word lines. The first voltage Vww is greater than the second voltage Vpass_s, and the second voltage Vpass_s is greater than the third voltage Vpass_d. The fourth voltage Vpass is less than the second voltage Vpass_s but is greater than the third voltage Vpass_d. In addition, the teachings, suggestions, and implementations of the biasing method provided in this embodiment may be sufficiently obtained from the descriptions of the embodiments depicted inFIG. 1toFIG. 4embodiments.

To sum up, in one or more embodiments of the disclosure, the voltage generating circuit outputs an asymmetric bias voltage to the unselected word lines adjacent to the selected word line during programming, which not only reduces the GIDL and improves the reliability of the memory cells but also increases the programming speed.