Method for manufacturing semiconductor device

In a method for manufacturing a semiconductor device, an opening formed in a semiconductor substrate by using a mask and covering an inner side face of the opening with a sidewall protective film. The mask is removed, while a part of the sidewall protective film remains.

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2011-41735 filed on Feb. 28, 2011, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing a semiconductor device.

2. Description of the Related Art

Conventionally, in semiconductor chip including stacked semiconductor substrates, a TSV (Through Silicon Via, i.e., through-hole electrode) is used so as to connect the semiconductor substrates to one another. Examples of a method of forming a hole for this TSV include a Bosch process in which etching and deposition are repeated alternately. It is known that using this method causes the cross section of the hole for the TSV to form into a concave shape referred to as a scallop shape.

JP2008-053568A discloses a method for forming a seed layer for TSVs, while leaving over a scallop shape on the inner wall of this hole after forming a hole for TSV by a Bosch process.

JP2007-311584A and JP2008-034508A disclose methods of removing a scallop shape formed on the inner wall of a hole for TSV by a Bosch process and planarizing the inner wall.

SUMMARY OF THE INVENTION

In one embodiment, there is provided a method for manufacturing a semiconductor device, comprising:

forming an opening in a semiconductor substrate by using a mask and covering an inner side face of the opening with a sidewall protective film; and removing the mask, while a part of the sidewall protective film remains.

In another embodiment, there is provided a method for manufacturing a semiconductor device including a through-hole electrode, the method comprising:

sequentially forming a first interlayer insulating film and an intermediate wiring on a main surface of a semiconductor substrate;

forming a first bump hole exposing the first interlayer insulating film and having an inner side face with a concave shape within the semiconductor substrate in a thickness direction thereof;

forming a second bump hole in the first interlayer insulating film by etching the first interlayer insulating film from an inner bottom face of the first bump hole, so as to expose the intermediate wiring, and forming a sidewall protective film on the inner side face of the first and second bump holes; and removing a part of the sidewall protective film, so that the sidewall protective film remains inside the concave shape of the inner side face in the first bump hole.

In another embodiment, there is provided a method for manufacturing a semiconductor device including a first interlayer insulating film on a first surface of a semiconductor substrate, the method comprising:

forming a mask on a second surface of the semiconductor substrate; forming a first bump hole by etching the semiconductor substrate in a thickness direction thereof and exposing the first interlayer insulating film, the etching being performed for patterning an inner side face of the semiconductor substrate so as to have a concave shape;

forming a second bump hole in the first interlayer insulating film by etching the first interlayer insulating film to pattern a inner side face and forming a sidewall protective film on the inner side face of the semiconductor substrate and the first interlayer insulating film; and

removing the mask and a part of the sidewall protective film so that the sidewall protective film remains inside the concave shape of the inner side face of the semiconductor substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A method for manufacturing a semiconductor device includes: forming a mask on a rear surface of a semiconductor substrate; forming a hole in the semiconductor substrate; and removing the mask so as to leave over a part of a sidewall protective film. In the step of forming the hole, there is formed, by using the mask, a hole penetrating through the semiconductor substrate and including an inner side face which is concave in shape and covered with the sidewall protective film. The inner side face of the hole can be smoothened because the part of the sidewall protective film remains on the inner side face of this hole even after the removal of the mask. As a result, a material can be buried in the hole with excellent embeddability in a later step, without giving rise to any voids. In addition, it is possible to reduce the resistance of the material buried in the hole and improve the yield of the semiconductor device. Examples of semiconductor devices to be buried in the hole may include a rear surface bump of a TSV and a contact plug.

The semiconductor device comprises a through-hole electrode. This through-hole electrode includes a rear surface bump, a first seed film, an intermediate wiring, a second seed film, and a front surface bump provided in sequence from the rear surface side toward the main surface side of the semiconductor substrate. The rear surface bump and the first seed film are provided in first and second bump holes, and a sidewall protective film is further provided between the first seed film and the first and second bump holes. In this semiconductor device, the inner side face of the bump hole can be covered with the uniform first seed film by leaving over the sidewall protective film on the inner side face of the bump hole, thereby preventing voids from generating therein. As a result, it is possible to prevent an increase in the wiring resistance of the rear surface bump. It is also possible to inhibit the disconnection of the rear surface bump leading to a product failure and causing a degradation in the yield.

A configuration and a manufacturing method for the semiconductor device according to the present exemplary embodiment will be described with reference to an example where the semiconductor device is a DRAM (Dynamic Random Access Memory).

FIG. 1A is a cross-sectional view illustrating a configuration of semiconductor package100in which the semiconductor device according to the present exemplary embodiment is housed.FIG. 1Bis an enlarged cross-sectional view illustrating a configuration of the semiconductor device at a part60shown by dashed lines inFIG. 1A. Here, a silicon substrate is used as a semiconductor substrate serving as a base in the semiconductor device of the present exemplary embodiment.FIG. 1Bis a simplified view and does not illustrate a detailed structure, such as a scallop shape (concave shape) on the inner side face of a bump hole.FIGS. 8 and 9to be described later do not illustrate detailed structures, either.

The following semiconductor substrates are generically referred to as “wafers”:A unit semiconductor substrate,A semiconductor substrate in the process for manufacturing a semiconductor device thereon, andA semiconductor substrate on which a semiconductor device has been formed.

In addition, each unit semiconductor device according to the present exemplary embodiment diced out of a wafer is generically referred to as “chip.”FIG. 2Ais a plan view illustrating a configuration of the interior of a chip in which a semiconductor device according to the present exemplary embodiment is provided.FIG. 2Bis an enlarged cross-sectional view illustrating a configuration of the chip at a region61shown by slant lines inFIG. 2A.

As illustrated inFIG. 1A, semiconductor package100includes chips1, film substrate2and lead frame3. Lateral sides of each chip1sandwiched by film substrate2and lead frame3are molded using mold material4such as resin. A gap between stacked chips1is completely filled with filling material5such as resin. Stacked chips1are electrically connected to one another. In addition, semiconductor package100is connected to a substrate on which the semiconductor package100is to be mounted, through solder bumps6provided on a lower surface of film substrate2. Although nine chips1are stacked here, a required number of chips1can be stacked in order to correspond to a variety of product specifications without changing the area of semiconductor package100. Such a semiconductor package is called a CSP (Chip Size Package), and semiconductor package100will be hereinafter referred to as “CSP100.”

In order to electrically connect stacked chips1to one another, a silicon through-hole electrode (hereinafter referred to as “TSV”: Through Silicon Via) is formed by filling a conductive material in a through-hole provided in a semiconductor substrate made of silicon. As illustrated inFIG. 2, TSVs9formed in each chip8of wafer7are disposed in X and Y directions in TSV region11provided separately from each semiconductor element region10. Here, semiconductor element regions10are arranged in four places by way of example. Two lines of TSVs9are disposed in the X direction and one array of TSVs9is disposed in the Y direction in TSV region11between respective semiconductor element regions10. The arrangement of TSV region11and TSVs9is not limited to this configuration, and may be changed in various ways, according to the design specification of chip1. The phrase “semiconductor device” as used hereinafter includes a TSV.

As illustrated inFIG. 1B, semiconductor devices in chip1are provided in semiconductor element region10and TSV region11. Semiconductor element region10comprises cell array portion12and peripheral circuit portion13. Here, a DRAM which is a memory element is illustrated as a semiconductor element in semiconductor element region10. The semiconductor element is not limited to a memory element, and may be a logic element or a mixed element of a memory element and a logic element. The semiconductor devices in semiconductor element region10correspond in configuration to the known memory elements or logic elements.

Each TSV9in TSV region11primarily comprises rear surface bump17made of copper (Cu), intermediate wiring26, and front surface bump28made of copper. First seed film18formed by sequentially depositing titanium (Ti) and copper (Cu) is provided on an upper surface of rear surface bump17. A lower surface of rear surface bump17is covered with rear surface plated layer16containing nickel (Ni) as the primary constituent thereof. Likewise, second seed film27formed by sequentially depositing titanium (Ti) and copper (Cu) serving as barrier films is provided on a lower surface of front surface bump28. An upper surface of front surface bump28is covered with front surface plated layer29which is an alloy containing tin (Sn) as the primary constituent thereof.

Intermediate wiring layer26comprises first wiring19, second wiring21, third wiring23, and fourth wiring25made of tungsten (W) or aluminum (Al), and first contact plug20, second contact plug22, and third contact plug24made of tungsten, so as to electrically connect the interconnects to one another. These wirings and contacts are not formed separately and are formed concurrently with the components of semiconductor element region10by using the same material as the components of semiconductor element region10.

In addition, first wiring19, second wiring21, third wiring23, fourth wiring25, first contact plug20, second contact plug22, and third contact plug24are isolated from the components of semiconductor element region10by first interlayer insulating film30, second interlayer insulating film31, third interlayer insulating film32, fourth interlayer insulating film33, fifth interlayer insulating film34, and sixth interlayer insulating film35which are silicon oxide films or silicon nitride films. Fourth wiring25is covered with first passivation film36which is an oxygen-containing silicon nitride film (SiON) and second passivation film37which is a heat-resistant thermoplastic resin as typified by polyimide. In the present exemplary embodiment, second interlayer insulating film31is formed into a laminated structure including a silicon oxide film and a silicon nitride film. Also hereinafter, first interlayer insulating film30to sixth interlayer insulating film35, first passivation film36, and second passivation film37may be collectively referred to as “TSV insulating films38.”

These TSV insulating films38are also provided concurrently with the components of semiconductor element region10by using the same materials as the components of semiconductor element region10. However, insulating ring15is formed separately so as to surround front surface bump17, by using an insulating film which is a silicon oxide film or a silicon nitride film. Exposed front surface bump28and rear surface bump17are protrudingly provided respectively on the front and rear surfaces of chip1provided with such components as described above. By connecting rear surface bump17in upper-layer chip1aand front surface bump28in lower-layer chip1bto each other through rear surface plated layer16of the front surface bump28and front surface plated layer29of the rear surface bump17, upper-layer chip la and lower-layer chip1bare electrically connected to each other. A gap between upper-layer chip1aand lower-layer chip1bis filled with filling material5to inhibit the ingress of mold material4and protect chips1.

Next, a manufacturing process of the semiconductor device according to the present exemplary embodiment will be described with reference toFIGS. 3 to 9.FIG. 3is a manufacturing flow showing main steps of the manufacturing process of the semiconductor device according to the present exemplary embodiment.FIGS. 4 to 9are cross-sectional views of the semiconductor device in the main steps shown inFIG. 3, and are based on the cross-sectional structure of upper-layer chip1aillustrated inFIG. 1B.

The manufacturing flow ofFIG. 3is classified into three main processes. A first process is a process carried out with the main surface of the semiconductor substrate facing up, a second process is a process carried out with the rear surface of the semiconductor substrate facing up, and a third process is a chip formation process (wafer dicing process). Here, the main surface of the semiconductor substrate refers to a surface of the semiconductor substrate on which semiconductor elements are provided and the rear surface is a surface on the opposite side of the main surface.

In the first process, as illustrated inFIG. 4, insulating ring15which is annular in plan view is first formed on main surface39of semiconductor substrate14(step A). In step A, a ring-shaped trench is formed in TSV region11of semiconductor substrate14by photolithography and dry etching, and then the trench is filled with an insulating film to form insulating ring15. The bottom face of insulating ring15is not exposed on rear surface40of semiconductor substrate14but is located inside semiconductor substrate14.

Next, as illustrated inFIG. 5, semiconductor elements41are formed on main surface39of semiconductor substrate14(step B). In step B, semiconductor elements41are formed in cell array section12and peripheral circuit section13of semiconductor substrate14. Concurrently, intermediate wiring26is formed in TSV region11by the same manufacturing method as that of semiconductor elements41.

Next, as illustrated inFIG. 6, front surface bump28and front surface plated layer29are formed on fourth wiring25contained in intermediate wiring26(step C). In step C, second seed film27is formed on a surface of fourth wiring25by using a sputtering method, and then front surface bump28and front surface plated layer29are formed on second seed film27by using a plating method. An upper surface of front surface plated layer29is planar at the end of plating.

Next, as illustrated inFIG. 6, semiconductor substrate14is heated by a reflow method to reshape the upper surface of front surface plated layer29into a dome-like shape (step D).

Next, as illustrated inFIG. 7, supporting substrate43made of glass with the same diameter as semiconductor substrate14(wafer) is bonded to the main surface39side thereof by adhesion layer42, so as to cover front surface plated layer29and second passivation film37(step E). In addition, rear surface40of semiconductor substrate14is ground to expose the bottom face of insulating ring15at rear surface40(step F). Supporting substrate43functions to prevent contaminants from sticking to front surface bump28and the like formed above the main surface39side of semiconductor substrate14at the time of grinding rear surface40of semiconductor substrate14, and to compensate for the mechanical strength of thinned semiconductor substrate14due to the ground of it. This function also applies in the subsequent second process. A thickness from thinned semiconductor substrate14A by grinding to supporting substrate43is set to be the same as the thickness of semiconductor substrate14before grinding, so that the semiconductor substrate with supporting substrate43can be handled in the same way as semiconductor substrate14alone is handled even if supporting substrate43is bonded thereto.

In the second process, as illustrated inFIG. 8, rear surface bump17is formed inside insulating ring15(step G). In practice, rear surface bump17is formed with rear surface40facing up, as described above, by inverting semiconductor substrate14. However,FIG. 8is also drawn with rear surface40facing down, so that newly processed regions inFIGS. 4 to 7can be easily recognized. Here, bump hole44which penetrates through semiconductor substrate14and exposes a part of first wiring19is formed inside insulating ring15by photolithography and dry etching. Next, the inner wall of bump hole44are covered with first seed film18formed by a sputtering method, and then rear surface bump17and rear surface plated layer16are formed by a plating method (step G).

In the third process, a dicing film, which is not illustrated, is attached to rear surface40of semiconductor substrate14(step H).

Next, as illustrated inFIG. 9, supporting substrate43is irradiated with laser light. Thus, supporting substrate43is separated from semiconductor substrate14by taking advantage of the effect that laser light having transmitted through supporting substrate43reduces the adhesion force of adhesion layer42, thereby exposing front surface bump28and front surface plated layer29on the main surface side of semiconductor substrate14(step I).

Next, as illustrated inFIG. 9, the wafer is diced with a dicer. The dicing film is peeled off from semiconductor substrate14by picking up chips diced and separated from the wafer, thereby exposing rear surface bump17and rear surface plated layer16(step J). The formation of TSVs9is completed here and the resultant structure is moved to a subsequent chip-stacking process to form above-described CSP100.

Next, a method for manufacturing a TSV which is a semiconductor device according to the present exemplary embodiment will be described with reference toFIGS. 10 to 22.FIGS. 10 to 22are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the present exemplary embodiment.FIGS. 23 to 25are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the related art.FIG. 26is a cross-sectional view illustrating a second structure of the semiconductor device according to the present exemplary embodiment. These cross-sectional views are shown with rear surface40of semiconductor substrate14facing up, in order to describe a method for manufacturing rear surface bumps constituting TSVs of the semiconductor device.

FIG. 10is a cross-sectional view illustrating TSV region11inFIG. 7. As illustrated inFIG. 10, insulating ring15is formed in semiconductor substrate14, and intermediate wiring26is formed in TSV insulating film38underneath semiconductor substrate14. Here, the configurations of TSV insulating film38and intermediate wiring26are as described inFIG. 1B. Front surface bump28is formed underneath fourth wiring25constituting intermediate wiring26, and the lower surface of front surface bump28is covered with dome-like front surface plated layer29. In addition, front surface bump28and front surface plated layer29are covered with supporting substrate43bonded with adhesion layer42.

As illustrated inFIG. 11, insulating film45made of a silicon nitride film is formed on an upper surface of semiconductor substrate14by a CVD method. In addition, photoresist46is applied onto insulating film45to form opening47for a mask, which is circular in plan view by photolithography. Opening47for a mask is located inside insulating ring15and opening dimension X1thereof is 11 μm. A part of insulating film45is exposed through opening47for a mask.

As illustrated inFIG. 12, insulating film45exposed on the bottom of opening47for a mask, semiconductor substrate14underlying insulating film45, and first interlayer insulating film30are etched by dry etching, thereby forming bump hole44with depth Z1of 35 μm. At this time, dry etching is performed in five steps, and dry etching conditions in each step are as follows:

That is, in a first step, source power is set to 2500 W, bias power is set to 300 W, reaction chamber temperature is set to −10° C., and reaction chamber pressure is set to 30 mTorr. Sulfur hexafluoride (SF6) is used as a process gas and the flow rate thereof is set to 200 sccm (Standard Cubic Centimeter per Minute) to perform treatment for 30 seconds. The conditions of the first step are not limited to these settings, but may be set so that, for example, the source power is 1500 W to 3000 W, the bias power is 100 W to 300 W, the reaction chamber temperature is −10° C. to 0° C., the reaction chamber pressure is 20 mT to 90 mT, the process gas flow rate is 50 sccm to 500 sccm, and the treatment time is 5 to 60 seconds. In addition, as the process gas, a mixed gas of SF6and C4F8or a mixed gas of SF6and CHF3may be used instead of SF6.

In a second step, the source power is set to 2500 W, the bias power is set to 0 W, the reaction chamber temperature is set to −10° C., and the reaction chamber pressure is set to 50 mTorr. Perfluorocyclobutane (C4F8) was used as the process gas and the flow rate thereof was set to 100 sccm to perform treatment for one second. The conditions of the second step are not limited to these settings, but may be set so that, for example, the source power is 1500 W to 3000 W, the bias power is 0 W, the reaction chamber temperature is −10° C. to 0° C., the reaction chamber pressure is 20 mT to 90 mT, the process gas flow rate is 50 sccm to 500 sccm, and the treatment time is 0.5 to 5 seconds. In addition, as the process gas, CHF3may be used instead of C4F8.

In a third step, the source power is set to 2500 W, the bias power is set to 100 W, the reaction chamber temperature is set to −10° C., and the reaction chamber pressure is set to 50 mTorr. Sulfur hexafluoride (SF6) is used as the process gas and the flow rate thereof was set to 100 sccm to perform treatment for one second. The conditions of the third step are not limited to these settings, but may be set so that, for example, the source power is 1500 W to 3000 W, the bias power is 200 W to 1000 W, the reaction chamber temperature is −10° C. to 0° C., the reaction chamber pressure is 20 mT to 90 mT, the process gas flow rate is 50 sccm to 500 sccm, and the treatment time is 0.5 to 5 seconds. In addition, as the process gas, a Cl gas may be used instead of SF6.

In a fourth step, the source power is set to 2500 W, the bias power is set to 0 W, the reaction chamber temperature is set to −10° C., and the reaction chamber pressure is set to 50 mTorr. Sulfur hexafluoride (SF6) is used as the process gas and the flow rate thereof was set to 100 sccm to perform treatment for one second. The conditions of the fourth step are not limited to these settings, but may be set so that, for example, the source power is 1500 W to 3000 W, the bias power is 0 W, the reaction chamber temperature is −10° C. to 0° C., the reaction chamber pressure is 20 mT to 90 mT, the process gas flow rate is 50 sccm to 500 sccm, and the treatment time is 0.5 to 5 seconds. In addition, as the process gas, a Cl gas may be used instead of SF6.

In a fifth step, the source power is set to 2500 W, the bias power is set to 500 W, the reaction chamber temperature is set to −10° C., and the reaction chamber pressure is set to 50 mTorr. Trifluoromethane (CHF3) and argon (Ar) are used as the process gases and the flow rates thereof were set to 450 sccm (CHF3) and 200 sccm (Ar), respectively, to perform treatment for 60 seconds. The conditions of the fifth step are not limited to these settings, but may be set so that, for example, the source power is 1500 W to 3000 W, the bias power is 300 W to 1500 W, the reaction chamber temperature is 10° C. to 0° C., the reaction chamber pressure is 20 mT to 90 mT, the flow rate of the process gases as a whole is 50 sccm to 500 sccm, and the treatment time is 10 to 300 seconds. In addition, as the process gases, a mixed gas of C4F8and Ar or a mixed gas of CF4and Ar may be used instead of a mixed gas of CHF3and Ar.

In this dry etching, as illustrated inFIG. 13, insulating film45exposed on the inner bottom face of opening47for a mask is first removed in the first step by using photoresist46as a mask, to form first opening48. A part of semiconductor substrate14is exposed on the inner bottom face of first opening48. Here, semiconductor substrate14is overetched in order to completely remove insulating film45on the inner bottom face of opening47for a mask. Consequently, the inner bottom face of first opening48reaches to the interior of semiconductor substrate14.

Next, as illustrated inFIG. 14, first protective film49is formed in the second step (step (a)), so as to cover the inner wall of first opening48. First protective film49is a polymer primarily comprising polytetrafluoroethylene ((CF2CF2)n), which is polymerized using perfluorocyclobutane by plasma energy. The primary constituent of such a polymer serving as a first protective film is dependent on a process gas used in the second step. The second step causes new second opening50to be formed in a region where first opening48had been provided.

Next, as illustrated inFIG. 15, first protective film49on the inner bottom face of second opening50is removed in the third step (step (b)) to expose a part of semiconductor substrate14. This third step causes new third opening51to be formed in a region where second opening50had been provided. Etching at this time works as anisotropic dry etching based on fluorine radicals and is performed so as to progress only in the depth direction (Z direction) of semiconductor substrate14. Consequently, first protective film49remains only on the inner side face of third opening51, thus forming into first protective film49A1. The final number of this reference numeral represents the frequency of dry etching in the third step. Accordingly, reference numeral49A1denotes a first protective film after first dry etching. Likewise, reference numeral49AXdenotes a first protective film after Xth dry etching.

Next, as illustrated inFIG. 16, semiconductor substrate14made of silicon (Si) is dry-etched in the fourth step (step (c)) to form bump hole44A1constituting bump hole44. The final number of this reference numeral represents the frequency of dry etching in the fourth step. Accordingly, reference numeral44A1denotes a bump hole formed by first dry etching. Likewise, reference numeral44AXdenotes a bump hole formed by Xth dry etching. Etching at this time works as isotropic dry etching based on fluorine radicals and is performed so as to progress not only in the depth direction (Z direction) of semiconductor substrate14but also in the horizontal direction (X direction). Consequently, the inner side face of bump hole44A1are not vertical but recessed in the X direction. The fourth step is finished at the same time as first protective film49A1disappears. Consequently, side surfaces of third opening51covered with first protective film49A1remain as they are without being etched.

Thereafter, as illustrated inFIG. 17, the second to fourth steps are repeated X times to form bump hole44AXin semiconductor substrate14. By way of more detailed description, bump hole44A2(not illustrated) to be formed subsequently to bump hole44A1can be formed in the following way. That is, first, first protective film49A2is formed on the inner side face of bump hole44A1by the second and third steps. Then, semiconductor substrate14exposed on the inner bottom face of bump hole44A1is etched by the fourth step, thereby forming bump hole44A2. Also in this fourth step, etching is finished before first protective film49A2disappears. Consequently, the inner side face of bump hole44A1covered with first protective film49A2remain as they are without being etched. Sequentially, as described above, the second to fourth steps are repeated X times to form bump hole44AX. As a result, continuous concave shape52(hereinafter referred to as scallop52) on the inner side face of bump hole44AXgenerates. Thus, scallop52becomes exposed on the inner wall of bump hole44AX.

Such dry etching as described above is known as a Bosch process for forming high-aspect ratio holes. The generation of scallops is unavoidable for holes formed by a Bosch process. In bump hole44AX, opening dimension Z2of scallop52is 0.1 μm and opening depth X2of scallop52is 0.3 μm. However, the bottom of bump hole44AXis fully overetched so that semiconductor substrate14does not remain on first interlayer insulating film30. Consequently, opening dimension Z3and opening depth X3of scallop52A are proportionally greater than those in other places by overetching amount, so as to be Z3=0.4 μm and X3=0.8 μm. Here, since overetching is performed by setting conditions so as to ensure a high etching selective ratio, the inner bottom face of bump hole44AXis positioned on a surface of first interlayer insulating film30. That is to say, if the cycle is repeated a plurality of times, an etching selective ratio of the isotropic etching in the fourth step (step (c)) of at least the last cycle for forming bump hole44AX, among the plurality of the cycles, is made higher than an etching selective ratio of the isotropic etching in the fourth step (step (c)) of the first cycle for forming bump hole44A1.

Next, first interlayer insulating film30exposed on the bottom of bump hole44AXis dry-etched in the fifth step to form second bump hole44F in first interlayer insulating film30. Consequently, as illustrated inFIG. 12, there is completed bump hole44comprising first bump hole44B (not illustrated) and second bump hole44F (not illustrated). At this time, sidewall protective film (hereinafter occasionally described as “second protective film”)53which is a reaction product of dry etching in the fifth step is formed so as to cover the inner side face of bump hole44, thereby preventing scallop52from becoming exposed. Second protective film53is a carbon and fluorine-containing polymer (CF polymer) primarily comprising carbon (C). The primary constituent of such a polymer serving as a second protective film is dependent on a process gas used in the fifth step. A part of the upper surface of first wiring19is exposed on the bottom of bump hole44.

As illustrated inFIG. 18, photoresist46is removed by plasma ashing. Plasma ashing conditions at this time are set so that the source power is 2000 W, the bias power is 300 W, the reaction chamber temperature is −10° C., and the reaction chamber pressure is 50 mTorr. Oxygen (O2), argon (Ar) and nitrogen (N2) are used as process gases and the flow rates thereof are set to 1000 sccm (O2), 400 sccm (Ar) and 100 sccm (N2), respectively. New bump hole44B is formed by this plasma ashing. In this plasma ashing, second protective film53which is a polymer primarily comprising carbon is also removed as with photoresist46. Since this plasma ashing is performed as anisotropic ashing in a normal-line direction of semiconductor substrate14by applying bias power, the process gases cannot reach to the inside of scallop52surrounded by semiconductor substrate14. Accordingly, a part of second protective film53covering the inside of scallop52remains as second protective film53A, thereby smoothening the inner side face of bump hole44B.

As illustrated inFIG. 23, plasma ashing in a related method is performed as isotropic ashing by setting both the source power and the bias power to 0 W. Consequently, second protective film53is completely removed from the inner side face of new bump hole44C, thus causing scallop52to become exposed.

Next, in the present exemplary embodiment, first seed film18A is formed by a sputtering method, so as to cover bump hole44B, as illustrated inFIG. 19. At this time, the inner wall surfaces of bump hole44B are smoothened because second protective film53A remains. Accordingly, first seed film18A having a uniform thickness can be formed without degrading the coverage (coatability) of first seed film18A. New bump hole44D is formed by this sputtering.

As illustrated inFIG. 24, scallop52is exposed on the inner wall of bump hole44C in the formation of first seed film18B by a related method. Accordingly, the coverage of first seed film18B degrades, and therefore, nonuniform first seed film18B is formed. Consequently, some portions of scallop52B are exposed on the inner wall of newly formed bump hole44E without being covered with first seed film18B.

Next, in the present exemplary embodiment, as illustrated inFIG. 20, photoresist54is applied onto the main surface of semiconductor substrate14, to form fourth opening55by photolithography. Fourth opening55is positioned so as to expose bump hole44D, and opening dimension X4of fourth opening55is made larger than dimension X1of first opening, so as to be 12 μm.

Next, in the present exemplary embodiment, as illustrated inFIG. 21, rear surface bump17and rear surface plated layer16are formed inside bump hole44D and fourth opening55by a plating method. At this time, first seed film18A having contact with rear surface bump17entirely covers the inner wall of bump hole44D. Accordingly, a plating solution of rear surface bump17uniformly wets and spreads over the surfaces of first seed film18A. Thus, it is possible to form rear surface bump17not containing any air bubbles (voids). As a result, rear surface bump17can be formed so as to have a diameter consistent with the design value of rear surface bump17A, thereby preventing an increase in wiring resistance. In addition, it is possible to inhibit the disconnection of rear surface bump17A leading to a product failure and thus inhibit a degradation in the yield.

As illustrated inFIG. 25, first seed film18B underlying rear surface bump17A does not entirely cover the interiors of bump hole44E in the formation of rear surface bump17A and rear surface plated layer16A by a related method, and scallops52B are partially exposed. Accordingly, a plating solution of rear surface bump17A does not uniformly wet and spread over the surfaces of first seed film18A, thus giving rise to voids56within rear surface bump17A. Due to voids56, minimum value X5of the diameter of rear surface bump17A becomes smaller than X1which is a design value.

As illustrated inFIG. 22, photoresist54is removed by a wet etching method. In addition, first seed film18A no longer necessary to be present on insulating film45is removed by a wet etching method, in order to allow first seed film18to remain only on the lower surface of rear surface bump17. Consequently, there is completed TSV9illustrated inFIG. 9.

FIG. 26illustrates a second structure according to the present exemplary embodiment. InFIG. 22, insulating ring15is provided in semiconductor substrate14surrounding rear surface bump17. However, inFIG. 26, a structure is adopted in which second insulating film57is provided inside bump hole44in place of the insulating ring. The inner side face of bump hole44B are smoothened because second protective film53A remains, as described in the present exemplary embodiment. Accordingly, such a structure as described above can be realized by allowing formed second insulating film57to have a uniform film thickness without being disturbed by scallop52. In the second structure, it is possible to eliminate a region in which insulating ring15is to be formed and, thereby, reduce the area of TSV region11. Consequently, it is possible to make the packaging density of a semiconductor chip higher in the second structure than in the first structure.

In a method for forming the second structure, bump hole44B is formed by skipping the above-described formation process of insulating ring15and performing the processing treatments illustrated inFIGS. 11 to 18. Next, insulating film57A (not illustrated) which is a silicon oxide film is formed by a CVD method, so as to cover bump hole44B. Next, insulating film57A is etched back so that the insulating film57A remains only on the inner side face of bump hole44B, thereby forming second insulating film57. After going through the steps illustrated inFIG. 19and subsequent figures, there can be obtained TSV58. Also in the case of TSV58, first seed film18can be formed with a uniform film thickness on second insulating film57, and therefore, no such voids as illustrated inFIG. 25arise.

In addition, while not specifically claimed in the claim section, the applications reserve the right to include in the claim section at any appropriate time the following semiconductor device:1. A semiconductor device including a through-hole electrode, the semiconductor device comprising:

a semiconductor substrate;

a first interlayer insulating film formed on a main surface of the semiconductor substrate;

an intermediate wiring, a second seed film, and a front surface bump formed sequentially on the first interlayer insulating film;

a sidewall protective film formed on an inner side face of a first bump hole and a second bump hole, the first bump hole being formed so as to penetrate through the semiconductor substrate and including the inner side face having a concave shape and the second bump hole penetrating through the first interlayer insulating film to communicate with the first bump hole;

a first seed film formed on the sidewall protective film in the first and second bump holes; and

a rear surface bump buried in the first and second bump holes.2. The semiconductor device according to the above 1,

wherein the sidewall protective film is formed so as to fill up the concave shape in the inner side face of the first bump.3. The semiconductor device according to the above 1,

wherein an opening diameter at rear surface of the semiconductor substrate is larger than an opening diameter at main surface of the semiconductor substrate.4. The semiconductor device according to the above 1, further comprising an insulating ring formed so as to penetrate through the semiconductor substrate in a thickness direction thereof and so as to surround the rear surface bump within the semiconductor substrate.5. The semiconductor device according to the above 1, further comprising a second insulating film between the sidewall protective film and the first seed film inside the first and second bump holes.6. The semiconductor device according to the above 1, further comprising a DRAM formed in the semiconductor substrate.7. The semiconductor device according to the above 1,

wherein the semiconductor device comprises a plurality of semiconductor chips,

each semiconductor chip includes the through-hole electrode, and

the plurality of the semiconductor chips are stacked through the through-hole electrodes.