Sense amplifiers with high voltage swing

A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.

TECHNICAL FIELD

The present invention relates generally to sense amplifiers, and more particularly, to sense amplifier circuits with high voltage swing for enhanced sensitivity.

BACKGROUND OF THE INVENTION

Referring toFIG. 1, a sense amplifier100of the prior art is used for determining the bit data of a core cell102that is typically part of a memory device. A current level (IR+Δi) through the core cell102varies depending on the bit data stored therein. A core bit voltage VCBITis generated at a source of a first NMOSFET (N-channel metal oxide semiconductor field effect transistor)104from the core cell102.

The source of the first NMOSFET104and the core cell102are coupled to a negative input108of a first differential amplifier106that compares the core bit voltage VCBITwith a regulation reference voltage VREG—REFapplied on a positive input110of the first differential amplifier106. The output of the first differential amplifier106is coupled to a gate of the first NMOSFET104for stably maintaining the core bit voltage VCBIT.

A drain of the first NMOSFET104is coupled to a positive voltage supply VCCvia a first resistor112. A core output voltage VCOREis generated at the drain of the first NMOSFET104and is applied on a negative input of a comparator120.

The sense amplifier100also includes a second NMOSFET122having a source coupled to a reference cell124. A current level IRflows through the reference cell124, and a reference bit voltage VRBITis generated at the source of the second NMOSFET122from the reference cell124.

The source of the second NMOSFET122and the reference cell124are coupled to a negative input126of a second differential amplifier128that compares the reference bit voltage VRBITwith the regulation reference voltage VREG—REFapplied on a positive input130of the second differential amplifier128. The output of the second differential amplifier130is coupled to a gate of the second NMOSFET122for stably maintaining the reference bit voltage VRBIT.

A drain of the second NMOSFET122is coupled to a positive voltage supply VCCvia a second resistor132. A reference output voltage VREFis generated at the drain of the second NMOSFET122and is applied on a positive input of the comparator120.

The output of the comparator generates an output signal OUT that is a logical high state or a logical low state depending on the core output voltage VCOREcompared to the reference output voltage VREF. Such a logical high or low state of the output signal OUT indicates the bit data stored within the core cell102.

The current (IR+Δi) through the core cell has a current offset component Δi from the reference current IRthrough the reference cell124that varies depending on the bit data stored within the core cell102. Such a variable current offset component Δi determines the core output voltage VCOREwhich in turn determines the logical state of the output signal OUT.

Unfortunately, the core output voltage VCOREin the sense amplifier100of the prior art has limited voltage swing because the core bit voltage VCBITis relatively high and substantially close to the positive supply voltage VCCfor proper operation of the core cell102. For example, when the positive supply voltage VCCis about 1.8 Volts, the core bit voltage VCBITis about 1.5 Volts for proper operation of the core cell102. In addition, a voltage drop is generated across the first resistor112. Thus for such example voltages, the core output voltage VCOREhas a voltage swing of from about 0.2 Volts to about 0.3 Volts for maintaining the first NMOSFET104in saturation.

Such a low voltage swing of the core output voltage VCOREdisadvantageously results in low sensitivity of the sense amplifier100in the prior art. Thus, sense amplifiers having higher voltage swing are desired for higher sensitivity.

SUMMARY OF THE INVENTION

In one embodiment of the present invention, a sense amplifier includes a reference voltage generator for generating a reference output voltage. In addition, the sense amplifier also includes a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage. The core front-end stage is coupled to a current conducting device for converting a core current through the current conducting device to a core bit voltage. The core back-end stage is coupled to the core front-end stage for converting the core bit voltage to the core output voltage having higher voltage swing from the core bit voltage.

The sense amplifier may be used to particular advantage when the current conducting device is a core cell of a memory device. However, the present invention may also be used for sensing the current level through any type of current conducting device.

In another embodiment of the present invention, the core output voltage generator includes a plurality of amplifier transistors each conducting a portion of a core current through the current conducting device. A gate of a selected one of the amplifier transistors has the core output voltage generated thereon. A width to length (W/L) ratio of the selected amplifier transistor is minimized such that the core output voltage has high voltage swing.

In this manner, such sense amplifiers have high voltage swing for high sensitivity. These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.

The figures referred to herein are drawn for clarity of illustration and are not necessarily drawn to scale. Elements having the same reference number inFIGS. 1,2,3,4,5,6,7, and8refer to elements having similar structure and function.

DETAILED DESCRIPTION

FIG. 2shows a circuit diagram of a sense amplifier200having high voltage swing according to an embodiment of the present invention. The sense amplifier200includes a reference voltage generator202for generating a reference output voltage VREF, and includes a core output voltage generator204for generating a core output voltage VCORE.

The reference voltage generator202includes a reference front-end stage206comprised of a reference regulation transistor MRP1coupled to a reference cell208having a reference current IRflowing there-through. A reference bit voltage VRBITis generated at a node for coupling a drain of the first reference PMOSFET (P-channel metal oxide semiconductor field effect transistor) MRP1and the reference cell208. A source of the first reference PMOSFET MRP1is coupled to a positive power supply VCC.

The reference voltage generator202also includes a reference back-end stage210coupled to the reference front-end stage206. The reference back-end stage210is comprised of a second reference PMOSFET MRP2and a first reference NMOSFET (N-channel metal oxide semiconductor field effect transistor) MRN1. The second reference PMOSFET MRP2has a gate coupled to the gate of the first reference PMOSFET MRP1, and has a source coupled to the positive power supply VCC. A drain of the second reference PMOSFET MRP2is coupled to a drain of the first reference NMOSFET MRN1at a node for generating the reference output voltage VREF.

A gate and the drain of the first reference NMOSFET MRN1are coupled together, and a source of the first reference NMOSFET MRN1is coupled to a low power supply such as a ground node. The first and second reference PMOSFETs MRP1and MRP2and the first reference NMOSFET MRN1each have the reference current IRflowing therethrough.

The gate and drain of the first reference PMOSFET MRP1are coupled to a reference feed-back regulator212that stabilizes the reference bit voltage VRBIT. In the example embodiment ofFIG. 2, the reference feed-back regulator212is a differential amplifier comprised of second, third, and fourth reference NMOSFETs MRN2, MRN3, and MRN4, respectively, and third and fourth reference PMOSFETs MRP3and MRP4, respectively.

Sources of the third and fourth reference PMOSFETs MRP3and MRP4are coupled to the positive power supply VCC, and gates of the third and fourth reference PMOSFETs MRP3and MRP4are coupled together. A drain of the third reference PMOSFET MRP3is coupled to a drain of the second reference NMOSFET MRN2, and a drain of the fourth reference PMOSFET MRP4is coupled to a drain of the third reference NMOSFET MRN3. The gate and the drain of the fourth reference PMOSFET MRP4are coupled together.

The drains of the third reference PMOSFET MRP3and the second reference NMOSFET MRN2are coupled to the gates of the first and second reference PMOSFETs MRP1and MRP2. A gate of the second reference NMOSFET MRN2has a regulation reference voltage VREG_REF applied thereon. A gate of the third reference NMOSFET MRN3is coupled to the reference cell208such that the reference bit voltage VRBITis applied thereon. Sources of the second and third reference NMOSFETs MRN2and MRN3are coupled together to a drain of the fourth reference NMOSFET MRN4.

The gate of the fourth reference NMOSFET MRN4has a bias voltage VBIASapplied thereon, and the source of the fourth reference NMOSFET MRN4is coupled to a low power supply such as the ground node. The bias voltage VBIASat the gate of the fourth reference NMOSFET MRN4sets the bias current through the reference MOSFETs MRP3, MRP4, MRN2, and MRN3of the differential amplifier212. In addition, the differential amplifier212acts to stabilize the reference bit voltage VRBITby feed-back.

The core output voltage generator204includes a core front-end stage216comprised of an amplifier regulation transistor MCP1coupled to a core cell218having a core current (IR+Δi) flowing there-through. The core current has a current deviation component Δi offset from the reference current IR. Such a current deviation component Δi depends on the bit data stored in the core cell218.

The core cell218is typically part of a memory device for example. A core bit voltage VCBITis generated at a node for coupling a drain of the first amplifier PMOSFET MCP1and the core cell218. A source of the first amplifier PMOSFET MCP1is coupled to a positive power supply VCC.

The core output voltage generator204also includes a core back-end stage220coupled to the core front-end stage216. The core back-end stage220is comprised of a second amplifier PMOSFET MCP2and a first amplifier NMOSFET MCN1. The second amplifier PMOSFET MCP2has a gate coupled to the gate of the first amplifier PMOSFET MCP1, and has a source coupled to the positive power supply VCC. A drain of the second amplifier PMOSFET MCP2is coupled to a drain of the first amplifier NMOSFET MCN1at a node for generating the core output voltage VCORE.

A gate and the drain of the first amplifier NMOSFET MCN1are coupled together, and a source of the first amplifier NMOSFET MCN1is coupled to a low power supply such as the ground node. The first and second amplifier PMOSFETs MCP1and MCP2and the first amplifier NMOSFET MCN1each have the core current (IR+Δi) flowing there-through.

The gate and drain of the first amplifier PMOSFET MCP1are coupled to a core feed-back regulator222that stabilizes the core bit voltage VCBIT. In the example embodiment ofFIG. 2, the core feed-back regulator222is a differential amplifier comprised of second, third, and fourth amplifier NMOSFETs MCN2, MCN3, and MCN4, respectively, and third and fourth amplifier PMOSFETs MCP3and MCP4, respectively.

Sources of the third and fourth amplifier PMOSFETs MCP3and MCP4are coupled to the positive power supply VCC, and gates of the third and fourth amplifier PMOSFETs MCP3and MCP4are coupled together. A drain of the third amplifier PMOSFET MCP3is coupled to a drain of the second amplifier NMOSFET MCN2, and a drain of the fourth amplifier PMOSFET MCP4is coupled to a drain of the third amplifier NMOSFET MCN3. The gate and the drain of the fourth amplifier PMOSFET MCP4are coupled together.

The drains of the third amplifier PMOSFET MCP3and the second amplifier NMOSFET MCN2are coupled to the gates of the first and second amplifier PMOSFETs MCP1and MCP2. A gate of the second amplifier NMOSFET MCN2has the regulation reference voltage VREG_REF applied thereon. A gate of the third amplifier NMOSFET MCN3is coupled to the core cell218such that the core bit voltage VCBITis applied thereon. Sources of the second and third amplifier NMOSFETs MCN2and MCN3are coupled together to a drain of the fourth amplifier NMOSFET MCN4.

The gate of the fourth amplifier NMOSFET MCN4has a bias voltage VBIASapplied thereon, and the source of the fourth amplifier NMOSFET MCN4is coupled to a low power supply such as the ground node. The bias voltage VBIASat the gate of the fourth amplifier NMOSFET MCN4sets the bias current through the core MOSFETs MCP3, MCP4, MCN2, and MCN3of the differential amplifier222. In addition, the differential amplifier222acts to stabilize the core bit voltage VCBITby feed-back.

Furthermore, the sense amplifier200includes a comparator230which is implemented as a differential amplifier for example. The comparator230has a positive input with the reference output voltage VREFapplied thereon, and has a negative input with the core output voltage VCOREapplied thereon. The comparator230generates the output signal OUT from comparing the core output voltage VCOREwith the reference output voltage VREF. The logical state of the output signal OUT indicates the bit data stored in the core cell218.

In this manner, referring toFIG. 2, note that the core front-end stage216does not have any resistor in series with the voltage regulation transistor MCP1. Thus, the core bit voltage VCBITmay be relatively high near the high power supply voltage VCCwith the voltage regulation transistor MCP1still operating in saturation. In addition, the core output voltage VCOREis generated at the subsequent back-end stage220that is not directly coupled to the core cell218. Thus, the core output voltage VCOREis not restricted from the core bit voltage VCBITsuch that the core output voltage VCOREhas higher voltage swing with the MOSFETs MCP1and MCN1still operating in saturation. Such higher voltage swing is advantageous for enhanced sensitivity of the sense amplifier200.

In the sense amplifier200of FIG.2:
ΔV=VREF−VCORE; and
ΔV=Δi/gml,
with gmlbeing the transconductance of each of the first reference and amplifier NMOSFETs MRN1and MCN1.

In addition, the sense amplifier200ofFIG. 2has high signal to noise ratio for both balanced and unbalanced power-supply noise within the reference voltage generator202and the core output voltage generator204. Balanced power-supply noise refers to noise at the power-supply that is present substantially equally within each of the reference voltage generator202and the core output voltage generator204. Unbalanced power-supply noise refers to noise at the power-supply that is present unequally only in one of the reference voltage generator202and the core output voltage generator204.

Referring toFIG. 2, if either balanced or unbalanced noise is present at the power supply VCCof the reference voltage generator202, the effect of such noise appears at the source of the second reference PMOSMFET MRP2. In addition, a similar effect from such noise appears at the gate of the second reference PMOSMFET MRP2through the reference feed-back regulator212. Such effects at the source and the gate of the second reference PMOSFET MRP2cancel each-other away to not have substantial effect on the reference output voltage VREF.

Similarly, if either balanced or unbalanced noise is present at the power supply VCCof the core output voltage generator204, the effect of such noise appears at the source of the second amplifier PMOSMFET MCP2. In addition, a similar effect from such noise appears at the gate of the second amplifier PMOSMFET MCP2through the amplifier feed-back regulator222. Such effects at the source and the gate of the second amplifier PMOSFET MCP2cancel each-other away to not have substantial effect on the core output voltage VCORE.

Furthermore, referring toFIG. 7, the MOSFETs of the reference voltage generator202may be appropriately sized such that the reference voltage generator202provides the reference output voltage VREFfor a plurality of core output voltage generators. Referring toFIG. 7, the second reference PMOSFET MRP2is sized with a W/L (width to length) ratio that is N times the W/L ratio of the first reference PMOSFET MRP1. Thus, a current of N×IRflows through the second reference PMOSFET MRP2.

Further referring toFIG. 7, the reference output voltage VREFfrom the reference voltage generator202is coupled to a respective positive input of N comparators230_1,230_2, . . . , and230_N. Each of the N comparators230_1,230_2, . . . , and230_N has a respective negative input coupled to a respective one of the core output voltage generators204_1,204_2, . . . , and204_N, respectively. Each of the core output voltage generators204_1,204_2, . . . , and204_N is implemented similarly to the core output voltage generator204ofFIG. 2to generate a respective one of the core output voltages VCORE—1, VCORE—2, . . . , and VCORE—N, respectively. Each of the comparators230_1,230_2. . . , and230_N compares a respective one of the core output voltages VCORE—1, VCORE—2, . . . , and VCORE—N, respectively, to the reference output voltage VREFfor generating a respective output signal OUT1, OUT2, . . . , and OUTN.

In this manner, the reference voltage generator202is used for the plurality of core output voltage generators204_1,204_2, . . . , and204_N for saving space of the integrated circuit of the sense amplifier200ofFIG. 7. Furthermore, because a higher level of current N×IRflows through the second reference PMOSFET MRP2, the sense amplifier200ofFIG. 7operates at higher speed.

FIG. 3shows a circuit diagram of a sense amplifier200A according to another embodiment of the present invention. Elements having the same reference number inFIGS. 2 and 3refer to elements having similar structure and function. Thus, the reference and core front-end stages206and216and the reference and core feed-back regulators212and222are substantially similar inFIGS. 2 and 3.

However, the reference and core back-end stages210A and220A ofFIG. 3are different from the reference and core back-end stages210and220ofFIG. 2. Referring toFIG. 3, reference and amplifier bias resistors RBR and RBC, respectively, replace the first reference and amplifier NMOSFETs MRN1and MCN1, respectively. Thus, the reference bias resistor RBR is coupled between the drain of the second reference PMOSFET MRP2and the ground node, and the amplifier bias resistor RBC is coupled between the drain of the second amplifier PMOSFET MCP2and the ground node.

The sense amplifier200A ofFIG. 3operates similarly to the sense amplifier200ofFIG. 2. If each of the reference and amplifier bias resistors RBR and RBC has a resistance value of R, then in the sense amplifier200A of FIG.3:
ΔV=VREF−VCORE; and
ΔV=Δi*R.

Similar to the sense amplifier200ofFIG. 2, the sense amplifier200A ofFIG. 3has high signal to noise ratio for both balanced and unbalanced noise within the reference voltage generator202and the core output voltage generator204. Furthermore, referring toFIG. 8, the reference voltage generator202may be used for the plurality of core output voltage generators204_1,204_2, . . . , and204_N. InFIG. 8, each of the core output voltage generators204_1,204_2, . . . , and204_N is implemented similarly to the core output voltage generator204ofFIG. 3.

In addition, the second reference PMOSFET MRP2is sized with a W/L (width to length) ratio that is N times the W/L ratio of the first reference PMOSFET MRP1. In addition, the resistance value of the reference bias resistor RBR is R/N when the resistance value of the amplifier bias resistor RBC within each of the core output voltage generators204_1,204_2, . . . , and204_N is R. Thus, a current of N×IRflows through the second reference PMOSFET MRP2inFIG. 8.

In this manner, the reference voltage generator202is used for the plurality of core output voltage generators204_1,204_2, . . . , and204_N for saving space of the integrated circuit of the sense amplifier200A ofFIG. 8. Furthermore, because a higher level of current N×IRflows through the second reference PMOSFET MRP2, the sense amplifier200A ofFIG. 8operates at higher speed.

FIG. 4shows a circuit diagram of a sense amplifier200B according to another embodiment of the present invention. Elements having the same reference number inFIGS. 2 and 4refer to elements having similar structure and function. Thus, the reference and core front-end stages206and216and the reference and core feed-back regulators212and222are substantially similar inFIGS. 2 and 4.

However, the reference and core back-end stages210B and220B ofFIG. 4are different from the reference and core back-end stages210and220ofFIG. 2. Referring toFIG. 4, the reference output voltage VREFfrom the reference back-end stage210B is also coupled to the gate of the first amplifier NMOSFET MCN1of the core back-end stage220B. In addition, the gate and the drain of the first amplifier NMOSFET MCN1are not coupled together.

Instead, the drains of the first amplifier NMOSFET MCN1and the second amplifier PMOSFET MCP2are coupled together at a node that generates the core output voltage VCOREinFIG. 4. Such a node is coupled to the negative input of the comparator230. Similar to the sense amplifier200ofFIG. 2, the sense amplifier200B ofFIG. 4also generates an output signal OUT at the output of the comparator230with a logical state that indicates the bit data stored in the core cell218.

In addition referring toFIG. 4, the core front-end stage216does not have any resistor in series with the voltage regulation transistor MCP1. Thus, the core bit voltage VCBITmay be relatively high near the high power supply voltage VCCwith the voltage regulation transistor MCP1still operating in saturation. In addition, the core output voltage VCOREis generated at the subsequent back-end stage220that is not directly coupled to the core cell218. Thus, the core output voltage VCOREis not restricted from the core bit voltage VCBITsuch that the core output voltage VCOREhas higher voltage swing with the MOSFETs MCP1and MCN1still operating in saturation. Such higher voltage swing is advantageous for enhanced sensitivity of the sense amplifier200B.

FIG. 5shows a circuit diagram of a sense amplifier200C according to another embodiment of the present invention. Elements having the same reference number inFIGS. 4 and 5refer to elements having similar structure and function. Thus, the reference and core front-end stages206and216and the reference and core feed-back regulators212and222are substantially similar inFIGS. 4 and 5.

However, the reference and core back-end stages210C and220C ofFIG. 5are different from the reference and core back-end stages210B and220B ofFIG. 4. Referring toFIGS. 4 and 5, in the sense amplifier200C ofFIG. 5, a reference noise immunity resistor RNR is coupled between the source of the first reference NMOSFET MRN1and the ground node223. Furthermore in the sense amplifier200C ofFIG. 5, an amplifier noise immunity resistor RNC is coupled between the source of the first amplifier NMOSFET MCN1and the ground node223.

Including such resistors RNR and RNC is advantageous for suppressing a noise or mismatch component Δi′ of Δi, resulting from noise at the ground node223or mismatch between the NMOSFETs MRN1and MCN1. For example, assume that noise at the ground node223results in a voltage bounce of 20 milli-Volts at the ground node223. In addition, assume that the transconductance gmlof each of the NMOSFETs MRN1and MCN1is about 1 milli-Amps/Volt. In that case, the noise component Δi′ from such voltage bounce is as follows in the sense amplifier200B of FIG.4:
Δi′=gml×20 milli-Volts=20 μA.

In contrast, for the same voltage bounce at the ground node223in the sense amplifier200C ofFIG. 5, the noise component Δi′ is reduced from the resistors RNR and RNC as follows:
Δi′≈20 milli-Volts/15 kilo-Ohms=1.3 μA.
with each of the resistors RNR and RNC having a resistance value of 15 kilo-Ohms for example inFIG. 5. Thus, such resistors RNR and RNC reduce the effect of noise on Δi inFIG. 5. The sense amplifier200C ofFIG. 5may also be implemented with the ground node223being a low supply voltage source VSSinstead. In that case, the resistors RNR and RNC reduce the effect of noise at the low supply voltage source VSSinFIG. 5.

Similarly, the NMOSFETs MRN1and MCN1may be mismatched from processing variations to have a difference in threshold voltage ΔVthwhich may be 20 milli-Volts for example. The mismatch component Δi′ is similar as described above for the voltage bounce. Thus, the resistors RNR and RNC reduce the effect of such MOSFET mismatch on Δi inFIG. 5. Otherwise, the sense amplifier200C ofFIG. 5operates similarly to the sense amplifier200B ofFIG. 4.

FIG. 6shows a circuit diagram of a sense amplifier300according to another embodiment of the present invention. Elements having the same reference number inFIGS. 2 and 6refer to elements having similar structure and function. Thus, the reference and core feed-back regulators212and222are substantially similar inFIGS. 2 and 6.

However, the sense amplifier300ofFIG. 6is not implemented with front-end and back-end stages. Rather, referring toFIG. 6, the reference voltage generator202includes a plurality of reference PMOSFETs MRP1and MRP2for collectively conducting the reference current IRthrough the reference cell208. Thus, the sum of the currents through the reference PMOSFETs MRP1and MRP2is the reference current IRthrough the reference cell208. The reference feed-back regulator212is coupled between the gates of the reference PMOSFETs MRP1and MRP2and the reference cell208for stabilizing the reference bit voltage VRBIT.

Additionally referring toFIG. 6, the core output voltage generator204includes a plurality of amplifier PMOSFETs MCP1and MCP2for collectively conducting the core current (IR+Δi) through the core cell218. Thus, the sum of the currents through the amplifier PMOSFETs MCP1and MCP2is the core current (IR+Δi) through the core cell218.

Furthermore, the gates of the reference PMOSFETs MRP1and MRP2are coupled together to generate the reference voltage VREFapplied on the positive input of the comparator230and on the gate of the second amplifier PMOSFET MCP2. The first amplifier PMOSFET MCP1is a selected one of the plurality of amplifier PMOSFETs MCP1and MCP2having a gate for generating the core output voltage VCOREapplied on the negative input of the comparator230. The core feed-back regulator222is coupled between the gate of the first amplifier PMOSFET MCP1and the core cell218for stabilizing the core bit voltage VCBIT.

In an example embodiment of the present invention, the W/L ratio of the first reference and amplifier PMOSFETs MRP1and MCP1inFIG. 6is minimized for higher voltage swing of the reference and core output voltages VREFand VCORE. The equation for current conduction through a MOSFET is as follows:
I=k(W/L)(VGS−Vth)2
with k being a constant, W/L being the width to length ratio, VGSbeing the gate to source voltage, and Vthbeing the threshold voltage, of the MOSFET. When the W/L of the first amplifier PMOSFET MCP1is minimized, the VGSof the first amplifier PMOSFET MCP1changes more drastically with variation of the core current (IR+Δi) through the core cell218. Such higher variation of the VGSof the first amplifier PMOSFET MCP1results in higher voltage swing of the core output voltage VCOREfor the sense amplifier300. Such higher voltage swing is advantageous for enhanced sensitivity of the sense amplifier300.

In the sense amplifier300of FIG.6:
ΔV=VREF−VCORE; and
ΔV=Δi/gml,
with gmlbeing the transconductance of each of the first reference and amplifier PMOSFETs MRP1and MCP1.

Similar to the sense amplifier200ofFIG. 2, the sense amplifier300ofFIG. 6also generates an output signal OUT at the output of the comparator230with a logical state that indicates the bit data stored in the core cell218. In addition referring toFIG. 6, the plurality of amplifier PMOSFETs MCP1and MCP2doe not have any resistor in series such that the core bit voltage VCBITmay be relatively high near the high power supply voltage VCCwith the plurality of transistors MCP1and MCP2still operating in saturation.

The foregoing is by way of example only and is not intended to be limiting. For example, the present invention is described for sensing the current level through the core cell218of a memory device. However, the present invention may also be used for sensing the current level when the core cell218is any other type of current conducting device. Thus, the terms “core current”, “core output voltage generator”, “core front-end state”, “core back-end stage”, “core feed-back regulator”, and “core output voltage” as used herein is hereby generalized for sensing the current level through any type of current conducting device with the core cell218of a memory device being just one example.

In addition, the present invention herein is described for specific connections of the transistors in the example circuits ofFIGS. 2,3,4,5,6,7, and8. However, the present invention may also be implemented with variation in the specific connections of the drain, source, and gate of the transistors. Furthermore, any dimensions or parameters specified herein are by way of example only. The present invention is limited only as defined in the following claims and equivalents thereof.