Memory device with voltage boosting circuit

A memory device including a voltage boosting circuit, a switching circuit and a word line driving circuit is provided. The voltage boosting circuit is activated in a sleep mode. The voltage boosting circuit, based on an activation signal, performs a voltage boosting operation on a power voltage of a power voltage rail to generate a boosting voltage and transmit the boosting voltage to a control voltage rail. The switching circuit is turned on or cut-off according to a first mode selection signal. The word line driving circuit generates a plurality of word line signals according to the boosting voltage in the sleep mode; in addition, the word line driving circuit generates the word line signals according to the power voltage in a normal mode.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application no. 109132509, filed on Sep. 21, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

TECHNICAL FIELD

The invention relates to a memory device, and more particularly, to a voltage supply mechanism of a memory device in a sleep mode.

BACKGROUND

Static random access memory (SRAM) is a commonly used storage medium in electronic devices. In application, as long as a power voltage can be continuously supplied to SRAM, data held in SRAM can be maintained without loss.

Nowadays, energy saving and carbon reduction are an important issue for the electronic devices. Therefore, power consumption requirement of SRAM also needs to be effectively reduced. In the prior art, power consumption of the electronic device is often reduced by reducing the power voltage in the sleep mode. However, when the power voltage drops too low, the data stored in SRAM may be lost. Even if the data stored in SRAM is not missing, SRAM is still unable to perform effective access operations with the power voltage being too low and results in a reduced efficiency in use.

SUMMARY

The invention provides a memory device capable of supplying an appropriate voltage in the sleep mode to maintain the operation of the memory device.

A memory device of the invention includes a voltage boosting circuit, a switching circuit and a word line driving circuit. The voltage boosting circuit is coupled to a power voltage rail. The voltage boosting circuit is activated in a sleep mode. The voltage boosting circuit, based on an activation signal, performs a voltage boosting operation on a power voltage of a power voltage rail to generate a boosting voltage and transmit the boosting voltage to a control voltage rail. The switching circuit is coupled between the power voltage rail and the control voltage rail and is turned on or cut-off according to a first mode selection signal. The word line driving circuit is coupled to the control voltage rail. The word line driving circuit generates a plurality of word line signals according to the boosting voltage in the sleep mode; in addition, the word line driving circuit generates the word line signals according to the power voltage in a normal mode.

Based on the above, the memory device of the invention generates the boosting voltage by boosting the received power voltage in the sleep mode. The boosting voltage is provided to the word line driving circuit through the control voltage rail so the word line driving circuit can still effectively generate the word line signals in the sleep mode to maintain a normal access of the memory device.

DETAILED DESCRIPTION

Referring toFIG. 1,FIG. 1is a schematic diagram illustrating a memory device in an embodiment of the invention. A memory device100includes a voltage boosting circuit110, a switching circuit120and a word line driving circuit130. The voltage boosting circuit110is coupled to a power voltage rail PWL1. The voltage boosting circuit110can be activated in a sleep mode. When the voltage boosting circuit110is activated, based on an activation signal OPEN, the voltage boosting circuit110can perform a voltage boosting operation on a power voltage VSRAM of the power voltage rail PWL1to generate a boosting voltage VCP. The voltage boosting circuit110then transmits the boosting voltage VCP to a control voltage rail PWL2as a control voltage VCtrl of the control voltage rail PWL2. Here, the memory device100is a static random access memory device.

The switching circuit120is coupled between the power voltage rail PWL1and the control voltage rail PWL2and is turned on or cut-off according to a mode selection signal SLEP. In this embodiment, when the mode selection signal SLEP indicates that the memory device100enters the sleep mode, the switching circuit120is cut-off so that the power voltage rail PWL1and the control voltage rail PWL2are electrically isolated from each other. In contrast, when the mode selection signal SLEP indicates that the memory device100enters a normal mode, the switching circuit120is turned on so that the power voltage rail PWL1and the control voltage rail PWL2are electrically connected to each other.

When the memory device100is in the normal mode, the switching circuit120electrically connects the power voltage rail PWL1and the control voltage rail PWL2to each other. In this state, the power voltage VSRAM of the power voltage rail PWL1can be transmitted to the control voltage rail PWL2through the switching circuit120so that the control voltage VCtrl is equal to the power voltage VSRAM. In contrast, when the memory device100is in the sleep mode, the switching circuit120electrically isolates the power voltage rail PWL1and the control voltage rail PWL2from each other. At this time, the voltage boosting circuit110is activated, and performs the voltage boosting operation on the power voltage VSRAM to generate the boosting voltage VCP. At this time, the voltage boosting circuit110can provide the boosting voltage VCP to the control voltage rail PWL2as the control voltage VCtrl.

On the other hand, the word line driving circuit130is coupled to the control voltage rail PWL2, receives the control voltage VCtrl through the control voltage rail PWL2, and generates word line signals WLS1to WLSN according to the control voltage VCtrl. The word line signals WLS1to WLSN are transmitted to a plurality of word lines in the memory device100. According to the foregoing description, when the memory device100is in the normal mode, the word line signals WLS1to WLSN are generated according to the power voltage VSRAM; in contrast, when the memory device100is in the sleep mode, the word line signals WLS1to WLSN are generated according to the boosting voltage VCP.

It is worth noting that the power voltage VSRAM in the sleep mode can be reduced to be lower than the power voltage VSRAM in the normal mode to reduce power consumption. At the same time, in order to maintain the memory device100to perform normal access operations, the voltage boosting circuit110can generate a sufficiently high charging voltage VCP according to the power voltage VSRAM, and provide the charging voltage VCP as the control voltage VCtrl. In this way, in the sleep mode, the word line driving circuit130can still generate the word line signals WLS1to WLSN with a sufficiently high voltage, and maintain the normal access operation of the memory device100.

In this embodiment, the voltage boosting circuit110can be any form of charge pump circuit without particular limitation.

Referring toFIG. 2AandFIG. 2B,FIG. 2Ais a schematic diagram illustrating an implementation of a voltage boosting circuit and a switching circuit in the embodiment ofFIG. 1, andFIG. 2Bis a schematic diagram illustrating a word line driving circuit of the embodiment inFIG. 1.

Referring toFIG. 2Afirst, the voltage boosting circuit110includes a buffer111, a capacitor C1, and a switch formed by a transistor M21. The buffer111is composed of a plurality of inverters INV1and INV2connected in series. The inverter INV1of the first stage receives the activation signal OPEN, and an output terminal of the inverter INV2of the last stage is coupled to a first terminal of the capacitor C1. In addition, a second terminal of the capacitor C1is coupled to one terminal of the transistor M21and is coupled to the control voltage rail PWL2. Another terminal of the transistor M21is coupled to the power voltage rail PWL1. The transistor M21has a control terminal receiving the activation signal OPEN and is turned on or cut-off according to the activation signal OPEN. In this embodiment, the transistor M21is a P-type transistor.

As operation details of the voltage boosting circuit110, in the normal mode, the activation signal OPEN may be a logic low level. At this time, the transistor M21is turned on and electrically connects the power voltage rail PWL1and the control voltage rail PWL2to each other. At this time, the control voltage VCtrl is equal to the power voltage VSRAM. Further, at this time, the first terminal of the capacitor C1receives the logic low level, and the second terminal of the capacitor C1receives the power voltage VSRAM.

When the sleep mode is entered, the activation signal OPEN is switched to a logic high level. The voltage of the first terminal of the capacitor C1is changed to the logic high level, and the transistor M21is correspondingly cut-off. At the same time, through the charge pump effect of the capacitor C1, the capacitor C1can boost the generated charging voltage VCP and accordingly generate the control voltage VCtrl.

On the other hand, the switching circuit120is composed of a transistor M22. The transistor M22is a P-type transistor. In this embodiment, the transistor M22is controlled by the mode selection signal SLEP and is turned on or cut-off according to the mode selection signal SLEP. In the normal mode, the transistor M22can be turned on according to the mode selection signal SLEP at logic low voltage to provide the power voltage VSRAM of the power voltage rail PWL1to the control voltage rail PWL2as the control voltage VCtrl. In the sleep mode, the transistor M22can be cut-off according to the mode selection signal SLEP at logic high voltage. In this way, the power voltage rail PWL1and the control voltage rail PWL2are electrically isolated. At this time, the voltage boosting circuit110provides the boosting voltage VCP to the control voltage rail PWL2as the control voltage VCtrl. Accordingly, the word line driving circuit can generate effective word line signals.

Incidentally, in this embodiment, a base of the transistor M21is coupled to the control voltage rail PWL2, and a base of the transistor M22is coupled to the power voltage rail PWL1.

InFIG. 2B, the word line driving circuit120includes buffers BUF1to BUF3and a pull-up circuit210. The buffer BUF1is a non-inverting buffer. The buffer BUF1receives the power voltage VSRAM as an operating power and receives a word line control signal WLi to generate a signal S1according to the word line control signal WLi. The buffer BUF2and the buffer BUF3are coupled in series. The buffer BUF2and the buffer BUF3may both be inverting buffers (inverters). Among them, the buffer BUF2generates a signal S2according to the signal S1, and the buffer BUF3generates a word line driving signal WLSx according to the signal S2.

It should be noted that the buffers BUF2and BUF3both receive the control voltage VCtrl of the control voltage rail PWL2as an operating power. In the normal mode, the control voltage VCtrl is equal to the power voltage VSRAM; in the sleep mode, the control voltage VCtrl may be equal to the boosting voltage VCP generated by boosting the power voltage VSRAM.

The buffer BUF2includes transistors MP21and MN21. The transistors MP21and MN21are connected in series between the control voltage rail PWL2and a reference ground terminal VSS. Control terminals of the transistors MP21and MN21receive the signal S1, and a mutually-coupled terminal of the transistors MP21and MN21generates the signal S2. The buffer BUF3includes transistors MP22and MN22. The transistors MP22and MN22are connected in series between the control voltage rail PWL2and the reference ground terminal VSS. Control terminals of the transistors MP22and MN22receive the signal S2, and a mutually-coupled terminal of the transistors MP22and MN22generates the word line driving signal WLSx.

The pull-up circuit210is coupled between the control voltage rail PWL2and an output terminal of the buffer BUF2. The pull-up circuit210includes a transistor MP23. The transistor MP23is a P-type transistor which has a control terminal receiving the word line driving signal WLSx, and is turned on when the word line driving signal WLSx is at logic low voltage to pull up the signal S2to the control voltage VCtrl.

It is worth mentioning that the word line driving circuit120shown inFIG. 2Bis only an example for illustration, and is not used to limit the scope of the invention. In the embodiments of the invention, any word line driving circuit well known to those skilled in the art can be applied to the invention as long as the control voltage VCtrl of the control voltage rail PWL2can be received as the operating power.

Referring toFIG. 3,FIG. 3is a schematic diagram illustrating a memory device according to another embodiment of the invention. A memory device300includes a voltage boosting circuit310, a switching circuit320, a word line driving circuit330and an internal voltage adjusting circuit340. In this embodiment, the operation details of the voltage boosting circuit310, the switching circuit320and the word line driving circuit330are similar to those of the voltage boosting circuit110, the switching circuit120, and the word line driving circuit130in the foregoing embodiment, and are not repeated here. In addition, the internal voltage adjusting circuit340is coupled to the power voltage rail PWL1to receive the power voltage VSRAM of the power voltage rail PWL1as an operating power. The internal voltage adjusting circuit340is further coupled to an internal voltage rail PWL3. The internal voltage adjusting circuit340selects whether to reduce the power voltage VSRAM to generate an internal voltage VAR according to another mode selection signal DSLEP. The internal voltage VAR is configured to be provided to a memory cell array in the memory device300.

In this embodiment, the internal voltage adjusting circuit340includes transistors M31and M32. Among them, the transistor M31is a P-type transistor, and the transistor M32is an N-type transistor. The transistors M31and M32are coupled in parallel with each other, and are connected between the power voltage rail PWL1and the internal voltage rail PWL3. Control terminals of the transistor M31and M32receive the mode selection signal DSLEP together. The mode selection signal DSLEP is used to indicate whether the memory device300enters a deep sleep mode.

In detail, when the memory device300does not enter the deep sleep mode, the mode selection signal DSLEP may be at logic low voltage. At this time, the transistor M31is turned on and the transistor M32is cut-off. Under such condition, the power voltage rail PWL1and the internal voltage rail PWL3are electrically connected to each other, and the power voltage rail PWL1transmits the power voltage VSRAM to the internal voltage rail PWL3so that the internal voltage VAR is equal to the power voltage VSRAM.

On the other hand, when the memory device300enters the deep sleep mode, the mode selection signal DSLEP may be at logic high voltage. At this time, the transistor M31is cut-off and the transistor M32is turned on. Since the transistor M32is an N-type transistor, the body effect generated on the transistor M32can make the internal voltage VAR equal to the power voltage VSRAM minus a threshold voltage of the transistor M32, and can reduce the operating power received by the memory cell array to achieve a power saving effect.

In this embodiment, a base terminal of the transistor M31can be coupled to the power voltage rail PWL1, and a base terminal of the transistor M32can be coupled to the reference ground terminal.

Referring toFIG. 4,FIG. 4is a schematic diagram illustrating another implementation of an internal voltage adjusting circuit in a memory device according to an embodiment of the invention. An internal voltage adjusting circuit400includes transistors M41and M42, a diode string410and a transistor M43. The transistors M41and M42are a P-type transistor and an N-type transistors, respectively. The operation details of the transistors M41and M42are the same as those of the transistors M31and M32in the embodiment ofFIG. 3, and are not repeated here.

On the other hand, the diode string410and the transistor M43are coupled in series between the power voltage rail PWL1and the internal voltage rail PWL3. The diode string410may include one or more diodes, which are sequentially coupled between the power voltage rail PWL1and the internal voltage rail PWL3in a forward bias direction. InFIG. 4, the diode string410includes the diodes composed of transistors MP41and MP42. The transistors MP41and MP42are both coupled in a diode configuration. Naturally, in other embodiments of the invention, the diodes in the diode string410may also be constructed through N-type transistors or generated through the P-N junction in the semiconductor wafer without particular limitation.

In addition, a control terminal of the transistor M43receives a backward mode selection signal DSLEPb. The backward mode selection signal DSLEPb and the mode selection signal DSLEP are complementary in terms of logic voltage. When the mode selection signal DSLEP is at logic high voltage (the memory device is in a non-deep sleep mode), the transistor M41is turned on, and the transistors M42and M43are cut-off. At this time, the internal voltage VAR is equal to the power voltage VSRAM. When the mode selection signal DSLEP is at logic low voltage (the memory device is in the deep sleep mode), the transistor M41is cut-off, and the transistors M42and M43are turned on. At this time, the body effect provided by the transistor M42can make the internal voltage VAR equal to the power voltage VSRAM minus a threshold voltage of the transistor M42. The diode string410and the transistor M43can make the internal voltage VAR equal to the power voltage VSRAM minus a breakover voltage of the diode string410.

It is worth mentioning that in this embodiment, one of the transistor M42and a series circuit formed by the diode string410and the transistor M43can be selected to be constructed in the internal voltage adjusting circuit400, or they can be disposed together in the internal voltage adjusting circuit400.

Incidentally, a coupling sequence of the diode string410and the transistor M43is not particularly limited. Here, as illustrated inFIG. 4, the diode string410and the transistor M43are sequentially connected in series between the power voltage rail PWL1and the internal voltage rail PWL3. In other embodiments of the invention, the positions of the diode string410and the transistor M43can also be interchanged without specific limitation.

Referring toFIG. 5toFIG. 7,FIG. 5toFIG. 7are schematic diagrams respectively illustrating different implementations of a boosting circuit in a memory device of the embodiment of the invention. In addition to the implementation of the voltage boosting circuit110shown inFIG. 2A, the voltage boosting circuit in the memory device of the embodiment of the invention can still be implemented by various other charge pump circuits. InFIG. 5, a voltage boosting circuit500includes a plurality of diodes formed by transistors M1to Mn+1, capacitors C1to Cn, and a switch constructed by a transistor M51. Among them, the diodes formed by the transistors M1to Mn+1 are coupled in series with each other, and are coupled between the power voltage rail PWL1and a voltage feed out point OE in a forward bias direction. First terminals of the capacitors C1to Cn are respectively coupled to cathodes of the diodes formed by the transistors M1to Mn, and second terminals of the capacitors C1to Cn sequentially and alternately receive a clock signal CLK and a backward clock signal CLKb. In the sleep mode, the clock signal CLK and the complementary backward clock signal CLKb are activated, and a charge pump operation is performed through the capacitors C1to Cn to perform the voltage boosting operation on the power voltage VSRAM and generate the boosting voltage VCP.

In addition, the transistor M51is coupled between the voltage feed out point OE and the control voltage rail PWL2. In the sleep mode, the transistor M51can be turned on according to a backward activation signal OPENb to transmit the boosting voltage VCP to the control voltage rail PWL2as the control voltage VCtrl. In contrast, in the normal mode, the transistor M51is cut-off (the formed switch is equivalently cut-off), and the control voltage rail PWL2and the voltage feed out point OE are electrically isolated.

It should be noted that a transistor M52forms a switch and is coupled between the control voltage rail PWL2and the power voltage rail PWL1. The function of the transistor M52is the same as that of the transistor M21inFIG. 2, and will not be repeated here.

Incidentally, in this embodiment, whether the clock signal CLK and the complementary backward clock signal CLKb are activated can be determined according to the activation signal OPEN. When the activation signal OPEN is at logic high voltage, the clock signal CLK and the complementary backward clock signal CLKb can be activated (which are complementary periodic pulse signals respectively). In contrast, when the activation signal OPEN is at logic low voltage, the clock signal CLK and the complementary backward clock signal CLKb can be turned off (which are complementary DC signals respectively).

Referring toFIG. 6, a voltage boosting circuit600ofFIG. 6includes cross coupling transistor pairs610and620and capacitors CCP1and CCP2. The cross coupling transistor pair610is coupled between the power voltage rail PWL1, a first node n0and a second node n1. The cross coupling transistor pair620is coupled between the first node n0, the second node n1and the control voltage rail PWL2. Conductivity types of the cross coupling transistor pairs610and620are complementary. The cross coupling transistor pair610includes P-type transistors MP61and MP62. A control terminal of the transistor MP61is coupled to a second terminal of the transistor MP62; a first terminal of the transistor MP61is coupled to the control voltage rail PWL2; and a second terminal of the transistor MP61is coupled to the first node n0. A control terminal of the transistor MP62is coupled to a second terminal of the transistor MP61; a first terminal of the transistor MP62is coupled to the control voltage rail PWL2; and a second terminal of the transistor MP62is coupled to the second node n1. In addition, the cross coupling transistor pair620includes N-type transistors MN61and MN62. A control terminal of the transistor MN61is coupled to a second terminal of the transistor MN62; a first terminal of the transistor MN61is coupled to the power voltage rail PWL1; and a second terminal of the transistor MN61is coupled to the first node n0. A control terminal of the transistor MN62is coupled to a second terminal of the transistor MN61; a first terminal of the transistor MN62is coupled to the power voltage rail PWL1; and a second terminal of the transistor MN62is coupled to the second node n1.

In this embodiment, the capacitors CCP1and CCP2are respectively coupled to the first node n0and the second node n1, and respectively receive the complementary backward clock signal CLKb and the clock signal CLK. In the sleep mode, the clock signal CLK and the complementary backward clock signal CLKb are activated, and a charge pump operation is performed through the capacitors CCP1and CCP2to perform the voltage boosting operation on the power voltage VSRAM and generate the boosting voltage VCP. In this embodiment, the backward clock signal CLKb is generated through an inverter INV.

In this embodiment, whether the clock signal CLK and the complementary backward clock signal CLKb are activated can also be determined according to the activation signal OPEN. The decision mechanism is the same as that of the embodiment inFIG. 5, and is not repeated here.

Further, in this embodiment, a switch formed by a transistor MP63is coupled between the control voltage rail PWL2and the power voltage rail PWL1, and the transistor MP63is cut-off or turned on according to the activation signal. The function of the transistor MP63is the same as that of the transistor M21inFIG. 2, and is not repeated here.

Referring toFIG. 7, a voltage boosting circuit700ofFIG. 7includes a cross coupling transistor pair710, a transmission channel selector720and capacitors C71, C72and C73. The cross coupling transistor pair710is coupled between the power voltage rail PWL1, a first node n71and a second node n72. Two first terminals of the capacitors C71and C72are respectively coupled to the first node n71and the second node n72, and two second terminals of the capacitors C71and C72respectively receive the complementary clock signal CLK and the backward clock signal CLKb. The transmission channel selector720is coupled to the first node n71and the second node n72and is coupled to the control voltage rail PWL2and the capacitor C73. The capacitor C73is also coupled to the reference ground terminal VSS.

The cross coupling transistor pair710includes transistors M71and M72. The transistor M71is coupled between the power voltage rail PWL1and the first node n71, and has a control terminal coupled to the second node n72. The transistor M72is coupled between the power voltage rail PWL1and the second node n72, and has a control terminal coupled to the first node n71. The cross coupling transistor pair710may be configured to raise a voltage of the second node n72or the first node n71to the power voltage VSRAM according to the voltage of the first node n71or the second node72.

The transmission channel selector720includes transistors M73to M76. Transistors M73and M74can form a first channel, and transistors M75and M76can form a second channel. The first channel is controlled by the voltage of the first node n71, and the second channel is controlled by the voltage of the second node n72. The first channel is connected to the capacitor C73, the control voltage track PWL2and the first node n71; the second channel is connected to the capacitor C73, the control voltage track PWL2and the second node n72.

According to the voltages of the first node n71and the second node n72, the transmission channel selector720can select the first channel for transmitting the voltage of the first node n71to the capacitor C73and the control voltage rail PWL2or the second channel for transmitting the voltage of the second node n72to the capacitor C73and the control voltage rail PWL2.

In this embodiment, in the sleep mode, the clock signal CLK and the complementary backward clock signal CLKb are activated, and a charge pump operation is performed through the capacitors C71, C72and C73to perform the voltage boosting operation on the power voltage VSRAM and generate the boosting voltage VCP.

In this embodiment, whether the clock signal CLK and the complementary backward clock signal CLKb are activated can also be determined according to the activation signal OPEN. The decision mechanism is the same as that of the embodiment inFIG. 5, and is not repeated here. Further, in this embodiment, a switch formed by a transistor MP77is coupled between the control voltage rail PWL2and the power voltage rail PWL1, and the transistor MP77is cut-off or turned on according to the activation signal. The function of the transistor MP77is the same as that of the transistor M21inFIG. 2, and is not repeated here.

Referring toFIG. 8,FIG. 8is a schematic diagram illustrating a layout structure of a memory device according to an embodiment of the invention. A memory device800includes a voltage boosting circuit810, a plurality of internal voltage adjusting circuits8211to821N and8221to822N, a plurality of memory cell arrays MC, a word line driving circuit830, a plurality of input output (I/O) circuits8411to841N and8421to842N and a control circuit850. The voltage boosting circuit810and the internal voltage adjusting circuits8211to821N and8221to822N are coupled to the power voltage rail PWL1and receive the single power supply voltage VSRAM.

The voltage boosting circuit810provides the control voltage VCtrl to the word line driving circuit830as an operating power source of the word line driving circuit830. The word line driving circuit830can generate word line signals WLS based on the control voltage VCtrl. As implementation details, the voltage boosting circuit810can be constructed by applying any of the voltage boosting circuits110,500to700ofFIG. 2AandFIG. 5toFIG. 7of the invention.

In this embodiment, the internal voltage adjusting circuits8211to821N and8221to822N in this embodiment are plural in numbers, and can be respectively arranged on two opposite sides of the memory device800. Among them, the internal voltage adjusting circuits8211to821N are arranged on a first side of the memory device800, and the internal voltage adjusting circuits8221to822N are arranged on a second side of the memory device800. The voltage boosting circuit810can be arranged in the middle of the first side and the second side. The internal voltage adjusting circuits8211to821N and8221to822N are respectively corresponding to the memory cell arrays MC on different rows, and configured to generate an operating power for the memory cell arrays MC. Each of the internal voltage adjusting circuits8211to821N and8221to822N can be implemented by applying the internal voltage adjusting circuit340or400in the embodiment ofFIG. 3orFIG. 4.

It is worth mentioning that the internal voltage adjusting circuits8211to821N and8221to822N in the embodiment of the invention may be multiple circuits independent of each other. In other words, the internal voltage adjusting circuits8211to821N and the internal voltage adjusting circuits8221to822N of the invention can operate in the same or different modes.

When the internal voltage adjusting circuits8211to821N are operated in the deep sleep mode, the internal voltage adjusting circuits8221to822N can be operated in the non-deep sleep mode. Alternatively, when the internal voltage adjusting circuits8211to821N are operated in the non-deep sleep mode, the internal voltage adjusting circuits8221to822N can be operated in the deep sleep mode. Alternatively, the internal voltage adjusting circuits8211to821N,8221to822N can be synchronously operated in the deep sleep mode or synchronously operated in the non-deep sleep mode.

The I/O circuits8411to841N and8421to842N are respectively coupled to bit lines BL of the memory cell arrays MC, and perform data transmission operations during access operations. The I/O circuits8411to841N and8421to842N can be respectively disposed on two opposite sides of the control circuit850.

In this embodiment of the invention, the memory cell arrays MC are static random access memory cell arrays.

In summary, in the memory device of the invention, the single power supply voltage in the memory device is received through the voltage boosting circuit. In the sleep mode, the voltage boosting operation is performed on the power voltage to generate the control voltage. The control voltage is used to provide a basis for generating the word line signals. In this way, the memory device can maintain normal access operations in the sleep mode, and achieve the effect of being operable under low power.