Variable resistance device, semiconductor device including the variable resistance device, and method of operating the semiconductor device

According to an example embodiment, a method of operating a semiconductor device includes applying a first voltage to the variable resistance device so as to change a resistance value of the variable resistance device from a first resistance value to a second resistance value that is different from the first resistance value, sensing first current flowing through the variable resistance device to which the first voltage is applied, determining a second voltage used to change the resistance value of the variable resistance device from the second resistance value to the first resistance value based on a distribution of the sensed first current, and applying the determined second voltage to the variable resistance device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims foreign priority under 35 U.S.C. §119 to the benefit of Korean Patent Application No. 10-2011-0021869, filed on Mar. 11, 2011, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Some example embodiments relate to semiconductor devices, and more particularly, to a variable resistance device, a semiconductor device including the variable resistance device, and/or a method of operating the semiconductor device.

2. Description of the Related Art

As a need for memory devices that have high storage capacity and low power consumption increases, more research is being conducted into next-generation memory devices that are not only non-volatile but also do not need to be refreshed. Such a next-generation memory device is desired to have high integration characteristics of Dynamic Random Access Memory (DRAM), non-volatile characteristics of flash memory, high-speed operating characteristics of Static RAM (SRAM), and so on. Next-generation memory devices may include Phase change RAM (PRAM), Nano Floating Gate Memory (NFGM), Polymer RAM (PoRAM), Magnetic RAM (MRAM), Ferroelectric RAM (FeRAM), and Resistive RAM (RRAM). From among the above next-generation memory devices, RRAM is based on the phenomenon that a path in which current flows is generated thus lowering electrical resistance when a sufficiently high current is applied to a nonconductive material. In this case, once the path is generated, the path may be canceled or regenerated by applying an adequate voltage to the nonconductive material.

SUMMARY

Some example embodiments relate to a variable resistance device, the dispersion of off current of which is improved so as to increase the reliability of a semiconductor device including the variable resistance device, the semiconductor device, and/or a method of operating the semiconductor device.

According to an example embodiment, a method of operating a semiconductor device including a variable resistance device, includes applying a first voltage to the variable resistance device to change a resistance value of the variable resistance device from a first resistance value to a second resistance value that is different from the first resistance value, sensing first current flowing through the variable resistance device to which the first voltage is applied, determining a second voltage used to change the resistance value of the variable resistance device from the second resistance value to the first resistance value based on a distribution of the sensed first current, and applying the determined second voltage to the variable resistance device.

The second resistance value may be greater than the first resistance value.

The determining of the second voltage may include comparing the distribution of the first current with an average level of the first current.

The determining of the second voltage may further include changing the second voltage if a difference between a sensed level of the first current and the average level of the first current is greater than a first threshold amount, and maintaining the second voltage if the difference between a sensed level of the first current and the average level of the first current is smaller than or equal to the first threshold amount.

The changing of the second voltage may include changing the second voltage to a third voltage that is greater than the second voltage if the sensed level of the first current is smaller than the average level of the first current, and changing the second voltage to a fourth voltage that is smaller than the second voltage if the sensed level of the first current is greater than the average level of the first current.

The changing of the second voltage may include changing at least one of a magnitude and a pulse width of the second voltage.

The determining of the second voltage may further include changing the second voltage if the sensed level of the first current is different from the average level of the first current, and maintaining the second voltage if the sensed level of the first current is equal to the average level of the first current.

The changing of the second voltage may include changing the second voltage to the third voltage that is greater than the second voltage if the sensed level of the first current is smaller than the average level of the first current, and changing the second voltage to the fourth voltage that is smaller than the second voltage if the sensed level of the first current is greater than the average level of the first current.

The changing of the second voltage may include changing at least one of the magnitude and the pulse width of the second voltage.

The determining of the second voltage may further include determining the second voltage so that the greater the distribution of the first current, the greater the variation of the second voltage.

The sensing of the first current may include sensing the first current flowing through the variable resistance device to which the first voltage is applied by applying a read voltage having an absolute value smaller than that of the first voltage.

The method may further include sensing a second current flowing through the variable resistance device to which the second voltage is applied.

The sensing of the second current may include sensing the second current flowing through the variable resistance device to which the second voltage is applied. The sensing of the second current my include applying a read voltage having an absolute value smaller than that of the second voltage to the variable resistance device.

The semiconductor device may include a multi-bit non-volatile memory device.

The first resistance may be a set resistance, and the second resistance may be a reset resistance.

The variable resistance device may include a variable resistance material layer including one of a perovskite material and a transition metal oxide.

The variable resistance device may include a lower electrode, an upper electrode, and a variable resistance material layer between the lower electrode and the upper electrode. At least one of the lower electrode and the upper electrode may include one of an oxidation resistance metal layer and a polysilicon layer.

The first voltage may be a reset voltage for changing the variable resistance device to a high resistance state, and the second voltage may be a set voltage for changing the variable resistance device a low resistance state. The reset voltage may be about 4.5V.

The semiconductor device may include a single-bit non-volatile memory device.

According to another example embodiment, a variable resistance device may include a first electrode and a second electrode, a variable resistance material layer between the first and second electrodes, and a control circuit operatively connected to the variable resistance material layer. The control circuit may be configured to change a resistance value of the variable resistance material layer from a first resistance value to a second resistance value greater than the first resistance value by causing the application of a first voltage between the first and second electrodes. The control circuit may be configured to change the resistance value of the variable resistance material layer from the second resistance value to the first resistance value by causing the application of a second voltage between the first and second electrodes. The control circuit may be configured to determine the second voltage based on a distribution of a first current flowing through the variable resistance device.

The control circuit may be configured to change the second voltage if a difference between a sensed level of the first current and an average level of the first current is greater than a first threshold amount, and the control circuit may be configured to maintain the second voltage if the difference between a sensed level of the first current and the average level of the first current is smaller than or equal to the first threshold amount.

The control circuit may be configured to change the second voltage if the sensed level of the first current and the average level of the first current are different from each other, the control circuit may be configured to maintain the second voltage if the sensed level of the first current and the average level of the first current are the same.

According to another example embodiment, a semiconductor device may include a variable resistance device. The variable resistance device may include a first electrode and a second electrode, a variable resistance material layer between the first and the second electrode, and a control circuit operatively connected to the variable resistance material layers. the control circuit may be configured to change a resistance value of the variable resistance material layer from a first resistance value to a second resistance value that is greater than the first resistance value by causing the application of a first voltage between the first and second electrode. The control circuit may be configured to change the resistance value of the variable resistance material layer from the second resistance value to the first resistance value by causing the application of a second voltage between the first and second electrodes. The control circuit may be configured to determine the second voltage based on a distribution of a first current flowing through the variable resistance device.

The control circuit may be configured to change the second voltage if a difference between a sensed level of the first current and the average level of the first current is greater than a first threshold amount. The control circuit may be configured to maintain the second voltage if the difference between a sensed level of the first current and the average level of the first current is smaller than or equal to the first threshold amount.

The control circuit may be configured to change the second voltage if the sensed level of the first current and the average level of the first current are different from each other. The control circuit may be configured to maintain the second voltage if the sensed level of the first current and the average level of the first current are the same.

The variable resistance material layer may include on of a perovskite material and a transition metal oxide.

According to an example embodiment, a memory card may include the foregoing semiconductor device and a controller operatively connected to the semiconductor device.

According to an example embodiment, an electronic system may include the foregoing semiconductor device, a process, and a bus that operatively connects the semiconductor device to the processor.

DETAILED DESCRIPTION

As used herein, ‘at least one’ means one or more and thus may include individual components as well as mixtures/combinations.

FIG. 1is a schematic cross-sectional view of a variable resistance device10according to an example embodiment. Referring toFIG. 1, the variable resistance device10may include a lower electrode11, a variable resistance material layer12, and an upper electrode13. The variable resistance material layer12may be formed between the lower electrode11and the upper electrode13. In another example embodiment, the variable resistance device10may further include a buffer layer (not shown) on the lower electrode11and/or on the variable resistance material layer12.

The lower electrode11and the upper electrode13may be formed of a conductive material, for example, an oxidation resistant metal layer or a polysilicon layer. For example, the oxidation resistant metal layer may be formed of at least one of iridium (Ir), platinum (Pt), an iridium oxide (IrO), a titanium nitride (TlN), a titanium aluminum nitride (TiAlN), tungsten (W), molybdenum (Mo), ruthenium (Ru), and a ruthenium oxide (RuO). The oxidation resistant metal layer may be formed after the buffer layer is formed. The lower electrode11and the upper electrode13may be located on and below the variable resistance material layer12, respectively, but example embodiments are not limited thereto. In another example embodiment, the lower electrode11and the upper electrode13may be located to the left and right sides of the variable resistance material layer12, respectively.

The variable resistance material layer12may include a perovskite-based oxide or a transition metal oxide, but example embodiments are not limited thereto. Examples of the perovskite-based oxide include Pr1-xCaxMnO3, La1-xCaxMnO3, SrZrO3/SrTiO3, CrTiO3, Pb(Zr, Ti)O3/Zn1-xCdxS, and so on. Examples of the transition metal oxide include oxides of nickel, niobium, titanium, zirconium, hafnium, cobalt, iron, copper, manganese, zinc, chrome, tantalum, and so on. A resistance value of the variable resistance material layer12may vary according to the difference between voltages applied to the lower electrode11and the upper electrode13.

FIG. 2is a schematic cross-sectional view of a variable resistance device10′ according to another example embodiment. Referring toFIG. 2, the variable resistance device10′ may include a lower electrode11, a variable resistance material layer12′, and an upper electrode13. The variable resistance material layer12′ may be formed between the lower electrode11and the upper electrode13. The variable resistance material layer12′ may include a base thin film12aand an oxygen exchange layer12b. For example, the base thin film12amay include a TaOxlayer, and the oxygen exchange layer12bmay include a Ta2O5layer, but example embodiments are not limited thereto. The variable resistance device10′ is a modified example embodiment of the variable resistance device10illustrated inFIG. 1, and the variable resistance device10shown inFIG. 1may also be modified to incorporate features of the variable resistance device10′ shown inFIG. 2.

FIG. 3is a graph schematically illustrating a distribution of resistance values of a variable resistance device, according to an example embodiment.

Referring toFIG. 3, the X-axis denotes a resistance value of the variable resistance device, and the Y-axis denotes the total number of variable resistance devices. The variable resistance device may include the variable resistance device10ofFIG. 1and/or the variable resistance device10′ ofFIG. 2. For descriptive convenience, the variable resistance device includes the variable resistance device10ofFIG. 1.

The variable resistance device10may be used in a semiconductor device, such as a single-bit non-volatile memory device, which memorizes data ‘0’ or ‘1’ according to the resistance state of the variable resistance material layer12. The variable resistance device10may be used in a semiconductor device, such as a multi-bit non-volatile memory device, which memorizes data ‘00’, ‘01’,10′, or ‘11’ according to the resistance state of the variable resistance material layer12.

InFIG. 3, data ‘0’ and data ‘1’ may denote a high resistance state and a low resistance state. Writing data ‘1’ to the variable resistance device may be referred to as a set operation, and writing data ‘0’ to the variable resistance device may be referred to as a reset operation. However, example embodiments are not limited thereto, and according to another example embodiment, data ‘1’ and data ‘0’ may correspond to a high resistance state and a low resistance state.

The variable resistance device10may be ‘on’ when data ‘1’ is written thereto, and may be ‘off’ when data ‘0’ is written thereto. In this case, in order to improve the reliability of the variable resistance device10(or a semiconductor device including the variable resistance device10), a sufficient sensing margin SM between the ‘on’ state and the ‘off’ state of the variable resistance device10should be secured.

When the variable resistance device10is in an ‘off’ state, that is, when the variable resistance device10is in the high resistance state, a resistance of the variable resistance device10may be an off resistance ROFFthat may be divided into first through third resistances R1, R2, and R3. In this regard, the first resistance R1may correspond to an average value of the off resistance ROFF, the second resistance R2may correspond to a resistance value smaller than the average value of the off resistance ROFF, and the third resistance R3may correspond to a resistance value greater than the average value of the off resistance ROFF. The off resistance ROFFof the variable resistance device10may have a desired (or alternatively predetermined) distribution.

When the variable resistance device10is switched from an “off” state to the “on” state, a conductive path is formed in the variable resistance material layer12between the lower electrode11and the upper electrode13. In this regard, the energy necessary for changing the variable resistance device10from the “on” state to the “off” state may vary according to the characteristics of the conductive path formed when the variable resistance device10is in the “on” state, for example, sizes, number, or lengths of components.

More specifically, when a size of the conductive path formed when the variable resistance device10is in the “on” state is relatively small, the energy necessary for changing the variable resistance device10from the “on” state to the “off” state may be relatively small. Meanwhile, when the size of the conductive path formed when the variable resistance device10is in the “on” state is relatively large, the energy necessary for changing the variable resistance device10from the “on” state to the “off” state may be relatively large.

FIG. 4is a graph showing operating voltages applied to a variable resistance device, according to an example embodiment.

Referring toFIG. 4, the X-axis denotes time (seconds) and the Y-axis denotes a voltage (V) applied to the variable resistance device10. The variable resistance device may include the variable resistance device10ofFIG. 1or the variable resistance device10′ ofFIG. 2. For descriptive convenience, the variable resistance device includes the variable resistance device10ofFIG. 1. The voltage (V) applied to the variable resistance device10denote the difference between voltages applied to the lower and upper electrodes11and13of the variable resistance device10, and more particularly, a value obtained by subtracting the voltage applied to the upper electrode13from the voltage applied to the lower electrode11.

First, a reset voltage VRESETmay be applied to the variable resistance device10, and a read voltage VREADmay be applied thereto to sense reset current IRESETflowing through the variable resistance device10. The read voltage VREADmay have an absolute magnitude smaller than that of the reset voltage VRESET. A cycle in which the reset voltage VRESETand the read voltage VREADare continuously applied to the variable resistance device10may be referred to as a reset cycle. The variable resistance device10may be switched from a low resistance state to a high resistance state, i.e., the variable resistance device10is switched from an “on” state to an “off” state, when the reset voltage VRESETis applied thereto. In this case, few current may flow through the variable resistance device10in the “off” state.

Next, a set voltage VSETmay be applied to the variable resistance device10, and the read voltage VREADmay be applied thereto to sense set current ISETflowing through the variable resistance device10. A cycle in which the set voltage VSETand the read voltage VREADare continuously applied to the variable resistance device10may be referred to as a set cycle. The variable resistance device10may be switched from the high resistance state to the low resistance state, i.e., the variable resistance device10is switched from the “off” state to the “on” state, when the set voltage VSETis applied thereto. In this case, current may flow through the variable resistance device10in the “on” state. In this regard, the set voltage VSETapplied to the variable resistance device10may have a constant value, in particular, a constant absolute value or a constant pulse width.

Next, the reset voltage VRESETmay be applied again to the variable resistance device10, and the read voltage VREADmay be applied thereto to sense the reset current IRESETflowing through the variable resistance device10. In this regard, the reset voltage VRESETapplied to the variable resistance device10may have a constant value, in particular, a constant absolute value or a constant pulse width.

The polarities of the reset voltage VRESETand the set voltage VSETmay be opposite to each other. If the variable resistance device10has the reset voltage VRESETand the set voltage VSET, the polarities of which are opposite to each other, then the variable resistance device10is referred to as a ‘bipolar variable resistance device’. In the graph ofFIG. 4, the set voltage VSETand the reset voltage VRESETapplied to the variable resistance device10have a negative value and a positive value, respectively. However, example embodiments are not limited thereto, and the set voltage VSETmay have the positive value and the reset voltage VRESETmay have the negative value according to the type of material used to form the variable resistance material layer12of the variable resistance device10.

FIG. 5is a schematic diagram for describing an operation of the variable resistance device10when the operating voltages ofFIG. 4are applied to thereto according to an example embodiment.

Referring toFIG. 5, when the variable resistance device10is in the “off” state, the variable resistance device10may have the off resistance ROFFthat may be divided into the first through the third resistances R1, R2, and R3as shown inFIG. 3. When the variable resistance device10has the first resistance R1, the reset current IRESETflowing through the variable resistance device10may have an average level IRESET—M. When the variable resistance device10has the second resistance R2, the reset current IRESETflowing through the variable resistance device10may have a first level IRESET—1. In this regard, the first level IRESET—1may be a level (i.e. IRESET—M+σ) higher than the average level IRESET—Mby a desired (or alternatively predetermined) level σ. When the variable resistance device10has the third resistance R3, the reset current IRESETflowing through the variable resistance device10may have a second level IRESET—2. In this regard, the first level IRESET—2may be a level (i.e. IRESET—M−σ) lower than the average level IRESET—Mby the desired (or alternatively predetermined) level σ.

The set voltage VSETis applied to the variable resistance device10in order to switch the variable resistance device10from the “off” state to the “on” state. The set voltage VSETmay have a constant value irrespective of the off resistance ROFFof the variable resistance device10as shown inFIG. 4. When the set voltage VSEThaving the constant value is applied to the variable resistance device10, the characteristics of conductive paths formed when the variable resistance device10is in the “on” state may differ each other.

More specifically, when the off resistance ROFFis the second resistance R2, the reset current IRESETflowing through the variable resistance device10has the first level IRESET—1higher than the average level IRESET—M. In this regard, when the set voltage VSETthat is equal to the set voltage VSETwhere the off resistance ROFFis the first resistance R1or the third resistance R3is applied to the variable resistance device10, the variable resistance device10may undergo an energy surplus compared to when the off resistance ROFFis the first resistance R1or the third resistance R3. Accordingly, energy applied to the variable resistance device10when the off resistance ROFFis the second resistance R2may be overshoot compared to energy applied to the variable resistance device10when the off resistance ROFFis the first resistance R1.

Meanwhile, when the off resistance ROFFmay be the third resistance R3, the reset current IRESETflowing through the variable resistance device10has the second level IRESET—2lower than the average level IRESET—M. In this regard, when the set voltage VSETthat is equal to the set voltage VSETwhere the off resistance ROFFis the first resistance R1or the second resistance R2is applied to the variable resistance device10, the variable resistance device10may undergo an energy lack compared to when the off resistance ROFFis the first resistance R1or the second resistance R2. Accordingly, energy applied to the variable resistance device10when the off resistance ROFFis the third resistance R3may be undershoot compared to energy applied to the variable resistance device10when the off resistance ROFFis the first resistance R1.

Next, the reset voltage VRESETis applied to the variable resistance device10in order to switch the variable resistance device10from the “on” state to the “off” state again. The reset voltage VRESETmay have a constant value irrespective of the off resistance ROFFof the variable resistance device10as shown inFIG. 4. When the same reset voltage VRESETis applied to the variable resistance device10, the reset voltage VRESETflowing through the variable resistance device10after the reset voltage VRESETis applied to the variable resistance device10may have a resistance distribution by the desired (or alternatively predetermined) level σ that is the same as the resistance distribution in the “off” state in a previous operation as shown inFIG. 5.

When the constant set voltage VSETis applied to the variable resistance device10irrespective of a distribution of the off resistance ROFFof the variable resistance device10, the variable resistance device10may generate conductive paths having different characteristics. Thus, when the variable resistance device10is switched from the “on” state to the “off” state again, if the constant reset voltage VRESETis applied to the variable resistance device10, the reset voltage VRESETmay have a distribution by the desired (or alternatively predetermined) level σ that is the same as the distribution in the reset voltage VRESETin a previous operation, and accordingly, the off resistance ROFFmay have a distribution by the desired (or alternatively predetermined) level σ that is the same as the distribution in the off resistance ROFFin a previous operation.

FIG. 6is a graph showing a variation in the amount of current flowing through the variable resistance device10when the operating voltages ofFIG. 4are applied thereto according to an example embodiment.

Referring toFIG. 6, the X-axis denotes the number of times that the set cycle or the reset cycle is performed, and the Y-axis denotes the amount of current A. In this regard, the variable resistance material layer12included in the variable resistance device10may include, for example, TaOx, the reset voltage VRESETmay be about 4.5 V, the set voltage VSETmay be about −3.5 V, and pulse widths of the reset voltage VRESETand the set voltage VSETmay be about 1 μs.

Current flowing through the variable resistance device10after the set cycle, i.e., current sensed when the set voltage VSETand the read voltage VSETare sequentially applied to the variable resistance device10, is referred to as set current ISET. Also, current flowing through the variable resistance device10after the reset cycle, i.e., current sensed when the reset voltage VRESETand the read voltage VREADare sequentially applied to the variable resistance device10, is referred to as reset current IRESET.

InFIG. 6, the set current ISETis maintained at a constant current level of about 1.00 E-5 A. That is, the set current ISETis maintained at a constant current level regardless of a number of times that the set cycle is performed. However, the reset current IRESEThas a relatively large dispersion and is maintained at a current level of about 1.00 E-9 to about 1.00 E-7. In this case, the reset current IRESETshows a non-linear distribution regardless of a number of times that the reset cycle is performed.

As described above, in the variable resistance device10, the set current ISEThas a relatively small dispersion and the reset current IRESEThas a relatively large dispersion. Thus, the relatively large dispersion for the reset current IRESETmay reduce a sensing margin between the ‘on’ state and the ‘off’ state of the variable resistance device10.

FIG. 7is a graph showing operating voltages applied to a variable resistance device, according to another example embodiment.

Referring toFIG. 7, the X-axis denotes time (seconds) and the Y-axis denotes a voltage (V) applied to the variable resistance device10. The variable resistance device may include the variable resistance device10ofFIG. 1or the variable resistance device10′ ofFIG. 2. For descriptive convenience, the variable resistance device includes the variable resistance device10ofFIG. 1. The voltage (V) applied to the variable resistance device10denote the difference between voltages applied to the lower and upper electrodes11and13of the variable resistance device10, and more particularly, a value obtained by subtracting the voltage applied to the upper electrode13from the voltage applied to the lower electrode11.

First, the reset voltage VRESETmay be applied to the variable resistance device10, and the read voltage VREADmay be applied thereto to sense reset current IRESETflowing through the variable resistance device10. The read voltage VREADmay have an absolute magnitude smaller than that of the reset voltage VRESET. The variable resistance device10may be switched from a low resistance state to a high resistance state, i.e., the variable resistance device10is switched from an “on” state to an “off” state, when the reset voltage VRESETis applied thereto. In this case, few current may flow through the variable resistance device10.

Next, the set voltage VSETmay be applied to the variable resistance device10, and the read voltage VREADmay be applied thereto to sense set current ISETflowing through the variable resistance device10. The read voltage VREADmay have an absolute magnitude smaller than that of the set voltage VSET. The variable resistance device10may be switched from the high resistance state to the low resistance state, i.e., the variable resistance device10is switched from the “off” state to the “on” state, when the set voltage VSETis applied thereto. In this case, current may flow through the variable resistance device10.

According to an example embodiment, as illustrated inFIG. 7, the set voltage VSETapplied to the variable resistance device10may have a variable value, in particular, a variable absolute value or a variable pulse width, according to a distribution of the reset current IRESETflowing through the variable resistance device10in the “off” state in a previous operation, i.e. according to a distribution of the off resistance ROFFof the variable resistance device10.

In particular, the higher the off resistance ROFFin the previous operation, the smaller the value of the reset current IRESET, and thus a relatively great amount of energy may be necessary for switching the variable resistance device10from the “off” state to the “on” state. In this case, the set voltage VSETmay be determined to have a relatively large value, i.e. a relatively large absolute value or pulse width.

Meanwhile, the lower the off resistance ROFFin the previous operation, the greater the value of the reset current IRESET, and thus a relatively small amount of energy may be necessary for switching the variable resistance device10from the “off” state to the “on” state. In this case, the set voltage VSETmay be determined to have a relatively small value, i.e. a relatively small absolute value or pulse width.

Next, the reset voltage VRESETmay be again applied to the variable resistance device10, and the read voltage VREADmay be applied thereto to sense the reset current IRESETflowing through the variable resistance device10. In this regard, the reset voltage VRESETapplied to the variable resistance device10may have a constant value, in particular, a constant absolute value or a constant pulse width.

FIG. 8is a schematic diagram for describing an operation of the variable resistance device10when the operating voltages ofFIG. 7are applied to thereto according to an example embodiment.

Referring toFIG. 8, when the variable resistance device10is in the “off” state, the variable resistance device10may have the off resistance ROFFthat may be divided into the first through the third resistances R1, R2, and R3as shown inFIG. 3. When the variable resistance device10has the first resistance R1, the reset current IRESETflowing through the variable resistance device10may have an average level IRESET—M. When the variable resistance device10has the second resistance R2, the reset current IRESETflowing through the variable resistance device10may have a first level IRESET—1. In this regard, the first level IRESET—1may be a level (i.e. IRESET—M+σ) higher than the average level IRESET—Mby a desired (or alternatively predetermined) level σ. When the variable resistance device10has the third resistance R3, the reset current IRESETflowing through the variable resistance device10may have a second level IRESET—2. In this regard, the first level IRESET—2may be a level (i.e. IRESET—M−σ) lower than the average level IRESET—Mby the desired (or alternatively predetermined) level σ.

The set voltage VSETis applied to the variable resistance device10in order to switch the variable resistance device10from the “off” state to the “on” state. The set voltage VSETmay be variable according to a distribution of the off resistance ROFFof the variable resistance device10as shown inFIG. 7. When the variable set voltage VSETis applied to the variable resistance device10according to a distribution of the off resistance ROFF, an energy level of the variable resistance device10may be relatively uniform when the variable resistance device10is switched to the “on” state.

More specifically, when the off resistance ROFFis the second resistance R2, the reset current IRESETflowing through the variable resistance device10has the first level IRESET—1higher than the average level IRESET—M. In this regard, a set voltage VSET−ΔV that is smaller by a desired (or alternatively predetermined) level ΔV than the set voltage VSETapplied to the variable resistance device1when the off resistance ROFFis the first resistance R1may be applied to the variable resistance device1, thereby reducing an energy surplus in the variable resistance device10when the variable resistance device10is switched to the “on” state. Accordingly, an overshoot of energy applied to the variable resistance device10when the variable resistance device10is switched to the “on” state and the off resistance ROFFis the second resistance R2may be reduced compared to the overshoot as shown inFIG. 5.

Meanwhile, when the off resistance ROFFmay be the third resistance R3, the reset current IRESETflowing through the variable resistance device10has the second level IRESET—2lower than the average level IRESET—M. In this regard, a set voltage VSET+ΔV that is greater by the desired (or alternatively predetermined) level ΔV than the set voltage VSETapplied to the variable resistance device1when the off resistance ROFFis the first resistance R1may be applied to the variable resistance device1, thereby reducing an energy lack in the variable resistance device10when the variable resistance device10is switched to the “on” state. Accordingly, an undershoot of energy applied to the variable resistance device10when the variable resistance device10is switched to the “on” state and the off resistance ROFFis the third resistance R3may be reduced compared to the undershoot as shown inFIG. 5.

Energy necessary for forming a conductive path when the variable resistance device10is switched to the “on” state may be expressed according to Equation 1 below,
P=IV=V2/R[Equation 1]

wherein, I denotes the set current ISET, V denotes the set voltage VSET, and R denotes the off resistance ROFF. Thus, the distribution of the off resistance ROFFmay be offset at the set voltage VSETby varying or maintaining the set voltage VSETaccording to a distribution of R, i.e. the distribution of the off resistance ROFF. Thus, the greater the distribution of the off resistance ROFF, the greater the variation of the set voltage VSET. Accordingly, the energy necessary for forming the conductive path when the variable resistance device10is switched to the “on” state may be maintained relatively uniform.

Next, the reset voltage VRESETis applied to the variable resistance device10in order to switch the variable resistance device10from the “on” state to the “off” state again. The reset voltage VRESETmay have a constant value irrespective of the off resistance ROFFof the variable resistance device10as shown inFIG. 7. In this regard, the reset current IRESETflowing through the variable resistance device10after the reset voltage VRESETis applied to the variable resistance device10may have a distribution of a level σ′ that is reduced compared to the “off” state in a previous operation.

According to an example embodiment, the set voltage VSETis determined to be variable according to the distribution of the off resistance ROFFin the previous operation, and the determined set voltage is applied to the variable resistance device10. Accordingly, although the same reset voltage VRESETis applied to the variable resistance device10in a next operation, a distribution of the reset current IRESETflowing through the variable resistance device10may be greatly reduced compared to the “off” state in the previous operation as shown inFIG. 8.

FIG. 9is a graph showing a variation in the amount of current flowing through a variable resistance device when the operating voltages ofFIG. 7are applied to thereto according to another example embodiment.

Referring toFIG. 9, the X-axis denotes the number of times that the set cycle or the reset cycle is performed, and the Y-axis denotes the amount of current A. In this regard, the variable resistance material layer12included in the variable resistance device10may include, for example, TaOx, the reset voltage VRESETmay be about 4.5 V, and a pulse width of the reset voltage VRESETmay be about 1 μs. An absolute value or a pulse width of the set voltage VSETmay be determined to be variable.

Current flowing through the variable resistance device10after the set cycle, i.e., current sensed when the set voltage VSETand the read voltage VSETare sequentially applied to the variable resistance device10, is referred to as set current ISET. Also, current flowing through the variable resistance device10after the reset cycle, i.e., current sensed when the reset voltage VRESETand the read voltage VREADare sequentially applied to the variable resistance device10, is referred to as reset current IRESET.

InFIG. 9, the set current ISETis maintained at a constant current level of about 1.00 E-5 A. That is, the set current ISETis maintained at a constant current level regardless of a number of times that the set cycle is performed. However, the reset current IRESETis maintained at a current level of about 1.00 E-8 to about 1.00 E-7. In this case, a distribution of the reset current IRESETis reduced compared to the distribution of the reset current IRESETshown inFIG. 6.

FIG. 10is a graph showing a resistance distribution of the variable resistance device10with respect to the graph ofFIG. 9according to an example embodiment.

Referring toFIG. 10, the X-axis denotes a resistance value of the variable resistance device, and the Y-axis denotes the total number of resistance devices. In this regard, reference numeral A denotes a distribution of the off resistance ROFFaccording toFIGS. 4 and 5, and reference numeral B denotes a distribution of the off resistance ROFFaccording to example embodiments, i.e.FIGS. 7 and 8.

The set voltage VSETdetermined to be variable according to the distribution of the off resistance ROFFis applied to the variable resistance device10, which makes energy, of the variable resistance device10relatively uniform when the variable resistance device10is in an “on” state, thereby greatly reducing the distribution of the off resistance ROFFwhen the variable resistance device10is in an “off” state in a next operation.

FIG. 11is a flowchart illustrating a method of operating a semiconductor device including a variable resistance device, according to an example embodiment.

Referring toFIG. 11, a method of operating the semiconductor device of according to an example embodiment may be a method of operating a semiconductor device including the variable resistance device10ofFIG. 1or the variable resistance device10′ ofFIG. 2. A method according to an example embodiment will now be described, for example, in relation to the variable resistance device10ofFIG. 1. The detailed descriptions described with reference toFIGS. 1 through 10will apply.

In operation S110, the reset voltage VRESETis applied to the variable resistance device10. The variable resistance device10may be switched from a low resistance state to a high resistance state, i.e., the variable resistance device10is switched from an “on” state to an “off” state. The reset voltage VRESETmay be about 4.5 V.

In operation S120, the reset current IRESETflowing through the variable resistance device10to which the reset voltage VRESETis applied, is sensed. More specifically, the read voltage VREADhaving a smaller absolute value than the reset voltage VRESETmay be applied to the variable resistance device10to which the reset voltage VRESETis applied, and then the reset current IRESETflowing through the variable resistance device10may be sensed.

In operation S130, the set voltage VSETis determined based on a distribution of the sensed reset current IRESET. More specifically, an absolute value or a pulse width of the set voltage VSETis determined based on the distribution of the sensed reset current IRESET, i.e. a distribution of the off resistance ROFFof the variable resistance device10. This will be in more detail described with reference toFIGS. 12 and 13below.

In operation S140, the determined set voltage VSETis applied to the variable resistance device10. Accordingly, the variable resistance device10may be switched from the high resistance state to the low resistance state, i.e., the variable resistance device10is switched from the “off” state to the “on” state.

The method may further include sensing the set current ISETflowing through the variable resistance device10to which the set voltage VSETis applied. More specifically, the read voltage VREADhaving a smaller absolute value than the set voltage VSETmay be applied to the variable resistance device10to which the set voltage VSETis applied, and then the set current ISETflowing through the variable resistance device10may be sensed. Further, the method may perform operation S110again after performing operation S140.

FIG. 12is a flowchart illustrating an operation of determining the set voltage VSETincluded inFIG. 11, according to an example embodiment.

Referring toFIG. 12, in operation S1311, it is determined whether a difference between the sensed level of the reset current IRESETand the average level IRESET—Mthereof is smaller than a first threshold amount. The first threshold amount may be a desired (or alternatively predetermined) ranged of distribution of reset current IRESET, but example embodiments are not limited thereto. If it is determined that the difference between the sensed level of the reset current IRESETand the average level IRESET—Mthereof is smaller than the first threshold amount, operation S1315is performed. Meanwhile, if it is determined that the difference between the sensed level of the reset current IRESETand the average level IRESET—Mthereof is greater than the first threshold amount, operation S1312is performed. In this regard, the first threshold amount may be a desired amount and/or previously determined. More specifically, the first threshold amount may be further narrowed in order to increase the reliability of a semiconductor device.

In operation S1312, it is determined whether the sensed level of the reset current IRESETis smaller than the average level IRESET—Mthereof. If it is determined that the sensed level of the reset current IRESETis smaller than the average level IRESET—Mthereof, operation S1313is performed. Meanwhile, if it is determined that the sensed level of the reset current IRESETis greater than the average level IRESET—Mthereof, operation S1314is performed.

In operation S1313, the set voltage VSETis changed to increase the set voltage VSET. More specifically, if the sensed level of the reset current IRESETis smaller than the average level IRESET—Mthereof, an energy level necessary for switching the variable resistance device10from an “off” state to an “on” state is relatively large.

In operation S1314, the set voltage VSETis changed to reduce the set voltage VSET. More specifically, if the sensed level of the reset current IRESETis greater than the average level IRESET—Mthereof, the energy level necessary for switching the variable resistance device10from the “off” state to the “on” state is relatively small.

Therefore, as described in operations S1313and S1314, the set voltage VSETis changed to increase or reduce the set voltage VSETaccording to a distribution of the reset current IRESET, and thus the energy level of the variable resistance device10may be relatively uniform when the variable resistance device10is in the “on” state.

In operation S1315, the set voltage VSETis maintained. More specifically, if the difference between the sensed level of the reset current IRESETand the average level IRESET—Mthereof is smaller than the first threshold amount, since it is unnecessary to change the set voltage VSET, it may be determined to maintain the set voltage VSET. The first threshold amount may be a desired (or alternatively predetermined) ranged of distribution of reset current iRESET, but example embodiments are not limited thereto.

FIG. 13is a flowchart illustrating an operation of determining a set voltage included inFIG. 11, according to another example embodiment.

Referring toFIG. 13, in operation S1321, it is determined whether the sensed level of the reset current IRESETis substantially equal to the average level IRESET—Mthereof. If it is determined that the sensed level of the reset current IRESETis substantially equal to the average level IRESET—Mthereof, operation S1325is performed. For example, the sensed level of the reset current IRESETmay be considered substantially equal to the average level IRESET—Mif the ratio of IRESET/IRESET—Mis about 0.90 to about 1.10, and/or more particularly from about 0.95 to about 1.05, and/or even more particularly from about 0.98 to about 1.02. Meanwhile, if it is determined that the sensed level of the reset current IRESETis not substantially equal to the average level IRESET—Mthereof, operation S1322is performed.

In operation S1322, it is determined whether the sensed level of the reset current IRESETis smaller than the average level IRESET—Mthereof. If it is determined that the sensed level of the reset current IRESETis smaller than the average level IRESET—Mthereof, operation S1323is performed. Meanwhile, if it is determined that the sensed level of the reset current IRESETis greater than the average level IRESET—Mthereof, operation S1324is performed.

In operation S1323, the set voltage VSETis changed to increase the set voltage VSET. More specifically, if the sensed level of the reset current IRESETis smaller than the average level IRESET—Mthereof, an energy level necessary for switching the variable resistance device10from an “off” state to an “on” state is relatively large.

In operation S1324, the set voltage VSETis changed to reduce the set voltage VSET. More specifically, if the sensed level of the reset current IRESETis greater than the average level IRESET—Mthereof, the energy level necessary for switching the variable resistance device10from the “off” state to the “on” state is relatively small.

Therefore, as described in operations S1323and S1324, the set voltage VSETis changed to increase or reduce the set voltage VSETaccording to a distribution of the reset current IRESET, and thus the energy level of the variable resistance device10may be relatively uniform when the variable resistance device10is in the “on” state.

In operation S1325, the set voltage VSETis maintained. More specifically, if the sensed level of the reset current IRESETis substantially equal to the average level IRESET—Mthereof, since it is unnecessary to change the set voltage VSET, it may be determined to maintain the set voltage VSET.

FIG. 14is a circuit diagram of a semiconductor device including a variable resistance device R, according to an example embodiment.

Referring toFIG. 14, the semiconductor device may be, for example, a non-volatile memory device, and a unit cell MC1thereof may include the variable resistance device R and a diode D. The variable resistance device R may be the same as and/or substantially the same as the variable resistance device10ofFIG. 1or the variable resistance device10′ ofFIG. 2. A first end of the variable resistance device R is connected to a bit line BL and a second end thereof is connected to the diode D. The diode D may operate bi-directionally, and may select the unit cell MC1according to a voltage applied to a word line WL.

If the semiconductor device is a single-bit non-volatile memory device, then the variable resistance device R may be switched from a low resistance state to a high resistance state and data ‘0’ may be written to the semiconductor device when the reset voltage is applied to the variable resistance device R, and may be switched from the high resistance state to the low resistance state and data ‘1’ may be written to the semiconductor device when the set voltage is applied to the variable resistance device R. In this case, a set voltage may be determined based on a distribution of a reset current flowing through the variable resistance device R when the variable resistance device R is in the high resistance state, i.e. based on a distribution of an off resistance of the variable resistance device R.

FIG. 15is a circuit diagram of a semiconductor device including a variable resistance device R, according to another example embodiment. Referring toFIG. 15, the semiconductor device may be, for example, a non-volatile memory device, and a unit cell MC2thereof may include a variable resistance device R and an access transistor T. The variable resistance device R may be the same as and/or substantially the same as the variable resistance device10ofFIG. 1or the variable resistance device10′ ofFIG. 2. A first end of the variable resistance device R is connected to a bit line BL and a second end thereof is connected to the access transistor T. The access transistor T includes a gate connected to a word line WL, a drain connected to the second end of the variable resistance device R, and a source connected to a source line SL. The access transistor T may be switched on or off to select the unit cell MC2, according to a voltage applied to the word line WL.

If the semiconductor device is a single-bit non-volatile memory device, then the variable resistance device R may be switched from a low resistance state to a high resistance state and data ‘0’ may be written to the semiconductor device when reset voltage is applied to the variable resistance device R, and may be switched from the high resistance state to the low resistance state and data ‘1’ may be written to the semiconductor device when set voltage is applied to the variable resistance device R. In this case, a set voltage may be determined based on a distribution of a reset current flowing through the variable resistance device R when the variable resistance device R is in the high resistance state, i.e. based on a distribution of an off resistance of the variable resistance device R.

FIG. 16is a schematic block diagram for a semiconductor device50according to an example embodiment. As shown inFIG. 16, a semiconductor device50includes a memory array20, a control circuit30, and an output circuit40. The memory array20may include a plurality of unit cells MC1and/or MC2, as shown inFIG. 14-15, but example embodiments are not limited thereto. The control circuit30is operatively connected to the memory array20and configured to sense a reset current IRESETand/or set current ISETfrom the variable resistance device R of unit cells MC1and/or MC2. The control circuit30is configured to receive a signal indicating the current sensed from the variable resistance device R of unit cells MC1and/or MC2, for example the reset current IRESETand/or set current ISET. The control circuit30is configured to cause the application of a reset voltage VRESETand/or set voltage VSETto the variable resistance device R of unit cells MC1and/or MC2, for example by causing the application of a voltage between an upper and lower electrode of the variable resistance device R in unit cells MC1and/or MC2. Based on the reset current IRESETsensed, the control circuit30determines a set voltage VSETand causes the application of the set voltage VSETto the variable resistance device R of unit cells MC1and/or MC2. The control circuit30may determine the set voltage according to the foregoing methods described inFIGS. 11-13, but example embodiments are not limited thereto. The output circuit40is operatively connected to the memory array20and the control circuit30. The output circuit40is configured to output, for example data read from the memory array20under the control of the control circuit30.

FIG. 17is a cross-sectional view of the semiconductor device ofFIG. 15, according to an example embodiment. Referring toFIG. 17, an isolation layer105is formed in a region of a semiconductor substrate100so as to define an active region. A drain region110and a source region115are formed in the active region to be disposed apart from each other. A gate insulating layer120is disposed on the active region between the drain region110and the source region115, and a gate electrode125is disposed on the gate insulating layer120. The gate electrode125may extend to act as a word line or may be connected to a word line (not shown). The gate electrode125, the drain region110, and the source region115form an access transistor T together.

A first interlevel insulating layer130is formed on the access transistor T, and a first contact plug CP1and a second contact plug CP2are formed in the first interlevel insulating layer130. The source region115may be connected to a source line SL via the first contact plug CP1and a source line electrode135, and the drain region110may be connected to a lower electrode140via the second contact plug CP2.

A second interlevel insulating layer160is formed on the first interlevel insulating layer130, and the lower electrode140, a variable resistance material layer145, and an upper electrode150are sequentially formed in a region of the second interlevel insulating layer160. The upper electrode150may be connected to a bit line170via a third contact plug CP3. The lower electrode140, the variable resistance material layer145, and the upper electrode150form a variable resistance device R together. The variable resistance device R corresponds to the variable resistance device10ofFIG. 1.

Cases where variable resistance devices according to example embodiments are included in a single-bit non-volatile memory device have been described above in detail. However, the variable resistance devices according to example embodiments may be included in a multi-bit non-volatile memory device.

Further, each of variable resistance devices according to example embodiments may be included into a logic gate so as to be used in a logic circuit. In this case, the size of the logic circuit may be reduced and the integration degree of a memory device may be improved. Particularly, a variable resistance device according to an example embodiment may be applied to a memristor. Thus, the memristor may operate substantially in a similar manner to one of the methods of operating a semiconductor device described above with reference toFIGS. 7 to 13. Here, the “memristor” refers to a device, in which, for example, the direction and amount of current are memorized and a resistance value varies according to the memorized direction and amount of current.

FIG. 18is a schematic block diagram of a memory card200according to an example embodiment.

Referring toFIG. 18, the memory card200includes a controller210and a memory unit220. The controller210and the memory unit220may be disposed to exchange an electrical signal with each other. For example, if the controller210provides a command to the memory unit220, then the memory unit220may transmit data to the controller210. The memory unit220may include a non-volatile memory device that includes a variable resistance device according to one of the example embodiments describe above.

The memory card200may be embodied in various types of cards (memory devices), e.g., a memory stick card, a smart media (SM) card, a secure digital (SD) card, a mini SD card, and a multi-media card (MMC).

FIG. 19is a schematic block diagram of an electronic system300according to an example embodiment.

Referring toFIG. 19, the electronic system300may include a processor310, a memory unit320, an input/output (I/O) device330, and an interface unit340. The electronic system300may be a mobile system or a system capable of transmitting and receiving information. The mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card.

The processor310may execute a program and control the electronic system300. The processor310may be, for example, a microprocessor, a digital signal processor, a microcontroller, or the like.

The I/O device330may be used to input data to or output data from the electronic system300. The electronic system300may be connected to an external device (not shown), such as a personal computer (PC) or a network, via the I/O device330so as to exchange data with the external device. The I/O device330may be, for example, a keypad, a keyboard, or a display.

The memory unit320may store code and/or data for operating the processor310, and/or may store data processed by the processor310. The memory unit320may include a non-volatile memory device that includes a variable resistance device according to one of the example embodiments described above.

The interface unit340may be used as a path, in which the electronic system300exchanges data with an external device (not shown). The processor310, the memory unit330, the I/O device330, and the interface unit340may communicate with one another via a bus350.

For example, the electronic system300may be employed in a mobile phone, an MP3 player, a navigation device, a portable multimedia player (PMP), a solid state drive (SSD), or household appliances.

As described above, according to one or more of the above example embodiments, a set current of a variable resistance device included in a semiconductor device is determined based on a distribution of the reset current, i.e. a distribution of an off resistance of the variable resistance device, thereby improving the distribution of an ‘off’ current of the variable resistance device, and accordingly improving the reliability of the semiconductor device including the variable resistance device.

According to one or more of the above example embodiments, an overshoot or an undershoot that may occur when the variable resistance device include in the semiconductor device is switched from an “off” state to an “on” state is reduced, thereby improving the durability of the semiconductor device.

Descriptions of features or aspects within each example embodiment should typically be considered as available for other similar features or aspects in other example embodiments. While some example embodiments have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the claims.