Reciprocal quantum logic (RQL) circuit simulation system

One example includes an RQL circuit simulation system. The system includes a circuit design tool that facilitates user inputs to design an RQL circuit design comprising at least one predetermined RQL circuit design component. The system also includes a memory system that stores the RQL circuit design and an RQL component library comprising predetermined RQL circuit design components from which the at least one predetermined RQL circuit design component is selected. Each of the predetermined RQL circuit design components includes predetermined RQL component metrics associated with performance of the respective one of the predetermined RQL circuit design components. The system also includes a circuit simulator configured to compile performance metrics associated with the RQL circuit design based on the predetermined RQL component metrics associated with the respective at least one of the predetermined RQL circuit design components and to simulate the RQL circuit design based on the performance metrics.

TECHNICAL FIELD

This disclosure relates generally to quantum and classical circuit systems, and specifically to Reciprocal Quantum Logic (RQL) circuit simulation system.

BACKGROUND

Circuit simulation is a manner for electronic circuits to be designed in a simulated manner and tested in a simulation environment for operational characteristics of the electronic circuits. Implementing circuit simulation can provide for a much more cost-effective and efficient way of testing circuit behavior, and thus for optimizing circuit design parameters. Typical simulated circuits can be complementary metal-oxide semiconductor (CMOS) circuits, such as to provide logic testing of the operation of the CMOS circuits. In CMOS circuits, combinatorial and sequential component building blocks can be included in a circuit simulation to verify logic success of the circuit and/or timing characteristics associated with the circuit. However, other types of circuits, such as superconducting circuit systems, are becoming more prevalent and can have entirely different operating characteristics. Superconducting circuit systems, such as Reciprocal Quantum Logic (RQL) circuits, do not operate with the same combinatorial and sequential classifications as CMOS circuits, and thus cannot be simulated in the same manner.

SUMMARY

One example includes an RQL circuit simulation system. The system includes a circuit design tool that facilitates user inputs to design an RQL circuit design comprising at least one predetermined RQL circuit design component. The system also includes a memory system that stores the RQL circuit design and an RQL component library comprising predetermined RQL circuit design components from which the at least one predetermined RQL circuit design component is selected. Each of the predetermined RQL circuit design components includes predetermined RQL component metrics associated with performance of the respective one of the predetermined RQL circuit design components. The system also includes a circuit simulator configured to compile performance metrics associated with the RQL circuit design based on the predetermined RQL component metrics associated with the respective at least one of the predetermined RQL circuit design components and to simulate the RQL circuit design based on the performance metrics.

Another embodiment of the invention includes a method for simulating an RQL circuit design. The method includes facilitating user inputs via a circuit design tool to design a plurality of predetermined RQL circuit design components and calculating predetermined RQL component metrics associated with each of the plurality of predetermined RQL circuit design components. The method also includes storing the predetermined RQL circuit design components and the associated predetermined RQL component metrics in an RQL component library and facilitating user inputs via the circuit design tool to design the RQL circuit design comprising at least one of the plurality of predetermined RQL circuit design components. The method further includes compiling aggregate performance metrics associated with the RQL circuit design based on the predetermined RQL component metrics associated with the respective at least one of plurality of predetermined RQL circuit design components and simulating the RQL circuit design via a circuit simulator based on the aggregate performance metrics.

Another embodiment of the invention includes an RQL circuit simulation system. The system includes a circuit design tool configured to facilitate user inputs to design an RQL circuit design comprising at least one predetermined RQL circuit design component. The system also includes a memory system configured to store the RQL circuit design and an RQL component library comprising a plurality of predetermined RQL circuit design components from which the at least one predetermined RQL circuit design component is selected. Each of the plurality of predetermined RQL circuit design components includes predetermined RQL component metrics. The predetermined RQL component metrics include timing data associated with at least one Josephson junction and timing behavior associated with single-flux quantum (SFQ) pulses associated with the respective one of the plurality of predetermined RQL circuit design components. The system also includes a circuit simulator that includes a performance metric compiler configured to evaluate the RQL circuit design and to access the RQL component library to compile aggregate performance metrics associated with the associated with the RQL circuit design based on the predetermined RQL component metrics associated with each individual one of the respective at least one of plurality of predetermined RQL circuit design components. The circuit simulator also includes a processor configured to simulate the RQL circuit design based on the aggregate performance metrics.

DETAILED DESCRIPTION

This disclosure relates generally to quantum and classical circuit systems, and specifically to Reciprocal Quantum Logic (RQL) circuit simulation system. The RQL circuit simulation system includes a circuit design tool configured to facilitate user inputs to design an RQL circuit design that can be simulated in the RQL circuit simulation system. The RQL circuit design can be stored in a memory system that can also store an RQL component library. The RQL component library can store a plurality of predetermined RQL circuit design components that each has associated predetermined RQL component metrics. The predetermined RQL circuit design components can have been designed via the circuit design tool, and can include Josephson transmission lines (JTLs) and/or RQL gates (e.g., superconducting logic gates). For example, the predetermined RQL circuit design components can be provided to a circuit simulator for a calculation of the RQL component metrics. For example, the RQL component metrics can include timing data associated with at least one Josephson junction and/or timing behavior of single-flux quantum (SFQ) pulses associated with each of the respective predetermined RQL circuit design components.

The RQL circuit design can be accessed by the circuit simulator for simulation of the operational characteristics of the RQL circuit design. The circuit simulator can include a performance metric compiler configured to evaluate the RQL circuit design to determine the RQL circuit design components associated with the RQL circuit design, and can access each of the predetermined RQL circuit design components from the RQL component library to compile aggregate performance metrics associated with the RQL circuit design. Thus, the circuit simulator can simulate the RQL circuit design via a processor based on the aggregate performance metrics, such as to determine operational behavior and/or logic success of the RQL circuit design. The circuit simulator can provide the simulation results to the circuit design tool, such that the circuit design tool can receive additional user inputs to provide optimization of the RQL circuit design in a feedback manner.

FIG. 1illustrates an example of a Reciprocal Quantum Logic (RQL) circuit simulation system10. The RQL circuit simulation system10can be implemented for designing and simulating circuits, such as complementary metal-oxide semiconductor (CMOS) circuits, Reciprocal Quantum Logic (RQL) circuits, or a combination of both.

The RQL circuit simulation system10includes a circuit design tool12, a memory system14, and a circuit simulator16. The circuit design tool12can be configured as any of a variety of types of user interfaces for receiving user inputs to design circuits, such as a computer, a dedicated workstation, an Internet portal, a graphical user interface (GUI), or any of a variety of other types of user interfaces. For example, the circuit design tool12can be configured as a circuit synthesis tool (e.g., commercially available) configured to design CMOS and/or RQL circuits, such as based on behavioral Register Transfer Level (RTL) code, VHSIC Hardware Description Language (VHDL) code, or Verilog code. The memory system14can be configured as a memory device or an arrangement of multiple memory devices that are configured to store data, such as in an associated computer system that includes the circuit design tool12. The circuit simulator16is configured to simulate circuits that are designed via the circuit design tool12, such as including classical computing circuit systems (e.g., CMOS circuits) and quantum computing circuit systems (e.g., RQL circuits). The circuit simulator16can be configured, for example, as a software component that is executed by a processor18and stored in the memory system14, or can be configured as an application specific integrated circuit (ASIC) or as part of an ASIC. As an example, the circuit simulator16can be configured as a physical circuit simulation engine, a logical circuit simulation engine, or a combination thereof.

In the example ofFIG. 1, the circuit design tool12can be configured to facilitate user inputs to design an RQL circuit design20that is stored in the memory system14. The RQL circuit design20can correspond to a collection of quantum computing components and a collection of classical computing components with which the quantum computing components can interact. For example, the RQL circuit design20can include one or more Josephson transmission lines (JTLs) that interconnect one or more RQL gate circuits that are configured to perform logic operations, such as based on a sequence of single-flux quantum (SFQ) pulses. As another example, the circuit design tool12can be configured to design an RQL circuit design component, such that it can constitute a portion of a larger RQL circuit design20, and thus a larger overall circuit. As described herein, the term “RQL circuit design component” describes a circuit component that is a building-block of a larger circuit, such that a larger functional RQL circuit (e.g., the RQL circuit design20) is composed of a plurality of predetermined RQL circuit design components coupled together to provide the composite function of the larger functional RQL circuit.

The memory system14also stores an RQL component library22that is configured to store a plurality of predetermined RQL circuit design components24. For example, the predetermined RQL circuit design components24can have been designed via the circuit design tool12and stored in the RQL component library22for the purpose of designing the RQL circuit design20based on a combination of predetermined RQL circuit design components24in the RQL component library22. The RQL component library22is also configured to store predetermined RQL component metrics associated with each respective one of the predetermined RQL circuit design components24. The RQL component metrics can include a variety of performance data, such as timing data and timing behavior, associated with each of the predetermined RQL circuit design components24under a variety of operating conditions. For example, the RQL component metrics can include performance data associated with at least one Josephson junction associated with the predetermined RQL circuit design components24, behavioral response to both positive and negative SFQ pulses, and/or corner metrics associated with an amplitude range of at least one of a bias (e.g. a bias current) and a clock signal associated with the RQL circuit design20. Therefore, the RQL component library22can store information that is pertinent to performance of each respective one of the predetermined RQL circuit design components in an individual manner.

The circuit simulator16includes the processor18and a performance metric compiler26. The processor18can be a processor specific to the circuit simulator16, or can be a processor that controls the RQL circuit simulation system10. The performance metric compiler26can be configured to implement post-processing of simulation data that is provided from a circuit simulator (e.g., the circuit simulator16) with respect to a circuit design (e.g., the RQL circuit design20). For example, the performance metric compiler26is configured to access the RQL circuit design20from the memory system14, as well as the access the predetermined RQL circuit design components24from the RQL component library22, to compile performance metrics associated with the RQL circuit design20based on the RQL component metrics associated with each respective one of the predetermined RQL circuit design components24associated with the RQL circuit design20. For example, the performance metric compiler26can be configured to evaluate the RQL circuit design20to identify the quantity and types of the predetermined RQL circuit design components24that constitute the RQL circuit design20. Thus, upon determining the predetermined RQL circuit design components24that collectively form the RQL circuit design20, the performance metric compiler26can access the RQL component metrics associated with each of the respective predetermined RQL circuit design components24. Accordingly, the performance metric compiler26can compile aggregate performance metrics associated with the RQL circuit design20based on the individual performance metrics of each of the respective predetermined RQL circuit design components24, in both quantity and type, that form the RQL circuit design20. Alternatively, the predetermined RQL circuit design components24can be communicated automatically to the performance metric compiler26in response to generation of or saving of the RQL circuit design20, such that the performance metric compiler26can compile aggregate performance metrics associated with the RQL circuit design20substantially automatically, such that the aggregate performance metrics can be saved in the memory system14along with the RQL circuit design20.

Based on the aggregate performance metrics of the RQL circuit design20, the processor18can be configured to simulate the RQL circuit design20. The simulation of the RQL circuit design20can be based on the aggregate performance metrics, such that the simulation of the RQL circuit design20can test operational and behavioral characteristics of the RQL circuit design20. For example, the simulation of the RQL circuit design20can be implemented to test performance of the RQL circuit design20and/or can indicate logic failures associated with the operation of the RQL circuit design20, such as based on the design parameters and/or the peripheral operational parameters of the RQL circuit design20. In the example ofFIG. 1, the simulation results of the simulation can be communicated from the circuit simulator16back to the circuit design tool12to provide the simulation results in a useful format to one or more respective users. As a result, the user(s) can implement the circuit design tool12to modify the RQL circuit design20in a feedback manner, such as in real-time, to optimize the RQL circuit design20. Therefore, the user(s) can monitor the effects of changes to RQL circuit design20in substantial real-time to facilitate changes to the RQL circuit design20to yield desired results.

In addition, in the example ofFIG. 1, the circuit simulator16also includes a circuit metric calculator28. As described earlier, the circuit design tool12can be configured to design an RQL circuit design component24, such that the RQL circuit design component24designed via the circuit design tool12can be stored in the RQL component library22in the memory system14. The circuit metric calculator28can be configured to calculate the RQL component metrics associated with the RQL circuit design component24that is designed via the circuit design tool12. For example, the circuit design tool12can be implemented to provide a predetermined set of test parameters, such as via the circuit simulator16, on the designed RQL circuit design component24based on the type of RQL circuit design component24(e.g., a JTL circuit system or an RQL gate circuit system). Thus, the circuit metric calculator28can calculate the RQL component metrics of the RQL circuit design component24with respect to the behavior of the RQL circuit design component24in response to the predetermined set of test parameters. Accordingly, the circuit metric calculator28can save the RQL component metrics of the respective RQL circuit design component24in the RQL component library22with the respective RQL circuit design component24. As a result, the performance metric compiler26can later access the predetermined RQL circuit design component24to determine the respective RQL component metrics of the respective predetermined RQL circuit design component24to compile the performance metrics of an associated RQL circuit design20that includes the respective RQL circuit design component24.

FIG. 2illustrates an example of an RQL component library50. The RQL component library50can correspond to the RQL component library22in the example ofFIG. 1. Therefore, reference is to be made to the example ofFIG. 1in the following description of the example ofFIG. 2.

The RQL component library50includes a plurality X of JTL circuit components52, where X is a positive integer, that forms a first subset of the predetermined RQL circuit design components stored in the RQL component library50(e.g., corresponding to the predetermined RQL circuit design components24in the example ofFIG. 1). The JTL circuit components52can each correspond to different types of JTL circuits that are each unique with respect to each other. As an example, the JTL circuit components52can correspond to different combinations of Josephson junctions, nodal junctions between and including sets of Josephson junctions, flux-shuttles, and/or a variety of other combinations of the Josephson junctions for propagating positive and/or negative SFQ pulses between devices (e.g., RQL gate circuit devices) in a given RQL circuit (e.g., the RQL circuit design20). Each of the JTL circuit components52includes a set of RQL component metrics54that are associated with the behavioral and/or timing characteristics of the respective JTL circuit components52. For example, the behavioral and/or timing characteristics can correspond to performance data associated with at least one Josephson junction associated with the respective JTL circuit component52, behavioral response to both positive and negative SFQ pulses, and/or corner metrics associated with an amplitude range of at least one of a bias (e.g., bias current) and a clock signal based on which the respective JTL circuit component52can operate.

The RQL component library50includes a plurality Y of RQL gate circuit components56, where Y is a positive integer, that forms a second subset of the predetermined RQL circuit design components stored in the RQL component library50(e.g., corresponding to the predetermined RQL circuit design components24in the example ofFIG. 1). The RQL gate circuit components56can each correspond to different types of RQL logic gates and/or devices that are each unique with respect to each other. As an example, the RQL gate circuit components56can correspond to different types of variable resonators (e.g., qubits), superconducting quantum interference devices (SQUIDs), arrangements of Josephson junctions, and/or a variety of other combinations of circuit devices for performing logic operations based on positive and/or negative SFQ pulses provided from and to JTLs (e.g., JTL circuit components52) in a given RQL circuit (e.g., the RQL circuit design20). Each of the RQL gate circuit components56includes a set of RQL component metrics58that are associated with the behavioral and/or timing characteristics of the respective RQL gate circuit components58. For example, the behavioral and/or timing characteristics can correspond to performance data associated with at least one Josephson junction associated with the respective RQL gate circuit component52, behavioral response to both positive and negative SFQ pulses, and/or corner metrics associated with an amplitude range of at least one of a bias current and a clock signal based on which the respective RQL gate circuit component52can operate.

The RQL component metrics54and58can be calculated by the component metric calculator28, such as in response to design of the respective JTL circuit components52and RQL gate circuit components56. As an example, a given JTL circuit component52can be provided to the circuit simulator16. JTL circuit components52that are designated as input JTLs can be driven by a conditioned SFQ pulse that is generated by a voltage source that can simulate a switching junction. JTL circuit components52that are designated as output JTLs can be terminated with a resistor that is approximately equal to an adequate shunt resistance. The behavior of all of the Josephson junctions of the JTL circuit components52can be monitored and evaluated based on a specific set of defined metrics, such as described in greater detail herein. Additionally, the JTL circuit components52can be tested based on a predetermined set of criteria to determine logical success or failure of the JTL circuit components52. As an example, the JTL circuit components52can be implemented in a test environment in which an SFQ pulse is propagated through a predetermined number of Josephson junctions, such as at an extreme input time (e.g., 45°) based on a clock signal, and monitored to determine if there is a logical failure. Furthermore, Josephson junctions in the JTL circuit components52can be evaluated to extract input times of an SFQ pulse at the respective Josephson junctions, and thus also a delay from one Josephson junction to a next in a given JTL circuit component52.

As another example, a given RQL gate circuit component56can likewise be provided to the circuit simulator16to calculate the RQL component metrics58. The RQL gate circuit component56can be arranged between predetermined JTL circuits or a single input Josephson junction and a single output Josephson junction, and can be coupled to a bias cell in the simulation environment provided by the circuit simulator16. Inductance values associated with the RQL gate circuit component56can be replaced with variables that can be unique to a given inductor associated with a respective bias arrangement (e.g., based on the bias cell) and/or the RQL gate circuit component56, and critical current density associated with the Josephson junctions therein can be changed to variables. Thus, the behavior of the RQL gate circuit component56can be tested in the simulated environment to calculate the RQL component metrics associated with the respective RQL gate component56. For example, an SFQ pulse delay (e.g., positive and negative) can be calculated based on a timing difference between the switching of an input Josephson junction relative to the switching of a first Josephson junction at an output of the RQL gate circuit component56. As another example, a pass/fail analysis can be conducted for a given RQL gate circuit component56based on providing an input time of approximately 90° with respect to a clock signal phase, such that the input time is late enough in the phase of the clock signal to fail while still allowing some time for propagation of the respective SFQ pulses through associated JTLs (e.g., at the input and/or output of the RQL gate circuit component56).

Additionally, for both the JTL circuit components52and the RQL gate circuit components56, the test parameters can be variably adjusted, such that corner metrics associated with the changes to the test parameters can be calculated and saved as part of the respective RQL component metrics54and58. For example, the circuit metric calculator28can be configured to sweep across a range of amplitudes associated with external factors, such as an AC clock bias current and/or a DC flux bias current, and/or a range of amplitudes associated with fabrication parameters, such as a global inductance and/or a critical current density. As an example, the circuit metric calculator28can hold a given one or more of the test parameters at a constant nominal magnitude, such as but not limited to the target operating value of the parameters, to determine the operational behavior of the JTL circuit components52and/or the RQL gate circuit components56. Additionally, the corner metrics can include ranges of the test parameters at which logical failure can occur for the respective JTL circuit components52and the RQL gate circuit components56. Thus, the corner metrics data can be included as part of the respective RQL component metrics54and58, such that the simulator circuit16can facilitate simulation of the RQL circuit design20that includes the respective JTL circuit components52and the RQL gate circuit components56based additionally on the corner metrics.

FIG. 3illustrates an example of an RQL component metrics file100. The RQL component metrics file100can correspond to a software file that is stored in the RQL component library22in the example ofFIG. 1, and can be associated with a respective one of the predetermined RQL circuit design components24to describe the behavioral and/or timing characteristics of the respective predetermined RQL circuit design component24. For example, the RQL component metrics file100can correspond to the RQL component metrics54associated with one of the JTL circuit components52or the RQL component metrics58associated with one of the RQL gate circuit components56. Therefore, reference is to be made to the examples ofFIGS. 1 and 2in the following description of the example ofFIG. 3.

In the example ofFIG. 3, the RQL component metrics file100includes a junction phase timing metric102corresponding to a time for a phase shift of one or more Josephson junctions in the respective predetermined RQL circuit design component. For example, the junction phase timing metric102can include a risetime of the Josepson junction(s) from 0 to 2π, demonstrated at104, and a falltime of the Josephson junction(s) from 2π to 0, demonstrated at106. The junction phase timing metric102also includes corner metrics108that can include an effect of variations in test parameters (e.g., bias current amplitude and/or clock signal amplitude) on the rise time104and/or the fall time106associated with the phase changes of the respective Josephson junction(s).

The RQL component metrics file100also includes a junction overshoot metric110corresponding to characteristics of overshoot exhibited by the one or more Josephson junctions in the respective predetermined RQL circuit design component, such as corresponding to a time and a magnitude of phase overshoot in response to an SFQ pulse. For example, the junction overshoot metric110can include overshoot characteristics associated with a positive SFQ pulse, demonstrated at112, and overshoot characteristics associated with a negative SFQ pulse, demonstrated at114. The junction overshoot metric110also includes corner metrics116that can include an effect of variations in test parameters (e.g., bias current amplitude and/or clock signal amplitude) on the overshoot characteristics of the respective Josephson junction(s) in response to the positive and negative SFQ pulses.

The RQL component metrics file100also includes a delay symmetry metric118corresponding to a gate delay symmetry between positive and negative SFQ pulses at separate respective inputs of the respective predetermined RQL circuit design component (e.g., an RQL gate circuit component). For example, the delay symmetry metric118can include an acceptable delay time associated with receipt of positive SFQ pulses at respective inputs, demonstrated at120, and an acceptable delay time associated with receipt of negative SFQ pulses at respective inputs, demonstrated at122. Therefore, the delay symmetry metric118can define ranges of delay times of the positive and negative SFQ pulses120and122for acceptable operation of the predetermined RQL circuit design component, and thus likewise can also define unacceptable delay symmetry times that can result in a logical failure of the predetermined RQL circuit design component. The delay symmetry metric118also includes corner metrics120that can include an effect of variations in test parameters (e.g., bias current amplitude and/or clock signal amplitude) on the gate delay symmetry times associated with the positive and negative SFQ pulses.

The RQL component metrics file100also includes a total delay metric124corresponding to a total delay of SFQ pulses through the predetermined RQL circuit design component (e.g., through the respective JTL circuit component52and/or the respective RQL gate circuit components56). For example, the total delay metric124can include a total delay time associated with propagation of a positive SFQ pulse through the respective predetermined RQL circuit design component, demonstrated at126, and a total delay time associated with propagation of a negative SFQ pulse through the respective predetermined RQL circuit design component, demonstrated at128. The total delay metric124also includes corner metrics130that can include an effect of variations in test parameters (e.g., bias current amplitude and/or clock signal amplitude) on the total delay times associated with the positive SFQ pulses126and the negative SFQ pulses128.

The RQL component metrics file100also includes a delay symmetry metric132corresponding to a gate delay symmetry between positive and negative SFQ pulses. The delay symmetry metric132can thus include data associated with a range of times for acceptable operation of the predetermined RQL circuit design component based on a delay between being provided respective positive and negative SFQ pulses, and thus likewise also defining unacceptable delay times that can result in a logical failure of the predetermined RQL circuit design component. The delay symmetry metric132also includes corner metrics134that can include an effect of variations in test parameters (e.g., bias current amplitude and/or clock signal amplitude) on the gate delay times associated with the positive and negative SFQ pulses.

It is to be understood that the RQL component metrics file100is not limited to the example ofFIG. 3. As an example, the RQL component metrics file100can include more or less metrics associated with the Josephson junctions and timing behavior with respect to positive and/or negative SFQ pulses. Therefore, the RQL component metrics file100is provided as but one example of a set of metrics that can define the timing behavior of a respective predetermined RQL circuit design component, such that the set of metrics can be compiled to determine aggregate performance metrics of an associated RQL circuit design20.

FIG. 4illustrates another example of an RQL circuit simulation system150. The RQL circuit simulation system150can correspond to a portion of the RQL circuit simulation system10in the example ofFIG. 1. In the example ofFIG. 4, a circuit design tool (e.g., the circuit design tool12) can be configured to facilitate user inputs to design an RQL circuit design152, such as can be stored in a memory system (e.g., the memory system14). The RQL circuit design152can correspond to a collection of quantum computing components and a collection of classical computing components with which the quantum computing components can interact. In the example ofFIG. 4, the RQL circuit design152includes one or more JTL circuit components154and one or more RQL gate circuit components156, such as corresponding to the predetermined RQL circuit design components24in the example ofFIG. 1(e.g., corresponding to the JTL circuit components52and the RQL gate circuit components56, respectively, in the example ofFIG. 2).

The RQL circuit simulation system150can be configured to simulate operation of the RQL circuit design152, such as via the circuit simulator16in the example ofFIG. 1. As an example, the JTL circuit component(s)154and the RQL gate circuit component(s)156can be stored as respective predetermined RQL circuit design components in an RQL component library in a memory system158. Therefore, the respective circuit design tool can be implemented to selectively design the RQL circuit design152based on the respective predetermined RQL circuit design components stored therein, including the JTL circuit component(s)154and the RQL gate circuit component(s)156. Similar to as described previously, each of the JTL circuit component(s)154and the RQL gate circuit component(s)156can have an associated respective RQL component metrics file stored in the memory system158. As an example, the associated respective RQL component metrics files associated with each of the JTL circuit component(s)154and the RQL gate circuit component(s)156can be arranged substantially similar to the RQL component metrics file100in the example ofFIG. 3. Thus, the RQL component metrics files can each include a variety of performance data, such as timing data and timing behavior, associated with each of the JTL circuit component(s)154and the RQL gate circuit component(s)156in the RQL circuit design152under a variety of operating conditions.

The RQL circuit simulation system150also includes a processor160and a performance metric compiler162. In the example ofFIG. 4, in response to initiation of a simulation or during design of the RQL circuit design152(e.g., via the circuit design tool12), the performance metric compiler162is configured to access each of the JTL circuit component(s)154and the RQL gate circuit component(s)156from the RQL component library in the memory system158to compile performance metrics associated with the RQL circuit design152based on the RQL component metrics associated with each respective one of the JTL circuit component(s)154and the RQL gate circuit component(s)156. For example, the performance metric compiler162can be configured to evaluate the RQL circuit design152to identify the quantity and types of each of the JTL circuit component(s)154and the RQL gate circuit component(s)156that constitute the RQL circuit design152. Thus, the performance metric compiler162can compile aggregate performance metrics associated with the RQL circuit design152based on the individual performance metrics each of the JTL circuit component(s)154and the RQL gate circuit component(s)156. In the example ofFIG. 4, the aggregate performance metrics are provided to the processor160as a signal TM_DT, such that the processor160can simulate the RQL circuit design152based on the aggregate performance metrics of the RQL circuit design152.

Accordingly, the RQL circuit design152can be simulated based on the aggregate performance metrics to test operational and behavioral characteristics of the RQL circuit design152. For example, the simulation of the RQL circuit design152can be implemented to test performance of the RQL circuit design152and/or can indicate logic failures associated with the operation of the RQL circuit design152, such as based on the design parameters and/or the peripheral operational parameters of the RQL circuit design152. In the example ofFIG. 4, the simulation results of the simulation can be communicated from the circuit simulator156back to a respective circuit design tool to provide the simulation results in a useful format to one or more respective users. As a result, the user(s) can implement the circuit design tool to modify the RQL circuit design152in a feedback manner, such as in real-time, to optimize the RQL circuit design152. Therefore, the user(s) can monitor the effects of changes to RQL circuit design152in substantial real-time to facilitate changes to the RQL circuit design152to yield desired results.

FIG. 5illustrates an example of a method200for simulating an RQL circuit design (e.g., the RQL circuit design20). At202, user inputs are facilitated via a circuit design tool (e.g., the circuit design tool12) to design a plurality of predetermined RQL circuit design components (e.g., the predetermined RQL circuit design components24). At204, predetermined RQL component metrics (e.g., stored in the RQL component metric file100) associated with each of the plurality of predetermined RQL circuit design components are calculated. At206, the predetermined RQL circuit design components and the associated predetermined RQL component metrics are stored in an RQL component library (e.g., the RQL component library22). At208, user inputs are facilitated via the circuit design tool to design the RQL circuit design comprising at least one of the plurality of predetermined RQL circuit design components. At210, aggregate performance metrics (e.g., the aggregate performance metrics TM_DT) associated with the RQL circuit design are compiled (e.g., via the performance metric compiler26) based on the predetermined RQL component metrics associated with the respective at least one of plurality of predetermined RQL circuit design components. At212, the RQL circuit design is simulated via a circuit simulator (e.g., the circuit simulator16) based on the aggregate performance metrics.

In view of the foregoing structural and functional description, those skilled in the art will appreciate that portions of the systems and method disclosed herein may be embodied as a method, data processing system, or computer program product such as a non-transitory computer readable medium. Accordingly, these portions of the approach disclosed herein may take the form of an entirely hardware embodiment, an entirely software embodiment (e.g., in a non-transitory machine readable medium), or an embodiment combining software and hardware. Furthermore, portions of the systems and method disclosed herein may be a computer program product on a computer-usable storage medium having computer readable program code on the medium. Any suitable computer-readable medium may be utilized including, but not limited to, static and dynamic storage devices, hard disks, optical storage devices, and magnetic storage devices.

Certain embodiments have also been described herein with reference to block illustrations of methods, systems, and computer program products. It will be understood that blocks of the illustrations, and combinations of blocks in the illustrations, can be implemented by computer-executable instructions. These computer-executable instructions may be provided to one or more processors of a general purpose computer, special purpose computer, or other programmable data processing apparatus (or a combination of devices and circuits) to produce a machine, such that the instructions, which execute via the one or more processors, implement the functions specified in the block or blocks.