Displacement method to grow cu overburden

A damascene-formed conductive region having a recess formed at the top surface thereof by a chemical-mechanical polish (CMP) process is repaired or regrown using a displacement method. A displacement material is deposited over the recessed conductive material. The displacement material is removed from a top surface of the insulating layer surrounding the damascene conductive region, and the semiconductor device is placed in a solution. The displacement material reacts with the solution, and copper in the solution is grown as a result of the displacement over the recess of the conductive region. The displacement method results in reducing or eliminating the recess formed by the CMP process.

TECHNICAL FIELD

The present invention relates generally to the fabrication of semiconductor devices, and more particularly to the fabrication of conductive lines of semiconductor devices using a damascene process.

BACKGROUND

Semiconductor devices are used in many electronic applications, such as radios, televisions, cell phones and computers, as examples. Semiconductor devices are often fabricated as integrated circuits, with hundreds or thousands devices often being manufactured on a single chip.

Semiconductor devices are typically manufactured by depositing several insulating, conducting, and semiconductor layers over a workpiece, and patterning each layer to form conductive lines and electrical circuit elements therein. Metallization layers are usually used for the interconnect layers of semiconductor devices. In multi-level metallization schemes, these metallization layers have insulating layers or inter-level dielectric layers (ILD) disposed between each metallization layer, with vias formed within the ILD layer that provide vertical electrical connection for the semiconductor device.

For many years, aluminum was the preferred choice of material for interconnect layers of semiconductor devices. Aluminum is advantageous in that it may be patterned in a subtractive etch process, e.g., a layer of aluminum is deposited, photoresist is deposited over the aluminum layer, the photoresist is patterned, and then the photoresist is used as a mask while exposed portions of the aluminum are removed in a subtractive etch process.

However, to improve device function and efficiency, copper is being used more and more as a material for interconnections because of its low resistivity, high melting point, and superior electromigration endurance. Copper is also advantageous as an interconnect material because of its stress-void resistance improvement over aluminum. However, copper is difficult to etch in a subtractive process; therefore, copper is usually patterned using damascene processes.

FIG. 1illustrates a cross-sectional view of a semiconductor device100in which conductive lines will be formed in a damascene process, and will be described herein in accordance with a prior art process. A workpiece110which may comprise a silicon substrate, for example, is provided. An insulating layer112is deposited or formed over the workpiece110. The insulating layer112is patterned, for example, using traditional photolithography techniques and a photoresist. The pattern formed in the insulating layer112comprises the pattern for conductive lines that will be formed. A liner114may be deposited over the insulating layer112, particularly if the conductive lines comprise copper, for example. A conductive material116, which may comprise copper, for example, is deposited over the liner114, as shown. The conductive material116has a top surface that is relatively conformal to the underlying topography of the insulating layer1112. For example, the conductive material116may have a recess formed over the top of the trench in the insulating layer112for the conductive lines.

To form conductive lines in the insulating layer112, the insulating layer112is planarized, for example, using a chemical-mechanical polish (CMP) process to remove the conductive material116and the liner114from the top surface of the insulating layer112, as shown inFIG. 2. Adisadvantage of using a CMP process to remove excess conductive material116and liner114from the top surface of the insulating layer112is that the copper material116dishes or forms a recess118below the top surface of the insulating layer112, as shown. The erosion, recess or dishing118is undesirable because the conducting area of the conductive material116is reduced and the sheet resistance of the conductive material116is increased.

What is needed in the art is a method of forming copper damascene conductive lines that has reduced dishing and/or no dishing at all of the copper conductive lines.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention, which provide a method of increasing copper material in a recessed area after a copper CMP step. A displacement method is used to grow a copper overburden, which decreases or eliminates the copper CMP dishing. A displacement material is deposited over the recessed copper conductive lines and the workpiece is placed in a copper and fluorine containing solution. The displacement material reacts with the fluorine in the solution, and copper from the solution is deposited over the recessed conductive line, filling in the recess at least partially, repairing the recess and growing a copper overburden.

In accordance with a preferred embodiment of the present invention, a method of forming conductive regions of a semiconductor device includes providing a workpiece, the workpiece having an insulating layer disposed thereon, the insulating layer being patterned with a pattern for at least one conductive region and having a top surface, and filling the patterned insulating layer with a conductive material. The workpiece is planarized to remove the conductive material from over the top surface of the insulating layer, leaving the conductive material recessed beneath the top surface of the insulating layer, a displacement material is deposited over the recessed conductive material and exposed portions of the insulating layer, and the workpiece is planarized to remove the displacement material from over the top surface of the insulating layer. The displacement material is reacted with a solution containing the conductive material to remove the displacement material from over the recessed conductive material and fill the conductive material recess at least partially with conductive material from the solution.

In accordance with another preferred embodiment of the present invention, a method of growing copper over chemically-mechanically polished recessed copper conductive lines of a semiconductor device includes providing a workpiece, disposing an insulating layer over the workpiece, the insulating layer having a top surface, and patterning the insulating layer with a pattern for at least one conductive region. The method includes forming a layer of copper over the insulating layer to fill the patterned insulating layer with copper, planarizing the workpiece to remove the copper from the top surface of the insulating layer, leaving the copper recessed beneath the top surface of the insulating layer, and depositing a displacement material over the recessed copper and exposed portions of the insulating layer. The method further includes planarizing the workpiece to remove the displacement material from over the top surface of the insulating layer, and exposing the workpiece to a solution containing copper and fluorine, removing the displacement material from over the recessed copper and filling the copper recess at least partially with copper from the solution.

In accordance with yet another preferred embodiment of the present invention, a method of repairing a recessed chemically-mechanically polished damascene conductive region of a semiconductor device includes providing a workpiece, the workpiece having a patterned insulating layer disposed thereon and a chemically-mechanically polished conductive material having a recessed top surface residing in the patterned insulating layer. The method includes depositing a displacement material over the recessed conductive material and exposed portions of the insulating layer, planarizing the workpiece to remove the displacement material from over the top surface of the insulating layer, and reacting the displacement material with a solution containing the conductive material to remove the displacement material from over the recessed conductive material and fill the conductive material recess at least partially with conductive material from the solution.

Embodiments of the present invention achieve technical advantages as a method of decreasing or eliminating the recess that is created during a CMP process of damascene conductive lines, repairing the damaged conductive lines and resulting in an increased conductive area of the copper conductive line and decreased sheet resistance.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to preferred embodiments in a specific context, namely, a damascene process for forming copper conductive lines or regions. The invention may also be applied, however, to other damascene processes for forming other conductive regions and materials, and also to multiple-damascene processes such as a dual-damascene process, for example, where the underlying insulating layer is patterned using more than one mask.

With reference now toFIG. 3, a semiconductor device200comprises a workpiece210. The workpiece210typically comprises silicon oxide over a single crystal silicon wafer. The workpiece210may include other conductive layers or other semiconductor elements, e.g., transistors, diodes, etc. Compound semiconductors such as GaAs, InP, Si/Ge, SiC, for example, may be used in place of silicon.

An insulating layer212is deposited over the workpiece210, as shown in FIG.3. The insulating layer212may comprise an ILD layer, for example, and typically comprises silicon dioxide or other insulating materials. Alternatively, the insulating layer212may comprise low-k dielectric materials or high-k dielectric materials, for example. If the conductive lines will comprise copper, often a low-k dielectric material will be used to reduce the R-C time delay of the device, for example.

Using a damascene process, the insulating layer212is patterned and etched to form at least one trench in which conductive lines or regions will later be formed. The at least one trench may comprise a long thin line that is straight, or may comprise square or circular shapes, as examples. The trenches may have 90-degree turns and may be coupled to vias or other circuit elements that are formed in previously formed insulating layers, not shown.

A liner214may be deposited over the insulating layer212. The liner214may comprise a barrier layer of TaN, Ta or Ti, or combinations thereof, deposited by physical vapor deposition (PVD), in a thickness of 100 to 200 Angstroms, as examples. The barrier layer of the liner214may alternatively comprise other materials and thicknesses, deposited by other methods, for example. The liner214may also comprise a seed layer disposed over the barrier layer, comprising sputtered copper, as an example.

Next, a layer of conductive material216, preferably comprising copper or a copper alloy, and alternatively comprising other metals, is deposited over the liner214to fill the trenches. The conductive material216may be deposited by sputtering, electrolysis copper plating (ECP), or electroless copper plating, as examples. After being deposited, the conductive material216typically covers the entire top surface219of the insulating layer212.

A CMP process is performed on the wafer210to remove the conductive material216and the liner214from the top surface219of the insulating layer212. As a result of the CMP process, during the CMP process, the conductive material216is removed not only from the top surface219of the insulating layer212, but the conductive material is also removed below the top surface of insulating layer212by a recessed amount, creating dishing or recessing218. The height of the recess218may be 10 to 100 nanometers lower than the top surface219of the insulating layer, for example. The conductive line214/216comprises the liner214and the conductive material216.

In accordance with embodiments of the present invention, next, a displacement material220is deposited over insulating layer212and conductive lines214/216, as shown in FIG.3. The displacement material220preferably comprises Si, Ti or Ta, as examples, although alternatively, the displacement material220may comprise other materials. The displacement material220may be deposited by PVD, e.g. sputtering, or chemical vapor deposition (CVD), as examples. The thickness of the displacement material220deposited preferably ranges from approximately 10 to 1500 Angstroms, and more preferably, ranges from 500 to 1500 Angstroms, as examples.

The displacement material220is planarized, e.g., with a CMP process to remove portions of the displacement material220from the top of the insulating layer212, as shown in FIG.4. After the CMP process, a portion of the displacement material220remains on top of the conductive lines214/216within the recess218. After the CMP process, the displacement material220is recessed slightly below the top surface219of the insulating material212.

Next, referring toFIG. 5, the workpiece210is placed in, e.g., submerged in a solution221. The solution221preferably comprises both copper and fluorine, for example. In one embodiment, for example, the solution221preferably comprises fluorine (F) in a F-complex such as HF, which is dissolved in water. The copper is an ion that is dissolved in the solution221.

The displacement material220reacts with the solution221to form a reactant that is distributed uniformly in the solution221. The copper in the solution221displaces the displacement material220, as the displacement material220reacts with the solution221. Therefore, in accordance with the embodiments of the present invention, copper is grown in the recessed surface218of the conductive line216in a displacement. For example, if silicon (Si) is used for the displacement material220, the chemical reaction that occurs is:
Si+6F−+2Cu++=>2Cu+SiF6.
In another embodiment, the displacement material220comprises tantalum (Ta). In this embodiment, the chemical reaction that occurs is:
2Ta+12F−+5Cu++==>5Cu+2TaF6.
In another embodiment of the present invention, the displacement material220comprises titanium (Ti). In this embodiment, the chemical reaction that occurs is the following:
2Ti+12F−+5Cu++==>5Cu+2TiF6.

A cross-sectional view of the semiconductor device200after reacting the displacement material220with the solution221is shown inFIG. 6a. In one embodiment, after the reaction with the solution221(not shown inFIG. 6a, see FIG.5), the conductive material216recess has been filled in completely, as shown at222. Alternatively, in another embodiment, the conductive material216may be partially grown such that the recess223has a height greater than the height of the recess218shown in FIG.3. In yet another embodiment shown inFIG. 6b, the conductive material224is slightly overgrown so that the height224of the top surface of the conductive material216is greater than the height of the top surface219of the insulating layer212.

Embodiments of the present invention achieve technical advantages by repairing or growing the recess218that is formed in a CMP process for copper conductive lines214/216. The dishing218that is formed during the copper CMP process may be reduced (the term “reduced” used herein with reference to the recess refers to filling in or re-growing the recess), as shown inFIG. 6aat223. Alternatively, the recess may be completely eliminated, as shown inFIG. 6aat222, or may be overgrown, as shown inFIG. 6bat224. A smooth overburdened copper surface222,223, and224is formed on the conductive material216, which reduces the sheet resistance and improves the performance of the semiconductor device. Semiconductor devices utilizing embodiments of the present invention benefit from increased signal speed, decreased heat generated when current is run through the conductive lines216, and reduced power consumption.

Embodiments of the present invention have been described herein with reference to copper as the conductive material216. However, embodiments of the present invention are beneficial in forming conductive lines from any conductive material that suffers from recessing during the CMP process from a damascene process.

Furthermore, although the conductive structure214/216has been described herein as a conductive line, alternatively, the conductive region214/216may comprise a contact pad or other contact region of a semiconductor device200.