Memory devices

A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims benefit of priority to Korean Patent Application No. 10-2015-0186005, filed on Dec. 24, 2015 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Field

The present inventive concept relates to memory devices.

Description of Related Art

Electronics are increasingly required to process high-capacity data while being gradually reduced in volume. Accordingly, an increase in a degree of integration of semiconductor memory elements used for electronics is required. As one method of increasing a degree of integration of semiconductor memory elements, a memory device having a vertical transistor structure in lieu of a conventional planar transistor structure has been proposed.

SUMMARY

An aspect of the present inventive concept may provide memory devices, which may prevent the occurrence of defects by accurately measuring a location of a pad region when the pad region connected to a contact plug is formed.

According to an aspect of the present inventive concept, memory devices may include a plurality of channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent to at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer, wherein each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers, and a vertical insulating layer extending from the interlayer insulating layer to be disposed between the plurality of channel regions and the plurality of cell contact plugs, and having a portion surrounded by at least one of the plurality of gate electrode layers.

According to an aspect of the present inventive concept, memory devices may include a first region having a plurality of channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers disposed to be adjacent the plurality of channel regions, and gate insulating films disposed between the plurality of channel regions and the plurality of gate electrode layers, a second region disposed to be adjacent the first region, and having a plurality of cell contact plugs connected to the plurality of gate electrode layers extending in a first direction parallel to the upper surface of the substrate to have different lengths, respectively, and a vertical insulating layer disposed to be adjacent a border between the first region and the second region, and having a portion adjacent at least one of the plurality of gate electrode layers in a direction parallel to the upper surface of the substrate.

According to an aspect of the present inventive concept, memory device may include a substrate, a plurality of channel regions extending in a direction perpendicular to an upper surface of a substrate, a gate structure stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, and having a plurality of gate electrode layers and a plurality of insulating layers extending in a first direction to have different lengths, respectively, a plurality of isolation insulating layers dividing the gate structure into a plurality of unit regions, and a vertical insulating layer disposed between an end of the plurality of gate electrode layers in the first direction and the plurality of channel regions to pass through an uppermost insulating layer of the plurality of insulating layers, and provided in at least a portion of the plurality of unit regions.

Some embodiments of the present inventive concept are directed to memory devices that may include a plurality of channel regions in a first region of a substrate and that extend in a direction that is perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate, wherein the plurality of gate electrode layers are adjacent at least a portion of the plurality of channel regions, and a plurality of cell contact plugs, wherein each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. Devices may include a second region of the substrate that is adjacent the first region of the substrate, a plurality of cell contact plugs connected to the plurality of gate electrode layers that extend in a first direction that is parallel to the upper surface of the substrate, and a vertical insulating layer that is between the plurality of channel regions and the plurality of cell contact plugs and that includes a portion that is adjacent a border between the first region and the second region.

It is noted that aspects of the inventive concept described with respect to one embodiment, may be incorporated in a different embodiment although not specifically described relative thereto. That is, all embodiments and/or features of any embodiment can be combined in any way and/or combination. These and other objects and/or aspects of the present inventive concept are explained in detail in the specification set forth below.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present inventive concept will be described as follows with reference to the attached drawings.

Hereinafter, embodiments of the present inventive concept will be described with reference to schematic views illustrating embodiments of the present inventive concept. In the drawings, for example, due to manufacturing techniques and/or tolerances, modifications of the shape shown may be estimated. Thus, embodiments of the present inventive concept should not be construed as being limited to the particular shapes of regions shown herein, for example, and may include changes in shapes resulting from manufacturing errors. The following embodiments may also be constituted by one or a combination thereof.

The contents of the present inventive concept described below may have a variety of configurations and only a required configuration is proposed herein, but the present inventive concept is not limited thereto.

FIG. 1is a schematic block diagram of a memory device according to some embodiments of the present inventive concept.

Referring toFIG. 1, a semiconductor device10according to some embodiments of the present inventive concept may include a memory cell array20, a row decoder30, and a core logic circuit55. The core logic circuit55may include a read/write circuit40and a control circuit50.

The memory cell array20may include a plurality of memory cells arranged in a plurality of rows and a plurality of columns. The plurality of memory cells included in the memory cell array20may be connected to the row decoder30through a word line WL, a common source line CSL, a string select line SSL, a ground select line GSL, and the like, and may be connected to the read/write circuit40through a bit line BL. According to an example embodiment, a plurality of memory cells arranged in an identical row may be connected to a single word line WL, and a plurality of memory cells arranged in an identical column may be connected to a single bit line BL.

The plurality of memory cells included in the memory cell array20may be divided into a plurality of memory blocks. Each of the memory blocks may include a plurality of word lines WLs, a plurality of string select lines SSLs, a plurality of ground select lines GSLs, a plurality of bit lines BLs, and at least one common source line CSL.

The row decoder30may receive address ADDR information externally, and may decode the received ADDR information to select at least a portion of the word line WL, the common source line CSL, the string select line SSL, and the ground select line GSL connected to the memory cell array20.

The read/write circuit40may select at least a portion of the bit lines BLs connected to the memory cell array20in response to a command received from the control circuit50. The read/write circuit40may read data stored in a memory cell connected to the selected at least a portion of the bit lines BLs, or may write data to the memory cell connected to the selected at least a portion of the bit lines BLs. The read/write circuit40may include circuits such as a page buffer, an input/output (I/O) buffer, a data latch, and the like to perform the above operations.

The control circuit50may control operations of the row decoder30and the read/write circuit40in response to a control signal CTRL transmitted from an external source. When data stored in the memory cell array20is read, the control circuit50may control the row decoder30to supply a voltage for a data reading operation to a word line WL in which data is stored. When a voltage for a data reading operation is supplied to a certain word line WL, the control circuit50may control the read/write circuit40to read data stored in a memory cell connected to the word line WL to which the voltage for a data reading operation is supplied.

Meanwhile, when data is written to the memory cell array20, the control circuit50may control the row decoder30to supply a voltage for a data writing operation to a word line WL to which data is written. When a voltage for a data writing operation is supplied to a certain word line WL, the control circuit50may control the read/write circuit40to write data to a memory cell connected to the word line WL to which the voltage for a data writing operation is supplied.

FIG. 2is an equivalent circuit diagram of a memory cell array of a memory device according to some embodiments of the present inventive concept. A semiconductor device according to some embodiments may be provided as a vertical NAND flash element.

Referring toFIG. 2, the memory cell array may include a plurality of memory cell strings S, each of which including n memory cells MC1to MCn connected to each other in series, and a ground select transistor GST and a string select transistor SST connected to both ends of the memory cells MC1to MCn in series. At least one dummy transistor can be connected between the ground select transistor GST and the memory cell MC1, and between the string select transistor SST and the memory cell MCn.

The n memory cells MC1to MCn connected to each other in series may be respectively connected to n word lines WL1to WLn for selecting the memory cells MC1to MCn.

A gate terminal of the ground select transistor GST may be connected to a ground select line GSL, and a source terminal of the ground select transistor GST may be connected to a common source line CSL. Meanwhile, a gate terminal of the string select transistor SST may be connected to a string select line SSL, and a source terminal of the string select transistor SST may be connected to a drain terminal of the memory cell MCn.FIG. 2illustrates a structure in which the ground select transistor GST and the string select transistor SST are connected to the n memory cells MC1to MCn connected to each other in series one by one. In a different manner, a plurality of ground select transistors GSTs or a plurality of string select transistors SSTs may also be connected to the n memory cells MC1to MCn.

A drain terminal of the string select transistor SST may be connected to a plurality of bit lines BL1to BLm. When a signal is applied to the gate terminal of the string select transistor SST through the string select line SSL, a signal applied through the plurality of bit lines BL1to BLm may be transmitted to the n memory cells MC1to MCn connected to each other in series, and a data reading operation or a data writing operation may be performed. In addition, when the source terminal of the string select transistor SST applies a signal to the gate terminal of the gate select transistor GST connected to the common source line CSL through the gate select line GSL, an erasing operation of removing all electric charges stored in the n memory cells MC1to MCn may be performed.

FIG. 3is a plan view of a memory device according to some embodiments of the present inventive concept.

Referring toFIG. 3, a memory device100according to some embodiments may have a cell region C and a peripheral circuit region P that is adjacent the cell region C. The cell region C may include channel regions CH extending in a direction perpendicular to an upper surface of a substrate101, and a plurality of cell contact plugs181to186collectively represented by a cell contact plug180and connected to a plurality of gate electrode layers stacked on the substrate101to be adjacent the channel regions CH. Meanwhile, the peripheral circuit region P may include a plurality of peripheral contact plugs220connected to peripheral circuit devices210formed on the substrate101. In the cell region C, the channel regions CH and the gate electrode layers may be divided into a plurality of portions by isolation insulating layers102. Meanwhile, an interlayer insulating layer disposed on the substrate101to cover the plurality of gate electrode layers, the peripheral circuit devices210, and the like, may be omitted from the illustration ofFIG. 3.

The upper surface of the substrate101may correspond to an X-Y plane, and the channel regions CH and the cell contact plug180may extend in a direction (a Z-axis direction ofFIG. 3) that is perpendicular to the upper surface of the substrate101. The plurality of gate electrode layers connected to the cell contact plug180may be disposed in the Z-axis direction to be stacked on the upper surface of the substrate101corresponding to the X-Y plane. A plurality of insulating layers may be disposed between the plurality of gate electrode layers in the Z-axis direction, respectively, and the plurality of gate electrode layers and the plurality of insulating layers may form gate structures.

The channel regions CH may be disposed to be spaced apart from each other on the X-Y plane. The number and an arrangement of the channel regions CHs may be various according to example embodiments, and for example, may also be disposed in a zigzag form as illustrated inFIG. 3. The arrangement of the channel regions CHs that are adjacent one another with the isolation insulating layers102interposed therebetween may be symmetrical as illustrated inFIG. 3, but the present inventive concept is not limited thereto. The channel regions CH may extend in the direction perpendicular to the upper surface of the substrate101, the Z-axis direction ofFIG. 3, to pass through the gate structures.

The plurality of gate electrode layers, the plurality of channel regions CHs, and the like may be divided into a plurality of unit regions by common source lines103and the isolation insulating layers102disposed around the common source lines103. Each of the plurality of unit regions defined by the common source lines103and the isolation insulating layers102may be provided as a unit cell of the memory device100. Each of the common source lines103may have a source region provided on a lower portion thereof in the Z-axis direction.

An interlayer insulating layer may be provided on the substrate101across the cell region C and the peripheral circuit region P. The interlayer insulating layer may cover the plurality of gate electrode layers, the peripheral circuit devices210, and the like, and may include a silicon oxide and/or a silicon nitride. The illustration ofFIG. 3may omit the interlayer insulating layer in order to describe an internal structure of the memory device100in more detail.

Each of the peripheral circuit devices210may include a planar transistor, and may include active regions213provided as a drain or source region, and a planar gate electrode layer211. The active regions213may be formed by injecting an impurity into portions of the substrate101, and the active regions213and the planar gate electrode layer211may intersect each other. The active regions213and the planar gate electrode layer211may be connected to the plurality of peripheral contact plugs220, respectively.

Meanwhile, referring toFIG. 3, the cell region C may include a first region C1in which the channel regions CH are disposed and a second region C2in which the cell contact plug180is connected to the plurality of gate electrode layers. The second region C2may be disposed between the first region C1and the peripheral circuit region P. Vertical insulating layers190may be provided to be adjacent a border between the first region C1and the second region C2.

The vertical insulating layers190may be inserted into the gate structures from upper surfaces of the gate structures to a predetermined depth, respectively, and may include an insulating material. According to some embodiments, each of the vertical insulating layers190may extend from the interlayer insulating layer disposed on each of the gate structures. According to some embodiments illustrated inFIG. 3, the vertical insulating layers190are illustrated as each having a rectangular cross section on the X-Y plane, but in a different manner, a cross section of each of the vertical insulating layers190may be modified to have various forms such as a triangle, a square, a circle, an oval, and the like.

The vertical insulating layers190may be provided in predetermined reference positions in a process of forming the second region C2, respectively. In the second region C2, the plurality of gate electrode layers may extend in a first direction (an X-axis direction ofFIG. 3) to have different lengths, respectively, and may be connected to the cell contact plug180. Therefore, when a length of each of the plurality of gate electrode layers is not properly limited in the second region C2, an open defect in which at least a portion of the cell contact plug180is not connected to the gate electrode layers or a short circuit defect in which the at least a portion of the cell contact plug180is connected to two or more of the gate electrode layers may occur.

According to the some embodiments, locations of ends of the plurality of gate electrode layers may be determined in the first direction, based on trenches provided to form the vertical insulating layers190. Therefore, since the length of each of the plurality of gate electrode layers is properly controlled in the second region C2, an open defect or a short circuit defect that may occur when the cell contact plug180is formed may be prevented.

The vertical insulating layers190may have certain thicknesses, respectively, to be utilized as reference locations in a process of forming the plurality of gate electrode layers to have different lengths, respectively. As an example, each of the vertical insulating layers190may have a thickness whereby a portion of an uppermost gate electrode layer of the gate electrode layers may be recessed in the Z-axis direction. In some embodiments, each of the vertical insulating layers190may also penetrate the uppermost gate electrode layer in the Z-axis direction. The features of a manufacturing process may allow each of the vertical insulating layers190to have a greater thickness than that of the uppermost insulating layer147.

According to the example embodiments ofFIG. 3, the vertical insulating layers190may be disposed one by one within the plurality of unit regions defined by the isolation insulating layers102. The vertical insulating layers190may also not be disposed within a portion of the plurality of unit regions. A width W2of each of the plurality of vertical insulating layers190may be limited to a certain reference value or less to prevent a deterioration in the characteristics of gate electrode layers recessed or penetrated by the vertical insulating layers190. According to some embodiments, the width W2of each of the plurality of vertical insulating layers190may be ½ or less of a width W1of each of the unit regions.

Meanwhile, a dummy trench195may be adjacent a border between the peripheral circuit region P and the cell region C. The dummy trench195may be provided as a portion in which the dummy trench195may be inserted into the substrate101to a certain depth, and may include an insulating material. The dummy trench195may be provided as a reference location for measuring locations of the plurality of gate electrode layers within the second region C2as in the vertical insulating layers190.

FIG. 4is a partially-cutaway perspective view of region A1of the memory device illustrated inFIG. 3.

Referring toFIG. 4, the memory device100according to some embodiments of the present inventive concept may include a channel layer110extending in the direction perpendicular to the upper surface of the substrate101, a plurality of gate electrode layers131to136collectively represented by a gate electrode layer130and stacked on the upper surface of the substrate101to be adjacent the channel layer110, and an interlayer insulating layer150and the plurality of cell contact plugs181to186provided on the gate electrode layer130, the plurality of cell contact plugs181to186collectively represented by the cell contact plug180. The cell contact plug180may pass through the interlayer insulating layer150to be connected to the gate electrode layer130. The gate electrode layers131to136may have a plurality of insulating layers141to147collectively represented by an insulating layer140therebetween, and a stack of the gate electrode layer130and the insulating layer140may be provided as the gate structure.

The channel layer110may be formed in a cavity passing through the gate structure, and may have an annular shape having a hollow. A space formed in the center of the channel layer110may be filled with an embedded insulating layer113, and the channel layer110may have a conductive layer115formed thereon. The conductive layer115may be connected to a bit line to be provided as a drain region of a plurality of memory cell devices formed in the cell region C.

Each of the gate electrode layers131to136may provide a gate electrode of a ground select transistor GST, a plurality of memory cell transistors MC1to MCn, and a string select transistor SST. The gate electrode layer130may extend while forming word lines WL1to WLn, and may be commonly connected to adjacent memory cell strings of predetermined units arranged in the first direction (X-axis direction) and the second direction (Y-axis direction). According to some embodiments, the total number of the gate electrode layers131to136forming the memory cell transistors MC1to MCn may be 2N(in which, N is a positive integer).

The gate electrode layer131of the ground select transistor GST may be connected to a ground select line GSL.FIG. 5illustrates a single gate electrode layer136of the string select transistor SST and a single gate electrode layer131of the ground select transistor GST, but the number of each of the gate electrode layer136and the gate electrode layer131is not limited to one. Meanwhile, the gate electrode layer136of the string select transistor SST and the gate electrode layer131of the ground select transistor GST may also have a structure that is different from that of the gate electrode layers132to135of the memory cell transistors MC1to MCn. The string select transistor SST may also be provided as a plurality of string select transistors SSTs within a single memory cell array.

The plurality of gate electrode layers131to136and the insulating layers141to147may extend in the first direction (X-axis direction) to have different lengths, respectively, to form a plurality of pad regions having a stepped shape. The plurality of pad regions may be provided by the plurality of gate electrode layers131to136and the plurality of insulating layers141to147respectively extending in the stacking direction (Z-axis direction) to have lengths different from those of another plurality of gate electrode layers131to136and another plurality of insulating layers141to147adjacent thereto.FIG. 4illustrates the insulating layer140positioned above the gate electrode layer130in the Z-axis direction in each of the pad regions, but in a different manner, the gate electrode layer130may be positioned above the insulating layer140.

The gate electrode layer130may include a polycrystalline silicon material and/or a metallic silicide material. The metal silicide material may be, for example, a silicide material including a metal selected from cobalt (Co), nickel (Ni), hafnium (Hf), platinum (Pt), tungsten (W), and/or titanium (Ti). According to some embodiments, the gate electrode layer130may also include a metallic material such as tungsten (W). In addition, although not illustrated, the gate electrode layer130may further include a diffusion barrier, and the diffusion barrier may include, for example, at least one of a tungsten nitride (WN), a tantalum nitride (TaN), and/or a titanium nitride (TiN).

The plurality of insulating layers141to147and the plurality of gate electrode layers131to136alternately stacked with each other, may be isolated from each other by the isolation insulating layers102in the Y-axis direction as in the gate electrode layer130. The insulating layer.140may include an insulating material such as a silicon oxide and/or a silicon nitride.

A gate insulating film may be disposed between the channel layer110and the gate electrode layer130and include a blocking layer162, an electric charge storage layer164, and a tunneling layer166. A structure of the memory device100may allow all of the blocking layer162, the electric charge storage layer164, and the tunneling layer166to surround the gate electrode layer130. In some embodiments, at least a portion of the gate insulating film may extend in the Z-axis direction in parallel to the channel layer110to be disposed outside of the channel layer110, and the remainder of the gate insulating film may be disposed to surround the gate electrode layer130. According to example embodiments illustrated inFIG. 4, the electric charge storage layer164and the tunneling layer166may be disposed outside the channel layer110to extend in the Z-axis direction in parallel to the channel layer110, and the blocking layer162may be disposed to surround the gate electrode layer130.

The blocking layer162may include, for example, a silicon oxide (SiO2), a silicon nitride (Si3N4), a silicon oxynitride (SiON) and/or a high-dielectric constant dielectric material. The high-dielectric constant dielectric material may be provided as one of an aluminum oxide (Al2O3), a tantalum oxide (Ta2O3), a titanium oxide (TiO2), a yttrium oxide (Y2O3), a zirconium oxide (ZrO2), a zirconium silicon oxide (ZrSixOy), a hafnium oxide (HfO2), a hafnium silicon oxide (HfSixOy), a lanthanum oxide (La2O3), a lanthanum aluminum oxide (LaAlxOy), a lanthanum hafnium oxide (LaHfxOy), a hafnium aluminum oxide (HfAlxOy), and/or a praseodymium oxide (Pr2O3). When the blocking layer162includes the high-dielectric constant dielectric material, the term “high-dielectric constant” may be defined as having a meaning in which a dielectric constant of the blocking layer162is higher than that of the tunneling layer166or a silicon oxide.

The blocking layer162may selectively include a plurality of layers having different dielectric constants, respectively. In this case, a layer having a relatively low dielectric constant among the plurality of layers may be disposed to be closer to the channel layer110than a layer having a relatively high dielectric constant thereamong, so that an energy gap such as a barrier height may be controlled, thereby improving the characteristics of the memory device100, for example, erase features.

The electric charge storage layer164may be provided as an electric charge trapping layer or a conductive floating gate layer. When the electric charge storage layer164is provided as the conductive floating gate layer, the electric charge storage layer164may be formed by depositing polycrystalline silicon using low pressure chemical vapor deposition (LPCVD). When the electric charge storage layer164is provided as the electric charge trapping layer, the electric charge storage layer164may include at least one of a silicon oxide (SiO2), a silicon nitride (Si3N4), a silicon oxynitride (SiON), a hafnium oxide (HfO2), a zirconium oxide (ZrO2), a tantalum oxide (Ta2O3), a titanium oxide (TiO2), a hafnium aluminum oxide (HfAlxOy), a hafnium tantalum oxide (HfTaxOy), a hafnium silicon oxide (HfSixOy), an aluminum nitride (AlxNy), and/or an aluminum gallium nitride (AlGaxNy).

The tunneling layer166may include at least one of a silicon oxide (SiO2), a silicon nitride (Si3N4), a silicon oxynitride (SiON), a hafnium oxide (HfO2), a hafnium silicon oxide (HfSixOy), an aluminum oxide (Al2O3), and/or a zirconium oxide (ZrO2).

The peripheral circuit device210may be disposed in the peripheral circuit region P. The peripheral circuit device210may include the active regions213formed by injecting the impurity into the portions of the substrate101, the planar gate electrode layer211intersecting the active regions213, and a planar gate insulating film212disposed between the planar gate electrode layer211and the substrate101. The planar gate electrode layer211may have gate spacers214disposed on side surfaces thereof. The active regions213may be provided as a source or drain region of the peripheral circuit device210, and may have an isolation layer215disposed outwardly thereof, respectively. At least a portion of the active region213may also be shared by two or more peripheral circuit devices210that are adjacent one another.

The peripheral circuit device210may have a cover layer230formed thereon. The cover layer230may include a material having a predetermined etch selectivity ratio with the interlayer insulating layer150. For example, when the interlayer insulating layer150includes a silicon oxide film, the cover layer230may include a silicon nitride film. The cover layer230may prevent the active region213from being excessively recessed in a process of forming the plurality of peripheral contact plugs220. The cover layer230may also be selectively removed from a portion of the planar gate electrode layer211. Therefore, the peripheral contact plugs220may be connected to the planar gate electrode layer211without contacting the cover layer230.

Meanwhile, the memory device100according to some example embodiments may include the interlayer insulating layer150disposed on the substrate101. The interlayer insulating layer150may include a first interlayer insulating layer151and a second interlayer insulating layer153. The first interlayer insulating layer151and the second interlayer insulating layer153may include the same material, for example, a silicon oxide or a silicon nitride. The first interlayer insulating layer151may cover the peripheral circuit device210. In particular, the first interlayer insulating layer151may also be formed only in a portion in which the peripheral circuit device210may be formed. As described above, the first interlayer insulating layer151may include a high density plasma (HDP) oxide film, and the second interlayer insulating layer153may include a tetraethyl orthosilicate (TEOS) oxide film. The second interlayer insulating layer153may be formed using a process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), sub-atmospheric chemical vapor deposition (SACVD), low pressure chemical vapor deposition (LPCVD), and/or plasma enhanced chemical vapor deposition (PECVD).

Referring toFIG. 4, the memory device100according to some embodiments may include the vertical insulating layer190. The vertical insulating layer190may have a structure in which the vertical insulating layer190is inserted into the gate structure from the upper surface of the gate structure to a certain depth, and may be provided as a portion extending from the interlayer insulating layer150. According to some embodiments, the vertical insulating layer190may be provided as a portion including an insulating material different from that of the interlayer insulating layer150. The vertical insulating layer190may be surrounded by at least one gate electrode layer136in at least a portion thereof. According to example embodiments illustrated inFIG. 4, the vertical insulating layer190may pass through the uppermost gate electrode layer136, and may be surrounded by a gate electrode layer136that is adjacent the uppermost gate electrode layer136in the direction (X-axis or Y-axis direction) parallel to the upper surface of the substrate101.

A thickness of the vertical insulating layer190may be greater than that of each of the plurality of insulating layers141to147. The vertical insulating layer190may pass through the uppermost insulating layer147, and at least a portion of the vertical insulating layer190may be adjacent to the gate insulating film. According to some embodiments illustrated inFIG. 4, the vertical insulating layer190may pass through the uppermost gate electrode layer136so that a portion of a side surface of the vertical insulating layer190may contact the blocking layer162. When the vertical insulating layer190does not pass through the uppermost gate electrode layer136, the portion of the side surface of the vertical insulating layer190and a lower surface thereof may contact the blocking layer162.

Meanwhile, the dummy trench195may be provided between the gate electrode layer130and the peripheral circuit device210. The dummy trench195may have a structure in which the dummy trench195may be inserted into the substrate101to a certain depth, and may include an insulating material. The dummy trench195may be provided as a reference location for measuring a length of the gate electrode layer130in the first direction (X-axis direction) as similar with the vertical insulating layer190.

FIG. 5is a cross-sectional view taken along line I-P of the memory device100illustrated inFIG. 3.

Referring toFIG. 5, the memory device100according to some embodiments of the present inventive concept may include the gate electrode layer130and the insulating layer140stacked on the substrate101. The gate electrode layer130and the insulating layer140may form the gate structure, and the second interlayer insulating layer153may be provided on the gate structure. The gate structure may be divided into the plurality of unit regions by the isolation insulating layers102and the common source lines103.

The plurality of unit regions may have the vertical insulating layers190formed in at least a portion thereof. According to the some embodiments illustrated inFIG. 5, the vertical insulating layers190may be illustrated by being formed one by one in each unit region, but in a different manner, may not be formed in a portion of the plurality of unit regions. Each of the vertical insulating layers190may be provided as a portion extending from the second interlayer insulating layer153, and may be inserted into a portion of the gate structure. Referring toFIG. 5, a thickness T2of each of the vertical insulating layers190may be greater than a thickness T1of the uppermost insulating layer147. Therefore, each of the vertical insulating layers190may be inserted into or penetrate through at least a portion of the uppermost gate electrode layer136. According to some embodiments, each of the vertical insulating layers190may also pass through the gate electrode layer130from the uppermost gate electrode layer136.

Meanwhile, a width W2of each of the plurality of vertical insulating layers190may be less than a width W1of each of the unit regions. In particular, when each of the vertical insulating layers190is inserted into or passes through the at least a portion of the uppermost gate electrode layer136, the width W2of each of the vertical insulating layers190may be less than the width W1of each of the unit regions for an electrical connection of the uppermost gate electrode layer136. According to some embodiments, the width W2may also be limited to be ½ or less of the width W1.

FIG. 6is a plan view of a memory device according to some embodiments of the present inventive concept.

Referring toFIG. 6, a memory device300according to some embodiments may include a plurality of gate electrode layers, a plurality of channel regions CH, and a plurality of cell contact plugs381to386collectively represented by a cell contact plug380. The plurality of gate electrode layers and the plurality of channel regions CH may be divided into a plurality of unit regions by isolation insulating layers302and common source lines303.

The memory device300according to the example embodiment illustrated inFIG. 6may include a cell region C and a peripheral circuit region P (refer toFIG. 7) disposed in a vertical direction. As an example, the memory device300may have a cell-on-peri (COP) structure in which the cell region C may be disposed on the peripheral circuit region P. Therefore, inFIG. 6, the plan view illustrates the cell region C, and the peripheral circuit region P positioned below the cell region C may not be illustrated.

The plurality of unit regions defined by the isolation insulating layers302may include vertical insulating layers390, respectively. The vertical insulating layers390may have a structure in which the vertical insulating layers390may be inserted into portions of gate structures defined by the plurality of gate electrode layers and the plurality of insulating layer alternately stacked, respectively. Each of the vertical insulating layers390may have a thickness by which at least one of the plurality of gate electrode layers and the plurality of insulating layers may be penetrated.

Each of the vertical insulating layers390may be used as a reference position for measuring a length of each of the plurality of gate electrode layers respectively extending in a first direction (an X-axis direction ofFIG. 6) to have different lengths in a second region C2. When the length of each of the plurality of gate electrode layers is not properly limited in the second region C2, a defect in which at least a portion of the cell contact plug380is not connected to the gate electrode layers or is connected to two or more of the gate electrode layers may occur.

According to some embodiments, the vertical insulating layers390may be formed before forming the plurality of gate electrode layers. A process of manufacturing the memory device300according to example embodiments may include alternately stacking a plurality of sacrificial layers and a plurality of insulating layers on a substrate301, preparing trenches for forming the vertical insulating layers390, and repeatedly etching the plurality of sacrificial layers and the plurality of insulating layers. By repeatedly etching the plurality of sacrificial layers and the plurality of insulating layers, the plurality of gate electrode layers may extend to have different lengths, respectively, in the second region C2.

The trenches for forming the vertical insulating layers390may be used as a certain reference location in the process of etching the plurality of sacrificial layers and the plurality of insulating layers. In more detail, the process of etching the plurality of sacrificial layers and the plurality of insulating layers may be performed while measuring lengths of the plurality of sacrificial layers and the plurality of insulating layers in the first direction (the X-axis direction) based on the trenches. Therefore, the lengths of the plurality of gate electrode layers extending in the second region C2may be accurately controlled, and a defect rate that may occur when the cell contact plug380is formed may be reduced.

A width W4of each of the plurality of vertical insulating layers390may be less than a width W3of each of the plurality of unit regions. When at least one of the plurality of gate electrode layers is penetrated or recessed by each of the vertical insulating layers390, the width W4of each of the vertical insulating layers390may be less than ½ of the width W3of each of the plurality of unit regions to prevent a deterioration in electrical characteristics due to the vertical insulating layers390. The memory device300will hereinafter be described with reference toFIGS. 7 and 8.

FIG. 7is a partially-cutaway perspective view of region A2of the memory device300illustrated inFIG. 6.FIG. 8is a cross-sectional view taken along line II-II′ of the memory device300illustrated inFIG. 6.

Referring toFIG. 7, the memory device300according to some embodiments of the present inventive concept may include the cell region C and the peripheral circuit region P disposed in the vertical direction. In more detail, the memory device300may have the COP structure in which the cell region C may be disposed on the peripheral circuit region P. Alternatively, unlike the example embodiment illustrated inFIG. 7, the memory device300may also have a peri-on-cell (POC) structure in which the peripheral circuit region P may be disposed on the cell region C.

The cell region C may include the first substrate301, a plurality of gate electrode layers331to336collectively represented by a gate electrode layer330and formed on the first substrate301, a plurality of insulating layers341to347collectively represented by an insulating layer340and formed on the first substrate301, the plurality of cell contact plugs381to386collectively represented by the cell contact plug380and connected to the gate electrode layer330, and a first interlayer insulating layer350. The plurality of gate electrode layers331to336may be alternately stacked with the plurality of insulating layers341to347to form the gate structure. Meanwhile, the cell region C may include the vertical insulating layer390inserted into a portion of the gate structure.

The vertical insulating layer390may include an insulating material, and may be provided as a portion extending from the first interlayer insulating layer350. The vertical insulating layer390may pass through the uppermost insulating layer347in the gate structure to be inserted into at least one gate electrode layer336. As an example, the vertical insulating layer390may also pass through the uppermost gate electrode layer336of the gate electrode layer330.

The peripheral circuit region P disposed below the cell region C may include a second substrate401, a plurality of peripheral circuit devices410formed on the second substrate401, and a second interlayer insulating layer450covering the plurality of peripheral circuit devices410. The second interlayer insulating layer450may have wiring patterns420disposed therein to be connected to the plurality of peripheral circuit devices410. Each of the plurality of peripheral circuit devices410may include active regions413, a planar gate electrode layer411intersecting the active regions413, a planar gate insulating film412formed between the planar gate electrode layer411and the second substrate401, and gate spacers414.

In the COP structure in which the cell region C may be disposed on the peripheral circuit region P, the first substrate301may be disposed on the second interlayer insulating layer450. Therefore, the first substrate301and the second substrate401may have different degrees of crystallinity, respectively. According to some embodiments, the second substrate401may be provided as a single crystalline silicon substrate, and the first substrate301may be provided as a poly crystalline silicon substrate.

A channel layer310may extend in a direction perpendicular to an upper surface of the first substrate301, and may have an annular shape having a hollow. The channel layer310may be filled with an embedded insulating layer313, and a gate insulating film may be disposed between the channel layer310and the gate electrode layer330. The gate insulating film may include a blocking layer362, an electric charge storage layer364, and a tunneling layer366. At least a portion of the gate insulating film may be disposed in parallel to the channel layer310, and the remainder of the gate insulating film may be disposed to surround the gate electrode layer330. In some embodiments, the whole of the gate insulating film may be disposed to surround the gate electrode layer330or to be parallel to the channel layer310.

The plurality of gate electrode layers331to336and the plurality of insulating layers341to347may extend in the first direction (the X-axis direction) to have different lengths, respectively. As illustrated inFIG. 7, each of the gate electrode layers331to336and each of the insulating layers341to347may form pairs, and may extend in the first direction to have different lengths, respectively, to form pad regions. The pad regions may correspond to the second region C2illustrated inFIG. 6, the cell contact plug380may pass through the first interlayer insulating layer350in the pad regions to be connected to the gate electrode layer330.

Referring toFIG. 8, the vertical insulating layers390may be disposed in the plurality of unit regions, defined by the isolation insulating layers302and the common source lines303, in the cell region C, respectively. The number of the vertical insulating layers390may be less than or equal to that of the plurality of unit regions. The width W4of each of the vertical insulating layers390may be limited to be less than or equal to ½ of the width W3of each of the unit regions to prevent a deterioration in electrical characteristics of the uppermost gate electrode layer336recessed or penetrated by each of the vertical insulating layers390. Meanwhile, a thickness T4of each of the vertical insulating layers390may be greater than a thickness T3of the uppermost insulating layer347included in each of the gate structures.

The memory device300according to example embodiments illustrated inFIG. 7may have the peripheral circuit region P and the cell region C disposed vertically, and the plurality of substrates301and401may thus be required. Therefore, unlike the memory device100illustrated inFIGS. 3 through 5, the peripheral circuit devices410may be formed on the second substrate401, and an additional process may thus be required to form a dummy trench in the first substrate301. According to some embodiments, the length of the gate electrode layer330in the first substrate (the X-axis direction) may be adjusted using trenches provided to form the vertical insulating layers390in the gate structures without forming the dummy trench in the first substrate301. Therefore, the number of processes of manufacturing the memory device300may be reduced as compared to forming the dummy trench in the first substrate301.

FIG. 9is a plan view of a memory device according to some embodiments of the present inventive concept.

Referring toFIG. 9, a memory device500according to some embodiments may have a cell region C and a peripheral circuit region P. The cell region C may include gate structures including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate501, and channel regions CH passing through each of the gate structures to be adjacent the plurality of gate electrode layers. The cell region C may include a first region C1and a second region C2, and the second region C2may be defined by a portion in which the plurality of gate electrode layers may be connected to a plurality of cell contact plugs581to586collectively represented by a cell contact plug580. The plurality of gate electrode layers may extend in a first direction (an X-axis direction) to have different lengths, respectively, in the second region C2.

The cell region C may be divided into a plurality of unit regions by isolation insulating layers502and common source lines503. The isolation insulating layers502and the common source lines503may extend in the first direction, and may be erected in a stacking direction (a Z-axis direction) perpendicular to an upper surface of the substrate501, the stacking direction in which the plurality of gate electrode layers are stacked.

The peripheral circuit region P may include a plurality of peripheral circuit devices610. Each of the peripheral circuit devices610may include active regions613and a planar gate electrode layer611intersecting the active regions613. The active regions613and the planar gate electrode layer611may be connected to a plurality of peripheral contact plugs620, respectively.

Meanwhile, the memory device500according to the example embodiment may include vertical insulating layers590and a dummy trench595. Each of the vertical insulating layers590may be inserted into a portion of each of the gate structures, and the dummy trench595may be inserted into a portion of the substrate501. The vertical insulating layers590may be disposed within the plurality of unit regions defined by the isolation insulating layers502, respectively. In addition, the vertical insulating layers590may have various different shapes other than a cross shape illustrated inFIG. 9, and the dummy trench595may have a line shape extending in a second direction (a Y-axis direction).

A width W6of each of the plurality of vertical insulating layers590may be less than a width W5of each of the unit regions. According to some embodiments, the width W6of each of the plurality of vertical insulating layers590may be less than or equal to ½ of the width W5of each of the unit regions. The width W6of each of the plurality of vertical insulating layers590may be set under the conditions described above, and a short circuit or a deterioration in electrical characteristics may be prevented from occurring in the gate electrode layers. The vertical insulating layers590and the dummy trench595may be used as certain reference locations in a process of forming the plurality of gate electrode layers to have different lengths, respectively, in the first direction in the second region C2.

FIG. 10is a partially-cutaway perspective view of region A3of the memory device500illustrated inFIG. 9.

Referring toFIG. 10, the memory device500according to some embodiments may have the cell region C and the peripheral circuit region P. The cell region C may include a plurality of gate electrode layers531to536collectively represented by a gate electrode layer530, a plurality of insulating layers541to547collectively represented by an insulating layer540, the gate electrode layers531to536and the insulating layers541to547alternately stacked on the substrate501, a channel layer510extending in the direction perpendicular to the upper surface of the substrate501, a gate insulating film562,564, and566disposed between the channel layer510and the gate electrode layer530, and the like. The gate electrode layer530and the insulating layer540may form the gate structure, and the gate structure may have the vertical insulating layer590formed therein.

The peripheral circuit region P may include the peripheral circuit device610. The peripheral circuit device610may have the active regions613and the planar gate electrode layer611, and the planar gate electrode layer611and the substrate501may have a planar gate insulating film612disposed therebetween. The planar gate electrode layer611may have gate spacers614provided on side surfaces thereof, respectively, and the peripheral circuit device610may have a cover layer630provided thereon. Meanwhile, an interlayer insulating layer550may be provided across the cell region C and the peripheral circuit region P, and may include a first interlayer insulating layer551and a second interlayer insulating layer553.

Meanwhile, the vertical insulating layer590may be provided in the cell region C, and the dummy trench595may be provided in close proximity to a border between the cell region C and the peripheral circuit region P. The dummy trench595may be provided as a portion inserted into the substrate501. The vertical insulating layer590may be provided as a portion in which the vertical insulating layer590may extend from the interlayer insulating layer550, in particular, the second interlayer insulating layer553, and may have a depth allowing at least one gate electrode layer530to penetrate therethrough.

According to some embodiments illustrated inFIG. 10, the vertical insulating layer590may have a depth allowing two or more gate electrode layers, for example, the gate electrode layers535and536, to penetrate therethrough. Therefore, the vertical insulating layer590may be formed using a manufacturing process different from that of the memory devices100and300illustrated inFIGS. 4 and 7.

FIGS. 11A through 22Bare views of a method of manufacturing the memory device100illustrated inFIGS. 3 through 5, respectively.

Referring toFIGS. 11A and 11B, the plurality of peripheral circuit devices210may be disposed on the substrate101in the peripheral circuit region P.FIG. 11Bis a cross-sectional view taken along line ofFIG. 11A. At least a portion of the plurality of peripheral circuit devices210may have different sizes. Each of the peripheral circuit devices210may be provided as a planar transistor, and may include the active regions213, the planar gate electrode layer211, and the planar gate insulating film212. The planar gate electrode layer211may have the gate spacers214provided on the side surfaces thereof, respectively, and the active regions213may have the isolation layer215provided therebetween.

Meanwhile, the dummy trench195may be adjacent the border between the peripheral circuit region P and the cell region C. The dummy trench195may have the depth allowing the dummy trench195to be inserted into at least a portion of the substrate101, and may have a line shape extending in the second direction (the Y-axis direction).FIGS. 11Aand11B illustrate the dummy trench195adjacent the border between the cell region C and the peripheral circuit region P to be included in the peripheral circuit region P, but in a different manner, may be included in the cell region C.

Referring toFIGS. 12A and 12B, the first interlayer insulating layer151may be formed. The first interlayer insulating layer151may cover the plurality of peripheral circuit devices210in the peripheral circuit region P. In order to fill a space between the plurality of peripheral circuit devices210and the substrate101, the first interlayer insulating layer151may include an HDP oxide film having improved gap filling characteristics. The first interlayer insulating layer151may not cover the dummy trench195.

Referring toFIGS. 13A and 13B, a plurality of sacrificial layers121to126collectively represented by a sacrificial layer120and the plurality of insulating layers141to147collectively represented by the insulating layer140may be alternately stacked on the substrate101. The sacrificial layer120and the insulating layer140may include a material having a predetermined etch selectivity ratio. As an example, when the sacrificial layer120includes a silicon nitride, the insulating layer140may include a silicon oxide. InFIGS. 13A and 13B, it is assumed that the sacrificial layer120may include the first to sixth sacrificial layers121to126and the insulating layer140may include the first to seventh insulating layers141to147, but the numbers of the sacrificial layer120and the insulating layer140may be changed according to some embodiments.

Each of the sacrificial layer120and the insulating layer140may have the same or different thicknesses. Referring toFIG. 13B, the first insulating layer141positioned on the top of the insulating layer140in the stacking direction (the Z-axis direction) may have a relatively less thickness than that of the second to seventh insulating layers142to147.

Referring toFIGS. 14A and 14B, when the sacrificial layer120and the insulating layer140are formed, a mask layer M1may be formed thereon. The mask layer M1may have a plurality of open regions O1, and the plurality of open regions O1may allow an upper surface of the seventh insulating layer147to be externally exposed in the cell region C. The mask layer M1may be formed only in the cell region C and may not be formed in the peripheral circuit region P.

Referring toFIGS. 15A and 15B, an etching process may be performed using the mask layer M1. A portion exposed by the mask layer M1may be removed by the etching process. As an example, as illustrated inFIGS. 15A and 15B, portions of the sixth sacrificial layer126positioned on the top of the sacrificial layer120and the seventh insulating layer147positioned on the top of the insulating layer140may be removed by the etching process. Therefore, an upper surface of the sixth insulating layer146may be externally exposed in a portion that may not be covered by the mask layer M1. When the etching process is completed, the mask layer M1may be removed.

In this case, the portions of the sixth sacrificial layer126and the seventh insulating layer147removed by the open regions O1of the mask layer M1may allow a plurality of trenches h1to be formed. The trenches h1may be filled with an insulating material in a subsequent process, and the insulating material provided in the trenches h1may be provided as the vertical insulating layer190illustrated inFIGS. 3 through 5.

Referring toFIGS. 16A and 16B, a mask pattern PM1may be formed on a portion of the upper surface of the seventh insulating layer147. The mask pattern PM1may fill the plurality of trenches h1, and may allow the portion of the upper surface of the seventh insulating layer147to be exposed. Referring toFIGS. 17A and 17B, portions of the sacrificial layer120and the insulating layer140may be etched in the portion exposed by the mask pattern PM1. In this case, the portions of a pair of each of the sacrificial layers121to126and each of the insulating layers141to147that are adjacent one another in the stacking direction of the sacrificial layer120and the insulating layer140may be removed. In more detail, as illustrated inFIGS. 17A and 17B, portions of the fifth and sixth sacrificial layers125and126and the sixth and seventh insulating layers146and147may be removed in the portion exposed by the mask pattern PM1. Therefore, in the portion exposed by the mask pattern PM1, a portion of the upper surface of the sixth insulating layer146and a portion of an upper surface of the fifth insulating layer145may be exposed.

Referring toFIGS. 18A and 18B, the mask pattern PM1may be trimmed. By trimming the mask pattern PM1, a portion of the upper surface of the seventh insulating layer147may be repeatedly exposed. When the mask pattern PM1is trimmed, a length of the mask pattern PM1in the first direction (the X-axis direction) and a thickness of the mask pattern PM1may be reduced.

Referring toFIGS. 19A and 19B, portions of the sacrificial layer120and the insulating layer140may be etched in the portion exposed by the trimmed mask pattern PM1. In this case, as illustrated inFIGS. 17A and 17B, the portions of a pair of each of the sacrificial layers121to126and each of the insulating layers141to147may be removed in the portion exposed by the mask pattern PM1. Therefore, as illustrated inFIGS. 19A and 19B, portions of upper surfaces of the fourth to sixth sacrificial layers144,145, and146may be externally exposed.

By repeating the processes described with reference toFIGS. 16A through 19B, the sacrificial layer120and the insulating layer140may be formed to have a structure illustrated inFIGS. 20A and 20B. The sacrificial layer120and the insulating layer140may have the second interlayer insulating layer153disposed thereon. The second interlayer insulating layer153may account for a relatively greater volume than that of the first interlayer insulating layer151, and may thus include a TEOS oxide film having a high deposition rate. A process of forming the second interlayer insulating layer153may allow the vertical insulating layer190to be formed.

In more detail, the vertical insulating layer190may be formed by filling the trenches h1with the insulating material. As described above, the trenches h1may be formed when the sixth sacrificial layer126positioned on the top of the sacrificial layer120and the seventh insulating layer147positioned on the top of the insulating layer140are removed by the etching process using the mask layer M1. Therefore, the thickness of the vertical insulating layer190may be substantially the same as a sum of a thickness of the sixth sacrificial layer126positioned on the top of the sacrificial layer120and a thickness of the seventh insulating layer147positioned on the top of the insulating layer140.

Meanwhile, when the processes as described above with reference toFIGS. 16A through 19Bare repeated, a length L of each of the pad regions may be determined according to lengths of the mask pattern PM1trimmed in the first direction (the X-axis direction). The length L of each of the pad regions may be properly selected in consideration of the numbers of the sacrificial layer120and the insulating layer140, a size of the memory device100, and the like. When the lengths L of the pad regions are excessively short or have a great variation therein, a defect or the like in which the cell contact plug180formed later is electrically connected to two or more of the gate electrode layers131to136may occur.

According to some embodiments, the lengths L of the pad regions may be controlled using the trenches h1for forming the vertical insulating layer190as a certain reference position. As described above, the lengths L of the pad regions may be determined according to the lengths of the mask pattern PM1trimmed in the first direction. According to the example embodiment, when the processes described with reference toFIGS. 16A through 19Bare performed, the length of the mask pattern PM1trimmed in the first direction may be controlled using the trenches h1as the reference position. Therefore, while the process of forming the pad regions is carried out, the lengths L of the pad regions may be checked, and the occurrence of defects may be prevented and managed more efficiently.

In a general manufacturing process, the trenches h1and the vertical insulating layer190may not be formed, and the lengths L of the pad regions may be measured based on the dummy trench195. In this case, after all of the pad regions are formed, the lengths L of the pad regions may be measured based on the dummy trench195, and it may thus be difficult to determine defect occurrence probability while the process of forming the pad regions is performed. According to some embodiments, while the process of forming the pad regions is performed, the lengths L of the pad regions may be predicted based on the trenches h1and the occurrence of defects may be prevented.

Meanwhile, the trenches h1may also be formed by a different process. According to some embodiments, unlike the embodiments illustrated inFIGS. 14A and 14B, the mask layer M1may be formed across the cell region C and the peripheral circuit region P. In more detail, the mask layer M1may cover the sacrificial layer120and the insulating layer140in the peripheral circuit region P as well as the cell region C. The mask layer M1may be provided in such a shape to form only the trenches h1, and the mask pattern PM1may then be provided to form the pad regions through repeating the etching and trimming processes. According to the some embodiments as described above, the trenches h1may not be formed along with the pad regions, and depths of the trenches h1may be changed.

Referring toFIGS. 21A and 21B, the channel regions CH may be formed. The channel regions CH may extend in the direction (the Z-axis direction) perpendicular to the upper surface of the substrate101, and may include the channel layers110, respectively. Each of the channel layers110may have an annular shape having a hollow, and may have the embedded insulating layer113provided therein. The conductive layer115provided on each of the channel layers110may be connected to the bit line BL to be provided as the drain region of the memory cell array.

An epitaxial layer117may be provided below each of the channel layers110. The epitaxial layer117may be formed by forming openings for forming the channel regions CH and performing a selective epitaxial process using the upper surface of the substrate101, exposed by the openings, as a seed layer. Prior to the formation of the channel layers110, portions164and166of the gate insulating film may also be formed in a direction parallel to each of the channel layers110.

When the channel regions CH are formed, openings for forming the isolation insulating layers102and the common source lines103may be provided, and the sacrificial layer120may be removed through the openings. Portions from which the sacrificial layers121to126are removed may be filled with the gate electrode layers131to136collectively represented by the gate electrode layer130. According to some embodiments, prior to the formation of the gate electrode layer130, a portion of the gate insulating film, for example, the blocking layer162, may be formed. Therefore, as illustrated inFIG. 20B, the blocking layer162may also surround the gate electrode layer130. The blocking layer162surrounding the gate electrode layer130may also be disposed between the vertical insulating layer190and the gate electrode layer130. After the formation of the gate electrode layer130, the isolation insulating layers102and the common source lines103may be formed.

Referring toFIGS. 22A and 22B, the plurality of cell contact plugs181to186collectively represented by the cell contact plug180and the plurality of peripheral contact plugs220may be formed. The cell contact plug180and the peripheral contact plugs220may be formed in different processes or in the same process, and may include a conductive material. The cell contact plug180may be connected to a word line WL.

FIGS. 23A through 28Bare views of methods of manufacturing the memory device300illustrated inFIGS. 6 through 8, respectively.

Referring toFIGS. 23A and 23B, the peripheral circuit region P may have the first substrate301provided thereon. Referring toFIG. 23Billustrating a cross-sectional view taken along line IV-IV′ ofFIG. 23A, the peripheral circuit region P may include the second substrate401, the plurality of peripheral circuit devices410formed on the second substrate401, and the second interlayer insulating layer450. Each of the peripheral circuit devices410may be provided as a planar transistor, and may include the active regions413, the planar gate electrode layer411, and the planar gate insulating film412. The planar gate electrode layer411may have the gate spacers414provided on the side surfaces thereof, respectively, and the active regions413and the planar gate electrode layer411may be electrically connected to the wiring patterns420. The wiring patterns420may be disposed in the second interlayer insulating layer450.

Referring toFIGS. 24A and 24B, a plurality of sacrificial layers321to326collectively represented by a sacrificial layer320and the plurality of insulating layers341to347collectively represented by the insulating layer340may be alternately stacked on the substrate301. The sacrificial layer320and the insulating layer340may include a material having a predetermined etch selectivity ratio. According to some embodiments, the insulating layer340may include a silicon oxide, and the sacrificial layer320may include a silicon nitride. The numbers of the sacrificial layer320and the insulating layer340are not limited to those of the embodiments illustrated inFIGS. 24A and 24B, and may be changed.

A mask layer M2may be disposed on the uppermost insulating layer347. The mask layer M2may allow a portion of the uppermost insulating layer347to be exposed. In particular, the mask layer M2may include open regions O2exposing portions of the uppermost insulating layer347, respectively.

Referring toFIGS. 25A and 25B, an etching process may be performed using the mask layer M2, and portions of the uppermost insulating layer347and the uppermost sacrificial layer346may thus be removed. In particular, the portions of the uppermost insulating layer347and the uppermost sacrificial layer346removed through the open regions O2may allow trenches h2to be formed.

When the etching process is completed, the mask layer M2may be removed, and a mask pattern PM2(refer toFIGS. 26A and 26B) may be formed. As illustrated inFIGS. 26A and 26B, the mask pattern PM2may have an area less than that of the mask layer M2. Therefore, a portion of the uppermost insulating layer347may be exposed by the mask pattern PM2. Meanwhile, the trenches h2may be filled with the mask pattern PM2.

Referring toFIGS. 27A and 27B, an etching process may be performed using the mask pattern PM2, and a stepped structure may thus be formed as illustrated inFIG. 27B. As described with reference toFIGS. 18A and 18B, a process of trimming a portion of the mask pattern PM2and etching portions of the sacrificial layer320and the insulating layer340in the portion may be repeated, and the pad regions having the stepped structures as illustrated inFIGS. 28A and 28Bmay thus be formed.

Lengths L of the pad regions may be determined in the process of trimming the mask pattern PM2. In more detail, the lengths L of the pad regions may correspond to lengths of the mask pattern PM2removed in the first direction (the X-axis direction) when the portion of the mask pattern PM2is trimmed. When the lengths L of the pad regions are not properly controlled, a defect or the like in which the cell contact plug380formed in a subsequent process may not be connected to the gate electrode layer330, or two or more of the gate electrode layers331to336may be connected to one of the cell contact plugs381to386may occur.

According to some embodiments, the portion of the mask pattern PM2may be trimmed based on the trenches h2, and the lengths L of the pad regions may thus be properly controlled. Therefore, the lengths L of the pad regions may be prevented from being excessively increased or decreased, and a short circuit defect in which two or more of the gate electrode layers331to336may be connected to one of the cell contact plugs381to386, or an open defect in which the gate electrode layer330may not be connected to the cell contact plug380may be avoided.

FIGS. 29A through 31Bare views of a method of manufacturing the memory device500illustrated inFIGS. 9 and 10, respectively.

Referring toFIGS. 29A and 29B, a plurality of sacrificial layers521to526collectively represented by a sacrificial layer520and the plurality of insulating layers541to547collectively represented by the insulating layer540may be alternately stacked on the substrate501.FIG. 29Bis a cross-sectional view taken along line V-V′ of the plan view ofFIG. 29A. The peripheral circuit region P may include the plurality of peripheral circuit devices610and the first interlayer insulating layer551covering the peripheral circuit devices610.

Each of the peripheral circuit devices610may be provided as a planar transistor, and may include the active regions613, the planar gate electrode layer612, and the gate spacers614. The active regions613may have the device isolation film615disposed therebetween, and each of the peripheral circuit devices610may have the cover layer630provided thereon. According to some embodiments, the cover layer630may include a material having a predetermined etch selectivity ratio with the first interlayer insulating layer551. The cover layer630may prevent the active regions613from being excessively recessed when the peripheral contact plugs620are formed.

According to some embodiments illustrated inFIGS. 29A and 29B, the sacrificial layer520and the insulating layer540may have the same shape as that of the example embodiments illustrated inFIGS. 16A and 16B. According to some embodiments illustrated inFIGS. 16A and 16B, the mask pattern PM1for trimming may be formed on the uppermost insulating layer147, but according to the example embodiments illustrated inFIGS. 29A and 29B, a mask layer M3for etching may be formed on the uppermost insulating layer547.

The mask layer M3may have open regions O3. The open regions O3may have the same shape as those of portions from which the uppermost sacrificial layer526and the uppermost insulating layer547are removed. The mask layer M3may also allow a portion of the uppermost insulating layer547to be exposed. In more detail, the mask layer M3may allow the portion of the uppermost insulating layer547to be exposed, and the open regions O3may allow portions of the second insulating layer546to be exposed.

Referring toFIGS. 30A and 30B, an etching process may be performed using the mask layer M3. Trenches h3may allow portions of the second insulating layer546and the second sacrificial layer525to be removed. Meanwhile, an etching process performed in the vicinity of the mask layer M3may allow a stepped structure as illustrated inFIG. 30Bto be formed. After the formation of the stepped structure, the mask layer M3may be removed, a mask pattern that can be trimmed may be formed, and similar processes as described with reference toFIGS. 16A through 19Bmay be performed so that the pad regions as illustrated inFIGS. 31A and 31Bmay be formed.

According to some embodiments illustrated with reference toFIGS. 29A through 31B, the trenches h3may have relatively greater thicknesses than those of the trenches h1and h2according to some embodiments described above. Therefore, as illustrated inFIG. 30B, the vertical insulating layer590may also have a greater thickness than those of the vertical insulating layers190and390according to the example embodiments described above. According to an example embodiment, the vertical insulating layer590may have a thickness allowing two or more sacrificial layers525and526to be penetrated.

According to some embodiments illustrated inFIGS. 29A through 31B, the trenches h3may be separately formed by two processes. In more detail, the sacrificial layer520and the insulating layer540may be stacked on the substrate501, and the structure as illustrated inFIGS. 29A and 29Bmay be formed using an etching process using the mask layer M3for opening regions corresponding to the trenches h3. After the formation of the structure, as illustrated inFIGS. 29A through 30B, the mask layer M3having the open regions O3may be repeatedly formed, and the etching process may be performed. The thicknesses of the trenches h3formed by the two processes as described above may be substantially the same as a sum of thicknesses of two sacrificial layers525and526and two insulating layers546and547together etched in the process of forming the trenches h3.

FIGS. 32 and 33are block diagrams of an electronic device including a memory device according to some embodiments of the present inventive concept, respectively.

Referring toFIG. 32, a storage device1000according to some embodiments may include a controller1010communicating with a host and memories1020-1,1020-2, and1020-3storing data. The respective memories1020-1,1020-2, and1020-3may include the memory devices100,300, and500according to various example embodiments described above.

The host communicating with the controller1010may be various types of electronic devices equipped with the storage device1000, such as a smartphone, a digital camera, a desktop PC, a laptop PC, a portable media player, and the like. The controller1010may receive a data write or read request transmitted from the host to generate a command (CMD) for storing or retrieving data to/from the memories1020-1,1020-2, and1020-3.

As illustrated inFIG. 32, at least one of the memories1020-1,1020-2, and1020-3may be connected to the controller1010in parallel within the storage device1000. By connecting the plurality of memories1020-1,1020-2, and1020-3to the controller1010in parallel, the storage device1000having a large capacity may be implemented, such as a solid state drive (SSD).

Referring toFIG. 33, an electronic device2000according to some embodiments may include a communications unit2010, an input unit2020, an output unit2030, a memory2040, and a processor2050.

The communication unit2010may include a wired/wireless communications module such as a wireless Internet module, a local communications module, a global positioning system (GPS) module, and/or a mobile communications module. The wired/wireless communications module included in the communications unit2010may be connected to an external communications network based on various communications standards to transmit and receive data.

The input unit2020may include a mechanical switch, a touchscreen, a voice recognition module, and the like, as a module provided for a user to control operations of the electronic device2000. In addition, the input unit2020may also include a mouse or a finger mouse device operating based on a trackball or a laser pointer, and may further include various sensor modules which enable a user to input data.

The output unit2030may output information processed by the electronic device2000in an audio and/or video format, and the memory2040may store a program for processing or control of the processor2050, or data. The memory2040may include at least one of the memory devices100,300, and500according to various embodiments described above, and the processor2050may send a command to the memory2040depending on required operations to store data in or retrieve data from the memory2040.

The memory2040may be embedded in the electronic device2000, or may communicate with the processor2050through an additional interface. When the memory2040communicates with the processor2050through the additional interface, the processor2050may store data in or retrieve data from the memory2040through various interface standards such as secure digital (SD), secure digital high capacity (SDHC), secure digital extended capacity (SDXC), micro SD, universal serial bus (USB), etc.

The processor2050may control operations of each component included in the electronic device2000. The processor2050may perform control and processing associated with a voice call, a video call, data communications, and the like, or may conduct control and processing for multimedia reproduction and management. The processor2050may also process an input entered by a user through the input unit2020and output a result thereof through the output unit2030. Furthermore, the processor2050may store or retrieve data required to control operations of the electronic device2000to/from the memory2040as described above.

As set forth above, according to some embodiments of the present inventive concept, a memory device may have a trench opening formed therein before forming a pad region connected to a contact plug, and may measure a location of the pad region based on the trench opening during a process of forming the pad region. Resultantly, a short circuit or the like between gate electrode layers that may occur in a process of forming the contact plug may be solved, thereby providing a memory device having high reliability. The trench opening may be filled with an insulating material when an interlayer insulating layer is formed, thereby remaining in the memory device as a vertical insulating layer.