Circuits with transient isolation operable in a low power state

An integrated circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch. The circuit also includes and a power consumption controller in communication with the core-logic, the latch and the isolation circuit, for controlling the latch to store a state of the core-logic output, and output a corresponding signal. The controller is further operable to signal the isolation circuit to isolate the core-logic output from the latch by providing an output corresponding to predetermined value and transition the core-logic from a high power state and a low power state. This prevents transient signals from propagating to interconnected circuit blocks and external devices.

FIELD OF THE INVENTION

The present invention relates generally to power management in circuits and more particularly to integrated circuits in which idle parts of a circuit maybe shut down and powered back as needed, while active parts remain powered; and any resulting spurious or transient signals are suppressed.

BACKGROUND OF THE INVENTION

Modern circuit designs attempt to reduce power consumption. Power consumption is especially of concern in electronic devices that are intended for mobile use such as handheld devices such as video games, personal digital assistants, global positioning satellite receivers, as well as portable computers and wireless handsets. Since mobile devices typically operate using battery power, it is important to conserve power by limiting its dissipation whenever possible.

Examples of circuits in which power consumption considerations are important include graphics chips used in portable or laptop computers. Clearly, power consumption can be reduced by minimizing the number of components used in a given electronic device. Moreover, parts of a circuit may not be needed by an electronic device even when it is powered on. Therefore, power consumption can further be reduced by shutting down inactive parts, even while other parts are powered.

In graphics chips, for example, separate power supply pins may be available for the functional logic (referred to as core-logic) and the drivers for the input/output (I/O) pads. Therefore the core-logic may be shut down when not in use, while the I/O drivers continue to be powered.

Two types of power consumption called dynamic power consumption and static power consumption are typically considered. Dynamic power consumption results primarily from the switching of logic gates and the attendant charging and discharging of capacitors. In contrast, static power consumption is primarily caused by leakage current.

Although dynamic power consumption has been the focus of power reduction efforts for decades, shrinking die sizes and increasing number of transistors in newer manufacturing technologies, such as 0.1 micron and smaller technologies, have made static power dissipation equally important.

As static power dissipation is caused by leakage current, it cannot be materially reduced by reducing switching. However, shutting down inactive component helps in its reduction.

Unfortunately, shutting down parts of a circuit, and powering them back may cause spurious transient signals (called “glitches”) on electrical interconnections to internal circuit blocks, or interconnected external components.

For example, transient voltage signals may be observed on signal lines interconnected to the I/O pads of an integrated circuit when its core-logic is shut down first and then powered back up. This in turn may interfere with the operation of other interconnected integrated circuits.

Accordingly, there is a need for better circuit designs that reduce static power dissipation while reducing undesirable spurious signals which may affect the performance of interconnected components.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, there is provided an integrated circuit including a core-logic, an isolation circuit, a latch and a controller. The core-logic provides a core-logic output. The isolation circuit is in communication with the core-logic and is operable to selectively provide an output corresponding to one of the core-logic output and a predetermined value. The latch is interconnected to the isolation circuit, and receives the output of the isolation circuit. The power consumption controller is in communication with the core-logic, the latch and the isolation circuit. The controller is operable to control the latch to store a value of the core-logic output and provide a corresponding output, control the isolation circuit to provide an output corresponding to the predetermined value at the output of the isolation circuit, and transition the core-logic from a high power state to a low power state.

In accordance with another aspect of the present invention, there is provided a method of operating an integrated circuit that includes a core-logic providing a digital signal, a latch in communication with the core-logic to store the state or level of the digital signal; and an isolation circuit operable to selectively provide the digital signal to an input of the latch. The method includes signaling the latch to store the state the digital signal, signaling the isolation circuit to provide a predetermined signal to the input of the latch, and removing power supplied to at least a portion of the core-logic, thereby placing the integrated circuit into a lower power state.

In accordance with another aspect of the present invention, there is provided a method of operating an integrated circuit including a core-logic providing a core-logic output to an isolation circuit. The isolation circuit is operable to selectively provide an output corresponding to one of the core-logic output and a predetermined value, to an input of a latch. The input of the latch is interconnected with an output of the isolation circuit. The method includes signaling the latch to store a value of the output of the isolation circuit corresponding to the core-logic output, and provide a corresponding output; signaling the isolation circuit to provide an output corresponding to the predetermined value; and removing power supplied to at least a portion of the core-logic thereby placing the integrated circuit in a low power state.

In accordance with yet another aspect of the present invention, there is provided an integrated circuit including a controller in communication with an isolation circuit and a latch. The isolation circuit includes a first input, a second input and an output for selectively providing an output signal corresponding to an input signal received at the first input or a predetermined signal value, in response to a signal received at the second input. The latch includes a data input interconnected to the output of the isolation circuit for receiving a data signal, a control input for receiving a control signal and an output. The controller is operable to assert the control signal to control the latch to store a value of the data signal, and output a corresponding signal. The controller is also operable to signal the isolation circuit to provide an output signal corresponding to the predetermined signal value.

DETAILED DESCRIPTION

FIG. 1is a schematic diagram of a conventional integrated circuit (IC)100including a core-logic102and input-output (I/O) pads104and I/O drivers118. A power input106supplies power to core-logic102. A separate power supply input114provides power to I/O drivers118. I/O pads104are interconnected to I/O drivers118which further interconnect core-logic102. The core-logic refers to the implementation of the specific logic that carries out all the functional requirements of the design, excluding generic circuitry such as I/O drivers/buffers, and power supply pins. An external device108may be interconnected to some of I/O pads104of circuit100via lines116which may form part of a bus. External device108may be a peripheral device.

A device reset input112accepts a reset signal used to reset circuit100. The device reset signal may be initiated by a host processor. A separate reset input110is used to receive a reset signal to reset core-logic102only, without resetting I/O pads104.

In operation, power supplied to core-logic102through power supply input106may be turned off when core-logic102is idle, while I/O drivers118interconnecting I/O pads104are still powered through a separate power supply input114. However, when core-logic102is powered again, external devices connected to I/O pads104of circuit100, such as device108, may be subject to transient voltages on lines116. Transient voltages are undesirable as they lead to unpredictable behavior in circuits and may potentially cause damage.

AccordinglyFIG. 2is a schematic diagram of an integrated circuit200, exemplary of an embodiment of the present invention. Integrated circuit200includes core-logic202and I/O pads204. Core-logic202may include one or more power-islands206A,206B (individually and collectively power-islands206). Power-islands206are sometimes called voltage-islands. Only two power islands206are illustrated. Of course, integrated circuit200may have many more such islands. Each power-island may consume differing amounts of dynamic and static power. In addition, each power-island may be operated at different power supply input voltage levels. Alternatively, the entirety of core-logic202could be a single power island.

Each power-island206is an individually powered block within core-logic202. Power is supplied to power-islands206A,206B from power source220through power supply inputs254A,254B (individually and collectively inputs254) respectively. In this way, power-islands206may be independently powered up and down, as practicable.

At least some outputs of core-logic202(or alternately at least some outputs of power-islands206A,206B) are interconnected to isolation circuits or isolation cells230A,230B (individually and collectively isolation cells230). The outputs of isolation cells230A,230B interconnect latches218A,218B (individually and collectively latches218) through signal lines238A,238B (individually and collectively signal lines238) respectively. Latches218A,218B interconnect I/O drivers219A,219B (individually and collectively I/O drivers219) through signal lines256A,256B (individually and collectively signal lines256). I/O drivers219interconnect individual I/O pads204, and may be implemented using non-inverting CMOS buffers.

Outputs of core-logic202interconnect one input of an isolation circuit or isolation cell230A,230B through signal lines240A,240B (individually and collectively signal lines240) respectively. Signal line240carries a core-logic output—a digital signal provided by core-logic202. Signal line240may be a data line, or a control line such as for example, an output-enable line or a strength line used to control I/O driver219.

Of course, there need not be a one-to-one correspondence between isolation cells230, latches218, and power-islands206. Instead, each power-island206may have multiple outputs, feeding multiple isolation cells230and latches218.

Isolation-control lines234A,234B (individually and collectively isolation control lines234) interconnect a control block232to an input of isolation cells230A,230B. The output of isolation cell230A is interconnected to a latch218A (through a signal line238A), and may also be connected the other power-islands in core-logic202. Similarly the output of isolation cell230B is interconnected to a latch218B through a signal line238B. Each of isolation cells230A,230B is thus operable to selectively interconnect an output signal from core-logic202, to an input of a corresponding one of latches218A,218B respectively.

A data input of latch218interconnects the output of isolation cell230through signal line238. I/O pads204interconnect an external device208though signal lines216. As will be appreciated, latch218is an asynchronous circuit. For example, when the latch-enable input of a latch218(e.g. a D-latch) is high, then the output of the latch simply follows its data input. However, the output of latch218will not respond to a signal input if its latch-enable input (interconnected to control block232inFIG. 2) is low—it simply stays latched in its last state. In other words, the output of latch218remains unchanged while the level of the signal supplied to its latch-enable input is low.

Controller250, which includes control block232, is a power consumption controller operable to transition core-logic202between at least one higher power state and a lower power state as needed. Controller250may include a processor and may optionally incorporate power source220. Controller250may for example, be a dedicated power controller, or may be a general purpose central processor operating under software control. Controller250or control block232under the control of controller250, may selectively transition any given power-island206from a low power state to a high power state or vice versa. In the depicted embodiment controller250and control block232are formed external to circuit200. Of course, controller250and/or control block232, or portions thereof may be formed as voltage islands on circuit200.

Power may be supplied to power-islands206in core-logic202using power input254A,254B. The power supplied may originate in a controllable power source220. Power source220may include a field-effect-transistor (FET) for shared power input. The FET (not shown) in power source220may be a metal-oxide-semiconductor FET (MOSFET) with low resistance when the transistor is in its on state. If power to input254is not shared, power source220may be a DC-to-DC converter or some other controllable power source under the control of controller250.

Control signal line236interconnects the control input of latches218to core-logic control block232.

Power-island206A may be turned on and off independently from the rest of core-logic202, through its power supply input254A. Similarly, power-island206B may be turned on and off separately from the rest of core-logic202, through its own power supply input254B. Power control switches248A,248B (individually and collectively power control switches248) of power supply220may be used to control power supplied to power-islands206A,206B respectively, by control block232, or controller250. A signal line258may be used to interconnect circuit200to power source220to allow circuit200to control power source220if needed. Alternately, power control switches248may reside inside circuit200rather than power source220.

In one exemplary embodiment, isolation cell230may be an AND-gate implemented using CMOS logic.FIG. 3depicts one exemplary isolation cell implemented as an AND-gate constructed using CMOS transistors302,304,306,308,310,312. NMOS transistors302,304and p-type metal oxide semiconductor (PMOS) transistors306,308form a NAND gate stage, which is followed by an inverter stage formed by PMOS transistor310and n-type metal oxide semiconductor (NMOS) transistor312to realize a CMOS AND-gate. A signal input316may interconnect signal line234(FIG. 2), while a control input318interconnects signal line240(FIG. 2), and output314may interconnect signal line238(FIG. 2).

Isolation cell230is thus produces a predetermined signal value or level (high or low) in response to a control input. However isolation cell230may additionally include built-in state storage elements such as a latch in alternate embodiments. Moreover, in multiple voltage-island circuits (that is, circuits in which individual islands may be operated using different supply voltage levels), isolation cell230can include voltage level-shifters.

A LATCH_ENABLE signal on control signal line236may be transmitted to latch218to signal it to store the value (last known state) of outputs from core-logic202(and hence I/O pads204), prior to transitioning to a low power state. When power-islands206are shut down or powered up, signal levels on signal lines240may be unknown. As noted, this is a potential source of undesirable transient signals observed on I/O pads (or I/O glitches). Thus, as noted below, isolation cell230and latch218may be used to eliminate the propagation of such signals when entering or exiting low power states in circuit200.

In operation, as power is disconnected from at least a portion of core-logic202(e.g. from power-island206A (or206B)), isolation cell230A (or230B) under the control of control block232may isolate potentially indeterminate signals on line240A (or240B) and instead output a known predefined signal level (i.e., high or low). This prevents an undesirable transient voltage signal originating in a power-island from propagating to interconnected external devices or other power-islands (FIG. 2). Thus isolation cell230when signaled by a control signal on line234, receives the output of power-island206(which may be a transient voltage signal) but nonetheless outputs a known predetermined signal level associated with either logic high or low. To achieve this, an isolation control signal is sent to isolation cell230on line234by control block232.

In one exemplary embodiment, control block232may drive the isolation signal on isolation-control line234low, which leads the AND-gate (isolation cell230) to clamp low or to output a signal level corresponding to logic low on line238. Alternately, an OR-gate may be used to clamp high (output a signal level corresponding to logic high on line238). As may be appreciated by a person skilled in the art, other suitable gates may be used to form isolation cell230.

Static power conservation in circuit200may be accomplished by disconnecting power applied to some or all power islands in core-logic202. If no power is supplied to a given power-island, then neither dynamic power nor static power would be consumed inside that power-island. If power is disconnected from all of core-logic202, circuit200is said to be operating in a floating core mode.

During normal (or high power state) operation, the signal on line236may be de-asserted making latch218transparent so that the output of latch218follows its input. However, before turning off power to a voltage island206to transition to a low power state, the last known signal values (or the state) of outbound signals destined for I/O pads204should be latched or buffered.

Latches218interconnecting signal lines238are used for storing the last known signal levels of outbound signals. Accordingly, a control signal on lines236may be asserted to latch each signal on line238on a corresponding latch218, before turning off power to core-logic202. When the signal is asserted on lines236, latches218are no longer transparent and thus retain signal levels on lines238at the time of assertion of the signal. When power to core-logic202is subsequently cut off, I/O pads204maintain their last known values since stored signal levels in latches218are maintained in electrical communication with I/O pads204through I/O drivers219.

Before transitioning circuit200to a low power state, as noted above, controller250may stop all operations including I/O operations so that circuit200is idle. Controller250may then control latch218by asserting a LATCH_ENALBE signal on line236to latch the state (store the value) of an I/O pad interconnected to the output of latch218. State information, such as controller register values and strap information, may be stored in storage outside core-logic202, which may be a volatile memory such as a block of random access memory (RAM) or non-volatile memory such as flash memory. Strap information includes configuration data need by core-logic202before normal operation starts, such as bus mode of any interconnected bus, clock source and the like.

Once core-logic202is idle and any desired control information is stored, controller250though control block232may control isolation cell230by asserting a signal on isolation-control line234so that isolation cell230outputs a known, predetermined signal value. If signal on isolation-control line234is set high and isolation cell230is an AND-gate, then isolation cell230would be transparent; that is, the output of line238is the same as the signal on line240. Conversely if signal on isolation-control line234is set low then the isolation cell230, the output of line238is also low.

After I/O pad values are stored, and isolation cells230have clamped the output signal on lines238, power to core-logic202(i.e., to all of the power islands) may be removed. Thus controller250transitions core-logic202to a low power state by removing power to core-logic202. Power to isolation cell230, latch218and I/O drivers219, continues to be supplied even when core-logic202is disconnected from its power supply.

Circuit200may also be operated in a low power state, by disconnecting power to some power-islands while other power-islands are powered. As noted, a power-island206is an individually powered block within core-logic202with its own power supply input, and may be shut down without causing power interruption to other power-islands. In circuit200each power-island206has its own power input254. Power supplied to power power-islands206A,206B at inputs254A,254B may be controlled by controller250(or control block232) through power control switches248A,248B respectively. Control block232may thus manage power input to individual power-islands206A,206B in core-logic202. In the depicted embodiment, control block232is under the control of controller250although this not required in general.

If power supplied to power-island206A is disconnected, leakage current and thus static power dissipation are eliminated in power-island206A. The rest of core-logic202including power-island206B however, remains powered and may continue to operate. Thus, while one power-island is shutdown, other power-islands and the rest of core-logic202may continue to operate and dissipate some static and dynamic power.

FIG. 4is a flowchart depicting steps S400taken by controller250to transition circuit200from a high power state to a low power state. As depicted controller250signals latch218A to store the logical state (1 or 0) of a signal on line238A at its input (S402). After some time (S404) controller250signals isolation cell230A to isolate the output of power-island206A from the input of latch218(S406). After another delay (S408) controller250disconnects power supplied to power-island230A by signaling power source220(S410).

Conversely,FIG. 5is a flowchart depicting steps S500taken by controller250to transition power-island206A from a low power state, back to a high power state. As depicted controller250, through power source220, connects power to power-island230A (S502) thereby transitioning core-logic202from a low power state to a high power state. After some delay (S504), controller250signals (controls) isolation circuit230A to output the output of the interconnected power-island206A (S506). After another delay (S508), and an optional initialization step for performing configurations of power-island206A (S509), controller250signals (controls) latch218A (through signal line234A) to output the signal value on line240A (i.e., the output of power-island206A) to complete the transition to high power state operation. Any remaining initializations that need not be performed prior to releasing latch218A may then be undertaken (S512).

FIG. 6depicts a timing diagram illustrating signals in circuit200as it is transitioned to a low power state having at least one power island206A disconnected, and then back to a higher power state, with that power-island reconnected. As can be appreciated, in a low power state, circuit200will have at least one power-island (e.g. power-island206A) and possibly all power-islands disconnected from a corresponding power source. Time instants t0, t1, t2, t3, t4, t5and t6will be used to describe the state or value of signals in circuit200. The time interval between time instants t0and t3corresponds to steps S400ofFIG. 4; while the time interval between time instants t4and t6corresponds to steps S500ofFIG. 5. Of course, each power island206may be individually disconnected as described, at different time instants, for which corresponding signals like those depicted at time instants t0, t1, t2, t3, t4and t5may be identified. Alternatively, multiple power islands or the entirety of core-logic202may be transitioned to a low power state at once.

At time t0, circuit200is still in its higher power state (normal operation). At time t1, a LATCH_ENABLE control signal is sent to latch218A (corresponding to S402inFIG. 4). At time t1, the output of power-island206A through signal line240A, isolation cell230A, and signal line238A is latched or stored, and the stored signal level is reflected at the output of latch218A.

At t2, an ISOLATION signal is transmitted from control block232to isolation cell230A though control line234A (corresponding to S406inFIG. 4). As noted above, isolation cell230A may be an AND-gate and thus ISOLATION signal may be set low to force the output of the gate to be low at line238A. Alternately, an OR-gate may be used to force the output of isolation cell230A to a predetermined signal level of high.

The signal level on line238A which interconnects I/O pads204, and may also interconnect the rest of core-logic202, would thus be in a known state as determined by the ISOLATION signal at t2.

At time t3, power to power-island206A is disconnected (corresponding to S410inFIG. 4). This does not affect interconnected I/O pads204since latch218A is still powered and the output of latch218A is maintained in a known state.

For the rest of core-logic202interconnected to an output of power-island206A (such as power-island206B), isolation cell230A provides a known signal level at its output on signal line238A. Thus, transients may be avoided inside circuit200. Latch218A prevents glitches that may affect external device208. Power to power-island206A may be restored at time t4(corresponding to S502inFIG. 5).

Now, recall that isolation cell230may be formed as an AND-gate formed from CMOS transistors as depicted inFIG. 3. Input316of the AND-gate interconnects transistors306,304. When ISOLATION signal on signal line234is asserted (i.e., driven low for an AND-gate), the output of isolation cell230is clamped low and any leakage path is cut-off even in the presence of a floating input on signal line240. After power-island206is powered, controller250may write control information and perform other configurations in power-island206(from about t4to t5inFIG. 6) to initialize outputs from power-island206to a desired state. After the outputs have been initialized to their proper states, ISOLATION signal is de-asserted at t5, which is then followed by transmitting a LATCH_ENABLE signal to make latch218transparent.

A floating input signal (i.e., indeterminate signal level that is neither definitely high nor low) to latch218A may also lead to increased static power consumption in circuit200. Latch218A contains complimentary metal oxide semiconductor inverters, each of which includes a PMOS transistor connected in series with an NMOS transistor, with a common input to their gate terminals. A floating input to such CMOS inverter may cause both the NMOS and PMOS transistors (inside latch218A) to simultaneously turn on thereby dissipating more power. Advantageously, isolation cell230A ensures that a definite signal level (high or low) is supplied at the input of latch218A (until the output signal on line240A is stable) thereby preventing a floating input from propagating to latch218A.

Referring again toFIG. 6, after some delay, the ISOLATION signal may be de-asserted at time t5(corresponding to S506inFIG. 5), to allow outputs of power-island206A to determine the output of isolation cell230A. The interval from t4to t5may range from nanoseconds to hundreds of microseconds. As can be appreciated, when one input of an AND-gate (isolation cell230) is set to high, the output of the gate simply reflects the signal level at the second input of the gate. Power-island206A, thus now effectively drives the output of isolation cell230A.

At t6, the LATCH_ENABLE control signal to latch218A may be de-asserted through signal line236A, by control block232(corresponding to S510inFIG. 5) to allow power-island206A to ultimately drive signals to interconnected I/O pads204and thus to interconnected external devices208. This restores the normal mode (high power state) of operation. The time interval from t5to t6may range from a few clock cycles to hundreds of microseconds depending on how long it takes to restore the state of the power-island outputs, which further depends on factors such as whether state information is stored in volatile or non-volatile memory.

Power-island206B (and other power islands) may remain powered and fully operational during the period from t0to t6.

In an alternate embodiment control signal lines236A,236B may interconnect latch218A,218B directly to controller250.

In the exemplary embodiment ofFIG. 2, only two power-islands206A,206B are shown. Of course, in other embodiments, many more power-islands may reside inside core-logic202.

InFIG. 2, isolation cell230in the form of an AND-gate, and latch218are shown at the gate level. However, in alternate embodiments, isolation cell230(further depicted inFIG. 3) and latch218may be combined into a single cell suitable for use in integrated circuits called an isolation latch. Transistor level implementations of isolation cell230(FIG. 3) and latch218can be easily interconnected to provide a cell that effectively functions as an isolation latch (that is a latch with an isolation circuit built in at its input). The isolation cell contained inside an isolation latch should still have its own control input separate from the control input for the standard latch (inside the isolation cell). Thus, the operation of the isolation latch would be the same as in the case of the embodiment depicted inFIG. 2where isolation cell230is a separate from the standard latch218.

As already noted, isolation cell230may be formed from logic gate structures other than an AND-gate. For example, OR gate structures may be used to clamp the output of an isolation cell to high.

In alternate embodiments, level-shifters may be incorporated into isolation cells. Isolation cells incorporating level-shifters are particularly useful in in multiple voltage-island circuits in which individual islands may be operated using different supply voltage levels.

Circuits exemplary of embodiments of the present invention may be used in graphics chips. For example, logic associated with a 3D engine in a graphics chip may reside in its own power-island. When applications that do not require 3D rendering are used, a host processor may shut down the power-island associated with the 3D engine to conserve power.

Exemplary embodiments of the present invention may also be used in handheld computing devices containing a display peripheral referred to as a smart display peripheral. A smart display peripheral often includes a frame buffer together with a liquid-crystal-display (LCD) array. The smart display peripheral relies on a graphics chip during animation but refreshes itself from its local memory in power saving modes. Thus the graphics chip can shut down its engine and display interface, while the smart display peripheral continues refreshing uninterrupted from its built-in frame buffer.

Other embodiments exemplary of the present invention may also be used circuits employing dynamic RAM (DRAM) controller and associated blocks of DRAM. When such a circuit enters a low power state, the DRAM controller interconnected to DRAM memory blocks may be powered down. After the controller is powered down, its interface signals interconnecting the DRAM blocks may be maintained in a known state using embodiments of the present invention, while the DRAM memory blocks continue to operate in a low power, self-refresh mode.