Synchronization of serial data signals

Various techniques are provided for synchronizing serial data signals received by electronic systems or devices such as programmable logic devices (PLDs). In one example, a method of synchronizing data includes receiving a serial data signal at a device. The serial data signal operates independently of the device. The method also includes oversampling the serial data signal to provide a plurality of samples distributed over bit periods of the serial data signal. The method further includes filtering the samples to correct errors in the samples. In addition, the method includes extracting a plurality of data bit values from the samples under the control of a clock signal associated with the device without adjusting a frequency of the clock signal. Each data bit value is associated with one of the bit periods of the serial data signal.

TECHNICAL FIELD

The present invention relates generally to data synchronization and, more particularly, to the synchronization of serial data signals received by electronic systems or devices such as programmable logic devices (PLDs).

BACKGROUND

In various types of electronic devices, synchronous serial data signals may be provided without a separate clock signal. In such implementations, a device receiving a serial data signal may be required to perform synchronization using only the serial data signal without the aid of a separate dedicated clock signal.

For example, in one approach (e.g., in conventional analog serializer/deserializer (SERDES) applications), a receiving device may adjust the speed of its local clock to properly synchronize with a serial data signal. However, such an approach may be impractical to implement in certain types of devices such as programmable logic devices (PLDs) including field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs).

For PLDs, an alternate approach may be used in which data provided by the serial data signal is synchronized with an existing stable local clock of a PLD. For example, a serial data signal received by one input (e.g., a low-voltage differential signaling input) of a PLD may be oversampled (e.g., four times oversampled) by the FPGA, and the data encoded in the serial data signal may be extracted from the samples. Unfortunately, this approach can be problematic when high speed serial data signals are received. For example, at serial data speeds in excess of approximately 200 Mbps, system skew and jitter may exceed approximately ¼ of a clock cycle, thus making it extremely difficult to extract the data from the serial data signal.

Accordingly, there is a need for an improved approach to the synchronization of serial data signals. In particular, there is a need for such an approach that addresses the concerns associated with the synchronization of such serial data signals with PLDs.

SUMMARY

In accordance with one embodiment of the present invention, a method of synchronizing data includes receiving a serial data signal at a device, wherein the serial data signal operates independently of the device; oversampling the serial data signal to provide a plurality of samples distributed over bit periods of the serial data signal; filtering the samples to correct errors in the samples; and extracting a plurality of data bit values from the samples under the control of a clock signal associated with the device without adjusting a frequency of the clock signal, wherein each data bit value is associated with one of the bit periods of the serial data signal.

In accordance with another embodiment of the present invention, a device includes sampling blocks adapted to oversample a serial data signal received by the device to provide a plurality of samples distributed over bit periods of the serial data signal, wherein the serial data signal operates independently of the device; a sample error filter adapted to filter the samples to correct errors in the samples; and a data extraction block adapted to extract a plurality of data bit values from the samples under the control of a clock signal associated with the device without adjusting a frequency of the clock signal, wherein each data bit value is associated with one of the bit periods of the serial data signal.

In accordance with another embodiment of the present invention, a device includes means for receiving a serial data signal, wherein the serial data signal operates independently of the device; means for oversampling the serial data signal to provide a plurality of samples distributed over bit periods of the serial data signal; means for filtering the samples to correct errors in the samples; and means for extracting a plurality of data bit values from the samples under the control of a clock signal associated with the device without adjusting a frequency of the clock signal, wherein each data bit value is associated with one of the bit periods of the serial data signal.

In accordance with another embodiment of the present invention, a method of extracting data bit values from a serial data signal includes sampling the serial data signal to provide a set of samples; storing the sample set; simultaneously comparing overlapping subsets of the sample set against a plurality of given error patterns to detect whether a sample subset matches an error pattern; changing a sample subset that matches an error pattern to a corrected pattern associated with the error pattern; and extracting a data bit value from samples of the serial data signal that include the corrected pattern.

In accordance with another embodiment of the present invention, a method of extracting data bit values from a serial data signal includes sampling the serial data signal with multiple phases of a clock signal to provide a set of samples; storing the set of samples; applying a plurality of masks to the samples to identify a plurality of bit positions within the set of samples; and extracting data bit values from the bit positions identified by the masks.

DETAILED DESCRIPTION

Various techniques further described herein may be used to perform clock and data recovery for a serial data signal received by an electronic system or an electronic device such as a programmable logic device (PLD) or other integrated circuit. In one embodiment, the PLD oversamples a serial data signal that operates independently of the PLD. The PLD filters the samples to correct errors in the samples. Data bit values are extracted from the samples under the control of a clock signal associated with the PLD without adjusting a frequency of the clock signal. Advantageously, the extracted data bit values may be used by the PLD as desired under the control of the clock signal associated with the PLD without requiring adjustment of the serial data signal itself.

FIG. 1illustrates a block diagram of a programmable logic device (PLD)100in accordance with an embodiment of the invention. PLD100(e.g., a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a field programmable system on a chip (FPSC), or other type of programmable device) generally includes input/output (I/O) blocks102and logic blocks104(e.g., also referred to as programmable logic blocks (PLBs), programmable functional units (PFUs), or programmable logic cells (PLCs)). I/O blocks102provide I/O functionality (e.g., to support one or more I/O and/or memory interface standards) for PLD100, while programmable logic blocks104provide logic functionality (e.g., LUT-based logic or logic gate array-based logic) for PLD100.

PLD100may also include blocks of memory106(e.g., blocks of EEPROM, block SRAM, and/or flash memory), clock-related circuitry108(e.g., PLL and/or DLL circuits), configuration logic110(e.g., for startup, decryption, encryption, multiple-boot support (e.g., dual boot support), and/or error detection), a configuration port112, configuration memory114, special function blocks116(e.g., digital signal processing (DSP) blocks or other forms of multiply and accumulate circuit functionality), and/or routing resources118. In general, the various elements of PLD100may be used to perform their intended functions for the desired application, as would be understood by one skilled in the art.

For example, configuration port112may be used for programming PLD100, such as memory106and/or configuration memory114or transferring information (e.g., various types of data and/or control signals) to/from PLD100as would be understood by one skilled in the art. For example, configuration port112may include a first programming port (which may represent a central processing unit (CPU) port, a peripheral data port, a serial peripheral interface, and/or a sysCONFIG programming port) and/or a second programming port such as a joint test action group (JTAG) port (e.g., by employing standards such as Institute of Electrical and Electronics Engineers (IEEE) 1149.1 or 1532 standards). Configuration port112typically, for example, may be included to receive configuration data and commands to support serial or parallel device configuration and information transfer.

It should be understood that the number and placement of the various elements, such as I/O blocks102, logic blocks104, memory106, clock-related circuitry108, configuration logic110, configuration port112, configuration memory114, special function blocks116, and routing resources118, are not limiting and may depend upon the desired application. For example, special function blocks116are optional and various other elements may not be required for a desired application or design specification (e.g., for the type of programmable device selected).

Furthermore, it should be understood that the elements are illustrated in block form for clarity and that certain elements, such as for example configuration memory114or routing resources118, would typically be distributed throughout PLD100, such as in and between logic blocks104, to perform their conventional functions (e.g., storing configuration data that configures PLD100or providing interconnect structure within PLD100, respectively). It should also be understood that the various embodiments of the present invention as disclosed herein are not limited to programmable logic devices, such as PLD100, and may be applied to various other types of programmable devices, as would be understood by one skilled in the art.

FIG. 2illustrates a PLD200and a serial data signal SDS in accordance with an embodiment of the invention. In one embodiment, PLD200may be implemented by PLD100ofFIG. 1, and signal SDS may be implemented as a low voltage differential signaling (LVDS) signal with a data rate in excess of approximately 200 Mbps (e.g., approximately 320 Mbps). Signal SDS is initially received by a splitter block250which provides two copies of signal SDS to PLD200. In one embodiment, splitter block250may be external to PLD200and implemented by a MAX9174 LVDS-to-LVDS splitter available from Maxim Integrated Products of Sunnyvale, Calif.

As shown inFIG. 2, PLD200has been configured to provide sampling blocks210and220, and a clock and data recovery (CDR) block230. In this regard, it will be appreciated that sampling blocks210and220, and CDR block230may be implemented by logic blocks (e.g., logic blocks104) configured by appropriate configuration data residing in configuration memory (e.g., configuration memory114).

Sampling blocks210and220include double data rate (DDR) blocks215and225, respectively, which may be used to sample signal SDS in response to clock signals ECLK A, ECLK B, SCLK A, and SCLK B which may be implemented in the manner further illustrated inFIG. 2. In one embodiment, PLD200may be configured to implement each of DDR blocks215and225in accordance with an IDDRX2B software primitive available from Lattice Semiconductor Corporation of Hillsboro, Oreg.

DDR block215provides four samples A distributed over two bit periods of signal SDS (e.g., samples A are taken at approximately 180 degree intervals of signal SDS). DDR block225provides an additional four samples B distributed over the same two bit periods of signal SDS (e.g., samples B are taken at approximately 180 degree intervals of signal SDS, but are shifted approximately 90 degrees relative to samples A). Accordingly, samples A and B collectively provide 8 samples distributed at approximately 90 degree intervals over two bit periods of signal SDS. Samples A and B are provided to CDR block230for further processing as described herein.

FIG. 3Aillustrates a CDR block300and DDR blocks315and325of PLD100or200in accordance with an embodiment of the invention. In one embodiment, CDR block300may be used to implement CDR block230ofFIG. 2described above. CDR block300includes sample reordering logic310, a sample error filter320, and a data extraction block330.

In one embodiment, a device (e.g., PLD100, PLD200, or another device) may be implemented with means such as I/O blocks102for receiving a serial data signal, wherein the serial data signal operates independently of the device. The device may also be implemented with means such as DDR blocks315and325for oversampling the serial data signal to provide a plurality of samples distributed over bit periods of the serial data signal. The device may further be implemented with means such as sample error filter320for filtering the samples to correct errors in the samples. In addition, the device may be implemented with means such as data extraction block330for extracting a plurality of data bit values from the samples under the control of a clock signal associated with the device without adjusting a frequency of the clock signal, wherein each data bit value is associated with one of the bit periods of the serial data signal.

FIG. 3Billustrates a process for performing clock and data recovery using CDR block300and DDR blocks315and325in accordance with an embodiment of the invention. In step340, each of DDR blocks315and325(e.g., which may be implemented by DDR blocks215and225described above) receive copies of signal SDS (e.g., provided by splitter block250ofFIG. 2). In step350, DDR blocks315and325oversample their respective copies of signal SDS to provide samples A and samples B, respectively, as previously discussed.

In step360, sample reordering logic310reorders samples A and samples B received from DDR blocks315and325, respectively, to provide samples C. In this regard,FIG. 4illustrates a reordering of samples A and samples B performed by sample reordering logic310during step360in accordance with an embodiment of the invention. As shown inFIG. 4, sample reordering logic310reorders samples A and samples B to provide samples C in a sequential order. As a result, in one embodiment, samples C correspond to 8 sequential samples of signal SDS distributed at approximately 90 degree intervals over two bit periods.

Referring again toFIG. 3B, in step370, sample error filter320receives samples C from sample reordering logic310and operates on samples C to identify and correct possible errors in samples C to provide corrected samples G to data extraction block330. In step380, data extraction block330extracts data bit values from samples G to provide data bit values CDR Out and validity bit values CDR Valid.

FIG. 5Aillustrates an implementation of a sample error filter500in accordance with an embodiment of the invention. In one embodiment, sample error filter500may be used to implement sample error filter320described above. Sample error filter500includes a 13-bit shift register510, a 14-bit shift register520, and a plurality of masks A, B, C, and D which may be applied to samples residing in shift registers510and520. In one embodiment, each of masks A, B, C, and D is implemented by a corresponding logic table to implement the filtering further described herein.

In one embodiment, sample error filter500identifies and corrects short duration “spikes” in the values of samples C which correspond to time periods that are significantly shorter than bit periods of signal SDS and therefore are not attributable to actual changes in data bit values of signal SDS.

As one example, two 1-bit spikes (e.g., 01) in samples “1101000” may be inverted to provide samples “1110000.” As another example, a 1-bit spike (e.g., 0) in samples “1110111” may be inverted to provide samples “1111111.” As yet another example, a 2-bit spike (e.g., 00) in samples “111001111” may be stretched to three bits to provide samples “111000111.” As a further example, a 1-bit spike (e.g., 1) followed by a 2-bit spike (e.g., 00) in samples “1110100111” may be corrected to provide samples “1110000111.”

Fluctuations in the values of samples C which last for only one or two samples may be attributed to, for example, sampling errors, jitter, noise, data skew, or other types of errors. By identifying and correcting such errors, a PLD that receives signal SDS may avoid inadvertently extracting erroneous data bit values caused by spikes in samples C and thus improve the accuracy at which signal SDS is extracted by the PLD.

The operation of sample error filter500can be further understood fromFIG. 5Bwhich illustrates a process for performing sample error filtering using sample error filter500in accordance with an embodiment of the invention. In step530, eight bits of samples C received from sample reordering logic310are shifted into 13-bit shift register510which stores resident samples D. In step540, sample error filter500applies masks A, B, C, and D to associated subsets of samples D stored by shift register510to detect possible errors in samples D.

In this regard,FIG. 6illustrates the application of masks A, B, C, and D by sample error filter500to samples D of shift register510during step540in accordance with an embodiment of the invention. As shown inFIG. 6, masks A, B, C, and D are applied in parallel in a single clock cycle to four corresponding subsets (e.g., 7-bit overlapping subsets) of samples D stored by shift register510. Using masks A, B, C, and D, sample error filter500identifies whether bit values associated with any two samples of each mask should be corrected. Following the detection of errors in step540, sample error filter500corrects the detected errors in step550.

The following Table 1 identifies various 7-bit error patterns that may be detected by masks A, B, C, and D as residing in resident samples D of shift register510in step540, as well as various 7-bit corrected patterns that may be provided by sample error filter500to correct the detected error patterns in step550.

As shown in Table 1 and illustrated inFIG. 6, corrections if needed are made to the third and/or fourth most significant bits of the detected error patterns (e.g., the third and/or fourth bits counting from the leftmost bit are inverted in the corrected patterns). Because masks A, B, C, and D are applied simultaneously in parallel to subsets of the samples stored by shift register510, up to eight bits of samples D may be simultaneously corrected during one clock cycle.

Upon inspection of Table 1, it will be appreciated that, in one embodiment, sample error filter500does not pass through sample spikes that are shorter than three samples. In this embodiment, 1-bit spikes are determined to be external interference thus not actual data bit values to be detected. Also in this embodiment, 2-bit spikes are stretched to three samples to address possible corruption of either edge of a sampled data bit value.

During step550, sample error filter500may invert appropriate bit values of samples D in shift register510to replace the detected error patterns found in samples D with the corrected patterns identified in Table 1. In step560, the corrected patterns are shifted from shift register510to shift register520in 8-bit groups as samples E.

In step570, sample error filter500applies masks A, B, C, and D to 7-bit overlapping subsets of resident samples F in 14-bit shift register520as similarly described above with regard to samples D and shift register510in step540. In step580, sample error filter500corrects the detected errors in samples F in shift register520as similarly described above with regard to samples D and shift register510in step550. In step590, the corrected patterns are shifted from shift register520to data extraction block330in eight bit groups as samples G.

Advantageously, by using the two filtering stages provided by shift registers510and520, errors occurring across mask boundaries (e.g., errors which would not necessarily be detected by considering only samples D in shift register510) can also be detected and corrected. In this regard, as shown inFIG. 5A, samples E provided to shift register520include overlapping samples that are present in both samples D and samples F. By applying masks A, B, C, and D to these overlapping samples (e.g., as part of samples F), errors occurring at the boundaries of masks A, B, C, and D can be detected and corrected.

FIG. 7illustrates an implementation of a data extraction block700in accordance with an embodiment of the invention. In one embodiment, data extraction block700may be used to implement data extraction block330described above. Data extraction block700includes a pipeline of 16-bit registers710,720,730, and740.

In one embodiment, register710is a 16-bit shift register that receives 8 samples per clock cycle (e.g., samples G) from a sample error filter, such as sample error filter320. During each clock cycle, new sets of 8 samples are shifted into the 8 leftmost bit positions of register710, while the previous samples residing in the 8 leftmost bit positions are shifted into the rightmost bit positions of register710. Thus, the leftmost 8 samples held by register710(e.g., bit positions8to15) include the most recent set of samples G received by data extraction block700, while the rightmost 8 samples held by register710(e.g., bit positions0to7) include the set of samples G received by data extraction block700during the previous clock cycle.

The 8 samples G received by register710correspond to corrected versions of samples C previously described herein. Accordingly, it will be appreciated that the 8 samples G are distributed at approximately 90 degree intervals over two bit periods of signal SDS. The 16 samples maintained in register710correspond to two sets of samples G sequentially received by data extraction block700. Thus, the 16 samples maintained in register710correspond to 16 samples distributed over 4 bit periods of signal SDS (e.g., 4 samples per bit period).

During each clock cycle, all 16 samples of register710are passed to register720. Registers720and730similarly pass their associated 16 samples down the pipeline during each clock cycle. Because only 8 new samples G are shifted into the pipeline during each clock cycle, there will be overlap between the samples shared by the various registers710,720,730, and740. In particular, the eight leftmost samples of registers720,730, and740will correspond to the eight rightmost samples of registers710,720, and730, respectively. Thus, although each of registers710,720,730, and740will hold 16 samples distributed over 4 bit periods of signal SDS, the two bit periods represented by the leftmost 8 bits of registers710,720,730, and740during a given clock cycle will be represented by the rightmost 8 bits in registers710,720,730, and740during the next clock cycle.

Data extraction block700also includes a plurality of 5-bit masks E, F, and G which may be applied to subsets of samples residing in registers710,720, and730. In one embodiment, each of masks E, F, and G is implemented by a corresponding logic table to identify data bit values to be extracted from corresponding subsets of samples to which the masks are applied. The positions of masks E, F, and G may be adjusted left and right in registers710,720, and730, respectively.

FIG. 8illustrates examples of different samples in mask E in accordance with an embodiment of the invention. As shown inFIG. 8, the 5 samples in mask E correspond to positions0to4(e.g., clock phase positions) in the order the samples are received by data extraction block700. In this regard, bit position2corresponds to the centermost sample of mask E.

Based on the different combinations of samples in mask E, data extraction block700may selectively adjust the position of mask E within register710. For example, the following Table 2 identifies various actions that may be taken by data extraction block700in response to different combinations of samples in mask E that are illustrated inFIG. 8.

TABLE 2SamplesDetected Condition Basedin MaskCaseon Contents of MaskAction Taken000001Input data stream isMaintain current maskconstant and stableposition to keepcentermost bit positionin middle of samples ofsame sample value000112Edge detected and theSlide mask 1 position toremains of the previousthe left to movebit are seen at the twocentermost bit positionoldest samples of theaway from edgemask110003Edge detected and theSlide mask 1 position tofirst samples of the newthe right to movebit are seen at the twocentermost bit positionyoungest samples of theaway from edgemask011104Short data pulse of onlyMaintain the current3 samples detected;mask position to keeppredict that thecentermost bit positionposition to the left ofin middle of samples ofcentermost position maysame sample valuebe one sample positionearly and that thesamples of the next bitvalue may only include 3samples111105Stable data after anMaintain the currentedgemask position to keepcentermost bit positionin middle of samples ofsame sample value011116Stable data followed bySlide mask 1 position toan edgethe right to movecentermost bit positionfurther away from theincoming edge

As identified in Table 2, data extraction block700may selectively adjust the position of mask E within register710to the left, to the right, or maintain the current position of mask E. In one embodiment, data extraction block700may perform the same actions identified in Table 2 if the combinations of samples are inverted. For example, if mask E detects samples “11100” then it may perform the same action as identified in Table 2 above for samples “00011.” For all other combinations of samples, data extraction block700may maintain the current mask position.

Referring again toFIG. 7, the position of mask F within register720may be determined based on the position of mask E within register710. In one embodiment, mask F may be positioned four bits to the left of the position of mask E as shown inFIG. 7. Accordingly, as mask E is moved to the left or right within register710, mask F will be moved in a corresponding fashion within register720.

The position of mask G within register730may be determined based on the position of mask F within register720. In one embodiment, mask G may be positioned four bits to the left of the position of mask F as shown inFIG. 7. Accordingly, as mask F is moved to the left or right within register720, mask G will be moved in a corresponding fashion within register730.

As also shown inFIG. 7, data extraction block700provides data bit values CDR Out and validity bit values CDR Valid. Data bit values CDR Out are the bit values (e.g., 0 or 1) extracted by data extraction block. In particular, data bit values CDR Out correspond to bit values maintained in bit positions an, bn, and cnof register740. These bit positions are determined by masks E, F, and G, respectively, as further described herein. Data bit values CDR Out are passed to other portions of PLD100/200or another appropriate device to represent the data encoded in signal SDS.

FIG. 9illustrates a process for performing data extraction using data extraction block700in accordance with an embodiment of the invention. In step910, during a first clock cycle (e.g., during a clock cycle of clock signal SCLK A), samples G from error filter320are shifted into register710. The leftmost 8 samples held by register710include samples G shifted in during step910, while the rightmost 8 samples held by register710include the set of samples G received by data extraction block700during the previous clock cycle.

In step915, data extraction block700applies mask E to a subset of samples in register710. As previously discussed, the position of mask E may be adjusted left and right in register710. In this regard, the initial position of mask E during step915may be determined based on a default value (for example, positioned as shown inFIG. 7) or a position determined in a previous iteration of step925which is further described herein.

Based on the application of mask E, data extraction block700identifies a bit position anwithin mask E corresponding to a data bit value to be extracted from the samples in mask E (step920). For example, in one embodiment, the centermost bit position of mask E is identified. In another embodiment, the bit position is selected from a range of the three centermost bit positions of mask E. For example, the bit position may be selected based on a data edge transition (e.g., a transition between data bit values) detected by mask E.

In step925, based on the application of mask E, data extraction block700identifies the position of mask E to be used during the next clock cycle. For example, in one embodiment, the next position of mask E may be determined as previously discussed with regard toFIG. 8and Table 2.

In another embodiment, if mask E is currently positioned at the extreme right side of register710(e.g., centered at bit position2of register710), then the next position of mask E determined in step925may be shifted four samples to the left (e.g., centered at bit position6of register710). This approach prevents mask E from being shifted in a manner that extends mask E beyond the rightmost bound of register710. As further described herein, mask G may be used in this case to identify a bit value which would otherwise be lost due to the four sample shift of mask E.

In another embodiment, if mask E is positioned at bit position8of register710, then the next position of mask E determined in step925may be shifted four samples to the right to bit position4of register710. This approach prevents mask E from being shifted in a manner that causes mask F to extend beyond the leftmost bound of register720(e.g., in cases where the position of mask F is shifted four bits to the left of mask E). As further described herein, mask F may be unused in this case to prevent the same bit value from being identified by both masks E and F due to the four sample shift of mask E.

During the next clock cycle, in step930, data extraction block700passes the samples of register710on to register720. In step935, data extraction block700applies mask F to a subset of samples in register720. In one embodiment, the position of mask F within register720may be determined based on the position of mask E within register710as previously discussed.

In step940, data extraction block700identifies a bit position bnwithin mask F corresponding to a data bit value to be extracted from the samples in mask F based on the application of mask F. For example, in one embodiment, the centermost bit position of mask F is identified. In another embodiment, the bit position is selected from a range of the three centermost bit positions of mask F. For example, the bit position may be selected based on a data edge transition (e.g., a transition between data bit values) detected by mask F.

During the next clock cycle, in step945, data extraction block700passes the samples of register720on to register730. In step950, data extraction block700applies mask G to a subset of samples in register730. As previously discussed, the position of mask G within register720may be determined based on the position of mask F within register720.

In step955, data extraction block700identifies a bit position cnwithin mask G corresponding to a data bit value to be extracted from the samples in mask G based on the application of mask G. For example, in one embodiment, the centermost bit position of mask G is identified. In another embodiment, the bit position is selected from a range of the three centermost bit positions of mask G. For example, the bit position may be selected based on a data edge transition (e.g., a transition between data bit values) detected by mask G.

During the next clock cycle, in step960, data extraction block700passes the samples of register730on to register740. In step965, data extraction block700provides data bit values CDR Out and validity bit values CDR Valid.

As previously described, data bit values CDR Out are the bit values of the samples in register740corresponding to selected bit positions an, bn, and cndetermined by masks E, F, and G, respectively. As also previously described, validity bit values CDR Valid identify whether corresponding data bit values CDR Out should be used to represent the data encoded in signal SDS.

The 16 samples maintained in register740correspond to two sets of samples G sequentially received by data extraction block700(e.g., passed down from register710through the pipeline ofFIG. 7). Thus, the 16 samples maintained in register710correspond to 16 samples distributed over 4 bit periods of signal SDS (e.g., 4 samples per bit period). Also, because samples G are shifted in to data extraction block700in groups of 8 during each clock cycle, the 8 leftmost samples of register740during a given clock cycle will become the 8 rightmost samples of register740during the next clock cycle.

Normally during step965, masks E and F will be used to identify bit values, but mask G will be unused (e.g., validity bit values CDR Valid [a] and [b] will be set, and [c] will not be set). In this case, masks E and F may be used to select two data bit values CDR Out [an] and [bn] from register740during a given clock cycle. During the next clock cycle, masks E and F may be used to select two additional data bit values CDR Out [an] and [bn] from register740.

For example, if masks E and F are both positioned to select data bit values from the rightmost 8 samples of register740(e.g., assuming that mask F is positioned four bits to the left of mask E), then a bit value from each of two bit periods represented by register740may be selected during a first clock cycle. As discussed, the 8 leftmost samples of register740become the 8 rightmost samples of register740during the next clock cycle. Thus, by continuing to apply masks E and F to the rightmost 8 samples of register740during the next clock cycle, a bit value from each of two additional bit periods represented by register740may be selected during the next clock cycle. Thus, a bit value for each of the four bit periods of signal SDS represented by the samples of register740may be extracted using only masks E and F during normal operation.

It will be appreciated that as the positions masks E and F change, a bit value for each of the four bit periods of signal SDS represented by the samples of register740can still be extracted using only masks E and F over two clock cycles. This is due to the shifting of samples G in sets of 8 samples which causes overlap between the samples stored by register740in successive clock cycles. This is also due to the four bit separation between masks E and F which permits bit values of two clock periods of signal SDS to be determined within each set of 8 samples.

In another embodiment, mask G is used during step965. For example, as previously discussed, if mask E is currently positioned at the extreme right side of register710(e.g., centered at bit position2of register710), then the next position of mask E determined in step925may be shifted four samples to the left (e.g., centered at bit position6of register710) to prevent mask E from being shifted in a manner that extends mask E beyond the rightmost bound of register710. In this case, mask G is used to identify the bit value of bit position10which would otherwise be lost due to the four sample shift of mask E. Accordingly, in this case, validity bit value CDR Valid [c] will be set and data bit value CDR Out [cn] will be extracted during step965.

In another embodiment, mask E is not used during step965. For example, as also previously discussed, if mask E is positioned at bit position8of register710, then the next position of mask E determined in step925may be shifted four samples to the right to bit position4of register710to prevent mask E from being shifted in a manner that causes mask F to extend beyond the leftmost bound of register720. In this case, mask F is disabled to prevent the same bit value from being identified by both masks E and F due to the four sample shift of mask E. As a result, the bit value which would have been identified by mask F will instead be identified by the newly shifted position of mask E. Accordingly, in this case, validity bit value CDR Valid [b] will not be set and data bit value CDR Out [bn] will not be extracted during step965.

Any of data bit values CDR Out which are valid (e.g., as indicated by validity bit values CDR Valid) may be used by PLD100/200or other appropriate devices under the control of a local clock signal (e.g., clock signal SCLK A) without adjusting the frequency of the local clock signal. PLD100/200or other appropriate devices may perform further processing as desired using data bit values CDR Out to represent the data bit values encoded in signal SDS.

Embodiments described above illustrate but do not limit the invention, which can be implemented using a variety of devices including general logic devices, standard cell and structured application-specific integrated circuits (ASICs), and programmable devices such as described above. It should also be understood that numerous modifications and variations are possible in accordance with the principles of the present invention. Accordingly, the scope of the invention is defined only by the following claims.