Hybrid gate driver

A hybrid gate driver circuit includes a field effect transistor (FET) drive terminal, a switching node terminal, a transistor, and a capacitor. The transistor includes a first terminal coupled to the FET drive terminal, and a second terminal coupled to ground. The capacitor includes a first terminal coupled to the switching node terminal, and a second terminal coupled to a third terminal of the transistor.

BACKGROUND

A switch-mode power supply is an electronic circuit that converts an input direct current (DC) supply voltage into one or more DC output voltages that are higher or lower in magnitude than the input DC supply voltage. A switch-mode power supply that generates an output voltage lower than the input voltage is termed a buck or step-down converter. A switch-mode power supply that generates an output voltage higher than the input voltage is termed a boost or step-up converter.

Some switch-mode power supply topologies include a drive/power transistor coupled at a switch node to an energy storage inductor/transformer. Electrical energy is transferred through the energy storage inductor/transformer to a load by alternately opening and closing the switch as a function of a switching signal. The amount of electrical energy transferred to the load is a function of the ON/OFF duty cycle of the switch and the frequency of the switching signal. Switch-mode power supplies are widely used to power electronic devices, particularly battery powered devices, such as portable cellular phones, laptop computers, and other electronic systems in which efficient use of power is desirable.

In order to reduce switching losses in power transistors, the power transistors must be switched on and off very rapidly. Because the power transistor's control terminal may present significant capacitance, a gate driver circuit may be employed to buffer an input signal and drive the power transistor's control terminal. The gate driver circuit receives a low-power input signal and buffers the input signal to produce a high-current signal that quickly charges or discharges the input capacitance of the power transistor. Examples of power transistors with which a gate driver circuit may be employed include insulated gate bipolar transistors and metal oxide semiconductor field-effect-transistors.

SUMMARY

A hybrid gate driver circuit that controls the low-side power transistor of a switch-mode power supply based on the slew rate of voltage at the switching node of the power supply is disclosed herein. In one example, a hybrid gate driver circuit includes a field effect transistor (FET) drive terminal, a switching node terminal, a transistor, and a capacitor. The transistor includes a first terminal coupled to the FET drive terminal, and a second terminal coupled to ground. The capacitor includes a first terminal coupled to the switching node terminal, and a second terminal coupled to a third terminal of the transistor.

In another example, a switch-mode power supply circuit includes a switching node, a low-side field effect transistor (FET), and a hybrid gate driver circuit. The low-side power FET includes a first terminal coupled to the switching node, and a second terminal coupled to ground. The hybrid gate driver circuit is configured to control activation of the low-side power FET based on a pulse width modulation signal and a slew rate of signal at the switching node.

In a further example, a method for driving a low-side power transistor in a switch-mode power supply includes turning off the low-side power transistor and turning on a high-side power transistor. A pulse is generated based on a slew rate of signal at a switching node of the switch-mode power supply. The pulse is applied to turn on a first transistor that holds the low-side power transistor off.

DETAILED DESCRIPTION

In a switch-mode power supply, such as a DC-DC converter, the power transistors (e.g., field effect transistors (FETs)) are selected for fast switching with reduced switching power loss. The gate driver circuits that activate the power transistors provide a low output resistance to ensure fast switching of the power transistors. With the parasitic inductance and capacitance of the packaging of power supply components and the circuit boards on which the packages are mounted, fast switching of the power transistors can create significant noise (power supply noise) at the integrated circuit power terminals, which results in a transient drop in power supply voltage. A reduction in power supply voltage causes the resistance of the gate drivers to increase. When the output switching node of the switch-mode power supply rises coincidentally with the drop in the power supply voltage provided to the gate driver circuit, capacitive coupling through the drain-gate capacitance of the low-side power transistor can cause the low-side power transistor to turn on and provide a conduction path from the output switching node to ground, which produces ground noise, reduces power supply efficiency, and can damage the low-side and/or the high-side power transistors.

FIG.1shows an example of transients on a low-side power transistor gate drive signal caused by power supply noise.FIG.1shows the low-side power transistor gate drive signal102and the high-side power transistor gate drive signal106in graph101, the switching node voltage110in graph103, and the power supply voltage114in graph105. The power supply voltage114may be 3.3.volts or another relatively low voltage.

At falling edge104, the low-side power transistor gate drive signal102is deactivated to turn off the low-side power transistor before the high-side power transistor is turned on. At108, the high-side power transistor gate drive signal106is activated to turn on the high-side power transistor. Responsive to turning off the high-side power transistor, the switching node voltage110transitions at rising edge112and noise116is induced on the power supply voltage114. Reduction of the power supply voltage114caused by the noise116reduces the resistance of the low-side gate driver circuit, and noise (transients)118arise on the low-side power transistor gate drive signal102. The noise116may be large enough to turn on the low-side power transistor, which connects the output switching node to ground causing a large, and potentially damaging, current to flow in both the low-side and high-side power transistors.

Some gate driver circuits include large pull-down transistors in an attempt to maintain low output resistance when power supply voltage is reduced. The large transistors may provide limited benefit in maintaining low output resistance, but require substantial increase in circuit size.

The hybrid gate driver circuits described herein provide low resistance pull down to the low-side power transistor by monitoring the slew rate of voltage at the output switching node, and reducing gate driver circuit output resistance in correspondence to the slew rate. Gate drive strength is adjusted as needed based on the slew rate independent of the power supply voltage provided to the gate driver circuit, and is therefore insensitive to noise induced power supply voltage transients. The hybrid gate driver circuits provide low resistance pull down without adding large pull-down transistors, which reduces circuit size relative of other gate driver circuit implementations.

FIG.2shows a schematic level diagram for an example switch-mode power supply200that includes a hybrid gate driver circuit as described herein. The switch-mode power supply200is illustrated as a step-down (buck) converter, but implementations of the hybrid gate driver circuit are applicable to other topologies, such as step-up (boost) converters. The switch-mode power supply200includes a high-side power transistor202, a high-side gate driver circuit204, a low-side power transistor206, and a hybrid gate driver circuit208. The switch-mode power supply200may include addition components that have been omitted fromFIG.2in the interest of clarity. For example, the switch-mode power supply200may include a control circuit including a pulse width modulator that controls switching of the high-side power transistor202and the low-side power transistor206to maintain a selected voltage at an output of the switch-mode power supply200.

In operation, the high-side power transistor202and the low-side power transistor206are alternately activated to charge and discharge an inductor228coupled to a switching node210. The high-side power transistor202is activated to connect the inductor228to a voltage source (VIN) for charging. The low-side power transistor206is activated to connect the inductor228to ground for discharging. The high-side gate driver circuit204generates a drive signal (HDRV) having voltage VBOOTto drive the gate of the high-side power transistor202to activate and deactivate the high-side power transistor202. VBOOTis greater than VINto turn on the transistor202. For example, VINmay be 12 volts and VBOOTmay be 15 volts. An input terminal of the high-side gate driver circuit204may be coupled to a pulse width modulator or other control circuit (not pictured) that generates a pulse width modulation signal (HDINZ) for activating and deactivating the high-side power transistor202. The hybrid gate driver circuit208generates a drive signal (LDRV) to drive the gate of the low-side power transistor206to activate and deactivate the low-side power transistor206. An input terminal232(pulse width modulation input terminal) of the high-side gate driver circuit204may be coupled to the pulse width modulator or other control circuit that generates a pulse width modulator signal (LDINZ) for activating and deactivating the low-side power transistor206. A FET drive terminal212of the hybrid gate driver circuit208is coupled to the gate terminal206G of the low-side power transistor206. A source terminal206S of the low-side power transistor206is coupled to ground. A drain terminal206D of the low-side power transistor206is coupled to the switching node210.

The hybrid gate driver circuit208includes a pull-up transistor230and a pull-down transistor218. The pull-up transistor230is activated to turn-on the low-side power transistor206responsive to a pulse width modulation signal received via the input terminal232. The pull-up transistor230includes a source terminal230S coupled to a power supply terminal215(VDD), a drain terminal coupled to the gate terminal206G of the low-side power transistor206, and a gate terminal230G coupled to the input terminal232. VDDmay be a relatively low voltage, such as 3.3 volts. The pull-down transistor218is activated to turn off the low-side power transistor206responsive to the pulse width modulation signal. The transistor218includes a drain terminal218D coupled to the gate terminal206G of the low-side power transistor206, a source terminal218S coupled to a ground terminal, and a gate terminal218G coupled to the input terminal232.

The hybrid gate driver circuit208also includes circuitry213that mitigates the effects of power supply noise and noise caused by switching at the switching node210on the low-side transistor gate drive signal LDRV. The circuitry213includes a transistor216, a slew rate monitoring circuit214, a transistor220, and a clamp circuit226. The transistor216pulls down the gate terminal206G of the low-side power transistor206responsive to a control signal generated by the slew rate monitoring circuit214. The transistor216includes a drain terminal216D coupled to the FET drive terminal212, a source terminal216S coupled to ground, and a gate terminal216G coupled to the slew rate monitoring circuit214.

The slew rate monitoring circuit214monitors the voltage at the switching node210, and generates a control signal to activate the pull-down transistor218based on the slew rate of the voltage at the switching node210. The slew rate monitoring circuit214includes a capacitor222and a resistor224. The capacitor222includes a terminal222A coupled to the switching node210and a terminal222B coupled to the gate terminal216G of the transistor216. The resistor224includes a terminal224B coupled to ground, and a terminal224A coupled to the terminal222B of the capacitor222and the gate terminal216G of the transistor216. When the high-side power transistor202is activated, creating a rising edge at the switching node210, a voltage is developed across the resistor224via the capacitor222. The voltage developed across the resistor224is a function of the slew rate of the rising edge at the switching node210. Higher slew rates at the switching node210produce a higher voltage across the resistor224and at the gate terminal216G of the transistor216. Thus, the transistor216is activated to pull down the FET drive terminal212and the gate terminal206G of the low-side power transistor206based on the slew rate of the signal at the switching node210.

The clamp circuit226ensures that the voltage across the resistor224is limited to a predetermined range (e.g., the voltage of the power supply powering the hybrid gate driver circuit208). The clamp circuit226includes a terminal226A coupled to the terminal224A of the resistor224, and a terminal226B coupled to ground. The clamp circuit226may be implemented using a Zener diode, a VGSclamping circuit, an active clamping circuit, or other clamping circuit.

The transistor220controls operation of the transistor216based on the state of the pulse width modulation signal received at the input terminal232. The transistor220enables operation of the transistor216when the pulse modulation signal received at the input terminal232has a state intended to activate the pull-down transistor218(i.e., to pull down the gate terminal206G of the low-side power transistor206). The transistor220disables operation of the transistor216, by pulling the gate terminal216G of the transistor216to ground, when the pulse modulation signal received at the input terminal232has a state intended to deactivate the pull-down transistor218(i.e., to pull up the gate terminal206G of the low-side power transistor206). Thus, the transistor220enables the transistor216to pull down the gate terminal206G of the low-side power transistor206only when the pulse modulation signal received at the input terminal232indicates that the gate terminal206G of the low-side power transistor206is to be pulled down. A drain terminal220D of the transistor220is coupled to the gate terminal216G of the transistor216. A source terminal220S of the transistor220is coupled to ground. A gate terminal220G of the transistor220is coupled to the input terminal232via an inverter236.

The high-side power transistor202, the high-side gate driver circuit204, the transistor216, the pull-down transistor218, and the transistor220may be N-channel metal oxide semiconductor field effect transistors (MOSFETs). The pull-up transistor230may be a P-channel MOSFET.

FIG.3shows an example of signals in the hybrid gate driver circuit208as described herein.FIG.3shows the signal302at the switching node210, the power supply voltage306that powers the hybrid gate driver circuit208, the signal310at the gate terminal218G of the pull-down transistor218, and the signal314at the gate terminal216G of the transistor216. When the high-side power transistor202is activated, the signal302rises at edge304. Switching of the high-side power transistor202induces noise308on the power supply voltage306. The noise308causes the voltage of the power supply voltage306to drop. The noise on the power supply voltage306reduces the voltage at the gate terminal218G of the pull-down transistor218, which increases the resistance of the pull-down transistor218making the low-side power transistor206more susceptible to activation via the drain-gate capacitance234thereof.

Transition of the signal302at edge304induces pulse316on the signal314. The pulse316activates the transistor216, which lowers the pull-down resistance at the gate terminal206G of the low-side power transistor206and prevents the low-side power transistor206from activating. Falling edge318of the signal302does not trigger the hybrid gate driver circuit208to activate the transistor216because the voltage at the terminal222B of the capacitor222falls responsive to the falling edge318of the signal302.

FIG.4shows an example of signals in the hybrid gate driver circuit208with positive and negative current flow in the inductor228.FIG.4shows a high-side pulse width modulation signal402(also shown inFIG.2as input HDINZ to the high-side gate driver circuit204), a low-side pulse width modulation signal404(also shown inFIG.2as input LDINZ to the hybrid gate driver circuit208), a signal406at the gate terminal218G of the pull-down transistor218, a signal408at the gate terminal220G of the transistor220, a signal410at the gate terminal206G of the low-side power transistor206, and a signal412at the gate of the high-side power transistor202. With positive current flowing in the inductor228, signal416at the switching node210transitions responsive to activation of the high-side power transistor202by the signal412, and the signal420at the gate terminal216G of the transistor216is generated in the hybrid gate driver circuit208to inhibit activation of the low-side power transistor206. With negative current flowing in the inductor228, a signal414at the switching node210transitions responsive to deactivation of the low-side power transistor206by the signal410, and the signal418at the gate terminal216G of the transistor216is generated in the hybrid gate driver circuit208to inhibit activation of the low-side power transistor206. Thus, the hybrid gate driver circuit208inhibits activation of the low-side power transistor206based on the slew rate of signal at the410for both positive and negative current flow in the inductor228.

FIG.5shows a comparison of transients on a low-side power transistor drive signal with and without the hybrid gate driver circuit208.FIG.5shows the signal502at the switching node210, the power supply voltage506that powers the hybrid gate driver circuit208, and the signal510at the gate terminal218G of the pull-down transistor218. When the high-side power transistor202is activated, the signal502rises at edge504. Switching of the high-side power transistor202induces noise508on the power supply voltage506. The noise508causes the voltage of the power supply voltage506to drop. The drop in the voltage of the power supply voltage506can be fairly large (e.g., about 2 volts with nominal 3.3 volt power supply). The noise on the power supply voltage506reduces the voltage at the gate terminal218G of the pull-down transistor218, which increases the resistance of the pull-down transistor218making the low-side power transistor206more susceptible to activation via the drain-gate capacitance of the low-side power transistor206.

In a conventional gate driver circuit, the noise on the power supply voltage506produces transients512at the gate terminal206G of the transistor206. The voltage of the transients512may exceed the threshold voltage of the low-side power transistor206and activate the low-side power transistor206in some switch-mode power supplies. In contrast, the voltage of the transients514generated on the drive signal516in the hybrid gate driver circuit208is substantially lower than that of the transients512. The voltage of the transients514generated in the hybrid gate driver circuit208is below the threshold voltage of the low-side power transistor206thereby preventing the low-side power transistor206from turning on.

FIG.6shows a flow diagram for a method600for driving a low-side power transistor in a switch-mode power supply as described herein. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some implementations may perform only some of the actions shown. Operations of the method600may be performed by an implementation of the switch-mode power supply200.

In block602, the low-side power transistor206turns off to disconnect the switching node210from ground.

In block604, the transistor220is turned off. The transistor220is turned off in conjunction with turning off the low-side power transistor206. Turning off the transistor220enables turn on of the transistor216.

In block606, the high-side power transistor202is turned on to connect the switching node210to VIN. Turning on the high-side power transistor202produces the edge304(FIG.3) at the switching node210.

In block608, the slew rate monitoring circuit214generates a pulse316(FIG.3) based on the slew rate of the edge304at the switching node210. The amplitude of the pulse316is a function of the slew rate of the edge304.

In block610, the pulse316is applied at the gate terminal216G of the transistor216to turn on the transistor216and hold the low-side power transistor206off. Thus, the slew rate monitoring circuit214and the transistor216operate to prevent the low-side power transistor206from turning on due to noise created by the edge304.

In block612, the high-side power transistor202is turned off to disconnect the switching node210from VIN.

In block614, the low-side power transistor206is turned on to connect the switching node210to ground.

In block616, the transistor220is turned on, in conjunction with turn off of the low-side power transistor206. Turning on the transistor216prevents turn on of the transistor216while the low-side power transistor206is on.