Multi chip package, manufacturing method thereof, and memory system having the multi chip package

A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2011-0035951 filed on Apr. 19, 2011, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Articles of manufacture, systems, and methods consistent with the present inventive concept relate to a multi chip package, and more particularly, to a multi-chip package that increases a manufacturing yield, a manufacturing method thereof, and a memory system having the multi-chip package.

2. Description of the Related Art

As a refining process reaches a limit in a semiconductor chip manufacturing process, costs of manufacturing a semiconductor chip using the refining process are apt to increase. To increase the density of a latest semiconductor memory and a memory module, a conventional two-dimensional (2D) chip manufacturing process technology is being developed to a three-dimensional (3D) chip manufacturing process technology using through silicon via (TSV) technology.

SUMMARY

The present general inventive concept provides a multi-chip package that increases a manufacturing yield by making a multi chip package including a bad chip perform a normal operation, a manufacturing method of the multi-chip package and a memory system including the multi-chip package.

According to an aspect of an exemplary embodiment, there is provided a multi-chip package, including a plurality of chips including at least one bad chip and at least one good chip that are stacked, and a plurality of through electrodes each penetrating the plurality of chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

Each of the plurality of through electrodes may be through silicon via (TSV). The logic circuit included in the at least a bad chip may be isolated from each of the plurality of through electrodes by a fuse, an anti-fuse or an efuse. Alternatively, the logic circuit included in the at least one bad chip may be isolated from each of the plurality of through electrodes by post package repair (PPR).

According to another aspect of an exemplary embodiment, there is provided a memory module that comprises the multi-chip package and a semiconductor substrate on which the multi-chip package is mounted.

The memory module may be embodied in a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a registered DIMM, a fully buffered DIMM (FBDIMM), a small outline dual in-line memory module (SO-DIMM) or a microDIMM.

According to another aspect of an exemplary embodiment, there is provided a memory system that comprises a memory module, a main board, a slot mounted on the main board and in which the memory module may be inserted, and a processor that controls, through the slot, an operation of the at least one good chip included in the multi-chip package mounted on the memory module.

According to another aspect of an exemplary embodiment, there is provided a memory system that comprises the multi-chip package and a memory controller that controls the at least one good chip included in the multi-chip package.

According to another aspect of an exemplary embodiment, there is provided a manufacturing method of the multi-chip package, the method comprises bonding a plurality of wafers in succession, stacking at least one good chip on at least one bad chip included in the plurality of bonded wafers, connecting the at least one bad chip and the at least one good chip electrically, and electrically isolating a logic circuit included in the at least one bad chip from the at least one good chip.

The step of isolating may use a fuse, an anti-fuse or an efuse. Alternatively, the step of isolating may use post package repair (PPR).

According to another aspect of an exemplary embodiment, there is provided a memory module manufacturing method, the method comprising mounting the multi-chip package manufactured by the multi-chip package manufacturing method on a semiconductor substrate.

According to another aspect of an exemplary embodiment, there is provided a memory system manufacturing method, the method comprising mounting a slot on a main board and inserting the memory module manufactured by the manufacturing method of the memory module in the slot.

DETAILED DESCRIPTION

Exemplary embodiments now will be described more fully hereinafter with reference to the accompanying drawings. The exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout.

FIG. 1is a cross-sectional diagram of a multi-chip package including a plurality of chips according to an exemplary embodiment. Referring toFIG. 1, a multi chip package10includes at least one good chip12-1or12-3and at least one bad chip12-2stacked to each other.

The at least one good chip12-1or12-3includes a logic circuit18and a plurality of connection circuits17, and the at least one bad chip12-2includes a logic circuit18-1and a plurality of connection circuits17-1. A plurality of chips12may be connected electrically to a plurality of through electrodes15through a plurality of connection elements16.

FIG. 1illustrates three chips stacked to each other for convenience of explanation; however, the technical concept of the present inventive concept does not restrict the number of chips stacked to each other.

Each of the plurality of chips12may be embodied in a volatile memory chip such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a thyristor RAM (T-RAM), a zero capacitor RAM (Z-RAM) or a twin transistor RAM (TTRAM).

In addition, each of the plurality of chips12may be embodied in a non-volatile memory chip such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM (MRAM), a spin-transfer torque MRAM, a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM) also called an ovonic unified memory (OUM), a resistive ram (RRAM or ReRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nano floating gate memory (NFGM), a holographic memory, a molecular electronics memory device or an insulator resistance change memory.

Here, the good chip12-1or12-3is a chip where a separate chip embodied on a wafer operates normally at a test step. The bad chip12-2is a chip where a separate chip embodied on a wafer malfunctions at a test step. Thus, a bad chip may also be denoted as a faulty chip or a malfunctioning chip.

Each of the plurality of through electrodes15transmits input data, an address, or a command to a logic circuit18. Each of the plurality of through electrodes15may be a through silicon via (TSV). The TSV is an example of an electrical vertical connection.

Each of the plurality of through electrodes15included in each of the plurality of chips12may be connected to each other through different connection elements16. For example, the plurality of connection elements16may be a bump or a solder ball. It may be an anisotropic conductive film (ACF) in some cases.

FIG. 2is a drawing for explaining a connection circuit inFIG. 1. A connection circuit17connected electrically plays a role of connecting the logic circuit18included in the good chip12-1or12-3with each of the plurality of through electrodes15electrically. For example, the connection circuit17may be embodied in a fusing element.

A connection circuit17-1isolated electrically plays a role of isolating a logic circuit18-1included in the bad chip12-2from each of the plurality of through electrodes15.

A fusing element17includes a fuse F and a pad P. A fuse F may be formed by a chemical mechanical polishing (CMP) method, and a pad P is connected to both sides of the fuse F and connected to each of the plurality of through electrodes15.

Each configuration of the connection circuits17and17-1is the same. However, a fuse of the connection circuit17is in an un-cut state and a fuse of the connection circuit17-1is in a cut state.

When a separate chip is determined to be the bad chip12-2through a test in a process of manufacturing each of the plurality of chips12, a fuse F of a fusing element17-1included in the bad chip12-2is cut by a laser. When the fuse F is cut, the logic circuit18-1included in the bad chip12-2and each of the plurality of through electrodes15are disconnected electrically each other.

Here, a method of utilizing a laser beam is explained as a method of cutting the fuse F in an exemplary embodiment for convenience of explanation; however, the present inventive concept is not restricted to thereto.

Additionally, the fuse F is explained as an example for isolating the logic circuit18-1from each of the plurality of through electrodes15; however, the present inventive concept is not restricted thereto. For example, an anti-fuse or an efuse may be used instead of the fuse. In addition, the logic circuit18-1and each of the plurality of through electrodes15may be isolated by post package repair (PPR).

FIG. 3is a flowchart for explaining a multi-chip package manufacturing method according to an exemplary embodiment, andFIGS. 4A and 4Bare drawings for explaining a manufacturing method of the multi-chip package illustrated inFIG. 1. Referring toFIGS. 1,3,4A and4B, a plurality of wafers41and43are stacked in succession (S310) and bonded successively. Chips12included in each of the plurality of wafers41and43through a bonding process are connected electrically through the plurality of through electrodes15included in the chips12, e.g., through silicon via (TSV).

At least one good chip12-1or12-3is stacked on at least one bad chip12-2included in a plurality of bonded wafers41and43(S320). The at least one bad chip12-2and the at least one good chip12-1or12-3are connected electrically (S330). A logic circuit18-1included in the at least one bad chip12-2is isolated from the at least one good chip12-1or12-3electrically (S340). It should be noted that operations S330and S340may be performed in reverse order.

The logic circuit18-1included in the at least one bad chip12-2and the at least one good chip12-1or12-3may be isolated from each other electrically by using a fuse, an anti-fuse or an efuse at a wafer manufacturing stage. The logic circuit18-1included in the at least one bad chip12-2and the at least one good chip12-1or12-3may be isolated by using post package repair (PPR) at a multi-chip package manufacturing stage.

FIGS. 5A and 5Bare drawings for explaining a multi-chip package manufacturing method according to another exemplary embodiment. Referring toFIGS. 5A and 5B, a plurality of wafers51,53and55are stacked successively (S310) and bonded successively. Good chips50-4and50-5as many as the number of bad chips50-1and50-3are successively stacked on the bad chips50-1and50-3included in the plurality of bonded wafers51,53and55. Here, the good chips50-4and50-5may be stacked on a wafer51stacked at the top or on a wafer55stacked at the bottom among the plurality of stacked wafers51,53and55, or may be stacked on both wafer51and wafer55. For example,FIG. 5Ashows good chips50-4and50-5stacked on the bottom of wafer55.

In addition, the good chips50-4and50-5may be stacked after all of the plurality of wafers51,53and55are bonded or while the plurality of wafers51,53and55are being bonded. A multi-chip package57manufactured through the wafer manufacturing process performs a normal operation even though it includes the bad chips50-1and50-3.

FIG. 6is a memory module including the multi-chip package illustrated inFIG. 1. Referring toFIG. 6, a memory module200includes a semiconductor substrate210and a plurality of multi-chip packages10mounted on the semiconductor substrate210.

Each configuration of the plurality of multi-chip packages10is substantially the same as configuration of the multi-chip package10explained inFIG. 1. The memory module200may be embodied in a single inline memory module (SIMM), a double in-line memory module (DIMM), a registered DIMM, a fully buffered DIMM (FBDIMM), a small outline dual in-line memory module (SO-DIMM) or a MicroDIMM.

FIG. 7is an exemplary embodiment of a memory system including the memory module illustrated inFIG. 6. Referring toFIG. 7, a memory system300which may be embodied in a computer system such as a personal computer (PC) or a mobile computing device includes a main board240, a slot250mounted on the main board240, the memory module200which may be inserted in the slot250and a memory controller270which may control operations of the plurality of multi-chip packages10mounted on the memory module200through the slot250.

The memory controller270may transmit or receive data to/from each of the plurality of multi-chip packages10through a data bus according to a control of a central processing unit (CPU)280. The memory system300may be embodied in a PC, a tablet PC or a laptop computer.

FIG. 8is another exemplary embodiment of a memory system including the multi-chip package illustrated inFIG. 1. Referring toFIGS. 1 and 8, a memory system400may be embodied in a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA) or a radio communication device.

The memory system400includes a multi-chip package10and a memory controller450controlling an operation of the multi-chip package10. The memory controller450may control a data access operation of the multi-chip package10, e.g., a program operation, an erase operation or a read operation, according to a control of a processor410.

A radio transceiver430may transmit or receive a radio signal through an antenna ANT. For example, the radio transceiver430may convert a radio signal received through the antenna ANT into a signal which may be processed by the processor410. Accordingly, the processor410may process a signal output from the radio transceiver430and transmit a processed signal to the memory controller450or the display420. The memory controller450may program or write a signal processed by the processor410in the multi-chip package10. The radio transceiver430may also convert a signal output from the processor410into a radio signal and output a converted radio signal to an external device through the antenna ANT.

An input device440is a device which may input a control signal for controlling an operation of the processor410or data to be processed by the processor410. It may be embodied in a pointing device such as a touch pad and a computer mouse, a keypad or a keyboard.

The processor410may control an operation of the display420so that data output from the memory controller450, data output from the radio transceiver430or data output from the input device440may be displayed through the display420.

According to an exemplary embodiment, the memory controller450which may control an operation of the multi-chip package10may be embodied in a part of the processor410or in a separate chip from the processor410.

FIG. 9is still another exemplary embodiment of a memory system including the multi-chip package illustrated inFIG. 1. A memory system500illustrated inFIG. 9may be embodied in a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), a Moving Picture Experts Group Layer-3 (MP3) player or a Moving Picture Experts Group Layer-4 (MP4) player.

The memory system500includes a memory controller540which may control a data processing operation of a multi-chip package10. A processor510may display data stored in the multi-chip package10through a display530according to data input through an input device520. For example, an input device520may be embodied in a pointing device such as a touch pad or a computer mouse, a keypad or a keyboard.

The processor510may control a general operation of the memory system500and an operation of the memory controller540. According to an exemplary embodiment, the multi-chip package10and the memory controller540which may control an operation of the multi-chip package10may be embodied in a part of the processor510or in a separate chip from the processor510.

FIG. 10is still another exemplary embodiment of a memory system including the multi-chip package10illustrated inFIG. 1. A memory system600illustrated inFIG. 10may be embodied in a memory card or a smart card. The memory system600includes a multi-chip package10, a memory controller610and a card interface620.

The memory controller610may control data exchange between the multi-chip package10and the card interface620. According to an exemplary embodiment, the card interface620may be a secure digital (SD) card interface or a multi-media card (MMC) interface; however, the card interface620is not restricted thereto. The card interface620may interface data exchange between a host630and the memory controller610according to a protocol of the host630.

According to an exemplary embodiment, the card interface620may support a universal serial bus (USB) protocol and an interchip (IC)-USB protocol. Here, a card interface may mean hardware supporting a protocol which the host630uses, software installed in the hardware or a signal transmission mode.

When the memory system600is connected to a host interface650of the host630such as a PC, a tablet PC, a digital camera, a digital audio player, a cellular phone, console video game hardware or a digital set-top box, the host interface650may perform data communication with a non-volatile multi-chip package10through the card interface620and the memory controller610according to a control of a microprocessor640.

FIG. 11is still another exemplary embodiment of a memory system including the multi-chip package10illustrated inFIG. 1. A memory system700illustrated inFIG. 11may be embodied in an image processing device, e.g., a digital camera, a cellular phone equipped with the digital camera, a smart phone equipped with the digital camera, or a tablet PC equipped with the digital camera.

The memory system700includes a multi-chip package10and a memory controller740which may control a data processing operation of the multi-chip package10, e.g., a program operation, an erase operation or a read operation. An image sensor720of the memory system700converts an optical image into digital signals, and converted digital signals are transmitted to the processor710or the memory controller740. According to a control of the processor710, the converted digital signals may be displayed through a display730or stored in the multi-chip package10through the memory controller740.

In addition, data stored in the multi-chip package10are displayed through the display730according to a control of the processor710or the memory controller740. According to an exemplary embodiment, the memory controller740which may control an operation of the multi-chip package10may be embodied in a part of the processor710or in a separate chip from the processor710.

FIG. 12is still another exemplary embodiment of a memory system including the multi-chip package illustrated inFIG. 1. Referring toFIG. 12, a memory system800includes a multi-chip package10and a central processing unit (CPU)810which may control an operation of the multi-chip package10.

The memory system800includes a memory device850which may be used as an operation memory of the CPU810. The memory device850may be embodied in a non-volatile memory such as a read only memory (ROM) or a volatile memory such as a static random access memory (SRAM). A host connected to the memory system800may perform data communication with the multi-chip package10through a memory interface820and a host interface840.

An error correction code (ECC) block830may detect an error bit included in data output from the multi-chip package10through the memory interface820, correct the error bit, and transmit error-corrected data to a host through the host interface840according to a control of the CPU810. The CPU810may control data communication among the memory interface820, the ECC block830, the host interface840and the memory device850through a bus801.

The memory system800may be embodied in a flash memory drive, a USB memory drive, an IC-USB memory drive or a memory stick.

A multi-chip package of the present inventive concept may increase a manufacturing yield by making a multi-chip package including a bad chip perform a normal operation.