Display substrate and method of manufacturing the same

In a manufacturing method of a display substrate according to one or more embodiments, a plurality of thin films are patterned by using a photoresist film pattern having different thicknesses in each area on a substrate as etch masks. The photoresist film pattern may be etch-backed at least twice during the manufacturing process of the display substrate and may be used as the etch mask for patterns having shapes different from each other. Accordingly, the number of processes for manufacturing the mask patterns, which may be formed by a photolithography method in order to pattern the thin films formed on the substrate, may be reduced.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and benefit from Korean Patent Application No. 2007-0126784 filed on Dec. 7, 2007, the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

1. Technical Field

Embodiments of the present invention generally relate to a display substrate and a method of manufacturing the display substrate.

2. Description of the Related Art

In general, a display apparatus that displays an image includes a display substrate. A plurality of pixel areas that displays an image is defined in the display substrate. Each pixel area includes a thin film transistor and a pixel electrode electrically connected to the thin film transistor.

The thin film transistor includes a semiconductor pattern to selectively provide the pixel electrode with a pixel voltage according to a voltage applied to a gate electrode thereof. The semiconductor pattern includes an organic semiconductor such as amorphous silicon or pentacene.

When the semiconductor pattern includes an organic semiconductor, the organic semiconductor is formed on the display substrate through an inkjet method. When forming the organic semiconductor on the display substrate through the inkjet method, precise patterning of the organic semiconductor is difficult. Thus, a technology has been proposed for forming a bank pattern on the display substrate and introducing the organic semiconductor into an opening of the bank pattern before forming the organic semiconductor on the display substrate.

However, when forming the organic semiconductor on the display substrate by using the bank pattern, this additional process of forming the bank pattern would be required. Thus, the number of processes for the display substrate increases, thereby increasing the manufacturing cost of the display substrate.

SUMMARY

Embodiments of the present invention generally provide a display apparatus having a simplified structure and reduced manufacturing cost and a method of manufacturing the display substrate.

In one aspect of an embodiment of the present invention, a method of manufacturing a display substrate is provided as follows. A gate electrode is formed on a substrate and a gate insulating layer is formed on the substrate to cover the gate electrode. Then, first and second conductive layers are sequentially formed on the gate insulating layer to form a source-drain layer, and a first insulating layer pattern is formed on the source-drain layer. A preliminary source-drain layer is formed by patterning the source-drain layer by using the first insulating layer pattern and a second insulating layer pattern, which is formed by primarily etching the first insulating layer pattern, as etch masks, respectively. A third insulating layer pattern is formed by secondarily etching the second insulating layer pattern, and a surface treatment is performed relative to the substrate. A source electrode and a drain electrode, which are spaced apart from each other, are formed by patterning the preliminary source-drain layer, and an organic semiconductor layer is formed on the source and drain electrodes. Then, a pixel electrode electrically connected to the drain electrode is formed on the substrate.

In another aspect of an embodiment of the present invention, a display substrate includes: a substrate in which a pixel area is defined, a gate line formed on the substrate, a gate insulating layer formed on the gate line to cover the gate line, a data line insulated from the gate line while crossing the gate line, and defining the pixel area in combination with the gate line, a gate electrode branching from the gate line, a source electrode branching from the data line, a drain electrode spaced apart from the source electrode, an organic semiconductor layer formed on the source electrode and the drain electrode, and a pixel electrode formed on the substrate in correspondence with the pixel area, and electrically connected to the drain electrode. In order to easily form the organic semiconductor layer on the gate insulating layer, the gate insulating layer has a different surface energy in each area. According to one or more embodiments, a portion of the gate insulating layer corresponding to an area in which the organic semiconductor layer is formed, has a surface energy greater than a surface energy of the gate insulating layer corresponding to an area in which the organic semiconductor layer is not formed.

According to the above description of one or more embodiments, when forming the organic semiconductor layer through an inkjet method, a bank pattern used for the organic semiconductor layer may be omitted. Accordingly, a photolithography process for the bank pattern may be omitted, so that the manufacturing process of the display substrate may be simplified and the manufacturing cost of the display substrate may be reduced.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present invention will be explained in detail with reference to the accompanying drawings. However, the scope of the present invention is not limited to such embodiments and the present invention may be realized in various forms. Embodiments of the present invention are defined only by the scope of the appended claims. In addition, the size of layers and regions shown in the drawings may be simplified or magnified for the purpose of clear explanation. In addition, the same reference numerals are used to designate the same elements throughout the drawings.

FIGS. 1A,2A,3A,4A,5A,6A,7A,8A and9A are plan views illustrating a method of manufacturing a display substrate according to one or more exemplary embodiments of the present invention, andFIGS. 1B,2B,3B,4B,5B,6B,7B,8B and9B are cross-sectional views taken along line I-I′ shown inFIGS. 1A,2A,3A,4A,5A,6A,7A,8A and9A, respectively, according to one or more embodiments.

Referring toFIGS. 1A and 1B, a gate line GL and a gate electrode GE branching from the gate line GL are formed on a substrate10. After forming the gate line GL and the gate electrode GE on the substrate10, a gate insulating layer20that covers the gate line GL and the gate electrode GE is formed on the substrate10. The gate line GL and the gate electrode GE may be made by forming a conductive layer (not shown) on the substrate10and patterning the conductive layer.

In the present exemplary embodiment, the substrate10may include a transparent glass base material. However, the substrate10may also include other transparent and flexible materials, e.g. plastic.

Referring toFIGS. 2A and 2B, a first conductive layer31and a second conductive layer34are sequentially formed on the substrate10to form a source-drain layer37. The first and second conductive layers31and34are sequentially formed on the substrate10because a surface treatment process for the substrate10is performed between a patterning process for the first conductive layer31and a patterning process for the second conductive layer34. Detailed descriptions of the surface treatment process according to one or more embodiments will be given with reference toFIGS. 5A and 5B.

Referring toFIGS. 2B,3A and3B, a first insulating layer pattern40is formed on the source-drain layer37. The first insulating layer pattern40is removed corresponding to a first area A1to form an opening. The first insulating layer pattern40may have thicknesses that are different from each other in the second to fourth areas A2to A4, respectively. According to an embodiment, the first insulating layer pattern40has a first thickness t1in the second area A2, a second thickness t2greater than the first thickness t1in the third area A3, and a third thickness t3greater than the second thickness t2in the fourth area A4.

The first insulating layer pattern40may be formed by forming a photoresist film on the substrate10, exposing the photoresist film by using a photomask formed with a slit pattern and a transflective member, and developing the photoresist film. Furthermore, the first insulating layer pattern40may also be formed through an imprint scheme, in which an imprint resin layer is formed on the substrate10, and then the imprint resin layer is pressed by a mold. The se two methods of forming the first insulating layer pattern40according to one or more embodiments will be described in more detail with reference toFIGS. 10 and 11.

FIG. 10is a sectional view illustrating a method of forming the first insulating layer pattern40according to an embodiment. Referring toFIG. 10, a photoresist film45having positive photosensitivity is formed on the substrate10on which the gate electrode GE, the gate insulating layer20and the source-drain layer37are formed.

After forming the photoresist film45on the substrate10, a photomask110is aligned above the substrate10such that the photomask110faces the substrate10, and source light L0is irradiated onto the photoresist film45to expose the photoresist film45.

A first part of the photomask110corresponding to the first area A1is open or prepared in the form of a transmitting member101, a second part of the photomask110corresponding to the second area A2is prepared in the form of a transflective member48, a third part of the photomask110corresponding to the third area A3is prepared in the form of the transflective member48and a slit pattern103, and a fourth part of the photomask110corresponding to the fourth area A4is prepared in the form of a light blocking member102.

Accordingly, the first light L1irradiated onto the first area A1of the photoresist film45has a first light amount, the second light L2irradiated onto the second area A2has a second light amount smaller than the first light amount, the third light L3irradiated onto the third area A3has a third light amount smaller than the second light amount, and light is not irradiated onto the fourth area A4.

As the exposed photoresist film45is developed, the photoresist film45is partially removed according to the amount of the irradiated light. According to an embodiment, the photoresist film45may be completely removed from the first area A1, the photoresist film45has a first thickness t1in the second area A2, the photoresist film45has a second thickness t2greater than the first thickness t1in the third area A3, and the photoresist film45has a third thickness t3greater than the second thickness t2in the fourth area A4.

FIG. 11is a sectional view illustrating a method of forming the first insulating layer pattern40according to another exemplary embodiment of the present invention. Referring toFIG. 11, after forming a photoresist film having photosensitivity on the substrate10on which the gate electrode GE, the gate insulating layer20and the source-drain layer37are formed, the first insulating layer pattern40may be formed by imprinting the photoresist film using a mold120.

Although not shown inFIG. 11, after forming the first insulating layer pattern40, the first insulating layer pattern40may be cured by irradiating light onto the first insulating layer pattern40, then the mold120may be separated from the substrate10so that photoresist film patterns having thicknesses different from each other may be formed in each area.

Referring again toFIGS. 2B,3A and3B, after forming the first insulating layer pattern40on the substrate10, the source-drain layer37is etched using the first insulating layer pattern40as an etch mask. Thus, the source-drain layer corresponding to the first area A1is removed to form a preliminary source-drain pattern38that includes a data line, and first and second preliminary conductive patterns32and35, and is located on the same plane with the first insulating layer pattern40.

Referring toFIGS. 3B,4A and4B, a second insulating layer pattern41may be formed by performing a first etch-back process relative to the first insulating layer pattern40. The second insulating layer pattern41has fourth and fifth thicknesses t4and t5in the third and fourth areas A3and A4, respectively. The second insulating layer pattern41is completely removed from the first and second areas A1and A2.

The first insulating layer pattern40is etched by the first thickness t1through the first etch-back process. Thus, the fourth thickness t4is identical to the difference between the second thickness t2and the first thickness t1, and the fifth thickness t5is identical to the difference between the third thickness t3and the first thickness t1.

After forming the second insulating layer pattern41on the substrate10, the second preliminary conductive pattern35corresponding to the second area A2may be etched by using the second insulating layer pattern41as an etch mask to form a top preliminary source electrode36aand a top preliminary drain electrode36b.

Referring toFIGS. 4B,5A and5B, a third insulating layer pattern42may be formed by performing a second etch-back process relative to the second insulating layer pattern41. The third insulating layer pattern42has a sixth thickness t6in the fourth area A4, and is completely removed from the first to third areas A1to A3.

The second insulating layer pattern41is etched by the fourth thickness t4through the second etch-back process. Thus, the sixth thickness t6is identical to the difference between the fifth thickness t5and the fourth thickness t4.

After forming the third insulating layer pattern42on the substrate10, the substrate10may be subjected to a surface treatment process to reduce the surface energy of the outermost thin film exposed on the substrate10. In the present exemplary embodiment, the surface treatment process for the substrate10may include plasma treatment.

The plasma treatment may increase or decrease the surface energy of the substrate10exposed to the exterior. Increasing or decreasing the surface energy of the substrate10exposed to the exterior through the plasma treatment may be determined according to the type of reaction gas used for the plasma treatment. According to the present exemplary embodiment, the plasma treatment may reduce the surface energy of the substrate10exposed to the exterior by using a reaction gas containing fluorine such as CF4.

Since the third insulating layer pattern42is exposed to the exterior after the surface treatment is completed, the surface energy of the third insulating layer pattern42may be reduced through, for example, the plasma treatment. Furthermore, after the surface treatment is completed, the gate insulating layer20may have a different surface energy in each area. According to an embodiment, a portion of the gate insulating layer20overlapping with the first preliminary conductive pattern32may have a surface energy greater than that of a portion of the gate insulating layer20exposed to the exterior.

Referring toFIGS. 5B,6A and6B, the first preliminary conductive pattern32corresponding to the second area A2may be etched using the top preliminary source electrode36aand the top preliminary drain electrode36bas etch masks, thereby forming a bottom source electrode33aand a bottom drain electrode33bwhile being spaced apart from each other.

Furthermore, the first preliminary conductive pattern32corresponding to the second area A2may be etched to expose to the exterior a portion of the gate insulating layer20, which corresponds to the second area A2. The exposed portion of the gate insulating layer20is referred to as a non-surface treatment section21since the non-surface treatment section21is not surface-treated through the surface treatment process. The non-surface treatment section21has a surface energy greater than that of a peripheral section such as the third insulating layer pattern42.

If the non-surface treatment section21has a surface energy greater than that of a peripheral section, an organic, for example, semiconductor layer (reference number50ofFIG. 8B) may be easily formed on the second and third areas A2and A3using an inkjet method. The surface energy of the non-surface treatment section21according to an embodiment will be described in detail with reference toFIGS. 8A and 8B.

Referring toFIGS. 6B,7A and7B, the top preliminary source electrode36aand the top preliminary drain electrode36bcorresponding to the third area A3are patterned using the third insulating layer pattern42, respectively, to form a top source electrode36a′ and a top drain electrode36b′, thereby completing fabrication of a source electrode SE including the top source electrode36a′ and the bottom source electrode33a, and a drain electrode DE including the top drain electrode36b′ and the bottom drain electrode33b.

The reason that the top preliminary source electrode36aand the top preliminary drain electrode36bthat correspond to the third area A3are removed is because the organic semiconductor layer has a lower contact resistance relative to the bottom source electrode33aand the bottom drain electrode33bthan the top source electrode36a′ and the top drain electrode36b′.

For example, when the bottom source electrode33aand the bottom drain electrode33binclude indium tin oxide (ITO) having a low contact resistance relative to the organic semiconductor layer, the organic semiconductor layer may be electrically connected to the bottom source electrode33aand the bottom drain electrode33bby removing the top preliminary source electrode36aand the top preliminary drain electrode36bcorresponding to the third area A3.

When the top source electrode36a′ and the top drain electrode36b′ include a conductor having a low contact resistance relative to the organic semiconductor layer, the process of removing the top preliminary source electrode36aand the top preliminary drain electrode36bcorresponding to the third area A3may also be omitted.

Referring toFIGS. 8A and 8B, an organic semiconductor layer50may be formed on the second and third areas A2and A3by spraying an organic semiconductor51toward the second and third areas A2and A3through a dispenser52, thereby completing fabrication of an organic thin film transistor T that includes the source electrode SE, the gate electrode GE, the drain electrode DE and the organic semiconductor layer50. The organic semiconductor layer50may include an organic material having high flexibility and conductivity such as pentacene, and may serve as an active pattern of the organic thin film transistor T.

The organic semiconductor layer50may be easily formed by spraying the organic semiconductor51toward the substrate10since the non-surface treatment section21of the gate insulating layer20has a surface energy greater than that of the peripheral section.

Referring again toFIG. 5B, since the third insulating layer pattern42is surface-treated through the surface treatment process, the third insulating layer pattern42has a surface energy lower than that of the non-surface treatment section21. Thus, attraction between the non-surface treatment section21and the organic semiconductor51is greater than between the third insulating layer pattern42and the organic semiconductor51. Consequently, although the dispenser52may not exactly (directly) spray the organic semiconductor51onto the second and third areas A2and A3, the organic semiconductor51may move (gravitate) towards the non-surface treatment section21without remaining around the second and third areas A2and A3, such as the third insulating layer pattern42.

As a result, when forming the organic semiconductor layer50by spraying the organic semiconductor51, since the organic semiconductor51is realigned by the surface energy difference, the process of spraying the organic semiconductor51toward the substrate10may be performed with a sufficient margin.

Referring toFIGS. 9A and 9B, after forming an interlayer dielectric layer60on the substrate10on which the organic semiconductor layer50is formed, a pixel electrode PE may then be formed on the interlayer dielectric layer60. The pixel electrode PE may be electrically connected to the drain electrode DE through a contact hole formed through the interlayer dielectric layer60.

The pixel electrode PE is formed in a pixel area defined in the substrate10. Although not shown in detail inFIGS. 9A and 9B, the pixel area is defined by the gate line GL and the data line DL that cross each other. A plurality of pixel areas is defined in proportion to the number of the gate and data lines GL and DL formed on the substrate10. The pixel electrode PE is formed in each pixel area.

Hereinafter, the final structure of the display substrate manufactured by a manufacturing method of the display substrate according to one or more embodiments of the present invention will be described in more detail with reference toFIGS. 9A and 9B.

The gate line GL and the data line DL are formed on the substrate10and are insulated from each other by interposing the gate insulating layer20therebetween. The gate line GL crosses the data line DL, thereby defining the pixel area. Furthermore, the pixel electrode PE is formed in each pixel area. Although the pixel area is not shown inFIGS. 9A and 9B, the pixel area may be regarded (considered) as an area in which the pixel electrode PE is formed.

An organic thin film transistor T electrically connected to the pixel electrode PE is formed in the pixel area. The organic thin film transistor T includes the gate electrode GE branching from the gate line GL, the source electrode SE branching from the data line DL, the drain electrode DE, which includes material the same as that of the data line DL, and the organic semiconductor layer50.

Referring toFIGS. 2A to 7B, the data line DL, the source electrode SE and the drain electrode DE may be made by forming the first conductive layer31on the substrate10, forming the second conductive layer34on the first conductive layer31, and then patterning the first and second conductive layers31and34. Thus, the data line DL, the source electrode SE and the drain electrode DE include the first conductive layer31and the second conductive layer34that is laminated on the first conductive layer31.

The source electrode SE includes the bottom source electrode33a, which includes material the same as that of the first conductive layer31, and the top source electrode36a, which includes material the same as that of the second conductive layer34. The drain electrode DE includes the bottom drain electrode33b, which includes material the same as that of the first conductive layer31, and the top drain electrode36b, which includes material the same as that of the second conductive layer34.

Furthermore, since the second conductive layer34may be removed from the area in which the source electrode SE, the drain electrode DE and the organic semiconductor layer50overlap each other, the top source electrode36amay have a shape different than that of the bottom source electrode33awhen viewed in a plan view, and the top drain electrode36bmay have a shape different than that of the bottom drain electrode33bwhen viewed in a plan view. The reason for removing the second conductive layer34from the area in which the organic semiconductor layer50is formed is because the contact resistance between the first conductive layer31and the organic semiconductor layer50is lower than the contact resistance between the second conductive layer34and the organic semiconductor layer50.

As described above, each of the data line DL, the source electrode SE and the drain electrode DE may include the first conductive layer31and the second conductive layer34formed on the first conductive layer31in an area in which the organic semiconductor layer50is not formed. Since the second conductive layer34may be removed from the area in which the organic semiconductor layer50is formed, each of the source electrode SE and the drain electrode DE may include only the first conductive layer31in such area in which the organic semiconductor layer50is formed.

The material of the second conductive layer34may be selected such that the contact resistance between the second conductive layer34and the organic semiconductor layer50is low. Since the top source electrode36amay have a shape identical to that of the bottom source electrode33awhen viewed in a plan view, the top source electrode36amay make contact with the organic semiconductor layer50. In addition, since the top drain electrode36bmay have a shape identical to that of the bottom drain electrode33bwhen viewed in a plan view, the top drain electrode36bmay also make contact with the organic semiconductor layer50.

Furthermore, the insulating layer pattern42may be formed on the data line DL, the source electrode SE and the drain electrode DE. The insulating layer pattern42may be located on the same plane with the data line DL, the source electrode SE and the drain electrode DE in an area in which the organic semiconductor layer50is not formed. As a result, the second conductive layer34and the insulating layer pattern42may be located on the same plane.

The organic semiconductor layer50may partially overlap the source electrode SE and the drain electrode DE, and face the gate electrode GE while interposing the gate insulating layer20therebetween. The organic semiconductor layer50may include an organic material having high flexibility and conductivity such as pentacene, and may serve as the active pattern of the organic thin film transistor T.

A portion of the gate insulating layer20corresponding to an area in which the organic semiconductor layer50is formed may have a surface energy greater than that of the insulating layer pattern42. Referring again toFIGS. 5A and 5B, when a portion is defined as a non-surface treatment section21, the non-surface treatment section21is not surface-treated by the first preliminary conductive pattern32during, for example, the plasma treatment process for the substrate10. Thus, the non-surface treatment section21may have a surface energy greater than that of the insulating layer pattern42and the gate insulating layer20, which are exposed to the exterior.

The interlayer dielectric layer60that covers the organic thin film transistor T is formed on the substrate10, and a contact hole is formed through the interlayer dielectric layer60such that the top drain electrode36bis exposed. Further, the pixel electrode PE is formed on the interlayer dielectric layer60, and is electrically connected to the top drain electrode36bthrough the contact hole.

According to embodiments of the display substrate and the method of manufacturing the display substrate, when forming the organic semiconductor layer through an inkjet method, the bank pattern used for the organic semiconductor layer may be omitted. Accordingly, a photolithography process for the bank pattern may also be omitted, so that the manufacturing process of the display substrate may be simplified and the manufacturing cost of the display substrate may be reduced.