System internal latency measurements in realtime applications

Systems, methods, circuits and computer-readable mediums for system internal latency measurements in realtime applications are disclosed. In some implementations, a trigger signal is selected from a plurality of trigger signals for interrupting a processor of an integrated circuit system. The trigger signal includes a pulse having width. The system detects a rising edge of the pulse and starts a counter. The system detects a falling edge of the pulse and stops the counter. The system then compares a count of the counter with first and second values stored in first and second registers, respectively. The first value represents a minimum pulse width and the second value represents a maximum pulse width. The count is stored in the first or second register based on a result of the comparing.

TECHNICAL FIELD

This disclosure relates generally to system internal latency measurements.

BACKGROUND

In an example scenario, debugging a microcontroller system may involve determining the optimum frequency at which to run the microcontroller system. If the frequency is too low, the microcontroller system will not have time to execute internal tasks and system errors may occur (e.g., under-run error). If the frequency is too high, the current consumption increases significantly which may limit the battery life for portable devices.

SUMMARY

Systems, methods, circuits and computer-readable mediums for system internal latency measurements in realtime applications are disclosed. In some implementations, a trigger signal is selected from a plurality of trigger signals for interrupting a processor of an integrated circuit system. The trigger signal includes a pulse having a width. The system detects a rising edge of the pulse and starts a counter. The system detects a falling edge of the pulse and stops the counter. The system then compares a count of the counter with first and second values stored in first and second registers, respectively. The first value represents a captured minimum pulse width and the second value represents a captured maximum pulse width. The count is stored in the first or second register based on a result of the comparing.

Other implementations are directed to systems, methods, circuits and computer-readable mediums.

DETAILED DESCRIPTION

Systems, methods, circuits and computer-readable mediums are disclosed for system internal latency measurements in realtime applications.

FIG. 1is a block diagram illustrating communication system100between a central processing unit (CPU) and peripherals. System100includes CPU102and peripherals104a. . .104n. When peripheral104has completed an action, which requires CPU102activity, an interrupt request signal is generated by one or more of peripherals104a. . .104nand sent to CPU102. When CPU102has completed this interrupt initiation, CPU102will send an interrupt request clear signal to the requesting peripheral allowing the peripheral to release its interrupt request signal.

FIG. 2is a block diagram illustrating an interrupt generation circuit200. Circuit200includes latch202(e.g., an SR flip-flop) having a set input (S) coupled to a trigger signal and a reset input (R) coupled to an acknowledge signal. Some examples of trigger signals include but are not limited to: an interrupt request signal (IRQ), a direct memory access (DMA) transfer request signal, an event system event signal, software writing to a trigger bit in a registers and an interrupt acknowledge signal (IRQ flag going off). The interrupt acknowledge signal can be used to measure a pure software contribution to latency, as will be described in further detail below.

Some examples of an acknowledge signal include but are not limited to: an interrupt acknowledge signal (IRQ flag going off), DMA transfer complete signal, an event system event, software that sets an acknowledge bit in a register and an execution of a return from interrupt signal (RETI).

The operation of circuit200will now be described for an analog-to-digital converter (ADC) application. When the ADC completes a conversion, CPU102is notified to read the conversion result from the ADC. When the conversion is completed, the ADC will send a pulse to latch202to set the interrupt request signal high. When CPU102receives the interrupt request signal, and depending on the priority of the interrupt signal, CPU102can halt the previous interrupt execution and execute the ADC interrupt, or delay the interrupt execution while the previous interrupt request signal is not completed.

If in the system there is only the ADC interrupt enabled, the interrupt request pulse width represents the minimum time CPU102takes to initiate the execution of the interrupt routine, including the different bus latencies. If more interrupts are enabled, the interrupt request pulse width represents the time CPU102takes to start execution of the interrupt routine, including the different bus latencies and latencies related to previous interrupt execution. This time may vary depending on the interrupt number enabled in the system and the interrupt priority order. As described in reference toFIG. 3, a maximum and minimum hardware execution time can be automatically measured for an application without any intrusion.

FIG. 3is a block diagram of a system300for performing system internal latency measurements in realtime applications. System300is configured to measure minimum and maximum widths of a trigger signal pulse, as described in reference toFIG. 2. System300can be included in an integrated circuit system, such as a microcontroller system. In some implementations, system300includes circuit module301coupled to selecting device308. Circuit module301includes base counter302and a set of compare/capture units303aand303b. Base counter302includes PER register304, counter305and control logic306. Each compare/capture unit303aor303bincludes compare and capture registers313(CC0, CC1) and control logic307.

In operation, base counter302receives a selected trigger signal from selector308. In the example shown, the trigger signal is an interrupt request signal and selecting device308is a multiplexer that selects one of a plurality of interrupt request signals based on a trigger source. In some implementations, the trigger source is a set of bits (e.g., user-configured bits). One of a plurality of interrupt request signals is selected by the trigger source to be output from selecting device308. The example configuration shown inFIG. 3measures one interrupt request signal pulse width at a time. Multiple instances of circuit module301can be implemented in system300to measure multiple trigger signal pulse widths at the same time.

PER register304stores a maximum value for counter305. In response to a “count” signal provided by control logic306, counter305counts up from zero to the maximum value in PER register304or counts down from the value stored in PER register304to zero. Control logic306also provides a “load” signal for initializing counter305and a “clear” signal for clearing counter305. When the count of counter305is equal to zero the bottom signal (“ev”) is generated and sent to control logic306. When the count of counter305is equal to PER the top signal (“ev”) is generated and sent to control logic306.

The interrupt request signals are sent by peripherals309ato CPU310, sent by peripherals309bto event system311and sent by peripherals309cto direct memory access (DMA) controller312. DMA controller312transfers data between memories and peripherals309cwith minimal CPU intervention. Event system311is a routing network independent of data bus paths that allows peripherals309bto communicate directly with other peripherals without involving a central processing unit (CPU) or bus resources. Different triggers at the peripheral level can result in an event, which can be indicated by logic values, e.g., 1 or 0.

Compare and capture registers313of compare/capture units303aand/or303bcapture minimum and maximum pulse widths of the selected interrupt request signal. If only one of a minimum or maximum pulse width measurement is needed, then one register313of compare/capture unit303aand/or303bcan be used. In some implementations, a user can program the maximum value for counter305into PER register304by a user. Control logic307can be configured to generate a capture signal in response to a comparison between the count of counter305and the values in compare and capture registers313of Units0and1(CC0, CC1).

FIG. 4is a timing diagram illustrating interrupt pulse width measurement. In this example, a received interrupt request input signal is a pulse having width tp. On the rising edge of the pulse, counter305starts counting. On the falling edge of the pulse, the count of counter305is saved into one of the compare and capture registers313(CC0, CC1) depending on the values stored in registers313(CC0, CC1). When a capture is completed, counter305is cleared and waits for the next rising edge on the interrupt request input signal. The selection of CC1or CC0to store the count of counter305is described in reference toFIG. 5.

FIG. 5is a timing diagram illustrating capture of minimum and maximum interrupt pulse widths. In this example, the CC0register is used to store the minimum pulse width and the CC1register is used to store the maximum pulse width. After reset, CC0is initialized with the maximum counter value, which can be taken from PER register304(e.g., all bits1) and CC1is initialized with the minimum counter value (e.g., all bits0). On a falling edge of an interrupt request input signal, the values stored in registers CC0, CC1are compared against the count of counter305. If CC0content is greater than the count, then the count is stored in register CC0. If CC1content is less than the count, then the count is stored in register CC1. In this manner, the value in register CC0can only decrease and the value in register CC1can only increase.

FIG. 6is timing diagram illustrating DMA transfer of capture registers to memory. In some implementations, a DMA interface (not shown) can be implemented in circuit module301to transfer each response time measurement to a buffer (e.g., a ring buffer) using DMA controller312. In this way a statistical distribution of time consumptions can be identified during testing or during runtime. The user may find that there are only a few instances that excessive time consumption and can use this information to program PER register304to trigger an event when a longer than expected time consumption occurs. This event can, in turn, trigger a code break, which will enable the user to see what code was executing that caused the response time to be longer than expected. For example, the unexpected time consumption might be the result of a higher priority interrupt that unintentionally or unexpectedly was triggered. The DMA transfers can take place at capture times as shown inFIG. 6.

In some implementations, during runtime of an application (rather than debugging or testing) the statistical distribution of time consumptions can be transferred to the CPU or clock module to dynamically adjust the system clock frequency during runtime of an application.

FIG. 7is a timing diagram illustrating generating overflow/event interrupts. If during operation counter305reaches the maximum counter value this means an acknowledge signal was not sent or generated within an expected maximum time. This can result in an overflow interrupt (IRQ) being generated and/or an event being generated by, for example, event system311and sent to CPU310to take corrective action. A corrective action may be a system clock or a performance level (e.g., core voltage) increase.

FIG. 8is a flow diagram of a process of system internal latency measurements for realtime applications. In some implementations, process800can be implemented using system300, described in reference toFIG. 3. Process800can begin by selecting a trigger signal (802). The trigger signal can be, for example, an interrupt request signal generated by a peripheral. The trigger signal can be selected form a plurality of trigger signals by a selecting device, such as multiplexer. The selecting of the trigger signal can be based on user configured bits in a register.

Process800can continue by detecting a rising edge of a trigger signal pulse (804) and starting a counter (806), which starts counting up or down until a falling edge of the trigger signal pulse is detected (808), at which time the counter is stopped (810). The counter can be an n-bit up/down counter. A user can program the maximum count of the counter in a register (e.g., PER register304).

Process800can continue by comparing the count of the counter to values stored in maximum and minimum registers (812) and storing the count in one of the maximum or minimum registers based on the comparing. For example, after reset, a first register is initialized with a maximum counter value (e.g., all bits1) and second register is initialized with a minimum counter value (e.g., all bits0). On a falling edge of a trigger signal, the values stored in the first and second registers are compared against the count of the counter. If the first register value is greater than count, then the count is stored in the first register. If the value of the second register is less than count, then the count is stored in the second register. In this manner, the first register value can only decrease and the second register value can only increase.