Circuit for converting a voltage range of a logic signal

In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor has a source coupled to the output node and a gate coupled to a bias voltage. A current source circuit selectively biases the second MOS transistor to act as part of a source-follower circuit when the output node is to be in a second state. Additionally, a memory circuit has an input coupled to the output node, and an output. The memory circuit is configured to temporarily store a Boolean value of the output node when the output node transitions from the first state to the second state. Further, a discharging circuit is coupled to the output node and a second reference voltage. The discharging circuit is configured to temporarily provide a discharging path between the output node and the second reference voltage when the output node is transitioning from the first state to the second state. The discharging circuit has a first input coupled to the output of the memory circuit and a second input coupled to a control signal. The control signal indicates that the output node is to transition from the first state to the second state.

FIELD OF TECHNOLOGY

The present disclosure relates generally to digital circuits, and more particularly, to circuits for converting signals that vary in a first voltage range to signals that vary in a second voltage range.

DESCRIPTION OF THE RELATED ART

Typical current steering digital-to-analog converters (DACs) comprise a plurality of cells, each cell selectively supplying a current to a current summing line based on the digital value that is to be converted. The total current selectively supplied by all of the cells corresponds to the digital value, and different digital values will result in different amounts of total current.

For instance,FIG. 1is a block diagram of an example current steering DAC100having a plurality of cells104,108,112, and116. Each of the cells104,108,112,116includes an output coupled to a current summing line120. Digital data that is to be converted may be supplied to each of the cells104,108,112,116. Each of the cells104,108,112,116cells includes a current source and a switch that selectively, based on the digital data, applies current from the current source to the summing line120. The total current on the summing line120will correspond to the digital value, and different digital values will result in different amounts of total current on the summing line120.

FIG. 2is a block diagram of an example cell150that may be utilized in the current steering DAC100ofFIG. 1. The cell150includes a current source154and a switch comprising a p-channel metal oxide semiconductor (PMOS) transistor158and a PMOS transistor162. A source of the transistor158is coupled to the current source154, and a drain of the transistor158is coupled to the summing line120. A source of the transistor162is coupled to the current source154, and a drain of the transistor158is coupled to ground. The cell150also includes logic166that receives the digital data that is to be converted and generates a switch control signal based on the digital data. The switch control signal is coupled to a gate of the transistor158and is coupled to an input of an inverter170. An output of the inverter170is coupled to a gate of the transistor162.

In operation, the logic166will generate either a low signal (e.g., 0 volts) or a high signal (e.g., 1.2 volts) depending upon a value of the digital data. If a value of the digital data results in the logic166generating a low signal, the transistor158will be turned ON. Additionally, the inverter170will generate a high signal, and thus the transistor162will be turned OFF. This will result in the current source154being coupled to the summing line120. Thus, the current source154will supply its current to the summing line120. On the other hand, if a value of the digital data results in the logic166generating a high signal, the transistor158will be turned OFF. Additionally, the inverter170will generate a low signal, and thus the transistor162will be turned ON. This will result in the current source154being coupled to ground. Thus, the current source154will not supply any of its current to the summing line120.

SUMMARY OF THE DISCLOSURE

In one embodiment, a circuit to convert a first logic signal having a first range to a second logic signal having a second range comprises a first metal oxide semiconductor (MOS) transistor to selectively couple an output node to a first reference voltage when the output node is to be in a first state, and a second MOS transistor having a source coupled to the output node and a gate coupled to a bias voltage. The circuit also comprises a current source circuit to selectively bias the second MOS transistor to act as part of a source-follower circuit when the output node is to be in a second state. Additionally, the circuit comprises a memory circuit having an input coupled to the output node and an output, the memory circuit configured to temporarily store a value indicative of the output node in the first state when the output node transitions from the first state to the second state.

Further, the circuit comprises a discharging circuit coupled to the output node and a second reference voltage. The discharging circuit is configured to temporarily provide a discharging path between the output node and the second reference voltage when the output node is transitioning from the first state to the second state. The discharging circuit has a first input coupled to the output of the memory circuit and a second input coupled to a control signal, wherein the control signal is to indicate that the output node is to transition from the first state to the second state.

In another embodiment, a circuit to convert a first logic signal having a first range to a pair of complementary second logic signals having a second range includes a MOS transistor to selectively couple a first output node to a first reference voltage when the first output node is to be in a first state, and a second MOS transistor having a source coupled to the first output node and a gate coupled to a bias voltage. The circuit additionally includes a third MOS transistor to selectively couple a second output node to the first reference voltage when the second output node is to be in the first state, and a fourth MOS transistor having a source coupled to the second output node and a gate coupled to the bias voltage.

The circuit also includes a current source circuit to selectively bias the second MOS transistor to act as part of a first source-follower circuit when the first output node is to be in a second state and to selectively bias the fourth MOS transistor to act as part of a second source-follower circuit when the second output node is to be in the second state. Further, the circuit includes a memory circuit having a first input coupled to the first output node, a second input coupled to the second output node, a first output, and a second output, the memory circuit configured to temporarily store a first value indicative of the first output node in the first state when the first output node transitions from the first state to the second state and to temporarily store a second value indicative of the second output node in the first state when the second output node transitions from the first state to the second state.

Still further, the circuit includes a first discharging circuit coupled to the first output node and a second reference voltage. The first discharging circuit is configured to temporarily provide a discharging path between the first output node and the second reference voltage when the first output node is transitioning from the first state to the second state. The first discharging circuit has a first input coupled to the first output of the memory circuit and a second input coupled to a first control signal, wherein the first control signal indicating that the first output node is to transition from the first state to the second state. Additionally, the circuit includes a second discharging circuit coupled to the second output node and the second reference voltage. The second discharging circuit is configured to temporarily provide a discharging path between the second output node and the second reference voltage when the second output node is transitioning from the first state to the second state. The second discharging circuit has a first input coupled to the second output of the memory circuit and a second input coupled to a second control signal, wherein the second control signal indicating that the second output node is to transition from the first state to the second state.

In yet another embodiment, a circuit to convert a first logic signal having a first range to at least one second logic signal having a second range comprises a p-channel metal oxide semiconductor (PMOS) transistor having a gate coupled to a control signal, a source coupled to a first reference voltage, and a drain coupled to an output node. The circuit also comprises an n-channel metal oxide semiconductor (NMOS) transistor having a source coupled to the output node and a gate coupled to a bias voltage. The circuit additionally comprises a current source circuit having an input coupled to the control signal to selectively bias the first NMOS transistor to act as part of a source-follower circuit when the control signal is HIGH.

Further, the circuit comprises a memory circuit having a first input coupled to the output node and an output, the memory circuit configured to temporarily store a representative value associated with the output node when the control signal changes from LOW to HIGH. Still further, the circuit comprises a discharging circuit coupled to the output node and a second reference voltage, the discharging circuit configured to temporarily provide a discharging path between the output node and the second reference voltage after the control signal changes from LOW to HIGH. The discharging circuit having a first input coupled to the output of the memory circuit and a second input coupled to the control signal. A steady-state voltage of the output node when the control signal is HIGH is a voltage within the range 100 millivolts and 350 millivolts, inclusive.

In still another embodiment, a cell of a current steering digital-to-analog converter (DAC) includes a cell current source, a MOS transistor coupled in series with the current source and coupled to a current summing line, and a second MOS transistor coupled in series with the current source and coupled to a reference node.

The cell of the DAC also includes a driver circuit having an input, a first output coupled to a gate of the first MOS transistor, and a second output coupled to a gate of the second MOS transistor. The driver circuit comprises a third MOS transistor to selectively couple the first output of the driver circuit to a first reference voltage when the first output of the driver circuit is to be in a first state, and a fourth MOS transistor having a source coupled to the first output of the driver circuit and a gate coupled to a bias voltage. The driver circuit additionally comprises a fifth MOS transistor to selectively couple the second output of the driver circuit to the first reference voltage when the second output of the driver circuit is to be in the first state, and a sixth MOS transistor having a source coupled to the second output of the driver circuit and a gate coupled to the bias voltage.

The driver circuit further comprises a driver circuit current source circuit to selectively bias the fourth MOS transistor to act as part of a first source-follower circuit when the first output of the driver circuit is to be in a second state and to selectively bias the sixth MOS transistor to act as part of a second source-follower circuit when the second output of the driver circuit is to be in the second state. The driver circuit still further comprises a memory circuit having a first input coupled to the first output of the driver circuit, a second input coupled to the second output of the driver circuit, a first output, and a second output. The memory circuit is configured to temporarily store a first representative value associated with the first output of the driver circuit when the first output of the driver circuit transitions from the first state to the second state and to temporarily store a second representative value associated with the second output of the driver circuit when the second output of the driver circuit transitions from the first state to the second state.

Still further, the driver circuit comprises a first discharging circuit coupled to the first output of the driver circuit and a second reference voltage. The first discharging circuit is configured to temporarily provide a discharging path between the first output of the driver circuit and the second reference voltage when the first output of the driver circuit is transitioning from the first state to the second state. The first discharging circuit has a first input coupled to the first output of the memory circuit and a second input coupled to a first control signal, wherein the first control signal indicating that the first output of the driver circuit is to transition from the first state to the second state. Additionally, the driver circuit comprises a second discharging circuit coupled to the second output of the driver circuit and the second reference voltage. The second discharging circuit is configured to temporarily provide a discharging path between the second output of the driver circuit and the second reference voltage when the second output of the driver circuit is transitioning from the first state to the second state. The second discharging circuit has a first input coupled to the second output of the memory circuit and a second input coupled to a second control signal, wherein the second control signal indicating that the second output of the driver circuit is to transition from the first state to the second state.

A steady-state voltage of the first output of the driver circuit in the second state is a voltage within the range 100 millivolts to 350 millivolts, inclusive. A steady-state voltage of the second output of the driver circuit in the second state is a voltage within the range 100 millivolts to 350 millivolts, inclusive.

DETAILED DESCRIPTION

FIG. 3is a block diagram of an example cell200that may be utilized in a current steering DAC. The cell200includes a current source204and a switch comprising a p-channel metal oxide semiconductor (PMOS) transistor208and a PMOS transistor212. A source of the transistor208is coupled to the current source204, and a drain of the transistor208is coupled to a summing line216. A source of the transistor212is coupled to the current source204, and a drain of the transistor212is coupled to ground. The cell200also includes a driver circuit220that receives an input signal and generates two output signals based on the input signal. The input signal is indicative of whether the current source204should be coupled to or isolated from the summing line216. The input signal may be generated by logic such as the logic block166ofFIG. 2.

The two output signals control the transistors208,212to selectively couple the current source204to the summing line216. One of the output signals, OUT, is coupled to a gate of the transistor208. The output signal, OUTB, is coupled to a gate of the transistor212. The input signal coupled to the driving circuit220will vary between voltages levels for a typical CMOS device. For example, the input signal may vary between 0 volts and 1.2 volts. An input signal of approximately 0 volts may indicate that the current source204should be coupled to the summing line216, and an input signal of approximately 1.2 volts may indicate that the current source204should be isolated from the summing line216, for example. Alternatively, an input signal of approximately 1.2 volts may indicate that the current source204should be coupled to the summing line216, and an input signal of approximately 0 volts may indicate that the current source204should be isolated from the summing line216, for example.

The driving circuit220generates the output signals such that they vary in a range that is less than the range of that of the input signal. For example, if the input signal varies between approximately 0 volts and 1.2 volts, the output signals may vary between approximately 300 millivolts and 1.2 volts, for example, or some other range. It has been found that, in at least some implementations, using such a reduced range reduces charge injection associated with the transistors208,212. It also has been found that, in at least some implementations, using such a reduced range tends to keep the transistors208,212biased in a desired region, such as in saturation.

In operation, when the input signal is HIGH (in the standard CMOS range), the driver circuit220will generate the signal OUT to be HIGH (in the reduced range) and will generate the signal OUTB to be LOW (in the reduced range). Similarly, when the input signal is LOW (in the standard CMOS range), the driver circuit220will generate the signal OUT to be LOW (in the reduced range) and will generate the signal OUTB to be HIGH (in the reduced range). As a specific example provided merely for explanatory purposes, if the input signal is 1.2 volts, the driver circuit220will generate the signal OUT to be 1.2 volts and will generate the signal OUTB to be 300 millivolts. Continuing with this example, if the input signal is 0 volts, the driver circuit220will generate the signal OUT to be 300 millivolts and will generate the signal OUTB to be 1.2 volts.

FIG. 4is a circuit diagram of one example of a driving circuit300that may be used as the driving circuit220ofFIG. 3. The driving circuit300includes a flip flop304. The flip flop304includes a data input coupled to the input signal and a clock input coupled to a clock signal. The clock signal may be a clock signal of a DAC for example. The flip flop304generates a Q signal and a QB signal. The Q signal corresponds to the input signal, and the QB signal corresponds to a logical complement of the input signal.

The driving circuit300also includes a PMOS transistor308having a source coupled to a reference voltage VDD, a drain coupled to a node OUT, and a gate coupled to the QB signal. The reference voltage VDDmay be 1.2 volts, for example, or any other suitable reference voltage. An n-channel metal oxide semiconductor (NMOS) transistor310has a drain coupled to the node OUT and a gate coupled to the QB signal. A source of the NMOS transistor310is coupled to an input node of a current source312. An output node of the current source312is coupled to a reference voltage VSS. The reference voltage VSSmay be ground, for example, or any other suitable reference voltage. An NMOS transistor314has a drain coupled to the reference voltage VDD, a source coupled to the node OUT, and a gate coupled to a bias voltage (BIAS).

A PMOS transistor318has a source coupled to VDD, a drain coupled to a node OUTB, and a gate coupled to the Q signal. An NMOS transistor320has a drain coupled to the node OUTB, a source coupled to the input node of a current source312, and a gate coupled to the Q signal. An NMOS transistor324has a drain coupled to the reference voltage VDD, a source coupled to the node OUTB, and a gate coupled to the BIAS voltage.

The driving circuit300further includes a memory circuit328. The memory circuit328is configured to temporarily hold the Boolean value of the node OUT so that when the node OUT is transitioning from a HIGH value to a LOW value, the stored value temporarily remains HIGH. One example memory circuit will be described below, but one of ordinary skill in the art will recognize that any of a variety of memory circuits may be utilized.

A discharging circuit330receives an output from the memory circuit228as well as the QB signal. The discharging circuit330is configured to temporarily provide a discharging path from the node OUT to the reference voltage VSSwhen the node OUT is transitioning from a HIGH value to a LOW value. In particular, the discharging circuit330is configured to provide the discharging path when QB is HIGH and when the output of the memory circuit328has not yet changed in response to the node OUT transitioning from HIGH to LOW. One example discharging circuit will be described below, but one of ordinary skill in the art will recognize that any of a variety of discharging circuits may be utilized.

The driving circuit300further includes a memory circuit332and a discharging circuit334which may be the same as or similar to the memory circuit228and the discharging circuit330, respectively. For instance, the memory circuit332is configured to temporarily hold the Boolean value of the node OUTB so that when the node OUTB is transitioning from a HIGH value to a LOW value, the stored value temporarily remains HIGH. Also, the discharging circuit334is configured to temporarily provide a discharging path from the node OUTB to the reference voltage VSSwhen the node OUTB is transitioning from a HIGH value to a LOW value. In particular, the discharging circuit334is configured to provide the discharging path when Q is HIGH and when the output of the memory circuit332has not yet changed in response to the node OUTB transitioning from HIGH to LOW.

Operation of the driving circuit300will now be described. First, assume that the input signal is HIGH, the Q signal is HIGH, and the QB signal is LOW. In this state, the transistor308is ON, and the transistor310is OFF. Thus, the node OUT is approximately VDD. Also, the memory circuit328stores the Boolean value HIGH because the node OUT is approximately VDD. Further, the discharging circuit330isolates the node OUT from the discharging path to the reference voltage VSSof the discharging circuit330.

Additionally, the transistor318is OFF, and the transistor320is ON. Further, the transistor324is biased by current drawn by the current source312. As will be described in more detail below, the node OUTB is some desired voltage above VSS, and this voltage will be referred to as VMIN.

Now, if the input signal transitions to LOW, the Q signal will transition to LOW and the QB signal will transition to HIGH in response to a clock event such as a rising edge. Thus, the transistor308will turn OFF and the transistor310will turn ON. Also, the transistor318will turn ON and the transistor320will turn OFF. This will cause the current drawn by the current source312to flow through the transistor314.

When the signal QB initially goes HIGH, the output of the memory circuit328does not change. As a result, the discharging circuit330creates a discharging path between the node OUT and VSS. This causes the voltage of the node OUT to fall towards VSS. Eventually, the output of the memory circuit328will change, causing the discharging circuit330to isolate the node OUT from the discharging path of the discharging circuit330.

The transistor314and the current source312act as an NMOS source-follower circuit. The eventual voltage of the node OUT will be the voltage of BIAS minus VGSof the transistor314. The node OUT can be made to fall to the desired voltage VMINby appropriately selecting BIAS in light of a known value of VGSof the transistor314when the current of the current source312flows through the transistor314. For example, BIAS could be set as VMIN+VGS. In one specific implementation, the voltage VMINmay be approximately 300 millivolts. It is to be understood, however, that other values of VMINmay be utilized as well. For example, the voltage VMINmay be approximately 100 millivolts, 125 millivolts, 150 millivolts, 175 millivolts, 200 millivolts, 225 millivolts, 250 millivolts, 275 millivolts, 325 millivolts, 350 millivolts, etc. Thus, the voltage BIAS and the current from current source320can be selected to provide a desired value of VMIN.

With regard to the node OUTB, the transistor318turns ON, and the transistor320turns OFF. Thus, the node OUTB will be pulled to approximately VDD. In steady state, the memory circuit332stores the Boolean value HIGH because the node OUTB is approximately VDD. Further, the discharging circuit334isolates the node OUTB from the discharging path to the reference voltage VSSof the discharging circuit334.

Now, if the input signal transitions to HIGH, the Q signal will transition to HIGH and the QB signal will transition to LOW in response to a clock event such as a rising edge. Thus, the transistor318will turn OFF and the transistor320will turn ON. Also, the transistor308will turn ON and the transistor310will turn OFF. This will cause the current drawn by the current source312to flow through the transistor324.

When the signal Q initially goes HIGH, the output of the memory circuit332does not change. As a result, the discharging circuit334creates a discharging path between the node OUTB and VSS. This causes the voltage of the node OUTB to fall towards VSS. Eventually, the output of the memory circuit332will change, causing the discharging circuit334to isolate the node OUTB from the discharging path of the discharging circuit334.

The transistor324and the current source312act as an NMOS source-follower circuit. The eventual voltage of the node OUT will be the voltage of BIAS minus VGSof the transistor324. The node OUT can be made to fall to the desired voltage VMINby appropriately selecting BIAS in light of a known value of VGSof the transistor324when the current of the current source312flows through the transistor324. For example, BIAS could be set as VMIN+VGS. In one specific implementation, the voltage VMINmay be approximately 300 millivolts. It is to be understood, however, that other values of VMINmay be utilized as well.

With regard to the node OUT, the transistor308turns ON, and the transistor310turns OFF. Thus, the node OUT will be pulled to approximately VDD.

As can be seen in the example driving circuit300, the current of the current source312is selectively directed to either bias the transistor314or the transistor324. In other words, only one of the transistors312and324is biased at a time. This may help to keep overall power usage down in a current steering DAC with many cells.

One of ordinary skill in the art will recognize many variations to the example circuit300. For example, if a complement output is not needed, portions of the circuit300may be omitted. For instance, the transistors318and320, the memory circuit332, and the discharging circuit334could be omitted and the drain of the transistor320could be coupled to a diverting node such as VDD. Also, the transistor320could be omitted and the current source312could be configured to draw current only if QB is HIGH, for example.

As another example, the flip-flop304may be omitted. For instance, the input signal could be coupled to the gates of the transistors318and320and to the discharging circuit334. Also, the circuit could include an inverter having an input coupled to the input signal and an output coupled to the gates of the transistors308and310and to the discharging circuit330. Still further, in some implementations the output node OUTB may track the input signal and/or the output node OUT may be complementary to the input signal. In such implementations, the control signals Q and QB may be swapped. For example, the control signal Q could be coupled to the gates of transistors308and310and to the discharging circuit330. Similarly, the control signal QB could be coupled to the gates of transistors318and320and to the discharging circuit334. Still further, separate bias voltages could be used for the transistors314and324. This could be useful, for example, if different VMINvalues for the node OUT and the node OUTB are desired.

As yet another variation, the memory circuit328may be coupled to the node OUTB and may be configured to temporarily hold the Boolean value of the node OUTB so that when the node OUTB is transitioning from a LOW value to a HIGH value, the stored value temporarily remains LOW. Also, the discharging circuit330may be coupled to the signal Q or the QB signal and may be configured to temporarily provide a discharging path from the node OUT to the reference voltage VSSwhen the node OUTB is transitioning from a LOW value to a HIGH value. In particular, the discharging circuit330may be configured to provide the discharging path when Q is LOW or QB is HIGH and when the output of the memory circuit328has not yet changed in response to the node OUTB transitioning from LOW to HIGH. In this implementation, the discharging circuit330still acts to temporarily provide a discharging path from the node OUT to the reference voltage VSSwhen the node OUT is transitioning from HIGH to LOW because this occurs when OUTB is transitioning from LOW to HIGH. Similarly, the memory circuit332may be coupled to the node OUT and may be configured to temporarily hold the Boolean value of the node OUT so that when the node OUT is transitioning from a LOW value to a HIGH value, the stored value temporarily remains LOW. Also, the discharging circuit334may be coupled to the signal Q or the signal QB and may be configured to temporarily provide a discharging path from the node OUTB to the reference voltage VSSwhen the node OUT is transitioning from a LOW value to a HIGH value. In particular, the discharging circuit334may be configured to provide the discharging path when Q is HIGH or QB is LOW and when the output of the memory circuit332has not yet changed in response to the node OUT transitioning from LOW to HIGH. The discharging circuit334still acts to temporarily provide a discharging path from the node OUTB to the reference voltage VSSwhen the node OUTB is transitioning from HIGH to LOW because this occurs when OUT is transitioning from LOW to HIGH.

One or ordinary skill in the art will recognize many other variations.

FIG. 5is a circuit diagram of another example driving circuit350that may be used as the driving circuit220ofFIG. 3. The driving circuit350includes many of the same elements as the driving circuit300ofFIG. 4, and these elements are like numbered. Additionally, the driving circuit350includes particular example implementations of the memory circuit328, the discharging circuit330, the memory circuit332, and the discharging circuit334. Of course, it is to be understood that many other implementations of the memory circuit328, the discharging circuit330, the memory circuit332, and the discharging circuit334additionally may be utilized as well, and one of ordinary skill in the art will recognize many other such implementations.

In the driving circuit350, the memory circuit328and the memory circuit332are implemented as a latch circuit352. The latch circuit352comprises a PMOS transistor354having a source coupled to VDD, a drain coupled to a node356, and a gate coupled to the OUT node. An NMOS transistor358has a drain coupled to the node356and a source coupled to VSS. An inverter360has an input coupled to the node356. The latch circuit further comprises a PMOS transistor362having a source coupled to VDD, a drain coupled to a node366, and a gate coupled to the OUTB node. An NMOS transistor368has a drain coupled to the node366and a source coupled to VSS. An inverter370has an input coupled to the node366. A gate of the NMOS transistor358is coupled to the node366and a gate of the NMOS transistor368is coupled to the node356.

In the driving circuit350, the discharging circuit330is implemented as a circuit368. The discharging circuit368comprises an NMOS transistor372having a drain coupled to the OUT node and a gate coupled to an output of the inverter360. An NMOS transistor374has a drain coupled to a source of the NMOS transistor372, a source coupled to VSS, and a gate coupled to the QB signal.

Similarly, in the driving circuit350, the discharging circuit334is implemented as a circuit376. The discharging circuit376comprises an NMOS transistor380having a drain coupled to the OUTB node and a gate coupled to an output of the inverter370. An NMOS transistor382has a drain coupled to a source of the NMOS transistor380, a source coupled to VSS, and a gate coupled to the Q signal.

In operation, when the input signal is HIGH in steady state, Q is HIGH and QB is LOW. Thus, the node OUT is at approximately VDDand the node OUTB is at approximately VMIN. The PMOS transistor362is ON, thus the node366is at approximately VDD. Thus, the transistor358is ON. Also, the transistor354is OFF. As a result, the node356is approximately at VSS. Thus, the output of the inverter360is HIGH and the output of the inverter370is LOW.

Because the output of the inverter360is HIGH, the transistor372is ON. But because the QB signal is LOW, the transistor374is OFF. Thus the discharging circuit368isolates the node OUT from VSS. Similarly, because the output of the inverter370is LOW, the transistor380is OFF and the discharging circuit376isolates the node OUTB from the discharging path to VSS.

When the input signal transitions from HIGH to LOW, Q will transition from HIGH to LOW and QB will transition from LOW to HIGH in response to a clock event such as a rising edge. This will cause the transistor374to turn ON which in turn creates a discharging path between the node OUT and VSS. This causes voltage at the node OUT to fall towards VSS. This will eventually cause the transistor354to turn ON and pull the node356towards VDD. Then, the output of the inverter360will transition from HIGH to LOW, causing the transistor372to turn OFF. This again isolates the discharging path of the discharging circuit368from the node OUT.

As described with respect toFIG. 4, when the signal Q goes LOW, the transistor318turns ON and the node OUTB rises toward VDD. This will cause the transistor362to turn OFF and the node366is isolated from VDD. Also, as voltage at the node356rises, the transistor368will turn ON pulling the node366toward VSS. Eventually, the output of the inverter370will transition from LOW to HIGH. This turns the transistor380ON. But because the signal Q is low, the transistor382is OFF and the node OUTB remains isolated from VSS.

When the circuit350reaches steady state, the node356is HIGH and the node366is LOW. Thus, the transistor372is OFF and the transistor380is ON. Because the transistor372is OFF, the discharging circuit368isolates the node OUT from the discharging path to VSS. Because the Q signal is LOW, the transistor382is OFF and the discharging circuit376isolates the node OUT from VSS.

When the input signal transitions from LOW to HIGH, Q will transition from LOW to HIGH and QB will transition from HIGH to LOW in response to a clock event such as a rising edge. This will cause the transistor382to turn ON which in turn creates a discharging path between the node OUTB and VSS. This causes voltage at the node OUTB to fall towards VSS. This will eventually cause the transistor362to turn ON and pull the node366towards VDD. Then, the output of the inverter370will transition from HIGH to LOW, causing the transistor380to turn OFF. This again isolates the discharging path of the discharging circuit376from the node OUTB.

As described with respect toFIG. 4, when the signal QB goes LOW, the transistor308turns ON and the node OUT rises toward VDD. This will cause the transistor354to turn OFF and the node356is isolated from VDD. Also, as voltage at the node366rises, the transistor358will turn ON pulling the node356toward VSS. Eventually, the output of the inverter360will transition from LOW to HIGH. This turns the transistor372ON. But because the signal QB is low, the transistor374is OFF and the node OUT remains isolated from VSS.

One or ordinary skill in the art will recognize many variations to the circuit350are possible such as variations discussed above with respect toFIG. 4.

A circuit such as the circuit300and the circuit350may be utilized in a variety of devices that require the conversion of a logic signal into a signal having a reduced range. As just one example, such a circuit may be utilized in current steering DACs. More generally, such a circuit may be utilized in a variety of electronic devices such as communication devices, computation devices, storage devices, networking devices, measurement devices, etc. Referring now toFIGS. 6A-6H, a few specific examples of devices that may utilize a circuit such as such as the circuit300or the circuit350will be described.

For example, referring toFIG. 6A, a hard disk drive500may include a circuit such as the circuit300or the circuit350. For example, signal processing and/or control circuits, which are generally identified inFIG. 6Aat502, may include a circuit such as the circuit300or the circuit350. For instance, signal processing and/or control circuits502may include one or more current steering DACs. In some implementations, signal processing and/or control circuit502and/or other circuits (not shown) in HDD500may process data, perform coding and/or encryption, perform calculations, and/or format data that is output to and/or received from a magnetic storage medium506.

HDD500may communicate with a host device (not shown) such as a computer, mobile computing devices such as personal digital assistants, cellular phones, media or MP3 players and the like, and/or other devices via one or more wired or wireless communication links508. HDD500may be connected to memory509, such as random access memory (RAM), a low latency nonvolatile memory such as flash memory, read only memory (ROM) and/or other suitable electronic data storage.

Referring now toFIG. 6B, a circuit such as the circuit300or the circuit350may be utilized in a digital versatile disc (DVD) drive510. A circuit such as the circuit300or the circuit350may be utilized in either or both signal processing and/or control circuits, which are generally identified inFIG. 6Bat512, and/or mass data storage518of DVD drive510. For instance, signal processing and/or control circuits512and/or the mass storage device518may include one or more current steering DACs. Signal processing and/or control circuit512and/or other circuits (not shown) in DVD510may process data, perform coding and/or encryption, perform calculations, and/or format data that is read from and/or data written to an optical storage medium516. In some implementations, signal processing and/or control circuit512and/or other circuits (not shown) in DVD510can also perform other functions such as encoding and/or decoding and/or any other signal processing functions associated with a DVD drive.

DVD drive510may communicate with an output device (not shown) such as a computer, television or other device via one or more wired or wireless communication links517. DVD510may communicate with mass data storage518that stores data in a nonvolatile manner. Mass data storage518may include a hard disk drive (HDD) such as that shown inFIG. 6B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″DVD510may be connected to memory519, such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage.

Referring toFIG. 6C, a circuit such as the circuit300or the circuit350may be utilized in a high definition television (HDTV)520. The HDTV520includes signal processing and/or control circuits, which are generally identified inFIG. 6Cat522, a WLAN interface529, and a mass data storage527. A circuit such as the circuit300or the circuit350may be utilized in the WLAN interface529or the signal processing circuit and/or control circuit522, for example. For instance, the WLAN interface529and/or signal processing and/or control circuits522may include one or more current steering DACs. HDTV520receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display526. In some implementations, signal processing circuit and/or control circuit522and/or other circuits (not shown) of HDTV520may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required.

HDTV520may communicate with mass data storage527that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. The mass data storage527may include one or more hard disk drives (HDDs) and/or one or more digital versatile disks (DVDs). At least one HDD may have the configuration shown inFIG. 6Aand/or at least one DVD may have the configuration shown inFIG. 6B. One or more of the HDDs may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″HDTV520may be connected to memory528such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. HDTV520also may support connections with a WLAN via a WLAN network interface529.

Referring now toFIG. 6D, a circuit such as the circuit300or the circuit350may be utilized in a control system of a vehicle530. In some implementations, a circuit such as the circuit300or the circuit350may be utilized by a powertrain control system532that receives inputs from one or more sensors such as temperature sensors, pressure sensors, rotational sensors, airflow sensors and/or any other suitable sensors and/or that generates one or more output control signals such as engine operating parameters, transmission operating parameters, and/or other control signals. For instance, the powertrain control system532may include one or more current steering DACs.

A circuit such as the circuit300or the circuit350may be utilized in other control systems540of vehicle530. For instance, control systems540may include one or more current steering DACs. Control system540may likewise receive signals from input sensors542and/or output control signals to one or more output devices544. In some implementations, control system540may be part of an anti-lock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc and the like. Still other implementations are contemplated.

Powertrain control system532may communicate with mass data storage546that stores data in a nonvolatile manner. Mass data storage546may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown inFIG. 6Aand/or at least one DVD may have the configuration shown inFIG. 6B. One or more of the HDDs may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″Powertrain control system532may be connected to memory547such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Powertrain control system532also may support connections with a WLAN via a WLAN network interface548. The WLAN interface548may include a circuit such as the circuit300or the circuit350. For instance, the WLAN interface548may include one or more current steering DACs. The control system540may also include mass data storage, memory and/or a WLAN interface (all not shown).

Referring now toFIG. 6E, a circuit such as the circuit300or the circuit350may be utilized in a cellular phone550that may include a cellular antenna551. The cellular phone550includes signal processing and/or control circuits, which are generally identified inFIG. 6Eat552, a WLAN interface568, and a mass data storage564. A circuit such as the circuit300or the circuit350may be utilized in the signal processing and/or control circuits552and/or the WLAN interface568, for example. For instance, the signal processing and/or control circuits and/or the WLAN interface568may include one or more current steering DACs. In some implementations, cellular phone550includes a microphone556, an audio output558such as a speaker and/or audio output jack, a display560and/or an input device562such as a keypad, pointing device, voice actuation and/or other input device. Signal processing and/or control circuits552and/or other circuits (not shown) in cellular phone550may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular phone functions.

Cellular phone550may communicate with mass data storage564that stores data in a nonvolatile manner such as optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown inFIG. 6Aand/or at least one DVD may have the configuration shown inFIG. 6B. At least one HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″Cellular phone550may be connected to memory566such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Cellular phone550also may support connections with a WLAN via a WLAN network interface568.

Referring now toFIG. 6F, a circuit such as the circuit300or the circuit350may be utilized in a set top box580. The set top box580includes signal processing and/or control circuits, which are generally identified inFIG. 6Fat584, a WLAN interface596, and a mass data storage device590. A circuit such as the circuit300or the circuit350may be utilized in the signal processing and/or control circuits584and/or the WLAN interface596, for example. For instance, the signal processing and/or control circuits584and/or the WLAN interface596may include one or more current steering DACs. Set top box580receives signals from a source such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display588such as a television and/or monitor and/or other video and/or audio output devices. Signal processing and/or control circuits584and/or other circuits (not shown) of the set top box580may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function.

Set top box580may communicate with mass data storage590that stores data in a nonvolatile manner. Mass data storage590may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown inFIG. 6Aand/or at least one DVD may have the configuration shown inFIG. 6B. At least one HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″Set top box580may be connected to memory594such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Set top box580also may support connections with a WLAN via a WLAN network interface596.

Referring now toFIG. 6G, a circuit such as the circuit300or the circuit350may be utilized in a media player600. The media player600may include signal processing and/or control circuits, which are generally identified inFIG. 6Gat604, a WLAN interface616, and a mass data storage device610. A circuit such as the circuit300or the circuit350may be utilized in the signal processing and/or control circuits604and/or the WLAN interface616, for example. For instance, the signal processing and/or control circuits604and/or the WLAN interface616may include one or more current steering DACs. In some implementations, media player600includes a display607and/or a user input608such as a keypad, touchpad and the like. In some implementations, media player600may employ a graphical user interface (GUI) that typically employs menus, drop down menus, icons and/or a point-and-click interface via display607and/or user input608. Media player600further includes an audio output609such as a speaker and/or audio output jack. Signal processing and/or control circuits604and/or other circuits (not shown) of media player600may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function.

Media player600may communicate with mass data storage610that stores data such as compressed audio and/or video content in a nonvolatile manner. In some implementations, the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats. The mass data storage may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown inFIG. 6Aand/or at least one DVD may have the configuration shown inFIG. 6B. At least one HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″Media player600may be connected to memory614such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Media player600also may support connections with a WLAN via a WLAN network interface616. Still other implementations in addition to those described above are contemplated.

Referring toFIG. 6H, a circuit such as the circuit300or the circuit350may be utilized in a Voice over Internet Protocol (VoIP) phone650that may include an antenna654, signal processing and/or control circuits658, a wireless interface662, and a mass data storage666. A circuit such as the circuit300or the circuit350may be utilized in the signal processing and/or control circuits658and/or the wireless interface662, for example. For instance, the signal processing and/or control circuits658and/or the wireless interface662may include one or more current steering DACs. In some implementations, VoIP phone650includes, in part, a microphone670, an audio output674such as a speaker and/or audio output jack, a display monitor678, an input device682such as a keypad, pointing device, voice actuation and/or other input devices, and a Wireless Fidelity (Wi-Fi) communication module662. Signal processing and/or control circuits658and/or other circuits (not shown) in VoIP phone650may process data, perform coding and/or encryption, perform calculations, format data and/or perform other VoIP phone functions.

VoIP phone650may communicate with mass data storage666that stores data in a nonvolatile manner such as optical and/or magnetic storage devices, for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown inFIG. 6Aand/or at least one DVD may have the configuration shown inFIG. 6B. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″VoIP phone650may be connected to memory686, which may be a RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. VoIP phone650is configured to establish communications link with a VoIP network (not shown) via Wi-Fi communication module662.

While the present invention has been described with reference to specific examples, which are intended to be illustrative only and not to be limiting of the invention, it will be apparent to those of ordinary skill in the art that changes, additions or deletions in addition to those explicitly described above may be made to the disclosed embodiments without departing from the spirit and scope of the invention.