Memory and storage device utilizing the same

A storage device including a memory and a reading circuit is disclosed. The memory includes a plurality of word lines, a first bit line, a second bit line, a third bit line, and a plurality of cells. The word lines are sequentially disposed in parallel. The first, the second, and the third bit lines are sequentially disposed in parallel and vertical with the word lines. Each cell corresponds to one word line and one bit line. The word line, which corresponds to the cell corresponding to the first bit line, differs from the word line, which corresponds to the cell corresponding to the second bit line. The read circuit is coupled to the memory for reading the data stored in the memory.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to an arrangement structure of cells, and more particularly to an arrangement structure of cells of a storage device.

2. Description of the Related Art

FIG. 1is a schematic diagram of a conventional arrangement for cells. When the word line WL is asserted, the transistors in the cells C0˜C3are turned on. Thus, the bit lines BL0˜BL3are capable of tramsmitting a corresponding level. Referring toFIG. 1, when the transistors in the cells C0˜C3are turned on, the bit line BL1transmits a high level and the bit lines BL0, BL2, and BL3transmit a low level (e.g. VSS).

However, coupling capacitances exist between the bit line BL1and the neighboring bit line, such as BL0and BL2. The bit line BL1may transmits an abnormal level (e.g. low level) due to the coupling capacitances. To solve the problem, the conventional method utilizes pull-up loads to connect the bit lines. However, costs are increased. Furthermore, unnecessary current paths are formed due to the extra pull-up loads. Thus, power consumption is increased.

BRIEF SUMMARY OF THE INVENTION

Storage devices are provided. An exemplary embodiment of a storage device comprises a memory and a reading circuit. The memory comprises a plurality of word lines, a first bit line, a second bit line, a third bit line, and a plurality of cells. The word lines are sequentially disposed in parallel. The first, the second, and the third bit lines are sequentially disposed in parallel and vertical with the word lines. Each cell corresponds to one word line and one bit line. The word line, which corresponds to the cell corresponding to the first bit line, differs from the word line, which corresponds to the cell corresponding to the second bit line. The read circuit is coupled to the memory for reading the data stored in the memory.

Memories are also provided. An exemplary embodiment of a memory comprises a plurality of word lines, a first bit line, a second bit line, a third bit line, and a plurality of cells. The word lines are sequentially disposed in parallel. The first, the second, and the third bit lines are sequentially disposed in parallel and vertical with the word lines. Each cell corresponds to one word line and one bit line. The word line, which corresponds to the cell corresponding to the first bit line, differs from the word line, which corresponds to the cell corresponding to the second bit line. The read circuit is coupled to the memory for reading the data stored in the memory.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2is a schematic diagram of an exemplary embodiment of a storage device. The storage device200comprises a memory210and a reading circuit230. The memory210comprises a large amount of cells (not shown). The reading circuit230reads the data stored in the cells of the memory210. In one embodiment, the memory210is a read-only memory (ROM).

The reading circuit230comprises a switching unit231and a sensing unit233. The switching unit231is coupled between the memory210and the sensing unit233to selectively output the data stored in the cells of the memory210to the sensing unit233. In this embodiment, the switching unit231comprises switches SW0˜SWn. Each of the switches SW0˜SWnis coupled to a corresponding bit line of the memory210. Thus, the number of the switches SW0˜SWncorresponds to the number of the bit lines of the memory210.

When one of the switches SW0˜SWnis turned on, the level on the corresponding bit line is transmitted to the sensing unit233. A controller (not shown) determines whether to turn on the switches SW0˜SWn. Those skilled in the art can utilize numerous methods to achieve the controller, thus, description thereof is omitted. In addition, when one switch is turned on, the other switches are turned off.

The sensing unit233obtains the data stored in the cell of the memory210. In this embodiment, the sensing unit233is a comparator CMP to determine the level on the corresponding bit line. As shown inFIG. 2, the comparator CMP comprises a non-inventing input receiving the output of the switching unit231, and an inventing input receiving a reference signal Vref. The comparator CMP compares the output of the switching unit231and the reference signal Vref and obtains the level on the bit line according to the compared result.

FIG. 3is a schematic diagram of an exemplary embodiment of a memory. The memory210comprises word lines WL0˜WLm, bit lines BL0˜BLn, and a plurality of cells. The word lines WL0˜WLmare sequentially disposed in parallel. The bit lines BL0˜BLnare vertical to the word lines WL0˜WLmand are sequentially disposed in parallel. In this embodiment, the word lines WL0˜WLmare extended to a horizontal direction.

Each cell corresponds to one word line and one bit line. For example, the cell C00corresponds to the word line WL0and the bit line BL0. The cell C11corresponds to the word line WL1and the bit line BL1. In this embodiment, the word line, which corresponds to the cell corresponding to the first bit line, differs from the word line, which corresponds to the cell corresponding to the second bit line. The first and the second bit lines are neighboring.

Taking the bit lines BL0˜BL2as an example, the bit lines BL0˜BL2are sequentially disposed in parallel. The word line (e.g. WL0), which corresponds to the cell (e.g. C00) corresponding to the bit line BL0, differs from the word line (e.g. WL1), which corresponds to the cell (e.g. C11) corresponding to the bit line BL1. The word line (e.g. WL2), which corresponds to the cell (e.g. C20) corresponding to the bit line BL0, differs from the word line (e.g. WL3), which corresponds to the cell (e.g. C31) corresponding to the bit line BL1.

Similarly, the word line (e.g. WL1), which corresponds to the cell (e.g. C11) corresponding to the bit line BL1, differs from the word line (e.g. WL0), which corresponds to the cell (e.g. C02) corresponding to the bit line BL2. The word line (e.g. WL3), which corresponds to the cell (e.g. C31) corresponding to the bit line BL1, differs from the word line (e.g. WL2), which corresponds to the cell (e.g. C22) corresponding to the bit line BL2.

Since the word line, which corresponds to the cell corresponding to the first bit line, differs from the word line, which corresponds to the cell corresponding to the second bit line neighbor on the first bit line, the level transmitted by the corresponding bit line is not affected by the coupling capacitances. For example, when the word line WL0is asserted and the word line WL1is un-asserted, since the bit lines BL1and BL3are not transmitting the corresponding level, the level on the bit lines BL0and BL2are not affected by the level on the neighboring bit lines (i.e. the bit lines BL1and BL3).

Similarly, when the word line WL0is un-asserted and the word line WL1is asserted, since the bit lines BL0and BL2are not transmitting the corresponding level, the level on the bit lines BL1and BL3are not affected by the level on the neighboring bit lines (i.e. the bit lines BL0and BL2).

The arrangement of the cells are interlaced, thus, the bit lines have a resistance function for noise generated by the coupling capacitances. Additionally, the memory does not require extra pull-up loads such that power consumption is not increased. Thus, the memory210requires less power consumption when compared to like, prior art memories.

In other embodiments, a row controller (not shown) is utilized to assert or un-assert the word lines WL0˜WLm. When one word line is asserted, the other word lines are un-asserted. Since those skilled in the art can utilize numerous methods to achieve the row controller, description thereof is omitted.

In this embodiment, the word line, which corresponds to the cell corresponding to one bit line, is the same as the word line, which corresponds to the cell corresponding to another bit line. The two bit lines are not neighboring. Taking the bit lines BL0˜BL3as an example, the bit lines BL0˜BL3are sequentially disposed in parallel. The bit lines BL0is not neighboring on the bit line BL2. Similarly, the bit lines BL1is not neighboring on the bit line BL3.

The word line (e.g. WL0), which corresponds to the cell (e.g. C00) corresponding to the bit line BL0, is the same as the word line (e.g. WL0), which corresponds to the cell (e.g. C02) corresponding to the bit line BL2. The word line (e.g. WL2), which corresponds to the cell (e.g. C20) corresponding to the bit line BL0, is the same as the word line (e.g. WL2), which corresponds to the cell (e.g. C22) corresponding to the bit line BL2. Similarly, the word line (e.g. WL1), which corresponds to the cell (e.g. C11) corresponding to the bit line BL1, is the same as the word line (e.g. WL1), which corresponds to the cell (e.g. C13) corresponding to the bit line BL3. The word line (e.g. WL3), which corresponds to the cell (e.g. C31) corresponding to the bit line BL1, is the same as the word line (e.g. WL3), which corresponds to the cell (e.g. C33) corresponding to the bit line BL3.

In this embodiment, the cells of the memory210comprise transistors. Taking the cell C00as an example, the cell C00comprises transistor T00. The transistor T00comprises a control terminal coupled to the corresponding word line (e.g. WL0), a first electrode receiving a low level (e.g. grounding level VSS), and a second electrode.

Since the second electrode of the transistor T00electrically connects to the bit line BL0, the cell C00stores 0. Similarly, since the second electrode of the transistor T11does not electrically connect to the bit line BL1, the cell C11stores 1. In this embodiment, all transistors are N type transistors. Thus, each N type transistor comprises a gate serving as the control terminal, a source serving as the first electrode, and a drain serving as the second electrode. In other embodiments, the N type transistors are replaced by P type transistors.

Due to the interlaced arrangement of the cells, the neighboring bit lines are not affected by the noise generated by the coupling capacitance. Furthermore, the memory does not require extra pull-up loads. Thus, costs and the power consumption are reduced when compared to like, prior art memories.