Receiver for receiving multilevel signal

A receiver includes a plurality of linear equalizers receiving an input signal; and a plurality of samplers configured to sample a plurality of equalization signals output from the plurality of linear equalizers according to a clock signal. Each of the plurality of linear equalizers compares the input signal with a reference voltage among a plurality of reference voltages to determine a level of the input signal.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2021-0160802, filed on Nov. 19, 2021, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a receiver for receiving a multilevel signal, and more particularly, to a receiver capable of minimizing an offset of a sampler.

2. Related Art

FIG.1is a block diagram showing a conventional receiver1for receiving a Pulse Amplitude Modulation 4-level (PAM4) signal.

The conventional receiver1includes a linear equalizer10, a first sampler21, a second sampler22, and a third sampler23.

The linear equalizer10receives an input signal IN, performs an equalization operation, and outputs an equalization signal OUT.

The first sampler21compares the equalization signal OUT with a first reference voltage VREFH and samples a result thereof to generate the first signal OUTH.

The second sampler22compares the equalization signal OUT with a second reference voltage VREFM and samples a result thereof to generate a second signal OUTM. The second reference voltage VREFM is smaller than the first reference voltage VREFH.

The third sampler23compares the equalization signal OUT with a third reference voltage VREFL and samples a result thereof to generate a third signal OUTL. The third reference voltage VREFL is smaller than the second reference voltage VREFM.

The first to third reference voltages VREFH, VREFM, and VREFL are used to distinguish four levels of the PAM4 signal.

For example, the first reference voltage VREFH distinguishes a fourth level from a third level, the second reference voltage VREFM distinguishes the third level from a second level, and the third reference voltage VREFL distinguishes the second level from a first level.

Each of the first, second, and third samplers21,22, and23includes input transistors for receiving differential signals.

In general, an input offset exists in the input transistors due to threshold voltage mismatch or beta mismatch.

An error may occur when the sampler determines a level due to the input offset, and accordingly, bit error rate (BER) may increase.

As shown inFIG.1, the conventional receiver1includes the linear equalizer10and a plurality of samplers21,22, and23, and an input offset exists in each of the plurality of samplers21,22, and23. Accordingly, the bit error rate may be further increased.

SUMMARY

In accordance with an embodiment of the present disclosure, a receiver may include a plurality of linear equalizers receiving an input signal; and a plurality of samplers configured to sample a plurality of equalization signals output from the plurality of linear equalizers according to a clock signal. Each of the plurality of linear equalizers compares the input signal with a reference voltage among a plurality of reference voltages to determine a level of the input signal.

DETAILED DESCRIPTION

The following detailed description references the accompanying figures in describing illustrative embodiments consistent with this disclosure. The embodiments are provided for illustrative purposes and are not exhaustive. Additional embodiments not explicitly illustrated or described are possible. Further, modifications can be made to the presented embodiments within the scope of teachings of the present disclosure. The detailed description is not meant to limit embodiments of this disclosure. Rather, the scope of the present disclosure is defined in accordance with claims and equivalents thereof. Also, throughout the specification, reference to “an embodiment” or the like is not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s).

FIG.2illustrates a receiver100receiving a multilevel signal (e.g., a PAM4 signal) according to an embodiment of the present disclosure.

The receiver100includes a first linear equalizer110, a second linear equalizer120, a third linear equalizer130, a first sampler210, a second sampler220, and a third sampler230.

The first linear equalizer110compares an input signal IN with a first reference signal (e.g., a first reference voltage) VREFH, performs an equalization operation, and outputs first equalization signals OUTHP and OUTHN. The first equalization signals OUTHP and OUTHN are differential signals.

The first sampler210samples the first equalization signals OUTHP and OUTHN according to a clock signal CLK and outputs a first signal OUTH.

The second linear equalizer120compares the input signal IN with a second reference signal (e.g., a second reference voltage) VREFM, performs an equalization operation, and outputs second equalization signals OUTMP and OUTMN. The second equalization signals OUTMP and OUTMN are differential signals. The second reference voltage VREFM is smaller than the first reference voltage VREFH.

The second sampler220samples the second equalization signals OUTMP and OUTMN according to the clock signal CLK and outputs a second signal OUTM.

The third linear equalizer130compares the input signal IN with a third reference signal (e.g., a third reference voltage) VREFL, performs an equalization operation, and outputs third equalization signals OUTLP and OUTLN. The third equalization signals OUTLP and OUTLN are differential signals. The third reference voltage VREFL is smaller than the second reference voltage VREFM.

The third sampler230samples the third equalization signals OUTLP and OUTLN according to the clock signal CLK and outputs a third signal OUTL.

The first to third reference voltages VREFH, VREFM, and VREFL are used to distinguish first to fourth levels of the PAM4 signal.

For example, the first reference voltage VREFH distinguishes the fourth level from the third level, the second reference voltage VREFM distinguishes the third level from the second level, and the third reference voltage VREFL distinguishes the second level from the first level.

FIG.3is a circuit diagram illustrating the first linear equalizer110ofFIG.2according to an embodiment.

The first linear equalizer110includes a first transistor (e.g., a first PMOS transistor) MP1having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between a first power source VDD and a first node N1, and a second transistor (e.g., a second PMOS transistor) MP2having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the first power source VDD and a second node N2.

A bias signal BIAS is provided to control terminals (e.g., the gates) of the first PMOS transistor MP1and the second PMOS transistor MP2.

The bias signal BIAS may be provided as a substantially fixed value after an optimal operating condition is found.

The first linear equalizer110includes a variable capacitor CC and a variable resistor RC coupled between the first node N1and the second node N2. For example, the variable capacitor CC and the variable resistor RC may be coupled in parallel between the first node N1and the second node N2.

The variable capacitor CC and the variable resistor RC may be adjusted according to a Nyquist frequency and an amplification ratio.

The first linear equalizer110includes a third transistor (e.g., a third PMOS transistor) MP3having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the first node N1and a third node N3and a fourth transistor (e.g., a fourth PMOS transistor) MP4having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the second node N2and the fourth node N4.

The input signal IN is provided to a control terminal (e.g., a gate) of the third PMOS transistor MP3, and the first reference voltage VREFH is provided to a control terminal (e.g., a gate) of the fourth PMOS transistor MP4.

The first linear equalizer110includes load resistors RL coupled between the third node N3and a second power source VSS and between the fourth node N4and the second power source VSS.

The third node N3outputs a second differential equalization signal (e.g., a negative equalization signal) OUTHN, and the fourth node N4outputs a first differential equalization signal (e.g., a positive equalization signal) OUTHP.

The first linear equalizer110performs an equalization operation for amplifying signal attenuation in the Nyquist frequency region of a channel. For example, the first linear equalizer110may perform an equalization operation for attenuating low-frequency signal components and amplifying components in the Nyquist frequency region of a signal transmitted through a channel.

Unlike the conventional linear equalizer that receives only the input signal IN, the first linear equalizer110of this embodiment compares and amplifies the input signal IN and the first reference voltage VREFH.

For example, when the input signal IN is greater than the first reference voltage VREFH, the first differential equalization signal OUTHP has a voltage greater than that of the second differential equalization signal OUTHN, and when the input signal IN is smaller than the first reference voltage VREFH, the first differential equalization signal OUTHP has a voltage smaller than that of the second differential equalization signal OUTHN.

The configuration and operation method of the second linear equalizer120and the third linear equalizer130are substantially the same as those of the first linear equalizer110except signals used therein. Accordingly, detailed descriptions of the configurations and operation methods of the second and third linear equalizers120and130may be omitted for the interest of brevity.

FIG.4is a circuit diagram illustrating the first sampler210ofFIG.2according to an embodiment of the present disclosure.

The first sampler210includes a fifth transistor (e.g., a fifth PMOS transistor) MP5having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the first power source VDD and a fifth node N5and a control terminal (e.g., a gate) to which a clock signal CLK is applied.

The first sampler210includes a sixth transistor (e.g., a sixth PMOS transistor) MP6having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the fifth node N5and a sixth node N6and a control terminal (e.g., a gate) to which a first differential equalization signal (e.g., a positive first equalization signal) OUTHP is applied, and a seventh transistor (e.g., a seventh PMOS transistor) MP7having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the fifth node N5and a seventh node N7and a control terminal (e.g., a gate) to which a second differential equalization signal (e.g., a negative first equalization signal) OUTHN is applied.

The first sampler210includes an eighth transistor (e.g., an eighth PMOS transistor) MP8having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the sixth node N6and the seventh node N7and a control terminal (e.g., a gate) to which the second power voltage VSS is applied.

The eighth PMOS transistor MP8provides a virtual ground in the process of comparing and amplifying the positive first equalization signal OUTHP and the negative first equalization signal OUTHN by the operation of a latch and improves an amplification characteristics of the latch.

The first sampler210includes a ninth transistor (e.g., a ninth PMOS transistor) MP9having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the sixth node N6and an eighth node N8and a control terminal (e.g., a gate) coupled to a ninth node N9and a tenth transistor (e.g., a tenth PMOS transistor) MP10having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the seventh node N7and the ninth node N9and a control terminal (e.g., a gate) coupled with the eighth node N8.

The first sampler210includes an eleventh transistor (e.g., a first NMOS transistor) MN1having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the eighth node N8and the second power source VSS and a control terminal (e.g., a gate) to which a clock signal CLK is applied and a twelfth transistor (e.g., a second NMOS transistor) MN2having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the ninth node N9and the second power source VSS and a control terminal (e.g., a gate) to which a clock signal CLK is applied.

The first sampler210includes a thirteenth transistor (e.g., a third NMOS transistor) MN3having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the eighth node N8and the second power source VSS and a control terminal (e.g., a gate) coupled to the ninth node N9, a fourteenth transistor (e.g., a fourth NMOS transistor) MN4having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the ninth node N9and the second power source VSS and a control terminal (e.g., a gate) coupled to the eighth node N8, and a fifteenth transistor (e.g., a fifth NMOS transistor) MN5having a first terminal (e.g., a source) and a second terminal (e.g., a drain) coupled between the eight node N8and the ninth node N9and a control terminal (e.g., a gate) to which a clock signal CLK is applied.

The first sampler210includes an SR latch211that outputs the first signal OUTH according to a set signal S and a reset signal R.

The first sampler210includes an inverter212for inverting a voltage SB of the eighth node N8to generate the set signal S, and an inverter213for inverting a voltage RB of the ninth node N9to generate the reset signal R.

When the clock signal CLK is at a high level, the voltages SB and RB of the eighth node N8and the ninth node N9are precharged to a first value (e.g., a low level).

At this time, both the set signal S and the reset signal R are at a second value (e.g., the high level), and the first signal OUTH maintains an existing value by the operation of the SR latch211.

When the clock signal CLK is at the low level, the voltages SB and RB of the eighth node N8and the ninth node N9are amplified differentially according to a voltage difference between the positive first equalization signal OUTHP and the negative first equalization signal OUTHN.

For example, when the positive first equalization signal OUTHP is greater than the negative first equalization signal OUTHN, the voltage of the sixth node N6becomes greater than the voltage of the seventh node N7, and the voltage SB of the eighth node N8is amplified to the low level and the voltage RB of the ninth node N9is amplified to the high level.

Accordingly, the set signal S becomes the high level, the reset signal R becomes the low level, and the first signal OUTH becomes the high level.

Conversely, when the positive first equalization signal OUTHP is smaller than the negative first equalization signal OUTHN, the voltage of the seventh node N7becomes greater than the voltage of the sixth node N6, and the voltage of the seventh node N7becomes higher than that of the sixth node N6, and the voltage SB of the node N8is amplified to the high level and the voltage RB of the ninth node N9is amplified to the low level by the latch operation.

Accordingly, the set signal S becomes the low level, the reset signal R becomes the high level, and the first signal OUTH becomes the low level.

The first sampler210may have an offset in the input transistors. However, the input offset of the first sampler210is reduced in inverse proportion to the amplification ratio of the first linear equalizer110ofFIG.3.

Accordingly, the first sampler210does not require a separate circuit for compensating for the input offset.

Since the second sampler220and the third sampler230differ only in signals and have substantially the same structure as the first sampler210, descriptions of the configurations and operation methods of the second and third linear samplers220and230will be omitted for the interest of brevity. As described above, the first, second, and third liner equalizers110,120, and130are coupled to the first, second, and third samplers210,220, and230, respectively. Each of the first, second, and third linear equalizers110,120, and130may provide a pair of differential equalization signals with a given amplification ratio to each of the first, second, and third samplers210,220, and230, and the input offset of each of the first, second, and third samplers210,220, and230may be in inverse proportion to the amplification ratio. As a result, a receiver (e.g., the receiver100inFIG.2) according to an embodiment of the present disclosure including the first, second, and third linear equalizers110,120, and130respectively coupled to the first, second, and third samplers210,220, and230may have a reduced input offset compared to that of a conventional receiver (e.g., the receiver1inFIG.1).

FIG.5is a block diagram illustrating a receiver1000according to an embodiment of the present disclosure.

The receiver1000includes a decoder300that generates a data signal DO corresponding to the multilevel input signal IN by decoding the outputs (or output signals) OUTL, OUTM, and OUTH of the first, second, and third samplers210,220, and230.

Since generating the data signal DO from the first signal OUTH, the second signal OUTM, and the third signal OUTL may be known in the art, a detailed configuration and operation of the decoder300will be omitted for the interest of brevity.

The receiver1000may further includes a reference voltage generator400that generates the first reference voltage VREFH, the second reference voltage VREFM, and the third reference voltage VREFL being provided to the first linear equalizer110, the second linear equalizer120and the third linear equalizer130, respectively.

Although various embodiments have been illustrated and described, various changes and modifications may be made to the described embodiments without departing from the spirit and scope of the invention as defined by the following claims.