Methods of producing fully self-aligned vias and contacts

Methods and apparatus to form fully self-aligned vias are described. First conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed first conductive lines and pillars are formed from the first metal film. Some of the pillars are selectively removed and a second insulating layer is deposited around the remaining pillar. The remaining pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.

TECHNICAL FIELD

Embodiments of the disclosure generally relate to methods of integrated circuit manufacturing requiring the connecting of multiple layers through a via. More particularly, embodiments of the disclosure are directed to methods of producing vias which are self-aligned such that conductive layers with lines running in opposing directions are connected.

BACKGROUND

Generally, an integrated circuit (IC) refers to a set of electronic devices, e.g., transistors formed on a small chip of semiconductor material, typically, silicon. Typically, the IC includes one or more layers of metallization having metal lines to connect the electronic devices of the IC to one another and to external connections. Typically, layers of the interlayer dielectric material are placed between the metallization layers of the IC for insulation.

As the size of the integrated circuit decreases, the spacing between the metal lines decreases. Typically, to manufacture an interconnect structure, a planar process is used that involves aligning and connecting one layer of metallization to another layer of metallization.

Typically, patterning of the metal lines in the metallization layer is performed independently from the vias above that metallization layer. Conventional via manufacturing techniques, however, cannot provide full via self-alignment. In the conventional techniques, the vias formed to connect lines in an upper metallization layer to a lower metallization are often misaligned to the lines in the lower metallization layer. The via-line misalignment increases via resistance and leads to potential shorting to the wrong metal line. The via-line misalignment causes device failures, decreases yield and increases manufacturing cost. Therefore, a method of producing fully self-aligned vias is needed.

SUMMARY

One or more embodiments of the disclosure are directed to methods to provide a self-aligned via. First conductive lines are recessed on a first insulating layer on a substrate. The first conductive lines extend along a first direction on the first insulating layer. A first metal film is formed in the recessed first conductive lines. Pillars are formed from the first metal film in the recessed conductive lines. Some of the pillars are selectively removed, leaving at least one pillar. A second insulating layer is deposited around the remaining pillars. The remaining pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias onto the recessed first conductive lines to form filled vias. An overburden of third insulating layer is formed on the second insulating layer. A portion of the overburden is selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of third insulating layer on the second insulating layer. The third insulating layer is removed from the filled vias to form a via opening to the first conductive line.

Additional embodiments of the disclosure are directed to systems to manufacture an electronic device. The systems include a processing chamber, a plasma source and a processor. The processing chamber comprises a pedestal to hold a substrate comprising a plurality of first conductive lines on a first insulating layer. The first conductive lines extend along a first direction on the first insulating layer. The plasma source is coupled to the processing chamber to generate plasma. The processor is coupled to the plasma source. The processor has one or more configurations to control actions selected from: recessing the first conductive lines, forming a first metal film on the recessed first conductive lines, forming pillars from the first metal film in the recessed first conductive lines, selectively removing some of the pillars and leaving at least one pillar, depositing a second insulating layer around the remaining pillars, removing the remaining pillars to form vias in the second insulating layer, depositing a third insulating layer through the vias onto the recessed first conductive lines to form filled vias, forming an overburden of third insulating layer on the second insulating layer, selectively etching a portion of the overburden from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of third insulating layer on the second insulating layer, and/or etching the third insulating layer from the filled vias to form a via opening to the first conductive line.

DETAILED DESCRIPTION

Methods and apparatuses to provide fully self-aligned vias are described. In one embodiment, a first metallization layer comprising a set of first conductive lines extending along a first direction on a first insulating layer on a substrate is formed. A second insulating layer is formed on the first insulating layer. A second metallization layer comprising a set of second conductive lines on a third insulating layer above the first metallization layer is formed. The set of second conductive lines extend along a second direction. A via is formed between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The via is self-aligned along the first direction to one of the second conductive lines, as described in further detail below. In one embodiment, the first and second directions cross each other at an angle. In one embodiment, the first direction and second direction are substantially orthogonal to each other.

In one embodiment, a fully self-aligned via is fabricated using a selective pillar growth technique. In one embodiment, the conductive lines on a first insulating layer on a substrate are recessed. The conductive lines extend along a first direction on the first insulating layer. Pillars are formed on the recessed conductive lines. A second insulating layer is deposited between the pillars. A third insulating layer is deposited on the second insulating layer. The third insulating layer is selectively etched relative to the second insulating layer form a via opening down to one of the conductive lines, as described in further detail below.

In one embodiment, a fully self-aligned via is the via that is self-aligned along at least two directions to the conductive lines in a lower and an upper metallization layers. In one embodiment, the fully self-aligned via is defined by a hard mask in one direction and the underlying insulating layer in another direction, as described in further detail below.

One or more embodiments provide fully self-aligned vias that advantageously eliminate the via misalignment issues and avoid shorting to the wrong metal line. The fully self-aligned vias provide lower via resistance and capacitance benefits over the conventional vias. Embodiments of the self-aligned vias provide full alignment between the vias and the conductive lines of the metallization layers that is substantially error free that advantageously increase the device yield and reduce the device cost.

When vias are printed close together—closer than the minimum pitch that can be obtained by lithography—the via mask layer set are split into multiple masks. For example, instead of defining via to metal in a single litho-etch sequence, two or more litho-etch sequences are used to avoid shorting the closely spaced vias. Some embodiments of the disclosure are directed to pillar growth processes in which all vias are defined as the cross-over between two metal layers so that adjacent vias will not short to each other. In some embodiments, multiple vias can be defined using one large lithography feature placed over multiple cross points. In this case, all areas where the metal layers overlap under the defined large lithography opening will form a via. As discussed later,FIG. 22shows the via1801linkages to the first conductive lines201and second conductive lines2001which cross each other. Cross-over portions that do not have a via1801can be maintained by the litho mask. Combining the self-aligned process with optimized via and routing design rules, the number of masks per layer can be reduced, saving costs and process complexity.

In the following description, numerous specific details, such as specific materials, chemistries, dimensions of the elements, etc. are set forth in order to provide thorough understanding of one or more of the embodiments of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the one or more embodiments of the present disclosure may be practiced without these specific details. In other instances, semiconductor fabrication processes, techniques, materials, equipment, etc., have not been described in great details to avoid unnecessarily obscuring of this description. Those of ordinary skill in the art, with the included description, will be able to implement appropriate functionality without undue experimentation.

While certain exemplary embodiments of the disclosure are described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current disclosure, and that this disclosure is not restricted to the specific constructions and arrangements shown and described because modifications may occur to those ordinarily skilled in the art.

Reference throughout the specification to “one embodiment”, “another embodiment”, or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

One or more embodiments of the disclosure are directed to methods and apparatus to provide fully self-aligned vias. The various aspects of the disclosure are described with respect to a detailed process illustrated in the Figures. Those skilled in the art will understand that the scope of the disclosure is not limited to the particular details described in the Figures and that some portions of the process can be altered or omitted.

FIG. 1Aillustrates a top view100and a cross-sectional view110of an electronic device structure to provide a fully self-aligned via or air gap according to some embodiments. The cross-sectional view110is along an axis A-A′, as depicted inFIG. 1A.FIG. 1Bis a perspective view120of the electronic device structure depicted inFIG. 1A. A lower metallization layer (Mx) comprises a set of conductive lines that extend along an X axis (direction)121on an insulating layer102on a substrate101, as shown inFIGS. 1A and 1B. As shown inFIG. 1B, X direction121crosses a Y axis (direction)122at an angle123. In one or more embodiments, angle123is about 90 degrees. In some embodiments, angle123is an angle that is other than a 90 degrees angle. The insulating layer102comprises trenches104. The conductive lines103are deposited in trenches104.

In some embodiments, the substrate101comprises a semiconductor material, e.g., silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), InP, GaAs, InGaAs, InAlAs, other semiconductor material, or any combination thereof. In some embodiments, substrate101is a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise any material listed above, e.g., silicon. In various embodiments, the substrate101can be, for example, an organic, a ceramic, a glass, or a semiconductor substrate. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) may be built falls within the spirit and scope of the present disclosure.

In some embodiments, substrate101includes one or more metallization interconnect layers for integrated circuits. In some embodiments, the substrate101includes interconnects, for example, vias, configured to connect the metallization layers. In some embodiments, the substrate101includes electronic devices, e.g., transistors, memories, capacitors, resistors, optoelectronic devices, switches, and any other active and passive electronic devices that are separated by an electrically insulating layer. For example, an interlayer dielectric, a trench insulation layer or any other insulating layer known to one of ordinary skill in the art of the electronic device manufacturing. In some embodiments, the substrate includes one or more buffer layers to accommodate for a lattice mismatch between the substrate101and one or more layers above substrate101and to confine lattice dislocations and defects.

Insulating layer102can be any material suitable to insulate adjacent devices and prevent leakage. In some embodiments, electrically insulating layer102is an oxide layer, e.g., silicon dioxide, or any other electrically insulating layer determined by an electronic device design. In some embodiments, insulating layer102comprises an interlayer dielectric (ILD). In some embodiments, insulating layer102is a low-k dielectric that includes, but is not limited to, materials such as, e.g., silicon dioxide, silicon oxide, carbon doped oxide (“CDO”), e.g., carbon doped silicon dioxide, porous silicon dioxide, silicon nitride or any combination thereof.

In some embodiments, insulating layer102includes a dielectric material having k value less than 5. In some embodiments, insulating layer102includes a dielectric material having k-value less than 2. In some embodiments, insulating layer102includes a nitride, oxide, a polymer, phosphosilicate glass, Fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), other electrically insulating layer determined by an electronic device design, or any combination thereof. In some embodiments, insulating layer102may include polyimide, epoxy, photodefinable materials, such as benzocyclobutene (BCB), and WPR-series materials, or spin-on-glass.

In some embodiments, insulating layer102is a low-k interlayer dielectric to isolate one metal line from other metal lines on substrate101. In some embodiments, the thickness of the layer102is in an approximate range from about 10 nanometers (nm) to about 2 microns (μm).

In some embodiments, insulating layer102is deposited using one of deposition techniques, such as but not limited to a chemical vapor deposition (“CVD”), a physical vapor deposition (“PVD”), molecular beam epitaxy (“MBE”), metalorganic chemical vapor deposition (“MOCVD”), atomic layer deposition (“ALO”), spin˜on, or other insulating deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

In some embodiments, the lower metallization layer Mx comprising metal lines103is a part of a back end metallization of the electronic device. In some embodiments, the insulating layer102is patterned and etched using a hard mask to form trenches104using one or more patterning and etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In some embodiments, the size of trenches in the insulating layer102is determined by the size of conductive lines formed later on in a process.

In some embodiments, forming the conductive lines103involves filling the trenches104with a layer of conductive material. In some embodiments, a base layer (not shown) is first deposited on the internal sidewalls and bottom of the trenches104, and then the conductive layer is deposited on the base layer. In some embodiments, the base layer includes a conductive seed layer (not shown) deposited on a conductive barrier layer (not shown). The seed layer can include copper, and the conductive barrier layer can include aluminum, titanium, tantalum, tantalum nitride, and the like metals. The conductive barrier layer can be used to prevent diffusion of the conductive material from the seed layer, e.g., copper, into the insulating layer102. Additionally, the conductive barrier layer can be used to provide adhesion for the seed layer (e.g., copper).

In some embodiments, to form the base layer, the conductive barrier layer is deposited onto the sidewalls and bottom of the trenches104, and then the seed layer is deposited on the conductive barrier layer. In another embodiment, the conductive base layer includes the seed layer that is directly deposited onto the sidewalls and bottom of the trenches104. Each of the conductive barrier layer and seed layer may be deposited using any thin film deposition technique known to one of ordinary skill in the art of semiconductor manufacturing, e.g., sputtering, blanket deposition, and the like. In one embodiment, each of the conductive barrier layer and the seed layer has the thickness in an approximate range from about 1 nm to about 100 nm. In some embodiments, the barrier layer may be a thin dielectric that has been etched to establish conductivity to the metal layer below. In some embodiments, the barrier layer may be omitted altogether and appropriate doping of the copper line may be used to make a “self-forming barrier”.

In some embodiments, the conductive layer e.g., copper, is deposited onto the seed layer of base layer of copper, by an electroplating process. In some embodiments, the conductive layer is deposited into the trenches104using a damascene process known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the conductive layer is deposited onto the seed layer in the trenches104using a selective deposition technique, such as but not limited to electroplating, electroless, a CVD, PVD, MBE, MOCVD, ALO, spin-on, or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

In some embodiments, the choice of a material for conductive layer for the conductive lines103determined the choice of a material for the seed layer. For example, if the material for the conductive lines103includes copper, the material for the seed layer also includes copper. In some embodiments, the conductive lines103include a metal, for example, copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hi), tantalum (Ta), tungsten (W), Vanadium (V), Molybdenum (Mo), palladium (Pd), gold (Au), silver (Au), platinum Pl, indium (In), tin (Sn), lead (Pb), antimony (Sb), bismuth (Bi), zinc (Zn), cadmium (Cd), or any combination thereof.

In some embodiments, portions of the conductive layer and the base layer are removed to even out top portions of the conductive lines103with top portions of the insulating layer102using a chemical-mechanical polishing (“CMP”) technique known to one of ordinary skill in the art of microelectronic device manufacturing.

In one non-limiting example, the thickness of the conductive lines103is in an approximate range from about 15 nm to about 1000 nm. In one non-limiting example, the thickness of the conductive lines103is from about 20 nm to about 200 nm. In one non-limiting example, the width of the conductive lines103is in an approximate range from about 5 nm to about 500 nm. In one non-limiting example, the spacing (pitch) between the conductive lines103is from about 2 nm to about 500 nm. In more specific non-limiting example, the spacing (pitch) between the conductive lines103is from about 5 nm to about 50 nm.

In some embodiments, the lower metallization layer Mx is configured to connect to other metallization layers (not shown). In some embodiments, the metallization layer Mx is configured to provide electrical contact to electronic devices, e.g., transistors, memories, capacitors, resistors, optoelectronic devices, switches, and any other active and passive electronic devices that are separated by an electrically insulating layer, for example, an interlayer dielectric, a trench insulation layer, or any other insulating layer known to one of ordinary skill in the art of electronic device manufacturing.

FIG. 2Ais a view200similar to view110ofFIG. 1A, after the conductive lines103are recessed according to some embodiments.FIG. 2Bis a view210similar toFIG. 1B, after the conductive lines103are recessed according to some embodiments. The conductive lines103are recessed to a predetermined depth to form recessed conductive lines201. As shown inFIGS. 2A and 2B, trenches202are formed in the insulating layer102. Each trench202has sidewalls204that are portions of insulating layer102and a bottom that is a top surface203of the recessed conductive line201.

In some embodiments, the depth of the trenches202is from about 10 nm to about 500 nm. In some embodiments, the depth of the trenches202is from about 10% to about 100% of the thicknesses of the conductive lines. In some embodiments, the conductive lines103are recessed using one or more of wet etching, dry etching, or a combination of techniques known to one of ordinary skill in the art of electronic device manufacturing.

FIG. 3is a view300similar toFIG. 2A, after a liner301is deposited on the recessed conductive lines201according to some embodiments. Liner301is deposited on the bottom and sidewalls of the trenches202, as shown inFIG. 3.

In some embodiments, liner301is deposited to protect the conductive lines201from changing the properties later on in a process (e.g., during tungsten deposition, or other processes). In some embodiments, liner301is a conductive liner. In another embodiment, liner301is a non-conductive liner. In some embodiments, when liner301is a non-conductive liner, the liner301is removed later on in a process, as described in further detail below. In some embodiments, liner301includes titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), or any combination thereof. In another embodiment, liner301is an oxide, e.g., aluminum oxide (AlO), titanium oxide (TiO2). In yet another embodiment, liner301is a nitride, e.g., silicon nitride (SiN). In an embodiment, the liner301is deposited to the thickness from about 0.5 nm to about 10 nm.

In some embodiments, the liner301is deposited using an atomic layer deposition (ALD) technique. In some embodiments, the liner301is deposited using one of deposition techniques, such as but not limited to a CVD, PVD, MBE, MOCVD, spin-on, or other liner deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

FIG. 4is a view400similar toFIG. 3, after a seed gapfill layer401is deposited on the liner301according to some embodiments. In some embodiments, seed gapfill layer401is a self-aligned selective growth seed film. As shown inFIG. 4, seed gapfill layer401is deposited on liner301on the top surface203of the recessed conductive lines201, the sidewalls204of the trenches202and top portions of the insulating layer102. In some embodiments, seed gapfill layer401is a tungsten (W) layer, or other seed gapfill layer to provide selective growth pillars. In some embodiments, seed gapfill layer401is a metal film or a metal containing film. Suitable metal films include, but are not limited to, films including one or more of Co, Mo, W, Ta, Ti, Ru, rhodium (Rh), Cu, Fe, Mn, V, Niobium (Nb), hafnium (Hf), Zirconium (Zr), Yttrium (Y), Al, Sn, Cr, Lanthanum (La), or any combination thereof. In some embodiments, seed gapfill layer401comprises is a tungsten (W) seed gapfill layer.

In some embodiments, the seed gapfill layer401is deposited using one of deposition techniques, such as but not limited to an ALD, a CVD, PVD, MBE, MOCVD, spin-on, or other liner deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

FIG. 5Ais a view500similar toFIG. 4, after portions of the seed gapfill layer401are removed to expose top portions of the insulating layer102according to one embodiment.FIG. 5Bis a perspective view of the electronic device structure shown inFIG. 5A. In some embodiments, the portions of the seed gapfill layer401are removed using one of the chemical-mechanical polishing (CMP) techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

FIG. 6Ais a view600similar toFIG. 5A, andFIG. 6Bis a view610similar toFIG. 5B, after self-aligned selective growth pillars601are formed using the seed gap fill layer401on the liner301on the recessed conductive lines201according to one or more embodiment. As shown inFIGS. 6A and 6B, an array of the self-aligned selective growth pillars601has the same pattern as the set of the conductive lines201. As shown inFIGS. 6A and 6B, the pillars601extend substantially orthogonally from the top surfaces of the conductive lines201. As shown inFIGS. 6A and 6B, the pillars601extend along the same direction as the conductive lines201. As shown inFIGS. 6A and 6B, the pillars601are separated by gaps603.

In some embodiments, the pillars601are selectively grown from the seed gapfill layer401on portions of the liner301on the conductive lines201. The pillars601are not grown on portions of the liner301on the insulating layer102, as shown inFIGS. 6A and 6B. In some embodiments, portions of the seed gapfill layer401above the conductive lines201are expanded for example, by oxidation, nitridation, or other process to grow pillars601. In some embodiments, the seed gapfill layer401is oxidized by exposure to an oxidizing agent or oxidizing conditions to transform the metal or metal containing seed gapfill layer401to metal oxide pillars601. In some embodiments, pillars601include an oxide of one or more metals listed above. In more specific embodiment, pillars601include tungsten oxide (e.g., WO, WO3and other tungsten oxide).

The oxidizing agent can be any suitable oxidizing agent including, but not limited to, O2, O3, N2O, H2O, H2O2, CO, CO2, NH3, N2/Ar, N2/He, N2/Ar/He or any combination thereof. In some embodiments, the oxidizing conditions comprise a thermal oxidation, plasma enhanced oxidation, remote plasma oxidation, microwave and radio-frequency oxidation (e.g., inductively coupled plasma (ICP), capacitively coupled plasma (CCP)).

In some embodiments, the pillars601are formed by oxidation of the seed gapfill layer at any suitable temperature depending on, for example, the composition of the seed gapfill layer and the oxidizing agent. In some embodiments, the oxidation occurs at a temperature in an approximate range of about 25 degrees C. to about 800 degrees C. In some embodiments, the oxidation occurs at a temperature greater than or equal to about 150° C. In some embodiments, the height602of the pillars601is in an approximate range from about 5 angstroms (A.) to about 10 microns (μm).

FIG. 7Ais a view700similar toFIG. 6A, andFIG. 7Bis a view710similar toFIG. 6B, after an insulating layer701is deposited to overfill the gaps between the pillars601according to some embodiments. As shown inFIGS. 7A and 7B, insulating layer701is deposited on the opposing sides702and top portions703of the pillars601and through the gaps on the portions of the insulating layer102and liner301between the pillars601. A first mask720and a second mask730are illustrated on the insulating layer701. The first mask720is shown covering the all of the insulating layer701and the second mask730is isolated over separate pillars601. Those skilled in the art will recognize that the masking and insulator layers can be single or multiple layers.

In some embodiments, insulating layer701is a low-k gapfill layer. In one embodiment, insulating layer701is a flowable silicon oxide (FSiOx) layer. In some embodiments, insulating layer701is an oxide layer, e.g., silicon dioxide, or any other electrically insulating layer determined by an electronic device design. In some embodiments, insulating layer701is an interlayer dielectric (ILD). In some embodiments, insulating layer701is a low-k dielectric that includes, but is not limited to, materials such as, e.g., silicon dioxide, silicon oxide, a carbon based material, e.g., a porous carbon film, carbon doped oxide (“CDO”), e.g., carbon doped silicon dioxide, porous silicon dioxide, porous silicon oxide carbide hydride (SiOCH), silicon nitride, or any combination thereof. In some embodiments, insulating layer701is a dielectric material having k-value less than 3. In some embodiments, insulating layer701is a dielectric material having k-value in an approximate range from about 2.2 to about 2.7. In some embodiments, insulating layer701includes a dielectric material having k-value less than 2. In some embodiments, insulating layer701represents one of the insulating layers described above with respect to insulating layer102.

In some embodiments, insulating layer701is a low-k interlayer dielectric to isolate one metal line from other metal lines. In some embodiments, insulating layer701is deposited using one of deposition techniques, such as but not limited to a CVD, spin-on, an ALD, PVD, MBE, MOCVD, or other low-k insulating layer deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

Mask720and/or mask730can be any suitable material. In some embodiments, one or more of mask720or mask730comprise silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride. In some embodiments, one or more of the mask720or the mask730comprises a photoresist.

The etch leaves at least one pillar601in contact with conductive lines201. In the embodiment illustrated, there are two pillars601remaining in contact with the conductive lines201and one pillar has been removed.

In the embodiment illustrated, the etch process isotropically removes material that is not directly below mask730. Portions of the insulating layer701remain on the sides702and top703of the remaining pillars601. The middle pillar601, or any pillar not shielded by the mask730, is removed leaving a gap801.

In the embodiment illustrated the liner301remains in the gap801. In some embodiments, the liner301is selectively removed using one or more of the dry and wet etching techniques known to one of ordinary skill in the art of electronic device manufacturing.

Etching can be performed in this part of the process, or any other part of the process incorporating an etch, by any suitable etch technique known to those skilled in the art. In some embodiments, the etch process is one or more of a dry etch or wet etch. In some embodiments, the etch solution comprises 5 wt % ammonium hydroxide aqueous solution at a temperature of about 80° C. In some embodiments, hydrogen peroxide is added to the ammonium hydroxide solution to increase the etch rate. In some embodiments, a hydrofluoric acid and nitric acid in a ratio of about 1:1 is used to etch. In some embodiments, the HF and HNO3in a ratio of about 3:7, respectively, is used to etch. In some embodiments, the HF:HNO3ratio is about 4:1. In some embodiments, the pillars601include tungsten and/or titanium and are etched using ammonium hydroxide:hydrogen peroxide in a ratio of 1:2. In one embodiment, the pillars601are selectively wet etched using 305 grams of potassium ferricyanide (K3Fe(CN)6), 44.5 grams of sodium hydroxide (NaOH) and 1000 ml of water (H2O). In one embodiment, the pillars601are selectively wet etched using diluted or concentrated one or more of the chemistries including hydrochloric acid (HCl), HNO3, sulfuric acid (H2SO4), HF, and H2O2. In one embodiment, the pillars601are selectively wet etched using HF, HNO3and acetic acid (HAc) in a ratio of 4:4:3, respectively. In one embodiment, the pillars601are selectively dry etched using a bromotrifluoromethane (CBrF3) reactive ion etching (RIE) technique. In one embodiment the pillar601am selectively dry etched using a chlorine, fluorine, bromine or any combination thereof based chemistries. In one embodiment, the pillars601are selectively wet etched using hot or warm Aqua Regia mixture including HCl and HNO3in a ratio of 3:1, respectively. In one embodiment, the pillars601arc selectively etched using alkali with oxidizers (potassium nitrate (KNO3) and lead dioxide (PbO2)).

FIG. 9Ais a view900andFIG. 9Bis a view910that are similar toFIGS. 8A and 8B, respectively, after removal of the insulating layer701, mask720and mask730to expose the pillars601and gap801. The insulating layer701, mask720and mask730can be removed by any suitable technique or combination of techniques. For example an etch process could selectively remove the insulating layer701, mask720and mask730without affecting pillar601or insulating layer102. In some embodiments, more than one etch process is used to remove the insulating layer701, mask720and mask730. For example, a first etch process can be used to remove mask730and a second etch process can be used to remove mask720and insulating layer701. In some embodiments, there are three etch processes used to remove the three layers with each etch process selective for one of the layers.

FIG. 10Ais a view1000andFIG. 10Bis a view1010that are similar toFIGS. 9A and 9B, respectively, after deposition of a second insulating layer1001, also referred to as interlayer dielectric or ILD-A. The second insulating layer1001can be any suitable dielectric material as described above with regard to insulating layer102. In some embodiments, ILD-A comprises a flowable film. In some embodiments, the flowable film comprises one or more of silicon oxide or silicon oxycarbide. In some embodiments, the ILD-A comprises a spin-on low-k material.

In the embodiment shown inFIGS. 10A and 10B, the second insulating layer1001has a height greater than pillars601. Stated differently, the thickness of the second insulating layer1001is sufficient to cover the pillars601. In some embodiments, the second insulating layer1001is formed so that a top of the ILD-A is substantially even with the pillars601or slightly below the top of pillars601.

FIG. 11Ais a view1100andFIG. 11Bis a view1110that are similar toFIGS. 10A and 10B, respectively, after chemical-mechanical planarization (CMP) of the second insulating layer1001to expose the tops703of the pillars601. The CMP process can be any suitable planarization process known to those skilled in the art. In some embodiments, the second insulating layer1001is deposited so that the top of the ILD-A is even with or slightly below the top703of the pillars601and the CMP process is not performed.

FIG. 12Ais a view1200andFIG. 12Bis a view1210that are similar toFIGS. 11A and 11B, respectively, after removal of the pillars601to leave vias1201in the second insulating layer1001. Etching of the pillars601can be done by any suitable technique. In some embodiments, etching the pillars601comprises exposing the pillars601to a metal halide compound. In some embodiments, the metal halide compound has a different metal than the pillars601.

In some embodiments, etching the pillars601comprises exposure to a metal-and-halogen-containing precursor (e.g. WCl6), also referred to as a metal halide precursor. The metal halide precursor can react with the pillars601. In some embodiments, exposure to the metal halide precursor causes an exothermic reaction with the pillar material and no plasma is present in the substrate processing region. In some embodiments, there is no plasma used to excite the metal-halide precursor prior to entering the substrate processing region.

In an exemplary non-limiting process, the pillars601comprise tungsten and are grown by reaction with oxygen to form the tungsten oxide pillars, which may take the form of WO3. Exposure of WO3to WCl6(or possibly WCl5) forms volatile WOCl4and/or WO2Cl2which leaves the surface until all tungsten oxide is removed. The reaction can spontaneously stop once the tungsten oxide portion (or metal oxide portion in general) is removed. The process can be repeated an integral number of cycles. Each cycle may remove a selectable amount of the original tungsten film (e.g. 1 or 2 monolayers).

In some embodiments, the metal halide precursor includes two or more or only two different elements including a metal element and a halogen element. The metal halide precursor may include only a single atom of the metal element but multiple atoms of the same halogen element (as is the case for WCl6and WCl5). The metal element of the metal halide may include one or more of titanium, hafnium, zirconium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, rhenium, technetium, iron, aluminum and gallium in embodiments. In some embodiments, the metal element of the metal halide has an atomic number of 22, 23, 24, 40, 41, 42, 72, 73 or 74. In one or more embodiments, the metal element comprises an element of group 4, group 5 or group 6 of the periodic table or may be transition metals. The halogen element may be one of F and Cl according to one or more embodiments. The halogen element may be one or more of F, Cl, Br and/or I. In some embodiments, the metal-and-halogen-containing precursor fluorine-free. Some examples of suitable metal halide precursors include, but are not limited to, vanadium pentahalides, tantalum pentahalides, chromium hexahalides, molybdenum pentahalides, molybdenum hexahalides, niobium pentahalides, tungsten pentahalides, tungsten hexahalides, and manganese tetrahalides. In some embodiments, the metal halide precursors include, but are not limited to, vanadium halides, tantalum halides, chromium halides, molybdenum halides, niobium halides, tungsten halides and/or manganese halides, where the oxidation state of the metal element can be any suitable oxidation state.

FIG. 13Ais a view1300andFIG. 13Bis a view1310that are similar toFIGS. 12A and 12B, respectively, after gapfilling the vias1201with a third insulating layer1301. The third insulating layer1301can be any suitable dielectric material that is different than the second insulating layer1001. The third insulating layer1301fills the vias1201and contacts the liner301(as shown) or the recessed first conductive lines201(if no liner301is present).

In the embodiment illustrated, the third insulating layer1301is deposited with a thickness sufficient to form an overburden1302on top of the second insulating layer1001. The overburden1302can be any suitable thickness that is readily removable in a subsequent planarization or etch process. The third insulating layer1301can also be referred to as a second interlayer dielectric or ILD-B. The third insulating layer1301of some embodiments comprises a low-k dielectric having a dielectric constant less than or equal to about 5. In some embodiments, one or more of the first insulating layer, the second insulating layer and the third insulating layer are independently selected from: oxides, carbon doped oxides, porous silicon dioxide, nitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), or any combinations thereof.

FIG. 14Ais a view1400andFIG. 14Bis a view1410that are similar toFIGS. 13A and 13B, respectively, after removal of the overburden1302of the third insulating layer1301. In some embodiments, the overburden1302can be removed by a chemical-mechanical planarization (CMP) process known to those skilled in the art.

In some embodiments, the overburden1302is removed by a selective etch process. The selective etch process can be selective for removal of the third insulating layer1301relative to the second insulating layer1001so that substantially none of the second insulating layer1001is removed. After removal of the overburden1302, the second insulating layer1001and the third insulating layer1301are exposed. Stated differently, after removal of the overburden1302both the first interlayer dielectric ILD-A and the second interlayer dielectric ILD-B are exposed.

FIG. 15Ais a view1500andFIG. 15Bis a view1510that are similar toFIGS. 14A and 14B, respectively, after formation of additional third insulating layer1501, stack1502and mask1503. The additional third insulating layer1501is the same material as the third insulating layer1301already present in the vias. The combination of the thickness of the additional third insulating layer1501and the stack1502is substantially the same as the depth of the via. The third insulating layer1301, additional third insulating layer1501, stack1502and mask1503can be formed by any suitable technique known to those skilled in the art.

FIG. 16Ais a view1600andFIG. 16Bis a view1610that are similar toFIGS. 15A and 15B, respectively, after etching the stack1502and additional third insulating layer1501to expose the second insulating layer1001. The mask1503covers portions of the stack1502and additional third insulating layer1501that are not removed during the etch process to form trench1601.

Trench1601extends in a second direction that is different from the first direction of the first conductive lines201. In the embodiment shown, the first conductive lines201extend along the x-axis and the trench1601extends along the y-axis. In some embodiments, the second direction is at an angle to the first direction in the range of about 30° to about 150°, or in the range of about 50° to about 130°, or in the range of about 70° to about 110°, or in the range of about 80° to about 100°, or in the range of about 85° to about 95°, or in the range of about 87° to about 93°, or in the range of about 89° to about 91°.

FIG. 17Ais a view1700andFIG. 17Bis a view1710that are similar toFIGS. 16A and 16B, respectively, after additional stack1701(e.g., a trilayer stack known to the skilled artisan) and mask1702is formed. The stack1701and mask1702can be any suitable materials. In some embodiments, the additional stack1701has a thickness that is substantially equal to the thickness of the additional third insulating layer1501and stack1502already present.

FIG. 18Ais a view1800andFIG. 18Bis a view1810that are similar toFIGS. 17A and 17B, respectively, after etching the additional stack1701and third insulating layer1301from the regions not beneath the mask1503or mask1702. After removal of the third insulating layer1301, via1801is formed in the second insulating layer1001. The etch process used to remove the third insulating layer1301is selective for the third insulating layer1301relative to the second insulating material1001so that the width of the via1801is controlled.

FIG. 19Ais a view1900andFIG. 19Bis a view1910that are similar toFIGS. 18A and 18B, respectively, after removing the mask1503, mask1702and stack1502leaving via1801and trench1901. The third insulating layer1301has been completely removed at this point leaving the second insulating layer1001on the first insulating layer102and the vias1801extending through the second insulating layer1001.

FIG. 20Ais a view2000andFIG. 20Bis a view2010that are similar toFIGS. 19A and 19B, respectively, after deposition of second conductive line2001in the via1801and trench1901. The second conductive line2001can be any suitable metal and can be deposited by any suitable deposition technique. The second conductive line2001extends in the second direction which is different than the first direction of the first conductive line201, as described above.

FIG. 21shows another embodiment of the disclosure. Here, a pillar601is grown to form a contact2150between gates2160. A dielectric2170prevents direct shorting of adjacent gates2160. The gate2160can be any suitable type of gate known to the skilled artisan. The particular structure of the gate2160is not broken down into individual components as the skilled artisan will recognize and know how a suitable gate is formed. In some embodiments, the gate2160contact forms one or more conductive lines103, as shown inFIG. 1, and the process described with respect to the various Figures forms the contact2150.

FIG. 22shows a portion of a device2100with the fully self-aligned vias in a nested structure. The first conductive lines201extend vertically on the page and the second conductive lines2001extend horizontally on the page. Vias1801are illustrated where the connections between the first conductive lines201and the second conductive lines2001occur. The packing and arrangement of the conductive lines and vias can be tighter (i.e., higher density) or looser (i.e., lower density) than the embodiment illustrated.

FIG. 23shows a block diagram of a plasma system to perform at least some of the operations to provide a fully self-aligned via according to one embodiment. As shown inFIG. 23, system2200has a processing chamber2201. A movable pedestal2202to hold an electronic device structure2203is placed in processing chamber2201. Pedestal2202comprises an electrostatic chuck (“ESC”), a DC electrode embedded into the ESC, and a cooling/heating base. In an embodiment, pedestal2202acts as a moving cathode. In an embodiment, the ESC comprises an Al2O3material, Y2O3, or other ceramic materials known to one of ordinary skill of electronic device manufacturing. A DC power supply2204is connected to the DC electrode of the pedestal2202.

As shown inFIG. 23, an electronic device structure2203is loaded through an opening2208and placed on the pedestal2202. The electronic device structure2203represents one of the electronic device structures described above. System2200comprises an inlet to input one or more process gases2212through a mass flow controller2211to a plasma source2213. A plasma source2213comprising a showerhead2214is coupled to the processing chamber2201to receive one or more gases2212to generate plasma. Plasma source2213is coupled to a RF source power2210. Plasma source2213through showerhead2214generates a plasma2215in processing chamber2201from one or more process gases2212using a high frequency electric field. Plasma2215comprises plasma particles, such as ions, electrons, radicals or any combination thereof. In an embodiment, power source2210supplies power from about 50 W to about 3000 W at a frequency from about 400 kHz to about 162 MHz to generate plasma2215.

A plasma bias power2205is coupled to the pedestal2202(e.g., cathode) via a RF match2207to energize the plasma. In an embodiment. the plasma bias power2205provides a bias power that is not greater than 1000 W at a frequency between about 2 MHz to 60 MHz. and in a particular embodiment at about 13 MHz. A plasma bias power2206may also be provided. for example to provide another bias power that is not greater than 1000 W at a frequency from about 400 kHz to about 60 MHz, and in a particular embodiment, at about 60 MHz. Plasma bias power2206and bias power2205are connected to RF match2207to provide a dual frequency bias power. In an embodiment. a total bias power applied to the pedestal2202is from about 10 W to about 3000 W.

As shown inFIG. 23, a pressure control system2209provides a pressure to processing chamber2201. As shown inFIG. 23, chamber2201has one or more exhaust outlets2216to evacuate volatile products produced during processing in the chamber. In an embodiment, the plasma system2200is an inductively coupled plasma (ICP) system. In an embodiment, the plasma system2200is a capacitively coupled plasma (CCP) system.

A control system2217is coupled to the chamber2201. The control system2217comprises a processor2218, a temperature controller2219coupled to the processor2218, a memory2220coupled to the processor2218and input/output devices2221coupled to the processor2218to form fully self-aligned via as described herein. The control system2217can also include one or more of circuits, non-transitory memory, transitory memory, electronic media or executable instruction sets as may be used to operate under various configurations.

In one embodiment, the control system2217, or the processor2218within the control system2217includes one or more configurations (i.e., executable instruction sets) to process a substrate. The control system2217and/or processor2218may have one or more configurations to control actions or processes selected from: recessing the first conductive lines, forming a first metal film on the recessed first conductive lines, forming pillars from the first metal film in the recessed first conductive lines, selectively removing some of the pillars and leaving at least one pillar, depositing a second insulating layer around the remaining pillars, removing the remaining pillars to form vias in the second insulating layer, depositing a third insulating layer through the vias onto the recessed first conductive lines to form filled vias, forming an overburden of third insulating layer on the second insulating layer, selectively etching a portion of the overburden from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of third insulating layer on the second insulating layer, and/or etching the third insulating layer from the filled vias to form a via opening to the first conductive line. In some embodiments, the configuration controls recessing the first conductive lines such that the first conductive lines are recessed in the range of about 10 nm to about 50 nm. In some embodiments, the control system2217and/or processor2218includes a configuration to deposit a liner on the recessed first conductive lines. In some embodiments, the control system2217and/or processor2218includes a configuration deposit a second conductive material into the via opening. In some embodiments, the control system2217and/or processor2218includes a configuration to deposit a plurality of second conductive lines on the second insulating layer and in contact with the second conductive material in the via opening, the second conductive lines extending along a second direction on the second insulating layer.

The control system2217is configured to perform at least some of the methods as described herein and may be either software or hardware or a combination of both. The plasma system2200may be any type of high performance processing plasma systems known in the art, such as but not limited to an etcher, a cleaner, a furnace, or any other plasma system to manufacture electronic devices.

According to one or more embodiments, the substrate is subjected to processing prior to and/or after forming the layer. This processing can be performed in the same chamber or in one or more separate processing chambers. In some embodiments, the substrate is moved from the first chamber to a separate, second chamber for further processing. The substrate can be moved directly from the first chamber to the separate processing chamber, or it can be moved from the first chamber to one or more transfer chambers, and then moved to the separate processing chamber. Accordingly, the processing apparatus may comprise multiple chambers in communication with a transfer station. An apparatus of this sort may be referred to as a “cluster tool” or “clustered system,” and the like.

Generally, a cluster tool is a modular system comprising multiple chambers which perform various functions including substrate center-finding and orientation, degassing, annealing, deposition and/or etching. According to one or more embodiments, a cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber may house a robot that can shuttle substrates between and among processing chambers and load lock chambers. The transfer chamber is typically maintained at a vacuum condition and provides an intermediate stage for shuttling substrates from one chamber to another and/or to a load lock chamber positioned at a front end of the cluster tool. However, the exact arrangement and combination of chambers may be altered for purposes of performing specific steps of a process as described herein. Other processing chambers which may be used include, but are not limited to, cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, pre-clean, chemical clean, thermal treatment such as RTP, plasma nitridation, degas, orientation, hydroxylation and other substrate processes. By carrying out processes in a chamber on a cluster tool, surface contamination of the substrate with atmospheric impurities can be avoided without oxidation prior to depositing a subsequent film.

According to one or more embodiments, the substrate is continuously under vacuum or “load lock” conditions, and is not exposed to ambient air when being moved from one chamber to the next. The transfer chambers are thus under vacuum and are “pumped down” under vacuum pressure. Inert gases may be present in the processing chambers or the transfer chambers. In some embodiments, an inert gas is used as a purge gas to remove some or all of the reactants. According to one or more embodiments, a purge gas is injected at the exit of the deposition chamber to prevent reactants from moving from the deposition chamber to the transfer chamber and/or additional processing chamber. Thus, the flow of inert gas forms a curtain at the exit of the chamber.

The substrate can be processed in single substrate deposition chambers, where a single substrate is loaded, processed and unloaded before another substrate is processed. The substrate can also be processed in a continuous manner, similar to a conveyer system, in which multiple substrate are individually loaded into a first part of the chamber, move through the chamber and are unloaded from a second part of the chamber. The shape of the chamber and associated conveyer system can form a straight path or curved path. Additionally, the processing chamber may be a carousel in which multiple substrates are moved about a central axis and are exposed to deposition, etch, annealing, cleaning, etc. processes throughout the carousel path.

During processing, the substrate can be heated or cooled. Such heating or cooling can be accomplished by any suitable means including, but not limited to, changing the temperature of the substrate support and flowing heated or cooled gases to the substrate surface. In some embodiments, the substrate support includes a heater/cooler which can be controlled to change the substrate temperature conductively. In one or more embodiments, the gases (either reactive gases or inert gases) being employed are heated or cooled to locally change the substrate temperature. In some embodiments, a heater/cooler is positioned within the chamber adjacent the substrate surface to convectively change the substrate temperature.

The substrate can also be stationary or rotated during processing. A rotating substrate can be rotated continuously or in discrete steps. For example, a substrate may be rotated throughout the entire process, or the substrate can be rotated by a small amount between exposures to different reactive or purge gases. Rotating the substrate during processing (either continuously or in steps) may help produce a more uniform deposition or etch by minimizing the effect of, for example, local variability in gas flow geometries.