Semiconductor device including transparent conductive oxide layer

A semiconductor device may comprise a stack structure on a substrate, the stack structure including a plurality of dielectric layers and a plurality of transparent conductive oxide layers, the dielectric layers and the transparent conductive oxide layers are alternately stacked, each of the dielectric layers and a corresponding one of the transparent conductive oxide layer adjacent to each other in a vertical direction have equal horizontal widths, and a channel structure extending through the stack structure, the channel structure including an information storage layer, a channel layer inside the information storage layer, and a buried dielectric layer inside the channel layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims from Korean Patent Application No. 10-2019-0123150, filed on Oct. 4, 2019, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Devices consistent with example embodiments relate to semiconductor devices including a transparent conductive oxide layer and semiconductor device manufacturing methods using a transparent conductive oxide layer.

2. Description of Related Art

A nonvolatile memory apparatus including memory cells three-dimensionally arranged for lightweight, thin, short, small, and highly integrated electronic products has been proposed. The nonvolatile memory apparatus includes a channel structure extending through a stack structure. In order to increase the degree of device integration, a higher stack structure may be used, whereby process difficulty may be increased, and misalignment may occur during photolithography or etching.

SUMMARY

Example embodiments of inventive concepts are directed to provide a semiconductor device manufactured through a simplified process and a method of manufacturing the same.

In an embodiment, a semiconductor device may comprise a stack structure on a substrate, the stack structure including a plurality of dielectric layers and a plurality of transparent conductive oxide layers, the dielectric layers and the transparent conductive oxide layers are alternately stacked, each of the dielectric layers and a corresponding one of the transparent conductive oxide layers adjacent to each other in a vertical direction have equal horizontal widths, and a channel structure extending through the stack structure, the channel structure including an information storage layer, a channel layer inside the information storage layer, and a buried dielectric layer inside the channel layer.

According to some example embodiments, a semiconductor device may comprise a peripheral circuit structure including a peripheral circuit device and a contact plug, a lower conductive layer on the peripheral circuit structure, a stack structure on the lower conductive layer, the stack structure including a plurality of dielectric layers and a plurality of transparent conductive oxide layers, the dielectric layers and the transparent conductive oxide layers are alternately stacked, and a plurality of channel structures extending through the stack structure, each channel structure including an information storage layer, a channel layer inside the information storage layer, the channel layer being connected to the lower conductive layer, and a buried dielectric layer inside the channel layer.

According to some example embodiments, a semiconductor device may comprise a peripheral circuit structure comprising a peripheral circuit device and a contact plug; a lower conductive layer on the peripheral circuit structure; a stack structure on the lower conductive layer, the stack structure comprising a plurality of dielectric layers and a plurality of transparent conductive oxide layers, the dielectric layers and the transparent conductive oxide layers are alternately stacked; a plurality of channel structures extending through the stack structure, each channel structure comprising an information storage layer, a channel layer inside the information storage layer, the channel layer being connected to the lower conductive layer, and a buried dielectric layer inside the channel layer; a plurality of conductive pads formed in the stack structure and on respective channel structures; a selection line separation layer extending into the stack structure separating at least one of the transparent conductive oxide layers; a buried layer adjacent to the channel structures, the buried layer extending through the stack structure; and a bit line on the stack structure, the bit line being electrically connected to the conductive pads. When viewed in a longitudinal sectional view, horizontal widths of each of the dielectric layers and a corresponding one of the transparent conductive oxide layers that are stacked adjacent to each other in a vertical direction may be substantially equal to each other. In each of the dielectric layers and the corresponding one of the transparent conductive oxide layers that are stacked adjacent to each other in the vertical direction, a central portion and an edge of the dielectric layer abut the transparent conductive oxide layer, and a horizontal distance between dielectric layers that are adjacent to each other in a horizontal direction, among the dielectric layers, may be substantially equal to a horizontal distance between transparent conductive oxide layers that are adjacent to each other in the horizontal direction, among the transparent conductive oxide layers.

According to some example embodiments, a semiconductor device manufacturing method may comprise alternately stacking a plurality of dielectric layers and a plurality of transparent conductive oxide layers on a substrate to form a stack structure; forming a channel hole so as to extend through the stack structure; forming a lower semiconductor layer in the channel hole so as to protrude from the substrate; and forming a channel structure comprising an information storage layer, a channel layer, and a buried dielectric layer on the lower semiconductor layer.

According to some example embodiments, a semiconductor device manufacturing method may comprise alternately stacking a plurality of dielectric layers and a plurality of transparent conductive oxide layers on a substrate to form a stack structure; forming a channel hole so as to extend through the stack structure; forming an information storage layer at a side surface and a lower surface of the channel hole; etching a lower surface of the information storage layer to form a recess in an upper surface of the substrate; forming a lower semiconductor layer in the channel hole so as to protrude from the substrate; and forming a channel layer and a buried dielectric layer on the lower semiconductor layer.

According to some example embodiments, a semiconductor device manufacturing method may comprise forming a peripheral circuit structure comprising a peripheral circuit device and a contact plug; forming a lower conductive layer on the peripheral circuit structure; alternately stacking a plurality of dielectric layers and a plurality of transparent conductive oxide layers on the lower conductive layer to form a stack structure; forming a channel hole so as to extend through the stack structure; forming an information storage layer at a side surface and a lower surface of the channel hole; etching a lower surface of the information storage layer to form a recess in an upper surface of the lower conductive layer; and forming a channel layer and a buried dielectric layer in the channel hole.

According to some example embodiments, a semiconductor device manufacturing method may comprise sequentially forming a source layer, a sacrificial layer, and a support layer on a substrate; alternately stacking a plurality of dielectric layers and a plurality of transparent conductive oxide layers on the support layer to form a stack structure; forming a channel structure so as to extend through the sacrificial layer, the support layer, the stack structure, and a portion of the source layer; forming a trench so as to be adjacent to the channel structure and to extend through the sacrificial layer, the support layer, and the stack structure; removing the sacrificial layer and forming a conductive line; and removing the transparent conductive oxide layers and forming a plurality of gate electrodes.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1is a layout of a semiconductor device according to some example embodiments of inventive concepts.FIG. 2are vertical cross-sectional views of the semiconductor device ofFIG. 1, taken along line I-I′. A memory apparatus according to embodiments of the present disclosure may include a flash memory, such as VNAND or 3D-NAND.

Referring toFIGS. 1 and 2, a semiconductor device100according to the embodiment of the present disclosure may include a substrate102, a lower dielectric layer104, a lower semiconductor layer106, an impurity region108, a stack structure110, a channel structure C, a conductive pad140, and a buried layer150. The semiconductor device100may further include a first upper dielectric layer160, a sub-bit line plug161, a second upper dielectric layer162, a sub-bit line163, a third upper dielectric layer164, a bit line plug165, and a bit line166.

The substrate102may include a semiconductor material. For example, the substrate102may be a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon-on-insulator (SOI) substrate. In some example embodiments, the substrate102may include a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor.

The lower dielectric layer104may be disposed on the substrate102. The lower dielectric layer104may include a silicon oxide, a silicon nitride, a silicon oxynitride, or a combination thereof. In some example embodiments, the lower dielectric layer104may include a silicon oxide.

The lower semiconductor layer106may protrude vertically from an upper surface of the substrate102. The lower semiconductor layer106may be an epitaxial layer using the substrate102as a seed. The lower semiconductor layer106may include silicon, germanium, silicon germanium, a group III-V compound, and/or a group II-VI compound. The impurity region108may be disposed at the upper part of the substrate102. The impurity region108may include an n-type impurity.

The stack structure110may include a plurality of transparent conductive oxide layers112and a plurality of dielectric layers114. The transparent conductive oxide layers112and the dielectric layers114may be alternately stacked. At least one of the transparent conductive oxide layers112disposed at the lower part of the stack structure110may be a ground selection line (GSL). At least one of the transparent conductive oxide layers112disposed at the upper part of the stack structure110may be a string selection line (SSL) or a drain selection line (DSL).

Each transparent conductive oxide layer112may include a metal oxide, such as ZnO, SnO2, TiO2, CuAlO2, CuGaO2, CuInO2, or SrCu2O2. In some example embodiments, each dielectric layer114may include a silicon oxide. In some example embodiments, each transparent conductive oxide layer112may have a carrier concentration of 1017/cm3to 1022/cm3.

The channel structure C may extend vertically through the stack structure110. The channel structure C may be electrically connected to the lower semiconductor layer106. A plurality of channel structures C may be disposed so as to be spaced apart from each other in a first horizontal direction D1. The channel structure C may include an information storage layer120, a channel layer130, and a buried dielectric layer135. The channel layer130may be disposed inside the information storage layer120, and the buried dielectric layer135may be disposed inside the channel layer130. In some example embodiments, in a longitudinal sectional view, the horizontal widths of each dielectric layer114and a corresponding transparent conductive oxide layer112that are stacked adjacent to each other in a vertical direction may be substantially equal to each other. For example, the difference between the horizontal widths of each dielectric layer114and a corresponding transparent conductive oxide layer112that are stacked adjacent to each other in the vertical direction may be less than 5 nm. In a longitudinal sectional view, in each dielectric layer114and a corresponding transparent conductive oxide layer112that are stacked adjacent to each other in the vertical direction, the central portion and the edge of the dielectric layer114may abut the transparent conductive oxide layer112. In a longitudinal sectional view, the horizontal distance between the dielectric layers114that are adjacent to each other in a horizontal direction may be substantially equal to the horizontal distance between the transparent conductive oxide layers112that are adjacent to each other in the horizontal direction. For example, the horizontal distance between the dielectric layers114that are adjacent to each other in the horizontal direction may be equal to the horizontal width of the channel structure C, and the horizontal distance between the transparent conductive oxide layers112that are adjacent to each other in the horizontal direction may be equal to the horizontal width of the channel structure C.

When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “generally” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes. While the term “same” or “identical” is used in description of example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±10%).

The conductive pad140may be disposed on the channel structure C. The conductive pad140may be electrically connected to the channel layer130, and may cover the upper surface of the buried dielectric layer135.

A selection line separation layer142may be disposed at the upper part of the stack structure110. The selection line separation layer142may extend in a second horizontal direction D2, which intersects the first horizontal direction D1. The selection line separation layer142may extend through at least one of the transparent conductive oxide layers112disposed at the upper part of the stack structure110. For example, the selection line separation layer142may electrically separate the string selection line SSL or the drain selection line DSL.

An interlayer dielectric layer144may cover the upper surface of the stack structure110. Each of the selection line separation layer142and the interlayer dielectric layer144may include a silicon oxide, a silicon nitride, a silicon oxynitride, or a combination thereof.

The buried layer150may extend through the stack structure110and the interlayer dielectric layer144. The buried layer150may abut the impurity region108. The buried layer150may extend in the second horizontal direction D2. Side spacers152may be disposed at opposite side surfaces of the buried layer150, and may extend in the second horizontal direction D2. The side spacers152may electrically isolate the transparent conductive oxide layers112and the buried layer150.

The first upper dielectric layer160, the second upper dielectric layer162, and the third upper dielectric layer164may be sequentially stacked on the interlayer dielectric layer144. The sub-bit line plug161may be connected to the conductive pad140through the interlayer dielectric layer144and the first upper dielectric layer160. The sub-bit line163may be disposed on the first upper dielectric layer160. The second upper dielectric layer162may be disposed at the same level as the sub-bit line163. The third upper dielectric layer164may be disposed at the upper surface of the sub-bit line163. The bit line plug165may be disposed at the same level as the third upper dielectric layer164, and may be connected to the sub-bit line163. The bit line166may be disposed on the third upper dielectric layer164, and may extend in the first horizontal direction D1. The bit line166may be electrically connected to the channel structure C through the conductive pad140, the sub-bit line plug161, the sub-bit line163, and the bit line plug165.

FIG. 3is a partial enlarged view of the semiconductor device shown inFIG. 2.

Referring toFIG. 3, the information storage layer120may include a blocking layer122, a charge storage layer124, and a tunnel dielectric layer126. The charge storage layer124may be disposed inside the blocking layer122, and the tunnel dielectric layer126may be disposed inside the charge storage layer124. The side surface of the information storage layer120may abut the lowermost one of the transparent conductive oxide layers112. In some example embodiments, each of the blocking layer122and the tunnel dielectric layer126may include a silicon oxide, and the charge storage layer124may include a silicon nitride.

The lower semiconductor layer106may protrude from the upper surface of the substrate102, and may abut the channel layer130. The lower surface of the lower semiconductor layer106may be located at a lower level than the upper surface of the substrate102. The upper surface of the lower semiconductor layer106may be located at a lower level than the lower surface of the lowermost one of the transparent conductive oxide layers112. The channel layer130may extend through the information storage layer120, and may abut the upper surface of the lower semiconductor layer106. The channel layer130may be formed conformally along the inner wall of the information storage layer120and the upper surface of the lower semiconductor layer106. However, the present disclosure is not limited thereto.

FIG. 4is a partial enlarged view of the semiconductor device according to some example embodiments of inventive concepts.

Referring toFIG. 4, a semiconductor device200may include a recess R1formed in the upper surface of a substrate102. A lower semiconductor layer206may protrude from the upper surface of the substrate102, and may abut a channel layer130. The upper surface of the lower semiconductor layer206may be located at a higher level than the upper surface of the lowermost one of a plurality of transparent conductive oxide layers112. The lower semiconductor layer206may fill the recess R1. The lower semiconductor layer206may extend through an information storage layer220including a blocking layer222, a charge storage layer224, and a tunnel dielectric layer226. In some example embodiments, the lower horizontal width of the lower semiconductor layer206may be smaller than the upper horizontal width of the lower semiconductor layer206.

The lower semiconductor layer206may not directly abut the transparent conductive oxide layer112, and the information storage layer220may be disposed between the lower semiconductor layer206and the transparent conductive oxide layer112. The lower surface of the information storage layer220may be located at a lower level than the upper surface of the substrate102. For example, the lower surface of the blocking layer222may be located at a lower level than the upper surface of the substrate102.

FIGS. 5-10are vertical cross-sectional views illustrating in a process order of a method of manufacturing a semiconductor device according to some example embodiments of inventive concepts.

Referring toFIG. 5, a lower dielectric layer104may be stacked on a substrate102. The lower dielectric layer104may include a silicon oxide. A stack structure110may be disposed on the lower dielectric layer104. The stack structure110may include a plurality of transparent conductive oxide layers112and a plurality of dielectric layers114, which are alternately stacked.

Referring toFIG. 6, a plurality of channel holes CHH may be formed so as to extend through the lower dielectric layer104and the stack structure110. The channel holes CHH may be formed by anisotropic etching, or other suitable methods, and the upper surface of the substrate102may be exposed through the channel holes CHH. Each channel hole CHH cross-section may be circular, however the channel hole CHH cross-section may be other shapes as well, for example a hexagonal shape. In some example embodiments, the lower width of the channel hole CHH may be smaller than the upper width of the channel hole CHH. The channel hole CHH may include a portion of the upper surface of the substrate102may be etched by anisotropic etching.

Referring toFIG. 7, a lower semiconductor layer106may be formed at the lower part of each channel hole CHH. The lower semiconductor layer106may be formed through selective epitaxial growth (SEG) using the substrate102as a seed. The lower semiconductor layer106may include silicon, germanium, silicon germanium, a group III-V compound, and/or a group II-VI compound. The lower semiconductor layer106may include an n-type impurity or a p-type impurity. In some example embodiments, the upper surface of the lower semiconductor layer106may be located at a lower level than the lower surface of the lowermost one of the transparent conductive oxide layers112.

Referring toFIG. 8, a channel structure C and a conductive pad140may be formed in each channel hole CHH. The channel structure C may include an information storage layer120, a channel layer130, and a buried dielectric layer135. The channel layer130may be disposed inside the information storage layer120, and the buried dielectric layer135may be disposed inside the channel layer130. The conductive pad140may be formed on the channel structure C. The conductive pad140may be electrically connected to the channel layer130, and may cover the upper surface of the buried dielectric layer135.

The channel layer130may include polysilicon. In some example embodiments, the channel layer130may include an n-type impurity or a p-type impurity. The buried dielectric layer135may include a silicon oxide, a silicon nitride, a silicon oxynitride, or a combination thereof. The conductive pad140may include doped polysilicon.

A string selection line cut SLC may be formed by etching a portion of the upper part of the stack structure110. The string selection line cut SLC may separate at least one of the transparent conductive oxide layers112. A selection line separation layer142may be formed in the string selection line cut SLC. The selection line separation layer142may extend in the second horizontal direction D2. The selection line separation layer may include a silicon oxide, a silicon nitride, a silicon oxynitride, or a combination thereof.

Referring toFIG. 9, a trench T may be formed so as to expose the upper surface of the substrate102while extending through the lower dielectric layer104and the stack structure110. The trench T may be formed by anisotropic etching. The trench T may correspond to a word line cut. In some example embodiments, an interlayer dielectric layer144may be formed on the stack structure110before the trench T is formed.

Referring toFIG. 10, a buried layer150and a side spacer152may be formed in the trench T. In some example embodiments, the substrate102may be doped with an impurity to form an impurity region108before the buried layer150and the side spacer152are formed.

The buried layer150may include a conductive material such as tungsten, aluminum, copper, titanium, tantalum, nickel silicide, titanium silicide, tungsten silicide, cobalt silicide, and/or polysilicon. The side spacer152may include a silicon oxide, a silicon nitride, a silicon oxynitride, or a combination thereof.

Referring back toFIG. 2, a first upper dielectric layer160may be formed so as to cover the interlayer dielectric layer144. A sub-bit line plug161may be formed so as to extend through the interlayer dielectric layer144and the first upper dielectric layer160, and may be connected to the conductive pad140. A second upper dielectric layer162and a sub-bit line163may be formed on the first upper dielectric layer160. The sub-bit line163may be connected to the sub-bit line plug161. A third upper dielectric layer164and a bit line plug165may be formed on the second upper dielectric layer162. The bit line plug165may be connected to the sub-bit line163. A bit line166may be formed on the third upper dielectric layer164, and may be connected to the bit line plug165.

Each of the first upper dielectric layer160, the second upper dielectric layer162, and the third upper dielectric layer164may include a silicon oxide, a silicon nitride, a silicon oxynitride, or a combination thereof. Each of the sub-bit line plug161, the sub-bit line163, the bit line plug165, and the bit line166may include a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof.

As shown inFIGS. 5 to 10, the transparent conductive oxide layers112may not be removed, and may be used as a gate electrode of a memory cell. Since the transparent conductive oxide layers112are more transparent than an insulating material such as a metal, a metal nitride, or a silicon nitride, misalignment may be reduced in a photolithography process or an etching process. In addition, a process of removing the transparent conductive oxide layers112may be omitted, whereby the device manufacturing process may be simplified.

FIGS. 11-13are vertical cross-sectional views illustrating in a process order of a method of manufacturing a semiconductor device according to some example embodiments of inventive concepts.FIGS. 11-13are views illustrating a process of manufacturing the semiconductor device shown inFIG. 4.

Referring toFIG. 11, an information storage layer220may be formed on the resultant structure ofFIG. 6. The information storage layer220may be formed conformally along the inner surface of each channel hole CHH, the upper surface of the substrate102, and the upper surface of the stack structure110. The lower surface of the information storage layer220may be located at a lower level than the upper surface of the substrate102.

The lower surface of the information storage layer220may be etched to form a recess R1. The recess R1may be formed in the lower surface of each channel hole CHH, and may expose the upper surface of the substrate102. The recess R1may be formed by anisotropic etching, and a portion of the upper surface of the substrate102may be etched. The information storage layer220located at the side surface of each channel hole CHH may not be removed.

Referring toFIG. 12, a lower semiconductor layer206may be formed at the lower part of each channel hole CHH. The lower semiconductor layer26may be formed through selective epitaxial growth using the substrate102as a seed. In some example embodiments, the upper surface of the lower semiconductor layer206may be located at a higher level than the upper surface of the lowermost one of the transparent conductive oxide layers112. The information storage layer220may be disposed between the lowermost transparent conductive oxide layer112and the lower semiconductor layer206.

Referring toFIG. 13, a channel layer230and a buried dielectric layer235may be formed in each channel hole CHH to form a channel structure C. The channel layer230may be formed along the side surface of the information storage layer220and the upper surface of the lower semiconductor layer206. The buried dielectric layer235may be formed on the channel layer230. The channel structure C may extend through a portion of the upper surface of the substrate102, and may be electrically connected to the lower semiconductor layer206. A conductive pad140may be formed on the channel structure C.

FIG. 14is a vertical cross-sectional view of the semiconductor device according to some example embodiments of inventive concepts. A detailed description of the same construction as the semiconductor device shown inFIG. 2may be omitted.

Referring toFIG. 14, the semiconductor device300according to the present disclosure may have a cell-over-peripheral (COP) structure. In some example embodiments, the semiconductor device300may include a peripheral circuit structure PS disposed at the lower part of a stack structure110. The semiconductor device300may further include a lower conductive layer312, a channel structure C, a conductive pad140, and a buried layer350.

The peripheral circuit structure PS may include a substrate10, a device separation layer12, an impurity region14, a first lower dielectric layer20, a contact plug22, a peripheral circuit device24, a second lower dielectric layer30, a peripheral circuit wire32, and a third lower dielectric layer40. The substrate10may include the device separation layer12and the impurity region14. The first lower dielectric layer20, the contact plug22, and the peripheral circuit device24may be disposed on the substrate10. The impurity region14may be disposed adjacent to the peripheral circuit device24. The first lower dielectric layer20may cover the contact plug22and the peripheral circuit device24. The contact plug22may be electrically connected to the impurity region14. The second lower dielectric layer30may be disposed on a first upper dielectric layer160, and may cover the peripheral circuit wire32. The peripheral circuit wire32may be connected to the contact plug22. The third lower dielectric layer40may be disposed on the second lower dielectric layer30.

The lower conductive layer312may be disposed on the peripheral circuit structure PS. A stack structure110including a plurality of transparent conductive oxide layers112and a plurality of dielectric layers114may be disposed on the lower conductive layer312.

The channel structure C may extend through the stack structure110in the vertical direction. The channel structure C may extend through a portion of the upper surface of the substrate302, and may be electrically connected to the lower conductive layer312. The channel structure C may include an information storage layer320, a channel layer330, and a buried dielectric layer335. The channel layer330may be disposed inside the information storage layer320, and the buried dielectric layer335may be disposed inside the channel layer330.

The buried layer350may extend through the stack structure110and an interlayer dielectric layer144, and may abut the lower conductive layer312. The buried layer350may extend in the second horizontal direction D2. The buried layer350may include a silicon oxide, a silicon nitride, a silicon oxynitride, or a combination thereof.

FIG. 15is a partial enlarged view of the semiconductor device shown inFIG. 14.

Referring toFIG. 15, the information storage layer320may include a blocking layer322, a charge storage layer324, and a tunnel dielectric layer326. The charge storage layer324may be disposed inside the blocking layer322, and the tunnel dielectric layer326may be disposed inside the charge storage layer324.

The lower conductive layer312may include a recess R2formed in the upper surface thereof. The lower surface of the channel layer330may fill at least a portion of the recess R2. The outer circumference of the lower part of the channel layer330may be smaller than the outer circumference of the upper part of the channel layer330. The channel layer330may be formed conformally along the inner wall of the information storage layer220and the inner wall of the recess R2. However, the present disclosure is not limited thereto. The side surface of the recess R2may abut the information storage layer320. The lower surface of the information storage layer220may be located at a lower level than the upper surface of the lower conductive layer312. For example, the lower surface of the blocking layer322may be located at a lower level than the upper surface of the lower conductive layer312.

FIGS. 16-22are vertical cross-sectional views illustrating in a process order of a method of manufacturing a semiconductor device according to some example embodiments of inventive concepts.

Referring toFIG. 16, a peripheral circuit structure PS may be provided. The peripheral circuit structure PS may include a substrate10, a device separation layer12, an impurity region14, a first lower dielectric layer20, a contact plug22, a peripheral circuit device24, a second lower dielectric layer30, a peripheral circuit wire32, and a third lower dielectric layer40. The device separation layer12and the impurity region14may be formed at the upper surface of the substrate10. In some example embodiments, the device separation layer12may include an insulating material such as a silicon oxide or a silicon nitride. The impurity region14may include an n-type impurity or a p-type impurity.

The peripheral circuit device24may be formed adjacent to the impurity region14, and the first lower dielectric layer20may be formed so as to cover the peripheral circuit device24. The contact plug22may be connected to the impurity region14through the first lower dielectric layer20. The peripheral circuit wire32, which is connected to the contact plug22, may be formed on the first lower dielectric layer20. The second lower dielectric layer30and the third lower dielectric layer40may be formed so as to cover the peripheral circuit wire32.

Referring toFIG. 17, a lower conductive layer312and a stack structure110may be stacked on the peripheral circuit structure PS. The stack structure110may be disposed on the lower conductive layer312. The stack structure110may include a plurality of transparent conductive oxide layers112and a plurality of dielectric layers114, which are alternately stacked. In some example embodiments, the lower conductive layer312may include the same material as the transparent conductive oxide layers112.

Referring toFIG. 18, a plurality of channel holes CHH may be formed so as to extend through the lower conductive layer312and the stack structure110. The upper surface of the lower conductive layer312may be exposed through the channel holes CHH.

Referring toFIG. 19, an information storage layer320may be formed on the resultant structure ofFIG. 18. The information storage layer320may be formed conformally along the inner surface of each channel hole CHH, the upper surface of the lower conductive layer312, and the upper surface of the stack structure110. The information storage layer320may include a blocking layer322, a charge storage layer324, and a tunnel dielectric layer326, which are sequentially stacked.

Referring toFIG. 20, the information storage layer320may be etched to form a recess R2. The recess R2may be formed in the lower surface of each channel hole CHH, and may expose the upper surface of the lower conductive layer312. A portion of the upper surface of the lower conductive layer312may be etched. The information storage layer220located at the side surface of each channel hole CHH may not be removed.

Referring toFIG. 21, a channel layer330may be formed on the resultant structure ofFIG. 20. The channel layer330may be formed conformally along the side surface of the information storage layer320, the upper surface of the lower conductive layer312, and the upper surface of the stack structure110. The channel layer330may fill at least a portion of the recess R2, and may abut the lower conductive layer312.

Referring toFIG. 22, a buried dielectric layer335may be formed inside the channel layer330to form a channel structure C. The channel structure C may include an information storage layer320, a channel layer330, and a buried dielectric layer335. A conductive pad140may be formed on the channel structure C. A selection line separation layer142may be formed by etching a portion of the upper part of the stack structure110. The selection line separation layer142may extend in the second horizontal direction D2.

Referring back toFIG. 14, a sub-bit line plug161, a sub-bit line163, a bit line plug165, and a bit line166may be formed on the stack structure110so as to be electrically connected to the conductive pad140.

FIG. 23is a vertical cross-sectional view of the semiconductor device according to some example embodiments of inventive concepts.

Referring toFIG. 23, the semiconductor device400according to the present disclosure may include a source layer402, a support layer408, a gate electrode layer412, an interlayer dielectric layer444, a buried layer450, and a conductive line460. The semiconductor device400may further include a channel structure C including an information storage layer420, a channel layer430, and a buried dielectric layer435.

The source layer402, the conductive line460, and the support layer408may be sequentially disposed on a substrate102. The substrate102may be a semiconductor layer including a p-type impurity, and each of the source layer402and the support layer408may be a semiconductor layer including an n-type impurity. The conductive line460may include a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof.

A stack structure110may include a plurality of dielectric layers114and a plurality of gate electrode layers412, which are alternately stacked. Each gate electrode layer412may include a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof. The buried layer450may extend through the stack structure110and the interlayer dielectric layer444.

FIG. 24is a partial enlarged view of the semiconductor device shown inFIG. 23.

Referring toFIG. 24, the information storage layer420may include a blocking layer422, a charge storage layer424, and a tunnel dielectric layer426. The charge storage layer424may be disposed inside the blocking layer422, and the tunnel dielectric layer426may be disposed inside the charge storage layer424. The tunnel dielectric layer426may abut the channel layer430.

The conductive line460may extend through the information storage layer420, and may abut the side surface of the channel layer430. For example, the lower surface of the conductive line460may be located at a higher level than the lower surface of the channel layer430. The conductive line460may correspond to a common source line (CSL).

FIGS. 25-29are vertical cross-sectional views illustrating in a process order of a method of manufacturing a semiconductor device according to some example embodiments of inventive concepts.

Referring toFIG. 25, a source layer402may be formed on a substrate102. A sacrificial layer406and a support layer408may be sequentially stacked on the source layer402. Passivation layers404may be disposed at the upper part and the lower part of the sacrificial layer406. A stack structure110including a plurality of dielectric layers114and a plurality of transparent conductive oxide layers112may be disposed on the support layer408.

The source layer402may be a semiconductor layer including an n-type impurity. The support layer408may include polysilicon. Each passivation layer404may include a material having etch selectivity over the sacrificial layer406. In some example embodiments, each passivation layer404may include a silicon oxide, and the sacrificial layer406may include a silicon nitride.

Referring toFIG. 26, a plurality of channel holes CHH may be formed so as to extend through the stack structure110, the passivation layers404, the sacrificial layer406, and the support layer408. A portion of the upper surface of the source layer402may be etched, and the upper surface of the source layer402may be exposed through the channel holes CHH. In addition, the side surface of the sacrificial layer406may be exposed through the channel holes CHH.

Referring toFIG. 27, a channel structure C and a conductive pad140may be formed in each of the channel holes CHH. The channel structure C may include an information storage layer420, a channel layer430, and a buried dielectric layer435. The conductive pad140may be disposed on the channel structure C. The conductive pad140may cover the upper surface of the buried dielectric layer435, and may be electrically connected to the channel layer430. The sacrificial layer406may abut the side surface of the information storage layer420

Referring toFIG. 28, a trench T may be formed so as to expose the upper surface of the source layer402while extending through the stack structure110. The trench T may be formed by anisotropic etching. An interlayer dielectric layer444may be formed on the stack structure110before the trench T is formed. The side surfaces of the passivation layers404and the sacrificial layer406may be exposed through the trench T. The sacrificial layer406may be selectively removed such that the side surface of the channel structure C is exposed. Subsequently, the passivation layers404may be removed, and the upper surface of the source layer402may be exposed. A side spacer445may be formed at the side surface of the trench T before the passivation layers404and the sacrificial layer406are removed. The side spacer445may prevent the dielectric layers114and the transparent conductive oxide layers from being etched. The side spacer445may include a material having etch selectivity over the stack structure110, and may include, for example, polysilicon.

Referring toFIG. 29, a conductive line460may fill a space defined as the result of removal of the passivation layers404and the sacrificial layer406. Referring toFIG. 24, a portion of the side surface of the information storage layer420may be etched such that the channel layer430is exposed before the conductive line460is formed. The conductive line460may abut the side surface of the channel layer430. The conductive line460may include a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof.

The transparent conductive oxide layers112may be selectively removed, and gate electrode layers412may be formed in spaces defined as the result of removal of the transparent conductive oxide layers112. Each gate electrode layer412may include W, WN, Ti, TiN, Ta, TaN, or a combination thereof.

A buried layer450may be formed in the stack structure110, and may fill the trench T. A selection line separation layer142may be formed at the upper part of the stack structure110. The selection line separation layer142may separate at least one of the gate electrode layers412. Each of the buried layer450and the selection line separation layer142may include a silicon oxide, a silicon nitride, a silicon oxynitride, or a combination thereof.

Referring back toFIG. 23, a sub-bit line plug161, a sub-bit line163, a bit line plug165, and a bit line166may be formed on the stack structure110so as to be electrically connected to the conductive pad140.

FIG. 30is a vertical cross-sectional view of the semiconductor device according to some example embodiments of inventive concepts.

Referring toFIG. 30, the semiconductor device500may include a stack structure110including a plurality of transparent conductive oxide layers112and a plurality of dielectric layers114, which are alternately stacked. Referring toFIGS. 27 to 29, after the passivation layers404and the sacrificial layer406are removed and the conductive line460is formed, the transparent conductive oxide layers112may not be removed. In some example embodiments, a method of manufacturing the semiconductor device500may include etching a portion of the side surface of an information storage layer420to expose a channel layer430, forming a conductive line460at the lower part of a support layer408so as to abut the side surface of the channel layer430, anisotropically etching a portion of the conductive line460along a trench T, removing a side spacer445, and forming a buried layer450so as to fill the trench T while abutting a source layer402.

FIG. 31is a vertical cross-sectional view of the semiconductor device according to some example embodiments of inventive concepts.

Referring toFIG. 31, the semiconductor device600may include a lower stack structure610a, an upper stack structure610b, and a channel structure C extending through the lower stack structure610aand the upper stack structure610b. The semiconductor device600may further include a source layer402, a conductive line460, and a support layer408.

The lower stack structure610amay include a plurality of transparent conductive oxide layers612aand a plurality of dielectric layers614a, which are alternately stacked. The upper stack structure610bmay be stacked on the lower stack structure610a. The upper stack structure610bmay include a plurality of transparent conductive oxide layers612band a plurality of dielectric layers614b, which are alternately stacked. A lower channel hole CHHa may vertically extend through the lower stack structure610a. An upper channel hole CHHb may vertically extend through the upper stack structure610b, and may overlap the lower channel hole CHHa.

The channel structure C may vertically extend through the lower stack structure610aand the upper stack structure610b. For example, the channel structure C may be disposed in the lower channel hole CHHa and the upper channel hole CHHb. The horizontal width of the upper end of the lower channel hole CHHa may be larger than the horizontal width of the lower end of the upper channel hole CHHb. The side surface of the channel structure C may have a step at a point at which the lower stack structure610aand the upper stack structure610bjoin. The channel structure C may include an information storage layer620, a channel layer630, and a buried dielectric layer635.

FIGS. 32-34are vertical cross-sectional views illustrating in a process order of a method of manufacturing a semiconductor device according to some example embodiments of inventive concepts.

Referring toFIG. 32, a source layer402, a sacrificial layer406, and a support layer408may be provided on a substrate102. Passivation layers404may be disposed at the upper surface and the lower surface of the sacrificial layer406.

A lower stack structure610aincluding a plurality of transparent conductive oxide layers612aand a plurality of dielectric layers614a, which are alternately stacked, may be formed on the support layer408. A lower channel hole CHHa may vertically extend through the lower stack structure610a, and a channel sacrificial layer615may be formed so as to fill the lower channel hole CHHa. The channel sacrificial layer615may include a metal, a metal nitride, a metal oxide, polysilicon, a silicon oxide, a silicon nitride, a silicon oxynitride, or a combination thereof. In some example embodiments, a barrier layer may be formed inside the lower channel hole CHHa so as to cover the side surface and the lower surface of the channel sacrificial layer615.

Referring toFIG. 33, an upper stack structure610bincluding a plurality of transparent conductive oxide layers612band a plurality of dielectric layers614b, which are alternately stacked, may be stacked on the lower stack structure610a. The upper stack structure610bmay be anisotropically etched to form an upper channel hole CHHb. The upper channel hole CHHb may extend vertically through the upper stack structure610b, and may expose the upper surface of the channel sacrificial layer615.

Referring toFIG. 34, the channel sacrificial layer615may be selectively removed. A channel structure C may be formed in the lower channel hole CHHa and the upper channel hole CHHb. The channel structure C may include an information storage layer620, a channel layer630, and a buried dielectric layer635. The information storage layer620and the channel layer630may be formed conformally at the inner walls of the lower channel hole CHHa and the upper channel hole CHHb. The buried dielectric layer635may fill the interiors of the lower channel hole CHHa and the upper channel hole CHHb.

Referring back toFIG. 31, the sacrificial layer406and the passivation layers404may be removed, and a conducive line460may be formed. The conducive line460may abut the side surface of the channel layer630. Subsequently, a buried layer450may be formed so as to extend through the lower stack structure610aand the upper stack structure610b, and a sub-bit line plug161, a sub-bit line163, a bit line plug165, and a bit line166may be formed on the upper stack structure610b.

FIG. 35is a vertical cross-sectional view of the semiconductor device according to some example embodiments of inventive concepts.

Referring toFIG. 35, the semiconductor device700may include an upper junction layer702disposed at the lower part of a stack structure110, a lower junction layer704disposed on a peripheral circuit structure PS, and a channel structure C extending vertically through the stack structure110. The lower surface of the upper junction layer702may abut and be electrically connected to the upper surface of the lower junction layer704. The channel structure C may include an information storage layer720, a channel layer730, and a buried dielectric layer735. The upper junction layer702may be connected to the channel structure C. The lower junction layer704may be connected to a peripheral circuit wire32. In some example embodiments, the upper junction layer702and the lower junction layer704may be a line extending in one direction, and the upper junction layer702and the lower junction layer704may extend in different directions. The semiconductor device700may further include a dielectric layer formed in the upper junction layer702so as to extend through the upper junction layer702. In addition, the semiconductor device700may further include a dielectric layer formed in the lower junction layer704so as to extend through the lower junction layer704.

FIGS. 36-39are vertical cross-sectional views illustrating in a process order of a method of manufacturing a semiconductor device according to some example embodiments of inventive concepts.

Referring toFIG. 36, a lower dielectric layer104may be formed on a substrate102. A stack structure110may include a plurality of transparent conductive oxide layers112and a plurality of dielectric layers114, which are alternately stacked, and may be formed on the lower dielectric layer104. A channel structure C may be formed so as to extend vertically through a portion of the substrate102, the lower dielectric layer104, and the stack structure110. The channel structure C may include an information storage layer720, a channel layer730, and a buried dielectric layer735, and the lower surface of the channel structure C may be located at a lower level than the upper surface of the substrate102. A conductive pad140may be formed at the upper surface of the channel structure C.

Referring toFIG. 37, a buried layer150may be formed adjacent to the channel structure C. The buried layer150may extend vertically through the stack structure110, and a side spacer152may be formed at the side surface of the buried layer150. A sub-bit line plug161, a sub-bit line163, a bit line plug165, and a bit line166may be formed on the stack structure110.

Referring toFIG. 38, the substrate102may be removed. In some example embodiments, a carrier may be formed on the bit line166, the substrate102may be turned over such that the lower surface of the substrate102faces upwards, and the substrate102may be removed. The substrate102may be removed through a planarization process, such as a chemical mechanical polishing process. In the process of removing the substrate102, a portion of the lower part of the channel structure C may be removed, and the channel layer730may be exposed. The information storage layer720, the channel layer730, and the buried dielectric layer735may be coplanar with the lower surface of the lower dielectric layer104.

Referring toFIG. 39, an upper junction layer702may be formed so as to cover exposed portions of the lower dielectric layer104, the buried layer150, the information storage layer720, the channel layer730, and the buried dielectric layer735. The upper junction layer702may include a semiconductor material, such as polysilicon, and/or a metal material.

Referring back toFIG. 35, the lower junction layer704formed on the peripheral circuit structure PS may be joined to the upper junction layer702. The lower junction layer704may include the same material as the upper junction layer702. The channel layer730may be electrically connected to the peripheral circuit wire32of the peripheral circuit structure PS via the upper junction layer702and the lower junction layer704.

As is apparent from the above description, according to example embodiments of the present disclosure, a transparent conductive oxide layer may be used in a stack structure, whereby a manufacturing process may be simplified and production cost may be reduced.

While example embodiments of inventive concepts have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of inventive concepts and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.