THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SILICON OXYCARBIDE LINERS AND METHODS OF FORMING THE SAME

A memory device includes an alternating stack of insulating layers and electrically conductive layers, such that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film containing a continuous memory material layer which continuously extends through the entire alternating stack.

FIELD

The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device containing silicon oxycarbide liners and methods of forming the same.

BACKGROUND

Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High-Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.

SUMMARY

According to an aspect of the present disclosure, a memory device includes an alternating stack of insulating layers and electrically conductive layers, such that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film containing a continuous memory material layer which continuously extends through the entire alternating stack.

According to another aspect of the present disclosure, a method of forming a memory device comprises forming a vertical repetition of multiple instances of a repetition unit over a substrate, wherein the repetition unit comprises, from bottom to top, an insulating layer, a first silicon oxycarbide liner, a sacrificial material layer, and a second silicon oxycarbide liner; forming a memory opening through the vertical repetition; forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises a memory film that includes, from outside to inside, a dielectric metal oxide blocking dielectric layer, a silicon oxide blocking dielectric layer, a continuous memory material layer, and a tunneling dielectric layer, and further comprises a vertical semiconductor channel that is formed on the memory film; forming backside recesses by removing the sacrificial material layers selective to the first and the second silicon oxycarbide liners; and forming electrically conductive layers in the backside recesses.

DETAILED DESCRIPTION

As discussed above, the embodiments of the present disclosure are directed to a three-dimensional memory device containing silicon oxycarbide liners and methods of forming the same, the various aspects of which are described below. The embodiments provide enhanced word line edge shape with reduced corner rounding, which reduces short channel effects.

As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/cm to 1.0×105S/cm upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105S/cm. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−6S/cm.

As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material either as formed as a crystalline material or if converted into a crystalline material through an anneal process (for example, from an initial amorphous state), i.e., to have electrical conductivity greater than 1.0×105S/cm. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.

Generally, a semiconductor die, or a semiconductor package, can include a memory chip. Each semiconductor package contains one or more dies (for example one, two, or four). The die is the smallest unit that can independently execute commands or report status. Each die contains one or more planes (typically one or two). Identical, concurrent operations can take place on each plane, although with some restrictions. Each plane contains a number of blocks, which are the smallest unit that can be erased by in a single erase operation. Each block contains a number of pages, which are the smallest unit that can be programmed, i.e., a smallest unit on which a read operation can be performed.

Referring toFIG.1, a first exemplary structure according to a first embodiment of the present disclosure is illustrated. The first exemplary structure comprises a substrate8, which may be a semiconductor substrate, an insulating substrate, a conductive substrate, or a combination thereof. The substrate8comprises a substrate material layer9, which may or may not be a semiconductor material layer. In one embodiment, the substrate8may8may comprise a semiconductor substrate consisting essentially of a single crystalline semiconductor material or a polycrystalline semiconductor material. In one embodiment, the substrate8may be a commercially available silicon wafer on which a plurality of semiconductor dies, such as a two-dimensional array of semiconductor dies, can be subsequently formed. In this case, the substrate material layer9may comprise a doped well in the silicon wafer or an epitaxial silicon layer located on the silicon wafer. In case the substrate8comprises a semiconductor substrate, semiconductor devices620may optionally be formed on top of the substrate8. Generally, the semiconductor devices620may comprise any type of semiconductor devices known in the art. In one embodiment, the semiconductor devices620may comprise complementary metal-oxide-semiconductor (CMOS) field effect transistors of a peripheral circuit for controlling operation of a three-dimensional memory device to be subsequently formed thereabove.

Optionally, metal interconnect structures680embedded within dielectric material layers660may be formed above the substrate8. The metal interconnect structures680are also referred to as lower-level metal interconnect structures680, and the dielectric material layers660are also referred to lower-level dielectric material layers660. In case the semiconductor devices620are present, the lower-level metal interconnect structures680may provide electrical connection to the semiconductor devices620. In one embodiment, the metal interconnect structures680may comprise metal pads682, which may be employed as a contact pad for connection via structures to be subsequently formed. Alternatively, the formation of the semiconductor devices620, metal interconnect structures680and dielectric material layers660over the substrate8may be omitted. Instead, the semiconductor devices620may be formed over a separate substrate and then bonded to the three-dimensional memory device.

In case the lower-level dielectric material layers660are present, a semiconductor material layer (e.g., polysilicon layer)10may be formed over the lower-level dielectric material layers660. The semiconductor material layer10may comprise a single semiconductor material layer, or may comprise a vertical stack of multiple semiconductor material sublayers. In one embodiment, the semiconductor material layer10may have a doping of a first conductivity type, which may be p-type or n-type. In one embodiment, in-process source-level material layers may be formed in lieu of the semiconductor material layer10. In this case, the in-process source-level material layers may comprise a vertical stack including a lower source semiconductor layer, a source-level sacrificial layer that is subsequently replaced with a source contact layer, and an upper source semiconductor layer. In case the lower-level dielectric material layers660are not employed, the semiconductor material layer10may be omitted. While an embodiment is described in which a semiconductor material layer10is employed, embodiments are expressly contemplated herein in which the semiconductor material layer is replaced with in-process source-level material layers or is omitted.

A vertical repetition of multiple instances of a repetition unit of an insulating layer32, a first silicon oxycarbide liner332, a sacrificial material layer, and a second silicon oxycarbide liner332can be formed over the substrate. The insulating layers32comprise an insulating material, such as a silicon oxide material. The sacrificial material layers42comprise a sacrificial material that can be removed selective to the insulating material of the insulating layers32. As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The first silicon oxycarbide liners332and the second silicon oxycarbide liners332comprise a silicon oxycarbide material containing at least 10 atomic percent of each of silicon, oxygen and carbon.

The bottommost one of the insulating layers32is herein referred to as a bottommost insulating layer32B. The topmost one of the insulating layers32is herein referred to as a topmost insulating layer32T. In one embodiment, the insulating layers32comprise a silicon oxide material, such as undoped silicate glass or a doped silicate glass.

The sacrificial material layers42may comprise an insulating material, a semiconductor material, or a conductive material. Non-limiting examples of the sacrificial material of the sacrificial material layers42include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the sacrificial material layers42can be spacer material layers that comprise silicon nitride or a semiconductor material including at least one of silicon and germanium.

The oxycarbide material of the first silicon oxycarbide liners332and the second silicon oxycarbide liners332may have a material composition of SiCxO2(1-x), in which x greater than 0.1 and is less than 0.9, and/or greater than 0.2 and less than 0.8, and/or greater than 0.3 and less than 0.7.

The insulating layers32can be deposited, for example, by chemical vapor deposition (CVD). The sacrificial material layers42can be formed, for example, CVD or atomic layer deposition (ALD). The first silicon oxycarbide liners332and the second silicon oxycarbide liners332can be deposited by CVD or ALD. In an illustrative example, the insulating layers32may comprise undoped silicate glass that is deposited by plasma-assisted decomposition of tetraethylorthosilicate (TEOS). The sacrificial material layers42may comprise silicon nitride deposited by plasma-enhanced chemical vapor deposition, and the first and second silicon oxycarbide liners322may be deposited by a plasma-assisted chemical vapor deposition process employing silane and carbon dioxide as precursor gases.

In one embodiment, the silicon oxycarbide liners332are thinner than the insulating layers32and the sacrificial material layers42. The thicknesses of the insulating layers32and the sacrificial material layers42can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each insulating layer32and for each sacrificial material layer42. The thickness of each of the first silicon oxycarbide liners332and the second silicon oxycarbide liners332can be in a range from 0.5 nm to 4 nm, and/or from 1.0 nm to 2.5 nm, although lesser and greater thicknesses may also be employed. The number of repetitions of the pairs of an insulating layer32and a sacrificial material layer42can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed.

The first exemplary structure may comprise a memory array region100in which memory stack structures are to be subsequently formed, and a contact region300in which stepped surfaces and contact via structures are to be subsequently formed.

Each sacrificial material layer42other than a topmost sacrificial material layer42within the vertical repetition (32,42,332) laterally extends farther than any overlying sacrificial material layer42within the vertical repetition (32,42,332) in the terrace region. The terrace region includes stepped surfaces of the vertical repetition (32,42,332) that continuously extend from a bottommost layer within the vertical repetition (32,42,332) to a topmost layer within the vertical repetition (32,42,332).

Each vertical step of the stepped surfaces can have the height of one or more pairs of an insulating layer32and a sacrificial material layer. In one embodiment, each vertical step can have the height of a single pair of an insulating layer32and a sacrificial material layer42. In another embodiment, multiple “columns” of staircases can be formed along a first horizontal direction hd1such that each vertical step has the height of a plurality of pairs of an insulating layer32and a sacrificial material layer42, and the number of columns can be at least the number of the plurality of pairs. Each column of staircase can be vertically offset among one another such that each of the sacrificial material layers42has a physically exposed top surface in a respective column of staircases. In the illustrative example, two columns of staircases are formed for each block of memory stack structures to be subsequently formed such that one column of staircases provide physically exposed top surfaces for odd-numbered sacrificial material layers42(as counted from the bottom) and another column of staircases provide physically exposed top surfaces for even-numbered sacrificial material layers (as counted from the bottom). Configurations employing three, four, or more columns of staircases with a respective set of vertical offsets among the physically exposed surfaces of the sacrificial material layers42may also be employed. Each sacrificial material layer42has a greater lateral extent, at least along one direction, than any overlying sacrificial material layers42such that each physically exposed surface of any sacrificial material layer42does not have an overhang. In one embodiment, the vertical steps within each column of staircases may be arranged along the first horizontal direction hd1, and the columns of staircases may be arranged along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1may be perpendicular to the boundary between the memory array region100and the contact region300.

Optionally, drain-select-level isolation structures72can be formed through the topmost insulating layer32T and a subset of the sacrificial material layers42located at drain-select-levels. The drain-select-level isolation structures72can be formed, for example, by forming drain-select-level isolation trenches and filling the drain-select-level isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the topmost insulating layer32T.

Referring toFIGS.4A and4B, a lithographic material stack (not shown) including at least a photoresist layer can be formed over the topmost insulating layer32T and the retro-stepped dielectric material portion65, and can be lithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region100and a second set of openings formed over the contact region300. The pattern in the lithographic material stack can be transferred through the topmost insulating layer32T or the retro-stepped dielectric material portion65, and through the vertical repetition (32,42,332) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the vertical repetition (32,42,332) underlying the openings in the patterned lithographic material stack are etched to form memory openings49and support openings19. As used herein, a “memory opening” refers to a structure in which memory elements, such as a memory stack structure, is subsequently formed. As used herein, a “support opening” refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The memory openings49are formed through the topmost insulating layer32T and the entirety of the vertical repetition (32,42,332) in the memory array region100. The support openings19are formed through the retro-stepped dielectric material portion65and the portion of the vertical repetition (32,42,332) that underlie the stepped surfaces in the contact region300.

The memory openings49extend through the entirety of the vertical repetition (32,42,332). The support openings19extend through a subset of layers within the vertical repetition (32,42,332). The chemistry of the anisotropic etch process employed to etch through the materials of the vertical repetition (32,42,332) may be modulated (i.e., periodically changed) to optimize etching of the various materials in the vertical repetition (32,42,332). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the memory openings49and the support openings19can be substantially vertical, or can be tapered. The patterned lithographic material stack can be subsequently removed, for example, by ashing.

The memory openings49and the support openings19can extend from the top surface of the vertical repetition (32,42,332) to at least the horizontal plane including the topmost surface of the semiconductor material layer10. In one embodiment, an overetch into the semiconductor material layer10may be optionally performed after the top surface of the semiconductor material layer10is physically exposed at a bottom of each memory opening49and each support opening19. The overetch may be performed prior to, or after, removal of the lithographic material stack. In other words, the recessed surfaces of the semiconductor material layer10may be vertically offset from the un-recessed top surfaces of the semiconductor material layer10by a recess depth. The recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be employed. The overetch is optional, and may be omitted. If the overetch is not performed, the bottom surfaces of the memory openings49and the support openings19can be coplanar with the topmost surface of the semiconductor material layer10.

Each of the memory openings49and the support openings19may include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the semiconductor material layer10. A two-dimensional array of memory openings49can be formed in the memory array region100. A two-dimensional array of support openings19can be formed in the contact region300.

FIGS.5A-5Fare sequential schematic vertical cross-sectional views of a memory opening49within the first exemplary structure during formation of a memory opening fill structure58according to the first embodiment of the present disclosure.

FIG.5Aillustrates a memory opening after the processing steps ofFIGS.4A and4B.

Referring toFIG.5B, an optional pedestal channel portion11can be formed at the bottom portion of each memory opening49and each support openings19, for example, by a selective semiconductor deposition process. In one embodiment, the pedestal channel portion11can be doped with electrical dopants of the same conductivity type as the semiconductor material layer10, which is a first conductivity type. In one embodiment, the top surface of each pedestal channel portion11can be formed below a horizontal plane including the top surface of the bottommost insulating layer32B. The pedestal channel portion11can be a portion of a transistor channel that extends between a source region to be subsequently formed in the semiconductor material layer10and a drain region to be subsequently formed in an upper portion of the memory opening49. A memory cavity49′ is present in the unfilled portion of the memory opening49above the pedestal channel portion11. If the semiconductor material layer10comprises a single crystalline semiconductor material, the pedestal channel portion11may comprise a single crystalline semiconductor material in epitaxial alignment with the single crystalline semiconductor material of the semiconductor material layer10. In one embodiment, the pedestal channel portion11can comprise single crystalline silicon.

Referring toFIG.5C, a memory film50can be formed by a series of conformal deposition processes. The memory film50may include, from bottom to top above the topmost insulating layer32T or from outside to inside within each memory opening49, a silicon oxide liner51, a dielectric metal oxide blocking dielectric layer52, a silicon oxide blocking dielectric layer53, a memory material layer54, and a tunneling dielectric layer56.

The silicon oxide liner51comprises, and/or consists essentially of, a silicon oxide material, such as undoped silicate glass. In one embodiment, the silicon oxide liner51can be formed by a low pressure chemical vapor deposition (LPCVD) process employing thermal decomposition of tetraethylorthosilicate (TEOS). The thickness of the silicon oxide liner51may be in a range from 1 nm to 12 nm, such as from 3 nm to 8 nm, although lesser and greater thicknesses may also be employed.

The dielectric metal oxide blocking dielectric layer52comprises a dielectric metal oxide material having a dielectric constant greater than 7.9. Exemplary dielectric metal oxide materials that may be employed for the dielectric metal oxide blocking dielectric layer52include, but are not limited to, aluminum oxide, hafnium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, dielectric oxides of other transition metals, or alloys or layer stacks thereof. The dielectric metal oxide blocking dielectric layer52can be deposited by a conformal deposition process, such as an atomic layer deposition (ALD) process. The thickness of the dielectric metal oxide blocking dielectric layer52may be in a range from 1 nm to 12 nm, such as from 3 nm to 8 nm, although lesser and greater thicknesses may also be employed.

The memory material layer54may comprise any memory material such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store data bits in the form of presence or absence of electrical charges, a direction of ferroelectric polarization, electrical resistivity, or another measurable physical parameter. In one embodiment, the memory material layer54can be a continuous silicon nitride layer. In one embodiment, the sacrificial material layers42and the insulating layers32can have vertically coincident sidewalls, and the memory material layer54can be formed as a single continuous layer. Generally, the memory material layer54may comprise a vertical stack of memory elements that are located at levels of the sacrificial material layers42. For example, the vertical stack of memory elements may comprise annular portions of the memory material layer54located at levels of the sacrificial material layers42.

The tunneling dielectric layer56can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer56can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer56can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the tunneling dielectric layer56can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

Optionally, a sacrificial cover layer (not shown) may be formed over the memory film50.

Referring toFIG.5D, the optional sacrificial cover material layer (not shown), the tunneling dielectric layer56, the memory material layer54, the silicon oxide blocking dielectric layer53, the dielectric metal oxide blocking dielectric layer52, and the silicon oxide liner51are sequentially anisotropically etched employing at least one anisotropic etch process. The portions of the sacrificial cover material layer, the tunneling dielectric layer56, the memory material layer54, the silicon oxide blocking dielectric layer53, the dielectric metal oxide blocking dielectric layer52, and the silicon oxide liner51located above the top surface of the topmost insulating layer32T can be removed by the at least one anisotropic etch process. Further, the horizontal portions of the sacrificial cover material layer, the tunneling dielectric layer56, the memory material layer54, the silicon oxide blocking dielectric layer53, the dielectric metal oxide blocking dielectric layer52, and the silicon oxide liner51at a bottom of each memory cavity49′ can be removed to form openings in remaining portions thereof. Each of the sacrificial cover material layer, the tunneling dielectric layer56, the memory material layer54, the silicon oxide blocking dielectric layer53, the dielectric metal oxide blocking dielectric layer52, and the silicon oxide liner51can be etched by a respective anisotropic etch process employing a respective etch chemistry, which may or may not be the same for the various material layers.

Each remaining portion of the sacrificial cover material layer (if present) can have a tubular configuration. A surface of the pedestal channel portion11(or a surface of the semiconductor material layer10in case a pedestal channel portions11is not employed) can be physically exposed underneath the opening through the sacrificial cover material layer, the tunneling dielectric layer56, the memory material layer54, the silicon oxide blocking dielectric layer53, the dielectric metal oxide blocking dielectric layer52, and the silicon oxide liner51at the bottom of each memory cavity49′. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity49′ is vertically offset from the topmost surface of the pedestal channel portion11(or of the semiconductor material layer10in case pedestal channel portions11are not employed) by a recess distance. The sacrificial cover material layer can be subsequently removed selective to the material of the tunneling dielectric layer56. In case the sacrificial cover material layer includes a semiconductor material, a wet etch process employing hot trimethyl-2 hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) can be performed to remove the sacrificial cover material layer. Alternatively, the sacrificial cover material layer may be retained in the final device if it comprises a semiconductor material.

Referring toFIG.5E, a semiconductor channel layer60L can be deposited directly on the semiconductor surface of the pedestal channel portion11(or the semiconductor material layer10if the pedestal channel portion11is omitted), and directly on the memory film50. The semiconductor channel layer60L includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer60L includes amorphous silicon or polysilicon. The semiconductor channel layer60L can have a doping of a first conductivity type, which is the same as the conductivity type of the semiconductor material layer10and the pedestal channel portions11. The semiconductor channel layer60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer60L can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The semiconductor channel layer60L may partially fill the memory cavity49′ in each memory opening, or may fully fill the cavity in each memory opening.

A dielectric core layer can be deposited to fill any remaining portion of the memory cavity49′ within each memory opening49. The dielectric core layer includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating. The horizontal portion of the dielectric core layer can be removed, for example, by a recess etch process such that each remaining portions of the dielectric core layer is located within a respective memory opening49and has a respective top surface below the horizontal plane including the top surface of the topmost insulating layer32T. Each remaining portion of the dielectric core layer constitutes a dielectric core62.

Referring toFIG.5F, a doped semiconductor material having a doping of a second conductivity type can be deposited within each recessed region above the dielectric cores62. The deposited semiconductor material can have a doping of a second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in a range from 5.0×1018/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

Excess portions of the deposited semiconductor material having a doping of the second conductivity type and a horizontal portion of the semiconductor channel layer60L can be removed from above the horizontal plane including the top surface of the topmost insulating layer32T, for example, by chemical mechanical planarization (CMP) or a recess etch process. Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region63. Each remaining portion of the semiconductor channel layer60L (which has a doping of the first conductivity type) constitutes a vertical semiconductor channel60.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a vertical semiconductor channel60, the tunneling dielectric layer56, a plurality of memory elements (comprising portions of the memory material layer54located at the levels of the sacrificial material layers42), the silicon oxide blocking dielectric layer53, the dielectric metal oxide blocking dielectric layer52, and the silicon oxide liner51. Each contiguous combination of a pedestal channel portion11(if present), a memory stack structure55, a dielectric core62, and a drain region63that fills a respective memory opening49is herein referred to as a memory opening fill structure58. Each contiguous combination of a pedestal channel portion11(if present), a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63that fills a respective support opening19is herein referred to as a support pillar structure.

Generally, a vertical semiconductor channel60is formed on each memory film50. Each memory film50comprises, from outside to inside, a silicon oxide liner51, a dielectric metal oxide blocking dielectric layer52, a silicon oxide blocking dielectric layer53, a memory material layer54, and a tunneling dielectric layer56. The silicon oxide liner51laterally surrounds and contacts the dielectric metal oxide blocking dielectric layer52.

Referring toFIG.6, the exemplary structure is illustrated after formation of memory opening fill structures58and support pillar structure20within the memory openings49and the support openings19, respectively. An instance of a memory opening fill structure58can be formed within each memory opening49of the structure ofFIGS.4A and4B. An instance of the support pillar structure20can be formed within each support opening19of the structure ofFIGS.4A and4B.

Referring toFIGS.7A and7B, a contact-level dielectric layer80can be formed over the vertical repetition (32,42,332) of insulating layer32and sacrificial material layers42, and over the memory opening fill structures58and the support pillar structures20. The contact-level dielectric layer80includes a dielectric material that is different from the dielectric material of the sacrificial material layers42. For example, the contact-level dielectric layer80can include silicon oxide. The contact-level dielectric layer80can have a thickness in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer (not shown) can be applied over the contact-level dielectric layer80, and is lithographically patterned to form openings in areas between clusters of memory stack structures55. The pattern in the photoresist layer can be transferred through the contact-level dielectric layer80, the vertical repetition (32,42,332) and/or the retro-stepped dielectric material portion65employing an anisotropic etch to form backside trenches79, which vertically extend from the top surface of the contact-level dielectric layer80at least to the top surface of the semiconductor material layer10, and laterally extend through the memory array region100and the contact region300.

In one embodiment, the backside trenches79can laterally extend along the first horizontal direction hd1(which may be a word line direction), and can be laterally spaced apart among one another along the second horizontal direction hd2(which can be a bit line direction) that is perpendicular to the first horizontal direction hd1. The memory stack structures55can be arranged in rows that extend along the first horizontal direction hd1. The drain-select-level isolation structures72can laterally extend along the first horizontal direction hd1. Each backside trench79can have a uniform width that is invariant along the lengthwise direction (i.e., along the first horizontal direction hd1). Each drain-select-level isolation structure72can have a uniform vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction hd1that is invariant with translation along the first horizontal direction hd1. Multiple rows of memory opening fill structures58can be located between a neighboring pair of a backside trench79and a drain-select-level isolation structure72, or between a neighboring pair of drain-select-level isolation structures72. In one embodiment, the backside trenches79can include a source contact opening in which a source contact via structure can be subsequently formed. The photoresist layer can be removed, for example, by ashing. Generally, backside trenches79laterally extending along the first horizontal direction hd1can be formed through the contact-level dielectric layer80and the vertical repetition (32,42,332). The vertical repetition (32,42,332) as formed at the processing steps ofFIG.2is divided into multiple alternating stacks (32,42) that are laterally spaced apart along the second horizontal direction hd2by the backside trenches79.

Dopants of the second conductivity type can be implanted into physically exposed surface portions of the semiconductor material layer10(which may be surface portions of the semiconductor material layer10) that are located at the bottom of the backside trenches by an ion implantation process. A source region61can be formed at a surface portion of the semiconductor material layer10under each backside trench79. Each source region61is formed in a surface portion of the semiconductor material layer10that underlies a respective backside trench79. Due to the straggle of the implanted dopant atoms during the implantation process and lateral diffusion of the implanted dopant atoms during a subsequent activation anneal process, each source region61can have a lateral extent greater than the lateral extent of the lateral extent of the overlying backside trench79.

An upper portion of the semiconductor material layer10that extends between the source region61and the vertical semiconductor channels60in the memory opening fill structures58constitutes a horizontal semiconductor channel59for a plurality of field effect transistors. The horizontal semiconductor channel59is connected to multiple vertical semiconductor channels60.

Referring toFIG.8, an etchant that selectively etches the sacrificial material layers42with respect to the first material of the insulating layers32and the silicon oxycarbide liners332can be introduced into the backside trenches79, for example, employing an etch process. Backside recesses43are formed in volumes from which the sacrificial material layers42are removed. The removal of the sacrificial material layers42can be selective to the first material of the insulating layers32, the material of the silicon oxycarbide liners332, the material of the retro-stepped dielectric material portion65, the semiconductor material of the semiconductor material layer10, and the material of the outermost layer of the memory films50(such as the silicon oxide liner51). In one embodiment, the sacrificial material layers42can include silicon nitride, and the materials of the insulating layers32and the retro-stepped dielectric material portion65can be selected from silicon oxide and dielectric metal oxides.

The etch process that etches the sacrificial material layers42selective to the insulating layers32, the silicon oxycarbide liners322, and the outermost layer of the memory films50can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trenches79. For example, if the sacrificial material layers42include silicon nitride, the etch process can be a wet etch process in which the first exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. The support pillar structure20, the retro-stepped dielectric material portion65, and the memory stack structures55provide structural support while the backside recesses43are present within volumes previously occupied by the sacrificial material layers42.

Each backside recess43can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess43can be greater than the height of the backside recess43. A plurality of backside recesses43can be formed in the volumes from which the sacrificial material layers42are removed. The memory openings in which the memory stack structures55are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses43. Each of the plurality of backside recesses43can extend substantially parallel to the top surface of the semiconductor material layer10. A backside recess43can be vertically bounded by a top surface of an underlying silicon oxycarbide liner322(such as a first silicon oxycarbide liner) and a bottom surface of an overlying silicon oxycarbide liner322(such as a second silicon oxycarbide liner). In one embodiment, each backside recess43can have a uniform height throughout.

FIGS.9A-9Care sequential vertical cross-sectional views of a region around a memory opening fill structure58in a first configuration of the first exemplary structure during formation of electrically conductive layers46according to the first embodiment of the present disclosure.

Referring toFIG.9A, a region around a memory opening fill structure58in the first configuration of the first exemplary structure is illustrated after the processing steps ofFIG.8. The isotropic etch process that etches the sacrificial material layers42may be selective to the materials of the insulating layers32, the silicon oxycarbide liners332, and the silicon oxide liner51.

Referring toFIG.9B, an isotropic etch process that etches the material of the silicon oxide liner51is performed. The etch chemistry of the isotropic etch process is selected such that the isotropic etch process etches the material of the silicon oxide liner51(i.e., a silicon oxide material) at a higher etch rate than the material of the silicon oxycarbide liners332. In other words, the isotropic etch process etches a material of the silicon oxide liner at a higher etch rate than materials of the first silicon oxycarbide liners332and the second silicon oxycarbide liners332.

In an illustrative example, the silicon oxide liner51may comprise silicon dioxide, and the isotropic etch process may comprise dilute hydrofluoric acid or buffered hydrofluoric acid. An etch rate of a silicon oxycarbide material formed by chemical vapor deposition employing silane and carbon dioxide as precursor gases in 500:1 dilute hydrofluoric acid is about 2.2 nm/minute. An etch rate of silicon dioxide formed by decomposition of tetraethylorthosilicate glass in 500:1 dilute hydrofluoric acid is about 11.8 nm/minute. The ratio of the etch rate of the silicon oxycarbide material to the etch rate of the silicon oxide material is about 0.18 in this case. The use of buffered hydrofluoric acid as the etching liquid provides a ratio of about 0.48 between the etch rate of a silicon oxycarbide material and the etch rate of a silicon oxide material.

Generally, the etch rate of the silicon oxycarbide liners322may be significantly less than the etch rate of the silicon oxide material of the silicon oxide liner51. In one embodiment, the etch rate of the silicon oxycarbide liners322is less than 50% of the etch rate of the silicon oxide material of the silicon oxide liner51. In one embodiment, the etch rate of the silicon oxycarbide liners322is less than 20% of the etch rate of the silicon oxide material of the silicon oxide liner51.

In one embodiment, the thickness of the silicon oxide liner51, the thickness of the silicon oxycarbide liners332, and the chemistry and the duration of the isotropic etch process can be selected such that cylindrical portions of the silicon oxide liner51are removed at each level of the backside recesses43without completely removing the silicon oxycarbide liners332. Cylindrical segments of the outer sidewall of a dielectric metal oxide blocking dielectric layer52can be physically exposed to the backside recesses43around each memory opening fill structure58. The silicon oxide liner51of each memory opening fill structure58can be divided into a plurality of discrete silicon oxide portions having a respective tubular configuration, which is herein referred to as a vertical stack of tubular silicon oxide spacers51′.

Each of the first silicon oxycarbide liners332and the second silicon oxycarbide liners332may be thinned. In one embodiment, the thickness of each of the first silicon oxycarbide liners332and the second silicon oxycarbide liners332prior to the isotropic etch process may be in a range from 0.5 nm to 4 nm, and/or from 1.0 nm to 2.5 nm, and the thickness of each of the first silicon oxycarbide liners332and the second silicon oxycarbide liners332after the isotropic etch process may be in a range from 0.25 nm to 2 nm, and/or from 0.5 nm to 1.2 nm. Generally, the thickness decrease of each of the first silicon oxycarbide liners332and the second silicon oxycarbide liners332may be in a range from 25% to 75% of the initial thickness of a respective silicon oxycarbide liner332.

Generally, portions of the silicon oxide liner51can be removed from around the backside recesses43by performing an isotropic etch process. Outer cylindrical surface segments of the dielectric metal oxide blocking dielectric layer52are exposed after the isotropic etch process. Remaining portions of the silicon oxide liner51comprise a vertical stack of tubular silicon oxide spacers51′. The memory film50comprises a vertical stack of tubular silicon oxide spacers51′ in contact with the respective insulating layers32.

The isotropic etch process etches the silicon oxide liner51isotropically. As such, concave annular surfaces are formed on each of the tubular silicon oxide spacers51′. Annular divots43D are formed by the isotropic etch process between the dielectric metal oxide blocking dielectric layer52and the first and second silicon oxycarbide liners332. In one embodiment, a plurality of tubular silicon oxide spacers51′ may comprise a respective upper concave annular surface and a respective lower concave annular surface having a respective radius of curvature that is the same as or greater than the thickness of each tubular silicon oxide spacer51′ (i.e., the lateral distance between an inner cylindrical sidewall and an outer cylindrical sidewall).

Referring toFIGS.9C and11, at least one conductive material can be deposited in the backside recesses43and in the divots43D by providing at least one reactant gas into the backside recesses43through the backside trenches79. A metallic barrier layer46A can be deposited in the backside recesses43. The metallic barrier layer46A includes an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for a metallic fill material to be subsequently deposited. The metallic barrier layer46A can include a conductive metallic nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer46A can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metallic barrier layer46A can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the metallic barrier layer46A can consist essentially of a conductive metal nitride such as TiN.

A metal fill material is deposited in the plurality of backside recesses43, on the sidewalls of the at least one the backside trench79, and over the top surface of the contact-level dielectric layer80to form a metallic fill material layer46B. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer46B can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer46B can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic fill material layer46B can consist essentially of a single elemental metal. In one embodiment, the metallic fill material layer46B can be deposited employing a fluorine-containing precursor gas such as WF6. In one embodiment, the metallic fill material layer46B can be a tungsten layer including a residual level of fluorine atoms as impurities. The metallic fill material layer46B is spaced from the insulating layers32and the memory stack structures55by the metallic barrier layer46A, which is a metallic barrier layer that blocks diffusion of fluorine atoms therethrough.

A plurality of electrically conductive layers46can be formed in the plurality of backside recesses43, and a continuous metallic material layer can be formed on the sidewalls of each backside trench79and over the contact-level dielectric layer80. Each electrically conductive layer46includes a portion of the metallic barrier layer46A and a portion of the metallic fill material layer46B that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers32. The continuous metallic material layer includes a continuous portion of the metallic barrier layer46A and a continuous portion of the metallic fill material layer46B that are located in the backside trenches79or above the contact-level dielectric layer80.

The deposited metallic material of the continuous electrically conductive material layer is etched back from the sidewalls of each backside trench79and from above the contact-level dielectric layer80by performing an isotropic etch process that etches the at least one conductive material of the continuous electrically conductive material layer. Each remaining portion of the deposited metallic material in the backside recesses43constitutes an electrically conductive layer46. Each electrically conductive layer46can be a conductive line structure. Thus, the sacrificial material layers42are replaced with the electrically conductive layers46.

Each electrically conductive layer46can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer46are the control gate electrodes for the vertical memory devices including the memory stack structures55. In other words, each middle electrically conductive layer46can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices. At least one uppermost electrically conductive layer46can be a drain side select gate electrode. At least one bottommost electrically conductive layer46can be a source side select gate electrode.

The electrically conductive layers46are formed directly on the outer cylindrical surface segments of the dielectric metal oxide blocking dielectric layer52of each memory opening fill structure58. As shown in the inset inFIG.9C, in one embodiment, the tubular silicon oxide spacers51′ comprise a respective upper concave annular surface UCAS and a respective lower concave annular surface LCAS, and the electrically conductive layers46are formed on the upper concave annular surface UCAS and the lower concave annular surface LCAS of the tubular silicon oxide spacers51′.

The electrically conductive layers46have a hammer-type shape. At least one of the electrically conductive layer46comprises an upper annular protrusion portion UAPP that protrudes into the divot43D above a first horizontal plane HP1including an interface between an electrically conductive layer46and the overlying silicon oxycarbide liner332, and a lower annular protrusion portion LAPP that protrudes into another divot43D below a second horizontal plane HP2including an interface between the electrically conductive layer46and the underlying silicon oxycarbide liner332.

In one embodiment, the upper annular protrusion portion UAPP contacts a sidewall SW1of an opening in the overlying silicon oxycarbide liner332; the lower annular protrusion portion LAPP contacts a sidewall of an opening in the underlying silicon oxycarbide liner332; and the memory opening fill structure58vertically extends through the opening in the overlying silicon oxycarbide liner332and through the opening in the underlying silicon oxycarbide liner332. In one embodiment, the upper annular protrusion portion UAPP comprises a first inner annular convex surface IACS1and a first outer cylindrical surface OCS1; and the lower annular protrusion portion LAPP comprises a second inner annular convex surface IACS2and a second outer cylindrical surface OCS2.

In one embodiment, the memory film50in each memory opening fill structure58comprises a vertical stack of tubular silicon oxide spacers51′ in contact with a respective one of the insulating layers32. In one embodiment, a plurality of the tubular silicon oxide spacers51′ comprises an upper concave annular surface UCAS that contacts a first electrically conductive layer46and further comprises a lower concave annular surface LCAS that contacts a second electrically conductive layer46.

The memory film50includes a continuous memory material layer (e.g., charge storage layer)54which continuously extends through all of the electrically conductive layers46. Since the insulating layers32are not replaced after formation, the insulating layers32do not embed a seam or an air gap therein.

FIGS.10A-10Eare sequential vertical cross-sectional views of a region around a memory opening fill structure58in a second configuration of the first exemplary structure during formation of electrically conductive layers46according to the first embodiment of the present disclosure.

Referring toFIG.10A, a region around a memory opening fill structure58in the second configuration of the first exemplary structure is illustrated after the processing steps ofFIG.8. The illustrated region ofFIG.10Acan be the same as the illustrated region inFIG.9A.

Referring toFIG.10B, an isotropic etch process that etches the material of the silicon oxide liner51is performed in the same manner as described with reference toFIG.9B. The illustrated region ofFIG.10Bcan be the same as the illustrated region inFIG.9B.

Referring toFIG.10C, a conformal dielectric liner432L is deposited in the annular divots43D around the memory opening fill structures58, on the physically exposed surfaces of the silicon oxycarbide spacers332, and on the physically exposed surfaces of the insulating layers32and the contact-level dielectric layer80. The conformal dielectric liner432L may comprise any insulating material, such as silicon oxide. The thickness of the conformal dielectric liner432L may be greater than one half of the thickness of the tubular silicon oxide spacers51′ so that the conformal dielectric liner432L fills the annular divots43D. For example, the thickness of the conformal dielectric liner432L may range from 2 nm to 4 nm. In one embodiment, the conformal dielectric liner432L comprises undoped silicate glass (e.g., silicon dioxide) or a doped silicate glass.

Referring toFIG.10D, an isotropic recess etch process can be performed to etch back portions of the conformal dielectric liner432L from outside the volumes of the annular divots43D. Horizontally-extending surfaces of the silicon oxycarbide liners332can be physically exposed around each backside recess43. The duration of the isotropic etch process can be selected to minimize collateral etching of the silicon oxycarbide liners332hwhich function as etch stop layers. Each remaining portion of the conformal dielectric liner432L that fills a respective annular divot43D has an annular shape, and is herein referred to as a divot-fill annular dielectric spacer432.

In one embodiment, each memory opening fill structure58comprises divot-fill annular dielectric spacers432. Each tubular silicon oxide spacer51′ is in contact with a respective overlying one of the divot-fill annular dielectric spacers432and is in contact with a respective underlying one of the divot-fill annular dielectric spacers432. In one embodiment, a plurality of the tubular silicon oxide spacers51′ comprise a respective upper concave annular surface and a respective lower concave annular surface.

Referring toFIGS.10E and11, the processing steps described with reference toFIGS.9C and11can be performed to form electrically conductive layers46in the backside recesses. The electrically conductive layers46may also have a hammer shape in this configuration. In the second configuration of the first exemplary structure, the electrically conductive layers46are formed on the concave annular surfaces SCAS of a pair of divot-fill annular dielectric spacers432.

The electrically conductive layers46are formed directly on the outer cylindrical surface segments of the dielectric metal oxide blocking dielectric layer52of each memory opening fill structure58. In one embodiment, the tubular silicon oxide spacers51′ comprise a respective upper concave annular surface UCAS and a respective lower concave annular surface LCAS.

At least one of the electrically conductive layers46comprises an upper annular protrusion portion UAPP that protrudes above a first horizontal plane HP1including an interface between an electrically conductive layer46and the overlying silicon oxycarbide liner332, and a lower annular protrusion portion LAPP that protrudes below a second horizontal plane HP2including an interface between the electrically conductive layer46and the underlying silicon oxycarbide liner332.

In one embodiment, the upper annular protrusion portion UAPP contacts a sidewall SW1of an opening in the overlying silicon oxycarbide liner332; the lower annular protrusion portion LAPP contacts a sidewall of an opening in the underlying silicon oxycarbide liner332; and the memory opening fill structure58vertically extends through the opening in the overlying silicon oxycarbide liner332and through the opening in the underlying silicon oxycarbide liner332. In one embodiment, the upper annular protrusion portion UAPP comprises a first inner annular convex surface IACS1and a first outer cylindrical surface OCS1; and the lower annular protrusion portion LAPP comprises a second inner annular convex surface IACS2and a second outer cylindrical surface OCS2.

In one embodiment, the memory film50in each memory opening fill structure58comprises a vertical stack of tubular silicon oxide spacers51′ in contact with a respective one of the insulating layers32. In one embodiment, a plurality of the tubular silicon oxide spacers51′ comprises an upper concave annular surface UCAS that contacts a first divot-fill annular dielectric spacer432and further comprises a lower concave annular surface LCAS that contacts a divot-fill annular dielectric spacer432.

Referring toFIGS.12A and12B, an insulating material layer can be formed in the backside trenches79and over the contact-level dielectric layer80and an alternating stack of insulating layers32and electrically conductive layers46by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in a range from 1.5 nm to 60 nm, although lesser and greater thicknesses can also be employed.

An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact-level dielectric layer80and at the bottom of each backside trench79. Each remaining portion of the insulating material layer constitutes an insulating spacer74. A backside cavity is present within a volume surrounded by each insulating spacer74.

A top surface of a source region61can be physically exposed at the bottom of each backside trench79. A bottommost electrically conductive layer46provided upon formation of the electrically conductive layers46within the alternating stack (32,46) can comprise a select gate electrode for the field effect transistors. Each source region61is formed in an upper portion of the semiconductor material layer10. Semiconductor channels (59,60) extend between each source region61and a respective set of drain regions63. The semiconductor channels (59,60) include the vertical semiconductor channels60of the memory stack structures55.

A backside contact via structure76can be formed within each backside cavity. Each contact via structure76can fill a respective cavity. The contact via structures76can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity) of the backside trench79. For example, the at least one conductive material can include a conductive liner76A and a conductive fill material portion76B. The conductive liner76A can include a conductive metallic liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The thickness of the conductive liner76A can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion76B can include a metal or a metallic alloy. For example, the conductive fill material portion76B can include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.

The at least one conductive material can be planarized employing the contact-level dielectric layer80overlying the alternating stack (32,46) as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer80can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches79constitutes a backside contact via structure76. Each backside contact via structure76extends through the alternating stacks (32,46), and contacts a top surface of a respective source region61.

Generally, a backside contact via structure76can be formed within each of the backside trenches79after formation of the insulating spacers74by depositing and planarizing at least one conductive material in volumes of the backside trenches79that are not filled with the insulating spacers74.

Alternatively, the above described insulating material layer can be formed in the backside trenches79to completely fill the entire volume of a backside trench79and may consist essentially of at least one dielectric material. In this alternative embodiment, the source region61and the backside trench via structure76may be omitted, and a horizontal source line (e.g., direct strap contact) may contact a side of the lower portion of the semiconductor channel60.

Referring toFIGS.13A and13B, additional contact via structures (88,86,386) can be formed through the contact-level dielectric layer80, and optionally through the retro-stepped dielectric material portion65. For example, drain contact via structures88can be formed through the contact-level dielectric layer80on each drain region63. Layer contact via structures86can be formed on the electrically conductive layers46through the contact-level dielectric layer80, and through the retro-stepped dielectric material portion65. Through-memory-level connection via structures386can be formed through the retro-stepped dielectric material portion65and through the semiconductor material layer10directly on a respective metal pad682. An insulating spacer384may be formed around each through-memory-level connection via structure386to electrically isolate the through-memory-level connection via structures386from the semiconductor material layer10.

FIGS.14A-14Fare sequential schematic vertical cross-sectional views of a memory opening49within a second exemplary structure during formation of a memory opening fill structure58according to a second embodiment of the present disclosure.

Referring toFIG.14A, a region around a memory opening49in a second exemplary structure according to the second embodiment of the present disclosure is illustrated. The second exemplary structure at this processing step may be the same as the first exemplary structure after the processing steps ofFIGS.4A and4B. The sacrificial material layers42comprise silicon nitride.

Referring toFIG.14B, the processing steps described with reference toFIG.5Bcan be optionally performed to form an optional pedestal channel portion11at the bottom of each of the memory openings49and the support openings19. An oxidation process is performed to convert physically exposed surface portions of the sacrificial material layers42around each memory opening49and around each support opening19into tubular silicon oxide portions41. Surface portions of each sacrificial material layer42is oxidized into tubular silicon oxide portions41. The oxidation process may comprise a thermal oxidation process or a plasma oxidation process. In one embodiment, the sacrificial material layers42comprise silicon nitride layers, and the tubular silicon oxide portions41either contain no nitrogen or contain a residual amount of nitrogen atoms (e.g., portions41may comprise silicon oxynitride). If the silicon oxide portions41contain a residual amount of nitrogen atoms, then each of the silicon oxide portions41may have a composition variation in which an atomic concentration of nitrogen atoms increases with a lateral distance from the memory opening49. In other words, atomic concentration of residual nitrogen atoms within the tubular silicon oxide portions41may increase with a lateral distance from the void of a respective memory opening49or from the void of a respective support opening19.

Each of the tubular silicon oxide portions41may have a uniform thickness except at top portions and at bottom portions. The top portions and the bottom portions of the tubular silicon oxide portions41may have a greater thickness near interfaces with a respective one of the silicon oxycarbide liners332because the oxycarbide material of the oxycarbide liners332and the silicon oxide material of the insulation layers32allow diffusion of oxygen atoms during the oxidation process. The thickness of the middle portion of each tubular silicon oxide portion42may be in a range from 1 nm to 12 nm, such as from 3 nm to 8 nm, although lesser and greater thicknesses may also be employed.

If the optional pedestal channel portion11is formed in the memory opening49, then an optional planar semiconductor oxide plate111is formed at the bottom of each of the memory openings49and the support openings19by oxidation of physically exposed surface portions of the pedestal channel portion11. The planar semiconductor oxide plate (e.g., silicon oxide plate)111is located on a top surface of the pedestal channel portion11.

Referring toFIG.14C, the processing steps described with reference toFIG.5Ccan be performed, with the omission of the silicon oxide liner51, to form a memory film50including, from bottom to top above the topmost insulating layer32T and from outside to inside within each memory opening49, a dielectric metal oxide blocking dielectric layer52, a silicon oxide blocking dielectric layer53, a memory material layer54, and a tunneling dielectric layer56.

Referring toFIG.14D, the processing steps described with reference toFIG.5Dcan be performed to remove horizontally-extending portions of the memory film50, and to physically expose a surface of a pedestal channel portion11or a semiconductor material layer10at the bottom of each of the memory openings49and the support openings19.

Referring toFIG.14E, the processing steps described with reference toFIG.5Ecan be performed to form a semiconductor channel layer60L and a dielectric core62within each of the memory openings49and the support openings19.

Referring toFIG.14F, the processing steps described with reference toFIG.5Fcan be performed to form a vertical semiconductor channel60and a drain region63in each of the memory openings49and the support openings19. A memory opening fill structure58is formed in each memory opening49, and a support pillar structure20is formed in each support opening19. Each of the memory opening fill structures58comprises a memory film50that includes, from outside to inside, a dielectric metal oxide blocking dielectric layer52, a silicon oxide blocking dielectric layer53, a memory material layer54, and the tunneling dielectric layer56, and further comprises a vertical semiconductor channel60that is formed on the memory film50.

Subsequently, the processing steps described with reference toFIGS.7A and7Bcan be performed to form a contact-level dielectric layer80, backside trenches79, and source regions61.

The processing steps described with reference toFIGS.8and9Acan be performed to remove the sacrificial material layers42and to form the backside recesses43.

FIGS.15A-15Care sequential vertical cross-sectional views of a region around a memory opening fill structure58in the second exemplary structure during formation of electrically conductive layers46according to the second embodiment of the present disclosure.

Referring toFIG.15A, a region around a memory opening fill structure58in the first configuration of the first exemplary structure is illustrated after formation of the backside recesses43. The isotropic etch process that etches the sacrificial material layers42may be selective to the materials of the insulating layers32, the silicon oxycarbide liners332, and the tubular silicon oxide portions41. The backside recesses43can be formed by removing the sacrificial material layer42selective to the silicon oxycarbide liners332and the tubular silicon oxide portions41.

Referring toFIG.15B, an isotropic etch process that etches the material of the tubular silicon oxide portions41is performed. The tubular silicon oxide portions41can be etched selective to the dielectric metal oxide blocking dielectric layer52. The etch chemistry of the isotropic etch process is selected such that the isotropic etch process etches the material of the tubular silicon oxide portions41(i.e., a silicon oxide material) at a higher etch rate than the material of the silicon oxycarbide liners332.

In an illustrative example, the tubular silicon oxide portions41may comprise silicon oxide, and the isotropic etch process may comprise dilute hydrofluoric acid or buffered hydrofluoric acid. The etch rate of the silicon oxycarbide liners322may be significantly less than the etch rate of the silicon oxide material of the tubular silicon oxide portions41. In one embodiment, the etch rate of the silicon oxycarbide liners322is less than 50% of the etch rate of the silicon oxide material of the tubular silicon oxide portions41. In one embodiment, the etch rate of the silicon oxycarbide liners322is less than 20% of the etch rate of the silicon oxide material of the tubular silicon oxide portions41.

The entirety of the tubular silicon oxide portions41can be removed without entirely removing the silicon oxycarbide liners332. Cylindrical segments of the outer sidewall of a dielectric metal oxide blocking dielectric layer52can be physically exposed to the backside recesses43around each memory opening fill structure58. Each of the first silicon oxycarbide liners332and the second silicon oxycarbide liners332may be thinned. In one embodiment, the thickness of each of the first silicon oxycarbide liners332and the second silicon oxycarbide liners332prior to the isotropic etch process may be in a range from 0.5 nm to 4 nm, and/or from 1.0 nm to 2.5 nm, and the thickness of each of the first silicon oxycarbide liners332and the second silicon oxycarbide liners332after the isotropic etch process may be in a range from 0.25 nm to 2 nm, and/or from 0.5 nm to 1.2 nm. Generally, the thickness decrease of each of the first silicon oxycarbide liners332and the second silicon oxycarbide liners332may be in a range from 25% to 75% of the initial thickness of a respective silicon oxycarbide liner332.

Referring toFIG.15C, the processing steps described with respective toFIG.9Ccan be performed to form electrically conductive layers46in the backside recesses43. In the second exemplary structure, the electrically conductive layers46can be formed directly on horizontally-extending surfaces of the silicon oxycarbide liners332. In one embodiment, the electrically conductive layers46are formed directly on cylindrical outer surface segments of the dielectric metal oxide blocking dielectric layer52. In one embodiment, each of the electrically conductive layers46has a respective uniform vertical thickness throughout. Each cylindrical surface of an electrically conductive layer46contacting a respective dielectric metal oxide blocking dielectric layer52may have an upper periphery that is adjoined to a horizontally-extending top surface of the electrically conductive layer46and a bottom periphery that is adjoined to a horizontally-extending bottom surface of the electrically conductive layer46.

Subsequently, the processing steps described with reference toFIGS.12A and12B, and the processing steps described with reference toFIGS.13A and13Bcan be performed.

Referring to all drawings and according to various embodiments of the present disclosure, a memory device comprises: an alternating stack (32,46) of insulating layers32and electrically conductive layers46, wherein a first electrically conductive layer46of the electrically conductive layers46is in contact with an underlying silicon oxycarbide liner332and with an overlying silicon oxycarbide liner332; a memory opening49vertically extending through the alternating stack (32,46); and a memory opening fill structure58located in the memory opening49and comprising a vertical semiconductor channel60and a memory film comprising a continuous memory material layer54which continuously extends through the entire alternating stack.

In one embodiment, the memory film50comprises, from outside to inside, a dielectric metal oxide blocking dielectric layer52, a silicon oxide blocking dielectric layer53, the continuous memory material layer54and a tunneling dielectric layer56.

In one embodiment, the first electrically conductive layer46comprises: an upper annular protrusion portion UAPP that protrudes above a first horizontal plane HP1including an interface between the first electrically conductive layer46and the overlying silicon oxycarbide liner332; and a lower annular protrusion portion LAPP that protrudes below a second horizontal plane HP2including an interface between the first electrically conductive layer46and the underlying silicon oxycarbide liner332. In one embodiment, the upper annular protrusion portion UAPP contacts a sidewall SW1of an opening in the overlying silicon oxycarbide liner332; the lower annular protrusion portion LAPP contacts a sidewall of an opening in the underlying silicon oxycarbide liner332; and the memory opening fill structure58vertically extends through the opening in the overlying silicon oxycarbide liner332and through the opening in the underlying silicon oxycarbide liner332. In one embodiment, the upper annular protrusion portion UAPP comprises a first inner annular convex surface IACS1and a first outer cylindrical surface OCS1; and the lower annular protrusion portion LAPP comprises a second inner annular convex surface IACS2and a second outer cylindrical surface OCS2.

In one embodiment, the memory film50comprises a vertical stack of tubular silicon oxide spacers51′ in contact with a respective one of the insulating layers32. In one embodiment, one the tubular silicon oxide spacers51′ comprises an upper concave annular surface UCAS that contacts the first electrically conductive layer46and further comprises a lower concave annular surface LCAS that contacts a second electrically conductive layer46among the electrically conductive layers46. In one embodiment, the memory opening fill structure58comprises divot-fill annular dielectric spacers432; and each tubular silicon oxide spacer51′ is in contact with a respective overlying one of the divot-fill annular dielectric spacers432and is in contact with a respective underlying one of the divot-fill annular dielectric spacers432.

In one embodiment, the overlying silicon oxycarbide liner332is in contact with a bottom surface of an overlying insulating layer32of the insulating layers32; and the underlying silicon oxycarbide liner332is in contact with a top surface of an underlying insulating layer32of the insulating layers32.

In one embodiment, the insulating layers32do not embed a seam or an airgap therein. In one embodiment, each of the electrically conductive layers46has a respective uniform vertical thickness throughout.

The various embodiments of the present disclosure provide electrically conductive layers46having less or no corner rounding around memory opening fill structures58. The electrically conductive layers46may comprise a respective pair of annular protrusions or orthogonal angular corners at an interface with a dielectric metal oxide blocking dielectric layers52. The decreased or eliminated corner rounding reduces short channel effects and improves the control gate electrode controllability and control gate electrode length adjacent to the memory film50.