Apparatuses and methods to accelerate vector multiplication of vector elements having matching indices

Methods and apparatuses relating to accelerating vector multiplication. In one embodiment, an apparatus includes a first buffer to store a first cache line of indices for elements of a first vector, a second buffer to store a second cache line of indices for elements of a second vector, a comparison unit to compare each index of the first cache line of indices with each index of the second cache line of indices, a plurality of multipliers to each multiply an element from the first vector and an element from the second vector for an index match from the comparison unit to produce a product, and an adder to add together the product from each of the plurality of multipliers.

TECHNICAL FIELD

The disclosure relates generally to electronics, and, more specifically, an embodiment of the disclosure relates to accelerating vector multiplication.

BACKGROUND

A processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). Instructions (e.g., code) to be executed may be separated into multiple threads for execution by various processor resources. Multiple threads may be executed in parallel. Further, a processor may utilize out-of-order execution to execute instructions, e.g., as the input(s) for such instructions are made available. Thus, an instruction that appears later in program order (e.g., in code sequence) may be executed before an instruction appearing earlier in program order.

DETAILED DESCRIPTION

A (e.g., hardware) processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). The instruction set is the part of the computer architecture related to programming, and generally includes the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term instruction herein may refer to a macro-instruction, e.g., an instruction that is provided to the processor for execution, or to a micro-instruction, e.g., an instruction that results from a processor's decode unit (decoder) decoding macro-instructions. A processor (e.g., having one or more cores to decode and/or execute instructions) may operate on data, for example, in performing arithmetic, logic, or other functions.

Certain functions may include operations on vectors (e.g., a tuple, array, or other ordered list of data elements (entries) with a corresponding index to identify each element), for example, vectors operating on other vectors, vectors operating on matrices, matrices operating on matrices, etc. An element of a vector may generally refer to a discrete section of data that represents a single value and is identified by its own index value. A vector may be a column vector or a row vector. Elements of a vector may be numbers (e.g., integer, floating-point, etc.). A matrix may generally refer to a two-dimensional (2D) vector, e.g., to represent data in two or more dimensions. A matrix may be formed from multiple (e.g., one-dimensional (1D)) vectors. The number of rows (e.g., represented by the variable m) and columns (e.g., represented by the variable n) of a vector may be referred to as the size, order, or dimension. A one-dimensional vector may include a single value (e.g., number) as an index for each element of the vector. A two-dimensional vector may include two values (e.g., numbers) as an index for each element of the vector. Certain operations on a plurality of vectors may multiply each element from one vector with a corresponding element of another vector to produce a product for each pair of elements. The product (e.g., as an addend) for each pair of elements may be added together to form the sum.

One the operations (e.g., kernel function) that may (e.g., frequently) be used is the squared distance computation pattern (L2-norm between two vectors). The squared distance function f (e.g., ∥f∥) between two vectors α and β is given as:
∥α−β∥2=α2+β2−2α·β  (1)
where · is the dot (e.g., inner or scalar) product between the two vectors. The dot product of two vectors α and β is given as:
α·β=Σ(α(i)*β(i)) with 0≤i≤min(length(α),length(β))  (2)
In one embodiment, a vector (or matrix) may be sparse (e.g., where >50% of the elements are zero or null). A sparse vector may be represented (e.g., in memory) in a compressed sparse row (CSR) format where individual vector elements are represented as <index:element> pairs, e.g., with the index denoting the column identification and the element being the data value. Although a colon (:) is illustrated as dividing the element and its index, other alternatives may be utilized to indicate which portion is the element and which is the index.

In certain embodiments (e.g., in a kernelized implementation of a machine learning kernel), this dot product of two vectors (e.g., represented in CSR format) may dominate the computational time of an entire application. In one embodiment without an accelerator circuit (e.g., the circuit as disclosed herein), more than 90% of computation time for a machine learning kernel (e.g., kernel function) is spent in the dot product loop. In one embodiment, a vector multiplication operation may include tens of thousands to millions of vectors and each vector may have tens of thousands to millions of elements.

Certain embodiments herein disclose a hardware accelerator circuit to accelerate vector multiplication. One embodiment includes a hardware accelerator circuit to accelerate a vector dot product (e.g., sparse-vector·sparse-vector) computation kernel. In one embodiment without the use of a hardware accelerator circuit according to this disclosure (e.g., by using a processor core's arithmetic logic unit (ALU) or floating point unit (FPU) without an accelerator circuit according to this disclosure), a vector dot product computation kernel may be dominated by mispredicted branches that lead to an average of four cycles per index computation and the use of a hardware accelerator circuit according to this disclosure may reduce that time to one cycle. Hardware accelerator circuit may be an application-specific integrated circuit (ASIC).

A hardware accelerator circuit may be part of a processor, e.g., part of a core or separate from the core. In one embodiment, an accelerator circuit(s) is (e.g., part of) an execution (e.g., functional) unit of a processor core (e.g., processor core690inFIG. 6B). A processor with a hardware accelerator circuit may include an instruction (e.g., with a particular opcode) in its instruction set to cause data to be sent to the hardware accelerator circuit. In one embodiment, a processor may decode that instruction once for a vector (e.g., a vector pair), and the hardware circuit may complete its operations on that vector (e.g., vector pair) without decoding the instruction again. In one embodiment, a hardware accelerator circuit includes a finite state machine (FSM) to control its operations, e.g., as discussed herein.

FIG. 1illustrates an accelerator circuit100to accelerate vector multiplication according to embodiments of the disclosure. Circuit100may be utilized to accelerate a (e.g., sparse) vector·(e.g., sparse) vector calculation. A first vector and a second vector may be stored in memory102. Memory102may be cache memory and/or system memory (e.g., separate from a cache memory). The first vector and second vector may each have the same number of elements therein and thus the same number of indices. Each element may be the same maximum size (e.g., number of bits). Each element for the same index (e.g., index2in each vector) may have the same maximum size (e.g., number of bits). Note that although certain components may be referred to in the singular, for example, a streamer104, there may be two or more such components utilized.

Streamer104(e.g., separate streamers104A,104B) may stream (e.g., portions of) a first vector (e.g., beginning at the address py as an example) and/or (e.g., portions of) a second vector (e.g., beginning at the address px as an example). Streamer may have direct memory access (DMA). Streamer may receive a command to stream a certain vector(s) from a control unit (not shown). Control unit may be a finite state machine (FSM). Control unit may be part of comparison unit108. Streamer104may stream (e.g., load in from memory and provide as an output) individual vector elements in the CSR format (represented as index:element pairs). Streamers104A,104B may simultaneously operate. Streamer may not stream any elements with a zero value. The circuit may track the number of zero valued elements and/or non-zero valued elements, for example, to use in determining if the streamer or other components of the circuit have completed their task(s). Streamer104(e.g., separate streamers104A,104B) may not output the vector elements in index order (e.g., sorted). One example of this is discussed further below.

Streamer104may output each vector's elements in the CSR format (represented as index:element pairs) to a buffer106. Buffer (e.g., data buffer) may generally refer to a storage device to temporarily store data. First streamer104A may output an element of the first vector (e.g., in the CSR format as an index:element pair) to a first buffer106A. Second streamer104B may output an element of the second vector (e.g., in the CSR format as an index:element pair) to a second buffer106B. A streamer may output one element (e.g., one index:element pair) at a time. Note that although four discrete storage elements are shown in a line of buffers106A,106B, any single or plurality of discrete storage elements may be utilized. In one embodiment, a streamer104streams (e.g., provides) the elements (e.g., index:element pairs) to a buffer as they are available, e.g., which may be Out-of-(program) Order (OoO). In one embodiment, a streamer104may stream one cache line worth of data (e.g., of index:element pairs) at a time (e.g., in one processor clock cycle) into a buffer106. In one embodiment, a streamer104(e.g., each streamer104A,104B) streams (e.g., provides) one element (e.g., one index:element pair) to a line of a buffer (e.g., each buffer106A,106B), for example, then moving to another line of the buffer once the previous line includes one cache line worth of data (e.g., of index:element pairs). As used herein, a cache line may generally refer to a block (e.g., a sector) of data that may be managed (e.g., by communication resources) as a unit for coherence purposes. A cache line may include multiple, discrete sections. In one embodiment, each section holds a single index:element pair. A width105of cache line may have a number of equally sized sections of a single width103. For example, a 512 bit wide cache line may have 4 sections of 128 bits of storage for each section, 8 sections with 64 bits of storage for each section, etc.

Buffer106may then provide pieces of data (e.g., sized less than an entire vector of index:element pairs) to the comparison unit108. For example, first buffer106A may provide a cache line of indices (e.g., including in that cache line each index's element as well, e.g., in the CSR format) to first vector data input108A (e.g., register) of comparison unit108. For example, second buffer106B may provide a cache line of indices (e.g., including in that cache line each index's element as well, e.g., in the CSR format) to second vector data input108B (e.g., register) of comparison unit108. First buffer106A and second buffer106B may provide their data (e.g., each with a plurality of index:element pairs) to the comparison unit108simultaneously or within the same clock cycle. Size of inputs (e.g., registers) of comparison circuit may be a cache line (e.g., the same size as the amount of data provided by a buffer). Size of output of comparator may be the size of an element of a vector. Comparison unit108may be a comparator. Comparison unit108may include further circuitry, e.g., to control data flow.

Comparison unit108may compare each index (e.g. from an index:element pair) of the first vector data input108A to each index (e.g. from an index:element pair) of the second vector data input108B. In such an embodiment, any matching indices (e.g., such that they include the same value) indicate to the circuit100that the corresponding elements of those indices may be forwarded on, e.g., to the multiplier-accumulator (MAC) units110. Any non-matching indices for that subset of indices of the first and second vectors that are being compared (e.g., when the comparison unit108has not found a match for that index (e.g. from an index:element pair) of the first vector data input108A with any index (e.g. from an index:element pair) of the second vector data input108B) may then be sent back to be checked again in the future. For example, comparison unit108may send back those non-matching index (indices) to their respective buffers or streamers. For example, comparison unit108may leave the non-matched index (indices) of one vector data input (108A or108B) and then load the empty parts of the inputs (108A,108B) with data from the buffer106.

In performing a comparison of two indices (one from each of the vectors), comparison unit108may subtract an index from the first vector from an index in a second vector, e.g., such that a zero (e.g., null) value indicates that index from the first vector matches that particular index from the second vector and a non-zero value indicates a non-matching index for those indices. For any circuit in this disclosure, please note that the control logic (e.g., providing control signals) may not be depicted so as to avoid obscuring the figures.

Circuit100(e.g., comparison unit108) may also purge (e.g., from the buffer or data inputs (108A,108B) from the buffer any element (e.g., and its index) that has a zero value as well as it may purge (e.g., from the buffer or data inputs (108A,108B)) the corresponding index from the other vector as the zero will also make zero the product with any value contained in the other vector during the multiplication step herein.

Circuit100(e.g., comparison unit108) may, e.g., upon completion of a comparison of the subset of indices in vector data inputs (108A,108B), request another input (e.g., a cache line of data) from a buffer and may request a streamer stream (e.g., load) more data (e.g., vector index:element pair(s)) from memory202(e.g., “stream more lines” shown schematically inFIG. 1). Circuit100(e.g., comparison unit108) may, e.g., upon completion of a comparison of the subset of indices in vector data inputs (108A,108B), request a buffer free up an entry (e.g., an entry for a matched index), for example, of a cache line thereof (e.g., “free entry identification (ID)) shown schematically inFIG. 1). The circuit may repeatedly iterate this process until complete, e.g., each non-zero element of the first vector has been multiplied with the corresponding non-zero element of the second vector.

Accelerator circuit100may include a multiplier accumulator (MAC) unit section110with a plurality of multiplier accumulator units (MACs). The variable “X” in multiplier accumulator unit110(X) is to indicate that any number of MACs may be used. In one embodiment, circuit100includes one MAC for each section of a vector data input (108A,108B) of the comparison unit108, e.g., one MAC for each possible match in a single comparison operation. For example, MACs110(1) through110(X) may operate in parallel on any matching indices (e.g., for simultaneous operation or to all operate within one clock cycle). Comparison unit108may then provide the elements from the index match (e.g., matching indices) of the first vector and the second vector to a respective input112A,112B of a multiplier112(multiplier unit) to perform a multiplication thereof to produce a product, and similarly for the other MACs, for example, from zero MACs to all the MACs may perform a calculation during each iteration of the circuit100, e.g., depending on how many indices matched during the comparison for those indices. The accumulator (e.g., accumulator register)116(e.g., for the storage of intermediate results) of the MAC110(1) may be set (e.g., reset) to zero, for example, for the first iteration (e.g., of a comparison) for a set of first and second vectors. Thus the accumulator116will then hold the first product and then each further product may be added to it (as an addend), e.g., as in the dot product equation (2). A multiply-accumulate process for all MACs110(1)-110(X) may occur in one processor clock cycle. When the first vector and second vector have had all of their index matched, non-zero elements multiplied together, circuit100may then send all of the individual MAC results to adder118(e.g., an adder having the same number of inputs as the total number of MACs (X)) to form a sum. Sum may be stored in memory (e.g., register120). Writing of the sum to register120may indicate to the circuit that the operation is complete. Circuit may (e.g., in response to the writing to or data storage in register120), notify (e.g., send a signal to) a processor core (e.g., that requested this operation on the first vector and second vector) that the accelerator is done with its work (e.g., the sum is ready).

Adder118may be controlled by circuit100(e.g., control logic) determining there are no further inputs into the comparison unit108or otherwise. A streamer may determine when a vector has been completely loaded by reaching a special value in the vector, e.g., “−1” in one embodiment with an unknown vector size). Other registers may be used in a circuit, e.g. in addition to those depicted.

In one embodiment, dotted line122indicates an optional output from the register120(or adder118) may be added back as an input to the adder118. For example, in a matrix calculation, multiple (e.g., sparse) vector·(e.g., sparse) vector calculations may be iteratively added together.

The following is one non-limiting example in a compressed sparse row (CSR) format where individual vector elements are represented as index:element pairs, e.g., where the index denotes the column number and a vector represents a row. First vector and second vector streamed from memory102in this example have 8 elements and their 8 respective indices.

The accumulator116is set to zero.

2. Do 4×4 index comparison (compare 2, 4, 7, 9 indices of V1 with each of 1, 2, 4 and 7 indices of V2) to find which indices match with comparison unit108(e.g., crossbar). In this case, there is an index match for indices 2, 4 and 7 from V1 and 2, 4 and 7 from V2. Forward the elements (values) corresponding to these indices to the multiplier accumulate units110(e.g., here using three of the MACs as there are three matches).
3. Do multiply with MACs110(0.01*0.02; 0.02*0.03; 0.03*0.04=Result (RES1, RES2, RES2) on each of three respective MACs).
4. Add 0 from accumulator registers (e.g.,116for MAC110(1) and RES1; 0+RES2, and 0+RES3) with adder (e.g.,114for MAC110(1) and store the result back into the accumulator register (e.g.,116for MAC110(1). Accumulator register for MAC110(1) now stores RES1; accumulator register for MAC110(2) now stores RES2; and accumulator register for MAC110(3) now stores RES3.
Optionally: in one embodiment, compare non-matching last index of V1 with last index of V2 (in this case 9 with 7) to find out which one is less. Fetch 4 more index:element pairs of the vector for which the last index is lower. In this case, 7<9, so we fetch 4 more indices of V2 and repeat the steps in an iteration. In one embodiment a comparison unit may compare the last indices of V1 and V2 that are being compared in that iteration and (i) if they do not match, a cache line of index:vector pairs may be fetched from one of the vectors (e.g., buffers) and (ii) if they do match, then a cache line of index:vector pairs may be fetched from each of the vectors (e.g., buffers).
Iteration 2:
1. Fetch [2:0.01 4:0.02 7:0.03 9:0.04] of V1 and [10:0.05 14:0.06 15:0.07 17:0.08] of V2 from the buffers (106A,106B).
2. Do 4×4 index comparison (compare 2, 4, 7, 9 indices of V1 with each of 10, 14, 15 and 17 indices of V2) to find which indices match with comparison unit108.
In this case, nothing matches.
3. Skip multiply and add with MACs.
4. Skip add with accumulator register.
Optionally: in one embodiment, compare last index of V1 with last index of V2 (in this case 9 with 17). 9<17, so fetch 4 more index:element pairs of V1 and repeat the steps.
Iteration 3:
1. Fetch [11:0.05 13:0.06 15:0.07 16:0.08] of V1 and [10:0.05 14:0.06 15:0.07 17:0.08] of V2 from the buffers (106A,106B).
2. Do 4×4 index comparison (compare 11, 13, 15, 16 indices of V1 with each of 10, 14, 15 and 17 indices of V2) to find which indices match. In this case, only indices 15 match (3rdsection of V1 and 3rdsection of V2).
3. Do multiply 0.07*0.07=RES4 (with any MAC, e.g., selected by control logic).
4. Add value in accumulator register116(RES1) and RES4 with adder114and store it back into accumulator register116. At this point, the accelerator circuit has used up all elements in each of the vectors V1 and V2, so the circuit100may instruct adder118to sum all of the values from each accumulator register of a MAC, and the circuit may send the final register120value to the invoking agent (core) and may send a signal that it is available to do additional work now.

An execution unit of this disclosure may also include a circuit to square a vector, e.g., with the result to be used in the vector squared portions of the L2 norm calculation, along with the accelerator circuits discussed herein.

Note that a single headed arrow herein may not be limited to one-way communication, for example, it may indicate two-way communication (e.g., both to and from that component). Any or all combinations of communications paths may be utilized in embodiments herein.

Accelerator circuit200may include a multiplier unit section210with a plurality of multipliers. The variable “X” in multiplier210(X) is to indicate that any number of multipliers may be used. In one embodiment, circuit100includes one multiplier for each section of a vector data input (208A,208B) of the comparison unit208, e.g., one multiplier for each possible match in a single comparison operation. For example, multiplier210(1) through210(X) may operate in parallel on any matching indices (e.g., for simultaneous operation or to all operate within one clock cycle). Comparison unit208may then provide the elements from the index match (e.g., matching indices) of the first vector and the second vector to a respective input212A,212B of a multiplier212(multiplier unit) to perform a multiplication thereof to produce a product, and similarly for the other multipliers, for example, from zero multipliers to all the multiplies may perform a calculation during each iteration of the circuit200, e.g., depending on how many indices matched during the comparison for those indices. The results of the multiplications vectors may be added together by adder218(as addends), e.g., as in the dot product equation (2), and stored in register220. For example, circuit200may send all of the individual multiplier results to adder218(e.g., an adder having the same number of inputs as the total number of multipliers (X)) to form a sum. A multiply with the multipliers210(1)-210(X) and an addition with the adder218may occur in one processor clock cycle. Dotted line122indicates an optional output from the register220(or adder218) may be added back as an input to the adder218. For example, to iterate but without including an adder and accumulator for each of the plurality of multipliers210. When the first vector and second vector have had all of their index matched, non-zero elements multiplied together, circuit200may then send the result (e.g., from register220) to a processor core (e.g., that requested this operation on the first vector and second vector) to notify (e.g., indicate) the accelerator is done with its work (e.g., the sum is ready).

FIG. 3illustrates an accelerator system300(e.g., complex) to accelerate vector multiplication according to embodiments of the disclosure. The term schema may generally refer to an information packet, e.g., which may invoke an accelerator complex and/or accelerator circuits. In one embodiment, an accelerator complex300includes one of more accelerator circuits302, e.g., as disclosed herein. For example, accelerator circuit302may be accelerator circuit100or accelerator circuit200. An accelerator complex may include hardware, software, firmware, or any combination thereof.

In certain embodiments, on receipt by the accelerator complex300of the schema (e.g., prepared by the compiler and embedded in the application binary), the accelerator controller (e.g., control logic) and scheduler304in the accelerator complex prepare a set of virtual accelerator threads (VATs) to be scheduled on the hardware accelerator circuit(s) (e.g., accelerator threads (ATs). These tasks may be queued into an accelerator work queue from which each of the hardware accelerators may pull work and notify completion with a done flag. This is schematically shown inFIG. 3.

FIG. 4illustrates an accelerator system400(e.g., complex) to accelerate vector multiplication according to embodiments of the disclosure. In one embodiment, accelerator circuits (e.g.,402) in the accelerator complex400may be utilized in parallel (e.g., chained together), e.g., instead of all the accelerators being of a single type, there may be multiple types (e.g., multiple of type1, multiple of type2, etc.). The scheduler404in this case may schedule tasks such that after a task is done on an accelerator of type1, that task is then scheduled on an accelerator of type2, and so on until the higher (e.g., highest) level task is done. One embodiment of this is an accelerator complex comprised of type1 accelerator circuit(s) to compute the squares (e.g., each of α2and β2) and type2 accelerator circuit(s) that compute the dot product (α·β). The scheduler404may then chain the output from both of these accelerator circuits to an execution (e.g., functional) unit that computes the final L2-norm in equation (1).

FIG. 5illustrates a flow diagram500of accelerating vector multiplication according to embodiments of the disclosure. Flow diagram500includes retrieving a first cache line of indices for elements of a first vector stored in a first buffer502, retrieving a second cache line of indices for elements of a second vector stored in a second buffer504, comparing each index of the first cache line of indices with each index of the second cache line of indices with a comparison unit506, multiplying an element from the first vector and an element from the second vector for each of a plurality of multipliers for an index match from the comparison unit to produce a product508, and adding together the product from each of the plurality of multipliers with an adder510.

An accelerator complex of a processor may be adjacent (e.g., close) to a core or in the uncore (e.g., in the cache, such as, but not limited to, level two or last level cache). If an accelerator complex is in the cache (e.g., L2, L3, or LLC) there may be less of a data movement cost, e.g., vector data may not be sent all the way up to L1 cache and/or register files in the core. In one embodiment of the dot (inner) product accelerator circuit, the accelerator circuit may not read its own output. The writes by the accelerator complex may be done using (e.g., user-specified) uncacheable speculative write combining (USWC) stores, e.g., streaming stores bypassing cache (e.g., L1, L2, L3, and/or LLC cache). When an accelerator complex is done with its assigned work, it may notify the core using a MWait instruction. A processor (e.g., core) may assign work to an accelerator complex using an (e.g., enqueue) instruction.

Certain embodiments of this disclosure may provide performance and/or efficient power usage improvement. For example, an accelerator circuit separate from a processor core may allow the core to be disengaged, (e.g., while the accelerator circuit is performing its operation), for example, allowing the (e.g., requesting) core to power down (e.g., idle) or do some other thread's (or application's) work. Data reuse of a vector may improve across multiple accelerator circuit invocations (e.g., can pin data for that vector in a cache). In one embodiment, the architecture of the accelerator circuit or accelerator complex is transparent to the programmer (e.g., it is virtualized) to allowing the hardware to accelerator vector multiplication operations without affecting the programmer. In one embodiment, if the accelerator circuit or accelerator complex is busy handling application A's work and application B invokes the accelerator circuit or accelerator complex, application B may get a busy status message, for example, it is then up to application B how to proceed, e.g., it may execute the threads on the core or wait for the accelerator circuit or accelerator complex to be available to do application B's work.

In one embodiment, an apparatus includes a first buffer to store a first cache line of indices for elements of a first vector, a second buffer to store a second cache line of indices for elements of a second vector, a comparison unit to compare each index of the first cache line of indices with each index of the second cache line of indices, and a plurality of multipliers to each multiply an element from the first vector and an element from the second vector for an index match from the comparison unit to produce a product. The apparatus may include an adder to add together the product from each of the plurality of multipliers. The apparatus may include a first streamer to provide an index and its element from a data storage device to the first buffer and a second streamer to provide an index and its element from the data storage device to the second buffer. The indices of the first cache line and the second cache line may not be in index order. The comparison unit may compare each index of the first cache line of indices with each index of the second cache line of indices in a single clock cycle of a processor. The cache line of indices for elements of the first vector and/or the second vector may also include each index's element. The plurality of multipliers may be a plurality of multiplier-accumulator units. The apparatus may include logic to notify a requesting processor core that operations on all elements of the first vector and the second vector are completed. The comparison unit may return each index of the first cache line to the first buffer and each index of the second cache line to the second buffer for non-matching indices.

In another embodiment, a method includes retrieving a first cache line of indices for elements of a first vector stored in a first buffer, retrieving a second cache line of indices for elements of a second vector stored in a second buffer, comparing each index of the first cache line of indices with each index of the second cache line of indices with a comparison unit, and multiplying an element from the first vector and an element from the second vector for each of a plurality of multipliers for an index match from the comparison unit to produce a product. The method may include adding together the product from each of the plurality of multipliers with an adder. The method may include providing an index and its element from a data storage device to the first buffer with a first streamer, and providing an index and its element from the data storage device to the second buffer with a second streamer. The method may include providing indices of the first cache line and the second cache line are not in index order. The comparing may be in a single clock cycle of a processor. The first cache line of indices for elements of the first vector may also include each index's element. The plurality of multipliers may be a plurality of multiplier-accumulator units. The method may include notifying a requesting processor core that operations on all elements of the first vector and the second vector are completed. The method may include returning each index of the first cache line to the first buffer and each index of the second cache line to the second buffer for non-matching indices.

In yet another embodiment, a system includes a data storage device to store a first vector and a second vector, a first buffer to store a first cache line of indices for elements of the first vector from the data storage device, a second buffer to store a second cache line of indices for elements of the second vector from the data storage device, a comparison unit to compare each index of the first cache line of indices with each index of the second cache line of indices, and a plurality of multipliers to each multiply an element from the first vector and an element from the second vector for an index match from the comparison unit to produce a product. The system may include an adder to add together the product from each of the plurality of multipliers. The system may include a first streamer to provide an index and its element from the data storage device to the first buffer and a second streamer to provide an index and its element from the data storage device to the second buffer. The indices of the first cache line and the second cache line may not be in index order. The comparison unit may compare each index of the first cache line of indices with each index of the second cache line of indices in a single clock cycle of a processor. The first cache line of indices for elements of the first vector may also include each index's element. The plurality of multipliers may be a plurality of multiplier-accumulator units. The system may further include logic to notify a requesting processor core that operations on all elements of the first vector and the second vector are completed. The comparison unit may return each index of the first cache line to the first buffer and each index of the second cache line to the second buffer for non-matching indices.

In another embodiment, an apparatus includes means for retrieving a first cache line of indices for elements of a first vector stored in a first buffer, means for retrieving a second cache line of indices for elements of a second vector stored in a second buffer, means for comparing each index of the first cache line of indices with each index of the second cache line of indices with a comparison unit, and means for multiplying an element from the first vector and an element from the second vector for each of a plurality of multipliers for an index match from the comparison unit to produce a product. The apparatus may include means for adding together the product from each of the plurality of multipliers with an adder. An apparatus to accelerate vector multiplication may be as described in the detailed description. A method for accelerating vector multiplication may be as described in the detailed description.

Exemplary Core Architectures

In-Order and Out-of-Order Core Block Diagram

InFIG. 6A, a processor pipeline600includes a fetch stage602, a length decode stage604, a decode stage606, an allocation stage608, a renaming stage610, a scheduling (also known as a dispatch or issue) stage612, a register read/memory read stage614, an execute stage616, a write back/memory write stage618, an exception handling stage622, and a commit stage624.

FIG. 6Bshows processor core690including a front end unit630coupled to an execution engine unit650, and both are coupled to a memory unit670. The core690may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core690may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit630includes a branch prediction unit632coupled to an instruction cache unit634, which is coupled to an instruction translation lookaside buffer (TLB)636, which is coupled to an instruction fetch unit638, which is coupled to a decode unit640. The decode unit640(or decoder or decoder unit) may decode instructions (e.g., macro-instructions), and generate as an output one or more micro-operations, micro-code entry points, micro-instructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit640may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core690includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit640or otherwise within the front end unit630). The decode unit640is coupled to a rename/allocator unit652in the execution engine unit650.

The execution engine unit650includes the rename/allocator unit652coupled to a retirement unit654and a set of one or more scheduler unit(s)656. The scheduler unit(s)656represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)656is coupled to the physical register file unit(s)658. Each of the physical register file unit(s)658represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file unit(s)658comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file unit(s)658is overlapped by the retirement unit654to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit654and the physical register file unit(s)658are coupled to the execution cluster(s)660. The execution cluster(s)660includes a set of one or more execution units662and a set of one or more memory access units664. The execution units662may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)656, physical register file unit(s)658, and execution cluster(s)660are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)664). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units664is coupled to the memory unit670, which includes a data TLB unit672coupled to a data cache unit674coupled to a level 2 (L2) cache unit676. In one exemplary embodiment, the memory access units664may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit672in the memory unit670. The instruction cache unit634is further coupled to a level 2 (L2) cache unit676in the memory unit670. The L2 cache unit676is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline600as follows: 1) the instruction fetch638performs the fetch and length decoding stages602and604; 2) the decode unit640performs the decode stage606; 3) the rename/allocator unit652performs the allocation stage608and renaming stage610; 4) the scheduler unit(s)656performs the schedule stage612; 5) the physical register file unit(s)658and the memory unit670perform the register read/memory read stage614; the execution cluster660perform the execute stage616; 6) the memory unit670and the physical register file unit(s)658perform the write back/memory write stage618; 7) various units may be involved in the exception handling stage622; and 8) the retirement unit654and the physical register file unit(s)658perform the commit stage624.

Specific Exemplary In-Order Core Architecture

FIG. 7Ais a block diagram of a single processor core, along with its connection to the on-die interconnect network702and with its local subset of the Level 2 (L2) cache704, according to embodiments of the disclosure. In one embodiment, an instruction decode unit700supports the x86 instruction set with a packed data instruction set extension. An L1 cache706allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit708and a vector unit710use separate register sets (respectively, scalar registers712and vector registers714) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache706, alternative embodiments of the disclosure may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

FIG. 7Bis an expanded view of part of the processor core inFIG. 7Aaccording to embodiments of the disclosure.FIG. 7Bincludes an L1 data cache706A part of the L1 cache704, as well as more detail regarding the vector unit710and the vector registers714. Specifically, the vector unit710is a 16-wide vector processing unit (VPU) (see the 16-wide ALU728), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit720, numeric conversion with numeric convert units722A-B, and replication with replication unit724on the memory input. Write mask registers726allow predicating resulting vector writes.

FIG. 8is a block diagram of a processor800that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the disclosure. The solid lined boxes inFIG. 8illustrate a processor800with a single core802A, a system agent810, a set of one or more bus controller units816, while the optional addition of the dashed lined boxes illustrates an alternative processor800with multiple cores802A-N, a set of one or more integrated memory controller unit(s)814in the system agent unit810, and special purpose logic808.

The memory hierarchy includes one or more levels of cache (e.g., cache unit(s)804A-N) within the cores, a set or one or more shared cache units806, and external memory (not shown) coupled to the set of integrated memory controller units814. The set of shared cache units806may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit812interconnects the integrated graphics logic808, the set of shared cache units806, and the system agent unit810/integrated memory controller unit(s)814, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units806and cores802-A-N.

In some embodiments, one or more of the cores802A-N are capable of multithreading. The system agent810includes those components coordinating and operating cores802A-N. The system agent unit810may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores802A-N and the integrated graphics logic808. The display unit is for driving one or more externally connected displays.

Exemplary Computer Architectures

Referring now toFIG. 9, shown is a block diagram of a system900in accordance with one embodiment of the present disclosure. The system900may include one or more processors910,915, which are coupled to a controller hub920. In one embodiment the controller hub920includes a graphics memory controller hub (GMCH)990and an Input/Output Hub (IOH)950(which may be on separate chips); the GMCH990includes memory and graphics controllers to which are coupled memory940and a coprocessor945; the IOH950is couples input/output (I/O) devices960to the GMCH990. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory940and the coprocessor945are coupled directly to the processor910, and the controller hub920in a single chip with the IOH950. Memory940may include an accelerator binary translator module940A, for example, to store code that when executed causes a processor to perform any method of this disclosure.

The optional nature of additional processors915is denoted inFIG. 9with broken lines. Each processor910,915may include one or more of the processing cores described herein and may be some version of the processor800.

The memory940may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub920communicates with the processor(s)910,915via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection995.

In one embodiment, the coprocessor945is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub920may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources910,915in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor910executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor910recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor945. Accordingly, the processor910issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor945. Coprocessor(s)945accept and execute the received coprocessor instructions.

Referring now toFIG. 10, shown is a block diagram of a first more specific exemplary system1000in accordance with an embodiment of the present disclosure. As shown inFIG. 10, multiprocessor system1000is a point-to-point interconnect system, and includes a first processor1070and a second processor1080coupled via a point-to-point interconnect1050. Each of processors1070and1080may be some version of the processor800. In one embodiment of the disclosure, processors1070and1080are respectively processors910and915, while coprocessor1038is coprocessor945. In another embodiment, processors1070and1080are respectively processor910coprocessor945.

Processors1070and1080are shown including integrated memory controller (IMC) units1072and1082, respectively. Processor1070also includes as part of its bus controller units point-to-point (P-P) interfaces1076and1078; similarly, second processor1080includes P-P interfaces1086and1088. Processors1070,1080may exchange information via a point-to-point (P-P) interface1050using P-P interface circuits1078,1088. As shown inFIG. 10, IMCs1072and1082couple the processors to respective memories, namely a memory1032and a memory1034, which may be portions of main memory locally attached to the respective processors.

Processors1070,1080may each exchange information with a chipset1090via individual P-P interfaces1052,1054using point to point interface circuits1076,1094,1086,1098. Chipset1090may optionally exchange information with the coprocessor1038via a high-performance interface1039. In one embodiment, the coprocessor1038is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

As shown inFIG. 10, various I/O devices1014may be coupled to first bus1016, along with a bus bridge1018which couples first bus1016to a second bus1020. In one embodiment, one or more additional processor(s)1015, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus1016. In one embodiment, second bus1020may be a low pin count (LPC) bus. Various devices may be coupled to a second bus1020including, for example, a keyboard and/or mouse1022, communication devices1027and a storage unit1028such as a disk drive or other mass storage device which may include instructions/code and data1030, in one embodiment. Further, an audio I/O1024may be coupled to the second bus1020. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG. 10, a system may implement a multi-drop bus or other such architecture.

Referring now toFIG. 11, shown is a block diagram of a second more specific exemplary system1100in accordance with an embodiment of the present disclosure. Like elements inFIGS. 10 and 11bear like reference numerals, and certain aspects ofFIG. 10have been omitted fromFIG. 11in order to avoid obscuring other aspects ofFIG. 11.

FIG. 11illustrates that the processors1070,1080may include integrated memory and I/O control logic (“CL”)1172and1182, respectively. Thus, the CL1172,1182include integrated memory controller units and include I/O control logic.FIG. 11illustrates that not only are the memories1032,1034coupled to the CL1172,1182, but also that I/O devices1114are also coupled to the control logic1172,1182. Legacy I/O devices1115are coupled to the chipset1090.

Referring now toFIG. 12, shown is a block diagram of a SoC1200in accordance with an embodiment of the present disclosure. Similar elements inFIG. 8bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. InFIG. 12, an interconnect unit(s)1202is coupled to: an application processor1210which includes a set of one or more cores202A-N and shared cache unit(s)806; a system agent unit810; a bus controller unit(s)816; an integrated memory controller unit(s)814; a set or one or more coprocessors1220which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit1230; a direct memory access (DMA) unit1232; and a display unit1240for coupling to one or more external displays. In one embodiment, the coprocessor(s)1220include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.