FIN PROFILE MODULATION

Fins for use in gate all-around field effect transistors (GAAFETs) can be manufactured to have substantially uniform profiles, so the shapes of the fins are independent of size and pitch. Fin profile optimization from a tapered profile to a substantially uniform profile can be achieved via fin height control modulation using additional physical shaping operations to reduce pattern loading. These improvements in the fin profile can be accomplished by stacking and refilling a flowable chemical vapor deposition (FCVD) film multiple times and by using composition tuning during the FCVD process to further modulate fin profiles.

BACKGROUND

With advances in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (FinFETs). Such scaling down has increased the complexity of semiconductor manufacturing processes.

DETAILED DESCRIPTION

The following disclosure provides different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed that are between the first and second features, such that the first and second features are not in direct contact.

The term “nominal” as used herein refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values is typically due to slight variations in manufacturing processes or tolerances.

The term “vertical,” as used herein, means nominally perpendicular to the surface of a substrate.

Vertical structures known as “fins” can be fabricated for use in advanced transistors, such as FinFETs and gate-all-around FETs (GAAFETs) that are built on semiconductor substrates. Fins extend upward from a top surface of the substrate, allowing a transistor gate to wrap around one or more current channels of the transistor in three dimensions, thus providing improved control, reduced current leakage, and a faster switching response. Ideally, the profile of the fin top has a substantially uniform width. However, in reality, fin profiles are often tapered such that the top of the fin is narrower than the base, by as much as about 3 nm to about 5 nm. Tapered fin profiles can reduce flexibility for subsequent patterning of the transistor gate, resulting in reduced device performance. Consequences of tapered fin profiles may be worse for narrower fins than for wider fins. Thus, it is desirable to fabricate fins having a more uniform width, so the shape of the fin is independent of its size and separation distance from adjacent fins (pitch). One way to fabricate a fin having substantially vertical sidewalls is to bury the wider fin base under the surface of the substrate so that the more uniform portion of the fin protrudes from the surface. However, it is also desirable to preserve the height of the fin top while improving uniformity of the fin profile.

FIG.1is an isometric view of a FinFET100, with transparency, in accordance with some embodiments. FinFET100includes a substrate102, isolation regions103incorporated into substrate102, a fin105having source and drain regions104, respectively (each also referred to as “source/drain region104”), a gate structure108, and a channel110.

As used herein, the term “substrate” describes a material onto which subsequent layers of material are added. The substrate itself may be patterned. Materials added on the substrate may be patterned or may remain unpatterned. Substrate102can be made of a semiconductor material, such as silicon (Si). Substrate102can be a bulk semiconductor wafer or the top semiconductor layer of a semiconductor-on-insulator (SOI) wafer (not shown), such as silicon-on-insulator. In some embodiments, substrate102can include a crystalline semiconductor layer with its top surface parallel to a crystal plane, e.g., one of (100), (110), (111), or c-(0001) crystal planes. In some embodiments, substrate102can be made from an electrically non-conductive material, such as glass, sapphire, and plastic. In some embodiments, substrate102can include (i) an elementary semiconductor, such as germanium (Ge); (ii) a compound semiconductor including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); (iii) an alloy semiconductor including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), gallium indium phosphide (InGaP), gallium indium arsenide (InGaAs), gallium indium arsenic phosphide (InGaAsP), aluminum indium arsenide (InAlAs), and/or aluminum gallium arsenide (AlGaAs); or (iv) a combination thereof. Substrate102can be doped with p-type dopants (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or n-type dopants (e.g., phosphorus (P) or arsenic (As)). In some embodiments, different portions of substrate102can have opposite type dopants.

Shallow trench isolation (STI) regions103are formed in substrate102to electrically isolate neighboring FinFETs100from one another. STI regions103can be formed adjacent to fin105For example, an insulating material can be blanket deposited over and between each fin105. The insulating material can be blanket deposited to fill trenches in substrate102(e.g., spaces that will be occupied by STI regions103in subsequent fabrication steps) surrounding fins105. A subsequent polishing process, such as a chemical mechanical polishing (CMP) process, can substantially planarize top surfaces of STI regions103. In some embodiments, the insulating material for STI regions103can include, for example, silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or a low-k dielectric material. In some embodiments, the insulating material for STI regions103can be deposited using a flowable chemical vapor deposition (FCVD) process, a high-density-plasma (HDP) CVD process, or silane (SiH4) and oxygen (O2) as reacting precursors. In some embodiments, the insulating material for STI regions103can be formed using a sub-atmospheric CVD (SACVD) process or high aspect-ratio process (HARP), where process gases can include tetraethoxysilane (TEOS) and/or ozone (O3). In some embodiments, the insulating material for STI regions103can be formed using a spin-on-dielectric (SOD), such as hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ).

A fin105including source/drain regions104is formed from a portion of substrate102, extending outward from an upper surface of substrate102in the z-direction. Source/drain regions104are doped with either a positive or a negative species to provide charge reservoirs for FinFET100. For example, for a negative FET (NFET), source/drain regions104can include the substrate material, such as Si, and n-type dopants. For a positive FET (PFET), source/drain regions104can include the substrate material, such as Si and SiGe, and p-type dopants. In some embodiments, the term “p-type” defines a structure, layer, and/or region as being doped with, for example, boron (B), indium (In), or gallium (Ga). In some embodiments, the term “n-type” defines a structure, layer, and/or region as being doped with, for example, phosphorus (P) or arsenic (As). An NFET device may be disposed in a p-type region of substrate102, or PWELL. A PFET device may be disposed in an n-type region of substrate102, or NWELL.

During operation of FinFET100, current flows between source/drain regions104, through channel110, in response to a voltage applied to gate structure108. Gate structure108surrounds three sides of the fin, so as to control the current flow through channel110. Gate structure108can be a multi-layered structure that includes (not shown) a gate electrode, a gate dielectric that separates the gate electrode from the fin, and sidewall spacers. Gate structure108can be made of polysilicon or metal. If metal is used for gate structure108, a temporary, or sacrificial, gate structure108may be formed initially from polysilicon and replaced with metal in a later operation. Gate structure108can be deposited, for example, by CVD, low pressure CVD (LPCVD), HDP CVD, plasma enhanced CVD (PECVD), or any other suitable deposition process. Gate structure108can be patterned using a photolithography process that employs a photoresist mask, a hard mask, or combinations thereof. Gate structure108can be etched using a dry etching process (e.g., reaction ion etching) or a wet etching process. In some embodiments, gas etchants used in the dry etching process can include chlorine, fluorine, bromine, or a combination thereof. In some embodiments, an ammonium hydroxide (NH4OH), sodium hydroxide (NaOH), and/or potassium hydroxide (KOH) wet etch can be used to pattern gate structure108, or a dry etch followed by a wet etch process can be used to pattern gate structure108.

A single FinFET100is shown inFIG.1. However, gate structure108may wrap around multiple fins105arranged along the y-direction to form multiple FinFETs100. Likewise, separated regions of a single fin may be controlled by multiple gate structures108, arranged along the x-direction, to form multiple FinFETs100.

When a voltage applied to gate structure108exceeds a certain threshold voltage, FinFET100switches on and current flows through channel110. When the applied voltage drops below the threshold voltage, FinFET100shuts off, and current ceases to flow through channel110. Because the wrap-around arrangement of gate structure108influences channel110from three sides, improved control of the conduction properties of channel110is achieved in FinFET100, compared with planar FETs, in which the gate influences current flow in the channel from a single side.

A FinFET in which channel110takes the form of a multi-channel stack is known as a gate-all-around (GAA) FET. In a GAAFET, the multiple channels within the stack are surrounded on all four sides by GAA gate structures, so as to further improve control of current flow in the stacked channels.

FIGS.2A-2Dillustrate different types of FinFET and GAAFET structures, in accordance with some embodiments.FIG.2Ashows an isometric view of a FinFET114having source/drain regions within fin105and a gate structure108.FIGS.2B-2Dshow similar isometric views of GAAFETs that are variations on the design of FinFET114. GAAFETs having 1-D, linear channels, or nanowires172are known as nanowire FETs116(FIG.2C); GAAFETs having 2-D channels, or nanosheets174, are known as nanosheet FETs118(FIG.2D). GAAFETs in which fins105have been recessed in the source/drain regions and replaced by epitaxial source/drain regions170are known as epi source/drain GAAFETs120(FIG.2B). FinFETs114and GAAFETs116,118, and120are formed on substrate102, in which devices are separated from one another by isolation regions103. Structures, such as those shown inFIGS.2A-2D, may be formed on a common substrate102, or on different substrates.

Embodiments of the present disclosure are shown and described, by way of example, as nanosheet FETs118(e.g., as shown inFIG.2D) or epi source/drain GAAFETs120(e.g., as shown inFIG.2B), where the nanosheet FETs118and epi source/drain GAAFETs120feature strained channels110. Strained channels as described herein may also be applied to other types of FETs—for example, FinFET114(e.g., as shown inFIG.2A) or nanowire FETs116(e.g., as shown inFIG.2C), or 2D planar FETs.

FIG.3is a flow diagram of a method300for fabricating fins105having either a monolithic structure for use in FinFETs114or nanostructured fins105for use in GAAFETs116,118, and120, according to some embodiments. For illustrative purposes, operations illustrated inFIG.3will be described with reference to an exemplary process for fabricating nanostructured fins105, as illustrated inFIGS.4A-4C,FIGS.5A-5E, andFIG.6, all of which are cross-sectional views of fins at various stages of their fabrication, according to some embodiments.

Operations of method300can be performed in a different order, or not performed, depending on specific applications. It is noted that method300may not produce a complete semiconductor device, e.g., GAAFET116,118, or120. Accordingly, it is understood that additional processes can be provided before, during, or after method300, and that some of these additional processes may only be briefly described herein.

Referring toFIG.3, in operation302, nanostructured fins105are formed on substrate102, as shown inFIGS.4A-4C. Nanostructured fins105will be part of adjacent GAAFETs118aand118b.First, a superlattice400can be formed on substrate102.FIG.4Aillustrates a cross-sectional view of substrate102prior to forming superlattice400, in which substrate102has a total height hsub.FIG.4Billustrates a cross-sectional view of substrate102after formation of superlattice400, including nanostructured channel layers421and nanostructured sacrificial layers422.FIG.4Cillustrates a cross-sectional view after formation of nanostructured fins105and STI regions103, where the view shown inFIG.4Cis transverse to that shown inFIG.4B.

In some embodiments, substrate102may or may not take the form of a silicon-on-insulator (SOI) substrate that includes a buried layer430e.g., a buried SiGe layer. Buried layer430is shown inFIGS.4A and4B. In some embodiments, a layer of SiGe may be deposited or grown on substrate102, followed by formation of a silicon layer above buried layer430. In some embodiments, a SiGe buried layer has a composition that includes a germanium content of about 30% to about 60%. In some embodiments, SiGe buried layer430has a composition that includes a germanium content of about 20%. Buried layer430may have a thickness in a range of about 1 nm to about 30 nm.

Referring toFIGS.4B and4C, superlattice400can include a stack of nanostructured layers421and422arranged in an alternating configuration. In some embodiments, nanostructured layers421include materials similar to one another, e.g., epitaxial Si, and nanostructured layers422include materials similar to one another, e.g., epitaxial SiGe. In some embodiments, superlattice400are formed by etching a stack of two different semiconductor layers (not shown) arranged in the alternating configuration. Nanostructured sacrificial layers422are replaced in subsequent processing, while nanostructured layers421remain as part of semiconductor devices118aand118b.AlthoughFIGS.4B and4Cshow four nanostructured layers421and four sacrificial nanostructured layers122, any number of nanostructured layers can be included in each superlattice400. The alternating configuration of superlattice400can be achieved by alternating deposition, or epitaxial growth, of SiGe and Si layers, starting from the top silicon layer of substrate102. Si layers can form nanostructured layers121, which are interleaved with SiGe nanostructured sacrificial layers122. Each of the nanostructured layers121-122may have thicknesses in a range of about 1 nm to about 5 nm. In some embodiments, the topmost nanostructured layers (e.g., Si layers) of superlattice400may be thicker than the underlying nanostructured layers.

The stack of two different semiconductor layers can be formed via an epitaxial growth process. The epitaxial growth process can include (i) chemical vapor deposition (CVD), such as low pressure CVD (LPCVD), rapid thermal chemical vapor deposition (RTCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer CVD (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), and other suitable CVD processes; (ii) molecular beam epitaxy (MBE) processes (iii) another suitable epitaxial process; or (iv) a combination thereof. In some embodiments, source-drain regions can be grown by an epitaxial deposition/partial etch process, which repeats the epitaxial deposition/partial etch process at least once. Such repeated deposition/partial etch process is also called a “cyclic deposition-etch (CDE) process.” In some embodiments, source-drain regions can be grown by selective epitaxial growth (SEG), where an etching gas can be added to promote selective growth on exposed semiconductor surfaces of substrate102or fin105, but not on insulating material (e.g., dielectric material of STI regions103).

Superlattice400can be doped by introducing one or more precursors during the above-noted epitaxial growth process. For example, the stack of two different semiconductor layers can be in-situ p-type doped during the epitaxial growth process using p-type doping precursors, such as diborane (B2H6) and boron trifluoride (BF3). In some embodiments, the stack of two different semiconductor layers can be in-situ n-type doped during an epitaxial growth process using n-type doping precursors, such as phosphine (PH3) and arsine (AsH3).

Next, superlattice400and underlying silicon substrate102can be patterned and etched to form fins105, as shown inFIG.4C. Top portions of fins105include the stacked layers e.g., Si/SiGe/Si. Bottom portions of fins105define trenches in substrate102and provide structural support for superlattice400. The trenches around fins105are then filled with an insulating material to form STI regions103, as shown inFIG.4C.

Insulating material in STI region103can include, for example, silicon oxide e.g., (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), or a low-k dielectric material, and/or other suitable insulating material. In some embodiments, STI regions103can include a multi-layered structure. In some embodiments, the process of depositing the insulating material can include any deposition method suitable for flowable dielectric materials (e.g., flowable silicon oxide). For example, flowable silicon oxide can be deposited for STI regions103using a flowable CVD (FCVD) process. The FCVD process can be followed by a wet anneal process. In some embodiments, the process of depositing the insulating material can include depositing a low-k dielectric material to form a liner. In some embodiments, a liner made of another suitable insulating material can be placed between STI region103and adjacent FETs.

In some embodiments, STI regions103may be annealed. Annealing the insulating material of STI regions103can include annealing the deposited insulating material in a steam environment at a temperature in a range from about 200° C. to about 700° C. for a time period in a range from about 30 min to about 120 min. The anneal process can be followed by a polishing process that can remove a surface layer of the insulating material. The polishing process can be followed by an etching process to recess the polished insulating material to form STI regions103.

Recessing the polished insulating material can be performed, for example, by a dry etch process, a wet etch process, or a combination thereof. In some embodiments, the dry etch process for recessing the polished insulating material can include using a plasma dry etch with a gas mixture that can include octafluorocyclobutane (C4F8), argon (Ar), oxygen (O2), helium (He), fluoroform (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), chlorine (Cl2), hydrogen bromide (HBr), or a combination thereof with a pressure ranging from about 1 mTorr to about 5 mTorr. In some embodiments, the wet etch process for recessing the polished insulating material can include using a diluted hydrofluoric acid (DHF) treatment, an ammonium peroxide mixture (APM), a sulfuric peroxide mixture (SPM), hot deionized water (DI water), or a combination thereof. In some embodiments, the wet etch process for recessing the polished insulating material can include using an etch process that uses ammonia (NH3) and hydrofluoric acid (HF) as etchants and inert gases, such as Ar, xenon (Xe), He, and a combination thereof. In some embodiments, the flow rate of HF and NH3used in the etch process can each range from about 10 sccm to about 100 sccm (e.g., about 20 sccm, 30 sccm, or 40 sccm). In some embodiments, the etch process can be performed at a pressure ranging from about 5 mTorr to about 100 mTorr (e.g., about 20 mTorr, about 30 mTorr, or about 40 mTorr) and a temperature ranging from about 50° C. to about 120° C.

Referring toFIG.3, in operation304, a flowable insulating material500acan be deposited over nanostructured fins105as illustrated inFIG.5A. In some embodiments, flowable insulating material500ahas a depth Dain a range of about 800 Å to about 2200 Å. In some embodiments, flowable insulating material500acan be deposited using a flowable chemical vapor deposition (FCVD) process similar to processes that can be used to deposit STI regions103. Flowable insulating material500amay provide improved gap fill around high-aspect ratio fin structures, compared with blanket depositing a non-flowable insulating material. In some embodiments, flowable insulating material500acan be deposited in a heated tube that is otherwise utilized in manufacturing glass fibers.

Referring toFIG.3, in operation305, flowable insulating material500acan be cured by exposure to UV light. The curing operation can solidify and seal flowable insulating material500ato provide structural stability, and to allow the material to withstand subsequent processing operations.

Referring toFIG.3, in operation306, fins105and flowable insulating material500acan be annealed to densify and further strengthen flowable insulating material500a.In some embodiments, the anneal temperature is in a range of about 500° C. to about 800° C. In some embodiments, the annealing process is performed at a temperature that is below a characteristic temperature at which flowable insulating material500acould re-flow. For example, instead of annealing at a temperature between about 500° C. to about 800° C., a low-temperature anneal below about 400° C. can be used. Referring toFIG.3, in operation308, a cap oxide502can be deposited on top of flowable insulating material500a,as shown inFIG.5B. In some embodiments, cap oxide502can be made of silicon dioxide (SiO2), which can be deposited using a plasma enhanced chemical vapor deposition (PECVD) process. In some embodiments, cap oxide502can have an as-deposited thickness trap in a range of about 1000 Å to about 2000 Å. The addition of cap oxide502can provide a larger window for a subsequent polishing process and can enhance depth control during the polishing operation.

Referring toFIG.3, in operation310, chemical mechanical planarization (CMP), also known as a polishing process, can be used to planarize the structure shown inFIG.5Bdown to top surfaces of fins105, as shown inFIG.5C. In some embodiments, the CMP process can remove all of cap oxide502as well as a thickness of flowable insulating material500aabove top surfaces of fins105, until flowable insulating material500ais coplanar with top surfaces of fins105.

Referring toFIG.3, in operation312, planarized fins105can be annealed a second time. In some embodiments, the second annealing process can be similar to, or the same as, the annealing process in operation310.

Referring toFIG.3, in operation314, flowable insulating material500acan be recessed to expose top portions of fins105, creating arrays of tapered fins505, as shown inFIG.5DandFIG.6. Fin recess can be accomplished by etching flowable insulating material500a,e.g., STI oxide, selective to fins105, e.g., silicon or SiGe. In some embodiments, the fin recess can include removing portions of the fins105to adjust a taper of the tapered fins505.

In some embodiments, operation314includes a plasma etching process, a wet etch process, or combinations thereof. The etching process used to recess flowable insulating material500amay be sensitive to pattern density, which can load the etch chemistry so as to cause tapered fins505to have fin profiles that flare at the bottom as shown inFIG.6. Bottom portions of tapered fins505may be more flared for smaller fin widths and spacings than for larger fin widths and spacings.

FIG.6shows a magnified view of an exemplary tapered fin505, according to some embodiments.FIG.6illustrates a single tapered fin505, indicating relevant height and width dimensions. For example, a fin top height htopof tapered fin505, from the top of tapered fin505to the surface of flowable insulating material500a,can be in a range of about 45 nm to about 55 nm. Near the exposed top surface of flowable insulating material500a,a bottom width of tapered fins505, wbot, can be as much as several times wider than a top width, wtop, of tapered fins505. In some embodiments of tapered fins505, wbois in a range of about 18 nm to about 22 nm. Because current flows through tapered fins505, in FinFETs and in GAAFETs, non-uniformities in the fin profile, as well as profile variations among fins can compromise device performance of transistors114,116,118, and120.

Following fin recess, tapered fins505can be trimmed and a thin silicon cap (not shown) can be grown on top of tapered fins505. Trimming lower portions of tapered fins505to a prescribed height can be an optional operation that is performed if needed, based on measurements of wbot. In some embodiments, the silicon cap has a thickness in a range of about 1 Å to about 2 Å.

FIG.7is a flow diagram of a method700for fabricating substantially uniform fins805from tapered fins505, according to some embodiments. For illustrative purposes, operations illustrated inFIG.7will be described with reference to the exemplary process for transforming tapered fins505into uniform fins805, as illustrated inFIGS.8A-8DandFIG.9B, which are cross-sectional views of uniform fins805, at various stages of their fabrication, according to some embodiments.

Operations of method700can be performed in a different order, or not performed, depending on specific applications. It is noted that method700may not produce a complete semiconductor device. Accordingly, it is understood that additional processes can be provided before, during, or after method700, and that some of these additional processes may only be briefly described herein.

Method700provides fin profile optimization from a tapered profile to a substantially uniform profile throughout the top height of tapered fins505. Method700also provides fin top height control modulation using extra physical shaping steps for pattern loading reduction. These improvements in the fin profile can be accomplished by stacking and refilling the FCVD film multiple times and by using composition tuning during the FCVD process, to further modulate fin profiles.

Referring toFIG.7, in operation702, another layer of flowable insulating material,500b,is deposited over tapered fins505as shown inFIG.8A. In some embodiments, flowable insulating material500bhas a depth Dbin a range of about 800 Å to about 2200 Å. In some embodiments, flowable insulating material500bcan be deposited in a heated tube that is otherwise utilized in manufacturing glass fibers. In some embodiments, flowable insulating material500bcan be deposited using a flowable chemical vapor deposition (FCVD) process similar to processes that can be used to deposit STI regions103, and similar to the FCVD process used to deposit flowable insulating material,500ain operation302of method300. In some embodiments, the FCVD process used during operation702can be modified from that used during operation302to tune the composition of flowable insulating material500bdifferently from the composition of flowable insulating material500a.For example, the deposition of flowable insulating material500bmay occur in the presence of different gases, such as argon and oxygen, or different gas flows, than were used to deposit flowable insulating material500a.Furthermore, gas flows used during deposition of flowable insulating material500baround tapered fins505may also alter, or tune, the composition of tapered fins505. Tuning the composition of flowable insulating material500band/or tapered fins505may produce films that respond differently to subsequent etching and polishing operations, as described below.

Referring toFIG.7, in operation704, flowable insulating material500bcan be cured by exposure to UV light. The curing operation can solidify and seal flowable insulating material500bto provide structural stability, and to allow the material to withstand subsequent processing operations.

Referring toFIG.7, in operation706, tapered fins505and flowable insulating material500acan be annealed to densify and further strengthen flowable insulating material500a.In some embodiments, the anneal temperature is in a range of about 500° C. to about 800° C.

Referring toFIG.7, in operation708, a cap oxide502can be deposited on top of flowable insulating material500aas shown inFIG.8B. In some embodiments, cap oxide502can be made of silicon dioxide (SiO2), which can be deposited using a plasma enhanced chemical vapor deposition (PECVD) process. In some embodiments, cap oxide502can have an as-deposited thickness tcapin a range of about 1000 Å to about 2000 Å. The addition of cap oxide502can provide a larger window for a subsequent polishing process and can enhance depth control during the polishing operation.

Referring toFIG.7, in operation710, chemical mechanical planarization (CMP), also known as a polishing process, can be used to planarize the structure shown inFIG.8Bdown to top surfaces of tapered fins505, as shown inFIG.8C. In some embodiments, the CMP process can remove all of cap oxide502as well as a thickness of flowable insulating material500babove top surfaces of tapered fins505, until flowable insulating material500bis coplanar with top surfaces of tapered fins505.

Referring toFIG.7, in operation712, planarized tapered fins505can be annealed a second time. In some embodiments, the second annealing process can be similar to, or the same as, the annealing process in operations306,312, and706.

Referring toFIG.7, in operation714, flowable insulating material500acan be recessed to expose top portions of uniform fins805, as shown inFIG.8DandFIG.9B. The fin recess operation can be used to adjust the top height htopof uniform fins805to substantially match a top height of tapered fin505.

Fin recess can be accomplished by etching flowable insulating material500a,e.g., oxide, selective to uniform fins805, e.g., silicon or SiGe. In some embodiments, operation714can use a plasma etching process, a wet etch process, or combinations thereof. In some embodiments, a dry etch process may utilize a gas mixture that includes, for example, octafluorocyclobutane (C4F8), argon (Ar), oxygen (O2), helium (He), fluoroform (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), chlorine (Cl2), hydrogen bromide (HBr), or a combination thereof with a pressure ranging from about 1 mTorr to about 500 mTorr. In some embodiments, the wet etch process can include using a diluted hydrofluoric acid (DHF) treatment, an ammonium peroxide mixture (APM), a sulfuric peroxide mixture (SPM), hot deionized water (DI water), tetramethylammonium hydroxide (TMAH), or a combination thereof. Other gas species or chemicals suitable for the etching process are within the scope and spirit of this disclosure.

FIG.9AreproducesFIG.6, showing a magnified view of a tapered fin505for comparison withFIG.9B, which shows a magnified view of uniform fin805, according to some embodiments.FIG.9Billustrates a single uniform fin805, indicating relevant height and width dimensions. For example, a fin top height htopof both tapered fin505and uniform fin805, from the top of fins505and705to the surface of flowable insulating material500/500acan be in a range of about 45 nm to about 55 nm. With reference toFIG.9B, near the exposed top surface of flowable insulating material500a,a bottom width of uniform fin805, wbot, is approximately equal to a top width, wtop, of uniform fin805. In some embodiments, the width of uniform fin805is in a range of about 3 nm to about 8 nm.FIG.9Bshows that the additional FCVD refill operation702has effectively buried the widest lower portion of the fin and retained the uniform upper portion as fin805.

Referring still toFIG.7, in operation714and following the fin recess, uniform fins805can be trimmed and a silicon cap (not shown) can be grown on top of uniform fins805. Trimming lower portions of uniform fin805can be an optional operation that is done if needed, based on measurements of wbot. In some embodiments, the silicon cap has a thickness in a range of about 1 Å to about 2 Å.

FIGS.10A and10Bshow variations in NMOS and PMOS fin profiles, respectively, according to some embodiments. The rightmost profiles correspond to tapered fin505. The leftmost fin profiles correspond to substantially uniform fins805, for different deposition process parameters used in FCVD refill operation702. In some embodiments, first and second sets of process conditions “FCVD1” and “FCVD2,” respectively, can correspond to different gas chemistries used during flowable CVD deposition, e.g., different amounts of oxygen (O2) flow, and argon (Ar) flow that can be present during deposition to tune the composition of uniform fins805. In some embodiments, first and second sets of process conditions “FCVD1” and “FCVD2,” respectively, can correspond to different ultraviolet (UV) light conditions used in post-FCVD UV cure operation704. Variations in process conditions used during operations702and704may be combined to further shape fin profiles to achieve substantially vertical fin profiles having a substantially uniform width along the exposed top height of uniform fins805.

FIG.11shows an array of substantially uniform fins805, following two iterations of method700, according to some embodiments.FIG.11shows that a first FCVD refill operation702has been performed to deposit flowable insulating material500a.In addition,FIG.11shows that a second FCVD refill operation702has also been performed to deposit flowable insulating material500b,after repeating operations704-714of method700, including curing, annealing, polishing, recessing trimming, and capping uniform fins805. Following two iterations of method700, a final thickness t of flowable insulating material between uniform fins805, including flowable insulating materials500aand500bcan be in a range of about 500 Å to about 4000 Å. The final thickness t will be substantially the same as the remaining thickness of500ainFIG.5D. In some embodiments, method700can be repeated any number of times, thus stacking multiple layers of flowable insulating material among tapered fins505, to further modulate profiles of uniform fins805.

FIG.12is a flow diagram of a method1200for fabricating nanosheet GAAFETs118and120from nanostructured uniform fins805, according to some embodiments. For illustrative purposes, operations illustrated inFIG.12will be described with reference to the exemplary process as illustrated inFIGS.13A-13BandFIGS.14A-14E, which are cross-sectional views of GAAFETs120at various stages of their fabrication, according to some embodiments.

Operations of method1200can be performed in a different order, or not performed, depending on specific applications. It is noted that method1200may not produce a complete semiconductor device, e.g., GAAFET116,118, or120. Accordingly, it is understood that additional processes can be provided before, during, or after method1200, and that some of these additional processes may only be briefly described herein.

Referring again toFIG.12, following formation of superlattice400, in operation1204, a sacrificial gate structure1307can be formed on superlattice400, as shown inFIG.13A. Sacrificial gate structure107can later be replaced by a metal gate structure108having sidewall spacers1328as shown inFIG.13B. Sacrificial gate structure1307can be deposited and then patterned using a hard mask, e.g., an oxide material that can be grown and/or deposited using an ALD process. When sacrificial gate structure1307is replaced by a metal gate108, gate-all-around (GAA) structures1358will also replace sacrificial layers422in gate region1357.

Still referring toFIG.12, in operation1204, gate spacers1328can be formed on sacrificial gate structure1307. The process of forming gate spacers1328can include conformally depositing a spacer material layer to cover sidewalls of polysilicon sacrificial gate structure1307, superlattice400, and STI regions103. In some embodiments, the spacer material layer can include (i) a dielectric material, such as silicon oxide, silicon carbide, silicon nitride, and silicon oxy-nitride, (ii) an oxide material, (iii) a nitride material, (iv) a low-k material, or (v) a combination thereof. The process of forming gate spacers1328can further include patterning processes e.g., lithography and etching processes. In some embodiments, the etching process can be an anisotropic etch that removes the spacer material layer faster on horizontal surfaces (e.g., on the X-Y plane) compared to vertical surfaces (e.g., on the Y-Z or X-Z planes). In some embodiments, the gate spacers1328can have a thickness in a range of about 1 nm to about 8 nm.

Referring toFIG.12, in operation1206, superlattice400, which makes up uniform fins805, can be etched back in source/drain regions, as shown by the dashed lines and arrows inFIG.13A. The etch-back operation can use any suitable etching process described above. Following the etch-back operation, layers of superlattice400remain in a channel region1357underneath sacrificial gate structure1307as shown inFIG.13B.

Referring toFIG.12, in operation1208, epitaxial source/drain regions170can be formed, as shown inFIG.13B. In some embodiments, epitaxial source/drain regions170made of silicon or SiGe are grown from nanostructured layers421and/or422of superlattice400underneath sacrificial gate structure1307. Epitaxial source/drain regions170can have elongated hexagonal-shaped cross-sections as shown inFIG.2B. Epitaxial source/drain regions170can be formed in similar fashion as other epitaxial layers described above.

Referring toFIG.12, in operation1210, an inter-layer dielectric (ILD)1330can be formed, as shown inFIG.13B, through which electrical contacts can be made to source, drain, and gate terminals of nanosheet FETs118aand118b.ILD1330may include silicon dioxide or a low-k dielectric material, such as a fluorosilicate glass, a carbon-doped silicon dioxide, a porous silicon dioxide, a porous carbon-doped silicon dioxide, a hydrogen silsesquioxane, a methylsilsesquioxane, a polyimide, a polynorbornene, a benzocyclobutene, and a polytetrafluoroethylene. For forming ILD1330, a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, and spin coating, may be performed.

Referring toFIG.12, in operation1212, sacrificial structure1307can be removed and replaced with a metal gate108and gate-all-around structures1358, as shown inFIGS.13B and14B-14E. In operation1212, nanostructured layers422are selectively removed to form gate openings1409in the channel region. Gate openings1409are then filled with metal by depositing gate structure108, to complete GAA channel region1357, as shown inFIG.14D. Remaining nanostructured channel layers421of superlattice400form nanostructured channels110of nanosheet FETs118aand118b.Each of GAA channel regions1357can include GAA structures1358(two shown inFIG.14C).

FIGS.14A-14Eare magnified views showing operations for forming gate structure108and GAA channel region1357, shown inFIG.14C, according to some embodiments. GAA channel region1357includes multiple GAA structures1358, which surround channels110to control current flow therein. Each GAA structure1358can be viewed as a radial gate stack that includes, from the outermost layer to the innermost layer, a gate dielectric layer1461, a work function metal layer1462, and a gate electrode1463. Gate electrode1463is operable to maintain a capacitive applied voltage across nanostructured channels110. Gate dielectric layer1461separates the metallic layers of GAA structure1358from nanostructured channels110. Inner spacers1464electrically isolate GAA structure1358from epitaxial source/drain region1470and prevent current from leaking out of nanostructured channels110.

FIG.14Ais a magnified cross-sectional view of superlattice400and sacrificial structure1307shown inFIG.4C. When superlattice400is etched back, a remaining portion of superlattice400is in GAA channel region1357, underneath sacrificial structure1307. Inner spacers1464are then formed adjacent to nanostructured layers422in the GAA channel region1357.

FIG.14Bis a magnified cross-sectional view of nanosheet FETs118.FIG.4Billustrates GAA channel region1357following formation of inner spacers1464and epitaxial source/drain regions170which can be grown laterally outward, in the x-direction, from nanostructured layers121.

FIG.14Cshows GAA channel region1357, following extraction of nanostructured layers422and thus forming gate openings1409.

FIG.14Dis a magnified view of GAA channel region1357, shown inFIG.13B, following replacement of sacrificial structure1307with gate structure108. First, sacrificial structure1307is removed, leaving sidewall spacers1328in place. Then, gate structure108is grown in a multi-step process to form a metal gate stack in place of sacrificial structure1307. Simultaneously, the radial gate stack is formed to fill gate openings1409from the outside in, starting with gate dielectric layer1461, and ending with gate electrode1463.

Referring toFIG.14E, gate dielectric layer1461can have a thickness between about 1 nm and about 5 nm. Gate dielectric layer1461can include a silicon oxide and may be formed by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), e-beam evaporation, or another suitable deposition process. In some embodiments, gate dielectric layer1461includes a high-k material, where the term “high-k” refers to a high dielectric constant. In the field of semiconductor device structures and manufacturing processes, high-k refers to a dielectric constant that is greater than the dielectric constant of SiO2(e.g., greater than 3.9). In some embodiments, the dielectric layer can include a silicon oxide, silicon nitride, and/or silicon oxynitride material, or a high-k dielectric material, such as hafnium oxide (HfO2). A high-k gate dielectric may be formed by ALD and/or other deposition methods. In some embodiments, the gate dielectric layer can include a single layer or multiple insulating material layers.

Gate work function metal layer1462can include a single metal layer or a stack of metal layers. The stack of metal layers can include metals having work functions similar to or different from each other. In some embodiments, the gate work function metal layer can include, for example, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), cobalt (Co), metal nitrides, metal silicides, metal alloys, and/or combinations thereof. The gate work function metal layer can be formed using a suitable process, such as ALD, CVD, PVD, plating, and combinations thereof. In some embodiments, the gate work function metal layer can have a thickness in a range of about 2 nm to about 15 nm.

Gate electrode1463may further include a gate metal fill layer. The gate metal fill layer can include a single metal layer or a stack of metal layers. The stack of metal layers can include metals different from each other. In some embodiments, the gate metal fill layer can include one or more suitable conductive materials or alloys, such as Ti, Al, TiN, and the like. The gate metal fill layer can be formed by ALD, PVD, CVD, or other suitable deposition processes. Other materials, dimensions, and formation methods for the gate dielectric layer161, the gate work function metal layer1462, and the gate electrode1463are within the scope and spirit of this disclosure.

Following formation of gate structures108and GAA structures1358in GAA channel regions1357, the structures of nanosheet FETs118aand118b,which include uniform fins805, are substantially complete, as shown in the isometric view ofFIG.2Band the cross-sectional view ofFIG.13B.

In some embodiments, a method includes: forming fins on a substrate; forming an insulating material between the fins; depositing a oxide over the insulating material to refill a space between the fins; exposing the fins to a first annealing process; planarizing the oxide; exposing the fins to a second annealing process; and recessing the fins to expose top portions of the fins.

In some embodiments, a method includes: forming, on an isolation region, fins with each fin having a base portion and a top portion narrower than the base portion; depositing a refill material to cover the base portions of the fins to form substantially uniform fins having substantially vertical sidewalls; curing the refill material; annealing the fins; and recessing a portion of the refill material to adjust a height of the fins.

In some embodiments, a structure includes: a semiconductor substrate; an insulating material in the semiconductor substrate; and an array of fins extending out from a surface of the semiconductor substrate, where adjacent fins of the array of fins are separated by the insulating material, and where the array of fins has substantially equal fin widths and substantially equal fin heights.