Semiconductor package

The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least one opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor package, and more particularly to a semiconductor package which can avoid solder bridge.

2. Description of the Related Art

FIGS. 1 to 4show schematic views of a method for making a conventional semiconductor package. As shown inFIG. 1, a substrate11is provided. The substrate11has a first surface111, a second surface112, a plurality of first pads113, a plurality of second pads114, a Ni/Au plating layer115and a solder mask116. The first pads113are exposed to the first surface111. The second pads114are exposed to the second surface112. The Ni/Au plating layer115is formed on the entire upper surface of the first pad113. The solder mask116contacts the Ni/Au plating layer115directly, and has at least one opening so as to expose part of the Ni/Au plating layers115. Then, a chip12is mounted on the substrate11, and a plurality of conductive elements (for example, a plurality of wires13) are formed so as to electrically connect the chip12and the first surface111of the substrate11. Then, a plurality of first conductors (for example, a plurality of first solder balls14) are formed on the Ni/Au plating layer115.

As shown inFIG. 2, a molding compound15is formed on the first surface111of the substrate11, so as to encapsulate the chip12, the wires13and the first solder balls14. As shown inFIG. 3, a plurality of second solder balls16are formed on the second pads114, and the second solder balls16are reflowed. As shown inFIG. 4, part of a periphery area of the molding compound15is removed, so that the molding compound15has at least two heights, and one end of the first solder balls14is exposed. Thus, the conventional semiconductor package1is formed.

The conventional semiconductor package1has the following disadvantages. First, the solder mask116contacts the Ni/Au plating layer115directly, however the solder mask116and the Ni/Au plating layer115has low bonding strength, therefore delamination between the solder mask116and the Ni/Au plating layer115occurs easily. Moreover, the Ni/Au plating layer115disposed on the first solder balls14is encapsulated by the molding compound15, and when the second solder balls16are reflowed, the first solder balls14expand because of high temperature. Meanwhile, the first solder balls14extrude to adjacent elements and protrude to the interface between the solder mask116and the Ni/Au plating layer115which has low bonding strength. As a result, it leads to the bridge between the first solder balls14, as shown in area A ofFIGS. 3 to 5, and the yield rate of the semiconductor package is decreased.

Therefore, it is necessary to provide a semiconductor package to solve the above problems.

SUMMARY OF THE INVENTION

The present invention is directed to a semiconductor package. The semiconductor package comprises a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a first surface, a second surface, a plurality of first pads and a solder mask. The first pads are exposed to the first surface, and the material of the first pads is copper. The solder mask directly contacts the first pads, and has at least one opening so as to expose part of the first pads. The chip is mounted on the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and the first conductors. The molding compound has a first top surface and a second top surface. The horizontal level of the first top surface is different from that of the second top surface, and one end of the first conductors is exposed. A top surface of the exposed first conductors is level with the second top surface of the molding compound.

The present invention is further directed to a semiconductor package. The semiconductor package comprises a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a first surface, a second surface, a plurality of first pads and a solder mask. The first pads are exposed to the first surface, and the material of the first pads is copper. The solder mask directly contacts the first pads, and has at least one opening so as to expose part of the first pads. The chip is mounted on the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. The molding compound has a first surface and a plurality of blind holes. The blind holes open at the first surface of the molding compound, and expose part of the first conductors.

Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 6shows a cross-sectional view of a semiconductor package according to a first embodiment of the present invention. The semiconductor package2comprises a substrate21, at least one chip22, a plurality of conductive elements (for example, a plurality of wires23), a plurality of first conductors (for example, a plurality of first solder balls24), a molding compound25and a plurality of second solder balls26. The substrate21has a first surface211, a second surface212, a plurality of first pads213, a plurality of second pads214, a solder mask216and an anti-oxidation layer217.

The first pads213are exposed to the first surface211, and the material of the first pads213is copper. The second pads214are exposed to the second surface212. The solder mask216contacts the first pads213directly, and has at least one opening so as to expose part of the first pads213. The anti-oxidation layer217is disposed on the first pads213exposed to the opening of the solder mask216. That is, the anti-oxidation layer217does not completely cover the entire upper surface of the first pad213. In the embodiment, the anti-oxidation layer217is a Ni/Au plating layer. However, in other applications, the anti-oxidation layer217can be an organic solderability preservative (OSP), and the anti-oxidation layer217does not exist in the final structure. Therefore, the present invention can avoid the first pads213from oxidizing after being exposed in the air, and thus the yield rate of the semiconductor package is increased.

The chip22is mounted on the substrate21. In the embodiment, the chip22is adhered to the solder mask216. In the present invention, the form of the chip22has no limitation. The wires23electrically connect the chip22and the substrate21. The first solder balls24are disposed on the first pads213, preferably, the first solder balls24are hemispheres. The second solder balls26are disposed on the second pads214.

The molding compound25is disposed on the first surface211of the substrate21, and encapsulates the chip22, the wires23and the first solder balls24. The molding compound25has a first top surface251and a second top surface252, the horizontal level of the first top surface251is different from that of the second top surface252, and one end of the first solder balls24is exposed. A top surface of the exposed first solder balls24is level with the second top surface252of the molding compound25.

The molding compound25has a first height H1and a second height H2, the first height H1is the height from the first top surface251to the solder mask216, the second height H2is the height from the second top surface252to the solder mask216, and the first height H1is greater than the second height H2.

FIG. 7shows a cross-sectional view of a semiconductor package according to a second embodiment of the present invention. The semiconductor package3comprises a substrate31, at least one chip32, a plurality of conductive elements (for example, a plurality of wires33), a plurality of first conductors (for example, a plurality of first solder balls34), a molding compound35and a plurality of second solder balls36. The substrate31has a first surface311, a second surface312, a plurality of first pads313, a plurality of second pads314, a solder mask316and an anti-oxidation layer317.

The first pads313are exposed to the first surface311, and the material of the first pads313is copper. The second pads314are exposed to the second surface312. The solder mask316contacts the first pads313directly, and has at least one opening so as to expose part of the first pads313. The anti-oxidation layer317is disposed on the first pads313exposed to the opening of the solder mask316, preferably, the anti-oxidation layer317is an organic solderability preservative (OSP) or a Ni/Au plating layer. Therefore, the present invention can avoid the first pads313from oxidizing after being exposed in the air, and thus the yield rate of the semiconductor package is is increased.

The chip32is mounted on the substrate31. In the embodiment, the chip32is adhered to the solder mask316. In the present invention, the form of the chip32has no limitation. The wires33electrically connect the chip32and the substrate31. The first solder balls34are disposed on the first pads313. The second solder balls36are disposed on the second pads314. The molding compound35is disposed on the first surface311of the substrate31, and encapsulates the chip32, the wires33and part of the first solder balls34. The molding compound35has a first surface351and a plurality of blind holes352. The blind holes352open at the first surface351of the molding compound35, and expose part of the first solder balls34.

Therefore, the solder masks216,316contact the first pads213,313directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors (the first solder balls24,34) caused by the first conductors (the first solder balls24,34) permeating into the interface between the solder masks216,316and the first pads213,313.

While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope defined by the appended claims.