Method and apparatus for routing transactions through partitions of a system-on-chip

A node having a node input is configured to receive a plurality of transactions intended for a plurality of different targets. The node has multiple node outputs. At least one target is provided, that target including an input configured to receive a respective output of the node. The node is configured to direct transactions to the at least one target or an output (for passing to a different partition) depending on whether the transactions are intended for the target or a different target. This determination is made in response to a conversion operation which converts a target address of the transaction to an identification associated with the target or the output.

PRIORITY CLAIM

This application claims priority from European Application for Patent No. 10425386.9 filed Dec. 16, 2010, the disclosure of which is hereby incorporated by reference.

TECHNICAL FIELD

The present invention relates to an arrangement and particularly but not exclusively to an arrangement in a partition of a system on chip.

BACKGROUND

Integrated circuits have an ever increasing number of components on them. A System-on-Chip (SoC) provides multiple computer components or in some cases entire electronic systems on a single chip. Further, modern SoCs in application domains integrate several peripherals in order to meet the requirements of a wide range of applications. The level of integration is being increased by the usage of smaller silicon feature technology, for example at the moment 32 nanometers.

SUMMARY

According to an aspect, there is provided an arrangement comprising a node having a node input configured to receive a plurality of transactions intended for a plurality of different targets, said node having a plurality of node outputs; at least one target, said at least one target comprising an input configured to receive a respective output of said node; an output, wherein said node is configured to direct said transactions to one of said at least one target and said output depending on if said transactions are intended for said at least one target or at least one different target.

According to another aspect, there is provided a method comprising receiving a plurality of transactions intended for a plurality of different targets, said node having a plurality of node outputs, at least one node output providing an input to a target and at least one output providing an input to a further node; directing said transactions to a respective one of said node outputs depending on if said transactions are intended for said at least one target or at least one different target which is downstream of said further node.

According to another aspect, a first partition of a system-on-chip includes: a first output node coupled to a bus; a first plurality of peripherals; a first address-to-identification converter operable to convert a target address of a transaction to a first identification associated with said address, said first identification either specifically identifying one of the first plurality of peripherals in the first partition as the target of the transaction or generally identifying a peripheral target outside of the first partition as the target of the transaction; and a first routing node configured to receive both the transaction and the first identification, the first routing node operable to route the received transaction based on the received identification to: (a) one of the first plurality of peripherals when the first identification is one of the first plurality of peripherals in the first partition or (b) said first output node when the first identification is a peripheral target outside of the first partition.

DETAILED DESCRIPTION OF THE DRAWINGS

Reference is made toFIG. 1.FIG. 1shows a first system on chip2. The first system on chip2comprises a first partition6, a second partition8and a third partition10. The partitions may be physical partitions in the silicon of the integrated circuit or any other suitable segregation of the system on chip. The partitions may be conceptual in some embodiments and are used to subdivide the SoC into different blocks. The partitions each comprise one or more peripherals. In the case of the first partition6, a video decoder12provides a first peripheral and a GFX (graphic effect)14provides a second peripheral. The second partition8comprises a first peripheral in the form of a DMA (direct memory access)16and a second peripheral VDP (video display processor)18. The third partition10has a first peripheral USB (universal serial bus)20and a second peripheral SATA (serial advanced technology attachment)22.

Interconnect23, part of the peripheral bus of the system on chip, is arranged in the first partition to connect or couple to the video decoder12and the GFX14to an interconnect24. The interconnect24, which is also part of the peripheral bus of the system on chip, connects or couples the first partition6and the second partition8. The interconnect24connects or couples to the DMA16and, the VDP18and to another interconnect26, which again is part of the peripheral bus. The interconnect26connects or couples the second partition8and the third partition10. The interconnect26is connected or coupled to the USB20and SATA22.

As can be seen, the partitions are daisy chained together. The first partition connects to the second partition which connects to the third partition. This is to minimize the inter-partition routing.

FIG. 2ashows a second system on chip where some redesign of the system on chip ofFIG. 1has taken place. This system on chip4has a first partition6a, a second partition8aand a third partition10a. The first partition10ahas a video decoder12aand a SATA22a. The second partition has a VDP18a. The third partition has a USB20a, a DMA16aand a GFX14a. Thus, as compared to the system on chip ofFIG. 1, some peripherals have moved to different partitions. The peripheral bus has however continued to have the same routing with respect to the peripherals, as shown inFIG. 1. Thus, a first interconnect23aon the first partition is connected to the video decoder12aof the first partition, the GFX of14aof the third partition via connection30and via interconnect24ato the second partition. It should be appreciated that in order to have the connection to GFX14a, the connection30is a new connection between the first partition6aand the third partition10a.

Similarly, peripheral bus24ais connected to VDP18aon the second partition and also to DMA16aon the third partition. To achieve this, an additional connection25ais provided between the second partition8aand the third partition10b. Finally, interconnect26ais provided between the second partition and the third partition as inFIG. 1. In order that interconnect26ais connected to SATA22aon the first peripheral device, an additional interconnect32is provided between the second partition8aand the first partition6a. The interconnect26ais connected to USB20aon the third partition10a. Thus, the same peripheral bus pattern as shown inFIG. 1is used but where a peripheral device has changed from one partition to another, additional routing is added to the peripheral bus. Increased inter-partition routing is undesirable as this increases the complexity of the integrated circuit and is undesirable from a physical layout perspective.

FIG. 2bshows an alternative to the arrangement ofFIG. 2awhere the system on chip ofFIG. 1again is again redesigned. It should be appreciated that the system on chip ofFIG. 2ais the same as the system on chip ofFIG. 2bbut the routing provided is different. The system on chip42shown inFIG. 2bcomprises a first partition6bwith a video decoder12band a SATA22b. A second partition8bcomprises a VDP18b. A third partition10bis provided with a DMA16b, a GFX14band a USB20b.

As can be seen, the peripherals have been rearranged in the same manner as shown inFIG. 2a. However, instead of maintaining the peripheral bus arrangement ofFIG. 1, the peripheral bus arrangement has been redesigned. Accordingly, there is an interconnect24bbetween the first partition6band the second partition8b. There is an interconnect26bbetween the second partition8band the third partition10b. However, this has required the peripheral bus to be redesigned or requires a system on chip memory map to be altered. Thus, the interconnect23bon the first partition6bis now connected to SATA22b, video decoder12band the interconnect24b. The interconnect24bis connected to VDP18band interconnect26b. The interconnect26bis thus connected to DMA16b, GFX14band USB20b. Thus, although the arrangement ofFIG. 2is advantageous in that the number of interconnects between partitions is reduced or minimized, this makes the reuse of designs more complex and involves more design time.

Reference is made toFIG. 3which shows an embodiment.FIG. 3shows a system on chip50which has a first partition52, a second partition54and a third partition56. The first partition comprises a video decoder58and a GFX60. The second partition54comprises a DMA62and a VDP64. The third partition56comprises a SATA66and a USB68. The first partition is connected to the second partition54via a peripheral bus70. The second partition54is connected to the third partition56via a peripheral bus72. Thus, in the embodiment shown inFIG. 3, the partitions are daisy chained together, thus removing any issue of routing complexity.

The first partition is provided with a node72. The node72is arranged to receive a transaction which is to be passed to one of the peripheral units of the system on chip. The transactions may be received from an NoC (Network on Chip) source73. The transaction information is input to the node72. This transaction information can include one or more of the following: data, opcode, request, acknowledgement or any other suitable information.

The node72is also arranged to receive an output from the address to ID converter74.

This address converter74is configured to receive the address associated with the transaction. The address is also provided to the node. The address generator74is configured to output an ID associated with that address. The address is the address of the target peripheral (defining a particular location in that target) and is part of the data transaction. For the transactions intended for a peripheral, the address needs to be associated with the transaction. The function of the address converter74will be described in more detail later.

The node72is arranged to have a first connection to the video decoder58, a second connection to the GFX60and a third connection to a transmitter76. The output of the transmitter76comprises the peripheral bus70. The peripheral bus70is input to a receiver78on the second partition54. The output of the receiver78is input to a second node80. In particular, the receiver78is arranged to output the address to an address converter82, similar to the address converter74of the first partition as well as to the second node. The output of the second address converter is an identifier ID which is input to the second node80. The remaining part of the transaction is, as with the first node, output by the receiver78to the second node.

The node80is connected the VDP64, the DMA62and to a transmitter84on the second partition. The transmitter on the second partition is connected to a receiver86on the third partition. The receiver86on the third partition is connected to a third node88in the partition. This third node is similar to or the same as the first and second nodes. The receiver86is also connected or coupled to an address converter90on the third partition. This is similar to or the same as the address convertor of the other partitions. The output of the address converter90is input to the third node and provides ID information. The address is also provided to the third node. The receiver provides the remainder of the transaction including the request, ACK, data and opcode. The third node88is connected to the USB68and the SATA66.

The address converter74of the first partition52is arranged to assign an identifier to each transaction based on the target address of the transaction. In the example shown inFIG. 3, there are three possible IDs which can be assigned to each transaction. The first ID T1is assigned to any transactions which are intended for the video decoder58. The second ID T2is assigned to any transactions which are for the GFX60. Both the video decoder58and the GFX60are in the same partition as the ID generator74. The third ID T0is assigned for any transaction which is intended for a peripheral which is not on the first partition52.

Thus, the ID is associated with the data transaction to the node. In one embodiment, the transaction including the address is modified to additionally include an ID. As mentioned previously, the address is input to the node. Based on the ID, the node72will route the transaction (including the address) to one of its three outputs. For those transactions which are intended for peripherals which are not on the first partition52, the address information is used to make sure that the transaction reaches its correct destination. The ID is used by node72to control to which output the transaction is routed. Accordingly, the ID may not be included in any of the outputs of the node72.

FIG. 4ashows the routing table used by the address generator74. As can be seen, transactions are received which specify an address. R0, R1, etc are the regions of the SoC memory map. The address for a given transaction will be in one of the regions. Each target occupies a memory region in the SoC memory map. The list of regions may be the same on all address converters. Only a subset of regions corresponds to real targets present on each partition. So for the first partition, the region R0corresponds to video decoder, R1corresponds to GFX.

R0is for the video decoder58and accordingly is assigned ID1(T1). R1is intended for the GFX60and accordingly is assigned ID2(T2). R4is for the GFX60and assigned ID2(T2). However, R2, R3, R5and RN are for peripherals which are outside the first partition and are thus given ID0(T0). Thus, the ID generator74is arranged to determine the ID on the basis of the target address included the transaction.

The address converter82on the second partition operates in the same way as the ID converter74of the first partition. Likewise, the second node operates in a similar manner to the first node. In particular, the address converter82is configured to assign ID1(T1) to all transactions which are intended for the VDP64. ID2(T2) is assigned to all transactions intended for the DMA62. ID0(T0) is assigned to all transactions which are intended for the peripherals on the first and third partition56. Thus, the second node is arranged to output the transactions including the address but without the ID to the transmitter84. Those transactions which are intended for the peripherals on the third partition are thus transmitted via the transmitter84to the receiver86. The receiver86thus provides the transactions to the node88and the addresses are provided to the ID converter92. The address converter92provides the ID1(T1) for those transactions which are required for the USB68and the ID2(T2) for those transactions which are for the SATA66.

Reference is made toFIG. 4bwhich shows the routing table for the address converter82. R0, R1, R4, R5and RN are all for the peripherals on the first and third partitions and are thus assigned ID0(T0). R2intended for the VDP64and is assigned ID1(T1). R3is for the DMA62and is assigned ID2(T2).

Finally,FIG. 4cshows the routing table of the address converter90of the third partition. As can be seen R0, R1, R2, R3, R4are for targets on the first and second partitions and R5is for the USB68and thus assigned ID1(T1). RN is for the SATA66and thus assigned ID2(T2). In summary, R0and R1are for the peripherals on the first partition, R2and R3are for the peripherals on the second partition and R4and RN are for the peripherals on the third partition.

Thus embodiments of the present invention allow easier reusability and simpler design. This may minimize the time to market and reduce the design costs. It should be appreciated that the examples shown in the figures show six peripherals. In practice, more or less than six peripherals may be provided. Further the number of peripherals on a partition can be anything from none to as many as can be physically accommodated.

In some embodiments of the invention, the simplified design of the peripheral bus may make an impact on the overall system on chip time development.

The peripheral bus provided by some embodiments is reusable in different systems on chip. Such a peripheral bus may be agnostic as compared to the physical aspect. Some embodiments allow the peripheral bus to share the same memory map across different system on chips. This is regardless as to the organization of the peripherals on the physical partitions. Embodiments of the present invention may avoid the need to respin the peripheral bus where there is physical partition reorganization. Further, embodiments of the present invention allow the simplicity of the daisy chaining peripheral bus to be maintained, at least in some embodiments.

Embodiments of the present invention allow asynchronous communication between the partitions.

In some embodiments, the nodes72,80and88may have the same structure. In some embodiments of the present invention, the nodes may have different structures and the number of outputs may differ from partition to partition.

It should be appreciated that in one embodiment, the transactions are received from a network on chip NoC or any other suitable source.

Reference is made toFIG. 5which shows a modification of the embodiment of the system on chip shown inFIG. 3. In addition to the elements shown inFIG. 3, each partition is provided with a second address to identifier converter100,102and104respectively. Each address to identifier converter is configured to receive transactions from, for example, a NoC or any other suitable source. These transactions are treated in the same way at the transactions received in the embodiment ofFIG. 3. The address is input to the address to ID converter and the respective node. The rest of the transaction is input to the respective node. The associated identifier is output by the respective address to ID converter to the node. The node will treat all the transactions it receives in the same manner as described previously.

In one modification, the peripheral bus may have an interconnect106from the third partition to the first partition. A transmitter108may be provided on the third partition which is configured to output transactions on the interconnect108which are received by a receiver110on the first partition. Thus the partitions are connected in a ring.

Each of the address to ID converters on each partition is configurable. Each table represents the system on chip memory map or a subset of the memory map related to that partition. This may be reconfigurable by for example software, an on chip table or a fixed table at the design stage.

It should be appreciated that some embodiments may use asynchronous bridges on the boundary partitions and may have a four-phase handshake based frequency converter. In some embodiments, the physical address is not decoded, it is carried up to the final target or a next address to ID converter.

Each address to ID converter may implement the system on chip memory or just the subset related to that partition. This may minimize the decoding time. Any address corresponding to a target not sitting in a given partition is remapped to a particular identifier and then transferred to the address converter of the next partition. This may minimize latency accesses. It should be appreciated that this table is distributed. In other words, a table is provided in each of the partitions. This means that there may be high scalability and frequency.

Embodiments of the present invention may provide for a compatible memory map amongst different system on chips. The peripheral bus may not be linked to any particular physical constraints. The peripheral bus may be shared amongst different system on chips. Thus, only the address to identifier converter has to be reconfigured. Embodiments of the present invention may have a regular structure in that the same building blocks are used: a node is used and the memory mapping is agnostic since embodiments use ID routing.

In embodiments of the present invention, the need to respin the peripheral bus in the case of a physical partition reorganization may be removed. Only the address to ID converter needs to be reconfigured. Again, there is no need to respin the peripheral bus in the case of memory map changes as the address to ID converter simply needs to be reconverted.

There is an asynchronous interface between the physical partitions as there is no top level timing to analyze. Further, no inter-partition clock balancing needs to be addressed.

The peripherals mentioned are by way of example and any other suitable peripherals may be used. The number of partitions may be more or less than three.

Embodiments may be used for any suitable chip. By way of example only, embodiments may be used with any suitable system on chip application domains such as TV, mobile communication and multimedia. For example some embodiments may have application to HDTV or 3DTV.