Apparatus and method for calibrating high speed serial receiver analog front end and phase detector

An apparatus is provided which comprises: an amplifier; a first slicer coupled to the amplifier; a de-serializer coupled to an output of the first slicer; a multiplexer which is operable to select one of data or a test signal for the amplifier; a filter coupled to an input of the multiplexer to provide test signal; and a frequency modulator coupled to the filter, wherein the frequency modulator is operable to modulate frequency of the test signal. An apparatus is also provided which comprises: an analog multiplexer having a first input to receive serial data, and a second input; an analog front-end (AFE) coupled to an output of the analog multiplexer; and a filter coupled to the second input of the analog multiplexer.

BACKGROUND

High speed serial receiver performance is sensitive to unit-to-unit variations in hardly observable receiver parameters such as analog frontend (AFE) transfer function and the phase detector transfer function. Accurate, automatic and quick measurements of these parameters enables performance optimization of the receiver with appropriate automatic calibration. However, performing these measurements is challenging since they are either input data dependent, which requires special test equipment, or extremely high speed signals dependent such as the phase detector response.

DETAILED DESCRIPTION

Various embodiments disclose an on-die design-for-test (DFT) circuit associated with an analog frontend (AFE) and its' associated circuits in a receiver. In some embodiments, an apparatus (e.g., the AFE, its associated circuits, and the on-die DFT circuit) is provided which comprises: an amplifier (e.g., part of the AFE); a first slicer coupled to the amplifier; and a de-serializer coupled to an output of the first slicer. In some embodiments, the apparatus further comprises a multiplexer (e.g., part of the on-die DFT) which is operable to select one of data or a test signal for the AFE amplifier. In some embodiments, the apparatus comprises a filter coupled to an input of the multiplexer to provide the test signal. In some embodiments, the apparatus comprises a frequency modulator coupled to the filter, wherein the frequency modulator is operable to modulate frequency of the test signal. In some embodiments, the amplifier is coupled to an equalizer, and wherein a combination of the amplifier and the equalizer is coupled to an input of the first slicer. In some embodiments, an output of the de-serializer is received by a pin of a chip. In some embodiments, the frequency modulator comprises a divider. In some embodiments, the filter is a harmonic filter.

In some embodiments, the apparatus comprises a phase interpolator coupled to an input of the frequency modulator, wherein an output of the phase interpolator is coupled to the first slicer. In some embodiments, the apparatus comprises a clock generator to provide a clock to an input of the phase interpolator, wherein the phase interpolator is to vary in delay one or more edges of the clock. In some embodiments, the apparatus comprises a second slicer coupled to the amplifier, wherein the clock is received by the second slicer. In some embodiments, the apparatus comprises a phase detector coupled to an output of the second slicer. In some embodiments, the apparatus comprises a low pass filter coupled to an output of the phase detector and a pin of a chip. In some embodiments, the first and second slicers comprise clock comparators. In some embodiments, the apparatus comprises a reference voltage node which is coupled to the first slicer.

The on-die DFT circuit of various embodiments is practically transparent to the normal operation of receiving and sampling incoming data, but allows for characterizing the transfer functions of the AFE and a phase detector associated with the AFE. As such, the AFE can continues to operate at high frequency allowing the on-die DFT circuit to capture the transfer functions of the AFE and the phase detector with higher accuracy and lower cost than trying to capture transfer functions of the AFE and the phase detector solely using an off-die test equipment. The measurements obtained from the on-die DFT allows for fine tuning the operation of the receiver with high confidence. In some embodiments, the characterization is performed upon a power-on event or in a test mode.

The term “scaling” generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term “scaling” generally also refers to downsizing layout and devices within the same technology node. The term “scaling” may also refer to adjusting (e.g., slowing down or speeding up—i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value.

For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

FIG. 1illustrates apparatus100operable to self-test an analog frontend (AFE) and its associated circuits, according to some embodiments of the disclosure. In some embodiments, apparatus100comprises a processor101(e.g., a system-on-chip (SOC), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable array (FPGA), a memory chip, a general purpose processor, a graphics processor, etc.) and a Test Equipment102for post processing the measurements obtained from the processor. In some embodiments, processor101comprises a receiver103, input-output (TO) pins104and105, AFE and its associated digital circuits106(also referred to as block106), clock generator107, and on-die design-for-test (DFT) circuit108.

In some embodiments, clock generator107provides a clock signal and a phase interpolated clock (together labeled as109) to AFE and digital circuits106. In some embodiments, on-die DFT circuit108provides frequency modulated test signal110to AFE of block106. In some embodiments, pins104provide access to output(s) of a phase detector (e.g., part of block106). In some embodiments, the phase detector transfer function is as accurate as a delay step of a phase interpolator (PI). As the output of the PI changes, the phase of test signal110changes. As the delay steps of the PI are adjusted, the phase detector output changes (because the phase of the test signal110changes), and this output is used to determine the transfer function of the phase detector (e.g., part of block106). By achieving an accurate transfer function of the phase detector, clock data recovery (CDR) loop parameters (e.g., filter coefficients, charge pump current, phase detector gain, etc.) can be optimized per receiver and/or per processor.

In some embodiments, pin105is used for receiving regular data (e.g., high speed serial data). In some embodiments, another pin is used to provide serial data which includes transfer function information of the AFE of block106. In some embodiments, frequency of test signal110is modulated by adjusting divider ratios of a clock divider. As the frequency of test signal110changes, the amplitude of the AFE in block106changes. This change in amplitude is digitized as an output of a de-serializer. The output of the de-serializer is then read from a pin. In some embodiments, test equipment102is any equipment that interfaces with pins104and other pins (not shown) and analyzes the DFT data and produces the desired transfer function(s).

FIG. 2illustrates apparatus200showing details of an on-die DFT circuit for characterizing a transfer function of the AFE and for characterizing a transfer function of a phase detector coupled to the AFE, according to some embodiments of the disclosure. It is pointed out that those elements ofFIG. 2having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

Apparatus200(e.g., part of a receiver) comprises multiplexer201, AFE202, roaming slicer203, data slicer204, phase detector205, de-serilizer206, signal processing logic (e.g., CDR)207, reference generator208, clock source/generator209, divider210, phase interpolator211, divider212, filter213, resistors R1and R2, and capacitors C1and C2. As indicated by the dashed lines, DFT circuit108may include multiplexer201, resistors R1and R2, capacitors C1and C2, divider212and filter213. As indicated by the dashed lines, clock generator107includes clock source/generator209, divider210, and phase interpolator211. These dashed lines are shown for describing the various embodiments, and do not limit certain logics and circuits in certain boxes or boundaries. The circuits can be rearranged in any suitable manner to perform the transfer function characterization with reference to the various embodiments.

In some embodiments, multiplexer201is an analog multiplexer. In some embodiments, the analog multiplexer is implemented using pass-gates for transmitting the signal from the input nodes of multiplexer201to an output node of multiplexer201, wherein the pass-gates are controlled by test mode signal and signals derived from the test mode signal (e.g., inverse of the test mode signal). In some embodiments, during normal mode (e.g., in non-test mode), multiplexer201selects Input data (e.g., a serial analog data) from a transmitter (not shown) and provides that Input data to AFE202. In some embodiments, AFE202comprises a high speed amplifier which converts the received analog input to a digital output with reference to a reference signal. In some embodiments, AFE202also includes a linear equalization stage coupled to an output of an amplifier. Any suitable linear equalizer can be used for implementing the linear equalization stage.

In some embodiments, output216of AFE202is provided to roaming slicer203(also referred to as the first slicer) and data slicer204(also referred to as the second slicer). In some embodiments, roaming slicer203and data slicer204are implemented as clocked comparators and/or flip-flops. In some embodiments, roaming slicer203receives a reference voltage217via a reference generator208. The output216is compared against reference voltage217by roaming slicer203to sample data216. In some embodiments, roaming slicer203receives a sampling clock215from phase interpolator211. In some embodiments, the sampling edge of sampling clock215is adjusted by phase interpolator211to sample data216near the center of its eye.

In some embodiments, the output of roaming slicer203is a digital output which is input to de-serializer206which converts the serial output of roaming slicer203into parallel output218. In some embodiments, output218is processed by a signal processing logic207. In some embodiments, output218is also received by a scan chain (or any design for test circuit) to carry that output to an external chip pin for analysis. Output219from processing logic207can then be used for any purpose.

In some embodiments, data slicer204receives clock signal214from divider210. This clock signal214samples the incoming data216and provides it to phase detector205. In some embodiments, phase detector205is a building block of a clock data recovery (CDR) circuit (e.g., part of block207) and is used to recover a clock from input data216. Any suitable high speed phase detector (or phase frequency detector) may be used for implementing phase detector205. The output of phase detector205are Up and Down signals that indicate whether the recovered clock phase and/or frequency needs to be adjusted in one direction or the other (e.g., move phase forward, pull-in phase, increase clock frequency, decrease clock frequency, etc.). Here, reference to signal names and nodes are interchangeably used. For example, the term “Up” may refer to the node Up or the signal Up according to the context of the sentence.

In some embodiments, a filter is coupled to the Up and Down nodes. In some embodiments, the filter comprises resistors R1and R2, and capacitors C1and C2. In some embodiments, resistor R1has one terminal coupled to Up and another terminal coupled to one of the pins104. In some embodiments, capacitor C1is coupled to resistor R1and ground. In some embodiments, resistor R2has one terminal coupled to Down and another terminal coupled to one of the pins104. In some embodiments, capacitor C2is coupled to resistor R2and ground.

In some embodiments, clock/source generator209receives a reference clock (Ref Clk) and generates a high frequency phase locked clock. In some embodiments, clock/source generator209is a phase locked loop (PLL). In some embodiments, the output of clock/source generator209is divided down by divider210that generates clock214for data slicer204and phase interpolator211. In some embodiments, frequency of clock214can be modulated by adjusting a divider ratio for the divider210. In some embodiments, divider210is implemented as a Johnson Counter. In other embodiments, other types of counters may be used for implementing divider210.

In some embodiments, clock214is received as input to phase interpolator211which is operable to adjust or modulate the phase of clock214. In some embodiments, phase interpolator211is implemented as a tree of delay inverters and multiplexers that receive clock214and generate clock215having a phase different from the phase of clock214. In some embodiments, phase interpolator211is operable to adjust the phase of clock214in very fine increments. In some embodiments, phase interpolator211is implemented as a current-controlled interpolator. In some embodiments, phase interpolator is a voltage-controlled interpolator. Any suitable circuit for phase interpolation can be used for interpolating the phase of clock214. In some embodiments, by adjusting the phase of clock215, the sampling edge of clock215is adjusted.

In some embodiments, clock215is received by divider212. In some embodiments, divider212generates a clock which has a slower frequency than the frequency of clock215. In some embodiments, frequency of clock215can be modulated by adjusting a divider ratio for the divider212. In some embodiments, divider212is implemented as a Johnson Counter. In other embodiments, other types of counters may be used for implementing divider212.

In some embodiments, the output of divider212is filtered by filter213. In some embodiments, filter213is a harmonic filter implemented using passive devices (e.g., resistor(s) and capacitor(s)). Any suitable arrangement of active and/or passive devices may be used for implementing filter213. In some embodiments, output217(also referred to as test signal217) of filter213is received by multiplexer201. In some embodiments, during test mode, multiplexer201selects test signal217and provides it to AFE202. In some embodiments, during test mode, reference voltage217is adjusted.

In some embodiments, to characterize AFE202(e.g., to generate a transfer function of AFE202), divider ratio of divider212is adjusted one ratio at a time and output218is monitored. In some embodiments, to characterize AFE202, phase interpolator211provides a set output and frequency of test signal217which is then modulated by adjusting frequency clock215.FIG. 3illustrates plot300showing a transfer function of AFE202obtained using the on-die DFT circuit, according to some embodiments of the disclosure. Here, x-axis is frequency (e.g., frequency of test signal217) and y-axis is the output amplitude of AFE202which is extracted from output218. Here, the various dots on the dotted line are the output amplitudes for different divider ratios of divider212. A curve can then be formed by connecting the dots to generate the transfer function.

Referring back toFIG. 2, in some embodiments, to characterize phase detector205, divider ratios of dividers210and212are fixed and phase of clock215is modulated. For example, phase interpolator211changes the phase of clock215and then signals Up and Down are monitored on pins104.FIG. 4illustrates plot400showing the transfer function of phase detector205obtained using the one-die DFT circuit, according to some embodiments of the disclosure. Here, x-axis is the delay in sampling clock215caused by phase interpolator211, and y-axis is the difference between Up and Down signals as detected on pins104.

FIG. 5illustrates flowchart500of a method for obtaining a transfer function of AFE202using the on-die DFT circuit, according to some embodiments of the disclosure. It is pointed out that those elements ofFIG. 5having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

At block501, to enter DFT mode to characterize AFE202, a test mode is selected in which a test signal is provided to AFE202instead of the regular input data. In some embodiments, test mode signal is received by multiplexer201which selects the test signal217from filter213as input of AFE202. At block502, reference generator208provides reference voltage217to roaming slicer203. In some embodiments, during test mode, reference voltage217may be adjusted for characterizing AFE202. For example, different transfer functions of AFE202can be obtained for different reference voltage217.

At block503, the frequency of the test signal217is modulated (or changed) by changing divider ratios of divider212. For each frequency change, the output of roaming slicer203changes. As such, at block504, output218of de-serializer206is stored (e.g., in memory) and then analyzed (e.g., by test equipment102). In some embodiments, the memory for storing output218resides in processor101. In some embodiments, the memory for storing output218is external to processor101. In some embodiments, the memory for storing output218resides in test equipment102.

At block505, a determination is made whether all desired frequencies changes have been made to test signal217. For example, a determination is made whether changes to all divider ratios are complete (e.g., all options or all intended options of divider ratios have been exercised). If a determination is made that more divider ratio changes need to be made to further modulate the frequency of test signal217, then the process proceeds to block503. In some examples, for each change in divider ratio, a dot on plot300is achieved.

When all desired divider ratios have been exercised, the process proceeds to block506. At block506, a transfer function of AFE202is plotted. In some embodiments, multiple transfer functions are plotted for different clock phase settings of clock215from phase interpolator211. In some embodiments, multiple transfer functions are plotted for different reference voltage levels of reference voltage217. As such, AFE202is characterized. This characterization can be used to tune various parameters (e.g., reference voltage level of reference voltage217, amplifier offset of amplifier in AFE202, sampling edge phase of clock215) associated with AFE202.

FIG. 6illustrates flowchart600of a method for obtaining a transfer function of phase detector205coupled to AFE202, according to some embodiments of the disclosure. It is pointed out that those elements ofFIG. 6having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

At block601, to enter DFT mode to characterize phase detector205, a test mode is selected in which a test signal is provided to AFE202instead of the regular input data. In some embodiments, test mode is received by multiplexer201which selects test signal217from filter213as input of AFE202. At block602, phase interpolator211receives input clock214adjusts its phase and provides the modified clock215to divider212. In some embodiments, high frequency harmonics are filtered from the output of divider212and a filtered test signal217is provided to multiplexer201.

At block603, phase detector205generates Up and Down signals according to the output of data slicer204. For each change in phase of clock215, Up and Down signals change. At block604, Up and Down signals are filtered by resistors R1and R2, and capacitors C1and C2. The filtered Up and Down signals are read at pins104. In some embodiments, test equipment102stores the data read from pins104.

At block605, a determination is made whether all desired phase shifting by phase interpolator211have been done. If more phase changes to clock215are to be made, the process proceeds to block602, otherwise the process proceeds to block606. At block606, plot400is plotted and characteristics of phase detector205are analyzed. In some embodiments, the transfer function of phase detector205can be used for tuning CDR parameters (e.g., charge pump current, loop filter capacitance, etc.). In some embodiments, a product of a gain of phase detector205(e.g., slope of plot400) and charge pump current (Icp) divided by loop filter capacitance is desired to be constant to achieve a constant response. If the gain of phase detector205is greater than expected, then that information can be used to reduce charge pump current (Icp). Likewise, if the gain of phase detector205is less than expected, then that information can be used to increase charge pump current (Icp). As such, performance of CDR207can be improved.

In some embodiments, the operations of DFT circuit (e.g., operations of characterizing AFE106) is controlled or managed by a finite state machine (FSM). In some embodiments, the flowcharts ofFIGS. 5-6are controlled by a finite state machine and/or software (e.g., operating system).

Although the blocks with reference toFIGS. 5-6are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks listed inFIGS. 5-6are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

FIG. 7illustrates a smart device or a computer system or a SoC (System-on-Chip) with on-die DFT circuit for obtaining transfer functions of the AFE and the phase detector, in accordance with some embodiments. It is pointed out that those elements ofFIG. 7having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

FIG. 7illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device2100represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device2100.

In some embodiments, computing device2100includes a first processor2110with an on-die DFT circuit for obtaining transfer functions of an AFE and a phase detector, according to some embodiments discussed. Other blocks of the computing device2100may also include an on-die DFT circuit for obtaining transfer functions of an AFE and a phase detector according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within2170such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

In one embodiment, computing device2100includes audio subsystem2120, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device2100, or connected to the computing device2100. In one embodiment, a user interacts with the computing device2100by providing audio commands that are received and processed by processor2110.

Display subsystem2130represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device2100. Display subsystem2130includes display interface2132, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface2132includes logic separate from processor2110to perform at least some processing related to the display. In one embodiment, display subsystem2130includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller2140represents hardware devices and software components related to interaction with a user. I/O controller2140is operable to manage hardware that is part of audio subsystem2120and/or display subsystem2130. Additionally, I/O controller2140illustrates a connection point for additional devices that connect to computing device2100through which a user might interact with the system. For example, devices that can be attached to the computing device2100might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller2140can interact with audio subsystem2120and/or display subsystem2130. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device2100. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem2130includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller2140. There can also be additional buttons or switches on the computing device2100to provide I/O functions managed by I/O controller2140.

Connectivity2170includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device2100to communicate with external devices. The computing device2100could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Connectivity2170can include multiple different types of connectivity. To generalize, the computing device2100is illustrated with cellular connectivity2172and wireless connectivity2174. Cellular connectivity2172refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface)2174refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

Peripheral connections2180include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device2100could both be a peripheral device (“to”2182) to other computing devices, as well as have peripheral devices (“from”2184) connected to it. The computing device2100commonly has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device2100. Additionally, a docking connector can allow computing device2100to connect to certain peripherals that allow the computing device2100to control content output, for example, to audiovisual or other systems.

For example, an apparatus is provided which comprises: an amplifier; a first slicer coupled to the amplifier; a de-serializer coupled to an output of the first slicer; a multiplexer which is operable to select one of data or a test signal for the amplifier; a filter coupled to an input of the multiplexer to provide the test signal; and a frequency modulator coupled to the filter, wherein the frequency modulator is operable to modulate frequency of the test signal. In some embodiments, the amplifier is coupled to an equalizer, and wherein a combination of the amplifier and the equalizer is coupled to an input of the first slicer. In some embodiments, an output of the de-serializer is received by a pin of a chip. In some embodiments, the frequency modulator comprises a divider. In some embodiments, the filter is a harmonic filter.

In some embodiments, the apparatus comprises: a phase interpolator coupled to an input of the frequency modulator, wherein an output of the phase interpolator is coupled to the first slicer. In some embodiments, the apparatus comprises a clock generator to provide a clock to an input of the phase interpolator, wherein the phase interpolator is to vary in delay one or more edges of the clock. In some embodiments, the apparatus comprises a second slicer coupled to the amplifier, wherein the clock is received by the second slicer. In some embodiments, the apparatus comprises a phase detector coupled to an output of the second slicer. In some embodiments, the apparatus comprises a low pass filter coupled to an output of the phase detector and a pin of a chip. In some embodiments, the first and second slicers comprise clock comparators. In some embodiments, the apparatus comprises a reference voltage node which is coupled to the first slicer.

In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor having a receiver which comprises an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to communicate with another device.

In another example, an apparatus is provided which comprises: an analog multiplexer having a first input to receive serial data, and a second input to receive a test signal; an analog front-end (AFE) coupled to an output of the analog multiplexer; and a filter coupled to the second input of the analog multiplexer, wherein the filter is to filter harmonics in the test signal. In some embodiments, the apparatus comprises a frequency modulator coupled to the filter, wherein the frequency modulator is to modulate a frequency of the test signal. In some embodiments, the apparatus comprises a phase interpolator coupled to an input of the frequency modulator.

In some embodiments, the apparatus comprises: a clock generator to provide a clock to the phase interpolator, wherein the phase interpolator is to vary in delay one or more edges of the clock. In some embodiments, the apparatus comprises: a first slicer including a clock node coupled to an output of the phase interpolator, a data node coupled to an output of the AFE, a reference node to receive a reference voltage; and an output; and a de-serializer coupled to the output of the first slicer. In some embodiments, the apparatus comprises: a second slicer including a data node coupled to an output of the AFE, and a clock node to receive the clock; a phase detector coupled to an output of the second slicer; and a low pass filter coupled to an output of the phase detector, wherein an output of the low pass filter is coupled to at least one pin of a chip.

In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor having a receiver which comprises an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to communicate with another device. In some embodiments, an output of the de-serializer is received by a pin of a chip.

In another example, a method for characterizing a transfer function is provided, wherein the method comprises: selecting a test mode to provide a test signal to an analog frontend (AFE); providing a reference voltage to a slicer coupled to the AFE; modulating frequency of the test signal by changing divider ratios; and for every change in divider ratio, store an output of a de-serializer coupled to the slicer. In some embodiments, the method comprises: providing a clock to the slicer. In some embodiments, the method comprises: filtering the test signal in response to changing the divider ratio.

In another example, a method is provided which comprises: selecting a test mode to provide a test signal to an analog frontend (AFE); modifying phase of a clock signal provided to a slicer coupled to the AFE; generating up and down signals according to an output of the slicer; and filtering the up and down signals. In some embodiments, the method comprises: dividing a frequency of the clock signal to generate of modulated clock signal; filtering the modulated clock signal and providing the filtered modulated clock signal as the test signal.

In another example, an apparatus is provided which comprises: means for means for selecting a test mode to provide a test signal to an analog frontend (AFE); means for means for providing a reference voltage to a slicer coupled to the AFE; means for modulating frequency of the test signal by changing divider ratios; and for every change in divider ratio, means for storing an output of a de-serializer coupled to the slicer. In some embodiments, the apparatus comprises means for providing a clock to the slicer. In some embodiments, the apparatus comprises means for filtering the test signal in response to changing the divider ratio.

In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor having a receiver which comprises an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to communicate with another device.

In another example, an apparatus is provided which comprises: means for selecting a test mode to provide a test signal to an analog frontend (AFE); means for modifying phase of a clock signal provided to a slicer coupled to the AFE; means for generating up and down signals according to an output of the slicer; and means for filtering the up and down signals. In some embodiments, the apparatus comprises: means for dividing a frequency of the clock signal to generate of modulated clock signal; and means for filtering the modulated clock signal and means for providing the filtered modulated clock signal as the test signal.

In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor having a receiver which comprises an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to communicate with another device.