High current capable access device for three-dimensional solid-state memory

The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention generally relate to three-dimensional solid-state memory and a method for addressing memory cells in a three-dimensional arrangement.

2. Description of the Related Art

Phase change memory (PCM) is a type of non-volatile memory technology. PCM is an emerging technology and a candidate for storage class memory (SCM) applications and a serious contender to dislodge NOR and NAND flash memory in solid state storage applications and, in the case of NAND flash, solid-state drives (SSDs). PCM functions based upon switching a memory cell, typically based on chalcogenides such as Ge2Sb2Te5, between two stable states, a crystalline state and an amorphous state, by heating the memory cell. To heat the memory cell, an electrical current flows through the PCM cell. For an effective memory device, numerous PCM cells will be present in an array. Each of the PCM cells needs to be addressed, programmed and read with low overhead electrical wiring. The PCM cell is the phase-change cell itself, and PCM device, as discussed herein, is the set of PCM cells plus accompanying heaters (represented by a resistor in the electrical diagrams). The PCM device is the memory element herein.

An array100of PCM cells is frequently arranged with a selecting transistor102in series with each memory cell104as shown inFIG. 1A. Word lines (WL) and bitlines (BL) are arranged so that each memory cell104can be programmed or queried. A row of PCM cells is activated by a single word line WL and each one of the PCM cells104in that row will affect the bitline BL to which it is electrically connected according to the state of the PCM cells104, i.e. according to the PCM cells104being in their high (amorphous) or low (crystalline) resistance state. As shown inFIG. 1A, a simple array100of PCM devices106is shown. The array100is a two dimensional array because the PCM devices106are all arranged along a common plane.

In an alternative design commonly named “cross-point”, shown inFIG. 1B. Each interception of word lines WL in the x direction and bit lines BL in the y direction has a PCM device106, which includes the PCM cell104itself and its heater (represented by a resistor). Frequently, a selecting device is added in series with the PCM device. This selecting device can be a diode or a transistor. The selecting device, diode or transistor, added to the cross-point array110, or alternatively, used externally to the array of PCM cells may frequently become the limiting factor on how dense can the PCM array become.

When the selecting device is added to the cross-point array, there will be one selecting device per PCM device106. Current requirements of the PCM device106need to be met by the selecting device. In consequence, even when the PCM device106can be made small to the lithographic limit and occupy only 4F2of area, where F is the half-pitch critical dimension in a lithographic technology, the selecting device might require 30F2if it is a CMOS transistor or 10F2if it is a bipolar transistor. Optimized diodes, where efforts to make them very conductive might attend the current requirement of a PCM device using 4F2area and are therefore very frequently considered as selecting device in cross point memories using PCM or any memory device requiring significant currents for operation.

Unfortunately, using diodes makes it very difficult to extend the concept of cross-point array110from a two-dimensional (2D) array to a three-dimensional (3D) array. In a 3D array, addressing the PCM devices106that are in the middle of the array is difficult.

Therefore, there is a need for a PCM device that permits each PCM cell to be accessed individually while minimizing the use of the surface area of the substrate over which the PCM device is disposed as well as minimizing the overhead wiring utilized to address PCM cells in the middle of the PCM 3D array.

SUMMARY OF THE INVENTION

The present invention generally relates to three-dimensional solid state memory cells and arrangements thereof. Examples of suitable three-dimensional solid state memory cells include PCM. In one embodiment, a three-dimensional solid state memory cell comprises a three-terminal device; a first electrical connector coupled to the three-terminal device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis; a second electrical connector coupled to the three-terminal device; a memory cell coupled to second electrical connector, the memory cell disposed along the second axis; and a third electrical connector coupled to the memory cell, the third electrical connector extending along the second axis and along a third axis perpendicular to both the second axis and the first axis.

In another embodiment, a method of addressing a memory cell in a three-dimensional solid state memory cell is disclosed. The memory cell comprises a three-terminal device; a first electrical connector coupled to the three-terminal device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis; a second electrical connector coupled to the three-terminal device; a memory cell coupled to second electrical connector, the memory cell disposed along the second axis; and a third electrical connector coupled to the memory cell, the third electrical connector extending along the second axis and a third axis perpendicular to both the second axis and the first axis. The method comprises applying an electrical current to the first electrical connector; applying an electrical current to the third electrical connector; and applying an electrical current to the three-terminal device.

In another embodiment, a method of addressing a memory cell in a three-dimensional solid state memory cell is disclosed. The memory cell comprises a plurality of macro cells that each comprise a three-terminal device; a first electrical connector coupled to the three-terminal device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis; a second electrical connector coupled to the three-terminal device; a memory cell coupled to second electrical connector, the memory cell disposed along the second axis; and a third electrical connector coupled to the memory cell, the third electrical connector extending along the second axis and a third axis perpendicular to both the second axis and the first axis. The method comprises applying a first electrical current to the first electrical connectors of a first plurality of macro cells; applying a second electrical current to the second electrical connectors of a second plurality of macro cells; and applying a third electrical current to the three-terminal devices of a third plurality of macro cells, wherein the first electrical current, the second electrical current and the third electrical current are collectively applied to a single macro cell.

DETAILED DESCRIPTION

The present invention generally relates to a PCM cell and arrangements thereof. The PCM cell is used as illustrative purposes only. It is contemplated that other memory cells like tunnel magneto-resistive (TMR) cells, or other memory cell element where information is stored by its change of resistance, could be used without departing from the spirit of the invention. In the case of spin-transfer torque TMR, current for the switching of the cell needs to be applied in two directions, and such a requirement will also be attended by the invention in this patent application. A PCM-based building block as used herein is comprised of numerous macro cells.FIG. 2is an isometric illustration of a macro cell200according to one embodiment. The macro cell200includes an electrically insulating spacer202at the bottom of the macro cell200in order to electrically insulate the macro cell200from underlying conductive material, such as transistors or adjacent macro cells. Suitable materials that may be utilized for the electrically insulating spacer202include silicon dioxide, silicon nitride, and silicon oxynitride.

The macro cell200also includes a selecting three-terminal device208, which could be a MESFET. As will be discussed below, the three-terminal selecting device208will have its gate electrode if it is a MESFET coupled to a control device external to the three-dimensional array to deliver electrical voltage or current to the gate electrode of that three-terminal device208. The three-terminal device208is electrically coupled to a first electrical connector206. The first electrical connector extends along a first axis216as well as a second axis218that is perpendicular to the first axis216. As shown inFIG. 2, the three-terminal device208is coupled to the first electrical connector206along the second axis218. It should additionally be noted that the gate of the three-terminal device208extends along another axis222that is perpendicular to both the first axis216and the second axis218. The portion of the first electrical connector206that extends along the first axis216is utilized to provide electrical current to the source of the three-terminal device208.

Those skilled in the art will recognize that a MESFET can be a completely symmetric device and its source and drain terminals be defined only after voltage levels are applied. In such, a MESFET will support current flow in two directions through the memory cell element.

The macro cell200also includes a memory cell212that is disposed along the second axis218and electrically coupled to the three-terminal device208by a second electrical connector210. The second electrical connector210is coupled to both the drain of the three-terminal device208, if the three-terminal device208is a MESFET, as well as the memory element. The memory cell212is also coupled to a third electrical connector214. The third electrical connector214extends both along the second axis218and along a third axis220that is perpendicular to both the first axis216and the second axis218. Another electrically insulating spacer204is coupled to the third electrical connector214to electrically insulate the macro cell200from adjacent macro cells.

To address the macro cell200, electrical voltage or current is applied to three distinct locations of the macro cell200. First, electrical voltage or current is applied to the first electrical connector206. Second, electrical voltage or current is applied to the gate of the three-terminal device208if the three-terminal device208is a MESFET. Third, electrical voltage or current is applied to the third electrical connector214. When all three voltage or currents are applied to the same macro cell200, then the macro cell200is addressed such that data may be written or read from the memory cell212. Memory cell212in this illustrative description represents the PCM cell and its heater, but other memory cell elements could be used such as magnetoresitive memory elements, or other variable resistance elements as well.

FIG. 3is an isometric view of a PCM-based building block array300having two macro cells200A,200B arranged side by side. As can be seen fromFIG. 3, each macro cell200A,200B contains electrically insulating spacers202,204, first electrical connectors206, selecting three-terminal device208, second electrical connectors210, memory cells212, and third electrical connectors214. However, while the first electrical connector206of one of the macro cells200A extends along both the first axis216and the second axis218, the first electrical connector206of the other macro cell200B extends along the first axis216and another axis302that is parallel to the second axis218and perpendicular to the first axis216. Additionally, the third electrical connector218of one macro cell200B extends along an axis304that is parallel to the third axis220. Finally, the selecting three-terminal device208of one macro cell200B extends along an axis306that is parallel to the axis222that the three-terminal device208of the other macro cell200A extends along.

In addition to extending along the first axis216, the first electrical connectors206of both macro cells200A,200B are electrically connected together. Thus, when electrical current is applied to the first electrical connector206of one macro cell200A, electrical current is also applied to the first electrical connector206of the other macro cell200B. Additionally, when electrical current is applied to the first electrical connectors206, electrical current is also applied to the source of the three-terminal devices208of both macro cells200A,200B.

FIG. 4is a schematic isometric view of a PCM-based memory building block array400having a plurality of macro cells200A-200D arranged side by side. Macro cells200A,200B are as discussed above with regards toFIG. 3, but two additional macro cells200C,200D have been added. Similar to macro cells200A,200B, macro cells200C,200D each have electrically insulating spacers202,204, first electrical connectors206, three-terminal devices208, second electrical connectors210, memory cells212, and third electrical connectors214. However, the first electrical connectors206for macro cells200C,200D are along a different axis402as compared to the first axis216upon which the first electrical connectors206for macro cells200A,200B extend. Additionally, the first electrical connectors206for both macro cell200C and200D extend along axis404,406that are parallel to axis218,302.

The third electrical connectors214for macro cells200A,200D extend along a common axis220and are electrically connected together. The third electrical connectors214for macro cells200B,200C extend along a common axis304and are electrically connected together. However, the third electrical connectors214for macro cells200A,200D are not electrically connected to the third electrical connectors214for macro cells200B,200C. Additionally, the three-terminal devices208for macro cells200A,200D extend along a common axis, axis222and are electrically connected together. The three-terminal devices208for macro cells200B,200C extend along a common axis306and are electrically connected together. However, the three-terminal devices208for macro cells200A,200D are not electrically connected to the three-terminal devices208for macro cells200B,200C.

A PCM-based building block can be arranged in more than one plane so that a 3D PCM memory array is fabricated.FIG. 5is a schematic isometric view of a 3D PCM-based memory array500having a plurality of macro cells200A-200H. The array500shows the macro cells200A-200D rotated counterclockwise 90 degrees from the view shown inFIG. 4. Four additional macro cells200E-200H are shown, but the macro cells200E-200H are disposed over the macro cells200A-200D and are electrically isolated from macro cells200A-200D by electrically insulating spacers204. It is contemplated that additional macro cells could be formed above macro cells200E-200H and would be electrically isolated by electrically insulating spacers502.

As shown inFIG. 5, the first electrical connectors206for macro cells200E,200F extend along an axis508that is parallel to axis216. Additionally, the first electrical connectors206for macro cells200E,200F are electrically coupled to the first electrical connectors206for macro cells200A,200B by element512. It is to be understood that element512comprises electrically conductive material such as wiring that connects the first electrical connectors206to transistors in the substrate. The first electrical connector206for macro cell200E extends along axis218, and the first electrical connector206for macro cell200F extends along axis302.

As also shown inFIG. 5, the first electrical connectors206for macro cells200G,200H extend along an axis510that is parallel to axis402. Additionally, the first electrical connectors206for macro cells200G,200H are electrically coupled to the first electrical connectors206for macro cells200C,200D by element514. It is to be understood that element514comprises electrically conductive material such as wiring that connects the first electrical connectors206to transistors in the substrate. The first electrical connector206for macro cell200G extends along axis404, and the first electrical connector206for macro cell200H extends along axis406.

As also shown inFIG. 5, the third electrical connectors214for macro cells200F,200G extend along an axis506that is parallel to axis304. Additionally, the third electrical connectors214for macro cells200F,200G are electrically coupled to the third electrical connectors214for macro cells200B,200C by element516. It is to be understood that element516comprises electrically conductive material such as wiring that connects the third electrical connectors214to transistors in the substrate. The third electrical connector214for macro cell200F extends along axis302, and the third electrical connector214for macro cell200G extends along axis404.

It is to be understood that the third electrical connectors214for macro cells200E,200H extend along an axis that is parallel to axis220. Additionally, the third electrical connectors214for macro cells200E,200H are electrically coupled to the third electrical connectors214for macro cells200A,200D by element518. Element518comprises electrically conductive material such as wiring that connects the third electrical connectors214to transistors in the substrate. The third electrical connector214for macro cell200E extends along axis218, and the third electrical connector206for macro cell200H extends along axis406.

The three-terminal devices208of macro cells200F,200G extend along a common axis504that is parallel to axis306and are electrically coupled together. Similarly, MESFETs208of macro cells200E,200H extend along a common axis that is parallel to axis222and are electrically coupled together.

FIGS. 6A-6Dare schematic isometric illustrations of a 3D PCM-based array600according to one embodiment. In the embodiment shown, the PCM array600includes four separate levels of macro cells with a total of sixty-four macro cells per level. Within each level, there are eight rows602that extend in a first direction and eight rows604that extend in a second direction perpendicular to the first direction. Each of the rows602is coupled to a corresponding element that comprises electrically conductive material, such as wiring, to connect the third electrical connectors214to transistors in the substrate. While only two elements516,518have been shown, it is to be understood that each row602has a corresponding element for electrical connection and that each element is connected to each third electrical connector214within the entire row602. Thus, eight elements would be present for the embodiment shown inFIGS. 6A-6D, but for clarity, only elements516,518have been shown. Additionally, it is understood that the third electrical connectors214within a common row602in one level are electrically connected to the third electrical connectors214within the same row that are on a different level. Similarly, each of the rows604is coupled to a corresponding element that comprises electrically conductive material, such as wiring, to connect the first electrical connectors206to transistors in the substrate. While only two elements512,514have been shown, it is to be understood that each row604has a corresponding element for electrical connection and that each element is connected to each first electrical connector206within the entire row604. Thus, eight elements would be present for the embodiment shown inFIGS. 6A-6D, but for clarity, only elements512,514have been shown. Additionally, it is understood that the first electrical connectors206within a common row604in one level re electrically connected to the first electrical connectors206within the same row that are on a different level.

For the three-terminal devices208, all of the three-terminal devices208within a common level are electrically coupled together as shown inFIGS. 6C and 6D. All of the three-terminal devices208within a given level electrically couple together with electrical connectors606A-606D, such as wiring, that spans across the level and then down to the substrate to provide electrical connection to a transistor. In the embodiment shown inFIGS. 6A-6D, there are four levels and hence, only four electrical connections to the transistors on the substrate for the three-terminal devices208. By selecting one row602, one row604and one electrical connector606A-606D, a single macro cell200can be addressed.

For the embodiment shown inFIGS. 6A-6D, the PCM array600is an 8×8×4 3D arrangement of macro cells, but it is contemplated that any electrically programmable/readable memory cell, as opposed to a PCM cell, may be arranged in such a manner. Each macro cell200is addressed by the interception of three planes. Therefore, the overhead wiring is minimal. For the footprint over the substrate, an additional 2FNx area (for the x-direction planes), 2FNy area (for the y-direction planes) and 4FNz area (for the z-direction planes), where F is the half pitch critical dimension for the lithography used, Nx, Ny and Nz are the number of cells in the x, y, and z dimensions, is all that is required for addressing any cell in the full 3D structure. Therefore, the number of memory cells grows with NxNyNz (i.e., N3) whereas the footprint overhead for addressability is a linear function of Nx, Ny and Nz.

For the embodiment shown inFIGS. 6A-6D, a total of 256 macro cells200are present, yet only 20 transistors are necessary on the substrate to address each macro cell200individually. Rather than providing three separate electrical connections to each macro cell, which would necessitate 768 transistors, the macro cells200can share transistors, yet be uniquely addressed. Because only 20 transistors are necessary on the substrate, the PCM array600utilizes a very small amount of substrate area outside of the footprint of the PCM array600. Additionally, no overhead wiring is necessary to address the macro cells200in the middle of the PCM array600. One can easily imagine that if 768 transistors were utilized, electrically connecting the 768 transistors to the macro cells200would be quite complex. Even if the macro cells200were stacked in a 3D arrangement, electrically connecting 768 transistors to the PCM array600would be much more complex than connecting 20 transistors external to the 3D memory cell array. Thus, the 3D PCM array arrangement disclosed herein provides a much less complex wiring strategy, utilizes fewer transistors, and has a smaller footprint over the substrate.

The PCM arrays disclosed herein are scalable 3D arrangements. It is to be understood that the description herein is not limited to PCMs, but rather is applicable to any memory with memory cell elements queried by current and it uses a small footprint even in the case where a high current 3D access (i.e., selecting) device capability is a requirement. The embodiments disclosed herein are scalable, yet have a low footprint overhead with regards to the 3D architectural arrangement of the cells. The wiring that is over the entire cell is minimal to query a macro cell in the middle of the 3D cell and thus diminishes the overhead contribution to the footprint of the device.

FIGS. 7A-7Care schematic illustrations of a MESFET three-terminal device208according to one embodiment.FIG. 7Bis a cross-sectional view taken along line A-A fromFIG. 7A, andFIG. 7Cis a cross-sectional view taken along line B-B fromFIG. 7A. The MESFET includes a surrounding gate electrode702and a channel704. The surrounding gate electrode702comprises a noble metal such as the noble metals that make schottky junctions with the channel704. The channel704comprises polysilicon. A source electrode708is shown as is a drain electrode706. The source electrode708is simply the first electrical connector206while the drain electrode706is the second electrical connector210from the macro cell200. The electric current flows from source708to drain706of the MESFET as a function of the voltage or current applied to the gate electrode702. Depending on the three-terminal device being designed as enhancement or depletion operation, a zero voltage applied to the gate electrode relative to source will allow current flow from source to drain. In the case of an enhancement MESFET, its necessary gate voltages differ from zero voltage to allow current flow from source to drain. A depletion mode MESFET will allow current to flow from source to drain with a zero voltage from gate to source, while current flow is blocked by changing the gate voltage to some other finite value. The current then flows from the drain electrode706to the memory cell212. Because the MESFET208is a surround gate MESFET, the surrounding gate electrode702can be arrayed across a plurality of macro cells200as shown inFIGS. 6A-6Dand permit control of the ‘on’ or ‘off’ of the MESFET from a single external contact. The channel704comprises polysilicon and can be either n-type or p-type. Because the channel704is doped, the channel704will be more conductive than diode devices of comparable cross section area. Polysilicon is also chosen as the channel704because of the limited thermal budget requirements in back-end processing for PCM cells over a substrate prefabricated with standard CMOS transistors. Polysilicon is advantageous over other alternatives because polysilicon is fully compatible with standard CMOS fabrication processes and can take advantage of volume production of already established CMOS fabs.

A method for addressing a PCM cell will now be discussed with reference to the Figures. Initially, a particular macro cell200is chosen. Then, current is applied to a plurality of first electrical connectors206, a plurality of third electrical connectors214and a plurality of gate electrodes702of a plurality of MESFETs208. A total of three transistors are utilized to apply the electrical currents, yet numerous macro cells200receive the electrical current. However, only one macro cell200receives all three currents. The current applied to the plurality of first electrical connectors206is applied to a plurality of first electrical connectors206that lie in a common plane and are all electrically coupled together. The current applied to the plurality of first electrical connectors206may be thought of as the “X” coordinate in an “X-Y-Z” 3D orientation.

The current applied to the plurality of third electrical connectors214is applied to a plurality of third electrical connectors214that lie in a common plane and are all electrically coupled together. The third electrical connectors214to which the current is applied lie in a plane that is perpendicular to the plane in which the first electrical connectors that have current applied thereto lie. The current applied to the third electrical connectors214may be thought of as the “Y” coordinate in an “X-Y-Z” 3D orientation.

In a 3D structure, identifying only two coordinates does not result in a single location, but, rather, multiple locations within the “Z” plane. Thus, the “Z” coordinate is necessary. Similarly, to address a single macro cell200, the third current is applied to the gate electrode702of a plurality of MESFETs208. The current applied to the gate electrodes702of the plurality of MESFETs208may be thought of as the “Z” coordinate in an “X-Y-Z” 3D orientation. The plurality of MESFETS208that have current applied thereto lie in a common plane which is perpendicular to each of the planes to which the first and third electrical connector206,214having electrical current applied thereto lie. The three currents, while applied to multiple first electrical connectors206, multiple third electrical connectors214, and multiple MESFETs208are collectively applied to only one specific macro cell200.

The PCM cells disclosed herein are scalable 3D arrangements. It is to be understood that the description herein is not limited to PCMs, but rather is applicable to any memory with memory cell elements queried by current. It uses small footprint even in the case where high current 3D access (i.e., selecting) device capability is a requirement. The embodiments disclosed herein are scalable, yet have a low footprint overhead with regards to the 3D architectural arrangement of the cells. The wiring that is over the entire cell is minimal to query a macro cell in the middle of the 3D cell and thus diminishes the overhead contribution to the footprint of the device. The 3D design, and the use of a surround gate MESFET, permits a single macro cell to be addressed while applying voltage to multiple macro cells.