Circuit and method for generating clock signals for clocking digital signal processor and memory

A circuit is provided for generating clock signals for clocking a digital signal processor (DSP) and a memory, the circuit comprising of a clock generator for receiving a first clock, generating a DSP clock signal by dividing the first clock by X, and generating a memory clock signal based on the first clock and the DSP clock signal, wherein the DSP is clocked by the DSP clock to generate a write command for writing data into the memory and to generate a read command for reading data in the memory, and data is written into the memory or read from the memory in response to the memory clock signal. A method is also provided for accessing a memory, the method comprising of receiving a first clock; generating a DSP clock signal by dividing by X the first clock; generating a memory clock signal according to the first clock and the DSP clock signal; outputting DSP data in response to the DSP clock signal; and reading data from a memory or writing the DSP data into the memory in response to the memory clock signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No. 2004-62056, filed on Aug. 6, 2004, in the Korean Intellectual Property Office.

1. Technical Field

The present invention relates to a circuit and method for generating clock signals for clocking a digital signal processor and a memory.

2. Discussion of the Related Art

A mobile system on chip (SOC) generally includes a digital signal processor (DSP) sub-system and a micro-controlling unit (MCU). The DSP sub-system executes a processing related operation and requires a memory having high capacity.

With demand for ever increasing speed of operation on the part of the DSP and increased memory capacity, timing control for reading and writing between the DSP and the memory become increasingly complex. Since write operation for writing data into the memory from the DSP and read operation for reading data from the memory by the DSP should be done within one clock cycle, the timing margin for memory access becomes smaller.

FIG. 1is a block diagram of a conventional system for receiving and transmitting data between a DSP and a memory for a wireless communication device.FIGS. 2 and 3are timing diagrams of a conventional system for receiving and transmitting data between the DSP and the memory.

Referring toFIGS. 1,2, and3, the system100for receiving and transmitting data includes a DSP110and a memory120.

The DSP110sends a write command DWR to the memory120for writing data. According to the write command DWR, the DSP sends a memory address ADDR and data WDATA to the memory120between a rising edge and the next rising edge of a DSP clock DSPCLK, then, the data WDATA is written into the memory120.

The DSP110sends a read command DRD to the memory120for reading data from the memory120. According to the read command DRD, the DSP110reads data RDATA from the memory120between one rising edge and the next rising edge of a DSP clock DSPCLK.

As shown inFIGS. 2 and 3, a read operation or a write operation is performed in the memory120when a memory clock transitions, e.g., from low to high, after receiving a read command DRD or a write command DWR, respectively. Buffers or delays (not shown) are typically included in the system100for use in latching or buffering the data so that the read/write operation is done within timing margins such as a write command margin T_WR, a read command margin T_RD, an address margin T_AD, and a data transfer margin T_DD. The skewing of clocks to avoid timing violations is referred to as “timing closure”.

Since a read operation or a write operation is to be performed within one cycle of the DSP clock DSPCLK, all of the above timing margins cannot be adjusted at the same time. For example, if a read command margin T_RD is increased, an address margin T_AD is reduced. If an address margin T_AD is increased, a data transfer margin T_DD is reduced. As respective timing margins are related to each other, it is often a difficult task to optimize all the timing margins.

SUMMARY OF THE INVENTION

A circuit for generating clock signals for clocking a digital signal processor (DSP) and a memory is provided, the circuit comprising of a clock generator for receiving a first clock, generating a DSP clock signal by dividing the first clock by X, and generating a memory clock signal based on the first clock and the DSP clock signal, wherein the DSP is clocked by the DSP clock to generate a write command for writing data into the memory and to generate a read command for reading data in the memory, and data is written into the memory or read from the memory in response to the memory clock signal.

The clock generator generates a clock-gating input signal by dividing the first clock by X and the memory clock signal is generated according to the first clock, a DSP clock signal, and the clock-gating input signal.

Preferably, the memory clock signal is generated during one of an enabling period of the write command and the enabling period of the read command. The generator of the memory clock signal is in the form of a strobe. The pulse width of the generated memory clock signal is about ½ cycle of a cycle of the first clock. The memory is a synchronous memory.

According to another aspect of the invention, a clock generator includes a counter for counting a first clock; a clock divider for generating a digital signal processor (DSP) clock signal and a clock gating input signal according to a count value output at the counter; and a clock gating circuit for generating a memory clock signal for clocking a memory according to the DSP clock signal, the clock gating input signal, a read command, and a write command.

A clock generating method is also provided, comprising of counting a first clock; dividing a digital signal processor (DSP) clock signal and a clock gating input signal according to a count value of the first clock; and generating a memory clock signal according to the DSP clock signal, the clock gating input signal, a read command, and a write command.

A method is also provided for accessing a memory, the method comprising of receiving a first clock; generating a DSP clock signal by dividing by X the first clock; generating a memory clock signal according to the first clock and the DSP clock signal; outputting DSP data in response to the DSP clock signal; and reading data from a memory or writing the DSP data into the memory in response to the memory clock signal.

According to still another aspect of the invention, a modem is provided, comprising a clock divider for generating a DSP clock signal and a clock gating input signal by dividing a first clock by X, X is a natural number equal to or greater than 2, and for generating a memory clock signal according to the first clock, the DSP clock signal, and the clock gating input signal, wherein the memory clock signal has an active period of about ½ cycle of the first clock; and a digital signal processor (DSP) for outputting DSP data in response to the DSP clock signal and for generating a write command for writing the DSP data into a memory and a read command for reading data from the memory, wherein the writing of the DSP data into the memory or the reading of the data from the memory is in response to the memory clock signal.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 4is a schematic block diagram of a system for receiving and transmitting data between a processor and a memory according to an embodiment of the present invention. This system can be applicable for use in a number of DSP-based devices, for example, as a modem chip for a wireless communication device. It is appreciated that the present disclosure is not limited to a modem chip, rather it can be applied to other systems having a memory and a processor.

Referring toFIG. 4, the system400includes: a processor410for processing data and generating commands such as a write command DWR and a read command DRD; a memory420for storing data or the processed data in the processor410; and a circuit for generating clock signals for clocking the processor410and the memory420. Preferably, the processor410is a digital signal processor (DSP). Hereinafter, the processor410is referred to as a DSP.

According to an embodiment of the present invention, the circuit includes a clock generator430for receiving a first clock FCLK, generating a DSP clock signal DSPCLK by dividing the first clock FCLK by X (wherein X is a natural number), and generating a memory clock signal MEMCLK based on the first clock FCLK and the DSP clock signal DSPCLK. The DSP410is clocked by the DSP clock DSPCLK to generate a write command DWR for writing data into the memory420and to generate a read command DRD for reading data in the memory420, and data is written into the memory420or read from the memory420in response to the memory clock signal MEMCLK.

According to an embodiment of the present invention, the memory420is preferably a synchronous memory.

The clock generator430receives the first clock FCLK which is generated by a phase locked loop (PLL) after receiving an external clock signal EXTCLK. The frequency of the external clock signal EXTCLK is, for example, about 810 MHz and the frequency of the first clock FCLK is, for example, about 273 MHz. According to this exemplary embodiment, the clock generator430divides the first clock FCLK by three (3). Thus, X is 3 for the present embodiment, but it is appreciated that X can be any natural number.

FIG. 5is a schematic block diagram of the clock generator430inFIG. 4.

Referring toFIG. 5, the clock generator430includes: a counter510for counting a first clock FCLK and outputting a count value at output L; a clock divider520for generating the DSP clock signal DSPCLK and a clock gating input signal; and a clock gating circuit530for generating the memory clock signal MEMCLK, which is used for clocking the memory420.

According to an embodiment of the present invention, the clock divider520includes a first comparator522for comparing between a count value of the first clock output at the counter510and a first given value M and a second comparator524for comparing a count value of the first clock output at the counter510and a second given value N. The DSP clock signal DSPCLK is generated by the first comparator522and the clock gating input signal is generated by the second comparator524.

According to an embodiment of the present invention, the clock generator430can further include a register block540for storing the read command DRD and the write command DWR and outputting the read command DRD and the write command DWR in response to the first clock FCLK. The register block540includes a first register542and a second register544for storing the read command DRD and the write command DWR, respectively. According to this exemplary embodiment, the first and second registers542,544can be flip-flops.

The first clock FCLK is connected to the counter510, the clock gating circuit530, and the register block540for clocking each of the connected components.

FIG. 6is a schematic block diagram of a given value generator600for generating the first given value M and the second given value N inFIG. 5.

Referring toFIG. 6, the given value generator600includes a first selector610and a second selector620which are, for example, composed of multiplexers. The first selector610and the second selector620select the first given value M and the second given value N, respectively, in response to a selection signal. The first value M is preferably a number different from the second value N. For example M=1, N=2. In such case, the selection signal applied to610selects ‘1’ and the selection signal applied to second selector620selects ‘2’. According to this exemplary embodiment, the first clock FCLK is divided by a count of 3. In such case, the first and second selectors610,620can select from a count of 1 to 3. It is appreciated that if the first clock FCLK is to be divided by a number X, the first and second selectors610,620are X-to-one multiplexer and 1 to X can be selected. For example, if X=4, a 4 to 1 multiplexer is used and 1 to 4 can be selected.

Referring toFIG. 7, the clock gating circuit530includes AND logic gates732,734which receive at least the DSP clock signal DSPCLK, the clock gating input signal, respectively, and an OR logic gate736connected to outputs of the AND gates732,734.

The AND logic gates732,734include at least two AND logic gates. The first AND logic gate732receives the read command DRD from the first register542, the DSP clock signal DSPCLK, and an inversed first clock FCLK from the PLL440, and executes an AND operation. The second AND logic gate734receives the write command DWR from the second register544, the clock gating input signal, and an inversed first clock FCLK from the PLL440, and executes an AND operation.

The OR logic gate736receives the outputs from the first and second AND logic gates732,734and generates the memory clock signal MEMCLK by an OR operation.

It is readily appreciated by one skilled in the art that the AND logic gates732,734and the OR logic gate736can be replaced by other logic gates having equivalent Boolean expressions to accomplish the same or equivalent gating operations.

Hereinafter, an operation of the circuit for generating clock signals for clocking the processor410and the memory420will be described.

FIG. 8is a timing diagram for receiving and transmitting data between the DSP410and the memory420.

Referring toFIGS. 4,5,7, and8, the PLL440receives an external clock EXTCLK and generates a first clock FCLK. The clock generator430receives the first clock FCLK. The counter510receives the first clock FCLK, counts the number of the clock cycles, and outputs a count at output L. For example, if the counter510is set to count to 3, the count will repeat every three FCLK 3 cycles.

The first comparator522compares the count value output at L and the first given value M and the second comparator524compares the count value L and the second given value N. The M and N values are preselected. For example, if M is preset equal to ‘1’, the DSP clock signal DSPCLK is periodically generated when the count is equal to ‘1’. Likewise, if N is set to ‘2’, the gating input signal outputs a replica of FCLK when the count reaches ‘2’.

Meanwhile, the DSP410sends a read command DRD for reading data from the memory420or a write command DWR for writing data into the memory420to the clock generator430. The DSP410sends data WDATA(A1) and an address A1to the memory420in response to the write command DWR. However, if the memory clock signal MEMCLK for operating the memory420does not transition, e.g., to “high” from “low”, the data WDATA(A1) is not written into memory.

Referring toFIGS. 7 and 8, a write pulse in the form of a strobe, CLK_WR is generated at the output of the OR logic gate736at MEMCLK when the write command DWR is “high”, the gating input is “high” (the count value is ‘2’), and the inverse of the first clock FCLK are inputted into the AND gate734of the clock gating circuit530. The read command DRD is “low” when the write command is “high” and visa versa. When the write pulse CLK_WR is generated, the data WDATA(A1) is written into the address A1of the memory420.

Likewise, a read pulse (or strobe) CLK_RD is generated as the memory clock signal MEMCLK through the OR logic gate736when the read command DRD is “high”, the DSP clock DSPCLK is pulsed when the count value is ‘1’, and the inverse of the first clock FCLK at a ‘low’ level are present at the AND gate732of the clock gating circuit530. When the read pulse CLK_RD is generated, the DSP410reads the data WDATA(A2) from the address A2of the memory420. Thus, the write pulse CLK_WR and the read pulse CLK_RD are generated when the first clock FCLK is low and each width of the write pulse CLK_WR and the read pulse CLK_RD is about half cycle of the first clock FCLK.

In the conventional circuit and timing diagram shown inFIGS. 1,2, and3, several delays and repeatedly testing may be employed for generating optimum memory clock signals. That is, since data read and data write should be within one cycle of the DSP clock signal DSPCLK, respectively, timing violation is protected by artificially skewing clocks by adding buffers or delays within the data write (T_WR), data read (T_RD), address (T_AD), and data transfer (T_DD) margins. According to an embodiment of the present invention, the generation of the memory clock signal MEMCLK is related to the DSP clock signal DSPCLK and memory access is accomplished within the data write (T_WR), data read (T_RD), address (T_AD), and data transfer (T_DD) margins and within one cycle of the DSP clock signal DSPCLK. Since the write strobe CLK_WR and read strobe CLK_RD are generated when the write command DWR and the read command DRD are activated, respectively, there is reduced duty cycle at the DSPCLK and MEMCLK signals, thereby reducing power consumption.

FIG. 9shows a block diagram of a clock generator according to another embodiment of the present invention. Referring toFIG. 9, the clock generator900are similar to the clock generator430inFIG. 5except the clock divider520ofFIG. 5is replaced by the clock divider920. As shown, the first and second comparators522,524ofFIG. 5are replaced by first, second, and third comparators922,924, and926in the clock divider920inFIG. 9.

According to the present embodiment, a second gating input signal is additionally generated. Thus, each of the first, second, and third given values K, M, N can output a pulse when the count value at L is any one of one (1) to three (3). If the first given value K is set to be the same as the second given value M,FIG. 9operates the same as the circuit shown inFIG. 5.

The first comparator922compares the count value at L and the first given value K. In case the first given value K is “1”, the DSP clock signal DSPCLK is periodically generated when the count value at L is “1”. Further, in case the second given value M is “2”, the second comparator924generates a first gating input signal. In case the third given value N is “3”, the third comparator926generates a second gating input signal. The clock gating circuit530receives the first gating input signal and the second gating input signal, and generates a memory clock signal MEMCLK in response to the read command DRD or the write command DWR.

FIG. 10is a schematic block diagram of a given value generator to generate the given values K, M, and N. Referring toFIG. 10, the given value generator1000includes a first selector1010, a second selector1020, and a third selector1030which are composed of X-to-1 multiplexers. In this case, X is ‘3’. The first selector1010, the second selector1020, and the third selector1030select the first given value K, the second given value M, and the given third value N, respectively, in response to a respective selection signal. If the first clock FCLK is to be divided by 3, the first, second, and third selectors1010,1020,1030can select one of one (1) to three (3). It is appreciated that if the first clock FCLK is to be divided into ‘X’ to generate the DSP clock DSPCLK (where X is a natural number equal or greater than 2), the first, second, third selectors1010,1020,1030can select one of X.