Trench power MOSFET fabrication using inside/outside spacers

A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to MOSFET fabrication, and more specifically, to MOSFET fabrication that uses spacers as masks.

2. Description of Related Art

Trench type power semiconductor devices such as power MOSFETs are well known. Referring toFIG. 1, a typical power MOSFET10includes a plurality of trenches12formed in semiconductor body14. Semiconductor body14is usually a silicon die that includes an epitaxially grown silicon layer (epitaxial silicon layer)16of one conductivity (e.g. N-type) formed over a silicon substrate18of the same conductivity, but of higher concentration of impurities. A channel region20(sometimes referred to as body region) is formed in epitaxial silicon layer16and extends from the top surface of the semiconductor body to a first depth. Channel region20has a conductivity opposite to that of epitaxial layer16(e.g. P-type). Formed within channel region20are source regions22, which have the same conductivity (e.g. N-type) as epitaxial silicon layer16.

As is well known, trenches12extend to a depth below the depth of channel region20and include gate insulation24, which may be formed with silicon dioxide, on at least the sidewalls of trenches12. The bottom of each trench12is also insulated with silicon dioxide or the like and a gate electrode26is disposed within each trench12. Gate electrodes26are typically composed of conductive polysilicon. As is illustrated inFIG. 1, gate electrodes26are recessed to a position below the top of the trenches and thereby below the top surface of the semiconductor body. However, gate electrodes26may also be “proud” electrodes, or in other words, extend out of trenches12and above the top surface of the semiconductor body.

A typical trench type power MOSFET further includes a source electrode28, which is electrically connected to source regions22, and a high conductivity contact region30, which is also formed in channel region20. High conductivity contact region30is highly doped with dopants of the same conductivity as channel region20(e.g. P-type) in order to reduce the contact resistance between source contact28and channel region20. A typical trench type power MOSFET10further includes a drain electrode32in electrical contact with silicon substrate18.

In operation, a voltage is applied to gate electrodes26. When this voltage reaches a threshold value (VTH) a channel is formed adjacent each trench12in channel region20, which formed channel has the same conductivity as that of source regions22and the region below channel20in epitaxial silicon layer16. As a result, a current may flow between source electrode28and drain electrode32of the power MOSFET.

As is well known, the density of the current that a power MOSFET may accommodate is directly proportional to the number of formed channels per unit area. Thus, the greater the number of trenches per unit area the more current a device can handle. Because of this relationship, it is desirable to pack as many trenches as possible for a given die area. This can be accomplished by either reducing the distance between trenches and/or reducing the width of each trench. However, traditional fabrication processes can limit the amount of reduction in these dimensions. For example, traditional masking methods used during the fabrication of a power MOSFET make it difficult to reduce trench width. Similarly, traditional masking methods can lead to mask misalignments. To compensate for these potential misalignments, designers may increase the size of the various regions (e.g., the source regions and high conductivity contact regions) of the MOSFET. However, increased sizes lead to larger distances between trenches.

SUMMARY OF THE INVENTION

Accordingly, it would be desirable to produce a trench type power semiconductor device that has increased cell density, thereby overcoming the above and other disadvantages of the prior art. In accordance with the present invention, power MOSFETs are fabricated through the use of inside and outside spacers that allow for the formation of gate electrode trenches with reduced widths and also allow for the self-alignment of source regions and high conductivity contact regions between each other and the trenches, which in turn allows for reduced distances between trenches. In accordance with a further aspect of the invention, shallower source regions are obtained. At least one benefit of these shallower source regions is that there is less lateral diffusion of the regions, thereby again allowing for reduced distances between trenches. As a result, power MOSFETs fabricated according to the present invention have reduced cell pitch and increased cell density. In general, the fabrication process of the present invention is applicable to power MOSFETS that have gate electrodes recessed below the top surface of the semiconductor body and to power MOSFETS that have gate electrodes that extend above the top surface of the semiconductor body.

More specifically, in accordance with a first embodiment of the present invention, a hard mask layer is first formed over the surface of a semiconductor body, which includes a substrate and epitaxial silicon layer of a first conductivity and a channel region thereupon of a second conductivity. This mask layer is then etched to form a plurality of openings that extend to and expose the surface of the semiconductor body. Inside spacers are then formed along the sidewalls of these openings such that the spacers expose a defined area of the surface of the semiconductor body. Using these spacers as masks, gate electrode trenches are formed into the channel region and epitaxial silicon layer of the semiconductor body. Notably, the use of the inside spacers to create the trenches allows for the formation of narrower trenches than a process such as photo-lithography, for example, would permit.

Thereafter, gate electrodes are formed in the trenches of the semiconductor body. Optionally, the process may also include a step for siliciding or saliciding the gate electrodes to reduce gate resistance. In accordance with this first embodiment, the gate electrodes are recessed below the top surface of the semiconductor body.

Next, the inside spacers are removed and source implant regions are formed in the channel region along the upper edges of the trenches. A diffusion drive is then carried out to form source regions. Notably, through the use of the inside spacers, the source regions are formed through self-alignment, thereby eliminating a need for a mask.

Next, using the initial openings formed in the hard mask layer, insulation caps are formed over the gate electrodes. Subsequently, the remaining hard mask layer is removed, thereby exposing the sidewalls of the insulation caps and exposing the surface of the semiconductor body that lies between the insulation caps. Thereafter, outside spacers are formed along the sidewalls of the insulation caps such that the spacers cover portions of the semiconductor body surface.

Using the outside spacers as masks, a contact etch is next performed along the surface of the semiconductor body and high conductivity contact regions are formed therein. The outside spacers are then removed and source and drain contacts formed. Notably, through the use of the outside spacers, the high conductivity contact regions are self-aligned between adjacent source regions and adjacent gate electrode trenches. Overall, by using the inside and outside spacers to self-align the source regions and high conductivity contact regions between each other and the gate electrode trenches, the distance between adjacent trenches can be reduced.

In accordance with a second embodiment of the invention, a two-phase source implant is used that results in shallower source regions as compared to the first embodiment. As indicated, shallower source regions result in less lateral diffusion of the source implants, which allows for the distance between adjacent trenches to be reduced, among other benefits.

Here, the source implant regions formed along the edges of the gate electrode trenches, as described above, are not initially driven. Rather, the diffusion drive is skipped and the insulation caps formed. Thereafter, once the remaining hard mask layer is removed as described above, a second blanket source implant is carried out to form source implant regions in the surface of the semiconductor body in the areas between adjacent insulation caps. The outside spacers are then formed covering portions of the source implant regions formed from the blanket source implant. The spacers are then used as masks to completely remove any exposed portion of the source implant regions. A source diffusion drive is then carried out to drive any remaining portions of the source implant regions, thereby creating source regions. Thereafter, high conductivity contact regions are formed in the etched regions.

In accordance with a third embodiment of the invention, the fabrication process is similar to the second embodiment. However, here, the gate electrodes are made larger to reduce gate resistance. Specifically, the gate electrodes, which again may be silicided or salicided, extend up to or above the surface of the semiconductor body, rather than being recessed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIGS. 2A-2L(note that the Figures are not drawn to scale), a power MOSFET fabrication process according to a first embodiment of the invention is illustrated, the fabrication process here resulting in gate electrodes that are recessed below the top surface of the semiconductor body. Beginning withFIG. 2A, there is shown an initial silicon body100. Silicon body100preferably includes a silicon substrate102of one conductivity (e.g., N-type) and epitaxial silicon layer104of the same conductivity (e.g., N-type) grown over one major surface of silicon substrate102. As is known, epitaxial silicon layer104includes a lower concentration of dopants as compared to substrate102. Silicon body100also includes channel region106, which has conductivity opposite to that of epitaxial silicon layer104(e.g. P-type). Preferably, channel region106is formed by implanting dopants on the surface of silicon layer104and driving these dopants in a diffusion drive to a desired channel depth. However, channel region106may also be formed by epitaxially growing the channel on the surface of layer104. As illustrated inFIG. 2A, once channel region106is formed, it is covered with a pad oxide layer108and a removable hard mask layer110, preferably composed of silicon nitride (Si3Ni4).

Referring toFIG. 2B, a masked pattern is next formed on the surface of mask layer110using, for example, a photolithographic process. A suitable etching process is then performed to remove the unmasked portion of hard mask layer110and the corresponding portion of oxide layer108, thereby forming openings112. As illustrated inFIG. 2B, openings112extend down to and thereby expose the top surface of channel region106. As also illustrated in this Figure, each of openings112is separated by the remaining regions of hard mask layer110and oxide layer108.

Thereafter, an oxide layer, composed from TEOS or the like for example, is formed over the surface of the structure inFIG. 2B. This oxide layer is then etched back, removing the oxide from the surface of hard mask layer110and more importantly, forming inside spacers114along the walls of openings112, as illustrated inFIG. 2C. Significantly, the oxide removal is controlled such that inside spacers114expose a desired width/cross section116of the surface of channel region106.

Referring toFIG. 2D, an appropriate etching process is next carried out through the inside spacers to form trenches118that extend from the surface of channel region106into epitaxial silicon layer104. Note that inside spacers114act as a mask during this etching step and as such, determine the width116of trenches118. Significantly, the use of spacers114to create trenches118allows for the formation of narrower trenches than a process such as photo-lithography, for example, would permit. Again, narrower trenches allow the resulting power MOSFET to have an increased cell density.

Referring next toFIG. 2E, the sidewalls and bottom surfaces of trenches118are oxidized to form gate oxide/insulation layers120. Note that because of hard mask layer110and inside spacers114, only the sidewalls and bottom surfaces of trenches118are oxidized in this step. Next, un-doped polysilicon is deposited over the surface of the structure such that the polysilicon fills trenches118. A suitable dopant is then applied to the surface of the structure and diffused. Thereafter, the doped polysilicon is removed from the surface of the structure through appropriate masking and etching, thereby leaving gate electrodes122within trenches118, as illustrated inFIG. 2E. Note that in accordance with this first embodiment of the invention, gate electrodes122are recessed below the top surface of trenches118and thereby the top surface of channel region106.

As an option and as also illustrated inFIG. 2E, silicide or salicide contacts124can be formed over the top ends of each gate electrode122in order to reduce the local resistive value. This is desirable, for example, when trenches118are narrow (as described above), which results in reduced gate electrode sizes and thereby increased gate electrode resistance. Thus, for example, a layer of metal such as titanium, cobalt, or nickel is next deposited over gate electrodes122and over mask layer110and spacers114, and is then annealed. The metal reacts with the polysilicon and silicides portions of the same. Thereafter, the unreacted portion of the metal is removed thereby forming silicide/salicide contacts124at the top of each gate electrode122. Again, note that silicide/salicide contacts124do not extend to the top surface of channel region106.

Referring toFIG. 2F, inside spacers114are next removed exposing a portion of channel region106along the upper edges of each trench118. A source implant is then carried out thereby forming source implant regions128in channel region106along the upper edges of each trench118. Next, as illustrated inFIG. 2G, a diffusion drive is carried out forming source regions130along the upper edges of the trenches. Notably, through the use of the inside spacers, the resulting source regions are formed through self-alignment, thereby eliminating the need for a mask.

Referring toFIG. 2H, an oxide layer, composed from TEOS or the like for example, is next formed over the surface of the structure ofFIG. 2G, covering hard mask layer110and filling openings112. This oxide layer is then etched back forming insulation caps132over gate electrodes122. Note that insulation caps132fill both openings112and also the remaining portion of trenches118(i.e., the portion that lies between the top of gate electrodes122and the top surface of channel region106).

Referring toFIG. 2I, an appropriate etching process is next carried out to remove the remaining hard mask layer110and pad oxide layer108. As a result, openings134are formed between adjacent insulation caps132, with the bottom of each opening exposing the top surface of channel region106and a portion of the top surface of source regions130that are not covered by insulation caps132. Thereafter, a second hard mask layer, preferably composed of silicon nitride (Si3Ni4), is formed over the surface of the structure shown inFIG. 2I, filling openings134and covering insulation caps132. This second hard mask layer is then etched back, removing the mask from the top surface of insulation caps132and forming outside spacers136along the walls of insulation caps132. The resulting structure is shown inFIG. 2J. Significantly, spacers136form openings of a desired width/cross-section138that are aligned between adjacent insulation caps132and thereby between adjacent source regions130and trenches118. As shown, spacers132are sized such that the surface of channel region106is exposed (as illustrated by arrow139a) and such that the surface of a desired portion of source regions130is exposed (as illustrated by arrows139b).

Referring toFIG. 2K, a contact etch is next performed through spacers136, along cross-section138, thereby using spacers136as a mask. This contact etch removes a portion of channel region106(along the region designated by arrow139ainFIG. 2J) and removes a portion of source regions130(along the region designated by arrows139binFIG. 2J). Thereafter, dopants of the same conductivity as channel region106are implanted in source regions130and channel region106along the etched region and after a diffusion drive, high conductivity contact regions140are formed as illustrated inFIG. 2K. Again, through the use of outside spacers136, conductivity regions140are self-aligned between adjacent source regions130and trenches118. Overall, by using inside spacers114and outside spacers136to self-align the source regions130and high conductivity contact regions140between each other and trenches118, the distance between adjacent trenches can be reduced. Again, this reduced distance allows the resulting power MOSFET to have an increased cell density.

Finally, referring toFIG. 2L, once high conductivity contact regions140are formed, nitride spacers136are stripped. Thereafter, a front metal and back metal are applied using known methods to obtain source contact142and drain contact144.

Referring now toFIGS. 3A-3G, a power MOSFET fabrication process according to a second embodiment of the invention is illustrated. This process is similar to the process of the first embodiment of the present invention but uses a two-phase source implant rather than one. This two-phase source implant results in shallower source regions as compared to those created according to the first embodiment. Significantly, shallower source regions results in less lateral diffusion of the source implant. Again, this is beneficial because it allows for the distance between adjacent trenches to be reduced. Shallower source regions also allow for reduced processing temperatures, among other benefits. Accordingly, the process of this second embodiment proceeds as described above throughFIG. 2Fwhere a source implant is carried out to form source implant regions128in channel region106along the upper edges of each trench118. However, rather than carrying out a source diffusion drive as inFIG. 2G, this step is skipped and insulation caps132are formed over the gate electrodes by applying and etching back an oxide layer, composed from TEOS or the like for example. The resulting structure is illustrated inFIG. 3A.

Referring toFIG. 3B, an appropriate etching process is next carried out to remove the remaining hard mask layer110and pad oxide layer108. As a result, openings134are formed between adjacent insulation caps132, with each opening now exposing the top surface of channel region106. Thereafter and as illustrated inFIG. 3C, a second blanket source implant is carried out through openings134to form source implant regions146in channel region106in the area along the bottom of each opening134.

Referring toFIG. 3D, a second hard mask layer, preferably composed of silicon nitride (Si3Ni4), is then formed over the surface of the structure shown inFIG. 3C, filling openings134and covering the top surface of insulation caps132. This second mask layer is then etched back, removing the mask layer from the top surface of insulation caps132and forming outside spacers148along the walls of insulation caps132. Again, spacers148form openings of a desired width/cross-section150that are aligned between adjacent insulation caps132and thereby adjacent trenches118. As shown inFIG. 3D, spacers148are sized such that a desired portion of source implant regions146is exposed (as illustrated by arrow149a).

Next, a contact etch is performed through outside spacers148, along cross-sections150, thereby using spacers148as a mask. This contact etch removes source implant regions146in the area designated by arrow149ainFIG. 3D, thereby exposing a portion of the top surface of channel region106. As illustrated inFIG. 3E, a source diffusion drive is then carried out to drive the remaining portions of source implant regions146(i.e., the portions masked by spacers148), thereby forming source regions152. As illustrated and as compared to the first embodiment, this two-phase source implant process for forming source regions152of this second embodiment results in shallower source regions. At least one benefit of these shallower source regions is that there is less lateral diffusion of the regions. Again, this is beneficial because it allows for the distance between adjacent trenches to be reduced.

Referring toFIG. 3F, dopants of the same conductivity as channel region106are next implanted in channel region106along the etched region created by the contact etch (i.e., the area designated by arrow149binFIG. 3E) and after a diffusion drive, high conductivity contact regions154are formed. Again, through the use of inside spacers114and outside spacers148, source regions152and high conductivity contact regions154are self-aligned between each other and trenches118, thereby allowing the distance between adjacent trenches118to be reduced.

Finally, referring toFIG. 3G, outside spacers148are stripped and a front metal and back metal are applied using known methods to obtain source contact142and drain contact144.

Referring now toFIGS. 4A-4H, a power MOSFET fabrication process according to a third embodiment of the invention is illustrated. This process is similar to the first and second embodiments and in particular, uses a two-phase source implant to create shallower source regions. However, the fabrication process of this third embodiment also results in larger gate electrodes, as compared to the first and second embodiments, and in particular, electrodes that extend up to and optionally above the top surface of the semiconductor body. As indicated above, thinner trenches result in smaller gate electrodes, which increases gate resistance. Among other benefits, by creating larger electrodes in accordance with this third embodiment of the invention, gate resistance is reduced.

Accordingly, the process of this third embodiment proceeds as described above for the first embodiment throughFIG. 2D. Thereafter, gate insulation layers120are formed on the sidewalls and bottom surfaces of trenches118. An un-doped polysilicon is then deposited over the surface of the structure and doped with a suitable dopant. The doped polysilicon is then removed from the surface of the structure through appropriate masking and etching in order to produce gate electrodes156within trenches118, as now illustrated inFIG. 4A. Again, silicide or salicide contacts158can optionally be formed over the top ends of each gate electrode156to reduce the local resistive value. Significantly, note that the polysilicon of gate electrodes156now extends to the upper edges of trenches118and to the top surface of channel region106. Note also that if silicide/salicide contacts158are included, these contacts extend out of the trenches and above the top surface of channel region106.

Referring toFIG. 4B, inside spacers114are next removed exposing a portion of channel region108along the upper edges of each trench118. The process then proceeds similar to the second embodiment for the formation of the source regions. Specifically, a first source implant is next carried out to form source implant regions160in channel region106along the upper edges of each trench118. However, again, a source diffusion drive is not carried out. Rather, a layer of oxide, composed from TEOS or the like for example, is formed over the surface of the structure, covering hard mask layer110and filling openings112. This oxide layer is then etched back, forming insulation caps162over the gate electrodes156. The resulting structure is shown inFIG. 4B.

Referring toFIG. 4C, an appropriate etching process is next carried out to remove the remaining hard mask layer110and pad oxide layer108. As a result, openings134are formed between adjacent insulation caps162, with each opening exposing the top surface of channel region106. Thereafter and as illustrated inFIG. 4D, a second blanket source implant is carried out through openings134to form source implant regions164in channel region106in the area along the bottom of each opening134.

Referring toFIG. 4E, a second hard mask layer, preferably composed of silicon nitride (Si3Ni4), is formed over the surface of the structure shown inFIG. 4D, filling trenches134and covering the top surface of insulation caps162. This second mask layer is then etched back, removing the mask layer from the top surface of insulation caps162and forming outside spacers166along the walls of insulation caps162. Again, spacers166form openings of a desired width/cross-section168that are aligned between adjacent insulation caps162and thereby adjacent trenches118. As shown inFIG. 4E, spacers166are sized such that a desired portion of source implant regions164is exposed (as illustrated by arrow169a).

Next, using outside spacers166as a mask, a contact etch is performed through the spacers, removing source implant regions164in the area designated by arrow169ainFIG. 4E. As a result, a portion of the top surface of channel region106is now exposed. A source diffusion drive is then carried out to drive the remaining portions of the source implant regions164(i.e., the portions masked by spacers166), thereby forming source regions170. The resulting structure is illustrated inFIG. 4F.

Referring toFIG. 4G, dopants of the same conductivity as channel region106are next implanted in channel region106along the etched region created by the contact etch (i.e., the area designated by arrow169binFIG. 4F) and after a diffusion drive, high conductivity contact regions172are formed.

Finally, referring toFIG. 4H, outside spacers166are stripped and a front metal and back metal are applied using known methods to obtain source contact142and drain contact144.

Note thatFIGS. 2A-2L,FIGS. 3A-3G, andFIG. 4A-4Hshow N-type trench MOSFETs. Nonetheless, one skilled in the art will realize that the above processes also apply to P-type trench MOSFETS.

Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore, the present invention should be limited not by the specific disclosure herein, but only by the appended claims.