Array substrate and manufacturing method thereof, and display device

An array substrate and a manufacturing method thereof and a display device are provided. The manufacturing method includes: forming a first signal line and a second signal line which have a same extension direction and are separated from each other on a base substrate; forming an initial pixel electrode on the base substrate, such that the initial pixel electrode includes a first extension portion, and the initial pixel electrode is connected to the first signal line by the first extension portion and the initial pixel electrode is separated from the second signal line; and removing at least part of the first extension portion of the initial pixel electrode to form the pixel electrode separated from the first signal line.

TECHNICAL FIELD

Embodiments of the present disclosure relate to an array substrate and a manufacturing method thereof; and a display device.

BACKGROUND

Liquid crystal display device is a mainstream product in a field of display. One of key components of the liquid crystal display device is an array substrate provided with a plurality of pixel units. For example, a manufacturing process for the array substrate includes forming the following layers on a substrate in sequence: a pixel electrode layer including a pixel electrode, a gate metal layer including a gate line and a common electrode line (also called as a storage capacitance line), a gate insulation layer, an active layer, a data metal layer including a source/drain electrode and a data line, a passivation layer and a common electrode layer including a common electrode.

SUMMARY

According to embodiments of the disclosure, a manufacturing method for an array substrate is provided. The method comprises: forming a first signal line and a second signal line which have a same extension direction and are separated from each other on a base substrate; forming an initial pixel electrode on the base substrate, wherein the initial pixel electrode includes a first extension portion, the initial pixel electrode is connected to the first signal line by the first extension portion, and the initial pixel electrode is separated from the second signal line; and removing at least part of the first extension portion of the initial pixel electrode to form a pixel electrode separated from the first signal line.

For example, the manufacturing method further comprises: forming a common electrode on the base substrate after forming the first signal line, the second signal line and the initial pixel electrode.

For example, the forming the common electrode on the base substrate includes: forming a common electrode film on the base substrate; and performing a patterning treatment on the common electrode film to form the common electrode; in the patterning treatment, the at least part of the first extension portion of the initial pixel electrode is removed.

For example, the manufacturing method further comprises: before forming the common electrode, forming an insulation layer covering the initial pixel electrode on the base substrate and a via hole located in the insulation layer. The via hole at least exposes the at least part of the first extension portion of the initial pixel electrode.

For example, one of the first signal line and the second signal line is a gate line, and the other of the first signal line and the second signal line is a common electrode line.

For example, forming the first signal line and the second signal line includes: forming a conductive film, performing a patterning treatment on the conductive film to form the first signal line and the second signal line.

For example, the manufacturing method further comprises: forming a thin film transistor on the base substrate, the thin film transistor including a gate electrode, a source electrode, a drain electrode and an active layer. The initial pixel electrode further includes a second extension portion, and the second extension portion is connected to the drain electrode.

For example, the manufacturing method further comprises: forming a thin film transistor on the base substrate, the thin film transistor including a gate electrode, a source electrode, a drain electrode and an active layer. The drain electrode of the thin film transistor is connected to the first extension portion of the initial pixel electrode.

For example, the manufacturing method further comprises: before removing the at least part of the first extension portion of the initial pixel electrode, performing defect detection on the first signal line and the second signal line between adjacent initial pixel electrodes.

According to the embodiments of the disclosure, an array substrate is provided. The array substrate comprises: a base substrate; a first signal line and a second signal line disposed on the base substrate, wherein the first signal line and the second signal line have a same extension direction and are separated from each other; and a pixel electrode layer disposed on the base substrate, wherein the pixel electrode layer includes a pixel electrode and a remain portion separated from the pixel electrode, and the remain portion is connected to the first signal line and is separated from the second signal line.

For example, the array substrate further comprises: a common electrode, disposed on a side of the pixel electrode layer away from the base substrate.

For example, the array substrate further comprises: an insulation layer covering the pixel electrode layer. A via hole is disposed in the insulation layer, and at least part of the via hole corresponds to an interval region between the pixel electrode and the remain portion.

For example, the via hole is located outside a region corresponding to the common electrode.

For example, the pixel electrode includes a first protrusion portion, the first protrusion portion is a protrusion protruding toward the first signal line connected to the remain portion, and the via hole is located between the first protrusion portion and the remain portion.

For example, the array substrate further comprises: a thin film transistor disposed on the base substrate, the thin film transistor including a gate electrode, a source electrode, a drain electrode and an active layer. The pixel electrode further includes a second protrusion portion, and the pixel electrode is connected to the drain electrode by the second protrusion portion.

For example, the array substrate further comprises: a thin film transistor disposed on the base substrate, the thin film transistor including a gate electrode, a source electrode, a drain electrode and an active layer. The pixel electrode is connected to the drain electrode by the first protrusion portion.

According to the embodiments of the disclosure, a display device is provided. The display device comprises the array substrate as described above.

DETAILED DESCRIPTION

Unless otherwise defined, the technical terms or scientific terms here should be of general meaning as understood by those ordinarily skilled in the art. In the descriptions and claims of the present disclosure, expressions such as “first”, “second” and the like do not denote any order, quantity, or importance, but rather are used for distinguishing different components. Expressions such as “include” or “comprise” and the like denote that elements or objects appearing before the words of “include” or “comprise” cover the elements or the objects enumerated after the words of “include” or “comprise” or equivalents thereof, not exclusive of other elements or objects. Expressions such as “connect” or “interconnect” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Expressions such as “up”, “down”, “left”, “right” and the like are only used for expressing relative positional relationship, the relative positional relationship may be correspondingly changed in the case that the absolute position of a described object is changed.

Thickness and shape of each layer in the drawings do not reflect a true proportion, and merely are intended to explain content of the embodiments of the present disclosure.

FIG. 1is a schematic view of a pixel structure of an array substrate. For example, a manufacturing method for the pixel structure shown inFIG. 1comprises steps S01to S06below.

Step S01: forming a pixel electrode layer including a pixel electrode03.

Step S02: forming a gate metal layer including a gate line02a, a common electrode line02band a gate electrode06a.

Step S03: forming a gate insulation layer covering the gate metal layer.

Step S04: forming an active layer06dand a data metal layer including a data line07, a source electrode06band a drain electrode06con the gate insulation layer. The active layer06d, the source electrode06band the drain electrode06cformed in this step and the gate electrode06aformed in the step S02form a thin film transistor06.

Step S05: forming a passivation layer covering the active layer06dand the data metal layer, wherein the passivation layer formed in this step and the gate insulation layer formed in the step S03are together called as an insulation layer04; and via holes04c,04band04dformed in the insulation layer04respectively expose a part of the pixel electrode03, a part of the drain electrode06cand a part of the common electrode line02b.

Step S06: forming a common electrode layer including a common electrode05and a connection portion05aon the insulation layer04, such that the common electrode05is connected to the common electrode line02bby the via hole04d, the connection portion05ais connected to the pixel electrode03by the via hole04band is connected to the drain electrode06cby the via hole04cto realize connection between the pixel electrode03and the drain electrode06c.

FIG. 2ais a schematic top view of the array substrate comprising the pixel structure as shown inFIG. 1. As shown inFIG. 2a, the gate line02aand the common electrode line02bare alternately disposed and the gate line02aand common electrode line02badjacent to each other are disposed between adjacent pixel electrodes03, thereby forming a plurality of pixel structures in periodical distribution. In the manufacturing process of the array substrate, after the gate line02aand the common electrode line02bare formed, whether short circuit defect occurs between the gate line02aand the common electrode line02bneeds to be detected. For example, as shown inFIG. 2b, a detection device includes a signal-loading test head and a signal-receiving test head01b, which are respectively located right above a group of signal lines to be tested (that is, the gate line02aand the common electrode line02badjacent to each other); by loading and receiving the test signal in a capacitance induction manner, whether the short circuit occurs among the group of signal lines is judged, and by moving the test heads (as shown by an arrow inFIG. 2b), whether the respective groups of signal lines have short circuit defect are detected one group by one group.

In research, an inventor of the present application found that: because the gate line and the common electrode line adjacent to each other are very close to each other a difference between a capacitance between the gate line and the test heads of the detection device and a capacitance between the common electrode line and the test heads of the detection device is very small; as a result, in a case that the short circuit occurs between the gate line and the common electrode line adjacent to each other, a resolution capacity of the detection device is insufficient, and the probability that the short circuit defect cannot be detected is larger.

In order to solve the problem above, as shown inFIG. 3, at least one embodiment of the present disclosure provides a manufacturing method for an array substrate, which comprises steps S1to S3below.

Step S1: as shown inFIG. 4a, forming a first signal line12aand a second signal line12bwhich have an approximately same extension direction and are separated from each other on a base substrate11;

Step S2: as shown inFIG. 4a, forming an initial pixel electrode13′ on the base substrate11, wherein the initial pixel electrode13′ includes a first extension portion131, the initial pixel electrode13′ is connected to the first signal line12aby the first extension portion131, and the initial pixel electrode13′ is separated from the second signal line12b; and

Step S3: after the steps S1and S2are finished, removing at least part of the first extension portion131of the initial pixel electrode13′ to form a pixel electrode13separated from the first signal line12a, as shown inFIG. 4b.

It needs to be noted that a sequence of the steps S1and S2is not limited, for example, the step S2is carried out after the step S1, or the step S1is carried out after the step S2. In addition, the first extension portion131for example is partially removed, for example, after the first extension portion131is removed, a pixel electrode layer130including the pixel electrode13and a remain portion131awhich are separated from each other are formed, and the pixel electrode13for example includes a first protrusion portion131b(as shown inFIG. 4b) or does not include the first protrusion portion131b. Alternatively, for example, the first extension portion131is totally removed.

In the manufacturing process of the array substrate, the pixel structures as shown inFIGS. 4aand 4bare in periodical distribution, and therefore, the first signal line12aand the second signal line12badjacent to each other are disposed between the adjacent initial pixel electrodes13′ (as shown inFIG. 11). By connecting one of the two adjacent signal lines with the initial pixel electrode13′, which is equivalent to the increase of an area of the signal line, in a subsequent process of detecting defects (for example, short circuit defect) between these two signal lines, an obvious difference exists between detection results (for example, capacitance) of the two signal lines detected by a detection device, and thus, a defect detection accuracy is improved; and after the detection is finished, by removing the at least part of the initial pixel electrode13′ to form the pixel electrode13, functions of the pixel electrode13and the signal line are prevented from being affected.

It needs to be explained that an application range of the embodiments of the present disclosure includes, but not limited to, the detection of short circuit defect between the signal lines, and the embodiments of the present disclosure are also used in detection of other types of defects of the signal lines.

For example, the initial pixel electrode13′ is made of a transparent conductive material, for example, transparent metal oxides such as indium tin oxide or indium zinc oxide.

For example, the first and second signal lines are made of a metal material, for example, one or more of aluminum, aluminum neodymium alloy, copper, titanium, molybdenum, molybdenum niobium alloy and the like.

Different signals are applied to the first signal line12aand the second signal line12bduring the first signal line12aand the second signal line12bwork, for example, a gate scanning signal is applied to one of the first signal line and the second signal line (that is, one of the first signal line and the second signal line is a gate line), and a common voltage signal is applied to the other of the first signal line and the second signal line (that is, the other of the first signal line and the second signal line is a common electrode line). Of course, in a case that the embodiments of the present disclosure are used for detecting the short circuit defect among other types of signal lines, other types of signals are respectively applied to the first and second signal lines.

For example, in the step S1, the first signal line12aand the second signal line12bare formed by patterning a same film to simplify the manufacturing process; for example, a forming process of the first signal line12aand the second signal line12bincludes: forming a conductive film, performing a patterning treatment on the conductive film to form the first signal line12aand the second signal line12b. For example, the patterning treatment includes photoresist coating, photoresist exposing by using a mask, photoresist developing to obtain a photoresist pattern, etching by using the photoresist pattern, and the like. Alternatively, for example, the first and second signal lines are formed by different films respectively and are disposed on the base substrate side by side.

For example, the embodiments of the present disclosure are used for manufacturing the array substrate in a liquid crystal display device or other similar array substrates; and the similar array substrates include the alternately disposed first and second signal lines and the adjacent first and second signal lines are disposed between the adjacent pixel electrodes, such as, an OLED array substrate.

For example, the manufacturing method provided by at least one embodiment of the present disclosure further comprises forming a common electrode. For example, the common electrode15is made of a transparent conductive material, for example, a transparent metal oxide such as indium tin oxide or indium zinc oxide.

For example, after the first signal line12a, the second signal line12band the initial pixel electrode13′ are formed (after the steps S1and S2are finished) and after the detection of the defects (for example, short circuit defect) between the first signal line12aand the second signal line12bis finished, the common electrode is formed on the base substrate11. That is to say, in the array substrate manufactured by the manufacturing method provided by at least one embodiment of the present disclosure, the pixel electrode13is disposed between the common electrode and the base substrate11. For example, forming the common electrode includes: forming a common electrode film150on the base substrate11, as shown inFIG. 5a; and performing patterning treatment on the common electrode film150to form a common electrode15, as shown inFIG. 5b.

It needs to be noted that in a case that the pixel electrode13is disposed between the common electrode15and the base substrate11, for example, the common electrode15is of a slit structure, and the pixel electrode13is of a slit structure or a plate structure.FIG. 5bmerely schematically shows the common electrode15and the pixel electrode13, but is not intended to limit the shapes thereof.

For example, in the patterning treatment process of forming the common electrode15, the at least part of the first extension portion131of the initial pixel electrode13′ is removed to form the pixel electrodes13as shown inFIG. 5b. The common electrode15and the pixel electrode13are formed by the same patterning treatment, and the manufacturing process is simplified.

For example, the manufacturing method provided by at least one embodiment of the present disclosure further comprises: before forming the common electrode, forming an insulation layer covering the initial pixel electrode on the base substrate and forming a via hole in the insulation layer, such that the via hole exposes the at least part of the first extension portion of the initial pixel electrode. By disposing the via hole, the at least part of the first extension portion is not covered by the insulation layer, such that a portion of the common electrode film in the via hole and the at least part of the first extension portion exposed by the via hole are removed by a single etching treatment to obtain the pixel electrode.

For example, the manufacturing method provided by at least one embodiment of the present disclosure further comprises: forming a thin film transistor, the thin film transistor including a gate electrode, an active layer, and a source electrode and a drain electrode respectively connected to the active layer, the drain electrode being connected to the initial pixel electrode. For example, a connection manner between the drain electrode and the initial pixel electrode includes the following two manners:

Manner I: on the basis that the initial pixel electrode includes the first extension portion, the initial pixel electrode further includes a second extension portion, and the initial pixel electrode is connected to the drain electrode of the thin film transistor by the second extension portion.

Manner II: the first extension portion that the initial pixel electrode includes is further connected to the drain electrode of the thin film transistor on the basis that the first extension portion is connected to the first signal line.

For example, the thin film transistor adopts a bottom gate structure, that is, the gate electrode is disposed between the active layer and the base substrate; or the thin film transistor adopts a top gate structure, that is, the active layer is disposed between the gate electrode and the base substrate.

The manner I is explained by taking the first signal line which is the gate line, the second signal line which is the common electrode line and the thin film transistor which is the bottom gate structure as examples.

For example, as shown inFIGS. 6aand 6b, before removing the at least part of the first extension portion131(that is, before the step S3), the array substrate manufactured by the method provided by any embodiments of the present disclosure includes the gate line121, the common electrode line122, a data line17, the initial pixel electrode13′, the insulation layer14, the common electrode15and the thin film transistor16. The gate line121and the common electrode line122extend approximately in a same direction and are separated from each other. The data line17is intersected with the gate line121and the common electrode line122. The thin film transistor16includes the gate electrode16a, the source electrode16b, the drain electrode16cand the active layer16d, the gate electrode16ais connected to the gate line121, and the source electrode16bis connected to the data line17. The initial pixel electrode13′ has the first extension portion131and the second extension portion132; the first extension portion131is located outside a region corresponding to the common electrode15and is connected to the gate line121, and the via hole14ain the insulation layer14exposes the at least part of the first extension portion131; the second extension portion132is connected to the drain electrode16c, for example, the second extension portion132is connected to the drain electrode16cby a connection portion15a(disposed in the same layer as the common electrode15) and via holes14band14cin the insulation layer14. The common electrode15is connected to the common electrode line122by the via hole14din the insulation layer14.

For example, as shown inFIG. 6c, the insulation layer14includes a first insulation layer141and a second insulation layer142; the first insulation layer141is, for example, a gate insulation layer located between the active layer14dand the gate electrode14a; and the second insulation layer142is, for example, a passivation layer covering the source electrode14b, the drain electrode14cand the active layer14d.

For example, as shown inFIGS. 7ato 7b, after the at least part of the first extension portion131in theFIGS. 6ato 6cis removed (that is, the step S3is finished), the pixel electrode13has the first protrusion portion131band a second protrusion portion132(i.e., the second extension portion of the initial pixel electrode); the first protrusion portion131band the remain portion131aof the initial pixel electrode (hereinafter short for “remain portion”) are separated; the second protrusion portion132is connected to the drain electrode16cof the thin film transistor16, for example, is connected to the drain electrode16cby the connection portion15aand the via holes14band14cin the insulation layer14. As shown inFIG. 7c, the via hole14apenetrating through the insulation layer14corresponds to an interval region131cbetween the pixel electrode (see the first protrusion portion131b) and the remain portion131a.

Regarding the array substrate as shown inFIG. 7atoFIG. 7c, the manufacturing method provided by the embodiments of the present disclosure comprises steps S11to S16below.

Step S11: as shown inFIG. 8a, forming the initial pixel electrode13′ including the first extension portion131and the second extension portion132.

Step S12: as shown inFIG. 8bandFIG. 8c, forming a gate metal film120, carrying out a patterning treatment to form a gate metal layer including the gate line121, the common electrode line122and the gate electrode16a.

Step S13: as shown inFIG. 8d, forming the first insulation layer141covering the gate metal layer.

Step S14: as shown inFIG. 8d, forming the active layer16don the first insulation layer141and a data metal layer including the data line17, the source electrode16band the drain electrode16c.

Step S15: as shown inFIG. 8e, forming the second insulation layer (not shown) covering the active layer16dand the data metal layer, thereby obtaining the insulation layer14, wherein the via holes14a,14b,14cand14dformed in the insulation layer14respectively correspond to the first extension portion131, the second extension portion132, the drain electrode16cand the common electrode line122.

Step S16: as shown inFIG. 8f, forming the common electrode film150covering the insulation layer14; performing a patterning treatment on the common electrode film150to form a common electrode layer (as shown inFIGS. 6ato 6c) including the common electrode15and the connection portion15aand a pixel electrode layer (as shown inFIGS. 7ato 7c) including the pixel electrode13and the remain portion131a. The common electrode15is connected to the common electrode line122by the via hole14d, the connection portion15aand the common electrode15are separated from each other, and the connection portion15ais connected with the pixel electrode13by the via hole14band is connected with the drain electrode16cby the via hole14cso that the pixel electrode13and the drain electrode16care connected together. In such step, the part of the initial pixel electrode13′ (as shown by the first extension portion131inFIG. 6c) exposed by the via hole14ais removed, and therefore, the first protrusion portion131bof the pixel electrode13is separated from the remain portion131a(as shown inFIG. 7c).

It can be known from the steps S11to S16above that compared with the manufacturing method for the array substrate as shown inFIG. 1, the array substrate as shown inFIGS. 7ato 7conly needs to change a mask for forming the pixel electrode13and a mask for forming the second insulation layer, therefore, the manufacturing method provided by the embodiments of the present disclosure further has the advantage of simple process on the basis that the accuracy of the detection result of the short circuit defect is improved.

In a case that the first signal line is the common electrode line and the second signal line is the gate line, the manufacturing method provided by at least one embodiment of the present disclosure refers to the steps S11to S16above; besides, compared with the manufacturing method for the array substrate as shown inFIG. 1, the manufacturing method needs to change masks for forming the pixel electrode13and the second insulation layer and the common electrode.

The above manner II is explained by taking the first signal line which is the gate line, the second signal line which is the common electrode line and the thin film transistor which is of the bottom gate structure as example.

For example, as shown inFIG. 9a, before the at least part of the first extension portion131that the initial electrode pixel13′ includes is removed, the connection portion15ais connected to the first extension portion131by the via hole14ain the insulation layer14and is connected to the drain electrode16cof the thin film transistor16by the via hole14cin the insulation layer14, and therefore, the electric connection between the first extension portion131and the drain electrode16cis realized. As shown inFIG. 9b, the part of the first extension portion131overlapped with the via hole14aincludes a first portion1311and a second portion1312, the first portion1311is covered by the connection portion15aand the second portion1312is not covered by the connection portion15a.

After the at least part of the first extension portion131in theFIG. 9ais removed, as shown inFIG. 10a, the first protrusion portion131bof the pixel electrode13is separated from the remain portion131aand is connected to the drain electrode16cby the connection portion15a. As shown inFIG. 10b, the first portion1311of the first extension portion131is covered by the connection portion15aand is thus not etched away; the second portion1312of the first extension portion131is not covered by the connection portion15aand is thus etched away, therefore, an interval region131cbetween the first protrusion portion131band the remain portion131ais formed, and part of the via hole14acorresponds to the interval region131c.

With respect to the array substrate as shown inFIGS. 10aand 10b, the manufacturing method provided by the embodiments of the present disclosure further comprise steps S21to S26below.

Step S21: as shown inFIG. 9a, forming the initial pixel electrode13′ including the first extension portion131.

Step S22: forming the gate metal film, performing a patterning treatment to form the gate metal layer including the gate line121, the common electrode line and the gate electrode16a, as shown inFIG. 9a.

Step S23: as shown inFIG. 9b, forming the first insulation layer141covering the gate metal layer.

Step S24: as shown inFIG. 9a, forming the active layer16dand the data metal layer including the data line17, the source electrode16band the drain electrode16con the first insulation layer (not shown).

Step S25: as shown inFIGS. 9aand 9b, forming the second insulation layer142covering the active layer16dand the data metal layer, thereby obtaining the insulation layer14; and forming the via hole14acorresponding to the first extension portion131, the via hole14ccorresponding to the drain electrode16cand the via hole14dcorresponding to the common electrode line122in the insulation layer14.

Step S26: forming the common electrode film covering the insulation layer14, and performing a patterning treatment on the common electrode film to form the common electrode layer including the common electrode15and the connection portion15a(as shown inFIGS. 9aand 9b) and the pixel electrode layer (as shown inFIGS. 10aand 10b) including the pixel electrode13and the remain portion131a, such that the common electrode15is connected to the common electrode line by the via hole14d, the connection portion15aand the common electrode15are separated, and the connection portion15ais connected with the pixel electrode13by the via hole14aand is connected with the drain electrode16cby the via hole14cso that the pixel electrode13and the drain electrode16care connected together. In such step, the part of the first extension portion131of the initial pixel electrode13′ (as shown inFIG. 9a) exposed by the via hole14ais partially removed, such that the first protrusion portion131band the remain portion131aof the pixel electrode13are separated.

It can be known from the steps S21to S26, compared with the manufacturing method for the array as shown inFIG. 1, the array substrate as shown inFIGS. 10aand 10bonly need to change a mask for forming the pixel electrode13and a mask for forming the second insulation layer. Therefore, the manufacturing method provided by the embodiments of the present disclosure further has the advantage of simple process on the basis that the accuracy of a detection result of the short circuit defect is improved.

For example, as shown inFIG. 11, the manufacturing method provided by the embodiment of the present disclosure further comprises: forming a plurality of the first signal lines12a, a plurality of the second signal lines12band a plurality of the initial pixel electrodes13′; the first signal lines12aand the second signal lines12bare alternately arranged, and the first signal line12aand the second signal line12bwhich are adjacent to each other are disposed between the adjacent initial pixel electrodes13′.

For example, the manufacturing method provided by at least one embodiment of the present disclosure further comprises: before removing the at least part of the first extension portion131of the initial pixel electrode13′, performing defect detection on the first signal line12aand the second signal line12bbetween the adjacent initial pixel electrodes13′. For example, the defect detection is defect detection of short circuits between the first signal line12aand the second signal line12b. The detection of the short circuit defects can refer to the related description above in combination withFIG. 2b, and repetitions are not repeated.

For example, a same first signal line12ais connected to a plurality of initial pixel electrodes13′, which is favorable for increasing a difference between the capacitance of the first signal line12adetected by the detection device and the capacitance of the second signal line12bdetected by the detection device in a short circuit detecting process.

After the short circuit detection is finished, the manufacturing method for the array substrate provided by the embodiments of the present disclosure further comprises the steps of forming the common electrode and the thin film transistor and the like, and these steps can refer to the embodiments about the manufacturing method, and will not be repeated.

At least one embodiment of the present disclosure further provides an array substrate, as shown inFIGS. 4band 5b, the array substrate comprises: the base substrate11; and the first signal line12aand the second signal line12bdisposed on the base substrate11, wherein the first signal line12aand the second signal line12bhave the same extension direction and are separated from each other; and the pixel electrode layer130disposed on the base substrate11, wherein the pixel electrode layer130includes the pixel electrode13and the remain portion131aseparated from the pixel electrode13, and the remain portion131ais connected to the first signal line12aand is separated from the second signal line12b.

For example, as shown inFIG. 5b, the array substrate provided by at least one embodiment of the present disclosure further comprises the common electrode15, disposed on one side of the pixel electrode13away from the base substrate11.

For example, as shown inFIGS. 7ato 7cor as shown inFIGS. 10aand 10b, the array substrate provided by at least one embodiment of the present disclosure further comprises the insulation layer14covering the pixel electrode layer, and the via hole14ais disposed in the insulation layer14; for example, an orthogonal projection of the via hole14ain the pixel electrode layer and the interval region131cbetween the pixel electrode13and the remain portion131aare overlapped (seeFIGS. 7ato 7c), or an orthogonal projection of part of the via hole14ain the pixel electrode layer and the interval region131cbetween the pixel electrode13and the remain portion131aare overlapped (seeFIGS. 10aand 10b).

For example, the via hole14ais located outside a region corresponding to the common electrode15. In this way, the common electrode and the pixel electrode are formed by a same etching treatment.

For example, as shown inFIG. 4bandFIG. 5b, the pixel electrode13includes the first protrusion portion131b, and the first protrusion portion131bis a protrusion protruding toward the first signal line12aconnected to the remain portion131a. For example, as shown inFIGS. 7ato 7cor as shown inFIGS. 10aand 10b, the via hole14ais located between the first protrusion portion131band the remain portion131a.

For example, the array substrate provided by at least one embodiment of the present disclosure further comprises the thin film transistor16disposed on the base substrate11, and the thin film transistor16includes the gate electrode16a, the source electrode16b, the drain electrode16cand the active layer16d.

For example, in a case of adopting the manner I in the manufacturing method for the array substrate, as shown inFIGS. 7ato 7c, the pixel electrode13further includes a second protrusion portion132; the pixel electrode13is connected to the drain electrode16cof the thin film transistor16by the second protrusion portion132, in other words, the second protrusion portion132of the pixel electrode13is connected to the drain electrode16cof the thin film transistor16.

For example, in a case of adopting the manner II in the manufacturing method for the array substrate, as shown inFIGS. 10aand 10b, the pixel electrode13is connected to the drain electrode16cof the thin film transistor16by the first protrusion portion131bthat the pixel electrode13includes, in other words, the first protrusion portion131bof the pixel electrode13is connected to the drain electrode16cof the thin film transistor16.

For example, as shown inFIG. 12, the array substrate provided by the embodiment of the present disclosure comprises a plurality of the first signal lines12a, a plurality of the second signal lines12b, a plurality of the pixel electrodes13and a plurality of the remain portions131a, the first signal lines12aand the second signal lines12bare alternately arranged, and the first signal line12aand the second signal line12bwhich are adjacent are arranged between the adjacent pixel electrodes13.

For example, a same first signal line12ais connected to a plurality of remain portions131a. In this way, in the manufacturing process, the first signal line12aare connected to a plurality of initial pixel electrodes, and therefore it is favorable for increasing a difference between the capacitance of the first signal line12adetected by the detection device and the capacitance of the second signal line12bdetected by the detection device in a short circuit detecting process.

At least one embodiment of the present disclosure further provides a display device, comprising the array substrate above.

For example, the display device is a liquid crystal panel, an OLED panel, an electronic paper, a cellphone, a tablet computer, a television, a display, a laptop, a digital photo frame, a navigator and any product or part having a display function.

According to the embodiments of the present disclosure, by designing the temporary initial pixel electrode, one of a group of signal lines is connected to the initial pixel electrode, which is equivalent to the increase of the area of the signal line, such that an obvious difference exists between detection results (for example, capacitances) of the two signal lines detected by the detection device, and further the detection accuracy of the defects (for example short circuit defect) between the two signal lines is improved; and after detection is finished, by removing part of the initial pixel electrode to form the pixel electrode, the functions of the pixel electrode and the signal line are prevented from being affected.

In addition, a common function of the via hole in the insulation layer is to realize connection among different parts. However, in at least one embodiment of the present disclosure, the via hole in the insulation layer is used for removing part of the initial pixel electrode to form the pixel electrode. Therefore, the embodiments of the present disclosure expand an application mode of the via hole.

The embodiments of the array substrate and the manufacturing method thereof and the embodiments of the display device mentioned above are mutually referable. In case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be inter-combined.

The foregoing embodiments merely are exemplary embodiments of the disclosure, and not intended to define the scope of the disclosure, and the scope of the disclosure is determined by the appended claims.

The application claims priority of Chinese Patent Application No. 201610620200.6 filed on Jul. 29, 2016, the disclosure of which is incorporated herein by reference in its entirety as part of the present application.