Semiconductor device with graphene encapsulated metal and method therefor

A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least one major surface of the first metal layer, and forming a second dielectric layer over the first metal layer and the first graphene layer. The method further includes forming an opening in the second dielectric layer which exposes the first metal layer, forming a second metal layer over the second dielectric layer and within the opening, and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening.

BACKGROUND

Field

This disclosure relates generally to semiconductor processing, and more specifically, to a semiconductor device with graphene encapsulated metal and methods for forming.

Related Art

As semiconductor technology advances, semiconductor devices continue to decrease in size. In conventional semiconductor device processing, barrier layers, such as tantalum nitride, are commonly used for interconnects in a semiconductor device to prevent the interconnect metal, such as copper, from reacting with the interlayer dielectrics. However, as sizes continue to shrink, the barrier layer thickness becomes a significant portion of the line width of the interconnect which increases the resistance of the interconnect. Therefore, a need exists for improved metal interconnects.

DETAILED DESCRIPTION

A metal having a surrounding graphene layer operates as a metal interconnect in a semiconductor structure. With the graphene, an additional barrier layer, such as TiN or TaN, is not needed if the metal chosen for the interconnect does not react with the interlayer dielectrics. For example, nickel surrounded by a graphene layer does not need a barrier layer since nickel does not react with silicon dioxide or low-k dielectrics (where k is the dielectric constant). While nickel has reduced conductivity as compared to copper, which is typically chosen as an interconnect metal, the conductivity of nickel is compensated with the higher conductivity of graphene. Furthermore, while copper has higher conductivity, a barrier layer is required, which, depending on its thickness as compared to the copper, can increase resistivity.

FIG. 1illustrates, in cross-sectional form, a semiconductor structure10at a stage in processing. Structure10includes a substrate12having a plurality of devices formed on an in substrate12, such as device16. The devices are isolated by isolation regions, such as isolation regions18. Structure10includes an interlayer dielectric layer (ILD)14over the devices. ILD14may be a silicon dioxide layer. Structure10includes a contact20extending through ILD14to a source/drain region of device16. Note that other contacts may be formed to other portions of device16or to other devices. A metal layer22is formed over ILD14. In one embodiment, metal layer22is nickel, and is blanket deposited over ILD14. In alternate embodiments metal layer22may be titanium, aluminum, or tungsten. Semiconductor substrate12described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.

FIG. 2illustrates, in cross-sectional form, semiconductor structure10at a subsequent stage in processing. Metal layer22is patterned, using, for example, a patterned masking layer, such as photoresist. Metal layer22is patterned, as needed, to form metal portion22within a metal interconnect layer. Metal portion22is a metal interconnect which can route signals as needed with the metal interconnect layer.

FIG. 3illustrates, in cross-sectional form, semiconductor structure10at a subsequent stage in processing. A graphene layer24is formed such that it surrounds the patterned metal portion22. For the discussions herein, it will be assumed that metal portion22is nickel. In one embodiment, to form graphene layer24, metal portion22is exposed to a growth process using a carbon-containing film such as acetylene or other carbon-containing gas. The carbon-containing gas may be part of a plasma, remote plasma, or chemical reaction process such that elemental carbon or carbon ions interact with the nickel. The carbon diffuses through the nickel and forms graphene on the outer surfaces of the nickel, once the carbon reaches its solid solubility limit in nickel. Excess carbon, which may not be in graphene form, such as graphite, is removed chemically, such as with the use of a plasma etch. Alternatively, to form graphene layer24, metal portion22is exposed to a plasma with some hydrogen and controlled amounts of methane. In another embodiment, to form graphene layer24, metal portion22is exposed to a carbon-containing paste. Another embodiment for the formation of graphene will be discussed in reference toFIGS. 11-16below. The formation of graphene in any of these embodiments can be performed at room temperature. In one embodiment, the graphene formation is performed at a temperature of -20 to 500 degrees Celsius. In one embodiment, it can be performed at a temperature in a range of 100 to 250 degrees Celsius.

FIG. 4illustrates, in cross-sectional form, semiconductor structure10at a subsequent stage in processing. An ILD26is formed over metal portion22and ILD14. In one embodiment, ILD36may subsequently be planarized.

FIG. 5illustrates, in cross-sectional form, semiconductor structure10at a subsequent stage in processing. A patterned masking layer28is formed over ILD26which includes an opening30which his located over metal portion22. That is, patterned masking layer defines a location where a conductive via will be formed to contact metal portion22. In one embodiment, patterned masking layer28is photo resist.

FIG. 6illustrates, in cross-sectional form, semiconductor structure10at a subsequent stage in processing. Opening30is extended through ILD26and through graphene24to form a via opening which exposes metal portion22. An etch can be performed to extend opening30through ILD26to stop on metal portion22. An etch stop layer is not needed if there is sufficient selectivity with the metal of metal portion22, such as when metal portion22is nickel.

FIG. 7illustrates, in cross-sectional form, semiconductor structure10at a subsequent stage in processing. A metal layer32is formed, such as by blanket deposition, over ILD26and within opening30. Note that in one embodiment, metal layer32is sufficiently thin that it does not fill opening30. In an alternate embodiment, metal layer32may be sufficiently thick to fill opening30. In one embodiment, metal layer32, like metal portion22, is nickel.

FIG. 8illustrates, in cross-sectional form, semiconductor structure10at a subsequent stage in processing. Metal layer32is patterned to result in a patterned metal portion32which operates as a metal interconnect to route signals between metal portion22to connections in the next metal interconnect layer.

FIG. 9illustrates, in cross-sectional form, semiconductor structure10at a subsequent stage in processing. A graphene layer36is formed such that it surrounds the patterned metal portion32. For the discussions herein, it will be assumed that metal portion32is nickel, and any technique used to form graphene layer24discussed herein can be used to form graphene layer36. Note that there is no barrier layer formed within opening30. In this manner, graphene layer24is in contact with graphene layer36within opening30.

FIG. 10illustrates, in cross-sectional form, semiconductor structure10at a subsequent stage in processing. An ILD38is formed over metal portion32and ILD26. Note that if metal portion32does not fill opening30, ILD30may leave a void40within opening30that does not get filled in. The void is located between ILD38and the section of metal portion32which extends through ILD26in opening30. Alternatively, ILD38completely fills opening30. In one embodiment, ILD38may subsequently be planarized.

Note that in this manner, metal layers can be patterned to form metal interconnects, such as metal portions22and32, to route signals as needed within structure10. A graphene layer is formed surrounding these metal portions to improve conductivity of the metal portions, which allows the metal portions to be formed of nickel (which has a higher resistivity than copper). The graphene-surrounded metal portions can be used in any metal layer of structure10, from metal layer 0 to the final metal layer. That is, the illustrated embodiments illustrate metal portions22and32in a particular metal layer as an example.

FIG. 11-16illustrate the formation of graphene layer24in accordance with an alternate embodiment of the present invention.FIG. 11illustrates a structure100at a stage in processing in which like numerals with structure10indicate like elements. Note that inFIG. 11, metal layer22has not yet been patterned, and it is again assumed metal layer22is nickel. After formation of metal layer22, an amorphous carbon anti-reflective coating (ARC) layer102is formed over metal layer22. In embodiment, ARC layer102is blanket deposited over metal layer22.

FIG. 12illustrates, in cross-sectional form, semiconductor structure100at a subsequent stage in processing. ARC layer102is a carbon layer or a carbon-containing layer in which, during deposition, the carbon drives into the nickel, thus forming a graphene layer104at the major surfaces of metal layer22. In one embodiment, graphene layer104is fully formed during the deposition of ARC layer102. In an alternate embodiment, after deposition of ARC layer102, structure100can be exposed to a high temperature to drive the carbon into the nickel to form graphene layer104. This temperature may be in a range of 100 to 500 degrees Celsius

FIG. 13illustrates, in cross-sectional form, semiconductor structure100at a subsequent stage in processing. An oxide layer103is formed over ARC layer102, and a patterned masking layer106is formed over oxide layer103. In one embodiment, oxide layer103is an oxide formed using tetraethyl orthosilicate (TEOS). Patterned masking layer106may be photoresist, and it corresponds to portion of metal layer22which will remain to form a metal interconnect.

FIG. 14illustrates, in cross-sectional form, semiconductor structure100at a subsequent stage in processing. Metal layer22, graphene104, ARC layer102, and oxide layer103are all patterned using patterned masking layer106. Therefore, ILD14is exposed on either side of patterned masking layer106.

FIG. 15illustrates, in cross-sectional form, semiconductor structure100at a subsequent stage in processing. Patterned masking layer106is removed. After removal of patterned masking layer106, an additional carbon driving step may be performed. For example, structure100may be exposed to a high temperature, such as 100 to 500 degrees Celsius, to further drive carbon into the nickel. Alternatively, the additional carbon driving may not be performed. Oxide layer103and ARC layer102are then removed. Removal of these layers also removes graphene104from the top surface of remaining metal portion22. Therefore, graphene104only remains between metal portion22and ILD14, and not on the top surface or side surfaces of metal portion22.

FIG. 16illustrates, in cross-sectional form, semiconductor structure100at a subsequent stage in processing. Since the graphene is removed from the top and side surfaces of metal portion22, a graphene layer108can again be formed surrounding metal portion22. In this case, graphene layer108is formed by exposing semiconductor structure100to a high temperature, such as 100 to 500 degrees Celsius. However, unlike the formation of graphene layer104, for the formation of graphene layer108, a carbon source, such as a plasma or paste, is not necessary because there is already carbon infused in the nickel previously provided by ARC layer102. Graphene layer108is formed on the top surface and side surfaces of metal portion22. Therefore, graphene layer104therefore becomes a part of graphene layer108which surrounds metal portion22. In an alternate embodiment, graphene layer108may not be formed, and only graphene layer104would remain. In this case, a graphene layer would be formed on only one major surface of metal portion22.

Processing can continue, as described above withFIGS. 4-10to form additional metal interconnects in any metal layer as needed. For example, an ILD layer can be formed over metal portion22and ILD14, with a via opening formed therein. In this via opening, another metal layer can be formed, with graphene surrounding the metal layer or below the metal layer using the processes described with respect toFIGS. 11-16. This metal layer may be used to form a metal interconnect with a conductive via extending through the ILD, similar to metal portion32and graphene layer36ofFIG. 9. Although the graphene layer may be formed on only the bottom major surface of a metal interconnect (such as if no additional carbon driving step is performed to form graphene layer108), the use of graphene still reduces the resistivity of the nickel. Also, no barrier is needed within via openings. In via openings, the graphene layer on the bottom surface of the metal interconnect would directly contact the underlying metal interconnect. Note that the use of ARC layer102can prevent reflective notching due to the surface topography of the via openings.

FIG. 17illustrates, in cross-sectional form, a semiconductor structure50including a number of graphene-cladded metal layers. That is, for each metal layer surrounded with graphene (as inFIGS. 1-10), or having a graphene layer on a least one major surface of the metal layer (as inFIGS. 11-16without the additional graphene formation after removal of the ARC layer), more than one layer may be formed. For example, as illustrated inFIG. 17, each metal layer described above can be formed as a stack of 4 metal layers (or any number greater than one). Structure50includes metal layers52,56,60, and64, each surrounded by a corresponding graphene layer54,58,62, and66. In one embodiment, alternating layers are formed of different metals. For example, metal layers52and60may be nickel and metal layers56and64may be aluminum. Any of the methods described above to form a graphene layer on or surrounding the metal layer may be used to form structure50.

Therefore, by now it can be understood how a graphene layer can be formed in combination with a metal interconnect within a semiconductor structure. The graphene allows the use of metals which may have reduced conductivity as compared to copper, such as nickel, because the graphene compensates for some of the loss conductivity. Furthermore, by allowing for the use of other metals, such as nickel, for the metal interconnects, barrier layers may be omitted thus resulting in reduced resistivity.

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, any number of metal layers with graphene of the same or different types of metal may be used to form each metal interconnect of a semiconductor structure. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

In one embodiment, a method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer; forming a first graphene layer on at least one major surface of the first metal layer; forming a second dielectric layer over the first metal layer and the first graphene layer; forming an opening in the second dielectric layer which exposes the first metal layer; forming a second metal layer over the second dielectric layer and within the opening; and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening. In one aspect of the embodiment, the first metal layer and the second metal layer comprise nickel. In another aspect, forming the first graphene layer on at least one major surface of the first metal layer includes exposing the first metal layer to a carbon-containing gas such that the carbon diffuses through the first metal layer to form the first graphene layer surrounding the first metal layer. In another aspect, forming the first graphene layer on at least one major surface of the first metal layer includes exposing the first metal layer to a carbon-containing paste such that the carbon diffuses through the first metal layer to form the first graphene layer surrounding the first metal layer. In another aspect, forming the first graphene layer on at least one major surface of the first metal layer includes forming an anti-reflective coating (ARC) layer over the first metal layer, wherein the ARC layer comprises carbon; and exposing the semiconductor structure to a temperature of at least −20 degrees Celsius such that the carbon is driven into the first metal layer from the ARC layer. In a further aspect, forming the first graphene layer on at least one major surface of the first metal layer include removing the ARC layer, wherein removing the ARC layer comprises removing the first graphene layer from a top surface of the first metal layer. In yet a further aspect, forming the first graphene layer on at least one major surface of the first metal layer includes after removing the first graphene layer from the top surface of the metal layer, exposing the semiconductor structure to a temperature of at least −20 degrees Celsius to form a third graphene layer on the top surface and side surfaces of the metal layer. In another aspect, the second metal layer and the second graphene layer do not completely fill the opening. In a further aspect, the method further includes forming a third dielectric layer over the second metal layer, the second graphene layer, and the opening, wherein a void is formed in the opening after formation of the third dielectric layer. In another aspect, the first graphene layer surrounds the first metal layer, and prior to forming the second dielectric layer, the method further includes forming a third metal layer over the first graphene layer; and forming a third graphene layer on at least one major surface of the third metal layer, wherein the first metal layer and the third metal layer are each a different metal and are separated by graphene. In a further aspect, the first metal layer is one of nickel, aluminum, titanium, or tungsten and the third metal layer is another one of nickel, aluminum, titanium, or tungsten. In another aspect, the first graphene layer surrounds the first metal layer and the second graphene layer surrounds the second metal layer, wherein the first graphene layer contacts the second graphene layer in the opening.

In another embodiment, a semiconductor structure includes a first metal interconnect over a first dielectric layer; a first graphene layer on at least one major surface of the first metal interconnect; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; and a second graphene layer on at least one major surface of the second metal interconnect. In one aspect of the another embodiment, the first metal interconnect and second metal interconnect comprise nickel. In another aspect, the semiconductor structure further includes a third dielectric layer over the second metal interconnect and second graphene layer; and a void between the third dielectric layer and a portion of the second metal interconnect which extends to the electrically contact the first metal layer. In another aspect, the first graphene layer surrounds the first metal interconnect and the second graphene layer surrounds the second metal interconnect. In a further aspect, the structure further includes a third metal interconnect with a third graphene layer surrounding the third metal interconnect, wherein the third graphene layer is on the first graphene layer, and wherein the first metal and the third metal are different metals. In another further aspect, the first metal interconnect is one of nickel or aluminum and the third metal interconnect is another one of nickel or aluminum.

In yet another embodiment, a method for forming a semiconductor structure, includes forming a first nickel layer over a first dielectric layer; forming a first graphene layer surrounding the first nickel layer; forming a second dielectric layer over the first nickel layer and the first graphene layer; forming an opening in the second dielectric layer which exposes the first nickel layer; forming a second nickel layer over the second dielectric layer and within the opening; and forming a second graphene layer surrounding the second nickel layer, wherein the first graphene layer is in contact with the second graphene layer within the opening. In one aspect of the yet another embodiment, forming the first graphene layer includes exposing the first nickel layer to a carbon-containing gas or paste such that the carbon diffuses through the first nickel layer to form the first graphene layer surrounding the first nickel layer.