Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate, a first gate structure, and a second gate structure. The substrate has a plurality of first fins and a plurality of second fins, wherein a first pitch between two adjacent first fins is greater than a second pitch between two adjacent second fins. The first gate structure crosses over the first fins. The second gate structure crosses over the second fins, wherein the second gate structure includes an upper portion having two first sidewalls substantially parallel to each other and a lower portion tapers toward the substrate.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth and has strived for higher device density, higher performance, and lower costs. However, problems involving both fabrication and design have been encountered. One solution to these problems has been the development of a fin-like field effect transistor (FinFET). A FinFET includes a thin vertical ‘fin’ formed in a free standing manner over a major surface of a substrate. The source, drain, and channel regions are defined within this fin. The transistor's gate wraps around the channel region of the fin. This configuration allows the gate to induce current flow in the channel from three sides. Thus, FinFET devices have the benefit of higher current flow and reduced short-channel effects.

The dimensions of FinFETs and other metal oxide semiconductor field effect transistors (MOSFETs) have been progressively reduced as technological advances have been made in integrated circuit materials. For example, high-k metal gate (HKMG) processes have been applied to FinFETs.

DETAILED DESCRIPTION

FIGS. 1-8, 10, 12, 14, 16, 18, and 20illustrate a method for manufacturing a semiconductor structure at various stages in accordance with some embodiments of the instant disclosure.

Reference is made toFIGS. 1-2. A substrate110having a plurality of first fins110aand a plurality of second fins110bis formed. The substrate110shown inFIG. 1is illustrated. The substrate110has a core region CR and a periphery region PR adjacent to the core region CR. For example, the periphery region PR surrounds the core region CR. The periphery region PR can be referred as an input/output (I/O) region. In some embodiments, the substrate110may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate110may be a wafer, such as a silicon wafer. An SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, a silicon substrate or a glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate110may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.

Please still referring toFIG. 1, a plurality of first photo-sensitive layers120are formed on the core region CR of the substrate110, and a plurality of second photo-sensitive layers130are formed on the periphery region PR of the substrate110. Although two first photo-sensitive layers120and two second photo-sensitive layers130are shown inFIG. 1, it should be clear that there are number of such “photo-sensitive layers” that are separated from one another. Moreover, it is noted that a first pitch p11between two adjacent first photo-sensitive layers120is greater than a second pitch p12between two adjacent second photo-sensitive layers130. In some embodiments, a width w11of the first photo-sensitive layer120is substantially equal to a width w11of the second photo-sensitive layer130. However, it is noted that the scope of this application is not limited thereto. The term “substantially” as used herein may be applied to modify any quantitative representation which could permissibly vary without resulting in a change in the basic function to which it is related.

In some embodiments, the photo-sensitive layers120and the second photo-sensitive layers130are formed by the following operations. A photo-sensitive layer is formed on the core region CR and the periphery region PR of the substrate110. The photo-sensitive layer is patterned, forming openings in the photo-sensitive layer, so that some regions of the substrate110are exposed, and thus the first photo-sensitive layers120and the second photo-sensitive layers130are formed.

Please referring toFIG. 2, the substrate110is etched through the first photo-sensitive layers120and the second photo-sensitive layers130to form the first fins110a, the second fins110b, first trenches T1adjacent to the first fins110a, and second trenches T2adjacent to the second fins110b. More specifically, a portion of the substrate110between neighboring first trenches T1forms the first fin110a, and a portion of the substrate110between neighboring second trenches T2forms the second fin110b. The first trenches T1and the second trenches T2may be trench strips (when viewed in the top view of the semiconductor structure) that are substantially parallel to each other. In some embodiments, a height of the first fin110ais substantially the same as a height of the second fin110b. Although two first fins110aand two second fins110bare shown, it should be clear that there are number of such “fins” that are separated from one another. In some other embodiments, the numbers of the first fins110aand the second fins110bcan be different. For example, the number of the second fins110bis greater than the number of the first fins110a. The number of the first fins110acan be less than or equal to 4, and the number of the second fins110bcan be greater than or equal to 12.

Because the substrate110is patterned by the first photo-sensitive layers120and the second photo-sensitive layers130, a first pitch p21between two adjacent first fins110ais greater than a second pitch p22between two adjacent second fins110b. In some embodiments, a fin width w21of the first fin110ais substantially equal to a fin width w22of the second fin110b. However, it is noted that the scope of this application is not limited thereto. In some other embodiments, the fin width w21of the first fin110ais substantially greater than the fin width w22of the second fin110b. In still some embodiments, the fin width w21of the first fin110ais substantially less than the fin width w22of the second fin110b. After forming the first fins110aand the second fins110b, the first photo-sensitive layers120and the second photo-sensitive layers130are removed.

Attention is now invited toFIG. 3. An isolation dielectric140is formed to cover the first fins110aand the second fins110b. The isolation dielectric140has a thickness t1. The isolation dielectric140may overfill the first trenches T1and the second trenches T2. The isolation dielectric140in the first trenches T1and the second trenches T2can be referred to as shallow trench isolation (STI) structure. In some embodiments, the isolation dielectric140is made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low-K dielectric materials. In some embodiments, the isolation dielectric140may be formed using a high-density-plasma (HDP) chemical vapor deposition (CVD) process, using silane (SiH4) and oxygen (O2) as reacting precursors. In some other embodiments, the isolation dielectric140may be formed using a sub-atmospheric CVD (SACVD) process or high aspect-ratio process (HARP), wherein process gases may include tetraethylorthosilicate (TEOS) and ozone (O3). In yet other embodiments, the isolation dielectric140may be formed using a spin-on-dielectric (SOD) process, such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). Other processes and materials may be used. In some embodiments, the isolation dielectric140can have a multi-layer structure, for example, a thermal oxide liner layer with silicon nitride formed over the liner. Thereafter, a thermal annealing may be optionally performed to the isolation dielectric140.

Reference is made toFIG. 4. The thickness t1of the isolation dielectric140is reduced to leave the isolation dielectric140covering top surfaces TS1of the first fins110aand top surfaces TS2of the second fins110b. In other words, reducing the thickness t1of the isolation dielectric140stops before the top surfaces TS1of the first fins110aand the top surfaces TS2of the second fins110bexpose. In other words, a portion of the isolation dielectric140outside the first trenches T1and the second trenches T2is removed without exposing the first fins110aand the second fins110b. The thickness t1of the isolation dielectric140shown inFIG. 3is reduced to a thickness t2of the isolation dielectric140shown inFIG. 4. In some embodiments, reducing the thickness t1of the isolation dielectric140is performed by chemical-mechanical planarization (CMP).

Please refer toFIG. 5. The isolation dielectric140covering the top surfaces TS1of the first fins110aand the top surfaces TS2of the second fins110bis etched to form a first isolation dielectric140abetween the first fins110aand a second isolation dielectric140bbetween the second fins110b. More specifically, etching the isolation dielectric140covering the top surfaces TS1of the first fins110aand the top surfaces TS2of the second fins110bstops until the top surfaces TS1and sidewalls SW1of the first fins110aand the top surfaces TS2and sidewalls SW2the second fins110bare exposed. In other words, etching the isolation dielectric140covering the top surfaces TS1of the first fins110aand the top surfaces TS2of the second fins110bincludes removing the isolation dielectric140above the top surfaces TS1of the first fins110aand the top surfaces TS2of the second fins110b, a portion of the isolation dielectric140between the first fins110a, and a portion of the isolation dielectric140between the second fins110b. After etching the isolation dielectric140, a portion of the first fin110ais higher than a top of the first isolation dielectric140a, and a portion of the second fin110bis higher than a top of the second isolation dielectric140b. Hence, this portion of the first fin110aprotrudes above the first isolation dielectric140a, and this portion of the second fin110bprotrudes above the second isolation dielectric140b. In some embodiments, etching the isolation dielectric140is performed by dry etching, wherein diluted HF, SiCoNi (including HF and NH3), or the like, may be used as the etchant.

As shown inFIG. 5, it is noted that the first isolation dielectric140abetween the first fins110ais thinner than the second isolation dielectric140bbetween the second fins110b. Accordingly, the top of the first isolation dielectric140ais below the top of the second isolation dielectric140b. Moreover, a first height h1from the top of at least one of the first fins110ato the top of the first isolation dielectric140ais greater than a second height h2from at least one of the top of the second fins110bto the top of the second isolation dielectric140b. In some embodiments, a height difference between the first height h1and the second height h2(h1−h2) is greater than about 3 nm. In some embodiments, the first fins110asubstantially level with the second fins110b.

Reference is made toFIG. 6. A gate dielectric layer150is blanket formed over the first fins110a, the second fins110b, the first isolation dielectric140a, and the second isolation dielectric140b. After the gate dielectric layer150is formed, a dummy gate electrode layer160is formed over the gate dielectric layer150. In some embodiments, the gate dielectric layer150is made of high-k dielectric materials, such as metal oxides, transition metal-oxides, or the like. Examples of the high-k dielectric material include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, or other applicable dielectric materials. In some embodiments, the gate dielectric layer150is an oxide layer. The gate dielectric layer150may be formed by a deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced CVD (PECVD) or other suitable techniques. In some embodiments, the dummy gate electrode layer160may include polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, or metals. In some embodiments, the dummy gate electrode layer160includes a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multi-layers thereof. The dummy gate electrode layer160may be deposited by CVD, physical vapor deposition (PVD), sputter deposition, or other techniques suitable for depositing conductive materials.

For clarity, in the followingFIGS. 7-17C, the gate dielectric layer150over the core region CR is referred to as a gate dielectric layer150a. The dummy gate electrode layer160over the core region CR is referred to as a dummy gate electrode layer160a. The gate dielectric layer150over the periphery region PR is referred to as a gate dielectric layer150b. The dummy gate electrode layer160over the periphery region PR is referred to as a dummy gate electrode layer160b.

Please refer toFIGS. 7-8. The dummy gate electrode layers160a,160b, and the gate dielectric layers150a,150b, are etched to form a plurality of first dummy gate structures DGS1and a plurality of second dummy gate structures DGS2. At least one of the first dummy gate structures DGS1includes the gate dielectric layer150aand the dummy gate electrode layer160a, and crosses the first fins110a. At least one of the second dummy gate structures DGS2includes the gate dielectric layer150band the dummy gate electrode layer160b, and crosses the second fins110b.

As shown inFIG. 7, a plurality of first mask layers170are formed on the dummy gate electrode layer160a, and a plurality of second mask layers180are formed on the dummy gate electrode layer160b. InFIG. 7, a width w31of at least one of the first mask layers170is less than a width w32of at least one of the second mask layers180. However, it is noted that the scope of this application is not limited thereto. In some other embodiments, a width w31of at least one of the first mask layers170is substantially equal to a width w32of at least one of the second mask layers180. In still some embodiments, a width w31of at least one of the first mask layers170is greater than a width w32of at least one of the second mask layers180. The first mask layers170and second mask layers180may be hard masks for protecting the underlying dummy gate electrode layer160a,160b, and the gate dielectric layer150a,150b, against subsequent etching process. The first mask layers170and second mask layers180may be formed by a series of operations including deposition, photolithography patterning, and etching processes. The photolithography patterning processes may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), and/or other applicable processes. The etching processes may include dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching).

As shown inFIG. 8, the dummy gate electrode layer160aand the gate dielectric layer150ais etched through the first mask layers170to form the first dummy gate structures DGS1wrapping portions of the first fins110a, and the dummy gate electrode layer160band the gate dielectric layer150bis etched through the second mask layers180to form the second dummy gate structures DGS2wrapping portions of the second fins110b. At least one of the first dummy gate structures DGS1includes a portion of the dummy gate electrode layer160aand a portion of the gate dielectric layer150acovered and protected by the first mask layer170. At least one of the second dummy gate structures DGS2includes a portion of the dummy gate electrode layer160band a portion of the gate dielectric layer150bcovered and protected by the second mask layer180. The first dummy gate structures DGS1and the second dummy gate structures DGS2have substantially parallel longitudinal axes that are substantially perpendicular to longitudinal axes of the first fins110aand the second fins110b. After forming the first dummy gate structures DGS1and the second dummy gate structures DGS2, the first mask layers170and the second mask layers180ofFIG. 7are removed. The first dummy gate structures DGS1and the second dummy gate structures DGS2will be replaced with replacement gate structures using a “gate-last” or replacement-gate process. Accordingly, the shape of the replacement gate structures can be determined by the shape of these dummy gate structures.

Further, because the width w31of at least one of the first mask layers170is less than the width w32of at least one of the second mask layers180, a width (i.e., gate length) w41of at least one of the first dummy gate structures DGS1is less than a width (i.e., gate length) w42of at least one of the second dummy gate structures DGS2. However, it is noted that the scope of this application is not limited thereto. The width w41and the width w42can be determined by the first mask layer170and the second mask layer180respectively. In some other embodiments, the width w41of at least one of the first dummy gate structures DGS1is equal to the width w42of at least one of the second dummy gate structures DGS2. In still some embodiments, the width w41of at least one of the first dummy gate structures DGS1is greater than the width w42of at least one of the second dummy gate structures DGS2.

Turning now toFIGS. 9A, 9B, and 9Cto further clarify the instant disclosure,FIGS. 9A, 9B, and 9Care cross-sectional views along the lines A-A′, B-B′, and C-C′ inFIG. 8respectively. As shown inFIGS. 9A-9C, the first height h1from the top of the first fin110ato the top of the first isolation dielectric140ais greater than the second height h2from the top of the second fin110bto the top of the second isolation dielectric140b. Moreover, the first isolation dielectric140aon the core region CR of the substrate110is thinner than the second isolation dielectric140bon the periphery region PR of the substrate110.

Please refer toFIGS. 7 and 8again. The dummy gate electrode layer160aand the gate dielectric layer150aare etched through the first mask layers170and the second mask layers180to form the first dummy gate structures DGS1and the second dummy gate structures DGS2until both the first isolation dielectric140aand the second isolation dielectric140bexpose. It is noted that, because the first isolation dielectric140ais thinner than the second isolation dielectric140b, the second isolation dielectric140bis exposed earlier than the first isolation dielectric140a. When etching the dummy gate electrode layer160aand the gate dielectric layer150ato form the lower portions of the first dummy gate structures DGS1, lower portions of the second dummy gate structures DGS2is continuously etched (or trimmed). Accordingly, the resulting second dummy gate structures DGS2have lower portions tapering toward the substrate110. In other words, footings of second dummy gate structures DGS2have notched profile.

When a dummy gate structure is formed to cross over fins, if a pitch between two adjacent fins is small, it is not easy to form the dummy gate structure with predetermined shape, especially the footing of the dummy gate structure. One skilled in the art should understand that the footing profile of the dummy gate structure will influence the subsequent process of forming a replacement gate structure, and thus is a factor for breakdown voltage (VBD) performance. It is noted that, the footings of second dummy gate structures DGS2of the instant disclosure have notched profile; therefore, the second dummy gate structures DGS2of the instant disclosure have upper portions wider than lower portions. Therefore, after the second dummy gate structures DGS2is removed to form gate trenches, the gate trenches have a good filling performance with replacement gate structures, reducing the possibility of breakdown between gate and source/drain.

Please refer toFIGS. 9B-9C. InFIG. 9B, it can be seen that the first dummy gate structure DGS1has two sidewalls SW1asubstantially parallel to each other. However, inFIG. 9C, only a portion of the second dummy gate structure DGS2has parallel sidewalls. More specifically, the second dummy gate structure DGS2includes an upper portion DU having two first sidewalls SWU1bsubstantially parallel to each other and a lower portion DL tapers toward the substrate110. Moreover, a top width w51of the lower portion DL is greater than a bottom width w52of the lower portion DL. Based on the above, it can be seen that, because the thickness of the first isolation dielectric140ais less than the thickness of the second isolation dielectric140b, the first height h1from the top of the first fin110ato the top of the first isolation dielectric140ais greater than the second height h2from the top of the second fin110bto the top of the second isolation dielectric140b. Accordingly, dummy gate structures with different shapes can be formed concurrently in the core region CR and the periphery region PR respectively.

Still referring toFIG. 9C, the lower portion DL has second sidewalls SWL1b, and the second sidewalls SWL1bare substantially straight. However, it is noted that the scope of this application is not limited thereto. In some other embodiments, the second sidewalls SWL1bare concave. InFIG. 9C, the lower portion DL is below the top surface TS2of the second fin110b. The lower portion DL has a top surface substantially leveling with the top surface TS2of the second fins110b. However, it is noted that the scope of this application is not limited thereto. In some other embodiments, the lower portion DL has a top surface above the top surface TS2of the second fin110b. In still some other embodiments, the lower portion DL has a top surface below the top surface TS2of the second fin110b.

Attention is now invited toFIGS. 10 and 11A-11C.FIGS. 11A, 11B, and 11Care cross-sectional views along the lines A-A′, B-B′, and C-C′ inFIG. 10respectively. First gate spacers190aare conformally formed on the opposite sidewalls SW1aof first dummy gate structures DGS1, and second gate spacers190bare conformally formed on the opposite sidewalls SW1b, of second dummy gate structures DGS2. As shown inFIG. 11B, a pair of first gate spacers190aconformally covers sidewalls SW1aof the first dummy gate structure DGS1. As shownFIG. 11C, a pair of second gate spacers190bconformally covers the first sidewalls SWU1bof the upper portion DU of the second dummy gate structure DGS2and second sidewalls SWL1bof the lower portion DL of the second dummy gate structure DGS2. At least one of the second gate spacers190bhas a slanted portion SP in contact with one of the second sidewalls SWL1bof the lower portion DL of the second dummy gate structure DGS2.

In some embodiments, the first gate spacers190aand the second gate spacers190bmay include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, porous dielectric materials, hydrogen doped silicon oxycarbide (SiOC:H), low-k dielectric materials or other suitable dielectric material. The first gate spacers190aand the second gate spacers190bmay include a single layer or multilayer structure made of different dielectric materials. The method of forming the first gate spacers190aand the second gate spacers190bincludes blanket forming a dielectric layer on the structure shown inFIG. 8using, for example, CVD, PVD or ALD, and then performing an etching process such as anisotropic etching to remove horizontal portions of the dielectric layer. The remaining portions of the dielectric layer on the sidewalls SW1aof the first dummy gate structures DGS1can serve as the first gate spacers190a, and the remaining portions of the dielectric layer on the sidewalls SW1bof the second dummy gate structures DGS2can serve as the second gate spacers190b. In some embodiments, the first gate spacers190aand the second gate spacers190bmay be used to offset subsequently formed doped regions, such as source/drain regions. The first gate spacers190aand the second gate spacers190bmay further be used for designing or modifying the source/drain region profile.

Reference is made toFIGS. 12 and 13A-13C.FIGS. 13A, 13B, and 13Care cross-sectional views along the lines A-A′, B-B′, and C-C′ inFIG. 12respectively. Portions of the first fins110anot covered by the first dummy gate structures DGS1and first gate spacers190a, and portions of the second fins110bnot covered by the second dummy gate structures DGS2and the second gate spacers190bare respectively partially removed (or partially recessed) to form first recesses R1and second recesses R2. After this removal, at least one of remaining first fins110amay have protruding portions110a1and embedded portions110a2, and at least one of remaining second fins110bmay have protruding portions110b1and embedded portions110b2. The embedded portions110a2are embedded in the first isolation dielectric140a, and exposed by the first recesses R1. The protruding portion110a1protrudes from the embedded portions110a2and is located between the first recesses R1. The embedded portions110b2are embedded in the second isolation dielectric140b, and exposed by the second recesses R2. The protruding portion110b1protrudes from the embedded portions110b2and is located between the second recesses R2. The first dummy gate structures DGS1wrap the protruding portions110a1and the second dummy gate structures DGS2wrap the protruding portions110b1, and hence the protruding portions110a1and the protruding portions110b1can act as channel regions of transistors. The embedded portions110a2spaced apart from the first dummy gate structures DGS1and the embedded portions110b2spaced apart from the second dummy gate structures DGS2can act as source/drain regions of transistors.

Formation of the first recesses R1and the second recesses R2may include a dry etching process, a wet etching process, or combination of dry and wet etching processes. This etching process may include reactive ion etch (RIE) using the first dummy gate structures DGS1, the first gate spacers190a, the second dummy gate structures DGS2, and the second gate spacers190bas masks, or by other suitable removal process.

Reference is made toFIGS. 14 and 15A-15C.FIGS. 15A, 15B, and 15Care cross-sectional views along the lines A-A′, B-B′, and C-C′ inFIG. 14respectively. First epitaxial source/drain structures200aare respectively formed in the first recesses R1, and second epitaxial source/drain structures200bare respectively formed in the second recesses R2. The first epitaxial source/drain structures200aand the second epitaxial source/drain structures200bmay be formed using one or more epitaxy or epitaxial (epi) processes, such that Si features, SiGe features, silicon phosphate (SiP) features, silicon carbide (SiC) features and/or other suitable features can be formed in a crystalline state on the embedded portions110a1of the first fins110aand the embedded portions110b1of the second fins110brespectively. As shown inFIGS. 15A and 15C, the second epitaxial source/drain structure200bis over one of the second fins110b, and has a footing portion FP in contact with the slanted portion SP of at least one of the second gate spacers190b. In some embodiments, lattice constants of the first epitaxial source/drain structures200aand the second epitaxial source/drain structures200bare different from that of the first fins110aand the second fins110b, so that the channel region between the first epitaxial source/drain structures200acan be strained or stressed by the first epitaxial source/drain structures200a, the channel region between the second epitaxial source/drain structures200bcan be strained or stressed by the second epitaxial source/drain structures200bto improve carrier mobility of the semiconductor structure and enhance the performance of the semiconductor structure.

The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the semiconductor fin150(e.g., silicon, silicon germanium, silicon phosphate, or the like). The first epitaxial source/drain structures200aand the second epitaxial source/drain structures200bmay be in-situ doped. The doping species include P-type dopants, such as boron or BF2; N-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the first epitaxial source/drain structures200aand the second epitaxial source/drain structures200bare not in-situ doped, a second implantation process (i.e., a junction implant process) is performed to dope the first epitaxial source/drain structures200aand the second epitaxial source/drain structures200b. One or more annealing processes may be performed to activate the first epitaxial source/drain structures200aand the second epitaxial source/drain structures200b. The annealing processes include rapid thermal annealing (RTA) and/or laser annealing processes.

Reference is made toFIGS. 16 and 17A-17C.FIGS. 17A, 17B, and 17Care cross-sectional views along the lines A-A′, B-B′, and C-C′ inFIG. 16respectively. A contact etch stop layer (CESL)210is blanket formed on the structure shown inFIG. 14, and an interlayer dielectric (ILD) layer220is formed on the CESL210. A CMP process may be optionally performed to remove excessive material of the ILD layer220and the CESL210to expose the first dummy gate structures DGS1and the second dummy gate structures DGS2. The CMP process may planarize a top surface of the ILD layer220with top surfaces of the first dummy gate structures DGS1, the first gate spacers190a, the second dummy gate structures DGS2, and the second gate spacers190b, and the CESL210in some embodiments. The CESL210includes silicon nitride, silicon oxynitride or other suitable materials. The CESL210can be formed using, for example, plasma enhanced CVD, low pressure CVD, ALD or other suitable techniques. The ILD layer220may include a material different from the CESL210. In some embodiments, the ILD layer220may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The ILD layer220may be formed using, for example, CVD, ALD, spin-on-glass (SOG) or other suitable techniques.

Please refer toFIGS. 18 and 20. The first dummy gate structures DGS1are replaced with first gate structures GS1, and the second dummy gate structures DGS2are replaced with second gate structures GS2. As such, as shown inFIG. 20, a semiconductor structure100is formed. The semiconductor structure100may be intermediate structures fabricated during processing of an integrated circuit, or portion thereof, that may include static random access memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as P-channel field effect transistors (PFET), N-channel FET (NFET), metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.

Attention is now invited toFIGS. 18 and 19A-19C.FIGS. 19A, 19B, and 19Care cross-sectional views along the lines A-A′, B-B′, and C-C′ inFIG. 18respectively. The first dummy gate structures DGS1is removed to form gate trenches GT1with the first gate spacers190aas its sidewalls, and the second dummy gate structures DGS2is removed to form gate trenches GT2with the second gate spacers190bas its sidewalls. As shown inFIG. 19B, the exposed sidewalls of the first gate spacers190aare substantially straight. Therefore, the gate trench GT1has substantially straight sidewalls. Further, a portion of the protruding portion110a1of the first fin110ais exposed. As shown inFIG. 19C, the gate trench GT2has an upper trench portion UP and a lower trench portion LP in communication with each other. The upper trench portion UP has substantially straight sidewalls, and the sidewalls substantially parallel to each other. The lower trench portion LP tapers toward the second isolation dielectric140b(or the periphery region PR of the substrate110). InFIG. 19C, the sidewalls of the lower trench portion LP are substantially straight. However, it is noted that the scope of this application is not limited thereto. In some other embodiments, the sidewalls of the lower trench portion LP are convex. Further, a portion of the protruding portion110b1of the second fin110bis exposed. InFIG. 19C, the lower trench portion LP of the gate trench GT2is below the top surface TS2of the second fin110b. The lower trench portion LP has a top substantially leveling with the top surface TS2of the second fins110b. However, it is noted that the scope of this application is not limited thereto. In some other embodiments, the lower trench portion LP has a top above the top surface TS2of the second fin110b. In still some other embodiments, the lower trench portion LP has a top below the top surface TS2of the second fin110b.

In some embodiments, the first dummy gate structures DGS1and the second dummy gate structures DGS2are removed by performing a first etching process and performing a second etching process after the first etching process. In some embodiments, the dummy gate electrode layers160a,160bare mainly removed by the first etching process, and the gate dielectric layers150a,150bare mainly removed by the second etching process. In some embodiments, the first etching process is a dry etching process and the second etching process is a wet etching process. In some embodiments, the dry etching process includes using an etching gas such as CF4, Ar, NF3, Cl2, He, HBr, O2, N2, CH3F, CH4, CH2F2, or combinations thereof. In some embodiments, the dry etching process is performed at a temperature in a range from about 20° C. to about 80° C. In some embodiments, the dry etching process is performed at a pressure in a range from about 1 mTorr to about 100 mTorr. In some embodiments, the dry etching process is performed at a power in a range from about 50 W to about 1500 W.

Attention is now invited toFIGS. 20 and 21A-21C.FIGS. 21A, 21B, and 21Care cross-sectional views along the lines A-A′, B-B′, and C-C′ inFIG. 20respectively.FIGS. 20 and 21A-21Cillustrate formation of replacement gates. The first gate structures GS1and the second gate structure GS2are respectively formed in the gate trenches GT1and GT2. Accordingly, the first gate structures GS1crosses over the first fins110a, and the second gate structures GS2crosses over the second fins110b. Exemplary method of forming these gate structures may include the following operations. A gate dielectric layer including a gate dielectric layer230aand a gate dielectric layer230bis blanket formed in the gate trenches GT1and the gate trenches GT2, and over the first gate spacers190a, the second gate spacers190b, CESL210, and ILD layer220. A work function conductor including a work function conductor240aand a work function conductor240bis conformally formed over the gate dielectric layer. A layer of filling conductor including a filling conductor250aand a filling conductor250bis conformally formed over the work function conductor. A CMP process is performed to remove excessive materials of the gate dielectric layer230a,230b, the work function conductor240a,240b, and the filling conductor250a,250boutside the gate trenches GT1and GT2. The resulting structure is shown inFIG. 20. In some embodiments, the work function conductor240ais a multi-layer structure. In some embodiments, the work function conductor240bis a multi-layer structure.

In some embodiments, the gate dielectric layer230a,230bmay respectively include, for example, a high-k dielectric material such as metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, or combinations thereof. In some embodiments, the gate dielectric layer230a,230bmay respectively include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitrides (SiON), and combinations thereof. In alternative embodiments, the gate dielectric layer230a,230bmay respectively have a multilayer structure such as one layer of silicon oxide (e.g., interfacial layer) and another layer of high-k material. The formation of the gate dielectric layer230a,230bmay include molecular-beam deposition (MBD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like.

The work function conductors240a,240bover the gate dielectric layers230a,230brespectively include work function metals to provide a suitable work function for the gate structures GS1, GS2. In some embodiments, the work function conductors240a,240bmay respectively include one or more n-type work function metals (N-metal) for forming an n-type transistor on the substrate110. The n-type work function metals may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and/or other suitable materials. In alternative embodiments, the work function conductors240a,240bmay respectively include one or more p-type work function metals (P-metal) for forming a p-type transistor on the substrate110. The p-type work function metals may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials.

Still referring toFIG. 20, at least one of the first gate structures GS1has a first gate length gl1. At least one of the second gate structures GS2has a second gate length gl2. The first gate length gl1is less than the second gate length gl2. However, it is noted that the scope of this application is not limited thereto. In some other embodiments, the first gate length gl1is greater than the second gate length gl2. In still some other embodiments, the first gate length gl1is substantially equal to the second gate length gl2.

As shown inFIGS. 20 and 21A-21C, the semiconductor structure100includes a substrate110, the first gate structures GS1, the second gate structures GS2, the first gate spacers190a, the second gate spacers190b, the contact etch stop layer210, the interlayer dielectric layer220, the first epitaxial source/drain structures200a, and the second epitaxial source/drain structures200b. The substrate110has the core region CR and the periphery region PR adjacent to the core region CR. The core region CR of substrate110has the first fins110a. The periphery region PR has the second fins110b. As shown inFIG. 21A, the first pitch p21between two adjacent first fins110ais greater than the second pitch p22between two adjacent second fins110b. Moreover, the first isolation dielectric140ais between the first fins110a. The second isolation dielectric140bis between the second fins110b. The first isolation dielectric140ais thinner than the second isolation dielectric140b.

As shown inFIG. 20, at least one of the first gate structures GS1crosses over the first fins and includes the gate dielectric layer230a, the work function conductor240a, and the filling conductor250a. As shown inFIG. 21B, the first gate structure GS1has two sidewalls SW2asubstantially parallel to each other. A pair of the first gate spacers190aconformally covers the sidewalls SW2aof the first gate structure GS1. As shown inFIG. 20, each second gate structure GS2crosses over the second fins110b, and includes the gate dielectric layer230b, the work function conductor240b, and the filling conductor250b. As shown inFIG. 21C, the second gate structure GS2includes an upper portion GU and a lower portion GL, and has two sidewalls SW2b. Each sidewall SW2bincludes first sidewalls SWU2band second sidewalls SWL2b. The upper portion GU has two first sidewalls SWU2bsubstantially parallel to each other, and a lower portion GL tapers toward the periphery region PR of the substrate110(or the second isolation dielectric140b). A top width w61of the lower portion GL is greater than a bottom width w62of the lower portion GL. InFIG. 21C, the lower portion GL has two second sidewalls SWL2b, and the second sidewalls SWL2bare substantially straight. However, it is noted that the scope of this application is not limited thereto. In some other embodiments, the second sidewalls SWL2bare concave. A pair of the second gate spacers190bconformally covers the first sidewalls SWU2bof the upper portion GU and the second sidewalls SWL2bof the lower portion GL. At least one of the second gate spacers190bhas the slanted portion SP in contact with one of the sidewalls SWL2bof the lower portion GL of the second gate structure GS2.

Still referring toFIG. 20, the pairs of the first gate spacers190across over the first fins110a. In each pair of the first gate spacers190a, the gate trench GT1is between two first gate spacers190a. As shown in21B, the gate trench GT1has sidewalls substantially parallel to each other. The first gate structure GS1is disposed in the gate trench GT1. More specifically, the gate dielectric layer230aof the first gate structure GS1is conformally disposed in the gate trench GT1and covers the sidewalls and bottom surface of the gate trench GT1. The work function conductor240aof the first gate structure GS1is conformally disposed on the gate dielectric layer230a. The filling conductor250aof the first gate structure GS1is conformally disposed on the work function conductor240a.

Still referring toFIG. 20, the pairs of the second gate spacers190bcross over the second fins110b. In each pair of the second gate spacers190b, the gate trench GT2is between two second gate spacers190b. As shown in21C, the gate trench GT2has the upper trench portion UP and the lower trench portion LP in communication with each other. The upper trench portion UP has substantially straight sidewalls, and the sidewalls substantially parallel to each other. The lower trench portion LP tapers toward the second isolation dielectric140b(or the periphery region PR of the substrate110). The second gate structure GS2is disposed in the gate trench GT2. More specifically, the gate dielectric layer230bof the second gate structure GS2is conformally disposed in the gate trench GT2, and covers the sidewalls of the upper trench portion UP of the gate trench GT2and the sidewalls and bottom surface of the lower trench portion LP of the gate trench GT2. The work function conductor240bof the second gate structure GS2is conformally disposed on the gate dielectric layer230b. The filling conductor250bof the second gate structure GS2is conformally disposed on the work function conductor240b.

Please refer toFIGS. 19C and 21Csimultaneously. As previously described inFIG. 19C, the lower trench portion LP of the gate trench GT2is below the top surface TS2of the second fin110b. The lower trench portion LP has the top substantially leveling with the top surface TS2of the second fins110b. Therefore, the lower portion GL of the second gate structure GS2(i.e., the portion of the second gate structure GS2filled in the lower trench portion LP) is below the top surface TS2of the second fin110b. The lower portion GL of the second gate structures GS2has a top surface substantially leveling with the top surface TS2of the second fin110b. However, it is noted that the scope of this application is not limited thereto. In some other embodiments, the lower portion GL of the second gate structures GS2has a top surface above the top surface TS2of the second fin110b. In still some other embodiments, the lower portion GL of the second gate structures GS2has a top surface below the top surface TS2of the second fin110b.

Embodiments of the instant disclosure may have at least following advantages. The dummy gate structures on the periphery region of the substrate have upper portions wider than lower portions. Accordingly, when replacing the dummy gate structures with the gate structures, the shape of gate trenches formed after removing the dummy gate structures may be advantageous to fill the gate structures and enlarge breakdown voltage (VBD) between gate structures and source/drain.

In some embodiments of the instant disclosure, a semiconductor structure includes a substrate, a first gate structure, and a second gate structure. The substrate has a plurality of first fins and a plurality of second fins, wherein a first pitch between two adjacent first fins is greater than a second pitch between two adjacent second fins. The first gate structure crosses over the first fins. The second gate structure crosses over the second fins, wherein the second gate structure includes an upper portion having two first sidewalls substantially parallel to each other and a lower portion tapers toward the substrate.

In some embodiments of the instant disclosure, a semiconductor structure includes a substrate, a first isolation dielectric, a second isolation dielectric, a first gate structure, and a second gate structure. The substrate has a core region and a periphery region, wherein the core region has a plurality of first fins, the periphery region has a plurality of second fins, and the first fins and the second fins have substantially the same height. The first isolation dielectric is between the first fins. The second isolation dielectric is between the second fins, wherein the first isolation dielectric is thinner than the second isolation dielectric. The first gate structure crosses over the first fins. The second gate structure crosses over the second fins. The first gate structure has a first gate length, the second gate structure has a second gate length, and the first gate length is less than the second gate length.

In some embodiments of the instant disclosure, a method of manufacturing a semiconductor structure includes forming a substrate having a plurality of first fins and a plurality of second fins, wherein a first pitch between two adjacent first fins is greater than a second pitch between two adjacent second fins, forming an isolation dielectric covering the first fins and the second fins, reducing a thickness of the isolation dielectric to leave the isolation dielectric covering top surfaces of the first fins and the second fins, etching the isolation dielectric covering the top surfaces of the first fins and the second fins to form a first isolation dielectric between the first fins and a second isolation dielectric between the second fins, and forming a first gate structure crossing over the first fins and a second gate structure crossing over the second fins.