Semiconductor packages having through electrodes and methods for fabricating the same

Semiconductor packages having through electrodes and methods for fabricating the same are provided. The method may comprise providing a first substrate including a first circuit layer, forming a front mold layer on a front surface of the first substrate, grinding a back surface of the first substrate, forming a first through electrode that penetrates the first substrate to be electrically connected to the first circuit layer, providing a second substrate on the back surface of the first substrate, the second substrate including a second circuit layer that is electrically connected to the first through electrode, forming a back mold layer on the back surface of the first substrate, the back mold layer encapsulating the second substrate, and removing the front mold layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. nonprovisional patent application claims benefit under 35 U.S.C. §119 of Korean Patent Application 10-2013-0071775 filed on Jun. 21, 2013, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present inventive concept relates to semiconductor and, more particularly, to semiconductor packages having through electrodes and methods for fabricating the same.

Through electrodes allow for accomplishing high performance semiconductor packages. Application of the through electrode to the semiconductor package generally results in grinding a wafer to which a carrier is bonded with an adhesive layer interposed between the carrier and wafer. Because the carrier process is needed for having through electrodes to the semiconductor packages, there are problems such as decrease of productivity and increase of cost.

SUMMARY

Therefore, its is an aspect of an example embodiment to provide a method of making a semiconductor device, the method including: providing a substrate including a first active layer on a front surface of a wafer; and forming a first mold layer on the first active layer to provide rigidity to the substrate, the first mold layer including a polymer material; thinning the substrate by removing a first back surface of the substrate after forming the first mold layer, to expose a second back surface, the substrate being held in place during the thinning by removably attaching the first mold layer to a device without using an adhesive; and forming pads on the thinned substrate, the pads being electrically connected to through electrodes in the substrate.

The device may be removably attached to the first mold layer without bonding the device to the first mold layer.

The device may be removably attached to the first mold layer without using an adhesive between the device and the first mold layer.

The thinning the first back surface of the substrate may include removing the first back surface using a mechanical process.

The thinning the first back surface of the substrate may include grinding the first back surface of the substrate.

In an example embodiment, the method may further include forming the through electrodes in the thinned substrate.

In another example embodiment, the method may further include stacking a chip on the second back surface of the thinned substrate, an active layer of the chip facing the second back surface of the thinned substrate.

In yet another example embodiment, the method may further include: forming a second mold layer on the chip to encapsulate the chip to provide rigidity to the substrate; and removing at least a portion of the first mold layer after forming the second mold layer to form a smooth planar surface.

In one example embodiment the method further includes: cutting the first and the second mold layers and the substrate to form a semiconductor package so that any one of a width of the first mold layer of the semiconductor package and a width of the second mold layer of the semiconductor package, and a width of the substrate of the semiconductor package is substantially greater than a width of the chip.

The width of the first mold layer of the semiconductor package, the width of the second mold layer of the semiconductor package, and the width of the substrate of the semiconductor package may be substantially same.

The second mold layer may not be disposed between the chip and the substrate.

In the thinning the substrate, the device may be a vacuum chuck which directly holds and is in direct contact with the first mold layer.

In the removing at least a portion of the first mold layer, the second mold layer may be directly held by and may be in direct contact with a vacuum chuck.

A coefficient of thermal expansion (CTE) of the first mold layer and a CTE of the substrate may be within an order of magnitude.

A ratio of the coefficient of thermal expansion (CTE) of the first mold layer and a CTE of the substrate may be in a range from 3 to 1.

The first active layer may be a circuit layer.

In an example embodiment, there is a method of making a semiconductor device, the method including: providing a substrate including a first active layer on a front surface of the wafer; and forming a first mold layer on the first active layer to provide rigidity to the substrate, the first mold layer including a polymer material; thinning the substrate by removing a first back surface of the substrate after forming the first mold layer, to expose a second back surface; forming through electrodes in the thinned substrate, the through electrodes being electrically connected to the first active layer; and forming pads on the thinned substrate, the pads being electrically connected to the through electrodes in the substrate.

The device may be removably attached to the first mold layer without bonding the device to the first mold layer.

The device may be removably attached to the first mold layer without using an adhesive between the device and the first mold layer.

The thinning the first back surface of the substrate may include removing the first back surface using a mechanical process.

The thinning the first back surface of the substrate may include grinding the first back surface of the substrate.

In an example embodiment, the method may further include: stacking a chip on the second back surface of the thinned substrate, an active layer of the chip facing the second back surface of the thinned substrate.

In another example embodiment, the method further includes: forming a second mold layer on the chip to encapsulate the chip to provide rigidity to the substrate; and removing at least a portion of the first mold layer after forming the second mold layer to form a smooth planar surface.

In yet another example embodiment the method further includes: cutting the first and the second mold layers and the substrate to form a semiconductor package so that any one of a width of the first mold layer of the semiconductor package and a width of the second mold layer of the semiconductor package, and a width of the substrate of the semiconductor package is substantially greater than a width of the chip.

The width of the first mold layer of the semiconductor package, the width of the second mold layer of the semiconductor package, and the width of the substrate of the semiconductor package may be substantially same.

The second mold layer may not be disposed between the chip and the substrate.

In the thinning the substrate, the device may be a vacuum chuck which directly holds and may be in direct contact with the first mold layer.

In the removing at least a portion of the first mold layer, the second mold layer may be directly held by and may be in direct contact with a vacuum chuck.

A coefficient of thermal expansion (CTE) of the first mold layer and a CTE of the substrate may be within an order of magnitude.

A ratio of the coefficient of thermal expansion (CTE) of the first mold layer and a CTE of the substrate may be in a range from 3 to 1.

In an example embodiment, there is a semiconductor device including: a first mold layer including a first polymer material; a first active layer disposed on the first mold layer; a substrate disposed on the first active layer, the substrate having through electrodes formed therein, the through electrodes electrically connected to the first active layer; pads formed on the substrate and electrically connected to the through electrodes; a chip disposed above the substrate, a second active layer of the chip facing the substrate and electrically connected to the pads; and a second mold layer covering at least a portion of the chip, the second mold layer providing rigidity to the substrate and including a second polymer material; wherein a width of the substrate is greater than a width of the chip.

The chip may be encapsulated by the second mold layer.

Sidewalls of the substrate and sidewalls of the first active layer may not be covered by the second mold layer.

A coefficient of thermal expansion (CTE) of the first mold layer and a CTE of the substrate may be within an order of magnitude.

A ratio of the coefficient of thermal expansion (CTE) of the first mold layer and a CTE of the substrate may be in a range from 3 to 1.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIGS. 1A to 1Jare cross sectional views illustrating a method for fabricating a semiconductor package according to exemplary embodiments.FIG. 1Dis a modified exemplary embodiment ofFIG. 1B.

Referring toFIG. 1A, there may be provided a wafer-level chip190including an active layer formed on a wafer101. In an exemplary embodiment, the active layer is a circuit layer103but is not limited thereto. The wafer101may comprise a semiconductor substrate (e.g., silicon substrate) having a front surface101aand a first back surface101b. At least one bump105may be provided on the front surface101aof the wafer-level chip109to be electrically connected to the circuit layer103. The circuit layer103may comprise an integrated circuit such as a memory circuit, a logic circuit, and a combination thereof, and further comprise at least one front pad104electrically connected to the elements within the circuit layer103. The bump105may be directly or indirectly coupled to the front pad104so as to be electrically connected to the circuit layer103.

Referring toFIG. 1B, a front mold layer111may be formed on the wafer-level chip190and the wafer101may be worked to be thinner. For example, the front mold layer111may be formed on the front surface101aof the wafer101and then the wafer101may be grinded. In some exemplary embodiments, the first back surface101bof the wafer101may be grinded by a grinder90so that the wafer101is supported by the front mold layer111. This wafer backside grinding process may reduce a thickness of the wafer101to expose a second back surface101c. In an exemplary embodiment, the wafer101maybe thinned using a thinning process such as a mechanical process. In this specification, the front surface101amay correspond to an active surface and the second back surface may correspond to an inactive surface.

The front mold layer111may have a thickness sufficient enough to provide rigidity or stiffness to the wafer101so the wafer101does not bend, flex, deform, or the like, and is held in place when the wafer backside grinding process is performed. Hereinafter, bending will be mentioned, but the exemplary embodiments are not limited thereto and may include flexing, deforming, warping and the like. The front mold layer111may comprise insulator, for example, high molecular substance such as epoxy resin. The epoxy resin may have a coefficient of temperature expansion (CTE) of about 50 to about 80 ppm/° C. and silicon constituting the wafer101may have about 3 ppm/° C. Due to the mismatch in CTE between the wafer101and the front mold layer111, the wafer101may suffer from the warpage. Hence, the front mold layer111may comprise an epoxy filler composite including epoxy resin mixed with silica (e.g., content of about 80 wt %) as a filler and having a CTE of about 5 to 7 ppm/° C. The front mold layer111may have the CTE similar to that of silicon such that the warpage of the wafer101may be prevented or reduced. In an exemplary embodiment, the CTE of the wafer101and the CTE of the front mold layer111would be in the same order of magnitude, e.g., both CTEs would be between 1-10 ppm/° C. Alternatively, the ratio of the CTE of the first mold layer111to the CTE of the wafer101and would be in a range from 3 to 1.

In some exemplary embodiments, the front mold layer111may support the wafer101during the wafer backside grinding process such that there may be no need to attach a carrier to the wafer101with an adhesive layer between the wafer101and the carrier. In other words, the front mold layer111may act as the carrier during the wafer backside grinding process. Moreover, the front mold layer111may have the CTE similar to that of the wafer101such that the wafer101may be free of damage due to the warpage.

In an exemplary embodiment, the front mold layer111provides rigidity or stiffness to the overall wafer-level chip109including the circuit layer103and the wafer101. In the wafer grinding process, the wafer-level chip109, specifically, the front mold layer111, is held by a device such as a vacuum chuck or other devices to provide rigidity or stiffness to prevent bending. In an exemplary embodiment, the vacuum chuck directly holds and is in direct contact with the front mold layer111.

The device may be removably attached to the front mold layer111without using an adhesive. In an exemplary embodiment, the device is removably attached without bonding the device to the front mold layer111. In yet another exemplary embodiment, the device may be removably attached to the front mold layer111without using an adhesive between the device and the front mold layer111.

Referring toFIG. 1C, there may be formed at least one through electrode121that penetrates the wafer101to be electrically connected to the circuit layer103. In other words, the through electrode121may be a through silicon via (TSV). For example, the inactive surface101cof the wafer101may be dry-etched or drilled to form at least one vertical hole120, and the vertical hole120may be filled with conductor such as tungsten or copper to form the through electrode121. The tungsten or copper constituting the through electrode121may be formed by an electroplating process or a deposition process. At least one back pad123may be further formed on the inactive surface101cof the wafer101to be electrically connected to the through electrode121. The back pad123and the through electrode121may be formed simultaneously or separately. For example, an electroplating process may be performed to form the through electrode121and the back pad123at the same time. In this case, the back pad123and the through electrode121may constitute a single structure. As another example, the through electrode121may be formed by a first process (e.g., an electroplating process), and thereafter the back pad123may be formed by a second process (e.g., a deposition process) different from the first process.

Alternatively, as illustrated inFIG. 1D, the wafer101may comprise the through electrode121that partially penetrates the wafer101and does not reach the first back surface101b. The front mold layer111may be formed on the front surface101aof the wafer101, and the first back surface101bof the wafer101may be grinded by the grinder90in a state that the wafer101is supported by the front mold layer111. The wafer backside grinding process may be performed to emerge the second back surface101cthat exposes the through electrode121. The back pad123as illustrated inFIG. 1Cmay be formed on the second back surface101cto be coupled to the through electrode121.

In some exemplary embodiments, the through electrode121may be formed after the wafer backside grinding process (Via Last scheme), as illustrated inFIG. 1C, or before the wafer backside grinding process (Via First or Via Middle scheme), as illustrated inFIG. 1D. As described above, exemplary embodiments may be compatible with any one of the Via First, Via Middle and Via Last schemes.

Referring toFIG. 1E, a plurality of chips200may be stacked on the wafer-level chip190. Each of the chips200may comprise a substrate201having an active surface201aand an inactive surface201c, a circuit layer203disposed on the active surface201a, and at least one bump205formed on the circuit layer203to be electrically connected thereto. For example, the chips200may be stacked in a flip-chip manner so that the active surface201aof the substrate201faces the inactive surface101cof the wafer101. The wafer101may be upside down such that the inactive surface101cmay face upward. The chip200may be electrically connected to the circuit layer103of the wafer101by the bump205coupled to the through electrode121. The circuit layer203of the chip200may comprise an integrated circuit such as a memory circuit, a logic circuit, and a combination thereof. The substrate201may be a chip-level semiconductor wafer. The bump205of the chip200may be vertically aligned with the through electrode121or may not be vertically aligned. The back pad123may be redistributed to electrically connect the through electrode121to the bump205vertically misaligned with the through electrode121.

Referring toFIG. 1F, a back mold layer211may be formed on the inactive surface101cof the wafer101so as to encapsulate the chips200, and the front mold layer111may be removed. In an exemplary embodiment, the second mold layer211provides rigidity to the resultant structure, including the wafer101. The back mold layer211may comprise epoxy filler composite identical or similar to that of the front mold layer111. The front mold layer111may be removed by a grinding process, a chemical mechanical polishing process, or an etching process. In an exemplary embodiment, a smooth planar surface is thus formed. In some exemplary embodiments, the front mold layer111may be grinded by the grinder90until a portion of the bump105is exposed. Therefore, the active surface101aor the circuit layer103may be covered with the front mold layer111that is partially removed, yet fills spaces between adjacent bumps105. As described inFIG. 1B, a device such as a vacuum chuck or other devices may be removably attached to the back mold layer211in a similar manner when the front mold layer111is being grinded. In an exemplary embodiment, the vacuum chuck directly holds and is in direct contact with the back mold layer211.

Referring toFIG. 1G, at least one second bump107may be attached to the at least one bump105to form at least one external terminal109. The second bump107may be formed by reflowing solder paste provided on the bump105. The solder paste may be provided by an evaporation process, an electrolytic plating process, an electroless plating process, a ball drop process, a screen printing process, and the like. Through the processes mentioned above, there may be fabricated a wafer-level package1including the plurality of chips200stacked on the wafer-level chip190. The wafer-level package1may be selectively packaged as described later.

Referring toFIG. 1H, a dicing process may be performed on the wafer-level package1. For example, a blade95or laser may divide the back mold layer211between adjacent chips200, the wafer101, and the front mold layer111. Due to the dicing process, the wafer-level chip190may be separated into a plurality of chips100as illustrated inFIG. 1I.

Referring toFIG. 1I, the dicing process may separate the wafer-level package1into a plurality of chip-level semiconductor packages11including the chip200(referred to as a slave chip) stacked on the chip100(referred to as a master chip). The master chip100may have a width greater than that of the slave chip200. The master chip100may be formed by the dicing process performed on the wafer101such that lateral sides100sof the master chip100may be exposed. Differently, the slave chip200may be encapsulated by the back mold layer211such that lateral sides200sof the slave chip200may be not exposed. The front mold layer111may serve as a protection layer to cover the circuit layer103of the master chip100. In an exemplary embodiment, the wafer-level package1is formed so that any one of a width of the front mold layer111and a width of the back mold layer211, and a width of the cut wafer101of the wafer-level package1is substantially greater than a width of the slave chip200. In yet another exemplary embodiment, the width of the front mold layer111, the width of the back mold layer211, and the width of the cut wafer101of the waver-level package1are substantially same.

According to embodiments of the present invention, the semiconductor package11may have a back-to-front structure where the inactive surface101c(or back side) of the master chip100faces the active surface201a(or front side) of the slave chip200. The bump205of the slave chip200may be coupled to the through electrode121of the master chip100, which may electrically connect the slave chip200to the master chip100. The external terminal109may protrude from the front mold layer111to easily electrically connect the semiconductor package11to any electrical apparatus such as a semiconductor chip, a semiconductor package, a printed circuit board, a module substrate, and so forth. In one exemplary embodiment, the back mold layer211is not disposed between the slave chip200and the cut wafer101.

Referring toFIG. 1J, the semiconductor package11may be mounted on a package substrate80to fabricate a semiconductor package12. For example, the semiconductor package12may be fabricated by mounting the semiconductor package11on a front surface80aof the package substrate80such as a printed circuit board and forming an outer mold layer83to encapsulate the semiconductor package11. At least one solder ball85may be attached to a back surface80bof the package substrate80. The master chip100may be encapsulated by the front mold layer111, the back mold layer211and the outer mold layer83. The slave chip200may be dually encapsulated by the back mold layer211and the outer mold layer83enclosing the back mold layer211. The semiconductor package11may be electrically connected to the package substrate80by the external terminal109and electrically connected to any electrical apparatus (e.g., a semiconductor chip, a semiconductor package, a module substrate) by the solder ball85.

FIGS. 2A to 2Dare cross sectional views illustrating a method for fabricating a semiconductor package according to exemplary embodiments of the present inventive concepts. For concise description, previously described elements may be identified by similar or identical reference numbers without repeating overlapping descriptions thereof.

Referring toFIG. 2A, the plurality of chips200may be stacked on the wafer-level chip190and the front mold layer111may be removed. For example, identical or similar to the descriptions with reference toFIGS. 1A to 1F, the front mold layer111may be formed on the active surface101aof the wafer101and then the wafer101may be grinded, the through electrode121and the back pad123may be formed and then the plurality of chips200may be mounted in the flip-chip manner on the inactive surface101cof the wafer101, and thereafter the back mold layer211may be formed to encapsulate the chips200and then the front mold layer111may be removed. In some embodiments, chemical capable of selectively etching the front mold layer111may be provided to remove the front mold layer111.

Referring toFIG. 2B, the removal of the front mold layer111may fabricate a wafer-level package2including the plurality of chips200mounted in the flip-chip manner on the inactive surface101cof the wafer101. In some embodiments, the front mold layer111may be completely removed to make the bump105entirely exposed. Alternatively, the front mold layer111may be partially removed to remain on the active surface101aor the circuit layer103. In this case, the remained mold layer111may have a thickness less than the height of the bump105so that the bump105may protrude from the remained front mold layer111.

Referring toFIG. 2C, the wafer-level package2may be divided into a plurality of semiconductor packages21including the slave chip200stacked on the master chip100. The semiconductor package21may have a back-to-front structure where the inactive surface101c(or back side) of the master chip100faces the active surface201a(or front side) of the slave chip200. In some embodiments, the bump105may be so protruded that there may be no need to form a second bump attached to the bump105.

Referring toFIG. 2D, the semiconductor package21may be mounted on the front surface80aof the package substrate80(e.g., printed circuit board) and the outer mold layer83may be formed to encapsulate the semiconductor package21, which fabricates a semiconductor package22. The master chip100may be encapsulated by the back mold layer211and the outer mold layer83. The slave chip200may be dually molded by the back mold layer211and the outer mold layer83.

FIGS. 3A to 1Hare cross sectional views illustrating a method for fabricating a semiconductor package according to exemplary embodiments of the present inventive concepts.FIGS. 3I and 3Jare modified exemplary embodiments ofFIGS. 3A and 3G, respectively. For concise description, previously described elements may be identified by similar or identical reference numbers without repeating overlapping descriptions thereof.

Referring toFIG. 3A, the plurality of chips200may be stacked on the wafer-level chip190. For example, identical or similar to the descriptions with reference toFIGS. 1A to 1E, the front mold layer111may be formed on the active surface101aof the wafer101and then the wafer101may be grinded, and thereafter the through electrode121and the back pad123may be formed and then the plurality of chips200may be mounted on the inactive surface101cof the wafer101. The chip200may comprise the substrate201including the front surface201aand a first back surface201b, the circuit layer203disposed on the substrate201, and the bump205provided on the circuit layer203. The chip200may be mounted in the flip-chip manner on the inactive surface101cof the wafer101and electrically connected to the circuit layer103of the wafer101by the bump205coupled to the through electrode121.

Referring toFIG. 3B, the back mold layer211may be formed on the wafer-level chip190and then the chips200may be thinned. For example, the back mold layer211may be formed on the wafer-level chip190in order to encapsulate the chips200and then the chips200may be grinded. The back mold layer211may cover or expose the first back surface201bof the chip200. The chip200may be grinded by a grinding process using the grinder90or a chemical mechanical polishing process. Due to the grinding of the chip200, the first back surface201bof the chip200may be grinded to emerge a second surface201c(referred to as an inactive surface). The back mold layer211may be grinded together with the chip200to have a shape encapsulating the chip200but exposing the inactive surface201cof the chip200. The back mold layer211may fill spaces between the adjacent chips200and between the chips200and the wafer101.

Referring toFIG. 3C, at least one through electrode221may be formed to penetrate the substrate201of the chip200so as to be electrically connected to the circuit layer203. For example, the inactive surface201cof the chip200may be dry-etched or drilled to form at least one vertical hole220, and the vertical hole220may be filled with conductor such as tungsten or copper to form the through electrode221. The tungsten or copper constituting the through electrode221may be formed by an electroplating process or a deposition process. At least one back pad223may be further formed on the inactive surface201cof the chip200to be connected to the through electrode221. The back pad223and the through electrode221may be formed simultaneously using a same process (e.g., electroplating process). Therefore, the back pad223and the through electrode221may constitute a single structure. Alternatively, the back pad223and the through electrode221may be formed separately using different processes. Differently, the chip200may comprise the through electrode221formed by the Via First or Via Middle scheme, as illustrated inFIG. 1D. In this case, the chip200may be grinded to expose the through electrode221and then the back pad223may be formed to be coupled to the through electrode221.

Referring toFIG. 3D, a plurality of chips300may be mounted on the inactive surfaces201cof the chip200s. The chip200(referred to as a first slave chip) and the chips300(referred to as a second slave chip) may be in a one-to-one correspondence. The second slave chip300may comprise a substrate301including an active surface301aand an inactive surface301c, a circuit layer303disposed on the substrate301, and at least one bump305provided on the circuit layer303. The second slave chip300may be mounted in the flip-chip manner on the inactive surface201cof the first slave chip200and the bump305may be coupled to the through electrode221, which may electrically connect the second slave chip300to the first slave chip200. The circuit layer303of the second slave chip300may comprise an integrated circuit such as a memory circuit, a logic circuit, and a combination thereof. The substrate301of the second slave chip300may be a chip-level semiconductor wafer.

Referring toFIG. 3E, a second back mold layer311may be formed to encapsulate the second slave chips300and then the front mold layer111may be removed. For example, the front mold layer111may be grinded by the grinder90so as to expose the bump105. A portion of the front mold layer111may remain on the active surface101aof the wafer101and fill spaces between adjacent bumps105. Alternatively, the front mold layer111may be completely removed using chemical, as illustrated inFIG. 2A. Differently, the front mold layer111may remain on the active surface101aof the wafer101, as illustrated inFIG. 2B. In this case, the bump105may protrude from the remained front mold layer111.

Referring toFIG. 3F, a wafer-level package3may be fabricated by attaching the second bump107to the bump105in order to form the external terminal109. The wafer-level package3may comprise the first and second slave chips200and300mounted in the flip-chip manner on the wafer-level chip190.

Referring toFIG. 3G, a dicing process may be performed on the wafer-level package3. The dicing process may separate the wafer-level package3into a plurality of semiconductor packages31including the first and second slave chips200and300mounted in the flip-chip manner on the master chip100. When the dicing process is performed, the wafer101may be divided into the plurality of master chips100. The semiconductor package31may have a first back-to-front structure between the master chip100and the first slave chip200and a second back-to-front structure between the first slave chip200and the second slave chip300. The bump205of the first slave chip200may be coupled to the through electrode121of the master chip100, which electrically connects the first slave chip200to the master chip100. The bump305of the second slave chip300may be coupled to the through electrode221of the first slave chip200, which electrically connects the second slave chip300to the first slave chip200.

The master chip100may have a width greater than those of the first and second slave chips200and300. The first slave chip200may have a width identical or similar to that of the second slave chip300. The master chip100may be formed by the dicing process performed on the wafer101such that the lateral sides100sof the master chip100may be exposed. Differently, the first slave chip200may be encapsulated by the back mold layer211and the second slave chip300may be encapsulated by the second back mold layer311, so that lateral sides200sand300sof the first and second slave chips200and300may be not exposed.

Referring toFIG. 3H, the semiconductor package31may be mounted on the front surface80aof the package substrate80(e.g., printed circuit board) and the outer mold layer83may be formed to encapsulate the semiconductor package31, which fabricates a semiconductor package32. The master chip100may be encapsulated by the back mold layer211, the second back mold layer311and the outer mold layer83. The first slave chip200may be molded by the outer mold layer83which surrounds the first and second mold layers211and311. The second slave chip300may be dually encapsulated by the second back mold layer311and the outer mold layer83.

Alternatively, as illustrated inFIG. 3I, an upper wafer-level chip290may be stacked on the wafer-level chip190. The upper wafer-level chip290may comprise an upper wafer201on which the circuit layer203and the bump205are provided. The upper wafer201may be stacked on the wafer101in a state that an active surface201aof the upper wafer201faces the inactive surface101cof the wafer101. A first back surface201bof the upper wafer201may be grinded to emerge the inactive surface201c, as illustrated inFIG. 3B.

Processes, identical or similar to those as illustrated inFIGS. 3B to 3G, may be performed to fabricate a semiconductor package31aincluding the first and second slave chips200and300stacked in the flip-chip manner on the master chip100. The master chip100may be formed by the dicing process performed on the wafer101such that the lateral sides100sof the master chip100may be exposed. Similarly, the first slave chip200may be formed by the dicing process performed on the upper wafer201such that the lateral sides200sof the first slave chip200may be exposed. Differently, the second slave chip300may be encapsulated by the second back mold layer311such that the lateral sides300sof the second slave chip300may be not exposed. Identically or similarly to the semiconductor package32as illustrated inFIG. 3H, the semiconductor package31amay be mounted on the package substrate80and encapsulated by the outer mold layer83.

FIGS. 4A to 4Eare cross sectional views illustrating a method for fabricating a semiconductor package according to exemplary embodiments of the present inventive concepts. For concise description, previously described elements may be identified by similar or identical reference numbers without repeating overlapping descriptions thereof.

Referring toFIG. 4A, a plurality of the semiconductor packages11may be stacked on the wafer-level chip190. For example, identical or similar to the descriptions with reference toFIGS. 1A to 1C, the front mold layer111may be formed on the active surface101aof the wafer101and then the wafer101may be grinded, and thereafter the through electrode121and the back pad123may be formed. The plurality of the semiconductor packages11ofFIG. 1Imay be stacked on the inactive surface101cof the wafer101. The external terminal109of the semiconductor package11may be coupled to the through electrode121of the wafer-level chip190such that the semiconductor package11may be electrically connected to the wafer-level chip190.

Referring toFIG. 4B, the back mold layer211may be formed on the inactive surface101cof the wafer101so as to encapsulate the semiconductor packages11and then the front mold layer111may be removed. The front mold layer111may be removed by a grinding process using the grinder90or an etching process using chemical. For example, the front mold layer111may be grinded by the grinder90and the bump105may be exposed through the grinded front mold layer111.

Referring toFIG. 4C, the second bump107may be attached to the bump105to form an external terminal109a, which may fabricate a wafer-level package4. The wafer-level package4may comprise the plurality of the semiconductor packages11mounted on the wafer-level chip190.

Referring toFIG. 4D, a dicing process may be performed on the wafer-level package4to fabricate a semiconductor package41including the semiconductor package11mounted on the master chip100formed from the divided wafer101. In some embodiments, the lateral sides100sof the master chip100may be exposed and the semiconductor package11may be encapsulated by the back mold layer211.

Referring toFIG. 4E, the semiconductor package41may be mounted on the front surface80aof the package substrate80(e.g., printed circuit board) and the outer mold layer83may be formed to encapsulate the semiconductor package41, which fabricates a semiconductor package42. The master chip100may be encapsulated by the front mold layer111, the back mold layer211and the outer mold layer83. The semiconductor package11may be dually molded by the back mold layer211and the outer mold layer83molding the back mold layer211.

FIGS. 5A to 5Eare cross sectional views illustrating a method for fabricating a semiconductor package according to exemplary embodiments of the present inventive concepts. For concise description, previously described elements may be identified by similar or identical reference numbers without repeating overlapping descriptions thereof.

Referring toFIG. 5A, an upper wafer-level package295may be stacked on the wafer-level package190. For example, identical or similar to the descriptions with reference toFIGS. 1A to 1C, the front mold layer111may be formed on the active surface101aof the wafer101, the wafer101may be grinded, and then the through electrode121and the back pad123may be formed. A wafer251(referred to as an upper wafer) having a circuit layer253may be stacked on the inactive surface101cof the wafer101(referred to as lower wafer). The upper wafer251may comprise a semiconductor substrate (e.g., silicon substrate) having an active surface251aand an inactive surface251c. At least one bump255may be provided on the active surface251aof the upper wafer251to be electrically connected to the circuit layer253. The upper wafer251may be stacked on the lower wafer101in a state that the active surface251aof the upper wafer251faces the inactive surface101cof the lower wafer101.

Referring toFIG. 5B, the back mold layer211may be formed on the inactive surface101cof the lower wafer101so as to encapsulate the upper wafer-level chip295and then the front mold layer111may be removed. The front mold layer111may be grinded by the grinder90until the bump105is exposed. Alternatively, the front mold layer111may be completely removed using chemical, as illustrated inFIG. 2A. Differently, the front mold layer111may remain on the active surface101aof the lower wafer101, as illustrated inFIG. 2B.

Referring toFIG. 5C, the second bump107may be attached to the bump105to form the external terminal109. Through the processes mentioned above, there may be fabricated a wafer-level package5including the upper wafer-level chip295molded by the back mold layer211and stacked on the wafer-level chip190.

Referring toFIG. 5D, a dicing process may be performed on the wafer-level package5to fabricate a semiconductor package51including a slave chip250formed from the divided upper wafer251, mounted on the master chip100. The lateral sides100sof the master chip100may be exposed and lateral sides250sof the slave chip250may be also exposed.

Referring toFIG. 5E, the semiconductor package51may be mounted on the front surface80aof the package substrate80(e.g., printed circuit board) and the outer mold layer83may be formed to encapsulate the semiconductor package51, which fabricates a semiconductor package52. The master chip100may be encapsulated by the front mold layer111, the back mold layer211and the outer mold layer83. The slave chip250may be surrounded by the back mold layer211and the outer mold layer83.

FIGS. 6A to 6Dare cross sectional views illustrating a method for fabricating a semiconductor package according to exemplary embodiments of the present inventive concepts. For concise description, previously described elements may be identified by similar or identical reference numbers without repeating overlapping descriptions thereof.

Referring toFIG. 6A, the plurality of chips200may be stacked on the wafer-level chip190. For example, identical or similar to the descriptions with reference toFIGS. 1A to 1E, the front mold layer111may be formed on the active surface101aof the wafer101and then the wafer101may be grinded, and thereafter the through electrode121and the back pad123may be formed and then the plurality of chips200may be mounted on the inactive surface101cof the wafer101. In some embodiments, the wafer-level chip190may not comprise a bump which is provided on the active surfaced101aof the wafer101to be electrically connected on the front pad104.

Referring toFIG. 6B, the back mold layer211may be formed on the wafer-level chip190and then the front mold layer111may be removed by a grinding process, a chemical mechanical polishing process or an etching process. In some embodiments, the front mold layer111may be grinded by the grinder90until the front pad104is exposed.

Referring toFIG. 6C, the removal of the front mold layer111may fabricate a wafer-level package6including the plurality of chips200stacked on the wafer-level chip190. The bump205may be coupled to the through electrode121such that the chips200may be electrically connected to the wafer-level chip190.

Referring toFIG. 6D, a dicing process may be performed on the wafer-level package6to form a plurality of chip stacks195. The chip stack195may be mounted on a package substrate70(e.g., printed circuit board) to fabricate a semiconductor package61. For example, a bonding pad74may be formed to be coupled to the front pad104and the chip stack195may be mounted on a front surface70aof the package substrate70. An adhesive layer71may be interposed between the chip stack195and the package substrate70. The chip stack195may comprise the slave chip200stacked in the flip-chip manner on the master chip100formed from the divided wafer101.

At least one solder ball75may be attached to a back surface70bof the package substrate70. In some embodiments, the package substrate70may comprise a window70wthat opens a center portion of the chip stack195. The chip stack195may be electrically connected to the package substrate70by a bonding wire72passing through the window70wto be coupled to the bonding pad74. The window70wmay be filled with a mold layer73that encapsulates the bonding wire72. The bonding wire72may be settled and protected by the mold layer73.

FIG. 7Ais a schematic block diagram illustrating an example of memory cards including a semiconductor package according to exemplary embodiments of the present inventive concepts.FIG. 7Bis a schematic block diagram illustrating an example of information process system including a semiconductor package according to exemplary embodiments of the present inventive concepts.

Referring toFIG. 7A, a semiconductor memory1210including the semiconductor device1according to exemplary embodiments of the inventive concepts is applicable to a memory card1200. For example, the memory card1200may include a memory controller1220generally controlling data exchange between a host1230and the flash memory device1210. An SRAM1221is used as a work memory of a processing unit1222. A host interface1223has a data exchange protocol of a host connected to the memory card1200. An error correction coding block1224detects and corrects errors of data that are read from the multi-bit flash memory device1210. A memory interface1225interfaces the semiconductor memory device1210according to the example embodiments. The processing unit1222generally controls data exchange of the memory controller1220. The memory1210may comprise at least one of the semiconductor packages according to exemplary embodiments of the inventive concepts.

Referring toFIG. 7B, an information processing system1300may include a memory system1310having at least one of the semiconductor packages according exemplary embodiments of the inventive concepts. The information processing system1300includes a mobile device or a computer. For example, the information processing system1300may include a modem1320, a central processing unit1330, a RAM1340, and a user interface1350electrically connected to the memory system1310via a system bus1360. The memory1310may include a memory1311and a memory controller1312and have substantially the same configuration as that of the memory card1200inFIG. 7A. The memory system1310stores data processed by the central processing unit1330or data input from the outside. The information process system1300may be provided as a memory card, a solid state disk, a semiconductor device disk, a camera image sensor, and other application chipsets. In some embodiments, the memory system1310may be used as a portion of a solid state drive (SSD), and in this case, the information processing system1300may stably and reliably store a large amount of data in the memory system1310.

According to embodiments of the present invention, attaching and detaching of carrier are not needed when the wafer grinding process is performed, so that productivity is raised and process cost is reduced. Because the mold layer has a coefficient of temperature expansion (CTE) similar to that of the wafer, warpage of the wafer can be prevented or reduced and process inferiority can be suppressed. The present invention is compatible with any one of Via First, Via Middle and Via Last.