Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

TECHNICAL FIELD

The present disclosure relates generally to analog-to-digital converters, and more particularly, to multichannel analog-to-digital converters.

BACKGROUND

Multichannel analog-to-digital converters (ADCs) can receive and convert multiple analog signals into corresponding digital signals. Typically, various performance and/or device metrics (such as signal-to-noise ratio, throughput, device footprint, and/or testing time) are balanced to achieve optimal multichannel analog-to-digital conversion. For example, a multichannel ADC that achieves optimal signal-to-noise ratio and throughput may occupy a larger than desirable device footprint, while a multichannel ADC that achieves optimal device footprint often suffers from signal-to-noise ratio and throughput losses. Accordingly, although multichannel ADCs have been generally adequate at balancing various performance and/or device metrics, they have not been entirely satisfactory in all respects.

OVERVIEW OF EXAMPLE EMBODIMENTS

Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. The multichannel SAR ADCs and associated methods and systems described herein can optimally balance various ADC performance and/or device metrics, including signal-to-noise ratio, throughput (such as analog-to-digital conversion speeds), device area, and/or other performance and/or device metric.

An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC and a multiplexer shared among the plurality of input channels. The first SAR ADC can receive a respective analog input signal from a respective input channel. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The multichannel SAR ADC can further include a residue amplifier coupled to the second SAR ADC and the multiplexer, where the residue amplifier is configured to amplify the selected residue analog signal. In various implementations, the second SAR ADC and the multiplexer may be shared among all of the plurality of input channels. In various implementations, where the multichannel SAR ADC includes N input channels, the second SAR ADC and the multiplexer may be shared among b channels of the N input channels, the multiplexer is configured to select the analog residue signal from one of the first SAR ADCs associated with the b channels. The multichannel SAR ADC may include N/b second SAR ADCs, multiplexers, and/or residue amplifiers, such that each second SAR ADC performs conversion for b channels.

In various implementations, the first SAR ADCs are configured to generate in parallel a respective first digital signal and a respective analog residue signal from the respective analog input signal, and the second SAR ADC is configured to serially generate second digital signals from the respective analog residue signals. In some implementations, the first SAR ADCs are configured to resolve a first few bits of an analog input signal, and the second SAR ADC is configured to resolve remaining bits of the analog input signal. The first SAR ADCs may directly sample respective analog input signals. In various implementations, the first SAR ADCs include a first comparator, a first digital-to-analog converter (DAC), and a first SAR controller; and the second SAR ADC includes a second comparator, a second DAC, and a second SAR controller. Each first SAR ADC can generate the respective first digital signal by comparing the respective analog input signal with a respective first DAC reference voltage; and the second SAR ADC can generate the second digital signal for each channel by comparing each respective analog residue signal with a second DAC reference voltage. In various implementations, multichannel SAR ADC further includes a mini-ADC coupled to the first SAR ADC for each of the plurality of input channels. In various implementations, where the first SAR ADC is configured to perform a p-bit analog-to-digital conversion, the mini-ADC can be configured to generate x bits of the p-bit analog-to-digital conversion.

An exemplary method for performing multichannel successive approximation register (SAR) analog-to-digital conversion includes performing a first SAR analog-to-digital conversion on a plurality of analog input signals; selecting an analog residue signal from among the first SAR analog-to-digital conversions; and performing a second SAR analog-to-digital conversion on the selected analog residue signal. The method can further comprise amplifying the selected analog residue signal. The method can further include directly sampling the plurality of analog input signals. In various implementations, the analog residue signal can be selected from among all of the first SAR analog-to-digital conversions. In various implementations, where the plurality of analog input signals includes N analog input signals, the analog residue signal can be selected from among b of the first SAR analog-to-digital conversions. In various implementations, performing the first SAR analog-to-digital conversions includes generating in parallel a respective first digital signal and a respective analog residue signal from a respective analog input signal; and performing the first SAR analog-to-digital conversions includes serially generating second digital signals from the respective analog residue signals. In various implementations, where the first SAR analog-to-digital conversion is a p-bit analog-to-digital conversion, the method can further include performing an analog-to-digital conversion to generate x bits of the p-bit analog-to-digital conversion.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various multichannel analog-to-digital (ADC) converters are disclosed herein. The multichannel ADCs, and associated methods and systems described herein, can optimally balance various ADC performance and/or device metrics, including signal-to-noise ratio, throughput (such as analog-to-digital conversion speeds), device area, and/or other performance and/or device metric.

FIG. 1is a simplified schematic circuit diagram of an exemplary multichannel analog-to-digital converter (ADC)100according to various aspects of the present disclosure. Multichannel ADC100is an electronic device (including an electronic circuit and/or one or more electronic components) configured to receive and convert an analog input signal into a digital output signal. The digital output signal can represent an n-bit digital code, where n is any number depending on design requirements of multichannel ADC100. In various implementations, multichannel ADC100represents an N-channel ADC, where N is a total number of channels, and multichannel ADC100is configured to convert analog signals from N channels into corresponding digital signals.FIG. 1has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in multichannel ADC100, and some of the features described can be replaced or eliminated in other embodiments of multichannel ADC100.

Multichannel ADC100includes an input for receiving analog signals Vin1, Vin2, . . . , Vin(N-1), and VinNvia channels CH1, CH2, . . . , CH(N-1), and CHN. InFIG. 1, multichannel ADC100includes a dedicated ADC per channel, such as an ADC102for conversion in each channel (thus including N ADCs102). For example, ADC1, ADC2, . . . , ADC(N-1), and ADCNcan convert respective analog signal Vin1, Vin2, . . . , Vin(N-1), and VinNinto a respective digital signal Dout1, Dout2, . . . , Dout(N-1), and DoutNin parallel (simultaneously). In various implementations, ADC1, ADC2, . . . , ADC(N-1), and ADCNcan each include a capacitive digital-to-analog converter, which can act as a sampling capacitor for sampling a respective analog signal and holding (locking) its value constant for some period of time. Each ADC can thus sample, hold, and convert its respective analog signal, in some implementations. Multichannel ADC100can also include a controller (not shown) coupled to ADCs102and/or THs104for managing operation thereof. An output of multichannel ADC100may be coupled to additional processing components, such as a digital signal processor, for processing digital signals Dout1, Dout2, . . . , Dout(N-1), and DoutN.

FIG. 2is a simplified schematic circuit diagram of another exemplary multichannel analog-to-digital converter (ADC)200according to various aspects of the present disclosure. Multichannel ADC200is an electronic device (including an electronic circuit and/or one or more electronic components) configured to receive and convert an analog input signal into a digital output signal. The digital output signal can represent an n-bit digital code, where n is any number depending on design requirements of multichannel ADC200. In various implementations, multichannel ADC200represents an N-channel ADC, where N is a total number of channels, and multichannel ADC200is configured to convert analog signals from N channels into corresponding digital signals.FIG. 2has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in multichannel ADC200, and some of the features described can be replaced or eliminated in other embodiments of multichannel ADC200.

Multichannel ADC200includes an input for receiving analog signals Vin1, Vin2, . . . , Vin(N-1), and VinNvia channels CH1, CH2, . . . , CH(N-1), and CHN. InFIG. 2, in contrast to multichannel ADC100, multichannel ADC200includes a single ADC for all channels. For example, multichannel ADC200includes ADC202for converting respective analog signals Vin1, Vin2, . . . , Vin(N-1), and VinNinto a digital signal Dout. Each channel can include a track-and-hold (TH)204. For example, TH1, TH2, . . . , THN-1, and THNsample respective analog signal Vin1, Vin2, . . . , Vin(N-1), and VinNand hold (lock) its value constant for some period of time (for example, during the analog-to-digital conversion implemented by ADC202). In various implementations, THs204include a capacitor component for holding the sampled analog signals, such that THs204may be referred to as a sampling capacitors. A multiplexer206is configured to select one of analog signals Vin1, Vin2, . . . , Vin(N-1), and VinNfor transmitting to ADC202for conversion. In the depicted embodiment, multiplexer206is an N:1 multiplexer, having an input coupled to N channels (here, via THs204) and an output coupled to ADC202. In operation, multiplexer206provides one of analog signals Vin1, Vin2, . . . , Vin(N-1), and VinNto ADC202, such that multichannel ADC200can serially convert analog signals Vin1, Vin2, . . . , Vin(N-1), and VinNinto digital signal Dout(generally representing each digital signal Dout1, Dout2, . . . , Dout(N-1), and DoutNfor respective channel CH1, CH2, . . . , CH(N-1), and CHN). In some implementations, multichannel ADC200implements a charge sharing scheme to effectively minimize power and device area. For example, instead of having multiple ADCs and their associated capacitive digital-to-analog converters sample and hold the analog input signals, multichannel ADC200includes dedicated sampling capacitors that share charge with ADC202. In particular, each TH204, which sample analog input signals, has a dedicated sampling capacitor that can share charge with capacitors of ADC202, as and when conversion happens. For example, multichannel ADC200can convert each analog signal by connecting each TH204to ADC202. Though such charge sharing scheme provides an optimal solution for overcoming device area limitations, performance metrics, such as signal-to-noise ratio and throughput, can be degraded since signal power losses often result from the charge sharing between capacitors of THs204and capacitors of ADC202. A controller208may be coupled with ADC202, THs204, and/or multiplexer206for managing operation thereof. An output of multichannel ADC200may be coupled to additional processing components, such as a digital signal processor, for processing digital signal Dout.

Multichannel ADC100and multichannel ADC200balance various performance and/or device metrics. For example, by implementing a dedicated ADC per channel, multichannel ADC100can minimize signal-to-noise ratio and throughput (such as conversion speed) losses. However, such configurations can consume larger than desirable device area and exhibit higher than desirable testing time. To combat such deficiencies, by implementing a single ADC for all channels, multichannel ADC200can significantly decrease device area (optimizing space-efficiency) and achieve lower test times when compared to multichannel ADC100, though such benefits are traded for less than desirable signal-to-noise ratio and throughput losses. Solutions are thus needed for optimally balancing performance and device metrics (such as signal-to-noise ratio, throughput, device area, and/or other performance and device metric) for multichannel ADCs.

To minimize area and power consumption, multichannel ADC100and multichannel ADC200can implement successive approximation register analog-to-digital converters (SAR ADCs). For example, in various implementations, multichannel ADC100and multichannel ADC200can configure ADCs102and ADC202as SAR ADCs.FIG. 3is a simplified schematic circuit diagram of an exemplary SAR ADC300according to various aspects of the present disclosure. SAR ADC300is an electronic device (including an electronic circuit and/or one or more electronic components) configured to receive and convert an analog input signal Vininto a digital output signal Dout. The digital output signal Doutcan represent an n-bit digital code, where n is any number depending on design requirements of SAR ADC300. Generally, SAR ADC300implements a successive approximation algorithm to provide digital output signal Dout.FIG. 3has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in SAR ADC300, and some of the features described can be replaced or eliminated in other embodiments of SAR ADC300.

SAR ADC300includes a comparator302coupled to a digital-to-analog-converter (DAC)304and a SAR controller306. SAR ADC300converts analog input signal Vininto digital output signal Doutby successively changing an output of DAC304(for example, a reference voltage, such as reference voltage Vdac) and comparing the output to analog input signal Vin. For example, comparator302determines whether analog input signal Vinis greater or less than reference voltage Vdac, and generates a digital signal D based on the comparison. Digital signal D can transition between a low state represented by a digital 0 and a high state represented by a digital 1. SAR controller306can include a successive approximation register (SAR) that stores a state of digital signal D, from which SAR controller306can generate digital output signal Dout. SAR controller306can manage DAC304based on a state of digital signal D received from comparator302. For example, based on the state of digital signal D, SAR controller306can selectively set bit(s) associated with DAC304. In various implementations, SAR ADC300can determine digital output signal Doutbit by bit, from a most significant bit to a least significant bit. In such implementations, for determining each bit, SAR controller306can generate a digital signal for setting DAC304, DAC304can generate reference voltage Vdacbased on the setting, and comparator302can determine a value for digital signal D by comparing reference voltage Vdacto analog input signal Vin.

The present disclosure describes various multichannel ADC configurations for optimally balancing signal-to-noise ratio (SNR), throughput (such as conversion speed), and device area concerns described above. In particular, the following describes a pipeline SAR ADC configured to achieve a multichannel ADC that optimally balances signal-to-noise ratio (SNR), throughput, and/or device area metrics. In various implementations, a multichannel pipeline SAR ADC is achieved by having a dedicated SAR ADC for each channel in a first SAR ADC stage, while sharing a SAR ADC in a second SAR ADC stage, along with other portions of the pipeline SAR ADC (such as a multiplexer and/or a residue amplifier), among more than one channel. In some implementations, the second SAR ADC stage, along with other portions of the pipeline SAR ADC (such as the multiplexer and/or the residue amplifier), are shared among all channels. Different embodiments may have different advantages than described herein, and no advantage described herein is required of any embodiment.

A pipeline SAR ADC can be implemented with minimal device area and minimal power consumption.FIG. 4is a simplified schematic circuit diagram of an exemplary pipeline SAR ADC400according to various aspects of the present disclosure. Pipeline SAR ADC400is an electronic device (including an electronic circuit and/or one or more components) configured to convert an analog input signal into a digital output signal. The digital output signal can represent an n-bit digital code, where n is any number depending on design requirements of pipeline SAR ADC400. Generally, pipeline SAR ADC400implements a successive approximation algorithm to provide digital output signal.FIG. 4has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in pipeline SAR ADC400, and some of the features described can be replaced or eliminated in other embodiments of pipeline SAR ADC400.

Pipeline SAR ADC400includes cascaded stages for converting analog signal Vininto a digital signal Dout. For example, pipeline SAR ADC400includes a SAR ADC stage402(Stage 1) and a SAR ADC stage404(Stage 2), where SAR ADC stage402include a SAR ADC406(SAR ADC1) and SAR ADC stage404includes a SAR ADC408(SAR ADC2). In various implementations, SAR ADC1 and SAR ADC2 can be configured as SAR ADC300depicted inFIG. 3. Each SAR ADC stage processes (for example, quantizes) an analog input signal to generate a digital output signal and/or an analog residue signal for a next stage of pipeline SAR ADC400for further processing. For example, SAR ADC stage402processes analog input signal Vinto generate a digital signal Dout1and an analog residue signal Vres; and SAR ADC stage404processes analog residue signal Vresto generate a digital signal Dout2. Digital signal Dout1can represent a p-bit digital code and digital signal Dout2can represent a q-bit digital code, where p and q are any number depending on design requirements of pipeline SAR ADC400. A residue amplifier410, coupled to SAR ADC stage402and SAR ADC stage404, can process (for example, amplify and/or level shift) analog residue signal Vres, from SAR ADC406, such that SAR ADC408can digitally convert an amplified version of analog residue signal Vres. Pipeline SAR ADC400can assemble digital signal Dout1and digital signal Dout2into a digital output signal Dout, which may be represented as (p+q)-bit digital code. In various implementations, a digital alignment/correction module (not shown) can assemble these digital signals. Digital alignment/correction module can insert appropriate delays, insert bit shifts, correct conversion errors, perform other alignment/correction, or a combination thereof to digital signals Dout1and Dout2to generate digital output signal Dout. An output of pipeline SAR ADC400may be coupled to additional processing components, such as a digital signal processor, for processing digital signal Dout. Furthermore, pipeline SAR ADC400can include a controller (not shown) for managing operations thereof.

In some implementations, SAR ADC stage402can include a mini-ADC412coupled to SAR ADC406. Mini-ADC412and SAR ADC406sample a same input, such as analog input signal Vin, where mini-ADC412is configured to convert analog input signal Vininto a digital output signal d. Digital output signal d can represent an x-bit digital code. Where SAR ADC406performs the p-bit analog-to-digital conversion, mini-ADC412can generate x bits of the p-bit analog-to-digital conversion. SAR ADC406can load the x-bit digital code and then proceed with converting analog input signal Vininto digital output signal Dout1. In some implementations, mini-ADC412is configured to generate most significant bits of the p-bit analog-to-digital conversion. For example, in some implementations, mini-ADC412can be configured as a most significant bits ADC, such as that described in U.S. Pat. No. 7,924,203, the entire disclosure of which is incorporated herein by reference. Since mini-ADC412can resolve a first few bits of the p-bit analog-to-digital conversion and load the results into SAR ADC406, which continues conversion with sufficient redundancy, some error can be tolerated in the conversion by mini-ADC412. Mini-ADC412can thus convert less accurately than SAR ADC406. Accordingly, device requirements for mini-ADC412(such as capacitor sizes and/or device sizes of comparators, in SAR implementation or flash-based mini-ADC implementations) can be relaxed quite substantially, resulting in mini-ADC412consuming less area than SAR ADC406.

The pipeline SAR ADC, such as pipeline SAR ADC400, can be modified to achieve a multichannel pipeline SAR ADC, which optimally balances various device and performance metrics.FIG. 5is a simplified schematic circuit diagram of an exemplary multichannel pipeline SAR ADC500according to various aspects of the present disclosure. Multichannel pipeline SAR ADC500is an electronic device (including an electronic circuit and/or one or more electronic components) configured to receive and convert an analog input signal into a corresponding digital output signal. The digital output signal can represent an n-bit digital code, where n is any number depending on design requirements of multichannel pipeline SAR ADC500. Multichannel pipeline SAR ADC500represents an N-channel ADC, where N is a total number of channels, and multichannel pipeline SAR ADC500is configured to convert analog signals from N channels into corresponding digital signals. Generally, multichannel pipeline SAR ADC500implements a successive approximation algorithm to provide digital signals.FIG. 5has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in multichannel pipeline SAR ADC500, and some of the features described can be replaced or eliminated in other embodiments of multichannel pipeline SAR ADC500.

Multichannel pipeline SAR ADC500includes an input for receiving analog signals Vin1, Vin2, . . . , Vin(N-1), and VinNvia channels CH1, CH2, . . . , CH(N-1), and CHN. InFIG. 5, multichannel pipeline SAR ADC500includes cascaded stages for converting the analog signals into a digital signal Dout. For example, multichannel pipeline SAR ADC500includes a SAR ADC stage502(Stage 1) and a SAR ADC stage504(Stage 2). Each SAR ADC stage processes (for example, quantizes) an analog input signal to generate a digital output signal and/or an analog residue signal for a next stage of multichannel pipeline SAR ADC500for further processing. For example, SAR ADC stage502processes analog input signal Vinto generate a digital signal Dout1and an analog residue signal; and SAR ADC stage504processes the analog residue signal to generate a digital signal Dout2. Digital signal Dout1can represent a p-bit digital code and digital signal Dout2can represent a q-bit digital code, where p and q are any number depending on design requirements of multichannel pipeline SAR ADC500. Multichannel pipeline SAR ADC500can assemble digital signal Dout1and digital signal Dout2into digital output signal Dout, which may be represented as (p+q)-bit digital code. In various implementations, a digital alignment/correction module (not shown) can assemble these digital signals. Digital alignment/correction module can insert appropriate delays, insert bit shifts, correct conversion errors, perform other alignment/correction, or a combination thereof to digital signals Dout1and Dout2to generate digital output signal Dout. An output of multichannel pipeline SAR ADC500may be coupled to additional processing components, such as a digital signal processor, for processing digital signal Dout. Furthermore, multichannel pipeline SAR ADC500can include a controller (not shown) for managing operations thereof.

SAR ADC stage502includes a dedicated SAR ADC per channel—an ADC506for each channel—and thus includes N ADCs506; and SAR ADC stage504includes a single ADC for all channels, ADC508. ADCs506and ADC508can be configured as SAR ADC300depicted inFIG. 3. In the depicted embodiment, SAR ADC stage502includes an ADC11that processes analog input signal Vin1to generate a digital signal Dpout1and an analog residue signal Vres1, an ADC12that processes analog input signal Vin2to generate a digital signal Dpout2and an analog residue signal Vres2, . . . , an ADC1(N-1)that processes analog input signal Vin(N-1)to generate a digital signal Dpout(N-1)and an analog residue signal Vres(N-1), and an ADC1Nthat processes analog input signal VinNto generate a digital signal DpoutNand an analog residue signal VresN. SAR ADC stage502can thus perform analog-to-digital conversion on analog input signals Vin1, Vin2, . . . , Vin(N-1), and VinNin parallel (simultaneously). In furtherance of the depicted embodiment, SAR ADC stage504includes an ADC2 that processes analog residue signals to generate digital signals for each channel. For example, ADC2 processes analog residue signal Vres1to generate a digital signal Dqout1analog residue signal Vres2to generate a digital signal Dqout2, . . . , analog residue signal Vres(N-1)to generate a digital signal Dqout(N-1), and analog residue signal VresNto generate a digital signal DqoutN. Note that digital signal Dpoutgenerally represents each digital signal Dpout1, Dpout2, . . . , Dpout(N-1), and DpoutNgenerated by SAR ADC stage502respectively for channels CH1, CH2, . . . , CH(N-1), and CHN; and digital signal Dqoutgenerally represents each digital signal Dqout1, Dqout2, . . . , Dqout(N-1), and DqoutNgenerated by SAR ADC stage504respectively for channels CH1, CH2, . . . , CH(N-1), and CHN. Accordingly, multichannel pipeline SAR ADC500can assemble digital signal Dpout1and digital signal Dqout1into digital output signal Doutfor channel CH1, digital signal Dpout2and digital signal Dqout2into digital output signal Doutfor channel CH2, . . . , digital signal Dpout(N-1)and digital signal Dqout(N-1)into digital output signal Doutfor channel CH(N-1), and digital signal DpoutNand digital signal DqoutNinto digital output signal Doutfor channel CHN.

Multichannel pipeline SAR ADC500further includes a single multiplexer and a single residue amplifier for all channels—in the depicted embodiment, a multiplexer510and a residue amplifier512shared by all channels. Multiplexer510is coupled to SAR ADC stage502and SAR ADC stage504, such that multiplexer510can select one of analog residue signals Vres1, Vres2, . . . , Vres(N-1), and VresNfor conversion by SAR ADC stage504. In the depicted embodiment, multiplexer510is an N:1 multiplexer (where, as noted above, N is a number of channels of multichannel pipeline SAR ADC500), having an input coupled to each ADC506(here, associated with N channels) and an output coupled to residue amplifier512. In operation, multiplexer510provides one of analog residue signals Vres1, Vres2, . . . , Vres(N-1), and VresNto residue amplifier512, which can process (for example, amplify and/or level shift) the selected analog residue signal for ADC508. ADC508can then digitally convert an amplified version of the selected analog residue signal. SAR ADC stage504can thus serially convert analog residue signals Vres1, Vres2, . . . , Vres(N-1), and VresN.

In various implementations, SAR ADC stage502can further include a dedicated mini-ADC for each channel. In such implementations, a mini-ADC, such as mini-ADC412depicted inFIG. 4, can be coupled to each ADC506, where the mini-ADC converts analog input signals Vin1, Vin2, . . . , Vin(N-1), and VinNinto respective digital output signals d1, d2, . . . , d(N-1), and dinN. Each digital output signal can represent an x-bit digital code. Where SAR ADC stage502performs the p-bit analog-to-digital conversion, the mini-ADC can generate x bits of the p-bit analog-to-digital conversion. In various implementations, SAR ADC stage502can include an ADC having portions duplicated across channels, and portions not duplicated across all channels. For example, SAR ADC stage502can include a SAR ADC, where a comparator of the SAR ADC is shared by channels CH1, CH2, . . . , CH(N-1), and CHN, while each channel CH1, CH2, . . . , CH(N-1), and CHN has a dedicated DAC. The dedicated DAC of each channel can be alternately coupled to (or attached) to the comparator to start conversion for the channel. In such implementations, SAR ADC stage502and SAR ADC stage504can perform conversions in a serialized manner.

FIG. 6is a simplified schematic circuit diagram of another exemplary multichannel pipeline SAR ADC600according to various aspects of the present disclosure. Multichannel pipeline SAR ADC600is an electronic device (including an electronic circuit and/or one or more electronic components) configured to receive and convert an analog input signal into a corresponding digital output signal. The digital output signal can represent an n-bit digital code, where n is any number depending on design requirements of multichannel pipeline SAR ADC600. Multichannel pipeline SAR ADC600represents an N-channel ADC, where N is a total number of channels, and multichannel pipeline SAR ADC600is configured to convert analog signals from N channels into corresponding digital signals. Generally, multichannel pipeline SAR ADC600implements a successive approximation algorithm to provide digital signals.FIG. 6has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in multichannel pipeline SAR ADC600, and some of the features described can be replaced or eliminated in other embodiments of multichannel pipeline SAR ADC600.

Similar to multichannel pipeline SAR ADC500, multichannel pipeline SAR ADC600includes an input for receiving analog signals Vin1, Vin2, . . . , Vin(N-1), and VinNvia channels CH1, CH2, . . . , CH(N-1), and CHN. InFIG. 6, multichannel pipeline SAR ADC600includes cascaded stages for converting the analog signals into a digital signal Dout. For example, multichannel pipeline SAR ADC600includes a SAR ADC stage602(Stage 1) and a SAR ADC stage604(Stage 2). Each SAR ADC stage processes (for example, quantizes) an analog input signal to generate a digital output signal and/or an analog residue signal for a next stage of multichannel pipeline SAR ADC600for further processing. For example, SAR ADC stage602processes analog input signal Vinto generate a digital signal Dout1and an analog residue signal; and SAR ADC stage604processes the analog residue signal to generate a digital signal Dout2. Digital signal Dout1can represent a p-bit digital code and digital signal Dout2can represent a q-bit digital code, where p and q are any number depending on design requirements of multichannel pipeline SAR ADC600. Multichannel pipeline SAR ADC600can assemble digital signal Dout1and digital signal Dout2into a digital output signal Dout, which may be represented as (p+q)-bit digital code. In various implementations, a digital alignment/correction module (not shown) can assemble these digital signals. Digital alignment/correction module can insert appropriate delays, insert bit shifts, correct conversion errors, perform other alignment/correction, or a combination thereof to digital signals Dout1and Dout2to generate digital output signal Dout. An output of multichannel pipeline SAR ADC600may be coupled to additional processing components, such as a digital signal processor, for processing digital signal Dout. Furthermore, multichannel pipeline SAR ADC600can include a controller (not shown) for managing operations thereof.

Similar to SAR ADC stage502, SAR ADC stage602includes a dedicated SAR ADC per channel—an ADC606for each channel—and thus includes N ADCs606. ADCs606can be configured as SAR ADC300depicted inFIG. 3. In the depicted embodiment, SAR ADC stage602includes an ADC11that processes analog input signal Vin1to generate a digital signal Dpout1and an analog residue signal Vres1, an ADC12that processes analog input signal Vin2to generate a digital signal Dpout2and an analog residue signal Vres2, . . . , an ADC1(N-1)that processes analog input signal Vin(N-1)to generate a digital signal Dpout(N-1)and an analog residue signal Vres(N-1), and an ADC1Nthat processes analog input signal VinNto generate a digital signal DpoutNand an analog residue signal VresN. SAR ADC stage602can thus perform analog-to-digital conversion on analog input signals Vin1, Vin2, . . . , Vin(N-1), and VinNin parallel (simultaneously). In contrast to SAR ADC stage504, SAR ADC stage604includes an ADC per b of N channels, such as an ADC608per b channels, where b is a number of channels from 1 to N, and y is a total number of ADCs provided by SAR ADC stage604. Each ADC608processes analog residue signals to generate digital signals for its respective channels. In some implementations, SAR ADC stage604may include N/b ADCs608(y=N/b), where each ADC608performs conversion for a same number of channels. In some implementations, ADCs508can perform conversion for various numbers of channels. ADCs608can be configured as SAR ADC300depicted inFIG. 3. In furtherance of the depicted embodiment, SAR ADC stage604includes an ADC per two channels (b=2), such as an ADC21for channel CH1 and channel CH2, . . . , and an ADC2yfor channel CH(N-1) and channel CHN. ADC21processes analog residue signal Vres1to generate a digital signal Dqout1and analog residue signal Vres2to generate a digital signal Dqout2, . . . , and ADC2yprocesses analog residue signal Vres(N-1)to generate a digital signal Dqout(N-1)and analog residue signal VresNto generate a digital signal DqoutN. Note that digital signal Dpoutgenerally represents each digital signal Dpout1, Dpout2, . . . , Dpout(N-1), and DpoutNgenerated by SAR ADC stage602respectively for channels CH1, CH2, . . . , CH(N-1), and CHN, and digital signal Dqoutgenerally represents each digital signal Dqout1, Dqout2, . . . , Dqout(N-1), and DqoutNgenerated by SAR ADC stage604respectively for channels CH1, CH2, . . . , CH(N-1), and CHN. Accordingly, multichannel pipeline SAR ADC600can assemble digital signal Dpout1and digital signal Dqout1into digital output signal Doutfor channel CH1, digital signal Dpout2and digital signal Dqout2into digital output signal Doutfor channel CH2, . . . , digital signal Dpout(N-1)and digital signal Dqout(N-1)into digital output signal Doutfor channel CH(N-1), and digital signal DpoutNand digital signal DqoutNinto digital output signal Doutfor channel CHN.

In further contrast to multichannel pipeline SAR ADC500, multichannel pipeline SAR ADC600includes a multiplexer and a residue amplifier per b channels—for example, a multiplexer610and a residue amplifier612per b of N channels. In the depicted embodiment, having an ADC per two channels (b=2), multichannel pipeline SAR ADC600includes a multiplexer and a residue amplifier per two channels, such as a MUX1and a RA1for channel CH1 and channel CH2, . . . , and a MUXyand a RAyfor channel CH(N-1) and channel CHN. MUX1, . . . , and MUXyare coupled to SAR ADC stage602and SAR ADC stage604, such that MUX1can select one of analog residue signals Vres1and Vres2for conversion by ADC21, . . . , and MUXycan select one of analog residue signals Vres(N-1)and VresNfor conversion by ADC2y. MUX1, . . . , and MUXyare b:1 multiplexers (such as 2:1 multiplexers where b=2), having an input coupled to b ADCs606(here, associated with b of N channels) and an output coupled respectively to RA1, . . . , and RAy. In operation, MUX1provides one of analog residue signals Vres1and Vres2to residue amplifier RA1, which can process (for example, amplify and/or level shift) the selected analog residue signal for ADC21. ADC21can then digitally convert an amplified version of the selected analog residue signal. Similarly, MUXyprovides one of analog residue signals Vres(N-1)and VresNto residue amplifier RAy, which can process (for example, amplify and/or level shift) the selected analog residue signal for ADC2y. ADC2ycan then digitally convert an amplified version of the selected analog residue signal. SAR ADC stage604can thus serially convert analog residue signals Vres1and Vres2, . . . , and analog residue signals Vres(N-1), and VresNin parallel, which can enhance throughput of multichannel pipeline SAR ADC600. In some implementations, SAR ADC stage604may include N/b ADCs608(y=N/b), where each ADC608performs conversion for a same number of channels.

In various implementations, SAR ADC stage602can further include a dedicated mini-ADC for each channel. In such implementations, a mini-ADC, such as mini-ADC412depicted inFIG. 4, can be coupled to each ADC606, where the mini-ADC converts analog input signals Vin1, Vin2, . . . , Vin(N-1), and VinNinto respective digital output signals d1, d2, . . . , d(N-1), and dinN. Each digital output signal can represent an x-bit digital code. Where SAR ADC stage602performs the p-bit analog-to-digital conversion, the mini-ADC can generate x bits of the p-bit analog-to-digital conversion. In various implementations, SAR ADC stage602can include an ADC having portions duplicated across channels, and portions not duplicated across all channels. For example, SAR ADC stage602can include a SAR ADC, where a comparator of the SAR ADC is shared by channels CH1, CH2, . . . , CH(N-1), and CHN, while each channel CH1, CH2, . . . , CH(N-1), and CHN has a dedicated DAC. The dedicated DAC of each channel can be alternately coupled to (or attached) to the comparator to start conversion for the channel. In such implementations, SAR ADC stage602and SAR ADC stage604can perform conversions in a serialized manner.

By modifying a first stage of a pipeline SAR ADC to include a dedicated SAR ADC per channel (essentially duplicating ADCs for each channel) while sharing SAR ADCs in subsequent stages among all the channels, multichannel pipeline SAR ADC500and multichannel pipeline SAR ADC600can eliminate a charge sharing scheme, such as described above, utilized by many multichannel ADCs. More specifically, the multichannel pipeline SAR ADCs described herein can directly sample using DACs of the duplicated SAR ADCs, and then perform first stage conversions in a parallel manner, while the subsequent stage conversions are performed in a serial manner. By eliminating the charge sharing scheme between the sampling capacitors and the SAR ADC capacitors (such as depicted with reference to multichannel ADC100and multichannel ADC200), multichannel pipeline SAR ADC500and multichannel pipeline SAR ADC600can boost signal-to-noise ratio and throughput (such as conversion speeds). For example, in various implementations, multichannel pipeline SAR ADC500and multichannel pipeline SAR ADC600realize signal-to-noise ratio similar to that of multichannel ADC100, while minimizing any device area penalty. In another example, in various implementations, multichannel pipeline SAR ADC500and multichannel pipeline SAR ADC600realize throughputs significantly higher than multichannel ADC200. Multichannel pipeline SAR ADC500and multichannel pipeline SAR ADC600can thus strike an optimal balance for achieving desired device and/or performance metrics, including signal-to-noise ratio, throughput, and/or device area. Such configurations can be implemented in a number of multichannel systems, where the demand for improved signal-to-noise ratio and throughput while minimizing device footprint, continues to increase.

FIG. 7is a simplified flowchart of exemplary method700that can be implemented for performing multichannel analog-to-digital conversion according to various aspects of the present disclosure. In various implementations, method700can be implemented by a multichannel pipeline SAR ADC, such as multichannel pipeline SAR ADC500or multichannel pipeline SAR ADC600described above. At block710, a first SAR analog-to-digital conversion is performed on a plurality of analog input signals. In some implementations, the plurality of analog input signals can be sampled and converted in parallel. At block720, an analog residue signal is selected from among the first SAR analog-to-digital conversions. In some implementations, the analog residue signal can be selected from among all of the first SAR analog-to-digital conversions. In some implementations, where the plurality of analog input signals includes N analog input signals, the analog residue signal can be selected from among b of the first SAR analog-to-digital conversions. At block730, a second SAR analog-to-digital conversion is performed on the selected analog residue signal. The method can further include amplifying the selected analog residue signal. In some implementations, each selected analog residue signal is sampled and converted serially.FIG. 7has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional steps can be provided before, during, and after method700and some of the steps described can be replaced or eliminated for other embodiments of method700.

In various implementations, multichannel systems, multichannel ADCs (for example, multichannel ADC100, multichannel200, multichannel pipeline SAR ADC500, and multichannel pipeline SAR ADC600), and/or the various circuits and/or components of the FIGURES can be implemented on a board of an associated electronic device. The board can be a general circuit board that can hold various components of an internal electronic system of the electronic device and, further, provide connectors for other peripherals. The board can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processors (inclusive of digital signal processors, microprocessors, supporting chipsets, etc.), memory elements, etc. can be suitably coupled to the board based on particular configuration needs, processing demands, computer designs, other considerations, or a combination thereof. Other components, such as external storage, sensors, controllers for audio/video display, and peripheral devices may be attached to the board as plug-in cards, via cables, or integrated into the board itself.

In various implementations, multichannel systems, multichannel ADCs (for example, multichannel ADC100, multichannel200, multichannel pipeline SAR ADC500, and multichannel pipeline SAR ADC600), and/or the various circuits and/or components of the FIGURES can be implemented as stand-alone modules (for example, a device with associated components and circuitry configured to perform a specific application or function) or implemented as plug-in modules into application specific hardware of electronic devices. Note that particular embodiments of the present disclosure may be readily included in a system-on-chip (SOC) package, either in part, or in whole. An SOC represents an integrated circuit that integrates components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio frequency functions: all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip-module (MCM), with a plurality of separate ICs located within a single electronic package and configured to interact closely with each other through the electronic package. In various other embodiments, the various functions described herein may be implemented in one or more semiconductor cores (such as silicon cores) in application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), other semiconductor chips, or combinations thereof.

Note that the activities discussed above with reference to the FIGURES are applicable to any integrated circuits that involve signal processing, particularly those that can execute specialized software programs or algorithms, some of which may be associated with processing digitized real-time data. Certain embodiments can relate to multi-DSP signal processing, floating point processing, signal/control processing, fixed-function processing, microcontroller applications, etc. In certain contexts, the features discussed herein can be applicable to medical systems, scientific instrumentation, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, instrumentation (which can be highly precise), and other digital-processing-based systems. Moreover, certain embodiments discussed above can be provisioned in digital signal processing technologies for medical imaging, patient monitoring, medical instrumentation, and home healthcare. This could include pulmonary monitors, accelerometers, heart rate monitors, pacemakers, etc. Other applications can involve automotive technologies for safety systems (e.g., stability control systems, driver assistance systems, braking systems, infotainment and interior applications of any kind). Furthermore, powertrain systems (for example, in hybrid and electric vehicles) can use high-precision data conversion products in battery monitoring, control systems, reporting controls, maintenance activities, etc. In yet other example scenarios, the teachings of the present disclosure can be applicable in the industrial markets that include process control systems that help drive productivity, energy efficiency, and reliability. In consumer applications, the teachings of the signal processing circuits discussed above can be used for image processing, auto focus, and image stabilization (e.g., for digital still cameras, camcorders, etc.). Other consumer applications can include audio and video processors for home theater systems, DVD recorders, and high-definition televisions. Yet other consumer applications can involve advanced touch screen controllers (e.g., for any type of portable media device). Hence, such technologies could readily be part of smartphones, tablets, security systems, PCs, gaming technologies, virtual reality, simulation training, etc.

The specifications, dimensions, and relationships outlined herein have only been offered for purposes of example and teaching only. Each of these may be varied considerably without departing from the spirit of the present disclosure, or the scope of the appended claims. The specifications apply only to non-limiting examples and, accordingly, they should be construed as such. In the foregoing description, example embodiments have been described with reference to particular processor and/or component arrangements. Various modifications and changes may be made to such embodiments without departing from the scope of the appended claims. The description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. Further the various circuitry configurations described above can be replaced, substituted, or otherwise modified to accommodate various design implementations that achieve the multichannel conversion mechanisms described herein. Moreover, using complementary electronic devices, hardware, software, etc. can offer an equally viable option for implementing the teachings of the present disclosure.

Note that with the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electrical components. However, this has been done for purposes of clarity and example only. It should be appreciated that the system can be consolidated in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, circuits, and elements of the FIGURES may be combined in various possible configurations, all of which are clearly within the broad scope of this Specification. In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows by only referencing a limited number of electrical components. It should be appreciated that the electrical circuits of the FIGURES and its teachings are readily scalable and can accommodate a large number of components, as well as more complicated/sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of the electrical circuits as potentially applied to a myriad of other architectures. Further, note that references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment”, “example embodiment”, “an embodiment”, “another embodiment”, “some embodiments”, “various embodiments”, “other embodiments”, “alternative embodiment”, “various implementations”, “some implementations”, “an implementation”, and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments. It is further noted that “coupled to” and “coupled with” are used interchangeably herein, and that references to a feature “coupled to” or “coupled with” another feature include any communicative coupling means, electrical coupling means, mechanical coupling means, other coupling means, or a combination thereof that facilitates the feature functionalities and operations, such as the multichannel conversion mechanisms, described herein.

OTHER NOTES, EXAMPLES, AND IMPLEMENTATIONS

In various implementations, a system is provided that can be part of any type of computer, which can further include a circuit board coupled to a plurality of electronic components. The system can include means for performing a first SAR analog-to-digital conversion on a plurality of analog input signals; means for selecting an analog residue signal from among the first SAR analog-to-digital conversions; and means for performing a second SAR analog-to-digital conversion on the selected analog residue signal. The ‘means for’ can also or alternatively include (but is not limited to) using any suitable component discussed herein, along with any suitable software, circuitry, hub, computer code, logic, algorithms, hardware, controller, interface, link, bus, communication pathway, etc. In various implementations, the system includes memory that includes instructions that when executed cause the system to perform any of the activities discussed herein. In various implementations, the various functions outlined herein may be implemented by logic encoded in one or more non-transitory and/or tangible media (for example, embedded logic provided in an application specific integrated circuit (ASIC), as digital signal processor (DSP) instructions, software (potentially inclusive of object code and source code) to be executed by a processor, or other similar machine, etc.).