In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.

BACKGROUND

Field

Aspects of the present disclosure relate to silicon-on-insulator devices, and more particularly, to structures and manufacturing methods for silicon-on-insulator backside contacts.

Background

Silicon-on-insulator (SOI) technology refers to the use of a layered silicon-insulator-silicon substrate in place of a conventional silicon substrate in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance. An integrated circuit built using SOI devices may show processing speed that is approximately 30% faster than a comparable bulk-based integrated circuit and power consumption being reduced by as much as 80%, which makes it ideal for mobile devices. SOI chips also reduce the soft error rate, which is data corruption caused by cosmic rays and natural radioactive background signals. SOI transistors offer a unique opportunity for CMOS architectures to be more scalable. The buried oxide layer (back insulating layer) limits the punch-through that may exist on deep sub-micron bulk devices.

In some examples, a layer transfer process is used to transfer a top active device portion of an SOI wafer to a handle wafer. In this process, the top portion of the SOI wafer is bonded to the handle wafer, and the bulk substrate layer (the sacrificial substrate) of the SOI wafer is removed. The process enables a backside connection system to be formed, in addition to a frontside connection system. For example, the back insulating layer may be thinned down. Openings may be formed in the back insulating layer so that backside contacts may be formed to connect to devices, such as a MOSFET's source, drain, and/or body. In addition, one or more metal layers and vias may be formed on the back insulating layer to route powers, grounds, and/or signals to the devices. The backside contacts and one or more metal layers and vias form the backside connection system as compared to frontside contacts and metal layers and vias in the frontside connection system. Source and drain silicide is often required to facilitate good connection between frontside or backside connection system with the devices. Conventionally, a dual-side silicidation process may be needed, forming a frontside silicide layer in the front of the source or drain for connection to the frontside connection system, and a backside silicide layer in the back of the source or drain for connection to the backside connection system.

The backside silicide layer is formed after the formation of the devices and the frontside connection system. Consequently, forming the backside silicide layer may pose several issues. It increases process complexity, resulting in additional cost and yield loss. Higher thermal from extra silicidation process may have adverse effect on device performance and integrity of the frontside connection system. Accordingly, it would be beneficial to enable backside connection system without additional backside silicide layer.

SUMMARY

The following presents a simplified summary of one or more implementations to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key nor critical elements of all implementations nor delineate the scope of any or all implementations. The sole purpose of the summary is to present concepts relate to one or more implementations in a simplified form as a prelude to a more detailed description that is presented later.

In one aspect, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.

In another aspect, a method comprises providing an SOI wafer having a back insulating layer, one or more MOSFETs on the back insulating layer each having a diffusion region as source or drain, and a frontside silicide layer on the diffusion region having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; forming a contact opening through the back insulating layer and a portion of the diffusion region; and forming a backside contact in the contact openings, wherein the backside contact connects to the frontside silicide layer by the back silicide side.

In another aspect, a method comprises providing an SOI wafer having a back insulating layer and one or more MOSFETs each having a diffusion region as source or drain of the MOSFET, wherein the diffusion region has a front diffusion side and a back diffusion side; forming a recess in a selected recess area in the diffusion region from the front diffusion side; forming a silicide layer in the diffusion region from the front diffusion side and the recess, wherein the silicide layer has a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side, and wherein the back silicide side touches the back insulating layer under the selected recess area; forming a contact opening in the back insulating layer; and forming a backside contact in the contact opening, wherein the backside contact connects to the silicide layer under the selected recess area by the back silicide side.

In another aspect, a method comprises providing an SOI wafer having a back insulating layer, one or more MOSFETs each having a diffusion region as source or drain of the MOSFET, and a shallow trench isolation opening adjacent to the diffusion region, wherein the diffusion region has a front diffusion side, a back diffusion side, and a sidewall, wherein the sidewall is also a sidewall of the shallow trench isolation opening; forming a silicide layer in the diffusion region from the front diffusion side and the sidewall, wherein the silicide layer touches the back insulating layer by the sidewall; forming a contact opening in the back insulating layer; and forming a backside contact in the contact opening, wherein the backside contact connects to the silicide layer by the sidewall.

To accomplish the foregoing and related ends, one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the described implementations are intended to include all such aspects and their equivalents.

DETAILED DESCRIPTION

Semiconductor-on-insulator (SOI) devices are widely used for their excellent electrical properties including lower threshold voltage, smaller parasitic capacitance, less current leakage and good switching property, etc. The layer transfer technology enables interconnect routing to be on both sides of the devices and is opening up new classes of materials, devices, integration and systems in the field of microelectronics, microelectromechanical systems (MEMS), optical devices, and optoelectronics.

A dual-side silicidation process is typically required to facilitate the dual-side routing.FIG. 1illustrates an example dual-side silicide dual-side connection systems SOI device according to certain aspects of the present disclosure. The SOI device100comprises a back insulating layer102(e.g., comprising SiO2), one or more diffusion regions114(e.g., comprising N+ silicon for an NMOSFET or P+ silicon for a PMOSFET) on the back insulating layer102that may be sources or drains of MOSFETs, one or more body regions104(e.g., comprising P silicon for an NMOSFET or N silicon for a PMOSFET) as channels of the MOSFETs, and one or more shallow trench isolation regions124(e.g., comprising SiO2). Each of the MOSFETs further comprises a gate insulating layer106(e.g., comprising SiO2or HfO) on the body region104, a gate conducting layer108(e.g., comprising polysilicon or metal) on the gate insulating layer106, and a spacer110(e.g., SiN).

Each of the diffusion regions114has a front diffusion side114fand a back diffusion side114b. Each of the diffusion regions114is silicidized in the front diffusion side114fto have a frontside silicide layer116(e.g., comprising CoSi or TiSi). The frontside silicide layers116may also be in and on the gate conducting layers108. Some of the diffusion regions114are also silicidized in the back diffusion side114bto have backside silicide layers118. The frontside silicide layers116and the backside silicide layers118provide low resistive connection for source, drain, and gate for the MOSFETs.

The SOI device100further comprises one or more frontside contacts122(e.g., comprising W, Ti, Cu, or Al) connected to the respective frontside silicide layers116and one or more backside contacts112(e.g., comprising W, Ti, Cu, or Al) connected to the respective backside silicide layers118. In addition, one or more front metal layers and vias142(e.g., comprising Cu or Al) coupled to the one or more frontside contacts122, and together form a frontside connection system. Similarly, one or more back metal layers and vias132(e.g., comprising Cu or Al) coupled to the backside contacts112and together form a backside connection system.

The dual-side silicidation process shown inFIG. 1enables a dual-side connection systems, allowing both a frontside connection system and a backside connection system in the same die. The technology, however, improves the circuit and interconnect density and routability at the cost of increased process complexity, higher thermal budget, potential yield loss, and potential performance degradation.

FIG. 2illustrates an exemplary single-side silicide dual-side connection systems SOI device according to certain aspects of the present disclosure. Similar to the SOI device100, the SOI device200comprises a back insulating layer202(e.g., comprising SiO2), one or more diffusion regions214(e.g., comprising N+ silicon for an NMOSFET or P+ silicon for a PMOSFET) on the back insulating layer202that may be sources or drains of MOSFETs, one or more body regions204(e.g., comprising P silicon for an NMOSFET or N silicon for a PMOSFET) on the back insulating layer202as channels of the MOSFETs, and one or more shallow trench isolation regions224(e.g., comprising SiO2). Each of the MOSFETs further comprises a gate insulating layer206(e.g., comprising SiO2or HfO) on a respective one of the body regions204, a gate conducting layer208(e.g., comprising polysilicon or metal) on the gate insulating layer206, and a spacer210(e.g., SiN).

Each of the diffusion regions214has a front diffusion side214fand a back diffusion side214b. Each of the diffusion regions214is silicidized in the front diffusion side214fto have a frontside silicide layer216(e.g., comprising CoSi or TiSi). Each of the frontside silicide layers216has a back silicide side216bfacing the respective one of the diffusion regions214and a front silicide side216fopposite to the back silicide side216b. The frontside silicide layers216also are in and on the respective one of the gate conducting layers208. The frontside silicide layers216provide low resistive connection for source, drain, and/or gate contacts for the MOSFETs.

The SOI device200also comprises one or more frontside contacts222(e.g., comprising W, Ti, Cu, or Al) connected to the frontside silicide layers216by the front silicide side216f. One or more front metal layers and vias242couple to the frontside contacts222and together form a frontside connection system. However, unlike the SOI device100, the SOI device200does not comprise backside silicide layers. Instead, one or more backside contacts212(e.g., comprising W, Ti, Cu, or Al) are in both the back insulating layer202and the respective diffusion regions214and connect directly to the respective frontside silicide layers216by the back silicide side216b. One or more back metal layers and vias232coupled to the backside contacts212and together form a backside connection system for the SOI device200.

As illustrated inFIG. 2, for the backside contacts212to be connected low resistively with the diffusion regions214, the backside contacts212must be through a portion of the diffusion regions214to reach the frontside silicide layers216. A portion of the backside contacts212is surrounded by the diffusion regions214while a portion is surrounded by the back insulating layer102. This requires selective diffusion silicon etching under the frontside silicide layers216for the etch to stop at the respective back silicide side216b. Additional end-point sensing may be needed for control to avoid over or under etching.

As also illustrated inFIG. 2, not every frontside silicide layer has to couple to a frontside contacts. Likewise, not every frontside silicide layer has to couple to a backside contacts. In addition, a frontside silicide layer may couple to both a frontside contact and a backside contact or neither.

Both the frontside contacts222and the backside contacts212may comprise any suitable conductive material or materials, such as W, Ti, Al, or Cu. A conductive diffusion barrier may be formed along the sidewall of the frontside contacts and/or the backside contacts. For example, Ti/TiN liner may be formed along the sidewall of the frontside contacts and/or the backside contacts.

FIGS. 3a-3dillustrate another exemplary single-side silicide dual-side connection systems SOI device according to certain aspects of the present disclosure. InFIG. 3a, a starting SOI wafer is provided. The starting SOI wafer comprises a sacrificial substrate362, a back insulating layer302on the sacrificial substrate362, one or more MOSFETs on the back insulating layer302each formed by diffusion regions314as source or drain, a body region304as channel, a gate insulating layer306, a gate conducting layer308on the gate insulating layer306, and a spacer310. Each of the diffusion regions314has a front diffusion side314fand a back diffusion side314b. The starting SOI wafer also comprises shallow trench isolation regions324to isolate two or more diffusion regions314.

InFIG. 3b, some of the diffusion regions314are patterned and etched in the front diffusion sides314fto form recesses334at selected recess areas. The diffusion regions314at the selected recess areas are thinned down to a thickness D. The thickness D is selected such that the following silicidation process would consume all diffusion silicon in the selected recess areas.

InFIG. 3c, a silicidation process is performed on the gate conducting layer308and on the diffusion regions314from the front diffusion sides314f, including the selected recess areas. As a result, frontside silicide layers316is formed on the diffusion regions314and the gate conducting layers308. Each of the frontside silicide layers316has a back silicide side316bfacing the respective diffusion regions314and a front silicide side316fopposite to the back silicide side316b.

In the selected recess areas, because the thickness of the silicon is reduced small enough, the silicidation process consumes all the remaining diffusion silicon. Both the front silicide sides316fand the back silicide sides316bof the respective frontside silicide layers316are not flat, but curve down in the selected recess areas. A portion of the front silicide sides316fmay be at the same level as, below, or above the front diffusion side314f. For example, the portion of the front silicide sides316fthat is not in the selected recess area may be above the front diffusion sides314fwhile the portion of the front silicide sides316fthat is in the selected recess area may be below the front diffusion sides314f. Moreover, a portion of the back silicide sides316bof the frontside silicide layers316touch the back insulating layer302, such as the portion of the frontside silicide layers316in the selected recess areas.

InFIG. 3d, after the formation of the frontside silicide layers316, one or more frontside contacts322(e.g., comprising W, Ti, Cu, or Al) connected to the respective frontside silicide layers316by the front silicide side316band one or more front metal layers and vias342coupled to the frontside contacts322. Together they form a frontside connection system.

After the formation of the frontside connection system, a handle wafer (not shown) is bonded to the starting SOI wafer. After the bonding of the handle wafer (not shown), the sacrificial substrate362is removed, exposing the back insulating layer302(which may be further thinned down). One or more backside contacts312(e.g., comprising W, Ti, Cu, or Al) are formed in the back insulating layer302and connected directly to the respective frontside silicide layers316by the back silicide sides316bunder the selected recess areas. As the portion of the frontside silicide layers316in the selected recess areas touches the back insulating layer302, the one or more backside contacts312do not have to pass through the diffusion regions314, saving the process of selective etching.

Following the formation of the backside contacts312, one or more back metal layers and vias332coupled to the backside contacts312are formed. Together, they form a backside connection system.

As illustrated inFIG. 3d, not every frontside silicide layer has to couple to a frontside contacts. Likewise, not every frontside silicide layer has to couple to a backside contacts. In addition, a frontside silicide layer may couple to both a frontside contact and a backside contact or neither. Accordingly, recesses334do not have to form in every diffusion region314. Only the diffusion regions314that couple to the backside connection system would form recesses334.

Both the frontside contacts322and the backside contacts312may comprise any suitable conductive material or materials, such as W, Ti, Al, or Cu. A conductive diffusion barrier may be formed along the sidewall of the frontside contacts and/or the backside contacts. For example, Ti/TiN liner may be formed along the sidewall of the frontside contacts and/or the backside contacts.

FIGS. 4a-4cillustrate yet another exemplary single-side silicide dual-side connection systems SOI device according to certain aspects of the present disclosure. InFIG. 4a, a starting SOI wafer is provided. The starting SOI wafer comprises a sacrificial substrate462, a back insulating layer402on the sacrificial substrate462, one or more MOSFETs on the back insulating layer402each formed by diffusion regions414as source or drain, a body region404as channel, a gate insulating layer406, a gate conducting layer408on the gate insulating layer406, and a spacer410. Each of the diffusion regions414has a front diffusion side414fand a back diffusion side414b. In addition, one or more shallow trench isolation openings434exist between two or more diffusion regions414. The one or more shallow trench isolation openings434are in place for shallow trench isolations that will be formed later. The sidewalls434sof the diffusion regions414are the sidewalls of the respective one or more shallow trench isolation openings434, too.

InFIG. 4b, a silicidation process is performed on the gate conducting layer408and on the diffusion regions414from the front diffusion sides414f, including the sidewalls434sin the one or more shallow trench isolation openings434. As a result, frontside silicide layers416are formed on the diffusion regions414and the gate conducting layers408. In the one or more shallow trench isolation openings434, the frontside silicide layers416are also form at the sidewalls434sand end at the back insulating layer402.

InFIG. 4c, after the formation of the frontside silicide layers416, the one or more shallow trench isolation openings434are filled with dielectric materials (e.g., SiO2) to form shallow trench isolation regions424. One or more frontside contacts422(e.g., comprising W, Ti, Cu, or Al) are formed to connect to the respective frontside silicide layers416. One or more front metal layers and vias442are formed to couple to the frontside contacts422. Together they form a frontside connection system.

After the formation of the frontside connection system, a handle wafer (not shown) is bonded to the starting SOI wafer. After the bonding of the handle wafer (not shown), the sacrificial substrate462is removed, exposing the back insulating layer402(which may be further thinned down). One or more backside contacts412(e.g., comprising W, Ti, Cu, or Al) are formed in the back insulating layer402and connected directly to the respective frontside silicide layers416by the sidewalls434s. As the portion of the frontside silicide layers416at the sidewalls434stouches the back insulating layer302, the one or more backside contacts412do not have to pass through the diffusion regions314, saving the process of selective etching.

Following the formation of the backside contacts412, one or more back metal layers and vias432coupled to the backside contacts412are formed. Together they form a backside connection system.

As illustrated inFIG. 4c, not every frontside silicide layer has to couple to a frontside contacts. Likewise, not every frontside silicide layer has to couple to a backside contacts. In addition, a frontside silicide layer may couple to both a frontside contact and a backside contact or neither.

Both the frontside contacts422and the backside contacts412may comprise any suitable conductive material or materials, such as W, Ti, Al, or Cu. A conductive diffusion barrier may be formed along the sidewall of the frontside contacts and/or the backside contacts. For example, Ti/TiN liner may be formed along the sidewall of the frontside contacts and/or the backside contacts.

FIG. 5illustrates an exemplary method500in making an exemplary single-side silicide dual-side connection systems SOI device according to certain aspects of the present disclosure. At502, a starting SOI wafer is provided. The starting SOI wafer comprises a sacrificial substrate, a back insulating layer (e.g., the back insulating layer302), one or more MOSFETs on the insulating layer each formed by diffusion regions (e.g., the diffusion regions214) as source or drain, a body region (e.g., the body region204) as channel, a gate insulating layer (e.g., the gate insulating layer206), a gate conducting layer (e.g., the gate conducting layer208) on the gate insulating layer, and a spacer (e.g., the spacer210). The starting SOI wafer also comprises a sacrificial substrate and shallow trench isolation regions (e.g., the shallow trench isolation regions224) to isolate two or more diffusion regions. Frontside silicide layers (e.g., the frontside silicide layers216) are formed in and on the diffusion regions and the gate insulating layers. One or more frontside contacts (e.g., the frontside contacts222) connect to the respective frontside silicide layers. One or more front metal layers and vias (e.g., the front metal layers and vias242) couple to the frontside contacts. The frontside contacts and the front metal layers and vias together form a frontside connection system.

At504, the SOI wafer is bonded to a handle wafer. The sacrificial substrate is then removed, exposing the back insulating layer (which may be further thinned down).

At506, one or more contact openings are formed by patterning and etching the back insulating layer and the diffusion regions. The one or more contact openings are formed under the diffusion regions. The openings have to be through a portion of the diffusion regions and stop at the frontside silicide layers. This requires selectively etching diffusion silicon under the frontside silicide layers. Additional end-point sensing may be needed for control to avoid over or under etching.

At508, one or more backside contacts (e.g., the backside contacts212) are formed in the one or more contact openings. The backside contacts connect low resistively to the diffusion regions through the frontside silicide layers.

At510, one or more back metal layers and vias (e.g., the back metal layers and vias232) are formed to couple to the backside contacts and together form a backside connection system for the SOI device.

FIG. 6illustrates another exemplary method600in making an exemplary single-side silicide dual-side connection systems SOI device according to certain aspects of the present disclosure. At602, a starting SOI wafer is provided. The starting SOI wafer comprises a sacrificial substrate (e.g., the sacrificial substrate362), a back insulating layer (e.g., the back insulating layer302) on the sacrificial substrate, one or more MOSFETs on the insulating layer each formed by diffusion regions (e.g., the diffusion regions314) as source or drain, a body region (e.g., the body region304) as channel, a gate insulating layer (e.g., the gate insulating layer306), a gate conducting layer (e.g., the gate conducting layer308) on the gate insulating layer, and a spacer (e.g., the spacer310). Each of the diffusion regions has a front diffusion side and a back diffusion side. The starting SOI wafer may also comprise shallow trench isolation regions (e.g., the shallow trench isolation regions324) to isolate two or more diffusion regions.

At604, one or more diffusion regions are patterned and etched from the front diffusion sides to form recesses (e.g., the recesses334) at selected recess areas. The diffusion regions at the selected recess areas are thinned down to a thickness D. The thickness D is such that the following silicidation process would consume all diffusion silicon in the selected recess areas.

At606, a silicidation process is performed in the diffusion regions from the front diffusion sides to form frontside silicide layers (e.g., the frontside silicide layers316), including the selected recess areas. In the selected recess areas, because the thickness of the diffusion silicon is reduced small enough, the frontside silicide layers touch the back insulating layer.

At608, a front metal connection system is formed, including frontside contacts (e.g., the frontside contacts322) coupled to the frontside silicide layers and one or more front metal layers and vias coupled to the frontside contacts. (e.g., the front metal layers and vias342).

At610, the starting SOI wafer is bonded to a handle wafer. The sacrificial substrate is then removed, exposing the back insulating layer (which may be further thinned down).

At612, one or more contact openings are formed by patterning and etching the back insulating layer. The one or more contact openings are formed under the selected recess areas of the diffusion regions. The one or more contact openings touch the frontside silicide layers under the selected recess areas.

At614, one or more backside contacts (e.g., the backside contacts312) are formed in the one or more contact openings. The backside contacts connect low resistively to the diffusion regions through the frontside silicide layers.

At616, one or more back metal layers and vias (e.g., the back metal layers and vias332) coupled to the backside contacts are formed. Together they form a backside connection system for the SOI device.

FIG. 7illustrates yet another exemplary method700in making an exemplary single-side silicide dual-side connection systems SOI device according to certain aspects of the present disclosure. At702, a starting SOI wafer is provided. The starting SOI wafer comprises a sacrificial substrate (e.g., the sacrificial substrate462), a back insulating layer (e.g., the back insulating layer402) on the sacrificial substrate, one or more MOSFETs on the insulating layer each formed by diffusion regions (e.g., the diffusion regions414) as source or drain, a body region (e.g. the body region404) as channel, a gate insulating layer (e.g., the gate insulating layer406), a gate conducting layer (e.g., the gate conducting layer408) on the gate insulating layer, and a spacer (e.g., the spacer410). Each of the diffusion regions has a front diffusion side and a back diffusion side. In addition, one or more shallow trench isolation openings (e.g., the shallow trench isolation openings434) exist between two or more diffusion regions. The one or more shallow trench isolation openings are in place for shallow trench isolations that will be formed later. The sidewalls (e.g., the sidewalls434s) of the diffusion regions are the sidewalls of the one or more shallow trench isolation openings, too.

At704, a silicidation process is performed on the gate conducting layer and on the diffusion regions from the front diffusion sides, including sidewalls in the one or more shallow trench isolation openings. As a result, frontside silicide layers (e.g., the frontside silicide layers416) are formed in the diffusion regions from the front diffusion sides and the sidewalls. The frontside silicide layers formed by the sidewalls touches the back insulating layer.

After the formation of the frontside silicide layers, the shallow trench isolation openings are filled with dielectric materials. A front metal connection system is then formed at706, including frontside contacts (e.g., the frontside contacts422) connected to the frontside silicide layers and one or more front metal layers and vias (e.g., the front metal layers and vias442) coupled to the frontside contacts.

After the formation of the frontside connection system, at708, a handle wafer is bonded to the starting SOI wafer at the front side. The sacrificial substrate is then removed, exposing the back insulating layer (which may be further thinned down).

At710, one or more contact openings are formed by patterning and etching the back insulating layer. The one or more contact openings are formed under the diffusion regions. The one or more contact openings touch the frontside silicide layers by the sidewalls.

At712, one or more backside contacts (e.g., the backside contacts412) are formed in the one or more contact openings. The backside contacts connect low resistively to the diffusion regions through the frontside silicide layers by the sidewalls.

At714, one or more back metal layers and vias (e.g., the back metal layers and vias432) coupled to the backside contacts are formed and together form a backside connection system.