A semiconductor device includes a substrate, a gate structure, at least one nanowire, at least one epitaxy structure, and at least one source/drain spacer. The gate structure is disposed on the substrate. The nanowire extends through the gate structure. The epitaxy structure is disposed on the substrate and is in contact with the nanowire. The source/drain spacer is disposed between the epitaxy structure and the gate structure and is embedded in the epitaxy structure.

BACKGROUND

Semiconductor nanowires are becoming a research focus in nanotechnology. Various methods of forming metal-oxide-semiconductor field-effect transistors (MOSFETs) comprising nanowires have been explored, including the use of dual material nanowire, where different material nanowires are used for N-channel field-effect transistor (NFET) and P-channel field-effect transistor (PFET) devices. For example, silicon (Si) nanowires may be used as the channel material for the NFET devices, while silicon germanium (SiGe) nanowires may be used as the channel material for the PFET devices. As another example, multiple-stacked (“multi-stack”) nanowires have been used in forming NFET and PFET devices, increasing the current carrying capability of these devices. One of the multi-stack candidates is the FET. A trigate FET device consists of a vertical standing Si body (fin) and the gate is wrapped around either side creating two channels on the sides and one on the top. High-aspect-ratio trigate FETs with aggressively scaled fin widths (30 nm and narrower) are of particular interest as they combine excellent short channel effect (SCE) immunity with high drivability per unit chip area.

DETAILED DESCRIPTION

As used herein, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Therefore, reference to, for example, a gate stack includes aspects having two or more such gate stacks, unless the context clearly indicates otherwise. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Further, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are intended for illustration.

A multi-stack structure, such as Ge/SiGe or Si/SiGe may be used to generate multi-stack nanowire devices. Such multi-stack nanowire devices may include one or more PFET devices and one or more NFET devices, where the PFET devices include Ge nanowire and the NFET devices comprise Si nanowire. However, it is difficult to reduce parasitic capacitance between source/drain and gate under such multi-stack nanowire devices. Illustrative embodiments described herein utilize a dual nanowire release scheme for gate and source/drain region.

An illustrative embodiment for forming a multi-stack nanowire FET device will be described below with reference toFIGS. 1A-15E. The structures illustrate operations which may be used in the process of forming a multi-stack nanowire FET device.FIGS. 1A-15Aare top views of a local semiconductor device100at various stages of fabrication in accordance with some embodiments of the present disclosure.FIGS. 1B-15Bare cross-sectional views along lines B-B inFIGS. 1A-15Arespectively.FIGS. 1C-15Care cross-sectional views along lines C-C inFIGS. 1A-15Arespectively.FIGS. 15D and 15Eare cross-sectional views along line D-D and line E-E inFIG. 15Arespectively.

Reference is made toFIGS. 1A-1C. A semiconductor substrate202is provided, and a multilayer stack210′ and a hard mask203are formed on the semiconductor substrate202. In some embodiments for NMOS, the semiconductor substrate202is made of a material, such as, Si, Ge, SiGe, In(Ga)As, or InSb. In some embodiments for PMOS, the semiconductor substrate202is made of a material, such as, Si, Ge, or (In)GaSb. The multilayer stack210includes sacrificial layers212′ and nanowire layers214′. The sacrificial layers212′ and the nanowire layers214′ are stacked alternatively. For example, the nanowire214′ is interposed in between two sacrificial layers212′. In some embodiments, the sacrificial layers212′ may include SiGe or Si, and the nanowires214′ may include Si, SiGe, Ge, GaAs, InAs, InSb, and GaSb, and the instant disclosure is not limited thereto. The nanowire layers214′ may use the same material as the semiconductor substrate202. The number of layers (sacrificial layer212′ and nanowire layer214′) in the multilayer stack210determines the number of nanowires in a fin after patterning.FIGS. 1A-1Cshow a multilayer stack210having four sacrificial layers212′ and three nanowire layers214′. In this case, three nanowires are formed later, and the instant disclosure is not limited thereto. The thickness of the sacrificial layers212′ also determines the pitch between the nanowires, and the thickness of the nanowire layers214′ determines the dimension of the nanowires. The hard mask203is formed over a portion of the topmost sacrificial layer212′, and may be selectively removed in the areas in which a FET stacked nanowire device is to be formed. Although the resulting hard mask203shown inFIGS. 1A-1Cis patterned into three strips with equal spacing, embodiments are not so limited. The resulting hard mask203may be in four, five, six or more strips, and the spacing between the strips may be varied in other embodiments. The hard mask203may be an oxide or nitride, for example, SiO2and Si3N4, and the instant disclosure is not limited thereto.

Reference is made toFIGS. 2A-2C. The multilayer stack210′ ofFIG. 1is patterned to form fins220(the multilayer stack210). The fins220result from the hard mask203(shown inFIGS. 1A-1C) formed over a portion of the topmost sacrificial layer212. The multilayer stack210includes a plurality of sacrificial layers212and a plurality of nanowires214. When the multilayer stack210is patterned, a portion of the underlying semiconductor substrate202is also removed. The fins220include protruded portions202aof the semiconductor substrate202. Then, the hard mask203is removed from the top sacrificial layer212as shown inFIGS. 2A-2C.

Reference is made toFIGS. 3A-3C. After the forming of the fins220, an isolation material is deposited to form isolation structures204at least in the spaces between the fins220. An anisotropic etch is used to recess the isolation material into the semiconductor substrate202at the base of the fins220. The fins220are exposed above the isolation structures204. A top portion of the protruded portion202aof the semiconductor substrate202is not covered by the isolation structures204. As shown inFIGS. 3B and 3C, from the top surface of the isolation structures204, a total of four sacrificial layers212and three nanowires214are exposed. The sacrificial layer212now caps the fins220.

Reference is made toFIGS. 4A-4C. InFIGS. 4A and 4B, for example, three rows of dummy gate structures310(in the positions of hard masks306shown in top view inFIG. 4A) are formed across the fins220. That is, the fins220go along a first direction and the dummy gate structures310go along a second direction. The first and second directions are different, and substantially perpendicular to each other in some embodiments. The term “substantially” as used herein may be applied to modify any quantitative representation which could permissibly vary without resulting in a change in the basic function to which it is related. At least one of the fins220has channel regions220aand source/drain regions220b. The dummy gate structures310define the channel regions220aand the source/drain regions220bof the fins220. The dummy gate structures310are straddle and disposed on the fins220to form channel regions220abelow it, and the source/drain regions220bof the fins220are exposed from the dummy gate structures310. The sacrificial layers212and the nanowires214in the channel regions220aare also referred to as first portions212aand214arespectively, and that in the source/drain regions220bare referred to as second portions212band214brespectively. At least one of the dummy gate structures310may include a gate dielectric layer302, a dummy gate electrode layer304, and a hard mask306, and other materials may also be used. The channel regions220aare covered by the gate dielectric layer302, the dummy gate electrode layer304, and the hard mask306. In some embodiments, the dummy gate structures310are deposited as a blanket layer and then patterned. As shown inFIGS. 4A and 4B, the dummy gate structures310at either ends of the fins220anchor the fins220, and therefore the anchoring dummy gate structures310have portions over the fins220and the remaining portion touches down to the isolation structures204. In some embodiments, the gate dielectric layer302may be made of, such as, SiO2, the dummy gate electrode layer304may be made of, such as, polysilicon, and the hard mask306may be made of, such as, oxide and/or nitride materials, but the instant disclosure is not limited thereto.

After the deposition of the dummy gate structures310, spacers312are formed on sides of the dummy gate structures310and on the sidewalls of the fins220exposed from the dummy gate structures310(seeFIG. 4A), and spaces300are left between the spacers312. Specifically, the spacers312are formed by depositing a spacer layer (such as oxide or nitride) conformally on the fins220and the dummy gate structures310, and then anisotropically etching from the surface of the spacer layer. The etching process removes spacer layer on the top portion of the dummy gate structures310and on the top portion of the fins220exposed from the dummy gate structures310. In the case, the spacers312formed on the side walls of dummy gate structures310can be referred to as gate spacers312a, and that formed on the sidewalls of fins220exposed from the dummy gate structures310can be referred to as fin spacers312b.

As shown inFIG. 4B, the dummy gate structures310are used as a mask where the channel regions220aare located. In other words, the channel regions220aof the fins220(i.e., the first portions214aof the nanowires214) are under the protection of the dummy gate structures310.

Reference is made toFIGS. 5A-5C. The fins220are recessed to form openings422therein. An etch process, such as, reactive ion etching (RIE), atomic layer etching (ALE), or a combination thereof, may be performed on portions of the fins220(shown inFIGS. 4A and 4B) exposed from the dummy gate structures310and the spacers312(outside the dummy gate structures310and the spacers312). As such, the exposed fins220are removed to expose the protruded portions202aof the semiconductor substrate202. The openings422are formed in the fins220and between the fin spacers312bas shown inFIGS. 5A and 5B. That is, the etching process is performed to remove the second portions212band214bof the sacrificial layer212and the nanowires214(shown inFIGS. 4B and 4C). The second portions212band214bof the sacrificial layer212and nanowire214respectively are removed to yield source/drain regions which will be formed later.

The openings422fall between the gate spacers312a, and between the fin spacers312b, and are located between the channel regions220aof the fins220. The openings422are in parallel with the fins220(i.e., perpendicular to the dummy gate structures310) and do not overlap the dummy gate structures310and channel regions220aof the fins220(i.e., the first portions214aof the nanowires214). Furthermore, the first portions212aand214aof the sacrificial layer212and the nanowires214are exposed from the gate spacers312athrough the openings422.

Reference is made toFIGS. 6A-6C. After the recessing of the fins220, the channel regions220aof the fins220exposed from the openings422are oxidized by an oxidation process500. The oxidation process500may be performed on the exposed channel regions220a, such as, an in-situ steam generated (ISSG) oxidation process500conducted in a temperature range about 600° C. to about 1100° C., an annealing process in oxidizing ambient O2and O3conducted in a temperature range about 600° C. to about 1100° C., or plasma enhanced chemical vapor deposition (PECVD) process with precursor (e.g., tetraethoxy silane (TEOS)) conducted in a temperature about 800° C. As such, the first portions212aof the exposed channel regions220a(the end sidewall2120of the first portions212a) are oxidized to form source/drain spacers216(can also be referred to as a second oxidation layer), and the first portions214aof the exposed channel regions220a(the end sidewall2140of the first portions214a) are oxidized to form first sacrificial portions218(can also be referred to as a first oxidation layer). For example, the first portions212aare made of a material, such as, SiGe, and the first portions214aare made of a material, such as, Ge/Si. The oxidation process500may be performed on the first portions212ato form SiGeOx as the source/drain spacers216, and on the first portions214ato form GeO2/SiO2as the first sacrificial portions218.

Reference is made toFIGS. 7A-7C. After the oxidation of the exposed channel regions220a, the first sacrificial portions218(shown inFIG. 6B) of the channel regions220aare removed by an etching process510, but the source/drain spacers216remain. In some embodiments, the etching process510is a selective removal process for different oxide materials, such as, a wet etching process with different etching rates depend on different oxide materials for the source/drain spacers216and the first sacrificial portions218. For example, when the source/drain spacers216are made of a material, such as, SiGeOx and the first sacrificial portions218are made of a material, such as, GeO2, the etching process510may include de-ionized water to remove the first sacrificial portions218and remain the source/drain spacers216. Similarly, when the source/drain spacers216are made of a material, such as, SiGeOx and the first sacrificial portions218are made of a material, such as, SiO2, the etching process510may include, such as, deionized water, ozonated DIW, buffered hydrofluoric acid (BHF), hydrofluoric acid (HF), HF water diluted by ethylene glycol (HFEG), or any combination thereof, to remove the first sacrificial portions218and remain the source/drain spacers216. It is note that, GeO2dissolves in water, while SiGeOx does not.

As such, after the removing of the first sacrificial portions218of the channel regions220a, at least one recess230is formed between adjacent two of the source/drain spacers216, and beneath the gate spacers312a. For example, there are a plurality of recesses230inFIG. 7B. The source/drain spacers216remain suspended on the dummy gate structures310. In other words, the source/drain spacers216protrude from sidewalls of the dummy gate structures310beneath the gate spacers312ato form the recesses230. The first portions214aof the nanowires214are exposed from the recesses230.

Reference is made toFIGS. 8A-8C. After the moving of the first sacrificial portions218(shown inFIGS. 6A-6C) of the channel regions220a, the channel regions220aof the fins220exposed from the contact openings422are oxidized by another oxidation process500again. The oxidation process500may be performed on the exposed channel regions220aexposed from the contact openings422. As such, parts of the first portions212aadjacent to the source/drain spacers216are oxidized such that to form source/drain spacers216′ with the source/drain spacers216. In addition, parts of the first portions214aexposed from the contact openings422are oxidized to form second sacrificial portions222.

Reference is made toFIGS. 9A-9C. After the oxidation of the exposed channel regions220a, the second sacrificial portions222of the channel regions220aare removed by the etching process510, but the source/drain spacers216′ remain. In some embodiments, the etching process510is the selective removal process for the source/drain spacers216′ and the second sacrificial portions222. As such, after the removing of the second sacrificial portions222of the channel regions220a, at least one recesses230′ is formed between adjacent two of the source/drain spacers216′, and beneath the gate spacers312a. For example, there are a plurality of recesses230′ inFIG. 9B. The source/drain spacers216′ remain suspended on the dummy gate structures310and positioned beneath the gate spacers312a. In other words, the source/drain spacers216′ protrude from sidewalls of the dummy gate structures310beneath the gate spacers312ato form the recesses230′. In some embodiments, the source/drain spacers216′ substantially have the same length as that of the gate spacers312a. The first portions214aof the nanowires214are exposed from the recesses230′.

In the case, the channel regions220aare performed on a cyclic oxidation etch (COE) process. That is, the source/drain spacers on the first portions214aare formed by repeated oxidation process500to achieve a predetermined thickness thereof. Relatively, the sacrificial portions formed on the first portions212aare removed by the selective removal process to remain the source/drain spacers without removing it. In the cyclic oxidation etch (COE) process of the source/drain spacers formation, it can ensure the thickness of source/drain spacers achieve designed thickness, and has a good control for widths of the source/drain spacers. In some embodiments of the instant disclosure, the oxidation for the source/drain spacers and the selective etching of the sacrificial portions may repeat twice or even more. As a result, the thickness of the source/drain spacers can be controlled in cycle times of the oxidation process500. Specifically, the thickness of the source/drain spacers216′ is larger than that of the source/drain spacers216shown inFIG. 7B. In addition, the length of the first portions214aof the nanowires214is shorter than that shown inFIG. 7Bdue to the multiple selective etching processes, and therefore the first portions214aof the nanowires214can expose from the recesses between the source/drain spacers and not cover by the oxide, such as, sacrificial portions in the present disclosure. Furthermore, the formation of the source/drain spacers216′ can be conducted in a self-aligned process, but no lithography process is required.

Reference is made toFIGS. 10A-10C. Epitaxy structures316are formed in the openings422by, for example, an epitaxial growth process as source/drain regions. As such, the fin spacers312bare in contact with opposite sidewalls of the epitaxy structure316. The epitaxial growth process is performed on exposed parts of the first portions214aof the nanowires214, and performed on exposed parts of the protruded portions202aof the semiconductor substrate202. Therefore, the epitaxy structures316are formed between the channel regions220a, further formed in the recesses230′ of the channel regions220a, and in contact with the protruded portions202a. More specifically, the epitaxy structures316have protruding portions318embedded in (or being protruding into) the recesses230′ of the channel regions220aand disposed between the gate spacer312aand the source/drain spacers216′. Furthermore, the protruding portion318is disposed between and extends pass two of the source/drain spacers216′, is in contact with the first portions214aof the nanowires214and top surfaces216tand/or bottom surfaces216bof the source/drain spacers216′, and the topmost protruding portion318is further disposed between the gate spacer312aand the source/drain spacer216′. In other words, the source/drain spacers216′ and the protruding portions318are arranged in an alternating manner. On the other hand, the source/drain spacers216′ are disposed between the epitaxy structure316and the dummy gate structure310, are embedded in the epitaxy structure316, and are in contact with opposite sidewalls of the epitaxy structure316. Therefore, the source/drain spacers216′ are separated from the first portions214aof the nanowires214by the epitaxy structures316.

In some embodiments, in situ doping (ISD) is applied to form doped source/drain regions316. N-type and p-type FETs are formed by implanting different types of dopants to selected regions of the device to form the necessary junction(s). N-type devices may be formed by implanting arsenic (As) or phosphorous (P), and p-type devices may be formed by implanting boron (B). For example, the epitaxy structures316may include materials such as SiP or SiGeB and any other suitable materials. The epitaxy structures316may be formed conformally by CVD, or by monolayer doping (MLD). Alternatively, the epitaxy structures316may be formed by an implantation with activation anneal step.

With such configuration, the epitaxy structures316are positioned such that subsequent etching processes that remove the first portions212aof the sacrificial layer212during device fabrication do not also damage the epitaxy structures316. That is, the epitaxy structures316are configured to be separated from the first portions212aof the sacrificial layer212at least by the source/drain spacers216′ and the first portions214aof the nanowires214, such that parasitic capacitance between the epitaxy structures316and gate under such multi-stack nanowire devices will be reduced.

Reference is made toFIGS. 11A-11C. An interlayer dielectric (ILD) layer320is blanket deposited on the semiconductor substrate202, fills in the spaces left between the gate spacers312a, and between the fin spacers312b. The epitaxy structures316are then covered by the interlayer dielectric layer320. Further, the interlayer dielectric layer320covers up the spacers312and the dummy gate structures310. At least one epitaxy structure316is disposed between the interlayer dielectric layer320and the source/drain spacer216′.

Then, a planarization process is performed to the interlayer dielectric layer320. The planarization process may be chemical mechanical polishing (CMP) process or any other suitable process. Portions of the interlayer dielectric layer320are removed. The interlayer dielectric layer320between the gate spacers312aand between the fin spacers312bremain. In the planarization process, the hard masks306shown inFIGS. 10A-10Cof the dummy gate structures310and portions of the spacers312(shown inFIGS. 10A-10C) are removed. On top of the epitaxy structures316, a layer of the interlayer dielectric layer320remains.

Reference is made toFIGS. 12A-12C. After planarization, the dummy gate structures310and the first portions212aof the sacrificial layers212(shown inFIGS. 11B and 11C) are removed to form gate trenches322, but the spacers312and the first portions214aof the nanowires214remain. The dummy gate electrode layer304and the gate dielectric layer302are removed by suitable process, leaving spaces between the gate spacers312a. The channel regions220aof the fins220are then exposed from the gate trenches322, while the epitaxy structures316are still under the coverage of the interlayer dielectric layer320.

Then, after the removal of the dummy gate structures310, the first portions212a(shown inFIGS. 11B and 11C) of the sacrificial layers212are removed. As shown inFIG. 12A, the first portions212aof the top sacrificial layers212are removed, leaving the underlying nanowire214exposed. The first portions212aof the sacrificial layers212between the nanowires214are also removed. The first portions214aof the nanowires214are released from the fins220and spaced apart from each other. The first portions214aof the nanowires214are not flanked by the sacrificial layer212anymore.

After the removal of the first portions212aof the sacrificial layers212, spaces are left between the nanowires214. The pitch P1between the nanowires214are determined by the thickness of the sacrificial layer212shown inFIGS. 11B and 11C. The first portions214aof the nanowires214suspend over one another without making contact. The pitch P1between the nanowires214reflects where the first portions212aof the sacrificial layers212use to stand. For example, if the sacrificial layer212has a thickness of 8 nm, after the removal of the first portions212aof the sacrificial layers212, the pitch P1is measured of about 8 nm. The pitch P1has pivotal effect in the nanowire214configuration at the channel regions220a. Furthermore, when the removing the first portions214aof the nanowires214, the source/drain spacers216′ avoid unwanted etching on the epitaxy structures316.

Reference is made toFIGS. 13A-13C. A high-k gate dielectric layer330(can also referred to as an interlayer dielectric layer) and a work function metal layer340are formed on the first portions214aof the nanowires214to fill the gate trench322. As shown inFIG. 13B, the high-k gate dielectric layer330is a thin layer formed on the exposed surfaces including the sidewalls of the gate spacers312aand first portions214aof the nanowires214. Specifically, the high-k gate dielectric layer330is in contact with the source/drain spacers216′ and covers the first portions214aof the nanowires214. As shown inFIG. 13C, the high-k gate dielectric layer330wraps around the first portions214aof each of the nanowires214. The surface of the isolation structures204and the protruded portions202aof the semiconductor substrate202are also covered by the high-k gate dielectric layer330. Spaces between the first portions214aof the nanowires214are still left after the deposition of the high-k gate dielectric layer330. The high-k gate dielectric layer330includes a material such as hafnium oxide (HfO2), zirconium oxide (ZrO2) or lanthanum oxide (La2O3). The high-k gate dielectric layer330may be formed by suitable deposition processes, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other like processes. The thickness of the high-k gate dielectric layer330may vary depending on the deposition process as well as the composition and number of the high-k gate dielectric layer330used.

Then, a work function metal layer340is formed. The work function metal layer340may be disposed over the high-k gate dielectric layer330, and fill up the spaces between the nanowires214replacing the first portions212aof the sacrificial layers212. The type of work function metal layer340depends on the type of transistor. That is, the work function metal layer340may include p-type work function metal materials and n-type work function metal materials. P-type work function materials include compositions such as ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), and conductive metal oxides, or any combination thereof. N-type metal materials include compositions such as hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), and aluminum carbide (Al4C3)), aluminides, or any combination thereof. The work function metal(s) may be deposited by a suitable deposition process, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), plating, thermal or e-beam evaporation, and sputtering. For example, the work function metal layer340may include materials such as titanium nitride (TiN) or tantalum nitride (TaN).

Reference is made toFIGS. 14A-14C. A gate electrode350is formed. The gate electrode350is deposited over the high-k gate dielectric layer330and the work function metal layer340to form the gate structures360. As shown inFIG. 14C, the gate electrode350fills up the spaces surrounding the nanowires214, thereby completely wrapping around the first portions214aof the nanowires214. In other words, the nanowires214extend through the gate structures360. The gate structures360replace the dummy gate structures310. Furthermore, the source/drain spacers216′ are in contact with and protrude from the gate structures360, and are separated from the first portions214aof the nanowires214by the gate structures360. The source/drain spacer216′ is disposed between the epitaxy structure316and the gate structures360.

The gate electrode350may include conductive material, such as, aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The gate electrode350may be deposited by a suitable deposition process, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), plating, thermal or e-beam evaporation, and sputtering. A planarization process, for example, chemical mechanical planarization (CMP), is performed to polish the surface of the conductive gate metal and form the gate structures360.

Reference is made toFIGS. 15A-15C.FIG. 15Ais a top view of the local semiconductor device100.FIGS. 15B and 15Care cross-sectional views taken along sections B-B and C-C inFIG. 15Arespectively. A plurality of contact openings542are formed in the interlayer dielectric layer320, and the contact openings542respectively expose the epitaxy structures316. A plurality of contacts are respectively formed in the contact openings542. In some embodiments, the contact includes a work function metal layer520and a metal layer530formed on the work function metal layer520. The work function metal layer520is deposited in the contact openings542and formed on a top surface of the epitaxy structures316. Subsequently, the metal layer530is formed on the work function metal layer520and fills in the contact openings542shown inFIGS. 15A and 15B.

Reference is made toFIGS. 15D and 15E.FIGS. 15D and 15Eare cross-sectional views along sections D-D and line E-E inFIG. 15Arespectively. The source/drain spacers216′ are disposed between the protruding portions318of the epitaxy structures316, and surrounded by the gate spacers312aas shown inFIG. 15D. Furthermore, the epitaxy structures316are conformally covered by the work function metal layer520, and disposed on and in contact with the protruded portions202aof the semiconductor substrate202as shown inFIG. 15E.

Some other illustrative embodiments for forming a local semiconductor device400at various stages of fabrication in accordance with some embodiments of the present disclosure will be described below with reference toFIGS. 16A-23E. The structures illustrate operations which may be used in the process of forming the local semiconductor device100.FIGS. 16A-23Aare top views of the local semiconductor device400at various stages of fabrication in accordance with some embodiments of the present disclosure.FIGS. 16B-23Bare cross-sectional views along lines B-B inFIGS. 16A-23Arespectively.FIGS. 16C-23Care cross-sectional views along lines C-C inFIGS. 16A-23Arespectively.FIGS. 23D and 23Eare cross-sectional views along line D-D and line E-E inFIG. 23Arespectively.

It should be pointed out that operations for forming the local semiconductor device400before the structure shown inFIG. 16are substantially the same as the operations for forming the local semiconductor device100shown inFIGS. 1A-5C, and the related detailed descriptions may refer to the foregoing paragraphs and are not discussed again herein. The differences between the present embodiment and the embodiment inFIGS. 16A-23Eare that operations of forming source/drain spacers.

Reference is made toFIGS. 16A-16C. After the recessing of the fins220(seeFIG. 5B), the channel regions220aof the fins220exposed from the contact openings422are performed by an atomic layer chemical vapor deposition (ALD) process600. Specifically, the ALD process600is conducted in an ALD H2O pulse with a duration t1followed by N2purge with a duration t2. In some embodiments, the duration t1has a range from about 0.1 second to about 5 seconds, the duration t2has a range from about 0.1 second to about 5 seconds, but the instant disclosure is not limited thereto. The ALD process600may be performed on the exposed channel regions220ato form selective oxide formations as source/drain spacers416. For example, the first portions212aare made of a material, such as, SiGe, and the first portions214aare made of a material, such as, Ge/Si. The atomic layer deposition (ALD) process600may be performed on the first portions212ato form SiGeOx as the source/drain spacers416, but without forming oxide formations on the first portions214aof the exposed channel regions220a.

As such, after the forming of the source/drain spacers416, at least one recess440is formed between adjacent two of the source/drain spacers416, and beneath the gate spacers312a. For example, there are a plurality of recesses440inFIG. 16B. The source/drain spacers416remain suspended on the dummy gate structures310. In other words, the source/drain spacers416protrude from sidewalls of the dummy gate structures310beneath the gate spacers312ato form the recesses440. The first portions214aof the nanowires214are exposed from the recesses440.

Reference is made toFIGS. 17A-17C. In the case, the channel regions220aare performed on a single multi-cycle ALD process600. That is, the source/drain spacers416′ on the first portions214aare formed by repeated ALD process600to achieve a predetermined thickness thereof. Relatively, the first portions214aof the exposed channel regions220aare without forming oxide formations thereon. As such, after the forming of the source/drain spacers416′, at least one recess440′ is formed between adjacent two of the source/drain spacers416′, and beneath the gate spacers312a. For example, there are a plurality of recesses440′ inFIG. 17B. In some embodiments, the width of the source/drain spacers416′ may be about 2 nm to 10 nm, and the instant disclosure is not limited thereto. In other words, the source/drain spacers416′ protrude from sidewalls of the dummy gate structures310beneath the gate spacers312ato form the recesses440′. The first portions214aof the nanowires214are exposed from the recesses440′.

In the single multi-cycle ALD process600of the source/drain spacer formation, it can ensure the thickness of source/drain spacers achieve designed thickness, and has a good control for widths of the source/drain spacers. In some embodiments of the instant disclosure, the ALD process600for the source/drain spacers may substantially be 20 cycles to 200 cycles, but the present disclosure is not limited thereto. As a result, the thickness of the source/drain spacers can be controlled in cycle times of the ALD process600. Specifically, the thickness of the source/drain spacers416′ is larger than that of the source/drain spacers416shown inFIG. 16B. The first portions214aof the exposed channel regions220aare without forming oxide formations thereon, and therefore the first portions214aof the nanowires214can be exposed from the recesses440′ or440between the source/drain spacers416′ or416and not cover by the oxide. Furthermore, the formation of the source/drain spacers416′ can be conducted in a self-aligned process, but no lithography process is required.

Reference is made toFIGS. 18A-18C. Epitaxy structures426are formed in the openings422by, for example, an epitaxial growth process as source/drain regions. The epitaxial growth process is performed on exposed parts of the first portions214aof the nanowires214, and performed on exposed parts of the protruded portions202aof the semiconductor substrate202. Therefore, the epitaxy structures426are formed between the channel regions220a, further formed in the recesses440′ of channel regions220a, and in contact with the protruded portions202a. More specifically, the epitaxy structures316have protruding portions418embedded in (or being protruding into) the recesses230′ of channel regions220aand disposed between the gate spacer312aand the source/drain spacers416′. Furthermore, the protruding portion418is disposed between and extends pass two of the source/drain spacers416′ and is in contact with the first portions214aof the nanowires214. In other words, the source/drain spacers416′ and the protruding portions418are arranged in an alternating manner. On the other hand, the source/drain spacers416′ are disposed between the epitaxy structure426and the dummy gate structure310, are embedded in the epitaxy structure426, and are in contact with opposite sidewalls of the epitaxy structure426. Therefore, the source/drain spacers416′ are separated from the first portions214aof the nanowires214by the epitaxy structures426.

With such configuration, the epitaxy structures426are positioned such that subsequent etching processes that remove the first portions212aof the sacrificial layer212during device fabrication do not also damage the epitaxy structures426. That is, the epitaxy structures426are configured to be separated from the first portions212aof the sacrificial layer212at least by the source/drain spacers416′ and the first portions214aof the nanowires214, such that parasitic capacitance between the epitaxy structures426and gate under such multi-stack nanowire devices will be reduced.

Reference is made toFIGS. 19A-19C. An interlayer dielectric (ILD) layer320is blanket deposited on the semiconductor substrate202, fills in the spaces left between the gate spacers312a, and between the fin spacers312b. The epitaxy structures426are then covered by the interlayer dielectric layer320. Further, the interlayer dielectric layer320covers up the spacers312and the dummy gate structures310. Then, a planarization process is performed to the interlayer dielectric layer320. Portions of the interlayer dielectric layer320are removed. The interlayer dielectric layer320between the gate spacers312aand between the fin spacers312bremain. In the planarization process, the hard masks306shown inFIGS. 18A-18Cof the dummy gate structures310and portions of the spacers312shown inFIGS. 10A-10Care removed. On top of the epitaxy structures426, a layer of the interlayer dielectric layer320remains.

Reference is made toFIGS. 20A-20C. After planarization, the dummy gate structures310and the first portions212aof the sacrificial layers212(shown inFIGS. 19B and 19C) are removed to form gate trenches322, but the spacers312and the first portions214aof the nanowires214remain. The dummy gate electrode layer304and the gate dielectric layer302are removed by suitable process, leaving spaces between the gate spacers312a. The channel regions220aof the fins220are then exposed from the gate trenches322, while the epitaxy structures426are still under the coverage of the interlayer dielectric layer320.

Then, after the removal of the dummy gate structures310, the first portions212a(shown inFIGS. 19B and 19C) of the sacrificial layers212are removed. As shown inFIG. 19A, the first portion212aof the top sacrificial layer212is removed, leaving the underlying nanowire214exposed. The first portions212aof the sacrificial layers212between the nanowires214are also removed. The first portions214aof the nanowires214are released from the fins220and spaced apart from each other. The first portions214aof the nanowires214are not flanked by the sacrificial layer212anymore. Furthermore, when the removing the first portions212aof the sacrificial layers212, the source/drain spacers416′ avoid unwanted etching on the epitaxy structures426.

Reference is made toFIGS. 21A-21C. A high-k gate dielectric layer330and a work function metal layer340are formed on the first portions214aof the nanowires214to fill the gate trench322. As shown inFIG. 21B, the high-k gate dielectric layer330is a thin layer formed on the exposed surfaces including the sidewalls of the gate spacers312aand first portions214aof the nanowires214. Specifically, the high-k gate dielectric layer330is in contact with the source/drain spacers416′ and covers the first portions214aof the nanowires214. On the other hand, the protruding portions418of the epitaxy structures426are disposed between the high-k gate dielectric layer330and the source/drain spacer416′. As shown inFIG. 21C, the high-k gate dielectric layer330wraps around the first portions214aof each of the nanowires214. The surface of the isolation structures204and the protruded portions202aof the semiconductor substrate202are also covered by the high-k gate dielectric layer330. Spaces between the first portions214aof the nanowires214are still left after the deposition of the high-k gate dielectric layer330. The thickness of the high-k gate dielectric layer330may vary depending on the deposition process as well as the composition and number of the high-k gate dielectric layer330used. Then, a work function metal layer340is formed. The work function metal layer340may be disposed over the high-k gate dielectric layer330, and fill up the spaces between the nanowires214replacing the first portions212aof the sacrificial layers212.

Reference is made toFIGS. 22A-22C. A gate electrode350is formed. The gate electrode350is deposited over the high-k gate dielectric layer330and the work function metal layer340to form the gate structures360. As shown inFIG. 22C, the gate electrode350fills up the spaces surrounding the nanowires214, thereby completely wrapping around the first portions214aof the nanowires214. In other words, the nanowires214extend through the gate structures360. The gate stack replaces the dummy gate structures310. The source/drain spacers416′ are in contact with the gate structures360, are separated from the first portions214aof the nanowires214by the gate stack, and protrude from the gate structures360.

Reference is made toFIGS. 23A-23C.FIG. 23Ais a top view of the local semiconductor device400.FIGS. 23B and 23Care cross-sectional views taken along sections B-B and C-C inFIG. 23Arespectively. A plurality of contact openings542are formed in the interlayer dielectric layer320, and the contact openings542respectively expose the epitaxy structures316. A plurality of contacts are respectively formed in the contact openings542. In some embodiments, the contact includes a work function metal layer520and a metal layer530formed on the work function metal layer520. The work function metal layer520is deposited in the contact openings542and formed on a top surface of the epitaxy structures426. Subsequently, the metal layer530is formed on the work function metal layer520and fills in the contact openings542shown inFIGS. 23A and 23B.

Reference is made toFIGS. 23D and 23E.FIGS. 23D and 23Eare cross-sectional views along sections D-D and line E-E inFIG. 23Arespectively. The source/drain spacers416′ are disposed between the protruding portions418of the epitaxy structures426, and surrounded by the gate spacers312aas shown inFIG. 23D. Furthermore, the epitaxy structures426are conformally covered by the work function metal layer520, and disposed on and in contact with the protruded portions202aof the semiconductor substrate202as shown inFIG. 23E.

According to some embodiments, the epitaxy structures are configured to be separated from the gate structure at least by the source/drain spacers, such that parasitic capacitance between the epitaxy structures and gate under such multi-stack nanowire devices will be reduced.

According to some embodiments, a semiconductor device includes a substrate, a gate structure, at least one nanowire, at least one epitaxy structure, and at least one source/drain spacer. The gate structure is disposed on the substrate. The nanowire extends through the gate structure. The epitaxy structure is disposed on the substrate and is in contact with the nanowire. The source/drain spacer is disposed between the epitaxy structure and the gate structure and is embedded in the epitaxy structure.

According to some embodiments, a semiconductor device includes a substrate, at least one nanowire, a gate structure, at least one epitaxial structure, and at least one source/drain spacer. The nanowire is disposed on the substrate. The gate structure is disposed on the substrate and wraps around the nanowire. The epitaxial structure is disposed on the substrate and is in contact with the nanowire. The source/drain spacer protrudes from the gate structure and is in contact with the epitaxial structure in which the epitaxial structure wraps around the source/drain spacer.

According to some embodiments, a semiconductor device includes a method for manufacturing a semiconductor device includes forming a multilayer stack on a substrate in which the multilayer stack comprises at least one sacrificial layer and at least one nanowire arranged in an alternating manner; forming a dummy gate on the multilayer stack; patterning the multilayer stack using the dummy gate as a mask to expose at least an end sidewall of the patterned sacrificial layer; oxidizing the end sidewall of the patterned sacrificial layer to form at least one source/drain spacer thereon; forming at least one epitaxial structure on the substrate and in contact with the patterned nanowire and the at least one source/drain spacer; removing the dummy gate and the patterned sacrificial layer; and forming a gate structure at least surrounding the patterned nanowire.