System and method for converting an AC input voltage to regulated output current

A converter according to one embodiment converts an AC voltage to a regulated output current provided to a DC load of a Z-type configuration. A filter capacitor is provided to average current flowing through the load. The converter includes a rectifier network for rectifying the AC voltage and for providing a rectified voltage, and a smoothing capacitor for smoothing the rectified voltage. The converter includes a hysteretic current mode controller which controls a switching transistor based on sensed voltage and sensed current provided through an inductor coupled in series with the load. The transistor is turned on when current reaches a low valley level and is turned off when the current reaches a peak level. Operation toggles in this manner while a sensed voltage is above a predetermined level. A valley fill network may be provided to keep sensed voltage from falling below the predetermined minimum level.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application Ser. No. 61/388,353, filed on Sep. 30, 2010, which is hereby incorporated by reference in its entirety for all intents and purposes.

BRIEF DESCRIPTION OF THE DRAWINGS

The benefits, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings in which:

FIG. 1is a simplified schematic and block diagram of a converter implemented according to one embodiment;

FIG. 2is a series of timing diagrams which illustrate operation of the converter ofFIG. 1;

FIG. 3is a schematic and block diagram of a converter, which is a more specific embodiment of the converter ofFIG. 1in which similar components assume identical reference designators;

FIG. 4is a schematic and block diagram of a converter, which is configured in substantially the same manner as the converter ofFIG. 1in which similar components assume identical reference designators;

FIG. 5shows the measurements of the conducted EMI spectrum for both a hysteretic current control simulation circuit and a duty ratio control simulation circuit;

FIG. 6is a timing diagram illustrating simulation results for a converter configured substantially similar to the converter ofFIG. 3, except replacing the LEDs with a static resistor;

FIGS. 7-10illustrate various electronic devices using a converter implemented according to any of the configurations described herein; and

FIG. 11is a block diagram of an electronic device including a converter configured in a similar manner as that shown inFIG. 9for providing current to one or more LEDs.

DETAILED DESCRIPTION

The benefits, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings The following description is presented to enable one of ordinary skill in the art to make and use the present invention as provided within the context of a particular application and its requirements. Various modifications to the preferred embodiment will, however, be apparent to one skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

A converter (also referred to herein as a regulator) according to one embodiment of the present invention is a simple, low-cost converter which converts an AC input into a regulated output current. A converter as described herein may be used to drive a variety of loads in which a DC current is desired. A non-limiting list of examples includes a battery charger, a light-emitting diode (LED) driver, a driver for a coil of an electric motor, one or more laser diodes, etc. A converter according to one embodiment may use standard inductors and avoids a custom transformer. A custom transformer is otherwise common for use in a conventional LED drivers. In one embodiment, the converter does not need a snubber circuit to control overshoot on a power switching device or electronic switching device. Examples of power switching devices or electronic switches include a metal-oxide semiconductor, field-effect transistor (MOSFET) or other similar forms (e.g., FETs, MOS devices, etc.), bipolar junction transistor (BJTs) and the like, insulated-gate bipolar transistors (IGBTs) and the like, etc. Smaller and less expensive capacitors may be used for switching frequency filtering so that electrolytic capacitors, which are generally characterized by short life, high cost, and large size, may thus be avoided. A simple hysteretic current controller provides accurate current regulation and reduced electromagnetic interference (EMI) emissions. A system and method according to an embodiment of the present invention uses a reduced number of components thereby reducing size and cost.

FIG. 1is a simplified schematic and block diagram of a converter100implemented according to one embodiment. The converter100is configured using a quasi-Z-source configuration and operates to convert an alternating current (AC) input voltage VAC to an output voltage VL applied across a load resistor RL relative to a reference supply voltage, such as ground (GND). VAC has a positive polarity applied on a node101and a negative polarity on a node103. VAC is applied to a bridge rectifier104including diodes D1, D2, D3and D4. The cathode of D1and the anode of D2are coupled to node101, and the cathode of D3and the anode of D4are coupled to node103. The cathodes of D2and D4are coupled to a node105developing a voltage VC1. Node105is coupled to one end (e.g., positive terminal) of a filter capacitor C1, to one end of an inductor L1, and to the drain of an electronic switch Q. The electronic switch Q is implemented as an N-channel MOSFET, although alternative power switching devices are contemplated.

The other end of L1is coupled to a node107developing a voltage VC2, in which node107is further coupled to one end (e.g., positive terminal) of another filter capacitor C2, to the cathode of a diode D, and to an input of a controller115. The source of Q, the other end of C2(e.g., negative terminal) and another input of the controller115are coupled to a node109, which is further coupled to GND. The load resistor RL is coupled between node109and another node111, and a filter capacitor CDC is coupled in parallel with RL. Node111develops the output voltage VL (relative to GND), and is coupled to one end of another inductor L2. The other end of L2is coupled to a node113, which is further coupled to the cathodes of diodes D, D1and D3, and to the other end (e.g., negative terminal) of the capacitor C1. A current IL1flows from node105to node107via the inductor L1. A current IL2flows from node109through the load (CDC and RL) and through the inductor L2into node113, and thus represents the current flowing through the inductor L2. A current sensor117senses IL2and develops a proportional voltage sense signal VS, which is provided to another input of the controller115. The controller115asserts a gate drive signal GD to the gate of Q. A load current IRL flows through RL.

The bridge rectifier104converts the AC input voltage VAC to a rectified DC voltage VC1across capacitor C1, and to another voltage VC2across capacitor C2. The configuration of the inductors (L1& L2), the capacitors (C1& C2), the switch Q, and the diode D collectively form a quasi-Z-source regulator. In operation, the controller115monitors the voltage VC2of the capacitor C2and the current IL2of the inductor L2and regulates the load by modulating activation of Q, e.g., by turning Q on and off via the GD signal.

FIG. 2is a series of timing diagrams which illustrate operation of the converter100, in which VAC, VC1, IL2, IRL and GD are plotted versus time. VAC is generally a sinusoidal signal which oscillates between positive and negative peaks centered at 0 Volts (V) or GND. VC1is a rectified version of VAC, so that the magnitude of VC1follows VAC except remains positive while VAC goes negative during the second half of each cycle. The capacitors C1and C2smooth the switching frequency rather than storing VAC frequency energy or holding up a rectified input voltage VC1. The capacitance used for switching frequency filtering is smaller than the capacitance used for line frequency energy storage. Electrolytic capacitors, which are generally characterized as short life, high cost, and large size, may thus be avoided for the converter100.

When VC1is below a positive voltage threshold shown as VRUN, GD is held low so that Q is turned off. Once VC1exceeds VRUN, the controller115asserts GD high so that Q is turned on and the current IL2through L2increases at a rate proportional to VC1plus the load voltage VL. It is noted that VL is negative with respect to GND. When IL2reaches a peak threshold current, shown as IPK, the controller115asserts GD low to turn Q off. The diode D conducts to provide a path for IL2, and IL2decreases at a rate proportional to VC2plus VL. When IL2reaches a valley threshold current, shown as IVAL, the controller115asserts GD high again to turn Q back on. The switching cycle repeats so that IL2transitions between IVAL and IPK while VC1is above VRUN. It is noted that the slope of the transitions of IL2change (increase/decrease) as VC1changes (increases/decreases). When VC1decreases below VRUN, the controller115pulls GD low to keep Q turned off. This control method may be referred to as hysteretic current mode or bang-bang control. The capacitor CDC filters the switching frequency ripple so that the load current IRL through the load RL is generally the average of IPK and IVAL while VC1is above VRUN.

Although not explicitly shown, the current wave shape of the current IL1in the inductor L1is similar to that of IL2. When Q is turned on, IL1increases at a rate proportional to the level of VC2(e.g., the rate of change or derivative of IL1is related to or otherwise approximately equal to VC2/L1), and when Q is turned off, diode D provides a path for IL1to decrease proportional to VC1.

FIG. 3is a schematic and block diagram of a converter300, which is a more specific embodiment of the converter100ofFIG. 1in which similar components assume identical reference designators. VAC is again provided across nodes101and103, in which a fusible resistor FR is provided between node101and a node101A for safety purposes. An EMI filter capacitor CEMI is coupled between nodes101A and103, and the anodes of the diodes D1and D2are instead coupled to node101A. The cathodes of diodes D2and D4are instead coupled to a node105A, and a filter inductor LEMI is coupled between nodes105and105A. LEMI, CEMI and C1collectively operate as an EMI filter to reduce emissions. Devices C1, C2, L1, L2, D and Q are coupled to nodes105,107,109,111and113in a similar manner as the converter100. The current sensor117is replaced by a sense resistor RS coupled between node109(GND) and a node109A. RS is typically a relatively small-valued resistance so that nodes109and109A have substantially the same voltage levels for purposes of the load. The load filter capacitor CDC is coupled between nodes111and109A. The load resistor RL is replaced with a series string of LEDs coupled between nodes111and109A. The load current through the LEDs is shown as a current ILED. The cathodes of D1and D3are coupled to node113in similar manner.

The controller115is replaced by a controller315. In the illustrated embodiment, the controller315includes an inverting buffer301, comparators303,305and321, logic gates307and309, a set-reset (SR) latch311, gate drive amplifier313, a frequency switching (FSW) limiter317, a bias regulator319, and a reference generator323. The input of the buffer301is coupled to node109A and its output is coupled to the non-inverting inputs of both comparators303and305. The output of the comparator303is coupled to one input of the logic gate307, which is configured as a 2-input NOR gate. The output of the comparator305is coupled to one input of the logic gate309, which is configured as a 2-input OR gate. The output of NOR gate307is coupled to the set input of the SR latch311and the output of OR gate309is coupled to the reset input of the SR latch311. The Q output of the SR latch311is coupled to the input of the amplifier313and to an input of the FSW limiter317. The output of the amplifier313develops the GD signal provided to the gate of Q. The output of the FSW limiter317is provided to the other input of the NOR gate307.

Node107developing VC2is provided to an input of the bias regulator319and to the inverting input of the comparator321. The bias regulator319develops a voltage VA filtered by a capacitor CB (relative to GND) to a source voltage input of the amplifier313also referenced to GND (or has its other supply voltage input coupled to GND). The bias regulator319also develops a source voltage provided to the reference generator323, which develops reference voltage levels VMIN, VVAL and VPK. VMIN is provided to the non-inverting input of the comparator321, VPK is provided to the inverting input of the comparator305, and VVAL is provided to the inverting input of the comparator303.

The current IL2through RS develops a relatively small negative voltage level on node109A, which is inverted and buffered (and amplified, if desired) by the buffer301to provided a proportional sense voltage VS to the comparators303and305. VVAL corresponds with IVAL, VPK corresponds with IPK, and VMIN corresponds with VRUN. In one embodiment, the FSW limiter317operates to limit switching frequency of Q to a predetermined maximum level. In one embodiment, the FSW limiter317is a falling edge delay. When the SR latch311is set, its Q output is high and the output of the FSW limiter317is also high. When the SR latch311is reset and its Q output is low, the falling edge delay output of the FSW limiter317stays for a predetermined time to prevent the SR latch311from being set. In one embodiment, the predetermined time is approximately 1 microsecond (μs). In this manner, the switching limit function limits switching frequency to a maximum of about 1 megaHertz (MHz) which may vary down to about 500 kiloHertz (kHz) with a 50% duty cycle. In this case, the switching limit function operates as a minimum off time function and is not necessarily a precise frequency limit.

Operation of the converter100is substantially similar to that of the converter100as illustrated by the timing diagrams ofFIG. 2. The current IRL is replaced by the LED current ILED through the LEDs. VAC and VC1operate in substantially the same manner. When VC1is below VRUN, VC2is below VMIN, the output of the comparator321is high, and the output of the OR gate309is high which keeps the SR latch311in a reset state to prevent GD from going high. When VC1rises above VRUN and VC2exceeds VMIN, the output of the comparator321goes low releasing the SR latch311from the held reset state. Since VS is below VVAL indicating that the current IL2is below IVAL, the output of the comparator303is low. Assuming the output of the FSW limiter317is also low, the output of the NOR gate307goes high to set the SR latch311to pull GD high to turn on switch Q. The current IL2increases at a linear rate (as previously described) until VS rises to VPK indicating that IL2reaches IPK, at which time the output of the comparator305goes high to pull the output of the OR gate309high to reset the SR latch309. The SR latch309pulls GD low to turn off Q, and IL2decreases at a linear rate back down to IVAL. Operation repeats in this manner as illustrated inFIG. 2.

The average LED current ILED is set by the peak and valley thresholds, IPK and IVAL as determined by VPK and VVAL, respectively. The controller315enables simplified biasing, gate drive and current sensing. A simple bias regulator319derives control and gate drive power from VC2. The source of Q is also coupled to ground, enabling a single-ended gate driver. The current IL2produces a negative voltage across RS (with respect to ground) and numerous methods (including an inverting voltage amplifier or a voltage-to-current amplifier) may provide the control with a suitable signal (e.g., VS) proportional to IL2.

FIG. 4is a schematic and block diagram of a converter400, which is configured in substantially the same manner as the converter100in which similar components assume identical reference designators. The converter400further includes an exemplary valley fill network401, which includes additional diodes D5, D6and D7and capacitors C3and C4. The anode of D5is coupled to node113, and its cathode is coupled to the anode of D6and to one end of C3. The other end of C3is coupled to node105. One end of C4is coupled to node113, and its other end is coupled to the cathode of D6and the anode of D7. The cathode of D7is coupled to node105.

The valley fill network401is added to the rectified quasi-Z-source converter configuration to provide a continuous load power at the output. The valley fill network401provides energy storage by holding up VC1near the zero crossing of VAC. The capacitors D3and C4within the valley fill network401charge in series near the peak voltage of VAC and discharge in parallel to fill in the valley of the rectified voltage VC1. The valley fill network401provides the energy during the zero crossing for applications that require continuous load regulation. The hysteretic current control provides a simple means to regulate load current. As previously stated, the load current is the mean between the IPK and IVAL thresholds. Another advantage of the hysteretic current mode control is the reduced EMI due to the variation of the switching frequency over the period of VAC. The switching frequency is a function of the inductance L2and the voltages VC1, VC2, and VL.

FIG. 5shows the measurements of the conducted EMI spectrum for both a hysteretic current control simulation circuit (not shown) and a duty ratio control simulation circuit (not shown), each with substantially identical power components. The spectrum is measured in Volts versus frequency in Hertz (“k” denoting kilohertz and “M” denoting MegaHertz). A first spectrum501is the conducted EMI for the hysteretic current control circuit, and a second spectrum503is the conducted EMI for the duty ratio control circuit. The characteristic peaks of the second spectrum503for the fixed switching frequency duty ratio control circuit are significantly larger than characteristic peaks of the first spectrum501for the hysteretic current control circuit.

FIG. 6is a timing diagram illustrating simulation results for a converter configured substantially similar to the converter300, except replacing the LEDs with a static 90Ω resistor. Voltages VC1, VDS, VL and a load current IRL are shown plotted versus time (in milliseconds or ms). VDS is the drain-to-source voltage of the switch Q. IRL is the load current (in milli-Amps or mA) through the static 90Ω resistor. The simulation results correlated well with corresponding breadboard results (not shown).

FIGS. 7-10illustrate various electronic devices using a converter700implemented according to any of the configurations described herein. The converter700may be implemented as a quasi-Z-source converter as described herein. As shown inFIG. 7, the converter700receives VAC and drives any type of DC load703. As shown inFIG. 8, the converter700receives VAC and charges a battery or battery bank801including one or more rechargeable batteries. As shown inFIG. 9, the converter700receives VAC and provides current to one or more light-emitting diodes (LEDs)901. As shown inFIG. 10, the converter700receives VAC and provides current to a coil1001or the like to generate a magnetic field for an electric motor1003or the like.

FIG. 11is a block diagram of an electronic device1100including the converter700configured in a similar manner as that shown inFIG. 9for providing current to one or more LEDs901. In this case, a conventional line dimmer1102receives VAC (e.g., AC line voltage) and provides an AC conductive angle modulated voltage or “chopped” voltage VACMOD, which is provided to the input of the converter700. In one embodiment, the line dimmer circuit1102operates to selectively chop one or both of the leading edge and the trailing edge of VAC, depicted at1101, at any phase angle between 0 and 180 degrees for every half cycle (i.e., 180 degrees), to provide VACMOD. An exemplary form of VACMODis depicted at1103in which the leading edge is chopped during every half cycle. In one embodiment, the line dimmer circuit1102uses a TRIAC (not shown) or the like to delay the VAC wave shape near zero until the predetermined phase angle. The greater the dimmer phase angle, the more VAC is chopped or zeroed to reduce the voltage of VACMOD. Once the phase angle is reached per half cycle, VAC steps up to the line voltage (e.g., the TRIAC conducts) and the remaining portion of VAC is output to the converter700.

The converter700provides an advantage for dimming operation as compared to a conventional line dimmer circuit. The LEDs901turn off twice per cycle of VAC near the zero crossing. The converter700regulates the LED current. In this case, the average LED current and the corresponding amount of light output are proportional to the dimmer phase angle. Conventional LED dimmers use complex control to derive the dimming phase angle and then regulate the average LED current in proportion to the phase angle. The converter700does not use complex control and automatically regulates the average LED current in proportion of the phase angle.

A converter according to one embodiment converts an AC voltage to a regulated output current provided to a load. The converter includes first through fifth nodes and a reference node coupled to the first node. The load is for coupling between the first and second nodes in parallel with a filter capacitor. The converter further includes a rectifier network for rectifying the AC voltage and for providing a rectified voltage on a third node, a second capacitor coupled between the third and fourth nodes, a first inductor coupled between the third and fifth nodes, a third capacitor coupled between the fifth node and the reference node, a second inductor coupled between the second and fourth nodes, and a first diode having an anode coupled to the fourth node and a cathode coupled to the fifth node. The converter further includes a current sensing device for sensing current which flows from the reference node to the fourth node through the second inductor and for providing a sense signal indicative thereof. The converter further includes a switching transistor having a first current terminal coupled to the third node, a second current terminal coupled to the reference node, and having a control terminal. The converter includes a hysteretic current mode controller which is coupled to the third node and to the control terminal of the switching transistor and which receives the sense signal. The converter controls the switching transistor based on the sense signal to regulate the current through the second inductor.

An electronic device according to one embodiment includes a Z-type converter, a current sensor, a DC load, and a controller. The Z-type converter includes a bridge rectifier, first and second capacitors, first and second inductors, a first inductor and an electronic switch. The rectifier rectifies an AC voltage to provide a rectified voltage on a first node. The first capacitor is coupled between the first node and a second node. The first inductor is coupled between the first node and a third node. The second capacitor is coupled between the third node and a fourth node having a reference voltage level. The second inductor is coupled between the second node and a fifth node. The first diode has an anode coupled to the second node and a cathode coupled to the third node. The electronic switch has a first current terminal coupled to the first node, a second current terminal coupled to the fourth node, and has a control terminal. The current sensor senses current from the fourth node to the fifth node and through the second inductor and provides a proportional sense signal. The DC load includes a filter capacitor and is coupled between the fourth and fifth nodes. The controller is coupled to the third node, receives the sense signal, and is coupled to the control terminal of the electronic switch. The controller controls the electronic switch to maintain relatively constant current through the second inductor.

A method of converting an AC input voltage to a DC output with a regulated output current using a converter is disclosed. The converter includes a first inductor coupled between first and second nodes, a first capacitor coupled between the second node and a reference node, a diode having an anode coupled to a third node and a cathode coupled to the second node, a load network including a filter capacitor coupled between the reference node and a fourth node, a second inductor coupled between the third and fourth nodes, and a switch having current terminals coupled between the first and reference nodes and having a control terminal. The method includes rectifying the AC input voltage to provide a rectified voltage between the first and third nodes, monitoring voltage of the second node, monitoring second inductor current flowing through the second inductor and providing a sense signal indicative thereof, turning on the switch when the sense signal indicates that the second inductor current falls to a valley current level while the voltage of the second node is at least a predetermined minimum level, and turning off the switch when the voltage of the second node is less than the predetermined minimum level and when the sense signal indicates that the second inductor current rises to a peak current level while the voltage of the second node is at least the predetermined minimum level.

Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for providing the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the following claim(s).