Semiconductor element and methods for manufacturing the same

A semiconductor element and method are provided such that the method includes providing a processed substrate arrangement including a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate. The method further includes release etching for generating a kerf in the metallization layer structure at a separation region in the processed semiconductor substrate, the separation region defining a border between a die region of the processed substrate arrangement and at least a second region of the processed substrate arrangement.

FIELD

The present disclosure relates generally to semiconductor elements and to methods for manufacturing the same, and, more particularly, to a dual use of microelectromechanical system (MEMS) release etch and passivation.

BACKGROUND

The term microelectromechanical system (MEMS) is often used to refer to small integrated devices or systems that combine electrical and mechanical components.

MEMS may be used as, for example, actuators, transducers or sensors, e.g., pressure sensors, loudspeakers or microphones. Pressure sensors are nowadays mass products in automobile electronics and consumer goods electronics. Many of these applications systems are used in which the sensor is integrated in an application-specific integrated circuit (ASIC). In particular, MEMS are manufactured in high numbers on a wafer at a time. The processing includes separation of the MEMS from each other.

SUMMARY

Exemplary embodiments provide a method in which a processed substrate arrangement including a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate is provided. Release etching is performed from a surface of the metallization layer structure towards the processed semiconductor substrate, for generating a kerf in the metallization layer structure at a separation region in the processed semiconductor substrate, the separation region defining a border between a the region of the processed substrate arrangement and at least a second region of the processed substrate arrangement. The release etching can also be optionally used to release a functional element which is arranged at the processed semiconductor substrate.

Further exemplary embodiments provide a method in which a processed substrate arrangement is provided. The processed substrate arrangement includes a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate structure, the metallization layer structure including a kerf, the kerf being arranged in the metallization layer structure at a separation region in the processed semiconductor substrate, the separation region defining a border between a die region of the processed substrate arrangement and at least a second region of the processed substrate arrangement.

Optionally, the metallization layer structure may further include an optional notch, the notch releasing an optional functional element which is arranged at the processed semiconductor substrate.

The method further includes depositing a passivation layer (e.g., an insulator layer) at a first surface (e.g., a notch surface) of the optional notch and at a second surface (e.g., a kerf surface) of the kerf.

Further exemplary embodiments provide a semiconductor element including a processed substrate arrangement including a processed semiconductor substrate and a metallization layer arrangement. The semiconductor element further includes a passivation layer arranged at an outer border of the processed substrate arrangement. The semiconductor element may further include an optional functional element arranged at the processed semiconductor substrate.

By a double use of etching steps or passivation steps, performance of the separation may be increased such that a wafer yield (i.e., MEMS per wafer) may be high and such that mechanical defects of the MEMS due to the separation may be low.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before exemplary embodiments are described in detail referring to the accompanying figures, it is to be pointed out that the same or functionally equal elements are given the same reference numbers in the figures and that a repeated description for elements provided with the same or similar reference numbers is typically omitted. Hence, descriptions provided for elements having the same reference numbers are mutually exchangeable and applicable.

Microelectromechanical system (MEMS) may be manufactured in silicon technology. MEMS may be configured for operating as sensors, actuators and/or transducers and may optionally comprise at least one functional element such as a membrane, a temperature element or other components to be connected with a physical, chemical and/or electrical influence (e.g., media). For example, a pressure sensor may comprise a membrane to be connected with a media in which the pressure shall be measured. Microphones or loudspeakers may comprise a membrane to sense or excite sound waves. Alternatively or in addition, a temperature probe may be exposed and connected to a media in which the temperature shall be measured.

Some MEMS including such a functional element may be arranged or attached at a semiconductor substrate. For example, the semiconductor substrate may be a locally doped or undoped silicon substrate but may also comprise other materials such as gallium arsenide (GaAs). For operating the MEMS and thereby the functional element a metallization layer structure may be arranged at the processed semiconductor substrate to obtain, receive and/or process electrical signals to or from the functional element, i.e., to operate the functional element.

For example, the optional functional element may be arranged or generated at the semiconductor substrate during processing. Other electrical and/or mechanical components may be processed to or at the semiconductor substrate to obtain a processed semiconductor substrate. The processed semiconductor substrate may be covered by a plurality of layers comprising semiconductor materials, insulator materials and/or metal materials.

Processing the semiconductor substrate and/or arranging the metallization layer structure may be denoted as back end of line (BEOL) process. The BEOL process may be performed, for example, after a front end of line (FEOL) process has been performed during which the semiconductor substrate may be patterned, for example, to obtain devices or elements such as transistors, capacitors, resistors or the like in the semiconductor substrate.

Usually, a plurality of semiconductor elements is manufactured or fabricated simultaneously at a wafer. After manufacturing or fabricating the plurality of semiconductor elements (chips) the semiconductor elements are separated from each other which is also referred as forming dies (dicing). Dicing may be performed, for example, by etching, cutting and/or breaking (cracking) the wafer into parts to separate (singularize) the single components.

Breaking the wafer may lead to cracks in BEOL layers which may lead to rejections during production, a shortened lifetime of the product or operational drifts due to media affecting the optional functional element through the cracks.

FIG. 1illustrates a schematic flow chart of a method100which may be used for fabricating or manufacturing a semiconductor element.

The method100comprises providing a processed substrate arrangement at a step110of the method100. The processed semiconductor substrate comprises a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate. The metallization layer structure may comprise a plurality of layers wherein one or more of those layers may comprise a metal material such as gold, platinum, copper, silver, tungsten, aluminum, other materials and/or a combination thereof. The metallization layer structure may be arranged at the main surface of the processed semiconductor substrate, for example, during a BEOL process.

The method100further comprises a step120comprising a release etching. The release etching may be performed from a surface of the metallization layer structure towards the processed semiconductor substrate such that a kerf is generated in the metallization layer structure at a separation region in the processed semiconductor substrate. The separation region may define a border between a die region of the processed substrate arrangement and at least a second region (e.g., other chip regions or the like) of the processed substrate arrangement.

Further, the release etching may be also performed from the surface of the metallization layer structure towards the processed semiconductor substrate such that an optional functional element which is arranged at the processed semiconductor substrate is released (uncovered or exposed).

The release etching may be performed, for example, by a dry or wet etch process which is configured for selectively removing the metallization layer structure at a region of an optional notch (trench) etched towards the optional functional element and at a region of the kerf. The kerf may be arranged such that it overlaps partially or essentially with the separation region. The separation region may be, for example, a predetermined breaking line, a predetermined saw line or a predetermined etching line at which the die region may be separated in later steps. The kerf may thus be denoted as a dicing street referring to a street-like structure (kerf) in the metallization layer structure. Simplified, by forming the kerf, the metallization layer structure is removed at least partially in the separation region. To summarize, the release etching may be a BEOL etching step for releasing the dicing streets of the wafer so that the realization of the following dicing step can be facilitated.

The optional notch and the kerf may be formed by a trench forming processes, such as by a dry etching process, a wet etching process or by a physical or a chemical etching processes. Thus, both, the kerf and the optional notch may also be referred to as a trench but are denoted as kerf and notch for the sake of clarity.

The method100further comprises an optional step130. The step130comprises depositing a passivation layer at a first surface (notch surface) of the optional notch (releasing the optional functional element) in the metallization layer structure and at a second surface (kerf surface) of the kerf. The first surface may be obtained at least partially during the release etching for releasing the functional element, i.e., when forming the notch. The second surface may be obtained, for example, at least partially by generating the kerf. The first surface and the second surface to be obtained at least partially may be understood as there may be additional steps between the step120and the step130, for example, for increasing (enlarging) the notch or the kerf such that a position and/or a size of the surfaces in the metallization layer structure and/or at the processed semiconductor substrate may be modified by this additional step. The passivation layer may be deposited at the first and second surface obtained after the step120or after the additional steps. The first surface may comprise one or more side wall structures of the notch in the metallization layer structure and/or a surface of the functional element, the surface defined by the notch. The second surface may comprise one or more side wall structures of the kerf in the metallization layer structure and/or a (bottom) surface thereof or of the processed semiconductor substrate. The release etching may be used for obtaining the kerf.

Optionally, the notch and the kerf may be etched during the release etching120, simultaneously. Simplified, the release etching which may be used for releasing the functional element may be double-used for obtaining the kerf. The double use of the release etching allows for a high process performance with low or no additional amount in time or costs.

The kerf allows for increased performance during separation of the die as the metallization layer structure (arrangement) is removed at the separation region such that the metallization layer structure is prevented from taking damage (e.g., cracks) during sawing or breaking the processed semiconductor substrate.

FIG. 2shows a schematic flow diagram of a method200which may be used, for example, for fabricating or manufacturing a semiconductor element. The method200comprises an optional step210. The step210comprises an etching (e.g., a release etching) from a surface of the metallization layer structure towards the processed semiconductor substrate for generating a kerf in the metallization layer structure at the separation region. The step210may also comprises an etching from a surface of the metallization layer structure towards the processed semiconductor substrate, for releasing the optional functional element by generating the notch in the metallization layer structure. The step210may be equal or essentially equal when compared to the step120.

The method220comprises a step220comprising providing a processed substrate arrangement. The processed substrate arrangement comprises a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate, the metallization layer structure. The metallization layer structure may comprise an optional notch and a kerf, the optional notch releasing an optional functional element which is arranged at the processed semiconductor substrate. The kerf is arranged in the metallization layer structure at a separation region in the processed semiconductor substrate. The notch and/or the kerf may be obtained, for example, by the step210or other processes. The separation region may define a border between a die region of the process substrate arrangement and at least a second region of the processed substrate arrangement. For example, the step220may comprise providing an etched and processed semiconductor substrate obtained when performing step120or step210.

The method200comprises a step230in which a passivation layer is deposited at a first surface (e.g., a notch surface) of the notch and at a second surface (e.g., a kerf surface) of the kerf. The step230may be equal or essentially equal when compared to the step130.

The passivation layer may comprise a passivation or seal ring material such as silicon oxide, silicon nitride or other materials. By passivating the surfaces of the notch and the kerf, a passivation of the metallization layer structure and, in particular, a protection of the layers thereof may be obtained. Further, short circuits or the like between layers of the metallization layer structure may be prevented. Alternatively or in addition, the passivation layer arranged at the surface of the kerf allows for a high protection of the device during separation of the die from further regions of the wafer (processed substrate arrangement). The kerf may define at least partially a separation pathway (e.g., a breaking line) of the metallization layer structure when the processed semiconductor substrate is separated, e.g., sawn or broken.

The kerf and the notch may be the kerf and the notch obtained when performing or executing method100. Thus, the kerf may allow for a simplified separation of the dies and may alternatively or in addition allow for a reduced and/or controlled distribution or propagation of cracks due to the separation. In particular, the kerf may hamper the propagation of cracks when breaking, separating or dicing the processed semiconductor substrate. Simplified, by providing the kerf in the metallization layer structure and aligned with a separation region (dicing street) of the processed semiconductor substrate, cracks that propagate through the material (e.g., the BEOL material) based on the separation (e.g., dicing) may be avoided or at least reduced. Additionally, the protection of the metallization layer structure obtained by the passivation layer may include but is not limited to a high resistivity against aggressive chemical media. Aggressive or corrosive media may be, for example, acids or bases and/or methane based materials, for example, diiodmethane.

For example, a robustness of silicon nitride used as a material for the passivation layer may be increased when compared to an arrangement of seal rings around the die, when the semiconductor element is configured for being exposed to diiodmethane. Diiodmethane may corrode metal based seal rings, wherein silicon nitride is less or not affected by such a media. Thus, a robustness and, therefore, a lifetime and an accuracy of the semiconductor element may be high. A passivation of surfaces of the notch may be performed sequentially but also simultaneously, i.e., during the passivation step. Such a double-use of the passivation step may allow for a high robustness of the with low or no additional amount in time or costs

Steps of the methods100and200may be combined and/or mutually exchanged with each other. In particular, method100may comprise a step in which the passivation layer is arranged and/or method200may comprise a step in which the kerf is generated.

FIG. 3shows a schematic flow chart of a method300for manufacturing a semiconductor element. The method300comprises an optional step340in which a predetermined breaking line is defined in the separation region. For example, a processed or unprocessed wafer may be provided. Between regions of the wafer, at which a functionality of the semiconductor element will be implemented (processed) at least partially during later steps, the separation region may be implemented by defining borders between different die areas. This may comprise, for example, an etching process for removing material of the wafer in the separation region to obtain a predetermined breaking line in the separation region. A predetermined breaking line may allow for a precise breaking (separation) of the later dies.

Alternatively, a so-called stealth dicing process may be performed for implementing the predetermined breaking line in the separation region. During a stealth dicing process a laser may be used to cut a semiconductor material, for example, the wafer, into pieces (die regions) by internal processing. The stealth dicing process may involve utilization of a laser beam at a wavelength permeable to the semiconductor material. The laser may be focused through an objective lens onto a point within the semiconductor layer. The laser beam may be guided to scan along a dicing line (predetermined breaking line) and/or along the separation region. An optical system used may allow for a high focusing performance capable of condensing light to the diffraction limit and so the high-repetition, short pulsed laser beam may temporally and spatially condense to an extremely localized region in the vicinity of the focal point to deliver a high peak power density. The laser beam permeable to the semiconductor substrate may begin to exhibit high absorption in a localized point when the peak power density exceeds a certain threshold in the light condensing process. The optical system and laser characteristics may allow for controlling this threshold so as to exceed just near the focal point within the semiconductor wafer. The laser beam may selectively machine only certain localized points without damaging the surface and rear sides of the semiconductor substrate. Simplified, a buried (i.e., hidden or stealth) predetermined breaking line may be obtained in the semiconductor substrate. The predetermined breaking line may be obtained, by applying a laser beam from a first main surface (e.g., a front side) and/or from a second main surface (e.g., a back side) of the semiconductor substrate.

Processing the predetermined breaking line, e.g., by performing the step340, may allow for a reduced an amount of damage and/or cracks when compared to a separation process during which the dies are separated by breaking and during which the breaking is performed at the kerf without such a pre-processing.

The method300comprises a step310during which a front end of a line process is performed for processing a main surface region of a semiconductor substrate to obtain the processed semiconductor substrate.

At a step320of the method300, a back end of a line process is performed for creating the metallization layer structure at the main surface of the processed semiconductor substrate.

The method100or the method200is performed at a step330of the method300.

At a step350of the method300the die region is separated from the second region (e.g., other dies) of the processed substrate arrangement by breaking the processed substrate arrangement at the separation region. Performance of the step350may be high when the step340is performed before the step350, for example, after the step330. The step340may also be performed before the step310or320is performed, for example, when a region of the processed semiconductor substrate may be processed (e.g., when the region is uncovered). For example, the laser beam may be guided through the kerf after the kerf has been provided or etched.

FIG. 4ashows a schematic cross-sectional view of a processed substrate arrangement10comprising a processed semiconductor substrate12and a metallization layer structure14which is arranged on a main surface16of the processed semiconductor substrate12. The main surface may be, for example, a side of the wafer comprising a high or even the highest area size. For example but without limitation, this may be a front or a back side of a wafer having a cylindrical shape, wherein a lateral surface is arranged between both main surfaces (i.e., the front side and the back side). The main surface16may be the surface comprising structures processed into the processed semiconductor substrate12, for example, transistors, resistors and/or capacitors.

A functional element18is optionally arranged at the processed semiconductor substrate12. The processed substrate arrangement10may be, for example, provided in the step110. The processed semiconductor substrate12may comprise the predefined breaking line32, for example, in a separation region25and may be obtained when performing the step340.

FIG. 4bshows a schematic cross-sectional view of the processed substrate arrangement10, wherein, when compared to the processed substrate arrangement10shown inFIG. 4a, a kerf22and an optional notch24are formed in the processed substrate arrangement10and at the separation region25, for example, by performing the step120or210. The separation region25may surround a die region27and form a border between the die region27and other parts or regions29of the processed substrate arrangement10.

The optional functional element18is released from the metallization layer structure14at least at a (e.g., top) side and with respect to a surrounding media of the processed substrate arrangement10, i.e., the optional functional element18may be contacted with the media. Alternatively, the notch may leave the functional element at least partially covered.

Although the kerf22is depicted as being etched through the complete metallization layer structure14(i.e., extending to the processed semiconductor substrate12), the kerf22may be formed such that one or more of the metallization layer structure14remains at or in the kerf22. Alternatively, the kerf22may be formed such that the kerf22extends into the semiconductor substrate12.

FIG. 4cshows a schematic cross-sectional view of the processed substrate arrangement10after a passivation layer26is arranged at the optional notch24and the kerf22. The passivation layer26may cover (i.e., be arranged at) a surface of the metallization layer structure14defined (i.e., opened) by the kerf22and/or the optional notch24. The passivation layer26may additionally cover a bottom of the kerf22and/or of the optional notch24. The bottom (wherein bottom shall only be understood as an end of the kerf in the processed semiconductor substrate) of the kerf22may be the processed semiconductor substrate12or a layer of the metallization layer structure14. For example, when a depth of the kerf22is lower than a thickness of the metallization layer structure14along a thickness direction28, one or more layers of the metallization layer structure may remain in the separation region. The thickness direction28may be parallel to a surface normal of the processed semiconductor substrate12. The passivation layer26may be arranged at almost all or all of the surfaces of the processed substrate arrangement10such that the passivation layer is arranged at the kerf22, at the notch24and at least partially on other surfaces of the processed substrate arrangement. Alternatively, the passivation layer26may be arranged selectively, for example, at side wall structures of the kerf22and/or of the notch24, wherein parts of the remaining surface(s) of the processed substrate arrangement may remain uncovered by the passivation layer26.

A thickness of the processed substrate arrangement may be, for example, at least 5 μm and at most 1000 μm, at least 10 μm and at most 400 μm or at least 20 μm and at most 300 μm. A thickness of the processed semiconductor substrate may be, for example, at least 2 μm and at most 1000 μm, at least 5 μm and at most 800 μm or at least 100 μm and at most 500, for example between 200 μm and 300 μm. A thickness of the metallization layer structure (BEOL) may be, for example, at least 100 nm and at most 100 μm, at least 1 μm and at most 10 μm or at least 4 μm and at most 6 μm such as 5 μm. The breaking line may comprise a lateral extension, for example, of at least 1 μm and at most 200 μm, of at least 5 μm and at most 100 μm or of at least 10 μm and at most 60 μm. Thus, the breaking line32may comprise a larger lateral extension along a direction perpendicular to the thickness direction28when compared to a lateral extension of the kerf22along the same direction.

Although the passivation layer26is depicted as being arranged at or on the optional functional element18, the functional element18may remain uncovered from the passivation layer26. Alternatively, the passivation layer may, for example, be removed in a subsequent processing step.

Although the passivation layer26is depicted as covering the processed semiconductor substrate12in the kerf22, the processed semiconductor substrate12may remain uncovered by the passivation layer26in the kerf22. Alternatively, the passivation layer may, for example, be removed in a subsequent processing step. Simplified, at least the side walls (side wall structure) of the kerf22and of the optional notch24are covered by the passivation layer26.

The processed semiconductor substrate12comprises, for example, the predefined breaking line32which may be obtained when performing the step340. Although the processed semiconductor substrate12is described as comprising the breaking line32before forming the kerf22and the notch24, the breaking line32may also be obtained during a process performed before separating the die region27from other regions29. For example, first the kerf22may be formed and then the step340may be performed, e.g., by stealth dicing. The predefined breaking line32may be arranged in the separation region25and in the processed semiconductor substrate12before arranging the passivation layer26, for example, after etching the kerf22and/or before arranging or providing the processed substrate arrangement10. Simplified, the processed substrate arrangement10depicted inFIG. 4aorFIG. 4bmay be implemented without comprising the predefined breaking line32.

The kerf22may comprise a width along a lateral direction perpendicular to the thickness direction28of at most 100 μm, of at most 50 μm or at most 30 μm. For example, the kerf may comprise a width of 16 μm (e.g., between 10 and 20 μm). Then, the passivation layer26is arranged subsequently, wherein the passivation layer26may comprise a thickness between 10 to 200 nm, between 20 to 100 or between 40 to 60 nm and may comprise a thickness of about 50 nm. The passivation layer26may comprise other extensions along the thickness direction28, for example, at least 1 nm, at least 1 μm or at least 50 μm. The notch24may comprise a width along the direction perpendicular to the thickness direction28, which is dependent from an extension of the functional element18along that direction and may be, for example, between 10 μm and 2000 μm, between 20 μm and 1000 μm or between 30 μm and 800 μm. For example, when viewed observed from a direction perpendicular to the side view (e.g., a top or bottom view), the notch may comprise an extension of 30×500 μm2. Adjacent to the notch28, for example, between the notch28and the kerf22stress decoupling trenches may be arranged. The stress decoupling trenches may comprise a width along the lateral direction perpendicular to the thickness direction28which may be, for example, at least 1 μm and at most 100 μm, at least 3 μm and at most 50 μm or at least 5 μm and at most 10 μm such as about 8 μm.

FIG. 5shows a schematic top view of the processed substrate arrangement10, wherein the processed substrate arrangement10is, for example, a wafer. The predetermined breaking line32is arranged at the wafer and may define a plurality of die regions34a-bseparated by separation regions comprising the predetermined breaking line32. The separation regions surround the die regions34a-band form a border between them.

FIG. 6shows a schematic cross-sectional view of the processed substrate arrangement10after the step350has been performed. The passivation layer26is arranged at a surface of the metallization layer structure14defined (opened) by kerfs22aand22band the notch24. The protection layer26arranged at the metallization layer structure14allows for protection and/or insulation of the metallization layer structure14.

As exemplarily shown inFIG. 6, the passivation layer26may be arranged selectively, for example, at side wall structures of the kerf22and/or of the optional notch24, wherein parts of the remaining surface(s) of the processed substrate arrangement may remain uncovered by the passivation layer26.

Alternatively, the passivation layer26may be arranged at additional surfaces, e.g. on the functional element18, or at almost all or all of the surfaces of the processed substrate arrangement10such that the passivation layer is arranged at the kerf22, at the optional notch24and at least partially on other surfaces of the processed substrate arrangement (see for exampleFIG. 4c).

The processed semiconductor substrate12may comprise one or more breaking edges33a-bin the separation region and in a region in which the kerf was arranged. The breaking edges33a-bmay extend to the passivation layer26, for example, when the passivation layer26is arranged at a bottom of the kerf, as described above. The passivation layer26allows for a low or at least controlled spreading of cracks which may occur when breaking the processed semiconductor substrate12. This may allow for overcoming cracking problems when using stealth dicing processes configured for preparing separation by breaking.

In other words, the separation region may surround the respective die region34a-b. In the absence of the predefined breaking line32, the separation region still surrounds and forms a border around the die regions34a-b.

FIG. 7shows a schematic cross-sectional view of a processed substrate arrangement70comprising the processed semiconductor substrate12and the metallization layer structure14. The kerf22is arranged such that it separates the metallization layer structure completely at the separation region25. The predefined breaking line32is arranged at the complete separation region25but may alternatively also exceed the separation region25or be arranged only partially in the separation region25.

The kerf22and the notch24are etched such that they comprise a conical shape, i.e., an extension along a lateral direction34perpendicular to the thickness direction28may vary along the thickness direction28. This may also be referred to as the kerf22comprising a taper (angle). The taper may comprise an angle value of at least 30°, at least 60° or at least 80°, such as 84°. For example, the metallization layer structure14may comprise a thickness of 5 μm. At the processed semiconductor substrate12, the kerf22may comprise a width (e.g., 16 μm) that is reduced by approximately 500 nm per edge (for example and without limitation: left and right, e.g., to 15 μm) when compared to a width of the kerf22at a surface of the metallization layer structure14averted from the processed semiconductor substrate12. The extension along the lateral direction34may decrease towards the processed semiconductor substrate12but may also increase or remain constant. Thus, exemplarily assuming a taper of 84° and a BEOL height of about 5 μm, the bottom dimension of the kerf22is about 500 nm/edge smaller than the top dimension. Thus, assuming a kerf22with a top with of 16 μm, the kerf has a bottom dimension of about 15 μm.

The processed substrate arrangement70may be obtained, for example, by performing one of the steps120,210or220.

The kerf22may be obtained by the release etching, wherein the kerf may define a so-called stealth dicing street, wherein the release etching may stop, for example, on a last FEOL module, i.e., a FEOL layer adjacent to the processed substrate layer12.

The notch24may be etched simultaneously with the kerf22, wherein the etching process may stop on the functional element18, for example, a MEMS sensor.

The processed substrate arrangement70comprises a seal ring36, for example, comprising a metal material such as copper extending through one, more or even all of the layers of the metallization layer structure14. The seal ring36is configured for protecting the metallization layer structure14arranged between the seal ring36and the notch24but may suffer, for example, from humidity or an aggressive environment when brought into contact therewith. A contact may be obtained, for example, by cracks resulting from separation by breaking.

Without a passivation at the kerf, the seal ring36may corrode as humidity enters the oxide layers and reaches the metal, especially in pre-molded packages. Apart from this obvious reliability issue, the corrosion may additionally cause stress and lead to sensor drifts. This can be avoided by the above described passivation, e.g., using silicon nitride (SiN) which is a proven humidity blocking layer. Simplified, the MEMS release etch is applied both on the MEMS area and the dicing area. The MEMS passivation is applied (on the whole wafer), becoming effective both on the MEMS device and the side-wall of the BEOL (metallization layer structure) at the chip edge. This may be obtained without extra manufacturing costs, without a change of an integration scheme of the obtained semiconductor element, without a chip area penalty while allowing for an improved crack guidance, especially when using stealth dicing, while reducing a dicing street dimension, while obtaining an improved media robustness of the BEOL as the BEOL side-wall is protected by passivation nitride. Further, an improved (reduced) humidity drift may be obtained.

The metallization layer structure14may be covered with a resistive layer38, for example, comprising a polymer material or any other appropriate material. The metallization layer structure14may comprise a plurality of insulating layers42a-hseparated from each other by a plurality of layers44a-i. The notch24partially releases the functional element18. The insulating layers42a-hmay comprise, for example, a silicon oxide material. The layers44a-imay comprise, for example, a silicon nitride material. The functional element18may comprise, for example, a silicon material. The layer structure may comprise less or further layers. The insulating layers may comprise a thickness (extension along the thickness direction) of, for example, at least 1 nm and at most 2000 nm, at least 5 nm and at most 1500 nm or at least 10 nm and at most 1000 nm.

The metallization layer structure further comprises an optional seal ring36which may comprise a metal material. The seal ring may surround an area of the functional element18. Although the seal ring36is depicted as being arranged only with respect to some of the layers of the metallization layer structure, the seal ring may also be arranged with respect to other or even all of the layers. The sealing ring may have a thickness between 5 and 20 μm or between 7 and 11 μm and may comprise a thickness of about 9 μm.

InFIG. 7, an indication shows the different materials exemplarily used for the different structures and elements of the processed substrate arrangement70. This indication is only exemplary, wherein other materials having a comparable functionality may be alternatively used.

FIG. 8shows a schematic cross-sectional view of the processed substrate arrangement70after the insulating layer26has been arranged at surfaces of the metallization layer structure14defined by the kerf22and the notch24and on the functional element18. This allows for a better crack guidance when breaking the processed semiconductor substrate12at the separation region24and for a protected die etch defined by the kerf22. The passivation layer26further allows for a protection of the metallization layer14at the notch25(side wall thereof) and of the functional element18. Breaking the processed substrate arrangement at the kerf22may allow for obtaining a structure according toFIG. 6.

The passivation layer26may be arranged (generated) at the kerf22and at the notch24simultaneously. This allows for a reduced effort in time and/or costs, for example, an additional effort when compared to an arrangement of the insulating layer26at the notch24, an additional effort in time may be zero or almost zero when simultaneously depositing the passivation layer26at the kerf22.

In other words, an integrated pressure sensor may be manufactured using stealth dicing as a separation technique and a thin SiN final passivation layer in the sensor region. Stealth dicing (SD) may be a favorable separation process as it may require only a narrow kerf and may thus save wafer area. Additionally, dicing liquid or debris may be prevented which may contaminate the sensor membrane. Above described embodiments allow for overcoming uncontrolled breaking in BEOL layers which may be a major risk for many technologies as it is sensitive to the FEOL and BEOL stack in the kerf.

Films such as high film-stress high density plasma (HDP) oxides introduced in sensor processes may even enhance SD-caused delamination which may yield severe yield loss. This severe yield loss may be reduced or even eliminated when executing above described embodiments. Above described embodiments also allow for a higher robustness of sensors which may be installed in pressure-sensing applications in harsh environments. In harsh environments standard pads and metal seal rings at chip edges may by insufficient protection, wherein the above described protection by the passivation layer may allow for such applications.

In above described embodiments, a dual use of processes for the etching (for etching the kerf and the notch) and for passivating (the edges of the kerf and of the notch) are described. The MEMS release etch may be used to remove the BEOL-insulating dielectric layer (IDL) stack in the chip separation area (dicing street, separating region) at least partially or even entirely and may thus guide the crack line (or saw in case of conventional sawing) more precisely and may thus avoid uncontrolled cracking. Dicing—independently of the method used—may effectively become separation of the substrate (processed semiconductor substrate) only.

Hence, the dicing street dimension can be reduced which directly translates into a yield win (e.g., more chips per wafer).

Further, the thin MEMS passivation layer that is deposited after the MEMS release etch will have no effect on the chip separation but inherently may seal the outer BEOL stack and thus may improve the media-robustness of the die etch. This may become vital for pressure-sensing application in harsh environments; in particular, if diiodmethane robustness is required and if a standard metal seal ring (copper) may not protect the chip sufficiently.

Uncontrolled cracking when using stealth dicing may be overcome with the above described embodiments. Above described embodiments use a MEMS release etch to remove the IDL in the SD area and thus improve the SD yield. Furthermore, a thin MEMS passivation may also be used to seal the die edge and thus prohibit humidity uptake (absorption) and metal corrosion of the guard ring. Thus, above described embodiments may refer to a combination of MEMS release etch and MEMS passivation for application in MEMS area and dicing street (chip edge) for improved chip separation yield, MEMS quality and chip edge seal. This may also be regarded as a dual use of MEMS release etch and passivation.

The above described embodiments are merely illustrative and it is understood that modifications and variations of the arrangements and the details described herein will be apparent to others skilled in the art. It is the intent, therefore, to be limited only by the scope of the impending patent claims and not by the specific details presented by way of description and explanation of the exemplary embodiments herein.