Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs)

Various embodiments of mechanisms for forming through a three-dimensional integrated circuit (3DIC) structure are provided. The 3DIC structure includes an interposer bonded to a die and a substrate. The interposer has a conductive structure with through silicon vias (TSVs) connected to a patterned metal pad and a conductive structure on opposite ends of the TSVs. The pattern metal pad is embedded with dielectric structures to reduce dishing effect and has regions over TSVs that are free of the dielectric structures. The conductive structure has 2 or more TSVs. By using a patterned metal pad and 2 or more TSVs, the reliability and yield of the conductive structure and the 3DIC structure are improved.

BACKGROUND

Three-dimensional integrated circuits (3DICs) have been created to further shrink integrated dies and packages. New packaging technologies have begun to be developed to enable 3DICs. These relatively new types of packaging technologies for semiconductors face manufacturing challenges.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Since the invention of the integrated circuit, the semiconductor industry has experienced continual rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing for the integration of more components into a given area.

These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.

Three-dimensional integrated circuits (3D ICs) have been therefore created to resolve the above-discussed limitations. In some formation processes of 3D ICs, two or more wafers, each including an integrated circuit, are formed. The wafers are sawed to form dies. Dies with different devices are packaged and are then bonded with the devices aligned. Through silicon vias (TSVs) and Through-package-vias (TPVs), also referred to as through-molding-vias (TMVs), are increasingly used as a way of implementing 3D ICs. TSVs and TPVs are often used in 3D ICs and stacked dies to provide electrical connections and/or to assist in heat dissipation.

FIG. 1Ais a perspective view of a package structure100including a die110bonded to an interposer120, which is further bonded to another substrate130in accordance with some embodiments. After die110is bonded to interposer120, the packaged structure may be sawed into individual pieces and interposer120would appear to be a semiconductor die. Each of die110and interposer120includes a semiconductor substrate as employed in a semiconductor integrated circuit fabrication, and integrated circuits may be formed therein and/or thereupon. The semiconductor substrate refers to any construction comprising semiconductor materials, including, but not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used. The semiconductor substrate may further comprise a plurality of isolation features (not shown), such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. The isolation features may define and isolate the various microelectronic elements. Examples of the various microelectronic elements that may be formed in the semiconductor substrate include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.); resistors; diodes; capacitors; inductors; fuses; and other suitable elements. Various processes are performed to form the various microelectronic elements including deposition, etching, implantation, photolithography, annealing, and/or other suitable processes. The microelectronic elements are interconnected to form the integrated circuit device, such as a logic device, memory device (e.g., SRAM), RF device, input/output (I/O) device, system-on-chip (SoC) device, combinations thereof, and other suitable types of devices. Interposer120includes through silicon vias (TSVs) or through-package-vias (TPVs), and function as an interposer, in accordance with some embodiments. In some embodiments, interposer120does not include active devices.

Substrate130may be made of bismaleimide triazine (BT) resin, FR-4 (a composite material composed of woven fiberglass cloth with an epoxy resin binder that is flame resistant), ceramic, glass, plastic, tape, film, or other supporting materials that may carry the conductive pads or lands needed to receive conductive terminals. In some embodiments, substrate130is a multiple-layer circuit board. Substrate130includes interconnect structures, in some embodiments.

Die110is bonded to interposer120via connectors (or bonding structures)115, and interposer120is bonded to substrate130via connectors145. If two or more dies, such as die110and other die(s), with different sizes of connectors are bonded to interposer120, the packaging mechanisms could be challenging. TSVs in interposer120assist electrical connection and heat dissipation.

FIG. 1Bshows a cross-sectional view of a die package100′, in accordance with some embodiments. Die package100′ includes a die110Aand a die110B. For example, die110Acould be a central processing unit (CPU) or graphic control unit (GPU), and die110Bcould be a memory device, such as static random-access memory (SRAM) dynamic random-access memory (DRAM), or other types of memory devices. Dies110Aand110Bare connected to a substrate (or interposer)120′ via connectors115Aand115Brespectively. Connectors115Aand115Bare bonding structures formed by bonding the external connectors for dies110Aand110Bwith external connectors of interposer120′. In some embodiments, connectors (or bonding structures)115Aand115Bare formed by bonding micro-bumps (or μ-bumps) on dies110Aand110Bwith μ-bumps112on interposer120′.FIG. 1Cshows a μ-bumps111Aon die110A bonded to a μ-bump112of interposer120′ to form a connector (or bonding structure)115A, in accordance with some embodiments. μ-bumps111Aincludes a copper post113A, an under-bump metallurgy (UBM) layer116A, and a solder layer, which bonds with a solder layer of μ-bump112to form solder layer118A. μ-bump112also includes a copper post114, and an UBM layer117. μ-bumps111Ais formed over a metal pad109Aand μ-bump112is formed over a metal pad119.

In some embodiments, the UBM layer116Aand117include a diffusion barrier layer formed of Ti and a seed layer formed of Cu. In some embodiments, both the diffusion barrier layer, such as a Ti layer, and the seed layer, such as a Cu layer, are deposited by physical vapor deposition (PVD) (or sputtering) methods. The solder layers from connected μ-bump bond to form a solder layer, such as solder layer118A, after a reflow process. A portion of μ-bump111Arests on a passivation layer141and a portion of μ-bump112rests on a passivation layer142. Passivation layers141and142are made of dielectric and yielding material(s), which provide insulation and absorb bonding stress. In some embodiments, passivation layers141and142are made of polymers, such as polyimide, polybenzoxazole (PBO)), or a solder resist.

Examples of bonding structures, and methods of forming them are described in U.S. application Ser. No. 13/427,753, entitled “Bump Structures for Multi-Chip Packaging,” filed on Mar. 22, 2012, U.S. application Ser. No. 13/338,820, entitled “Packaged Semiconductor Device and Method of Packaging the Semiconductor Device,” filed on Dec. 28, 2011, and U.S. application Ser. No. 13/667,306, entitled “Bonded Structures for Package and Substrate,” filed on Nov. 2, 2012. The above-mentioned applications are incorporated herein by reference in their entireties.

FIG. 1Bshows that interposer120′ includes a silicon substrate121with TSVs125. Interposer120′ includes an interconnect structure122on one side of the silicon substrate121and bumps126on the opposite side of the interconnect structure122. Bumps126are similar to connectors145inFIG. 1A. Interconnect structures122connect TSVs125to external connectors, μ-bumps112. Interconnect structures122include conductive interconnect structures, such as metal pads, metal lines and vias. The conductive interconnect structures are insulated by dielectric layers. For example, the conductive interconnect structures include metal lines, such as M1, M2and M3, and vias, such as V1, V2, and V3. The conductive interconnect structures also include metal pads, such as metal pads127and119. In some embodiments, metal pads127are formed at M1level. Metal pads127are connected to TSVs125and metal pads119are connected to μ-bumps112. TSVs125are connected to respective UBM structures (a conductive structure)129, which connect with bumps126. In some embodiments, bumps126are C4bumps, which are made of solder. The UBM structure129is made of conductive material. The conductive material may be formed by a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, an electro-chemical plating process, or a combination thereof. Examples of conductive material include, but are not limited to, titanium, nickel, copper, tungsten, aluminum, silver, gold, or a combination thereof. In some embodiments, the UBM structure is made of Ti. UBM structures129are separated from each other by a passivation layer124. In some embodiments, passivation layer124is made of polymers, such as polyimide, polybenzoxazole (PBO), or a solder resist. Passivation layer124is made of a yielding material to protect interposer120′ and bump126′ from bonding stress.

Interposer120′ is connected to substrate130′ via bumps126. Each bump126is connected to UBM structure129on interposer120′ and to a metal pad131on substrate130′. Metal pads131are separated from each other by a passivation layer132. Passivation layer132is made of polymers, such as polyimide, polybenzoxazole (PBO), or a solder resist. Passivation layer132is made of a yielding material to protect interposer120′ and substrate130′ from bonding stress resulting from the bonding process.

FIG. 1Bshows at least 2 TSVs125are connected to a metal pad127on interposer120′ and to an UBM structure129. Two or more TSVs125connecting to a metal pad127on interposer120′ and to an UBM structure129are more desirable than one TSV125because they improve the yield in the event there are issues with one of the connecting TSVs125. For example, TSVs125could have poor contact with metal pad127or UBM structure129. Having two or more TSVs to connect with metal pad127and UBM structure129improves fault tolerance and yield.

FIG. 1Balso shows that an underfill143is formed between dies110.A,110B, and interposer120′. An underfill146is also formed between interposer120′ and substrate130′. Underfill143protects connectors (or bonding structures)115A and115B. Similarly, underfill146protects the bumps126.FIGS. 1Balso shows that a molding compound144is formed to surround, cover, and protect dies110A,110B, and interposer120′.

As mentioned above, TSVs125are connected to metal pads127. Metal pads127are formed over TSVs125after TSVs125are formed in substrate121.FIGS. 2A-2Dshow cross-sectional views of a sequential process of forming a metal pad127over TSVs125, in accordance with some embodiments.FIG. 2Ashows TSVs125formed in substrate121. The formation of TSVs125involves forming deep trenches. The widths W1of the trenches for TSVs125are in a range from about 5 μm to about 15 μm some embodiments. The depths D1of the trenches for TSVs125are in a range from about 40 μm to about 120 μm some embodiments. A dielectric liner layer201is used to line the walls of the trenches and also the surface of substrate121, as shown inFIG. 2A. The dielectric liner layer201is made of silicon oxide, in some embodiments. In some embodiments, the thickness of the dielectric liner layer201is in a range from about 0.3 μm to about 1.5 μm some embodiments.

A barrier layer202is then deposited over the dielectric liner layer201. The barrier layer202may be made of Ti, Ta, TiN, TaN, or a combination thereof. In some embodiments, the thickness of the barrier layer202is in a range from about 0.05 μm to about 0.5 μm some embodiments. The remaining portions of the trenches are filled with a conductive layer203, which is made of a conductive material with low-resistivity, such as Cu, Cu alloy, Al, Al alloy, or other applicable material(s). In some embodiments, the thickness of the conductive layer203(measured on the substrate surface) is in a range from about 4 μm to about 14 μm some embodiments. The excess conductive layers203and202outside of the trenches are then removed, such as by a chemical-mechanical polishing (CMP) process. The TSVs125are formed as shown inFIG. 2A.

After TSVs125are formed, a dielectric stack204is formed over exposed dielectric liner layer201and the top surfaces of TSVs125. In some embodiments, the dielectric stack204includes an etch stop layer205, and an inter-level dielectric (ILD) layer206. In some embodiments, the etch stop layer205is made of SiC, SiN or SiON. The etch stop layer205has a thickness in a range from about 200 nm to about 800 nm, in some embodiments. The ILD layer206may be made of silicon oxide, or dielectric material with low dielectric constant (low-k). The ILD layer206could be doped. In some embodiments, the k value of the ILD layer206is less than 3.5. In some embodiments, the k value of the ILD layer206is less than 2.5. The ILD layer206has a thickness in a range from about 700 nm to about 1000 nm, in some embodiments.

After the dielectric stack204is formed, the dielectric stack204is patterned to form an opening208for metal pad127. The patterning process involves applying a photoresist layer over substrate201, a lithography process, and an etching process.FIG. 2Ashows the dielectric stack204after it is patterned. In some embodiments, the opening208has a width W2in a range from about 10 μm to about 50 μm some embodiments. The height D2of the dielectric stack204is in a range from about 100 nm to about 3000 nm, in some embodiments.

After the dielectric stack204is patterned, a barrier-seed layer209is formed to cover the surface of the dielectric stack204and also to line opening208, as shown inFIG. 2Bin accordance with some embodiments. In some embodiments, the barrier-seed layer209includes a barrier sub-layer and a plating seed sub-layer. The barrier sub-layer is used to prevent copper diffusion and the seed sub-layer is used to enable subsequent copper plating. In some embodiments, the barrier sub-layer is made of Ti, TiN, Ta, TaN, or a combination thereof. In some embodiments, the barrier sub-layer has a thickness in a range from about 10 nm to about 100 nm. In some embodiments, the plating seed sub-layer is made of Cu or Cu alloy. In some embodiments, the plating seed sub-layer has a thickness in a range from about 100 nm to about 500 nm. In some embodiments, each of the barrier sub-layer and plating seed layer is formed by physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, and other applicable processes.

After the barrier-seed layer209is formed, a copper layer210is deposited over the barrier-seed layer209and fills the remaining portion of opening208, as shown inFIG. 2C. The copper layer210is formed by a plating process, in some embodiments. The copper layer210also deposits outside opening208. Copper layer210needs to be removed. In some embodiments, the excess copper layer210and barrier-seed layer209outside opening208are removed by a chemical-mechanical polishing (CMP) process220, as shown inFIG. 2D. After the excess copper layer210and barrier-seed layer209outside opening208are removed, metal pad127is formed.

As mentioned above, the width W2of opening208is in a range from about 10 μm to about 50 μm some embodiments. The width W2of opening208is the width of metal pad127. Due to the width of metal pad127, the CMP process220could cause dishing of the metal pad127, as shown inFIG. 2D.FIG. 2Dshows that center of metal pad127is lower than edges of metal pad127due to CMP dishing effect. The dishing of metal pad127could result in metal stringers between vias formed over metal pad127, which could result in shorting and/or reliability issues lowering the yield.

After the metal pad127is formed, additional processing is performed to complete the formation of interconnect structure122and bump structures, such as μ-bumps112, described above. The back side of substrate121is then grounded to expose TSVs125. Afterwards, the conductive structures129and passivation layer124are formed.

In order to reduce dishing effect, dielectric structures should be inserted in the metal pads, such as metal pad127.FIG. 3Ashows a metal pad127′ with embedded dielectric structures212and213, in accordance with some embodiments. Dielectric structures212and213are made of un-etched dielectric stack204.FIG. 3Ashows4possible locations214(marked by dotted circles) with an underlying TSV125. As mentioned above, 2 or more TSVs are needed between metal pad127and UBM structures129. For each metal pad127, two or more of locations214are connected to TSVs125. Locations214are placed near corners of metal pad127′, because the corner regions are less susceptible to CMP dishing effect. Regions215(marked by dotted lines) surrounding and including locations214of metal pad127′ do not include embedded dielectric structures to provide low resistance and good conductivity in connection to TSVs125.

The center of metal pad127′ is most likely to suffer from dishing effect. As a result, a large dielectric structure213is embedded in the center region of metal pad127′. In some embodiments, the metal pad127′ is shaped as a square with a width WM. Metal pad127′ needs to be large enough to cover TSVs125and provide sufficiently low resistance for structures connected to it. In some embodiments, the WMis in a range from about 30 μm to about 50 μm. The width of dielectric structure213is WD. To avoid dishing effect near center of metal pad127′, WDcannot be too small. In some embodiments, the ratio of WD/WMis in a range from about ¼ to about ½. In some embodiments, the WDis in a range from about 10 μabout 25 μm.

To prevent dishing of the regions217between neighboring regions215, dielectric structures212are embedded.FIG. 3Ashows two dielectric structures (bars)212are formed in each of regions217. The length L212of each dielectric structure (bar)212is about equal to the width WDof dielectric structure213in some embodiments. However, the length L212of dielectric structure212could be wider or narrower than the width WDof dielectric structure213. The dielectric structures212are evenly distributed in regions217. In some embodiments, the width W212of dielectric structures212is in a range from about ⅕ to about ¼ of length L217of region217. In some embodiments, the W212is in a range from about 2 μm to about 5 μm.FIG. 3A′ illustrates a cross-sectional view of metal pad127′ along line3A′-3A′ ofFIG. 3A.

The metal pad127′ with embedded dielectric structures212,213described is an embodiment. Other embodiments are also possible.FIG. 3Bshows a metal pad127″ in accordance with some other embodiments. Metal pad127″ also includes dielectric structures to reduce CMP dishing effect. The dielectric structures are configured differently from metal pad127′. Metal pad127″ includes dielectric structures212″ and213″. Dielectric structure213″ is similar to dielectric structure213. Each region217″ includes one dielectric structure212″, instead of two structures inFIG. 3A. Dielectric structure212″ is wider than dielectric structure212. In some embodiments, the width W212″of dielectric structures212″ is in a range from about ½ to about ⅔ of length L217″of region217″. In some embodiments, the W212″is in a range from about 2 μm to about 5 μm. The length L212″of each dielectric structure (bar)212″ is about equal to the width WD″of dielectric structure213″ in some embodiments. However, the length L212″of dielectric structure212″ could be wider or narrower than the width WD″of dielectric structure213″.

FIGS. 3A and 3Bshow one or two dielectric structures in regions217and217″ respectively. There could be more than 2 dielectric structures in these regions. In addition, the dielectric structures in these regions could be shaped and arranged differently from what have been described above. Studies show that the embedded dielectric structures described above reduce the dishing effect to non-existent or almost non-existent (see, e.g.,FIG. 3A′). As a result, the risk of metal strings between vias is eliminated.

FIG. 4Ashows a perspective view of a conductive structure400, in accordance with some embodiments. The conductive structure400includes a metal pad127, four TSVs125and a UBM structure129. As mentioned above, a bump (126), which could be a C4bump, is connected to UBM structure129(not shown).FIG. 4Bshows a top view of conductive structure400, in accordance with some embodiments. Due to the large size of bump126, the UBM structure129is large, in comparison to metal pad127.FIG. 4Bshows that UBM structure129has a top view in octagonal shape. The width WUof UBM structure129is in a range from about 80 μm to about 100 μm, in some embodiments. The width WUof UBM structure129is larger than the width WMof the metal pad127. The ratio of WM(width of metal pad) to WU(width of UBM structure129for bump126) is in a range from about ⅓ to about ½, in some embodiments.

The conductive structure400inFIGS. 4A and 4Bincludes four TSVs125. As mentioned above, the number of TSVs125connecting metal pad127and UBM structure129for bump126should be more than one to ensure good yield. However, the number of TSVs125could be2,3, or4, depending on the manufacturing need.

FIG. 5shows a process flow of forming a 3DIC structure, in accordance with some embodiments. The process starts after interposers120′ are formed. At operation510, one or more dies, such as dies110Aand/or110Bare bonded to a substrate with interposers, such as interposers120′. After dies110Aand/or110Bare bonded to a substrate with interposers120′, underfill143is applied to fill the space between dies110Aand/or110Band interposers120′. After underfill143is formed, molding compound144is formed to cover the exposed surfaces of interposers120′ and to fill the space between dies110Aand/or110B. A sawing is then performed to separate interposers with bonded dies into individual die packages at operation520. Each die package includes dies110Aand/or110Band interposer120′. The die package is then bonded to substrate130′ at operation530. After die package is bonded to substrate130′, underfill146is filled between the space between the die package and substrate130′ to form 3DICdie package100′.

Various embodiments of mechanisms for forming through a three-dimensional integrated circuit (3DIC) structure are provided. The 3DIC structure includes an interposer bonded to a die and a substrate. The interposer has a conductive structure with through silicon vias (TSVs) connected to a patterned metal pad and a conductive structure on opposite ends of the TSVs. The pattern metal pad is embedded with dielectric structures to reduce dishing effect and has regions over TSVs that are free of the dielectric structures. The conductive structure has anf has more TSVs. By using a patterned metal pad and 2 or more TSVs, the reliability and yield of the conductive structure and the 3DIC structure are improved.

In some embodiments, an interposer structure is provided. The interposer structure includes two or more through silicon vias (TSVs), and a patterned metal pad. The two or more TSVs are physically connected to the patterned metal pad, and the patterned metal pad has embedded dielectric structures. The embedded dielectric structures are not over the two or more TSVs. The interposer structure also includes a conductive structure physically connected to the two or more TSVs on an opposite end from the patterned metal pad.

In some other embodiments, a package structure is provided. The package structure includes a semiconductor die, and an interposer structure connected to the semiconductor die. The interposer structure further comprises two or more through silicon vias (TSVs) and a patterned metal pad. The two or more TSVs are physically connected to the patterned metal pad, and the patterned metal pad has embedded dielectric structures. The embedded dielectric structures are not over the two or more TSVs. The package structure also includes a conductive structure physically connected to the two or more TSVs on an opposite end from the patterned metal pad. In addition, the package structure includes a substrate connected to the interposer.

In yet some other embodiments, a method of forming an interposer structure is provided. The method includes forming two or more through silicon vias (TSVs) in a substrate, and forming a patterned metal pad. The two or more TSVs are physically connected to the patterned metal pad, and the patterned metal pad has embedded dielectric structures. The embedded dielectric structures are not over the two or more TSVs. The method also includes grinding a backside of the substrate to expose the two or more TSVs, and forming a conductive structure on the backside of the structure. The conductive structure is physically connected to the two or more TSVs.