Implementing buried FET below and beside FinFET on bulk substrate

A method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with buried field effect transistors (FETs) below and beside a traditional FinFET on a bulk substrate, and a design structure on which the subject circuit resides are provided. Buried field effect transistors (FETs) are formed on either side and under the traditional FinFET. The gate of the FinFET becomes the gate of the parallel buried (FETs) and allows self alignment to the underlying sources and drains of the buried FET devices in the bulk semiconductor.

FIELD OF THE INVENTION

The present invention relates generally to the data processing field, and more particularly, relates to a method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with a buried field effect transistor (FET) below and beside traditional FinFETs on a bulk substrate, and a design structure on which the subject circuit resides.

DESCRIPTION OF THE RELATED ART

Fin-type field effect transistors (FinFETs) are high speed devices that can be densely packed on a substrate. FinFETs offer relatively high current density transistors but limitations still drive designs to utilize a large number of FinFET fingers to drive large capacitance loads both on die and particularly off die.

A need exists for a method and circuit for implementing an enhanced transistor topology enabling added device drive strength with a buried field effect transistor (FET) below and beside traditional FinFETs on a bulk substrate, for example, increasing current densities per fin and per unit area of transistor.

SUMMARY OF THE INVENTION

Principal aspects of the present invention are to provide a method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with buried field effect transistors (FETs) below and beside traditional FinFETs on a bulk substrate, and a design structure on which the subject circuit resides. Other important aspects of the present invention are to provide such method, circuit and design structure substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.

In brief, a method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with buried field effect transistors (FETs) below and beside a traditional FinFET on a bulk substrate, and a design structure on which the subject circuit resides are provided. Buried field effect transistors (FETs) are formed on either side and under the traditional FinFET. The gate of the FinFET becomes the gate of the parallel buried (FETs) and allows self alignment to the underlying sources and drains of the buried FET devices in the bulk semiconductor.

In accordance with features of the invention, a traditional semiconductor FinFET is formed via traditional FinFET processing and includes forming the FinFET gate, gate dielectric and depositing a blanket spacer film via traditional FinFET processing. The traditional source and drain implants are utilized to dope not only the FinFET sources and drains but also the new buried transistor sources and drains (S/D) diffusions. These areas exist on either side of the FinFET gate material that exists on the sides of the semiconductor fin. The implanted regions are activated via the same anneal or anneals as the base FinFET.

In accordance with features of the invention, process flow is substantially the same as an existing FinFET process flow with only predefined layout shape changes.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In accordance with features of the invention, a method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with buried field effect transistors (FETs) below and beside traditional FinFETs on a bulk substrate are provided.

In accordance with features of the invention, process flow is substantially identical to the existing FinFET process flow with only selected layout shape changes. The present invention allows fabrication of buried field effect transistor (FETs) below and beside a FinFET with no traditional landing areas required to fully land the contacts to the FinFET source and drain as the new buried diffusions on either side advantageously are part of the landing area.

Having reference now to the drawings, inFIGS. 1-5, there are shown example structures and processing steps for implementing an enhanced transistor topology enabling added device drive strength with buried field effect transistors (FETs) formed below and beside traditional FinFETs on a bulk substrate in accordance with the preferred embodiment.

InFIG. 1, there is shown a processing step with a formed FinFET generally designated by the reference character100. The FinFET100is formed using traditional FinFET fabrication technique on a semiconductor substrate102. The FinFET100includes a gate region104formed on a gate dielectric106, a drain region108, and a source region110. FinFET100includes the drain region108and the source region110that are formed without a dog-bone shaped source and drain. For example, for an N type FinFET, the semiconductor substrate102is a P— silicon substrate; or alternatively for a P type FinFET, an N—Si substrate could be used.

InFIG. 2, a next processing step generally designated by the reference character200provides a blanket spacer202. The blanket spacer, such as SiO2spacer film, is applied or deposited over the FinFET100and substrate102.

Referring toFIG. 3, there are shown next doping processing steps generally designated by the reference character300to form first and second buried FETs generally designated by the reference character302. The first and second buried FETs302are formed in the substrate102, with the left and right extensions of the FinFET gate104acting as the gate306of the planar buried FETs. Angled S/D implants, such as ˜45 deg and ˜135 deg angled source/drain implants are provided through the spacer202into the source and drain regions304. The angled S/D implants are utilized to dope the FinFET source and drain and the new buried field effect transistor S/D diffusions304. These S/D diffusion areas304exist on either side of the FinFET drain108and source110regions and form two planar buried FETs in parallel with the FinFET. The implanted S/D diffusion regions304are activated via the same anneals as the base FinFET device that utilize a conventional or traditional process. Subsequent contacting to the gate of all three parallel transistors is made via traditional means.

Referring toFIG. 4, there is shown next step generally designated by the reference character400that includes anisotropically etching to remove the spacer from all horizontal surfaces of the FinFET100and substrate102leaving only sidewall spacer202.

In accordance with features of the invention, the source and drain contacts are one of the greatest advantages of this invention. No traditional landing areas are required to fully land the contacts to the FinFET source and drain as the new buried diffusion on either side advantageously are part of the landing area.

Referring toFIG. 5, there is shown next steps providing circuit structure generally designated by the reference character500that include constructing a respective bar contact that crosses the fin and contacts all three drains, and another all three sources is constructed. A bar contact502to the common drains and another bar contact (not shown inFIG. 5) that crosses the fin and contacts all three common sources is constructed. Circuit structure500nominally requires less total transistor area than a traditional FinFET area and adds significantly to the total transistor current.

Referring now toFIG. 6, there are shown example process steps for implementing the enhanced transistor topology enabling enhanced current capability via added device drive strength with buried field effect transistors (FETs) formed below and beside traditional FinFETs on a bulk substrate in accordance with the preferred embodiments.

As indicated in a block600, a FinFET is formed using traditional fabrication technique on a bulk substrate without a dog-bone shaped source and drain. As indicated in a block602, a blanket spacer is applied to the sidewall and horizontal surfaces of the FinFET and the bulk substrate.

As indicated in a block604, ˜45 deg and ˜135 deg angled source and drain implants are completed through the blanket spacer and into the source and drain regions of buried FETs that are formed on either side and under the FinFET where the gate of the FinFET becomes the gate of each of the buried FETs and allows self alignment to the underlying sources and drains of the buried FETs in the bulk semiconductor. The implanted regions are activated via the same anneal or anneals as the base FinFET.

As indicated in a block606, anisotropically etching is provided to remove the blanket spacer from the horizontal surfaces of the FinFET and the bulk substrate.

As indicated in a block608, a first bar contact to all three drains is constructed, and another bar contact to all three sources is constructed. The FinFET and first and second buried FETs are connected in parallel, having the common source connection and the common drain connection. The parallel-connected FinFET with first and second buried FETs enable enhanced current capability, and no traditional landing areas are required to fully land the contacts to the FinFET source and drain as the new buried diffusion on either side advantageously are part of the landing area with the enhanced transistor topology of the invention.

FIG. 7shows a block diagram of an example design flow700that may be used for high speed serial link circuit and the interconnect chip described herein. Design flow700may vary depending on the type of IC being designed. For example, a design flow700for building an application specific IC (ASIC) may differ from a design flow700for designing a standard component. Design structure702is preferably an input to a design process704and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure702comprises circuit structure400in the form of schematics or Hardware Description Language (HDL), a hardware-description language, for example, Verilog, VHSIC Hardware Description Language (VHDL) where VHSIC is Very High Speed Integrated Circuit, C, and the like. Design structure702may be contained on one or more machine readable medium. For example, design structure702may be a text file or a graphical representation of circuit structure500. Design process704preferably synthesizes, or translates, circuit structure500into a netlist706, where netlist706is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist706is resynthesized one or more times depending on design specifications and parameters for the circuits.

Design process704may include using a variety of inputs; for example, inputs from library elements708which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology, such as different technology nodes, 22 nm, 14 nm, and smaller, design specifications710, characterization data712, verification data714, design rules716, and test data files718, which may include test patterns and other testing information. Design process704may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, and the like. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process704without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.

Design process704preferably translates embodiments of the invention as shown inFIGS. 1-5, and6along with any additional integrated circuit design or data (if applicable), into a second design structure720. Design structure720resides on a storage medium in a data format used for the exchange of layout data of integrated circuits, for example, information stored in a Graphic Data System (GDS) or GDSII (GDS2), Global Level-1 (GL1), Open Artwork System Interchange Standard_(OASIS), or any other suitable format for storing such design structures. Design structure720may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce embodiments of the invention as shown inFIGS. 1-5, and6. Design structure720may then proceed to a stage722where, for example, design structure720proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, and the like.