Method of manufacturing a semiconductor package and semiconductor package having an electrode pad with a small pitch

A board on which a wiring having an electrode pad is formed is prepared. A resist film is formed on the board in order to cover the wiring and then the resist film is left on the electrode pad through patterning. An inorganic insulating film is formed on the board in order to cover the wiring and then the resist film is removed, thereby removing the inorganic insulating film provided on the resist film to leave the inorganic insulating film between the wirings. A solder resist layer is formed on the board in order to cover the wiring and then the electrode pad is exposed.

This application claims priority to Japanese Patent Application No. 2009-081922, filed Mar. 30, 2009, in the Japanese Patent Office. The Japanese Patent Application No. 2009-081922 is incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor package and a manufacturing technique thereof, and more particularly to a technique which is effective for an application to a semiconductor package having an electrode pad with a small pitch which is formed on a printed board.

RELATED ART

JP-A-2001-326466 Publication (Patent document 1) has disclosed a technique for forming an insulating intermediate layer between an inner layer plate provided with a conductive pattern and a buildup resin layer, thereby reinforcing the buildup resin layer.

A semiconductor package has a printed board (an organic board) to be a core, a buildup resin layer formed on both surfaces or one of the surfaces in the printed board, and a wiring layer and a via which are formed on the buildup resin layer, for example.

FIGS. 16 and 17are views for explaining a semiconductor package investigated by the inventors, illustrating a section of a main part of the semiconductor package. InFIG. 16, the semiconductor package has an electrode pad102aformed on a buildup resin layer101, a solder resist layer103formed as a top surface layer of the semiconductor package in order to cover the electrode pad102a, and an electrode bump104formed on the electrode pad102a. InFIG. 17, moreover, the semiconductor package has an uppermost wiring layer102formed on the buildup resin layer101, and the solder resist layer103formed to cover the wiring layer102.

In the semiconductor package, for example, the electrode bump104is set to have a small pitch of approximately 150 μm, a distance between the electrode pads102ais set to be approximately 30 μm and L/S (line and space) of the wiring102is set to be equal to or smaller than 10 μm in some cases. In the design rule, a migration between the electrode pads102aor a migration between the wirings102causes a problem so that a reliability of the semiconductor package is influenced. If the electrode pad102aand the wiring102are formed by using copper (Cu) as a principal component, for example, a migration occurring due to a copper ion causes a problem.

For example, if the semiconductor package is continuously used for a long period of time in a high temperature and high humidity environment, an insulation deterioration occurs in the solder resist layer103between the electrode pads102aas shown inFIG. 16. With a further progress, a short circuit is caused by the migration in some cases. As shown inFIG. 17, moreover, a foreign substance sticks to the buildup resin layer101so that a conductive passage is formed, and the copper ion is moved due to the migration between the wirings102because of presence of an electric field, resulting in a deposition or corrosion of a metal in some cases.

In the semiconductor package, furthermore, an adhesion (an adhesiveness) between layers, for example, between the buildup resin layer101and the electrode pad102aor between the electrode pad102aand the electrode bump104causes a problem so that the reliability of the semiconductor package is influenced. For example, in some cases in which the semiconductor package is continuously used for a long period of time in a high temperature and high humidity environment, peeling is caused between the layers so that water enters a portion between the layers.

SUMMARY

Exemplary embodiments of the present invention provide a technique capable of enhancing a reliability of a semiconductor package.

A method of manufacturing a semiconductor package, according to an exemplary embodiment of the invention comprises steps of:

(a) preparing a board on which a wiring having an electrode pad is formed;

(b) forming a resist film on the board in order to cover the wiring and then leaving the resist film on the electrode pad through patterning;

(c) forming an inorganic insulating film on the board in order to cover the wiring and then removing the resist film, thereby removing the inorganic insulating film provided on the resist film to leave the inorganic insulating film between the wirings after the step (b); and

(d) forming a solder resist layer on the board in order to cover the wiring and then exposing the electrode pad after the step (c).

According to the exemplary embodiments of the present invention, a reliability of a semiconductor package can be enhanced.

Other features and advantages may be apparent from the following detailed description, the accompanying drawings and the claims.

DETAILED DESCRIPTION

Embodiments according to the invention will be described below in detail with reference to the drawings. In all of the drawings for explaining the embodiments, members having the same functions have the same reference numerals and repetitive description thereof will be omitted in some cases.

A method of manufacturing a semiconductor package according to the embodiment will be described with reference toFIGS. 1 to 6. As shown inFIG. 7, a semiconductor package20has, as a final configuration, a structure having a printed board (a board1S) serving as a core, buildup resin layers1formed on both surfaces of the board1S, and wirings2formed on the buildup resin layers1, for example.

First of all, as shown inFIG. 1, there is prepared the board1S on which the wiring2having an electrode pad2ais formed. InFIG. 1, the buildup resin layer1formed as a top surface layer of the board1S is indicated as the board1S. The electrode pad2ais formed integrally when a conductor film containing copper (Cu) as a principal component is subjected to patterning to form the wiring2, for example. Moreover, an epoxy resin or a prepreg can be used for the buildup resin layer1, for example, and the buildup resin layer1has an insulating property.

Next, the wiring2including the electrode pad2ais subjected to a roughening treatment. The roughening treatment for the wiring2is carried out to enhance an adhesion to an inorganic insulating film to be formed on the wiring2at a subsequent step, and a surface of the wiring2is set to be a roughened surface having a roughness of approximately 1 to 2 μm. As the roughening treatment for the wiring2containing Cu as a principal component, it is possible to apply a black oxidation treatment, a CZ treatment or a neobrown treatment.

In the black oxidation treatment, the board1S is immersed in a solution which mainly contains sodium hydroxide and sodium chlorite to oxidize a Cu surface, thereby forming a roughened surface. Consequently, a needle-like oxide film is provided on the Cu surface so that minute concavo-convex portions are formed. Thus, it is possible to enhance the adhesion of the inorganic insulating film to be formed on the surface by an anchor effect.

In the CZ treatment, a solution containing a formic acid as a principal component is sprayed onto the Cu surface to carry out etching over Cu, thereby forming a roughened surface. In the neobrown treatment, moreover, an immersing or spraying treatment is carried out by using a hydrogen peroxide based/hydrogen sulfate based solution. Thus, the Cu surface is subjected to etching so that the roughened surface is formed. Referring to the CZ treatment and the neobrown treatment, there is obtained an etching shape along a grain boundary of Cu. Consequently, it is possible to enhance the adhesion of the inorganic insulating film to be formed on the surface by the anchor effect.

Subsequently, a resist film4is formed on the board1S in order to cover the wiring2. As shown inFIG. 2, then, the resist film4is left on the electrode pad2athrough patterning. For the resist film4, a liquid photosensitive resist or a dry film resist (DFR) is used, for example. In the embodiment, the resist film4is left on a part of the electrode pad2a.

As shown inFIG. 3, thereafter, an inorganic insulating film5to be an insulating film having an excellent water resistance and adhesion is formed on the board1S in order to cover the wiring2including the electrode pad2a. In other words, the inorganic insulating film5is formed to cover surfaces of the board1S, the resist film4and the wiring2. The inorganic insulating film5is silicon oxide (such as SiO2) with which the whole surface of the board1S is coated by a plasma CVD (Chemical Vapor Deposition) method, for example. The inorganic insulating film5is set to have a thickness which is equal to or greater than a roughness of the roughened surface. In the case in which the roughened surface (surface) of the wiring2is set to have a roughness of Ra=approximately 1 to 2 μm, the thickness of the inorganic insulating film5is set to be approximately 1 to 2 μm. In the case in which the thickness is smaller than the roughness of the roughened surface, a defect is caused in the inorganic insulating film5so that an insulation cannot be obtained. On the other hand, in the case in which the thickness is excessively greater than the roughness of the roughened surface, it is impossible to cope with a reduction in a pitch.

The inorganic insulating film5can also be formed by a sputtering method. In contrast with the sputtering method, however, the plasma CVD method is effective for a formation of a film at a low temperature, an enhancement in an adhesion of the wiring2(for example, copper) and the inorganic insulating film5(for example, silicon oxide) and an improvement in a uniformity and a throwing power.

By using the plasma CVD method, for example, it is possible to form the inorganic insulating film5at a low temperature of approximately 100° C. Consequently, it is possible to form the inorganic insulating film5at a temperature which is equal to or lower than a heat-resistant temperature (for example, 180° C.) of the buildup resin layer1or the printed board to be used as the core of the board1S. By using TEOS (tetraethoxysilane) as a gas for CVD, moreover, it is also possible to form a silicon oxide film having an excellent adhesion on a side surface of the wiring2including the electrode pad2a, between the wirings2having a small interval or between the electrode pads2a. Furthermore, it is also possible to apply silicon nitride (for example, SiN) as the inorganic insulating film5. The silicon nitride film can enhance a humidity resistance more greatly than the silicon oxide film.

As shown inFIG. 4, subsequently, the left resist film4is removed, and furthermore, the inorganic insulating film5provided on the resist film4is removed to expose the electrode pad2aby a lift-off method. In other words, the resist film4is removed so that the inorganic insulating film5provided on the resist film4is removed. Thus, the inorganic insulating film5is left between the wirings2. As will be described below, it is possible to suppress an occurrence of a migration between the wirings2or between the electrode pads2aby the inorganic insulating film5provided between the wirings2.

At the step shown inFIG. 4, in the case in which the DFR is used as the resist film4, the resist film4is peeled by aqueous sodium hydroxide or an amine based peeling solution. In the case in which a liquid photosensitive resist is used for the resist film4, moreover, the resist film4is peeled by a solvent or O2ashing. In the embodiment, at the step shown inFIG. 2, the resist film4is left on a part of the electrode pad2aand the inorganic insulating film5is then formed. Therefore, the resist film4is removed so that an opening portion5afor exposing the electrode pad2ais formed on the inorganic insulating film5.

Subsequently, a solder resist layer6is formed on the board1S in order to cover the wiring2including the electrode pad2a. As shown inFIG. 5, then, the solder resist layer6is subjected to patterning in order to expose the electrode pad2a. The solder resist layer6subjected to the patterning is formed by screen printing, for example. In the embodiment, the electrode pad2ais exposed and an opening portion6ato be a smaller opening (opening diameter) than the opening portion5a(opening diameter) is thereafter formed on the solder resist layer6.

As the solder resist layer6, for example, it is possible to use a material obtained by containing silica or a photopolymerization initiator in an epoxy based resin, a modified epoxy resin or an acrylate based resin, and the solder resist layer6has an insulating property. The solder resist layer6to be a top surface layer in the semiconductor package20is resistant to a heat temperature (approximately 260° C.) of soldering and a performance for protecting a circuit from an environment such as a heat or a humidity is more excellent than that of the buildup resin layer1to be an inner layer.

As shown inFIG. 6, subsequently, there is formed an electrode bump7serving as an external electrode which is to be electrically connected to the electrode pad2a. More specifically, an UBM (Under Barrier Metal) film8is formed, by a plating method, on the electrode pad2aexposed from the opening portion6aof the solder resist layer6, and the electrode bump7constituted by a solder bump is then formed on the UBM film8through solder printing. The UBM film8is formed by sequentially providing an Ni (nickel) and Au (gold) or sequentially providing an Ni, Pd (palladium) and Au, on the electrode pad2aexposed from the opening portion6aof the solder resist layer6so that the Au film becomes an uppermost layer of the UBM film8. Moreover, the electrode bump7may be formed by mounting a solder ball on the UBM film8.

It is possible to form the semiconductor package20shown inFIG. 7through the steps. The semiconductor package20includes the board1S on which the wiring2having the electrode pad2ais formed, the inorganic insulating film5formed to cover the wiring2and having the opening portion5aon the electrode pad2a, the solder resist layer6formed to cover the wiring2and the inorganic insulating film5and having, on the electrode pad2a, the opening portion6ato be the smaller opening than the opening portion5a, and the electrode bump7(7a,7b) to be the external electrode which is provided in the opening portion6aand is electrically connected to the electrode pad2a.

In the semiconductor package20, it is possible to constitute a semiconductor device by flip-chip mounting a semiconductor chip30through the electrode bump7a. The semiconductor chip30is mounted on the semiconductor package20in a state in which an electrode bump31to be an external electrode thereof is electrically connected to the electrode bump7a. An underfill resin32is formed between the semiconductor chip30and the semiconductor package20. In the semiconductor package20, moreover, an electrode pin22connected electrically to the electrode bump7bis formed on the electrode pad2aat a back face which is opposite to a mounting surface of the semiconductor chip30.

In the board1S, furthermore, a printed board is used as a core board, and the buildup resin layer (insulating layer)1and the wiring2are formed on both surfaces thereof and the wirings2on the both surface sides are electrically connected to each other via a through hole21. Accordingly, the electrode pin22to be the external electrode of the semiconductor device is electrically connected to the semiconductor chip30. It is possible to mount the semiconductor device on a mother board through the electrode pin22, for example. In addition, the inorganic insulating film5is provided on the both surfaces of the semiconductor package20. Therefore, it is possible to prevent water from entering an inner part of the package more suitably. Consequently, it is possible to enhance a reliability of the semiconductor package and the semiconductor device.

Although the electrode bump7band the electrode pin22are bonded to form an external connecting terminal in the semiconductor package20shown inFIG. 7, it is also possible to use the electrode bump7bitself as the external connecting terminal without providing the electrode pin22. Moreover, it is also possible to use the electrode pad2aitself as the external connecting terminal without providing the electrode pin22and the electrode bump7b.

In the embodiment, furthermore, the description has been given to the case in which the printed board is used as the core board. For the semiconductor package, however, the invention can also be applied to a coreless package in which only the buildup resin layer (the insulating layer) and the wiring are provided and the core board is not provided.

As described with reference toFIGS. 16 and 17, in the structure in which the electrode pad102aand the wiring102are directly covered with the solder resist layer103, the reliability of the semiconductor package (the semiconductor device) is influenced when a migration occurs between the electrode pads102aor between the wirings102.

In the embodiment, therefore, there is employed the structure in which the wiring2having the electrode pad2ais protected (coated) with the inorganic insulating film5and the solder resist layer6is formed thereon as shown inFIG. 6. By the structure, water entering from a surface of the solder resist layer6is blocked by the inorganic insulating film5so that the water can be prevented from reaching the wiring2having the electrode pad2a(which contains copper as a principal component, for example). Moreover, the inorganic insulating film5is provided between the wirings2and between the electrode pads2a. Therefore, it is possible to suppress the occurrence of the migration. As the material to be provided therebetween, moreover, the inorganic insulating film5(for example, silicon oxide or silicon nitride) is used. Consequently, it is possible to enhance the adhesion of the wiring2and the electrode pad2a. According to the embodiment, thus, it is possible to provide the semiconductor package20having the reliability enhanced.

For the structure in which the wiring2having the electrode pad2ais coated with the inorganic insulating film5and the solder resist layer6is formed thereon, moreover, it is also possible to propose structures shown inFIGS. 8 and 9.FIG. 8shows the structure in which the opening portion5a(the opening diameter) of the inorganic insulating film5is smaller than the opening portion6a(the opening diameter) of the solder resist layer6.FIG. 9shows the structure in which the opening portion5a(the opening diameter) of the inorganic insulating film5and the opening portion6a(the opening diameter) of the solder resist layer6are formed as the openings having an equal size to the electrode pad2a.

By regulating the sizes, it is possible to form the opening portion5aof the inorganic insulating film5and the opening portion6aof the solder resist layer6in the structures shown inFIGS. 8 and 9at the steps described with reference toFIGS. 4 and 5, respectively. For example, with the structure illustrated inFIG. 8, it is preferable to expose the electrode pad2a, thereby forming, on the solder resist layer6, the opening portion6awhich is larger than the opening portion5aof the inorganic insulating film5at the step shown inFIG. 5. With the structure illustrated inFIG. 9, moreover, the resist film4is formed on the whole surface of the electrode pad2aat the step shown inFIG. 2and the opening portion5aof the inorganic insulating film5which exposes the whole surface of the electrode pad2ais formed at the step shown inFIG. 4. Then, it is preferable to expose the electrode pad2aand to form, on the solder resist layer6, the opening portion6ahaving an equal size to the opening portion5aof the inorganic insulating film5at the step shown inFIG. 5.

With the structure shown inFIG. 8, the electrode pad2ais coated with the inorganic insulating film5in non-contact with the solder resist layer6. Therefore, it can be supposed that the suppression of the migration is more effective. With the structure shown inFIG. 9, moreover, the electrode pad2ais not provided in contact with the solder resist layer6and the electrode bump7is formed through the UBM film8from the opening portions5aand6ahaving the equal size to the electrode pad2a. Therefore, it can be supposed that the suppression of the migration is more effective, and furthermore, an adhesion area of the electrode pad2aand the electrode bump7is the largest and a bonding strength is high.

In contrast with the structures, in the structure shown inFIG. 6, the opening portion5aof the inorganic insulating film5is formed to be larger than the opening portion6aof the solder resist layer6. With the structure shown inFIG. 6, even if it is hard to align the opening portion5aof the inorganic insulating film5with the opening portion6aof the solder resist layer6as shown inFIG. 9, it is possible to form them including a dimension error. Therefore, it is possible to enhance a manufacturing yield of the semiconductor package. With the structure shown inFIG. 6, moreover, the inorganic insulating film5is not provided between the electrode pad2aand the electrode bump7as shown inFIG. 8. Consequently, the adhesion of the electrode bump7and the electrode pad2acan be prevented from being reduced so that the reliability of the semiconductor package20can be enhanced.

A method of manufacturing a semiconductor package according to the embodiment will be described with reference toFIGS. 10 to 12. Overlapping description with the first embodiment will be omitted in some cases.

In the same manner as the step described with reference toFIG. 1, first of all, there is prepared a board1S on which a wiring2having an electrode pad2ais formed, and the wiring2including the electrode pad2ais then subjected to a roughening treatment through a black oxidation treatment, a spraying treatment or a neobrown treatment, for example.

As shown inFIG. 10, subsequently, an inorganic insulating film5is formed on the board1S in order to cover the wiring2. The inorganic insulating film5is silicon oxide (for example, SiO2) with which a whole surface of the board1S is coated by a plasma CVD method, for example.

Then, a solder resist layer6is formed on the board1S in order to cover the inorganic insulating film5. As shown inFIG. 11, thereafter, the solder resist layer6provided on the electrode pad2ais removed (patterned). Consequently, an opening portion6afor exposing the inorganic insulating film5provided on the electrode pad2ais formed on the solder resist layer6.

As shown inFIG. 12, next, the inorganic insulating film5provided on the electrode pad2ais removed through plasma etching by using the left solder resist layer6as a mask, for example, and the electrode pad2ais thus exposed. Consequently, an opening portion5afor exposing the electrode pad2ais formed on the inorganic insulating film5. The etching is carried out based on the opening portion6aof the solder resist layer6. Therefore, the opening portion5aof the inorganic insulating film5and the opening portion6ahave an equal size.

In the same manner as the step described with reference toFIG. 9, subsequently, there is formed an electrode bump7to be an external electrode which is electrically connected to the electrode pad2a. More specifically, an Ni/Au or Ni/Pd/Au UBM film8is formed, by a plating method, on the electrode pad2aexposed from the opening portion6aof the solder resist layer6, and the electrode bump7constituted by a solder bump is then formed on the UBM film8through solder printing.

Also in the embodiment, as shown inFIG. 9, there is employed the structure in which the wiring2having the electrode pad2ais protected (coated) by the inorganic insulating film5, and the solder resist layer6is formed thereon. By the structure, it is possible to enhance a water resistance and to suppress an occurrence of a migration. As a material to be provided, moreover, the inorganic insulating film5is used. Therefore, it is possible to enhance an adhesion. According to the embodiment, thus, it is possible to improve a reliability of the semiconductor package.

Although the lift-off method has been used in the first embodiment, moreover, the opening portion5afor exposing the electrode pad2acan be formed on the inorganic insulating film5with high precision by the plasma etching (dry etching) using the solder resist layer6as a mask in the embodiment. Although a step of forming and removing a resist film4is required for the lift-off method, furthermore, the step is not necessary in the embodiment. Therefore, it is possible to reduce a manufacturing cost of the semiconductor package.

A method of manufacturing a semiconductor package according to the embodiment will be described with reference toFIGS. 13 to 15. Overlapping description with the first and second embodiments will be omitted in some cases.

In the same manner as the step described with reference toFIG. 1, first of all, there is prepared a board1S on which a wiring2having an electrode pad2ais formed, and the wiring2including the electrode pad2ais then subjected to a roughening treatment through a black oxidation treatment, a spraying treatment or a neobrown treatment, for example.

In the same manner as the step described with reference toFIG. 10, subsequently, an inorganic insulating film5is formed on the board1S in order to cover the wiring2. The inorganic insulating film5is silicon oxide (for example, SiO2) with which a whole surface of the board1S is coated by a plasma CVD method, for example.

Then, a resist film9is formed on the board1S in order to cover the inorganic insulating film5. As shown inFIG. 13, thereafter, the resist film9provided on the electrode pad2ais removed (patterned). Consequently, an opening portion9afor exposing the inorganic insulating film5provided on the electrode pad2ais formed on the resist film9. As the resist film9, for example, a liquid photosensitive resist or a dry film resist (DFR) is used.

As shown inFIG. 14, next, the inorganic insulating film5provided on the electrode pad2ais removed through plasma etching by using the left resist film9as a mask, for example, and the electrode pad2ais thus exposed. Consequently, an opening portion5afor exposing the electrode pad2ais formed on the inorganic insulating film5. The etching is carried out based on the opening portion9aof the resist film9. Therefore, the opening portion5aof the inorganic insulating film5and the opening portion9ahave an equal size.

As shown inFIG. 15, then, the left resist film9is removed. In the case in which the DFR is used as the resist film9, the resist film9is peeled by aqueous sodium hydroxide or an amine based peeling solution. In the case in which a liquid photosensitive resist is used for the resist film9, moreover, the resist film9is peeled by a solvent or O2ashing. Next, a solder resist layer6is formed on the board1S in order to cover the wiring2and the electrode pad2ais thereafter exposed. Consequently, a structure shown inFIG. 12is obtained.

In the same manner as the step described with reference toFIG. 9, subsequently, there is formed an electrode bump7serving as an external electrode which is to be electrically connected to the electrode pad2a. More specifically, an Ni/Au or Ni/Pd/Au UBM film8is formed, by a plating method, on the electrode pad2aexposed from an opening portion6aof the solder resist layer6, and the electrode bump7constituted by a solder bump is then formed on the UBM film8through solder printing.

Also in the embodiment, as shown inFIG. 9, there is employed the structure in which the wiring2having the electrode pad2ais protected (coated) by the inorganic insulating film5, and the solder resist layer6is formed thereon. By the structure, it is possible to enhance a water resistance and to suppress an occurrence of a migration. As a material to be provided, moreover, the inorganic insulating film5is used. Therefore, it is possible to enhance an adhesion. According to the embodiment, thus, it is possible to improve a reliability of the semiconductor package.

As described with reference toFIG. 12in the second embodiment, moreover, the opening portion5aof the inorganic insulating film5is formed through the plasma etching by using the solder resist layer6as a mask. For this reason, the solder resist layer6is damaged. In the embodiment, however, the opening portion5aof the inorganic insulating film5is formed and the solder resist layer6is then formed without the damage. Therefore, it is possible to enhance a reliability of the semiconductor package.

Furthermore, in the second embodiment, the opening portion5aof the inorganic insulating film5is formed by using the solder resist layer6as a mask. For this reason, the opening portion5aof the inorganic insulating film5has the equal size to the opening portion6aof the solder resist layer6. In the embodiment, the solder resist layer6is formed after the opening portion5aof the inorganic insulating film5is formed. Therefore, it is possible to regulate the size of the opening portion6a.

The invention is widely utilized in the manufacturing industry for a semiconductor package, particularly, a semiconductor package having an electrode pad with a small pitch which is formed on a printed board.