Method and system for reducing deadlock in fibre channel fabrics using virtual lanes

A method and system for processing fibre channel frames is provided. The method includes, assigning a virtual lane for a frame based on a hop count for the frame; determining if the assigned virtual lane has available credit; and transmitting the frame if credit is available. The system includes, a fibre channel fabric switch element including a receive port for receiving fibre channel frames, which includes a look up table to assign a virtual lane based on a hop count of the frame; and a transmit port that receives a primitive with the assigned virtual lane by the receive port and the transmit port includes a credit control module that determines if an assigned virtual lane can transmit a frame based on available credit.

BACKGROUND

1. Field of the Invention

The present invention relates to Fibre Channel systems, and more particularly, to reducing deadlock problems in Fibre Channel Fabrics.

2. Background of the Invention

Fibre channel is a set of American National Standard Institute (ANSI) standards, which provide a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others. Fibre channel provides an input/output interface to meet the requirements of both channel and network users.

Fibre channel supports three different topologies: point-to-point, arbitrated loop and fibre channel fabric. The point-to-point topology attaches two devices directly. The arbitrated loop topology attaches devices in a loop. The fibre channel fabric topology attaches host systems directly to a fabric, which are then connected to multiple devices. The fibre channel fabric topology allows several media types to be interconnected.

Fibre channel is a closed system that relies on multiple ports to exchange information on attributes and characteristics to determine if the ports can operate together. If the ports can work together, they define the criteria under which they communicate.

In fibre channel, a path is established between two nodes where the path's primary task is to transport data from one point to another at high speed with low latency, performing only simple error detection in hardware.

Fibre channel fabric devices include a node port or “N_Port” that manages fabric connections. The N_port establishes a connection to a fabric element (e.g., a switch) having a fabric port or F_port. Fabric elements include the intelligence to handle routing, error detection, recovery, and similar management functions.

A fibre channel switch is a multi-port device where each port manages a simple point-to-point connection between itself and its attached system. Each port can be attached to a server, peripheral, I/O subsystem, bridge, hub, router, or even another switch. A switch receives messages from one port and automatically routes it to another port. Multiple calls or data transfers happen concurrently through the multi-port fibre channel switch.

Fibre channel switches use memory buffers to hold frames received and sent across a network. Associated with these buffers are credits, which are the number of frames that a buffer can hold per fabric port.

The following Fibre Channel standards are used for Fibre Channel systems and Fibre Channel Fabrics, and are incorporated herein by reference in their entirety:

ANSI INCITS xxx-200x Fibre Channel Framing and Signaling Interface (FC-FS)—T11/Project 1331D; and ANSI INCITS xxx-200x Fibre Channel Switch Fabric-3(FC-SW-3), T11/Project 1508D

As discussed above, a Fibre Channel Fabric can consist of multiple switches connected in an arbitrary topology. The links between the switches use a buffer-to-buffer credit scheme for flow control so that all frames transmitted have a receive buffer. Fabric deadlock may occur if a switch cannot forward frames because the recipient switch buffers (receive buffers) are full.

The following example, described with respect toFIG. 6, shows how a deadlock situation can occur.FIG. 6shows five switches (“SW”)1,2,3,4, and5that are linked together by ISLs (Inter Switch Links) in a ring topology. Host11and target21are linked to switch1, host12and target22are linked to switch2, and so forth.

In this example, hosts11-15can send data as fast as they can to a target that is two (2) hops away, for example:Host11can send data to target23;Host12can send data to target24;Host13can send data to target25;Host14can send data to target21; andHost15can send data to target22

For illustration purposes only, all traffic goes in the clockwise direction inFIG. 6.

The receive buffers available for each ISL in the direction of traffic may get filled with frames addressed to the next switch.

For example:For the ISL between switch1and switch2, the receive buffers on switch2get filled with frames for switch3;For the ISL between switch2and switch3, the receive buffers on switch3get filled with frames for switch4;For the ISL between switch3and switch4, the receive buffers on switch4get filled with frames for switch5;For the ISL between switch4and5, the receive buffers on5get filled with frames for switch1; andFor the ISL between switch5and switch1, the receive buffers on switch1get filled with frames for switch2.

The transmit side of a switch waits for R_RDYs before it can transmit any frames. If frames cannot be transmitted from one ISL, then the receive buffers for the other ISL cannot be emptied. If the receive buffers cannot be emptied, no R_RDY flow control signals can be transmitted, which deadlocks the Fabric.

Many large Fabrics have paths that form rings within them, especially if they are designed to avoid single points of failure by using redundant switches. Such network traffic patterns may result in a deadlock situation disrupting networks using fibre channel switches and components.

Therefore, there is need for a system and method for minimizing deadlock problems in fibre channel switches.

SUMMARY OF THE PRESENT INVENTION

In one aspect of the present invention, a method for processing fibre channel frames is provided. The method includes, assigning a virtual lane for a frame based on a hop count for the frame; determining if the assigned virtual lane has available credit; and transmitting the frame if credit is available.

The method also includes, incrementing a counter value for counting available credit for the assigned virtual lane, if the frame is sent using the assigned virtual lane. If all credit for the assigned virtual lane has been used, then a next virtual lane is selected with non-zero credit.

In yet another aspect of the present invention, a method for processing fibre channel frames using a fabric switch element having a receive port and a transmit port is provided. The method includes assigning a virtual lane in the receive port based on a hop count for the frame; and sending a primitive to a transmit port with the assigned virtual lane.

The method further includes, assigning a virtual lane on the transmit port based on the hop count of the frame; and determining if credit is available for the assigned virtual lane to send the frame. A credit count for the assigned virtual lane is maintained by a counter and the assigned virtual lane has a maximum credit count.

In another aspect of the present invention, a system for processing fibre channel frames is provided. The system includes, a fibre channel fabric switch element including a receive port for receiving fibre channel frames, which includes a look up table to assign a virtual lane based on a hop count of the frame; and a transmit port that receives a primitive with the assigned virtual lane by the receive port and the transmit port includes a credit control module that determines if an assigned virtual lane can transmit a frame based on available credit.

The credit control module increments a credit count for an assigned virtual lane if a frame has been transmitted from the assigned virtual lane. The credit control module also decrements a credit count for an assigned virtual lane if a VC_RDY is received. The credit control module also maintains a maximum count for every virtual lane used for transmitting frames. An increment selector is used to increment credit count and a decrement selector is used to decrease the credit count. The credit control module also uses compare logic to compare available credit for an assigned virtual lane at any given time with a programmed maximum credit value for the assigned virtual lane.

In yet another aspect of the present invention, a system for processing fibre channel frames is provided. The system includes, the means for assigning dedicated virtual lanes for transmitting frames, where the virtual lanes are assigned based on a hop count of a frame; means for maintaining a credit count for each virtual lane used for transmitting frames; and means for determining if credit is available for a particular virtual lane that is assigned based on the hop count.

The system also includes the means for maintaining a maximum credit count for each virtual lane; and means for comparing the maximum credit count with the credit available for a virtual lane at any given time.

In yet another aspect of the present invention, a fibre channel fabric switch element for processing fibre channel frames, is provided. The switch element includes, means for assigning dedicated virtual lanes for transmitting frames, where the virtual lanes are assigned based on a hop count of a frame; means for maintaining a credit count for each virtual lane used for transmitting frames; and means for determining if credit is available for a particular virtual lane that is assigned based on the hop count.

The switch element also includes, means for maintaining a maximum credit count for each virtual lane; and means for comparing the maximum credit count with the credit available for a virtual lane at any given time.

In yet another aspect, the present invention reduces/prevents the deadlock by separating frames queued for transmission into virtual lanes, each with its own transmit queue and flow control. Flow control uses the Fibre Channel VC_RDY primitive signal to give separate flow control signals to each virtual lane. Also, no frames are discarded to reduce/avoid deadlock.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following definitions are provided as they are typically (but not exclusively) used in the fibre channel environment, implementing the various adaptive aspects of the present invention.

“D_ID”: 24-bit fibre channel header field that contains destination address.

“EOF”: End of Frame

“E-Port”: A fabric expansion port that attaches to another Interconnect port to create an Inter-Switch Link.

“F-Port”: A port to which non-loop N_Ports are attached to a fabric and does not include FL_ports.

“Fibre channel ANSI Standard”: The standard (incorporated herein by reference in its entirety) describes the physical interface, transmission and signaling protocol of a high performance serial link for support of other high level protocols associated with IPI, SCSI, IP, ATM and others.

“FC-1”: Fibre channel transmission protocol, which includes serial encoding, decoding and error control.

“FC-2”: Fibre channel signaling protocol that includes frame structure and byte sequences.

“FC-3”: Defines a set of fibre channel services that are common across plural ports of a node.

“FC-4”: Provides mapping between lower levels of fibre channel, IPI and SCSI command sets, HIPPI data framing, IP and other upper level protocols.

“Fabric”: The structure or organization of a group of switches, target and host devices (NL_Port, N_ports etc.).

“Fabric Topology”: A topology where a device is directly attached to a fibre channel fabric that uses destination identifiers embedded in frame headers to route frames through a fibre channel fabric to a desired destination.

“FL_Port”: A L_Port that is able to perform the function of a F_Port, attached via a link to one or more NL_Ports in an Arbitrated Loop topology.

“Inter-Switch Link” (“ISL”): A Link directly connecting the E_port of one switch to the E_port of another switch.

Port: A general reference to N.Sub._-- Port or F.Sub._--Port.

“L_Port”: A port that contains Arbitrated Loop functions associated with the Arbitrated Loop topology.

“N-Port”: A direct fabric attached port.

“NL_Port”: A L_Port that can perform the function of a N_Port.

“S_ID”: 24 bit fibre channel header field that contains the source address of a frame.

“SOF”: Start of Frame

“Switch”: A fabric element conforming to the Fibre Channel Switch standards.

“VL” (Virtual Lane): A virtual portion of the data path between a source and destination port each having independent buffer to buffer flow control.

To facilitate an understanding of the preferred embodiment, the general architecture and operation of a fibre channel system will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture of the fibre channel system.

FIG. 1Ais a block diagram of a fibre channel system100implementing the methods and systems in accordance with the adaptive aspects of the present invention. System100includes plural devices that are interconnected. Each device includes one or more ports, classified as node ports (N_Ports), fabric ports (F_Ports), and expansion ports (E_Ports). Node ports may be located in a node device, e.g. server103, disk array105and storage device104. Fabric ports are located in fabric devices such as switch101and102. Arbitrated loop106may be operationally coupled to switch101using arbitrated loop ports (FL_Ports).

The devices ofFIG. 1Aare operationally coupled via “links” or “paths”. A path may be established between two N_ports, e.g. between server103and storage104. A packet-switched path may be established using multiple links, e.g. an N-Port in server103may establish a path with disk array105through switch102.

FIG. 1Bis a block diagram of a 20-port ASIC fabric element according to one aspect of the present invention.FIG. 1Bprovides the general architecture of a 20-channel switch chassis using the 20-port fabric element. Fabric element includes ASIC20with non-blocking fibre channel class 2 (connectionless, acknowledged) and class 3 (connectionless, unacknowledged) service between any ports. It is noteworthy that ASIC20may also be designed for other fibre channel classes of service, within the scope and operation of the present invention as described herein.

The fabric element of the present invention is presently implemented as a single CMOS ASIC, and for this reason the term “fabric element” and ASIC are used interchangeably to refer to the preferred embodiments in this specification. AlthoughFIG. 1Bshows 20 ports, the present invention is not limited to any particular number of ports.

ASIC20has 20 ports numbered inFIG. 1Bas GL0through GL19. These ports are generic to common Fibre Channel port types, for example, F_Port, FL_Port and E-Port. In other words, depending upon what it is attached to, each GL_Port can function as any type of port. Also, the GL_Port may function as a special port useful in fabric element linking, as described below.

For illustration purposes only, all GL_Ports are drawn on the same side of ASIC20inFIG. 1B. However, the ports may be located on both sides of ASIC20as shown in other figures. This does not imply any difference in port or ASIC design. Actual physical layout of the ports will depend on the physical layout of the ASIC.

Each port GL0-GL19has transmit and receive connections to switch crossbar50. One connection is through receive buffer52, which functions to receive and temporarily hold a frame during a routing operation. The other connection is through a transmit buffer54.

Switch crossbar50includes a number of switch crossbars for handling specific types of data and data flow control information. For illustration purposes only, switch crossbar50is shown as a single crossbar. Switch crossbar50is a connectionless crossbar (packet switch) of known conventional design, sized to connect 21×21 paths. This is to accommodate 20 GL_Ports plus a port for connection to a fabric controller, which may be external or internal to ASIC20.

In the preferred embodiments of switch chasis described herein, the fabric controller is a firmware-programmed microprocessor, also referred to as the input/out processor (“IOP”). IOP66is shown inFIG. 1Cas a part of a switch chassis utilizing one or more of ASIC20. As seen inFIG. 1B, bi-directional connection to IOP66is routed through path67, which connects internally to a control bus60. Transmit buffer56, receive buffer58, control register62and Status register64connect to bus60. Transmit buffer56and receive buffer58connect the internal connectionless switch crossbar50to IOP66so that it can source or sink frames.

Control register62receives and holds control information from IOP66, so that IOP66can change characteristics or operating configuration of ASIC20by placing certain control words in register62. IOP66can read status of ASIC20by monitoring various codes that are placed in status register64by monitoring circuits (not shown).

FIG. 1Cshows a 20-channel switch chassis S2using ASIC20and IOP66. S2will also include other elements, for example, a power supply (not shown). The 20 GL_Ports correspond to channel C0-C19. Each GL_Port has a serial/deserializer (SERDES) designated as S0-S19. Ideally, the SERDES functions are implemented on ASIC20for efficiency, but may alternatively be external to each GL_Port.

Each GL_Port may have an optical-electric converter, designated as OE0-OE19connected with its SERDES through serial lines, for providing fibre optic input/output connections, as is well known in the high performance switch design. The converters connect to switch channels C0-C19. It is noteworthy that the ports can connect through copper paths or other means instead of optical-electric converters.

FIG. 1Dshows a block diagram of ASIC20with sixteen GL_Ports designated as GL0-GL15and four 10G port control modules designated as XG0-XG3. ASIC20include a control port62A that is coupled to IOP66through a PCI connection66A.

IOP66is also shown inFIG. 2as a part of a switch chasis201, containing switch ports204,207,210and215. Each port as described above has a transmit port (segment), for example,205,208,211and213, and receive port (segment), for example,206,209,212and214.

Transmit ports and receive ports are connected by switch crossbar50so that they can transfer frames. IOP66controls and configures the switch ports.

In one aspect of the present invention, dividing frame traffic on ISLs into virtual lanes by assigning virtual lanes based on the number of hops to a destination switch, as described below reduces deadlock. Each virtual lane has its own buffer-to-buffer credit scheme. The term hop count means the number of ISLs a frame has to traverse before it reaches a destination switch.

To reduce and/or avoid deadlock in fibre channel switches, the following port requirements are used:

A receive port has receive buffers at least equal to the largest number of hops to a destination as seen by the transmit port of the switch that receives a frame. A receive buffer is also reserved for each hop count.

The hop count for frames can be derived from the data exchanged by switches using the standard FSPF protocol to set up routing within the Fabric, as described in the fibre channel standard, FC-SW-3, incorporated herein by reference in its entirety.

The transmit and receive ports assign a virtual lane to each hop count.

Each virtual lane is assigned some buffer-to-buffer credit. The total credit for all the virtual lanes is less than or equal to the total number of receive buffers available at a receive port.

Frames queued for transmissions are assigned a virtual lane and each hop count has a virtual lane.

Frames are transmitted if credit is available for its virtual lane.

Receive ports assign a virtual lane for the received frames. In one example, virtual lanes are assigned based on the hop count to a destination switch. If the destination is within the switch that received the frame, then the hop count is 0.

When a receive port empties a receive buffer, making it available for another frame, it sends a VC_RDY (n) primitive to the other end of the link. The VC_RDY contains the number of the virtual lane of the frame just processed. The fibre channel standard, FC-FS (incorporated herein by reference in its entirety) describes the VC_RDY primitive signal.

Using virtual lanes as discussed above, keeps the receive buffers of an ISL from filling up with frames for the same destination and provides receive buffers space for frames to other destination.

The following sequence shows how frames are delivered, using one aspect of the present invention:

Frames arriving on an ISL addressed to a particular switch can empty its receive buffers for virtual lane0and return VC_RDY (0) to the sender.

A switch that is 1 hop away from a destination switch (for example, switch2if the destination switch is switch3for a frame sent from switch1) gets VC_RDY (0). In this example, this will allow switch2to empty the receive buffer for frames received from other switches.

During the exchange of ELP messages (fibre channel standard log-in messages) to log in the ISL ports (per FC-SW-3 standard, incorporated herein by reference in its entirety) virtual lanes and hop counts in the ELP messages can be used for flow control. If both ends of the ISL agree, the virtual lane flow control option is used. Since the virtual lane assignment is derived from the hop count, there is no need to negotiate virtual lane assignments.

If the receive port on an ISL receives a frame that it cannot route, it returns a VC_RDY (255) to the sender after the receive buffer is emptied. If a VC_RDY (255) is received, the credit is allocated to the lowest numbered virtual lane that does not have maximum transmit credit available. If any VC_RDY(n) is received where virtual lane n does not exist or is already at maximum transmit credit, the credit is allocated the same way.

FIG. 3shows how received frames are processed using Virtual Lanes, according to one aspect of the present invention. The Fibre Channel header D_ID field301A and a look-up table in logic302is used to look up the hop count for a frame based on the destination. The hop count number is used to assign a Virtual Lane (302A). The look-up table in logic302is loaded with data derived from the standard “FSPF” routing algorithm to determine the hop count. The frame and the assigned Virtual Lane302A are stored in receive buffers301.

When a frame (301A) is moved out of a receive buffer to a transmit port, receive buffer301sends a signal303to the transmit port. If the port is an ISL using the deadlock prevention process of the present invention, the flow control signal303is a VC_RDY primitive containing the assigned virtual lane (302A) when the frame was received.

FIG. 4shows a block diagram of logic400used in flow control for a transmit port using virtual Lanes (in this example, 4 virtual lanes) for reducing and/or avoiding deadlocks, according to one aspect of the present invention. Logic400can be used for ISLs (E-ports) that connect switches. Frames are queued in queue401and are assigned a Virtual Lane (401A).

In one aspect of the present invention, the assigned Virtual Lane401A is one less than the Virtual Lane assigned by the receive port (303,FIG. 3). The assigned Virtual Lane401A is used by multiplexer403to determine which credit control output from credit control module402is used to determine if a frame has available credit for transmission. Transmit control module404determines if a frame is available for transmission and credit is available. If a frame and credit is available, then frame405is transmitted to its destination.

FIG. 5shows a block diagram of credit control module402, according to one aspect of the present invention. Credit control module402has an increment selector501and decrement selector502for increasing and decreasing counters503. Counter503maintains count for each virtual lane, for example, VL0, VL1, VL2and VL3. Selector501increments a virtual lane credit count based on501B, i.e., the VL of a frame that is transmitted. Selector501also receives input501A from transmit control module404which indicates when a frame has been sent.

If a VC_RDY502A is received from a receive buffer, then selector502decrements the value of the appropriate counter503. Selector502also receives the Virtual Lane associated with the VC_RDY (502) from the receive buffer (similar to303,FIG. 3).

Counter(s)503maintain(s) count for the virtual lanes VL0, VL1, VL2and VL3. In one aspect of the present invention, each virtual lane may have a pre-programmed maximum count value that is stored in counters504.

Logic (also referred to as “compare module”)505compares the maximum count value for virtual lane0to determine if credit is available on virtual lane0. Logic506-508performs the same function for virtual lanes1,2and3, respectively. Compare modules505-508generate signals505A-505D indicating if credit is available for a particular Virtual Lane to transmit a frame.

To illustrate the adaptive aspects of the present invention separate counters have been shown, however, the present invention is not limited to any particular number of counters. For example, logic with a single counter may be used to compare the maximum count (504) and the count (503) for each lane.

In another aspect of this invention, other queuing methods could be used instead of the one described for this embodiment. For instance, a transmit port may have a transmit queue for each Virtual Lane, and/or for each receive port.

FIG. 7shows a process flow diagram, according to one aspect of the present invention using virtual lanes for frame transmission.

In step S700, the process selects a particular virtual lane, for example, virtual lane0. In step S701, the process determines if the credit used for a particular virtual lane (for example, virtual lane0) is less than a maximum programmed amount or a particular value (FIG. 5,504). This is performed by logic505-508, depending upon which lane is selected. In the foregoing example, for VL0, it is logic505. If virtual lane credit exceeds the maximum count, then in step S705, the process selects the next available virtual lane (for example, virtual lane1). In step S706, the process determines if the selected virtual lane has used it's maximum credit. If yes, the process reverts back to step S700, otherwise the process moves to step S701.

In step S702, the process determines if a frame is available for the selected virtual lane (i.e. the lane that is selected in step S701or S706). If a frame is not available, the process moves to step S705.

If a frame is available in step S702, the frame is sent in step S703(for example,505A), and then in step S704, the credit counter for the virtual lane is incremented by selector501using one of the counters503.

FIG. 8provides a flow diagram for selecting a virtual lane, according to one aspect of the present invention. In step S800, the process determines the hop count for a frame's D_ID. In step S801, the process sets the virtual lane of a frame (401A). In one example, the virtual lane is one less than the hop count.

FIG. 9shows a flow diagram for processing VC_RDY primitives, according to one aspect of the present invention. In step S900, the process uses a VC_RDY virtual lane number to index virtual lane credit that has been used for a particular frame. This information comes as502B to selector502from the receive port.

In step S901, the process determines if all the credit for a particular virtual lane has been used. If yes, then in step S903, the process finds the next virtual lane with non-zero credit.

If in step S901, virtual lane credit is not equal to zero, then in step S902, selector502decrements the virtual lane credit value that has been used.

FIG. 10shows a flow diagram for processing frame in the receive port of a switch, according to one aspect of the present invention. In step S1000, the process receives frame D-ID301A. In step S1001, the process determines the hop count for the frame. This can be obtained by using the standard FSPF algorithm.

In step S1002, the process assigns a virtual lane based on the hop count. If the frame is destined for the same switch, the virtual lane is zero.

In step S1003, the receive port sends the frame to the transmit segment and in step S1004, a VC_RDY primitive is sent to the transmit port with the VL assignment value (502B).

FIG. 11is an overall process flow diagram for sending frames from the transmit port of a switch. In step1100, the process assigns a virtual lane for a frame that is queued (401A).

In step S1101, the process determines if credit is available for a particular virtual lane. This is performed by credit control module402, as described above.

In step S1102, a frame is sent if credit is available.

In one aspect, the present invention reduces/prevents the deadlock by separating frames queued for transmission into virtual lanes, each with its own transmit queue and flow control. Flow control uses the Fibre Channel VC_RDY primitive signal to give separate flow control signals to each virtual lane. Also, no frames are discarded to reduce/avoid deadlock.

Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.