A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.

FIELD OF THE INVENTION

The present invention relates generally to semiconductors, and more particularly, to a finFET integration method and structure.

BACKGROUND OF THE INVENTION

Transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), are the core building block of the vast majority of semiconductor devices. Some semiconductor devices, such as high performance processor devices, can include millions of transistors. For such devices, decreasing transistor size, and thus increasing transistor density, has traditionally been a high priority in the semiconductor manufacturing industry.

FinFET technology is becoming more prevalent as device size continues to shrink. It is therefore desirable to have improved fabrication methods and structures for utilization of FinFET structures.

SUMMARY OF THE INVENTION

In one embodiment, a method of fabricating a semiconductor structure is provided. The method comprises depositing a dielectric layer on an interior surface of a cavity in a silicon-on-insulator structure, forming a capacitor electrode in a lower portion of the cavity, forming a polysilicon plug on the capacitor electrode, forming an oxide region on the polysilicon plug, forming a finFET, said finFET comprising a plurality of fins and a gate, said gate disposed over a portion of the plurality of fins, wherein the gate is disposed over the oxide region in an upper portion of the cavity.

In another embodiment, a method of fabricating a semiconductor structure is provided. The method comprises depositing a dielectric layer on an interior surface of a cavity in a silicon-on-insulator structure, wherein the silicon-on-insulator structure comprises a first silicon layer, an insulator layer disposed on the first silicon layer; a second silicon layer disposed on the insulator layer, and a nitride layer disposed on the second silicon layer, forming a capacitor electrode in a lower portion of the cavity, forming a polysilicon plug on the capacitor electrode, forming a first oxide region on the polysilicon plug, planarizing the first oxide region to the nitride layer, removing the nitride layer, forming a second oxide region, wherein the second oxide region is disposed over the first oxide region and is disposed over the second silicon layer, and forming a finFET, said finFET comprising a plurality of fins and a gate electrode, said gate electrode disposed over a portion of the plurality of fins, wherein the gate electrode of the finFET is in direct physical contact with the first oxide region in an upper portion of the cavity.

In another embodiment, a semiconductor structure is provided. The structure comprises a finFET. The finFET comprises a plurality of fins and a gate, said gate disposed over a portion of the plurality of fins. The structure further comprises a trench capacitor, the trench capacitor comprising a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The structure further comprises a polysilicon plug disposed over the second electrode, and a trench top oxide disposed over the polysilicon plug. The gate of the finFET is disposed over the trench top oxide.

DETAILED DESCRIPTION

FIG. 1shows a semiconductor structure100at a starting point for methods in accordance with embodiments of the present invention. Semiconductor structure100comprises a silicon substrate102. Disposed on the silicon substrate is insulator layer104. Insulator layer104may be comprised of oxide, and may be referred to as a buried oxide (BOX) layer. Disposed on insulator layer104is a second silicon layer106. Second silicon layer106may be referred to as a silicon-on-insulator (SOI) layer, and hence, semiconductor structure100may be referred to as a silicon-on-insulator structure. Disposed on second silicon layer106is a pad nitride layer108. A cavity or trench111is formed in the semiconductor structure100. A trench dielectric layer110is disposed on the interior surface of the trench. In particular, the trench dielectric layer110is disposed on the bottom of the trench and the lower sidewalls of the trench111. A capacitor electrode112comprised of a conductive material is deposited in the lower portion of the trench. As a capacitor is a two-terminal device, capacitor electrode112serves as one of the two electrodes. The second electrode may be a so-called “buried plate” comprising a doped region117within silicon substrate102.

In some embodiments, the trench dielectric layer110may comprise silicon nitride, Al2O3, HfO2, Ta2O5, or ZrO2. Other materials are possible for dielectric layer110. In some embodiments, the capacitor electrode112may comprise polysilicon, titanium, tungsten, molybdenum, cobalt, titanium silicide, tungsten silicide, molybdenum silicide, or cobalt silicide. Other materials may be used for capacitor electrode112.

FIG. 2shows a semiconductor structure200after a subsequent step of pad nitride layer removal (compare with108ofFIG. 1). As stated previously, often, similar elements may be referred to by similar numbers in various figures (FIGs) of the drawing, in which case typically the last two significant digits may be the same, the most significant digit being the number of the drawing figure (FIG). For example, silicon substrate202ofFIG. 2is similar to silicon substrate102ofFIG. 1. In some embodiments, the pad nitride layer removal is performed via a selective wet etch process.

FIG. 3shows a semiconductor structure300after a subsequent step of oxide formation. Oxide layer316is formed such that it grows at a first rate R1over the second silicon layer306, which is a single crystal silicon layer, and it grows at a second rate R2over the polysilicon plug314. Embodiments of the present invention may utilize the different growth rates to form an oxide layer316that is planar at a depth (thickness) D1over the second silicon layer306and at a depth D2over the polysilicon plug314. The oxidation (growth) rate over the polysilicon plug314is faster than the oxidation rate over the second silicon layer316. In one embodiment, oxidation parameters may be selected such that the oxide layer306is planar when the oxide thickness reaches predetermined depth D1over the second silicon layer316. The following formulas may be used to compute a desired thickness and oxidation time.
D1=R1Tx
D32 2=R2Tx
D2=D1+d

Where: Tx is an oxidation process time; d is the offset distance between the top of the polysilicon plug314and top of the second silicon layer306; R1is the oxidation rate over the second silicon layer; R2is the oxidation rate over the polysilicon plug; and R2>R1.

In one embodiment, the oxidation process temperature is a parameter that is tuned (adjusted) to achieve the relationship between R2and R1such that the oxide layer is planar when it reaches a level of D1over the second silicon layer316. In one embodiment, the temperature is in the range of about 700 degrees Celsius to about 1000 degrees Celsius. The ratio R2/R1is a function of the oxidation process temperature. As the oxidation process temperature decreases, the ratio R2/R1increases. Hence, adjusting the temperature can tune the oxidation process so that it is planar at the desired thickness.

Given certain design parameters, the formulas can be solved to determine D1, D2, and Tx. Rates R1and R2may be non-linear functions of multiple parameters. An oxide growth calculation, such as the Grove Model, may be used to compute an oxidation rate during the oxidation process, such that appropriate oxidation parameters may be selected to achieve a planar oxide layer (such as316ofFIG. 3), thus avoiding the need for a planarization step, which saves cost and reduces fabrication time.

FIG. 4shows a semiconductor structure400of an alternative embodiment after a subsequent step of oxide formation. In this embodiment, if the oxide growth rates are not sufficiently tuned, there may be a non-planar region416R. In this case, a planarization process, such as a chemical mechanical polish (CMP) may be used to planarize the oxide such that it is similar to semiconductor structure300ofFIG. 3.

FIG. 5shows a semiconductor structure500after a subsequent step of planarization to form trench top oxide (TTO) region516.

FIG. 6shows a semiconductor structure600after a subsequent step of depositing a fin cap layer618. The fin cap layer618may be comprised of nitride, and is used to protect the second silicon layer606, which will constitute the fins of the finFET once fabrication is complete.

FIG. 7shows a perspective view of a trench top oxide716after deposition of a fin cap layer718. The trench top oxide (TTO)716is disposed on the capacitor node724(which may include a polysilicon or metal conductor and the polysilicon plug). The second silicon layer706is adjacent to the TTO716, and is disposed over the insulator layer (BOX)704and a portion of the capacitor node724. In one embodiment, the thickness W of the TTO716ranges from about 10 nanometers to about 30 nanometers.

FIG. 8shows a semiconductor structure800in accordance with an embodiment of the present invention showing a top-down view of a finFET821comprising a gate823. The gate823comprises a plurality of silicon fins825, which comprise a source/drain for finFET821. The fins825are adjacent to, and in contact with, trench capacitor819. Trench capacitor819has a trench top oxide (TTO)816covering its top. A passing gate831is disposed over the trench top oxide816. The drawing shows the passing gate831as transparent, so that the trench top oxide816is visible “behind” the passing gate831. In one embodiment, the passing gate831is part of a finFET transistor for a neighboring DRAM cell having fins837connected to adjacent cell(s). The passing gate831may be in direct physical contact with the trench top oxide region816. Alternatively, there may be a dielectric layer (not shown) disposed in between the gate831and the TTO816. In a DRAM circuit embodiment, the gate831may be electrically connected to a word line. The trench top oxide816may therefore provide improved isolation between the trench capacitor and a word line. Hence, semiconductor structure800integrates a trench capacitor819with a finFET by providing trench top oxide816to provide additional electrical isolation from the passing gate831, thus allowing the gate to “pass over” the trench capacitor819without interfering with its electrical operation.

FIG. 9shows a semiconductor structure900at an intermediate fabrication step of a first oxide formation in accordance with an alternative embodiment of the present invention. In this embodiment, a first oxide region916is formed that extends part way into pad nitride layer908.

FIG. 10shows a semiconductor structure1000at a subsequent processing step of pad nitride layer removal (compare with908ofFIG. 9). The pad nitride layer may be removed with a selective wet etch.

FIG. 11shows a semiconductor structure1100at an intermediate fabrication step of formation of a second oxide region1116. Optionally, a planarization process may follow formation of the second oxide region1116. The planarization process may include a chemical mechanical polish (CMP) process. From this point, the fabrication process proceeds similar to the embodiment described inFIGS. 5-8.

FIG. 12shows a semiconductor structure1200at an intermediate fabrication step of forming a first oxide region1216in accordance with another alternative embodiment of the present invention. In this embodiment, the first oxide region1216is grown above the level of pad nitride layer1208, and then planarized such that the first oxide region1216is level with the top of the pad nitride layer1208.

FIG. 13shows a semiconductor structure1300at a subsequent processing step of pad nitride layer removal (compare with1208ofFIG. 12). The pad nitride layer may be removed with a selective wet etch.

FIG. 14shows a semiconductor structure1400at an intermediate fabrication step of forming a second oxide region1416, and performing a subsequent planarization process. The planarization process may include a chemical mechanical polish (CMP) process. From this point, the fabrication process proceeds similar to the embodiment described inFIGS. 5-8.

Hence there are various embodiments of the present invention that provide varying degrees of oxide formation control along with various levels of process complexity. The embodiments that avoid the need for planarization have the lowest complexity, but also the least amount of control over the oxide growth. The embodiments that use multiple stages of oxide growth have more control, but also more complexity. The embodiments that use multiple stages of oxide growth along with one or more planarization steps have the most complexity, but also the most control over the oxide growth. Hence, a process engineer can select an embodiment that is most appropriate for a given process, taking into consideration such factors as node size, desired yield, and manufacturing throughput.

FIG. 15is a flowchart1500indicating process steps for a method in accordance with embodiments of the present invention. In process step1550a node dielectric layer is deposited (see110ofFIG. 1). In process step1552, a capacitor electrode is formed (see112ofFIG. 1). In process step1554, a polysilicon plug is formed (see114ofFIG. 1). In process step1556, a trench top oxide (TTO) is formed (see716ofFIG. 7 and 816ofFIG. 8). In process step1558, a finFET is formed, which comprises a gate electrode (see828ofFIG. 8) disposed on a gate dielectric (see826ofFIG. 8) which is disposed over the trench top oxide (see816ofFIG. 8).

Design flow1600may vary depending on the type of representation being designed. For example, a design flow1600for building an application specific IC (ASIC) may differ from a design flow1600for designing a standard component or from a design flow1600for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.

FIG. 16illustrates multiple such design structures including an input design structure1620that is preferably processed by a design process1610. Design structure1620may be a logical simulation design structure generated and processed by design process1610to produce a logically equivalent functional representation of a hardware device. Design structure1620may also or alternatively comprise data and/or program instructions that when processed by design process1610, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure1620may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure1620may be accessed and processed by one or more hardware and/or software modules within design process1610to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown inFIGS. 1-15. As such, design structure1620may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

Design process1610may include using a variety of inputs; for example, inputs from library elements1630which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications1640, characterization data1650, verification data1660, design rules1670, and test data files1685(which may include test patterns and other testing information). Design process1610may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process1610without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.

Design process1610preferably translates an embodiment of the invention as shown inFIGS. 1-15, along with any additional integrated circuit design or data (if applicable), into a second design structure1690. Design structure1690resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g. information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures). Design structure1690may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as described above with reference toFIGS. 1-15. Design structure1690may then proceed to a stage1695where, for example, design structure1690proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.