Semicondcutor package and manufacturing method thereof

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has at least one chip, through interlayer vias aside the chip and a composite molding compound encapsulating the chip and the through interlayer vias. The semiconductor package may further include a redistribution layer and conductive elements disposed on the redistribution layer.

BACKGROUND

Developments of the three-dimensional integration technology for wafer level packaging are underway to satisfy the demands of size reduction, high performance interconnects and heterogeneous integration for high-density integration packages.

DETAILED DESCRIPTION

In addition, terms, such as “first,” “second,” “third,” “fourth,” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description.

FIG. 1AtoFIG. 1Iare schematic cross sectional views of various stages in a manufacturing method of a semiconductor package according to some exemplary embodiments.FIG. 5is an exemplary flow chart showing the process steps of a manufacturing method of a semiconductor package according to some exemplary embodiments of the present disclosure. In exemplary embodiments, the semiconductor manufacturing method is part of a packaging process. In some embodiments, two chips or dies are shown to represent plural chips or dies of the wafer, and one or more packages10are shown to represent plural semiconductor packages obtained following the semiconductor manufacturing method.

Referring toFIG. 1Aand in Step S502ofFIG. 5, in some embodiments, a carrier102with a buffer layer104coated thereon is provided, the carrier102may be a glass carrier or any suitable carrier for carrying a semiconductor wafer or a reconstituted wafer for the manufacturing method of the semiconductor package. In some embodiments, the buffer layer104includes a debond layer and the material of the debond layer may be any material suitable for bonding and debonding the carrier102from the above layers or wafer disposed thereon. In some embodiments, the buffer layer104includes, for example, a light-to-heat conversion (“LTHC”) layer, and such layer enables room temperature debonding from the carrier by applying laser irradiation. Referring toFIG. 1A, in some embodiments, the buffer layer104includes a dielectric material layer made of a dielectric material including benzocyclobutene (“BCB”), polybenzooxazole (“PBO”), or any other suitable polymer-based dielectric material. In certain embodiments, a seed layer106is formed on the buffer layer104. In some embodiments, the seed layer106includes one or more metal layers formed by sputtering or deposition.

Referring toFIG. 1Band in Step S504ofFIG. 5, in some embodiments, through interlayer vias (“TIVs”)120are formed on the buffer layer104over the carrier102. In some embodiments, the TIVs120are through integrated fan-out (“InFO”) vias. In some embodiments, the formation of the TIVs120includes forming a mask pattern (not shown) with openings on the seed layer106partially exposing the seed layer106, then forming a metallic material (not shown) filling up the openings by electroplating or deposition, and removing the mask pattern to form the TIVs120on the seed layer106. The seed layer106is partially removed or patterned using the TIVs120as the mask so that the seed layer106located between the TIVs120and the buffer layer104is remained. The material of the seed layer106varies depending on the material of the later-formed TIVs. In certain embodiments, the seed layer106(inFIG. 1A) is formed by firstly sputtering a composite layer of a titanium layer and a copper seed layer (not shown) over the buffer layer104on the carrier102, while the TIVs120are subsequently formed by electroplating the metallic material (such as copper or a copper alloy) to fill the openings of the mask pattern. However, it is appreciated that the scope of this disclosure is not limited to the materials and descriptions disclosed above.

Referring toFIG. 1Cand in Step S506ofFIG. 5, first chips130are provided and disposed on the exposed buffer layer104on the carrier102. In exemplary embodiments, the first chips130may include the same types of chips or different types of chips or and may be digital chips, analog chips or mixed signal chips, such as application-specific integrated circuit (“ASIC”) chips, sensor chips, wireless and radio frequency chips, memory chips, logic chips or voltage regulator chips. In some embodiments, the first chip130includes pads132on the active surface130aand metal posts134located on the pads132. In exemplary embodiments, the pads132are aluminum contact pads. In one embodiment, the metal posts134are copper posts or copper alloy posts having a height ranging from about 20 microns to about 25 microns measuring from the active surface130ato its own top surface, for example. In certain embodiment, solders136may further be included and disposed on top of the metal posts134. In certain embodiments, a die attach film110is disposed between the backside of the first chip130and the buffer layer104for better attachment, and the backsides of the first chips130are adhered to the carrier102. In some embodiments, before placing the first chips130on the carrier102, the metal posts134along with the solders136on the first chips130are uncovered (i.e. bare dies not molded or encapsulated) and the die attach film110is attached to the backside of the first chip130. In some embodiments, the first chips130are placed over the carrier102and arranged aside the TIVs120(within the area surrounding by the TIVs). In some embodiments, as shown inFIG. 1C, the dotted line represents the cutting line of the whole package100in the subsequent cutting process and some of the TIVs120are arranged close to but not on the cutting line, and are arranged around the first chips130.

Referring toFIG. 1Dand in Step S508ofFIG. 5, in some embodiments, a molding compound160is formed over the carrier102and the first chips130on the buffer layer104and the TIVs120located over the carrier102beside the first chips130are molded in the molding compound160. In some embodiments, the molding compound160covers the buffer layer104and fills between the first chips130and the TIVs120. In certain embodiments, the molding compound160that partially covers the TIVs120and the first chips is formed through the exposed TIV over molding technology. In exemplary embodiments, the exposed TIV over molding technology utilizes a mold chase with a release film coated on its inner surface to control the cured molded material covers the chips or components but exposes the TIVs. In some embodiments, the formed molding compound160covers the first chips130(covering the pads132but exposing portions of the metal posts134and exposing the solders136) and covers the TIVs120partially with top portions of the TIVs120exposed. That is, the top surface160aof the molding compound160is lower than the top surfaces120aof the TIVs120, lower than the solders136and lower than the tops of the metal posts134but higher than the active surface130aof the first chip130. In one embodiment, the height difference h1(i.e., the distance in the thickness direction vertical to the active surface130a) between the molding compound160and the first chip130(i.e. the height difference between the top surface160aand the active surface130a) ranges from about 15 microns to about 20 microns. As shown inFIG. 1D, the molding compound160does not cover the entirety of the TIVs120and the metal posts134as the solders136, the tops of the metal posts134and the top portions of the TIVs120are exposed from the molding compound160. That is, portions of the TIVs120and portions of the metal posts134(and solders136) are protruded from the top surface160aof the molding compound160. In one embodiment, the material of the molding compound160includes at least one type of filler-containing resins and the resins may be epoxy resins, phenolic resins or silicon-containing resins. In exemplary embodiments, the fillers are made of non-melting inorganic materials and the fillers include metal oxide particles, silica particles or silicate particles. In some embodiments, the fillers are particles with the average particle size ranging from about 3 microns to about 20 microns, ranging from about 10 microns to about 20 microns or ranging from about 15 microns to about 20 microns. In one embodiment, the particle size of the fillers contained in the molding compound160is smaller than or at most equivalent to the height difference h1. In other words, the height difference h1is larger than or at least equivalent to the particle size of the fillers contained in the molding compound160to better cover the active surface of the first chip(s). The surface roughness or surface flatness of the cured molding compound varies depending on fine or coarse filler particles added in the molding compound material. Better surface smoothness and flatness of the molding compound is achievable if fine filler particles are used. Alternatively, some pits may be formed in the surface(s) of the molding compound added with medium or coarse filler particles, resulting in larger surface roughness or even unevenness and possible connection failure.

Referring toFIG. 1Eand in Step S510ofFIG. 5, in some embodiments, a polymeric molding compound170is formed on the molding compound160. As shown inFIG. 1E, the polymeric molding compound170is formed over the molding compound160covering the solders136, the tops of the metal posts134and the top portions of the TIVs120, which are exposed from the molding compound160, so that the entirety of the TIVs120, the first chips130and the metal posts134and solders136thereon is encapsulated by the molding compound160and the polymeric molding compound170. In some embodiments, the protruded portions of the TIVs120and the metal posts134(and the solders136) are encapsulated by the polymeric molding compound170. In some embodiments, the thickness (or height h2) of the polymeric molding compound170(measuring from the top surface160aof the molding compound160to the top surface170aof the polymeric molding compound170) ranges from about 10 microns to about 15 microns, for example. That is, the top surface170aof the polymeric molding compound170is higher than the top surfaces120aof the TIVs120and the solders136and higher than the tops of the metal posts134of the first chip130. In alternative embodiments, the top surface170aof the molding compound170may be substantially leveled with the top surfaces120aof the TIVs120and the solders136and higher than the tops of the metal posts134of the first chip130. In one embodiment, the height difference h2between the top surface170aof the polymeric molding compound170and the top surface160aof the molding compound160ranges from about 10 microns to about 15 microns. In certain embodiments, the material of the polymeric molding compound170is different from the material of the molding compound160. In exemplary embodiments, the material of the molding compound170includes a polymeric material free of fillers, and the polymeric material is selected from low-temperature curable polyimide (PI) materials, photosensitive or non-photosensitive dry film materials, epoxy resins, benzocyclobutene, polybenzooxazole, and any other suitable polymeric dielectric material. As the material of the polymeric molding compound170does not contain fillers and has better flow ability, the polymeric molding compound170can offer better coverage and filling capability over the underlying elements and molding compound160, leading to better surface flatness and structural integrity and strength for the composite structure of the polymeric molding compounds160,170.

Referring toFIG. 1Fand in Step S512ofFIG. 5, in some embodiments, a planarization process is performed to the composite structure of the molding compounds160,170, so that parts of the polymeric molding compound170and the TIVs120are removed together with the removal of the solders136until the metal posts134of the first chips130are exposed from the polymeric molding compound170. In certain embodiments, after the planarization, the metal posts134, the TIVs120and the polymeric molding compound170become flattened and substantially leveled (i.e. top surfaces134bof the metal posts134and top surfaces120bof the TIVs120are substantially coplanar and flush with the polished top surface170bof the polymeric molding compound170). In some embodiments, the planarization process for planarizing the polymeric molding compound170and the TIVs120includes a fly cut process, a grinding process or a chemical mechanical polishing (“CMP”) process. In some embodiments, the thickness (or height h3) of the planarized polymeric molding compound170(measuring from the top surface160aof the molding compound160to the planarized top surface170bof the polymeric molding compound170) ranges from about 5 microns to about 10 microns, for example. In exemplary embodiments, the ratio of h1/h3ranges from about 1.5 to about 4. The metal posts134and the TIVs120are exposed from the top surface170bof the planarized polymeric molding compound170for further connection. The polymeric molding compound170and the molding compound160constitute a composite molding compound. In alternative embodiments, the planarization process may be optional if the polymeric molding compound almost flushes with the tops of the metal posts and/or the TIVs.

FIG. 2is a schematic enlarged cross sectional view illustrating a semiconductor package following the processes ofFIGS. 1A-1Faccording to some exemplary embodiments of the present disclosure. Referring toFIG. 2, certain structural features including the interface between the molding compound160and the polymeric molding compound170are stressed for illustration purposes, and only one package10of the whole package structure100is shown for easy illustration. In exemplary embodiments, as shown inFIG. 2, the package10includes at least one first chip130and TIVs120arranged aside of the first chip130, and the first chip includes pads132formed on the active surface130aof the first chip130and metal posts134disposed on the pads132. In some embodiments, the first chip130(together with the pads132and the metal posts134of the first chip130) and the TIVs120are encapsulated within the molding compound160and the polymeric molding compound170. In some embodiments, the molding compound160at least covers the first chip130and the pads132thereon and partially covers and wraps around the TIVs120. In some embodiments, the top surface160aof the molding compound160is higher than the active surface130aof the first chip130but lower than the top surfaces120bof the TIVs120. That is, portions of the metal posts134and portions of the TIVs120are exposed from the molding compound160but are encapsulated in the polymeric molding compound170. In certain embodiments, some pits P may be formed in the top surface160aof the molding compound160added with fillers162(e.g. medium or coarse filler particles), and the polymeric molding compound170without fillers is formed to cover the molding compound160, encapsulate the metal posts134and TIVs120and fill the pits P. In some embodiments, the size of the pits P at the interface160abetween the molding compound160and the polymeric molding compound170is slightly smaller or about the size of the fillers162. Referring toFIG. 2, as the polymeric molding compound170does not contain fillers, the polished or planarized polymeric molding compound170has little or even no pits generated thereon following the planarization process and has satisfactory surface smoothness and flatness. In certain embodiments, the planarized top surface170bof the polymeric molding compound170has a surface roughness of merely about 3 microns or even less than 3 microns. As shown inFIG. 1FandFIG. 2, the composite structure of molding compound160and the polymeric molding compound170provides better planarization and enhanced protection for the chips and TIVs encapsulated therein.

Referring toFIG. 1Gand in Step S514ofFIG. 5, in some embodiments, a redistribution layer180is formed on the polymeric molding compound170, over the metal posts134of the first chips130and on the TIVs120. In some embodiment, the redistribution layer180is electrically connected to the TIVs120and the metal posts134of the first chips130. The formation of the redistribution layer180includes sequentially forming one or more dielectric material layers and one or more metallization layers in alternation. In certain embodiments, the metallization layer(s) may be sandwiched between the dielectric material layer(s), but at least the bottom metallization layer182of the redistribution layer180is physically connected to the metal posts134of the first chips130and the TIVs120. In some embodiments, the material of the metallization layer(s) includes aluminum, titanium, copper, nickel, tungsten, silver and/or alloys thereof. In some embodiments, the material of the dielectric material layer(s) includes polyimide, benzocyclobutene, or polybenzooxazole. In some embodiments, the redistribution layer180is a front-side redistribution layer electrically connected to the first chips130and is electrically connected to the TIVs120. In certain embodiments, as the underlying molding compounds160,170provides better planarization and evenness, the later-formed redistribution layer180, especially the metallization layer with thin line width or tight spacing, can be formed with uniform line-widths or even profiles over the flat and level polymeric molding compound170, resulting in improved line/wiring reliability.

Referring toFIG. 1Gand in Step S516ofFIG. 5, in some embodiments, the conductive elements200are disposed on the redistribution layer180and are electrically connected to the redistribution layer180. In some embodiments, prior to disposing the conductive elements200, flux may be applied so that the conductive elements200are better fixed to a top metallization layer (not shown) of the redistribution layer, and the top metallization layer may function as contact pads for the conductive elements200. In some embodiments, the conductive elements200are, for example, solder balls or ball grid array (“BGA”) balls placed on the redistribution layer180and the top metallization layer underlying the conductive elements200functions as ball pads. In some embodiments, some of the conductive elements200are electrically connected to the first chips130through the redistribution layer180, and some of the conductive elements200are electrically connected to the TIVs120.

In Step S518ofFIG. 5and referring toFIGS. 1G & 1H, in some embodiments, the whole package100is debonded from the carrier102to separate the first chips130from the carrier102. In some embodiments, after debonding from the carrier102, the buffer layer104remained on the whole package100is removed through an etching process or a cleaning process. Optionally, in later processes, another redistribution layer (not shown) will be formed at the backside of the chip130and over the other surface160bof the molding compound160. Alternatively, in one embodiment, the buffer layer104may be remained.

Referring toFIG. 1H, in some embodiments, the whole package100is turned upside down and disposed on a carrier film300. Subsequently, in certain embodiments, a dicing process is performed to cut the whole package structure (at least cutting though the molding compound160, the polymeric molding compound170, and the redistribution layer180) along the cutting line (the dotted line) into individual and separated semiconductor packages10, as shown inFIG. 1Iand in Step S520ofFIG. 5. In one embodiment, the dicing process is a wafer dicing process including mechanical blade sawing or laser cutting.

Referring toFIG. 1I, as the package structure is turned upside down, the top surfaces may become the bottom surfaces and the relative positional relationships (such as above, below, higher or lower) may become the opposite for the package structures as described above, but the same surfaces, common surfaces or interfaces will be marked with the same reference numbers for the individual semiconductor package(s)10.

In exemplary embodiments, the manufacturing method(s) described above is part of the packaging processes, and a plurality of semiconductor packages10is obtained after the wafer dicing process. During the packaging processes, the semiconductor package structure10may be further mounted with additional packages, chips/dies or other electronic devices.

FIG. 3is a schematic cross sectional view illustrating a semiconductor package according to some exemplary embodiments. InFIG. 3, a semiconductor package10similar to the structure as shown inFIG. 1Iis described, except the seed layer106is omitted. Referring toFIG. 3, in exemplary embodiments, the semiconductor package10comprises a redistribution layer180, a polymeric molding compound170disposed on the redistribution layer and through interlayer vias (TIVs)120disposed on the redistribution layer180and penetrating through the polymeric molding compound170. In some embodiments, conductive elements200are disposed on the redistribution layer180and the conductive elements200are electrically connected to the redistribution layer180. Also, in some embodiments, a molding compound160is disposed on the polymeric molding compound170and at least one chip130is encapsulated within the molding compound160. The chip130is disposed above the redistribution layer180and the polymeric molding compound170. In some embodiments, an active surface130aof the chip130has pads132thereon and metal posts134connected to the pads132are disposed on and underneath the pads132. In some embodiments, the TIVs120are arranged aside and surrounding the chip130, and the redistribution layer180is physically and electrically connected with the TIVs120and the metal posts134of the chip130. In some embodiments, the molding compound160encapsulates the pads132and the chip130and wraps around the TIVs120and the metal posts134. In some embodiments, as shown inFIG. 3, portions of the TIVs120and the metal posts134are protruded out of the molding compound160, and the protruded portions of the TIVs120and the metal posts134are encapsulated by the polymeric molding compound170. In some embodiments, the TIVs120penetrating through the molding compound160and the polymeric molding compound170are in physical contact with the metallization layer182of the redistribution layer180. In some embodiments, a material of the polymeric molding compound is different from a material of the molding compound. In some embodiments, the molding compound160includes fillers and the polymeric molding compound170contains no fillers. In some embodiments, the material of the molding compound160includes at least one type of filler-containing resins and the resins may be epoxy resins, phenolic resins or silicon-containing resins. In exemplary embodiment, the fillers are made of non-melting inorganic materials and the fillers include metal oxide particles, silica particles or silicate particles with the average particle size ranging from about 3 microns to about 20 microns, from about 10 microns to about 20 microns or ranging from about 15 microns to about 20 microns. In exemplary embodiments, the material of the molding compound170includes a polymeric material free of fillers and the polymeric material is selected from low-temperature curable polyimide (PI) materials, photosensitive or non-photosensitive dry film materials, epoxy resins, benzocyclobutene, polybenzooxazole, and any other suitable polymeric dielectric material.

Referring toFIG. 3, in some embodiments, the height difference h1between an active surface130aof the chip130and the interface160abetween the molding compound160and the polymeric molding compound170is larger than the height difference h3between the interface160abetween the molding compound160and the polymeric molding compound170and the interface170bbetween the polymeric molding compound170and the redistribution layer180. In some embodiments, the height difference h1is about 1.5 times to about 4 times of the height difference h3. In some embodiments, the height difference h1is larger than or at least equivalent to the particle size of the fillers contained in the molding compound160so that the molding compound160fully covers the active surface130aof the chip130.

InFIG. 4, in exemplary embodiments, a semiconductor package10is provided, and the semiconductor package10is similar to the package10as seen inFIG. 1Iand may be fabricated following the previously described manufacturing process as described inFIG. 1A-1H. The elements similar to or substantially the same as the elements described above will use the same reference numbers, and certain details or descriptions of the same elements will not be repeated herein. Referring toFIG. 4, in some embodiments, at least one semiconductor sub-package50is provided and disposed on the semiconductor package10. In exemplary embodiments, the sub-package50includes a second chip502, a third chip504stacked thereon, at least one redistribution layer510electrically connected with the second and third chips502,504and connectors520disposed on the redistribution layer510. In some embodiments, the semiconductor sub-package50is connected with the semiconductor package10through the connectors520. In some embodiments, at least one of the chips502,504is electrically connected with the first chip130and/or the conductive elements200through the redistribution layer510, connectors520, TIVs120and the redistribution layer180. In some embodiments, an underfill material400is filled between the semiconductor sub-packages50and the semiconductor package10.

The formation of the molding compound and the polymeric molding compound covering the molding compound provides flexibility in material choices and larger process window for the molding compound and improved reliability for the redistribution layer having fine line/space. Corresponding to particle sizes of the fillers contained in the material of the molding compound, the polymeric molding compound without containing fillers can cover possibly generated pits on the molding compound to provide a better planarized surface, beneficial for the later formed metal lines or wirings thereon, especially for metal lines with fine line/space.

According to some embodiments, a semiconductor package has at least one chip, a polymeric molding compound, a molding compound, and through interlayer vias. The through interlayer vias are disposed within and penetrate through the molding compound. The at least one chip is disposed within the molding compound. The through interlayer vias are arranged aside and surrounding the at least one chip. The at least one chip has metal posts disposed thereon. The molding compound encapsulates the at least one chip and wraps around the through interlayer vias and the metal posts of the at least one chip, and portions of the metal posts and the through interlayer vias are protruded out of the molding compound. The polymeric molding compound is disposed on the molding compound, and the polymeric molding compound encapsulates the protruded portions of the metal posts and the through interlayer vias. A material of the polymeric molding compound is different from a material of the molding compound.

According to some embodiments, a semiconductor package has a chip, through interlayer vias and a composite molding compound. The composite molding compound comprises a polymeric molding compound and a molding compound disposed on the polymeric molding compound. The through interlayer vias are disposed within the composite molding compound and penetrate through the composite molding compound. The chip is disposed within the molding compound, encapsulated by the molding compound and surrounded by the through interlayer vias. An active surface of the chip has metal posts disposed thereon. Portions of the through interlayer vias and the metal posts are wrapped by the molding compound and other portions of the through interlayer vias and the metal posts are wrapped by the polymeric molding compound. The molding compound contains fillers and the polymeric molding compound contains no fillers.

According to some embodiments, a manufacturing method for semiconductor packages is provided. Through interlayer vias are formed on a carrier. Chips are disposed on the carrier and aside the through interlayer vias. An active surface of the chip has metal posts formed thereon. A molding compound is formed over the carrier, encapsulating the chips and wrapping around portions of the through interlayer vias and the metal posts, leaving portions of the through interlayer vias and the metal posts protruded out of the molding compound. A polymeric molding compound is formed on the molding compound, encapsulating the protruded portions of the through interlayer vias and the metal posts. The polymeric molding compound is planarized until the through interlayer vias and the metal posts are exposed. A dicing process is performed cutting through the molding compound and the planarized polymeric molding compound to separate the semiconductor packages.