Semiconductor device

A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

This application claims the benefit of priority under 35 USC § 119 to Korean Patent Application No. 10-2018-0068000, filed on Jun. 14, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The present disclosure relates to a semiconductor device.

2. Description of the Related Art

As one of the scaling techniques for increasing the density of a semiconductor device, a multi-gate transistor has been suggested. The multi-gate transistor may be obtained by forming a fin- or nanowire-shaped multi-channel active pattern (or silicon body) on a substrate and forming gates on the surface of the multi-channel active pattern.

The multi-gate transistor can be easily scaled because it uses a three-dimensional (3D) channel. In addition, the current control capability of the multi-gate transistor can be improved without the need to increase the gate length of the multi-gate transistor. Moreover, it is possible to effectively suppress a short channel effect (SCE) in which an electric potential of a channel region is affected by a drain voltage.

SUMMARY

Aspects of the present disclosure provide a semiconductor device with increased element integration density and improved reliability and performance.

According to some embodiments of the present disclosure, there is provided a semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

According to some embodiments of the present disclosure, there is provided a semiconductor device comprising a first fin pattern and a second fin pattern aligned in a first direction which is a longitudinal direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a first isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern, a third gate structure which intersects the first fin pattern and the third fin pattern and a first element isolation structure which fills the first isolation trench, wherein an upper surface of the first element isolation structure is higher than an upper surface of the third fin pattern.

According to some embodiments of the present disclosure, there is provided a semiconductor device comprising a first fin pattern and a second fin pattern which are disposed in an n-type metal oxide semiconductor (NMOS) region and aligned in a first direction which is a longitudinal direction, a third fin pattern which is disposed in a p-type metal oxide semiconductor (PMOS) region, is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a first isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern, a first element isolation structure which fills the first isolation trench and a gate insulating support which is formed between the first gate structure and the first element isolation structure to contact the first gate structure and the first element isolation structure.

DETAILED DESCRIPTION

In the drawings relating to semiconductor devices according to embodiments, a fin field effect transistor (FinFET) including a channel region of a fin pattern shape is illustrated by way of example. However, embodiments are not limited to the FinFET. The semiconductor devices according to the embodiments may also include a tunneling FET, a transistor including nanowires, a transistor including a nanosheet, or a three-dimensional (3D) transistor. In addition, the semiconductor devices according to the embodiments may include a bipolar junction transistor, a lateral double diffusion transistor (LDMOS), or the like.

FIG. 1is a schematic plan view of a semiconductor device according to embodiments.FIG. 2is a cross-sectional view taken along line A-A ofFIG. 1.FIG. 3is a cross-sectional view taken along line B-B ofFIG. 1.FIG. 4is a cross-sectional view taken along line C-C ofFIG. 1.FIG. 5is a cross-sectional view taken along line D-D ofFIG. 1.FIG. 6is a cross-sectional view taken along line E-E ofFIG. 1. For ease of description, a lower interlayer insulating film191and an upper interlayer insulating film192are not illustrated inFIG. 1.

It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Unless the context indicates otherwise, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, for example as a naming convention. Thus, a first element, component, region, layer or section discussed below in one section of the specification could be termed a second element, component, region, layer or section in another section of the specification or in the claims without departing from the teachings of the present invention. In addition, in certain cases, even if a term is not described using “first,” “second,” etc., in the specification, it may still be referred to as “first” or “second” in a claim in order to distinguish different claimed elements from each other.

Referring toFIGS. 1 through 6, the semiconductor device according to the embodiments includes first fin patterns110, second fin patterns210, third fin patterns310and fourth fin patterns410, first gate structure120, second gate structure220, third gate structure320, and fourth gate structure420, a gate insulating support160, and a first element isolation structure180.

Each of the first through fourth fin patterns110,210,310, and410may protrude from the substrate100. Each of the first through fourth fin patterns110,210,310, and410may extend on the substrate100along a first direction X. For example, each of the first through fourth fin patterns110,210,310, and410may include long sides extending in the first direction X and short sides extending in a second direction Y perpendicular to the first direction X. Each of the first through fourth fin patterns110,210,310, and410may be defined by a fin trench FT. For example, each of long sides110a,210a,310aand410aof the first through fourth fin patterns110,210,310, and410may be defined by the fin trench FT.

The first and second fin patterns110and210may be aligned in the first direction X which is a longitudinal direction. The first fin patterns110may be spaced apart from the second fin patterns210in the first direction X. Short sides110bof the first fin patterns110and short sides210bof the second fin patterns210may face each other. The first fin patterns110and the second fin patterns210may be separated by a fin-cut trench ST.

The third and fourth fin patterns310and410may be aligned in the first direction X which is the longitudinal direction. The third fin patterns310may be spaced apart from the fourth fin patterns410in the first direction X. Short sides310bof the third fin patterns310and short sides410bof the fourth fin patterns410may face each other. The third fin patterns310and the fourth fin patterns410may be separated by a first isolation trench180t. For example, a width W11of the fin-cut trench ST in the first direction X is greater than a width W12of the first isolation trench180tin the first direction X based on upper surfaces of the first through fourth fin patterns110,210,310, and410.

The third and fourth fin patterns310and410may be spaced apart from the first fin patterns110in the second direction Y. The long sides310aof the third fin patterns310may face the long sides110aof the first fin patterns110, and the long sides410aof the fourth fin patterns410may face the long sides210aof the second fin patterns210. Although each of the first through fourth fin patterns110,210,310, and410is illustrated as being plural, embodiments are not limited to this case.

When the first and second fin patterns110and210are formed in a first region and the third and fourth fin patterns310and410are formed in a second region, the first region and the second region may be regions in which transistors of the same conductivity type are formed or may be regions in which transistors of different conductivity types are formed.

In the following description, it is assumed that the first and second fin patterns110and210are formed in an n-type metal oxide semiconductor (NMOS) region and the third and fourth fin patterns310and410are formed in a p-type metal oxide semiconductor (PMOS) region.

Each of the first through fourth fin patterns110,210,310, and410may be a part of the substrate100or may include an epitaxial layer grown from the substrate100. Each of the first through fourth fin patterns110,210,310, and410may include an elemental semiconductor material such as silicon or germanium. In addition, each of the first through fourth fin patterns110,210,310, and410may include a compound semiconductor such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, e.g., a binary or ternary compound including two or more of carbon (C), silicon (Si), germanium (Ge) and tin (Sn) or a compound obtained by doping the binary or ternary compound with a group IV element. The group III-V compound semiconductor may be, e.g., a binary, ternary, or quaternary compound composed of at least one of aluminum (Al), gallium (Ga) and indium (In) (i.e., group III elements) bonded with one of phosphorus (P), arsenic (As) and antimony (Sb) (i.e., group V elements).

A field insulating layer105may be formed on the substrate100. The field insulating layer105may at least partially fill the fin-cut trench ST and the fin trench FT. The field insulating layer105may be disposed on a part of sidewalls of each of the first through fourth fin patterns110,210,310, and410.

The upper surfaces of the first through fourth fin patterns110,210,310, and410may protrude above an upper surface of the field insulating layer105. The field insulating layer105may include at least one of, for example, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. In the semiconductor device according to the embodiments, the field insulating layer105may fill a part of the fin-cut trench ST.

Each of first through fourth gate structures120,220,320, and420may extend on the field insulating layer105in the second direction Y. The first gate structure120may be disposed on the first fin patterns110to intersect the first fin patterns110. The first gate structure120may overlap ends of the first fin patterns110including the short sides110bof the first fin patterns110. A portion of the first gate structure120may extend along the upper surface of each of the first fin patterns110.

The second gate structure220may be disposed on the second and fourth fin patterns210and410to intersect the second and fourth fin patterns210and410. The second gate structure220may overlap ends of the second fin patterns210including the short sides210bof the second fin patterns210. A portion of the second gate structure220may extend along the upper surface of each of the second fin patterns210.

The third gate structure320may be disposed on the first and third fin patterns110and310to intersect the first and third fin patterns110and310. The fourth gate structure420may be disposed on the second and fourth fin patterns210and410to intersect the second and fourth fin patterns210and410. The third and fourth gate structures320and420do not overlap the ends of the first and second fin patterns110and210, respectively.

In the semiconductor device according to the embodiments, the first gate structure120may cover the ends of the first fin patterns110, and the second gate structure220may cover the ends of the second fin patterns210. The first gate structure120may cover the sidewalls of the first fin patterns110which define the short sides110bof the first fin patterns110. The second gate structure220may cover the sidewalls of the second fin patterns210which define the short sides210bof the second fin patterns210.

The first through fourth gate structures120,220,320, and420may include first through fourth gate electrodes130,230,330, and430, first through fourth gate insulating layers135,235,335, and435, first through fourth gate spacers140,240,340, and440, first through fourth gate trenches140t,240t,340t, and440tdefined by the first through fourth gate spacers140,240,340, and440, and first through fourth capping patterns145,245,345, and445, respectively.

The first through fourth gate insulating layers135,235,335, and435may extend along sidewalls and bottom surfaces of the first through fourth gate trenches140t,240t,340t, and440t, respectively. Each of the first through fourth gate insulating layers135,235,335, and435may include a high dielectric constant insulating layer.

The high dielectric constant insulating layer may include a high dielectric material having a higher dielectric constant than a silicon oxide layer. Each of the first through fourth gate insulating layers135,235,335, and435may include one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

The first through fourth gate electrodes130,230,330, and430may be disposed on the first through fourth gate insulating layers135,235,335, and435, respectively. The first through fourth gate electrodes130,230,330, and430may at least partially fill the first through fourth gate trenches140t,240t,340t, and440t, respectively.

The first through fourth gate spacers140,240,340, and440may be formed on sidewalls of the first through fourth gate electrodes130,230,330, and430, respectively. Each of the first through fourth gate spacers140,240,340, and440may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), and silicon oxycarbonitride (SiOCN).

The first through fourth capping patterns145,245,345, and445may be formed on the first through fourth gate electrodes130,230,330, and430and the first through fourth gate spacers140,240,340, and440, respectively.

Each of the first through fourth capping patterns145,245,345, and445may include at least one of, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon oxycarbonitride (SiOCN).

InFIGS. 2, 3 and 5, the first through fourth capping patterns145,245,345, and445are illustrated as not filling part of the first through fourth gate trenches140t,240t,340t, and440t, respectively. However, this is merely an example used for ease of description, and embodiments are not limited to this example.

A first epitaxial pattern150may be formed on each of the first fin patterns110. A second epitaxial pattern250may be formed on each of the second fin patterns210. A third epitaxial pattern350may be formed on each of the third fin patterns310. A fourth epitaxial pattern450may be formed on each of the fourth fin patterns410.

The first epitaxial pattern150may be included in a source/drain of a transistor using the first fin pattern110as a channel region. The second epitaxial pattern250may be included in a source/drain of a transistor using the second fin pattern210as a channel region. The third epitaxial pattern350may be included in a source/drain of a transistor using the third fin pattern310as a channel region. The fourth epitaxial pattern450may be included in a source/drain of a transistor using the fourth fin pattern410as a channel region.

The lower interlayer insulating film191may be formed on the field insulating layer105and may cover the first through fourth epitaxial patterns150,250,350, and450. The lower interlayer insulating film191may be formed around the first through fourth gate structures120,220,320, and420. The lower interlayer insulating film191may at least partially cover sidewalls of the first through fourth gate structures120,220,320, and420.

An upper surface of the lower interlayer insulating film191may lie in the same plane as an upper surface of each of the first through fourth capping patterns145,245,345, and445. A lower surface of the lower interlayer insulating film191may lie below a lower surface of each of the first through fourth capping patterns145,245,345, and445.

Although not illustrated, the lower interlayer insulating film191may further include an etch stop layer extending along upper surfaces of the first through fourth epitaxial patterns150,250,350, and450.

The first element isolation structure180may be disposed between the third fin patterns310and the fourth fin patterns410. The first element isolation structure180may be disposed between the short sides310band410bof the third and fourth fin patterns310and410. The first element isolation structure180may separate the third fin patterns310and the fourth fin patterns410. The first element isolation structure180may be disposed between the second gate structure220and the third gate structure320.

The first element isolation structure180includes first sides180aextending in the first direction X and second sides180bextending in the second direction Y. A first side180aof the first element isolation structure180may face a short side120bof the first gate structure120. The second sides180bof the first element isolation structure180may face the short sides310band410bof the third and fourth fin patterns310and410.

The first element isolation structure180and the first gate structure120may be aligned in the second direction Y. The first element isolation structure180is disposed on an extension line of the first gate structure120extending in the second direction Y.

The first element isolation structure180may be disposed in the first isolation trench180tincluded in the lower interlayer insulating film191. The first element isolation structure180may fill the first isolation trench180t. The first isolation trench180tmay be formed between the third epitaxial pattern350and the fourth epitaxial pattern450.

Sidewalls of the first isolation trench180textending in the second direction Y between the third epitaxial pattern350and the fourth epitaxial pattern450may be defined by first dummy spacers185, the lower interlayer insulating film191, and the third and fourth fin patterns310and410.

An upper surface of the first element isolation structure180is higher in the second direction Y than the upper surfaces of the third and fourth fin patterns310and410in the second direction Y. For example, the upper surface of the first element isolation structure180may lie in the same plane as the upper surface of the lower interlayer insulating film191. The upper surface of the first element isolation structure180may lie in the same plane as upper surfaces of the second through fourth gate structures220,320, and420.

InFIG. 3, a width between the sidewalls of the first isolation trench180tdefined by the third and fourth fin patterns310and410increases as the distance from the substrate100increases. For example, a width of the first isolation trench180tin the first direction X between the sidewalls of the first isolation trench180tdefined by the third and fourth fin patterns310and410may gradually increase in an upward direction (second direction Y) away from an upper surface of the substrate100. However, embodiments are not limited to this case. For example, according to alternative embodiments, a width between the sidewalls of the first isolation trench180tdefined by the third and fourth fin patterns310and410may not change as the distance from the substrate100increases.

InFIG. 4, a part of sidewalls of the first isolation trench180textending in the first direction X may be defined by the field insulating layer105. A portion of the first isolation trench180tmay be, but not necessarily, recessed into the field insulating layer105.

A bottom surface of the first isolation trench180tmay be defined by the field insulating layer105, the substrate100and a remaining fin RF. The remaining fin RF may be a portion remaining after a fin pattern portion is removed in an etching process for forming the first isolation trench180t. The remaining fin RF may also not be present, unlike in the drawing.

The first element isolation structure180may include at least one of, for example, silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, and aluminum oxide. Although the first element isolation structure180is illustrated as a single layer, this is merely an example used for ease of description, and the first element isolation structure180is not limited to a single layer.

The material composition of the first dummy spacers185and the first gate spacers140may be the same. Unlike in the drawings, the first dummy spacers185may not be disposed on sidewalls of the first element isolation structure180.

The gate insulating support160may be disposed on the field insulating layer105between the first and third fin patterns110and310. The gate insulating support160may be spaced apart from the first and third fin patterns110and310in the second direction Y.

The gate insulating support160may be disposed between the first gate structure120and the first element isolation structure180. The gate insulating support160may be disposed on the field insulating layer105between the first gate structure120and the first element isolation structure180.

The gate insulating support160may separate the first gate structure120and the first element isolation structure180. The gate insulating support160may cross between the first gate structure120and the first element isolation structure180. The first gate structure120and the first element isolation structure180may be disposed in the second direction Y with the gate insulating support160interposed between them.

The gate insulating support160contacts the first gate structure120and the first element isolation structure180.

It will be understood that when an element is referred to as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact.

The gate insulating support160includes first sides160aextending in the first direction X and second sides160bextending in the second direction Y. The first gate structure120and the first element isolation structure180contact the first sides160aof the gate insulating support160.

In the semiconductor device according to the embodiments, a width W22of the gate insulating support160in the first direction X (seeFIG. 5) may be greater than or equal to a width W21of the first gate structure120in the first direction X (seeFIG. 2).

InFIGS. 1 and 5, the width W22of the gate insulating support160in the first direction X is greater than the width W21of the first gate structure120in the first direction X.

In addition, inFIGS. 1 and 5, the gate insulating support160is not in contact with the second and third gate structures220and320. However, embodiments are not limited to this case.

The gate insulating support160may be disposed in an insulating trench160tincluded in the lower interlayer insulating film191. The gate insulating support160may fill the insulating trench160t. InFIGS. 4 and 5, a part of sidewalls of the first insulating trench160tmay be recessed into the field insulating layer105and defined by the field insulating layer105. However, embodiments are not limited to this case.

InFIG. 4, the bottom surface of the first isolation trench180tdefined by the field insulating layer105is illustrated as being closer to the substrate100than a bottom surface of the first insulating trench160t. However, embodiments are not limited to this case.

The gate insulating support160may include at least one of, for example, silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, and aluminum oxide. Although the gate insulating support160is illustrated as a single layer inFIGS. 4 and 5, this is merely an example used for ease of description, and the gate insulating support160is not limited to a single layer.

InFIG. 4, the first gate insulating layer135does not extend along the sidewalls of the gate insulating support160. The first gate electrode130may contact the gate insulating support160. For example, a sidewall of the first gate electrode130extending in the second direction Y may contact a sidewall of the gate insulating support160extending in the second direction Y. InFIG. 5, an upper surface of the gate insulating support160may lie in the same plane as the upper surface of the lower interlayer insulating film191. The upper surface of the gate insulating support160may lie in the same plane as the upper surfaces of the second through fourth gate structures220,320, and420.

The upper interlayer insulating film192is formed on the lower interlayer insulating film191, the gate insulating support160, the first element isolation structure180, and the first through fourth gate structures120,220,320, and420. An interlayer insulating film190includes the lower interlayer insulating film191and the upper interlayer insulating film192. Each of the lower interlayer insulating film191and the upper interlayer insulating film192may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, flowable oxide (FOX), tonen silazen (TOSZ), undoped silica glass (USG), borosilica glass (BSG), phosphosilica glass (PSG), borophosphosilica glass (BPSG), plasma enhanced tetraethylorthosilicate (PETEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organo silicate glass (OSG), parylene, bis-benzocyclobutenes (BCB), SiLK, polyimide, a porous polymeric material, or a combination of the same.

FIG. 7illustrates a semiconductor device according to embodiments.FIG. 8illustrates a semiconductor device according to embodiments.FIG. 9illustrates a semiconductor device according to embodiments. For ease of description, the following embodiments will be described, focusing mainly on differences from elements and features described above with reference toFIGS. 1 through 6.

Referring toFIG. 7, in the semiconductor device according to the embodiments, a first gate insulating layer135includes a portion extending along a sidewall of a gate insulating support160in the second direction Y.

The first gate insulating layer135may extend between a first gate electrode130and the gate insulating support160.

Referring toFIG. 8, in the semiconductor device according to the embodiments, first through fourth gate electrodes130,230,330, and430may partially fill first through fourth gate trenches140t,240t,340t, and440t, respectively.

First through fourth capping patterns145,245,345, and445may fill the first through fourth gate trenches140t,240t,340t, and440tremaining after the first through fourth gate electrodes130,230,330, and430are formed, respectively. Upper surfaces of first through fourth gate spacers140,240,340, and440may lie in the same plane as upper surfaces of the first through fourth capping patterns145,245,345, and445.

Although first through fourth gate insulating layers135,235,335, and435are illustrated as not extending between the first through fourth capping patterns145,245,345, and445and the first through fourth gate spacers140,240,340, and440in the drawing, embodiments are not limited to this case.

Referring toFIG. 9, in the semiconductor device according to the embodiments, upper surfaces of first through fourth gate electrodes130,230,330, and430may lie in the same plane as an upper surface of a lower interlayer insulating film191.

The upper surfaces of the first through fourth gate electrodes130,230,330, and430may lie in the same plane as an upper surface of a gate insulating support160(seeFIG. 5) and an upper surface of a first element isolation structure180(seeFIG. 3). First through fourth gate structures120,220,320, and420may not include capping patterns145,245,345, and445, respectively.

FIG. 10illustrates a semiconductor device according to embodiments.FIG. 11illustrates a semiconductor device according to embodiments. For ease of description, the following embodiments will be described, focusing mainly on differences from elements and features described above with reference toFIGS. 1 through 6.

Referring toFIG. 10, the semiconductor device according to the embodiments may further include connection spacers120cs, which protrude from an upper surface of a field insulating layer105, between a gate insulating support160and the field insulating layer105.

The connection spacers120csmay be recessed into the gate insulating support160. For example, the height of the connection spacers120csin the second direction Y is smaller than the heights of the second through fourth gate spacers240through440in the second direction Y. Bottom surfaces of the connection spacers120csand bottom surfaces of the second through fourth gate spacers240,340, and440may contact the field insulating layer105. Thus, upper surfaces of the second through fourth gate spacers240,340, and440are higher than upper surfaces of the connection spacers120cs.

In addition, the connection spacers120csare directly connected to a first gate structure120. The connection spacers120csare directly connected to first dummy spacers185disposed on sidewalls of a first element isolation structure180. The connection spacers120cscontact the first gate structure120. The material composition of the connection spacers120csand the first gate spacers140may be the same.

A bottom surface of the gate insulating support160may be defined by the field insulating layer105and the connection spacers120cs.

Referring toFIG. 11, in the semiconductor device according to the embodiments, a portion of a lower interlayer insulating film191may be interposed between a gate insulating support160and a field insulating layer105.

A bottom surface of the gate insulating support160includes a first portion defined by the field insulating layer105and second portions defined by the lower interlayer insulating film191. The second portions of the gate insulating support160may be disposed in the first direction X with the first portion of the gate insulating support160interposed between the second portions.

The gate insulating support160whose bottom surface is defined by the field insulating layer105may contact the field insulating layer105. The gate insulating support160whose bottom surface is defined by the lower interlayer insulating film191may not contact the field insulating layer105.

FIGS. 12 and 13illustrate a semiconductor device according to embodiments.FIGS. 14 and 15illustrate a semiconductor device according to embodiments. For ease of description, the following embodiments will be described, focusing mainly on differences from elements and features described above with reference toFIGS. 1 through 6.

Referring toFIGS. 12 and 13, a deep trench DT may be formed in a substrate100between a first fin pattern110and a third fin pattern310.

The deep trench DT may be deeper than a fin trench FT defining long sides110a(seeFIG. 1) of the first fin pattern110and long sides310a(seeFIG. 1) of the third fin pattern310. A field insulating layer105fills the deep trench DT.

A gate insulating support160may be formed on the field insulating layer105filling the deep trench DT.

Referring toFIGS. 14 and 15, the semiconductor device according to the embodiments may further include a protruding pattern FP protruding from a substrate100between a first fin pattern110and a third fin pattern310.

The height of the protruding pattern FP is smaller than the height of the first fin pattern110and the height of the third fin pattern310. The height of the protruding pattern FP is smaller than the height of a portion of the field insulating layer105which is overlapped by a first gate electrode130.

For example, an upper surface of the protruding pattern FP may be covered with the field insulating layer105. The protruding pattern FP may extend, but not necessarily, in the first direction X (seeFIG. 1).

Although a bottom surface of the gate insulating support160is illustrated as being higher than the upper surface of the protruding pattern FP, embodiments are not limited to this case. The gate insulating support160may also contact the protruding pattern FP. In this case, the upper surface of the protruding pattern FP is not covered with the field insulating layer105.

FIG. 16illustrates a semiconductor device according to embodiments.FIGS. 17 and 18illustrate a semiconductor device according to embodiments. For ease of description, the following embodiments will be described, focusing mainly on differences from elements and features described above with reference toFIGS. 1 through 6.

Referring toFIG. 16, the semiconductor device according to the embodiments may include contacts195penetrating an interlayer insulating film190.

The contacts195may be connected to a first epitaxial pattern150and a second epitaxial pattern250, respectively. Although the contacts195are illustrated as not contacting first through fourth gate structures120,220,320, and420, embodiments are not limited to this case.

Although each of the contacts195is illustrated as a single structure, embodiments are not limited to this case. Each of the contacts195may also include a plurality of structures arranged in a thickness direction of a substrate100.

The contacts195may include at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten carbonitride (WCN), tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu) and doped polysilicon. Unlike in the drawing, a silicide layer may also be formed between the contacts195and the epitaxial patterns150and250.

Referring toFIGS. 17 and 18, in the semiconductor device according to the embodiments, an upper surface of a field insulating layer105filling a fin-cut trench ST may be at the same height as or higher than an upper surface of a first fin pattern110and an upper surface of a second fin pattern210.

Sidewalls of the first fin pattern110defining short sides110bof the first fin pattern110and sidewalls of the second fin pattern210defining short sides210bof the second fin pattern210may be covered with the field insulating layer105.

For example, a first gate structure120does not cover the sidewalls of the first fin pattern110defining the short sides110b(seeFIG. 1) of the first fin pattern110. A second gate structure220does not cover the sidewalls of the second fin pattern210defining the short sides210b(seeFIG. 1) of the second fin pattern210.

FIG. 19is a schematic plan view of a semiconductor device according to embodiments.FIG. 20is a cross-sectional view taken along line D-D ofFIG. 19. For ease of description, the following embodiments will be described, focusing mainly on differences from elements and features described above with reference toFIGS. 1 through 6.

Referring toFIGS. 19 and 20, in the semiconductor device according to the embodiments, the width of a gate insulating support160in the first direction X may be smaller than or equal to the width of a first gate structure120in the first direction X.

The gate insulating support160may be formed between first dummy spacers185. The first dummy spacers185may be disposed on sidewalls of the gate insulating support160. The first dummy spacers185may extend along the sidewalls of the gate insulating support160and sidewalls of a first element isolation structure180.

An insulating trench160tmay be aligned with the first dummy spacers185. In the semiconductor device manufacturing process, the insulating trench160tmay be formed using the first dummy spacers185as a mask.

FIG. 21is a schematic plan view of a semiconductor device according to embodiments.FIG. 22is a cross-sectional view taken along line B-B ofFIG. 21.FIG. 23is a cross-sectional view taken along line D-D ofFIG. 21.FIG. 24is a cross-sectional view taken along line F-F ofFIG. 21. For ease of description, the following embodiments will be described, focusing mainly on differences from elements and features described above with reference toFIGS. 1 through 6.

Referring toFIGS. 21 through 24, the semiconductor device according to the embodiments may further include fifth fin patterns510, a second element isolation structure181, and a connection isolation structure182.

The fifth fin patterns510may protrude from a substrate100. The fifth fin patterns510may extend on the substrate100along the first direction X. The fifth fin patterns510may include long sides510aextending in the first direction X and short sides510bextending in the second direction Y.

The fifth fin patterns510may be aligned with third and fourth fin patterns310and410in the first direction X which is a longitudinal direction. The third through fifth fin patterns310through510may be sequentially arranged in the first direction X. The fourth fin patterns410may be disposed between the third fin patterns310and the fifth fin patterns510. The fourth fin patterns410and the fifth fin patterns510may be separated by a second isolation trench181t. The third through fifth fin patterns310through510are disposed in a region in which transistors of the same conductivity type are formed.

A second gate structure220may intersect second fin patterns210, but may not intersect the fourth and fifth fin patterns410and510. The second gate structure220may extend up to a gate insulating support160. A fourth gate structure420may be disposed on the second and fifth fin patterns210and510to intersect the second and fifth fin patterns210and510.

A fourth epitaxial pattern450may be formed on each of the fourth fin patterns410. A fifth epitaxial pattern550may be formed on each of the fifth fin patterns510.

The second element isolation structure181may be disposed between the fourth and fifth fin patterns410and510. The fourth fin patterns410may be disposed between a first element isolation structure180and the second element isolation structure181. The second element isolation structure181may be disposed between the short sides of the fourth and fifth fin patterns410and510.

The second element isolation structure181may separate the fourth fin patterns410and the fifth fin patterns510. The first and second element isolation structures180and181may be disposed between a third gate structure320and the fourth gate structure420.

The second element isolation structure181includes first sides181aextending in the first direction X and second sides181bextending in the second direction Y. A first side181aof the second element isolation structure181may face a short side220bof the second gate structure220. The second sides181bof the second element isolation structure181may face the short sides of the fourth and fifth fin patterns410and510.

The second element isolation structure181and the second gate structure220may be aligned in the second direction Y. The second element isolation structure181is disposed on an extension line of the second gate structure220extending in the second direction Y.

The second element isolation structure181may be disposed in the second isolation trench181tincluded in a lower interlayer insulating film191. The second element isolation structure181may fill the second isolation trench181t.

The second isolation trench181tmay be formed between the fourth epitaxial pattern450and the fifth epitaxial pattern550. Sidewalls of the second isolation trench181textending in the second direction Y between the fourth epitaxial pattern450and the fifth epitaxial pattern550may be defined by second dummy spacers186, the lower interlayer insulating film191, and the fourth and fifth fin patterns410and510.

An upper surface of the second element isolation structure181is higher than upper surfaces of the fourth and fifth fin patterns410and510. For example, the upper surface of the second element isolation structure181may lie in the same plane as an upper surface of the lower interlayer insulating film191.

The upper surface of the second element isolation structure181may lie in the same plane as upper surfaces of the third and fourth gate structures320and420.

InFIG. 22, a width between the sidewalls of the second isolation trench181tdefined by the fourth and fifth fin patterns410and510increases as the distance from the substrate100increases. For example, a width between the sidewalls of the second isolation trench181tdefined by the fourth and fifth fin patterns410and510in the first direction X may gradually increase in the second direction Y as the distance from the substrate100increases. However, embodiments are not limited to this case. For example, a width between the sidewalls of the second isolation trench181tdefined by the fourth and fifth fin patterns410and510in the first direction X may remain the same as the distance from the substrate100increases in the second direction Y.

InFIG. 24, a part of sidewalls of the second isolation trench181textending in the first direction X may be defined by a field insulating layer105. A portion of the second isolation trench181tmay be, but not necessarily, recessed into the field insulating layer105.

A bottom surface of the second isolation trench181tmay be defined by the field insulating layer105, the substrate100, and a remaining fin RF. The remaining pin RF may be a portion remaining after a fin pattern portion is removed in an etching process for forming the second isolation trench181t. The remaining fin RF may also not be present, unlike in the drawing.

InFIG. 24, the bottom surface of the second isolation trench181tdefined by the field insulating layer105is illustrated as being closer to the substrate100than a bottom surface of a first insulating trench160t. However, embodiments are not limited to this case.

The second element isolation structure181may include at least one of, for example, silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, and aluminum oxide. Although the second element isolation structure181is illustrated as a single layer, this is merely an example used for ease of description, and the second element isolation structure181is not limited to a single layer.

The material composition of the second dummy spacers186and the second gate spacers240may be the same. Unlike in the drawings, the second dummy spacers186may not be disposed on sidewalls of the second element isolation structure181.

The connection isolation structure182may be disposed between the first element isolation structure180and the second element isolation structure181. The connection isolation structure182may connect the first element isolation structure180and the second element isolation structure181. The second element isolation structure181may be connected to the first element isolation structure180by the connection isolation structure182.

The connection isolation structure182may connect an upper portion of the first element isolation structure180and an upper portion of the second element isolation structure181. An upper surface of the connection isolation structure182may lie in the same plane as upper surfaces of the first and second element isolation structures180and181.

The connection isolation structure182may cover the fourth fin patterns410and the fourth epitaxial patterns450. A portion of the lower interlayer insulating film191may be disposed between the connection isolation structure182and each of the fourth fin patterns410.

For example, a portion of the lower interlayer insulating film191may be disposed between the connection isolation structure182and each fourth epitaxial pattern450. For example, a lower surface of the connection isolation structure182is higher than the upper surfaces of the fourth fin patterns410and upper surfaces of the fourth epitaxial patterns450based on bottom surfaces of the first and second element isolation structures180and181.

The first and second element isolation structures180and181and the connection isolation structure182may be included in an integrated isolation structure180ST. For example, the first and second element isolation structures180and181and the connection isolation structure182may be formed in the same process to produce an integral structure.

The connection isolation structure182may include at least one of, for example, silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, and aluminum oxide.

The gate insulating support160may be disposed between a first gate structure120and the first element isolation structure180and between the second gate structure220and the second element isolation structure181. The gate insulating support160may be disposed on a field insulating layer105between the first gate structure120and the first element isolation structure180and between the second gate structure220and the second element isolation structure181.

The gate insulating support160may separate the second gate structure220and the second element isolation structure181. The gate insulating support160may cross between the second gate structure220and the second element isolation structure181.

The second gate structure220and the second element isolation structure181may be arranged in the second direction Y with the gate insulating support160interposed between them.

The gate insulating support160contacts the second gate structure220and the second element isolation structure181. The gate insulating support160may contact the connection isolation structure182.

The gate insulating support160includes first sides160aextending in the first direction X and second sides160bextending in the second direction Y. The second gate structure220and the second element isolation structure181contact the first sides160aof the gate insulating support160. The connection isolation structure182may contact a first side160aof the gate insulating support160.

In the semiconductor device according to the embodiments, the width of the gate insulating support160in the first direction X is greater than the width of the first gate structure120in the first direction X and the width of the second gate structure220in the first direction X. Although the gate insulating support160is illustrated as not contacting the third and fourth gate structures320and420inFIG. 23, embodiments are not limited to this case.

FIG. 25illustrates a semiconductor device according to embodiments.FIG. 26illustrates a semiconductor device according to embodiments. For ease of description, the following embodiments will be described, focusing mainly on differences from elements and features described above with reference toFIGS. 21 through 24.

Referring toFIG. 25, in the semiconductor device according to the embodiments, a connection isolation structure182may contact a fourth epitaxial pattern450.

In an etching process for forming the connection isolation structure182, an upper surface of the fourth epitaxial pattern450may be exposed. The connection isolation structure182may be formed on the exposed fourth epitaxial pattern450.

Referring toFIG. 26, in the semiconductor device according to the embodiments, a portion of a connection isolation structure182may be recessed into a fourth epitaxial pattern450.

In an etching process for forming the connection isolation structure182, a portion of the fourth epitaxial pattern450may be etched. The connection isolation structure182may be formed on the partially etched fourth epitaxial pattern450.

FIG. 27is a schematic plan view of a semiconductor device according to embodiments.FIG. 28is a cross-sectional view taken along line B-B ofFIG. 27. For ease of description, the following embodiments will be described, focusing mainly on differences from elements and features described above with reference toFIGS. 21 through 24.

Referring toFIGS. 27 and 28, in the semiconductor device according to the embodiments, a first element isolation structure180is separated from a second element isolation structure181.

A connection isolation structure for connecting the first element isolation structure180and the second element isolation structure181is not disposed between the first element isolation structure180and the second element isolation structure181.

The connection isolation structure for connecting the first element isolation structure180and the second element isolation structure181is not disposed on fourth fin patterns410and fourth epitaxial patterns450.

FIG. 29is a schematic plan view of a semiconductor device according to embodiments.FIG. 30is a cross-sectional view taken along line C-C ofFIG. 29. For ease of description, the following embodiments will be described, focusing mainly on differences from elements and features described above with reference toFIGS. 1 through 6.

Referring toFIGS. 29 and 30, in the semiconductor device according to the embodiments, a first gate structure120may contact a first element isolation structure180.

A short side120bof the first gate structure120may contact a second side180bof the first element isolation structure180. The first gate structure120and the first element isolation structure180that are in contact with each other may be aligned in a line along the second direction Y.

A first gate electrode130, a first gate insulating layer135, and a first capping pattern145may be in contact with the first element isolation structure180.

FIGS. 31 through 34are views for explaining steps of a method of manufacturing a semiconductor device according to embodiments.

Referring toFIG. 31, first fin patterns110and second fin patterns210aligned in the first direction X are formed. The first fin patterns110and the second fin patterns210are spaced apart from each other in the first direction X.

Pre-fins F1extending in the first direction X are formed. The pre-fins F1are spaced apart from the first fin patterns110and the second fin patterns210in the second direction Y.

Referring toFIG. 32, a pre-gate structure120G and a third gate structure320are formed on the first fin patterns110and the pre-fins F1.

Each of the pre-gate structure120G and the third gate structure320intersects the first fin patterns110and the pre-fins F1. The pre-gate structure120G overlaps ends of the first fin patterns110including short sides110bof the first fin patterns110. The third gate structure320does not overlap the ends of the first fin patterns110.

A second gate structure220and a fourth gate structure420are formed on the second fin patterns210and the pre-fins F1.

Each of the second gate structure220and the fourth gate structure420intersects the second fin patterns210and the pre-fins F1. The second gate structure220overlaps ends of the second fin patterns210including short sides210bof the second fin patterns210. The fourth gate structure420does not overlap the ends of the second fin patterns210.

In an example, the pre-gate structure120G may include a gate electrode formed by a replacement metal gate (RMG) process. In another example, the pre-gate structure120G may include a dummy mold gate prior to the RMG process.

In the method of manufacturing a semiconductor device according to the embodiments, the pre-gate structure120G is described as including the gate electrode formed by the RMG process.

The gate insulating support160may separate the pre-gate structure120G into a first gate structure120and a fifth gate structure120RG.

The first gate structure120intersects the first fin patterns110. The fifth gate structure120RG intersects the pre-fins F1.

Referring toFIG. 34, the fifth gate structure120RG and the pre-fins F1may be partially removed.

As a result of the partial removal of the pre-fins F1, the pre-fins F1may be separated into third fin patterns310and fourth fin patterns410.

A first element isolation structure180may be formed at a position from which the fifth gate structure120RG and the pre-fins F1have been removed.

The gate insulating structure160may contact the first element isolation structure180and the first gate structure120.