SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate, lower electrodes on the substrate, a dielectric layer covering the lower electrodes, and an upper electrode covering the dielectric layer. Each of the lower electrodes includes a first electrode layer having a cylindrical shape, a first insertion layer disposed on the first electrode layer and having a cylindrical shape, a second electrode layer disposed on the first insertion layer and extending to cover an upper end of the first electrode layer and an upper end of the first insertion layer. At least one of the first electrode layer and the second electrode layer has a first stress, and the first insertion layer has a second stress, different from the first stress. The first stress is one of tensile stress and compressive stress, and the second stress is the other of the tensile stress and the compressive stress.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims benefit of priority to Korean Patent Application No. 10-2022-0087756, filed on Jul. 15, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Example embodiments relate to semiconductor devices.

2. Description of the Related Art

With the demand for high integration and size reductions of semiconductor devices, a size of a data storage structure in a semiconductor device has been reduced. Accordingly, various studies have been conducted to structurally optimize a data storage structure for storing data in a dynamic random-access memory (DRAM).

SUMMARY

According to an example embodiment, a semiconductor device includes a substrate, a plurality of lower electrodes on the substrate, a dielectric layer covering the plurality of lower electrodes, and an upper electrode covering the dielectric layer. Each of the plurality of lower electrodes includes a first electrode layer having a cylindrical shape, a first insertion layer disposed on the first electrode layer and having a cylindrical shape, a second electrode layer disposed on the first insertion layer and extending to cover an upper end of the first electrode layer and an upper end of the first insertion layer. At least one of the first electrode layer and the second electrode layer has a first stress, and the first insertion layer has a second stress, different from the first stress. The first stress is one of tensile stress and compressive stress, and the second stress is the other thereof.

According to an example embodiment, a semiconductor device includes a substrate, a plurality of lower electrodes on the substrate, a dielectric layer covering the plurality of lower electrodes, and an upper electrode covering the dielectric layer. Each of the plurality of lower electrodes includes a first electrode layer, a second electrode layer on the first electrode layer, and an insertion layer disposed between the first electrode layer and the second electrode layer to be surrounded by the first electrode layer and the second electrode layer, having a cylindrical shape, and including a metal oxide.

According to an example embodiment, a semiconductor device includes an isolation layer defining active regions on a substrate, gate electrodes crossing the active regions and extending inwardly of the isolation layer, first impurity regions and second impurity regions disposed in the active regions on opposite sides adjacent to the gate electrodes, bit lines disposed on the gate electrodes and the active regions, and electrically connected to the first impurity regions, conductive patterns disposed on side surfaces of the bit lines and electrically connected to the second impurity regions, a plurality of lower electrodes extending vertically on the conductive patterns and electrically connected to each of the conductive patterns, at least one supporter layer contacting a side surface of each of the plurality of lower electrodes, a dielectric layer covering the plurality of lower electrodes and the at least one supporter layer, and an upper electrode covering the dielectric layer. Each of the plurality of lower electrodes includes a first electrode layer having a cylindrical shape, an insertion layer disposed on an internal surface of the first electrode layer, having a cylindrical shape, and including a metal oxide, and a second electrode layer disposed on an internal surface of the insertion layer and extending to cover an upper end of the first electrode layer and an upper end of the insertion layer.

DETAILED DESCRIPTION

FIG.1Ais a schematic layout diagram of a semiconductor device100according to example embodiments,FIG.1Bis a schematic perspective view of a semiconductor device100′ according to example embodiments, andFIG.1Cis a schematic layout diagram of the semiconductor device100′ according to example embodiments.

FIG.2is a schematic cross-sectional view of the semiconductor device100along lines I-I′ and ofFIG.1A.FIG.3Ais a schematic partially-enlarged view of the semiconductor device100according to example embodiments, andFIGS.3B and3Care schematic cross-sectional views of the semiconductor device100along lines and IV-IV′, respectively, ofFIG.3A. For ease of description, only main components of semiconductor devices are illustrated inFIGS.1A to1C,FIG.2, andFIGS.3A to3C.

Referring toFIGS.1A,2, and3A to3C, the semiconductor device100may include a substrate101with active regions ACT, isolation layers110defining the active regions ACT in the substrate101, a word line structure WLS buried in the substrate101and including a word line WL extending, e.g., lengthwise, in a first direction X, a bit line structure BLS extending, e.g., lengthwise, in a second direction Y to intersect the word line structure WLS on the substrate101and including a bit line BL, and a data storage structure CAP on the bit line structure BLS. The data storage structure CAP may store data, e.g., information, and may be, e.g., a capacitor structure of a DRAM. The semiconductor device100may further include a lower conductive pattern150on the active region ACT, an upper conductive pattern160on the lower conductive pattern150, and an insulating pattern165penetrating through the upper conductive pattern160.

The semiconductor device100may include, e.g., a cell array of a DRAM. For example, the bit line BL may be connected to a first impurity region105aof an active region ACT, and may be electrically connected to the data storage structure CAP on the upper conductive pattern160through the lower and upper conductive patterns150and160. The data storage structure CAP may include lower electrodes170, a dielectric layer180on the lower electrodes170, and an upper electrode190on the dielectric layer180. Each of the lower electrodes170may include a first electrode layer171, an insertion layer172, and a second electrode layer173. The data storage structure CAP may further include supporter layers SP1, SP2, and SP3.

The semiconductor device100may include a cell array region, in which a cell array is disposed, and a peripheral circuit region in which peripheral circuits for driving memory cells, disposed in the cell array, are disposed. The peripheral circuit region may be disposed around the cell array region.

The substrate101may include a semiconductor material, e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate101may further include impurities. The substrate101may be, e.g., a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

The active regions ACT may be defined in the substrate101by the isolation layers110. The active region ACT may have a bar shape, and may be disposed to have an island shape extending in the substrate101in one direction. The one direction may be a direction inclined with respect to a direction in which the word lines WL and the bit lines BL extend. The active regions ACT may be arranged to be parallel to each other, and an end portion of one active region ACT may be disposed to be adjacent to a center of another active region ACT adjacent to the one active region ACT.

The active region ACT may have first and second impurity regions105aand105bhaving a predetermined depth from an upper surface of the substrate101. The first and second impurity regions105aand105bmay be spaced apart from each other. The first and second impurity regions105aand105bmay serve as source/drain regions of a transistor formed by the word line WL. The source region and the drain region may be formed by the first and second impurity regions105aand105bformed by doping substantially the same impurities or implanting ions, and may be interchangeably referred to, depending on a circuit configuration of a finally formed transistor. The impurities may include impurities having a conductivity type opposite to a conductivity type of the substrate101. In example embodiments, depths of the first and second impurity regions105aand105bin the source region and the drain region may be different from each other.

The isolation layer110may be formed by a shallow trench isolation (STI) process. The isolation layer110may electrically isolate the active regions ACT from each other while surrounding the active regions ACT. The isolation layer110may be formed of an insulating material, e.g., a silicon oxide, a silicon nitride, or a combination thereof. The isolation layer110may include a plurality of regions having lower ends having different depths depending on a width of a trench formed by etching the substrate101.

The word line structures WLS may be disposed in gate trenches115extending within the substrate101. Each of the word line structures WLS may include a gate dielectric layer120, a word line WL, and a gate capping layer125. In the present specification, a “gate” may refer to a structure including the gate dielectric layer120and the word line WL, while the word line WL may be referred to as a “gate electrode,” and the word line structure WLS may be referred to as a “gate structure.”

The word line WL may be disposed to extend in the first direction X across the active region ACT. For example, a pair of adjacent word lines WL may be disposed to cross one active region ACT. The word line WL may constitute a gate of a buried channel array transistor (BCAT), but example embodiments are not limited thereto, e.g., the word lines WL may be disposed on the substrate101. The word line WL may be disposed below the gate trench115to have a predetermined thickness. An upper surface of the word line WL may be disposed at a level lower than a level of the upper surface of the substrate101. In the present specification, a high “level” and a low “level” may be defined based on a substantially planar lower surface of the substrate101.

The word line WL may be formed of a conductive material, e.g., at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). For example, the word line WL may include a lower pattern and an upper pattern formed of different materials. The lower pattern may include, e.g., at least one of tungsten (W), titanium (Ti), tantalum (Ta), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN), and the upper pattern may be a semiconductor pattern including polysilicon doped with P-type or N-type impurities.

The gate dielectric layer120may be disposed on a bottom surface and an internal surface of the gate trench115. The gate dielectric layer120may conformally cover the internal wall of the gate trench115. The gate dielectric layer120may include at least one of, e.g., a silicon oxide, a silicon nitride, and a silicon oxynitride. The gate dielectric layer120may be, e.g., a silicon oxide layer or an insulating layer having a high dielectric constant. In example embodiments, the gate dielectric layer120may be a layer formed by oxidizing the active region ACT or a layer formed by deposition.

The gate capping layer125may be disposed to fill the gate trench115on the word line WL. An upper surface of the gate capping layer125may be disposed at substantially the same level as the upper surface of the substrate101. The gate capping layer125may be formed of an insulating material, e.g., a silicon nitride.

The bit line structure BLS may extend in one direction, e.g., the second direction Y, perpendicular to the word line WL. The bit line structure BLS may include a bit line BL and a bit line capping pattern BC on the bit line BL.

The bit line BL may include a first conductive pattern141, a second conductive pattern142, and a third conductive pattern143stacked sequentially. The bit line capping pattern BC may be disposed on the third conductive pattern143. A buffer insulating layer128may be disposed between the first conductive pattern141and the substrate101, and a portion of the first conductive pattern141(hereinafter referred to as a “bit line contact pattern DC”) may contact the first impurity region105aof the active region ACT. The bit line BL may be electrically connected to the first impurity region105athrough the bit line contact pattern DC. A lower surface of the bit line contact pattern DC may be disposed at a level lower than a level of the upper surface of the substrate101, and may be disposed at a level higher than a level of an upper surface of the word line WL. In an example embodiment, the bit line contact pattern DC may be locally disposed in a bit line contact hole formed in the substrate101to expose the first impurity region105a.

The first conductive pattern141may include a semiconductor material, e.g., polycrystalline silicon. The first conductive pattern141may directly contact the first impurity region105a. The second conductive pattern142may include a metal-semiconductor compound. The metal-semiconductor compound may be, e.g., a layer formed by siliciding a portion of the first conductive pattern141. The metal-semiconductor compound may include, e.g., cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), and/or other metal silicides. The third conductive pattern143may include a metal material, e.g., titanium (Ti), tantalum (Ta), tungsten (W), and/or aluminum (Al). The number of conductive patterns constituting the bit line BL, the type of material thereof, and/or the stacking order thereof may vary according to example embodiments.

The bit line capping pattern BC may include a first capping pattern146, a second capping pattern147, and a third capping pattern148, sequentially stacked on the third conductive pattern143. Each of the first to third capping patterns146,147, and148may include an insulating material, e.g., a silicon nitride. The first to third capping patterns146,147, and148may be formed of different materials. Even when the first to third capping patterns146,147, and148are formed of the same material, boundaries therebetween may be distinct due to a difference in physical properties. A thickness of the second capping pattern147may be lower than a thickness of the first capping pattern146and lower than a thickness of the third capping pattern148. The number of capping patterns and/or the type of material constituting the bit line capping pattern BC may vary according to example embodiments.

Spacer structures SS may be disposed on opposite sidewalls of each of the bit line structures BLS to extend in one direction, e.g., the second direction Y. The spacer structures SS may be disposed between the bit line structure BLS and the lower conductive pattern150. The spacer structures SS may be disposed to extend along sidewalls of the bit line BL and sidewalls of the bit line capping pattern BC. A pair of spacer structures SS, disposed on opposite sides adjacent to a single bit line structure BLS, may be asymmetric with respect to the bit line structure BLS. Each of the spacer structures SS may include a plurality of spacer layers, and may further include an air spacer according to example embodiments.

The lower conductive pattern150may be connected to one region of the active region ACT, e.g., the second impurity region105b. The lower conductive pattern150may be disposed between the bit lines BL and between the word lines WL. The lower conductive pattern150may penetrate through the buffer insulating layer128to be connected to the second impurity region105bof the active region ACT. The lower conductive pattern150may directly contact the second impurity region105b. A lower surface of the lower conductive pattern150may be disposed at a level lower than a level of the upper surface of the substrate101, and may be disposed at a level higher than a level of the lower surface of the bit line contact pattern DC. The lower conductive pattern150may be insulated from the bit line contact pattern DC by the spacer structure SS. The lower conductive pattern150may be formed of a conductive material and may include at least one of, e.g., polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In example embodiments, the lower conductive pattern150may include a plurality of layers.

A metal-semiconductor compound layer155may be disposed between the lower conductive pattern150and the upper conductive pattern160. The metal-semiconductor compound layer155may be, e.g., a layer formed by siliciding a portion of the lower conductive pattern150when the lower conductive pattern150includes a semiconductor material. The metal-semiconductor compound layer155may include, e.g., cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), and/or other metal silicides. According to example embodiments, the metal-semiconductor compound layer155may be omitted.

The upper conductive pattern160may be disposed on the lower conductive pattern150. The upper conductive pattern160may extend between the spacer structures SS to cover the upper surface of the metal-semiconductor compound layer155. The upper conductive pattern160may include a barrier layer162and a conductive layer164. The barrier layer162may cover a lower surface and side surfaces of the conductive layer164. The barrier layer162may include a metal nitride, e.g., at least one of titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). The conductive layer164may include a conductive material, e.g., at least one of polycrystalline silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

The insulating patterns165may be disposed to penetrate through the upper conductive pattern160. The upper conductive pattern160may be divided into a plurality of upper conductive patterns160by the insulating patterns165. The insulating patterns165may include an insulating material, e.g., at least one of a silicon oxide, a silicon nitride, and a silicon oxynitride.

An etch-stop layer168may cover the insulating patterns165between the lower electrodes170. The etch-stop layer168may contact lower regions of side surfaces of the lower electrodes170. The etch-stop layer168may be disposed below the supporter layers SP1, SP2, and SP3. An upper surface of the etch-stop layer168may include a portion directly contacting the dielectric layer180. The etch-stop layer168may include at least one of, e.g., a silicon nitride and a silicon oxynitride.

The lower electrodes170may be disposed on the upper conductive patterns160. The lower electrodes170may penetrate through the etch-stop layer168to contact the upper conductive patterns160. The lower electrodes170may have a cylindrical shape, but example embodiments are not limited thereto, e.g., the lower electrodes170may have a hollow cylindrical shape. This will be described later with reference toFIG.4A.

Each of the lower electrodes170may include the first electrode layer171, the insertion layer172, and the second electrode layer173. The first electrode layer171may be disposed on the upper conductive patterns160. The first electrode layer171may have a cylindrical shape, e.g., a hollow cylindrical shape, and may have a first height H1. The first height H1 may refer to a height from a bottom surface (i.e., a lowermost end or surface) of the first electrode layer171to an uppermost end of the first electrode layer171. The first height H1 may be smaller than a height of the lower electrodes170. In example embodiments, the first electrode layer171may have a substantially uniform thickness, e.g., in the first direction X.

The insertion layer172may be disposed, e.g., conformally, on the first electrode layer171. The insertion layer172may be disposed, e.g., directly, between the first electrode layer171and the second electrode layer173. The insertion layer172may be surrounded by the first electrode layer171and the second electrode layer173. The insertion layer172may have a cylindrical shape, e.g., a hollow cylindrical shape having a U-shape or an inverted H-shape in a vertical cross-section. An external surface of the insertion layer172may, e.g., directly, contact an internal surface of the first electrode layer171, and an internal surface of the insertion layer172may, e.g., directly, contact an external surface of a first portion173_1of the second electrode layer173. In example embodiments, an upper end of the insertion layer172may be disposed at a substantially same level as an upper end of the first electrode layer171, e.g., uppermost surfaces of the insertion layer172and the first electrode layer171may be coplanar. However, the shape of the insertion layer172is not limited thereto, e.g., the upper end of the insertion layer172may be disposed at a level lower than a level of the upper end of the first electrode layer171.

The insertion layer172may have a second height H2. The second height H2 may refer to a height from a bottom surface (i.e., a lowermost end or surface) of the insertion layer172to an uppermost end of the insertion layer172. The second height H2 may be about 30% to about 90% of the first height H1, e.g., a difference between the first height H1 and the second height H2 may equal a thickness of the first electrode layer171. The insertion layer172may have a thickness d, e.g., in the first direction X. In example embodiments, the insertion layer172may have a substantially uniform thickness d. The thickness d of the insertion layer172may be greater than about 0 angstroms and less than about 10 angstroms, e.g., about 2 angstroms to about 4 angstroms. Since the insertion layer172has the second height H2 and a thickness d within the above-mentioned ranges, capacitance of the data storage structure CAP may be secured while preventing physical deformation of the lower electrode170. The second electrode layer173may fill an internal space defined by the insertion layer172, e.g., an internal space defined by the U-shape or the inverted H-shape, and may extend to cover upper ends, e.g., uppermost surfaces, of the first electrode layer171and the insertion layer172. An upper surface of the second electrode layer173may be disposed at a level higher than a level of the upper end of the first electrode layer171and a level of the upper end of the insertion layer172. The second electrode layer173may include a first portion173_1, filling the internal empty space defined by the insertion layer172, and a second portion173_2on the first portion173_1. The first portion173_1may contact an internal surface of the insertion layer172and may have a pillar shape, e.g., a linear shape in a vertical cross-section. The second portion173_2may extend, e.g., integrally and continuously, from the first portion173_1and may have a pillar shape covering, e.g., completely and continuously, the upper ends of the first electrode layer171and the insertion layer172. The second portion173_2may have a width (e.g., thickness) that is greater than a width of the first portion173_1, e.g., in the first direction X. A side surface of the second portion173_2may include a portion vertically aligned with a side surface of the first electrode layer171, e.g., lateral external sides of the second portion173_2and the first electrode layer171may be coplanar. In the present specification, the “first portion173_1” and the “second portion173_2” may be referred to as a “first pillar portion” and a “second pillar portion,” respectively.

As illustrated inFIG.3B, at a level of line ofFIG.3A, the lower electrode170may include the first portion173_1, the insertion layer172surrounding the external surface of the first portion173_1, and the first electrode layer171surrounding an external surface of the insertion layer172. For example, as illustrated inFIG.3B, the insertion layer172may have a circular shape in a top view, so the insertion layer172may continuously and directly contact the, e.g., entire, external surface of the first portion173_1and the, e.g., entire, internal surface of the first electrode layer171. For example, as illustrated inFIG.3B, the thickness of the insertion layer172may be smaller than the thickness of the first electrode layer171.

As illustrated inFIG.3C, at a level of line IV-IV′ ofFIG.3A, the lower electrode170may include the second portion173_2. For example, the second portion173_2may directly contact the third supporter layer SP3.

The insertion layer172may be disposed between the first electrode layer171and the second electrode layer173, and may be surrounded by the first electrode layer171and the second electrode layer173. An external surface of the insertion layer172may contact the first electrode layer171, and an internal surface of the insertion layer172may contact the second electrode layer173. An uppermost end of the insertion layer172may contact the second electrode layer173. The insertion layer172may be surrounded by the first electrode layer171and the second electrode layer173in all directions. The insertion layer172has a structure surrounded, e.g., completely enclosed, by the first electrode layer171and the second electrode layer173, so that damage to the insertion layer172may be prevented. In example embodiments, the first electrode layer171and the second electrode layer173may prevent a mold etchant (e.g., hydrogen fluoride (HF)), used in the process of forming the upper electrode190, from permeating into the insertion layer172to prevent damage to the insertion layer172.

The insertion layer172may include a material different from a material of the first electrode layer171and the second electrode layer173. The insertion layer172may include a material having stress in a direction different from a direction of stress of the material included in the first electrode layer171and the second electrode layer173. In example embodiments, at least one of the first electrode layer171and the second electrode layer173may have, e.g., exhibit, one of compressive stress and tensile stress. The insertion layer172may have the other of the compressive stress and the tensile stress. For example, the first electrode layer171and the second electrode layer173may have tensile stress, and the insertion layer172may have compressive stress. In exemplary embodiments, the first electrode layer171and the second electrode layer173may include a conductive material having tensile stress, e.g., at least one of polycrystalline silicon (Si), TiN, NbN, WN, VN, MoN, TaN, TiSiN, and TiCN. The first electrode layer171and the second electrode layer173may include the same material or different materials. The insertion layer172may include a metal oxide having compressive stress. The insertion layer172may include at least one of, e.g., TiO, NbO, MoO, TaO, and TiON.

The insertion layer172may have a stress in a direction opposite to the direction of the stress of the first electrode layer171and the second electrode layer173, in order to offset the overall stress of the lower electrodes170. Accordingly, physical deformation of the lower electrodes170, e.g., caused by the stress of the first electrode layer171and the second electrode layer173(e.g., collapse and bending of the lower electrodes170) may be prevented.

One or more supporter layers SP1, SP2, and SP3 may be provided between adjacent lower electrodes170to support the lower electrodes170. For example, a first supporter layer SP1, a second supporter layer SP2, and a third supporter layer SP3 may be provided between the adjacent lower electrodes170to contact the lower electrodes170.

Referring toFIG.1A, in a plan view viewed from above, the lower electrodes170may have a regular arrangement. For example, the lower electrodes170may be disposed to be spaced apart by a predetermined distance in the first direction X and disposed in a zigzag pattern in the second direction Y.

A through-hole pattern may be disposed between the plurality of adjacent lower electrodes170. In example embodiments, as illustrated in the semiconductor device100ofFIG.1A, a single through-hole pattern may be disposed between four adjacent lower electrodes170. However, the through-hole pattern is not limited thereto. In other embodiments, as illustrated in a semiconductor device100′ ofFIGS.1B and1C, a single through-hole pattern may be disposed between three adjacent lower electrodes170.

The supporter layers SP1, SP2, and SP3 may include the first supporter layer SP1, the second supporter layer SP2 on the first supporter layer SP1, and the third supporter layer SP3 on the second supporter layer SP2. The supporter layers SP1, SP2, and SP3 may be disposed to be spaced apart from the substrate101in a direction perpendicular to the upper surface of the substrate101, e.g., in a third direction Z. The supporter layers SP1, SP2, and SP3 may contact the lower electrodes170and extend in a direction parallel to the upper surface of the substrate101.

The first supporter layer SP1 and the second supporter layer SP2 may contact the first electrode layer171, and may be spaced apart from the second electrode layer173. The third supporter layer SP3 may contact the second portion173_2of the second electrode layer173. The supporter layers SP1, SP2, and SP3 may include a portion directly contacting the lower electrodes170and the dielectric layer180. For example, as illustrated inFIG.2, the third supporter layer SP3 may have a thickness higher than a thickness of each of the first supporter layer SP1 and the second supporter layer SP2, e.g., in the third direction Z. The supporter layers SP1, SP2, and SP3 may be layers supporting the lower electrodes170having a high aspect ratio. Each of the supporter layers SP1, SP2, and SP3 may include, e.g., at least one of a silicon nitride and a silicon oxynitride, or a material similar thereto. The number, thickness, and/or dispositional relationship of the supporter layers SP1, SP2, and SP3 may be adjusted according to example embodiments.

The dielectric layer180may cover the lower electrodes170on surfaces of the lower electrodes170. The dielectric layer180may be disposed between the lower electrodes170and the upper electrode190. The dielectric layer180may cover upper and lower surfaces of the supporter layers SP1, SP2, and SP3. The dielectric layer180may cover an upper surface of the etch-stop layer168.

The dielectric layer180may include, e.g., a high-κ dielectric material, a silicon oxide, a silicon nitride, or a combination thereof. However, in some embodiments, the dielectric layer180may be an oxide, a nitride, a silicide, an oxynitride, or silicide oxynitride including one of hafnium (Hf), aluminum (Al), zirconium (Zr), and lanthanum (La).

The upper electrode190may cover the plurality of lower electrodes170, the supporter layers SP1, SP2, and SP3, and the dielectric layer180. The upper electrode190may fill a space between the plurality of lower electrodes170and a space between the supporter layers SP1, SP2, and SP3. The upper electrode190may directly contact the dielectric layer180.

For example, the upper electrode190may include a single electrode layer, as illustrated inFIG.2. In other examples, the upper electrode190may include a plurality of electrode layers. The upper electrode190may include a conductive material. The upper electrode190may include at least one of, e.g., polycrystalline silicon (Si), TiN, NbN, WN, VN, MoN, TaN, TiSiN, and TiCN.

Semiconductor devices according to example embodiments will be described with reference toFIGS.4A to4C,5A to5C, and6A to6C. The semiconductor devices illustrated inFIGS.4A to4C,5A to5C, and6A to6Care different from the semiconductor device according to the previous embodiment ofFIGS.1A to3C, in terms of a structure of lower electrodes.

In the embodiments ofFIGS.4A to4C,5A to5C, and6A to6C, when components have the same reference numerals as those ofFIGS.1A to3Cbut have alphabetic characters, it is to describe an example embodiment, different from the example embodiment ofFIGS.1A to3C. Features described with the same reference numerals are the same or similar.

FIG.4Ais a schematic partially-enlarged view of a region of a data storage structure of a semiconductor device according to example embodiments, andFIGS.4B and4Care schematic cross-sectional views of a data storage structure of a semiconductor device according to example embodiments.FIGS.4B and4Cillustrate cross-sections taken along lines V-V and VI-VI′ ofFIG.4A.

Referring toFIGS.4A to4C, lower electrodes170amay each have a cylindrical shape.

Each of the lower electrodes170amay include a first electrode layer171a, an insertion layer172a, and a second electrode layer173a. The first electrode layer171amay have a cylindrical shape. The insertion layer172amay have a cylindrical shape and may be disposed on an internal surface of the first electrode layer171a. The second electrode layer173amay include a first portion173a_1, disposed on the insertion layer172a, and a second portion173a_2extending from the first portion173a_1. For example, as illustrated inFIG.4A, the first portion173a_1of the second electrode layer173amay have a cylindrical shape, e.g., may be conformal on an inner surface of the insertion layer172a, and the second portion173a_2may cover upper ends of the first electrode layer171aand the insertion layer172a, e.g., the second portion173a_2may extend horizontally above uppermost surfaces of the first electrode layer171aand the insertion layer172a. In the present specification, the “first portion173a_1” and the “second portion173a_2” may be referred to as a cylindrical portion and an extending portion, respectively.

The dielectric layer180amay cover the second electrode layer173a, e.g., the dielectric layer180amay continuously extend along an inner surface of the first portion173a_1of the second electrode layer173a. The dielectric layer180amay, e.g., directly, contact both the first portion173a_1and the second portion173a_2of the second electrode layer173a. An upper electrode190amay cover the dielectric layer180a. The upper electrode190amay include a portion filling an internal space defined by the first portion173a_1of the second electrode layer173a.

Referring toFIG.4B, at a level of line V-V ofFIG.4A, the data storage structure may include the upper electrode190a, the dielectric layer180asurrounding an external surface of the upper electrode190a, the first portion173a_1of the second electrode layer173asurrounding an external surface of the dielectric layer180a, the insertion layer172asurrounding an external surface of the first portion173a_1of the second electrode layer173a, and the first electrode layer171asurrounding an external surface of the insertion layer172a. Referring toFIG.4C, at a level of line VI-VI′ ofFIG.4A, the data storage structure may include the upper electrode190a, the dielectric layer180asurrounding an external surface of the upper electrode190a, and the second portion173a_2of the second electrode layer173asurrounding an external surface of the dielectric layer180a.

Referring toFIGS.5A to5C, the lower electrode170bmay further include a second insertion layer174and a third electrode layer175. For example, the second insertion layer174and the third electrode layer175may be inserted between the dielectric layer180and the first electrode layer171b.

In detail, the lower electrode170bmay include the third electrode layer175disposed on the upper conductive patterns (160ofFIG.2), the second insertion layer174disposed on the third electrode layer175, a first electrode layer171bdisposed on the second insertion layer174, the first insertion layer172disposed on the first electrode layer171b, and the second electrode layer173disposed on the first insertion layer172. The first insertion layer172may be disposed between the first electrode layer171band the second electrode layer173. The second insertion layer174may be disposed between the third electrode layer175and the first electrode layer171b. The first insertion layer172and the second insertion layer174may be spaced apart from each other. An external side surface of the second portion173_2of the second electrode layer173may include a portion vertically aligned with an external side surface of the third electrode layer175.

Each of the third electrode layer175, the second insertion layer174, the first electrode layer171b, and the first insertion layer172may have a cylindrical shape. The second electrode layer173may include the first portion173_1, filling an empty space defined by the first insertion layer172, and the second portion173_2extending from the first portion173_1. The second portion173_2may cover an upper end of the first insertion layer172, an upper end of the first electrode layer171b, an upper end of the second insertion layer174, and an upper end of the third electrode layer175. For example, as illustrated inFIG.5A, each of the first portion173_1and the second portion173_2of the second electrode layer173may have a pillar shape. In another example, the first portion173_1of the second electrode layer173may have a cylindrical shape, and the second portion173_2of the second electrode layer173may have a shape extending from the first portion173_1to cover the upper ends of the first electrode layer171b, the second insertion layer174, and the third electrode layer175.

The first electrode layer171b, the second electrode layer173, and the third electrode layer175may have stress in a direction different from a direction of stress of the first and second insertion layers172and174. In example embodiments, the first electrode layer171b, the second electrode layer173, and the third electrode layer175may be formed of a conductive material having tensile stress, and the first insertion layer172and the second insertion layer174may be formed of a metal oxide having compressive stress. The first electrode layer171b, the second electrode layer173, and the third electrode layer175may include the same material or different materials. The first insertion layer172and the second insertion layer174may include the same material or different materials.

Referring toFIG.5B, at a level of line VII-VII′ ofFIG.5A, the lower electrode170bmay include the first portion173_1of the second electrode layer173, the first insertion layer172surrounding an external surface of the first portion173_1, the first electrode layer171bsurrounding an external surface of the first insertion layer172, the second insertion layer174surrounding an external surface of the first electrode layer171b, and the third electrode layer175surrounding an external surface of the second insertion layer174. Referring toFIG.5C, at a level of line VIII-VIII′ ofFIG.5A, the lower electrode170bmay include the second portion173_2.

Referring toFIGS.6A to6C, the insertion layer172cof the lower electrode170cmay include a plurality of material layers. For example, the insertion layer172cmay include a first material layer172c_1and a second material layer172c_2.

An external surface of the first material layer172c_1may contact an internal surface of the first electrode layer171, and an internal surface of the first material layer172c_1may contact an external surface of the second material layer172c_2. An external surface of the second material layer172c_2may contact an internal surface of the first material layer172c_1, and an internal surface of the second material layer172c_2may contact an external surface of the second electrode layer173. The first material layer172c_1and the second material layer172c_2may have stress in a direction different from a direction of stress of the first electrode layer171and the second electrode layer173. In example embodiments, when the first electrode layer171and the second electrode layer173have tensile stress, the first material layer172c_1and the second material layer172c_2may have compressive stress. The first material layer172c_1and the second material layer172c_2may include the same material or different materials.

Referring toFIG.6B, at a level of line IX-IX′ ofFIG.6A, the lower electrode170cmay include the first portion173_1of the second electrode layer173, the second material layer172c_2surrounding an external surface of the first portion173_1of the second electrode layer173, the first material layer172c_1surrounding an external surface of the second material layer172c_2, and the first electrode layer171surrounding an external surface of the first material layer172c_1. Referring toFIG.6C, at a level of line X-X′ ofFIG.6A, the lower electrode170cmay include the second portion173_2.

FIGS.7to12are cross-sectional views illustrating stages in a method of fabricating a semiconductor device according to example embodiments.FIGS.7to12illustrate cross-sections corresponding to lines I-I′ and ofFIG.2.

Referring toFIG.7, the isolation layer110may be formed in the substrate101to define the active region ACT. An isolation trench may be formed in the substrate101, and the isolation layer110may fill the isolation trench. In a plan view, the active region ACT may have an elongated bar shape extending in a direction oblique to a direction in which the word line WL extends. An ion implantation process may be performed using the isolation layer110as an ion implantation mask to form impurity regions on the active region ACT. The active region ACT and the isolation layer110may be patterned to form the gate trench115. A pair of gate trenches115may cross the active region ACT. The impurity regions may also be separated by the gate trench115to form the first impurity region105aand the second impurity region105b.

The gate dielectric layer120may be formed on an internal surface of the gate trench115to have a substantially conformal thickness. Then, the word line WL may be formed to fill at least a portion of the gate trench115. An upper surface of the word line WL may be recessed to be lower than an upper surface of the active region ACT. An insulating layer may be stacked on the substrate101to fill the gate trench115, and may then be etched to form the gate capping layer125on the word line WL.

An insulating layer and a conductive layer may be sequentially formed and patterned on an entire surface of the substrate101to form the buffer insulating layer128and the first conductive pattern141stacked sequentially. The buffer insulating layer128may be formed of at least one of a silicon oxide, a silicon nitride, and a silicon oxynitride. The buffer insulating layer128may include a plurality of buffer insulating layers128formed to be spaced apart from each other. The first conductive pattern141may have a shape corresponding to a planar shape of the buffer insulating layer128. The buffer insulating layer128may be formed to simultaneously cover the end portions of two adjacent active regions ACT, e.g., adjacent second impurity regions105b. Upper portions of the isolation layer110, the substrate101, and the gate capping layer125may be etched using the buffer insulating layer128and the first conductive pattern141as etching masks to form a bit line contact hole. The bit line contact hole may expose the first impurity region105a.

The bit line contact pattern DC may be formed to fill the bit line contact hole. The formation of the bit line contact pattern DC may include forming a conductive layer to fill the bit line contact hole and performing a planarization process. For example, the bit line contact pattern DC may be formed of polysilicon. The second conductive pattern142, the third conductive pattern143, and the first to third capping patterns146,147, and148may be sequentially formed on the first conductive pattern141, and the first to third conductive patterns141,142, and143may be sequentially etched using the three capping patterns146,147, and148as etch masks. As a result, the bit line structure BLS including the bit line BL including the first to third conductive patterns141,142, and143and the bit line capping pattern BC including the first to third capping patterns146,147, and148may be formed.

Spacer structures SS may be formed on side surfaces of the bit line structure BLS. The spacer structure SS may include a plurality of layers. Fence insulating patterns154may be formed between the spacer structures SS. The fence insulating patterns154may include a silicon nitride or a silicon oxynitride. An anisotropic etching process may be performed using the fence insulating patterns154and the third capping pattern148as etching masks to form opening exposing the second impurity region105b.

The lower conductive pattern150may be formed below the opening. The lower conductive pattern150may be formed of a semiconductor material, e.g., polysilicon. For example, the lower conductive pattern150may be formed by forming a polysilicon layer to fill the opening and then performing an etch-back process.

The metal-semiconductor compound layer155may be formed on the lower conductive pattern150. The formation of the metal-semiconductor compound layer155may include a metal layer deposition process and a heat treatment process.

The upper conductive pattern160may be formed on an upper portion of the opening. The formation of the upper conductive pattern160may include sequentially forming the barrier layer162and the conductive layer164. Then, a patterning process may be performed on the barrier layer162and the conductive layer164to form the insulating patterns165penetrating therethrough. Accordingly, a lower structure including the substrate101, the word line structure WLS, and the bit line structure BLS may be formed.

The etch-stop layer168may be conformally formed on a lower structure, and mold layers118and preliminary supporter layers SP1′, SP2′, and SP3′ may be alternately stacked on the etch-stop layer168. The mold layers118and the preliminary supporter layers SP1′, SP2′, and SP3′ may constitute a stack structure ST. The etch-stop layer168may include an insulating material, having etch selectivity with respect to the mold layers118under specific etch conditions, e.g., at least one of a silicon oxide, a silicon nitride, a silicon carbide, a silicon oxycarbide, and a silicon carbonitride. The mold layers118may be formed of a silicon oxide, and the preliminary supporter layers SP1′, SP2′, and SP3′ may be formed of a silicon nitride.

Referring toFIG.8, a plurality of holes H1 may be formed to penetrate through the mold layers118and the preliminary supporter layers SP1′, SP2′, and SP3′. In the operation of forming the plurality of holes H1, the etch-stop layer168may serve as a stopper stopping the etching process. The plurality of holes H1 may penetrate through the etch-stop layer168to expose the upper conductive patterns160. The plurality of holes H1 may be regions, in which the lower electrodes170are to be formed, and may be formed to be spaced apart from each other by a predetermined distance and to be arranged at regular intervals.

Referring toFIG.9, a first preliminary electrode layer171L and a preliminary insertion layer172L may be formed in the plurality of holes H1.

The first preliminary electrode layer171L may be formed, e.g., conformally, along a surface of the stack structure ST and upper surfaces of the upper conductive patterns160exposed by the plurality of holes H1. The first preliminary electrode layer171L may be formed of a conductive material. The first preliminary electrode layer171L may be formed of at least one of, e.g., polycrystalline silicon (Si), TiN, NbN, WN, VN, MoN, TaN, TiSiN, and TiCN. In example embodiments, the process of forming the first preliminary electrode layer171L may be performed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD).

The preliminary insertion layer172L may be formed, e.g., conformally, on the first preliminary electrode layer171L. The preliminary insertion layer172L may be formed of a material having stress in a direction opposite to a direction of stress of the first preliminary electrode layer171L. In example embodiments, when the first preliminary electrode layer171L is formed of a material having tensile stress, the preliminary insertion layer172L may be formed of a material having compressive stress. For example, the preliminary insertion layer172L may be formed of a metal oxide, e.g., at least one of TiO, NbO, MoO, TaO, and TiON. In example embodiments, the process of forming the preliminary insertion layer172L may be performed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). However, the process of forming the preliminary insertion layer172L is not limited thereto, e.g., the preliminary insertion layer172L may be formed by oxidizing the surface of the first preliminary electrode layer171L. In this case, the preliminary insertion layer172L may include a material forming the first preliminary electrode layer171L.

Referring toFIG.10, the first electrode layer171and the insertion layer172may be formed in the plurality of holes H1. The first electrode layer171and the insertion layer172may be formed by etching a portion of the first preliminary electrode layer (171L ofFIG.9) and the preliminary insertion layer (172L ofFIG.9).

The first electrode layer171and the insertion layer172may be etched to have upper ends disposed at a level lower than a level of an upper surface of the stack structure ST. Each of the first electrode layer171and the insertion layer172may have a cylindrical shape. For example, the upper end of the first electrode layer171may be disposed at a substantially same level as the upper end of the insertion layer172. In another example, the insertion layer172may be etched to have an upper end disposed at a level lower than a level of the upper end of the first electrode layer171.

Referring toFIG.11, a second preliminary electrode layer173L may be formed to cover the first electrode layer171, the insertion layer172, and the stack structure ST. The second preliminary electrode layer173L may be formed to, e.g., completely, fill the plurality of holes H1 including an empty space defined by the cylindrical shape of the insertion layer172and to cover the upper surface of the stack structure ST.

The second preliminary electrode layer173L may cover upper ends of the first electrode layer171and the insertion layer172. The second preliminary electrode layer173L may be formed of a conductive material. The second preliminary electrode layer173L may be formed of at least one of, e.g., polycrystalline silicon (Si), TiN, NbN, WN, VN, MoN, TaN, TiSiN, and TiCN. In example embodiments, the process of forming the second preliminary electrode layer173L may be performed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). The second preliminary electrode layer173L may include the same material as the first electrode layer171or a material different from a material of the first electrode layer171.

Referring toFIG.12, the second electrode layer173may be formed, and the mold layers118may be removed. A portion of the second preliminary electrode layer (173L ofFIG.11) may be etched to form the second electrode layer173including the first portion173_1and the second portion173_2.

Accordingly, lower electrodes170including the first electrode layer171, the insertion layer172, and the second electrode layer173may be formed. In example embodiments, the second electrode layer173may be etched to have an upper surface disposed at a same level as an upper surface of the third supporter layer SP3, an uppermost supporter layer. However, the shape of the second electrode layer173is not limited thereto, e.g., the upper surface of the second electrode layer173may be disposed at a level lower than a level of the upper surface of the third supporter layer SP3.

Then, an additional mask may be formed on the second preliminary electrode layer (173L ofFIG.11), and at least a portion of the mold layers (118ofFIG.11) and the preliminary supporter layers (SP1′, SP2′, SP3′ ofFIG.11) may be removed using the mask. Accordingly, the preliminary supporter layers SP1′, SP2′, and SP3′ ofFIG.11may form the first to third supporter layers SP1, SP2, and SP3. The first to third supporter layers SP1, SP2, and SP3 may be patterned according to a structure of the mask to have a shape including a plurality of openings. The plurality of openings may be disposed between four adjacent lower electrodes170, as illustrated inFIG.1A, or may be disposed between three adjacent lower electrodes170, as illustrated inFIGS.1B and1C. The first to third supporter layers SP1, SP2, and SP3 may connect the adjacent lower electrodes170to each other. The mold layers118may be selectively removed with respect to the supporter layers SP1, SP2, and SP3. In example embodiments, the process of removing the mold layers118may be performed by a wet etching process using an etchant (e.g., a hydrogen fluoride (HF) solution). The mask may be removed after etching the mold layers118or while etching the mold layers118. An empty space H2 may be formed in a region in which the mold layers118are removed.

Returning toFIGS.1A,2and3A to3C, the dielectric layer180may be formed to cover the lower electrodes170, and the upper electrode190may be formed to cover the dielectric layer180. Each of the process of forming the dielectric layer180and the upper electrode190may be performed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). Accordingly, the data storage structure CAP including the lower electrodes170, the dielectric layer180, and the upper electrode190may be formed, and thus the semiconductor device100including the data storage structure CAP may be fabricated.

By way of summation and review, example embodiments provide a semiconductor device having improved electrical characteristics and reliability. That is, as described above, a semiconductor device according to example embodiments may include a data storage structure including a lower electrode in which an insertion layer is interposed between electrode layers. Accordingly, physical deformation of the lower electrode may be prevented.