DISPLAY APPARATUS

A display apparatus includes: a first connection electrode layer on a substrate and comprising a horizontal connection line extending in a first direction; and a second connection electrode layer on the first connection electrode layer, comprising a vertical connection line extending in a second direction crossing the first direction and a driving voltage line extending in the second direction, the driving voltage line comprising a protrusion overlapping the horizontal connection line.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to and the benefit of Korean Patent Application No. 10-2022-0129752, filed on Oct. 11, 2022, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

Aspects of one or more embodiments relate to a display apparatus.

2. Description of the Related Art

Generally, in a display apparatus such as an organic light-emitting display apparatus, thin-film transistors are respectively arranged in (sub-)pixels to control the brightness, etc. of the (sub-)pixels. Such thin-film transistors control the brightness, etc. of their corresponding (sub-)pixels according to transmitted data signals or the like.

The data signals are transmitted to respective (sub-)pixels through data lines from a driver located in a peripheral area on an outer side of a display area.

SUMMARY

Aspects of one or more embodiments relate to a display apparatus, and for example, to a display apparatus capable of displaying high-quality images.

In a display apparatus, when an area of a region where a driver, etc. are arranged is large or when the area is reduced, the quality of images displayed in a display area may degrade.

Aspects of some embodiments include a display apparatus that may address the above-described issues, and may be capable of displaying relatively high-quality images. However, this is merely an example, and the scope of embodiments according to the present disclosure is not limited thereto.

According to one or more embodiments, a display apparatus includes a first connection electrode layer on a substrate and including a horizontal connection line extending in a first direction, a second connection electrode layer on the first connection electrode layer, including a vertical connection line extending in a second direction crossing the first direction and a driving voltage line extending in the second direction, the driving voltage line including a protrusion overlapping the horizontal connection line.

According to some embodiments, the driving voltage line may include a first driving voltage branch extending in the second direction, a second driving voltage branch extending in the second direction and arranged apart from the first driving voltage branch in the first direction, and a driving voltage body connected to the first driving voltage branch and the second driving voltage branch.

According to some embodiments, the protrusion may protrude from the driving voltage body in the second direction to be arranged between the first driving voltage branch and the second driving voltage branch.

According to some embodiments, the protrusion may include a first protrusion which has one end connected to the driving voltage body and extends in the second direction and a second protrusion connected to the other end of the first protrusion and extending in the first direction.

According to some embodiments, the second protrusion may overlap the horizontal connection line.

According to some embodiments, the driving voltage line may include a plurality of driving voltage bodies arranged in the second direction, a plurality of first driving voltage branches extending in the second direction and arranged between the plurality of driving voltage bodies to connect the plurality of driving voltage bodies to each other, and a plurality of second driving voltage branches arranged apart from the plurality of first driving voltage branches in the first direction, wherein each of the plurality of second driving voltage branches has an end connected to a corresponding one of the plurality of driving voltage bodies.

Another end of each of the plurality of second driving voltage branches may be spaced apart from the plurality of driving voltage bodies.

According to some embodiments, the second connection electrode layer may further include connection electrodes arranged apart from the driving voltage line, each of the connection electrodes including a portion arranged between the another end of a corresponding one of the plurality of second driving voltage branches and a corresponding one of the plurality of driving voltage bodies.

According to some embodiments, the display apparatus may further include pixel electrodes on the second connection electrode layer, each of the pixel electrodes being electrically connected to a corresponding one of the connection electrodes through a contact hole.

According to one or more embodiments, a display apparatus includes a first semiconductor layer on a substrate, a first gate layer on the first semiconductor layer and including a driving gate electrode, a second gate layer on the first gate layer and including an initialization gate line extending in a first direction, a second semiconductor layer on the second gate layer and including a 2nd-1stsemiconductor layer extending in a second direction crossing the first direction and a semiconductor extension layer extending from the 2nd-1stsemiconductor layer in the first direction, a first connection electrode layer on the second semiconductor layer and including a horizontal connection line extending in the first direction and comprising a portion overlapping the semiconductor extension layer, and a second connection electrode layer on the first connection electrode layer and including a vertical connection line extending in the second direction and a driving voltage line extending in the second direction.

According to some embodiments, the first gate layer may further include an initialization voltage line extending in the first direction, and the semiconductor extension layer is electrically connected to the initialization voltage line.

According to some embodiments, the first connection electrode layer may further include a connection electrode connected to the initialization voltage line and the semiconductor extension layer through contact holes.

According to some embodiments, the 2nd-1stsemiconductor layer and the semiconductor extension layer may be integrally formed as a single body and include oxide semiconductor materials.

According to some embodiments, the second semiconductor layer may further include a 2nd-2ndsemiconductor layer extending in the second direction, an end of the semiconductor extension layer may be connected to the 2nd-1stsemiconductor layer, and the other end of the semiconductor extension layer may be connected to the 2nd-2ndsemiconductor layer.

According to some embodiments, a portion of the horizontal connection line, which overlaps the semiconductor extension layer, may be located in the semiconductor extension layer, when viewed in a direction perpendicular to the substrate.

According to one or more embodiments, a display apparatus includes a first semiconductor layer on a substrate, a first gate layer on the first semiconductor layer and including a driving gate electrode and a bias gate line extending in a first direction, a second gate layer on the first gate layer and including an initialization gate line extending in the first direction, a third gate layer on the second gate layer and including a bias voltage line extending in the first direction and overlapping the bias gate line, a first connection electrode layer on the third gate layer and including a horizontal connection line extending in the first direction, and a second connection electrode layer on the first connection electrode layer and including a vertical connection line extending in a second direction and a driving voltage line extending in the second direction.

According to some embodiments, the first connection electrode layer may further include a connection electrode connected to the bias voltage line and the first semiconductor layer through contact holes.

Other aspects, features, and characteristics other than those described above will become more apparent from the following detailed description, claims and drawings for carrying out the disclosure.

DETAILED DESCRIPTION

As the disclosure allows for various changes and numerous embodiments, particular embodiments will be shown in the drawings and described in detail in the written description. The attached drawings for illustrating preferred embodiments of the present disclosure are referred to in order to gain a sufficient understanding of the present disclosure, the merits thereof, and the objectives accomplished by the implementation of the present disclosure. The disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.

Hereinafter, one or more embodiments of the disclosure will be described in more detail with reference to the accompanying drawings. Like elements in the drawings denote like elements, and repeated descriptions thereof are omitted.

It will be understood that when a component, such as a layer, a film, a region, or a plate, is referred to as being “on” another component, the component can be directly on the other component or intervening components may be present thereon. Sizes of components in the drawings may be exaggerated for convenience of explanation. In other words, since sizes and thicknesses of elements in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

FIG.1is a schematic plan view of a portion of a display apparatus according to some embodiments. As shown inFIG.1, the display apparatus includes a display panel10. The display apparatus including the display panel10may be any type of display apparatus. For example, the display apparatus may be various products such as a smartphone, a tablet computer, a laptop, a television, or a billboard.

The display panel10includes a display area DA and a peripheral area PA at outside (e.g., in a periphery) of the display area DA. The display area DA is an area where images are displayed, and a plurality of pixels may be arranged therein. When viewed in a direction substantially perpendicular or normal to the display panel10(e.g., in a plan view), the display area DA may have various shapes such as a circle, an oval, a polygon, and other specific shapes.FIG.1shows that the shape of the display area DA is substantially a rectangle with rounded edges, but embodiments according to the present disclosure are not limited thereto.

The peripheral area PA may be located over the outer side of the display area DA. The peripheral area PA may include a first peripheral area PA1surrounding at least a portion of an edge portion of the display area DA (in a −y direction and a −x direction), and a second peripheral area PA2arranged on a side of the outer side of the display area DA (in the −y direction). The second peripheral area PA2may be adjacent to the first peripheral area PA1. That is, the second peripheral area PA2may be located relatively in a center direction of the display panel10with respect to the first peripheral area PA1. A width of the second peripheral area PA2(in an x-axis direction) may be less than a width of the display area DA (in the x-axis direction). As described below based on the above structure, at least a portion of the second peripheral area PA2may be easily bent.

Because the display panel10includes a substrate, it may be described that a substrate100includes the display area DA and the peripheral area PA described above. Hereinafter, for convenience, it is described that the substrate100includes the display area DA and the peripheral area PA.

The display panel10may be bent with respect to a bending axis (in the x-axis direction) in at least a portion of the second peripheral area PA2. When the display panel10is bent, a portion of the second peripheral area PA2may overlap the display area DA when viewed in a z-axis direction. Embodiments according to the present disclosure are not limited to a display apparatus that is bent and may also be applied to a display apparatus that is not bent. The second peripheral area PA2may be a non-display area. Because the display panel10is bent as described above, when the display apparatus is viewed from a front surface (in a −z direction) thereof, a viewed area of the non-display area may decrease even though the non-display area is viewed.

A driving chip20may be arranged in the second peripheral area PA2of the display panel10. The driving chip20may include an integrated circuit for driving the display panel10. Such an integrated circuit may be a data driving integrated circuit for generating a data signal, but one or more embodiments are not limited thereto.

The driving chip20may be mounted in the second peripheral area PA2of the display panel10. Although the driving chip20is mounted on the same surface as a display surface of the display area DA, because the display panel10is bent in the second peripheral area PA2as described above, the driving chip20may be located on a rear surface of the display area DA.

A printed circuit board30, etc. may be attached to an end of the second peripheral area PA2of the display panel10. The printed circuit board30, etc. may be electrically connected to the driving chip20, etc. through a pad on the substrate100.

Hereinafter, an organic light-emitting display apparatus is described as an example of the display apparatus, but the display apparatus is not limited thereto. As another example, the display apparatus may be a display apparatus such as an inorganic light-emitting display apparatus, an inorganic EL display apparatus, or a quantum dot light-emitting display apparatus. For example, an emission layer of a display element of the display apparatus may include an organic material or an inorganic material. Also, the display apparatus may include an emission layer and quantum dots arranged in a path of light emitted from the emission layer.

As described above, the display panel10may include the substrate100. Various components included in the display panel10may be located over the substrate100. The substrate100may include a glass material, metals, or polymer resin. As described above, when the display panel10is bent in the second peripheral area PA2, the substrate100needs to be flexible or bendable. In this case, the substrate100may include polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Various modifications may be made to the substrate100, and for example, the substrate100may have a multilayered structure that includes two layers including the above polymer resin and a barrier layer including an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, or the like) and arranged between the layers.

In the display area DA, pixels PX are arranged. Each of the pixels PX may be a sub-pixel and include a display element such as an organic light-emitting diode OLED and a pixel circuit electrically connected to the display element. The pixel PX may emit, for example, red light, green light, blue light, or white light. The pixels PX may be electrically connected to outer circuits arranged in the peripheral area PA. In the peripheral area PA, a first scan driving circuit11, a second scan driving circuit12, an emission control driving circuit13, a terminal14, a driving voltage supply line15, and a common voltage supply line16are arranged.

The first scan driving circuit11may provide a scan signal to the pixel PX through a scan line SL. The second scan driving circuit12may be arranged side by side with the first scan driving circuit11with the display area DA therebetween. Some of the pixels PX arranged in the display area DA may be electrically connected to the first scan driving circuit11, and the others of the pixels PX may be connected to the second scan driving circuit12. According to necessity, the second scan driving circuit12may be omitted, and all of the pixels PX arranged in the display area DA may be electrically connected to the first scan driving circuit11.

The emission control driving circuit13may be arranged on a side of the first scan driving circuit11and configured to provide an emission control signal to the pixel PX through an emission control line EL.FIG.3shows that the emission control driving circuit13is arranged only on a side of the display area DA, but the emission control driving circuit13may be arranged on both sides of the display area DA like the first scan driving circuit11and the second scan driving circuit12.

The terminal14may be arranged in the second peripheral area PA2of the substrate100. The terminal14may not be covered by an insulating layer and be exposed, thus being electrically connected to the printed circuit board30. A terminal32of the printed circuit board30may be electrically connected to the terminal14of the display panel10.

The printed circuit board30may be configured to transmit a signal or power from a controller to the display panel10. Control signals generated in the controller may be transmitted to the driving circuits11to13, respectively, through the printed circuit board30. Also, the controller may transmit a driving voltage (ELVDD, seeFIG.4) to the driving voltage supply line15and a common voltage (ELVSS, seeFIG.4) to the common voltage supply line16. The driving voltage ELVDD may be transmitted to each pixel PX through a driving power line PL connected to the driving voltage supply line15, and the common voltage ELVSS may be transmitted to an opposite electrode (a common electrode) of the pixel PX connected to the common voltage supply line16. The driving voltage supply line15may have a shape extending in a direction (e.g., the x-axis direction) on a lower side of the display area DA. The common voltage supply line16may have a loop shape with one open side and thus partially surround the display area DA.

The controller may generate data signals, and the generated data signals may be transmitted to an input line IL through the driving chip20and to the pixel PX through a data line DL connected to the input line IL.

For reference, the term “line” may indicate a “wire,” which is also applied to embodiments below and modified examples.

FIGS.2and3are schematic plan views showing an enlarged view of the portion A of the display apparatus ofFIG.1.

Various signals may be applied to the display area DA. For example, a data signal, etc. for adjusting the brightness of each pixel may be applied to the display area DA. To this end, as shown inFIG.2, data lines DL1to DL6, which are arranged in a first direction (the x-axis direction) to be substantially parallel to each other and extend in a second direction (a y-axis direction) crossing the first direction, may be arranged in the display area DA. According to necessity, as shown inFIG.2, the data lines DL1to DL6may have shapes extending from the peripheral area PA to the display area DA. Various lines such as power lines or scan lines other than the data lines DL1to DL6may also be arranged in the display area DA.

In the peripheral area PA, specifically, the second peripheral area PA2, a first input line IL1to a sixth input line IL6may be located. The first input line IL1to the sixth input line IL6may be connected to the driving chip20and receive the data signals. The first data line DL1to the sixth data line DL6may be electrically connected to the first input line IL1to the sixth input line IL6, and configured to transmit the data signals to pixels in the display area DA.

InFIGS.2and3, the number of input lines and the number of data lines each are six for convenience of explanation. However, one or more embodiments are not limited thereto, and the number of each of the input lines and the data lines may be greater than or equal to six.

The first input line IL1to the sixth input line IL6may be sequentially arranged on an edge of the second peripheral area PA2(in a direction towards the first peripheral area PA1) in a central direction (a +x direction) of the second peripheral area PA2.

According to some embodiments, the first input line IL1, the third input line IL3, and the fifth input line IL5, which are odd-numbered lines, may be electrically connected to the first data line DL1, the third data line DL3, and the fifth data line DL5, which are adjacent to each other and continuously arranged. The first input line IL1, the third input line IL3, and the fifth input line IL5may be integrally formed with corresponding ones among the first data line DL1, the third data line DL3, and the fifth data line DL5, and as shown inFIGS.2and3, the first input line IL1, the third input line IL3, and the fifth input line IL5may be electrically connected to corresponding ones of the first data line DL1, the third data line DL3, and the fifth data line DL5through a first contact hole CNT1, respectively. In the latter case, as shown inFIG.3, the first data line DL1, the third data line DL3, and the fifth data line DL5may be located over an insulating layer covering the first input line IL1, the third input line IL3, and the fifth input line IL5. The first data line DL1, the third data line DL3, and the fifth data line DL5may receive the data signals from the first input line IL1, the third input line IL3, and the fifth input line IL5.

As shown inFIG.2, the second input line IL2, the fourth input line IL4, and the sixth input line IL6, which are even-numbered lines, may be electrically connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6, which are adjacent to each other and continuously arranged, through a first data transmission line DTL1, a second data transmission line DTL2, and a third data transmission line DTL3. That is, the second data line DL2, the fourth data line DL4, and the sixth data line DL6may receive the data signals from the second input line IL2, the fourth input line IL4, and the sixth input line IL6through the first data transmission line DTL1to the third data transmission line DTL3.

The first data transmission line DTL1to the third data transmission line DTL3may be arranged to pass a portion of the display area DA, which is adjacent to the peripheral area PA, that is, the display area DA. The second input line IL2may be electrically connected to the second data line DL2through the first data transmission line DTL1, the fourth input line IL4may be electrically connected to the fourth data line DL4through the second data transmission line DTL2, and the sixth input line IL6may be electrically connected to the sixth data line DL6through the third data transmission line DTL3.

Ends of the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3may be electrically connected to the second input line IL2, the fourth input line IL4, and the sixth input line IL6, respectively, through a second contact hole CNT2, and the other ends thereof may be respectively connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6.FIGS.2and3show that the second contact hole CNT2is located in the second peripheral area PA2, but one or more embodiments are not limited thereto. For example, the second contact hole CNT2may be located in the display area DA.

Because of the above structure, the second input line IL2may be configured to transmit the data signal to the second data line DL2, the fourth input line IL4may be configured to transmit the data signal to the fourth data line DL4, and the sixth input line IL6may be configured to transmit the data signal to the sixth data line DL6.

FIG.3shows in detail example configurations of the first data transmission line DTL1to the third data transmission line DTL3.

As described above, the second input line IL2, the fourth input line IL4, and the sixth input line IL6may be electrically connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6through the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3. In this case, the first data transmission line DTL1may include a first vertical connection line DV1′, a first horizontal connection line DH1, and a first additional vertical connection line DV1. Similarly, the second data transmission line DTL2may include a second vertical connection line DV2′, a second horizontal connection line DH2, and a second additional vertical connection line DV2. The third data transmission line DTL3may include a third vertical connection line DV3′, a third horizontal connection line DH3, and a third additional vertical connection line DV3.

The first vertical connection line DV1′ to the third vertical connection line DV3′ and the first additional vertical connection line DV1to the third additional vertical connection line DV3may be arranged substantially in parallel with the first data line DL1to the sixth data line DL6. The first horizontal connection line DH1to the third horizontal connection line DH3may each have a shape extending in the first direction (the x-axis direction) crossing the second direction (the y-axis direction) in which the first data line DL1to the sixth data line DL6extend.

The second input line IL2, the fourth input line IL4, and the sixth input line IL6may be electrically and respectively connected to their corresponding ones of the first additional vertical connection line DV1to the third additional vertical connection line DV3through the second contact hole CNT2. The first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3may be electrically connected to their corresponding ones of the first additional vertical connection line DV1, the second additional vertical connection line DV2, and the third additional vertical connection line DV3through first connection contact holes DH-CNT1located in ends of the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3. The first connection contact hole DH-CNT1may be located in the display area DA. The first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3may be electrically connected to their corresponding ones of the first vertical connection line DV1′, the second vertical connection line DV2′, and the third vertical connection line DV3′ through second connection contact holes DH-CNT2located in the other ends of the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3. The second connection contact hole DH-CNT2may be located in the display area DA.

The first vertical connection line DV1′, the second vertical connection line DV2′, and the third vertical connection line DV3′ may be electrically connected to their corresponding ones of the second data line DL2, the fourth data line DL4, and the sixth data line DL6, respectively. In detail, the first vertical connection line DV1′, the second vertical connection line DV2′, and the third vertical connection line DV3′ may be electrically connected to their corresponding ones of the second data line DL2, the fourth data line DL4, and the sixth data line DL6, respectively, in the peripheral area PA on the outer side of the display area DA, for example, in the first peripheral area PA1.FIG.3shows that the first vertical connection line DV1′, the second vertical connection line DV2′, and the third vertical connection line DV3′ respectively correspond to and are integrally formed with the second data line DL2, the fourth data line DL4, and the sixth data line DL6, and thus, the first vertical connection line DV1′, the second vertical connection line DV2′, and the third vertical connection line DV3′ are respectively connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6in the first peripheral area PA1.

The first data line DL1to the sixth data line DL6, the first vertical connection line DV1′ to the third vertical connection line DV3′, and the first additional vertical connection line DV1to the third additional vertical connection line DV3may be arranged on the same layer. The first horizontal connection line DH1to the third horizontal connection line DH3may be located on a different layer from the first data line DL1to the sixth data line DL6.FIG.3shows that the first data line DL1to the sixth data line DL6, etc. are located on an insulating layer covering the first horizontal connection line DH1to the third horizontal connection line DH3. For reference, the description that components are on the same layer may indicate that the components are simultaneously formed of the same material through the same mask process. In this case, the components may include the same material.

When viewed in a direction perpendicular to the substrate100(in the z-axis direction), the first horizontal connection line DH1may cross the first data line DL1, the second horizontal connection line DH2may cross the first data line DL1to the third data line DL3, and the third horizontal connection line DH3may cross the first data line DL1to the fifth data line DL5. Therefore, as described above, the first horizontal connection line DH1to the third horizontal connection line DH3may be arranged under the first data line DL1to the sixth data line DL6not to contact data lines crossing the first horizontal connection line DH1to the third horizontal connection line DH3.

As shown inFIG.3, the display apparatus may further include dummy lines.

As shown inFIG.3, the display apparatus may include a first auxiliary horizontal connection line ADH1that is apart from the first horizontal connection line DH1, is electrically insulated from the first horizontal connection line DH1and the second data line DL2, and has the same extension axis as an extension axis of the first horizontal connection line DH1. For example, the display apparatus may include the first auxiliary horizontal connection line ADH1arranged on one side of the first horizontal connection line DH1(the −x direction) and the first auxiliary horizontal connection line ADH1arranged on the other side of the first horizontal connection line DH1(the +x direction). Likewise, the display apparatus may include a second auxiliary horizontal connection line ADH2arranged on one side of the second horizontal connection line DH2(the −x direction) and a second auxiliary horizontal connection line ADH2arranged on the other side of the second horizontal connection line DH2(the +x direction), and may include a third auxiliary horizontal connection line ADH3arranged on one side of the third horizontal connection line DH3(the −x direction) and a third auxiliary horizontal connection line ADH3arranged on the other side of the third horizontal connection line DH3(the +x direction). The first auxiliary horizontal connection line ADH1, the second auxiliary horizontal connection line ADH2, and the third auxiliary horizontal connection line ADH3are electrically insulated from the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3and also from the data lines.

To this end, a structural difference between pixels, through which the first horizontal connection line DH1to the third horizontal connection line DH3pass, and pixels, through which the first horizontal connection line DH1to the third horizontal connection line DH3do not pass, may be reduced. As a result, when the same electrical signal is applied to the pixels, the difference in the brightness of the pixels may be reduced, and thus, a display apparatus capable of displaying a high-quality image may be realized. The first auxiliary horizontal connection line ADH1to the third auxiliary horizontal connection line ADH3may be on the same layer as the first horizontal connection line DH1to the third horizontal connection line DH3.

Similarly, the display apparatus may include a first auxiliary vertical connection line ADV1′ that is apart from the first vertical connection line DV1′, is electrically insulated from the first vertical connection line DV1′ and the first horizontal connection line DH1, has the same extension axis as an extension axis of the first vertical connection line DV1′, and thus is arranged on one side of the first vertical connection line DV1′ (the +y direction). Likewise, the display apparatus may include a second auxiliary vertical connection line ADV2′ that is on one side of the second vertical connection line DV2′ (the +y direction) and a third auxiliary vertical connection line ADV3′ that is on one side of the third vertical connection line DV3′ (+y direction). The first auxiliary vertical connection line ADV1′ to the third auxiliary vertical connection line ADV3′ may be on the same layer as the first vertical connection line DV1′ to the third vertical connection line DV3′.

The display apparatus may include a first auxiliary additional vertical connection line ADV1that is apart from the first additional vertical connection line DV1, is electrically insulated from the first additional vertical connection line DV1and the first horizontal connection line DH1, has the same extension axis as an extension axis of the first additional vertical connection line DV1, and thus is arranged on one side of the first additional vertical connection line DV1(the +y direction). Likewise, the display apparatus may include a second auxiliary additional vertical connection line ADV2that is on one side of the second additional vertical connection line DV2(the +y direction) and a third auxiliary additional vertical connection line ADV3that is on one side of the third additional vertical connection line DV3(+y direction). The first auxiliary additional vertical connection line ADV1to the third auxiliary additional vertical connection line ADV3may be on the same layer as the first additional vertical connection line DV1to the third additional vertical connection line DV3.

To this end, the structural difference between the pixels, through which the first additional vertical connection line DV1to the third additional vertical connection line DV3pass, and the pixels, through which the first vertical connection line DV1′ to the third vertical connection line DV3′ do not pass, may decrease. The structural difference between the pixels, through which the first additional vertical connection line DV1to the third additional vertical connection line DV3pass, and the pixels, through which the first additional vertical connection line DV1to the third additional vertical connection line DV3do not pass, may decrease. As a result, when the same electrical signal is applied to the pixels, the difference in the brightness of the pixels may be reduced, and thus, a display apparatus capable of displaying a high-quality image may be realized.

As shown inFIG.3, a fourth horizontal connection line DH4may be located in a central direction (the +y direction) of the display area DA of the third horizontal connection line DH3. Similar to the third horizontal connection line DH3, the fourth horizontal connection line DH4may extend in the first direction (the x-axis direction). The fourth horizontal connection line DH4may extend from the first peripheral area PA1on one side of the display area DA (in the −x direction) to the first peripheral area PA1on the other side of the display area DA (in the +x direction). The fourth horizontal connection line DH4may not be electrically connected to the data lines. The display apparatus may include a plurality of fourth horizontal connection lines DH4that are apart from each other. As there are the fourth horizontal connection lines DH4, the structural difference between pixels, through which the third horizontal connection line DH3, etc. pass, and pixels located at the center of the display area DA, etc. may be reduced. Both ends of each of the fourth horizontal connection lines DH4that are not electrically connected to the data lines may be electrically connected to, for example, the common voltage supply line16. To this end, the common voltage ELVSS may be evenly transmitted to the opposite electrode in the entire display area DA.

FIG.4is an equivalent circuit diagram of a pixel PX included in the display apparatus ofFIG.1. As shown inFIG.4, the pixel PX may include a pixel circuit PC and an organic light-emitting diode OLED electrically connected thereto.

As shown inFIG.4, the pixel circuit PC may include a plurality of thin-film transistors T1to T8and a storage capacitor Cst. The thin-film transistors T1to T8and the storage capacitor Cst may be connected to signal lines GWL, GCL, GIL, GBL, EL, and DL, a first initialization voltage line VIL, a second initialization voltage line VL, a driving voltage line PL, and a bias voltage line VBL. At least any one of the above lines, e.g., the driving voltage line PL, may be shared by neighboring pixels PX.

The thin-film transistors T1to T8may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6, a bias transistor T7, and a second initialization transistor T8.

The organic light-emitting diode OLED may include a pixel electrode and an opposite electrode, the pixel electrode of the organic light-emitting diode OLED may be connected to the driving transistor T1through the emission control transistor T6and receive a driving current, and the opposite electrode of the organic light-emitting diode OLED may receive the common voltage ELVSS. The organic light-emitting diode OLED may generate light having a brightness corresponding to the driving current.

Some of the thin-film transistors T1to T8may each be an n-channel MOSFET (NMOS), and the others thereof may each be a p-channel MOSFET (PMOS). For example, the compensation transistor T3and the first initialization transistor T4among the thin-film transistors T1to T8may each be an NMOS, and the others thereof may each be a PMOS. Alternatively, the compensation transistor T3, the first initialization transistor T4, and the second initialization transistor T8among the thin-film transistors T1to T8may each be an NMOS, and the others thereof may each be a PMOS. Alternatively, all of the thin-film transistors T1to T8may be NMOSs or PMOSs. The thin-film transistors T1to T8may include amorphous silicon or polysilicon. According to necessity, an NMOS may include an oxide semiconductor. Hereinafter, the compensation transistor T3and the first initialization transistor T4each are an NMOS including an oxide semiconductor, and the others each are a PMOS.

The signal lines may include a first scan line GWL configured to transmit a first scan signal GW, a second scan line GCL configured to transmit a second scan signal GC, a third scan line GIL configured to transmit an initialization scan signal GI to the first initialization transistor T4, a fourth scan line GBL configured to transmit a bias scan signal GB to the second initialization transistor T8, an emission control line EL configured to transmit an emission control signal EM to the operation control transistor T5and the emission control transistor T6, and a data line DL crossing the first scan line GWL and configured to transmit a data signal DATA.

The driving voltage line PL may be configured to transmit the driving voltage ELVDD to the driving transistor T1, the first initialization voltage line VIL may be configured to transmit a first initialization voltage Vint for initializing the driving transistor T1, and the second initialization voltage line VL may be configured to transmit a second initialization voltage Vaint for initializing the pixel electrode of the organic light-emitting diode OLED.

A driving gate electrode of the driving transistor T1may be connected to the storage capacitor Cst through a second node N2, any one of a source area and a drain area of the driving transistor T1may be connected to the driving voltage line PL through a first node N1via the operation control transistor T5, and the other of the source area and the drain area of the driving transistor T1may be electrically connected to the pixel electrode of the organic light-emitting diode OLED through a third node N3via the emission control transistor T6. The driving transistor T1may receive the data signal DATA according to a switching operation of the switching transistor T2and may be configured to supply a driving current to the organic light-emitting diode OLED. That is, the driving transistor T1may control the amount of current flowing to the organic light-emitting diode OLED from the first node N1electrically connected to the driving voltage line PL, according to a voltage differing according to the data signal DATA and applied to the second node N2.

A switching gate electrode of the switching transistor T2may be connected to the first scan line GWL configured to transmit the first scan signal GW, any one of a source area and a drain area of the switching transistor T2may be connected to the data line DL, and the other thereof may be connected to the driving transistor T1through the first node N1and also to the driving voltage line PL via the operation control transistor T5. The switching transistor T2may be configured to transmit, to the first node N1, the data signal DATA transmitted through the data line DL, according to a voltage applied to the first scan line GWL. That is, the switching transistor T2may be turned on in response to the first scan signal GW transmitted through the first scan line GWL and perform a switching operation of transmitting the data signal DATA, which is transmitted through the data line DL, to the driving transistor T1through the first node N1.

A compensation gate electrode of the compensation transistor T3is connected to the second scan line GCL. Any one of a source area and a drain area of the compensation transistor T3may be connected to the pixel electrode of the organic light-emitting diode OLED through the third node N3via the emission control transistor T6. The other of the source area and the drain area of the compensation transistor T3may be connected to a first capacitor electrode of the storage capacitor Cst and the driving gate electrode of the driving transistor T1through the second node N2. The compensation transistor T3may be turned on in response to the second scan signal GC transmitted through the second scan line GCL and may diode-connect the driving transistor T1.

A first initialization gate electrode of the first initialization transistor T4may be connected to the third scan line GIL. Any one of a source area and a drain area of the first initialization transistor T4may be connected to the first initialization voltage line VIL. The other of the source area and the drain area of the first initialization transistor T4may be connected to the first capacitor electrode of the storage capacitor Cst, the driving gate electrode of the driving transistor T1, and the like through the second node N2. The first initialization transistor T4may apply the first initialization voltage Vint, which is transmitted through the first initialization voltage line VIL, to the second node N2, according to a voltage applied to the third scan line GIL. That is, the first initialization transistor T4may be turned on in response to the initialization scan signal GI transmitted through the third scan line GIL and may be configured to transmit the first initialization voltage Vint to the driving gate electrode of the driving transistor T1, thereby performing an initialization operation of initializing a voltage of the driving gate electrode of the driving transistor T1.

An operation control gate electrode of the operation control transistor T5may be connected to the emission control line EL, any one of a source area and a drain area of the operation control transistor T5may be connected to the driving voltage line PL, and the other thereof may be connected to the driving transistor T1and the switching transistor T2through the first node N1.

An emission control gate electrode of the emission control transistor T6may be connected to the emission control line EL, any one of a source area and a drain area of the emission control transistor T6may be connected to the driving transistor T1and the compensation transistor T3through the third node N3, and the other thereof may be electrically connected to the pixel electrode of the organic light-emitting diode OLED.

The operation control transistor T5and the emission control transistor T6may be simultaneously turned on in response to the emission control signal EM transmitted through the emission control line EL and configured to transmit electrical signals from the driving voltage ELVDD to the organic light-emitting diode OLED so that the driving current flows in the organic light-emitting diode OLED.

The bias transistor T7may be connected between the first node N1and the bias voltage line VBL. The bias transistor T7may be turned on in response to the bias scan signal GB transmitted through the fourth scan line GBL and apply a bias voltage VOBS to the first node N1to thus preset, in the first node N1, a voltage appropriate for a subsequent operation of the driving transistor T1. In this regard, the fourth scan line GBL may be referred to as a bias gate line.

A second initialization gate electrode of the second initialization transistor T8may be connected to the fourth scan line GBL, any one of a source area and a drain area of the second initialization transistor T8may be connected to the pixel electrode of the organic light-emitting diode OLED, and the other thereof may be connected to the second initialization voltage line VL and receive the second initialization voltage Vaint. The second initialization transistor T8is turned on in response to the bias scan signal GB transmitted through the fourth scan line GBL and initializes the pixel electrode of the organic light-emitting diode OLED.

The storage capacitor Cst may include the first capacitor electrode and a second capacitor electrode. The first capacitor electrode of the storage capacitor Cst is connected to the driving gate electrode of the driving transistor T1through the second node N2, and the second capacitor electrode of the storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst may store therein electric charges corresponding to a difference between the voltage of the driving gate electrode of the driving transistor T1and the driving voltage ELVDD.

A detailed operation of each pixel PX according to some embodiments is described as follows.

During an initialization period, when the initialization scan signal GI is provided through the third scan line GIL, the first initialization transistor T4is turned on in response to the initialization scan signal GI, and the driving transistor T1is initialized according to the first initialization voltage Vint provided through the first initialization voltage line VIL. When the bias scan signal GB is provided through the fourth scan line GBL, the second initialization transistor T8is turned on in response to the bias scan signal GB, and the pixel electrode of the organic light-emitting diode OLED is initialized according to the second initialization voltage Vaint provided through the second initialization voltage line VL. Also, the bias transistor T7is also turned on in response to the bias scan signal GB and configured to apply the bias voltage VOBS to the first node N, and thus, a voltage appropriate for a subsequent operation of the driving transistor T1may be preset in the first node N1.

During a data programming period, when the first scan signal GW and the second scan signal GC are respectively provided through the first scan line GWL and the second scan line GCL, the switching transistor T2and the compensation transistor T3are respectively turned on in response to the first scan signal GW and the second scan signal GC. In this case, the driving transistor T1is diode-connected by the compensation transistor T3that is on, and biased in a forward direction. Then, a compensation voltage DATA+Vth (where Vth has a negative value), which is generated by subtracting a threshold voltage Vth of the driving transistor T1from the data signal DATA provided through the data line DL, is applied to the driving gate electrode of the driving transistor T1. The driving voltage ELVDD and the compensation voltage DATA+Vth are applied to both ends of the storage capacitor Cst, and electric charges corresponding to a voltage difference in the ends of the storage capacitor Cst are stored in the storage capacitor Cst.

During an emission period, the operation control transistor T5and the emission control transistor T6are turned on in response to the emission control signal EM transmitted through the emission control line EL. A driving current according to a difference between the voltage of the driving gate electrode of the driving transistor T1and the driving voltage ELVDD is generated, and the driving current is supplied to the organic light-emitting diode OLED through the emission control transistor T6.

As described above, some of the thin-film transistors T1to T8may include oxide semiconductors. For example, the compensation transistor T3and the first initialization transistor T4may include oxide semiconductors.

Because polysilicon is highly reliable, an accurately intended current may be allowed to flow. Therefore, the driving transistor T1directly affecting the brightness of the display apparatus includes a semiconductor layer including polysilicon with high reliability, and thus, a high-resolution display apparatus may be realized. Because an oxide semiconductor has high carrier mobility and a low leakage current, a voltage drop is not great despite a long operation time. That is, in the case of the oxide semiconductor, because a color change in images according to the voltage drop is not noticeable even during a low-frequency operation, the display apparatus may operate at a low frequency. Therefore, the compensation transistor T3and the first initialization transistor T4each are designed to include an oxide semiconductor, and thus, a display apparatus in which the occurrence of a leakage current may be prevented or reduced and the power consumption is reduced may be realized.

Such an oxide semiconductor is sensitive to light, and thus, some changes may be made to the amount of current, etc. because of external light. Therefore, a metal layer is arranged under the oxide semiconductor to absorb or reflect the external light. As shown inFIG.4, in each of the compensation transistor T3and the first initialization transistor T4including the oxide semiconductors, gate electrodes may be respectively arranged over and under an oxide semiconductor layer. That is, when viewed in a direction perpendicular to an upper surface of the substrate100(in a z-axis direction), the metal layer arranged under the oxide semiconductor may overlap the oxide semiconductor.

FIG.5is a schematic layout of emission areas of pixels included in the display apparatus ofFIG.1.

The pixels arranged in the display area DA may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3may be repeatedly arranged along a certain pattern in an x-axis direction and a y-axis direction. The first pixel PX1, the second pixel PX2, and the third pixel PX3may each include a pixel circuit and an organic light-emitting diode OLED electrically connected thereto. The organic light-emitting diode OLED of each pixel may be located on an upper layer of the pixel circuit. The organic light-emitting diode OLED may be located directly on the pixel circuit to overlap the same or may be offset from the pixel circuit and arranged to partially overlap a pixel circuit of another pixel in an adjacent pixel and/or column.

FIG.5shows a pixel electrode PE and an emission area of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. The emission area is an area where an emission layer of the organic light-emitting diode OLED is arranged. The emission area may be defined by a pixel-defining layer including an opening corresponding to a central portion of the pixel electrode PE. Each pixel electrode PE may include a first area PEA1corresponding to the emission area and a second area PEA2surrounding the first area PEA1. The first area PEA1may correspond to the opening of the pixel-defining layer, and the second area PEA2may be a portion covered by the pixel-defining layer.

In a first column M1, a first emission area EA1of the first pixel PX1and a third emission area EA3of the third pixel PX3may be alternately arranged in the y-axis direction. In a second column M2, a second emission area EA2of the second pixel PX2may be repeatedly arranged in the y-axis direction. The first column M1and the second column M2may be alternately arranged in the x-axis direction, and the first emission areas EA1of the first pixels PX1may be arranged opposite to the third emission areas EA3of the third pixels PX3in adjacent first columns M1.

In a first sub-row SN1of each row N, the first emission area EA1of the first pixel PX1and the third emission area EA3of the third pixel PX3may be alternately arranged in the x-axis direction, and in a second sub-row SN2, the second emission areas EA2of the second pixels PX2may be repeatedly arranged in the x-axis direction. That is, in each row N, the first emission area EA1of the first pixel PX1, the second emission area EA2of the second pixel PX2, the third emission area EA3of the third pixel PX3, and the second emission area EA2of the second pixel PX2may be repeatedly arranged in a zigzag form.

The first emission area EA1of the first pixel PX1, the second emission area EA2of the second pixel PX2, and the third emission area EA3of the third pixel PX3may have different areas. For example, the third emission area EA3of the third pixel PX3may have a greater area than the first emission area EA1of the first pixel PX1. Also, the third emission area EA3of the third pixel PX3may have a greater area than the second emission area EA2of the second pixel PX2. The first emission area EA1of the first pixel PX1may have a greater area than the second emission area EA2of the second pixel PX2. In some embodiments, the third emission area EA3of the third pixel PX3may have the same area as the first emission area EA1of the first pixel PX1. However, one or more embodiments are not limited thereto. Various modifications may be made, and for example, the first emission area EA1of the first pixel PX1may have a greater area than the second emission area EA2of the second pixel PX2and the third emission area EA3of the third pixel PX3.

Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3may have a polygonal shape such as a rectangular shape or an octagonal shape, a circular shape, or an oval shape. In the case of the polygonal shape, corners (vertices) of the first emission area EA1, the second emission area EA2, and the third emission area EA3may be rounded.

The first pixel PX1may be a red pixel R emitting red light, the second pixel PX2may be a green pixel G emitting green light, and the third pixel PX3may be a blue pixel B emitting blue light.

FIG.6is a schematic layout showing locations of transistors, capacitors, and other components in pixels of the display apparatus ofFIG.1,FIGS.7to13are schematic layouts showing, for each level, components, e.g., transistors and capacitors, which are included in the display apparatus ofFIG.6,FIG.14is a schematic layout of a pixel electrode layer of the display apparatus ofFIG.6, and FIG.15is a schematic cross-sectional view of the display apparatus ofFIG.6taken along a line A-A′ and a line B-B′ ofFIG.6.

As shown in the above drawings, the display apparatus may include a first pixel area PXA1and a second pixel area PXA2that are adjacent to each other. A pixel circuit of the first pixel PX1may be arranged in the first pixel area PXA1, and a pixel circuit of the second pixel PX2may be arranged in the second pixel area PXA2. The first pixel area PXA1may be substantially symmetrical to the second pixel area PXA2with respect to a virtual boundary line IBL, as shown inFIG.6, etc. Alternatively, the first pixel area PXA1may have the same configuration as the second pixel area PXA2, instead of a symmetrical configuration. Hereinafter, for convenience, some conductive patterns are described based on the pixel circuit in the first pixel area PXA1, but such conductive patterns may be symmetrically or identically arranged in the second pixel area PXA2.

For reference, the configuration shown inFIGS.6to13may be repeated in the first direction (the x-axis direction) as well as the second direction (the y-axis direction).

On the substrate100, a buffer layer (101, seeFIG.15) including silicon oxide, silicon nitride, or silicon oxynitride may be located. The buffer layer101may prevent or reduce instances of metal atoms, impurities, or the like diffusing from the substrate100towards a first semiconductor layer SACT located on the buffer layer101. Also, the buffer layer101may adjust the heat irradiation speed during a crystallization process of forming the first semiconductor layer SACT, and thus, the first semiconductor layer SACT may be evenly crystallized.

The first semiconductor layer SACT shown inFIG.7may be located on the buffer layer101. The first semiconductor layer SACT may include a silicon semiconductor. For example, the first semiconductor layer SACT may include amorphous silicon or polysilicon. In detail, the first semiconductor layer SACT may include polysilicon crystallized at a low temperature. According to necessity, ions may be injected into at least a portion of the first semiconductor layer SACT.

The first semiconductor layer SACT may include a first sub-semiconductor layer SACT1and a second sub-semiconductor layer SACT2separated from the first sub-semiconductor layer SACT1. The first sub-semiconductor layer SACT1in the first pixel area PXA1may be integrally formed with the first sub-semiconductor layer SACT1in the second pixel area PXA2. As described below, the second sub-semiconductor layer SACT2may be electrically connected to the first sub-semiconductor layer SACT1by a connection electrode176included in a first connection electrode layer SD1.

The first sub-semiconductor layer SACT1may have a shape curved in various forms. The driving transistor T1, the switching transistor T2, the operation control transistor T5, the emission control transistor T6, and the second initialization transistor T8may be arranged along the first sub-semiconductor layer SACT1. That is, the first sub-semiconductor layer SACT1may include a channel area of each of the driving transistor T1, the switching transistor T2, the operation control transistor T5, the emission control transistor T6, and the second initialization transistor T8, and a source area and a drain area arranged on both sides of the channel area. The second sub-semiconductor layer SACT2may include a channel area, a source area, and a drain area of the bias transistor T7. InFIG.7, locations of the channel areas of the above transistors T1, T2, and T5to T8are indicated by reference symbols of the transistors T1, T2, and T5to T8. The source area and the drain area are located on one side and the other side of the channel area.

A first gate insulating layer (102, seeFIG.15) may cover the first semiconductor layer SACT and may be arranged above the substrate100. The first gate insulating layer102may include an insulating material. For example, the first gate insulating layer102may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

A first gate layer GTL1shown inFIG.8may be located on the first gate insulating layer102. The first gate layer GTL1includes the first scan line GWL configured to transmit the first scan signal GW, the fourth scan line GBL configured to transmit the bias scan signal GB to the second initialization transistor T8, the emission control signal EL configured to transmit the emission control signal EM to the operation control transistor T5and the emission control transistor T6, the first initialization voltage line VIL configured to transmit the first initialization voltage Vint for initializing the driving transistor T1, and a driving gate electrode131aof the driving transistor T1having an isolated shape. The driving gate electrode131amay function as a lower electrode that is a first electrode of the storage capacitor Cst.

The first scan line GWL, the fourth scan line GBL, the emission control line EL, and the first initialization voltage line VIL may each have a shape substantially extending in the first direction (the x-axis direction). Portions of the first scan line GWL, the fourth scan line GBL, and the emission control line EL, which overlap the first semiconductor layer SACT, may respectively function as gate electrodes of transistors. That is, the portion of the first scan line GWL, which overlaps the first semiconductor layer SACT, may be the switching gate electrode of the switching transistor T2, the portion of the fourth scan line GBL, which overlaps the first semiconductor layer SACT, may be a bias gate electrode of the bias transistor T7, the portions of the emission control line EL, which overlaps the first semiconductor layer SACT, may be the operation control gate electrode of the operation control transistor T5and the emission control gate electrode of the emission control transistor T6.

The first gate layer GTL1may include a metal, an alloy, conductive metal oxide, a transparent conductive material, or the like. For example, the first gate layer GTL1may include silver (Ag), an alloy containing Ag, molybdenum (Mo), an alloy containing Mo, aluminum (Al), an alloy containing Al, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), or the like. The first gate layer GTL1may have a multilayered structure, for example, a two-layer structure of Mo/Al or a three-layer structure of Mo/Al/Mo.

A second gate insulating layer (103, seeFIG.15) may cover the first gate layer GTL1and may be located on the first gate insulating layer102. The second gate insulating layer103may include the same insulating material as or a similar insulating material to the first gate insulating layer102.

A second gate layer GTL2shown inFIG.9may be located on the second gate insulating layer103. The second gate layer GTL2may include an electrode voltage line HL, a lower gate line GCL1of the second scan line GCL, and a lower gate line GIL1of the third scan line GIL. The electrode voltage line HL, the lower gate line GCL1of the second scan line GCL, and the lower gate line GIL1of the third scan line GIL may extend in the first direction (the x-axis direction).

A portion of the electrode voltage line HL may be an upper electrode that is a second electrode of the storage capacitor Cst and overlap the driving gate electrode131athat is the lower electrode of the storage capacitor Cst. Upper electrodes of storage capacitors Cst of pixel circuits in the same row may be integrally formed with each other by the electrode voltage line HL. The driving voltage ELVDD may be applied to the upper electrode of the storage capacitor Cst. An opening SOP may be formed in the upper electrode of the storage capacitor Cst, and at least a portion of the driving gate electrode131amay overlap the opening SOP.

A portion of the lower gate line GCL1of the second scan line GCL, which overlaps a second semiconductor layer OACT which is an oxide semiconductor layer described below, may be a compensation lower gate electrode of the compensation transistor T3, and a portion of the lower gate line GIL1of the third scan line GIL, which overlaps the second semiconductor layer OACT, may be a first initialization lower gate electrode of the first initialization transistor T4.

The second gate layer GTL2may include a metal, an alloy, conductive metal oxide, a transparent conductive material, or the like. For example, the second gate layer GTL2may include Ag, an alloy containing Ag, Mo, an alloy containing Mo, Al, an alloy containing Al, AlN, W, WN, Cu, Ni, Cr, CrN, Ti, Ta, Pt, Sc, ITO, IZO, or the like. The second gate layer GTL2may have a multilayered structure, for example, a two-layer structure of Mo/Al or a three-layer structure of Mo/Al/Mo.

A first interlayer insulating layer (104, seeFIG.15) may cover the second gate layer GTL2and may be located on the second gate insulating layer103. The first interlayer insulating layer104may include an insulating material. For example, the first interlayer insulating layer104may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

The second semiconductor layer OACT shown inFIG.10may be located on the first interlayer insulating layer104. As described above, the second semiconductor layer OACT may include an oxide semiconductor. The second semiconductor layer OACT may be located on a different layer from the first semiconductor layer SACT and may not overlap the same when viewed in the direction perpendicular to the substrate100(in the z-axis direction). The second semiconductor layer OACT may form the compensation transistor T3and the first initialization transistor T4. InFIG.10, locations of the channel areas of the compensation transistor T3and the first initialization transistor T4are indicated by the reference symbols thereof. The source area and the drain area are located on one side and the other side of the channel area.

The second semiconductor layer OACT may include a 2nd-1stsemiconductor layer OACT1located in the first pixel area PXA1and extending in the second direction (the y-axis direction) and a semiconductor extension layer OACTE extending from the 2nd-1stsemiconductor layer OACT1in the first direction (the x-axis direction). Because a 2nd-2ndsemiconductor layer OACT2extending in the second direction (the y-axis direction) may be located in the second pixel area PXA2, an end of the semiconductor extension layer OACTE may be connected to the 2nd-1stsemiconductor layer OACT1, and the other end thereof may be connected to the 2nd-2ndsemiconductor layer OACT2. That is, the 2nd-1stsemiconductor layer OACT1in the first pixel area PXA1, the 2nd-2ndsemiconductor layer OACT2in the second pixel area PXA2, and the semiconductor extension layer OACTE may be integrally formed.

A third gate insulating layer (105, seeFIG.15) may cover the second semiconductor layer OACT and may be located on the first interlayer insulating layer104. The third gate insulating layer105may include an insulating material. The third gate insulating layer105may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

A third gate layer GTL3shown inFIG.11may be located on the third gate insulating layer105. The third gate layer GTL3may include an upper gate line GCL2of the second scan line GCL, an upper gate line GIL2of the third scan line GIL, and the bias voltage line VBL. The upper gate line GCL2of the second scan line GCL, the upper gate line GIL2of the third scan line GIL, and the bias voltage line VBL may extend in the first direction (the x-axis direction), respectively.

A portion of the upper gate line GCL2of the second scan line GCL, which overlaps the second semiconductor layer OACT, may be a compensation upper gate electrode of the compensation transistor T3, and a portion of the upper gate line GIL2of the third scan line GIL, which overlaps the second semiconductor layer OACT, may be a first initialization upper gate electrode of the first initialization transistor T4. That is, the compensation transistor T3and the first initialization transistor T4may each have a double gate structure in which gate electrodes are located on and under the second semiconductor layer OACT.

The third gate layer GTL3may include a metal, an alloy, conductive metal oxide, a transparent conductive material, or the like. For example, the third gate layer GTL3may include Ag, an alloy containing Ag, Mo, an alloy containing Mo, Al, an alloy containing Al, AlN, W, WN, Cu, Ni, Cr, CrN, Ti, Ta, Pt, Sc, ITO, IZO, or the like. The third gate layer GTL3may have a multilayered structure, for example, a two-layer structure of Mo/Al or a three-layer structure of Mo/Al/Mo.

A second interlayer insulating layer (106, seeFIG.15) may cover at least a portion of the third gate layer GTL3ofFIG.11. The second interlayer insulating layer106may include an insulating material. For example, the second interlayer insulating layer106may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

The first connection electrode layer SD1shown inFIG.12may be located on the second interlayer insulating layer106. The first connection electrode layer SD1may include the second initialization voltage line VL, a horizontal connection line BRSH, and connection electrodes171to178. The second initialization voltage line VL and the horizontal connection line BRSH may each have a shape substantially extending in the first direction. The connection electrodes171to178may each have an isolated shape.

The second initialization voltage line VL may be connected to the first semiconductor layer SACT through a contact hole67penetrating an insulating layer under the second initialization voltage line VL in the first pixel area PXA1, where the pixel circuit of the first pixel PX1is arranged, and thus the second initialization voltage line VL may be electrically connected to the drain area of the second initialization transistor T8. The second initialization voltage line VL may have a curve and extend in a zigzag form in the first direction (the x-axis direction).

The horizontal connection line BRSH may be the first horizontal connection line DH1, the second horizontal connection line DH2, the third horizontal connection line DH3, the fourth horizontal connection line DH4, the first auxiliary horizontal connection line ADH1, the second auxiliary horizontal connection line ADH2, or the third auxiliary horizontal connection line ADH3described above with reference toFIG.3. That is, depending on the location of the horizontal connection line BRSH, the horizontal connection line BRSH may be the first horizontal connection line DH1, the second horizontal connection line DH2, the third horizontal connection line DH3, the fourth horizontal connection line DH4, the first auxiliary horizontal connection line ADH1, the second auxiliary horizontal connection line ADH2, or the third auxiliary horizontal connection line ADH3described above with reference toFIG.3.

An end of the connection electrode171may contact the second semiconductor layer OACT through a contact hole51and may be electrically connected to the second semiconductor layer OACT. In detail, the end of the connection electrode171may be electrically connected to the source area of the compensation transistor T3and the drain area of the first initialization transistor T4through the contact hole51penetrating insulating layers under the connection electrode171. The other end of the connection electrode171may be electrically connected to the driving gate electrode131aof the driving transistor T1through a contact hole52penetrating the insulating layers under the connection electrode171, wherein the driving gate electrode131aalso functions as the lower electrode of the storage capacitor Cst. Such a contact hole52may penetrate the opening SOP in the upper electrode of the storage capacitor Cst.

A connection electrode172may be electrically connected to the drain area of the driving transistor T1and the source area of the emission control transistor T6through a contact hole53penetrating insulating layers under the connection electrode172. The connection electrode172may be electrically connected to the drain area of the compensation transistor T3through a contact hole54penetrating insulating layers under the connection electrode172.

A connection electrode173may be electrically connected to the source area of the switching transistor T2through a contact hole55penetrating insulating layers under the connection electrode173.

A connection electrode174may be electrically connected to the source area of the operation control transistor T5through a contact hole56penetrating insulating layers under the connection electrode174. Also, the connection electrode174may be electrically connected to the electrode voltage line HL through a contact hole57penetrating insulating layers under the connection electrode174, wherein the electrode voltage line HL also functions as the upper electrode of the storage capacitor Cst.

A connection electrode175may be electrically connected to the first initialization voltage line VIL through a contact hole58penetrating insulating layers under the connection electrode175. The connection electrode175may be electrically connected to the drain area of the first initialization transistor T4through a contact hole59penetrating insulating layers under the connection electrode175. Accordingly, a first initialization voltage that is a constant voltage may be applied to the semiconductor extension layer OACTE of the second semiconductor layer OACT.

A connection electrode176may electrically connect the first sub-semiconductor layer SACT1to the second sub-semiconductor layer SACT2. In detail, the connection electrode176may be electrically connected to the source area of the driving transistor T1, the drain area of the operation control transistor T5, and the drain area of the switching transistor T2through a contact hole60penetrating insulating layers under the connection electrode176. The connection electrode176may be electrically connected to the drain area of the bias transistor T7through a contact hole61penetrating insulating layers under the connection electrode176.

A connection electrode177may be electrically connected to the drain area of the emission control transistor T6through a contact hole62penetrating insulating layers under the connection electrode177.

A connection electrode178may be electrically connected to the source area of the bias transistor T7through a contact hole65penetrating insulating layers under the connection electrode178. The connection electrode178may be electrically connected to the bias voltage line VBL through a contact hole66penetrating an insulating layer under the connection electrode178.

The first connection electrode layer SD1may include a metal, an alloy, conductive metal oxide, a transparent conductive material, or the like. For example, the first connection electrode layer SD1may include Ag, an alloy containing Ag, Mo, an alloy containing Mo, Al, an alloy containing Al, AlN, W, WN, Cu, Ni, Cr, CrN, Ti, Ta, Pt, Sc, ITO, IZO, or the like. The first connection electrode layer SD1may have a multilayered structure, for example, a two-layer structure of Ti/Al or a three-layer structure of Ti/Al/Ti.

A first planarization insulating layer (107, seeFIG.15) may cover the first connection electrode layer SD1and may be located on the second interlayer insulating layer106. The first planarization insulating layer107may include an organic insulating material. For example, the first planarization insulating layer107may include photoresist, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl-ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or any blend thereof.

A second connection electrode layer SD2shown inFIG.13may be located over the first planarization insulating layer107. The second connection electrode layer SD2may include the data line DL, the driving voltage line PL, a vertical connection line BRSV, and a connection electrode181. The data line DL, the driving voltage line PL, and the vertical connection line BRSV may substantially extend in the second direction (the y-axis direction).

The data line DL is electrically connected to the connection electrode173, which is included in the first connection electrode layer SD1, through a contact hole81penetrating the first planarization insulating layer107. As described above, the connection electrode173is connected to the source area of the switching transistor T2through the contact hole55penetrating the insulating layers under the connection electrode173, and the data line DL may be electrically connected to the source area of the switching transistor T2accordingly.

The driving voltage line PL extending in the second direction (the y-axis direction) may be electrically connected to the connection electrode174, which is included in the first connection electrode layer SD1, through a contact hole82penetrating the first planarization insulating layer107. As described above, the connection electrode174is connected to the electrode voltage line HL, which is included in the second gate layer GTL2and extends in the first direction (the x-axis direction), through the contact hole57penetrating the insulating layers under the connection electrode174. Therefore, the driving voltage line PL and the electrode voltage line HL, which are electrically connected to each other, may have a mesh structure. Accordingly, an IR drop of the driving voltage ELVDD may be prevented or reduced in the display area DA.

The driving voltage line PL may include a plurality of first driving voltage branches PL1, a plurality of second driving voltage branches PL2, and a plurality of driving voltage bodies PL3.

The driving voltage bodies PL3may be arranged in the second direction (the y-axis direction). The first driving voltage branches PL1may each have a shape extending in the second direction (the y-axis direction). The first driving voltage branches PL1may be arranged between the driving voltage bodies PL3to connect the driving voltage bodies PL3to each other. Accordingly, the first driving voltage branches PL1and the driving voltage bodies PL3may form the driving voltage line PL extending in the second direction (the y-axis direction).

The second driving voltage branches PL2may each have a shape extending in the second direction (the y-axis direction). The second driving voltage branches PL2may be arranged apart from the first driving voltage branches PL1in the first direction (the x-axis direction). However, the second driving voltage branches PL2do not respectively connect the driving voltage bodies PL3to each other. That is, an end of each of the second driving voltage branches PL2(in the −y direction) is connected to its corresponding one of the driving voltage bodies PL3. However, the other ends of the second driving voltage branches PL2(in the +y direction) are apart from the driving voltage bodies PL3.

The driving voltage line PL may include protrusions in addition to the first driving voltage branches PL1, the second driving voltage branches PL2, and the driving voltage bodies PL3.FIG.13shows that the protrusions include a first protrusion PL4and a second protrusion PL5. Such protrusions may protrude from the driving voltage bodies PL3in the second direction (the y-axis direction) to be arranged between the first driving voltage branches PL1and the second driving voltage branches PL2. In detail, the first protrusion PL4has a shape extending in the second direction (the y-axis direction) and has one side (in the −y direction) connected to the driving voltage body PL3. The second protrusion PL5is connected to the other end of the first protrusion PL4(in the +y direction). The second protrusion PL5may have a shape extending in the first direction (the x-axis direction).

The vertical connection line BRSV may be the first vertical connection line DV1′, the second vertical connection line DV2′, the third vertical connection line DV3′, the first additional vertical connection line DV1, the second additional vertical connection line DV2, the third additional vertical connection line DV3, the first auxiliary vertical connection line ADV1′, the second auxiliary vertical connection line ADV2′, the third auxiliary vertical connection line ADV3′, the first auxiliary additional vertical connection line ADV1, the second auxiliary additional vertical connection line ADV2, or the third auxiliary additional vertical connection line ADV3described above with reference toFIG.3. That is, depending on the location of the vertical connection line BRSV, the vertical connection line BRSV may be the first vertical connection line DV1′, the second vertical connection line DV2′, the third vertical connection line DV3′, the first additional vertical connection line DV1, the second additional vertical connection line DV2, the third additional vertical connection line DV3, the first auxiliary vertical connection line ADV1′, the second auxiliary vertical connection line ADV2′, the third auxiliary vertical connection line ADV3′, the first auxiliary additional vertical connection line ADV1, the second auxiliary additional vertical connection line ADV2, or the third auxiliary additional vertical connection line ADV3described above with reference toFIG.3. The vertical connection line BRSV may be connected to the horizontal connection line BRSH, which is included in the first connection electrode layer SD1, through a contact hole, which is described above with reference toFIG.3.

The connection electrode181is electrically connected to the connection electrode177, which is included in the first connection electrode layer SD1, through a contact hole83penetrating the first planarization insulating layer107. As described above, the connection electrode177may be electrically connected to the drain area of the emission control transistor T6. Therefore, the connection electrode181may be electrically connected to the drain area of the emission control transistor T6.

The second connection electrode layer SD2may include a metal, an alloy, conductive metal oxide, a transparent conductive material, or the like. For example, the second connection electrode layer SD2may include Ag, an alloy containing Ag, Mo, an alloy containing Mo, Al, an alloy containing Al, AlN, W, WN, Cu, Ni, Cr, CrN, Ti, Ta, Pt, Sc, ITO, IZO, or the like. The second connection electrode layer SD2may have a multilayered structure, for example, a two-layer structure of Ti/Al or a three-layer structure of Ti/Al/Ti.

A second planarization insulating layer (108, seeFIG.15) may cover the second connection electrode layer SD2and may be located on the first planarization insulating layer107. The second planarization insulating layer108may include an organic insulating material. For example, the second planarization insulating layer108may include photoresist, BCB, polyimide, HMDSO, PMMA, polystyrene, a polymer derivative having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl-ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or any blend thereof.

A pixel electrode layer PXEL shown inFIG.14may be located over the second planarization insulating layer108. The pixel electrode layer PXEL may include a plurality of pixel electrodes.FIG.14shows a pixel electrode PE1of the first pixel PX1, a pixel electrode PE2of the second pixel PX2, and a pixel electrode PE3of the third pixel PX3. Each of the pixel electrodes PE1, PE2, and PE3may include a first area corresponding to an emission area and a second area surrounding the first area.

The pixel electrode PE1is electrically connected to the connection electrode181of the second connection electrode layer SD2through a contact hole91penetrating the second planarization insulating layer108. Accordingly, the pixel electrode PE1may be electrically connected to the driving transistor T1through the connection electrode181and the emission control transistor T6. The contact hole91may be arranged to correspond to the second area of the pixel electrode PE1.

A pixel-defining layer109may be located on the second planarization insulating layer108to cover edges of the pixel electrode PE1. The pixel-defining layer109includes an opening corresponding to an emission area of each pixel and thus defines the pixels. For reference, the openings in the pixel-defining layer109are not shown in the cross-sectional view ofFIG.15. An emission layer may be arranged in the opening of the pixel-defining layer109, and an opposite electrode CAT may be located on the emission layer. The pixel electrode PE1, the emission layer, and the opposite electrode CAT may form an organic light-emitting diode. The opposite electrode CAT may be integrally formed over a plurality of organic light-emitting diodes and thus may correspond to a plurality of pixel electrodes. For reference, at least one functional layer may be further arranged between the pixel electrode PE1and the emission layer and/or the emission layer and the opposite electrode CAT. Such a functional layer may also be arranged between the pixel-defining layer109and the opposite electrode CAT.

In the case of the display apparatus according to some embodiments, the protrusion of the driving voltage line PL of the second connection electrode layer SD2at least partially overlaps the horizontal connection line BRSH of the first connection electrode layer SD1. In detail, the second protrusion PL5of the protrusion at least partially overlaps the horizontal connection line BRSH.

As described above, the pixel electrode PE1is connected to the connection electrode181, which is included in the second connection electrode layer SD2located under the pixel electrode PE1, through a contact hole. A parasitic capacitance may exist between the connection electrode181and the horizontal connection line BRSH included in the first connection electrode layer SD1under the connection electrode181. As described above with reference toFIG.3, because the horizontal connection line BRSH is connected to the data line DL and configured to transmit the data signal DATA, the data signal DATA may not be accurately transmitted because of the above parasitic capacitance, and thus, the quality of images displayed in the display area DA may degrade.

However, in the case of the display apparatus according to some embodiments, the connection electrode181and the protrusion of the driving voltage line PL of the second connection electrode layer SD2at least partially overlap the horizontal connection line BRSH included in the first connection electrode layer SD1. In detail, as shown in the layout ofFIG.16, in whichFIG.12overlapsFIG.13, and in the cross-sectional view ofFIG.15, the second protrusion PL5of the protrusion at least partially overlaps the horizontal connection line BRSH. Because the second protrusion PL5at least partially shields the horizontal connection line BRSH, and thus, the influence of the connection electrode181on the horizontal connection line BRSH may be prevented or reduced. Therefore, a display apparatus capable of displaying high-quality images may be realized. For example, because the protrusion receives the driving voltage ELVDD, which is the constant voltage, as a portion of the driving voltage line PL, the protrusion may effectively prevent or reduce instances of the horizontal connection line BRSH being affected by the connection electrode181or reduce the influence of the connection electrode181.

For reference, when viewed in the direction perpendicular to the substrate100(e.g., in a plan view or a view that is normal with respect to the display surface), the center of the second protrusion PL5in a widthwise direction (the y-axis direction) is between the center of the horizontal connection line BRSH in a widthwise direction (the y-axis direction) and the connection electrode181, and thus, the shielding effect may be improved.

As described above, an end of the second driving voltage branch PL2(in the −y direction) extending in the second direction (the y-axis direction) is connected to its corresponding one of the driving voltage bodies PL3, but the other end of the second driving voltage branch PL2is apart from the driving voltage bodies PL3. Accordingly, there may be a space between the other end of the second driving voltage branch PL2and the driving voltage body PL3, and the connection electrode181included in the second connection electrode layer SD2may have a portion located in the above space together with the driving voltage line PL. Because the pixel electrode PE1is connected to the connection electrode181through the contact hole91, the contact hole91may be located in the portion of the connection electrode181that is in the space.

Similar to the first driving voltage branch PL1, when an end and the other end of the second driving voltage branch PL2are connected to the driving voltage bodies PL3, and when viewed in the direction perpendicular to the substrate100, the connection electrode181may be entirely arranged between the first driving voltage branch PL1and the second driving voltage branch PL2and closer to the horizontal connection line BRSH. In this case, the parasitic capacitance between the connection electrode181and the horizontal connection line BRSH increases, and thus, the quality of images displayed in the display area DA may degrade as described above.

However, in the display apparatus according to some embodiments, the other end of the second driving voltage branch PL2(in the +y direction) may be apart from the driving voltage bodies PL3, and thus, a portion of the connection electrode181, which is connected to the pixel electrode PE1and corresponds to the contact hole91, may be located in the space between the other end of the second driving voltage branch PL2and the driving voltage bodies PL3, the space being generated because of the separation. Accordingly, the distance between the horizontal connection line BRSH and the connection electrode181may increase, and thus, a display apparatus capable of displaying high-quality images may be realized.

As described above, the lower gate line GIL1(of the third scan line GIL) including the first initialization gate electrode of the first initialization transistor T4is located over the second gate layer GTL2. Because the lower gate line GIL1includes the first initialization gate electrode, the lower gate line GIL1may be referred to as an initialization gate line. The parasitic capacitance may exist between the lower gate line GIL1and the horizontal connection line BRSH included in the first connection electrode layer SD1. As described above with reference toFIG.3, because the horizontal connection line BRSH is connected to the data line DL and configured to transmit the data signal DATA, the data signal DATA may not be accurately transmitted because of the parasitic capacitance, and thus, the quality of images displayed in the display area DA may degrade.

For example, the lower gate line GIL1extending in the first direction (the x-axis direction) periodically turns on or off the first initialization transistor T4. Thus, electrical signals periodically changing flow in the lower gate line GIL1. Therefore, the horizontal connection line BRSH, which is located at a different layer from the lower gate line GIL1, is adjacent to the lower gate line GIL1in a plan view, and extends in the first direction (the x-axis direction), is electrically affected by the lower gate line GIL1. As described above, the horizontal connection line BRSH is electrically connected to the data line DL and configured to transmit the data signal DATA to the data line DL, according to the location of the horizontal connection line BRSH in the display area DA. When the horizontal connection line BRSH is periodically electrically affected by the lower gate line GIL1, the data line DL electrically connected to the horizontal connection line BRSH may also periodically be electrically influenced by the lower gate line GIL1. Such electrical influence eventually causes an unintended brightness change in pixels connected to the data line DL so that the degradation in the image quality of the display apparatus may occur.

However, in the display apparatus according to some embodiments, the second semiconductor layer OACT includes the semiconductor extension layer OACTE extending in the first direction (the x-axis direction) as described above. The semiconductor extension layer OACTE overlaps a portion of the horizontal connection line BRSH included in the first connection electrode layer SD1located over the semiconductor extension layer OACTE. In the layout ofFIG.17in whichFIGS.10and12overlap each other, when viewed in the direction perpendicular to the substrate100, a portion of the horizontal connection line BRSH, which overlaps the semiconductor extension layer OACTE, is located in the semiconductor extension layer OACTE.

In the case of the display apparatus according to some embodiments, the semiconductor extension layer OACTE may shield the horizontal connection line BRSH from the lower gate line GIL1(of the third scan line GIL). Accordingly, the influence of the lower gate line GIL1on the horizontal connection line BRSH may be prevented or reduced. To this end, a display apparatus capable of displaying a high-quality image may be realized. For example, the semiconductor extension layer OACTE may be electrically connected to the first initialization voltage line VIL by the connection electrode175included in the first connection electrode layer SD1. Accordingly, because the first initialization voltage that is the constant voltage is applied to the semiconductor extension layer OACTE, the influence of the lower gate line GIL1on the horizontal connection line BRSH may be effectively prevented or reduced.

As described above, the fourth scan line GBL including the bias gate electrode of the bias transistor T7is in the first gate layer GTL1. The parasitic capacitance may exist between the fourth scan line GBL and the horizontal connection line BRSH included in the first connection electrode layer SD1. As described above with reference toFIG.3, because the horizontal connection line BRSH is connected to the data line DL and configured to transmit the data signal DATA, the data signal DATA may not be accurately transmitted because of the parasitic capacitance, and thus, the quality of images displayed in the display area DA may degrade.

For example, the fourth scan line GBL extending in the first direction (the x-axis direction) periodically turns on or off the bias transistor T7. Thus, electrical signals periodically changing flow in the fourth scan line GBL. Therefore, the horizontal connection line BRSH, which is located at a different layer from the fourth scan line GBL, is adjacent to the fourth scan line GBL in a plan view, and extends in the first direction (the x-axis direction), is electrically affected by the fourth scan line GBL. As described above, the horizontal connection line BRSH is electrically connected to the data line DL and configured to transmit the data signal DATA to the data line DL, according to the location of the horizontal connection line BRSH in the display area DA. When the horizontal connection line BRSH is periodically electrically affected by the fourth scan line GBL, the data line DL electrically connected to the horizontal connection line BRSH may also periodically be electrically influenced by the fourth scan line GBL. Such electrical influence eventually causes an unintended brightness change in pixels connected to the data line DL so that the degradation in the image quality of the display apparatus may occur.

As shown in the layout ofFIG.18, in whichFIG.8overlapsFIG.11, and the cross-sectional view ofFIG.15, in the display apparatus according to some embodiments, the bias voltage line VBL, which is included in the third gate layer GTL3and extends in the first direction (the x-axis direction), overlaps the fourth scan line GBL that may be referred to as a bias gate line.

In the case of the display apparatus according to some embodiments, the bias voltage line VBL may shield the fourth scan line GBL. Accordingly, it may be possible to prevent or reduce instances of the horizontal connection line BRSH being affected by the fourth scan line GBL or reduce the influence of the fourth scan line GBL. To this end, a display apparatus capable of displaying a high-quality image may be realized. For example, because the bias voltage VOBS that is a constant voltage is applied to the bias voltage line VBL, it may be possible to effectively prevent or reduce the influence of the fourth scan line GBL on the horizontal connection line BRSH. For reference, when viewed in the direction perpendicular to the substrate100, the center of the bias voltage line VBL in the widthwise direction (the y-axis direction) is located between the center of the horizontal connection line BRSH in the widthwise direction (the y-axis direction) and the center of the fourth scan line GBL in the widthwise direction (the y-axis direction), and thus, a shielding effect may be improved.

According to the one or more embodiments, a display apparatus capable of displaying high-quality images may be realized. However, the scope of embodiments according to the present disclosure is not limited by the effects.