Single-ended reading circuit

A single-ended reading circuit includes a pre-charger, a high-level maintainer, a first NAND gate, a second NAND gate, a third NAND gate, and an output driver. The first NAND gate has a first input terminal for receiving a pre-charging clock, a second input terminal coupled to a first node, and an output terminal coupled to a second node. The second NAND gate has a first input terminal coupled through a third node to the second node, a second input terminal coupled to a fourth node, and an output terminal coupled to a fifth node. The third NAND gate has a first input terminal coupled to the fifth node, a second input terminal coupled to the first node, and an output terminal coupled to the fourth node.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of China Patent Application No. 201810397959.1 filed on Apr. 28, 2018, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The disclosure generally relates to a single-ended reading circuit, and more specifically, to a single-ended reading circuit with low power-consumption, high speed, and high reliability.

Description of the Related Art

SRAM (Static Random Access Memory) is one type of random access memory. The term “static” means that such memory can keep stored data only if it is powered on. A conventional single-ended reading circuit applicable to SRAM usually operates using both a pre-charging clock and a reading clock. However, the design of conventional single-ended reading circuits tends to have the disadvantages of high power-consumption, many output glitches, and low reliability. Accordingly, there is a need to propose a novel solution for solving the problems of the prior art.

BRIEF SUMMARY OF THE INVENTION

In a preferred embodiment, the invention is directed to a single-ended reading circuit including a pre-charger, a high-level maintainer, a first NAND gate, a second NAND gate, a third NAND gate, and an output driver. The pre-charger and the high-level maintainer are coupled to a bit-line node. The pre-charger and the high-level maintainer are configured to selectively pull up a bit-line voltage at the bit-line node. The first NAND gate has a first input terminal for receiving a pre-charging clock, a second input terminal coupled to a first node, and an output terminal coupled to a second node. The second NAND gate has a first input terminal coupled through a third node to the second node, a second input terminal coupled to a fourth node, and an output terminal coupled to a fifth node. The third NAND gate has a first input terminal coupled to the fifth node, a second input terminal coupled to the first node, and an output terminal coupled to the fourth node. The output driver is coupled to the fourth node, and it generates an output voltage at an output node.

In some embodiments, the pre-charger includes a first P-type transistor. The first P-type transistor has a control terminal for receiving the pre-charging clock, a first terminal coupled to a supply voltage, and a second terminal coupled to the bit-line node.

In some embodiments, the high-level maintainer includes a second P-type transistor, a third P-type transistor, a fourth P-type transistor, and a fifth P-type transistor. The second P-type transistor has a control terminal coupled to a ground voltage, a first terminal coupled to a supply voltage, and a second terminal coupled to a sixth node. The third P-type transistor has a control terminal coupled to the ground voltage, a first terminal coupled to the sixth node, and a second terminal coupled to a seventh node. The fourth P-type transistor has a control terminal coupled to the ground voltage, a first terminal coupled to the seventh node, and a second terminal coupled to an eighth node. The fifth P-type transistor has a control terminal coupled to the fourth node, a first terminal coupled to the eighth node, and a second terminal coupled to the bit-line node.

In some embodiments, the output driver includes an inverter. The inverter has an input terminal coupled to the fourth node, and an output terminal coupled to the output node.

In some embodiments, the first node is directly electrically connected to the bit-line node.

In some embodiments, the third node is directly electrically connected to the second node.

In some embodiments, the output pulling-up capability of the first NAND gate is stronger than the output pulling-down capability of the first NAND gate.

In some embodiments, the output pulling-up capability of the second NAND gate is weaker than the output pulling-down capability of the second NAND gate.

In some embodiments, the output pulling-up capability of the third NAND gate is stronger than the output pulling-down capability of the third NAND gate.

In some embodiments, the output pulling-up capability of the third NAND gate is stronger than the output pulling-up capability of the first NAND gate.

In some embodiments, the single-ended reading circuit further includes an N-type transistor. The N-type transistor has a control terminal for receiving a control clock, a first terminal coupled to the first node, and a second terminal coupled to the bit-line node.

In some embodiments, the control clock and the pre-charging clock are in-phase.

In some embodiments, the single-ended reading circuit further includes a sixth P-type transistor. The sixth P-type transistor has a control terminal for receiving the pre-charging clock, a first terminal coupled to a supply voltage, and a second terminal coupled to the first node.

In some embodiments, the single-ended reading circuit further includes an even number of inverters coupled in series between the second node and the third node.

DETAILED DESCRIPTION OF THE INVENTION

In order to illustrate the purposes, features and advantages of the invention, the embodiments and figures of the invention are described in detail as follows.

FIG. 1is a diagram of a single-ended reading circuit100according to an embodiment of the invention. The single-ended reading circuit100is applicable to SRAM (Static Random Access Memory). As shown inFIG. 1, the single-ended reading circuit100includes a pre-charger101, a high-level maintainer102, a first NAND gate110, a second NAND gate120, a third NAND gate130, and an output driver103. The single-ended reading circuit100can perform a reading operation according to a pre-charging clock CLK, and its detailed operation will be introduced in the following embodiments.

The first NAND gate110has a first input terminal for receiving the pre-charging clock CLK, a second input terminal coupled to a first node N1, and an output terminal coupled to a second node N2. The second NAND gate120has a first input terminal coupled through a third node N3to the second node N2, a second input terminal coupled to a fourth node N4, and an output terminal coupled to a fifth node N5. The third NAND gate130has a first input terminal coupled to the fifth node N5, a second input terminal coupled to the first node N1, and an output terminal coupled to the fourth node N4. An SR-latch is formed by the second NAND gate120and the third NAND gate130. The fourth node N4and the fifth node N5are used as the SR-latch's two locking nodes for storing digital data. The SR-latch is also controlled by the first NAND gate110according to the pre-charging clock CLK. The pre-charger101and the high-level maintainer102are both coupled to a bit-line node NR. The pre-charger101and the high-level maintainer102are configured to selectively pull up a bit-line voltage VR at the bit-line node NR. For example, the pre-charger101may determine whether to pull up the bit-line voltage VR according to the pre-charging clock CLK, and the high-level maintainer102may determine whether to pull up the bit-line voltage VR according to the voltage V4at the fourth node N4, but they are not limited thereto. The output driver103is coupled to the fourth node N4. The output driver103can generate an output voltage VOUT at an output node NOUT according to the voltage V4at the fourth node N4.

It should be noted that the proposed single-ended reading circuit100merely uses the pre-charging clock CLK, but does not use any reading clock (the conventional single-ended reading circuit should use both the pre-charging clock and the reading clock). According to practical measurements, using such a design for the invention helps to reduce the power consumption of the single-ended reading circuit100and increase the operation speed and the reliability of the single-ended reading circuit100. The following embodiments will introduce a variety of different configurations of the single-ended reading circuit100in detail. However, the figures and descriptions of these embodiments are merely exemplary, rather than limitations of the invention.

FIG. 2is a diagram of a single-ended reading circuit200according to an embodiment of the invention. As shown inFIG. 2, the single-ended reading circuit200includes a pre-charger201, a high-level maintainer202, a first NAND gate110, a second NAND gate120, a third NAND gate130, and an output driver203. The circuit connections and functions of the first NAND gate110, the second NAND gate120, and the third NAND gate130have been described in the embodiment ofFIG. 1. In the embodiment ofFIG. 2, the first node N1is directly electrically connected to the bit-line node NR, and the third node N3is directly electrically connected to the second node N2. That is, the first node N1is equivalent to the bit-line node NR, and the third node N3is equivalent to the second node N2.

The pre-charger201includes a first P-type transistor MP1. For example, the first P-type transistor MP1may be a PMOS transistor (P-type Metal Oxide Semiconductor Field Effect Transistor). The first P-type transistor MP1has a control terminal for receiving the pre-charging clock CLK, a first terminal coupled to a supply voltage VDD (e.g., 1V), and a second terminal coupled to the bit-line node NR. In some embodiments, if the pre-charging clock CLK has a low logic level (e.g., a logic “0” or a digit “0”), the pre-charger201will pull up the bit-line voltage VR at the bit-line node NR; conversely, if the pre-charging clock CLK has a high logic level (e.g., a logic “1” or a digit “1”), the pre-charger201will not pull up the bit-line voltage VR at the bit-line node NR.

The high-level maintainer202includes a second P-type transistor MP2, a third P-type transistor MP3, a fourth P-type transistor MP4, and a fifth P-type transistor MP5, which may be coupled in series. For example, each of the second P-type transistor MP2, the third P-type transistor MP3, the fourth P-type transistor MP4, and the fifth P-type transistor MP5may be a respective PMOS transistor. The second P-type transistor MP2has a control terminal coupled to a ground voltage VSS (e.g., 0V), a first terminal coupled to the supply voltage VDD, and a second terminal coupled to a sixth node N6. The third P-type transistor MP3has a control terminal coupled to the ground voltage VSS, a first terminal coupled to the sixth node N6, and a second terminal coupled to a seventh node N7. The fourth P-type transistor MP4has a control terminal coupled to the ground voltage VSS, a first terminal coupled to the seventh node N7, and a second terminal coupled to an eighth node N8. The fifth P-type transistor MP5has a control terminal coupled to the fourth node N4for receiving the voltage V4, a first terminal coupled to the eighth node N8, and a second terminal coupled to the bit-line node NR. In some embodiments, if the voltage V4at the fourth node N4has a low logic level, the high-level maintainer202will pull up the bit-line voltage VR at the bit-line node NR; conversely, if the voltage V4at the fourth node N4has a high logic level, the high-level maintainer202will not pull up the bit-line voltage VR at the bit-line node NR. Although there are merely four P-type transistors MP2, MP3, MP4and MP5displayed inFIG. 2, in other embodiments, the single-ended reading circuit200may include two, three, five, six, seven or more P-type transistors coupled in series according to different requirements.

The output driver203includes an inverter240. The inverter240has an input terminal coupled to the fourth node N4for receiving the voltage V4, and an output terminal coupled to the output node NOUT for outputting the output voltage VOUT. In some embodiments, the voltage V4at the fourth node N4and the output voltage VOUT have complementary logic levels. Other features of the single-ended reading circuit200ofFIG. 2are similar to those of the single-ended reading circuit100ofFIG. 1. Accordingly, these embodiments can achieve similar levels of performance.

FIG. 3is a diagram of waveforms of the single-ended reading circuit200according to an embodiment of the invention. Please refer toFIG. 2andFIG. 3together, so as to understand the operation principles of the invention. Generally, when the pre-charging clock CLK has a low logic level, the single-ended reading circuit200can perform a pre-charging operation to pull up the bit-line voltage VR and maintain the data stored in the SR-latch, and when the pre-charging clock CLK has a high logic level, the single-ended reading circuit200can perform a reading operation to read out digital data corresponding to the bit-line voltage VR. The signal waveforms ofFIG. 3can be divided into a first time interval T1, a second time interval T2, a third time interval T3, and a fourth time interval T4, which will be introduced in detail below.

During the first time interval T1, the pre-charging clock CLK has a high logic level. At this time, the word line of the SRAM is enabled, and a digit “0” is read out from the SRAM. The bit-line voltage VR is discharged to a low logic level. The SR-latch reads out data using the third NAND gate130. It should be noted the data read result of the SR-latch is not affected, regardless of a high or low logic level of the voltage V5at the fifth node N5. Within the first time interval T1, the voltage V4of the fourth node N4has a high logic level, the output voltage VOUT has a low logic level, the voltage V2at the second node N2has a high logic level, and the voltage V5at the fifth node N5has a low logic level.

During the second time interval T2, the pre-charging clock CLK has a low logic level. At this time, the bit-line voltage VR and the voltage V2at the second node N2are both pre-charged to a high logic level. Within the second time interval T2, the SR-latch can maintain the data, and the voltage V5at the fifth node N5, the voltage V4at the fourth node N4, and the output voltage VOUT are unchanged (i.e., the voltage V5still has a low logic level, the voltage V4still has a high logic level, and the output voltage VOUT still has a low logic level; they are the same as those within the first time interval T1).

During the third time interval T3, the pre-charging clock CLK has a high logic level. At this time, the word line of the SRAM is enabled, and a digit “1” is read out from the SRAM. The bit-line voltage VR is kept at a high logic level. The SR-latch reads out the data using the first NAND gate110, the second NAND gate120, and the third NAND gate130. Within the third time interval T3, the voltage V2at the second node N2is transferred from a high logic level to a low logic level, the voltage V5at the fifth node N5is transferred from a low logic level to a high logic level, the voltage V4at the fourth node N4is transferred from a high logic level to a low logic level, and the output voltage VOUT is transferred from a low logic level to a high logic level.

During the fourth time interval T4, the pre-charging clock CLK has a low logic level. At this time, the bit-line voltage VR and the voltage V2at the second node N2are both pre-charged to a high logic level. Within the fourth time interval T4, the SR-latch can maintain the data, and the voltage V5at the fifth node N5, the voltage V4at the fourth node N4, and the output voltage VOUT are unchanged (i.e., the voltage V5still has a high logic level, the voltage V4still has a low logic level, and the output voltage VOUT still has a high logic level; they are the same as those within the third time interval T3).

In some embodiments, the output pulling-up capabilities and the output pulling-down capabilities of the first NAND gate110, the second NAND gate120, and the third NAND gate130are adjustable by appropriately designing their transistor sizes. The so-called “output pulling-up capability” means the NAND gate's driving capability in pulling up its output terminal voltage, and the so-called “output pulling-down capability” means the NAND gate's driving capability in pulling down its output terminal voltage. If the driving capability is stronger, it will take the NAND gate shorter time to pull up or pull down its output terminal voltage. For example, the output pulling-up capability of the first NAND gate110may be stronger than the output pulling-down capability of the first NAND gate110; the output pulling-up capability of the second NAND gate120may be weaker than the output pulling-down capability of the second NAND gate120; the output pulling-up capability of the third NAND gate130may be stronger than the output pulling-down capability of the third NAND gate130; the output pulling-up capability of the third NAND gate130may be stronger than the output pulling-up capability of the first NAND gate110. According to practical measurements, the design of the above transistor sizes helps to eliminate the output glitches of the single-ended reading circuit200, thereby reducing the whole power consumption.

It should be noted that the single-ended reading circuit100(or200) can operate according to only the pre-charging clock CLK, without using any reading clock. Such a design can reduce the non-ideal difference between the pre-charging clock CLK and the reading clock, thereby enhancing the reliability of the single-ended reading circuit100(or200). In addition, since the reading-in to reading-out operation of the single-ended reading circuit100(or200) uses only two circuit stages, the operation speed of the single-ended reading circuit100(or200) is further improved.

TABLE IComparison of Single-ended Reading Circuit's Powerconsumption Between Conventional Design and the InventionAlternately reading aContinuouslyUnit: μAdigit “1” and a digit “0”reading two digits “0”The Invention67.46348.945Conventional Design89.884136.656

According to the measurements of Table I and Table II, it should be understood that the power consumption of the single-ended reading circuit100(or200) of the invention is reduced by about 50% compared to that of the conventional design, and the operation speed of the single-ended reading circuit100(or200) of the invention is increased by about 10% compared to that of the conventional design. Therefore, the design of the invention can significantly improve a variety of performance indicators of the single-ended reading circuit100(or200).

FIG. 4is a diagram of a single-ended reading circuit400according to an embodiment of the invention.FIG. 4is similar toFIG. 2. In the embodiment ofFIG. 4, the single-ended reading circuit400further includes an N-type transistor MN1and a sixth P-type transistor MP6. For example, the N-type transistor MN1may be an NMOS transistor (N-type Metal Oxide Semiconductor Field Effect Transistor), and the sixth P-type transistor MP6may be a PMOS transistor. The N-type transistor MN1has a control terminal for receiving a control clock CCK, a first terminal coupled to the first node N1, and a second terminal coupled to the bit-line node NR. In some embodiments, the control clock CCK and the pre-charging clock CLK are in-phase, and only a small time difference may exist between them. The sixth P-type transistor MP6has a control terminal for receiving the pre-charging clock CLK, a first terminal coupled to the supply voltage VDD, and a second terminal coupled to the first node N1. The N-type transistor MN1may be used as a multiplexer, and the sixth P-type transistor MP6may be used as an additional pre-charger. According to practical measurements, the incorporation of the N-type transistor MN1and the sixth P-type transistor MP6helps to further increase the reliability of the single-ended reading circuit400. Other features of the single-ended reading circuit400ofFIG. 4are similar to those of the single-ended reading circuits100and200ofFIGS. 1 and 2. Accordingly, these embodiments can achieve similar levels of performance.

FIG. 5is a diagram of a single-ended reading circuit500according to an embodiment of the invention.FIG. 5is similar toFIG. 4. In the embodiment ofFIG. 5, the single-ended reading circuit500further includes an even number of inverters551and552, which are coupled in series between the second node N2and the third node N3. Specifically, the inverter551has an input terminal coupled to the second node N2, and an output terminal; the inverter552has an input terminal coupled to the output terminal of the inverter551, and an output terminal coupled to the third node N3. The aforementioned inverters551and552are used as a delay unit. Although there are merely two inverters551and552displayed inFIG. 5, in other embodiments, the single-ended reading circuit500may include four, six, eight, or more inverters coupled in series according to different requirements. According to practical measurements, the incorporation of the aforementioned inverters551and552helps to eliminate the output glitches of the single-ended reading circuit500and reduce the power consumption of the single-ended reading circuit500. Other features of the single-ended reading circuit500ofFIG. 5are similar to those of the single-ended reading circuits100,200and400ofFIGS. 1, 2 and 4. Accordingly, these embodiments can achieve similar levels of performance.

Note that the above voltages, currents, resistances, inductances, capacitances and other element parameters are not limitations of the invention. A designer can adjust these parameters according to different requirements. The single-ended reading circuit of the invention is not limited to the configurations ofFIGS. 1-5. The invention may merely include any one or more features of any one or more embodiments ofFIGS. 1-5. In other words, not all of the features displayed in the figures should be implemented in the single-ended reading circuit of the invention. Although the embodiments of the invention use MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as examples, the invention is not limited thereto, and those skilled in the art may use other types of transistors such as BJT (Bipolar Junction Transistor), JFET (Junction Gate Field Effect Transistor), FinFET (Fin Field Effect Transistor), etc.

It will be apparent to those skilled in the art that various modifications and variations can be made in the invention. It is intended that the standard and examples be considered exemplary only, with the true scope of the disclosed embodiments being indicated by the following claims and their equivalents.