Printhead with a memristor

In an example, a printhead includes a memristor, in which the memristor may include a first electrode, a second electrode positioned in a crossed relationship with the first electrode to form a junction, and a switching element positioned at the junction between the first electrode and the second electrode, in which the switching layer includes a via formed in the switching element to reduce an area of the switching element.

BACKGROUND

A memristor may generally be defined as an electrically actuated apparatus formed of a pair of spaced apart electrodes with a switching element positioned between the electrodes. Memristors are able to change the value of their resistances in response to various programming conditions and are able to exhibit a memory of past electrical conditions. For instance, memristors may be programmed to respectively represent a logical “1” or ON while in a low resistance state and a logical “0” or OFF while in a high resistance state and may retain these states. Particularly, the resistance state of the switching element may be changed through application of a current, in which the current may cause mobile dopants in the switching element to move, which may alter the electrical operation of the memristor. After removal of the current, the locations and characteristics of the dopants remain stable until the application of another programming electrical field. The state of the memristor may be read by applying a lower reading voltage across the switching element which allows the internal electrical resistance of the memristor to be sensed but does not generate a sufficiently high electrical field to cause significant dopant motion.

DETAILED DESCRIPTION

Generally speaking, the overall current required to change the resistance state of a switching element in a memristor may have a relatively strong correlation to the size of the memristor. That is, the larger the memristor, and thus the switching element, the larger the current that is required to change the resistance state of the switching element. Relatively high current requirements may make it difficult to switch the switching element to the low resistance state because the memristor may have a relatively small resistance. This issue may be exacerbated when a conduction path in the switching element has certain parasitic resistance. In addition, the voltage divider effect may lead to small voltage drops across the memristor, which may lead to the memristor being stuck at the ON state.

The minimum size that the memristor, and thus the switching element, may have may be limited by the minimum technology critical dimension. The minimum technology critical dimension may be defined as the smallest dimension that may be attained using currently available fabrication techniques. In addition, or alternatively, the minimum technology critical dimension may be defined as the smallest dimension that may be attained using fabrication techniques that do not require a substantial capital investment to modify the fabrication techniques, such as by fabricating new tools. By way of particular example, the technology is lithography and the minimum size of the memristor may be about 2.6 μm × about 2.6 μm.

Disclosed herein is a printhead that includes a memristor, in which the memristor includes a switching element that has a via, in which the via enables the switching element to have an area that is smaller than the area attainable at the minimum technology critical dimension. In other words, the area of the memristor, and particularly, the area of the switching element, disclosed herein breaks through the minimum technology critical dimension area limit without requiring a substantial capital investment to increase the ability of lithographic techniques to further minimize the attainable size. As discussed in greater detail herein, the area of the switching element may be made to be smaller than the minimum technology critical dimension area limit through formation of the via in the switching element. The switching element may be formed to have dimensions that are relatively larger than the minimum technology critical dimension while the via may be formed to have dimensions at or around the minimum technology critical dimension limit. In this regard, both the switching element and the via may be formed in compliance with the minimum technology critical dimension, but the area of the switching element may be made to be smaller than the area attainable in compliance with the minimum technology critical dimension limit.

According to an example, a crossbar memory array may be formed with a plurality of the memristors disclosed herein. The crossbar memory array may be integrated in or on a printhead.

With reference first toFIG. 1, there is shown a perspective view of a cartridge100, according to an example. It should be understood that the cartridge100depicted inFIG. 1may include additional components and that some of the components described herein may be removed and/or modified without departing from a scope of the cartridge100. It should also be understood that the cartridge100depicted inFIG. 1may not be drawn to scale and thus, the cartridge100may have a different size and/or configuration other than as shown therein.

As shown inFIG. 1, the cartridge100includes a host102on which electrical contacts104and a printhead106are positioned. The cartridge100may house a fluid supply chamber that stores fluid, such as ink, for delivery onto a media through nozzles108in the printhead106. Although not shown, actuating mechanisms may be positioned with respect to the nozzles108to cause the fluid to be ejected through the nozzles108. The actuating mechanisms may be thermal resistors, piezoelectric actuators, etc. In addition, the electrical contacts104may carry electrical signals to and from a controller (not shown) to controllably actuate the actuating mechanisms and cause the fluid to be ejected through the nozzles108in a controlled manner. According to various examples, the cartridge100may be used in a printing system, such as a thermal inkjet printer, a piezoelectric printer, a facsimile machine, a multifunction machine, etc.

As discussed in greater detail herein a memory device (not shown) may be incorporated or integrated with the printhead106, such as by being on-chip with the printhead106. The memory device may be a non-volatile erasable programmable read only memory (EPROM), a non-volatile electrically erasable programmable read-only memory (EEPROM), or the like. In addition, the memory device may store information regarding the cartridge100, such as information that may be used in authenticating the cartridge100, information that may be used for marketing purposes, etc. By way of particular example, the memory device may store any of an identification number, part of a secret code, manufacturing information, etc.

The memory device may be communicatively connected to the electrical contacts104and a controller may access the information stored in the memory device through the electrical contacts104. It should, however, be understood that the information contained in the memory device may be accessed in other manners, such as through a direct connection to the memory device, through a wireless communication mechanism (e.g., radio frequency identification), etc. In addition, although the memory device is depicted as being positioned on a particular section of the host102, it should be understood that the memory device may be positioned at other locations with respect to the host102, including within the host102.

As discussed in greater detail below, the memory device may include a crossbar memory array in which a plurality of memristors are formed at multiple junctions of the crossbar memory array. An example of a crossbar memory array200that the memory device may include is depicted inFIG. 2. Particularly,FIG. 2depicts a perspective view of a portion of a crossbar memory array200, according to an example. It should be understood that the crossbar memory array200depicted inFIG. 2may include additional components and that some of the components described herein may be removed and/or modified without departing from a scope of the crossbar memory array200. In other examples, the memory device may include a 1T1M structure instead of the crossbar structure depicted inFIG. 2.

As shown inFIG. 2, the crossbar memory array200includes a first layer210formed of a plurality of first electrodes212and a second layer220formed of a plurality of second electrodes222. The first electrodes212are depicted as extending along a first plane and the second electrodes222are depicted as extending along a second plane, in which the second plane is parallel or nearly parallel to the first plane.

The first electrodes212and the second electrodes222are also depicted as being in a crossed relationship with respect to each other such that junctions230are formed at intersections between respective pairs of the first electrodes212and second electrodes222. That is, the first electrodes212are depicted as extending in a direction that is perpendicular to the direction in which the second electrodes222extend. According to an example, the second electrodes222may be substantially perpendicular to the first electrodes212, e.g., there may be less than about a 5° of rotation difference between the first electrodes212and the second electrodes222.

The second electrodes222are further depicted as being in a spaced relationship with respect to the first electrodes212such that a gap exists between the first electrodes212and the second electrodes222. In addition, switching elements232are depicted as being positioned at the junctions230at which the second electrodes222cross the first electrodes212. The switching elements232and the sections of the first electrodes212and the second electrodes222around the switching elements232may form respective memristors. In addition, as discussed in greater detail below, a via may be formed in each of the switching elements to reduce an area of the switching element. Moreover, the via may be formed to extend through either or both of the first and second electrodes212,222.

The first electrodes212may be formed of an electrically conductive material, such as AlCu, AlCuSi, AlCuSi with a barrier layer, such as TiN, or the like. The second electrodes222may be formed of any of the example materials listed for the first electrodes212. In addition, the second electrodes222may be formed of the same or different materials as compared with the first electrodes212. The second electrodes222may be formed of an electrically conductive material, such as TaAl, WSiN, AlCu combination, or the like. The switching elements232may be formed of switching oxides, such as a metallic oxide. Specific examples of switching oxide materials may include magnesium oxide, titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, manganese oxide, iron oxide, cobalt oxide, copper oxide, zinc oxide, aluminum oxide, gallium oxide, silicon oxide, germanium oxide, tin dioxide, bismuth oxide, nickel oxide, yttrium oxide, gadolinium oxide, and rhenium oxide, among other oxides. In addition to the binary oxides presented above, the switching oxides may be ternary and complex oxides such as silicon oxynitride. The oxides presented may be formed using any of a number of different processes such as sputtering from an oxide target, reactive sputtering from a metal target, atomic layer deposition (ALD), oxidizing a deposited metal or alloy layer, etc.

Turning now toFIG. 3A, there is shown a cross-sectional side view of a circuit component300including a memristor310, according to an example. It should be understood that the circuit component300depicted inFIG. 3Amay include additional components and that some of the components described herein may be removed and/or modified without departing from a scope of the circuit component300.

The circuit component300may represent a junction230in the crossbar memory array200depicted inFIG. 2.FIG. 3Amay thus depict one of the junctions230depicted inFIG. 2along with other circuit elements. In this regard, each or a plurality of the junctions230in the crossbar memory array200may include the features depicted in the circuit component300.

As shown inFIG. 3A, the circuit component300includes a memristor310having a first electrode212, a second electrode222, and a switching element232. A via312is also depicted as extending through the first electrode212, the switching element232, and the second electrode222. The via312may extend through a central portion of the switching element232as shown inFIG. 3B, which shows a top view of the memristor310with the second electrode222removed, according to an example. As shown inFIG. 3B, the via312may have a width L, in which the width L is a size that is equivalent to a technology critical dimension. That is, the width L may be equivalent to a minimum size that is attainable by a current technology, without requiring relatively expensive retooling. For instance, the technology critical dimension may be the smallest size attainable through current lithography processes, without requiring that a relatively large amount of money, e.g., millions of dollars, be spent to attain a smaller size.

In addition, the switching element232may have a width that is larger than the technology critical dimension. InFIG. 3B, the switching element232is depicted as having a width that is larger than the dimension L, i.e., the width of the switching element232is depicted as being a*L, which may be the same width for the switching element232. According to an example, the value for the variable “a” may be a value that causes the effective area of the switching element232with the via to be less than the area L×L. In other words, through formation of the via312into the switching element232, the area over which a current flows through the switching element232may be made to be smaller than is possible through conventional lithographic processes due to the technology critical dimension limitation. In addition, the variable “a” may have a sufficiently large value to enable the switching element232to have a sufficiently large area for the switching element232to switch from an “off” to an “on” state and for that information to be read from the switching element232. By way of particular example, “a” may be equal to a value that is between approximately 1.2 and approximately 1.4.

According to an example, the first electrode212, the second electrode222, and the switching element232may each have a width equal to a×L to substantially minimize the size the of the memristor310, while also enabling for the formation of the via312having the width L. However, the first electrode212and the second electrode222may have lengths that are substantially larger than a×L, for instance, to form a crossbar memory array200.

According to a further example, the via312may be filled with a dielectric material314, such as silicon dioxide, silicon nitride, silicon carbide, SiC with SiN, or the like.

With reference back toFIG. 3A, the circuit component300may also include additional components including transistors and resistors to enable the memristor310to be electrically addressed and programmed. For instance, the circuit component300may include a substrate320, which may be doped to be a p-type semiconductor, semiconductors322and324, which may be doped to be n-type semiconductors, and a poly326. The circuit component300may also include a glass layer328, which may be formed of, for instance, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. The circuit component300may further include a tetraethyl orthosilicate (TEOS) layer330and a passivation layer332. The TEOS layer330may serve as an inter-layer dielectric layer between the first electrode212and the second electrode222for electrical isolation. In addition, the TEOS layer330may provide planarization functions to mitigate topography differences. The passivation layer332may be formed of silicon carbide (SiC), silicon nitride (SiN), or the like.

Although the switching element232is depicted in the figures as being in direct contact with the first electrode212and the second electrode222, in other examples, an additional layer or additional layers may be provided between the switching element232and either or both of the first electrode212and the second electrode222. The additional layer(s) may be provided to enhance switching characteristics and/or operation of the memristor310and may be, for instance, TiN, TaN, or the like. In any regard, the via312may extend through the additional layer(s).

With reference now toFIG. 4, there is shown a cross-sectional side view of a circuit component400including a memristor410, according to another example. It should be understood that the circuit component400depicted inFIG. 4may include additional components and that some of the components described herein may be removed and/or modified without departing from a scope of the circuit component400.

The circuit component400depicted inFIG. 4includes all of the same elements as those depicted in the circuit component300depicted inFIG. 3A. The circuit component400differs from the circuit component300depicted inFIG. 3in that the via312extends through the second electrode222and the switching element232without extending through the first electrode212.

Turning now toFIG. 5, there is shown a flow diagram of a method500for fabricating a printhead106, according to an example. It should be understood that the method500depicted inFIG. 5may include additional operations and that some of the operations described herein may be removed and/or modified without departing from a scope of the method500. Although the method500describes a process in which printhead including a memristor310,410is fabricated, with particular discussion of the memristor fabrication, it should be understood that the memristor410may be fabricated along with the other components of the circuit component300,400as shown inFIGS. 3A and 4A. Thus, for instance, the other components of the circuit components300,400may be fabricated before, during, and/or after the processes discussed below with respect to the method500. In addition, the method500may be repeated as desired or needed to form a crossbar memory array200composed of multiple memristors310,410on or in the printhead106.

At block502, a first electrode212may be provided. The first electrode212may be provided, e.g., formed, through any suitable formation process, such as, chemical vapor deposition, sputtering, etching, lithography, etc. As discussed above, the first electrode212may be formed of an electrically conductive material such as AlCu, AlCuSi, AlCuSi with a barrier layer, such as TiN, or the like.

At block504, a switching element232may be provided over the first electrode212. The switching element232may be provided, e.g., formed, through any suitable formation process, such as, through sputtering, pulse laser deposition, atomic layer deposition, etc. As discussed above, the switching element232may be provided through use of sputtering from an oxide target, reactive sputtering from a metal target, atomic layer deposition (ALD), oxidizing a deposited metal or alloy layer, etc. As also discussed above, the switching element232may be formed to have dimensions that are larger than a lithography minimum technology critical dimension. Likewise, the first electrode212and the second electrode222may also have widths that are larger than the lithography minimum technology critical dimension.

At block506, a second electrode222may be provided over the switching element232. The second electrode222may be provided, e.g., formed, through a formation process, such as E-beam evaporation, chemical vapor deposition, sputtering, atomic layer deposition, etching, (imprint) lithography, etc. Following block508, a memristor310,410may be formed.

At block508, a via312may be formed through the second electrode222and the switching element232. The via312may be formed through any suitable combined process of lithography and etching processes, including dry etching and wet etching. As discussed above, the size of the via312may be limited by the lithographic technology critical dimension. As such, the via312may be formed to have dimensions that are substantially equal to the lithography minimum technology critical dimension. For instance, the via312may be formed to have dimensions that are equal to the lithography minimum technology critical dimension or less than about 10% of the lithography minimum technology critical dimension.

At block510, the memristor310,410may be incorporated onto a printhead106. The memristor310,410may be incorporated onto the printhead106in any of the manners discussed above with respect toFIG. 1. For instance, a plurality of memristors310,410may be formed into an array, such as the crossbar memory array200depicted inFIG. 2, and the array may be incorporated into a memory device, which is integrated onto the printhead106. According to an example, block510may be omitted, for instance, when the memristor310,410is formed directly on or with the printhead106.

According to an example, instead of forming the via312through only the second electrode222and the switching element232at block508, the via312may also be formed through the first electrode212, as shown inFIG. 3A. In this example, at block508, the via312may be formed through the second electrode222, the switching element232, and the first electrode212.

According to another example, the via312may be filled with a dielectric layer314, for instance, to prevent undesired particles from being deposited into the via312.