Method for manufacturing semiconductor substrate

It is an object to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide. The method for manufacturing a semiconductor device includes the steps of performing carbonization treatment on a surface of a silicon substrate to form a silicon carbide layer; adding ions to the silicon substrate to form an embrittlement region in the silicon substrate; bonding the silicon substrate and a base substrate with insulating layers interposed between the silicon substrate and the base substrate; heating the silicon substrate and separating the silicon substrate at the embrittlement region to form a stacked layer of the silicon carbide layer and a silicon layer over the base substrate with the insulating layers interposed between the base substrate and the stacked layer; and removing the silicon layer to expose a surface of the silicon carbide layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

A technical field of the present invention relates to a method for manufacturing a semiconductor substrate.

2. Description of the Related Art

It is known that silicon carbide as a semiconductor material is more advantageous than silicon in terms of increasing the withstand voltage of a semiconductor element (for example, a transistor), reducing a loss of electric power, or the like. Therefore, it is expected that silicon carbide is used for practical application of a transistor for electric power.

The cost of a silicon carbide substrate itself is the biggest problem for realizing the semiconductor element using silicon carbide. It is difficult to melt silicon carbide because of its characteristics; therefore, the silicon carbide substrate cannot be manufactured by a Czochralski (CZ) method or the like which are used for manufacturing a silicon substrate. Therefore, a sublimation recrystallization method which is disadvantageous in terms of productivity has to be used for manufacturing a silicon carbide substrate for application of semiconductor (for example, see Patent Document 1 and Patent Document 2). The sublimation recrystallization method is a method in which a material is sublimated by heating and single-crystal silicon carbide is grown on seed crystal; therefore, there are problems in that a device in which the sublimation recrystallization method is performed at a very high temperature of 2000° C. to 3000° C. is needed and it is difficult to increase an area of the silicon carbide substrate.

Moreover, there is also a problem in that the silicon carbide substrate has defects called micropipes. The micropipes are hollow-core defects with a diameter of about 1 μm to 3 μm. If the micropipes exist in a semiconductor element, conductive defect occurs locally, and as a result, operation defect of a semiconductor element occurs. Other than the micropipes, there are also problems such as dislocation or the like.

After all, although a semiconductor element having a silicon carbide is expected to be high performance device, its commercialization is delayed in practice due to low productivity and low quality of crystals.

SUMMARY OF THE INVENTION

In view of the foregoing problems, an object of one embodiment of the present invention disclosed in this specification and the like (at least including claims, specification, and drawings) is to provide a novel manufacturing method of a semiconductor substrate having silicon carbide.

One embodiment of the present invention disclosed in this specification and the like is to perform carbonization treatment on a surface of a silicon substrate so as to form a silicon carbide layer and manufacture a semiconductor substrate by using the silicon carbide layer.

For example, one embodiment of the present invention disclosed in this specification and the like is a method for manufacturing a semiconductor device including the steps of performing carbonization treatment on a surface of a silicon substrate to form a silicon carbide layer; adding ions to the silicon substrate to form an embrittlement region in the silicon substrate; bonding the silicon substrate to a base substrate with insulating layers interposed therebetween; heating the silicon substrate and separating the silicon substrate at the embrittlement region to form a stacked layer structure of the silicon carbide layer and a silicon layer over the base substrate with the insulating layers interposed therebetween; and removing the silicon layer to expose a surface of the silicon carbide layer.

In addition, another embodiment of the present invention disclosed in this specification and the like is a method for manufacturing a semiconductor device including the steps of performing carbonization treatment on a surface of a silicon substrate to form a silicon carbide layer; adding ions to the silicon substrate to form an embrittlement region in the silicon substrate; bonding the silicon substrate to a base substrate with insulating layers interposed therebetween; heating the silicon substrate and separating the silicon substrate at the embrittlement region to form a stacked layer structure of the silicon carbide layer and a silicon layer over the base substrate with the insulating layers interposed therebetween; removing the silicon layer to expose a surface of the silicon carbide layer; and thickening the silicon carbide layer by an epitaxial growth method.

Moreover, in the above description, it is preferable that the silicon layer is removed after the silicon layer is oxidized.

Further, another embodiment of the present invention disclosed in this specification and the like is a method for manufacturing a semiconductor device including the steps of performing carbonization treatment on a surface of a silicon substrate to form a silicon carbide layer; adding ions to the silicon substrate to form an embrittlement region in the silicon substrate; bonding the silicon substrate to a base substrate with insulating layers interposed therebetween; heating the silicon substrate and separating the silicon substrate at the embrittlement region to form a stacked layer structure of the silicon carbide layer and a silicon layer over the base substrate with the insulating layers interposed therebetween; and oxidizing the silicon layer to form a stacked layer structure of the silicon carbide layer and a silicon oxide layer.

Note that, in the above description, it is preferable that the carbonization treatment contains any of heat treatment or laser light irradiation treatment under a carbon-containing atmosphere, heat treatment or laser light irradiation treatment after a thin film containing carbon is formed on the surface of the silicon substrate, or heat treatment or laser light irradiation treatment after liquid containing carbon is applied on the surface of the silicon substrate.

In addition, in the above description, a conductive layer may be formed on the silicon carbide layer after the silicon carbide layer is formed and before the silicon substrate and the base substrate are bonded to each other.

By using the above semiconductor substrate, various semiconductor elements and a semiconductor device including the various semiconductor elements can be manufactured.

In one embodiment of the disclosed invention, a silicon carbide layer is formed by using a silicon substrate. Accordingly, a semiconductor substrate including silicon carbide can be provided at very low cost. In addition, a silicon substrate which is to be a silicon carbide layer can be reused; therefore, manufacturing cost can be further reduced.

Moreover, since a semiconductor substrate having a silicon carbide layer over an insulating layer can be provided, characteristics of a semiconductor element can be improved by using this. That is, characteristics of a semiconductor device using the semiconductor element can be improved.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the description of the embodiments, and it is apparent to those skilled in the art that modes and details can be modified in various ways without departing from the spirit of the present invention disclosed in this specification and the like. In addition, structures in different embodiments can be implemented by combination appropriately. In structures of the invention described below, a reference numeral indicating the same part or a similar function is used in common throughout different drawings, and the repeated description is omitted.

This embodiment describes an example of a method for manufacturing a semiconductor substrate according to one embodiment of the disclosed invention with reference toFIGS. 1A to 1G, andFIGS. 2A and 2B. First, an example of a basic method for manufacturing a semiconductor substrate will be described with reference toFIGS. 1A to 1G

<Method for Manufacturing Semiconductor Substrate1>

First, a base substrate100is prepared (seeFIG. 1A). As the base substrate100, although it is preferable to use a substrate with a high heat resistance, such as a quartz substrate, an alumina substrate, and a silicon substrate, a light-transmitting glass substrate used for liquid crystal display devices or the like can be used. A substrate having a strain point of greater than or equal to 580° C. (preferably greater than or equal to 600° C.) may be used as the glass substrate. In terms of the heat resistance, it is preferable to use a substrate having the strain point as high as possible. Further, it is preferable that the glass substrate be a non-alkali glass substrate. As a material of the non-alkali glass substrate, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used, for example.

Note that, as the base substrate100, as well as the above substrate, a substrate which is formed with an insulator, such as a ceramic substrate or a sapphire substrate; a substrate which is formed with a semiconductor such as germanium or a silicon germanium; a substrate which is formed with a conductor such as stainless steel; or the like can be used.

Next, an insulating layer102is formed over the base substrate100(seeFIG. 1A). A method for forming the insulating layer102is not particularly limited to a certain method, and for example, a sputtering method, a plasma CVD method, or the like can be used. In addition, the thermal oxidation treatment may be used for forming the insulating layer102. The insulating layer102is a layer having a surface for bonding; therefore, the surface preferably has high planarity. The insulating layer102can be formed using one or more materials selected from silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, and the like. For example, in the case where the insulating layer102is formed using silicon oxide, the insulating layer102which is extremely superior in planarity can be obtained by a chemical vapor deposition method with the use of an organosilane gas. Note that the insulating layer102may have a single-layer structure or a stacked layer structure.

Note that in this specification and the like, oxynitride refers to a substance that contains more oxygen (atoms) than nitrogen (atoms). For example, silicon oxynitride is a substance including oxygen, nitrogen, silicon, and hydrogen in ranges of greater than or equal to 50 at. % and less than or equal to 70 at. %, greater than or equal to 0.5 at. % and less than or equal to 15 at. %, greater than or equal to 25 at. % and less than or equal to 35 at. %, and greater than or equal to 0.1 at. % and less than or equal to 10 at. %, respectively. Further, nitride oxide refers to a substance that contains more nitrogen (atoms) than oxygen (atoms). For example, a silicon nitride oxide is a substance including oxygen, nitrogen, silicon, and hydrogen in ranges of greater than or equal to 5 at. % and less than or equal to 30 at. %, greater than or equal to 20 at. % and less than or equal to 55 at. %, greater than or equal to 25 at. % and less than or equal to 35 at. %, and greater than or equal to 10 at. % and less than or equal to 25 at. %, respectively. Note that the above ranges are obtained by measurement using Rutherford Backscattering Spectrometry (RBS) or Hydrogen Forward Scattering (HFS). Moreover, the total of the percentages of the constituent elements does not exceed 100 at. %.

Next, a silicon substrate110is prepared (seeFIG. 1B). A single-crystal silicon substrate, a polycrystalline silicon substrate and the like are silicon substrates, and any type of silicon substrate can be used for the silicon substrate. This embodiment describes the case where the single-crystal silicon substrate is used as the silicon substrate110. Note that a substrate formed of a material other than silicon may also be used as long as a material which combines with carbon to form carbide semiconductor is used. For example, a germanium substrate, a silicon germanium substrate, or the like may be used.

Although there is no limitation on the size of the silicon substrate110, for example, a circular silicon substrate having a diameter of 8 inches (200 mm), 12 inches (300 mm), or 18 inches (450 nm) can be used. In addition, the circular silicon substrate may be processed into a rectangular shape for being used as the silicon substrate110. Note that in this specification and the like, the term “single-crystal” indicates a crystal which has a regular crystal structure and crystal axes oriented in the same direction in all portions of the crystal. Note that, it is not a matter of how many defects there are.

Next, a silicon carbide layer112is formed on the surface of the silicon substrate110by carbonization treatment (seeFIG. 1B). Although there are various kinds of carbonization treatment, for example, heat treatment or laser light irradiation treatment under a carbon-containing atmosphere, heat treatment or laser light irradiation treatment after a thin film containing carbon is formed on the surface of the silicon substrate, heat treatment or laser light irradiation treatment after liquid containing carbon is applied on the surface of the silicon substrate, or the like can be applied.

As the heat treatment under a carbon-containing atmosphere, for example, there is heat treatment under a mixed atmosphere of hydrogen and a hydrocarbon gas such as methane or propane. The heat treatment may be performed at temperatures of 1000° C. to 1300° C., preferably 1100° C. to 1250° C. The silicon substrate110is impregnated with carbon from the surface to the depth of about 20 nm by this treatment, and the silicon carbide layer112is formed.

As the laser light irradiation treatment under a carbon-containing atmosphere, for example, there is laser light irradiation treatment under a mixed atmosphere of hydrogen and a hydrocarbon gas such as methane or propane. In this case, it is preferable that the laser light be delivered in a manner such that at least a surface portion of the silicon substrate110melts. Note that in the case of performing the laser light irradiation treatment while heating the silicon substrate110at 500° C. to 1000° C., there is an advantage that the silicon carbide layer112is formed easily.

Note that the above-mentioned heat treatment can be performed using a heat treatment apparatus such as a rapid thermal anneal (RTA), a furnace, a millimeter wave heating device, or the like. As a heating method of the heat treatment apparatus, a resistance heating method, a lamp heating method, a gas heating method, a radio wave heating method, and the like can be given. The heat treatment may be performed by thermal plasma jet irradiation or the like.

In addition, a pulsed laser from which a high-energy laser light is easily obtained is preferably used for the above laser light irradiation treatment. The repetition rate is preferably about greater than or equal to 1 Hz and less than or equal to 10 MHz, more preferably greater than or equal to 10 Hz and less than or equal to 1 MHz. As the pulsed laser, an Ar laser, a Kr laser, an excimer (ArF, KrF, or XeCl) laser, a CO2laser, a YAG laser, a YVO4laser, a YLF laser, a YAlO3laser, a GdVO4laser, a Y2O3laser, a ruby laser, an alexandrite laser, a Ti:sapphire laser, a copper vapor laser, a gold vapor laser, or the like can be used. Note that the laser light is not limited to the pulsed laser, and a continuous-wave laser may be used. Example of the continuous-wave laser include an Ar laser, a Kr laser, a CO2laser, a YAG laser, a YVO4laser, a YLF laser, a YAlO3laser, a GdVO4laser, a Y2O3laser, a ruby laser, an alexandrite laser, a Ti:sapphire laser, a helium-cadmium laser, and the like. Note that a wavelength of the laser light is needed to be a wavelength which is absorbed into the silicon substrate110. For example, when the silicon substrate110is a single-crystal silicon substrate, laser light having a wavelength of greater than or equal to 250 nm and less than or equal to 700 nm may be used.

After the silicon carbide layer112is formed as described above, treatment (planarization treatment) to reduce surface unevenness of the silicon carbide layer112may be performed. As the treatment, one of a dry etching process or a wet etching process or a combination of both of the etching processes may be performed. Alternatively, polishing treatment such as a chemical mechanical polishing (CMP) or the like may be performed. In addition, a combination of both the etching process and the polishing treatment may be performed.

A thickness of the silicon carbide layer112is not particularly limited, but for example, the silicon carbide layer112may be formed with a thickness of greater than or equal to 1 nm and less than or equal to 100 nm. In the case where a thicker silicon carbide layer is preferred, it is possible to make the silicon carbide layer thick by performing epitaxial growth method or the like. In addition, there is no particular limitation on crystallinity of the silicon carbide layer112, and the silicon carbide layer112can have any of single-crystal, polycrystalline, or amorphous structures. Note that in this embodiment, a single-crystal silicon substrate is used as the silicon substrate110and therefore, a single-crystal silicon carbide layer can be formed as the silicon carbide layer112.

Next, by adding ions to the silicon substrate110after the silicon carbide layer112is formed, an embrittlement region114is formed (seeFIG. 1C). More specifically, for example, an ion beam including ions accelerated by an electric field is delivered to form the embrittlement region114at a predetermined depth from a surface of the silicon substrate110(more precisely, a surface of the silicon carbide layer112formed on the silicon substrate110). The depth of the region where the embrittlement region114is formed is controlled by the accelerating energy of the ion beam and the incidence angle the ion beam. Note that, the embrittlement region114is formed in a region at a depth the same or substantially the same as the average penetration depth of the ions.

Depending on the depth at which the embrittlement region114is formed, the thickness of the semiconductor layer which is separated from the silicon substrate110is determined. The depth where the embrittlement region114is formed is greater than or equal to 50 nm and less than or equal to 1 μm from the surface of the silicon substrate110, and is preferably greater than or equal to 50 nm and less than or equal to 300 nm.

At the time of adding ions to the silicon substrate110, an ion implantation apparatus or an ion doping apparatus can be used. In the ion implantation apparatus, a source gas is excited to produce ion species, the produced ion species are mass-separated, and an object to be processed is irradiated with the ion species having a predetermined mass. In the ion doping apparatus, a process gas is excited to produce ion species, the produced ion species are not mass-separated, and an object to be processed is irradiated with the produced ion species. Note that in an ion doping apparatus provided with a mass separator, ion irradiation with mass separation can also be performed as in the ion implantation apparatus.

In the case of using the ion doping apparatus, a step of forming the embrittlement region114can be performed, for example, under the following conditions:

Accelerating voltage is greater than or equal to 10 kV and less than or equal to 100 kV (preferably greater than or equal to 30 kV and less than or equal to 80 kV)

Dose is greater than or equal to 1×1016/cm2and less than or equal to 4×1016/cm2.

Beam current intensity is greater than or equal to 2 μA/cm2(preferably greater than or equal to 5 μA/cm2, more preferably greater than or equal to 10 μA/cm2).

In the case of using the ion doping apparatus, a gas containing hydrogen can be used as a source gas. With the gas containing hydrogen, H+, H2+, and H3+can be produced as ion species. In the case where a hydrogen gas is used as the source gas, it is preferable to perform irradiation with a larger amount of H3+ions. Specifically, it is preferable that the ion beam contains H3+ions at a proportion of 70% or higher with respect to the total amount of H+, H2+, and H3+ions. It is more preferable that the proportion of H3+ions be higher than or equal to 80%. By increasing the proportion of H3+ions in this manner, the embrittlement region114can contain hydrogen at a concentration of higher than or equal to 1×1020atoms/cm3. Accordingly, separation at the embrittlement region114can be performed easily. By irradiation with a larger amount of H3+ions, the embrittlement region114can be formed in a shorter period of times as compared to the case of irradiation with H+ions and H2+ions. Moreover, with the use of H3+, the average penetration depth of ions can be made shallower; thus, the embrittlement region114can be formed at a shallower region.

In the case of using the ion implantation apparatus, it is preferable to perform irradiation with H3+ions through mass separation. Of course, irradiation with H+ions or H2+ions may be performed. Note that, since ion species are selected to perform irradiation in the case of using the ion implantation apparatus, ion irradiation efficiency is decreased compared to the case of using the ion doping apparatus, in some cases.

As the source gas for the ion irradiation step, as well as the gas containing hydrogen, one or more kinds of gases selected from a rare gas such as helium or argon; a halogen gas typified by a fluorine gas or a chlorine gas; or a halogen compound gas such as a fluorine compound gas (for example, BF3) can be used. When helium is used for the source gas, an ion beam with high proportion of He+ions can be formed without mass separation. By using such ion beams, the embrittlement region114can be efficiently formed.

Further, the embrittlement region114can also be formed by performing the ion irradiation step plural times. In this case, either different source gases or the same source gas may be used for the ion irradiation steps. For example, ion irradiation can be performed using a gas containing hydrogen as a source gas after ion irradiation is performed using a rare gas as a source gas. Alternatively, ion irradiation may be performed first using a halogen gas or a halogen compound gas, and then, ion irradiation may be performed using the gas containing hydrogen.

Note that before the above ion irradiation step is performed, an insulating layer which functions as a protective insulating layer may be formed on the surface of the silicon substrate110(or the silicon carbide layer112). Needless to say, it is also possible that the insulating layer is not provided; however, the insulating layer is preferably provided in order to prevent contamination of the silicon substrate110and surface damage of the silicon substrate110(or the silicon carbide layer112) due to later ion irradiation. The thickness of the insulating layer is preferably greater than or equal to 10 nm and less than or equal to 400 nm. In addition, the description regarding the insulating layer may be referred to for the formation method, material, structure, and the like of the insulating layer102. The insulating layer may be removed or may remain after the ion irradiation step.

An insulating layer116is formed on the silicon carbide layer112(seeFIG. 1C). The description regarding the insulating layer116may be referred to for the formation method, material, structure, and the like of the insulating layer102. In the same manner as the insulating layer102, the insulating layer116is a layer having a surface for bonding; therefore, the surface preferably has high planarity. Note that the insulating layer116is not necessary the same as the insulating layer102.

Note that in this embodiment, the case in which the insulating layer102is formed on the base substrate100side and the insulating layer116is formed on the silicon substrate110side is described; however, one embodiment of the disclosed invention disclosed herein is not limited thereto. For example, the insulating layer may be provided only on the base substrate100side or only on the silicon substrate110side. In addition, in the case where the surfaces for bonding are sufficiently planarized, a structure without an insulating layer may be employed.

Note that the ion irradiation step (step of forming the embrittlement region114) may be performed before or after the insulating layer116is formed.

Then, the base substrate100and the silicon substrate110are bonded to each other (seeFIG. 1D). Specifically, the base substrate100and the silicon substrate110are bonded to each other with the insulating layer102and the insulating layer116interposed therebetween. Note that the surfaces of the insulating layer102and the insulating layer116for bonding are preferably cleaned by an ultrasonic cleaning method or the like before the bonding. After the surface of the insulating layer102is in contact with the surface of the insulating layer116, heat treatment is performed, so that the base substrate100and the silicon substrate110are bonded to each other. As bonding mechanism, mechanism relating to van der Waals' force, mechanism relating to hydrogen bonding, or the like is conceivable.

Note that the surfaces for bonding may be subjected to oxygen plasma treatment or ozone treatment before bonding so that the surface may be hydrophilic. By this treatment, a hydroxyl is added to the surfaces for bonding so that a hydrogen bond can be formed at a bonding interface.

After the bonding, heat treatment may be performed on the base substrate100and the silicon substrate110which are bonded to each other so as to strengthen the bonding. The heat temperature at this time needs to be a temperature that does not promote separation at the embrittlement region114. For example, a temperature lower than 400° C., more preferably lower than or equal to 300° C. can be employed. There is no particular limitation on heat treatment time, and an optimal condition may be set as appropriate in accordance with a relation between heat treatment time and bonding force. For example, heat treatment can be performed at 200° C. for two hours. Note that only the region for bonding can be locally heated by irradiating the region with microwaves or the like. When there is no problem with the bonding strength of the substrates, the heat treatment may be omitted.

Next, the silicon substrate110is separated into a semiconductor layer122including a stacked layer structure of the silicon carbide layer112and a silicon layer120and a silicon substrate124at the embrittlement region114(seeFIG. 1E). The silicon substrate110is separated by heat treatment. The temperature for the heat treatment can be set based on the upper temperature limit of the base substrate100. For example, when a glass substrate is used as the base substrate100, the temperature of the heat treatment is preferably equal to or greater than 400° C. and equal to or lower than the strain point of the glass substrate. Note that in this embodiment, heat treatment is performed at 600° C. for two hours.

By performing the above-described heat treatment, the volume of microvoids formed in the embrittlement region114is changed, and a crack is generated in the embrittlement region114. As a result, separation of the silicon substrate110is caused along the embrittlement region114. Accordingly, the semiconductor layer122separated from the silicon substrate110is left over the base substrate100. Further, since the interface for bonding the insulating layer102to the insulating layer116is heated by this heat treatment, a covalent bond is formed at the interface for bonding, so that the bonding force between the insulating layer102and the insulating layer116can be further improved.

In the structural body (hereinafter simply referred to as a semiconductor substrate) including the base substrate100formed as described above, an upper portion of the semiconductor layer122is the silicon layer120. Therefore, treatment for removing the silicon layer120is performed.

In this embodiment, oxidation treatment is performed on the silicon layer120to form a silicon oxide layer126(seeFIG. 1F), and the silicon oxide layer126is removed, whereby the silicon carbide layer112is left on the base substrate100(seeFIG. 1G). By oxidation of the silicon layer120, selection ratio between the silicon layer120and the silicon carbide layer112can be high; therefore, the silicon layer120can be removed very easily. Note that the thickness of the silicon layer120is preferably less than or equal to 300 nm, more preferably less than or equal to 200 nm to perform oxidation and removing efficiently. Thus, oxidation and removing of the silicon layer120can be realized since the thickness of the silicon layer120is thin. Therefore, it can be said that this technique is especially effective in the case of forming the semiconductor layer122by using separation due to addition of ions.

As oxidation treatment of the silicon layer120, a dry oxidation method, a pyrogenic oxidation method (a wet oxidation method) in which water vapor and oxygen are used for oxidation, an HCl oxidation method in which hydrogen chloride is mixed with oxygen, or the like can be employed. In addition, an oxidation method using oxygen plasma and ozone may be used.

In order to remove the silicon oxide layer126, one of dry etching treatment or wet etching treatment or a combination of both of the etching treatment may be performed. For example, when dry etching using an inert gas such as helium, argon, or xenon is performed, a silicon oxide layer can be selectively removed, which is preferable. Further, for example, wet etching using etchant (etching solution) such as buffered fluoric acid or other hydrofluoric acid based etchant is also preferable since a silicon oxide layer can be selectively removed.

Note that in this embodiment, a method for oxidation of the silicon layer120and removing thereof is described; however, one embodiment of the disclosed invention is not limited thereto. The intrinsic effect of technique according to one embodiment of the disclosed invention is remaining the silicon carbide layer112preferably; therefore, an oxidation method is not necessarily limited to the above as long as this can be realized. For example, etching selection ratio may be higher by performing nitridation treatment on the silicon layer120.

Further, a silicon oxide layer may be removed by the CMP method or the like. Even in this case, the silicon oxide layer can be selectively removed by appropriately selecting the kind of slurry. Note that as the slurry, silica slurry, cerium oxide slurry and the like may be used.

After the silicon layer120is removed as described above, treatment (planarization treatment) to reduce surface unevenness of the silicon carbide layer112may be performed. As the treatment, one of a dry etching process or a wet etching process or a combination of both of the etching processes may be performed. Alternatively, polishing treatment such as CMP or the like may be performed. In addition, a combination of both the etching process and the polishing treatment may be performed. Note that etching treatment for removing the silicon oxide layer126may have a planarization effect on the silicon carbide layer112.

In the foregoing manner, a semiconductor substrate including the silicon carbide layer112over the base substrate100can be manufactured (seeFIG. 1G).

As described above, in this embodiment, a silicon carbide layer is formed by using a silicon substrate. Accordingly, a semiconductor substrate including silicon carbide can be provided at very low cost. In addition, a silicon substrate which is to be a silicon carbide layer can be reused; therefore, manufacturing cost can be further reduced. Moreover, since a semiconductor substrate having a silicon carbide layer over an insulating layer can be provided, characteristics of the semiconductor element can be improved by using this.

<Thickening Treatment of Silicon Carbide Layer>

Note that the silicon carbide layer112formed by the above method has a comparatively small film thickness (for example, less than or equal to 100 nm) because of manufacturing method thereof. Therefore, thickening treatment of a silicon carbide layer may be performed after the above step. Hereinafter, thickening treatment of a silicon carbide layer is described with reference toFIGS. 2A and 2B. Needless to say, the thickening treatment may be omitted if unnecessary.

As the thickening treatment of a silicon carbide layer, for example, an epitaxial growth method can be used. Typically, there is a vapor deposition method, a solid phase growth method, or the like as the epitaxial growth method, and any of those can be used. Here, the case of thickening a silicon carbide layer by using a vapor deposition method will be described.

First, by using the manufacturing method shown inFIGS. 1A to 1G, and the like, a semiconductor substrate including the silicon carbide layer112over the base substrate100is formed (seeFIG. 2A). Planarization treatment may be performed on the silicon carbide layer112.

Next, a silicon carbide layer140is formed on the silicon carbide layer112(seeFIG. 2B). The silicon carbide layer140can be formed by using a CVD method or the like. In the case of forming a single-crystal silicon carbide layer by a vapor deposition method, it is preferably performed under a temperature condition of higher than or equal to 1000° C., more preferably higher than or equal to 1200° C. By the vapor deposition method, the silicon carbide layer140having crystallinity corresponding to the silicon carbide layer112is obtained.

Note that it is preferable to remove a natural oxide film and the like formed on the surface of the silicon carbide layer112before the silicon carbide layer140is formed on the silicon carbide layer112. This is because when an oxide film or the like exists on the surface of the silicon carbide layer112, the silicon carbide layer140having crystallinity corresponding to the silicon carbide layer112cannot be formed and crystallinity of the silicon carbide layer140might be reduced. Here, the above oxide film can be removed using a solution containing fluorinated acid or the like.

In the foregoing manner, a semiconductor substrate having a silicon carbide layer150including a stacked layer structure of the silicon carbide layer112and the silicon carbide layer140can be manufactured. After formation of the silicon carbide layer150, planarization treatment may be performed on the silicon carbide layer150.

Here, a method for thicken a silicon carbide layer by using a vapor deposition method is described; however, the silicon carbide layer may also be thicken by a solid phase growth method. In this case, after a silicon carbide layer having lower crystallinity than the silicon carbide layer112is formed on the silicon carbide layer112, heat treatment is performed, so that the silicon carbide layer is subjected to solid phase growth. By the solid phase growth method, crystallinity of the silicon carbide layer140corresponds to crystallinity of the silicon carbide layer112.

The above heat treatment is preferably performed under a saturated SiC vapor pressure and at a temperature of greater than or equal to 1900° C. Note that in the case of thicken the silicon carbide layer by the solid phase growth, the base substrate100, the insulating layer102, the insulating layer116, and the like need to resist heat treatment for the solid phase growth. As a material satisfying such a condition, a metal compound such as an aluminum oxide can be given.

By thickening the silicon carbide layer as described above, application range of the semiconductor substrate can be increased. According to one embodiment of the disclosed invention, a semiconductor substrate, which includes a silicon carbide layer and can be used for various purposes, can be provided at low cost.

This embodiment describes another example of a method for manufacturing a semiconductor substrate according to one embodiment of the disclosed invention with reference toFIGS. 3A to 3GNote that there are many common points between the method for manufacturing a semiconductor substrate in this embodiment and the method for manufacturing a semiconductor substrate, according to the aforementioned embodiment. Therefore, in this embodiment, a method for manufacturing a semiconductor substrate which is different from the method according to the aforementioned embodiment will be described.

First, a base substrate100is prepared and an insulating layer102is formed on the base substrate100(seeFIG. 3A). The aforementioned embodiment can be referred to for a detailed description thereof.

Next, a silicon substrate110is prepared and carbonization treatment is performed on the surface of the silicon substrate110to form a silicon carbide layer112(seeFIG. 3B). Then, by adding ions to the silicon substrate110after the silicon carbide layer112is formed, an embrittlement region114is formed, and an insulating layer116is formed on the silicon carbide layer112(seeFIG. 3C). The aforementioned embodiment can be referred to for a detailed description thereof.

Note that in this embodiment, the case in which the insulating layer102is formed on the base substrate100side and the insulating layer116is formed on the silicon substrate110side is described; however, it is the same as the aforementioned embodiment that one embodiment of the disclosed invention disclosed herein is not limited thereto.

Then, the base substrate100and the silicon substrate110are bonded to each other (seeFIG. 3D), and the silicon substrate110is separated at the embrittlement region114(seeFIG. 3E). The aforementioned embodiment also can be referred to for the detail of the step.

Then, treatment for removing the silicon layer120is performed over the semiconductor substrate formed as described above. Specifically, oxidation treatment is performed on the silicon layer120to form a silicon oxide layer126(seeFIG. 3F), and part of the silicon oxide layer126is removed, whereby a stacked layer structure of the silicon carbide layer112and a silicon oxide layer128is formed on the base substrate100(seeFIG. 3G).

One difference between the method for manufacturing the semiconductor substrate according to this embodiment and the method for manufacturing the semiconductor substrate according to aforementioned embodiment is a method for removing the silicon oxide layer126. That is, while the silicon oxide layer126is completely removed to expose the silicon carbide layer112in the method for manufacturing the semiconductor substrate according to aforementioned embodiment, part of the silicon oxide layer126is removed to leave the silicon oxide layer128in the method for manufacturing the semiconductor substrate according to this embodiment.

In this manner, by leaving the silicon oxide layer128over the silicon carbide layer112, the silicon oxide layer128can be used as part of a semiconductor element. As an example of application of the silicon oxide layer128, a gate insulating layer of a transistor can be given. In the case of using the silicon oxide layer128as the gate insulating layer of the transistor, it is possible to form the silicon carbide layer112which functions as an active layer of the transistor and the silicon oxide layer128which functions as a gate insulating layer in an integrated manner; therefore, defects and the like are not easily generated at an interface between the silicon carbide layer112and the silicon oxide layer128. Accordingly, a transistor having excellent characteristics can be manufactured.

Note that in this embodiment, a step in which part of the silicon oxide layer126is removed after oxidation of the silicon layer120to form the silicon oxide layer128is described; however, one embodiment of the disclosed invention is not limited thereto. Alternatively, after the silicon layer120is thinned by removing part thereof, oxidation treatment may be performed on the thinned silicon layer120to form the silicon oxide layer128. In addition, the thickness of the silicon oxide layer128may be set as appropriate in accordance with required characteristics of a semiconductor element.

The aforementioned embodiment can be referred to for a detailed description of oxidation treatment of the silicon layer120and treatment for removing the silicon oxide layer126.

As described above, in this embodiment, a silicon carbide layer is formed by using a silicon substrate. Accordingly, a semiconductor substrate including silicon carbide can be provided at very low cost. In addition, a silicon substrate which is to be a silicon carbide layer can be reused; therefore, manufacturing cost can be further reduced. Moreover, since a semiconductor substrate having a silicon carbide layer over an insulating layer can be provided, characteristics of the semiconductor element can be improved by using this.

In addition, by leaving the silicon oxide layer and using that as part of a semiconductor element, the manufacturing step of the semiconductor element can be simplified. Further, by forming a stacked layer structure of the silicon carbide layer and a silicon oxide layer in this manner, defects generated at an interface between the silicon carbide layer and the silicon oxide layer can be significantly reduced.

This embodiment can be implemented in combination with the aforementioned embodiment, as appropriate.

This embodiment describes another example of a method for manufacturing a semiconductor substrate according to one embodiment of the disclosed invention with reference toFIGS. 4A to 4GNote that there are many common points between the method for manufacturing a semiconductor substrate in this embodiment and the method for manufacturing a semiconductor substrate according to the aforementioned embodiment. Therefore, in this embodiment, a method for manufacturing a semiconductor substrate which is different from the method according to the aforementioned embodiment will be described in detail.

First, a base substrate100is prepared and an insulating layer102is formed on the base substrate100(seeFIG. 4A). The aforementioned embodiment can be referred to for a detailed description thereof.

Next, a silicon substrate110is prepared and carbonization treatment is performed on the surface of the silicon substrate110to form a silicon carbide layer112(seeFIG. 4B). Then, by adding ions to the silicon substrate110after the silicon carbide layer112is formed, an embrittlement region114is formed, and a conductive layer130and an insulating layer116are formed on the silicon carbide layer112(seeFIG. 4C).

A method for forming the conductive layer130is not particularly limited to a certain method, and for example, a sputtering method, a vacuum evaporation method, or the like can be used. The conductive layer130can be formed using a metal selected from aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), niobium (Nb), chromium (Cr), and cerium (Ce); an alloy containing any of these metals as its main component; or nitride containing any of these metals as a component. The conductive layer130may be formed using conductive oxide such as indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO); silicon to which an impurity element imparting conductivity is added; or the like. Note that the conductive layer130may have a single-layer structure or a stacked layer structure.

The aforementioned embodiment can be referred to for a detailed description of other structure.

Note that in this embodiment, the case the conductive layer130is formed on the silicon carbide layer112is described; however, one embodiment of the disclosed invention is not limited thereto. Various kinds of layers can be formed as well as a conductive layer. For example, a semiconductor layer to which an impurity element imparting one conductivity type is added may be formed and a semiconductor layer made from a material different from that may be formed. Alternatively, a plurality of those layers may be stacked.

Note that in this embodiment, the case in which the insulating layer102is formed on the base substrate100side and the insulating layer116is formed on the silicon substrate110side is described; however, it is the same as the aforementioned embodiment that one embodiment of the disclosed invention is not limited thereto.

Then, the base substrate100and the silicon substrate110are bonded to each other (seeFIG. 4D), and the silicon substrate110is separated at the embrittlement region114(seeFIG. 4E). The aforementioned embodiment also can be referred to for the detail of the step.

Then, treatment for removing the silicon layer120is performed over the semiconductor substrate formed as described above. Specifically, oxidation treatment is performed on the silicon layer120to form a silicon oxide layer126(seeFIG. 4F), and the silicon oxide layer126is removed, whereby the silicon carbide layer112is left on the base substrate100(seeFIG. 4G). The aforementioned embodiment can be referred to for a detailed description thereof. Note that the thickness of the silicon carbide layer may be increased after the silicon oxide layer126is removed.

Through the above steps, a semiconductor substrate having a structure in which a conductive layer and a silicon carbide layer are formed over a base substrate with insulating layers interposed therebetween. Note that in this embodiment, an example in which the conductive layer130is formed on the silicon substrate110side is described; however, one embodiment of the disclosed invention is not construed as being limited thereto. The conductive layer130and the like can be formed on the base substrate100side.

As described above, in this embodiment, a silicon carbide layer is formed by using a silicon substrate. Accordingly, a semiconductor substrate including silicon carbide can be provided at very low cost. In addition, a silicon substrate which is to be a silicon carbide layer can be reused; therefore, manufacturing cost can be further reduced.

In addition, by forming various kinds of layers below a silicon carbide layer, various kinds of semiconductor elements can be realized. For example, by forming a conductive layer below a silicon carbide layer, a semiconductor element having a lower electrode can be formed. In this manner, application of the semiconductor substrate is expanded by forming various kinds of layer below a silicon carbide layer. That is, according to one embodiment of the disclosed invention, a semiconductor substrate, which includes a silicon carbide layer and can be used for various purposes, can be provided at low cost.

This embodiment can be implemented in combination with any of the aforementioned embodiments, as appropriate.

This embodiment describes a method for manufacturing a semiconductor device using a semiconductor substrate manufactured by a method described in aforementioned embodiments with reference toFIGS. 5A to 5DandFIGS. 6A to 6D. More specifically, a method for manufacturing a semiconductor element used for a semiconductor device will be described. In particular, this embodiment describes a case of manufacturing an n-channel FET and a p-channel FET which are used for a CMOS circuit; however, a semiconductor element and a semiconductor device using the semiconductor element manufactured by using the semiconductor substrate is not particularly limited thereto.

First, after the semiconductor substrate is obtained in accordance with a method described in aforementioned embodiments or the like, a protective layer500which functions as a mask for formation of an element isolation insulating layer is formed over a silicon carbide layer112(seeFIG. 5A). A silicon oxide layer, a silicon nitride layer, or the like is used as the protective layer500. Note that the semiconductor substrate used in this embodiment is equivalent to that manufactured in accordance with the aforementioned embodiments. A thickness of the silicon carbide layer112may be increased and planarization treatment may be performed on the surface thereof.

To control threshold voltages of the silicon carbide layer112, a p-type impurity such as boron, aluminum, or gallium or an n-type impurity such as phosphorus or arsenic may be added to the silicon carbide layer112.

Next, etching is performed using the protective layer500as a mask and exposed part of the silicon carbide layer112is removed. After that, an insulating layer is deposited. The insulating layer can be a silicon oxide layer, for example. The insulating layer may be formed by using any of a variety of film deposition techniques typified by a CVD method or a sputtering method. Here, the insulating layer is deposited thickly so as to be embedded in the silicon carbide layer112.

Next, an insulating layer overlapping with the silicon carbide layer112is removed by polishing, etching, or the like. Then, the protective layer500is removed and an element isolation insulating layer502formed of part of the insulating layer is left (seeFIG. 5B). Note that a structure in which the element isolation insulating layer502is provided is employed in this embodiment; however, a structure in which the element isolation insulating layer502is not provided may be employed.

Next, an insulating layer504functioning as a gate insulating layer is formed and an gate electrode506is formed on the insulating layer504(seeFIG. 5C). The insulating layer504can be formed by a CVD method, a sputtering method or the like. It is preferable that the insulating layer504be formed using silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, or the like. Note that the insulating layer504may have a single-layer structure or a stacked layer structure. Here, a silicon oxide layer which covers a surface of the silicon carbide layer112is formed to have a single-layer structure by a CVD method.

A material having high heat resistance is preferably used for the gate electrode506. For example, titanium, molybdenum, tungsten, tantalum, chromium, or nickel can be used. In addition, the gate electrode506may be formed using a material having low resistance, such as aluminum and copper. Further, a semiconductor material (for example, polysilicon) to which an impurity element imparting one conductivity type is added may be used.

Note that in this embodiment, the gate electrode506employs a single-layer structure; however, a stacked layer structure may also be used. Further, combination of the aforementioned materials may be used. In this case, combination of a material having high heat resistance and a material having low resistance, for example, a stacked layer structure of titanium and aluminum, a stacked layer structure of tungsten and aluminum, or the like may be used. Further, a stacked layer structure of the aforementioned metal material and nitride of the metal material may be employed. For example, a stacked layer structure of a titanium nitride layer and a titanium layer, a stacked layer structure of a tantalum nitride layer and a tantalum layer, a stacked layer structure of a tungsten nitride layer and a tungsten layer, and the like can be used. Note that the gate electrode506is formed using an evaporation method, a sputtering method, or the like.

Next, the insulating layer504is etched using the gate electrode506as a mask to form a gate insulating layer508. In this etching, part of the element isolation insulating layer502is etched. After that, an insulating layer510covering the gate electrode506is formed (seeFIG. 5D).

Next, part of a region which is to be an n-channel FET later is doped with phosphorus (P), arsenic (As), or the like at a low concentration to form a first impurity region512, and part of a region which is to be a p-channel FET later is doped with boron (B) or the like at a low concentration to form a second impurity region514(seeFIG. 6A). Note that although the impurity regions are formed after formation of the insulating layer510here, the impurity regions may be formed before the insulating layer510is formed.

After that, a sidewall insulating layer516and a sidewall insulating layer518are formed (seeFIG. 6B). The sidewall insulating layer518of the region which is to be the p-channel FET is preferably larger in width (the length in a channel length direction) than the sidewall insulating layer516of the region which is to be the n-channel FET.

Next, the insulating layer510is partly etched to expose a surface of the first impurity region512and a surface of the second impurity region514. At this time, a top surface of the gate electrode506is also exposed. Then, the region which is to be the n-channel FET is doped with phosphorus (P), arsenic (As), or the like at a high concentration to form a third impurity region520, and the region which is to be the p-channel FET is doped with boron (B) or the like at a high concentration to form a fourth impurity region522(seeFIG. 6C). Note that although the impurity regions are formed after the insulating layer510is partly etched here, the impurity regions may be formed before the insulating layer510is etched.

Next, an interlayer insulating layer524is formed and a contact plug526and a contact plug528which reach the third impurity region520and the fourth impurity region522, respectively, are formed. As described above, an n-channel FET530and a p-channel FET532can be manufactured using the silicon carbide layer112formed over the base substrate100(seeFIG. 6D).

The n-channel FET530and the p-channel FET532can be complementarily combined to form a CMOS circuit. Further, a variety of semiconductor devices can be manufactured by using such a semiconductor element.

As described in this embodiment, increasing the withstand voltage of a semiconductor element, reducing a loss of electric power, and the like are realized by using the silicon carbide as an active layer of a FET. According to one embodiment of the disclosed invention, a semiconductor substrate including silicon carbide can be provided at very low cost; therefore, manufacturing cost of a semiconductor element and a semiconductor device can be reduced.

This embodiment can be implemented in combination with any of the aforementioned embodiments, as appropriate.

This embodiment describes a method for manufacturing a semiconductor device using a semiconductor substrate manufactured by a method described in aforementioned embodiments with reference toFIGS. 7A to 7DandFIGS. 8A to 8B. In particular, this embodiment describes a case of manufacturing a semiconductor device having a so-called power MOSFET (MOSFET for electric power) as a semiconductor element; however, a semiconductor element and a semiconductor device manufactured by using the semiconductor substrate is not particularly limited thereto.

First, a semiconductor substrate manufactured by the method described in aforementioned embodiment is prepared (seeFIG. 7A). The semiconductor substrate has a structure in which an insulating layer102, an insulating layer116, a conductive layer130, and a silicon carbide layer112are successively stacked over a base substrate100. In addition, an impurity element imparting one conductivity type is added to the silicon carbide layer112and the silicon carbide layer112is divided into two regions according to a concentration of the impurity element. Here, a first impurity region700in contact with the conductive layer130is a region to which an impurity element is added at high concentration, and a second impurity region702in contact with the first impurity region700is a region to which an impurity element is added at low concentration.

As an impurity element which can be added to the silicon carbide layer112, phosphorus (P) and arsenic (As) which impart n-type conductivity, and boron (B) which impart p-type conductivity can be given. The case in which phosphorus (P) is added to the first impurity region and the second impurity region to impart n-type conductivity will be described in this embodiment.

Note that this embodiment employs a structure in which the conductive layer130is provided below a bottom surface of the silicon carbide layer112; however, one embodiment of the disclosed invention is not limited thereto and may employ a structure in which the conductive layer130may be provided selectively. In addition, a thickness of the silicon carbide layer112may be increased and planarization treatment may be performed on the surface thereof. In the power MOSFET described in this embodiment, the conductive layer130functions as a drain electrode (or a source electrode). Further, the first impurity region700functions as a drain region (or a source region).

Next, an impurity element imparting p-type conductivity (for example, boron) and an impurity element imparting n-type conductivity (for example, phosphorus) are selectively added to the second impurity region702, thereby forming a region706having a conductivity type different from that of the second impurity region702and a region704having the same conductivity type as that of the second impurity region702(seeFIG. 7B). Here, part of the region704functions as a channel formation region later and the region706functions as a source region (or a drain region). In addition, an impurity concentration of the region706is higher than that of the second impurity region702.

After formation of the region704and the region706, an insulating layer708functioning as a gate insulating layer is formed over the second impurity region702, and a conductive layer710functioning as a gate electrode is selectively formed over the insulating layer708. Then, an insulating layer712is formed covering the conductive layer710(seeFIG. 7C). Here, it is preferable that the conductive layer710be formed so that at least part of the conductive layer710overlaps with the region706. Thus, the concentration of electric field is alleviated, whereby higher withstand voltage of MOSFET can be obtained.

The insulating layer708can be formed using silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, hafnium oxide, aluminum oxide, tantalum oxide, or the like. As examples of a manufacturing method, a thermal oxidation method (a thermal nitridation method), a plasma CVD method, a sputtering method, oxidation or nitridation by high density plasma treatment, and the like can be given. Although the insulating layer712can be formed in a manner similar to the insulating layer708, a material different from that of the insulating layer708may be used for the insulating layer712. For example, the insulating layer712can be formed by using organic material.

A material having high heat resistance is preferably used for the conductive layer710. For example, titanium, molybdenum, tungsten, tantalum, chromium, or nickel can be used. In addition, the conductive layer710may be formed using a material having low resistance, such as aluminum and copper. Further, a semiconductor material (for example, polysilicon) to which an impurity element imparting one conductivity type is added may be used.

Note that in this embodiment, the case in which the insulating layer708is formed after the region704and the region706are formed is described; however, one embodiment of the disclosed invention is not construed as being limited thereto. For example, the region704and the region706may be formed after the insulating layer708is formed. Alternatively, an insulating layer which is to be the insulating layer708may be formed in manufacturing steps of the semiconductor substrate (seeFIGS. 3A to 3G).

Next, after openings are formed in the insulating layer712and the insulating layer708, a conductive layer714which is electrically connected to the region706is formed (seeFIG. 7D). Note that the conductive layer714functions as a source region (or a drain region).

The openings in the insulating layer712and the insulating layer708can be formed by selective etching with the use of a resist mask or the like. In addition, the conductive layer714may be formed in a manner similar to the conductive layer130and the conductive layer710.

In this manner, a so-called power MOSFET can be manufactured.FIGS. 8A and 8Billustrate a cross sectional view and a plane view of the power MOSFET in this embodiment.FIGS. 8A and 8Bare the cross sectional view and the plane view of the power MOSFET in this embodiment, respectively. Here,FIG. 8Acorresponds to a cross section taken along a line A-B inFIG. 8B. InFIG. 8B, part of structures of the insulating layer708, the conductive layer710, the insulating layer712, and the conductive layer714are omitted for simplicity.

Note that positions or connections of the layers are not limited to the structure illustrated inFIGS. 8A and 8B. For example, it is possible that part of the conductive layer710and the conductive layer130are electrically connected to each other, whereby the part of the conductive layer710can function as a wiring for the conductive layer130.

Note that, the planar shape of the region704and the region706is a circular shape (seeFIG. 8B) in this embodiment; however, an embodiment of the disclosed invention is not limited thereto. Either a rectangular shape or any other shape can be employed. The region704and the region706are circular as described in this embodiment, whereby the channel length L can be uniform. Accordingly, the concentration of the electric field in the channel formation region can be alleviated, whereby the transistor can have higher withstand voltage. Further, the conductive layer130has an effect of improving efficiency in waste heat of a transistor with large current.

As described in this embodiment, increasing the withstand voltage of a semiconductor element, reducing a loss of electric power, and the like are realized by using the silicon carbide as an active layer of a power MOSFET. That is, characteristics of the semiconductor device having the power MOSFET can be improved. According to one embodiment of the disclosed invention, a semiconductor substrate including silicon carbide can be provided at very low cost; therefore, manufacturing cost of a semiconductor element and a semiconductor device can be reduced.

This embodiment can be implemented in combination with any of the aforementioned embodiments, as appropriate.

This application is based on Japanese Patent Application serial no. 2009-075824 filed with Japan Patent Office on Mar. 26, in 2009, the entire contents of which are hereby incorporated by reference.