Capacitance measuring circuit

A variable capacitor, which may be a humidity sensitive capacitor, and a fixed reference capacitor are connected at a node. The node is clamped at a reference potential during a first phase of a two phase measuring cycle as the variable capacitor is charged to a fixed voltage and the fixed capacitor is charged to a feedback voltage. The node is unclamped during the second phase and the capacitors are connected in a series loop to allow a redistribution of the charge in the capacitors or force a reversal of that charge with a voltage source. The deviation of the node from its reference potential after charge redistribution occurs is used as input to a feedback circuit which integrates that deviation over a number of cycles until it provides a feedback voltage of magnitude sufficient to cause the node deviation to be reduced to zero. A second reference capacitor can be supplied to provide an offset. The capacitors are constructed by simultaneous deposition on a substrate of a first plate followed by a dielectric film and a second plate. The second plate of the variable capacitor is porous to admit water molecules and the second plate of the fixed capacitor is impervious to water. The simultaneous deposition provides similar characteristics for the capacitors.

BACKGROUND OF THE INVENTION 
This invention relates to a method and apparatus for measuring the 
capacitance of variable capacitors and to methods and apparatus for 
measuring relative humidity using capacitive sensors whose capacitance 
varies with relative humidity. This invention also relates to methods and 
apparatus for measuring other variables by using capacitive sensors whose 
capacitance is related to the magnitude of the variable to be measured. 
Capacitive humidity sensors may, for example, be constructed by laying a 
first conductive plate area on a silicon chip, then covering that area 
with a polymer, such as a polyimide, of desired thickness as a dielectric, 
and then depositing the second plate as a conductive layer over the 
dielectric. The polyimide forms a thin, water absorbing dielectric film 
whose dielectric constant varies in proportion to the concentration of the 
absorbed water so that the capacitance of the combination varies with the 
humidity of the surrounding region. 
Another example of a capacitive sensor is the capacitive pressure 
transducer. One form these transducers take at the present involves the 
use of a silicon diaphragm which is bonded between two silicon plates to 
form a capacitor on each side of the diaphragm. Those capacitors are 
responsive to the difference in pressure between the two sides of the 
diaphragm. The dielectric between the plates in these structures is 
usually silicone oil. 
In both the capacitive pressure transducer and the capacitive humidity 
sensor, it has been found to be desireable to integrate the measuring 
circuit and the capacitive sensor onto a single monolithic silicon chip, 
if that is possible. By so doing, the sensor and the other capacitive 
elements of the circuit can easily be constructed on the substrate at the 
same time so that they have the same plate dimensions and the same 
dielectric thickness. This gives all of the capacitors the same 
characteristics making it possible to incorporate them into measuring 
circuits without the need for either electrically trimming those circuits 
or physically trimming the plate dimensions to attempt to match their 
characteristics. Also, by using a single chip the components of the 
circuit will be subjected to the same ambient conditions so that 
temperature and pressure variations will affect the components of the 
circuit by the same amount. If placing all of the measuring circuit 
components on a single chip is not possible, then it has been found to be 
desirable to make the measuring circuit elements as nearly similar as 
possible and place them as close as possible to the sensor so that they 
have very similar characteristics to those of the sensor and are subjected 
to ambient conditions closely approximating those to which the sensor is 
subjected. 
Typically, the prior art relating to the measurement of capacitance 
requires the use of resistors. It is well known that large accurate 
resistors require a significant area on a chip. Also, it is desirable to 
avoid the need to depend on the accuracy of the parameters introduced into 
a circuit by a resistor. Similarly, it is desirable to avoid variation 
which can be introduced by a semiconductor device or by a multivibrator. 
For these reasons improvements can be foreseen if it is only necessary to 
depend on the parameter values of capacitors and external reference 
voltages. One such improvement would be minimizing the cost of 
manufacture. This benefit is evident when one considers the fact that 
capacitors can be matched during the mask and layout stage of the 
semiconductor manufacturing procedure, and the fact that the possibility 
of closely matching those elements makes trimming unecessary even when one 
must provide finished units which will all have the same span and the same 
offset so that they can be used interchangeably without the need for 
calibration. 
Switched capacitor circuits are known in the field of A/D converters. Such 
circuits have used switched capacitors which are effective to change the 
input of an amplifier circuit in the manner shown in the publication 
"Intuitive IC CMOS Evolution" by Frederiksen, at pages 103-105. In those 
circuits, there is shown a sampled data comparator which consists of CMOS 
analog switches, a string of capacitively-coupled logic inverters for 
voltage gain, and capacitors, some of which convert from voltage to charge 
and others of which serve to couple the converters. The particular 
circuits described, while not useful in measuring capacitance, do show the 
use of a string of capacitively coupled logic inverters providing 
amplification for a switched-capacitor circuit, where the capacitors in 
the circuit are zeroed by shorting out the logic inverters. That approach 
is used to provide the amplification and the setting-up of the capacitors 
in one form of the switched capacitor circuit of the present invention. 
It is an object of this invention to provide an improved capacitance 
measuring circuit and, more particularly, one which will measure the 
capacitance of a capacitive sensor by using only capacitors and other 
circuit components which can be easily integrated onto a small monolithic 
silicon chip so as to avoid the need for either physically trimming the 
components or electrically trimming the associated measuring circuit for 
calibration purposes. 
It is a further object of this invention to provide a measuring circuit for 
measuring the capacitance of a capacitive humidity sensor so that a 
minimum of trimming is needed even though it is not possible to integrate 
all of the capacitors of the measuring circuit onto the same silicon chip. 
In addition, it is an object of this invention to provide a measuring 
circuit for measuring the capacitance of a capacitive humidity sensor in a 
manner which will make the measurement immune to drift with changes in 
temperature or humidity. 
SUMMARY OF THE INVENTION 
In carrying out the present invention there is provided a method and a 
circuit for measuring the capacitance of a variable capacitor such as a 
capacitive sensor whose capacitance varies with the magnitude of a 
variable to be measured. The circuit requires at least one reference 
capacitor, which is charged to a variable output voltage during the first 
phase of a two phase measuring cycle while the variable capacitor is 
charged to a fixed voltage. The capacitors are connected in a loop during 
the second phase of the measuring cycle. The potential at the junction 
between the capacitors is then compared with a predetermined balance value 
and the output voltage is iteratively varied in a direction to reduce the 
deviation from the balance value to zero so that the output voltage will 
be proportional to the capacitance of the variable capacitor. 
When it is desired to convert the output voltage to a digital readout by 
using an A/D converter which has differential inputs for both the unknown 
and the reference potential and a digital indicator, the present invention 
can include a circuit for tailoring the inputs to the A/D converter so 
that the full scale range and zero offset of the output voltage, for the 
range of humidity being measured, generates a full scale indication on the 
indicator. This circuit includes a potentiometer supplied from the 
sampling voltage and connected with its tap supplying a potential which 
will change the magnitude of the unknown input depending on the position 
of said tap so that the input of the converter is adapted to the zero 
offset. Also included is a network which is supplied from the tap and from 
a voltage divider across said sampling voltage so that the output of the 
network is effective to modify the reference inputs to adapt the converter 
to the change in the output voltage which represents full scale range. The 
potentiometer tap must be adjustable to provide the necessary trimming 
when the reference capacitor does not exactly match the unknown variable 
capacitor, as would be the case if they were manufactured by integrated 
circuit techniques on the same substrate and at the same time. If they are 
manufactured to be exactly alike, the tap can be a fixed point since 
trimming is not needed. 
Where the variable capacitor is a humidity sensor, one form of the 
invention contemplates manufacturing both capacitors at the same time with 
the same materials by integrated circuit techniques on the same substrate 
in order to perfectly match the two capacitors. Sealing the reference 
capacitor from exposure to the atmosphere whose humidity is to be measured 
is then necessary to prevent it from changing capacitance with humidity 
changes.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 shows a simplified circuit which illustrates the operation of both 
the method and apparatus of this invention. In FIG. 1 a variable 
capacitor, C.sub.x, such as a capacitive sensor for measuring relative 
humidity, is connected in series with a fixed or reference capacitor, 
C.sub.r, at a node 10. In a first phase of a measuring cycle having two 
non-overlapping phases, the switches 1 and 2 are closed, as shown, so that 
the fixed voltage source 3 provides a voltage V.sub.t across C.sub.x and 
the variable voltage source 4 provides a voltage V.sub.o across the 
capacitor C.sub.r. In the second phase of the measuring cycle the 
capacitors C.sub.x and C.sub.r are connected in series with a fixed 
sampling voltage, as supplied by source 5, by the making of the switch 6 
and the disconnection of the switches 1 and 2. The charges in the 
capacitors are allowed to redistribute themselves, and then the high 
impedance detector 7 detects or measures the difference between the 
existing potential at the junction between the capacitors and a 
predetermined balance value for that potential. In FIG. 1 that difference 
is detected or measured by looking at the difference between the potential 
at the node 10 and at a reference point 8, the balance value. If the 
deviation or difference is not zero then the variable voltage source 4 is 
modified. In the circuit shown, the modification would be in a direction 
corresponding with the deviation detected. In other words, if the 
potential difference between node 10 and reference point 8 is negative the 
voltage V.sub.o is decreased. The reference point 8 may be at any of a 
number of potentials; for example, circuit common potential, which allows 
elimination of the resistors R.sub.1 and R.sub.2, or a potential 
representing half of the drop across the source 5, in which case the 
resistors will be of equal value. 
The value of the voltage V.sub.o will be found to be proportional to the 
changing value of the capacitance of capacitor C.sub.x if the deviation of 
the difference detected by 7 from the predetermined balance value is kept 
at zero. This results from the fact that, as the capacitance of C.sub.x 
changes with a resulting change in the charge it carries after its 
charging in the first phase, the charging voltage on C.sub.r is changed to 
similarly change the charge it carries. Then, the redistribution of 
charges which occurs during the second phase will provide a changed 
balance between the resulting voltages across the two capacitors such that 
there will be a reduction of the deviation detected by the detector. After 
a number of iterations in the proper sense the deviation will reach zero 
and V.sub.o will be a measure of the capacitance of C.sub.x. 
Proper operation of the circuit of FIG. 1 does not require that the 
sampling voltage be a certain polarity of magnitude-indeed the magnitude 
may be zero-or that the output voltage V.sub.o be a certain polarity. The 
reversal of the polarity of the sampling voltage wil only invert the 
relationship of V.sub.o and the variable capacitance being measured, 
whereas the polarity of V.sub.o will generally be a function of other 
parameters. 
In FIG. 2, there is shown in more detail a circuit which follows the 
principles of operation illustrated by FIG. 1. In FIG. 2, the reference 
point 8 of FIG. 1 is circuit common potential and the detector 7 is 
comprised of cascaded logic inverters and an integrating amplifier with 
its associated switches. The predetermined potential difference across the 
reference capacitor to be detected by the detector 7 as an indication of 
balance is the trigger voltage of the inverters as established by the 
shorting of their inputs and outputs. That trigger voltage is also the 
voltage to which C.sub.x is charged, namely V.sub.t. in FIG. 2, the 
variable capacitor C.sub.x, which may be a capacitive humidity sensor, is 
connected in a network with reference capacitor C.sub.r and an additional 
reference capacitor C.sub.o by connecting one terminal of each to the node 
10. The other terminals of these capacitors are selectively connected by 
way of switching elements 11-16 to either the output voltage, V.sub.o, or 
to a predetermined sampling voltage, V.sub.s, or to circuit common. For 
the purpose of this circuit the switching elements 11- 15 are MOS 
transistor switches and switch 16 is a CMOS switch. In addition to the 
capacitors mentioned, there will, of course, be a stray capacitance, which 
is represented in FIG. 1 by C.sub.y. As will be demonstrated later, the 
stray capacitance will only have a second order effect. 
In the operation of this circuit the switches 11, 13, and 16 are closed, 
and the remainder of the switches are open during the first, setup phase, 
.phi..sub.1, of a two phase clock which is used to time the two phases of 
the measuring cycle. This clock, which is shown in FIG. 5 and described 
subsequently, provides two non-overlapping clock signals of both 
polarities, P.sub.1 and P.sub.1 -, during the first phase; and P.sub.2 and 
P.sub.2 -during the second, or sampling phase, .phi..sub.2. During the 
second, sampling phase the switches 12, 14 and 15 are closed and switches 
11, 13, and 16 are open. 
As shown in FIG. 2, the node 10 is connected to the input circuit of a 
logic inverter, which is in turn connected through capacitor 22 to another 
logic inverter 24. The output of inverter 24 is then connected through 
still another logic inverter and through CMOS switch 28 to terminal 29, 
which connects through capacitor 30 to circuit common. The terminal 29 is, 
as shown, connected through CMOS switch 32 to the inverting input of an 
operational amplifier 34. That amplifier has the capacitor 36 in its 
negative feedback circuit so as to form an integrating amplifying circuit. 
Also, as shown, the non-invertinng input to amplifier 34 is connected to a 
voltage V.sub.a, and the output of the amplifier is an output voltage 
V.sub.o, which is fed back to one side of switch 16 and is also provided 
to any indicating or recording circuits which may be utilized to obtain a 
readout of the measured capacitance value of C.sub.x. 
The switches 28 and 32 are driven by the clock signals so that 32 is closed 
and 28 is open during the setup phase, when the charge on capacitor 30 is 
effective to cause the output of amplifier 34 to change and hence the 
charge on capacitor 36 to change until the potential at the inverting 
input of the amplifier is equal to the potential at the non-inverting 
input, V.sub.a. This provides an output V.sub.o which is the integral of 
the voltages to which the capacitor 30 is charged during consecutive 
sampling phases. During the sampling phase, the switches 28 and 32 are 
reversed and the capacitor 30 is charged from the output of the logic 
inverters in proportion to the change in potential at node 10 which occurs 
upon switching from the setup phase to the sampling phase. 
It will be evident that the timing of the clock and the parameters of the 
capacitors C.sub.x, C.sub.o and C.sub.r must be such that the capacitors 
are allowed to obtain their full charge as appropriate for the voltages 
applied to them during each phase. Thus, the transients caused by the 
switching of the connections are allowed to settle out before the circuit 
is again switched. 
FIG. 3 shows a circuit which can be used for the logic inverter 20. In that 
circuit the CMOS amplifiers 40 and 42 provide the amplification and the 
logic inversion while the CMOS switches 44 and 46 provide the shorting of 
the amplifier's input and output as is required during the setup phase of 
the measuring cycle in order to keep the node 10 at a fixed potential. In 
this case that fixed potential will be the threshold potential of the 
logic inverters, known as the trigger voltage, V.sub.t, which during the 
first phase is V.sub.t1. The switches 44 and 46 are closed to short the 
input and output of the inverter during the setup phase and are open 
during the sampling phase of the measuring cycle so that the node 10 is 
clamped at the threshold potential, V.sub.t1, during the setup phase and 
potential at the node 10, V.sub.t2, is allowed to float during the 
sampling phase. 
It is, of course, evident that the logic inverter 20 will not draw any 
significant current during the sampling phase, but will supply any 
necessary current to charge the capacitors during the setup phase to hold 
node 10 at V.sub.t1. The other logic inverters 22 and 24 can be 
constructed as shown for inverter 20 in FIG. 3. The inverters 22-24 will 
also have their inputs tied to their outputs during the setup phase; and 
capacitors, such as capacitor 22, can be provided between inverters for 
accomodating any differences between their individual threshold voltages. 
In FIG. 2 only the interstage capacitor 22 is shown, for it is not always 
necessary to incorporate such capacitance between the remaining stages. As 
is characteristic of logic inverters of the type described, the output of 
these units will go low when the input deviates from the threshold voltage 
in a positive direction and will go high when the deviation is in the 
opposite direction. This characteristic is illustrated in inverter 
transfer characteristic shown in FIG. 4 which shows V.sub.o vs. V.sub.in. 
It will be noted that any small change of the input from the trigger 
voltage, V.sub.t, will cause a considerable change in the output. The 
slope of the steep portion of the characteristic will be dependent on the 
particular way in which the element is manufactured. 
FIG. 5 shows a clock circuit which can be used to time the two phases of 
the measuring cycle. In this circuit a non-overlapping clock module 50 is 
driven by D-flop 52 whose input is from the multivibrator 53. As shown, 
the output of the clock module is the plus and minus potentials of 
.phi..sub.1, P.sub.1 and P.sub.1 -, and the plus and minus potentials of 
.phi..sub.2, P.sub.2 and P.sub.2 -. 
The operation of the measuring circuit of FIG. 2 may be considered by 
examining the charges on the capacitors C.sub.x, C.sub.o and C.sub.r 
during the two phases .phi..sub.1 and .phi..sub.2. 
During .phi..sub.1 the voltage on node 10 is held at the trigger voltage, 
V.sub.t1, and during .phi..sub.2 the voltage on node 10 is allowed to 
float at voltage V.sub.t2, as determined by the charges on the capacitors 
in the network. The charges on the capacitors are as follows: 
______________________________________ 
for .phi..sub.1 for .phi..sub.2 
______________________________________ 
Q.sub.x1 = C.sub.x (-V.sub.t1) 
Q.sub.x2 = C.sub.x (V.sub.s - V.sub.t2) 
Q.sub.o1 = C.sub.o (V.sub.s - V.sub.t1) 
Q.sub.o2 = C.sub.o (-V.sub.t2) 
Q.sub.r1 = C.sub.r (V.sub.o - V.sub.t1) 
Q.sub.r2 = C.sub.r (-V.sub.t2) 
Q.sub.y1 = C.sub.y (-V.sub.t1) 
Q.sub.y2 = C.sub.y (-V.sub.t2). 
If .DELTA.Q = Q.sub.1 - Q.sub.2 and .DELTA.V.sub.t = V.sub.t2 - V.sub.t1, 
then .DELTA.Q.sub.x = C.sub.x (-V.sub.s + .DELTA.V.sub.t), 
.DELTA.Q.sub.o = C.sub.o (V.sub.s + .DELTA.V.sub.t), 
.DELTA.Q.sub.r = C.sub.r (V.sub.o + .DELTA.V.sub.t), 
and .DELTA.Q.sub.y = C.sub.y (.DELTA.V.sub.t). 
______________________________________ 
Since the total change in the node 10 must be zero, then 
EQU .DELTA.Q.sub.x +.DELTA.Q.sub.o +.DELTA.Q.sub.r +.DELTA.Q.sub.y =0; 
and if 
EQU .SIGMA.C=C.sub.x +C.sub.o +C.sub.r +C.sub.y, 
then 
EQU C.sub.x (-V.sub.s +.DELTA.V.sub.t)+C.sub.o (V.sub.s 
+.DELTA.V.sub.t)+C.sub.r (V.sub.o +.DELTA.V.sub.t)+C.sub.y 
(.DELTA.V.sub.t)=0, 
and 
EQU V.sub.s (C.sub.o -C.sub.x)+C.sub.r V.sub.o +.SIGMA.C.DELTA.V.sub.t =0. 
Since .DELTA.V.sub.t =0 is the network condition defined as balance, and 
V.sub.o is a measure of C.sub.x ; 
##EQU1## 
Thus, it can be seen that the output voltage is a function of the variable 
capacitance C.sub.x plus a constant offset determined by the capacitance 
of C.sub.o. 
It will be evident to those skilled in the art that the capacitor C.sub.o 
and its associated switching elements can be omitted if it is not desired 
to offset the relationship between the output voltage and the indicated 
value of C.sub.x. 
It is also evident that the value of the stray capacitance C.sub.y does not 
affect the accuracy of the resulting measure of the variable capacitor 
since it does not appear as a term in the final relationship between 
C.sub.x and V.sub.o, as derived above. The stray capacitance, C.sub.y, 
does, however, affect the sensitivity. 
The MOSFET switches 44 and 46 will have capacitance between the gate, on 
one side, and the source and drain, respectively, on the other side. These 
capacitances will cause error, but that error can be minimized by using 
small transistors for this switching service and by using similar sizes so 
as to closely match them. 
The voltage V.sub.a on the non-inverting input of the amplifier 34 should 
be approximately equal to V.sub.s /2. If V.sub.a is not exactly equal to 
V.sub.s /2 the effect is only to introduce a small asymmetry in step size 
for raise steps as compared with lower steps in the integrator output 
V.sub.o. 
As has been stated, where the variable capacitor is a capacitive humidity 
sensor, it is desirable to have all capacitors in the measuring network on 
the same substrate and to construct them with the same plate area and the 
same dielectic constant. The area of the plates can be carefully 
controlled by photolithography, but the thickness of the dielectric and 
hence the dielectric constant is not as easily controlled. It can, 
however, be matched to better than 0.1% by known techniques which use the 
same substance for all capacitors in the network. Care must be exercised 
in completely sealing the capacitors C.sub.o and C.sub.r from humidity, 
but C.sub.x must allow moisture to quickly penetrate the dielectric in 
order to obtain fast response to humidity changes. 
The capacitor C.sub.x may be constructed as shown in FIG. 6 using well 
known integrated circuit techniques. In this structure the n-type silicon 
has a p+diffused region forming one plate of the capacitor. That plate is 
covered by the polyimide dielectric which is bounded by a field oxide. 
Over the dielectric is deposited an aluminum foil as the second plate of 
the capacitor. This foil is sufficiently thin so that it allows the water 
molecules to permeate the dielectric from the surrounding atmosphere after 
it has permeated the protective coating of polyimide covering the foil. 
The capacitors C.sub.o and C.sub.r can be constructed as shown in FIG. 7, 
in which the second electrode is constructed of a thick aluminum plate 
instead of a thin foil as in FIG. 6. The thick plate is designed to 
prevent the water molecules from permeating to the dielectric of these 
capacitors, for they must not be sensitive to changes in the relative 
humidity of the surrounding atmosphere. The polyimide protective coating 
shown in FIG. 6 can be omitted since it is not necessary to protect the 
top plate from contaminents. 
In applications where it is not possible to protect the capacitors C.sub.o 
and C.sub.r from the changes in humidity of the surrounding atmosphere, it 
is desirable to construct these capacitors differently so that they will 
not have a dielectric which changes its dielectric constant with changes 
in the humidity of the surroundings. For this type of service the 
capacitors C.sub.o and C.sub.r can be constructed as shown in FIG. 8 In 
that arrangement, it has been found useful to use SiO.sub.2 as the 
dielectric. That material is not humidity sensitive so there is no need to 
seal the capacitors from water vapor. Using a different dielectric as 
compared to that use for C.sub.x will, of course, cause the capacitors 
C.sub.o and C.sub.r to fail to track C.sub.x with changes in temperature 
and humidity. More importantly, it will cause the circuits to have 
different span and range magnitudes due to the fact that the capacitor 
C.sub.x is not being produced at the same time and by the same process as 
C.sub.o and C.sub.r and therefore can not be expected to have exactly the 
same characteristics. 
By way of example, C.sub.x can have a value of 8-10 pf, C.sub.o can have a 
value of 7 pf, and C.sub.r can have a value of 3 pf. The voltage V.sub.a 
can be 2.5 volts and V.sub.t will normally be approximately 2.5 volts. 
V.sub.s can be in the area of 5-6 volts. Clock frequencies on the order of 
8 Khz have been used so that the capacitors will be allowed to charge 
completely during each phase of the measuring cycle. Capacitor 22 can be 
20 pf and capacitor 30 can be 0.3 pf with capacitor 36 having a value of 
200 pf. The voltage V.sub.o will vary in a range between 1-5 volts which 
provides a desirable voltage range for use in measuring systems. 
In another form the present invention could use a digital counter coupled 
to a digital to analog converter in place of the integrating amplifier of 
FIG. 2. 
Still another form of the present invention can utilize an analog to 
digital converter at the output of the integrating amplifier of FIG. 2 
when it is desirable to obtain a digital readout. 
FIG. 9 illustrates a useful circuit for coupling the integrating amplifier 
of FIG. 2 to an analog to digital converter, such as a CMOS TSC7126 as 
manufactured by Teledyne Semiconductor and shown in their Data Acquisition 
Design Handbook of 1984, on page 7-73. 
This unit provides a digital readout of 2000 counts. In order to provide 
for a scale factor other than unity, circuitry is required to determine 
the reference voltage for the A/D converter to accomodate the scale 
factor. Also, it is necessary to accomodate the offset at the zero 
humidity point by introducing an appropriate voltage at the low input 
terminal, IN LO, of the 7126. The circuit of FIG. 9 is arranged to provide 
these accomodations and to provide them in such a way that there is no 
necessity for making more than one potentiometer adjustment when one is 
using capacitors C.sub.o and C.sub.r of the type shown in FIG. 8. This 
simplifies the manufacture of the circuit of FIG. 9 considerably, for it 
is only necessary to adjust the circuit at one value of relative humidity 
instead of two in calibrating the units so that they will be 
interchangeable. Separate adjustments at different humidities would 
normally be required for offset and range. 
The factors which must be kept in mind to understand the following 
explanation of the circuit of FIG. 9 are: 
1. The dielectric of the measuring capacitor C.sub.x is of different 
material (a polyimide) than the dielectric of C.sub.o and C.sub.r 
(SiO.sub.2). Thus, the capacitance of the measuring capacitor varies with 
humidity while the capacitance of the others do not. 
2. C.sub.o /C.sub.r is a constant for each circuit since the two capacitors 
are manufactured at the same time by the same process so that their 
characteristics are inherently the same. 
3. C.sub.x /C.sub.r varies from unit to unit due to variations in the 
manufacturing processes by which the two capacitors are made. 
4. The capacitance of C.sub.x at full scale (100% relative humidity) is 
designated as C.sub.x (100) and the capacitance of C.sub.x at 0% relative 
humidity is designated as C.sub.x (0). The ratio C.sub.x (100)/C.sub.x (0) 
is designated as .alpha.. 
5. .alpha. is a constant. 
6. A/D converters, such as the 7126, have differential inputs for both the 
measured variable and the reference voltage. 
It is evident from the above that it is desired to provide a circuit that 
can correct for C.sub.x /C.sub.r and, as stated, it is desired to do this 
with a single potentiometer. 
In FIG. 9 the offset of the range to be measured is accomodated by 
adjusting potentiometer tap 60a of potentiometer 60 to provide the 
required input to the IN LO terminal of the A/D converter 62, namely at 
pin 30. The potentiometer is supplied by a source of emf, 64, shown a 6 
volt source, which supplies the series circuit shown as including 
resistors 66 and 68 in series with the potentiometer 60 and a zener diode 
70. The zener diode is incorporated into the circuit to provide a negative 
power source for other components of the circuit. 
The following equation may be written to express the quantity C.sub.x 
(100)-C.sub.x (0), which shall be referred to as the gain G. 
EQU G=(.alpha.-1)C.sub.x (0) (V.sub.s)/C.sub.r 
Since V.sub.os, the output voltage of the circuit of FIG. 2 at 0% humidity, 
is as follows 
EQU V.sub.os =C.sub.x (0)-C.sub.o (V.sub.s)/C.sub.r 
then 
EQU C.sub.x (0)=(V.sub.os C.sub.r)/V.sub.s +C.sub.o, 
and substituting; 
EQU G=(.alpha.-1)V.sub.os +((.alpha.-1)C.sub.o)/C.sub.r V.sub.s. 
Since .alpha. and C.sub.o /C.sub.r are constants, the latter term in the 
above equation can be represented by a divider on V.sub.s. This is shown 
in FIG. 4 as the divider which consists of the resistors 72 and 74. Thus, 
the voltage introduced to the REF HI pin 36 over line 76 accomodates for 
the constant term of the equation. The first term is taken care of by 
resistor 78 which forms part of another divider circuit with resistor 72 
and thus also influences REF HI. REF LO, pin 35, is connected to circuit 
common, as shown. The result of the divider and resistor 78 which together 
provide the input to pin 36 is to accomodate the span of the measuring 
circuit to the span of the A/D converter so that the voltage V.sub.o which 
corresponds to 100% relative humidity, for example, will cause the readout 
of the 7126 to be full scale. 
The reference capacitor for the 7126 is shown as capacitor 90 and may have 
a value of 0.1 f. The external oscillator circuit provided for the 7126 is 
shown connected to pins 38, 39 and 40. This circuit includes the resistor 
92 of 18 K and the capacitor 94 of 56 pf. The required circuitry for the 
pins 27, 28 and 29 is shown as including the capacitor 96 of 0.15 f, the 
capacitor 98 of 0.24 f and the resistor 99 of 1.8 M. 
As shown in FIG. 9, the input V.sub.o from the output of the circuit of 
FIG. 2 is introduced to the IN HI pin 34 through resistor 100, which may 
be of 1M, and across the capacitor 102, which may be 0.002 f.