Semiconductor devices having buried metal silicide layers and methods of fabricating the same

A semiconductor device includes a substrate and a plurality of active pillars disposed on the substrate and spaced apart from each other by trenches. Each of the active pillars includes a buried metal silicide pattern and an active region stacked on the buried metal silicide pattern, and the active region includes impurity junction regions.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2012-0151669, filed on Dec. 24, 2012, in the Korean intellectual property Office, which is incorporated herein by reference in its entirety as set forth in full.

BACKGROUND

Embodiments of the present disclosure relate to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices having buried metal silicide layers and methods of fabricating the same.

As digital home appliances become smaller in size and mobile systems become wide-spread, semiconductor devices employed in the digital home appliances and the mobile systems have been continuously scaled down. Attempts to increase the device integration density in dynamic random access memory (DRAM) devices or flash memory devices including memory cells have typically resulted in the reduction of areas (planar areas) that the memory cells occupy. In general, a unit memory cell of the DRAM devices includes a cell transistor and a cell capacitor. The DRAM cell transistors may be formed in and/or on a semiconductor substrate and the DRAM cell capacitors may be stacked on the DRAM cell transistors to increase the integration density of the DRAM devices.

The DRAM cell transistors may be electrically connected to the DRAM cell capacitors through storage node contact plugs which are disposed between source regions of the DRAM cell transistors and bottom electrodes of the DRAM cell capacitors. Further, drain regions of the DRAM cell transistors may be electrically connected to bit lines through bit line contact plugs, and gate electrodes of the DRAM cell transistors may be electrically connected to word lines. Therefore, the bit lines and the word lines for transmitting electric signals may be disposed between the DRAM cell transistors and the DRAM cell capacitors. Thus, there may be some limitations in increasing the cell capacitance due to the presence of the bit lines and the word lines. Moreover, most of the DRAM cell transistors may be formed to have a planar configuration. In such a case, if a width of the word lines is reduced to increase the integration density of the DRAM devices, electrical resistance of the word lines may increase. As a result, RC delay time of the word lines may increase to degrade the performance of the DRAM devices. In addition, if the planar type cell transistors are scaled down, leakage current of the planar type cell transistors may abruptly increase to degrade the cell characteristics of the DRAM devices. Accordingly, vertical transistors have been proposed to solve or overcome the disadvantages of the planar transistors.

SUMMARY

Various embodiments are directed to semiconductor devices having buried metal silicide layers and methods of fabricating the same.

According to some embodiments, a semiconductor device includes a substrate and a plurality of active pillars disposed on the substrate to be spaced apart from each other by trenches. Each of the active pillars includes a buried metal silicide pattern and an active region stacked on the buried metal silicide pattern, and the active region includes impurity junction regions therein.

In some embodiments, the semiconductor device may further include a partial filling insulation layer disposed in the trenches. The partial filing insulation layer may be disposed between a bottom surface level of the trenches and a first height level located at the same level as bottom surfaces of the metal silicide patterns. The partial filing insulation layer may include a silicon oxide layer.

In some embodiments, the semiconductor device may further include capping insulation patterns disposed on respective ones of the active pillars. The capping insulation patterns may include a silicon nitride layer. The semiconductor device may further include spacers disposed on respective ones of sidewalls of the capping insulation patterns. The spacers may extend onto sidewalls of the active regions under the capping insulation patterns. The spacers may include a silicon oxide layer.

In some embodiments, the buried metal silicide patterns may include a cobalt silicide layer.

In some embodiments, the impurity junction regions in the active region may include an upper impurity region disposed in an upper portion of the active region and a lower impurity region disposed in a lower portion of the active region.

According to further embodiments, a semiconductor device includes a plurality of active pillars disposed on a substrate to be spaced apart from each other by first trenches and second trenches which are alternately arrayed. Each of the active pillars includes a buried metal silicide pattern and an active region which are sequentially stacked. The first trenches are filled with a full filling insulation layer. A partial filling insulation layer is disposed in the second trenches. The partial filling insulation layer is disposed between a bottom surface level of the second trenches and a first height level located at the same level as bottom surfaces of the buried metal silicide patterns. Spacers are disposed on respective ones of sidewalls of the active regions in the second trenches. The active region includes impurity junction regions therein.

In some embodiments, the semiconductor device may further include capping insulation patterns on respective ones of the active pillars.

In some embodiments, the buried metal silicide patterns may include a cobalt silicide layer.

According to further embodiments, a semiconductor device includes a plurality of active pillars disposed on a substrate to be spaced apart from each other by trenches. Each of the active pillars includes a buried metal silicide pattern and an active region which are sequentially stacked. A partial filling insulation layer is disposed in the trenches. The partial filling insulation layer is disposed between a bottom surface level of the trenches and a predetermined height level on the bottom surface level. Insulation patterns are disposed in respective ones of the trenches to provide air gaps between sidewalls of the buried metal silicide patterns. The sidewalls of the metal silicide patterns are exposed to the air gaps, and each of the active regions includes impurity junction regions therein.

According to further embodiments, a semiconductor device includes a plurality of active pillars disposed on a substrate to be spaced apart from each other by first trenches and second trenches which are alternately arrayed. Each of the active pillars includes a buried metal silicide pattern and an active region which are sequentially stacked. A full filling insulation layer fills the first trenches. A partial filling insulation layer is disposed in the second trenches. The partial filling insulation layer is disposed between a bottom surface level of the second trenches and a first height level located at the same level as bottom surfaces of the buried metal silicide patterns. Insulation patterns are disposed in respective ones of the second trenches to provide air gaps between sidewalls of the buried metal silicide patterns in the second trenches. The active region includes impurity junction regions therein.

According to further embodiments, a method of fabricating a semiconductor device includes forming trenches in a substrate to define a plurality of active pillars spaced apart from each other by the trenches, forming a partial filling insulation layer which fills lower regions in the trenches, forming a first sacrificial layer in the trenches on the partial filling insulation layer, forming spacers on respective ones of sidewalls of the active pillars exposed by the trenches on the first sacrificial layer, removing the first sacrificial layer to expose sidewalls of the active pillars between a top surface of the partial filling insulation layer and bottom surfaces of the spacers, forming a metal layer contacting the exposed sidewalls of the active pillars, applying a silicidation process to the substrate including the metal layer to form metal silicide patterns in respective ones of the active pillars, and removing the metal layer remaining in the trenches.

In some embodiments, the partial filling insulation layer may be formed to be in direct contact with bottom surfaces and lower sidewalls of the trenches.

In some embodiments, the partial filling insulation layer may be formed of a silicon oxide layer and the first sacrificial layer may be formed of a carbon layer or a photoresist layer.

In some embodiments, the method may further include forming a second sacrificial layer in the trenches between the metal silicide patterns, forming insulation patterns in respective ones of the trenches to cover the second sacrificial layer, and removing the second sacrificial layer to form air gaps in the trenches between the metal silicide patterns.

According to further embodiments, a method of fabricating a semiconductor device includes forming first trenches and second trenches in a substrate to define a plurality of active pillars spaced apart from each other by the first and second trenches, forming a full filling insulation layer which fills the first and second trenches, selectively recessing the full filling insulation layer in the second trenches to form a partial filling insulation layer, forming a first sacrificial layer in the second trenches on the partial filling insulation layer, forming spacers on respective ones of sidewalls of the active pillars exposed by the second trenches on the first sacrificial layer, removing the first sacrificial layer to expose sidewalls of the active pillars between a top surface of the partial filling insulation layer in the second trenches and bottom surfaces of the spacers in the second trenches, forming a metal layer contacting the exposed sidewalls of the active pillars, applying a silicidation process to the substrate including the metal layer to form metal silicide patterns in respective ones of the active pillars, and removing the metal layer remaining after the silicidation process. The first trenches and the second trenches are alternately arrayed.

In some embodiments, selectively recessing the full filling insulation layer in the second trenches may be performed using a mask pattern that covers the full filling insulation layer in the first trenches and exposes the full filling insulation layer in the second trenches. The mask pattern may be formed of a polysilicon layer.

In some embodiments, the partial filling insulation layer may be formed to be in direct contact with bottom surfaces and lower sidewalls of the second trenches.

In some embodiments, the partial filling insulation layer may be formed of a silicon oxide layer and the first sacrificial layer may be formed of a carbon layer or a photoresist layer.

In some embodiments, the method may further include forming a second sacrificial layer in the second trenches between the metal silicide patterns, forming insulation patterns in respective ones of the second trenches to cover the second sacrificial layer, and removing the second sacrificial layer to form air gaps in the second trenches between the metal silicide patterns.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a cross sectional view illustrating a general vertical transistor. As illustrated inFIG. 1, a vertical transistor100may be configured to include a drain region112disposed in a lower sidewall of a semiconductor substrate110and a source region114disposed in an upper sidewall of a semiconductor substrate110. A channel region116may be defined along a vertical direction between the drain region112and the source region114, and a gate insulation layer118and a gate electrode120may be sequentially stacked on a sidewall surface of the channel region116. If the vertical transistor100is employed as a cell transistor of a DRAM device, the drain region112may be electrically connected to a bit line and the source region114may be electrically connected to a storage node of a cell capacitor.

In such a case, the bit line may be buried in a lower portion of the semiconductor substrate110. Thus, the storage node may be freely disposed on the vertical transistor100without restriction of the bit line. That is, even though the integration density of the DRAM device increases, use of the vertical transistor100may prevent the cell capacitance of the DRAM device from being reduced. Further, since the bit line is buried in the semiconductor substrate110, the parasitic capacitance of the bit line may be reduced and the height of the storage node may also be reduced without degradation of the cell capacitor.

In order to fabricate the vertical transistor100, a side junction region, for example, the drain region112, is formed in a lower sidewall of the semiconductor substrate110. To form the drain region112, a side contact opening process may be performed to expose the lower sidewall of the semiconductor substrate110. The side contact opening process may be performed using various techniques. For example, one of the side contact opening processes is taught in US patent publication No. 2012/0208364 A1 to Rouh et al., entitled “Method for Opening One-side Contact Region of Vertical Transistor and Method for Fabricating One-side Junction Region Using the Same”.

FIG. 2is a cross sectional view illustrating a semiconductor device according to an embodiment. Referring toFIG. 2, a semiconductor device200according to an embodiment may include a plurality of active pillars230disposed on a substrate210and uniformly spaced apart from each other by trenches220. The substrate210may include a silicon substrate, but embodiments are not limited thereto. In some embodiments, the active pillars230may extend from the substrate210. That is, the active pillars230and the substrate210may constitute a single unified body without any heterogeneous junction therebetween. In such a case, a pitch size and a height of the active pillars230may be defined by the trenches220which are formed by partially removing the substrate210.

The trenches220may have a uniform dimension, and the active pillars230may also have a uniform dimension. For example, a depth of the trenches220corresponding to a height of the active pillars230may be within the range of about 2200 Å to about 3200 Å, and a width of the active pillars230may be within the range of about 14 nm to about 18 nm. Further, a width of the trenches220corresponding to a space of the active pillars230may be within the range of about 13 nm to about 18 nm.

Lower portions in the trenches220between a bottom level H0 of the trenches220and a first height level H1 above the bottom level H0 may be filled with a partial filling insulation layer242. In some embodiments, the partial filling insulation layer242may include a silicon oxide layer. As such, lowermost portions232of adjacent active pillars230may be insulated from each other by the partial filling insulation layer242.

Portions of the active pillars230between the first height level H1 and a second height level H2 above the first height level H1 may correspond to metal silicide regions234. Each of the metal silicide regions234may be filled with metal silicide patterns235. In some embodiments, each of the metal silicide patterns235may include a cobalt silicide (CoSi) layer. The metal silicide patterns235may be distributed from the first height level H1 to the second height level H2 in the active pillars230. Thus, sidewalls of the metal silicide patterns235may be exposed by the trenches220.

Each of the active pillars230may further include a transistor active region236disposed on the metal silicide region234. The transistor active region236may include a drain region251disposed in a lower portion thereof and a source region252disposed in an upper portion thereof. Although not indicated in the drawing, the transistor active region236may also include a channel region between the drain region251and the source region252.

Capping insulation patterns260may be disposed on the active pillars230. In some embodiments, the capping insulation patterns260may be silicon nitride patterns. Spacers270may be disposed on sidewalls of the capping insulation patterns260and the transistor active regions236. In some embodiments, the spacers270may include a silicon oxide layer. In the semiconductor device200according to the present embodiment, the metal silicide patterns235may be used as buried bit lines.

FIG. 3is a cross sectional view illustrating a semiconductor device according to another embodiment. Referring toFIG. 3, a semiconductor device300according to the present embodiment may include first trenches321and second trenches322which are alternately arrayed in a substrate310. The semiconductor device300may further include active pillars330disposed between the first trenches321and the second trenches322.

In some embodiments, the active pillars330may extend from the substrate310. That is, the active pillars330and the substrate310may constitute a single unified body without any heterogeneous junction therebetween. In such a case, a pitch size and a height of the active pillars330may be defined by the first and second trenches321and322which are formed by partially removing the substrate310.

The first and second trenches321and322may have uniform dimensions, and the active pillars330may also have uniform dimensions. For example, a depth of the first and second trenches321and322(corresponding to a height of the active pillars330) may be within the range of about 2200 Å to about 3200 Å, and a width of the active pillars330may be within the range of about 14 nm to about 18 nm. Further, a width of the first and second trenches321and322(corresponding to a space of the active pillars330) may be within the range of about 13 nm to about 18 nm.

The first trenches321may be completely filled with a full filling insulation layer340, whereas lower portions of the second trenches322between a bottom level H0 of the second trenches322and a first height level H1 on the bottom level H0 may be filled with a partial filling insulation layer342. The full filling insulation layer340and the partial filling insulation layer342may be the same material. In some embodiments, the full filling insulation layer340and the partial filling insulation layer342may be a silicon oxide layer.

As a result, lowermost regions332of the adjacent active pillars330may be insulated from each other by the partial filling insulation layer342or the full filling insulation layer340. As described above, while the partial filling insulation layer342may fill only a lower portion of each of the second trenches322, the full filling insulation layer340may completely fill first trenches321. Thus, in an embodiment in which the width of the active pillars330is relatively low, the full filling insulation layer340may support the active pillars330to suppress a leaning phenomenon of the active pillars330.

Portions of the active pillars330between the first height level H1 and a second height level H2 above the first height level H1 may correspond to metal silicide regions334, and each of the metal silicide regions334may be filled with a metal silicide pattern335. In some embodiments, each of the metal silicide patterns335may include a cobalt silicide (CoSi) layer. The metal silicide patterns335may be distributed from the first height level H1 to the second height level H2 in the active pillars330. Thus, in embodiments, one sidewall of each metal silicide pattern335may be exposed by the second trench322, and the opposite sidewall of each metal silicide pattern335may be in contact with the full filling insulation layer340filling the first trenches321.

Each of the active pillars330may further include a transistor active region336disposed on the metal silicide region334, and the transistor active region336may include a drain region351disposed in a lower portion thereof and a source region352disposed in an upper portion thereof. Although not indicated in the drawing, the transistor active region336may also include a channel region between the drain region351and the source region352.

Capping insulation patterns360may be disposed on respective ones of the active pillars330. In some embodiments, the capping insulation patterns360may be silicon nitride patterns. One of both sidewalls of each capping insulation pattern360and one of both sidewalls of each the transistor active regions336may be covered with a spacer370. In some embodiments, the spacer370may include a silicon oxide layer. In the semiconductor device300according to the present embodiment ofFIG. 3, the metal silicide patterns335may be used as buried bit lines.

FIG. 4is a cross sectional view illustrating a semiconductor device according to still another embodiment. Referring toFIG. 4, a semiconductor device400according to the present embodiment may include a plurality of active pillars430disposed on a substrate410and uniformly spaced apart from each other by trenches420. The substrate410may include a silicon substrate, but embodiments are not limited thereto.

In some embodiments, the active pillars430may extend upward from the substrate410. That is, the active pillars430and the substrate410may constitute a single unified body without any heterogeneous junction therebetween. In such an embodiment, a pitch size and a height of the active pillars430may be defined by the trenches420which are formed by partially removing the substrate410.

The trenches420may have uniform dimensions, and the active pillars430may also have uniform dimensions. For example, a depth of the trenches420corresponding to a height of the active pillars430may be within the range of about 2200 Å to about 3200 Å, and a width of the active pillars430may be within the range of about 14 nm to about 18 nm. Further, a width of the trenches420corresponding to a space of the active pillars430may be within the range of about 13 nm to about 18 nm.

Lower portions in the trenches420between a bottom level H0 of the trenches420and a first height level H1 above the bottom level H0 may be filled with a partial filling insulation layer442. In some embodiments, the partial filling insulation layer442may include a silicon oxide layer. As such, lowermost regions432of the adjacent active pillars430may be insulated from each other by the partial filling insulation layer442.

Portions of the active pillars430between the first height level H1 and a second height level H2 above the first height level H1 may correspond to metal silicide regions434. Each of the metal silicide regions434may be filled with metal silicide patterns435. In some embodiments, each of the metal silicide patterns435may include a cobalt silicide (CoSi) layer. The metal silicide patterns435may be distributed from the first height level H1 to the second height level H2 in the active pillars430. Thus, sidewalls of the metal silicide patterns435may be exposed by the trenches420.

Each of the active pillars430may further include a transistor active region436disposed on the metal silicide region434. The transistor active region436may include a drain region451disposed in a lower portion thereof and a source region452disposed in an upper portion thereof. Although not indicated in the drawing, the transistor active region436may also include a channel region between the drain region451and the source region452.

Capping insulation patterns460may be disposed on the active pillars430. In some embodiments, the capping insulation patterns460may be silicon nitride patterns.

An insulation pattern470having a ‘U’-shaped vertical cross section may be disposed in each of the trenches420, and a bottom surface of the ‘U’-shaped insulation pattern470may be located at substantially the same level as the second height level H2. Thus, air gaps480may exist between sidewalls of the metal silicide patterns435. Specifically, each of the insulation patterns470may include spacer-shaped sidewalls covering sidewalls of the adjacent transistor active regions436as well as sidewalls of the adjacent capping insulation patterns460, and a base portion connecting lower ends of the spacer-shaped sidewalls to each other. Thus, the air gaps480may be provided between the base portions of the insulation patterns470and the partial filling insulation layer442.

That is, each of the air gaps480may be surrounded by a top surface of the partial filling insulation layer442, sidewalls of the pair of adjacent metal silicide patterns435, and a bottom surface of the insulation pattern470. Accordingly, the air gaps480may exist between the metal silicide patterns435. As a result, a parasitic capacitance or a coupling capacitance between the adjacent metal silicide patterns435may be reduced because the air in the air gaps480has a lower dielectric constant than other insulation materials such as a silicon oxide material and a silicon nitride material. In some embodiments, each of the insulation patterns470may include a silicon oxide layer. In a semiconductor device400according to the present embodiment, the metal silicide patterns435may be used as buried bit lines.

FIG. 5is a cross sectional view illustrating a semiconductor device according to yet another embodiment. Referring toFIG. 5, a semiconductor device500according to the present embodiment may include first trenches521and second trenches522which are alternately arrayed in a substrate510. The semiconductor device500may further include active pillars530disposed between the first trenches521and the second trenches522.

In some embodiments, the active pillars530may extend from the substrate510. That is, the active pillars530and the substrate510may constitute a single unified body without any heterogeneous junction therebetween. In such a case, a pitch size and a height of the active pillars530may be defined by the first and second trenches521and522which are formed by partially removing the substrate510.

The first and second trenches521and522may have uniform dimensions, and the active pillars530may also have uniform dimensions. For example, a depth of the first and second trenches521and522(corresponding to a height of the active pillars530) may be within the range of about 2200 Å to about 3200 Å, and a width of the active pillars530may be within the range of about 14 nm to about 18 nm. Further, a width of the first and second trenches521and522(corresponding to spaces between the active pillars530) may be within the range of about 13 nm to about 18 nm.

The first trenches521may be completely filled with a full filling insulation layer540, while lower portions of the second trenches522between a bottom level H0 of the second trenches522and a first height level H1 on the bottom level H0 may be filled with a partial filling insulation layer542. The full filling insulation layer540and the partial filling insulation layer542may be the same material. In some embodiments, the full filling insulation layer540and the partial filling insulation layer542may be a silicon oxide layer.

As such, lowermost regions532of the adjacent active pillars530may be insulated from each other by the partial filling insulation layer542or the full filling insulation layer540. As described above, whereas the partial filling insulation layer542may fill only a portion of each of the second trenches522, the full filling insulation layer540may completely fill the first trenches521. Thus, in an embodiment where the width of the active pillars530is relatively low, the full filling insulation layer540may support the active pillars530to suppress a leaning phenomenon of the active pillars530.

Portions of the active pillars530between the first height level H1 and a second height level H2 above the first height level H1 may correspond to metal silicide regions534, and each of the metal silicide regions534may be filled with a metal silicide pattern535. In some embodiments, each of the metal silicide patterns535may include a cobalt silicide (CoSi) layer. The metal silicide patterns535may be distributed from the first height level H1 to the second height level H2 in the active pillars530. Thus, one sidewall of each metal silicide pattern535may be exposed by the second trench522, and the opposite sidewall of each metal silicide pattern535may be in contact with the full filling insulation layer540filling the first trenches521.

Each of the active pillars530may further include a transistor active region536disposed on the metal silicide region534, and the transistor active region536may include a drain region551disposed in a lower portion thereof and a source region552disposed in an upper portion thereof. Although not indicated in the drawing, the transistor active region536may also include a channel region between the drain region551and the source region552.

Capping insulation patterns560may be disposed on the active pillars530. In some embodiments, the capping insulation patterns560may be silicon nitride patterns.

An insulation pattern570having a ‘U’-shaped vertical cross section may be disposed in each of the second trenches542, and a bottom surface of the ‘U’-shaped insulation pattern570may be located at substantially the same level as the second height level H2. Thus, air gaps580may be provided in the second trenches522between sidewalls of the metal silicide patterns535. Specifically, each of the insulation patterns570may include spacer-shaped sidewalls covering sidewalls of the adjacent transistor active regions536as well as sidewalls of the adjacent capping insulation patterns560, and a base portion connecting lower ends of the spacer-shaped sidewalls to each other. Thus, the air gaps580may be provided between the base portions of the insulation patterns570and the partial filling insulation layer542.

That is, each of the air gaps580may be surrounded by a top surface of the partial filling insulation layer542, sidewalls of the pair of adjacent metal silicide patterns535, and a bottom surface of the insulation pattern570. Accordingly, the air gaps580may exist between the metal silicide patterns535. As a result, a parasitic capacitance or a coupling capacitance between the adjacent metal silicide patterns535may be reduced because the air in the air gaps580has a lower dielectric constant than other insulation materials such as a silicon oxide material and a silicon nitride material. In some embodiments, each of the insulation patterns570may include a silicon oxide layer. In a semiconductor device500according to the present embodiment, the metal silicide patterns535may be used as buried bit lines.

FIGS. 6 to 12are cross sectional views illustrating a method of fabricating a semiconductor device according to an embodiment. Referring toFIG. 6, a plurality of capping insulation patterns260may be formed on a substrate210to expose portions of the substrate210. The substrate210may be, for example, a silicon substrate. The capping insulation patterns260may be formed of a silicon nitride layer. The substrate210may be partially etched using the capping insulation patterns260as etch masks to form a plurality of trenches220which are uniformly spaced apart from each other.

The trenches220may define a plurality of active pillars230which are uniformly spaced apart from each other. That is, a width, a height and a volume of the active pillars230may be defined by the trenches220which are formed by partially removing the substrate210. The trenches220may be formed to have uniform dimensions, and the active pillars230may also be formed to have uniform dimensions. For example, each of the trenches220may be formed to have a depth of about 2200 Å to about 3200 Å. The depth of the trenches220may correspond to a height of the active pillars230.

Each of the active pillars230may be formed to have a width of about 14 nm to about 18 nm. In addition, each of the trenches220may be formed to have a width of about 13 nm to about 18 nm. The width of the trenches220may correspond to a space between the active pillars230.

Referring toFIG. 7, a partial filling insulation layer242may be formed to fill lower portions in the trenches220between a bottom level H0 of the trenches220and a first height level H1 above the bottom level H0. In some embodiments, the partial filling insulation layer242may be formed of a silicon oxide layer. Specifically, a buried insulation layer may be formed to completely fill all the trenches220. The buried insulation layer may then be planarized to expose top surfaces of the capping insulation patterns260. Subsequently, a portion of the buried insulation layer may be recessed to form the partial filling insulation layer242whose top surface is located at substantially the same level as the first height level H1. After planarization of the buried insulation layer, a portion of the buried insulation layer may be recessed using a wet etch-back process. Lowermost regions232of the active pillars230may be defined by formation of the partial filling insulation layer242. That is, the lowermost regions232of the active pillars230may be defined between the first height level H1 and the bottom level H0.

Referring toFIG. 8, a sacrificial layer280may be formed to fill the trenches220between the first height level H1 and a second height level H2 above the first height level H1. In some embodiments, the sacrificial layer280may be formed of a carbon layer or a photoresist layer. Specifically, a sacrificial material layer may be formed on the partial filling insulation layer242to completely fill all the trenches220. The sacrificial material layer may then be planarized and recessed to form the sacrificial layer280whose top surface is located at substantially the same level as the second height level H2. The planarization and recession of the sacrificial material layer may be performed using an etch-back process.

Metal silicide regions234of the active pillars230may be defined by formation of the sacrificial layer280. That is, the metal silicide regions234of the active pillars230may be defined between the first height level H1 and the second height level H2, which corresponds to the location of sacrificial layer280. Portions of the active pillars230above the metal silicide regions234may be defined as transistor active regions236. That is, the transistor active regions236may be defined in the active pillars230between the second height level H2 and a third height level H3 located at the same level as top surfaces of the active pillars230.

Referring toFIGS. 9 and 10, a spacer insulation layer272may be formed on an entire surface of the substrate including the sacrificial layer280. The spacer insulation layer272may be conformally formed to have a uniform thickness on top surfaces and sidewalls of the capping insulation patterns260, sidewalls of the transistor active regions236, and a top surface of the sacrificial layer280. In some embodiments, the spacer insulation layer272may be formed of a silicon oxide layer, for example, an ultra low temperature oxide (ULTO) layer.

The spacer insulation layer272may be etched back to expose the top surfaces of the capping insulation patterns260and the top surface of the sacrificial layer280. As a result, spacers270may be formed on the sidewalls of the capping insulation patterns260and the sidewalls of the transistor active regions236. That is, the spacers270may be formed between the second height level H2 and a top surface level of the capping insulation patterns260. The top surface of the sacrificial layer280may be exposed in the trenches220after formation of the spacers270.

Referring toFIG. 11, the sacrificial layer280exposed by the spacers270may be removed. In an embodiment where the sacrificial layer280is formed of a carbon layer or a photoresist layer, the sacrificial layer280may be removed by an ashing process using an oxygen gas. After the sacrificial layer280is removed, sidewalls of the metal silicide regions234between the first and second height levels H1 and H2 may be exposed in the trenches220. In contrast, the sidewalls of the lowermost regions232may be covered with the partial filling insulation layer242, and the sidewalls of the transistor active regions236may be covered by the spacers270.

Referring toFIG. 12, a metal layer290may be formed in the trenches220. The metal layer290may be formed of a cobalt (Co) layer. The metal layer290may be formed to directly contact the sidewalls of the metal silicide regions234of the active pillars230, and the other regions of the active pillars230may be separated from the metal layer290by the spacers270and the partial filling insulation layer242. Subsequently, a thermal treatment process may be applied to the substrate including the metal layer290to perform silicidation of the metal silicide regions234. As a result, metal silicide patterns235may be formed in the metal silicide regions234. After the metal silicide patterns235are formed, the remaining metal layer290may be removed.

FIGS. 13,14and15are cross sectional views illustrating a method of fabricating a semiconductor device according to another embodiment. The present embodiment will be described in conjunction with a method of fabricating a semiconductor device including the air gaps480illustrated inFIG. 4.

First, the same processes as described with reference toFIGS. 6 to 12may be performed to obtain a resultant illustrated inFIG. 13. As a result, trenches420may be formed in a substrate410to define active pillars430that vertically extend from the substrate410, and each of the active pillars430may be formed to include a lowermost region432, a metal silicide region434and a transistor active region436which are sequentially stacked. The lowermost region432may be defined between a bottom level H0 of the trenches420and a first height level H1 above the bottom level H0, the metal silicide region434may be defined between the first height level H1 and a second height level H2 above the first height level H1, and the transistor active region436may be defined between the second height level H2 and a third height level H3 above the second height level H2.

Further, a partial filling insulation layer442may be formed to fill lowermost regions in the trenches420, and spacers472may be formed on sidewalls of transistor active regions436and sidewalls of capping insulation patterns460stacked on the active pillars430. Metal silicide patterns435may be formed in the metal silicide regions434, and sidewalls of the metal silicide patterns435may be exposed in the trenches420.

As illustrated inFIG. 14, a sacrificial layer482may be formed on the partial filling insulation layer442. The sacrificial layer482may be formed to have the same thickness as the metal silicide patterns435. Thus, after the sacrificial layer482is formed, sidewalls of the metal silicide patterns435may be in direct contact with the sacrificial layer482. In some embodiments, the sacrificial layer482may be formed of a carbon layer or a photoresist layer. The sacrificial layer482may be formed by depositing a sacrificial material layer on an entire surface of the substrate including the exposed metal silicide patterns435to fill the trenches420and by removing upper portions of the sacrificial material layer with an etch-back process.

As illustrated inFIG. 15, insulation patterns470may then be formed on the sacrificial layer482in the trenches420. The insulation patterns470may be formed of the same material layer, for example, a silicon oxide layer as the spacers472illustrated inFIG. 14. In more detail, the insulation patterns470may be formed of an ultra low temperature oxide (ULTO) layer. The insulation patterns470may be formed to conformally cover sidewalls of the capping insulation patterns460, sidewalls of the transistor active regions436, and a top surface of the sacrificial layer482.

After the insulation patterns470are formed, the sacrificial layer482under the insulation patterns470may be removed to form the air gaps480illustrated inFIG. 4. In an embodiment in which the sacrificial layer482is formed of a carbon layer or a photoresist layer, the sacrificial layer482may be removed by an ashing process using an oxygen gas. Although not shown in the drawings, portions of the insulation patterns470may be etched to expose a portion of the sacrificial layer482before the sacrificial layer482is removed.

FIGS. 16 to 23are cross sectional views illustrating a method of fabricating a semiconductor device according to still another embodiment. The present embodiment will be described in conjunction with a method of fabricating a semiconductor device having a structure in which one of a pair of adjacent trenches is completely filled with a single insulation layer, as illustrated inFIG. 3.

Referring toFIG. 16, a plurality of capping insulation patterns patterns360may be formed on a substrate310to expose portions of the substrate310. The substrate310may be, for example, a silicon substrate. The capping insulation patterns360may be formed of a silicon nitride layer. The substrate310may be partially etched using the capping insulation patterns360as etch masks to form first trenches321and second trenches322which are alternately arrayed in the substrate310and uniformly spaced apart from each other.

The first and second trenches321and322may define a plurality of active pillars330disposed therebetween. A width, a height and a volume of the active pillars330may be defined by the first and second trenches321and322which are formed by removing portions of the substrate310. The first and second trenches321and322may be formed to have uniform dimensions, and the active pillars330may also be formed to have uniform dimensions. For example, each of the first and second trenches321and322may be formed to have a depth of about 2200 Å to about 3200 Å.

The depth of the first and second trenches321and322may correspond to a height of the active pillars330. Further, each of the active pillars330may be formed to have a width of about 14 nm to about 18 nm. In addition, each of the first and second trenches321and322may be formed to have a width of about 13 nm to about 18 nm. The width of the first and second trenches321and322may correspond to a space between the active pillars330.

Referring toFIG. 17, after the first and second trenches321and322are formed, a full filling insulation layer340may be formed to completely fill the first and second trenches321and322. In some embodiments, the full filling insulation layer340may be formed of a silicon oxide layer, for example, a ULTO layer. The full filling insulation layer340may be formed by depositing an insulation layer on an entire surface of the substrate including the trenches321and322and by planarizing the insulation layer to expose top surfaces of the capping insulation patterns360.

After formation of the full filling insulation layer340, a mask pattern390may be formed on the substrate having the full filling insulation layer340. The mask pattern390may be formed to cover the full filling insulation layer340in first trenches321and to have openings392that expose the full filling insulation layer340in second trenches322. The mask pattern390may be formed of a material layer having an etch selectivity with respect to the capping insulation patterns360and the full filling insulation layer340. For example, when the capping insulation patterns360are formed of a silicon nitride layer and the full filling insulation layer340is formed of a silicon oxide layer, the mask pattern390may be formed of a polysilicon layer.

Referring toFIG. 18, the full filling insulation layer340in the second trenches322may be selectively etched back using the mask pattern390as an etch mask, thereby forming a partial filling insulation layer342that remains in the second trenches322between a bottom level H0 of the second trenches322and a first height level H1 above the bottom level H0. As a result, lowermost regions332of the active pillars330may be defined by formation of the partial filling insulation layer342. That is, the lowermost regions332of the active pillars330may be defined between the bottom level H0 of the second trenches322and the first height level H1 coplanar with a top surface of the partial filling insulation layer342.

The full filling insulation layer340in the second trenches322may be selectively etched back using a wet etch-back process. As a result, the first trenches321may be completely filled with the full filling insulation layer340, and the second trenches322may be partially filled with the partial filling insulation layer342. After the partial filling insulation layer342is formed, the mask pattern390may be removed.

Referring toFIG. 19, a sacrificial layer380may be formed in the second trenches322between the first height level H1 and a second height level H2 above the first height level H1. In some embodiments, the sacrificial layer380may be formed of a carbon layer or a photoresist layer. Specifically, a sacrificial material layer may be formed to completely fill all the second trenches322on the partial filling insulation layer342. The sacrificial material layer may then be planarized and recessed to form the sacrificial layer380whose top surface is located at substantially the same level as the second height level H2. The planarizing and recessing the sacrificial material layer may be performed using an etch-back process.

Metal silicide regions334of the active pillars330may be defined by formation of the sacrificial layer380. That is, the metal silicide regions334of the active pillars330may be defined between the first height level H1 and the second height level H2. The active pillars330on the metal silicide regions334may be defined as transistor active regions336. That is, the transistor active regions336may be defined in the active pillars330between the second height level H2 and a third height level H3 located at the same level as top surfaces of the active pillars330.

Referring toFIG. 20, a spacer insulation layer372may be formed on an entire surface of the substrate including the sacrificial layer380. The spacer insulation layer372may be conformally formed to uniformly cover top surfaces of the capping insulation patterns360and the full filling insulation layer340, sidewalls of the transistor active regions336and the capping insulation patterns360exposed in the second trenches322, and a top surface of the sacrificial layer380. In some embodiments, the spacer insulation layer372may be formed of a silicon oxide layer, for example, an ultra low temperature oxide (ULTO) layer.

Referring toFIG. 21, the spacer insulation layer372may be etched back to expose the top surfaces of the capping insulation patterns360, the top surface of the full filling insulation layer340and the top surface of the sacrificial layer380. As a result, spacers370may be formed on the sidewalls of the capping insulation patterns360and the sidewalls of the transistor active regions336which are exposed by the second trenches322. That is, the spacers370may be formed to cover sidewalls of the second trenches322above the sacrificial layer380.

Referring toFIG. 22, the sacrificial layer380exposed by the spacers370may be removed. In an embodiment where the sacrificial layer380is formed of a carbon layer or a photoresist layer, the sacrificial layer380may be removed by an ashing process using an oxygen gas. After the sacrificial layer380is removed, sidewalls of the metal silicide regions334between the first and second height levels H1 and H2 may be exposed in the second trenches322. In contrast, the sidewalls of the lowermost regions332of the active pillars330may be still covered with the partial filling insulation layer342, and the sidewalls of the transistor active regions336may be still covered with the spacers370.

Referring toFIG. 23, a metal layer395may be formed in the second trenches322. The metal layer395may be formed of a cobalt (Co) layer. The metal layer395may be formed to directly contact the sidewalls of the metal silicide regions334of the active pillars330, and the other regions of the active pillars330may be separated from the metal layer395by the spacers370and the partial filling insulation layer342.

Subsequently, a thermal treatment process may be applied to the substrate including the metal layer395to perform silicidation of the metal silicide regions334. As a result, metal silicide patterns335may be formed in the metal silicide regions334. After the metal silicide patterns335are formed, the remaining metal layer395may be removed.

FIGS. 24,25and26are cross sectional views illustrating a method of fabricating a semiconductor device according to yet another embodiment. The present embodiment will be described in conjunction with a method of fabricating a semiconductor device having a structure in which one of a pair of adjacent trenches is completely filled with a single insulation layer and the other of the pair of adjacent trenches includes an air gap therein, as illustrated inFIG. 5.

First, the same processes as described with reference toFIGS. 16 to 23may be performed to obtain the structure illustrated inFIG. 24. As a result, first trenches521and second trenches522, which are alternately arrayed, may be formed in a substrate510to define active pillars530that vertically extend from the substrate510, and each of the active pillars530may be formed to include a lowermost region532, a metal silicide region534and a transistor active region536which are sequentially stacked. The lowermost region532may be defined between a bottom level H0 of the first and second trenches521and522and a first height level H1 above the bottom level H0, the metal silicide region534may be defined between the first height level H1 and a second height level H2 above the first height level H1, and the transistor active region536may be defined between the second height level H2 and a third height level H3 above the second height level H2.

While the first trenches521are completely filled with a full filling insulation layer540, the second trenches522may be partially filled with a partial filling insulation layer542. Specifically, the partial filling insulation layer542may be buried in the second trenches522between the bottom level H0 and the first height level H1. Thus, one sidewall of the lowermost region532of the active pillar530may be covered with the full filling insulation layer540in the first trench521, and the other sidewall of the lowermost region532of the active pillar530may be covered with the partial filling insulation layer542in the second trench522.

Metal silicide patterns535may be formed in the metal silicide regions534of the active pillars530. Further, spacers572may be formed on sidewalls of the transistor active regions536and sidewalls of the capping insulation patterns560stacked on the active pillars530. Accordingly, sidewalls of the metal silicide patterns535may be exposed in the second trenches522.

As illustrated inFIG. 25, a sacrificial layer582may be formed on the partial filling insulation layer542in the second trenches522. The sacrificial layer582may be formed to have the same thickness as the metal silicide patterns535. Thus, after the sacrificial layer582is formed, sidewalls of the metal silicide patterns535may be in direct contact with the sacrificial layer582in the second trenches522and sidewalls of the metal silicide patterns535may be in direct contact with the full filling insulation layer540in the first trenches521. In some embodiments, the sacrificial layer582may be formed of a carbon layer or a photoresist layer. The sacrificial layer582may be formed by depositing a sacrificial material layer on an entire surface of the substrate including the exposed metal silicide patterns535to fill the second trenches522, and by recessing the sacrificial material layer with an etch-back process.

As illustrated inFIG. 26, insulation patterns570may then be formed in respective ones of the second trenches522on the sacrificial layer582. The insulation patterns570may be formed of the same material layer, for example, a silicon oxide layer, as the spacers572illustrated inFIG. 25. In more detail, the insulation patterns570may be formed of an ultra low temperature oxide (ULTO) layer. The insulation patterns570may be formed in the second trenches522to conformally cover sidewalls of the capping insulation patterns560, sidewalls of the transistor active regions536, and a top surface of the sacrificial layer582.

After the insulation patterns570are formed, the sacrificial layer582under the insulation layer570may be removed to form the air gaps580illustrated inFIG. 5. In an embodiment in which the sacrificial layer582is formed of a carbon layer or a photoresist layer, the sacrificial layer582may be removed by an ashing process using an oxygen gas. Although not shown in the drawings, portions of the insulation patterns570may be etched to expose a portion of the sacrificial layer582before the sacrificial layer582is removed.

According to the embodiments set forth above, semiconductor devices including buried metal silicide patterns may be fabricated using simple processes even though the semiconductor devices are scaled down to increase the integration density thereof.

The above embodiments have been disclosed above for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concepts disclosed in the accompanying claims.