Fast clear memory of system memory

Various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment. One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer.

BACKGROUND

The present invention relates in general to computing systems, and more particularly, to various embodiments for compressing data in latency-critical processor links of a computing system in a computing environment using a computing processor.

SUMMARY

According to an embodiment of the present invention, a method for compressing data in latency-critical processor links of a computing system in a computing environment using a computing processor, is depicted. One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer.

An embodiment includes a computer usable program product. The computer usable program product includes a computer-readable storage device, and program instructions stored on the storage device.

An embodiment includes a computer system. The computer system includes a processor, a computer-readable memory, and a computer-readable storage device, and program instructions stored on the storage device for execution by the processor via the memory.

Thus, in addition to the foregoing exemplary method embodiments, other exemplary system and computer product embodiments are provided.

DETAILED DESCRIPTION OF THE DRAWINGS

In modern computer systems, a multi-processor system comprises multi-core central processing units (CPUs) in a single module. Typically, communication between the processors in the multi-processor system is via an inter-processor bus (also referred to as a processor link). The processors that are coupled via the processor link (i.e., a driver processor and a destination processor) are typically associated with I/O parameters that govern analog characteristics of a signal transmitted from the driver processor and the corresponding signal received at the destination processor. Characterizing the processor link during a testing/validation phase can help identify the best I/O parameters for reliably achieving desired performance levels.

Additionally, computer hardware caches are temporary holding storages for fast access to frequently used memory data. Said differently, to reduce or avoid the time delay (or “latency”) of accessing data stored in the main memory of a computer, modern computer processors include a cache memory (or “cache”) that stores recently accessed data so that it can be quickly accessed again by the processor. Data that is stored in a cache can be quickly accessed by a processor without the need to access the main memory (or “memory”), thereby increasing the performance of the processor and the computer overall. A cache has a shorter access time than the computer system memory (e.g., frequently referred to as dynamic random-access memory, “DRAM”). Caches are typically constructed with Static Random-Access Memory (“SRAM”), which are faster than DRAM. However, cache capacities are smaller than DRAM. The cache/memory access speed and capacity are inversely proportional.

Several different layers of cache may be provided in a computer system. Level 1 (or primary) cache, for example, is used to store data on behalf of system memory (which comprises random access memory, i.e., RAM) for access by a processor. Level 1 (“L1”) cache can be built directly into the processor and can run at the same speed as the processor, providing the fastest possible access time. Level 2 (or secondary) (“L2”) cache is also used to store a portion of system memory and may be included within a chip package but is separate from the processor. Level 2 cache has greater capacity than Level 1 cache but is slower. Some systems may even include Level 3 (“L3”) cache that has even greater capacity than Level 2 cache. However, Level 3 cache is typically slower than Level 2 cache, yet still faster than the primary storage device, and may be located off the chip package.

Data in a cache are stored in “lines,” which are contiguous chunks of data (i.e., being a power-of-2 number of bytes long, aligned on boundaries corresponding to this size). That is, data is typically transferred and accessed in groupings known as cache lines, which may include more than one item of data.

In typical computing architecture, a processor core may be connected to a cache (e.g., an on-chip cache or “nest”), which is in turn connected to the processor link (“link”). The nest and link are designed to operate at a much lower speed than the processor core. The nest may be a computing infrastructure that handles the transfer of data between the core and other cores, main memory, and input/output (“I/O”) devices. The nest is responsible for maintaining coherency of data lines across the system. It is not an industry-standard term, so maybe we should define it better before using it. There are many data links in a computing system—Processor to IO links (PCIe, ethernet), Processor to memory links and Processor to Processor links. The nest includes all the infrastructure that handles these links. Thus, a link may be a connection that facilitates data transfer to/from a processor. In other words, in a computer system configuration, which shares the caches across different processors that are connected together by inter-processor links, there may be coherent transfer of cache data lines among processors.

Typical computing systems have a handshake protocol for the cache line transfer and only a limited number of requests over the link can be outstanding. Requests for cache line transfers are fulfilled but limited by the link speed. Since not all processor core computations require nest or link interaction, this provides a computer system performance with reasonable power consumption. However, when the processor core requests a cache line over the processor link, the speed mismatch negatively impacts the performance of the computer system. For example, physical limitations restrict the link speed, which is a combination of the number of serial lanes per link and the speed of operation.

Thus, the present invention provides for improving and optimizing the effective bandwidth and latency of such a constrained processor link, while reducing computing processor overheads, to improve and provide increased computing efficiency.

In this way, the present invention provides for increased computing system performance via latency reductions of a single cache-line transfer via lossless compression.

Accordingly, various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment using a computing processor, is depicted. One or more cache lines may be dynamically compressed at the lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer. In some examples, data packets created for transfer over the link may be comprised of header information, cache line data, and some control information. The cache line data may be compressed while the other the other parts of the data pack (e.g., header, control flags) are not compressed. So, in effect, more of the cache line data can fit into a single data packet when compressed. That is, the cache lines may be dynamically compressed at the lowest level of the networking stack (framer/DLL) as opposed to application layer.

It should be noted, as used herein, a networking stack may be comprised of the following layers; 1) an application layer (the application layer may be the core and any software that runs), 2) a transport layer (the layer that handles the coherency of the data transfers—creates packets from the cache line data for transmission and processes the received packets to deliver to the application layer), 3) a data link layer (the layer that is responsible for guaranteeing error-free and in-order delivery of the data packets), and 4) a physical layer (the actual electrical circuit). Thus, a core may be the application layer, the nest may be the transport layer, and the link may be the link layer and the physical layer.

As such, the compression at the lower level is that it is purely a hardware (“HW”)-driven mechanism without any intervention from the core or the software application.

In one example, the framer can be defined as a component/module that frames the data to transfer it over the link by adding some additional information in a pre-defined organization to allow the data to be processed on the receiving side. The DLL may be the data link layer.

In some examples, various embodiments provide for compressing data in the data link layer with framer feedforward. In some examples, various embodiments provide for compressing data in a framer with bus feedback. In some examples, various embodiments provide for dynamic compression toggling based on cache line contention. For example, an attacker may try to create frequent transfer of cache lines between processors to get information about its compressibility. If a high volume of transfers is observed in a particular address space, i.e. there is high contention for some cache lines, then it is safer to disable compression to prevent any leakage of information.

In this way, various embodiments provide for pipelined compression at the data link layer and enables compression in a computing system without any performance penalty. That is, the present invention provides for low latency compression on the data links without compromising security via side channels, as compared to just compressing on the cache all the time. By enabling dynamic compression operations on the data links, any real-time impact (positive or negative) of compression on performance may be evaluated thus enabling a corrective action/choice to be made to adjust the compression and reduce latency.

In some examples, various embodiments provide for compressing data at the data link level by using control signals at the link layer. That is, data may be dynamically compressed by dynamically adapting to the data link layer conditions to increase compression efficiency equal to or greater than the data link speed without compression in terms of latency.

In some examples, various embodiments provide for implementing compression at the link level to reduce link latency while not increasing the complexity of the cache implementation and keeping the overall cache data access latency equal or better than a system without compression. The cache line is considered as the smallest entity to operate on and hence can be implemented on link data.

It should be noted that one or more calculations may be performed using various mathematical operations or functions that may involve one or more mathematical operations (e.g., solving differential equations or partial differential equations analytically or computationally, using addition, subtraction, division, multiplication, standard deviations, means, averages, percentages, statistical modeling using statistical distributions, by finding minimums, maximums or similar thresholds for combined variables, etc.).

In general, as used herein, “optimize” may refer to and/or defined as “maximize,” “minimize,” “best,” or attain one or more specific targets, objectives, goals, or intentions. Optimize may also refer to maximizing a benefit to a user (e.g., maximize a trained machine learning scheduling agent benefit). Optimize may also refer to making the most effective or functional use of a situation, opportunity, or resource.

Additionally, optimizing need not refer to a best solution or result but may refer to a solution or result that “is good enough” for a particular application, for example. In some implementations, an objective is to suggest a “best” combination of operations, schedules, compression/decompression operations, and/or framer/DLL manager options, but there may be a variety of factors that may result in alternate suggestion of a combination of operations, schedules, compression/decompression operations, and/or framer/DLL manager options yielding better results. Herein, the term “optimize” may refer to such results based on minima (or maxima, depending on what parameters are considered in the optimization problem). In an additional aspect, the terms “optimize” and/or “optimizing” may refer to an operation performed in order to achieve an improved result such as reduced execution costs or increased resource utilization, whether or not the optimum result is actually achieved. Similarly, the term “optimize” may refer to a component for performing such an improvement operation, and the term “optimized” may be used to describe the result of such an improvement operation.

Characteristics are as follows:

Service Models are as follows:

Deployment Models are as follows:

As previously stated, the present invention provides novel solutions for improving and optimizing the effective bandwidth and latency of such a constrained processor link, while reducing computing processor overheads, to improve and provide increased computing efficiency. Accordingly, various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment using a computing processor, is depicted. One or more cache lines may be dynamically compressed at the lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer. That is, the cache lines may be dynamically compressed at the lowest level of the networking stack (framer/DLL) as opposed to application layer.

In some examples, as described herein, the various embodiments are provided herein for dynamic compression of cache lines at the lowest level of the networking stack (framer/DLL) as opposed to application layer performed via pipelined compression. In some examples, data is feed from a framer to the DLL using that feed data to determine amount of compression to attempt. One or more queue levels in a framer may be monitored.

In some examples, as described herein, the various embodiments are provided herein for dynamic compression by dynamically toggling on or off the dynamic compression, which may be based on rate-matching. Various embodiments provide for compression operations designed with awareness of clocking differences between link and nest using the rate-matching. In some examples, as described herein, the various embodiments are provided herein for dynamic compression by preventing of timing side-channel attacks by dynamically controlling compression on hot cache lines (e.g., a cache line that is frequently transferred such as, for example transferred more than other cache lines, transferred above a predetermined threshold, transferred at or above a defined percentage, and/or an nth number of transfers in a defined period of time, etc., where n is a positive integer). That is, an attack that might make use of the time spent in performing a particular operation to gain additional information of the operation itself. Thus, if some amount of data is observed to be quickly transferred between processors, it indicates that the data has low entropy and the attacker can attempt to gain further information based on this low entropy.

Turning now toFIG.4, a block diagrams depicting exemplary functional components of a cache system400for use in compressing data in latency-critical processor links of a computing system in a computing environment according to various mechanisms of the illustrated embodiments is shown. In one aspect, one or more of the components, modules, services, applications, and/or functions described inFIGS.1-3may be used inFIG.4. As will be seen, many of the functional blocks may also be considered “modules” or “components” of functionality, in the same descriptive sense as has been previously described inFIGS.1-3.

The system400comprises of a memory410, a cache420(e.g., cache data array) and a cache directory430, all of which may be in communication with a processor450.

Data in the cache420are stored in “lines,” such as, for example, memory line422, which are contiguous chunks of data (i.e., being a power-of-2 number of bytes long, aligned on boundaries corresponding to this size). A cache line422of memory data, typically in units of 64 to 256-bytes long, is stored in a data array location and the respective memory address is stored in the directory, as shown inFIG.4. The processor450will supply the memory address to the cache such as, for example, the cache data array420. If the address is found in the cache directory430, the processor450may access a respective line of data in the cache420. If the address is not found in the cache directory430, the processor450may access the respective line of data in the memory410.

Turning now toFIG.5, a block diagram depicting exemplary functional components of system500for compressing data in latency-critical processor links of a computing system in a computing environment according to various mechanisms of the illustrated embodiments is shown. In one aspect, one or more of the components, modules, services, applications, and/or functions described inFIGS.1-4may be used inFIG.5. As will be seen, many of the functional blocks may also be considered “modules” or “components” of functionality, in the same descriptive sense as has been previously described inFIGS.1-4.

A data compression service510is shown, incorporating processing unit520(“processor”) to perform various computational, data processing and other functionality in accordance with various aspects of the present invention. In one aspect, the processor520and memory530may be internal and/or external to the interleaving service510, and internal and/or external to the computing system/server12. The interleaving service510may be included and/or external to the computer system/server12, as described inFIG.1. The processing unit520may be in communication with the memory530. The data compression service510may include a compression component540, a framer/data link layer (“DLL”) component550, a determination component560, and a decompression component570.

In one aspect, the system400may provide virtualized computing services (i.e., virtualized computing, virtualized storage, virtualized networking, etc.). More specifically, the system500may provide virtualized computing, virtualized storage, virtualized networking and other virtualized services that are executing on a hardware substrate.

The data compression service510may, using the compression component540, the framer/DLL component550, the determination component560, and the decompression component570may determine to compress one or more cache lines based on one or more of a plurality of parameters, where the plurality of parameters include a number of pending data packets, a quality of service (“QoS”), and a current packet type, where the current packet types are either a data packet or a control packet.

The data compression service510may, using the compression component540, the framer/DLL component550, the determination component560, and the decompression component570may dynamically compress one or more cache lines at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, wherein the networking stack includes a framer and a data link layer.

The data compression service510may, using the compression component540, the framer/DLL component550, the determination component560, and the decompression component570may enable compression of the one or more cache lines based on a data in a queue above a defined threshold, or disable compression of the one or more cache lines based on data in a queue below a defined threshold.

The data compression service510may, using the compression component540, the framer/DLL component550, the determination component560, and the decompression component570may feed data from the framer to the data link layer to determine an amount of data to compress based on the one or more of the plurality of parameters.

The data compression service510may, using the compression component540, the framer/DLL component550, the determination component560, and the decompression component570may dynamically toggle the compression of the one or more cache lines using a bloom filter on a set of previously transferred cache line addresses.

The data compression service510may, using the compression component540, the framer/DLL component550, the determination component560, and the decompression component570may dynamically compressing one or more cache lines to match a data input rate.

The data compression service510may, using the compression component540, the framer/DLL component550, the determination component560, and the decompression component570may dynamically controlling the compression of the one or more cache lines based on a number of hot cache lines.

For further explanation,FIG.6is a block diagram depicting operations for compressing data in latency-critical processor links of a computing system in a computing environment according to an embodiment of the present invention. In one aspect, one or more of the components, modules, services, applications, and/or functions described inFIGS.1-5may be used inFIG.6. As shown, various blocks of functionality are depicted with arrows designating the blocks' of system600relationships with each other and to show process flow (e.g., steps or operations). Additionally, descriptive information is also seen relating each of the functional blocks' of system600. As will be seen, many of the functional blocks may also be considered “modules” of functionality, in the same descriptive sense as has been previously described inFIGS.1-5. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

With the foregoing in mind, the module blocks' of systems600may also be incorporated into various hardware and software components of a computing system, may also be in a cloud computing environment in accordance with the present invention. Many of the functional blocks of systems600may execute as background processes on various components, either in distributed computing components, or elsewhere.

As depicted, in a first example of the system600, a framer610A, at the data link layer, is depicted for receiving data packets (e.g., receiving data from a processor core not shown for illustrative convenience). A queue612A may exist in the framer610A where the queue612A may be monitored. A determination operation may be executed in the queue612A to determine if the data (e.g., number of data packets in the queue612A) are below a threshold to disable compression. If yes, a decision is determined to disable compression and a compressor614A bypasses compression of data in the queue610A and transfers the data616A to a parser618A that receives the non-compressed data, for example,620A and622A. In one example, the threshold may be dynamically set as an average compressibility of previous packets multiplied/times the number of clocks taken to compress a single packet.

In a second example of the system600, a framer610B, at the data link layer, is depicted for receiving data packets (e.g., receiving data from a processor core not shown for illustrative convenience). A queue612B may exist in the framer610B where the queue612B may be monitored. A determination operation may be executed in the queue612B to determine if the data (e.g., number of data packets in the queue612B) are above a threshold to enable compression. If yes, a decision is executed to enable compression and the data may be sent to a compressor614B and a cache line may be dynamically compressed. The compressed cache lines616B may be transferred to a parser618B for decompressing one or more cache lines such as, for example,620B and622B.

In this way, the embodiments dynamically determine how much the next data should be compressed by (if at all), which allows scale a computing systems performance by transferring more data using the same link bandwidth, yet not compromising on the latency. While this change might add certain side-channels, one or more safeguards are provided against side-channels attacks.

FIG.7is an additional block diagram depicting operations for compressing data in latency-critical processor links of a computing system in a computing environment according to an embodiment of the present invention. In one aspect, one or more of the components, modules, services, applications, and/or functions described inFIGS.1-6may be used inFIG.7. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

A network stack700is depicted that includes a framer710, a compressor720, and a data link layer (e.g., a data link adaptor730(“DLA”) or also referred to as the DLL)), which may be associated with a processor core. It should be noted that “DLA” may be used interchangeable with “DLL.” The DLA730A may be in communication with an additional DLA such as, for example DLA730B, which is associated with a decompressor740and a parser750. In some implementations, the framer710and the DLA730A may be in communication with one or more compression (“CMP”) controls.

In operation, the framer710may receive incoming data (e.g., from a processor core). That is, the incoming packet may be 30 bytes and include a packet identifier (“ID”), which may indicate the packet type.

The framer710may indicates to the DLL (e.g., DLA730A) a variety of parameters for compressing or not compressing the data. In one example, the framer710indicates to the DLA730A at least three parameters; 1) a number of pending data packets (e.g., pending data), 2) a quality of service (“QoS”), and 3) a current packet type, where the current packet types are either a data packet or a control packet. In some examples, the stall signal from the link layer to the framer may be used to allow the DLL to control the flow rate of data. In one example, the link may not be ready to accept new packet due to certain error conditions in the link and the DLL will stall the framer. In some implementations, a modified version of the stall signal may be used to indicate the compression engine is busy processing the packets and no new packets should be driven in. As such, a modified stall signal is the original DLL stall along with any reasons the compression engine might have.

Based on these parameters, the compressor720may execute at least two stages: 1) a compression stage, or a non-compression stage. That is, in the non-compression stage, the compressor does not attempt compression on current packet types that are indicated as control packets. That is, cache lines indicated as control are not compressed. Rather, the compressor720passes the data (e.g., the cache line) through to the DLA730A, based on the assumption that control packets are difficult to compress.

Alternatively, in the compression stage, the compressor720attempts compression on data depending on amount of data pending (e.g., pending data in a queue in the framer710). For example, if there the amount of pending data is greater than a threshold, the compressor720will attempt to compress more cache lines. Alternatively, if the amount of pending data is less than a threshold, the compressor720will compress and zero-pad to packet size. For example, consider a situation where there are three packets P0, P1 and P2. Ideally, if all three packets can be compressed together, than only one packet is then transferred out. After compressing P0 and P1, it may be observed that P2 is unable to be compressed into the same packet and that it overflows. At this point, the compressed form of P0 and P1 (e.g., P0+P1) along with zeros added to reach the fixed packet size may be sent and transferred out. Then P2 may be sent out separately.

The compressor720also takes into account the quality of service (“QoS”) required for compression. The QoS is an indication of how much additional latency can be added to that particular data packet (e.g., cache line) without having a negative system impact. A higher latency indicates the compressor720will try to pack more data (e.g., pack more cache lines) into a packet, else the compressor720will compress, zero-pad to packet size and flush earlier.

For example, as described in the P0, P1, P2 scenario earlier, another option for the compression engine is to take P0, P1, and P2 together and attempt a increase compression rather than process them separately. Compressing the packets individually is ideal for latency because there is no need to buffer multiple packets. However, compressing the packets together increase efficiency and can result in more compression at the cost of latency. The QoS factor indicates if that data can afford to be delayed, even if only slightly in order to identify a more efficient compression format. If the latency is critical, a decision may be executed to just send out the packet without processing.

For example, as an example of operations ofFIG.7, a transferring core (e.g., Tx side) bus may free up faster than normal number of processor clock signals (“pclks”) earlier such as, for example, 28 pclks. Also, the operations ofFIG.7may complete cache line transfer (256 bytes) in an nth number of pclks earlier/faster (e.g., complete cache line transfer 24 pclks earlier). Also, the bandwidth on average increases such as, for example, bandwidth increases up by 20%. On average, each oct-word (“OW”) (32 bytes) reaches a number of pclks faster such as, for example, each OW reaches 10 pclk earlier. In one aspect, the first OW is 2 pclks delayed, while all others reach pclks early.

FIG.8is an additional block diagram depicting operations for compressing data in latency-critical processor links of a computing system with compression in framer with buss feedback (e.g., compression in a framer and decompression in a parser) in a computing environment according to an embodiment of the present invention. In one aspect, one or more of the components, modules, services, applications, and/or functions described inFIGS.1-7may be used inFIG.8. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

As depicted, a compressor in a framer810may receive an input flow of data with a tag (n+1) and data (n). The compressor may tag a buffer and 8-deep data buffer. Assuming nest clock is equal to the processor core clock divided by two for the input flow rate (e.g., nest clock=processor core clock/2 input flow rate), and the link clock is equal to processor core clock divided by three for the output flow rate (e.g., link clock=processor core clock/3 output flow rate). That is, the cache (e.g., nest) is working half the speed of a processor core and the link is working one-third the speed of a processor core.

It should be noted that the threshold calculation may be similar to the previous case and the maximum compression to be attempted (e.g., 2×, 4×, 8×) may be determined as the fill level divided by the output flow rate.

Thus, given a packet, which may be received at 37 bytes, only twenty (20) bytes may be flushed. That is, the DLL framer fill rate is equal to 37 bytes (“B”) per nest clock (37 B/nest clock). The DLL framer flush rate is equal to twenty bytes per nest clock (e.g., 20 B/nest clock).

A compressor of the framer (e.g., DLL compression) attempts to compress based on rate matching. That is, in some examples, the compressor of the framer810attempts the dynamic compression of the cache line by a compression rate (e.g., eight times ‘8×’) if fill level is equal to or greater than 180 bytes. In some examples, the compressor of the framer810attempts the dynamic compression of the cache line by a compression rate (e.g., four times ‘4×’) if fill level is equal to or greater than 100 bytes. In some examples, the compressor of the framer810attempts the dynamic compression of the cache line by a compression rate (e.g., two times ‘2×’) if fill level is equal to or greater than 60 bytes.

In some examples, the compressor of the framer810does not compress the data and allows the data to pass through. In this way, the various embodiments provided the dynamic compression with no increase in latency on transmission of the cache line.

The framer810may send the compressed or non-compressed data to the parser820and the decompressor of the parser820may decompress the data.

For further example, various embodiments provided the dynamic compression and transmission (“Tx”) frees up 9 pclks early per cache line. The receiving (“Rx”) completes cache line transfer 4 pclks early (and the nominal latency for 1 cache line assuming everything else is idle). Also, the transmission of zero to tow OWs experience no additional latency on parser820output. A third OW may only be delayed by 2 pclks. The transmission of OW 4-7 may arrive earlier by 1, 2, 3, 4 pclks, respectively. Thus, the averaged over an isolated cache line, each OW arrives 1 pclks early. The averaged over multiple transactions, each OW arrives at least 7 pclks early.

Additionally, due to compression of cache lines, an attacker can mount an attack, which constantly flushes and reloads sensitive lines. Based on time taken for flushing and reloading, the attacker can determine compressibility of the lines, which leaks entropy. To overcome this vulnerability, the present invention may implement a bloom filter over a set of previously transferred cache line addresses. If the same cache line is moving back-and-forth too many times (programmable limit), then compression may be turned off (e.g., dynamic compression is toggled off). The dynamic compression may be turned on again if a computing system does not have a hot cache line getting flushed/reloaded too many times. The compression can also be turned on (e.g., dynamic compression is toggled on) again after a defined period of time.

Turning now toFIG.9, a method900for compressing data in latency-critical processor links of a computing system in a computing environment using a processor is depicted, in which various aspects of the illustrated embodiments may be implemented. The functionality900may be implemented as a method (e.g., a computer-implemented method) executed as instructions on a machine, where the instructions are included on at least one computer readable medium or one non-transitory machine-readable storage medium. The functionality900may start in block902.

One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer, as in block904. The functionality900may end, as in block906.

In one aspect, in conjunction with and/or as part of at least one blocks ofFIG.9, the operations of method900may include each of the following. The operations of method900may enable compression of the one or more cache lines based on a data in a queue above a defined threshold; or disable compression of the one or more cache lines based on data in a queue below a defined threshold.

The operations of method900may determine to compress the one or more cache lines based on the one or more of the plurality of parameters, wherein the plurality of parameters include a number of pending data packets, a quality of service (“QoS”), and a current packet type, wherein the current packet types are either a data packet or a control packet.

The operations of method900may feed data from the framer to the data link layer to determine an amount of data to compress based on the one or more of the plurality of parameters. The operations of method900may dynamically toggle the compression of the one or more cache lines using a bloom filter on a set of previously transferred cache line addresses. The operations of method900may dynamically compress the one or more cache lines to match a data input rate. The operations of method900may dynamically control the compression of the one or more cache lines based on a number of hot cache lines.