Push-pull amplifier circuit and operational amplifier circuit using the same

A push-pull amplifier including first to third current paths. The first current path includes first transistor allowing first current to flow through the first current path according to input signal. The second current path includes second transistor allowing second current having opposite phase to the first current to flow through the second current path according to the first current; first resistor; and third transistor connected to one end of the first resistor and having control terminal connected to the other end of the first resistor. The third current path includes output terminal; fourth transistor allowing current having the same phase as the first current to flow through the third current path according to the input signal; and fifth transistor allowing current having the same phase as the second current to flow through the third current path according to voltage of first node between the first resistor and the third transistor.

INCORPORATION BY REFERENCE

This application is based upon and claims the benefit of priority from Japanese patent application No. 2009-198000, filed on Aug. 28, 2009, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

1. Field of the Invention

The present invention relates to a push-pull amplifier circuit and an operational amplifier circuit using the same.

2. Description of Related Art

FIG. 7shows a push-pull amplifier circuit1disclosed in Japanese Unexamined Patent Application Publication No. 2002-261550 as prior art. As shown inFIG. 7, the push-pull amplifier circuit1includes constant current sources I1to I3, NMOS transistors M1to M5and M8, a depletion-type NMOS transistor M6, PMOS transistors M7and M9, resistors R1to R3, a signal input terminal TIN, and a signal output terminal TOUT. The NMOS transistors M1to M5and M8and the PMOS transistors M7and M9are enhancement-type MOS transistors. Note that reference symbols “I1” to “I3” denote constant current sources as well as currents output from the constant current sources and current values thereof.

The operation of the push-pull amplifier circuit1will be described. First, consider a case that voltage Vin of the input signal supplied to the signal input terminal TIN (hereinafter, referred to as “input voltage”) decreases. When the input voltage Vin decreases, drain currents IM7and IM9of the PMOS transistors M7and M9increase. The NMOS transistors M5and M4constitute a current mirror. Thus, when the drain current IM7increases, a drain current IM4of the NMOS transistor M4also increases. When the drain current IM4increases, a gate-source voltage V1of the NMOS transistor M8decreases. As a result, the drain current of the NMOS transistor M8decreases. Accordingly, an output voltage Vout of the signal output terminal TOUT increases.

Next, consider a case that the input voltage Vin supplied to the signal input terminal TIN increases. When the input voltage Vin increases, the drain currents IM7and IM9of the PMOS transistors M7and M9decrease. When the drain current IM7decreases, the drain current IM4of the NMOS transistor M4also decreases. When the drain current IM4decreases, the gate-source voltage V1of the NMOS transistor M8increases. As a result, the drain current of the NMOS transistor M8increases. Accordingly, the output voltage Vout of the signal output terminal TOUT decreases.

In this way, the push-pull amplifier circuit1makes the drain currents of the PMOS transistor M9and the NMOS transistor M8vary according to the input voltage Vin. The PMOS transistor M9and the NMOS transistor M8constitute a current path for an output stage of the push-pull amplifier circuit1. Accordingly, the push-pull amplifier circuit1operates push-pull output function on output current Tout. Regard that a portion composed of the constant current sources I1to I3, the NMOS transistors M1to M3, and the resistors R1and R2is designed so that the appropriate gate-source voltage V1is applied to the NMOS transistor M8when the value of the output current Iout (source direction is defined as positive) flowed from the signal output terminal TOUT is zero. The value of the output current Iout flowed from the signal output terminal TOUT is zero means that the drain current values of IM8and IM9are equal (IM9=IM8).

Now, consider a case that the input voltage Vin is further decreased so as to further increase the output current Iout or further increase the output voltage Vout in the operation of the push-pull amplifier circuit1. When the input voltage Vin decreases, the drain current IM9increases and the drain current IM7also increases. As the drain current IM7increases, the drain current IM8decreases. Then, the voltage Vout increases. When the output voltage Vout is close to a power supply voltage VDD, the drain-source voltage of the PMOS transistor M9decreases. This makes the PMOS transistor M9operate in a linear region and contribute less to increase of the drain current IM9even if the input voltage Vin is greatly decreased. Therefore, further decrease in the input voltage Vin does not effect further increase in the output current Tout or the output voltage Vout. In such a case, the NMOS transistor M6and the resistor R3suppress the upper limit value of the drain current IM7of the PMOS transistor M7, thereby reducing power consumption of the push-pull amplifier circuit1. This effect is based on the operation principle of the push-pull amplifier circuit1as described below.

To explain the above-mentioned effect, assume a configuration of the push-pull amplifier circuit1in which the NMOS transistor M6and the resistor R3are omitted. First, since the NMOS transistor M5operates as a MOS diode, the drain voltage V2of the NMOS transistor M5would be approximately slightly higher than the threshold voltage, for example, about 1.0 V. Assuming that the power supply voltage VDD is 3.0 V, the drain-source voltage of the PMOS transistor M7is about 2.0 V. Such a voltage is generally sufficient for the PMOS transistor M7to operate in the saturated region. Accordingly, if the input voltage Vin is decreased, the drain current IM7further increases and this leads increase in wasteful current consumption while an increase in the output current Iout is not gained.

In the push-pull amplifier circuit1, the NMOS transistor M6is a depletion-type transistor which is self-biased by the drain current with the resistor R3the NMOS transistor M6is suppressed flowing drain current under normally-on where the gate-source voltage is zero or less. Therefore, the upper limit value of the drain current IM7is controlled and an increase in wasteful current consumption is prevented.

SUMMARY

The present inventor has found a problem as described below. In the push-pull amplifier circuit1, even when the value of the output current Tout is zero, the portion composed of the constant current sources I1to I3, the NMOS transistors M1to M3, and the resistors R1and R2is required merely to maintain the circuit in the normal operating state, i.e., in a so-called stand-by state. The above-mentioned configuration is not directly involved in the output operation of the circuit. Additionally, the currents I1, I2, and IM2that flow through the configuration are also required.

In recent years, a reduction in the number of elements constituting a circuit has been demanded. If the number of elements is reduced, the number of components that constitute a circuit and the chip area of an LSI can be reduced. This leads to a reduction in manufacturing costs. Further, a reduction in current consumption in the circuit has also been demanded.

Contrary to the demands for products, the push-pull amplifier circuit1has a problem that the size of the circuit portion that is not directly involved in the output operation as described above becomes large. The push-pull amplifier circuit1has another problem that current consumption becomes large.

A first exemplary aspect of the present invention is a push-pull amplifier circuit including first, second, and third current paths. The first current path includes a first transistor that allows a first current to flow through the first current path according to an input signal. The second current path includes: a second transistor that allows a second current to flow through the second current path according to the first current, the second current having a phase opposite to a phase of the first current; a first resistor; and a third transistor that is connected to one end of the first resistor and has a control terminal connected to the other end of the first resistor. The third current path includes: an output terminal; a fourth transistor that is connected to the output terminal and allows a current to flow through the third current path according to the input signal, the current having the same phase as the first current; and a fifth transistor that is connected to the output terminal and allows a current to flow through the third current path according to a voltage of a first node between the first resistor and the third transistor, the current having the same phase as the second current.

The push-pull amplifier circuit according to the first exemplary aspect of the present invention allows a current having the same phase as the first current flowing through the first current path to flow through the fourth transistor included in the third current path serving as an output stage. Further, the push-pull amplifier circuit allows a current having a phase opposite to that of the first current flowing through the second current path to flow through the fifth transistor included in the third current path. The second current path has a function of suppressing excessive current consumption caused due to the input signal. Consequently, the amplifier circuit according to an exemplary aspect of the present invention has a function of suppressing excessive current consumption, and can be formed using the minimum number of elements that constitute the current paths. Moreover, the number of current paths through which a current flows is reduced, which is advantageous in reducing current consumption.

According to an exemplary aspect of the present invention, a push-pull amplifier circuit capable of reducing the circuit size and current consumption can be provided.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

First Exemplary Embodiment

A first exemplary embodiment of the present invention will be described in detail below with reference to the drawings.FIG. 1shows a configuration of a push-pull amplifier circuit100according to the first exemplary embodiment. As shown inFIG. 1, the push-pull amplifier circuit100includes constant current sources I101and I102, PMOS transistors MP101to MP104, NMOS transistors MN101and MN102, a resistor R101, a signal input terminal TIN, and a signal output terminal TOUT. Note that reference symbols “I101” and “I102” denote constant current sources as well as currents output from the constant current sources and current values thereof. Reference symbols “VDD” and “GND” denote a power supply voltage terminal and a ground voltage terminal, respectively, and also denote a power supply voltage supplied from the power supply voltage terminal and a ground voltage supplied from the ground voltage terminal, respectively.

The PMOS transistor MP101has a source connected to the power supply voltage terminal VDD, a drain connected to a node N101, and a gate connected to the signal input terminal TIN. The PMOS transistor MP102has a source connected to the power supply voltage terminal VDD, a drain connected to the node N101, and a gate connected to the node N101.

The PMOS transistor MP103has a source connected to the power supply voltage terminal VDD, a drain connected to a node N102, and a gate connected to the node N101. The PMOS transistor MP104has a source connected to the power supply voltage terminal VDD, a drain connected to the signal output terminal TOUT, and a gate connected to the signal input terminal TIN.

The resistor R101has one end connected to the node N102, and the other end connected to a node N103. The NMOS transistor MN101has a drain connected to the node N103, a source connected to a node N104, and a gate connected to the node N102. The NMOS transistor MN102has a drain connected to the signal output terminal TOUT, a source connected to the ground voltage terminal GND, and a gate connected to the node N103.

The constant current source I101is connected between the node N101and the ground voltage terminal GND. The constant current source I102is connected between the node N104and the ground voltage terminal GND.

To facilitate understanding of the principle of the circuit, assume that the constant current sources I101and I102are ideal constant current sources. As described later, the constant current sources I101and I102may actually be composed of transistors which have gates supplied with a predetermined bias voltage and which are driven by constant currents, or may be composed of transistors which constitute a current mirror and which are driven by constant currents. Further, the signal input terminal TIN may directly receive an input signal from the outside, and a differential amplifier circuit may be connected at a pre-stage of the circuit. In this case, the output of the differential amplifier circuit may be connected to the signal input terminal TIN to thereby constitute an operational amplifier circuit (Op Amp) as a whole.

The operation of the push-pull amplifier circuit100will be qualitatively described. First, consider a case that a voltage Vin of an input signal supplied to the signal input terminal TIN (hereinafter, referred to as “input voltage”) decreases. When the input voltage Vin decreases, drain currents IMP101and IMP104of the PMOS transistors MP101and MP104increase.

The PMOS transistor MP102operates as a MOS diode. A drain current IMP102of the PMOS transistor MP102has a value obtained by subtracting the value of the drain current IMP101from the value of the constant current I101. Thus, when the drain current IMP101increases, the drain current IMP102decreases.

However, the PMOS transistor MP103and the constant current source I102are connected in series in the same current path. Thus, when the drain current IMP103tends to decrease, voltages at the nodes N102to N104, which are located between the PMOS transistor MP103and the constant current source I102, decrease. The voltages are decreased to a level at which an increase of the drain current IMP103due to an increase of the drain-source voltage of the PMOS transistor MP103is balanced by a decrease of the current I102due to a decrease of the drain-source voltage of the transistor operating as the constant current source I102.

As a result, voltages V102to V104at the respective nodes N102to N104decrease. Then, a drain current IMN102of the NMOS transistor MN102having a gate connected to the node N103decreases, and an output voltage Vout of the signal output terminal TOUT increases.

Next, consider a case that the input voltage Vin supplied to the signal input terminal TIN increases. When the input voltage Vin increases, the drain currents IMP101and IMP104of the PMOS transistors MP101and MP104decrease.

The drain current IMP102of the PMOS transistor MP102operating as the MOS diode has a value obtained by subtracting the value of the drain current IMP101from the value of the constant current I101. Accordingly, when the drain current IMP101decreases, the drain current IMP102increases.

The PMOS transistors MP102and MP103constitute a current mirror. Thus, when the drain current IMP102increases, also the drain current IMP103of the PMOS transistor MP103tends to increase.

However, the PMOS transistor MP103and the constant current source I102are connected in series in the same current path. Accordingly, when the drain current IMP103tends to increase, the voltages at the nodes N102to N104, which are located between the PMOS transistor MP103and the constant current source I102, increase. The voltages are increased to a level at which a decrease of the drain current IMP103due to a decrease of the drain-source voltage of the PMOS transistor MP103is balanced by an increase of the current I102due to an increase of the drain-source voltage of the transistor operating as the constant current source I102.

As a result, the voltages V102to V104of the respective nodes N102to N104increase. Then, the drain current IMN102of the NMOS transistor MN102having a gate connected to the node N103increases, and the output voltage Vout of the signal output terminal TOUT decreases. In this way, the push-pull amplifier circuit100operates push-pull output function on the drain currents of the PMOS transistor MP104and the NMOS transistor MN102which are provided at the output stage.

Next, the operation of the push-pull amplifier circuit100will be quantitatively described. In the push-pull amplifier circuit100, gate W/L ratios of MOS transistors that are required to operate relatively are defined by the expression (1). Assume that the W/L ratios of the PMOS transistors MP101to MP104are respectively represented by “(W/L)MP101” to “(W/L)MP104”. Also assume that the W/L ratios of the NMOS transistors MN101and MN102are respectively represented by “(W/L)MN101” and “(W/L)MN102”.

Hereinafter, to simplify the explanation, assume that a short channel effect, a substrate bias effect, and an early voltage effect in the PMOS transistors MP101to MP104and the NMOS transistors MN101and MN102are disregarded and the relative error of each element in the circuit is zero. Furthermore, assume that the transistors constituting the constant current sources I101and I102, the PMOS transistors MP101to MP104, and the NMOS transistors MN101and MN102operate in a saturated region. It is generally easy to design a circuit such that every transistor operates in the saturated region, unless the power supply voltage is extremely low. Therefore, the circuit design can be made without loss of generality. Let a threshold voltage of the NMOS transistors MN101and MN102be Vthn, and a mutual conductance coefficient be βn (βn=μn·Coxn, where μn represents an electron mobility and Coxn represents a gate capacitance per area).

Under the above-mentioned conditions, drain currents IMN101and IMN102can be expressed as the following expressions (2) and (3), respectively.

From the expressions (2) and (3), IMN102/IMN101can be expressed as the following expression (4).

Here, if the relationship between the voltages V102and V103satisfies the following expression (5), IMN102/IMN101can be expressed as the following expression (6).
V102−V104=V103  (5)

In order to satisfy the condition of the expression (5), the following expression (7) should be satisfied.
V104=V102−V103=R101×I102  (7)
Further, from the expression (1), the drain currents IMP104and IMN102are given by the expressions (8) and (9), respectively.
IMP104=p×IMP101  (8)
IMP103=q×(I101−IMP101)  (9)

Next, assume that the drain current IMP101of the PMOS transistor MP101is “I0” when an output current Iout from the signal output terminal TOUT is zero, i.e., when the circuit is in a stand-by state. In this case, from the expressions (6) and (9), the drain current IMN102can be expressed as the following expression (10).
IMN102=r×IMN101=r×IMP103=r×q×(I101−IMP101)  (10)

If IMP101=I0, it is obvious that IMN102=IMP104. Thus, the expression (11) is derived from the expressions (8) and (10), and the expression (12) is further obtained.
IMN102=r×q×(I101−I0)=p×I0=IMP104  (11)

When the expression (12) is substituted into the expression (9), the expression (13) is obtained.

As is apparent from the above, the expression (7) is a condition that defines the voltage V104and the resistance value of the resistor R101, the expression (12) is a condition that defines the value of a current output from the constant current source I101, and the expression (13) is a condition that defines the value of a current output from the constant current source I102, during the circuit design. Note that the value of the voltage V104, the resistance value of the resistor R101, and the current value of the constant current source I102are appropriately determined so as to satisfy the expression (7). In order to stabilize the drain current IMN102of the NMOS transistor MN102and to multiply the drain current IMN101of the NMOS transistor MN101by r, it is necessary to satisfy the expression (7), i.e., to set the voltage drop of the resistor R101to be substantially equal to the voltage difference between both ends of the constant current source I102.

Also in the case of the push-pull amplifier circuit100, as with the push-pull amplifier circuit1, consider a case that the input voltage Vin is greatly decreased so as to further increase the output current Iout or further increase the output voltage Vout. When the input voltage Vin decreases, the drain current IMP104increases and the drain current IMP101also increases. However, the constant current source I101is connected to the current path from the PMOS transistor MP101to the ground voltage terminal GND. For this reason, the value of the drain current IMP101cannot be equal to or greater than the value of the current I101output from the constant current source I101. Then, the upper limit value of the drain current IMP101is suppressed to prevent an increase in wasteful current consumption. Such a circuit configuration allows lower power consumption of the push-pull amplifier circuit100according to the first exemplary embodiment.

In the push-pull amplifier circuit1according to the prior art, the upper limit value of the drain current IM7is suppressed by the NMOS transistor M6and the resistor R3, to thereby prevent an increase in wasteful current consumption. The NMOS transistor M6and the resistor R3are components that are not directly involved in the output operation of the circuit. The components cause an undesirable increase in the size of the push-pull amplifier circuit1.

Further, in the push-pull amplifier circuit1, even when the value of the output current Iout is zero, the components including the constant current sources I1to I3, the NMOS transistors M1to M3, and the resistors R1and R2are required merely to maintain the push-pull amplifier circuit1in the normal operating state, i.e., in a state called a stand-by state. The above-mentioned components are not directly involved in the output operation of the circuit, resulting in an undesirable increase in the size of the push-pull amplifier circuit1. Furthermore, among the currents flowing through the components including the constant current sources I1to13, the NMOS transistors M1to M3, and the resistors R1and R2, the currents I1, I2, and IM2which flow through the portion that is not directly involved in the output operation of the circuit are also required. This results in an undesirable increase in power consumption.

Similar to the push-pull amplifier circuit1, the push-pull amplifier circuit100according to the first exemplary embodiment has a function of preventing an increase in wasteful current consumption by limiting the upper limit value of the drain current IMP101corresponding to, for example, the drain current IM7in the push-pull amplifier circuit1of the prior art. On the other hand, the push-pull amplifier circuit100need not include any element dedicated to the operation for preventing an increase in wasteful current consumption. Therefore, the number of elements corresponding to the NMOS transistors M6and the resistor R3of the push-pull amplifier circuit1of the prior art can be reduced.

Further, in the push-pull amplifier circuit100of the first exemplary embodiment, only the constant current sources I101and I102, the NMOS transistor MN101, and the resistor R101are required merely to maintain the circuit in the normal state, i.e., in the stand-by state when the value of the output current Iout is zero. Thus, compared to the push-pull amplifier circuit1of the prior art, the push-pull amplifier circuit100can reduce the number of elements that constitute the circuit. Furthermore, among the currents flowing through the portion composed of the constant current sources I101and I102, the NMOS transistor MN101, and the resistor R101, only the currents IMP102and1102flow through the portion that is not directly involved in the output operation of the circuit. This results in a further reduction in current consumption, compared to the push-pull amplifier circuit1of the prior art.

As described above, the push-pull amplifier circuit100of the first exemplary embodiment requires no particular design value for the elements to implement the circuit. Therefore, such necessity is not presented or hidden as each element will actually be increased in size and the whole circuit size will also be increased compared to the push-pull amplifier circuit1, even though the number of elements is small.

Furthermore, in contrast to the push-pull amplifier circuit1, only the drain current IM102and the current I102of the constant current source I102flow through the portion that is not directly involved in the output operation of the circuit. Thus, the amount of currents flowing through the portion is reduced compared to the push-pull amplifier circuit1, thereby achieving low power consumption. Such necessity is not presented or hidden as the values of the currents will actually be increased compared to the push-pull amplifier circuit1, even though the number of current paths for determining current consumption is small. As described above, the push-pull amplifier circuit100of the first exemplary embodiment can solve the problem that the size of the push-pull circuit1of the prior art becomes large and current consumption also becomes large.

Second Exemplary Embodiment

A second exemplary embodiment of the present invention will be described in detail below with reference to the drawings.FIG. 2shows a configuration of a push-pull amplifier circuit200according to the second exemplary embodiment. As shown inFIG. 2, the push-pull amplifier circuit200includes a differential amplifier circuit210and the push-pull amplifier circuit100. Reference symbols inFIG. 2that are identical to those inFIG. 1denote identical or similar components.

As seen fromFIG. 2, the push-pull amplifier circuit200has a configuration in which the differential amplifier circuit210is connected as a pre-stage circuit of the push-pull amplifier circuit100. Thus, the second exemplary embodiment differs from the first exemplary embodiment in that the differential amplifier circuit210is added as the pre-stage circuit. Therefore, in the second exemplary embodiment, only the difference is mainly described and description of the other identical components is omitted.

The differential amplifier circuit210includes PMOS transistors MP211and MP212, NMOS transistors MN211and MN212, a constant current source I211, a non-inverting input terminal TIP, an inverting input terminal TIM, and an output terminal TOUTD.

The PMOS transistor MP211has a source connected to the power supply voltage terminal VDD, and a drain and a gate both connected to a node N201. The PMOS transistor MP212has a source connected to the power supply voltage terminal VDD, a drain connected to the output terminal TOUTD, and a gate connected to the node N201.

The NMOS transistor MN211has a drain connected to the node N201, a source connected to a node N202, and a gate connected to the inverting input terminal TIM. The NMOS transistor MN212has a drain connected to the output terminal TOUTD, a source connected to the node N202, and a gate connected to the non-inverting input terminal TIP. The output terminal TOUTD of the differential amplifier circuit210is connected to the signal input terminal TIN of the push-pull amplifier circuit100.

The differential amplifier circuit210is similar to an ordinary differential-input and single-output type differential amplifier circuit, so the description of the operation and the like thereof is omitted. Since the operation of the push-pull amplifier circuit100has been described in the first exemplary embodiment, a duplicate description thereof is omitted.

As described above, the push-pull amplifier circuit200has a configuration in which the differential amplifier circuit210is connected as the pre-stage circuit of the push-pull amplifier circuit100. The push-pull amplifier circuit200having such a configuration can be constituted as an operational amplifier circuit (Op Amp) as a whole. The operational amplifier circuit (Op Amp) is suitable for use as a push-pull amplifier circuit. This is because the operational amplifier produces negative feedback in the whole application circuit to which the operational amplifier is applied, thereby improving the operation accuracy.

Third Exemplary Embodiment

A third exemplary embodiment of the present invention will be described in detail below with reference to the drawings.FIG. 3shows a configuration of a push-pull amplifier circuit300according to the third exemplary embodiment. As shown inFIG. 3, the push-pull amplifier circuit300includes the constant current sources I101and I102, the PMOS transistors MP101to MP104, the NMOS transistors MN101and MN102, the resistor R101, capacitor elements C301to C303, the signal input terminal TIN, and the signal output terminal TOUT. Note that reference symbols inFIG. 3that are identical to those inFIG. 1denote identical or similar components. The third exemplary embodiment differs from the first exemplary embodiment in that the capacitor elements C301to C303are added. Therefore, in the third exemplary embodiment, only the difference is mainly described and the description of the other identical components is omitted.

The capacitor element C301has one end connected to the node N102, and the other end connected to the node N103. The capacitor element C302has one end connected to the node N103, and the other end connected to the signal output terminal TOUT. The capacitor element C303has one end connected to the signal input terminal TIN, and the other end connected to the signal output terminal TOUT.

The operation of the push-pull amplifier circuit300is similar to that of the push-pull amplifier circuit100of the first exemplary embodiment, so the description thereof is omitted. The capacitor elements C301to C303of the push-pull amplifier circuit300function as capacitor elements that compensate for a signal phase. An advantageous effect of the push-pull amplifier circuit300is described below.

As described in the second exemplary embodiment, an amplifier circuit is used as an operational amplifier circuit (Op Amp) in many cases. An operational amplifier circuit having a negative feedback configuration is suitable for use as an application circuit. When the operational amplifier circuit is configured in this manner, the differential amplifier circuit210described in the second exemplary embodiment is connected as a pre-stage of the push-pull amplifier circuit300.

Further, as shown inFIG. 4, the output terminal TOUTD of the differential amplifier circuit210is connected to the signal input terminal TIN of the push-pull amplifier circuit300. Since the configuration of the differential amplifier circuit210has been described in the second exemplary embodiment, a duplicate description thereof is omitted.

The operational amplifier circuit having a configuration in which the differential amplifier circuit210is added as described above is used as a push-pull amplifier circuit400. The push-pull amplifier circuit400includes three or more stages of signal paths in total from the gate to the drain of a transistor. If the multiple stages of circuit paths are formed in a negative feedback configuration, a problem arises due to a delay in phase of a signal which is negatively fed back. For example, there arises a problem that the circuit may oscillate when put into a positive feedback state due to the delay in phase of the signal which is negatively fed back. As a countermeasure against this problem, a method of adding a phase compensation circuit using a capacitor element as an output stage portion is generally employed. In the third exemplary embodiment, the push-pull amplifier circuit300including the capacitor elements C301to C303is used to constitute the push-pull amplifier circuit400serving as an operational amplifier circuit. When the push-pull amplifier circuit400has a negative feedback configuration, the occurrence of oscillation can be prevented by the effect of the capacitor elements C301to C303for phase compensation.

In particular, the capacitor element C301has a circuit configuration which is not generally employed. In the push-pull amplifier circuit300, an output current value of the constant current source I102is set to about 100 nA, for example, in order to reduce current consumption in the circuit. In this case, a typical enhancement-type MOS transistor requires about 200 mV, for example, as the voltage of V104. Accordingly, a large value, such as 200 mV/100 nA=2 MΩ, is required as the resistance value of the resistor R101. When the resistance value of the resistor R101is large, parasitic capacitances between electrodes of the PMOS transistor MP103and the NMOS transistor MN101, which are connected with the resistor R101, are combined with the resistance value, resulting in a large time constant. This causes a large phase delay. However, when the capacitor element C301of the push-pull amplifier circuit300serving as a phase compensating capacitor is connected in parallel with the resistor R101, an advantageous effect of more effectively preventing the oscillation of the circuit can be obtained.

Fourth Exemplary Embodiment

A fourth exemplary embodiment of the present invention will be described in detail below with reference to the drawings.FIG. 5shows a configuration of a push-pull amplifier circuit500according to the fourth exemplary embodiment. As shown inFIG. 5, the push-pull amplifier circuit500includes the PMOS transistors MP101to MP104, the NMOS transistors MN101and MN102, NMOS transistors MN501to MN505, the resistor R101, resistors R501and R502, the signal input terminal TIN, and the signal output terminal TOUT. Note that reference symbols inFIG. 5that are identical to those inFIG. 1denote identical or similar components. The fourth exemplary embodiment differs from the first exemplary embodiment in that a portion corresponding to the constant current sources I101and I102is replaced by a portion composed of the NMOS transistors MN501to MN505and the resistors R501and R502. Therefore, in the fourth exemplary embodiment, only the difference is mainly described and the description of the other identical components is omitted.

The resistor R501has one end connected to the power supply voltage terminal VDD, and the other end connected to a node N501. The resistor R502has one end connected to the node N501, and the other end connected to a node N502. The NMOS transistor MN501has a drain connected to the node N502, a source connected to a node N503, and a gate connected to the node N501. The NMOS transistor MN502has a drain connected to the node M503, a source connected to the ground voltage terminal GND, and a gate connected to the node N502.

The NMOS transistor MN503has a drain connected to the node N101, a source connected to a node N504, and a gate connected to the node N501. The NMOS transistor MN504has a drain connected to the node N504, a source connected to the ground voltage terminal GND, and a gate connected to the node N502.

The NMOS transistor MN505has a drain connected to the node N104, a source connected to the ground voltage terminal GND, and a gate connected to the node N502. The voltages of the nodes N501to N504are respectively represented by V501to V504. The drain currents of the NMOS transistors MN502, MN504, and MN505are respectively represented by IMN502, IMN504, and IMN505.

Thus, in the fourth exemplary embodiment, the constant current sources I101and I102of the first exemplary embodiment are implemented by the NMOS transistors MN501to MN505and the resistors R501and R502. The NMOS transistors MN501and MN502and the resistors R501and R502may constitute a bias voltage generation circuit that generates a bias voltage supplied to the NMOS transistors MN503to MN505.

Now, a method of obtaining the current value I102in the expression (7) which is a condition for the circuit design as described in the first exemplary embodiment will be described using the NMOS transistors MN501to MN505and the resistors R501and R502which are added in the fourth exemplary embodiment. To simplify the explanation, assume that a short channel effect and a substrate bias effect in the NMOS transistors MN501, MN502, and MN505are disregarded and the relative error of each element in the circuit is zero. Further, assume that every transistor operates in the saturated region. Furthermore, assume that the NMOS transistors MN501and MN502have the same gate W/L ratio.

When the NMOS transistors MN501and MN502have the same gate W/L ratio, both the transistors have the same gate-source voltage. Thus, the following expressions (14) and (15) are satisfied.
V501−V503=V502  (14)
V501−V502=R502×IMN502=V503  (15)

Assuming that an early voltage is VAn, the drain currents IMN502and IMN505are given as the following expressions (16) and (17). Assume that the gate W/L ratios of the NMOS transistors MN501and MN502are respectively represented by “(W/L)MN502” and “(W/L)MN505”.

Here, assuming that the NMOS transistors MN502and MN505have the same drain-source voltage, the following expressions (18) and (19) are derived from the expressions (7), (16), and (17).

As is apparent from the above, the relationship between the W/L ratios of the NMOS transistors MN501and MN505and the resistors R502and R101as shown in the expression (19) is a condition for specifically designing the constant current source I102of the first exemplary embodiment.

As described above, in the push-pull amplifier circuit500of the fourth exemplary embodiment, the constant current sources I101and I102of the first exemplary embodiment can be implemented by the NMOS transistors MN501to MN505and the resistors R501and R502. Further, as with the second exemplary embodiment, the differential amplifier circuit210may be connected as the pre-stage circuit of the push-pull amplifier circuit500to constitute an operational amplifier circuit (Op Amp). In this case, the configuration of the constant current source I211of the differential amplifier circuit210can be implemented using a configuration similar to that of the constant current sources I101and I102.

Fifth Exemplary Embodiment

A fifth exemplary embodiment of the present invention will be described in detail below with reference to the drawings.FIG. 6shows a configuration of a push-pull amplifier circuit600according to the fifth exemplary embodiment. As shown inFIG. 6, the push-pull amplifier circuit600includes the constant current source I102, a constant current source I601, the PMOS transistors MP101and MP104, the NMOS transistors MN101and MN102, NMOS transistors MN601and MN602, the resistor R101, the signal input terminal TIN, and the signal output terminal TOUT. Note that reference symbols inFIG. 6that are identical to those inFIG. 1denote identical or similar components. The fifth exemplary embodiment differs from the first exemplary embodiment in that the constant current source I101and the PMOS transistors MP102and MP103are omitted and the constant current source I601and the NMOS transistors MN601and MN602are added. Therefore, in the fifth exemplary embodiment, only the difference is mainly described and the description of the other identical components is omitted.

The NMOS transistor MN601has a drain and a gate both connected to the node N101, and a source connected to the ground voltage terminal GND. The NMOS transistor MN602has a drain connected to the node N104, a source connected to the ground voltage terminal GND, and a gate connected to the node N101.

The constant current source I601is connected between the power supply voltage terminal VDD and the node N102. Reference symbol “I601” denotes a current output from the constant current source I601to the node N102as well as the current value thereof. The drain currents of the NMOS transistors MN601and MN602are respectively represented by IMN601and IMN602.

The operation of the push-pull amplifier circuit600will be qualitatively described. First, consider a case that the input voltage Vin supplied to the signal input terminal TIN decreases. When the input voltage Vin decreases, the drain currents IMP101and IMP104of the PMOS transistors MP101and MP104increase. The NMOS transistors MN601and MN602constitute a current mirror. Thus, when the drain current IMN101increases, the drain current IMN602of the NMOS transistor MN602tends to increase.

However, the NMOS transistor MN602is connected in parallel with the constant current source I102, and this parallel configuration is connected in series with the constant current source I601in the same current path. Thus, when the drain current IMN602tends to increase, the voltages at the nodes N102to N104, which are located between the constant current source I601and the parallel configuration, decrease. Meanwhile, when the voltage V104of the node N104decreases, the drain-source voltage of the NMOS transistor MN602decreases and the drain current IMN602tends to decrease. Accordingly, the voltages at the nodes N102to N104decrease to a level at which the increase and decrease of the drain current IMN602are balanced.

As a result, the voltages V102to V104at the nodes N102to N104decrease. Then, the drain current IMN102of the NMOS transistor MN102having a gate connected to the node N103decreases, and the output voltage Vout of the signal output terminal TOUT increases.

Next, consider a case that the input voltage Vin supplied to the signal input terminal TIN increases. When the input voltage Vin increases, the drain currents IMP101and IMP104of the PMOS transistors MP101and MP104decrease. Because the NMOS transistors MN601and MN602constitute a current mirror, when the drain current IMN101decreases, also the drain current IMN602of the NMOS transistor MN602tends to decrease.

However, the NMOS transistor MN602is connected in parallel with the constant current source I102, and this parallel configuration is connected in series with the constant current source I601in the same current path. Thus, when the drain current IMN602tends to decrease, the voltages at the nodes N102to N104, which are located between the constant current source I601and the parallel configuration, increase. Meanwhile, when the voltage V104of the node N104increases, the drain-source voltage of the NMOS transistor MN602increases and the drain current IMN602tends to increase. Accordingly, the voltages at the nodes N102to N104increase to a level at which the increase and decrease of the drain current IMN602are balanced. In this way, the push-pull amplifier circuit600operates push-pull output function on the PMOS transistor MP104and the NMOS transistor MN102which are provided at the output stage.

Further, the operation of the push-pull amplifier circuit600will be quantitatively described. In the push-pull amplifier circuit600, (W/L)MP102and (W/L)MP103shown in the expression (1) are replaced by (W/L)MN601and (W/L)MN602, respectively. Note that (W/L)MN601and (W/L)MN602represent gate W/L ratios of the NMOS transistors MN601and MN602, respectively. Thus, the following expression (20) is satisfied in place of the expression (7).
V104=V102−V103=R101×(IMN602+I102)  (20)

Furthermore, the following expression (21) is satisfied in place of the expression (9).
I601=q×IMP101+I102  (21)

From the expressions (6) and (21), the drain current IMN102can be expressed as the following expression (22).
IMN102=r×IMN101=r×I601=r×(q×IMP101+I102)  (22)

Assume that the drain current IMP101of the PMOS transistor MP101is “I0” when the output current Iout from the signal output terminal TOUT is zero, i.e., when the circuit is in the stand-by state. If IMP101=I0, it is obvious that IMN102=IMP104. Thus, the expression (23) is obtained, and the expression (24) is further obtained.
IMN102=r×(q×I0+I102)=p×I0=IMP104  (23)

When the expression (24) is substituted into the expression (21), the following expression (25) is obtained.

In view of the foregoing, the expressions (20), (24), and (25) are conditions that define the voltage V104, the resistance value of the resistor R101, and the current values output from the constant current sources I102and I601, during the circuit design. As seen from the expression (24), if p/r=q, I102=0. This eliminates the need for the constant current source I102, and thus the constant current source I102can be omitted from the push-pull amplifier circuit600. Consequently, the push-pull amplifier circuit can be formed with a small number of circuit elements.

Further, as with the push-pull amplifier circuit200of the second exemplary embodiment, the push-pull amplifier circuit600may have a configuration in which the differential amplifier circuit210is connected as the pre-stage circuit. When the differential amplifier circuit210is connected as the pre-stage circuit, an operational amplifier circuit (Op Amp) can be constituted.

Furthermore, as with the push-pull amplifier circuit300of the third exemplary embodiment, the push-pull amplifier circuit600may include a capacitor element for phase compensation. This configuration prevents the occurrence of oscillation due to a phase delay, as with the push-pull amplifier circuit400, even if an operational amplifier circuit (Op Amp) is formed to apply negative feedback.

Moreover, as with the push-pull amplifier circuit500of the fourth exemplary embodiment, the constant current source I102of the push-pull amplifier circuit600may be composed of a transistor, a resistor, and the like. In this case, the current mirror composed of the MNOS transistors MN601and MN602of the push-pull amplifier circuit600may also be implemented with the NMOS transistors MN501, MN502, and MN504and the resistor R501. Also in this case, the condition for the circuit design as shown in the expression (19) is applicable.

Note that the present invention is not limited to the above exemplary embodiments and can be modified in various manners without departing from the scope of the present invention. Circuits that operate in the same manner as in the exemplary embodiments can be obtained also in the following case. That is, in the circuits according to the exemplary embodiments, all of the NMOS transistors may be replaced by PMOS transistors and all of the PMOS transistors may be replaced by NMOS transistors. Further, the direction of the current from the constant current source may be inverted. Furthermore, the power supply voltage VDD may be replaced by the ground voltage GND and the ground voltage GND may be replaced by the power supply voltage VDD.

Alternatively, the MOS transistors provided in the circuits according to the exemplary embodiments may be replaced by bipolar transistors.

While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above.

The first to fifth exemplary embodiments can be combined as desirable by one of ordinary skill in the art.