SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

Please replace the currently pending Abstract with the following amended A parasitic capacitance of a wiring arranged on a back surface side of a semiconductor substrate is reduced. A semiconductor apparatus includes a semiconductor substrate, a back surface side wiring, a through wiring, and a separation region. In the semiconductor substrate, a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side. The back surface side wiring is arranged on a back surface side of the semiconductor substrate. The through wiring is arranged in a through hole formed in the semiconductor substrate to connect the front surface side wiring and the back surface side wiring. The separation region is arranged between the semiconductor substrate and the back surface side wiring.

TECHNICAL FIELD

The present disclosure relates to a semiconductor apparatus and a method for manufacturing the semiconductor apparatus. Specifically, the present disclosure relates to a semiconductor apparatus including a wiring penetrating a semiconductor substrate, and a method for manufacturing the semiconductor apparatus.

BACKGROUND ART

A conventional semiconductor apparatus configured in a semiconductor package reduced to the size of a semiconductor chip such as a chip size package (CSP) has been used. For example, a solid-state imaging apparatus has been used in which an imaging element is formed on a first main surface (front surface) of a silicon semiconductor substrate, and a solder ball constituting an external terminal is arranged on a second main surface (back surface) (see, for example, Patent Document 1). In this solid-state imaging apparatus, a through hole formed to penetrate from the first main surface to the second main surface of the silicon semiconductor substrate is arranged. A through electrode is arranged in the through hole, and an internal electrode connected to the imaging element on the first main surface and the solder ball are electrically connected via the through electrode.

CITATION LIST

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

In the above-described conventional technology, there is a problem that the parasitic capacitance of the through electrode is large. The above-described conventional through electrode is arranged on the through hole and the second main surface via an insulating film. A parasitic capacitance with the silicon semiconductor substrate adjacent via the insulating film causes a signal propagation delay. In particular, a through electrode arranged on the second main surface, that is, a wiring portion called rewiring extending from an end of the through hole to the solder ball has a relatively large area, and thus parasitic capacitance increases. For this reason, there is a problem that the propagation delay of the signal increases and the transmission speed of the signal decreases. Such a problem may occur due to parasitic capacitance between the semiconductor substrate and the rewiring even in a configuration in which the through electrode is not formed on the semiconductor substrate.

The present disclosure has been made in view of the above-described problems, and an object of the present disclosure is to provide a semiconductor apparatus and a method for manufacturing the semiconductor apparatus capable of reducing parasitic capacitance of a wiring arranged on a back surface side of a semiconductor substrate and improving signal transmission characteristics.

Solutions to Problems

The present disclosure has been made to solve the above-described problems, and a first aspect thereof is a semiconductor apparatus including: a semiconductor substrate in which a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side; a back surface side wiring arranged on a back surface side of the semiconductor substrate; and a separation region arranged between the semiconductor substrate and the back surface side wiring.

Furthermore, in the first aspect, the semiconductor apparatus may include a through wiring arranged in a through hole formed in the semiconductor substrate and connecting the front surface side wiring and the back surface side wiring.

Furthermore, in the first aspect, the separation region may include a resin.

Furthermore, in the first aspect, the separation region may include a photosensitive resin.

Furthermore, in the first aspect, the separation region may include an inorganic material.

Furthermore, in the first aspect, the separation region may be formed to have a thickness of equal to or greater than 5 μm.

Furthermore, in the first aspect, the separation region may be arranged in a recess portion formed on the back surface side of the semiconductor substrate.

Furthermore, in the first aspect, the separation region may have a gap.

Furthermore, in the first aspect, the back surface side wiring may be provided so as to at least partially overlap the recess portion in plan view.

Furthermore, in the first aspect, a plurality of types of recess portions having different depths may be formed as the recess portion.

Furthermore, in the first aspect, the recess portion may be formed so as to overlap a plurality of the back surface side wiring in plan view.

Furthermore, in the first aspect, the recess portion may be formed to form a polygonal or circular periodic structure in plan view.

Furthermore, in the first aspect, the semiconductor apparatus may include: a through wiring arranged in a through hole formed in the semiconductor substrate and connecting the front surface side wiring and the back surface side wiring; and a liner film including an insulating material, covering at least a part of the through wiring, and interposed between the through wiring and the separation region.

Furthermore, in the first aspect, the semiconductor apparatus may further include a through wiring arranged in a through hole formed in the semiconductor substrate and connecting the front surface side wiring and the back surface side wiring, the separation region may include an in-hole separation region portion covering an inner circumferential surface of the through hole and a back surface side separation region portion formed on a back surface side of the semiconductor substrate, and the gap may be formed in the back surface side separation region portion.

Furthermore, in the first aspect, the separation region may be further arranged between the semiconductor substrate and the through wiring.

Furthermore, in the first aspect, the separation region may be used as a mask in etching for forming the through hole in the semiconductor substrate.

Furthermore, in the first aspect, the semiconductor substrate may further include an insulating film that insulates the back surface side wiring.

Furthermore, in the first aspect, the semiconductor element may be a photoelectric conversion element that performs photoelectric conversion of incident light.

Furthermore, a second aspect of the present disclosure is a method for manufacturing a semiconductor apparatus, the method including: a separation region arrangement step of arranging a separation region on a back surface side of a semiconductor substrate on which a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side; a through hole forming step of forming a through hole in the semiconductor substrate; a back surface side wiring arrangement step of arranging a back surface side wiring on the back surface side of the semiconductor substrate; and a through wiring arrangement step of arranging a through wiring connecting the front surface side wiring and the back surface side wiring in the through hole that has been formed.

According to an aspect of the present disclosure, there is an effect that the separation region is arranged between the semiconductor substrate and the back surface side wiring. It is assumed that the back surface side wiring is spaced from the semiconductor substrate.

MODE FOR CARRYING OUT THE INVENTION

Next, an embodiment for implementing the present disclosure (hereinafter, referred to as an embodiment) will be described with reference to the drawings. In the drawings, the same or similar parts are denoted by the same or similar reference numerals. Furthermore, the embodiments will be described in the following order.

1. First Embodiment

2. Second Embodiment

12. Application example to camera

1. First Embodiment

FIG.1is a diagram illustrating a configuration example of an imaging apparatus according to an embodiment of the present disclosure. The drawing is a diagram illustrating a configuration example of an imaging apparatus10which is an example of a semiconductor apparatus according to the embodiment of the present disclosure. A semiconductor apparatus according to the embodiment of the present disclosure will be described with reference to the imaging apparatus10in the drawing as an example.

The imaging apparatus10includes a semiconductor substrate130, a wiring region140, a transparent substrate172, an adhesive171, a semiconductor substrate110, and a wiring region120.

The imaging apparatus10is configured by bonding two semiconductor substrates, that is, semiconductor substrates130and110. The semiconductor substrate130constitutes an imaging element that generates an image signal on the basis of incident light. A plurality of pixels100is arranged in the imaging element. The pixel100includes a photoelectric conversion unit that performs photoelectric conversion of incident light. The photoelectric conversion unit can include a photodiode. Furthermore, in the pixel100, a pixel circuit that generates an image signal according to a charge generated by photoelectric conversion is arranged. Such pixels100are arrayed in a two-dimensional lattice pattern to form an imaging element. Furthermore, an on-chip lens109is arranged in each pixel100. The on-chip lens109is a lens arranged for each pixel100to focus incident light. In the drawing, an example of the on-chip lens109formed to have a hemispherical shape is described.

The semiconductor substrate130is a semiconductor substrate on which an imaging element is arranged. As the semiconductor substrate130, a semiconductor substrate including silicon (Si) can be used. In the semiconductor substrate130, diffusion regions of the photoelectric conversion unit of the pixel100and the element of the pixel circuit described above are formed. These diffusion regions are formed on the front surface side of the semiconductor substrate130. On the other hand, light incident on the photoelectric conversion unit of the pixel100is applied to the back surface side of the semiconductor substrate130. The above-described on-chip lens109is arranged on the back surface side of the semiconductor substrate130. Such an imaging element is referred to as a back-illuminated imaging element.

The wiring region140is a region arranged on the front surface side of the semiconductor substrate130and in which a wiring layer that transmits a signal to an element of the semiconductor substrate130is arranged. The wiring region140includes a wiring layer142and an insulating layer141. The wiring layer142is a wiring that transmits a signal to an element of the semiconductor substrate130. This wiring layer142can include a metal such as copper (Cu), for example. The insulating layer141insulates the wiring layer142. This insulating layer141can include an insulator, for example, silicon oxide (SiO2).

Furthermore, a pad144is arranged on the surface of the wiring region140. The pad144is an electrode-like terminal that transmits a signal. The pad144includes Cu or the like. The pad144transmits a signal between the semiconductor substrates130and110when the semiconductor substrates130and110are bonded together. When the semiconductor substrates130and110are bonded together, the pad144is joined to a pad124arranged in the wiring region120of the semiconductor substrate110as described later. The semiconductor region of the semiconductor substrate130and the wiring layer142are connected by a via plug143. The via plug143can include a columnar metal. Furthermore, the wiring layer142and the pad144can also be connected by the via plug143.

The transparent substrate172is a transparent substrate that protects the back surface side of the semiconductor substrate130. The transparent substrate172can include, for example, a glass substrate.

The adhesive171adheres the semiconductor substrate130and the transparent substrate172. Furthermore, the adhesive171is arranged adjacent to the back surface side of the semiconductor substrate130, which is a surface irradiated with incident light, and further performs sealing on the back surface side of the semiconductor substrate130.

As similar to the semiconductor substrate130, the semiconductor substrate110is a semiconductor substrate including Si or the like. For example, a processing circuit that processes an image signal generated by the pixel100of the semiconductor substrate130is arranged on the semiconductor substrate110. The signal processed in the processing circuit of the semiconductor substrate110is output to the outside of the imaging apparatus10. Furthermore, a control circuit that generates a control signal of the pixel100can be arranged on the semiconductor substrate110.

The wiring region120is a wiring region arranged on the front surface side of the semiconductor substrate110, and the wiring layer122, the insulating layer121, and the via plug123are arranged in the wiring region120. The wiring layer122is a wiring that transmits a signal of an element included in the above-described processing circuit or the like. Furthermore, the pad124is further arranged in the wiring region120. The pad124is an electrode-like terminal that is joined to the above-described pad144and transmits a signal.

When the semiconductor substrates130and110are bonded together, the wiring region140of the semiconductor substrate130and the wiring region120of the semiconductor substrate110are bonded together. At this time, the pad144of the wiring region140and the pad124of the wiring region120are aligned and joined. As a result, signals can be transmitted between the elements of the semiconductor substrates130and110.

The output of the signal generated by the imaging apparatus10to the outside, the input of the signal to the imaging apparatus10, and the like can be performed via a connection terminal182arranged on the back surface side of the semiconductor substrate110. The connection terminal182can include, for example, solder. Mounting of the imaging apparatus10on an external substrate can be performed by soldering the connection terminal182to an external substrate. Note that, as the connection terminal182, for example, a pillar including a metal material such as copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), nickel (Ni), ruthenium (Ru), or cobalt (Co) is used in addition to a solder ball formed by solder.

The back surface side wiring165is arranged on the back surface side of the semiconductor substrate110. The connection terminal182is arranged adjacent to and connected to the back surface side wiring165. The back surface side wiring165and the wiring layer122in the wiring region120of the semiconductor substrate110are connected by a through via (through silicon via (TSV))160.

Furthermore, a protective film180is arranged on the back surface side of the semiconductor substrate110. The protective film180is a film that protects the back surface side of the semiconductor substrate110excluding the connection terminal182. As the protective film180, for example, a solder resist can be used. Furthermore, as a material of the protective film180, for example, a polyimide resin, an acrylic resin, silicone, an epoxy resin, or the like, or a material in which a filler is contained in these resins is appropriately selected.

Note that the configuration of the imaging apparatus10is not limited to this example. For example, it is also possible to adopt a configuration in which a signal is transmitted by a through via penetrating the semiconductor substrate130instead of the pads124and144.

[Configuration of Back Surface Side of Semiconductor Substrate]

FIG.2is a diagram illustrating a configuration example of a back surface side of a semiconductor substrate according to a first embodiment of the present disclosure. The drawing is a diagram representing a configuration example of the vicinity of the through via160on the back surface side of the semiconductor substrate110, and is a diagram representing a configuration example on the back side of the imaging apparatus10. InFIG.2, the semiconductor substrate110obtained by making upside down the semiconductor substrate110ofFIG.1is described for convenience.

As illustrated inFIG.2, the imaging apparatus10further includes a through hole161, a through wiring169, a back surface side wiring165, a seed layer164, a barrier layer163, an insulating film162, and a separation region150in addition to the semiconductor substrate110, the wiring layer122, and the insulating layer121. The through via160is constituted by the through wiring169arranged in the through hole161. Note that the semiconductor substrate110is an example of a semiconductor substrate described in the claims. The wiring layer122is an example of a front surface side wiring described in the claims.

The back surface side wiring165is a wiring arranged on the back surface side of the semiconductor substrate110. As similar to the wiring layer122, the back surface side wiring165transmits a signal and the like of the pixel100. The back surface side wiring165can include Cu and can be formed by plating.

The through hole161is a hole penetrating the semiconductor substrate110. The through hole161can be formed by etching the semiconductor substrate110. Note that the through hole161illustrated inFIG.2further perforates the separation region150and the insulating layer121as described later. Furthermore, the hole shape of the through hole161is not limited to a circular shape, and may be another shape such as a rectangular shape.

The through wiring169is a wiring that connects the wiring layer122and the back surface side wiring165. The through wiring169is arranged in the through hole161. The through wiring169is arranged adjacent to the wiring layer122on the bottom surface of the through hole161and is connected to the wiring layer122. Furthermore, the through wiring169illustrated inFIG.2is configured integrally with the back surface side wiring165and connected to the back surface side wiring165.

The insulating film162is a film that is arranged on the back surface side of the semiconductor substrate110and insulates the back surface side wiring165and the through wiring169. This insulating film162can include, for example, SiO2.

The barrier layer163is arranged below the back surface side wiring165and the seed layer164to prevent diffusion of metal constituting the back surface side wiring165and the like into the semiconductor substrate110and the like. The barrier layer163can include, for example, titanium (Ti).

The seed layer164conducts a current when the back surface side wiring165is formed by electrolytic plating. The seed layer164can include Cu. Note that the barrier layer163and the seed layer164can also be regarded as conductors that are integrated with the back surface side wiring165and the through wiring169and constitute a part of the back surface side wiring165and the through wiring169.

The separation region150is arranged on the back surface side of the semiconductor substrate110to separate the semiconductor substrate110and the back surface side wiring165. The separation region150includes an insulator or a dielectric, and causes the back surface side wiring165to be separated and spaced from the back surface side of the semiconductor substrate110. By arranging the separation region150, the electrostatic capacitance between the back surface side wiring165and the semiconductor substrate110can be reduced. This is because the distance between the back surface side wiring165and the semiconductor substrate110becomes long. The separation region150can be formed to have a film thickness of, for example, equal to or greater than 5 μm. In this case, by setting the film thickness of the insulating film162to 2 μm, the distance between the back surface side wiring165and the semiconductor substrate110can be set to 7 μm. This makes it possible to obtain a transmission speed of a signal exceeding 9 Gbps. As the separation region150, for example, a resin having a relative permittivity smaller than that of SiO2, for example, is suitably used. Specifically, as the resin for forming the separation region150, a resin having a relative permittivity of equal to or less than 4.0 is preferably used, and a resin having a relative permittivity of equal to or less than 3 is more preferably applied. This is because the electrostatic capacitance between the back surface side wiring165and the semiconductor substrate110can be further reduced. Furthermore, the separation region150can include a resin, for example. Specifically, the separation region150can include an acrylic resin.

Furthermore, the separation region150can be used as a mask when the through hole161is formed by etching. Specifically, the separation region150is arranged as a resist for etching the semiconductor substrate110, and an opening is formed in a region where the through hole161is formed. The semiconductor substrate110adjacent to the opening is etched to form the through hole161. In this case, the separation region150preferably includes a photosensitive resin. This is because the opening of the separation region150can be easily formed.

As described above, the wiring layer122is connected to the photoelectric conversion unit of the pixel100of the semiconductor substrate130via the via plug123, the pads124and144, the via plug143, and the wiring layer142. The imaging apparatus10is configured such that a semiconductor substrate130constituting an imaging element is arranged on the front surface side of the semiconductor substrate110.

Note that the configuration of the imaging apparatus10is not limited to this example. An imaging element formed on the semiconductor substrate110can also be used instead of the semiconductor substrate130. In this case, the imaging element formed on the semiconductor substrate110has a configuration in which the front surface side of the imaging element (semiconductor substrate110) is irradiated with incident light.

[Method for Manufacturing Imaging Apparatus]

FIGS.3to5are diagrams illustrating an example of a method for manufacturing an imaging apparatus according to the first embodiment of the present disclosure.FIGS.3to5are diagrams illustrating a manufacturing process of the through via160in the semiconductor substrate110of the imaging apparatus10.

First, the semiconductor substrate130and the semiconductor substrate110are bonded to each other, and the on-chip lens109is formed on the semiconductor substrate130. Next, the transparent substrate172is bonded to the back surface side of the semiconductor substrate130using the adhesive171.

Next, a photosensitive resin film401is arranged on the back surface side of the semiconductor substrate110. The resin film401can be configured to have a film thickness of 10 μm, for example. This can be performed by applying a liquid resin (FIG.3A). Next, an opening402is formed in a region of the resin film401where the through hole161is to be formed, and the separation region150is formed. This can be formed by exposing and developing the resin film401using a mask in which the pattern of the opening402is formed (FIG.3B). This step corresponds to the separation region arrangement step.

Next, the through hole161is formed in the semiconductor substrate110. This can be performed by etching the semiconductor substrate110using the separation region150as a mask. For this etching, for example, anisotropic dry etching can be applied (FIG.3C). At this time, the separation region150is also etched to reduce the film thickness, and the film thickness becomes approximately 5 μm. After the etching, a chemical solution is used for cleaning to remove the etching product. This step corresponds to a through hole forming step.

Next, an insulator film403is arranged adjacent to the separation region150. At this time, the insulator film403is also arranged on the bottom surface and the wall surface of the through hole161. This can be performed, for example, by forming a SiO2film using chemical vapor deposition (CVD). The insulator film403can be formed to have a film thickness of 4 μm, for example (FIG.4D). At the time of film formation, the insulator film403adjacent to the bottom surface and the side wall of the through hole161is configured to be thinner than the insulator film403adjacent to the separation region150. This is because of step coverage of CVD.

Next, the insulator film403is etched (so-called etch-back) to remove the insulator film403at the bottom of the through hole161. Therefore, the insulating film162adjacent to the separation region150and the side walls of the through hole161can be formed. Thereafter, etching is further performed to remove the insulating layer121adjacent to the wiring layer122. As a result, the through hole161extending from the back surface side of the semiconductor substrate110to the wiring layer122can be formed. This etching can be performed by, for example, anisotropic dry etching (FIG.4E). At the time of this etching, the insulating film162is also etched, and the film thickness of the region adjacent to the separation region150becomes approximately 2 μm.

Next, the metal films404and405are arranged adjacent to the insulating film162. In a subsequent step, these films are configured as the barrier layer163and the seed layer164. The metal film404can be arranged by forming a Ti film. Furthermore, the metal film405can be arranged by forming a Cu film. These films can be formed, for example, by sputtering (FIG.4F).

Next, a resist406is arranged adjacent to the metal film405. In the resist406, an opening407is arranged in a region where the back surface side wiring165is formed. Next, electrolytic plating is performed to form the back surface side wiring165and the through wiring169(FIG.5G). This step corresponds to the back surface side wiring arrangement step and the through wiring arrangement step.

Next, the resist406is removed, and the metal films404and405in a region other than the lower layer of the back surface side wiring165are removed. As a result, the barrier layer163and the seed layer164are formed (FIG.5H).

Thereafter, the imaging apparatus10can be manufactured by arranging the protective film180and the connection terminal182.

Through the above steps, the separation region150, the back surface side wiring165, and the through via160can be formed. In the step illustrated inFIG.4Edescribed above, the insulating film162is arranged on the semiconductor substrate110on the wall surface of the through hole161, and then the insulating layer121is etched, so that Cu constituting the wiring layer122can be prevented from diffusing into the semiconductor substrate110.

Note that the method for manufacturing the imaging apparatus10is not limited to this example. For example, in the step illustrated inFIG.3C, the insulating layer121can be etched in addition to the semiconductor substrate110to form the through hole161.

As described above, in the imaging apparatus10of the first embodiment of the present disclosure, the separation region150is arranged between the semiconductor substrate110and the back surface side wiring165, so that the semiconductor substrate110and the back surface side wiring165can be spaced from each other. As a result, the electrostatic capacitance between the back surface side wiring165and the semiconductor substrate110can be reduced, and the parasitic capacitance of the back surface side wiring165can be reduced. This enables high-speed signal transmission in the back surface side wiring165.

2. Second Embodiment

The imaging apparatus10of the above-described first embodiment uses the separation region150including a resin. On the other hand, the imaging apparatus10of a second embodiment of the present disclosure is different from that of the above-described first embodiment in that a separation region including an inorganic material is used.

[Configuration of Back Surface Side of Semiconductor Substrate]

FIG.6is a diagram illustrating a configuration example of a back surface side of a semiconductor substrate according to the second embodiment of the present disclosure. As similar toFIG.2, the drawing is a diagram illustrating a configuration example of the vicinity of the through via160on the back surface side of the semiconductor substrate110, and is a diagram illustrating a configuration example on the back side of the imaging apparatus10. The imaging apparatus10is different from the imaging apparatus10described in the first embodiment as illustrated inFIG.2in that a separation region151is arranged instead of the separation region150.

The separation region151is a separation region including inorganic material. The separation region151can include, for example, SiO2, SiOF, SiOC, and SiC. Furthermore, the separation region151can be used also as a mask when the through hole161is formed.

[Method for manufacturing imaging apparatus]

FIG.7is a diagram illustrating an example of a method for manufacturing an imaging apparatus according to the second embodiment of the present disclosure. As similar toFIGS.3to5, the drawing is a diagram illustrating a manufacturing process of the through via160in the semiconductor substrate110of the imaging apparatus10.

First, a material film408of the separation region151is arranged on the back surface side of the semiconductor substrate110(FIG.7A).

Next, a resist409is arranged adjacent to the material film408. In the resist409, an opening410is arranged in a region where the through hole161is formed (FIG.7B).

Next, the material film408is etched using the resist409as a mask to form the separation region151. For this etching, dry etching can be applied. Next, etching of the semiconductor substrate110is continuously performed using the separation region151as a mask. As a result, the through hole161can be formed (FIG.7C).

Thereafter, the imaging apparatus10can be manufactured by applying the step fromFIG.4D.

In the above-described step illustrated inFIG.7B, after etching is performed using the resist409as a mask to form the separation region151, the separation region151becomes a new mask. Since it is not necessary to use the resist409as a mask for etching the semiconductor substrate110, the resist409having a relatively thin film thickness can be used.

The other configuration of the imaging apparatus10is similar to the configuration of the imaging apparatus10described in the first embodiment of the present disclosure, and thus a description thereof will not be repeated.

As described above, the imaging apparatus10of the second embodiment of the present disclosure can use the separation region151including inorganic material, and can reduce the parasitic capacitance of the back surface side wiring165by separating the semiconductor substrate110and the back surface side wiring165from each other.

In the imaging apparatus10of the above-described first embodiment, the back surface side wiring165and the through wiring169are insulated by the insulating film162. On the other hand, the imaging apparatus10of a third embodiment of the present disclosure is different from the above-described first embodiment in that the back surface side wiring165and the through wiring169are insulated by a separation region.

[Configuration of back surface side of semiconductor substrate]

FIG.8is a diagram illustrating a configuration example of a back surface side of a semiconductor substrate according to the third embodiment of the present disclosure. As similar toFIG.2, the drawing is a diagram illustrating a configuration example of the vicinity of the through via160on the back surface side of the semiconductor substrate110, and is a diagram illustrating a configuration example on the back side of the imaging apparatus10. The imaging apparatus10is different from the imaging apparatus10described in the first embodiment as illustrated inFIG.2in that the insulating film162is not included, and a separation region152is arranged instead of the separation region150.

The separation region152is a separation region arranged on the back surface side of the semiconductor substrate110and the wall surface of the through hole161. The separation region152insulates the through wiring169from the semiconductor substrate110. The separation region152can include a photosensitive resin, for example.

[Method for Manufacturing Imaging Apparatus]

FIGS.9and10are diagrams illustrating an example of a method for manufacturing an imaging apparatus according to the third embodiment of the present disclosure. As similar toFIGS.3to5,FIGS.9and10are diagrams illustrating a manufacturing process of the through via160in the semiconductor substrate110of the imaging apparatus10.

First, a resist411is arranged on the back surface side of the semiconductor substrate110. This resist411is a resist in which an opening412is arranged in a region where the through hole161is formed (FIG.9A).

Next, the semiconductor substrate110is etched using the resist411as a mask to form the through hole161(FIG.9B).

Next, the resist411is removed (FIG.9C). Next, a resin film413is arranged on the back surface side of the semiconductor substrate110. The resin film413is a film including a photosensitive resin. At this time, the resin film413is arranged and embedded in the through hole161(FIG.10D).

Next, the resin film413is exposed and developed to form a through hole168in a region where the through via160is to be formed. The through hole168is a through hole having a smaller diameter than that of the through hole161. As a result, a resin film is formed on the wall surface of the semiconductor substrate110, and the separation region152can be formed (FIG.10E).

Next, the insulating layer121is etched using the separation region152as a mask (FIG.10F).

Thereafter, the imaging apparatus10can be manufactured by applying the step fromFIG.4F.

The other configuration of the imaging apparatus10is similar to the configuration of the imaging apparatus10described in the first embodiment of the present disclosure, and thus a description thereof will not be repeated.

As described above, in the imaging apparatus10of the third embodiment of the present disclosure, the insulating film162can be eliminated by arranging the separation region152adjacent to the back surface side of the semiconductor substrate110and the wall surface of the through hole161. The manufacturing process of the imaging apparatus10can be simplified.

In the imaging apparatus10of the above-described first embodiment, the separation region150is arranged between the back surface side wiring165and the semiconductor substrate110. On the other hand, the imaging apparatus10of a fourth embodiment of the present disclosure is different from the above-described first embodiment in that a separation region is further arranged in a recess portion formed on the back surface side of the semiconductor substrate110.

[Configuration of Back Surface Side of Semiconductor Substrate]

FIG.11is a diagram illustrating a configuration example of a back surface side of a semiconductor substrate according to the fourth embodiment of the present disclosure. As similar toFIG.2, the drawing is a diagram illustrating a configuration example of the vicinity of the through via160on the back surface side of the semiconductor substrate110, and is a diagram illustrating a configuration example on the back side of the imaging apparatus10. The imaging apparatus10is different from the imaging apparatus10described inFIG.2in that the separation region153is further arranged.

The separation region153is a separation region arranged in a recess portion166formed on the back surface side of the semiconductor substrate110. That is, the configuration according to the present embodiment includes, as the separation regions, the separation region150which is a planar separation region formed between the back surface side wiring165and the semiconductor substrate110, and the separation region153which is an in-recess portion separation region formed in the recess portion166. The separation region153can be arranged on the back surface side of the semiconductor substrate110below the back surface side wiring165. In the region where the separation region153is arranged, the distance between the back surface side wiring165and the semiconductor substrate110increases, so that the electrostatic capacitance decreases. Therefore, by arranging the separation region153, the electrostatic capacitance between the back surface side wiring165and the semiconductor substrate110in the drawing can be reduced.

As illustrated inFIG.11, a plurality of the separation region153can be arranged. Furthermore, the separation region153can include the same material as the material of the separation region150, and can be formed simultaneously. The separation region153can include a photosensitive resin, for example. Furthermore, the recess portion166can be configured to have a depth of 3 μm, for example.

[Configuration of Back Surface Side of Semiconductor Substrate]

FIG.12is a plan view illustrating a configuration example of the back surface side of the semiconductor substrate according to the fourth embodiment of the present disclosure. The drawing is a plan view illustrating a configuration example of the separation region153and the recess portion166. In the drawing, a solid rectangle represents the back surface side wiring165. A dashed rectangle represents the recess portion166of the semiconductor substrate110.

FIG.12Ais a diagram illustrating an example of the recess portion166having a rectangular shape on the back surface side of the semiconductor substrate110. The separation region153is arranged in the recess portion166ofFIG.12A. The separation region153inFIG.12Ahas a rectangular shape on the back surface side of the semiconductor substrate110. Note that, the recess portion166can be configured to have a width of equal to or less than 3 μm, for example.

FIG.12Bis a diagram illustrating an example of the recess portion166formed in a groove shape. The separation region153inFIG.12Bis also formed in a groove shape. The recess portion166inFIG.12Bcan be formed in a groove shape having a width of equal to or less than 3 μm, for example.

Note that the configuration of the separation region153is not limited to this example. For example, the separation region153may be formed in another shape such as a mesh shape.

[Method for Manufacturing Imaging Apparatus]

FIGS.13and14are diagrams illustrating an example of a method for manufacturing an imaging apparatus according to the fourth embodiment of the present disclosure. As similar toFIGS.3to5,FIGS.13and14are diagrams illustrating a manufacturing process of the through via160in the semiconductor substrate110of the imaging apparatus10.

First, a resist414is arranged on the back surface side of the semiconductor substrate110. This resist414is a resist in which an opening415is arranged in a region where the recess portion166is formed (FIG.13A).

Next, the semiconductor substrate110is etched using the resist414as a mask to form the recess portion166(FIG.13B).

Next, the resist414is removed (FIG.13C). Next, a resin film417is arranged on the back surface side of the semiconductor substrate110. The resin film417is a film including a photosensitive resin. At this time, the resin film417is arranged and embedded in the recess portion166. As a result, the separation region153can be formed (FIG.14D).

Next, the resin film417is exposed and developed to form an opening418in a region where the through hole161is to be formed. As a result, the separation region150can be formed (FIG.14E).

Next, the semiconductor substrate110is etched using the separation region150as a mask to form the through hole161(FIG.14F).

Thereafter, the imaging apparatus10can be manufactured by applying the step fromFIG.4D.

The other configuration of the imaging apparatus10is similar to the configuration of the imaging apparatus10described in the first embodiment of the present disclosure, and thus a description thereof will not be repeated.

As described above, the imaging apparatus10of the fourth embodiment of the present disclosure can further reduce the parasitic capacitance of the back surface side wiring165by forming the recess portion166on the back surface side of the semiconductor substrate110and further arranging the separation region153.

The imaging apparatus10of the above-described fourth embodiment uses the separation region153including a resin. On the other hand, the imaging apparatus10of a fifth embodiment of the present disclosure is different from that of the above-described fourth embodiment in that a separation region including a gap is used.

[Configuration of Back Surface Side of Semiconductor Substrate]

FIG.15is a diagram illustrating a configuration example of a back surface side of a semiconductor substrate according to the fifth embodiment of the present disclosure. As similar toFIG.11, the drawing is a diagram illustrating a configuration example of the vicinity of the through via160on the back surface side of the semiconductor substrate110, and is a diagram illustrating a configuration example on the back side of the imaging apparatus10. The imaging apparatus10is different from the imaging apparatus10described in the fourth embodiment as illustrated inFIG.11in that the separation region150is not included, and a separation region154is arranged instead of the separation region153.

As similar to the separation region153, the separation region154is a separation region arranged in the recess portion166of the semiconductor substrate110. The separation region154can include an insulator having a gap155therein. The separation region154in the drawing is an example in which SiO2that is an insulator constituting the insulating film162is embedded in the recess portion166. When this SiO2is embedded in the recess portion166, the gap155is formed. This can be performed by using a film forming method with low step coverage such as CVD when forming the SiO2film.

In a case where the insulating film162is a separation region, the configuration according to the present embodiment includes, as separation regions, an in-hole separation region that covers a wall surface (inner circumferential surface) of the through hole161, a planar separation region formed on a back surface side of the semiconductor substrate110, and a separation region154that is an in-recess portion separation region formed in the recess portion166. Then, a gap155is formed in the separation region154. Note that the gap155is only required to be formed such that at least a part thereof is located in the recess portion166. That is, the entire gap155may be located in the recess portion166, and a part of the gap155may be located over a portion from the recess portion166to the insulating film162.

Air or the like can be enclosed in the gap155. Since the relative permittivity of air is approximately 1.0, the electrostatic capacitance between the back surface side wiring165and the semiconductor substrate110can be further reduced. The recess portion166inFIG.15is preferably configured to have a width of equal to or less than 2 μm. This is to facilitate closing of the opening of the recess portion166in the step of forming the gap155as described later. Note that, since the separation region150is not included in the imaging apparatus10in the drawing, the insulating film162in the drawing is preferably configured to have a thick film. The insulating film162in the drawing can be configured to have a film thickness of 7 μm, for example.

[Method for Manufacturing Imaging Apparatus]

FIG.16is a diagram illustrating an example of a method for manufacturing an imaging apparatus according to a fifth embodiment of the present disclosure. As similar toFIGS.13to14, the drawing is a diagram illustrating a manufacturing process of the through via160in the semiconductor substrate110of the imaging apparatus10.

First, the steps ofFIGS.13A to14Fare performed, and etching is performed on the semiconductor substrate110on which the recess portion166is formed to form the through hole161. At the time of this etching, a resist419is used instead of the separation region150(FIG.16A).

Next, the resist419is removed (FIG.16B). Next, an insulator film420is arranged on the back surface side of the semiconductor substrate110. This can be performed by forming a film of SiO2using CVD. At this time, the gap155can be formed by forming the insulator film420on the bottom surface and the side surface of the recess portion166and closing the opening of the recess portion166(FIG.16C).

Thereafter, the imaging apparatus10can be manufactured by applying the step fromFIG.4E.

The other configuration of the imaging apparatus10is similar to the configuration of the imaging apparatus10described in the fourth embodiment of the present disclosure, and thus a description thereof will not be repeated.

As described above, the imaging apparatus10of the fifth embodiment of the present disclosure can further reduce the parasitic capacitance of the back surface side wiring165by arranging the separation region154having the gap155.

The imaging apparatus10of the above-described fifth embodiment has the gap155in the separation region154in the recess portion166formed on the back surface side of the semiconductor substrate110. On the other hand, the imaging apparatus10of a sixth embodiment of the present disclosure is different from the fifth embodiment in that a portion formed on the back surface side of the semiconductor substrate110in the separation region includes a gap.

[Configuration of Back Surface Side of Semiconductor Substrate]

FIG.17is a diagram illustrating a configuration example of a back surface side of a semiconductor substrate according to the sixth embodiment of the present disclosure. As similar toFIG.15,FIG.17is a cross-sectional view illustrating a configuration example of the vicinity of the through via160on the back surface side of the semiconductor substrate110, and is a cross-sectional view illustrating a configuration example on the back side of the imaging apparatus10. The configuration according to the present embodiment is different from the imaging apparatus10described in the fifth embodiment as illustrated inFIG.15in that the recess portion166is not formed on the back surface side of the semiconductor substrate110and the gap157is provided in the separation region156.

As illustrated inFIG.17, the imaging apparatus10according to the present embodiment includes a through wiring169that is arranged in the through hole161formed in the semiconductor substrate110and connects the wiring layer122and the back surface side wiring165. Then, the separation region156is formed in a portion extending from the inside of the through hole161of the semiconductor substrate110to the back surface side of the semiconductor substrate110. That is, the separation region156includes an in-hole separation region portion156acovering the inner circumferential surface161aof the through hole161and a back surface side separation region portion156bformed on the back surface110aside of the semiconductor substrate110.

The in-hole separation region portion156ais formed as a film-like portion covering the inner circumferential surface161aof the through hole161, and has a cylindrical shape corresponding to the hole shape of the through hole161. The barrier layer163, the seed layer164, and the back surface side wiring165are sequentially stacked on the inner circumferential side of the in-hole separation region portion156a.

The back surface side separation region portion156bis a layer portion covering the back surface110aof the semiconductor substrate110. The barrier layer163, the seed layer164, and the back surface side wiring165are sequentially stacked on the upper side of the portion around the formation portion of the through hole161in the back surface side separation region portion156b. The in-hole separation region portion156aand the back surface side separation region portion156bare formed as portions continuous with each other.

In such a configuration including the separation region156, the gap157is formed in the back surface side separation region portion156b. The gap157is a hollow portion in the separation region156, and air or the like is enclosed therein. The gap157is formed at a plurality of positions with a common formation range in the thickness direction (vertical direction inFIG.17) of the back surface side separation region portion156b.

FIG.18is a plan view illustrating a configuration example of the back surface side of the semiconductor substrate according to the sixth embodiment of the present disclosure.FIGS.18A and18Bare plan views illustrating planar arrangement examples of the gaps157.

As illustrated inFIG.18A, the gaps157are formed, for example, in a two-dimensional lattice point-like arrangement. In such an arrangement of the gaps157, the gaps157located around the through via160are formed so as to partially or entirely overlap the back surface side wiring165in plan view. That is, as the gap157, there are an outer gap157A formed outside the back surface side wiring165in plan view and an inner gap157B formed so as to at least partially overlap with the back surface side wiring165in plan view. The inner gap157B is a gap157formed such that at least a part thereof is located in a portion of the separation region156sandwiched between the back surface110aof the semiconductor substrate110and the barrier layer163.

As illustrated inFIG.18B, the gaps157are formed in a plurality of linear arrays arranged in parallel, for example. In such an arrangement of the gaps157, the gaps157located around the through via160are formed so as to partially overlap the back surface side wiring165in plan view. That is, as the gap157, there are a gap157C formed so as not to overlap the back surface side wiring165in plan view and a gap157D formed so as to partially overlap with the back surface side wiring165in plan view.

Note that the arrangement of the gaps157is not limited to these examples. As the plan view shape of the gap157, a circular shape, a polygonal shape, an elliptical shape, or the like is appropriately adopted. Furthermore, the gaps157may be formed in another pattern such as a lattice pattern (mesh pattern).

[Method for Manufacturing Imaging Apparatus]

FIGS.19and20are diagrams illustrating an example of a method for manufacturing an imaging apparatus according to the sixth embodiment of the present disclosure. As similar toFIGS.3to5,FIGS.19and20are diagrams illustrating a manufacturing process of the through via160in the semiconductor substrate110of the imaging apparatus10.

First, as illustrated inFIG.19A, a material film431including the material of the separation region156is formed on the back surface side of the semiconductor substrate110. The material film431is formed with a thickness of 2.5 μm on the entire back surface110aof the semiconductor substrate110using SiO2as a material, for example.

Next, as illustrated inFIG.19B, a resist432for forming a recess portion (trench) is formed on the material film431. The resist432is partially formed in a range of the entire surface of the material film431according to the formation positions of the gaps157by patterning using a photolithography technology, for example. The arrangement of the opening432awhich is a portion where the resist432is not formed corresponds to the final arrangement of the gap157.

Next, as illustrated inFIG.19C, the material film431is etched using the resist432as a mask, and a pattern is formed on the material film431. For this etching, for example, dry etching is used. Through this step, the material film431is partially removed, and the material film433having the uneven portion corresponding to the shape of the resist432is formed. Note that, after the formation of the material film433, the resist432is peeled off and removed.

In the etching step of forming the material film433, the material film431is partially removed such that a bottom portion433acovering the entire back surface110aof the semiconductor substrate110remains. Accordingly, the etched material film433has the bottom portion433a, a convex portion433bcorresponding to the shape of the resist432, and a recess portion433cformed between the adjacent convex portions433b. The recess portion433cfinally becomes a portion forming the gap157in the separation region156.

Next, as illustrated inFIG.19D, a resist434for forming the through via160is formed on the material film433by patterning or the like using a photolithography technology. The resist434is formed so as to fill the recess portion433cof the material film433and to be stacked on the material film433. In the resist434, an opening434ais formed in a region corresponding to a formation portion of the through hole161.

Next, as illustrated inFIG.20A, the semiconductor substrate110is etched using the resist434as a mask to form the through hole161. For this etching, for example, dry etching is used. In this step, only the semiconductor substrate110forming the through hole161is etched, and the insulating layer121on the front surface side of the semiconductor substrate110is not etched.

Next, as illustrated inFIG.20B, after the resist434is peeled off and removed, a film is formed by the material of the separation region156. Here, for example, a film is formed with a thickness of 9 μm using SiO2that is the same material as the material film433as a material by a CVD method. By this film forming step, the insulator film435is formed. The insulator film435includes a bottom film portion435athat covers the surface of the insulating layer121exposed by etching for forming the through hole161, an in-hole film portion435bthat covers the inner circumferential surface161aof the through hole161, and a surface layer film portion435cformed on the material film433.

Through this film forming step, the recess portion433cof the material film433is closed by the layer film portion435cof the insulator film435from above, and thereby, the gap157is formed. In this film forming step, a film forming method and film forming conditions with low step coverage, that is, low coverage, such as CVD, are used in order to form the gap157.

Subsequently, as illustrated inFIG.20C, the insulator film435is etched (so-called etch-back) to remove the bottom film portion435aof the bottom portion of the through hole161. As a result, the separation region156having the gap157is formed. Thereafter, by further performing etching, the portion of the insulating layer121on the wiring layer122is completely removed, and the upper surface of the wiring layer122is exposed to the through hole161side. As a result, the through hole161extending from the back surface side of the semiconductor substrate110to the wiring layer122is formed.

For this etching, for example, anisotropic dry etching is used. In this etching step, as the bottom film portion435ais removed, the film thickness of the surface layer film portion435cis also reduced. This etching step is performed such that the film thickness of a back surface side separation region portion156b, which is a field portion of the separation region156, remains by, for example, 9 μm.

Then, as illustrated inFIG.20D, after the barrier layer163and the seed layer164are formed, the through wiring169is formed. Steps subsequent to the step of forming these layers are similar to those in the first embodiment, and thus are omitted.

According to the configuration of the sixth embodiment of the present disclosure, the separation region156having the gap157in the field portion is provided between the semiconductor substrate110and the back surface side wiring165, so that the parasitic capacitance of the back surface side wiring165can be effectively reduced. That is, for example, air is sealed in the gap157, so that the dielectric constant of the separation region156can be reduced, and the parasitic capacitance can be reduced. As a result, a signal propagation delay can be suppressed, and a high-speed operation can be achieved. In particular, by forming the gap157so as to overlap the back surface side wiring165in plan view, the parasitic capacitance between the semiconductor substrate110and the back surface side wiring165can be effectively reduced.

Furthermore, in the method for manufacturing the imaging apparatus10according to the present embodiment, the trench of the insulator film435is not completely embedded by the material for forming the separation region156using the film forming method and film forming conditions with low coverage, and thereby, the gap157can be formed. As a result, the separation region156having the gap157can be formed at low cost, and the parasitic capacitance can be reduced.

Furthermore, according to the configuration according to the present embodiment, the following effects can be obtained in the relationship with the configuration according to the fifth embodiment (seeFIG.15) in which the recess portion166is formed in the semiconductor substrate110and the gap155is formed in the separation region154in the recess portion166. That is, since the step of forming the recess portion166in the semiconductor substrate110is unnecessary, the manufacturing method can be simplified. Furthermore, since the gap157is formed in the field portion on the back surface110aof the semiconductor substrate110in the separation region156, the gap157can be formed closer to the through via160side in the direction along the back surface110a(right and left direction inFIG.17). That is, the range in which the gap157can be formed can be widened on the through via160side. As a result, the parasitic capacitance can be effectively reduced.

In the configuration including the through via160, the imaging apparatus10of the above-described fourth embodiment includes the separation region153in the recess portion166formed on the back surface side of the semiconductor substrate110. On the other hand, a semiconductor apparatus10A of a seventh embodiment of the present disclosure is different from that of the fourth embodiment mainly in that the through via160is not provided.

FIG.21is a diagram illustrating a configuration example of the semiconductor apparatus according to the seventh embodiment of the present disclosure. As illustrated inFIG.21, in the semiconductor apparatus10A according to the present embodiment, a rewiring501as a back surface side wiring is provided on the back surface110aside of the semiconductor substrate110, and a plurality of recess portions503is formed on the back surface110aside of the semiconductor substrate110. Furthermore, the separation region505is arranged using an insulating resin so as to fill the recess portion503and cover the back surface110aof the semiconductor substrate110. The rewiring501is formed on the separation region505.

As described above, the semiconductor apparatus10A includes the rewiring501arranged on the back surface side of the semiconductor substrate110and the separation region505arranged between the semiconductor substrate110and the rewiring501.

As illustrated inFIG.21, in the semiconductor apparatus10A, a frame-shaped peripheral edge portion along an outer shape of the semiconductor substrate110that is, for example, a rectangular chip is a scribe region507. The scribe region507is a region where a scribe line defining the regularly arrayed and formed chip region508is located before the dicing step of dividing the semiconductor substrate110is performed. A region inside the scribe region507is the chip region508(seeFIG.31).

As illustrated inFIG.21, in the semiconductor substrate110, a plurality of recess portions503is formed in a regular array. The plurality of recess portions503is formed at a predetermined depth Dl with respect to the back surface110aof the semiconductor substrate110. In the example illustrated inFIG.21, the adjacent recess portions503are formed at intervals narrower than the dimension of the recess portion503in the width direction (the right and left direction inFIG.21). Accordingly, a wall portion110bhaving a width (thickness) smaller than the dimension in the width direction of the recess portion503is formed between the adjacent recess portions503. That is, the adjacent recess portions503are defined by the wall portion110b.

In the example illustrated inFIG.21, the recess portion503is formed along a rectangular shape in a cross-sectional view by an inner side surface503aperpendicular to the horizontal back surface110aand a horizontal bottom surface503b, but the shape of the recess portion503is not limited. The shape of the recess portion503may be, for example, a shape in which the inner side surface503ais inclined with respect to the vertical direction, a shape in which a corner portion formed by the inner side surface503aand the back surface110ais a chamfered curved surface, or the like. Furthermore, the depth of the recess portion503is also not limited. The recess portion503may be, for example, a hole penetrating the semiconductor substrate110. Furthermore, the recess portion503is formed, for example, in the semiconductor substrate110so that the aperture ratio with respect to the back surface110ais 50 to 95%.

Furthermore, regarding the formation portion of the recess portion503in the semiconductor substrate110, a configuration in which the recess portion503is formed only in the chip region508and the recess portion503is not formed in the scribe region507is preferably adopted. In the separation region505, a portion formed by filling the recess portion503with the resin material is a portion thicker than other portions. For this reason, in a case where there is a layer thickness portion of the separation region505by the recess portion503in the scribe region507, it is difficult to perform cutting processing at the time of dividing the chip depending on the resin material of the separation region505. Accordingly, a configuration in which the recess portion503is not formed in the scribe region507is advantageous from the viewpoint of facilitating the cutting processing.

As illustrated inFIG.21, the separation region505includes a recess portion inner region portion511which is a portion including resin filled in the recess portion503, and a surface layer region portion512which covers the back surface110aof the semiconductor substrate110and is a portion connecting the plurality of recess portion inner region portions511. The surface layer region portion512forms a flat front surface505ain the separation region505. In the example illustrated inFIG.21, the recess portion inner region portion511is formed by completely filling the recess portion503with the material of the separation region505, but a gap may be formed in the recess portion inner region portion511. Furthermore, a configuration in which the entire recess portion503is hollow, that is, the separation region505has only the layer region portion512may be adopted.

Examples of the resin material forming the separation region505include polyimide resin, acrylic resin, silicone, epoxy resin, and the like. Note that a similar material can be applied to the separation region in other embodiments.

The rewiring501is formed on the front surface505aof the separation region505. The rewiring501includes a single conductive film or a plurality of stacked conductive films. The rewiring501includes, for example, a metal material such as Cu, Ti, Ta, Al, W, Ni, Ru, or Co. Note that a film including an insulating material may be stacked on the front surface505aof the separation region505, and the rewiring501may be formed on the film.

The rewiring501is provided with the connection terminal182as an external terminal. On the front surface505aside of the separation region505, except for the connection portion of the connection terminal182to the rewiring501, a protective film515which is a wiring protective film covering the rewiring501and the back surface110ais formed.

[Method for Manufacturing Semiconductor Apparatus]

FIGS.22and23are diagrams illustrating an example of a method for manufacturing the semiconductor apparatus10A according to the seventh embodiment of the present disclosure.

First, as illustrated inFIG.22A, a step of forming the recess portion503on the back surface110aside of the semiconductor substrate110is performed. In this step, a resist (not illustrated) corresponding to the formation mode of the recess portion503is formed on the back surface110aof the semiconductor substrate110by photolithography, and the back surface110aside of the semiconductor substrate110is partially removed by etching such as dry etching to form the recess portion503.

Next, as illustrated inFIG.22B, a step of forming the separation region505is performed. This step corresponds to a separation region arrangement step of arranging the separation region505on the back surface side of the semiconductor substrate110. In this step, a coating method, a lamination method, or the like is used, and a film is formed using an insulating resin which is a material of the separation region505. In a case where the resin of the material of the separation region505is a thermosetting resin, a heat treatment for curing the resin is performed. Here, for example, the annealing treatment may be performed at a temperature higher than the curing temperature of the resin. By this step, the separation region505including the recess portion inner region portion511and the surface layer region portion512is formed.

Note that, since the surface of the resin is more easily planarized than at least the surface of the semiconductor substrate110, the rewiring501is easily formed. Furthermore, in the step of forming the separation region505, the resin that is the material of the separation region505may be completely filled in the recess portion503as illustrated inFIG.22B, or a cavity may be formed in the resin in the recess portion503.

Next, as illustrated inFIG.22C, a step of forming the rewiring501on the front surface505aof the separation region505is performed. This step corresponds to a back surface side wiring arrangement step of arranging the rewiring501on the back surface side of the semiconductor substrate110. The rewiring501is formed as a stacked film of a barrier layer including Ti and a wiring layer including Cu, for example. For the formation of the rewiring501, for example, a known method such as a semi-additive method, a subtractive method, or a damascene method is used. Preferably, the rewiring501is arranged so as to entirely overlap the recess portion503in plan view, but a part of the rewiring501may be arranged so as not to overlap the recess portion503in plan view.

Next, as illustrated inFIG.23A, a step of forming the protective film515is performed. In this step, for example, first, a coating method or a lamination method is used, and film formation with a photosensitive insulating resin is performed. Then, a region of a formation portion of the connection terminal182is opened with respect to the formed film by a lithography method, and the opening515ais formed.

Then, as illustrated inFIG.23B, the connection terminal182is arranged in the opening515aof the protective film515. The semiconductor apparatus10A is manufactured by the above method.

The effect of the semiconductor apparatus10A according to the present embodiment as described above will be described. For example, a semiconductor substrate including Si is excellent in flatness, mechanical strength, and microfabrication performance, but on the other hand, since the semiconductor substrate is not an insulator, there is a problem that a parasitic element is generated between the semiconductor substrate and a rewiring or a through electrode, and signal transmission characteristics are deteriorated. In order to solve such a problem, there have been proposed a conventional method in which a low dielectric constant material is used for a liner film, which is an insulating film arranged between a semiconductor substrate and a rewiring, or the thickness of the liner film is increased (for example, Japanese Patent Application Laid-Open No. 2010-205990), and a conventional method in which the parasitic capacitance is reduced by delving a substrate around a through electrode (for example, Japanese Patent Application Laid-Open No. 2015-153930).

However, according to the former method related to the liner film, since the liner film becomes thick, the chip becomes thicker and the weight also increases accordingly. This is disadvantageous for high integration of the semiconductor apparatus. Furthermore, in a case where the chip becomes thicker, in a case of a configuration having a through electrode, the difficulty of manufacturing the through electrode increases, leading to an increase in cost and a decrease in yield. Furthermore, according to the latter method of delving down the substrate, it is possible to reduce the capacitance around the through electrode, but the capacitance reduction for the rewiring is not considered.

Therefore, the semiconductor apparatus10A according to the present embodiment has a configuration in which the recess portion503is formed in the semiconductor substrate110, the separation region505including an insulating resin is arranged in the recess portion503and on the back surface110aof the semiconductor substrate110, and the rewiring501is provided on the separation region505. According to such a configuration, parasitic capacitance (capacitance between wiring substrates) between the rewiring501and the semiconductor substrate110can be reduced without causing an increase in the thickness of the chip or a significant decrease in the mechanical strength of the chip.

Furthermore, by using a material having a specific gravity smaller than that of the semiconductor substrate110as the resin material of the separation region505, it is possible to reduce the weight of the chip. As described above, since it is possible to reduce the thickness and weight of the chip, it is possible to obtain a configuration suitable for high integration.

Furthermore, in the separation region505, by forming a gap in the recess portion inner region portion511which is a portion formed in the recess portion503, the capacitance between wiring substrates can be effectively reduced.

Furthermore, in the semiconductor apparatus10A, the rewiring501is provided so as to at least partially overlap the recess portion503in plan view. According to such a configuration, the capacitance between wiring substrates can be reduced. In particular, in the present embodiment, since the rewiring501is provided so as to mostly overlap the recess portion503in plan view, the capacitance between wiring substrates can be effectively reduced. The fact that such an effect can be obtained will be described using a result of simulation regarding the capacitance between wiring substrates.

FIG.24Ais a diagram illustrating a configuration used in this simulation and dimensions of each part in the configuration. As illustrated inFIG.24A, in the present simulation, a configuration is used in which the separation region505is formed in a portion including the recess portion503of the semiconductor substrate110, and the rewiring501is arranged at a position above the recess portion503. Furthermore, the rewiring501has a thickness of 1.5 μm and a width of 3 μm. Furthermore, each of the vertical dimension and the horizontal dimension of the semiconductor substrate110are 20 μm, and the thickness of the surface layer region portion512of the separation region505is 2 μm.

In this simulation, in the configuration (hereinafter referred to as “present configuration”) illustrated inFIG.24A, the configuration illustrated inFIG.24Bwas a comparison target, and a simple calculation was performed on the change in the capacitance between wiring substrates in a case where the dimension of each of a recess portion depth A1, which is the depth of the recess portion503with respect to the back surface110aof the semiconductor substrate110, and a recess portion width A2, which is the width of the recess portion503, was changed. In the present configuration, the semiconductor substrate110is a silicon substrate, and the separation region505includes SiO2.

As illustrated inFIG.24B, the configuration of the comparison target is a configuration in which the recess portion503is not formed in the present configuration. That is, the configuration of the comparison target is a configuration in which the separation region505is formed as a single film having a film thickness of 2 μm on the back surface110aof the semiconductor substrate110.

FIG.25illustrates a result of this simulation. In the table illustrated inFIG.25, the case A in which both the recess portion depth A1and the recess portion width A2are 0 μm is the configuration of the comparison target. In the cases B to E, the amount of decrease in the capacitance between wiring substrates with respect to the case A in a case where the values of the recess portion depth A1and the recess portion width A2in the present configuration are changed is indicated by a difference (%).

From the results of this simulation, it can be seen that the capacitance between wiring substrates is reduced by positioning the recess portion503below the rewiring501. Furthermore, it can be seen that the capacitance between wiring substrates decreases as the values of the recess portion depth A1and the recess portion width A2increase. In particular, it can be seen that the capacitance between wiring substrates can be effectively reduced by increasing the value of the recess portion width A2. Accordingly, it can be said that it is preferable to make the width of the recess portion503(recess portion width A2) larger than the width of the rewiring501in order to obtain the effect of reducing the capacitance between wiring substrates.

Therefore, regarding the relationship between the rewiring501and the recess portion503, it is preferable that 50% or more of the formation region of the rewiring501overlaps the recess portion503in plan view. Furthermore, a configuration in which 100% of the formation region of the rewiring501overlaps the recess portion503in plan view is more preferable. Furthermore, it is more preferable that 100% of the formation region of the rewiring501overlaps the recess portion503in plan view, the formation region of the recess portion503is wider than the formation region of the rewiring501, and the formation region of the recess portion503protrudes from the formation region of the rewiring501.

A modification of the semiconductor apparatus10A according to the seventh embodiment of the present disclosure will be described. As illustrated inFIG.26A, in the configuration of Modification1, the depth (recess portion depth) of the recess portion503of the semiconductor substrate110differs depending on the location. That is, a plurality of types of recess portions503having different depths is formed as the recess portion503.

In the example illustrated inFIG.26A, two types of recess portions503, that is, a first recess portion503A having a relatively shallow depth and a second recess portion503B having a relatively deep depth are formed. The first recess portion503A has a recess portion depth of a first depth B1, and the second recess portion503B has a recess portion depth of a second depth B2that is deeper than the first depth B1.

According to such a configuration, the depth of the recess portion503can be changed according to the use, function, and the like of the rewiring501located above the recess portion503. For example, the recess portion depth can be made relatively deep for the recess portion503formed below the rewiring501for signal transmission for which relatively high signal transmission performance is required, and the recess portion depth can be made relatively shallow for the recess portion503formed below the rewiring501used for power supply wiring that does not particularly require high signal transmission performance. As a result, it is possible to effectively reduce the capacitance between wiring substrates with respect to the rewiring501for improving the signal transmission performance while maintaining the mechanical strength of the semiconductor substrate110. Note that, from the viewpoint of securing the strength of the semiconductor substrate110, the recess portion depth of the recess portion503is preferably set such that a thickness of at least 2 μm is secured for a portion forming the bottom portion of the recess portion503on the front surface side of the semiconductor substrate110.

Furthermore, as illustrated inFIG.26B, in the configuration of Modification2, the height of the wall portion110bof the semiconductor substrate110differs depending on the location. Specifically, in the semiconductor substrate110, a height H1of a wall portion110bX located below the rewiring501is lower than a height H2of a wall portion110bY located in a region other than the formation region of the rewiring501. Note that the height of the wall portion110bis the height of the recess portion503with respect to the bottom surface503b.

According to such a configuration, the distance between the rewiring501and the semiconductor substrate110can be increased, and the formation region of the separation region505can be widened by the decrease in the wall portion110b. As a result, the capacitance between wiring substrates can be effectively reduced.

A semiconductor apparatus10B of an eighth embodiment of the present disclosure is different from the semiconductor apparatus10A of the seventh embodiment mainly in that the through via520is provided.

FIG.27is a cross-sectional view representing a configuration example of the semiconductor apparatus according to the eighth embodiment of the present disclosure. As illustrated inFIG.27, the semiconductor apparatus10B according to the present embodiment includes a semiconductor substrate110in which a semiconductor element521and a front surface side wiring522connected to the semiconductor element521are arranged on a front surface110cside, a rewiring501arranged on a back surface110aside of the semiconductor substrate110, and a separation region505arranged between the semiconductor substrate110and the rewiring501. The front surface side wiring522is arranged in a wiring layer523as a wiring region formed on the back surface110aside of the semiconductor substrate110.

Then, the semiconductor apparatus10B includes: a through electrode525as a through wiring that is arranged in a through hole formed in the semiconductor substrate110and connects the front surface side wiring522and the rewiring501; and a liner film526that includes an insulating material, covers at least a part of the through electrode525, and is interposed between the through electrode525and the separation region505. As described above, the semiconductor apparatus10B according to the present embodiment has the wiring layer523formed on the front surface side of the semiconductor substrate110, the rewiring501formed on the back surface side of the semiconductor substrate110, and the through electrode525that connects the wiring layer523on the front surface side and the rewiring501on the back surface side.

In the present embodiment, the through electrode525is formed from the front surface110cside with respect to the semiconductor substrate110, that is, from the wiring layer523side. As a result, the semiconductor apparatus10B has a so-called via middle structure with respect to the through via520.

The type of the semiconductor element521provided on the front surface side of the semiconductor substrate110is not limited. The semiconductor element521is, for example, a circuit element that performs signal processing, a photoelectric conversion element such as a memory or an image sensor, or the like.

The wiring layer523includes an insulating film524and a front surface side wiring522that transmits a signal of an element included in the above-described processing circuit or the like. The wiring layer523is a layer having a stacked structure including a plurality of522stacked with an insulating film524interposed therebetween. The insulating film524is, for example, a SiO2film, a SiN film, a SiOC film, a SiCN film, a Low-k film, or the like. The front surface side wiring522includes a metal material such as Cu or Ti similarly to the rewiring501. Note that the wiring layer523is not limited to a stacked wiring layer, and may be a wiring layer having a single-layer structure.

The through electrode525is a wiring portion formed in a columnar shape with the thickness direction of the semiconductor substrate110as a longitudinal direction. The through electrode525is provided in a state of penetrating through a through hole110dformed in the semiconductor substrate110. One end side of the through electrode525, which is the front surface110cside of the semiconductor substrate110, protrudes from the front surface110cand is electrically connected to the front surface side wiring522. In the through electrode525, the other end side which is the back surface110aside of the semiconductor substrate110is located on substantially the same horizontal plane as the back surface110a. The through electrode525includes a similar material to that of the front surface side wiring522. However, the through electrode525may include a material different from that of the front surface side wiring522.

In the example illustrated inFIG.27, in the semiconductor substrate110, a through hole110dfor arranging the through electrode525is formed at a formation portion of the recess portion503. That is, the through hole110dopens facing the front surface110cof the semiconductor substrate110, opens facing the bottom surface503bof the recess portion503, and penetrates a bottom portion110eof the recess portion503forming the bottom surface503b. Accordingly, the through electrode525is formed in a manner of protruding from the bottom surface503binto the recess portion503. Therefore, the recess portion inner region portion511of the separation region505exists in the periphery of the through electrode525via the liner film526. Note that, in the semiconductor substrate110, the through hole110dthrough which the through electrode525passes may be formed in a portion other than the formation portion of the recess portion503.

The liner film526includes, for example, an insulating film such as a SiO2film. The liner film526covers substantially the entire portion of the through electrode525other than the portion protruding from the front surface110cof the semiconductor substrate110. The liner film526has a side surface portion526acovering the outer circumferential side surface of the through electrode525and an end surface portion526bcovering the end surface of the through electrode525on the rewiring501side.

Furthermore, in the semiconductor apparatus10B of the present embodiment, as similar to the semiconductor apparatus10A of the seventh embodiment, the separation region505that fills the recess portion503of the semiconductor substrate110and covers the wall portion110bis formed, the rewiring501is formed on the separation region505, and the connection terminal182and the protective film515are formed. In the present embodiment, in the rewiring501electrically connected to the through electrode525, a wiring connection portion501athat penetrates a portion of the separation region505on the front surface505aside and the end surface portion526bof the liner film526and is connected to the end surface portion of the through electrode525is formed.

Furthermore, in the present embodiment, with respect to the depth of the recess portion503, it is preferable that the depth is set such that a thickness of at least 2 μm is secured for the bottom portion110eof the semiconductor substrate110. This is based on the viewpoint of securing the strength of the semiconductor substrate110and the viewpoint of avoiding the characteristic change of the semiconductor element521due to the influence of the stress accompanying the deformation of the semiconductor substrate110.

[Method for manufacturing semiconductor apparatus]

FIGS.28and29are diagrams illustrating an example of a method for manufacturing the semiconductor apparatus10B according to the eighth embodiment of the present disclosure. In this example, as a process of forming the through via520, a via middle method which is an existing technology is used.

First, as illustrated inFIG.28A, the through electrode525and the wiring layer523are formed on a semiconductor substrate110X to be the semiconductor substrate110. That is, after the semiconductor element521is formed on the front surface110cside of the semiconductor substrate110X, the via hole110fis formed on the semiconductor substrate110X by etching or the like from the front surface110cside, and the through electrode525is formed after the liner film526is formed in the via hole110f. Thereafter, the wiring layer523is formed on the front surface110cside of the semiconductor substrate110X so that the front surface side wiring522is connected to the through electrode525.

Next, as illustrated inFIG.28B, the semiconductor substrate110X is ground from a back surface110gside so that the through electrode525is not exposed, and thereby, the semiconductor substrate110X is thinned. Thereafter, the semiconductor substrate110X is further thinned by dry etching or wet etching so as to obtain a selection ratio with respect to the liner film526. As a result, a structure in which the end portion of the through electrode525covered with the liner film526is exposed from the back surface110aof the semiconductor substrate110is obtained.

In this step, from the viewpoint of securing the strength of the semiconductor substrate110, it is preferable to thin the semiconductor substrate110X so that the thickness of the semiconductor substrate110is about 10 to 300 μm. Furthermore, the protrusion amount of the through electrode525from the back surface110aof the semiconductor substrate110is preferably about 0.3 to 10 μm so as not to hinder the next step.

Next, as illustrated inFIG.28C, a step of forming the recess portion503on the back surface110aside of the semiconductor substrate110by photolithography and dry etching is performed. Here, by etching the semiconductor substrate110so as to obtain a selection ratio with the liner film526of the through electrode525, the recess portion503can be formed in the periphery of the through electrode525without exposing the through electrode525.

Next, as illustrated inFIG.28D, a step of forming the separation region505is performed similarly to the case of the seventh embodiment.

Subsequently, as illustrated inFIG.29A, an opening527for connecting the rewiring501is formed above the through electrode525by photolithography and dry etching. The opening527is formed with respect to the separation region505and the liner film526located above the through electrode525from the front surface505aside of the separation region505. The opening527is formed within the range of the end surface of the through electrode525in plan view.

Next, as illustrated inFIG.29B, a step of forming the rewiring501on the front surface505aof the separation region505is performed in a similar manner to the seventh embodiment. Here, the rewiring501(wiring connection portion501a) is also formed in the opening527formed on the through electrode525, and conduction between the through electrode525and the rewiring501is achieved.

Then, as illustrated inFIG.29C, the protective film515and the connection terminal182are formed similarly to the case of the seventh embodiment. The semiconductor apparatus10B is manufactured by the above method.

According to the semiconductor apparatus10B of the present embodiment as described above, in the configuration including the through electrode525that connects the front surface side wiring522on the front surface110cside of the semiconductor substrate110and the rewiring501on the back surface110aside, it is possible to obtain the effect of reducing the capacitance between wiring substrates by arranging the separation region505in the recess portion503and on the back surface110aof the semiconductor substrate110. Furthermore, in the configuration in which the semiconductor element521is formed on the front surface110cside of the semiconductor substrate110, the effect of reducing the capacitance between wiring substrates can be obtained without deteriorating the characteristics of the semiconductor element521. Furthermore, it is not necessary to consider the density difference of the through vias520when the separation region505is formed.

Furthermore, in the semiconductor apparatus10B of the present embodiment, the recess portion503of the semiconductor substrate110is formed in the periphery of the through electrode525. That is, the through via520is formed in the recess portion503. According to such a configuration, not only the parasitic capacitance with the rewiring501but also the parasitic capacitance between the through electrode525and the semiconductor substrate110can be reduced.

A semiconductor apparatus10C of a ninth embodiment of the present disclosure is different from the semiconductor apparatus10B of the eighth embodiment in the configuration of the through via520.

FIG.30is a cross-sectional view representing a configuration example of the semiconductor apparatus according to the ninth embodiment of the present disclosure. As illustrated inFIG.27, in the semiconductor apparatus10C according to the present embodiment, a through electrode535constituting the through via520is formed from the back surface110aside of the semiconductor substrate110. Furthermore, the through electrode535includes the same material as that of the rewiring501. As described above, the semiconductor apparatus10C has a so-called via last structure with respect to the through via520.

Furthermore, the through via520according to the present embodiment does not have the liner film526according to the eighth embodiment, and the through electrode535is directly covered with the recess portion inner region portion511of the separation region505in the recess portion503. In other words, the liner film526includes the same material as that of the separation region505.

FIG.31illustrates a layout of each component in the semiconductor apparatus10C of the present embodiment in plan view. Note that, inFIG.31, illustration of the protective film515is omitted, and a formation portion of the recess portion503is illustrated as a thin black portion for convenience. Furthermore, a two-dot chain line Cl indicates a boundary between the scribe region507and the chip region508.

As illustrated inFIG.31, the through electrode535and the connection terminal182are connected by the rewiring501. Depending on the positional relationship between the through electrode535and the connection terminal182, the shape of the rewiring501connecting them is appropriately different. Furthermore, on the lower side of the rewiring501and the connection terminal182, a recess portion503is formed in a range larger than the width or outer diameter thereof. Furthermore, the through electrode535is formed in the recess portion503, and the periphery of the through electrode535is surrounded by the separation region505(seeFIG.30).

In the example illustrated inFIG.31, in plan view, the formation range of the recess portion503protrudes from the formation ranges of the connection terminal182and the rewiring501in a shape that borders the outer shapes of the connection terminal182and the rewiring501. Note that, in the example illustrated inFIG.31, regarding a wiring connection structure540of a combination of the connection terminal182, the through electrode535, and the rewiring501for connecting the connection terminal182and the through electrode535, the recess portion503is formed for all the wiring connection structures540, but the recess portion503may be formed for some of the wiring connection structures540.

[Method for Manufacturing Semiconductor Apparatus]

FIGS.32and33are diagrams illustrating an example of a method for manufacturing the semiconductor apparatus10C according to the ninth embodiment of the present disclosure.

First, as illustrated inFIG.32A, the semiconductor element521and the wiring layer523are formed on a semiconductor substrate110X to be the semiconductor substrate110. Thereafter, the semiconductor substrate110X is thinned by grinding, dry etching, or wet etching from the back surface110gside. Here, from the viewpoint of securing the strength of the semiconductor substrate110, the semiconductor substrate110preferably has a thickness of about 10 to 300 μm.

Next, as illustrated inFIG.32B, a step of forming a first recess portion531on the back surface110aside of the semiconductor substrate110by photolithography and dry etching is performed. The first recess portion531is formed at a predetermined depth at a formation portion of the through electrode535so as to partially cut off the semiconductor substrate110in the thickness direction. For example, the first recess portion531is formed with an inner diameter larger than the outer shape of the through electrode535so as to have a circular shape in plan view.

Next, as illustrated inFIG.32C, a step of forming the recess portion503on the back surface110aside of the semiconductor substrate110by photolithography and dry etching is performed. Here, the recess portion503is formed such that the formation portion of the first recess portion531is included in the formation range of the recess portion503.

In the step of forming the recess portion503, the processing amount of the semiconductor substrate110, that is, the depth of the recess portion503is adjusted such that the formation portion of the first recess portion531penetrates the semiconductor substrate110. With respect to the depth of the recess portion503, as described above, it is preferable that the depth is set such that a thickness of at least 2 μm is secured for the bottom portion110eof the semiconductor substrate110. Through this step, a through hole110hfor exposing the insulating film524of the wiring layer523is formed at a position corresponding to the formation portion of the first recess portion531in the bottom portion110eof the semiconductor substrate110.

Subsequently, as illustrated inFIG.33A, in a similar manner to that in the seventh embodiment, after the separation region505is formed, a hole portion532for forming the through electrode535is formed. Here, the separation region505is also formed in the through hole110h.

The hole portion532is formed at a position corresponding to a formation portion of the through hole110h. The hole portion532penetrates the separation region505and is formed as a portion obtained by removing a portion of the insulating film524on the semiconductor substrate110side. The hole portion532is formed such that the portion of the separation region505remains on the inner circumferential side of the through hole110h. As a method of processing the hole portion532, for example, dry etching can be adopted. Furthermore, in a case where a photosensitive material is used as the material of the separation region505and the material of the insulating film524, photolithography can be selected as processing of these materials.

Next, as illustrated inFIG.33B, a step of forming the rewiring501on the front surface505aof the separation region505is performed in a similar manner to the seventh embodiment. Here, the through electrode535is formed in the hole portion532, and conduction between the front surface side wiring522and the rewiring501is achieved.

As described above, in the present embodiment, the back surface side wiring arrangement step of arranging the rewiring501on the back surface110aside of the semiconductor substrate110and the through wiring arrangement step of arranging the through electrode535that connect the front surface side wiring522and the rewiring501to each other are simultaneously performed (as one step).

Then, as illustrated inFIG.33C, the protective film515and the connection terminal182are formed similarly to the case of the seventh embodiment. The semiconductor apparatus10C is manufactured by the above method.

According to the semiconductor apparatus10C of the present embodiment as described above, effects similar to those of the semiconductor apparatus10B according to the eighth embodiment can be obtained, and the configuration of the through via520can be simplified as compared with the semiconductor apparatus10B. This makes it possible to reduce the number of steps in the manufacturing process.

A semiconductor apparatus10D of a tenth embodiment of the present disclosure is different from the semiconductor apparatus10C of the ninth embodiment in a formation mode of the recess portion503in plan view.

FIG.34illustrates a layout of each component in the semiconductor apparatus10D of the present embodiment in plan view. Note that, inFIG.34, as similar toFIG.31, illustration of the protective film515is omitted, and a formation portion of the recess portion503is illustrated as a thin black portion.

As illustrated inFIG.34, in the semiconductor apparatus10D of the present embodiment, the recess portion503is formed so as to overlap the plurality of rewirings501in plan view. In the semiconductor apparatus10D, a plurality of wiring connection structures540including the rewiring501is arranged in one recess portion503.

In the example illustrated inFIG.34, as the recess portion503, a recess portion503C including three wiring connection structures540in a rectangular formation range in plan view and a recess portion503D including two wiring connection structures540and a part of one wiring connection structure540in a rectangular formation range in plan view are formed.

According to the semiconductor apparatus10D of the present embodiment, it is possible to obtain similar effects to those of the semiconductor apparatus10B according to the ninth embodiment, and it is possible to alleviate the restriction on the design of the recess portion503when the patterns related to the wiring connection structure540are densely arranged. As a result, a configuration advantageous for high integration can be obtained.

A semiconductor apparatus10E of an eleventh embodiment of the present disclosure is different from the semiconductor apparatus10C of the ninth embodiment in a formation mode of the recess portion503in plan view.

FIG.35illustrates a layout of each component in the semiconductor apparatus10E of the present embodiment in plan view. Note that, inFIG.35, as similar toFIG.31, illustration of the protective film515is omitted, and a formation portion of the recess portion503is illustrated as a thin black portion.

As illustrated inFIG.35, in the semiconductor apparatus10E of the present embodiment, the recess portion503is formed so as to form a polygonal or circular periodic structure in plan view. That is, the semiconductor apparatus10E includes a large number of recess portions503formed in a periodic arrangement.

In the example illustrated inFIG.35, the recess portion503is formed by arranging a honeycomb structure which is a large number of hexagonal periodic structures as periodic arrangement. That is, in the semiconductor apparatus10E, a large number of recess portions503having a hexagonal shape in plan view are periodically arranged and formed in the semiconductor substrate110.

Note that, in the example illustrated inFIG.35, the recess portions503are periodically arranged and formed over the entire chip region508, but the recess portions503may be formed in a partial region of the chip region508.

Furthermore, in the example illustrated inFIG.35, a part of the wiring connection structure540is formed in a region other than the formation region of the recess portion503, but from the viewpoint of reducing the capacitance between wiring substrates, the through electrode535is preferably formed in the formation region of the recess portion503as illustrated inFIG.35. However, the through electrode535may also be formed in a region other than the formation region of the recess portion503.

According to the semiconductor apparatus10E of the present embodiment, similar effects to those of the semiconductor apparatus10B according to the ninth embodiment can be obtained, and the following effects can be obtained. That is, according to the formation mode of the recess portion503according to the present embodiment, stress can be dispersed, the strength of the semiconductor substrate110can be maintained and secured, and the recess portion503can be formed relatively deep. As a result, the capacitance between wiring substrates can be effectively reduced, and it is possible to achieve both weight reduction of the chip as the semiconductor apparatus10E and maintenance and securing of mechanical strength.

Regarding the weight reduction of the chip, for example, since the specific gravity of the acrylic resin is about ½ with respect to the silicon semiconductor substrate110, by removing a volume portion of about 60% of the volume of the semiconductor substrate110to form the recess portion503, the weight reduction of about 30% of the semiconductor substrate110can be achieved. Furthermore, by adopting a periodic structure with respect to the arrangement of the recess portions503, it is possible to make it difficult to be affected by the difference in density when the resin material is applied to form the separation region505. This makes it possible to reduce variations in the coating film thickness of the material of the separation region505. As a result, a uniform reduction effect of the capacitance between wiring substrates can be obtained.

A modification of the semiconductor apparatus10E according to the eleventh embodiment of the present disclosure will be described. As the periodic structure of the recess portion503, various shapes such as a polygonal shape such as a quadrangular shape and a pentagonal shape, a circular shape, and an elliptical shape can be adopted.

For example, as in the configuration of Modification1illustrated inFIG.36, the recess portion503may be formed by arrangement of a large number of triangular periodic structures as periodic arrangement. As described above, a large number of recess portions503having a triangular shape in plan view may be periodically arranged and formed in the semiconductor substrate110.

Furthermore, as in the configuration of Modification2illustrated inFIG.37, the recess portion503may be formed by arrangement of a large number of circular periodic structures as periodic arrangement. As described above, a large number of recess portions503having a circular shape in plan view may be periodically arranged and formed in the semiconductor substrate110.

Also with the configuration of these modifications, the capacitance between wiring substrates can be effectively reduced, and it is possible to achieve both weight reduction of the chip and maintenance and securing of mechanical strength.

12. Application Example to Camera

The technology (the present technology) according to the present disclosure can be applied to various products. For example, the present technology may be achieved as an imaging element mounted on an imaging apparatus such as a camera.

FIG.38is a block diagram illustrating a schematic configuration example of a camera which is an example of an imaging apparatus to which the present technology can be applied. A camera1000in the drawing includes a lens1001, an imaging element1002, an imaging control unit1003, a lens drive unit1004, an image processing unit1005, an operation input unit1006, a frame memory1007, a display unit1008, and a recording unit1009.

The lens1001is an imaging lens of the camera1000. The lens1001focuses light from a subject and causes the light to enter the imaging element1002as described later to form an image of a subject.

The imaging element1002is a semiconductor element that images light from the subject focused by the lens1001. The imaging element1002generates an analog image signal corresponding to the emitted light, converts the analog image signal into a digital image signal, and outputs the digital image signal.

The imaging control unit1003controls imaging in the imaging element1002. The imaging control unit1003controls the imaging element1002by generating a control signal and outputting the control signal to the imaging element1002. Furthermore, the imaging control unit1003can perform autofocus in the camera1000on the basis of an image signal output from the imaging element1002. Here, autofocus is a system that detects the focal position of the lens1001and automatically adjusts the focal position. As the autofocus, a method (image plane phase difference autofocus) of detecting the focal position by detecting the image plane phase difference using the phase difference pixel arranged in the imaging element1002can be used. Furthermore, a method (contrast autofocus) of detecting a position where the contrast of the image is the highest as a focal position can also be applied. The imaging control unit1003adjusts the position of the lens1001via the lens drive unit1004on the basis of the detected focal position, and performs autofocus. Note that the imaging control unit1003can include, for example, a digital signal processor (DSP) equipped with firmware.

The lens drive unit1004drives the lens1001under the control of the imaging control unit1003. The lens drive unit1004can drive the lens1001by changing the position of the lens1001using a built-in motor.

The image processing unit1005processes an image signal generated by the imaging element1002. This processing corresponds to, for example, demosaic for generating an image signal of an insufficient color among image signals corresponding to red, green, and blue for each pixel, noise reduction for removing noise of the image signal, encoding of the image signal, and the like. The image processing unit1005can be configured by, for example, a microcomputer equipped with firmware.

The operation input unit1006receives an operation input from a user of the camera1000. For example, a push button or a touch panel can be used as the operation input unit1006. The operation input received by the operation input unit1006is transmitted to the imaging control unit1003and the image processing unit1005. Thereafter, processing according to the operation input, for example, processing such as imaging of the subject is started.

The frame memory1007is a memory that stores a frame that is an image signal for one screen. The frame memory1007is controlled by the image processing unit1005and holds frames in the process of image processing.

The display unit1008displays the image processed by the image processing unit1005. For example, a liquid crystal panel can be used as the display unit1008.

The recording unit1009records the image processed by the image processing unit1005. For example, a memory card or a hard disk can be used as the recording unit1009.

The camera to which the present disclosure can be applied has been described above. The present technology can be applied to the imaging element1002among the configurations described above. Specifically, the imaging apparatus10described inFIG.1can be applied to the imaging element1002. By applying the imaging apparatus10to the imaging element1002, a signal delay time can be shortened, and high-speed imaging can be performed.

Note that the configuration of the imaging apparatus10of the fourth embodiment can be combined with other embodiments. Specifically, the separation region153inFIG.11can be applied to the semiconductor substrate110inFIG.8.

Furthermore, the configuration of the imaging apparatus10of the fifth embodiment can be combined with other embodiments. Specifically, the separation region154inFIG.15can be applied to the semiconductor substrate110inFIG.6.

Lastly, the description of each of the above-described embodiments is an example of the present disclosure, and the present disclosure is not limited to the above-described embodiments. For this reason, it is of course that various modifications can be made according to the design and the like, other than the above-described embodiments, as long as the modifications do not depart from the technical idea according to the present disclosure. The technology according to the present disclosure can also be applied to, for example, an interposer used as a relay component in a package structure of an IC component.

Furthermore, the effects described in the present specification are merely examples and are not intended to be limiting. Furthermore, other effects may be provided. Furthermore, the configurations of the above-described embodiments and the configurations of the modifications can be appropriately combined.

Furthermore, the drawings in the above-described embodiments are schematic, and the dimensional ratios and the like of the respective parts do not necessarily match actual ones. Furthermore, it is of course that dimensional relationships and ratios are different between drawings.

Note that, the present technology can also adopt the following configuration.

(1) A semiconductor apparatus including:

a semiconductor substrate in which a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side;

a back surface side wiring arranged on a back surface side of the semiconductor substrate; and

a separation region arranged between the semiconductor substrate and the back surface side wiring.

(2) The semiconductor apparatus according to (1), further including a through wiring arranged in a through hole formed in the semiconductor substrate and connecting the front surface side wiring and the back surface side wiring.

(3) The semiconductor apparatus according to (1), in which the separation region includes a resin.

(4) The semiconductor apparatus according to (3), in which the separation region includes a photosensitive resin.

(5) The semiconductor apparatus according to (1), in which the separation region includes an inorganic material.

(6) The semiconductor apparatus according to any one of (1) to (5), in which the separation region is formed to have a thickness of equal to or greater than 5 μm.

(7) The semiconductor apparatus according to any one of (1) to (5), in which the separation region is arranged in a recess portion formed on a back surface side of the semiconductor substrate.

(8) The semiconductor apparatus according to (7), in which the separation region includes a gap.

(9) The semiconductor apparatus according to (7) or (8), in which the back surface side wiring is provided so as to at least partially overlap the recess portion in plan view.

(10) The semiconductor apparatus according to any one of (7) to (9), in which a plurality of types of recess portions having different depths is formed as the recess portion.

(11) The semiconductor apparatus according to any one of (7) to (10), in which the recess portion is formed so as to overlap a plurality of the back surface side wiring in plan view.

(12) The semiconductor apparatus according to any one of (7) to (11), in which the recess portion is formed so as to form a polygonal or circular periodic structure in plan view.

(13) The semiconductor apparatus according to any one of (7) to (12), further including: a through wiring arranged in a through hole formed in the semiconductor substrate and connecting the front surface side wiring and the back surface side wiring; and a liner film including an insulating material, covering at least a part of the through wiring, and interposed between the through wiring and the separation region.

(14) The semiconductor apparatus according to (1), in which the separation region includes a gap.

(15) The semiconductor apparatus according to (14), further including a through wiring arranged in a through hole formed in the semiconductor substrate and connecting the front surface side wiring and the back surface side wiring, in which the separation region includes an in-hole separation region portion covering an inner circumferential surface of the through hole and a back surface side separation region portion formed on a back surface side of the semiconductor substrate, and the gap is formed in the back surface side separation region portion.

(16) The semiconductor apparatus according to (2), in which the separation region is further arranged between the semiconductor substrate and the through wiring.

(17) The semiconductor apparatus according to (2) or (16), in which the separation region is used as a mask in etching for forming the through hole in the semiconductor substrate.

(18) The semiconductor apparatus according to any one of (1) to (8), (16), and (17), further including an insulating film that insulates the back surface side wiring.

(19) The semiconductor apparatus according to any one of (1) to (18), in which the semiconductor element is a photoelectric conversion element that performs photoelectric conversion of incident light.

(20) A method for manufacturing a semiconductor apparatus, the method including:

a separation region arrangement step of arranging a separation region on a back surface side of a semiconductor substrate on which a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side;

a through hole forming step of forming a through hole in the semiconductor substrate;

a back surface side wiring arrangement step of arranging a back surface side wiring on the back surface side of the semiconductor substrate; and

a through wiring arrangement step of arranging a through wiring connecting the front surface side wiring and the back surface side wiring in the through hole that has been formed.

REFERENCE SIGNS LIST