FREQUENCY MULTIPLIER CIRCUITS HAVING CROSS-COUPLED CAPACITORS THEREIN WHICH SUPPORT FREQUENCY MULTIPLICATION

A frequency multiplier includes a capacitor circuit having a plurality of capacitors therein, and is responsive to a differential input signal applied to an inverting input node and a non-inverting input node thereof. A frequency multiplication circuit (FMC) is provided, which has a plurality of transistors therein. The FMC is configured to receive components of the differential input signal passing through the plurality of capacitors, and multiply a frequency of the components of the differential input signal. A plurality of inductor loads are provided, which are connected to an inverting output node and a non-inverting output node of the FMC, and are configured to convert a current signal generated by the FMC into a voltage signal.

REFERENCE TO PRIORITY APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2022-0062315 and 10-2022-0111676, filed May 20, 2022 and Sep. 2, 2022, respectively, in the Korean Intellectual Property Office, the disclosures of which are hereby incorporated herein by reference.

BACKGROUND

The inventive concept relates to integrated circuit devices and, more particularly, to frequency multiplier circuits.

Recently, as the level of demand for high integration, downsizing, and high performance for smartphones and various other types of high-tech electronic devices increases, the significance of a system on chip (SoC) field has increased. Electronic devices may need to use signals having various frequencies in systems to meet the increased integration levels, and still provide high performance. However, it is often difficult to mount, in electronic devices, multiple frequency generators, which support the many signals having different frequencies. Therefore, there is a need for a frequency multiplier that enables a small number of frequency generators to generate various frequencies, including generating a millimeter wave (mm-wave) signal by multiplying a relatively low frequency signal.

SUMMARY

The inventive concept may provide a frequency multiplier having cross-coupled capacitors therein, which support high conversion gain.

According to an aspect of the inventive concept, there is provided a frequency multiplier including: (i) a first transistor having a drain connected to a non-inverting output node, (ii) a second transistor having a drain connected to the drain of the first transistor and the non-inverting output node, (iii) a third transistor having a drain connected to an inverting output node, and a source connected to a source of the first transistor, (iv) a fourth transistor having a drain connected to the drain of the third transistor and the inverting output node, and a source connected to a source of the second transistor, (v) a first capacitor connected between a gate of the first transistor and an inverting input node, (vi) a second capacitor connected between a gate of the second transistor and a non-inverting input node, (vii) a third capacitor connected between a gate of the third transistor and the inverting input node, (viii) and a fourth capacitor connected between a gate of the fourth transistor and the non-inverting input node.

According to another aspect of the inventive concept, there is provided a frequency multiplier including a capacitor circuit having a plurality of capacitors therein, which are configured to receive a differential input signal, and a frequency multiplication circuit having a first transistor, a second transistor, a third transistor, and a fourth transistor therein. This frequency multiplication circuit is configured to multiply a frequency of a signal received from the capacitor circuit, and at least some of the plurality of capacitors are connected to corresponding gates of the first to fourth transistors.

According to another aspect of the inventive concept, there is provided a frequency multiplier having a capacitor circuit therein, which includes a plurality of capacitors connected to an inverting input node or a non-inverting input node, and a frequency multiplication circuit (FMC). The FMC may include a plurality of transistors, which are collectively configured to receive an input signal through the plurality of capacitors, and multiply a frequency of the input signal. A plurality of inductor loads are also provided. These loads, which convert a current signal to a voltage signal, are connected to a corresponding inverting output node and a non-inverting output node.

According to a further aspect of the inventive concept, a frequency multiplier is provided, which includes: (i) a first totem pole arrangement of a first NMOS transistor and a first PMOS transistor having source terminals electrically connected together at a first source node, (ii) a second totem pole arrangement of a second NMOS transistor and a second PMOS transistor having source terminals electrically connected together at a second source node, (iii) a first input terminal capacitively coupled to the first source node, (iv) a second input terminal capacitively coupled to the second source node, (v) a first load having a net inductive reactance, electrically connected to drain terminals of the first and second NMOS transistors, and (vi) a second load having a net inductive reactance, electrically connected to drain terminals of the first and second PMOS transistors. The first and second input terminals of the frequency multiplier may be responsive to true and complementary signals of a differential input signal.

The frequency multiplier may also include (i) a first capacitor having a first terminal electrically coupled to the second input terminal and a second terminal electrically connected to a gate terminal of the first NMOS transistor, (ii) a second capacitor having a first terminal electrically coupled to the first input terminal and a second terminal electrically connected to a gate terminal of the second NMOS transistor, (iii) a third capacitor having a first terminal electrically coupled to the second input terminal and a second terminal electrically connected to a gate terminal of the first PMOS transistor, (iv) a fourth capacitor having a first terminal electrically coupled to the first input terminal and a second terminal electrically connected to a gate terminal of the second PMOS transistor, (v) a fifth capacitor having a first terminal electrically coupled to a first input terminal of the frequency multiplier and a second terminal electrically connected to the first source node, and (vi) a sixth capacitor having a first terminal electrically coupled to a second input terminal of the frequency multiplier and a second terminal electrically connected to the second source node. In some embodiments of the inventive concept, the first, second, third and fourth capacitors may have an equivalent capacitance, and the fifth and sixth capacitors may have an equivalent capacitance, which is greater than a capacitance of the first, second, third and fourth capacitors. In further embodiments, the first capacitor may have a capacitance that is at least ten (10) times greater than a gate-to-source capacitance of the first NMOS transistor.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG.1is a block diagram illustrating a frequency multiplier according to an embodiment. In general, an oscillator, which generates a frequency signal in a millimeter wave (mm-wave) band, may not be easily designed due to high phase noise, large signal loss associated with signal distribution, and the like. Therefore, even when the oscillator outputs a signal having a relatively low frequency, a frequency multiplier for multiplying a frequency may be needed to generate a signal having a high frequency.

Referring toFIG.1, a frequency multiplier10according to an embodiment may include a capacitor circuit110, a frequency multiplication circuit120, and/or inductor loads131and132. The capacitor circuit110may be a circuit configured to receive a differential input signal. In detail, the capacitor circuit110may be connected to a non-inverting input node and an inverting input node, and may include a plurality of capacitors.

The frequency multiplication circuit120may be a circuit configured to multiply a frequency of a signal received from the capacitor circuit110. The frequency multiplication circuit120may be connected to the capacitor circuit110, and may include a plurality of transistors. The transistors included in the frequency multiplication circuit120may receive a differential input signal from the capacitors included in the capacitor circuit110.

The inductor loads131and132may be circuits for converting a current signal having a multiplied frequency into a voltage signal. The inductor loads131and132may be connected to the frequency multiplication circuit120. As shown, the inductor load131may be connected to a non-inverting output node (Vout+), and the inductor load132may be connected to an inverting output node (Vout−). Details of a detailed circuit configuration of the frequency multiplier10will be described more fully hereinbelow.

FIG.2is a circuit diagram of an example of a frequency multiplier, which may be described with reference toFIG.1. Referring toFIG.2, a frequency multiplier20may include P-channel metal-oxide semiconductor (PMOS) transistors M1and M2and N-channel metal-oxide semiconductor (NMOS) transistors M3and M4. The PMOS transistors M1and M2, and the NMOS transistors M3and M4may be applied with a gate voltage VB via gates thereof, and may be applied with a non-inverted input voltage VIN+and an inverted input voltage VIN−via sources/drains thereof. The PMOS transistor M1and the PMOS transistor M2make a pair and the NMOS transistor M3and the NMOS transistor M4make a pair, and thus, the PMOS transistors M1and M2, and the NMOS transistors M3and M4may operate as switches. For example, during a first half cycle of an input signal having a sine wave shape, the PMOS transistor M1and the NMOS transistor M4may be turned on, and the PMOS transistor M2and the NMOS transistor M3may be turned off, whereas during a second half cycle of the input signal, the opposite operation may be performed. In detail, when an input signal is vin+=cos(w0t) and an inverted input signal is vin−=cos(w0t−π), iD1=A(−vin+−Vth)2and iD2=A(−vin−−Vth)2. Accordingly, a current iDof an output signal may be calculated as follows:

As shown by these expressions, a frequency of the output signal may be two times (i.e., 2 w0) a frequency w0of an input signal. From among harmonics generated from the frequency of the input signal, a frequency to be multiplied may be selected by the frequency multiplier20. In addition, an intensity of a multiplied frequency signal may be smaller than an intensity of the input signal (i.e., a loss of a signal may occur).

In contrast, the frequency multiplier10ofFIG.1according to an embodiment may include cross-coupled capacitors connected to a frequency multiplication circuit, and thus may increase a magnitude and effective transconductance of an effective input signal without additional current consumption, and may have a higher frequency conversion gain with low power, thereby minimizing a loss in an intensity of an output signal. In detail, the frequency multiplier10may have a high frequency conversion gain by including capacitors connected to transistors. For example, each of the capacitors respectively connected between gates of a plurality of transistors and a non-inverting input node or an inverting input node may be referred to as a cross-coupled capacitor. The cross-coupled capacitors may be included in the capacitor circuit110. More details regarding cross-coupling of transistors and capacitors will be described later.

FIG.3Ais a diagram illustrating a circuit of a frequency multiplier, according to an embodiment. Referring toFIG.3A, a frequency multiplier30according to an embodiment may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor CC1, a second capacitor CC2, and a third capacitor CC3, and/or a fourth capacitor CC4, connected as illustrated.

The first capacitor CC1may be connected between a gate of the first transistor M1and an inverting input node. The second capacitor CC2may be connected between a gate of the second transistor M2and a non-inverting input node. The third capacitor CC3may be connected between a gate of the third transistor M3and the inverting input node. The fourth capacitor CC4may be connected between a gate of the fourth transistor M4and the non-inverting input node.

A drain of the first transistor M1, a drain of the second transistor M2, and a non-inverting output node may be connected to one another, a drain of the third transistor M3, a drain of the fourth transistor M4, and an inverting output node may be connected to one another, and a source of the first transistor M1and a source of the third transistor M3may be connected to each other, and a source of the second transistor M2and a source of the fourth transistor M4may be connected to each other. Each of the first transistor M1and the second transistor M2may be an NMOS transistor. In addition, each of the third transistor M3and the fourth transistor M4may be a PMOS transistor.

The first capacitor CC1, the second capacitor CC2, the third capacitor CC3, and the fourth capacitor CC4may have the same capacitance. In addition, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4may have the same gate-source capacitance. Gate-source capacitors connected to a plurality of transistors are illustrated in more detail inFIGS.3B and3Cto be described later.

In addition, each of the first capacitor CC1, the second capacitor CC2, the third capacitor CC3, and the fourth capacitor CC4may have a capacitance that is sufficiently greater than a gate-source capacitance of each of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4. For example, each of the first capacitor CC1, the second capacitor CC2, the third capacitor CC3, and the fourth capacitor CC4may have a capacitance that is at least ten (10) times a gate-source capacitance of each of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4, but is not limited thereto.

FIG.3Bis a diagram illustrating an equivalent circuit of a portion of a frequency multiplier, according to an embodiment. Hereinafter,FIG.3Bwill be described with reference toFIG.3A. In particular,FIG.3Bis a diagram illustrating an equivalent circuit of a portion310including a first transistor M1and a second transistor M2in the frequency multiplier30ofFIG.3A. In detail,FIG.3Bmay be a small signal equivalent model of the portion310ofFIG.3A. Referring toFIG.3B, the first transistor M1may be represented by an equivalent circuit including a gate-source capacitor Cgsand current sources of the first transistor M1, and the second transistor M2may be represented by an equivalent circuit including a gate-source capacitor Cgsand current sources of the second transistor M2.

In the first transistor M1, a current by a fundamental frequency component may be referred to as ifund+, a current by a second-order frequency component may be referred to as isecond+, and in the second transistor M2, a current by a fundamental frequency component may be referred to as ifund−, and a current by a second-order frequency component may be referred to as isecond−. Here, when a capacitance of each of a first capacitor CC1and a second capacitor CC2is sufficiently greater than a capacitance of the gate-source capacitors Cgs(capacitance of each of CC1and CC2»capacitance of Cgs) (e.g., the first capacitor CC1may have a capacitance that is greater than or equal to 10 times a capacitance of the gate-source capacitor Cgsof the first transistor M1, but is not limited thereto). A conversion gain (CG) of the frequency multiplier30according to an embodiment may be calculated as follows.

Here, VAmay denote a magnitude of an input signal, and ZLmay denote an impedance of an inductor load.

In contrast, a conversion gain CGwoCCcalculated with respect to the frequency multiplier20ofFIG.2by the same method as described above may be as follows.

As a result, a conversion gain of the frequency multiplier30according to an embodiment may be four times higher than that of the frequency multiplier20. In addition, the frequency multiplier30does not need additional power consumption for obtaining a high conversion gain described above. The conversion gain of the frequency multiplier30is higher than the conversion gain of the frequency multiplier20because a magnitude of an effective input voltage is doubled by cross-coupled capacitors. In other words, the frequency multiplier30according to an embodiment may use cross-coupled capacitors to increase a magnitude of an effective input voltage, and increase an effective transconductance. In addition, the frequency multiplier30may have a higher conversion gain, compared to current consumption.

FIG.3Cis a diagram illustrating an equivalent circuit of a portion320including a third transistor M3and a fourth transistor M4in the frequency multiplier30ofFIG.3A. In detail,FIG.3Cmay be a small signal equivalent model of the portion320ofFIG.3A. Referring toFIG.3C, the third transistor M3may be represented by an equivalent circuit including a gate-source capacitor Cgsand current sources of the third transistor M3, and the fourth transistor M4may be represented by an equivalent circuit including a gate-source capacitor Cgsand current sources of the fourth transistor M4.

Conversion gains of the third transistor M3and the fourth transistor M4may be calculated by the same method as the first transistor M1and the second transistor M2ofFIG.3B, and as a result, a conversion gain of the frequency multiplier30may be four times higher than that of the frequency multiplier20. In addition, the frequency multiplier30does not need additional power consumption for obtaining a high conversion gain described above. The conversion gain of the frequency multiplier30is higher than the conversion gain of the frequency multiplier20because a magnitude of an effective input voltage is doubled by cross-coupled capacitors. In other words, the frequency multiplier30according to an embodiment may use cross-coupled capacitors to increase a magnitude of an effective input voltage, and increase an effective transconductance. In addition, the frequency multiplier30may have a high conversion gain, compared to current consumption.

FIG.4Ais a diagram illustrating a circuit of a frequency multiplier, according to an embodiment. Referring toFIG.4A, a frequency multiplier40according to an embodiment may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor CC1, a second capacitor CC2, a third capacitor CC3, a fourth capacitor CC4, a fifth capacitor CDC5, and/or a sixth capacitor CDC6.

The first capacitor CC1may be connected between a gate of the first transistor M1and an inverting input node. The second capacitor CC2may be connected between a gate of the second transistor M2and a non-inverting input node. The third capacitor CC3may be connected between a gate of the third transistor M3and the inverting input node. The fourth capacitor CC4may be connected between a gate of the fourth transistor M4and the non-inverting input node.

A drain of the first transistor M1, a drain of the second transistor M2, and a non-inverting output node may be connected to one another, a drain of the third transistor M3, a drain of the fourth transistor M4, and an inverting output node may be connected to one another, a source of the first transistor M1and a source of the third transistor M3may be connected to each other, and a source of the second transistor M2and a source of the fourth transistor M4may be connected to each other. Each of the first transistor M1and the second transistor M2may be an NMOS transistor. In addition, each of the third transistor M3and the fourth transistor M4may be a PMOS transistor.

The fifth capacitor CDC5may be connected between a first node between the source of the first transistor M1and the source of the third transistor M3and the non-inverting input node. The sixth capacitor CDC6may be connected between a second node between the source of the second transistor M2and the source of the fourth transistor M4and the inverting input node. Each of the fifth capacitor CDC5and the sixth capacitor CDC6is a capacitor connected between NMOS and PMOS transistors. A voltage having a DC component may be generated by a connection between NMOS and PMOS transistors, a voltage level of the DC component generated by the connection between the NMOS and the PMOS transistors may be different from a voltage level of a DC component of an input signal, and a current may be generated due to the difference between the voltage levels. Each of the fifth capacitor CDC5and the sixth capacitor CDC6may be a capacitor for preventing a current from being generated due to a difference between voltage levels as described above.

The first capacitor CC1, the second capacitor CC2, the third capacitor CC3, and the fourth capacitor CC4may have the same capacitance. In addition, the fifth capacitor CDC5and the sixth capacitor CDC6may have the same capacitance. The first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4may have the same gate-source capacitance.

In addition, each of the first capacitor CC1, the second capacitor CC2, the third capacitor CC3, the fourth capacitor CC4, the fifth capacitor CDC5, and the sixth capacitor CDC6may have a capacitance that is sufficiently greater than a gate-source capacitance of each of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4. For example, each of the first capacitor CC1, the second capacitor CC2, the third capacitor CC3, and the fourth capacitor CC4may have a capacitance that is greater than or equal to ten (10) times a gate-source capacitance of each of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4, but is not limited thereto. In addition, each of the fifth capacitor CDC5and the sixth capacitor CDC6may have a capacitance that is twice (2×) a capacitance of each of the first capacitor CC1, the second capacitor CC2, the third capacitor CC3, and the fourth capacitor CC4, but is not limited thereto.

FIG.4Bis a diagram illustrating an equivalent circuit of a portion410including a first transistor M1and a second transistor M2in the frequency multiplier40ofFIG.4A. In detail,FIG.4Bmay be a small signal equivalent model of the portion410ofFIG.4A. Referring toFIG.4B, the first transistor M1may be represented by an equivalent circuit including a gate-source capacitor Cgsand current sources of the first transistor M1, and the second transistor M2may be represented by an equivalent circuit including a gate-source capacitor Cgsand current sources of the second transistor M2.

Conversion gains of the first transistor M1and the second transistor M2may be calculated by the same method as the first transistor M1and the second transistor M2ofFIG.3B. Here, a capacitance of each of a fifth capacitor CDC5and a sixth capacitor CDC6needs to be sufficiently greater than a capacitance of a gate-source capacitor Cgs. For example, each of the fifth capacitor CDC5and the sixth capacitor CDC6may have a capacitance that is at least twenty (20) times a capacitance of the gate-source capacitor Cgs, but is not limited thereto. Accordingly, a conversion gain of the frequency multiplier40is four times higher than that of the frequency multiplier20, and the frequency multiplier40does not need additional power consumption for obtaining a high conversion gain described above. The conversion gain of the frequency multiplier40is higher than the conversion gain of the frequency multiplier20because a magnitude of an effective input voltage is doubled by cross-coupled capacitors. In other words, the frequency multiplier40according to an embodiment may use cross-coupled capacitors to increase a magnitude of an effective input voltage, and increase an effective transconductance. In addition, the frequency multiplier40may have a high conversion gain, compared to current consumption.

FIG.4Cis a diagram illustrating an equivalent circuit of a portion of a frequency multiplier, according to an embodiment. Hereinafter,FIG.4Cwill be described with reference toFIGS.4A and4B.FIG.4Cis a diagram illustrating an equivalent circuit of a portion420including a third transistor M3and a fourth transistor M4in the frequency multiplier40ofFIG.4A. In detail,FIG.4Cmay be a small signal equivalent model of the portion420ofFIG.4A. Referring toFIG.4C, the third transistor M3may be represented by an equivalent circuit including a gate-source capacitor Cgsand current sources of the third transistor M3, and the fourth transistor M4may be represented by an equivalent circuit including a gate-source capacitor Cgsand current sources of the fourth transistor M4.

Conversion gains of the third transistor M3and the fourth transistor M4may be calculated by the same method as the first transistor M1and the second transistor M2ofFIG.3B. Here, a capacitance of each of a fifth capacitor CDC5and a sixth capacitor CDC6needs to be sufficiently greater than a capacitance of a gate-source capacitor Cgs. For example, each of the fifth capacitor CDC5and the sixth capacitor CDC6may have a capacitance that is greater than or equal to 20 times a capacitance of the gate-source capacitor Cgs, but is not limited thereto. Accordingly, a conversion gain of the frequency multiplier40is four times higher than that of the frequency multiplier20, and the frequency multiplier40does not need additional power consumption for obtaining a high conversion gain described above. The conversion gain of the frequency multiplier40is higher than the conversion gain of the frequency multiplier20because a magnitude of an effective input voltage is doubled by cross-coupled capacitors. In other words, the frequency multiplier40according to an embodiment may use cross-coupled capacitors to increase a magnitude of an effective input voltage, and increase an effective transconductance. In addition, the frequency multiplier40may have a high conversion gain, compared to current consumption.

FIG.5Ais a diagram illustrating a circuit of a frequency multiplier, according to an embodiment. Referring toFIG.5A, a frequency multiplier50according to an embodiment may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor CC1, a second capacitor CC2, a third capacitor CC3, a fourth capacitor CC4, a first inductor load ZL1, and/or a second inductor load ZL2.

The first capacitor CC1may be connected between a gate of the first transistor M1and an inverting input node. The second capacitor CC2may be connected between a gate of the second transistor M2and a non-inverting input node. The third capacitor CC3may be connected between a gate of the third transistor M3and the inverting input node. The fourth capacitor CC4may be connected between a gate of the fourth transistor M4and the non-inverting input node.

A drain of the first transistor M1, a drain of the second transistor M2, and a non-inverting output node may be connected to one another, a drain of the third transistor M3, a drain of the fourth transistor M4, and an inverting output node may be connected to one another, and a source of the first transistor M1and a source of the third transistor M3may be connected to each other, and a source of the second transistor M2and a source of the fourth transistor M4may be connected to each other. Each of the first transistor M1and the second transistor M2may be an NMOS transistor. In addition, each of the third transistor M3and the fourth transistor M4may be a PMOS transistor.

The first capacitor CC1, the second capacitor CC2, the third capacitor CC3, and the fourth capacitor CC4may have the same capacitance. In addition, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4may have the same gate-source capacitance. In addition, each of the first capacitor CC1, the second capacitor CC2, the third capacitor CC3, and the fourth capacitor CC4may have a capacitance that is sufficiently greater than a gate-source capacitance of each of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4. For example, each of the first capacitor CC1, the second capacitor CC2, the third capacitor CC3, and the fourth capacitor CC4may have a capacitance that is ten (10) times greater than a gate-source capacitance of each of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4, but is not limited thereto.

The first inductor load ZL1may be connected to the non-inverting output node, and the second inductor load ZL2may be connected to the inverting output node. Each of the first inductor load ZL1and the second inductor load ZL2may include an inductor, a capacitor, and a resistor, and the capacitor and the resistor may be a parasitic capacitor of the inductor and a parasitic resistor of the inductor, respectively. In detail, the first inductor load ZL1may include a first inductor L1, a first parasitic capacitor CP1, and a first parasitic resistor RP1. In addition, the second inductor load ZL2may include a second inductor L2, a second parasitic capacitor CP2, and a second parasitic resistor RP2.

The first inductor load ZL1and the second inductor load ZL2may be circuits for converting a current signal having a multiplied frequency into a voltage signal. Accordingly, a resonant frequency of the first inductor L1and the first parasitic capacitor CP1of the first inductor load ZL1may be twice a frequency of an input signal. In addition, a resonant frequency of the second inductor L2and the second parasitic capacitor CP2of the second inductor load ZL2may be twice the frequency of the input signal.

FIG.5Bis a diagram illustrating an equivalent circuit of a portion510including a first transistor M1and a second transistor M2in the frequency multiplier50ofFIG.5A. In detail,FIG.5Bmay be a small signal equivalent model of the portion510ofFIG.5A. Referring toFIG.5B, the first transistor M1may be represented by an equivalent circuit including a gate-source capacitor Cgsand current sources of the first transistor M1, and the second transistor M2may be represented by an equivalent circuit including a gate-source capacitor Cgsand current sources of the second transistor M2.

Conversion gains of the first transistor M1and the second transistor M2may be calculated by the same method as the first transistor M1and the second transistor M2ofFIG.3B. Here, an inductor load corresponding to ZLdescribed with reference toFIG.3Bis a first inductor load ZL1. Accordingly, a conversion gain of the frequency multiplier50is four times higher than that of the frequency multiplier20, and the frequency multiplier50does not need additional power consumption for obtaining a high conversion gain described above. The conversion gain of the frequency multiplier50is higher than the conversion gain of the frequency multiplier20because a magnitude of an effective input voltage is doubled by cross-coupled capacitors. In other words, the frequency multiplier50according to an embodiment may use cross-coupled capacitors to increase a magnitude of an effective input voltage, and may increase an effective transconductance. In addition, the frequency multiplier50may have a high conversion gain, compared to current consumption.

FIG.5Cis a diagram illustrating an equivalent circuit of a portion520including a third transistor M3and a fourth transistor M4in the frequency multiplier50ofFIG.5A. In detail,FIG.5Cmay be a small signal equivalent model of the portion520ofFIG.5A. Referring toFIG.5C, the third transistor M3may be represented by an equivalent circuit including a gate-source capacitor Cgsand current sources of the third transistor M3, and the fourth transistor M4may be represented by an equivalent circuit including a gate-source capacitor Cgsand current sources of the fourth transistor M4.

Conversion gains of the third transistor M3and the fourth transistor M4may be calculated by the same method as the first transistor M1and the second transistor M2ofFIG.3B. Here, an inductor load corresponding to ZLofFIG.3Bis a second inductor load ZL2. Accordingly, a conversion gain of the frequency multiplier50is four times higher than that of the frequency multiplier20, and the frequency multiplier50does not need additional power consumption for obtaining a high conversion gain described above. The conversion gain of the frequency multiplier50is higher than the conversion gain of the frequency multiplier20because a magnitude of an effective input voltage is doubled by cross-coupled capacitors. In other words, the frequency multiplier50according to an embodiment may use cross-coupled capacitors to increase a magnitude of an effective input voltage, and increase an effective transconductance. In addition, the frequency multiplier50may have a high conversion gain, compared to current consumption.

FIG.6is a block diagram illustrating a wireless communication device according to an embodiment. A wireless communication device1300may include an antenna1340, and may communicate with a counterpart device by transmitting or receiving a signal thereto or therefrom via the antenna1340. As a non-limiting example, a wireless communication system in which the wireless communication device1300communicates with the counterpart device may be a wireless communication system using a cellular network, such as a 5th generation (5G) wireless system, a long term evolution (LTE) system, an LTE-advanced system, a code division multiple access (CDMA) system, or a global system for mobile communication (GSM) system, a wireless local area network (WLAN) system, or any other wireless communication system.

According to an embodiment, the wireless communication device1300may include a signal processor1310, a transceiver1320, and a transmission/reception duplexer1330. The transmission/reception duplexer1330may provide the transceiver1320with a signal received via the antenna1340as an RF input signal RFin, and may provide the antenna1340with an RF output signal RFout received from the transceiver1320. According to an embodiment, the signal processor1310may be a baseband processor, and may include a control logic1312. The signal processor1310may process a transmission/reception signal in a baseband, in detail, may generate a baseband signal for a transmission signal path of the transceiver1320, and may process a baseband signal received via a reception signal path of the transceiver1320.

The transceiver1320may include a transmitter1322, a receiver1325, and an oscillator circuit1324. A frequency multiplier according to an embodiment may be included in the oscillator circuit1324, or may be used in connection with the oscillator circuit1324.

The transmitter1322may generate the RF output signal RFout by processing a transmission input signal TXin received from the signal processor1310. As illustrated inFIG.6, the transmitter1322may include a variable gain amplifier (VGA), a TX filter, a TX mixer1323, and a power amplifier (PA) to process the transmission input signal TXin. The receiver1325may generate a reception input signal RXin by processing the RF input signal RFin and provide the generated reception input signal RXin to the signal processor1310. The receiver1325may include a low noise amplifier (LNA), an RX mixer1326, a VGA, and an RX filter to process the RF input signal RFin. The oscillator circuit1324may generate a reference clock signal having a frequency for sampling the transmission input signal TXin and the RF input signal RFin and provide the generated reference clock signal to the TX mixer1323and the RX mixer1326.

AlthoughFIG.6illustrates an example in which control information is provided from the signal processor1310, an embodiment is not limited thereto. For example, the control information may be generated inside the transceiver1320, or may be generated from another control circuit outside the transceiver1320.

FIG.7is a block diagram illustrating a computing system according to an embodiment. A computing system1400may be a stationary computing system, such as a desktop computer, a workstation, or a server, or a portable computing system, such as a laptop computer. Also, the computing system1400may be a semiconductor device implemented with a semiconductor. As illustrated inFIG.7, the computing system1400may include a central processing unit (CPU)1410including an oscillator1412, a memory1420, input/output devices1430, a storage device1440, and a network interface1450. The CPU1410, the memory1420, the input/output devices1430, the storage device1440, the network interface1450, and a modem1460may be connected to a bus1470and may communicate with one another through the bus1470.

The CPU1410may be referred to as a processing unit, and may include, for example, at least one core capable of executing a certain instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit expansion IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, and the like), such as a micro-processor, an application processor (AP), a digital signal processor (DSP), and a graphics processing unit (GPU). For example, the CPU1410may access the memory1420through the bus1470, and may execute instructions stored in random access memory (RAM) or read only memory (ROM). In addition, the CPU1410may include the oscillator1412. The oscillator1412may include a frequency multiplier according to an embodiment, or may be used in connection with the frequency multiplier. For example, the oscillator1412may generate a clock signal for operating the CPU1410needing a clock signal, and may change or multiply a frequency of the clock signal according to a situation. The memory1420may include a volatile memory (e.g., RAM), including dynamic RAM (DRAM), or a nonvolatile memory (e.g., ROM), including a flash memory.

In addition, the memory1420may include an oscillator1422. The oscillator1422may include a frequency multiplier according to an embodiment, or may be used in connection with the frequency multiplier. For example, the oscillator1422may generate a clock signal for operating the CPU1410needing a clock signal, and may change or multiply a frequency of the clock signal according to a situation. The input/output devices1430may include an input device, such as a keyboard or a pointing device, and may include an output device, such as a display device or a printer. For example, a user may input M and digital trim code K_int or K_frac through the input/output devices1430, and the input/output devices1430may transmit the input M and digital trim code K_int or K_frac to the oscillator1412included in the CPU1410, and the oscillator1422included in the memory1420through the bus1470. The oscillator1412included in the CPU1410and the oscillator1422included in the memory1420may adjust the frequency of the clock signal according to the received M and digital trim code K_int or K_frac.

The storage device1440may store data to be processed by the CPU1410or data processed by the CPU1410. In other words, the CPU1410may generate data by processing the data stored in the storage device1440, and may store the generated data in the storage device1440. The network interface1450may provide access to a network outside the computing system1400. For example, the network may include a plurality of computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other types of links. The modem1460may perform wireless communication or wired communication with an external device. For example, the modem1460may perform ethernet communication, near field communication (NFC), radio Frequency Identification (RFID) communication, mobile telecommunication, memory card communication, universal serial bus (USB) communication, and the like, but is not limited thereto. In addition, the modem1460may include an oscillator1462. For example, the oscillator1462may generate a clock signal for operating the modem1460needing a clock signal, and may change or multiply a frequency of the clock signal according to a situation. The oscillator1462may include a frequency multiplier according to an embodiment, or may be used in connection with the frequency multiplier.

According to an embodiment, the oscillators1412,1422, and1462may be constituted as externally independent devices, and may further include clock control units configured to control frequencies of clock signals of the computing system1400. Accordingly, different clock signals may be provided to the CPU1410, the memory1420, and the modem1460that operate at different operation frequencies.

Embodiments have been illustrated in the drawings and description as described above. Although the embodiments have been described herein by using certain terms, these are used only for the purpose of describing the spirit of the inventive concept and not used to limit the meaning or the scope of the inventive concept defined by claims. While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.