Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator

An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device for measuring a state of the PD SOI device indicating a body voltage thereof, the measuring device being communicatively coupled to a calculating means which determines a history state of a data in the data retaining device based on the measured state of the PD SOI device.

The current application is related to co-pending U.S. patent application Ser. No. 11/279,507, currently pending.

BACKGROUND OF THE DISCLOSURE

1. Technical Field

The disclosure relates generally to a history state of data in data retaining device, and more particularly, to a method and system for determining a history state of data in a data retaining device based on a state of a partially depleted silicon-on-insulator (PD SOI) device coupled to the data retaining device.

2. Background Art

A history state of a piece of data in a data retaining device needs to be determined for various applications. A history state of data refers to a state of the data regarding any activities and inactivities (idling) that have been involved with the data since the data was stored in a data retaining device. For example, a multi-port cache is usually limited in size so that if the cache is full, some of the items in the cache need to be removed to make room for new items. A cache replacement algorithm is usually used to select items to be removed. Examples of cache replacement algorithms include a Least Recently Used (LRU) algorithm which discards the least recently used item first, and a Least Frequently Used (LFU) algorithm which discards the least frequently used item first. These algorithms require keeping track of a history state of the data, e.g., a history of the usage of the data.

For another instance, a history state of data may also need to be determined to monitor a validity of a particular machine state or a condition code in a processor. For example, to monitor whether a new clock cycle has been validly propagated into a latch, a history state of data retained in the latch needs to be determined.

According to the present state of the art technology, it is very expensive to determine a history state of data in a data retaining device. Based on the above, there is a need in the art for a solution to determine a history state of data in a data retaining device in an inexpensive/efficient way.

SUMMARY OF THE DISCLOSURE

A first aspect of the disclosure provides a design structure embodied in a machine readable medium used in a design flow process, the design structure comprising a circuit, the circuit comprising: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device for measuring a state of the PD SOI device indicating a body voltage thereof, the measuring device being communicatively coupled to a calculating means which determines a history state of a data in the data retaining device based on the measured state of the PD SOI device.

A second aspect of the disclosure provides an integrated circuit comprising: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device for measuring a state of the PD SOI device indicating a body voltage thereof, the measuring device being communicatively coupled to a calculating means which determines a history state of a data in the data retaining device based on the measured state of the PD SOI device.

DETAILED DESCRIPTION

1. General Description

The current disclosure takes advantage of the potential floating body effects, especially the history effects, of a partially depleted silicon-on-insulator (PD SOI) device that is coupled to a data retaining device to determine a history state of data stored in the data retaining device.FIG. 1shows an example of a partially depleted silicon-on-insulator (PD SOI) n-channel field-effect transistor (NFET)10. In PD SOI FET10, as shown inFIG. 1, a body20is isolated by insulator22so that a potential of body20, i.e., a body voltage, may vary with time, which is referred to as a floating body voltage. Factors contributing to the floating body voltage include coupling capacitance of body20with a drain24, a gate26and a source28, and charges that are stored in the body. PD SOI body20may be charged or discharged by activities involved with PD SOI FET10depending on, inter alia, the circuit topology, the process/device design details, and/or the relative magnitudes of the various charging/discharging mechanisms. For example, in the case that a PD SOI NFET is used as a pass gate, for each cycle of ON/OFF switches, the reverse-biased drain-to-body and source-to-body diodes may carry small diode leakage currents into body20, i.e., a small amount of charge is injected into body20. As a consequence, the body voltage of body20increases with each cycle of ON/OFF switch.

On the other hand, when pass gate PD SOI FET10idles, the body voltage reaches an equilibrium as, inter alia, the amount of charges exiting from the source-to-body diode equals the amount of charges entering from the drain-to-body diode. In addition, during a long period of idling, charges on body20further decay due to natural means. As a consequence of the decay, the body voltage equilibrium may drift either to the value of a positive power supply (VDD) or to the value of a ground (GND) depending on circuit designs.

As is appreciated, a threshold voltage of a PD SOI device, e.g., NFET10, relates directly to the body voltage of the PD SOI device. Specifically, increase in the PD SOI body voltage causes decrease in the threshold voltage of PD SOI NFET10; while decrease in the PD SOI body voltage causes increase in the threshold voltage of PD SOI NFET10. In addition, a subthreshold leakage current of a PD SOI device, here, PD SOI NFET10, depends upon the threshold voltage of the PD SOI device. An increase in the threshold voltage reduces the subthreshold leakage current. As such, a subthreshold leakage current of PD SOI NFET10may be used as an indicator of a body voltage of the same.

2. System Overview

FIG. 2shows a schematic diagram of one embodiment of an implementation system100for detecting a history state of data in a data retaining device112. As shown inFIG. 2, data retaining sub-system110, e.g., a multi-port cache, includes multiple data retaining devices112(112a,112b), e.g., ports of cache110. Each data retaining device112(112a,112b) is coupled to a PD SOI field-effect-transistor (FET)116(116a,116b, respectively). PD SOI FETs116are used as pass gates so that accesses to data retaining devices112a,112bby access line120are controlled/through PD SOI FETs116a,116b, respectively. A state of PD SOI FET116may be measured by measurer132of monitoring device130, the state indicating a body voltage of the PD SOI FET116, and the measurement results of different PD SOI FETs116may be compared in comparator134. Measurer132may be any now known or later developed devices that can measure, inter alia, a state of a PD SOI FET116including, but not limited to, a body voltage, a threshold voltage, or a subthreshold leakage current of the PD SOI FET116. According to one embodiment, PD SOI FETs116are tuned to be of the same size to facilitate processing and a comparison between the states, e.g., body voltages, of different PD SOI FETs116. However, any choices of PD SOI FETs116with different sizes are also included in the current disclosure, and methods may be taken to make the states of PD SOI FETs116a,116bcomparable.

Monitoring device130is responsive to a computer system200. Specifically, computer system200controls monitoring device130in performing, inter alia, the above-mentioned measurement and comparison, and receives measurement and comparison results from monitoring device130. Upon processing the measurement and/or comparison results, computer system200may determine an action to be performed upon data retaining devices112, and may control data retaining sub-system110to do the same. For example, computer system200may determine which data retaining device(s)112of data retaining sub-system110needs to be refreshed.

It is appreciated that the units of system100may reside at separate physical locations or at a single physical location. In addition, components or functions of one unit of system100may be integrated into other units. For example, the functions of comparator134may be performed by computer system200, as will be described later. Details of computer system200will be described below.

3. Computer System

FIG. 3shows a block diagram of an illustrative computer system200according to one embodiment of the disclosure. In one embodiment, computer system200includes a memory220, a processing unit (PU)222, input/output devices (1/0)224and a bus226. A database228may also be provided for storage of data relative to processing tasks. Memory220includes a program product230that, when executed by PU222, comprises various functional capabilities described in further detail below. Memory220(and database228) may comprise any known type of data storage system and/or transmission media, including magnetic media, optical media, random access memory (RAM), read only memory (ROM), a data object, etc. Moreover, memory220(and database228) may reside at a single physical location comprising one or more types of data storage, or be distributed across a plurality of physical systems. PU222may likewise comprise a single processing unit, or a plurality of processing units distributed across one or more locations. I/O224may comprise any known type of input/output device including a network system, modem, keyboard, mouse, scanner, voice recognition system, CRT, printer, disc drives, etc. Additional components, such as cache memory, communication systems, system software, etc., may also be incorporated into computer system200.

As shown inFIG. 3, program product230may include a data history state determining system232that includes a data collector240; a priority controller242; a measurement controller244; a comparator246; an implementer248; and other system components250. Other system components250may include any now known or later developed parts of a computer system200not individually delineated herein, but understood by those skilled in the art.

Inputs to computer system200include measurement result inputs260and user instruction inputs262. Measurement result inputs260may include measurement (and/or comparison) results of monitoring device130regarding, e.g., a state of a PD SOI FET116(FIG. 2). User instruction inputs262include instructions of a user of computer system200regarding the operation of, inter alia, data history state determining system232. For example, a user may instruct priority controller242with respect to a priority of a data retaining device112. These inputs may be obtained by data collector240, and may be saved in database228. Outputs of computer system200include instruction outputs264that are communicated to, inter alia, data retaining sub-system110to perform an action on data retaining devices112, e.g., refreshing data retaining devices112.

FIG. 4shows a flow diagram of one embodiment of an operation of data history state determining system232according to one embodiment of the disclosure. As stated above, a history state of data refers to a state of the data regarding any activities and inactivities (idling) that have been involved with the data since the data was stored in a data retaining device112(FIG. 2). In the following description of the disclosure, an idling period of data in a data retaining device112(also an idling period of the data retaining device), i.e., a period that the data is not accessed, will be used as an illustrative example of a history state of the data. It is appreciated that determining of other history states of data in a data retaining device is similarly included in the current disclosure.

Referring toFIGS. 2-4, in process S1, priority controller242prioritizes PD SOI FETs116(FIG. 2) according to determined/obtained priorities of data retaining devices112coupled to PD SOI FETs116. Any methods for determining/obtaining a priority of a data retaining device (DRD)112are included in the current disclosure. For instance, according to one embodiment, the priority of a data retaining device112may be communicated directly by a user through user instruction input(s)262to data collector240. According to an alternative embodiment, priority controller242determines a priority of a data retaining device112based on a policy preset by a user. For example, a policy may stipulate that a data retaining device112with a certain type of data stored therein shall have a priority. In this case, if priority controller242detects that the type of data is contained in a data retaining device112, priority controller242will set a priority to that specific data retaining device112. In the following description, it is assumed that priority controller242has determined/set data retaining device112a(FIG. 2) has a priority over data retaining device112b, for illustrative purposes.

Various methods may be used to prioritize PD SOI FET116athat is coupled to data retaining device112awith a priority as described above. According to one embodiment, a decay rate of PD SOI FET116amay be controlled so that the body voltage of PD SOI FET116awill decay more slowly than the body voltage of PD SOI FET116bthat is coupled to data retaining device112bwith no priority. For example, a dislocation or a controlled degradation of the source and drain diodes of PD SOI FET116amay change the decay rate of the body voltage of PD SOI FET116a. As such, in the case that PD SOI FET116aand PD SOI FET116bhave idled for a same period of time, body voltage of PD SOI FET116awill decay less than the body voltage of PD SOI FET116b(except that body voltages of both have decayed completely). As a consequence, a comparison between the body voltages of PD SOI FETs116aand116bwill choose data retaining device112b(with no priority) as the one that has idled “longer” and needs to be, e.g., refreshed. According to an alternative embodiment, a weight factor may be assigned to a measured state of PD SOI FET116athat indicates the body voltage of the same. As such, in the case that PD SOI FETs116a,116bhave been idled for a same period of time, and body voltages of PD SOI FETs116aand116bhave decayed to the same value, the assigned weight factor will differentiate PD SOI FET116afrom PD SOI FET116band make data retaining device112b(with no priority) as the one that has idled “longer” and needs to be refreshed. The results of the prioritizing by priority controller242may be communicated to, e.g., a user through instruction outputs264to tune PD SOI FETs116, or may be communicated to comparator246as a weight factor.

Next in process S2, measurement controller244controls measurer132to measure a state of a PD SOI FET116that indicates a body voltage of the PD SOI FET116. Any states of a PD SOI FET116that can indicate, directly or indirectly, a body voltage of the PD SOI FET116may be measured by measurer132. According to one embodiment, a subthreshold leakage current of a PD SOI FET116may be measured as an indicator of the body voltage of the same. As has been described above, a subthreshold leakage current of a PD SOI FET116varies in the same direction as a body voltage of the PD SOI FET116does. That is, the subthreshold leakage current increases with an increase in the body voltage, and decreases with a decrease in the body voltage. One advantage of measuring the subthreshold leakage current as an indicator of the body voltage of a PD SOI FET116is that it will not corrupt the body voltage. As is appreciated, based on the current state of the art technology, measuring a body voltage of a PD SOI directly will corrupt (e.g., change) the body voltage, which is not preferable. Various methods may be used to measure a subthreshold leakage current of a PD SOI FET116, and all are included in the current disclosure. As details of such a measurement are not necessary for an understanding of the current disclosure, no further details will be provided.

Next in process S3, comparator246determines a history state of data stored in data retaining devices112a,112bbased on the measured state of PD SOI FETs116a,116b, respectively. According to one embodiment, comparator246first weighs the measured state of each PD SOI FET116according to a weight factor (if any) preset by priority controller242in process S1. Next, comparator246compares the weighted measurement results of all the PD SOI FETS116of concern to determine, e.g., a PD SOI FET116that has idled/decayed for a longest time (with consideration of the weight factor, as is appreciated). Different standards may be used in the determination for different circuit designs involving PD SOI FETs116. Specifically, in the case that body voltage equilibriums of PD SOI FETs116are designed to drift to a positive power supply (VDD), comparator246selects a PD SOI FET116with the highest weighted subthreshold leakage current as the one that has decayed/idled for the longest time. On the other hand, in the case that body voltage equilibriums of PD SOI FETs116are designed to drift to a ground (GND), comparator246selects a PD SOI FET116with the lowest weighted subthreshold leakage current as the one that has decayed/idled for the longest time. Please note again that a subthreshold leakage current changes in the same direction as a body voltage of a PD SOI device. The history state, here, e.g., the idling period, of data stored in data retaining devices112a,112bmay be determined based on the period of idling/decay of PD SOI FETS116a,116b, respectively, as the idle periods of PD SOI FETs116a,116bindicate the periods during which data stored in data retaining devices112a,112b, respectively are not accessed, i.e., idling.

According to an alternative embodiment, comparator246compares the weighted measurement results of the state of PD SOI FETs116to a preset threshold. If the weighted measurement result of the state of a PD SOI FET116meets the threshold, a history state of the data in the data retaining device112coupled to the PD SOI FET116is considered as meeting a threshold to be taken actions upon. For example, comparator246may compare a period of idling/decay of a PD SOI FET116, which may be indicated by the measured subthreshold leakage current, to a preset threshold for a period of idling.

It is appreciated that the function of comparator246of computer system200may also be performed by comparator134of monitoring device130, as a hardware implementation. For example, comparator134may be a hardware comparator or a current mirror to compare the subthreshold leakage currents of PD SOI FETs116.

Next in process S4, implementer248determines an action upon a data retaining device112based on the determined history state of data stored therein, and controls data retaining sub-system110to implement the action. For example, implementer248may determine to refresh the data retaining device112with data that has not been accessed for the longest period among all data retaining devices112of concern. Moreover, in the case that comparator246cannot yield a valid result of comparison, e.g., the weighted subthreshold leakage currents of two PD SOI FETs116a,116bare the same, implementer248will determine an action based on other standards, e.g., priority of data retaining devices112a,112b.

The above description uses PD SOI FETs116acting as pass gates to data retaining devices112(FIG. 2) only as illustrative examples of PD SOI devices that are coupled to data retaining devices112. It should be appreciated that other types of PD SOI devices are also included in the current disclosure. For example, a PD SOI device may include multiple PD SOI FETs that are coupled together in a static random access memory (SRAM).FIG. 5shows a six-transistor SRAM300including PD SOI FETs302,304,306,308,310and312. In SRAM300, after SRAM300sits idle for a long time in the same state, the balance of forward and reverse diode leakage currents establishes an equilibrium static body voltage which is a function of the source and drain voltages of each PD SOI FET302,304,306,308,310and312. As a consequence, the body voltage of one side of SRAM300goes high and the body voltage of the other side goes low, which causes an increases in the subthreshold leakage current.

A complete integrated circuit including circuit100or300, which may be referred to herein as a design structure, is created in a graphical computer programming language, and coded as a set of instructions on machine readable removable or hard media (e.g., residing on a graphical design system (GDS) storage medium). That is, design structure(s) is embodied in a machine readable medium used in a design process. (The design structure(s) may interface with any part of a machine readable media). The design structure(s) may include a netlist, which describes circuit100or300, and may include test data files, characterization data, verification data, or design specifications. If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design structure by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities as a foundry, directly or indirectly. The stored design is then converted into the appropriate format (e.g., graphic design system II (GDSII)) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

FIG. 6depicts a block diagram of an example design flow1000, which may vary depending on the type of IC being designed. For example, a design flow1000for building an application specific IC (ASIC) will differ from a design flow1000for designing a standard component. A design structure1020is an input to a design process1010and may come from an IP provider, a core developer, or other design company. The design structure1020comprises a circuit, e.g., circuits100,300, in the form of schematics or HDL, a hardware-description language, (e.g., Verilog, VHDL, C, etc.). The design structure1020may be on one or more of machine readable medium, e.g., memory220as shown inFIG. 3. For example, the design structure1020may be a text file or a graphical representation of circuit100or300. The design process1010synthesizes (or translates) the circuits100,300into a netlist1080, where the netlist1080is, for example, a list of fat wires, transistors, logic gates, control circuits, I/O, models, etc., and describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one machine readable medium220.

The design process1010includes using a variety of inputs; for example, inputs from library elements1030which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications1040, characterization data1050, verification data1060, design rules1070, and test data files1085, which may include test patterns and other testing information. The design process1010further includes, for example, standard circuit design processes such as timing analysis, verification tools, design rule checkers, place and route tools, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process1010without deviating from the scope and spirit of the disclosure.

Ultimately, the design process1010translates the circuit100or300along with the rest of the integrated circuit design (if applicable), into a final design structure1090(e.g., information stored in a GDS storage medium). The final design structure1090may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, test data, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce circuit10,110. The final design structure1090may then proceed to a stage1095of design flow1000; where stage1095is, for example, where final design structure1090: proceeds to tape-out, is released to manufacturing, is sent to another design house or is sent back to the customer.

While shown and described herein as a method and system for determining a history state of data in a data retaining device, it is understood that the disclosure further provides various alternative embodiments. For example, in one embodiment, the disclosure provides a program product stored on a computer-readable medium, which when executed, enables a computer infrastructure to determine a history state of data in a data retaining device. To this extent, the computer-readable medium includes program code, such as data history state determining system232(FIG. 3), which implements the process described herein. It is understood that the term “computer-readable medium” comprises one or more of any type of physical embodiment of the program code. In particular, the computer-readable medium can comprise program code embodied on one or more portable storage articles of manufacture (e.g., a compact disc, a magnetic disk, a tape, etc.), on one or more data storage portions of a computing device, such as memory220(FIG. 3) and/or database228(FIG. 3), and/or as a data signal traveling over a network (e.g., during a wired/wireless electronic distribution of the program product).

In another embodiment, the disclosure provides a method of generating a system for determining a history state of data in a data retaining device. In this case, a computer infrastructure, such as computer system200(FIG. 3), can be obtained (e.g., created, maintained, having made available to, etc.) and one or more systems for performing the process described herein can be obtained (e.g., created, purchased, used, modified, etc.) and deployed to the computer infrastructure. To this extent, the deployment of each system can comprise one or more of: (1) installing program code on a computing device, such as computing system200(FIG. 3), from a computer-readable medium; (2) adding one or more computing devices to the computer infrastructure; and (3) incorporating and/or modifying one or more existing systems of the computer infrastructure, to enable the computer infrastructure to perform the process processes of the disclosure.

In still another embodiment, the disclosure provides a business method that performs the process described herein on a subscription, advertising supported, and/or fee basis. That is, a service provider could offer to determine a history state of data in a data retaining device as described herein. In this case, the service provider can manage (e.g., create, maintain, support, etc.) a computer infrastructure, such as computer system200(FIG. 3), that performs the process described herein for one or more customers and communicates the results of the data history state determination to the one or more customers. In return, the service provider can receive payment from the customer(s) under a subscription and/or fee agreement and/or the service provider can receive payment from the sale of advertising to one or more third parties.