3-level line driver

Included are embodiments of a 3-level line driver. At least one embodiment of a method includes generating a repetitive wave; receiving an input signal and a complement of the input signal; providing a 3-level output signal; and filtering a feedback signal, the means for filtering including at least one of the following: a 0th order filter, and an even order filter.

BACKGROUND

A sampling scheme to generate pulse width modulated (PWM) signals may include a comparator to compare an input signal with a triangular waveform. The design of such a comparator in a fully differential manner can be difficult. First, a fully differential comparator may utilize two input terminals and two reference inputs for the differential reference. The input stage may be arranged as a differential differencing amplifier. Further, an input common mode of the circuit may be from rail-to-rail. These constraints can adversely affect the speed and accuracy of the comparator.

Further, a digital subscriber line (DSL) line driver at a central office (CO) may be implemented as a bipolar class-AB amplifier. However, linear amplification of a discrete multi tone (DMT) signal may be very power inefficient because the signal hovers around zero with occasional peaks due to the large peak-to-root mean square (rms) ratio (PAR).

SUMMARY

Included are embodiments of a 3-level line driver. At least one exemplary embodiment includes means for generating a repetitive wave, means for receiving an input signal and a complement of the input signal, means for providing a 3-level output signal, and means for filtering a feedback signal, the means for filtering including at least one of the following: a 0thorder filter and an second order filter.

Also included are embodiments of a method. At least one embodiment of a method includes generating a repetitive wave; receiving an input signal and a complement of the input signal; providing a 3-level output signal; and filtering a feedback signal, the means for filtering including at least one of the following: a 0thorder filter and a second order filter.

DETAILED DESCRIPTION

To deliver 20 dBm of power in an asynchronous digital subscriber line 2+ (ADSL2+) system, the peak line voltage is generally about 18 Volts. As technology limits supply voltage, a step-up transformer is often used. For a given technology, it can be shown that class-D power amplifier efficiency degrades as transformer ratio is increased and/or supply voltage is reduced. Further, step-up ratios larger than 2.5 may become impractical, as such ratios can degrade transformer bandwidth and signal to noise ratio (SNR) of the signal received from a customer premise equipment (CPE). Therefore, it is desirable to choose a process that supports high voltage. Although some complementary metal oxide semiconductor (CMOS) processes offer high-voltage double diffused metal oxide semiconductor (DMOS) transistors, DMOS devices are generally much slower than the CMOS devices. Further, such processes are often more expensive than conventional CMOS. Embodiments disclosed herein may use a mainstream 0.35 μm CMOS technology with thick oxide 5V transistors that can support a 10V supply voltage when stacked. Core devices may be used to perform low-power signal processing. Three-level (+1, 0, −1) differential pulse width modulation (PWM) is chosen to better track the predominantly low-level DMT signal. The switching frequency of each bridge half is approximately only 8.832 MHz compared to the 25 MHz self-oscillation frequency of an earlier solution. The lower switching rate is favorable for lower power consumption. Class-D PWM amplifiers are common in audio applications. The triangle or ramp rate for audio is generally more than a factor of ten times the signal bandwidth. For broadband applications, such large over-sampling may be difficult to utilize.

Referring now to the drawings,FIG. 1illustrates an exemplary 2-level PWM line driver with a triangular voltage being used as a reference. As illustrated in the nonlimiting example ofFIG. 1, an input signal is received at a summer102, which subtracts the input signal with a feedback signal. The subtracted signal is sent to an integrator104, which may be configured to output a signal that is an integrated version of the input. The integrator sends the integrated signal to a comparator106, as well as to a comparator108via inverter110. The comparators106and108compare the received signals with a triangle wave from triangle generator112to obtain naturally sampled PWM signals, which drive a bridge or other bridge power stage114. The comparators106and108send the resulting compared signals to the bridge114. The bridge114processes and sends the signals to a summer116for subtraction, as well to inductors118,122and capacitors120,124for filtering out high frequency portions of the signal. The resulting signals are sent to a load126.

Additionally, the summer116subtracts the received signals and sends the subtracted signal to a low pass filter (LPF)128. The LPF128further suppresses high frequency Bessel components that are sent to the summer102and comparators106,108. This reduces the aliasing effect caused by the feedback signal.

FIG. 2illustrates an exemplary 2-level PWM line driver with a square current being applied to the integrator, similar to the diagram fromFIG. 1. As illustrated inFIG. 2, a square wave generator202is configured to generate a square wave for input into a combiner204. Also received at the combiner204are an input signal and a feedback signal from an LPF228. The combiner204may be configured to add the square wave with the input signal and subtract the feedback signal. The resulting signal may be sent to an integrator206. As withFIG. 1, the integrator may be configured to integrate the received signal. Additionally, the integrator206can convert the square wave into a triangular voltage.

The integrator206may send the integrated signal to a first comparator208, which is also referenced to ground. Similarly, the integrated signal may also be sent to an inverter210, which inverts the signal and sends the inverted signal to a comparator212. One should note that, in some embodiments, all the circuit blocks are fully differential although shown as single-ended to simplify the drawings. Hence, the integrator may be configured to provide both true and complementary (inverted) outputs. Block210is only a mathematical representation of the inverted signal. The comparator212compares the inverted signal with ground and sends the resulting signal to the bridge214. The bridge214processes the received signals and sends the processed signals to a summer216, as well as to inductors218,222and capacitors220and224. The inductor/capacitor pairs may be configured to filter high frequency portions of the signal before being sent to the load226.

Additionally, as indicated above, the summer216receives the processed signals from the bridge214and subtracts them. The summer216additionally sends the resulting signal as a feedback signal to the LPF228and back to the combiner204.

FIG. 3illustrates an exemplary embodiment of a 3-level line driver, similar to the 2-level line driver fromFIG. 1. As illustrated in other embodiments, true and complementary versions of an analog input signal from integrators306and312are compared with a triangular waveform from triangle wave generator308to obtain naturally sampled PWM signals. The naturally sampled PWM signals may be configured to drive the bridge power stage316. Additionally, a differencing operation in the bridge results in a 3-level PWM signal. The signals P+ and P− may be combined by combiner318to result in a feedback signal. The feedback may be configured to minimize non-linearity introduced in the power stage. An LPF332may be configured to reduce aliasing by suppressing the high-frequency Bessel components that feed back into the comparators310and314, via the integrators306and312(after being combined with input signals via combiners302and304). The integrators306and312in the forward path provide the in-band distortion “shaping”. The LC (inductor320and capacitor322; inductor324and capacitor326) filters and suppresses high frequency energy and increases the load impedance seen by the power stage at the switching frequency. The filtered signal may be sent to a transformer330to provide an output voltage Vout.

The frequency of the triangular signal (ftriangle) from the triangle wave generator308may be configured to be minimal to reduce switching losses and dissipation in the low level signal processing section. However, a low switching frequency may lead to an increase in distortion due to aliasing. Aliasing can occur when high-frequency Bessel components located around multiples of ftrianglefeed back into the comparators that perform natural sampling. Thus, energy folds into the signal band and results in distortion, even in an ideal system. Aliasing may depend strongly on a transfer function from comparator output back to its input, similar to a 2-level PWM. As this transfer also affects the distortion “shaping,” the overall goal is to find a loop transfer that minimizes aliasing while maximizing shaping.

FIG. 4illustrates an exemplary 3-level PWM line driver, with comparators referenced to ground, similar to the diagram fromFIG. 2. As illustrated in the nonlimiting example ofFIG. 3, a square wave generator402may be utilized as providing an input to combiners404and410. The combiner404also receives an input signal and an inverted feedback signal from a LPF430. Similarly, the combiner410receives the square wave signal, as well as the feedback signal from the LPF430and an inverted input signal. The combined signals are sent to integrators406and412, respectively. As discussed above, the integrators integrate the input signal.

After integration, the signals from integrators406and412may be sent to comparators408and414, respectively. The comparators408and414compare the received signals to ground and send the result to a bridge416. The bridge416processes the received signals, and sends the processed signals to a combiner418, as well as inductors420,424, and capacitors422,426. From the inductor/capacitor pairs (which serve to filter out high frequency portions of the signals), the signals are sent to a load428. Additionally, the combiner418subtracts the signals received from the bridge416and sends the subtracted signal as a feedback signal to the LPF430, which is returned to combiners404and410, as discussed above. One issue with this scheme is that the integrators may be sensitive to offset errors. Offset can saturate the output of the integrators406and412.

FIG. 5illustrates an exemplary embodiment of integrators with common-mode direct current (DC) feedback, such as might be utilized inFIG. 4. As illustrated in the nonlimiting example ofFIG. 5, the input voltage (Vin+ and Vin−) may be the same input received at integrators306and/or312fromFIG. 3. The voltage may be sent to a resistor R1502aand R1502b. From the resistors R1502a,502b, the signal may be sent to a negative terminal of op amps510aand510b, which have a positive terminal coupled to ground. From R1502a,502b, the signal may also be sent to a capacitors C1508aand508b, and resistors Rf506aand506b. The signal (Vout+ and Vout−) may then be sent to a resistors R3512aand512b, respectively and then combined and sent to a negative terminal of an operational amplifier (op amp)516(with a positive terminal coupled to ground), as well as a capacitor C3514. The signal may be recombined and sent to an inverter518, which may be sent back to resistors R2504aand504bas a direct current feedback signal. Such a configuration may be utilized to overcome offset problems associated with integrator saturation, described above.

FIG. 6illustrates another exemplary embodiment of a line driver, with common mode DC feedback, as illustrated inFIG. 5. The design inFIG. 6is fully differential and illustrated as single ended for simplicity. A charge-pump616supplies a square current to the integrator (embodied as resistors604,606,610, capacitor612, inverter619, and op amp614for a first integrator; and resistors618,620,622, and626, capacitor628, and op amp630), which generate the triangle.

Each forward integrator (e.g., resistors634,636, capacitor637, op amp638, and inverter624) with the common DC feedback path forms a leaky integrator, e.g., an integrator with finite low-frequency gain. The leaky integrators' outputs may be configured to substantially match the response of an ideal integrator for frequencies above 100 kHz. The 2nd-order LPF in the feedback path (e.g., resistors656,658,664, capacitor662, and op amp665) may be implemented as a Rauch biquad based on a single op-amp665. This offers common mode suppression and performs a level shift from the 10V bridge section to the 3.3V signal processing part. A high supply voltage may be utilized to achieve high efficiency. A simple stack of two 5V transistors for both n- and p-devices may be configured for a supply voltage of 10V for the bridge. The gates of the cascode devices may be fixed at 5V. As the devices do not experience maximum gate-to-source and drain-to-source voltages at the same instant, hot carrier effects may be less. In a conventional CMOS process with a p-substrate, the p-channel devices can be placed in separate n-wells. As a result, the 10V supply appears across two drain-to-body diodes and junction breakdown is not an issue. Unfortunately, the n-channel devices have no isolated wells and the entire 10V appears across a single drain-to-substrate diode of the cascode device. The breakdown voltage of this process is just above 10V.

FIGS. 7A and 7Bshow the effect of the phase of the feedback signal, such as might be utilized in the line driver ofFIG. 6. When the phase of the received signal is 0 compared to the triangle as shown inFIG. 7Afor an input equal to DC1, the compoutsignal is displaced to the right and the width is not affected much. On the other hand, if the phase of the feedback signal is 90 as shown inFIG. 7B, the width of the compoutsignal can shrink, thus introducing distortion.

FIG. 8illustrates exemplary theoretical and simulated third-order harmonic distortion (HD3) due to aliasing for a 3-level PWM closed loop system. This nonlimiting example assumes a single integrator with various feedback low-pass filter orders NLPF; all components are ideal. Theoretical results are obtained by extending the theory of a 2-level PWM to a 3-level PWM and confirmed with simulation. Integrator ftriangleand LPF cutoff frequencies are chosen such that the signal bandwidth is approximately 2.2 MHz.

As shown inFIG. 8, theory and simulation match closely. At very low and very high input amplitudes, distortion due to aliasing (HD3) may be less due to the decrease in energy of the high frequency Bessel components in the 3-level PWM signal. Surprisingly, a single integrator without any LPF (NLPF=0; plot840) outperforms a combination of integrator and 1st-order feedback filter (plot841). Even though the 1st-order filter reduces high frequency Bessel components, it worsens aliasing. This is because both magnitude and phase transfer from modulator output back to its input play a crucial role in the amount of aliasing. The 2nd-order filter (plot842) provides a better solution, particularly at medium and low input levels. As the DMT signal hovers around zero most of the time, the system benefits from having a 2nd-order filter in the feedback path. Similarly, other even order filters (2nd-order, 4th-order, etc.) and/or 0th-order filters may have similar results.

FIG. 9illustrates an exemplary simulated multi-tone-power-ratio (MTPR), such as from the line driver inFIG. 6. More specifically, the MTPR illustrated inFIG. 6may be due to aliasing in a closed-loop 3-level PWM system with ftriangle=8.832 MHz and signal bandwidth (BW)=2.2 MHz, again assuming the system is ideal. The out-of-band suppression of the LC filter is not included. The plot inFIG. 9is obtained by taking an average output power spectrum over 40 random DMT symbols (e.g., from the system ofFIG. 6), each with PAR=5.6. The input signal may be applied at approximately 90% full-scale. Again a 2nd-order feedback filter may be a desirable option, both in- and out-of-band.

As illustrated, a signal with NLPF=1 (plot941) produces worse MTPR over much of the frequency range compared with the cases with NLPF=0 (plot940) and NLPF=2 (plot942). Additionally, NLPF=2 (plot942) has better MTPR than NLPF=0 (plot940) and NLPF=1 (plot941) for most of the frequencies.

FIG. 10illustrates exemplary measured waveforms in one half of a bridge, such as the bridge fromFIG. 6. The nonlimiting example ofFIG. 10shows an input sinusoidal signal1050, a triangle wave subtracted form the sinusoid1052, and a 2-level PWM signal of one bridge half1054. Together with the 2-level PWM signal1054of the other bridge half this forms the 3-level PWM signal in differential mode. The triangle wave1052may be measured through an on-chip test buffer. As also shown, the average level of the subtracted triangular wave1052follows the input sinusoid1050, allowing the comparator to operate as a zero crossing detector. Additionally, the PWM signal1054may be configured to switch whenever the triangle subtracted wave1052crosses the zero level, confirming the correct functionality of the circuit. Voltage spikes in the PWM signal1054caused by bond wire inductance can also be seen. These spikes may cause temporary breakdown of the drain-to-substrate junction of the n-channel device resulting in higher non-linearity and higher power consumption. A Multi-Tone Power Ratio (MTPR) test may be performed to determine the non-linearity of the ADSL2+ line driver (e.g., from the line driver inFIGS. 3,4, and/or8). A Discrete Multi Tone (DMT) waveform is a signal including a plurality of discrete frequency components. In the case of an MTPR test, this waveform may include missing frequency components, or spectral notches. The MTPR may include a ratio of the power in a spectral notch to the power in the adjacent individual frequency components.

FIG. 11illustrates an exemplary measured DMT spectrum, such as in the line driver fromFIG. 6. As shown, the DMT spectrum1150is plotted at the line while delivering 100 mW of power to a 100 Ohm line through a 1:2.3 step-up transformer. In this nonlimiting example, the signal has a peak-to-average ratio (PAR) of approximately 5, giving a peak line voltage of approximately 18V. The resulting worst-case for this exemplary MTPR is approximately −52 dB.

FIG. 12illustrates a measured ADSL2+ downstream data rate as a function of line length, such as may be provided in the line driver fromFIG. 6. The measurement may be taken by connecting a central office (CO) board including a class D line driver to a customer premises (CPE) device, through a line simulator box. Generally speaking, in a DSL setup, the line attenuation may increase dramatically as the length increases, especially at higher frequencies, causing the system to reduce the bit loading of the high-frequency DMT tones. Also, the system automatically increases line power1252at long loop lengths, to compensate for the increased attenuation and thus loss in SNR. The downstream data rate1250may be measured by the CPE itself and obtained through an Ethernet connection to the CPE. Existing firmware may be used in the CO and CPE; by optimizing firmware for this particular line driver the data rate can be increased somewhat more.

It should be emphasized that the above-described embodiments are merely possible examples of implementations, merely set forth for a clear understanding of the principles of this disclosure. Many variations and modifications may be made to the above-described embodiment(s) without departing substantially from the spirit and principles of the disclosure. Further, the scope of the present disclosure is intended to cover all combinations and sub-combinations of all elements, features, and aspects discussed above. All such modifications and variations are intended to be included herein within the scope of this disclosure.