Pixel circuit with fast read out

An image sensor includes a first photodiode with associated first sense node and a second photodiode with associated second sense node. A first transistor has its control node coupled to the first sense node and a second transistor has its control node coupled to the second sense node. The conduction paths (for example, source-drain paths) of the first and second transistors are coupled in series between first and second column lines associated with a column of the image sensor array. Switches control connection of the first and second column lines in two modes: one mode where a voltage is applied to the first column line and data from one of the photodiodes is read out by the second column line; and another mode where a voltage is applied to the second column line and data from the other of the photodiodes is read out by the first column line.

PRIORITY CLAIM

This application claims priority from French Application for Patent No. 1450614 filed Jan. 24, 2014, the disclosure of which is incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to the field of image sensors, and in particular to a pixel circuit of an image sensor and to a method of reading a pixel value.

BACKGROUND

In the field of CMOS image sensors, there is a continuing need for pixel circuits having fewer transistors in order to permit increased resolutions and/or reduced surface area.

One technique often used for reducing the number of transistors in each pixel circuit is to use common reset and read transistors for multiple photodiodes. The number of transistors in a pixel circuit is generally expressed as the number of transistors per photodiode, and the use of multiple photodiodes can permit the number of transistors per photodiode to be reduced to two or less.

Indeed, in such a pixel circuit, each photodiode is usually associated with a corresponding transistor forming a transfer gate, for transferring charge accumulated by the photodiode to a sense node. The pixel circuit further comprises a reset transistor for resetting the photodiodes, and a read transistor for selectively coupling the sense node to an output line via a source follower transistor. Reference is made to United States Patent Application Publication No. 2006/0208163 (incorporated by reference) which further proposes a pixel circuit without any read transistor.

However, there are difficulties in reducing the number of transistors in each pixel circuit without also reducing the speed at which the pixels of the image sensor can be read. There is a need in the art to at least partially address one or more problems in the prior art.

SUMMARY

According to one aspect, there is provided a circuit of an image sensor comprising: a first transistor having its control node coupled to a first sense node, the first sense node being coupled to at least one photodiode; and a second transistor having its control node coupled to a second sense node, the second sense node being coupled to at least one photodiode; wherein said first and second transistors are coupled in series with each other between first and second column lines.

According to one embodiment, the first sense node is coupled to a first photodiode via a first transfer transistor and to a second photodiode via a second transfer transistor; and the second sense node is coupled to a third photodiode via a third transfer transistor and to a fourth photodiode via a fourth transfer transistor.

According to one embodiment, the first, second, third and fourth photodiodes are positioned in consecutive rows of a column of a pixel array of the image sensor.

According to one embodiment, the first, second, third and fourth photodiodes are positioned in a two-by-two pixel block of a pixel array of the image sensor.

According to one embodiment, the first transistor has a first main current node coupled to said first column line; the second transistor has a first main current node coupled to the second column line; and the second main current nodes of the first and second transistors are coupled together.

According to one embodiment, the circuit further comprises: a first reset transistor coupled between the first sense node and a first variable voltage level; and a second reset transistor coupled between the second sense node and a second variable voltage level.

According to one embodiment, the circuit further comprises a plurality of switches adapted to switch the first and second column lines between first and second configurations, wherein: in the first configuration, the first column line is coupled to a supply voltage level and the second column line is coupled to a column output node; and in the second configuration, the second column line is coupled to the supply voltage level and the first column line is coupled to the column output node.

According to one embodiment, the circuit further comprises a control circuit adapted to control the switches to be in one of the first and second configurations during a read operation of a voltage at the first sense node, and adapted to control the switches to be in the other of the first and second configurations during a read operation of a voltage at the second sense node.

According to a further aspect of the present disclosure, there is provided an image sensor comprising an array of photodiodes, arranged in rows and columns, each column comprising a plurality of the above circuits, each circuit comprising at least two of the photodiodes of the column.

According to yet a further aspect of the present disclosure, there is provided an electronic device comprising: a processing device; and the above image sensor.

According to yet a further aspect of the present disclosure, there is provided a method comprising: reading, using the above circuit, a pixel value captured by the first photodiode.

According to one embodiment, reading the pixel value comprises: applying a first supply voltage to the control node of the second transistor to activate the second transistor; applying a second supply voltage to one of the first and second column lines; and reading the pixel value via the other of the first and second column lines.

According to one embodiment, applying the first supply voltage to the control node of the second transistor comprises activating a reset transistor coupled between the second sense node and the first supply voltage.

According to one embodiment, applying the second supply voltage to one of the first and second column lines and reading the pixel value via the other of the first and second column lines comprises controlling a plurality of switches to couple one of the first and second column lines to the second supply voltage and to couple the other of the first and second column lines to a column output node.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1schematically illustrates circuitry100of an image sensor and substantially reproduces FIG. 4 of the United States Patent Application Publication No. 2006/0208163. The circuitry100comprises four photodiodes PD1to PD4split between two pixel circuits101and101′, sometimes referred to in the art as 2T pixels, which have no read transistor.

The photodiodes PD1and PD2are in corresponding rows ROW1and ROW2of the image sensor and form part of the pixel circuit101having a sense node SN1. The photodiodes PD1and PD2are coupled to the sense node SN1via corresponding transfer transistors102,104controlled by transfer signals Tx. The sense node SN1is coupled to the gate of a source follower transistor SF1, which is in turn coupled between a supply voltage VDDand a column line Vx. The sense node SN1is also coupled to a supply level VSSor VREFvia a reset transistor106controlled by a reset signal RESET.

Similarly, the photodiodes PD3and PD4are in corresponding rows ROW3and ROW4of the image sensor, and form part of the pixel circuit101′ having a sense node SN2. The photodiodes PD3and PD4are coupled to the sense node SN2via corresponding transfer transistors102′,104′ controlled by transfer signals Tx. The sense node SN2is coupled to the gate of a source follower transistor SF2, which is in turn coupled between the supply voltage VDDand the column line Vx. The sense node SN2is also coupled to the supply level VSSor VREFvia a reset transistor106′ controlled by a reset signal RESET.

In operation, when the signal from the row ROW1is to be read out, the reset transistor106is turned on such that a high voltage reference VREFis applied to the sense node SN1. The other sense nodes of the other pixel circuits are placed at voltage VSSthrough their respective reset transistors. Thus, only the node SN1associated with the mw to be read is at a high voltage, while all the other sense nodes are at a low voltage.

Next, the reset transistor for the row to be read is turned off, and the transfer gate for the mw is turned on. The accumulated charge from the photodiode is then transferred to the sensor node SN1, and the signal produced by the photodiode of the pixel in row ROW1is then amplified by the source follower transistor SF1and provided on the column line Vx. The reset transistor106is then coupled again to the low voltage VSS.

A drawback of the circuit ofFIG. 1is that it is not possible to reset the voltage at the sense node of one pixel circuit at the same time as a sense node of another pixel circuit in the same column is being read. For example, a reset of the photodiode102involves activating the reset transistor106to apply the high voltage VREFto the sense node SN1, thereby causing the source follower transistor SF1to be activated. Therefore, the column line Vx can not be used to read out a voltage from another pixel circuit. An integration phase of each photodiode is generally initiated by a reset operation. Thus, in the circuit ofFIG. 1, the start integration operations for the pixels of a column must be performed in series, and not in parallel, with the read operations of the pixels in the column, leading to a slow read out of the pixels of the image sensor.

A further drawback is that, while in other types of circuits a relatively low voltage of 0.3 to 0.5 V can be applied to the sense nodes of the pixels in order to reduce dark current, this is not possible in the circuit ofFIG. 1. Consequently, the transistors SF1and SF2have relatively high threshold voltages in order to avoid drain/source leakage. This leads to a lower charge to voltage factor (CVF) of the source follower transistor during read operations.

FIG. 2schematically illustrates a circuit200of an image sensor array comprising two pixel circuits201,201′ each having a single photodiode PD1and PD2respectively. For example, the photodiodes PD1and PD2correspond to pixels in adjacent rows of a same column of an image sensor array.

The photodiode PD1of pixel circuit201is coupled via a transfer transistor202to a sense node SN1, which is in turn coupled to the control node of a transistor M1. The sense node SN1is also coupled to a variable supply voltage VRST1via a reset transistor204controlled at its control node by a reset signal RST1. The voltage VRST1is for example variable between a high level of between 2.3 and 2.7 V, and a low level of between 0.3 and 0.5 V, such that dark current can be limited during the integration phase.

Similarly, the photodiode PD2of the other pixel circuit201′ is coupled via a transfer transistor202′ to a sense node SN2, which is in turn coupled to the control node of a transistor M2. The sensor node SN2is also coupled to a variable supply voltage VRST2via a reset transistor204′ controlled with this control node by a reset signal RST2.

The transfer transistors202,202′, reset transistors204,204′ and the transistors M1, M2are for example MOS transistors, although in alternative embodiments other transistor technologies could be used.

One of the main current nodes of the transistor M2, for example its sense node, is coupled to a column line Vx0, and one of the main current nodes of the transistor M1, for example its sense node, is coupled to another column line Vx1. The other main current nodes of the transistors M1and M2, which are for example their drain nodes, are coupled together.

By coupling the transistors M1and M2from neighboring pixel circuits in series with each other between the two column lines Vx0and Vx1, the role of each of these transistors can be either that of a source follower transistor or that of a read transistor. For example, the transistor M1operates as a source follower transistor during a read operation of the photodiode PD1, and as a read transistor during a read operation of the photodiode PD2. Conversely, the transistor M2operates as a source follower transistor during a read operation of the photodiode PD2, and as a read transistor during a read operation of the photodiode PD1.

When the photodiode PD1is to be read, the transistor M2is activated by a high voltage at the sense node SN2. In particular, the signal RST2and the voltage level VRST2are both high, such that the sense node SN2is coupled to a high voltage level. The voltage level VRST1is also at a high level, and the signal RST1is brought high for a short time to pre-charge the voltage level of the sense node SN1. Once the signal RST1has gone low again, the transfer signal TG1is brought high to transfer the accumulated charge from the photodiode PD1to the sense node SN1. The column line Vx1is coupled to a high voltage level VRTSF, such that the voltage at the sense node SN1is read out via the column line Vx0.

When the photodiode PD2is to be read, the transistor M1is activated by a high voltage at the sense node SN1. In particular, the signal RST1and the voltage level VRST1are both high, such that the sense node SN1is coupled to a high voltage level. The voltage level VRST2is also at a high level, and the signal RST2is brought high for a short time to pre-charge the voltage level of the sense node SN2. Once the signal RST2has gone low again, the transfer signal TG2is brought high to transfer the accumulated charge from the photodiode PD2to the sense node SN2. The column line Vx0is coupled to a high voltage level VRTSF, such that the voltage at the sense node SN2is read out via the column line Vx1.

It will be apparent to those skilled in the art that it would be equally possible, when reading the voltage from the sense node SN1, to couple the high voltage level VRTSF to the column line Vx0and read out the voltage from the sense node SN1via the column line Vx1. Similarly, it would be equally possible, when reading the voltage from the sense node SN2, to couple the high voltage level VRTSF to the column line Vx1and read out the voltage from the sense node SN2via the column line Vx0. However, the column line used for reading the sense node voltage, for example, changes for the sense nodes SN1and SN2, such that the output path is equivalent for both read operations.

In the embodiment ofFIG. 2, the pixel circuits201,201′ are adjacent pixel circuits, and the photodiodes PD1and PD2are part of a same column of the image sensor. However, it will be apparent to those skilled in the art that in alternative embodiments the pixels circuit may not be adjacent, and the photodiodes could be separated by one or more other photodiodes, and could be in different columns.

FIG. 3schematically illustrates a circuit300of an image sensor, similar to the circuit ofFIG. 2, but in which each pixel circuit comprises a pair of photodiodes. In particular, the sense node SN1is coupled to a photodiode PD1via a transfer transistor302controlled by a transfer signal TG1, and to a photodiode PD2via a further transfer transistor303controlled by a transfer signal TG2. Similarly, the sense node SN2is coupled to a photodiode PD3via a transfer transistor302′ controlled by a transfer signal TG3, and to a further photodiode PD4via a further transfer transistor303′ controlled by a transfer signal TG4.

For example, the photodiodes PD1to PD4correspond to pixels in four consecutive rows of a same column of an image sensor array. Alternatively, the photodiodes PD1to PD4could form a two-by-two grid of pixels.

In operation, the reading of the photodiodes PD1or PD2is for example achieved in the same way as reading of photodiode PD1as described in relation toFIG. 2, by asserting the corresponding transfer signal TG1or TG2. Similarly, the reading of the photodiodes PD3or PD4is for example achieved in the same way as reading of photodiode PD2as described in relation toFIG. 2, by asserting the corresponding transfer signal TG3or TG4.

While the pixel circuits ofFIG. 3each comprise two photodiodes, in alternative embodiments the sense nodes SN1and SN2could additionally be coupled via further transfer transistors to further photodiodes, each pixel circuit comprising for example four or more photodiodes.

FIG. 4illustrates one column400of an image sensor comprising the pixel circuits ofFIG. 2orFIG. 3according to an example embodiment. As illustrated, pairs of the transistors M1, M2of pairs of pixel circuits are coupled in series between the column lines Vx0and Vx1. Two such pairs of pixel circuits are illustrated inFIG. 4, and as represented by dots, there may be further intermediate pairs of pixel circuits coupled between the column lines Vx0and Vx1.

One end of the column line Vx0is coupled to a supply node402via a transistor404, which is for example an NMOS transistor, controlled at its control node by an enable signal ENVx0. Similarly, one end of the column line Vx1is coupled to the supply node402via a transistor406, which is for example an NMOS transistor, controlled at its control node by the inverse of the enable signal ENVx0. The supply node402is for example coupled to ground via a current source408, and to black and white clamps (B+W CLAMPS)410, which are in turn coupled to the supply voltage VRTSF. The white clamp is used to maintain an appropriate current level in the current mirror408in case of nearly white pixels, and the black clamp is used to avoid the dark sun effect.

The column line Vx0is also coupled to the supply voltage VRTSF via a transistor412, which is for example a PMOS transistor controlled by the enable signal ENVx0. The column line Vx1is also coupled to the supply voltage VRTSF via a transistor414, which is for example a PMOS transistor controlled by the inverse of the enable signal ENVx0. The supply voltage VRTSF is for example in the range 2.3 to 2.7 V.

The other end of the column line Vx0is for example coupled to an output node416of the column400via a transistor418, which is for example an NMOS transistor controlled by the enable signal ENVx0. Similarly, the other end of column line Vx1is coupled to the output node416via a transistor420, which is for example an NMOS transistor controlled by the inverse of the enable signal ENVx0. The output node416is coupled to an ADC (analog to digital converter)422, which provides the digital output value of the column on output lines424. A control circuit426for example provides the control signal ENVx0for controlling the various switches404,406,412,414,418,420.

In operation, when the enable signal ENVx0is high, the column line Vx1is coupled to the supply voltage VRTSF and the column line Vx0is coupled to the supply node402and to the output node416of the column. In this configuration, one of the sense nodes SN1, SN2of each pair of pixel circuits is read via the column line Vx0. When the enable signal ENVx0is low, the column line Vx0is coupled to the supply voltage VRTSF and the column line Vx1is coupled to the supply node402and to the output node416of the column. In this configuration, the other of the sense nodes SN1, SN2of each pair of pixel circuits is read via the column line Vx1.

FIG. 5is a timing diagram illustrating an example of the voltage at the sense node SN1and the signals RST2, VRST2, VRST1, RST1and TG2in the circuit ofFIG. 2during integration and read operations of the photodiode PD2. It will be apparent to those skilled in the art how the signals can be adapted for reading the photodiode PD1ofFIG. 2, or any of the photodiodes PD1to PD4ofFIG. 3.

An integration period tintof the photodiode PD2is triggered by a start integration operation (START INTEGRATION) which involves, while the reset signal RST2is asserted, bringing the signal VRST2high as shown by a rising edge502. The sense node SN2is thus brought to a high voltage. While the voltage VRST2is high, a high pulse504of the transfer gate signal TG2causes charge to be evacuated from the photodiode PD2. The integration period tintis then triggered by the falling edge of the high pulse504of the transfer gate signal TG2, and the voltage VRST2for example then goes low again.

A read operation (READ) of the photodiode involves applying a high voltage to the sense node SN1as shown by a rising edge505. For this, the voltage VRST1is brought high as shown by a rising edge506, while the reset voltage RST1is asserted. The voltage VRST2is also brought high while the reset signal RST2is asserted as shown by a rising edge508, in order to pre-charge the sense node SN1to a high voltage. The reset signal RST2is then brought low as shown by a falling edge510, and read operations R1and R2are for example performed before and after a high pulse512of the signal TG2, as indicated by arrows inFIG. 5. The rising edge of the pulse512ends the integration period tint. The reset signal RST2is then for example reasserted, as shown by a rising edge514, and the voltages VRST2and VRST1are for example brought low, as shown by falling edges516and518respectively.

As shown by dashed lines inFIG. 5, the levels of the voltage VRST1and the voltage at the sense node SN1during the start integration operation can be high or low, and are thus compatible with a read operation of the photodiode PD1during this operation. Indeed, such a read operation can occur while the signal VRST2is asserted.

FIG. 6illustrates an image sensor600comprising an array602of pixels arranged in columns and rows. In the example ofFIG. 6, the pixel array602comprises 16 columns and 12 rows of pixels, although in alternative embodiments there could be a different number of columns and rows. The rows in the array602are labeled to l1to lI. The rows of pixels forming odd columns of the array602have photodiodes that alternate between blue (shown by shaded squares) and green (shown by empty squares). The rows of pixels forming even columns of the array602have photodiodes that alternate between green and red (shown by striped squares). Thus two-by-two blocks of pixels comprise one red, one blue, and two green photodiodes.

A row decoder (ROW DECODER)604provides signals to the rows of the array, such as the reset signal RSTi, and the transfer gate signals TGi, for the corresponding row li. Column circuitry (COLUMN CIRCUITRY)606for example provides the supply voltages VRST and VRTSF to each pixel via one or the other of the column lines Vx0and Vx1, as described above. A column ADC array (COLUMN ADC ARRAY)608for example comprises ADCs (analog to digital converter), which convert the voltages read via the column lines to digital signals provided on output lines610.

In the case that the pixel array602comprises the pixel circuit200ofFIG. 2, the photodiodes PD1and PD2are for example adjacent to each other and in a same column. For example, in the odd columns, the photodiodes PD1and PD2for example correspond to adjacent blue and green photodiodes, and in the even columns, the photodiodes PD1and PD2for example correspond to adjacent green and red photodiodes.

Alternatively, in the case that the pixel array602comprises the pixel circuits ofFIG. 3, the photodiodes PD1to PD4for example correspond to photodiodes in four consecutive rows of a same column of the array. In such a case, different operations should not be performed at the same time on each of the photodiodes coupled to a same sense node. Examples of the timing of operations in the case of video capture using a rolling shutter will now be described with reference toFIGS. 7A and 7B.

FIG. 7Ais a table illustrating an example of operations performed during line cycles in the pixel array ofFIG. 6during video capture that is performed using a rolling shutter. Start integration (SI) operations are for example performed during consecutive cycles on consecutive rows of the array, starting with a first row liof the array in a cycle1, and so on. The read operation is for example performed for each line two cycles after the start integration operation, such that the photodiodes of consecutive lines do not have start integration and read operations occurring in the same cycle.

FIG. 7Bis a table illustrating an example of operations performed during line cycles in the pixel array ofFIG. 6according to an alternative embodiment in which the integration period is reduced to a single cycle by performing the start integration operations on consecutive cycles in the order of rows li, li+2, li+1, li+3, li+4, li+6, li+5etc. In an alternative embodiment, a similar result could be achieved by positioning the photodiodes PD1, PD2, PD3and PD4of the pixel circuit ofFIG. 3in rows li, li+2, li+1and li+3respectively of the pixel array.

FIG. 8illustrates an electronic device800comprising the image sensor (IMAGE CAPTURE DEVICE)600ofFIG. 6. The electronic device800further comprises a processing device (P)802coupled to the image sensor, and for example comprising one or more processors. A memory (MEM)804is coupled to the processing device802, and for example receives and stores images captured by the image sensor600. A user interface (USER INTERFACE)806is also for example coupled to the processing device804, and for example comprises a display, touch screen, and/or other user input device.

The electronic device800is for example a digital camera, tablet computer, mobile telephone or smart phone, or other portable electronics devices comprising an image sensor.

An advantage of the embodiments described herein is that, within a same column of an image sensor, a read operation can be performed in one pixel circuit at the same time as a reset operation in another pixel circuit. This leads to a relatively fast read-out operation of the pixels of the image sensor. Furthermore, advantageously, the transistors M1and M2of the pixel circuits that are coupled in series may have a relatively low threshold voltage, and a relatively high charge to voltage factor (CVF) can therefore be achieved.

A further advantage is that, with respect to the circuitry ofFIG. 1, there is no longer a supply voltage VDDsupplied to each pixel circuit. Therefore, the use of two column lines Vx0, Vx1rather than a single column line does not increase the number of supply lines with respect to the embodiment ofFIG. 1.

Having thus described at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art.

For example, it will be apparent to those skilled in the art that, while embodiments have been described in which the transistors M1and M2coupled in series are of adjacent pixel circuits of a same column, in alternative embodiments the pixels circuits could be separated by one or more intermediate pixel circuits, and they are not necessarily in the same column.

Furthermore, it will be apparent to those skilled in the art that the various features described in relation to the various embodiments could be combined, in alternative embodiments, in any combination.