Nonvolatile memory device comprising one-time-programmable lock bit register

A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2010-0021897, filed on Mar. 11, 2010, in the Korean Intellectual Property Office (KIPO), the entirety of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

Embodiments of the inventive concept relate generally to semiconductor memory devices. More particularly, embodiments of the inventive concept relate to nonvolatile memory devices comprising a one-time-programmable lock bit register.

Semiconductor memory devices can be roughly divided into two categories according to whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power.

Examples of volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous DRAM (SDRAM). Examples of nonvolatile memory devices include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable PROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM).

Among nonvolatile memory devices, flash memory has achieved increasing popularity in recent years due to a variety of attractive features, such as relatively high storage capacity and performance, and relatively low power consumption and cost. Recently, however, PRAM has been proposed as a potential alternative to flash memory. PRAM, also known as an Ovonic Unified Memory (OUM), is a type of variable-resistance memory.

A PRAM typically comprises a one-time-programmable (OTP) block that stores security data such as a serial number, information regarding a vendor, and a date of manufacture. The security data is sensitive information and must be secured against external interference such as unwanted tampering or reprogramming. However, unlike many flash memory devices, conventional PRAMs do not have a specific memory block designed for one time programming and subsequent data protection. As a result, security data stored in an OTP block of a conventional PRAM may be vulnerable to external interference.

SUMMARY OF THE INVENTION

Embodiments of the inventive concept provide nonvolatile memory devices comprising an OTP lock bit register for protecting an OTP memory against unauthorized data manipulation. Embodiments of the inventive concept also provide electronic systems incorporating such nonvolatile memory devices.

According to one embodiment of the inventive concept, a nonvolatile memory device comprises a variable-resistance memory cell array comprising a memory block that stores protected data, and a register that stores lock state information indicating whether the protected data is changeable, wherein the register comprises a variable-resistance memory cell and an initial value of the lock state information is set to a program protection state.

In certain embodiments, the nonvolatile memory device further comprises a mode controller that changes the protected data stored in the memory block in response to the lock state information.

In certain embodiments, the mode controller causes the register to store program unprotection information in response to a hidden code received from an external source.

In certain embodiments, the nonvolatile memory device further comprises an address decoder that selects the memory block, wherein the mode controller causes the address decoder select the memory block where the register stores program unprotection information.

In certain embodiments, the nonvolatile memory device further comprises a write driver that programs the memory block, wherein the mode controller causes the write driver to program the memory block where the register stores program unprotection information.

In certain embodiments, the lock state information comprises program protection information or program unprotection information.

In certain embodiments, the variable-resistance memory cell array comprises phase-change memory cells.

In certain embodiments, the variable-resistance memory cell comprises a phase-change memory cell and the program protection state corresponds to an amorphous state of a phase-change material in the phase-change memory cell.

According to another embodiment of the inventive concept, a nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that stores protected data, and a register that stores OTP lock state information indicating whether the protected data is changeable, wherein the register comprises by an E-fuse device and an initial value of the OTP lock state information is set to a program unprotection state.

In certain embodiments, the nonvolatile memory device further comprises an OTP mode controller that changes the protected data stored in the OTP block in response to the OTP lock state information.

In certain embodiments, the OTP mode controller causes the register to store program protection information in response to a command from an external source.

In certain embodiments, the nonvolatile memory device further comprises an address decoder that selects the OTP block, wherein the OTP mode controller causes the address decoder to select the OTP block where the register stores the program unprotection information.

In certain embodiments, the nonvolatile memory device further comprises a write driver that programs the OTP block, wherein the OTP mode controller causes the write driver to program the OTP block where the register stores the program unprotection information.

In certain embodiments, the OTP lock state information comprises program protection information or program unprotection information.

In certain embodiments, the variable-resistance memory cell array comprises phase-change memory cells.

According to another embodiment of the inventive concept, a method is provided for operating a nonvolatile memory device comprising a variable-resistance memory cell array comprising a memory block that stores protected data, and a variable-resistance memory cell that stores lock state information indicating whether the protected data is changeable. The method comprises initializing the variable-resistance memory cell to a program protection state, receiving a security code, in response to the security code, changing the variable-resistance memory cell to a program unprotection state, and while the variable-resistance memory cell is in the program unprotection state, programming the memory block. The method further comprises receiving a data protection command, and in response to the protection command, changing the variable-resistance memory cell to the program protection state.

DETAILED DESCRIPTION

Embodiments of the inventive concept are described below with reference to the accompanying drawings. These embodiments are presented as teaching examples and should not be construed to limit the scope of the inventive concept.

In general, embodiments of the inventive concept relate to nonvolatile memory devices comprising an OTP block. The OTP block is a memory block that can be used to store security data regarding the nonvolatile memory device, such as a serial number and a date of manufacture.

The OTP block has a similar structure to other memory blocks that can be read and written multiple times. However, to prevent damage and leakage of the security data, the OTP block is prevented from being written more than once. To determine whether the OTP block has been written once, some nonvolatile memory devices perform a read operation on the OTP block. However, such a read operation can degrade the performance of the nonvolatile memory device.

FIG. 1is a block diagram of a nonvolatile memory device according to an embodiment of the inventive concept.

Referring toFIG. 1, the nonvolatile memory device comprises an OTP cell array100, a normal cell array110, a bitline selection circuit120, a sense amplifier130, a data input-output (I/O) buffer140, an address decoder200, an OTP controller300, and a write driver600. OTP controller300comprises an OTP mode controller400and an OTP lock bit register500.

The nonvolatile memory device prohibits a program operation of OTP cell array100in response to program protection information stored in OTP lock bit register500and allows the program operation in response to program unprotection information stored in OTP lock bit register500.

OTP cell array100and normal cell array110each comprise a plurality of memory cells. Each of the memory cells comprises a variable-resistance element GST and a selection element MT. Selection element MT typically comprises a transistor or a diode. Each memory cell is connected to one of wordlines WL0through WLn or WLn′ and one of bitlines BL0through BLm. OTP cell array100is connected to wordline WLn′. A structure of OTP cell array100and normal cell array110will be explained in further detail with reference toFIGS. 2 and 3.

OTP cell array100stores security data. The security data typically comprises information regarding the nonvolatile memory device, such as a manufacturer name, serial number, and date of manufacture. OTP cell array100must be protected from unauthorized manipulation. Accordingly, in a program operation, OTP cell array100refers to program protection information stored in OTP lock bit register500to determine whether access is allowed.

A conventional OTP cell array allows a one-time program operation. However, the nonvolatile memory device ofFIG. 1can permit multiple program operations to OTP cell array100by referring to program protection information.

Address decoder200receives an address ADDR and an OTP_MODE signal as an input. Address ADDR is divided into a row address for selecting one of wordlines WL0through WLn or WLn′ and a column address for selecting one of bitlines BL0through BLm. The OTP_MODE signal is a signal to select OTP cell array100. In other words, where OTP_MODE signal is enabled, wordline WLn′ of OTP cell array100of is selected.

Bitline selection circuit120connects data line DL to a corresponding one of bitlines BL0through BLm in response to a bitline selection signal Yi from address decoder200. Bitline selection circuit120typically comprises one or more NMOS transistors.

During a read operation, sense amplifier130detects a difference between a sensing line SL voltage and a reference voltage Vref and identifies data stored in selected memory cells according to the detected difference. Reference voltage Vref is provided by a reference voltage generation circuit. Data I/O buffer140then outputs data DATA received from sense amplifier130to an external destination.

OTP controller300controls program operations of OTP cell array100. During a program operation of OTP cell array100, OTP controller300controls address decoder200and write driver600.

OTP mode controller400generates OTP_MODE signal in response to an external command CMD and data stored in OTP lock bit register500. As indicated above, the OTP_MODE signal is used to select OTP cell array100. Accordingly, address decoder200selects wordline WLn′ connected to OTP cell array100in response to the OTP_MODE signal.

OTP mode controller400changes data stored in OTP lock bit register500in response to external command CMD. OTP mode controller400stores the program protection information in OTP lock bit register500to protect data stored in OTP cell array100. On the other hand, OTP mode controller400stores the program unprotection information in OTP lock bit register500to allow data stored in OTP cell array100to be changed.

OTP mode controller400refers to data stored in OTP lock bit register500. Where the program protection information is stored in OTP lock bit register500, OTP mode controller400does not generate the OTP_MODE signal. On the other hand, where the program unprotection information is stored in OTP lock bit register500, OTP mode controller400generates the OTP_MODE signal.

Where the program protection information is stored in OTP lock bit register500, OTP mode controller400generates an OTP protection signal OTP_PROT. OTP protection signal OTP_PROT is a signal for restricting a program operation to OTP cell array100. OTP protection signal OTP_PROT is provided to write driver600. On the other hand, where the program unprotection information is stored in OTP lock bit register500, OTP mode controller400does not generate OTP protection signal OTP_PROT.

Write driver600supplies a program current to selected memory cells during program operations. The program current can take the form of a set current or a reset current. The set current places a variable-resistance material in a set state, and the reset current places the variable-resistance material in a reset state.

Write driver600receives data DATA through data I/O buffer140. Write driver600supplies the set current or the reset current to data line DL in response to data DATA. For example, write driver600can provide the reset current in response to data ‘1’, and it can provide the set current in response to data ‘0’.

Write driver600shuts off the set current or the reset current in response to OTP protection signal OTP_PROT. Accordingly, the nonvolatile memory device blocks a program operation of OTP cell array100in response to OTP protection signal OTP_PROT.

As indicated by the foregoing, the nonvolatile memory device ofFIG. 1stores program protection information or program unprotection information in OTP lock bit register500and prohibits or conducts a program operation on OTP cell array100according to the stored information. Consequently, security data can be stored securely and changed as need arises.

Various examples of nonvolatile memory devices comprising phase-change one-time-programmable memory cells are disclosed in U.S. Patent Publication No. 2007/0133269, the disclosure of which is hereby incorporated by reference in its entirety.

FIG. 2is a circuit diagram illustrating an example of a variable-resistance memory cell. OTP lock bit register500can be implemented by a variable-resistance memory cell such as that illustrated inFIG. 2.

Referring toFIG. 2, a variable-resistance memory cell10comprises a variable-resistance element GST and a selection element MT. Variable-resistance element GST is connected to a bitline BL, and selection element MT connects variable-resistance element GST to ground. A gate of selection element MT is connected to a wordline WL.

Selection element MT turns on in response to a voltage applied to wordline WL. Where selection element MT is turned on, variable-resistance element GST receives a current through bitline BL.

Variable-resistance element GST comprises a phase change material. The phase change material typically comprises Germanium-Antimony-Tellurium (GST), which changes its resistance in response to heat. The phase change material can be placed in two different stable states in response to temperature changes. The two stable states are a crystalline state and an amorphous state.

The phase change material changes to the crystalline state or the amorphous state in response to current supplied through bitline BL. The variable-resistance memory device programs data using this characteristic of the phase change material. Examples of variable-resistance memory cells using such a phase change material are described in U.S. Patent Publication No. 2007/0133269.

FIG. 3is a graph illustrating characteristics of the variable-resistance memory cell ofFIG. 2. InFIG. 3, a reference numeral “1” represents temperature conditions corresponding to the amorphous state of the phase change material, and a reference numeral “2” represents temperature conditions corresponding to the crystalline state of the phase change material.

Referring toFIG. 3, the phase change material is changed to the amorphous state by heating it a temperature higher than a melting temperature Tm and then quenching it after a time T1. The amorphous state is usually called a reset state and the reset state stores data ‘1’.

On the other hand, the phase change material is changed to the crystalline state by heating it to a temperature between crystallization temperature Tc and melting temperature Tm during and then slowly cooling it after a time T2. The crystalline state is usually called a set state and the set state stores data ‘0’.

The resistance of the variable-resistance memory cell depends on amorphous volume of the phase change material. The resistance of the memory cell is high when it is in the amorphous state and low when it is in the crystalline state.

As indicated by the foregoing, the variable-resistance memory cell can be reset by heat. Accordingly, an unauthorized person could potentially reset OTP lock bit register500by applying heat from an external source. Consequently, the unauthorized person could cause OTP lock bit register500to store program unprotection information. It is desirable, however, for OTP lock bit register500to maintain the program protection information even when heat is applied from an external source.

Accordingly, in certain embodiments of the inventive concept, the reset state is defined as program protection information and the set state is defined as program unprotection information. As a result, OTP lock bit register500maintains the program protection information even if heat is applied from an external source.

FIG. 4is a flowchart illustrating a method of modifying data stored in an OTP lock bit register comprising a variable-resistance memory cell. The method will be described with reference to the variable-resistance memory device ofFIG. 1. In the description that follows, example method steps will be indicated by parentheses (SXXX).

Referring toFIG. 4, OTP lock bit register500stores program protection information by default (S110). In a program protection state, data stored in an OTP block of OTP cell array100cannot be changed.

A security code (also referred to as a hidden code) is provided to a vendor desiring to write data to the OTP block. The vendor can cause OTP lock bit register500to store program unprotection information by entering the hidden code (S120). The vendor typically applies the hidden code to OTP mode controller400. OTP mode controller400then instructs OTP lock bit register500to store program unprotection information in response to the hidden code (S130).

OTP mode controller400applies the OTP_MODE signal to address decoder200to select the OTP block. Meanwhile, OTP mode controller400does not apply the OTP_PROT signal to write driver600so that write driver600can perform the program operation on the OTP block (S140).

After the program operation of the OTP block, a protection command is received from an external source (S150). In response to the protection command, OTP mode controller400instructs OTP lock bit register500to store the program protection information (S160). As a result, data stored in OTP cell array100is protected.

Where an unauthorized access attempt is made to OTP lock bit register500(S170), the data stored in OTP lock bit register500indicates protection state (S110). Accordingly, the unauthorized access attempt will be rejected.

FIG. 5is a circuit diagram illustrating an E-fuse circuit comprising a latch type current-sense amplifier. In certain embodiments of the inventive concept, OTP lock bit register500is implemented using the E-fuse circuit ofFIG. 5.

Referring toFIG. 5, a first node of an E-fuse F1and a first node of a resistor R1are connected to an external supply voltage VCC. A second node of E-fuse F1is connected to a cutting driver transistor MN1. Cutting driver transistor MN1is controlled by a cutting control signal EFUSE_CUT.

Transistors M1, M2, M3, and M4form a complementary latch. The complementary latch places nodes A and B in opposite states. At initial power-up, node A and node B are in random states due to a parasitic load.

Transistors M5, M6, M3, and M4form a current-sense amplifier. Transistors M5and M6are controlled by an initial signal INIT_SET. Initial signal INIT_SET can be provided by an output signal of a mode register set MRS in a semiconductor memory device.

To determine initial voltages of node A and node B, a resistance of resistor R1is set to a value larger than a resistance of E-fuse F1. A small current difference occurs in nodes A and B according to the resistance difference between E-fuse F1and resistor R1. In addition, a small voltage difference will occur between node A and node B.

As initial signal INIT_SET transitions from logical “high” to logical “low”, the complementary latch formed by transistors M1, M2, M3, and M4amplifies a small voltage difference between node A and node B.

Next, where cutting control signal EFUSE_CUT transitions to logical “high”, cutting driver transistor MN1is turned on. Where cutting driver transistor MN1is turned on, a significant current flows therethrough, and the significant current cuts E-fuse F1. As a result, the resistance of E-fuse F1exceeds that of resistor R1.

Where initial signal INIT_SET transitions to logical “high”, the current-sense amplifier operates. The current-sense amplifier generates a small voltage difference between node A and node B. When initial signal INIT_SET transitions to logical “low”, the complementary latch reverses the voltages of node A and node B. In this way, the complementary latch stores information indicating that E-fuse F1is cut. Signals needed to drive the E-fuse can be provided by OTP mode controller400.

FIG. 6is a flowchart illustrating a method of modifying data stored in an OTP lock bit register comprising an E-fuse.

Referring toFIG. 6, OTP lock bit register500stores program unprotection information by default (S210). In a program unprotection state, data in the OTP block can be changed.

Because the default state is an unprotected state, hidden code is unnecessary. OTP mode controller400applies the OTP_MODE signal to address decoder200to select the OTP block. In addition, OTP mode controller400does not apply the OTP_PROT signal to write driver600(or applies deactivated OTP_PROT signal to write driver600). Thus, write driver600performs a program operation on the OTP block (S220).

After the program operation for the OTP block, E-fuse F1is cut (S230). A vendor typically cuts E-fuse F1by applying a command to OTP mode controller400. As a consequence of cutting E-fuse F1, OTP lock bit register500stores program protection information (S240). Therefore, data stored in the OTP block is protected.

As indicated by the foregoing, by using E-fuse F1for OTP lock bit register500, the program protection information is not changed to program unprotection information by external manipulation. An E-fuse has a characteristic that is irreversible. Therefore, data stored in the OTP block may be protected. Accordingly, the security and reliability of the nonvolatile memory device are improved.

In the embodiment ofFIG. 6, the E-fuse circuit comprises a latch type current-sense amplifier. However, the E-fuse circuit can be implemented in other forms.

FIG. 7is a block diagram illustrating a computational system700comprising one or more integrated circuit devices each comprising at least one nonvolatile memory device according to an embodiment of the inventive concept.

Referring toFIG. 7, computational system700comprises a processor710, a main memory760, an input device730, a memory controller720, a nonvolatile memory750, and an output device740connected via a system bus. One or both of main memory760and nonvolatile memory750comprises a plurality of memory devices. In certain embodiments, the plurality of memory devices is arranged on a memory card, such as a printed circuit board physically mounting and operatively connecting the plurality of memory devices.

Computational system700receives data from an external source through input device730. The received data can comprise, for instance, a command from a user or multi-media data. The received data is stored in nonvolatile memory750or main memory760.

Results generated by processor710are stored in nonvolatile memory750or main memory760. Output device740outputs the data stored in nonvolatile memory750or main memory760. Output device740outputs digital data in a human-perceivable form. Output device740can comprise, for instance, a display or speaker. The method ofFIG. 4or6can be applied to nonvolatile memory750. As the security of nonvolatile memory750improves, the security of the computational system improves accordingly.

Nonvolatile memory750or memory controller720can be mounted in various types of packages. Examples of these packages or package types include package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), and wafer-level processed stack package (WSP).

In some embodiments, computational system700is a portable device. In such embodiments, computational system700can comprise a portable battery.

Computational system700can take a variety of alternative forms, such as a mobile phone, an MP3 player, a navigation system, a solid state disk (SSD), or a household appliance, to name but a few.

FIG. 8is a block diagram illustrating a memory system according to an embodiment of the inventive concept.

Referring toFIG. 8, the memory system comprises a memory3010connected to a memory controller3020. Memory3010can take the form of one of the semiconductor devices described above.

Memory controller3020supplies input signals for controlling the operation of memory3010. For example, memory controller3020supplies command and address signals to control memory3010. Memory controller3020comprises a memory interface, a host interface, an error detection/correction (ECC) circuit, a central processing unit (CPU), and a buffer memory.

The memory interface provides data transmitted from the buffer memory to memory3010and transmits data read out of memory3010to the buffer memory. The memory interface provides commands and addresses transmitted from an external host to memory3010.

The host interface communicates with the external host using a protocol such as universal serial bus (USB), small computer system interface (SCSI), peripheral component interconnect (PCI) express, advanced technology attachment (ATA), parallel ATA (PATA), serial ATA (SATA), or serial attached SCSI (SAS).

The ECC circuit generates a parity bit using data transmitted to memory3010. The generated parity bit is stored in a specific area of memory3010, together with data. The ECC circuit detects errors in data read out of memory3010. Where the detected errors are within a correctable range, the ECC circuit corrects the detected errors.

The CPU analyzes input signals received from the external host and processes the input signals. The CPU controls the external host or memory3010through the host interface or the memory interface. The CPU controls write, read, and erase operations according to firmware used to drive memory3010.

The buffer memory temporarily stores write data provided from the external host or data read out of memory3010. The buffer memory also stores metadata or cache data to be stored in memory3010. In an unexpected power outage, metadata or cache data stored in the buffer memory is stored in memory3010. The buffer memory typically comprises a DRAM or an SRAM.

FIG. 9is a block diagram illustrating a memory card3130according to an embodiment of the inventive concept. The embodiment ofFIG. 9is the same as the embodiment ofFIG. 8, except that memory3010and memory controller3020are incorporated in memory card3130.

Memory card3130can take a variety of forms, such as a flash memory card or another type of card meeting an industry standard for use with consumer electronics devices such as digital cameras, personal computers, etc. Memory controller3020controls memory3010based on controls signals received by memory card3130from an external device.

FIG. 10is a block diagram illustrating memory3010connected to a host system3210.

Host system3210can comprise a processing system such as a personal computer, or a digital camera. Host system3210may use memory3010as a removable storage medium. Host system3210supplies input signals for controlling operation of memory3010. For example, host system3210can supply command and address signals to memory3010.

FIG. 11is a block diagram illustrating a system comprising memory card3130connected to host system3210. Host system3210applies control signals to memory card3130, and memory controller3020controls the operation of memory3010in response to the control signals.

FIG. 12is a block diagram illustrating a computer system3410comprising CPU3120connected to memory3010. Computer system3410can take a variety of forms, such as a personal computer or a personal data assistant. Memory3010can be directly connected to CPU3120, or intervening components may be present. For simplicity,FIG. 11does not illustrate all of the features that can be included within computer system3410.

FIG. 13is a block diagram illustrating a portable computing system comprising a memory according to an embodiment of the inventive concept.

Referring toFIG. 13, the portable computing system comprises memory3010, which can take the form of one of the semiconductor memory devices described above. In this and other embodiments, memory3010can comprise one or more integrated circuit dies each comprising a memory array that operates in conjunction with a method such as those described in relation toFIGS. 4 and 6. These IC dies can be separate, stand alone memory devices arranged in modules such as conventional DRAM modules, or they can be integrated with other on-chip functionalities. In certain embodiments, memory3010can be part of an I/O processor or a microcontroller.

The portable computing system ofFIG. 13can take any of several forms, such as a portable notebook computer, a digital still or video camera, a personal digital assistant, a mobile hand-held telephone unit, a navigation device, a global positioning system (GPS) system, or an audio and/or video player. Memory3010can also be incorporated in a variety of non-portable devices, such as large network servers or other computing devices that can benefit from nonvolatile memory devices.

The portable computing system ofFIG. 13comprises a processor/CPU3510that uses memory3010as program memory to store code and data for its execution. Alternatively, memory3010can be used as a mass storage device for nonvolatile storage of code and data. The portable computing system can communicate with other devices, such as a personal computer or a network of computers, via an I/O interface3515. I/O interface3515can provide access to a computer peripheral bus, a high speed digital communication transmission line, or an antenna for unguided transmissions. Data communication between processor/CPU3510and memory3010, as well as between processor/CPU3510and I/O interface3515can be accomplished using a bus3500.

In various alternative embodiments, memory3010can be replaced with memory card3130ofFIG. 9, and communication with processor/CPU3510can be conducted via memory controller3020. Furthermore, I/O interface3515can communicate with memory3010via memory controller3020or directly with memory3010if memory controller3020is not present. In portable applications, the above-described features are typically powered by a battery3520via a power supply bus3525.

FIG. 14is a block diagram illustrating a memory system3700according to an embodiment of the inventive concept.

Referring toFIG. 14, memory system3700comprises memory3010, memory controller3020, and host system3210. Memory3010comprises a resistive memory device configured to store single-bit data or multi-bit data in each memory cell. A memory cell that stores single-bit data is called a “single-bit cell”, and a memory cell that stores multi-bit data is called a “multi-bit cell”. A method of operating memory controller3020is described below with respect to an example where memory cells of memory3010store multi-bit data.

Memory controller3020is configured to control memory3010in response to an access request from host system3210. Memory controller3020maps a logical address of input data to a first physical address corresponding to first order data (e.g., least significant bit (LSB) data) of multi-bit cells in memory3010. After mapping the logical address of program data to the first physical address of the first bit, memory controller3020sequentially maps a logical address of program data to a second physical address corresponding to second order data (e.g., most significant bit (MSB) data) of multi-bit cells in memory3010.

The mapped first and second physical addresses are provided to memory3010. Memory3010sequentially writes program data into second bits of multi-bit cells in memory3010after first writing the program data into first bits of multi-bit cells in memory3010in sequence of the mapped first and second physical addresses.

Memory controller3020comprises a control block3023and a memory3025. One or more translation layers TL1through TLn are stored in memory3025. When an access is requested from host system3210, control block3023maps a logical address of program data to a physical address of a multi-bit memory cell using translation layers TL1through TLn.

Memory controller3020determines whether an access request from host system3210is associated with an area of memory3010using translation layers TL1through TLn. Memory controller3020selects one of translation layers TL1through TLn according to a result of the determination and manages mapping information of memory3010according to a selected translation layer.

To write a small amount of data, control block3023selects a translation layer based on page mapping and performs a write operation by page unit. According to the selected translation layer, a logical address of program data is first mapped to first physical addresses by a unit of page before being mapped to second physical addresses. Consequently, memory3010performs a write operation by a page unit.

To write a large amount of data, control block3023selects a translation layer based on block mapping and performs a write operation by block unit. According to the selected translation layer, a logical address of program data is first mapped to first physical addresses by block unit before being mapped to second physical addresses. Consequently, memory3010performs a write operation by block unit. This approach can be applied to a whole area of the memory cell array in memory3010without performing a write operation by page unit or block unit.

In certain embodiments, a semiconductor device can be used as a storage class memory. The storage class memory can be used for both data storage and program code storage. In various embodiments, memory devices such as PRAM, FeRAM, and MRAM can be used for a variety of purposes, such as general data storage, as replacements for conventional flash memory, and as main memory applications such as SRAM.

FIG. 15is a block diagram illustrating a memory system4100according to an embodiment of the inventive concept. In this embodiment, an SCM is used instead of a flash memory. Memory system4100comprises a CPU4110, an SDRAM4120, and an SCM4130used instead of a flash memory.

In memory system4100, data access speed of SCM4130is higher than that of a flash memory. For example, in a PC environment where CPU4110runs at 4 GHz, data access speed of a PRAM, which is a type of SCM4130, is about 32 times higher than that of a flash memory. Thus, memory system4100equipped with SCM4130can achieve higher-speed access than a memory system equipped with a flash memory.

FIG. 16is a block diagram illustrating a memory system4200according to an embodiment of the inventive concept. In the embodiment ofFIG. 16, an SCM is used instead of an SDRAM.

Referring toFIG. 16, memory system4200comprises a CPU4210, an SCM4220, and a flash memory4230. SCM4130is used as a main memory instead of an SDRAM.

In memory system4200, power dissipation of SCM4220is lower than that of an SDRAM. Energy dissipation for a main memory in a computer system may account for up to 40 percent of total energy use. Accordingly, improvements in the energy efficiency of main memory can significantly lower power consumption of a computer system. Incorporation of an SCM can reduce energy dissipation requirements by an average of about 53 percent, and reduce energy dissipation caused by power leakage by an average of about 73 percent. As a result, memory system4200equipped with SCM4220allows power dissipation to be reduced more than a memory system equipped with an SDRAM.

FIG. 17is a block diagram illustrating a memory system4300according to an embodiment of the inventive concept. In the embodiment ofFIG. 17, an SCM is used to replace an SDRAM and a flash memory.

Referring toFIG. 17, memory system4300comprises a CPU4310and an SCM4320. SCM4320is used as a main memory instated of an SDRAM and as a data storage memory instead of a flash memory. Memory system4300provides relatively efficient data access speed, power consumption, space utilization, and cost.

FIG. 18is a block diagram illustrating a mobile system5000comprising a variable-resistance memory device according to an embodiment of the inventive concept.

Referring toFIG. 18, memory system5000comprises a chipset5100, a mass storage5200, an LPDDR2-DRAM5300, and an LPDDR2N-PRAM5400. Mass storage5200is a high-capacity storage such as a hard disk drive (HDD) or a flash memory. LPDDR2-DRAM5300is a low-power DDR2 DRAM, and LPDDR2N-PRAM5400is a low-power DDR2 nonvolatile PRAM acting as a variable-resistance memory device.

DRAM can consume a large amount of standby current because it performs a refresh operation even in a standby state. Increasing the standby current causes power of a battery to be consumed, reducing the amount of time that mobile system5000can go without recharging. A variable-resistance memory device (e.g., PRAM) according to certain embodiments of the inventive concept does not need to perform a refresh operation. Therefore, if the variable-resistance memory device is used instead of a DRAM or together with a DRAM, mobile system5000can reduce power consumption.

FIG. 19is a block diagram illustrating a hierarchical structure of a computer system6000comprising a variable-resistance memory device according to an embodiment of the inventive concept.

Referring toFIG. 19, computer system6000comprises a CPU cache memory in an upper layer, a DRAM and a phase change memory (PCM) in a middle layer, and a hard disk or a flash memory in a lower layer. In the hierarchical structure illustrated inFIG. 19, data access speed is highest in the upper layer and lowest in the lower layer. In some embodiments, a variable-resistance memory device can be substituted for a DRAM or used as a memory in the middle layer together with a DRAM, within computer system6000.

The CPU cache memory in the upper layer can comprise a level 1 (L1) memory and a level 2 (L2) memory. The L1 memory and the L2 memory are arranged in a cache memory layer inside computer system5000. In a memory region of the middle layer, a DRAM6210and a PCM6200can be used together. For example, a 256-megabyte DRAM6210and a 1-gigabyte PCM6220can be installed a computer system after being merged into a module.

DRAM6210can function as a main memory for processing data from a CPU at high speed and PCM6220can function to store the data. Similar to an external peripheral device, a lower layer of a hard disk drive or a flash memory device6300may store data through a predetermined interface such as ATA/SATA or communicate with a main memory or the CPU.

A variable-resistance memory device according to certain embodiments of the inventive concept can be incorporated in a server-oriented SSD. For example, U.S. Patent Publications Nos. 2008/0256292, 2008/0256183, and 2008/0168304 variously disclose a solid-state storage comprising a PRAM, a flash memory, an MRAM, an NRAM, and DRAM, as well as a solid-state storage device comprising a solid-state storage controller and a solid-state storage. U.S. Patent Publications Nos. 2008/0256292, 2008/0256183, and 2008/0168304 disclosed a solid-state memory and controller improving the speed of a high-speed interface as well as a redundant array of independent drivers (RAID) in a solid-sate device. The respective disclosures of these U.S. patent publications are hereby incorporated by reference in their entirety.

The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.