Power supply circuit including stably operating voltage regulators

A power supply circuit is constructed by a step-up circuit for receiving an input DC voltage to generate a plurality of output DC voltages, and a plurality of voltage regulators, each powered by two voltages selected from a combination of the output DC voltages and the ground voltage. The difference between the two voltages of each of the voltage regulators are substantially the same, to stably operate the voltage regulators.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a power supply circuit used in a liquid crystal display (LCD) apparatus, for example.

2. Description of the Related Art

Generally, in an LCD apparatus including an LCD panel, a data line (signal line) driver circuit and a gate line (scan line) driver circuit, a power supply circuit is provided to supply regulated voltages to the data line driver circuit and the gate line driver circuit.

In the data line driver circuit, the regulated voltage supplied thereto does not need to be high; however, a high current drive ability is required. Therefore, the regulated voltage is derived from 2·VDD, for example, where VDDis the power supply voltage. On the other hand, in the gate line driver circuit, the regulated voltages supplied thereto do not require a high current drive ability; however, the regulated voltages are a sufficiently high voltage and a sufficiently low voltage. Therefore, the regulated voltages are derived from 4·VDDand (−2)·VDD, for example. This will be explained later in detail.

A prior art power supply circuit is constructed by a step-up circuit for receiving a power supply voltage VDDto generate a 4-multiple step-up voltage 4·VDD, a 2-multiple step-up voltage 2·VDDand a (−2)-multiple step-up voltage (−2)·VDD, a first voltage regulator powered by the 4-multiple step-up voltage and the ground voltage to generate a first regulated voltage, a second voltage regulator powered by the 2-multiple step-up voltage and the ground voltage to generate a second regulated voltage, and a third voltage regulator powered by the ground voltage and the (−2)-multiple step-up voltage. This also will be explained later in detail.

In the above-described prior art power supply circuit, however, the difference between the two power voltages of the first voltage regulator is 4·VDD, the difference between the two power voltages of the second voltage regulator is 2·VDD, and the difference between the two power voltages of the third voltage regulator is 2·VDD. As a result, all of the first, second and third voltage regulators are not always stably operated, or the reliability of some of the voltage regulators may deteriorate.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a power supply circuit capable of stably operating voltage regulators thereof and improving the reliability.

According to the present invention, a power supply circuit is constructed by a step-up circuit for receiving an input DC voltage to generate a plurality of output DC voltages, and a plurality of voltage regulators, each powered by two voltages selected from a combination of the output DC voltages and the ground voltage. The difference between the two voltages of each of the voltage regulators are substantially the same, to stably operate the voltage regulators.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before the description of the preferred embodiments, a prior art power supply circuit will be explained with reference toFIGS. 1,2,3,4,5and6.

InFIG. 1, which illustrates a conventional LCD apparatus to which a prior art power supply circuit is applied, reference numeral100designates a glass substrate of an LCD panel101having 240×320 pixels (=32 240×3×320 dots), where one pixel is formed by three color dots, for example. In this case, the LCD panel101includes 720 (=240×3) data lines (or signal lines) DL and 240 gate lines (or scan lines) GL. One pixel, which is located between the data lines DL and the gate lines CL, is constructed by one thin film transistor (TFT) Q, one pixel capacitor C and one liquid crystal cell CC. A common voltage VCOM is applied to the pixel capacitor C and the liquid crystal cell CC.

A data line driver circuit102is provided to drive the 720 data lines DL, while a gate driver circuit103is provided to drive the 320 gate lines GL.

Also, a power supply circuit104supplies a regulated voltage VR2to the data line driver circuit102and supplies regulated voltages VR1and VR3to the gate line driver circuit103.

Further, a control circuit105controls the data line driver circuit102, the gate line driver circuit103and the power supply circuit104. In this case, the control circuit105generates a horizontal clock signal HCK, a horizontal start pulse signal HST, 8-bit data signals D1, D2, . . . , D8and so on, and transmits them to the data line driver circuit102. Also, the control circuit105generates a vertical clock signal VCK, a vertical start pulse signal VST and so on, and transmits them to the gate line driver circuit103. Further, the control circuit105generates two complementary clock signals φ and/φ and transmits them to the power supply circuit104.

The data line driver circuit102, the gate line driver circuit103, the power supply circuit104and the control circuit105are constructed by large scale integrated (LSI) circuits which are mounted on the glass substrate100of the LCD panel101by a chips-on-glass (COG) process or a system-on-glass (SOG) process in order to decrease the manufacturing cost.

In the data line driver circuit102, a data voltage at each of the data lines DL is applied to the pixel capacitor C and the liquid crystal cell CC does not need to be high; however, a high current drive ability is required for the data voltage at each of the data lines DL for charging and discharging the pixel capacitor C and the liquid crystal cell CC. Therefore, the regulated voltage VR2supplied to the data line driver circuit102is a voltage derived from 2·VDD, for example.

On the other hand, in the gate line driver circuit103, since a selection voltage at each of the gate lines GL is applied to the gate of the TPT Q, a high current drive ability is not required; however, the selection voltage at each of the gate lines GL is sufficiently higher than the threshold voltage of the TFT Q to turn ON the TFT Q, while a non-selection voltage at each of the gate lines GL is sufficiently lower than the voltage at a corresponding data line to turn OFF the TFT Q. Therefore, the regulated voltage VR1for the selection voltage is a voltage derived from 4·VDD, for example, while the regulated voltage VR3is derived from (−2)·VDD, for example.

InFIG. 2, which illustrates a detailed circuit diagram of the power supply circuit104ofFIG. 1, a step-up circuit1receives a power supply voltage VDDusing clock signals φ and/φ to generate voltages of 4·VDD, 2·VDDand (−2)·VDD.

A voltage regulator2is powered by the voltage 4·VDDand the ground voltage GND to generate the regulated voltage VR1. Also, a voltage regulator3is powered by the voltage 2˜VDDand the ground voltage GND to generate the regulated voltage VR2. Further, a voltage regulator4is powered by the ground voltage GND and the voltage (−2)·VDDto generate the regulated voltage VR3.

InFIG. 2, a reference voltage Vrefis the power supply voltage VDD, for example.

InFIG. 3, which is a detailed circuit diagram of the step-up circuit1ofFIG. 2, the step-up circuit1is constructed by a 2-multiple charge pump circuit1-1for receiving the voltage VDDclocked by the clock signals φ and/φ to generate a voltage of 2·VDD, a 2-multiple charge pump circuit1-2for receiving the voltage 2·VDD, from the 2-multiple charge pulp circuit1clocked by the clock signals φ and/φ to generate 4·VDD, and a (−1)-multiple charge pump circuit1-3for receiving the voltage 2·VDDfrom the 2-multiple charge pump circuit1-1to generate a voltage of (−2)·VDD.

The 2-multiple charge pump circuit1-1is constructed by charging switches111and112clocked by the clock signal φ, a step-up switch113clocked by the clock signal/φ and an output switch114clocked by the clock signal/φ, a step-up capacitor115and a smoothing capacitor116. First, when the clock signals φ and/φ are high and low, respectively, the switches111and112are turned ON and the switches113and114are turned OFF, so that the capacitor115is charged at VDD. Next, when the clock signals φ and/φ are low and high, respectively, the switches111and112are turned OFF and the switches113and114are turned ON, so that the voltage VDDis added to the output voltage VDDof the capacitor115, thus generating the voltage 2·VDD.

The 2-multiple charge pump circuit1-2is constructed by charging switches121and122clocked by the clock signal φ, a step-up switch123clocked by the clock signal/φ and an output switch124clocked by the clock signal/φ, a step-up capacitor125and a smoothing capacitor126. First, when the clock signals φ and/φ are high and low, respectively, the switches121and122are turned ON and the switches123and124are turned OFF, so that the capacitor125is charged at 2·VDD. Next, when the clock signals φand/φ are low and high, respectively, the switches121and122are turned OFF and the switches123and124are turned ON, so that the voltage 2·VDDis added to the output voltage 2·VDDof the capacitor125, thus generating the voltage 4·VDD.

The (−1)-multiple charge pump circuit1-3is constructed by charging switches131and132clocked by the clock signal φ, a step-down switch133clocked by the clock signal/φ and an output switch134clocked by the clock signal/φ, a step-up capacitor135and a smoothing capacitor136. First, when the clock signals φ and/φ are high and low, respectively, the switches131and132are turned ON and the switches133and134are turned OFF, so that the capacitor135is charged at 2·VDD. Next, when the clock signals φ and/φ are low and high, respectively, the switches131and132are turned OFF and the switches133and134are turned ON, so that the voltage 2·VDDis subtracted from the output voltage GND of the capacitor135, thus generating the voltage (−2)·VDD.

InFIG. 3, the switches111,112,113,114,121,122,123,124,131,132,133and134can be formed by N-channel MOS transistors. Also, if the switches111,112,121,122,131and132are formed by N-channel MOS transistors and the switches113,114,123,124,133and134are formed by P-channel MOS transistors, the clock signals φ and/φ are replaced by a single clock signal φ.

InFIG. 4, which illustrates a detailed circuit diagram of the voltage regulator2ofFIG. 2(see: FIG. 7 of JP-A-2002-189454), the voltage regulator2is of a differential amplifier type which is constructed by a differential pair formed by N-channel MOS transistors21and22, a load circuit connected to the differential pair formed by P-channel MOS transistors23and24forming a current mirror circuit, an output P-channel MOS transistor25for generating the regulated voltage VR1, and constant current sources formed by N-channel MOS transistors26and27whose gates receive a constant bias voltage VB1. The transistors26and27are connected to the differential pair (21,22) and the transistor25, respectively. Also, a reference voltage Vrefis applied to the gate of the transistor21, while a voltage of the regulated voltage VR1divided by resistors28and29is applied to the gate of the transistor22. In this case, the voltage regulator2ofFIG. 4is powered by the voltage 4·VDDand the ground voltage GND whose difference is 4·VDD. Therefore, if a threshold voltage of the P-channel MOS transistors is defined by Vthpand a threshold voltage of the N-channel NOS transistors is defined by Vthn, the difference 4·VDDis required to be larger than 3·Vthwhere |Vthp|=Vthn=Vth, to stabilize the operation of the voltage regulator2, thus obtaining the following:
Vref=(R29/(R28+R29))·VR1
∴VR1=((R28+R29)/R29)·Vref(1)

where R28and R29are resistance values of the resistors28and29, respectively.

InFIG. 5, which illustrates a detailed circuit diagram of the voltage regulator3ofFIG. 2, the voltage regulator3has a similar configuration to that of the voltage regulator2ofFIG. 4. That is, the voltage regulator3is constructed by a differential pair formed by N-channel MOS transistors31and32, a load circuit connected to the differential pair formed by P-channel MOS transistors33and34forming a current mirror circuit, an output P-channel MOS transistor35for generating the regulated voltage VR2, and constant current sources formed by N-channel MOS transistors36and37whose gates receive a constant bias voltage VB2. The transistors36and37are connected to the differential pair (31,32) and the transistor35, respectively. Also, the reference voltage Vrefis applied to the gate of the transistor31, while a voltage of the regulated voltage VR2divided by resistors38and39is applied to the gate of the transistor32. In this case, the voltage regulator3ofFIG. 5is powered by the voltage 2·VDDand the ground voltage GND whose difference is 2·VDD. Therefore, if a threshold voltage of the P-channel MOS transistors is defined by Vthpand a threshold voltage of the N-channel MOS transistors is defined by V|thn, the difference 2·VDDis required to be larger than 3·Vthwhere |Vthp|=Vthn=Vth, to stabilize the operation of the voltage regulator3, thus obtaining the following:
Vref=(R39/(R38+R39))·VR2
∴VR2=((R38+R39)/R39)·Vref(2)

where R38and R39are resistance values of the resistors38and39, respectively.

InFIG. 6, which illustrates a detailed circuit diagram of the voltage regulator4ofFIG. 2, the voltage regulator4is of a differential amplifier type which is constructed by a differential pair formed by P-channel MOS transistors41and42, a load circuit connected to the differential pair formed by N-channel MOS transistors43and44forming a current mirror circuit, an output N-channel MOS transistor45for generating the regulated voltage VR3, and constant current sources formed by P-channel MOS transistors46and47whose gates receive a constant bias voltage VB3. The transistors46and47are connected to the differential pair (41,42) and the transistor45, respectively. Also, the ground voltage GND is applied to the gate of the transistor41, while a difference between reference voltage Vrefand the regulated voltage VR3, divided by resistors48and49, is applied to the gate of the transistor42. In this case, the voltage regulator4ofFIG. 6is powered by the ground voltage GND and the voltage (−2)·VDDwhose difference is 2·VDD. Therefore, if a threshold voltage of the P-channel MOS transistors is defined by Vthpand a threshold voltage of the N-channel MOS transistors is defined by Vthn, the difference 2·VDDis required to be larger than 3·Vthwhere |Vthp|=Vthn=Vth, to stabilize the operation of the voltage regulator4, thus obtaining the following:
Vref=(R49/(R48+R49))·(VR3−Vref)
VR1=((R48+2·R49)/R49)·Vref(3)

where R48and R49are resistance values of the resistors48and49, respectively.

Thus, inFIG. 2, the voltage regulator2is powered by the large voltage difference 4·VDD, the voltage regulator3is powered by the small voltage difference 2·VDD, and the voltage regulator4is powered by the small voltage difference 2·VDD.

Therefore, if the threshold voltages of the MOS transistors of the voltage regulator2are the same as those of the voltage regulators3and4, the absolute values of the threshold voltages of the MOS transistors need to be sufficiently small to operate the MOS transistors of the voltage regulators3and4powered by the small voltage difference 2·VDD. However, generally, in MOS transistors, the smaller the absolute value of the threshold voltage, the smaller the breakdown voltage. As a result, the MOS transistors of the voltage regulator2powered by the large voltage difference 4·VDDare easily broken down, thus deteriorating the reliability.

Note that since TFTs used in the LCD panel101ofFIG. 1generally have large absolute threshold voltages, the MOS transistors having such small absolute threshold voltages cannot be replaced by TFTs, which would increase the manufacturing cost of the LCD apparatus ofFIG. 1.

Note that the absolute threshold voltages of the MOS transistors of the voltage regulator2can be higher than those of the voltage regulators3and4to improve the breakdown characteristics of the voltage regulator2; however, this would increase the manufacturing cost.

InFIG. 7, which illustrates a first embodiment of the power supply circuit according to the present invention, the voltage regulator3ofFIG. 2is powered by the voltage 2·VDDand the voltage (−2)·VDD, and the voltage regulator4ofFIG. 2is powered by the voltage 2·VDDand the voltage (−2)·VDD. That is, all the voltage regulators2,3and4are powered by the large voltage difference 4·VDD.

Thus, the absolute threshold voltages of the MOS transistors of all the voltage regulators2,3and4can be increased-to operate the MOS transistors, so that the breakdown voltage can be enhanced. Also, in this case, since the MOS transistors can be replaced by TFTs having large absolute threshold voltages, the manufacturing cost of the LCD apparatus ofFIG. 1would be decreased. Note that the step-up circuit1ofFIG. 1can also be formed by TFTs, which further would decrease the manufacturing cost of the LCD apparatus ofFIG. 1.

InFIG. 8, which illustrates a second embodiment of the power supply circuit according to the present invention, the voltage regulator2ofFIG. 2is powered by the voltage 4·VDDand the voltage 2·VDD. That is, all the voltage regulators2,3and4are powered by the small voltage difference 2·VDD.

Thus, the absolute threshold voltages of the MOS transistors of all the voltage regulators2,3and4can be decreased to operate the MOS transistors. In this case, the breakdown voltage is decreased; however, this would create no problem, since all the voltage regulators2,3and4are powered by the small voltage difference.

InFIG. 9, which illustrates a third embodiment of the power supply circuit according to the present invention, the regulated voltages VR1and VR3ofFIG. 7are not used; the voltage 4·VDDand the voltage (−2)·VDDare supplied directly to the gate line driver circuit103ofFIG. 1. That is, in the gate line driver circuit103, a high current drive ability is not required as explained above, and also, the power consumption is small and the fluctuation of supplied currents is small. Therefore, the gate lines GL can be driven directly by the voltage 4·VDDand (−2)·VDD.

Thus, inFIG. 9, since the voltage regulators2and4ofFIG. 7are unnecessary, the manufacturing cost of the LCD apparatus ofFIG. 1can be decreased.

As explained hereinabove, according to the present invention, all the voltage regulators can be stably operated and, also, the reliability can be improved.