Narrowband gain control of receiver with digital post filtering

An Automatic Gain Control (AGC) circuit as used in a digital receiver that utilizes a main loop filter that is of a relatively wide bandwidth. A pre-filter, wideband variance is determined from the input digital signal, and a post-filter, narrowband variance is also determined. The wideband and narrowband variances are then compared to determine if the wideband signal power indicates a variance level that is too great to permit normal loop operation. By reapplying this difference in the power levels to the filter output as needed, such as by a scaling operation, the loss in dynamic range is effectively recovered. In a preferred embodiment, an adjustable gain input amplifier feeds an intermediate frequency (IF) signal to an analog-to-digital converter (ADC). The digitized IF signal is then down-converted to a baseband frequency and subjected to digital filtering. A narrowband sample variance (PN) of the digitally filtered (narrowband) data is then determined. A wideband sample variance (PW) is also taken from the raw ADC output data over the same period as the time period used for PN. In the presence of out-of-band signal components, PW will be quite different from PN. This difference indicates a desired proportional difference in a control voltage or a gain backoff amount.

BACKGROUND OF THE INVENTION

The present invention relates generally to radio receivers in which intermediate frequency signals are processed digitally, and more specifically to an automatic gain control circuit that compensates for added wideband signal power.

Modern radio receivers, such as used in cellular telephone, wireless Local Area Network (LAN), wireless Internet access systems, and similar equipment typically now employ digital signal processing techniques to some degree. Digital signal processing permits the replacement of physically large, costly, and unpredictable analog filtering components with their digital counterparts. These receiver architectures require high speed, wideband, analog-to-digital converts (ADCs) and digital filters. Present day ADC technology permits sampling at Intermediate Frequency (IF) or even greater frequencies. However, by replacing traditional analog filters with digital filters implemented after digitization, the ADC potentially also samples out-of-band unwanted signal components. These unwanted signal components may consist of adjacent channels, extra noise, or even jamming signals along with the desired signal of interest.

Direct application of analog receiver architectures to a digital implementation therefore, is often not sufficient to provide the required signal filtering properties. One difficulty stems from the fact that analog demodulation techniques are not directly adaptable to digital receivers. For example, clipping of a received signal lowers the probability of correctly detecting the signal of interest and the data derived there from.

To reduce clipping, digital receivers often include one or more variable gain amplifiers that permit the gain of the receiver to be adjusted by a feedback control signal. The process of adjusting the received signal in this fashion is called Automatic Gain Control (AGC). In the typical digital receiver, the AGC circuitry measures an output signal power of the variable gain amplifier. This measured value is then compared with a value representing the desired signal power to derive an error signal. The error signal is then used to control the variable amplifier gain so that the input signal strength coincides with the desired input signal power. In the typical desired arrangement, the AGC circuit therefore may hold the amplitude of the variable gain amplitude close to the full dynamic range of the analog-to-digital converter.

In the presence of out-of-band signal components, standard gain control loop architectures are often insufficient to guarantee proper analog-to-digital converter operation. Especially in the cellular environment, a digital receiver may receive signals that exhibit rapid and wide variation in signal power. For example, in Code Division Multiple Access (CDMA) wireless communications, it is necessary to precisely control the power level of transmitted signals for proper capacity management.

Some have proposed the use of an AGC circuit wherein the filter bandwidth may be changed. In particular, as described in U.S. Pat. No. 6,178,211, the filter coefficients of a digital signal processor are switchable between a first wide bandwidth to a second narrower bandwidth. A post-filter level detector is responsive to the filtered signal and provides a control signal for selecting one of the banks of filter coefficients. Thus, the circuit reduces the effect of adjacent channel interference by narrowing the bandwidth of a filter in the receiver, which reduces the signal content from the adjacent channel propagating through the receiver.

This type of circuit provides an effective method of filtering out of band signals after the ADC. However, gain control in this circuit is based entirely on the signal power present at the input to the ADC, rather, its digital output. This requires an adaptive filtering technique to switch to the proper coefficients as needed. Often, cases arise in which multiple sets of filter coefficients are not available due to signal processing or memory resource restrictions.

SUMMARY OF THE INVENTION

The circuit proposed herein benefits from reduced complexity by using a fixed set of filter coefficients and switching control of the AGC loop from narrowband to wideband power calculations (and the reverse) as necessary. Furthermore, backend gain control is achieved with a simple scale multiplier applied to both the in-phase (I) and quadrature (Q) data paths.

More particularly, the present invention is an architecture for an Automatic Gain Control (AGC) circuit as used in a digital receiver that utilizes a main loop filter that is of a relatively wide bandwidth. A pre-filter, wideband variance is determined from the input digital signal. In addition, a post-filter, narrowband variance is also determined. The wideband and narrowband variances are then compared to determine if the wideband signal power indicates a variance level that is too great to permit normal loop operation. In such a case, the dynamic range of the desired signal components (e.g., the desired narrowband signal) would otherwise be reduced. By reapplying this difference in the power levels to the filter output, such as by a scaling operation, the loss in dynamic range is effectively recovered.

In a preferred embodiment, an Automatic Gain Control (AGC) circuit includes an additional wideband and narrowband variance comparison section. An adjustable gain input amplifier feeds an intermediate frequency (IF) signal to an analog-to-digital converter (ADC). The digitized IF signal is then down-converted to a baseband frequency and subjected to digital filtering. A narrowband sample variance (PN) of the digitally filtered (narrowband) data is then determined. A wideband sample variance (PW) is also taken from the raw ADC output data over the same period as the time period used for PN.

Assuming that the input signal fed to the ADC is relatively band limited, under normal operating conditions without much interference signal level, the digitally post-filtered signal level has relatively the same power as the raw ADC output. In other words, the normal condition is such that the digital filter removes only perhaps low-level noise and aliasing components generated from the down-conversion process.

In the presence of out-of-band signal components, the wideband sample variance (PW) will be quite different from the narrowband sample variance (PN). This difference indicates a desired proportional difference in a control voltage or a gain backoff amount. Once this backoff amount exceeds a predetermined level, that value is used in a control voltage calculation to reduce input signal.

However, simply replacing the narrowband variance with the wideband variance in the control voltage calculation may yield an inaccurate received signal strength indication and, in turn, actually reduce the signal level of the filtered data. Thus, this power level backoff voltage is also converted to a scale value used to multiply or amplify the filtered data.

This results in recovering the reduced signal level of the filtered data. In addition, if the sampling or decimation rate is high enough, lost sample resolution can also be recovered by output filtering.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Turning attention now toFIG. 1, there is shown a high-level block diagram of an Automatic Gain Control (AGC) circuit10operated in accordance with the invention. The AGC circuit10includes a variable gain input intermediate frequency (IF) amplifier12, an analog-to-digital converter (ADC)14, digital down-converter and filter block15that includes quadrature mixers16-iand16qas well as a pair of low pass filters17-iand17-q, associated with an in-phase quadrature signal path, a main AGC loop filter18, and digital-to-analog converter (DAC)19. The variable gain amplifier12, ADC14, digital down-converter and filter15, main ACG loop filter18, and DAC19are standard components of a digitally implemented Automatic Gain Control circuit.

A unique aspect of the present invention is to also include a wideband variance block22coupled to the output of the ADC14, a narrowband variance block21coupled to the output of the digital down-converter and filter15, a comparison function23to compare the output of wideband variance22and narrowband variance21, as well as output scaler24. In general, the components that comprise the invention add a variance comparison section that determines the difference between a narrowband sample variance as represented by the signal samples at the output of the filters17, and comparing that to a wideband sample variance associated with the input to the digital down-converter and filter15.

The difference between the wideband sample variance (PW) as provided by the wideband variance circuit22and narrowband variance value (PN) as provided by the narrowband variance circuit21represents an indication of whether the setting of the gain control loop is sufficient to guarantee proper operation of the ADC14. In particular, when the difference between the wideband sample variance PWand the narrowband sample variance PNexceeds a predetermined level, an input power level voltage is provided to the main AGC loop18to cause it to limit clipping by the ADC14.

Thus, in cases when the narrowband sample variance PNof the narrowband data is sufficiently the same as the determined wideband variance PW, then the loop operates as in the prior art as a standard automatic gain control loop. However, when the power level of out-of-band signal components is sufficiently large (as provided by jamming signals, noise, interfering adjacent channels, etc.), the difference in variance is detected at the output of the comparison23. In this instance, an additional input power level voltage is provided to offset the AGC loop setpoint input.

A scale value is also preferably provided at the output of the comparison23. The scale value allows the multiplier24to offset a reduction in the power level of the filtered data during conditions when the wideband variance exceeds the narrowband variance. In systems with relatively high decimation rates, even the lost sample resolution can be recovered, provided adequate filtering is applied after the multiplication.

Turning attention now toFIGS. 2 and 3, the situation addressed by the invention is described in relative terms. In particular, in connection withFIG. 2, there is shown a signal power diagram for signals present at the input of the ADC14. In this instance, not only is a desired signal30present, but also there is present an out-of-band interfering signal31. The ideal power level setpoint for the analog-to-digital converter should be at a level32. However, the presence of the relatively strong interference31, that is, a signal that is much stronger than the desired signal30, causes a standard AGC loop to adjust itself to avoid clipping of the ADC14output. Thus, the desired signal30is suppressed in amplitude, causing reduced accuracy in RSSI calculation and the like.

FIG. 3shows a program in a situation as provided by the invention. In particular, using a comparison between the narrowband variance and wideband variance, the loop gain control signals are adjusted accordingly such that the power of the desired signal is increased at the output of the ADC14. This results in a more accurate magnitude of an output signal and results in overall improved receiver performance.

FIG. 4is a signal flow representation of the AGC circuit10. In the preferred embodiment, an input signal scaled from a range of −57 through zero decibels with respect to a millivolt (dBm) is provided to an input adder40. The adder40represents the operation of the variable gain amplifier that is controlled by the gain control input signal70.

The amplifier output is fed to a lowpass filter42. The difference circuit44provides an estimate of the difference between the input and output voltages applied to the lowpass filter42. A comparator46then compares this difference to a predetermined threshold. In this instance, the predetermined threshold is set to −3 dBm or a half-power level. If the output signal power provided by the lowpass filter42is less than the input signal power, then the jamming signal (JAM) is asserted. In this instance, it is concluded that jamming or interfering signal power is present such that the power level that is between the in-band and out-of-band signals needs to be added back into the down-converter data. In this instance, the unfiltered input signal is selected by the multiplexer48.

In an instance where the narrowband signal power is approximately the same or greater than the broadband signal power, then the filtered signal is used for the low control signal. An AGC setpoint is then compared by comparator50and the signal is scaled by the gain constant K1. A loop filter53represented by the summer and delay56filters this feedback signal. Additional delay may be provided by a delay block60.

The digital analog converter (DAC) is represented by a model52that includes log-to-linear converter, lowpass filter66, and linear-to-log converter68.

The resulting signal is then fed as the gain control signal70back to the input. Decimation, although not shown inFIG. 4, can be provided so that any values larger than a predetermined value merely serve to scale the data while maintaining the same relative resolution.

FIGS. 5A,5B, and5C are a detailed circuit diagram for one preferred embodiment of the AGC circuit10. In this implementation, the variable gain amplifier12is seen to comprise three individual variable gain stages120-1,120-2, and120-3. signal on a 70 MHz IF frequency. The sample rate of 58.9824 Msps represents a rate of 48 times the known bandwidth of an input signal that is 1.2288 MHz, which is typical for an input CDMA radio frequency signal.

The digital down conversion and filtering circuit15is implemented in an integrated circuit known as an AD6620 available from Analog Devices of Wilmington, Mass. The device provides a 16-bit signal path for both in-phase (I) and quadrature (Q) signal processing. The sampling rate is set at 4.9152 mega samples per second at baseband and an AGC update rate of 38.4 kilohertz. The AD6620 includes the input quadrature mixer16-i,16-q, two cascaded integrator comb (CIC) type filters, and a Ram Coefficient Filter (RCF).

FIG. 6is a more detailed diagram of a two-stage CIC filter shown as elements160-i-1and160-q-1. This filter provides decimation by a factor of three. For the preferred implementation, the filter has an equivalent Finite Impulse Response (FIR) as follows:
H2=[1, 2, 3, 2, 1]/16

An estimate of narrowband variance provided by the power level determination circuit is implemented with the squarers170-i,170-q, and summer172, as well as accumulator174. The accumulator174provides an average output power indication for every 128 samples, with the shift-out operation being controlled by a 1/32 times clock. The average power value output on signal line175is then fed to the differencing circuit180. The narrowband variance value is determined from components of the received RF signal across a bandwidth which is less than twice a bandwidth of the intended received signal.

A wideband variance estimate is provided by taking the signal140output from the ADC and feeding it to a squaring circuit190. As in the case with squaring circuits170-iand170-g, the squaring circuit190results in an output signal at twice the frequency of the input RF signal. The wide band variance value is determined from components of the received RF signal across a bandwidth which is at least twice as wide as a bandwidth of the intended receiver signal. The output of squaring circuit190is then fed to an accumulator192that provides a sample output every 1/32 clock period time. The accumulated power value is then fed to a divider194and rounding196to provide an average value for the wideband variance estimate. This value is then fed to the flip-flop198to align it in time with the narrowband value.

Returning attention to generation of the narrowband variance value, the differencing circuit feeds a rounding circuit182and log table184prior to being fed as the Received Signal Strength Indication (RSSI) value to the input of an A minus B comparator200. The A minus B comparator200accepts the output of the log table199containing the average wideband power value at input B.

The differencing circuit200thus provides the narrowband minus wideband estimate that is needed to determine the value of the scale factor and other control factors on the loop. For example, the comparator202compares the output of differencing circuit200to a (arbitrary) value 0xFA00 that is a 16-bit hexadecimal representation of a −3 dB reference value multiplied by 512. This comparator202thus indicates whether the wideband value is greater than the threshold value, and if so, asserting the JAM signal203to control the multiplexer204output to create the crest signal205.

Thus, if the narrowband variance signal is greater in magnitude than the wideband variance signal, then the narrowband signal is used to control the remainder of the loop. Otherwise, the signal is zeroed out and not permitted to control the crest of the loop operation.

The crest signal205is then fed about to the AGC setpoint summer208that is, in turn, fed to the loop filter. The loop filter in this embodiment consists of the multiplier210, gain input212, summer214and delay216. The loop output signal217is then ingested by an attenuation factor to provide attitude220to provide an attenuated output signal. This is then fed to a gain distribution circuit212that provides various signals to control the operation of the D to A converters (DACs)214. The DACs214provide signals IF_AGC1and IF_AGC2to control the respective variable gain amplifiers120-1,120-2, and120-3.

Since the gain control voltage in the loop filter is linear-linear, filtering the RMS power level in decibels is possible. Otherwise, if alternate formats are used, the data needs to be converted to volts prior to the integration process performed by the local filter components214and216.

A crest value205is also fed to an inverse log table240to provide the scale factor241. The scale factor is then used as an input to the multiplier173that provides the visual received data output on both I and Q channels.