System for debugging DMA system data transfer

Systems and methods for generating DMA transaction trace records are described. One example system includes a controller that includes a trace module. The trace module receives transfer requests for direct memory access channels, receives timestamps indicative of a transfer request time, generates trace records, wherein each trace record includes a respective timestamp indicative of a transfer request time, generates save commands, and delivers the trace records and the save commands as outputs. The system includes a storage module for saving trace records.

TECHNICAL FIELD

This disclosure relates generally to electronics including controllers.

BACKGROUND

Microcontrollers can be used for controlling other devices. Devices that can be controlled by microcontrollers include analog to digital converters, digital to analog converters, input and output ports, direct memory access (DMA) controllers, coprocessors, and memories.

A DMA controller can transfer data between different memories and the devices controlled by a microcontroller, and thus can allow high speed data transfer with little CPU involvement. The DMA controller may move data between memories and devices using a number of independent DMA channels and may allow a number of independent and parallel data transfers.

The DMA controllers can move data between static random access memory (SRAM) and devices, between SRAM locations, and between device registers. With access to all devices, the DMA controller can handle automatic transfer of data to/from communication modules (i.e., ports). The DMA controller can also read from a memory mapped electronic erasable programmable read only memory (EEPROM).

SUMMARY

In one aspect, a controller system includes a trace module that receives transfer requests for direct memory access channels, receives timestamps indicative of a transfer request time, generates trace records, wherein each trace record includes a respective timestamp indicative of a transfer request time, generates save commands, and delivers the trace records and the save commands as outputs; and a storage module for saving trace records.

In another aspect, a method includes receiving transfer requests for direct memory access channels; receiving timestamps indicative of a time associated with a given request; sampling the received transfer requests; generating trace records, wherein each trace record includes a respective timestamp indicative of a transfer request time; generating save commands in response to the received transfer requests; and saving a trace record in response to a save command in an external device.

Implementations may include one or more of the following features. The trace module may include a latch module that samples the received transfer requests, an assembly module that generates trace records, and a detection module that detects the transfer requests and generates save commands responsive thereto to enable saving of the trace records.

The storage module saves one or more trace records in response to receipt of corresponding save commands, wherein the storage module provides an overflow signal, and the overflow signal sets or clears an overflow bit of a current trace record upon unsuccessful storage of a preceding trace record or upon successful storage of the preceding trace record.

One or more peripheral devices may be coupled to the controller system and the transfer requests may be initiated by the controller or by a peripheral device. The controller system can be a part of an integrated circuit incorporated in a chip. Transfer requests may include a read request from a direct memory access channel, or a write request to a direct memory access channel and a transfer request may be generated for each unit of data transferred from/to direct memory access channels.

The controller system may be coupled to one or more devices for saving and/or viewing the trace records. The devices may include a dedicated timestamp trace buffer, a dedicated physical trace port, an existing trace port, wherein the existing port is configured to be shared, or an onboard direct access memory channel coupled to an onboard static random access memory.

Generating a trace record further includes receiving an overflow signal, the overflow signal indicating success or failure of a preceding save command to save a trace record, and modifying an overflow bit of a current trace record according to the received overflow signal, including setting the overflow bit when a preceding trace record failed to be saved. An overflow bit of a current trace record may be cleared when a preceding trace record is successfully saved.

Aspects of the invention may implement none, one or more of the following advantages. Proposed systems and methods can be used to connect a DMA controller to a storage module so as to enable saving of timestamps indicating corresponding times of the DMA transfer requests.

DETAILED DESCRIPTION

Microcontrollers can be used for controlling one or more other devices (as will be referred to hereafter as, peripheral devices). DMA controllers can transfer data between memories and peripheral devices with little involvement of the central processing unit(s) (CPU)(s) of the microcontroller, and may allow high speed data transfers between peripheral devices and memories.

A DMA transaction is defined as a complete DMA read or write between memories or between memories and peripheral devices. Traditionally, DMA transactions are performed in data blocks. Data block sizes may be controlled by software and can be divided into smaller burst transfers that can be characterized as successive single units of data wherein a single unit of data may be defined as a single bus access. A unit of data can vary depending on the architecture of the system, and can be configured to support, for example, sizes of a byte, a half-word, or a word. A burst may be defined as N units of data where N can be an integer such as 1, 2, 4, or 8 in some configurations. DMA transfers start when a DMA transfer request is detected. A transfer request can be triggered from software, from a peripheral device, or in response to an event.

Referring toFIG. 1, an example of a controller100is shown that includes a trace module150which receives transfer requests120through the input port112. The trace module150also receives, through the input port114, the system timestamps135generated by the controller100. Based on the transfer requests120and the timestamps135, the trace module150generates trace records and save commands. The trace records and save commands are respectively delivered through the output ports115and117to a storage module160. The trace module150is described below with respect toFIG. 2.

The storage module160receives the trace records through the input port124and the save commands through the input port126, respectively. In response to receiving a save command from the input port126, the storage module160saves the corresponding trace record received from the input port124. The storage module160stores one or more trace records and may deliver the saved trace records140at the output port128.

In some implementations, the storage module160may be coupled to/replaced with a dedicated trace buffer for saving the trace records. In some implementations, the storage module160may be coupled to a dedicated physical trace port or may be coupled to an existing trace port being configured to be shared and enabling saving the trace records. In some implementations, the storage module160can be coupled to an onboard direct access memory channel which is coupled to an onboard static random access memory for saving the trace records. In some implementations, the storage module160can be coupled to an external buffer using an Ethernet port or universal serial bus (USB) port.

In some implementations, the storage module160may deliver an overflow signal145through the output port122of the module160to input port118of the trace module150. The overflow signal145may be used by the storage module160to indicate to the trace module150that the storage module160succeeded/failed to execute a latest save command of the trace module150and a trace record associated with the latest save command was/was not saved. As an example, a voltage value may be used for the overflow signal145wherein a high voltage value may indicate a success and a low voltage value may indicate a failure, or vice versa.

In some implementations, the controller100can be implemented as an integrated circuit on a microcontroller chip and the system timestamps may be generated with reference to a system clock on the chip. In some implementations, the trace records140generated at the output128of the storage module160may be combined with instruction trace records of one or more software programs (e.g., generated by a program debugger), all trace records sharing the same timestamp and producing combined trace records of the program instructions and transfer requests.

In some implementations, the trace records140generated at the output128of the storage module160may be combined with event trace records capturing the signaling events of the controller100and instruction trace records of the software program, all three traces having the same timestamp and producing combined trace records of the program instructions, signaling events, and transfer requests. In some implementations, the system clock that is associated with the timestamps is a precise clock.

In some implementations, the trace records140or the combined trace records described above may additionally be combined with other records based on respective timestamps, the respective timestamps may be correlated with the timestamps of the trace records140. As an example, the trace records described above may be combined with the time stamped power measurements, time stamped data transfers.

FIG. 2illustrates an example of a trace module150. The trace module150includes a latch module180. The latch module180receives the transfer requests120through the input port112. The latch module180can be configured to sample and hold the transfer requests. The sampled transfer requests can be passed through the output port172to a detection module190. In some implementations, transfer requests may be sampled synchronously. In some implementations, edge detectors may be used for asynchronous sampling of the transfer requests.

The detection module190receives the sampled transfer requests through the input port182. When transfer requests are detected by the detection module190, save commands177can be generated and provided on the output port117. In some implementations, the detection module190can generate a save command in response to each one of the transfer requests.

In some implementations, the detection module190may not be used, the input port182may directly couple to output port177and the sampled transfer requests of the input port182may be used as save commands.

In some implementations, a transfer request includes a write request to a DMA channel and/or a read request from a DMA channel and the transfer requests may be initiated by, for example, software, or peripheral devices. Examples of peripheral devices initiating transfer requests include analog to digital converters, wireless ports, optical ports, timers, coprocessors, secondary CPU cores, and touch screens. In some implementations, a transfer request is initiated for the read/write of every single byte.

In some implementations, the detection module190may receive mask data indicating the transfer requests that may be masked. The masked transfer requests are the requests that are not traced/monitored and in some implementations, can be discarded. In some implementations, only the transfer requests that are not masked may generate the save commands. In some implementations, all transfer requests except for the transfer requests of a single memory module may be masked. In some implementations, all transfer requests except for the transfer requests associated with a single DMA channel may be masked. In some implementations, no transfer request may be masked.

The assembly module195receives the sampled transfer requests through the input port186and the timestamps135through the input port114. The assembly module195may generate a trace record associated with an unmasked request and incorporate a timestamp into the trace record. The generated trace records are provided at the output port115of the assembly module195. In some implementations, the assembly module195may receive an overflow signal145through the input port118and may incorporate the overflow signal145into the trace records. In some implementations, the assembly module195may include a memory buffer for combining a timestamp and the overflow signal and creating a trace record. As an example, the memory buffer may include one or more bits designated for a timestamp, and at least one bit for incorporating the overflow signal145.

As described with respect toFIG. 1, the respective output ports115and117of the assembly module195and the detection module190may be coupled to the storage module160so as to enable saving the trace records. The storage module160may provide the overflow signal145to indicate to the assembly module195that the storage module160failed or succeeded to execute the save command.

In some implementations, each trace record includes a single overflow bit and each saved trace record may indicate if a preceding trace record failed/succeeded to be saved. As an example, by checking the overflow bit of the trace records, a user of the trace records can find if any gap exists in the trace record of the transfer requests. In some implementations, the trace records may include between one and ten (e.g., 5) overflow bits. In some implementations, the overflow bits may indicate the number of consecutive failures or successes.

In some implementations, any two or more modules including the latch module180, the detection module190, and the assembly module195can be joined into a single command module that performs the functions of the combination.

Referring toFIG. 3a flow diagram of a method300is shown. As an example, the method300can be performed by the system100ofFIG. 1. The method includes receiving transfer requests for direct memory access channels (310). The transfer requests can be initiated by software running on one or more CPUs, a peripheral device, or in response to an event. The transfer requests can be received by an example trace module150shown inFIG. 1. The transfer requests can be generated in parallel and therefore may simultaneously be available.

The timestamps are received, for example, by the trace module (320). In some implementations, system timestamps are internally generated and reference a system clock. The system timestamps may be made available to every module of the system100.

The received transfer requests are sampled (330). As an example, the sampling of the transfer requests is performed by a latch module180. The routing of the transfer requests may not be affected by the sampling. The transfer requests may last a few clock cycles and the sampling time period can be set to ensure transfer requests are not lost.

In some implementations, the transfer requests may last a very short period of time and synchronous sampling may not be performed. In some implementations, the latch module may use edge detectors for asynchronous detection and latching of the transfer requests.

Trace records are generated wherein each trace record includes a timestamp (340). As an example, trace records are generated by the assembly module195and each trace record includes a timestamp indicating a corresponding time of the sampling. In some implementations, the assembly module195may incorporate one or more overflow bit(s) in each trace record. In some implementations, trace records may indicate the DMA channel number and/or the target memory module associated with a given request. Setting or clearing the overflow bit(s) of trace records is described with respect toFIG. 4.

Save commands are generated in response to received transfer requests (350). As an example, the detection of the transfer requests may occur in the detection module190wherein upon detecting a transfer request, a save command can be generated and the save command may cause an example storage module160to save a trace record.

In response to issuance/receipt of a save command, a trace record is saved (360). As an example, a storage module160external to the trace module150receives the save commands and the trace records through the ports126and124, respectively. When a save command is received by an example storage module160, in response, the storage module160saves the corresponding content of the trace record that is delivered at the input port124of the storage module160. In some implementations, the storage module160is used as a buffer and the trace records140are delivered to a memory module external to the storage module160. In some implementations, one or more trace records are saved in the storage module160.

In some implementations, trace records of different DMA channels may be separated by using separate buffers for saving trace records of different DMA channels. In some implementations, the DMA channel number may be included in a trace record and may indicate the DMA channel to which the trace record belongs.

In some implementations, the system timestamps can be shared with a debugger module configured for generating instruction trace records of the software programs running on one or more CPUs. The system timestamps may also be shared with an event tracing system configured for generating event trace records of the signaling events. Combining the trace records140with event trace records and instruction trace records that share the same timestamps and create a combined trace record of the program instructions, signaling events, and transfer requests.

In some implementations, the above described trace records may be combined with other records based on respective timestamps that may be synchronized in post processing.

Referring toFIG. 4, the flow diagram of a method400is shown. As an example, the method400can be performed by the assembly module195ofFIG. 2and can be used to set or clear the overflow bit(s) of trace records. An overflow signal indicating success or failure of a preceding save command is received (410). As an example the overflow signal145is received on the input port118of the assembly module195. In some implementations the overflow signal145is received from an example storage module160that is configured to buffer or save the trace records.

The overflow bit(s) of a current trace record is modified according to the received overflow signal (420). In some implementations, each trace record may include one overflow bit and the overflow bit is modified according the received overflow signal.

An overflow bit is set/cleared when the preceding trace record failed/succeeded to be saved (430). As an example, the assembly module195sets or clears the overflow bit of a current trace record. In some implementation the overflow bit can be set when the preceding trace record failed to be saved and is cleared (reset) when the preceding trace record succeeded to be saved, or vice versa.