Digital-to-analog converter with constant differential gain and method

A digital-to-analog converter is provided that includes an input stage and an output stage. The input stage is operable to receive a digital bit of data, to convert the digital bit into a quasi-differential current, and to convert the quasi-differential current into a first voltage using a load that is comprised of transconductance and resistance. The output stage is coupled to the input stage and is operable to generate analog data based on the first voltage.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to integrated circuits and, more particularly, to a digital-to-analog converter with constant differential gain and method.

BACKGROUND OF THE INVENTION

Digital-to-analog converter blocks are often used in mixed-signal based integrated circuits to interface between a digital-based engine and analog blocks. Such architectures are widely used in various data communications products, in addition to many other types of products. For example, a digital-to-analog converter may be used for providing a DC offset cancellation in a servo loop of a communication channel where the DC offset is sensed through the digital domain and cancelled in the analog domain via the digital-to-analog conversion.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a circuit diagram illustrating a digital-to-analog converter100with constant differential gain in accordance with one embodiment of the present invention. As illustrated inFIG. 1, the digital-to-analog converter100may comprise a differential current source into a polysilicon (poly) resistor load.

The digital-to-analog converter100is operable to receive as an input an N-bit digital word and convert the digital bits into two quasi-differential currents. These currents are provided in the digital-to-analog converter100by two input current sources102aand102b. The digital-to-analog converter100is also operable to generate as an output an analog signal in the form of two fully-differential voltages at output nodes104aand104b.

Associated with each input current source102, the digital-to-analog converter100also comprises a first transistor108and a first resistor110that makeup an input stage and a second current source112, a second transistor114and a second resistor116that makeup an output stage.

The illustrated embodiment also includes a load resistor120for each output node104, which represents the resistance of a load (not explicitly shown inFIG. 1) that is coupled to the digital-to-analog converter100and that is operable to receive the analog output from the digital-to-analog converter100.

The digital-to-analog converter100is powered by a power supply122that is operable to provide a specified voltage to the digital-to-analog converter100. According to one embodiment, the power supply122is operable to provide about 1.8V to 3.3V; however, it will be understood that the power supply122may be operable to provide any other suitable voltage without departing from the scope of the present invention. In addition, the digital-to-analog converter100is operable to receive a bias voltage124at each of the first transistors108. According to one embodiment, the bias voltage may comprise about 1.8V to 3.3V; however, it will be understood that the bias voltage124may comprise any other suitable voltage without departing from the scope of the present invention.

In operation, according to one embodiment, one bit of an N-bit digital word is converted into quasi-differential currents that are provided by the input current sources102of the digital-to-analog converter100. These quasi-differential currents, which track with poly resistor variations over process and temperature, flow into an impedance comprised of first resistors110and transconductance of first transistors108that form the input stage and produce quasi-differential voltages at nodes126.

These voltages are then fed into a fully-differential transconductance output stage with second resistors116used as the source degeneration. The voltages are converted into current by stirring a specified amount of tail currents into the load using the second current sources112, which produces differential output voltages at the output nodes104. The amount of the specified currents generated by the second current sources112aand112btrack with poly resistor variations over process and temperature also and may be determined based on the resistances of the load120aand120bin accordance with differential output swing and bandwidth conditions.

The voltage, V, at either of the nodes126aor126bmay be written as:
V=Ipoly1*(R1+1/Gm1),
where Ipoly1is the current represented by the input current source102aor102b, R1is the resistance of the first resistor110aor110b, and Gm1is the transconductance of the first transistor108aor108b.

The output voltage, Vo, at either of the output nodes104aor104bmay be written as:
Vo=V*[1/(R2+1/Gm2)]*RL,
where R2is the resistance of the second resistor116aor116b, Gm2is the transconductance of the second transistor114aor114b, and RLis the resistance of the load resistor120aor120b. Thus, the output voltage, Vo, may also may be written as:
Vo=Ipoly1*[(R1+1/Gm1)/(R2+1/Gm2)]*RL.

Therefore, as shown in the above equations, the voltages at the nodes126aand126bare quasi-differential voltages generated from Ipoly1. These voltages are then converted back into currents proportional to the effective transconductance of the differential pair of second transistors114aand114b, which include the source degeneration second resistors116aand116b. The first transistors108track with the second transistors114, and the first resistors110track with the second resistors116.

The gain through the input stage of the digital-to-analog converter100((R1+1/Gm1)/(R2+1/Gm2)) may be set to the desired ratio and the output stage gain may be set by Ipoly1*RL, which produces a relatively constant gain and swing at the output nodes104of the digital-to-analog converter100that are fully differential in nature with common-mode rejection. In addition, the limited output swing, So, may be written as:
So=Ipoly2*RL,
which is also relatively constant over process, voltage and temperature variations.

For one embodiment, the first resistors110and the second resistors116may comprise poly resistors in order to further linearize the transconductance of the first and second transistors108and116and thereby support a wide dynamic range in the differential output current.

In addition, according to one embodiment, the first resistors110aand110bmay each comprise a resistance of approximately 1K–10KΩ and the second resistors116aand116bmay each comprise a resistance of approximately 1K–10KΩ. However, it will be understood that the resistors110and116may comprise any suitable resistances without departing from the scope of the present invention.

In this way, the digital-to-analog converter100may convert a digital bit of data into a quasi-differential weighted summing current. The summed current may be a poly resistor type-based current such that it tracks over poly resistor process and temperature variations. The current may then be converted into voltage by a load that is comprised of transconductance and poly resistance. Furthermore, the voltage may then be fed into a differential stage that uses poly resistors in the sources of the input pair transistors114to degenerate the transconductance and, thus, track the input voltage. The resulting current is a true fully-differential current that does not depend on the transconductance of the differential pair of transistors114and provides relatively constant gain and swing with respect to the poly resistor load120coupled to the output nodes104of the differential pair114.

FIG. 2is a circuit diagram illustrating the digital-to-analog converter100implemented in a particular application in accordance with one specific embodiment of the present invention. For this embodiment, the digital-to-analog converter100is implemented as a DC offset canceller, which may be used in a communication channel or other suitable application. It will be understood that this is simply one example of an application in which the digital-to-analog converter100may be implemented and that many other implementations are also possible.

The digital-to-analog converter100in the illustrated embodiment is operable to inject a DC offset cancellation current into an operational amplifier202. The operational amplifier202is operable to receive two differential inputs204and206, each of which comprises an associated resistance208and210, at two input nodes212and214. The operational amplifier202is also operable, in conjunction with two feedback resistors220and222, to amplify the inputs received at the input nodes212and214in order to generate two differential outputs at two output nodes224and226.

Because the operational amplifier202will generally comprise an offset due to slight imperfections within the circuits of the operational amplifier202, the digital-to-analog converter100is operable to substantially cancel that offset by injecting a differential current into the input nodes212and214of the operational amplifier202that will allow the operational amplifier202to function more closely to its ideal. Thus, the outputs provided by the digital-to-analog converter100at the output nodes104aand104bare added to the inputs received at the input nodes212and214of the operational amplifier202, thereby improving the performance of the operational amplifier202.

FIG. 3is a flow diagram illustrating a method for providing digital-to-analog conversion using the digital-to-analog converter100in accordance with one embodiment of the present invention. The method begins at step300where the gain through the input stage of the digital-to-analog converter100is set to the desired ratio by using the following equation:
GainIN=(R1+1/Gm1)/(R2+1/Gm2).

At step302, the gain through the output stage is set by using the following equation:
GainOUT=Ipoly1*RL,
which produces a relatively constant gain and swing at the output nodes104of the digital-to-analog converter100.

At step304, a bit of a digital word is converted into quasi-differential currents provided by the input current sources102of the digital-to-analog converter100. At step306, the quasi-differential currents are provided to the input stage of the digital-to-analog converter100, which corresponds to an impedance comprised of first resistors110and transconductance of first transistors108.

At step308, quasi-differential voltages are produced at nodes126based on the quasi-differential currents. At step310, the quasi-differential voltages are fed into the output stage, which is a differential transconductance stage comprising second resistors116used as the source.

At step312, the quasi-differential voltages are converted back into fully-differential currents by stirring a specified amount of tail currents into the load using the second current sources112. The amount of the specified currents generated by the second current sources112aand112bmay be determined based on the limited output swing requirement. The currents into which the voltages are converted in step312are proportional to the effective transconductance of the differential pair of second transistors114aand114b, which include the source degeneration second resistors116aand116b.

At step314, fully-differential output voltages are produced at the output nodes104based on the currents into which the voltages are converted in step312. This results in a fully-differential, relatively constant output voltage swing that is produced based on the required load. At this point the method returns to step304where the next bit to be converted from digital data into analog data is converted into quasi-differential currents.

In this way, a single differential pair may be used in the signal path, which allows a reduction in capacitance. In addition, constant swing and gain over process and temperature variations for a digital-to-analog converter100is provided, and power and space requirements are lowered. Thus, using the digital-to-analog converter100, a differential current may be provided into a load as a function of digital inputs that may be utilized, for example, in high-speed communication channels by providing open-loop constant gain and swing across the output loads.