Semiconductor device and method of fabricating the same

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 from Korean Patent Application No. 10-2010-0021370, filed in the Korean Intellectual Property Office on Mar. 10, 2010, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present disclosure herein relates to a semiconductor device and a method of fabricating the same, and more particularly, to a flash memory device including a charge storage structure and a gate, and a method of fabricating the same.

As the integration degree of a semiconductor memory device is improved, the critical dimension of a gate of a flash memory is gradually reduced. There is a limitation in that the electrical resistance of a gate increases as the critical dimension of the gate decreases. Accordingly, many studies are being conducted to overcome the above limitation.

SUMMARY

The present disclosure provides a semiconductor device including a gate having improved electrical resistance characteristics.

The present disclosure also provides a method of fabricating the semiconductor device.

The object is not limited to the aforesaid, but other objects not described herein will be clearly understood by those skilled in the art from descriptions below.

Embodiments disclosed herein provide semiconductor devices including: a charge storage structure on a substrate; and a gate on the charge storage structure, the gate including a lower portion formed of silicon and an upper portion formed of metal silicide, wherein the upper portion of the gate has a width greater than that of the lower portion of the gate.

A cross section of the gate may have a trapezoidal shape, tapering from an upper portion of the gate to a relatively wider lower portion. In some embodiments, the lower portion of the gate may have the same width.

In other embodiments, the upper portion of the gate may have a minimum width equal to or greater than a width of the lower portion of the gate.

In still other embodiments, the upper portion of the gate may have a thickness equal to or greater than a thickness of the lower portion of the gate.

In even other embodiments, the upper portion of the gate may include cobalt silicide (CoSix), nickel silicide (NiSix), molybdenum silicide (MoSix), titanium silicide (TiSix), tantalum silicide (TaSix), tungsten silicide (WSix), or a combination thereof.

In yet other embodiments, the semiconductor device may further include an interlayer dielectric filling a gap of a structure in which the charge storage structure and the gate are stacked.

In further embodiments, the interlayer dielectric may cover the lower portion of the gate and expose the upper portion of the gate.

In still further embodiments, the charge storage structure may include a tunnel dielectric layer, a floating gate, and a dielectric pattern.

In even further embodiments, the charge storage structure may include a first insulation layer, a charge trap pattern, and a second insulation pattern.

In other embodiments, methods of fabricating a semiconductor device include: forming a preliminary charge storage structure and a first conductive layer having silicon on a substrate; forming a charge storage structure and a second conductive pattern by etching the preliminary charge storage structure and the first conductive layer; forming a second conductive pattern including metal on an upper sidewall of the first conductive pattern; and forming a gate having an upper portion formed of metal silicide and a lower portion formed of silicon by performing silicidation on the first and second conductive pattern, wherein the upper portion of the gate has a width greater than a width of the lower portion of the gate, and has a trapezoidal shape having a greater width downward.

In some embodiments, the method may further include forming an interlayer dielectric filling a gap of a structure in which the charge storage structure and the first conductive pattern are stacked, wherein the interlayer dielectric covers a lower portion of the conductive pattern and exposes an upper portion of the conductive pattern.

In other embodiments, the forming of the second conductive pattern may include: conformally forming a second conductive layer including metal on the interlayer dielectric and the first conductive pattern; and anisotropically etching the second conductive layer to form the second conductive pattern.

In still other embodiments, the second conductive layer may include cobalt, nickel, molybdenum, titanium, tantalum, or a combination thereof.

In even other embodiments, the second conductive pattern may have an upper portion of a greater thickness than that of a lower portion thereof.

In yet other embodiments, the forming of the charge storage structure may include: forming a tunnel dielectric layer on the substrate; forming a third conductive pattern extending in a first direction on the tunnel dielectric layer; forming a dielectric layer on the third conductive pattern; and forming a dielectric pattern and a floating gate by etching the dielectric layer and the third conductive pattern in a second direction different from the first direction.

In further embodiments, the forming of the charge storage structure may include: forming a first insulation layer on the substrate; forming a charge trap layer on the first insulation layer; forming a second insulation layer on the charge trap layer; and forming a second insulation pattern and a charge trap pattern by etching the second insulation layer and the charge trap layer.

In still other embodiments, semiconductor devices include: a substrate including a first region and a second region; a memory device in the first region of the substrate, the memory device including a charge storage structure and a first gate; and a selection device in the second region of the substrate, the selection device including an insulation layer, a second gate and a source/drain region, wherein the first gate includes a lower portion formed of silicon and an upper portion formed of metal silicide, and the upper portion of the first gate has a width greater than that of the lower portion of the first gate and has a trapezoidal shape having a greater width downward.

In some embodiments, the second gate may include a lower portion formed of silicon and an upper portion formed of metal silicide, and the upper portion of the second gate may have a width greater than that of the lower portion of the second gate and have a trapezoidal shape having a greater width downward.

In other embodiments, the semiconductor device may further include an interlayer dielectric filling the memory device and the selection device, wherein the interlayer dielectric may cover the lower portions of the first and second gates and expose the upper portions of the first and second gates.

In still other embodiments, the upper portions of the first and second gates may have thicknesses equal to or greater than those of the lower portions of the first and second gates, respectively.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The above-described objects, other objects, features, and advantages will be clarified through the exemplary embodiments described below. This technology may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Modifications may be made to the disclosed embodiments without departing from the spirit and scope of the invention set forth in the claims below.

In the present disclosure, it will also be understood that when a component is referred to as being ‘on’ another component, it can be directly on the other component, or intervening components may also be present. In the figures, the dimensions of components are exaggerated for clarity of illustration.

Additionally, the embodiments in the detailed description will be described with sectional views and/or plan views as exemplary views. In the figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. Accordingly, shapes of the exemplary views may be modified according to manufacturing techniques and/or allowable errors. Therefore, the embodiments are not limited to the specific shapes illustrated in the exemplary views, but may include other shapes that may be created according to manufacturing processes. For example, a right-angled etched area may have a rounded shape or a certain curvature. Areas exemplified in the drawings have general properties, and are used to illustrate a shape of a device region. However other shapes and areas are possible such that the illustrated shapes and areas should not be construed as limitations. Also, though terms like a first, a second, and the like are used to describe various components in various embodiments, the components are not limited to these terms. These terms are used only to discriminate one component from another component. Embodiments described and exemplified herein include complementary embodiments thereof.

In the following description, the technical terms are used only for explaining a specific exemplary embodiment and are not intended to be limitations. The terms of a singular form may include plural forms unless referred to the contrary. The meaning of “include,” “comprise,” “including,” or “comprising,” specifies a property, a region, a fixed number, a step, a process, an element and/or a component but does not exclude other properties, regions, fixed numbers, steps, processes, elements and/or components.

FIG. 1is a circuit diagram illustrating a semiconductor device according to an exemplary embodiment.

Referring toFIG. 1, a semiconductor device according to an exemplary embodiment may be a NAND flash memory device.

The NAND flash memory device may include a plurality of memory cells and selection lines. The plurality of memory cells may be disposed in a first region. The selection lines may be disposed in a second region at the both ends of the first region. The selection lines may include a string selection line SSL and a ground selection line GSL.

The semiconductor device may include a plurality of word lines WL and a plurality of bit lines BL.

The respective word lines WL may include a plurality of memory cells that are connected in series to each other. The respective word lines WL may be extended in one direction, and may be parallel to each other.

The bit line BL may include a plurality of memory cells, a string selection line SSL, and a ground selection line GSL that are connected in series to each other. The respective bit lines BL may be extended in a direction different from that of the word line WL, and may be parallel to each other. For example, the word lines WL and the bit lines BL may be perpendicular to each other.

FIGS. 2A through 2Mare perspective views illustrating a method of fabricating a semiconductor device according to an exemplary embodiment.FIGS. 2N and 2Oare cross-sectional views taken along lines x-x′ and y-y′ ofFIG. 2M, respectively.

According to an exemplary embodiment, the semiconductor device shown inFIGS. 2A through 2Mmay include a memory cell of a NAND flash memory device. According to this embodiment, the memory cell may have a structure including a floating gate and a control gate.

Referring toFIG. 2A, a tunnel dielectric layer102may be formed on a substrate100.

The substrate100may include a semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, and a silicon-germanium (Si—Ge) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, and a silicon-germanium-on-insulator (SGOI) substrate.

Although not shown in detail, the substrate100may include an active region that is limited to a field region. The field region may be formed by a shallow trench isolation process. Also, the field region may include oxide, nitride, or oxynitride. For example, the field region may include silicon oxide, silicon nitride, or silicon oxynitride.

The tunnel dielectric layer102may include oxide, for example, silicon oxide. The tunnel dielectric layer102may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a thermal oxidation process.

Referring toFIG. 2B, a first conductive layer104may be formed on the tunnel dielectric layer102.

The first conductive layer104may include silicon doped with impurities, metal, metal compound, or a combination thereof. For example, when the first conductive layer104includes silicon doped with impurities, the first conductive layer104may be formed by a low-pressure chemical vapor deposition process. The doping of impurities may be performed by diffusion, ion implantation, or an in-situ doping process.

Referring toFIG. 2C, a first mask106may be formed on the first conductive layer104.

More specifically, a first mask layer (not shown) may be formed. The first mask layer may include nitride, for example, silicon nitride. A photoresist pattern (not shown) may be formed on the first mask layer. The first mask layer may be etched using the photoresist pattern as an etch mask to form the first mask106. After the first mask106is formed, the photoresist pattern may be removed by an ashing process and a strip process.

The first mask106may have a line shape extending in a first direction. Referring toFIG. 2D, a first conductive pattern108may be formed by an etching process using the first mask106.

More specifically, the first conductive layer (104ofFIG. 2C) may be etched by an anisotropic etching process using the first mask106. The anisotropic etching process may include a plasma etching process or a Reactive Ion Etching (RIE). As a result of the anisotropic etching process, the first conductive pattern108may be formed.

The first conductive pattern108may have a line shape extending in the same first direction as the first mask106.

According to some embodiments, when there are a plurality of the first conductive patterns108, the plurality of first conductive patterns108may be spaced from each other at the same interval, and may be disposed parallel to each other. Also, a plurality of first openings110may be formed between the plurality of first conductive patterns108.

After the first conductive pattern108is formed, the first mask106may be removed.

Referring toFIG. 2E, a dielectric layer112may be conformally formed on the first conductive pattern108and the tunnel dielectric layer102.

The dielectric layer112may be continuously formed along the surface profile of the first conductive pattern and the tunnel dielectric layer102, and may be formed not to completely fill the first openings110.

According to an exemplary embodiment, the dielectric layer112may have a multi-layer structure in which a first oxide layer, a nitride layer, and a second oxide layer are stacked. The first and second oxide layers and the nitride layer may include silicon oxide and silicon nitride, respectively.

According to another exemplary embodiment, the dielectric layer112may include metal oxide having a higher dielectric constant than silicon oxide. Examples of metal oxides may include tantalum oxide (TaOx), titanium oxide (TiOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), aluminum oxide (AlOx), yttrium oxide (YOx), cesium oxide (CsOx), indium oxide (InOx), lanthanum oxide (LaOx), strontium titan oxide (ScTiOx), lead titanium oxide (PbTiOx), strontium ruthenium oxide (ScRuOx), calcium ruthenium oxide (CaRuOx), aluminum nitride oxide (AlNxOy), hafnium silicate (HfSiOy), zirconium silicate (ZrSixOy), hafnium nitride silicate (HfNxSiyOx), zirconium nitride silicate (ZrNxSiyOx), and hafnium aluminate (HfAlOx). The dielectric layer112may be formed of one of the above-enumerated materials or a combination thereof.

Referring toFIG. 2F, a second conductive layer114may be formed on the dielectric layer112.

The second conductive layer114may be formed to fill the first opening110in which the dielectric layer112is formed. According to some embodiments, the second conductive layer114may include polysilicon doped with impurities. In this case, the second conductive layer114may be formed by a low pressure chemical vapor deposition process. The doping of impurities may be performed by diffusion, ion implantation, or an in-situ doping process. Alternatively, in place of polysilicon could be used amorphous silicon or a combination of poly and amorphous silicon. In addition to Si, other useful semiconductor materials can be used, such as other semiconductor elements, or compounds comprising or forming semiconductors, including various silicides, carbides and germanides. Examples include those elements from Group IV of the Periodic Table, including Si, C, or Ge, or alloys of these such as SiC or SiGe; Group II-VI compounds (including binary, ternary, and quaternary forms), e.g., compounds formed from Group II materials such as Zn, Mg, Be or Cd and Group VI materials such as Te, Se or S, such as ZnSe, ZnSTe, or ZnMgSTe; and Group III-V compounds (including binary, ternary, and quaternary forms), e.g., compounds formed from Group III materials such as In, Al, or Ga and group V materials such as As, P, Sb or N, such as InP, GaAs, GaN, InAlAs, AlGaN, InAlGaAs, etc. Conductive layer114could also be formed of a metal, or a conductive metal compound or alloy. While the description of many embodiments disclosed herein reference an exemplary polysilicon/silicide structured word line, the structure for all embodiments described herein, including shapes, sizes, relative sizes, etc., may be equally applicable to other materials. For example, for all embodiments disclosed, contemplated alternative embodiments include use of an alternative semiconductor in place of (or in addition to) polysilicon and/or use of an alternative semiconductor-metal compound in place of (or in addition to) silicide, including those semiconductor and semiconductor-metal compounds referenced here.

Referring toFIG. 2G, a second mask116may be formed on the second conductive layer114.

According to some embodiments, the second mask116may have a line shape extending in a second direction substantially different from the first direction. For example, the second direction may be perpendicular to the first direction.

The second mask116may be a hard mask, and include nitride, for example, silicon nitride. If the second mask116is a hard mask, it may be formed by depositing a hard mask material layer (e.g., nitride) and patterning the hard mask layer via a patterned photoresist material formed on the hard mask material layer, the patterned photoresist material may be subsequently removed. Alternatively, the second mask116may be photoresist.

Referring toFIG. 2H, a second conductive pattern118, a dielectric pattern120, and a floating gate122may be formed by an etching process using the second mask116.

More specifically, the second conductive layer (114ofFIG. 2G), the dielectric layer (112ofFIG. 2G), and the first conductive pattern (108ofFIG. 2G) may be etched by an anisotropic etching process using the second mask116. The examples of the anisotropic etching processes may include a plasma etching process and an active ion etching process.

As a result of the anisotropic etching, a preliminary unit cell124including the floating gate122, the dielectric pattern120, and the second conductive pattern118may be formed on the tunnel dielectric layer102. The floating gate122may be formed on the tunnel dielectric layer102to have a hexahedral structure. The dielectric pattern120may be formed on the floating gate122to extend in the second direction. The second conductive pattern118may be formed on the dielectric pattern120to extend in the second direction.

Also, when a plurality of the preliminary unit cell124are formed, a second opening125may be formed between rows of the plurality of preliminary unit cells124as exemplified byFIG. 2H.

Referring toFIG. 2I, an interlayer dielectric126may be formed on the preliminary unit cell124.

The interlayer dielectric126may be form on the preliminary unit cell124to fill the second opening125.

The interlayer dielectric126may include oxide, nitride, or oxynitride, each of which may include silicon oxide, silicon nitride, or silicon oxynitride.

Referring toFIG. 2J, an upper portion of the second conductive pattern118may be exposed by partially etching the interlayer dielectric126.

While the interlayer dielectric127is being etched, the second mask (116ofFIG. 2I) may be removed.

More specifically, when the interlayer dielectric126includes oxide, and the second mask116includes nitride, an upper portion of the interlayer dielectric126may be etched until the upper surface of the second mask116is exposed. This initial etch may be performed by chemical-mechanical polishing (CMP), for example. The etching of the upper portion of the interlayer dielectric126remaining after the CMP may continue with an etch back process. During the etch back process, the second mask116may be removed such that the upper portion of the second conductive pattern118is exposed. While the second mask116is being removed, the interlayer dielectric126located at the same level as the second mask116may be etched. The interlayer dielectric126may be continuously etched past the level of the second mask116to expose the upper portion of the second conductive pattern118so that it protrudes from the interlayer dielectric layer126. Alternative etching processes to achieve a similar result will be apparent to one of ordinary skill. For example, the above described CMP etching may be performed to remove the second mask116, stopping when the top surface of the second conductive pattern118is exposed, after which the above described etch back process may be performed. Alternatively, a CMP step may be eliminated entirely and a single etch (e.g., a wet etch process) may be used to remove the second mask116and perform the etch back process such that the upper portion of the second conductive pattern118protrudes from the interlayer dielectric layer126. As yet another alternative, the second mask116may be removed prior to depositing interlayer dielectric layer126.

The thickness TUof the upper portion of the second conductive pattern118exposed by the etching of and protruding above the interlayer dielectric126may be substantially equal to, or greater than the thickness TLof a lower portion of the second conductive pattern118below the top surface the interlayer dielectric126(adjacent the conductive pattern118). For example,

In some embodiments, when there is a plurality of second conductive patterns118, a third opening128may be formed between the second conductive patterns118. The interlayer dielectric126may be exposed at the bottom of the third opening128.

Referring toFIG. 2K, a third conductive layer130may be conformally formed on the interlayer dielectric126and the second conductive pattern118.

The third conductive layer130may be continuously formed along a surface profile of the interlayer dielectric126and the second conductive pattern118. Also, the third conductive layer130may be formed not to completely fill the third opening128.

The third conductive layer130may include metal or metal compound. For example, the third conductive layer130may include Ti, Ta, Ni, Co, Mo, W, or a combination thereof. The third conductive layer130may be a refractory metal.

Referring toFIG. 2L, a third conductive pattern132may be formed on the sidewall of the second conductive pattern118by etching the third conductive layer (130ofFIG. 2K).

More specifically, an anisotropic etching process may be performed on the third conductive layer130. The third conductive layer130formed on the conductive pattern118and the conductive layer130formed at the bottom of the third opening128may be selectively etched. Plasma etching is one example of this anisotropic etching.

As a result of the anisotropic etching, the third conductive pattern132may be formed on the sidewall of the second conductive pattern118. The third conductive pattern132may have a sloped sidewall, such that the width of bottom portion of the conductive pattern132is larger than the upper portion of the conductive pattern132. The inner sidewall of the third conductive pattern132may be vertical.

Referring toFIGS. 2Mthorough2O, a silicidation process may be performed on an upper portion of the second conductive pattern118and the third conductive pattern132to form a control gate136. The upper portion134of the control gate136may be formed to have a trapezoidal shape. As will be recognized, the sidewalls of the trapezoidally shaped upper portion134may not be linear and may be rounded, such as shown inFIG. 2M. In addition, the cross sectional shape of the upper portion134need not be trapezoidal, but may instead be substantially rectangular, or rounded, such as exemplified byFIGS. 2P and 2Q, respectively, or have some other shape.

According to some embodiments, if a silicidation process is performed when the second conductive pattern118includes polysilicon doped with impurities, and the third conductive pattern132includes metal, the second and third conductive patterns118and132may be converted into an upper portion134of the control gate136including metal silicide. One of ordinary skill will recognize that design and process conditions may effect the level of silicidation. In some embodiments, silicide—polysilicon boundary may be substantially at the same level and/or co-planar with the upper surface of interlayer dielectric layer126(adjacent to the control gate136), as disclosed in the figures. In other embodiments, the silicide—polysilicon boundary may extend above the upper surface of the dielectric layer126(e.g., into an internal portion of the upper portion134), or may extend below the upper surface of the dielectric layer126(e.g., partly into conductive pattern118).

To describe the silicidation process more specifically, a primary heat-treatment process may be performed on the second conductive pattern118and the third conductive pattern132. Polysilicon and metal in the second and third conductive patterns118and132may be converted into metal silicide through the primary heat-treatment process. After the primary heat-treatment process, polysilicon or metal that is not reacted may be removed through a cleaning process. The portion134of the control gate136including metal silicide having a chemically stable structure may be formed by performing a secondary heat-treatment process.

The upper portion134of the control gate136may include metal silicide by the silicidation process, and the lower portion118of the control gate136may include polysilicon doped with impurities. Also, the upper portion134of the control gate136may have a width WUsubstantially greater than the width WLof the lower portion118of the control gate136. For example, the upper portion134of the control gate136may have a width WUthat is greater than the width of WLof the lower portion118of the control gate136, or at least 20% greater than the width of WLof the lower portion118of the control gate136. The width WLmay be made small if desired, such as less than 40 nm. When considering a portion of the control gate with varying width, such as the trapezoidal shaped upper portion of the control gate, the width is considered to be the larger width, such as WUB(in view of the cross section taken perpendicular to the direction of the line length).

When the upper portion134of the control gate136has a trapezoidal shaped cross section, such as shown inFIG. 2O, the width of the bottom portion WUBof the trapezoidal cross section may be substantially greater than the width of the top WUTof the trapezoidal cross section. For example, the width of the bottom portion WUBof the trapezoidal cross section may be at least 20% greater than the width of the top WUTof the trapezoidal cross section.

Thus, since the upper portion134of the control gate136may include metal silicide, and may have a substantially greater width than that of the lower portion thereof, electrical resistance can be reduced. Since the control gate136may serve as a word line WL, a word line having a smaller electrical resistance can improve the operation speed of the memory device. For example, the silicided cross sectional area of the portion of the word line WL may be at least 20%, or at least 50% of the total cross sectional area of the word line WL.

Thus, a unit cell138including the floating gate122, the dielectric pattern120, and the control gate136may be formed on the tunnel dielectric layer102. It should be noted that this invention has broad applicability outside of tightly spaced word line applications and is not limited to any particular pitch requirement. However, it may be beneficial to implement the invention when pitches (e.g., pitch P inFIGS. 2O-2Q) of lines are 45 nm or less. One example of use is in increasing memory cell density, such as NAND flash cell density, PRAM (phase-change RAM) cell density, RRAM (resistive RAM) cell density and MRAM (magnetoresistive) cell density, where word lines in these memory devices may be word line136described above. Modifications to other portions of the unit cell to that disclosed above particular to the memory device type will be apparent to one of ordinary skill and need not be set forth in detail here. The invention is also applicable to lines in memory devices other than word lines, for example bit lines or data lines. The invention is also applicable to other devices other than memory devices, such as LED (light emitting diode) arrays and CIS (CMOS image sensor) arrays, where the above described word line structure may be used as a row line to access a row of LEDs or light sensitive diodes, respectively, in these arrays. The row lines in the LED array and CIS array may have a pitch range as described herein with respect to memory devices.

FIG. 3Ais a perspective view illustrating a semiconductor device according to another exemplary embodiment.FIG. 3Bis a cross-sectional view taken along line x-x′ ofFIG. 3A.FIG. 3Cis a cross-sectional view taken along line y-y′ ofFIG. 3A

According to an exemplary embodiment, a semiconductor device may include a memory cell of a NAND flash memory. Also, in an embodiment, a memory cell may have a structure including a charge trap pattern and a gate.

Referring toFIGS. 3A through 3C, the semiconductor device may include a charge storage structure207and a gate212on a substrate200.

The charge storage structure207may include a first insulation layer202, a charge trap pattern204, and a second insulation pattern206.

The first insulation layer202may be disposed on the substrate200. The first insulation layer202may include oxide. For example, the oxide may include silicon oxide or metal oxide. Examples of the metal oxide may include aluminum oxide, hafnium oxide, zirconium oxide, and lanthanum oxide.

The charge trap pattern204may be disposed on the first insulation layer202. The charge trap pattern204may have a line structure extending in one direction. Also, the charge trap pattern204may include nitride, nanocrystal material, oxide, or a combination thereof. For example, the charge trap pattern204may include silicon nitride, aluminum oxide, hafnium oxide, or a combination thereof. Also, examples of nanocrystal material may include Si, SiGe, W, Co, Mo, CdSe, and WN.

The second insulation pattern206may have a line structure extending in the substantially same direction as the charge trap pattern204. Also, the second insulation pattern206may include oxide, and may include silicon oxide or metal oxide. Examples of metal oxide may include aluminum oxide, hafnium oxide, zirconium oxide, and lanthanum oxide.

The gate212may have a line structure extending in the substantially same direction as the charge storage structure207. The gate212may have an upper portion210and a lower portion208. The upper portion210of the gate212may include metal silicide. Also, the upper portion210of the gate212may have a greater width downward, for example, may have a trapezoidal shape. However, other shapes may be implemented, such as those described above. The lower portion208of the gate212may include silicon. For example, the lower portion208of the gate212may include silicon doped with impurities. Also, the lower portion208of the gate212may have a certain width. The upper portion210of the gate212may have a thickness substantially equal to or greater than that of the lower portion208of the gate212.

Thus, since the width of the upper portion210of the gate212becomes wider, the electrical resistance characteristics of the gate212can be improved. Since the gate212can serve as a word line WL, the word line WL having a smaller electrical resistance can improve the operating speed of the memory device. Details and modifications thereof described above with respect to the previous embodiments may be equally applicable to this embodiment, including without limitation details and alternative modifications to shape, size, relative sizes, materials, etc.

FIGS. 4A through 4Kare cross-sectional views illustrating a method of fabricating a memory device according to another embodiment.FIGS. 4A through 4Kare cross-sectional views taken by cutting a portion A ofFIG. 1in a bit line direction.

In an embodiment, the semiconductor device may be a NAND flash memory device.

Also, the NAND flash memory device may include a memory cell and a selection line. The memory cell may include a floating gate and control gate structure, which will be described in detail with reference to the first embodiment illustrated inFIGS. 2A through 2O.

Referring toFIGS. 1 and 4A, an insulation layer302and a first conductive pattern304may be formed on a first region and a second region of a substrate300. The first conductive pattern304may be extended in a first direction.

The substrate300may include the first region and the second region. The first region may be a region where a memory cell is formed, and the second region may be a region where a selection line is formed. The selection line may include a ground selection line GSL and a string selection line SSL.

Since a process for forming the insulation layer302and the first conductive pattern304may be substantially identical to the process for forming the tunnel dielectric layer102and the first conductive pattern108, described with reference toFIGS. 2A through 2D, detailed description thereof will be omitted herein.

Referring toFIG. 4B, a dielectric layer306may be formed on the first conductive pattern304. A portion of the dielectric layer306formed in the second region of the substrate300may be etched, which is called a butting process. The butting process may form a first opening308exposing an upper portion of the first conductive pattern304.

Referring toFIG. 4C, a second conductive layer310and a mask312may be formed on the dielectric layer306.

The second conductive layer310may be formed on the first and second regions of the substrate300. According to an embodiment, the second conductive layer310may be formed to completely fill the first opening308of the second region. Accordingly, the first conductive pattern304and the second conductive layer310may be electrically connected.

Also, the mask312may have a line shape extending in a second direction different from the first direction.

Referring toFIG. 4D, the second conductive layer310, the dielectric layer306, and the first conductive pattern304may be etched by an etching process using the mask312.

As a result of the etching process, a first preliminary unit cell320including a floating gate314, a dielectric pattern316, and a second conductive pattern318may be formed. In this case, the insulation layer302may serve as a tunnel dielectric layer. The floating gate314may have a hexahedral shape. When there are a plurality of first preliminary unit cells320, a second opening321may be defined by the first preliminary unit cells320.

Also, a second preliminary unit cell326including a first gate electrode324, a dielectric pattern316, and a second preliminary gate electrode322may be formed on the second region of the substrate300. The first gate electrode324of the second region may correspond to the floating gate314of the first region, and the second preliminary gate electrode322may correspond to the second conductive pattern318of the second region. When there are a plurality of second preliminary unit cells326, a third opening327may be defined by the second preliminary unit cells326. The third opening327may have a width greater than that of the second opening321.

Referring toFIG. 4E, a first interlayer dielectric328may be formed in the first and second regions of the substrate300.

The first interlayer dielectric328may be formed on the substrate300to cover the first and second preliminary unit cells320and326. Also, the first interlayer dielectric328may include oxide, for example, silicon oxide.

The first interlayer dielectric328may be formed on the mask312to completely fill the second and third openings321and327of the first and second regions. In this case, since the second opening321of the first region has a large aspect ratio, a void or seam330may be formed at an upper portion of the first interlayer dielectric328formed in the first region.

Referring toFIG. 4F, an etch stop layer332may be formed on the first interlayer dielectric328.

The etch stop layer332may include material having an etch selectivity with respect to the first interlayer dielectric328. Also, the etch stop layer332may include material having an etch selectivity with the second interlayer dielectric (334ofFIG. 4G) that is subsequently formed.

According to some embodiments, when the first interlayer dielectric328includes oxide, the etch stop layer332may include nitride. For example, the etch stop layer332may include silicon nitride.

Referring toFIG. 4G, a second interlayer dielectric334may be formed on the etch stop layer332.

The second interlayer dielectric334may include oxide, for example, silicon oxide. Also, the second interlayer dielectric334may include the substantially same material as the first interlayer dielectric328.

Referring toFIG. 4H, an upper portion of the second interlayer dielectric334may be etched.

According to some embodiments, the second interlayer dielectric334may be etched to expose the upper surface of the etch stop layer332. The etching process may include an etch back process.

Referring toFIG. 4I, the etch stop layer332and the first interlayer dielectric328may be partially etched, and the mask312may be removed.

According to some embodiments, the etch stop layer332may be etched to expose the upper surface of the mask312. While the etch stop layer332is being etched, the second interlayer dielectric334remaining on the etch stop layer332may be etched. Next, the mask312may be removed to expose the upper surface of the second conductive pattern318of the first region and the upper surface of a preliminary gate electrode of the second region. While the mask312is being removed, an upper portion of the first interlayer dielectric328may be partially etched. The etching process may be an etch back process.

As a result of the etching process, the upper surface of the first interlayer dielectric328may have the substantially same level as the upper surface of the second conductive pattern318and the second preliminary gate electrode322.

Also, while the etching process is being performed, the void or seam330in the first interlayer dielectric328may be exposed to the outside. The size of the exposed void or seam330may be extended by the etching process.

Referring toFIG. 4J, the first interlayer dielectric328may be etched to expose the upper portion of the second preliminary gate electrode322and the upper portion of the second conductive pattern318.

The thickness TUof the upper portion of the second conductive pattern318may be substantially equal to or greater than the thickness TLof the lower portion of the second conductive pattern318. In this case, the lower portion of the second conductive pattern318may be the portion below the surface of the first interlayer dielectric328adjacent the second conductive pattern318, and the upper portion of the second conductive pattern318may be the portion protruding above the first interlayer dielectric328. The alternative thickness relationships of the portions of the word line described above with respect to other embodiments may also be implemented.

Also, the thickness of the upper portion of the second preliminary gate electrode322may be substantially equal to or greater than the thickness of the lower portion of the second preliminary gate electrode322. In this case, the lower portion of the second preliminary gate electrode322may be the portion below the surface of the first interlayer dielectric328adjacent the second preliminary gate electrode322, and the upper portion of the second preliminary gate electrode322may be the portion protruding above the first interlayer dielectric328. The alternative thickness relationships of the portions of the word line described above with respect to other embodiments may also be implemented.

Referring toFIG. 4K, a second gate electrode346and a control gate340may be formed through a silicidation process.

The control gate340may have a lower portion316including silicon, and an upper portion338including metal silicide. The upper portion338of the control gate340may have a width substantially greater than that of the lower portion316, and may have a trapezoidal shape. Thus, a first unit cell342including the control gate340, the dielectric pattern316, and the floating gate314may be formed in the first region of the substrate300.

The second gate electrode346may have a lower portion322including silicon, and an upper portion344including metal silicide. The upper portion344of the second gate electrode346may have a width substantially greater than that of the lower portion322of the second gate electrode346, and may have a trapezoidal shape. Thus, a second unit cell348including the second gate electrode346, the dielectric pattern316, and the first gate electrode324may be formed in the second region of the substrate300.

Since the process for forming the upper portion344of the second gate electrode346and the upper portion338of the control gate340is substantially identical to the process for forming the upper portion of the control gate136including metal silicide and the upper portion134, detailed description thereof will be omitted herein. Details and modifications thereof described above with respect to the previous embodiments may be equally applicable to this embodiment, including without limitation details and alternative modifications to shape, size, relative sizes, materials, etc.

The first unit cell342formed in the first region of the substrate300may serve as a memory cell. Also, the second unit cell348formed in the second region of the substrate300may serve as a selection line.

FIG. 5Ais a block diagram illustrating a memory card including a semiconductor device according to an exemplary embodiment.

Referring toFIG. 5A, a memory including a semiconductor device manufactured according to an embodiment may be applied to a memory card400.

As an example, the memory card400may include a memory controller420removing overall data exchanges between a host and a memory410. An SRAM422may be used as an operating memory of a CPU424. A host interface426may include a data exchange protocol of the host connected to the memory card. An Error Correction Code (ECC)428may detect and correct an error included in data read from the memory410. A memory interface430may interface with the memory410. The CPU424may perform overall control operations for the data exchange of the memory controller420.

The memory410applied in the memory card400may include a semiconductor device manufactured according to an embodiment. In this case, the width of an upper portion of a gate may increase to improve the operating speed of the semiconductor device.

FIG. 5Bis a block diagram illustrating an information processing system to which a semiconductor device according to an exemplary embodiment is applied.

Referring toFIG. 5B, an information processing system500may include a memory system510including a semiconductor device according to an embodiment. The information processing system500may include a mobile device or a computer. As an example, the information processing system500may include a memory system510, a modem520, a CPU530, a RAM540, a user interface550that are electrically connected to a system bus560, respectively. The memory system510may store data processed by the CPU530or data inputted from the outside. The memory system510may include a memory512and a memory controller514, and may be configured substantially similarly to the memory card500described with reference toFIG. 5A. The information processing system500may be provided to memory cards, Solid State Disks (SSDs), Camera Image Sensors (CISs), and other application chipsets. As an example, the memory system510may be configured with an SSD. In this case, the information processing system500may store large-capacity data in the memory system510stably and reliably.

According to some embodiments, since a gate including an upper portion having a width greater than that of a lower portion is formed, electrical resistance of the gate can be reduce. Accordingly, electrical characteristics of a semiconductor device including the gate can be improved.

The above-disclosed subject matter is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the claimed invention. Thus, to the maximum extent allowed by law, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.