SEMICONDUCTOR DEVICE

There is provided a semiconductor device including an active portion which is provided in a semiconductor substrate; a temperature sensing portion which has a PN junction provided above the semiconductor substrate; an interlayer dielectric film provided above the semiconductor substrate; and a front surface side electrode provided above the interlayer dielectric film, in which a contact region between the front surface side electrode and the interlayer dielectric film covers the PN junction, in a top view. The semiconductor device may include a conductive wiring portion electrically connected to the temperature sensing portion, inside the interlayer dielectric film.

The contents of the following patent applications are incorporated herein by reference:NO. 2023-060220 filed in JP on Apr. 3, 2023

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device.

2. Related Art

Patent Document 1 discloses that “a triple point does not exist since the plated layer36is away from the protective film150. Accordingly, the stress concentration due to the triple point can be prevented”.

PRIOR ART DOCUMENT

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, embodiments of the present invention will be described. However, the following embodiments are not for limiting the invention according to the claims. In addition, not all of the combinations of features described in the embodiments are essential to the solution of the invention.

In the present specification, technical matters may be described using orthogonal coordinate axes consisting of an X axis, a Y axis, and a Z axis. The orthogonal coordinate axes merely specify relative positions of components, and do not limit a specific direction. For example, the Z axis is not limited to indicating a height direction with respect to the ground. It should be noted that a +Z axis direction and a −Z axis direction are directions opposite to each other. When the Z axis direction is described without describing the signs, it means that the direction is parallel to the +Z axis and the −Z axis. In addition, in the present specification, a view from the +Z axis direction may be referred to as a top view.

In the present specification, a case where a term such as “same” or “equal” is mentioned may include a case where an error due to a variation in manufacturing or the like is included. The error is, for example, within 10%.

In the present specification, a conductivity type of a doping region where doping has been carried out with an impurity is described as a P type or an N type. Note that the conductivity type of each doping region may also be of reversed polarity. In addition, in the present specification, a term p+ type or n+ type means that its doping concentration is higher than that of the p type or n type, and a term p-type or n-type means that its doping concentration is lower than that of the p type or n type.

The doping concentration in the present specification indicates a concentration of an impurity activated as a donor or an acceptor. In the present specification, in some cases, a concentration difference between the donor and the acceptor may be a higher concentration of the two, the donor or the acceptor. The concentration difference can be measured by capacitance-voltage profiling (CV profiling). Also, a carrier concentration measured by a spread resistance (SR) measurement method may be a concentration of the donor or the acceptor. In addition, in a case where a concentration distribution of the donor or the acceptor has a peak, the peak value may be a concentration of the donor or the acceptor in the region. In a region where donors or acceptors are present, when the concentration of the donors or the acceptors is substantially uniform or the like, an average value of the donor concentration or the acceptor concentration in this region may be set as the donor concentration or the acceptor concentration.

FIG.1shows an example of an upper surface of a semiconductor device100. The semiconductor device100includes a semiconductor substrate10, a gate pad50, a current sensing pad172, a temperature sensing portion178, and an anode pad174and a cathode pad176which are electrically connected to the temperature sensing portion178. The semiconductor device100may include a bidirectional diode portion210and an output comparison diode portion220. A gate wiring portion48includes metal wiring47and a gate runner46.

The semiconductor substrate10has an edge side102. As used herein, in the top view ofFIG.1, a direction along one edge side102-1of the semiconductor substrate10is considered to be an X axis direction, and a direction perpendicular to the X axis direction is considered to be a Y axis direction. In the present example, the X axis is taken in a direction along the edge side102-1. In addition, a direction being perpendicular to the X axis direction and the Y axis direction, and forming a right-hand system with the X axis direction and the Y axis direction is referred to as a Z axis direction.

The semiconductor substrate10has an active portion120at a front surface. The active portion120is a region in which a main current flows in a depth direction between the front surface and a back surface of the semiconductor substrate10when the semiconductor device100is turned on. A gate conductive portion44which will be described below is electrically connected to the gate pad50by the gate wiring portion48.

The active portion120may include an active portion120-1, an active portion120-2, an active portion120-3, an active portion120-4, an active portion120-5, and an active portion120-6, which are divided and arranged. The active portion120may be provided with a transistor portion70including a transistor element such as an IGBT (insulated gate bipolar transistor) and a MOS-FET (metal oxide semiconductor field effect transistor), and may be provided with a diode portion80including a diode element such as a FWD (freewheeling diode). The transistor portion70and the diode portion80will be described below. The active portion120may be a region in which at least one of the transistor portion70or the diode portion80is provided. The transistor portion70and the diode portion80may be alternately arranged in each region in the active portion120along the X axis direction.

The semiconductor device100has a well region130of the P+ type outside the active portion120at the front surface. The semiconductor device100has an edge termination structure portion outside the well region130. The edge termination structure portion includes, for example, a guard ring that is annularly provided so as to surround the active portion120, or a field plate, or a combination thereof.

The temperature sensing portion178is provided above the semiconductor substrate10. The temperature sensing portion178in the present example is provided near the center of the semiconductor substrate10. When the active portions120of the semiconductor substrate10are integrated, the center of the semiconductor substrate10is easily heated by heat generated from switching devices which are formed in the active portions120. By providing the temperature sensing portion178near the center, a temperature of the transistor portion70can be monitored. This can prevent the transistor portion70from overheating beyond a junction temperature that is a normal operating temperature range.

The temperature sensing portion178may have a PN junction. The temperature sensing portion178may include a temperature sensing diode. As an example, the temperature sensing portion178is provided by a Schottky diode. In addition, the temperature sensing portion178may include a PN junction diode that is provided above the semiconductor substrate10via a dielectric film, and is made of polycrystalline silicon. The temperature sensing portion178may include a temperature resistor whose resistance value is temperature dependent. For example, polycrystalline silicon may be used as the temperature resistor.

A conductive wiring portion181connects the temperature sensing portion178, and the anode pad174and the cathode pad176. The conductive wiring portion181is provided extending in a predetermined direction (in the present example, the X axis direction) inside an interlayer dielectric film380which will be described below. The conductive wiring portion181includes first wiring180and second wiring182.

The conductive wiring portion181may be made of polysilicon. The conductive wiring portion181may be made of metal with a high melting point such as tungsten, titanium, titanium nitride, tantalum, and tantalum nitride. By the conductive wiring portion181being made of polysilicon or metal with a high melting point, it is possible to suppress a deterioration of temperature sensing wiring due to migration.

The first wiring180connects one end of the temperature sensing portion178and the anode pad174. The first wiring180in the present example extends inside the interlayer dielectric film380provided above the semiconductor substrate10, and is not provided above the interlayer dielectric film380. In this way, by forming the first wiring180inside the interlayer dielectric film380, it is possible to connect the temperature sensing portion178and the anode pad174, without providing a protective film such as a polyimide film above the conductive wiring portion181and the temperature sensing portion178.

The second wiring182connects another end of the temperature sensing portion178and the cathode pad176. The second wiring182may be formed simultaneously with the first wiring180, or may be formed separately. A material of the second wiring182may be the same as or different from a material of the first wiring180.

Similarly to the first wiring180, the second wiring182in the present example extends inside the interlayer dielectric film380provided above the semiconductor substrate10, and is not provided above the interlayer dielectric film380. In this way, by forming the second wiring182inside the interlayer dielectric film380, it is possible to connect the temperature sensing portion178and the cathode pad176, without providing a protective film such as a polyimide film above the conductive wiring portion181and the temperature sensing portion178.

The cathode pad176is connected to the temperature sensing portion178via the second wiring182. The anode pad174is connected to the temperature sensing portion178via the first wiring180. The cathode pad176and the anode pad174are electrodes containing metal such as aluminum.

The current sensing pad172is electrically connected to a current sensing portion110. The current sensing pad172is an example of a front surface side electrode. The current sensing portion110has a structure similar to the structure of the transistor portion70in the active portion120, and simulates operations of the transistor portion70. A current that flows into the current sensing portion110is in proportion to a current that flows into the transistor portion70. This makes it possible to monitor a current flow of the transistor portion70.

It should be noted that the current sensing portion110is different from the transistor portion70in that the current sensing portion110has no emitter region12, which will be described below. In this manner, the current sensing portion110does not operate as a transistor. The current sensing portion110is provided with a gate trench portion. The gate trench portion of the current sensing portion110is electrically connected to a gate wiring portion.

The bidirectional diode portion210is arranged between the anode pad174and the cathode pad176at the front surface of the semiconductor device100. The bidirectional diode portion210includes a diode electrically connected in a serial bidirectional way between the anode pad174and the cathode pad176. The bidirectional diode portion210prevents the temperature sensing portion178from being damaged by an Electro-Static Discharge (ESD).

The output comparison diode portion220is provided between the anode pad174and the cathode pad176. The output comparison diode portion220is electrically connected to the anode pad174and the cathode pad176. The output comparison diode portion220includes an output comparison diode having a direction of the PN junction connected antiparallel to a direction of the PN junction of the temperature sensing portion178.

At a time of an operation of the semiconductor device100, no current is applied to the output comparison diode portion220. An output comparison operation is performed for each predetermined cycle. At a time of the output comparison operation, the current is applied to the output comparison diode portion220. By the output comparison operation, it is possible to grasp a time for replacing the temperature sensing portion178.

The gate wiring portion48may be electrically connected to the gate pad50. Further, the gate wiring portion48is connected to the below-described gate conductive portion44of the transistor portion70arranged in the active portion120, and sets the gate conductive portion44to a gate potential. The gate conductive portion44corresponds to a gate electrode of the transistor portion70. In this manner, a transistor of the transistor portion70is switched on.

The metal wiring47is provided above the semiconductor substrate10. The metal wiring47may extend in an annular shape to surround an outer periphery of the active portion120. The metal wiring47may be formed of a conductive material such as aluminum or an aluminum-silicon alloy. The metal wiring47and an emitter electrode52are provided separately from each other.

The gate runner46is provided above the semiconductor substrate10and below the metal wiring47. The gate runner46is electrically connected to the metal wiring47. The gate runner46may extend in an annular shape to surround the outer periphery of the active portion120, and may be arranged to surround the temperature sensing portion178. The gate runner46may be formed to partially overlap the conductive wiring portion181in the top view. The gate runner46may be formed to partially overlap the temperature sensing portion178in the top view.

The gate runner46may be formed of the same material as that of the metal wiring47, or may be formed of a different material. The gate runner46in the present example is made of polysilicon.

InFIG.1, a position where the gate wiring portion48is provided at the front surface of the semiconductor substrate10is indicated by a dashed line. Note that the position of the wiring in the drawing merely shows an approximate position to avoid a confusion with other wiring. The detailed position of the gate wiring portion48will be described below.

The gate pad50is electrically connected to an external control terminal. The gate pad50is formed of a conductor made of metal such as aluminum. The gate pad50may be externally connected by means of wire bonding.

FIG.2Ais an example of a top plan view of the semiconductor device100.FIG.2Ashows a vicinity of an end portion of the active portion120-2on a negative side in the Y axis direction. The semiconductor device100includes the semiconductor substrate10having the transistor portion70including a transistor element such as an IGBT, and the diode portion80including a diode element such as a freewheeling diode (FWD).

The semiconductor device100of the present example includes a gate trench portion40, a dummy trench portion30, the well region130, the emitter region12, a base region14, and a contact region15which are provided inside a front surface side of the semiconductor substrate10. The gate trench portion40and the dummy trench portion30each are an example of the trench portion.

In addition, the semiconductor device100of the present example includes the metal wiring47and the emitter electrode52which are provided above the front surface of the semiconductor substrate10. The emitter electrode52is an example of the front surface side electrode. The metal wiring47and the emitter electrode52are electrically insulated.

An interlayer dielectric film is provided between the emitter electrode52and the metal wiring47, and the front surface of the semiconductor substrate10, although it is omitted inFIG.2A. In the interlayer dielectric film of the present example, contact holes49,54and56are provided penetrating through the interlayer dielectric film. InFIG.2A, each contact hole is hatched with oblique lines.

The emitter electrode52is provided above the gate trench portion40, the dummy trench portion30, the well region130, the emitter region12, the base region14, and the contact region15. The emitter electrode52is electrically connected to the emitter region12, the base region14, and the contact region15at the front surface of the semiconductor substrate10, by the contact hole54.

In addition, the emitter electrode52is connected to a dummy conductive portion in the dummy trench portion30by the contact hole56. A connection portion25formed of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode52and the dummy conductive portion. The connection portion25is provided at the front surface of the semiconductor substrate10via a dielectric film such as the interlayer dielectric film and a dummy dielectric film of the dummy trench portion30.

The gate runner46is connected to the gate conductive portion in the gate trench portion40at the front surface of the semiconductor substrate10. The gate runner46is electrically connected to the metal wiring47via the contact hole49. The gate runner46is not electrically connected to the dummy conductive portion in the dummy trench portion30and the emitter electrode52.

The gate runner46and the emitter electrode52are electrically separated by an insulator such as the interlayer dielectric film and an oxide film. The gate runner46of the present example is provided from a position below the contact hole49to an edge portion (an end portion in the Y axis direction) of the gate trench portion40. At the edge portion of the gate trench portion40, the gate conductive portion is exposed to the front surface of the semiconductor substrate10, and is connected to the gate runner46.

The emitter electrode52is formed of a conductive material including metal. For example, they are formed of aluminum or an aluminum-silicon alloy. The emitter electrode52may have barrier metal formed of titanium, a titanium compound, and the like under a region formed of aluminum and the like.

The emitter electrode52may also have a plug formed of tungsten or the like in the contact hole. The plug may have the barrier metal on a side in contact with the semiconductor substrate10and have tungsten embedded to be in contact with the barrier metal, and may be formed of aluminum or the like on tungsten.

The well region130extends to an outside of the gate runner46to overlap an outer peripheral region, and is annularly provided in the top view. The well region130also extends to the active portion120inside the gate runner46by a predetermined width, and is annularly provided in the top view. The well region130in the present example is provided in a range farther away from an end portion of the contact hole54in the Y axis direction toward a gate runner46side. The well region130is a region of a second conductivity type in which the doping concentration is higher than that of the base region14. The doping concentration of the well region130may be the same as the doping concentration of the contact region15, or may be lower than that. The gate runner46is electrically insulated from the well region130.

The base region14of the present example is the P− type, and the well region130is the P+ type. In addition, the well region130is formed from the front surface of the semiconductor substrate to a position deeper than a lower end of the base region14. The base region14is provided in contact with the well region130in the transistor portion70and the diode portion80. The well region130is electrically connected to the emitter electrode52.

Each of the transistor portion70and the diode portion80includes a plurality of trench portions arrayed in an array direction. In the transistor portion70of the present example, one or more gate trench portions40and one or more dummy trench portions30are alternately provided along the array direction. In the diode portion80of the present example, the plurality of dummy trench portions30is provided along the array direction.

In the present example, the array direction of the trench portions is the X axis direction, and the extension direction perpendicular to the array direction is the Y axis direction. The gate trench portion40of the present example may have two extension parts41extending along the extension direction (parts of the trench that are linear along the extension direction), and a connection part43connecting the two extension parts41.

At least a part of the connection part43may be provided in a curved shape in the top view. The connection part43connects end portions of the two extension parts41in the Y axis direction to the gate runner46, which functions as a gate electrode to the gate trench portion40. On the other hand, by forming the connection part43into the curved shape, an electric field concentration at the end portions can be reduced, in comparison with a case where the extension part41makes the completion.

In the transistor portion70, the dummy trench portions30are provided between the respective extension parts41of the gate trench portions40. In the example ofFIG.2A, one dummy trench portion30is provided between the respective extension parts41; however, two or more dummy trench portions30may be provided.

In addition, between the respective extension parts41, the dummy trench portion30may not be provided, and the gate trench portion40may be provided. with such a structure, the electron current from the emitter region12can be increased, so that an ON voltage is reduced.

The dummy trench portion30may have a linear shape extending in the extension direction, and may have an extension part31and a connection part33, similarly to the gate trench portion40. In the semiconductor device100shown inFIG.2A, only the dummy trench portion30having the connection part33is arrayed; however, in another example, the semiconductor device100may include the dummy trench portion30with a linear shape that does not have the connection part33.

A diffusion depth of the well region130may be deeper than depths of the gate trench portion40and the dummy trench portion30. The end portions in the Y axis direction of the gate trench portion40and the dummy trench portion30are provided in the well region130in the top view. That is, at the end portion of each trench portion in the Y axis direction, a bottom portion of each trench portion in the depth direction (a positive side in the Z axis direction) is covered with the well region130. With this configuration, the electric field concentration on the bottom portion of each trench portion can be reduced.

A mesa portion is provided between the respective trench portions in the array direction. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate10. As an example, a depth position of the mesa portion is from the front surface of the semiconductor substrate to a lower end of the trench portion.

The mesa portion of the present example is sandwiched between trench portions that are adjacent to each other in the X axis direction, and is provided to extend in the extension direction (the Y axis direction) along the trench at the front surface of the semiconductor substrate10.

Each mesa portion is provided with the base region14. In each mesa portion, at least one of the emitter region12of a first conductivity type or the contact region15of the second conductivity type may be provided in a region sandwiched between the base regions14in the top view. The emitter region12of the present example is the N+ type, and the contact region15is the P+ type. The emitter region12and the contact region15may be provided between the base region14and the front surface of the semiconductor substrate10in the depth direction. Examples of a dopant of the emitter region12include arsenic (As), phosphorus (P), antimony (Sb), and the like.

The mesa portion of the transistor portion70has the emitter region12exposed to the front surface of the semiconductor substrate10. The emitter region12is provided in contact with the gate trench portion40. The mesa portion in contact with the gate trench portion40is provided with the contact region15exposed to the front surface of the semiconductor substrate10.

Each of the contact region15and the emitter region12in the mesa portion is provided from one trench portion to the other trench portion in the X axis direction. As an example, the contact region15and the emitter region12in the mesa portion are alternately arranged along the extension direction of the trench portion (the Y axis direction).

In another example, the contact region15and the emitter region12in the mesa portion may be provided in a stripe shape along the extension direction of the trench portion (the Y axis direction). For example, the emitter region12is provided in a region in contact with the trench portion, and the contact region15is provided in a region sandwiched between the emitter regions12.

The mesa portion of the diode portion80is not provided with the emitter region12. An upper surface of the mesa portion of the diode portion80may be provided with the base region14. The base region14may be arranged in the entire mesa portion of the diode portion80. The base region14of the diode portion80operates as an anode.

The contact hole54is provided above each mesa portion. The contact hole54is arranged in a region sandwiched between the base regions14in its extension direction (the Y axis direction). The contact hole54of the present example is provided above each region of the contact region15, the base region14, and the emitter region12. The contact hole54may be arranged at the center of the mesa portion in the array direction (the X axis direction).

In the diode portion80, a region adjacent to the back surface of the semiconductor substrate is provided with a cathode region82of the N+ type. In the back surface of the semiconductor substrate, a region in which the cathode region82is not provided may be provided with a collector region22of the P+ type. InFIG.2A, a boundary between the cathode region82and the collector region22is indicated by a dotted line.

The boundary between the collector region22and the cathode region82is a boundary between the transistor portion70and the diode portion80. That is, in the present example, the transistor portion70is a region where the collector region22provided in a back surface side of the semiconductor substrate10is projected onto an upper surface of the semiconductor substrate10. In addition, the diode portion80is a region where the cathode region82provided at the back surface of the semiconductor substrate10is projected onto the upper surface of the semiconductor substrate10.

FIG.2Bshows an example of a cross section B-B′ inFIG.2A. The cross section B-B′ is an XZ plane passing through the emitter region12in the transistor portion70. The semiconductor device100of the present example has: the semiconductor substrate10including the emitter region12, the base region14, an accumulation region16, a drift region18, a buffer region20, the collector region22, and the cathode region82; an interlayer dielectric film38; and the emitter electrode52and a collector electrode24, in the cross section B-B′. The collector electrode24is an example of a back surface side metal layer provided in contact with a back surface23of the semiconductor substrate10.

The drift region18is a region of the first conductivity type which is provided in the semiconductor substrate10. The drift region18in the present example is the N-type as an example. The drift region18may be a region that has remained without other doping regions being formed in the semiconductor substrate10. That is, the doping concentration of the drift region18may be the doping concentration of the semiconductor substrate10.

The accumulation region16is a region of the first conductivity type provided below the base region14in the semiconductor substrate10. The doping concentration of the accumulation region16is higher than the doping concentration of the drift region18. the accumulation region16in the present example is the N+ type as an example.

The accumulation region16may be provided in the transistor portion70, and may not provided in the diode portion80. The accumulation region16may be provided in both of the transistor portion70and the diode portion80. By providing the accumulation region16, it is possible to enhance the carrier injection enhancement effect (IE EFFECT) to reduce an ON voltage of the transistor portion70.

The buffer region20of the first conductivity type may be provided below the drift region18. The buffer region20of the present example is the n type. The doping concentration of the buffer region20is higher than the doping concentration of the drift region18. The buffer region20may function as a field stopper layer configured to prevent a depletion layer expanding from a lower surface side of the base region14from reaching the collector region22and the cathode region82.

In the transistor portion70, the collector region22is provided below the buffer region20. The collector region22may be provided in contact with the cathode region82in the back surface23.

In the diode portion80, the cathode region82is provided below the buffer region20. The cathode region82may be provided at the same depth as that of the collector region22of the transistor portion70. The diode portion80may function as a freewheeling diode (FWD) configured to pass a freewheeling current that is conducted in a reverse direction, when the transistor portion70is turned off.

The collector electrode24is formed at the back surface23of the semiconductor substrate10. The collector electrode24is formed of a conductive material such as metal. The collector electrode24may be formed of the same conductive material as that of the emitter electrode52, or may be formed of a different conductive material.

The gate trench portion40has a gate trench, a gate dielectric film42, and the gate conductive portion44which are formed at a front surface21. The gate dielectric film42is formed to cover an inner wall of the gate trench. The gate dielectric film42may be formed by oxidizing or nitriding a semiconductor on the inner wall of the gate trench. The gate conductive portion44is formed in an interior of the gate trench, and is also formed inside the gate dielectric film42. The gate dielectric film42insulates the gate conductive portion44from the semiconductor substrate10. The gate conductive portion44is formed of a conductive material such as polysilicon. The gate trench portion40is covered with the interlayer dielectric film38at the front surface21.

The gate conductive portion44includes a region facing the base region14which is adjacent with the gate dielectric film42being sandwiched therebetween in the depth direction of the semiconductor substrate10. When a predetermined voltage is applied to the gate conductive portion44, a channel is formed to a surface layer being at a boundary within the base region14and in contact with the gate trench, due to an electron inversion layer.

The dummy trench portion30may have the same structure as that of the gate trench portion40. The dummy trench portion30includes a dummy trench, a dummy dielectric film32, and a dummy conductive portion34which are formed in a front surface21side. The dummy dielectric film32is formed to cover an inner wall of the dummy trench. The dummy conductive portion34is formed in an interior of the dummy trench, and is also formed inside the dummy dielectric film32. The dummy dielectric film32insulates the dummy conductive portion34from the semiconductor substrate10. The dummy trench portion30is covered with the interlayer dielectric film38at the front surface21.

The interlayer dielectric film38is provided on the front surface21. The emitter electrode52is provided above the interlayer dielectric film38. The interlayer dielectric film38may be provided with one or more trench contact portions to electrically connect the emitter electrode52and the semiconductor substrate10. Similarly, the contact hole49and the contact hole56may also have the trench contact portion provided to pass through the interlayer dielectric film38.

FIG.3Ais a view showing an example of an enlarged view of a vicinity of the temperature sensing portion178in a cross section A-A′ ofFIG.1. The cross section A-A′ is an XZ cross section passing through the anode pad174, the gate runner46, the first wiring180, the temperature sensing portion178, and the gate pad50.

The interlayer dielectric film380is provided between the front surface of the semiconductor substrate10and the front surface side electrode. The interlayer dielectric film380includes a first dielectric layer381, a second dielectric layer382, a third dielectric layer383, and a gate oxide film384. The interlayer dielectric film380may include an additional dielectric layer.

The gate oxide film384is provided between the gate runner46and the semiconductor substrate10. Similarly to the dummy dielectric film32and the gate dielectric film42, the gate oxide film384may be formed by oxidizing or nitriding the front surface of the semiconductor substrate10.

The first dielectric layer381is provided above the front surface of the semiconductor substrate10. The first dielectric layer381may be provided on lower surfaces of the temperature sensing portion178and the conductive wiring portion181. The first dielectric layer381may be a high temperature silicon oxide (HTO: High Temperature Oxide) film. The first dielectric layer381may be a silicon oxide film which is non-doped. In an example, the first dielectric layer381is formed of silicon oxide (SiO2). By providing the first dielectric layer381on the lower surface of the temperature sensing portion178, it is possible to enhance a breakdown voltage.

The second dielectric layer382is provided above the first dielectric layer381. The second dielectric layer382may be provided on an upper surface of the conductive wiring portion181. The material of the second dielectric layer382may be the same as or different from that of the first dielectric layer381.

In the present example, both of the first dielectric layer381and the second dielectric layer382are the silicon oxide films which are non-doped. By the first dielectric layer381and the second dielectric layer382being made of the silicon oxide films which are non-doped, even when the gate runner46, the temperature sensing portion178, and the conductive wiring portion181are made of polysilicon, it is possible to prevent a contamination by an element such as boron (B) that is contained in the interlayer dielectric film38.

The third dielectric layer383is provided above the second dielectric layer382. The third dielectric layer383may be a BPSG (Boro-phospho Silicate Glass) film, may be a BSG (borosilicate glass) film, or may be a PSG (Phosphosilicate glass) film. The third dielectric layer383in the present example is the BPSG film.

The temperature sensing portion178may be made of polysilicon. The temperature sensing portion178of the present example has the PN junction in the Y axis direction. A resistance of the PN junction exhibits temperature dependence, and thus it is possible for the temperature sensing portion178to measure the temperature in the active portion120of the semiconductor device100.

The PN junction of the temperature sensing portion178is covered with the interlayer dielectric film380and a contact region151of the front surface side electrode in the top view. In the semiconductor device of a comparison example, anode wiring or cathode wiring connected to the temperature sensing portion178is provided above the temperature sensing portion178, and the front surface side electrode is not provided. In the semiconductor device100of the present example, the anode wiring and the cathode wiring are not provided above the temperature sensing portion178, and the temperature sensing portion178is electrically connected by the conductive wiring portion181extending inside the interlayer dielectric film380, and thus it is possible to cover the PN junction with the contact region151.

An upper surface of the temperature sensing portion178is covered with the second dielectric layer382. In the semiconductor device of the comparison example, a contact hole for connecting the temperature sensing portion178and the anode wiring or the cathode wiring is provided above the temperature sensing portion178, and is not covered with the second dielectric layer382. In the semiconductor device100of the present example, by providing the conductive wiring portion181inside the interlayer dielectric film380, it is possible to cover the upper surface of the temperature sensing portion178with the second dielectric layer382, and to stabilize a characteristic of the temperature sensing portion178.

FIG.3Bshows an example of a cross section A-A′ inFIG.1. InFIG.3B, hatching is shown in a part that is conductive.

As shown inFIG.3B, the gate runner46may be provided to at least partially overlap the conductive wiring portion181in the top view. The gate runner46may be provided below the conductive wiring portion181with the interlayer dielectric film380being sandwiched between the gate runner46and the conductive wiring portion181. The gate oxide film384may be provided between the gate runner46and the front surface of the semiconductor substrate10. The gate runner46may be connected to the gate pad50via a contact hole57.

As shown inFIG.3B, the first wiring180is provided to extend inside the interlayer dielectric film380in the X axis direction. The first wiring180is connected to the anode pad174via the contact hole57. This makes it possible to electrically connect the anode pad174and the temperature sensing portion178. Similarly, the second wiring182can electrically connect the cathode pad176and the temperature sensing portion178.

A plating film155is provided above the front surface side electrode. The plating film155is provided in a part that is above the front surface side electrode and in which a protective film150is not provided. The material of the plating film155may be metal having a higher surface tension than that of solder. In an example, the plating film155is for nickel plating.

A thickness of the plating film155may be thinner than a thickness of the front surface side electrode. The thickness of the plating film155may be 1.0 μm or more, and may be 6.0 μm or less.

In the top view, a contact region152between the plating film155and the front surface side electrode may cover the temperature sensing portion178. In the semiconductor device of the comparison example, the anode wiring or the cathode wiring is provided above the temperature sensing portion, and the front surface side electrode and the plating film155are not provided.

A solder layer160is provided on an upper surface of the plating film155. The solder layer160is electrically connected to an external control terminal. The solder layer160may form a lead frame region that is externally connected by a lead frame.

The protective film150is provided above the front surface side electrode. The protective film150may be in contact with an upper surface of the emitter electrode52. By providing the protective film150, it is possible to protect the upper surface of the semiconductor device100. The protective film150is, as an example, a polyimide film.

The protective film150of the present example is provided to be spaced apart from the solder layer160. Typically, the protective film150made of an organic material has a coefficient of thermal expansion different from those of the plating film155and the solder layer160which are made of the metal materials, and thus when there is a triple point where total three of the protective film150, the plating film155, and the solder layer160are in contact, a stress concentration may occur at the triple point. The protective film150of the present example is provided to be spaced apart from the solder layer160, and thus it is possible to avoid the occurrence of the triple point, and to prevent the stress concentration from occurring.

FIG.4Ashows an example of a cross section taken along lines a-a′ shown inFIG.1andFIG.3B. The cross section taken along the lines a-a′ is a YZ cross section passing through the temperature sensing portion178. The temperature sensing portion178of the present example has the PN junction in the XZ plane, but is not limited to this. That is, the temperature sensing portion178may have the PN junction in a different direction.

As an example, the temperature sensing portion178includes one semiconductor region of the first conductivity type and one semiconductor region of the second conductivity type. The temperature sensing portion178may include a plurality of semiconductor regions of the first conductivity type and a plurality of semiconductor regions of the second conductivity type. As an example, the temperature sensing portion178has a junction of a PNP type.

The temperature sensing portion178may not have the PN junction as long as temperature sensing portion178is made of polysilicon. A resistance value of polysilicon shows the temperature dependence, and thus it is possible for the temperature sensing portion178to measure the temperature of the semiconductor device100. The resistance value in the temperature sensing portion178is higher when the temperature sensing portion178has the PN junction, than when the temperature sensing portion178does not have the PN junction, and thus it is possible to further enhance a precision of the temperature measurement.

In the present example, the anode pad174and a P type region of the temperature sensing portion178are connected, and the cathode pad176and an N type region of the temperature sensing portion178are connected, respectively. The anode pad174and the N type region of the temperature sensing portion178may be connected, and the cathode pad176and the P type region of the temperature sensing portion178may be connected, respectively. In this manner, when the temperature sensing portion178detects the temperature, the direction of the current flowing through the PN junction is reversed, and the resistance value at the PN junction of the temperature sensing portion178becomes high, and thus it is possible to enhance a precision of the temperature sensing portion178.

FIG.4Bshows a modification example of the cross section taken along the lines a-a′ inFIG.1andFIG.3B. InFIG.4B, a difference fromFIG.4Awill be described.

As shown inFIG.4B, the gate runner46may be provided to partially overlap the temperature sensing portion178in the top view. That is, the temperature sensing portion178may be provided to face the gate runner46with the first dielectric layer381being sandwiched therebetween. The temperature sensing portion178may be provided above the gate runner46. In an example, both of the P type region and the N type region included in the temperature sensing portion178are provided above the gate runner46. In this way, by providing the interlayer dielectric film380between the gate runner46and the temperature sensing portion178, it is possible to enhance a degree of freedom of each wiring inside the interlayer dielectric film380.

FIG.4Cshows an example of a cross section taken along lines b-b′ shown inFIG.1andFIG.3B. The cross section taken along the lines b-b′ is a YZ cross section passing between temperature sensing portion178and the anode pad174. The semiconductor device100of the present example may have a structure in which the gate oxide film384, the gate runner46, the first dielectric layer381, the conductive wiring portion181, the second dielectric layer382, and the third dielectric layer383are stacked in order, above the front surface of the semiconductor substrate10.

The entire peripheries of the cross sections of the first wiring180and the second wiring182are covered with the interlayer dielectric film380which is non-doped. That is, the entire periphery of the conductive wiring portion181in a cross section perpendicular to the extension direction is covered with the first dielectric layer381and the second dielectric layer382. In this way, by covering the conductive wiring portion181with the interlayer dielectric film380which is non-doped, it is possible to protect the conductive wiring portion181from the contamination, and stabilize the characteristic of the temperature sensing portion178.

The conductive wiring portion181may be made of polysilicon, or may be made of a metal material with a high melting point. When the conductive wiring portion181is made of polysilicon, amounts of dopants that are contained in the conductive wiring portion181and the temperature sensing portion178may be the same as or different from each other. The resistance value of the conductive wiring portion181is lower when the conductive wiring portion181is made of the metal material, than when the conductive wiring portion181is made of polysilicon, and thus it is possible to enhance a precision of the temperature detection of the temperature sensing portion178.

The cross sectional area of the conductive wiring portion181is greater than that of the PN junction of the temperature sensing portion178. That is, in the present example, the cross sectional area (an area) of the PN junction of the temperature sensing portion178in the XZ plane is smaller than the cross sectional area of the conductive wiring portion181in an YZ plane. In this manner, the resistance value at the PN junction of the temperature sensing portion178becomes higher than the resistance value of the conductive wiring portion181, and even when the conductive wiring portion181is made of polysilicon, it is possible to enhance a precision of the temperature sensing portion178.

The gate runner46and the conductive wiring portion181of the present example may be arranged to be partially overlapped in the top view. Both of the gate runner46and the conductive wiring portion181extend in the X axis direction; however, the gate runner46may extend in the Y axis direction. By providing the interlayer dielectric film380between the gate runner46and the conductive wiring portion181, it is possible to enhance a degree of freedom of each wiring inside the interlayer dielectric film380.

FIG.4Dshows an example of a cross section taken along lines c-c′ shown inFIG.1andFIG.3B. The cross section along the lines c-c′ is a YZ cross section passing between the temperature sensing portion178and the gate pad50.

InFIG.4D, the gate runner46electrically connected to the gate pad50is shown. The gate runner46is electrically connected to the gate trench portion40via the contact hole, and can control the operation of the semiconductor device100.

When the conductive wiring portion181is not provided above the gate runner46, the first dielectric layer381and the second dielectric layer382may not be provided above the gate runner46. An upper surface of the gate runner46may be covered with the third dielectric layer383. The second dielectric layer382is provided above the gate runner46of the present example. The gate oxide film384is provided between the gate runner46and the front surface of the semiconductor substrate10.

FIG.5shows an example of an upper surface of the semiconductor device100of the present example. InFIG.5, hatching is shown in a region where the protective film150is provided.

As shown inFIG.5, in the semiconductor device100of the present example, the connection of the temperature sensing portion178, and the anode pad174and the cathode pad176is performed inside the interlayer dielectric film380, and thus the protective film150is not provided above the temperature sensing portion178. This makes it possible to use the single emitter electrode52to control the operation of the semiconductor device100, without the front surface side electrode such as the emitter electrode52being separated by the protective film150.

In the present example, the single emitter electrode52is electrically connected to each of the active portion120-1, the active portion120-2, the active portion120-3, the active portion120-4, the active portion120-5, and the active portion120-6which are provided to be spaced apart. By using the single emitter electrode52, it is possible to control the operation of the semiconductor device100, without using a configuration of a wire or the like for connecting the emitter electrodes.

As shown inFIG.5, in the semiconductor device100of the present example, the solder layer160and the protective film150are separated from each other. This makes it possible to avoid the occurrence of the triple point in the semiconductor device100, and to prevent the stress concentration.

While the present invention has been described by way of the embodiments, the technical scope of the present invention is not limited to the above-described embodiments. It is apparent to persons skilled in the art that various modifications or improvements can be made to the above-described embodiments. It is also apparent from description of the claims that the embodiments to which such alterations or improvements are made can be included in the technical scope of the present invention.

It should be noted that the operations, procedures, steps, stages, and the like of each processing performed by an apparatus, system, program, and method shown in the claims, specification, or drawings can be realized in any order as long as the order is not indicated by “prior to,” “before,” or the like and as long as the output from a previous processing is not used in a later processing. Even if the operation flow is described using phrases such as “first” or “next” for the sake of convenience in the claims, specification, or drawings, it does not necessarily mean that the process must be performed in this order.

EXPLANATION OF REFERENCES