Integrated circuits with replacement metal gates and methods for fabricating the same

Integrated circuits and methods for fabricating integrated circuits are provided. In one embodiment, a method for fabricating integrated circuits includes forming a gate dielectric overlying a substrate, and forming a base work function layer that includes tungsten overlying the gate dielectric. The base work function layer overlies the gate dielectric in a first and second region, where the first region is one of a pFET region or an nFET region and the second region is the other of the pFET region or the nFET region. A mask is formed over the first region, and then the second region is exposed. A work function value of the base work function layer in the second region is altered to produce a modified work function layer. The mask is removed from the over the first region, and a gate electrode is formed overlying the base and modified work function layers.

TECHNICAL FIELD

The present disclosure generally relates to integrated circuits and methods for fabricating integrated circuits, and more particularly, relates to integrated circuits having replacement metal gate stacks and methods for fabricating such integrated circuits.

BACKGROUND

As the critical dimensions of integrated circuits continue to shrink, the fabrication of gate electrodes for complementary metal-oxide-semiconductor (CMOS) transistors has advanced to replace silicon dioxide gate dielectrics and polysilicon gate electrodes with high-k dielectric material and electrically conductive materials such as metals, respectively. A replacement metal gate (RMG) process is often used to form the gate electrode. An exemplary replacement metal gate process includes forming a sacrificial gate oxide and a sacrificial polysilicon gate between a pair of spacers on a semiconductor substrate. After further processing steps, such as an annealing process, the sacrificial gate oxide and sacrificial polysilicon gate are removed and the resulting trench is filled with a high-k dielectric and one or more replacement metal layers. The replacement metal layers can include work function materials as well as a metallic gate electrode, which may include aluminum (Al), tungsten (W), and/or other metals.

Processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating (EP), and electroless plating (ELP) may be used to form the one or more replacement metal gate layers that form the replacement metal gate stack. Unfortunately, as critical dimensions decrease, issues such as trench overhang and void formation become more prevalent and pose a greater challenge to overcome. This is due to the smaller gate dimensions. Specifically, at smaller dimensions, the aspect ratio of the trench used to form the replacement metal gate electrode becomes higher as the replacement metal layers form on the trench sidewalls. Metallization of high aspect ratio trenches quite often results in void formation.

Additional issues arise with lateral scaling. For example, lateral scaling presents issues for the formation of contacts. When the contacted gate pitch is reduced to about 64 nanometers (nm), it is difficult to form contacts between the gate lines while maintaining reliable electrical isolation properties between the gate line and the contact. Self-aligned contact (SAC) methodology has been developed to address this problem. Conventional SAC approaches involve recessing the replacement metal gate stack, which includes recessing both work function metal liners and a gate electrode. Work function metal lines may include titanium nitride (TiN), titanium silicon nitride (TiSixNy), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), and/or titanium aluminum nitride (TiAlN), and gate electrode materials may include aluminum (Al), tungsten (W), cobalt (Co), copper (Cu) or the like. A dielectric cap may be formed overlying the replacement metal gate stack followed by chemical mechanical planarization (CMP). To set the correct work function for the device, work function layers with varied thicknesses ranging from about 1 to 7 nanometers (nm) are typically used. The work function layers may include a variety of materials, as mentioned above, with a total thickness of more than 5 nm. As gate length continues to scale down, for example for sub-15 nm gates, the replacement metal gate electrode structure is so narrow that it may be “pinched-off” by the work function layers, leaving little or no space remaining for the lower-resistance metallic gate electrode. The reduced space for the gate electrode increases the overall electrical resistance of the replacement metal gate stack. This often results in high resistance issues for devices with small gate lengths, and also causes problems in the SAC replacement metal gate recess process.

Conventional replacement metal gate stacks may suffer from significant threshold voltage variations due in part to variation in the thicknesses of the work function layers. Further, the diffusion of aluminum, oxygen, or fluorine (where fluorine is often used in tungsten deposition processes) into the work function layers and into the high-k gate dielectric can alter the threshold voltage of the replacement metal gate stacks. Conventional processing of titanium nitride and subsequent plasma treatment that can also cause threshold voltage variations of the replacement metal gate stacks. In addition, conventional replacement metal gate for CMOS processes may include the deposition of one work function layer(s) that are appropriate for a p-type field effect transistor (“pFET”) and one or more work function layer(s) that are appropriate for an n-type field effect transistor (“nFET”), and this process may involve the removal of the work function layer that is appropriate for one type of FET to prepare for deposition of the work function layer that is appropriate for the other type of FET. The removal steps often cause non-uniformity issues and surface modification in the FET region, which can also result in threshold voltage variation of the replacement metal gate stacks.

Accordingly, it is desirable to provide improved integrated circuits having replacement metal gate stacks and methods for fabricating such improved integrated circuits, particularly as aspect ratios of the replacement metal gate electrodes continue to scale down. Also, it is desirable to provide integrated circuits with replacement metal gate stacks that exhibit low gate electrode resistance and methods for fabricating such integrated circuits. Further, it is desirable to provide integrated circuits with replacement metal gate stacks that exhibit reduced threshold voltage variation and methods for fabricating such integrated circuits. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

BRIEF SUMMARY

Integrated circuits and methods for fabricating integrated circuits are provided. In one embodiment, a method for fabricating integrated circuits includes forming a gate dielectric overlying a substrate, and forming a base work function layer overlying the gate dielectric where the base work function layer includes tungsten. The base work function layer overlies the gate dielectric in a first and second region, where the first region is one of a pFET region or an nFET region and the second region is the other of the pFET region or the nFET region. A mask is formed over the first region, and then the second region is exposed. A work function value of the base work function layer in the second region is altered to produce a modified work function layer. The mask is removed from over the first region, and a gate electrode is formed overlying the base and modified work function layers.

In another embodiment, a method for fabricating an integrated circuit includes forming a gate dielectric overlying a substrate that includes a substrate surface. A base work function layer is formed overlying the gate dielectric, and a gate electrode is formed overlying the base work function layer. The gate electrode is about 30 angstroms or less from the substrate surface.

In another embodiment, an integrated circuit is provided. The integrated circuit includes a gate dielectric overlying a substrate. A modified work function layer overlies the substrate, where the modified work function layer includes indium at a concentration of about 20 weight percent or greater and tungsten at a concentration of from about 20 to about 80 weight percent, based on the total weight of the modified work function layer. A gate electrode overlies the modified work function layer.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and is not intended to limit the integrated circuits or the methods for fabricating integrated circuits claimed herein. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background or brief summary, or in the following detailed description. Embodiments of the present disclosure are generally directed to integrated circuits and methods for fabricating the same. For the sake of brevity, conventional techniques related to integrated circuit device fabrication may not be described in detail herein. Moreover, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor-based integrated circuits are well-known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. Further, it is noted that integrated circuits include a varying number of components and that single components shown in the illustrations may be representative of multiple components.

Integrated circuits having replacement metal gate stacks and methods for fabricating such integrated circuits are provided that avoid issues faced by conventional processes for forming replacement metal gate stacks. For example, the methods contemplated herein provide for the formation of integrated circuits with replacement metal gate stacks exhibiting minimized threshold voltage variation within an integrated circuit and between integrated circuits. Also, the methods contemplated herein provide for the formation of integrated circuits with replacement metal gate stacks exhibiting lower overall resistance than conventionally formed replacement metal gate stacks. For example, the methods contemplated herein utilize a common base work function layer across both nFET regions and pFET regions and chemically modify or alter the base work function layer in one of the regions to provide the appropriate work function for both regions in a single layer. As deposited, the base work function layer is appropriate for use in one of the nFET region or the pFET region. In the other region, the work function layer is chemically modified, rather than removed, so that it is appropriate for use in the other of the nFET region or the pFET region. In exemplary embodiments, the work function value of the base work function layer is modified by diffusing a work function altering element into the base work function layer.

A “work function” of a material is generally described as the energy, usually measured in electron volts (eV), needed to remove an electron from the Fermi level to a point immediately outside a solid surface of the material or the energy needed to move an electron from the Fermi level into a vacuum. Work function is a material property of any material, whether the material is a conductor, semiconductor, or dielectric. For a metal, the Fermi level lies within the conduction band, indicating that the band is filled with many freely moving electrons (based on Fermi statistics with respect to electron energy) as known to those skilled in the art. For an insulator, the Fermi level lies within the band gap, indicating an empty conduction band. For insulators, the minimum energy to remove an electron is about the sum of half the band gap and the electron affinity. For metal oxide semiconductor field effect transistor (MOSFET) devices, an effective work function for a metal on a dielectric structure is generally defined by the work function of the metal layer immediately adjacent to the dielectric of a metal-dielectric interface.

The work function of a material can be altered by diffusing an element into the material (sometimes referred to as “doping”). For example, undoped polysilicon has a work function of about 4.65 eV, whereas an exemplary polysilicon doped with boron (P-type) may have a work function of about 5.15 eV. The Fermi level of the boron doped polysilicon is close to the valence band of silicon, which may be referred to as “P-type” work function. Similarly, an N-type doped polysilicon may have a work-function of about 3.95 eV, which may be referred to as “N-type” work-function as the Fermi level is close to the conduction band of silicon. When a work function layer is used in a replacement metal gate stack, the work function layer can directly affect the threshold voltage of the transistor.

The work function layer used in replacement metal gate stacks, which is typically a metal nitride such as titanium nitride, is a parameter for setting the threshold voltage of a field effect transistor (FET), whether an nFET or pFET. In order to obtain a target electrical control of the FET devices, the work function layer used in replacement metal gate stacks should be P-type for a pFET and N-type for an nFET, and more particularly, about 5.2 eV or more and about 4.0 eV or less, respectively, for the pFET and nFET in the case of silicon.

InFIG. 1, a partially fabricated integrated circuit10is shown that includes a substrate12, where the substrate12includes semiconductor material. It is to be appreciated that various fabrication techniques may be conducted in accordance with the methods described herein to form the partially fabricated integrated circuit10as shown. As used herein, the term “semiconductor material” will be used to encompass semiconductor materials conventionally used in the semiconductor industry from which to make electrical devices. Semiconductor materials include monocrystalline silicon materials, such as the relatively pure or lightly impurity-doped monocrystalline silicon materials typically used in the semiconductor industry, as well as polycrystalline silicon materials, and silicon admixed with other elements such as germanium, carbon, and the like. In addition, “semiconductor material” encompasses other materials such as relatively pure and impurity-doped germanium, gallium arsenide, zinc oxide, glass, and the like. In many embodiments, the substrate12primarily includes a monocrystalline semiconductor material. The substrate12may be a bulk silicon wafer (as illustrated) or may be a thin layer of silicon on an insulating layer (commonly known as silicon-on-insulator or SOI, not illustrated) that, in turn, is supported by a carrier wafer. Also, the semiconductor substrate12may be planar or in the form of fin structures for use in a FinFET.

In exemplary embodiments, the semiconductor substrate12is provided with a first region14and a second region16. The first region14is one of an nFET region or a pFET region and the second region16is the other of the nFET region or the pFET region. As described below, integrated circuit fabrication processes may differ for the first and second regions14,16to form the appropriate replacement metal gate stacks for the pFET region or the nFET region. An nFET region is to include one or more nFETS and the pFET region is to include one or more pFETS. The nFET region may be formed with a P-type well region by doping the substrate12with “P” type conductivity imparting ions. The pFET region may be formed with an N-type well region by doping the substrate12with “N” type conductivity imparting ions. “N” type conductivity imparting ions primarily include ions of phosphorous, arsenic, and/or antimony, but other materials could also be used. “P” type conductivity imparting ions primarily include boron, aluminum, gallium, and indium, but other materials could also be used. Ion implantation may involve ionizing the conductivity imparting element (the dopant) and propelling the dopant ion into the substrate12under the influence of an electrical field. The substrate12may then be annealed to repair crystal damage from the ion implantation process, to electrically activate the dopants, and to redistribute the dopants within the semiconductor material. The annealing process can use widely varying temperatures, such as temperatures ranging from about 500 degrees centigrade (° C.) to about 1,200° C. The terms first and second region14,16are used to generally describe two primary embodiments where the work function for nFETs are established first (nFET first embodiments), and also describe embodiments where the work function for the pFETs are established first (pFET first embodiments).

In the embodiment illustrated inFIG. 1the substrate12is provided with a substantially planar substrate surface18. One or more sacrificial gates20(sometimes referred to as dummy gates) are formed overlying the substrate surface18. As referred to herein, the term “overlying” is used to encompass both “over” and “on”, with features that “overlie” other features being disposed over and possibly directly upon the underlying features. In this regard, the overlying feature may directly contact the underlying feature or it may lie over the underlying feature such that another material layer is interposed between the overlying feature and the underlying feature. A sacrificial cap22may overlie the sacrificial gate20and serve as a hard mask for the sacrificial gate20. The sacrificial gate20and sacrificial cap22can be fabricated using conventional processing techniques such as material deposition, photolithography, and etching. In one example, the material used for the sacrificial gate20is formed overlying the substrate surface18, and then a hard mask material used for the sacrificial cap22is formed overlying the sacrificial gate material. In an exemplary embodiment, the sacrificial gate material includes a polycrystalline silicon material, and the hard mask material includes a silicon nitride material or a silicon oxide material, but other materials can be used in alternate embodiments. As referred to herein, a material or component that includes a recited element/compound includes the recited element/compound in an amount of at least 10 weight percent or more based on the total weight of the material or component unless otherwise indicated. In typical embodiments, the sacrificial gate materials and the sacrificial cap materials are sequentially blanket deposited on the substrate surface18in a conformal manner (using, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD) or another suitable deposition technique). A resulting sacrificial cap material mask layer (not illustrated) is photolithographically patterned to form a sacrificial gate etch mask that serves as the sacrificial caps22, and the underlying sacrificial gate material is anisotropically etched into the desired topology that is defined by the sacrificial caps22. The resulting sacrificial gates20and sacrificial caps22include sacrificial gate side walls24.

After the sacrificial gates20and sacrificial caps22have been formed, the process may continue by forming spacers26adjacent to the sacrificial gate side walls24. In this regard,FIG. 2depicts the state of the partially fabricated integrated circuit10after the formation of the spacers26. The spacers26may be formed adjacent to and on the sacrificial gate side walls24. In an exemplary embodiment, formation of the spacers26includes conformally depositing a spacer material overlying the sacrificial gate20, the sacrificial cap22, and the substrate surface18to form a spacer layer (not illustrated). The spacer layer includes an appropriate insulator, such as silicon nitride. The spacer material may be deposited by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), semi-atmospheric chemical vapor deposition (SACVD), plasma enhanced chemical vapor deposition (PECVD), or other techniques. The spacer material is deposited to a thickness so that, after anisotropic etching, the spacers26have a thickness that is appropriate for the subsequent etching steps described below. Thereafter, the spacer layer is anisotropically and selectively etched to define the spacers26. In practice, the spacer layer can be etched by, for example, reactive ion etching (RIE) using a suitable etching chemistry.

After the spacers26have been formed, other processing may be performed to form desired source/drain regions (not illustrated) in the substrate12, such as trench etching in the substrate12and epitaxial deposition of source/drain material, stressing techniques, and ion implantations optionally using the sacrificial gates20as ion implantation masks. The fabrication process may proceed by forming dielectric areas28adjacent to and between the spacers26, as illustrated in an exemplary embodiment inFIG. 3. At this point in an exemplary fabrication process, previously unoccupied space around the spacers26has been filled with the dielectric material of the dielectric areas28, such as by blanket deposition.

In certain embodiments, the dielectric areas28are formed from an interlayer dielectric (ILD) material that is initially blanket deposited overlying the substrate12, the sacrificial gates20and sacrificial caps22, and the spacers26using a technique such as CVD, LPCVD, or PECVD. The dielectric material is deposited such that it fills the spaces adjacent to the spacers26and such that it covers the spacers26and the sacrificial caps22. Thereafter, the deposited dielectric material may be planarized using, for example, a chemical mechanical polishing (CMP) tool and such that the sacrificial caps22serve as a polish stop indicator to produce the dielectric areas28.

The exemplary fabrication process proceeds as illustrated inFIG. 4by removing the sacrificial caps22and the sacrificial gates20while leaving the spacers26intact or at least substantially intact. Accordingly, removal of the sacrificial gates20exposes the substrate surface18between the spacers26in a trench30formed between adjacent spacers26and dielectric areas28. As shown, the trenches30are defined by the spacers26and the substrate surface18. In an exemplary embodiment, the sacrificial cap22and the sacrificial gate20are removed by sequentially or concurrently etching in a selective manner, and stopping at the desired point, such as a top surface of the substrate12. The etching chemistry and technology used for this etching technique is chosen such that the spacers26and the dielectric areas28are not etched or are only etched by an insignificant amount. Etching of the sacrificial gates20may be controlled to stop at the substrate surface18. The etching process may be a dry etch, such as a reactive ion etch, a wet etch, or a combination of the two.

As illustrated in an exemplary embodiment inFIG. 5, a gate dielectric32is formed. In an exemplary embodiment, the gate dielectric32includes a high-k dielectric material that is conformally deposited over the partially fabricated integrated circuit10. As used herein, “high k” denotes a dielectric material featuring a dielectric constant (k) higher than about 3.9. The gate dielectric32is formed over the first region14and the second region16, adjacent to the spacers26, overlying the substrate surface18within the trenches30, and over the dielectric area28outside of the trenches30. Exemplary high-k dielectric materials that may be included in the gate dielectric32include hafnium oxide (HfO2), hafnium silicate (HfSiOx), hafnium oxide silicate nitride (HfOxSiyNz), aluminum oxide (Al2O3), titanium oxide (TiO2), zirconium oxide (ZrO2), lanthanum nitride (LaN) and lanthanum oxide (La2O3), although other high-k dielectric materials are also contemplated. In an exemplary embodiment, the gate dielectric32is formed by ALD. The gate dielectric32may have a thickness of from about 14 angstroms (Å) to about 18 Å, such as about 15 Å, but other thicknesses are also possible.

After formation of the gate dielectric32, the exemplary method continues inFIG. 6with formation of a bottom cap layer34. The exemplary bottom cap layer34may be conformally formed over the gate dielectric32, both within and outside of the trenches30. An exemplary bottom cap layer34is formed from tungsten carbide or titanium nitride, although other suitable materials may be used. An exemplary process for forming the bottom cap layer34is ALD. An exemplary tungsten carbide bottom cap layer34may be formed with a thickness of from about 8 Å to about 15 Å, such as about 10 Å. An exemplary titanium nitride bottom cap layer34may be formed with a thickness of from about 5 Å to about 25 Å, such as about 10 Å. Other thicknesses are also possible in alternate embodiments.FIG. 6illustrates the structure of the partially fabricated integrated circuit10after formation of the bottom cap layer34.

FIGS. 7-14illustrate exemplary embodiments of further processing for the partially fabricated integrated circuit10ofFIG. 5to form replacement metal gate stacks. A work function layer(s) for the pFET may be formed before the work function layer(s) for the nFET, or the work function layer(s) for the nFET may be formed before the work function layer(s) for the pFET in alternate embodiments, and the materials and techniques may vary for the different embodiments. The materials and techniques used in the processing ofFIGS. 7-14may differ depending on whether the work function layer for the nFET or for the pFET is formed first. Each embodiment will be discussed herein.

The exemplary fabrication process proceeds by forming a work function layer or a plurality of work function layers such that the replacement metal gate stacks have desired electrical characteristics. InFIG. 7, a base work function layer40is formed overlying the bottom cap layer34. The base work function layer40may include a single work function material or a plurality of work function materials in various embodiments. An exemplary base work function layer40contains tungsten (W). When the work function for the pFET region is established first, an exemplary base work function layer40includes tungsten nitride, or be nitride rich. The work function of tungsten nitride may range from about 4.5 eV to about 5.0 eV and becomes larger (more P-type) with increased nitrogen content. Tungsten and nitrogen content can be controlled through the deposition process conditions as is well known. When the work function for the nFET region is established first, the exemplary base work function layer40may include tungsten carbide (WCx), or be carbon rich. For tungsten carbide, the work function decreases (becomes more N-type) with increased carbon content, and the carbon content can be controlled through the deposition process. The work function for tungsten carbide may range from about 3.5 eV to about 4.0 eV. The base work function layer40may also include tungsten nitride carbide (WNyCx), where the concentration of the nitrogen and carbon are adjusted for a desired work function value that is appropriate for whichever of the nFET or pFET region is formed first, where the region formed first is the first region14. The exemplary base work function layer40may be conformally formed over the bottom cap layer34. In an exemplary embodiment, the base work function layer40is formed by ALD with a thickness of from about 5 Å to about 20 Å, such as about 10 Å. As illustrated, the base work function layer40is formed over both the first region14and the second region16, so the base work function layer40overlies both the nFET region and the pFET region.

In an embodiment illustrated inFIG. 8, a mask42is formed and patterned to cover the first region14and expose the second region16. In an exemplary embodiment, amorphous silicon may be deposited over the first and second regions14,16, and photoresist (not illustrated) may be deposited and processed conventionally to selectively remove the amorphous silicon from the second region16such that the mask42includes amorphous silicon. The photoresist may then be removed, such as with a wet strip or other known techniques. InFIG. 8, the second region16is exposed so that it may be chemically modified to change the work function value of the base work function layer40to an appropriate degree for the nFET or the pFET associated with the second region16.

FIGS. 9 and 10provide alternative exemplary methods for chemically modifying the base work function layer40overlying the second region16. In many embodiments, a work function altering element is diffused into the base work function layer40overlying the second region16to change its work function value. InFIG. 9, an implantation process is performed to diffuse ions44by implantation into the exposed portion of the base work function layer40overlying the second region16. The base work function layer40is transformed into a modified work function layer46when the work function altering element is diffused into the base work function layer40, so the material that formed the base work function layer40remains and is a part of the modified work function layer46. As shown, the ions44are implanted into the exposed portion of the base work function layer40overlying the second region16to form the modified work function layer46while the mask42inhibits implantation into the base work function layer40overlying the first region14. In an exemplary process where the second region16is a pFET region, silicon ions may be implanted to form the modified work function layer46, where the silicon ions are at a concentration of from about 1×1012to about 1×1019atoms/cm3, but other concentrations are also possible. In this embodiment, silicon is the work function altering element. The work function value of the modified work function layer46can be controlled and tuned by controlling the concentration of silicon ions diffused into the modified work function layer46. Tungsten nitride that includes silicon ions may have a work function value higher than the work function value of tungsten nitride that does not include silicon (i.e, more toward a P-type work function material), or that includes silicon at lower concentrations. The implantation may be performed with silicon ions at an energy of from about 0.1 kilo electron volts (KeV) to about 2 KeV or less, where these relatively low implantation energies may provide good control of the silicon on the surface of the work function layer. Alternatively, in embodiments where the second region16is a pFET, nitrogen may be diffused into the exposed modified work function layer46with a nitrogen plasma treatment or plasma assisted doping at an energy of from about 0.1 to about 2 KeV. The resulting nitrogen concentration may be from about 1×1012to about 1×1019atoms/cm3. In another embodiment, the nitrogen atoms may be introduced into the base work function layer40by a nitrogen plasma treatment with a low bias voltage, such as about 100 volts or less, and an operating pressure of from about 10 to about 100 torr. After ion implantation or plasma treatment, the mask42may be removed.

In other embodiments, the base work function layer40overlying the second region16may be modified by alternative techniques as illustrated inFIG. 10. InFIG. 10, a work function altering layer50is formed over the mask42and the exposed portion of the base work function layer40overlying the second region16. The work function altering layer50includes one or more work function altering elements, and the work function altering elements are diffused into the base work function layer40overlying the second region16to form the modified work function layer46, as illustrated inFIG. 11. The type and concentration of the work function altering element, and the degree of diffusion of the work function altering element into the modified work function layer46, can be adjusted to tune the work function value of the modified work function layer46. The remaining work function altering layer50and the mask42may be removed after the work function altering elements are diffused into the base work function layer40. A wet strip or dry etching may be used in various embodiments. The work function altering element(s) can be diffused into the modified work function layer46with an anneal, and the parameters of the anneal may be adjusted based on the work function altering element(s), the desired concentration, the desired degree of diffusion, etc. The anneal may be performed at a wide variety of points in the manufacturing process, as described more fully below.

For an embodiment in which the second region16is a pFET region (i.e., the base work function layer40includes an N-type work function material such as tungsten carbide for an nFET first embodiment), an exemplary work function altering layer50to move towards a more P-type work function includes nickel, platinum, palladium, cobalt, or others as the work function altering element. In an exemplary embodiment, the work function altering layer50is deposited by PVD, metal organic chemical vapor deposition (MOCVD), or ion implantation at a thickness of from about 3 Å to about 25 Å, such a thickness of about 5 to about 10 Å. Nickel may be present in the work function altering layer50at a concentration of about 50 weight percent or more. As such, nickel may be present in the modified work function layer46at a concentration of from about 1 to about 5 weight percent, based on the total weight of the modified work function layer46. The diffusion of nickel into a base work function layer40to form the modified work function layer46may raise the work function value (i.e., make the work function layer more P-type) from about 4.3 electron volts or less to a work function value of more than about 4.9 electron volts.

In embodiments where the second region16is an nFET region i.e., the base work function layer40includes a P-type work function material such as tungsten nitride for a pFET first embodiment), the work function altering layer50that moves more towards an N-type work function includes a work function altering element selected from one or more of indium (In), lanthanum (La), strontium (Sr), and aluminum (Al), such as one or more of indium, lanthanum, and strontium. In some embodiments, the dominant work function altering element is indium, and the indium may be present at a concentration of from about 50 weight percent or more in the work function altering layer50, based on the total weight of the work function altering layer50. As used herein, a “dominant work function altering element” is the work function altering element with the highest concentration in the modified work function layer46. In alternate embodiments, lanthanum, strontium, or aluminum may be present in the work function altering layer50at concentrations of about 50 weight percent or more, based on the total weight of the work function altering layer50. The work function altering layer50may have a thickness of from about 3 Å to about 25 Å, such a thickness of about from about 5 to about 10 Å, and may be formed by sputtering or other deposition techniques. The work function altering elements for an nFET (In, La, Sr, or Al) may be diffused into the base work function layer40that includes tungsten nitride. The diffusion of In, La, Sr, and/or Al into the base work function layer40to form the modified work function layer46may lower the work function value (i.e., make the work function value more N-type) from about 4.5 eV or more to a work function value of less than about 4.0 eV.

In some embodiments, P-type or N-type work function altering element ions may be incorporated into a base work function layer40that includes WCxor WCxNyby sputter deposition. By properly controlling the sputter power and pressure (such as with a controlled ionization potential), some of the ions are incorporated into the base work function layer40or are incorporated at the interface or surface. Excess P-type or N-type metallic work function altering elements that form over the newly created modified work function layer46can be selectively etched away leaving the WCxor WCxNywith either P-type or N-type work function metals incorporated therein. A laser based anneal can then be performed to re-distribute the diffused species either in the bulk or at the interface of the modified work function layer46.

After forming the work function altering layer50, an annealing process is performed to diffuse the work function altering element(s) into the modified work function layer46, as illustrated in an exemplary embodiment inFIG. 11, with continuing reference toFIG. 10. The remaining work function alternating layer50and top cap layer42may be removed after the annealing that forms the work function altering layer46, such as with a wet strip or dry etching, as mentioned above. The work function altering layer50may no longer be present in some embodiments because it has diffused into the modified work function layer46. For example, the annealing process where indium is the work function altering element may include heating the partially fabricated integrated circuit to a temperature of from about 400° C. to about 900° C., such as about 900° C., for a duration of from about 0.1 milliseconds to about 10 seconds. An exemplary anneal process may be a flash anneal, spike anneal or laser based anneal. The annealing process causes diffusion of the work function altering element from the work function altering layer50into the modified work function layer46overlying the second region16. As a result, the work function value of the modified work function layer46is changed such the modified work function layer46can be used with one of an nFET or a pFET, and the base work function layer40that remains overlying the first region14can be used with the other of the nFET or the pFET. In an exemplary embodiment, the modified work function layer46has a concentration of about 20 weight percent or more, such as from about 20 weight percent to about 80 weight percent of one or more of indium, lanthanum, strontium, or aluminum after the anneal, but the modified work function layer46may have a concentration of about 10 weight percent or greater or about 30 weight percent or greater of one or more of indium, lanthanum, strontium or aluminum after the anneal in alternate embodiments. The modified work function layer46also has a concentration of from about 20 to about 80 weight percent tungsten after the anneal.

Reference is made to an exemplary embodiment illustrated inFIG. 12, with continuing reference toFIGS. 10 and 11. A top cap layer52may optionally be formed overlying the base work function layer40and the modified work function layer46in the first and second regions14,16. The top cap layer52may include titanium nitride, and may have a thickness of from about 5 Å to about 20 Å, such as about 10 Å. The top and bottom cap layers52,34may help prevent the work function altering element(s) from migrating out of the area between the top and bottom cap layers52,34, so essentially all of the work function altering element(s) in the work function altering layer50may be diffused into the modified work function layer46overlying the second region16. The integrated circuit10may then optional be cleaned, such as with a nitrogen trifluoride plasma treatment to remove undesired oxides.

The top cap layer52, the modified work function layer46, the base work function layer40, and the bottom cap layer34may act as diffusion barriers that help reduce or eliminate aluminum or fluorine diffusion from the gate electrode60into the gate dielectric32. The anneal that diffuses the work function altering element into the base work function layer40may be performed at almost any point of time after the work function altering layer50is formed, as long as enough heat is supplied to the work function altering layer50to diffuse the work function altering elements and form the modified work function layer46.

InFIG. 13, a gate electrode60is formed within the trench30and overlying the dielectric area28. The gate electrode60is deposited to form a conductive core overlying the base work function layer40in the first region and the modified work function layer46in the second region. Several fill materials can be used for the gate electrode60as long as the fill materials are electrically conductive. As used herein, an “electrically insulating material” is a material with a resistivity of about 1×104ohm meters or more, and an “electrically conductive material” is a material with a resistivity of about 1×104ohm meters or less. Exemplary materials for the gate electrode60include tungsten, aluminum, cobalt, or copper. Low resistance tungsten may be used for the gate electrode60in some embodiments, where low resistance tungsten may be deposited by a CVD process. In other embodiments, the gate electrode60may be deposited by ALD, a nitrogen assisted CVD process, or another conformal process.

Overburden is removed in an exemplary embodiment illustrated inFIG. 14to form the replacement metal gate stacks70over each of the first and second regions14,16. The overburden may be removed with a chemical mechanical planarization (CMP) process in some embodiments. The planarization process may remove portions of the gate dielectric32, the bottom cap layer34, the base work function layer40and the modified work function layer46, the top cap layer52, and the gate electrode60located over the top of trenches30and overlying the dielectric area28. The replacement metal gate stacks70include the gate electrode60, the top and bottom cap layers34,52, and the base work function layer40or the modified work function layer46. As such, the replacement metal gate stacks70include all electrically conductive materials positioned between the spacers26. The replacement metal gate stacks70have a gate length72measured from the gate dielectric32adjacent to one spacer26across the replacement metal gate stack70to the gate dielectric32adjacent to the next spacer26. The gate length72may be from about 120 Å to about 300 Å, or about 240 Å or less in other embodiments. The top and bottom cap layers52,34may have a combined thickness of about 20 Å, and the thickest of the base work function layer40or the modified work function layer46may have a thickness of about 15 Å. As such, the gate electrode60may have a thickness along the gate length72of from about 85 Å to about 265 Å, or a thickness along the gate length72of about 215 Å or less. A work function thickness74, as measured from the gate dielectric32to the gate electrode60, may be about 50 Å or less, or about 40 Å or less, or about 35 Å or less in various embodiments. As such, the gate electrode60may be thicker than in traditional FETs produced with thicker work function thicknesses74. Therefore, the gate electrode60is less likely to form voids during producing and has a lower electrical resistance than traditional FETs of similar overall dimensions but with thicker work function thicknesses. Furthermore, the gate electrode60is about 50 Å or less, or about 40 Å or less, or about 35 Å or less in various embodiments from the gate dielectric32.

After formation of the replacement metal gate stacks70, further processing may be performed to complete the integrated circuit10. For example and although not shown, back-end-of-line processing may involve the formation of gate caps, deposition of interlayer dielectric materials, formation of contacts, formation of interconnects between devices on the substrate12, etc.

The integrated circuits10and methods for fabricating integrated circuits10described herein provide for replacement metal gate stacks70having improved threshold voltage uniformity, i.e., reduced threshold voltage variability, compared to more traditional replacement metal gate stacks (i.e., replacement metal gate stacks that do not include tungsten in the work function layers.) Specifically, conventional material deposition processes that increase threshold voltage variability, such as plasma treatment of titanium nitride, are avoided in accordance with the techniques described herein. Further, the methods described herein may exhibit a reduction in deposition processes (i.e., use of fewer layers), compared to more traditional replacement metal gate stacks. Also, the methods described herein avoid the removal of a work function layer from either the first or second region14,16, and instead modifies the work function layer in the second region16to allow for its use therein. Further, the materials used for the bottom and top cap layers34,52and/or the base and modified work function layers46,40may provide for better etch selectivities as compared to processing for more traditional replacement metal gate stacks. The materials used for the bottom and top cap layers34,52and/or the base and modified work function layers46,40may also be better diffusion barriers against aluminum and fluorine diffusion as compared to processing for more traditional replacement metal gate stacks.