Memory device and method of fabricating the same

A memory device including a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface, the second top surface being lower than the first top surface with respect to the substrate, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough, a first conductive pattern filling the first through hole, a second conductive pattern at least partially filling the second through hole, a magnetic tunnel junction pattern on the first conductive pattern, and a contact plug coupled to the second conductive pattern may be provided. Further, a method of fabricating the memory device also may be provided.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2015-0118177, filed on Aug. 21, 2015, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND

Example embodiments of the inventive concepts relate to memory devices and/or methods of fabricating the same, and in particular, to memory devices including a magnetic tunnel junction and methods of fabricating the same.

Due to increasing demands for high speed, low power electronic devices, a faster operating speed and/or a lower operating voltage are desired for memory devices to be in the electronic devices. Magnetic memory devices have been suggested as a candidate device to satisfy such demands. For example, the magnetic memory device can provide, for example, reduced latency and/or non-volatility. Thus, the magnetic memory device is emerging as a next-generation memory device.

The magnetic memory device may include a plurality of magnetic tunnel junctions (MTJ), each of which includes two magnetic layers and a tunnel barrier layer interposed therebetween. Resistance of the magnetic tunnel junction may vary depending on magnetization directions of the two magnetic layers. The resistance of the magnetic tunnel junction is higher when magnetization directions of the magnetic layers are anti-parallel to each other than when they are parallel to each other. This difference in resistance can be used as a data storing mechanism for the magnetic memory device.

Recently, a spin-transfer-torque magnetic random access memory (STT-MRAM) is regarded as a promising high-density memory device because this device can perform a write operation with less current, even when a magnetic memory cell is scaled down.

SUMMARY

Some example embodiments of the inventive concepts provide a highly reliable memory device.

Some example embodiments of the inventive concepts provide a method of fabricating a highly reliable memory device.

According to an example embodiment, a memory device includes a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface, the second top surface being lower than the first top surface with respect to the substrate, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough, a first conductive pattern filling the first through hole, a second conductive pattern at least partially filling the second through hole, a magnetic tunnel junction pattern on the first conductive pattern, and a contact plug coupled to the second conductive pattern.

In some example embodiments, a top surface of the second conductive pattern may be one of substantially coplanar with and under the second top surface of the second region of the insulating layer.

In some example embodiments, the memory device may further include a protection pattern on the second conductive pattern.

In some example embodiments, the first conductive pattern may include a metallic material and the protection pattern may include a metallic oxide material.

In some example embodiments, a top surface of the protection pattern may be one of substantially coplanar with and above the second top surface of the second region of the insulating layer.

In some example embodiments, the memory device may further include an insulating cover layer covering a sidewall of the magnetic tunnel junction pattern, which includes a first magnetic pattern, a second magnetic pattern, and a tunnel barrier pattern interposed therebetween.

According to an example embodiment, a memory device includes a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface recessed with respect to the first top surface, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough, a first conductive pattern filling the first through hole, a second conductive pattern at least partially filling the second through hole, a protection pattern on the second conductive pattern, a magnetic tunnel junction pattern electrically connected to a top surface of the first conductive pattern, and a contact plug electrically connected to a top surface of the second conductive pattern, while penetrating the protection pattern such that a residual portion of the protection pattern remains around a bottom portion of the contact plug.

In some example embodiments, the first conductive pattern may include a metallic material and the protection pattern may include a metallic oxide material.

In some example embodiments, the top surface of the second conductive pattern may be one of substantially coplanar with and under the second top surface of the second region of the insulating layer.

In some example embodiments, a top surface of the protection pattern may be one of substantially coplanar with and above the second top surface of the second region of the insulating layer.

In some example embodiments, the memory device may further include an insulating cover layer covering a sidewall of the magnetic tunnel junction pattern, and the magnetic tunnel junction pattern may include a first magnetic pattern, a second magnetic pattern, and a tunnel barrier pattern interposed therebetween. The insulating cover layer may include a same material as the protection pattern.

According to an example embodiment, a magnetic memory device includes a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface, a second region having a second top surface, and a third region having a third top surface, the third top surface being lower than the first and second top surfaces with respect to the substrate, the first, second, and third regions including first, second, and third through holes penetrating therethrough, respectively, a first conductive pattern and a second conductive pattern filling the first and second through holes, respectively, a third conductive pattern at least partially filling the third through hole, a first magnetic tunnel junction pattern including a first electrode, a second electrode, and a first tunnel barrier pattern interposed therebetween, the first electrode electrically connected to the first conductive pattern, a second magnetic tunnel junction pattern including a third electrode, a fourth electrode, and a second tunnel barrier pattern interposed therebetween, the third electrode electrically connected to the second conductive pattern, and a contact plug electrically connected to the third conductive pattern.

In some embodiments, the first and second electrodes of the first magnetic tunnel junction pattern may be a fixed pattern and a free pattern of the first magnetic tunnel junction pattern, respectively, and the third and fourth electrodes of the second magnetic tunnel junction pattern may be a fixed pattern and a free pattern of the second magnetic tunnel junction pattern, respectively.

In some example embodiments, the magnetic memory device may further include a first bit line electrically connected to the free pattern of the first magnetic tunnel junction pattern, and a second bit line connected to the fixed pattern of the second magnetic tunnel junction pattern.

In some example embodiments, the magnetic memory device may further include an interconnection pattern electrically connecting the free pattern of the second magnetic tunnel junction pattern to the contact plug.

In some example embodiments, the magnetic memory device may further include a first selection transistor electrically connected to the first conductive pattern, and a second selection transistor electrically connected to the third conductive pattern.

In some example embodiments, the magnetic memory device may further include a common source line connected in common to source regions of both the first selection transistor and the second selection transistor.

In some example embodiments, the magnetic memory device may further include a protection pattern on the third conductive pattern.

In some example embodiments, the first and second conductive patterns may include a metallic material, the protection pattern may include a metallic oxide material, and the contact plug may be provided through the protection pattern such that the protection pattern remains at around a bottom portion of the third conductive pattern.

In some example embodiments, a top surface of the protection pattern may be one of substantially coplanar with and above the third top surface of the third region of the insulating layer.

According to an example embodiment, a magnetic memory device includes a substrate, a first level structure including a first insulating layer on the substrate, the first insulating layer including a first region having a first top surface and a second region having a second top surface, the second top surface being lower than the first top surface with respect to the substrate, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough, a first conductive pattern filling the first through hole, a second conductive pattern at least partially filling the second through hole, a first magnetic tunnel junction pattern electrically connected to the first conductive pattern, and a first contact plug electrically connected to the second conductive pattern, and a second level structure on the first level structure, the second level structure including, a second insulating layer including a third region having a third top surface and a fourth region having a fourth top surface, the third top surface being lower than the fourth top surface with respect to the substrate, the third region including a third through hole penetrating therethrough, the fourth region including a fourth through hole penetrating therethrough, a third conductive pattern at least partially filling the third through hole and electrically connected to the first magnetic tunnel junction pattern of the first level structure, a fourth conductive pattern filling the fourth through hole and connected to the first contact plug of the first level structure, a second magnetic tunnel junction pattern electrically connected to the fourth conductive pattern, and a second contact plug electrically connected to the third conductive pattern.

In some example embodiments, the magnetic memory device may further include a first bit line electrically connected to the second contact plug, and a second bit line electrically connected to the second magnetic tunnel junction pattern.

In some example embodiments, the magnetic memory device may further include a first selection transistor electrically connected to the first conductive pattern, and a second selection transistor electrically connected to the second conductive pattern.

In some example embodiments, the magnetic memory device may further include a common source line electrically connected in common to source regions of both the first selection transistor and the second selection transistor.

In some example embodiments, a top surface of the second conductive pattern may be one of substantially coplanar with and under the second top surface of the second region of the first insulating layer.

In some example embodiments, a top surface of the third conductive pattern may be one of substantially coplanar with and under the third top surface of the third region of the second insulating layer.

In some example embodiments, the magnetic memory device may further include at least one of a first protection pattern on the second conductive pattern, and a second protection pattern on the third conductive pattern.

In some example embodiments, the first to fourth conductive patterns may include a metallic material and the first and second protection patterns may include a metallic oxide material.

In some example embodiments, at least one of the first and second contact plugs may be provided through at least a corresponding one of the first and second protection patterns.

In some example embodiments, when the magnetic memory device includes the first protection pattern, a top surface of the first protection pattern may be one of substantially coplanar with and above the second top surface of the second region of the first insulating layer, and when the magnetic memory device includes the second protection pattern, a top surface of the second protection pattern may be one of substantially coplanar with and above the third top surface of the third region of the second insulating layer.

In some example embodiments, a top surface of the second conductive pattern may be one of substantially coplanar with and under the second top surface of the second region of the first insulating layer, and a top surface of the third conductive pattern may be one of substantially coplanar with and under the third top surface of the third region of the second insulating layer.

DETAILED DESCRIPTION

Hereinafter, some example embodiments will be explained in further detail with reference to the accompanying drawings.

FIGS. 1A through 1Iare sectional views illustrating a method of fabricating a memory device, according to an example embodiment of the inventive concepts.FIG. 1Jis an enlarged sectional view illustrating a portion ‘A’ ofFIG. 1I.FIGS. 2A and 2Bare sectional views illustrating an example of a method of forming a first conductive pattern and a protection pattern, according to an example embodiment of the inventive concepts.FIGS. 3A through 3Dare sectional views illustrating another example of a method of forming a first conductive pattern and a protection pattern, according to an example embodiment of the inventive concepts.

Referring toFIG. 1A, a lower insulating layer120may be formed on a substrate110. The substrate110may include selection elements (not shown), for example, diodes or transistors.

The lower insulating layer120may include a first through hole120aextending therethrough from a top surface to a bottom surface thereof. In some example embodiments, the substrate110may be partially exposed by the first through hole120a. The lower insulating layer120may be formed of or include at least one of silicon oxide, silicon nitride, or silicon oxynitride. The lower insulating layer120may be formed by, for example, a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

A first conductive pattern130may fill at least a portion of the first through hole120a. In some example embodiments, the first conductive pattern130may be electrically connected to the substrate110. The first conductive pattern130may have a top surface positioned at lower level than that of the lower insulating layer120. In this disclosure, the term ‘level’ refers to height from a top surface of the substrate110. The first conductive pattern130may include a conductive material. As an example, the first conductive pattern130may be formed of or include at least one of metallic materials, for example, copper, aluminum, tungsten, or titanium.

A protection pattern140may cover the top surface of the first conductive pattern130. The protection pattern140may fill the remaining space of the first through hole120a, in which the first conductive pattern130is provided. For example, a side surface of the first conductive pattern130may be covered by the lower insulating layer120and a top surface of the first conductive pattern130may be covered by the protection pattern140. Thus, the first conductive pattern130may not be exposed to the outside. The protection pattern140may include an insulating material. As an example, the protection pattern140may be formed of or include at least one of metal oxides, for example, copper oxide, aluminum oxide, tungsten oxide, or titanium oxide. In the case where the first conductive pattern130contains a metallic material, the protection pattern140may include a metal oxide compound. The metallic material of the protection pattern may be the same as the metallic material contained in the first conductive pattern130. As an example, in the case where the first conductive pattern130includes tungsten, the protection pattern140may include tungsten oxide. As another example, in the case where the first conductive pattern130includes titanium, the protection pattern140may include titanium oxide.

FIGS. 2A and 2Billustrate an example of a method for forming the first conductive pattern130and the protection pattern140.

Referring toFIG. 2A, a conductive layer135may be formed while filling the first through hole120a. The conductive layer135may be formed of or include at least one of metallic materials, for example, copper, aluminum, tungsten, or titanium.

Referring toFIG. 2B, the conductive layer135may be partially oxidized to form an oxide layer145. For example, the oxide layer145may be formed by oxidizing some portions of the conductive layer135on the lower insulating layer120and in an upper portion of the first through hole120a. The remaining portion of the conductive layer135(e.g., a lower portion of the conductive layer135in the first through hole120a) may not be oxidized during the oxidation process, and thus, it may be used as the conductive pattern130. The oxidation process may be performed using, for example, an oxygen ion beam or oxygen ashing process.

Referring back toFIG. 1A, a planarization process may be performed until the top surface of the lower insulating layer120is exposed. For example, the planarization process may be performed to remove a portion of the oxide layer145on the top surface of the lower insulating layer120. Accordingly, the protection pattern140may be locally formed in the first through hole120a.

FIGS. 3A through 3Dillustrate another example of a method for forming the first conductive pattern130and the protection pattern140.

Referring toFIG. 3A, a first lower insulating layer122with a through hole122amay be formed on the substrate110. Thereafter, a preliminary first conductive pattern130pmay be formed to fill the through hole122a. The formation of the preliminary first conductive pattern130pmay include forming a conductive layer (not shown) to fill the through hole122aand planarizing the conductive layer until the top surface of the first lower insulating layer122is exposed. The preliminary first conductive pattern130pmay be formed of or include at least one of metallic materials, for example, copper, aluminum, tungsten, or titanium.

Referring toFIG. 3B, a top portion of the first lower insulating layer122may be etched or recessed to expose an upper portion of the preliminary first conductive pattern130p.

Referring toFIG. 3C, the protection pattern140may be formed by oxidizing the exposed upper portion of the preliminary first conductive pattern130p. A portion of the preliminary first conductive pattern130plocated in the through hole122amay not be oxidized in the oxidation process, thereby serving as the first conductive pattern130. The oxidation of the upper portion of the preliminary first conductive pattern130pmay be performed using, for example, an oxygen ion beam or oxygen ashing process.

Referring toFIG. 3D, a second lower insulating layer124may be formed to cover a sidewall of the protection pattern140. The formation of the second lower insulating layer124may include forming an insulating layer (not shown) on the first lower insulating layer122to cover the protection pattern140and planarizing the insulating layer to expose the top surface of the protection pattern140. The first and second lower insulating layers122and124may be used as constituting parts of the lower insulating layer120.

Although some methods for forming the first conductive pattern130and the protection pattern140have been described with reference toFIGS. 2A and 2BandFIGS. 3A through 3D, but example embodiments of the inventive concepts are not limited thereto.

Referring toFIG. 1B, a second conductive pattern132may be formed to pass through the lower insulating layer120. The formation of the second conductive pattern132may include forming a second through hole120bextending throughout from the top surface to the bottom surface of the lower insulating layer120, forming a conductive layer (not shown) to fill the second through hole120b, and planarizing the conductive layer until the top surface of the lower insulating layer120and/or the top surface of the protection pattern140are/is exposed. Accordingly, the lower insulating layer120, the second conductive pattern132, and the protection pattern140may have top surfaces that are substantially coplanar with each other. The second conductive pattern132may include a conductive material. As an example, the second conductive pattern132may be formed of or include at least one of metallic materials (e.g., copper, aluminum, tungsten, titanium, etc.).

The optional bottom electrode layer OBEL and the optional top electrode layer OTEL may include at least one of conductive metal nitrides, such as titanium nitride and/or tantalum nitride. The optional bottom electrode layer OBEL may be formed to be in contact with the top surface of the second conductive pattern132. In some example embodiments, the formation of the optional bottom electrode layer OBEL and the optional top electrode layer OTEL may be omitted. Hereinafter, for the sake of simplicity, the description that follows will refer to example embodiments in which the optional bottom electrode layer OBEL and the optional top electrode layer OTEL are provided, but example embodiments of the inventive concepts are not limited thereto.

The magnetic tunnel junction layer MTJL may include a first magnetic layer ML1, a tunnel barrier layer TBL, and a second magnetic layer ML2, which are sequentially stacked on the substrate110. The magnetic tunnel junction layer MTJL will be described in more detail with reference toFIGS. 4A and 4B.

The top electrode layer TEL may be formed of or include at least one of metals (e.g., tungsten, tantalum, aluminum, copper, gold, silver, titanium) or conductive metal nitrides thereof.

A mask pattern MP may be formed on the top electrode layer TEL. When viewed in a plan view, the mask pattern MP may be, at least partially, overlapped with the second conductive pattern132. Further, when viewed in a plan view, the mask pattern MP may be formed spaced apart from the first conductive pattern130. The mask pattern MP may include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride.

Referring toFIG. 1D, a top electrode pattern TEP and an optional top electrode pattern OTEP may be formed. The formation of the top electrode pattern TEP and the optional top electrode pattern OTEP may include sequentially patterning the top electrode layer TEL and the optional top electrode layer OTEL using the mask pattern MP as an etch mask. The patterning process may be performed using a dry etching process (e.g., a reactive ion etching (RIE) process).

Referring toFIGS. 1E and 1H, a magnetic tunnel junction pattern MTJP and an optional bottom electrode pattern OBEP may be formed on the second conductive pattern132. The formation of the magnetic tunnel junction pattern MTJP and the optional bottom electrode pattern OBEP may include patterning the magnetic tunnel junction layer MTJL and the optional bottom electrode layer OBEL using the mask pattern MP as an etch mask. The patterning of the magnetic tunnel junction layer MTJL and the optional bottom electrode layer OBEL may include sequentially performing a first etching process ETCH1and a second etching process ETCH2on the structure including the magnetic tunnel junction layer MTJL.

For example, as shown inFIGS. 1E and 1H, the first etching process ETCH1may be performed. The first etching process ETCH1may be a sputter etching process using inactive or inert gas, for example, argon. As an example, as shown inFIG. 1E, in the first etching process ETCH1, atoms or ions of the inactive gas may be accelerated toward the substrate110in a direction substantially normal to the top surface of the substrate110to collide against the structure including the magnetic tunnel junction layer MTJL.

In some example embodiments, as a result of the first etching process ETCH1, the magnetic tunnel junction pattern MTJP may be formed to expose the top surfaces of the lower insulating layer120and the protection pattern140. When viewed in a plan view, the magnetic tunnel junction pattern MTJP may be spaced apart from the first conductive pattern130and may be, at least partially, overlapped with the second conductive pattern132. The magnetic tunnel junction pattern MTJP may include a first magnetic pattern MP1, a tunnel barrier pattern TBP, and a second magnetic pattern MP2, which are sequentially stacked on the substrate110. The magnetic tunnel junction pattern MTJP will be described in more detail with reference toFIGS. 4A and 4B.

As shown inFIG. 1F, as a result of the first etching process ETCH1, a first re-deposition layer RD1may be formed on a sidewall of the magnetic tunnel junction pattern MTJP. During or after the first etching process ETCH1, a part of the magnetic tunnel junction layer MTJL may be re-deposited on the magnetic tunnel junction pattern MTJP, thereby forming the first re-deposition layer RD1. In this case, the first re-deposition layer RD1may include the same material as the magnetic tunnel junction layer MTJL. In some example embodiments, the first re-deposition layer RD1may extend to cover sidewalls of the optional bottom electrode pattern OBEP, the optional top electrode pattern OTEP, the top electrode pattern TEP, and the mask pattern MP.

As shown inFIGS. 1G and 1H, the second etching process ETCH2may be performed to remove the first re-deposition layer RD1. For example, the second etching process ETCH2may be a sputter etching process, which is performed using inactive or inert gas, for example, argon. As an example, in the second etching process ETCH2, atoms or ions of the inactive gas may be accelerated toward the substrate110at an angle to collide against the structure including the first re-deposition layer RD1, as shown inFIG. 1G. Accordingly, atoms or ions of the inactive gas may collide against the first re-deposition layer RD1formed on the sidewall of the magnetic tunnel junction pattern MTJP, and as a result of such a collision, the first re-deposition layer RD1may be removed. In some example embodiments, the second etching process ETCH2may be performed continuously after the first etching process ETCH1by tilting the substrate110from its original position. However, example embodiments of the inventive concepts are not limited thereto, and the first and second etching processes ETCH1and ETCH2may be performed in a separated manner.

During the second etching process ETCH2, at least a portion of the protection pattern140may be etched. In some example embodiments, the protection pattern140may be portionially etched to leave a remaining portion140r, as shown inFIG. 1H. The remaining portion140rof the protection pattern may cover the top surface of the first conductive pattern130so that the top surface of the first conductive pattern130is not exposed. In certain example embodiments, unlikeFIG. 1H, the entire portion of the protection pattern140may be etched, and the top surface of the first conductive pattern130may be exposed.

As shown inFIG. 1H, as a result of the second etching process ETCH2, a second re-deposition layer RD2may be formed on the sidewall of the magnetic tunnel junction pattern MTJP. During or after the second etching process ETCH2, a portion of the protection pattern140may be re-deposited on the sidewall of the magnetic tunnel junction pattern MTJP, thereby forming the second re-deposition layer RD2. For example, etch residues of the protection pattern140, which are produced from the collision of the inactive gas onto the protection pattern140, may be adhered on the sidewall of the magnetic tunnel junction pattern MTJP. Accordingly, the second re-deposition layer RD2may include the same material as the protection pattern140. The second re-deposition layer RD2may extend to cover sidewalls of the optional bottom electrode pattern OBEP, the optional top electrode pattern OTEP, the top electrode pattern TEP, and the mask pattern MP.

As a result of the second etching process ETCH2, a portion of the lower insulating layer120may be etched to form a recess region120rdefined by the etched top surface of the lower insulating layer120. When viewed in a plan view, the portion of the lower insulating layer120overlapped with the magnetic tunnel junction pattern MTJP may not be recessed. In the second etching process ETCH2, an etch rate of the lower insulating layer120may be faster than that of the protection pattern140. Accordingly, the bottom surface of the recess region120rmay be positioned at a lower level than the top surface of the remaining portion of the protection pattern140r. In some example embodiments, as shown inFIG. 1H, the bottom surface of the recess region120rmay be positioned at a higher level than the top surface of the first conductive pattern130, and thus, the sidewall of the first conductive pattern130may not be exposed. In certain example embodiments, unlike that shown inFIG. 1H, the bottom surface of the recess region120rmay be positioned at a lower level than the top surface of the first conductive pattern130.

Referring toFIGS. 1I and 1J, an interlayer insulating layer150may be formed to cover the top surface of the lower insulating layer120. The interlayer insulating layer150may cover the second re-deposition layer RD2. The interlayer insulating layer150may include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride. The interlayer insulating layer150may be formed by, for example, a CVD or PVD process.

A contact plug PLG may be formed to pass through the interlayer insulating layer150and may be electrically connected to the first conductive pattern130. The contact plug PLG may be formed to pass through the remaining portion of the protection pattern140r. The formation of the contact plug PLG may include forming a third through hole150ato pass through the interlayer insulating layer150and the protection pattern140runtil the top surface of the first conductive pattern130is exposed, forming a conductive layer (not shown) to fill the third through hole150a, and performing a planarization process to expose the top surface of the top electrode pattern TEP.

In a method of fabricating a memory device according to some example embodiments of the inventive concepts, the protection pattern140may be formed on the first conductive pattern130. The protection pattern140may prevent the first conductive pattern130from being etched in the etching process (e.g., the first and/or second etching processes) for forming the magnetic tunnel junction pattern MTJP, thereby mitigating or preventing the first conductive film130from being re-deposited on the sidewall of the magnetic tunnel junction pattern MTJP. Accordingly, a short circuit between the first and second magnetic patterns MP1and MP2of the magnetic tunnel junction pattern MTJP may be mitigated or prevented.

In a method of fabricating a memory device according to some example embodiments of the inventive concepts, a portion of the protection pattern140may be etched and re-deposited on the sidewall of the magnetic tunnel junction pattern MTJP, during the etching process for forming the magnetic tunnel junction pattern MTJP. Because the protection pattern140includes an insulating material, the re-deposition of the protection pattern140may not cause to an electric short between the first and second magnetic patterns MP1and MP2of the magnetic tunnel junction pattern MTJP.

Some structural features of the semiconductor device fabricated by the method according to some example embodiments of the inventive concepts will be described with reference toFIGS. 1I and 1J.

Referring toFIGS. 1I and 1J, the lower insulating layer120may be provided on the substrate110. The substrate110may include selection elements (not shown), for example, diodes or transistors. The lower insulating layer120may be provided such that a portion of the top surface of the lower insulating layer120defines the recess region120r. The lower insulating layer120may be formed of or include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride.

The lower insulating layer120may have the first and second through holes120aand120bextending therethrough from a top surface to a bottom surface thereof. The first through hole120amay be formed to pass through the recessed portion of the lower insulating layer120, and the second through hole120bmay be formed to pass through the un-recessed portion of the lower insulating layer120. For example, when viewed in a plan view, the first through hole120amay be overlapped with the recess region120r, and the second through hole120bmay be spaced apart from the recess region120r.

The first and second conductive patterns130and132may be provided in the first and second through holes120aand120b, respectively. The first conductive pattern130may be provided to fill at least a portion of the first through hole120a, and the second conductive pattern132may be provided to fill the second through hole120b. The first conductive pattern130may have a top surface130_TS, which is positioned at a lower level than the top surface of the second conductive pattern132. In some example embodiments, the top surface130_TS of the first conductive pattern130may be lower than the bottom surface120r_BS of the recess region120r, but example embodiments of the inventive concepts are not limited thereto. The top surface of the second conductive pattern132may be higher than the bottom surface120r_BS of the recess region120r. The first and second conductive patterns130and132may include at least one of conductive materials. As an example, the first and second conductive patterns130and132may be formed of or include at least one of metallic materials, for example, copper, aluminum, tungsten, or titanium.

The protection pattern140rmay be provided to cover the top surface130_TS of the first conductive pattern130. At least a portion of the protection pattern140rmay fill the remaining space of the first through hole120aon the first conductive pattern130. The top surface140r_TS of the protection pattern140rmay be positioned at a higher level than the bottom surface120r_BS of the recess region120r. Furthermore, the top surface140r_TS of the protection pattern140rmay be positioned at a lower level than the top surface of the second conductive pattern132. The protection pattern140rmay include at least one of insulating materials. As an example, the protection pattern140rmay be formed of or include at least one of metal oxides (e.g., copper oxide, aluminum oxide, tungsten oxide, titanium oxide, etc.). In the case where the first conductive pattern130contains a metallic material, the protection pattern140rmay include a metal oxide compound. The metallic material of the protection pattern140rmay be the same as the metallic material of the first conductive pattern130. As an example, in the case where the first conductive pattern130includes tungsten, the protection pattern140rmay include tungsten oxide. As another example, in the case where the first conductive pattern130includes titanium, the protection pattern140rmay include titanium oxide.

The optional bottom electrode pattern OBEP, the magnetic tunnel junction pattern MTJP, the optional top electrode pattern OTEP, and the top electrode pattern TEP may be sequentially stacked on the second conductive pattern132. Sidewalls of the optional bottom electrode pattern OBEP, the magnetic tunnel junction pattern MTJP, the optional top electrode pattern OTEP, and the top electrode pattern TEP may be substantially coplanar with each other.

The optional bottom electrode pattern OBEP and the optional top electrode pattern OTEP may include at least one of conductive metal nitrides, for example, titanium nitride or tantalum nitride. The top electrode pattern TEP may be formed of or include at least one of metals (e.g., tungsten, tantalum, aluminum, copper, gold, silver, titanium) and conductive metal nitrides including the metals.

The magnetic tunnel junction pattern MTJP may include the first magnetic pattern MP1, the tunnel barrier pattern TBP, and the second magnetic pattern MP2, which are sequentially stacked on the substrate110. The magnetic tunnel junction pattern MTJP will be described in more detail with reference toFIGS. 4A and 4B.

The second re-deposition layer RD2may be provided on the sidewall of the magnetic tunnel junction pattern MTJP. In some example embodiments, the second re-deposition layer RD2may extend to cover the sidewalls of the optional bottom electrode pattern OBEP, the optional top electrode pattern OTEP, and the top electrode pattern TEP. The second re-deposition layer RD2may be formed of or include the same material as the protection pattern140r. As an example, in the case where the protection pattern140ris formed of tungsten oxide, the second re-deposition layer RD2may be formed of or include tungsten oxide. As another example, in the case where the protection pattern140ris formed of titanium oxide, the second re-deposition layer RD2may be formed of or include titanium oxide.

The interlayer insulating layer150may be provided to cover the top surface of the lower insulating layer120. The interlayer insulating layer150may cover the second re-deposition layer RD2. The interlayer insulating layer150may be formed of or include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride.

The contact plug PLG may be provided to pass through the interlayer insulating layer150and may be electrically connected to the first conductive pattern130. The contact plug PLG may also be provided to pass through the protection pattern140r.

FIGS. 4A and 4Bare schematic diagrams illustrating magnetization directions of magnetic tunnel junction patterns according to an example embodiment of the inventive concepts. The magnetic tunnel junction pattern MTJP may include the first magnetic pattern MP1, the tunnel barrier pattern TBP, and the second magnetic pattern MP2. One of the first magnetic pattern MP1and the second magnetic pattern MP2may serve as a free pattern of a magnetic tunnel junction (MTJ), and the other may serve as a fixed (or alternatively, pinned) pattern of the MTJ. For the sake of simplicity, the description that follows will refer to example embodiments in which the first and second magnetic patterns MP1and MP2are used as fixed and free patterns, respectively, but in certain example embodiments, the first and second magnetic patterns MP1and MP2may be used as the free and fixed patterns, respectively. Electrical resistance of the magnetic tunnel junction pattern MTJP may be sensitive to a relative orientation of magnetization directions of the free and fixed patterns. For example, the electric resistance of the magnetic tunnel junction pattern MTJP may be much higher when magnetization directions of the free and fixed patterns are anti-parallel than when they are parallel. This means that the electric resistance of the magnetic tunnel junction pattern MTJP can be controlled by changing the magnetization direction of the free pattern with respect to the direction of the fixed pattern, and the magnetic memory devices according to example embodiments of the inventive concepts may be realized based on this data-storing mechanism.

Referring toFIG. 4A, the first magnetic pattern MP1and the second magnetic pattern MP2may be configured to have an in-plane magnetization structure. For example, each of the first and second magnetic patterns MP1and MP2may be or include at least one magnetic layer, whose magnetization direction is substantially parallel to a top surface of the tunnel barrier pattern TBP. In some example embodiments, the first magnetic pattern MP1may include two layers, one of which includes an antiferromagnetic material, and the other of which includes a ferromagnetic material. The antiferromagnetic material may include, for example, at least one of PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, or Cr. In some example embodiments, the layer including the antiferromagnetic material may include at least one of precious metals. The precious metals may include, for example, ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or silver (Ag). The ferromagnetic material may include, for example, at least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, or Y3Fe5O12.

The second magnetic pattern MP2may be configured to have a variable or switchable magnetization direction. For example, the second magnetic pattern MP2may include, for example, a ferromagnetic material. As an example, the second magnetic pattern MP2may be formed of or include, for example, at least one of FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, or Y3Fe5O12.

The second magnetic pattern MP2may include a plurality of layers. For example, the second magnetic pattern MP2may include a plurality of ferromagnetic layers and at least one non-magnetic layer interposed between the ferromagnetic layers. In this case, the ferromagnetic layers and the non-magnetic layer may constitute a synthetic antiferromagnetic layer. The presence of the synthetic antiferromagnetic layer may reduce a critical current density desired for an operation of the magnetic memory device and improve a thermal stability of the magnetic memory device.

The tunnel barrier pattern TBP may include, for example, at least one of magnesium oxide, titanium oxide, aluminum oxide, magnesium-zinc oxide, magnesium-boron oxide, titanium nitride, or vanadium nitride. As an example, the tunnel barrier pattern TBP may be a single layer of magnesium oxide (MgO). Alternatively, the tunnel barrier pattern TBP may include a plurality of layers. The tunnel barrier pattern TBP may be formed by a CVD process.

Referring toFIG. 4B, the first and second magnetic patterns MP1and MP2may be configured to have a perpendicular magnetization structure. For example, each of the first and second magnetic patterns MP1and MP2may be or include at least one magnetic layer, whose magnetization direction is substantially normal to the top surface of the tunnel barrier pattern TBP. In some example embodiments, the first and second magnetic patterns MP1and MP2may include at least one of materials with an L10crystal structure, materials having the hexagonal closed packed structure, or amorphous rare-earth transition metal (RE-TM) alloys. As an example, the first and second magnetic patterns MP1and MP2may include at least one of L10materials, such as Fe50Pt50, Fe50Pd50, Co50Pt50, Co50Pd50, and Fe50Ni50. In other example embodiments, the first and second magnetic patterns MP1and MP2may include at least one of cobalt-platinum (CoPt) disordered Hexagonal-Close-Packed (HCP) alloys having a platinum content of 10 to 45 at. % or Co3Pt ordered HCP alloys hexagonal close packed. In still other example embodiments, the first and second magnetic patterns MP1and MP2may include at least one of the amorphous rare earth-transition metal (RE-TM) alloys containing at least one of iron (Fe), cobalt (Co), or nickel (Ni) and at least one of rare-earth metals. for example, terbium (Tb), dysprosium (Dy), or gadolinium (Gd).

The first and second magnetic patterns MP1and MP2may include a material with an interface perpendicular magnetic anisotropy. The interface perpendicular magnetic anisotropy may refer to a perpendicular magnetization phenomenon, which may be seen at an interface of a magnetic layer with an intrinsically in-plane magnetization property, when the magnetic layer is in contact with another layer. Here, the term “intrinsic in-plane magnetization property” will be used to mean that a magnetization direction of a magnetic layer is oriented parallel to a longitudinal direction thereof, when there is no external magnetic field applied thereto. For example, in the case that a magnetic layer with the intrinsic in-plane magnetization property is formed on a substrate and there is no external magnetic field applied thereto, a magnetization direction of the magnetic layer may be oriented substantially parallel to the top surface of the substrate.

As an example, the first magnetic pattern MP1and the second magnetic pattern MP2may include, for example, at least one of cobalt (Co), iron (Fe), or nickel (Ni). The first magnetic pattern MP1and the second magnetic pattern MP2may further include, for example, at least one of non-magnetic materials including boron (B), zinc (Zn), aluminum (Al), titanium (Ti), ruthenium (Ru), tantalum (Ta), silicon (Si), silver (Ag), gold (Au), copper (Cu), carbon (C), and nitrogen (N). As an example, the first magnetic pattern MP1and the second magnetic pattern MP2may include a layer of CoFe or NiFe, in which boron (B) is added. Further, at least one of the first magnetic pattern MP1and the second magnetic pattern MP2may further include, for example, at least one of titanium (Ti), aluminum (Al), magnesium (Mg), tantalum (Ta), or silicon (Si) to lower saturation magnetization thereof. The first magnetic pattern MP1and the second magnetic pattern MP2may be formed by, for example, a sputtering process or a CVD process.

The magnetic tunnel junction layer MTJL ofFIG. 1Cmay be configured to contain the same material as the magnetic tunnel junction pattern MTJP.

FIG. 5is a block diagram schematically illustrating a memory device according to an example embodiment of the inventive concepts.

Referring toFIG. 5, a memory device may include a memory cell array1, a word line decoder2, a word line driver3, a bit line decoder4, a read and write circuit5, and a control logic6.

The memory cell array1may include a plurality of memory blocks BLK0-BLKn, and each of the memory blocks BLK0-BLKn may include a plurality of memory cells and word lines, bit lines, and source lines that are electrically connected to the memory cells.

The word line decoder2may be configured to decode the address information transmitted from the outside and select one of the word lines based on the decoded address information. The address information decoded in the word line decoder2may be transmitted to the word line driver3. Under the control of the control logic6, the word line driver3may provide word line voltages, which are generated by a voltage generating circuit (not shown), to selected and unselected ones of the word lines. The word line decoder2and the word line driver3may be connected in common to the plurality of memory blocks BLK0-BLKn and may provide a driving signal to the word lines of the selected one of the memory blocks BLK0-BLKn, in response to a block selection signal (not shown).

The bit line decoder4may decode address information input from the outside and then select one of the bit lines. The bit line decoder4may be connected in common to the plurality of memory blocks BLK0-BLKn and may provide data signals to the bit lines of the selected one of the memory blocks BLK0-BLKn, in response to the block selection signal (not shown).

The read and write circuit5may be connected to the memory cell array1through the bit lines. The read and write circuit5may be configured to select at least one of the bit lines, in response to a bit line selection signal (not shown) from the bit line decoder4. The read and write circuit5may be configured to exchange data with the external device. The read and write circuit5may be operated in response to control signals from the control logic6. The read and write circuit5may be configured to receive a power (e.g., voltage or current) transmitted from the control logic6and provide it to the selected at least one of the bit lines.

The control logic6may control overall operations of the memory device. The control logic6may receive control signals and an external voltage and may be operated in response to the received control signals. The control logic6may generate powers, which are desired for internal operations of the memory device, using the external voltage. The control logic6controls read, write, and/or erase operations in response to the control signals.

FIG. 6is a circuit diagram illustrating a memory cell array of a memory device according to an example embodiment of the inventive concepts. For example,FIG. 6is a circuit diagram illustrating the memory cell array described with reference toFIG. 5.

Referring toFIG. 6, the memory cell array1may include a plurality of word lines WL, a plurality of bit lines BL1and BL2, a plurality of source lines SL, and a plurality of unit memory cells10. The bit lines BL1and BL2may be arranged to cross the word lines WL. As shown inFIG. 6, the source lines SL may be parallel to the bit lines BL1and BL2. However, example embodiments of the inventive concepts are not limited thereto, and unlike that shown inFIG. 6, the source lines SL may be parallel to the word lines WL.

Each of the unit memory cells10may be provided between a corresponding one of the word line WL and a corresponding pair of the bit lines BL1and BL2. Each of the unit memory cells10may include first and second memory elements ME1and ME2and first and second selection elements SE1and SE2.

The first memory element ME1may be disposed between the first selection element SE1and the first bit line BL1, and the second memory element ME2may be disposed between the second selection element SE2and the second bit line BL2. The first selection element SE1may be disposed between the first memory element ME1and the source line SL, and the second selection element SE2may be disposed between the second memory element ME2and the source line SL. In each of the unit memory cells10, the first and second selection elements SE1and SE2may share a corresponding one of the source lines SL and may be controlled by a corresponding one of the word lines WL. In certain example embodiments, a plurality of the unit memory cells10arranged parallel to the source line SL may be connected in common to the source line SL.

Each of the unit memory cells10may be selected by one of the word lines WL and a pair of the bit lines BL1and BL2. In some example embodiments, each of the first and second memory elements ME1and ME2may be a variable resistance element, whose electric resistance can be changed into, for example, one of two different values using an electric pulse applied thereto. The first and second memory elements ME1and ME2may be formed of a material, whose resistance is changed depending on a magnitude and/or direction of an electric current or voltage applied thereto, and further, may have a non-volatile data storing property. In some example embodiments, the first and second memory elements ME1and ME2may have a structure exhibiting a magneto-resistance property. For example, each of the first and second memory elements ME1and ME2may be provided to have substantially the same features as those of the magnetic tunnel junction pattern MTJP described with reference toFIG. 4AorFIG. 4B. In certain example embodiments, the first and second memory elements ME1and ME2may contain at least one of perovskite compounds or transition metal oxides.

The first and second selection elements SE1and SE2may be one of a diode, a PNP or NPN bipolar transistor, or a NMOS or PMOS field effect transistor. In some example embodiments, the first and second selection elements SE1and SE2may control a flow of electric current to be supplied to the first and second memory elements ME1and ME2, in response to voltages applied to the word lines WL.

FIG. 7is a circuit diagram illustrating a unit memory cell of a memory device according to an example embodiment of the inventive concepts. For example,FIG. 7may be a circuit diagram illustrating an example of the unit memory cell ofFIG. 6.

Referring toFIG. 7, the unit memory cell10may include first and second magnetic tunnel junction patterns MTJP1and MTJP2, which are used as memory elements thereof, and first and second selection transistors SE1and SE2, which are used as selection elements thereof. The first magnetic tunnel junction pattern MTJP1may include a first free pattern FP1, a first fixed pattern PP1, and a first tunnel barrier pattern TBP1interposed therebetween. The second magnetic tunnel junction pattern MTJP2may include a second free pattern FP2, a second fixed pattern PP2, and a second tunnel barrier pattern TBP2interposed therebetween. Each of the first and second fixed patterns PP1and PP2may have a fixed magnetization direction. The first and second free patterns FP1and FP2may have magnetization directions that can be changed to be parallel or antiparallel to the directions of the first and second fixed patterns PP1and PP2, respectively. In some example embodiments, each of the first and second magnetic tunnel junction patterns MTJP1and MTJP2may have substantially the same features as those of the magnetic tunnel junction pattern MTJP described with reference toFIG. 4AorFIG. 4B.

The first and second bit lines BL1and BL2may be provided to cross the word lines WL, and the source line SL may be connected in common to the first and second selection transistors SE1and SE2. The first magnetic tunnel junction pattern MTJP1may electrically connect the first bit line BL1to the first selection transistor SE1, and the first selection transistor SE1may electrically connect the first magnetic tunnel junction pattern MTJP1to the source line SL. The second magnetic tunnel junction pattern MTJP2may electrically connect the second bit line BL2to the second selection transistor SE2, and the second selection transistor SE2may electrically connect the second magnetic tunnel junction pattern MTJP2to the source line SL.

In some example embodiments, as shown inFIG. 7, the first free pattern FP1may be connected to the first bit line BL1, and the first fixed pattern PP1may be connected to the first selection transistor SE1. In such example embodiments, the second free pattern FP2may be connected to the second selection transistor SE2, and the second fixed pattern PP2may be connected to the second bit line BL2.

In certain example embodiments, unlike that shown inFIG. 7, the first fixed pattern PP1may be connected to the first bit line BL1, and the first free pattern FP1may be connected to the first selection transistor SE1. In such example embodiments, the second fixed pattern PP2may be connected to the second selection transistor SE2, and the second free pattern FP2may be connected to the second bit line BL2. For the sake of simplicity, the description that follows will refer to one of example embodiments in which the first free pattern FP1is connected to the first bit line BL1, the first fixed pattern PP1is connected to the first selection transistor SE1, the second free pattern FP2is connected to the second selection transistor SE2, and the second fixed pattern PP2is connected to the second bit line BL2.

In some example embodiments, to write data ‘1’ in a selected one of the unit memory cells10, a turn-on voltage may be applied to the word line WL. A first bit line voltage may be applied to the first and second bit lines BL1and BL2, and a source line voltage lower than the first bit line voltage may be applied to the source line SL.

Under such voltage conditions, the first and second selection transistors SE1and SE2may be turned on to allow the first and second magnetic tunnel junction patterns MTJP1and MTJP2to be electrically connected to the source line SL. Also, a first write current IW1may flow from the first bit line BL1to the source line SL through the first magnetic tunnel junction pattern MTJP1, and a second write current IW2may flow from the second bit line BL2to the source line SL through the second magnetic tunnel junction pattern MTJP2. Here, the first and second write currents IW1and IW2may pass through the first and second magnetic tunnel junction patterns MTJP1and MTJP2, respectively, in opposite directions. That is, in such example embodiments, if the first and second bit lines BL1and BL2are applied with the same voltage, write currents of opposite directions may be supplied to the first magnetic tunnel junction pattern MTJP1and the second magnetic tunnel junction pattern MTJP2.

In detail, in the first magnetic tunnel junction pattern MTJP1, the first write current IW1may flow in a direction from the first free pattern FP1to the first fixed pattern PP1. In other words, electrons of the first write current IW1may be injected into the first magnetic tunnel junction pattern MTJP1in the direction from the first fixed pattern PP1toward the first free pattern FP1. In this case, some of such electrons which have the same spin direction as the first fixed pattern PP1may pass through the first tunnel barrier pattern TBP1(e.g., through a tunneling effect), and may exert a spin transfer torque to switch the magnetization of the first free pattern FP1. As a result, the magnetization direction of the first free pattern FP1may be changed to be parallel to that of the first pinned pattern PP1. By contrast, in the second magnetic tunnel junction pattern MTJP2, the second write current IW2may flow in a direction from the second fixed pattern PP2to the second free pattern FP2. In other words, electrons of the second write current IW2may be injected into the second magnetic tunnel junction pattern MTJP2in the direction from the second free pattern FP2toward the second fixed pattern PP2. In this case, some of such electrons which have a spin direction opposite to that of the second pinned pattern PP2may be reflected from the second tunnel barrier pattern TBP2, and may exert a spin transfer torque to switch the magnetization of the second free pattern FP2. Thus, the second free pattern FP2may be configured to have a magnetization direction that is antiparallel to that of the second fixed pattern PP2.

As described above, data ‘1’ may be written by configuring the first magnetic tunnel junction pattern MTJP1to have parallel magnetization directions and configuring the second magnetic tunnel junction pattern MTJP2to have antiparallel magnetization directions. As a result of writing data ‘1’, the first magnetic tunnel junction pattern MTJP1may have a relatively low resistance state and the second magnetic tunnel junction pattern MTJP2may have a relatively high resistance state.

In some example embodiments, to write data ‘0’ in a selected one of the unit memory cells10, a turn-on voltage may be applied to the word line WL. A second bit line voltage may be applied to the first and second bit lines BL1and BL2, and a second source line voltage higher than the second bit line voltage may be applied to the source line SL.

Under such voltage conditions, currents flowing in directions opposite to those of the first and second write currents IW1and IW2may be applied to the first and second magnetic tunnel junction patterns MTJP1and MTJP2, respectively. Accordingly, on the contrary to writing data ‘1’, magnetization directions of the first magnetic tunnel junction pattern MTJP1may be changed to be antiparallel to each other, and magnetization directions of the second magnetic tunnel junction pattern MTJP2may be changed to be parallel to each other. As a result writing data ‘0’, the first magnetic tunnel junction pattern MTJP1may have a relatively high resistance state and the second magnetic tunnel junction pattern MTJP2may have a relatively low resistance state.

Because, as described above, the first and second magnetic tunnel junction patterns MTJP1and MTJP2have resistance states different from each other, one of the first and second magnetic tunnel junction patterns MTJP1and MTJP2may be used to define a reference resistance value, when a read operation is performed on the unit memory cell10. Thus, a finite difference in resistance value between the first and second magnetic tunnel junction patterns MTJP1and MTJP2may be realized and can be used as a sensing margin in an operation of reading data from the unit memory cell10. Accordingly, operational reliability and/or data reliability of the unit memory cell10may be improved.

FIG. 8is a sectional view illustrating an example of a unit memory cell according to an example embodiment of the inventive concepts. For example,FIG. 8may be a sectional view illustrating the unit memory cell ofFIG. 7.

Referring toFIG. 8, a substrate210may be provided. The substrate210may include the first and second selection transistors SE1and SE2. The first and second selection transistors SE1and SE2may be controlled by one of the word lines. Furthermore, the source line may be connected in common to source regions of the first and second selection transistors SE1and SE2.

A first lower insulating layer215may be provided on the substrate210. The first lower insulating layer215may be formed of or include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride.

First and second contact plugs PLG1and PLG2and the second bit line BL2may be provided on the substrate210. The first contact plug PLG1may penetrate the first lower insulating layer215and may be connected to a drain region (for example, in or on the substrate210) of the first selection transistor SE1. The second contact plug PLG2may penetrate the first lower insulating layer215and may be connected to a drain region (for example, in or on the substrate210) of the second selection transistor SE2.

A second lower insulating layer220may be provided on the first lower insulating layer215. The second lower insulating layer220may be provided to have technical features similar to those of the first lower insulating layer120described with reference toFIGS. 1I and 1J. For example, the second lower insulating layer220may have a top surface defining a recess region220r.

First, second, and third conductive patterns230,232, and234may be provided. Further, a protection pattern240rmay be provided to cover the top surface of the first conductive pattern230. The first conductive pattern230may be provided to have technical features similar to those of the first conductive pattern130described with reference toFIGS. 1I and 1J, and each of the second and third conductive patterns232and234may be provided to have technical features similar to those of the second conductive pattern132described with reference toFIGS. 1I and 1J. The protection pattern240rmay have technical features similar to those of the protection pattern140rdescribed with reference toFIGS. 1I and 1J.

The first conductive pattern230and the protection pattern240rmay pass through the recessed portion of the second lower insulating layer220, and each of the second and third conductive patterns232and234may pass through an un-recessed portion of the second lower insulating layer220. The first conductive pattern230may be electrically connected to the second contact plug PLG2, the second conductive pattern232may be electrically connected to the second bit line BL2, and the third conductive pattern234may be electrically connected to the first contact plug PLG1. In some example embodiments, the first conductive pattern230may have a top surface lower than a lowest position of the top surface defining the recess region220r, but example embodiments of the inventive concepts are not limited thereto. Top surfaces of the second and third conductive patterns232and234may be higher than the lowermost position of the top surface defining the recess region220r. The first to third conductive patterns230,232, and234may include a conductive material. As an example, the first to third conductive patterns230,232, and234may be formed of or include, for example, at least one of metallic materials, such as copper, aluminum, tungsten, or titanium.

The top surface of the protection pattern240rmay be positioned at a higher level than the lowermost position of the top surface of the recess region220r. Further, the top surface of the protection pattern240rmay be positioned at a lower level than the top surfaces of the second and third conductive patterns232and234. The protection pattern240rmay include an insulating material. As an example, the protection pattern240rmay be formed of or include at least one of metal oxides (e.g., copper oxide, aluminum oxide, tungsten oxide, titanium oxide, etc.). In the case where the first conductive pattern230contains a metallic material, the protection pattern240rmay include a metal oxide compound, the metallic material of which is the same as that contained in the first conductive pattern230.

A first optional bottom electrode pattern OBEP1, the first magnetic tunnel junction pattern MTJP1, a first optional top electrode pattern OTEP1, and a first top electrode pattern TEP1may be sequentially stacked on the third conductive pattern234. A second optional bottom electrode pattern OBEP2, the second magnetic tunnel junction pattern MTJP2, a second optional top electrode pattern OTEP2, and a second top electrode pattern TEP2may be sequentially stacked on the second conductive pattern232.

The first and second optional bottom electrode patterns OBEP1and OBEP2and the first and second optional top electrode patterns OTEP1and OTEP2may include at least one of conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.). The first and second top electrode patterns TEP1and TEP2may be formed of or include at least one of metals (e.g., tungsten, tantalum, aluminum, copper, gold, silver, titanium, etc.) or conductive metal nitrides thereof.

The first magnetic tunnel junction pattern MTJP1may include the first free pattern FP1, the first fixed pattern PP1, and the first tunnel barrier pattern TBP1interposed therebetween. The second magnetic tunnel junction pattern MTJP2may include the second free pattern FP2, the second fixed pattern PP2, and the second tunnel barrier pattern TBP2interposed therebetween. The stacking order of the first free pattern FP1, the first fixed pattern PP1, and the first tunnel barrier pattern TBP1may be the same as that of the second free pattern FP2, the second fixed pattern PP2, and the second tunnel barrier pattern TBP2. Accordingly, the first fixed pattern PP1may be connected to the drain region (e.g., in or on the substrate210) of the first selection transistor SE1through the third conductive pattern234and the first contact plug PLG1, similar to the previous example embodiment described with reference toFIG. 7. Also, the second fixed pattern PP2may be connected to the second bit line BL2through the second conductive pattern232.

The second re-deposition layers RD2may be provided on the sidewalls of the first and second magnetic tunnel junction patterns MTJP1and MTJP2. Each of the second re-deposition layers RD2may be provided to have technical features similar to those of the second re-deposition layer RD2described with reference toFIGS. 1H and 1I. For example, each of the second re-deposition layers RD2may include the same material as the protection pattern240r. As an example, in the case where the protection pattern240ris formed of tungsten oxide, the second re-deposition layer RD2may be formed of or include tungsten oxide. As another example, in the case where the protection pattern240ris formed of titanium oxide, the second re-deposition layer RD2may be formed of or include titanium oxide.

An interlayer insulating layer250may be provided to cover the top surface of the second lower insulating layer220. Further, the interlayer insulating layer250may cover the second re-deposition layers RD2. The interlayer insulating layer250may be formed of or include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride.

A third contact plug PLG3may be provided to pass through the interlayer insulating layer250and may be electrically connected to the first conductive pattern230. The third contact plug PLG3may pass through the protection pattern240r.

The first bit line BL1and an interconnection pattern INC may be provided on the interlayer insulating layer250. The first bit line BL1may be connected to the first top electrode pattern TEP1. The interconnection pattern INC may be connected in common to the second top electrode pattern TEP2and the third contact plug PLG3. Accordingly, the first free pattern FP1may be connected to the first bit line BL1through the first top electrode pattern TEP1, similar to the previous example embodiment described with reference toFIG. 7. The second free pattern FP2may be connected to the drain region (for example, in or on the substrate210) of the second selection transistor SE2through the second top electrode pattern TEP2, the interconnection pattern INC, the third contact plug PLG3, the first conductive pattern230, and the second contact plug PLG2.

FIGS. 9A through 9Eare sectional views illustrating a method of fabricating the unit memory cell ofFIG. 8. For concise description, an element previously described with reference toFIG. 8may be identified by a similar or identical reference number without repeating an overlapping description thereof.

Referring toFIG. 9A, the substrate210including the first and second selection transistors SE1and SE2may be provided. The first lower insulating layer215may be formed on the substrate210. Further, the first and second contact plugs PLG1and PLG2and the second bit line BL2may be formed to pass through the first lower insulating layer215. The first contact plug PLG1may be connected to the first selection transistor SE1, and the second contact plug PLG2may be connected to the second selection transistor SE2. Further, the second bit line BL2may be formed through the first lower insulating layer215.

The second lower insulating layer220may be formed on the first lower insulating layer215. Thereafter, the first conductive pattern230may be formed to pass through the second lower insulating layer220and may be connected to the second contact plug PLG2, and a protection pattern240may be formed on the first conductive pattern230. The first conductive pattern230and the protection pattern240may be formed in a manner similar to the method of forming the first conductive pattern130and the protection pattern140as described with reference toFIG. 1A. Accordingly, the protection pattern240may include a metal oxide compound, the metallic material of which is the same as that contained in the first conductive pattern230.

The second and third conductive patterns232and234may be formed to pass through the second lower insulating layer220. The second conductive pattern232may be connected to the second bit line BL2, and the third conductive pattern234may be connected to the first contact plug PLG1.

As shown inFIG. 9B, the magnetic tunnel junction layer MTJL may include a fixed layer PL, the tunnel barrier layer TBL, and a free layer FL, which are sequentially stacked on the substrate210, but example embodiments of the inventive concept are not limited thereto. For example, the stacking order of the fixed layer PL and the free layer FL may be changed from the above.

The top electrode layer (not shown) and the optional top electrode layer (not shown) may be sequentially patterned using the mask patterns MP as an etch mask to form the first and second top electrode patterns TEP1and TEP2and the first and second optional top electrode patterns OTEP1and OTEP2.

A method of forming the first and second magnetic tunnel junction patterns MTJP1and MTJP2and the first and second optional bottom electrode patterns OBEP1and OBEP2will be described with reference toFIGS. 9C and 9D. The formation of the first and second magnetic tunnel junction patterns MTJP1and MTJP2and the first and second optional bottom electrode patterns OBEP1and OBEP2may include patterning the magnetic tunnel junction layer MTJL and the optional bottom electrode layer OBEL using the mask patterns MP as an etch mask. The patterning of the magnetic tunnel junction layer MTJL and the optional bottom electrode layer OBEL may include sequentially performing a first etching process and a second etching process.

First, as shown inFIG. 9C, the first etching process may be performed. The first etching process may be performed in a manner similar to the first etching process ETCH1described with reference toFIGS. 1E and 1F.

In particular, the first etching process may be performed using, for example, a sputter etching technique of accelerating atoms or ions of an inactive gas toward the substrate210in a direction substantially normal to a top surface of the substrate210so that the accelerated atoms or ions collide against the resulting structure. As a result of the first etching process, the top surfaces of the second lower insulating layer220and the protection pattern240may be exposed and the first and second magnetic tunnel junction patterns MTJP1and MTJP2may be formed. As a result of the first etching process, the first re-deposition layers RD1may be formed on sidewalls of the first and second magnetic tunnel junction patterns MTJP1and MTJP2. For example, during or after the first etching process, a portion of the magnetic tunnel junction layer MTJL may be re-deposited on the first and second magnetic tunnel junction patterns MTJP1and MTJP2, thereby forming the first re-deposition layer RD1. Thus, the first re-deposition layer RD1may include the same material as the magnetic tunnel junction layer MTJL.

Next, as shown inFIG. 9D, the second etching process may be performed to remove the first re-deposition layer RD1. The second etching process may be performed in a similar manner to the second etching process ETCH2described with reference toFIGS. 1G and 1H.

In particular, the second etching process may be performed using a sputter etching technique of accelerating atoms or ions of an inactive gas toward the substrate210in a direction at an angle to the top surface of the substrate210so that the accelerated atoms or ions collide against the resulting structure. As a result of the second etching process, at least a portion (or an entirety) of the protection pattern240may be etched. In some embodiments, the protection pattern240may be partially etched to leave a portion240r. As a result of the second etching process, the second re-deposition layers RD2may be formed on sidewalls of the first and second magnetic tunnel junction patterns MTJP1and MTJP2. For example, during or after the second etching process, a portion of the protection pattern240may be re-deposited on the first and second magnetic tunnel junction patterns MTJP1and MTJP2, thereby forming the second re-deposition layer RD2In this case, the second re-deposition layer RD2may include the same material as the protection pattern240. The second etching process may be performed to partially etch the second lower insulating layer220, thereby forming the recess region220ron the second lower insulating layer220.

Referring toFIG. 9E, the interlayer insulating layer250may be formed to cover a top surface of the second lower insulating layer220. Furthermore, the interlayer insulating layer250may cover the second re-deposition layers RD2. The third contact plug PLG3may be formed to pass through the interlayer insulating layer250and to be electrically connected to the first conductive pattern230. The third contact plug PLG3may be formed to pass through the remaining portion240rof the protection pattern240.

Referring back toFIG. 8, the first bit line BL1and the interconnection pattern INC may be formed on the interlayer insulating layer250. The first bit line BL1may be connected to the first top electrode pattern TEP1, and the interconnection pattern INC may be connected to both of the second top electrode pattern TEP and the third contact plug PLG3.

In a method of fabricating a unit memory cell according to some example embodiments of the inventive concepts, the protection pattern240may be formed on the first conductive pattern230. The protection pattern240may prevent the first conductive pattern230from being etched during the etching process for forming the first and second magnetic tunnel junction patterns MTJP1and MTJP2and from being re-deposited on the sidewalls of the first and second magnetic tunnel junction patterns MTJP1and MTJP2. Accordingly, a short circuit between the free and fixed patterns of each of the first and second magnetic tunnel junction patterns MTJP1and MTJP2may be prevented.

In a method of fabricating a unit memory cell according to some example embodiments of the inventive concepts, a portion of the protection pattern240may be etched and re-deposited on the sidewalls of the first and second magnetic tunnel junction patterns MTJP1and MTJP2, during the etching process for removing the first re-deposition layer RD1. Because the protection pattern240includes an insulating material, the re-deposition of the protection pattern240may not lead to an electric short circuit between the free and fixed patterns of each of the first and second magnetic tunnel junction patterns MTJP1and MTJP2.

FIG. 10is a sectional view illustrating another example of a unit memory cell according to an example embodiment of the inventive concepts. For example,FIG. 10may be a sectional view illustrating the unit memory cell ofFIG. 7.

Referring toFIG. 10, a substrate310may be provided. The substrate310may include the first and second selection transistors SE1and SE2. The first and second selection transistors SE1and SE2may be controlled by one of the word lines WL (not shown). Furthermore, the source line SL may be connected in common to source regions of the first and second selection transistors SE1and SE2(not shown).

A lower insulating layer320may be provided on the substrate310. The lower insulating layer320may have technical features similar to those of the lower insulating layer120described with reference toFIGS. 1I and 1J. For example, the lower insulating layer320may have a top surface defining a recess region320r.

First and second conductive patterns330and332may be provided. Further, a first protection pattern340rmay cover a top surface of the first conductive pattern330. The first conductive pattern330may have technical features similar to those of the first conductive pattern130described with reference toFIGS. 1I and 1J, and the second conductive pattern332may have technical features similar to those of the second conductive pattern132described with reference toFIGS. 1I and 1J. The first protection pattern340rmay have technical features similar to those of the protection pattern140rdescribed with reference toFIGS. 1I and 1J.

In particular, the first conductive pattern330and the first protection pattern340rmay pass through the recessed region320rof the lower insulating layer320, and the second conductive pattern332may pass through an un-recessed portion of the lower insulating layer320. The first conductive pattern330may be connected to a drain region (e.g., in or on the substrate310) of the second selection transistor SE2, and the second conductive pattern332may be connected to a drain region (e.g., in or on the substrate310) of the first selection transistor SE1. In some example embodiments, the first conductive pattern330may have a top surface lower than a bottom surface of the recess region320r, but example embodiments of the inventive concepts are not limited thereto. The top surface of the second conductive pattern332may be higher than a bottom surface of the recess region320r. The first and second conductive patterns330and332may include a conductive material. As an example, the first and second conductive patterns330and332may be formed of or include at least one of metallic materials, for example, copper, aluminum, tungsten, or titanium.

A top surface of the first protection pattern340rmay be at a level higher than the bottom surface of the recess region320r. Furthermore, the top surface of the first protection pattern340rmay be at a level lower than the top surface of the second conductive pattern332. The first protection pattern340rmay include an insulating material. As an example, the first protection pattern340rmay be formed of or include at least one of metal oxides (e.g., copper oxide, aluminum oxide, tungsten oxide, titanium oxide, etc.). In the case where the first conductive pattern330contains a metallic material, the first protection pattern340rmay include a metal oxide compound, the metallic material of which is the same as that contained in the first conductive pattern330.

The first optional bottom electrode pattern OBEP1, the first magnetic tunnel junction pattern MTJP1, the first optional top electrode pattern OTEP1, and the first top electrode pattern TEP1may be sequentially stacked on the second conductive pattern332.

The first magnetic tunnel junction pattern MTJP1may include a first free pattern FP1, a first fixed pattern PP1, and a first tunnel barrier pattern TBP1interposed therebetween. The second magnetic tunnel junction pattern MTJP2may include a second free pattern FP2, a second fixed pattern PP2, and a second tunnel barrier pattern TBP2interposed therebetween. The first free pattern FP1, the first fixed pattern PP1, and the first tunnel barrier pattern TBP1may be stacked in an order opposite to that of the second free pattern FP2, the second fixed pattern PP2, and the second tunnel barrier pattern TBP2. In some embodiments, the first fixed pattern PP1, the first tunnel barrier pattern TBP1, and the first free pattern FP1may be stacked on the substrate310in the order enumerated, as shown inFIG. 10. In this case, similar to the previous example embodiment described with reference toFIG. 7, the first fixed pattern PP1may be connected to the drain region of the first selection transistor SE1through the second conductive pattern332.

The second re-deposition layer RD2may be formed on the sidewall of the first magnetic tunnel junction pattern MTJP1. The second re-deposition layer RD2may have technical features similar to those of the second re-deposition layer RD2described with reference toFIGS. 1I and 1J. For example, the second re-deposition layer RD2may be formed of or include the same material as the first protection pattern340r.

A first interlayer insulating layer350may cover the top surface of the lower insulating layer320. Furthermore, the first interlayer insulating layer350may cover the second re-deposition layer RD2. The first contact plug PLG1may pass through the first interlayer insulating layer350and to be electrically connected to the first conductive pattern330.

A second interlayer insulating layer352may be provided on the first interlayer insulating layer350. The second interlayer insulating layer352may have technical features similar to those of the lower insulating layer120described with reference toFIGS. 1I and 1J. For example, the second interlayer insulating layer352may have a top surface defining a recess region352r.

Third and fourth conductive patterns334and336may be provided. Further, a second protection pattern342rmay cover a top surface of the third conductive pattern334. The third conductive pattern334may have technical features similar to those of the first conductive pattern130described with reference toFIGS. 1I and 1J, and the fourth conductive pattern336may have technical features similar to those of the second conductive pattern132described with reference toFIGS. 1I and 1J. The second protection pattern342rmay have technical features similar to those of the protection pattern140rdescribed with reference toFIGS. 1I and 1J.

In particular, the third conductive pattern334and the second protection pattern342rmay pass through the recessed portion of the second interlayer insulating layer352, and the fourth conductive pattern336may pass through an un-recessed portion of the second interlayer insulating layer352. The third conductive pattern334may be connected to the first top electrode pattern TEP1, and the fourth conductive pattern336may be connected to the first contact plug PLG1. In some example embodiments, the third conductive pattern334may have a top surface lower than a bottom surface of the recess region352r, but example embodiments of the inventive concepts are not limited thereto. The top surface of the fourth conductive pattern336may be higher than a bottom surface of the recess region352r. The third and fourth conductive patterns334and336may include a conductive material. As an example, the third and fourth conductive patterns334and336may be formed of or include at least one of metallic materials, for example, copper, aluminum, tungsten, or titanium.

A top surface of the second protection pattern342rmay be higher than the bottom surface of the recess region352r. Furthermore, the top surface of the second protection pattern342rmay be positioned at a level lower than the top surface of the fourth conductive pattern336. The second protection pattern342rmay include an insulating material. As an example, the second protection pattern342rmay be formed of or include at least one of metal oxides (e.g., copper oxide, aluminum oxide, tungsten oxide, titanium oxide, etc.). In the case where the third conductive pattern334contains a metallic material, the second protection pattern342rmay include a metal oxide compound, the metallic material of which is the same as that contained in the third conductive pattern334.

The second optional bottom electrode pattern OBEP2, the second magnetic tunnel junction pattern MTJP2, the second optional top electrode pattern OTEP2, and the second top electrode pattern TEP2may be sequentially stacked on the fourth conductive pattern336.

The second magnetic tunnel junction pattern MTJP2may include the second free pattern FP2, the second fixed pattern PP2, and the second tunnel barrier pattern TBP2interposed therebetween. The second free pattern FP2, the second fixed pattern PP2, and the second tunnel barrier pattern TBP2may be stacked in an order opposite to that of the first free pattern FP1, the first fixed pattern PP1, and the first tunnel barrier pattern TBP1. Accordingly, as shown inFIG. 10, the second free pattern FP2, the second tunnel barrier pattern TBP2, and the second fixed pattern PP2may be stacked on the substrate310in the order enumerated. In this case, similar to the previous example embodiment described with reference toFIG. 7, the second free pattern FP2may be connected to the drain region of the second selection transistor SE2through the fourth conductive pattern336, the first contact plug PLG1, and the first conductive pattern330.

A fourth re-deposition layer RD4may be provided on the sidewall of the second magnetic tunnel junction pattern MTJP2. The fourth re-deposition layer RD4may have technical features similar to those of the second re-deposition layer RD2described with reference toFIGS. 1I and 1J. For example, the fourth re-deposition layer RD4may be formed of or include the same material as the second protection pattern342r.

A third interlayer insulating layer354may cover the top surface of the second interlayer insulating layer352. The third interlayer insulating layer354may also cover the fourth re-deposition layer RD4. The second contact plug PLG2may pass through the third interlayer insulating layer354and to be electrically connected to the third conductive pattern334.

The first and second bit lines BL1and BL2may be provided on the third interlayer insulating layer354. The first bit line BL1may be connected to the second contact plug PLG2, and the second bit line BL2may be connected to the second top electrode pattern TEP2. Accordingly, the first free pattern FP1may be connected to the first bit line BL1through the first top electrode pattern TEP1, the third conductive pattern334, and the second contact plug PLG2, similar to the previous example embodiment described with reference toFIG. 7. Also, the second fixed pattern PP2may be connected to the second bit line BL2through the second top electrode pattern TEP2.

FIGS. 11A through 11Fare sectional views illustrating a method of fabricating the unit memory cell ofFIG. 10. For concise description, an element previously described with reference toFIG. 10may be identified by a similar or identical reference number without repeating an overlapping description thereof.

Referring toFIG. 11A, the substrate310including the first and second selection transistors SE1and SE2may be provided. The lower insulating layer320, the first and second conductive patterns330and332, and a protection pattern340may be formed on the substrate310. The method of forming the lower insulating layer320, the first and second conductive patterns330and332, and the protection pattern340may be similar to the method of forming the lower insulating layer120, the first and second conductive patterns130and132, and the protection pattern140, as described with reference toFIGS. 1A, 1B,FIGS. 2A, 2B, andFIGS. 3A through 3D. Thus, a detailed description thereof will be omitted.

Referring toFIG. 11B, a first optional bottom electrode layer OBEL1, a first magnetic tunnel junction layer MTJL1, a first optional top electrode layer (not shown), and a first top electrode layer (not shown) may be sequentially formed on the lower insulating layer320. On the first top electrode layer, a first mask pattern MSK1may be formed to overlap with the second conductive pattern332.

As shown inFIG. 11B, the first magnetic tunnel junction layer MTJL1may include a first fixed layer PL1, a first tunnel barrier layer TBL1, and a first free layer FL1, which are sequentially stacked on the substrate310, but example embodiments of the inventive concepts are not limited thereto. For example, the stacking order of the first fixed layer PL1and the first free layer FL1may be different from the above.

The first top electrode layer and the first optional top electrode layer may be sequentially patterned using the first mask pattern MSK1as an etch mask to form the first top electrode pattern TEP1and the first optional top electrode pattern OTEP1. The patterning process may be performed using, for example, dry etching techniques (e.g., a reactive ion etching (RIE) method).

Referring toFIG. 11C, the first optional bottom electrode pattern OBEP1and the first magnetic tunnel junction pattern MTJP1may be formed between the second conductive pattern332and the first optional top electrode pattern OTEP1. The formation of the first optional bottom electrode pattern OBEP1and the first magnetic tunnel junction pattern MTJP1may be performed in a similar manner to the method of forming the optional bottom electrode pattern OBEP and the magnetic tunnel junction pattern MTJP, as described with reference toFIGS. 1E through 1H.

In particular, the first magnetic tunnel junction layer MTJL1and the first optional bottom electrode layer OBEL1may be sequentially patterned to form the first magnetic tunnel junction pattern MTJP1and the first optional bottom electrode pattern OBEP1. The patterning process may include sequentially performing a first etching process and a second etching process.

The first etching process may be performed in a similar manner to the first etching process ETCH1described with reference toFIGS. 1E and 1F. As a result of the first etching process, a first re-deposition layer (not shown) may be formed on the sidewall of the first magnetic tunnel junction pattern MTJP1. The second etching process may be performed in a similar manner to the second etching process ETCH2described with reference toFIGS. 1G and 1H. The second etching process may be performed to remove the first re-deposition layer. During this process, at least a portion of the first protection pattern340may be removed. For example, the first protection pattern340may be partially etched to leave a portion340r, as shown inFIG. 11B.

As a result of the second etching process, the second re-deposition layer RD2may be formed on the sidewall of the first magnetic tunnel junction pattern MTJP1. For example, during or after the second etching process, a portion of the first protection pattern340may be re-deposited on the first magnetic tunnel junction pattern MTJP1, thereby forming the second re-deposition layer RD2. The second re-deposition layer RD2may include the same material as the first protection pattern340.

The second etching process may be performed to partially etch the lower insulating layer320, thereby forming the recess region320ron the lower insulating layer320.

The first interlayer insulating layer350may be formed on the lower insulating layer320. Thereafter, the first contact plug PLG1may be formed to pass through the first interlayer insulating layer350and the remaining portion340rof the first protection pattern340and may be connected to the first conductive pattern330.

Referring toFIG. 11D, the second interlayered insulating layer352may be formed on the first interlayer insulating layer350. Thereafter, the third conductive pattern334may be formed to pass through the second interlayer insulating layer352and may be connected to the first top electrode pattern TEP1, and a second protection pattern342may be formed on the third conductive pattern334. The method of forming the third conductive pattern334and the second protection pattern342may be similar to the method of forming the first conductive pattern130and the protection pattern140, as described with reference toFIGS. 1A, 2A,FIG. 2B, andFIGS. 3A through 3D, and thus, a detailed description thereof will be omitted. Thereafter, the fourth conductive pattern336may be formed to pass through the second interlayer insulating layer352and may be connected to the first contact plug PLG1.

Referring toFIG. 11E, a second optional bottom electrode layer OBEL2, a second magnetic tunnel junction layer MTJL2, a second optional top electrode layer (not shown), and a second top electrode layer (not shown) may be sequentially formed on a second interlayer insulating layer352. A second mask pattern MSK2may be formed on the second top electrode layer to overlap with the fourth conductive pattern336.

The second magnetic tunnel junction layer MTJL2may include a second free layer FL2, a second fixed layer PL2, and a second tunnel barrier layer TBL2interposed between the second free layer FL2and the second fixed layer PL2. The second free layer FL2, the second fixed layer PL2, and the second tunnel barrier layer TBL2may be stacked in an order opposite to that of the first free layer FL1, the first fixed layer PL1, and the first tunnel barrier layer TBL1.

As shown inFIGS. 11B and 11E, the first fixed layer PL1, the first tunnel barrier layer TBL1, and the first free layer FL1are sequentially stacked, the second free layer FL2, the second tunnel barrier layer TBL2, and the second fixed layer PL2may be sequentially the substrate310in the order enumerated. Alternatively, the first free layer FL1, the first tunnel barrier layer TBL1, and the first fixed layer PL1are sequentially stacked, the second fixed layer PL2, the second tunnel barrier layer TBL2, and the second free layer FL2may be sequentially stacked on the substrate310in the order enumerated.

The second top electrode layer and the second optional top electrode layer may be sequentially patterned using the second mask pattern MSK2as an etch mask to form the second top electrode pattern TEP2and the second optional top electrode pattern OTEP2. The patterning process may be performed using, for example, dry etching techniques (e.g., a reactive ion etching (RIE) method).

Referring toFIG. 11F, the second optional bottom electrode pattern OBEP2and the second magnetic tunnel junction pattern MTJP2may be formed between the fourth conductive pattern336and the second optional top electrode pattern OTEP2. The formation of the second optional bottom electrode pattern OBEP2and the second magnetic tunnel junction pattern MTJP2may be performed in a similar manner to the method of forming the optional bottom electrode pattern OBEP and the magnetic tunnel junction pattern MTJP, as described with reference toFIGS. 1E through 1H.

In particular, the second magnetic tunnel junction layer MTJL2and the second optional bottom electrode layer OBEL2may be sequentially patterned to form the second magnetic tunnel junction pattern MTJP2and the second optional bottom electrode pattern OBEP2. The patterning process may include sequentially performing a third etching process and a fourth etching process.

The third etching process may be performed in a similar manner to the first etching process ETCH1described with reference toFIGS. 1E and 1F. As a result of the third etching process, a third re-deposition layer (not shown) may be formed on the sidewall of the second magnetic tunnel junction pattern MTJP2. The fourth etching process may be performed in a similar manner to the second etching process ETCH2described with reference toFIGS. 1G and 1H. For example, the fourth etching process may be performed to remove the third re-deposition layer, and during this process, at least a portion of the second protection pattern342may be removed. In some example embodiments, the second protection pattern342may be at least partially etched to leave a portion342r, as shown inFIG. 11F.

As a result of the fourth etching process, the fourth re-deposition layer RD4may be formed on the sidewall of the second magnetic tunnel junction pattern MTJP2. For example, during or after the fourth etching process, a portion of the second protection pattern342may be re-deposited on the second magnetic tunnel junction pattern MTJP2, thereby forming the fourth re-deposition layer RD4. The fourth re-deposition layer RD4may include the same material as the second protection pattern342.

The fourth etching process may be performed to partially etch the second interlayer insulating layer352. During this case, the recess region352rmay be formed on the second interlayer insulating layer352.

The third interlayer insulating layer354may be formed on the second interlayer insulating layer352. Thereafter, the second contact plug PLG2may be formed to pass through the third interlayer insulating layer354and the remaining portion342rof the second protection pattern342and may be connected to the third conductive pattern334.

Referring back toFIG. 10, the first bit line BL1and the second bit line BL2may be formed on the third interlayer insulating layer354and may be connected to the second contact plug PLG2and the second top electrode pattern TEP2, respectively.

In a method of fabricating a unit memory cell according to some example embodiments of the inventive concepts, the first protection pattern340may be formed on the first conductive pattern330and the second protection pattern342may be formed on the third conductive pattern334. The first protection pattern340may prevent the first conductive pattern330from being etched in the etching process for forming the first magnetic tunnel junction pattern MTJP1and from being re-deposited on the sidewall of the first magnetic tunnel junction pattern MTJP1. Accordingly, a short circuit between the free and fixed patterns of the first magnetic tunnel junction pattern MTJP1may be prevented. Similarly, the second protection pattern342may prevent the third conductive pattern334from being etched in the etching process for forming the second magnetic tunnel junction pattern MTJP2and from being re-deposited on the sidewall of the second magnetic tunnel junction pattern MTJP2. Accordingly, a short circuit between the free and fixed patterns of the second magnetic tunnel junction pattern MTJP2may be prevented.

In a method of fabricating a unit memory cell according to some example embodiments of the inventive concepts, during the etching process for forming the first or second magnetic tunnel junction pattern MTJP1or MTJP2, the first or second protection pattern340or342may be partially etched and may be re-deposited on the sidewall of the first or second magnetic tunnel junction pattern MTJP1or MTJP2. Because the first and second protection patterns340and342are formed of include an insulating material, the re-deposition of the first or second protection pattern340or342may not lead to an electric short circuit between the free and fixed patterns of each of the first and second magnetic tunnel junction patterns MTJP1and MTJP2.

In a method of fabricating a memory device according to some example embodiments of the inventive concepts, a protection pattern may be formed on a conductive pattern. The protection pattern may prevent the conductive pattern from being etched in an etching process for forming the magnetic tunnel junction pattern and from being re-deposited on a sidewall of a magnetic tunnel junction pattern. Accordingly, a short circuit between free and pinned patterns of the magnetic tunnel junction pattern may be prevented.

Furthermore, the protection pattern may be formed of or include an insulating material. In the etching process for forming the magnetic tunnel junction pattern, a portion of the protection pattern may be etched and re-deposited on the sidewall of the magnetic tunnel junction pattern. Because the protection pattern is formed of or includes an insulating material, the re-deposition of the protection pattern may not lead to a short circuit between the free and fixed patterns of the magnetic tunnel junction pattern.