System for converting analog video signals to digital video signals

A system for converting analog video signals to digital video signals receives an analog video signal that generates a reference horizontal synchronization signal. A phase-locked loop receives the reference horizontal synchronization signal and generates a pixel clock signal and a horizontal synchronization signal from the reference horizontal synchronization signal. An analog-to-digital converter converts the analog video signals to digital video signals. Differences between the measured values of the sampling of a test line of adjacent pixels are formed and phase parameters of the different phase positions are generated by summation of these differences. A phase position of the video signal from the phase parameters is determined, and the phase position is determined with the set phase position, and based on the comparison the set phase is changed.

CLAIM OF PRIORITY

This patent application claims priority to German patent application DE 101 36 677.9 filed on Jul. 27, 2001.

FIELD OF THE INVENTION

The invention relates to the field of converting analog video signals to digital video signals.

RELATED ART

In order to reproduce an analog RGB image on a digital display, analog-to-digital conversion is required. The quality of this image display depends upon the pixel precision of on the pixel precision of this conversion. Otherwise the reproduction of the fine vertical line structures is inadequate. If the sampling frequency does not correspond to the pixel frequency, sampling outside the minimum and maximum video signal values causes false minima and maxima to be recognized which agree neither in their absolute value nor in their phase with the actual values.

Another problem is the selection of the sample phase when the sampling frequency does not correspond to the pixel frequency. Errors in selection of the sampling phase are manifest themselves most clearly in images with sharp, vertical edges such as those found on navigation charts, etc. Therefore, to evaluate the selected phase position, a test line with alternating black and white pixels may be utilized. If, in the extreme case, with a uniformly periodic test line, the phase position lies precisely between the minima and maxima, matching gray tones are determined, in a sine curve, for example, and the test line is thus reproduced as a gray line.

To minimize such problems, the synchronization signals determining the time of the sample are first modulated upon the actual RGB signal to minimize the skew between video content and control signals. In addition, the lines generated by the source are generated with a precisely defined number of pixels, thereby enabling the receiving module to regenerate the precise pixel frequency of the line frequency by appropriate multiplication. To enable selection by the receiving module of the phase position between the recovered synchronization signal and the RGB signal, a defined test signal which preferably contains a change between the maximum and minimum RGB amplitude from one pixel to the next i.e., an alternating sequence of white and black pixels, is tagged by the source.

Since the sampling frequency is generated based on knowledge of the exact pixel number per line and corresponding multiplication of the line frequency by a phase-locked loop (PLL), the optimum sampling phase must still be determined from the sampling signal.

The goal of the invention is therefore to create, preferably at relatively low expense, a technique for converting analog video signals to digital video signals which enable precise determination of the phase position between the recovered synchronization signal and the RGB signal.

SUMMARY OF THE INVENTION

The basic principle of the invention is to determine the actual phase position of the RGB signals by finer and finer sampling with different phase positions, and by qualitative evaluation of the measured values through formation of suitable parameters. For this purpose, sampling of the pixels of a test line is effected with preferably alternating white and black pixels at a frequency that is n times the pixel frequency. As a result, n sampling values with fixed phase positions are obtained for each pixel. The parameters for the individual phase positions are determined by forming the difference between the measured values of adjacent pixels and summing these differences. These parameters thus contain information on the relative phase position between the recovered synchronization signal and the RGB signal, which information may then be evaluated.

In order, for example, to counteract Hsync jitter, that is, a phase fluctuation of the Hsync signal while still precisely determining the sampling instant to a fraction of a sampling period, multiple lines rather than simply the test line are preferably employed for the calibration. This action may be effected, specifically, by low-pass filtering.

According to the invention, readjustment of the sampling instant may be omitted if it is determined that no image is present with the relevant sharp, vertical lines, and that, as a result, the problems referred to in the preamble are not relevant.

The technique according to the invention may be implemented, specifically, by double or triple oversampling. Each pixel is thereby subdivided into two or three phase segments which are each written by a phase register, such that during a readjustment the phase register value of the sampling phase is correspondingly incremented or decremented in steps.

DETAILED DESCRIPTION OF THE INVENTION

InFIG. 3, analog video signals are input through an input circuit to an analog-to-digital converter7and a synchronization separator8. A reference horizontal synchronization signal is formed by synchronization separator8via an interface filter9, the signal being input to a PLL (phase-locked loop)10. From this signal, and with knowledge of the pixel number per line, the PLL10forms a pixel clock signal PixClk on a line100and a horizontal synchronization signal Hsync on a line102. The analog-to-digital converter7relays a digital video signal RGB on a line104to a frame processing device13, and from this, the green signal G to an evaluation unit14. Via an adjustment device11for shifting horizontal synchronization signal HSync as a function of a horizontal shift signal HShft, horizontal synchronization signal HSync is fed to a detection device12to establish the beginning of a test line. The detection device12inputs a start signal Start on a line108to the evalution device13which then picks up pixel clock signal PixClk on the line100in addition to the green signal G on the line104. Phase parameters θi are computed in evaluation device13, from which parameters averaged phase parameters θ*iare computed by averaging multiple lines, the averaged parameters being referenced in a following signal phase determination device15to determine the phase position, wherein this phase position is in turn compared in a following device for generating an analog-to-digital converter phase16, with a currently set phase position of the analog-to-digital converter, from which, among other things, horizontal shift signal HShft and a modified phase position of the analog-to-digital conversion are defined. The subsequent circuit components17,21,22,23have the function of precise readjustment and serve as the interface to a microprocessor.

In evaluation device13, the lines of digital green video signal G are read out at the nth pixel frequency. Out of one test line, preferably the last line before the active image and alternating white and black pixels, n measured values are sampled per pixel.FIG. 1shows an example in which n=2, whileFIG. 2shows an example in which n=3. The detection device12establishes the beginning of the test line and outputs the start signal Start to the evaluation unit.

Through multiplication, n measured values are obtained for each pixel at corresponding phase positions. The basis of the method is that, in each case, measured values of the same phase positions of white and black pixels are subtracted from each other and these differences are summed to form phase parameters θiover the entire test line. For this purpose, the measured values of adjacent pixels are subtracted from each other.

In principle, according to the invention, the phase position may be determined simply from these phase parameters. This phase position is then optimized for the test line. A remaining problem, however, is the phase shift of the HSync signal generally known as jitter. Regeneration by the PLL of the pixel clock signal already counteracts this jitter; however, since the sampling instant still needs to be aligned to the fraction of a sampling period, it is appropriate not only to use the current test line for calibration but to average multiple lines. This averaging may be performed, specifically, by including the lines of the active image so that an optimized sampling instant is determined averaged over the active image.

This averaging is effected by low-pass filtering. Especially suited for this purpose is an FIR filter of the Nth order, the coefficients of which are all 1, that isH1⁡(z)=∑i=0N⁢⁢Z-i=1-Z-(N+1)1-Z-1

This filter may be implemented, for example, with N=15. A relatively low level of production expense may be achieved with IIR filters. Specifically, the following form may be selected:H2⁡(z)=1+Z-11-(1-2p)⁢z-1
From the θ*i, the actual phase position may be determined mathematically, and the sampling phase of the analog-to-digital converter corrected accordingly.

Since the implementation expense is relatively high, however, especially for mathematical operations such as division and arctangent formation, and the analog prefilter would have to be designed so that the analyzed test signal already sufficiently approximates a sine curve, the method may be drastically simplified. While the readjustment takes somewhat longer in this case, this is generally not a problem since a readjustment is rarely required given a sampling phase that is already properly adjusted.

This simplified method determines only whether, and if so, in which direction the sampling phase must be adjusted. The readjustment is then effected by a phase register in minimum increments predetermined by analog-to-digital converter7.

Evaluation of the averaged phase parameters θ*iproceeds by the following steps which are shown inFIGS. 4 and 5for cases n=2 and n=3:1. An assessment is made as to whether an image with sharp, vertical lines is present. If not, all instantaneously made settings are maintained.2. If such an image with sharp, vertical lines is present, an assessment is made as to what the best sampling phase is.3. An assessment is made as to whether a readjustment of the sampling phase is required.4. If a readjustment is required, a decision is made as to the direction in which to change the phase position.

In the embodiment ofFIG. 4where n=2, a comparison of the values of the averaged phase parameters first determines which of the two phase positions better fits the maxima and minima of the video signal curve1(FIG1) of the measurement signal assumed to be a sine curve (green). The better phase position is taken to be the greater phase parameter based on the absolute value. The better phase parameter is subsequently compared with a limit S and, if the limit is not reached, step24decides that no relevant sharp, vertical lines, or an insufficient number of such lines, are present in the image, and that consequently there is no adjustment requirement.

Otherwise, the phase position whose averaged phase parameter has the higher absolute value is selected as best by steps25,26. Subsequently, based on a quantitative comparison of a quarter of the absolute value of the better averaged phase parameter selected with the absolute value of the other phase parameter, a decision is made as to whether the phase position has already been sufficiently optimized. In this case, step27decides that the phase position will not be changed. Otherwise, optimization of the sampling phase continues, whereby the signs of the phase parameters are compared, and if agreement is found, the sampling phase is shifted in steps28and31(when the first sampling is selected and the signs are equal, or when the second sampling is selected and the signs are not equal) by a predetermined value to the right, and in the other cases accordingly in blocks29and30is shifted by a predetermined value to the left.

In the embodiment ofFIG. 5where n=3, first the sign of the averaged phase parameter θ*iis determined, and in the cases indicated in block31(when the signs of the first two samplings are equal and different from the third sampling) the first sampling is selected; in block32(when all signs are equal) the second sampling is selected, and in block33(when the signs of the last two samplings are equal and different from the first sampling) the third sampling is selected. In all other cases, as in block34, it is then recognized that no relevant image with sharp, vertical edges is present and no change is made. Subsequently, a new check is made in the first three cases as to whether the absolute value of the phase parameter of the best sampling |θ*| has reached or exceeded a predetermined limit S. If this is not the case, no change is made, as in block34.

If a change must be made, the absolute values of the (averaged) phase parameters of the subsequent sampling|θ*| and the prior sampling |θ*| are compared, and the smaller value is in turn compared with a quarter of the absolute value of the phase parameter of the best sampling. If the smaller value is below this absolute value, the phase position is not changed as in step27; otherwise a shift occurs in step36to the right (if the absolute value of the previous phase parameter is greater that that of the following phase parameter), the shift otherwise occurring in block35to the left.

A five-digit digital number may be used, for example with values between 0 and 31 for the phase register. The phase register is incremented or decremented by 1 according to the above instruction. For transitions 0→31 and 31→0, it should be noted that the phase segment of the relevant sampling has been left and that the corresponding adjacent sampling has been selected. Thus, given n=2 and n=3 from the value 31 of the first sampling, and given an increment of 1, the value 0 must be taken from the second sampling. Given a value of 31 from the second sampling, for an increment of 1, the value 0 of the third sampling must be taken. In addition, given a change from the second to the first sampling (for n=2) and from the third to the first sampling (for n=3), the next pixel is selected. This is taken into account by adjustment device 11 for the shift of the Hsync signal. Via the HShft signal, and the latter is prompted to delay the Hsync signal for all on the input side by 0, 1, and 2 pixel-clock pulses; the start value after a reset is always 1. This results, first of all, in a negative shift, and secondly, in the fact that, for the next frame, the algorithm provides a result that lies in a noncritical region since all sampling values have been shifted by one pixel-clock pulse. This corresponds to a control region of the duration of one complete pixel.

The process may be illustrated in a table as follows:

LIST OF REFERENCE SYMBOLS

1. video signal curve2. center line3a. measured value of the white pixel in the first phase position3b. measured value of the white pixel in the second phase position3c. measured value of the white pixel in the third phase position4a. measured value of the black pixel in the first phase position4b. measured value of the black pixel in the second phase position4c. measured value of the black pixel in the third phase position5a. measured value of the black pixel in the first phase position5b. measured value of the black pixel in the second phase position5c. measured value of the black pixel in the third phase position6a. difference of the first measured values6b. difference of the second measured values6c. difference of the third measured values7. analog-to-digital converter8. synchronization separator9. interface filter10. PLL11. adjustment device for the Hsync12. detection device for the beginning of a test line13. evaluation device14. filter for averaging multiple lines15. signal phase determination device16. device for generating an analog-to-digital converter phase17,21,22,23additional circuit components19. frame processing device20. decimation device