Co-planar oxide semiconductor TFT substrate structure and manufacture method thereof

The present invention provides a co-planar oxide semiconductor TFT substrate structure and a manufacture method thereof. In the co-planar oxide semiconductor TFT substrate structure, the active layer comprises a main body and a plurality of short channels connected to the main body, and the plurality of short channels are separated with the plurality of strip metal electrodes to make the active layer possess higher mobility and lower leak current. Thus, the performance of the TFT element can be improved. The present invention provides a manufacture method of a co-planar oxide semiconductor TFT substrate structure. With forming the plurality of strip metal electrodes between the source and the drain, which are separately positioned, as deposing the oxide semiconductor layer, the plurality of short channels can be formed between the source and the drain. The method is simple and does not require additional mask or process to obtain the active layer structure different from prior art. The manufactured actively layer possesses higher mobility and lower leak current. Thus, the performance of the TFT element can be improved.

FIELD OF THE INVENTION

The present invention relates to a flat panel display field, and more particularly to a co-planar oxide semiconductor TFT substrate structure and manufacture method thereof.

BACKGROUND OF THE INVENTION

The active matrix panel display elements possess many merits of thin frame, power saving, no radiation, etc. and have been widely used. The Organic Light Emitting Diode (OLED) display technology is a flat panel display technology which has great prospects for development. It possesses extremely excellent display performance, and particularly the properties of self-illumination, simple structure, ultra thin, fast response speed, wide view angle, low power consumption and capability of realizing flexible display, and therefore is considered as the “dream display”. Meanwhile, the investment for the production equipments is far smaller than the TFT-LCD (Thin Film Transistor-Liquid Crystal Display). It has been favored by respective big display makers and has become the main selection of the third generation display element of the display technology field. At present, the OLED has reached the point before mass production. With the further research and development, the new technologies constantly appear, and someday, there will be a breakthrough for the development of the OLED display elements.

The Oxide Semiconductor possesses higher electron mobility and non crystalline structure, and has higher compatibility with the amorphous silicon process. Therefore, the Oxide Semiconductor has been widely utilized in the skill field of large scale Organic Light Emitting Display.

At present, the common structure of the oxide semiconductor TFT substrate is the ESL (Etching Stop Layer) structure. However, the structure itself has some problems. For example, the uniformity of the etching is difficult to control, and the additional mask and photolithographic process are required, and the gate overlaps with the source/the drain, and the storage capacitor is larger, and it is difficult to reach high resolution.

In comparison with the Etching Stop Layer structure, the Coplanar oxide semiconductor TFT substrate structure is more reasonable and has the production prospect which is more possible. As shown fromFIG. 1toFIG. 5, disclosed is a manufacture method of a co-planar oxide semiconductor TFT substrate structure according to prior art, comprising steps of:

step1, providing a substrate100, and deposing a first metal layer on the substrate100, and patterning the first metal layer with a photolithographic process to form a first gate210and a second gate220which are separately positioned;

step2, deposing a gate isolation layer300on the first gate210, the second gate220and the substrate100, and patterning the same with a photolithographic process to form a first via310in the gate isolation layer300correspondingly above the second gate220;

step3, deposing a second metal layer on the gate isolation layer300, and patterning the second metal layer with a photolithographic process to form a source410, a drain420, which are separately positioned, and forming a second via425on the drain420;

Specifically, the drain420is connected with the second gate220through the first via310.

step4, deposing an oxide semiconductor layer on the source410, the drain420and the gate isolation layer300, and patterning the same with a photolithographic process to form an active layer500, and the active layer500comprises a main body520and a channel510connected to the main body520between the source410and the drain420;

step5, deposing a passivation layer600on the active layer500, the source410and the drain420, and patterning the same with a photolithographic process to form a third via610in the passivation layer600correspondingly above the drain420.

Specifically, the passivation layer600fills in the second via425on the drain420.

In the co-planar oxide semiconductor TFT substrate structure manufactured by the aforesaid method, the channel510of the active layer500is a long channel. The active layer500possesses lower mobility and higher leak current. The performance of the TFT element is worse.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a co-planar oxide semiconductor TFT substrate structure. The active layer comprises a main body and a plurality of short channels connected to the main body between the source and the drain, and the plurality of short channels are separated with the plurality of strip metal electrodes to make the active layer possess higher mobility and lower leak current. Thus, the performance of the TFT element can be improved.

Another objective of the present invention is to provide a manufacture method of a co-planar oxide semiconductor TFT substrate structure. With one photolithographic process, the source, the drain and the plurality of strip metal electrodes between the source and the drain, which are separately positioned are formed, and as deposing the oxide semiconductor layer in the next process, the plurality of short channels can be formed between the source and the drain, and the plurality of short channels can separate the plurality of strip metal electrodes. The method is simple and does not require usage of additional mask or process to obtain the active layer structure different from prior art. The manufactured actively layer possesses higher mobility and lower leak current. Thus, the performance of the TFT element can be improved.

For realizing the aforesaid objectives, the present invention provides a co-planar oxide semiconductor TFT substrate structure, comprising a substrate, a first gate and a second gate on the substrate, a gate isolation layer on the first gate, the second gate and the substrate, a source, a drain on the gate isolation layer, a plurality of strip metal electrodes between the source and the drain, which are separately positioned, an active layer on the source, the drain, the strip metal electrodes and the gate isolation layer, a passivation layer on the active layer, the source and the drain;

wherein the active layer comprises a main body and a plurality of short channels connected to the main body between the source and the drain, and the plurality of short channels are separated with the plurality of strip metal electrodes.

The gate isolation layer is provided with a first via correspondingly above the second gate, and the drain is connected with the second gate through the first via.

The drain is provided with a second via, and the passivation layer fills in the second via; the passivation layer is provided with a third via correspondingly above the drain.

Material of the active layer is metal oxide; material of the first gate and the second gate is copper, aluminum or molybdenum; material of the gate isolation layer is silicon oxide or silicon nitride.

Material of the source, the drain and the strip metal electrodes is copper, aluminum or molybdenum, and material of the passivation layer is silicon oxide or silicon nitride.

The present invention further provides a manufacture method of a co-planar oxide semiconductor TFT substrate structure, comprising steps of:

step1, providing a substrate, and deposing a first metal layer on the substrate, and patterning the first metal layer with a photolithographic process to form a first gate and a second gate which are separately positioned;

step2, deposing a gate isolation layer on the first gate, the second gate and the substrate, and patterning the same with a photolithographic process to form a first via in the gate isolation layer correspondingly above the second gate;

step3, deposing a second metal layer on the gate isolation layer, and patterning the second metal layer with a photolithographic process to form a source, a drain and a plurality of strip metal electrodes between the source and the drain, which are separately positioned;

the drain is connected with the second gate through the first via;

a second via is formed on the drain;

step4, deposing an oxide semiconductor layer on the source, the drain, the strip metal electrodes and the gate isolation layer, and patterning the same with a photolithographic process to form an active layer, and the active layer comprises a main body and a plurality of short channels connected to the main body between the source and the drain, and the plurality of short channels are separated with the plurality of strip metal electrodes;

step5, deposing a passivation layer on the active layer, the source and the drain, and patterning the same with a photolithographic process to form a third via in the passivation layer correspondingly above the drain;

the passivation layer fills in the second via on the drain.

Material of the active layer is metal oxide.

Material of the first gate and the second gate is copper, aluminum or molybdenum; material of the gate isolation layer is silicon oxide or silicon nitride.

Material of the source, the drain and the strip metal electrodes is copper, aluminum or molybdenum.

Material of the passivation layer is silicon oxide or silicon nitride.

The present invention further provides a manufacture method of a co-planar oxide semiconductor TFT substrate structure, comprising steps of:

step1, providing a substrate, and deposing a first metal layer on the substrate, and patterning the first metal layer with a photolithographic process to form a first gate and a second gate which are separately positioned;

step2, deposing a gate isolation layer on the first gate, the second gate and the substrate, and patterning the same with a photolithographic process to form a first via in the gate isolation layer correspondingly above the second gate;

step3, deposing a second metal layer on the gate isolation layer, and patterning the second metal layer with a photolithographic process to form a source, a drain and a plurality of strip metal electrodes between the source and the drain, which are separately positioned;

the drain is connected with the second gate through the first via;

a second via is formed on the drain;

step4, deposing an oxide semiconductor layer on the source, the drain, the strip metal electrodes and the gate isolation layer, and patterning the same with a photolithographic process to form an active layer, and the active layer comprises a main body and a plurality of short channels connected to the main body between the source and the drain, and the plurality of short channels are separated with the plurality of strip metal electrodes;

step5, deposing a passivation layer on the active layer, the source and the drain, and patterning the same with a photolithographic process to form a third via in the passivation layer correspondingly above the drain;

the passivation layer fills in the second via on the drain;

wherein material of the active layer is metal oxide;

wherein material of the first gate and the second gate is copper, aluminum or molybdenum; material of the gate isolation layer is silicon oxide or silicon nitride;

wherein material of the source, the drain and the strip metal electrodes is copper, aluminum or molybdenum;

wherein material of the passivation layer is silicon oxide or silicon nitride.

The benefits of the present invention are: the present invention provides a co-planar oxide semiconductor TFT substrate structure and a manufacture method thereof. In the co-planar oxide semiconductor TFT substrate structure, the active layer comprises a main body and a plurality of short channels connected to the main body, and the plurality of short channels are separated with the plurality of strip metal electrodes to make the active layer possess higher mobility and lower leak current. Thus, the performance of the TFT element can be improved. The present invention provides a manufacture method of a co-planar oxide semiconductor TFT substrate structure. With one photolithographic process, the source, the drain and the plurality of strip metal electrodes between the source and the drain, which are separately positioned are formed, and as deposing the oxide semiconductor layer in the next process, the plurality of short channels can be formed between the source and the drain, and the plurality of short channels can separate the plurality of strip metal electrodes. The method is simple and does not require usage of additional mask or process to obtain the active layer structure different from prior art. The manufactured actively layer possesses higher mobility and lower leak current. Thus, the performance of the TFT element can be improved.

In order to better understand the characteristics and technical aspect of the invention, please refer to the following detailed description of the present invention is concerned with the diagrams, however, provide reference to the accompanying drawings and description only and is not intended to be limiting of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Please refer toFIG. 1. The present invention first provides a co-planar oxide semiconductor TFT substrate structure, comprising a substrate10, a first gate21and a second gate22on the substrate10, a gate isolation layer30on the first gate21, the second gate22and the substrate10, a source41, a drain42on the gate isolation layer30, a plurality of strip metal electrodes43between the source41and the drain42, which are separately positioned, an active layer50on the source41, the drain42, the strip metal electrodes43and the gate isolation layer30, a passivation layer60on the active layer50, the source41and the drain42;

wherein the active layer50comprises a main body51and a plurality of short channels52connected to the main body51between the source41and the drain42, and the plurality of short channels52are separated with the plurality of strip metal electrodes43.

Specifically, the gate isolation layer30is provided with a first via31correspondingly above the second gate22, and the drain42is connected with the second gate22through the first via31.

The drain42is provided with a second via421, and the passivation layer60fills in the second via421.

The passivation layer60is provided with a third via61correspondingly above the drain42.

Preferably, material of the first gate21and the second gate22is copper, aluminum or molybdenum.

Material of the gate isolation layer30is silicon oxide or silicon nitride.

Material of the source41, the drain42and the strip metal electrodes43is copper, aluminum or molybdenum.

Specifically, material of the active layer50is metal oxide, and preferably, the metal oxide is Indium Gallium Zinc Oxide (IGZO).

Preferably, material of the passivation layer60is silicon oxide or silicon nitride.

The present invention provides a co-planar oxide semiconductor TFT substrate structure. The channel of the active layer50is composed by a plurality of short channels52, which are separately positioned. In comparison with prior art, it is equivalent to that the original long channel510(as shown inFIG. 5) is divided into several short channels52, which are separately positioned. According to the short channel effect of the element, by changing the width and dimension of the short channel52, the performance parameters, such as the gate voltage (Vth), the switch speed (S.S.), the working current (Ion) and leakage current (Ioff) of the TFT element can be regulated to improve the performance of the TFT element without adding photo or other processes.

Please refer fromFIG. 6toFIG. 11. The present invention further provides a manufacture method of a co-planar oxide semiconductor TFT substrate structure, comprising steps of:

step1, as shown inFIG. 8, providing a substrate10, and deposing a first metal layer on the substrate10, and patterning the first metal layer with a photolithographic process to form a first gate21and a second gate22which are separately positioned.

Preferably, material of the first gate21and the second gate22is copper, aluminum or molybdenum.

step2, as shown inFIG. 9, deposing a gate isolation layer30on the first gate21, the second gate22and the substrate10, and patterning the same with a photolithographic process to form a first via31in the gate isolation layer30correspondingly above the second gate22.

Preferably, material of the gate isolation layer30is silicon oxide or silicon nitride.

step3, as shown inFIG. 10, deposing a second metal layer on the gate isolation layer30, and patterning the second metal layer with a photolithographic process to form a source41, a drain42and a plurality of strip metal electrodes43between the source41and the drain42, which are separately positioned.

Specifically, the drain42is connected with the second gate22through the first via31.

Specifically, a second via421is formed on the drain42.

Specifically, the source41, the drain42and the strip metal electrodes43are formed with one photolithographic process.

Preferably, material of the source41, the drain42and the strip metal electrodes43is copper, aluminum or molybdenum.

step4, as shown inFIG. 11, deposing an oxide semiconductor layer on the source41, the drain42, the strip metal electrodes43and the gate isolation layer30, and patterning the same with a photolithographic process to form an active layer50, and the active layer50comprises a main body51and a plurality of short channels52connected to the main body51between the source41and the drain42, and the plurality of short channels52are separated with the plurality of strip metal electrodes43.

Specifically, material of the active layer50is metal oxide, and preferably, the metal oxide is Indium Gallium Zinc Oxide (IGZO).

With one photolithographic process of step3of the present invention, the source41, the drain42and the plurality of strip metal electrodes43between the source41and the drain42, which are separately positioned are formed, and as deposing the oxide semiconductor layer in step4, the plurality of short channels52can be formed between the source41and the drain42, and the plurality of short channels52can separate the plurality of strip metal electrodes43. The method is simple and does not require additional mask or process to obtain the active layer structure different from prior art. The manufactured actively layer50possesses higher mobility and lower leak current. Thus, the performance of the TFT element can be improved.

step5, deposing a passivation layer60on the active layer50, the source41and the drain42, and patterning the same with a photolithographic process to form a third via61in the passivation layer60correspondingly above the drain42. Accordingly, the co-planar oxide semiconductor TFT substrate structure shown inFIG. 6can be obtained.

Specifically, the passivation layer60fills in the second via421on the drain42.

Preferably, material of the passivation layer60is silicon oxide or silicon nitride.

The present invention provides a manufacture method of a co-planar oxide semiconductor TFT substrate structure. With one photolithographic process, the source, the drain and the plurality of strip metal electrodes between the source and the drain, which are separately positioned are formed, and as deposing the oxide semiconductor layer in the next process, the plurality of short channels can be formed between the source and the drain, and the plurality of short channels can separate the plurality of strip metal electrodes. The method is simple and does not require additional mask or process to obtain the active layer structure different from prior art. The manufactured actively layer possesses higher mobility and lower leak current. Thus, the performance of the TFT element can be improved.

In conclusion, in a co-planar oxide semiconductor TFT substrate structure provided by the present invention, the active layer comprises a main body and a plurality of short channels connected to the main body between the source and the drain, and the plurality of short channels are separated with the plurality of strip metal electrodes to make the active layer possess higher mobility and lower leak current. Thus, the performance of the TFT element can be improved. The present invention provides a manufacture method of a co-planar oxide semiconductor TFT substrate structure. With one photolithographic process, the source, the drain and the plurality of strip metal electrodes between the source and the drain, which are separately positioned are formed, and as deposing the oxide semiconductor layer in the next process, the plurality of short channels can be formed between the source and the drain, and the plurality of short channels can separate the plurality of strip metal electrodes. The method is simple and does not require usage of additional mask or process to obtain the active layer structure different from prior art. The manufactured actively layer possesses higher mobility and lower leak current. Thus, the performance of the TFT element can be improved.