Digital low power symbol rate detector

This detector provides a computationally simple digital low power detector of symbol rate, also called baud rate. It uses an approximate Hilbert transform function to create approximate in-phase and quadrature signals. An approximate envelope detector (feature extractor) processes these signals to produce a signal with a strong frequency component at the symbol rate. This signal is then filtered, accumulated, and threshold detected. The approximate in-phase and quadrature signals are formed by a linear sequence of six delay elements, the output of the third delay element being the in-phase signal. A first summer receives the output of the second delay element at a minus input and the output of the fourth delay element at a plus input. A second summer receives the signal input at a minus input and the output of the sixth delay element at a plus input, and drives a right two bit shifter. A third summer receives the output of the right two bit shifter and the output of the first summer and drives both a right one bit shifter and a right three bit shifter, the outputs of which are summed to form the quadrature signal.

BACKGROUND OF THE INVENTION 
This invention relates to communications and to signal processing of 
digitally modulated signals. It has particular reference to timing 
recovery in demodulation systems, type recognition for both commercial and 
military applications, and signal detection, especially as a chip rate 
detector for wide band signal detection. 
Many of the applications referred to above require simple, low power, low 
cost implementations. However, traditional digital solutions to this 
problem require significant computation. This translates directly to 
increased size, cost, and power requirements. 
SUMMARY OF THE INVENTION 
The present invention overcomes these problems by providing a 
computationally simple digital low power detector of symbol rate, also 
called baud rate. It uses an approximate Hilbert transform function to 
create approximate in-phase and quadrature signals. An approximate 
envelope detector (feature extractor) processes these signals to produce a 
signal with a strong frequency component at the symbol rate. This signal 
is then filtered, accumulated, and threshold detected. 
The approximate in-phase and quadrature signals are formed by a linear 
sequence of six delay elements, the output of the third delay element 
being the in-phase signal. A first summer receives the output of the 
second delay element at a minus input and the output of the fourth delay 
element at a plus input. A second summer receives the signal input at a 
minus input and the output of the sixth delay element at a plus input, and 
drives a right two bit shifter. A third summer receives the output of the 
right two bit shifter and the output the first summer and drives both a 
right one bit shifter and a right three bit shifter, the outputs of which 
are summed to approximate the quadrature signal.

DETAILED DESCRIPTION OF THE DRAWINGS Block Overview 
In FIG. 1 (a block overview of the present invention), a symbol rate 
detector 10 has an in-phase and quadrature (I&Q) generator 12, a feature 
extractor 14, a filter combination 16, and an accumulator-detector 18. 
The I&Q generator 12 includes a signal input 20 (which receives input 
signals to the symbol rate detector 10), an in-phase signal output 22, and 
a quadrature signal output 24. The details of the I&Q generator are shown 
in FIG. 2. 
The feature extractor 14 includes, in the preferred embodiment, a first 
means 26, connected to the in-phase signal output 22, for taking the 
absolute value of the in-phase signal. It also includes a second means 28, 
connected to the quadrature signal output 24, for taking the absolute 
value of the quadrature signal. The outputs of the first and second means 
are summed in a summer 30. 
The filter combination 16 includes a first band pass filter 32 centered at 
the timing frequency and a second band pass filter 34 centered at a 
reference frequency adjacent to the timing frequency. Each band pass 
filter 32, 34 receives the output of the summer 30, and each band pass 
filter 32, 34 delivers its output to the accumulator-detector 18. 
The accumulator-detector 18 includes a timing absolute-accumulator means 
36, receiving the output of the first band pass filter 32, and a reference 
absolute-accumulator means 38, receiving the output of the second band 
pass filter 34. Each of these absolute-accumulator means 36, 38 includes a 
means for taking the absolute values of its input signals, and for 
accumulating these respective absolute values. The difference between the 
respective accumulated absolute values is determined by a differencer 40, 
which in turn drives a threshold detector 42. The output of the threshold 
detector 42 is the output of the symbol rate detector 10. 
Details of the I&Q Generator 
FIG. 2 is a more detailed view of the in-phase and quadrature signal 
generator 12 of FIG. 1. The input signal drives a linear sequence of six 
delay elements 44, 46, 48, 50, 52, and 54. The output of the third delay 
element 48 is the in-phase signal. A first summer 56 receives the output 
of the second delay element 46 at a minus input and the output of the 
fourth delay element 50 at a plus input. A second summer 58 receives the 
signal input at a minus input and the output of the sixth delay element 54 
at a plus input. The second summer 58 drives a right two bit shifter 60, 
shown as a box around "1/4" since the effect is to divide by four. A third 
summer 62 receives the output of the right two bit shifter 60 and the 
output of the first summer 56. The third summer 62 drives both a right one 
bit shifter 64 (box with "1/2") and a right three bit shifter 66 (box with 
"1/8"), the outputs of which are summed on a fourth summer 68 to 
approximate the quadrature signal. 
Other Embodiments of the Feature Extractor 
The feature extractor 14 shown in FIG. 1 is the preferred embodiment. Other 
embodiments are shown in FIGS. 3-5. 
In FIG. 3, a first alternate feature extractor 14' is shown. In it, the I 
and Q signals do not drive the absolute value means 26 and 28 directly. 
Instead, they drive a comparator 70, which determines which of the signals 
is larger. The comparator 70 routes that larger signal directly to one of 
the absolute value means, shown in FIG. 3 as means 28. The smaller signal 
is first directed to a one bit right shifter 72, the output of which is 
applied to the other absolute value means, shown in FIG. 3 as 26. The 
remainder of FIG. 3's first alternate feature extractor 14' is the same as 
FIG. 1's preferred feature extractor 14. 
In FIG. 4, a second alternate feature extractor 14" is shown. In it, the I 
and Q signals do not drive the absolute value means 26 and 28, but instead 
drive squaring means 74 and 76. The remainder of FIG. 4's second alternate 
feature extractor 14" is the same as FIG. 1's preferred feature extractor 
14. 
In FIG. 5, a third alternate feature extractor 14'" is shown. It is the 
same as that shown in FIG. 4, except that a square root extractor 78 is 
driven by the summer 30. It is the output of the square root extractor 78 
which is passed on to the filter combination 16, rather than the output of 
the summer 30 being passed on directly. 
Scope of the Invention 
Several embodiments of the present invention have been shown, but the true 
spirit and scope of the present invention are not limited thereto. 
Instead, such spirit and scope are limited only by the appended claims, 
and their equivalents.