Semiconductor device, memory device and memory module having digital interface

An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

CLAIM OF PRIORITY

The present application claims priority from Japanese application serial no. 2004-217509, filed on Jul. 26, 2004, the content of which is hereby incorporated by reference into this application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a bus connection technique for connecting among functional circuits such as a processor, a memory, etc., which is used in an information processing apparatus such as a personal computer or the like, and its constituent elements, and particularly to a semiconductor device which realizes low jitter in a digital signal interface.

2. Description of the Related Art

When digital data is transferred among functional circuits such as a processor, a memory, etc. in an apparatus, a physical portion related to the data transfer is divided into two. That is, they are transmission lines which connect between a semiconductor device (hereinafter called “LSI”) for realizing a functional circuit and an LSI. They are collectively called “interface”. Although the speeding up of the interface is essential to an improvement in the performance of the apparatus, the speeding up thereof is becoming difficult due to physical restrictions on the transmission lines.

When the transfer of data is performed between two LSIs14and16as shown inFIG. 3, for example, waveform blunting occurs due to a dielectric loss or a skin effect at a high frequency of a data bus wire15. An example of a blunt waveform is illustrated inFIG. 4. Let's assume that binary data like a data signal320is outputted from an LSI on the transmission side through a driver14inFIG. 4. A waveform321is a waveform which has reached an input terminal of a receiver16. This results in the input waveform of the receiver16. The receiver16receives the waveform321therein and returns it to a rectangular pulse. This waveform is designated at numeral322. Here, the waveform322greatly changes in waveform width with respect to the transmitted pulse320. This results from the following reasons.

Now, a rectangular wave is driven from L to H and H to L, and such a waveform321that data has reached the receiver16, indicates blunting due to the previous effect. When a rising pulse is transmitted from L to H, for example, blunting occurs in the waveform321transmitted through a wire, so that the signal is not capable of perfectly rising to an H voltage during one cycle or it cannot be perfectly charged in another expression. Therefore, the signal remains at a perfectly non-charged voltage even if the time at which the next cycle starts is reached.

Upon the high-speed data transfer, the next data is transmitted before its charge is completed. Therefore, the input waveform321of the receiver16varies according to data in the previous cycle in terms of the voltage waveform of the data. This is called “data/pattern dependency or Inter Symbol Interference (ISI)”, which is one problem about speeding-up.

This shows that a setup time corresponding to a time width necessary to determine data and a hold time become short for the LSI on the receiving side. When the threshold voltage for reception is defined as VREF0, the times at which the waveform crosses it, vary according to data patterns at T1, T2, T3and T4. . . . This variation is called “jitter”. When the jitter increases, the time width (data window) necessary to determine the data cannot be ensured so that the rate of failure of data transfer increases. That is, it is not possible to perform higher-speed data transfer due to the waveform blunting.

In order to avoid it, there have been proposed such prior arts as shown in Dana Hall, et al., “Method for Transmitting Data over a Data Bus with Minimized Digital Inter-Symbol Interference”, U.S. Pat. No. 6,577,687 B2 June, 2003 and Sanjay Dabral. et. al, “Data-Pattern Induced Skew Reducer”, U.S. Pat. No. 5,953,521, September, 1999.

When the binary signal is transmitted through such a bus-connected data wire as shown inFIG. 3, actual data is transmitted in wait for a while (in wait for a sufficient reduction in voltage) without sending the actual data from a first cycle, thereby avoiding an error due to jitter. Since the reverse symbol of data was transmitted where one bit string has continued, the jitter could be reduced.

As described in U.S. Pat. No. 5,953,521, jitter reduced by data patterns was reduced by controlling driver's timing. That is, data lying in the present cycle and data lying in the immediately preceding cycle were compared. When they were found to be different from each other, a high frequency delay circuit (HF) was added with the data lying in the present cycle, whereas when they were found to be the same, a low frequency delay circuit (LF) was added with the data, thereby expanding a data window. Thus, although the jitter on the driver side can be reduced, the jitter on the receiver side cannot be reduced. This specification does not show such a disclosure as to determine a delay time or amount of the high frequency delay circuit and a delay time or amount of the low frequency delay circuit.

When such a technique as disclosed in U.S. Pat. No. 5,953,521 is used, dependency on a data pattern between continuous 2 bits can be controlled or adjusted. However, it was not possible to control a delay time or amount of dependency on data patterns of 3 bits or more.

If the state of the transmission line between LSIs is known in advance, then the delay time of the high frequency delay circuit and the delay time of the low frequency delay circuit can be determined at the stage of design of LSIs. However, when the LSI is used in a plurality of devices, the delay times cannot be determined uniquely. This is because the delay time necessary for jitter control varies for each device according to the condition of packaging of the transmission line.

A problem that the invention is to solve is to reduce jitter dependent on data patterns by an interface receiver. Another problem to be solved by the invention is to provide an LSI capable of automatically controlling the setting of a delay time for jitter reduction so as to be able to control its setting for each device.

SUMMARY OF THE INVENTION

Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data.

As a control mechanism lying in the receiver, for determining a delay time dependent on the form of packaging, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Since the receiver is configured like the previous means, the jitter dependent on the data patterns having reached the receiver can be reduced. Thus, the speeding up of data is further enabled. Since the delay time for jitter reduction can be set by the automatic delay control circuit mechanism, the delay time can automatically be adjusted even in the case of transmission lines different in cable length or the like every devices. Therefore, it is possible to provide an LSI having a general-purpose interface free of device dependency.

PREFERRED DESCRIPTION OF THE EMBODIMENTS

First Preferred Embodiment

A first embodiment will be explained usingFIG. 1.

Reference numeral100indicates a deskew receiver having a jitter control circuit function, according to the present invention. The deskew receiver100receives a data signal20connected to a transmission line and a clock signal (φ)210as inputs. The data signal20is synchronized with the clock signal210and outputted as an output signal201.

The deskew receiver100comprises a differential comparator10, a latch11, a delay controller12and a variable delay13.

The data signal20is compared with a reference voltage (VREF0) inputted to the differential comparator10. Each of “0” and “1” is outputted as a receiver output signal200according to the magnitude thereof. The receiver output signal200is inputted to the latch11and the delay controller12. The latch11calculates a delay amount or time in accordance with a signal outputted from the delay controller12and is inputted with a clock signal203delayed by the variable delay13.

The clock signal203is produced by adding a delay time to the clock signal (φ)210by the variable delay13and subtracting it therefrom thereby. The variable delay13adjusts or controls a delay time in accordance with a signal202outputted from the delay controller12. The delay controller12inputs the receiver output signal200and the synchronized output signal201therein and outputs the delay control signal202.

Control corresponding to such a delay ΔTi as shown inFIG. 2is performed by a combination of the delay controller12and the variable delay13.

FIG. 2shows an input wave of the signal20indicative of various data, the clock signal210, the latch signal203, etc. The horizontal axis indicates the time and the vertical axis indicates the voltage. The input waveform of the data signal20is plotted by superimposing five waveforms301through305on one another.

The waveform301indicates a waveform having L at which an input data pattern prior to a time T0continues, and H continuous till a time T6. Now, the times T0through T5indicated by dotted lines indicate cycles of the data inputted to the deskew receiver100having the jitter control circuit function. Incidentally, when a data pattern continuous in an intended range is represented as L*, the data pattern ( . . . LLLLHHH . . . ) of the waveform301can be described as (L*H*).

The waveform302is represented as L before the time T0, H during one cycle and then L at the time T2and subsequently. This data pattern can be represented as (L*HL*).

Similarly, the waveform303is represented as (L*HHL*) at which H continues during two cycles, the waveform304is represented as (L*HHHL*) at which H continues during three cycles in succession, and the waveform305is a waveform corresponding to a data pattern represented as (L*HHHHL*) at which H continues during four cycles, respectively. Since sections identical in data pattern to one another, of the waveforms301through305draw the same traces inFIG. 2, they are represented so as to overlap one another.

The waveform301is placed in an H state at the time T0and subsequently and draws approximately a charge curve due to blunting or desensitization of the transmission line. Of course, reflection and crosstalk caused by impedance mismatching on the transmission line also overlap. In the case of a well-designed transmission line, however, these reflection/crosstalk noise are small but waveform blunting due to a dielectric loss and a skin effect at a high frequency is large. Thus, the waveform at a receiving terminal grows dull or blunt as designated at301.

When the data changes before it perfectly rises or before its charge, a waveform trace in the next cycle greatly changes. Since L starts from the position on the way to the charge of the waveform301, the waveform302shown inFIG. 2becomes earlier than the waveform301in time at which it comes across the reference voltage VREF0. Assuming that the time at which the waveform301comes across the reference voltage VREF0is taken as the reference, it is understood that the respective waveforms302through305respectively have time differences among time intervals at which they cross the VREF0. The time differences are respectively represented as ΔT1through ΔT4(or ΔTi) with respect to the waveforms302through305.

Reference numeral210inFIG. 2indicates the clock signal210inFIG. 1, and reference numerals200-1through200-3respectively indicate output waveforms of the differential comparator10. The input data correspond to (1) L*HL* (2) L*HH*L and (3) L*HHHL* respectively. Here, the delay time of the differential comparator10has been described as being negligible. Reference numerals203-1through203-3respectively indicate clock signals having delay times conforming to the input data patterns, which are delayed by the variable delay13and the delay controller12on the basis of the clock signal210. The latch11latches the corresponding data therein in accordance with the signals203-1through203-3.

The delay controller12and the variable delay13shown inFIG. 1are operated so as to adjust the time differences of ΔT1through ΔT4with respect to the waveforms302through305inFIG. 2and thereby generate the delayed clock signals203-1through203-3or the like. Here, ΔT1through ΔT4indicate differences among timing fetching times, based on data pattern differences and correspond to time constants included in the delay controller12in advance.

A method of specifically generating the delayed clock signal203for data fetching will next be explained.

The initial clock210is in sync with the times T0through T6.

When the input data20is processed as follows:

(1) With respect to L*H*L* input (waveform302)

The output waveform of the differential comparator10with respect to the input data is designated at200-1. The delay controller12functions so as to allow the variable delay13to make the receiver output200-1in a T0cycle (between T0and T1) earlier by k×ΔT1. The latch11takes it therein in accordance with the clock signal203-1of the variable delay13. Here, k indicates a suitable constant such as 0.5. While a solid line and a dotted line are being provided in203-1, the solid line means a signal determined in an intended data cycle, and the dotted line means an undetermined signal. By operating the receiver in this way, a stable setup and a stable hold time can be ensured upon capturing of H data in the T0cycle.

(2) With respect to (L*HHL*) input (waveform303)

The output waveform of the differential comparator10with respect to the input data is designated at200-2. The delay controller12functions so as to cause the variable delay13to make the waveform receiver output200-2in a T1cycle (between T1and T2) earlier by k×ΔT2. The latch11captures it therein in accordance with the clock signal203-2of the variable delay13. By operating the receiver in this way, a stable hold time can be ensured upon stably capturing of H data in the T1cycle.

(3) With respect to (L*HHHL*) input (waveform304)

Similarly, the delay controller12is operated to allow the variable delay13to make fetch timing of the latch11earlier by k×ΔT3in a T2cycle (between T2and T3). By operating the receiver in this way, a stable hold time can be ensured upon capturing H data in the T2cycle.

With the receiver being operated in this way, a timing window can be expanded and data can be latched on the safe side even in the case of any data pattern from L*, with the result that its speeding up can be achieved.

Similarly, a similar effect is shown even on the falling edge like (H*LH*). Here, H* means the state of continuous H data. When a transmission LSI not described in the drawing is well designed, the output impedance of a driver of the LSI can be regarded as substantially identical between both L and H, and the rising edge and falling edge can be made identical in signal amplitude. Therefore, the delay controller12and the variable delay13can be operated in the same manner except for polarity.

If the delay controller12and the variable delay13are operated in this way, then the deskew receiver100having the jitter control circuit function is capable of fetching data regardless of pre-cycle data like (L*H) and (H*L), thus making it possible to reduce jitter with respect to these input data.

A configuration of the delay controller12which performs such an operation, is shown inFIG. 5.

The delay controller12is inputted with a receiver output signal200and a synchronized output signal201. Then, the delay controller12is internally processed and thereafter outputs a delay control signal202.

Now consider where a reduction in jitter is effected on an input signal corresponding to an nth cycle from the start of signal transfer. The state of 0 or 1 in the nth cycle will be expressed in Qn. Data Qn−1corresponding to a previous (n−1)th cycle is held in the synchronized output signal201. When the data corresponding to the nth cycle is different from the data corresponding to the (n−1)th cycle, i.e., Qn≠Qn−1, that is, when data switching occur on the rising edge or falling edge, an exclusive OR (XOR) circuit123which XORs both of the receiver output signal200and the synchronized output signal201detects this switching. A signal125outputted from the XOR circuit123is retained in a latch124and inputted to a delay selection circuit122.

Further, reference numeral121indicates a voltage holding circuit for an (n−1)th cycle. The voltage holding circuit121holds eight voltage states.

Input waveforms shown inFIG. 6are used to describe the operation thereof.

FIG. 6shows input waveforms inputted to the receiver every data transfer cycles as in the case of times T0, T1, T2, . . . . A solid line310indicates a rising waveform at the time T0, and a broken line311indicates a falling waveform at the time T0, respectively. These waveforms are not perfectly brought to an H state even at the time T1subsequent to one cycle. Voltages at the times T1, T2, T3and T4are respectively assumed to be w1, w2, w3and w4with respect to the rising waveform310. Similarly, voltages thereat are respectively defined as u1, u2, u3and u4with respect to the falling waveform311. This figure shows that these are charged to approximately signal amplitude after 4 cycles from data switching. However, they might be longer or shorter than it depending on the system. Although ui and wi are different in the number of states in these cases, the essential operation of the present invention is the same.

Assuming that when a transition occurs in the nth cycle, the time corresponding to the nth cycle is expressed in Tn−1, an input waveform voltage v(t) of the differential comparator10connected with the transmission line is expressed as follows:a) Initial condition (state prior to transfer of data)
v(t)=Vol or Voh (t<0)   (1)

where Vol indicates an L state output voltage of the driver connected to the transmission line, and Voh indicates an H state output voltage. Since the input waveform voltage v(t) is expressed by superimposing signal amplitude of w1as viewed from Vol or signal amplitude of u1as viewed from Voh on v(Tn−1), the input waveform voltage v(t) corresponding to the nth cycle is as follows:b) Input voltage v(t) corresponding to the nth cycle
v(t)=v(Tn−1)+Q′n−1u(t−Tn−1)v0(t−Tn−1) (Tn−1<t≦Tn)   (2)

where v(Tn−1) indicates an input voltage at a start time (Tn−1) of the nth cycle, and Q′n−1indicates differential of data Q in the (n−1)th cycle and nth cycle. When a transition occurs, {+1 and −1} are taken, and the former means rising whereas the latter means falling. When no transition occurs, “0” is taken. Further, v0(t) indicates a voltage function of a rising pulse relative to a single pulse input L*H*. Also u(t) indicates a unit function and is defined as follows:c)
u(t)=1(t≧0)=0(t<0)   (3)

Although the previous wi and ui (where i=1, 2, 3 and 4) are voltages dispersed on the rising (L*H*) and falling (H*L*), they are identical in post-data switching amplitude despite of the previous states. Therefore, when the voltages subsequent to switching cycle (Tn) reach either wi or ui even if the previous data corresponds to any of wi and ui, they can be made approximate. That is, it can be said that the input voltage has eight states of wi and ui.

These eight states and their transitions can be arranged as shown inFIG. 7. The present figure is a diagram showing a relationship of transition between continuous two data Qn−1and Qnin the delay controller12. These are equal to transitions among eight states {wi, ui; i={1, 2, 3, 4}} shown inFIG. 6.

wi and ui surrounded by circles indicate internal states of the delay controller12, and arrows indicate state transitions each corresponding to the value of Q′n. Now, consider where Q′nrepresents logical differentiation of Qn, and where when the transition occurs, “1” is taken, whereas when no transition occurs, “0” is taken. Although the same symbols as the expression (2) of the analog quantity are used, the same symbols are used because discussion gets untangled.

ui falls as shown inFIG. 6. In contrast, when no data switching exists (Q′n=0), u2makes a transition to u3and u3makes a transition to u4. These are expressed in ui→ui+1. Since the voltage remains unchanged where the next cycle is the same data (Q′n=0) in the case of u4, a state transition to the same u4is taken. Similarly, wi→wi+1 indicates a state transition (Q′n=0) free of data switching with respect to the rising waveform. The state transition from w4remains unchanged because of no change in voltage.

A description will next be made of a case in which data switching is performed from these states wi and ui (Q′n=1).

Since they are identical in switching voltage width, state transitions to u1→w4, u2→w3, u3→w2and u4→w1are made. The inverse thereof also makes state transitions to w4→u1, w3→u2, w2→u3, w1→u4in the same combination.

Those described in parentheses ( ) inFIG. 7indicate delay times to be set by the variable delay13. That is, the transition to u1→w4needs ΔT1for jitter reduction. However, this corresponds to the input waveform302of L*H*L inFIG. 2. Similarly, w1→u4also needs the same ΔT1because the polarity of the input waveform simply varies. Similarly, u2→w3and w2→u3correspond to the waveform303shown inFIG. 2need ΔT2for jitter reduction. Further, u3→w2and w3→u2correspond to the waveform304shown inFIG. 2need ΔT3for jitter reduction.

WhileFIGS. 6 and 7has explained as described above that the behaviors of the input waveform of the receiver connected with the transmission line are considered to be the dispersed state transitions, and the transitions are provided as a finite number and regarded as the delay times necessary for jitter reduction,FIGS. 6 and 7will be defined as functional specs of the delay controller12and variable delay13shown inFIG. 1. That is, the delay controller12includes thereinside the eight states shown inFIG. 7. The delay controller12brings their transitions to state transitions according to data switching. Further, the delay controller12is operated so as to determine the delay time of the variable delay13with respect to each of the transitions, thereby making it possible to reduce jitter.

Referring toFIG. 5, the voltage holding circuit121is operated so as to make each state transition as shown inFIG. 7and hold the voltage in the (n−1)th cycle. This can be realized by, for example, configuring it as an integration circuit having a time constant (τ=RC), based on a resistor R and a variable capacitor C on an analog basis. Because this results from the following. That is, the input of the voltage holding circuit121corresponds to the synchronized output signal201. This can show data pattern dependency corresponding to the same behavior as the input waveform of the differential comparator10because the latch11outputs binary data and charge/discharge is carried out with the binary data as a voltage source. Here, the time constant (τ=RC) of the voltage holding circuit121needs not to be identical to time constant of the input waveform shown inFIG. 6. This is because the voltage holding circuit121has such time constant as to be substantially saturated in the 4 cycles ofFIG. 6and may distinguish among those states. Then, a state monitoring buffer127detects each state stably. This can be configured of a multistage comparator. Thus, the voltage holding circuit121is capable of outputting the eight states.

Summarizing the delay time amounts necessary for jitter reduction every hours usingFIG. 7yields the following:
ΔT1=Q′n(u1+w1)
ΔT2=Q′n(u2+w2)
ΔT3=Q′n(u3+w3)
ΔT4=Q′n(u4+w4)=0   (4)
This computation is performed by the delay selection circuit122. Here, Q′nis realized by the output signal125of the XOR circuit123, which has been retained in the latch124. The data lying in parentheses ( ) are realized by a signal126outputted from the voltage holding circuit121. Making the product of these output signals125and126enables the generation of the delay control signal202.

Thus, since the delay controller12is operated as shown inFIGS. 5 and 7, the delay controller12is capable of generating the delay control signal202indicative of a jitter-reduced amount ΔTi corresponding to the input wave. The delay control signal202generated by the delay controller12is inputted to the variable delay13shown inFIG. 1from which a delay time corresponding to the value of the delay control signal202is generated. That is, when the delay control signal202is of a signal corresponding to ΔT1, the variable delay13makes a ΔT1time early. Similarly, when the delay control signal202is of a signal corresponding to ΔT2, the variable delay13makes a ΔT2time early. The following are performed in like manner.

Since it is generally not possible to make the time early, the time equal to half as much as a constant time, e.g., a data cycle is provided in advance. In contrast, the variable delay can be configured which has such an effect as to make the time early by making ΔTi early. In this case, the delay time of the variable delay13has a positive value in any case.

The implement of the variable delay13may be configured so as to vary the delay time by connecting delay elements in serial-parallel form and controlling the number of stages thereof. Alternatively, even control on a delay time interval by varying the voltage corresponding to the delay control signal202can perform the action similar to above.

Second Preferred Embodiment

A deskew receiver100′ having a jitter control circuit function, showing a second embodiment will be explained usingFIG. 8.

Blocks of the same configurations/functions as those shown inFIG. 1are given the same symbols, and the description thereof will therefore be omitted.

The difference in configuration therebetween resides in that the time to be delayed is the clock of the latch11in the first embodiment, whereas a data signal is delayed in the present embodiment. As to the configuration, a signal200outputted from a differential comparator10is inputted to a latch11through a variable delay13′, where it is synchronized. The variable delay13′ is controlled by a delay controller12, which is operated as shown inFIG. 5descriptive of the first embodiment. Therefore, a delay control signal202serves so as to transfer a delay controlled amount to the variable delay13′ in accordance with patterns of input data of the data signal20.

The variable delay13′ generates a delay time corresponding to the delay control signal202received therein. The difference between the first embodiment and the present embodiment resides in that the variable delay13′ allows the signal200to have a delay according to the delay control signal202for the purpose of delaying the signal200in the present embodiment. For example, the delay control signal202generated by the delay controller12is inputted to the variable delay13ofFIG. 1from which a delay time corresponding to the value of the delay control signal202is generated. That is, when the delay control signal202is of a signal corresponding to ΔT1, the variable delay13delays a ΔT1time. Similarly, when the delay control signal202is of a signal corresponding to ΔT2, the variable delay13delays a ΔT2time. The following are processed in like manner. A delaying circuit can be realized by various methods in a manner similar to the first embodiment. This can be configured even by performing switching to the number of stages of delay elements or performing delay control by varying the voltage.

Configuring the deskew receiver100′ having the jitter control circuit function in this way makes it possible to reduce jitter related to dependency of the data of the data signal20as in the same effect as the first embodiment. Even if the cycle of the data dependency is 3 cycles or more, jitter can be reduced owing to their effects. Therefore, a data's timing window can be taken wide and a high-speed interface can be provided.

Further, since an internal clock (φ) can be used as a clock210for the latch11, the deskew receiver can have the same timing window as the latch11upon data transfer of the following stage, and hence the present embodiment can be operated stabler as compared with the first embodiment.

Third Preferred Embodiment

A third embodiment will be explained usingFIG. 9. The present embodiment relates to automatic control on a variable delay time that acts on the transfer of data between two LSIs. A transmission LSI500transmits a data signal (DQ) and a strobe signal (DQS) to a reception LSI501. The data signal (DQ) is transmitted from a driver14lying in the transmission LSI500to a receiver100lying in the reception LSI501through a wire15. The data strobe signal (DQS) is transmitted from a driver14alying in the transmission LSI500to a receiver100alying in the reception LSI501through a wire15a. The data signal (DQ) corresponds to a signal end system using one wire15per bit, whereas the strobe signal (DQS) is defined as a differential signal using two wires15aper bit. Therefore, the fetching or capturing of an input waveform by the receiver100afor the DQS signal is taken at a cross point of the input waveform without using VREF0.

Next, a flow chart for jitter delay automatic control and the like are shown inFIGS. 10aand10b.

A power-on sequence601is effected on the LSIs500and501and thereafter an initialization sequence602is operated. In the present sequence, the reset of a circuit by a reset signal, the input of a clock for DLL control, the setting of respective registers in the LSIs, etc. are carried out. This is based on specs of the respective LSIs.

Dejitter phase control is performed in Step603.

Waveforms corresponding to the jitter phase control Step603are shown inFIG. 10b.

In a sequence604, the reset of a delay time corresponding to initialization for automatic control, and the setting of a parameter i to “1” are performed. Thereafter, a handshake for the start of an automatic control sequence is performed in a sequence605. A request for the start of the automating sequence is sent to the transmission LSI500through a signal line not shown inFIG. 9. After an acknowledge signal indicative of “ready” has been received on the transmission LSI500side, the sequence procedure proceeds to a delay control sequence606.

In the sequence606, the driver14of the transmission LSI500outputs a pulse (i.e., L*HL*)350having one cycle width to its corresponding DQ signal line as shown in the left drawing ofFIG. 10b-1. At this time, the driver14aoutputs a repetitive waveform to its corresponding DQS signal line. The two DQ and DQS signals are synchronized and hence the difference in timing for switching of the DQ signal is the same in any cycle.

Although the reception LSI501receives the DQ signal through the input circuit100and receives the DQS signal through the input circuit100a, respectively, its input waveform351is being blunted as shown on the upper side of the right drawing ofFIG. 10b-1.

In the sequence605, the following is done:

The differences ΔT1rand ΔT1fin phase between the rising and falling edges of the input DQ signal351with respect to the DQS signal are measured. For the sake of simplicity, the output signal of the receiver100is typified by the blunted input waveform351. This measurement is done by incrementing or decrementing the number of stages of variable delay elements undescribed inFIG. 9to thereby compare the phases of two waveforms and repeating the input of a 1 cycle pulse until the result of comparison becomes the same.

For example, the delay time of the variable delay from the rising edge of the DQ signal of the receiver100for the DQ signal is adjusted, and the signal thereof is compared in phase with the rising signal of the receiver100afor the DQS signal to thereby determine a delay time difference ΔTir.

Further, the delay time of the variable delay from the falling edge of the DQ signal of the receiver100is adjusted, and the signal thereof is compared in phase with a rising signal in another cycle of the receiver100afor the DQS signal to thereby determine a delay time difference ΔT1f.

When the phase differences ΔT1rand ΔT1fare determined, a delay time ΔT1to be corrected thereby can be determined by the following equation:

This is because ΔT1rcorresponds to the difference in delay time between the input circuit100for the DQ signal and the input circuit100afor the DQS signal, with respect to (L*H), and the falling ΔT1fof L*HL contains a delay time having data dependency of the transmission line15in terms of the difference.

Several methods are known as a method of measuring a delay time. The delay time measurement is made by being executed in the following manner, for example.

Two delay circuits identical in the minimum delay time are prepared. Then, a time difference ΔT1rbetween a rising signal of the receiver100afor a DQS signal and the output of the receiver100for a DQ signal, and a time difference ΔT1fbetween the rising signal of the receiver100afor the DQS signal and the output of the receiver100for the DQ signal are adjusted so as to be identical in delay time to each other (sequence607).

Assuming that the numbers of stages of delay circuits for ΔT1rand ΔT1fare counted and they are defined as s and t, s−t is delay information about ΔT1to be determined. This information is set to the variable delay13shown inFIG. 1. If the variable delay13corresponds to each of variable delays identical in minimum delay time, then the value thereof per se means a delay time.

Similarly, i is incremented and the sequence procedure returns to the sequence603.

When i=2, the driver14of the transmission LSI500outputs a pulse (i.e., L*HHL*)360having a 2 data cycle width as shown inFIG. 10b-2. A DQS signal having a repetitive waveform is outputted from the driver14a. The two DQ signal360and DQS signal are in sync with each other and the difference in timing for switching of the DQ signal is the same.

In the sequence606, a pulse of 2 cycles is received. In the sequence607, the reception LSI501measures phase differences ΔT2rand ΔT2fbetween the rising edges and falling edges of the DQ and DQS signals. Then, if the difference therebetween is determined, then it corresponds to a delay time ΔT2to be corrected and set to the variable delay13in the sequence607. This loop is repeated four times. Thus, all of ΔT1, ΔT2, ΔT3and ΔT4are determined and set to the variable delay13.

Although the dejitter phase control has been effected on the rise in Step603, the delay time can be automatically determined by using a pulse of opposite polarity in the fall. Even when the falling automatic control is not done, the value in Step603can also be used. This is effective for the case in which the rising edge and falling edge are symmetrical in output impedance at the driver14.

By performing the above measurement in this way, the delay time ΔTiin the variable delay13ofFIG. 1showing the first embodiment can be decided automatically. Similarly, the delay time ΔTiin the variable delay13′ ofFIG. 8showing the second embodiment can be determined automatically.

Fourth Preferred Embodiment

A fourth embodiment will be explained usingFIG. 11. The present embodiment shows a case in which a jitter reduction technique is applied to a memory.

A memory module30is equipped with a plurality of DRAMs32and a register buffer31for control/address signal (C/A). The control/address signal (C/A)35is inputted to the register31and then transmitted to the respective DRAMs32. The register31outputs a clock signal37and a C/A signal38.

A data input circuit100is mounted in each of the DRAMs32. Here, the input circuit100may be a configuration in which a jitter-reducing delay circuit is provided for the clock employed in the first embodiment. Alternatively, the input circuit100may be a configuration in which a jitter-reducing delay circuit is provided for the data signal employed in the second embodiment.

Also the DRAM32performs reading and writing of data from and to a memory controller not shown here, through the data (DQ) signal36.

It is understood that since jitter can be reduced even by the C/A signal38having plural bits, such a configuration is suitable for speeding-up thereof.

Setting the receiver to a dejitter input circuit type is suitable even for speeding up of the data signals36in a manner similar to the C/A signal38.

Fifth Preferred Embodiment

A fifth embodiment will be explained usingFIG. 12.

Reference numeral110indicates a deskew receiver having a jitter control circuit function, according to the present invention. The deskew receiver inputs a data signal20connected to a transmission line and a clock signal (φ)210therein. The data signal20is synchronized with the clock signal210and outputted as an output signal201.

The deskew receiver110comprises differential comparators10and11, a variable voltage source17, a latch11and a controller12.

The data signal20is inputted to the differential comparators10and11and the signals inputted thereto are compared with a reference voltage (VREF0) and a reference voltage (VREF1) respectively. “0” or “1” is outputted as receiver output signals200and209, respectively, according to the magnitude thereof. Here, the reference voltage (VREF1) is supplied from the variable voltage source and determined by a signal outputted from the controller12. In a data cycle region in which the data signal20changes from H to L in which 4 pulses or less are continuous, a selector switch18serves so as to select the output signal209. In a data cycle region in which the data signal changes from L* or H* in which 5 pulses or more are continuous, the selector switch18selects the output signal200. The output signal209is brought to a signal211via the selector switch18and inputted to the latch11. The output signal200of the differential comparator10is latched therein. The amount of control of the reference voltage corresponding to each of patterns of input data of the data signal20is determined by the controller12.

FIG. 13shows an input waveform of the data signal20. The horizontal axis indicates the time and the vertical axis indicates the voltage. The input signal of the data signal20is plotted by superimposing five waveforms301through305on one another.

The waveform301indicates a waveform having L at which an input data pattern prior to a time T0continues, and thereafter H continuous till a time T6. Now, the times T0through T5indicated by dotted lines indicate cycles of the data inputted to the deskew receiver110having the jitter control circuit function. Incidentally, the description of the data pattern of the waveform301as (L*H*) conforms to the method shown in the first embodiment. Similarly, the data patterns of the waveform302and the like can be represented as (L*HL*) or the like subsequently.

InFIG. 13, the latched input signal results in H during a time interval at which the waveform of the data signal20, which rises from L* continuous over 5 pulses, crosses the reference voltage VREF0(1301). When the input waveform falls from the position on the way to the charge of the waveform301, the latched input signal211results in L during the difference between the falling time and the time in which the waveform crosses the reference voltage VREF1(1302). It is understood that the respective waveforms302through305respectively have time differences among times at which they cross the VREF0and VREF1. The time differences are respectively represented as ΔT1through ΔT4(or ΔTi) with respect to the waveforms302through305.

On the falling edge of each of the waveforms302through305, signal amplitude up to the elapse of one cycle from its switching time is substantially identical to amplitude from T0to T1of the waveform301.

In the present embodiment, the differential comparator10makes use of the reference voltage (VREF1) lower than the reference voltage (VREF0) used upon using the voltage comparison of the inputted data signal upon its rise when the data patterns fall, thereby making it possible to expand timing windows of data of the latched input signal211by ΔT1, ΔT2, . . . ΔT4at the falling signals of the data patterns of the waveforms302through305and provide speeding up. Using the reference voltage VREF1higher than the reference voltage VREF0even when the waveform301falls and the waveforms302through305rise to the contrary makes it possible to expand a data window of the signal inputted to the latch11in like manner.

Sixth Preferred Embodiment

A sixth embodiment will be explained usingFIG. 14.

Reference numeral120indicates a deskew receiver having a jitter control circuit function, according to the present invention. The deskew receiver inputs a data signal20connected to a transmission line and a clock signal (φ)210therein. The data signal20is synchronized with the clock signal210and outputted as an output signal201.

The deskew receiver120comprises differential comparators10and11, a variable voltage source17, a latch11, a controller12and a variable delay13.

The data signal20is inputted to the differential comparators10and11and the signals inputted thereto are compared with a reference voltage (VREF0) and a reference voltage (VREF1) respectively. “0” or “1” is outputted as receiver output signals200and209, respectively, according to the magnitude thereof. Here, the reference voltage (VREF1) is supplied from the variable voltage source and determined by a signal outputted from the controller12. In a data cycle region in which the data signal20changes from H to L in which the same pulses are continuous from over 4 to under 4, a selector switch18serves so as to select the output signal209. In a data cycle region in which the data signal changes from L to H in which 5 pulses or more are continuous, the selector switch18selects the output signal200. Next, the latch11is inputted with the output signal209sent through the selector switch18and a signal203outputted from the variable delay13. The output signal200or209of the differential comparator10or11is latched in the latch11. The amount of control of the reference voltage corresponding to each of patterns of input data of the data signal20is supplied by controlling the reference voltage (VREF1) by means of the variable voltage source.

On the other hand, the variable delay13is controlled by the controller12. A delay control signal202serves so as to transfer the amount of delay control to the variable delay13according to each of the patterns of the input data of the data signal20.

The variable delay13generates the delay time corresponding to the received delay control signal202. Further, the difference between the fifth embodiment and the sixth embodiment resides in that as in the case of the method employed in the first embodiment, a clock signal delayed by a predetermined time is inputted to the latch11according to the delay control signal202, and time-base control on the amount of delay is additionally provided.

FIG. 15shows an input waveform of the data signal20. The horizontal axis indicates the time and the vertical axis indicates the voltage. The input signal or input waveform of the data signal20is plotted by superimposing five waveforms301through305on one another.

The description of the waveforms301through305is the same as one made in the fifth embodiment.

InFIG. 15, the time at which the rising waveform crosses the reference voltage VREF0, is read. When the waveform falls from the position on the way to the charge of the waveform301, the time at which the waveform crosses the reference voltage VREF1, is read. The difference between the times is represented as ΔTi. It is understood that the respective waveforms302through305respectively have time differences among times at which they cross the VREF0and VREF1in like manner subsequently. The time differences are respectively represented as ΔT1through ΔT4(or ΔTi) with respect to the waveforms302through305.

Further, in a manner similar to the first embodiment, the present embodiment is provided with the operation of allowing the variable delay13to make fetch timing of the latch11in a T1cycle early by ΔT1with respect to the waveform302in which the input data is of (L*HL*). The remaining waveforms302through305are also similar to the above.

Seventh Preferred Embodiment

A seventh embodiment will be explained usingFIGS. 16,17,18and19. InFIG. 16, reference numeral101indicates a deskew receiver having a jitter control circuit function, according to the present invention. The deskew receiver inputs a data signal20connected to a transmission line and a clock signal (φ)210therein. The data signal20is synchronized with the clock signal210and outputted as an output signal201.

The deskew receiver101comprises a differential comparator10, a variable voltage source17, a latch11, and a reference voltage controller12.

The data signal20is inputted to the differential comparator10and the signal inputted thereto is compared with a reference voltage (VREF). “H” or “L” is outputted as its corresponding receiver output signal200according to the magnitude thereof. Here, the reference voltage (VREF) is supplied from the variable voltage source17and determined from three voltage values VREF+, VREF0and VREF− in accordance with a signal outputted from the reference voltage controller12. Here, VREF+=VDDQ×5/8, VREF0=VDDQ/2, and VREF−=VDDQ×3/8. VDDQ indicates a source voltage value and corresponds to a stable value of an H level voltage of the signal.

Firstly,FIG. 19shows waveforms of the data signal20and an output signal200of the differential comparator10where the deskew receiver is operated without controlling the reference voltage, with respect to a data signal waveform at the time that a “4 cycle type” data cycle time at which the voltage is stable by the signal where the same value of H or L is continuous 4 pulses or more, is equal to time constant τ of the data signal waveform. The horizontal axis indicates the time, and the vertical axis indicates the voltage. The data signal20is drawn by superimposing seven waveforms301through308on one another. The output signals of the comparator10corresponding to those are designated at numerals1301through1308respectively. In this case, the reference voltage is fixed to VREF=VREF0, and a data width1300becomes very narrow in the case of a data pattern (LHL) at T0through T2. The H level of the data signal20at the time T1has almost no allowance for the reference voltage, and the characteristic of the reference voltage resistant to noise is weak.

Now,FIG. 17is a state transition diagram for determining a reference voltage according to the pattern of the output signal201by the reference voltage controller in the “4 cycle type” data signal waveform. A state SO indicates a state in which L is continuous 4 pulse or more and the data signal20is stable. A state S4indicates a state in which H is continuous 4 pulses or more and the data signal20is stable. The state S0is first defined as an initial state. When L is inputted to the reference voltage controller here, the state is not transitioned. When H is inputted to the reference voltage controller, the state makes a transition to S1H. When L is inputted thereto in the state S1H, the state is transitioned to a state S2L, whereas when H is inputted thereto, the state is transitioned to a state S2H. When L is inputted thereto in the state S2H, the state is transitioned to a state S1L, whereas when H is inputted thereto, the state makes a transition to a state S3H. When L is inputted thereto in the state S3H, the state is transitioned to the state S1L, whereas when H is inputted thereto, the state is transitioned to the state S4. When H is inputted thereto in the state S4, no transition is made, whereas when L is inputted thereto, the state is transitioned to the state S1L. When H is inputted thereto in the state S1L, the state makes a transition to the state S2H, whereas when L is inputted thereto, the state is transitioned to a state S2L. When H is inputted thereto in the state S2L, the state is transitioned to the state S1H, whereas when L is inputted thereto, the state is transitioned to a state S3L. When H is inputted thereto in the state S3L, the state is transitioned to the state S1H, whereas when L is inputted thereto, the state is transitioned to the state S0. Then, the reference voltage controller controls the reference voltage according to the respective states as follows: VREF=VREF−in the state S0, VREF=VREF−in the state S1H, VREF=VREF0in the state S2H, VREF=VREF0in the state S3H, VREF=VREF+in the state S4, VREF=VREF+in the state S1L, VREF=VREF0in the state S2L, and VREF=VREF0in the state S3L, respectively. Incidentally, when the reference voltage in each state is set, the reference voltage is determined so as to approach the voltage at which the data signal20passes at the center time of the data cycle.

FIG. 18shows waveforms of the “4 cycle type” data signal20and the output signal200of the differential comparator10corresponding thereto. The horizontal axis indicates the time, and the vertical axis indicates the voltage. The data signal20is drawn by superimposing seven waveforms301through308on one another in a manner similar toFIG. 19. The output signals of the comparator10corresponding to those are designated at numerals1301through1308respectively. The waveform301indicates a waveform having L at which an input data pattern prior to a time T0continues, and thereafter H continuous till a time T4. Now, the times T0through T8indicate cycles of the data inputted to the deskew receiver101having the jitter control circuit function. Incidentally, the description of the data pattern of the waveform301as (L*H*) conforms to the method shown in the first embodiment. Similarly, the data patterns of the waveform302and the like can be represented as (L*HL*) or the like subsequently. The differential comparator refers to VREF−in the case of a data pattern (LHL) at T0through T2. Here, VREF−is near a level at which the data signal20passes at the center time between T0and T1and is close to a level at which the data signal20passes at the center time between T1and T2. Therefore, the time close to a data cycle is obtained as a data width1301. Further, it is understood that if the clock signal210is synchronized with each of T0through T8, then a stable data window in which a setup time and a hold time are well balanced, is obtained. The H level of the data signal20at the time T1has allowance for the reference voltage VREF−and also has the characteristic of the reference voltage resistant to noise.

Eighth Preferred Embodiment

An eighth embodiment will be explained usingFIGS. 20,21,22and23.FIG. 20is a state transition diagram for determining a reference voltage according to a pattern of an output signal201by a reference voltage controller in the case of a “3 cycle type” data signal waveform stable in signal voltage where the same value of H or L is continuous 3 pulses or more.FIG. 21is a diagram showing output waveforms of a data signal20and a differential comparator10where the time constant τ of the “3 cycle type” data signal waveform is equal to 75% of a data cycle time Tcycle.FIG. 22is a state transition diagram for determining a reference voltage according to the pattern of the output signal201by the reference voltage controller in the case of a “2 cycle type” data signal waveform stable in signal voltage where the same value of H or L is continuous 2 pulses or more.FIG. 23is a diagram showing output waveforms of the data signal20and the differential comparator10where the time constant τ of the “2 cycle type” data signal waveform is equal to 50% of a data cycle time Tcycle. It is understood that in either case, a stable data window in which a setup time and a hold time are well balanced, is obtained in a manner similar to the above “4 cycle type”.

Controlling the reference voltage using the history of the data patters in this way makes it possible to obtain a stable data window, i.e., reduce jitter.

While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.