METHOD, APPARATUS, AND SYSTEM FOR IMPROVED CELL DESIGN HAVING UNIDIRECTIONAL METAL LAYOUT ARCHITECTURE

At least one method, apparatus and system disclosed involves circuit layout for comprising a unidirectional metal layout. A first trench silicide (TS) formation is formed in a first active area of a functional cell. A first CA formation if formed above the first TS formation. A first vertical metal formation is formed in a first metal layer from the first active area to a second active area of the functional cell. The first vertical metal formation is formed offset relative to, and in contact with, the CA formation. A second TS formation is formed in a second active area of the functional cell. A second CA formation is formed above the second TS formation. The CA formation is formed offset the first vertical metal formation, operatively coupling the first and second active areas.

BACKGROUND OF THE INVENTION

Field of the Invention

Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods and structures, including unidirectional metal layout, for using improved cell routability for metal lines for manufacturing integrated circuits.

Description of the Related Art

The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.

The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.

Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using semiconductor-manufacturing tools, such as exposure tool or a stepper. As an example, an etch process may be performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum or copper, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another.

In this manner, integrated circuit chips may be fabricated. In some cases, integrated circuit or chips may comprise various devices that work together based upon a hard-coded program. For example, application-specific integrated circuit (ASIC) chips may use a hard-coded program for various operations, e.g., boot up and configuration processes. The program code, in the form of binary data, is hard-coded into the integrated circuit chips.

When designing a layout of various devices with an integrated circuits (e.g., CMOS logic architecture), designers often select pre-designed functional cells comprising various features (e.g., diffusion regions, transistors, metal lines, vias, etc.) and place them strategically to provide an active area of an integrated circuit. One challenge of designing a layout is accommodating ever-increasing density of cell components and still maintain routability for connecting various components of the cells. This is increasingly a challenge as dimensions of these components get smaller, such as for 10 nm or lower integrated circuit designs.

In order to accommodate smaller integrated circuit designs, designers have provided more dense, smaller-track functional cells (e.g., 10-track or lower functional cells). For larger track designs, generally, designers desire to have a unidirectional metal-1 (M1) design where M1 is parallel to the gate (PC) structures, while allocating metal-2 (M2) as power rail. However, with smaller-track designs, in order to complete routing, designers are forced to make M1 bi-directional.

Because of the power rail limit in a cell, there is a desire to make M0/M1 horizontal-directional metal structures in circuits of smaller track dimensions. That is, since the power rail runs horizontal, it is desirable that M1 also runs horizontal. However, in order to make M1 unidirectional for smaller-designs (e.g., 10-track or smaller), designers are forced to use other resources, such as CA/TS pass-through structures.FIG. 1illustrates a stylized depiction of a typical functional cell having a local interconnect formation/trench silicide, CA/TS pass-through structure.

FIG. 1illustrates a stylized depiction of a cell100that comprises a plurality of PC (gate) formations110. An intermediate, local interconnect formation CB metal formation150may be used to connect up some gates310to formations in other/upper metal layer. The CB formation150is slightly offset on the gate formation110. The cell100includes a 1stactive region120and a 2ndactive region130. The cell100may also comprise local interconnect formations, i.e., a 1stCA formation360and a 2ndCA formation365. The 1stCA formation360may be connected to the active region120using a via361, and the 2ndCA formation365may be connected to the active region330using a via366. The 1stCA formation360from the NMOS region may be connected to the 2ndCA formation365by using a middle-of-line (MOL) structure, i.e., a CA/TS pass-through140.

Despite the offset of the CB formation150away from the CA/TS pass-through140, the CB to CA/TS pass-through is sufficiently close such that it could cause shorts between the CB formation150and the CA/TS pass-through140. Further, the diffusion area between the CB to CA/TS pass-through can become too small.

The CA/TS pass-through140can be problematic during processing of a semiconductor device. For example, the usage of a CA/TS pass-through140causes a reduction of useful active regions in the cell. The active regions (i.e., the 1stand 2ndactive regions120,130) may be pushed to the sides and/or may be limited in the size of the active regions in order to allow for the CA/TS pass-through140connections. As the contacted poly pitch (CPP) of cells decrease, the space issues caused by the CA/TS pass-through140are exacerbated.

FIGS. 2 and 3describe the spacing issues caused by use of CA/TS pass-through140in cell with decreased CPPs.FIGS. 2 and 3illustrate stylized depictions of cross sectional views of the CA/TS pass-through ofFIG. 1(see cut-line150).FIG. 2illustrates a stylized depiction of a cross-sectional view of the cell100ofFIG. 1with a CPP of 90 nm. Generally, the CB formation150the gate formations110to metal layers, while the CA/TS pass-through140connects the source/drain associated with the gates110to metal layers. As shown inFIG. 2, the CB formation150is offset from the gate (PC) structure110by about 19 nm. The center of the gate structure110is about 45 nm from the CA/TS pass-through140center. The center of the CB formation150is about 64 nm from the center of the CA/TS pass-through140.

In contrast to the example ofFIG. 2, where the CPP is 90 nm, as the CPP for cells decrease, problems with the state of the art designs increase.FIG. 3illustrates a stylized depiction of a cross-sectional view of the cell100ofFIG. 1with a CPP of 64 nm. In this case, the CB formation150is offset from the gate (PC) structure110by about 8 nm. The center of the gate structure110is only about 32 nm from the CA/TS pass-through140center. The center of the CB formation150is only about 40 nm from the center of the CA/TS pass-through140. This causes the CB to CA/TS pass-through to be sufficiently small to cause problems. As noted, even with the offset of the CB formation150away from the CA/TS pass-through140, the CB to CA/TS pass-through is close enough to cause shorts between the CB formation150and the CA/TS pass-through140as a result of slight process variations.

Therefore, as CPP of cells become smaller and denser, the likelihood of process errors increases. Accordingly, as described above, using CA/TS pass-through140force designers to shrink active areas and/or move active areas around in an undesirable fashion. This can cause device performance problems. The usage of CA/TS pass-through causes difficulties in shrinking integrated circuit devices, in improving performance, and in maintaining sufficient active areas when decreasing track sizes.

Designers have attempted at least three basic design approaches to avoid using CA/TS pass-through140, as shown inFIGS. 4-6.FIG. 4illustrates a stylized depiction of a typical MO-less architecture.FIG. 4illustrates a cell400that comprises a plurality of gates structures410. A CB formation450may be used to connect gates410to formations in other/upper metal layer (i.e., M1 layer). The cell400includes a 1stactive region420(e.g., NMOS region) and a 2ndactive region430(e.g., PMOS region). The cell400comprises a 1stmetal formation492formed over the 1stactive region420. The cell400also comprises a 2ndmetal formation494formed over the 2ndactive region430. The 1stand 2ndmetal formations492,494are formed in a horizontal configuration, and may be used as power rails. A 3rdmetal formation496is formed in a vertical configuration. The CB formation450connects a gate410to the 3rdM1 formation496.

The cell400may also comprise a 1stCA formation460and a 2ndCA formation465. The 1stCA formation460may be formed in the 1stactive region420, and the 2ndCA formation465may be formed in the 2ndactive region430. The 1stactive region420may be connected to the 2ndactive region430by using a “C” shaped M1 structure490. The M1 structure490is connected to the 1stactive region420using a via461, while the M1 structure490is also connected to the 2ndactive region430using a via466.

The C-shaped M1 arrangement of the cell400causes “wrong-way” M1 features wherein M1 features have to be used in undesirable directions for routing, thereby causing the M1 metal layer to be bi-directional. This is problematic in performing side-wall patterning since this process requires unidirectional metal layer structures. Wrong-way power rail architecture requires triple patterning M1 LELELE. This process can cause printability and manufacturing problems.

The C-shaped structures may cause various other process issues. For example, usage of the C-shaped structures requires more space, and thus, causes the cell400to become taller. This causes the integrated circuit formed using the cell400to be larger, and increases power consumption. Further, formation of the C-shaped structures can cause lateral connection problems. Also, more silicon would be required at the corners of the C-shaped structures, which could cause process errors. Further, the C-shaped structures cause various routing congestion problems.

Designers also have used other approaches to avoid using CA/TS pass-through140, as shown inFIG. 5.FIG. 5illustrates a stylized depiction of a typical M0 architecture.FIG. 5shows a cell500that comprises a plurality of gates structures510. A CB formation550may be used to connect gate510to formations in other/upper metal layer (i.e., M0, M1 layers). The cell500includes a 1stactive region520(e.g., NMOS region) and a 2ndactive region530(e.g., PMOS region). The cell500comprises a 1stM1 formation592formed over the 1stactive region520. The cell500also comprises a 2ndM1 formation594formed over the 2ndactive region530. The 1stand 2ndM1 features592,594are formed in a horizontal manner. The 1stand 2ndmetal formations592,594are formed in a horizontal configuration, and may be used as power rails. A 3rdmetal formation596is formed in a vertical configuration. The CB formation550connects a gate510to the 3rdM1 formation596. Further, a plurality of TS structures542are formed in the active areas.

The cell500comprises a 1stM0 structure583in the 1staction region520, and a 2ndM0 structure585in the 2ndactive region530. The 1stand 2ndM0 structures583,585are formed in a horizontal configuration and is generally connected to power/ground nodes, using 1stand 2ndvias567,568, respectively.

The cell500may also comprise local interconnect formations, i.e., a 1stCA formation560and a 2ndCA formation565. The 1stCA formation560may be connected to 3rdM0 structure587, and the 2ndCA formation565may be connected to the 4thM0 structure589. The 3rdand 4thM0 structures587,589are also formed in a horizontal configuration.

The 1stactive region520may be connected to the 2ndactive region530by using M1 structure570and 3rdand 4thvias591,592, respectively. As shown inFIG. 5, the M0 features are horizontal, and the M1 features are vertical, except for the power rail M1 formations, which are horizontal. Again, this also causes wrong-way M1 features, wherein M1 features have to be used in undesirable directions for routing, thereby causing the M1 metal layer to be bi-directional. Again, this is problematic in performing side-wall patterning, as described above.

FIG. 6illustrates a stylized depiction of a typical CB-M0 handshake architecture.FIG. 6shows a cell600that comprises a plurality of gates structures610. A local interconnect formation, i.e., CB formation550, is used for a CD-M0 horizontal handshake formation. The cell600includes a 1stactive region620(e.g., NMOS region) and a 2ndactive region630(e.g., PMOS region). The cell600comprises a 1stM1 formation692formed over the 1stactive region620. The cell600also comprises a 2ndM1 formation694formed over the 2ndactive region630. The 1stand 2ndM1 features are formed in a horizontal manner.

The cell600comprises a 1stM0 structure683in the 1staction region620and a 2ndM0 structure685in the 2ndactive region530. The M0 structures683,685are formed in a horizontal configuration and is generally connected to power/ground nodes, using 1stand 2ndvias667,668, respectively. The cell600comprises a 3rdM0 structure587that is coupled to a CB structure650, which is electrically coupled to the 3rdM0 structure683. The 3rdM0 structure687is electrically coupled to the to the 3rdM1 structure687using a 5thvia687, wherein the 3rdM0687, the CB structure650, and the 5thvia693form a CB-M0 horizontal handshake configuration. The 3rdM0 structure687is formed in a horizontal configuration.

The 1stactive region520may be connected to the 2ndactive region530by using the 4thM1 structure690and 3rdand 4thvias691,692, respectively. As shown inFIG. 6, the M0 features are formed in a horizontal configuration, and the M1 features are vertical, except for the horizontal power rail M1 formations. The configuration of the cell600causes wrong-way M1 features, wherein M1 features have to be used in undesirable directions for routing, thereby causing the M1 metal layer to be bi-directional. As described above, issues relating to bi-directional metal formations can be problematic in performing side-wall patterning. Accordingly, as described above, there are various inefficiencies, errors, and other problems associated with the state-of-art.

The present disclosure may address and/or at least reduce one or more of the problems identified above.

SUMMARY OF THE INVENTION

Generally, the present disclosure is directed to various methods, apparatus and system for providing a circuit layout comprising unidirectional metal layout. A first trench silicide (TS) formation is formed in a first active area of a functional cell. A first CA formation if formed above the first TS formation. A first vertical metal formation is formed in a first metal layer from the first active area to a second active area of the functional cell. The first vertical metal formation is formed offset relative to, and in contact with, the CA formation. A second TS formation is formed in a second active area of the functional cell. A second CA formation is formed above the second TS formation. The CA formation is formed offset the first vertical metal formation, operatively coupling the first and second active areas.

DETAILED DESCRIPTION

Embodiments herein provide for using middle-of-line (MOL) structures, such as local interconnect formations CA, CB, and trench silicide (TS) formations to provide connections/routing to enable use of unidirectional metal formations. Embodiments herein provide for a cell for an integrated circuit that comprises a CA-M0 and CB-M0 offset side-touch hand-shake design. Embodiments herein provide for source/drain connections that comprise unidirectional metal connections. Embodiments herein also provide for an increased amount of edge placement tolerance as compared to CA/TS pass-through designs.

Further, embodiments herein provide for a middle of line (MOL) architecture that substantially reduces or eliminates “wrong way” power rails, i.e., substantially reducing or eliminating metal structures on a metal layer that run in a different direction as compared to power rail structures of that metal layer. Embodiments herein provide for unidirectional M1 (e.g., horizontal unidirectional) SADP compatible designs. Using embodiments herein, improved scalability may be achieved as compared to wrong-way M1 architecture. Designs provided by embodiments herein provide for all MOL layers of an integrated circuit to be ultra-regular and compatible with LELE and SADP designs.

Turning now toFIG. 7, a stylized depiction of a functional cell having a CA-M0 and CB-M0 offset side-touch handshake, in accordance with embodiments herein is illustrated.FIG. 7shows a cell700that comprises a plurality of PC (gate) formations710a,710b,710c. A local interconnect CB formation750may be used to connect the gate710bto formations in other/upper metal layers. The CB formation750is offset relative to the gate formation710b. Further, a 1stM0 metal formation770ais formed in a vertical configuration. The 1stM0 formation770ais offset relative to the CB formation750and the gate710b.

The cell700includes a 1stactive region720(e.g., NMOS region) and a 2ndactive region730(e.g., PMOS region). Trench silicide (TS) formations780may be formed in the 1stand 2ndactive areas720,730. A 2ndM0 formation770bis formed in a vertical configuration. The 2ndM0 formation770bis formed in an offset fashion relative to the gate710c. The cell700may also comprise local interconnect formations, a 1stCA formation760in the 1stactive region720, and a 2ndCA formation765in the 2ndactive region. The 1stand 2ndCA formations760,765are formed offset relative to the 2ndM0 formation770band aligned on a TS formation780, as shown. In this manner, the 1stand 2ndactive regions720,730may be operatively coupled using vertical M0 features.

Turning now toFIG. 8, a stylized depiction of a cross-sectional view of a first portion of the cell700ofFIG. 7, in accordance with embodiment herein, is illustrated. Referring simultaneously toFIGS. 7 and 8, a cross-sectional view of the cell700at the cut line781(FIG. 7) is shown.

As shown inFIG. 8, the 2ndCA formation765is formed offset to the 2ndM0 formation770b. The 2ndCA765formation is formed above the TS formation780, within the 2ndactive area730. The centers of the 1stM0 formation770aand the 2ndM0 formation770bare separated by a single track spacing, e.g., 64 nm. The CA-M0 handshake illustrated inFIG. 8may be used to replace a TS pass-through to operatively couple the 1stand 2ndactive areas720,730.

Turning now toFIG. 9, a stylized depiction of a cross-sectional view of a second portion of the cell700ofFIG. 7, in accordance with embodiment herein, is illustrated. Referring simultaneously toFIGS. 7 and 9, a cross-sectional view of the cell700at the cut line782(FIG. 7) is shown.

As shown inFIG. 9, the CB formation750is formed offset relative to the gate structure710b, leaving a CB-PC overlap. The 1stM0 formation770ais formed offset relative to the CB750. The 2ndM0 formation770bis formed offset to the gate formation710c. The centers of the 1stM0 formation770aand the 2ndM0 formation770bare separated by a single track spacing, e.g., 64 nm. The CB-M0 handshake illustrated inFIG. 9provides for enabling gate pick-up, using the CB formation750.

The offset nature of the CA-M0 and CB-M0 handshaking exemplified inFIGS. 7-10, provide for forming all of the M0 formations in a vertical configuration. Therefore, all M1 metal formations may then be formed in horizontal configurations, as described inFIG. 10and accompanying description below. Since M0 formations are on the same level as CB formations, they can be formed at the same height, thereby increasing process tolerances. Since M0 formations are shifted, and since there is no pass-through, an increase in the tolerance margin is realized because of the position of CB and the vertical routing provided by this design. The problems associated with the CA/TS pass-through design are substantially decreased or eliminated.

Turning now toFIG. 10, a stylized depiction of a cell comprising horizontal M1 and vertical M0 formations, and having CA-M0 and CB-M0 offset side-touch handshakes, in accordance with embodiments herein, is illustrated.FIG. 10shows a cell1000that comprises a plurality of PC (gate) formations1010a,1010b,1010c. A CB formation1050may be used to connect the gate1010bto formations in other/upper metal layers. The CB formation1050is offset relative to the gate formation1010b. Further, a 1stM0 metal formation1070ais formed in a vertical configuration. The 1stM0 formation1070ais offset relative to the CB formation1050and the gate1010b. Vias1085may be used to operatively couple the metal formations (M1 and M0 formations) to MOL features, such as CA1060,1065and CB1050features.

The cell1000includes a 1stactive region1020(e.g., NMOS region) and a 2ndactive region1030(e.g., PMOS region). TS formations1080may be formed in the 1stand 2ndactive areas1020,1030. Further, a 1stM1 horizontal power rail1015ais formed in the 1stactive area1020. A 2ndM1 horizontal power rail1015bis formed in the 2ndactive area1030. Also, a plurality of M1 formations1040in a horizontal configuration may be formed in the cell1000. Therefore, all of the M1 formations, including the M1 power rails, are formed in a unidirectional, horizontal configuration.

A plurality of additional M0 formations may be formed in a unidirectional, vertical configuration. For example, a 2ndM0 formation1070bis formed in a vertical configuration. The 2ndM0 formation1070bis formed in an offset manner (side-touch) relative to the gate1010c. The cell1000may also comprise a 1stCA formation1060in the 1stactive region1020, and a 2ndCA formation1065in the 2ndactive region1030. The 1stand 2ndCA formations1060,1065are formed offset (side-touch) to the 2ndM0 formation1070band to a TS formation1080. In this manner, the 1stand 2ndactive regions1020,1030may be operatively coupled using vertical M0 features.

Using the vertical, unidirectional M0 formations, along with horizontal, unidirectional M1 formations described above, various connections (e.g., source/drain connections) may be made in an integrated circuit without bending metal formations. This may provide increased edge placement tolerance, which provides routing and space efficiencies. Using the CA-M0 and CB-M0 offset side-touch handshake designs described herein, MOL architecture that substantially eliminates wrong-way power rails, may be achieved. Further, designs provided by embodiments herein provide for increased scalability and more efficient self-aligned double patterning and lithography-etch-lithography-etch (LELE) processing.

Using the CA-M0/CB-M0 offset side-touch handshake provided by embodiments herein, more complex functional cells may be provided For example, using components such as the components described inFIG. 10, complex cells such as an AND cell, an OR cell, a NAND cell, a NOR cell, an XOR cell, an inverter cell, an AND-OR-INVERT (AOI) cell, (e.g., AOI22×1), a memory portion cell, and/or a cell that performs another circuit function, etc. may be formed.

Turning now toFIG. 11, a stylized depiction of a NAND function cell, in accordance with embodiments herein, is illustrated.FIG. 11shows a NAND function cell1100that comprises a plurality of PC (gate) formations1011. A plurality of CB formations1150may be used to connect several gates1110to formations in other/upper metal layers. The CB formations1150are offset from the gate formations1110. Further, a plurality of M0 metal formations1170are formed in vertical configurations. The M0 formations1170are offset relative to the CB formations1150and the gates1110.

The cell1100includes a 1stactive region1120(e.g., NMOS region) and a 2ndactive region1130(e.g., PMOS region). TS formations1080may be formed in the 1stand 2ndactive areas1120,1130. Further, a 1stM1 horizontal power rail1115ais formed in the 1stactive area1120. A 2ndM1 horizontal power rail1115bis formed in the 2ndactive area1130. Further a plurality of M1 formations1140in horizontal configurations are formed in the cell1100. Therefore, all of the M1 formations, including the M1 power rails, are formed in a unidirectional, horizontal configuration. A plurality of vias1106may be used to couple various formations to metal layer, e.g., M1 formations1140, to MOL features (CB, CA, TS features).

The cell1100may also comprise a CA formation1160in the 1stactive region1120. The 1stCA formation1160is formed offset to a M0 formation1170and to a TS formation1180. In this manner, the 1stand 2ndactive regions1020,1030may be operatively coupled using vertical M0 features. The arrangement of the formations in the cell1100provides for a NAND gate. Similar formations, with modifications such increased number of gates1110, more elongated CB formations1150, etc., may be implemented to form other types of functional cells, such as AND-OR-Invert circuits, etc. Using the vertical, unidirectional M0 formations, along with horizontal, unidirectional M1 formations, and the CA-M0/CB-M0 handshakes described above, various efficient cell designs that are SADP and LELE process friendly may be formed.

Those skilled in the art would appreciate that even though some embodiments herein are described in terms of a cell, similar concepts would apply to embodiments where circuits described herein are formed on an integrated circuit without using standard cells.

Turning now toFIG. 12, a stylized depiction of a system for fabricating a device comprising unidirectional metal features, in accordance with some embodiments herein, is illustrated. The semiconductor device processing system1210may comprise various processing stations, such as etch process stations, photolithography process stations, CMP process stations, etc. One or more of the processing steps performed by the processing system1210may be controlled by the processing controller1220. The processing controller1220may be a workstation computer, a desktop computer, a laptop computer, a tablet computer, or any other type of computing device comprising one or more software products that are capable of controlling processes, receiving process feedback, receiving test results data, performing learning cycle adjustments, performing process adjustments, etc.

The semiconductor device processing system1210may produce integrated circuits on a medium, such as silicon wafers. The production of integrated circuits by the device processing system1210may be based upon the circuit designs provided by the integrated circuits design unit1240. The processing system1210may provide processed integrated circuits/devices1215on a transport mechanism1250, such as a conveyor system. In some embodiments, the conveyor system may be sophisticated clean room transport systems that are capable of transporting semiconductor wafers. In one embodiment, the semiconductor device processing system1210may comprise a plurality of processing steps, e.g., the 1stprocess step, the 2ndprocess set, etc., as described above.

In some embodiments, the items labeled “1215” may represent individual wafers, and in other embodiments, the items1215may represent a group of semiconductor wafers, e.g., a “lot” of semiconductor wafers. The integrated circuit or device1215may be a transistor, a capacitor, a resistor, a memory cell, a processor, and/or the like. In one embodiment, the device1215is a transistor and the dielectric layer is a gate insulation layer for the transistor.

The integrated circuit design unit1240of the system1200is capable of providing a circuit design that may be manufactured by the semiconductor processing system1210. The design unit1240may receive data relating to the functional cells to utilize, as well as the design specifications for the integrated circuits to be designed. In one embodiment, the integrated circuit design unit1240may provide cell designs that comprise horizontal M1 unidirectional formation, vertical M0 unidirectional formations, CA-M0 and CB-M0 offset, side-touch handshake formations.

In other embodiments, the integrated circuit design unit1240may perform an automated determination of the shifts, automatically select a substitute or child, and automatically incorporate the substitute cell into a design. For example, once a designer or a user of the integrated circuit design unit1240generates a design using a graphical user interface to communicate with the integrated circuit design unit1240, the unit1240may perform automated modification of the design using substitute cells. In other embodiments, the integrated circuit design unit1240may be capable of automatically generating one or more cells that comprise horizontal M1 unidirectional formation, vertical M0 unidirectional formations, CA-M0 and CB-M0 offset, side-touch handshake formations, or retrieve one or more such cells from a library.

The system1200may be capable of performing analysis and manufacturing of various products involving various technologies. For example, the system1200may use design and production data for manufacturing devices of CMOS technology, Flash technology, BiCMOS technology, power devices, memory devices (e.g., DRAM devices), NAND memory devices, and/or various other semiconductor technologies.

The methods described above may be governed by instructions that are stored in a non-transitory computer readable storage medium and that are executed by, e.g., a processor in a computing device. Each of the operations described herein may correspond to instructions stored in a non-transitory computer memory or computer readable storage medium. In various embodiments, the non-transitory computer readable storage medium includes a magnetic or optical disk storage device, solid state storage devices such as flash memory, or other non-volatile memory device or devices. The computer readable instructions stored on the non-transitory computer readable storage medium may be in source code, assembly language code, object code, or other instruction format that is interpreted and/or executable by one or more processors.