Source driver and the data switching circuit thereof

A data switching circuit is provided, which reduces power consumption of the source drivers when used together with a dot inversion driving method. The circuit comprises a control unit and a switching unit. Wherein, the control unit provides a switching signal. The switching unit has 2N input terminals and 2N output terminals and receives the switching signal. Assume that N is a positive integer and 1≦i≦N. When the switching signal is in a first state, the switching unit connects the (2i−1)th input terminal and the (2i−1)th output terminal, and connects the 2ith input terminal and the 2ith output terminal. When the switching signal is in a second state, the switching unit connects the 2ith input terminal and the (2i−1)th output terminal, and connects the (2i−1)th input terminal and the 2ith output terminal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 94123503, filed on Jul. 12, 2005. All disclosure of the Taiwan application is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a source driver and a data switching circuit thereof, and more particularly, to a source driver using a dot inversion driving method and a data switching circuit thereof.

2. Description of the Related Art

The source driver is a key component in the Thin Film Transistor Liquid Crystal Display (TFT LCD) for converting a digital data signal required for displaying image into an analog signal, and providing the analog signal to each sub-pixel (also known as a dot) of the TFT LCD.

FIG. 1is a block diagram illustrating the major structures of a conventional source driver100. Referring toFIG. 1, the source driver100receives a data signal110and outputs the analog signals from its N output channels Y1˜YN. The source driver100includes a shift register101, a line latch102, a level shifter103, a digital-to-analog converter (DAC)104, and an output buffer105. In general, the source driver is a conventional art and its structures and functions are apparent to one of the ordinary skill in the art. The process is briefly described below. First, a data signal110is dispatched by the shift register101and output to output channels Y1˜YN. Then, the output from the output channels Y1˜YNare temporarily stored in the line latch102and then amplified by the level shifter103. Finally, the DAC104converts the amplified data signals into analog signals, which are then outputted by the output buffer105.

Since the TFT LCD uses liquid crystal for controlling the display, the TFT LCD must be driven by an alternating current (AC) to avoid the liquid crystal material from being polarized. Accordingly, a variety of inversion driving methods, such as line inversion, column inversion, and dot inversion are developed. Wherein, the dot inversion driving method is shown inFIG. 2.FIG. 2schematically shows the driving polarity of the sub-pixel in TFT LCD in a frame T and the next frame T+1, where “+” represents a positive driving polarity, and “−” represents a negative driving polarity. As shown inFIG. 2, the so-called dot inversion means that both neighboring sub-pixels in the same frame have opposite driving polarities in their horizontal and vertical directions, and the driving polarity of the same sub-pixel will be inversed as it goes to the next frame.

Although the dot inversion driving method has many advantages, its major disadvantage is the consumption of excessive power. Referring toFIG. 3, the source driver301inFIG. 3outputs the analog signals to the sub-pixels SP0˜SP3located on the same scan line in a pixel array303through the output buffer302and the data lines DL0˜DL3. The largerscreen TFT LCD panel in current market adopts the direct current (DC) common voltage Vcom design, and having a positive polarity voltage and a negative polarity voltage. Wherein, the positive polarity voltage is higher than the common voltage Vcom, and the negative polarity voltage is lower than the common voltage Vcom. For example, the sequence of the voltage polarity output from the data lines DL0and DL2is positive, negative, and positive; and the sequence of the voltage polarity output from the data lines DL1and DL3is negative, positive, and negative. Each time as it enters into the next scan line or the next frame, the polarity of the voltage on the data lines DL0˜DL3must be inversed. Therefore, the source driver310should provide a swing voltage Vswing that is twice of the common voltage Vcom. The greater the swing voltage Vswing is, the greater the power is consumed. Along with the increasing of panel size and the resolution, a higher voltage is required to drive the wide view angle technology such as the in-plane switching (IPS) and the multi-domain vertical alignment (MVA). As a result, the problem is made more serious.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a data switching circuit, which reduces the swing voltage output from a source driver and further reduces the power consumption when used together with a dot inversion driving method.

Another object of the present invention is to provide a source driver, which is used together with a dot inversion driving method to have the output channel that only outputs a positive polarity voltage or a negative polarity voltage, such that the power consumption is reduced.

To achieve the objects mentioned above and others, the present invention provides a data switching circuit, which includes a control unit and a switching unit. In which, the control unit provides a switching signal. The switching signal may be either in a first state or in a second state, and the state of the switching signal is changed every time when the frame and the scan line in the TFT LCD are started. The switching unit has 2N input terminals and 2N output terminals for receiving the switching signal. Assume that N is a positive integer and 1≦i≦N. When the switching signal is in a first state, the switching unit connects the (2i−1)thinput terminal and the (2i−1)thoutput terminal, and connects the 2ithinput terminal and the 2ithoutput terminal. When the switching signal is in a second state, the switching unit connects the 2ithinput terminal and the (2i−1)thoutput terminal, and connects the (2i−1)thinput terminal and the 2ithoutput terminal.

In the aforementioned data switching circuit according to an embodiment of the present invention, the input terminal of the switching unit is electrically coupled to the line latch of the source driver, and the output terminal of the switching unit is electrically coupled to the level shifter of the same source driver.

In accordance with another aspect, the present invention further provides a source driver, which comprises a line latch, a control unit, a switching unit, and a DAC. In which, the control unit provides a switching signal. The switching signal may be either in a first state or in a second state, and the state of the switching signal is changed every time when the frame and the scan line in the TFT LCD are started. The switching unit has 2N input terminals and 2N output terminals. The input terminal mentioned above is electrically coupled to the line latch. Assume that N is a positive integer and 1≦i≦N. When the switching signal is in a first state, the switching unit connects the (2i−1)thinput terminal and the (2i−1)thoutput terminal, and connects the 2ithinput terminal and the 2ithoutput terminal. When the switching signal is in a second state, the switching unit connects the 2ithinput terminal and the (2i−1)thoutput terminal, and connects the (2i−1)thinput terminal and the 2ithoutput terminal. In addition, the DAC is electrically coupled to the output terminal of the switching unit.

In accordance with a preferred embodiment of the present invention, a special designed data switching circuit is used to switch the data signal in pairs between the output channels of the source driver, and a special designed pixel array is used to transmit the switched data signal to the proper sub-pixel. In addition, if the dot inversion driving method is used, a positive polarity voltage or a negative polarity voltage is continuously outputted from the same output channel during the same frame, such that the switching between the positive polarity and the negative polarity is eliminated. Accordingly, the swing voltage output from the source driver is reduced, and the power consumption is further reduced.

DESCRIPTION OF EMBODIMENTS

As described above, a special designed data switching circuit is used together with a special designed pixel array in the present invention.FIG. 4schematically illustrates a portion of the pixel array400used in an embodiment of the present invention. The aforementioned portion includes the data lines DL0˜DL1, the scan lines SL0˜SL3, and 8 sub-pixels. In which, the sub pixel SP0,0is electrically coupled to the data line DL0and the scan line SL0, the sub pixel SP1,0is electrically coupled to the data line DL1and the scan line SL0, the sub pixel SP0,1is electrically coupled to the data line DL1and the scan line SL1, the sub pixel SP1,1is electrically coupled to the data line DL0and the scan line SL1, and other sub pixels are extended along with the horizontal and vertical directions, following the same rules. In other words, if both x and y are even numbered, the sub pixel SPx,yis electrically coupled to the data line DL(x) and the scan line SL(y), the sub pixel SPx+1,yis electrically coupled to the data line DL(x+1) and the scan line SL(y), the sub pixel SPx,y+1is electrically coupled to the data line DL(x+1) and the scan line SL(y+1), and the sub pixel SPx+1,y+1is electrically coupled to the data line DL(x) and the scan line SL(y+1).

FIG. 5is a block diagram illustrating the major structures of a source driver500, according to an embodiment of the present invention. The source driver500includes a shift register501receiving a data signal510, a line latch502electrically coupled to the shift register501, a control unit504generating a switching signal CHANGE, a switching unit503receiving the switching signal CHANGE, a level shifter505electrically coupled to the output terminal of the switching unit503, a DAC506electrically coupled to the level shifter505, and an output buffer507electrically coupled to the DAC506. In addition, the data switching circuit of the present embodiment includes the switching unit503and the control unit504. Unless described specifically, the rest of the components all have the same functions as the components with the same names inFIG. 1.

In the present embodiment, the control unit504receives a frame start signal FS and a scan line start signal HS, and generates a switching signal CHANGE according to these two signals. As show inFIG. 6, the frame start signal FS is synchronized with each frame start of the TFT LCD, and the scan line start signal HS is synchronized with each scan line start. Each time when the frame and the scan line are started, the switching signal CHANGE is to change its state for adapting with the change of the sub pixel driving polarity. A couple of the existing signals in the TFT LCD may be utilized by the control unit504. For example, the frame start signal FS may be from the vertical synchronization signal or from the start pulse signal that is provided to the gate driver, and the scan line start signal HS may be from the horizontal synchronization signal or from the latch data signal that is provided to the source driver.

In the present embodiment, there are 2N data lines in the pixel array400, and the gray scale resolution for each sub pixel is n bits, in which both N and n are positive integers. Therefore, the source driver500has 2N output channels Y1˜Y2N, and the switching unit503also has 2N input signals A1˜A2Nand 2N output signals B1˜B2N. Of course, the input signals A1˜A2Nand the output signals B1˜B2Nare the n-bit digital signals. The switching unit503changes the connection relationship between the output signals B1˜B2Nand the input signals A1˜A2Naccording to the state of the switching signal CHANGE, and its details are as shown inFIG. 7.

FIG. 7schematically illustrating a signal timing diagram of the switching unit503. As shown inFIG. 7, the switching signal CHANGE has two states, i.e. the logic low level and the logic high level. If i is a positive integer and 1≦i≦N, the switching signal CHANGE is in the logic low level; meanwhile, the switching unit503outputs A2i−1as B2i−1and outputs A2ias B2i. On the other hand, when the switching signal CHANGE is in the logic high level, the switching unit503outputs A2i−1as B2iand outputs A2ias B2i−1. This operation is the so-called switching in pairs.

Although the input terminal of the switching unit503is electrically coupled to the line latch502, the output terminal is electrically coupled to the level shifter505inFIG. 5. Alternatively, the input terminal of the switching unit503may be electrically coupled to the level shifter505and the output terminal may be electrically coupled to the DAC506. Both connections mentioned above would provide the same function.

FIG. 8is a circuit diagram of the switching unit503. Referring toFIG. 8, the switching unit503of the present embodiment has 2N input terminals that respectively receive the input signals A1˜A2Nand 2N output terminals that respectively provide the output signals B1˜B2N. The switching unit503further comprises 2N inverters I1˜I2Nand 4N switching modules SW1˜SW4N. In which, all of the inverters I1˜I2Nreceive the switching signal CHANGE and output the inverse switching signal. If i is a positive integer and 1≦i≦N, the switching modules SW1˜SW4Nconnect and operate as the method described below.

The operating terminal G of the switching module SW4i−3is electrically coupled to the switching signal CHANGE for connecting the (2i−1)thinput terminal to the (2i−1)thoutput terminal of the switching unit503when the switching signal CHANGE is in the logic low level, and for disconnecting the (2i−1)thinput terminal from the (2i−1)thoutput terminal of the switching unit503when the switching signal CHANGE is in the logic high level.

The operating terminal G of the switching module SW4i−2is electrically coupled to the inverse switching signal output by the inverter I2i−1for connecting the 2ithinput terminal to the (2i−1)thoutput terminal of the switching unit503when the inverse switching signal is in the logic low level, that is the switching signal CHANGE is in the logic high level, and for disconnecting the 2ithinput terminal from the (2i−1)thoutput terminal of the switching unit503when the inverse switching signal is in the logic high level, that is the switching signal CHANGE is in the logic low level.

The operating terminal G of the switching module SW4i−1is electrically coupled to the inverse switching signal output by the inverter I2ifor connecting the (2i−1)thinput terminal to the 2ithoutput terminal of the switching unit503when the inverse switching signal is in the logic low level, that is the switching signal CHANGE is in the logic high level, and for disconnecting the (2i−1)thinput terminal from the 2ithoutput terminal of the switching unit503when the inverse switching signal is in the logic high level, that is the switching signal CHANGE is in the logic low level.

Finally, the operating terminal G of the switching module SW4iis electrically coupled to the switching signal CHANGE for connecting the 2ithinput terminal to the 2ithoutput terminal of the switching unit503when the switching signal CHANGE is in the logic low level, and for disconnecting the 2ithinput terminal from the 2ithoutput terminal of the switching unit503when the switching signal CHANGE is in the logic high level.

In reference toFIG. 8, the switching unit503is definitely able to perform the function of switching in pairs as described inFIG. 7. It is to be noted that although the switching modules SW1˜SW4NofFIG. 8are turned on when the input of the operating terminal G is in the logic low level, and turned off when the input of the operating terminal G is in the logic high level, the present invention is not necessarily limited by it. In other embodiments, the operation mentioned above may be totally conversed. In other words, the switching modules SW1˜SW4NofFIG. 8may be turned on when the input of the operating terminal G is in the logic high level, and turned off when the input of the operating terminal G is in the logic low level. Moreover, the circuit of the switching unit503shown inFIG. 8is only one of the embodiments in the present invention, other circuits capable of achieving the function of switching in pairs ofFIG. 7also applicable in the present invention and also regarded as within the scope of the present invention.

In the present embodiment, the structures of the switching modules SW1˜SW4Nare all the same. Using the switching module SW1as an example,FIG. 9is a circuit diagram of the switching module SW1. The switching module SW1has an operating terminal G, an n-bit input terminal P[1:n], and an n-bit output terminal Q[1:n]. The input terminal P[1:n] and the output terminal Q[1:n] may be regarded as P1˜Pnand Q1˜Qnwhen the n bits are separated. The switching module SW1comprises n switching apparatus. In the present embodiment, all of the switching apparatuses mentioned above are the Metal Oxide Semiconductor Field Effect Transistors (MOSFET or MOS transistor). As shown inFIG. 9, the operating terminal G is connected to the gates of all MOS transistors. In addition, if k is an integer and 1≦k≦N, the kthMOS transistor among the N MOS transistors connects or disconnects the input terminal Pkto/from the output terminal Qkaccording to the input state of the operating terminal G.

In summary, in the present invention, a special designed data switching circuit is used to switch the data signal in pairs between the output channels of the source driver, and a special designed pixel array is used to transmit the switched data signal to the proper sub-pixel. In addition, if the dot inversion driving method is used, a positive polarity voltage or a negative polarity voltage is continuously outputted from the same output channel during the same frame, such that it is not required to switch between positive polarity and negative polarity. Accordingly, the swing voltage output from the source driver is reduced, and the power consumption is further reduced.