Package substrates and integrated circuit packages including the same

Packages substrates are provided. The package substrates may include a substrate and a set of leads disposed on the substrate. The set of lead may include a first lead, a second lead and a third lead, which are sequentially disposed along a first direction. Each of the first lead, the second lead and the third lead may extend along a second direction that is different from the first direction. The first lead and the second lead may be spaced apart at a first distance, and the second lead and the third lead may be spaced apart at a second distance that is less than the first distance.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application 10-2014-0000322, filed on Jan. 2, 2014, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The present disclosure generally relates to the field of electronics and, more particularly, to integrated circuit devices.

As integrated circuit devices become slim, light, fast, versatile and highly functional, integrated circuit devices have decreased in size and a number of terminals in these devices have increased. Accordingly, research has been conducted to decrease a pitch of terminals while reducing electrical contacts between the terminals and leads disposed on package substrates.

SUMMARY

A package substrate may include a substrate including a chip area configured to receive a semiconductor chip. The package substrate may also include a first set of leads and a second set of leads disposed on the chip area of the substrate along a first direction. The first set of leads may be disposed directly adjacent to the second set of leads. The first set of leads may include a first lead, a second lead and a third lead, which are sequentially disposed along the first direction. The second set of leads may include a fourth lead, a fifth lead and a sixth lead, which are sequentially disposed along the first direction. A first spacing between the first lead and the second lead may be similar to a third spacing between the third lead and the fourth lead. A second spacing between the second lead and the third lead may be less than the first spacing and the third spacing.

In various embodiments, each of the first spacing and the third spacing may be in a range of about 15 μm to about 40 μm, and the second spacing may be in a range of about 5 μm to about 25 μm.

In various embodiments, a first width of the first lead may be greater than a second width of the second lead and a third width of the third lead, and the second width of the second lead may be similar to the third width of the third lead.

According to various embodiments, the first width of the first lead may be in a range of about 15 μm to about 40 μm, and each of the second width of the second lead and the third width of the third lead may be in a range of about 10 μm to about 30 μm.

In various embodiments, a second distance between a center of the second lead and a center of the third lead may be less than a first distance between a center of the first lead and the center of the second lead and a third distance between the center of the third lead and a center of the fourth lead. The first distance may be similar to the third distance.

According to various embodiments, a distance between a center of the first lead and a center of the fourth lead in the first direction may be in a range of about 50 μm to about 150 μm.

In various embodiments, the package substrate may further include a seventh lead on the chip area of the substrate. The seventh lead may face the first lead and may be spaced apart from the first lead in a second direction that may be substantially perpendicular to the first direction. The second lead and the third lead may extend toward the first lead in the first direction such that each of the second lead and the third lead may have a segment that is disposed between the first lead and the seventh lead.

A semiconductor package may include a package substrate including a chip area, a first set of leads and a second set of leads. The first set of leads and the second set of leads may be disposed on the chip area of the package substrate along a first direction. The first set of leads may be disposed directly adjacent to the second set of leads. The first set of leads may include a first lead, a second lead and a third lead that are sequentially disposed along the first direction, and the second set of leads may include a fourth lead, a fifth lead and a sixth lead that are sequentially disposed along the first direction. The semiconductor package may also include a semiconductor chip mounted on the chip area of the package substrate and a plurality of input/output bumps disposed on a surface of the semiconductor chip. The plurality of input/output bumps may be connected to respective end portions of the first lead, the second lead and the third lead. A first spacing between the first lead and the second lead may be similar to a third spacing between the third lead and the fourth lead, and a second spacing between the second lead and the third lead may be less than the first spacing and the third spacing.

According to various embodiments, each of the first spacing and the third spacing may be in a range of about 15 μm to about 40 μm, and the second spacing may be in a range of about 5 μm to about 25 μm.

In various embodiments, a first width of the first lead may be greater than a second width of the second lead and a third width of the third lead, and the second width of the second lead may be similar to the third width of the third lead.

In various embodiments, the first width of the first lead may be in a range of about 15 μm to about 40 μm, and each of the second width of the second and the third width of the third lead may be in a range of about 10 μm to about 30 μm.

According to various embodiments, a second distance between a center of the second lead and a center of the third lead may be less than a first distance between a center of the first lead and the center of the second lead and a third distance between the center of the third lead and a center of the fourth lead. The first distance may be similar to the third distance.

According to various embodiments, a distance between a center of the first lead and a center of the fourth lead in the first direction may be in a range of about 50 μm to about 150 μm.

In various embodiments, the semiconductor package may further include a seventh lead on the chip area of the package substrate. The seventh lead may face the first lead and may be spaced apart from the first lead in a second direction that may be substantially perpendicular to the first direction. The second lead and the third lead may extend toward the first lead in the first direction such that each of the second lead and the third lead may have a segment that is disposed between the first lead and the seventh lead. The plurality of input/output bumps may be arranged along the second direction and spaced apart from each other at a regular interval.

According to various embodiments, each of the plurality of input/output bumps may include s a connection pillar and a solder bump, and the solder bump may directly contact a corresponding one of the first lead, the second lead and the third lead.

A package substrate may include a substrate and a set of leads disposed on the substrate. The set of leads may include a first lead, a second lead and a third lead. The first lead, the second lead and the third lead may be sequentially disposed along a first direction. Each of the first lead, the second lead and the third lead may extend along a second direction that may be different from the first direction. The first lead and the second lead may be spaced apart at a first distance, and the second lead and the third lead may be spaced apart at a second distance that may be less than the first distance.

According to various embodiments, the first distance may be in a range of about 15 μm to about 40 μm, and the second distance may be in a range of about 5 μm to about 25 μm.

In various embodiments, the first lead may have a first width, the second lead may have a second width, and the third lead may have a third width. The first width may be greater than the second width and the third width.

According to various embodiments, the first width may be in a range of about 15 μm to about 40 μm, and each of the second width and the third width may be in a range of about 10 μm to about 30 μm.

In various embodiments, each of the second lead and the third lead may have a segment extending toward the first lead in the first direction.

According to various embodiments, the segments of the second lead and the third lead extending toward the first lead in the first direction may be aligned to the first lead along the second direction.

In various embodiments, the package substrate may further include a fourth lead on the substrate. The fourth lead may be spaced apart from the first lead in the second direction. The segments of the second lead and the third lead extending toward the first lead in the first direction may be disposed between the first lead and the fourth lead.

According to various embodiments, the set of leads may be a first set of leads. The package substrate may further include a second set of leads that may be disposed directly adjacent to the first set of leads in the first direction on the substrate. The second set of leads may include a fourth lead, a fifth lead and a sixth lead, which may be sequentially disposed along the first direction. Each of the fourth lead, the fifth lead and the sixth lead may extend along the second direction. The fourth lead may be spaced apart from the third lead in the first direction at a third distance that may be greater than the second distance.

In various embodiments, the third distance may be similar to the first distance.

According to various embodiments, the third distance may be in a range of about 15 μm to about 40 μm, and the second distance may be in a range of about 5 μm to about 25 μm.

In various embodiments, a fourth distance between a center of the first lead and a center of the second lead may be similar to a fifth distance between a center of third lead and a center of the fourth lead.

According to various embodiments, a distance between a center of the first lead and a center of the fourth lead in the first direction may be in a range of about 50 μm to about 150 μm.

According to various embodiments, the substrate may include a chip area, which may be configured to receive an integrated circuit device thereon. The set of leads may be disposed on the chip area.

DETAILED DESCRIPTION

Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the spirit and teachings of this disclosure, and so the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout.

Example embodiments of the present inventive concept are described herein with reference to cross-sectional views or plan views that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the present inventive concept should not be construed as limited to the particular shapes illustrated herein but may include deviations in shapes.

It will be understood that when an element is referred to as being “coupled,” “connected,” or “responsive” to or “on” or “adjacent” another element, it can be directly coupled, connected, or responsive to or on or adjacent the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly coupled,” “directly connected” or “directly responsive” to or “directly on” or “directly adjacent” another element, there are no intervening elements present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.

Referring first toFIG. 1, a cross-sectional view illustrating a semiconductor package according to some embodiments of the present inventive concept will be discussed. As illustrated inFIG. 1, a semiconductor chip201may be mounted on a package substrate101. For example, the package substrate101may be a printed circuit board. In particular, the package substrate101may be a two-layered printed circuit board formed of copper clad laminate. Leads103may be disposed on a first surface of the package substrate101, and conductive pads may be placed on portions of the leads103. The leads103may contact chip pads105of the package substrate101. External terminals107may be attached onto a second surface of the package substrate101. The first surface of the package substrate101may be opposite the second surface of the package substrate101.

Bumps207may be formed on a surface of the semiconductor chip201. In some embodiments, each of the bumps207may include a connection pillar203having a predetermined height and a solder bump205on the connection pillar203. For example, the connection pillar203may be formed on the semiconductor chip201by photolithography and plating processes, and thereafter the solder bump205may be formed on the connection pillar203by a plating process. The connection pillar203may include copper.

A molding layer301may be formed on the semiconductor chip201on the package substrate101and to fill a space between the package substrate101and the semiconductor chip201. The molding layer301may fill spaces between the bumps207. In some embodiments, the molding layer301may completely fill the spaces between the bumps207.

Referring now toFIG. 2, a plan view illustrating a semiconductor package according to some embodiments of the present inventive concept will be discussed. InFIG. 2, a body of a semiconductor chip201is represented as transparent to show arrangements of bumps207, which are disposed under the semiconductor chip201. As illustrated inFIG. 2, the semiconductor chip201may be mounted on a chip area D of a package substrate101in a flip-chip bonding. The bumps207may include reference bumps207aand input/output bumps207b. The reference bumps207amay act as reference points such that the bumps207may attach to the conductive pads of the package substrate101correctly. The input/output bumps207bmay act as electrical interconnections between the package substrate101and the semiconductor chip201.

The chip area D may include a central region CR and a peripheral region PR. The reference bumps207amay be disposed on the central region CR of the chip area D, and the input/output bumps207bmay be disposed on the peripheral region PR of the chip area D. A distance DIST between the central region CR and the peripheral region PR may be about 400 μm. It will be understood that the distance DIST between the central region CR and the peripheral region PR refers a distance between edges of the central region CR and the peripheral region PR. The reference bumps207amay be disposed along a first direction at a first interval and the input/output bumps207bmay be disposed along the first direction at a second interval that is less than the first interval. For example, the first interval may be in a range of about 100 μm to about 200 μm, and the second interval may be in a range of about 20 μm to about 70 μm. The reference bumps207amay be disposed along a second direction at a third interval, and the input/output bumps207bmay be disposed along the second direction at a fourth interval. In some embodiments, the fourth interval may be less than the third interval. The second direction may be different from the first direction. In some embodiments, the second direction may be substantially perpendicular to the first direction.

Some input/output bumps207bmay be disposed on corners C of the peripheral region PR and may be arranged along a diagonal direction between the first direction and the second direction to reduce or possibly prevent a molding material (e.g., an epoxy resin solution) from flowing toward outside of the chip area D. Accordingly, the molding material may fill a space between the package substrate101and the semiconductor chip201. In some embodiments, the molding material may completely fill the space between the package substrate101and the semiconductor chip201.

Referring now toFIG. 3, an enlarged plan view of the section “A” ofFIG. 2illustrating configurations of bumps and leads included in a semiconductor package according to some embodiments of the present inventive concept will be discussed. As illustrated inFIG. 3, a first lead11, a second lead13and a third lead15may be arranged along the first direction on the package substrate101. The first lead11, the second lead13and the third lead15may extend in the second direction. Lengths of the first lead11, the second lead13and the third lead15may increase from the first lead11to the third lead14such that the first lead11has a length shorter than lengths of the second lead13and the third lead15, respectively. In some embodiments, the first lead11, the second lead13and the third lead15may extend from a side of the package substrate101. A fourth lead17may be disposed on the package substrate101and may extend along the second direction. The first lead11may face the fourth lead17and may be spaced apart from the fourth lead17in the second direction. In some embodiments, the first lead11and the fourth lead17may be aligned each other along the second direction.

As further illustrated inFIG. 3, the second lead13and the third lead15may extend toward the first lead11in the first direction. Specifically, the second lead13may have a first segment13aextending toward the first lead11in the first direction, and the third lead15may have a second segment15aextending toward the first lead11in the first direction. The first segment13aand the second segment15amay be disposed between the first lead11and the fourth lead17. In some embodiments, the first segment13aand the second segment15adisposed between the first lead11and the fourth lead17may be aligned to the first lead11along the second direction. Each of the second lead13and the third lead15may include several segments as shown inFIG. 3.

The input/output bumps207bmay include a first input/output bump21, a second input/output bump23, a third input/output bump25and a fourth input/output bump27. The first input/output bump21may contact the first lead11, the second input/output bump23may contact the second lead13, the third input/output bump25may contact the third lead15, and the fourth input/output bump27may contact the fourth lead17. In some embodiments, the first through the fourth input/output bumps21,23,25and27may contact respective end portions of the first through the fourth lead11,13,15and17. The second input/output bump23and the third input/output bump25may be disposed between the first input/output bump21and the fourth input/output bump27.

The first through the fourth input/output bumps21,23,25and27may be arranged along the second direction. In some embodiments, the first through the fourth input/output bumps21,23,25and27may be arranged in a straight line that extends in the second direction. The first through the fourth input/output bumps21,23,25and27may be arranged at a regular interval L1. It will be understood that the interval L1refers to a distance between centers of two input/output bumps in the second direction as illustrated inFIG. 3. For example, the interval L1may be in a range of from about 100 μm to about 200 μm. Each of the first through the fourth input/output bumps21,23,25and27may have a length L2in the second direction, and the length L2may be, for example, in a range of about 70 μm to about 150 μm. In some embodiments, each of the first through the fourth input/output bumps21,23,25and27may have a first width W1in the first direction, and the first width W1may be in a range of about 15 μm to about 60 μm.

It will be understood that as a pitch of the input/output bumps207bthat act as electrical interconnections decreases, a number of the input/output bumps207bwhich can be disposed on a limited area of the peripheral region PR may increase. Therefore, the input/output bumps207bmay have a fine pitch and a narrow spacing to increase the number of the input/output bumps207bin the peripheral region PR. When the input/output bumps207bhave a narrow spacing, the first through the third leads11,13and15may also have a narrow spacing. It will be understood that the narrow spacing of the first through the third leads11,13and15may cause electrical contact between the input/output bumps207band the first through the third leads11,13and15. For example, there may be a short due to electrical contact between the first input/output bump21and the second lead13.

A semiconductor package substrate according to some embodiments of the present inventive concept may include the first through the third leads11,13and15that have widths and arrangements, which allow increasing or possibly maximizing a number of the input/output bumps207bin the peripheral region PR, thereby improving integration of the input/output bumps207b.

As illustrated inFIG. 3, the first lead11, the second lead13and the third lead15may be included in a first set of leads, and multiple sets of leads may be disposed along the first direction. Further, fourth leads17may be also disposed along the first direction. It will be understood that each set of leads may include more than three leads.

Referring now toFIG. 4, a cross-sectional view taken along the line I-I′ ofFIG. 3illustrating a semiconductor package according to some embodiments of the present inventive concept will be discussed. As illustrated inFIG. 4, the first lead11, the second lead13and the third lead15may be formed to have a second width W2, a third width W3and a fourth width W4, respectively. In some embodiments, the third width W3of the second lead13and the fourth width W4of the third lead15may be less than the second width W2of the first lead11. In some embodiments, the third width W3and the fourth width W4may be similar or substantially equivalent. For example, the second width W2of the first lead11may be in a range of about 15 μm to about 40 μm, and each of the third width W3of the second lead13and the fourth width W4of the third lead15may be in a range of about 10 μm to about 30 μm.

Within one set of leads, a first spacing L3may be provided between the first lead11and the second lead13, and a second spacing L4may be provided between the second lead13and the third lead15. A third spacing L5may be provided between the third lead15and a first lead11of another set of leads that is disposed directly adjacent to the one set of leads along the first direction. It will be understood that the term “spacing” refers to a distance between sides of two leads as illustrated inFIG. 4. The first spacing L3, the second spacing L4and the third spacing L5may be different each other. In some embodiments, the first spacing L3and the third spacing L5may be greater than the second spacing L4, and the first spacing L3and the third spacing L5may be similar or substantially equivalent. For example, the first spacing L3may be in a range of about 15 μm to about 40 μm. The first spacing L3may be a minimum distance that is necessary to separate the second lead13from the first input/output bump21contacting the first lead11. The second spacing L4may be in a range of about 5 μm to about 25 μm. The third spacing L5may be in a range of about 15 μm to about 40 μm. The third spacing L5may be a minimum distance that is necessary to separate the third lead15from the first input/output bump21contacting the first lead11.

Still referring toFIG. 4, a second distance L7between a center of the second lead13and a center of the third lead15may be less than a first distance L6between a center of the first lead11and the center of the second lead15and a third distance L8between the center of the third lead15and a center of the first lead11that is disposed next to the third lead15. It will be understood that each of the first distance L6, the second distance L7and the third distance L8is a distance along the first direction. A distance between the centers of two first leads11along the first direction may be L6+L7+L8and may be in a range of about 50 μm to about 150 μm. It will be further understood that a phrase “a center of a lead” refers a center of a lead in the first direction as illustrated inFIG. 4.

The second spacing L4, the third width W3of the second lead13and the fourth width W4of the third lead15may decrease to increase the first spacing L3and the third spacing L5. Accordingly, the possibility of an electrical short between the first input/output bump21and the second lead13or between the third lead15and the first input/output bump21may be reduced or possibly prevented. According to some embodiments of the present inventive concept, when the first spacing L3or the third spacing L5increases, the distance between the centers of two first leads11, L6+L7+L8, may decrease. Therefore, a number of the input/output bumps207bdisposed in the peripheral region PR of the chip area D may increase such that reliability and electrical characteristics of a semiconductor package may be improved.

FIG. 5is a schematic block diagram illustrating an electronic system including a semiconductor package according to some embodiments of the present inventive concept.FIG. 6is a schematic block diagram illustrating a memory system including a semiconductor package according to some embodiments of the present inventive concept.

Referring toFIG. 5, an electronic system1000may include a controller1100, an input/output (I/O) device1200, and a memory1300. The controller1100, the I/O device1200, and the memory1300may be connected to each other through a bus1500. The bus1500may correspond to a data transfer path. The controller1100may include at least one of a microprocessor, a digital signal processor, a microcontroller, and other logic devices capable of performing similar functions thereto. The controller1100and the memory1300may include a semiconductor package according to some embodiments of the present inventive concept. The I/O device1200may include, for example, a keypad, a keyboard or a display device. The memory1300may store data and/or commands executed by the controller1100. The memory1300may include a volatile memory device and/or a nonvolatile memory device. In some embodiments, the memory1300may be a flash memory device. For example, a flash memory device according to some embodiments may be mounted on an information processing system such as a mobile device or desktop computer. For example, the flash memory device may be a solid state disk (SSD). In this case, the electronic system1000can store large amounts of data in the flash memory device. The electronic system1000may further include an interface1400to communicate data with a communication network. The interface1400may be wired or wireless. For example, the interface1140may include antennas, wire/wireless transceivers, etc. It will be understood that the electronic system1000may further include an application chipset, a camera image processor (CIS) and/or an input/output device.

The electronic system1000may be a mobile system, a personal computer, an industrial computer, or system carrying out various functions. For example, the mobile system may be a personal digital assistant (PDA), a portable computer, a web-tablet, a mobile phone, a wireless phone, a laptop computer, a memory card, a digital music system, or an information transmitting/receiving system. The electronic system1000may be used in a wireless communication system using an interface protocol such as CDMA, GSM, NADC, E-TDMA, WCDAM, and CDMA1000.

Referring now toFIG. 6, a memory card1600may include a nonvolatile memory device1610and a memory controller1620. The nonvolatile memory device1610may store data, and the memory controller1620may read stored data. The nonvolatile memory device1610may include a semiconductor package according to some embodiments of the present inventive concept. The memory controller1620may read stored data and control to store data in the nonvolatile memory device1610in response to a read/write request of a host1630.

According to some embodiments of the present inventive concept, input/output bumps of a chip contacting leads that are disposed on a package substrate may be arranged to have a small pitch and to reduce or possibly prevent the occurrence of electrical shorts between the input/output bumps and the leads. Widths and/or arrangement of the leads may be determined to reduce the occurrence of electrical shorts between the input/output bumps and the leads. Thus, a number of the input/output bumps disposed on a limited area of the package substrate may increase, thereby reducing fabrication cost of the package substrate and improving reliability and electrical characteristics of the semiconductor package.