SEMICONDUCTOR PACKAGE AND COOLING SYSTEM THEREOF

A semiconductor package includes a package substrate; an interposer on the package substrate; a first semiconductor chip on the interposer; at least one second semiconductor chip on the interposer; a molding layer extending around the first semiconductor chip and the at least one second semiconductor chip; a barrier layer on the upper surface of the molding layer; a separation wall on the barrier layer, the separation wall configured to define a first cooling space adjacent the first semiconductor chip and a second cooling space adjacent the at least one second semiconductor chip; and a heat dissipation structure on the separation wall, wherein the heat dissipation structure provides a cooling channel through which the cooling fluid flows.

CROSS-REFERENCE TO RELATED APPLICATION

BACKGROUND

The inventive concept relates generally to semiconductor packages and, more particularly, to cooling semiconductor packages.

There is increased demand for semiconductor devices with enhanced functionality. In order to meet performance and price requirements of consumers, the degree of integration and miniaturization of semiconductor elements has increased. To satisfy these demands multiple semiconductor chips are being provided within smaller packages. Unfortunately, heat generated by multiple semiconductor chips in a single package may hinder performance and/or cause thermal stress.

SUMMARY

The inventive concept provides a semiconductor package capable of cooling using a cooling fluid and a cooling system thereof.

According to an aspect of the inventive concept, there is provided a semiconductor package including: a package substrate; an interposer on the package substrate; a first semiconductor chip on the interposer; at least one second semiconductor chip on the interposer; a molding layer extending around the first semiconductor chip and the at least one second semiconductor chip; a barrier layer on an upper surface of the molding layer; a separation wall on the barrier layer, the separation wall configured to define a first cooling space adjacent the first semiconductor chip and a second cooling space adjacent the at least one second semiconductor chip, wherein the separation wall is configured to allow a cooling fluid to flow between the first cooling space and the second cooling space; and a heat dissipation structure on the separation wall adjacent the first cooling space and the second cooling space, wherein the heat dissipation structure includes: an inlet; an outlet; a cooling channel in fluid communication with the inlet, the first cooling space and the second cooling space, wherein the cooling channel is configured to receive the cooling fluid from the inlet and direct the cooling fluid into the first cooling space and the second cooling space; and an outflow channel in fluid communication with the first cooling space and the outlet, wherein the outflow channel is configured to discharge the cooling fluid from the first cooling space through the outlet.

According to another aspect of the inventive concept, there is provided a semiconductor package including: a plurality of semiconductor chips; a molding layer extending around the plurality of semiconductor chips; a barrier layer on an upper surface of the molding layer and including a metal; a separation wall on the barrier layer, the separation wall configured to define a plurality of cooling spaces adjacent the plurality of semiconductor chips and to allow a cooling fluid to flow between the plurality of cooling spaces; and a heat dissipation structure adjacent the plurality of cooling spaces and contacting the separation wall, the heat dissipation structure includes: an inlet; an outlet; a cooling channel in fluid communication with the inlet and the plurality of cooling spaces, wherein the cooling channel is configured to receive the cooling fluid from the inlet and direct the cooling fluid into the plurality of cooling spaces; and an outflow channel in fluid communication with the plurality of cooling spaces and the outlet, wherein the outflow channel is configured to discharge the cooling fluid from the plurality of cooling spaces through the outlet.

According to an aspect of the inventive concept, there is provided a cooling system for cooling a semiconductor package, the cooling system including: a package substrate; an interposer on the package substrate; a first semiconductor chip on the interposer; at least one second semiconductor chip on the interposer; a molding layer extending around the first semiconductor chip and the at least one second semiconductor chip; a barrier layer on an upper surface of the molding layer; a separation wall on the barrier layer, the separation wall configured to define a first cooling space adjacent the first semiconductor chip and a second cooling space adjacent the at least one second semiconductor chip, wherein the separation wall is configured to allow a cooling fluid to flow between the first cooling space and the second cooling space; and a heat dissipation structure on the separation wall adjacent the first cooling space and the second cooling space, wherein the heat dissipation structure comprises an inlet, an outlet, a cooling channel in fluid communication with the inlet and the second cooling space, and an outflow channel in fluid communication with the first cooling space and the outlet; a water cooling pump configured to provide the cooling fluid to the inlet of the heat dissipation structure; and a heat dissipater configured to collect the cooling fluid discharged from the outlet of the heat dissipation structure, wherein the cooling channel is configured to provide the cooling fluid into the second cooling space to cool the second semiconductor chip, and the separation wall is configured to allow the cooling fluid to flow from the second cooling space into the first cooling space to cool the first semiconductor chip.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the technical idea of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof will be omitted.

FIG.1Ais a cross-sectional view illustrating main components of a semiconductor package10according to example embodiments of the inventive concept.FIGS.1B to1Gare plan views taken along levels LV1 to LV6 ofFIG.1A, respectively.

Referring toFIGS.1A to1G, the semiconductor package10may include a first semiconductor chip100, a second semiconductor chip200, a molding layer300, an interposer400, a package substrate500, a moisture absorption barrier layer610, a support structure620, a sealing ring630, a heat dissipation structure700, and a separation wall800.

The semiconductor package10may include the first semiconductor chip100and the second semiconductor chip200, which perform different functions. The semiconductor package10may include one or more first semiconductor chips100and one or more second semiconductor chips200. The first and second semiconductor chips100and200may be arranged side by side in a first horizontal direction (e.g., an X direction) and/or a second horizontal direction (e.g., a Y direction), and may be electrically connected to each other through the interposer400. As shown inFIG.1B, four second semiconductor chips200may be arranged around the first semiconductor chip100. That is, two second semiconductor chips200may be arranged adjacent to one edge of an upper surface100S of the first semiconductor chip100, and two second semiconductor chips200may be arranged adjacent to the other edge of the upper surface1000S of the first semiconductor chip100.

The first semiconductor chip100may include a logic chip. The logic chip may include a plurality of logic devices (not shown) therein. Each of the logic devices may refer to, for example, a device including a logic circuit, such as an AND, an OR, a NOT, a flip-flop, or the like, thereby performing various signal processing. In some embodiments, the logic devices may include devices performing signal processing, such as analog signal processing, analog-to-digital conversion, control, and the like.

In some embodiments, the first semiconductor chip100may be implemented as a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an application processor, a system on chip, and the like, depending on the function of the first semiconductor chip100.

The second semiconductor chip200may include a volatile memory chip and/or a nonvolatile memory chip. The volatile memory chip may include, for example, dynamic random access memory (DRAM), static RAM (SRAM), or thyristor RAM (TRAM). The nonvolatile memory chip may include, for example, flash memory, magnetic RAM (MRAM), spin-transfer torque MRAM (STT-MRAM), ferroelectric RAM (FRAM), phase change RAM (PRAM), or resistive RAM (RRAM).

In some embodiments, the second semiconductor chip200may include a memory chiplet including a plurality of memory chips capable of merging data therebetween. In addition, the second semiconductor chip200may include a high bandwidth memory (HBM) chip.

Each component constituting the first and second semiconductor chips100and200will be described in detail below.

The first semiconductor chip100may include a first semiconductor substrate101, a first semiconductor interconnect layer110, a first connection pad140, and a first connection member150.

The first semiconductor chip100may include a single slice, and the single slice may include the first semiconductor substrate101. The first semiconductor substrate101may include an active surface and an inactive surface facing each other as a wafer. Here, the inactive surface of the first semiconductor substrate101may include an upper surface100S of the first semiconductor chip100exposed from the molding layer300.

The first semiconductor substrate101may include, for example, a silicon (Si) wafer including crystalline silicon, polycrystalline silicon, or amorphous silicon. Alternatively, the first semiconductor substrate101may include a semiconductor element, such as germanium, or a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).

Meanwhile, the first semiconductor substrate101may have a silicon on insulator (SOI) structure. For example, the first semiconductor substrate101may include a buried oxide (BOX) layer. In some embodiments, the first semiconductor substrate101may include a conductive region, for example, a well doped with impurities or a structure doped with impurities. In addition, the first semiconductor substrate101may have various device isolation structures, such as a shallow trench isolation (STI) structure.

The first semiconductor interconnect layer110may be arranged on the active surface of the first semiconductor substrate101and may be electrically connected to the first connection pad140on the first semiconductor interconnect layer110. The first semiconductor interconnect layer110may be electrically connected to the first connection member150through the first connection pad140. The first connection pad140may include, for example, at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

The first connection member150may be arranged to electrically connect the first semiconductor chip100to the interposer400. The first connection member150may include a solder ball attached to the first connection pad140. The material constituting the solder ball may include at least one of gold (Au), silver (Ag), copper (Cu), tin (Sn), and aluminum (Al). In some embodiments, the solder ball may be connected to the first connection pad140by any one of a thermal compression connection and an ultrasonic connection, and may be connected to the first connection pad140by a thermosonic connection method, which is obtained by combining a thermal compression connection method with an ultrasonic connection method.

At least one of a control signal, a power signal, and a ground signal for operation of the first semiconductor chip100may be provided from the outside through the first connection member150, or a data signal to be stored in the first semiconductor chip100may be externally provided through the first connection member150, or data stored in the first semiconductor chip100may be provided to the outside through the first connection member150.

The second semiconductor chip200may include a second semiconductor substrate201, a second semiconductor interconnect layer210, a second upper connection pad220, a second through electrode230, a second lower connection pad240, and a second connection member250.

The second semiconductor chip200may include a plurality of slices, and each of the plurality of slices may include the second semiconductor substrate201. The plurality of second semiconductor substrates201constitute a chip stack and may be stacked in a vertical direction (Z-direction). The plurality of second semiconductor substrates201may be substantially the same as each other. That is, the second semiconductor chip200may have a structure in which each of a plurality of slices operates as a memory chip and is stacked to allow data to be merged with each other.

Each of the plurality of second semiconductor substrates201may have an active surface and an inactive surface facing each other. Here, an inactive surface of the uppermost one among the plurality of second semiconductor substrates201may include an upper surface200S of the second semiconductor chip200exposed from the molding layer300. The remainder of the plurality of second semiconductor substrates201, except for the uppermost one, may include the second through electrode230passing therethrough. The second through electrode230may include, for example, a through silicon via (TSV).

The second upper connection pad220and the second lower connection pad240may be electrically connected to the upper and lower parts of the second through electrode230. In addition, the second lower connection pad240may be electrically connected to the second semiconductor interconnect layer210on the active surface of the second semiconductor substrate201. The second semiconductor interconnect layer210may be electrically connected to the second connection member250through the second lower connection pad240.

The second connection member250contacting the lowermost one of the plurality of second semiconductor substrates201may electrically connect the second semiconductor chip200to the interposer400. The second connection member250may include a solder ball attached to the second lower connection pad240.

At least one of a control signal, a power signal, and a ground signal for operation of the second semiconductor chip200may be provided from the outside through the second connection member250, or a data signal to be stored in the second semiconductor chip200may be externally provided through the second connection member250, or data stored in the second semiconductor chip200may be provided to the outside through the second connection member250.

The molding layer300may be formed to surround the first and second semiconductor chips100and200. Specifically, the molding layer300may extend along the side and lower surfaces of each of the first and second semiconductor chips100and200, and cover the side and lower surface of each of the first and second semiconductor chips100and200. Here, the molding layer300may not cover the upper surface100S of the first semiconductor chip100and the upper surface200S of the second semiconductor chip200. Accordingly, at the first level LV1, an upper surface300S of the molding layer300may be coplanar with the upper surface100S of the first semiconductor chip100and the upper surface200S of the second semiconductor chip200.

The molding layer300may protect the first and second semiconductor chips100and200from external influences, such as impact and contamination. To perform this role, the molding layer300may be made of an epoxy mold compound or a resin. In addition, the molding layer300may be formed by a process, such as compression molding, lamination, screen printing, or the like.

The interposer400may be arranged below the first and second semiconductor chips100and200, and may electrically connect the first semiconductor chip100and the second semiconductor chip200to each other. In some embodiments, the interposer400may include a silicon substrate401and may include a redistribution structure420arranged on an upper portion of the silicon substrate401. The interposer400may include a through electrode430electrically connected to the redistribution structure420and penetrating the silicon substrate401, a connection pad440arranged below the silicon substrate401and electrically connected to the through electrode430, and an internal connection terminal450attached to the connection pad440.

A package substrate500may be arranged below the interposer400. The package substrate500may be formed on the basis of a printed circuit board, a wafer substrate, a ceramic substrate, a glass substrate, or the like. In example embodiments, the package substrate500may include a printed circuit board. The package substrate500may include a bump pad540arranged under a lower surface of a body portion501and an external connection terminal550attached to the bump pad540. The semiconductor package10may be electrically connected to a main board or a system board of an external electronic device on which the semiconductor package10is mounted through the external connection terminal550.

An underfill UF may be formed between the interposer400and the package substrate500. The underfill UF may be between the interposer400and the package substrate500to surround the internal connection terminal450. The underfill UF may be made of, for example, an epoxy resin. In some embodiments, a non-conductive film (NCF) other than the underfill (UF) may be formed.

The moisture absorption barrier layer610may be arranged on the molding layer300, the first semiconductor chip100, and the second semiconductor chip200. The moisture absorption barrier layer610may conformally extend along (i.e., conform to various configurations, levels, shapes, etc., of) the upper surface300S of the molding layer300, the upper surface100S of the first semiconductor chip100, and/or the upper surface200S of the second semiconductor chip200. The moisture absorption barrier layer610may cover the upper surface300S of the molding layer300, the upper surface100S of the first semiconductor chip100, and/or the upper surface200S of the second semiconductor chip200.

In example embodiments, the moisture absorption barrier layer610may entirely cover the upper surface300S of the molding layer300, the upper surface100S of the first semiconductor chip100, and/or the upper surface200S of the second semiconductor chip200. In example embodiments, the moisture absorption barrier layer610may entirely cover the upper surface300S of the molding layer300, but may not cover at least a part of the upper surface100S of the first semiconductor chip100and/or at least a part of the upper surface200S of the second semiconductor chip200.

The moisture absorption barrier layer610may prevent a cooling fluid (CT ofFIG.4A) from penetrating the molding layer300, the first semiconductor chip100, and/or the second semiconductor chip200. That is, the moisture absorption barrier layer610may be configured to prevent the cooling fluid CT from being absorbed or adsorbed to the molding layer300, the first semiconductor chip100, and/or the second semiconductor chip200. In example embodiments, the moisture absorption barrier layer610may include a waterproof material, such as metal, silicon (Si), or the like. For example, the moisture absorption barrier layer610may include material layers stacked in a vertical direction (e.g., a Z direction). For example, the moisture absorption barrier layer610may include titanium (Ti), copper (Cu), nickel (Ni), gold (Au), silver (Ag), aluminum (Al), silicon (Si), or a combination thereof. For example, the moisture absorption barrier layer610may include a first layer including titanium (Ti) and a second layer including at least one of copper (Cu), nickel (Ni), and silicon (Si).

In addition, the moisture absorption barrier layer610includes a material having excellent thermal conductivity, such as metal, and thus may facilitate cooling of the first semiconductor chip100and cooling of the second semiconductor chip200using the cooling fluid CT. When the moisture absorption barrier layer610is formed to cover the upper surface100S of the first semiconductor chip100and the upper surface200S of the second semiconductor chip200, heat generated from the first semiconductor chip100and heat generated from the second semiconductor chip200may be transferred to the cooling fluid CT through the moisture absorption barrier layer610.

The separation wall800may be arranged on the moisture absorption barrier layer610. The separation wall800may cover the upper surface300S of the molding layer300between the upper surface100S of the first semiconductor chip100and the upper surface200S of the second semiconductor chip200. In a plan view, the separation wall800may cover the upper surface300S of the molding layer300between the upper surface100S of the first semiconductor chip100and the upper surface200S of the second semiconductor chip200and the upper surface300S of the molding layer300between the upper surfaces of the two adjacent first semiconductor chips100. In a plan view, the separation wall800may extend along a boundary between the first semiconductor chip100and the molding layer300, and may extend along a boundary between the second semiconductor chip200and the molding layer300. According to example embodiments, the upper surface300S of the molding layer300may be doubly covered by the moisture absorption barrier layer610and the separation wall800, as illustrated inFIG.1A, thereby effectively preventing the cooling fluid CT from being absorbed by the molding layer300.

The separation wall800may define a first cooling space810adjacent (e.g., overlying) the first semiconductor chip100in a vertical direction (for example, in a Z direction) and a second cooling space820adjacent (e.g., overlying) the second semiconductor chip200, as illustrated inFIG.1A. When viewed in a plan view, the first cooling space810directly overlies the first semiconductor chip100in a vertical direction (e.g., the Z direction), but does not directly overlie the second semiconductor chip200, as illustrated inFIG.1A. When viewed in a plan view, the second cooling space820directly overlies the second semiconductor chip200in a vertical direction (e.g., the Z direction), but does not directly overlie the first semiconductor chip100, as illustrated inFIG.1A. When viewed in a plan view, the first cooling space810and the second cooling space820may be separated or partitioned from each other by the separation wall800. Furthermore, when viewed in a plan view, the first cooling spaces810adjacent to each other may be separated or partitioned from each other by the separation wall800.

The separation wall800may be configured to allow the cooling fluid CT to pass or transmit therethrough. For example, the separation wall800may include a passage for passing or transmitting the cooling fluid CT. The cooling fluid CT may flow through the passage of the separation wall800between the first cooling space810and the second cooling space820, and the cooling fluid CT may flow through the passage of the separation wall800between the adjacent first cooling spaces810. The separation wall800may be formed of a metal material or a non-metal material. In example embodiments, the separation wall800may include a porous material. In embodiments, the separation wall800may include a metal foam such as copper foam or nickel foam, a plastic foam, and/or a mesh structure. For example, the thickness of the separation wall800may range between about 100 micrometers (μm) and about 1,000 μm, but is not limited thereto.

In example embodiments, a material layer formed of a material different from that of the separation wall800may be between the separation wall800and the moisture absorption barrier layer610. The material layer may increase adhesion between the separation wall800and the moisture absorption barrier layer610, or may prevent a part of the moisture absorption barrier layer610overlapping the upper surface300S of the molding layer300from directly contacting the cooling fluid CT passing through the separation wall800.

The support structure620may be arranged on an outer portion of an upper surface of the package substrate500. The support structure620may support the heat dissipation structure700. For example, the support structure620may provide a mounting groove in which the heat dissipation structure700may be mounted on an upper side thereof. In addition, the support structure620may have a through hole formed in a region overlapping the first semiconductor chip100and the second semiconductor chip200. For example, the through hole of the support structure620may have a rectangular shape. In addition, when viewed in a plan view, a portion of the support structure620may cover an outer portion of the upper surface300S of the molding layer300. As illustrated inFIG.1D, a portion of the support structure620may surround the first cooling space810and the second cooling spaces820. The support structure620may include a metal material, such as copper (Cu), aluminum (Al), stainless steel (SUS), or the like. The support structure620may be spaced apart from the first and second semiconductor chips100and200and the interposer400to form a cavity or space VA. That is, the first and second semiconductor chips100and200and the interposer400may be accommodated in the cavity VA provided by the support structure620.

The sealing ring630may be arranged between the moisture absorption barrier layer610and the support structure620. The sealing ring630may include a material having excellent elastic resilience, for example, rubber. The sealing ring630may be arranged on an outer region of the moisture absorption barrier layer610covering the outer region of the upper surface300S of the molding layer300. The sealing ring630may continuously extend along the outer periphery of the upper surface300S of the molding layer300. The sealing ring630may surround the separation wall800when viewed in a plan view. Alternatively, the sealing ring630may surround the first cooling space810and the second cooling space820defined by the separation wall800when viewed in a plan view. The sealing ring630may be between the moisture absorption barrier layer610and the support structure620to remove (i.e., fill) a gap between the moisture absorption barrier layer610and the support structure620. The sealing ring630may remove (i.e., fill) a gap between the moisture absorption barrier layer610and the support structure620to prevent the cooling fluid CT in the first cooling space810and the second cooling space820from leaking to the empty space VA of the support structure620.

The heat dissipation structure700may be arranged on the support structure620and the separation wall800. The heat dissipation structure700may be in close contact with the upper side of the separation wall800to cover the first cooling space810and the second cooling space820. The heat dissipation structure700may be formed of a material having high thermal conductivity. For example, the heat dissipation structure700may be formed of a metal material, such as copper (Cu), aluminum (Al), stainless steel (SUS), or the like, but is not limited thereto. The heat dissipation structure700may provide an internal channel through which the cooling fluid CT may flow. The cooling fluid CT may be provided to the first cooling space810and the second cooling space820through an internal channel of the heat dissipation structure700to cool the first semiconductor chip100and the second semiconductor chip200.

The heat dissipation structure700may include an inlet701through which a cooling fluid CT is introduced, an outlet703through which the cooling fluid CT is discharged, a cooling channel710extending from the inlet701, a plurality of apertures720that provide fluid communication between the cooling channel710and the first cooling space810and/or between the cooling channel710and the second cooling space820, and an outflow channel750extending between the first cooling space810and the outlet703. The cooling fluid CT flows into the cooling channel710through the inlet701of the heat dissipation structure700, flows from the cooling channel710through the plurality of apertures720to the first cooling space810or the second cooling space820, flows from the second cooling space820to the first cooling space810through one or more passages in the separation wall800, and flows from the first cooling space810to the outlet703through the outflow channel750.

A plurality of apertures720may be provided adjacent (e.g., above) the first cooling space810and/or the second cooling space820. The apertures720are formed in a lower portion of the heat dissipation structure700, as illustrated inFIG.1A, such that the cooling fluid flowing through the cooling channel710flows downward through the apertures720and into the first cooling space810and/or the second cooling space820. For example, as illustrated inFIG.1A, the first cooling space810and the second cooling space820may be at the third level LV3, the plurality of apertures720may be at a fourth level LV4 that is higher than the third level LV3, and the cooling channel710may be at a fifth level LV5 that is higher than the fourth level LV4.

When viewed in a plan view, some of the plurality of apertures720provide fluid communication between the cooling channel710and the first cooling space810, and some other ones of the plurality of apertures720provide fluid communication between the cooling channel710and the second cooling space820. In some example embodiments, the plurality of apertures720are provided so as to be in fluid communication only with the second cooling space820and may not also be in fluid communication with the first cooling space810. The plurality of apertures720may have a width (or diameter) between several micrometers and hundreds of micrometers. For example, the width of each of the plurality of apertures720may be in a range of about 1 μm to about 500 μm.

When the semiconductor package10includes a plurality of second semiconductor chips200and a plurality of second cooling spaces820, the number and arrangement of apertures720communicating with each of the plurality of second cooling spaces820may be substantially the same. When the number and arrangement of the apertures720provided above the plurality of second cooling spaces820are substantially the same, the flow rate of the cooling fluid CT supplied to each of the second cooling spaces820through the plurality of apertures720is uniform, thereby uniformly controlling cooling performance for the plurality of second semiconductor chips200.

As illustrated inFIG.1F, the cooling channel710may overlie all semiconductor chips included in the semiconductor package10. For example, the cooling channel710may have a rectangular ring shape in a plan view and overlie the first semiconductor chip100and all second semiconductor chips200arranged around the first semiconductor chip100.

In addition, as illustrated inFIG.1G, the outlet703and outflow channel750may be closer to the center of the upper surface100S of the first semiconductor chip100than the inlet701. For example, the outlet703and outflow channel750may overlie the first semiconductor chip100when viewed in a plan view, and the inlet701may be spaced apart from the first semiconductor chip100in an outward direction when viewed in a plan view. The inlet701may overlie the second semiconductor chips200or may be spaced apart from the second semiconductor chips200in an outward direction.

Since the first cooling space810related to cooling of the first semiconductor chip100and the second cooling space820related to cooling of the second semiconductor chip200are separated by the separation wall800, thermal coupling between the first semiconductor chip100and the second semiconductor chip200may be reduced. For example, when the first semiconductor chip100includes a logic chip and the second semiconductor chip200includes a memory chip, the highest allowable temperature of the first semiconductor chip100may be greater than the highest allowable temperature of the second semiconductor chip200. Since thermal coupling between the first semiconductor chip100and the second semiconductor chip200is reduced, performance of the second semiconductor chip200having a relatively low maximum allowable temperature may be reduced due to heat generation of the first semiconductor chip100having a relatively high maximum allowable temperature.

According to example embodiments, the cooling fluid CT may be sprayed into the first cooling space810and/or the second cooling spaces820through the plurality of apertures720, and the velocity of the cooling fluid CT may increase as it flows through the plurality of apertures720. Since the cooling fluid CT having an increased velocity is sprayed to the first semiconductor chip100and the second semiconductor chip200, jet impingement cooling may be performed for cooling of the first semiconductor chip100and the second semiconductor chip200. Accordingly, the cooling efficiency for the first semiconductor chip100and the second semiconductor chip200may be improved.

FIGS.2A to2Fare plan views illustrating apertures720of a heat dissipation structure700according to example embodiments of the inventive concept.

Referring toFIG.2A, the apertures720may have a circular shape.

Referring toFIG.2B, the apertures720may have a slit shape or an oval shape.

Referring toFIG.2C, the apertures720may have a polygonal shape. For example, the apertures720may have a rectangular shape, as illustrated.

Referring toFIG.2D, the apertures720may have a cross shape. For example, the apertures720may have a rectangular central part and protrusions from the central part in four different directions, as illustrated.

Referring toFIG.2E, the apertures720may have a star shape. For example, the apertures720may have a central portion and protrusions from the central portion in four different directions, as illustrated. In this case, the widths of the protrusions may narrow away from the central portion.

Referring toFIG.2F, the apertures720may have an arrowhead shape. For example, the apertures720may have a shape in which two portions linearly extending in different directions meet each other at one point, as illustrated.

FIGS.3A to3Dare cross-sectional views schematically illustrating a cross-section of a separation wall800according to example embodiments of the inventive concept.

Referring toFIG.3A, the separation wall800may have a mesh structure. The cooling fluid may be transmitted through passages860of the separation wall800having a mesh structure.

Referring toFIG.3B, the passages860of the separation wall800may have a circular shape and have a constant diameter. Alternatively, the passages860of the separation wall800may have a polygonal shape, such as a rectangular shape.

Referring toFIG.3C, the passages860of the separation wall800may have an oval shape or a slit shape.

Referring toFIG.3D, the passages860of the separation wall800may have a slit shape, but the sizes thereof may be different from each other, as illustrated.

FIG.4Ais a cross-sectional view illustrating a cooling system CS of a semiconductor package10according to example embodiments of the inventive concept.FIG.4Bis a plan view of the cooling system CS ofFIG.4A.FIG.4Billustrates a cut surface of the cooling system CS along a level corresponding to the LV2 level ofFIG.1A.

Referring toFIGS.4A and4Btogether withFIG.1A, the cooling system CS is provided on the semiconductor package10and may include a cooling fluid CT, a water cooling pump910, and a heat dissipater920.

The cooling fluid CT may be deionized water or a mixture of deionized water and one or more additives. The additives may include, for example, a surfactant, a corrosion inhibitor, antifreeze, and thermally conductive nanoparticles.

The water cooling pump910may be connected to the inlet701of the heat dissipation structure700, and the heat dissipater920may be connected to the outlet703of the heat dissipation structure700. The water cooling pump910and the heat dissipater920may be respectively connected to the inlet701and the outlet703of the heat dissipation structure700through a piping system.

The operation process of the cooling system CS will be described in detail below. InFIGS.4A and4B, arrows schematically indicate flow paths of the cooling fluid CT. First, the cooling fluid CT provided from the water cooling pump910flows into the inlet701of the heat dissipation structure700. Next, the cooling fluid CT flows along the cooling channel710of the heat dissipation structure700and flows to the first cooling space810and the second cooling space820through the plurality of apertures720. The cooling fluid CT in the second cooling space820flows to the first cooling space810through the separation wall800configured to transmit the cooling fluid CT. Next, the cooling fluid CT flows from the first cooling space810to the outlet703through the outflow channel750and is collected by the heat dissipater920connected to the outlet703.

In general, the internal temperature of the semiconductor package10may increase while the semiconductor package10is operating. In this case, the internal temperature of the semiconductor package10may be higher than the temperature of the heat dissipation structure700and the temperature of the cooling fluid CT. Accordingly, when the cooling fluid CT is provided to the first cooling space810and the second cooling space820, heat exchange may occur between each of the first and second semiconductor chips100and200and the cooling fluid CT. As a result of the heat exchange, the internal temperature of the semiconductor package10may be lowered, and the temperature of the cooling fluid CT may be increased. The cooling fluid CT having an increased temperature may be cooled by the heat dissipater920before being used again for cooling the semiconductor package10.

Demand for portable devices has been increasing rapidly in the electronic products market, and for this reason, miniaturization and lighter weight electronic components mounted on these electronic products may be required. To accomplish miniaturization and weight reduction, semiconductor packages are increasingly required to process high-capacity data within a smaller package volume. Thus, there is a need for high integration and single packaging of semiconductor chips mounted in semiconductor packages. However, problems due to overheating and thermal fatigue may become significant because of the structure of conventional semiconductor packages.

The semiconductor package10according to the example embodiments is designed to connect a water-cooled cooling device to the upper part of the heat dissipation structure700. Accordingly, cooling of the first and second semiconductor chips100and200may be realized by direct cooling using the cooling fluid CT, and the moisture absorption barrier layer610and the separation wall800are also formed to cover the upper surface300S of the molding layer300, to thereby ensure excellent waterproof performance.

In addition, in the semiconductor package10according to example embodiments, a cooling fluid CT having an increased velocity while passing through the plurality of apertures720may be sprayed on the first semiconductor chip100and the second semiconductor chip200to perform jet impingement cooling on the first semiconductor chip100and the second semiconductor chip200, thereby improving cooling efficiency of the first semiconductor chip100and the second semiconductor chip200. Accordingly, a failure, such as a malfunction of the first and second semiconductor chips100and200, may be prevented from deteriorating product reliability due to overheating.

FIG.5Ais a cross-sectional view illustrating a semiconductor package10A according to example embodiments of the inventive concept.FIG.5Bis a cross-sectional view taken along line VB-VB′ ofFIG.5A. Hereinafter, the semiconductor package10A illustrated inFIGS.5A and5Bwill be described based on the difference from the semiconductor package10described above with reference toFIGS.1A to1G.

Referring toFIGS.5A and5B, the barrier layer610A may cover an upper surface300S of the molding layer300, but may not cover at least a part of the upper surface100S of the first semiconductor chip100and at least a part of the upper surface200S of the second semiconductor chip200. The barrier layer610A may include a first opening611for exposing at least a part of the upper surface100S of the first semiconductor chip100and a second opening613for exposing at least a part of the second semiconductor chip200, as illustrated inFIG.5B. The first cooling space810and the upper surface100S of the first semiconductor chip100may directly communicate with each other through the first opening611of the barrier layer610A. The second cooling space820and the upper surface200S of the second semiconductor chip200may directly communicate with each other through the second opening613of the barrier layer610A.

FIG.6Ais a cross-sectional view illustrating a semiconductor package10B according to example embodiments of the inventive concept.FIG.6Bis a cross-sectional view taken along line VIB-VIB′ ofFIG.6A. Hereinafter, the semiconductor package10B illustrated inFIGS.6A and6Bwill be described based on the difference from the semiconductor package10described above with reference toFIGS.1A to1G.

Referring toFIGS.6A and6B, the barrier layer610B may cover the upper surface300S of the molding layer300and the upper surface100S of the first semiconductor chip100, but may not cover at least a part of the upper surface200S of the second semiconductor chip200. The barrier layer610B may include a second opening613for exposing at least a portion of the second semiconductor chip200, as illustrated inFIG.6B. The second cooling space820and the top surface200S of the second semiconductor chip200may directly communicate with each other through the second opening613of the barrier layer610B.

FIG.7Ais a cross-sectional view illustrating a semiconductor package10C according to example embodiments of the inventive concept.FIG.7Bis a cross-sectional view taken along line VIIB-VIIB′ ofFIG.7A. Hereinafter, the semiconductor package10C illustrated inFIGS.7A and7Bwill be described based on the difference from the semiconductor package10described above with reference toFIGS.1A to1G.

Referring toFIGS.7A and7B, the semiconductor package10C may include a plurality of structures650provided in the first cooling space810. The illustrated structures650have a “pillar” or “column” shape, and extend upward from the moisture absorption barrier layer610. The illustrated plurality of structures650extend upward from the moisture absorption barrier layer610in the form of a two-dimensional array. The plurality of structures650are configured to induce vortex generation (i.e., turbulence) in the flow of the cooling fluid (CT ofFIG.4A) in the first cooling space810, thereby increasing the heat exchange efficiency between the cooling fluid CT and the first semiconductor chip100.

The plurality of structures650are arranged so as not to be positioned directly beneath any of the apertures720of the heat dissipation structure700, thereby preventing the plurality of structures650from being damaged due to the cooling fluid CT flowing at high velocity through the apertures720.

In example embodiments, the plurality of structures650may be formed of metal. For example, the plurality of structures650may be formed using an electroplating process using, as a seed, the moisture absorption barrier layer610including a metal. The structures650may have various configurations and shapes and are not limited to the illustrated configuration and shape.

FIGS.8to11are cross-sectional views illustrating heat dissipation structures700A,700B,700C, and700D according to example embodiments of the inventive concept, respectively.FIGS.8to11respectively show cut surfaces of heat dissipation structures700A,700B,700C, and700D cut along the levels corresponding to the LV5 level ofFIG.1A. Hereinafter, the heat dissipation structures700A,700B,700C, and700D illustrated inFIGS.8to11will be described based on a difference of the heat dissipation structure700of the semiconductor package10described above with reference toFIGS.1A to1G.

Referring toFIG.8together withFIG.1A, in the heat dissipation structure700A, the inlet701and the outlet703may be provided on the upper surface100S of the first semiconductor chip100in a plan view. In this case, the cooling fluid (CT inFIG.4A) is first supplied to the region above the first semiconductor chip100, and then moves to the region above the second semiconductor chip200along the cooling channel710.

Referring toFIG.9together withFIG.1A, the heat dissipation structure700B may include a plurality of inlets701. The plurality of inlets701may be positioned so as not to overlie the first semiconductor chip100in a plan view. The plurality of inlets701may be arranged above the second semiconductor chip200or spaced apart from the second semiconductor chip200in an outward direction. The cooling fluid (CT inFIG.4A) may be provided to the cooling channel710through each of the plurality of inlets701.

In addition, the heat dissipation structure700B may include a plurality of outlets703. The plurality of outlets703may overlie the first semiconductor chip100in a plan view. The plurality of outlets703may be connected to the second cooling space820through different outflow channels750, and the cooling fluid CT of the second cooling space820may be discharged to the outside of the heat dissipation structure700B through the plurality of outlets703.

Referring toFIG.10together withFIG.1A, the cooling channel710of the heat dissipating structure700C may be a single channel that extends in a serpentine manner in a plan view. For example, the cooling channel710may include: a first sub-channel linearly extending in the second horizontal direction (e.g., Y direction) above the second semiconductor chips200provided on one side of the first semiconductor chip100(e.g., the left side of the first semiconductor chip100); a second sub-channel linearly extending in the second horizontal direction (e.g., the Y direction) above the first semiconductor chip100; a third sub-channel linearly extending in the second horizontal direction (e.g., in the Y direction) above the first semiconductor chip100and spaced apart from the second sub-channel in the first horizontal direction (e.g., in the X direction); a fourth sub-channel linearly extending in the second horizontal direction (e.g., Y direction) above the second semiconductor chips200provided on the other side of the first semiconductor chip100(e.g., the right side of the first semiconductor chip100); and connection channels for sequentially connecting the first to fourth sub-channels. Here, the first to fourth sub-channels may be spaced apart from each other in a first horizontal direction (e.g., X direction).

Referring toFIG.11together withFIG.1A, the semiconductor package10may include a plurality of first semiconductor chips100and a plurality of second semiconductor chips200. For example, in the semiconductor package10, two first semiconductor chips100may be arranged in a second horizontal direction (e.g., Y direction), and two second semiconductor chips200may be arranged at one side and the other side of each of the two first semiconductor chips100.

When the semiconductor package10includes a plurality of first semiconductor chips100, the first cooling spaces810may be separated or partitioned from each other by the separation wall800, and the first cooling spaces810may be connected to the outlet703through different outflow channels750and channels790. That is, the cooling fluid (CT inFIG.4A) may flow to the outlet703through the first cooling spaces810and the outflow channels750and then may be discharged to the outside of a heat dissipation structure700D.

The cooling channel710of the heat dissipation structure700D may extend in a serpentine configuration above all semiconductor chips provided in the semiconductor package10. For example, the cooling channel710may include: a first sub-channel linearly extending in the second horizontal direction (e.g., Y direction) above the second semiconductor chips200provided on one side of each of the first semiconductor chips100(e.g., the left side of each of the first semiconductor chips100); a second sub-channel linearly extending in the second horizontal direction (e.g., the Y direction) above the first semiconductor chips100; a third sub-channel linearly extending in the second horizontal direction (e.g., in the Y direction) above the first semiconductor chips100and spaced apart from the second sub-channel in the first horizontal direction (e.g., in the X direction); a fourth sub-channel linearly extending in the second horizontal direction (e.g., Y direction) above the second semiconductor chips200provided on the other side of each of the first semiconductor chips100(e.g., the right side of each of the first semiconductor chips100); and connection channels for sequentially connecting the first to fourth sub-channels. Here, the first to fourth sub-channels may be spaced apart from each other in a first horizontal direction (e.g., X direction).

FIGS.12A to12Gare cross-sectional views illustrating a method of manufacturing a semiconductor package10according to example embodiments. Hereinafter, referring toFIGS.12A to12G, a method of manufacturing the semiconductor package10described with reference toFIGS.1A to1Gand a method of configuring the cooling system CS of the semiconductor package10will be described.

Referring toFIG.12A, the first and second semiconductor chips100and200may be arranged on the interposer400.

The first semiconductor chip100and the second semiconductor chip200, which perform different functions, may be manufactured. The manufactured first and second semiconductor chips100and200may be mounted on the upper portion of the interposer400, and a molding layer300may be formed to surround the first and second semiconductor chips100and200.

Here, the molding layer300may expose the upper surfaces100S and200S of each of the first and second semiconductor chips100and200. Accordingly, the upper surface300S of the molding layer300may be coplanar with the upper surface100S of the first semiconductor chip100and the upper surface200S of the second semiconductor chip200.

The interposer400may serve to electrically connect the first semiconductor chip100and the second semiconductor chip200with each other. In addition, an internal connection terminal450may be formed below the interposer400.

Referring toFIG.12B, the interposer400on which the first and second semiconductor chips100and200are mounted may be arranged on the package substrate500.

The interposer400may be arranged on the package substrate500such that the internal connection terminal450arranged below the interposer400is electrically connected to the upper surface of the package substrate500.

An underfill UF may be formed between the interposer400and the package substrate500. The underfill UF may be between the interposer400and the package substrate500to surround the internal connection terminal450.

The package substrate500may include a printed circuit board. In the printed circuit board, the body portion501may be implemented by compressing, in a constant thickness, a polymer material, such as a thermosetting resin, or an epoxy resin such as a flame retardant 4 (FR-4), a bismaleimide triazine (BT), an Ajinomoto build up film (ABF), a phenol resin, or the like, to form a thin shape, and then forming a wiring which is a transmission path of an electrical signal through patterning after the copper foil is deposited on both sides.

Meanwhile, the printed circuit board may be divided into a single-sided PCB having a wiring formed only on one side and a double-sided PCB having a wiring formed on both sides. In addition, a PCB having a multi-layered structure may be implemented by forming three or more layers of copper foils using an insulator, which is referred to as a prepreg, and forming three or more wirings according to the number of layers of the copper foils.

Referring toFIG.12C, a moisture absorption barrier layer610is formed on the upper surface100S of the first semiconductor chip100, the upper surface200S of the second semiconductor chip200, and the upper surface300S of the molding layer300. The moisture absorption barrier layer610may be formed to entirely cover the upper surface300S of the molding layer300. In some embodiments, the moisture absorption barrier layer610may be formed to expose at least a portion of the upper surface100S of the first semiconductor chip100and/or at least a portion of the upper surface200S of the second semiconductor chip200.

Referring toFIG.12D, separation walls800are arranged on the moisture absorption barrier layer610. The moisture absorption barrier layer610may cover the upper surface300S of the molding layer300between the upper surface100S of the first semiconductor chip100and the upper surface200S of the second semiconductor chip200. As the separation walls800are arranged on the moisture absorption barrier layer610, a first cooling space810overlies the first semiconductor chip100and second cooling spaces820overlie the second semiconductor chip200may be formed.

Referring toFIG.12E, a sealing ring630is arranged on an outer portion of the moisture absorption barrier layer610, and a support structure620is arranged on the package substrate500. The sealing ring630is arranged between the support structure620and the moisture absorption barrier layer610so that a gap between the support structure620and the moisture absorption barrier layer610may be removed (i.e., the gap is filled by the sealing ring630).

Referring toFIGS.12F and12G, the heat dissipation structure700is arranged on the support structure620and the separation walls800. The heat dissipation structure700is inserted into a mounting groove provided on the upper side of the support structure620, and may cover the first cooling space810and the second cooling space820. When the arrangement of the heat dissipation structure700is completed, the cooling channel710of the heat dissipation structure700may communicate with the first cooling space810and/or the second cooling spaces820through the plurality of apertures720, and the outflow channel750of the heat dissipation structure700may communicate with the first cooling space810.

Referring toFIG.4A, in order to configure the cooling system CS for the semiconductor package10, the water cooling pump910may be connected to the inlet701of the heat dissipation structure700, and the heat dissipater920may be connected to the outlet703of the heat dissipation structure700. The water cooling pump910may be connected to the inlet701of the heat dissipation structure700through a pipe, and may supply the cooling fluid CT to the inlet701of the heat dissipation structure700. The heat dissipater920may be connected to the outlet703of the heat dissipation structure700through a pipe, collect the cooling fluid CT discharged through the outlet703of the heat dissipation structure700, and cool the cooling fluid CT. The cooling fluid CT provided by the water cooling pump910may flow along a flow path provided to the semiconductor package10to cool the semiconductor package10, and then may be collected to the heat dissipater920.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the following claims.