Interconnect structure, printed circuit board, semiconductor device, and manufacturing method for interconnect structure

An interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing the miniaturization of signal lines and increasing the film thickness. The interconnect structure includes a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an interconnect structure, printed circuit board, a semiconductor device, and a manufacturing method for the interconnect structure.

2. Description of the Related Art

An interconnect pattern formed on a semiconductor device or a printed circuit board needs to have a sectional area corresponding to the amount of current flowing through interconnects in order to prevent excessive heating of the interconnects during current conduction.

For example, in a power device or a control device, an interconnect pattern for a power supply system involving a large amount of current needs to have a large sectional area. However, an increase in interconnect width is limited.

A method for further increasing current capacity without increasing the interconnect width is to increase the thickness of the interconnects or to form a pattern by using a plurality of conductive layers in a multilayer board in parallel.

However, the method of increasing the thickness of the interconnects has the disadvantages of needing more time to plate the interconnects and precluding miniaturization based on a reduction in interconnect intervals between signal lines through which a large current need not flow.

The method of using a plurality of conductive layers in a multilayer circuit board in parallel is limited in the increase in the number of conductive layers.

Japanese Patent Publication No. H10-32201 describes photolithography masks used to form interconnect patterns and including a mask in which all interconnect patterns are drawn as mask patterns and a mask in which only interconnect patterns for large currents are drawn as mask patterns. These masks are used to form a thick interconnect pattern for a large amount of current, while forming a thin interconnect pattern for a small amount of current, thus allowing miniaturization.

In Japanese Patent Publication No. 2007-165642, a groove is formed in an insulating resin on an interconnect layer and filled with a conductive paste, and surfaces that are not in contact with the conductive paste are plated with copper. This increases the current capacity per unit width of pattern in one layer.

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

An object of the present invention is to provide an interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing a miniaturization of signal lines and increasing a film thickness.

To accomplish this object, an aspect of the present invention is configured as follows.

(1) An interconnect structure including:

a resin layer; and

interconnects formed on the resin layer, wherein

the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and

the interconnects are formed of a plating film created on a resin layer front surface in the area in which the interconnects are formed and on inner wall surfaces of the plurality of grooves.

(2) A printed circuit board including the interconnect structure set forth in (1).

(3) A semiconductor device including the interconnect structure set forth in (1).

(4) The semiconductor device according to (3), wherein the interconnects constituting the interconnect structure are in direct contact with a front surface of a semiconductor chip.

(5) A manufacturing method for an interconnect structure, the method including:

a step of forming a plurality of parallel grooves in a front surface of a resin layer in an area in which interconnects are formed; and

a step of forming a plating film on a resin layer front surface in an area in which the interconnects are formed and on inner wall surfaces of the plurality of grooves.

The interconnect structure in the present invention enables a partial increase in current capacity of the interconnects without an increase in the plating thickness of the interconnects. As a result, the plating time needed to obtain the desired current capacity can be reduced, thereby enhancing productivity.

Compared to a case where a plating thickness is increased, a reduced plating thickness of the present invention precludes a hindrance to the miniaturization of signal lines.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described below. The embodiments will be described below based on the drawings. However, the drawings are provided for description, and the present invention is not limited to the drawings.

FIG. 1Adepicts a basic example of an interconnect structure in the present invention.

The interconnect structure has a resin layer1and a plating film3constituting interconnects formed on the resin layer1. The resin layer1is formed on the core member10including conductive films10band10claminated on the respective opposite surfaces of a core plate10a.

FIG. 1Bis a diagram depicting a section of the resin layer1on which the plating film3is not yet formed. The resin layer1has a plurality of parallel grooves2in an area in which the plating film3is formed.

The plating film (interconnects)3is formed on inner wall surfaces1bof the grooves2and on resin layer front surfaces1ain the area where the interconnects are formed.

Such an interconnect structure is obtained by forming the plurality of parallel grooves2in the resin layer front surface1ain an area S of the resin layer1on the core member10where the interconnects are formed and forming the plating film3on the inner wall surfaces1bof the grooves2and the resin layer front surfaces1aas depicted inFIG. 1B.

InFIG. 1B, the inner wall surfaces of the grooves refer to side surfaces and bottom surfaces (conductive film10b) of the grooves.

Wiring formed of the plating film3as depicted inFIG. 1Ais hereinafter sometimes referred to as groove-shaped interconnects.

FIGS. 2A and 2Billustrate a comparison of an interconnect structure according to an embodiment of the present invention (seeFIG. 2A) with an interconnect structure that is not the embodiment of the present invention (seeFIG. 2B).

In the interconnect structure depicted inFIG. 2A, the plating film3is formed on side walls of the grooves2as well.

In the conventional interconnect structure depicted inFIG. 2B, the grooves2are not formed in the resin layer1, and the plating film3is formed only on the resin layer front surfaces1aof the resin layer1.

Wiring resistance is expressed by Equation (1).

A comparison of the interconnect structure depicted inFIG. 2Awith the interconnect structure depicted inFIG. 2Bindicates that, compared to the interconnect structure depicted inFIG. 2B, the interconnect structure depicted inFIG. 2Aincludes conductor portions formed of the plating film on the side surfaces of the grooves, with these conductor portions being enlarged with those of the interconnect structure depicted inFIG. 2B. Therefore, the interconnect structure depicted inFIG. 2Ahas a larger interconnect sectional area A and a lower interconnect resistance R in Equation (1) than the interconnect structure depicted inFIG. 2B.

The current that can pass through the interconnects is limited to the degree that the current is prevented from excessively elevating temperature. However, the interconnect structure in the embodiment of the present invention depicted inFIG. 2Ahas a lower interconnect resistance R, and thus, a reduced amount of heat is generated by the interconnects during current conduction. Consequently, a larger current can pass through the interconnect structure.

Now, an embodiment of the interconnect structure in the present invention will be described.

The present embodiment relates to a printed circuit board having the interconnect structure according to the present invention.

Steps for producing a printed circuit board having the interconnect structure depicted inFIGS. 1A and 1Bwill be described below based onFIGS. 3A to 3N.

The core member10is prepared which includes the conductive films10band10claminated on the respective opposite surfaces of the core plate10a.

An unwanted part of the conductive film10bon one side of the core member10is melted and removed with a chemical to form conductive patterns4a,4b, and4cneeded as interconnects.

FIG. 3Cis a top view of the core member10depicted inFIG. 3B.

Resin is accumulated on the core member10with the conductive patterns4a,4b, and4cformed thereon, to form a resin layer1.

On the resin layer1, grooving is performed in which the plurality of grooves2for large-current interconnects are formed and drilling is further performed in which via openings5for signal lines are formed. In the present embodiment, four grooves2are formed.

The drilling can be performed using a CO2laser or a THG laser. The grooving is preferably performed by excimer laser ablation.

When the grooves2and the via openings5are formed by laser processing, the conductive patterns4a,4b, and4care provided to control the depths of the grooves2and the via openings5. That is, if the laser light has an energy with a value equal to or smaller than a predetermined value, a conductive film forming the conductive patterns4a,4b, and4cacts as a barrier to stop the formation of the grooves2and the via openings5directly before the depth of the conductive patterns4a,4b, and4c(upper side of the figures).

FIG. 3Fis a top view of a laminated body including the core member10and the resin layer1depicted inFIG. 3E.FIG. 3Gis a sectional perspective view of the laminated body depicted inFIG. 3Fand is taken along line A-A′ inFIG. 3F.

FIG. 3Gillustrates that the conductive pattern4cat the bottom surfaces of the grooves2formed in the resin layer1is exposed.

Seeding is performed on inner wall surfaces of the grooves2, peripheral portions of the grooves2, the via openings5, and peripheral portions thereof in the laminated body depicted inFIG. 3E. Then, conductive films are formed by electroless plating, and vias7and interconnects6(interconnects6a,6b,6c, and6d) are formed by electroplating.

The interconnects6a,6b, and6care utilized as small-current conduction interconnects such as signal lines.

The interconnect6dis a groove-shaped interconnect and is utilized as a large-current conduction interconnect.

FIG. 3Iis a top view of the laminated body depicted inFIG. 3H.

FIG. 3Jis a sectional perspective view of the laminated body depicted inFIG. 3Iand is taken along line A-A′ inFIG. 3I.

A resin layer20is formed on an upper surface of the laminated body depicted inFIG. 3H.

Via openings8are formed, by laser processing, in the resin layer20in the laminated body depicted inFIG. 3K.

Via openings8in the laminated body depicted inFIG. 3Kand peripheral portions of the via openings8are plated to form vias11and interconnects9.

A solder resist film30is formed which includes exposed portions (interconnects9) serving as external connection pads. Thus, a printed circuit board is obtained.

The printed circuit board in the present embodiment includes the interconnect structure in the present invention and thus enables a partial increase in the current capacity of the interconnects without increasing the plating thickness. As a result, the plating time needed to obtain a desired current capacity can be reduced, enhancing the productivity. Compared to a case where a plating thickness is increased, the reduced plating thickness of the present invention precludes a hindrance to the miniaturization of signal lines.

The present embodiment relates to a semiconductor device that includes a power device or a control device embedded therein and interconnects formed by plating and in which the plated interconnects include connection structures according to the present invention.

The present embodiment will be described based onFIG. 4A.

Interconnects42are formed on a resin layer41a.

Semiconductor chips43aand43bare secured onto the interconnects42via insulating materials and sealed with a resin layer41b.

Interconnects45are formed on a front surface of the resin layer41bby plating.

On a front surface of the resin layer41b, vias44are formed which connect electrode pads for the semiconductor chips43aand43bto the interconnects45.

Vias44are also formed in the resin layer41bto electrically connect the interconnects42and the interconnects45together.

The interconnects45are embedded in a resin layer41c. The vias44and a groove-shaped interconnect47are formed in the resin layer41c.

Interconnects48are formed on a front surface of the resin layer41cby plating. On a front surface of the resin layer41c, a solder resist layer50is formed which has openings through each of which a part of the corresponding interconnect48is exposed.

The groove-shaped interconnect can be formed executing a series of steps illustrated inFIGS. 3D to 3Jon the resin layer41c.

The steps of forming the groove-shaped interconnect will be described below.

The interconnects45are formed on the surface of resin layer41bsealing the semiconductor chips43aand43b.

The resin layer41cis accumulated on the interconnects45.

As depicted inFIG. 4B, on the resin layer41c, drilling is further performed in which via openings5for signal lines are formed and grooving is performed in which the plurality of grooves2for large-current interconnects are formed.

The via openings5, peripheral portions of the via openings5, and inner wall surfaces and peripheral portions of the grooves2are plated to form the vias44, the interconnects48, and the groove-shaped interconnect47.

The interconnects48produced as described above are utilized as small-current conduction interconnects such as signal lines. The groove-shaped interconnect47is utilized as a large-current conduction interconnect.

The present embodiment produces effects similar to the effects of Embodiment 1 on a semiconductor device with interconnects formed by plating.

The present embodiment relates to a semiconductor device that includes a power device or a control device embedded therein and interconnects formed by plating and in which the plated interconnects include connection structures according to the present invention.

As depicted inFIG. 5A, the semiconductor device in the present embodiment is structured such that the groove-shaped interconnect47is in direct contact with the semiconductor chip43a.

To form such an interconnect structure, first, grooves2are formed which extend from a front surface of the resin layer41bwith semiconductor chips43aand43bsealed therein and which reach a front surface of the semiconductor chip43a, and openings5are formed which also extend from the front surface of the resin layer41band which reach front surfaces of the interconnects42, as depicted inFIG. 5B.

Normally, Al pads, SiN, and the like are exposed from the front surfaces of the semiconductor chips43a. If a CO2laser is used to form the grooves2, when the semiconductor chips are irradiated directly with CO2laser light, prevention of damages to the semiconductor chip43ais difficult.

However, since the etch rate of Al pads or SiN is lower and involves higher etch selectivity than the etch rate of a resin, processing can be stopped at the front surfaces of the Al pads or SiN when an excimer laser is used for drilling that allows via openings to be formed and for grooving. Furthermore, ablation processing such as this has only a low thermal effect on the semiconductor chips. Thus, as a laser, an excimer laser is preferably used.

After the grooves2and the via openings5depicted inFIG. 5Bare formed, the via openings5, peripheral portions of the via openings5, inner wall surfaces and peripheral portions of the grooves2are plated to form the vias44, the interconnects45, and the groove-shaped interconnect47.

Then, the resin layer41cis accumulated on the vias44and the groove-shaped interconnect47. The vias44are formed in the resin layer41c, and the interconnects48are formed on a front surface of the resin layer41c.

Then, the solder resist layer50is formed which has openings through each of which a part of the corresponding interconnect layer is exposed on the surface of the resin layer41c. Compared to Embodiment 2, Embodiment 3 eliminates the need to further increase interconnects in order to allow groove-shaped interconnects to be produced, thereby enabling the provision of a semiconductor device with a reduced number of layers.