Chip package and manufacturing method thereof

A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.

BACKGROUND

Field of Invention

The present invention relates to a chip package and a manufacturing method of the chip package.

Description of Related Art

Generally, in manufacturing a chip package of an image sensor, a light transmissive substrate is disposed on a surface of a wafer, and a dam element is used to separate the light transmissive substrate and the wafer with a gap.

Thereafter, an etching process may be performed on the wafer to form a through silicon via (TSV), and then a conductive layer is formed on the wafer, such that the conductive layer may be connected to a conductive pad that is in the through silicon via. Subsequently, a cutter is utilized to cut the wafer and the light transmissive substrate in a vertical direction, thereby forming plural image sensors.

However, since the cutter dices the wafer and the light transmissive substrate, a region of the wafer for being cut by the cutter needs to be reserved. As a result, after the wafer and the light transmissive substrate are cut by the cutter, a distance between an edge of the wafer formed by cutting and the through silicon via is large, and it is difficult to reduce the packaging volume of the chip package, and the type of the through silicon via is limited by the distance. Moreover, through cutting the wafer by the cutter, the strength and reliability of the chip package are reduced, and the electric leakage of the chip package is prone to occur.

SUMMARY

An aspect of the present invention is to provide a chip package.

According to an embodiment of the present invention, a chip package includes a light transmissive substrate, a chip, and a dam element. The chip has a conductive pad, a hollow region, a trench, a first surface, and a second surface that faces away from the first surface. The conductive pad is located on the first surface and exposed through the hollow region, and the hollow region is at one side of the trench and selectively communicated with the trench. The dam element between the light transmissive substrate and the first surface of the chip and covers the hollow region and the trench.

In one embodiment of the present invention, when the hollow region is not communicated with the trench, the chip has at least one sidewall that surrounds the hollow region.

In one embodiment of the present invention, the top view shape of the sidewall includes square, elongated, circular, elliptical, or a combination thereof.

In one embodiment of the present invention, the height of the sidewall is smaller than or equal to a distance that is between the first and second surfaces.

In one embodiment of the present invention, when the hollow region is communicated with the trench, the chip has at least one sidewall that faces the hollow region. The top view shape of the sidewall includes U-shaped, semicircular, semi-elliptical, or a combination thereof. The hollow region has an opening that faces the trench.

In one embodiment of the present invention, the chip package further includes an isolation layer. The isolation layer is located on the second surface of the chip and the sidewall of the chip facing the hollow region.

In one embodiment of the present invention, the chip package further includes a redistribution layer. The redistribution layer is located on the isolation layer and electrically connected to the conductive pad.

In one embodiment of the present invention, the chip package further includes a protection layer. The protection layer is located on the redistribution layer and in the hollow region and the trench.

In one embodiment of the present invention, the protection layer has an opening, and the redistribution layer is exposed through the opening. The chip package further includes a conductive protrusion. The conductive protrusion is located on the redistribution layer that is in the opening of the protection layer.

Another aspect of the present invention is to provide a manufacturing method of a chip package.

According to an embodiment of the present invention, a manufacturing method of a chip package includes the following steps. (a) A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. (b) A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench that is selectively communicated with the hollow region are synchronously formed in the wafer. (c) A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.

In one embodiment of the present invention, when the hollow region is not communicated with the trench, step (b) includes forming at least one sidewall of the wafer surrounding the hollow region, and the top view shape of the sidewall includes square, elongated, circular, elliptical, or a combination thereof.

In one embodiment of the present invention, step (b) includes forming the sidewall with a height that is smaller than or equal to a distance that is between the first and second surfaces.

In one embodiment of the present invention, when the hollow region is communicated with the trench, step (b) includes forming at least one sidewall of the wafer facing the hollow region, and the top view shape of the sidewall includes U-shaped, semicircular, semi-elliptical, or a combination thereof, and the hollow region has an opening that faces the trench.

In one embodiment of the present invention, the manufacturing method further includes forming a second isolation layer on the second surface of the wafer and a sidewall of the wafer facing the hollow region.

In one embodiment of the present invention, the manufacturing method further includes forming a redistribution layer on the second isolation layer and the conductive pad.

In one embodiment of the present invention, the manufacturing method further includes forming a protection layer on the redistribution layer and in the hollow region and the trench.

In one embodiment of the present invention, the manufacturing method further includes forming an opening in the protection layer and forming a conductive protrusion on the redistribution layer that is in the opening of the protection layer.

In one embodiment of the present invention, the manufacturing method further includes cutting the protection layer, the dam element, and the light transmissive substrate in a vertical direction, thereby forming a plurality of chip packages.

In the aforementioned embodiments of the present invention, etching synchronously forms the hollow region and the trench of the wafer, and thus the trench may be selectively communicated with the hollow region through process control. As a result, a distance between the hollow region and the trench may be reduced, and the hollow region may have different types of variation through an etching process. Moreover, since a cutter does not cut the wafer, the strength and reliability of the chip package may be improved, and the electric leakage of the chip package does not easily occur.

DETAILED DESCRIPTION

FIG. 1is a flow chart of a manufacturing method of a chip package according to one embodiment of the present invention. In step S1, a light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. Thereafter in step S2, a second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench that is selectively communicated with the hollow region are synchronously formed in the wafer. Subsequently in step S3, a first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region. In the following description, the aforesaid steps of the manufacturing method of the chip package will be described.

FIG. 2is a cross-sectional view of a light transmissive substrate110after being bonded to a wafer120according to one embodiment of the present invention. The light transmissive substrate110may be bonded to a first surface122of the wafer120, such that a dam element130between the light transmissive substrate110and the wafer120covers a conductive pad126of the wafer120. Before the light transmissive substrate110is bonded to the wafer120, the dam element130may be disposed on the light transmissive substrate110or the wafer120as deemed necessary by designers. In this embodiment, the wafer120may be made of a material including silicon, such as a silicon wafer, which is not yet diced to form plural chips by a cutting process. Image sensors may be manufactured from the wafer120. The conductive pad126may be made of a material including aluminum. The light transmissive substrate110may be made of a material including glass, plastic, or acrylic. However, the present invention is not limited to the aforementioned materials.

FIG. 3is a cross-sectional view of a hollow region121and a trench123that is communicated with the hollow region121after being formed in the wafer120shown inFIG. 2. As shown inFIG. 2andFIG. 3, after the light transmissive substrate110is bonded to the wafer120, a second surface124of the wafer120facing away from the first surface122may be etched, such that the hollow region121and the trench123that is selectively communicated with the hollow region121are synchronously formed in the wafer120. The hollow region121of the wafer120is referred to as a region that can expose the conductive pad126, such as a region under the conductive pad126shown inFIG. 3. The trench123of the wafer120is referred to as a region that can be cut by a cutter in a subsequent cutting (dicing) process. In this embodiment, the hollow region121is communicated with the trench123, but in another embodiment, the hollow region121may be not communicated with the trench123, is separated from the trench123, as shown inFIG. 6.

FIG. 4is a cross-sectional view of a first isolation layer140on the conductive pad126after being etched shown inFIG. 3. As shown inFIG. 3andFIG. 4, after the hollow region121and the trench123that is communicated with the hollow region121are formed in the wafer120, the first isolation layer140on the conductive pad126may be etched, such that the conductive pad126is exposed through the hollow region121. As a result, a semiconductor structure100amay be obtained. The semiconductor structure100aincludes the light transmissive substrate110, the wafer120, and the dam element130. The wafer120has the conductive pad126, the hollow region121, the trench123, the first surface122, and the second surface124that faces away from the first surface122. The conductive pad126is located on the first surface122and exposed through the hollow region121. The hollow region121is at one side of the trench123and selectively communicated with the trench123. The dam element130is between the light transmissive substrate110and the first surface122of the wafer120and covers the hollow region121and the trench123.

FIG. 5is a perspective view of the semiconductor structure100ashown inFIG. 4, in which the perspective view is from the second surface124of the wafer120. As shown inFIG. 4andFIG. 5, when the wafer120is etched to form the hollow region121and the trench123that is communicated with the hollow region121, at least one sidewall127of the wafer120facing the hollow region121may be formed. The top view shape of the sidewall127includes U-shaped, semicircular, semi-elliptical, or a combination thereof. In this embodiment, the top view shape of the sidewall127is U-shaped. The hollow region121has an opening125that faces the trench123, such that the position of the conductive pad126can be adjacent to the trench123. Hence, the miniaturizing design of the semiconductor structure100amay be improved.

Since etching synchronously forms the hollow region121and the trench123of the wafer120, the trench123may be selectively communicated with the hollow region121through process control. As a result, a distance between the hollow region121and the trench123may be reduced, and the hollow region121may have different types of variation through an etching process. Moreover, due to the reduced distance between the hollow region121and the trench123, space of the wafer120for designing lines outside of the hollow region121and the trench123may be increased, such that the layout of the lines is in a significantly adjustable manner.

FIG. 6is another embodiment ofFIG. 4.FIG. 7is a perspective view of a semiconductor structure100bshown inFIG. 6, in which the perspective view is from the second surface124of the wafer120. As shown inFIG. 6andFIG. 7, the semiconductor structure100bincludes the light transmissive substrate110, the wafer120, and the dam element130. The difference between this embodiment and the embodiment shown inFIGS. 4 and 5is that the hollow region121is not communicated with the trench123. When the wafer120is etched to form the hollow region121and the trench123that is not communicated with the hollow region121, at least one sidewall127of the wafer120surrounding the hollow region121may be formed, and the top view shape of the sidewall127may include square, elongated, circular, elliptical, or a combination thereof. In this embodiment, the top view shape of the sidewall127is square, and the height H1of the sidewall127is substantially equal to the distance H2that is between the first and second surfaces122,124.

Since subsequent processes for the semiconductor structure100aofFIG. 4are similar to that for the semiconductor structure100bofFIG. 6, only the semiconductor structure100aofFIG. 4is used as an example to describe in the following description.

FIG. 8is a cross-sectional view of a second isolation layer150after being formed on the wafer120shown inFIG. 4. As shown inFIG. 4andFIG. 8, after the conductive pad126is exposed through the hollow region121, the second isolation layer150may be formed on the second surface124of the wafer120and the sidewall127of the wafer120facing the hollow region121.

FIG. 9is a cross-sectional view of a redistribution layer160and a protection layer170after being formed on the second isolation layer150and the conductive pad126shown inFIG. 8. As shown inFIG. 8andFIG. 9, after the second isolation layer150is formed on the wafer120, the redistribution layer160may be formed on the second isolation layer150and the conductive pad126, such that the redistribution layer160is electrically connected to the conductive pad126. The redistribution layer160may include metal layers162,164. When the metal layer162is aluminum, the metal layer164may be gold. Alternatively, when the metal layer162is titanium, the metal layer164may be copper. Sputtering may be used to form titanium, and electroplating may be used to form copper. After the redistribution layer160is formed on the second isolation layer150and the conductive pad126, the protection layer170may be formed on the redistribution layer160and in the hollow region121and the trench123. Thereafter, the protection layer170may be patterned to form an opening172, such that the redistribution layer160is exposed through the opening172of the protection layer170.

FIG. 10is a cross-sectional view of a conductive protrusion180after being formed on the redistribution layer160shown inFIG. 9. As shown inFIG. 9andFIG. 10, after the opening172is formed in the protection layer170, the conductive protrusion180may be formed on the redistribution layer160that is in the opening172of the protection layer170, such that the conductive protrusion180may be electrically connected to the conductive pad126through the redistribution layer160. The conductive protrusion180may be solder ball, and the present invention is not limited to the shape and material of the conductive protrusion180.

After the conductive protrusion180is formed on the redistribution layer160, the protection layer170, the dam element130, and the light transmissive substrate110may be cut in a vertical direction along the trench123(i.e., along line L), such that the semiconductor structure100aofFIG. 9is divided to form plural chip packages102a. The chip package102amay be an image sensing chip, such as a CMOS element, but the present invention is not limited in this regard. Since a cutter does not cut the wafer120, the strength and reliability of the chip package102amay be improved, and the electric leakage of the chip package102adoes not easily occur.

The chip package102ais a portion of the semiconductor structure100aafter the semiconductor structure100ais cut, so that the chip package102ahas the same structure as the semiconductor structure100a. The chip package102aincludes the light transmissive substrate110, the chip120, and the dam element130. The chip120is referred to as a piece of the wafer120ofFIG. 9after being divided. The chip120has the conductive pad126, the hollow region121, the trench123, the first surface122, and the second surface124that faces away from the first surface122. The conductive pad126is located on the first surface122and exposed through the hollow region121. The hollow region121is at one side of the trench123and selectively communicated with the trench123. The dam element130is between the light transmissive substrate110and the first surface122of the chip120and covers the hollow region121and the trench123. In this embodiment, the hollow region121is communicated with the trench123.

Furthermore, the second isolation layer150, the redistribution layer160, the protection layer170, and the conductive protrusion180may also be formed on the semiconductor structure100bofFIG. 6. That is to say, in the structure ofFIG. 9, the semiconductor structure100aofFIG. 4may be replaced by the semiconductor structure100bofFIG. 6. After the dam element130and the light transmissive substrate110are cut along the trench123, another chip package of another embodiment may be obtained, and the hollow region121is not communicated with the trench123in such chip package.

It is to be noted that the connection relationships and materials of the elements described above will not be repeated in the following description, and only aspects related to other types of semiconductor structures will be described. Since plural chip packages may be formed by cutting a semiconductor structure along the trench, each of the semiconductor structures shown inFIGS. 5, 7, 11A to 11C, and 12A to 12Dmay be referred to as at least two chip packages that are connected with each other. That is to say, each of the chip packages has the same structure as the corresponding semiconductor structure, and the chip of each of the chip packages also has the same structure as the wafer of the corresponding semiconductor structure.

FIGS. 11A to 11Care other embodiments of the semiconductor structure100ashown inFIG. 5. The difference between a semiconductor structure100cofFIG. 11Aand the semiconductor structure100aofFIG. 5is that the top view shape of the sidewall127of the wafer120facing the hollow region121show inFIG. 11Ais semicircular.

The difference between a semiconductor structure100dofFIG. 11Band the semiconductor structure100aofFIG. 5is that the width W1of the sidewall127between two adjacent hollow regions121show inFIG. 11Bis smaller than the width W2of the sidewall127between two adjacent hollow regions121show inFIG. 5. Hence, two adjacent conductive pads126ofFIG. 11Bare closer, such that the density of lines may be improved.

The difference between a semiconductor structure100eofFIG. 11Cand the semiconductor structure100aofFIG. 5is that the top view shape of the sidewall127of the wafer120facing the hollow region121show inFIG. 11Cincludes semicircular and semi-elliptical. In this embodiment, the sidewall127at the right side of the trench123can separate the conductive pads126that are used to sending different signals.

FIGS. 12A to 12Dare other embodiments of the semiconductor structure100bshown inFIG. 7. The difference between a semiconductor structure100fofFIG. 12Aand the semiconductor structure100bofFIG. 7is that the height H3of the sidewall127of the wafer120ofFIG. 12Ais smaller than the height H1of the sidewall127of the wafer120ofFIG. 7(i.e., the distance H2between the first and second surfaces122,124shown inFIG. 6). Moreover, the width between the hollow region121and the trench123shown inFIG. 12Ais smaller than the width W3between the hollow region121and the trench123shown inFIG. 7, such that the position of the conductive pad126ofFIG. 12Acan be more adjacent to the trench123, and space of the wafer120for designing lines may be increased.

The difference between a semiconductor structure100gofFIG. 12Band the semiconductor structure100bofFIG. 7is that the top view shape of the sidewall127of the wafer120facing the hollow region121show inFIG. 11Bis circular.

The difference between a semiconductor structure100hofFIG. 12Cand the semiconductor structure100bofFIG. 7is that the width W1of the sidewall127between two adjacent hollow regions121show inFIG. 12Cis smaller than the width W4of the sidewall127between two adjacent hollow regions121show inFIG. 7. Hence, two adjacent conductive pads126ofFIG. 12Care closer, such that the density of lines may be improved.

The difference between a semiconductor structure100iofFIG. 12Dand the semiconductor structure100bofFIG. 7is that the top view shape of the sidewall127of the wafer120facing the hollow region121show inFIG. 12Dincludes circular and elliptical. In this embodiment, the sidewall127at the right side of the trench123can separate the conductive pads126that are used to sending different signals.