Low energy processor for controlling operating states of a computer system

Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.

BACKGROUND

Technical Field

Embodiments described herein relate to computing systems, and more particularly, to techniques adjusting performance settings for functional units within the computing system.

Description of the Related Art

Computing systems may include one or more systems-on-a-chip (SoC), which may integrate a number of different functions, such as, e.g., graphics processing, onto a single integrated circuit. With numerous functions included in a single integrated circuit, chip count may be kept low in mobile computing systems, such as tablets, for example, which may result in reduced assembly costs, and a smaller form factor for such mobile computing systems.

Within an SoC, different regions or functional units may operate at different clock frequencies (functional blocks operating at different clock frequencies are commonly referred to as being in different “clock domains”). For example, functional units coupled to external interfaces may operate at a clock frequency commensurate with the needs of such external interfaces, while other functional units may be designed to function at a highest clock frequency possible for a given semiconductor manufacturing process. Other functional units may include logic circuits operating at different clock frequencies, while some functional units may also allow for varying clock frequencies over time dependent upon work load.

Additionally, within an SoC, different regions or functional units may employ different internal power supplies, each of which may be at a different voltage level. For example, certain analog and Input/Output (I/O) circuits may require voltage levels higher than other digital circuit units. The SoC may include circuits, such as voltage regulators, e.g., configured to generate the internal power supplies.

During operation, voltage levels of the internal power supplies may be adjusted dependent upon performance or power requirements. For example, during periods of reduced activity within the SoC, voltage levels of one or more of the internal power supplies may be reduced to inactive portions of the SoC to reduce leakage power consumption. Alternatively or additionally, frequencies of internal clock signals may also be adjusted.

SUMMARY OF THE EMBODIMENTS

Various embodiments of a method and apparatus for tuning delay in a circuit path are disclosed. Broadly speaking, an apparatus and a method are contemplated in which, a system includes one or more functional units. At least one functional unit includes a monitor circuit that is configured to monitor an operational parameter associated with its corresponding functional unit. The monitor circuit is further configured to send data indicative of the operational parameter to a power manager processor. The power manager processor may be configured to receive the data, and adjust one or more performance settings dependent upon the received data.

In one embodiment, the power manager processor may be configured to exit a low power mode. The power manager processor may exit the low power mode after a first time period has elapsed since the power manager processor entered the low power mode.

In a further embodiment, each monitor circuit may be further configured generate an interrupt. The power manager processor may be further configured to exit the low power mode responsive to the interrupt.

DETAILED DESCRIPTION OF EMBODIMENTS

In computing systems, the execution of different applications may result in different levels of activity for various functional units within the computing system. For example, for various video related applications, a Graphics Processing Unit (GPU) and its associated memory may have a high level of activity, while other functional units, such as, e.g., an Input/Output (I/O) unit may have minimal activity. In such cases, the performance of the active components of the computing system may be adjusted to provide additional processing speed or the like. Such adjustments may involve increasing or decreasing a voltage level of a power supply to active functional units. In some cases, a change in a frequency of a clock signal may accompany, or be in lieu of, the changes in the voltage level of the power supply.

Adjustments to the performance of a functional unit within a computing system may be based on events within the functional unit, such as changes in temperature, a level of activity within the functional unit, or any other suitable metric. A main processor or CPU may, as instructed by an operating system, track such events, and adjust system performance accordingly. However, the main processor may have other tasks to handle, resulting in a lag to respond to the aforementioned events, as well as the power consumed in switching processing contexts to respond to the event. The embodiments illustrated in the drawings and described below may provide techniques for quickly adjusting performance settings within a computing system while limiting additional power consumption.

A block diagram of an integrated circuit is illustrated inFIG. 1. In the illustrated embodiment, the integrated circuit100includes a processor101coupled to memory unit102, and analog/mixed-signal unit103, and I/O block104through internal bus105(also referred to herein as a “switch fabric”). Integrated circuit100also includes power manager processor106, memory unit102, and monitor circuits107a-c. In various embodiments, integrated circuit100may be configured for use in a desktop computer, server, or in a mobile computing application such as, e.g., a tablet or laptop computer.

Processor101may, in various embodiments, be representative of a general-purpose processor that performs computational operations. For example, processor101may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). In some embodiments, processor101may execute program instructions, which may be stored in memory unit102to perform various computational tasks. Processor101may, in some embodiments, perform primary computation tasks, such as, e.g., executing operating system instructions, for integrated circuit100.

Memory unit102may include any suitable type of memory such as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), a Read-only Memory (ROM), Electrically Erasable Programmable Read-only Memory (EEPROM), or a FLASH memory, for example. It is noted that in the embodiment of an integrated circuit illustrated inFIG. 1, a single memory unit is depicted. In other embodiments, any suitable number of memory blocks may be employed.

Memory unit102may include various circuit blocks such as decoders, data storage cells, and the like. Memory unit102may also include monitor circuit107a. In various embodiments, monitor circuit107may be configured to monitor or track an operating parameter associated with memory unit102. For example, monitor circuit107amay track a temperature of integrated circuit100at a location near memory unit102. Monitor circuit107amay, in other embodiments, include counters or other suitable state machines capable of tracking accesses to and responses from memory unit102. In some embodiments, monitor circuit107amay be configured to detect an event, i.e., a specific condition related to the monitor operational parameter, and, in response to the event, generate an interrupt for power manager processor106. Monitor circuit107amay also be configured to store data related to the monitored operational parameter, and send the data to power manager processor106. It is noted that although a single monitor circuit is illustrated inFIG. 1, in other embodiments any suitable number of monitor circuits may be employed.

Monitor circuits, such as those described herein, may also be configured to enter a power down or reduced power state dependent upon operating conditions with a computing system. In some embodiments, an operational state of one monitor circuit may depend on data received from one or more other monitor circuits. For example, a monitor circuit configured to detect variations in a voltage level of a power supply may be disabled for certain temperature ranges as measured by another monitor circuit. In various embodiments, a power manager processor, such as is described below in regard toFIG. 2, may control an operational state of multiple monitor circuits.

Analog/mixed-signal unit103may include a variety of circuits including, for example, a crystal oscillator, a phase-locked loop (PLL), an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC) (all not shown). In other embodiments, analog/mixed-signal unit103may be configured to perform power management tasks with the inclusion of on-chip power supplies and voltage regulators. Analog/mixed-signal block103may also include, in some embodiments, radio frequency (RF) circuits that may be configured for operation with wireless networks. Analog/mixed signal unit103may also include monitor circuit107bwhich may include some or all of the functionality described above in regard to monitor circuit107a.

I/O unit104may be configured to coordinate data transfer between integrated circuit100and one or more peripheral devices. Such peripheral devices may include, without limitation, storage devices (e.g., magnetic or optical media-based storage devices including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral devices. In some embodiments, I/O block104may be configured to implement a version of Universal Serial Bus (USB) protocol or IEEE 1394 (Firewire®) protocol. I/O unit104may also include monitor circuit107cwhich may include some or all of the functionality described above in regard to monitor circuit107a.

I/O block104may also be configured to coordinate data transfer between integrated circuit100and one or more devices (e.g., other computer systems or integrated circuits) coupled to integrated circuit100via a network. In one embodiment, I/O unit104may be configured to perform the data processing necessary to implement an Ethernet (IEEE 802.3) networking standard such as Gigabit Ethernet or 10-Gigabit Ethernet, for example, although it is contemplated that any suitable networking standard may be implemented. In some embodiments, I/O unit104may be configured to implement multiple discrete network interface ports.

Power manager processor106may, in various embodiments, be representative of a general-purpose processor that performs computational operations. For example, power manager processor106may be a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA), or any suitable processing engine. As described below, in more detail in regard toFIG. 2, power manager processor106may include a dedicated memory. Program instructions included in one or more control loops for execution by power manager processor106may be stored in the dedicated memory. By retrieving program instructions from the dedicated memory, power manager processor may, in various embodiments, be able to process interrupts with minimal latency, and not consume system resources being used by an operating system or other software applications.

In some embodiments, power manager processor106may include interrupt interface108configured to receive interrupts from one or more monitor circuits, such as, monitor circuits107a-c, for example. Interrupt interface108may remain active during periods when other portions of power manager processor106are in a low power mode. Upon receiving an interrupt, power manager processor may exit the low power mode in order to execute the program instructions included in the control loops. In some embodiments, by employing a low power mode when not in use, the power manager processor may perform adjustments to performance settings of integrated circuit100with a minimal impact on overall power consumption of the integrated circuit.

Power manager processor106may, in some embodiments, receive data from a monitor circuit, such as, e.g., monitor circuit107a, via communication bus105. In some circumstances, however, using communication bus105for transmission of monitor circuit data may interfere with a measurement made by a monitor circuit. For example, a monitor circuit configured to measure activity on communication bus105and relay the measured activity via communication bus105would affect the measurement of bus activity by transmitting additional data via communication bus105. In such cases, direct interface109may be employed to allow monitor circuit107ato directly report measurement results to power manager processor106.

It is noted that although power manager processor106is depicted as being part of integrated circuit100, in other embodiments, power manager processor106may be included on a separate integrated circuit within a computing system. In some embodiments, power manager processor106may be physically located near, or included within a power manager unit (PMGR). The PMGR may be included in integrated circuit100or, in other embodiments, on a different integrated circuit. By locating power manager processor106near the PMGR, the overhead associated with accessing data, program instructions, and the like, stored in the PMGR.

Turning toFIG. 2, an embodiment of a power manager processor is illustrated. In the illustrated embodiment, power manager processor200includes processor core201coupled to memory202. In various embodiments, power manager processor200may correspond to power manager processor106as illustrated inFIG. 1, and may be dedicated to handle interrupts in order to perform power management operations. Although only a single instance of a memory is depicted in the embodiment illustrated inFIG. 2, in other embodiments, any suitable number of memories may be employed.

In various embodiments, processor core201may be a general-purpose processor that executes program instructions. For example, processor core201may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). Processor core201may, in various embodiments, be coupled to other functional units, such as, I/O block104as illustrated inFIG. 1through an internal bus or other suitable communication network. In other embodiments, processor core may be coupled to functional units via a direct interface. For example, processor core201may be coupled to a power management unit (PMU) and clock generation circuitry by respective direct dedicated interfaces.

In some embodiments, only a small portion of processor core201may be active, and upon detection of an interrupt from a monitor circuit, all portions of processor core201may become active in order to execute program instructions. Processor core201may, in other embodiments, return to an active state at various times in order to monitor data received from different monitor circuits. For example, processor core201may become active every 10 ms to receive data from a monitor circuit configured to measure temperature, and then return to a low power state. In other embodiments, processor core201may include multiple timers (not shown), each configured to indicate the passage of various time periods for monitoring different events.

Memory202may, in various embodiments, include any suitable type of memory such as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or any other suitable memory type. In some embodiments, memory202may be coupled to a separate power supply than processor core201. By employing a separate power supply for memory202, data, such as, e.g., program instructions, may be retained in memory202even when power has been removed from processor core201. Memory202may, in some embodiments, employ a retention mode, in which power is supplied to only the memory cells in memory202to maintain the stored data while reducing power consumption due to leakage in peripheral circuits of memory202

During operation, processor core201may execute program instructions stored in memory202. Such program instructions may include instructions to retrieve data (also referred to as “telemetry”) from one or more monitor circuits, such as, monitor circuit107as illustrated inFIG. 1. It is noted, one or more monitor circuits may provide telemetry via an I/O interface, from another chip with in a computing system, such as, e.g., a Power Management Unit (PMU). The I/O interface may, in various embodiments, include any suitable interface, such as I2C, UART, and the like. The data may be retrieved at regular intervals, or in response to receiving an interrupt from a given monitor circuit. In some embodiments, the retrieved data may be stored in memory202for further processing or analysis.

In various embodiments, the program instructions stored in memory202may also include instructions to track received data from one or more monitor circuits. The program instructions may, in some embodiments, include separate sets of instructions (also referred to as “loops” or “control loops”) that may be repeatedly executed by processor core201to analyze data received from a given monitor circuit. Such loops may also include instructions that adjust various voltage and frequency settings (commonly referred to as “performance settings”) that affect operational capability of a given functional unit within a computing system. For example, in reference toFIG. 1, a loop monitoring processor101may detect that the processor101has to repeatedly wait for memory102. In such cases, processor core201may, in response to instructions included in the loop, send a signal to a power management and clock unit to increase a voltage of the power supply to the memory, or increase a frequency of a clock signal provided to memory102, or both, thereby increasing the performance of memory102.

Processor core201may, in some embodiments, monitor, using received telemetry, memory throughput, memory latency, and switch fabric activity. The aforementioned control loops may adjust a frequency or performance level of switch fabric or memory in order to reduce latency, increase memory throughput, or reduce contention within the switch fabric.

It is noted that the embodiment illustrated inFIG. 2is merely an example. In other embodiments, the program instructions stored in memory202may be updated or changed in response to variations in operating mode, physical operating conditions of the system, and the like.

Turning toFIG. 3, a flow diagram depicting an embodiment of a method for adjusting performance of a system is illustrated. Referring collectively toFIG. 1and the flow diagram ofFIG. 3, the method begins in block301.

Monitor circuit107amay then monitor an operating parameter of memory unit102(block302). In some embodiments, monitor circuit107amay monitor a voltage level of a power supply, temperature, number of accesses to memory unit102, or any other suitable metric. It is noted that although only a single monitor circuit is shown inFIG. 1, other embodiments may include multiple monitor circuit operating in parallel. Moreover, a functional unit may include multiple monitor circuits, each of which may be configured to monitor a different operating parameter within the functional unit. In some embodiments, multiple monitor circuits may be coupled to bus105to track different transactions or numbers of a specific transaction on bus105.

The method may then depend on if an event occurs (block303). Monitor circuit107amay detect an event based on the monitoring of the operating parameter. For example, an event may, in some embodiments, include a change in temperature, operating voltage, or the like. Alternatively, the event may include a particular type of access to a functional unit, e.g., a write access, or when a number of accesses to the functional unit exceeds a predetermined value. In some embodiments, the event may include an access to the functional unit from another specific functional unit within a computing system, such as, integrated circuit100, for example.

When no event is detected, monitor circuit107acontinues to monitor the operating parameter as described above in regards to block302. If an event is detected, then the method may depend on the power state of power manager processor106(block304). If power manager processor is in a power off or reduced power state, monitor circuit107amay assert an interrupt (block305). The interrupt may be sent to power manager processor106through bus105. In other embodiments, monitor circuit107amay have a direct connection (not shown) to power manager processor106allowing the interrupt to be sent directly to power manager processor106. If power manager processor106is operating in an active mode, then the method may proceed as described below from block307.

In response to the asserted interrupt, power manager processor106may exit from a low power (also referred to as a “sleep mode”) and return to an active mode (block306). While in the low power mode, a voltage level of a power supply to portions of power manager processor106may be at ground potential, thereby reducing leakage power consumption. Additionally, or alternatively, a clock signal to portions of power manager processor106may be stopped (commonly referred to as “clock gating”), thereby reducing dynamic power. While in the low power mode, a portion of power manager processor106may remain operational to detect the occurrence of interrupts or other system related events. Upon detection of an interrupt, the active portion of power manager processor106may re-activate the inactive portions of power manager processor106, thereby allowing the resumption of processing activities. In various embodiments, by employing a low power mode for power manager processor106, the power consumed to monitor system performance and adjust performance settings may be minimized.

Power manager processor106may then execute a control loop (block307) to adjust performance settings. The control loop may be related to the event that trigger the interrupt, and may include one or more program instructions. Such program instructions may be stored in a memory dedicated to power manager processor106, such as, e.g., memory202as illustrated inFIG. 2. Power manager processor106may retrieve the program instructions from the dedicated memory prior to execution. As described below in more detail in regard toFIG. 4, the program instructions may include instructions for retrieving data from a monitor circuit, performing an analysis of the retrieved data, and adjusting performance setting of the system, such as, e.g., a voltage level of a power supply, and/or a frequency of a clock signal of a given functional unit, dependent upon the results of the analysis. In some embodiments, the program instruction may include instructions for storing results of the analysis in the dedicated memory.

Once the control loop has completed, power manager processor106may then return to the low power state (block308). It is noted that in some embodiments, power manager processor106may remain in active state. As described above, a clock signal to portions of power manager processor106may be gated, or a voltage level of a power supply coupled to portions of power manager processor106may be set to ground potential or any other suitable voltage level to reduce leakage power within power manager processor106. A portion of power manager processor106related to interrupt handling may, in various embodiments, remain in an active state. In some embodiments, a last instruction in the control loop may signal power manager processor106to enter the low power mode. Once power manager processor106has entered the low power mode, the method may conclude in block309.

It is noted that the embodiment of the method illustrated inFIG. 3is merely an example. In other embodiments, different operations and different orders of operation are possible and contemplated.

A flow diagram depicting an embodiment of a method for executing a control loop by a power manager processor is illustrated inFIG. 4. In some embodiments, the embodiment of the method depicted in the flow diagram ofFIG. 4may correspond to the operation described in block306of the flow diagram illustrated inFIG. 3. Referring collectively toFIG. 2and the flow diagram ofFIG. 4, the method begins in block401.

Data may then be received from a monitor circuit (block402). In some embodiments, the data may be retrieved via an internal communication bus, such as, e.g., bus105as illustrated inFIG. 1, while, in other embodiments, the data may be retrieved from an off-chip location via an I/O interface, such as, I/O block104as illustrated inFIG. 1, for example. The data may, in other embodiments, be retrieved via a direct connection between processor core201and a given monitor circuit.

The received data may then be processed (block403). In some embodiments, previously received data may be retrieved from memory202, and a statistical analysis, such as, e.g., a running average, may be performed. A Proportional-Integral-Derivative (PID) loop, or other suitable analysis, may be performed in various embodiments. Results from the analysis of the retrieved data may, in various embodiments, be stored in memory202for later use or further analysis to determine trends and the like.

The method may depend on the value of the processed data (block404). In some embodiments, the data may be compared to a predetermined threshold value. In other cases, a trend of multiple data points over a predetermined threshold value may trigger further action. The aforementioned threshold values may, in some embodiments, be adjustable or programmable depending on system configuration or other operating parameters.

If the processed data value is acceptable, the control loop may complete execution, and the method may conclude in block406. Processor core201may then return to a low power state as described in more detail above in regard toFIG. 3. If the processed data value is not acceptable, e.g., the value is greater than a predetermined threshold value, the one or more performance settings may be adjusted (block405). In some embodiments processor core201may send instructions to a power and clock management unit to change a voltage level of a power supply, and/or a frequency of a clock signal of a given functional unit within the computing system. Once the performance settings have been adjusted, the method may conclude in block406as described above.

Although the execution of a single control loop is depicted in embodiment illustrated inFIG. 4, in other embodiments, a power manager processor may execute any suitable number of control loops. In some embodiments, a separate control loop may retrieve data from numerous monitor circuits, and data received from each monitor circuit may be processed by a respective control loop. Multiple control loops, each responsible for retrieving and processing data from a respective monitor circuit, may be employed in other embodiments.

Turning toFIG. 5, a flow diagram depicting an embodiment of a method for threshold based interrupts is illustrated. Referring collectively toFIG. 1and the flow diagram ofFIG. 5, the method begins in block501.

Monitor circuit107amay then monitor an operating parameter of memory unit102(block502). In some embodiments, monitor circuit107amay monitor a voltage level of a power supply, temperature, number of accesses to memory unit102, or any other suitable metric. It is noted that although only a single monitor circuit is shown inFIG. 1, other embodiments may include multiple monitor circuit operating in parallel. Moreover, a functional unit may include multiple monitor circuits, each of which may be configured to monitor a different operating parameter within the functional unit. In some embodiments, multiple monitor circuits may be coupled to bus105to track different transactions or numbers of a specific transaction on bus105.

The method may then depend on if an event occurs (block503). Monitor circuit107amay detect an event based on the monitoring of the operating parameter. For example, an event may, in some embodiments, include a change in temperature, operating voltage, or the like. Alternatively, the event may include a particular type of access to a functional unit, e.g., a write access, or when a number of accesses to the functional unit exceeds a predetermined threshold value. In some embodiments, the event may include an access to the functional unit from another specific functional unit within a computing system, such as, integrated circuit100, for example.

When no event is detected, monitor circuit107acontinues to monitor the operating parameter as described above in regards to block502. If an event is detected, then monitor circuit107amay assert an interrupt (block504). The interrupt may be sent to power manager processor106through bus105or any other suitable communication bus.

Power manager processor106may then exit from a low power state and return to an active mode (block505). In some embodiments, upon detection of an interrupt, the active portion of power manager processor106may re-activate the inactive portions of power manager processor106, thereby allowing the resumption of processing activities. The interrupt may, in some embodiments, be generated by a monitor circuit, such as, e.g., monitor circuit107a, or by a timer included within power manager processor206. In various embodiments, by employing a low power mode for power manager processor106, the power consumed to monitor system performance and adjust performance settings may be minimized.

Once power manager processor106has exited the low power state, monitoring of one or more events may be performed (block506). In various embodiments, power manager processor106may request telemetry from one or more monitor circuits. The monitor circuits may relay data acquired during a period of time during which power manager processor106was operating in the low power mode. In some embodiments, power manager processor106may receive the telemetry from monitor circuits located on different integrated circuits.

Power manager processor106may then execute a control loop (block507) to adjust performance settings using event data as input. The control loop may be related to the event that trigger the interrupt, and may include one or more program instructions. Such program instructions may be stored in a memory dedicated to power manager processor106, such as, e.g., memory202as illustrated inFIG. 2. Power manager processor106may retrieve the program instructions from the dedicated memory prior to execution.

The method may then depend on a value of the previously detected event (block508). If the value of the event is greater than or equal to a threshold value, power manager processor106may disable further interrupts and enable one or more timer circuits (block509). Each timer circuit may include one or more counters, and may be configured to detect a passage of a predetermined period of time. Once the timers have been enabled, power manager processor106may enter the low power mode for the predetermined period of time tracked by at least one of the timers (block510). After the predetermined period of time has elapsed, the method may proceed as described above from block505.

If the value of the previously detected event is less than another threshold value, power manager processor106may disable the timers and re-enable threshold interrupt operation (block511). Once the timers have been disabled and threshold interrupt operation has been re-enabled, the method may conclude in block512.

It is noted that the embodiment of the method illustrated inFIG. 5is merely an example. In other embodiments, different operations and different orders of operation are possible and contemplated.