Enhanced loop streaming detector to drive logic optimization

An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.

TECHNICAL FIELD

The present disclosure pertains to the field of processing logic, microprocessors, and associated instruction set architecture that, when executed by the processor or other processing logic, perform logical, mathematical, or other functional operations.

BACKGROUND ART

A typical application spends a significant amount of time in loops, and many of the loops have relatively small loop bodies. Modern processors generally include logic to detect loops; e.g., a Loop Streaming Detector (LSD) is hardware logic in the front end of a processor for detecting the presence of these frequent small loops in a stream of micro-instructions.

During normal execution, micro-operations are streamed from fetch and decode units (which may include instruction decoders (XLAT), the micro-sequencer ROM (MSROM), or the decoded streaming buffer (DSB)) through an Instruction Decode Queue (IDQ) into the back end of the processor, where the micro-operations are executed. The LSD checks whether the decoded micro-operations in the IDQ contain a loop. If a loop is detected, the micro-operations in the loop body can be streamed directly out of the IDQ. That is, rather than repeatedly streaming the iterations of the loop body from the fetch and decode units, the iterations can be dispatched directly from the IDQ, allowing the fetch and decode units to be powered down. Thus, the IDQ is treated as a loop cache to reduce power consumption in the front end. The IDQ will continue to stream micro-operations into the processor back end until one of the loop branches redirects control outside of the cached loop body.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the invention provide an enhanced loop streaming detection mechanism to reduce power consumption. Instead of or in addition to disabling the logic that feeds into the instruction decode queue (IDQ), the enhanced mechanism disables the logic downstream from the IDQ to save power. The enhanced mechanism learns the contents of the loop body from the IDQ and, based on the learning, determines whether logic downstream from the IDQ can be disabled. In one embodiment, the loop body is issued repeatedly through an Allocator and Register Alias Table (RAT), which is downstream from the IDQ. The enhanced mechanism may optimize the hardware logic in the Allocator and RAT, or may optimize any other hardware logic downstream from the IDQ. The enhanced mechanism may be implemented in a processor having one or more in-order execution cores, or a processor having one or more out-of-order execution cores.

In the following description, examples of the enhanced loop streaming detection mechanism are provided with respect to loops issued from the IDQ and detected by the LSD. It should be appreciated that the enhanced loop streaming detection mechanism can be applied to loops that are stored and detected elsewhere in the front end of a processor. Therefore, examples that are specific to the IDQ are illustrative but not limiting.

InFIG. 1A, a processor pipeline100includes a fetch stage102, a length decode stage104, a decode stage106, an allocation stage108, a renaming stage110, a scheduling (also known as a dispatch or issue) stage112, a register read/memory read stage114, an execute stage116, a write back/memory write stage118, an exception handling stage122, and a commit stage124.

FIG. 1Bshows processor core190including a front end unit130coupled to an execution engine unit150, and both are coupled to a memory unit170. The core190may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core190may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit130includes a branch prediction unit132coupled to an instruction cache unit134, which is coupled to an instruction translation lookaside buffer (TLB)136, which is coupled to an instruction fetch unit138, which is coupled to a decode unit140. The decode unit140(or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit140may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core190includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit140or otherwise within the front end unit130). The decode unit140is coupled to a rename/allocator unit152(also referred to as Allocator and RAT) in the execution engine unit150.

The execution engine unit150includes the rename/allocator unit152coupled to a retirement unit154and a set of one or more scheduler unit(s)156. The scheduler unit(s)156represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)156is coupled to the physical register file unit(s)158. Each of the physical register file unit(s)158represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file unit(s)158comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file unit(s)158is overlapped by the retirement unit154to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit154and the physical register file unit(s)158are coupled to the execution cluster(s)160.

The execution cluster(s)160includes a set of one or more execution units162and a set of one or more memory access units164. The execution units162may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)156, physical register file unit(s)158, and execution cluster(s)160are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)164). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units164is coupled to the memory unit170, which includes a data TLB unit172coupled to a data cache unit174coupled to a level 2 (L2) cache unit176. In one exemplary embodiment, the memory access units164may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit172in the memory unit170. The instruction cache unit134is further coupled to a level 2 (L2) cache unit176in the memory unit170. The L2 cache unit176is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline100as follows: 1) the instruction fetch138performs the fetch and length decoding stages102and104; 2) the decode unit140performs the decode stage106, where an instruction is decoded into one or more micro-operations (also referred to as “uops”); 3) the rename/allocator unit152performs the allocation stage108and renaming stage110, where logical register names are mapped to physical register names and physical registers are allocated; 4) the scheduler unit(s)156performs the schedule stage112, where uops wait in a queue (e.g., a reservation station) until their input operands are available; 5) the physical register file unit(s)158and the memory unit170perform the register read/memory read stage114; the execution cluster160perform the execute stage116; 6) the memory unit170and the physical register file unit(s)158perform the write back/memory write stage118; 7) various units may be involved in the exception handling stage122; and 8) the retirement unit154and the physical register file unit(s)158perform the commit stage124, where the results are queued and serialized according to the original order of the uops. A result is written back (“committed”) to memory or a register file only after all of the older uops have their results written back.

The core190may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.), including the instruction(s) described herein. In one embodiment, the core190includes logic to support a packed data instruction set extension (e.g., SSE, AVX1, AVX2, etc.), thereby allowing the operations used by many multimedia applications to be performed using packed data.

According to embodiments of the invention, the front end unit130also includes a loop streaming detector (LSD141) and an instruction decode queue (IDQ142) coupled to the decode unit140. The IDQ142stores the uops decoded by the decode unit140. The LSD141checks each uop in the IDQ142, issued from the IDQ142, and/or information from the branch predictor, decoded streaming buffer (DSB), or other source of micro-operations to detect the presence of a loop. For simplicity of the illustration, signal paths between the LSD141and these other sources of micro-operations are not shown. The IDQ142may store one or more iterations of unrolled loop body; the number of uops stored in the IDQ142is limited by the size of the IDQ142. In an alternative embodiment, loops may be stored and detected by different hardware logic in the front end unit130. The hardware logic that detects the presence of loops may include one hardware component or multiple distributed hardware components. For simplicity of the description, the loop-detecting hardware in the front end unit130is collectively referred to as the LSD141.

When a loop is detected, the LSD141sets the tracker bits in a loop characteristic tracker143to track the specific operations performed in the loop body. In one embodiment, each tracker bit tracks one or more uops in the loop body that will be using the functions of one or more hardware components in the back end (the execution engine unit150in this example). For example, a tracker bit may track whether there is any uop in the loop body that uses floating point functions. If there is none, that hardware components that check for floating point usage, allocate floating point registers, manage and execute floating point operations may be disabled. Thus, according to these tracker bits, the loop characteristic tracker143can disable a portion of the hardware components in the execution engine unit150to save power. The loop characteristic tracker143may be implemented as one hardware component coupled to the hardware components in the execution engine unit150. Alternatively, the loop characteristic tracker143may be implemented as multiple hardware components that are distributed among and coupled to the hardware components in the execution engine unit150. To avoid obscuring the diagram ofFIG. 1B, the loop characteristic tracker143is shown as one single component and the connections between the loop characteristic tracker143and the components in the execution engine unit150are not shown. It is appreciated that alternative embodiments of the loop characteristic tracker143may exist as described above.

In one embodiment, the operations tracked by the loop characteristic tracker143are those operations that alter the contents of one or more logical registers, where each logical register can be mapped to a (versioned) physical register.FIG. 2illustrates an embodiment of register architecture200that implements the physical register file unit(s)158. The register architecture200is based on the Intel® Core™ processors implementing an instruction set including x86, MMX™, Streaming SIMD Extensions (SSE), SSE2, SSE3, SSE4.1, and SSE4.2 instructions, as well as an additional set of SIMD extensions, referred to the Advanced Vector Extensions (AVX). However, it is understood different register architecture that supports different register lengths, different register types and/or different numbers of registers may also be used.

In the embodiment illustrated, there are thirty-two vector registers210that are 512 bits wide; these registers are referenced as zmm0through zmm31. The lower order 256 bits of the lower sixteen zmm registers are overlaid on registers ymm0-16. The lower order 128 bits of the lower sixteen zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15. In the embodiment illustrated, there are eight mask registers220(k0through k7), each 64 bits in length. In an alternate embodiment, the mask registers220are 16 bits width.

In the embodiment illustrated, the register architecture200further includes sixteen 64-bit general-purpose (GP) registers230. In an embodiment they are used along with the existing x86 addressing modes to address memory operands. The embodiment also illustrates a number of special-purpose registers, including but not limited to: RFLAGS registers260, RIP registers270, Multimedia Extensions Control and Status Register (MXCSR) register280, Floating Point Control Word (FPCW)290and segment registers292. The MXCSR280contains flags that control and indicate the status of SSE instructions, such as precision, rounding mode, and exception generation. The FPCW290also contains flags that control the precision, rounding mode, and exception generation of the floating point units. Each segment register292contains a segment address, which can be appended with an offset to form a real address.

The embodiment also illustrates a scalar floating point (FP) stack register file (x87 stack)240, on which is aliased the MMX packed integer flat register file250. In the embodiment illustrated, the x87 stack is an eight-element stack used to perform scalar floating-point operations on 32/64/80-bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and xmm registers.

The above description provides an overview of the underlying architecture for the enhanced loop streaming detection. The following description provides the details and examples of enhanced loop streaming detection.FIG. 3is a state machine300for the enhanced loop streaming detection according to one embodiment. The state machine300has three states: a reset state310, a learn state320and a replay state330. During the reset state310, the tracker bits of the loop characteristic tracker143for all tracked functions are cleared. Referring also toFIG. 1B, the LSD141is not engaged in the reset state310. When the LSD141detects the top of the loop body, the LSD141sends a trigger to the state machine300to transition the reset state310into the learn state320. In the learn state320, for each uop in the detected loop body, the tracker bit for the corresponding tracked characteristic is set if the uop has that tracked characteristic. Each tracked characteristic of the uops identifies a set of functions performed by hardware logic. Thus, using the tracker bits, the loop characteristic tracker143is able to learn and identify what hardware logic is to be used by the loop body at the pipe-stage downstream from the decode unit140(or more specifically, downstream from the IDQ142). When the next top of the loop body is detected by the LSD141, the state machine300enters the replay state330. In the replay state330, the loop characteristic tracker143disables the hardware logic corresponding to each tracker bit that is cleared (or remains cleared from the reset state310). That is, the loop characteristic tracker143disables the hardware logic downstream from the decode unit140that is not utilized by the uops in the loop body. If the tracker bit is set, then the corresponding hardware logic is needed and is clocked or powered up as normal.

In one embodiment, only a single path through the loop body can be issued from the IDQ142. Therefore, during the learn state320or the replay state330, if execution strays from the predetermined path through the loop body (e.g., when a loop exit is taken), the state machine300transitions back to the reset state300and re-enables all of the tracked logic.

The term “disable” as used herein may be used to mean “power down” or “clock gate.” Power down refers to shutting down all power supply to hardware logic; as a result, logic states stored in the hardware logic are lost. Clock gating refers to disabling the toggling of the hardware logic and clocks to save switching power. When hardware logic is clock gated, the logic states stored therein are retained and only leakage currents are incurred. Therefore, clock gating may be used instead of power down when it is necessary or more beneficial to retain the current values of the logic states.

FIG. 4illustrates an example architecture for the enhanced loop streaming detection according to one embodiment. In this embodiment, the enhanced loop streaming detection is implemented by a core400with out-of-order execution capabilities. It is appreciated that a similar enhanced loop streaming detection mechanism can also be deployed in a processor that performs in-order execution. Like elements inFIGS. 1B and 4bear like reference numerals, and certain aspects ofFIG. 1Bhave been omitted fromFIG. 4in order to avoid obscuring other aspects ofFIG. 4. In the embodiment ofFIG. 4, the core400in the front end includes fetch and decode units410(which correspond to the instruction fetch138and the decode unit140), the LSD141and the IDQ142. In the back end of the core400(which corresponds to the execution engine unit150), the core400includes an Allocator and Register Alias Table440(corresponding to the rename/allocator unit152), reservation stations and uop scheduler460(corresponding to the scheduler unit(s)156), execution units and registers470(corresponding to the execution unit(s)162and the physical register file unit(s)158), and memory units480(corresponding to the memory access unit(s)164and the memory unit170). The registers in the execution units and registers470further include FPCW, MXCSR and segment registers (an example of which is shown inFIG. 2). The memory units480further include load buffers and store buffers. The execution units and registers470and the memory units480are both coupled to the retirement unit154.

FIG. 4also shows a loop characteristic tracker450(which corresponds to the loop characteristic tracker143) within the allocator and RAT440. It is appreciated that the loop characteristic tracker450in alternative embodiments may be located outside of the allocator and RAT440and/or may be distributed among the components downstream from the fetch and decode units410and the IDQ142. The loop characteristic tracker450includes a state machine circuitry451to implement the state machine300ofFIG. 3. The loop characteristic tracker450includes multiple tracker bits to track the uops in the loop body, and includes circuitry to disable hardware components that are not to be used by the uops in the loop body. In the example ofFIG. 4, the loop characteristic tracker450disables the hardware components within the allocator and RAT440only. In an alternative embodiment, the loop characteristic tracker450may enable and disable the hardware components within and outside the allocator and RAT440; for example, any hardware component downstream from the fetch and decode units410and the IDQ142that are not to be used by the uops in the loop body. However, to disable a hardware component in the any of the units460,470,480and154, the loop characteristic tracker450needs to wait until all of the uops prior to the detected loop complete their pipeline stages.

In the example ofFIG. 4, the loop characteristic tracker450includes four tracker bits, where each tracker bit indicates the presence of uops having a shared characteristic in the loop. Having the shared characteristic means that these uops will be using the functions of one or more hardware components. The value of each tracker bit is used to determine whether the one or more hardware components will be used by these uops. The hardware components are disabled if they will not be used by these uops. In an alternative embodiment, the loop characteristic tracker450may include any number of tracker bits to track uops with any number of characteristics. Multiple tracker bits can be used to indicate the number of times that a characteristic is detected, or whether a characteristic is detected more than once. For example, a first tracker bit can be set if a specified functionality is detected in the first half of the loop body; likewise, a second tracker bit can be set if the specified functionality is detected in the second half of the loop body.

In one embodiment, the tracker bit0may be used to indicate whether the loop body contains any x87 Floating Point Control Word (FPCW) writers or Multimedia Extensions Control and Status Register (MXCSR) writers. Embodiments of the FPCW and the MXCSR are shown inFIG. 2as the FPCW290and MXCSR280. If there are no uops in the loop body that write into the FPCW or the MXCSR, the hardware components that may be disabled include but are not limited to: the logic that detects whether any uop is a writer to the FPCW/MXCSR, the logic that allocates new FPCW/MXCSR physical registers, and the logic that handles the full stall condition of the FPCW/MXCSR physical registers.

In one embodiment, the tracker bit1may be used to indicate whether the loop body contains any memory segment register writers. If there are no uops in the loop body that write into the segment registers, the hardware components that may be disabled include but are not limited to: the logic that detects whether any uop is a writer to the segment registers, the logic that allocates new segment registers, and the logic that handles the full stall condition of the segment registers.

In one embodiment, the tracker bit2may be used to indicate whether transactional synchronization is engaged, or there are any uops that alter the state of transactional synchronization. In the embodiment ofFIG. 4, the core400implements an instruction set architecture, which provides a set of instruction set extensions that allow programmers to specify regions of code for transactional synchronization. Programmers can use these extensions to achieve the performance of fine-grain locking while actually programming using coarse-grain locks. Intel® Core™ processors implement two software interfaces: Hardware Lock Elision (HLE) and Restricted Transactional Memory (RTM), both of which allow programmers to define transactional regions. If there are no uops in the loop body that perform transactional synchronization, the hardware components that may be disabled include but are not limited to: the logic that performs transactional memory operations, the logic that alters a state of the transactional memory operations, and the logic that performs hardware lock control (e.g., HLE control) such as the nesting depth logic, the register liveness tracking logic, etc.

In one embodiment, the tracker bit3may be used to indicate whether there are any uops in the loop body that adjust x87 Top of Stack (ToS) indicator or alter the valid status of the floating point stack. If there are no uops in the loop body that perform x87 floating point stack related operations, the hardware components that may be disabled include but are not limited to: the logic that detects x87 floating point stack adjustment uops, and the logic that tracks which x87 stack locations are valid.

FIG. 5is a flow diagram of a method500for performing the enhanced loop streaming detection according to one embodiment. The method500begins when a processor (more specifically, the core190ofFIG. 1Bor the core400ofFIG. 4) detects the presence of a loop in micro-operations that are decoded by a decoder (block510). The processor identifies hardware components downstream from the decoder that are not to be used by the micro-operations of the loop (block520), and executes the micro-operations of the loop with the identified hardware components disabled (block530).

In one embodiment, the LSD141may perform the detection at block510by examining the uops in the IDQ142, uops issued from the IDQ142, and/or information from the branch predictor, decoded streaming buffer (DSB), or other source of micro-operations. Upon detection of a loop, the LSD141signals the loop characteristic tracker143to transition from the reset state to the learn state as shown inFIG. 3. Hardware components that will be used by the uops of the loop are identified by a first tracker bit value, and hardware components that will not be used by the uops of the loop are identified by a second tracker bit value. The hardware components identified by the second tracker bit value are disabled to save power.

In various embodiments, the method500ofFIG. 5may be performed by a general-purpose processor, a special-purpose processor (e.g., a graphics processor or a digital signal processor), or another type of digital logic device or instruction processing apparatus. In some embodiments, the method500ofFIG. 5may be performed by a processor, apparatus, or system, such as the embodiments shown inFIGS. 1, 4 and 6-10. Moreover, the processor, apparatus, or system shown inFIGS. 1, 4 and 6-10may perform embodiments of operations and methods either the same as, similar to, or different than those of the method500ofFIG. 5.

Processor with Integrated Memory Controller and Graphics

FIG. 6is a block diagram of a processor600that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes inFIG. 6illustrate a processor600with a single core602A, a system agent610, a set of one or more bus controller units616, while the optional addition of the dashed lined boxes illustrates an alternative processor600with multiple cores602A-N, a set of one or more integrated memory controller unit(s)614in the system agent unit610, and special purpose logic608.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units606, and external memory (not shown) coupled to the set of integrated memory controller units614. The set of shared cache units606may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit612interconnects the integrated graphics logic608, the set of shared cache units606, and the system agent unit610/integrated memory controller unit(s)614, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units606and cores602-A-N.

In some embodiments, one or more of the cores602A-N are capable of multi-threading. The system agent610includes those components coordinating and operating cores602A-N. The system agent unit610may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores602A-N and the integrated graphics logic608. The display unit is for driving one or more externally connected displays.

Exemplary Computer Architectures

Referring now toFIG. 7, shown is a block diagram of a system700in accordance with one embodiment of the present invention. The system700may include one or more processors710,715, which are coupled to a controller hub720. In one embodiment the controller hub720includes a graphics memory controller hub (GMCH)790and an Input/Output Hub (IOH)750(which may be on separate chips); the GMCH790includes memory and graphics controllers to which are coupled memory740and a coprocessor745; the IOH750is couples input/output (I/O) devices760to the GMCH790. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory740and the coprocessor745are coupled directly to the processor710, and the controller hub720in a single chip with the IOH750.

The optional nature of additional processors715is denoted inFIG. 7with broken lines. Each processor710,715may include one or more of the processor cores described herein and may be some version of the processor600.

The memory740may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub720communicates with the processor(s)710,715via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection795.

In one embodiment, the coprocessor745is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub720may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources710,715in terms of a spectrum of metrics of merit including architectural, micro-architectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor710executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor710recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor745. Accordingly, the processor710issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor745. Coprocessor(s)745accept and execute the received coprocessor instructions.

Referring now toFIG. 8, shown is a block diagram of a first more specific exemplary system800in accordance with an embodiment of the present invention. As shown inFIG. 8, multiprocessor system800is a point-to-point interconnect system, and includes a first processor870and a second processor880coupled via a point-to-point interconnect850. Each of processors870and880may be some version of the processor600. In one embodiment of the invention, processors870and880are respectively processors710and715, while coprocessor838is coprocessor745. In another embodiment, processors870and880are respectively processor710coprocessor745.

Processors870and880are shown including integrated memory controller (IMC) units872and882, respectively. Processor870also includes as part of its bus controller units point-to-point (P-P) interfaces876and878; similarly, second processor880includes P-P interfaces886and888. Processors870,880may exchange information via a point-to-point (P-P) interface850using P-P interface circuits878,888. As shown inFIG. 8, IMCs872and882couple the processors to respective memories, namely a memory832and a memory834, which may be portions of main memory locally attached to the respective processors.

Processors870,880may each exchange information with a chipset890via individual P-P interfaces852,854using point to point interface circuits876,894,886,898. Chipset890may optionally exchange information with the coprocessor838via a high-performance interface839. In one embodiment, the coprocessor838is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

Chipset890may be coupled to a first bus816via an interface896. In one embodiment, first bus816may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.

As shown inFIG. 8, various I/O devices814may be coupled to first bus816, along with a bus bridge818which couples first bus816to a second bus820. In one embodiment, one or more additional processor(s)815, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus816. In one embodiment, second bus820may be a low pin count (LPC) bus. Various devices may be coupled to a second bus820including, for example, a keyboard and/or mouse822, communication devices827and a storage unit828such as a disk drive or other mass storage device which may include instructions/code and data830, in one embodiment. Further, an audio I/O824may be coupled to the second bus820. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG. 8, a system may implement a multi-drop bus or other such architecture.

Referring now toFIG. 9, shown is a block diagram of a second more specific exemplary system900in accordance with an embodiment of the present invention. Like elements inFIGS. 8 and 9bear like reference numerals, and certain aspects ofFIG. 8have been omitted fromFIG. 9in order to avoid obscuring other aspects ofFIG. 9.

FIG. 9illustrates that the processors870,880may include integrated memory and I/O control logic (“CL”)872and882, respectively. Thus, the CL872,882include integrated memory controller units and include I/O control logic.FIG. 9illustrates that not only are the memories832,834coupled to the CL872,882, but also that I/O devices914are also coupled to the control logic872,882. Legacy I/O devices915are coupled to the chipset890.

Referring now toFIG. 10, shown is a block diagram of a SoC1000in accordance with an embodiment of the present invention. Similar elements inFIG. 6bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. InFIG. 10, an interconnect unit(s)1002is coupled to: an application processor1010which includes a set of one or more cores602A-N and shared cache unit(s)606; a system agent unit610; a bus controller unit(s)616; an integrated memory controller unit(s)614; a set or one or more coprocessors1020which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit1030; a direct memory access (DMA) unit1032; and a display unit1040for coupling to one or more external displays. In one embodiment, the coprocessor(s)1020include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art upon studying this disclosure. In an area of technology such as this, where growth is fast and further advancements are not easily foreseen, the disclosed embodiments may be readily modifiable in arrangement and detail as facilitated by enabling technological advancements without departing from the principles of the present disclosure or the scope of the accompanying claims.