SEMICONDUCTOR APPARATUS AND TEST METHOD THEREOF

A semiconductor apparatus includes a data output unit and a test output unit. The data output unit outputs a plurality of data, through a plurality of data lines, to a plurality of input/output pads. The test output unit receives one of the plurality of data and a plurality of output data, which is output to the plurality of input/output pads, and outputs the received data to a probe pad in a probe test mode.

DETAILED DESCRIPTION

Hereinafter, a semiconductor apparatus and a test method thereof according to various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring toFIG. 2, a semiconductor apparatus having a data output path for outputting the data includes a data output unit10, an input/output pad20, a test output unit30, and a probe pad40.

The data output unit10may be configured to receive data DI transmitted from a data line GIO and generate output data DO. In detail, the data output unit10may include a circuit such as a flip-flop for outputting data in synchronization with a clock or an output driver for driving data.

The input/output pad20may be configured to output the output data DO to other circuit blocks which are separate from the semiconductor apparatus or to receive a signal from one of the other circuit blocks. In an embodiment, a bump pad may be used as the input/output pad20. Since the bump pad has a low data output loading ability, a driving ability of the data output unit10may be set to low by extension.

The test output unit30may be configured to be activated in response to a test mode signal TM. The test output unit30may be configured to selectively receive the data DI as first test input data TDI—1 or the output data DO as second test input data TDI—2 in response to a test selection signal TM_SEL. That is, in the state in which the test output unit30has been activated, when a test selection signal TM_SEL having a first level is applied, the test output unit30may receive the data DI and output the data DI to the probe pad40as test data TDO. When a test selection signal TM_SEL having a second level is applied, the test output unit30may receive the output data DO and output the output data DO to the probe pad40as the test data TDO.

The probe pad40may be configured to output the test data TDO to other circuits which are separate from the semiconductor apparatus, such as a probe test apparatus. The probe pad40may be formed to include a higher data output loading ability than that of the input/output pad20. Since the probe pad40may be formed to include relatively high data output loading ability, the driving ability of the test output unit30may be set higher than that of the data output unit10by extension.

The operation of the semiconductor apparatus according to an embodiment will be described below.

In a normal operation, when the semiconductor apparatus performs a data output operation such as a data read operation, data stored in the memory cell may be transmitted to the data output unit10through the data line GIO. The data output unit10may receive the- data DI transmitted from the memory cell and may output the data DI to the input/output pad20as the output data DO. Since during the normal operation the test mode signal TM is deactivated, the test output unit30may enter a deactivated state, although the data DI may be provided to the test output unit30.

In a test mode, when the semiconductor apparatus performs the data output operation such as the data read operation, data stored in the memory cell may be transmitted to the data output unit10through the data line GIO. The data output unit10may receive the data DI transmitted from the memory cell and may output the data DI to the input/output pad20as the output data DO.

Since during the test mode the test mode signal TM is activated, the test output unit30may enter an activated state. An operation mode of the test output unit30may be determined in response to the test selection signal TM_SEL. For example, when the test selection signal TM_SEL having a first level is applied, the test output unit30may operate in a first mode. In the first mode, the test output unit30may receive the first test input data TDI—1, that is, the data DI, and may output the first test input data TDO—1 as the test data TDO. When the test selection signal TM_SEL having a second level is applied, the test output unit30may operate in a second mode. In the second mode, the test output unit30may receive the second test input data TDI—2, that is, the output data DO provided from the input/output pad20, and may output the second test input data TDI—2 as the test data TDO.

The semiconductor apparatus according to an embodiment may include the test output unit30which may provide the data DI transmitted to the data line GIO or the output data DO output to the input/output pad20, to the probe pad40, thereby performing the probe test. In the first mode, the semiconductor apparatus may perform a probe test for the data of the memory cell loaded on the data line GIO, thereby verifying fail of a memory cell. In the second mode, the semiconductor apparatus may perform a probe test for the data output to the input/output pad20through a data output path of the data output unit10, thereby verifying fail of the data output path.

For example, when the test data TDO has a normal first preset value in the first mode, it may represent that no fail exists in the memory cell. However, when the test data TDO is beyond the normal first preset value in the first mode, it is possible to recognize that a fail exists in the memory cell.

When the test data TDO has a normal second preset value in the second mode, it may represent that no fail exists in the data output path. However, when the test data TDO is beyond the normal second present value in the second mode, it is possible to recognize that a fail exists in the data output path.

As shown inFIG. 3, the test output unit30may include a multiplexing section31, a compression section32, a selection section33, and a test output driver34.

The multiplexing section31may be configured to receive a plurality of first test input data TDI—1<0:15> and output one of the plurality of the first test input data TDI—1<0:15> as selection transmission data MTDI—1<0> in response to a control signal CTRL. The data line GIO may include a plurality of lines, and the plurality of first test input data TDI—1<0:15> may correspond to a plurality of data DI transmitted through the plurality of data lines GIO. The control signal CTRL may be applied in order to select one of the plurality of first test input data TDI—1<0:15>. The plurality of first test input data TDI—1<0:15> may be sequentially selected according to level changes of the control signal CTRL. The semiconductor apparatus according to an embodiment may not need a plurality of probe pads corresponding to numbers of the plurality of first input data TDI—1<0:15>, since one of the plurality of first input data TDI—1<0:15> may be selected through the multiplexing section31. Thus, the semiconductor apparatus can perform a test for all data through less probe pads40compared to the number of input/output pads20.

The compression section32may be configured to compress a plurality of second test input data TDI—2<0:15> and output compression data CTDI—2<0>. A compression scheme may be used to simultaneously verify a plurality of data, and may be set in such a manner that when all the plurality of second test input data TDI—2<0:15> has substantially the same level, compression data CTDI—2<0> having a first level is generated, and when the plurality of second test input data TDI—2<0:15> does not have substantially the same level, compression data CTDI—2<0> having a second level is generated. That is, if all of the second test input data TDI—2<0:15> have substantially the same level, there is no fail in the semiconductor apparatus, and the compression section32may output the compression data CTDI—2<0> having a first level. If at least one second test input data TDI—2<0:15> have different level, there is a fail generated in the data output path of the semiconductor apparatus, and the compression section32may output the compression data CTDI—2<0> having a second level.

The selection section33may be configured to be activated in response to the test mode signal TM, receive the selection is transmission data MTDI—1<0> and the compression data CTDI—2<0>, and select one of the selection transmission data MTDI—1<0> or the compression data CTDI—2<0> in response to the test selection signal TM_SEL. That is, in the state in which the selection section33has been activated, when a test selection signal TM_SEL having a first level is applied, the selection section33may select and output the selection transmission data MTDI—1<0>. When a test selection signal TM_SEL having a second level is applied, the selection section33may receive and output the compression data CTDI—2<0>.

The test output driver34may be configured to receive the output signal of the selection section33, drive the output signal of the selection section33, and output the output signal as test data TDO<0>.

Referring toFIG. 4, the compression section32may include first to fourth exclusive NOR gates XNOR1 to XNOR4 and an AND gate AD1.

The exclusive NOR gates XNOR1 to XNOR4 may be configured to receive a predetermined number of second test input data TDI—2 <0:15> and perform an XNOR operation on the received data, respectively. The exclusive NOR gate may generate an output signal having a high level when all the levels of a plurality of input values are substantially equal to one another, and may generate an output signal having a low level when the levels of the plurality of input values are different from one another. For example, each of the exclusive NOR gates XNOR1 to XNOR4 is a 4-input element: the first exclusive NOR gate XNOR1 performs an XNOR operation on TDI—2<0> to TDI—2<3>, the second exclusive NOR gate XNOR2 performs an XNOR operation on TDI—2<4> to TDI—2<7>, the third exclusive NOR gate XNOR3 performs an XNOR operation on TDI—2<8> to TDI—2<11>, and the fourth exclusive NOR gate XNOR4 performs an XNOR operation on TDI—2<12> to TDI—2<15>.

The AND gate AD1 may be configured to receive the output of the first to fourth exclusive NOR gates XNOR1 to XNOR4, perform an AND operation on the received output, and output the compression data CTDI—2<0>. When all the output values of the first to fourth exclusive NOR gates XNOR1 to XNOR4 have a high level, the AND gate AD1 generates may generate the compression data CTDI—2<0> having a high level. Even when one of the output values of the first to fourth exclusive NOR gates XNOR1 to XNOR4 has a low level, the AND gate AD1 may generate the compression data CTDI—2<0> having a low level.

Referring toFIG. 5, in a test mode, data may be simultaneously written in all of a plurality of memory cells of the semiconductor apparatus. That is, when a write command WRITE is activated (S1), data having high level or low level are written in a plurality of memory cells of the semiconductor apparatus. (S1—1).

Subsequently, a reading operation of the semiconductor apparatus may be performed. That is, when a read command READ is activated (S2), the data written in the plurality of memory cells may be output to the input/output pads through the data output circuit (S2—1). The data of the input/output pad may be transmitted to the probe pad through the test output unit in order to check for fail data of the data output path. However, since the number of the probe pads may be limited due to design efficiency, a step of compressing a plurality of data output to the input/output pads may be added (S2—2). As described above, compression may be performed in such a manner where compression data having a first level is generated when all the levels of the plurality of data are substantially equal to one another, and compression data having a second level is generated when the levels of the plurality of data are different from one another. The compression data may be output to the probe pads as test data (S2—3) and the test data may be probed by a probe test apparatus. Thus, it is possible to perform a probe test for the data output path.

According to an embodiment, it is possible to verify a fail of the data output path of the semiconductor memory apparatus as well as a fail of the memory cell. It will be understood to those skilled in the art that the absence of a fail of a memory cell may be verified through the memory cell fail test, and when the data output path test is performed and thus the presence of fail has been checked through the test data, it is possible to recognize that fail exists on the data output path including the output driver and the output circuit.