Switching device and testing apparatus

There is provided a switching device that electrically connects or disconnects a first terminal and a second terminal to/from each other. The switching device includes a semiconductor layer, a drain electrode that is formed in the semiconductor layer, where the drain electrode is connected to the first terminal, a source electrode that is formed in the semiconductor layer, where the source electrode is connected to the second terminal, a gate insulator that is formed on the semiconductor layer between the drain electrode and the source electrode, a floating gate that is formed on the gate insulator, where the floating gate retains a charge therein, and a tunnel gate that is formed on the floating gate, the tunnel gate supplying a tunnel current determined by a driving voltage applied thereto to charge or discharge the floating gate.

CROSS REFERENCE TO RELATED APPLICATION

This is a continuation application of PCT/JP2007/066267 filed on Aug. 22, 2007 which claims priority from a Japanese Patent Application NO. 2006-253846 filed on Sep. 20, 2006, the contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

The present invention relates to a switching device and a testing apparatus. More particularly, the present invention relates to a switching device that connects or disconnects, to/from each other, a drain electrode and a source electrode provided on a semiconductor layer and to a testing apparatus using the same.

2. Related Art

Patent Document 1 discloses a mechanical relay using a reed switch surrounded by a metal guard pipe. The mechanical relay achieves excellent high-frequency characteristics since the guard pipe and the reed switch are arranged coaxially. Patent Document 2 discloses an photo MOSFET relay. The photo MOSFET relay is a semiconductor relay and thus has a longer lifetime than a mechanical relay. Patent Document 3 discloses a semiconductor relay that is turned on/off in such a manner that a high voltage is applied to a control gate to inject electrons into a floating gate and that a gate portion is irradiated with an ultraviolet ray to cause the electrons to be emitted.

A testing apparatus for performing a logic test on a device under test (DUT) includes a pin driver that outputs a test signal to the DUT and a pin comparator that detects an output signal output from the DUT. In order to be capable of performing a direct current (DC) test as well as the logic test, the testing apparatus additionally includes a DC test unit that outputs a DC voltage, a relay (an I/O relay) that connects and disconnects the DUT to/from the pin driver and the pin comparator, and a relay (a DC relay) that connects and disconnects the DC test unit to/from the DUT. The I/O relay and the DC relay are mechanical relays or photo MOSFET relays, for example.

A mechanical relay provides electrical connection and disconnection by opening and closing of a metal contact. Therefore, the metal contact deteriorates due to friction and the like. Accordingly, the mechanical relay has a short lifetime. Furthermore, the mechanical relay cannot be integrated into a semiconductor integrated circuit, which results in a large size and undermines efforts to increase the device density.

A photo MOSFET relay is configured such that components such as a photocell, alight emitting diode, and a MOSFET are mounted on a lead frame and connected to each other by means of bonding wires. Therefore, the photo MOSFET relay is complex in structure, large and expensive. In addition, the photo MOSFET relay exhibits poor high-frequency characteristics because of the parasitic inductances of the lead frame, bonding wires and the like and the RC product of the on resistance and the gate capacitance of the MOSFET. Furthermore, since the photocell and the light emitting diode are formed by using a GaAs semiconductor or the like, the photo MOSFET relay cannot be integrated together with other circuits that are formed by using a silicon semiconductor. For the reasons stated above, the photo MOSFET relay hampers attempts to reduce the size of a device including the photo MOSFET relay, to increase the density of the device and to lower the cost of the device.

According to the semiconductor relay disclosed in Patent Document 3, it is required to irradiate the gate portion with an ultraviolet ray to cause the electrons to be emitted. The semiconductor relay thus cannot be easily turned on/off.

Here, the testing apparatus outputs a test signal having a high frequency such as several GHz. Accordingly, it is desirable that the I/O relay is capable of transmitting a high-frequency test signal with low distortion and transmitting a test signal whose frequency widely ranges from a DC to approximately several 10 GHz with a low loss. In the testing apparatus, it is desirable that the impedance of the transmission path between the pin driver and the DUT accurately takes a predetermined value (for example, 50Ω). Accordingly, the I/O relay desirably has a small number of impedance mismatch points. Furthermore, the I/O relay desirably has a low DC on resistance so that the loss and waveform distortion can be prevented.

The DC relay is connected at one end thereof to the DUT-side terminal of the I/O relay. Therefore, when the testing apparatus performs a logic test, the electrostatic capacitance of the DC relay during the off state is added to the impedance of the transmission path between the pin driver and the DUT. For this reason, the DC relay desirably has a low electrostatic capacitance during the off state in order to reduce its influence on the impedance of the transmission path for a logic test. Furthermore, the DC relay desirably has a low DC on resistance such that there is no difference in DC level between the output end of the DC test unit and the input end of the DUT.

Here, the testing apparatus repeatedly performs tests, which indicates that the I/O relay and the DC relay are turned on/off a very large number of times. Therefore, the I/O relay and the DC relay desirably have a long lifetime.

In light of the above, a switch that is utilized as the I/O relay in the testing apparatus desirably has excellent high-frequency transmission characteristics, a wide frequency range and a low loss, a small number of impedance mismatch points, and a low DC on resistance. On the other hand, a switch that is utilized as the DC relay in the testing apparatus desirably has a low electrostatic capacitance during the off state and a low DC on resistance. Furthermore, the switches that are utilized as the I/O relay and the DC relay in the testing apparatus desirably have a long lifetime. Here, the mechanical relay and the photo MOSFET relay discussed above both have advantages and disadvantages for their usage as the I/O relay and the DC relay in the testing apparatus.

SUMMARY

Therefore, it is an object of an aspect of the innovations herein to provide a switching device and a testing apparatus which are capable of overcoming the above drawbacks accompanying the related art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the innovations herein.

According to the first aspect related to the innovations herein, one exemplary switching device may electrically connect or disconnect a first terminal and a second terminal to/from each other. The switching device includes a semiconductor layer, a drain electrode that is formed in the semiconductor layer, where the drain electrode is connected to the first terminal, a source electrode that is formed in the semiconductor layer, where the source electrode is connected to the second terminal, a gate insulator that is formed on the semiconductor layer between the drain electrode and the source electrode, a floating gate that is formed on the gate insulator, where the floating gate retains a charge therein, and a tunnel gate that is formed on the floating gate, where the tunnel gate supplies a tunnel current determined by a driving voltage applied thereto to charge or discharge the floating gate.

According to the second aspect related to the innovations herein, one exemplary testing apparatus may test a device under test. The testing apparatus includes a test signal generating section that generates a test signal, a driver that supplies the test signal to the device under test, a comparator that detects an output signal from the device under test, a judging section that judges the output signal detected by the comparator, and a switching device that electrically connects or disconnects, to/from each other, a first terminal and a second terminal, which are respectively (i) at least one of an output end of the driver and an input end of the comparator and (ii) an input and output end of the device under test. Here, the switching device includes a semiconductor layer, a drain electrode that is formed in the semiconductor layer, where the drain electrode is connected to the first terminal, a source electrode that is formed in the semiconductor layer, where the source electrode is connected to the second terminal, a gate insulator that is formed on the semiconductor layer between the drain electrode and the source electrode, a floating gate that is formed on the gate insulator, the floating gate retaining a charge therein, and a tunnel gate that is formed on the floating gate, where the tunnel gate supplies a tunnel current determined by a driving voltage applied thereto to charge or discharge the floating gate.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1illustrates the configuration of a switching device10relating to an embodiment of the present invention. The switching device10includes a semiconductor switch20and a driving section22. The switching device10electrically connects or disconnects a first terminal12and a second terminal14to/from each other. The semiconductor switch20is formed on a semiconductor, and electrically connects or disconnects its drain and its source to/from each other (i.e., turned on or off) depending on a driving voltage supplied to its gate. The semiconductor switch20may be of an n-channel type whose majority carrier of the current flowing between the drain and the source is electrons or a p-channel type whose majority carrier is holes. The driving section22applies a driving voltage to the gate of the semiconductor switch20in order to electrically connect or disconnect the drain and the source to/from each other.

FIG. 2is an exemplary top view illustrating the configuration of the semiconductor switch20relating to the embodiment.FIG. 3is a cross-sectional view illustrating the semiconductor switch20relating to the embodiment along a line A-A′ shown inFIG. 2. The semiconductor switch20includes a semiconductor substrate30, an insulating layer32, a semiconductor layer34, a drain electrode36, a source electrode38, a substrate contact electrode40, an inter-channel insulating portion42, a gate insulator48, a floating gate50, and a tunnel gate52.

The semiconductor substrate30may be formed from single-crystal silicon, for example. The insulating layer32is formed on the semiconductor substrate30, and insulates the upper layer, i.e., the semiconductor layer34and the lower layer, i.e., the semiconductor substrate30from each other. The insulating layer32may be a silicon dioxide film, for example.

The semiconductor layer34is disposed on the insulating layer32. The semiconductor layer34may be formed by implanting n- or p-type impurities into a semiconductor such as silicon. For example, the semiconductor layer34may be a p-type semiconductor region when the semiconductor switch20is an n-channel switch and may be an n-type semiconductor region when the semiconductor switch20is a p-channel switch.

The drain electrode36is formed as a partial region within the semiconductor layer34. For example, the drain electrode36may be an n-type semiconductor region when the semiconductor switch20is a n-channel switch and may be a p-type semiconductor region when the semiconductor switch20is a p-channel switch. The drain electrode36is connected to the first terminal12through interconnections.

The source electrode38is formed as a partial region within the semiconductor layer34and positioned away by a predetermined distance from the drain electrode36when the semiconductor switch20is seen from above. For example, the source electrode38may be an n-type semiconductor region when the semiconductor switch20is an n-channel switch and may be a p-type semiconductor region when the semiconductor switch20is a p-channel switch. The source electrode38is connected to the second terminal14through interconnections. Here, the region in the semiconductor layer34between the drain electrode36and the source electrode38constitutes a channel56for the carrier between the drain and the source.

The substrate contact electrode40is formed as a partial region within the semiconductor layer34, which is different from the regions of the drain electrode36and the source electrode38when the semiconductor switch20is seen from above. For example, the substrate contact electrode40may be a p-type semiconductor region when the semiconductor switch20is an n-channel switch and may be an n-type semiconductor region when the semiconductor switch20is a p-channel switch. For example, the source electrode38may be connected to the second terminal14through interconnections.

The inter-channel insulating portion42is formed within the semiconductor layer34and insulates a region at least including the drain electrode36, the source electrode38, the substrate contact electrode40, and the channel56positioned between the drain electrode36and the source electrode38, from a different region. For example, the inter-channel insulating portion42may be formed so as to surround the drain electrode36, the source electrode38, the substrate contact electrode40and the channel56when the semiconductor switch20is seen from above. For example, the inter-channel insulating portion42may extend through the semiconductor layer34from the upper surface of the semiconductor layer34to the insulating layer32when the semiconductor switch20is seen in cross-section.

The semiconductor switch20having the above-described configuration forms a Silicon-on-Insulator (SOI) device due to the insulating layer32. In the semiconductor switch20, the inter-channel insulating portion42formed on the insulating layer32may electrically insulates the region at least including the drain electrode36, the source electrode38, the substrate contact electrode40, and the channel56positioned between the drain electrode36and the source electrode38, from a different region.

Because of the above-described insulator arrangement, the semiconductor switch20is electrically coupled to the outside via the insulating layer32and the inter-channel insulating portion42by means of a significantly low electrostatic capacitance. Thus, the semiconductor switch20can significantly reduce the electrostatic capacitance coupling between the substrate and the drain and source regions and the electrostatic capacitance coupling between the channel and the substrate. As a result, when used as a switch, the semiconductor switch20can achieve significantly small electrostatic capacitance coupling between the signal transmission path and a different region, thereby improving both the high-frequency transmission characteristics and the electrostatic capacitance during the off state. Here, the semiconductor switch20may not necessarily form an SOI device. Furthermore, the inter-channel insulating portion42may not be required to be formed on the insulating layer32in the semiconductor switch20.

The gate insulator48is formed on the semiconductor layer34at least between the drain electrode36and the source electrode38. In other words, the gate insulator48is formed on the channel56. For example, the gate insulator48may be a thin film formed from silicon dioxide. The floating gate50is formed on the gate insulator48, and retains therein charges when the charges are injected. For example, the floating gate50may be a polysilicon member surrounded by a floating gate insulating portion58formed by a silicon oxide film. With such a configuration, the floating gate50can prevent electrons from being emitted outside and retain the electrons therein.

The tunnel gate52is formed on the floating gate50, and is supplied with the driving voltage output from the driving section22. The tunnel gate52provides a tunnel current determined by the supplied driving voltage in order to charge or discharge the floating gate50. For example, the tunnel gate52may be formed on a portion, of the insulator on the upper surface of the floating gate50, whose thickness is reduced to such a degree that the tunnel current can flow.

For example, the area of the tunnel gate52on the floating gate50may be smaller than the area of the floating gate50on the channel56. As another example, the area of the tunnel gate52on the floating gate50may be substantially the same as the area of the floating gate50on the channel56. As yet another example, when the tunnel gate52is formed on and shared by a plurality of floating gates50and a common driving voltage is supplied, the area of the tunnel gate52on the floating gates50may be larger than the area of each floating gate50on the channel56.

The switching device10having the above-described configuration operates as described below when the semiconductor switch20is of an n-channel type. To begin with, with the floating gate50being in the uncharged state, the driving section22applies a driving voltage having a predetermined polarity to the tunnel gate52so that a tunnel current flows in such a direction that charges are injected into the floating gate50. In this way, the floating gate50is charged. For example, the driving section22may apply to the tunnel gate52a voltage of approximately 10 to 20 volts relative to the potential of the source electrode38to provide the tunnel current in such a direction that charges are injected into the floating gate50. After the charging is completed, i.e., after a predetermined amount of charges have been injected into the floating gate50, the driving section22may stop applying the driving voltage. After this, the floating gate50can retain the injected charges therein without requiring the driving voltage being applied.

While the floating gate50is charged, an inversion layer is formed at the interface between the channel56and the gate insulator48. Accordingly, while the floating gate50is charged, the semiconductor switch20allows currents to flow between the drain and the source. In other words, while the floating gate50is charged, the semiconductor switch20electrically connects the drain electrode36and the source electrode38to each other (i.e., the semiconductor switch20is turned on).

Subsequently, with the floating gate50being in the charged state, the driving section22applies to the tunnel gate52a driving voltage having a predetermined polarity so that a tunnel current flows in such a direction that the charges are emitted from the floating gate50. In this manner, the floating gate50is discharged. For example, the driving section22may apply to the tunnel gate52a voltage whose polarity is opposite to the polarity of the voltage applied to charge the floating gate50in order to cause the tunnel current to flow in such a direction that the charges are emitted from the floating gate50. As an example, the driving section22may apply to the tunnel gate52a voltage of approximately −10 to −20 volts relative to the potential of the source electrode38to provide the tunnel current in such a direction that the charges are emitted from the floating gate50. After the discharging is completed, i.e., after the amount of charges in the floating gate50has been reduced to zero or a significantly low level, the driving section22may stop applying the driving voltage. After this, the floating gate50can retain the zero or significantly low charge level without requiring the driving voltage being applied.

While the floating gate50is uncharged, no inversion layer is formed at the interface between the channel56and the gate insulator48. Accordingly, while the floating gate50is uncharged, the semiconductor switch20allows no currents to flow between the drain and the source. In other words, while the floating gate50is uncharged, the semiconductor switch20electrically disconnects the drain electrode36and the source electrode38from each other (i.e., the semiconductor switch20is turned off).

On the other hand, the switching device10operates as described below when the semiconductor switch20is of a p-channel type. When compared with the case where the semiconductor switch20is of an n-channel type, the charges are injected into and emitted from the floating gate50with the polarity of the driving voltage being reversed.

While the floating gate50is charged with a negative potential relative to the potential of the source, an inversion layer is formed at the interface between the channel56and the gate insulator48. Accordingly, while the floating gate50is charged with a negative potential, the semiconductor switch20allows currents to flow between the drain and the source. In other words, while the floating gate50is charged, the semiconductor switch20electrically connects the drain electrode36and the source electrode38to each other (i.e., the semiconductor switch20is turned on).

While the floating gate50is not charged with a negative potential, no inversion layer is formed at the interface between the channel56and the gate insulator48. Accordingly, while the floating gate50is not charged with a negative potential, the semiconductor switch20allows no currents to flow between the drain and the source. In other words, while the floating gate50is uncharged, the semiconductor switch20electrically disconnects the drain electrode36and the source electrode38from each other (i.e., the semiconductor switch20is turned off).

As described above, the driving section22controls the driving voltage to be applied to the tunnel gate52to cause the tunnel gate52to charge or discharge the floating gate50, thereby electrically connecting or disconnecting the drain electrode36and the source electrode38to/from each other. In this manner, the semiconductor switch20can electrically connects or disconnects the first terminal12and the second terminal14to/from each other.

In the switching device10described above, since the capacitance component of the floating gate50is connected in series to the capacitance component of the tunnel gate52, there is a very low gate coupling capacitance (C) between (i) the driving section22and (ii) the drain electrode36, the channel56and the source electrode38. Therefore, the switching device10can decrease the product of the gate coupling capacitance (C) and the on resistance (R) between the drain electrode36and the source electrode38(RC product), thereby enhancing the transmission characteristics of high-frequency signals. Furthermore, the switching device10can accomplish a further lower gate coupling capacitance (C) since the size of the tunnel gate52can be made smaller as long as the tunnel current can at least flow, thereby further improving the transmission characteristics of high-frequency signals.

Being formed from a semiconductor, the switching device10has a longer lifetime and is more reliable than a mechanical relay. Moreover, the switching device10can be turned on/off by means of a voltage, which makes it easy to control the switching device10. The switching device10has a smaller number of constituents than an photo MOSFET relay and can be integrated into a silicon semiconductor integrated circuit. Therefore, the switching device10has a simplified configuration, can contribute to efforts of decreasing the size of devices utilizing the switching device10, and can lower the manufacturing cost.

FIG. 4is a cross-sectional view illustrating a first modification example of the semiconductor switch20relating to the embodiment. The constituents of the switching device10relating to the first modification example have substantially the same configurations and functions as the corresponding constituents assigned with the same reference numerals inFIGS. 1 to 3. Therefore, the following description only mentions the difference between the first modification example and the above embodiment.

In the semiconductor switch20relating to the first modification example, the regions constituting the drain electrode36and the source electrode38extend from the surface of the semiconductor layer34to the boundary between the semiconductor layer34and the insulating layer32. Furthermore, the semiconductor switch20relating to the first modification example does not include the substrate contact electrode40. In other words, the semiconductor switch20forms a fully depleted SOI device. The semiconductor switch20having such a configuration can further decrease the electrostatic capacitance between (i) the semiconductor substrate30and (ii) the drain electrode36, the channel56and the source electrode38.

FIG. 5is a cross-sectional view illustrating a second modification example of the semiconductor switch20relating to the embodiment. The constituents of the switching device10relating to the second modification example have substantially the same configurations and functions as the corresponding constituents assigned with the same reference numerals inFIG. 4. Therefore, the following description only mentions the difference between the first and second modification examples.

The semiconductor switch20relating to the second modification example includes a first floating gate50-1, a second floating gate50-2, a first tunnel gate52-1, and a second tunnel gate52-2. The first floating gate50-1is disposed on a region on the gate insulator48which is closer to the drain electrode36than to the source electrode38. The second floating gate50-2is disposed on a region on the gate insulator48in which the first floating gate50-1is not disposed and which is spaced away by a predetermined gap from the region on which the first floating gate50-1is disposed. In other words, the second floating gate50-2is disposed on a region on the gate insulator48which is closer to the source electrode38than to the drain electrode36, and is positioned away form the first floating gate50-1by a predetermined distance.

The first tunnel gate52-1is disposed on the first floating gate50-1. The second tunnel gate52-2is disposed on the second floating gate50-2. As discussed above, the floating gate50and the tunnel gate52are respectively divided into two portions between the drain and the source in the semiconductor switch20. The switching device10having the above-described configuration can further decrease the electrostatic capacitance between the drain electrode36and the source electrode38during the off state.

FIG. 6is a cross-sectional view illustrating a first semiconductor switch20-1and a second semiconductor switch20-2relating to a third modification example of the embodiment. The constituents of the switching device10relating to the third modification example have substantially the same configurations and functions as the corresponding constituents assigned with the same reference numerals inFIG. 4. Therefore, the following description only mentions the difference between the first and third modification examples.

The switching device10relating to the third modification example includes a first semiconductor switch20-1and a second semiconductor switch20-2. The drain electrode36of the first semiconductor switch20-1is connected to the first terminal12through interconnections. The source electrode38of the second semiconductor switch20-2is connected to the second terminal14through interconnections. The source electrode38of the first semiconductor switch20-1is connected to the drain electrode36of the second semiconductor switch20-2through interconnections. Since the two semiconductor switches20are connected in cascade, the switching device10having the above-described configuration can further reduce the electrostatic capacitance between the first terminal12and the second terminal14during the off state.

FIG. 7illustrates the configuration of a fourth modification example of the switching device10relating to the embodiment. The constituents of the switching device10relating to the fourth modification example have substantially the same configurations and functions as the corresponding constituents assigned with the same reference numbers shown inFIG. 1. Therefore, the following description only mentions the difference between the fourth modification example and the embodiment.

The switching device10relating to the fourth modification example includes a third semiconductor switch20-3that is of an n-channel type and a fourth semiconductor switch20-4that is of a p-channel type. The third and fourth semiconductor switches20-3and20-4shown inFIG. 7have the same configurations and functions as the semiconductor switch20shown inFIGS. 1 to 3. Therefore, the following description only mentions the difference between the fourth modification example and the embodiment. The n-channel third semiconductor switch20-3and the p-channel fourth semiconductor switch20-4are each connected at the drain electrode36thereof to the first terminal12and at the source electrode38thereof to the second terminal14.

The driving section22applies driving voltages with different polarities to the tunnel gate52of the third semiconductor switch20-3and the tunnel gate52of the fourth semiconductor switch20-4in such a manner that one of the third and fourth semiconductor switches20-3and20-4is charged while the other is discharged. According to such a configuration, when one of the third and fourth semiconductor switches20-3and20-4is turned on, the other is also turned on. Similarly, when one of the third and fourth semiconductor switches20-3and20-4is turned off, the other is also turned off. In other words, the third and fourth semiconductor switches20-3and20-4can be both turned on or off. The switching device10relating to the fourth modification example can improve the DC transmission characteristics during the on state and reduce the transmission distortion during the on state.

FIG. 8illustrates the configuration of a fifth modification example of the switching device10relating to the embodiment. The constituents of the switching device10relating to the fifth modification example have substantially the same configurations and functions as the corresponding constituents assigned with the same reference numerals inFIGS. 1 to 3. Therefore, the following description only mentions the difference between the fifth modification example and the embodiment.

According to the fifth modification example, the semiconductor switch20includes a plurality of tunnel gates52formed in different regions on the floating gate50. Furthermore, the switching device10relating to the fifth modification example additionally includes a selecting section64and a supply section66. The selecting section64selects at least one of the tunnel gates52. For example, the selecting section64may select one of the tunnel gates52or more than one of the tunnel gates52.

The supply section66supplies the driving voltage output from the driving section22to the tunnel gate52selected by the selecting section64. For example, the supply section66may switch the driving voltage destination among the tunnel gates52by means of a switch that turns on the connecting path that supplies the driving voltage to the selected tunnel gate52and turns off the connecting paths that supply the driving voltage to the other tunnel gates52.

The above-mentioned switch may turn on/off the connecting paths between the driving section22and the tunnel gates52by means of a plurality of pass transistors. The pass transistors may be smaller in size than the semiconductor switch20. For example, the pass transistors may be approximately a hundredth of the semiconductor switch20in size. According to such a configuration, all of the pass transistors are turned off except for the pass transistor to supply the driving voltage to the selected tunnel gate52. Therefore, the provision of the pass transistors newly adds only a low capacitance to the gate coupling capacitance (C) of the semiconductor switch20. According to the switching device10having the above-described configuration, when one of the tunnel gates52deteriorates and cannot provide a sufficient tunnel current, one of the remaining tunnel gates52that have not deteriorated can be alternatively selected. In such a manner, the fifth modification example can increase the lifetime and reliability.

The switching device10relating to the fifth modification example may further include a diagnosing section68. The diagnosing section68diagnoses the characteristics of the connection and disconnection between the first terminal12and the second terminal14observed when each tunnel gate52is selected. For example, the diagnosing section68may detect the characteristics of the connection and the disconnection between the first terminal12and the second terminal14and diagnose whether each tunnel gate52can be used based on the detection result. For example, the diagnosing section68may detect the on resistance and the off resistance between the first terminal12and the second terminal14observed when each tunnel gate52is selected, and diagnose that the associated tunnel gate52can be used when the detected on resistance is no greater than a predetermined first threshold value and the detected off resistance is no lower than a predetermined second threshold value. For example, the diagnosing section68may directly detect and measure the on resistance and the off resistance between the first terminal12and the second terminal14. As an alternative example, the diagnosing section68may supply a signal to the switching device10with the use of a driver circuit or a DC test unit and measure the characteristics of the output signal.

When the switching device10includes the diagnosing section68, the selecting section64may select one of the tunnel gates52depending on the diagnosis made by the diagnosing section68. For example, the selecting section64may select one of the tunnel gates52which is diagnosed usable. In this way, the switching device10can eliminate one or more defective tunnel gates52and select one or more usable tunnel gates52.

Alternatively to the above-described diagnosing procedure, the diagnosing section68may diagnose the characteristics of the connection and the disconnection between the first terminal12and the second terminal14observed when a first tunnel gate52is selected. For example, the diagnosing section68may diagnose the characteristics of the connection and the disconnection between the first terminal12and the second terminal14observed when a first tunnel gate52that is used in an immediately preceding test is selected. The selecting section64may select a second tunnel gate52when the diagnosis of the characteristics observed when the first tunnel gate52is selected indicates a defective result. For example, the selecting section64may select a second tunnel gate52that has not been used in past tests. With such a configuration, the switching device10can sequentially select a next new tunnel gate52when the characteristics of a particular tunnel gate52age over time.

FIG. 9illustrates the configuration of a sixth modification example of the semiconductor switch20relating to the embodiment. The constituents of the switching device10relating to the sixth modification example have substantially the same configurations and functions as the corresponding constituents assigned with the same reference numerals shown inFIGS. 1 to 3. Therefore, the following description only mentions the difference between the sixth modification example and the embodiment.

The switching device10relating to the sixth modification example may additionally include a microstrip substrate70. The microstrip substrate70includes a first semiconductor layer72, a first insulating layer74, a second semiconductor layer76, a ground layer78, an inter-layer insulator80, an interconnection layer81in which a first transmission line82and a second transmission line84are formed, and vias86.

For example, the first semiconductor layer72may be a silicon substrate. The first insulating layer74is disposed on the first semiconductor layer72, and insulates the upper layer, i.e., the second semiconductor layer76from the lower layer, i.e., the first semiconductor layer72. The second semiconductor layer76is disposed on the first insulating layer74. The second semiconductor layer76may be a silicon film, for example.

The ground layer78is disposed on the second semiconductor layer76. The ground layer78is formed from an electrically conductive material, and connected to the ground. The inter-layer insulator80is disposed on the ground layer78, and insulates the upper layer, i.e., the interconnection layer81from the lower layer, i.e., the ground layer78. The interconnection layer81has interconnections formed therein. The interconnection layer81may be formed by a plurality of layers. When the interconnection layer81is formed by a plurality of interconnection layers81, the microstrip substrate70may include an inter-layer insulator80between adjacent interconnection layers81to insulate the upper interconnection layer81from the lower interconnection layer81. Here, at least one of the interconnection layers81includes the first and second transmission lines82and84.

The first and second transmission lines82and84are metal interconnections or the like formed on the inter-layer insulator80that transmit signals. The first and second transmission lines82and84form a microstrip relative to the ground layer78. Therefore, the first and second transmission lines82and84can transmit high frequency signals. Alternatively, the ground layer78may be formed in the interconnection layer81. Furthermore, the first semiconductor layer76may have interconnections formed therein.

The first transmission line82is connected at one end thereof to the first terminal12and at the other end thereof to one of the drain electrode36and the source electrode38of the semiconductor switch20formed on the microstrip substrate70. The second transmission line84is connected at one end thereof to the second terminal14and at the other end thereof to the other of the source electrode38and the drain electrode36of the semiconductor switch20formed on the microstrip substrate70, which is not connected to the second transmission line84. Note that the first and second transmission lines82and84may be connected to the first and second terminal12and14that are disposed on a different substrate, through pads formed on the surface of the microstrip substrate70. Alternatively, the first and second transmission lines82and84may be connected to the first and second terminals12and14that are provided in a different integrated circuit within the microstrip substrate70.

The vias86extend through the inter-layer insulator80and the interconnection layer81, and electrically connect the ground layer78to the ground pads formed on the surface of the microstrip substrate70. For example, the ground pads may be provided to mount the microstrip substrate70to a different substrate by means of, for example, flip-chip bonding.

The above-described switching device10relating to the sixth modification example can reduce interconnections such as lead frames and bonding wires. Therefore, the switching device10can decrease the floating inductance and capacitance and further reduce the number of impedance mismatching points. Note that the first and second transmission lines82and84may be coplanar lines or differently structured transmission lines formed on a semiconductor substrate, instead of being microstrips.

FIG. 10illustrates the configuration of a testing apparatus100relating to an embodiment of the present invention. The testing apparatus100tests a device under test200. For example, the testing apparatus100conducts a logic test and a DC test on the device under test200. The testing apparatus100includes a test signal generating section110, a driver120, a comparator130, a judging section140, a DC test unit150, a fifth semiconductor switch20-5, and a sixth semiconductor switch20-6. Here, the fifth and sixth semiconductor switches20-5and20-6shown inFIG. 10have the same configurations and functions as the semiconductor switch20shown inFIGS. 1 to 3. Therefore, the following description only mentions the difference between the present embodiment and the previously discussed embodiment.

The test signal generating section110generates a test signal to be input into the device under test200. For example, the test signal generating section110may include a pattern generator and a waveform shaper. The pattern generator generates a test pattern designating the waveform of the test signal. The waveform shaper generates the test signal in accordance with the test pattern output from the pattern generator.

The driver120supplies the test signal generated by the test signal generating section110to the device under test200via an input/output (I/O) terminal160. The comparator130is connected at the input end thereof to the output end of the driver120, receives the output signal from the device under test200via the I/O terminal160, and detects the logic of the received output signal. The judging section140judges the output signal detected by the comparator130. In one example, the judging section140judges the acceptability of the device under test200by referring to the logic of the output signal detected by the comparator130. The DC test unit150supplies a predetermined DC voltage to the device under test200via the I/O terminal160. For example, the testing apparatus100may use the DC test unit150to perform a voltage test through current application or a current test through voltage application.

The fifth semiconductor switch20-5is positioned between the first terminal12and the second terminal14, which are respectively (i) at least one of the output end of the driver120and the input end of the comparator130and (ii) the input and output end of the device under test200. The fifth semiconductor switch20-5electrically connects or disconnects the first and second terminals12and14to/from each other. According to the present embodiment, the fifth semiconductor switch20-5is positioned between the I/O terminal160and a connection point connecting together the output end of the driver120and the input end of the comparator130. According to the present embodiment, the fifth semiconductor switch20-5is turned on when the testing apparatus100performs a logic test and turned off when the testing apparatus100does not perform a logic test. In other words, the fifth semiconductor switch20-5functions as an I/O relay that turns on/off the passage of the test signal and the output signal.

The sixth semiconductor switch20-6is positioned between the first terminal12and the second terminal14, which are respectively (i) the output end of the DC test unit150and (ii) the input and output end of the device under test200. The sixth semiconductor switch20-6electrically connects or disconnects the first and second terminals12and14to/from each other. According to the present embodiment, the sixth semiconductor switch20-6is positioned between the I/O terminal160and the output end of the DC test unit150. According to the present embodiment, the sixth semiconductor switch20-6is turned on when the testing apparatus100performs a DC test and turned off when the testing apparatus100does not perform a DC test. In other words, the sixth semiconductor switch20-6functions as a DC relay that turns on/off the passage of the DC voltage.

Utilizing the fifth semiconductor switch20-5, which exhibits a small RC product, as the I/O relay, the testing apparatus100with the above-described configuration only causes low distortion when transmitting high-frequency test signals and output signals and low loss when transmitting test signals and output signals whose frequency falls within a wide range from the DC to approximately several dozen GHz. In addition, since the fifth semiconductor switch20-5has a small number of impedance mismatching points, the testing apparatus100can accurately achieve a predetermined impedance (for example, 50Ω) for the transmission path between (i) the device under test200and (ii) the driver120and the comparator130. Furthermore, since the fifth semiconductor switch20-5has a low DC on resistance, the testing apparatus100can reduce the loss and waveform distortion of the test signal and the output signal.

Utilizing the sixth semiconductor switch20-6, which has a low electrostatic capacitance during the off state, as the DC relay, the testing apparatus100with the above-described configuration can reduce the influence made by the sixth semiconductor switch20-6, during a logic test, on the impedance of the transmission path connecting the device under test200to the driver120and the comparator130. In addition, since the sixth semiconductor switch20-6has a low DC on resistance, the testing apparatus100can reduce the difference in DC level between the output end of the DC test unit150and the input and output end of the device under test200.

Since the fifth and sixth semiconductor switches20-5and20-6have a long lifetime, the testing apparatus100can obtain a long mean down time. Furthermore, since the fifth and sixth semiconductor switches20-5and20-6have a small size and a simple configuration, the testing apparatus100can reduce the device size and lower the manufacturing cost.

The claims, specification and drawings describe the processes of an apparatus, a system, a program and a method by using the terms such as operations, procedures, steps and stages. When a reference is made to the execution order of the processes, wording such as “before” or “prior to” is not explicitly used. The processes may be performed in any order unless an output of a particular process is used by the following process. In the claims, specification and drawings, a flow of operations may be explained by using the terms such as “first” and “next” for the sake of convenience. This, however, does not necessarily indicate that the operations should be performed in the explained order.