SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF

A method of forming a semiconductor device includes forming a fin over a substrate, the fin comprising alternately stacking first semiconductor layers and second semiconductor layers, removing the first semiconductor layers to form spaces each between the second semiconductor layers, forming a gate dielectric layer wrapping around each of the second semiconductor layers, forming a fluorine-containing layer on the gate dielectric layer, performing an anneal process to drive fluorine atoms from the fluorine-containing layer into the gate dielectric layer, removing the fluorine-containing layer, and forming a metal gate on the gate dielectric layer.

BACKGROUND

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 230 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, “around,” “about,” “approximately,” or “substantially” may generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated.

In the present disclosure, a method for fabricating a gate dielectric layer wrapping around the channels, in which the gate dielectric layer includes fluorine atoms, for a GAA FET and a stacked channel FET are provided. In this disclosure, a source/drain refers to a source and/or a drain. It is noted that in the present disclosure, a source and a drain are interchangeably used and the structures thereof are substantially the same.

In the foregoing process, however, it is difficult to precisely control the fluorine atoms in the gate dielectric layer in different device regions. Since the fluorine atoms can influence the threshold voltage of the device, it is difficult to precisely control the threshold voltage of devices with different types. In view of this, the present disclosure provides a method for fabricating a gate dielectric layer free from fluorine atoms in a first device region and including fluorine atoms in a second device region, which can tune the threshold voltage more precisely for devices with different types.

The present disclosure is generally related to integrated circuit (IC) structures and methods of forming the same, and more particularly to fabricating gate-all-around (GAA) transistors having gate dielectric layer free from fluorine atoms in a first device region and including fluorine atoms in a second device region. It is also noted that the present disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two-sides of a channel region. These multi-gate devices may include a p-type metal-oxide-semiconductor device or an n-type metal-oxide-semiconductor device. Specific examples may be presented and referred to herein as FinFET, on account of their fin-like structure. Also presented herein are embodiments of a type of multi-gate transistor referred to as a gate-all-around (GAA) device. A GAA device includes any device that has its gate structure, or portion thereof, formed on 4-sides of a channel region (e.g., surrounding a portion of a channel region). Devices presented herein also include embodiments that have channel regions disposed in nanosheet channel(s), nanowire channel(s), and/or other suitable channel configuration. Presented herein are embodiments of devices that may have one or more channel regions (e.g., nanosheets) associated with a single, contiguous gate structure. However, one of ordinary skill would recognize that the teaching can apply to a single channel (e.g., single nanosheet) or any number of channels. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.

FIG.1illustrates an example of GAA-FETs (e.g., nanowire FETs, nanosheet FETs, or the like) in a three-dimensional view, in accordance with some embodiments. The GAA-FETs comprise nanostructures104(e.g., nanosheets, nanowires, nanorings, nanoslabs, or other structures having nano-scale size (e.g., a few nanometers)) over fins102on a substrate100(e.g., a semiconductor substrate), wherein the nanostructures104act as channel regions for the GAA-FETs. The nanostructure104may include p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions106are disposed between adjacent fins102, which may protrude above and from between neighboring isolation regions106. Although the isolation regions106are described/illustrated as being separate from the substrate100, as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of the fins102are illustrated as being single, continuous materials with the substrate100, the bottom portion of the fins102and/or the substrate100may comprise a single material or a plurality of materials. In this context, the fins102refer to the portion extending between the neighboring isolation regions106.

Gate dielectrics110are over top surfaces of the fins102and along top surfaces, sidewalls, and bottom surfaces of the nanostructures104. Gate electrodes112are over the gate dielectrics110. Epitaxial source/drain regions108are disposed on the fins102on opposing sides of the gate dielectrics110and the gate electrodes112.

FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of a gate electrode112and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions108of a GAA-FET. Cross-section B-B′ is perpendicular to cross-section A-A′ and is parallel to a longitudinal axis of a fin102of the GAA-FET and in a direction of, for example, a current flow between the epitaxial source/drain regions108of the GAA-FET. Cross-section C-C′ is parallel to cross-section A-A′ and extends through epitaxial source/drain regions of the GAA-FETs. Subsequent figures refer to these reference cross-sections for clarity.

Some embodiments discussed herein are discussed in the context of GAA-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs).

FIGS.2through5,6A,13A,14A, and15Aillustrate reference cross-section A-A′ illustrated inFIG.1that extends through a gate region along a longitudinal axis of the gate region.FIGS.6B,7B,8B,9B,10B,11B,12B,13B,14B, and15Billustrate reference cross-section B-B′ illustrated inFIG.1that extends through a fin along a longitudinal axis of the fin.FIGS.7A,8A,9A,10A,11A,12A, and13Cillustrate reference cross-section C-C′ illustrated inFIG.1that extends through source/drain regions along the longitudinal direction of the gate region.FIGS.16,17,18,19,20A,21A, and21Bare cross-sectional views at intermediate fabrication stages, illustrating reference cross-section A-A′ illustrated inFIG.1that extends through a gate region along a longitudinal axis of the gate region.FIG.22is a graph illustrating a fluorine concentration in the high-k gate dielectric layer, the interfacial layer and the nanostructure in accordance with some embodiments.FIGS.23,24,25,26,27and28are cross-sectional views at intermediate fabrication stages, illustrating reference cross-section A-A′ illustrated inFIG.1that extends through a gate region along a longitudinal axis of the gate region.

The substrate100has a first device region1001and a second device region1002. The first device region1001is a region in which first transistors will reside, and the second device region1002is a region in which second transistors will reside. In some embodiments, the first transistors are different from the second transistors at least in threshold voltage. For example, first transistors in the first device region1001may be HV devices (e.g., I/O devices), and second transistors in the second device region1002may be LV devices (e.g., logic devices). In some other embodiments, the first transistors are different from the second transistors at least in conductivity type. For example, first device region1001can be for forming n-type devices, such as NMOS transistors, e.g., n-type GAA-FETs, and the second device region1002can be for forming p-type devices, such as PMOS transistors, e.g., p-type GAA-FETs.

The first device region1001may be separated from the second device region1002, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the first device region1001and the second device region1002. Although one first device region1001and one second device region1002are illustrated, any number of first device regions1001and second device regions1002may be provided.

Further inFIG.2, a multi-layer stack201is formed over the substrate100. The multi-layer stack201includes alternating layers of first semiconductor layers202A-C (collectively referred to as first semiconductor layers202) and second semiconductor layers204A-C (collectively referred to as second semiconductor layers204). For purposes of illustration and as discussed in greater detail below, the first semiconductor layers202will be removed and the second semiconductor layers204will be patterned to form channel regions of GAA-FETs.

The multi-layer stack201is illustrated as including three layers of each of the first semiconductor layers202and the second semiconductor layers204for illustrative purposes. In some embodiments, the multi-layer stack201may include any number of the first semiconductor layers202and the second semiconductor layers204. Each of the layers of the multi-layer stack201may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the second semiconductor layers204may be formed of a semiconductor material suitable for serving as channel regions of GAA-FETs, such as silicon, silicon carbon, silicon germanium, or the like.

The first semiconductor materials and the second semiconductor materials may be materials having a high-etch selectivity to one another. As such, the first semiconductor layers202of the first semiconductor material may be removed without significantly removing the second semiconductor layers204of the second semiconductor material, thereby allowing the second semiconductor layers204to serve as channel regions of GAA-FETs.

Referring now toFIG.3, fin structures206are formed in the substrate100and nanostructures203are formed in the multi-layer stack201, in accordance with some embodiments. In some embodiments, the nanostructures203and the fin structures206may be formed in the multi-layer stack201and the substrate100, respectively, by etching trenches in the multi-layer stack201and the substrate100. Each fin structure206and overlying nanostructures203can be collectively referred to as a fin extending from the substrate100. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Forming the nanostructures203by etching the multi-layer stack201may further define first nanostructures202A-C (collectively referred to as the first nanostructures202) from the first semiconductor layers202and define second nanostructures204A-C (collectively referred to as the second nanostructures204) from the second semiconductor layers204. The first nanostructures202and the second nanostructures204may further be collectively referred to as nanostructures203.

FIG.3illustrates the fin structures206in the first device region1001and the second device region1002as having substantially equal widths for illustrative purposes. In some embodiments, widths of the fin structures206in the first device region1001may be greater or thinner than the fin structures206in the second device region1002. Further, while each of the fin structures206and the nanostructures203are illustrated as having a consistent width throughout, in other embodiments, the fin structures206and/or the nanostructures203may have tapered sidewalls such that a width of each of the fin structures206and/or the nanostructures203continuously increases in a direction towards the substrate100. In such embodiments, each of the nanostructures203may have a different width and be trapezoidal in shape.

InFIG.4, shallow trench isolation (STI) regions208are formed adjacent the fin structures206. The STI regions208may be formed by depositing an insulation material over the substrate100, the fin structures206, and nanostructures203, and between adjacent fin structures206. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by an FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers the nanostructures203. Although the insulation material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along a surface of the substrate100, the fin structures206, and the nanostructures203. Thereafter, a fill material, such as those discussed above may be formed over the liner.

A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures203. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the nanostructures203such that top surfaces of the nanostructures203and the insulation material are level after the planarization process is complete.

The insulation material is then recessed to form the STI regions208. The insulation material is recessed such that upper portions of fin structures206in the first and second device regions1001and1002and protrude from between neighboring STI regions208. Further, the top surfaces of the STI regions208may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions208may be formed flat, convex, and/or concave by an appropriate etch. The STI regions208may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fin structures206and the nanostructures203). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used.

The process described above with respect toFIGS.2through4is just one example of how the fin structures206and the nanostructures203may be formed. In some embodiments, the fin structures206and/or the nanostructures203may be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate100, and trenches can be etched through the dielectric layer to expose the underlying substrate100. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fin structures206and/or the nanostructures203. The epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together.

Additionally, the first semiconductor layers (and resulting nanostructures202) and the second semiconductor layers (and resulting nanostructures204) are illustrated and discussed herein as comprising the same materials in the second device region1002and the first device region1001for illustrative purposes only. As such, in some embodiments one or both of the first semiconductor layers and the second semiconductor layers may be different materials or formed in a different order in the first and second device regions1001and1002.

Further inFIG.4, appropriate wells (not separately illustrated) may be formed in the fin structures206, the nanostructures203, and/or the STI regions208. In some embodiments with different well types in different device regions1001and1002, different implant steps for the first device region1001and the second device region1002may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over the fin structures206and the STI regions208in the first device region1001and the second device region1002. The photoresist is patterned to expose the second device region1002. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a first impurity (e.g., n-type impurity such as phosphorus, arsenic, antimony, or the like) implant is performed in the second device region1002, and the photoresist may act as a mask to substantially prevent the first impurities from being implanted into the first device region1001. After the implant, the photoresist is removed, such as by an acceptable ashing process.

Following or prior to the implanting of the second device region1002, a photoresist or other masks (not separately illustrated) is formed over the fin structures206, the nanostructures203, and the STI regions208in the first device region1001and the second device region1002. The photoresist is then patterned to expose the first device region1001. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a second impurity (e.g., p-type impurity such as boron, boron fluoride, indium, or the like) implant may be performed in the first device region1001, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the second device region1002. After the implant, the photoresist may be removed, such as by an acceptable ashing process.

After one or more well implants of the first device region1001and the second device region1002, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.

InFIG.5, a dummy dielectric layer210is formed on the fin structures206and/or the nanostructures203. The dummy dielectric layer210may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer212is formed over the dummy dielectric layer210, and a mask layer214is formed over the dummy gate layer212. The dummy gate layer212may be deposited over the dummy dielectric layer210and then planarized, such as by a CMP. The mask layer214may be deposited over the dummy gate layer212. The dummy gate layer212may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer212may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer212may be made of other materials that have a high etching selectivity from the etching of isolation regions. The mask layer214may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer212and a single mask layer214are formed across the first device region1001and the second device region1002. It is noted that the dummy dielectric layer210is shown covering only the fin structures206and the nanostructures203for illustrative purposes only. In some embodiments, the dummy dielectric layer210may be deposited such that the dummy dielectric layer210covers the STI regions208, such that the dummy dielectric layer210extends between the dummy gate layer212and the STI regions208.

FIGS.6A through24illustrate various following steps in the manufacturing of embodiment devices.FIGS.6A,7A,8A,9A,10A,11A,12A,13A,13C,14A, and15Aillustrate features in either the first device regions1001or the second device regions1002. InFIGS.6A and6B, the mask layer214(seeFIG.5) may be patterned using acceptable photolithography and etching techniques to form masks218. The pattern of the masks218then may be transferred to the dummy gate layer212and to the dummy dielectric layer210to form dummy gates216and dummy gate dielectrics211, respectively. The dummy gates216cover respective channel regions of the fin structures206. The pattern of the masks218may be used to physically separate each of the dummy gates216from adjacent dummy gates216. The dummy gates216may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective fin structures206.

InFIGS.7A and7B, a first spacer layer220and a second spacer layer222are formed over the structures illustrated inFIGS.6A and6B, respectively. The first spacer layer220and the second spacer layer222will be subsequently patterned to act as spacers for forming self-aligned source/drain regions. InFIGS.7A and7B, the first spacer layer220is formed on top surfaces of the STI regions208; top surfaces and sidewalk of the fin structures206, the nanostructures203, and the masks218; and sidewalls of the dummy gates216and the dummy gate dielectric211. The second spacer layer222is deposited over the first spacer layer220. The first spacer layer220may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, using techniques such as thermal oxidation or deposited by CVD, ALD, or the like. The second spacer layer222may be formed of a material having a different etch rate than the material of the first spacer layer220, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.

InFIGS.8A and8B, the first spacer layer220and the second spacer layer222are etched to form first spacers221and second spacers223. As will be discussed in greater detail below, the first spacers221and the second spacers223act to self-align subsequently formed source drain regions, as well as to protect sidewalls of the fin structures206and/or nanostructure203during subsequent processing. The first spacer layer220and the second spacer layer222may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of the second spacer layer222has a different etch rate than the material of the first spacer layer220, such that the first spacer layer220may act as an etch stop layer when patterning the second spacer layer222and such that the second spacer layer222may act as a mask when patterning the first spacer layer220. For example, the second spacer layer222may be etched using an anisotropic etch process wherein the first spacer layer220acts as an etch stop layer, wherein remaining portions of the second spacer layer222form second spacers223as illustrated inFIG.8A. Thereafter, the second spacers223acts as a mask while etching exposed portions of the first spacer layer220, thereby forming first spacers221as illustrated inFIG.8A.

As illustrated inFIG.8A, the first spacers221and the second spacers223are disposed on sidewalls of the fin structures206and/or nanostructures203. In some embodiments, the spacers221and223only partially remain on sidewalls of the fin structures206. In some embodiments, no spacer remains on sidewalls of the fin structures206. As illustrated inFIG.8B, in some embodiments, the second spacer layer222may be removed from over the first spacer layer220adjacent the masks218, the dummy gates216, and the dummy gate dielectrics211, and the first spacers221are disposed on sidewalls of the masks218, the dummy gates216, and the dummy gate dielectrics211. In other embodiments, a portion of the second spacer layer222may remain over the first spacer layer220adjacent the masks218, the dummy gates216, and the dummy gate dielectrics211.

The above disclosure generally describes a process of forming spacers. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the first spacers221may be patterned prior to depositing the second spacer layer222), additional spacers may be formed and removed, and/or the like. Furthermore, devices in first device region1001and devices in the second device region1002may be formed using different structures and steps.

InFIGS.9A and9B, source/drain recesses226are formed in the fin structures206, the nanostructures203, and the substrate100, in accordance with some embodiments. Epitaxial source/drain regions will be subsequently formed in the source/drain recesses226. The source/drain recesses226may extend through the first nanostructures202and the second nanostructures204, and into the substrate100. As illustrated inFIG.9A, bottom surfaces of the source/drain recesses226may be level with top surfaces of the STI regions58, as an example. In some other embodiments, the fin structures206may be etched such that bottom surfaces of the source/drain recesses226are disposed below the top surfaces of the STI regions208, or above the top surfaces of the STI regions208. The source/drain recesses226may be formed by etching the fin structures206, the nanostructures203, and the substrate100using anisotropic etching processes, such as RIE, NBE, or the like. The first spacers221, the second spacers223, and the masks218mask portions of the fin structures206, the nanostructures203, and the substrate100during the etching processes used to form the source/drain recesses226. A single etch process or multiple etch processes may be used to etch each layer of the nanostructures203and/or the fin structures206. Timed etch processes may be used to stop the etching of the source/drain recesses226after the source/drain recesses226reach a target depth.

InFIGS.10A and10B, portions of sidewalls of the layers of the multi-layer stack201formed of the first semiconductor materials (e.g., the first nanostructures202) exposed by the source/drain recesses226are etched to form sidewall recesses228between corresponding second nanostructures204. Although sidewalls of the first nanostructures202in the sidewall recesses228are illustrated as being straight inFIG.10B, the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like. In some embodiments in which the first nanostructures202include, e.g., SiGe, and the second nanostructures204include, e.g., Si or SiC, a dry etch process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch sidewalls of the first nanostructures202.

InFIGS.11A-11B, inner spacers230are formed in the sidewall recess228. The inner spacers230may be formed by depositing an inner spacer layer (not separately illustrated) over the structures illustrated inFIGS.10A and10B. The inner spacers230act as isolation features between subsequently formed source/drain regions and gate structure. As will be discussed in greater detail below, source/drain regions will be formed in the recesses226, and the first nanostructures202will be replaced with corresponding gate structures.

The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The inner spacer layer may then be anisotropically etched to form the inner spacers230. Although outer sidewalls of the inner spacers230are illustrated as being flush with sidewalls of the second nanostructures204, the outer sidewalls of the inner spacers230may extend beyond or be recessed from sidewalls of the second nanostructures204.

Moreover, although the outer sidewalls of the inner spacers230are illustrated as being straight inFIG.11B, the outer sidewalls of the inner spacers230may be concave or convex. The inner spacer layer may be etched by an anisotropic etching process, such as RIE, NBE, or the like. The inner spacers230may be used to prevent damage to subsequently formed source/drain regions (such as the epitaxial source/drain regions232, discussed below with respect toFIGS.12A-12B) by subsequent etching processes, such as etching processes used to form gate structures.

InFIGS.12A-12B, epitaxial source/drain regions232are formed in the source/drain recesses226. In some embodiments, the epitaxial source/drain regions232may exert stress on the second nanostructures204, thereby improving device performance. As illustrated inFIG.12B, the epitaxial source/drain regions232are formed in the source/drain recesses226such that each dummy gate216is disposed between respective neighboring pairs of the epitaxial source/drain regions232. In some embodiments, the first spacers221are used to separate the epitaxial source/drain regions232from the dummy gates216and the inner spacers230are used to separate the epitaxial source/drain regions232from the first nanostructures202by an appropriate lateral distance so that the epitaxial source/drain regions232do not short out with subsequently formed gates of the resulting GAA-FETs.

In some embodiments, the epitaxial source/drain regions232may include any acceptable material appropriate for n-type GAA-FETs. For example, if the second nanostructures204are silicon, the epitaxial source/drain regions232may include materials exerting a tensile strain on the second nanostructures204, such as silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. In some embodiments, the epitaxial source/drain regions232may include any acceptable material appropriate for p-type GAA-FETs. For example, if the second nanostructures204are silicon, the epitaxial source/drain regions232may comprise materials exerting a compressive strain on the second nanostructures204, such as silicon germanium, boron doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions232may have surfaces raised from respective upper surfaces of the nanostructures203and may have facets.

The epitaxial source/drain regions232may be implanted with dopants to form source/drain regions, followed by an anneal. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions232may be in situ doped during growth.

As a result of the epitaxy processes used to form the epitaxial source/drain regions232, upper surfaces of the epitaxial source/drain regions232have facets which expand laterally outward beyond sidewalls of the nanostructures203. In some embodiments, these facets cause adjacent epitaxial source/drain regions232to merge as illustrated byFIG.12A. In some other embodiments, adjacent epitaxial source/drain regions232remain separated after the epitaxy process is completed. In the embodiments illustrated inFIG.12A, the first spacers221may be formed to a top surface of the STI regions208thereby blocking the lateral epitaxial growth. In some other embodiments, the first spacers221may cover portions of the sidewalls of the nanostructures203further blocking the epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers221may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region58.

The epitaxial source/drain regions232may comprise one or more semiconductor material layers. For example, the epitaxial source/drain regions232may comprise a first semiconductor material layer232A, a second semiconductor material layer232B, and a third semiconductor material layer232C. Any number of semiconductor material layers may be used for the epitaxial source/drain regions232. Each of the first semiconductor material layer232A, the second semiconductor material layer232B, and the third semiconductor material layer232C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer232A may have a dopant concentration less than the second semiconductor material layer232B and greater than the third semiconductor material layer232C. In embodiments in which the epitaxial source/drain regions232comprise three semiconductor material layers, the first semiconductor material layer232A may be deposited, the second semiconductor material layer232B may be deposited over the first semiconductor material layer232A, and the third semiconductor material layer232C may be deposited over the second semiconductor material layer232B.

InFIGS.13A-13C, an interlayer dielectric (ILD) layer236is deposited over the structure illustrated inFIGS.12A-12B. The ILD layer236may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)234is disposed between the ILD layer236and the epitaxial source/drain regions232, the masks218, and the first spacers221. The CESL234may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying ILD layer236.

InFIGS.14A-14B, a planarization process, such as a CMP, may be performed to level the top surface of the ILD layer236with the top surfaces of the dummy gates216or the masks218. The planarization process may also remove the masks218on the dummy gates216, and portions of the first spacers221along sidewalls of the masks218. After the planarization process, top surfaces of the dummy gates216, the first spacers221, and the ILD layer236are level within process variations. Accordingly, the top surfaces of the dummy gates216are exposed through the ILD layer236. In some embodiments, the masks218may remain, in which case the planarization process levels the top surface of the ILD layer236with top surface of the masks218and the first spacers221.

InFIGS.15A and15B, the dummy gates216, and the masks218if present, are removed in one or more etching steps, so that gate trenches238are formed between corresponding gate spacers221. In some embodiments, portions of the dummy gate dielectrics211in the gate trenches238are also be removed. In some embodiments, the dummy gates216and the dummy gate dielectrics211are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates216at a faster rate than the ILD layer236or the first spacers221. Each gate trench238exposes and/or overlies portions of nanostructures204, which act as channel regions in subsequently completed GAA-FETs. The nanostructures204which act as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions232. During the removal, the dummy gate dielectrics211may be used as etch stop layers when the dummy gates216are etched. The dummy gate dielectrics211may then be removed after the removal of the dummy gates216.

The first nanostructures202in the gate trenches are removed by an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the first nanostructures202, as shown inFIG.16. Stated differently, the first nanostructures202are removed by using a selective etching process that etches the first nanostructures202at a faster etch rate than it etches the second nanostructures204, thus forming spaces between the second nanostructures204(also referred to as sheet-sheet spaces if the nanostructures204are nanosheets). This step can be referred to as a channel release process. At this interim processing step, the spaces between second nanostructures204may be filled with ambient environment conditions (e.g., air, nitrogen, etc). In some embodiments, the second nanostructures204can be referred to as nanosheets, nanowires, nanoslabs, nanorings having nano-scale size (e.g., a few nanometers), depending on their geometry. For example, in some embodiments the second nanostructures204may be trimmed to have a substantial rounded shape (i.e., cylindrical) due to the selective etching process for completely removing the first nanostructures202. In that case, the resultant second nanostructures204can be called nanowires.

In embodiments in which the first nanostructures202include, e.g., SiGe, and the second nanostructures204include, e.g., Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH) or the like may be used to remove the first nanostructures202. In some embodiments, both the channel release step and the previous step of laterally recessing first nanostructures202(i.e., the step as illustrated inFIGS.10A-10B) use a selective etching process that etches first nanostructures202(e.g., SiGe) at a faster etch rate than etching second nanostructures204(e.g., Si), and therefore these two steps may use the same etchant chemistry in some embodiments. In this case, the etching time/duration of channel release step is longer than the etching time/duration of the previous step of laterally recessing first nanostructures202, so as to completely remove the sacrificial nanostructures202.

An interfacial layer240and a gate dielectric layer242are deposited conformally in the gate trenches238in both the first device region1001and the second device region1002. The interfacial layer240may include an oxide-containing material such as silicon oxide or silicon oxynitride and may be formed by chemical oxidation using an oxidizing agent (e.g., hydrogen peroxide (H2O2), ozone (O3)), plasma enhanced atomic layer deposition, thermal oxidation, ALD, CVD, and/or other suitable methods. In some embodiments, a cleaning process, such as an HF-last pre-gate cleaning process (for example, using a hydrofluoric (HF) acid solution), may be performed before the interfacial layer240is formed in the gate trenches238. The gate dielectric layer242wraps around the second nanostructures204. In some embodiments, the gate dielectric layer242includes high-k dielectric material having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The high-k dielectric material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), yttrium oxide, strontium titanate, hafnium oxynitride (HfOxNy), other suitable metal-oxides, or combinations thereof. The gate dielectric layer242may be formed by ALD, chemical vapor deposition (CVD), physical vapor deposition (PVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), metal organic CVD (MOCVD), sputtering, other suitable processes, or combinations thereof.

InFIG.17, a hard mask layer244is deposited on the gate dielectric layer242in both the first device region1001and the second device region1002. In some embodiments, the hard mask layer244includes aluminum oxide (AlOx), which is deposited over the gate dielectric layer242using ALD, CVD or PVD.

InFIG.18, a photoresist layer246is then formed over the hard mask layer244and patterned to expose the second device region1002but not expose the first device region1001. In some embodiments, the photoresist layer246is an organic material formed using a spin-on coating process, followed by patterning the organic material to expose the second device region1002using suitable photolithography techniques. For example, photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. In greater detail, a photomask or reticle (not shown) may be placed above the photoresist material, which may then be exposed to a radiation beam which may be ultraviolet (UV) or an excimer laser such as a Krypton Fluoride (KrF) excimer laser, or an Argon Fluoride (ArF) excimer laser. Exposure of the photoresist material may be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and decrease the minimum achievable pitch. A bake or cure operation may be performed to harden the exposed photoresist material, and a developer may be used to remove either the exposed or unexposed portions of the photoresist material depending on whether a positive or negative resist is used.

After the patterned photoresist layer246is formed, the exposed portion of the hard mask layer244in the second device region1002is removed by using the patterned photoresist layer246as an etch mask, so that the gate dielectric layer242is exposed in the second device region1002. In some embodiments, the hard mask layer244may be etched by using a plasma dry etching using fluorine-based and/or chlorine-based etchants.

For example, the hard mask layer244may be removed by a wet etching process using an etchant that is selective to the material of the hard mask layer244. Stated differently, the etchant used in removing the hard mask layer244etches the material (e.g., aluminum oxide) of the hard mask layer244at a faster etch rate than etching the material of the gate dielectric layer242.

Next, the photoresist layer246is removed from the first device region1001by using, for example, a plasma ash process. The resultant structure is illustrated inFIG.19. In some embodiments, a plasma ash process is performed such that the temperature of the organic material of the photoresist is increased until these organic materials experience a thermal decomposition and may be removed.

InFIG.20A, a barrier layer247is formed on the hard mask layer244in the first device region1001and over the gate dielectric layer242in the second device region1002. After the barrier layer247is formed, a fluorine-containing layer248is formed on the barrier layer247. In some embodiments, the barrier layer247includes TiN, TaN, Titanium Silicon Nitride (TSN), or the like. The fluorine-containing layer248is a conductive element such as tungsten (W) deposited using a fluorine-containing precursor by ALD, CVD, or the like. In some embodiments where the fluorine-containing layer248is tungsten, a fluorine-containing precursor gas, such as hexafluoride (WF6), and silane (SiH4) are used as precursor gases for depositing the tungsten. By using the fluorine-containing gas to form the tungsten, residual fluorine atoms from the fluorine-containing gas may inherently exist in the fluorine-containing layer248. The fluorine-containing layer248may be deposited at a temperature in a range from 250° C. to 475° C. and under a process pressure in a range from 0.5 torr to 400 torr.

In some embodiments where the fluorine-containing layer248is formed using ALD process, the ALD process is performed by sequentially exposing the surface of the barrier layer247to two different gaseous precursors in a cyclic manner, i.e., alternating application of a first gaseous precursor and a second gaseous precursor to an exposed surface of the barrier layer247. In some embodiments, the first gaseous precursor is a fluorine-containing gas, such as WF6. The second gaseous precursor includes elements such as silicon (Si) and hydrogen (H). Examples of the second gaseous precursor include silane (SiH4). The barrier layer247can help prevent the fluorine-containing gas to damage the underlying layer (e.g., the gate dielectric layer242) during forming the fluorine-containing layer248. In some other embodiments, the barrier layer247can be omitted.

InFIG.20B, an anneal process2000is performed to drive the fluorine atoms from the fluorine-containing layer248to diffuse through the barrier layer247into the gate dielectric layer242and the interfacial layer240in the second device region1002. In some embodiments, the anneal process2000is performed at a temperature in a range from 150° C. to 750° C. for a duration in a range from 0.5 seconds to 60 seconds. During the anneal process2000, the hard mask layer244in the first device region1001can serve as a fluorine diffusion barrier that prevents the fluorine atoms in the fluorine-containing layer248in the first device region1001from driving into the gate dielectric layer242and the interfacial layer240in the first device region1001. In other words, the gate dielectric layer242and the interfacial layer240in the first device region1001are fluorine-free after the anneal process2000is completed. Therefore, the gate dielectric layer242and the interfacial layer240in the first device region1001have a lower fluorine atomic concentration than that in the second device region1002, or the gate dielectric layer242and the interfacial layer240in the first device region1001may be fluorine-free.

In some other embodiments, instead of forming the fluorine-containing layer248, a thermal soaking process followed by the anneal process is performed. Reference is made first toFIG.21A. In some other embodiments, after the barrier layer247is formed, a thermal soaking process2002is performed on an exposed surface of the barrier layer247using a fluorine-containing gas to embed fluorine atoms into the barrier layer247. Examples of the fluorine-containing gas include NF3, WF6, a combination thereof; or the like.

During the thermal soaking process2002, the structure inFIG.21Ais heated in a non-plasma ambient, for example, at an elevated temperature in a range from 250° C. to 475° C. under a pressure in a range from 0.5 torr to 50 torr. The soaking duration may be in a range from 0.1 second to 1 hour.

InFIG.21B, after the thermal soaking process2002, an anneal process2000ais performed to drive the fluorine atoms from the barrier layer247into the gate dielectric layer242and the interfacial layer240in the second device region1002. The anneal process2000ais similar to the anneal process2000with regard toFIG.20B. During the anneal process2000a, the hard mask layer244in the first device region1001can serve as a fluorine diffusion barrier to prevent the fluorine atoms from driving into the gate dielectric layer242and the interfacial layer240in the first device region1001. Therefore, the gate dielectric layer242and the interfacial layer240in the first device region1001have a lower fluorine atomic concentration than that in the second device region1002, or the gate dielectric layer242and the interfacial layer240in the first device region1001may be fluorine-free.

Fluorine can passivate interfacial and/or bulk defects for each of the interfacial layer240and the gate dielectric layer242by filling the oxygen vacancies and attaching to interfacial dangling bonds. By including fluorine in the gate dielectric layer242and the interfacial layer240, charge trapping and interfacial charge scattering can be reduced, which in turn may reduce oxide leakage current, improve threshold voltage stability and device performance. In some embodiments where the first device region1001is n-type device region, in the absence of fluorine in the gate dielectric layer242and the interfacial layer240in the first device region1001, unwanted threshold voltage degradation of an NMOS device (increasing NMOS threshold voltage) may be prevented. As a result, threshold voltages of the resulting devices in different device regions (e.g., the first device region1001and the second device region1002) can be individually tuned to meet different target threshold voltages for different devices.

FIG.22is a graph illustrating a fluorine concentration in the gate dielectric layer242, the interfacial layer240and the nanostructure204in accordance with some embodiments. In some embodiments, the gate dielectric layer242and the interfacial layer240may each have a fluorine concentration gradient. For example, the gate dielectric layer242has a fluorine concentration decreasing in a direction toward the nanostructure204. The interfacial layer240has a fluorine concentration decreasing in a direction toward the nanostructure204as well.

Reference is made toFIG.23. After the anneal process2000, the fluorine-containing layer248and the barrier layer247(if present) are removed, for example, using a wet removal process such as wet etch using HCl, H2O2, H2O, a combination thereof, or the like.

InFIG.24, one or more p-type work function metal layers249are deposited on the hard mask layer244in the first device region1001and on the gate dielectric layer242in the second device region1002. The one or more p-type work function metal layers249may include one or more work function metals to provide a suitable work function for the high-k/metal gate structures. The one or more p-type work function metal layers249may include one or more p-type work function metals (P-metal). The p-type work function metals may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials.

InFIG.25, a photoresist layer250is then formed over the p-type work function metal layers249and patterned to expose the first device region1001but not expose the second device region1002. In some embodiments, the photoresist layer250is an organic material formed using a spin-on coating process, followed by patterning the organic material to expose the first device region1001using suitable photolithography techniques. For example, photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. In greater detail, a photomask or reticle (not shown) may be placed above the photoresist material, which may then be exposed to a radiation beam which may be ultraviolet (UV) or an excimer laser such as a Krypton Fluoride (KrF) excimer laser, or an Argon Fluoride (ArF) excimer laser. Exposure of the photoresist material may be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and decrease the minimum achievable pitch. A bake or cure operation may be performed to harden the exposed photoresist material, and a developer may be used to remove either the exposed or unexposed portions of the photoresist material depending on whether a positive or negative resist is used.

After the patterned photoresist250is formed, the exposed p-type work function metal layers249and the underlying hard mask layer244in the first device region1001are removed by using the patterned photoresist as an etch mask, so that the gate dielectric layer242is exposed in the first device region1001. In some embodiments, the hard mask layer244may be etched by using a plasma dry etching using fluorine-based and/or chlorine-based etchants. For example, the hard mask layer244may be removed by a wet etching process using an etchant that is selective to the material of the hard mask layer244. Stated differently, the etchant used in removing the hard mask layer244etches the material (e.g., aluminum oxide) of the hard mask layer244at a faster etch rate than etching the material of the gate dielectric layer242.

Next, the photoresist layer250is removed from the second device region1002by using, for example, a plasma ash process. The resultant structure is illustrated inFIG.26. In some embodiments, a plasma ash process is performed such that the temperature of the organic material of the photoresist is increased until these organic materials experience a thermal decomposition and may be removed.

InFIG.27, one or more n-type work function metal layers252are deposited on the gate dielectric layer242in the first device region1001, and on the one or more p-type work function metal layers249in the second device region1002.

The one or more n-type work function metal layers252may include one or more work function metals to provide a suitable work function for the high-k/metal gate structures. The one or more n-type work function metal layers252may include one or more n-type work function metals (N-metal). The n-type work function metals may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and/or other suitable materials.

InFIG.28, a fill metal254is formed on the one or more n-type work function metal layers252to fill a remainder of gate trenches. A CMP is then performed on the fill metal254until the ILD layer236is exposed, resulting in the one or more n-type work function metal layers252, the one or more p-type work function metal layers249, the gate dielectric layer242and the ILD layer236having substantially level top surfaces. The fill metal254, the one or more n-type work function metal layers252, and the corresponding gate dielectric layer242and interfacial layer240may be collectively referred to as a gate stack256a. The one or more n-type work function metal layers252, the one or more p-type work function metal layers249, and the corresponding gate dielectric layer242and interfacial layer240may be collectively referred to as a gate stack256b.

In some embodiments, the fill metal254may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials. Additional processing may be performed to finish fabrication of the device, as one of ordinary skill readily appreciates, thus details may not be repeated here. For example, another inter-layer dielectric (ILD) may be deposited over the ILD layer236. Further, gate contacts and source/drain contacts may be formed extending through the additional ILD and/or the ILD layer236to electrically couple to the gate stacks256a,256band the epitaxial source/drain regions232(seeFIG.15B), respectively.

Based on the above discussions, it can be seen that the present disclosure in various embodiments offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that by including fluorine in the gate dielectric layer and the interfacial layer, charge trapping and interfacial charge scattering can be reduced, which in turn may reduce oxide leakage current, improve threshold voltage stability and device performance. Another advantage is that in the absence of fluorine in the gate dielectric layer and the interfacial layer in the n-type device region, unwanted threshold voltage degradation of an NMOS device (increasing NMOS threshold voltage) may be prevented. Yet another advantage is that threshold voltages of the resulting devices in different device regions can be individually tuned.

In some embodiments, a method of forming a semiconductor device includes forming a fin over a substrate, the fin comprising alternately stacking first semiconductor layers and second semiconductor layers, removing the first semiconductor layers to form spaces each between the second semiconductor layers, forming a gate dielectric layer wrapping around each of the second semiconductor layers, forming a fluorine-containing layer on the gate dielectric layer, performing an anneal process to drive fluorine atoms from the fluorine-containing layer into the gate dielectric layer, removing the fluorine-containing layer, and forming a metal gate on the gate dielectric layer. In some embodiments, the fluorine-containing layer is formed using WF6and silane as precursors. In some embodiments, the fluorine-containing layer is tungsten. In some embodiments, the method further includes forming a barrier layer on the gate dielectric layer prior to forming the fluorine-containing layer, wherein the barrier layer comprises TiN, TaN, or Titanium Silicon Nitride (TSN). In some embodiments, the method further includes removing the barrier layer after the anneal process. In some embodiments, removing the fluorine-containing layer comprises using a wet etch using HCl, H2O2, H2O, a combination thereof. In some embodiments, the method further includes forming an interfacial layer wrapping around each of the second semiconductor layers prior to forming the gate dielectric layer, wherein the annealing process is performed such that the fluorine atoms in the fluorine-containing layer drives into the interfacial layer.

In some embodiments, a method of forming a semiconductor device includes forming a first fin and a second fin in a first device region and a second device region on a substrate, respectively, each of the first fin and the second fin comprises alternately stacked first semiconductor layers and second semiconductor layers, removing the first semiconductor layers to form spaces each between the second semiconductor layers, forming a gate dielectric layer wrapping around each of the second semiconductor layers, forming a fluorine diffusion barrier layer on the gate dielectric layer in the first device region, performing a thermal soaking process to the substrate using a fluorine-containing gas, performing an anneal process to the substrate after performing the thermal soaking process, removing the fluorine diffusion barrier layer, and forming a metal gate on the gate dielectric layer. In some embodiments, the fluorine-containing gas comprises NF3, WF6, or a combination thereof. In some embodiments, the method further includes prior to performing the thermal soaking process, forming a TiN layer on the fluorine diffusion barrier layer. In some embodiments, the method further includes after performing the anneal process, removing the TiN layer from the fluorine diffusion barrier layer. In some embodiments, the method further includes forming one or more first work function layers on the fluorine diffusion barrier layer in the first device region and on the gate dielectric layer in the second device region, and after forming the one or more first work function layers, removing the one or more first work function layers and the fluorine diffusion barrier layer in the first device region. In some embodiments, the one or more first work function layers include p-type work function metal. In some embodiments, the method further includes forming one or more second work function layers on the gate dielectric layer in the first device region and on the one or more first work function layers in the second device region. In some embodiments, the one or more second work function layers include n-type work function metal. In some embodiments, the gate dielectric layer is fluorine-free after the anneal process is completed. In some embodiments, the method further includes prior to forming the gate dielectric layer, forming an interfacial layer wrapping around the second semiconductor layers, wherein the interfacial layer is fluorine-free after the anneal process is completed.

In some embodiments, a semiconductor device includes first semiconductor channels extending in a first direction above a substrate and spaced apart in a second direction perpendicular to the substrate, a first gate dielectric layer wrapping around the first semiconductor channels, wherein the first gate dielectric layer comprises fluorine atoms, one or more work function metal layers on the first gate dielectric layer, wherein the first gate dielectric layer and the one or more work function metal layers are collectively referred to as a gate stack, and source/drain regions on opposite sides of the gate stack. In some embodiments, the semiconductor device further includes second semiconductor channels separated from the first semiconductor channels and extending in the first direction above the substrate and spaced apart in the second direction perpendicular to the substrate, and a second gate dielectric layer wrapping around the second semiconductor channels, wherein the second gate dielectric layer has a lower fluorine concentration than the first gate dielectric layer. In some embodiments, the semiconductor device further comprises an interfacial layer between the first semiconductor channels and the first gate dielectric layer, wherein the interfacial layer comprises fluorine atoms.