Doping a non-planar semiconductor device

In doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. A first ion implant is performed in a region of the non-planar semiconductor body. The first ion implant has a first implant energy and a first implant angle. A second ion implant is performed in the same region of the non-planar semiconductor body. The second ion implant has a second implant energy and a second implant angle. The first implant energy may be different from the second implant energy. Additionally, the first implant angle may be different from the second implant angle.

BACKGROUND

This relates generally to the manufacturing of semiconductor devices and, more specifically, to doping a non-planar semiconductor device.

2. Related Art

As semiconductor manufacturers continue to shrink the dimensions of transistor devices in order to achieve greater circuit density and higher performance, short-channel effects, such as parasitic capacitance and off-state leakage, increasingly impair transistor device characteristics. Fin field effect transistors (FinFETs), such as double-gate transistors, tri-gate transistors, and gate-all-around transistors, are a recent development in semiconductor processing for controlling such short-channel effects. A FinFET has a fin that protrudes above a substrate surface. The fin forms the body of the FinFET device and has fewer paths for current leakage than a planar body. Additionally, the fin creates a longer effective channel width, thereby increasing the on-state current and reducing short channel effects.

The fin defines the channel, the source/drain regions, and the source/drain extension regions of the FinFET. Like conventional planar metal-oxide semiconductor field effect transistors (MOSFETs), the channel, source, drain, source extension, and drain extension regions of a FinFET device are doped with impurities (i.e., dopants) to produce desired electrical characteristics. Ideally, these regions are each uniformly doped along the height of the fin. Poor dopant uniformity may cause undesirable threshold voltage variations across the height of the gate as well as source/drain punch-through issues.

One conventional method for doping the channel, source/drain, and source/drain extension regions of a FinFET is ion implantation. In order to provide uniform doping on both the top and sides of the fin, ion implantation is conventionally performed at a single energy and at an oblique angle to the vertical. However, as device structures become increasingly dense, adjacent structures, such as mask layers and neighboring fins, can cause implant shadowing and result in the non-uniform doping of the FinFET. One method for avoiding implant shadowing is to perform implants at a lower implant angle where dopants are implanted more vertically. However, a lower implant angle results in poor dopant distribution across the height of the fin as well as poor dopant retention along the sidewalls of the fin, thereby causing poor dopant uniformity in fin.

SUMMARY

In one exemplary embodiment, a substrate having a non-planar semiconductor body formed thereon is obtained. A first ion implant is performed in a region of the non-planar semiconductor body. The first ion implant has a first implant energy and a first implant angle. A second ion implant is performed in the same region of the non-planar semiconductor body. The second ion implant has a second implant energy and a second implant angle. The first implant energy may be different from the second implant energy. Additionally, the first implant angle may be different from the second implant angle.

DETAILED DESCRIPTION

The following description is presented to enable a person of ordinary skill in the art to make and use the various embodiments. Descriptions of specific devices, methods, and applications are provided only as examples. Various modifications to the examples described herein will be readily apparent to those of ordinary skill in the art, and the general principles defined herein may be applied to other examples and applications without departing from the spirit and scope of the various embodiments. Thus, the various embodiments are not intended to be limited to the examples described herein and shown, but are to be accorded the scope consistent with the claims. For example, exemplary processes for doping a FinFET device are disclosed below. It should be appreciated that these exemplary processes may also be applied to non-planar semiconductor devices other than FinFET devices, such as, non-planar multi-gate transistor devices and non-planar nano-wire transistor devices.

FIG. 1depicts an exemplary process100for doping a FinFET device. At block102of process100, a substrate having a fin formed thereon may be obtained. The fin may include a channel region, a source region, a drain region, a source extension region, and a drain extension region. At block104, a first ion implant may be performed in a region of the fin. The region may include any one of the channel region, source region, drain region, source extension region, and drain extension region. Dopants may be implanted at a first implant energy and at a first implant angle relative to an axis orthogonal to the surface of the substrate. At block106, a second ion implant may be performed in the same region as in the first ion implant. Dopants may be implanted at a second implant energy and at a second implant angle relative to an axis orthogonal to the surface of the substrate. In one example, the second implant energy is different from the first implant energy and the second implant angle is different from the first implant angle. In one such example, the first implant energy may be greater than the second implant energy and the first implant angle may be smaller than the second implant angle.

A more detailed description of exemplary process100is now provided with simultaneous reference toFIG. 1andFIGS. 2A-2C.FIGS. 2A-2Cillustrate cross-sectional views of a FinFET device200at various stages of exemplary process100. At block102of exemplary process100and shown inFIG. 2A, a substrate202having a fin204formed thereon may be obtained. Substrate202may include any commonly known substrate suitable for forming a FinFET device200. For example, substrate202may include a single crystalline semiconductor wafer (e.g., silicon, germanium, gallium arsenide, etc.). In another example, substrate may include one or more epitaxial single crystalline semiconductor layers (e.g., silicon, germanium, silicon germanium, gallium arsenide, indium phosphide, indium gallium arsenide, etc.) grown atop a distinct crystalline wafer (silicon, germanium, gallium arsenide etc.). The one or more epitaxially grown semiconductor layers may serve as buffer layers to grade the lattice constant from the distinct crystalline wafer to the top surface of substrate202. In yet another example, substrate202may include an insulating layer (e.g., silicon dioxide, silicon oxynitride, a high-k dielectric layer, etc.) in between a single crystalline semiconductor substrate and an epitaxial layer to form, for example, a silicon-on-insulator substrate. It should be recognized that substrate202may include other structures and layers, such as shallow trench isolation structures.

Fin204on substrate202may be formed by conventional semiconductor fabrication methods, such as, but not limited to, photolithography, etch, and chemical vapor deposition. Fin204may have a channel region212disposed between a source region214and a drain region216. A source extension region213may be disposed between channel region212and source region214and a drain extension region215may be disposed between channel region212and drain region216. Fin204may comprise a single crystalline semiconductor material (e.g., silicon, germanium, gallium arsenide etc.). Alternatively, fin204may comprise multiple layers of epitaxially grown semiconductor materials. For example, the multiple layers of epitaxially grown semiconductor materials may form a vertical array of multiple nanowires in the channel region. As shown inFIG. 2A, fin204has a critical dimension206, a height208, and a length210. In one example, critical dimension206may be 5-50 nm, height208may be 15-150 nm, and length may be 20-1200 nm.

At block104of exemplary process100and as shown inFIG. 2B, a first ion implant is performed. The ion implant may be performed by any suitable ion beam implanting system known in the art. An exemplary ion beam implanting system is described later in greater detail. Arrows220represent the implanting of dopant ions into fin204during the first ion implant. Dopant ions may be implanted into one or more regions of fin204such as the source/drain regions214,216, the source/drain extension regions213,215, or the channel region212. The channel region212is typically implanted with p-type dopant ions when forming a NMOS transistor device and with n-type dopant ions when forming a PMOS transistor device. Conversely, the source/drain regions214,216, and the source/drain extension regions213,215are typically implanted with p-type dopant ions when forming a PMOS transistor device and with n-type dopant ions when forming a NMOS transistor device. Examples of p-type dopant ions include boron containing ions such as, but not limited to B+, B2+, BF+, BF2+, and BF3+. Examples of n-type dopants include phosphorous and arsenic containing ions such as, but not limited to As+, As2+, P+, and P2+.

The first ion implant may be performed at a first implant energy. The implant energy at least partially determines the depth219at which dopant ions are implanted into fin204. The higher the implant energy, the greater the depth219at which dopant ions may be implanted into fin204. The first implant energy may be defined to implant dopant ions to any desired depth in fin204. As shown inFIG. 2B, the first implant energy may be defined to implant dopant ions to a depth219in a bottom portion224of fin204. For example, the first implant energy may be defined to implant boron ions mainly to a depth of 5-110 nm in fin204. In one example, the first implant energy may be 0.5-15 KeV. In another example, the first implant energy may be 2-10 KeV. In yet another example, the first implant energy may be 2-6 KeV.

The first ion implant may have a first implant angle218. First implant angle218may define the direction at which dopant ions are implanted into fin204. First implant angle218may be defined relative to an axis222that is orthogonal to the surface of substrate202. First implant angle218may be substantially vertical (e.g., 0-10 degrees) to avoid implant shadowing. In this way, the doping of fin204may be independent of the dimensions and spacing of neighboring structures. In one example, first implant angle218may be 0-5 degrees. In another example, first implant angle218may be 0-3 degrees. In yet another example, first implant angle218may be 0-1 degrees. It should be recognized that FinFET device200may be rotated during the first ion implant to achieve an even distribution of dopants on all sides of fin204.

At block106of exemplary process100and as shown inFIG. 2C, a second ion implant may be performed. Second ion implant may be performed by the same ion beam implanting system that performs the first ion implant. Alternatively, a different ion beam implanting system may perform the second ion implant. Arrows228represent the implanting of dopant ions into fin204during the second ion implant. Dopant ions are implanted into the same one or more regions (i.e., source/drain regions, source/drain extension regions, or channel region) of fin204in which the first ion implant is performed. The second ion implant also implants the same dopant ion type (i.e., p-type or n-type) as the first ion implant in the same one or more regions.

The second ion implant may be performed at a second implant energy. The second implant energy may be different from the first implant energy where dopant ions are implanted to a different depth in fin204. For example, the second implant energy may be lower than the first implant energy. As shown inFIG. 2B, the second implant energy may be defined to implant dopant ions to a depth225in portion226that is above portion224. Portion226may be on or partially overlapping with portion224. In an alternative example, second implant energy may be higher than the first implant energy. In one example, the second implant energy may be defined to implant boron ions mainly to a depth of 5-75 nm in fin204. In one example, the second implant energy may be 0.5-10 KeV. In another example, the second implant energy may be 0.5-6 KeV. In yet another example, the second implant energy may be 0.5-2 KeV.

The second ion implant may have a second implant angle230. Second implant angle230may be defined relative to an axis orthogonal to the surface of substrate202. Second implant angle230may be approximately equal to first implant angle218. Alternatively, second implant angle230may be different from first implant angle218. Second implant angle230may be substantially vertical (e.g., 0-10 degrees) to avoid implant shadowing. In one example, second implant angle230may be 1-8 degrees. In another example, second implant angle230may be 3-5 degrees. It should be recognized that FinFET device200may be rotated during the second ion implant to achieve an even distribution of dopants on all sides of fin204.

The implant energy may affect the straggle of dopants implanted into fin204. The straggle is the spread of the dopant ions implanted in fin204. Straggle occurs both in the horizontal direction (e.g., along the length210of fin204) and in the vertical direction (e.g., along the height208of fin204) and increases with implant energy. The different implant energies of the first ion implant and the second ion implant may cause greater combined straggle and may result in poor dopant uniformity across the length210and height208of fin204. For example,FIG. 3Ashows a cross-section view of a fin304along the length of the fin. Fin304may be provided a first ion implant308and a second ion implant310where the first ion implant308has a higher energy than the second implant310. Patterned mask layer306defines the region in fin304to be implanted. Because of the different implant energies, first ion implant308may produce a horizontal straggle314that is greater than the horizontal straggle316produced by the second ion implant310. This may result in poor dopant uniformity.

The implant angles of the first ion implant and the second ion implant may be defined to reduce the overall horizontal straggle resulting from different implant energies. For example, the first implant energy may be higher than the second implant energy while the first implant angle may be smaller than the second implant angle. In one such example, the first ion implant may have a first implant energy of 2-10 KeV and a first implant angle of 0-2 degrees while the second ion implant may have a second implant energy of 0.5-2 KeV and a second implant angle of 2-10 degrees.FIG. 3Bshows a cross-sectional view of a fin304along the length of the fin and illustrates one such example. The first ion implant320may have a higher implant energy and a lower implant angle than the second ion implant322. The different implant energies and implant angles may be defined such that the first ion implant320produces a straggle324that approximately matches the straggle326produced by the second ion implant322, thereby improving the dopant uniformity in fin304.

Different dopant ion species having different molecular masses may be implanted in the first and second ion implants to reduce the overall straggle caused by the different implant energies. A dopant ion species having a larger molecular mass tends to have a smaller penetration depth and also less straggle. To reduce overall straggle, a dopant ion species having a larger molecular mass may be implanted at a higher implant energy while a dopant ion species having a lower molecular mass may be implanted at a lower implant energy. For example, the first implant energy may be higher than the second implant energy and the first ion implant may implant a dopant ion species having a molecular mass larger than that of the second ion implant. In one such example, the first ion implant may implant a dopant ion species of arsenic having a larger molecular mass of 74.9 at the higher implant energy of 2-10 KeV and the second ion implant may implant a dopant ion species of phosphorous having a smaller molecular mass of 31.0 at a lower implant energy of 0.5-2 KeV.

Higher energy ion implants may be preferably performed prior to lower energy ion implants. In this way, shallowly implanted dopants are not displaced (“knocked in”) by subsequent deeper dopants implanted by higher energy implants. Moreover, performing higher energy implants prior to lower energy implants improves manufacturability as ion beam tuning in ion beam implanting systems is more favorable from high to low energy rather than vice versa. In one example, the first implant energy may be greater than the second implant energy and the first ion implant may be performed prior to the second ion implant.

As previously discussed, it should be appreciated that exemplary process100may be applied to other non-planar semiconductor devices, such as, but not limited to non-planar multi-gate transistor devices, non-planar gate-all-around transistor devices, and non-planar nano-wire transistor devices. For example, fin204may be substituted with other non-planar semiconductor bodies such as, nano-wires or vertical arrays of nanowires.

With reference toFIG. 4, another exemplary process400for doping a FinFET device is shown.FIGS. 5A-5Fillustrate cross-sectional views of a FinFET device500representing the various stages in exemplary process400. Exemplary process400comprises blocks402to412. Optional blocks404and406are represented with a dotted outline.

At block402of exemplary process400and as shown inFIG. 5A, a substrate having a fin504formed thereon may be obtained. Substrate502may comprise a single crystalline semiconductor substrate, one or more epitaxial grown layers over a distinct silicon wafer, a silicon-on-insulator substrate, or any other well-known substrate on which a FinFET device may be formed. Fin504may include source/drain regions, source/drain extension regions, and a channel region. Fin504may have a critical dimension510, a height508, and a length (not shown). Adjacent structures506such as masks, dummy features, or neighboring fins may be formed next to fin504.

At optional block404of exemplary process400and as shown inFIG. 5B, a padding layer511may be formed over and around fin504. Padding layer511may fully fill the spaces between fin504and adjacent structures506and may have a top surface that is approximately planar over fin504and adjacent structures506. Padding layer511may be formed to block dopants from reaching substrate502and to prevent re-sputtering of ions onto the sidewalls of fin504during ion implanting. Additionally, padding layer511increases dopant retention on the sidewalls of fin504. Padding layer511may comprise any material that traps implanted dopant ions. For example, padding layer511may be a dielectric material or an in-situ doped material, such as, but not limited to, undoped silicon oxide, doped silicon oxide, silicon nitride, and silicon oxynitride.

The thickness512of padding layer511above the top surface of fin504may be sufficiently thin so as not to impede dopant ions from entering fin504during implanting. For example, padding layer511may be formed to a thickness512of 0-10 nm above the top surface of fin504. Padding layer511may be formed by conventional semiconductor processes such as chemical vapor deposition, spin-on deposition, sol-gel deposition processes, selective deposition processes, and selective etch back processes. Padding layer511may be formed prior to implant blocks408and410and may be removed prior or subsequent to block412of annealing fin504.

Referring to optional block406of exemplary process400and as shown inFIG. 5C, a punch through stopper (PTS) layer514may be formed in fin504. PTS layer514may be formed under the source/drain regions, the channel region and/or the source/drain extension regions of fin504to prevent electrical punch-through. The source/drain regions, the channel region and/or the source/drain extension regions may partially overlap with PTS layer514. Additionally, PTS layer514may act as a barrier by blocking or significantly retarding dopant migration during implanting and annealing processes and thus may minimize the vertical straggle of dopants in fin504. PTS layer514may create an abrupt interface515between the PTS layer514and the source/drain regions, the channel region and/or the source/drain extension regions of fin504in which the dopant concentration in each region abruptly extinguishes. For example, PTS layer514may be formed such that the sheet resistance (Rs) in the source/drain regions, the channel region and/or the source/drain extension regions increases by 3 orders of magnitude over a 3 nm thickness at the interface515between the PTS layer514and the source/drain regions, the channel region and/or the source/drain extension regions.

PTS layer514may be formed by implanting into fin504any species that resist the movement of dopants such as, but not limited to carbon, oxygen, fluorine, nitrogen, or any combinations thereof. Alternatively, PTS layer514may be formed by implanting a dopant type that is opposite from the dopant type that is implanted above PTS layer514. For example, the PTS layer514may be formed with an n-type dopant if a p-type dopant is implanted in the region above PTS layer514.

The depth516at which PTS layer514is formed may define the effective height516of FinFET device500. The effective height516partially determines the effective channel width of FinFET device500. For example, a greater effective height516may create a greater effective channel width. The effective channel width of FinFET device500may thus be defined using the implant process by controlling the depth at which the PTS layer514is formed. In this way, different FinFET devices having the same physical fin height, but having different effective channel widths, may be fabricated on the same substrate by controlling the depth at which the fins are implanted. This obviates the need to fabricate different fins with different physical heights or to implement various FinFET widths across the substrate, thereby eliminating costly lithography and etch steps.

PTS layer514may be formed in the substrate502under fin504. In one such example, PTS layer514may partially overlap with the bottom portion of fin504. In another example, PTS layer514may be formed at any depth516within fin504. PTS layer514may be preferably formed at a depth516greater than the critical dimension510of fin504. For example, PTS layer514may be formed in fin504at a depth516greater than critical dimension510and less than height508. The depth516of the PTS layer514formed may have a uniformity of 5% or less across the length of fin504. PTS layer514may be formed either prior to or subsequent to steps408and410of the providing a first and second ion implant.

At block408of exemplary process400and as shown inFIG. 5D, a first ion implant is performed. Dopant ions may be implanted into one or more regions of fin504, such as, the source/drain regions, the source/drain extension regions, or the channel region. The first ion implant may be performed at a first implant energy. The first implant energy may be defined to implant dopant ions to any desired depth520in fin504. For example, the first implant energy may be defined to implant dopant ions to a depth above PTS layer514. Implanted dopant ions from the first ion implant may partially overlap with PTS layer514in fin504. In one example, the first implant energy may be 0.5 KeV-15 KeV. In another example, the first implant energy may be 2 eV-10 KeV. In yet another example, the first implant energy may be 2 KeV-6 KeV. The first ion implant may have a first implant angle518. First implant angle518may be substantially vertical (e.g., 0-10 degrees) to avoid implant shadowing. In one example, first implant angle518may be 0-5 degrees. In another example, first implant angle518may be 0-3 degrees. In yet another example, first implant angle518may be 0-1 degrees.

At block410of exemplary process400and as shown inFIG. 5E, a second ion implant may be performed. Dopant ions of the same dopant type (i.e., p-type or n-type) may be implanted into the same one or more regions (i.e., source/drain regions, source/drain extension regions, or channel region) as in the first ion implant. The second ion implant may be performed at a second implant energy. The second implant energy may be different from the first implant energy where dopant ions may be implanted to a different depth in fin504. For example, as shown inFIG. 5E, the second implant energy may be lower than the first implant energy where the second ion implant implants dopant ion to a depth less that of the first ion implant. Dopant ions from the second ion implant may partially overlap with dopant ions from the second ion implant in fin504. In one example, the second implant energy may be 0.5 KeV-10 KeV. In another example, the second implant energy may be 0.5 KeV-6 KeV. In yet another example, the second implant energy may be 0.5 KeV-2 KeV. The second ion implant may have a second implant angle522. Second implant angle522may be approximately equal to first implant angle518. Alternatively, second implant angle522may be different from first implant angle218. Second implant angle522may be sufficiently vertical (e.g., 0-10 degrees) to avoid implant shadowing. In one example, second implant angle522may be 1-8 degrees. In another example, second implant angle522may be 3-5 degrees.

It should be appreciated that additional ion implants may be performed to implant additional dopant ions into fin504. For example a third ion implant (not shown) may be performed. Each additional ion implant may have an implant energy and an implant angle. For each additional ion implant, the same dopant ion type (i.e., p-type or n-type) is implanted into the same one or more regions (i.e., source/drain regions, source/drain extension regions, and channel region) as the first and second ion implants. In one example, the total number of ion implants (including the first and second ion implants) may be 2-20. In another example, the total number of ion implants may be 2-6. Each ion implant may have a different implant energy. The ion implants may be performed in a sequence of decreasing implant energy to prevent dopant displacement (“knocking in”) during implanting. For example, each ion implant may implant dopant ions into fin504to a depth on or above that of the previous ion implant.

The implant angles of the ion implants may be inversely proportional to the implant energies. For example, the ion implant with the highest implant energy may have the smallest implant angle while the ion implant with the lowest implant energy may have the largest implant angle. Table 1 describes an exemplary process where the implant angles are inversely proportional to the implant energies. The exemplary process implants boron ions into the source/drain extension regions of a PMOS FinFET device. The exemplary process comprises a sequence of 6 ion implants where the implant energy decreases while the implant angle increases for each subsequent ion implant.

The implant energy and implant angle of each ion implant may be defined to minimize the overall horizontal straggle of dopants in fin504. For example, the implant energies and implant angles of each ion implant may be defined to achieve a dopant concentration uniformity of 3% or less across the height of the implanted region of fin504. In an exemplary process where a PTS layer514is formed, the implant energies and implant angles of each ion implant may be defined to achieve a dopant concentration uniformity of 3% or less across the depth516at which PTS layer514is formed.

To reduce overall straggle, one or more of the ion implants may implant a dopant ion species having a different molecular mass from that of the other ion implants. For example, one or more ion implants having higher implant energies may implant a dopant ion species having a higher molecular mass than that of the other ion implants.

Each of the ion implants may be performed serially in a suitable ion implanting system. Alternatively, any two implant steps may be performed simultaneously by an ion implanting system having dual ion beams where one ion beam may perform an ion implant step at one implant energy and the other ion beam may perform another ion implant step at a different implant energy.

At block412of exemplary process400and as shown inFIG. 5F, fin504may be annealed. Annealing is represented by arrows524. During annealing, implanted dopants in fin504are activated. Additionally, implant damage (e.g, amorphization and crystalline damaged) to fin504is repaired by means of crystalline re-growth. During annealing, dopant diffusion is preferably minimized to maintain good dopant uniformity in fin504. Fin504may be annealed by an anneal process that minimizes dopant diffusion. For example, fin504may be annealed by a laser annealing process or a pulse laser annealing process. In another example, fin504may be annealed such that the dopant diffusion does not exceed 5 nm.

It should be appreciated that blocks402through412of exemplary process400may be performed in any order. For example, block408of providing a first ion implant may be performed prior to or after block410of providing a second ion implant. Additionally, it should be appreciated that additional semiconductor processing steps not shown in exemplary process400may be performed in manufacturing FinFET device500. For example, a conformal gate dielectric layer may be formed over the channel region of FinFET device500, a gate electrode may be formed over the conformal gate dielectric layer, and a pair of sidewall spacers may be formed on each side of the gate electrode. The completed FinFET500may be a dual-gate FinFET, a tri-gate FinFET, or a gate-all-around FinFET.

Additionally, as previously discussed, it should be appreciated that exemplary process400may be applied to other non-planar semiconductor devices, such as, but not limited to non-planar multi-gate transistor devices, non-planar gate-all-around transistor devices, and non-planar nano-wire transistor devices. For example, fin504may be substituted with other non-planar semiconductor bodies such as, nano-wires or vertical arrays of nanowires, where the non-planar semiconductor bodies may be doped by exemplary process400.

With reference toFIGS. 6A-6C, an exemplary FinFET600formed by the exemplary processes described herein is shown.FIG. 6Adepicts a three-dimensional cross-sectional view of exemplary FinFET device600.FIG. 6Bdepicts a two-dimensional cross-section view of exemplary FinFET device600along the length of fin604.FIG. 6Cdepicts a two-dimensional cross-section view of exemplary FinFET device600along the length of gate electrode618. In the present embodiment, FinFET device600may comprise a fin604disposed on a substrate602. Fin604may include a source region606, a drain region608, a source extension region610, a drain extension region612, and a channel region614. A PTS layer616may be disposed in fin604at a depth622greater than critical dimension626and less than height624. Depth626of PTS layer616may have a uniformity of 5% or less across the length of fin604. As depicted inFIG. 6B, source/drain regions606608, source/drain extension regions610612, and channel region614may be disposed above PTS layer616. Any one of the regions may partially overlap with PTS layer616. Each region may be doped to a concentration uniformity of 3% or less across the depth622. The dopant concentration in any one region may abruptly extinguish at an interface626between PTS layer616and source/drain regions606608, source/drain extension regions610612, and channel region614. In one example, the sheet resistance (Rs) in any one region may increase by 3 orders of magnitude over a 3 nm thickness at interface626. A gate dielectric layer620may be disposed over the channel region614of fin604. Gate dielectric layer620may comprise any suitable electrically insulating material such as, but not limited to, silicon oxide, high-k dielectrics, hafnium oxide, and titanium oxide. A gate electrode618may be disposed over the gate dielectric layer620. Gate electrode618may comprise any suitable electrically conductive material such as, but not limited to, doped polysilicon, metals, metal nitrides, metal silicides, titanium, tantalum, and tungsten.

The methods of doping a non-planar semiconductor device described herein may be performed using any suitably adapted ion implanting system such as the iPulsar® and the iPulsar Plus®, Advanced USJ Enabler system, available from Advanced Ion Beam Technologies Inc. of Fremont, Calif., USA. It is contemplated that other suitably adapted ion implanting systems, including those available from other manufacturers, may also be utilized to practice the present invention.

FIG. 7depicts a schematic, cross-sectional diagram of an exemplary ion implanting system700suitable for doping a non-planar semiconductor device, such as a FinFET. The exemplary ion implanting system700may comprise an ion source702, a mass analyzer unit704, an acceleration stage708, a deceleration electrode assembly709, a holding apparatus710, and a controller714. During processing, the holding apparatus710may support a substrate712having a non-planar semiconductor device to be implanted formed thereon. Holding apparatus710may rotate substrate712to allow dopant ions to be evenly distributed across substrate712and may tilt substrate712at an angle to provide an implant angle. An ion beam706may be extracted from ion source702. The acceleration stage708may accelerate ion beam706to an initial energy level by applying an extraction voltage. The mass analyzer unit704may analyze ion beam706and allow only ions having the desired charge-mass ratio to pass through. Deceleration electrode assembly709may modify the energy level of ion beam706from the initial energy level by applying a deceleration voltage. Ion beam706impinges onto substrate712and implants dopants into the non-planar semiconductor device at a desired implant energy and implant angle.

Controller714is coupled to the various components of the ion implanting system and controls the ion implanting system700to perform the methods and exemplary processes described herein. For example, controller714controls the extraction voltage applied by the acceleration stage708and the deceleration voltage applied by the deceleration electrode assembly709to define the implant energy of the ion beam implanting the non-planar semiconductor device on substrate712. Controller714also controls the holding apparatus710to tilt substrate712, thereby controlling the implant angle at which ion beam706implants the non-planar semiconductor device on substrate712. Controller714may implement various algorithms to synchronize the implantation energy and the implantation angle to achieve the required dopant distribution in the non-planar semiconductor device.

Controller714may be one of any form of general purpose data processing system that can be used for controlling the various components of ion implanting system700. Generally, controller714may include a processor716in communication with a main memory718, a storage medium720, and supporting devices722through a bus724. Processor716may be one or more general-purpose processing devices such as a microprocessor, a central processing unit (CPU), or the like. Main memory718may be random access memory (RAM) or any other dynamic memory for transient storage of information and instructions to be executed by processor716. Storage medium720may include any non-transitory computer-readable storage medium capable of storing computer software, instructions, or data, such as, but not limited to a hard disk, a floppy disk, a magnetic tape, an optical disk, read only memory (ROM) or other removable or fixed media. The supporting devices722may include input/output interfaces or communication interfaces such as USB ports, network interface, Ethernet, PCMCIA slot, etc.). The supporting devices722may allow computer programs, software, data, or other instructions to be loaded into controller714and provided to processor716for execution.

Non-transitory computer-readable storage medium, such as, main memory718, storage medium720, or any other suitable media internal or external to controller714may provide one or more sequences of one or more instructions to processor716for execution. Such instructions, generally referred to as “computer program code” (which may be grouped in the form of computer programs or other groupings), when executed by processor716, may enable the controller714to cause the ion implanting system700to perform any one or more features or functions of the processes of doping a non-planar semiconductor device described herein.

As described, the implant energy of the ion beam706may be controlled by the adjusting the extraction voltage and/or the deceleration voltage. However, adjusting the extraction voltage to control the implant energies for a multi-energy implant process, such as the exemplary processes described herein, may not be a manufacturable solution. Adjusting the extraction voltage may require long stabilization periods to achieve a stable ion beam required for implanting. Long stabilization times result in poor productivity and throughput. Alternatively, the implant energies may be controlled by adjusting the deceleration voltage. The extraction voltage may be fixed at a value that generates an ion beam having the maximum required implant energy for a given ion implant in a multi-energy implant process (e.g., a first implant energy for a first ion implant). The deceleration voltage may then be adjusted to lower the implant energy to a different implant energy for a given ion implant in a multi-energy implant process (e.g., a second implant energy for a second ion implant). Because no stabilization period is required after adjusting the deceleration voltage, the implant energy of ion beam706may be controlled more efficiently with the deceleration voltage when performing a multi-energy implant process, such as the exemplary processes described herein.

Although embodiments have been fully described with reference to the accompanying drawings, it is to be noted that various changes and modifications will become apparent to those skilled in the art. Such changes and modifications are to be understood as being included within the scope of the various embodiments as defined by the appended claims.