Solid-state imaging device, analogue-digital converting method in solid-state imaging device and imaging apparatus

The present invention provides a solid-state imaging device including: a pixel array block; a row scanning device; and an analogue-digital conversion device, the analogue-digital conversion device including: a comparing device having a reset device; a counting device that counts a comparison period from initiation to completion of comparison performed by the comparing device; and a changing device that changes a voltage at the other input terminal to a predetermined voltage after a resetting operation performed by the reset device.

CROSS REFERENCE TO RELATED APPLICATIONS

The present invention contains subject matter related to Japanese Patent Application JP 2005-162327 filed in the Japanese Patent Office on Jun. 2, 2006, the entire contents of which being incorporated here by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a solid-state imaging device, an analogue-digital converting method in the solid-state imaging device, and an imaging apparatus and, more specifically, to a solid-state imaging device configured to convert an analogue signal outputted from a unit pixel via a column signal line into a digital signal and read the digital signal, an analogue-digital converting method in the solid-state imaging device and an imaging apparatus in which the solid-state imaging device is employed as an imaging device.

In recent years, a CMOS image sensor including a column parallel Analogue-Digital Converter (hereinafter, referred to as “ADC”), in which ADCs are arranged on a column-to-column basis in a row-column (matrix) array of unit pixels, mounted thereon has been reported (for example, see W. Yang et. al, “An Integrated 800×600 CMOS Image System” ISS CC Digest of Technical Papers, pp. 304-305, February 1999).

2. Description of the Related Art

FIG. 8is a block diagram showing a configuration of a CMOS image sensor100including a column parallel ADC mounted thereon according to the related art.

InFIG. 8, a unit pixel101includes a photodiode and an in-pixel amplifier, and constitutes a pixel array block102by being arranged two-dimensionally in a row and column array. In the row-column pixel arrangement in the pixel array block102, row control lines103(103-1,103-2, . . . ) are wired on a row-to-row basis and column signal lines104(104-1,104-2, . . . ) are wired on a column-to-column basis. Control of a row address and a row scanning in the pixel array block102is performed by a row scanning circuit105via the row control lines103-1,103-2, . . . .

ADCs106are arranged for the respective column signal lines104-1,104-2, . . . and constitute a column processing block (column parallel ADC block)107on one side of the column signal lines104-1,104-2, . . . . A Digital-Analogue Converter (hereinafter, referred to as “DAC”)108for generating reference voltages RAMP of a RAMP waveform and a counter109for counting time period during which a comparing operation is performed by a comparator110, described later, by performing a counting operation synchronously with a clock CK of a predetermined cycle are also provided for the respective ADCs106.

Each ADC106includes the comparator110for comparing an analogue signal obtained from the unit pixel101in a selected row via the column signal lines104-1,104-2, . . . with the reference voltage RAMP generated by the DAC108for each column control line103-1,103-2, . . . , and a memory unit111for retaining a counted value of the counter109in response to the compared result outputted from the comparator110, and has a function to convert an analogue signal provided from the unit pixel101into an N-bit digital signal.

Control of a column address and a column scanning for each ADC106of the column processing block107is performed by a column scanning circuit112. In other words, the N-bit digital signals which are AD-converted by the respective ADCs106are read by a horizontal output line113of 2N bit in width in sequence by column scanning by the column scanning circuit112, and are transmitted to signal processing circuit114by the horizontal output line113. The signal processing circuit114includes 2N sense circuits corresponding to the horizontal output line113of 2N bit in width, a subtract circuit and an output circuit.

A timing control circuit115generates clock signals or timing signals used for the operations of the row scanning circuit105, the ADC106, the DAC108, the counter109and the column scanning circuit112on the basis of a master clock MCK, and supplies these clock signals or the timing signals to the corresponding circuit member.

Referring now to a timing chart inFIG. 9, an operation of the CMOS image sensor100according to the related art configured as described above will be described below.

After a first reading operation from the unit pixels101of a certain selected row to the column signal lines104-1,104-2, . . . is stabilized, the reference voltage RAMP of the RAMP waveform is applied from the DAC108to the comparators110. Consequently, the comparators110compare signal voltages Vx of the column signal lines104-1,104-2, . . . and the reference voltage RAMP. When the reference voltage RAMP and the signal voltages Vx become the same during this comparing operation, polarities of outputs Vco from the comparators110are inverted. In response to the reception of the inverted outputs from the comparators110, a count value N1 of the counter109corresponding to a comparison period of the comparators110is retained in the memory unit111.

In this first reading operation, a reset component ΔV of the unit pixel101is read. The reset component ΔV contains fixed pattern noise which varies from the unit pixel101to the unit pixel101as an offset. However, since the variation in reset component is generally small and a reset level is common for all the pixels, the signal voltage Vx of the column signal line104at the first reading is almost known. Therefore, at the first reading of the reset component ΔV, the comparison period of the comparator110can be shortened by adjusting the reference voltage RAMP of the RAMP waveform. In this related art, the reset component ΔV is compared during a count period (128 clocks) which corresponds to 7 bits.

In a second reading operation, the signal component corresponding to the amount of incident light is read for each unit pixel101in addition to the reset component ΔV in the same operation as in the case of the first reading operation. In other words, after the second reading operation from the unit pixels101of the certain selected row to the column signal lines104-1,104-2, . . . is stabilized, the reference voltage RAMP of the RAMP waveform is provided from the DAC108to the comparators110. Consequently, the comparators110compare the signal voltages Vx of the column signal lines104-1,104-2, . . . and the reference voltage RAMP.

Simultaneously with provision of the reference voltage RAMP to the comparators110, the counter109performs the second counting operation. Then, when the reference voltage RAMP and the signal voltages Vx become the same during the second comparing operation, the polarities of the outputs Vco from the comparators110are inverted. In response to the reception of the inverted outputs from the comparators110, a count value N2 of the counter109corresponding to the comparison period of the comparators110is retained in the memory unit111. At this time, the first count value N1 and the second count value N2 are retained in the different places in the memory unit111.

After completion of the series of AD converting operations described above, the N-bit digital signals of the first time and the second time retained in the memory unit111are supplied to the signal processing circuit114via the 2N horizontal output lines113by the column scanning by the column scanning circuit112, are applied with subtracting process of (second signal)−(first signal) in the subtract circuit (not shown) in the signal processing circuit114, and are outputted toward an outside. Subsequently, by repeating the same operation for each row in sequence, a two-dimensional image is generated.

SUMMARY OF THE INVENTION

As described above, in the ADCs106, the signal voltages Vx obtained from the unit pixels101of the selected row via the column signal lines104-1,104-2, . . . are compared with the reference voltage RAMP generated in the DAC108by the comparators110, and the count value of the counter109is stored in the memory unit111in response to the compared results outputted therefrom, so that the operation to convert the signal voltages Vx to the N-bit digital signals is achieved.

The comparator110employed here may be the one having a configuration of a differential amplifier which is generally well known. When a state in which voltages at two input terminals of the differential amplifier are balanced is compared with a state in which the signal voltage Vx is applied to one of the two input terminals and the reference voltage RAMP is applied to the other input terminal directly with the comparator110having the configuration of the differential amplifier, the output of the comparator110might not be inverted at all, or might be inverted immediately after input of the reference voltage RAMP although there may be a case in which it is inverted normally during input of the reference voltage RAMP.

Accordingly, it is desirable to provide a solid-state imaging device in which an output of compared result can be inverted reliably during input of a reference voltage RAMP in an AD converting operation using a comparator having a configuration of a differential amplifier, an AD converting method using the solid-state imaging device, and an imaging apparatus.

According to an embodiment of the present invention, there is provided a solid-state imaging device including: a pixel array block in which unit pixels each including a photoelectric conversion element are two-dimensionally arranged in a row and column array, and column signal lines are wired for each column with respect to the matrix arrangement of the unit pixels; and a row scanning device that selectively controls the respective unit pixels of the pixel array block on a row-to-row basis, the solid-state imaging device including a reset device that resets potentials at two input terminals, wherein when performing AD conversion for converting an analogue signal to a digital signal using a comparing device having a configuration of a differential amplifier that compares the analogue signal provided to one input terminal via the column signal line from the unit pixel of a row which is selectively controlled by the row scanning device and an inclined reference signal provided to the other input terminal, a voltage at the other input terminal is changed to a predetermined voltage after a resetting operation by the reset device, then a comparison period from the initiation to the completion of the comparison performed by the comparing device is counted by varying the reference signal into an inclined state, and the AD conversion is performed on the basis of the comparison period.

In the solid-state imaging device configured as described above, the voltage at the input terminal to which the reference voltage at the comparing device is applied is changed to a predetermined voltage once after the resetting operation by the reset device, then, the reference signal is varied in the inclined state, so that even though there remains a variation in voltage to some extent at the two input terminals, since the voltage at the input terminal to which the reference signal of the comparing device is provided is normally higher than the voltage at the input terminal to which the analogue signal is provided, the output of the comparing device is reliably inverted while the reference signal is being inputted, that is, during the comparison period for comparing the reference signal and the analogue signal.

According to an embodiment of the present invention, since the comparison output can be reliably inverted while the reference signal is being entered in the AD converting operation using the comparator having a configuration of the differential amplifier, the AD converting operation can be performed reliably.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Configuration of CMOS Image Sensor

FIG. 1is a block diagram showing a configuration of a solid-state imaging device according to an embodiment of the present invention, for example, a CMOS image sensor including a column parallel ADC mounted thereon.

As shown inFIG. 1, the CMOS image sensor10according to the embodiment of the present invention includes a pixel array block12in which a number of unit pixels11each having a photoelectric conversion element arranged two-dimensionally in a row and column (matrix) array, a row scanning circuit13, a column processing block14, a reference voltage supplying unit15, a column scanning circuit16, a horizontal output line17and a timing control circuit18.

In this system configuration, the timing control circuit18generates clock signals and control signals which serve as a reference of operations of the row scanning circuit13, the column processing block14, the reference voltage supplying unit15and the column scanning circuit16on the basis of a master clock MCK, and provides these signals to the row scanning circuit13, the column processing block14, the reference voltage supplying unit15and the column scanning circuit16.

A drive system and a signal processing system in the periphery for driving and controlling the respective unit pixels11of the pixel array block12, that is, the peripheral circuits such as the row scanning circuit13, the column processing block14, the reference voltage supplying unit15, the column scanning circuit16, the horizontal output line17and the timing control circuit18are integrated on a chip (semiconductor substrate)19shared with the pixel array block12.

The unit pixel11employed here, although not shown in the drawing, may have a three-transistor configuration including, for example, a transfer transistor that transfers electric charges obtained by photoelectric conversion by a photoelectric conversion element to an FD (floating diffusion) unit, a reset transistor for controlling the potential of the FD unit, and an amplifier transistor that outputs a signal according to the potential of the FD unit in addition to the photoelectric conversion element (for example, photodiode), or a four-transistor configuration further including a selection transistor that selects the pixel separately.

The pixel array block12includes the unit pixels11two-dimensionally arranged in m columns×n rows, row control lines21(21-1to21-n) wired for each row of the m columns×n rows pixel array, and column signal lines22(22-1to22-m) for each column thereof. The row control lines21-1to21-nare connected at respective ends on one side thereof to respective output terminals of the row scanning circuit13corresponding to the respective rows. The row scanning circuit13includes a shift resistor and a decoder and controls a row address or a row scanning of the pixel array block12via the row control lines21-1to21-n.

The column processing block14includes ADCs (analogue-digital converting circuits)23-1to23-mprovided for the respective pixel columns, that is, for the respective column signal lines22-1to22-m, and converts the analogue signals outputted from the respective unit pixels11of the pixel array block12on a column-to-column basis into the digital signals and outputs the same. Configuration of these ADCs23-1to23-maccording to an embodiment of the present invention will be described in detail later.

The reference voltage supplying unit15includes, for example, a DAC (digital-analogue converting circuit)151as a device for generating a reference voltage RAMP having so-called a RAMP waveform, in which a level varies stepwise (is inclined downward in this example) over time. The device for generating the reference voltage RAMP having the RAMP waveform is not limited to the DAC151.

The DAC151generates the reference voltage RAMP on the basis of a clock CK provided from the timing control circuit18under control of a control signal CS1provided from the timing control circuit18, and supplies the same to the ADCs23-1to23-min the column processing block15respectively via a reference signal line24.

The configuration of the ADCs23-1to23-maccording to the embodiment of the present invention will be described in detail.

The ADCs23-1to23-mare respectively configured to be able to perform selectively an AD converting operation corresponding to respective operation modes; a normal frame rate mode in a progressive scanning system that reads information on all the unit pixels11and a high-speed frame rate mode in which an exposure time of the unit pixel11is set to 1/N and a frame rate is increased to N-times, for example, 2 times of the normal frame rate mode.

Mode switching between the normal frame rate mode and the high-speed frame rate mode is executed by control by control signals CS2, CS3provided by the timing control circuit18. The timing control circuit18receives instruction information for switching the operating modes between the normal frame rate mode and the high-speed frame rate mode from an external host device (not shown).

All the ADCs23-1to23-mhave the same configuration, and hence the ADC23-mwill be described as an example. The ADC23-mincludes a comparator31, an up/down counter (represented as U/DCNT in the drawing)32as a counting device, a transfer switch33and a memory unit34.

The comparator31compares a signal voltage Vx of the column signal line22-maccording to a signal outputted from the respective unit pixels11on the nthcolumn in the pixel array block12with the reference voltage RAMP having the RAMP waveform supplied from the reference voltage supplying unit15. For example, when the reference voltage RAMP is larger than the signal voltage Vx, an output Vco becomes an “H” level, and when the reference voltage RAMP is lower than the signal voltage Vx, the output Vco becomes an “L” level. Examples of the circuit and the operation of the comparator31will be described later in detail.

The up/down counter32is an asynchronous counter, which receives the clock CK from the timing control circuit18simultaneously with the DAC151under the control of the control signal CS2supplied from the timing control circuit18, and performs DOWN-count or UP-count synchronously with the clock CK to count a comparison period from the initiation of a comparing operation to the termination of the comparing operation by the comparator31.

More specifically, in the normal frame rate mode, at a signal reading operation from the single unit pixel11, a comparison period at the time of a first reading operation is obtained by performing the down-count during the first reading operation, and a comparison period at the time of a second reading operation is obtained by performing the up-count during the second reading operation.

On the other hand, in the high-speed frame rate mode, the comparison period at the time of the first reading operation is obtained by retaining the counted result for the unit pixel11of a certain row as is and, subsequently, performing the down-count from the previous counted result for the unit pixel11of the next row during the first reading operation, and the comparison period at the time of the second reading operation is obtained by performing the up-count during the second reading operation.

Under the control of the control signal CS3provided by the timing control circuit18, in the normal frame rate mode, the transfer switch33is turned ON (closed) state at a time point when the counting operation of the up/down counter32for the unit pixel11of a certain row is completed, and transfers the counted result of the up/down counter32to the memory unit34.

On the other hand, in the case of the high-speed frame rate of N=2, the transfer switch33stays in OFF (opened) state at a time point when the counting operation of the up/down counter32for the unit pixel11of a certain row is completed, and subsequently, is turned ON at a time point when the counting operation of the up/down counter32for the unit pixel11of the next row is completed to transfer the counted result for the two pixels in the vertical direction of the up/down counter32to the memory unit34.

In this manner, analogue signals supplied from the respective unit pixels11in the pixel array block12via the column signal lines22-1to22-mon a column-to-column basis are converted into N-bit digital signals by the respective operations of the comparators31and the up/down counters32in the ADCs23(23-1to23-m) and are stored to the memory units34(34-1to34-m).

The column scanning circuit16includes a shift register, and controls the row address or the column scanning of the ADCs23-1to23-min the column processing block14. Under the control of the column scanning circuit16, the N-bit digital signals which are AD-converted by the respective ADCs23-1to23-mare read into the horizontal output line17in sequence, and are outputted as imaging data via the horizontal output line17.

Although not shown in the drawing since it has no direct relation to the present invention, a circuit or the like for performing various signal processing on the imaging data outputted via the horizontal output line17may be provided in addition to the above-described components.

Since the CMOS image sensor10including the column parallel ADCs mounted thereon according to the embodiment of the present invention configured as described above can selectively transfer the counted results of the up/down counters32to the memory units34via the transfer switch33, the counting operation of the up/down counters32and the reading operation of the counted results of the up/down counters32to the horizontal output line17can be controlled independently.

Example of Circuit of Comparator31

FIG. 2shows a circuit drawing showing an example of a detailed circuit configuration of the comparator31. The comparator in this example31is a differential comparator including a differential amplifier310as a basic structure.

InFIG. 2, the differential amplifier310includes Nch. input transistor pair311,312commonly connected to a source, Pch. transistor pair313,314connected between respective drains of the transistor pair311,312and a power source VDD and commonly connected to a gate, and a Nch. current source transistor315connected between a common-source connecting node of the input transistor pair311,312and the ground.

In this differential amplifier310, Pch. transistors316,317are connected between the respective gates and drains of the input transistor pair311,312. These transistors316,317serve as reset devices that are turned ON when a Low active reset pulse PSET is applied to respective gates to short circuit the respective gates and the drains of the input transistor pair311,312, thereby resetting respective gate voltages of the transistor pair311,312, that is, the voltage at two input terminals of the comparator31.

Respective one-ends of capacities318,319for cutting down a DC level are connected respectively to the respective gates of the input transistor pair311,312. The other end of the capacity318is connected to the column signal lines22(22-1to22-m) for transferring the analogue signals Vx outputted from the respective unit pixels11of the pixel array block12. The other end of the capacity319is connected to the reference signal line24for transferring the reference voltage RAMP generated by the DAC151.

Example of Operation of Comparator31

Referring now to a timing chart inFIG. 3, the circuit operation of the comparator31configured as described above will be described.

A reset component described later is read out to the column signal lines22from the unit pixel11, and an arbitrary voltage VS1is applied from the DAC151to the reference signal line24. After potentials of the column signal line22and the reference signal line24are stabilized, and immediately before the comparison is initiated, the reset pulse PSET is activated (Low active). Consequently, the transistors316,317are turned ON to short circuit the respective gates and drains of the input transistor pair311,312, thereby resetting operating points of the input transistor pair311,312as the drain voltage.

At the determined operating point, the two input terminal voltages of the differential amplifier310, that is, the offset components of the respective gate voltages of the input transistor pair311,312(DC offset of the analogue signal Vx and the reference voltage RAMP, and an offset caused by variation in threshold value of the input transistor pair311,312are almost cancelled (hereinafter, this operation is referred to as “auto-zero”). In other words, the two input terminal voltages of the differential amplifier310become almost the same. The auto-zero enables shortening of the comparison period between the analogue signal Vx and the reference voltage RAMP thereafter.

However, in the auto-zero, a slight variation in two input terminal voltages at the differential amplifier310might remain in a case in which the auto-zero period is short. Therefore, when the reference voltage RAMP is entered to the comparator31as is from the arbitrary voltage VS1and is compared with the analogue signal Vx, the output Vco of the comparator31may be normally inverted while the reference voltage RAMP is being entered. However, there is a possibility that the output Vco of the comparator31is not inverted at all, or is inverted immediately after the reference voltage RAMP is entered. In a case in which the offset is completely cancelled as well, when the reference voltage RAMP is entered as is from the arbitrary voltage VS1to perform the comparison with the analogue signal Vx, the output Vco of the comparator31is not inverted at all, or is inverted immediately after the reference voltage RAMP is entered.

Therefore, for example, this embodiment employs a configuration in which a changing unit25for changing the potential of the reference signal line24is added to change the voltage at the input terminal to which the potential of the reference signal line24, that is, the reference voltage RAMP of the comparator31is applied from the arbitrary voltage VS1to a higher voltage VS2(VS2>Vs1) after the auto zero, that is, after the resetting operation by the transistors316,317as the reset device by the operation of the changing unit25.

The changing unit25includes, for example, an Nch. transistor252connected between a voltage line251to which the voltage VS2is applied and the reference signal line24. The transistor252is turned ON by applying a High active control pulse CS4generated by the timing control circuit15to the gate after the auto-zero, that is, after the reset pulse PSET is distinguished, and applies the voltage VS2to the reference signal line24.

In this manner, by configuring to change the voltage at the input terminal to which the reference voltage RAMP of the comparator31is applied from the voltage VS1to the voltage VS2once after the auto-zero, that is, after the resetting operation by the transistors316,317, and then cause the reference voltage RAMP to be changed stepwise, even when the slight variation in the two input terminal voltages of the differential amplifier310remains in the case in which the auto-zero period is short, the voltage at the input terminal to which the reference voltage RAMP of the comparator31is applied becomes higher than the voltage at the input terminal to which the analogue signal Vx is provided. Therefore, inversion of the output Vco of the comparator31while the reference voltage RAMP is being entered, that is, during the comparison period between the reference voltage RAMP and the analogue signal Vx is ensured. In other words, the possibility that the output Vco of the comparator31is not inverted at all or that it is inverted immediately after the reference voltage RAMP is entered is eliminated.

As regards the voltage VS2, when a voltage value is extremely larger in comparison with the voltage VS1, the output voltage Vco of the comparator31is not inverted unless the comparison period between the reference voltage RAMP and the analogue signal Vx is set to a long period. Therefore, it is preferable to set the voltage VS2to a voltage value to an extent that can compensate the variation in the auto-zero, that is, the difference of the two input terminal voltages of the differential amplifier310after the resetting operations by the transistors316,317, generally to a range between several mV to several tens of mV.

In this example, the changing unit25including the Nch. transistor252connected between the voltage line251and the reference signal line24is provided, so as to change the voltage at the input terminal to which the reference voltage RAMP of the comparator31is applied to the predetermined voltage VS2by the operation of the changing unit25. However, it is only an example, and the changing device for changing the voltage at the input terminal to which the reference voltage RAMP of the comparator31is applied to the predetermined voltage VS2is not limited to the changing unit25including the transistor252.

As another example of the changing device, for example, the DAC151that generates the reference voltage RAMP itself may be employed. In this DAC151, the voltage at the input terminal to which the reference voltage RAMP of the comparator31is applied can be changed to the predetermined voltage VS2by generating the arbitrary voltage VS1, then generating the predetermined voltage VS2once, and then generating the reference voltage RAMP having the RAMP waveform, but not by generating the reference voltage RAMP directly from the arbitrary voltage VS1.

The DAC151having the function of the changing device will be described with a detailed example below.FIG. 4is a block diagram showing a detailed configuration of the DAC151which has a function of the changing device.

As shown inFIG. 4, the DAC151according to this example includes a slope current source array41, a sequential selection circuit42, an offset current source array43, an offset selection circuit44and a resistance45. The resistance45is connected between a circuit input terminal46and a circuit output terminal47. A predetermined reference voltage VREF is applied to the circuit input terminal46.

The slope current source array41includes unit current source circuits50configured as shown inFIG. 5arranged in an array. The unit current source circuit50includes, for example, Nch. switch transistor pair51,52to which the source is commonly connected, and a current source transistor53connected between the common-source connecting node and the ground of these switch transistor pair51,52. The offset current source array43also includes the unit current source circuits50arranged in an array in the same manner as the slope current source array41.

In the DAC151having the configuration as described above, when a control pulse S or an inverted pulse XS of the unit current source circuit50is activated and the switch transistor51or52is turned ON, a current flows to an end of the resistance45, and hence the reference voltage RAMP outputted from the circuit output terminal47varies. The reference voltage RAMP having a slope waveform (stepwise waveform) is generated by one of the switch transistor pair (51or52) of the unit current source circuit50being turned ON in sequence so as to increase the current flowing toward the circuit output terminal47of the resistance45gradually according to the sequential selection by the sequential selection circuit42.

The predetermined voltage VS2can be generated as an offset by controlling the switch transistor pair51,52of the unit current source circuit50in the same manner as generation of the reference voltage RAMP before generating the reference voltage RAMP. The arbitrary voltage (offset) VS1is outputted from the circuit output terminal47by the control that causes a current of the arbitrary unit current source circuit50to flow toward the circuit input terminal46of the resistance45by an output of the offset selection circuit44which is determined according to the offset amount which can be set as desired from the outside.

The changing device may be of any configuration as long as the voltage at the input terminal to which the reference voltage RAMP of the comparator31is applied can be change from the arbitrary voltage VS1to the predetermined voltage VS2once, and is not limited to the above-described two examples.

Operation of the CMOS Image Sensor

Referring now to a timing chart inFIG. 6, a general operation of the CMOS image sensor10configured as described above will be described.

Although description of the detailed operation of the unit pixel11will be omitted here, the resetting operation and the transfer operation are performed in the unit pixel11, a potential of the FD unit when being reset to a predetermined potential is outputted from the unit pixel11to the column signal line22-1to22-mas a reset component in the resetting operation, and the potential of the FD unit when the electric charge generated by the photoelectric conversion is transferred from the photoelectric conversion element is outputted from the unit pixel11to the column signal lines22-1to22-mas a signal component in the transfer operation as publicly known.

First, the arbitrary voltage VS1is set by the DAC151. Then, after a certain row i is selected by the row scanning circuit13through the row scanning operation, and a first reading operation from the unit pixel11of the selected row i to the column signal lines22-1to22-mis stabilized, the comparator31is reset by the reset pulse PSET, and then the voltages of the input terminals of the ADCs23-1to23-mto which the reference voltage RAMP of the respective comparators31is applied are changed from the arbitrary voltage VS1to the predetermined voltage VS2by the changing unit25, and then the reference voltage RAMP having the RAMP waveform is applied from the DAC151to the respective comparators31, so that the respective signal voltages (analogue signal) Vx of the column signal lines22-1to22-mand the reference voltage RAMP are compared in the comparators31.

When the clock CK is applied to the up/down counter32from the timing control circuit18simultaneously with supply of the reference voltage RAMP to the comparators31, the up/down counter32counts the comparison period with the comparator31during the first reading operation by the down-counting operation. Then, when the reference voltage RAMP and the signal voltages Vx of the column signal lines22-1to22-mbecome the same, the output Vco of the comparator31is inverted from the “H” level to the “L” level. The up/down counter32stops the down-counting operation and retains a count value according to the first comparison period with the comparator31in response to inversion of the polarity of the output Vco of the comparator31.

In the first reading operation, as described above, the reset component ΔV of the unit pixel11is read. A fixed pattern noise which varies from the unit pixel11to the unit pixel11is included in the reset component ΔV as the offset. However, since the variation in the reset component ΔV is generally small and the reset level is common for all the pixels, the signal voltages Vx of the column signal lines22-1to22-mare almost known. Therefore, when the first reset component ΔV is read out, the comparison period can be shortened by adjusting the reference voltage RAMP. In this embodiment, comparison of the reset component ΔV is performed in a count period (128 clocks) which corresponds to 7 bits.

In the second reading operation, in addition to the reset component ΔV, a signal component Vsig according to the amount of incident light for the respective unit pixels11is read out by the same operation as the first reading operation of the reset component ΔV. In other words, when the second reading operation from the unit pixel11of the selected row i to the column signal lines22-1to22-mis stabilized, and the reference voltage RAMP is applied from the DAC151to the comparators31of the ADCs23-1to23-m, whereby the comparator31performs the comparing operation between the respective signal voltages Vx of the column signal lines22-1to22-mand the reference voltage RAMP, and simultaneously, the second comparison period performed by the comparator31is counted by the up-counting operation which is opposite from the first operation by the up/down counter32.

In this manner, by setting the counting operation of the up/down counter32to perform firstly the down-counting operation, and secondly the up-counting operation, a subtracting process of (second comparison period)−(first comparison period) is automatically performed in the up/down counter32. Then, when the reference voltage RAMP and the signal voltage Vx of the column signal lines22-1to22-mbecome the same, the polarity of the output Vco of the comparator31is inverted, and in response to the inversion of the polarity, the counting operation of the up/down counter32is stopped. Consequently, the count value according to the result of the subtracting process of (second comparison period)−(first comparison period) is retained in the up/down counter32.

Since the expression: (second comparison period)−(first comparison period)=(signal component Vsig+reset component ΔV+offset component of ADC23)−(reset component ΔV+offset component of ADC23)=(signal component Vsig) is established, and the offset component for each ADC23(23-1to23-m) is removed in addition to the reset component ΔV including variations from the unit pixel11to the unit pixel11by the above-described twice reading operation and the subtracting process in the up/down counter32. Therefore, only the signal component Vsig according to the amount of incident light for each unit pixel11can be extracted. The process to eliminate the reset component ΔV including the variations from the unit pixel11to the unit pixel11is so called CDS (Correlated Double Sampling; relative double sampling) process.

Since the signal component Vsig according to the amount of incident light is read out at the time of second reading operation, it is necessary to change the reference voltage RAMP significantly for determining whether or not the amount of incident light is significant in a wide range. Therefore, the CMOS image sensor10in this embodiment is adapted to compare the reading out of the signal component Vsig during the count period (1024 clocks) which corresponds to the 10 bits. In this case, although the comparison bit number is different between the first reading operation and the second reading operation, the accuracy of the AD conversion can be equalized by equalizing the inclinations of the RAMP waveform of the reference voltage RAMP in the first and the second reading operations. Therefore, an accurate subtracted result can be obtained as a result of the subtracting process of (second comparison period)−(first comparison period) by the up/down counter32.

After the above-described series of the AD converting operation, an N bit digital value is retained in the up/down counter32. Then, the N-bit digital values (digital signal) which are AD-converted in the respective ADCs23-1to23-min the column processing block14are outputted in sequence to the outside via the horizontal output line17of N bit in width by the column scanning by the column scanning circuit16. Subsequently, a two-dimensional image is generated by repeating the same operation for each column in sequence.

As described above, in the CMOS image sensor10including the column parallel ADC mounted thereon, the output Vco of the comparator31is reliably inverted during the input of the reference voltage RAMP, that is, during the comparison period between the reference voltage RAMP and the analogue signal Vx by changing the voltage at the input terminal to which the reference voltage RAMP of the comparator31is applied into the voltage VS2once from the voltage VS1after the auto-zero, that is, after the resetting operation by the transistors316,317as the reset device, and then changing the reference voltage RAMP stepwise (inclined) without depending on the reset state of the comparator31by the reset pulse PSET.

In other words, even though there remains a variation to some extent at the two input terminal voltages of the differential amplifier310in the case in which the auto-zero period is short, the voltage at the input terminal of the comparator31to which the reference voltage RAMP is applied is normally higher than the voltage at the input terminal to which the analogue signal Vx is applied. Therefore, the output Vco of the comparator31is reliably inverted during the comparison period between the reference voltage RAMP and the analogue signal Vx. Consequently, the AD converting operation can be performed reliably. Then, by counting the comparison period from the initiation to the completion of the comparison by the comparator31with the up/down counter32, the signal voltage (analogue signal) Vx can be converted to the digital signal on the basis of the comparison period.

According to the CMOS image sensor10including the column parallel ADC according to this embodiment mounted thereon, since the ADCs23-1to23-meach include the memory unit34, the digital value of the unit pixel11of the ithrow after AD conversion is transferred to the memory unit34, and then outputted from the horizontal output line17to the outside, while the reading operation and the up/down counting operation of the unit pixel11of the i+1strow can be performed simultaneously in parallel.

However, it is not essential to provide the memory unit34for each of ADCs23-1to23-m. In other words, the present invention can also be applied to a CMOS image sensor of a configuration in which the respective ADCs23-1to23-meach do not have the memory unit34as in the case of the CMOS image sensor10including the column parallel ADC mounted thereon according to the embodiment shown above.

Example of Application

The CMOS image sensor including the column parallel ADC mounted thereon according to the above-described embodiment is preferable to be used as an imaging device in the imaging apparatus such as a video camera, digital still camera, or a camera module for a mobile device such as a cellular phone.

FIG. 7is a block diagram showing an example of a configuration of the imaging apparatus according to an embodiment of the present invention. As shown inFIG. 7, the imaging apparatus according to this example includes an optical system including a lens61, an imaging device62, a camera signal processing circuit63and a system controller64.

The lens61forms an image of an image light from a photographic object on an imaging plane of the imaging device62. The imaging device62outputs an imaging signal which can be obtained by converting the image light formed as an image on the imaging plane by the lens61into an electric signal on a pixel by pixel basis. The CMOS image sensor10including the column parallel ADC mounted thereon according to the embodiment described above is used as the imaging device62.

The camera signal processing circuit63performs various signal processing for the imaging signal outputted from the imaging device62. The system controller64controls the imaging device62or the camera signal processing circuit63. In particular, when the column parallel ADC of the imaging device62can perform the AD converting operation corresponding to the respective operating modes including the normal frame rate mode and the high-speed frame rate mode in which the exposure time of the pixel is set to 1/N to increase the frame rate to N times higher in comparison with the normal frame rate mode in the progressive scanning system which reads information on every pixel, the switching control of the operation mode according to the instruction from the outside is performed.