Semiconductor device having a fin-type semiconductor region

A fin-semiconductor region (13) is formed on a substrate (11). A first impurity which produces a donor level or an acceptor level in a semiconductor is introduced in an upper portion and side portions of the fin-semiconductor region (13), and oxygen or nitrogen is further introduced as a second impurity in the upper portion and side portions of the fin-semiconductor region (13).

RELATED APPLICATIONS

This application is the U.S. National Phase under 35 U.S.C. §371 of International Application No. PCT/JP2010/000285, filed on Jan. 20, 2010, which in turn claims the benefit of Japanese Application No. 2009-029564, filed on Feb. 12, 2009, the disclosures of which Applications are incorporated by reference herein.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device, a method for fabricating the same, and a plasma doping system, and particularly to a semiconductor device of a three-dimensional structure having a fin-type semiconductor region on a substrate, and a method for fabricating the same.

BACKGROUND ART

In recent years, as semiconductor devices have become higher in integration, functionality, and speed, demand for miniaturization of the semiconductor devices has been growing. To satisfy the demand, various device structures have been proposed for reducing the area occupied by transistors over a substrate. Among them, a field effect transistor having a fin-type structure has drawn attention. The field effect transistor having the fin-type structure is generally called a fin-FET (Fin-Field Effect Transistor), and has an active region made of a semiconductor region (hereinafter referred to as a fin-semiconductor region) having a thin-wall (fin) shape perpendicular to the principal surface of a substrate. In the fin-FET, the both side surfaces of the fin-semiconductor region can be used as channel surfaces, and accordingly the area occupied by transistors over the substrate can be reduced (see, e.g., Patent Document 1 and Non-Patent Document 1).

FIGS. 12(a)-12(d) are views each showing a structure of a conventional fin-FET, of whichFIG. 12(a) is a plan view,FIG. 12(b) is a cross-sectional view along the line A-A inFIG. 12(a),FIG. 12(c) is a cross-sectional view along the line B-B inFIG. 12(a), andFIG. 12(d) is a cross-sectional view along the line C-C inFIG. 12(a).

As shown inFIGS. 12(a)-12(d), the conventional fin-FET has a support substrate101made of silicon, an insulating layer102made of silicon dioxide formed on the support substrate101, fin-semiconductor regions103a-103dformed on the insulating layer102, a gate electrode105formed over the fin-semiconductor regions103a-103dwith gate insulating films104a-104dbeing interposed therebetween, insulating sidewall spacers106formed on the side surfaces of the gate electrode105, extension regions107formed in the both side regions of the fin-semiconductor regions103a-103dwith the gate electrode105being interposed therebetween, and source/drain regions117formed in the both side regions of the fin-semiconductor regions103a-103dwith the gate electrode105and the insulating sidewall spacers106being interposed therebetween. The fin-semiconductor regions103a-103bare disposed on the insulating layer102to be arranged at given intervals in a gate width direction. The gate electrode105is formed so as to extend over the fin-semiconductor regions103a-103din the gate width direction. Each of the extension regions107includes a first impurity region107aformed in the upper portion of each of the fin-semiconductor regions103a-103d, and second impurity regions107bformed in the side portions of each of the fin-semiconductor regions103a-103d. Each of the source/drain regions117includes a third impurity region117aformed in the upper portion of each of the fin-semiconductor regions103a-103d, and fourth impurity regions117bformed in the side portions of each of the fin-semiconductor regions103a-103d. Note that a description and depiction of pocket regions is omitted.

FIGS. 13(a)-13(d) are cross-sectional views showing a method for fabricating the conventional semiconductor device in the order of process steps. Note thatFIGS. 13(a)-13(d) correspond to a cross-sectional structure along the line C-C inFIG. 12(a). In FIGS.13(a)-13(d), the same components as those of the structure shown inFIGS. 12(a)-12(d) are provided with the same reference characters, and an overlapping description is omitted.

First, as shown inFIG. 13(a), a SOI (Silicon On Insulator) substrate is prepared in which a semiconductor layer made of silicon is provided over the support substrate101made of silicon with the insulating layer102made of silicon dioxide being interposed therebetween. Then, the semiconductor layer is patterned to form the fin-semiconductor region103bserving as an active region.

Next, as shown inFIG. 13(b), a gate insulating film104is formed on the surface of the fin-semiconductor region103b, and then a polysilicon film105A is formed over the entire surface of the support substrate101.

Next, as shown inFIG. 13(c), the polysilicon film105A and the gate insulating film104are successively etched to form the gate electrode105over the fin-semiconductor region103bwith the gate insulating film104bbeing interposed therebetween. Then, using the gate electrode105as a mask, impurity ions are implanted into the semiconductor region103bto form the extension regions107and the pocket regions (not shown).

Next, as shown inFIG. 13(d), an insulating film is formed over the entire surface of the support substrate101, and then etched back using anisotropic dry etching, thereby forming the insulating sidewall spacers106on the side surfaces of the gate electrode105. Then, using the gate electrode105and the insulating sidewall spacers106as a mask, impurity ions are implanted into the semiconductor region103bto form the source/drain regions117.

By the foregoing process steps, a fin-MISFET (Metal Insulator Semiconductor Field Effect Transistor) having the gate electrode105formed over the fin-semiconductor region103bwith the gate insulating film104bbeing interposed therebetween can be obtained.

FIG. 14(a) is a cross-sectional view showing the step of forming the extension regions of a fin-FET in Patent Document 1.FIG. 14(b) is a cross-sectional view showing the step of forming the extension regions of a fin-FET in Non-Patent Document 1. Note thatFIGS. 14(a) and14(b) correspond to a cross-sectional structure (prior to the formation of the insulating sidewall spacers106) along the line B-B inFIG. 12(a). InFIGS. 14(a) and14(b), the same components as those of the structure shown inFIGS. 12(a)-12(d) are provided with the same reference characters, and an overlying description is omitted.

As shown inFIG. 14(a), in the method disclosed in Patent Document 1, in order to introduce an impurity not only into the upper surfaces of the fin-semiconductor regions103a-103d, but also into the side surfaces thereof, ions108aand108bare implanted at respective implantation angles inclined to the opposite sides of a vertical direction into the fin-semiconductor regions103a-103d, thereby forming the extension regions107. In this case, in the upper portions of the fin-semiconductor regions103a-103d, the first impurity regions107aare formed in which both of the ions108aand108bhave been implanted. However, in the side portions of the fin-semiconductor regions103a-103d, the second impurity regions107bare formed in which either the ions108aor the ions108bhave been implanted. That is, when the dosage of the ions108aand the dosage of the ions108bare the same, the implantation dosage in each of the first impurity regions107ahas a magnitude double that of the implantation dosage in each of the second impurity regions107b.

On the other hand, as shown inFIG. 14(b), in the method disclosed in Non-Patent Document 1, the extension regions107are formed in the fin-semiconductor regions103a-103dusing a plasma doping process. When impurity introduction is performed using the plasma doping process, the first impurity regions107aeach having an introduction dosage determined by the balance among introduced ions109a, adsorbed species (neutral species such as gas molecules and radicals)109b, and impurities109cdesorbed by sputtering from the fin-semiconductor regions103a-103dare formed in the upper portions of the fin-semiconductor regions103a-103d. However, as for the introduction dosage in each of the side portions of the fin-semiconductor regions103a-103d, it is less affected by the introduced ions109aor the impurities109cdesorbed by sputtering so that the second impurity regions107beach having the introduction dosage primarily determined by the adsorbed species109bare formed in the side portions of the fin-semiconductor regions103a-103d. As a result, the introduction dosage in the first impurity region107ais higher than the introduction dosage in the second impurity region107bby, e.g., about 25%.

Thus, according to the method for forming the extension regions of the conventional fin-FET, the introduction dosage in each of the first impurity regions107aformed in the upper portions of the fin-semiconductor regions103a-103dis higher than the introduction dosage in each of the second impurity regions107bformed in the side portions of the fin-semiconductor regions103a-103d. In addition, the junction depth of the second impurity region107bis shallower than the junction depth of the first impurity region107a. As a result, the sheet resistance, specific resistance, or spreading resistance of the first impurity region107ais lower than the sheet resistance, specific resistance, or spreading resistance of the second impurity region107b. Note that, when it is assumed that the sheet resistance of a target object is Rs, the resistivity (specific resistance) thereof is ρ, the thickness (junction depth) thereof is t, and the spreading resistance thereof is ρw, Rs=ρ/t is satisfied. In addition, as represented by a relational expression ρw=CF×k×ρ/(2πr) widely known in the measurement of a spreading resistance, the resistivity (specific resistance) ρ and the spreading resistance ρw are basically in one-to-one relation so that an expression Rs∝ρw/t is obtained.

In the relational expression shown above, CF is a correction term (CF=1 in the case where there is no correction) in which the volume effect of the spreading resistance ρw is considered, k is a correction term (k=1 when the sample is, e.g., p-type silicon, and k=1 to 3 when the sample is, e.g., n-type silicon) in which polarity dependence in a Schottky barrier between a probe and a sample is considered, and r is the radius of curvature of the tip of the probe.

When the fin-FET having such an extension structure is operated, a current flowing in each of the extension regions107is localized to the first impurity region107ahaving the introduction dosage higher (i.e., sheet resistance lower) than that in the second impurity region107b. As a result, the problem arises that desired transistor characteristics cannot be obtained.

In the conventional fin-FET, the source/drain regions are also formed using the same ion implantation process or the same plasma doping process as that used to form the extension regions. Accordingly, in the source/drain regions117also, the introduction dosage in each of the third impurity regions117aformed in the upper portions of the fin-semiconductor regions103a-103dis higher than the introduction dosage in each of the fourth impurity regions117bformed in the side portions of the fin-semiconductor regions103a-103d. In addition, the junction depth of the fourth impurity region117bis shallower than the junction depth of the third impurity region117a. When the fin-FET having such a source/drain structure is operated, a current flowing in each of the source/drain regions117is localized to the third impurity region117ahaving the introduction dosage higher (i.e., sheet resistance lower) than that in the fourth impurity region117b. As a result, the problem arises that desired transistor characteristics cannot be obtained.

CITATION LIST

Patent Documents

SUMMARY OF THE INVENTION

Technical Problem

To solve the problem described above, a semiconductor device in which impurity regions each having an introduction dosage equal to or more than that in each of the upper portions of fin-semiconductor regions are provided in the side portions of the fin-semiconductor regions and a method for fabricating the same are proposed in, e.g., Patent Document 2. In accordance with the method disclosed in Patent Document 2, in the step of introducing an impurity into the fin-semiconductor regions by a plasma doping process, and thereby forming first impurity regions in the upper portions of the fin-semiconductor regions and forming second impurity regions in the side portions of the fin-semiconductor regions, a plasma doping process is performed under a first condition in which the introduction dosage becomes a first dosage, and then a plasma doping process is performed under a second condition in which the introduction dosage becomes a second dosage lower than the first dosage. This makes it possible to obtain a semiconductor device including impurity regions each having an introduction dosage equal to or more than that in each of the upper portions of the fin-semiconductor regions, i.e., a semiconductor device having desired transistor characteristics.

However, in accordance with the method disclosed in Patent Document 2, it is necessary to change the plasma doping process conditions after the introduction of the impurity has advanced to a degree, and then perform the plasma doping process till the introduction dosage sufficiently approximates the second dosage, which may result in an increased process time.

In view of the foregoing, an object of the present disclosure is to allow a semiconductor device having a fin-semiconductor region to obtain desired characteristics using a plasma doping process, and reduce a process time before the desired characteristics are obtained.

Solution to the Problem

In order to attain the above object, a first method for fabricating a semiconductor device according to the present disclosure includes the steps of: (a) forming a fin-semiconductor region on a substrate; (b) introducing a first impurity which produces a donor level or an acceptor level in a semiconductor into an upper portion and side portions of the fin-semiconductor region by a plasma doping process; and (c) introducing oxygen or nitrogen as a second impurity into the upper portion and side portions of the fin-semiconductor region.

In accordance with the first method for fabricating a semiconductor device according to the present disclosure, the first impurity which produces a donor level or an acceptor level in a semiconductor is introduced into the upper portion and side portions of the fin-semiconductor region, and oxygen or nitrogen, i.e., an impurity which changes a semiconductor into an insulator is further introduced as the second impurity into the upper portion and side portions of the fin-semiconductor region. At this time, by introducing a larger amount of the second impurity into the upper portion of the fin-semiconductor region than into each of the side portions of the fin-semiconductor region, the resistance (specific resistance, sheet resistance, or spreading resistance, which holds true hereinafter) of the side portion of the fin-semiconductor region can be set equal to or less than the resistance of the upper portion of the fin-semiconductor region. Also, by introducing the second impurity which changes a semiconductor into an insulator, it is sufficient for a process time (time required for the step (c)) required to increase the resistance of the upper portion of the fin-semiconductor region to be short. Therefore, it is possible to implement a three-dimensional device having excellent characteristics, such as a FET, with an excellent throughput.

Note that the step (b) may be performed prior to the step (c) or after the step (c).

The amount of the second impurity introduced in the side portion of the fin-semiconductor region is of an order that does not affect the respective characteristics of extension regions and source/drain regions.

As the second impurity which changes a semiconductor into an insulator, oxygen or nitrogen which is introduced into Si and forms an insulator (SiO2or SiNx) is preferably used if the semiconductor is, e.g., Si. However, it will be appreciated that the second impurity is not limited thereto.

In the first method for fabricating a semiconductor device according to the present disclosure, a plasma doping process or an ion implantation process may be used in the step (c).

The first method for fabricating a semiconductor device according to the present disclosure may further include, after both of the steps (b) and (c) are completed, the step of: (d) removing the upper portion of the fin-semiconductor region. This allows an insulator region formed in the upper portion of the fin-semiconductor region through the introduction of the second impurity therein to be removed. Therefore, it is possible to form a triple-gate FET in which the upper portion and both side portions of the fin-semiconductor region function as a channel. In this case, if a wet etching process is used in the step (d), only a portion where the second impurity which changes a semiconductor into an insulator has been introduced in a large amount can be precisely removed irrespective of an etching time. Alternatively, if a dry etching process is used in the step (d), it is possible to avoid a situation where lateral etching on a gate insulating film (etching from the side surfaces of the gate insulating film) advances.

In the first method for fabricating a semiconductor device according to the present disclosure, at the time when both of the steps (b) and (c) are completed, a resistance of each of the side portions of the fin-semiconductor region may be equal to or less than a resistance of the upper portion of the fin-semiconductor region. The arrangement allows a three-dimensional device having more excellent characteristics, such as a FET, to be implemented.

The first method for fabricating a semiconductor device according to the present disclosure may further include, after the step (a) and prior to both of the steps (b) and (c), the steps of: (e) forming a gate insulating film on at least each of side surfaces of a predetermined portion of the semiconductor region; and (f) forming a gate electrode on the gate insulating film and, in the steps (b) and (c), the first impurity and the second impurity may be introduced into the fin-semiconductor region located outside the gate electrode. The arrangement allows a three-dimensional device having more excellent characteristics, such as a FET, to be implemented.

In the first method for fabricating a semiconductor device according to the present disclosure, the first impurity may be boron, phosphorus, or arsenic. The arrangement allows the effects of the present disclosure described above to be reliably obtained.

Note that, if the second impurity is oxygen or nitrogen in the first method for fabricating a semiconductor device according to the present disclosure, the introduction of the second impurity can be performed using an oxygen gas or a nitrogen gas which is inexpensive and safe. This offers cost and process advantages.

A second method for fabricating a semiconductor device according to the present disclosure includes the steps of: (a) forming a fin-semiconductor region on a substrate; (b) introducing a first impurity which produces a donor level or an acceptor level in a semiconductor into an upper portion and side portions of the fin-semiconductor region by a plasma doping process; and (c) after the step (b), removing the upper portion of the fin-semiconductor region.

In accordance with the second method for fabricating a semiconductor device according to the present disclosure, the first impurity which produces a donor level or an acceptor level in a semiconductor is introduced into the upper portion and side portions of the fin-semiconductor region, and then the upper portion of the fin-semiconductor region is removed. As a result, it is possible to remove a high-concentration first-impurity introduced layer from the upper portion of the fin-semiconductor region, and leave a low-concentration first-impurity introduced layer therein. Accordingly, the resistance of each of the side portions of the fin-semiconductor region can be set equal to or less than the resistance of the upper portion of the fin-semiconductor region. In addition, it is sufficient for a process time (time required for the step (c)) required to remove the upper portion of the fin-semiconductor region to be short. Therefore, it is possible to implement a three-dimensional device having excellent characteristics, such as a FET, with an excellent throughput.

In the second method for fabricating a semiconductor device according to the present disclosure, a dry etching process may be used in the step (c). The arrangement allows the avoidance of a situation where lateral etching on a gate insulating film (etching from the side surfaces of the gate insulating film) advances.

In the second method for fabricating a semiconductor device according to the present disclosure, at the time when the step (c) is completed, a resistance of each of the side portions of the fin-semiconductor region may be equal to or less than a resistance of the upper portion of the fin-semiconductor region. The arrangement allows a three-dimensional device having more excellent characteristics, such as a FET, to be implemented.

The second method for fabricating a semiconductor device according to the present disclosure may further include, after the step (a) and prior to the step (b), the steps of: (d) forming a gate insulating film on at least each of side surfaces of a predetermined portion of the semiconductor region; and (e) forming a gate electrode on the gate insulating film and, in the step (b), the first impurity may be introduced into the fin-semiconductor region located outside the gate electrode. The arrangement allows a three-dimensional device having more excellent characteristics, such as a FET, to be implemented.

In the second method for fabricating a semiconductor device according to the present disclosure, the first impurity may be boron, phosphorus, or arsenic. The arrangement allows the effects of the present disclosure described above to be reliably obtained.

In the first or second method for fabricating a semiconductor device according to the present disclosure, the fin-semiconductor region may be formed on an insulating layer formed on the substrate. The arrangement allows a three-dimensional device having more excellent characteristics, such as a FET, to be implemented.

In the first or second method for fabricating a semiconductor device according to the present disclosure, the fin-semiconductor region may be made of silicon. The arrangement allows a three-dimensional device having more excellent characteristics, such as a FET, to be implemented.

A first semiconductor device according to the present disclosure includes: a fin-semiconductor region formed on a substrate, wherein a first impurity which produces a donor level or an acceptor level in a semiconductor is introduced in each of an upper portion and side portions of the fin-semiconductor region, and oxygen or nitrogen is further introduced as a second impurity in each of the upper portion and side portions of the fin-semiconductor region.

In the first semiconductor device according to the present disclosure, the first impurity which produces a donor level or an acceptor level in a semiconductor is introduced in the upper portion and side portions of the fin-semiconductor region, and oxygen or nitrogen, i.e., an impurity which changes a semiconductor into an insulator is further introduced as the second impurity in the upper portion and side portions of the fin-semiconductor region. At this time, if a larger amount of the second impurity is introduced in the upper portion of the fin-semiconductor region than in each of the side portions of the fin-semiconductor region, the resistance of the side portion of the fin-semiconductor region can be set equal to or less than the resistance of the upper portion of the fin-semiconductor region. Also, by introducing the second impurity which changes a semiconductor into an insulator, it is sufficient for a process time required to increase the resistance of the upper portion of the fin-semiconductor region to be short. Therefore, it is possible to implement a three-dimensional device having excellent characteristics, such as a FET, with an excellent throughput.

Note that the amount of the second impurity introduced in the side portion of the fin-semiconductor region is of an order that does not affect the respective characteristics of extension regions and source/drain regions.

As the second impurity which changes a semiconductor into an insulator, oxygen or nitrogen which is introduced into Si and forms an insulator (SiO2or SiNx) is preferably used if the semiconductor is, e.g., Si. However, it will be appreciated that the second impurity is not limited thereto.

In the first semiconductor device according to the present disclosure, a resistance of each of the side portions of the fin-semiconductor region may be equal to or less than a resistance of the upper portion of the fin-semiconductor region. The arrangement allows a three-dimensional device having more excellent characteristics, such as a FET, to be implemented.

In the first semiconductor device according to the present disclosure, an insulator may be formed in the upper portion of the fin-semiconductor region through introduction of the second impurity therein. In this case, a double-gate FET in which only the both side portions of the fin-semiconductor region function as a channel is formed. However, a triple-gate FET may also be formed by removing an insulator region formed through the introduction of the second impurity, and causing the upper portion of the fin-semiconductor region to function as a channel. That is, by removing the insulator region, a high-concentration first-impurity introduced layer is also removed from the upper portion of the fin-semiconductor region but, if a low-concentration first-impurity introduced layer remains under the insulator region, the triple-gate FET can be formed. Here, the resistance of a first-impurity introduced layer in each of the side portions of the fin-semiconductor region is preferably equal to or less than the resistance of the low-concentration first-impurity introduced layer remaining in the upper portion of the fin-semiconductor region. Also, the low-concentration first-impurity introduced layer remaining in the upper portion of the fin-semiconductor region may also contain the second impurity in an amount that does not affect the respective characteristics of the extension regions and the source/drain regions.

In the first semiconductor device according to the present disclosure, the fin-semiconductor region may be formed on an insulating layer formed on the substrate. The arrangement allows a three-dimensional device having more excellent characteristics, such as a FET, to be implemented.

The first semiconductor device according to the present disclosure may further include: a gate insulating film formed on at least each of side surfaces of a predetermined portion of the fin-semiconductor region; and a gate electrode formed on the gate insulating film, and the first impurity and the second impurity may be introduced in the fin-semiconductor region located outside the gate electrode. The arrangement allows a three-dimensional device having more excellent characteristics, such as a FET, to be implemented. In this case, it is particularly effective if extension regions are formed in the side portions of the fin-semiconductor region located outside the gate electrode through introduction of the first impurity therein. More preferably, the first semiconductor device according to the present disclosure further includes: insulating sidewall spacers formed on side surfaces of the gate electrode, the extension regions are formed in portions of the fin-semiconductor region covered with the insulating sidewall spacers, and source/drain regions are formed in the side portions of the fin-semiconductor region located outside the insulating sidewall spacers through introduction of the first impurity therein.

In the first semiconductor device according to the present disclosure, the fin-semiconductor region may be made of silicon, or the first impurity may be boron, phosphorus, or arsenic. The arrangement allows the effects of the present disclosure described above to be reliably obtained.

Note that, if the second impurity is oxygen or nitrogen in the first semiconductor device according to the present disclosure, the introduction of the second impurity can be performed using an oxygen gas or a nitrogen gas which is inexpensive and safe. This offers cost and process advantages.

A first plasma doping system according to the present disclosure includes: a first plasma doping apparatus for introducing a first impurity which produces a donor level or an acceptor level in a semiconductor into an object to be processed by a plasma doping process; and a second plasma doping apparatus for introducing oxygen or nitrogen as a second impurity into the object to be processed by a plasma doping process.

The first plasma doping system according to the present disclosure allows the first impurity which produces a donor level or an acceptor level in a semiconductor to be introduced into the object to be processed by the plasma doping process, and allows oxygen or nitrogen, i.e., an impurity which changes a semiconductor into an insulator to be introduced as the second impurity into the object to be processed by the plasma doping process. Therefore, it is possible to implement the first method for fabricating a semiconductor device according to the present disclosure.

A second plasma doping system according to the present disclosure includes: a plasma doping apparatus for introducing a first impurity which produces a donor level or an acceptor level in a semiconductor into an object to be processed by a plasma doping process; and an ion implantation apparatus for introducing oxygen or nitrogen as a second impurity into the object to be processed by an ion implantation process.

The second plasma doping system according to the present disclosure allows the first impurity which produces a donor level or an acceptor level in a semiconductor to be introduced into the object to be processed by the plasma doping process, and allows oxygen or nitrogen, i.e., an impurity which changes a semiconductor into an insulator to be introduced as the second impurity into the object to be processed by the ion implantation process. Therefore, it is possible to implement the first method for fabricating a semiconductor device according to the present disclosure.

The first or second plasma doping system according to the present disclosure may further include: a dry etching apparatus for performing dry etching on the object to be processed. With the arrangement, when the first method for fabricating a semiconductor device according to the present disclosure is implemented, it is possible to remove the upper portion of the fin-semiconductor region after the introduction of the first and second impurities.

A third plasma doping system according to the present disclosure includes: a plasma doping apparatus for introducing a first impurity which produces a donor level or an acceptor level in a semiconductor into an object to be processed by a plasma doping process; and a dry etching apparatus for performing dry etching on the object to be processed.

The third plasma doping system according to the present disclosure allows the first impurity which produces a donor level or an acceptor level in a semiconductor to be introduced into the object to be processed by the plasma doping process, and allows the dry etching to be performed on the object to be processed. Therefore, it is possible to implement the second method for fabricating a semiconductor device according to the present disclosure.

A third method for fabricating a semiconductor device according to the present disclosure includes the steps of: (a) forming a fin-semiconductor region on a substrate; and (b) introducing an impurity which produces a donor level or an acceptor level in a semiconductor and oxygen into upper portion and side portions of the fin-semiconductor region by a plasma doping process.

The third method for fabricating a semiconductor device according to the present disclosure allows the same effects as achieved by the first method for fabricating a semiconductor device according to the present disclosure to be obtained.

A second semiconductor device according to the present disclosure includes: a fin-semiconductor region formed on a substrate, wherein an impurity which produces a donor level or an acceptor level in a semiconductor and oxygen are introduced in upper portion and side portions of the fin-semiconductor region.

The second semiconductor device according to the present disclosure allows the same effects as achieved by the first semiconductor device according to the present disclosure to be obtained.

A fourth plasma doping system according to the present disclosure is a plasma doping system for introducing an impurity which produces a donor level or an acceptor level in a semiconductor and oxygen into an object to be processed by a plasma doping process.

The fourth plasma doping system according to the present disclosure allows the same effects as achieved by the first plasma doping system according to the present disclosure to be obtained.

ADVANTAGES OF THE INVENTION

In accordance with the present disclosure, it is possible to obtain desired characteristics by forming low-resistance impurity regions in the side portions of a fin-semiconductor region using a plasma doping process, and reduce a process time till the desired characteristics are obtained.

DESCRIPTION OF EMBODIMENTS

A semiconductor device according to the first example embodiment of the present disclosure and a method for fabricating the same will be described with reference to the drawings.

FIGS. 1(a)-1(e) are views each showing a structure of the semiconductor device according to the present example embodiment, specifically the semiconductor device having a fin-FET, of whichFIG. 1(a) is a plan view,FIG. 1(b) is a cross-sectional view along the line A-A inFIG. 1(a),FIG. 1(c) is a cross-sectional view along the line B-B inFIG. 1(a),FIG. 1(d) is a cross-sectional view along the line C-C inFIG. 1(a), andFIG. 1(e) is a cross-sectional view along the line D-D inFIG. 1(a).

As shown inFIGS. 1(a)-1(e), the fin-FET according to the present example embodiment has a support substrate11made of, e.g., silicon, an insulating layer12made of, e.g., silicon dioxide formed on the support substrate11, fin-semiconductor regions13a-13dformed on the insulating layer12and made of, e.g., silicon, a gate electrode15formed over the fin-semiconductor regions13a-13dwith gate insulating films14a-14deach made of, e.g., a silicon oxynitride film being interposed therebetween, insulating sidewall spacers16formed on the side surfaces of the gate electrode15, extension regions17formed in the both side regions of the fin-semiconductor regions13a-13dwith the gate electrode15being interposed therebetween, and source/drain regions27formed in the both side regions of the fin-semiconductor regions13a-13dwith the gate electrode15and the insulating sidewall spacers16being interposed therebetween. Each of the fin-semiconductor regions13a-13dhas a width a in a gate width direction of, e.g., about 30 nm, a width b in a gate length direction of, e.g., about 200 nm, and a height (thickness) c of, e.g., about 50 nm. The fin-semiconductor regions13a-13dare disposed on the insulating layer12to be arranged with a pitch d (e.g., about 60 nm) in the gate width direction.

Note that the upper surface and side surfaces of each of the fin-semiconductor regions13a-13dmay be or may not be perpendicular to each other. The gate electrode15is formed so as to extend over the fin-semiconductor regions13a-13din the gate width direction. The extension regions17are formed in the side portions of the fin-semiconductor regions13a-13dcovered with the insulating sidewall spacers16. The source/drain regions27are formed in the side portions of the fin-semiconductor regions13a-13dlocated outside the insulating sidewall spacers16. Note that the description and depiction of pocket regions is omitted.

The present example embodiment has the following features. That is, a first impurity (e.g., boron) which produces a donor level or an acceptor level in a semiconductor is introduced in the upper portion and side portions of each of the fin-semiconductor regions13a-13d, and a second impurity (e.g., oxygen) which changes a semiconductor into an insulator is further introduced in the upper portion of each of the fin-semiconductor regions13a-13d. In this manner, the sheet resistance of the side portions of each of the fin-semiconductor regions13a-13dis set equal to or less than the sheet resistance of the upper portion of each of the fin-semiconductor regions13a-13d.

Specifically, as shown inFIGS. 1(c) and1(d), in the upper portions of the fin-semiconductor regions13a-13dcovered with the insulating sidewall spacers16, insulator regions37are formed through the introduction of the second impurity therein and, in the upper portions of the fin-semiconductor regions13a-13dlocated outside the insulating sidewall spacers16, insulator regions47are formed through the introduction of the second impurity therein.

Also as shown inFIGS. 1(c) and1(d), in the sidewall portions of the fin-semiconductor regions13a-13dcovered with the insulating sidewall spacers16, impurity regions serving as the extension regions17are formed through the introduction of the first impurity therein and, in the side portions of the fin-semiconductor regions13a-13dlocated outside the insulating sidewall spacers16, impurity regions serving as the source/drain regions27are formed through the introduction of the first impurity therein.

Thus, in the present example embodiment, a double-gate FET is formed in which only the both side portions of the fin-semiconductor regions13a-13dfunction as a channel. That is, as the ratio of the height (height (thickness) c ofFIG. 1(a)) of each of the fin-semiconductor regions13a-13dto the width (width a in the gate width direction ofFIG. 1(a)) thereof increases, it becomes possible to more positively ensure a sufficient width in the gate width direction for each of the extension regions17and the source/drain regions27. As a result, desired transistor characteristics can be obtained.

Note that the second impurity may also be introduced into the side portions of the fin-semiconductor regions13a-13din an amount that does not affect the respective characteristics of the extension regions17and the source/drain regions27.

In the description given above, the sheet resistance of each of the side portions (the extension regions17and the source/drain regions27) of the fin-semiconductor regions13a-13dis set equal to or less than the sheet resistance of each of the upper portions (the insulator regions37and47) of the fin-semiconductor regions13a-13d. However, the same effects can be obtained if, instead of this, the specific resistance or spreading resistance of each of the side portions (the extension regions17and the source/drain regions27) of the fin-semiconductor regions13a-13dis set equal to or less than the specific resistance or spreading resistance of each of the upper portions (the insulator regions37and47) of the fin-semiconductor regions13a-13d. When it is assumed here that the sheet resistance of a target object is Rs, the resistivity (specific resistance) thereof is ρ, the thickness (junction depth) thereof is t, and the spreading resistance thereof is ρw, Rs=ρ/t is satisfied. Because the resistivity (specific resistance) ρ and the spreading resistance ρw are basically in one-to-one relation, the expression Rs∝ρw/t is obtained. A description will be given below primarily using the “sheet resistance” but, with regard to the ordering relations among the resistances, the “sheet resistance” may also be replaced with the “specific resistance” or “spreading resistance.”

The method for fabricating the semiconductor device according to the first example embodiment of the present disclosure will be described below with reference to the drawings.

FIGS. 2(a)-2(e) are cross-sectional views showing the method for fabricating the semiconductor device according to the present example embodiment in the order of process steps. Note thatFIGS. 2(a)-2(e) correspond to a cross-sectional structure along the line D-D inFIG. 1(a).

First, as shown inFIG. 2(a), a SOI substrate is prepared in which a semiconductor layer made of, e.g., silicon and having a thickness of 50 nm is provided over the support substrate11made of, e.g., silicon and having a thickness of 800 μm with the insulating layer12made of, e.g., silicon dioxide and having a thickness of 150 nm being interposed therebetween. Then, the semiconductor layer is patterned to form the n-type fin-semiconductor region13bserving as an active region. Here, the fin-semiconductor region13bhas the width a in the gate width direction of, e.g., about 30 nm, the width b in the gate length direction of, e.g., about 200 nm, and the height (thickness) c of, e.g., about 50 nm, and is disposed to be aligned with another adjacent fin-semiconductor region with the pitch d (e.g., about 60 nm).

Next, as shown inFIG. 2(b), the gate insulating film14made of, e.g., a silicon oxynitride film and having a thickness of 3 nm is formed on the surface of the fin-semiconductor region13b, and then a polysilicon film15A having a thickness of, e.g., about 60 nm is formed over the entire surface of the support substrate11.

Next, as shown inFIG. 2(c), the polysilicon film15A and the gate insulating film14are successively etched to form the gate electrode15having a width in the gate length direction of, e.g., 60 nm over the fin-semiconductor region13bwith the gate insulating film14bbeing interposed therebetween.

Then, using the gate electrode15as a mask, the first impurity (e.g., boron) which produces a donor level or an acceptor level in a semiconductor is introduced into the upper portion and side portions of the fin-semiconductor region13bby a plasma doping process. As a result, p-type first impurity regions7aare formed in the upper portion of the fin-semiconductor region13b, and p-type second impurity regions7bare formed in the side portions of the fin-semiconductor region13b.

At this time, each of the first impurity regions7ais formed to have an introduction dosage higher than that in each of the second impurity regions7b. The reason for this is as follows (seeFIG. 14(b) showing a conventional example). When impurity introduction is performed using the plasma doping process, the first impurity regions107aeach having an introduction dosage determined by the balance among introduced ions109a, adsorbed species (neutral species such as gas molecules and radicals)109b, and impurities109cdesorbed by sputtering from the fin-semiconductor regions103a-103dare formed in the upper portions of the fin-semiconductor regions103a-103d. On the other hand, as for the introduction dosage in each of the side portions of the fin-semiconductor regions103a-103d, it is less affected by the introduced ions109aor the impurities109cdesorbed by sputtering so that the second impurity regions107beach having the introduction dosage primarily determined by the adsorbed species109bare formed in the side portions of the fin-semiconductor regions103a-103d. As a result, the introduction dosage in the first impurity region107ais higher than the introduction dosage in the second impurity region107bby, e.g., about 25%.

The plasma doping process for forming the first and second impurity regions7aand7bcan be performed using, e.g., the plasma doping apparatus shown inFIG. 3. In the plasma doping apparatus shown inFIG. 3, a predetermined gas is introduced from a gas supply device52into a vacuum vessel51, while the gas is exhausted using a turbo molecule pump53as a gas exhaust device, to allow a pressure adjustment valve54to maintain the inside of the vacuum vessel51under a predetermined pressure. By supplying an RF power of, e.g., 13.56 MHz from an RF power source55to a coil58provided in the vicinity of a dielectric window57opposing a sample electrode56, an inductively coupled plasma can be generated in the vacuum vessel51. A substrate59as a sample is placed on the sample electrode56. In addition, an RF power source60for supplying an RF power to the sample electrode56is provided to function as a voltage source which controls the potential of the sample electrode56such that the substrate59as the sample has a negative potential with respect to the plasma. In this manner, it is possible to amorphize the surface of the sample or introduce an impurity by accelerating ions in the plasma toward the surface of the sample (substrate59) and causing collision therebetween.

Note that the gas supplied from the gas supply device52is exhausted from an exhaust hole61to the turbo molecule pump53. The turbo molecule pump53and the exhaust hole61are disposed immediately under the sample electrode56, and the pressure adjustment valve54is an elevator valve located immediately under the sample electrode56and immediately over the turbo molecule pump53. The sample electrode56is fixed to the vacuum vessel51by four support rods62(of which the two support rods62are depicted).

Plasma doping conditions for forming the first and second impurity regions7aand7bare such that, e.g., a raw material gas is B2H6(diborane) diluted with He (helium), the concentration of diborane in the raw material gas is 0.05 mass percent, a total flow rate of the raw material gas is 420 cc/minute (standard state), an in-chamber pressure is 0.9 Pa, an RF power supplied to the coil is 2000 W, an RF power supplied to the sample electrode is 135 W, and a substrate temperature is 20° C.

Next, using the gate electrode15as a mask, the second impurity (e.g., oxygen) which changes a semiconductor into an insulator is introduced into the upper portion of the fin-semiconductor region13bby a plasma doping process. As a result, as shown inFIG. 2(d), the insulator regions37are formed in the upper portion of the fin-semiconductor region13b. At this time, the second impurity may also be introduced into the side portions of the fin-semiconductor region13bin an amount which does not degrade the respective characteristics of the extension regions and the source/drain regions. In that case, the p-type second impurity regions7bformed in the side portions of the fin-semiconductor region13bin the step shown inFIG. 2(c) are modified into p-type second impurity regions17b. The p-type second impurity regions17bserve as the extension regions17(seeFIG. 1(c)) in the side portions of the fin-semiconductor region13bcovered with the insulating sidewall spacers16(seeFIG. 2(e)).

In the present example embodiment, the sheet resistance of each of the second impurity regions17bforming the extension regions17can be set lower than the sheet resistance of each of the insulator regions37in the upper portion of the fin-semiconductor region13b. That is, the sheet resistance, specific resistance, or spreading resistance of the second impurity region17bcan be set lower than the sheet resistance, specific resistance, or spreading resistance of the insulator region37. Accordingly, as the ratio of the height (height (thickness) c ofFIG. 1(a)) of the fin-semiconductor region13bto the width (width a in the gate width direction ofFIG. 1(a)) thereof increases, it becomes possible to more positively ensure a sufficient width in the gate width direction for each of the extension regions17, and therefore obtain desired transistor characteristics.

Here, for the plasma doping with oxygen as the second impurity which changes a semiconductor into an insulator, the plasma doping apparatus shown inFIG. 3described above, e.g., can be used. Plasma doping conditions used at that time are such that, e.g., a raw material gas is O2(oxygen), a flow rate of the raw material gas is 50 cc/minute (standard state), an in-chamber pressure is 0.5 Pa, an RW power supplied to the coil is 2000 W, an RF power supplied to the sample electrode is 800 W, and a substrate temperature is 20° C. In the case of thus performing doping with oxygen by supplying the relatively high RF power to the sample electrode, the doping results in anisotropic doping which selectively advances in a direction perpendicular to the principal surface of the substrate. As a result, the second impurity regions17bin the side portions of the fin-semiconductor region13bare scarcely doped with oxygen.

Note that the dosage of oxygen is set such that the atomic density of oxygen in the range (from the upper surface of the substrate to a depth of about several nanometers therefrom) where the insulator regions37are formed is about not less than the atomic density (about 5.0×1022/cm3) of silicon and about not more than double the atomic density of silicon.

As a typical plasma process using oxygen as a reactive species, an ashing process is well known. In contrast to the case of the ashing process where an oxidation (ashing) reaction isotropically occurs, high bias plasma doping according to the present example embodiment can cause anisotropic doping.

In the present example embodiment, plasma doping with oxygen as the second impurity may also be performed using a microwave plasma source with a magnetic field, and using a gas mixture of Ar (argon) and O2as a raw material gas (see, e.g., Japanese Laid-Open Patent Publication No. H11-219950).

Next, using the gate electrode15as a mask, impurity ions are implanted into the fin-semiconductor region13bto form n-type pocket regions, although the depiction thereof is omitted.

Next, as shown inFIG. 2(e), an insulating film having a thickness of, e.g., 60 nm is formed over the entire surface of the support substrate11, and then etched back using anisotropic dry etching to form the insulating sidewall spacers16on the side surfaces of the gate electrode15.

Then, in the same manner as in the plasma doping process for forming the first and second impurity regions7aand7b, using the gate electrode15and the insulating sidewall spacers16as a mask, the first impurity (e.g., boron) which produces a donor level or an acceptor level in a semiconductor is introduced into the upper portion and side portions of the fin-semiconductor region13bby a plasma doping process. Subsequently, in the same manner as in the plasma doping process for forming the insulator regions37, using the gate electrode15and the insulating sidewall spacers16as a mask, the second impurity (e.g., oxygen) which changes a semiconductor into an insulator is introduced into the upper portion of the fin-semiconductor region13bby a plasma doping process. As a result, as shown inFIG. 2(d), the insulator regions47are formed in the upper portion of the fin-semiconductor region13blocated outside the insulating sidewall spacers16, and p-type impurity regions serving as the source/drain regions27are formed in the side portions of the fin-semiconductor region13blocated outside the insulating sidewall spacers16.

In the present example embodiment, the sheet resistance of each of the source/drain regions27can be set lower than the sheet resistance of each of the insulator regions47in the upper portion of the fin-semiconductor region13b. That is, the sheet resistance, specific resistance, or spreading resistance of each of the source/drain regions27can be set lower than the sheet resistance, specific resistance, or spreading resistance of each of the insulator regions47. Accordingly, as the ratio of the height (height (thickness) c ofFIG. 1(a)) of the fin-semiconductor region13bto the width (width a in the gate width direction ofFIG. 1(a)) thereof increases, it becomes possible to more positively ensure a sufficient width in the gate width direction for each of the source/drain regions27, and therefore obtain desired transistor characteristics.

The present example embodiment has the following features. That is, when the extension regions17of the fin-FET are formed using the plasma doping process, the first impurity (e.g., boron) which produces a donor level or an acceptor level in a semiconductor is introduced into the upper portion and side portions of the fin-semiconductor region13bby the plasma doping process, and then the second impurity (e.g., oxygen) which changes a semiconductor into an insulator is introduced into the upper portion of the fin-semiconductor region13bby the plasma doping process. In this manner, a fin-MISFET can be obtained in which the second impurity regions17b(extension regions17) each having the sheet resistance, specific resistance, or spreading resistance lower than that of each of the insulator regions37in the upper portion of the fin-semiconductor region13bare provided in the side portions of the fin-semiconductor region13b. Accordingly, as the ratio of the height (height (thickness) c ofFIG. 1(a)) of the fin-semiconductor region13bto the width (width a in the gate width direction ofFIG. 1(a)) thereof increases, it becomes possible to more positively ensure a sufficient width in the gate width direction for each of the extension regions17, and therefore obtain desired transistor characteristics.

Moreover, since a typical plasma doping process can be used in each of the steps of introducing the first impurity and the second impurity when the extension regions17are formed, the introduction of each of the impurities can be completed in an extremely short period of time (e.g., about 10 to 120 seconds). As a result, the total process time can be significantly reduced compared with the conventional total process time.

Additionally, in the same manner as in the case of the extension regions17, when the source/drain regions27of the fin-FET are formed using the plasma doping process, the first impurity (e.g., boron) which produces a donor level or an acceptor level in a semiconductor is introduced into the upper portion and side portions of the fin-semiconductor region13bby the plasma doping process, and then the second impurity (e.g., oxygen) which changes a semiconductor into an insulator is introduced into the upper portion of the fin-semiconductor region13bby the plasma doping process. In this manner, the fin-MISFET can be obtained in which the source/drain regions27each having the sheet resistance, specific resistance, or spreading resistance lower than that of each of the insulator regions47in the upper portion of the fin-semiconductor region13bare provided in the side portions of the fin-semiconductor region13b. Accordingly, as the ratio of the height (height (thickness) c ofFIG. 1(a)) of the fin-semiconductor region13bto the width (width a in the gate width direction ofFIG. 1(a)) thereof increases, it becomes possible to more positively ensure a sufficient width in the gate width direction for each of the source/drain regions27, and therefore obtain desired transistor characteristics.

Moreover, since a typical plasma doping process can be used in each of the steps of introducing the first impurity and the second impurity when the source/drain regions27are formed, the introduction of each of the impurities can be completed in an extremely short period of time (e.g., about 10 to 120 seconds). As a result, the total process time can be significantly reduced compared with the conventional total process time.

Note that, in the present example embodiment, the exemplary case has been shown where the p-type extension regions17and the p-type source/drain regions27are formed, i.e., the p-type MISFET is formed by plasma doping the n-type fin-semiconductor region13bwith a p-type impurity. However, instead of these, n-type extension regions and n-type source/drain regions, i.e., an n-type MISFET may also be formed by doping a p-type fin-semiconductor region with an n-type impurity.

Also in the present example embodiment, when each of the extension regions17and the source/drain regions27is formed, the plasma doping with the first impurity is performed first, and then the plasma doping with the second impurity is performed. Instead, however, it is also possible that the plasma doping with the second impurity may be performed first, and then the plasma doping with the first impurity may be performed.

In the present example embodiment, the plasma doping with the second impurity may also be omitted when the source/drain regions27are formed. In this case, the second impurity may also be preliminarily introduced in a sufficient dosage into the upper portion of the fin-semiconductor region13bin the plasma doping with the second impurity when the extension regions17are formed.

A semiconductor device according to the second example embodiment of the present disclosure and a method for fabricating the same will be described with reference to the drawings.

The semiconductor device according to the present example embodiment, specifically the semiconductor device having a fin-FET has the same two-dimensional structure as the two-dimensional structure of the semiconductor device according to the first example embodiment shown inFIG. 1(a).FIGS. 4(a)-4(c) are views each showing a structure of the semiconductor device according to the present example embodiment, specifically the semiconductor device having the fin-FET, of whichFIG. 4(a) is a cross-sectional view along the line B-B inFIG. 1(a),FIG. 4(b) is a cross-sectional view along the line C-C inFIG. 1(a), andFIG. 4(c) is a cross-sectional view along the line D-D inFIG. 1(a). Note that, in the present example embodiment, the cross-sectional structure along the line A-A inFIG. 1(a) is the same as the cross-sectional structure of the semiconductor device according to the first example embodiment shown inFIG. 1(b).

As shown inFIGS. 1(a),1(b), and4(a)-4(c), the fin-FET according to the present example embodiment has the support substrate11made of, e.g., silicon, the insulating layer12made of, e.g., silicon dioxide formed on the support substrate11, the fin-semiconductor regions13a-13dformed on the insulating layer12, the gate electrode15formed over the fin-semiconductor regions13a-13dwith the gate insulating films14a-14deach made of, e.g., a silicon oxynitride film being interposed therebetween, the insulating sidewall spacers16formed on the side surfaces of the gate electrode15, the extension regions17formed in the both side regions of the fin-semiconductor regions13a-13dwith the gate electrode15being interposed therebetween, and the source/drain regions27formed in the both side regions of the fin-semiconductor regions13a-13dwith the gate electrode15and the insulating sidewall spacers16being interposed therebetween. Each of the fin-semiconductor regions13a-13dhas the width a in the gate width direction of, e.g., about 30 nm, the width b in the gate length direction of, e.g., about 200 nm, and the height (thickness) c of, e.g., about 50 nm. The fin-semiconductor regions13a-13dare disposed on the insulating layer12to be arranged in the gate width direction with the pitch d (e.g., about 60 nm).

Note that the upper surface and side surfaces of each of the fin-semiconductor regions13a-13dmay be or may not be perpendicular to each other. The gate electrode15is formed so as to extend over the fin-semiconductor regions13a-13din the gate width direction. Each of the extension regions17includes a first impurity region17aformed in the upper portion of each of the fin-semiconductor regions13a-13dand the second impurity regions17bformed in the side portions of each of the fin-semiconductor regions13a-13d. On the other hand, each of the source/drain regions27includes a third impurity region27aformed in the upper portion of each of the fin-semiconductor regions13a-13dand fourth impurity regions27bformed in the side portions of each of the fin-semiconductor regions13a-13d. Note that the description and depiction of pocket regions is omitted.

In the present example embodiment, a triple-gate FET is formed in which the upper portion and both side portions of each of the fin-semiconductor regions13a-13dfunction as a channel. The present example embodiment has the following features. That is, the introduction dosage in each of the second impurity regions17bformed in the side portions of each of the fin-semiconductor regions is set equal to or more than the introduction dosage in each of the first impurity regions17aformed in the upper portion of each of the fin-semiconductor regions. This allows the sheet resistance of the second impurity region17bforming each of the extension regions17to be set equal to or less than the sheet resistance of the first impurity region17a. As a result, even when the ratio of the width of each of the second impurity regions17bformed in the side portions of the fin-semiconductor regions to the width of each of the extension regions17in the gate width direction increases, desired transistor characteristics can be obtained. Likewise, the introduction dosage in each of the fourth impurity regions27bformed in the side portions of each of the fin-semiconductor regions is set equal to or more than the impurity dosage in each of the third impurity regions27aformed in the upper portion of each of the fin-semiconductor regions. This allows the sheet resistance of the fourth impurity region27bforming each of the source/drain regions27to be set equal to or less than the sheet resistance of the third impurity region27a. As a result, even when the ratio of the width of each of the fourth impurity regions27bformed in the side portions of the fin-semiconductor regions to the width of each of the source/drain regions27in the gate width direction increases, desired transistor characteristics can be obtained.

In the foregoing description, the sheet resistance of the second impurity region17b(fourth impurity region27b) is set equal to or less than the sheet resistance of the first impurity region17a(third impurity region27a). However, the same effects can be obtained if the specific resistance or spreading resistance of the second impurity region17b(fourth impurity region27b) is set equal to or less than the specific resistance or spreading resistance of the first impurity region17a(third impurity region27a). When it is assumed here that the sheet resistance of a target object is Rs, the resistivity (specific resistance) thereof is ρ, the thickness (junction depth) thereof is t, and the spreading resistance thereof is ρw, Rs=ρ/t is satisfied. Since the resistivity (specific resistance) ρ and the spreading resistance ρw are basically in one-to-one relation, the expression Rs∝ρw/t is obtained. A description will be given below primarily using the “sheet resistance” but, with regard to the ordering relations among the resistances, the “sheet resistance” may also be replaced with the “specific resistance” or “spreading resistance.”

Note that, as long as the implantation dosage in each of the second impurity regions17bformed in the side portions of the fin-semiconductor region is about 80% (more preferably 90%) or more of the implantation dosage in each of the first impurity regions17aformed in the upper portion of the fin-semiconductor region, the transistor characteristics can be significantly improved compared with those obtained with the prior art technology. Likewise, as long as the implantation dosage in each of the fourth impurity regions27bformed in the side portions of the fin-semiconductor region is about 80% (more preferably 90%) or more of the implantation dosage in each of the third impurity regions27aformed in the upper portion of the fin-semiconductor region, the transistor characteristics can be significantly improved compared with those obtained with the prior art technology.

In the present example embodiment, when a “Height of Side Surface of Fin-Semiconductor Region”/“Width of Upper Surface of Fin-Semiconductor Region in Gate Width Direction” ratio (hereinafter referred to as the aspect ratio) is low, even if the implantation dosage in the second impurity region17bis lower to a degree than the implantation dosage in the first impurity region17a, i.e., even if the sheet resistance, specific resistance, or spreading resistance of the second impurity region17bis higher to a degree (e.g., by about 10% or less) than the sheet resistance, specific resistance, or spreading resistance of the first impurity region17a, the degradation of the transistor characteristics is small. On the other hand, as the aspect ratio increases, the need to set the implantation dosage in the second impurity region17bequal to or more than the implantation dosage in the first impurity region17a, i.e., the need to set the sheet resistance, specific resistance, or spreading resistance of the second impurity region17bequal to or less than the sheet resistance, specific resistance, or spreading resistance of the first impurity region17aincreases. Likewise, when the aspect ratio is low, even if the implantation dosage in the fourth impurity region27bis lower to a degree than the implantation dosage in the third impurity region27a, i.e., even if the sheet resistance, specific resistance, or spreading resistance of the fourth impurity region27bis higher to a degree (e.g., by about 10% or less) than the sheet resistance, specific resistance, or spreading resistance of the third impurity region27a, the degradation of the transistor characteristics is small. On the other hand, as the aspect ratio increases, the need to set the implantation dosage in the fourth impurity region27bequal to or more than the implantation dosage in the third impurity region27a, i.e., the need to set the sheet resistance, specific resistance, or spreading resistance of the fourth impurity region27bequal to or less than the sheet resistance, specific resistance, or spreading resistance of the third impurity region27aincreases.

The method for fabricating the semiconductor device according to the second example embodiment of the present disclosure will be described below with reference to the drawings.

FIGS. 5(a)-5(g) are cross-sectional views showing the method for fabricating the semiconductor device according to the present example embodiment in the order of process steps. Note thatFIGS. 5(a)-5(g) correspond to a cross-sectional structure along the line D-D inFIG. 1(a).

First, as shown inFIG. 5(a), a SOI substrate is prepared in which a semiconductor layer made of, e.g., silicon and having a thickness of 50 nm is provided over the support substrate11made of, e.g., silicon and having a thickness of 800 μm with the insulating layer12made of, e.g., silicon dioxide and having a thickness of 150 nm being interposed therebetween. Then, the semiconductor layer is patterned to form the p-type fin-semiconductor region13bserving as an active region. Here, the fin-semiconductor region13bhas the width a in the gate width direction of, e.g., about 30 nm, the width b in the gate length direction of, e.g., about 200 nm, and the height (thickness) c of, e.g., about 50 nm, and is disposed to be aligned with another adjacent fin-semiconductor region with the pitch d (e.g., about 60 nm).

Next, as shown inFIG. 5(b), the gate insulating film14made of, e.g., a silicon oxynitride film and having a thickness of 3 nm is formed on the surface of the fin-semiconductor region13b, and then a polysilicon film15A having a thickness of, e.g., about 60 nm is formed over the entire surface of the support substrate11.

Next, as shown inFIG. 5(c), the polysilicon film15A and the gate insulating film14are successively etched to form the gate electrode15having a width in the gate length direction of, e.g., 60 nm over the fin-semiconductor region13bwith the gate insulating film14bbeing interposed therebetween.

Then, using the gate electrode15as a mask, the first impurity (e.g., arsenic) which produces a donor level or an acceptor level in a semiconductor is introduced into the upper portion and side portions of the fin-semiconductor region13bby a plasma doping process. As a result, the n-type first impurity regions7aare formed in the upper portion of the fin-semiconductor region13b, and the n-type second impurity regions7bare formed in the side portions of the fin-semiconductor region13b.

At this time, each of the first impurity regions7ais formed to have an introduction dosage higher than that in each of the second impurity regions7b. The reason for this is as follows (seeFIG. 14(b) showing a conventional example). When impurity introduction is performed using the plasma doping process, the first impurity regions107aeach having the introduction dosage determined by the balance among the introduced ions109a, the adsorbed species (neutral species such as gas molecules and radicals)109b, and the impurities109cdesorbed by sputtering from the fin-semiconductor regions103a-103dare formed in the upper portions of the fin-semiconductor regions103a-103d. On the other hand, as for the introduction dosage in each of the side portions of the fin-semiconductor regions103a-103d, it is less affected by the introduced ions109aor the impurities109cdesorbed by sputtering so that the second impurity regions107beach having the introduction dosage primarily determined by the adsorbed species109bare formed in the side portions of the fin-semiconductor regions103a-103d. As a result, the introduction dosage in the first impurity region107ais higher than the introduction dosage in the second impurity region107bby, e.g., about 25%.

The plasma doping process for forming the first and second impurity regions7aand7bcan be performed using, e.g., the plasma doping apparatus shown inFIG. 3. At this time, plasma doping conditions for forming the first and second impurity regions7aand7bare such that, e.g., a raw material gas is AsH4(arsine) diluted with He (helium), the concentration of arsine in the raw material gas is 0.3 mass percent, a total flow rate of the raw material gas is 300 cc/minute (standard state), an in-chamber pressure is 0.9 Pa, an RW power supplied to the coil is 2000 W, an RF power supplied to a sample electrode is 200 W, and a substrate temperature is 20° C.

Next, using the gate electrode15as a mask, the second impurity (e.g., oxygen) which changes a semiconductor into an insulator is introduced into the upper portion of the fin-semiconductor region13bby a plasma doping process. As a result, as shown inFIG. 5(d), the insulator regions37are formed in the surface portions of the first impurity regions7aformed in the upper portion of the fin-semiconductor region13b, and the n-type first impurity regions17a(residues of the first impurity regions7a) remain under the insulator regions37. At this time, each of the first impurity regions17amay also contain the second impurity in an amount that does not degrade the respective characteristics of the extension regions and the source/drain regions. The second impurity may also be introduced into the side portions of the fin-semiconductor region13bin an amount that does not degrade the respective characteristics of the extension regions and the source/drain regions. In that case, the n-type second impurity regions7bformed in the side portions of the fin-semiconductor region13bin the step shown inFIG. 5(c) are modified into the n-type second impurity regions17b. The first impurity regions17aand the second impurity regions17bserve as the extension regions17(seeFIG. 4(a)) in the fin-semiconductor region13bcovered with the insulating sidewall spacers16(seeFIG. 5(f)).

In the present example embodiment, the high-concentration first-impurity introduced portions of the first impurity regions7abecome the insulator regions37, and the remaining first impurity regions7abecome the first impurity regions17a. Therefore, the sheet resistance of each of the second impurity regions17bin the side portions of the fin-semiconductor region13bcan be reduced to be lower than the sheet resistance of each of the first impurity regions17ain the upper portion of the fin-semiconductor region13b. That is, the sheet resistance, specific resistance, or spreading resistance of the second impurity region17bcan be reduced to be lower than the sheet resistance, specific resistance, or spreading resistance of the first impurity region17a. Accordingly, as the ratio of the height (height (thickness) c ofFIG. 1(a)) of the fin-semiconductor region13bto the width (width a in the gate width direction ofFIG. 1(a)) thereof increases, it becomes possible to more positively ensure a sufficient width in the gate width direction for each of the extension regions17, and therefore obtain desired transistor characteristics.

Here, for the plasma doping with oxygen as the second impurity which changes a semiconductor into an insulator, the plasma doping apparatus shown inFIG. 3described above, e.g., can be used. Plasma doping conditions used at that time are such that, e.g., a raw material gas is O2(oxygen), a flow rate of the raw material gas is 50 cc/minute (standard state), an in-chamber pressure is 0.5 Pa, an RW power supplied to the coil is 2000 W, an RF power supplied to the sample electrode is 800 W, and a substrate temperature is 20° C. In the case of thus performing doping with oxygen by supplying the relatively high RF power to the sample electrode, the doping results in anisotropic doping which selectively advances in a direction perpendicular to the principal surface of the substrate. As a result, the second impurity regions17bin the side portions of the fin-semiconductor region13bare scarcely doped with oxygen.

Note that the dosage of oxygen is set such that the atomic density of oxygen in the range (from the upper surface of the substrate to a depth of about several nanometers therefrom) where the insulator regions37are formed is about not less than the atomic density (about 5.0×1022/cm3) of silicon and about not more than double the atomic density of silicon.

As a typical plasma process using oxygen as a reactive species, an ashing process is well known. In contrast to the case of the ashing process in which an oxidation (ashing) reaction isotropically occurs, high bias plasma doping according to the present example embodiment can cause anisotropic doping.

In the present example embodiment, plasma doping with oxygen as the second impurity may also be performed using a microwave plasma source with a magnetic field, and using a gas mixture of Ar (argon) and O2as a raw material gas (see, e.g., Japanese Laid-Open Patent Publication No. HEI 11-219950).

Next, as shown inFIG. 5(e), the insulator regions37formed in the upper portion of the fin-semiconductor region13bare removed. As a method for removing the insulator regions37, dry etching using a plasma made of a gas mixture of, e.g., Ar and CF4can be used. At this time, the exposed surface of the insulating layer12made of silicon dioxide is also etched, although slightly.

Here, for the dry etching process performed on the insulator regions37, a dry etching apparatus having the same structure as that of, e.g., the plasma doping apparatus shown inFIG. 3can be used. In that case, dry etching conditions are such that, e.g., a raw material gas is CF4(tetrafluoromethane) diluted with argon (Ar), the concentration of tetrafluoromethane in the raw material gas is 5 mass percent, a total flow rate of the raw material gas is 200 cc/minute (standard state), an in-chamber pressure is 1.3 Pa, an RW power supplied to the coil is 1500 W, an RF power supplied to a sample electrode is 100 W, and a substrate temperature is 20° C. In the case of thus performing dry etching by supplying the RF power to the sample electrode, the dry etching results in anisotropic etching which selectively advances only in a direction perpendicular to the principal surface of the substrate. As a result, the second impurity regions17bin the side portions of the fin-semiconductor region13bare scarcely etched.

Next, using the gate electrode15as a mask, impurity ions are implanted into the fin-semiconductor region13bto form n-type pocket regions, although the depiction thereof is omitted.

As described above, in the present example embodiment, the n-type first impurity regions17aformed in the upper portion of the fin-semiconductor region13band the n-type second impurity regions17bformed in the side portions of the fin-semiconductor region13bform the n-type extension regions17. Specifically, the first impurity regions7aformed in the step shown inFIG. 5(c) are modified into the upper-layer insulator regions37and the lower-level first impurity regions17ain the step shown inFIG. 5(d), and the insulator regions37are removed in the step shown inFIG. 5(e). At this time, the areas of the first impurity regions17aformed in the step shown inFIG. 5(c) that are heavily doped with As are selectively removed so that the As concentration in each of the first impurity regions17awhich remain in the step shown inFIG. 5(e) is low. As a result, it is possible to set the sheet resistance of each of the second impurity regions17bforming the extension regions17equal to or less than the sheet resistance of each of the first impurity regions17a. That is, it is possible to set the sheet resistance, specific resistance, or spreading resistance of the second impurity region17bequal to or less than the sheet resistance, specific resistance, or spreading resistance of the first impurity region17a. Therefore, even when the ratio of the width of each of the second impurity regions17bformed in the side portions of the fin-semiconductor region13bto the width of each of the extension regions17in the gate width direction increases, desired transistor characteristics can be obtained.

Next, as shown inFIG. 5(f), an insulating film having a thickness of, e.g., 60 nm is formed over the entire surface of the support substrate11, and then etched back using anisotropic dry etching to form the insulating sidewall spacers16on the side surfaces of the gate electrode15.

Thereafter, in the same manner as in the plasma doping process for forming the first and second impurity regions7aand7b, using the gate electrode15and the insulating sidewall spacers16as a mask, the first impurity (e.g., arsenic) which produces a donor level or an acceptor level in a semiconductor is introduced into the upper portion and side portions of the fin-semiconductor region13bby a plasma doping process. Subsequently, in the same manner as in the plasma doping process for forming the insulator regions37, using the gate electrode15and the insulating sidewall spacers16as a mask, the second impurity (e.g., oxygen) which changes a semiconductor into an insulator is introduced into the upper portion of the fin-semiconductor region13bby a plasma doping process. As a result, as shown inFIG. 5(f), the n-type third impurity regions27aare formed in the upper portion of the fin-semiconductor region13blocated outside the insulating side wall spacers16, and the surface portions thereof are modified into the insulator regions47. On the other hand, the n-type fourth impurity regions27bare formed in the side portions of the fin-semiconductor region13blocated outside the insulating sidewall spacers16. The third impurity regions27aand the fourth impurity regions27bform the source/drain regions27. Note that each of the third and fourth impurity regions27aand27bmay also contain the second impurity in an amount that does not degrade the characteristics of the source/drain regions27.

Next, as shown inFIG. 5(g), the insulator regions47formed in the upper portion of the fin-semiconductor region13bare removed. As a method for removing the insulator regions47, dry etching using a plasma made of a gas mixture of, e.g., Ar and CF4can be used. At this time, the exposed surface of the insulating layer12made of silicon dioxide is also etched, although slightly.

As described above, in the present example embodiment, the n-type third impurity regions27aformed in the upper portion of the fin-semiconductor region13band the n-type fourth impurity regions27bformed in the side portions of the fin-semiconductor region13bform the n-type source/drain regions27. Specifically, in the step shown inFIG. 5(f), the third impurity regions27aare formed, and the surface portions thereof are modified into the insulator regions47and, in the step shown inFIG. 5(g), the insulator regions47are removed. At this time, the areas of the third impurity regions27aformed in the step shown inFIG. 5(f) that are heavily doped with As are selectively removed so that the As concentration in each of the third impurity regions27awhich remain in the step shown inFIG. 5(g) is low. As a result, it is possible to set the sheet resistance of each of the fourth impurity regions27bforming the source/drain regions27equal to or less than the sheet resistance of each of the third impurity regions27a. That is, it is possible to set the sheet resistance, specific resistance, or spreading resistance of the fourth impurity region27bequal to or less than the sheet resistance, specific resistance, or spreading resistance of the third impurity region27a. Therefore, even when the ratio of the width of each of the fourth impurity regions27bformed in the side portions of the fin-semiconductor region13bto the width of each of the source/drain regions27in the gate width direction increases, desired transistor characteristics can be obtained.

The present example embodiment has the following features. That is, when the extension regions17of the fin-FET are formed using a plasma doping process, the first impurity (e.g., arsenic) which produces a donor level or an acceptor level in a semiconductor is introduced into the upper portion and side portions of the fin-semiconductor region13bby a plasma doping process, and then the second impurity (e.g., oxygen) which changes a semiconductor into an insulator is introduced into the upper portion of the fin-semiconductor region13bby a plasma doping process. In this manner, the surface portions of the first impurity regions17aformed in the upper portion of the fin-semiconductor region13bare modified into the insulator regions37, and then the insulator regions37are removed. As a result, a fin-MISFET (triple-gate FET in which the upper portion and both side portions of the fin-semiconductor region13bfunction as a channel) can be obtained which includes the extension regions17including the first impurity regions17aremaining in the upper portion of the fin-semiconductor region13band the second impurity regions17beach having the sheet resistance, specific resistance, or spreading resistance equal to or less than that of the first impurity region17a. Accordingly, as the ratio of the height (height (thickness) c ofFIG. 1(a)) of the fin-semiconductor region13bto the width (width a in the gate width direction ofFIG. 1(a)) thereof increases, it becomes possible to more positively ensure a sufficient width in the gate width direction for each of the extension regions17, and therefore obtain desired transistor characteristics.

In addition, since a typical plasma doping process can be used in each of the steps of introducing the first impurity and the second impurity when the extension regions17are formed, the introduction of each of the impurities can be completed in an extremely short period of time (e.g., about 10 to 120 seconds). Moreover, since the step of removing the insulator regions37is a typical etching step, the step can be completed in an extremely short period of time (e.g., about 5 to 30 seconds). Therefore, the total process time can be significantly reduced compared with the conventional total process time.

When the source/drain regions27of the fin-FET are formed using a plasma doping process, the first impurity (e.g., arsenic) which produces a donor level or an acceptor level in a semiconductor is introduced into the upper portion and side portions of the fin-semiconductor region13bby a plasma doping process, and then the second impurity (such as, e.g., oxygen) which changes a semiconductor into an insulator is introduced into the upper portion of the fin-semiconductor region13bby a plasma doping process, in the same manner as in the case of the extension regions17. In this manner, the surface portions of the third impurity regions27aformed in the upper portion of the fin-semiconductor region13bare modified into the insulator regions47, and then the insulator regions47are removed. As a result, the fin-MISFET (triple-gate FET in which the upper portion and both side portions of the fin-semiconductor region13bfunction as a channel) can be obtained which includes the source/drain regions27including the third impurity regions27aremaining in the upper portion of the fin-semiconductor region13band the fourth impurity regions27beach having the sheet resistance, specific resistance, or spreading resistance equal to or less than that of the third impurity region27a. Accordingly, as the ratio of the height (height (thickness) c ofFIG. 1(a)) of the fin-semiconductor region13bto the width (width a in the gate width direction ofFIG. 1(a)) thereof increases, it becomes possible to more positively ensure a sufficient width in the gate width direction for each of the source/drain regions27, and therefore obtain desired transistor characteristics.

In addition, since a typical plasma doping process can be used in each of the steps of introducing the first impurity and the second impurity when the source/drain regions27are formed, the introduction of each of the impurities can be completed in an extremely short period of time (e.g., about 10 to 120 seconds). Moreover, since the step of removing the insulator regions47is a typical etching step, the step can be completed in an extremely short period of time (e.g., about 5 to 30 seconds). Therefore, the total process time can be significantly reduced compared with the conventional total process time.

Note that, in the present example embodiment, the exemplary case has been shown where the n-type extension regions17and the n-type source/drain regions27are formed, i.e., the n-type MISFET is formed by plasma doping the p-type fin-semiconductor region13bwith an n-type impurity. However, instead of these, p-type extension regions and p-type source/drain regions, i.e., a p-type MISFET may also be formed by doping an n-type fin-semiconductor region with a p-type impurity.

Also in the present example embodiment, when each of the extension regions17and the source/drain regions27is formed, the plasma doping with the first impurity is performed first, and then the plasma doping with the second impurity is performed. Instead, however, it is also possible that the plasma doping with the second impurity may be performed first, and then the plasma doping with the first impurity may be performed.

In the present example embodiment, the plasma doping with the second impurity (i.e., the formation of the insulator regions47) may also be omitted when the source/drain regions27are formed. It will be appreciated that, in this case, the step of removing the insulator regions47is also unnecessary.

Also in the present example embodiment, as the method for removing the insulator regions37and47formed in the upper portion of the fin-semiconductor region13b, the exemplary case has been shown which uses dry etching using a plasma made of the gas mixture of Ar and CF4. However, instead of this, anisotropic etching by dry etching (sputter etching) using a plasma made of an inert gas such as Ar may also be performed. Otherwise, the insulator regions37and47may also be removed by wet etching by, e.g., dipping the support substrate11in a hydrofluoric acid solution. In this case, an etching reaction has isotropy, but the second impurity (oxygen) which changes a semiconductor into an insulator has not been introduced into the second and fourth impurity regions17band27b. As a result, etching of the second and fourth impurity regions17band27bdoes not advance.

FIG. 6shows an As concentration profile (dot-dash line) in a silicon substrate into which As (arsenic) and O (oxygen) have been introduced each by plasma doping and an As concentration profile (solid line) in the silicon substrate after the insulator regions formed through the introduction of O (oxygen) are removed. Here, a depth of 0 nm on the abscissa corresponds to the surface of the silicon substrate after the insulator regions are removed. That is,FIG. 6shows the case where the insulator regions each having a thickness of 6 nm are formed, but it will be appreciated that this case is only illustrative. Note that the removal of the insulator regions is performed by wet etching, and the measurement of the As concentration is performed by SIMS (Secondary Ion Mass Spectrometry). As shown inFIG. 6, prior to wet etching, As has been introduced at a high concentration into the portion of the silicon substrate from the outermost surface (corresponding to a depth of −6 nm on the abscissa) thereof to a depth of about 6 nm. However, as a result of the removal of the portion by wet etching, the introduction dosage of As is significantly reduced in the surface portion of the silicon substrate after wet etching.

That is, in the case of using dry etching for the removal of the insulator regions37and47, an advantage is obtained that a situation where lateral etching of a gate insulating film (etching from the side surfaces of the gate insulating film) advances can be avoided. On the other hand, in the case of using wet etching, the following advantage is obtained. That is, since an etching selectivity between silicon dioxide (or a silicon nitride) forming the insulator regions37and47and silicon forming the fin-semiconductor region13bsignificantly increases as compared to that in the case of dry etching, only the portions where the second impurity which changes a semiconductor into an insulator has been introduced in large amounts can be precisely removed irrespective of an etching time.

In the first and second example embodiments, the exemplary case has been shown in which B2H6diluted with He or AsH4diluted with He is used as the raw material gas in the plasma doping with the first impurity which produces a donor level or an acceptor level in a semiconductor. However, the raw material gas is not limited thereto, and a gas mixture obtained by diluting a raw material gas containing the impurity (hereinafter referred to as an impurity raw material gas) with an inert gas can be used. Specifically, as the impurity raw material gas, BxHy, AsxHy, PxHy(where each of x and y is a natural number), or the like can be used. These gases are advantageous in that, besides B, As, and P, only H which is less influential even when mixed as an impurity in a substrate is contained therein. However, it is also possible to use another gas containing B such as, e.g., BF3, BCl3, or BBr3, and use another gas containing P such as, e.g., PF3, PF5, PCl3, PCl5, or POCl3. As an inert gas for dilution, He, Ne, Ar, Kr, Xe, or the like can be used, but He is most appropriate. The main reason for that is a low sputtering property. An inert gas preferred second to He is Ne. Ne has a drawback of a sputter rate slightly higher than that of He, but has an advantage of a low voltage which allows easy discharging.

Note that, in the case of using B2H6diluted with He as the raw material gas in the plasma doping with the first impurity which produces a donor level or an acceptor level in a semiconductor as used in the first example embodiment, the mass concentration of B2H6in the raw material gas is preferably not less than 0.01% and not more than 1%. The arrangement allows easy introduction of boron into the fin-semiconductor region. Conversely, when the concentration of a B2H6gas is less than 0.01%, it is difficult to introduce a sufficient amount of boron and, when the concentration of the B2H6gas is more than 1%, a deposit containing boron tends to easily adhere to the surface of the substrate. It will be appreciated that plasma doping may also be performed using a solid impurity source without using the impurity raw material gas.

In each of the first and second example embodiments, the exemplary method has been shown in which the second impurity which changes a semiconductor into an insulator is introduced into the upper portion of the fin-semiconductor region by the plasma doping process. Instead, however, the second impurity may also be introduced into the upper portion of the fin-semiconductor region by an ion implantation process. When the ion implantation process is used, a process having anisotropy stronger than that of the plasma doping process can be performed. As a result, it is possible to change only the upper portion of the fin-semiconductor region into an insulator without even slightly changing the side portions of the fin-semiconductor region into an insulator.

Also in each of the first and second example embodiments, the exemplary case has been shown where oxygen is used as the second impurity which changes a semiconductor into an insulator. However, instead of this, nitrogen may also be used. Silicon nitride obtained by introducing nitrogen into silicon is an insulator similarly to silicon dioxide, which can be selectively removed by anisotropic dry etching and has a high etching selectivity to silicon in wet etching using, e.g., a hydrofluoric acid solution similarly to silicon dioxide. It will be appreciated that the second impurity is not limited to oxygen or nitrogen but, when the second impurity is oxygen or nitrogen, it offers cost and process advantages since the introduction of the second impurity can be performed using an oxygen gas or a nitrogen gas which is inexpensive and safe.

In the second example embodiment, the exemplary method has been shown in which, after the first impurity which produces a donor level or an acceptor level in a semiconductor is introduced into the upper portion and side portions of the fin-semiconductor region, the second impurity which changes a semiconductor into an insulator is introduced into the upper portion of the fin-semiconductor region to form the insulator regions, and then the insulator regions are removed. However, instead of this, it is also possible that, after the first impurity is introduced into the upper portion and side portions of the fin-semiconductor region, the upper portion of the fin-semiconductor region into which the first impurity has been introduced may be removed using an anisotropic removing reaction such as dry etching without performing the introduction of the second impurity. This allows the high-concentration first-impurity introduced layers to be removed from the upper portion of the fin-semiconductor region, and then allows the low-concentration first-impurity introduced layers to remain therein. Therefore, it is possible to implement a fin-FET including the extension regions and the source/drain regions in each of which the sheet resistance, specific resistance, or spreading resistance of each of the impurity regions formed in the side portions of the fin-semiconductor region is equal to or less than the sheet resistance, specific resistance, or spreading resistance of each of the impurity regions formed in the upper portion of the fin-semiconductor region (after the removing step).

In the first and second example embodiments, the plasma doping apparatus (first plasma doping apparatus) used for the plasma doping with the first impurity which produces a donor level or an acceptor level in a semiconductor and the plasma doping apparatus (second plasma doping apparatus) used for the plasma doping with the second impurity which changes a semiconductor into an insulator may have the same structure as that of, e.g., the plasma doping apparatus shown inFIG. 3. However, it is preferred that the first plasma doping apparatus and the second plasma doping apparatus have different vacuum chambers (vacuum vessels) as respective specific entities thereof. This is because the arrangement allows the avoidance of the possibility that a reaction product formed when an organic material (such as a resist) on the substrate is etched by an oxygen plasma may remain in the vacuum vessel, and cause undesirable contamination. Such a structure can be implemented by, e.g., the plasma doping system shown inFIG. 7. As shown inFIG. 7, a substrate loaded in the vacuum vessel71aof a load-lock chamber71is moved into a transfer chamber72by a transfer arm72a, and then moved into the vacuum vessel73aof a first plasma doping apparatus73where the first impurity which produces a donor level or an acceptor level in a semiconductor is introduced into the substrate. Subsequently, the substrate is moved again into the transfer chamber72by the transfer arm72a, and then moved into the vacuum vessel74aof a second plasma doping apparatus74where the second impurity which changes a semiconductor into an insulator is introduced into the substrate. Thereafter, the substrate is moved again into the transfer chamber72by the transfer arm72a, then moved into the vacuum vessel71aof the load-lock chamber71, and retrieved.

Likewise, it is also preferred in the second example embodiment that the vacuum chamber (vacuum vessel) of the dry etching apparatus as a specific entity thereof is different from the vacuum vessels of the first and second plasma doping apparatus as the respective specific entities thereof. This is because the arrangement allows the avoidance of the probability that a reaction product formed when an organic material (such as a resist) on the substrate is etched by a plasma for etching or a halogen element such as fluorine may remain in the vacuum vessel, and cause undesirable contamination. Such a structure can be implemented by, e.g., the plasma doping system shown inFIG. 8. As shown inFIG. 8, a substrate loaded in the vacuum vessel71aof the load-lock chamber71is moved into the transfer chamber72by the transfer arm72a, and then moved into the vacuum vessel73aof the first plasma doping apparatus73where the first impurity which produces a donor level or an acceptor level in a semiconductor is introduced into the substrate. Subsequently, the substrate is moved again into the transfer chamber72by the transfer arm72a, and then moved into the vacuum vessel74aof the second plasma doping apparatus74where the second impurity which changes a semiconductor into an insulator is introduced into the substrate. Then, the substrate is moved again into the transfer chamber72by the transfer arm72a, and then moved into the vacuum vessel75aof a dry etching apparatus75where the insulator regions formed in the upper portion of the fin-semiconductor region are removed by a dry etching process. Thereafter, the substrate is moved again into the transfer chamber72by the transfer arm72a, then moved into the vacuum vessel71aof the load-lock chamber71, and retrieved.

It will be appreciated that, in each of the plasma doping systems shown inFIGS. 7 and 8, instead of the second plasma doping apparatus74used for the introduction of the second impurity which changes a semiconductor into an insulator, an ion implantation apparatus used for the introduction of the second impurity which changes a semiconductor into an insulator may also be provided.

In the second example embodiment, in the case where the first impurity which produces a donor level or an acceptor level in a semiconductor is introduced into the upper portion and side portions of the fin-semiconductor region, and then the upper portion of the fin-semiconductor region in which the first impurity has been introduced is removed using an anisotropic removing reaction such as dry etching without introducing the second impurity which changes a semiconductor into an insulator into the upper portion of the fin-semiconductor region, the use of, e.g., the plasma doping system shown inFIG. 9is preferred. As shown inFIG. 9, the substrate loaded in the vacuum vessel71aof the load-lock chamber71is moved into the transfer chamber72by the transfer arm72a, and then moved into the vacuum vessel73aof the first plasma doping apparatus73where the first impurity which produces a donor level or an acceptor level in a semiconductor is introduced into the substrate. Subsequently, the substrate is moved again into the transfer chamber72by the transfer arm72a, and then moved into the vacuum vessel75aof the dry etching apparatus75where the insulator regions formed in the upper portion of the fin-semiconductor region are removed by a dry etching process. Thereafter, the substrate is moved again into the transfer chamber72by the transfer arm72a, then moved into the vacuum vessel71aof the load-lock chamber71, and retrieved.

To the first and second example embodiments, various modifications can be made.

FIG. 10is a plan view of a semiconductor device according to a variation of the first example embodiment of the present disclosure, specifically a semiconductor device having a fin-FET. InFIG. 10, the same components as those of the structure of the first example embodiment shown inFIGS. 1(a)-1(e) are provided with the same reference characters, and an overlapping description is omitted. As shown inFIG. 10, the present variation is different from the first example embodiment shown inFIGS. 1(a)-1(e) in that the both end portions of the fin-semiconductor regions13a-13din the gate length direction are connected by other fin-semiconductor regions13eand13f. According to the present variation, the same effects as obtained in the first example embodiment can be obtained, and one fin-FET can be formed from the fin-semiconductor regions13a-13f. It will be appreciated that a similar modification can be made to the second example embodiment.

FIGS. 11(a)-11(d) are views each showing a structure of a semiconductor device according to another variation of the first example embodiment of the present disclosure, specifically a semiconductor device having a fin-FET. Note that the two-dimensional structure of the present variation is the same as the two-dimensional structure of the first example embodiment shown inFIG. 1(a).FIG. 11(a) is a cross-sectional view along the line A-A inFIG. 1(a).FIG. 11(b) is a cross-sectional view along the line B-B inFIG. 1(a).FIG. 11(c) is a cross-sectional view along the line C-C inFIG. 1(a).FIG. 11(d) is a cross-sectional view along the line D-D inFIG. 1(a). As shown inFIGS. 11(a)-11(d), the present variation is different from the first example embodiment shown inFIGS. 1(a)-1(e) in the following point.

That is, in the first example embodiment, the gate insulating films14a-14deach made of, e.g., a silicon oxynitride film and having a thickness of 3 nm are formed on the upper surfaces and side surfaces of the fin-semiconductor regions13a-13d. By contrast, in the present variation, the gate insulating films14a-14dare formed only on the side surfaces of the fin-semiconductor regions13a-13d, and insulating films24a-24deach made of, e.g., a silicon dioxide film and having a thickness of 20 nm are formed on the upper surfaces of the fin-semiconductor regions13a-13d. That is, in the present variation, by using only the both side portions of the fin-semiconductor regions13a-13das a channel region, a double-gate FET is formed. With such a structure also, as long as the aspect ratio (“Height of Side Surface of Fin-Semiconductor Region”/“Width of Upper Surface of Fin-Semiconductor Region in Gate Width Direction”) is high, the same effects as obtained in the first example embodiment can be obtained.

INDUSTRIAL APPLICABILITY

The present disclosure relates to a semiconductor device, a method for fabricating the same, and a plasma doping system, and is particularly useful in obtaining desired characteristics in a semiconductor device of a three-dimensional structure having a fin-type semiconductor region on a substrate

DESCRIPTION OF REFERENCE CHARACTERS