Communication system

A communication system in which circuits for generating transmitting-end synchronizing signals and receiving-end synchronizing signals can be realized easily even in the case of a data transmission rate being high and in which power consumption is low. A transmitting-end synchronizing signal selector in a transmitter selects one of a plurality of transmitting-end synchronizing signals with different phases outputted from a transmitting-end synchronizing signal generator on the basis of code-spread data to be transmitted. A transmitting-end signal output unit outputs a radio signal in synchronization with the selected transmitting-end synchronizing signal. A receiving-end synchronizing signal selector in a receiver selects one of a plurality of receiving-end synchronizing signals which are outputted from a receiving-end synchronizing signal generator and which are the same as the plurality of transmitting-end synchronizing signals on the basis of a despreading code. A receiving-end signal output unit outputs a correlation-detected signal which is synchronized with the selected receiving-end synchronizing signal and with which the correlation of the radio signal is detected. A correlator detects a correlation between the radio signal transmitted from the transmitter and the correlation-detected signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefits of priority from the prior Japanese Patent Application No. 2003-365171, filed on Oct. 24, 2003, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

This invention relates to a communication system and, more particularly, to a communication system for performing UWB communication.

(2) Description of the Related Art

Currently, the operation speed of CPUs used in electronics has progressively increased. If the operation speed (frequency) of CPUs used in electronics for radio communication becomes approximately equal to a radio communication frequency, then they will interfere with each other. Accordingly, electronics for radio communication must use radio signals at higher frequencies.

The frequency bands of 3.1 to 10.6 GHz (microwave) and 22 to 29 GHz (sub-millimeter wave) are allocated for ultrawide band (UWB) communication and probing in which a bandwidth ratio (bandwidth/center frequency) is higher than or equal to 20% or in which a bandwidth wider than or equal to 500 MHz is used. The UWB techniques will also be used in a milliwave band in the future.

A bandwidth ratio is high in the microwave band. This enables communication in which the hopping of the time when a single cycle pulse occurs is performed without using a carrier wave. A bandwidth to center frequency ratio is low in the sub-millimeter wave or millimeter wave band compared to microwave UWB band, so a wave train of several to several hundred waves can be used instead of a single cycle pulse in the microwave UWB monocycle system.

FIG. 27is a block diagram of a UWB transmitter for performing direct sequence spread spectrum communication. A code spreader142spreads data to be transmitted by the use of a spreading code outputted from a code generator141and sends it to a waveform generator143. The waveform generator143generates a single cycle pulse or a burst waveform on the basis of the spread data to be transmitted. A band pass filter (BPF)144takes only a predetermined band from the single cycle pulse or the burst waveform. The predetermined band is transmitted from an antenna145.

FIG. 28is a block diagram of a UWB receiver for performing direct sequence spread spectrum communication. Only a permissible band of the UWB signal received by an antenna151is outputted to a pulse correlator153via a BPF152. On the other hand, a code spreader155generates a spreading signal from a code generated by a code generator154. A waveform generator156generates a received waveform template corresponding to the spreading signal. The pulse correlator153detects a correlation between the received waveform template and the received signal. (With binary phase shift keying (BPSK), there is a non-inverted or inverted correlation between the template and the received signal over the entire length of the spreading code. Therefore, after the pulse correlation detection a positive or negative correlation signal is obtained by performing integration over each code interval.) A pulse train integrator157calculates an integration value for the received signal in each code interval. A comparator158takes demodulated data on the basis of whether the integration value is positive or negative.

The code spreaders and the waveform generators in the transmitter and the receiver must operate at a clock frequency given by (data transmission rate×spreading code length/number of modulated bits). For example, if a data transfer rate is 500 Mbps, spreading code length is 64 bits, and the number of modulated bits is one, then the code spreaders and the waveform generators must operate at a clock frequency of 3.2 GHz.

An oscillation circuit capable of generating multiphase clocks, such as two-phase clocks, which have a certain phase difference and a stable frequency and in which phase noise is low without dividing a high source oscillation frequency or using many phase shifters is disclosed (see, for example, Japanese Unexamined Patent Publication No. 2002-208817, paragraph nos. [0011]-[0021] and FIGS. 1-4).

SUMMARY OF THE INVENTION

In the present invention, a communication system comprising a transmitter including a code spreader for performing code spreading on data to be transmitted, a transmitting-end synchronizing signal generator for generating a plurality of transmitting-end synchronizing signals with different phases on which the timing of the outputting of a radio signal is based, a transmitting-end synchronizing signal selector for selecting one of the plurality of transmitting-end synchronizing signals on the basis of the code-spread data to be transmitted, and a transmitting-end signal output unit for outputting the radio signal in synchronization with the selected transmitting-end synchronizing signal and a receiver including a code output unit for outputting a despreading code for performing despreading on the radio signal, a receiving-end synchronizing signal generator for generating a plurality of receiving-end synchronizing signals which are the same as the plurality of transmitting-end synchronizing signals, a receiving-end synchronizing signal selector for selecting one of the plurality of receiving-end synchronizing signals on the basis of the despreading code, a receiving-end signal output unit for outputting a correlation-detected signal which is synchronized with the selected receiving-end synchronizing signal and with which the correlation of the radio signal is detected, and a correlator for detecting a correlation between the radio signal and the correlation-detected signal is provided.

The above and other features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Each of transmitters and receivers includes a circuit for generating a synchronizing signal used for determining timing with which a radio signal of a single cycle pulse or a burst wave is outputted. A high data transfer rate will make it difficult to realize a synchronizing signal generation circuit and result in an increase in power consumption.

The present invention was made in order to solve such problems. An object of the present invention is to provide a communication system in which a synchronizing signal generation circuit can be realized easily even in the case of a high data transfer rate and which can control an increase in power consumption.

The principles underlying the present invention will now be described with reference to the drawing.

FIG. 1is a view for describing the principles underlying a communication system according to the present invention.

A transmitter1shown inFIG. 1includes a code spreader1a, a transmitting-end synchronizing signal generator1b, a transmitting-end synchronizing signal selector1c, a transmitting-end signal output unit1d, and an antenna1e. A receiver2includes a code output unit2a, a receiving-end synchronizing signal generator2b, a receiving-end synchronizing signal selector2c, a receiving-end signal output unit2d, a correlator2e, and an antenna2f.

A spreading code and data to be transmitted are inputted to the code spreader1ain the transmitter1. The code spreader1aspreads the data to be transmitted by the use of the spreading code and outputs the spread data to the transmitting-end synchronizing signal selector1c.

The transmitting-end synchronizing signal generator1bgenerates a plurality of transmitting-end synchronizing signals with different phases.

The transmitting-end synchronizing signal selector1cselects one of the plurality of transmitting-end synchronizing signals outputted from the transmitting-end synchronizing signal generator1bon the basis of the signal to be transmitted code-spread by the code spreader1a.

The transmitting-end signal output unit1doutputs the radio signal to the antenna1ein synchronization with the transmitting-end synchronizing signal selected by the transmitting-end synchronizing signal selector1c.

The code output unit2ain the receiver2outputs a despreading code for despreading the radio signal transmitted from the transmitter1and received by the antenna2f.

The receiving-end synchronizing signal generator2bgenerates a plurality of receiving-end synchronizing signals the frequencies and phases of which are the same as those of the plurality of transmitting-end synchronizing signals generated by the transmitting-end synchronizing signal generator1bin the transmitter1.

The receiving-end synchronizing signal selector2cselects and outputs one of the plurality of receiving-end synchronizing signals outputted from the receiving-end synchronizing signal generator2bon the basis of the despreading code outputted from the code output unit2a.

The receiving-end signal output unit2doutputs a correlation-detected signal which is synchronized with the receiving-end synchronizing signal selected by the receiving-end synchronizing signal selector2cand with which the correlation of the radio signal is detected.

The correlator2edetects a correlation between the radio signal received by the antenna2fand the correlation-detected signal outputted from the receiving-end signal output unit2d.

The transmitting-end synchronizing signal generator1bin the transmitter1generates the plurality of transmitting-end synchronizing signals with different phases. The transmitting-end signal output unit1doutputs the radio signal in synchronization with the transmitting-end synchronizing signal selected on the basis of the code-spread data to be transmitted. The transmitting-end signal output unit1doutputs the radio signal in synchronization with the selected transmitting-end synchronizing signal. Therefore, radio signals with different phases corresponding to the code-spread data to be transmitted are outputted from the transmitting-end signal output unit1d.

The receiving-end synchronizing signal generator2bin the receiver2generates the plurality of receiving-end synchronizing signals which are the same as the plurality of transmitting-end synchronizing signals. The receiving-end signal output unit2doutputs the correlation-detected signal which is synchronized with the receiving-end synchronizing signal selected on the basis of the despreading code and with which the correlation of the radio signal is detected. Therefore, correlation-detected signals with different phases corresponding to the despreading code are outputted from the receiving-end signal output unit2d.

The correlator2edetects a correlation between the radio signal received by the antenna2fand the correlation-detected signal outputted from the receiving-end signal output unit2d. If the waveforms of the radio signal received by the antenna2fand the correlation-detected signal outputted from the receiving-end signal output unit2dmatch, then a great correlation value will be obtained. Output from the correlator2eis integrated over one symbol period and it is judged whether the result is one or zero. By doing so, received data is obtained.

As stated above, in the transmitter one of the plurality of transmitting-end synchronizing signals with different phases is selected on the basis of the code-spread data to be transmitted and the radio signal is transmitted in synchronization with the selected transmitting-end synchronizing signal. In the receiver one of the plurality of receiving-end synchronizing signals with different phases is selected on the basis of the despreading code and the radio signal is received in synchronization with the selected receiving-end synchronizing signal. Therefore, even if a data transfer rate is high, there is no need to increase the frequencies of a transmitting-end synchronizing signal and a receiving-end synchronizing signal. As a result, a synchronizing signal generation circuit can be realized easily and power consumption can be controlled.

A communication system according to a first embodiment of the present invention will now be described in detail with reference to the drawings. This communication system includes a transmitter and a receiver and the transmitter will be described first.

FIG. 2is a block diagram of the transmitter.

As shown inFIG. 2, the transmitter includes a code generator11, a code spreader12, a phase selector13, a waveform generator14, a BPF15, and an antenna16. For example, the transmitter performs UWB communication in which a carrier wave is not needed in the millimeter wave band.

The code generator11outputs a spreading code for code-spreading data to be transmitted.

The data to be transmitted and the spreading code outputted from the code generator11are inputted to the code spreader12. The code spreader12spreads the inputted data to be transmitted with the spreading code and outputs the code-spread data to be transmitted.

A plurality of clocks with different phases, being multiple phase clocks, and the code-spread data to be transmitted outputted from the code spreader12are inputted to the phase selector13. The phase selector13selects one of the multiple phase clocks inputted on the basis of the code-spread data to be transmitted and outputs it to the waveform generator14.

The waveform generator14outputs a single cycle pulse synchronized with the clock selected by the phase selector13. Single cycle pulses with different phases corresponding to the code-spread data to be transmitted are outputted from the waveform generator14, so information given by the data to be transmitted will be included in the phases of the single cycle pulses.

The BPF15allows only a permissible band of the single cycle pulse signal outputted from the waveform generator14to pass and outputs it to the antenna16.

A circuit which forms each block inFIG. 2will now be described. A circuit which forms the waveform generator14will be described first.

FIG. 3is a circuit diagram of a single cycle generator.

A single cycle generator shown inFIG. 3is located as the waveform generator14shown inFIG. 2and outputs a signal as a basis for modulating spread data to be transmitted.

As shown inFIG. 3, the single cycle generator includes transistors M1and M2, resistors R1and R2, a condenser C1, and inductors L1through L3.

A drain of the transistor M1is connected to one end of the inductor L1the other end of which is connected to a power supply Vcc. A drain of the transistor M2is connected to one end of the inductor L2the other end of which is connected to the power supply Vcc. The drains of the transistors M1and M2are connected via the resistor R1. Sources of the transistors M1and M2are connected to the inductor L3. The condenser C1and the resistor R2are connected in parallel. One end of each of the condenser C1and the resistor R2is connected to the inductor L3and the other end of each of the condenser C1and the resistor R2is connected to a ground.

By considering the inductors L1and L2as loads and using mutual inductance between them, the single cycle generator becomes differential. If a high frequency is needed, then a stub with a length equal to a fourth of the wavelength corresponding to the center frequency is used. One of the multiple phase clocks selected and outputted by the phase selector13is inputted to gates of the transistors M1and M2included in the single cycle generator. The single cycle generator outputs the clock input signals i+ and i− inputted to the gates of the transistors M1and M2from the drains of the transistors M1and M2as an output signals o− and o+, respectively, of a single cycle pulse (impulse). The frequency of the output signals o+ and o− depends on a series resonance circuit including the inductor L3and a parallel circuit made up of the condenser C1and the resistor R2.

FIG. 4shows the waveforms of input to and output from the single cycle generator.

The horizontal axis of a graph shown inFIG. 4indicates time in ns. The vertical axis of the graph indicates voltage in volts. Dotted lines shown inFIG. 4indicate the input signals i+ and i− inputted to the gates of the transistors M1and M2respectively. A solid line shown inFIG. 4indicates a waveform corresponding to the differential ((o+)−(o−)) between the output signals o+ and o− taken from the drains of the transistors M2and M1respectively. As shown inFIG. 4, the output signals o+ and o− of a single cycle pulse are outputted in synchronization with the clock input signals i+ and i−.

A circuit for outputting multiple phase clocks will now be described.

FIG. 5is a block diagram of a PLL.

As shown inFIG. 5, a phase locked loop (PLL) includes a voltage controlled oscillator (VCO)21, T flip-flops (TFFs)22and23, a phase detector (PD)24, a loop filter (LF)25, and a level shifter (LS)26. In addition, the PLL includes resistors R3and R4and condensers C2through C5. The PLL shown inFIG. 5outputs a signal having a frequency four times the frequency of a reference signal Fref.

Voltage outputted from the PLL (voltage outputted from the level shifter26) is inputted to the voltage controlled oscillator21and is used for controlling an oscillation frequency.

The TFFs22and23divide the frequency of a signal outputted from the VCO21. Each of the TFFs22and23divides the frequency of the signal inputted thereto in two. Accordingly, the frequency of the signal outputted from the TFF23is a fourth of the frequency of the signal inputted to the TFF22.

The reference signal Fref having a reference frequency and the signal outputted from the TFF23are inputted to the phase detector24. The phase detector24detects difference between the phase of the signal outputted from the TFF23and the phase of the reference signal Fref and outputs a pulse signal with a pulse width proportional to the phase difference.

The loop filter25blocks a high frequency band of the pulse signal outputted from the phase detector24and converts the phase difference outputted from the phase detector24into a voltage value. A lag-lead filter is formed by a circuit in which the resistor R3and the condenser C3connected in series and the condenser C2are connected in parallel and a circuit in which the resistor R4and the condenser C5connected in series and the condenser C4are connected in parallel between the input side and the output side of the loop filter25.

The level shifter26converts the voltage outputted from the loop filter25into an appropriate voltage level and outputs it to the voltage controlled oscillator21.

By the way, the scale of circuits which make up the frequency dividers (TFFs22and23) is large and high speed operation is required especially at the first stage. Therefore, a PLL which includes no frequency dividers and which directly compares the phases of a signal having a frequency equal to a fourth of a frequency generated by the voltage controlled oscillator21and a reference signal will now be described.

FIG. 6is a circuit diagram of a PLL including no frequency dividers.

A signal VCO+ outputted from a voltage controlled oscillator (VCO)27is inputted to drains of the transistors M9and M10via the condenser C8. A signal VCO− outputted from the voltage controlled oscillator (VCO)27is inputted to sources of the transistors M9and M10via the condenser C9. The drains of the transistors M9and M10are connected to one end of the resistor R9the other end of which is connected to a ground. The sources of the transistors M9and M10are connected to one end of the resistor R10the other end of which is connected to the ground. A reference signal Cref+ having a reference frequency is inputted to a gate of the transistor M9. A reference signal Cref− having the reference frequency is inputted to a gate of the transistor M10.

The transistors M9and M10, the resistors R9and R10, and the condensers C8and C9make up a phase detector (PD inFIG. 6). The phase detector detects difference in phase between the reference signals Cref+ and Cref− and the signals VCO+ and VCO− outputted from the voltage controlled oscillator27and outputs a pulse signal with a pulse width proportional to the phase difference.

A drain of the transistor M5is connected to one end of the resistor R5the other end of which is connected to a power supply Vcc. A drain of the transistor M6is connected to one end of the resistor R6the other end of which is connected to the power supply Vcc. A circuit in which the condenser C6and the resistor R7connected in series and the condenser C7are connected in parallel is inserted between the drains of the transistors M5and M6. Sources of the transistors M5and M6are connected to drains of the transistors M7and M8respectively. A gate of the transistor M7is connected to the drain of the transistor M8and a gate of the transistor M8is connected to the drain of the transistor M7. A source of the transistor M7is connected to the drains of the transistors M9and M10. A source of the transistor M8is connected to the sources of the transistors M9and M10. Bias voltage Vb is inputted to gates of the transistors M5and M6.

The transistors M5through M8, the resistors R5through R7, and the condensers C6and C7make up a loop filter (LF inFIG. 6). The loop filter blocks a high frequency band of the pulse signal outputted from the phase detector and converts the phase difference into a voltage value.

A drain of the transistor M3is connected to the power supply Vcc. A source of the transistor M3is connected to a drain of the transistor M11. A gate of the transistor M3is connected to the drain of the transistor M5included in the loop filter. A source of the transistor M11is connected to one end of the resistor R8the other end of which is connected to the ground. A gate of the transistor M11is connected to a gate and a drain of the transistor M12.

A drain of the transistor M4is connected to the power supply Vcc. A source of the transistor M4is connected to a drain of the transistor M12. A gate of the transistor M4is connected to the drain of the transistor M6included in the loop filter. A source of the transistor M12is connected to one end of the resistor R11the other end of which is connected to the ground.

The transistors M3, M4, M11and M12and the resistors R8and R11make up a level shifter (LS inFIG. 6). The level shifter converts the voltage outputted from the loop filter into an appropriate voltage level Vc and outputs it to the voltage controlled oscillator27.

The voltage controlled oscillator27controls an oscillation frequency on the basis of the voltage Vc outputted from the level shifter and outputs the signals VCO+ and VCO−.

The voltage controlled oscillator27may be a balanced voltage controlled oscillator or a multi-phase voltage controlled oscillator. A balanced voltage controlled oscillator will be described first.

FIG. 7is a circuit diagram of a balanced voltage controlled oscillator.

A drain of the transistor M13is connected to one end of the inductor L4the other end of which is connected to the power supply Vcc. A drain of the transistor M14is connected to one end of the inductor L5the other end of which is connected to the power supply Vcc. A source of the transistor M13is connected to one end of the resistor R12the other end of which is connected to the ground. A source of the transistor M14is connected to one end of the resistor R13the other end of which is connected to the ground. A gate of the transistor M13is connected to the drain of the transistor M14and a gate of the transistor M14is connected to the drain of the transistor M13.

The condenser C10is located between the drain and the source of the transistor M13and the condenser C11is located between the drain and the source of the transistor M14.

An anode of the diode D1is connected to the source of the transistor M13. An anode of the diode D2is connected to the source of the transistor M14. Cathodes of the diodes D1and D2are connected to each other and the voltage Vc outputted from the level shifter is inputted to these cathodes. The signals VCO+ and VCO− having a frequency which depends on the voltage Vc are outputted from the drains of the transistors M13and M14respectively. The diodes D1and D2are varactor diodes.

A multi-phase voltage controlled oscillator will now be described.

FIG. 8is a circuit diagram of a multi-phase voltage controlled oscillator.

As shown inFIG. 8, a multi-phase voltage controlled oscillator includes circuits28athrough28n. The circuits28athrough28nare connected to one another via diodes D3and D4and a resistor R15, diodes D5and D6and a resistor R16, diodes D7and D8and a resistor R17, and so on.

The circuit28aincludes a transistor M15, a resistor R14, an inductor L6, a condenser C12, and a current source I1. A drain of the transistor M15is connected to one end of the resistor R14the other end of which is connected to the power supply Vcc. A source of the transistor M15is connected to one end of the current source I1the other end of which is connected to the ground. A gate of the transistor M15is connected to a point where the inductor L6and the condenser C12are connected in series. The bias voltage Vb is inputted to a terminal of the inductor L6where the condenser C12is not connected. A terminal of the condenser C12where the inductor L6is not connected is connected to the source of the transistor M15. The structure (not shown) of the circuits28bthrough28nis the same as that of the circuit28a.

The voltage Vc outputted from the level shifter is inputted to the circuits28athrough28nvia the resistors R15, R16, R17, and so on and the diodes D3, D4, D5, D6, D7, D8, and soon. The circuits28athrough28noutput multiple phase clocks O0, O1, . . . , On−1, respectively, with different phases the frequency of which depends on the voltage Vc. The multiple phase clocks O0, O1, . . . , On−1 are used for synchronizing radio signals. Therefore, the frequency of the multiple phase clocks O0, O1, . . . , On−1 may be lower than the center frequency of the radio signals, but it must be higher than the frequency corresponding to the timing with which the radio signals are outputted.

By using the balanced voltage controlled oscillator shown inFIG. 7and the multi-phase voltage controlled oscillator shown inFIG. 8as the voltage controlled oscillator27shown inFIG. 6, multiple phase clocks can be generated. To be concrete, the frequency (62.5 MHz, for example) of TCXO output (signal outputted from a crystal oscillator) is multiplied four times by a PLL including the balanced voltage controlled oscillator to obtain an internal balanced reference frequency of 250 MHz. Furthermore, this frequency is multiplied four times by a PLL including the multi-phase voltage controlled oscillator to obtain multiple phase clocks at a frequency of 1 GHz.

The circuits shown inFIGS. 6 through 8can be formed on a unitary semiconductor substrate, so the area of a substrate and power consumption can be reduced.

Desired multiple phase clocks may be obtained by the PLL including the multi-phase voltage controlled oscillator without using the PLL including the balanced voltage controlled oscillator.

The phase selector13will now be described.

FIG. 9is a circuit diagram of the phase selector.

As shown inFIG. 9, the phase selector13includes a decoder (DEC)30a, a flip-flop circuit (FF)30b, and a selector30c. In addition, a PLL30ddescribed inFIGS. 6 through 8and a single cycle generator30edescribed inFIG. 3are shown inFIG. 9.

The code-spread data to be transmitted outputted from the code spreader12is inputted to the decoder30a. The decoder30aoutputs a signal for turning on/off switches in the selector30cto the flip-flop circuit30bon the basis of the code-spread data to be transmitted.

The PLL30doutputs multiple phase clocks to the selector30c. The PLL30dalso outputs two of the multiple phase clocks to the flip-flop circuit30b.

The flip-flop circuit30binputs the signal outputted from the decoder30awhen one of the two multiple phase clocks is inputted. The flip-flop circuit30bsettles the input of the signal outputted from the decoder30awhen the other of the two multiple phase clocks is inputted. The flip-flop circuit30bcan input or output the signal reliably with timing given by the multiple phase clocks with different phases.

The selector30cincludes a plurality of switches. The selector30cturns on/off these switches in response to the signal outputted from the flip-flop circuit30band outputs one of the multiple phase clocks outputted from the PLL30dto the single cycle generator30e.

As described above, in the phase selector one of the multiple phase clocks outputted from the PLL30dis selected on the basis of the code-spread data to be transmitted and is outputted to the single cycle generator30e. A single cycle pulse synchronized with the selected multiple phase clock is outputted from the single cycle generator30e. The single cycle pulse is outputted to the BPF15shown inFIG. 2and is transmitted to the receiver via the antenna16.

A convolver will now be described.

FIG. 10shows the structure of a convolver.

As shown inFIG. 10, a convolver includes a data bus31, decoders32aand32b, memories (first-in first-out (FIFO) memories)33aand33b, digital-analog converters (DACs)34aand34b, conductive sections35aand35b, and an interdigital transducer (IDT)36. An integration circuit made up of an amplifier37, condensers C13and C14, and switches SW1and SW2is connected to the output side of the conductive sections35aand35b.

A first signal is outputted to the data bus31and an address is outputted to the decoders32aand32b. When the decoders32aand32bare selected by the address, the decoders32aand32boutput the first signal outputted to the data bus31to the memories33aand33brespectively. The memories33aand33bhold the first signal outputted from the decoders32aand32brespectively and output it to the DACs34aand34brespectively. The DACs34aand34bconvert a voltage value in each bit included in the first signal outputted from the memories33aand33brespectively into an analog value and output it to the conductive sections35aand35brespectively.

A plurality of strain resistance elements (strain resistance stripes) are formed in the conductive sections35aand35band voltage outputted from the DACs34aand34bis inputted to these strain resistance elements.

A second signal is inputted to the IDT36. The second signal inputted to the IDT36propagates through the conductive sections35aand35bperpendicularly to the strain resistance stripes as a surface acoustic wave. As the distance from the IDT36increases, the surface acoustic wave will attenuate. Accordingly, a digital or analog correction can be made to a voltage value in each bit included in the first signal in the DACs34aand34bso that as the distance on the conductive sections35aand35bfrom the IDT36increases, the voltage value will become greater.

The conductive section35ais located on one side of the IDT36and the conductive section35bis located on the other side of the IDT36. The DAC34a, the memory33a, and the decoder32aare formed on the conductive section35a. The DAC34b, the memory33b, and the decoder32bare formed on the conductive section35b. If the second signal inputted to the IDT36includes a positive-phase-sequence component and a negative-phase-sequence component, then surface acoustic waves corresponding to these components will propagate through the different conductive sections. For example, a surface acoustic wave corresponding to the positive-phase-sequence component propagates through the conductive section35aand a surface acoustic wave corresponding to the negative-phase-sequence component propagates through the conductive section35b.

The integration circuit made up of the amplifier37, the condensers C13and C14, and the switches SW1and SW2integrates the sum of the products of the voltage applied to the strain resistance stripes on the conductive sections35aand35band the surface acoustic waves which propagate through the strain resistance stripes over a certain period of time and outputs a result obtained.

The convolver can be used for spreading data to be transmitted, despreading a received signal, code correlation, waveform correlation, or generating a waveform. In the transmitter shown inFIG. 2, for example, the convolver can be used as the code spreader by inputting the data to be transmitted and the spreading code thereto as the first and second signals respectively. In this case, one of the two signals must be converted into an analog signal and be outputted to the IDT36. In addition, as will be described later, the convolver can be used as, for example, a pulse correlator in the receiver.

In general, a convolver using a surface acoustic wave or a compression wave near a surface functions in the following way. There are two signal input terminals. The sum of the product of each of many delayed signals obtained by passing one signal through a delay line using mechanical vibration and the other signal is outputted. One method for outputting this sum is to generate waves which correspond to the first and second signals and which propagate in opposite directions at both ends of the delay line and to obtain the sum of the products from one electrode by using the nonlinearity of the delay line itself. Another method is to convert each delayed wave into an electrical signal with many IDT electrodes, to obtain product signals with a nonlinear element, such as a diode, and to output the sum of them. With these methods, however, the signals attenuate significantly on the delay line.

Still another method is to provide only one input signal from one end of a delay line and to provide the other input signal as an electrical signal. Delayed signals converted into electrical signals with many IDT electrodes are obtained, the product of each delayed signal and the second signal (electrical signal) is found, and the sum of them is outputted.

In the convolver shown inFIG. 10, a wave corresponding to the first signal occurs in the conductive sections35aand35b. The second signal is provided to one end of each of the many strain resistance stripes located perpendicularly to the direction in which the wave propagates, and the sum of signals obtained at the other end of each strain resistance elements is outputted.

The conductive sections35aand35bbeing conductive regions are formed on a semiconductor of silicon, GaAs, or InP by ion implantation (I.I.) or selective epitaxial growth so that they will form stripes or thin lines. If silicon is used, then they should be formed on a conductor substrate of an opposite type or a well. If elements are separated by field oxides (FOXes) by the use of the local oxidation of silicon (LOCOS) technique generally used, then surface wave loss and scattering will occur. If this convolver is formed together with a CMOS circuit, element separation should be performed by, for example, I.I. without using FOXes to narrow a conductor pattern separation. The IDT is fabricated by forming a ferroelectric on the surface of the semiconductor or in a recess portion formed in the semiconductor by etching, and by forming a metal film electrode so that it will face the surface of the ferroelectric.

One of the following structures for preventing reflection can be located outside the area where the conductive regions are arranged like stripes. The IDT is grounded. A structure for reflecting a wave to an area where it will have no influence is formed on the semiconductor (by forming an oblique FOX pattern or forming a drop in surface level on the substrate) A plurality of areas which differ from the conductive regions in the type of a dopant and the propagation speed of an elastic wave are formed.

If a compound semiconductor is used, a semi-insulating substrate is used. In this case, ZnO, LiNbO3, KNbO3, or the like is formed near the conductive regions (semiconductor stripes) formed like stripes or thin lines and the film pattern IDT in the shape of combs opposite to each other is formed on it by using, for example, aluminum. If the delay line and the strain resistance stripes are made of a compound semiconductor having a considerable piezoelectric effect, more particularly of GaAs or GaN, there is no need to form a ferroelectric layer separately. The metal film pattern IDT should be formed directly on the compound semiconductor. The second signal is inputted to one end of each conductive region perpendicular to the direction in which the surface acoustic wave (SAW) travels, and the product of the first signal and the second signal is outputted from the other end of each conductive region.

The surface acoustic wave propagates across the semiconductor stripes. The electric conductivity of the semiconductor stripes changes due to a piezo resistance effect. For example, the convolution of a filter factor inputted from one end of each semiconductor stripe and the surface acoustic wave is outputted from the other end of each semiconductor stripe. The attenuation of the surface acoustic wave can be corrected by the filter factor.

InFIG. 10, the second signal is distributed and is given to the conductive sections35aand35bas voltage. To be concrete, a transversal filter factor and the spreading code or the despreading code are written from the data bus31and the decoders32aand32bto the 8-bit FIFO memories33aand33b. The transversal filter factor and the spreading code or the despreading code are converted into analog voltages by the R2R type DACs34aand34blocated in the conductive sections35aand35brespectively and are provided to the conductive sections35aand35b.

The first signal is converted into the surface wave by the IDT36and propagates to both sides of the IDT36. If the intervals between the teeth of the metal film pattern of the IDT36are equal to half of a wavelength corresponding to the center frequency of the first signal and the number of the teeth is an even number, the phases of the surface wave which propagates to both sides of the IDT36are opposite to each other at two points at the same distance from the IDT36. By locating the conductive regions on both sides of the IDT36which converts the first signal into the surface wave, providing the second signal complementarily to both sides of the IDT36, and finding out the difference between signals outputted from both sides of the IDT36, convolution output can be obtained. By applying this, the surface wave which propagates to both sides of the IDT36can be used effectively. If the starting points of the conductive sections35aand35bare shifted to the outside by half of the wavelength and the intervals between the semiconductor stripes are equal to the wavelength, then a Nyquist sampling process can be performed. In this case, a margin for fabrication precision is left.

By providing the transversal filter factor as the first signal and providing a single pulse as the second signal with desired timing, a multiplex waveform can be generated. In addition, a waveform having any power spectrum density can be generated in a frequency domain.

With a conventional SAW delay line, a first signal is converted into a surface wave by an IDT, this surface wave is converted into an electrical signal by another IDT (receiving-end IDT) located at another place, and an operation is performed by using the electrical signal and a second signal. A fourth of the wavelength of the surface wave is suitable for intervals d between the teeth of the receiving-end IDT. The intervals between the semiconductor stripes (strain resistance stripes) shown inFIG. 10should be wider than or equal to about a fourth of the wavelength of the surface wave. By connecting n convolver fabricated by shifting the starting position of the semiconductor stripes by, for example, d/n (n is an integer) in parallel, a factor can be set more finely (nth order oversampling). With a conventional SAW element using a ferroelectric, the propagation speed of a surface wave is about 3,000 to 6,000 m/s and the upper limits of signal frequency components which can be handled depend on precision in the fabrication of an IDT. If d=0.5 μm, then

where v is the propagation speed of the surface wave and λ is the wavelength of the surface wave.

Operation performed inFIG. 2will now be described.

The code spreader12shown inFIG. 2spreads the data to be transmitted with the spreading code generated by the code generator11.

The phase selector13selects one of the multiple phase clocks generated by the PLL shown inFIGS. 6 through 8on the basis of the code-spread data to be transmitted and outputs it to the waveform generator14.

The waveform generator14converts the selected multiple phase clock into a single cycle pulse signal by the single cycle generator shown inFIG. 3. The BPF15takes only the permissible band from the single cycle pulse outputted from the single cycle generator. The signal to be transmitted outputted from the BPF15is sent to the receiver by the antenna16.

Descriptions will now be given by using a timing chart.

FIG. 11shows a timing chart for the transmitter.

Data to be transmitted shown inFIG. 11is inputted to the code spreader12shown inFIG. 2. The numbers “1,” “0,” “1,” “1,” and so on indicated on the data to be transmitted are bit values included in the data to be transmitted. A spreading code shown inFIG. 11is outputted from the code generator11. The numbers “1,” “0,” “3,” “2,” and so on indicated on the spreading code are decimal numbers included in the spreading code. In this example, two bits are used as the spreading code. Clocks phi0, phi1, . . . , and phi15are multiple phase clocks inputted to the phase selector13shown inFIG. 2. In this example, it is assumed that the phase selector13selects one of the clocks phi0through phi3on the basis of the spread data to be transmitted and that the phase selector13outputs it. The clocks phi0through phi3are used for synchronizing an output waveform (signal to be transmitted), so the frequency of the clocks phi0through phi3may be lower than the center frequency of the output waveform. For the sake of simplicity it is assumed that the frequency of the clocks phi0through phi3is equal to the timing with which a radio signal is outputted, that is to say, to a chip frequency. An output waveform shown inFIG. 11indicates the waveform of a radio signal outputted from the waveform generator14shown inFIG. 2.

The data to be transmitted is spread by the code spreader12with the 2-bit spreading code. As shown inFIG. 11, the phase selector13selects one of the clocks phi0through phi3with different phases on the basis of the code-spread data to be transmitted and outputs it to the waveform generator14. The waveform generator14converts the selected clock into a single cycle pulse signal as shown by the output waveform inFIG. 11by the single cycle generator shown inFIG. 3and outputs it. The single cycle pulse signal is outputted in synchronization with one of the clocks phi0through phi3, so the phase of the single cycle pulse signal outputted depends on a selected clock.

The single cycle pulse signal outputted from the single cycle generator is outputted to the BPF15and is sent from the antenna16to the receiver.

The high-order spreading code except the first two bits is used as a data sequence.

A receiver will now be described.

FIG. 12is a block diagram of a receiver.

As shown inFIG. 12, a receiver includes an antenna41, a BPF42, a code generator43, a code spreader44, a phase selector45, a waveform generator46, a pulse correlator47, a pulse train integrator48, and a comparator49. The receiver performs, for example, UWB communication in which a carrier wave is not needed with the transmitter shown inFIG. 2in the milliwave band.

The antenna41receives a radio signal transmitted from the transmitter. The BPF42takes only a required band from the radio signal received by the antenna41.

The code generator43generates a despreading code for despreading the received signal (radio signal received by the antenna41).

The code spreader44expand-spreads the despreading code outputted from the code generator43and outputs it to the waveform generator46.

A plurality of clocks with different phases, being multiple phase clocks, are inputted to the phase selector45. The frequencies and phases of these multiple phase clocks are the same as those of the multiple phase clocks generated in the transmitter. The phase selector45selects one of the multiple phase clocks inputted on the basis of the despreading code outputted from the code spreader44and outputs it.

The clock selected by the phase selector45is inputted to the waveform generator46. The waveform generator46outputs the despreading code as a single cycle pulse signal in synchronization with the clock selected by the phase selector45.

The pulse correlator47outputs a correlation value between the received signal outputted from the BPF42and the single cycle pulse outputted from the waveform generator46. When the waveform (phase) of the received signal and the waveform (phase) of the single cycle pulse match, the greatest correlation value will be obtained.

The pulse train integrator48integrates correlation values for the same received signal repeatedly transmitted which are obtained at the same timing in, for example, slots. As a result, a correlation value at the timing will become greater accumulatively in one symbol period.

The comparator49outputs the received signal every symbol period when the correlation value integrated by the pulse train integrator48reaches a peak.

A circuit which forms each block inFIG. 12will now be described.

The multiple phase clocks inputted to the phase selector45are generated by a PLL which is the same as that shown inFIGS. 6 through 8. The phase selector45includes the circuit shown inFIG. 9. InFIG. 9, the despreading code outputted from the code spreader44is inputted to the decoder30a.

The waveform generator46includes the single cycle generator shown inFIG. 3. The clock outputted from the phase selector45is inputted to the single cycle generator as the input signals i+ and i−. The single cycle generator outputs output signals o+ and o− each having the waveform of a single cycle pulse. This is the same withFIG. 4.

The pulse correlator47includes, for example, the convolver shown inFIG. 10. In this case, however, the received signal outputted from the BPF42is converted into a digital signal and is outputted to the data bus31in the convolver. The single cycle pulse outputted from the waveform generator46is inputted to the IDT36. The correlation value between the received signal and the single cycle pulse is outputted from the integration circuit in the convolver.

Operation performed inFIG. 12will now be described.

The code spreader44shown inFIG. 12spreads the despreading code generated by the code generator43.

The phase selector45selects one of the multiple phase clocks generated by the PLL on the basis of the despreading code outputted from the code spreader44and outputs it to the waveform generator46.

The waveform generator46converts the selected clock into the single cycle pulse signal by the single cycle generator.

The pulse correlator47detects a correlation between the single cycle pulse outputted from the waveform generator46and the received signal received by the antenna41and outputted via the BPF42.

The pulse train integrator48integrates the correlation value. The comparator49checks the integrated correlation value outputted from the pulse train integrator48every symbol period and outputs it as received data.

The operation of the receiver will now be described with a timing chart.

FIG. 13shows a timing chart for the receiver.

A despreading code shown inFIG. 13is outputted from the code generator43shown inFIG. 12. The numbers “1,” “0,” “3,” “2,” and soon indicated on the despreading code are decimal numbers included in the despreading code. In this example, two bits are used as the despreading code. This is the same with the spreading code shown inFIG. 11. Clocks phi0, phi1, . . . , and phi15are multiple phase clocks inputted to the phase selector45shown inFIG. 12. In this example, it is assumed that the phase selector45selects and outputs the four clocks phi1through phi4in that order. An output waveform shown inFIG. 13indicates the waveform of a single cycle pulse outputted from the waveform generator46shown inFIG. 12. A received signal shown inFIG. 13is received by the antenna41. Correlation output shown inFIG. 13indicates a waveform obtained when the pulse correlator47shown inFIG. 12detects a correlation between the received signal and the output waveform. Received data shown inFIG. 13indicates received signal data demodulated when a correlation value between the received signal and the output waveform is great.

Conventionally, an increase in data transfer rate has led to an increase in the frequency of a signal for determining timing with which a radio signal is outputted. Accordingly, a high-frequency circuit is needed to generate a signal having such a high frequency. However, it is difficult to design or fabricate such a high-frequency circuit. Moreover, it is difficult to realize such a high-frequency circuit by using CMOS semiconductor devices. As a result, consumption of power is high. As described above, however, an increase in the frequency of the clocks phi0through phi3shown inFIG. 11can be prevented by transmitting and receiving a radio signal of a single cycle pulse in synchronization with multiple phase clocks with different phases. Therefore, the circuits can be realized easily by using CMOS semiconductor devices. In addition, the scale of the circuits can be reduced, resulting in lower power consumption.

A communication system according to a second embodiment of the present invention will now be described in detail with reference to the drawings. As shown inFIG. 4, in the first embodiment a selected multiple phase clock is converted into a single cycle pulse and is transmitted as a radio signal. In the second embodiment, a selected multiple phase clock is converted into a burst wave and is transmitted as a radio signal. Only the differences in circuit which forms each block between the first embodiment shown inFIGS. 2 and 12and the second embodiment will now be described.

FIG. 14is a circuit diagram of a balanced interrupted oscillator for outputting a burst wave.

The single cycle generator included in the waveform generator14shown inFIG. 2or the waveform generator46shown inFIG. 12is a balanced interrupted oscillator for outputting a burst wave. The balanced interrupted oscillator converts a selected multiple phase clock into a burst wave. As shown inFIG. 14, the balanced interrupted oscillator includes transistors M16through M19, condensers C15through C17, and inductors L7and L8.

A drain of the transistor M16is connected to one end of the inductor L7the other end of which is connected to a power supply Vcc. A source of the transistor M16is connected to a drain of the transistor M18. A gate of the transistor M16is connected to a drain of the transistor M17.

The drain of the transistor M17is connected to one end of the inductor L8the other end of which is connected to the power supply Vcc. A source of the transistor M17is connected to a drain of the transistor M19. A gate of the transistor M17is connected to the drain of the transistor M16.

The condenser C15is connected between the drain and source of the transistor M16. The condenser C16is connected between the drain and source of the transistor M17. The condenser C17is connected to the sources of the transistors M16and M17.

The sources of the transistors M18and M19are connected to a ground. Multiple phase clocks tg0and tg1are inputted to gates of the transistors M18and M19respectively. Burst waves bo+ and bo− are taken from the drains of the transistors M16and M17respectively.

The balanced interrupted oscillator shown inFIG. 14generates a wave train with a center frequency of fc and any length. This balanced interrupted oscillator can be used in cases where a short wave train is used in the sub-millimeter wave or millimeter wave band, or for multiband communication. If a higher frequency is needed, then a stub with a length equal to a fourth of the wavelength corresponding to the center frequency is used. Moreover, the balanced interrupted oscillator is balanced by connecting the inductors (or stubs) in the resonance sections in the two Colpitts oscillators. When the multiple phase clock tg0and tg1rises, the balanced interrupted oscillator begins to oscillate. When the multiple phase clock tg0and tg1falls, the balanced interrupted oscillator stops oscillating. The polarity of the burst waves bo+ and bo− depends on the order in which the multiple phase clocks tg0and tg1rise. An interval Δtg between the time when the multiple phase clock tg0rises and the time when the multiple phase clock tg1rises is given by
(2k+1)/2fc

where k is an integer greater than or equal to zero.

FIG. 15shows the waveforms of input to and output from the balanced interrupted oscillator.

The horizontal axis of a graph shown inFIG. 15indicates time in ns. The vertical axis of the graph indicates voltage in volts. A dotted line shown inFIG. 15indicates the multiple phase clock tg0inputted to the gate of the transistor M18shown inFIG. 14. A chain line shown inFIG. 15indicates the multiple phase clock tg1inputted to the gate of the transistor M19shown inFIG. 14. A solid line shown inFIG. 15indicates a waveform corresponding to the differential ((bo+)−(bo−)) between the burst waves bo+ and bo−.

As shown inFIG. 15, the burst waves are outputted in synchronization with the multiple phase clocks tg0and tg1. The polarity of the burst waves depends on the positional relation between the phases of the multiple phase clocks tg0and tg1inputted to the gates of the transistors M18and M19respectively. For example, if the phase of the multiple phase clock tg0precedes the phase of the multiple phase clock tg1inFIG. 15, then the burst wave falls at first. If the phase of the multiple phase clock tg1precedes the phase of the multiple phase clock tg0, then the burst wave rises at first.

FIG. 16is a circuit diagram of a PPM circuit.

The phase selector13shown inFIG. 2or the phase selector45shown inFIG. 12is a pulse position modulation (PPM) circuit. As shown inFIG. 16, a PPM circuit includes a decoder (DEC)51, a flip-flop circuit (FF)52, a 16-phase clock source53, and selectors54aand54b. The 16-phase clock source53can be realized by the PLL shown inFIGS. 6 through 8.

Code-spread data to be transmitted or a despreading code is inputted to the decoder51. The decoder51decodes the code inputted thereto and outputs the decoded code to the flip-flop circuit52.

The 16-phase clock source53outputs clocks Φ00through Φ03, Φ10through Φ13, Φ20through Φ23, and Φ30through Φ33with different phases. The five phase clocks Φ00through Φ03and Φ10of the sixteen phase clocks are outputted to the selectors54aand54b. The clocks Φ20and Φ23with different phases of the sixteen phase clocks are outputted to the flip-flop circuit52. The 16-phase clock source53outputs a clock at a frequency equal to, for example, a fourth of the center frequency fc of a radio signal. To be concrete, the 16-phase clock source53outputs a clock at a frequency of 6.375 GHz.

The flip-flop circuit52inputs the code outputted from the decoder51in response to the clock Φ20inputted and settles the input of the code outputted from the decoder51in response to the clock Φ33inputted. The flip-flop circuit52can input or output the code reliably with timing given by the multiple phase clocks with different phases.

Each of the selectors54aand54bincludes a plurality of switches. The selectors54aand54bturn on/off the switches in accordance with the decoded code outputted from the flip-flop circuit52and outputs a clock outputted from the 16-phase clock source53as the multiple phase clocks tg0and tg1.

There are four kinds of phase patterns. In addition, the phase of the multiple phase clock tg0may precede the phase of the multiple phase clock tg1, and vice versa. That is to say, the PPM circuit shown inFIG. 16can output eight kinds of multiple phase clocks tg0and tg1. For example, the switch in the selector54bcorresponding to the clock Φ00is turned on and the switch in the selector54acorresponding to the clock Φ01is turned on. Then the switch in the selector54bcorresponding to the clock Φ01is turned on and the switch in the selector54acorresponding to the clock Φ02is turned on. As a result, multiple phase clocks tg0and tg1with different phases will be outputted. On the other hand, by turning on the switch in the selector54acorresponding to the clock Φ00and turning on the switch in the selector54bcorresponding to the clock Φ01, the positional relation between the phases of multiple phase clocks tg0and tg1outputted is reversed.

Multiple phase clocks outputted from the PPM circuit are inputted to the balanced interrupted oscillator shown inFIG. 14and are converted into a burst wave. In a transmitter, the burst wave is outputted to a BPF and is transmitted from an antenna as a radio signal. This is the same with the first embodiment. In a receiver, the burst wave is outputted to a pulse correlator where a correlation between the burst wave and the signal received by an antenna is detected.

As described above, the communication system according to the second embodiment of the present invention is also applicable to multiband communication by transmitting and receiving a radio signal of a burst wave in synchronization with multiple phase clocks with different phases. Moreover, a high-frequency circuit is unnecessary. Therefore, the circuits can be realized by using CMOS semiconductor devices and consumption of power can be reduced.

An example of application of the communication system according to the first or second embodiment of the present invention will now be described.

FIG. 17shows an example of communication in an enclosure.

A plurality of CPU boards62a,62b,62c, etc. on each of which a CPU is mounted are housed in an enclosure61shown inFIG. 17. Transmitting modules63a,63b,63c, etc. and receiving modules64a,64b,64c, etc. for performing radio communication are mounted on the CPU boards62a,62b,62c, etc. respectively. A filter window65which a radio wave passes through is placed in the enclosure61. A mirror66for reflecting a radio wave is located in the enclosure61. In addition, windows67for inputting radio waves from other enclosures or outputting radio waves to the other enclosures are placed in the top, bottom, left side, and right side of the enclosure61. InFIG. 17, a notebook computer71is shown. The structure of the other enclosures shown inFIG. 17is the same as that of the enclosure61.

Each enclosure houses many CPU boards (blade computers) A transmitting module and a receiving module for performing radio communication are mounted at one end of each CPU board housed in each enclosure. High-speed digital circuits including a CPU will produce RF noise. Many of them are made up of CMOS LSIs. This RF noise includes noise at frequencies higher than or equal to the maximum operating frequencies (ft) of high power transistors, but the amount of energy radiated by this noise is small. The upper limit of communication capacity is given by Shannon's theorem, that is to say, by
R=Blog2(1−SNR)

where B is a bandwidth used and SNR is an S/N ratio at communication time. By performing communication at higher frequencies where noise is low, greater SNR will be obtained without changing power. This enables high-speed large-capacity communication.

The operating speed of CPUs and advanced CMOSes used in their peripheral circuits has increased and ft has already reached 200 GHz. However, usually transistors the maximum operating frequencies of which are lower than about 50 GHz are used in high power off-chip drivers in order to ensure high breakdown voltages and electrostatic breakdown strength. Accordingly, a transmitter-receiver RF module in which In-P high electron mobility transistors (In-PHEMTs) are formed is used and these transistors are made to operate at frequencies in the 60 GHz band. By doing so, communication can be performed at rates of several tens to several hundreds of gigabits per second. With the progress of CMOS technologies, there is a possibility that the 80 GHz band or a band higher than or equal to 100 GHz must be used in the future. By using In-PHEMTs, however, these bands can be used even at present. In the first and second embodiments of the present invention, communication is performed in synchronization with the timing of multiple phase clocks. Therefore, on the one hand, low-speed elements, such as CMOS semiconductor devices, are used for forming a circuit for generating these multiple phase clocks in order to raise an integration level. On the other hand, the use of In-PHEMTs the manufacturing costs of which are high is minimized. By doing so, a high-frequency band can be used.

Another example of application of the communication system according to the first or second embodiment of the present invention will now be described.

FIG. 18shows another example of communication in an enclosure.

As shown inFIG. 18, a plurality of CPU boards82aon each of which a CPU is mounted and a plurality of CPU boards82bon each of which a CPU is mounted are mounted in two rows on a back plane81. High-speed parallel bus boards83aand83bare fixed to the sides of the CPU boards82aand82brespectively. Three transmitter-receiver modules84afor performing radio communication are mounted on each CPU board82a. Similarly, three transmitter-receiver modules84bfor performing radio communication are mounted on each CPU board82b. The upper transmitter-receiver modules84amounted on the CPU boards82aare connected to one another by a dielectric waveguide85aa. The middle transmitter-receiver modules84amounted on the CPU boards82aare connected to one another by a dielectric waveguide85ab. The upper transmitter-receiver modules84bmounted on the CPU boards82bare connected to one another by a dielectric waveguide85ba. The middle transmitter-receiver modules84bmounted on the CPU boards82bare connected to one another by a dielectric waveguide85bb. Transmitter-receiver modules84cfor performing radio communication are mounted on the back plane81. The CPU boards82aand82bare connected by serial communication cables86aand86brespectively.

The plurality of CPU boards82aand the plurality of CPU boards82bare mounted on the back plane81below them. An external sensor, an actuator, a power supply, and the like are connected to the back plane81. The CPU boards82aare connected to one another by the high-speed parallel bus board83aand the CPU boards82bare connected to one another by the high-speed parallel bus board83b. In addition, each of the CPU boards82aare connected to near CPU boards82aby serial communication cables86a, being high-speed Ethernet (registered trademark) or the like, and each of the CPU boards82bare connected to near CPU boards82bby serial communication cables86b. These are conventional data communication means in which the sending end uniquely determines a destination to perform communication (a multicast and broadcast can also be performed by specifying addresses arranged).

Each of the transmitter-receiver modules84aand84bincludes an antenna. Millimeter wave radio communication is performed with the transmitter-receiver modules84aand84bamong the CPU boards82aand82band the back plane81. As a result, a more flexible communication network is obtained. InFIG. 18, three transmitter-receiver modules84aare mounted on each of the CPU boards82aand three transmitter-receiver modules84bare mounted on each of the CPU boards82b. The upper transmitter-receiver modules84amounted on the CPU boards82aare connected to one another by the dielectric waveguide85aa. The middle transmitter-receiver modules84amounted on the CPU boards82aare connected to one another by the dielectric waveguide85ab. The upper transmitter-receiver modules84bmounted on the CPU boards82bare connected to one another by the dielectric waveguide85ba. The middle transmitter-receiver modules84bmounted on the CPU boards82bare connected to one another by the dielectric waveguide85bb. In this example, an antenna included in each of the upper and middle transmitter-receiver modules84aand84bis smaller than an antenna included in each of the lower transmitter-receiver modules84aand84band is inserted into the waveguide so that it will reach the center of the waveguide. Reflection prevention structures are fitted on both ends of each waveguide and a microwave absorber is fitted on each reflection prevention structure. The side of each waveguide is covered with a microwave absorber to prevent signals from the lower transmitter-receiver modules84aand84bfrom entering it.

As described above, the communication system according to the first or second embodiment of the present invention is applicable to remote controllers for electronics, short-haul digital communication systems for wireless LANs, and the like.

By making the transmitter and the receiver described in the first or second embodiment of the present invention operate on the basis of the same clock, overhead necessary for chip synchronization in each communication session can be saved.

FIG. 19is a circuit block diagram of a communication apparatus.

As shown inFIG. 19, a communication apparatus comprises a transmitter90a, a receiver90b, and a TCXO90c. The transmitter90aincludes a microcontroller unit (MCU)90aa, a synchronization circuit90ab, a phase detector-loop filter (PD-LF)90ac, a polyphase VCO (PPVCO)90ad, an SW90ae, a QO90af, and an antenna90ag. The receiver90bincludes an antenna90ba, a BPF90bb, a low noise amplifier (LNA)90bc, a mixer90bd, an MCU90be, a synchronization circuit90bf, a PD-LF90bg, a PPVCO90bh, an SW90bi, a QO90bj, an integrator90bk, and an A/D90bl.

The MCU90aain the transmitter90acontains a memory in which a spreading code is stored. In synchronization with a chip rate clock cc outputted from the PPVCO90ad, the MCU90aacode-spreads data Tx to be transmitted inputted thereto and outputs the code-spread data to the synchronization circuit90abby bits corresponding to each symbol.

In synchronization with one of multiple phase clocks outputted from the PPVCO90adwhich gives the maximum timing margin, the synchronization circuit90abaccepts the code-spread data Tx to be transmitted outputted from the MCU90aaand outputs it to the SW90ae.

The PD-LF90acoutputs the difference in phase between a reference clock (at a frequency of several to 50 megahertz) outputted from the TCXO90c, being a crystal oscillator, and a clock outputted from the SW90aeas a voltage value. The PPVCO90adoutputs the multiple phase clocks obtained by multiplying the frequency of the reference clock outputted from the TCXO90c. In this case, the PPVCO90adexercises control according to the voltage value outputted from the PD-LF90acso that the frequencies of the multiple phase clocks outputted will be constant. The frequency of the multiple phase clocks is the chip rate clock cc.

On the basis of the code-spread data Tx to be transmitted outputted from the synchronization circuit90ab, the SW90aeselects one of the multiple phase clocks outputted from the PPVCO90adand performs a PPM and a BPSK modulation.

The QO90afconverts the selected multiple phase clock outputted from the SW90aeinto a single cycle pulse like that shown inFIG. 4or a burst wave like that shown inFIG. 15.

The antenna90agtransmits the single cycle pulse or the burst wave outputted from the QO90afto a receiving-end communication apparatus as a radio signal.

The antenna90bain the receiver90breceives the radio signal from the transmitting-end communication apparatus. The antenna90baoutputs the radio signal (received signal) it received to the BPF90bb.

The BPF90bbtakes only a permissible band from the received signal and outputs it to the LNA90bc. The LNA90bcamplifies the received signal outputted from the BPF90bband outputs it to the mixer90bd.

The MCU90becontains a memory in which a despreading code for despreading the received signal is stored. The MCU90beoutputs the despreading code to the synchronization circuit90bfin synchronization with a chip rate clock cc outputted from the PPVCO90bh.

In synchronization with one of multiple phase clocks outputted from the PPVCO90bhwhich gives the maximum timing margin, the synchronization circuit90bfaccepts the despreading code outputted from the MCU90beand outputs it to the SW90bi.

The PD-LF90bgoutputs the difference in phase between a reference clock outputted from the TCXO90c, being a crystal oscillator, and a clock outputted from the SW90bias a voltage value. This is the same with the PD-LF90acin the transmitter90a. The PPVCO90bhoutputs the multiple phase clocks obtained by multiplying the frequency of the reference clock outputted from the TCXO90c. In this case, the PPVCO90bhexercises control according to the voltage value outputted from the PD-LF90bgso that the frequencies of the multiple phase clocks outputted will be constant. The frequency of the multiple phase clocks is generated on the basis of the reference clock outputted from the TCXO90c, so the frequency of the chip rate clock cc in the receiver90bis the same as that of the chip rate clock cc in the transmitter90a.

On the basis of the despreading code outputted from the synchronization circuit90bf, the SW90biselects one of the multiple phase clocks outputted from the PPVCO90bhand performs a PPM and a BPSK modulation.

The QO90bjconverts the selected multiple phase clock outputted from the SW90biinto a single cycle pulse or a burst wave.

The mixer90bddetects a correlation between the received signal outputted from the LNA90bcand the single cycle pulse or the burst wave outputted from the QO90bjand outputs it to the integrator90bk. Strictly speaking, carrier synchronization at the center frequency of the burst wave is required between the transmitting end and the receiving end. To avoid this, the following method, for example, can be used. Burst waves which orthogonally cut each other are generated by a delay unit or the like on the receiver90bside and are handled by the mixer90bdused as a correlator.

The integrator90bkobtains received data by performing integration over a symbol period and outputs it to the A/D90bl. The A/D90blperforms digital conversion on the received data and outputs the digital-converted received data to the MCU90be. The MCU90beoutputs the digital-converted received data as received data Rx. The MCU90begives the integrator90bkinstructions to perform integration over the symbol period.

The operation of the communication apparatus shown inFIG. 19will now be described.

The PPVCO90adin the transmitter90amultiplies the frequency of the reference clock outputted from the TCXO90cshared by the PPVCO90bhin the receiver90band oscillates at the frequency of the chip rate clock cc.

The data Tx to be transmitted is temporarily stored in a register in the MCU90aain synchronization with the chip rate clock cc. The MCU90aaspreads the data Tx to be transmitted with the spreading code stored in advance in the memory contained in the MCU90aaand outputs the code-spread data to the synchronization circuit90abby bits corresponding to each symbol. In synchronization with one of the multiple phase clocks outputted from the PPVCO90adwhich gives the maximum timing margin, the synchronization circuit90abaccepts the code-spread data Tx to be transmitted outputted from the MCU90aa.

On the basis of the code-spread data Tx to be transmitted synchronized and outputted from the synchronization circuit90ab, the SW90aeselects one of the multiple phase clocks outputted from the PPVCO90ad. The QO90afconverts the selected multiple phase clock into a single cycle pulse or a burst wave and outputs it to the antenna90ag. As a result, a PP-modulated, BPSK-modulated radio signal is outputted from the antenna90ag.

The BPF90bbin the receiver90btakes a permissible band from the received signal received by the antenna90ba. The LNA90bcamplifies the received signal and then the mixer90bdperforms detection on the received signal.

The MCU90beoutputs the despreading code to the synchronization circuit90bfby bits corresponding to each symbol. In synchronization with one of the multiple phase clocks outputted from the PPVCO90bhwhich gives the maximum timing margin, the synchronization circuit90bfaccepts the despreading code outputted from the MCU90be.

The SW90biselects one of the multiple phase clocks outputted from the PPVCO90bhon the basis of the despreading code outputted from the synchronization circuit90bf. The QO90bjconverts the selected multiple phase clock into a single cycle pulse or a burst wave and outputs it to the mixer90bd.

The integrator90bkintegrates a signal outputted from the mixer90bdover a symbol period and outputs an obtained signal to the A/D90bl. The A/D90blperforms digital conversion on the signal outputted from the integrator90bk. The MCU90beoutputs the digital-converted signal as the received data Rx.

As described above, by synchronizing the transmitter90aand the receiver90bby one TCXO90c, overhead necessary for chip synchronization in each communication session can be saved. A delay for output from the TCXO90con a wiring and a propagation delay on an air channel between the transmitter90aand the receiver90bare calibrated at idle time or at the time of starting the system.

The above method is also applicable to the transmitting modules63a,63b,63c, and so on and the receiving modules64a,64b,64c, and so on shown inFIG. 17. By making all of these modules operate on the basis of the same clock, overhead necessary for chip synchronization in each communication session can be saved. In addition, the above method is applicable to the transmitter-receiver modules84aand84bshown inFIG. 18. By making all of these modules operate on the basis of the same clock, overhead necessary for chip synchronization in each communication session can be saved.

A communication system according to a third embodiment of the present invention will now be described in detail with reference to the drawings. This communication system is applicable to probing apparatus, obstacle detection radars, and the like.

To reduce the amount of energy radiated and perform probing or communication in a wide area, a narrow beam (radio signal) should be used for scanning. Accordingly, mechanical scanning (rotating an antenna, for example) is performed, but this is inferior to a fixed antenna in durability, earthquake resistance, size, and power consumption.

The following phase distributor is used for performing electronic scanning. This phase distributor includes n common-gate type Colpitts oscillators the gate electrodes of which are connected to one another via resistors, and outputs n sine waves obtained by dividing the difference in phase between sine waves inputted to both ends into (n+1) parts.

FIG. 20is a circuit diagram of a phase distributor.

A drain of the transistor M16is connected to one end of the inductor L9the other end of which is connected to a power supply Vcc. A source of the transistor M16is connected to one end of the resistor R17the other end of which is connected to a ground. The condenser C18is connected between the drain and source of the transistor M16. The source of the transistor M16is connected to one end of the condenser C19the other end of which is connected to the ground. A gate of the transistor M16is connected to the resistors R15and R16. A sine-wave signal is inputted to the resistor16. Bias voltage Vb is inputted to the resistor R16.

The transistor M16, the resistors R16and R17, the condensers C18and C19, and the inductor L9make up a Colpitts oscillator. Similarly, the transistor M17, the resistors R19and R20, the condensers C20and C21, and the inductor L10make up a Colpitts oscillator. Furthermore, the transistor M18, the resistors R22and R23, the condensers C22and C23, and the inductor L11make up a Colpitts oscillator. The transistors in these Colpitts oscillators are connected to one another via the resistors R18and R21. In addition, Colpitts oscillators each having the same structure are connected. That is to say, a Colpitts oscillator made up of the transistor M19, the resistors R25and R26, the condensers C24and C25, and the inductor L12and a Colpitts oscillator made up of the transistor M20, the resistors R28and R29, the condensers C26and C27, and the inductor L13are connected to the above Colpitts oscillators via the resistors R24and R27. The resistors R15and R30are connected to the gates of the transistors M16and M20respectively.

When the sine wave Pr1=Aei(Φi+ωct)is inputted to the resistor R15connected to the gate of the transistor M16at one end and the sine wave Pr2=Aei(Φi+θ+ωct)is inputted to the resistor R30connected to the gate of the transistor M20at the other end, phase-divided signals Out1, Out2, Out3, . . . , Out(n−1), and Outn generated by dividing the difference in phase between these sine waves are outputted from the sources of the transistors in the Colpitts oscillators. The phase-divided signal Outk outputted from the source of the kth transistor is given by
Outk=Bei(Φo+kθ/(n+1)+ωct)

where A and B are amplitude, Φi, Φo, and θ are phase angles, ωc is angular velocity, t is time, k is a constant, and n is a positive number.

With the phase distributor shown inFIG. 20, the difference between the oscillation frequency of each Colpitts oscillator and the frequencies of the sine waves inputted is within a range of about 2 to 5%. By comparing the phases of signals outputted from adjacent Colpitts oscillators and providing negative feedback of the difference to each Colpitts oscillator, input with a wider frequency range can be handled regardless of product variations and a change in operating conditions (this can be realized easily by applying the above method to the voltage controlled oscillator27included in the PLL shown inFIG. 6). A method for combining oscillation circuits for the same purpose is also presented in Brian K. Meadows et al.,Nonlinear Antenna Technology, Proceedings of The IEEE, Vol. 90, No. 5, May 2002.

An antenna for scanning beams will now be described.

FIG. 21is a sectional view of an antenna for scanning beams by controlling delay time.

A section of an antenna is shown inFIG. 21. InFIG. 21, two beams radiated from an antenna surface at an interval of a distance d are shown.

It is assumed that a radio signal is transmitted from a plurality of antennas and that transmission time is staggered by
−ΔT=dsin(θ)/c

where θ is the angle between the normal to the antenna surface and the beams, and c is the velocity of light. The wave front of the beams is indicated by a chain line inFIG. 21. As a result, the beams can be scanned. By generating receiving template signals which differ from one another in timing in a receiver, scanning can be performed in the direction of receiving. Since a wide band is used, the distance d can be set comparatively freely. In addition, even if the number of antenna elements is small, the diameter of an aperture can be made large.

A transmitter and receiver for scanning beams will now be described.

FIG. 22shows the rough structure of a transmitter for deflecting a directional beam.

Arbitrary waveforms are given by convolvers91a,91b, . . . , and91non the basis of a single cycle pulse generated with timing corresponding to a deflection direction and are transmitted via antennas92a,92b, . . . , and92n. If the convolvers91a,91b, . . . , and91nare not included, then this transmitter is a single cycle pulse transmitter. If BPFs are used in place of the convolvers, then this transmitter is a wave train transmitter. Moreover, if the balanced interrupted oscillator shown inFIG. 14is driven by the phase distributor shown inFIG. 20to perform transmission, the balanced interrupted oscillator functions as a wave train transmitter.

FIG. 23shows the rough structure of a receiver for deflecting a receiving direction.

Each of convolvers101a,101b, . . . , and101nshown inFIG. 23contains a square circuit in place of an integrator. Each of the convolvers101a,101b, . . . , and101nis paired with an orthogonal convolver the conductive layer pattern of which is shifted by T/4. Different values corresponding to deflection angles are provided to the respective conductive sections of the convolvers on the routes from antennas102a,102b, . . . , and102n. This structure can also be used on the transmitting side.

Receiving template signals which differ from one another in timing are generated in order and a correlation between a received signal and a receiving template signal is detected. By detecting the timing of the generation of a receiving template signal which gives a great correlation value, the timing of a received signal received by each of the antennas102a,102b, . . . , and102nis known. The direction from which the received signal reached is known from the timing of the received signal (θ, being the direction from which the received signal reached, can be calculated by using the above equation).

By outputting single cycle pulses with different phases by using the phase distributor shown inFIG. 20, the transmitter can scan beams more finely. By generating receiving template signals with different phases by using the phase distributor shown inFIG. 20, the receiver can scan received signals more finely.

A wide band receiver will now be described.

FIG. 24is a block diagram of a wide band receiver using a reference wave.

The multiphase clock source116outputs clocks the phases of which differ by the same amount. A despreading code is inputted to the selector117. The selector117selects and outputs one of the clocks outputted from the multiphase clock source116in accordance with the despreading code.

The phase distributor118is the same as that shown inFIG. 20and divides the phase of the clock outputted from the selector117. As a result, clocks with various phases can be outputted and beams (received radio signal) can be detected more finely.

The waveform generators119a,119b, . . . , and119ngenerate reference waves with which the correlation of the beams should be detected on the basis of the clocks outputted from the phase distributor118.

If directivity is not required, then one waveform generator, one antenna, and one mixer should be used. A phase distributor is unnecessary. Furthermore, down conversion or direct conversion can be performed by using an orthogonal local oscillator. In this case, carrier synchronization is unnecessary. In addition, a receiving direction can be changed. In this case, a plurality of waveform generators are used and a phase distributor is used at need. By locating phase distributors at many stages, a receiving direction can be adjusted more finely.

As described above, a radio signal is deflected, is transmitted, and is received from a specific direction. As a result, the transmitting and receiving of a signal can be performed between, for example, the back plane81and a lower transmitter-receiver module84aor84bon a particular CPU board82aor82bshown inFIG. 18. An antenna is contained in each of the transmitter-receiver modules84amounted on the CPU boards82aand the transmitter-receiver modules84bmounted on the CPU boards82b. Moreover, a small receiving antenna and a receiving circuit are contained in some of LSIs mounted on the CPU boards82aand82b.

A communication system according to a fourth embodiment of the present invention will now be described in detail with reference to the drawing.

FIG. 25is a circuit diagram of a quadrature modulation sending circuit.

A 16-phase clock source121shown inFIG. 25is a clock source for outputting sixteen clocks (negative pulses) with different phases at a frequency of 15.625 GHz. As shown inFIG. 25, sources of transistors M31and M32are connected to one output terminal of the 16-phase clock source121. An antenna123is connected to a drain of the transistor M31and a power supply is connected to a drain of the transistor M32. A stub122with a length equal to a fourth of the wavelength corresponding to a frequency of 62.5 GHz is connected between the antenna123and the power supply. Transistors which are the same as the transistors M31and M32, a stub which is the same as the stub122, and an antenna which is the same as the antenna123are connected to each output terminal of the 16-phase clock source121.

Code-spread serial data is inputted to gates of these transistors. This data is mutually orthogonal differential baseband signals and inputted as signals I and Q. When the transistors turn on by the signal I or Q, the stubs are driven by negative current pulses outputted from the 16-phase clock source121. The antennas output signals at frequency of 62.5 GHz are generated in respective stubs. The transistors are turned on/off by the signal I or Q with the timing of four clocks outputted from the 16-phase clock source121at 4-phase spacing.

The phases of the signals I and Q are selected in increments of 90 degrees, so four different states can be obtained. By selecting four clocks outputted from the 16-phase clock source121at 4-phase spacing, the quadrature-modulated signals I and Q at a frequency of 62.5 GHz, which is four times the frequency (=15.625 GHz) of a clock outputted from the 16-phase clock source121, can be generated. As stated above, the code-spread data is quadrature-modulated and is output from the antennas as the signals at a frequency four times the frequency of the sixteen clocks with different phases.

In the above example, a signal generated in each stub is outputted from each antenna. However, a signal obtained by summing the outputs from the sixteen transistors at one stub may be outputted from one antenna.

A quadrature modulation receiving circuit for receiving a signal outputted from the quadrature modulation sending circuit shown inFIG. 25will now be described.

FIG. 26is a circuit diagram of a quadrature modulation receiving circuit.

A 16-phase clock source131shown inFIG. 26is the same as the 16-phase clock source121shown inFIG. 25. As shown inFIG. 26, sources of transistors M33and M34are connected to one output terminal of the 16-phase clock source131. A mixer135, an amplifier134, and an antenna133are connected in series and the mixer is connected to a drain of the transistor M33. A power supply is connected to a drain of the transistor M34. A stub132which is the same as the stub122shown inFIG. 25is connected between the mixer135and the power supply. Transistors which are the same as the transistors M33and M34, a stub which is the same as the stub132, a mixer which is the same as the mixer135, an amplifier which is the same as the amplifier134, and an antenna which is the same as the antenna133are connected to each output terminal of the 16-phase clock source131.

A signal Q with which the correlation of the code-spread data described inFIG. 25is detected is inputted to gates of the transistors M33and M34. A negative current pulse is sent to the stub132in response to the signal Q. A short wave train at a frequency of 62.5 GHz generated at the end of the stub132is outputted to the mixer135. On the other hand, the signal received by the antenna133is amplified at need by the amplifier134and is outputted to the mixer135. The mixer135detects a correlation between the signal received by the antenna133and the signal outputted from the stub132and outputs it. By integrating the sum total of signals outputted from the mixer135over a code period, received data after quadrature demodulation and despreading can be obtained. As described above, radio communication can also be performed by using the circuits shown inFIGS. 25 and 26.

In the transmitter in the communication system according to the present invention, one of a plurality of transmitting-end synchronizing signals with different phases is selected and a radio signal is transmitted in synchronization with the selected transmitting-end synchronizing signal. In the receiver, one of a plurality of receiving-end synchronizing signals with different phases is selected and the radio signal is received in synchronization with the selected receiving-end synchronizing signal. As a result, even if a data transmission rate is high, there is no need to increase the frequencies of transmitting-end and receiving-end synchronizing signals. Therefore, circuits can be realized easily and power consumption can be reduced.