DEEP TRENCH CAPACITOR BRIDGE FOR MULTI-CHIP PACKAGE

A device is provided, including a bridge substrate and a redistribution layer on a top surface of the bridge substrate. The bridge substrate may include a plurality of trenches extending vertically into the bridge substrate from a bottom surface of the bridge substrate, wherein each of the plurality of trenches may include a conductive filling; a conductive layer partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer; a plurality of first contact pads under the bottom surface of the bridge substrate and coupled to the conductive layer; and a plurality of second contact pads under the bottom surface of the bridge substrate and coupled to the conductive fillings of the plurality of trenches.

BACKGROUND

In power delivery network (PDN) design, decoupling capacitors may be added to improve the PDN impedance and performance, especially for devices with very tight voltage constraint while having fast and big transient current. For embedded multi-die interconnect bridge (EMIB) based interface solutions, providing a low impedance connection to die side capacitance will be challenging when the EMIB interface is deep inside the die edge.

Existing solutions in mitigating power integrity for a multi-chip package (MCP) with EMIB include embedded package capacitor, package land-side capacitor (LSC) and/or package die side capacitor (DSC) designs. For DSC design, additional package surface area is required to implement DSC, which may lead to increased package form factor and costs. In addition, package substrate layer count may be increased to effectively connect the inner EMIB interfacing power domain to the DSC at the edge of the package. For LSC design, increased ball grid array (BGA) cavity keep-out zone (KOZ) for LSC component placement may lead to BGA input/output (TO) density trade-off and/or package form-factor expansion.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawings that show,

by way of illustration, specific details and aspects in which the present disclosure may be practiced. These aspects are described in sufficient detail to enable those skilled in the art to practice the present disclosure. Various aspects are provided for devices, and various aspects are provided for methods. It will be understood that the basic properties of the devices also hold for the methods and vice versa. Other aspects may be utilized and structural, and logical changes may be made without departing from the scope of the present disclosure. The various aspects are not necessarily mutually exclusive, as some aspects can be combined with one or more other aspects to form new aspects.

The present disclosure introduces a bridge with deep trench capacitors (DTC) to enable shorter decoupling capacitance connection for improved power integrity in multi-chip package applications.

Advantages of the present disclosure may include improved power integrity through shorter interconnects between a silicon bridge deep trench capacitor (DTC) and power domains of an inter-chip interface, e.g., multi-die fabric interconnects (MDFI) interface. Reduced power delivery network impedance (ZPDN) and higher decoupling capacitance density may be achieved, compared to a metal-insulator-metal capacitor (MIMCAP) solution, e.g., up-to 400 nF/mm2vs 86 nF/mm2.

Further advantages of the present disclosure may include device miniaturization through minimized package real-estate keep-out-zone requirement for the placement of decoupling capacitor components.

In all aspects, the present disclosure generally relates to a device that may include a bridge substrate, and a redistribution layer on a top surface of the bridge substrate. The bridge substrate may include a plurality of trenches extending vertically into the bridge substrate from a bottom surface of the bridge substrate, wherein each trench of the plurality of trenches may include a conductive filling. The bridge substrate may further include a conductive layer partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer, a plurality of first contact pads under the bottom surface of the bridge substrate and coupled to the conductive layer, and a plurality of second contact pads under the bottom surface of the bridge substrate and coupled to the conductive fillings of the plurality of trenches.

The present disclosure generally relates to a method of forming a device. The method may include providing a bridge substrate and a redistribution layer under a bottom surface of the bridge substrate; forming a plurality of intermediate trenches vertically extending into the bridge substrate from a top surface of the bridge substrate; forming a conductive layer on inner walls of the plurality of intermediate trenches, and forming a dielectric layer on the conductive layer; forming conductive fillings into the plurality of intermediate trenches, wherein the conductive fillings are on the dielectric layer; and forming a plurality of first contact pads and a plurality of second contact pads on the top surface of the bridge substrate, wherein the plurality of first contact pads are coupled to the conductive layer, and wherein the plurality of second contact pads are coupled to the conductive fillings in the plurality of intermediate trenches.

The present disclosure generally relates to a semiconductor package. The semiconductor package may include a package substrate, a bridge at least partially embedded in the package substrate, a first die and a second die on the package substrate. The bridge may include a bridge substrate, and a redistribution layer on a top surface of the bridge substrate. The bridge substrate may include a plurality of trenches extending vertically into the bridge substrate from a bottom surface of the bridge substrate, wherein each trench of the plurality of trenches may include a conductive filling. The bridge substrate may further include a conductive layer partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer, a plurality of first contact pads under the bottom surface of the bridge substrate and coupled to the conductive layer, and a plurality of second contact pads under the bottom surface of the bridge substrate and coupled to the plurality of trenches. The first die and the second die may be coupled to the conductive layer through the plurality of first contact pads. The first die may be coupled to at least a respective one of the plurality of trenches through a corresponding one of the plurality of second contact pads. The second die may be coupled to at least an other respective one of the plurality of trenches through an other corresponding one of the plurality of second contact pads.

The present disclosure generally relates to a computing device. The computing device may include a printed circuit board and a semiconductor package coupled to the printed circuit board. The semiconductor package may include a package substrate, a bridge at least partially embedded in the package substrate, a first die and a second die on the package substrate. The bridge may include a bridge substrate, and a redistribution layer on a top surface of the bridge substrate. The bridge substrate may include a plurality of trenches extending vertically into the bridge substrate from a bottom surface of the bridge substrate, wherein each trench of the plurality of trenches may include a conductive filling. The bridge substrate may further include a conductive layer partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer, a plurality of first contact pads under the bottom surface of the bridge substrate and coupled to the conductive layer, and a plurality of second contact pads under the bottom surface of the bridge substrate and coupled to the plurality of trenches. The first die and the second die may be coupled to the conductive layer through the plurality of first contact pads. The first die may be coupled to at least a respective one of the plurality of trenches through a corresponding one of the plurality of second contact pads. The second die may be coupled to at least an other respective one of the plurality of trenches through an other corresponding one of the plurality of second contact pads.

To more readily understand and put into practice the aspects of the present semiconductor package, particular aspects will now be described by way of examples and not limitations, and with reference to the figures. For the sake of brevity, duplicate descriptions of features and properties may be omitted.

It should be understood that the terms “on”, “under”, “top”, “bottom”, etc., when used in this description are used for convenience and to aid understanding of relative positions or directions, and not intended to limit the orientation of any device, or structure or any part of any device or structure.

In an aspect shown inFIG.1, a semiconductor device100of the present disclosure is shown in a cross-sectional view layout, including a bridge substrate102, and a redistribution layer (RDL)130on a top surface104of the bridge substrate102. The bridge substrate102may include a plurality of trenches112extending vertically into the bridge substrate102from a bottom surface106of the bridge substrate102, wherein each trench112of the plurality of trenches112may include a conductive filling114. The bridge substrate102may include a conductive layer116partially surrounding the plurality of trenches112and separated from the plurality of trenches112by a dielectric layer118. The bridge substrate102may further include a plurality of first contact pads122under the bottom surface106of the bridge substrate102and coupled to the conductive layer116, and a plurality of second contact pads124under the bottom surface106of the bridge substrate102and coupled to the conductive fillings114of the plurality of trenches112.

According to various aspects of the present disclosure, the plurality of trenches112may be entirely filled with the conductive fillings114, and may be referred to as the plurality of conductive trenches. The plurality of trenches112may be coupled to a power supply in an aspect, and may be referred to as power trenches accordingly. The plurality of trenches112may be coupled to ground in another aspect, and may be referred to as ground trenches accordingly. In an aspect, the conductive fillings114may include copper (Cu), titanium nitride (TiN), or tin-silver (SnAg) composites.

According to various aspects of the present disclosure, the plurality of trenches112may have a height substantially larger than a width, and may be referred to as deep trenches. In an aspect, the trenches112may have a high aspect ratio greater than 4:1. In another aspect, the trenches112may have a high aspect ratio greater than 10:1. In an example, the aspect ratio of the trenches112may be about 10:1.

In an aspect, the plurality of trenches112may be configured spaced apart from the top surface104of the bridge substrate102. In other words, the plurality of trenches112may have one end exposed from the bottom surface106of the bridge substrate102, while have another end spaced apart from the top surface104of the bridge substrate102, as shown inFIG.1. The end of the trenches112exposed from the bottom surface106of the bridge substrate102may be in physical contact with the second contact pads124. According to an example, the heights of the plurality of trenches112may be about 20%-80% of a thickness of the bridge substrate102. In an example, the thickness of the bridge substrate102may be in a range from about 50 μm to about 300 μm.

In another aspect, the plurality of trenches112may extend vertically through the bridge substrate102, as shown inFIG.3Abelow. In other words, the plurality of trenches112may have one end exposed from the bottom surface106of the bridge substrate102, and have another end exposed from the top surface104of the bridge substrate102.

The plurality of trenches112may be spaced apart from each other, wherein the intervals between adjacent trenches may be the same or may be different. It is understood that the dimensions, e.g., the height, the width, and/or the aspect ratio, of the trenches112may be the same or may be different from each other.

According to an aspect of the present disclosure, the conductive layer116may further extend along the bottom surface106of the bridge substrate102and may extend between the plurality of trenches112. The dielectric layer118may further extend along the conductive layer116and may extend between the plurality of trenches112. In an aspect, the conductive layer116and the dielectric layer118may each be a continuous layer extending along the periphery of the trenches112and between the trenches112, as shown in in the examples ofFIG.1andFIG.2.

The dielectric layer118may include a high-k material having a relative permittivity of 20-15000. In an example, the high-k material may include calcium copper titanium oxide (CCTO) or barium titanate (BaTiO3). In an aspect, the dielectric layer118may include hafnium dioxide (HfO2).

The plurality of first contact pads122and the plurality of second contact pads124may lie in a same plane under the bottom surface106of the bridge substrate102. In other words, the first contact pads122and the second contact pads124may be levelled under the bottom surface106of the bridge substrate102. The plurality of first contact pads122are labelled differently from the plurality of second contact pads124in the drawings for convenience and to aid understanding of relative positions or couplings. It is understood that the plurality of first contact pads122may include the same conductive material as or may include different conductive materials from the plurality of second contact pads124. It is also understood that the plurality of first contact pads122and the plurality of second contact pads124may be formed simultaneously or separately.

According to various aspects of the present disclosure, the conductive layer116, the dielectric layer118and the conductive fillings114of the plurality of trenches112may form an array of capacitors, e.g., an array of deep trench capacitors (DTC), which may be used as decoupling capacitors. The conductive layer116may form a first terminal of the capacitor, and the conductive fillings114of the trenches112may form a second terminal of the capacitor. The deep trench capacitors have very high capacitance density, especially when they are coupled in parallel, and when combined with the bridge substrate may be used to form a dense structure for improved power delivery.

In an aspect, the conductive layer116may be coupled to a reference voltage, e.g., a ground (Vss) reference voltage. The plurality of trenches112may be coupled to a power (Vcc) supply voltage. Accordingly, the inner ground layer116may be a continuous plane or layer across all the vertical trenches112, and the vertical deep trench conductors112may be connected to power domain to form the capacitance with the ground layer116. In another example, the plurality of trenches112may include a first group and a second group. The first group of trenches may be coupled to a first power supply voltage, and the second group of trenches may be coupled to a second power supply voltage different from the first power supply voltage. Accordingly, multiple power domain decoupling capacitors may be formed by connecting the vertical deep trench conductors112to different power sources.

In another example, the conductive layer116may be coupled to the power (Vcc) supply voltage, and the trenches112may be coupled to the ground (Vss) reference voltage. In a further example, the conductive layer116may be partitioned or interrupted between the trenches112(not shown inFIG.1), such that the segments of the conductive layer116associated with the first group of trenches may be coupled to the first power supply voltage and the segments of the conductive layer116associated with the second group of trenches may be coupled to the second power supply voltage to form multiple power domain decoupling capacitors.

According to a further aspect of the present disclosure, the conductive layer116and the plurality of trenches112may be coupled to the redistribution layer130. In an aspect, the conductive layer116may surround only the sidewalls of the trenches112and may be absent over the top surface of the trenches112to expose the conductive filling of the trenches for coupling with the redistribution layer130(e.g., for coupling with a power layer in the redistribution layer) from the top surface of the bridge substrate, as shown in the example ofFIG.3Abelow. The conductive layer116may also be coupled with the redistribution layer130(e.g., with a ground layer in the redistribution layer) from the top surface of the bridge substrate.

The bridge substrate102may include a silicon substrate, a glass-based substrate, a ceramic substrate, or an organic substrate. In an aspect, the organic bridge substrate may include a thermoset epoxy polymer, silicone or composites molding compound. The redistribution layer (RDL)130may include one or more metal layers isolated by one or more dielectric layers, wherein metal interconnection or metal traces may be formed in the metal layers to route electrical signals between various dies in a semiconductor package. In an aspect, the RDL130may include a signal layer for signal transmission, and one or more reference voltage layers, e.g., a ground reference voltage (Vss) plane and/or a power supply voltage (Vcc) plane. The device100including the bridge substrate102and the redistribution layer130may form a bridge, which may be referred to as an embedded multi-die interconnect bridge (EMIB) and may be embedded in an integrated circuit package to connect one chip to another. According to various aspects, deep trench capacitors may be implemented at the backside of the bridge to leverage the available EMIR substrate area.

According to various aspect of the present disclosure, the device100may further include a package substrate, wherein the bridge substrate102and the redistribution layer130may be at least partially embedded in the package substrate as shown inFIG.2andFIG.3Abelow. The package substrate may include contact pads, electrical interconnects and routings, and other features, for signal routing and electrical connection to various devices and components.

The conductive layer116and the plurality of trenches112may be coupled to the package substrate through the plurality of first contact pads122and the plurality of second contact pads124, respectively.

In an aspect, the device100may further include a first die and a second die on the package substrate, wherein the first die and the second die may be coupled through the redistribution layer130as shown inFIG.2andFIG.3Abelow.

The conductive layer116may be coupled to the first die and the second die through the plurality of first contact pads122, and each of the plurality of trenches112may be coupled to at least one of the first die or the second die through a respective one of the plurality of second contact pads124. Accordingly, the decoupling capacitors in the bridge substrate102may be coupled to the first die and the second die through the first contact pads122and the second contact pads124from the bottom surface106of the bridge substrate102.

In a further aspect, the conductive layer116and each of the plurality of trenches112may be coupled to at least one of the first die or the second die through the redistribution layer130. Accordingly, the decoupling capacitors in the bridge substrate102may be further coupled to the first die and the second die through the redistribution layer130from the top surface104of the bridge substrate102. In an aspect, the conductive layer116may include a copper (Cu) layer or a titanium nitride (TiN) layer. In an aspect, an insulation layer (not shown) e.g., a silicon dioxide (SiO2) layer may be formed in between the bridge substrate102and the conductive layer116for improved reliability.

FIG.2shows a cross-sectional view of a semiconductor device200according to another aspect of the present disclosure.

Many of the aspects of the semiconductor device200are the same or similar to those of the semiconductor device100. For the sake of brevity, duplicate descriptions of features and properties are omitted. Accordingly, it will be understood that the descriptions of any feature and/or property relating toFIG.2that are the same or similar to a feature and/or property inFIG.1will have those descriptions be applicable hereinbelow as well.

In the aspect shown inFIG.2, a semiconductor device200of the present disclosure is shown in a cross-sectional view layout, including a bridge substrate202, and a redistribution layer (RDL)230on a top surface204of the bridge substrate202. The bridge substrate202may include a plurality of trenches212extending vertically into the bridge substrate202from a bottom surface206of the bridge substrate202, wherein each trench212may include a conductive filling214. The bridge substrate202may include a conductive layer216partially surrounding the plurality of trenches212and separated from the plurality of trenches212by a dielectric layer218. The bridge substrate202may further include a plurality of first contact pads222under the bottom surface206of the bridge substrate202and coupled to the conductive layer216, and a plurality of second contact pads224under the bottom surface206of the bridge substrate202and coupled to the conductive fillings214of the plurality of trenches212.

The plurality of trenches212may be entirely filled with the conductive fillings214, and may be referred to as the plurality of conductive trenches. The plurality of trenches212may be coupled to a power supply in an aspect, and may be referred to as power trenches accordingly. The plurality of trenches212may be coupled to ground in another aspect, and may be referred to as ground trenches accordingly.

According to various aspects of the present disclosure, the plurality of trenches212may have a height substantially larger than a width, and may be referred to as deep trenches. In an aspect, the trenches212may have a high aspect ratio greater than 4:1. In another aspect, the trenches212may have a high aspect ratio greater than 10:1. In an example, the aspect ratio of the trenches212may be about 10:1.

In an aspect, the plurality of trenches212may be configured spaced apart from the top surface204of the bridge substrate202. As shown inFIG.2, the plurality of trenches212may have one end exposed from the bottom surface206of the bridge substrate202, while have another end spaced apart from the top surface204of the bridge substrate202. The end of the trenches212exposed from the bottom surface206of the bridge substrate202may be in physical contact with the second contact pads224. According to an example, the heights of the plurality of trenches212may be about 20%-80% of a thickness of the bridge substrate202.

The plurality of trenches212may be spaced apart from each other, wherein the intervals between adjacent trenches may be the same or may be different. It is understood that the dimensions, e.g., the height, the width, and/or the aspect ratio, of the trenches212may be the same or may be different from each other.

Similar toFIG.1, the conductive layer216may further extend along the bottom surface206of the bridge substrate202and may extend between the plurality of trenches212. The dielectric layer218may further extend along the conductive layer216and may extend between the plurality of trenches212. As shown inFIG.2, the conductive layer216and the dielectric layer218may each be a continuous layer extending along the periphery of the trenches212and between the trenches212. The dielectric layer218may include a high-k material having a relative permittivity of 20-15000. In an example, the high-k material may include calcium copper titanium oxide (CCTO) or barium titanate (BaTiO3). In an aspect, the dielectric layer218may include hafnium dioxide (HfO2).

The plurality of first contact pads222and the plurality of second contact pads224may lie in a same plane under the bottom surface206of the bridge substrate202. In other words, the first contact pads222and the second contact pads224may be levelled under the bottom surface206of the bridge substrate202.

The conductive layer216, the dielectric layer218and the conductive fillings214of the plurality of trenches212may form an array of capacitors, e.g., an array of deep trench capacitors, which may serve as decoupling capacitors. The conductive layer216may form a first terminal of the capacitors, and the conductive fillings214of the trenches212may form a second terminal of the capacitors.

In an aspect, the conductive layer216may be coupled to a reference voltage, e.g., a ground (Vss) reference voltage. The plurality of trenches212may be coupled to a power (Vcc) supply voltage. Accordingly, the inner ground layer216may be a continuous plane across all the vertical trenches212, and the vertical deep trench conductors212may be connected to power domain to form the capacitance with the ground layer216. In another example, the plurality of trenches212may include a first group and a second group. The first group of trenches may be coupled to a first power supply voltage, and the second group of trenches may be coupled to a second power supply voltage different from the first power supply voltage. Accordingly, multiple power domain decoupling capacitors may be formed by connecting the vertical deep trench conductors212to different power sources.

In another example, the conductive layer216may be coupled to the power (Vcc) supply voltage, and the trenches212may be coupled to the ground (Vss) reference voltage. In a further example, the conductive layer216may be partitioned or interrupted between the trenches212(not shown inFIG.2), such that the segments of the conductive layer216associated with the first group of trenches may be coupled to the first power supply voltage and the segments of the conductive layer216associated with the second group of trenches may be coupled to the second power supply voltage to form multiple power domain decoupling capacitors.

Similar toFIG.1, the bridge substrate202may include a silicon substrate, a glass-based substrate, a ceramic substrate, or an organic substrate. The redistribution layer (RDL)230may include one or more metal layers isolated by one or more dielectric layers. In an aspect, the RDL230may include a signal layer for signal routing between various dies in a semiconductor package, and one or more reference voltage layers, e.g., a ground reference voltage (Vss) plane and/or a power supply voltage (Vcc) plane. The bridge substrate202and the redistribution layer230may form a bridge, which may be referred to as an embedded multi-die interconnect bridge (EMIB) and may be embedded in the device200(also referred to as a semiconductor package or an integrated circuit package) to connect one chip to another. According to various aspects, deep trench capacitors may be implemented at the backside of the bridge to leverage the available EMIR substrate area.

According to various aspect ofFIG.2, the device200may further include a package substrate240, wherein the bridge including the bridge substrate202and the redistribution layer230may be at least partially embedded in the package substrate240. The package substrate240may include contact pads, electrical interconnects and routings, and other features, for signal routing and electrical connection to various devices and components. An underfill layer250may be provided to fill a gap between the package substrate240and the bridge, and to cover and protect the solder bumps.

The bridge may be coupled to the package substrate240at the bottom surface through the first and second contact pads222,224. As shown inFIG.2, the bridge substrate202may be electrically coupled to the package substrate240through the first and second contact pads222,224, the solder bumps and the contact pads of the package substrate240. The conductive layer216and the plurality of trenches212may be coupled to the package substrate240through the first contact pads222and the second contact pads224, respectively.

The semiconductor package200may further include a first die252and a second die254on the package substrate240. The first die252and the second die254may be coupled through the redistribution layer230, which may be configured for signal routing and power delivery between the first die252and the second die254. In an aspect as shown inFIG.2, the first die252and the second die254may be spaced apart from each other, and may each overlie both the package substrate240and the bridge for electrical coupling to the package substrate240and the bridge.

The bridge at least partially embedded within the package substrate240may facilitate electrical interconnects between the first die252and the second die254. In an aspect, the first die252may be a first silicon device, e.g., a central processing unit (CPU) or a graphic processing unit (GPU). The second die254may be a second silicon device, e.g., a platform controller hub (PCH), a DRAM memory, an I/O tile or a field programmable gate array (FPGA) device.

In an aspect, the first die252and the second die254may be coupled to the plurality of deep trench capacitors through the first and second contact pads222,224and the package substrate240to facilitate improved power delivery, e.g., supply of charges from the deep trench capacitor storage.

The conductive layer216may be coupled to the first die252and the second die254through the first contact pads222, and each of the plurality of trenches212may be coupled to at least one of the first die252or the second die254through a respective one of the plurality of second contact pads224. Accordingly, the deep trench capacitors in the bridge substrate202may be coupled to the first die252and the second die254through the first contact pads222and the second contact pad224from the bottom surface206of the bridge substrate202.

In an aspect, the conductive layer216, the first die252and the second die254may be coupled to a reference voltage, e.g., the ground (Vss) reference voltage, as represented by the connections242inFIG.2. The plurality of trenches212may be coupled to one or more power (Vcc) supply voltages. In an example as shown inFIG.2, the plurality of trenches212may include a first group and a second group. The first group of trenches and the first die252may be coupled to a first power supply voltage provided by a first power supply, e.g., a 1.0V supply, as represented by the connections244inFIG.2. The second group of trenches and the second die254may be coupled to a second power supply voltage provided by a second power supply, e.g., a 1.8V supply, as represented by the connections246inFIG.2. The second power voltage may be different from the first power supply voltage.

Various aspects ofFIG.2provide a multi-chip electronic package200with a deep trench capacitor (DTC) bridge for improved electrical performance and device miniaturization. The semiconductor package200may be coupled to a printed circuit board (not shown), e.g., a motherboard, through solder balls and associated contact pads.

FIG.3Ashows a cross-sectional view of a semiconductor device300along line A-A′ ofFIG.3Baccording to a further aspect of the present disclosure, andFIG.3Bshows a top view layout of the semiconductor device300according to the aspect as shown inFIG.3A.

Many of the aspects of the semiconductor device300are the same or similar to those of the semiconductor devices100,200. For the sake of brevity, duplicate descriptions of features and properties are omitted. Accordingly, it will be understood that the descriptions of any feature and/or property relating toFIG.3AandFIG.3Bthat are the same or similar to a feature and/or property inFIG.1andFIG.2will have those descriptions be applicable hereinbelow as well.

In the aspect shown inFIG.3A, a semiconductor device300of the present disclosure is shown in a cross-sectional view layout, including a bridge substrate302, and a redistribution layer (RDL)330on a top surface304of the bridge substrate302. The bridge substrate302may include a plurality of trenches312extending vertically into the bridge substrate302from a bottom surface306of the bridge substrate302, wherein each trench312may include a conductive filling314. The bridge substrate302may include a conductive layer316partially surrounding the plurality of trenches312and separated from the plurality of trenches312by a dielectric layer318. The bridge substrate302may further include a plurality of first contact pads322under the bottom surface306of the bridge substrate302and coupled to the conductive layer316, and a plurality of second contact pads324under the bottom surface306of the bridge substrate302and coupled to the conductive fillings314of the plurality of trenches312.

Similar toFIG.1andFIG.2above, the plurality of trenches312may be entirely filled with the conductive fillings314, and may be referred to as the plurality of conductive trenches. The plurality of trenches312may be power trenches coupled to a power supply in an aspect, or may be ground trenches coupled to a ground voltage in another aspect.

The plurality of trenches312may be deep trenches having a height substantially larger than a width. In an example, an aspect ratio of the trench312may be about 10:1. The plurality of trenches312may be spaced apart from each other, wherein the intervals between adjacent trenches may be the same or may be different. It is understood that the dimensions, e.g., the height, the width, and/or the aspect ratio, of the trenches312may be the same or may be different from each other.

In an aspect as shown inFIG.3A, the plurality of trenches312may extend vertically through the bridge substrate302. In other words, the plurality of trenches312may have one end exposed from the bottom surface306of the bridge substrate302, and have another end exposed from the top surface304of the bridge substrate302. The end of the trenches312exposed from the bottom surface306of the bridge substrate302may be in physical contact with the second contact pads324.

Similar toFIG.1andFIG.2, the conductive layer316may further extend along the bottom surface306of the bridge substrate302and may extend between the plurality of trenches312. The dielectric layer318may further extend along the conductive layer316and may extend between the plurality of trenches312.

According to an aspect ofFIG.3A, the conductive layer316may surround only the sidewalls of the trenches312and may be absent over the top surface of the trenches312, to expose the conductive filling314of the trenches312for coupling with the redistribution layer330(e.g., for coupling with a power (Vcc) layer334in the redistribution layer330) from the top surface304of the bridge substrate302. Accordingly, the plurality of trenches312may be coupled to the redistribution layer330. In a further aspect, the conductive layer316may also be coupled to the redistribution layer330(e.g., to a ground (Vss) layer336in the redistribution layer330) from the top surface304of the bridge substrate302.

The conductive layer316, the dielectric layer318and the conductive fillings314of the plurality of trenches312may form an array of capacitors311as shown inFIG.3B, e.g., an array of deep trench capacitors, which may serve as decoupling capacitors. The conductive layer316may form a first terminal of the capacitors311, and the conductive fillings314of the trenches312may form a second terminal of the capacitors311.

Similar to the disclosure ofFIG.1andFIG.2above, the conductive layer316may be coupled to a reference voltage, e.g., a ground (Vss) reference voltage, and the plurality of trenches312may be coupled to one or more power (Vcc) supply voltages. In another example, the conductive layer316may be coupled to one or more power (Vcc) supply voltages, and the trenches312may be coupled to the ground (Vss) reference voltage, as described above.

In an aspect, the redistribution layer (RDL)330may include one or more metal layers isolated by one or more dielectric layers. As illustrated inFIG.3, the RDL330may include a signal layer332to facilitate signal transmission between various silicon devices in the semiconductor package300. The RDL330may include a power (Vcc) layer334to facilitate power delivery between various silicon devices. The RDL330may further include a ground (Vss) layer336to facilitate current return path and/or to facilitate a shielding layer for the signal layer and/or the power layer. The bridge substrate302and the redistribution layer330may form a bridge, which may be referred to as an embedded multi-die interconnect bridge (EMIR), wherein deep trench capacitors311may be implemented at the backside of the bridge to leverage the available EMIR substrate area.

According to various aspect ofFIGS.3A and3B, the semiconductor package300may further include a package substrate340, wherein the bridge including the bridge substrate302and the redistribution layer330may be at least partially embedded in the package substrate340. The package substrate340may include contact pads, electrical interconnects and routings, and other features, for signal routing and electrical connection to various devices and components. An underfill layer350may be provided to fill a gap between the package substrate340and the bridge, and to cover and protect the solder bumps.

The bridge may be coupled to the package substrate340at the bottom surface through the first and second contact pads322,324. As shown inFIG.3A, the bridge substrate302may be electrically coupled to the package substrate340through the first and second contact pads322,324, the solder bumps and the contact pads of the package substrate340. The conductive layer316and the plurality of trenches312may be coupled to the package substrate340through the first contact pads322and the second contact pads324, respectively.

Similar toFIG.2, the semiconductor package300may further include a first die352and a second die354on the package substrate340. The first die352and the second die354may be coupled through the redistribution layer330, which may be configured for signal routing and power delivery between the first die352and the second die354. In an aspect, the first die352and the second die354may be spaced apart from each other, and may each overlie both the package substrate340and the bridge for electrical coupling to the package substrate340and the bridge.

The bridge at least partially embedded within the package substrate340may facilitate electrical interconnects between the first die352and the second die354. In an aspect, the first die352may be a central processing unit (CPU) or a graphic processing unit (GPU). The second die354may be a platform controller hub (PCH), a DRAM memory, an I/O tile or a field programmable gate array (FPGA) device.

In an aspect, the first die352and the second die354may be coupled to the plurality of deep trench capacitors311through the first and second contact pads322,324and the package substrate340to facilitate improved power delivery, e.g., supply of charges from the deep trench capacitor storage.

The conductive layer316may be coupled to the first die352and the second die354through the plurality of first contact pads322, and each of the plurality of trenches312may be coupled to at least one of the first die352or the second die354through a respective one of the plurality of second contact pads324. In an example as shown inFIG.3AandFIG.3B, a first group313of capacitors311including the first group of trenches may be coupled to the first die352through the respective second contact pads324. In an example, the first group313of capacitors311may be coupled in parallel. A second group315of capacitors311including the second group of trenches may be coupled to the second die354through the respective second contact pads324. In an example, the second group315of capacitors311may be coupled in parallel. Accordingly, the deep trench capacitors311in the bridge substrate302may be coupled to the first die352and the second die354through the first contact pads322and the second contact pads324from the bottom surface306of the bridge substrate302.

In an aspect, the conductive layer316, the first die352and the second die354may be coupled to a reference voltage, e.g., the ground (Vss) reference voltage, as represented by the connections342inFIG.3A. The plurality of trenches312may be coupled to one or more power (Vcc) supply voltages. In an example as shown inFIG.3A, the plurality of trenches312may include a first group313and a second group315. The first group313of trenches312and the first die352may be coupled to a first power supply voltage provided by a first power supply, e.g., a 1.0V supply, as represented by the connections344inFIG.3A. The second group315of trenches312and the second die354may be coupled to a second power supply voltage provided by a second power supply, e.g., a 1.8V supply, as represented by the connections346inFIG.3A.

In a further aspect ofFIG.3A, the conductive layer316and each of the plurality of trenches312may be coupled to at least one of the first die352or the second die354through the redistribution layer330. In an aspect, the trenches312may be coupled to the power layer334within the RDL330to facilitate power delivery between the first and second dies352,354. The conductive layer316may be coupled to the ground (Vss) layer336within the RDL330. Accordingly, the decoupling capacitors311in the bridge substrate302may be further coupled to the first die352and the second die354through the redistribution layer330from the top surface304of the bridge substrate302.

According to various aspects described above, a multi-chip electronic package300with a deep trench capacitor (DTC) bridge may be provided for improved electrical performance and device miniaturization. The semiconductor package300may be coupled to a printed circuit board (not shown), e.g., a motherboard, through solder balls and associated contact pads.

FIG.4shows a flowchart400illustrating a method of forming a device, such as the device100,200,300ofFIGS.1,2and3A-3B, according to an aspect of the present disclosure. Various aspects described with reference toFIGS.1,2and3A-3Bmay be similarly applied for the method ofFIG.4.

At402, a bridge substrate and a redistribution layer under a bottom surface of the bridge substrate may be provided.

At404, a plurality of intermediate trenches vertically extending into the bridge substrate from a top surface of the bridge substrate may be formed.

At406, a conductive layer may be formed on inner walls of the plurality of intermediate trenches, and a dielectric layer may be formed on the conductive layer.

At408, conductive fillings may be formed into the plurality of intermediate trenches, wherein the conductive fillings may be on the dielectric layer.

At410, a plurality of first contact pads and a plurality of second contact pads may be formed on the top surface of the bridge substrate, wherein the plurality of first contact pads may be coupled to the conductive layer, and wherein the plurality of second contact pads may be coupled to the conductive fillings in the plurality of intermediate trenches.

According to an aspect of the present disclosure, the method may further include at least partially embedding the bridge substrate and the redistribution layer in a package substrate, wherein the conductive layer and the conductive fillings are coupled to the package substrate through the plurality of first contact pads and the plurality of second contact pads, respectively.

In an aspect, the method may further include arranging a first die and a second die on the package substrate, wherein the first die and the second die are coupled to the conductive layer through the plurality of first contact pads and each are coupled to a respective one of the conductive fillings through a corresponding one of the plurality of second contact pads.

It will be understood that the operations described above relating toFIG.4are not limited to this particular order. Any suitable, modified order of operations may be used.

FIGS.5A through5Gshow cross-sectional views directed to an exemplary process flow for a method of making a semiconductor device (e.g., the device100,200,300) according to an aspect of the present disclosure. Various aspects described with reference toFIGS.1,2, and3A-3B may be similarly applied for the process flow ofFIG.5A-5G.

InFIG.5A, a bridge501including a bridge substrate502and a redistribution layer530on a first surface504of the bridge substrate502may be provided. The bridge501may be an EMIB, and may be flipped with the bridge substrate502facing up. Accordingly, the redistribution layer530may appear under the bridge substrate502inFIG.5A.

InFIG.5B, a plurality of intermediate trenches517may be formed to vertically extend into the bridge substrate502from a second surface506of the bridge substrate502, e.g., through a mechanical or laser drilling process. The second surface506may be opposing the first surface504.

InFIG.5C, a conductive layer516may be formed on inner walls of the plurality of intermediate trenches517, e.g., through an electroless or electrolytic plating process. The conductive layer516may extend along the second surface506of the bridge substrate502and extend between the plurality of intermediate trenches517. In an aspect, an insulation layer (not shown), e.g., a silicon dioxide (SiO2) layer may be formed between the conductive layer516and the bridge substrate502. For example, the insulation layer may be formed on the inner walls of the plurality of intermediate trenches517prior to the deposition of the conductive layer516.

InFIG.5D, dielectric materials519may be formed on the conductive layer516and may be filled into the plurality of intermediate trenches517, e.g., through polymer filling, spin coating, printing or spraying process.

InFIG.5E, a dielectric layer518may be formed on the conductive layer516, e.g., through an etching or a laser drilling process, wherein portions of the dielectric materials519within the plurality of intermediate trenches517may be removed to form a plurality of trenches512and portions of the dielectric materials519on the second surface506of the bridge substrate502may be removed to form a plurality of recesses562.

InFIG.5F, conductive fillings may be formed on the dielectric layer518, e.g., through an electroplating or printing process. Conductive materials may be filled into the plurality of trenches512to form the conductive fillings514of the trenches512, and may be filled into the recesses562to form conductive vias564.

InFIG.5G, a plurality of first contact pads522and second contact pads524may be formed over the second surface506of the bridge substrate502, e.g., through an electrolytic plating or etching process. The first contact pads522may be formed on the vias564, and may be coupled to the conductive layer516through the vias564. The second contact pads524may be formed on the conductive fillings514of the trenches512, and may be coupled to the conductive fillings514in the plurality of trenches512. As shown inFIG.5G, the first contact pads522may be in physical contact with the vias564, and the second contact pads524may be in physical contact with the conductive fillings514of the trenches512. The structure500ofFIG.5Gmay be similar to the device100ofFIG.1above, and accordingly the device100may be manufactured according to the processes ofFIGS.5A-5G. The structure500ofFIG.5Gmay be referred to as the EMIB500, which may be flipped over and embedded into a package substrate to form the device200,300ofFIGS.2and3Aabove, as illustrated inFIG.6below.

FIGS.5A-5Gabove illustrate an exemplary process flow to manufacture a silicon bridge with deep trench capacitors for multi-chip package applications. The operation order described above may be interchangeable to achieve optimum assembly yield and/or throughput time.

FIG.6shows a flowchart600illustrating a method of forming a device, such as the device100,200,300ofFIGS.1,2and3A-3B, according to an aspect of the present disclosure. Various aspects described with reference toFIGS.1,2and3A-3Bmay be similarly applied for the method ofFIG.6.

At602, deep trench capacitors may be formed on a first surface of a bridge component, e.g. through drilling, lamination, etching and/or electroplating processes. The fabrication of deep trench capacitors may be performed according to the exemplary process flow ofFIGS.5A-5Gabove, wherein the bridge component with deep trench capacitor may be similar to the EMIB500illustrated inFIG.5Gabove.

At604, a recess opening is formed in a package substrate, e.g., through a drilling or etching process.

At606, the bridge component with deep trench capacitors may be attached or embedded within the recess opening of the package substrate, e.g., through a surface mounting or thermal compression bonding process.

At608, an underfill layer may be provided to fill a gap between the bridge component and the recess opening, e.g., through a capillary dispense process.

At610, a first die and a second die may be attached to a first side of the package substrate and to a second surface of the bridge component, e.g., through a surface mounting or thermal compression bonding process. The second surface of the bridge component may be opposing to the first surface.

At612, an underfill may be provided to the first die and the second die on the first side of the package substrate, to fill a gap between the dies and the package substrate, e.g., through a capillary dispense process.

At614, solder balls may be attached or formed on a second side of the package substrate opposing to the first side, e.g., through a surface mounting or thermal compression bonding process. The structure formed at614may be similar to the the device200,300ofFIGS.2and3Aabove, and accordingly the device200,300may be manufactured according to the processes ofFIG.6. The structure formed at614may be mounted onto a printed circuit board through the solder balls. Accordingly,FIG.6depicts a simplified process flow to assemble a multi-chip package with a deep-trench-capacitor bridge component according to various aspects of the present disclosure.

Aspects of the present disclosure may be implemented into a system using any suitable hardware and/or software.FIG.7schematically illustrates a computing device700that may include a semiconductor package100,200,300,500as described herein, in accordance with some aspects. The computing device700may house a board such as a motherboard702. The motherboard702may include several components, including but not limited to a semiconductor package704, according to the present disclosure, and at least one communication chip706. The semiconductor package704, which may include a bridge with deep trench capacitors according to the present disclosure, may be physically and electrically coupled to the motherboard702. In some implementations, the at least one communication chip706may also be physically and electrically coupled to the motherboard702.

The communication chip706may enable wireless communications for the transfer of data to and from the computing device700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some aspects they might not. The communication chip706may implement any of several wireless standards or protocols, including but not limited to Institute for Electrical and Electronics Engineers (IEEE) standards including Wi-Fi (IEEE 502.11 family), IEEE 502.16 standards (e.g., IEEE 502.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra-mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 502.16 compatible BWA networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 502.16 standards.

The communication chip706may also operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip706may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip706may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip706may operate in accordance with other wireless protocols in other aspects.

The computing device700may include a plurality of communication chips706. For instance, a first communication chip706may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip706may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Examples

Example 1 may include a device, including a bridge substrate and a redistribution layer on a top surface of the bridge substrate. The bridge substrate may include a plurality of trenches extending vertically into the bridge substrate from a bottom surface of the bridge substrate, wherein each trench of the plurality of trenches may include a conductive filling; a conductive layer partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer; a plurality of first contact pads under the bottom surface of the bridge substrate and coupled to the conductive layer; and a plurality of second contact pads under the bottom surface of the bridge substrate and coupled to the conductive fillings of the plurality of trenches.

Example 2 may include the subject matter of Example 1, wherein the plurality of trenches may be configured spaced apart from the top surface of the bridge substrate.

Example 3 may include the subject matter of Example 1, wherein the plurality of trenches may extend vertically through the bridge substrate.

Example 4 may include the subject matter of any one of Example 1 to 3, wherein the conductive layer may further extend along the bottom surface of the bridge substrate and extend between the plurality of trenches, and wherein the dielectric layer may further extend along the conductive layer and extend between the plurality of trenches.

Example 5 may include the subject matter of any one of Example 1 to 4, wherein the dielectric layer may include a high-k material having a relative permittivity of 20-15000.

Example 6 may include the subject matter of any one of Example 1 to 5, wherein the plurality of first contact pads and the plurality of second contact pads may lie in a same plane under the bottom surface of the bridge substrate.

Example 7 may include the subject matter of any one of Example 1 to 6, wherein the conductive layer, the dielectric layer and the conductive fillings of the plurality of trenches may form an array of capacitors.

Example 8 may include the subject matter of any one of Example 1 to 7, wherein the conductive layer may be coupled to a reference voltage.

Example 9 may include the subject matter of any one of Example 1 to 8, wherein the plurality of trenches may be coupled to a power supply voltage.

Example 10 may include the subject matter of any one of Example 1 to 8, wherein the plurality of trenches may include a first group and a second group, wherein the first group of trenches may be coupled to a first power supply voltage, and wherein the second group of trenches may be coupled to a second power supply voltage different from the first power supply voltage.

Example 11 may include the subject matter of any one of Example 1 to 10, wherein the conductive layer and the plurality of trenches may be coupled to the redistribution layer.

Example 12 may include the subject matter of any one of Example 1 to 11, further including a package substrate, wherein the bridge substrate and the redistribution layer may be at least partially embedded in the package substrate.

Example 13 may include the subject matter of Example 12, wherein the conductive layer and the plurality of trenches may be coupled to the package substrate through the plurality of first contact pads and the plurality of second contact pads, respectively.

Example 14 may include the subject matter of Example 12 or 13, further comprising a first die and a second die on the package substrate, wherein the bridge substrate and the redistribution layer may form an embedded multi-die interconnect bridge, and wherein the first die and the second die may be coupled through the redistribution layer.

Example 15 may include the subject matter of Example 14, wherein the conductive layer may be coupled to the first die and the second die through the plurality of first contact pads, and wherein each of the plurality of trenches may be coupled to at least one of the first die or the second die through a respective one of the plurality of second contact pads.

Example 16 may include the subject matter of Example 14 or 15, wherein the conductive layer and each of the plurality of trenches may be coupled to at least one of the first die or the second die through the redistribution layer.

Example 17 may include a method of forming a device, the method including providing a bridge substrate and a redistribution layer under a bottom surface of the bridge substrate; forming a plurality of intermediate trenches vertically extending into the bridge substrate from a top surface of the bridge substrate; forming a conductive layer on inner walls of the plurality of intermediate trenches and forming a dielectric layer on the conductive layer; forming conductive fillings into the plurality of intermediate trenches, wherein the conductive fillings may be on the dielectric layer; and forming a plurality of first contact pads and a plurality of second contact pads on the top surface of the bridge substrate, wherein the plurality of first contact pads may be coupled to the conductive layer, and wherein the plurality of second contact pads may be coupled to the conductive fillings in the plurality of intermediate trenches.

Example 18 may include the subject matter of Example 17, further including at least partially embedding the bridge substrate and the redistribution layer in a package substrate, wherein the conductive layer and the conductive fillings may be coupled to the package substrate through the plurality of first contact pads and the plurality of second contact pads, respectively; and arranging a first die and a second die on the package substrate, wherein the first die and the second die may be coupled to the conductive layer through the plurality of first contact pads and each may be coupled to a respective one of the conductive fillings through a corresponding one of the plurality of second contact pads.

Example 19 may include a semiconductor package including a package substrate, a bridge at least partially embedded in the package substrate, a first die and a second die on the package substrate. The bridge may include a bridge substrate and a redistribution layer on a top surface of the bridge substrate. The bridge substrate may include a plurality of trenches extending vertically into the bridge substrate from a bottom surface of the bridge substrate, wherein each trench of the plurality of trenches may include a conductive filling; a conductive layer partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer; a plurality of first contact pads under the bottom surface of the bridge substrate and coupled to the conductive layer; and a plurality of second contact pads under the bottom surface of the bridge substrate and coupled to the plurality of trenches. The first die and the second die may be coupled to the conductive layer through the plurality of first contact pads. The first die may be coupled to at least a respective one of the plurality of trenches through a corresponding one of the plurality of second contact pads. The second die may be coupled to at least an other respective one of the plurality of trenches through an other corresponding one of the plurality of second contact pads.

Example 20 may include the subject matter of Example 19, wherein the first die and the second die may overlie both the package substrate and the bridge.

In a further example, any one or more of examples 1 to 20 may be combined.

These and other advantages and features of the aspects herein disclosed will be apparent through reference to the above description and the accompanying drawings. Furthermore, it is to be understood that the features of the various aspects described herein are not mutually exclusive and can exist in various combinations and permutations.

It will be understood that any property described herein for a specific device may also hold for any device described herein. It will also be understood that any property described herein for a specific method may hold for any of the methods described herein. Furthermore, it will be understood that for any device or method described herein, not necessarily all the components or operations described will be enclosed in the device or method, but only some (but not all) components or operations may be enclosed.

The term “comprising” shall be understood to have a broad meaning similar to the term “including” and will be understood to imply the inclusion of a stated integer or operation or group of integers or operations but not the exclusion of any other integer or operation or group of integers or operations. This definition also applies to variations on the term “comprising” such as “comprise” and “comprises”.

The term “coupled” (or “connected”) herein may be understood as electrically coupled or as mechanically coupled, e.g., attached or fixed or attached, or just in contact without any fixation, and it will be understood that both direct coupling or indirect coupling (in other words: coupling without direct contact) may be provided.

While the present disclosure has been particularly shown and described with reference to specific aspects, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the present disclosure as defined by the appended claims. The scope of the present disclosure is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.