Scalable dielectric

An interpoly dielectric is formed using only a single layer of oxide and a single layer of nitride to allow a reduction in thickness. The nitride is thermally grown on silicon in a nitrogen environment to maintain a high quality layer, while the oxide is deposited by LPCVD.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others. 
 First embodiment: Oxide Over Nitride One method of forming the disclosed dielectric in processing a FLASH array will now be discussed. There are many methods of forming such an array, and it is to be understood that the disclosed dielectric layer can be used on many variations on this process. Nor is this process meant to be an exhaustive discussion of the process of forming a FLASH array, as many steps are conventional and do not need to be discussed in detail. For instance, doping of the semiconductor regions is not discussed, although it is an important part of the process flow. FIG. 1A shows a cross-section of a chip on which an exemplary FLASH array is being formed. A number of steps have already been performed. Tunnel oxide 110 is formed on the surface of the silicon wafer 100 . A layer of polysilicon 120 is deposited, masked, and etched to form the floating gates. It is at this point that the disclosed interpoly dielectric is formed, as shown in FIG. 1B . It has been found to be difficult to deposit nitride by LPCVD to significantly less than 60 &angst; without defects. For that reason, the nitride film should not be LPCVD-deposited. Rather, in the presently preferred embodiment, thermal nitride 130 is grown directly on the surface of the polysilicon 120 by rapid thermal nitridation (RTP), using a furnace and a nitrogen atmosphere. In the presently preferred embodiment, a temperature of 1150° C. is used for 10 seconds to produce a silicon nitride layer 20-30 &angst; thick. After the nitride layer is formed, a layer of oxide 140 is then deposited by LPCVD to a thickness of about 100 &angst;. This is somewhat thicker than the oxide layer in the ONO dielectric, but less than the two layers of oxide together. Overall, the dielectric thickness is reduced from about 180 &angst; to 120-130 &angst;. Once the disclosed dielectric is completed, a subsequent layer of polysilicon 150 can be deposited and etched to form the control gate. Additional dielectric layers and contacts to the transistors are formed. 
 Alternate Embodiment: Nitridation After Oxide Deposition In an alternative embodiment, the order in which the interpoly dielectric layers are formed is reversed, so that oxide layer 140 is first deposited by LPCVD over polysilicon layer 120 . This is followed by rapid thermal processing in a nitrogen environment, causing nitridation of the underlying polysilicon layer 120 by diffusion through the oxide layer 140 , forming nitride layer 130 . 
 Alternate Embodiment: Thermal Nitridation Before Floating Gate Etched The thermal nitridation step can also be done after the first polysilicon layer is deposited, but before it is etched, seen in Figure 2. However, this method is less desirable, as it does not achieve capacitances as high as the method above. 
 Alternate Embodiment: HSG Polysilicon In a further alternate embodiment, the polysilicon layers can be hemispherical grain (HSG) polysilicon to increase the capacitance two to three times. According to a disclosed class of innovative embodiments, there is provided: An integrated circuit structure, comprising: a first layer of silicon and a second layer of silicon, said first and second layers of silicon being separated, in at least some areas, only by a dielectric layer; wherein said dielectric layer consists only of a single layer of oxide arid a single layer of nitride. According to another disclosed class of innovative embodiments, there is provided: A FLASH memory integrated circuit structure, comprising: a floating gate; a control gate at least partially overlying said floating gate; wherein said floating gate and said control gate are separated solely by a dielectric layer consisting of a single layer of oxide and a single layer of nitride. According to another disclosed class of innovative embodiments, there is provided: A fabrication method, comprising the steps of: forming a first layer of silicon at least partially overlying a substantially monolithic body of semiconductor material; forming a layer of nitride at least partially overlying said first layer of silicon; forming a layer of oxide at least partially overlying said first layer of silicon; after said steps of forming said layer of nitride and forming said layer of oxide, but prior to performing any other steps, forming a second layer of silicon at least partially overlying said layer of oxide, said layer of nitride, and said first layer of silicon; wherein only two layers are present between said first layer of silicon and said second layer of silicon. 
 Modifications and Variations As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given, but is only defined by the issued claims. For example, if defect levels can be corrected, LPCVD nitride can be an acceptable alternative to growing silicon nitride. For another example, while the specification refers to polysilicon, this dielectric layer can also be formed between two layers containing monocrystalline silicon, polysilicon, or amorphous silicon, or any combination of these layers.