Real time digital reception focusing method and apparatus adopting the same

A real time digital reception focusing apparatus calculates a focusing delay time using information on the center of array transducing element, a corresponding transducing element and a scan line. The focusing delay time with respect to each transducing element is calculated by each transducing element. To calculate the focusing delay time on a real time basis, first coefficient signals output from a plurality of coefficient generators which are disposed in parallel are input to a first multiplexer. The first multiplexer selects one among the first coefficient signals according to a select control signal corresponding to a present decision variable signal. The decision variable signal with respect to the present focal point output from the decision variable generator is used for generation of a decision variable signal in the next focal point. A sampling clock generator calculates an integer focusing delay time for the next focal point and generates a sampling clock in a sampling interval using the integer focusing delay time obtained by the above calculation. Thus, it is possible to design the digital reception focusing apparatus using a simple hardware to enable a real time focusing operation. The digital focusing apparatus can be applied to a beam focusing system as well as an ultrasound reception focusing apparatus using an array transducer.

TECHNICAL FIELD 
The present invention relates to a method for focusing a reception signal 
which is reflected from an object and an apparatus adopting the same, and 
more particularly to a real time processing method of digital reception 
focusing in an ultrasound imaging system or beam focusing system which 
uses an array transducer, and an apparatus adopting the same. 
BACKGROUND ART 
In the field of a modern medical science, ultrasound diagnosis has been 
well advanced and became a general, essential diagnostic technology. Such 
ultrasound diagnostic equipment becomes digitized and integrated due to an 
engineering technological development on its design and implementation, 
thereby accomplishing compactness, light and high efficiency. To improve 
lateral resolution which is a crucial factor among performances of the 
ultrasound diagnostic equipment, a method of focusing transmission and 
reception waves by using an array transducer is widely used. Particularly, 
a reception focusing portion which is used in focusing a reception wave is 
very complex, so that a number of researches on performance improvement 
has been progressed. Such researches are shown in the following references 
entitled: 1! "Ultrasound Phased Array Delay Lines Based on Quadrature 
Sampling Techniques" by J. E. Powers, D. J. Phillips, M. A. Brandestini 
and R. A. Sigelmann disclosed in IEEE Trans. Son. Ultrason., vol. SU-27, 
no. 6, pp. 287-294, 1980; 2! "Delay Quantization Error in Phased Array 
Images" by P. A. Maginin, O. T. Von Ramm and F. L. Thurstone disclosed in 
IEEE Trans. Son. Ultrason., vol. SU-28, no. 5, pp. 305-310, 1981; 3! 
"Beam Steering with Linear Arrays" by O. T. Von Ramm and S. W. Smith 
disclosed in IEEE Trans. Son. Biomed. Eng., vol. BME-30, no. 8, pp. 
438-452, 1983; and 4! "Synchronous Dynamic Focusing for Ultrasound 
Imaging" by G. Manes, P. Tortoli, F. Andreuccetti, G. Avitabile and C. 
Atzeni disclosed in IEEE Trans. UFFC. vol. 35, no. 1, pp. 14-21, 1988. The 
reception focusing portion should be made of an integrated circuit (IC) to 
achieve compactness and high efficiency. A number of researches for 
digitizing the reception focusing portion are shown in the following 
references entitled: 5! "Pipelined Sampled-Delay Focusing in Ultrasound 
Imaging Systems" by J. H. Kim, T. K. Song and S. B. Park disclosed in IEEE 
Trans. Ultrason. Imag., vol. 9, pp. 75-91, 1987; and 6! "A New Digital 
Phased Array System for Dynamic Focusing and Steering with Reduced 
Sampling Rate" by T. K. Song and S. B. Park disclosed in IEEE Trans. 
Ultrason. Imag., vol. 12, pp. 1-16, 1990. 
As presented in the above reference 6!, the essential elements of a 
digital reception focusing portion are a digital delay device, a digital 
full-adder, a sampling clock generator, etc. Among them, the sampling 
clock generator is generally comprised of a large-capacity, high-speed 
look-up table (LUT) memory in the form of a read-only-memory (ROM). Thus, 
it has been very difficult in implementing all three portions such as a 
digital delay device, a digital full-adder, and a sampling clock generator 
into an application specific integrated circuit (ASIC). 
DISCLOSURE OF INVENTION 
Therefore, to solve the above problems, it is an object of the present 
invention to provide a new method and apparatus for calculating focusing 
delay on a real time basis with a sufficient accuracy via a simple 
hardware implementation without using a look-up table memory as a sampling 
clock generator. 
To accomplish the above object of the present invention, there is provided 
a real time digital reception focusing method for sampling a signal having 
image information on an object received via an array transducer having a 
plurality of transducing elements and for performing a digital reception 
focusing of the sample image information, the real time digital reception 
focusing method comprising the steps of: 
establishing an integer focusing reference distance and an integer focusing 
delay distance with respect to each of the transducing elements so that a 
rate of change of the focusing delay distance with respect to the focusing 
reference distance when a focal point is altered is within a predetermined 
boundary; 
updating the integer focusing reference distance and the integer focusing 
delay distance with respect to a second focal point according to a 
magnitude of a decision variable with respect to a first focusing point 
and coefficients for calculating the decision variable; and 
generating a sampling clock for focusing a signal having the image 
information input to each of the transducing elements into the second 
focal point, by a sampling interval corresponding to the updated integer 
focusing delay distance. 
The above object can be also accomplished by providing a real time digital 
reception focusing apparatus for sampling a signal having image 
information on an object received via an array transducer having a 
plurality of transducing elements and for performing a digital reception 
focusing of the sample image information, the real time digital reception 
focusing apparatus comprising: 
means for generating a first coefficient signal in the form of an integer 
which is used for generating a decision variable signal; 
means for receiving the first coefficient signal generated from the 
coefficient signal generation means and generating the decision variable 
signal; and 
means for receiving the decision variable signal, calculating an integer 
focusing delay distance according to a magnitude of the decision variable 
signal, and generating a sampling clock by a sampling interval 
corresponding to the integer focusing delay distance. 
Preferably, the apparatus according to the present invention can be 
embodied by comprising registers, adders, comparators and multiplexers.

BEST MODE FOR CARRYING OUT THE INVENTION 
Hereinbelow, methods and apparatuses for real time focusing ultrasound 
images according to the preferred embodiments of the present invention 
will be described in detail with reference to the accompanying drawings. 
A real time digital reception focusing method according to the present 
invention has been developed on the basis of a midpoint algorithm which is 
disclosed in a reference 7! entitled "An Efficient Ellips-Drawing 
Algorithm" by J. R. Van Aken disclosed in IEEE J. of Computer Graphics and 
Application, vol. 4, no. 9, pp. 24-35, 1984. 
FIG. 1 is a geometrically conceptual diagram for determining focusing delay 
of a phased array. An array transducer 1 has a one-dimensional linear 
arrangement. Each array elements 1A are arranged by a predetermined 
interval along a horizontal axis. The center of array transducer 1 is 
located at the origin "O." A symbol x is a horizontal coordinate at the 
center of an array element, .theta. is a steering angle which is generally 
zero in case of a linear array, r is a focusing reference distance which 
is a distance between a midpoint of an array element and a focal point P, 
and l is a real focusing delay distance. When an ultrasound passes through 
a homogeneous undamped medium, a focusing delay time of an array element 
is represented as the time taken when the ultrasound travels along a 
distance l expressed as the following equation (1), as an example of FIG. 
1. 
EQU l=(r.sup.2 +.alpha.r+.beta.).sup.1/2 -r (1) 
In the above equation, .alpha.=2x sin .theta. and .beta.=x.sup.2. In the 
equation (1), r is varied according to a scan line (line OP of FIG. 1), 
.theta. is invariable with respect to the scan line, and x is constant 
with respect to a given array element. Thus, if a real number l can be 
obtained so that the equation (1) is satisfied with real number l 
depending on a given r, a focusing delay time is calculated to generate a 
sampling clock. However, in reality, calculation of a focusing delay time 
using equation (1) is not processed on a real time basis because of a time 
consumed for operations of a multiplication and a square root. 
Therefore, the present invention proposes an algorithm which adopts an 
application of a midpoint algorithm of reference 7! and uses an addition 
operation of integers, to calculate a focusing delay time. First, r is 
moved from the right term to the left term and both terms are squared, the 
result from which is a function f(r, l) expressed as equation (2). 
EQU f(r, l)=l.sup.2 +2lr-.alpha.r-.beta.=0 (2) 
The present invention proposes an algorithm for rapidly calculating an 
approximate value of l according to r by using an algorithm which is used 
for a computer graphic based on the fact that equation (2) derived from 
equation (1) is a two-order equation with respect to r and l. Hereinbelow, 
several algorithms are proposed to locate an integer i which is closest to 
real number l which satisfies equation (2) when a focal point r increases 
discretely at a predetermined interval based on a midpoint algorithm. 
However, real number l cannot satisfies equation (1). Thus, r and l are 
set to satisfy equation (1) as an initial condition of the proposed 
algorithm. The function f(r, l) should satisfy the following conditions 1) 
and 2). 
Condition 1): All coefficients and r's in equation (1) are integer. 
Condition 2): r and l satisfies the following equation (3). 
##EQU1## 
The above condition 1) is satisfied so that the center frequency of a 
sampling clock is adjusted to make the center of each array element have a 
coordinate value of an integer, if steering angle .theta. is 0. However, 
When condition 1) is not met by adjustment of the center frequency in the 
sampling clock, the coefficient values are slightly truncated. As can be 
seen from a later description, an error between the coefficient values 
generated in this case is so small that an influence on the decision of 
the coefficient can be ignored. The condition 2) is met when the 
geometrical relationships of the steering angle .theta., focal point P and 
array element 1A are appropriate, as shown in FIG. 1. 
FIG. 2 is a conceptual graph for explaining a proposed algorithm according 
to an aspect of the present invention. Four circles shown in FIG. 2 
represent a relationship between focusing reference distance r and integer 
focusing delay distance i, respectively. The circle selected by an 
algorithm which will be described later has focusing reference distance r 
and integer focusing delay distance i with respect to the focal point. The 
integer focusing delay distance i is used for generation of a sampling 
clock with respect to a particular focal point. An algorithm proposed to 
calculate a focusing delay time with respect to each focal point in an 
ultrasound image system will be described as follows. 
First, it is assumed that an integer which is closest to real focusing 
delay distance l.sub.n obtained from equation (1) by n-th focusing 
reference distance r.sub.n is an integer focusing delay distance i.sub.n. 
If r.sub.n and i.sub.n are given as initial conditions satisfying that 
r.sub.n+1 =r.sub.n +1, it is possible to obtain an equation i.sub.n+1 
=i.sub.n or i.sub.n+1 =i.sub.n -1 by condition 2). Thus, integer focusing 
delay distance i.sub.n+1 with respect to (n+1)-th focal point is 
determined as one of i.sub.n or i.sub.n -1 according to a first decision 
variable d.sub.n defined by following equation (4). 
##EQU2## 
The first decision variable d.sub.n of equation (4) is obtained by 
multiplying equation (2) by four to represent a resulting value of 
equation (2) at the midpoint of possible two points (r.sub.n+1, i.sub.n) 
and r.sub.n+1, i.sub.n -1) with respect to r.sub.n+1. As shown in FIG. 2, 
when first decision variable d.sub.n is greater than zero, since i.sub.n+1 
is closer to i.sub.n-1 than i.sub.n, integer focusing delay distance 
i.sub.n+1 is updated into i.sub.n-1. In the reverse case, i.sub.n+1 is 
updated into i.sub.n. If d.sub.n =0, since each distance between i.sub.n+1 
and i.sub.n or i.sub.n-1 is identical to each other, i.sub.n+1 can be any 
one of two. In such a manner, integer focusing delay distance i.sub.n can 
be calculated from focusing reference distance r.sub.n which progressively 
increases. However, although calculation of integer focusing delay 
distance i.sub.n using equation (4) is slightly more efficient than that 
using equation (1), such a calculation still includes the multiplication 
operations, requiring much calculation time and amount. Thus, to avoid a 
direct calculation of integer focusing delay distance i.sub.n via equation 
(4), first decision variable d.sub.n is modified by the following 
equations (5a) and (5b) when an initial value d.sub.0 is given. 
##EQU3## 
Therefore, when initial values r.sub.0, i.sub.0 and d.sub.0 are given, 
integer focusing delay distance i.sub.n corresponding to r.sub.n in which 
n is positive integers, is calculated using the above equations (5a) and 
(5b). A basic pattern of the algorithm proposed in the present invention 
as described above is expressed as follows. 
##EQU4## 
FIG. 3 is block diagram showing an apparatus embodying the algorithm 1 
according to an embodiment of the present invention. In FIG. 3, a 
coefficient generator 10 includes a register 11 for storing a coefficient 
C1 shown in algorithm 1, a register 12 for storing a coefficient C2 shown 
in algorithm 1, and a multiplexer 13 for selectively outputting signals 
output from registers 11 and 12. Both signal outputs of a down-counter 14 
for down-counting an initial value i.sub.0 of the integer focusing delay 
distance and an up-counter 15 for up-counting an initial value r.sub.0 of 
the focusing reference distance whenever a sampling clock is generated, 
are connected to signal inputs of a multiplexer 16, respectively. A 
multiplier 17 multiplies the output signal of multiplexer 16 by 8 or -8 
according to the signal output from a register 20 and outputs the 
multiplication result. An adder 18 adds the output signals of multiplier 
17 and multiplexer 13. An adder 19 adds the output signals of adder 18 and 
register 20, and applies the addition result to the input of register 20. 
Register 20 whose output is connected to a sampling clock generator 100 
stores initial value d.sub.0 of the first decision variable. Sampling 
clock generator 100 stores initial values (r.sub.0, i.sub.0) with respect 
to an initial focal point. Then, sampling clock generator 100 updates 
initial value (r.sub.0, i.sub.0) according to first decision variable data 
d.sub.n and generates a sampling clock according to the updated integer 
focusing delay distance. 
If the FIG. 3 apparatus starts to operate, sampling clock generator 100 
generates a sampling clock by using stored initial values r.sub.0 and 
i.sub.0. That is, sampling clock generator 100 generates the sampling 
clock which is delayed by integer focusing delay distance i.sub.0 with 
respect to the focal point focusing reference distance r.sub.0. Register 
20 outputs the stored initial value d.sub.0 to sampling clock generator 
100. The most significant bit (MSB) which is a sign bit of data d.sub.0 
output from register 20 represents information as to whether initial value 
d.sub.0 is larger than 0. When a value of the MSB being a sign bit of data 
d.sub.0 output from register 20 is in a low level, multiplexer 13 of 
coefficient generator 10 outputs coefficient value C2 supplied from 
register 12. Here, down-counter 14 receives initial value i.sub.0 
according to the MSB applied to an enable end E, and stores i.sub.0 -1 
which is obtained by down-counting the initial value. Up-counter 15 
receives initial value r.sub.0, and stores r.sub.0 +1 which is obtained by 
up-counting the initial value. Multiplexer 16 outputs data i.sub.0 output 
from down-counter 14 to multiplier 17 according to the MSB. Multiplier 17 
multiplies the data output from multiplexer 16 by 8 or -8 according to the 
MSB applied from register 20 and outputs the multiplied result. That is, 
multiplier 17 multiplies the input data by 8 if the MSB data is in a high 
level, while the former multiplies the input data by -8 if the MSB data is 
in a low level. Adder 18 adds the output data from coefficient generator 
10 and multiplier 17. Thus, the output data from adder 18 becomes a value 
of -8.times.r+C2. Adder 19 adds data d.sub.0 stored in register 20 and the 
output data from adder 18. As a result, register 20 stores a value of 
d-8.times.r+C2. Sampling clock generator 100 receives the data stored in 
register 20 and compares the received data with 0 to determine whether the 
former is larger than the latter. Sampling clock generator 100 updates the 
stored integer focusing delay distance from i.sub.0 to i.sub.0 -1 if the 
data stored in register 20 is larger than 0, and generates a sampling 
clock delayed by a time corresponding to integer focusing delay distance 
i.sub.0 -1. If the data stored in register 20 is not more than 0, stored 
integer focusing delay distance i.sub.0 is maintained as it is, and 
generates a sampling clock delayed by a time corresponding to integer 
focusing delay distance i.sub.0. Such an integer focusing delay distance 
is calculated with respect to each n of focusing reference distance 
r.sub.n. 
Meanwhile, a unit distance is defined as a distance between adjacent two 
focal points, a system embodying algorithm 1 should update d once each 
time r increases by the unit distance. By the way, assuming that a period 
of time of the center frequency for the sampling clock is T, a time 
corresponding to an increase of r by the unit distance becomes 2T since an 
ultrasound reciprocates from an array element to a focal point. Thus, as 
an example when T=20 ns, since d should be updated every 40 ns, a system 
designed for low-speed calculation is burdened in hardware. Therefore, 
rather than calculating i with respect to all r's when r=n in which n is 
an integer not less than 0, a calculation amount becomes reduced into 1K 
when i can be calculated only when r=Kn in which K and n are natural 
numbers. However, condition 2) expressed as equation (3) should be 
modified into the following equation (6). 
##EQU5## 
If an aperture of an array transducer in an actual system can vary 
according to a value of r, equation (6) can be met with respect to a much 
larger value of K. In this case, the proposed algorithm is simply 
represented by substituting r with Kr. In the proposed algorithm, 
equations (2), (4), (5a) and (5b) are changed into the following equations 
(7), (8), (9a) and (9b). 
EQU f(r, l)=l.sup.2 +2lKr-.alpha.Kr-.beta.=0 (7) 
EQU d.sub.n =4l.sub.n.sup.2 +4l.sub.n (2K-1)+8Kr.sub.n l.sub.n 
-4K(1+.alpha.)r.sub.n -4K(1+.alpha.)-4.beta.+1+8 (8) 
EQU when d.sub.n .ltoreq.0, d.sub.n+1 =d.sub.n +8Ki.sub.n -4K(1+.alpha.) (9a) 
EQU when d.sub.n &gt;0, d.sub.n+1 =d.sub.n -8(1-K)i.sub.n -8Kr.sub.n 
-4K.alpha.-20K+8 (9b) 
Thus, the above-described algorithm 1 is generalized as the following 
algorithm 2. 
##EQU6## 
FIG. 4 is block diagram showing an apparatus embodying the algorithm 2 
according to another embodiment of the present invention. 
In FIG. 4, a coefficient generator 21 includes a register 22 for storing a 
coefficient C1 shown in algorithm 2, a register 23 for storing a 
coefficient C2 shown in algorithm 2, and a multiplexer 24 for selectively 
outputting signals output from registers 22 and 23. Multiplexer 24 outputs 
coefficients C1 and C2 according to the MSB of the data output from 
register 34. A down-counter 25 is enabled by the MSB of the data output 
from register 34 and down-counts an initial value i.sub.0 of the integer 
focusing delay distance. An up-counter 26 up-counts an initial value 
r.sub.0 of the focusing reference distance whenever the data is output to 
a sampling clock generator 200 from register 34. A multiplier 28 
multiplies the output signal of down-counter 25 by 8K and outputs the 
multiplication result 8.times.K.times.i. Here, calculation determination 
factor K is determined by a system designer. An adder 31 adds the output 
signals 8.times.K.times.i, -8.times.i and -8.times.K.times.r of 
multipliers 28, 29 and 30. Multiplexer 27 selectively outputs the output 
data 8.times.K.times.i of adder 28 and the output data 
8.times.K.times.i-8.times.i-8.times.K.times.r of adder 31 according to the 
output data of register 34. An adder 32 adds the output signals of 
multiplexers 24 and 27, and applies the addition result to an adder 33. 
Adder 33 adds the first decision variable data stored at the prior step in 
register 34 and the data applied from adder 32. 
A signal processing procedure of the FIG. 4 apparatus will be described 
below. When the first decision variable data output from register 34 is 
less than 0, sampling clock generator 200 calculates a focusing delay time 
by using a stored integer focusing delay distance and generates a sampling 
clock delayed according to a focusing delay time. Meanwhile, multiplexer 
24 outputs coefficient C1 to adder 32 by the MSB which is a select control 
signal from register 34. Multiplexer 27 outputs data 8.times.K.times.i 
generated in multiplier 28 to adder 32 according to the MSB information 
output from register 34. Adder 32 adds coefficient C1 and data 
8.times.K.times.i and outputs the added result to adder 33. Adder 33 adds 
the first decision variable data of the prior step stored in register 34 
and the data output from adder 32 to generate new first decision variable 
data. Register 34 stores the first decision variable data supplied from 
adder 33. The first decision variable data stored in register 34 is used 
for determination of the first decision variable data of the next step and 
generation of the sampling clock in sampling clock generator 200. Since 
the FIG. 4 apparatus embodying the algorithm 2 has more than two terms to 
be added in an addition operation, the former is disadvantageous in 
high-speed calculation. In this case, the above equations (9a) and (9b) 
can be altered for parallel operations as follows. 
EQU when d.sub.n .ltoreq.0, d.sub.n+1 =d.sub.n +A.sub.n (10a) 
EQU when d.sub.n &gt;0, d.sub.n+1 =d.sub.n +B.sub.n (10b) 
Here, A.sub.n and B.sub.n are expressed as follows. 
EQU A.sub.n =8Ki.sub.n -4K(1+.alpha.) (11a) 
EQU B.sub.n =-8(1-K)i.sub.n -8Kr.sub.n -4K.alpha.-20K+8 (11b) 
By this modification, A.sub.n+1 and B.sub.n+1 are calculated via the 
following equations (12a), (12b), (12c) and (12d) instead of using 
equations (11a) and (11b). 
##EQU7## 
Thus, if initial values A.sub.0 and B.sub.0 are further given, A.sub.n, 
B.sub.n, d.sub.n, r.sub.n, and i.sub.n can be obtained in sequence where 
n=0, 1, 2, . . . . A pattern for parallel operation of algorithm 2 is 
represented in the following algorithm 3. 
##EQU8## 
FIG. 5 is block diagram showing an apparatus embodying the algorithm 3 
according to still another embodiment of the present invention. 
In FIG. 5, a register 41 for storing a coefficient C1 shown in algorithm 3, 
and a register 42 for storing a coefficient C2 shown in algorithm 3 supply 
the outputs to a multiplexer 43, respectively. 
Multiplexer 43 selectively outputs one of the signals output from registers 
41 and 42, according to a select control signal, that is, the MSB of the 
data output from register 50. An adder 44 adds data C1 applied from 
register 41 and data A applied from register 46 and outputs the added 
result to register 46. Register 46 operates according to the select 
control signal output from register 50. An adder 45 adds data B applied 
from register 47 and data C1 or C2 applied from multiplexer 43 and outputs 
the added result to register 47. A multiplexer 48 receives data A output 
from register 46 and data B output from register 47, and selectively 
outputs either data A or B according to the select control signal output 
from register 50. An adder 49 adds data D output from register 50 and the 
data output from multiplexer 48 and outputs the added result to register 
50. A sampling clock generator 300 updates integer focusing delay distance 
i using first decision variable data D applied from register 50. Sampling 
clock generator 300 calculates a focusing delay time using an integer 
focusing delay distance and generates a sampling clock delayed according 
to the focusing delay time. 
A signal processing procedure of the FIG. 5 apparatus will be described 
below. When the first decision variable data D output from register 50 is 
larger than 0, multiplexer 43 outputs coefficient C2 to adder 45 according 
to a select control signal generated from register 50. Multiplexer 48 
outputs data B output from register 47 to adder 49. Adder 49 adds first 
decision variable data D output from register 50 and data B output from 
multiplexer 48. Thus, register 50 stores data D+B output from adder 49. 
The FIG. 5 apparatus embodying algorithm 3 is advantageous since all 
addition operations are accomplished by adding only two terms and each 
variable is independently updated by parallel operation. 
The algorithm 3 can be embodied by a high-speed hardware system, but has a 
limitation since only two sampling periods KT.DELTA. (K-1)T.DELTA. are 
generated. For example, when an aperture of an array transducer is very 
large and a value of K is very large, equation (6) cannot be met. 
Accordingly, an exact sampling cannot be performed using two sampling 
periods. As an example of such a case, a bandwidth sampling of the 
above-discussed reference 6! can be referred to. In this case, three 
sampling periods such as KT.DELTA., (K-1)T.DELTA. and (K-2)T.DELTA. can be 
calculated, to greatly relax a condition of the equation (6). Hereinbelow, 
an algorithm for obtaining two sampling periods is proposed. 
FIGS. 6A and 6B are conceptual views for explaining another proposed 
algorithm for calculating focusing delay to generate three sampling 
periods according to another aspect of the present invention. In FIGS. 6A 
and 6B, each point represents a position for obtaining image information 
to be represented on a screen as in FIG. 2. The above described algorithms 
1-3 comparatively directly employ the midpoint algorithm, while this 
algorithm is further extended from algorithms 1-3 to obtain three sampling 
periods. To obtain three sampling periods KT.DELTA., (K-1)T.DELTA. and 
(K-2)T.DELTA., a position (r, i) which is the closest to a value of 
function f(r, l)=0 is determined as one among three points (r.sub.n+1, 
i.sub.n), (r.sub.n+1, i.sub.n -1), and (r.sub.n+1, i.sub.n -2), 
considering a sign and value of d.sub.n. Two points (r.sub.n+1, i.sub.n) 
and (r.sub.n+1, i.sub.n -1) are identical to the points used in algorithms 
1-3. The point (r.sub.n+1, i.sub.n -2) is newly added to obtain three 
sampling periods. Given initial point (r.sub.0, i.sub.0), the next 
position becomes (r.sub.n+1, i.sub.n) when d.sub.n &lt;0. Meanwhile, the next 
position becomes one of (r.sub.n+1, i.sub.n -1) and (r.sub.n+1, i.sub.n 
-2) according to a value of d.sub.n when d.sub.n .gtoreq.0 as can be seen 
from FIG. 6A. Thus, a second decision variable u.sub.n which equals 
4.multidot.f(r.sub.n+1, i.sub.n -3) is newly defined to select one among 
three points. From a characteristic of function f(r, l), if a value 
satisfying function f(r, l)=0 passes a point P.sub.n which equals 
(r.sub.n+1, i.sub.n -3/2), second decision variable u.sub.n becomes 0. If 
a value satisfying function f(r, l)=0 passes below a point P.sub.n, second 
decision variable u.sub.n becomes positive. If a value satisfying function 
f(r, l)=0 passes over a point P.sub.n, second decision variable u.sub.n 
becomes negative. A relationship between such decision variables u.sub.n 
and d.sub.n follows equation (13) 
EQU u.sub.n +8L.sub.n -8=d.sub.n (13) 
Here, L.sub.n =i.sub.n +Kr.sub.n +K. From equation (13) and function f(r, 
l), the following relationship 1 is obtained. 
Relationship 1: 
(a) If a value satisfying f(r, l)=0 passes in the neighbourhood of a point 
(r.sub.n+1, i.sub.n), then d.sub.n &lt;0; 
(b) If a value satisfying f(r, l)=0 passes in the neighbourhood of a point 
(r.sub.n+1, i.sub.n -1) while not in the case of (a), then 
0.ltoreq.d.sub.n .ltoreq.8L.sub.n -8; and 
(c) If a value satisfying f(r, l)=0 passes in the neighbourhood of a point 
(r.sub.n+1, i.sub.n -2) while not in the cases of (a) and (b), then 
d.sub.n &gt;8L.sub.n -8. 
If the sign and value of first decision variable d.sub.n are used in the 
above relationship 1, a point closest to a value satisfying equation f(r, 
l)=0 can be determined. If 8L.sub.n -8 is defined as a comparison 
reference value T.sub.n which is calculated again by the value of the 
prior step, T.sub.n is compared with d.sub.n with respect to all n-th 
steps. The resultant new focusing delay calculation algorithm is as 
follows. 
##EQU9## 
Since calculation of d.sub.n according to algorithm 4 includes at least two 
times addition operations, a speed of the calculation is lowered. Thus, as 
in the above algorithm 2, the algorithm 4 is restructured and paralleled 
by the following method. First, to simplify the calculation of d.sub.n, if 
it is defined that A.sub.n =8Ki.sub.n -4K(1+.alpha.), B.sub.n 
=-8(1-K)i.sub.n -8Kr.sub.n -4K.alpha.-20K+8, and C.sub.n =-8(2-K)i.sub.n 
-16Kr.sub.n -4K.alpha.-36K+24 the following relationship 2 is established. 
Relationship 2: 
(a) If d.sub.n &lt;0, then d.sub.n+1 =d.sub.n +A.sub.n, 
(b) If 0.ltoreq.d.sub.n .ltoreq.8L.sub.n -8 while not in the case of (a), 
then d.sub.n+1 =d.sub.n +B.sub.n' ; and 
(c) If d.sub.n &gt;8L.sub.n -8 while not in the cases of (a) and (b), then 
d.sub.n+1 =d.sub.n +C.sub.n. 
If initial values A.sub.0, B.sub.0 and C.sub.0 of the addition operation 
are given, A.sub.n, B.sub.n and C.sub.n are not directly calculated, but 
updated by the following relationship 3 using the corresponding values of 
the prior step. 
##EQU10## 
FIG. 7 is block diagram showing an apparatus embodying the algorithm 5 
according to yet another embodiment of the present invention, which will 
be described later. Meanwhile, first decision variable d.sub.n has the 
largest value among values of various variables in the above algorithms. 
With respect to l.sub.z satisfying that f(r.sub.n+1, l.sub.z)=0, an 
integer i.sub.n which is the closest to l.sub.z is represented as the 
following expression (14). 
EQU i.sub.n =l.sub.z +.DELTA., .vertline..DELTA..vertline..ltoreq.1 (14) 
From equations (8) and (14), 
##EQU11## 
In equation (15), since r&gt;&gt;l.sub.z, r&gt;&gt;.vertline..DELTA..vertline. mostly, 
EQU d.sub.n .congruent.8.DELTA.Kr.sub.n (16) 
Here, since r.sub.n is obtained by multiplying n by K, Kr in equation (16) 
is replaced by r on the same scale as l in the algorithm 2. If a speed of 
the ultrasound is 1,480 m/sec and a temporal precision of the sampling 
clock is 20 ns, the unit distance is 29.6 .mu.m. Accordingly, assuming 
that the maximum value is 20 cm, the maximum value d.sub.max of d.sub.n is 
approximately 54,054. To represent d.sub.max into a binary number, about 
sixteen bits are required. Also, considering that all coefficients are 
multiplied by a constant to reduce a coefficient truncation error. the 
system uses about nineteen bits as a proper word length in the most of the 
actual case. 
Returning to the above algorithm 1, when the linear array transducer is 
used, conditions 1) and 2) are well met, i.sub.n is accurately calculated. 
However, when the phased array transducer is used, condition 2) is 
satisfied by a proper variation of r, but condition 1) is not satisfied 
even with the variation. Thus, .alpha. and .beta. in equation (1) are 
inevitably truncated. Here, the generated truncation error is reviewed 
below. When a coefficient is truncated, equation (1) is expressed as the 
following equation (17). 
EQU l.sub.e =(r.sup.2 +(.alpha.+e.sub.1)r+(.beta.+e.sub.2)).sup.0.5 -r (17) 
Here, l.sub.e is a real number having the relationship in which l.sub.e 
=l+e.sub.0, and represents l which is influenced by the truncation. The 
e.sub.1 and e.sub.2 represent truncation errors which satisfy expressions 
.vertline.e.sub.1 .vertline.&lt;0.5 and .vertline.e.sub.2 .vertline.&lt;0.5, 
respectively. From equations (1) and (17), the following equation (18) is 
obtained. 
EQU e.sub.0.sup.2 +2(1+r)e.sub.0 -e.sub.1 r-e.sub.2 =0 (18) 
From the roots of equation (18), the following equation (19) can be 
obtained. 
EQU e.sub.0 =-(1+r).+-.(1+r).sup.2 +e.sub.1 r+e.sub.2).sup.0.5 (19) 
The sign ".+-." in equation (19) is replaced by sign "+" since e.sub.0 =0 
when e.sub.1 =e.sub.2 =0 from equations (1) and (17). First, when e.sub.1 
&gt;0 and e.sub.2 &gt;0, if x.gtoreq.0, then (1+x).sup.0.5 .ltoreq.x+1. Thus, 
from equation (19), the following equation (20) can be obtained. 
##EQU12## 
Using the fact (1+x).sup.0.5 .gtoreq.x+1 under the condition, 
-1.ltoreq.x.ltoreq.0, equation (20) is extended as the following equation 
(21). 
##EQU13## 
In actuality, since 1+r.apprxeq.r in most cases, e.sub.0 is expressed as 
the following equation (22). 
##EQU14## 
However, such an error is not well observed. If such an error is not 
acceptable, all the coefficients are multiplied by a proper constant and 
then the multiplied results are truncated to reduce a truncation error, so 
that a sufficient precision can be obtained. The transducers of a convex 
array, a concave array, an annular array and a two-dimensional array are 
similar to the phased array transducer in view of the geometrical 
structure of reception focusing. Also, the above-described algorithm of 
the present invention calculates the focusing delay time using the 
information on the center of the array transducer, the corresponding array 
element and the scan line. Accordingly, the algorithm according to the 
present invention can be applied to a general beam focusing using the 
array transducer having various types as well as the ultrasound reception 
focusing. 
FIG. 7 is a block diagram of an apparatus embodying algorithm 5, by using 
registers, multiplexers and comparators. FIG. 7 shows algorithm 5 for 
generating a sampling clock with respect to a single transducer element. 
The FIG. 7 apparatus embodying the present invention includes coefficient 
generators 60, 70 and 80 having the same structure, respectively. The 
signal output ends of coefficient generators 60, 70 and 80 are connected 
to a multiplexer 88. The output signal of multiplexer 88 is supplied to 
decision variable generator 90 which generates a decision variable signal 
d.sub.n. A comparison reference value generator 93 generates a comparison 
reference signal T.sub.n which is compared with first decision variable 
d.sub.n and supplies the generated signal to a sampling clock generator 
400. A comparator 110 compares decision variable signal d.sub.n with the 
comparison reference signal T.sub.n and supplies the comparison resulting 
signal C.sub.out to a selection controller 120. Selection controller 120 
receives the output signal of comparator 110 and supplies the select 
control signal to multiplexers 64, 74, 84, 88 and 97. Sampling clock 
generator 400 receives decision variable signal d.sub.n and comparison 
reference signal T.sub.n and generates a sampling clock signal. 
Coefficient generators 60, 70 and 80 and comparison reference value 
generator 93 includes registers which are designed so that coefficients 
N1-N7 shown in the algorithm 5 are output. The coefficients used in 
algorithm 5 are labelled in the respective register blocks. First 
coefficient generator 60 includes a register 61 for generating a signal 
being a signal value of "0," a register 62 which is designed according to 
coefficient N1, and a register 63 of coefficient N3. The signal output 
ends of registers 61, 62 and 63 are connected to multiplexer 64. The 
signal output end of adder 65 is connected to latch 66, and adds the 
output signals of latch 66 and multiplexer 64. Second coefficient 
generator 70 includes a register 71 which is designed according to 
coefficient N1, a register 72 of coefficient N2 and a register 73 of 
coefficient N4. Second multiplexer 74 are connected to receive the output 
signals of registers 71, 72 and 73. Third coefficient generator 80 
includes a register 81 of coefficient N3, a register 82 of coefficient N4 
and a register 83 of coefficient N5. Third multiplexer 84 are connected to 
receive the output signals of registers 81, 82 and 83. Second and third 
coefficient generators 70 and 80 include adders 75 and 85 and latches 76 
and 86 which are disposed in the same manner as those of first coefficient 
generator 60, respectively. Decision variable generator 90 includes an 
adder 91 of which the signal output end is connected to latch 92 and adds 
the output signals of latch 92 and multiplexer 88. Comparison reference 
value generator 93 includes registers 94, 95 and 96, multiplexer 97, adder 
98 and latch 99 which are disposed in the same manner as those of 
coefficient generators 60, 70 and 80. 
First, if decision variable generator 90 outputs a decision variable signal 
d.sub.n of the n-th step and comparison reference value generator 93 
outputs the stored comparison signal T.sub.n, respectively, comparator 110 
compares two signals d.sub.n and T.sub.n and generates comparison 
resulting signal C.sub.out to be output to selection controller 120. 
Selection controller 120 generates a select control signal corresponding 
to comparison resulting signal C.sub.out according to the above-described 
relationship 3. Each of multiplexers 64, 74 and 84 in coefficient 
generators 60, 70 and 80 selects one among the signals supplied from the 
registers according to the input select control signal. For example, if 
the n-th decision variable signal d.sub.n satisfies the condition where 
d.sub.n &lt;0, multiplexer 64 outputs the signal supplied from register 61, 
multiplexer 74 outputs the signal supplied from register 71, and 
multiplexer 84 outputs the signal supplied from register 81. Adder 65 adds 
the output signal of second multiplexer 64 and signal A.sub.n stored in 
latch 66, that is, the signal obtained by the n-th operation. Latch 66 
outputs stored signal A.sub.n and stores a new signal A.sub.n+1 supplied 
from adder 65. Since the adders and the latches in second and third 
coefficient generators 70 and 80 operate in the same manner as that of 
first coefficient generator 60, the detailed description thereof will be 
omitted. 
Multiplexer 88 selectively outputs signals A.sub.n, B.sub.n and C.sub.n 
output from coefficient generators 60, 70 and 80. When d.sub.n &lt;0, 
multiplexer 88 outputs the signal A.sub.n supplied from latch 66 according 
to the above-described relationship 2. Adder 91 adds the output signal 
d.sub.n of latch 92 and signal A.sub.n. Latch 92 stores a new signal 
d.sub.n+1 therein. Multiplexer 97 in comparison reference value generator 
93 supplies the output signal of register 94 to adder 98 according to 
algorithm 5 when d.sub.n &lt;0. If adder 98 adds comparison reference signal 
T.sub.n of latch 99 and the output signal of multiplexer 97 and outputs 
the added result, latch 99 stores a new signal T.sub.n+1 therein. Signals 
d.sub.n+1 and T.sub.n+1 stored in decision variable generator 90 and 
comparison reference value generator 93 are used in generation of the 
select control signal at the next stage and calculation of the focusing 
delay time at the next stage to be described below. 
Coefficient generators 60, 70 and 80 and sampling clock generator 400 store 
a plurality of initial values which are used in calculation of the 
focusing delay distance signal. Such initial values have integer values 
via truncation according to the pattern of the applied transducers, which 
are A.sub.0, B.sub.0, C.sub.0, r.sub.0 and i.sub.0 described in algorithm 
5. Sampling clock generator 400 receives comparison reference signal 
T.sub.n and decision variable signal d.sub.n, compares the magnitudes 
thereof, and updates the stored integer focusing delay distance signal 
i.sub.n and focusing reference distance signal r.sub.n according to the 
comparison result. Sampling clock generator 400 uses a newly obtained 
(n+1)-th integer focusing delay distance signal i.sub.n+1 to calculate an 
integer focusing delay time signal. Also, sampling clock generator 400 
uses the integer focusing delay time signal to generate a sampling clock 
signal corresponding to each array element. That is, sampling clock 
generator 400 generates a sampling clock with respect to (n+1)-th focusing 
point in the sampling interval of the integer focusing delay time 
interval. 
As described above in connection with equation (2), various algorithms 
proposed in the present invention employs the simplest midpoint algorithm 
illustratively based on the fact that a second order equation is 
established between a focal length and a focusing delay distance l. It is 
apparent that the other drawing algorithms can be applied to the present 
invention. Also, since the circuitry embodying the proposed algorithm is 
only illustrative, it is apparent that various modifications can be 
possible. 
As described above, since the present invention apparatus calculates the 
focusing delay time on a real time basis with a sufficient precision using 
only an integer adder, a digital focusing system can be embodied in the 
ASIC. The present invention apparatus can independently calculate the 
focusing delay time with respect to each array element, to thereby 
simplify the system construction. 
INDUSTRIAL APPLICABILITY 
The above-described algorithm of the present invention calculates the 
focusing delay time using the information on the center of the array 
transducer, the corresponding array element and the scan line. 
Accordingly, the algorithm according to the present invention can be 
applied to a general beam focusing technology using the array transducer 
having various patterns as well as the ultrasound reception focusing.