Glass frit wafer bond protective structure

A bonded semiconductor device comprising a support substrate, a semiconductor device located with respect to one side of the support substrate, a cap substrate overlying the support substrate and the device, a glass frit bond ring between the support substrate and the cap substrate, an electrically conductive ring between the support substrate and the cap substrate. The electrically conductive ring forms an inner ring around the semiconductor device and the glass frit bond ring forms an outer bond ring around the semiconductor device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to semiconductor devices formed from wafers bonded with a glass frit.

2. Description of the Related Art

With some types of semiconductor devices such as micro electrical mechanical systems (MEMS) devices, it is desirable to seal the device (e.g. hermetically) for proper operation of the device. For example, it is desirable to seal a MEMS accelerometer in a chamber to prevent contamination of the moving parts of the accelerometer during subsequent processes and during operation. One method for sealing a MEMS device is to bond a cap wafer to a device wafer with a glass frit.

DETAILED DESCRIPTION

In some embodiments, a bonded semiconductor device die can be formed by bonding two wafers with an outer glass frit bond and an inner ring that provides an electrically conductive path between structures of the two wafers. In addition, the inner ring also provides a stop that prevents the glass frit from overflowing to the semiconductor device during the wafer bonding process. Also, in some embodiments, the inner ring may prevent gasses produced by the frit bonding process from contaminating the semiconductor device.

FIG. 1is a partial side view of a device wafer101. In the embodiment shown, device wafer101includes a substrate103made of e.g., bulk mono crystalline silicon. A dielectric layer105is located on substrate103.

Located on dielectric layer105are outer ring104, inner ring110, semiconductor device114, and bond pad125. In the embodiment shown, outer ring104, inner ring110, semiconductor device114, and bond pad125each include structures formed from two poly silicon layers. Ring104includes structure108and structure107. Inner ring110includes structures112and111. Semiconductor device includes structures116and115, and pad125includes structures117and119. Structures108,112,116, and117are made from a layer126of patterned poly silicon, and structures107,111,115, and119are made from a layer127of patterned poly silicon formed over layer126. In addition, inner ring110and pad125each include a conductive metal layer (structure113and structure121, respectively) formed form a layer129of metal (e.g. an aluminum layer with 0.5% copper). In one embodiment, layers126and127are doped with a conductivity dopant (e.g. boron, phosphorous, or arsenic).

In one embodiment, layer105has a thickness of 25000 angstroms, layer126has a thickness of 3500 angstroms, layer127has a thickness of 250,000 angstroms, and layer129has a thickness of 14,000 Angstroms. However, these layers may be of other thickness and/or be made of other materials in other embodiments. For example, layer127may have a thickness of 30,000 angstroms. Also in other embodiments, wafer101may have a different configuration including a different number and/or types of layers. For example, rings104and110may include a greater or lesser number of layers.

In one embodiment, semiconductor device114is a MEMS device. Examples of MEMS devices include accelerometers, gyroscopes, pressure sensors, switches, and mini motors. In one embodiment, device114is a “teeter totter” accelerometer. However, device114may be another type of semiconductor device, e.g. an integrated circuit that includes a processor, memory device, RF components, logic, and/or analog devices. In other embodiments, semiconductor device may be a discrete component (e.g. a capacitor, resistor, or inductor).

Device114may also include dielectric and metal layers (not shown) that are selectively patterned to form the specific structures of the device. For example, dielectric layers (e.g. silicon dioxide, nitride) may be located between structures116and115for electrical isolation. Also, device114may include multiple structures formed from each layer126and127.

In the embodiment shown, layer105includes openings (e.g.109) so that ring110can be in electrical contact with substrate103. In one embodiment, these openings may be formed by forming an oxidation barrier at locations of the openings prior to oxidizing substrate103to form layer105. However, in another embodiments, layer105may be selectively etched at the location109, e.g. as where layer105is formed from a deposited layer of dielectric material.

FIG. 2shows a partial top view of wafer101. As shown in the embodiment ofFIG. 2, inner ring110is continuous in that is completely surrounds device114. Outer ring104is also continuous in that it completely surrounds inner ring110and device114. Bond pad125is located outside of rings104and110. In the embodiment shown, electrical traces (205) electrically couple device114to the bond pads. In one embodiment, the traces (205) are formed from layer126, where poly silicon of the traces are electrically isolated by dielectric material (not shown) from the poly silicon of structures111and112of ring110and structures108and107of ring104.

Shown in dashed lines are the locations of openings (109,207) in layer105where structure112is in electrical contact with substrate103. Also shown in dashed lines in the embodiment of Figure are openings (209) in layer105where structure108is in electrical contact with substrate103.

Although not shown, wafer101may include multiple sections similar to that shown inFIG. 2where each section will be subsequently singulated to form an individual die with a bonded semiconductor device in subsequent processes. Also in other embodiments, multiple semiconductor devices may be located within an inner ring (110) and outer ring (104). Furthermore, the rings may have different shapes (e.g. oval, circular) other than the rectangular shape shown inFIG. 2. Also, in other embodiments, the outer rings of adjacent sections may share segment portions.

FIG. 3is a partial side view of a cap wafer301. Cap wafer301includes a substrate303which in one embodiment is made of bulk mono crystalline silicon, but may be made of other materials (e.g. other semiconductor materials) in other embodiments. In one embodiment, substrate303is doped with a conductivity dopant (e.g. arsenic, phosphorous, or boron).

A layer305of doped mono crystalline silicon is located over substrate303. In one embodiment, layer305has a higher net conductivity dopant concentration than substrate303. In one embodiment, layer305is formed by ion implanting conductivity dopants into a top portion of substrate303. In other embodiments, layer305is formed by epitaxially growing in-situ doped mono crystalline silicon on substrate303. In one embodiment, layer305is doped with n-type conductivity dopant (e.g. phosphorous, arsenic) having a conductivity dopant concentration of greater than 8e19atoms per cm3. However, layer305may have a different doping concentration and may be doped with different conductivity dopants (e.g. boron), in other embodiments. In one embodiment, substrate303has doping concentration to provide a bulk resistivity of 10±5 ohms-cm. Layer305has a bulk resistivity of less than 1.4 mohms-cm. For such a resistivity range, substrate303has a lower net dopant concentration than layer305. In one embodiment, wafer301may be highly doped to meet the desired resistivity of layer305such that additional doping to form layer305is not needed. In one embodiment, layer305has a thickness of 6 micrometers, but may have thicknesses in other embodiments.

FIG. 4shows a partial side view of wafer301after wafer301has been etched to form various structures. In the embodiment shown, layer305has been patterned to form an inner ring401. Also substrate303has been etched to form device cavity403and pad cavity405. A Z-directional stop413is located in cavity403. Ring401surrounds cavity403. In one embodiment, ring401has a width of 25 microns, but may have other widths in other embodiments.

In one embodiment, the structures of wafer301inFIG. 4are formed by first etching layer305to form ring401. In one embodiment, a layer of photo resist (not shown) is formed over wafer301where the remaining portion of layer305is exposed to an etchant for removal with a timed etch to level409. Afterwards an oxide (not shown) is deposited on wafer301and patterned to remove the oxide over the regions of the device cavity403(excluding over stop413) and pad cavity405. The wafer is then subjected to a timed isotropic etch where portions of the substrate303are removed to level411. In one embodiment, tetramethylammonium hydroxide is used as an etchant where the etch boundaries follow the crystalline plane of the <100> crystalline orientation of silicon substrate303. The patterned oxide is then removed. The structures shown inFIG. 4may be made by other processes in other embodiments. Also, wafer301may have other structures and/or configurations in other embodiments.

FIG. 5shows a partial side view of wafer301after a ring501of glass frit is applied to wafer301. In one embodiment, the glass frit includes lead. In one embodiment, the glass frit is applied through a screen printing process, but may be applied by other methods in other embodiments. In one embodiment, glass frit ring501has a thickness of 14 microns and a width (the horizontal direction inFIG. 5) of 150 microns. However, ring501may be other dimensions and/or have other configurations in other embodiments.

In an embodiment where multiple devices are formed on a wafer101, the glass frit ring501may have a width such that it extends into a portion of an adjacent device region (not shown) of cap wafer301. The frit ring would be separated when the wafers are singulated. Thus, a portion of the glass frit ring as applied would also serve as a portion of the glass frit ring for adjacent device regions.

Referring toFIG. 6, after the formation of wafer301at the stage ofFIG. 5, wafer301is flipped over and aligned with wafer101where ring501is aligned with ring104and ring401is aligned with ring110. In the alignment shown, cavity403is located over device114and cavity405is located over pad125. In an embodiment where a portion of ring501is also used to seal an adjacent device, ring501may be aligned such that a portion of its width for one segment is located over ring104and also over an adjacent ring portion (not shown) of the adjacent device portion (not shown) of wafer101.

FIG. 7is a partial side view of the wafers301and101after they have been bonded together to form a composite wafer700. In one embodiment, the wafers are bonded at a temperature in the range of 400-450 C and under an ambient pressure in the range of 1-2400 Torr. Also, a bonding pressure in the range of 5,000-10,000 millibars is applied to the wafers during bonding. However, the wafers maybe bonded at other temperatures, atmospheric pressures, and/or bonding pressures in other embodiments. In one embodiment, wafers101and301are bonded in a multi chamber bonding tool where they are aligned and then clamped together. After clamping, heat and bonding pressure are applied to the wafers.

During the bonding process, the top surface of structure113of ring110contacts and forms an electrically conductive bond705with lower surface of ring401. In one embodiment, this electrically conductive bond is formed by contact of the aluminum of structure112and the doped mono crystalline silicon of ring401. In some embodiments, the silicon migrates into the aluminum during the bonding process.

In the embodiment shown, during the bonding process, the glass frit material701of ring501overflows around the sides of ring104. The seal of ring401and ring110, serves as a frit stop that prevents the glass frit material701from reaching device114.

Accordingly, providing an inner ring to separate the semiconductor device from the grass frit ring may in some embodiments, provide for a process where the frit material can be applied with lower manufacturing tolerances. With the use of a frit stop, a greater amount of frit material may be applied to the ring without the concern of the frit over flowing into the semiconductor device.

In one embodiment, the seal of frit material to ring104bonds the wafers and forms a hermetic seal of the cap wafer to the device wafer. In other embodiments, the seal may not be hermetic. In other embodiments, ring104(or other wafer structure) may have an opening to expose the device to atmospheric conditions after bonding.

FIG. 8is a side view of a bonded semiconductor device801. Device801is formed by singulating the bonded wafers shown inFIG. 7. Prior to singulation, cap wafer301is removed over the location of the bond pads (125) to expose the pads. Afterwards the bonded wafers are singulated (e.g. with a saw or laser) to form multiple bonded devices such as device801.

In some embodiments where ring501extends (laterally in the view ofFIG. 7) to other device regions of cap wafer301and device wafer101, the singulation is performed to separate the glass frit material701between the device regions. Also in other embodiments, a portion of ring104may extend (laterally in the view ofFIG. 7over to an adjacent device region of wafer101such that that segment also serves as a portion of the outer ring for the adjacent device (not shown). During singulation, that portion of ring104would be separated where a remaining half would go to each singulated device.

In some embodiments, the portion of cap wafer of device801is electrically grounded via the electrically conductive contact between ring401and ring110. Accordingly, with some embodiments, an additional cap grounding structure is not needed.

In subsequent processes, device801may be implemented in an electronic package and e.g. encapsulated with other devices such a processor or controller where the pads (125) are electrically coupled (e.g. by wire bonding) to the other circuitry for operation. The package can be implemented in an electronic system (e.g. computer, cell phone, or motor control unit for an automobile).

In other embodiments, the inner ring may be discontinuous such that there may be openings in the ring (e.g. in the corners). Providing openings in the inner ring may provide for more interlocking strength of the frit bond where portions of frit material701reside in between portions of the inner ring.

Also, in some embodiments, the inner ring not only prevents glass frit material701from flowing to the semiconductor device, but it may also prevent gasses (e.g. gaseous lead) from contaminating the semiconductor device during the bonding process. In some embodiments, gaseous lead may lead to undesirable whisker formation on the silicon structures of the semiconductor device114.

In some embodiments, a ring segment similar to a segment of ring401and ring110may be formed between the outer ring104(and501) and the pads (125) to prevent the glass frit material from overflowing to the pads. See for example,FIG. 2where such a ring segment would be located between the right side of ring104and the bond pads201and125. In some embodiments where a device wafer includes rows of device regions, rings having the same structures as rings110and401would be formed around the group of pads of the wafer100and around cavity405of wafer301, respectively, to keep the glass frit from over flowing on the pads during the bonding process.

One advantage that may occur with some embodiments described herein is that an electrically conductive contact can be formed between the device substrate and cap portion without a poly silicon or metal layer formed on the cap wafer for such purposes. However in some embodiments, such materials may be formed on the cap wafer.

In one embodiment, a bonded semiconductor device includes a device substrate with a semiconductor device located with respect to one side of the device substrate, a cap substrate overlying the one side of the device substrate and the semiconductor device, and a glass frit bond ring between the device substrate and the cap substrate. The device includes an electrically conductive ring between the device substrate and the cap substrate, wherein the electrically conductive ring forms an inner ring around the semiconductor device and the glass frit bond ring forms an outer ring around the semiconductor device.

In another embodiment, a method of manufacturing a bonded semiconductor device includes forming a polysilicon ring over a support substrate. The polysilicon ring surrounds a semiconductor device. The method includes forming conductive contact material over the polysilicon ring, forming a mono crystalline ring over a cap substrate, and forming a glass frit ring of material over the cap substrate. The glass frit ring surrounds the mono crystalline ring. The method also includes bonding the cap substrate to the support substrate with at least the glass frit ring such that the mono crystalline ring contacts the conductive contact material for forming an electrically conductive ring.