HEAT DISSIPATING FEATURES FOR LASER DRILLING PROCESS

Embodiments provide metal features which dissipate heat generated from a laser drilling process for exposing dummy pads through a dielectric layer. Because the dummy pads are coupled to the metal features, the metal features act as a heat dissipation feature to pull heat from the dummy pad. As a result, reduction in heat is achieved at the dummy pad during the laser drilling process.

BACKGROUND

The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a trend for smaller and more creative packaging techniques of semiconductor dies has emerged. An example of such packaging systems is Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables production of semiconductor devices with enhanced functionalities and small footprints on a printed circuit board (PCB).

In some packaging processes, device dies are sawed from wafers before they are packaged, wherein redistribution lines are formed to connect to the device dies. An advantageous feature of this packaging technology is the possibility of forming fan-out packages, which means the I/O pads on a die can be redistributed to a greater area than the die, and hence the number of I/O pads on the surfaces of the dies can be increased.

DETAILED DESCRIPTION

Dummy pads may be included in a backside pad layer of a die package. The backside pad layer may be buried beneath a dielectric layer. After the front side structures of the die package are formed, the die package may be flipped over and the buried pads of the backside pad layer revealed through the dielectric layer by a laser drilling process. Embodiments provide integrated heat dispersion for dummy pads so that when the laser contacts the dummy pads in the backside pad layer, potential damage to the dummy pads or pad layer may be reduced or eliminated by providing sufficient heat dispersion. Embodiments provide several options for physically coupling the dummy pads to other isolated (electrically floating or electrically disconnected) metal features in the die package. In one embodiment, the dummy pads are connected to a wide metal in the backside pad layer, while the active pads remain isolated from the wide metal. In one embodiment, the dummy pads are physically coupled to a redistribution structure which provides coupling to other dummy pads, a mesh metal, a bulk metal, a comb metal, dummy metal routing, or any combination thereof. The heat from the laser-drilling process can be dissipated using the redistribution structure and additional metal into the surrounding materials.

Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

FIG.1illustrates a cross-sectional view of an integrated circuit die50in accordance with some embodiments. The integrated circuit die50will be packaged in subsequent processing to form an integrated circuit package or die package. The integrated circuit die50may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof.

The integrated circuit die50may be formed in a wafer, which may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit dies. The integrated circuit die50may be processed according to applicable manufacturing processes to form integrated circuits. For example, the integrated circuit die50includes a semiconductor substrate52, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate52may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate52has an active surface (e.g., the surface facing upwards inFIG.1), sometimes called a front side, and an inactive surface (e.g., the surface facing downwards inFIG.1), sometimes called a backside.

Devices (represented by a transistor)54may be formed at the front surface of the semiconductor substrate52. The devices54may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An inter-layer dielectric (ILD)56is over the front surface of the semiconductor substrate52. The ILD56surrounds and may cover the devices54. The ILD56may include one or more dielectric layers formed of materials such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like.

Conductive plugs58extend through the ILD56to electrically and physically couple the devices54. For example, when the devices54are transistors, the conductive plugs58may couple the gates and source/drain regions of the transistors. The conductive plugs58may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof. An interconnect structure60is over the ILD56and conductive plugs58. The interconnect structure60interconnects the devices54to form an integrated circuit. The interconnect structure60may be formed by, for example, metallization patterns in dielectric layers on the ILD56. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers. The metallization patterns of the interconnect structure60are electrically coupled to the devices54by the conductive plugs58.

The integrated circuit die50further includes pads62, such as aluminum pads, to which external connections are made. The pads62are on the active side of the integrated circuit die50, such as in and/or on the interconnect structure60. One or more passivation films64are on the integrated circuit die50, such as on portions of the interconnect structure60and pads62. Openings extend through the passivation films64to the pads62. Die connectors66, such as conductive pillars (for example, formed of a metal such as copper), extend through the openings in the passivation films64and are physically and electrically coupled to respective ones of the pads62. The die connectors66may be formed by, for example, plating, or the like. The die connectors66electrically couple the respective integrated circuits of the integrated circuit die50.

Optionally, solder regions (e.g., solder balls or solder bumps) may be disposed on the pads62. The solder balls may be used to perform chip probe (CP) testing on the integrated circuit die50. CP testing may be performed on the integrated circuit die50to ascertain whether the integrated circuit die50is a known good die (KGD). Thus, only integrated circuit dies50, which are KGDs, undergo subsequent processing and are packaged, and dies, which fail the CP testing, are not packaged. After testing, the solder regions may be removed in subsequent processing steps.

A dielectric layer68may (or may not) be on the active side of the integrated circuit die50, such as on the passivation films64and the die connectors66. The dielectric layer68laterally encapsulates the die connectors66, and the dielectric layer68is laterally coterminous with the integrated circuit die50. Initially, the dielectric layer68may bury the die connectors66, such that the topmost surface of the dielectric layer68is above the topmost surfaces of the die connectors66. In some embodiments where solder regions are disposed on the die connectors66, the dielectric layer68may bury the solder regions as well. Alternatively, the solder regions may be removed prior to forming the dielectric layer68.

The dielectric layer68may be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof. The dielectric layer68may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the die connectors66are exposed through the dielectric layer68during formation of the integrated circuit die50. In some embodiments, the die connectors66remain buried and are exposed during a subsequent process for packaging the integrated circuit die50. Exposing the die connectors66may remove any solder regions that may be present on the die connectors66.

In some embodiments, the integrated circuit die50is a stacked device that includes multiple semiconductor substrates52. For example, the integrated circuit die50may be a memory device such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like that includes multiple memory dies. In such embodiments, the integrated circuit die50includes multiple semiconductor substrates52interconnected by through-substrate vias (TSVs). Each of the semiconductor substrates52may (or may not) have an interconnect structure60.

FIGS.2through17andFIGS.21through26illustrate the cross-sectional or plan views of intermediate stages in the formation of a package including one or more common metal features connected by a metal connection to dummy pads, in accordance with some embodiments of the present disclosure. The corresponding processes are also reflected schematically in the process flow shown inFIG.27.

Referring toFIG.2, carrier101is provided, and release film102is coated on carrier101. Carrier101may be formed of a transparent material, and may be a glass carrier, a ceramic carrier, or the like. Release film102may be formed of a Light-To-Heat-Conversion (LTHC) coating material, and may be applied onto carrier101through coating. In accordance with some embodiments of the present disclosure, the LTHC coating material is capable of being decomposed under the heat of light/radiation (such as laser), and hence can release carrier101from the structure formed thereon.

In accordance with some embodiments, as shown inFIG.3, dielectric layer104is formed on release film102. Dielectric layer104may be formed of or comprise a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer104is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer104may be formed by any acceptable deposition process, such as spin coating, CVD, laminating, the like, or a combination thereof. Dielectric layer104provides good planarity to serve as a level base to construct overlying features.

Metal seed layer106A is deposited over dielectric layer104. The respective process is illustrated as process402in the process flow400shown inFIG.27. In accordance with some embodiments, metal seed layer26A includes a titanium layer and a copper layer over the titanium layer. The metal seed layer may be formed through, for example, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or the like.

Next, as shown inFIG.3, a patterned plating mask108is applied and patterned. The respective process is illustrated as process404in the process flow400shown inFIG.27. In accordance with some embodiments, the patterned plating mask108comprises a patterned photo resist. In accordance with alternative embodiments, plating mask108comprises a dry film, which is laminated and then patterned. Some portions of metal seed layer106A are exposed through the patterned plating mask108.

Still referring toFIG.3, next, metallic material106B is deposited on the exposed portions of metal seed layer106A. The respective process is illustrated as process406in the process flow400shown inFIG.27. The deposition process may include a plating process, which may be an electro-chemical plating process, an electroless plating process, or the like. Metallic material106B may include Cu, Al, Ti, W, Au, or the like. After the plating process, the patterned plating mask108is removed, exposing the underlying portions of metal seed layer106A. The respective process is illustrated as process408in the process flow400shown inFIG.27. The patterned plating mask108may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like.

The exposed portions of metal seed layer106A are then removed, such as by using an acceptable etching process, such as by wet or dry etching, and the remaining portions of the metal seed layer106A and metallic material106B together become a metal layer110(or conductive features110), as shown inFIG.4. The metal layer110may include several different types of metal features, including for example, a metal mesh110M, active pads110A, dummy pads110D, pad bridges110B (seeFIG.7), metal lines110L, and/or a wide metal110W (seeFIG.7). The respective process is also illustrated as process408in the process flow400shown inFIG.27. In some embodiments, the metal mesh110M is positioned so as to be aligned with a subsequently placed integrated circuit die50and can help to provide heat dispersion capabilities. In some embodiments, the metal mesh110M can be replaced with a bulk metal, dummy metal lines, a metal comb, the like, or combinations thereof. Examples of these types of structures are discussed in connection withFIG.10, below.

FIG.5illustrates a top view of the structure illustrated inFIG.4. The cross-sectional view shown inFIG.3is an example which may be obtained from cross-section A-A inFIG.5. In accordance with some embodiments, the metal mesh110M includes a plurality of strips having lengthwise directions in the X-direction, and a plurality of strips having lengthwise directions in the Y-direction, which may be (or may not be) perpendicular to the X-direction. These sets of plurality of strips define a plurality of openings112M therein. In accordance with some embodiments, the plurality of openings112M form an array, and may have same sizes. The plurality of strips have crossing areas, which are the areas in which the X-direction and Y-direction plurality of strips overlap. Other openings112include any areas not covered by the metal layer110, and may be found, for example, between dummy pads110D and/or active pads110A or surrounding dummy pads110D and/or active pads110A.

FIG.6illustrates an enlarged view of the box labeled F6inFIG.5, in accordance with some embodiments. The active pads110A and dummy pads110D may have elongated portions110V which protrude laterally from the respective active pad110A or dummy pad110D. The elongated portions110V provides a place for a subsequently formed via136V to land. In some embodiments the subsequently formed via136V may land directly on the main portion of the active pad110A or dummy pad110D. In some embodiments, the active pad110A and/or dummy pad110D may include multiple elongated portions110V and several vias136V may be used for one or more of the active pads110A and/or dummy pads110D.

As illustrated inFIG.7, in some embodiments, a wide metal110W structure may be formed over the dielectric layer104. The wide metal110W provides large metal surface and thermal bulk for heat dissipation. Some of the wide metal110W may be reserved for a power plane or a ground plane. Some of the wide metal110W may be electrically floating, i.e., electrically isolated from any power, ground, or signal sources. Isolation regions112imay separate the various sections of the wide metal110W. Isolation rings112irmay surround individual active pads110A and/or dummy pads110D or a plurality of active pads110A and/or dummy pads110D. Openings112omay be dispersed in an interrupted pattern or randomly throughout the wide metal110W.

The dummy pads110D may be physically coupled to the wide metal110W by pad bridges110B, the pad bridges110B providing thermally conductive paths to the wide metal110W to help disperse heat which may be generated from a subsequent laser drilling process. The pad bridges110B may have a length between about 8 µm and about 200 µm, depending on the spacing of the dummy pad110D to the wide metal110W. The width of the pad bridges110B across the spacing between the dummy pad110D and the wide metal110W may be between about 10 µm and about 50 µm, though other values may be used.. The pad bridges110B may be formed at the same time as the dummy pads110D and wide metal110W. Each of the dummy pads110D may include several pad bridges110B to the wide metal110W. In some embodiments, for example, the number of pad bridges110B may be between 4 and12for each dummy pad110D, though more or fewer pad bridges110B may be used. As indicated inFIG.7, the subsequently formed vias136V may be coupled directly to the wide metal110W, providing further physically coupling and thermal coupling to a subsequently formed redistribution structure. It should be understood that the features illustrated inFIG.7may be combined without limitation as needed to achieve a particular design.

In some embodiments, rather than have some dummy pads110D completely isolated from every other metal feature, none of the dummy pads110D may remain isolated from any other feature. In other words, every dummy pad110D is connected to another metal feature, such as the wide metal110W or a metal via to a metal feature in another metal layer (e.g., metal layer136, described below with respect toFIGS.9and10), and is not limited thereto.

Referring toFIG.8, dielectric layer130is formed on the metal layer110. The respective process is illustrated as process410in the process flow400shown inFIG.27. The bottom surface of dielectric layer130is in contact with the top surfaces of metal mesh110M, active pads110A, dummy pads110D, wide metal110W (if used), and pad bridges110B (if used), and so forth. In accordance with some embodiments of the present disclosure, dielectric layer130is formed of or comprises a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like. In accordance with alternative embodiments, dielectric layer130is formed of an inorganic dielectric material, which may include a nitride such as silicon nitride, or an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), or the like.

In accordance with some embodiments, the formation of dielectric layer130includes dispensing dielectric layer130in a flowable form, and then curing the flowable dielectric layer130to solidify it. Dielectric layer130is then patterned to form openings132therein, thereby exposing portions of the dummy pads110D, active pads110A, metal lines110L, elongated portions110V, wide metal110W (if used), metal mesh110M, and/or combinations thereof. The patterning may be formed by an acceptable process, such as by exposing the dielectric layer130to light when the dielectric layer130is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer130is a photo-sensitive material, the dielectric layer130can be developed after the exposure.

FIGS.9and10illustrates the formation of metal layer136(which is also collectively referred to as conductive features136), which may include redistribution lines136L, metal vias136V, and optionally one or more of a dummy interconnect136I, metal mesh136M, dummy routing136D, bulk metal136B, or metal comb136C. The respective process is illustrated as process412in the process flow400shown inFIG.27. For example, metal layer136may include redistribution lines136L over dielectric layer130and vias portion (also referred to as vias)136V extending through the dielectric layer130to contact physically and electrically the metal layer110. The formation of metal layer136may adopt processes and materials similar to those for forming the metal layer110. Also, each of vias136V may have a tapered profile, with the upper portions being wider than the corresponding lower portions. The vias136V may land on any of the dummy pads110D, active pads110A, metal lines110L, elongated portions110V, wide metal110W (if used), metal mesh110M, and/or combinations thereof.

FIG.10illustrates an example top view of the metal layer136, in accordance with some embodiments. Some features are omitted for clarity. As noted above, the metal layer136may optionally include one or more of a dummy interconnect136I,metal mesh136M, dummy routing136D, bulk metal136B, or metal comb136C. When utilized, these features provide heat dissipation properties for a subsequent laser drilling process, such as discussed in greater detail below.

The metal mesh136M is a grid of interconnecting metal lines. The metal mesh136M may similar to the metal mesh110M, such as described above. The metal mesh136M may be about the same size as the metal mesh110M or may be larger or smaller. In some embodiments, the metal mesh136M may be aligned to the metal mesh110M or may be offset from the metal mesh110M.

The bulk metal136B is a wide metal that has a length and width which exceed the line width for redistribution lines136L. For example, the bulk metal136B may have a width and length footprint which is between 2 and 100 times the line width of the redistribution lines136L. Or, in another example, the bulk metal136B may have a top view surface area which is greater than the top view surface area of one of the redistribution lines136L leading to the bulk metal136B. The bulk metal136B may also have angled or curved sides in top down view, so as to fit a particular area amongst redistribution lines136L.

The metal comb136C has multiple parallel lines which are connected at one or both ends by a bulk metal or a perpendicular line. The metal comb136C provides a large surface area interface with a surrounding overlying dielectric material which is subsequently deposited over the metal layer136.

The dummy routing136D includes routed lines which may be routed in a pattern or which may be routed randomly and which are coupled only to dummy pads110D. The dummy routing136D may also include inefficient routing to provide more metal mass for the routing and more routed linear distance between two dummy pads110D. For example, the dummy routing136D may provide linear routed distance between two dummy pads110D which is between 2 and 50 times further than the shortest linear distance between the same two dummy pads110D. In some embodiments, the dummy routing136D may include metal lines which extend from a dummy pad110D which do not connect to another dummy pad110D.

The dummy interconnect136I may physically connect several dummy pads110D together. The dummy interconnect136I may also include an optional feature interconnect136FI (which is also a type of dummy interconnect136I) which couples one or more dummy pads110D to one of the aforementioned features, such as the bulk metal136B, metal comb136C, or dummy routing136D.

InFIG.10, some dummy pads110D and active pads110A from the underlying metal layer110are illustrated in dashed outline to show the relation between the overlying features of the metal layer136and the dummy pads110D and active pads110A. The metal layer136may include corresponding pads, in some embodiments, which are aligned to the active pads110A and the dummy pads110D. Examples of corresponding pads are illustrated, for example, inFIGS.18through20. As illustrated inFIG.10, in some embodiments, dummy pads110D may be interconnected to other dummy pads110D by the dummy interconnect136I. In such embodiments, these dummy pads110D may optionally be connected to another heat dissipation feature by a feature interconnect136FI.

FIG.10illustrates one each of a bulk metal136B, a metal comb136C, a metal mesh136M, a dummy routing136D, a dummy interconnect136I, and a feature interconnect136FI, however, it should be understood that the resulting package may utilize any combination of these features, including multiples thereof. Each of these may also be coupled to the underlying metal mesh110M. As such, the dummy pads110D may be coupled to the metal mesh110M. For example, the dummy pad110D may be coupled to a via136V, which may be coupled to a dummy interconnect136I and/or feature interconnect136FI, which may be coupled to the bulk metal136B, metal comb136C, dummy routing136D, and/or metal mesh136M, which may be coupled to a via136V, which may be coupled to the metal mesh110M.

Accordingly, embodiments utilizing one of these heat dissipation features may have a heat dissipation path which radiates to the metal mesh110M. Other embodiments may omit the use of a bulk metal136B, a metal comb136C, a metal mesh136M, a dummy routing136D, and a dummy interconnect136I,in favor of using the wide metal110W and pad bridges110B, the wide metal110W providing heat dissipation capabilities. Other embodiments may utilize both the wide metal110W and one or more of the heat dissipation features of the metal layer136. As such, a network of dummy structures is formed which results in a large thermal bulk which provide heat dissipation for a subsequent laser drilling process.

FIG.11illustrates the formation of dielectric layer138. Openings140are formed in dielectric layer138to expose the underlying metal layer136. The respective processes are illustrated as process414in the process flow400shown inFIG.27. In accordance with some embodiments of the present disclosure, dielectric layer138is formed of a material selected from the same group of candidate materials for forming dielectric layers130and104, and may include organic materials, as aforementioned. It is appreciated that although in the illustrated example embodiments, two dielectric layers130and138, and the respective metal layers110and136are discussed as examples, fewer or more dielectric layers and conductive layers may be adopted, depending on the signal routing requirement. Throughout the description, metal layers110and136and dielectric layers104,130, and138are collectively referred to as backside interconnect structure141, which is on the backside of the subsequently placed device die. The formation of dielectric layer138may include dispensing dielectric layer138in a flowable form, and then curing the flowable dielectric layer138to solidify it.

Referring toFIG.12, vias146are formed in openings140, and metal posts148are formed over and joined with vias146. The respective process is illustrated as process416in the process flow400shown inFIG.27. Vias146and metal posts148may be formed in common formation processes. In accordance with some embodiments, the formation processes include depositing a metal seed layer, forming a plating mask (not shown) over the metal seed layer, plating a metallic material in the openings in the plating mask, removing the plating mask, and etching the portions of the metal seed layer previously covered by the plating mask. In accordance with some embodiments of the present disclosure, the metal seed layer may include a titanium layer and a copper layer over the titanium layer. The formation of the metal seed layer may include PVD, CVD, or the like. The plating mask may include photo resist. The plated metallic material may include copper or a copper alloy, tungsten, or the like. The plated metallic material and the remaining portions of the metal seed layer thus form vias146and the metal posts148.

FIG.13illustrates the placement/attachment of circuit die50(seeFIG.1), with Die-Attach Film (DAF)51being used to adhere circuit die50to dielectric layer138. The respective process is illustrated as process418in the process flow400shown inFIG.27. Although one circuit die50is illustrated, there may be a plurality of package components being placed, which may be the same as each other or different from each other. In accordance with some embodiments, circuit die50is a device die, a package with a device die(s) packaged therein, a System-on-Chip (SoC) die including a plurality of integrated circuits (or device dies) integrated as a system, or the like. The device die in circuit die50may be or may include a logic die, a memory die, an input-output die, an Integrated Passive Device (IPD), or the like, or combinations thereof. For example, the logic die in circuit die50may be a Central Processing Unit (CPU) die, a Graphic Processing Unit (GPU) die, a mobile application die, a Micro Control Unit (MCU) die, a BaseBand (BB) die, an Application processor (AP) die, or the like. The memory die in circuit die50may include a Static Random Access Memory (SRAM) die, a Dynamic Random Access Memory (DRAM) die, or the like. Circuit die50may include dielectric layer68and die connectors66(such as metal pillars, micro-bumps, and/or bond pads) embedded in dielectric layer68.

Next, as shown inFIG.14, encapsulant158is dispensed to encapsulate circuit die50and metal posts148therein. The respective process is illustrated as process420in the process flow400shown inFIG.27. Encapsulant158fills the gaps between neighboring metal posts148and circuit die50. Encapsulant158may include a molding compound, a molding underfill, an epoxy, a resin, and/or the like. At the time of encapsulation, the top surface of encapsulant158is higher than the top ends of metal posts148and the top surface of circuit die50. The molding compound or molding underfill (if used) may include a base material, which may be a polymer, a resin, an epoxy, or the like, and filler particles in the base material. The filler particles may be dielectric particles of silica, alumina, boron nitride, or the like, and may have spherical shapes. A planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process is then performed to thin encapsulant158and circuit die50, until both of die connectors66and metal posts148are revealed. Due to the planarization process, the top ends of die connectors66and metal posts148are level (coplanar) with the top surfaces of encapsulant158. Metal posts148are alternatively referred to as through-vias148hereinafter since they penetrate through encapsulant158.

FIGS.15through17illustrate the formation of a front-side interconnect structure overlying and connecting to circuit die50and metal posts148. The respective process is illustrated as process422in the process flow400shown inFIG.27. Referring toFIG.15, dielectric layer162is formed. In accordance with some embodiments of the present disclosure, dielectric layer162is formed of or comprises a polymer such as PBO, polyimide, BCB, or the like. The formation process includes coating dielectric layer162in a flowable form, and then curing dielectric layer162. In accordance with alternative embodiments of the present disclosure, dielectric layer162is formed of an inorganic dielectric material such as silicon nitride, silicon oxide, or the like. The formation method may include CVD, Atomic Layer Deposition (ALD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), or another applicable deposition method.

Openings (occupied by the via portions of RDLs166) are then formed, for example, through a photo lithography process. Through-vias148and die connectors66are exposed through the openings. Next, RDLs166are formed. The formation process may be similar to the formation of metal layers110and136. RDLs166are electrically connected to die connectors66and through-vias148.

FIG.15further illustrates the formation of dielectric layers168,172, and176, and RDLs170and174. In accordance with some embodiments of the present disclosure, dielectric layers168,172, and176are formed of materials selected from the same or similar group of candidate materials for forming dielectric layers130and138, and may include organic materials or inorganic materials. Throughout the description, RDLs166,170and174and dielectric layers162,168,172, and176are collectively referred to as front-side interconnect structure160.

FIG.16illustrates the formation of Under-Bump Metallurgies (UBMs)177and conductive connectors178in accordance with some embodiments. The respective processes are illustrated as process424in the process flow400shown inFIG.27. To form UBMs177, openings are formed in dielectric layer176to expose the underlying metal pads, which are parts of RDLs174in the illustrative embodiments. UBMs177may be formed of nickel, copper, titanium, or multi-layers thereof. UBMs177may include a titanium layer and a copper layer over the titanium layer.

Conductive connectors178are then formed on UBMs177. The conductive connectors178may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors178may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors178are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors178comprise metal pillars (such as a copper pillar) formed by sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

In accordance with some embodiments of the present disclosure, optional Independent Passive Device (IPD)181may be bonded to the front-side interconnect structure160through some of conductive connectors178. The respective process is illustrated as process426in the process flow400shown inFIG.27. IPD181may be or may comprise a passive device such as a capacitor die, an inductor die, a resistor die, or the like, or may include the combinations of the passive devices.

Accordingly, the reconstructed wafer100W is formed. The reconstructed wafer100W may include several package regions, such as the first package region100A and the second package region100B (illustrated by the dashed lines).

Next, inFIG.17, the reconstructed wafer100W is de-bonded from carrier101. The respective process is illustrated as process428in the process flow400shown inFIG.27. In accordance with some embodiments, a light beam (which may be a laser beam) is projected on release film102, and the light beam penetrates through the transparent carrier101. Release film102is thus decomposed. Carrier101may be lifted off from release film102, and hence reconstructed wafer100W is de-bonded (demounted) from carrier101. The reconstructed wafer100W is then flipped over and placed on a tape (not shown).

FIGS.18and19illustrate perspective views andFIG.20illustrates a perspective view and a top down (or plan) view of devices which are consistent with that illustrated inFIG.17. Some features have been omitted to aid in clarity, for example, the dielectric layer130has been omitted and the dielectric layer138altered to make the metal layer110and the metal layer136visible. Notably, these devices are not direct representations of that depicted inFIG.17, but are consistent with such, and may be formed using the above-described processes and materials. Like elements have been labeled with like references.FIGS.18through20also illustrate that the metal layer136may also include corresponding pad areas136P, which correspond to the active pads110A or dummy pads110D.

FIG.18illustrates a portion of a device that includes a circuit die50surrounded by an encapsulant158. A portion of the dielectric layer138is illustrated as well. The metal layer110includes a metal mesh110M and a dummy pads110D. The dummy pad110D is coupled to the metal mesh110M by way of the metal layer136. In particular, a metal via136V couples the dummy pad110D to a dummy interconnect136I or feature interconnect136FI to a metal mesh136M. Then, the metal mesh136M is coupled to the metal mesh110M by vias136V. When a laser drilling process is used to expose the dummy pad110D, as described below with respect toFIG.22, heat paths are provided to dissipate heat through the via136V, through the dummy interconnect136I (or feature interconnect136FI), to the metal mesh136M, back up through the vias136V, and to the metal mesh110M.

FIG.19illustrates a portion of a device that includes a circuit die50surrounded by an encapsulant158. A portion of the dielectric layer138is also illustrated. The metal layer110includes dummy pads110D and active pads110A. The active pads110A are coupled by vias136V to metal lines136L which are routed to other electrical features, such as other conductors, signal lines, power lines, ground lines, etc. The dummy pads110D are coupled by vias136V to the dummy interconnect136I. The dummy interconnect136I is then coupled to the dummy routing136D by the feature interconnect136FI. The dummy interconnect is also coupled to the metal mesh136M by a feature interconnect136FI and coupled to the bulk metal136B by another feature interconnect136FI. When a laser drilling process is used to expose the dummy pads110D, as described below with respect toFIG.22, heat paths are provided to dissipate heat through the vias136V, through the dummy interconnect136I, and through the feature interconnects136FI) to the metal mesh136M, bulk metal136B, and/or dummy routing136D.

FIG.20provides a perspective view and a top down view of a portion of a device, including an encapsulant158and dielectric layer138over the encapsulant158. Active pads110A are coupled to metal lines136L by way of the vias136V. The metal lines136L may be routed in the dielectric layer138to couple together certain active pads110A or routed to other electrical features, such as other conductors, signal lines, power lines, ground lines, etc. The dummy pads110D are coupled by vias136V to the dummy interconnect136I. As noted above, the dummy interconnect136I may then be coupled to other metal features in the metal layer136, such as dummy routing136D, bulk metal136B, metal comb136C, and/or metal mesh136M. InFIG.20, however, the dummy interconnect136I couples together several dummy pads110D. When a laser drilling process is used to expose the dummy pads110D, as described below with respect toFIG.22, heat paths are provided to dissipate heat through the vias136V, through the dummy interconnect136I,through the other vias136V coupled to the dummy interconnect136I,and through the other dummy pads110D.

InFIG.21, a backside dielectric layer182is attached to the dielectric layer104. The respective process is illustrated as process430in the process flow400shown inFIG.27. The backside dielectric layer182provides warpage control and protection of the backside interconnect structure141when mounting another device over the backside of the reconstructed wafer100W. The thickness of the backside dielectric layer182may be between about 30 µm and 150 µm thick, although other thicknesses may be used. The backside dielectric layer182may be formed of any suitable material. In some embodiments, the backside dielectric layer182is made of an inorganic filler, such as silicon oxide, and epoxy resin. In some embodiments, the composition of the backside dielectric layer182may include a filler at 10-90% by weight, resin at 10-90% by weight, a coupling agent at 0.5-1% by weight, a stress release agent at 0.5-5% by weight, an adhesion promoter at 0.5-1% by weight, a catalyst at 0.3-0.7% by weight, and a colorant at 0.5-1% by weight. Other suitable materials include any polymer dry film which is able to be drilled by laser. The backside dielectric layer182stabilizes and controls warpage by inducing an inward horizontal compression force toward the backside of the reconstructed wafer100W. For example, the co-efficient of thermal expansion (CTE) for the reconstructed wafer100W may be between about 12 ppm and 20 ppm, such as about 16 ppm, while the CTE for the backside dielectric layer182is greater than the CTE of the reconstructed wafer100W, for example, greater than about 16-20 ppm to about 30 ppm, such as about 22 ppm. The backside dielectric layer182may be attached to the dielectric layer104by a thermal lamination process, so that when the backside dielectric layer182cools after attaching, the compressive counter force is generated by the backside dielectric layer182to control warpage of the reconstructed wafer100W.

InFIG.22, openings184are formed to expose features (e.g., active pads110A and/or dummy pads110D) of the metal layer110. The respective process is illustrated as process432in the process flow400shown inFIG.27. The openings184may be formed by any suitable process. In one embodiment, due in part to the thickness of the backside dielectric layer182, a laser drilling process186is used to expose features of the metal layer110through the openings184. As the laser is energized, the material of the backside dielectric layer182is vaporized in a downward direction, removing material of the backside dielectric layer182until the laser reaches the dielectric layer104. Then the material of the dielectric layer104is removed until the features of the metal layer110are exposed. One side-effect of the laser drilling process is that the surrounding material becomes heated. When the laser begins to heat the metal layer110, a risk of delamination between the metal layer and the dielectric layer104may occur due to overheating the feature (e.g., active pad110A or dummy pad110D) of the metal layer110being exposed. The delamination reduces reliability of the device by causing the risk of device failure. Active pads110A which are exposed by the laser drilling process may be routed by vias (e.g., vias136V) to a redistribution structure, e.g., backside interconnect structure141, which may help disperse heat from the laser drilling process through the metallization routings of the redistribution structure. Because embodiment dummy pads110D may also be attached to other metal features of the metal layer110and/or metal layer136, the heat generated by exposing the dummy pads110D may also be routed to other metal features and away from the dummy pads110D, thereby reducing and/or eliminating the risk of delamination from overheating.

In some embodiments, heat from the laser drilling process186may travel, for example, from the dummy pads110D across the pad bridges110B and to the wide metal110W (seeFIG.7), which provides a large bulk of metal material and a large interface to the surrounding dielectric layers. In some embodiments, heat from the laser drilling process186may travel by vias136V to the metal layer136, which may radiate to the dummy interconnect136I,metal mesh136M, dummy routing136D, and/or bulk metal136B (seeFIG.10) by way of a feature interconnect136FI. In some embodiments, the heat may also be radiated back up to the metal layer110from the metal layer136by vias136V, for example to the metal mesh110M (such as illustrated inFIGS.18and22).

InFIG.23, a solder-containing layer188, which may be a solder layer (sometimes known as a pre-solder layer), a silver paste, a solder paste, or the like, is formed on each of the exposed portions of the metal layer110(e.g., dummy pads110D and active pads110A) in the openings184. The respective process is illustrated as process434in the process flow400shown inFIG.27. The process used to form the solder-containing layer188may be a solder printing or solder stenciling process. In some embodiments, the solder-containing layer188may completely fill or overfill the openings184, while, in other embodiments, the solder-containing layer188may only partially fill the openings184. After the solder-containing layer188is deposited, a reflow process may be performed before bonding the conductive connectors190to the solder-containing layer188(see, e.g.,FIG.25). In some embodiments, the solder-containing layer188can be omitted.

InFIG.24, the conductive connectors190are formed by depositing an additional solder material in the remainder of the openings184and reflowing the solder-containing layer188and additional solder material to bond the additional solder material to the solder-containing layer188, thereby forming the conductive connectors190. The respective process is also illustrated as process434in the process flow400shown inFIG.27. The additional solder material may be deposited by a printing process, a stenciling process, a ball-drop process, or the like. After the reflow process to bond the additional solder material to the solder-containing layer188, the solder-containing layer188and the additional solder material may intermix and not be distinctly visible as separate structures as shown inFIG.24. In some embodiments, the conductive connectors190are formed in a manner similar to the conductive connectors178, and may be formed of a similar material as the conductive connectors178.FIG.24also illustrates optional conductive connectors190in a dashed outline which may provide connectors which land on the metal mesh110M.

FIG.25illustrates the formation and implementation of device stacks, in accordance with some embodiments. The device stacks are formed from the package regions of the reconstructed wafer100W, each package region corresponding to a package component of the device stacks. The device stacks may also be referred to as package-on-package (PoP) structures.

InFIG.25, second package components200are coupled to the reconstructed wafer100W. The respective process is illustrated as process436in the process flow400shown inFIG.27. One of the second package components200is coupled in each of the package regions100A and100B to a corresponding package component to form an integrated circuit device stack in each region of the reconstructed wafer100W. For example, the second package components200are attached to the first package component100.

The second package components200include, for example, a substrate202and one or more stacked dies210(e.g.,210A and210B) coupled to the substrate202. Although one set of stacked dies210(210A and210B) is illustrated, in other embodiments, a plurality of stacked dies210(each having one or more stacked dies) may be disposed side-by-side coupled to a same surface of the substrate202. The substrate202may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate202may be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. The substrate202is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. Build up films such as Ajinomoto build-up film (ABF) or other laminates may be used for the substrate202.

The substrate202may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the second package components200. The devices may be formed using any suitable methods.

The substrate202may also include metallization layers (not shown) and the conductive vias208. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate202is substantially free of active and passive devices.

The substrate202may have bond pads204on a first side of the substrate202to couple to the stacked dies210, and bond pads206on a second side of the substrate202, the second side being opposite the first side of the substrate202, to couple to the conductive connectors152. In some embodiments, the bond pads204and206are formed by forming recesses (not shown) into dielectric layers (not shown) on the first and second sides of the substrate202. The recesses may be formed to allow the bond pads204and206to be embedded into the dielectric layers. In other embodiments, the recesses are omitted as the bond pads204and206may be formed on the dielectric layer. In some embodiments, the bond pads204and206include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bond pads204and206may be deposited over the thin seed layer. The conductive material may be formed by an electro-chemical plating process, an electroless plating process, CVD, atomic layer deposition (ALD), PVD, the like, or a combination thereof. In an embodiment, the conductive material of the bond pads204and206is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

In some embodiments, the bond pads204and the bond pads206are UBMs that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, may be utilized for the formation of the bond pads204and206. Any suitable materials or layers of material that may be used for the bond pads204and206are fully intended to be included within the scope of the current application. In some embodiments, the conductive vias208extend through the substrate202and couple at least one of the bond pads204to at least one of the bond pads206.

In the illustrated embodiment, the stacked dies210are coupled to the substrate202by wire bonds212, although other connections may be used, such as conductive bumps. In an embodiment, the stacked dies210are stacked memory dies. For example, the stacked dies210may be memory dies such as low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like memory modules.

The stacked dies210and the wire bonds212may be encapsulated by a molding material214. The molding material214may be molded on the stacked dies210and the wire bonds212, for example, using compression molding. In some embodiments, the molding material214is a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A curing process may be performed to cure the molding material214; the curing process may be a thermal curing, a UV curing, the like, or a combination thereof.

In some embodiments, the stacked dies210and the wire bonds212are buried in the molding material214, and after the curing of the molding material214, a planarization step, such as a grinding, is performed to remove excess portions of the molding material214and provide a substantially planar surface for the second package components200.

After the second package components200are formed, the second package components200are mechanically and electrically bonded to the first package components100of the reconstructed wafer100W by way of the conductive connectors190, the bond pads206, and the metal layer110(e.g., active pads110A and dummy pads110D). In some embodiments, the stacked dies210may be coupled to the integrated circuit dies50A and50B through the wire bonds212, the bond pads204and206, the conductive vias208, the conductive connectors190, the backside interconnect structure141, the through-vias148, and the front-side interconnect structure160.FIG.25also illustrates optional conductive connectors190in a dashed outline and corresponding bond pads206, which may provide connectors between the second package components200and first package component100which land on the metal mesh110M.

In some embodiments, a solder resist (not shown) is formed on the side of the substrate202opposing the stacked dies210. The conductive connectors190may be disposed in openings in the solder resist to be electrically and mechanically coupled to conductive features (e.g., the bond pads206) in the substrate202. The solder resist may be used to protect areas of the substrate202from external damage.

In some embodiments, the conductive connectors190have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the second package components200are attached to the first package components100.

In some embodiments, an underfill (not shown) is formed between the first package component100and the second package components200, surrounding the conductive connectors190. The underfill may reduce stress and protect the joints resulting from the reflowing of the conductive connectors190. The underfill may be formed by a capillary flow process after the second package components200are attached, or may be formed by a suitable deposition method before the second package components200are attached. In embodiments where the epoxy flux is formed, it may act as the underfill.

FIG.25illustrates the second package region100B with dashed lines, the second package region100B being adjacent to the first package region100A of the reconstructed wafer100W with dashed lines.FIG.25also shows the resulting singulated device stack250following a singulation process. The respective process is illustrated as process438in the process flow400shown inFIG.27. The singulation process is performed by sawing along scribe line regions, e.g., between the first package region100A and the second package region100B, resulting in a first package component100from the first package region100A. The sawing singulates the first package region100A from the second package region100B. The resulting, singulated device stack250is from one of the first package region100A or the second package region100B. For example, the singulated device stack250may include the first package component100and second package components200attached to the first package component, resulting in the singulated device stack250. In some embodiments, the singulation process is performed after the second package components200are coupled to the first package component100(e.g., in the package region100A). In other embodiments (not shown), the singulation process is performed before the second package components200are coupled to the first package component100, such as after the carrier101is de-bonded and the conductive connectors178are formed.

InFIG.26, each singulated device stack250may then be mounted to a package substrate300using the conductive connectors178. The respective process is illustrated as process440in the process flow400shown inFIG.27. The package substrate300includes a substrate core302and bond pads304over the substrate core302. The substrate core302may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate core302may be an SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The substrate core302is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. Build up films such as ABF or other laminates may be used for substrate core302.

The substrate core302may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the device stack. The devices may be formed using any suitable methods.

The substrate core302may also include metallization layers and vias (not shown), with the bond pads304being physically and/or electrically coupled to the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate core302is substantially free of active and passive devices.

In some embodiments, the conductive connectors178are reflowed to attach the first package component100to the bond pads304. The conductive connectors178electrically and/or physically couple the package substrate300, including metallization layers in the substrate core302, to the first package component100. In some embodiments, a solder resist306is formed on the substrate core302. The conductive connectors150may be disposed in openings in the solder resist306to be electrically and mechanically coupled to the bond pads304. The solder resist306may be used to protect areas of the substrate202from external damage.

The conductive connectors178may have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the first package component100is attached to the package substrate300. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from reflowing the conductive connectors178. In some embodiments, an underfill308may be formed between the first package component100and the package substrate300and surrounding the conductive connectors150. The underfill308may be formed by a capillary flow process after the first package component100is attached or may be formed by a suitable deposition method before the first package component100is attached.

In some embodiments, passive devices (e.g., surface mount devices (SMDs), such as the IPD181) may also be attached to the first package component100or to the package substrate300(e.g., to the bond pads304). For example, the passive devices may be bonded to a same surface of the first package component100or the package substrate300as the conductive connectors178. The passive devices may be attached to the first package component100prior to mounting the first package component100on the package substrate300, or may be attached to the package substrate300prior to or after mounting the first package component100on the package substrate300.

Embodiments may achieve advantages. Embodiments provide metal features which help dissipate heat generated from a laser drilling process for exposing dummy pads through a dielectric layer. Because the dummy pads are coupled to the metal features, the metal features act as a heat dissipation feature to pull heat from the dummy pad. As a result, reduction in heat is achieved at the dummy pad which reduces or eliminates delamination between the dummy pad and the surrounding dielectric materials. The metal features may include a variety of features, including features disposed in the same metallization layer as the dummy pad, such as a wide metal coupled to the dummy pad by metal bridges or a metal mesh coupled to the dummy pad by an interconnect. The metal features may also include features disposed in another metallization layer of the interconnect structure, including a metal mesh, a dummy interconnect (coupling together at least one other dummy pad), a dummy wire routing, a bulk metal, and a metal comb, which may be connected to the dummy pad using a metal via and optionally a feature interconnect to couple the metal via to the metal features.

One embodiment is a method including forming a first dielectric layer over a carrier. The method also includes forming a first metal layer over the first dielectric layer, the first metal layer including a dummy pad and an active pad. The method also includes forming a second dielectric layer over the first metal layer. The method also includes forming a second metal layer over the first dielectric layer, where the dummy pad of the first metal layer is physically coupled to the second metal layer. The method also includes forming a third dielectric layer over the second metal layer. The method also includes attaching a device die over the third dielectric layer. The method also includes laser drilling an opening in the first dielectric layer to expose the dummy pad. The method also includes, while laser drilling the opening, dispersing heat from the laser drilling to the second metal layer by a metal connection between the first metal layer and the second metal layer. In an embodiment, the method further includes: attaching a supporting dielectric layer to the first dielectric layer prior to the laser drilling, the supporting dielectric layer having a thickness greater than 30 µm. In an embodiment, the first metal layer includes a metal mesh aligned to the device die. In an embodiment, forming the first metal layer includes forming a wide metal, the method further including: attaching the dummy pad to the wide metal by one or more bridge metals, the one or more bridge metals physically coupling a side of the dummy pad with a side of the wide metal. In an embodiment, forming the second metal layer includes forming a via coupling the dummy pad to the second metal layer, and forming one or more heat dispersion features, the one or more heat dispersion features including a metal mesh, a dummy interconnect, a dummy routing, or a metal comb. In an embodiment, a first heat dispersion feature of the one or more heat dispersion features in the second metal layer is physically coupled to a second heat dispersion feature of the first metal layer. In an embodiment, the second heat dispersion feature is a second metal mesh or a wide metal. In an embodiment, the package is electrically coupled to the device die by a second connector coupled to the active pad.

Another embodiment is a method including forming a first metallization layer over a carrier, the first metallization layer including a first set of pads and a second set of pads, each pad of the first set of pads being an active pad, each pad of the second set of pads being a dummy pad. The method also includes forming a first dielectric layer over the first metallization layer. The method also includes forming a second metallization layer over the first dielectric layer, where each pad of the second set of pads are coupled by a metal connection to a common metal feature in the second metallization layer and/or the first metallization layer. The method also includes forming a second dielectric layer over the second metallization layer. The method also includes encapsulating a device die and a metal pillar in an encapsulant disposed over the second dielectric layer. The method also includes forming a front side interconnect over the encapsulant. The method also includes forming first connectors over the front side interconnect. In an embodiment, the common metal feature includes a wide metal disposed in the first metallization layer, where the metal connection bridges a portion of the second set of pads to the wide metal. In an embodiment, the common metal feature includes a dummy interconnect, a dummy routing, a metal mesh, or a dummy comb, and the metal connection includes a through via extending through the first dielectric layer. In an embodiment, the metal connection further includes a feature interconnect, the feature interconnect coupling a first common metal feature to a second common metal feature. In an embodiment, the common metal feature includes a first wire mesh disposed in the first metallization layer. In an embodiment, the common metal feature electrically floats. In an embodiment, the method further includes: removing the carrier; laser drilling through a third dielectric layer to expose the second set of pads through a set of openings, the laser drilling generating heat; and dispersing the heat through the metal connection to the common metal feature.

Another embodiment is a device, the device including an embedded die and a front side interconnect disposed over a front of the embedded die. The device also includes a backside interconnect disposed over a back of the embedded die. The device also includes front connectors disposed on the front side interconnect. The device also includes back connectors disposed on the backside interconnect. The device also includes a first connector of the back connectors extending through a first dielectric layer and attached to a first dummy pad. The device also includes a second connector of the back connectors extending through the first dielectric layer and attached to a second dummy pad. The device also includes a common metal feature connected to the first dummy pad and the second dummy pad. In an embodiment, the common metal feature includes one or more of a metal mesh, a wide metal, a dummy interconnect, a dummy routing, or a metal comb. In an embodiment, the device further includes: a first via, the first via coupling the first dummy pad to a first metallization layer of the backside interconnect, the first metallization layer including the common metal feature. In an embodiment, the device further includes: a first metallization including the first dummy pad, the second dummy pad, and a first metal mesh aligned over the embedded die; a second metallization including a second metal mesh and a first interconnect, the first interconnect coupled to the first dummy pad by a first via and to the second metal mesh, the second metal mesh coupled to the first metal mesh by a second via. In an embodiment, the common metal feature is in a same metallization layer as the first dummy pad and the second dummy pad, the common metal feature including a wide metal; and a set of conductive bridges, each one of the set of conductive bridges connecting the first dummy pad or the second dummy pad to the wide metal.