Integrated circuit and method of forming same

A method of forming an integrated circuit includes placing a first cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on the layout design. Placing the first cell layout design includes placing a first active region layout pattern adjacent to a first cell boundary, placing a second active region layout pattern adjacent to a second cell boundary, and placing a first set of active region layout patterns between the first and second active region layout patterns, according to a first set of guidelines. The first set of guidelines includes selecting transistors of a first type with a first driving strength and transistors of a second type with a second driving strength. In some embodiments, the first, second and first set of active region layout patterns extend in the first direction, and are on a first layout level.

BACKGROUND

The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to address issues in a number of different areas. The recent trend in miniaturizing ICs has resulted in smaller devices which consume less power yet provide more functionality at higher speeds. The miniaturization process has also resulted in stricter design and manufacturing specifications as well as reliability challenges. Various electronic design automation (EDA) tools generate, optimize and verify standard cell layout designs for integrated circuits while ensuring that the layout designs and manufacturing specifications are met.

DETAILED DESCRIPTION

In accordance with some embodiments, a method of forming an integrated circuit (IC) includes generating a first cell layout design of the integrated circuit and manufacturing the integrated circuit based on at least the first cell layout design.

In some embodiments, generating the first cell layout design includes generating a first active region layout pattern corresponding to a first set of transistors of a first type, generating a second active region layout pattern corresponding to a second set of transistors of a second type different from the first type, generating a third active region layout pattern corresponding to a third set of transistors of the first type, and generating a fourth active region layout pattern corresponding to a fourth set of transistors of the second type. In some embodiments, the first and second active region layout patterns extend in the first direction, and are adjacent to a first cell boundary of the first cell layout design. In some embodiments, the third and fourth active region layout patterns extend in the first direction, and are adjacent to a second cell boundary of the first cell layout design.

In some embodiments, at least the first, second, third or fourth active region layout pattern satisfies a first set of design guidelines. In some embodiments, the first set of design guidelines includes balancing a first driving strength of the first and second set of transistors with a second driving strength of the third and fourth set of transistors. In some embodiments, the second driving strength is different from the first driving strength. In some embodiments, balancing the first driving strength with the second driving strength results in better circuit performance than other approaches.

In some embodiments, the first set of transistors includes a first number of fins, the second set of transistors includes a second number of fins, the third set of transistors includes a third number of fins, and the fourth set of transistors includes a fourth number of fins. In some embodiments, a sum of the third and fourth number of fins is equal to a sum of the first and second number of fins thereby balancing the first driving strength of the first and second set of transistors with the second driving strength of the third and fourth set of transistors. In some embodiments, balancing the first driving strength with the second driving strength results in better circuit performance than other approaches.

FIG.1is a diagram of a layout design100, in accordance with some embodiments. Layout design100is a layout diagram of an integrated circuit, such as integrated circuit300ofFIGS.3A-3B, integrated circuit600ofFIGS.6A-6B, or integrated circuit800ofFIGS.8A-8B. In some embodiments, at least a portion of layout design100is usable to manufacture integrated circuit300(FIGS.3A-3B), integrated circuit600(FIGS.6A-6B) or integrated circuit800(FIGS.8A-8B).

Components that are the same or similar to those in each ofFIGS.1,2A-2B,3A-3B,4A-4B,5A-5B,6A-6B,7A-7B,8A-8B,9A-9C,10A-10E,11,12A-12B and13-14are given the same reference numbers, and similar detailed description thereof is thus omitted.

Layout design100A includes layout designs102a,102b,104aand104b. In some embodiments, layout design100A includes additional elements not shown inFIG.1.

In some embodiments, layout designs102aand104acorrespond to at least layout design200ofFIGS.2A-2B, layout design500ofFIGS.5A-5Bor layout design700ofFIGS.7A-7B. In some embodiments, layout designs102band104bcorrespond to at least layout design200ofFIGS.2A-2B, layout design500ofFIGS.5A-5Bor layout design700ofFIGS.7A-7B.

In some embodiments, at least layout design102a,102b,104aor104ais referred to as a cell, and is standard cell-like. In some embodiments, standard cell-like includes a cell that is not a standard cell, but exhibits some similarities to a standard cell.

Each of layout designs102a,102b,104aand104bextend in at least a first direction X. Each of layout designs102a,102b,104aand104bare separated from another of layout designs102a,102b,104aand104bin a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is the same as the first direction X.

Layout design102ahas a cell boundary101athat extends in a first direction X. In some embodiments, layout design102ais adjacent in the first direction along the cell boundary101ato other layout designs (not shown for ease of illustration).

Layout design102ais adjacent to layout design104ain the first direction X along a cell boundary101b. Layout design104ais adjacent to layout design102bin the first direction X along a cell boundary101c. Layout design102bis adjacent to layout design104bin the first direction X along cell boundary101d.

Layout design104bhas a cell boundary101ethat extends in the first direction X. In some embodiments, layout design104bis adjacent in the first direction along the cell boundary101eto other layout designs (not shown for ease of illustration).

Other configurations or quantities of layout designs102a,102b,104aand104bare within the scope of the present disclosure. For example, layout design100ofFIG.1includes one column (Column1) and four rows (Rows1-4) of cells (e.g., layout designs102a,102b,104aand104b). Other numbers of rows and/or columns in layout design100are within the scope of the present disclosure. For example, in some embodiments, layout design100includes at least an additional column of cells, similar to column1, and being adjacent to column1. For example, in some embodiments, layout design100includes additional rows of cells, similar to rows3and4, adjacent to row1along cell boundary101a. For example, in some embodiments, layout design100includes additional rows of cells, similar to rows1and2, adjacent to row4along cell boundary101e. For example, in some embodiments, layout design100includes at least an additional row of cells, similar to row3, adjacent to row4along corresponding cell boundary101e. In some embodiments, layout designs102aand104aalternate with layout designs102bor104bin the second direction Y.

Each of layout designs102aand102bhave a height H1in the second direction Y. Layout designs102aand102bare a same layout design as each other. In some embodiments, layout designs102aand102bare a different layout design from each other.

Each of layout designs104aand104bhave a height H2in the second direction Y. Height H2is different from height H1. Layout designs104aand104bare a same layout design as each other. In some embodiments, layout designs104aand104bare a different layout design from each other.

In some embodiments, layout designs102aand104ahave a height H3in the second direction Y equal to the sum of height H1and height H2. In some embodiments, layout designs102band104bhave a height H3in the second direction Y equal to the sum of height H1and height H2.

At least layout design102aor102bis useable to manufacture cell301ofFIGS.3A-3B, cell601ofFIGS.6A-6Band cell801ofFIGS.8A-8B. At least layout design104aor104bis useable to manufacture cell303ofFIGS.3A-3B, cell603ofFIGS.6A-6Band cell803ofFIGS.8A-8B.

In some embodiments, one or more of layout designs102a,102b,104aor104bis a layout design of a logic gate cell. In some embodiments, a logic gate cell includes an AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, Flip-flop, BUFF, Latch, delay, or clock cells. In some embodiments, one or more of layout designs102a,102b,104aor104bis a layout design of a memory cell. In some embodiments, a memory cell includes a static random access memory (SRAM), a dynamic RAM (DRAM), a resistive RAM (RRAM), a magnetoresistive RAM (MRAM) or read only memory (ROM). In some embodiments, one or more of layout designs102a,102b,104aor1084bincludes layout designs of one or more active or passive elements. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), finFETs, and planar MOS transistors with raised source/drain. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, and resistors.

FIGS.2A-2Bare diagrams of a layout design, in accordance with some embodiments.

FIGS.2A-2Bare diagrams of a layout design200of an integrated circuit300ofFIGS.3A-3B, in accordance with some embodiments.

Layout design200is an embodiment of layout designs102aand104aofFIG.1or layout designs102band104bofFIG.1.

Layout design200is usable to manufacture integrated circuit300.

For ease of illustration, some of the labeled elements ofFIG.2A-2B,3A-3B,5A-5B,6A-6B,7A-7B or8A-8Bare not labelled in at leastFIG.2A-2B,3A-3B,5A-5B,6A-6B,7A-7B or8A-8B. In some embodiments,FIG.2A-2B,3A-3B,5A-5B,6A-6B,7A-7B or8A-8Bincludes additional elements that are not shown.

FIG.2Ais a diagram of a portion200A of layout design200ofFIGS.2A-2B, simplified for ease of illustration. For example, in comparison withFIG.2B, portion200A ofFIG.2Adoes not show a set of conductive feature layout patterns230and232ofFIG.2Bfor ease of illustration.

Layout design200has a height H3in the second direction Y. Layout design200includes a cell layout design201and a cell layout design203. Cell layout design201has a height H1in the second direction Y, and cell layout design203has a height H2in the second direction Y.

Cell layout design201is an embodiment of layout design102aor104aofFIG.1. Cell layout design203is an embodiment of layout design102bor104bofFIG.1. Cell layout design201or203is a layout design of corresponding cell301or303(FIGS.3A-3B), in accordance with some embodiments. Cell layout design201or203is usable to manufacture corresponding cell301or303(FIGS.3A-3B), in accordance with some embodiments.

Layout design200further includes active region layout patterns202aand202b(collectively referred to as a “set of active region layout patterns202”) extending in the first direction X. Active region layout patterns202aand202bof the set of active region layout patterns202are separated from one another in the second direction Y. Active region layout pattern202aor202bis usable to manufacture corresponding active region302aor302bof a set of active regions302(FIGS.3A-3B). In some embodiments, the set of active region layout patterns202is referred to as an oxide diffusion (OD) region which defines source or drain diffusion regions of an integrated circuit400B (FIG.4B). In some embodiments, active region layout pattern202aor202bis usable to manufacture an active region412(FIG.4B) of integrated circuit400B.

Layout design200further includes active region layout patterns204aand204b(collectively referred to as a “set of active region layout patterns204”) extending in the first direction X. Active region layout patterns204aand204bof the set of active region layout patterns204are separated from one another in the second direction Y. Active region layout pattern204aor204bis usable to manufacture corresponding active region304aor304bof a set of active regions304(FIGS.3A-3B). In some embodiments, the set of active region layout patterns204defines source or drain diffusion regions of integrated circuit400B (FIG.4B). In some embodiments, active region layout pattern204aor204bis usable to manufacture active region412(FIG.4B) of integrated circuit400B.

Layout design200further includes active region layout patterns206aand206b(collectively referred to as a “set of active region layout patterns206”) extending in the first direction X. Active region layout patterns206aand206bof the set of active region layout patterns206are separated from one another in the second direction Y. Active region layout pattern206aor206bis usable to manufacture corresponding active region306aor306bof a set of active regions306(FIGS.3A-3B). In some embodiments, the set of active region layout patterns206defines source or drain diffusion regions of an integrated circuit400A (FIG.4A). In some embodiments, active region layout pattern206aor206bis usable to manufacture an active region402(FIG.4A) of integrated circuit400A.

Layout design200further includes active region layout patterns208aand208b(collectively referred to as a “set of active region layout patterns208”) extending in the first direction X. Active region layout patterns208aand208bof the set of active region layout patterns208are separated from one another in the second direction Y. Active region layout pattern208aor208bis usable to manufacture corresponding active region308aor308bof a set of active regions308(FIGS.3A-3B). In some embodiments, the set of active region layout patterns208defines source or drain diffusion regions of integrated circuit400B (FIG.4B). In some embodiments, active region layout pattern208aor208bis usable to manufacture active region412(FIG.4B) of integrated circuit400B.

Layout design200further includes active region layout patterns210aand210b(collectively referred to as a “set of active region layout patterns210”) extending in the first direction X. Active region layout patterns210aand210bof the set of active region layout patterns210are separated from one another in the second direction Y. Active region layout pattern210aor210bis usable to manufacture corresponding active region310aor310bof a set of active regions310(FIGS.3A-3B). In some embodiments, the set of active region layout patterns210defines source or drain diffusion regions of an integrated circuit400B (FIG.4B). In some embodiments, active region layout pattern210aor210bis usable to manufacture active region412(FIG.4B) of integrated circuit400B.

In some embodiments, active region layout patterns202a,204a,204band206aare part of cell layout design201. In some embodiments, active region layout patterns206b,208a,208band210aare part of cell layout design203. In some embodiments, active region layout pattern202bis part of a cell layout design different from cell layout design201or203. In some embodiments, active region layout pattern210bis part of another cell layout design different from cell layout design201or203.

In some embodiments, set of active region layout patterns202,206and210correspond to set of active regions302,306and310of a first device type, and the set of active region layout patterns204and208correspond to set of active regions304and308of a second device type different from the first device type, respectively.

In some embodiments, the first device type is an n-type finFET and the second device type is a p-type finFET. For example, in some embodiments, active region layout patterns202a,202b,206a,206b,210aand210bcorrespond to active regions302a,302b,306a,306b,310aand310bof n-type finFET transistors, and active region layout patterns204a,204b,208aand208bcorrespond to active regions304a,304b,308aand308bof p-type finFET transistors, respectively. In some embodiments, at least active region layout pattern202a,202b,206a,206b,210aand210bis usable to manufacture corresponding active regions302a,302b,306a,306b,310aand310b(e.g., source and drain regions of n-type finFET transistors), and at least active region layout pattern204a,204b,208aand208bis usable to manufacture corresponding active regions304a,304b,308aand308b(e.g., source and drain regions of p-type finFET transistors).

In some embodiments, the first device type is a p-type finFET and the second device type is an n-type finFET. For example, in some embodiments, active region layout patterns202a,202b,206a,206b,210aand210bcorrespond to active regions302a,302b,306a,306b,310aand310bof p-type finFET transistors, and active region layout patterns204a,204b,208aand208bcorrespond to active regions304a,304b,308aand308bof n-type finFET transistors, respectively. In some embodiments, at least active region layout pattern202a,202b,206a,206b,210aand210bis usable to manufacture corresponding active regions302a,302b,306a,306b,310aand310b(e.g., source and drain regions of p-type finFET transistors), and at least active region layout pattern204a,204b,208aand208bis usable to manufacture corresponding active regions304a,304b,308aand308b(e.g., source and drain regions of n-type finFET transistors). In some embodiments, a different transistor type for at least the set of active region layout patterns202,204,206,208or210or the set of active regions302,304,306,308or310is within the scope of the present disclosure.

In some embodiments, at least active region layout pattern202a,202b,204a,204b,208a,208b,210aor210bis usable to manufacture fins412a1,412a2and412a3of active region412(FIG.4B). In some embodiments, at least active region layout pattern206aor206bis usable to manufacture fins402a1and402a2of active region402(FIG.4A).

While the set of active region layout patterns202,204,206,208and210ofFIGS.2A-2B, are described as being usable to manufacture fins of active regions402and412ofFIGS.4A-4B, it is understood that the fins of active region402or412can be replaced with corresponding nanosheets or nanowires. For example, in some embodiments, at least active region layout pattern202a,202b,204a,204b,208a,208b,210aor210bis usable to manufacture nanosheets (not shown) for active region412of a nanosheet transistor. For example, in some embodiments, at least active region layout pattern206aor206bis usable to manufacture nanosheets (not shown) for active region402of a nanosheet transistor. For example, in some embodiments, at least active region layout pattern202a,202b,204a,204b,208a,208b,210aor210bis usable to manufacture nanowire (not shown) for active region412of a nanowire transistor. For example, in some embodiments, at least active region layout pattern206aor206bis usable to manufacture nanowire (not shown) for active region402of a nanowire transistor.

Active region layout patterns202a,202b,204a,204b,208a,208b,210aand210beach have a width W2ain the second direction Y. In some embodiments, the width W2aof at least one of active region layout pattern202a,202b,204a,204b,208a,208b,210aor210bis different from the width W2bof at least another of active region layout pattern202a,202b,204a,204b,208a,208b,210aor210b.

Active region layout patterns206aand206beach have a width W2bin the second direction Y. In some embodiments, the widths W2bof active region layout patterns206aand206bare different from each other.

The width W2ais greater than the width W2b. In some embodiments, at least the width W2aof active region layout patterns202a,202b,204a,204b,208a,208b,210aand210bis directly related to the number of fin layout patterns (not shown) useable to manufacture corresponding fins in active region412. In some embodiments, the width W2aof active region layout patterns202a,202b,204a,204b,208a,208b,210aand210bis related to the number of conducting devices (e.g., transistors) manufactured by the set of active region layout patterns202,204,208and210and the corresponding speed and driving strength of the conducting devices (e.g., transistors) in the active regions302,304,308and310.

In some embodiments, at least the width W2bof active region layout patterns206aand206bis directly related to the number of fin layout patterns (not shown) useable to manufacture corresponding fins in active region402. In some embodiments, the width W2bof active region layout patterns206aand206bis related to the number of conducting devices (e.g., transistors) manufactured by the set of active region layout patterns206and the corresponding speed and driving strength of the conducting devices (e.g., transistors) in the active regions306.

For example, in some embodiments, an increase in the width W2aof active region layout patterns202a,202b,204a,204b,208a,208b,210aand210bor the width W2aof active region layout patterns206aand206bcauses the number of fins and the number of conducting devices (e.g., transistors) manufactured by set of active region layout patterns202,204,206,208and210to increase, and the corresponding speed and driving strength of the conducting devices (e.g., transistors) increases.

For example, in some embodiments, a decrease in the width W2aof active region layout patterns202a,202b,204a,204b,208a,208b,210aand210bor the width W2aof active region layout patterns206aand206bcauses the number of fins and the number of conducting devices (e.g., transistors) manufactured by set of active region layout patterns202,204,206,208and210to decrease, and the corresponding speed and driving strength of the conducting devices (e.g., transistors) decreases.

In some embodiments, since the width W2ais greater than the width W2bresults in an asymmetric active region within cell layout design201or203. For example, within cell layout design201or203, the width W2aof active region layout patterns in the set of active region layout patterns202,204,208and210and the width W2bof active region layout patterns in the set of active region layout patterns206is different resulting in an asymmetric or mixed width active region and corresponding active region layout patterns.

In some embodiments, at least one of the active region layout patterns in the set of active region layout patterns202,204,208or210is useable to manufacture a corresponding set of active regions302,304,308or310having m fins, and at least one of the active region layout patterns in the set of active region layout patterns206is useable to manufacture a corresponding set of active regions306having n fins, where m is an integer and n is another integer. In some embodiments, integer m is not equal to integer n resulting in cell layout design201or203having asymmetric active region layout patterns or cell301or303having asymmetric active regions.

For example, in some embodiments, integer m is equal to 3 and integer n is equal to 2 in layout design200or integrated circuit300, such that the set of active region layout patterns202,204,208and210are useable to manufacture corresponding set of active regions302,304,308and310having 3 fins, and the set of active region layout patterns206are useable to manufacture corresponding set of active regions306having 2 fins. Other values for at least integer m or integer n are within the scope of the present disclosure.

In some embodiments, in cell layout design201or203, a sum of the widths of the set of active region layout patterns202,204,206,208and210of the first device type is different from a sum of widths of the set of active region layout patterns202,204,206,208and210of the second device type resulting in the first device type and the second device type having asymmetric active region layout patterns within cell layout design201or203or asymmetric active regions within cell301and303.

For example, in some embodiments, the first device type is an n-type finFET and the second device type is a p-type finFET, and the sum of the widths of active region layout patterns202aand206a(which is equal to a sum of W2aand W2b) is less than the sum of the widths of active region layout patterns204aand204b(which is equal to 2*W2a), and thus for cell layout design201, the strength of the n-type finFETs is less than the strength of the p-type finFETs. In these embodiments, for cell layout design203the strength of the n-type finFETs is less than the strength of the p-type finFETs for reasons similar to cell layout design201, and are omitted for brevity.

For example, in some embodiments, the first device type is a p-type finFET and the second device type is an n-type finFET, and the sum of the widths of active region layout patterns202aand206a(which is equal to a sum of W2aand W2b) is less than the sum of the widths of active region layout patterns204aand204b(which is equal to 2*W2a), and thus for cell layout design201, the strength of the p-type finFETs is less than the strength of the n-type finFETs. In these embodiments, for cell layout design203the strength of the p-type finFETs is less than the strength of the n-type finFETs for reasons similar to cell layout design201, and are omitted for brevity.

In some embodiments, in cell layout design201or203, a sum of a number of fins of the manufactured by the set of active region layout patterns202,204,206,208or210of the first device type is different from a sum of a number of fins manufactured by the set of active region layout patterns202,204,206,208or210of the second device type resulting in the first device type and the second device type having asymmetric active region layout patterns within cell layout design201or203or asymmetric active regions within cell301and303.

For example, in some embodiments, the first device type is an n-type finFET and the second device type is a p-type finFET, and the sum of the fins of active region layout patterns202aand206aor active regions302aand306a(which is equal to 5 (e.g., a sum of 3 and 2)) is less than the sum of the fins of active region layout patterns204aand204bor active regions304aand304b(which is equal to 6 (e.g., a sum of 3 and 3)), and thus for cell layout design201, the strength of the n-type finFETs is less than the strength of the p-type finFETs. In these embodiments, for cell layout design203the strength of the n-type finFETs is less than the strength of the p-type finFETs for reasons similar to cell layout design201, and are omitted for brevity.

In these embodiments, if the first device type is an n-type finFET and the second device type is a p-type finFET, then a number of n-type finFETs manufactured by the set of active region layout patterns202,206and210is less than or equal to a number of p-type finFETs manufactured by the set of active region layout patterns204and208.

For example, in some embodiments, the first device type is a p-type finFET and the second device type is an n-type finFET, and the sum of the fins of active region layout patterns202aand206aor active regions302aand306a(which is equal to 5 (e.g., a sum of 3 and 2)) is less than the sum of the fins of active region layout patterns204aand204bor active regions304aand304b(which is equal to 6 (e.g., a sum of 3 and 3)), and thus for cell layout design201, the strength of the p-type finFETs is less than the strength of the n-type finFETs. In these embodiments, for cell layout design203the strength of the p-type finFETs is less than the strength of the n-type finFETs for reasons similar to cell layout design201, and are omitted for brevity.

In these embodiments, if the first device type is a p-type finFET and the second device type is an n-type finFET, then a number of p-type finFETs manufactured by the set of active region layout patterns202,206and210is less than or equal to a number of n-type finFETs manufactured by the set of active region layout patterns204and208.

Thus, asymmetric active region layout patterns and corresponding asymmetric active regions may result in a possible unbalanced device strength between the n-type finFET devices and the p-type finFET devices. However, by using the features of layout design200, the widths W2aand W2bor number of fins (e.g., integer m or integer n) are selected or adjusted to better balance the n-type finFET and p-type finFET device strengths compared to other approaches resulting in better circuit performance than other approaches.

For example, in some embodiments, the location of n-type or p-type finFET devices (e.g., active region layout patterns202a,206a,206band210aare positioned at cell boundaries (e.g., cell boundary101a,101b,101c,101dor101e) to better balance any mismatch between the number of widths W2aand W2bor the number of fins in layout design200compared to other approaches.

In some embodiments, the first device type is an n-type finFET and the second device type is a p-type finFET, and the location of n-type finFETs (e.g., active region layout patterns202a,206a,206band210aare positioned at cell boundaries (e.g., cell boundary101a,101b,101c,101dor101e) to better balance the mismatch between the number of widths W2aand W2bor the number of fins in layout design200compared to other approaches.

In some embodiments, the first device type is a p-type finFET and the second device type is an n-type finFET, and the location of p-type finFETs (e.g., active region layout patterns202a,206a,206band210aare positioned at cell boundaries (e.g., cell boundary101a,101b,101c,101dor101e) to better balance the mismatch between the number of widths W2aand W2bor the number of fins in layout design200compared to other approaches.

In some embodiments, the set of active region layout patterns202is located on a first level. In some embodiments, the first level corresponds to an active level or an OD level of one or more of layout designs100,200,500,700,900A-900C,1000A-1000E or1200B (FIG.1,2A-2B,5A-5B,7A-7B,9A-9C,10A-10E or12B) or integrated circuit300,400A-400B,600or800(FIG.3A-3B,4A-4B,6A-6B or8A-8B).

Other configurations or quantities of patterns in at least set of active region layout patterns202,204,206,208or210are within the scope of the present disclosure.

Layout design200A further includes at least conductive feature layout patterns220a,220b,220c,220dor220e(collectively referred to as a “set of conductive feature layout patterns220”) extending in the first direction X. In some embodiments, the set of conductive feature layout patterns220is also referred to as a set of power rail layout patterns.

The set of conductive feature layout patterns220is usable to manufacture the set of conductive structures320of integrated circuit300(FIGS.3A-3B). In some embodiments, conductive feature layout patterns220a,220b,220c,220dand220eare usable to manufacture corresponding conductive structures320a,320b,320c,320dand320eof integrated circuit300(FIGS.3A-3B).

In some embodiments, the set of conductive feature layout patterns220is over at least the set of active region layout patterns202,204,206,208or210. In some embodiments, each conductive feature layout pattern of the set of conductive feature layout patterns220is separated from an adjacent layout pattern of the set of conductive feature layout patterns220in at least the second direction Y.

Each conductive feature layout pattern of the set of conductive feature layout patterns220has a corresponding width W1in the second direction Y. In some embodiments, at least one conductive feature layout pattern of the set of conductive feature layout patterns220has a corresponding width 2*W1in the second direction Y.

In some embodiments, each conductive feature layout pattern of the set of conductive feature layout patterns220has width W1. In some embodiments, at least one width W1of a conductive feature layout pattern of the set of conductive feature layout patterns220differs from at least one width W1of another conductive feature layout pattern of the set of conductive feature layout patterns220.

Conductive feature layout pattern220ais between active region layout pattern202aand active region layout pattern202b. Conductive feature layout pattern220bis between active region layout pattern204aand active region layout pattern204b. Conductive feature layout pattern220cis between active region layout pattern206aand active region layout pattern206b. Conductive feature layout pattern220dis between active region layout pattern208aand active region layout pattern208b. Conductive feature layout pattern220eis between active region layout pattern210aand active region layout pattern210b.

In some embodiments, conductive feature layout patterns220a,220cand220ecorrespond to a first supply voltage, and conductive feature layout patterns220band220dcorrespond to a second supply voltage different from the first supply voltage. In some embodiments, the first supply voltage is supply voltage VDD, and the second supply voltage is reference supply voltage VSS. In some embodiments, the first supply voltage is reference supply voltage VSS, and the second supply voltage is supply voltage VDD.

In some embodiments, the first device type or the second device type of the set of active region layout patterns202,204,206,208and210determines whether conductive feature layout patterns220a,220b,220c,220dand220ecorrespond to supply voltage VDD or reference supply voltage VSS. For example, if the set of active region layout patterns202,206and210correspond to n-type finFETs (e.g., the first device type), and the set of active region layout patterns204and208correspond to p-type finFETs (e.g., the second device type), then the first supply voltage is reference supply voltage VSS, the second supply voltage is supply voltage VDD, conductive feature layout patterns220a,220cand220ecorrespond to reference supply voltage VSS, and conductive feature layout patterns220band220dcorrespond to supply voltage VDD.

For example, if the set of active region layout patterns202,206and210correspond to p-type finFETs (e.g., the second device type), and the set of active region layout patterns204and208correspond to n-type finFETs (e.g., the first device type), then the first supply voltage is supply voltage VDD, the second supply voltage is reference supply voltage VSS, conductive feature layout patterns220a,220cand220ecorrespond to supply voltage VDD, and conductive feature layout patterns220band220dcorrespond to reference supply voltage VSS.

Conductive feature layout pattern220aoverlaps cell boundary101aor101c. Conductive feature layout pattern220coverlaps cell boundary101bor101d. Conductive feature layout pattern220eoverlaps cell boundary101cor101e.

In some embodiments, conductive feature layout pattern220boverlaps a mid-point in the second direction Y of cell layout design201. In some embodiments, the mid-point in the second direction Y of layout design201is a mid-point between cell boundary101aor101cand cell boundary101bor101din the second direction Y.

In some embodiments, conductive feature layout pattern220doverlaps a first mid-point in the second direction Y of cell layout design203. In some embodiments, the mid-point in the second direction Y of layout design203is a mid-point between cell boundary101bor101dand cell boundary101cor101ein the second direction Y.

In some embodiments, a center of conductive feature layout pattern220ais aligned with cell boundary101aor101c. In some embodiments, the center of conductive feature layout pattern220ais separated from the active region layout pattern202bor202ain the second direction Y by at least a corresponding distance d7or d8.

In some embodiments, a center of conductive feature layout pattern220bis aligned with the mid-point in the second direction Y of cell layout design201. In some embodiments, the center of conductive feature layout pattern220bis separated from the active region layout pattern204aor204bin the second direction Y by at least a corresponding distance d1or d2.

In some embodiments, a center of conductive feature layout pattern220cis aligned with cell boundary101bor101d. In some embodiments, the center of conductive feature layout pattern220cis separated from the active region layout pattern206aor206bin the second direction Y by at least a corresponding distance d3or d4.

In some embodiments, a center of conductive feature layout pattern220dis aligned with the mid-point in the second direction Y of cell layout design203. In some embodiments, the center of conductive feature layout pattern220dis separated from the active region layout pattern208aor208bin the second direction Y by at least a corresponding distance d5or d6.

In some embodiments, a center of conductive feature layout pattern220eis aligned with cell boundary101cor101e. In some embodiments, the center of conductive feature layout pattern220eis separated from the active region layout pattern210aor210bin the second direction Y by at least a corresponding distance d7or d8.

In some embodiments, conductive feature layout patterns220a,220b,220c,220dand220eare placed between corresponding set of active region layout patterns202,204,206,208and210according to a set of design guidelines (described below inFIGS.10A-10E).

In some embodiments, by placing conductive feature layout pattern220a,220b,220c,220dor220ebetween corresponding set of active region layout patterns202,204,206,208or210, a difference between corresponding distances d7and d8, d1and d2, d3and d4, d5and d6, & d7and d8is reduced, resulting in a more balanced current resistance (IR) drop across the corresponding n-type or p-type finFETs and corresponding conductive structures320a,320b,320c,320dor320ethereby yielding better performance than other approaches with unbalanced IR drops.

The set of conductive feature layout patterns220is on a second level different from the first level. In some embodiments, the second level corresponds to the metal zero (M0) level of one or more of layout designs100,200,500,700,900A-900C,1000A-1000E or1200B (FIG.1,2A-2B,5A-5B,7A-7B,9A-9C,10A-10E or12B) or integrated circuit300,400A-400B,600or800(FIG.3A-3B,4A-4B,6A-6B or8A-8B). Other levels, quantities or configurations of the set of conductive feature layout patterns220are within the scope of the present disclosure.

Layout design200further includes at least conductive feature layout patterns230a,230b,230c,230d,230eor230f(collectively referred to as a “set of conductive feature layout patterns230”) extending in the first direction X. In some embodiments, the set of conductive feature layout patterns230is also referred to as a first set of pin layout patterns.

The set of conductive feature layout patterns230are located on the second level. The set of conductive feature layout patterns230is usable to manufacture a corresponding set of conductive structures330(FIGS.3A-3B) of integrated circuit300. Conductive feature layout patterns230a,230b,230c,230d,230e,230fare usable to manufacture corresponding conductive structures330a,330b,330c,330d,330e,330f(FIGS.3A-3B).

Each conductive feature layout pattern of the set of conductive feature layout patterns230is separated from an adjacent conductive feature layout pattern of the set of conductive feature layout patterns230or an adjacent conductive feature layout pattern of the set of conductive feature layout patterns220in the second direction Y by a same pitch (not labelled) and are therefore evenly distributed. In some embodiments, at least one conductive feature layout pattern of the set of conductive feature layout patterns230is separated from an adjacent conductive feature layout pattern of the set of conductive feature layout patterns230or an adjacent conductive feature layout pattern of the set of conductive feature layout patterns220in the second direction Y by a pitch different from the same pitch.

The set of conductive feature layout patterns230overlaps set of active region layout patterns202,204and206. Conductive feature layout pattern230a,230c,230d,230foverlaps corresponding active region layout pattern202a,204a,204b,206a.

Conductive feature layout patterns230a,230band230care between conductive feature layout pattern220aand conductive feature layout pattern220b. Conductive feature layout patterns230d,230eand230fare between conductive feature layout pattern220band conductive feature layout pattern220c.

In some embodiments, the set of conductive feature layout patterns230overlaps other underlying layout patterns (not shown) of other layout levels (e.g., MD, or the like) of layout design200. In some embodiments, each layout pattern230a,230b,230c,230d,230e,230fof the set of conductive feature layout patterns230has a width W3in the second direction Y.

In some embodiments, each layout pattern230a,230b,230c,230d,230e,230fof the set of conductive feature layout patterns230overlaps a corresponding gridline (not shown) of a set of gridlines (not shown). In some embodiments, a center of each layout pattern230a,230b,230c,230d,230e,230fof the set of conductive feature layout patterns230is aligned in the first direction X with a corresponding gridline (not shown) of the set of gridlines (not shown).

In some embodiments, layout patterns230a,230b,230c,230d,230eand230fof the set of conductive feature layout patterns230correspond to 6 M0 routing tracks in cell layout design201. Other numbers of routing tracks in the set of conductive feature layout patterns230are within the scope of the present disclosure.

The set of conductive feature layout patterns230is on the second level. Other levels, quantities or configurations of the set of conductive feature layout patterns230are within the scope of the present disclosure.

Layout design200further includes at least conductive feature layout patterns232a,232b,232c,232d,232eor232f(collectively referred to as a “set of conductive feature layout patterns232”) extending in the first direction X. In some embodiments, the set of conductive feature layout patterns232is also referred to as a second set of pin layout patterns.

The set of conductive feature layout patterns232is usable to manufacture a corresponding set of conductive structures332(FIGS.3A-3B) of integrated circuit300. Conductive feature layout patterns232a,232b,232c,232d,232e,232fare usable to manufacture corresponding conductive structures332a,332b,332c,332d,332e,332f(FIGS.3A-3B).

Each conductive feature layout pattern of the set of conductive feature layout patterns232is separated from an adjacent conductive feature layout pattern of the set of conductive feature layout patterns232or an adjacent conductive feature layout pattern of the set of conductive feature layout patterns220in the second direction Y by a same pitch (not labelled) and are therefore evenly distributed. In some embodiments, at least one conductive feature layout pattern of the set of conductive feature layout patterns232is separated from an adjacent conductive feature layout pattern of the set of conductive feature layout patterns232or an adjacent conductive feature layout pattern of the set of conductive feature layout patterns220in the second direction Y by a pitch different from the same pitch.

The set of conductive feature layout patterns232overlaps set of active region layout patterns206,208and210. Conductive feature layout pattern232a,232c,232d,232foverlaps corresponding active region layout pattern206b,208a,208b,210a.

Conductive feature layout patterns232a,232band232care between conductive feature layout pattern220cand conductive feature layout pattern220d. Conductive feature layout patterns232d,232eand232fare between conductive feature layout pattern220dand conductive feature layout pattern220e.

In some embodiments, the set of conductive feature layout patterns232overlaps other underlying layout patterns (not shown) of other layout levels (e.g., MD, or the like) of layout design200. In some embodiments, each layout pattern232a,232b,232c,232d,232e,232fof the set of conductive feature layout patterns232has a width W3in the second direction Y.

In some embodiments, each layout pattern232a,232b,232c,232d,232e,232fof the set of conductive feature layout patterns232overlaps a corresponding gridline (not shown) of a set of gridlines (not shown). In some embodiments, a center of each layout pattern232a,232b,232c,232d,232e,232fof the set of conductive feature layout patterns232is aligned in the first direction X with a corresponding gridline (not shown) of the set of gridlines (not shown).

In some embodiments, layout patterns232a,232b,232c,232d,232eand232fof the set of conductive feature layout patterns232correspond to 6 M0 routing tracks in cell layout design203. Other numbers of routing tracks in the set of conductive feature layout patterns232are within the scope of the present disclosure.

The set of conductive feature layout patterns232is on the second level. Other levels, quantities or configurations of the set of conductive feature layout patterns232are within the scope of the present disclosure.

FIGS.3A-3Bare diagrams of a top view of an integrated circuit300, in accordance with some embodiments.

FIG.3Ais a diagram of a portion300A of integrated circuit300ofFIGS.3A-3B, simplified for ease of illustration. For example, in comparison withFIG.3B, portion300A ofFIG.3Adoes not show a set of conductive structures330and332ofFIG.3Bfor ease of illustration.

In some embodiments,FIGS.3A-3Bshow one or more features of integrated circuit300of the active region (OD) level and M0 level of integrated circuit300or layout design200for ease of illustration. In other words, in some embodiments, integrated circuit300does not show at least gates and contacts for ease of illustration.

Integrated circuit300is manufactured by layout design200. Structural relationships including alignment, distances, lengths and widths, as well as configurations of at least integrated circuit300ofFIGS.3A-3B,400A-400BofFIGS.4A-4B,600ofFIGS.6A-6B,800ofFIGS.8A-8Bare similar to the corresponding structural relationships and corresponding configurations of at least layout design100ofFIG.1,200ofFIGS.2A-2B,500ofFIGS.5A-5B,700ofFIGS.7A-7B,900A-900CofFIGS.9A-9C,1000A-1000EofFIGS.10A-10E or1200BofFIG.12B, and similar detailed description will not be described inFIGS.1,2A-2B,3A-3B,4A-4B,5A-5B,6A-6B,7A-7B,8A-8B,9A-9B,10A-10E and12Bfor brevity.

Integrated circuit300has a height H3′ in the second direction Y. Integrated circuit300includes a cell301and a cell303. Cell301has a height H1′ in the second direction Y, and cell303has a height H2′ in the second direction Y. In some embodiments, the height H1′ of cell301is different from the height H2′ of cell303.

Integrated circuit300further includes at least active regions302aand302b(collectively referred to as a “set of active regions302”), active regions304aand304b(collectively referred to as a “set of active regions304”), active regions306aand306b(collectively referred to as a “set of active regions306”), active regions308aand308b(collectively referred to as a “set of active regions308”) or active regions310aand310b(collectively referred to as a “set of active regions310”).

In some embodiments, the set of active regions302,304,308or310defines source or drain diffusion regions of integrated circuit400B (FIG.4B). In some embodiments, at least active region302a,302b,304a,304b,308a,308b,310aor310bincludes active region412(FIG.4B) of integrated circuit400B. In some embodiments, at least active region302a,302b,304a,304b,308a,308b,310aor310bincludes fins412a1,412a2and412a3of active region412(FIG.4B).

In some embodiments, the set of active regions306defines source or drain diffusion regions of integrated circuit400A (FIG.4A). In some embodiments, at least active region306aor306bincludes active region402(FIG.4A) of integrated circuit400A. In some embodiments, at least active region306aor306bincludes fins402a1and402a2of active region402(FIG.4A).

In some embodiments, active regions302a,304a,304band306aare part of cell301. In some embodiments, active regions306b,308a,308band310aare part of cell303. In some embodiments, active region302bis part of a cell different from cell301or303. In some embodiments, active region312bis part of another cell different from cell301or303.

Active regions302a,302b,304a,304b,308a,308b,310aand310beach have a width W2a′ in the second direction Y. In some embodiments, the width W2a′ of at least one of active region302a,302b,304a,304b,308a,308b,310aor310bis different from the width W2a′ of at least another of active region302a,302b,304a,304b,308a,308b,310aor310b.

Active regions306aand306beach have a width W2b′ in the second direction Y. In some embodiments, the widths W2b′ of active regions306aand306bare different from each other.

The width W2a′ is greater than the width W2b′. In some embodiments, the relationship between at least the width W2a′ of active regions302a,302b,304a,304b,308a,308b,310aand310band the width W2b′ of active regions306aand306bis similar to the width W2aof active region layout patterns202a,202b,204a,204b,208a,208b,210aand210band the width W2bof active region layout patterns206aand206bofFIGS.2A-2B, and similar detailed description is omitted for brevity.

In some embodiments, the relationship between at least the number of fins and resulting driving strength of active regions302a,302b,304a,304b,308a,308b,310aand310band the number of fins and resulting driving strength of active regions306aand306bis similar to the corresponding number of fin layout patterns (not shown) and driving strength of width W2aof active region layout patterns202a,202b,204a,204b,208a,208b,210aand210band the corresponding number of fin layout patterns (not shown) and driving strength of width W2bof active region layout patterns206aand206b, and similar detailed description is omitted for brevity.

In some embodiments, at least the width W2a′ of active regions302a,302b,304a,304b,308a,308b,310aand310bis directly related to the number of corresponding fins in active region412, and at least the width W2b′ of active regions306aand306bis directly related to the number of corresponding fins in active region402.

In some embodiments, an increase (or decrease) in the width W2a′ of active regions302a,302b,304a,304b,308a,308b,310aand310bor the width W2a′ of active regions306aand306bcauses the number of fins and the number of conducting devices (e.g., transistors) in the set of active regions302,304,306,308and310to increase (or decrease), and the corresponding speed and driving strength of the conducting devices (e.g., transistors) increases (or decreases).

In some embodiments, since the width W2a′ is greater than the width W2b′ results in an asymmetric active region within cell301or303. For example, within cell301or303, the width W2a′ of active regions in the set of active regions302,304,308and310and the width W2b′ of active regions in the set of active regions306is different resulting in an asymmetric or mixed width active region.

In some embodiments, in cell301or303, a sum of the widths of the set of active regions302,304,306,308and310of the first device type is different from a sum of widths of the set of active regions302,304,306,308and310of the second device type resulting in the first device type and the second device type having asymmetric active regions with different corresponding device strengths within cell301or303, and is similar to the asymmetric active region layout pattern description ofFIGS.2A-2B, and similar detailed description is omitted for brevity.

In some embodiments, in cell301or303, a sum of the number of fins of the set of active regions302,304,306,308and310of the first device type is different from a sum of the number of fins of the set of active regions302,304,306,308and310of the second device type resulting in the first device type and the second device type having asymmetric active regions with different corresponding device strengths within cell301or303, and is similar to the description ofFIGS.2A-2Bof asymmetric active region layout patterns with different numbers of fins, and similar detailed description is omitted for brevity.

For example, in some embodiments, the first device type is an n-type finFET and the second device type is a p-type finFET, for cell301the strength of the n-type finFETs is less than the strength of the p-type finFETs for reasons similar to cell layout design201, and for cell303the strength of the n-type finFETs is less than the strength of the p-type finFETs for reasons similar to cell layout design203, and are omitted for brevity.

For example, in some embodiments, the first device type is a p-type finFET and the second device type is an n-type finFET, for cell301the strength of the p-type finFETs is less than the strength of the n-type finFETs for reasons similar to cell layout design201, and for cell303the strength of the p-type finFETs is less than the strength of the n-type finFETs for reasons similar to cell layout design203, and are omitted for brevity.

Asymmetric active regions may result in a possible unbalanced device strength between the n-type finFET devices and the p-type finFET devices. However, by using the features of integrated circuit300, the widths W2a′ and W2b′ or number of fins (e.g., integer m or integer n) are selected or adjusted to better balance the n-type finFET and p-type finFET device strengths compared to other approaches resulting in better circuit performance than other approaches.

For example, in some embodiments, the location of n-type or p-type finFET devices (e.g., active regions302a,306a,306band310aare positioned at cell boundaries (e.g., cell boundary101a,101b,101c,101dor101e) to better balance any mismatch between the number of widths W2a′ and W2b′ or the number of fins in integrated circuit300compared to other approaches.

In some embodiments, the first device type is an n-type finFET and the second device type is a p-type finFET, and the location of n-type finFETs (e.g., active regions302a,306a,306band310aare positioned at cell boundaries (e.g., cell boundary101a,101b,101c,101dor101e) to better balance the mismatch between the number of widths W2a′ and W2b′ or the number of fins in integrated circuit300compared to other approaches.

In some embodiments, the first device type is a p-type finFET and the second device type is an n-type finFET, and the location of p-type finFETs (e.g., active regions302a,306a,306band310aare positioned at cell boundaries (e.g., cell boundary101a,101b,101c,101dor101e) to better balance the mismatch between the number of widths W2a′ and W2b′ or the number of fins in integrated circuit300compared to other approaches.

In some embodiments, the set of active regions302is located on the first level. Other configurations or quantities of patterns in at least set of active regions302,304,306,308or310are within the scope of the present disclosure.

Integrated circuit300further includes at least conductive structure320a,320b,320c,320dor320e(collectively referred to as a “set of conductive structures320”), at least conductive structure330a,330b,330c,330d,330eor330f(collectively referred to as a “set of conductive structures330”) or at least conductive structure332a,332b,332c,332d,332eor332f(collectively referred to as a “set of conductive structures332”).

In some embodiments, the set of conductive structures320is over at least the set of active regions302,304,306,308or310. Each conductive structure of the set of conductive structures320has a corresponding width W1′in the second direction Y. In some embodiments, at least one conductive structure of the set of conductive structures320has a corresponding width 2*W1′in the second direction Y. In some embodiments, at least one width W1′ of a conductive structure of the set of conductive structures320differs from at least one width W1′ of another conductive structure of the set of conductive structures320.

In some embodiments, the set of conductive structures320is also referred to as a set of power rails. In some embodiments, conductive structures320a,320cand320eare configured to supply the first supply voltage, and conductive structures320band320dare configured to supply the second supply voltage. In some embodiments, the first supply voltage is supply voltage VDD, and the second supply voltage is reference supply voltage VSS. In some embodiments, the first supply voltage is reference supply voltage VSS, and the second supply voltage is supply voltage VDD.

In some embodiments, if the set of active regions302,306and310correspond to n-type finFETs (e.g., the first device type), and the set of active regions304and308correspond to p-type finFETs (e.g., the second device type), then the first supply voltage is reference supply voltage VSS, the second supply voltage is supply voltage VDD, conductive structures320a,320cand320eprovide reference supply voltage VSS, and conductive structures patterns320band320dprovide supply voltage VDD.

In some embodiments, if the set of active regions302,306and310correspond to p-type finFETs (e.g., the second device type), and the set of active regions304and308correspond to n-type finFETs (e.g., the first device type), then the second supply voltage is reference supply voltage VSS, the first supply voltage is supply voltage VDD, conductive structures320a,320cand320eprovide supply voltage VDD, and conductive structures patterns320band320dprovide reference supply voltage VSS.

In some embodiments, the center of conductive structure320ais separated from the active region302bor302ain the second direction Y by at least a corresponding distance d7′ or d8′. In some embodiments, the center of conductive structure320bis separated from the active region304aor304bin the second direction Y by at least a corresponding distance d1′ or d2′. In some embodiments, the center of conductive structure320cis separated from the active region306aor306bin the second direction Y by at least a corresponding distance d3′ or d4′. In some embodiments, the center of conductive structure320dis separated from the active region308aor308bin the second direction Y by at least a corresponding distance d5′ or d6′. In some embodiments, the center of conductive structure320eis separated from the active region310aor310bin the second direction Y by at least a corresponding distance d7′ or d8′.

In some embodiments, by placing conductive structure320a,320b,320c,320dor320ebetween corresponding set of active regions302,304,306,308or310, a difference between corresponding distances d7′ and d8′, d1′ and d2′, d3′ and d4′, d5′ and d6′, & d7′ and d8′ is reduced, resulting in a more balanced IR drop across the corresponding n-type or p-type finFETs and corresponding conductive structures320a,320b,320c,320dor320ethereby yielding better performance than other approaches with unbalanced IR drops.

In some embodiments, the set of conductive structures330or332overlaps other underlying structures (not shown) of other levels (e.g., MD, or the like) of integrated circuit300.

In some embodiments, each conductive structure330a,330b,330c,330d,330e,330fof the set of conductive structures330or each conductive structure332a,332b,332c,332d,332e,332fof the set of conductive structures332has a width W3′ in the second direction Y.

In some embodiments, each conductive structure of the set of conductive structures330is separated from an adjacent conductive structure of the set of conductive structures330or an adjacent conductive structure of the set of conductive structures320in the second direction Y by a same pitch (not labelled) and are therefore evenly distributed. In some embodiments, each conductive structure of the set of conductive structures332is separated from an adjacent conductive structure of the set of conductive structures332or an adjacent conductive structure of the set of conductive structures320in the second direction Y by a same pitch (not labelled) and are therefore evenly distributed.

In some embodiments, conductive structures330a,330b,330c,330d,330eand330fof the set of conductive structures330or conductive structures332a,332b,332c,332d,332eand332fof the set of conductive structures332correspond to 6 M0 routing tracks in cell301. Other numbers of routing tracks in the set of conductive structures330or332are within the scope of the present disclosure.

The set of conductive structures320,330or332is on the second level. Other levels, quantities or configurations of the set of conductive structures320,330or332are within the scope of the present disclosure.

FIGS.4A-4Bare perspective views of finFETs410and420, in accordance with some embodiments.

In some embodiments, active region402corresponds to active regions with 2 fins, and active region412corresponds to active regions with 3 fins. For example, in some embodiments, active region402corresponds to at least active region306aor306binFIGS.3A-3B. For example, in some embodiments, active region412corresponds to at least active region302a,302b,304a,304b,308a,308b,310aor310binFIGS.3A-3B.

In some embodiments, active region402corresponds to at least active region606bor608ainFIGS.6A-6B. In some embodiments, active region412corresponds to at least active region302a,302b,604a,604b,606a,608b,310aor310binFIGS.6A-6B.

In some embodiments, active region402corresponds to at least active region804bor806ainFIGS.8A-8B. In some embodiments, active region412corresponds to at least active region302a,302b,804a,806b,308a,308b,310aor310binFIGS.8A-8B.

InFIG.4A, a finFET410is formed over two fin structures402a1and402a2in active region402. The gate of finFET410is formed by gate404over fin structures402a1and402a2. One of the source terminal or drain terminal of finFET410is formed by contact406over fin structures402a1and402a2. The other of the source terminal or drain terminal of finFET410is formed by contact408over fin structures402a1and402a2.

InFIG.4B, a finFET420is formed over three fin structures412a1,412a2and412a3in active region412. The gate of finFET420is formed by gate414over fin structures412a1,412a2and412a3. One of the source terminal or drain terminal of finFET420is formed by contact416over fin structures412a1,412a2and412a3. The other of the source terminal or drain terminal of finFET420is formed by contact418over fin structures412a1,412a2and412a3.

In some embodiments, the number of fin structures in finFET420is greater than the number of fin structures in finFET410. Other configurations or number of fin structures in active region402or412are within the scope of the present disclosure.

In some embodiments, the number of gates in finFET420is greater than the number of gates in finFET410. Other configurations or number of gates for at least gate404or424are within the scope of the present disclosure.

FIGS.5A-5Bare diagrams of a layout design, in accordance with some embodiments.

FIGS.5A-5Bare diagrams of a layout design500of an integrated circuit600ofFIGS.6A-6B, in accordance with some embodiments.

FIG.5Ais a diagram of a portion500A of layout design500ofFIGS.5A-5B, simplified for ease of illustration. For example, in comparison withFIG.5B, portion500A ofFIG.5Adoes not show a set of conductive feature layout patterns230and232ofFIG.5Bfor ease of illustration.

Layout design500is an embodiment of layout designs102aand104aofFIG.1or layout designs102band104bofFIG.1. Layout design500is usable to manufacture integrated circuit600.

Layout design500is a variation of layout design200(FIGS.2A-2B), and therefore similar detailed description is omitted. For example, layout design500illustrates an example where the location of the cells (e.g., cell layout designs501and503) are shifted by a distance D1in the second direction Y compared with the location of the cells (e.g., cell layout designs201and203) of layout design200. Stated differently, layout design500corresponds to layout design200shifted by distance D1in the second direction Y, but the locations of cell layout designs501and503are in similar positions as the location of cell layout designs201and203.

Layout design500includes cell layout designs501and503. In comparison with layout design200, cell layout designs501and503replace corresponding cell layout designs201and203, and similar detailed description is therefore omitted. Cell layout design501or503is usable to manufacture corresponding cell601or603(FIGS.6A-6B), in accordance with some embodiments. In comparison with cell layout designs201and203, cell layout design501is a mirror image of cell layout design503with respect to at least cell boundary101bor101d.

Layout design500further includes set of active region layout patterns202, a set of active region layout patterns504, a set of active region layout patterns506, a set of active region layout patterns508, set of active region layout patterns210, a set of conductive feature layout patterns520, set of conductive feature layout patterns230and set of conductive feature layout patterns232.

In comparison with layout design200ofFIGS.2A-2B, set of active region layout patterns504replaces set of active region layout patterns204, set of active region layout patterns506replaces set of active region layout patterns206, set of active region layout patterns508replaces set of active region layout patterns208, and set of conductive feature layout patterns520replaces set of conductive feature layout patterns220, and similar detailed description is therefore omitted.

The set of active region layout patterns504includes at least active region layout patterns504aor504b. Active region layout pattern504aor504breplaces corresponding active region layout pattern204aor204bofFIGS.2A-2B, and similar detailed description is therefore omitted. In comparison with active region layout pattern204aor204b, active region layout pattern504aor504bcorresponds to n-type finFET devices when active region layout patterns204aor204bcorrespond to p-type finFET devices, and therefore conductive feature layout pattern520bcorresponds to the reference supply voltage VSS instead of supply voltage VDD ofFIGS.2A-2B. Similarly, in comparison with active region layout pattern204aor204b, active region layout pattern504aor504bcorresponds to p-type finFET devices when active region layout pattern204aor204bcorresponds to n-type finFET devices respectively, and therefore conductive feature layout pattern520bcorresponds to the supply voltage VDD instead of reference supply voltage VSS ofFIGS.2A-2B.

The set of active region layout patterns506includes at least active region layout patterns506aor506b. Active region layout pattern506aor506breplaces corresponding active region layout pattern206aor206bofFIGS.2A-2B, and similar detailed description is therefore omitted. In comparison with active region layout pattern206aor206b, active region layout pattern506aor506bcorresponds to p-type finFET devices when active region layout patterns206aor206bcorrespond to n-type finFET devices, and therefore conductive feature layout pattern520bcorresponds to the supply voltage VDD instead of reference supply voltage VSS ofFIGS.2A-2B. Similarly, in comparison with active region layout pattern206aor206b, active region layout pattern506aor506bcorresponds to n-type finFET devices when active region layout patterns206aor206bcorrespond to p-type finFET devices, and therefore conductive feature layout pattern520bcorresponds to the reference supply voltage VSS instead of supply voltage VDD ofFIGS.2A-2B. In comparison with active region layout pattern206a, active region layout pattern506ais useable to manufacture an active region606ahaving 2 fins.

The set of active region layout patterns508includes at least active region layout patterns508aor508b. Active region layout pattern508aor508breplace corresponding active region layout pattern208aor208bofFIGS.2A-2B, and similar detailed description is therefore omitted. In comparison with active region layout pattern208a, active region layout pattern508ais useable to manufacture an active region608ahaving 2 fins.

In some embodiments, active region layout patterns504a,504b,506aand506bare part of cell layout design501. In some embodiments, active region layout patterns508a,508b,210aand210bare part of cell layout design503. In some embodiments, active region layout patterns202aand202bare part of a cell layout design different from cell layout design501or503.

In some embodiments, at least active region layout pattern504a,504b,506a,506b,508aor508bis usable to manufacture at least corresponding active region604a,604b,606a,606b,608aor608b(e.g., source and drain regions of n-type or p-type finFET transistors).

In some embodiments, set of active region layout patterns202,504and210correspond to active regions302,604and310of the first device type, and the set of active region layout patterns506and508correspond to the set of active regions606and608of the second device type, respectively.

In some embodiments, the first device type is an n-type finFET and the second device type is a p-type finFET. For example, in some embodiments, active region layout patterns202a,202b,504a,504b,210aand210bcorrespond to active regions302a,302b,604a,604b,310aand310bof n-type finFET transistors, and active region layout patterns506a,506b,508aand508bcorrespond to active regions606a,606b,608aand608bof p-type finFET transistors, respectively. In some embodiments, at least active region layout pattern202a,202b,504a,504b,210aor210bis usable to manufacture corresponding active region302a,302b,604a,604b,310aor310b(e.g., source and drain regions of n-type finFET transistors), and at least active region layout pattern506a,506b,508aor508bis usable to manufacture corresponding active region606a,606b,608aor608b(e.g., source and drain regions of p-type finFET transistors).

In some embodiments, the first device type is an n-type finFET and the second device type is a p-type finFET. In these embodiments, if the first device type is an n-type finFET and the second device type is a p-type finFET, then a number of n-type finFETs of the set of active regions604and310manufactured by the corresponding set of active region layout patterns504and210is greater than a number of p-type finFETs of the set of active regions606and608manufactured by the corresponding set of active region layout patterns506and508, and thus for at least cell layout design501or503(or cell601or603), the strength of the n-type finFETs is greater than the strength of the p-type finFETs.

In some embodiments, the first device type is a p-type finFET and the second device type is an n-type finFET. For example, in some embodiments, active region layout patterns202a,202b,504a,504b,210aand210bcorrespond to active regions302a,302b,604a,604b,310aand310bof p-type finFET transistors, and active region layout patterns506a,506b,508aand508bcorrespond to active regions606a,606b,608aand608bof n-type finFET transistors, respectively. In some embodiments, at least active region layout pattern202a,202b,504a,504b,210aor210bis usable to manufacture corresponding active region302a,302b,604a,604b,310aor310b(e.g., source and drain regions of p-type finFET transistors), and at least active region layout pattern506a,506b,508aor508bis usable to manufacture corresponding active region606a,606b,608aor608b(e.g., source and drain regions of n-type finFET transistors).

In some embodiments, the first device type is a p-type finFET and the second device type is an n-type finFET. In these embodiments, if the first device type is a p-type finFET and the second device type is an n-type finFET, then a number of p-type finFETs of the set of active regions604and310manufactured by the corresponding set of active region layout patterns504and210is greater than a number of n-type finFETs of the set of active regions606and608manufactured by the corresponding set of active region layout patterns506and508, and thus for at least cell layout design501or503(or cell601or603), the strength of the p-type finFETs is greater than the strength of the n-type finFETs.

In some embodiments, a different transistor type for at least the set of active region layout patterns202,504,506,508or210or the set of active regions302,604,606,608or310is within the scope of the present disclosure.

In comparison withFIGS.2A-2B, in some embodiments, at least active region layout pattern504a,504b,506aor508bis useable to manufacture corresponding active region604a,604b,606aor608bhaving m fins, and at least active region layout pattern506bor508ais useable to manufacture corresponding active region606bor608ahaving n fins, where m is an integer and n is another integer. For example, in some embodiments, integer m is equal to 3 and integer n is equal to 2 in layout design500or integrated circuit600, such that the set of active region layout patterns202,504and210are useable to manufacture corresponding set of active regions302,604and310having 6 fins each, active region layout patterns506aand508bare useable to manufacture corresponding active regions606aand608bhaving 3 fins, and active region layout patterns506band508aare useable to manufacture corresponding active regions606band608ahaving 2 fins. Other values for at least integer m or integer n are within the scope of the present disclosure.

In some embodiments, by using the features of layout design500, the widths W2aand W2bor number of fins (e.g., integer m or integer n) of the set of active region layout patterns202,504,506,508and210are selected or adjusted to better balance the n-type finFET and p-type finFET device strengths compared to other approaches resulting in better circuit performance than other approaches.

In some embodiments, at least the set of active region layout patterns504,506or508is located on the first level. Other configurations or quantities of patterns in at least set of active region layout patterns504,506or508are within the scope of the present disclosure.

The set of conductive feature layout patterns520includes at least conductive feature layout pattern220a,520b,520c,220dor220e. In comparison withFIGS.2A-2B, conductive feature layout pattern520bor520creplaces corresponding conductive feature layout pattern220bor220cofFIGS.2A-2B, and similar detailed description is therefore omitted.

In comparison with the set of conductive feature layout patterns220ofFIGS.2A-2B, in some embodiments, the set of conductive feature layout patterns520are shifted in the second direction Y by a distance D1.

In comparison with conductive feature layout pattern220b, conductive feature layout pattern520bcorresponds to reference supply voltage VSS instead of supply voltage VDD ofFIGS.2A-2B, when active region layout pattern504aor504bcorresponds to n-type finFET devices. Similarly, in comparison with conductive feature layout pattern220b, conductive feature layout pattern520bcorresponds to supply voltage VDD instead of reference supply voltage VSS ofFIGS.2A-2B, when active region layout pattern504aor504bcorresponds to p-type finFET devices.

In comparison with conductive feature layout pattern220c, conductive feature layout pattern520ccorresponds to supply voltage VDD instead of reference supply voltage VSS ofFIGS.2A-2B, when active region layout pattern506aor506bcorresponds to p-type finFET devices. Similarly, in comparison with conductive feature layout pattern220c, conductive feature layout pattern520ccorresponds to reference supply voltage VSS instead of supply voltage VDD ofFIGS.2A-2B, when active region layout pattern506aor506bcorresponds to n-type finFET devices.

In comparison with layout design200ofFIGS.2A-2B, the reference supply voltage VSS or supply voltage VDD inFIGS.5A-5Bare positioned in groups of 2 versus alternating in the second direction Y.

In some embodiments, the set of conductive feature layout patterns520is usable to manufacture the set of conductive structures620. In some embodiments, at least conductive feature layout pattern520bor520cis usable to manufacture at least corresponding conductive structure620bor620c.

In some embodiments, at least one conductive feature layout pattern of the set of conductive feature layout patterns520does not overlap cell boundary101a,101b,101c,101dor101e.

In some embodiments, by placing conductive feature layout pattern220a,520b,520c,220dor220ebetween corresponding set of active region layout pattern202,504,506,508or210, a difference between corresponding distances d7and d8, d1and d2, d3and d4, d5and d6, & d7and d8is reduced, resulting in a more balanced IR drop across the corresponding n-type or p-type finFETs and corresponding conductive structures320a,620b,620c,320dor320ethereby yielding better performance than other approaches with unbalanced IR drops.

The set of conductive feature layout patterns520is on the second level. Other levels, quantities or configurations of the set of conductive feature layout patterns520are within the scope of the present disclosure.

FIGS.6A-6Bare diagrams of a top view of an integrated circuit600, in accordance with some embodiments.

FIG.6Ais a diagram of a portion600A of integrated circuit600ofFIGS.6A-6B, simplified for ease of illustration. For example, in comparison withFIG.6B, portion600A ofFIG.6Adoes not show a set of conductive structures330and332ofFIG.6Bfor ease of illustration.

Integrated circuit600is manufactured by layout design500.

Integrated circuit600is a variation of integrated circuit300(FIGS.3A-3B), and therefore similar detailed description is omitted. For example, integrated circuit600illustrates an example where the location of the cells (e.g., cells601and603) are shifted by a distance D1′ in the second direction Y compared with the location of the cells (e.g., cells301and303) of integrated circuit300. Stated differently, integrated circuit600corresponds to integrated circuit300shifted by distance D1′ in the second direction Y, but the locations of cells601and603are in similar positions as the location of cells301and303.

Integrated circuit600includes cells601and603. In comparison with integrated circuit300, cells601and603replace corresponding cells301and303, and similar detailed description is therefore omitted. In comparison with cells301and303, cell601is a mirror image of cell603with respect to at least cell boundary101bor101d.

Integrated circuit600further includes set of active regions302, a set of active regions604, a set of active regions606, a set of active regions608, set of active regions310, a set of conductive structures620, set of conductive structures330and set of conductive structures332.

In comparison with integrated circuit300ofFIGS.3A-3B, set of active regions604replaces set of active regions304, set of active regions606replaces set of active regions306, set of active regions608replaces set of active regions308, and set of conductive structures620replaces set of conductive structures320, and similar detailed description is therefore omitted.

The set of active regions604includes at least active regions604aor604b. Active region604aor604breplaces corresponding active region304aor304bofFIGS.3A-3B, and similar detailed description is therefore omitted. In comparison with active region304aor304b, active region604aor604bcorresponds to n-type finFET devices when active region304aor304bcorresponds to n-type finFET devices, and therefore conductive structure620bcorresponds to the reference supply voltage VSS instead of supply voltage VDD ofFIGS.3A-3B. Similarly, in comparison with active region304aor304b, active region604aor604bcorresponds to p-type finFET devices when active region304aor304bcorresponds to n-type finFET devices respectively, and therefore conductive structure620bcorresponds to the supply voltage VDD instead of reference supply voltage VSS ofFIGS.3A-3B.

The set of active regions606includes at least active region606aor606b. Active region606aor606breplaces corresponding active region306aor306bofFIGS.3A-3B, and similar detailed description is therefore omitted. In comparison with active region306aor306b, active region606aor606bcorresponds to p-type finFET devices when active region306aor306bcorresponds to n-type finFET devices, and therefore conductive structure620bcorresponds to the supply voltage VDD instead of reference supply voltage VSS ofFIGS.3A-3B. Similarly, in comparison with active region306aor306b, active region606aor606bcorresponds to n-type finFET devices when active region306aor306bcorresponds to p-type finFET devices, and therefore conductive structure620bcorresponds to the reference supply voltage VSS instead of supply voltage VDD ofFIGS.3A-3B. In comparison with active region306a, active region606ahas 2 fins.

The set of active regions608includes at least active region608aor608b. Active region608aor608breplace corresponding active region308aor308bofFIGS.3A-3B, and similar detailed description is therefore omitted. In comparison with active region308a, active region608ahas 2 fins.

In some embodiments, active regions604a,604b,606aand606bare part of cell601. In some embodiments, active regions608a,608b,310aand310bare part of cell603. In some embodiments, active regions302aand302bare part of a cell different from cell601or603. In some embodiments, active regions310aand310bare part of another cell different from cell601or603.

In some embodiments, by using the features of integrated circuit600, the widths W2a′ and W2b′ or number of fins (e.g., integer m or integer n) of the set of active regions302,604,606,608and210are selected or adjusted to better balance the n-type finFET and p-type finFET device strengths compared to other approaches resulting in better circuit performance than other approaches.

In some embodiments, at least the set of active regions604,606or608is located on the first level. Other configurations or quantities of patterns in at least set of active regions604,606or608are within the scope of the present disclosure.

The set of conductive structures620includes at least conductive structure320a,620b,620c,320dor320e. In comparison withFIGS.3A-3B, conductive structure620bor620creplace corresponding conductive structure320bor320cofFIGS.3A-3B, and similar detailed description is therefore omitted.

In comparison with the set of conductive structures320ofFIGS.3A-3B, in some embodiments, the set of conductive structures620are shifted in the second direction Y by a distance D1′.

In comparison with conductive structure320b, conductive structure620bcorresponds to reference supply voltage VSS instead of supply voltage VDD ofFIGS.3A-3B, when active region604aor604bcorresponds to n-type finFET devices. Similarly, in comparison with conductive structure320b, conductive structure620bcorresponds to supply voltage VDD instead of reference supply voltage VSS ofFIGS.3A-3B, when active region604aor604bcorresponds to p-type finFET devices.

In comparison with conductive structure320c, conductive structure620ccorresponds to supply voltage VDD instead of reference supply voltage VSS ofFIGS.3A-3B, when active region606aor606bcorresponds to p-type finFET devices. Similarly, in comparison with conductive structure320c, conductive structure620ccorresponds to reference supply voltage VSS instead of supply voltage VDD ofFIGS.3A-3B, when active region606aor606bcorresponds to n-type finFET devices.

In comparison with integrated circuit300ofFIGS.3A-3B, the reference supply voltage VSS or supply voltage VDD inFIGS.6A-6Bare positioned in groups of 2 versus alternating in the second direction Y.

In some embodiments, at least one conductive structure of the set of conductive structures620does not overlap cell boundary101a,101b,101c,101dor101e.

In some embodiments, by placing conductive structure320a,620b,620c,320dor320ebetween corresponding set of active regions302,604,606,608or310, a difference between corresponding distances d7′ and d8′, d1′ and d2′, d3′ and d4′, d5′ and d6′, & d7′ and d8′ is reduced, resulting in a more balanced IR drop across the corresponding n-type or p-type finFETs and corresponding conductive structures320a,620b,620c,320dor320ethereby yielding better performance than other approaches with unbalanced IR drops.

The set of conductive structures620is on the second level. Other levels, quantities or configurations of the set of conductive structures620are within the scope of the present disclosure.

FIGS.7A-7Bare diagrams of a layout design, in accordance with some embodiments.

FIGS.7A-7Bare diagrams of a layout design700of an integrated circuit800ofFIGS.8A-8B, in accordance with some embodiments.

FIG.7Ais a diagram of a portion700A of layout design700ofFIGS.7A-7B, simplified for ease of illustration. For example, in comparison withFIG.5B, portion700A ofFIG.7Adoes not show a set of conductive feature layout patterns230and232ofFIG.5Bfor ease of illustration.

Layout design700is an embodiment of layout designs102aand104aofFIG.1or layout designs102band104bofFIG.1. Layout design700is usable to manufacture integrated circuit800.

Layout design700is a variation of layout design200(FIGS.2A-2B), and therefore similar detailed description is omitted. For example, layout design700illustrates an example where the location of the cells (e.g., cell layout designs701and703) are shifted by distance D1in the second direction Y compared with the location of the cells (e.g., cell layout designs201and203) of layout design200. Stated differently, layout design700corresponds to layout design200shifted by distance D1in the second direction Y, but the locations of cell layout designs701and703are in similar positions as the location of cell layout designs201and203.

Layout design700includes cell layout designs701and703. In comparison with layout design200, cell layout designs701and703replace corresponding cell layout designs201and203, and similar detailed description is therefore omitted. Cell layout design701or703is usable to manufacture corresponding cell801or803(FIGS.8A-8B), in accordance with some embodiments.

In comparison with cell layout design201, the set of active region layout patterns704and conductive feature layout pattern220bare mirror images of the set of active region layout patterns706and conductive feature layout pattern220cwith respect to cell segment770. In comparison with cell layout design203, the set of active region layout patterns208and conductive feature layout pattern220dare mirror images of the set of active region layout patterns210and conductive feature layout pattern220ewith respect to cell segment772.

Layout design700further includes set of active region layout patterns202, a set of active region layout patterns704, a set of active region layout patterns706, a set of active region layout patterns208, set of active region layout patterns210, a set of conductive feature layout patterns220, set of conductive feature layout patterns230and set of conductive feature layout patterns232.

In comparison with layout design200ofFIGS.2A-2B, set of active region layout patterns704replaces set of active region layout patterns204, and set of active region layout patterns706replaces set of active region layout patterns206, and similar detailed description is therefore omitted.

The set of active region layout patterns704includes at least active region layout pattern704aor704b. Active region layout pattern704aor704breplaces corresponding active region layout pattern204aor204bofFIGS.2A-2B, and similar detailed description is therefore omitted. In comparison with active region layout pattern204aor204b, active region layout pattern704aor704bcorresponds to n-type finFET devices when active region layout pattern204aor204bcorresponds to p-type finFET devices, and therefore conductive feature layout pattern220bcorresponds to the reference supply voltage VSS instead of supply voltage VDD ofFIGS.2A-2B. Similarly, in comparison with active region layout pattern204aor204b, active region layout pattern704aor704bcorresponds to p-type finFET devices when active region layout pattern204aor204bcorresponds to n-type finFET devices respectively, and therefore conductive feature layout pattern220bcorresponds to the supply voltage VDD instead of reference supply voltage VSS ofFIGS.2A-2B. In comparison with active region layout pattern204b, active region layout pattern704bis useable to manufacture an active region804bhaving 2 fins.

The set of active region layout patterns706includes at least active region layout pattern706aor706b. Active region layout pattern706aor706breplaces corresponding active region layout pattern206aor206bofFIGS.2A-2B, and similar detailed description is therefore omitted. In comparison with active region layout pattern206aor206b, active region layout pattern706aor706bcorresponds to p-type finFET devices when active region layout pattern206aor206bcorresponds to n-type finFET devices, and therefore conductive feature layout pattern220bcorresponds to the supply voltage VDD instead of reference supply voltage VSS ofFIGS.2A-2B. Similarly, in comparison with active region layout pattern206aor206b, active region layout pattern706aor706bcorresponds to n-type finFET devices when active region layout pattern206aor206bcorresponds to p-type finFET devices, and therefore conductive feature layout pattern220bcorresponds to the reference supply voltage VSS instead of supply voltage VDD ofFIGS.2A-2B. In comparison with active region layout pattern206a, active region layout pattern706ais useable to manufacture an active region806ahaving 2 fins.

In some embodiments, active region layout patterns704a,704b,706aand706bare part of cell layout design701. In some embodiments, active region layout patterns208a,208b,210aand210bare part of cell layout design703. In some embodiments, active region layout patterns202aand202bare part of a cell layout design different from cell layout design701or703.

In some embodiments, at least active region layout pattern704a,704b,706aor706bis usable to manufacture at least corresponding active region604a,604b,606aor606b(e.g., source and drain regions of n-type or p-type finFET transistors).

In comparison with layout design200ofFIGS.2A-2B, the type of fins or finFETs of active regions302,308and310manufactured by corresponding set of active region layout patterns202,208and210inFIGS.7A-7B, are swapped with the type of fins or finFET of active regions302,308and310manufactured by corresponding set of active region layout patterns202,208and210inFIGS.2A-2B, and similar detailed description is therefore omitted. For example, in some embodiments, set of active region layout patterns202,706and210correspond to active regions302,806and310of the first device type, and the set of active region layout patterns704and208correspond to the set of active regions804and308of the second device type, respectively.

In some embodiments, the first device type is a p-type finFET and the second device type is an n-type finFET. For example, in some embodiments, active region layout pattern202a,202b,706a,706b,210aor210bcorresponds to active region302a,302b,806a,806b,310aor310bof p-type finFET transistors, and active region layout pattern704a,704b,208aor208bcorresponds to active region804a,804b,308aor308bof n-type finFET transistors, respectively.

In some embodiments, at least active region layout pattern202a,202b,706a,706b,210aor210bis usable to manufacture corresponding active region302a,302b,806a,806b,310aor310b(e.g., source and drain regions of p-type finFET transistors), and at least active region layout pattern704a,704b,208aor208bis usable to manufacture corresponding active region804a,804b,308aor308b(e.g., source and drain regions of n-type finFET transistors).

In some embodiments, the first device type is a p-type finFET and the second device type is an n-type finFET. In these embodiments, if the first device type is a p-type finFET and the second device type is an n-type finFET, then a number of p-type finFETs of the set of active regions806and310manufactured by the corresponding set of active region layout patterns706and210is equal to a number of n-type finFETs of the set of active regions804and308manufactured by the corresponding set of active region layout patterns704and208, and thus for at least cell layout design701or703(or cell801or803), the strength of the p-type finFETs is equal to the strength of the n-type finFETs.

In some embodiments, the first device type is an n-type finFET and the second device type is a p-type finFET. For example, in some embodiments, active region layout patterns202a,202b,706a,706b,210aand210bcorrespond to active regions302a,302b,806a,806b,310aand310bof n-type finFET transistors, and active region layout patterns704a,704b,208aand208bcorrespond to active regions804a,804b,308aand308bof p-type finFET transistors, respectively.

In some embodiments, at least active region layout pattern202a,202b,706a,706b,210aor210bis usable to manufacture corresponding active region302a,302b,806a,806b,310aor310b(e.g., source and drain regions of n-type finFET transistors), and at least active region layout pattern704a,704b,208aor208bis usable to manufacture corresponding active region804a,804b,308aor308b(e.g., source and drain regions of p-type finFET transistors).

In some embodiments, the first device type is an n-type finFET and the second device type is a p-type finFET. In these embodiments, if the first device type is an n-type finFET and the second device type is a p-type finFET, then a number of n-type finFETs of the set of active regions806and310manufactured by the corresponding set of active region layout patterns706and210is equal to a number of p-type finFETs of the set of active regions804and308manufactured by the corresponding set of active region layout patterns704and208, and thus for at least cell layout design701or703(or cell801or803), the strength of the n-type finFETs is equal to the strength of the p-type finFETs.

In some embodiments, a different transistor type for at least the set of active region layout patterns202,704,706,208or210or the set of active regions302,804,806,308or310is within the scope of the present disclosure.

In comparison withFIGS.2A-2B, in some embodiments, at least active region layout patterns704a,706b,208aor208bis useable to manufacture corresponding active region804a,806b,308aor308bhaving m fins, and at least active region layout pattern704bor706ais useable to manufacture corresponding active region804bor806ahaving n fins, where m is an integer and n is another integer. For example, in some embodiments, integer m is equal to 3 and integer n is equal to 2 in layout design700or integrated circuit800, such that the set of active region layout patterns202,208and210are useable to manufacture corresponding set of active regions302,308and310having 6 fins each, active region layout patterns704aand706bare useable to manufacture corresponding active regions804aand806bhaving 3 fins, and active region layout patterns704band706aare useable to manufacture corresponding active regions804band806ahaving 2 fins. Other values for at least integer m or integer n are within the scope of the present disclosure.

In some embodiments, by using the features of layout design700, the widths W2aand W2bor number of fins (e.g., integer m or integer n) of the set of active region layout patterns202,704,706,208and210are selected or adjusted to better balance the n-type finFET and p-type finFET device strengths compared to other approaches resulting in better circuit performance than other approaches.

In some embodiments, at least the set of active region layout patterns704or706is located on the first level. Other configurations or quantities of patterns in at least set of active region layout patterns704or706are within the scope of the present disclosure.

The set of conductive feature layout patterns220includes at least conductive feature layout pattern220a,220b,220c,220dor220e. In comparison withFIGS.2A-2B, the set of conductive feature layout patterns220ofFIGS.7A-7Bare similar to the set of conductive feature layout patterns220ofFIGS.2A-2B, and therefore similar detailed description is omitted.

In comparison with the set of conductive feature layout patterns220ofFIGS.2A-2B, in some embodiments, the set of conductive feature layout patterns220ofFIGS.7A-7Bare shifted in the second direction Y by distance D1.

In comparison with layout design200ofFIGS.2A-2B, the voltage supply (e.g., voltage supply VDD or reference voltage supply VSS) of at least conductive structure320a,320b,320c,320dor320einFIGS.8A-8Bmanufactured by corresponding conductive feature layout pattern220a,220b,220c,220dor220einFIGS.7A-7B, are swapped with the voltage supply (e.g., reference voltage supply VSS or voltage supply VDD) of at least conductive structure320a,320b,320c,320dor320einFIGS.3A-3Bmanufactured by corresponding conductive feature layout pattern220a,220b,220c,220dor220einFIGS.2A-2B, and similar detailed description is therefore omitted.

In some embodiments, at least one conductive feature layout pattern of the set of conductive feature layout patterns220ofFIGS.7A-7Bdoes not overlap cell boundary101a,101b,101c,101dor101e.

In some embodiments, by placing conductive feature layout pattern220a,220b,220c,220dor220ebetween corresponding set of active region layout patterns202,704,706,208or210, a difference between corresponding distances d7and d8, d1and d2, d3and d4, d5and d6, & d7and d8is reduced, resulting in a more balanced IR drop across the corresponding n-type or p-type finFETs and corresponding conductive structure320a,320b,320c,320dor320ethereby yielding better performance than other approaches with unbalanced IR drops.

The set of conductive feature layout patterns220inFIGS.7A-7Bis on the second level. Other levels, quantities or configurations of the set of conductive feature layout patterns220inFIGS.7A-7Bare within the scope of the present disclosure.

FIGS.8A-8Bare diagrams of a top view of an integrated circuit800, in accordance with some embodiments.

FIG.8Ais a diagram of a portion800A of integrated circuit800ofFIGS.8A-8B, simplified for ease of illustration. For example, in comparison withFIG.8B, portion800A ofFIG.8Adoes not show a set of conductive structures330and332ofFIG.8Bfor ease of illustration.

Integrated circuit800is manufactured by integrated circuit800.

Integrated circuit800is a variation of integrated circuit300(FIGS.3A-3B), and therefore similar detailed description is omitted. For example, integrated circuit800illustrates an example where the location of the cells (e.g., cells801and803) are shifted by a distance D1′ in the second direction Y compared with the location of the cells (e.g., cells301and303) of integrated circuit300. Stated differently, integrated circuit800corresponds to integrated circuit300shifted by distance D1′ in the second direction Y, but the locations of cells801and803are in similar positions as the location of cells301and303.

Integrated circuit800includes cells801and803. In comparison with integrated circuit300, cells801and803replace corresponding cells301and303, and similar detailed description is therefore omitted.

In comparison with cell301, the set of active regions804and conductive structures320bare mirror images of the set of active regions806and conductive structure320cwith respect to cell segment870. In comparison with cell303, the set of active regions308and conductive structure320dare mirror images of the set of active regions310and conductive structure320ewith respect to cell segment872.

Integrated circuit800further includes set of active regions302, a set of active regions804, a set of active regions806, set of active regions308, set of active regions310, set of conductive structures320, set of conductive structures330and set of conductive structures332.

In comparison with integrated circuit300ofFIGS.3A-3B, set of active regions804replaces set of active regions304, and set of active regions806replaces set of active regions306, and similar detailed description is therefore omitted.

The set of active regions804includes at least active region804aor804b. Active region804aor804breplaces corresponding active region304aor304bofFIGS.3A-3B, and similar detailed description is therefore omitted. In comparison with active region304aor304b, active region804aor804bcorresponds to n-type finFET devices when active region304aor304bcorresponds to p-type finFET devices, and therefore conductive structure320bcorresponds to the reference supply voltage VSS instead of supply voltage VDD ofFIGS.3A-3B. Similarly, in comparison with active region304aor304b, active region804aor804bcorresponds to p-type finFET devices when active region304aor304bcorresponds to n-type finFET devices respectively, and therefore conductive structure320bcorresponds to the supply voltage VDD instead of reference supply voltage VSS ofFIGS.3A-3B. In comparison with active region304b, active region804bhas 2 fins.

The set of active regions806includes at least active region806aor806b. Active region806aor806breplaces corresponding active region306aor306bofFIGS.3A-3B, and similar detailed description is therefore omitted. In comparison with active region306aor306b, active region806aor806bcorresponds to p-type finFET devices when active region306aor306bcorresponds to n-type finFET devices, and therefore conductive structure320bcorresponds to the supply voltage VDD instead of reference supply voltage VSS ofFIGS.3A-3B. Similarly, in comparison with active region306aor306b, active region806aor806bcorresponds to n-type finFET devices when active region306aor306bcorresponds to p-type finFET devices, and therefore conductive structure320bcorresponds to the reference supply voltage VSS instead of supply voltage VDD ofFIGS.3A-3B. In comparison with active region306a, active region806ahas 2 fins. In comparison with active region306b, active region806bhas 3 fins.

In some embodiments, active regions804a,804b,806aand806bare part of cell801. In some embodiments, active regions308a,308b,310aand310bare part of cell803. In some embodiments, active regions302aand302bare part of a cell different from cell801or803.

In some embodiments, by using the features of integrated circuit800, the widths W2a′ and W2b′ or number of fins (e.g., integer m or integer n) of the set of active regions302,804,806,308and310are selected or adjusted to better balance the n-type finFET and p-type finFET device strengths compared to other approaches resulting in better circuit performance than other approaches. For example, in some embodiments, within cell801or803, the sum of the number of fins in the n-type finFETs is equal to the number of fins in the p-type finFETs, thereby causing the strength of the n-type finFETs to be equal to the strength of the p-type finFETs and thus being balanced resulting in better circuit performance than other approaches.

In some embodiments, at least the set of active regions804or806is located on the first level. Other configurations or quantities of patterns in at least set of active regions804or806are within the scope of the present disclosure.

The set of conductive structures320includes at least conductive structure320a,320b,320c,320dor320e. In comparison withFIGS.3A-3B, the set of conductive structures320ofFIGS.7A-7Bare similar to the set of conductive structures320ofFIGS.3A-3B, and therefore similar detailed description is omitted.

In comparison with the set of conductive structures320ofFIGS.3A-3B, in some embodiments, the set of conductive structures320ofFIGS.7A-7Bare shifted in the second direction Y by distance D1′.

In comparison with integrated circuit300ofFIGS.3A-3B, the voltage supply (e.g., voltage supply VDD or reference voltage supply VSS) of at least conductive structure320a,320b,320c,320dor320einFIGS.8A-8Bare swapped with the voltage supply (e.g., reference voltage supply VSS or voltage supply VDD) of at least conductive structure320a,320b,320c,320dor320einFIGS.3A-3B, and similar detailed description is therefore omitted.

In some embodiments, at least one conductive structure of the set of conductive structures320ofFIGS.8A-8Bdoes not overlap cell boundary101a,101b,101c,101dor101e.

In some embodiments, by placing conductive structure320a,320b,320c,320dor320ebetween corresponding set of active regions302,804,806,308or310, a difference between corresponding distances d7′ and d8′, d1′ and d2′, d3′ and d4′, d5′ and d6′, & d7′ and d8′ is reduced, resulting in a more balanced IR drop across the corresponding n-type or p-type finFETs and corresponding conductive structure320a,320b,320c,320dor320ethereby yielding better performance than other approaches with unbalanced IR drops.

The set of conductive structures320inFIGS.8A-8Bis on the second level. Other levels, quantities or configurations of the set of conductive structures320inFIGS.8A-8Bare within the scope of the present disclosure.

In some embodiments, at least one structure of the set of conductive structures320,330,332,620or at least contact406,408,416or418includes one or more layers of metal materials, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

FIGS.9A-9Care schematic views of layout designs900A-900C of integrated circuits, in accordance with some embodiments. In some embodiments, layout designs900A-900C are corresponding layout designs after execution of one or more operations of method1102ofFIG.11.

FIG.9Ais a schematic view of a layout design900A of sets of active region layout patterns902,904,906,908and910. In some embodiments, layout design900A is a layout design after execution of operation1102of method1100(FIG.11). For example, in some embodiments, layout design900A illustrates the design guideline of operation1102of method1100when the strength of the p-type fin FET devices is greater than the strength of the n-type finFET devices.

In some embodiments, layout design900A is a variation of layout design200ofFIGS.2A-2B. For example, in some embodiments, layout design900A is similar to layout design200when the first device type is an n-type finFET and the second device type is a p-type finFET, and a number of n-type finFETs manufactured by the set of active region layout patterns202,206and210is less than a number of p-type finFETs manufactured by the set of active region layout patterns204and208, and similar detailed description is therefore omitted.

Layout design900A includes cell layout designs901and903. In comparison with layout design200, cell layout designs901and903replace corresponding cell layout designs201and203, and similar detailed description is therefore omitted. In some embodiments, cell layout design901or903is usable to manufacture corresponding cells301,601and801or303,603and803, in accordance with some embodiments.

Cell boundary901ais similar to corresponding cell boundary101aor101c, cell boundary901bis similar to corresponding cell boundary101bor101d, cell boundary901cis similar to corresponding cell boundary101cor101e, and similar detailed description is therefore omitted.

Layout design900A further includes sets of active region layout patterns902,904,906,908and910.

The set of active region layout patterns902includes at least active region layout patterns902aor902b. Active region layout pattern902aor902bare similar to corresponding active region layout pattern202bor202afor when the first device type is an n-type finFET, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern902aor902bis useable to manufacture a corresponding active region having n fins, where n is an integer.

The set of active region layout patterns906includes at least active region layout patterns906aor906b. Active region layout pattern906aor906bare similar to corresponding active region layout pattern206aor206bfor when the first device type is an n-type finFET, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern906aor906bis useable to manufacture a corresponding active region having n fins, where n is an integer.

The set of active region layout patterns910includes at least active region layout patterns910aor910b. Active region layout pattern910aor910bare similar to corresponding active region layout pattern210aor210bfor when the first device type is an n-type finFET, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern910aor910bis useable to manufacture a corresponding active region having n fins, where n is an integer.

The set of active region layout patterns904includes at least active region layout patterns904a,904b, . . . ,904jwhere j is an integer corresponding to a number of devices having m fins in the set of active region layout patterns904. The set of active region layout patterns904is similar to at least the set of active region layout pattern204or208, and similar detailed description is therefore omitted. In some embodiments, each of active region layout pattern904a,904b,904jis useable to manufacture a corresponding active region having m fins, where m is an integer.

The set of active region layout patterns908includes at least active region layout patterns908a,908b, . . . ,908kwhere k is an integer corresponding to a number of devices having m fins in the set of active region layout patterns908. The set of active region layout patterns908is similar to at least the set of active region layout pattern204or208, and similar detailed description is therefore omitted. In some embodiments, each of active region layout pattern908a,908b, . . . ,908kis useable to manufacture a corresponding active region having m fins, where m is an integer. In some embodiments, integer j is equal to integer k. In some embodiments, integer j is different from integer k.

In some embodiments, at least active region layout pattern904a,904b, . . . ,904gor904jor at least active region layout pattern908a,908b, . . . ,908kcan include n-type finFETs (e.g., the first device type) or p-type finFETs (e.g., the second device type) provided that the strength of the p-type fin FET devices in layout design900A is greater than the strength of the n-type finFET devices.

In some embodiments, the set of active region layout patterns902,906and910are placed at corresponding cell boundaries901a,901band901cin accordance with the design guidelines of operation1102of method100to offset the stronger device strength of the p-type devices. By using the features of layout design900A-900C, the positions of at least the set of active region layout patterns902,906,910,912,916,920,922,926or930are selected or adjusted to better balance the n-type finFET and p-type finFET device strengths compared to other approaches resulting in better circuit performance than other approaches.

FIG.9Bis a schematic view of a layout design900B of sets of active region layout patterns912,904,916,908and920. In some embodiments, layout design900B is a layout design after execution of operation1102of method1100(FIG.11). For example, in some embodiments, layout design900B illustrates the design guideline of operation1102of method1100when the strength of the n-type fin FET devices is greater than the strength of the p-type finFET devices.

In some embodiments, layout design900B is a variation of layout design200ofFIGS.2A-2Bor layout design900A ofFIG.9A. For example, in some embodiments, layout design900B is similar to layout design200when the first device type is a p-type finFET and the second device type is an n-type finFET, and a number of p-type finFETs manufactured by the set of active region layout patterns202,206and210is less than a number of n-type finFETs manufactured by the set of active region layout patterns204and208, and similar detailed description is therefore omitted.

In comparison with layout design900B, set of active region layout patterns902,906,910of layout design900A is replaced with corresponding set of active region layout patterns912,916,920, and similar detailed description is therefore omitted. In some embodiments, set of active region layout patterns912,916,920are similar to corresponding set of active region layout patterns902,906,910, but the set of active region layout patterns912,916,920correspond to when the first device type is p-type finFETs.

The set of active region layout patterns912includes at least active region layout patterns912aor912b. Active region layout pattern912aor912bis similar to corresponding active region layout pattern202bor202afor when the first device type is a p-type finFET, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern912aor912bis useable to manufacture a corresponding active region having n fins, where n is an integer.

The set of active region layout patterns916includes at least active region layout patterns916aor916b. Active region layout pattern916aor916bis similar to corresponding active region layout pattern206aor206bfor when the first device type is a p-type finFET, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern916aor916bis useable to manufacture a corresponding active region having n fins, where n is an integer.

The set of active region layout patterns920includes at least active region layout patterns920aor920b. Active region layout pattern920aor920bis similar to corresponding active region layout pattern210aor210bfor when the first device type is a p-type finFET, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern920aor920bis useable to manufacture a corresponding active region having n fins, where n is an integer.

In some embodiments, at least active region layout pattern904a,904b, . . . ,904gor904jor at least active region layout pattern908a,908b, . . . ,908kcan include n-type finFETs (e.g., the first device type) or p-type finFETs (e.g., the second device type) provided that the strength of the n-type fin FET devices in layout design900B is greater than the strength of the p-type finFET devices.

In some embodiments, the set of active region layout patterns912,916and920are placed at corresponding cell boundaries901a,901band901cin accordance with the design guidelines of operation1102of method100to offset the stronger device strength of the n-type devices.

FIG.9Cis a schematic view of a layout design900C of sets of active region layout patterns922,904,926,908and930. In some embodiments, layout design900C is a layout design after execution of operation1102of method1100(FIG.11). For example, in some embodiments, layout design900C illustrates the design guideline of operation1102of method1100when the strength of the n-type fin FET devices is equal to the strength of the p-type finFET devices.

In some embodiments, layout design900C is a variation of layout design200ofFIGS.2A-2B, layout design900A ofFIG.9Aor layout design900B ofFIG.9B.

For example, in some embodiments, layout design900C is similar to layout design200when the active region layout patterns202b,206aand210aare n-type finFETs, and active region layout patterns202a,206band210bare p-type finFETs, and the number of p-type finFETs manufactured by the set of active region layout patterns202,204,206,208and210is equal to the number of n-type finFETs manufactured by the set of active region layout patterns202,204,206,208and210, and similar detailed description is therefore omitted.

Layout design900C incorporates aspects of each of layout designs900A and900B. In comparison with layout designs900A-900B, set of active region layout patterns922,926,930replaces corresponding set of active region layout patterns902,906,910of layout design900A or corresponding set of active region layout patterns912,916,920of layout design900B, and similar detailed description is therefore omitted.

The set of active region layout patterns922includes at least active region layout patterns922aor922b. Active region layout pattern922ais similar to active region layout pattern912a, and corresponds to a p-type finFET with n fins, and similar detailed description is therefore omitted. Active region layout pattern922bis similar to active region layout pattern902b, and corresponds to an n-type finFET with n fins, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern922aor922bis useable to manufacture a corresponding active region having n fins, where n is an integer.

The set of active region layout patterns926includes at least active region layout patterns926aor926b. Active region layout pattern926ais similar to active region layout pattern906a, and corresponds to an n-type finFET with n fins, and similar detailed description is therefore omitted. Active region layout pattern926bis similar to active region layout pattern916b, and corresponds to a p-type finFET with n fins, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern926aor926bis useable to manufacture a corresponding active region having n fins, where n is an integer.

The set of active region layout patterns930includes at least active region layout patterns930aor930b. Active region layout pattern930ais similar to active region layout pattern910a, and corresponds to an n-type finFET with n fins, and similar detailed description is therefore omitted. Active region layout pattern930bis similar to active region layout pattern920b, and corresponds to a p-type finFET with n fins, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern930aor930bis useable to manufacture a corresponding active region having n fins, where n is an integer.

In some embodiments, at least active region layout pattern904a,904b, . . . ,904gor904jor at least active region layout pattern908a,908b, . . . ,908kcan include n-type finFETs (e.g., the first device type) or p-type finFETs (e.g., the second device type) provided that the strength of the n-type fin FET devices in layout design900C is equal to the strength of the p-type finFET devices.

In some embodiments, the set of active region layout patterns922,926and930are placed at corresponding cell boundaries901a,901band901cin accordance with the design guidelines of operation1102of method100to balance the device strength of the n-type devices and the p-type devices.

FIGS.10A-10Eare schematic views of layout designs1000A-1000E of integrated circuits, in accordance with some embodiments. In some embodiments, layout designs1000A-1000E are corresponding layout designs after execution of one or more operations of method1100ofFIG.11.

FIG.10Ais a schematic view of a layout design1000A of a set of active region layout patterns1002and conductive feature layout pattern1020.

The set of active region layout patterns1002includes at least active region layout patterns1002aor1002b. Active region layout pattern1002aor1002bare similar to corresponding active region layout pattern206aor206b, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern1002aor1002bis useable to manufacture an active region having n fins, where n is an integer.

Conductive feature layout pattern1020is similar to conductive feature layout pattern220c, and similar detailed description is therefore omitted. Distances d10and d11are similar to corresponding distance d3and d4, and similar detailed description is therefore omitted.

Conductive feature layout pattern1020is between active region layout pattern1002aand active region layout pattern1002b.

In some embodiments, layout design1000A is a layout design after execution of operation1106of method1100(FIG.11). For example, in some embodiments, layout design1000A illustrates the placement of conductive feature layout pattern1020between active region layout patterns with n fins (e.g., active region layout patterns1002aand1002b) in satisfying a design guideline of operation1106. For example, in some embodiments, layout design1000A illustrates the placement of conductive feature layout pattern1020between the set of active region layout patterns1002in satisfying a design guideline of operation1106.

FIG.10Bis a schematic view of a layout design1000B of a set of active regions1004and conductive feature layout pattern1022.

The set of active region layout patterns1004includes at least active region layout patterns1004aor1004b. Active region layout pattern1004aor1004bare similar to corresponding active region layout pattern508aor508bor corresponding active region layout pattern706aor706b, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern1004ais useable to manufacture an active region having n fins, and active region layout pattern1004bis useable to manufacture an active region having m fins, where n and m are integers.

Conductive feature layout pattern1022is similar to conductive feature layout pattern220dinFIGS.5A-5Bor conductive feature layout pattern220cinFIGS.7A-7B, and similar detailed description is therefore omitted. Distances d10and d11are similar to corresponding distance d5and d6inFIGS.5A-5Bor distances d3and d4inFIGS.7A-7B, and similar detailed description is therefore omitted.

Conductive feature layout pattern1022is between active region layout pattern1004aand active region layout pattern1004b.

In some embodiments, layout design1000B is a layout design after execution of operation1106of method1100(FIG.11). For example, in some embodiments, layout design1000B illustrates the placement of conductive feature layout pattern1022between active region layout patterns with n fins (e.g., active region layout pattern1004a) and active region layout patterns with m fins (e.g., active region layout pattern1004b) in satisfying a design guideline of operation1106. For example, in some embodiments, layout design1000B illustrates the placement of conductive feature layout pattern1022between the set of active region layout patterns1004in satisfying a design guideline of operation1106.

FIG.10Cis a schematic view of a layout design1000C of a set of active regions1006and conductive feature layout pattern1024.

The set of active region layout patterns1006includes at least active region layout patterns1006aor1006b. Active region layout pattern1006aor1006bare similar to corresponding active region layout pattern506aor506bor corresponding active region layout pattern704aor704b, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern1006ais useable to manufacture an active region having m fins, and active region layout pattern1006bis useable to manufacture an active region having n fins, where n and m are integers.

Conductive feature layout pattern1024is similar to conductive feature layout pattern520cinFIGS.5A-5Bor conductive feature layout pattern220binFIGS.7A-7B, and similar detailed description is therefore omitted. Distances d10and d11are similar to corresponding distance d3and d4inFIGS.5A-5Bor distances d1and d2inFIGS.7A-7B, and similar detailed description is therefore omitted.

Conductive feature layout pattern1024is between active region layout pattern1006aand active region layout pattern1006b.

In some embodiments, layout design1000C is a layout design after execution of operation1106of method1100(FIG.11). For example, in some embodiments, layout design1000C illustrates the placement of conductive feature layout pattern1024between active region layout patterns with m fins (e.g., active region layout pattern1006a) and active region layout patterns with n fins (e.g., active region layout pattern1006b) in satisfying a design guideline of operation1106. For example, in some embodiments, layout design1000C illustrates the placement of conductive feature layout pattern1024between the set of active region layout patterns1006in satisfying a design guideline of operation1106.

FIG.10Dis a schematic view of a layout design1000D of a set of active regions1008and conductive feature layout pattern1026.

The set of active region layout patterns1008includes at least active region layout patterns1008aor1008b. Active region layout pattern1008aor1008bare similar to corresponding active region layout pattern204aor204b, and similar detailed description is therefore omitted. In some embodiments, active region layout pattern1008aor1008bis useable to manufacture an active region having m fins, where m is an integer. In some embodiments, the set of active region layout patterns1008is similar to other set of active region layout patterns in the present disclosure having m fins, and similar detailed description is therefore omitted.

Conductive feature layout pattern1026is similar to conductive feature layout pattern220b, and similar detailed description is therefore omitted. Distances d10and d11are similar to corresponding distance d1and d2, and similar detailed description is therefore omitted.

Conductive feature layout pattern1026is between active region layout pattern1008aand active region layout pattern1008b.

In some embodiments, layout design1000D is a layout design after execution of operation1106of method1100(FIG.11). For example, in some embodiments, layout design1000D illustrates the placement of conductive feature layout pattern1026between active region layout patterns with m fins (e.g., active region layout patterns1008aand1008b) in satisfying a design guideline of operation1106. For example, in some embodiments, layout design1000D illustrates the placement of conductive feature layout pattern1026between the set of active region layout patterns1008in satisfying a design guideline of operation1106.

In some embodiments, by placing conductive feature layout pattern1020,1022,1024or1026between the corresponding set of active region layout patterns1002,1004,1006or1008, a difference between distance d10and d11is reduced, thereby causing a distance travelled by corresponding current I1, I2, I3or I4to the corresponding set of active region layout patterns1002,1004,1006or1008to be reduced, resulting in a more balanced IR profile of the corresponding set of active region layout patterns1002,1004,1006or1008and the corresponding conductive feature layout pattern1020,1022,1024or1026, thereby yielding better performance than other approaches with unbalanced IR profiles or drops.

FIG.10Eis a schematic view of a layout design1000E after execution of operation1108of method1100(FIG.11).

Layout design1000E includes set of gridlines1048,1050,1052and1054, a set of active regions1010, a set of conductive feature layout patterns1028, and sets of conductive feature layout patterns1040,1042and1044.

The set of active region layout patterns1010includes at least active region layout patterns1010a,1010b,1010cor1010d. Active region layout pattern1010a,1010b,1010cor1010dare similar to corresponding active region layout patterns204a,204b,206aor206b, and similar detailed description is therefore omitted. In some embodiments, each of active region layout patterns1010a,1010b,1010cor1010dis useable to manufacture an active region having n or m fins, where n and m are different integers.

The set of conductive feature layout patterns1028includes at least conductive feature region layout patterns1028aor1028b. Conductive feature layout pattern1028aor1028bis similar to corresponding conductive feature layout pattern220bor220c, and similar detailed description is therefore omitted. Each conductive feature layout pattern of the set of conductive feature layout patterns1028has a corresponding width W3in the second direction Y. In some embodiments, width W3is different from width W1. In some embodiments, width W3is equal to 2*W1.

The set of conductive feature layout patterns1040includes at least conductive feature region layout patterns1040aor1040b. Conductive feature layout pattern1040aor1040bis similar to corresponding conductive feature layout pattern230bor230c, and similar detailed description is therefore omitted.

The set of conductive feature layout patterns1042includes at least conductive feature region layout patterns1042a,1042b,1042c,1042d,1042eor1042f. Conductive feature layout pattern1042a,1042b,1042c,1042d,1042eor1042fis similar to corresponding conductive feature layout pattern230d,230e,230f,232a,232bor232c, and similar detailed description is therefore omitted.

The set of conductive feature layout patterns1044includes at least conductive feature region layout patterns1044aor1044b. Conductive feature layout pattern1044aor1044bis similar to corresponding conductive feature layout pattern232dor232e, and similar detailed description is therefore omitted.

Each of the set of gridlines1048,1050,1052and1054extends in the first direction X.

The set of gridlines1048includes at least gridline1048aor1048b. Gridlines1048aand1048bare separated from each other in the second direction Y by a pitch (not labelled). In some embodiments, each gridline1048aor1048bdefines a region where corresponding conductive feature layout pattern1028aor1028bis positioned.

The set of gridlines1050includes at least gridline1050aor1050b. Gridlines1050aand1050bare separated from each other in the second direction Y by a pitch P1. In some embodiments, each gridline1050aor1050bdefines a region where corresponding conductive feature layout pattern1040aor1040bis positioned.

The set of gridlines1052includes at least gridline1052a,1052b,1052c,1052d,1052eor1052fEach gridline1052a,1052b,1052c,1052d,1052eor1052fis separated from an adjacent gridline1052a,1052b,1052c,1052d,1052eor1052fin the second direction Y by pitch P1. In some embodiments, each gridline1052a,1052b,1052c,1052d,1052eor1052fdefines a region where corresponding conductive feature layout pattern1042a,1042b,1042c,1042d,1042eor1042fis positioned.

The set of gridlines1054includes at least gridline1054aor1054b. Gridlines1054aand1054bare separated from each other in the second direction Y by pitch P1. In some embodiments, each gridline1054aor1054bdefines a region where corresponding conductive feature layout pattern1044aor1044bis positioned.

In some embodiments, gridline1048ais separated from each of gridlines1050band1052ain the second direction Y by a distance D3. In some embodiments, gridline1048bis separated from each of gridlines1052fand1054ain the second direction Y by distance D3. In some embodiments, each of the set of gridlines1048,1050,1052or1054is also referred to as a corresponding set of routing M0 tracks. In some embodiments, pitch P1is equal to distance D3. In some embodiments, pitch P1is different from distance D3.

In some embodiments, layout design1000E is a layout design after execution of operation1108of method1100(FIG.11). For example, in some embodiments, layout design1000E illustrates the placement of the set of conductive feature layout patterns1040,1042and1044in satisfying a design guideline of operation1108. For example, in some embodiments, layout design1000E illustrates that the placement of each conductive feature layout pattern of the set of conductive feature layout patterns1042is evenly distributed between the set of conductive feature layout patterns1028in satisfying a design guideline of operation1108. Similarly, for example, in some embodiments, layout design1000E illustrates that the placement of the set of conductive feature layout patterns1040or1044is evenly distributed between a conductive feature layout pattern of the set of conductive feature layout patterns1028and a conductive feature layout pattern of another set of conductive feature layout patterns (not shown) in satisfying a design guideline of operation1108.

FIG.11is a functional flow chart of at least a portion of an integrated circuit design and manufacturing flow1100, in accordance with some embodiments.

It is understood that additional operations may be performed before, during, and/or after the method1100depicted inFIG.11, and that some other processes may only be briefly described herein. In some embodiments, the method1100is usable to at least generate or place one or more layout patterns of layout design100(FIG.1),200(FIGS.2A-2B),500(FIGS.5A-5B),700(FIGS.7A-7B),900A-900C (FIGS.9A-9C),1000A-1000E (FIGS.10A-10E), or1200B (FIG.12B) of an integrated circuit, such as integrated circuit300(FIGS.3A-3B),600(FIGS.6A-6B),800(FIGS.8A-8B) or1200A (FIG.12A). In some embodiments, the method1100is usable to manufacture an integrated circuit, such as integrated circuit300(FIGS.3A-3B), integrated circuit600(FIGS.6A-6B), integrated circuit800(FIGS.8A-8B) or integrated circuit1200(FIG.12A).

In operation1102of method1100, a set of active region layout patterns is generated or placed on a first level of a layout design. In some embodiments, the layout design of method1100includes at least layout design100,102a,102b,104a,104b,200,500,700,900A-900C,1000A-1000E or1200B. In some embodiments, the first level of method1100corresponds to the OD level. In some embodiments, the first level of method1100corresponds to the first level described in the specification.

In some embodiments, the set of active region layout patterns of method1100includes at least one or more layout patterns of at least the set of active region layout patterns202,204,206,208,210,504,506,508,704,706,902,904,906,908,910,912,916,920,922,926,930,1002,1004,1006,1008or1010.

In some embodiments, the set of active region layout patterns of method1100correspond to fabricating a set of active regions of the integrated circuit. In some embodiments, the set of active regions of method1100includes at least one or more regions of the set of active regions302,304,306,308,310,402,412,604,606,608,804or806.

In some embodiments, operation1102includes generating or placing the set of active region layout patterns according to a first set of guidelines or design rules.

The first set of design guidelines of operation1102is described with respect toFIGS.9A-9C, but is applicable to each of the layout designs of the present disclosure.

In some embodiments, the first set of design guidelines of method1100includes placing the set of active region layout patterns of the first device type and the second device type thereby reducing the device strength mismatch between the n-type finFETs and the p-type finFETs.

In some embodiments, the first set of design guidelines of operation1102includes placing the set of active region layout patterns of the first device type at cell boundaries901a,901band901cto offset the stronger device strength of the second device type. For example, in some embodiments, if the first device type is n-type finFETs and the second device type is p-type finFETs, and the device strength of the n-type finFETs in the layout design is less than the device strength of the p-type finFETs, then the design guideline of operation1102includes placing the set of active region layout patterns902,906and908of the n-type finFETs at corresponding cell boundaries901a,901band901c.

For example, in some embodiments, if the first device type is p-type finFETs and the second device type is n-type finFETs, and the device strength of the p-type finFETs in the layout design is less than the device strength of the n-type finFETs, then the design guideline of operation1102includes placing the set of active region layout patterns912,916and918of the p-type finFETs at corresponding cell boundaries901a,901band901c.

In some embodiments, the first set of design guidelines of operation1102includes placing the set of active region layout patterns of the first device type and the second device type at cell boundaries901a,901band901cto balance the device strength of the first device type and the second device type. For example, in some embodiments, if the first device type is n-type finFETs and the second device type is p-type finFETs, and the device strength of the n-type finFETs in the layout design is equal to the device strength of the p-type finFETs, then the design guideline of operation1102includes placing n-type finFETs of active region layout patterns922b,926aand930a, and placing p-type finFETs of active region layout patterns922a,92baand930bat corresponding cell boundaries901a,901band901c.

In some embodiments, if a number of active region layout patterns in the set of active region layout patterns904and908of the first device type is greater than a number of active region layout patterns in the set of active region layout patterns902,906and910of the second device type, then the first set of design guidelines of operation1102includes placing each of the set of active region layout patterns902,904and906at corresponding cell boundary901a,901bor901c.

In some embodiments, if a number of fins in active region layout patterns in the set of active region layout patterns904and908of the first device type is greater than a number of fins in active region layout patterns in the set of active region layout patterns902,906and910of the second device type, then each of the set of active region layout patterns902,906and910are placed at corresponding cell boundary901a,901bor901c.

In operation1104of method1100, a set of gridlines is generated or placed on the layout design. In some embodiments, the set of gridlines of method1100includes at least one or more gridlines of at least the set of gridlines1048,1050,1052or1054. In some embodiments, the inclusion of one or more elements from the gridlines set of gridlines of method1100corresponds to including further sets and/or sub-sets of the set of gridlines.

In operation1106of method1100, a first set of conductive feature layout patterns is generated or placed on the layout design on a second level of the layout design. In some embodiments, the second level is different from the first level. In some embodiments, the second level of method1100corresponds to the M0 level. In some embodiments, the second level of method1100corresponds to the second level described in the specification.

In some embodiments, the first set of conductive feature layout patterns of method1100includes at least one or more layout patterns of at least the set of conductive feature layout patterns220,520,1020,1022,1024,1026or1028. In some embodiments, the inclusion of one or more elements from the first set of conductive feature layout patterns of method1100corresponds to including further sets and/or sub-sets of the first set of conductive feature layout patterns.

In some embodiments, the first set of conductive feature layout patterns of method1100corresponds to fabricating a first set of conductive structures of the integrated circuit. In some embodiments, the first set of conductive structures of method1100includes at least one or more conductive structures of the set of conductive structures320or620. In some embodiments, the first set of conductive feature layout patterns of method1100is also referred to as a set of power rail layout patterns.

In some embodiments, operation1106includes generating or placing the first set of conductive feature layout patterns according to a second set of guidelines or design rules.

The second set of design guidelines of operation1106is described with respect toFIGS.10A-10D, but is applicable to each of the layout designs of the present disclosure.

In some embodiments, the second set of design guidelines of method1100includes placing conductive feature layout patterns1020,1022,1024or1026between the set of active region layout patterns1002,1004,1006or1008reducing the difference between distance d10and d11, thereby causing a distance travelled by corresponding current I1, I2, I3or I4to the corresponding set of active region layout patterns1002,1004,1006or1008to be reduced, which results in a more balanced IR profile of the corresponding set of active region layout patterns1002,1004,1006or1008and the corresponding conductive feature layout pattern1020,1022,1024or1026, thereby yielding better performance than other approaches with unbalanced IR profiles or drops.

In operation1108of method1100, a second set of conductive feature layout patterns is generated or placed on layout design on the second level.

In some embodiments, the second set of conductive feature layout patterns of method1100includes at least one or more layout patterns of at least the set of conductive feature layout patterns230,232,1040,1042or1044. In some embodiments, the inclusion of one or more elements from the second set of conductive feature layout patterns of method1100corresponds to including further sets and/or sub-sets of the second set of conductive feature layout patterns.

In some embodiments, the second set of conductive feature layout patterns of method1100corresponds to fabricating a second set of conductive structures of the integrated circuit. In some embodiments, the second set of conductive structures of method1100includes at least one or more conductive structures of the set of conductive structures330or332. In some embodiments, the second set of conductive feature layout patterns of method1100is also referred to as a set of pin layout patterns.

In some embodiments, operation1108includes generating or placing the second set of conductive feature layout patterns according to a third set of guidelines or design rules.

The third set of design guidelines of operation1108is described with respect toFIG.10E, but is applicable to each of the layout designs of the present disclosure. In some embodiments, the third set of design guidelines of method1100includes uniformly placing the set of conductive feature layout patterns1042between the set of conductive feature layout patterns1028. In some embodiments, the third set of design guidelines of method1100includes uniformly placing the set of conductive feature layout patterns1040or1044between a conductive feature layout pattern of the set of conductive feature layout patterns1028and a conductive feature layout pattern of another set of conductive feature layout patterns (not shown).

In operation1110of method1100, the integrated circuit is fabricated according to the layout design. In some embodiments, the integrated circuit of method1100is fabricated by system1300or IC manufacturing system1400. In some embodiments, operation1110of method1100comprises manufacturing at least one mask based on the layout design, and manufacturing the integrated circuit based on the at least one mask.

In some embodiments, one or more of the operations of method1100is performed to generate or place a first layout pattern on the layout design of method1100, and then one or more of the operations of method1100is repeated to generate or place additional layout patterns on the design of method1100. In some embodiments, one or more of the operations of method1100is performed to generate or place a first layout design on the layout design of method1100, and then one or more of the operations of method1100is repeated to generate or place additional layout designs on the design of method1100.

In some embodiments, at least one or more operations of method1100is performed by an EDA tool, such as system1300ofFIG.13. In some embodiments, at least one method(s), such as method1100discussed above, is performed in whole or in part by at least one EDA system, including system1300. In some embodiments, an EDA system is usable as part of a design house of an IC manufacturing system1400ofFIG.14.

In some embodiments, one or more of the operations of method1100(e.g.,1102-1110) is not performed. One or more of the operations of method1100is performed by a processing device configured to execute instructions for manufacturing the integrated circuit of method1100. In some embodiments, one or more operations of method1100is performed using a same processing device as that used in a different one or more operations of method1100. In some embodiments, a different processing device is used to perform one or more operations of method1100from that used to perform a different one or more operations of method1100.

FIG.12Ais a circuit diagram of an integrated circuit1200, in accordance with some embodiments. In some embodiments, integrated circuit1200is a NOR gate circuit. A NOR gate circuit is used for illustration, other types of circuits including other configurations for NOR gate circuits are within the scope of the present disclosure.

Each of a gate terminal of PMOS transistor MP1and a gate terminal of NMOS transistor MN1are configured as an input node (not labelled) and are coupled together. Each of a gate terminal of PMOS transistor MP2and a gate terminal of NMOS transistor MN2are configured as another input node (not labelled) and are coupled together.

A source terminal of PMOS transistor MP1is coupled to the voltage supply VDD. A drain terminal of PMOS transistor MP1is coupled to a source terminal of PMOS transistor MP2. Each of a drain terminal of PMOS transistor MP2, a drain terminal of NMOS transistor MN1and a drain terminal of NMOS transistor MN2are coupled together. A source terminal of NMOS transistor MN1and a source terminal of NMOS transistor MN2are each coupled to a reference voltage supply VSS.

Other circuits, other types of transistors, and/or quantities of transistors are within the scope of various embodiments.

FIG.12Bis a circuit diagram of an integrated circuit1200, in accordance with some embodiments.

Layout design1200B is a layout diagram of integrated circuit1200A. Layout design1200B is usable to manufacture integrated circuit1200A.

Layout design1200B is an embodiment of layout designs102aand104aofFIG.1or layout designs102band104bofFIG.1. In some embodiments, layout design1200B is an embodiment of at least layout design200,500,700,900A-900C or1000A-1000E.

Layout design1200B includes active region layout patterns202a,202b,204aand204bfromFIGS.2A-2B, and conductive feature layout patterns220a,220b,220c,220dfromFIGS.2A-2B.

A first row of active region layout patterns202aand202bcorrespond to NMOS transistor MN1, a second row of active region layout patterns202aand202bcorrespond to NMOS transistor MN2, the first row of active region layout patterns204aand204bcorrespond to PMOS transistor MP1, and the second row of active region layout patterns204aand204bcorrespond to PMOS transistor MP2.

InFIG.12B, NMOS transistors MN1and MN2and PMOS transistors MP1and MP2are grouped together as element A1. Similarly, other NMOS transistors and PMOS transistors similar to element A1are grouped together and labelled as elements A2-A8, and similar detailed description is therefore omitted.

FIG.13is a schematic view of a system1300for designing an IC layout design and manufacturing an IC circuit in accordance with some embodiments. In some embodiments, system1300generates or places one or more IC layout designs described herein. System1300includes a hardware processor1302and a non-transitory, computer readable storage medium1304(e.g., memory1304) encoded with, i.e., storing, the computer program code1306, i.e., a set of executable instructions1306. Computer readable storage medium1304is configured for interfacing with manufacturing machines for producing the integrated circuit. The processor1302is electrically coupled to the computer readable storage medium1304via a bus1308. The processor1302is also electrically coupled to an I/O interface1310by bus1308. A network interface1312is also electrically connected to the processor1302via bus1308. Network interface1312is connected to a network1314, so that processor1302and computer readable storage medium1304are capable of connecting to external elements via network1314. The processor1302is configured to execute the computer program code1306encoded in the computer readable storage medium1304in order to cause system1300to be usable for performing a portion or all of the operations as described in method1100.

In some embodiments, the processor1302is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In some embodiments, the storage medium1304stores the computer program code1306configured to cause system1300to perform method1100. In some embodiments, the storage medium1304also stores information needed for performing method1100as well as information generated during performing method1100, such as layout design1316, user interface1318and fabrication unit1320, and/or a set of executable instructions to perform the operation of method1100. In some embodiments, layout design1316comprises one or more of layout patterns of layout design100,200,500,700,900A-900C,1000A-1000E or1200B.

In some embodiments, the storage medium1304stores instructions (e.g., computer program code1306) for interfacing with manufacturing machines. The instructions (e.g., computer program code1306) enable processor1302to generate manufacturing instructions readable by the manufacturing machines to effectively implement method1100during a manufacturing process.

System1300also includes network interface1312coupled to the processor1302. Network interface1312allows system1300to communicate with network1314, to which one or more other computer systems are connected. Network interface1312includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interface such as ETHERNET, USB, or IEEE-1394. In some embodiments, method1100is implemented in two or more systems1300, and information such as layout design, and user interface are exchanged between different systems1300by network1314.

System1300is configured to receive information related to a layout design through I/O interface1310or network interface1312. The information is transferred to processor1302by bus1308to determine a layout design for producing integrated circuit300,400A-400B,600,800or1200A. The layout design is then stored in computer readable medium1304as layout design1316. System1300is configured to receive information related to a user interface through I/O interface1310or network interface1312. The information is stored in computer readable medium1304as user interface1318. System1300is configured to receive information related to a fabrication unit through I/O interface1310or network interface1312. The information is stored in computer readable medium1304as fabrication unit1320. In some embodiments, the fabrication unit1320includes fabrication information utilized by system1300. In some embodiments, the fabrication unit1320corresponds to mask fabrication1434ofFIG.14.

In some embodiments, method1100is implemented as a standalone software application for execution by a processor. In some embodiments, method1100is implemented as a software application that is a part of an additional software application. In some embodiments, method1100is implemented as a plug-in to a software application. In some embodiments, method1100is implemented as a software application that is a portion of an EDA tool. In some embodiments, method1100is implemented as a software application that is used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of the integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer readable medium. In some embodiments, the layout is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. In some embodiments, the layout is generated based on a netlist which is created based on the schematic design. In some embodiments, method1100is implemented by a manufacturing device to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs generated by system1300. In some embodiments, system1300a manufacturing device to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs of the present disclosure. In some embodiments, system1300ofFIG.13generates layout designs of an integrated circuit that are smaller than other approaches. In some embodiments, system1300ofFIG.13generates layout designs of integrated circuit structure that occupy less area and provide better routing resources than other approaches.

InFIG.14, IC manufacturing system1400(hereinafter “system1400”) includes entities, such as a design house1420, a mask house1430, and an IC manufacturer/fabricator (“fab”)1440, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device1460. The entities in system1400are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, one or more of design house1420, mask house1430, and IC fab1440is owned by a single larger company. In some embodiments, one or more of design house1420, mask house1430, and IC fab1440coexist in a common facility and use common resources.

Design house (or design team)1420generates an IC design layout1422. IC design layout1422includes various geometrical patterns designed for an IC device1460. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device1460to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout1422includes various IC features, such as an active region, gate electrode, source electrode and drain electrode, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house1420implements a proper design procedure to form IC design layout1422. The design procedure includes one or more of logic design, physical design or place and route. IC design layout1422is presented in one or more data files having information of the geometrical patterns. For example, IC design layout1422can be expressed in a GDSII file format or DFII file format.

Mask house1430includes data preparation1432and mask fabrication1434. Mask house1430uses IC design layout1422to manufacture one or more masks1445to be used for fabricating the various layers of IC device1460according to IC design layout1422. Mask house1430performs mask data preparation1432, where IC design layout1422is translated into a representative data file (“RDF”). Mask data preparation1432provides the RDF to mask fabrication1434. Mask fabrication1434includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)1445or a semiconductor wafer1442. The design layout1422is manipulated by mask data preparation1432to comply with particular characteristics of the mask writer and/or requirements of IC fab1440. InFIG.14, mask data preparation1432and mask fabrication1434are illustrated as separate elements. In some embodiments, mask data preparation1432and mask fabrication1434can be collectively referred to as mask data preparation.

In some embodiments, mask data preparation1432includes a mask rule checker (MRC) that checks the IC design layout that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to compensate for limitations during mask fabrication1434, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

It should be understood that the above description of mask data preparation1432has been simplified for the purposes of clarity. In some embodiments, data preparation1432includes additional features such as a logic operation (LOP) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to IC design layout1422during data preparation1432may be executed in a variety of different orders.

After mask data preparation1432and during mask fabrication1434, a mask1445or a group of masks1445are fabricated based on the modified IC design layout1422. In some embodiments, mask fabrication1434includes performing one or more lithographic exposures based on IC design1422. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)1445based on the modified IC design layout1422. The mask1445can be formed in various technologies. In some embodiments, the mask1445is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary version of mask1445includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask1445is formed using a phase shift technology. In the phase shift mask (PSM) version of mask1445, various features in the pattern formed on the mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication1434is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in the semiconductor wafer, in an etching process to form various etching regions in the semiconductor wafer, and/or in other suitable processes.

IC fab1440includes wafer fabrication tools1452(hereinafter “fabrication tools1452”) configured to execute various manufacturing operations on semiconductor wafer1442such that IC device1460is fabricated in accordance with the mask(s), e.g., mask1445. In various embodiments, fabrication tools1452include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

System1400is shown as having design house1420, mask house1430or IC fab1440as separate components or entities. However, it is understood that one or more of design house1420, mask house1430or IC fab1440are part of the same component or entity.

One aspect of this description relates to a method of forming an integrated circuit. In some embodiments, the method includes placing, by a processor, a first cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on the layout design. In some embodiments, the first cell layout design has a first cell boundary and a second cell boundary extending in a first direction. In some embodiments, the second cell boundary is separated from the first cell boundary in a second direction different from the first direction. In some embodiments, placing the first cell layout design includes placing a first active region layout pattern according to a first set of guidelines adjacent to the first cell boundary. In some embodiments, the first active region layout pattern corresponds to transistors of a first type, extending in the first direction, and being in a first layout level, and having a first width in the first direction. In some embodiments, placing the first cell layout design further includes placing a second active region layout pattern according to the first set of guidelines adjacent to the second cell boundary. In some embodiments, the second active region layout pattern corresponds to transistors of the first type, extending in the first direction, being in the first layout level, and being separated from the first active region layout pattern in the second direction and having a second width different from the first width. In some embodiments, placing the first cell layout design further includes placing a first set of active region layout patterns according to the first set of guidelines between the first active region layout pattern and the second active region layout pattern. In some embodiments, the first set of active region layout patterns extends in the first direction and is in the first layout level. In some embodiments, for at least the first cell layout design, the first set of guidelines includes selecting transistors of a first type with a first driving strength and transistors of a second type with a second driving strength different from the first driving strength, the second type being different from the first type.

Another aspect of this description relates to a method of forming an integrated circuit. In some embodiments, the method includes generating, by a processor, a first cell layout design of the integrated circuit and manufacturing the integrated circuit based on at least the first cell layout design. In some embodiments, the first cell layout design has a first cell boundary and a second cell boundary extending in a first direction. In some embodiments, the second cell boundary is separated from the first cell boundary in a second direction different from the first direction. In some embodiments, generating the first cell layout design includes generating a first active region layout pattern corresponding to a first set of transistors of a first type, generating a second active region layout pattern corresponding to a second set of transistors of the first type, generating a third active region layout pattern corresponding to a third set of transistors of a second type different from the first type, generating a fourth active region layout pattern corresponding to a fourth set of transistors of the second type. In some embodiments, the first active region layout pattern extends in the first direction, is in a first layout level, and is adjacent to the first cell boundary. In some embodiments, the second active region layout pattern extends in the first direction, is in the first layout level, is adjacent to the first active region layout pattern, and is separated from the first active region layout pattern in the second direction. In some embodiments, the third active region layout pattern extends in the first direction, is in the first layout level, and is adjacent to the second active region layout pattern. In some embodiments, the fourth active region layout pattern extends in the first direction, is in the first layout level, is adjacent to the second cell boundary, and is separated from the third active region layout pattern in the second direction. In some embodiments, at least the first, second, third or fourth active region layout pattern satisfies a first set of guidelines. In some embodiments, the first set of guidelines including balancing a first driving strength of the first set of transistors and the second set of transistors with a second driving strength of the third set of transistors and the fourth set of transistors. In some embodiments, the second driving strength is equal to the first driving strength. In some embodiments, the first set of transistors include a first number of fins, the second set of transistors include a second number of fins, the third set of transistors include a third number of fins, and the fourth set of transistors include a fourth number of fins. In some embodiments, a sum of the third number of fins and the fourth number of fins is equal to a sum of the first number of fins and the second number of fins.

Yet another aspect of this description relates to an integrated circuit. In some embodiments, the integrated circuit includes a first active region of the first set of transistors of a first type, the second active region of the second set of transistors of the first type, the third active region of a third set of transistors of the first type, a fourth active region of a fourth set of transistors of the first type, a fifth active region of a fifth set of transistors of a second type, and a sixth active region of a sixth set of transistors of the second type. In some embodiments, the second type is different from the first type. In some embodiments, the first active region extends in a first direction, is in a first level, is adjacent to a first boundary and has a first width in a second direction different from the first direction. In some embodiments, the second active region extends in the first direction, is in the first level, is adjacent to the first boundary, and is separated from the first active region in the second direction, and has and has the first width in the second direction. In some embodiments, the third active region extends in the first direction, is in the first level, and is adjacent to a second boundary, and has a second width different from the first width in the second direction. In some embodiments, the fourth active region extends in the first direction, is in the first level, is adjacent to the second boundary, and is separated from the third active region in the second direction, and has the second width. In some embodiments, the fifth active region extends in the first direction, is in the first level, is between the second active region and the third active region, and has the first width. In some embodiments, the sixth active region extends in the first direction, is in the first level, and is between the second active region and the third active region. In some embodiments, a sum of a first driving strength of the first set of transistors, the second set of transistors, the third set of transistors and the fourth set of transistors is less than a sum of a second driving strength of the fifth set of transistors and the sixth set of transistors, the second driving strength is different from the first driving strength.

A number of embodiments have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, various transistors being shown as a particular dopant type (e.g., N-type or P-type Metal Oxide Semiconductor (NMOS or PMOS)) are for illustration purposes. Embodiments of the disclosure are not limited to a particular type. Selecting different dopant types for a particular transistor is within the scope of various embodiments. The low or high logical value of various signals used in the above description is also for illustration. Various embodiments are not limited to a particular logical value when a signal is activated and/or deactivated. Selecting different logical values is within the scope of various embodiments. In various embodiments, a transistor functions as a switch. A switching circuit used in place of a transistor is within the scope of various embodiments. In various embodiments, a source of a transistor can be configured as a drain, and a drain can be configured as a source. As such, the term source and drain are used interchangeably. Various signals are generated by corresponding circuits, but, for simplicity, the circuits are not shown.

Various figures show capacitive circuits using discrete capacitors for illustration. Equivalent circuitry may be used. For example, a capacitive device, circuitry or network (e.g., a combination of capacitors, capacitive elements, devices, circuitry, or the like) can be used in place of the discrete capacitor. The above illustrations include exemplary operations or steps, but the steps are not necessarily performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments.