DRAM with self-resetting data path for reduced power consumption

A random access memory (RAM), such as a dynamic RAM (DRAM) or embedded DRAM (eDRAM) on a CMOS integrated circuit (IC) logic chip. Memory banks drive one line of a connected global data line pair to develop a difference signal on the pair. Simultaneously, a global signal monitor line discharges to develop a signal that mirrors the signal developing on one of the pair. When the global signal monitor line discharges sufficiently to indicate that the difference signal is large enough to sense, a global sense control sets a global data sense amplifier, the memory banks drive shuts off, and the global sense control initiates restoring global data line.

FIELD OF THE INVENTION

The present invention is related to reducing memory power consumption and more particularly to reducing power consumption in dynamic random access memory (DRAM) macros on integrated circuit (IC) chips.

BACKGROUND DESCRIPTION

Semiconductor technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). Generally, all other factors being constant, the active power consumed by a given unit increases linearly with switching frequency. Thus, not withstanding the decrease of chip supply voltage, chip power consumption has increased as well. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power. For low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, reducing net power consumption is important but, such a power reduction must come without degrading chip/circuit performance below acceptable levels.

To minimize semiconductor circuit power consumption, most integrated circuits (ICs) are made in the well-known complementary insulated gate Field Effect Transistor (FET) technology known as CMOS. A typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (ideally modeled as a resistor (R) in series with the closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa. Thus, ideally, there is no static or DC current path in a typical CMOS circuit.

A CMOS inverter, for example, is a PFET and NFET pair that are series connected between a power supply voltage (Vdd) and ground (GND). Both are gated by the same input and both drive the same output, typically a capacitive load. The PFET pulls the output high and the NFET pulls the output low at opposite input signal states. Ideally, when the gate of a NFET is below some positive threshold voltage (VT) with respect to its source, the NFET is off, i.e., the switch is open. Above VT, the NFET is on conducting current, i.e., the switch is closed. Similarly, a PFET is off when its gate is above its VT, i.e., less negative, and on below VT. So, ideal CMOS circuits use no static or DC power and primarily consume transient power from charging and discharging capacitive loads.

Random access memories (RAMs) are well known in the art. A typical RAM has a memory array of rows (word lines) and columns (bit lines) of cell locations wherein every location is addressable and freely accessible by providing the correct corresponding address. Dynamic RAMs (DRAMs) are dense RAMs with a very small memory cell. DRAM arrays, increasingly, are being embedded in logic and included on CMOS logic chips, e.g. in on-chip, processor or microprocessor cache memory. Essentially, a DRAM cell is a capacitor for storing charge and a switch, a pass transistor (also called a pass gate or access transistor) that switches on and off to transfer charge to and from the capacitor. Data (1 bit) stored in the cell is determined by the absence or presence of charge on the storage capacitor. Since each cell has numerous leakage paths from the storage capacitor, unless it is periodically refreshed, charge stored on the storage capacitor eventually leaks off.

Each DRAM cell is read by coupling the cell's storage capacitor (through the access transistor) to a bit line, which is a larger capacitance. A signal develops on the bit line that reflects the contents of the cell. Typically, the signal is a bit line voltage difference (determined by ratio of the cell and bit line capacitances) when the cell storage capacitor voltage does not match the bit line; and no difference when the voltages match. A sense amplifier measures the resulting bit line voltage difference, and develops a fully complementary signal from the bit line signal. For a typical segmented data path, the sense amplifier drives that fully complementary signal on a global data line that may also be a complementary pair of lines, each of which is a much larger capacitance than the bit line capacitance, normally, driving one of the pair low/high with the other of the pair remaining high/low. The global data line, in turn, may be an input to a driver, a latch, etc. that passes the data contents external to the DRAM, e.g., to chip logic for an eDRAM. Writing to a cell is, essentially, the reverse, i.e., driving one of the global bit line pair low/high, coupling the driven global line to the bit line and the bit line to the cell. Consequently, charging and discharging data path capacitance in each access (read/write) can consume an appreciable amount of power, to significantly increase chip power consumption.

Thus, there is a need for reducing power in high performance DRAMs, and more particularly, for reducing power in high performance DRAMs suitable for embedded use in logic chips.

SUMMARY OF THE INVENTION

It is a purpose of the invention to improve memory power consumption; It is another purpose of the invention to reduce DRAM power; It is another purpose of the invention to reduce embedded DRAM power consumption without impacting eDRAM performance.

The present invention relates to a random access memory (RAM), such as a dynamic RAM (DRAM) or embedded DRAM (eDRAM) on a CMOS integrated circuit (IC) logic chip. Memory banks drive one line of a connected global data line pair to develop a difference signal on the pair. Simultaneously, a global signal monitor line discharges to develop a signal that mirrors the signal developing on one of the pair. When the global signal monitor line discharges sufficiently to indicate that the difference signal is large enough to sense, a global sense control sets a global data sense amplifier, the memory banks drive shuts off, and the global sense control initiates restoring global data line.

DESCRIPTION OF PREFERRED EMBODIMENT

Turning now to the drawings and, more particularly,FIG. 1shows a block diagram cross-sectional example of a single bit of a preferred embodiment self-resetting memory100for reduced power consumption, e.g., a dynamic random access memory (DRAM) macro or embedded DRAM (eDRAM). Preferably, the eDRAM100is formed in the insulated gate Field Effect Transistor (FET) technology known as CMOS. The preferred eDRAM100is organized into n identical banks102-0,102-1,102-2, . . . ,102-(n−1), connected to a pair of complementary global data lines,104T,104C. A global signal monitor line108develops a signal that substantially mirrors a signal on a global data line104T or104C. Signals on the global data line pair104T,104C and the global signal monitor line108are passed to a global data sense110for sensing and passing data106externally, e.g., to on-chip logic (not shown). A discharge monitor driver112pulses the global signal monitor line108during a read to develop a signal representative of a signal coincidentally developing on a global data line104T,104C. When the signal on the global signal monitor line108is sufficient for sensing, the global data sense and control110sets and latches, and the global data lines104T,104C begin a restore. Glue logic114provides local logic and control (e.g., bit and address decode and local clocks) for the embedded DRAM100. It should be noted that although shown herein as having a global signal monitor line108with a global data line pair104T,104C, this is for example only and not intended as a limitation. A single global signal monitor line108may be included with a group of global data line pairs104T,104C, e.g., a single global signal monitor line108for an entire eDRAM (m pairs with an m-bit word).

In this example, each bank102-0,102-1,102-2, . . . ,102-(n−1) includes a word select116to select a row of cells (not shown) in a sub-array118of cells in one selected bank102-0,102-1,102-2, . . . ,102-(n−1). A bit select120selects an array column, typically a bit line connected to cells and a reference or dummy line, and couples the selected column to a complementary pair of local data lines122T,122C. The local data lines122T,122C carry the selected data signal and the reference line signal from the selected column as a difference signal to a local sense amplifier124. So for each bank102-0,102-1,102-2, . . . ,102-(n−1), in this example, cells of a sub-array118are selected by coincidence of a row (i.e., a word line) selected by word select116and a column selected by the bit select120. The local sense amplifier124for the selected bank102-0,102-1,102-2, . . . ,102-(n−1) senses the signal on the complementary pair of local data lines122T,122C, and provides a pair of complementary outputs126T,126C. Complementary sense amplifier outputs126T,126C each pass through an edge shaper128T,128C that may simply be an AND gate driving an inverting driver, for example. A read select signal130selectively passes complementary outputs126T,126C through the edge shapers128T,128C, to emerge as a pair of complementary intermediate signals132T,132C. Global data drivers134T,134C re-drive the pair of complementary intermediate signals132T,132C onto a corresponding one of the global data line pair104T,104C, to develop a difference signal on the global data line pair104T,104C.

The global signal monitor line108may have substantially the same capacitance as each of the global data line pair104T,104C with the discharge monitor driver112driving the global signal monitor line108substantially the same as the edge shapers128T,128C and as selected by the read select signal130. Optionally, the capacitance on the global signal monitor line108may be a fraction of that one the global data line pair104T,104C with an equivalent ratioed drive reduction in the discharge monitor driver112. Regardless, however, as the signal develops on one of the global data lines104T,104C, a substantially matching signal develops on the global signal monitor line108to mirror the developing signal. Thus, it may be determined when a sufficient difference voltage has developed on the global data line pair104T,104C by monitoring the global signal monitor line108. Upon such determination, the global data sense110may complete the read access by sensing and latching the contents of the difference signal on the global data line pair104T,104C and, automatically terminating discharge. So, in a preferred embodiment RAM, instead of fully discharging and recharging the global data line capacitance for the full voltage, the read access automatically terminates after discharging only a fraction of the discharging global data line104T or104C. Since power is proportional to CV2, a 30% reduction in discharge/charge voltage, for example, provides a 50% power reduction. Advantageously, read power consumed in a preferred embodiment RAM is only a fraction of that used for a full signal of prior art RAMs.

FIGS. 2A–Bshow an example of a preferred embodiment global data sense and control, e.g.,110in the example ofFIG. 1. As can be seen inFIG. 2A, a sense amplifier140selectively receives the difference signal from the global data lines104T,104C through a pair of pass gates142,144, N-type FETs (NFETs) in this example. The global signal monitor line108drives a global sense amp control (SSAC) circuit150. The SSAC circuit150provides a sense amplifier set signal146to set the sense amplifier140after sufficient signal has developed on the global data lines104T,104C. The SSAC circuit150also provides a sense enable148that opens/closes the pass gates142,144to couple the global data lines104T,104C to the sense amplifier140. The sense enable148also gates pair of restore devices, P-type FETs (PFETs)142R,144R, to selectively float during a read, or to restore the global data lines104T,104C between reads.FIG. 2Bshows an example of the SSAC circuit150, which includes a pair of pulse generators152,154. The global signal monitor line108drives one of the pulse generators152, which pulses the sense amplifier140. A read select signal130′, timed substantially the same as read select130inFIG. 1, initiates a pulse from the second pulse generator154to turn on the pass gates (142,144) and turn off the restore devices142R,144R. The pulse from the first pulse generator152, which sets the sense amplifier142R, terminates the pulse from the second, turning off the pass gates142,144and turning on the restore devices142R,144R.

In this example, the first pulse generator152includes an inverter156driven by the global signal monitor line108. The inverter156drives an inverting delay158and one input of a NAND gate160. The inverting delay158may be, for example, an odd number of series connected inverters (not shown), selected for a propagation delay for the desired pulse width to set the sense amplifier140. The inverting delay158drives the other input to NAND gate160, which provides a low going pulse whenever the output of the first inverter156switches from a low to a high. The NAND gate160drives an inverter162that drives the global sense amplifier set signal146. The second pulse generator154includes a pair of series connected PFETs164,166connected between the supply (Vdd) and the sense enable148output. A pair of series connected NFETs168,170are connected in parallel with a single NFET172, all connected between the output and ground of the sense enable148. An inverter174is connected between the gates of one of the series connected NFETs170and the single NFET172, driving the gate of the single NFET172. The read select signal130′ drives both gate of NFET172and the inverter174. The sense amplifier set signal146drives the gate of one each of the series connected PFETs and series connected NFETs, in this example164and168.

Initially, with the read select signal130′ low and the global signal monitor line108high, the global sense amplifier set signal146is low, series connected PFET164is on, and both series connected NFETs168,170are off. The output of inverter174is high, so PFET166is off, and the single NFET172is on, holding the sense enable148low, which holds the pass gates142,144open and the restore devices142R,144R on. When the read select signal130′ rises, NFET170turns off and the output of the inverter174falls. With the output of inverter174low, single NFET172turns off and PFET164turns on. With both PFETs164,166on, the sense enable148rises turning on the pass gates142,144, and, simultaneously, turning off the restore devices142R,144R, to couple the global data lines104T,104C to the sense amplifier140. When the global signal monitor line108falls below the switch point of the first inverter156, the output of the first inverter156switches high. The high on the output of inverter156matches the high on the output of the inverting delay158, and so, the output of NAND gate160drops. The low from the NAND gate160is inverted by inverter162, which sets the sense amplifier140, turns off PFET164and turns on the second series connected NFET168, i.e. both NFETs168,170are on. Having NFETs168,170on, pulls the sense enable148low, which isolates the input to sense amplifier140and begins restoring the global data lines104T,104C. At this point, the read select signal130′ can return low, which again turns off NFET170and the output of inverter174switches to turn off PFET166and on single NFET172to clamp sense enable148low. Once the high on the output of first inverter156traverses the inverting delay158, the output of the inverting delay158falls. The low on the output of the inverting delay158causes the output of NAND gate160to rise, which causes second inverter162to drive the sense amplifier set signal146low. The read ends with the global signal monitor line108being restored high until the next read access.

FIGS. 3A–Bshow examples of each of a preferred discharge monitor driver112and a preferred global data driver134, which are substantially similar in this example and with like electrical elements labeled identically. Each circuit112,134, includes a NAND gate180driving three (3) series connected inverters182,184,186. One input to the NAND gate180gates a PFET188, that is connected source to drain between Vddand the respective output,108,104. The output of the third inverter186drives an NFET190that is connected drain to source between the respective output,108,104and ground. In the preferred discharge monitor driver112the second input to the NAND gate180is tied high to Vdd. In the preferred global data driver134the global data line104output feeds back to the second input to the NAND gate180.

Thus, in the preferred discharge monitor driver112the NAND gate180and 3 series connected inverters182,184,186act as a non-inverting delay. So, with the read select130′ low, PFET188is on and NFET190is off. When the read select130′ switches, PFET188turns off, and the high begins to propagate through the non-inverting delay. When the high exits the third inverter186, NFET190turns on, to begin pulling the global signal monitor line108low. When the read select130′ returns low, the PFET188turns on immediately to begin pulling the global signal monitor line108high. Again, when the low exits the third inverter186, NFET190turns off. Thus, rise and fall times can be selected for the global signal monitor line108by proper selection of line capacitance (load) and PFET188, NFET190, dimensions.

Similarly, in a preferred global data driver134, the NAND gate180and 3 series connected inverters182,184,186act as a gated non-inverting delay. Prior to a read, with the read select130low, input132is low, because both edge shapers (e.g.,128T and128C inFIG. 1) hold their respective outputs low. So, prior to a read with input132low, PFET188is on, NFET190is off and the global data line104is high. When the read select130switches, one edge shaper (128T or128C) drives an output high. When132rises, the PFET188turns off, and the high begins to propagate through the non-inverting delay. When the high exits the third inverter186, NFET190turns on, to begin pulling the global data line104low. When, the global data line falls below the switching point for NAND gate180, the low begins to propagate through the non-inverting delay and turn off the NFET190. Further, NFET190is held off until the global data line104is returned high, either by the input132being pulled low or by a respective restore device (e.g.,142R,144R inFIG. 2A). When the input132is pulled low, PFET188turns on, immediately, to begin pulling the global data line104high with the respective restore device. Again, when the low exits the third inverter186, NFET190turns off. Thus, global data line104rise and fall times can be determined by selected PFET188, NFET190, and restore device dimensions for the particular line capacitance.

FIG. 4shows a timing example for reading a zero (“0”) in the segment labeled200followed by reading a one (“1”) in the segment labeled202. The read select130rises, which drives one of the pair of complementary intermediate signals132T,C high. Simultaneously, both the global signal monitor line108and one of the global data lines104T,104C begin to fall. The global data line104T or104C falls until pulse generator152triggers. Thus, as can be seen from this example, the low-going global data line104T,104C, stops short of fully discharging line capacitance, at approximately 30% of full charge. Thus, for this single bit cross-section, read access power is approximately half that of full discharge. Further, this savings is realized for each bit of a multi-bit memory word, e.g., 128 bits. Additional savings may be realized by selecting a sense amplifier110with a higher sense point and adjusting the trigger point for the SSAC circuit150. After sufficient delay, e.g., setup time for the global sense amplifier142, the sense amplifier set signal146pulses the sense amplifier142, which passes sensed data106out.

Advantageously, power consumption is dramatically reduced for a preferred embodiment DRAM or eDRAM by self-resetting the data path, without trading performance, density or external complexity.