Method and Device for Short Circuit Detection in Power Semiconductor Switches

Devices and methods are provided, which detect a short circuit condition related to a semiconductor switch. A short circuit condition may be determined when a control signal of the switch exceeds a first reference, and a change of load current of the switch exceeds a second reference.

TECHNICAL FIELD

The present application relates to short circuit detection for power semiconductor switches.

BACKGROUND

Power semiconductor switch devices, like power metal oxide semiconductor field effect transistors (MOSFETs) are insulated gate bipolar transistors (IGBT) are used to switch high voltages and/or currents. For example, in the automotive field such power semiconductor switches may be used to selectively couple an electric motor with supply voltages in the order to some hundreds of volts, with corresponding high currents of the order of above 10 A. In case of a short circuit occurring e.g. in a load coupled to the switch, due to the high voltages extremely high currents may flow, which may damage or even destroy the semiconductor switch device. Therefore, it is desirable to detect such short circuit conditions and take appropriate steps, for example open (switch off) the semiconductor switch device thus interrupting any current flow.

Conventional approaches use a desaturation behavior of the semiconductor switch device to detect short circuits. However, this approach is not suitable for all semiconductor devices and short circuit situations.

SUMMARY

According to an embodiment of a device, the device comprises: a semiconductor switch comprising a control terminal and at least two load terminals; and an evaluation circuit configured to detect a short circuit condition based on a magnitude of a signal at the control terminal and based at least in part on a magnitude of a variation of a load current via the at least two load terminals.

According to another embodiment of a device, the device comprises: a power transistor comprising a first load terminal, a second terminal and a control terminal; a first comparator comprising a first input coupled with the control terminal and a second input to be coupled with a first reference voltage; a second comparator comprising a first input coupled with the second load terminal and a second input to be coupled with a second reference voltage; and an AND gate comprising a first input coupled with an output of the first comparator and a second input coupled with an output of the second comparator.

According to an embodiment of a method of short circuit detection, the method comprises: providing a first voltage at a control terminal of a semiconductor switch; providing a second voltage indicative of a load current change of the semiconductor switch; and detecting a short circuit condition based on a magnitude of the first voltage and of the second voltage.

DETAILED DESCRIPTION

In the following, various embodiments will be discussed in detail referring to the attached drawings. These embodiments are only given by way of example and are not be understood in a limiting sense. For example, describing an embodiment with a plurality of features or components is not to be construed as indicating that all these features or components are necessary for implementation of embodiments. Instead, in other embodiments some of the features or components described may be omitted, and/or may be replaced by alternative features or components. Moreover, apart from the features and components explicitly shown and described, other features or components, for example components conventionally used in power semiconductor devices and associated circuits, may be provided.

Features or components from various embodiments may be combined to form further embodiments. A modification or variation described with respect to one of the embodiments may also be applicable to other embodiments.

Electrical connections or couplings shown in the drawings or described herein may be direct connections or couplings, i.e. direct connections or couplings without intervening elements (for example simple metal connections), or may be indirect connections or couplings, i.e. connections or couplings with one or more additional intervening elements, as long as the general purpose of the connection or coupling, for example to transmit a certain kind of signal, to transmit a certain kind of information or to provide a certain kind of control, is essentially maintained. Connections or couplings may be wire-based connections or couplings (for example metal connections) or wireless connections or couplings unless noted otherwise. Any numerical values given herein are merely for illustration purposes and may vary depending on an implementation.

In embodiments, transistors are used as semiconductor power switches. Generically, transistors are being described as comprising a control terminal and at least two load terminals herein. For example, in case of a field effect transistor (FET) like a metal oxide semiconductor FET (MOSFET), the control terminal is a gate terminal, and the load terminals includes source and drain terminals. In case of a bipolar transistor, the control terminal is a base terminal, and the load terminals are collector and emitter terminals. In case of an insulated gate bipolar transistor (IGBT), the control terminal is a gate terminal, and the load terminals are collector and emitter terminals. Generally, by applying appropriate signals, for example voltages, to the control terminal, a transistor may be switched between an open or non-conducting state, where the transistor is essentially non-conducting between its load terminals (apart from possible small leakage currents) and a conducting or closed state, where the transistor provides a low ohmic connection between its load terminals. The open state is also referred to as a switched-off state, and the closed state is also referred to as a switched-on state of the transistor herein. In embodiments, such transistors are used as power devices to switch comparatively high voltages and/or currents via their load terminals.

Furthermore, embodiments use one or more auxiliary load terminals, for example one or more auxiliary emitters. An auxiliary load terminal is a terminal which is connected with the same contact of the respective semiconductor device (transistor) on a chip die (for example emitter contact), but is not used to carry the current to be switched. For example, in case of a power IGBT, an emitter contact on the chip may be coupled with an emitter terminal as load terminal of a chip package via one or a plurality of bond wires, and when the transistor is closed, current to be switched may flow via these bond wires to the emitter terminal. Additionally, the emitter contact of the chip may be coupled with an additional bond wire (or a plurality of additional bond wires) with an additional auxiliary emitter terminal as auxiliary load terminal, which is not used to carry the load current. As will be explained below such an auxiliary load terminal may for example be used to apply a control voltage, for example a gate-emitter voltage. Furthermore, in embodiments such an auxiliary load terminal may be used for measurements enabling to detect a short circuit condition.

In some embodiments, a short circuit condition may be detected based on a magnitude of a control signal applied to the control terminal and on the magnitude of a signal caused by a load current, in particular by a change of the load current, at a load terminal. Both magnitudes may be measured with respect to a magnitude of a signal at an auxiliary load terminal. In some embodiments, short circuit conditions may be detected early even for semiconductor devices which have a comparatively high desaturation current. Therefore, semiconductor devices having such a high desaturation current may be used, which may have a higher conductivity in a closed state.

Turning now to the Figures, inFIG. 1a device according to an embodiment is illustrated. The device ofFIG. 1comprises a transistor device10. Transistor device10in embodiments is a power transistor device designed to switch high voltages and/or high current. In some embodiments, transistor device10is a power MOSFET. In other embodiments, transistor device10is a power IGBT.

Transistor device10comprises a first load terminal11, a second load terminal14and a control terminal12. Furthermore, transistor device10comprises an auxiliary load terminal13associated with load terminal14. For example, in some embodiments load terminal14may be an emitter terminal, and auxiliary load terminal13may be an auxiliary emitter terminal. In other embodiments, load terminal14may be a drain terminal, and auxiliary load terminal13may be an auxiliary drain terminal.

Furthermore, the device ofFIG. 1comprises an evaluation circuit15to detect a short circuit condition. In embodiments, evaluation circuit15evaluates a magnitude of a control signal at control terminal12and a magnitude of a signal at load terminal14. The signals at terminals12,14may be evaluated with reference to a signal level at auxiliary load terminal13. For example, a gate voltage may be applied between terminals12,13and the magnitude of the gate voltage is evaluated in evaluation circuit15, and a voltage at load terminal14may also be evaluated with respect to a voltage at auxiliary load terminal14(for example as a voltage between emitter terminal and auxiliary emitter terminal). In some embodiments, the signal at load terminal14is caused by a voltage drop of a load current, comprising e.g. an inductive voltage drop caused by a rising load current. In embodiments, a short circuit condition is detected when an absolute signal magnitude at terminal12exceeds a first threshold, and simultaneously an absolute signal magnitude at terminal14exceeds a second threshold.

In case evaluation circuit15detects a short circuit condition, countermeasures may be taken. For example, in some embodiments evaluation circuit15may control transistor device10to open (for example by applying a corresponding signal at terminal12), such that any current flow is interrupted. In other embodiments, the current flow may be merely reduced.

To further illustrate this, more detailed embodiments will be described next by way of example only. In the following embodiments, as an example for a transistor device an insulated gate bipolar transistor (IGBT) is used. However, this is merely for ease of reference, and corresponding principals may also be applied to other transistors (for example power MOSFETs and/or super junction MOSFETs).

FIG. 2is a circuit diagram of a device according to an embodiment. The device ofFIG. 2comprises an IGBT21as a power switch device, which in a closed state carries a current icbetween a collector terminal C and an emitter terminal E. A resistor22and an inductivity23may represent for example a bond wire coupling the emitter terminal E to an emitter contact of transistor21on a chip die thereof. G represents a gate terminal of transistor21, and C represents a collector terminal. Typical inductivities of inductivity23are in the range of some nH, for example about 5 nH. With large currents icand therefore large current slopes dic/dt when switching transistor21, such a comparatively small inductivity may have significant effects and provide a comparatively large voltage drop during such switching events. E′ represents an auxiliary emitter terminal, which is also coupled to the emitter contact of transistor21, for example also via a bond wire. While this bond wire also has a resistance and an inductivity, as no large currents flow via auxiliary emitter terminal E′, the effects of this bond wire are considerably smaller.

A voltage between gate terminal G and auxiliary emitter terminal E′ is labeled gate voltage uginFIG. 2, and a voltage between emitter terminal E and auxiliary emitter terminal E′, which is caused mainly by a voltage drop over resistor22and inductivity23, is labeled uee′.

A driver circuit20applies the gate voltage ugto selectively close or open transistor21in normal operation.

To detect a possible short circuit, the device ofFIG. 2comprises a first comparator24and second comparator25. First comparator24compares the gate voltage ugwith a reference voltage Ug,ref. In the embodiment ofFIG. 2gate terminal G is coupled with a positive input of comparator24, and voltage Ug,refis coupled with a negative input of comparator24. In other embodiments, the logic may be reversed. Ug,refis a reference voltage with respect to the voltage at further emitter E′, such that it is only necessary to couple gate terminal G with comparator24, without explicitly coupling auxiliary emitter E′ with comparator24. In other embodiments, a differential comparator24may be used, which is coupled both with gate terminal G and auxiliary emitter E′. When the voltage ugexceed the reference voltage Ug,ref, comparator24for example outputs a logic 1, and otherwise outputs a logic 0.

Furthermore, the emitter terminal E is coupled with a negative input of comparator25, and a reference voltage Uee′,refis coupled with the positive input of comparator25. In this respect, it has to be noted that both uee′and Uee′,refare negative in the embodiment ofFIG. 2. Therefore, when the an absolute value of (negative) voltage uee′exceeds the absolute value of (negative) voltage Uee′,ref, comparator25outputs a logic 1 and otherwise a logic 0. When both comparators24,25output a logic 1 simultaneously, a latch circuit26detects a short circuit condition and outputs a signal SCDS indicating this short circuit condition to driver20. For example, latch circuit26may comprise an AND gate, such that signal SCDS corresponds to logic 1 when a short circuit is detected. Responsive to the signal SCDS, driver20in case of a short circuit may then open transistor21to interrupt the current is or control transistor21to limit the current ic.

In some embodiments, latch circuit26comprises an AND gate followed by an asynchronous flip flop. The asynchronous flip flop “holds” the signal SCDS on a value indicating a short circuit (for example logic 1) once the short circuit has been detected (both comparators24,25output a logic 1) even if later one of the comparators outputs a 0 again (for example when transitioning from area46to the non-overlapping part of area45inFIG. 4).

While inFIG. 2latch circuit26and driver20are depicted as separate entities, latch circuit26may be a part of driver20in some embodiments. The response of driver20to a short circuit being detected may be designed in any desired manner. For example, an opening of transistor21may be performed comparatively slowly, for example with a comparatively high gate resistance and/or with a higher gate voltage than usually used for opening the transistor (for example zero Volt instead of a negative voltage) to a voltage peak when opening transistor21.

To illustrate the detection of a short circuit with a device as illustrated inFIG. 2further,FIGS. 3 and 4show example switching behaviors of an example IGBT.FIG. 3illustrates a switching behavior in normal operation, andFIG. 4shows a behavior in case of a short circuit.FIGS. 3 and 4show various voltages or currents in arbitrary units over time. The curves ofFIGS. 3 and 4are merely for illustration, and time scale and the form of the curves may vary depending on an implementation of a transistor and control thereof. Typical voltages switched by such a transistor in power applications may be of the order of 600 to 800 V, although higher and lower voltages are also possible. Typical currents may be of the order of 10 A to 40 A but all other values are also possible.

FIG. 3shows a closing of a transistor (switching on) with an inductive load. InFIG. 3, a curve30denotes a collector-emitter voltage, a curve31shows a gate voltage (for example uginFIG. 2), a curve32illustrates a load current (for example icinFIG. 2), and a curve33shows essentially a derivative of curve32with respect to time (di/it). A variation of the current with respect to time may cause an induced voltage as seen by an inductive current sensor, e.g. a voltage drop over inductivity23ofFIG. 2. An area35illustrates an area where the gate voltage31has values above the Miller plateau, which is at about 100 a.u. inFIG. 3. InFIG. 3, the collector emitter voltage (curve30) decreases to a saturation value, and during this decrease the gate voltage (curve31) is held at the Miller plateau (Miller effect).

An area34is an area where the current increases (increase of curve32, curve33different from 0). As can be seen, areas34,35do not overlap in case ofFIG. 3.

FIG. 4shows a corresponding diagram for a short circuit. A curve40shows a collector-emitter voltage, a curve41illustrates a gate voltage, a curve42illustrates a load current and a curve43illustrates the derivative of the current with respect to time, i.e. curves40to43inFIG. 4correspond to curves30to33inFIG. 3, respectively. As can be seen, due to the short circuit the current (curve42) rises to considerably higher values than in case ofFIG. 3. Furthermore, in case ofFIG. 4an area where the current increases (44inFIG. 4) overlaps with an area45where the gate voltage (curve41) is higher than the Miller plateau level ofFIG. 3. The overlapping region is labeled46inFIG. 4. It should be noted that inFIG. 4there is no Miller plateau, as due to the short circuit the transistor cannot reduce its collector-emitter voltage as in case ofFIG. 3.

Therefore, as can be seen from comparingFIGS. 4 and 3, in case of a short circuit, there is the region46where the gate voltage (curve41) is above a threshold (for example above the Miller plateau), and the derivative of the current over time (43) is non-zero. This changing current in the embodiment ofFIG. 2causes a voltage drop over inductivity23, and which leads to a correspondingly high voltage uee′, in particular this voltage being above the threshold Uee′,ref. Therefore, as explained previously, a short circuit may be detected when both ugand uee′have absolute values above correspondingly chosen thresholds (Ug,refand Uee′,refinFIG. 2).

In other words, in the situation ofFIG. 3, comparators24,25ofFIG. 2output a logic 1 at different, separate times (for example comparator25during area34inFIG. 3and comparator24during area35inFIG. 3), while in case of a short circuit as shown inFIG. 4both comparators output a logic 1 simultaneously for a certain time (for example during area46ofFIG. 4).

With the approach explained above, both short circuits with a low inductivity load and short circuits with a high inductivity load as illustrated inFIGS. 3 and 4may be detected. With a low inductive short circuit when the transistor is already closed, the gate voltage is already at its end value (i.e. above the threshold), and the short circuit leads to rapid increase in current and therefore leads to the voltage uee′also exceeding the threshold as above. Therefore, not only short circuits when switching on the transistor as illustrated inFIG. 4, but also short circuits when the transistor is already switched on may be detected.

The reference voltage Uee′,refin embodiments, as follows from the above explanations, may be chosen such that the resistive voltage drop of the load current of transistor21is not sufficient to exceed the threshold in normal operation, but an additional inductive voltage drop over inductivity23when the current icincreases or a significantly higher load current icthan in normal operation is needed to exceed the reference voltage Uee′,ref.

In some embodiments, Uee′,reftherefore may be chosen such that an ohmic voltage drop of the transistor22is sufficient in case icexceeds a nominal value (for example when it three times the nominal value). In this case, also short circuits with loads having a very high inductivity, which leads to a slow increase of the current (lower di/dt) may be detected, as such low di/dt leads to a low voltage at inductivity23.

Embodiments may be used with conventional drivers using a desaturation of a transistor to detect a short circuit. A corresponding embodiment is illustrated inFIG. 5. In order to avoid repetitions, elements common to the embodiments ofFIGS. 5 and 2bear the same reference numerals and will not be discussed again in detail. InFIG. 5, a conventional driver50is used to control transistor21. Driver50has a desaturation (DESAT) output terminal which in conventional approaches would be used for detecting a desaturation state of transistor21to detect a short circuit. In the embodiment ofFIG. 5, this pin or terminal instead is used sensing a short circuit condition indicated by the detection approach discussed above with respect toFIGS. 2 to 4. In particular, inFIG. 5outputs of the comparators24,25are fed to an AND gate56, which may be followed by delay element (not shown inFIG. 5). The output of AND gate56is coupled with the DESAT output terminal of driver50via a diode57. Driver50provides a low constant current at the DESAT terminal, which conventionally is coupled via diode57with collector terminal C of transistor21. In many conventional cases transistor modules, in particular IGBT modules, may have an additional collector terminal (auxiliary collector terminal) for this case. When transistor21is in desaturation, i.e. the collector emitter voltage exceeds a threshold (for example by several Volts), driver50cannot drive the above-mentioned constant current anymore against this voltage and thus detects an error.

In the device ofFIG. 5, AND gate56outputs a zero (for example zero Volt) in case no short circuit is detected, and the above-mentioned constant current output by driver50may be sunk to this zero Volt level and therefore be driven by driver50. In case of a short circuit, both comparators24and25as output above output a logic 1, and therefor AND gate56outputs a logic 1, which may for example correspond to a voltage in the range of 12 to 15 Volt. Against such a voltage, driver50cannot drive the constant current any longer, and therefore detects the short circuit condition and takes appropriate measures, for example switching off (opening) transistor21.

In the embodiment ofFIG. 5, for example comparators24,25and AND gate56may be integrated in a module, possibly together with transistor21, which then may be combined with a conventional driver50. In some embodiments, additionally a low pass filter may be provided at the output of AND gate56. A low pass filter or delay element may ensure that in case of a short circuit a voltage corresponding to logic 1 is present at the output of AND gate56for a sufficiently long time for driver50to react.

In the above embodiments, gate voltage ugis applied between gate terminal G and auxiliary emitter E′, and the voltage uee′is measured between emitter E and auxiliary emitter E′. In other embodiments, a further auxiliary emitter may be used. A corresponding embodiment is illustrated inFIG. 6.FIG. 6illustrates a part of a device according to an embodiment. Other parts, for example a short circuit detection, may be implemented using for example two comparators as illustrated inFIGS. 2 and 5.

As illustrated inFIG. 6, when driver20controls transistor21, during switching events a gate current igflows via gate terminal G, a gate resistance60, a gate-emitter capacitance61of transistor21, a resistor63and an inductivity62to auxiliary emitter terminal E′. Inductivity62and resistor63represent a bond wire which, as mentioned previously, couples an emitter contact of transistor21with auxiliary emitter terminal E′.

Changes of igwhich occur at switching events of transistor21may lead to a non-negligible voltage drop over inductivity62and resistor63, which influences the voltage uee′, which in the above explained embodiments was used for detecting a short circuit. In some instances, depending on the magnitude of dig/dt and the values of inductivity62and resistor63, this voltage drop could lead to an inadvertent indication of a short circuit with the circuits discussed previously, in particular to comparator25inadvertently outputting a logic 1. It is to be noted that in other implementations, depending on the voltages and currents used and the particular transistor implementation, this need not be an issue. Such an inadvertent detection may in particular occur when switching off (opening) transistor21, as at this time when starting the switching comparator24outputs a logic 1, corresponding to areas35ofFIG. 3.

In such implementations where there is a danger of an inadvertent short circuit detection although no short circuit is present, in embodiments a further auxiliary emitter E″ may be provided as shown inFIG. 6, and instead of the voltage uee′a voltage uee″between emitter E and further auxiliary emitter E″ may be used for detecting a short circuit condition. Further auxiliary emitter E″ may be an additional terminal which is coupled to an emitter contact of transistor21for example via one or more bond wires. As further auxiliary emitter E″ is only used for obtaining the voltage uee″and not for gate control, the above explained effects when switching transistor21do not affect the voltage uee″.

In other embodiments, yet other terminals or internal nodes may be used for measuring an inductive and/or ohmic voltage drop. In embodiments, generally an inductive and/or ohmic voltage drop is measured between two nodes, wherein the load current flows between the two notes. Depending on the nodes, the corresponding reference voltage Uee′, refhas to be adjusted accordingly. An example for such an embodiment is shown inFIG. 7. Again, elements or components already discussed previously bear the same reference numerals and will not be discussed again in detail.

Instead of measuring voltage uee′, in the embodiment ofFIG. 7a voltage between a node71and emitter E is measured by a differential amplifier70and provided to comparator25. Apart from a possibly necessary adjustment of Uee′, ref, the effect is the same as using the voltage uee′, i.e. at high slopes of ica high voltage drop over inductivity23is generated, which is then used for short circuit detection. Instead of AND gate56, any other usable latch circuit may be used. Furthermore, instead of driver20, a driver like driver50with a DESAT terminal may be used. Node71may for example be a node on a metallic conductive part within a package containing transistor21.

In some implementations, when switching on the transistor comparatively strong oscillations in the load current icmay occur, which in some cases may lead to an inadvertent detection of a short circuit although no short circuit is present. In implementations where this may occur, a detection circuit detecting oscillations may be used, which deactivates the short circuit detection (for example by setting an output of latch circuit26inFIG. 2to zero) temporarily, for example for a pre-defined time, when oscillations are detected. For example, such a deactivation may be performed when a negative dic/dt is detected, for example via a positive voltage drop over inductivity23. Such a negative value of dic/dt does usually not occur during a short circuit, where icincreases as explained with reference toFIG. 4.

As shown above, using a measurement of a voltage drop over resistance22and inductivity23, which may be a parasitic resistance and inductivity of a bond wire, a hard short circuit (where the current rapidly increases) may be detected mainly via the voltage drop over the inductivity, while a “soft” short circuit with a slower increase of the current may be detected via a voltage drop over a resistance like resistance22. For detecting only a hard short circuit with a high inductive voltage drop, a higher threshold voltage at comparator25could be chosen. In contrast, a “soft” short circuit needs a lower reference voltage at comparator25to be sensitive enough for short circuits. In embodiments, high reference voltages may be desirable to reduce a likelihood of an erroneous short circuit detections. Therefore, in embodiments the reference voltage Uee′, ref supplied to comparator25may be adaptable.

For example, in embodiments as long as the gate voltage ugis below a threshold value, a comparatively higher value of Uee′, ref may be used. As soon as the gate voltage exceeds a certain threshold value, a comparatively lower reference voltage Uee′, ref may be used. In such an embodiment, when the transistor is switched on, the gate voltage is low, and a high threshold voltage comparator25is used. Therefore, a normal switching on may be performed with a comparatively high robustness against erroneous detections.

When a short circuit is present when the transistor is switched on, the threshold value is exceeded (in particular in case of a low inductive short circuit). In case of a high inductive short circuit (i.e. a short circuit via a high inductivity as a load), the gate voltage reaches its maximum value, whereas the dic/dt-behavior is mainly dominated by the short circuit inductivity. When the high gate voltage is used, the voltage drop over resistor22and inductivity23is compared against a lower threshold voltage, thus being able to detect also this type of fault. Also, through this, the detection may react quickly to very soft short circuits during a switched-on state of the transistor.

In some applications, a plurality of power transistors may be used in combination. In such application, it may happen that switching one of the transistors inadvertently triggers a short circuit detection in another one of the transistors. In such cases, to prevent an erroneous short circuit detection during switching of one of the transistors a short circuit detection of another one of the transistors may be temporarily deactivated. An example for such an approach will now be discussed with reference toFIGS. 8 and 9.

FIG. 8shows an application scenario where power transistors82A,82B,82C,85A,85B and85C are used to control an electric motor81. In the embodiments ofFIG. 8electric motor81is a three-phase motor. Numeral80denotes a power source, for example a battery. In some embodiments, battery80may be a battery of an automobile, and motor81may be an electric motor in the automobile. Transistors82A and85A form a first half bridge selectively supplying current to a first terminal of motor81, transistors82B and85B form a second half bridge selectively supplying current to a second terminal of motor81, and transistors82C and85C form a third half bridge selectively supplying current to a third terminal of motor81. Transistors82A to82C,85A to85C are provided with freewheel diodes83A to83C,86A to86C, respectively, as illustrated inFIG. 8.

In embodiments, for cost reasons the transistors85A to85C (also referred to as low side transistors), which are generally labeled84inFIG. 8, are supplied by a common logic. In particular, transistors85A,85B and85C inFIG. 8have a common emitter terminal E, but separate auxiliary emitter terminals E′1, E′2, E′3and separate gate terminals G1, G2and G3. For the transistors82A to82C in embodiments separate short circuit detection logics with separate emitter terminals E are provided, such that this problem is less of an issue for these transistors.

A short circuit detection for transistors85A to85C for example may use a voltage drop between emitter terminal E and the auxiliary emitter terminal E′ associated with the respective transistor, as explained previously. However, switching one of transistors85A to85C may cause a voltage drop at inductivities88A to88C which may lead to an erroneous short circuit detection at another one of the transistors. In embodiments, therefore a short circuit detection for one of the transistors, for example for transistor85A, is only active when none of the other transistors, for example85B and85C, is currently switching. In other words, the detection of a short circuit is only active when the other transistors are in a stable closed or open condition.

This condition may be obtained by monitoring gate voltages at gates G1, G2, G3. For example, when the gate voltage is below a lower threshold, for example zero Volt or minus five Volt, the transistor is in a stable open state. If the gate voltage is above an upper threshold, for example plus eleven Volt, plus twelve Volt etc., the transistor is in a stable closed state. If the gate voltage is between the above-mentioned threshold values, the transistor is evaluated as just switching.

As such switching events usually have a very short duration, for example smaller than one microsecond, the short circuit detection is only deactivated for a short time.

FIG. 9shows a detection logic which is for example usable for the three transistors85A to85C ofFIG. 8. For each transistor, an input stage90A,90B and90C, respectively, is provided. In the following, input stage90A will be described in detail. Input stages90B,90C are both implemented correspondingly, and the reference numerals correspond to each other, wherein an “A” for input stage90A is replaced by a “B” for input stage90B and a “C” for input stage90C. For example, component91A of input stage90A corresponds to component91B in input stage90B and to component91C in input stage90C.

Input stage90A comprises a first comparator91A, a second comparator92A and an AND gate94A. Comparator91A essentially corresponds to comparator25discussed previously for example inFIG. 2and compares a voltage drop caused by a load current of a first transistor (for example85A ofFIG. 8) at an inductive load (for example an inductivity of a bond wire, as discussed previously) with a reference value. The voltage drop of the first transistor is marked di/dt1(as the inductive voltage drop depends on the derivative of the load current over time), and the corresponding reference value is marked di/dtrefinFIG. 9. di/dtrefmay for example correspond to Uee,refdiscussed previously. The values di/dt1and di/dtrefas explained previously with respect toFIG. 2are negative values, such that comparator91A outputs a logic 1 when an absolute value of the voltage drop exceeds a threshold.

Second comparator92A compares the gate voltage of the first transistor, labeled gate1inFIG. 9, with an upper gate voltage threshold Gateref,high, which may correspond to Ug,refofFIG. 2. When the gate voltage of the first transistor exceeds the reference value Gateref,highsecond comparator92A outputs a logic 1. When both comparators91A,92A output a logic 1, AND gate94A outputs a logic 1, which as discussed previously may indicate a short circuit condition.

Furthermore, input stage98comprises a third comparator93A. Third comparator93A compares the gate voltage Gate1with a lower reference value Gateref,low, which is smaller than the reference value Gateref,high. When the gate voltage Gate exceeds the lower gate reference value Gateref,low, third comparator93A outputs a logic 1 and otherwise a logic 0.

The outputs of second comparator92A and third comparator93A are provided to an XOR gate95A. When the first transistor is in a switched-off state, the gate voltage Gate1is low (below the lower reference Gateref,low) and therefore both comparators92A,93A output a logic 0. Therefore, in this state XOR gate outputs a logic 0.

When the transistor is fully switched on, gate voltage Gate1exceeds both reference voltages Gateref,highand Gateref,low, and therefore both comparators92A,93A output a logic 1. Consequently, in this state XOR gate95A also outputs a logic 0.

When the transistor is switching, the gate voltage is between Gateref,lowand Gateref,high. In this state, comparator93A outputs a logic 1, and comparator92A outputs a logic 0. Consequently, in this state XOR gate95A outputs a logic 1. To summarize, therefore XOR gate95A outputs a logic 1 when the transistor is switching, and outputs a logic 0 when the transistor is in a stable switched-off state or in a stable switched-on state.

Therefore, in input stage90A a second comparator92A has two functions: on the one hand, it is used for short circuit detection similar to comparator24ofFIG. 2(via AND gate94A), and on the other hand it is used for detecting a switching state of the transistor (via XOR gate95A). In other embodiments, separate comparators may be used for these two functions, possibly with different threshold values.

As mentioned above, the input stages90B,90C operate accordingly.

In the embodiment ofFIG. 9, the reference values (di/dtref, Gateref,highand Gateref,low) are the same for all three input stages90A,90B,90C. In other embodiments, different threshold voltages may be used for different input stages.

The outputs of XOR gates95A,95B and95C are provided to a triple OR gate96. Therefore, triple OR gate96outputs a logic 1 when at least one of the three transistors is currently switching (i.e. its gate voltage between Gateref,lowand Gateref,high) and outputs a logic 0 only when none of the transistors is switching.

Furthermore, the detection logic ofFIG. 9comprises an output stage97A,97B and97C, respectively, for each of the transistors. The output stages97A to97C have the same structure, and similar to the input stages only output stage97A will be described in detail, the other output stages97B,97C operating accordingly.

Output stage97A comprises an AND gate98A and an XNOR gate99A. XNOR99A receives outputs from XOR gate95A and from triple OR gate96. When both XOR gate95A and triple OR gate96output a logic 0 (none of the transistors is switching), XNOR gate99A outputs a logic 1. When both XOR gate95A and triple OR gate96output a logic 1 (the first transistor is switching), XNOR gate99A also outputs a logic 1. In these two cases, AND gate98A, which receives an output of XNOR gate99A and of AND gate94A, has an output state according to the output state of AND gate94A, and therefore the short circuit detection provided by AND gate94A is output. In other words, in these cases the short circuit detection is enabled.

However, when XOR gate95A outputs a logic 0, and triple OR gate96outputs a logic 1, this means that the first transistor is not switching, but one of the other transistors is currently switching. In this case, XNOR gate99A outputs a logic 0, and therefore AND gate98A also outputs a logic 0, thus effectively disabling the short circuit detection for the first transistor during a switching of one of the other two transistors (or both). The same applies to the other transistors.

It should be noted that whileFIGS. 8 and 9show examples for three transistors, application of the techniques described here are not limited to three transistors (or three half bridges as inFIG. 8) but may be applied to any plurality of transistors (for example two transistors or four or more transistors, two half bridges or four or more half bridges) where a switching event in one of the transistors may lead to an erroneous short circuit detection in one of the other transistors.

As mentioned previously, in some embodiments instead of switching a transistor of completely immediately, at least at first the current may be reduced.FIG. 10illustrates a corresponding embodiment. Again, to avoid repetitions, features and elements already discussed in previous Figs. LikeFIG. 2bear the same reference numerals, and will not be discussed again in detail.

InFIG. 10, a gate resistance100is additionally explicitly shown, although such a gate resistance may also be present in other embodiments. Moreover, the gate terminal of transistor21in the embodiment ofFIG. 10is coupled to ground via a Zener diode101, an optional diode102and a transistor103. Transistor103is controlled by the short circuit detection signal output by latch circuit26.

As long as no short circuit is detected, transistor103is open, and the path provided by Zener diode101, diode102and transistor103essentially has no effect on the operation of the device shown. As soon as a short circuit is detected, the output signal of latch circuit26closes transistor103. This reduces the gate voltage of transistor21to the reverse voltage of Zener diode101, for example to between 8 and 12 V. Therefore, transistor21is still operated despite the short circuit, but with a reduced gate voltage and consequently lower load current, which causes a reduced power dissipation. Under these conditions, transistor21may carry the short circuit current longer without being damaged. After some time, driver20then may completely switch off transistor21. For example, driver20may switch off transistor21based on the signal from latch circuit26, or may use a conventional desaturation based short circuit detection.

Diode102is optional and prevents a current flow from ground to driver20via gate resistor100when transistor21is open and thus the gate voltage is negative.

FIG. 11illustrates a device according to a further embodiment. The device ofFIG. 11again comprises transistor21, which is controlled via a gate voltage Vgateusing a gate terminal via a gate resistor110. Moreover, transistor21has a collector terminal C, an emitter terminal E and an auxiliary emitter terminal E′ as explained previously.111represent inductivities and resistances between auxiliary emitter terminal E′ and emitter terminal E, for example caused by bond wires as explained previously.

The embodiment ofFIG. 11comprises a short circuit detection circuit as explained previously, with comparators1111and1112corresponding to comparators24,25explained previously. Vref,gatecorresponds to Ug,refexplained previously, and Vref,di/dtcorresponds to Uee′,refexplained previously. The outputs of comparators1111,1112are fed to an AND gate1113, which for example corresponds to AND gate56discussed previously. Therefore, an output of logic 1 from AND gate1113indicates a short circuit condition.

Furthermore, the embodiment ofFIG. 11comprises additional circuitry, the function of which will be explained next.

A circuit portion116comprises a comparator118and a low pass filter formed by a resistor119and a capacitor1110. Comparator118compares the gate voltage with a reference voltage Vref. When the gate voltage is smaller than 0 V indicating a switched-off state of transistor21, comparator118outputs a logic 0 to the above-mentioned low path. Therefore, AND gate117output a logic 0, which causes transistor111which in the embodiment ofFIG. 11, is a p channel MOSFET, to close. Therefore, the gate voltage at a gate contact of transistor21is drawn to a predetermined value Vcvia transistor111and diode112.

When now the gate driver is activated to close transistor21, as diode112is blocking the potential at the gate of transistor21may rise to Vcand beyond. Prior to reaching Vc, Vrefis exceeded at comparator118, such that comparator118outputs a logic 1 to low path119,1110. Therefore, the input of AND gate117coupled to block116rises to logic 1 according to the time constant of the low pass filter.

An output of AND gate1113is coupled to a flip-flop1114, and an inverted output of flip-flop1114is coupled to an input of AND gate117. When at the above mentioned closing of transistor21no short circuit is present, AND gate1113outputs a logic 0 and therefore the inverted output of flip flop1114outputs a logic 1 to AND gate117. When both inputs of AND gate117are at logic 1 (after the time constant of the low pass filter), AND gate117outputs a logic 1, thus opening transistor111. Therefore, the gate voltage can continue to rise, finally closing transistor21.

If, however, a short circuit is present, the output of the inverted output of flip-flop1114is 0 (as in this case AND gate1113outputs a logic 1), and transistor111keeps conducting. This inhibits a rise of a gate voltage of transistor21at least to some extent, thus delaying the transistor from turning fully on and therefore reducing a probability that transistor21is damaged prior to being turned off due to the detected short circuit.

Reference number113inFIG. 11denotes a capacitance providing voltage Vc. Instead of capacitance113, also a Zener diode may be provided. Vcmay be for example of the order of 8 to 12 V in some embodiments.

Furthermore, a reset input R of flip-flop1114is coupled with the output of comparator1111. This may lead to a self-reset functionality of flip-flop1114after a short circuit condition has passed.

Vref,offmay be selected depending on how transistor21is driven. When the gate voltage is set to negative voltage for opening transistor21, Vref,offmay be set for example to 0 V. When the gate voltage is set to 0 V for opening transistor21, Vref,offmay for example be set to a value between 0 V and the threshold voltage of transistor21.

The logic illustrated inFIG. 11may be adapted for the use of an n channel transistor instead of p channel transistor111, by changing the logic levels accordingly.

As already mentioned, the various modifications shown may be combined with each other. For instance, while several embodiments show modifications of the embodiment ofFIG. 2, two or more of these modifications from different embodiments may be implemented jointly.

FIG. 12illustrates a method according to an embodiment. While the method ofFIG. 12is shown and described as a series of acts or events, the order in which these acts or events are presented is not be construed as limiting. The method ofFIG. 12may be implemented using the devices shown and discussed with reference toFIGS. 1 to 11, but is not limited thereto. Modifications and variations discussed with respect to the devices ofFIGS. 1 to 11may also be applied to the method ofFIG. 12.

At120inFIG. 12, a voltage at a control terminal of a semiconductor switch, for example a gate voltage of an IGBT or MOSFET, is provided. At121, a voltage caused by voltage drop of a load current at a load terminal, for example a voltage between emitter and auxiliary emitter as described above, is provided. At122, a short circuit condition is detected based on a magnitude of the voltages provided at120and121. For example, as explained above, a short circuit condition may be determined when both voltages exceed respective magnitudes (in particular absolute magnitudes) at a same time.

As already mentioned, the embodiments above should not be construed as limiting, but merely serve illustrative purposes.