Multi-chip package for imaging systems

A multi-chip package may include an image sensor chip, an image signal processor (ISP) chip, a cover glass, and a package substrate. The ISP chip may be placed on the substrate. The image sensor chip may be placed over the ISP chip. An adhesive film may be formed between the ISP and image sensor chips. A cover glass may be suspended above the image sensor chip. The ISP chip and the image sensor chip may be wire bonded to the substrate. The multi-chip package may be hermetically sealed using a liquid compound or a dam structure. During normal operation, the ISP chip sends control signals to the image sensor chip via a first set of wire bond members and conductive traces in the substrate while the image sensor chip sends output signals to the ISP chip via a second set of wire bond terminals and conductive traces in the substrate.

BACKGROUND

This relates generally to imaging systems, and more particularly, to imaging systems with stacked-chip image sensors.

Image sensors are commonly used in imaging systems such as cellular telephones, cameras, and computers to capture images. In a typical arrangement, an image sensor includes an array of image sensor pixels and associated control and processing circuitry for operating the image sensor pixels. In a conventional imaging system, the control and processing circuitry is formed laterally from the image sensor pixels on a silicon semiconductor substrate. Each row of image sensor pixels typically communicates with the control circuitry along a common metal line on the silicon semiconductor substrate. Similarly, each column of image sensor pixels communicates with the control circuitry along a common metal line. Image signals captured using the image sensor pixels are then fed to the processing circuitry for performing analog-to-digital signal conversion and desired digital signal processing operations.

In this type of system, a substantial amount of valuable integrated circuit real estate has to be allocated to the control and processing circuitry. This increases the lateral footprint of the image sensor chip. An increased lateral footprint may be undesirable for compact imaging systems such as cellular telephones and cameras.

It would therefore be desirable to be able to provide improved imaging systems such as imaging systems with stacked-chip image sensors and to provide ways for packaging such types of stacked-chip image sensors.

DETAILED DESCRIPTION

Digital camera modules are widely used in imaging systems such as digital cameras, computers, cellular telephones, or other electronic devices. These imaging systems may include image sensors that gather incoming light to capture an image. The image sensors may include arrays of image sensor pixels. The pixels in an image sensor may include photosensitive elements such as photodiodes that convert the incoming light into digital data. Image sensors may have any number of pixels (e.g., hundreds or thousands or more). A typical image sensor may, for example, have hundreds of thousands or millions of pixels (e.g., megapixels).

FIG. 1is a diagram of an illustrative imaging system for capturing images. Imaging system10ofFIG. 1may be a portable imaging system such as a camera, a cellular telephone, a video camera, or other6imaging device that captures digital image data. Camera module12may be used to convert incoming light into digital image data. Camera module12may include an array of lenses14and a corresponding array of image sensors16(sometimes referred to as an image sensor array). Image sensors16may provide image data to control and processing circuitry18.

Control and processing circuitry18may include one or more integrated circuits (e.g., image processing circuits, microprocessors, storage devices such as random-access memory and non-volatile memory, etc.) and may be implemented using components that are separate from camera module12and/or that form part of camera module12(e.g., circuits that form part of an integrated circuit that includes image sensors16or an integrated circuit within module12that is associated with image sensors16). Image data that has been captured by camera module12may be processed and stored using control and processing circuitry18.

Processed image data may, if desired, be provided to external equipment (e.g., a computer or other device) using wired and/or wireless communications paths coupled to control and processing circuitry18. Control processing circuitry may, for example, include row driver circuitry configured to drive row control signals associated with the image pixel arrays in image sensor array16, column control circuitry coupled to column output lines associated with the image pixel arrays in image sensor array16, circuitry for optimizing captured image quality, circuitry for running a built-in firmware, circuitry configured to implement desired image capture functions such as facial recognition, and other digital signal processing circuitry.

In some embodiments, a color filter array (CFA) may be formed on top of image sensor array16(not shown for simplicity). The color filters that are used for image sensor pixel arrays in the image sensors may, for example, be red filters, blue filters, and green filters. Each filter may form a continuous color filter layer that covers an individual pixel in an image pixel array, an image pixel array in an image sensor with multiple image pixel arrays, or an image sensor in an array of image sensors. Other filters such as white color filters, dual-band IR cutoff filters (e.g., filters that allow visible light and a range of infrared light emitted by LED lights), etc. may also be used.

As shown inFIG. 2, image sensor array16may be formed on an integrated circuit substrate17. Image sensor array16may therefore sometimes be referred to an image sensor integrated circuit, an image sensor chip, or an image sensor die. In the example ofFIG. 2, image sensor chip16includes four image pixel arrays such as image pixel arrays20on die17. However, this is merely illustrative. If desired, image sensor chip16may include a single image pixel array, two image pixel arrays, three image pixel arrays, or more than four image pixel arrays.

Each pixel array20may have image sensor pixels such as image pixels30that are arranged in rows and columns. Image sensor pixel arrays20may have any suitable resolution (e.g., 640×480, 4096×3072, etc.). Image sensor pixels30may be formed on a planar surface (e.g., parallel to the x-y plane ofFIG. 2) of a semiconductor substrate such as a silicon die.

As shown inFIG. 2, each image pixel array20may be provided with a plurality of conductive paths such as row interconnects40R and column interconnects40C. Row interconnects40R and column interconnects40C may be respectively coupled to first and second sets of wire bond pads33formed along the border of die16. Configured in this way, row control signals may be conveyed to each image pixel30over row interconnects40R via the first set of wire bond pads33(as indicated by path96), whereas pixel output voltage signals may be received from column interconnects40C via the second set of wire bond pads33(as indicated by path98).

As consumer demand pushes towards compact high-resolution imaging devices, it becomes increasingly challenging to design an entire imaging system on a single integrated circuit die (sometimes referred to as a system-on-chip). Forming a high density image sensor array16and circuitry18on a single chip within a constrained amount of area can be an extremely difficult and time consuming design task.

An alternative to single-die packages is an arrangement in which multiple dies are placed within a single package. Such types of packages that contain multiple interconnected dies may sometimes be referred to as systems-in-package (SiPs), multi-chip modules (MCM), or multi-chip packages. Placing multiple chips (dies) into a single package may provide a more efficient use of area by allowing multiple dies to be stacked on top of one another (e.g., an image sensor chip may be stacked on top of a digital image processor chip), may allow each die to be implemented using the most appropriate technology process (e.g., an image sensor chip may be implemented using a first technology node, whereas the digital image processor chip may be implemented using a second technology node that is different than the first technology node), may increase the performance of die-to-die interface (e.g., driving signals from one die to another within a single package is substantially easier than driving signals from one package to another, thereby reducing power consumption of associated input-output buffers), and may help simplify printed circuit board (PCB) design (i.e., the design of the PCB on which the multi-chip package is mounted during normal system operation).

FIG. 3is a cross-sectional side view of a multi-chip package99for housing an imaging system10. As shown inFIG. 3, multi-chip package99may include a package substrate such as package substrate100(sometimes referred to as an interposer substrate), an image signal processing die (e.g., a chip that contains image sensor control and processing circuitry18) mounted on substrate100, an image sensor die (e.g., a chip that contains image sensor array16) mounted over die18, and a cover glass118mounted over die16. Image signal processing die18may include along its periphery wire bond pads such as wire bond pads19that are connected to corresponding wire contact members102(sometimes referred to as wire pins, wire leads, or lead fingers) that are formed at a top surface of substrate100on which die18is mounted via bond wires108. Image sensor die16may include along its periphery wire bond pads such as wire bond pads33that are connected to corresponding wire contact members104that are formed at the top surface of substrate100via bond wires110. Wires108and110may be formed from gold (Au), aluminum (Al), copper (Cu), silver (Ag), other metals, or a combination of these materials (as examples).

Dies16and18may exchange digital and/or analog signals via conductive interposer traces106formed within interposer substrate100. For example, image signal processing (ISP) die18may send row control signals for selectively accessing desired pixels30within image sensor die10via a first set of wires108, traces106, and wires110, whereas signals output from each image sensor pixel on image sensor die16may be conveyed to die18via a second set of wires108, traces106, and wires110. Package contact members such as contact members130may be formed at a bottom surface of substrate100. Package contact members130may be coupled to at least some of wire contact members102associated with die18for receiving processed image data. Package contact members130may include pins, leads, springs, solder balls, or other conductive structures suitable for engaging with corresponding mating structures on a printed circuit board (as an example).

As shown inFIG. 3, a layer of adhesive material112may be formed between die16and die18. Adhesive material112may, for example, be formed using an epoxy-based adhesive, a rubber-based adhesive, a polyimide-based adhesive, a polyolefin-based adhesive, an acrylic-based adhesive, other suitable dielectric materials, or a combination of these materials. In one suitable embodiment, adhesive film112may be disposed in a way such that the area within the image signal processor wire bond pads19is substantially covered by film112(see, e.g.,FIG. 3andFIG. 4A). In another suitable embodiment, adhesive material112may be disposed in a ring pattern that only covers the image signal processor wire bond pads19(see, e.g.,FIG. 4B). The patterns as shown inFIGS. 4A and 4Bare merely illustrative and do not serve to limit the scope of the present invention. If desired, adhesive material112may be disposed in any desired pattern over die18to sufficiently secure die16on top of die18.

A ring-shaped cover glass support structure such as support structure114may be formed between image sensor die16and cover glass118. Cover glass support structure114may be formed within the image sensor wire bond pads33while not covering the image pixel arrays formed at the surface of die16(i.e., the image pixel arrays are capable of receiving incoming light through cover glass118without being obstructed by support structure114). Structure114may be formed from polymers such as epoxy resin, polyimide, polyolefin, acrylic, glass, ceramic, other suitable dielectric materials, or a combination of these materials (as examples).

Cover glass118may, in general, be formed from clear glass, plastic, or other suitable transparent material. Cover glass118may be placed over image sensor die16to prevent dust and other undesired particles from contaminating and attaching to the surface of image sensor chip16. Region116that is contained within cover glass118, image sensor die16, and support structure114may be devoid of air (i.e., a vacuum) and undesired contaminants.

Multi-chip package99may be hermetically sealed using a liquid compound such as liquid sealant120. Liquid sealant120may be an epoxy resin sealant, silicone resin sealant, and other suitable types of semiconductor packaging sealants. As shown inFIG. 3, sealant120fills in any free space between bond wires108and110and provides a protective non-conductive layer that extends from the edge of cover glass118to the edge of interposer substrate100.

The configuration of multi-chip package99as shown inFIG. 3is merely illustrative and does not serve to limit the scope of the present invention. In general, dies that are part of a multi-chip package99may be contained within a housing that is molded from plastic, resin, ceramic, or other suitable materials. Multi-chip package99may contain more than two vertically stacked dies, more than three vertically stacked dies, two horizontally stacked dies (e.g., dies that are positioned laterally with respect to one another on a common interposer substrate), more than two horizontally stacked dies, multiple vertically and horizontal stacked dies, etc.

FIG. 5is a flow chart of illustrative steps involved in forming a multi-chip package of the type described in connection withFIG. 3. At step200, image signal processing die18may be placed on top of interposer substrate100.

At step202, image signal processing die18may be wire bonded to interposer substrate100(e.g., conductive wires108may have first ends that are soldered to wire bond pads19and second ends that are soldered to corresponding conductive members102).

At step204, an uncured adhesive layer112may be disposed on top of image signal processor die18using dispensing equipment.

While adhesive layer112is an uncured state, image sensor die16may be placed on top of adhesive layer112(step206). When image sensor die16is in its proper position, adhesive layer112may be thermally cured (as an example).

At step208, image sensor die16may be wire bonded to interposer substrate100(e.g., conductive wires110may have first ends that are soldered to wire bond pads33and second ends that are soldered to corresponding conductive members104).

At step210, ring-shaped cover glass support structure114may be formed on top of image sensor die16using dispensing equipment.

While support structure114is in an uncured state, cover glass118may be placed on top of cover glass support structure144(step212). A vacuum pump may be used during step212to create a vacuum in region116contained within cover glass118, image sensor die16, and structure114. When cover glass118is in its proper position, structure114may be cured using ultraviolet (UV) light (as an example).

At step214, multi-chip package99may be hermetically sealed using liquid compound120(e.g., a thermally-cured epoxy resin) to cover wires108and110and to secure cover glass118. Liquid compound120may be dispensed and cured without the use of a molding tool.

The steps ofFIG. 5are merely illustrative. If desired, other necessary equipment for forming package99ofFIG. 3may be used (e.g., thermal curing equipment, UV curing equipment, soldering equipment, patterning equipment, etc.), and other suitable steps for forming multi-chip package99may be performed.

FIG. 6shows another suitable arrangement of multi-chip package99. As shown inFIG. 6, liquid compound120need not be used to seal package66. Instead, multi-chip package99may be sealed using a cover glass support structure such as structure220that surrounds outer wire contact members104and has a height H that extends above image sensor die16. Support structure220may be formed using plastic, ceramic, resin, or other types of dielectric material.

Cover glass222may be placed on top of support structure220. In particular, cover glass222may be sufficiently wide to be supported by structure220. Cover glass222may be supported in a way such that the bottom surface of glass222does not physically contact any circuitry contained within package99(e.g., cover glass222should not make direct contact with wires108, wires110, die16, and die18).

A layer of adhesive material224may be formed between cover glass222and support structure224to hermetically seal package99. Adhesive material224may, for example, be formed using an epoxy-based adhesive, a rubber-based adhesive, a polyimide-based adhesive, a polyolefin-based adhesive, an acrylic-based adhesive, other suitable dielectric materials, or a combination of these materials. Cavity226that is contained within cover glass222, support structure220, and substrate100may be devoid of air (i.e., a vacuum) and undesired contaminants. Cover glass222and support structure220may collectively serve as a sealing dam for cavity226and may therefore sometimes be referred to as a cavity wall or dam wall.

FIG. 7is a flow chart of illustrative steps involved in forming a multi-chip package of the type described in connection withFIG. 6. At step300, image signal processing die18may be placed on top of interposer substrate100.

At step302, image signal processing die18may be wire bonded to interposer substrate100(e.g., conductive wires108may have first ends that are soldered to wire bond pads19and second ends that are soldered to corresponding conductive members102).

At step304, an uncured adhesive layer112may be disposed on top of image signal processor die18using dispensing equipment.

While adhesive layer112is an uncured state, image sensor die16may be placed on top of adhesive layer112(step306). When image sensor die16is in its proper position, adhesive layer112may be thermally cured (as an example).

At step308, image sensor die16may be wire bonded to interposer substrate100(e.g., conductive wires110may have first ends that are soldered to wire bond pads33and second ends that are soldered to corresponding conductive members104).

At step310, a ring-shaped cavity wall220may be formed to surround stacked dies16and18and associated contact members104and102.

At step312, an uncured adhesive layer224may be disposed on top of cavity wall220using dispensing equipment. While adhesive224is in the uncured state, cover glass222may be mounted on top of cavity wall200(step314). A vacuum pump may be used during step314to create a vacuum in region226that is contained within cover glass222, cavity wall220, and substrate100. When cover glass222is in its proper position, adhesive224may be cured using UV light (as an example).

The steps ofFIG. 7are merely illustrative. If desired, other necessary equipment and/or steps for forming package99ofFIG. 6may be used.

In general, the multi-chip package configurations as described in connection withFIGS. 3 and 6are merely exemplary and can be used to house other types of multi-chip arrangements. As an example, multi-chip imaging package99may be used to house three vertically stacked chips, at least one of which is an image sensor die (see, e.g.,FIG. 8). As another example, multi-chip imaging package99may include two horizontally stacked dies, at least one of which is an image sensor die (see, e.g.,FIG. 9). As another example (see, e.g.,FIG. 10), multi-chip imaging packaging99may include vertically stacked dies (i.e., dies #1and #2) and horizontally stacked dies (i.e., dies #3and #4), where the horizontally stacked dies are vertically stacked on top of die #2. Each of the different multi-chip configurations ofFIGS. 8,9, and10may be sealed using the packaging methods as described in connection with inFIGS. 5 and 7(see, sealing barrier400).

Various embodiments have been described illustrating different multi-chip packaging arrangements that can be used for imaging systems. In one suitable embodiment, a multi-chip package may include a semiconductor package substrate, at least a first integrated circuit and a second integrated circuited mounted on top of a semiconductor substrate, and a cover glass. The second integrated circuit may be stacked on top of the first integrated circuit. The first integrated circuit may be an image signal processing integrated circuit, whereas the second integrated circuit may be an image sensor integrated circuit.

The first and second integrated circuits may be wire bonded to the substrate. In particular, the first integrated circuit may be wire bonded to the substrate through a first set of wires while the second integrated circuit may be wire bonded to the substrate through a second set of wires. Signals may be conveyed between the first and second integrated circuits via the first and second sets of wires and conductive traces formed in the substrate.

An adhesive layer may be formed between the first and second integrated circuits. The cover glass may be suspended over the second integrated circuit using a ring-shaped support structure resting on the second integrated circuit. A region within the multi-chip package that is surrounded by the cover glass, the supporting structure, and the second integrated circuit may be devoid of air. A liquid compound may be dispensed over the bond wires with the use of molding equipment to hermetically seal the multi-chip package.

In another suitable embodiment, a support structure that surrounds the first and second integrated circuits and the first and second set of wires may be formed. The support structure may have a top surface supporting the cover glass and a bottom surface resting on the substrate. The cover glass supported using this arrangement may be suspended over the second integrated circuit so that the cover glass does not make contact with the second integrated circuit and the associated bonding wires. Adhesive material may be formed between the cover glass and the top surface of the support structure. The cover glass, the supporting structure, and the substrate may surround an internally sealed cavity region within which the first and second integrated circuits are contained, and wherein the internally sealed cavity region is devoid of air.

The foregoing is merely illustrative of the principles of this invention which can be practiced in other embodiments.