Active-matrix substrate and display device including the substrate wherein a bottom-gate TFT has data lines formed below the gate lines

An active-matrix substrate includes: a base substrate; source lines; gate lines; thin-film transistors; and pixel electrodes. Each transistor is a bottom-gate thin-film transistor. The source lines are arranged under the gate lines with a first interlayer insulating film interposed and are electrically connected to the respective source electrodes of their associated thin-film transistors through contact holes cut through the first interlayer insulating film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an active-matrix substrate for use in liquid crystal TVs, liquid crystal monitors, notebook PCs and so on. The present invention also relates to a display device including such an active-matrix substrate.

2. Description of the Related Art

A liquid crystal display (LCD) is a display device with significantly reduced thickness and power dissipation, and has found a broad variety of applications in various fields. Among other things, an active-matrix-addressed LCD, including a switching element such as a thin-film transistor (TFT) for each pixel, has such high contrast ratio, excellent response characteristic and high performance as to be applied to TVs, monitors, notebook PCs, and so on. And the LCD market has been expanding faster and faster year after year.

On an active-matrix substrate for use to make such an active-matrix-addressed LCD, provided are a plurality of gate lines, a plurality of source lines that cross the gate lines with an insulating film interposed between them, and thin-film transistors, each of which is arranged near the intersection between its associated pair of gate and source lines for the purpose of switching its associated pixel.

The capacitance produced in each gate line-source line intersection (which is usually called a “parasitic capacitance”) may cause some deterioration in display quality. That is why such a parasitic capacitance preferably has as small a capacitance value as possible.

For that purpose, Japanese Patent Application Laid-Open Publication No. 5-61069 discloses a technique of reducing the parasitic capacitance to be produced in each gate line-source line intersection by decreasing the widths of the gate lines and source lines in those intersections and thereby decreasing the area of the intersections.

However, if the line widths were decreased albeit locally, then the resistance of those lines would increase to possibly produce rounded signal waveforms. Also, if the line widths were decreased, then the chances of line snapping would increase. For that reason, the decreased line width usually needs be at least about 50% of the original width. That is why the parasitic capacitance in the intersections cannot be reduced beyond a certain limit according to the technique disclosed in Japanese Patent Application Laid-Open Publication No. 5-61069. However, the sizes and definitions of LCDs in high demand have been on a steep rise recently. In those big and high-definition LCDs, the line widths are broadened to reduce the wiring resistance, and the lines cross each other in an increased number of intersections. As a result, increased parasitic capacitance is produced in those intersections. Consequently, the rounding of the signal waveforms becomes even more significant.

Another technique of reducing the capacitance to be produced in the gate line-source line intersection may be to thicken the insulating film that covers the gate lines. However, if a portion of the insulating film that covers the gate line function as a gate insulating film as in a bottom-gate TFT, the thickened insulating film would decrease the drivability of the TFT.

SUMMARY OF THE INVENTION

In order to overcome the problems described above, an object of the present invention is to provide an active-matrix substrate that can reduce the capacitance produced in the intersections between the gate lines and source lines without increasing the wiring resistance or decreasing the drivability of switching elements, and also provide a display device including such an active-matrix substrate.

An active-matrix substrate according to a preferred embodiment of the present invention preferably includes: a base substrate; a plurality of source lines provided on the base substrate; a plurality of gate lines, which are arranged so as to cross the source lines; a plurality of thin-film transistors, which have been formed on the base substrate and each of which operates in response to a signal that has been supplied to an associated one of the gate lines; and a plurality of pixel electrodes, each of which is electrically connectible to an associated one of the source lines by way of an associated one of the thin-film transistors. Each said thin-film transistor is a bottom-gate thin-film transistor, which includes a gate electrode that is electrically connected to an associated one of the gate lines, a gate insulating film that coats the gate electrode, a semiconductor layer that is provided over the gate electrode with the gate insulating film interposed, and source/drain electrodes that have been formed on the semiconductor layer. The source lines are arranged under the gate lines with a first interlayer insulating film interposed and are electrically connected to the respective source electrodes of their associated thin-film transistors through contact holes that have been cut through the first interlayer insulating film.

In one preferred embodiment of the present invention, the active-matrix substrate preferably further includes: a first conductive member, which has been formed by patterning the same conductive film as the gate lines; and a second conductive member, which has been formed by patterning the same conductive film as the pixel electrodes. Each of the source lines is preferably electrically connected to the source electrodes through the first and second conductive members.

In this particular preferred embodiment, the first conductive member is preferably in contact with the source line in the contact holes that have been cut through the first interlayer insulating film.

In a specific preferred embodiment, the active-matrix substrate preferably further includes a second interlayer insulating film, which is provided so as to cover the thin-film transistors. The second conductive member is preferably in contact with the first conductive member in contact holes that have been cut through the second interlayer insulating film.

More particularly, the second conductive member is preferably in contact with the source electrodes of the thin-film transistors in the contact holes that have been cut through the second interlayer insulating film.

In another preferred embodiment, the first interlayer insulating film preferably has a greater thickness and a lower dielectric constant than the gate insulating film.

In still another preferred embodiment, the first interlayer insulating film preferably has a thickness of 1.0 μm to 4.0 μm.

In yet another preferred embodiment, the first interlayer insulating film preferably has a dielectric constant of 4.0 or less.

In yet another preferred embodiment, the first interlayer insulating film is preferably made of an insulator including an organic ingredient.

In a specific preferred embodiment, the first interlayer insulating film may be made of a spin-on-glass (SOG) material, of which the skeleton is an Si—O—C bond.

In an alternative preferred embodiment, the first interlayer insulating film may be made of a spin-on-glass (SOG) material, of which the skeleton is an Si—C bond.

In another alternative preferred embodiment, the first interlayer insulating film may be made of a spin-on-glass (SOG) material including a filler made of silica.

In yet another preferred embodiment, the semiconductor layer is preferably made of amorphous silicon.

In yet another preferred embodiment, the active-matrix substrate preferably includes a plurality of pixel regions, which are arranged in matrix and in each of which an associated one of the pixel electrodes is provided.

In that case, the active-matrix substrate preferably includes: a display area, which is defined by the pixel regions; and a non-display area, which is located around the display area and in which a plurality of terminals are provided to receive signals for driving the pixel regions. The first interlayer insulating film is preferably substantially non-existent in the non-display area.

In yet another preferred embodiment, the active-matrix substrate may further include a shield electrode, which is provided so as to extend substantially parallel to the source lines.

In this particular preferred embodiment, the shield electrode is preferably electrically connected to an associated one of the gate lines.

In an alternative preferred embodiment, the active-matrix substrate preferably further includes a plurality of storage capacitor lines, which are arranged on the base substrate, and the shield electrode is preferably electrically connected to an associated one of the storage capacitor lines.

In yet another preferred embodiment, the shield electrode is preferably arranged so as to overlap with the edge of an associated one of the pixel electrodes.

A display device according to a preferred embodiment of the present invention preferably includes: an active-matrix substrate according to any of the preferred embodiments of the present invention described above; and a display medium layer arranged on the active-matrix substrate, whereby the objects mentioned above are achieved.

In one preferred embodiment of the present invention, the display device preferably further includes a counter substrate, which faces the active-matrix substrate through the display medium layer, and the display medium layer is preferably a liquid crystal layer.

According to a preferred embodiment of the present invention, source lines are provided under gate lines with a first interlayer insulating film interposed between them and are electrically connected to the source electrodes of thin-film transistors through contact holes that have been cut through the first interlayer insulating film. Thus, in an active-matrix substrate including thin-film transistors of a bottom-gate type, the capacitance produced in the intersections between the gate lines and source lines can be reduced without increasing the wiring resistance or decreasing the drivability of the thin-film transistors.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the present invention is in no way limited to the following specific preferred embodiments.

FIGS. 1 and 2illustrate an LCD100according to a first specific preferred embodiment of the present invention.FIG. 1is a plan view schematically illustrating one pixel region of the LCD100.FIG. 2is a cross-sectional view of the LCD100as viewed on the plane II-II shown inFIG. 1.

The LCD100includes an active-matrix substrate100a(which will be referred to herein as a “TFT substrate100a”), a counter substrate100b(which will be sometimes referred to herein as a “color filter substrate100b”) that faces the TFT substrate100a, and a liquid crystal layer60interposed between the two substrates100aand100b.

The TFT substrate100apreferably includes a transparent insulating substrate (e.g., a glass substrate)10, a plurality of source lines11arranged on the substrate10, a first interlayer insulating film12provided so as to cover the source lines11, and a plurality of gate lines13, which are provided on the first interlayer insulating film12so as to cross the source lines11.

In each pixel region of the TFT substrate100a, provided are a thin-film transistor (TFT)14, which operates in response to a signal supplied to its associated gate line13, and a pixel electrode15, which is electrically connectible to its associated source line11by way of the TFT14.

The counter substrate100bpreferably includes a transparent insulating substrate (e.g., a glass substrate)50and a counter electrode51, which has been formed on the substrate50so as to face the pixel electrodes15. Typically, the counter substrate100bfurther includes color filters.

The liquid crystal layer60preferably changes its orientation states in response to the voltage applied between the pixel electrodes15and the counter electrode51and modulates the light passing through itself, thereby conducting a display operation. The liquid crystal layer60may be of any of various display modes. For example, a twisted nematic (TN) mode liquid crystal layer that utilizes its optical rotatory property or an electrically controlled birefringence (ECB) mode liquid crystal layer that utilizes its birefringence property may be used. Among a number of ECB modes, vertically aligned (VA) mode contributes to achieving a high contrast ratio. A VA mode liquid crystal layer is typically obtained by sandwiching a liquid crystal layer, including a liquid crystal material with negative dielectric anisotropy, between two vertical alignment layers.

Hereinafter, the configuration of the TFT substrate100awill be described more fully with reference toFIGS. 3A,3B and3C, too, which are cross-sectional views of the TFT substrate100aas respectively viewed on the planes IIIa-IIIa, IIIb-IIIb and IIIc-IIIc shown inFIG. 1.

As shown inFIG. 3A, the TFT14of the TFT substrate100ais preferably an amorphous silicon TFT of bottom gate type (which is also called an “inverse stagger type”) including: a gate electrode14G that is electrically connected to its associated gate line13; a gate insulating film16that covers the gate electrode14G; a semiconductor layer (i.e., an intrinsic semiconductor layer)17that has been formed over the gate electrode14G with the gate insulating film16interposed between them; and source/drain electrodes14S and14D that have been formed on the semiconductor layer17.

The source/drain regions of the semiconductor layer17are preferably electrically connected to the source/drain electrodes14S and14D by way of a doped semiconductor layer18that functions as a contact layer. Another region of the semiconductor layer17between the source/drain regions functions as a channel region, on which no doped semiconductor layer18is present.

Also, as shown inFIG. 3B, the TFT substrate100afurther includes a plurality of storage capacitor lines20, which are arranged over the substrate10with the first interlayer insulating film12interposed between them, and a plurality of storage capacitor electrodes21, which face those storage capacitor lines20with the gate insulating film16interposed between them. A so-called “Cs on Com structure” is adopted for this TFT substrate100a. The storage capacitor lines20have been formed by patterning the same conductive film as that of the gate lines13and gate electrodes14G. The storage capacitor electrodes21have been formed by patterning the same conductive film as that of the source/drain electrodes14S and14D.

The second interlayer insulating film19has been formed so as to cover the TFT14. And the pixel electrode15is located on the second interlayer insulating film19. As shown inFIGS. 1 and 2, the pixel electrode15is in contact with, and electrically connected to, the drain electrode14D of the TFT14through a contact hole19′ that has been cut through the second interlayer insulating film19over the drain electrode14D. On the other hand, the storage capacitor electrode21is in contact with, and electrically connected to, the pixel electrode15through another contact hole19′ that has been cut through the second interlayer insulating film19over the storage capacitor electrode21as shown inFIG. 3B.

In the TFT substrate100aof this preferred embodiment, the source line11is located under the gate line13with the first interlayer insulating film12interposed between them as shown inFIG. 3C. Also, as shown inFIGS. 2 and 3A, the source line11is electrically connected to the source electrode14S of its associated TFT14by way of a contact hole12′ that has been cut through the first interlayer insulating film12. More specifically, the source line11is in contact with the source electrode14S of the TFT14within the contact hole12′ of the first interlayer insulating film12and a contact hole16′ that has been cut through the gate insulating film16, and thereby electrically connected to the TFT14.

Hereinafter, the structure of a conventional TFT substrate700a, including a bottom gate TFT, will be described with reference toFIGS. 16A and 16B.FIG. 16Ais a cross-sectional view illustrating the TFT714and surrounding portions of the TFT substrate700a(corresponding toFIG. 3A).FIG. 16Bis a cross-sectional view schematically illustrating an intersection between a source line711and a gate line713(corresponding toFIG. 3C). In the conventional TFT substrate700a, the source line711is located over the gate line713with a gate insulating film716interposed between them. In many cases, the source line711is formed by patterning the same conductive film as that of the source/drain electrodes714S and714D of the TFT714.

In contrast, according to this preferred embodiment, the source line11is located under the gate line13with the first interlayer insulating film12interposed between them as shown inFIG. 3C. The first interlayer insulating film12does not function as a gate insulating film or a dielectric film for a storage capacitor. Accordingly, even if the first interlayer insulating film12were thickened or made of a material with a low dielectric constant, the drivability or storage capacitance value of the TFT14would not decrease. Consequently, the capacitance to be produced in the intersection between the gate line13and source line11can be reduced without decreasing the drivability or storage capacitance value of the TFT14. In addition, since the first interlayer insulating film12is interposed between the source line11and the pixel electrode15and between the source line11and the counter electrode51, the capacitance produced between the source line11and the pixel electrode15and the capacitance produced between the source line11and the counter electrode51can also be reduced.

To sufficiently reduce the capacitance produced in the intersection between the gate line13and the source line11, the first interlayer insulating film12is preferably thicker, and preferably has a lower dielectric constant, than the gate insulating film16.

The gate insulating film16typically has a thickness of about 0.2 μm to about 0.4 μm and a dielectric constant of about 5.0 to about 8.0. Meanwhile, the first interlayer insulating film12preferably has a thickness of 1.0 μm to 4.0 μm and a dielectric constant of 4.0 or less.

Also, the gate insulating film16is typically made of an inorganic insulator such as SiNxor SiOx. On the other hand, the first interlayer insulating film12is preferably made of an insulator including an organic ingredient. As the material of the first interlayer insulating film12, a spin-on-glass material including an organic ingredient (i.e., a so-called “organic SOG material”) can be used effectively. Among other things, an SOG material of which the skeleton is an Si—O—C bond and an SOG material of which the skeleton is an Si—C bond are particularly preferred.

The SOG material is a material that can form a glass film (i.e., a silica based coating) by a coating technique such as spin coating. The organic SOG material has a low dielectric constant and can be made into a thick film easily. That is why by using an organic SOG material, the dielectric constant of the first interlayer insulating film12can be easily decreased and the thickness thereof can be easily increased.

As the SOG material having an Si—O—C bond as its skeleton, the material disclosed in Japanese Patent Application Laid-Open Publications Nos. 2001-98224 and 6-240455 and DD1100 produced by Dow Corning Toray Co., Ltd. and disclosed in Proceedings of IDW′ 03, p. 617 may be used. As the SOG material having an Si—C bond as its skeleton, the material disclosed in Japanese Patent Application Laid-Open Publication No. 10-102003 may be used, for example.

Hereinafter, a method of fabricating the TFT substrate100awill be described with reference toFIGS. 4A through 4I.

First, as shown inFIG. 4A, a molybdenum (Mo) film, an aluminum (Al) film and another molybdenum (Mo) film are stacked in this order by a sputtering process on an insulating substrate10of glass, for example, and the stack is patterned by a photolithographic process, thereby forming a source line11. In this preferred embodiment, the thicknesses of the Mo, Al and Mo films are 150 nm, 500 nm and 50 nm in the descending order.

Next, as shown inFIG. 4B, the substrate10is coated with an organic SOG material by a spin coating process and then pre-baked and post-baked, thereby forming a first interlayer insulating film12. Thereafter, a portion of the first interlayer insulating film12, overlapping with the source line11, is removed by a photolithographic process, thereby cutting a contact hole12′. In this preferred embodiment, an organic SOG material is applied to a thickness of 1.5 μm, pre-baked at 150° C. for five minutes by a hot plate, and then post-baked at 350° C. for an hour by an oven, thereby forming a first interlayer insulating film12with a dielectric constant of 2.5. In etching the first interlayer insulating film12, a dry etching process is carried out by using a mixture of carbon fluoride (CF4) and oxygen (O2).

Next, as shown inFIG. 4C, an Mo film, an Al film and another Mo film are stacked in this order by a sputtering process and then the stack is patterned by a photolithographic process, thereby forming a gate electrode14G. In this process step, gate lines13and storage capacitor lines20(neither is shown inFIG. 4C) are formed at the same time. In this preferred embodiment, the thicknesses of the Mo, Al and Mo films are 150 nm, 200 nm and 50 nm in the descending order.

Subsequently, as shown inFIG. 4D, an SiNxfilm, an amorphous silicon (a-Si) film and an n+-amorphous silicon (n+a-Si) film are deposited continuously by a CVD process, and then the a-Si film and the n+a-Si film are patterned by a photolithographic process (i.e., portions of the n+a-Si and a-Si films are dry-etched away), thereby forming an island-like semiconductor structure (i.e., semiconductor active regions) consisting of a gate insulating film16, an intrinsic semiconductor layer17and a doped semiconductor layer18. In this preferred embodiment, a gate insulating film16with a thickness of 0.4 μm and a dielectric constant of 7.0, an intrinsic semiconductor layer17with a thickness of about 50 nm to about 200 nm, and a doped semiconductor layer18with a thickness of about 40 nm are formed.

Thereafter, as shown inFIG. 4E, a portion of the gate insulating film16is removed by a photolithographic process from inside of the contact hole12′ of the first interlayer insulating film12, thereby cutting a contact hole16′ through the gate insulating film16.

Subsequently, as shown inFIG. 4F, an Mo film is deposited by a sputtering process and then patterned by a photolithographic process, thereby forming a source electrode14S, a drain electrode14D and a storage capacitor electrode21(not shown inFIG. 4F), each having a thickness of 150 nm. The Mo film is preferably patterned by a wet etching process. As described above, in this preferred embodiment, the source/drain electrodes14S,14D and storage capacitor electrode21are formed on a different layer from the source lines11(i.e., these members are formed by patterning two different conductive films). For that reason, the material of the source/drain electrodes14S,14D and so on does not have to have as low resistance as that of the source lines11. Accordingly, the source/drain electrodes14S,14D and so on may be made of Mo as in this preferred embodiment, a refractory metal such as titanium (Ti) or tantalum (Ta), or ITO. As a result, the manufacturing process can be shortened and the material costs can be cut down.

Next, as shown inFIG. 4G, a portion of the doped semiconductor layer18, which will define a channel region for the island-like semiconductor structure, is dry-etched away by using the source/drain electrodes14S and14D as an etching mask. While that portion of the doped semiconductor layer18is being removed, the surface of the intrinsic semiconductor layer17is also lightly etched.

Thereafter, as shown inFIG. 4H, SiNxis deposited by a CVD process, thereby forming an interlayer insulating film19to a thickness of about 150 nm to about 700 nm over the entire surface of the substrate10. And then a contact hole19′ (not shown inFIG. 4H) is cut by a photolithographic process. In this process step, the interlayer insulating film19may be a film of an organic insulator (e.g., a photosensitive resin material) with a thickness of about 1.0 μm to about 3.0 μm. Alternatively, the interlayer insulating film19may also be a stack of a film of SiNxor any other inorganic insulator and a film of such an organic insulator.

Finally, as shown inFIG. 4I, an ITO film is deposited to a thickness of 100 nm by a sputtering process and then patterned by a photolithographic process (e.g., wet-etched), thereby forming a pixel electrode15. The pixel electrode15does not have to be made of a transparent conductive material such as ITO but may also be made of Al or any other metallic material with optical reflectivity.

In this manner, the TFT substrate100ais completed. According to the method of this preferred embodiment, the first interlayer insulating film12has a thickness of 1.5 μm and a dielectric constant of 2.5. Thus, the capacitance to be produced in every intersection between the gate lines13and the source lines11has a capacitance value of 1.48×10−5pF per μm2. Meanwhile, in a configuration in which a gate insulating film (with a thickness of 0.4 μm and a dielectric constant of 7.0 just like the counterpart of this preferred embodiment) is located between the gate lines and the source lines as in a conventional active-matrix substrate, the capacitance value per unit area will be 1.55×10−4pF/μm2. Consequently, by adopting the configuration of this preferred embodiment, the value of the capacitance produced in every intersection can be reduced by more than 90%. In addition, since the first interlayer insulating film12is also provided between the source lines11and the pixel electrodes15, the capacitance produced in the overlap portion between the source lines11and the pixel electrodes15can be reduced significantly, too. Furthermore, since the first interlayer insulating film12is also provided between the source lines11and the counter electrode51, the capacitance produced between them can be reduced as well.

An LCD200according to a second specific preferred embodiment of the present invention will be described with reference toFIG. 5andFIGS. 6A through 6C. The following description of the second preferred embodiment will be focused on the difference between the LCD100of the first preferred embodiment and the LCD200of the second preferred embodiment.

In the TFT substrate200aof the LCD200, the source line11and the source electrode14S are connected together differently from the TFT substrate100aof the first preferred embodiment. In the TFT substrate100a, the source electrode14S is directly in contact with the source line11within the contact hole12′ of the first interlayer insulating film12, thereby electrically connecting the source line11and the source electrode14S together as shown inFIG. 3A.

On the other hand, the TFT substrate200afurther includes a first conductive member13aformed by patterning the same conductive film as the gate lines13and a second conductive member15aformed by patterning the same conductive film as the pixel electrodes15as shown inFIG. 6A. The source line11of the TFT substrate200ais electrically connected to the source electrode14S by way of the first and second conductive members13aand15a.

More specifically, the first conductive member13amakes a contact with the source line11within the contact hole12′ of the first interlayer insulating film12and the second conductive member15amakes a contact with the first conductive member13aand the source electrode14S within the contact hole19′ of the second interlayer insulating film19. As a result, the source line11is electrically connected to the source electrode14S.

In the TFT substrate200aof this second preferred embodiment, the source lines11are also located under the gate lines13with the first interlayer insulating film12interposed between them as shown inFIG. 6C. Consequently, the capacitance produced in every intersection between the gate lines13and source lines11, the capacitance produced between each source line11and its associated pixel electrode15, and the capacitance produced between the source lines11and the counter electrode51can all be reduced without decreasing the drivability of the TFTs14or the capacitance value of the storage capacitors.

Furthermore, in this preferred embodiment, the source lines11are electrically connected to the source electrodes by way of the first conductive member13athat has been formed by patterning the same conductive film as the gate lines13and the second conductive member15athat has been formed by patterning the same conductive film as the pixel electrodes15. By adopting such a configuration, a number of advantages are achieved in manufacturing process as will be described later.

Hereinafter, a method for fabricating the TFT substrate200awill be described with reference toFIGS. 7A through 7H.

First, as shown inFIG. 7A, a conductive film is deposited by a sputtering process on an insulating substrate10of glass, for example, and then patterned by a photolithographic process, thereby forming a source line11.

Next, as shown inFIG. 7B, the substrate10is coated with an organic SOG material by a spin coating process and then pre-baked and post-baked, thereby forming a first interlayer insulating film12. Thereafter, a portion of the first interlayer insulating film12, overlapping with the source line11, is removed by a photolithographic process, thereby cutting a contact hole12′.

Next, as shown inFIG. 7C, another conductive film is deposited by a sputtering process and then patterned by a photolithographic process, thereby forming a gate electrode14G and a first conductive member13a. In this process step, the first conductive member13ais formed so as to make a contact with the source line11within the contact hole12′ that has been cut through the first interlayer insulating film12. Also, in this process step, gate lines13and storage capacitor lines20(neither is shown inFIG. 7C) are formed at the same time.

Subsequently, as shown inFIG. 7D, an inorganic insulating film, an intrinsic semiconductor film and a doped semiconductor film are deposited continuously by a CVD process, and then the intrinsic semiconductor film and the doped semiconductor film are patterned by a photolithographic process, thereby forming an island-like semiconductor structure consisting of a gate insulating film16, an intrinsic semiconductor layer17and a doped semiconductor layer18.

Thereafter, as shown inFIG. 7E, a conductive film is deposited by a sputtering process and then patterned by a photolithographic process, thereby forming a source electrode14S, a drain electrode14D and a storage capacitor electrode21(not shown inFIG. 7E).

Next, as shown inFIG. 7F, a portion of the doped semiconductor layer18, which will define a channel region for the island-like semiconductor structure, is dry-etched away by using the source/drain electrodes14S and14D as an etching mask. While that portion of the doped semiconductor layer18is being removed, the surface of the intrinsic semiconductor layer17is also lightly etched.

Thereafter, as shown inFIG. 7G, a second interlayer insulating film19is deposited by a CVD process over the entire surface of the substrate10. And then a contact hole19′ is cut by removing a portion of the second interlayer insulating film19by a photolithographic process. In this process step, a portion of the gate insulating film16(i.e., a portion overlapping with the source line11) is also removed to make a contact hole16′ through the gate insulating film16, too.

Finally, as shown inFIG. 7H, an ITO film is deposited by a sputtering process and then patterned by a photolithographic process, thereby forming a pixel electrode15and a second conductive member15a. In this process step, the second conductive member15ais formed so as to make a contact with both the first conductive member13aand the source electrode14S within the contact hole19′ of the second interlayer insulating film19. In this manner, the TFT substrate200ais completed.

This preferred embodiment adopts an arrangement in which the source line11is electrically connected to the source electrode14S by way of the first and second conductive members13aand15a. Thus, a contact hole can be made through both the second interlayer insulating film19and gate insulating film16at the same time as described above. That is to say, the process step of cutting a contact hole through only the gate insulating film16(i.e., the process step shown inFIG. 4E) can be omitted. As a result, the number of photomasks used, and eventually the overall manufacturing cost, can be reduced.

It should be noted that a film made of an organic SOG material is usually less resistible to mechanical and thermal stresses, and more likely to crack, than an inorganic film made of SiNx, for example. That is why if the first interlayer insulating film12is made of an organic SOG material, the first interlayer insulating film12is preferably substantially non-existent in the non-display area2as shown inFIG. 8to minimize cracking.

The non-display area2is located around a display area1, which is defined by a plurality of pixel regions that are arranged in matrix, and is sometimes called a “picture frame area”. In the non-display area2, provided are a plurality of terminals at which signals for driving the pixel regions are received. And gate drivers30and source drivers40are connected to those terminals. Stress is easily placed on the non-display area2in the process step of mounting or dicing. Thus, the cracking phenomenon can be minimized by making the first interlayer insulating film12non-existent in the non-display area2.

Also, the thicker the first interlayer insulating film12and the bigger the size of the substrate, the more easily such cracking occurs. The present inventors carried out an intensive research on what effects the material of the first interlayer insulating film12had on such cracking phenomenon. As a result, the present inventors discovered that by using an SOG material including a filler made of silica (i.e., a silica filler), the cracking phenomenon could be minimized and the first interlayer insulating film12could be thickened even in a big active-matrix substrate.

FIG. 9schematically illustrates a cross-sectional structure of the first interlayer insulating film12made of an organic SOG material including a silica filler. As shown inFIG. 9, the first interlayer insulating film12has a structure in which silica filler particles12bare dispersed in a matrix12amade of an organic SOG material. By adopting such a structure, the silica filler particles12brelax the stress and minimize the cracking phenomenon, thus making it easier to thicken the first interlayer insulating film12even on a big substrate. The silica filler12btypically has a particle size of 10 nm to 30 nm and the ratio of the silica filler12bto the overall first interlayer insulating film12is typically 20 vol % to 80 vol %. As an organic SOG material including a silica filler, LNT-025 produced by Catalysts and Chemicals Industries Co., Ltd. may be used, for example.

The present inventors conducted a crackability test on an organic SOG film with a silica filler and an organic SOG film with no silica fillers. The results are shown in the following Table 1. As a sample substrate, a glass substrate (Corning 1737) with dimensions of 360 mm×465 mm was used. The crackability was evaluated following the procedure shown inFIG. 10. Specifically, an SOG material was applied onto the sample substrate, pre-baked at 180° C. for four minutes, and then post-baked at 350° C. for an hour within a nitrogen atmosphere, thereby forming an SOG film. Then, the substrate on which the SOG film had been deposited was subjected to a heat cycle test, in which the substrate was kept heated at 350° C. for an hour within the nitrogen atmosphere and then rapidly cooled.

As can be seen from Table 1, if no filler was added, the cracking phenomenon sometimes occurred (as indicated by the crosses “×”) when the thickness was 1.5 μm or more. On the other hand, if a filler was added, the cracking phenomenon still could be checked even when the thickness was increased to 3.0 μm.

FIG. 11andFIGS. 12A through 12Dschematically illustrate an LCD300according to a third specific preferred embodiment of the present invention.

As shown inFIG. 11andFIGS. 12A through 12C, the TFT substrate300aof the LCD300of this preferred embodiment has almost the same configuration as the TFT substrate200aof the LCD200of the second preferred embodiment described above.

However, unlike the TFT substrate200aof the LCD200, the TFT substrate300aof the LCD300of this preferred embodiment includes a plurality of shield electrodes23, extending substantially parallel to the source lines11, as shown inFIGS. 11 and 12D.

In this preferred embodiment, the shield electrodes23are formed by patterning the same conductive film as the gate lines13. These shield electrodes23are connected to the storage capacitor line20and are supplied with a constant potential. Hereinafter, problems that may happen without the shield electrodes23and advantages achieved by providing the shield electrodes23will be described.

FIG. 13shows simulated electric fields (electric flux lines) to be created when a voltage is applied to an LCD including a conventional active-matrix substrate. The cell parameters used to make this simulation (i.e., the thicknesses, widths, dielectric constants, and applied potentials of respective members) are as shown inFIG. 13. As shown inFIG. 13, the electric flux lines are formed so as to connect not only the pixel electrodes to the counter electrode but also the pixel electrodes to the source lines as well. That is to say, an electrostatic capacitance happens to be created between the pixel electrodes and the source lines. As a result, the potential at the pixel electrodes, which should be kept constant throughout a frame, varies as being affected by a variation in potential on the source lines. A similar problem may also happen even if the source lines are provided under the gate lines with the first interlayer insulating film interposed between them as shown inFIG. 14.

On the other hand, if the shield electrodes23are provided, then the electric flux lines, emitted from the pixel electrodes15toward the source lines13, can be guided toward the shield electrodes23as shown inFIG. 15, thus preventing a capacitance from being produced between the pixel electrodes15and the source lines13. As a result, it is possible to avoid an unwanted situation where the potential at the pixel electrodes15varies as being affected by the potential on the source lines13. That is to say, the shield electrodes23have the function of shielding the pixel electrodes15from an electric field generated by the source lines11.

It should be noted that even if such shield electrodes are provided for the conventional active-matrix substrate shown inFIG. 13, the influence of the potential on the source lines11can also be reduced to a certain degree. However, the effects of the shield electrodes are achieved most significantly in an arrangement in which the source lines11are provided under the gate lines13with the first interlayer insulating film12interposed between them as in the TFT substrate300aof this preferred embodiment. Contrary to the conventional active-matrix substrate, the source lines11are located under the gate lines13. Thus, the shield electrodes23(which are typically made of the same conductive film as the gate lines13) can be easily provided over the source lines11(i.e., between the source lines11and the pixel electrodes15). As a result, high shielding effects are easily achieved as shown inFIG. 15.

To guide more electric flux lines from the pixel electrodes15toward the shield electrodes23and to reduce the variation in the potential at the pixel electrodes15more effectively, an edge of the shield electrode23, facing the source line11, is preferably located closer to the source line11than the associated edge of the pixel electrode15as shown inFIG. 12D.

Also, in an LCD, light sometimes leaks through the gap between the gate line13and the pixel electrode15. Thus, this gap is preferably shielded from light by providing an opaque member (which is also called a “black matrix”) for the counter substrate. However, such an opaque member on the counter substrate is a little oversized in order to bond the substrates together as accurately as possible. That is why the opaque member may possibly decrease the aperture ratio and transmittance of the LCD. Nevertheless, if the shield electrode23(which is typically made of an opaque material and may function as an opaque layer) is provided such that it overlaps with the edge of the pixel electrode15as shown inFIG. 12D, then the opaque member on the counter substrate may have a narrower width. As a result, the aperture ratio and transmittance of the LCD can be increased.

Various preferred embodiments of the present invention described above provide an active-matrix substrate that can reduce the capacitance produced in the intersections between the gate lines and source lines without increasing the wiring resistance or decreasing the drivability of switching elements, and also provide a display device including such an active-matrix substrate.

This non-provisional application claims priority under 35 USC § 119(a) on Patent Application No. 2004-254876 filed in Japan on Sep. 1, 2004, the entire contents of which are hereby incorporated by reference.