ELECTRONIC DEVICE MANUFACTURING METHOD

The present description concerns a method of manufacturing a device comprising a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, the method comprising: a. the forming of first insulating trenches separating from one another the substrate regions of a same cell row, and b. the forming of second trenches separating from one another the regions of a same cell column, the second trenches having a height greater than the height of the first trenches, step a. comprising the independent forming of a lower portion and of an upper portion of each first trench, the forming of the upper portions comprising the deposition of a first insulating layer, the etching of the portions of the first insulating layer which are not located on the upper portions.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the priority benefit of French patent application number FR2205853, filed on Jun. 6, 2022, entitled “Procédé de fabrication de dispositifs électroniques,” which is hereby incorporated by reference to the maximum extent allowable by law.

BACKGROUND

Technical Field

The present disclosure generally concerns methods of manufacturing electronic devices, and more particularly devices comprising memory cells.

Description of the Related Art

Electronic devices comprising memories for example comprise arrays of memory cells. Memory cell arrays comprise rows and columns of memory cells, the cells of a same row being coupled by a bit line and the cells of a same column being coupled by a word line.

BRIEF SUMMARY

An embodiment overcomes all or part of the disadvantages of known electronic device manufacturing methods.

An embodiment provides a method of manufacturing a device comprising a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, each memory cell being located on a region of a substrate, the method comprising the following steps:

the forming of first insulating trenches separating from one another the substrate regions of a same cell row, andthe forming of second trenches separating from one another the substrate regions of a same cell column, the second trenches having a height greater than the height of the first trenches,step a. comprising the following steps:a1. the forming of a lower portion of each first trench, anda2. the forming of an upper portion of each first trench,the forming of the upper portions comprising the deposition of a first insulating layer and the etching of the portions of the first insulating layer which are not located on the upper portions.

According to an embodiment, the substrate is of substrate-on-insulator type in the second portion of the device.

According to an embodiment, the method comprises, before steps a. and b., a step c. of removal, in the first portion, of the upper semiconductor layer of a substrate of substrate-on-semiconductor type and the growth of the insulating material of the intermediate insulating layer of the substrate of substrate-on-semiconductor type along a height at least equal to the height of the upper semiconductor layer of the substrate, the intermediate layer being made of a first insulating material.

According to an embodiment, the method comprises, before steps a. and b. and after step c., step d. of forming of the first layer on the first and second portions.

According to an embodiment, step a2. comprises the forming of first openings in the first layer in front of the locations of the regions, and step a1. comprises the etching of the intermediate layer through the first openings, step a2. comprising, after step a1., the removal of the portions of the first layer located in the second portion, the first layer being made of a second insulating material.

According to an embodiment, step a2. comprises the removal of the portions of the first layer located outside of the first portion and the removal of the portions of the intermediate layer and of the first layer located at the locations of the first trenches, the first layer being made of the first insulating material.

According to an embodiment, the method comprises, after step a. and before step b., a step e. of growth of the lower layer of the substrate of semiconductor-on-insulator type at the locations of the regions.

According to an embodiment, the method comprises, after step e., a step f. of forming of a stack comprising a second layer made of the first material and a third layer made of the second material on the first and second portions.

According to an embodiment, the first and second materials are selectively etchable with respect to each other.

According to an embodiment, the first material is silicon oxide and the second is silicon nitride.

According to an embodiment, step b. comprises, after step f., the forming of second openings in the third layer of the stack in front of the locations of the second trenches, the forming of cavities through the second openings, and the forming, on the first and second portions, of a fourth layer made of the first material sufficiently thick to fill the cavities.

According to an embodiment, the method comprises, after step b., a step g. of removal by chemical mechanical polishing of the portions of the fourth layer located above the third layer of the stack and a step h. of removal of the third layer.

According to an embodiment, the method comprises, after step h., steps of doping of the substrate.

According to an embodiment, the method comprises the deposition of silicon strips on the upper portions of the first trenches.

Another embodiment provides a device comprising a first portion having an array of memory cells arranged therein and a second portion having transistors arranged therein, each memory cell being located on a region of a substrate, the device comprising first insulating trenches separating from one another the substrate regions of a same cell row, and second trenches separating from one another the substrate regions of a same cell column, the second trenches having a height greater than the height of the first trenches, wherein the upper surfaces of the first and second trenches are separated by a distance shorter than 10 nm.

Another embodiment provides a device comprising a first portion having an array of memory cells arranged therein and a second portion having transistors arranged therein, each memory cell being located on a region of a substrate, the device comprising first insulating trenches separating from one another the substrate regions of a same cell row, and second trenches separating from one another the substrate regions of a same cell column, the second trenches having a height greater than the height of the first trenches, wherein each first trench comprises a lower portion made of a first material and a lower portion made of a second material different from the first material, where the second trenches do not comprise the second material.

DETAILED DESCRIPTION

For the sake of clarity, only the steps and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail.

In the following disclosure, when reference is made to absolute positional qualifiers, such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or to relative positional qualifiers, such as the terms “above,” “below,” “upper,” “lower,” etc., or to qualifiers of orientation, such as “horizontal,” “vertical,” etc., reference is made, unless specified otherwise, to the orientation of the figures.

FIG.1schematically shows a top view of an electronic device comprising an array10of memory cells12.

Cells12are formed on a same substrate, not shown inFIG.1. Each memory cell for example comprises a via13resting on the substrate and having the rest of the cell resting thereon. The memory cells are for example phase-change memory cells. Thus, each cell comprises a layer, not shown, of phase-change material. Said layer is for example located between two metal layers, not shown, the lower layer for example resting on the via13of the cell.

Array10comprises a plurality of columns14of memory cells12and a plurality of rows16of memory cells12. Only three rows and three columns are shown inFIG.1.

The different rows16of memory cells are separated from one another by shallow insulating trenches (Shallow Trench Insulation—STI)18. Each row16of memory cells is thus separated from each neighboring row16by a trench18.

The different columns14of memory cells are separated from one another by super shallow insulating trenches (Super Shallow Trench Insulation—SSTI)20. Each column14of memory cells is thus separated from each neighboring column14by a trench20.

In other words, rows16and trenches18extend in a same direction, for example, the direction of the bit line, and are thus substantially parallel to one another. Similarly, columns14and trenches20extend in a same direction, for example, the direction of the word line, and are thus substantially parallel to one another. The direction in which trenches18extend and the direction in which trenches20extend are substantially orthogonal. In top view, that is, in the plane ofFIG.1, the direction in which trenches18extend and the direction in which trenches20extend are substantially perpendicular.

The device for example comprises a chip comprising various electronic components. Memory array10is for example located on the chip. For example, the chip having array10arranged thereon comprises the substrate, the array located on a region of the substrate, and components, for example, logic components, located in another region of the substrate. The components comprise, for example, as a majority, transistors. The transistors, and possibly other components located around the array, comprise polysilicon, for example, in the gate of the transistors. During the manufacturing of a chip, it is useful to ensure that the density of polysilicon is not too uneven. For this purpose, polysilicon lines, not shown inFIG.1, are for example placed in the memory arrays. For example, a polysilicon line is for example located on each trench20. Preferably, the polysilicon lines are not used in the device for other functions than the homogenizing of the polysilicon density. Preferably, the polysilicon lines are not electrically coupled to electronic components other than themselves.

FIG.2Ashows a cross-section view of the device ofFIG.1in the direction of a word line.FIG.2Bshows a cross-section view of the device ofFIG.1in the direction of a bit line. More precisely,FIG.2Ashows a cross-section view of the device ofFIG.1in plane A-A ofFIG.1andFIG.2Bshows a cross-section view of the device ofFIG.1in plane B-B ofFIG.1.

The device comprises a substrate22. Substrate22is a semiconductor substrate, for example, made of silicon. Substrate22for example comprises a lower doped region22aof a first conductivity type, for example, P-type doped. Substrate22for example comprises an intermediate doped region22b, of a second conductivity type, for example, P-type doped. Region22bcovers, preferably entirely, region22a.

Substrate22comprises upper regions22c. Each memory cell is located on a, preferably a single, region22c. Regions22cthus form an array corresponding to the array of memory cells. The array of regions22cthus comprises rows extending in the same direction as the rows of the array of memory cells and columns extending in the same direction as the columns of the array of memory cells. The array of regions22cthus comprises rows extending in front of the rows of the array of memory cells and columns extending in front of the columns of the array of memory cells. The regions22cof the array having regions22clocated thereon are for example doped with the first conductivity type. For example, certain regions22c, for example regions having no memory cell located thereon, are doped with the second conductivity type and are in contact with a via, to deliver a voltage to region22b.

The regions22cof a same row of the array of regions22care separated from one another by trenches20. Trenches20extend from the upper surface of regions22c, in particular from the upper surface of the neighboring regions22c, to region22b. Trenches20extend at least along the entire height of regions22c. Trenches20extend for example along part of the height of region22b.

The regions22cof a same column of the array of regions22care separated from one another by trenches18. Trenches18extend from the upper surface of regions22c, in particular from the upper surface of the neighboring regions22c, to region22a. Trenches18extend at least along the entire height of regions22band22c. Trenches18for example extend along part of the height of region22a.

Regions22care preferably each covered with a metal layer24. Layers24preferably only cover the upper surface of regions22c. Vias13each rest on a layer24. Thus, vias13are electrically coupled to regions22cby layers24. Thus, a current may be delivered to each memory cell, in particular to the via13of each cell, via the region22cand the layer24corresponding to this cell.

The device further comprises metal strips26. Strips26are for example made of titanium nitride. A strip26is located on each trench20. Strips26preferably extend along the entire length of the array, in the direction of trenches20. Thus, strips26for example extend along the entire length of trenches20.

The width of strips26is smaller than the width of trenches20. By width of strips26, there is meant the dimension of strips26in the direction from a lateral wall of a trench20to the other lateral walls, that is, in the direction of a word line.

Each strip26is covered with a polysilicon layer28. Each strip26is preferably entirely covered with layer28. Thus, strip26is entirely buried between trench20and layer28. Layers28enable to homogenize the polysilicon density in the device. In other words, layers28enable to ensure that the polysilicon density difference between the memory array and the areas comprising the transistors is not too high to allow the manufacturing of the device.

Each layer28is covered with an electrically-insulating layer30, for example made of silicon nitride. Layer30is for example covered with an electrically-insulating layer32, for example, made of silicon oxide. Vias13are for example entirely laterally surrounded with insulating layers30and32.

In known manufacturing methods, the steps of manufacturing of trenches18and20cause the forming of trenches18and20having non-coplanar upper surfaces. Thus, the strips26deposited on trenches20are not planar. Each strip26for example comprises portions26abeing located in a lower plane and portions26blocated in an upper plane. The distance D1between the lower and upper planes is for example in the range from 10 nm to 30 nm. Portions26aare for example adjacent to regions22cand portions26bare for example adjacent to trenches18. Thus, regions22care separated from one another by trench portions20having portions26aresting thereon.

As shown inFIG.2A, portions26aare close to regions22cand layers24. For example, the lower plane having portions26alocated therein is for example in the plane of layers24or in a lower plane, that is, in a plane comprising regions22c. The risk of interference between strips26and regions22cand layers24is thus significant. Indeed, the distance between each portion of insulating material located between a strip26and the neighboring regions22c, or the neighboring layers24, risks being sufficiently low to allow the forming of a current between neighboring regions22c, or the neighboring regions24, via strip26. The reading and the programming of the memory cells would then be disturbed.

FIG.3A,FIG.3B,FIG.3C,FIG.3D,FIG.3E,FIG.3F,FIG.3G,FIG.3Hshow steps, preferably successive, of a method of manufacturing an electronic device comprising memory cells.FIGS.3A to3Hcomprise:a first portion showing the steps in a portion SOI of the device comprising components, for example, logic components, formed on a portion of semiconductor-on-insulator (SOI) type of a substrate;a second portion showing the steps in a solid portion (bulk) BK of the device comprising components, for example, logic components, formed on a solid substrate portion of the substrate;a third portion A-A showing a portion A-A of the device comprising a memory array in cross-section plane A-A, that is, the plane ofFIG.2A; anda fourth portion B-B showing the portion B-B of the device comprising a memory array in cross-section plane B-B, that is, the plane ofFIG.2B. The first, second, and third portions are located on a same substrate.

During the step resulting in the structure ofFIG.3A, an etch mask34is formed on a substrate36of semiconductor-on-insulator (SOI) type in portion SOI of the substrate. Substrate36comprises a lower semiconductor layer38, for example, made of silicon, an insulating layer40, for example, made of silicon oxide, covering layer38, and an upper semiconductor layer42, for example, made of silicon. Mask34is for example made of silicon nitride. A silicon oxide layer44is for example formed on layer42before the forming of mask34. Mask34is for example thus separated from layer42by layer44.

Mask34is formed to have openings at the level of the portions of the substrate corresponding to portions BK and A-A, B-B ofFIG.3A.

Layers42and44are then etched through the openings in mask34. Thus, layers42and44are removed from the portions of the substrate corresponding to the portions BK and A-A, B-B ofFIG.3A.

Layer40then undergoes a growth step. During this step, layer40in the portions of the substrate corresponding to the portions BK, A-A, B-B ofFIG.3Agrows to reach an upper level at the upper surface level of layer44of portion SOI, for example to reach the level of the upper surface of layer34. In the example ofFIG.3A, the upper surface of layer34in portion SOI and the upper surface of layer40in portions BK, A-A, B-B are coplanar.

During the step resulting in the structure ofFIG.3B, mask34is removed. A layer46of a material capable of being selectively etched over the material of layer40is formed on the structure, that is, on layer40, in portions BK, A-A, B-B, and on layer44in portion SOT. By selectively etchable, there is meant that there exists an etch method with which the material of layer46is etched at least twice faster than the material of layer40. Layer46is for example made of silicon nitride. Preferably, the materials of layers40and46are selectively etchable with respect to each other.

During the step resulting from the structure ofFIG.3C, openings are formed in layer46so that layer46forms an etch mask.

In particular, an opening is formed in front of portion BK, that is, the portion of the substrate forming a solid substrate, and in front of the regions22cof portion A-A, B-B.

Layer40is then etched through the openings. Thus, layer40is removed from portions BK and from the locations of regions22c.

During the step resulting in the structure ofFIG.3D, layer38undergoes a growth step. More precisely, the portions of layer38exposed during the step ofFIG.3Cundergo a growth step. Thus, layer38extends, in portion BK and at the locations of regions22c, in the openings formed during the step ofFIG.3C. Preferably, layer38extends, in portion BK and at the locations of regions22c, to an upper level at the level of the upper surface of layer42. For example, layer38extends, in portion BK and at the locations of regions22c, to the level of the upper surface of layer40in portion A-A, B-B. The upper surface of layer38in portion BK and at the locations of regions22cis for example coplanar with the upper surface of layer40in portion A-A, B-B.

The portion of layer46located in portion SOI is then removed. Thus, at the end of the steps ofFIGS.3C and3D, layer46is then entirely removed, except for the portions located on the portions of the layer40of portion A-A, B-B, which correspond to the trenches20located in the memory array. This thus corresponds to a step of raising of the portions of the layer40of portion A-A, B-B which correspond to the trenches20located in the memory array. Thus, each trench20comprises a lower portion, formed by a portion of layer40, and an upper portion, formed by a portion of layer46.

During the step resulting in the structure ofFIG.3E, a stack of an insulating layer48and of an insulating layer50is formed on the structure resulting from the step ofFIG.3D.

Layer48is conformally formed on the structure. Layer48thus covers, preferably entirely, the layer44of portion SOI. More precisely, layer48thus covers, preferably entirely, the upper surface of layer44of portion SOI. Layer48covers, preferably entirely, the layer38of portion BK. More precisely, layer48covers, preferably entirely, the upper surface of the layer38of portion BK. Layer48covers, preferably entirely, the portions of layer46and layer38of portion A-A, B-B. More precisely, layer48covers, preferably entirely, the upper surface of the layer38of portion A-A, B-B, the upper surface of the layer38of portion A-A, B-B, and the upper and lateral surfaces of the portions of layer46of portion A-A, B-B.

Layer50covers, preferably entirely, layer48. The portions of layer46which have not been removed by the etching of the step ofFIG.3D, that is, the portions of layer46located on the portions of layer40forming trenches20, are separated from layer50by layer48.

Preferably, layer48is made of the same material as layer40. Layer48is for example made of silicon oxide.

Layer50is for example made of the same material as layer46. Layer50is for example made of silicon nitride. Layer50is made of a material selectively etchable over the material of layer48.

The thickness of layer50is such that the level, or plane, of the portion of the upper surface of layer50closest to layer38is separated from layer38by the level of the portion of the upper surface of layer48most distant from layer38. In other words, the level of the portion of the upper surface of layer50closest to layer38is only covered with portions of layer50.

During the step resulting in the structure ofFIG.3F, openings are formed in layer50, forming an etch mask, in front of the locations of the shallow trenches (STI). Shallow trenches may be formed in portions SOI, BK, and A-A, B-B. In particular, in portion A-A, B-B, that is, in the portion of the chip having the memory array formed therein, the shallow trenches comprise the trenches18ofFIGS.2A and2B. Shallow trenches for example all have substantially the same depth. An etch step is then performed through said openings in layer50to form cavities at the locations of trenches18.

In portion SOI, the portions of layers38,40,42,44, and48located at the locations of the shallow trenches are etched through the openings in layer50. Thus, layers40,42,44, and48are preferably entirely crossed by the cavities formed by the etching. Layer38is preferably partially crossed by the cavities formed by the etching.

In portion BK, the portions of layers38and48located at the locations of the shallow trenches are etched through the openings in layer50. Thus, layer48is preferably entirely crossed by the cavities formed by the etching. Layer38is preferably partially crossed by the cavities formed by the etching.

In portion A-A, B-B, that is, in the portion having the memory array formed therein, the portions of layers38,40,46, and48located at the locations of shallow trenches18are etched through the openings in layer50. Thus, layers40,46, and48are preferably entirely crossed by the cavities formed by the etching. Layer38is preferably partially crossed by the cavities formed by the etching.

A layer52is formed on the structure. The thickness of layer52is such that layer52fills the cavities formed at the locations of the shallow trenches and covers, preferably entirely, layer50.

Layer52is made of an electrically-insulating material, for example, of silicon oxide. Preferably, layer52is made of the same material as layer48. Preferably, layer52is made of the same material as layer40.

During the step resulting in the structure ofFIG.3G, the structure undergoes a polishing step, for example, by a chemical mechanical polishing step. The polishing method is carried out to expose, preferably, entirely, layer50.

In portion SOT, the portion of layer52located above the level of the upper surface of layer50is for example removed. The upper surface of the device in portion SOI is thus planar and comprises the upper surface of layer50laterally surrounded with the upper surface of layer52.

In portion BK, the portion of layer52located above the level of the upper surface of layer50is for example removed. The upper surface of the device in portion BK is thus planar and comprises the upper surface of layer50laterally surrounded with the upper surface of layer52.

In portion A-A, B-B, layers50and52are polished to remove all the material of layer52located above layer50. Thus, layers50and52are removed all the way to the level of the portion of layer50closest to layer38.

The portions of layer50are then removed by a method of etching of the material of layer50selective over the material of layer48and the material of layer52. Thus, the plane of the upper surface of the shallow trenches is separated from the plane of the upper surface of layer48by a height substantially corresponding to the thickness of layer50.

During the step resulting in the structure ofFIG.3H, various electronic component manufacturing steps may be carried out. In particular, semiconductor material doping steps are carried out. The layer42of portion SOI and the layer38of portion BK are for example doped to form electronic components, in particular transistors. Similarly, the layer38of portion A-A, B-B is doped to form regions22a,22b, and22c.

The doping steps for example comprise the forming and the removal of masks, for example, lithophotography masks. These steps cause the partial removal of the material of layer48and of the shallow trenches. Thus, layer48is removed during these steps. Preferably, the thickness of layer48is such that layer48is fully removed. The portions of layer46located on trenches20are not removed. Further, the height of the shallow trenches, in particular the trenches18of the memory array, is decreased by the steps of forming and of removal of the masks.

Strips26are then formed on the portions of layer46located on portions of layer40. Layer28, not shown inFIG.3H, made of polysilicon is then formed on the structure.

The presence and the holding of the portions of layer46enable to decrease the distance between portions26aand26b. Thus, the lower and upper planes, that is, portions26aand26b, are separated by a distance D2, shorter than distance D1. In other words, the upper surfaces of trenches18and20are separated by distance D2. Distance D2is for example shorter than 10 nm. Further, portions26aare more strongly separated from regions22c, which enables to avoid current leakages.

The memory cells are then formed on regions22c. In particular, vias13are then formed on regions22c.

FIG.4A,FIG.4B,FIG.4C,FIG.4D,FIG.4E,FIG.4F,FIG.4G,FIG.4Hshow steps, preferably successive, of another electronic device manufacturing method.

During the step resulting in the structure ofFIG.4A, as during the step resulting in the structure ofFIG.3A, an etch mask34is formed on a substrate36of semiconductor-on-insulator (SOI) type. Substrate36comprises a lower semiconductor layer38, for example, made of silicon, an insulating layer40, for example, made of silicon oxide, covering layer38, and an upper semiconductor layer42, for example, made of silicon. Mask34is for example made of silicon nitride. A silicon oxide layer44is for example formed on layer42before the forming of mask34. Mask34is thus for example separated from layer42by layer44.

Mask34is formed to have openings at the level of the substrate portions corresponding to portions BK, A-A, B-B ofFIG.3A.

Layers42and44are then etched through the openings in mask34. Thus, layers42and44are removed from the portions of the substrate corresponding to the portions BK, A-A, B-B ofFIG.3A.

Layer40then undergoes a growth step. During this step, layer40in the substrate portions corresponding to the portions BK, A-A, B-B ofFIG.3Agrows to reach an upper level at the level of the upper surface of layer44of portion SOI, for example to reach the level of the upper surface of layer34. In the example ofFIG.3A, the upper surface of layer34in portion SOI and the upper surface of layer40in portions BK, A-A, and B-B are coplanar.

During the step resulting in the structure ofFIG.4B, mask34and layer44are removed. A layer54is formed on the structure, that is, on layer40, in portions BK, A-A, B-B, and on layer44in portion SOI. Layer54is preferably made of the same material as layer40. Layer54is for example made of silicon oxide.

During the step resulting in the structure ofFIG.4C, the portions of layer40and54located, in portions SOI and BK, under the plane of the upper surface of layer42are removed. Layers40and54are not etched in portion A-A, B-B, that is, the portion corresponding to the memory array.

This thus corresponds to a step of raising of the portions of the layer40of portion A-A, B-B which correspond to the trenches20located in the memory array.

During the step resulting in the structure ofFIG.4D, a layer55is formed on the structure. Layer55is made of an insulating material, preferably of the same material as layer40, for example, of silicon oxide. Layer55covers layer42in portion SOI, layer38in portion BK, and layer54in portion A-A, B-B.

Layer55is covered, preferably entirely, with a layer56of a material that can be selectively etched over the material of layers40and54. Layer46is for example made of silicon nitride.

Openings are formed in layer56so that layer56forms an etch mask. In particular, an opening is formed in front of portion BK, that is, the portion of the substrate forming a solid substrate, and in front of the regions22cof portion A-A, B-B.

The layers located between layer56and layer38, that is, the substrate, are then etched through the openings. Thus, layer40is removed from portion BK. Further, the portions of layers40,54, and55located in front of the openings, that is, at the locations of regions22c, are etched.

During the step resulting in the structure ofFIG.4E, layer38undergoes a growth step. More precisely, the portions of layer38exposed during the step ofFIG.4Dundergo a growth step. Thus, layer38extends, in portion BK and at the locations of regions22c, in the openings formed during the step ofFIG.4D. Preferably, layer38extends, in portion BK and at the locations of regions22c, all the way to the level of the upper surface of layer42in portion SOI. The upper surface of layer38in portion BK and at the locations of regions22cis for example coplanar with the upper surface of layer42in portion SOI.

During the step resulting in the structure ofFIG.4F, the portion of layer56located in portion SOI is then removed. Thus, after the steps ofFIGS.4E and4F, layer56as been totally removed, except for the portions located on the portions of layer40of portion A-A, B-B, which correspond to the trenches20located in the memory array.

Further, a layer58is formed on the structure. Layer58is made of an insulating material, preferably of the same material as layer40, for example, of silicon oxide. Layer58covers layer55in portion SOI, layer35in portion BK, and layer55in portion A-A, B-B.

Layer58is covered, preferably entirely, with a layer60of a material that can be selectively etched over the material of layers40and58. Layer60is for example made of silicon nitride.

The thickness of layer60is such that the level, or plane, of the portion of the upper surface of layer60closest to layer38is separated from layer38by the level of the portion of the upper surface of the layer58most distant from layer38. In other words, the level of the portion of the upper surface of layer60closest to layer38is only covered with portions of layer60.

During the step resulting in the structure ofFIG.4G, openings are formed in layer60, forming an etch mask, in front of the locations of the shallow trenches (STI). Shallow trenches may be formed in portions SOI, BK, and A-A, B-B. In particular, in portion A-A, B-B, that is, in the portion of the chip having the memory array formed therein, the shallow trenches comprise the trenches18ofFIGS.2A and2B. The shallow trenches for example all have substantially the same depth. An etch step is then carried out through said openings in layer60to form cavities at the locations of trenches18.

In portion SOI, the portions of layers38,40,42,55, and58located at the locations of the shallow trenches are etched through the openings in layer60. Thus, layers40,42,55, and58are preferably entirely crossed by the cavities formed by the etching. Layer38is preferably partially crossed by the cavities formed by the etching.

In portion BK, the portions of layers38and58located at the locations of the shallow trenches are etched through the openings in layer60. Thus, layer58is preferably entirely crossed by the cavities formed by the etching. Layer38is preferably partially crossed by the cavities formed by the etching.

In portion A-A, B-B, that is, in the portion where the memory array is formed, the portions of layers38,40,54,55, and58located at the locations of shallow trenches18are etched through the openings in layer60. Thus, layers40,54,55, and58are preferably entirely crossed by the cavities formed by the etching. Layer38is preferably partially crossed by the cavities formed by the etching.

A layer62is formed on the structure. The thickness of layer62is such that layer62fills the cavities formed at the locations of the shallow trenches and covers, preferably entirely, layer60.

Layer62is made of an electrically-insulating material, for example, of silicon oxide. Preferably, layer62is made of the same material as layer58. Preferably, layer62is made of the same material as layer40.

During the step resulting in the structure ofFIG.4H, the structure undergoes a step of polishing, for example, by a chemical mechanical polishing method. The polishing method is carried out to expose, preferably entirely, an upper surface of layer60.

In portion SOI, the portion of layer62located above the level of the upper surface of layer60is for example removed. The upper surface of the device in portion SOI is thus planar and comprises the upper surface of layer60laterally surrounded with the upper surface of layer62.

In portion BK, the portion of layer62located above the level of the upper surface of layer60is for example removed. The upper surface of the device in portion BK is thus planar and comprises the upper surface of layer60laterally surrounded with the upper surface of layer62.

In portion A-A, B-B, layers60and62are polished to remove all the material of layer62located above layer60. Thus, layers60and62are removed all the way to the level of the portion of layer60closest to layer38. The upper surface of the device in portion A-A, B-B is thus planar and comprises the upper surface of layer60laterally surrounded with the upper surface of layer62. No portion of layer60in portion A-A, B-B is separated from the upper surface of the device by a portion of layer62.

The portions of layer60are then removed by a step of etching of the material of layer60selective over the material of layer58and the material of layer62. Thus, the plane of the upper surface of the shallow trenches18is separated from the plane of the upper surface of layer58by a height substantially corresponding to the thickness of layer60.

The method further comprises, after the step described in relation withFIG.4H, a step during which various steps of manufacturing of electronic components may be carried out. In particular, semiconductor material doping steps are carried out.

The layer42of portion SOI and the layer38of portion BK are for example doped to form electronic components, in particular transistors. Similarly, the layer38of portion A-A, B-B is doped to form regions22a,22b, and22c.

The doping steps for example comprise the forming and the removal of masks, for example, lithophotography masks. These steps cause the partial removal of the material of layer58and of the shallow trenches. Thus, layer58is removed during these steps. Preferably, the thickness of layer58is such that layer58is fully removed. The portions of layer54, and for example the portions of layer55, located on trenches20are not removed. Further, the height of the shallow trenches, in particular the trenches18of the memory array, is decreased by the steps of forming and of removal of the masks.

Strips26are then formed on the portions of layer54or55located on trenches20. Layer28, not shown inFIG.4H, made of polysilicon is then formed on the structure.

The presence and the maintaining of the portions of layer54enable to decrease the distance between portions26aand26bof strips26(FIGS.2A and2B). Thus, the lower and upper planes, that is, portions26aand26b, are separated by a distance D3, shorter than distance D1. In other words, the upper surfaces of trenches18and20are separated by distance D. Distance D3is for example shorter than 10 nm. Further, portions26aare more strongly separated from regions22c, which enables to avoid current leakages.

The memory cells are then formed on regions22c. In particular, vias13are then formed on regions22c.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art. In particular, although the drawings show a device comprising a portion SOI comprising electronic components formed inside and on top of an SOI-type substrate and a portion BK comprising electronic components formed inside and on top of a solid substrate, the device may only comprise portion BK or portion SOI, in addition to the portion A-A, B-B comprising the memory array.

Method of manufacturing a device may be summarized as including a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, each memory cell being located on a region of a substrate, the method including the following steps: a. the forming of first insulating trenches separating from one another the substrate regions of a same cell row, and b. the forming of second trenches separating from one another the substrate regions of a same cell column, the second trenches having a height greater than the height of the first trenches, step a. including the following steps: a1. the forming of a lower portion of each first trench, and a2. the forming of an upper portion of each first trench, the forming of the upper portions including the deposition of a first insulating layer, the etching of the portions of the first insulating layer which are not located on the upper portions.

The substrate may be of substrate-on-insulator type in the second portion of the device.

The method may include, before steps a. and b., a step c. of removal, in the first portion, of the upper semiconductor layer of a substrate of substrate-on-semiconductor type and the growth of the insulating material of the insulating intermediate layer of the substrate of substrate-on-semiconductor type along a height at least equal to the height of the upper semiconductor layer of the substrate, the intermediate layer being made of a first insulating material.

The method may include, before steps a. and b. and after step c., step d. of forming of the first layer on the first and second portions.

Step a2. may include the forming of first openings in the first layer in front of the locations of the regions, and step a1. may include the etching of the intermediate layer through the first openings, step a2. may include, after step a1, the removal of the portions of the first layer located in the second portion, the first layer being made of a second insulating material.

Step a2. may include the removal of the portions of the first layer located outside of the first portion and the removal of the portions of the intermediate layer and of the first layer located at the locations of the first trenches, the first layer being made of the first insulating material.

The method may include, after step a. and before step b., a step e. of growth of the lower layer of the substrate of semiconductor-on-insulator type at the locations of the regions.

The method may include, after step e., a step f. of forming of a stack may include a second layer made of the first material and a third layer made of the second material on the first and second portions.

The first and second materials may be selectively etchable with respect to each other.

The first material may be silicon oxide and the second may be silicon nitride.

Step b. may include, after step f., the forming of second openings in the third layer of the stack in front of the locations of the second trenches, the forming of cavities through the second openings, and the forming, on the first and second portions, of a fourth layer made of the first material sufficiently thick to fill the cavities.

The method may include, after step b, a step g. of removal by chemical mechanical polishing of the portions of the fourth layer located above the third layer of the stack and a step h. of removal of the third layer.

The method may include, after step h., substrate doping steps.

The method may include the deposition of silicon strips on the upper portions of the first trenches.

Device may be summarized as including a first portion having an array of memory cells arranged therein and a second portion having transistors arranged therein, each memory cell being located on a region of a substrate, the device including first insulating trenches separating from one another the substrate regions of a same cell row, and second trenches separating from one another the substrate regions (22c) of a same cell column, the second trenches having a height greater than the height of the first trenches, wherein the upper surfaces of the first and second trenches are separated by a distance shorter than 10 nm.

Device may be summarized as including a first portion having an array of memory cells arranged therein and a second portion having transistors arranged therein, each memory cell being located on a region of a substrate, the device including first insulating trenches separating from one another the substrate regions of a same cell row, and second trenches separating from one another the substrate regions of a same cell column, the second trenches having a height greater than the height of the first trenches, wherein each first trench includes a lower portion made of a first material and a lower portion of a second material different from the first material, where the second trenches do not include the second material.