Transmission lines using bending fins from local stress

Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application No. PCT/US2016/069538, filed Dec. 30, 2016, entitled “TRANSMISSION LINES USING BENDING FINS FROM LOCAL STRESS,” which designates the United States of America, the entire disclosure of which is hereby incorporated by reference in its entirety and for all purposes.

FIELD OF THE INVENTION

Embodiments of the invention are in the field of semiconductor devices and processing and, in particular, the formation of on-chip electromagnetic wave guides formed with high aspect ratio bent fins.

BACKGROUND OF THE INVENTION

Optical fiber and nano patterned silicon based waveguides have been used as interconnects on-chip to transmit ultra-high frequencies. Typically, a waveguide includes an inner core layer, a dielectric cladding layer with a refractive index that is higher than the core layer, and an outer shielding layer. Such a structure guides optical waves by total internal reflection. The formation of these components presently requires unique processing operations that are not the same as those used to form the transistors, diodes, and/or other circuitry on the chip. Accordingly, the fabrication of such waveguides requires additional processing operations and utilizes additional area on the surface of the chip. Therefore, the use of such interconnects increases the overall cost of such chips.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention may utilize high aspect ratio fins to form a structure through which electromagnetic radiation may be propagated. According to an embodiment, electromagnetic waveguides may be formed with high aspect ratio fins that are patterned at the same time as high aspect ratio fins that are used to form transistors and other features on the semiconductor. The fins used to form the electromagnetic waveguide may be bent by stresses that are generated in a shallow trench isolation (STI) oxide when the STI oxide layer is annealed. As such, embodiments may utilize closely spaced fins that are subsequently bent towards each other to form a cavity with processing operations that are already needed to fabricate other devices on the substrate. Additionally, the electromagnetic waveguide may be modified by doping the fins and/or by including various cladding layers and shielding layers that may enhance the propagation of certain wavelengths of electromagnetic radiation, while at the same time attenuating the propagation of other wavelengths of electromagnetic radiation.

Referring now toFIG. 1A, a cross-sectional illustration of a pair of electromagnetic waveguides100are shown according to an embodiment of the invention. According to an embodiment, the electromagnetic waveguide100may include a pair of bent fins110A and110E that extend up from a substrate105. The fins110A and110E are bent towards each other to form a cavity112through which electromagnetic radiation may propagate. As used herein, a “bent fin” is a fin110that has a centerline109that forms an angle θ with a top surface106of substrate105on which the fin110is formed that is not substantially a right angle. For example, the angle θ may be approximately ±1° or more away from a right angle. In an embodiment, the angle θ may be ±15° or more away from a right angle. Embodiments may include bent fins that contact each other. In such embodiments, the shape of the cavity112may be defined by a first fin110A, a second fin110B, and a top surface106of the substrate105. However, embodiments are not limited to such configurations and the shape of the cavity112may also be defined by additional material layers, as will be described in greater detail below. In an embodiment, the fins110are high aspect ratio fins110. For example, the aspect ratio may be 10:1 or greater. In a specific embodiment, the aspect ratio may be 50:1 or greater. In an embodiment, the fins110may be spaced with a pitch P. The pitch P may be approximately 50 nm or less. In a particular embodiment, the pitch P may be approximately 42 nm or less.

In an embodiment, the fins110may be formed from a semiconducting material. For example, the fins110may be silicon. Additional embodiments may include fins110that are formed with other semiconductor materials, such as III-V semiconductor materials. The fins110may be a single semiconductor material or the fins may include a stack of two or more semiconductor materials. In an embodiment, the fins110may be the same material as the substrate105. For example, the substrate105may be a semiconductor substrate. In one implementation, the semiconductor substrate105may be a crystalline substrate formed using a bulk semiconductor or a semiconductor-on-insulator substructure. In one particular embodiment, the semiconductor substrate105may include a stack of semiconductor materials. For example, the semiconductor substrate105may include a silicon base layer and one or more III-V semiconductor materials grown over the silicon base layer. In one example, a GaN layer may be separated from the silicon base layer by one or more buffer layers. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate105and fins110may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of embodiments of the invention.

In an embodiment, the fins110may also be doped in order to change the propagation characteristics of the electromagnetic waveguide100. In an embodiment, the fins110may be doped with an implantation/diffusion process. For example, dopants (e.g., boron, phosphorous, silicon, magnesium, nitrogen, or any other commonly used dopant) may be ion-implanted into the fins110. An annealing process that activates the dopants and causes them to diffuse further into the fins110typically follows the ion implantation process. Doping may be used to enhance and/or attenuate the propagation of specific wavelength through the electromagnetic waveguides100, by changing the refractive index of the fins110.

According to an embodiment, a conductive layer122may be formed over the surfaces of the fins110to provide shielding to the electromagnetic waveguide. The conductive layer122may be a conformal layer. As such, the conductive layer122may be formed on the outer surfaces111of the fins110and the inner surfaces113that define the cavity112without filling the cavity112. For example, the conductive layer122may be a metallic material. In a particular embodiment, the conductive layer122may be titanium nitride. In some embodiments, the conductive layer122may be omitted. In embodiments where the conductive layer122is omitted, the fins110may be highly doped so that they function as a conductive material.

In order to improve the propagation efficiency of the electromagnetic waveguide110, embodiments of the invention may include a cavity112that is lined with a cladding layer132and filled with a core134. The cladding layer132may be a material that has a refractive index that is greater than a refractive index of the core134. In an embodiment, the cladding layer132may be a dielectric material. For example, the cladding layer132may be glass. Additionally, it is to be appreciated that the cladding layer132is formed with a conformal deposition process. As such, the cladding layer132may form over the surfaces of the conductive layer122within the cavity112without filling the cavity112. In an embodiment, the core134may be an insulative material. For example, the core134may be an oxide, such as an STI oxide. Additional embodiments may omit forming a core134in the cavity112(i.e., the cavity112may have an air core112).

Referring now toFIG. 1B, a pair of electromagnetic waveguides101are shown, according to an additional embodiment of the invention. The electromagnetic waveguides101are substantially similar to the electromagnetic waveguides100illustrated inFIG. 1Awith the exception that the fins110do not contact each other. In an embodiment, the ends of fins110may be spaced away from each other by a spacing S. For example, the spacing S may be less than approximately 15 nm. In an additional embodiment, the spacing S may be less than approximately 5 nm. Since the fins110do not contact each other to form a sealed cavity112, the conductive layer122may be used to fill the gap between the ends of the fins110. The conformal deposition process allows for the conductive layer122to grow together and seal the cavity112without filling the cavity112with the conductive material. Accordingly, the shape of the cavity112may be defined by a first fin110A, a second fin110B, the top surface106of the substrate105, and a portion of the conductive layer122

Referring now toFIG. 2, a schematic plan view of a portion of an on-chip mixer region270is shown, according to an embodiment. InFIG. 2, a first electromagnetic waveguide200A and a second electromagnetic waveguide200Bare formed on a substrate205and are communicatively coupled with an on-chip mixer272. In an embodiment, the first and second electromagnetic waveguides200A and200Bmay be substantially similar to the electromagnetic waveguides100or101described above with respect toFIGS. 1A and 1B, and therefore, will not be described in greater detail here. Embodiments may also include an on-chip mixer that is fabricated on the semiconductor substrate205. In a particular embodiment, transistors, diodes, and/or other circuitry and components used to form the mixer272may be fabricated substantially in parallel with the formation of the first and second electromagnetic waveguides200A and200B. According to an embodiment, the first electromagnetic waveguide200A may be used to transmit a local oscillator signal to the mixer272and the second electromagnetic waveguide200Bmay be used to transmit an information signal to the mixer272. Accordingly, the mixer272may generate a difference frequency output signal that is transmitted along a third electromagnetic waveguide274. The use of such a mixer272may allow for the difference frequency signal to be generated in the far IR (i.e., 1-3 THz) range.

While embodiments illustrated and described inFIGS. 1A, 1B, and 2each include at least two electromagnetic waveguides, embodiments are not limited to such configurations. Particularly, embodiments may include any number of electromagnetic waveguides formed on a substrate. For example, a single electromagnetic waveguide may be formed on the substrate or two or more electromagnetic waveguides may be formed on the substrate. Furthermore, while embodiments of the invention describe the formation of electromagnetic waveguides in the mixer region270of the substrate205, it is to be appreciated that electromagnetic waveguides formed according to embodiments of the invention may be fabricated on any portion of the semiconductor substrate205.

Referring now toFIGS. 3A-3I, a series of cross-sectional illustrations depicting processing operations for forming an electromagnetic waveguide with bent fins are shown, according to an embodiment of the invention. Starting withFIG. 3A, a sacrificial mask structure352is formed over a semiconductor substrate305. In an embodiment, the sacrificial mask structure352may be formed over an isolation layer307. For example, the isolation layer307may be any suitable etchstop material (e.g., a nitride). The sacrificial mask structure352may be polysilicon or any other suitable material. Spacers353may also be formed along the sidewall surfaces of the sacrificial mask structure with known spacer deposition and etching processes. The spacers353may be a material that is resistant to an etching chemistry used to selectively remove the sacrificial mask structure352. For example, the spacers353may be an oxide, a nitride, or the like. The use of spacers353allows for the spacing and critical dimension of the features patterned into the substrate305to be reduced. In an embodiment, the pitch P of the spacers353that are formed along the vertical faces of the sacrificial mask structure352that face each other may be approximately 50 nm or less. In an embodiment, the pitch P may be approximately 42 nm or less. As such, the subsequently formed fins are spaced close enough together so that they may be bent towards each other to form a cavity.

Referring now toFIG. 3B, a cross-sectional illustration is shown after the sacrificial mask structure352is removed, according to an embodiment of the invention. In an embodiment, the sacrificial mask structure352may be removed with any suitable etching process (e.g., wet etching or dry etching). As illustrated, the etching process may also include removing portions of the isolation layer307that are not covered by the spacers353to form a patterned hardmask308. In an embodiment, the sacrificial mask structure352and the isolation layer307may be removed with different etching chemistries.

Referring now toFIG. 3C, a cross-sectional illustration is shown after the pattern of the spacers353has been transferred into the semiconductor substrate305, according to an embodiment of the invention. In an embodiment, the spacers305formed above the patterned hardmask308may be removed prior to etching the semiconductor substrate305. Embodiments may then include etching the semiconductor substrate305using the patterned hardmask308as a mask to form fins310. For example, the semiconductor substrate305may be etched with a dry etching process (e.g., plasma etching or the like). The fins310may be high aspect ratio fins310. For example, the aspect ratio may be 10:1 or greater. In a specific embodiment, the aspect ratio may be 50:1 or greater.

It is to be appreciated that the process for forming the fins310described inFIGS. 3A-3Cmay be substantially similar to the process for forming fins that will be further processed to form non-planar transistors (not shown) on the semiconductor substrate305. Accordingly, the fins310used for the electromagnetic waveguide may be formed in parallel with the fins used to form non-planar transistors or other devices. Therefore, additional processing operations are not needed to fabricate the fins310, and the throughput is not significantly decreased.

Referring now toFIG. 3D, a cross-sectional illustration is shown after an isolation oxide is deposited over the substrate305, according to an embodiment of the invention. In an embodiment, the patterned hardmask308may be removed with an etching process and the isolation oxide315may be deposited over the semiconductor substrate305. For example, the isolation oxide315may be deposited with a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or the like. The isolation oxide315may then be planarized with a top surface of the fins310. For example, the isolation oxide315may be planarized with a chemical mechanical polishing (CMP) process, or the like. In an additional embodiment, the patterned hardmask308may be removed during the planarization process after the isolation oxide315is deposited. In an embodiment, the isolation oxide315may be formed at the same time a shallow trench isolation (STI) oxide is deposited in the active regions (i.e., regions where transistor devices are fabricated) of the semiconductor substrate305. Accordingly, the formation of the isolation oxide315may not require additional processing operations to be added to the process flow.

Referring now toFIG. 3E, a cross-sectional illustration is shown after the isolation oxide is annealed, according to an embodiment of the invention. In an embodiment, the annealing process may be a typical annealing process used in STI formation. For example, the annealing process may range from approximately 800° C. to approximately 1100° C., and be held for lengths of times between tens of seconds to tens of minutes. According to an embodiment, annealing the isolation oxide315induces stresses in the isolation oxide315. Due to the high aspect ratio of the fins310, the stress in the isolation oxide315may cause the fins310that are closely spaced to each other to bend towards each other. In an embodiment, the fins310are bent towards each other so that a centerline309of the fin310and a top surface306of substrate305on which the fin310is formed produce an angle θ that is not substantially a right angle. For example, the angle θ may be approximately ±1° or more away from a right angle. In an embodiment, the angle θ may be ±15° or more away from a right angle. In an embodiment, the angle θ of each fin310may be substantially similar to each other. In an additional embodiment, the angle θ of each fin310may not be substantially similar to each other. In the illustrated embodiment, the fins310are bent towards each other, but are not touching. However, in additional embodiments of the invention, the fins310may be bent so that they contact each other, similar to the embodiment illustrated inFIG. 1A.

Referring now toFIG. 3F, a cross-sectional illustration is shown after the isolation oxide is removed, according to an embodiment of the invention. In an embodiment, the isolation oxide315may be removed with a suitable etching process. For example, a wet etching process may be used to remove the isolation oxide315. In some embodiments the exposed fins310may be doped with dopants to alter the propagation characteristics of the electromagnetic waveguide. For example, dopants (e.g., boron, phosphorous, silicon, magnesium, nitrogen, or any other commonly used dopant) may be ion-implanted into the fins310. An annealing process that causes the dopants to diffuse further into the fins310may follow the ion implantation process. It is to be appreciated that the fins310may also be doped prior to the formation of the isolation oxide315or at any other suitable time in accordance with other embodiments of the invention.

Referring now toFIG. 3G, a cross-sectional illustration is shown after a conductive layer322is formed over the surfaces of the fins310to provide shielding to the electromagnetic waveguide. The conductive layer322may be a conformal layer. In an embodiment, the conductive layer322may be deposited with a conformal deposition process such as atomic layer deposition (ALD). As such, the conductive layer322may form on the outer surfaces311of the fins310and the inner surfaces313that face the cavity312without filling the cavity312. In embodiments where the fins310do not contact each other, the conductive layer322may be grown to a thickness that results in the opening between the fins310being closed to form an enclosed cavity312between the fins310. In an embodiment, the conductive layer322may be between approximately 1 nm thick or greater. In some embodiments, the conductive layer322may be approximately 50 nm thick or greater. In an embodiment, the conductive layer322may be a metallic material. In a particular embodiment, the conductive layer322may be titanium nitride. In some embodiments, the conductive layer322may be omitted. In such embodiments, the fins310may be highly doped so that they function as a conductive material.

Referring now toFIG. 3H, a cross-sectional illustration is shown after a cladding layer332is formed, according to an embodiment. In an embodiment, the cladding layer332may be a dielectric material. For example, the cladding layer332may be glass. Additionally, it is to be appreciated that the cladding layer332may be formed with a conformal deposition process, such as an ALD process. As such, the cladding layer332may form over the surfaces of the conductive layer322within the cavity312without filling the cavity312. In an embodiment, the cladding layer332may be between approximately 1 nm thick or greater. In some embodiments, the cladding layer332may be approximately 50 nm thick or greater. In an embodiment, the cladding layer332may also be doped in order to alter the refractive index of the cladding layer322to improve transmission of a desired frequency and/or to attenuate undesired frequencies of electromagnetic radiation. For example, the dopants may be in-situ deposited during the ALD process.

Referring now toFIG. 3I, a cross-sectional illustration is shown after a core334is deposited within the cavity312. In an embodiment, the core334may be a material that has a refractive index that is greater than the refractive index of the cladding layer332. In an embodiment, the core334is an insulative material. For example, the core may be an oxide, such as an STI oxide. In an embodiment, the core334is deposited with a conformal deposition process, such as ALD in order to allow for the core334to be formed within the cavity312. After the material used to form the core334is deposited, an etching process (e.g., a dry etching process) may be used to remove the portions of the core material from outside the cavity312. Since the core334is shielded from the etching chemistry by the fins310, the core334will remain in the cavity312after the excess core material is removed from the outer surfaces of the fins310. In additional embodiments, the excess core material may not be removed from outside the electromagnetic waveguide.

FIG. 4illustrates an interposer400that includes one or more embodiments of the invention. The interposer400is an intervening substrate used to bridge a first substrate402to a second substrate404. The first substrate402may be, for instance, an integrated circuit die. The second substrate404may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer400is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer400may couple an integrated circuit die to a ball grid array (BGA)406that can subsequently be coupled to the second substrate404. In some embodiments, the first and second substrates402/404are attached to opposing sides of the interposer400. In other embodiments, the first and second substrates402/404are attached to the same side of the interposer400. And in further embodiments, three or more substrates are interconnected by way of the interposer400.

The interposer may include metal interconnects408and vias410, including but not limited to through-silicon vias (TSVs)412. The interposer400may further include embedded devices414, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer400.

In accordance with embodiments of the invention, apparatuses that include electromagnetic waveguides formed with bent fins, or processes for forming such devices disclosed herein may be used in the fabrication of interposer400.

FIG. 5illustrates a computing device500in accordance with one embodiment of the invention. The computing device500may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. The components in the computing device500include, but are not limited to, an integrated circuit die502and at least one communication chip508. In some implementations the communication chip508is fabricated as part of the integrated circuit die502. The integrated circuit die502may include a CPU504as well as on-die memory506, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).

Computing device500may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory510(e.g., DRAM), non-volatile memory512(e.g., ROM or flash memory), a graphics processing unit514(GPU), a digital signal processor516, a crypto processor542(a specialized processor that executes cryptographic algorithms within hardware), a chipset520, an antenna522, a display or a touchscreen display524, a touchscreen controller526, a battery528or other power source, a power amplifier (not shown), a global positioning system (GPS) device544, a compass530, a motion coprocessor or sensors532(that may include an accelerometer, a gyroscope, and a compass), a speaker534, a camera536, user input devices538(such as a keyboard, mouse, stylus, and touchpad), and a mass storage device540(such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The processor504of the computing device500includes one or more devices, such as transistors with one or more field plates that are formed over the channel region, according to an embodiment of the invention. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip508may also include one or more devices, such as one or more electromagnetic waveguides formed with bent fins, according to an embodiment of the invention.

In further embodiments, another component housed within the computing device500may contain one or more devices, such as transistors that include one or more electromagnetic waveguides formed with bent fins, or processes for forming such devices, according to an embodiment of the invention.

an electromagnetic waveguide, comprising: a first semiconductor fin extending up from a substrate; a second semiconductor fin extending up from the substrate, wherein a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle; a cavity defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate; and a cladding layer lining surfaces of the cavity.

the electromagnetic waveguide of Example 1, wherein the first semiconductor fin and the second semiconductor fin contact each other at least at one point.

the electromagnetic waveguide of Example 1, wherein the first semiconductor fin and the second semiconductor fin do not contact each other.

the electromagnetic waveguide of Example 1, Example 2, or Example 3, wherein the cavity is further defined by a conductive layer formed along the surfaces of the first and second semiconductor fins.

the electromagnetic waveguide of Example 4, wherein the conductive layer is between the cladding layer and the first and second semiconductor fins.

the electromagnetic waveguide of Example 1, Example 2, Example 3, Example 4, or Example 5, wherein the centerline of each fin forms an angle with the tops surface of the substrate that is 1° or more away from orthogonal.

the electromagnetic waveguide of Example 6, wherein the angle of the first fin and the angle of the second fin are substantially equal.

the electromagnetic waveguide of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, or Example 7, wherein the first and second semiconductor fins and/or the cladding layer are doped.

the electromagnetic waveguide of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, or Example 8, wherein the first and second semiconductor fins are high aspect ratio fins.

the electromagnetic waveguide of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, or Example 9, further comprising a core formed in the cavity.

the electromagnetic waveguide of Example 10, wherein the core has a refractive index that is greater than a refractive index of the cladding layer.

the electromagnetic waveguide of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Example 10, or Example 11, wherein a pitch between the first semiconductor fin and the second semiconductor fin is less than approximately 50 nm.

a method of forming an electromagnetic waveguide, comprising: forming a first and second semiconductor fin on a semiconductor substrate, wherein the first and second semiconductor fins are high aspect ratio fins; depositing an oxide over the substrate and the first and second semiconductor fins; annealing the oxide, wherein annealing the oxide bends the first and second semiconductor fins toward each other; removing the oxide; and forming a conformal cladding layer along the surface of the first and second semiconductor fins.

the method of Example 13, wherein the bent first and second semiconductor fins and a top surface of the substrate define a cavity.

the method of Example 13 or Example 14, wherein the cladding layer lines the cavity.

the method of Example 15, further comprising: forming a core in the cavity, wherein the core has a refractive index that is greater than a refractive index of the cladding layer.

the method of Example 15 or Example 16, wherein the first semiconductor fin and the second semiconductor fin contact each other after being bent.

the method of Example 15 or Example 16, wherein the first semiconductor fin and the second semiconductor fin do not contact each other after being bent.

the method of claim17, further comprising: forming a conformal conductive layer over the surface of the first and second semiconductor fins prior to forming the conformal cladding layer.

the method of Example 13, Example 14, Example 15, Example 16, Example 17, Example 18, or Example 19, further comprising: doping the first and second semiconductor fins; and doping the cladding layer.

an on-chip communication system, comprising: a first electromagnetic waveguide; a second electromagnetic waveguide, wherein the first and second electromagnetic waveguides each comprise: a first semiconductor fin extending up from a substrate; a second semiconductor fin extending up from the substrate, wherein a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle; a cavity defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate; and a cladding layer lining surfaces of the cavity; and a mixer communicatively coupled to the first and second electromagnetic waveguides.

the on-chip communication system of Example 21, wherein the first electromagnetic waveguide is a local oscillator signal line and the second electromagnetic waveguide is an information signal line.

the on-chip communication system of Example 21 or Example 22, wherein the mixer outputs a difference signal, wherein the difference signal is in the far infrared range.

the on-chip communication system of Example 21, Example 22, or Example 23, further comprising: a conductive layer formed between the cladding layer and the first and second semiconductor fins; and a core formed in the cavity.

the on-chip communication system of Example 24, wherein the first and second semiconductor fins are doped and/or the cladding layer is doped, and wherein a refractive index of the core is greater than a refractive index of the cladding layer.