METHODS AND APPARATUS FOR A KNOWLEDGE-BASED DEEP LEARNING REFACTORING MODEL WITH TIGHTLY INTEGRATED FUNCTIONAL NONPARAMETRIC MEMORY

Methods and apparatus for a knowledge-based deep learning refactoring model with tightly integrated functional nonparametric memory are disclosed. An example non-transitory computer readable medium comprises instructions that, when executed, cause a machine to at least estimate a first information extraction cost corresponding to retrieval of information from a local knowledge base, estimate a second information extraction cost corresponding retrieval of information from a remote knowledge base, select an information source based on the first and second estimated information extraction costs, query the selected information source, in response to determining that the selected information source was an external information source, store the queried information in the local knowledge base, organize the stored information in the local knowledge base, and return the queried information.

FIELD OF THE DISCLOSURE

This disclosure relates generally to deep learning, and more particularly, to a knowledge-based deep learning refactoring model with tightly integrated functional nonparametric memory.

BACKGROUND

Deep Learning (DL) models, and more particularly, Knowledge-Based Deep Learning (DL) models are typically coupled to a Knowledge Base (KB), which generally incorporates a large volume of specific information (e.g., particular facts) used to answer queries. The accumulation of information in the corresponding Knowledge Bases (KBs) of these models leads to an increased overall model size over time.

The figures are not to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts.

DETAILED DESCRIPTION

Artificial intelligence (AI), including machine learning (ML), deep learning (DL), and/or other artificial machine-driven logic, enables machines (e.g., computers, logic circuits, etc.) to use a model to process input data to generate an output based on patterns and/or associations previously learned by the model via a training process. For instance, the model may be trained with data to recognize patterns and/or associations when processing input data such that other input(s) result in output(s) consistent with the recognized patterns and/or associations.

Many different types of machine learning models and/or machine learning architectures exist. In some examples disclosed herein, a Neural Network (NN) is used. Using a Neural Network (NN) model enables the interpretation of data wherein patterns can be recognized. In general, machine learning models/architectures that are suitable to use in the example approaches disclosed herein will be Convolutional Neural Network (CNN) and/or Deep Neural Network (DNN), wherein interconnections are not visible outside of the model. However, other types of machine learning models could additionally or alternatively be used such as Recurrent Neural Network (RNN), Support Vector Machine (SVM), Gated Recurrent Unit (GRU), Long Short Term Memory (LSTM), etc.

In general, implementing a ML/AI system involves two phases, a learning/training phase and an inference phase. In the learning/training phase, a training algorithm is used to train a model to operate in accordance with patterns and/or associations based on, for example, training data. In general, the model includes internal parameters that guide how input data is transformed into output data, such as through a series of nodes and connections within the model to transform input data into output data. Additionally, hyperparameters are used as part of the training process to control how the learning is performed (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.). Hyperparameters are defined to be training parameters that are determined prior to initiating the training process.

Different types of training may be performed based on the type of ML/AI model and/or the expected output. For example, supervised training uses inputs and corresponding expected (e.g., labeled) outputs to select parameters (e.g., by iterating over combinations of select parameters) for the ML/AI model that reduce model error. As used herein, labelling refers to an expected output of the machine learning model (e.g., a classification, an expected output value, etc.) Alternatively, unsupervised training (e.g., used in deep learning, a subset of machine learning, etc.) involves inferring patterns from inputs to select parameters for the ML/AI model (e.g., without the benefit of expected (e.g., labeled) outputs).

In examples disclosed herein, ML/AI models are trained on functions (e.g., extracting necessary information on a per-query basis from the Knowledge Base). However, any other training algorithm may additionally or alternatively be used. In examples disclosed herein, training is performed on the feature-based classification model and appendix classification model.

Training is performed using hyperparameters that control how the learning is performed (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.).

Training is performed using training data. In examples disclosed herein, the training data includes an example set of data stored within a Knowledge Base (KB), however, any other type of data may be used.

Once training is complete, the model is deployed for use as an executable construct that processes an input and provides an output based on the network of nodes and connections defined in the model. The model is stored in a parametric memory for execution by the example KBRM system100ofFIG. 1.

Once trained, the deployed model may be operated in an inference phase to process data. In the inference phase, data to be analyzed (e.g., live data) is input to the model, and the model executes to create an output. This inference phase can be thought of as the AI “thinking” to generate the output based on what it learned from the training (e.g., by executing the model to apply the learned patterns and/or associations to the live data). In some examples, input data undergoes pre-processing before being used as an input to the machine learning model. Moreover, in some examples, the output data may undergo post-processing after it is generated by the AI model to transform the output into a useful result (e.g., a display of data, an instruction to be executed by a machine, etc.).

In some examples, output of the deployed model may be captured and provided as feedback. By analyzing the feedback, an accuracy of the deployed model can be determined. If the feedback indicates that the accuracy of the deployed model is less than a threshold or other criterion, training of an updated model can be triggered using the feedback and an updated training data set, hyperparameters, etc., to generate an updated, deployed model.

While Deep Learning (DL) has recently provided high accuracy solutions for Natural Language Processing (NLP), computer vision, medical diagnosis, and a variety of other applications, the technology has seen several substantial gaps over the years. In particular, Deep Learning (DL) models are growing at an unsustainable rate. A key factor leading to the huge size of DL models is the exhaustive incorporation of unstructured information into the Deep Learning (DL) structure, leading to a highly inefficient implementation. Current DL approaches also have well-documented challenges in Out-Of-Distribution (OOD) accuracy, limited extensibility to new domains, and limited explainability of their results.

Current published approaches for deep learning (DL) have several additional limitations. Some approaches cannot readily adapt to addition of new knowledge. For example, some approaches use a predetermined vocabulary of 1 million entities. Any additions, deletions or modification of the entity memory requires retraining the entire system from scratch, which requires significant computation (e.g., a few days with 64 Tensor Processing Units (TPUs)). Some approaches are accessing direct plaintext in a large document corpus. This class of algorithms relies on the data being directly articulated and tagged in the document corpus, and therefore lacks the general ability to synthesize information from multiple sources.

Additionally, some approaches are incorporating embeddings trained from a Knowledge Graph (KG) as a source of information. These trained embeddings have rather limited layered and abstracted Knowledge Representation and Reasoning (KR&R) constructs, constraining their ability to deduct knowledge from given information. Models for some of the approaches have not shown explainability capabilities, in which an output of an inference (e.g., an answer in a Question and Answer (QnA) solution) is fully traceable to the base information and mapping that yielded that outcome. Model sizes of some of the approaches for more general domains are very large and new contributions in this area have demonstrated a rapid growth in model size over time.

Disclosed herein is a Knowledge-Based Refactored DL Model (KBRM) where the capability of the model is achieved by a Neural Network (NN) tightly coupled with a structured Knowledge Base (KB) which contains aggregated and consolidated information across multiple sources. The NN portion is trained on functions (also can be referred to as ‘skills’) and on extracting needed information on a per-query basis from the KB. The KB is adjacent to the NN and tightly integrated with it to provide facts and concepts as required to produce high quality results. This separation of machine learned functionality and/or skills in the NN model from a set of facts and concepts in the KB enables significant reduction in DL model size, increased extensibility with reduced retraining and/or adaptation, and much improved explainability by tracking the explicit data being utilized on a per-query basis.

While the distinction between Functionality (or Skills) and the model information does not create non-overlapping sets, many elements can be clearly identified as part of the function (ex: entity recognition) while others can be clearly identified as ‘Model information’ (ex: ‘1890’ as the year in which Idaho gained statehood). The volume of model data grows at a fast rate as models address more real-life spaces and are expected to handle the very long tail of less frequently used OOD information. A DL model will be considered to be ‘Refactored’ if the NN model primarily contains ‘Skills’ and commonly used information in its parametric memory, while the vast majority of the Model Information resides in the associated KB that is accessed as part of executing the function.

A model trained on functions and classes/abstractions will be applicable as effectively to any information of that class whether the particular information was available during training or not. This significantly alleviates the challenges of OOD and domain adaptation. As long as the functions are similar and the classes/abstractions are equivalent, the effective scope of the AI system covers whatever is the scope of information in the KB during inference. For this reason, it is also possible to localize information and customize an AI solution without re-training or fine-tuning. As long as the functions are similar and the classes/abstractions are matched, particular localized information can be applied during inference. This feature of the KBRM contributes to much-improved data extensibility, domain transferability and customization with localized data.

The dual functionality of providing any programmed (non-NN) functionality, as well as outputting explanations to the results delivered by the NN model is highly desirable. In particular, examples of the KBRM disclosed herein provide tracking of the entities and links extracted from the KB to yield the results. They will also include visualization of the embeddings and attention across layers in the latent space. The requirement for the KB to have explicit and intelligible information, relationships and abstractions, enables clear communication of the path used to reach the AI outcome.

The pace of growth of Language Models and other large DL models is costly and unsustainable. By refactoring the DL models and retaining the vast majority of information in an auxiliary KB, model size can be reduced by orders of magnitude and the pace of model growth substantially curtailed. This can have strategic implications for the Total Cost of Ownership (TCO) for both training and inference and boost deployment of DL at scale. Reducing model size opens more opportunities to deploy highly capable AI approaches in systems with power and cost constrains, such as in Edge computing.

KBRMs possess a separation between functional skills and the information on which they operate. This removes much of the statistical limitations caused by a particular distribution present in the DL training data. As long as no new functionality (or skill) is required, the quality of results is dependent on the information present during inference. This information can be broader than what was used for training (therefore alleviating OOD issues) as well as reflect a new domain or localized knowledge. This capability will increase the value of DL approaches in areas like autonomous driving or financial systems where rare events (e.g., ‘Black Swan’ events) have catastrophic results and thus must be readily recognized. Also, the ability to apply a DL model with minimal retraining to new domains or to localized information opens the door for a much broader use of AI systems for small and medium businesses where the volume of custom information and the available data science capabilities cannot support specialized re-training or model fine-tuning.

In general, current DL systems are considered to exhibit ‘black box’ inferencing as the mapping is achieved through learned statistical models applied to embeddings in a latent space and cannot be directly traced to the source information in the inference process. A Knowledge-Based Refactored DL Model (KBRM) retrieves its information on a per-query basis from the KB, which has a set of intelligible facts, concepts and relations. The ability to trace the information used for inference enhances the explainability of the results. Explainability is an essential requirement in fields where AI outcomes need to be understood for use at scale (e.g., in the healthcare or financial domains). Explainability of results can also contribute to faster improvement cycles as the cause of the failure might be deduced and the correction might be a KB change rather than model re-training.

The KB can include explicit, intelligible abstractions (such as classes of objects, properties, causal relationships, and more), which allows for higher-level reasoning compared to today's DL systems. This underlying Knowledge Representation & Reasoning (KR&R) capability created by the tightly integrated NN and KB addresses use cases requiring higher levels of machine intelligence.

A KBRM utilizes a relatively small DL model and requires tightly integrated extraction of only needed information for specific input from an auxiliary memory containing the (potentially large) KB. A KBRM can provided through a highly efficient and effective full-stack solution that is optimized across algorithms, SW stack and underlying HW. This can bring into play heterogeneous systems with CPUs/XPUs, and effective large memory integration, such as Intel® Optane™ Persistent Memory. Such highly optimized SW/HW approaches benefit customers and the ecosystem by reducing TCO, power requirements, specialized configurations for massive training, carbon emission footprint, and more.

In a KBRM, the vast majority of information used by the AI system is residing in a KB integrated with the NN. In a non-KBRM, all of the information utilized by the model either resides in parametric memory or is retrieved from some other unstructured source such as plain text.

A KBRM will show little to no degradation when the inference system uses previously learned functionality (skills) to solve for new data that was not reflected in the distribution of the training—either because the data was OOD for training, or because it reflects a new domain not seen during training.

A KBRM will be able to report out what particular information was used for a given query to arrive at the results. It can include the facts being used and any relevant relations and abstractions associated with the facts.

Because only the needed information is included on a per-query basis, a KBRM will provide correct answers even in cases where the information needed is spread over multiple sources or requires reasoning to reach conclusions. It is characterized by leveraging the aggregation, synthesis and abstraction provided by the KB. It will show differentiation where the outcome is not just retrieval of relevant information provided by the sources, but rather requires such aggregation, synthesis, abstraction and deduction.

A full implementation of KBRM includes optimized SW layers and a HW system that can extract information from a KB with very high performance and power efficiency. A KBRM solution will have direct support for per-query extraction from a large memory structure, including hashing of KB elements for fast access, and caching for reduced latency of accessing successive items in a similar graph/memory space.

FIG. 1is a block diagram illustrating an example Knowledge-Based Refactored DL Model (KBRM) system100in accordance with teachings of this disclosure.

Current leading self-contained DL models are growing rapidly in size at an unsustainable pace in part due to incorporating a large volume of specific information (e.g., particular facts). Incorporation of information in parametric models leads to increased model size corresponding to the volume of information that will potentially be needed during inference (irrespective of the likelihood of occurrence in inference). This is expected to continue to grow in real-world use cases. Information memorization by current models also creates a marked difference in result quality between domains based on the degree of coverage provided by the incorporated information.

The example KBRM system100employs a method wherein a vast majority of the information required for its functionality resides in an adjacent, tightly integrated, structured Knowledge Base (KB) (e.g., Deep Knowledge Base108). The example KBRM system100is a self-contained model with a few key components—the example Neural Network (NN)104, its corresponding Deep Knowledge Base (KB)108, example reasoned extraction circuitry106, example knowledge acquisition circuitry110, example indexed handles112, example retrieval circuitry114, and an example External Information Corpus116. The example KBRM system100construct results in substantial NN model size reduction, better extensibility and robustness, a path to localization of information and new domains, enhanced explainability, and improved power/performance in both training and inference for information-rich workloads.

The KBRM system100accepts an example input102(e.g., image, query, time series, etc.) into the example Neural Network (NN)104. The Neural Network (NN)104extracts only the needed information from the Deep Knowledge Base (KB)108in order to address this specific input102and product an example output118. However, in examples disclosed herein, if the Deep KB108does not already contain the information necessary to produce the intended output118, the NN104works in conjunction with the example reasoned extraction circuitry106, the example Deep KB108, the example knowledge acquisition circuitry110, the example indexed handles112, the example retrieval circuitry114, and/or the example External Information Corpus116to generate the desired output118.

The Deep KB108is the repository of the information used by the KBRM system100, and the NN104, in particular. In examples disclosed herein, the Deep KB108will most commonly be represented as a Knowledge Graph (KG) but can also be other structured information representations, such as a table or a relational database. In examples disclosed herein, information stored within the Deep KB108will include the relevant basic elements (such as relevant nouns, verbs, and adjectives), as well as applicable relationships between elements, and a hierarchical set of classes/abstractions. In examples disclosed herein, if deemed necessary for the target workload and/or the received input102, the Deep KB108may also include relevant Knowledge Representation (KR) constructs such as declarative knowledge, contextual information, and causality models. The information stored within the Deep KB108is aggregated and sorted from multiple resources, consolidating all relevant information (e.g., information across all sources related to a particular entity—like ‘Charles Darwin’—will be linked to the representation of that entity). In examples disclosed herein, the information stored within the Deep KB108can also be enhanced and/or augmented through successive Machine Learning (ML) iterations. Additionally, in examples disclosed herein, all aspects (e.g., information stored therein) of the Deep KB108need to be intelligible and can be reflected in communication as part of an explanation provided by the example reasoned extraction circuitry106.

The example knowledge acquisition circuitry110(explained further in conjunction withFIG. 2) determines whether the required information is presently located in the NN104. If the information is not in the NN104, the knowledge acquisition circuitry110calculates costs for various information extractions paths (e.g., KB extraction path, external corporal extraction path, etc.) and chooses the lowest-cost extraction path to obtain the necessary information. The example reasoned extraction circuitry106creates an accompanying explanation of how the KBRM system100came up with this output (e.g., a visualization of embeddings across layers in the latent space). The example retrieval circuitry114tracks the entities, links, etc. extracted from the Deep KB108to yield the example output118and provides that information to the reasoned extraction circuitry106to enable clear communication of the path used to reach the AI outcome (e.g., output118).

The example external information corpus116represents a collection of information from external sources, or sources other than the present Deep KB108(e.g., Wikipedia, online and/or offline databases, etc.).

The example indexed handles112represent a part of the KBRM system100wherein the collected information is structured for easy access. In current self-contained DL models, wherein all the information from both internal (e.g., KB) and/or external sources is incorporated into the parametric memory, the information needs to be actively available as model parameters for computation. The algorithmic time complexity of a self-contained DL model that incorporates all information in its parametric memory is estimated to be greater than O(n), due to the combined effect of including the n information elements, as well as cross-relationships between the information elements. In contrast, in examples disclosed herein, the algorithmic time complexity of the example KBRM system100is expected to be O(log n). In examples disclosed herein, the structured information (entities, facts, concepts, relationships) in the KBRM system100resides in the memory of the Deep KB108and is only addressed associatively per need. Additionally, in examples disclosed herein, the algorithmic time complexity is expected to have an upper bound of O(log n), with opportunities to lower it using applicable hashing and indexing techniques, such as those included in the indexed handles112.

The key role of the NN104within the example KBRM system100is to learn the functionality and operations required for delivering the AI task results, and the ability to extract required per-query information from the Deep KB108. In examples disclosed herein, the NN104is to perform functions and/or skills. When the ratio of function (operations) volume to all Model Information is very large (e.g., 1:1000), it will benefit the effectiveness of the model to retrieve information from an adjacent Deep KB108, rather than incorporate it in its parametric memory. The KBRM system100approach of separating function from information is expected to be applicable when the semantic space addressable by the workload is large (e.g., in Natural Language Processing (NLP), Visual Scene Understanding and advanced QnA). In contrast, this separation is not recommended for tasks with a low ratio of Function to Model Information such as in syntactic analysis (e.g., named-entity-recognition or part-of-speech tagging).

The exclusion of most of the information from the NN model104is expected to yield very substantial reduction in the size of the NN model compared with other self-contained approaches. In examples disclosed herein, it is projected that in some data-rich domains where the distribution of information is very wide, the model reduction could reach 100× or more. This reduction will be achieved on top of other optimization methods such as sparsity, compression, or quantization which address gross model inefficiencies but are limited by the need to keep all the information required for inference within the parametric memory.

In the example KBRM system100, the embedding and mapping functions included in the indexed handles112and the retrieval circuitry114are associated primarily with classes (or abstractions) rather than particular individual objects. The NN104is trained to handle classes with the ability to pull in the particular instances. For example, in dealing with U.S. history, the KBRM system100should effectively address the concepts of State (as a class including Texas, Nevada, Idaho, etc.), of State Governor (as a class including ‘James Richard Perry’ and ‘Arnold Schwarzenegger’), and of calendar dates (e.g., 2000, 2001). Given a subset of the information (e.g., ‘Texas’ and ‘James R. Perry’), it can complete the rest (e.g., the year ‘2000’ to the year ‘2015’ in which Perry was the governor of Texas). In that sense, the latent space is parametrized—i.e., it includes “variable” placeholders (such as a class/generalization/abstraction related to individual entities) that guide the utilization of the particular information that is retrieved from the Deep KB108on-the-fly per query.

FIG. 2is a block diagram of an example implementation of the knowledge acquisition circuitry110ofFIG. 1, to operate within the example KBRM system100and in conjunction with at least the example external information corpus116and the example deep knowledge base108. The example knowledge acquisition circuitry110includes an example known information retrieval circuitry205, an example extraction cost estimating circuitry210, an example extraction path activating circuitry215, an example selected source information retrieval circuitry220, an example knowledge base augmenting circuitry225, and an example knowledge base organizing circuitry230.

The example known information retrieval circuitry205extracts the information and/or objects needed from the example input102ofFIG. 1to query the model and obtain the information (e.g., from the external information corpus116and/or the Deep KB108ofFIG. 1) to be output as a final result (e.g., output118ofFIG. 1). Once object extraction from the input102has been completed, the known information retrieval circuitry205then queries the model (e.g., NN104fromFIG. 1) and retrieves the desired information from the model if it exists within the model (e.g., the query results in a hit).

In some examples, the knowledge acquisition circuitry110ofFIGS. 1 and/or 2includes means for extracting objects from input, querying a model for information, and retrieving the information from the model if it exists. For example, the means for extracting objects from input, querying a model for information, and retrieving the information from the model if it exists may be implemented by the known information retrieval circuitry205. In some examples, the known information retrieval circuitry205may be implemented by machine executable instructions such as that implemented by at least blocks702,704,706,708ofFIG. 7and block605ofFIG. 6executed by processor circuitry, which may be implemented by the example processor circuitry912ofFIG. 9, the example processor circuitry1000ofFIG. 10, and/or the example Field Programmable Gate Array (FPGA) circuitry1100ofFIG. 11. In other examples, the known information retrieval circuitry205is implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the known information retrieval circuitry205may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

The example extraction cost estimating circuitry210calculates the costs (e.g., runtime cost) associated with retrieving the information, deemed by the known information retrieval circuitry205to be missing from the model, from both the external information corpus116and the Deep KB108ofFIG. 1.

In some examples, the knowledge acquisition circuitry110ofFIGS. 1 and/or 2includes means for estimating costs associated with extracting desired information from external corpora and the internal knowledge base. For example, the means for estimating costs associated with extracting desired information from external corpora and the internal knowledge base may be implemented by the extraction cost estimating circuitry210. In some examples, the extraction cost estimating circuitry210may be implemented by machine executable instructions such as that implemented by at least blocks710,712ofFIG. 7executed by processor circuitry, which may be implemented by the example processor circuitry912ofFIG. 9, the example processor circuitry1000ofFIG. 10, and/or the example Field Programmable Gate Array (FPGA) circuitry1100ofFIG. 11. In other examples, the extraction cost estimating circuitry210is implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the extraction cost estimating circuitry210may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

The example extraction path activating circuitry215sorts the estimated extraction costs generated by the extraction costs generating circuitry210and determines the information source with the lowest associated retrieval cost. In examples disclosed herein, the extraction path activating circuitry215sorts the list of estimated extraction costs in ascending order and selects the first information source and its associated extraction cost in the sorted list. However, in other examples, the extraction path activating circuitry215may sort the list of estimated extraction costs in descending order, etc. to determine the information source associated with the lowest retrieval cost.

In some examples, the knowledge acquisition circuitry110ofFIGS. 1 and/or 2includes means for determining an information source with a lowest associated extraction. For example, the means for means for determining an information source with a lowest associated extraction cost may be implemented by extraction path activating circuitry215. In some examples, the extraction path activating circuitry215may be implemented by machine executable instructions such as that implemented by at least blocks714,716,718,720ofFIG. 7executed by processor circuitry, which may be implemented by the example processor circuitry912ofFIG. 9, the example processor circuitry1000ofFIG. 10, and/or the example Field Programmable Gate Array (FPGA) circuitry1100ofFIG. 11. In other examples, the extraction path activating circuitry215is implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the extraction path activating circuitry215may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

The example selected source information retrieval circuitry220receives the identified information source with the lowest extraction cost from the extraction path activating circuitry210and queries the selected source for the desired information.

In some examples, the knowledge acquisition circuitry110ofFIGS. 1 and/or 2includes means for receiving an identified information source with a lowest associated extraction cost and querying the selected source for desired information. For example, the means for receiving an identified information source with a lowest associated extraction cost and querying the selected source for desired information may be implemented by selected source information retrieval circuitry220. In some examples, the selected source information retrieval circuitry220may be implemented by machine executable instructions such as that implemented by at least blocks722,724,726,728ofFIG. 7executed by processor circuitry, which may be implemented by the example processor circuitry912ofFIG. 9, the example processor circuitry1000ofFIG. 10, and/or the example Field Programmable Gate Array (FPGA) circuitry1100ofFIG. 11. In other examples, the selected source information retrieval circuitry220is implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the selected source information retrieval circuitry220may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

The example knowledge base augmenting circuitry225determines whether the intended information (e.g., result) was retrieved from an external source. If so, the knowledge base augmenting circuitry225stores the object information in the knowledge base (e.g., Deep KB108ofFIG. 1) of the model (e.g., NN104ofFIG. 1).

In some examples, the knowledge acquisition circuitry110ofFIGS. 1 and/or 2includes means for determining whether the retrieved result was obtained from an external information source, and in response to establishing that it was, storing the retrieved object information in the knowledge base. For example, the means for determining whether the retrieved result was obtained from an external information source, and in response to establishing that it was, storing the retrieved object information in the knowledge base may be implemented by knowledge base augmenting circuitry225. In some examples, the knowledge base augmenting circuitry225may be implemented by machine executable instructions such as that implemented by at least blocks730,732ofFIG. 7executed by processor circuitry, which may be implemented by the example processor circuitry912ofFIG. 9, the example processor circuitry1000ofFIG. 10, and/or the example Field Programmable Gate Array (FPGA) circuitry1100ofFIG. 11. In other examples, the knowledge base augmenting circuitry225is implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the knowledge base augmenting circuitry225may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

The example knowledge base organizing circuitry230structures the newly-added information in the knowledge base (e.g., Deep KB108ofFIG. 1) of the model, using algorithms such as caching, indexing, hashing, etc. in order to provide a structure for the information contained therein.

In some examples, the knowledge acquisition circuitry110ofFIGS. 1 and/or 2includes means for structuring the newly-added information in the knowledge base for easy access. For example, the means for structuring the newly-added information in the knowledge base for easy access may be implemented by knowledge base organizing circuitry230. In some examples, the knowledge base organizing circuitry230may be implemented by machine executable instructions such as that implemented by at least blocks734,736ofFIG. 7executed by processor circuitry, which may be implemented by the example processor circuitry912ofFIG. 9, the example processor circuitry1000ofFIG. 10, and/or the example Field Programmable Gate Array (FPGA) circuitry1100ofFIG. 11. In other examples, the knowledge base organizing circuitry230is implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the knowledge base organizing circuitry230may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

FIG. 3is a block diagram illustrating Neural Network training and Knowledge-Based co-optimization, implemented in accordance with the teachings of this disclosure and the KBRM system100ofFIG. 1.

The example NN training system300includes an example training data set302and an example test data set304, and the example refactored neural network (NN)104, the external information corpus116, the deep knowledge base (KB)108, and the output118ofFIG. 1.

Preparation of the KBRM system100ofFIG. 1requires a combined refactored NN104training and deep KB108enhancement. In examples disclosed herein, the deep KB108includes both specific facts and relations as well as their classes and abstractions. Training is strongly guided to identify and learn classes/abstractions, plus the ability to extract the particular instances from the deep KB108. For example, when provided with a question “When was Perry the governor of Texas?” as input (e.g., input102ofFIG. 1), the refactored NN104should parse the question, identify ‘Perry’ as the entity ‘James R. Perry’, ‘Texas’ as a US State, and ‘governor’ as a political post. The NN104learns to complete the rest (e.g., the start year as ‘2000’ and end year as ‘2015’) from the deep KB108.

The deep KB108is generated from and/or trained using larger sources of information, be it an unstructured source (like plaintext Wikipedia), a structured source (like ConceptNet or WikiData), or extracted out of parametric language models (e.g., COMET). During the preparation and/or training of the NN104model, the deep KB108will be enhanced to create a complete ontology of the known target domains with emphasis on classes, abstractions and relationships. In examples disclosed herein, the deep KB108does not need to contain a complete set of data reflecting the domains during inference, but rather all the classes, abstractions and relationships that are required to train the refactored NN104model functions.

In examples disclosed herein, training of both the refactored NN104and/or the deep KB108utilizes a retrieval scheme and an information source that corresponds to the retrieval and information source that will be used during inference (e.g., deep KB108, external information corpus116). The refactored NN104is trained to maintain an ability to function on abstractions and on retrieval of the appropriate specific values. In examples disclosed herein, however, the training environment does not need to include all the data that will be used during inference.

During inference, the refactored NN104and deep KB108operate in tandem, with the refactored NN104applying the learned functionality and mapping, and the deep KB108providing all the needed particulars. As long as the functions and tasks are similar, new information in the deep KB108can be processed effectively, regardless of its presence in the training data set302. For example, in examples disclosed herein, if the deep KB108is provided information about states in Mexico and their respective governors, the KBRM system100ofFIG. 1can effectively provide information on ‘Jaime Bonilla Valdez’ as the governor of ‘Baja California’ even if Mexico's information was not present during training and was only made available during inference.

FIG. 4is a block diagram of an example configuration of a hardware-accelerated KBRM system400. The example hardware-accelerated KBRM system400includes an example caching module408, an example hashing and/or associative retrieval module410, and an example explanation416, and the input102, the reasoned extraction circuitry106, the deep knowledge base (KB)108, the example refactored neural network (NN)104, and the example output118ofFIG. 1.

Refactoring of the NN model104shifts most of the information outside the model (non-parametric memory) to be retrieved during inference. This substantially reduces the NN104model size for data-rich domains and shifts cycles and value from massive tensor structures to integrated retrieval systems. The compute and power efficiency of a KBRM system (e.g., KBRM system100, hardware-accelerated KBRM system400) is dependent on efficient per-query associative access and retrieval from an arbitrarily large memory. The level of overall optimization between algorithm, software (SW), and hardware (HW) plays a major role in the efficiency of the system during inference. The mix of types of compute between scalar, vector and tensor operations is much more balanced than in current large DL non-factored models and therefore stands to benefit from a CPU, XPU and memory-optimized system solution.

Further optimization of performance is achieved by an efficient associative access mechanism, using hashing techniques, such as the hashing and/or associative retrieval module410. Due to the locality of information in many expected usages, the caching module408provides high value by bringing data closer to the NN104for subsequent retrievals in a similar area of the deep KB1080. In examples disclosed herein, leveraging similarity-based extraction from persistent memory (e.g., Optane) provides stable physical access and therefore reduces latency and reducing power consumption.

The reasoned extraction circuitry106within the hardware-accelerated KBRM system400provides an optional output of explanation416, providing information regarding information retrieval paths, etc.

FIG. 5is a table500illustrating a comparison of features of the KBRM system100ofFIG. 1with that of previous approaches. The table500includes previous approaches such as Retrieval-Augmented Generation (RAG)504, Entities as Experts (EaE)506, Efficient-Bidirectional Encoder Representations from Transformers (E-BERT)508, k-Nearest Neighbor Language Model (kNN-LM)510, and ERNIE512.

Retrieval-Augmented Generation (RAG)504uses Dense Passage Retrieval (DPR) to retrieve the top-K matches from Wikipedia passages for a query. The input query, as well as the Wikipedia passages, are represented through dense embeddings created by transformer models, and the product of these embeddings is used as a similarity scoring function. The text of the retrieved passages is used as additional context by a generative Language Model (LM) (e.g., BERT) to answer the query.

Entities as Experts (EaE)506introduces a concept of entity memories within the transformer model architecture. Along with the standard token vocabulary of 30,000 tokens (similar to BERT), EaE also has a 1 million entity vocabulary. The embeddings of the entities and their retrieval from the entity memory is trained along with the full transformer model.

E-BERT508introduces entity embeddings from an external source (e.g., Wikipedia2vec) and aligns these entity vectors with BERT's WordPiece vectors at the beginning of BERT.

k-Nearest Neighbor Language Model (kNN-LM)510introduces an additional component to a language model, which involves retrieval of the k most similar contexts from a datastore along with corresponding targets. Instead of re-training on new data, embeddings of new contexts and targets are created which can be added to the datastore, which can then be retrieved at inference time.

ERNIE512introduces a knowledge encoder on top of a textual encoder which is identical to BERT. In the knowledge encoder, information fusion takes place between token embeddings and entity embeddings which are obtained from a Knowledge Graph (KG).

The first row516of the table500includes the design feature of a self-contained system which includes a tightly integrated NN (e.g., NN104ofFIG. 1), KB (e.g., deep KB108ofFIG. 1), and R&E module (e.g., reasoned extraction circuitry106ofFIG. 1). As shown in the table500, RAG504, EaE506, E-BERT508, kNN-LM510, and ERNIE512do not possess such a design solution, however, the KBRM system100does.

The second row518describes the design feature of a KB that incorporates information aggregated and consolidated from multiple sources in a structured knowledge graph (KG) of data elements, relationships, etc. between elements and classes and/or abstractions. As shown in the table500, RAG504, EaE506, E-BERT508, kNN-LM510, and ERNIE512do not possess such a design solution, however, the KBRM system100does.

The third row520of the table500describes the design feature of having a vast majority of model information reside in the KB, rather than the NN. As shown in the table500, RAG504, EaE506, E-BERT508, kNN-LM510, and ERNIE512do not possess such a design solution, however, the KBRM system100does.

The fourth row522of the table500describes the design feature of a KB that can include new and/or additional information during inference. As shown in the table500, EaE506, E-BERT508, and ERNIE512do not possess such a design solution, however, RAG504, kNN-LM510, and the KBRM system100do.

The fifth row524of the table500describes the design feature of an NN that is trained together with its KB, focusing on learning at the highest abstraction (most general) level available at the KB. As shown in the table500, RAG504, EaE506, E-BERT508, kNN-LM510, and ERNIE512do not possess such a design solution, however, the KBRM system100does.

The sixth row526of the table500describes the design feature of an NN that extracts specifics (e.g., data items, relationships attributes, etc.) from the KB for each forward propagation (F-PROP) in both training and inference stages. As shown in the table500, RAG504, EaE506, E-BERT508, kNN-LM510, and ERNIE512do not possess such a design solution, however, the KBRM system100does.

The seventh row528of the table500describes the design feature of an explainability (“R&E”) module (e.g., reasoned extraction circuitry106ofFIG. 1), module that tracks and reports out the particular information and KB path used per inference. As shown in the table500, EaE506, E-BERT508, kNN-LM510, and ERNIE512do not possess such a design solution, however, RAG504and the KBRM system100do.

The eighth row530of the table500describes the design feature of a tuned hardware (HW) architecture that greatly improves latency and power per query (e.g., F-PROP) through integration of large associative memory, hashing for efficient physical access, and caching for rapid access to related information. As shown in the table500, RAG504, EaE506, E-BERT508, kNN-LM510, and ERNIE512do not possess such a design solution, however, the KBRM system100does.

While an example manner of implementing the knowledge acquisition circuitry110ofFIG. 1is illustrated inFIG. 2, one or more of the elements, processes and/or devices illustrated inFIG. 2may be combined, divided, re-arranged, omitted, eliminated and/or implemented in any other way. Further, the example known information retrieval circuitry205, example extraction cost estimating circuitry210, example extraction path activating circuitry215, example selected source information retrieval circuitry220, example knowledge base augmenting circuitry225, example knowledge base organizing circuitry230, and/or, more generally, the example knowledge acquisition circuitry110fFIG. 1may be implemented by hardware, software, firmware and/or any combination of hardware, software and/or firmware. Thus, for example, any of the example known information retrieval circuitry205, example extraction cost estimating circuitry210, example extraction path activating circuitry215, example selected source information retrieval circuitry220, example knowledge base augmenting circuitry225, example knowledge base organizing circuitry230and/or, more generally, the example knowledge acquisition circuitry110ofFIG. 1could be implemented by one or more analog or digital circuit(s), logic circuits, programmable processor(s), programmable controller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)) and/or field programmable logic device(s) (FPLD(s)). When reading any of the apparatus or system claims of this patent to cover a purely software and/or firmware implementation, at least one of the the example known information retrieval circuitry205, example extraction cost estimating circuitry210, example extraction path activating circuitry215, example selected source information retrieval circuitry220, example knowledge base augmenting circuitry225, and example knowledge base organizing circuitry230is/are hereby expressly defined to include a non-transitory computer readable storage device or storage disk such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc. including the software and/or firmware. Further still, the example knowledge acquisition circuitry110may include one or more elements, processes and/or devices in addition to, or instead of, those illustrated inFIG. 2, and/or may include more than one of any or all of the illustrated elements, processes and devices. As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.

FIG. 6is a flowchart representative of example machine readable instructions and/or example operations600that may be executed and/or instantiated by processor circuitry to access a query, gather object information, provide results, and output explainability information. The machine readable instructions and/or operations600ofFIG. 6begin at block605, at which the known information retrieval circuitry205access the query for extraction.

As illustrated inFIG. 6, at block605, the known information retrieval circuitry205accesses the query (e.g., input102fromFIG. 1) for extraction. From the query, the known information retrieval circuitry205extracts information needed to produce the query result. For example, when provided with the question “When was Perry the governor of Texas?” as input (e.g., input102ofFIG. 1), the known information retrieval circuitry205parses the question and extracts and/or identifies ‘Perry’ as the entity ‘James R. Perry’, ‘Texas’ as a US State, and ‘governor’ as a political post.

At block610, the knowledge acquisition circuitry110ofFIG. 1gathers object information from an information source (e.g., NN model104, deep KB108, external information corpus116). An example process for gathering object information is described in conjunction withFIG. 7.

At block615, the selected source information retrieval circuitry220provides the results of the object information gathered by the knowledge acquisition circuitry110of block610.

At block620, the reasoned extraction circuitry106ofFIG. 1provides explainability information, including the particular information and knowledge base (KB) path used for each inference.

FIG. 7is a flowchart representative of example machine readable instructions and/or example operations which may be executed to implement block610ofFIG. 6to gather information from the knowledge base (KB).

As illustrated inFIG. 7, at block702, the known information retrieval circuitry205extract objects from the input (e.g., input102ofFIG. 1) in order to determine which information is needed to supply an answer. For example, when provided with the question “When was Perry the governor of Texas?” as input (e.g., input102ofFIG. 1), the known information retrieval circuitry205parses the question and extracts and/or identifies ‘Perry’ as the entity ‘James R. Perry’, ‘Texas’ as a US State, and ‘governor’ as a political post.

At block704, the known information retrieval circuitry205queries the model (e.g., NN model104ofFIG. 1) to check if the desired information is stored therein. If the known information retrieval circuitry205determines that the desired information is stored within the NN, the process moves forward to block706. However, if the known information retrieval circuitry205establishes that the desired information is not located within the NN, the process moves to block710.

At block706, after determining that the desired information is stored within the NN, the known information retrieval circuitry205retrieves the information from the neural network (e.g., NN104fromFIG. 1).

At block708, the known information retrieval circuitry205checks whether the desired result was achieved (e.g., an answer to the input query is ready to be output). If the known information retrieval circuitry205establishes that the desired result was achieved, the process moves to block736. However, if the known information retrieval circuitry205determines that the desired result was not achieved, the process moves to block710.

At block710, the extraction cost estimating circuitry210estimates the information extraction cost from the knowledge base (e.g., deep KB108ofFIG. 1). In examples disclosed herein, the extraction cost estimating circuitry210estimates the information extraction cost from the knowledge base by estimating an expected amount of retrieval time for information from the knowledge base (e.g., a temporal cost). However, in other examples, any other type of cost estimation could additionally or alternatively be used (e.g., an amount of computational resources used to obtain the requested information from the knowledge base).

At block712, the extraction cost estimating circuitry210estimates the information extraction cost from external corpora (e.g., external information corpus116ofFIG. 1). In examples disclosed herein, the extraction cost estimating circuitry210estimates the information extraction cost from external corpora by estimating an expected amount of retrieval time for information from the external corpora (e.g., a temporal cost). However, in other examples, any other type of cost estimation could additionally or alternatively be used (e.g., an amount of computational resources used to obtain the requested information from the external corpora).

At block714, the extraction path activating circuitry215sorts the list of estimated costs calculated by the extraction cost estimating circuitry210and associated with each possible extraction path (e.g., path from KB, path from external corpora). In examples disclosed herein, the list of estimated costs and their associated information sources are sorted in ascending and/or descending order, with the information source yielding the lowest extraction cost being the most desirable.

At block716, the extraction path activating circuitry215determines whether the list of possible information sources is empty. If the extraction path activating circuitry215determines that the list of information sources is empty, the process moves to block718. However, if the extraction path activating circuitry215establishes that the list of information sources is not empty, the process moves forward to block720.

At block718, the extraction path activating circuitry215returns an indication of no result, since the list of possible information sources wherein the desired information could be gathered has been determined to be empty.

At block720, the extraction path activating circuitry215parses the list of information sources, sorted by their respective extraction costs and selects an information source. In examples disclosed herein, the information source with the lowest associated retrieval cost (i.e., extraction cost) is selected. However, the selection may be based on any other criteria such as, for example, a veracity of the information source. For example, information sources with information more likely to be true may be selected over information sources that are more prone to false information.

At block722, the selected source information retrieval circuitry220the selected information source (as determined by the extraction path activating circuitry215) is queried to gather the desired information.

At block724, the selected source information retrieval circuitry220determines, similar to block708, whether the desired query result was achieved. If the selected source information retrieval circuitry220establishes that the desired result was achieved, the process moves forward to block728. However, if the selected source information retrieval circuitry220determines that the desired result was not achieved, the process moves to block726.

At block726, the selected source information retrieval circuitry220removes the selected source from the list of available information sources and their associated extraction costs and proceeds back to block716wherein the extraction path activating circuitry215checks if the list of information sources wherein the desired information may be contained is empty.

At block728, the selected source information retrieval circuitry220determines whether the desired result, as queried and obtained by the selected source information retrieving circuitry220in blocks722and744, was retrieved from a remote source (e.g., external information corpus116ofFIG. 1).

At block730, the knowledge base augmenting circuitry225determines whether the collected object information is to be retained in the knowledge base of the model. If the knowledge base augmenting circuitry225establishes that the newly-gathered object information is to be retained, the process moves forward to block732. However, if the knowledge base augmenting circuitry225determines that the collected object information is not to be retained in the local knowledge base, the process moves to block736.

At block732, the knowledge base augmenting circuitry225stores the gathered object information in the knowledge base (e.g., deep KB108ofFIG. 1).

At block734, the knowledge base organizing circuitry230organizes and/or structures the newly-gathered information using a variety of organizational algorithms (e.g., hashing, caching, indexing, etc.) in order to promote easy access during future use.

At block736, the knowledge base organizing circuitry230returns the result of the query (e.g., information gathered in response to input). In examples disclosed herein, the result includes the answer to the input query along with an explanation of how the result was achieved (e.g., information extraction path).

The processor platform800of the illustrated example includes processor circuitry825. The processor circuitry825of the illustrated example is hardware. For example, the processor circuitry825can be implemented by one or more integrated circuits, logic circuits, FPGAs microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The processor circuitry825may be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, the processor circuitry825implements the example knowledge acquisition circuitry110, including the example known information retrieval circuitry205, the example extraction cost estimating circuitry210, the example extraction path activating circuitry215, the example selected source information retrieval circuitry220, the example knowledge base augmenting circuitry225, and the example knowledge base organizing circuitry230.

The processor circuitry825of the illustrated example includes a local memory805(e.g., a cache, registers, etc.). The processor circuitry825of the illustrated example is in communication with a main memory including a volatile memory815and a non-volatile memory820by a bus830. The volatile memory815may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. The non-volatile memory820may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory815,820of the illustrated example is controlled by a memory controller817.

The processor platform800of the illustrated example also includes interface circuitry845. The interface circuitry845may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a PCI interface, and/or a PCIe interface.

In the illustrated example, one or more input devices840are connected to the interface circuitry845. The input device(s)840permit(s) a user to enter data and/or commands into the processor circuitry825. The input device(s)840can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system.

One or more output devices850are also connected to the interface circuitry845of the illustrated example. The output devices850can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, and/or speaker. The interface circuitry845of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip, and/or graphics processor circuitry such as a GPU.

The processor platform800of the illustrated example also includes one or more mass storage devices835to store software and/or data. Examples of such mass storage devices835include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid state storage devices such as flash memory devices, and DVD drives.

The machine executable instructions805, which may be implemented by the machine readable instructions ofFIGS. 6-7, may be stored in the mass storage device835, in the volatile memory815, in the non-volatile memory820, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.

FIG. 9is a block diagram of an example implementation of the processor circuitry825ofFIG. 8. In this example, the processor circuitry825ofFIG. 8is implemented by a microprocessor900. For example, the microprocessor900may implement multi-core hardware circuitry such as a CPU, a DSP, a GPU, an XPU, etc. Although it may include any number of example cores902(e.g., 1 core), the microprocessor900of this example is a multi-core semiconductor device including N cores. The cores902of the microprocessor900may operate independently or may cooperate to execute machine readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores902or may be executed by multiple ones of the cores902at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more of the cores902. The software program may correspond to a portion or all of the machine readable instructions and/or operations represented by the flowchart ofFIGS. 6-7.

The cores902may communicate by an example first bus904. In some examples, the first bus904may implement a communication bus to effectuate communication associated with one(s) of the cores902. For example, the first bus904may implement at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus904may implement any other type of computing or electrical bus. The cores902may obtain data, instructions, and/or signals from one or more external devices by example interface circuitry906. The cores902may output data, instructions, and/or signals to the one or more external devices by the interface circuitry906. Although the cores902of this example include example local memory920(e.g., Level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessor900also includes example shared memory910that may be shared by the cores (e.g., Level 2 (L2_cache)) for high-speed access to data and/or instructions. Data and/or instructions may be transferred (e.g., shared) by writing to and/or reading from the shared memory910. The local memory920of each of the cores902and the shared memory910may be part of a hierarchy of storage devices including multiple levels of cache memory and the main memory (e.g., the main memory815,820ofFIG. 8). Typically, higher levels of memory in the hierarchy exhibit lower access time and have smaller storage capacity than lower levels of memory. Changes in the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.

Each core902may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core902includes control unit circuitry914, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU)916, a plurality of registers918, the L1 cache920, and an example bus922. Other structures may be present. For example, each core902may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load/store unit (LSU) circuitry, branch/jump unit circuitry, floating-point unit (FPU) circuitry, etc. The control unit circuitry914includes semiconductor-based circuits structured to control (e.g., coordinate) data movement within the corresponding core902. The AL circuitry916includes semiconductor-based circuits structured to perform one or more mathematic and/or logic operations on the data within the corresponding core902. The AL circuitry916of some examples performs integer based operations. In other examples, the AL circuitry916also performs floating point operations. In yet other examples, the AL circuitry916may include first AL circuitry that performs integer based operations and second AL circuitry that performs floating point operations. In some examples, the AL circuitry916may be referred to as an Arithmetic Logic Unit (ALU). The registers918are semiconductor-based structures to store data and/or instructions such as results of one or more of the operations performed by the AL circuitry916of the corresponding core902. For example, the registers918may include vector register(s), SIMD register(s), general purpose register(s), flag register(s), segment register(s), machine specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. The registers918may be arranged in a bank as shown inFIG. 9. Alternatively, the registers918may be organized in any other arrangement, format, or structure including distributed throughout the core902to shorten access time. The second bus922may implement at least one of an I2C bus, a SPI bus, a PCI bus, or a PCIe bus

FIG. 10is a block diagram of another example implementation of the processor circuitry825ofFIG. 8. In this example, the processor circuitry825is implemented by FPGA circuitry1000. The FPGA circuitry1000can be used, for example, to perform operations that could otherwise be performed by the example microprocessor900ofFIG. 9executing corresponding machine readable instructions. However, once configured, the FPGA circuitry1000instantiates the machine readable instructions in hardware and, thus, can often execute the operations faster than they could be performed by a general purpose microprocessor executing the corresponding software.

In the example ofFIG. 10, the FPGA circuitry1000is structured to be programmed (and/or reprogrammed one or more times) by an end user by a hardware description language (HDL) such as Verilog. The FPGA circuitry1000ofFIG. 10, includes example input/output (I/O) circuitry1002to obtain and/or output data to/from example configuration circuitry1004and/or external hardware (e.g., external hardware circuitry)1006. For example, the configuration circuitry1004may implement interface circuitry that may obtain machine readable instructions to configure the FPGA circuitry1000, or portion(s) thereof. In some such examples, the configuration circuitry1004may obtain the machine readable instructions from a user, a machine (e.g., hardware circuitry (e.g., programmed or dedicated circuitry) that may implement an Artificial Intelligence/Machine Learning (AI/ML) model to generate the instructions), etc. In some examples, the external hardware1006may implement the microprocessor900ofFIG. 9. The FPGA circuitry1000also includes an array of example logic gate circuitry1008, a plurality of example configurable interconnections1010, and example storage circuitry1012. The logic gate circuitry1008and interconnections1010are configurable to instantiate one or more operations that may correspond to at least some of the machine readable instructions ofFIGS. 6-7and/or other desired operations. The logic gate circuitryl008shown inFIG. 10is fabricated in groups or blocks. Each block includes semiconductor-based electrical structures that may be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., And gates, Or gates, Nor gates, etc.) that provide basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the logic gate circuitry1008to enable configuration of the electrical structures and/or the logic gates to form circuits to perform desired operations. The logic gate circuitry1008may include other electrical structures such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

The storage circuitry1012of the illustrated example is structured to store result(s) of the one or more of the operations performed by corresponding logic gates. The storage circuitry1012may be implemented by registers or the like. In the illustrated example, the storage circuitry1012is distributed amongst the logic gate circuitry1008to facilitate access and increase execution speed.

The example FPGA circuitry1000ofFIG. 10also includes example Dedicated Operations Circuitry1014. In this example, the Dedicated Operations Circuitry1014includes special purpose circuitry1016that may be invoked to implement commonly used functions to avoid the need to program those functions in the field. Examples of such special purpose circuitry1016include memory (e.g., DRAM) controller circuitry, PCIe controller circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special purpose circuitry may be present. In some examples, the FPGA circuitry1000may also include example general purpose programmable circuitry1018such as an example CPU1020and/or an example DSP1022. Other general purpose programmable circuitry1018may additionally or alternatively be present such as a GPU, an XPU, etc., that can be programmed to perform other operations.

AlthoughFIGS. 9 and 10illustrate two example implementations of the processor circuitry825ofFIG. 8, many other approaches are contemplated. For example, as mentioned above, modern FPGA circuitry may include an on-board CPU, such as one or more of the example CPU1020ofFIG. 10. Therefore, the processor circuitry825ofFIG. 8may additionally be implemented by combining the example microprocessor900ofFIG. 9and the example FPGA circuitry1000ofFIG. 10. In some such hybrid examples, a first portion of the machine readable instructions represented by the flowcharts ofFIGS. 6-7may be executed by one or more of the cores902ofFIG. 9and a second portion of the machine readable instructions represented by the flowcharts ofFIGS. 6-7may be executed by the FPGA circuitry1000ofFIG. 10.

In some examples, the processor circuitry825ofFIG. 8may be in one or more packages. For example, the processor circuitry900ofFIG. 9and/or the FPGA circuitry1000ofFIG. 10may be in one or more packages. In some examples, an XPU may be implemented by the processor circuitry825ofFIG. 8, which may be in one or more packages. For example, the XPU may include a CPU in one package, a DSP in another package, a GPU in yet another package, and an FPGA in still yet another package.

A block diagram illustrating an example software distribution platform1105to distribute software such as the example machine readable instructions1132ofFIG. 11to hardware devices owned and/or operated by third parties is illustrated inFIG. 11. The example software distribution platform1105may be implemented by any computer server, data facility, cloud service, etc., capable of storing and transmitting software to other computing devices. The third parties may be customers of the entity owning and/or operating the software distribution platform1105. For example, the entity that owns and/or operates the software distribution platform1105may be a developer, a seller, and/or a licensor of software such as the example machine readable instructions represented by the flowcharts ofFIGS. 6-7. The third parties may be consumers, users, retailers, OEMs, etc., who purchase and/or license the software for use and/or re-sale and/or sub-licensing. In the illustrated example, the software distribution platform1105includes one or more servers and one or more storage devices. The storage devices store the machine readable instructions1132, which may correspond to the example machine readable instructions represented by the flowcharts ofFIGS. 6-7, as described above. The one or more servers of the example software distribution platform1105are in communication with a network1110, which may correspond to any one or more of the Internet and/or any of the example networks described above. In some examples, the one or more servers are responsive to requests to transmit the software to a requesting party as part of a commercial transaction. Payment for the delivery, sale, and/or license of the software may be handled by the one or more servers of the software distribution platform and/or by a third party payment entity. The servers enable purchasers and/or licensors to download the machine readable instructions1132from the software distribution platform1105. For example, the software, which may correspond to the example machine readable instructions represented by the flowcharts ofFIGS. 6-7may be downloaded to the example processor platform1100, which is to execute the machine readable instructions1132to implement the knowledge acquisition circuitry110ofFIGS. 1 and/or 2. In some example, one or more servers of the software distribution platform1105periodically offer, transmit, and/or force updates to the software (e.g., the example machine readable instructions1132ofFIG. 11) to ensure improvements, patches, updates, etc., are distributed and applied to the software at the end user devices.

Example methods, apparatus, systems, and articles of manufacture for a knowledge-based deep learning refactoring model with tightly integrated functional nonparametric memory are disclosed herein. Further examples and combinations thereof include the following:

Example 1 includes an apparatus for a knowledge-based deep learning refactoring model comprising interface circuitry, processor circuitry including one or more of at least one of a central processing unit, a graphic processing unit or a digital signal processor, the at least one of the central processing unit, the graphic processing unit or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations according to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus, a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations, or Application Specific Integrated Circuitry (ASIC) including logic gate circuitry to perform one or more third operations, the processor circuitry to perform at least one of the first operations, the second operations or the third operations to instantiate extraction cost estimating circuitry to estimate a first information extraction cost corresponding to retrieval of information from a local knowledge base, the extraction cost estimating circuitry to estimate a second information extraction cost corresponding retrieval of information from a remote knowledge base, extraction path activating circuitry to select an information source based on the first and second estimated information extraction costs, selected source information retrieval circuitry to query the selected information source, and return the queried information, knowledge base augmenting circuitry to in response to a determination that the selected information source was an external information source, store the queried information in the local knowledge base, and knowledge base organizing circuitry to organize the stored information in the local knowledge base.

Example 2 includes the apparatus of example 1, wherein known information retrieval circuitry is to determine whether a result information is stored within a neural network model by querying the neural network model for the result information, and in response to determining that the result information is stored within a neural network model, extract the information from the neural network model.

Example 3 includes the apparatus of example 1, wherein the extraction cost estimating circuitry is to further estimate a third information extraction cost corresponding to retrieval of information from third information source, the third information extraction cost added to a plurality of information costs including one or more of a first and second information extraction cost.

Example 4 includes the apparatus of example 3, wherein extraction path activating circuitry is to further sort the plurality of information extraction costs to determine an information source associated with a minimum information extraction cost of the plurality of information extraction costs.

Example 5 includes the apparatus of example 1, wherein the extraction cost estimating circuitry is to calculate a first and second information extraction cost by estimating an expected amount of retrieval time for information from an information source.

Example 6 includes the apparatus of example 1, wherein the extraction path activating circuitry is to select the information source to be queried based on a minimum associated extraction cost of a sorted plurality of information costs.

Example 7 includes the apparatus of example 1, wherein the knowledge base organizing circuitry is to structure stored information in a local knowledge base using one or more of a hashing, caching, and indexing algorithm.

Example 8 includes the apparatus of example 1, wherein the knowledge base organizing circuitry is further to return explainability information corresponding to an extraction path with the queried information.

Example 9 includes a method to perform information retrieval, the method comprising estimating a first information extraction cost corresponding to retrieval of information from a local knowledge base, estimating a second information extraction cost corresponding retrieval of information from a remote knowledge base, selecting an information source based on the first and second estimated information extraction costs, querying the selected information source, in response to determining that the selected information source was an external information source, storing the queried information in the local knowledge base, organizing the stored information in the local knowledge base, and returning the queried information.

Example 10 includes the method of example 9, further including determining whether a result information is stored within a neural network model by querying the neural network model for the result information, and in response to determining that the result information is stored within a neural network model, extracting the information from the neural network model.

Example 11 includes the method of example 9 further including estimating a third information extraction cost corresponding to retrieval of information from third information source, the third information extraction cost added to a plurality of information costs including one or more of the first and second information extraction costs.

Example 12 includes the method of example 11 further including sorting the plurality of information extraction costs to determine an information source associated with a minimum information extraction cost of the plurality of information extraction costs.

Example 13 includes the method of example 9, wherein the first and second information extraction costs are calculated by estimating an expected amount of retrieval time for information from an information source.

Example 14 includes the method of example 9, wherein the selected information source to be queried has a minimum associated extraction cost of a sorted plurality of information costs.

Example 15 includes the method of example 9, wherein the stored information in the local knowledge base is organized using one or more of a hashing, caching, and indexing algorithm.

Example 16 includes the method of example 9, wherein explainability information corresponding to an extraction path is returned with the queried information.

Example 17 includes a non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least estimate a first information extraction cost corresponding to retrieval of information from a local knowledge base, estimate a second information extraction cost corresponding retrieval of information from a remote knowledge base, select an information source based on the first and second estimated information extraction costs, query the selected information source, in response to determining that the selected information source was an external information source, store the queried information in the local knowledge base, organize the stored information in the local knowledge base, and return the queried information.

Example 18 includes the non-transitory computer readable medium of example 17, further including determining whether a result information is stored within a neural network model by querying the neural network model for the result information, and in response to determining that the result information is stored within a neural network model, extracting the information from the neural network model.

Example 19 includes the non-transitory computer readable medium of example 17, further including estimating a third information extraction cost corresponding to retrieval of information from third information source, the third information extraction cost added to a plurality of information costs including one or more of the first and second information extraction costs.

Example 20 includes the non-transitory computer readable medium of example 19, further including sorting the plurality of information extraction costs to determine an information source associated with a minimum information extraction cost of the plurality of information extraction costs.

Example 21 includes the non-transitory computer readable medium of example 17, wherein the first and second information extraction costs are calculated by estimating an expected amount of retrieval time for information from an information source.

Example 22 includes the non-transitory computer readable medium of example 17, wherein the selected information source to be queried has a minimum associated extraction cost of a sorted plurality of information costs.

Example 23 includes the non-transitory computer readable medium of example 17, wherein the stored information in the local knowledge base is organized using one or more of a hashing, caching, and indexing algorithm.

Example 24 includes the non-transitory computer readable medium of example 17, wherein explainability information corresponding to an extraction path is returned with the queried information.

Example 25 includes an apparatus for a knowledge-based deep learning refactoring model comprising means for estimating a first information extraction cost corresponding to retrieval of information from a local knowledge base, the means for estimating to estimate a second information extraction cost corresponding to retrieval of information from a remote knowledge base, means for selecting an information source based on the first and second estimated information extraction costs, means for querying the selected information source, the means for querying to return the queried information, means for storing, in response to a determination that the selected information source was an external information source, the queried information in the local knowledge base, means for organizing the stored information in the local knowledge base.

Example 26 includes the apparatus of example 25, wherein the means for extracting is to determine whether result information is stored within a neural network model by querying the neural network model for the result information, and in response to a determination that the result information is stored within a neural network model, extract the information from the neural network model.

Example 27 includes the apparatus of example 25, wherein the means for estimating is to estimate a third information extraction cost corresponding to retrieval of information from third information source, the third information extraction cost added to a plurality of information costs including one or more of the first and second information extraction costs.

Example 28 includes the apparatus of example 27, wherein the means for selecting an information source is to further sort the plurality of information extraction costs to determine an information source associated with a minimum information extraction cost of the plurality of information extraction costs.

Example 29 includes the apparatus of example 25, wherein means for estimating is to estimate an expected amount of retrieval time for information from an information source.

Example 30 includes the apparatus of example 25, wherein the means for selecting an information source is to select the information source of a plurality of information sources to be queried based on a minimum associated extraction cost of a sorted plurality of information costs.

Example 31 includes the apparatus of example 25, wherein the stored information in the local knowledge base is to be structured using one or more of a hashing, caching, and indexing algorithm.

Example 32 includes the apparatus of example 25, wherein the means for returning the queried information is further to return explainability information corresponding to an extraction path with the queried information.

It is noted that this patent claims priority from U.S. Provisional Patent Application No. 63/125,962 which was filed on Dec. 15, 2020, and is hereby incorporated by reference in its entirety.