Substrate structure and method for manufacturing the same

A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to a substrate structure and a method, and to a substrate structure including a compensation structure, and a method for manufacturing the substrate structure.

2. Description of the Related Art

A substrate structure may include a dielectric structure, a plurality of redistribution layer embedded in the dielectric structure, and a plurality of bump pads disposed on the dielectric structure and electrically connected to the redistribution layers. The dielectric structure includes a plurality of dielectric layers. However, due to the layout of the redistribution layers, a top surface of each of the dielectric layers that covers the redistribution layer may not be flat or planar. Thus, a top surface of the dielectric structure may not be flat or planar. Accordingly, the bump pads disposed thereon may not be at a same level. Due to the level differences between these bump pads, a semiconductor die may not be properly connected to each of the bump pads of the substrate structure.

SUMMARY

In some embodiments, a substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.

In some embodiments, a substrate structure includes a wiring structure, a bump pad and a dummy metal layer. The wiring structure includes a dielectric layer and a redistribution layer disposed on the dielectric layer. The bump pad is bonded to and electrically connected to the wiring structure. The bump pad has a projection region on the dielectric layer. The projection region of the bump pad has a first area. A portion of the redistribution layer is disposed within the projection region of the bump pad. The portion of the redistribution layer in the projection region has a second area. The second area is less than 40% of the first area. The dummy metal layer is disposed on the dielectric layer. At least a portion of the dummy metal layer is disposed within the projection region of the bump pad on the dielectric layer.

In some embodiments, a method for manufacturing a substrate structure includes: (a) providing a wiring structure and a compensation structure, wherein the wiring structure includes a plurality of redistribution layers, an amount of redistribution layers at a position corresponding to a first position is greater than an amount of redistribution layers at a position corresponding to a second position, and the compensation structure is located at the position corresponding to the second position; and (b) forming a first bump pad and a second bump pad on and electrically connected to the wiring structure, wherein the first bump pad and the second bump pad are respectively located at the position corresponding to the first position and the position corresponding to the second position, and the first bump pad and the second bump pad are substantially at a same level.

DETAILED DESCRIPTION

A comparative substrate structure may include a first dielectric layer, a first redistribution layer disposed on the first dielectric layer, a second dielectric layer covering the first redistribution layer, and a second redistribution layer disposed on the second dielectric layer, etc. The substrate structure may further include a plurality of bump pads disposed on a topmost dielectric layer.

In the comparative substrate structure, since the second dielectric layer covers the first redistribution layer, a shape of a top surface of the second dielectric layer may be affected by the first redistribution layer which is a patterned layer. That is, the top surface of the second dielectric layer may not be flat or planar. For example, the top surface of the second dielectric layer may be relatively high at a position where the first redistribution layer exists, and may be relatively low at a position where the first redistribution is absent. The level difference may accumulate when the amount of the redistribution layers and the dielectric layers increase. In some embodiments, a level difference between a highest position and a lowest position of a top surface of the topmost dielectric layer may be about 4 μm, or even greater. Accordingly, the bump pads disposed on the topmost dielectric layer may not be at a same level, which may adversely affect the bonding quality between the comparative substrate structure and a semiconductor die. For example, the semiconductor die may not be properly connected to each of the bump pads of the substrate structure.

The present disclosure addresses at least some of the above concerns and provides for a substrate structure including a compensation structure for compensating the level difference of the bump pads. Some embodiments of the present disclosure further provides for a method for manufacturing the substrate structure.

FIG. 1illustrates a cross-sectional view of a substrate structure1according to some embodiments of the present disclosure. The substrate structure1may include a wiring structure2, a first bump pad31, a second bump pad32, a compensation structure (e.g., an intermediate bump34) and an external connector13.

The wiring structure2includes a plurality of redistribution layers, such as four redistribution layers (e.g., a first redistribution layer22, a second redistribution layer24, a third redistribution layer26, a fourth redistribution layer28,) as shown inFIG. 1. In some embodiments, the wiring structure2may include a first dielectric layer21, a first redistribution layer22, a second dielectric layer23, a second redistribution layer24, a third dielectric layer25, a third redistribution layer26, a fourth dielectric layer27, a fourth redistribution layer28, and a fifth dielectric layer29. However, in other embodiments, the wiring structure2may include more or less redistribution layers and/or dielectric layers.

The first dielectric layer21may be a bottommost dielectric layer of the wiring structure2. As shown inFIG. 1, the first dielectric layer21may be substantially planar. That is, a thickness of the first dielectric layer21may be substantially consistent.

The first redistribution layer22is disposed on the first dielectric layer21. The first redistribution layer22may be a patterned layer that includes at least one conductive trace and at least one conductive pad. As shown inFIG. 1, the first redistribution layer22includes at least one first conductive via221extending through the first dielectric layer21to form an external contact. The external connector13is connected to the first conductive via221of the first dielectric layer21for external connection purpose.

The second dielectric layer23is disposed on the first dielectric layer21and covers the first redistribution layer22. The second dielectric layer23may be conformal to the first redistribution22. For example, the second dielectric layer23may be applied in a liquid form by coating, or in a dry film form by laminating. The second dielectric layer23may be applied in a constant volume over the entire first dielectric layer21to cover the first redistribution layer22. Hence, the “topography” of the second dielectric layer23may be affected by the first redistribution layer22disposed thereunder. That is, the “topography” of the second dielectric layer23may be ascending at a position where the first redistribution layer22exists, and may be descending at a position where the first redistribution layer22is absent. Accordingly, a top surface of the second dielectric layer23may not be flat or planar. In some embodiments, the top surface of the second dielectric layer23may be in a wave shape.

The second redistribution layer24is disposed on the second dielectric layer23. The second redistribution layer24may be a patterned layer that includes at least one conductive trace and at least one conductive pad. As shown inFIG. 1, the second redistribution layer24includes at least one second conductive via241extending through the second dielectric layer23to contact and electrically connect the first redistribution layer22. In some embodiments, as shown inFIG. 1, second redistribution layer24includes a plurality of second conductive vias241.

The third dielectric layer25is disposed on the second dielectric layer23and covers the second redistribution layer24. The third dielectric layer25may be conformal to the second redistribution layer24and the second dielectric layer23. Similar to the second dielectric layer23described above, the “topography” of the third dielectric layer25may be ascending at a position where the first redistribution layer22and second redistribution layer24exist, and may be descending at a position where the first redistribution layer22and/or the second redistribution layer24is omitted. Accordingly, a top surface of the third dielectric layer25may not be flat or planar. For example, at a position corresponding to a position P1shown inFIG. 1, the top surface of the third dielectric layer25is at a higher level due to the existence of the second redistribution layer24. In contrast, at a position corresponding to a position P2shown inFIG. 1, the top surface of the third dielectric layer25is at a lower level due to the absent of the second redistribution24. In some embodiments, a level difference of the top surface of the third dielectric layer25between the position corresponding to the first position P1and the position corresponding to the second position P2may be about 2 μm.

The third redistribution layer26is disposed on the third dielectric layer25. The third redistribution layer26may be a patterned layer that includes at least one conductive trace and at least one conductive pad. As shown inFIG. 1, the third redistribution layer26includes at least one third conductive via261extending through the third dielectric layer25to contact and electrically connect the second redistribution layer24. In some embodiments, as shown IFIG. 1, the third redistribution layer26includes a plurality of third conductive vias261. Some of the third conductive vias261are disposed on respective ones of the second conductive vias241.

The fourth dielectric layer27is disposed on the third dielectric layer25and covers the third redistribution layer26. The fourth dielectric layer27may be conformal to the third redistribution layer26and the third dielectric layer25. Similar to the second dielectric layer23and the third dielectric layer25described above, the “topography” of the fourth dielectric layer27may be ascending at a position where the first redistribution layer22, the second redistribution layer24and the third redistribution layer26exist, and may be descending at a position where the first redistribution layer22, the second redistribution layer24and/or the third redistribution layer26is omitted. Accordingly, a top surface of the fourth dielectric layer27may not be flat or planar. For example, at a position corresponding to the position P1shown inFIG. 1, the top surface of the fourth dielectric layer27is at a higher level due to the existence of the first redistribution layer22, the second redistribution layer24and the third redistribution layer26. In contrast, at a position corresponding to the position P2shown inFIG. 1, the top surface of the fourth dielectric layer27is at a lower level due to the absent of the second redistribution24and the third redistribution layer26. In some embodiments, due to the absent of two redistribution layers (e.g., the second redistribution layer24and the third redistribution layer26) at the second position P2, a level difference of the top surface of the fourth dielectric layer27between the position corresponding to the first position P1and the position corresponding to the second position P2may be about 4 μm.

The fourth redistribution layer28is disposed on the fourth dielectric layer27. The fourth redistribution layer28may be a patterned layer that includes at least one conductive trace and at least one conductive pad. As shown inFIG. 1, the fourth redistribution layer28includes at least one fourth conductive via281extending through the fourth dielectric layer27to contact and electrically connect the third redistribution layer26. In some embodiments, as shown inFIG. 1, the fourth redistribution layer28includes a plurality of fourth conductive vias281. Some of the fourth conductive vias281are disposed on respective ones of the third conductive vias261.

The fifth dielectric layer29is disposed on the fourth dielectric layer27and covers the fourth redistribution layer28. The fifth dielectric layer29may be conformal to the fourth redistribution layer28and the fourth dielectric layer27. Similarly, the “topography” of the fifth dielectric layer29may be ascending at a position where the first redistribution layer22, the second redistribution layer24, the third redistribution layer26and the fourth redistribution layer28exists, and may be descending at a position where the first redistribution layer22, the second redistribution layer24, the third redistribution layer26and/or the fourth redistribution layer28is omitted. Accordingly, a top surface of the fifth dielectric layer29may not be flat or planar. For example, at a position corresponding to the position P1shown inFIG. 1, the top surface of the fifth dielectric layer29is at a higher level due to the existence of the first redistribution layer22, the second redistribution layer24, the third redistribution layer26and the fourth redistribution layer28. In contrast, at a position corresponding to the position P2shown inFIG. 1, the top surface of the fifth dielectric layer29is at a lower level due to the absent of the second redistribution24and the third redistribution layer26. In some embodiments, due to the absent of two redistribution layers (e.g., the second redistribution layer24and the third redistribution layer26) at the second position P2, a level difference of the top surface of the fourth dielectric layer27at a position corresponding to the first position P1and a position corresponding to the second position P2may be about 4 μm or greater.

In some embodiments, a material of the first dielectric layer21, the second dielectric layer23, the third dielectric layer25, the fourth dielectric layer27and/or the fifth dielectric layer29may include an insulating material, a passivation material, a dielectric material or a solder resist material, such as, for example, a benzocyclobutene (BCB) based polymer or a polyimide (PI). In some embodiments, the second dielectric layer23, the third dielectric layer25, the fourth dielectric layer27and/or the fifth dielectric layer29may be made of a photoimageable dielectric (PID) material.

In some embodiments, a material of the first redistribution layer22, the second redistribution layer24, the third redistribution layer26and/or the fourth redistribution layer28may be a conductive metal. For example, the first redistribution layer22, the second redistribution layer24, the third redistribution layer26and/or the fourth redistribution layer28may include a seed layer and a conductive layer. A material of the seed layer may be titanium, copper, another metal or an alloy. In some embodiments, the seed layer includes a titanium layer and a copper layer. A material of the conductive layer may include, for example, copper, another conductive metal, or an alloy thereof.

The wiring structure2has a first surface201and a second surface202opposite to the first surface201. As shown inFIG. 1, the first surface201may be a bottom surface of the wiring structure2, and the second surface202may be a top surface of the wiring structure2. For example, the first surface201may be a bottom surface of the first dielectric layer21, and the second surface202may be a top surface of the fifth dielectric layer29. The first surface201may be substantially flat or planar, while the second surface202may not be flat or planar.

As discussed above, the second redistribution layer24and the third redistribution layer26are absent at a position corresponding to the second position P2. That is, an amount of redistribution layers at a position corresponding to the first position P1is greater than an amount of redistribution layers at the second position P2. For example, as shown inFIG. 1, the amount of redistribution layers at the position corresponding to the first position P1is four (e.g., including the first redistribution layer22, the second redistribution layer24, the third redistribution layer26and the fourth redistribution layer28), and an amount of redistribution layers at the position corresponding to the second position P2is only two (e.g., including the first redistribution layer22and the fourth redistribution layer28). Due to the absent of the second redistribution layer24and the third redistribution layer26at the position corresponding to the second position P2, a thickness T1of the wiring structure2at the position corresponding to the first position P1is greater than a thickness T2of the wiring structure2at the position corresponding to the second position P2. In some embodiments, the thickness T1of the wiring structure2at the position corresponding to the first position P1is greater than the thickness T2of the wiring structure2at the position corresponding to the second position P2by at least about 4 μm.

As shown inFIG. 1, the compensate structure includes an intermediate bump34. The intermediate bump34is bonded to and electrically connected to the wiring structure2. As shown inFIG. 1, the intermediate bump34is disposed at the position corresponding to the second position P2of the wiring structure2. As described above, thickness T1of the wiring structure2at the position corresponding to the first position P1is greater than a thickness T2of the wiring structure2at the position corresponding to the second position P2. Accordingly, the compensate structure (e.g., the intermediate bump34) is utilized to compensate the thickness difference between the thickness T1and the thickness T2.

The first bump pad31and the second bump pad32are bonded to and electrically connected to the wiring structure2. As shown inFIG. 1, the first bump pad31and the second bump pad32are respectively disposed at the position corresponding to the first position P1and the position corresponding to the second position P2of the wiring structure2. Accordingly, an amount of redistribution layers (e.g., including the first redistribution layer22, the second redistribution layer24, the third redistribution layer26and the fourth redistribution layer28) disposed under the first bump pad31is greater than an amount of redistribution layers (e.g., including the first redistribution layer22and the fourth redistribution layer28) disposed under the second bump pad32.

In some embodiments, the first bump pad31and the second bump pad32are formed concurrently. It is difficult to form the first bump pad31and the second bump pad32with different thicknesses. That is, a thickness of the first bump pad31may substantially equal to a thickness of the second bump pad32. The thickness of the first bump pad31may be measured from the second surface202of the wiring structure2to a top surface of the first bump pad31. Besides, a barrier layer35and a wetting layer36may be disposed on the first bump pad31and the second bump pad32. A material of the barrier layer35may include nickel. A material of the wetting layer36may include gold.

The compensation structure (e.g., the intermediate bump34) is disposed under the second bump pad32. The intermediate bump34is interposed between and electrically connecting the wiring structure2and the second bump pad32. A lateral surface341of the intermediate bump34may be not coplanar with a lateral surface321of the second bump pad32. A width W2of the intermediate bump34may be greater than a width W1of the second bump pad32.

Due to the arrangement of the intermediate bump34, the first bump pad31and the second bump pad32are substantially at a same level. In some embodiments, the level of the first bump pad31may be measured from the first surface201of the wiring structure2to the top surface of the first bump pad31. The level of the second bump pad32may be measured from the first surface201of the wiring structure2to a center of a top surface of the second bump pad32. However, the top surface of the first bump pad31may not be coplanar with the top surface of the second bump pad32.

In some embodiments, as shown inFIG. 1, the second conductive via241, the third conductive via261and the fourth conductive via281are stacked together to improve signal transmitting efficiency, and reduce signal loss. However, since the second conductive via241, the third conductive via261and the fourth conductive via281may expand in subsequent thermal processes, the first bump pad31and the second bump pad32may not be disposed directly above the second conductive via241, the third conductive via261and the fourth conductive via281. That is, the first bump pad31and the second bump pad32may be misaligned with the second conductive via241, the third conductive via261and the fourth conductive via281.

FIG. 2illustrates a cross-sectional view of a substrate structure1aaccording to some embodiments of the present disclosure. The substrate structure1ais similar to the substrate structure1shown inFIG. 1, except that the compensation structure of the substrate structure1aincludes at least one dummy metal layer (e.g., a first dummy metal layer37and a second dummy metal layer38) instead of the intermediate bump34of the substrate structure1.

As shown inFIG. 2, the compensation structure includes a first dummy metal layer37and a second dummy metal layer38embedded in the wiring structure2. As described in the substrate structure1shown inFIG. 1, since the second redistribution layer24and the third redistribution layer26are omitted at the position corresponding to the position P2, the thickness T2of the wiring structure2at the position corresponding to the position P2is less than the thickness T1of the wiring structure2at the position corresponding to the position P1. Hence, in the substrate1ashown inFIG. 2, the first dummy metal layer37and the second dummy metal layer38are disposed to compensate the omitted second redistribution layer24and third redistribution layer26at the position corresponding to the position P2. The “dummy metal layer” provides merely for supporting purpose, without any electrical connection function. For example, the first dummy metal layer37and the second dummy metal layer38are insulated from the redistribution layers of the wiring structure2, such as the first redistribution layer22, the second redistribution layer24, the third redistribution layer26and the fourth redistribution layer28.

The first dummy metal layer37and the second dummy metal layer38are disposed at the position corresponding to the position P2under the second bump pad32. As shown inFIG. 2, the first dummy metal layer37is disposed on the second dielectric layer23. In some embodiments, the first dummy metal layer37may be formed concurrently with the second redistribution layer24. The second dummy metal layer38is disposed on the third dielectric layer25a. In some embodiments, the second dummy metal layer38may be formed concurrently with the third redistribution layer26. Due to the arrangement of the first dummy metal layer37and the second dummy metal layer38, the third dielectric layer25a, the fourth dielectric layer27aand the fifth dielectric layer29amay not be descending at the position corresponding to the position P2. The thickness T2of the wiring structure2at the position corresponding to the position P2may thus be substantially equal to the thickness T1of the wiring structure2at the position corresponding to the position P1. Accordingly, the first bump pad31and the second bump pad32are substantially at a same level. In some embodiments, the first dummy metal layer37may include a plurality of metal blocks, and the metal blocks may be separated from each other by a plurality of gaps. Similarly, the second dummy metal layer38may also include a plurality of metal blocks, and the metal blocks may be separated from each other by a plurality of gaps.

FIG. 3illustrates a cross-sectional view of a substrate structure1baccording to some embodiments of the present disclosure. The substrate structure1bis similar to the substrate structure1ashown inFIG. 2, except that the second redistribution layer24and/or the third redistribution layer26is not completely omitted under the second bump pad32.

As shown inFIG. 3, the second bump pad32has a projection region320on the second dielectric layer23. The projection region320of the second bump pad32has a first area. A portion of the second redistribution layer24is disposed within the projection region of the second bump pad32. The portion of the second redistribution layer24in the projection region320has a second area. The second area is less than 40% of the first area. That is, an area of a portion of the second redistribution layer24within a projection region320of the second bump pad32on the second dielectric layer23is less than 40% of an area of the projection region320of the second bump pad32on the second dielectric layer23. In this case, the first dummy metal layer37is necessary for supporting purpose. That is, the present disclosure further provides a design rule for dummy metal layers. When an area of a portion of the redistribution layer within a projection region of the bump pad on the dielectric layer is less than 40% of an area of the projection region of the bump pad on the dielectric layer, a dummy metal layer may be disposed on the dielectric layer for supporting purpose. As shown inFIG. 3, the first dummy metal layer37is disposed on the second dielectric layer23. At least a portion of the first dummy metal layer37is disposed within the projection region320of the second bump pad32on the second dielectric layer23.

Besides, the aforementioned design rule for dummy metal layers may be applied to each redistribution layer under the bump pad. For example, the second bump pad32has a projection region320on the third dielectric layer25a. The projection region320of the second bump pad32has a first area. A portion of the third redistribution layer26is disposed within the projection region320of the bump pad32. The portion of the third redistribution layer26in the projection region320has a second area. The second area is less than 40% of the first area. That is, as for the third redistribution layer26, an area of a portion of the third redistribution layer26within the projection region320of the second bump pad32on the third dielectric layer25ais less than 40% of an area of the projection region320of the second bump pad32on the third dielectric layer25a. Accordingly, the second dummy metal layer38is disposed on the third dielectric layer25afor supporting purpose. As shown inFIG. 3, the second dummy metal layer38is disposed on the third dielectric layer25a, wherein at least a portion of the second dummy metal layer38is disposed within the projection region320of the bump pad32on the third dielectric layer25a.

FIG. 4illustrates a cross-sectional view of a semiconductor device5according to some embodiments of the present disclosure. The semiconductor device5includes the substrate structure1shown inFIG. 1, and further includes a semiconductor die54electrically connected to the first bump pad31and the second bump pad32.

As shown inFIG. 4, the semiconductor die54may include a plurality of bump pads544. Each of the bump pad544of the semiconductor die54is connected to a respective one of the first bump pad31and the second bump pad32of the substrate structure1through a solder ball56disposed therebetween. Since the first bump pad31and the second bump pad32are substantially at a same level, the semiconductor die54may be properly connected to the substrate structure1. A top surface of the semiconductor die54may thus be substantially coplanar with a bottom surface (e.g., the first surface201) of the wiring structure2.

FIG. 5throughFIG. 16illustrate a method for manufacturing a substrate structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a substrate structure, such as the substrate structure1shown inFIG. 1.

Referring toFIG. 6, a first dielectric layer21is formed or disposed on the carrier80. The first dielectric layer21defines a through hole210to expose a portion of the carrier80. The through hole210may be formed by mechanical drilling, laser drilling, or lithographic techniques.

Referring toFIG. 7, a first redistribution layer22is formed or disposed on the first dielectric layer21by, for example, plating. The first redistribution layer22includes at least one first conductive via221extending in the through hole210through the first dielectric layer21to form an external contact. The first redistribution layer22may be a patterned layer.

Referring toFIG. 8, a second dielectric layer23is formed or disposed on the first dielectric layer21to cover the first redistribution layer22. The second dielectric layer23may be conformal to the first redistribution layer22. For example, the second dielectric layer23may be applied in a liquid form by coating, or in a dry film form by laminating. The second dielectric layer23may be applied in a constant volume over the entire first dielectric layer21to cover the first redistribution layer22. Hence, the “topography” of the second dielectric layer23may be affected by the first redistribution layer22disposed thereunder. That is, the “topography” of the second dielectric layer23may be ascending at a position where the first redistribution layer22exists, and may be descending at a position where the first redistribution layer22is absent. Accordingly, a top surface of the second dielectric layer23may not be flat or planar. The second dielectric layer23defines at least one through hole230to expose a portion of the first redistribution layer22.

Referring toFIG. 9, a second redistribution layer24is formed or disposed on the second dielectric layer23by, for example, plating. The second redistribution layer24includes at least one second conductive via241extending in the though hole230through the second dielectric layer23to contact and electrically connect the first redistribution layer22. In some embodiments, as shown inFIG. 9, the second redistribution layer24includes a plurality of second conductive vias241. The second redistribution layer24may be a patterned layer.

Referring toFIG. 10, a third dielectric layer25is formed or disposed on the second dielectric layer23to cover the second redistribution layer24. The third dielectric layer25may be conformal to the second redistribution layer24and the second dielectric layer23. Similar to the second dielectric layer23described above, the “topography” of the third dielectric layer25may be ascending at a position where the first redistribution layer22and second redistribution layer24exist, and may be descending at a position where the first redistribution layer22and/or the second redistribution layer24is omitted. Accordingly, a top surface of the third dielectric layer25may not be flat or planar. For example, at a position corresponding to the position P1shown inFIG. 1, the top surface of the third dielectric layer25is at a higher level due to the existence of the second redistribution layer24. In contrast, at a position corresponding to the position P2shown inFIG. 10, the top surface of the third dielectric layer25is at a lower level due to the absent of the second redistribution24. In some embodiments, a level difference of the top surface of the third dielectric layer25between the position corresponding to the first position P1and the position corresponding to the second position P2may be about 2 μm. The third dielectric layer25defines at least one through hole250to expose a portion of the second redistribution layer24. In some embodiments, the third dielectric layer25defines a plurality of through holes250, and some of the through holes250expose respective ones of the second conductive vias241.

Referring toFIG. 11, a third redistribution layer26is formed or disposed on the third dielectric layer25by, for example, plating. The third redistribution layer26includes at least one third conductive via261extending in the though hole250through the third dielectric layer25to contact and electrically connect the second redistribution layer24. In some embodiments, as shown inFIG. 11, the third redistribution layer26includes a plurality of third conductive vias261. Some of the third conductive vias261are disposed on respective ones of the second conductive vias241. The third redistribution layer26may be a patterned layer.

Referring toFIG. 12, a fourth dielectric layer27is formed or disposed on the third dielectric layer25to cover the third redistribution layer26. The fourth dielectric layer27may be conformal to the third redistribution layer26and the third dielectric layer25. Similar to the second dielectric layer23and the third dielectric layer25described above, the “topography” of the fourth dielectric layer27may be ascending at a position where the first redistribution layer22, the second redistribution layer24and the third redistribution layer26exist, and may be descending at a position where the first redistribution layer22, the second redistribution layer24and/or the third redistribution layer26is omitted. Accordingly, a top surface of the fourth dielectric layer27may not be flat or planar. For example, at a position corresponding to the position P1shown inFIG. 1, the top surface of the fourth dielectric layer27is at a higher level due to the existence of the first redistribution layer22, the second redistribution layer24and the third redistribution layer26. In contrast, at a position corresponding to the position P2shown inFIG. 12, the top surface of the fourth dielectric layer27is at a lower level due to the absent of the second redistribution24and the third redistribution layer26. In some embodiments, due to the absent of two redistribution layers (e.g., the second redistribution layer24and the third redistribution layer26) at the second position P2, a level difference of the top surface of the fourth dielectric layer27between the position corresponding to the first position P1and the position corresponding to the second position P2may be about 4 μm. The fourth dielectric layer27defines at least one through hole270to expose a portion of the third redistribution layer26. In some embodiments, the fourth dielectric layer27defines a plurality of through holes270, and some of the through holes270expose respective ones of the third conductive vias261.

Referring toFIG. 13, a fourth redistribution layer28is formed or disposed on the fourth dielectric layer27by, for example, plating. The fourth redistribution layer28includes at least one fourth conductive via281extending in the through hole270through the fourth dielectric layer27to contact and electrically connect the third redistribution layer26. In some embodiments, as shown inFIG. 13, the fourth redistribution layer28includes a plurality of fourth conductive vias281. Some of the fourth conductive vias281are disposed on respective ones of the third conductive vias261. The fourth redistribution layer28may be a patterned layer.

Referring toFIG. 14, the fifth dielectric layer29is formed or disposed on the fourth dielectric layer27to cover the fourth redistribution layer28, thus forming a wiring structure2. The fifth dielectric layer29may be conformal to the fourth redistribution layer28and the fourth dielectric layer27. Similarly, the “topography” of the fifth dielectric layer29may be ascending at a position where the first redistribution layer22, the second redistribution layer24, the third redistribution layer26and the fourth redistribution layer28exists, and may be descending at a position where the first redistribution layer22, the second redistribution layer24, the third redistribution layer26and/or the fourth redistribution layer28is omitted. Accordingly, a top surface of the fifth dielectric layer29may not be flat or planar. For example, at a position corresponding to the position P1shown inFIG. 14, the top surface of the fifth dielectric layer29is at a higher level due to the existence of the first redistribution layer22, the second redistribution layer24, the third redistribution layer26and the fourth redistribution layer28. In contrast, at a position corresponding to the position P2shown inFIG. 14, the top surface of the fifth dielectric layer29is at a lower level due to the absent of the second redistribution24and the third redistribution layer26. In some embodiments, due to the absent of two redistribution layers (e.g., the second redistribution layer24and the third redistribution layer26) at the position corresponding to the second position P2, a level difference of the top surface of the fourth dielectric layer27between the position corresponding to the first position P1and the position corresponding to the second position P2may be about 4 μm or greater.

Meanwhile, a wiring structure2is obtained. The wiring structure2has a first surface201and a second surface202opposite to the first surface201. As shown inFIG. 14, the first surface201may be a bottom surface of the wiring structure2, and the second surface202may be a top surface of the wiring structure2. For example, the first surface201may be a bottom surface of the first dielectric layer21, and the second surface202may be a top surface of the fifth dielectric layer29. The first surface201may be substantially flat or planar, while the second surface202may not be flat or planar.

As discussed above, the second redistribution layer24and the third redistribution layer26are absent at the position corresponding to the second position P2. That is, an amount of redistribution layers at the position corresponding to the first position P1is greater than an amount of redistribution layers at the position corresponding to the second position P2. For example, as shown inFIG. 14, the amount of redistribution layers at the position corresponding to the first position P1is four (e.g., including the first redistribution layer22, the second redistribution layer24, the third redistribution layer26and the fourth redistribution layer28), and an amount of redistribution layers at the position corresponding to the second position P2is only two (e.g., including the first redistribution layer22and the fourth redistribution layer28). Besides, due to the absent of the second redistribution layer24and the third redistribution layer26at the position corresponding to the second position P2, a thickness T1of the wiring structure2at the position corresponding to the first position P1is greater than a thickness T2of the wiring structure2at the position corresponding to the second position P2. In some embodiments, the thickness T1of the wiring structure2at the position corresponding to the first position P1is greater than the thickness T2of the wiring structure2at the position corresponding to the second position P2by at least about 4 μm.

Referring toFIG. 15, a compensation structure, such as an intermediate bump34, is formed on the wiring structure2by, for example, plating. The intermediate bump34is bonded to and electrically connected to the wiring structure2. As shown inFIG. 15, the intermediate bump34is disposed at the position corresponding to the second position P2of the wiring structure2. As described above, thickness T1of the wiring structure2at the position corresponding to the first position P1is greater than a thickness T2of the wiring structure2at the position corresponding to the second position P2. Accordingly, the compensate structure (e.g., the intermediate bump34) is utilized to compensate the thickness difference between the thickness T1and the thickness T2. A top portion of the intermediate bump34may be disposed on the second surface202of the wiring structure2. A bottom portion of the intermediate bump34may be disposed in an opening of the fifth dielectric layer29to electrically connect the fourth redistribution layer28.

Referring toFIG. 16, a first bump pad31and a second bump pad32are formed on the wiring structure2by, for example, plating. The first bump31and the second bump32are electrically connected to the wiring structure2. The first bump31and the second bump32are respectively located at the position corresponding to the first position P1and the position corresponding to the second position P2.

The second bump pad32is disposed on the compensation structure (e.g., the intermediate bump34). Thus, the intermediate bump34is interposed between and electrically connecting the wiring structure2and the second bump pad32. A lateral surface341of the intermediate bump34may be not coplanar with a lateral surface321of the second bump pad32. A width W2of the intermediate bump34may be greater than a width W1of the second bump pad32.

Due to the arrangement of the intermediate bump34, the first bump pad31and the second bump pad32are substantially at a same level. In some embodiments, the level of the first bump pad31may be measured from the first surface201of the wiring structure2to the top surface of the first bump pad31. The level of the second bump pad32may be measured from the first surface201of the wiring structure2to a center of a top surface of the second bump pad32. However, the top surface of the first bump pad31may not be coplanar with the top surface of the second bump pad32.

Then, the carrier80is removed. An external connector13is connected to the first conductive via221of the first dielectric layer21. Then, a singulation process may be conducted to the wiring structure2, thus forming the substrate structure1as shown inFIG. 1.

FIG. 17throughFIG. 19illustrates a method for forming a substrate structure according to some embodiments of the present disclosure, such as the substrate structure1ashown inFIG. 2. The initial stage of the illustrated process is the same as, or similar to, the stage illustrated inFIG. 5throughFIG. 8.FIG. 17depict a stage subsequent to that depicted inFIG. 8.

Referring toFIG. 17, a second redistribution layer24is disposed on the second dielectric layer23by, for example, plating. Besides, a first dummy metal layer37is also formed on the second dielectric layer23by, for example, plating. The first dummy metal layer37is located at a position corresponding to the position P2. In some embodiments, the first dummy metal layer37may be formed concurrently with the second redistribution layer24. For example, the first dummy metal layer37and the second redistribution layer24may be formed in a same process with a same material. However, the first dummy metal layer37is insulated from the second redistribution layer24.

Referring toFIG. 18, a third dielectric layer25ais formed on the second dielectric layer23to cover the second redistribution layer24and the first dummy metal layer37. The third dielectric layer25amay be applied in a liquid form by coating, or in a dry film form by laminating. The third dielectric layer25amay be conformal to the first redistribution layer22, the second redistribution layer24and the first dummy metal layer37. Due to the existence of the first dummy metal layer37, the third dielectric layer25ais not descending at the position corresponding to the position P2.

Then, a third redistribution layer26is disposed on the third dielectric layer25aby, for example, plating. Besides, a second dummy metal layer38is also formed on the third dielectric layer25aby, for example, plating. The second dummy metal layer38is located at a position corresponding to the position P2. In some embodiments, the second dummy metal layer38may be formed concurrently with the third redistribution layer26. For example, the second dummy metal layer38and the third redistribution layer26may be formed in a same process with a same material. However, the second dummy metal layer38is insulated from the third redistribution layer26.

Referring toFIG. 19, a fourth dielectric layer27ais formed on the third dielectric layer25ato cover the third redistribution layer26and the second dummy metal layer38. The fourth dielectric layer27amay be applied in a liquid form by coating, or in a dry film form by laminating. The fourth dielectric layer27amay be conformal to the first redistribution layer22, the second redistribution layer24, the first dummy metal layer37, the third redistribution layer26and the second dummy metal layer38. Due to the existence of the first dummy metal layer37and the second dummy metal layer38, the fourth dielectric layer27ais not descending at the position corresponding to the position P2.

Then, a fourth redistribution layer28and a fifth dielectric layer29aare sequentially formed on the fourth dielectric layer27a, thus forming a wiring structure2a. The formation processes of the fourth redistribution layer28and the fifth dielectric layer29aare similar to those of the fourth redistribution layer28and the fifth dielectric layer29described inFIGS. 13 and 14. A compensation structure (e.g., including the first dummy metal layer37and/or the second dummy metal layer38) is embedded in the wiring structure2a.

Then, a first bump pad31and a second bump pad32are formed on the wiring structure2aby, for example, plating. The first bump31and the second bump32are electrically connected to the wiring structure2a. The first bump31and the second bump32are respectively located at the position corresponding to the first position P1and the position corresponding to the second position P2. Due to the arrangement of the first dummy metal layer37and/or the second dummy metal layer38, the first bump pad31and the second bump pad32are substantially at a same level.

Then, the carrier80is removed. An external connector13is connected to the first conductive via221of the first dielectric layer21for external connection purpose. Then, a singulation process may be conducted to the wiring structure2a, thus forming the substrate structure1aas shown inFIG. 2.