Scalable serial/de-serial I/O for chip-to-chip connection based on multi-frequency QAM scheme

A serializer and de-serializer circuit which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scalable and utilize a multi-frequency quadrature amplitude modulation (QAM) mechanism for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. The serializer has multiple digital-to-analog converters (DACs) whose outputs are directed to QAM mixer inputs, within QAMs at multiple frequencies, whose outputs are summed into a single analog signal for communication over an I/O connection. The de-serializer amplifies the analog signal which is received by QAM mixers at different frequencies, whose outputs are low pass filtered and converted back to parallel digital data bits.

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BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention pertains generally to chip-to-chip communications, and more particularly to a serializer and de-serializer based on quadrature amplitude modulation (QAM) at multiple frequencies.

2. Description of Related Art

Conventional serial/de-serial I/O is based on multiplexing and demultiplexing digital communications. Using these conventional schemes to increase communications bandwidth requires increasing clock rate. Because a given process technology has its own limitations on clock rates, one must often increase the number of I/O connections to increase the bandwidth, whereby the I/O bandwidth increase comes at the expense of higher manufacturing costs. These costs are even further increased in 3D integrated circuit integration, such as those based on through-substrate-via (TSV) for vertical interconnections. The number of TSVs for the I/O is non-scalable due to fundamental physical or mechanical constraints. Higher than a certain number of TSVs per unit area (or population density) leads to thinned Si substrate (about 100 μm/tier) which can result in collapse. Therefore, this thinning can seriously limit inter-tier communication bandwidth in 3D integrated circuits.

Accordingly, a need exists for chip-to-chip communication circuits having higher communication bandwidths without a concurrent need for increased clock rates or additional I/O connections. The present invention fulfills that need, and overcomes the shortcomings of previous chip-to-chip communications topologies.

BRIEF SUMMARY OF THE INVENTION

This serializer de-serializer utilizes multi-frequency band modulation (e.g., quadrature amplitude modulation (QAM)) to exchange digital data chip-to-chip (i.e., between integrated circuit devices) as an analog serial signal comprising a sum of modulated signals on multiple frequencies. Communication over an I/O connection of a first chip is performed in response to serializing the data into an analog stream, which is received at a second chip and de-serialized back to the original parallel digital data. Multiple frequency bands, such as that of QAM signaling, are utilized simultaneously over the single I/O channel to exchange data simultaneously. Such concurrent data transfer allows increasing data transfer bandwidth as more frequency band is used in a single I/O connection. The chip-to-chip interconnection can be either simplified by reducing the number of interconnection while keeping the same application bandwidth or by increasing the application bandwidth while keeping the same number of I/O connections. Using the inventive serializer de-serializer allows the user to increase communication performance, or reduce the cost of chip manufacture, or a combination thereof. The inventive chip-to-chip communication is particularly well-suited for use in advanced three dimensional chip (3DIC) integration.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1illustrates an example embodiment10of chip-to-chip communications between a first chip12over an I/O connect14to a second chip16. The chip-to-chip communication is performed by serializing parallel digital data (having N bits) onto an analog signal (sum of M analog signals) which is communicated to a second chip, where the analog signal is de-serialized back into parallel digital data. The communication in this embodiment utilizes multiple (e.g., two) frequency bands encoded with a quadrature amplitude modulation (e.g., QAM) scheme to serialize and de-serialize data through an input-output chip connection, providing chip-to-chip communications. Embodiments of the present invention can utilize more than two frequency bands into which the digital data is encoded. It should be appreciated that one of these modulation frequencies can be zero, that is DC. Using DC as one modulation frequency can reduce the number of frequency generation circuits needed, including phase-locking circuits (e.g., PLL) which are also needed. As generation of these modulation frequencies is well known with regard to analog modulation and demodulation, the circuits for generating them are not shown.

It will be appreciated that QAM, as described in this embodiment, is an analog modulation mechanism, which differs from digital multiplexing used in a digital serialization scheme. In analog QAM, two analog message signals are communicated on each frequency channel by changing (modulating) two carrier waves. The two carrier waves (typically sinusoids), are out of phase with each other by 90° and are thus called quadrature carriers. Output over a frequency channel is the sum of the modulated waves of phase modulation (PM) and amplitude modulation (AM). For the sake of simplicity of description, the internal circuitry for analog QAM is not described. It will be noted that a large number of QAM circuits are available and the technology is well known to one of ordinary skill in the art.

An 8 bit parallel input18is seen with bits D0through D7, grouped with pairs of bits (i.e., D0and D1, D2and D3, D4and D5, D6and D7), with each pair of bits received by a two bit digital-to-analog converter (DAC)20a,20b,20cand20d. Each analog output from the DACs (20a,20b,20cand20d) is coupled to QAM mixers. Output from DAC20ais received at the QAM I channel at mixer22awhich also receives a 90 degree out-of-phase modulation carrier F1_I, with the output from DAC20bcoupled to the Q channel at mixer22b, along with a 90 degree out-of-phase modulation carrier F1_Q. Mixers22a,22bare both associated with QAM modulator24. Similarly, outputs from DAC20cis coupled to mixer22cwhich also receives 90 degree out-of-phase modulation carrier F2_I, while output from DAC22dis received at mixer22dwhich also receives 90 degree out-of-phase modulation carrier F2_Q. Mixers22c,22dare both associated with QAM modulator26. Outputs from the mixers of both QAM modulators24,26are summed at adder28and output over I/O connection14from first chip12. Through this modulation process, the parallel input is thus serialized into a series output as an analog signal.

The analog signal over I/O connection14is preferably received by an amplifier32which provides a gain stage to compensate for loss in the low pass filter. Amplified signal14is coupled to mixers38a,38bin a first QAM demodulator34, which receives 90 degree out-of-phase modulation carriers F1_I, F1_Q, respectively. In a second QAM demodulator36, mixers38c,38dreceive the amplified signal as well as 90 degree out-of-phase modulation carriers F2_I, F2_Q. Four analog signal channels are output from mixers38a,38b,38c,38dto low pass filters40a,40b,40cand40d. The low pass filters may be of any desired configuration and order (i.e., 2ndorder, 3rdorder and so forth). Output from the filters is received by two-bit analog-to-digital converters (ADC)42a,42b,42cand42d. Data44from each pair of bits is output from the ADCs. Through this demodulation process, the analog serial input is thus de-serialized back to a parallel digital output.

It should be appreciated that certain embodiments, for example a sufficiently low fan out or high impedance QAM mixers under low noise conditions, can be implemented without the amplifier. It should also be noted that the low pass filters can be replaced with a peak detector, without departing from the teachings of the present invention.

Accordingly,FIG. 1illustrates an 8 bit parallel input serialized by two frequency bands of QAM16 to one I/O port for a first chip, output from which is then de-serialized at a second chip by two frequency bands of QAM16 demodulation back into the original parallel data. It should be appreciated, however, that the serializing and de-serializing according to the present invention can be implemented in a number of different ways without departing from the present invention. By way of example and not limitation, the above embodiment can be scaled up to serialize and de-serialize 16 bits of parallel data by using either four frequency bands of QAM16 or two frequency bands of QAM256, as described in the following sections.

FIG. 2AandFIG. 2Billustrate an example embodiment50of a serializer de-serializer in which the communications bandwidth from a first chip52inFIG. 2Ato a second chip56inFIG. 2Bover I/O channel54is increased by utilizing additional frequency bands. It will be seen that the following expands on the circuit shown inFIG. 1, from 8 data bits to 16 data bits.

A 16 bit parallel input58is shown inFIG. 2Awith bits D0through D15, grouped with pairs of bits (i.e., D0and D1, D2and D3, D4and D5, . . . , D14and D15), with each pair of bits received by two bit digital-to-analog converters (DACs)60a,60b,60c, . . . ,60d. Each analog output from the DACs (60a,60b,60c, . . . ,60d) is coupled to QAM mixer inputs (Q and I inputs for each QAM). In particular, output from DAC60ais coupled to mixer62awhich also receives a 90 degree out-of-phase modulation carrier F1_I, while the output from DAC60bis coupled to mixer62bwhich also receives a 90 degree out-of-phase modulation carrier F1_Q. Mixers22a,22bare both associated with QAM modulator64. In a similar manner outputs from DACs60c,60dare coupled to mixers62c,62d, which also receives 90 degree out-of-phase modulation carrier F2_I, F2_Q, respectively. Mixers62c,62dare both associated with QAM modulator66.

Output from the mixers of QAM modulators64,66,68,70are summed at adder72and output over I/O connection54from first chip52to second chip56. Through this modulation process, the 16 bit parallel input is thus serialized into a series output as an analog signal.

The analog signal over I/O connection54is preferably received by an amplifier74inFIG. 2Bwhich provides a gain stage to compensate for loss in a subsequent low pass filter. Amplified signal54is coupled to mixers84a,84b,84c, . . . ,84h, along with 90 degree out-of-phase modulation carriers F1_I, F1_Q, F2_I, F2_Q, F3_I, F3_Q, F4_I, F4_Q respectively, in QAM demodulators76,78,80,82. The eight analog outputs from these QAM demodulators are then filtered through low pass filters86a,86b,86c, . . . ,86h, before receipt by two-bit analog-to-digital converters (ADC)88a,88b,88c, . . . ,88h. Data90from the eight pairs of bits is output from the ADCs. Through this demodulation process, the analog serial input is thus de-serialized back to an output of the original parallel output of 16 digital data bits.

FIG. 3illustrates an example embodiment110of a serializer de-serializer in which bandwidth is increased, between a first chip112over an I/O connect114to a second chip116, by using a higher order QAM. It should be appreciated that a variety of forms of QAM are available and can be utilized with the present invention, some of the more common forms that can be selected for use include: QAM8, QAM16, QAM32, QAM64, QAM128, and QAM256. It will be appreciated that QAM distributes information in the I-Q plane evenly, and the higher orders of QAM involve information spaced more closely in the constellation. Thus, higher order QAM allows transmitting more bits per symbol, but if the energy of the constellation is to remain the same, the points on the constellation are closer together and the transmission becomes more susceptible to noise. It should also be appreciated that modulation and demodulation can be performed according to the present invention utilizing other forms of multi-frequency analog modulation-demodulation. Examples of other forms of multi-frequency modulation which can be utilized include pulse-width modulation (PWM), frequency-shift keying (FSK), frequency-hopping, spread spectrum, and so forth.

Parallel digital data input of 16 bits118parallel is seen with bits D0through D15, grouped in nibbles (i.e., 4 bits) (i.e., D0-D3, D4-D7, D8-D11, D12-D15), with each nibble of bits received by four bit digital-to-analog converters (DACs)120a,120b,120cand120d. Each analog output from the DACs (120a,120b,120cand120d) is coupled to QAM mixers. In particular, output from DAC120ais coupled to mixer122awhich also receives a 90 degree out-of-phase modulation carrier F1_I, while the output from DAC120bis coupled to mixer122b, along with a 90 degree out-of-phase modulation carrier F1_Q. Mixers122a,122bare both associated with QAM modulator124. Similarly, outputs from DACs120c,120dare coupled to mixers122c,122d, respectively, which also receive 90 degree out-of-phase modulation carriers F2_I, F2_Q. Mixers122c,122dare both associated with QAM modulator126. Outputs from the mixers of both QAM modulators124,126are summed at adder128and output over I/O connection114from first chip112to second chip116. Utilizing this inventive modulation process, the parallel digital input is thus serialized into a series output as an analog signal.

The analog signal over I/O connection114is preferably received by an amplifier132which provides a gain stage to compensate for loss in the low pass filter. Amplified signal114is coupled to mixers138a,138bin a first QAM demodulator134, which receives 90 degree out-of-phase modulation carriers F1_I, F1_Q, respectively. In a second QAM demodulator136, mixers138c,138dreceive the amplified signal as well as 90 degree out-of-phase modulation carriers F2_I, F2_Q. Four analog signal channels are output from mixers138a,138b,138c,138dto low pass filters140a,140b,140cand140d, before receipt by four-bit analog-to-digital converters (ADCs)142a,142b,142cand142d. Data144comprising the nibbles from the ADCs is output as parallel digital data shown here with the 16 bits. Thus, it has been shown inFIG. 3that the original 16 bits of digital data was serialized, communicated off-chip, de-serialized and converted back to 16 bits of parallel digital data.

The examples above inFIG. 2andFIG. 3demonstrate that the present invention can be scaled to a desired number of bits by utilizing more frequency channels of QAM, or higher order QAM encoding, or a combination of more QAM frequency channels and higher order QAM encoding. It should also be appreciated that other multi-frequency analog modulation techniques can be utilized in place of QAM without departing from the invention (e.g., pulse-width modulation (PWM), frequency-shift keying (FSK), frequency-hopping, spread-spectrum, and so forth). The above example circuits can be implemented in any device technology, and are particularly well-suited for use in advanced silicon process technology, such as at or below 28 nm.

The unique multi frequency (or band) serializer and de-serializer of the present invention provide numerous advantages over existing technology. In particular, this new paradigm breaks through silicon process limitations of requiring advanced process nodes, or large numbers of nodes, to increase the bandwidth. Using any given device process, the proposed scheme can increase data transfer bandwidth by using combined frequency bands and QAM modulations. The added circuit overhead becomes relatively insignificant as CMOS technology is further scaled. In the advanced system-on-chip (SoC) designs, large numbers of I/O connections can be reduced by at least a factor of five (×5) by applying the teachings of the present invention while maintaining the same bandwidth.

Another option is to keep the same I/O number but increase bandwidth by the same factor (e.g., ×5), since I/O number does not scale down as process technology advances. Of course a combination approach can be wrought with the present invention, thus providing over a two fold increase in bandwidth and over a twofold reduction in the number of I/Os. This innovative I/O circuit scheme not only improves chip-to-chip I/O performance but also reduces manufacturing cost.

From the discussion above it will be appreciated that the invention can be embodied in various ways, including the following:

1. An apparatus for serializing and de-serializing chip-to-chip communications, comprising: a serializer configured for integration within a first integrated circuit chip, comprising: multiple digital-to-analog converters (DACs) configured for converting N parallel bits of digital data to M analog signals, wherein N is an integer value which is at least two times larger than M; one or more mixers at each of multiple frequencies configured for performing analog modulation; wherein each said mixer receives one of said M analog signals and a modulation carrier; and an adder configured for summing outputs from each of said multiple mixers at said multiple frequencies into an I/O output; a de-serializer configured for integration within a second integrated circuit chip, comprising: an amplifier configured for amplifying said I/O output from said serializer; one or more mixers at each of multiple frequencies configured for performing analog demodulation; wherein each said mixer receives said I/O output from said serializer containing said M analog signals, and a modulation carrier; a low pass filter coupled to an output of each said mixer; multiple digital-to-analog converters (DACs), each said DAC receiving input from each said low pass filter, and outputting digital data bits; and wherein a given number of parallel digital data bits are converted to a serial analog signal, configured for communication over a single I/O line by the serializer to a de-serializer in a second chip which de-serializes the analog information back into the original parallel digital data bits.

2. The apparatus of any of the previous embodiments, wherein said digital-to-analog and analog-to-digital converters operate with at least two bits.

3. The apparatus of any of the previous embodiments, wherein said multiple frequencies comprises at least a first frequency and a second frequency.

4. The apparatus of any of the previous embodiments, wherein said multiple frequencies comprises at least four frequencies.

5. The apparatus of any of the previous embodiments, wherein said analog modulation and demodulation is performed by a modulator or demodulator utilizing quadrature amplitude modulation (QAM); wherein said modulation carrier comprises a 90 degree out-of-phase modulation carrier; and wherein each of said modulator or demodulator utilizing QAM has two of said mixers for a Q and an I channel.

6. The apparatus of any of the previous embodiments, wherein said quadrature amplitude modulation (QAM) is selected from the group of QAM orders consisting of QAM8, QAM16, QAM32, QAM64, QAM128 or QAM256.

7. The apparatus of any of the previous embodiments, wherein said N parallel bits comprises at least 8 bits.

8. An apparatus for serializing and de-serializing chip-to-chip communications, comprising: a serializer configured for integration within a first integrated circuit chip, comprising: multiple digital-to-analog converters (DACs) in said serializer, wherein said DACs convert N parallel bits of digital data to M analog signals, wherein N is an integer value which is at least two times larger than M; two mixers at each of multiple frequencies configured for quadrature amplitude modulation (QAM); wherein each said mixer receives one of said M analog signals, and a 90 degree out-of-phase modulation carrier; and an adder configured for summing outputs from each of said multiple mixers at said multiple frequencies into an I/O output; a de-serializer configured for integration within a second integrated circuit chip, comprising: an amplifier configured for amplifying said I/O output from said serializer; two mixers at each of multiple frequencies configured for quadrature amplitude demodulation (QAM); wherein each said mixer receives said I/O output from said serializer containing said M analog signals, and a 90 degree out-of-phase modulation carrier; a low pass filter coupled to an output of each said mixer; multiple digital-to-analog converters (DACs), each said DAC receiving input from each said low pass filter, and outputting digital data bits; and wherein a given number of parallel digital data bits are converted to a serial analog signal, configured for communication over a single I/O line by the serializer to a de-serializer in a second chip which de-serializes the analog information back into the original parallel digital data bits.

9. The apparatus of any of the previous embodiments, wherein said digital-to-analog and analog-to-digital converters operate with two or four bits.

10. The apparatus of any of the previous embodiments, wherein said multiple frequencies comprises at least a first frequency and a second frequency.

11. The apparatus of any of the previous embodiments, wherein said multiple frequencies comprises at least four frequencies.

12. The apparatus of any of the previous embodiments, wherein said quadrature amplitude modulation (QAM) is selected from the group of QAM orders consisting of QAM8, QAM16, QAM32, QAM64, QAM128 or QAM256.

13. The apparatus of any of the previous embodiments, wherein said quadrature amplitude modulation (QAM) encodes two analog message signals into carrier waves at each output frequency.

14. The apparatus of any of the previous embodiments, wherein said N parallel bits comprises at least 8 bits.

15. A serializer apparatus for chip-to-chip communications, comprising: multiple digital-to-analog converters (DACs) in said serializer apparatus, wherein said DACs convert N parallel bits of digital data to M analog signals, wherein N is an integer value which is at least two times larger than M; two mixers at each of multiple frequencies configured for quadrature amplitude modulation (QAM); wherein each said mixer receives one of said M analog signals, and a 90 degree out-of-phase modulation carrier; and an adder configured for summing outputs from each of said multiple mixers at said multiple frequencies into an I/O output configured for connection to a de-serializer for converting the serial analog I/O output signal back into N parallel bits of digital data.

16. The apparatus of any of the previous embodiments, wherein said digital-to-analog and analog-to-digital converters operate with two or four bits.

17. The apparatus of any of the previous embodiments, wherein said multiple frequencies comprise at least a first frequency and a second frequency.

18. The apparatus of any of the previous embodiments, wherein said multiple frequencies comprise at least four frequencies.

19. The apparatus of any of the previous embodiments, wherein said quadrature amplitude modulation (QAM) is selected from the group of QAM orders consisting of QAM8, QAM16, QAM32, QAM64, QAM128 or QAM256.

20. The apparatus of any of the previous embodiments, wherein said quadrature amplitude modulation (QAM) encodes two analog message signals into carrier waves at each output frequency.

21. The apparatus of any of the previous embodiments, wherein said N parallel bits comprises at least 8 bits.

22. A de-serializer apparatus for chip-to-chip communications, comprising: an amplifier configured for receiving and amplifying a serial analog I/O signal in which N parallel bits of digital data are contained within M analog signals; wherein N is an integer value which is at least two times larger than M; two mixers at each of multiple frequencies configured for quadrature amplitude demodulation (QAM); wherein each said mixer receives said serial analog I/O signal containing M analog signals, and a 90 degree out-of-phase modulation carrier; a low pass filter coupled to an output of each said mixer; and multiple digital-to-analog converters (DACs), each said DAC receiving input from each said low pass filter, and outputting digital data as N parallel bits from said M analog signals.

23. The apparatus of any of the previous embodiments, wherein said N parallel bits comprises at least 8 bits, and wherein said digital-to-analog and analog-to-digital converters operate with two or four bits.

24. The apparatus of any of the previous embodiments, wherein said multiple frequencies comprises at least a first frequency and a second frequency.

25. The apparatus of any of the previous embodiments, wherein said multiple frequencies comprise at least four frequencies.

26. The apparatus of any of the previous embodiments, wherein said quadrature amplitude modulation (QAM) is selected from the group of QAM orders consisting of QAM8, QAM16, QAM32, QAM64, QAM128 or QAM256.

27. The apparatus of any of the previous embodiments, wherein said quadrature amplitude modulation (QAM) encodes two analog message signals into carrier waves at each output frequency.