SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR DEVICES

A method for manufacturing semiconductor packages. The method includes providing a first semiconductor die including a plurality of metallization layers; completely overlaying a topmost one of the metallization layers with a barrier layer; completely overlaying the barrier layer sequentially with a stop layer and a laser liftoff layer; attaching a first side of the first semiconductor die to a first wafer through at least the laser liftoff layer; attaching a second side of the first semiconductor die to a second wafer; removing the first wafer from the first semiconductor die based on the laser liftoff layer; forming a plurality of connectors on the first side of the first semiconductor die to electrically couple to the topmost metallization layer; and bonding the first semiconductor die to a third wafer that includes a second semiconductor die.

TECHNICAL FIELD

This disclosure relates to semiconductor devices and methods of bonding a plural number of semiconductor devices.

BACKGROUND

SUMMARY

At least one aspect of the present disclosure is directed to a method for manufacturing semiconductor packages. The method includes providing a first semiconductor die including a plurality of metallization layers; completely overlaying a topmost one of the metallization layers with a barrier layer; completely overlaying the barrier layer sequentially with a stop layer and a laser liftoff layer; attaching a first side of the first semiconductor die to a first wafer through at least the laser liftoff layer; attaching a second side of the first semiconductor die to a second wafer; removing the first wafer from the first semiconductor die through the laser liftoff layer; forming a plurality of connectors on the first side of the first semiconductor die to electrically couple to the topmost metallization layer; and bonding the first semiconductor die to a third wafer that includes a second semiconductor die.

In some embodiments, the second semiconductor die includes a plurality of second metallization layers and a plurality of second connectors. The step of bonding the first semiconductor die to a third wafer comprises connecting at least one of the plurality of connectors to a corresponding one of the plurality of second connectors.

In some embodiments, prior to forming the plurality of connectors, the method further includes forming a plurality of vias extending through the barrier layer to be in contact with the topmost metallization layer. Each of the plurality of vias is in contact with a corresponding one of the plurality of connectors.

In some embodiments, the step of removing the first wafer includes applying a laser from the first side of the of the first semiconductor die to cause thermochemical dissociation of the laser liftoff layer. The method further includes polishing out any remaining portion of the laser liftoff layer until the stop layer is exposed.

In some embodiments, the step of attaching a second side of the first semiconductor die to a second wafer includes forming a first bonding layer over the second side of the first semiconductor die; planarizing the first bonding layer using a laser; forming a second bonding layer over the second wafer; and bonding the first bonding layer to the second bonding layer. The step of forming a first bonding layer, the step of planarizing the first bonding layer, and the step of bonding the first bonding layer to the second bonding layer are each performed in an elevated temperature.

In some embodiments, the step of forming a plurality of connectors on the first side of the first semiconductor die is performed at a temperature not greater than about 250° C.

At least another aspect of the present disclosure is directed to a method for manufacturing semiconductor packages. The method includes bonding a plurality of semiconductor dies to a first wafer on their respective first sides; bonding the plurality of semiconductor dies to a second wafer on their respective second sides; decoupling the first wafer from the plurality of semiconductor dies; forming a plurality of first connecters in electrical contact with the plurality of semiconductor dies that are placed on the second wafer; and bonding the plurality of semiconductor dies to a third wafer by connecting the plurality of first connecters to a plurality of second connectors disposed on the third wafer, respectively.

In some embodiments, the step of forming a plurality of first connecters is performed after any of the step of bonding a plurality of semiconductor dies to a first wafer, the step of bonding the plurality of semiconductor dies to a second wafer, or the step of decoupling the first wafer from the plurality of semiconductor dies. Each of the step of bonding a plurality of semiconductor dies to a first wafer, the step of bonding the plurality of semiconductor dies to a second wafer, and the step of decoupling the first wafer from the plurality of semiconductor dies is performed in an elevated temperature.

In some embodiments, the step of decoupling the first wafer from the plurality of semiconductor dies includes applying a laser through the first wafer on the first sides of the semiconductor dies.

In some embodiments, prior to forming the plurality of first connecters, each of the semiconductor dies includes a plurality of metallization layers; a barrier layer completely overlaying a topmost one of the plurality of metallization layers; a dielectric layer overlaying the barrier layer; a stop layer overlaying the dielectric layer; and a laser liftoff layer overlaying the stop layer. Subsequently to decoupling the first wafer from the plurality of semiconductor dies, the method further includes polishing from the first sides of the semiconductor dies until the stop layer of at least one of the semiconductor dies is exposed; and forming a plurality of vias extending through the barrier layer and the dielectric layer. The plurality of first connectors are electrically coupled to the topmost metallization layer through the plurality of vias, respectively.

In some embodiments, the step of bonding the plurality of semiconductor dies to a third wafer is performed through a hybrid bonding technique.

Yet another aspect of the present disclosure is directed to a method for manufacturing semiconductor packages. The method includes preparing a plurality of semiconductor dies, each of the plurality of semiconductor dies, on its first side, including a plurality of metallization layers, a dielectric layer completely overlaying a topmost one of the metallization layers, a stop layer overlaying the dielectric layer, and a laser liftoff layer overlaying the stop layer; bonding the plurality of semiconductor dies to a first wafer with the respective first sides; bonding the plurality of semiconductor dies to a second wafer with their respective second sides; decoupling, based on causing thermochemical dissociation of the laser liftoff layer of each of the plurality of semiconductor dies, the first wafer from the plurality of semiconductor dies; forming a plurality of vias extending through the dielectric layers to be in contact with the topmost metallization layers, respectively; forming a plurality of first connecters in contact with the plurality of vias, respectively; and bonding the plurality of semiconductor dies to a third wafer by connecting the plurality of first connecters to a plurality of second connectors disposed on the third wafer, respectively.

In some embodiments, each of the step of bonding a plurality of semiconductor dies to a first wafer, the step of bonding the plurality of semiconductor dies to a second wafer, and the step of decoupling the first wafer from the plurality of semiconductor dies is performed in an elevated temperature.

In some embodiments, each of the step of forming a plurality of vias and the step of forming a plurality of first connectors is performed at a temperature not greater than about 250° C.

These and other aspects and implementations are discussed in detail below. The foregoing information and the following detailed description include illustrative examples of various aspects and implementations, and provide an overview or framework for understanding the nature and character of the claimed aspects and implementations. The drawings provide illustrations and a further understanding of the various aspects and implementations, and are incorporated in and constitute a part of this specification. Aspects can be combined, and it will be readily appreciated that features described in the context of one aspect of the invention can be combined with other aspects. Aspects can be implemented in any convenient form. As used in the specification and in the claims, the singular form of “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise.

DETAILED DESCRIPTION

As semiconductor technologies further advance, stacked semiconductor devices, e.g., 3D integrated circuits (3DICs), have emerged as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits and the like are fabricated on different semiconductor wafers. Two or more semiconductor wafers may be installed on top of one another to further reduce the form factor of the semiconductor device.

Two semiconductor wafers or dies may be bonded together through suitable bonding techniques. The commonly used bonding techniques include direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding, hybrid bonding, and/or the like. An electrical connection may be provided between the stacked semiconductor wafers/dies (or stacked semiconductor devices). The stacked semiconductor devices may provide a higher density with smaller form factors and allow for increased performance and lower power consumption.

Of particular interest is hybrid bonding, which requires no specific high-temperature annealing process. In the hybrid bonding technique, a permanent bond combines a dielectric bond (e.g., SiOx) with one or more embedded metal (e.g., Cu) bonds to form interconnections. Hybrid bonding extends fusion bonding with embedded metal pads in the bond interface, which allows face-to-face connection of different semiconductor wafers/dies. However, in the existing technologies, the embedded metal pads of a semiconductor device are typically formed right after a topmost metallization layer of the semiconductor device is formed, i.e., prior to the semiconductor device being processed for bonding to another semiconductor device. One or more of such process steps (e.g., fusion bonding to a carrier/sacrificial substrate, laser planarization, laser liftoff, etc.) typically require a high-temperature annealing process, which can likely damage the metal pads. As such, the existing technologies to bond different semiconductor devices have not been entirely satisfactory in some aspects.

The present disclosure provides various embodiments of a method for bonding semiconductor devices (e.g., dies-to-wafer, wafer-to-wafer, die-to-die) that may advantageously circumvent the above-identified issues. In one aspect of the present disclosure, instead of forming metal pads right after the topmost metallization layer of a to-be bonded semiconductor device, the method, as disclosed herein, may include not forming metal pads (and corresponding via structures connecting them to the topmost metallization layer) until the semiconductor device has progressed through the steps that require a high-temperature annealing process. For example, the semiconductor device may be first bonded to a first carrier/sacrificial wafer through a number of layers completely overlaying the topmost metallization layer, bonded to a second carrier/sacrificial wafer through a bonding layer, and then released from the first carrier/sacrificial wafer. Each of these steps may include a high-temperature annealing process. By arranging the step of forming metal pads after those high-temperature annealing process, the metal pads can advantageously be free from damage induced by the high-temperature annealing process. As such, the disclosed method can solve the technical issues that the existing technologies are facing.

FIG.1illustrates a flowchart of an example method100for forming a semiconductor package with at least one reconstituted wafer having a number of semiconductor dies boned to another wafer through low-temperature hybrid bonding. It is noted that the method100is merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method100ofFIG.1, and that some other operations may only be briefly described herein.

In various embodiments, operations of the method100may be associated with cross-sectional views of an example semiconductor package200at various fabrication stages as shown inFIGS.2to11, respectively, which will be discussed in further detail below. It should be understood that the semiconductor package200, shown inFIGS.2to11, may include a number of other devices such as inductors, fuses, capacitors, coils, etc., while remaining within the scope of the present disclosure.

In brief overview, the method100starts with operation102of providing a number of first semiconductor dies, each of which includes a number of metallization layers formed on its first side. In various embodiments, a topmost one of the metallization layer of each of the first semiconductor dies may be completely overlaid with at least a barrier layer, a stop layer, and a laser liftoff (LLO) layer. The method100proceeds to operation104of attaching the first semiconductor dies to a first (sacrificial) wafer on their first sides. The method100proceeds to operation106of thinning the first semiconductor dies from their respective second sides (e.g., backside). The method100proceeds to operation108of overlaying the first semiconductor dies with an encapsulating layer. The method100proceeds to operation110of planarizing the encapsulating layer. The method100proceeds to operation112of attaching the first semiconductor dies to a second (support) wafer on their second sides. The method100proceeds to operation114of removing the first wafer based on the LLO layer. The method100proceeds to operation116of forming metal connectors on the first side of each of the first semiconductor dies. The method100proceeds to operation118of bonding the first semiconductor dies to a third (semiconductor) wafer that includes a number of second semiconductor dies. In various embodiments of the present disclosure, any operation after operation116(e.g., operation118) may be performed without an annealing process or in a substantially low temperature, for example, not greater than about 250° C.

Corresponding to operation102ofFIG.1,FIG.2is a cross-sectional view of an example first semiconductor die250to be included in the semiconductor package200, at one of the various stages of fabrication, in accordance with various embodiments.

As shown, the first semiconductor die250includes a substrate252, a number of metallization layers254over the substrate252, a barrier layer256over a topmost one of the metallization layers, an interlayer dielectric (ILD) or intermetal dielectric (IMD) material258over the barrier layer256, a stop layer260over the ILD material258, and a laser liftoff (LLO) layer262over the stop layer260. Each of the metallization layers254, disposed on a first side of the substrate252, includes a number of interconnect structures such as, for example, metal lines270and vias272. A bottommost of the metallization layers254is sometimes referred to as M0, with the following metallization layers referred to as M1, M2, etc., respectively, and the topmost metallization layer is sometimes referred to as Mx. In various embodiments of the present disclosure, the barrier layer256(and the following layers258to262) may completely overlay the topmost metallization layer Mx.

The substrate252includes a number of device features/structures253(e.g., transistors, diodes, resistors, etc., which are not shown for the sake of clarity) formed along a surface of the substrate252. Over the surface of the substrate252, a plural number of the metallization layers254, each including a number of interconnect structures (e.g., metal lines270and vias272), can be formed. These interconnect structures across the metallization layers254are configured to electrically connect the device structures to one another so as to form an integrated circuit, which can function as a logic device, a memory device, an input/output device, or the like. The interconnect structures (e.g., formed of conductive materials, such as Cu, Al, W, Ti, TiN, Ta, TaN, or multiple layers or combinations thereof) may be embedded in one or more ILD or IMD materials (e.g., low-k dielectric materials, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like).

Further, on the topmost metallization layer, Mx, the barrier layer256is formed, followed by the formation of ILD/IMD material258, stop layer260, and LLO layer262. The barrier layer256may comprises cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, titanium nitride, and/or combinations thereof, as examples, although alternatively, the barrier layer256may comprise other materials. The ILD/IMD material258may include one or more low-k dielectric materials, such as silicon oxide (SiO2). The stop layer260, which is configured to stop at least one of an etching process or a polishing process, may include a dielectric material such as, for example, silicon nitride (SiN). The LLO layer262can be utilized as a bonding layer to attach the first semiconductor die250to a carrier wafer (which will be illustrated inFIG.3). Further, the LLO layer262can be induced with thermochemical dissociation, upon being applied with a laser, thereby allowing the first semiconductor die250to be later removed from the carrier wafer (which will be illustrated inFIG.8). In some embodiments, the LLO layer262may include a silicon-based dielectric material such as, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, multilayers thereof, or the like, and may be deposited or thermally grown.

Corresponding to operation104ofFIG.1,FIG.3is a cross-sectional view of the semiconductor package200in which a number of the first semiconductor die250are bonded to a sacrificial wafer300, at one of the various stages of fabrication, in accordance with various embodiments.

In some embodiments, the first semiconductor die250can be bonded to the sacrificial wafer300to form a reconstituted wafer. It should be noted that the reconstituted wafer at the current stage may not be completely finished, i.e., one or more components will be removed or added. For example inFIG.3, each of the first semiconductor die250is flipped and attached to the sacrificial wafer300, with their respective metallization layers254and the overlaying layers256to262interposed therebetween. Further, the first semiconductor die250may be bonded to the sacrificial wafer300through a fusion bonding process. The fusion bonding process may involve bringing the first semiconductor die250and the sacrificial wafer300into intimate contact, which causes them to hold together due to atomic attraction forces (i.e., Van der Waal forces). The first semiconductor die250and the sacrificial wafer300may be subjected to an annealing process, after which a solid bond may be formed between the first semiconductor die250and the sacrificial wafer300. A temperature for the annealing process may be any suitable temperature, such as between about 250° C. and about 350° C. The fusion bonding process may arise from SiO2(oxide)/Si bonding, Si/Si bonding, and/or other suitable bonding. In some embodiments, an optional bonding layer320(e.g., formed of silicon oxide) may be formed over the sacrificial wafer300.

Corresponding to operation106ofFIG.1,FIG.4is a cross-sectional view of the semiconductor package200in which a polishing process401is performed from backsides of the first semiconductor die250, at one of the various stages of fabrication, in accordance with various embodiments.

With each of the first semiconductor die250having a respective thickness (or height) as shown inFIG.3, the polishing process401may polish the first semiconductor dies250from their backsides. As such, a level (virtual) surface may be formed by respective polished bottom surfaces of the first semiconductor die250, as shown inFIG.4. The polishing process401may include a chemical mechanical polishing (CMP) process, in some embodiments.

Corresponding to operation108ofFIG.1,FIG.5is a cross-sectional view of an the semiconductor package200in which an encapsulating layer500may be formed over the first semiconductor dies250, at one of the various stages of fabrication, in accordance with various embodiments.

The encapsulating layer500, formed over the reconstituted wafer300, may be continuously around each of the semiconductor dies250. In some embodiments, the encapsulating layer500, which may be deposited or thermally grown at an elevated temperature (e.g., higher than 250° C.), may include epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO) or a combination thereof, with or without filler embedded therein. The filler may include carbon filler or glass filler. In some embodiments, the encapsulating layer500may include a silicon-based dielectric material such as, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, multilayers thereof, or the like.

Corresponding to operation110ofFIG.1,FIG.6is a cross-sectional view of the semiconductor package200in which a polishing process601may be performed on the encapsulating layer500, at one of the various stages of fabrication, in accordance with various embodiments.

As shown inFIG.5, upon being formed, the encapsulating layer500may present a non-even surface. In order to bond the reconstituted wafer to another wafer (e.g., a support wafer which will be shown below), the non-even surface of the encapsulating layer500may be polished using the polishing process601. Accordingly, the surface of the encapsulating layer500opposite to its other surface contacting the sacrificial wafer300may be leveled. In some embodiments, the polishing process601may include a laser polishing process. Such a laser polishing process can include applying a laser beam with very high power densities in pulse form, which is typically performed at an elevated temperature (e.g., higher than 250° C.).

Corresponding to operation112ofFIG.1,FIG.7is a cross-sectional view of the semiconductor package200in which the reconstituted wafer (including the first semiconductor dies250bonded to the sacrificial wafer300) is attached to a support wafer700, at one of the various stages of fabrication, in accordance with various embodiments.

The reconstituted wafer may be bonded to the support wafer700through a fusion bonding process. The fusion bonding process may involve bringing the reconstituted wafer and the support wafer700into intimate contact, which causes them to hold together due to atomic attraction forces (i.e., Van der Waal forces). The reconstituted wafer and the support wafer700may be subjected to an annealing process, after which a solid bond may be formed between the reconstituted wafer and the support wafer700(e.g., between the encapsulating layer500and the support wafer700). A temperature for the annealing process may be any suitable temperature, such as between about 250° C. and about 350° C. The fusion bonding process may arise from SiO2(oxide)/Si bonding, Si/Si bonding, and/or other suitable bonding. In some embodiments, an optional bonding layer720(e.g., formed of silicon oxide) may be formed between the encapsulating layer500and the support wafer700.

Corresponding to operation114ofFIG.1,FIG.8is a cross-sectional view of the semiconductor package200in which the sacrificial wafer300is removed from a remaining portion of the reconstituted wafer, at one of the various stages of fabrication, in accordance with various embodiments.

The sacrificial wafer300may be removed through a laser liftoff (LLO) process. In such a LLO process, optical energy (e.g., a laser beam)810irradiates the reconstituted wafer through a first surface of the sacrificial wafer300with the radiation passing through the sacrificial wafer300and to an interface between a second, opposite surface of the sacrificial wafer300and the first semiconductor dies250, e.g., between the second surface of the sacrificial wafer300and the LLO layer262(FIG.2) disposed over each of the first semiconductor dies250. In various embodiments, the sacrificial wafer300may be optically transparent to a wavelength of the optical energy810. As a non-limiting example, the laser radiation incident upon the sacrificial wafer300may be 248 nm radiation from a KrF pulsed excimer laser having a pulse width of 38 ns. The energy, passing through the sacrificial wafer300, is then absorbed by the LLO layer262which causes thermochemical dissociation in the LLO layer262. The first semiconductor dies250(while still being bonded to the support wafer700) can be released, disconnected, or otherwise decoupled from the sacrificial wafer300. Accordingly, the LLO layer262may sometimes be referred to as a release layer. The LLO process can be performed in either vacuum, air, or other ambient environment, and, in general, is performed at an elevated temperature (e.g., higher than 250° C.).

Corresponding to operation116ofFIG.1,FIG.9is a cross-sectional view of the semiconductor package200in which a polishing process901may be performed on the first semiconductor dies250until their stop layers260are exposed, at one of the various stages of fabrication, in accordance with various embodiments.

The polishing process901may include a chemical mechanical polishing (CMP) process, which may not be stopped until the stop layers260are exposed, in some embodiments. For example, after decoupling from the sacrificial wafer300(FIG.8), respective remaining portions of the LLO layers262may still be present over the first semiconductor dies250. The polishing process901can polish out such remaining portions until the stop layers260are exposed. Alternatively stated, the stop layers260may be configured to stop the polishing process901. Upon being exposed, the stop layers260may be removed to expose the ILD material258. Next, a number of metal connectors (e.g., bond pads and corresponding vias) can be formed to extend through the ILD material258and the barrier layer256to be in contact with the interconnect structures disposed in the topmost metallization layer Mx of each first semiconductor die250, as illustrated inFIG.10.

FIG.10illustrates a cross-sectional view of one of the first semiconductor dies250that are bonded to the support wafer700, in which a number of vias1070and a number of bond pads1072are formed over the topmost metallization layer Mx. The vias1070and bond pads1072may each be formed of one or more conductive materials, such as Cu, Al, W, Ti, TiN, Ta, TaN, or multiple layers or combinations thereof. The vias1070and bond pads1072may be formed by one or more damascene processes performed on the re-exposed ILD material258. After forming the bond pads1072(as shown inFIG.10), the first semiconductor dies250can have a bonding surface1050including both at least one dielectric material (e.g., the ILD material258) and at least one metal material (e.g., the bond pads1072). Such a hybrid bonding surface along each of the first semiconductor dies250allows the reconstituted wafer (the first semiconductor dies250bonded to the support wafer700) to be bonded to another wafer that may also include a number of (e.g., second) semiconductor dies through a hybrid bonding process that is typically performed at a relatively low temperature (e.g., not greater than 250° C.). As such, the metal connectors may be immune from potential heat damage.

Corresponding to operation118ofFIG.1,FIG.11is a cross-sectional view of the semiconductor package200in which the first semiconductor dies250are bonded to a semiconductor wafer1100that can also include a number of second semiconductor dies, at one of the various stages of fabrication, in accordance with various embodiments. For clarity, the second semiconductor dies bonded, attached, or otherwise integrated to the semiconductor wafer1100are not shown, but it should be appreciated that each of such second semiconductor dies is substantially similar to the first semiconductor die250. For example, each of the second semiconductor dies can have a hybrid bonding surface (e.g., a combination of dielectric material and metal material), which collectively form a bonding surface1150. As such, the bonding surface1050and bonding surface1150can be connected (bonded) to each other through a hybrid bonding process.