Semiconductor device and fabrication method thereof

A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of Taiwan Patent Application No. 97110055, filed on Mar. 21, 2008, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for fabricating a semiconductor device, and in particular relates to a method for fabricating a semiconductor device for increasing operation voltage.

2. Description of the Related Art

High voltage MOS transistors are widely used in many electronic devices, such as central processing unit voltage supply devices, power supply manager system devices and AC/DC inverters and the like. Because high voltage MOS transistors are usually operated under high operation voltage, a high electric field may be formed, resulting in a large number of hot electrons near the junction region of the channel and the drain. The hot electrons will excite the electrons near the drain to the conduction band to form an electron-hole pair, thereby affecting covalent electrons near the drain. Most of the electrons ionized by hot electrons may move to the drain to increase drain current (Isub), and a small portion of the ionized electrons may be injected into and trapped by the gate oxide, resulting in changing the threshold voltage of a gate electrode. Additionally, the holes resulting from hot electrons may flow to the substrate to produce a drain current (Isub). Thus, when the operation voltage increase, the number of electron-hole pair increases and results in “carrier multiplication”.

FIG. 1shows a cross-section view of a traditional high voltage MOS transistor with a lateral diffused drain. AsFIG. 1shows, a high voltage MOS transistor130is formed on a semiconductor wafer110. The semiconductor wafer110has a P-type silicon substrate111and a P-type epitaxial layer112formed on the P-type silicon substrate111. The high voltage MOS transistor130has a P-type well121, N-type source region122formed in the P-type well121, an N-type drain region124formed in the P-type epitaxial layer112, and a gate electrode114.

When the drain current mentioned above flows through the P-type silicon substrate111, the resistance (Rsub) of the P-type silicon substrate111may produce an induced voltage (Vb). If the induced voltage is large enough, forward bias may occur between the P-type silicon substrate111and the source region122to form a parasitic bipolar transistor140. When the parasitic bipolar transistor140is turned on, the current from the drain region124flowing to source region122is rapidly increased, resulting in electrical breakdown to cause the high voltage MOS transistor130to malfunction.

In some high voltage MOS devices, in order to provide a high voltage, “double diffused drain” structures are used in the source and drain.FIG. 2shows a high voltage MOS transistor with a double diffused drain structure disclosed by U.S. Pat. No. 5,770,880. A substrate210has an N-type body212. A gate220on a gate oxide222is formed between a source230and a drain240. The source and drain are substantially the same and interchangable, therefore only the drain is described in the flowing. Every drain has a double diffuse region comprising a first heavily doped contact region214and a lightly doped region216. The diffusion regions are formed by implanting P-type ions such as boron into the exposed surface of the substrate after forming an open219on the oxide layer and performing an annealing process to make P-type ions diffuse into the substrate210to form the doped regions214and216. The contact region214is usually limited on the surface of the N-type body212and do not extend into the N-type body212. The second lightly doped region216extends into the N-type body212and a portion of the second lightly doped region216is under the gate electrode220. A junction region is formed between the doped region216and N-type body212and the junction region determines the breakdown voltage value of the device. The diffusion doped region216, having a low doping concentration gradient, may decrease the reverse bias electric field near the body-drain junction region. Specifically, this allows the device to operate under a high voltage before reaching the breakdown voltage. However, fabricating the device mentioned above requires a complicated process and additional masks may be needed, thus increasing costs. Therefore, a new semiconductor device and a fabrication method thereof are needed to improve the breakdown voltage of the device without incurring extra costs.

BRIEF SUMMARY OF THE INVENTION

The invention provides a method for fabricating a semiconductor device, comprising: providing a semiconductor substrate; forming a first type well in the semiconductor substrate; and forming a second type well and a plurality of junction regions in the semiconductor substrate, wherein each of the junction region is between the first and the second type wells, and adjoins the first and the second type wells.

The invention also provides a semiconductor device, comprising: a semiconductor substrate comprising a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells; a gate electrode on the semiconductor substrate and overlies at least two of the junction regions; and a source and a drain in the semiconductor substrate are oppositely adjacent to the gate electrode.

DETAILED DESCRIPTION OF THE INVENTION

Reference will be made in detail to the present embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness of one embodiment may be exaggerated for clarity and convenience. This description will be directed in particular to elements forming part of, or cooperating more directly with, apparatus in accordance with the present invention. It is to be understood that elements not specifically shown or described may take various forms well known to those skilled in the art. Further, when a layer is referred to as being on another layer or “on” a substrate, it may be directly on the other layer or on the substrate, or intervening layers may also be present.

FIGS. 3-9are cross section views illustrating the step for fabricating a semiconductor device according to an embodiment of the invention.

Referring toFIG. 3, first, a semiconductor substrate such as a P-type substrate100is provided. The P-type substrate100is preferably a silicon substrate. In other embodiments, the P-type substrate100comprises SiGe, silicon on insulator (SOI) substrate or other semiconductor material substrates. Then, a lithography process is performed and a photoresist layer15ais applied on the P-type substrate100. After that, a mask500, comprising an opaque area60and a transparent area61, is provided. Light5is then made to pass through mask500to perform an exposure process to transfer a pattern on the mask500onto the photoresist layer15aon the P-type substrate100.

AsFIG. 4shows, a development is performed and a portion of the photoresist layer15awhich is not covered by opaque area60is removed to form a patterned photoresist layer15b. The patterned photoresist layer15bis used to define a predetermined area of the first type ion implant region16.

FIG. 5illustrates the P-type substrate100, wherein a first type ion implant is performed by using the patterned photoresist layer15bas a mask to form a first type well102in the P-type substrate100. The first type ions mentioned above may be N-type or P type ions.

In the embodiment, the steps of forming a mask500comprise first providing a first integrated circuit layout database comprising data of the first type well and then forming the mask500by using the first integrated circuit layout database.

Referring toFIG. 6A, after removing the patterned photoresist layer15b, a photoresist layer18is blanketly deposited on the P-type substrate100. After that, a mask600comprising an opaque area70and a transparent area71is provided. Light6is then made to pass through mask600to perform an exposure process to transfer a pattern on the mask600onto the photoresist layer18on the P-type substrate100.

AsFIG. 7shows, a development is performed and a portion of the photoresist layer18which is not covered by the opaque area70is removed to form a patterned photoresist layer19. The patterned photoresist layer19is used to define predetermined areas of the second type ion implant region21and junction region22. A second type ion implant is performed on the P-type substrate100by using the patterned photoresist layer19as a mask to form a second type well104and a plurality of junction regions106ain the P-type substrate100. The second type ions mentioned above may be N-type or P type ions and have an opposite conductive type to the first type ions. It is noted that, the mask600and the mask500have patterns which are complementary to each other. Therefore, by adjusting ranges of opaque areas and transparent areas of the two masks, the plurality of junction regions106amay be formed between the first type well102and the second type well104and each of the junction regions adjoins the first and the second type wells. The steps of forming the mask600comprise providing a second integrated circuit layout database comprising data of the first type well102, data of the second type well104and data of the plurality of junction regions106a, then accessing the second integrated circuit layout database and performing a Boolean logic operation to obtain an operation result, and finally using the operation result to form the mask600. The length of the plurality of junction regions is about 0.2-5 μm, preferably 0.5-1.5 μm.

Referring toFIGS. 3-7again, in the embodiment, an additional opaque area (Fig. not shown) is formed between opaque areas60and70by reducing the opaque range of the opaque areas60(asFIG. 3shown) of the mask500or the opaque areas70of the mask600(asFIG. 6Ashown). This may laterally extend the range of the first type well102and the second type well104, resulting in edges of the first type well102and the second type well104having doped overlapped regions. Therefore, after completing the first ion implant20and the second ion implant30, respectively, a plurality of junction regions106a, which are both doped with the first and second type ions, may be formed. In one embodiment, the implant dosage of the first type ion implant20is greater than that of the second type ion implant30, and thus a lightly doped first type ion region may be formed in the junction regions106. In other embodiment, a lightly doped second type ion region may be formed in the junction regions by doping second type ions having a concentration higher than that of the first type ions.

FIG. 5andFIG. 6Billustrate another embodiment of forming junction regions in the P-type substrate100. Compared with the embodiment inFIG. 7, the opaque range of the opaque area80of the mask700is larger than that of the opaque area70of the mask600, and thus the range of the first type well102and the second type well104may be laterally reduced to form a plurality of junction regions106bwithout doping the first and second type ions mentioned above, after completing the first ion implant20and the second ion implant40. In other words, the junction regions have substantially the same conductive type with the P-type substrate100.

FIG. 7andFIG. 8illustrate a plurality of isolation structures, such as a shallow trench isolation (STI) structure74, formed in the P-type substrate100to define a device region200. In general, the steps of forming the shallow trench isolations comprise forming a trench, filling the trench with a dielectric material such as a high-density plasma oxide, and then performing a planarization process such as a chemical mechanical polishing process to remove the excess dielectric material to form the shallow trench isolations. However, the isolation structures may also be field oxides (FOX) formed by local oxidation of silicon.

FIG. 9illustrates a MOS device116formed on device region200. The MOS device116further comprises a gate dielectric layer125. In one preferred embodiment, the gate dielectric layer125comprises an oxide layer, and the gate dielectric layer125may be formed by a process such as a dry or wet thermal oxidation oxide process in the atmosphere with oxide, water, NO or the combinations thereof, or by a CVD process using tetraethoxysilane (TESO) and oxygen as a precursor. The steps of forming the MOS device116comprise first forming a gate electrode120on the P-type substrate100, wherein the gate electrode120overlies at least two of the junction regions106a, then forming a source123and a drain124in the semiconductor substrate which is oppositely adjacent to the gate electrode. The source123and drain124may be formed by well-known ion implant processes and the source123and drain124have the same conductive type with the first type well102.

The gate electrode120preferably comprises the conductive material of Ta, Ti, Mo, W, Pt, Al, Hf, Ru, or silicide or nitride thereof. In one preferred embodiment, the gate electrode120is composed of polysilicon and may be formed by depositing doped or undoped polysilicon through a CVD process.

The gate electrode120and gate dielectric layer125may be patterned, for example, by a lithography process. In general, the lithography process comprises applying a photoresist material, then masking, exposing, and developing the photoresist material to form a photoresist mask. After patterning the photoresist mask, an etch process is performed to remove the unwanted portion, thus forming the gate electrode120and gate dielectric layer125mentioned above.

Similarly, in other embodiments, using the method mentioned above, a MOS device116may be formed with a gate electrode120, a gate dielectric layer125, a source123, and a drain124on the P-type substrate100of the embodiment inFIG. 6B, wherein the gate electrode120overlies at least two of the junction regions106b(not shown).

It is noted that because the junction regions106aand106bare between the first type well102and the second type well104, the PN junctions may be formed between the second type well104under the source123and the second type well104under the gate electrode120, and between the second type well104under the drain124and the second type well104under the gate electrode120, respectively. A depletion region may be formed in the second type well104under the source123and/or drain124and gate electrode120by the PN junctions. With the depletion region, breakdown voltage may increase during operation and the range of operation voltage of the device may be increased.

Referring toFIGS. 10A and 10B, under different gate operation voltage, drain voltage-drain current measurement values of a traditional semiconductor device and an embodiment of semiconductor device of the invention, respectively, are shown. AsFIG. 10Ashows, the gate operation voltage (Vg) is about 0-45 V. However, as shown inFIG. 10B, the gate operation voltage (Vg) of an embodiment of semiconductor device of the invention may be raised to about 0-60 V. Specifically, compared with the conventional semiconductor device, the range of the gate operation voltage may be raised to 30% by using the embodiment of semiconductor device of the invention. Moreover, an additional process is not needed in the method for fabricating the embodiment of semiconductor device. Processes substantially the same with well-known processes may be used, and thus, costs are not increased.