A fast latching flip-flop has a transparent latch master section with an input amplifier, an output latch, a current source connected to provide current for the input amplifier and the output latch, and a switch for applying the current from the current source to either the input amplifier or the output latch. A slave section is connected to the output latch to transfer the data from the output latch to the output of the fast latching flip-flop. A delay transistor is inserted between the switch and the input amplifier to add delay in the turn-off of the input amplifier. Additional delay is attained by connecting a plurality of diode-connected transistors to the junction of the delay transistor and the switch. The result is a reduction of the metastable region between the turn-off of the input amplifier and the turn-on of the output latch.

BACKGROUND OF THE INVENTION 
The present invention relates to flip-flops, and more particularly to a 
fast latching flip-flop for higher frequency clocking and faster data 
latching with a shortened metastable region. 
In digital systems where input signals come from different sources with no 
common time reference, signals may occur which are not logically defined. 
The interactions between these systems are asynchronous. An example is a 
test instrument, such as a logic analyzer, which has an internal clock to 
provide internal synchronization but which samples signals from devices 
under test having an unrelated clock. This means that data samples taken 
by the test instrument are random in time with respect to the internal 
clock, and an input signal may change during a sample clock edge of the 
internal clock. To prevent system failure a synchronizer, such as a 
flip-flop, is used at the input to the test instrument to provide reliable 
communication between asynchronous systems. 
In an ECL master-slave D-type flip-flop there is a transparent data input 
amplifier followed by a latch. In operation the data is input to the input 
amplifier and transferred to the latch at the leading edge of a clock 
pulse. The clock pulse turns off the input amplifier and turns on the 
latch. Due to the parasitic capacitances of the components there is a 
period of time during which the input amplifier is off before the latch is 
on. During this period new data at the input will not be transferred to 
the latch, or will cause the latch to make an erroneous or random 
decision. This period commonly is referred to as the metastable region. A 
typical flip-flop of this type has a metastable region on the order of 600 
picoseconds. However, where an acquisition accuracy for the data of 0.5 
nanoseconds is desired, a metastable region of much shorter duration is 
desired. 
SUMMARY OF THE INVENTION 
Accordingly the present invention provides a fast latching ECL flip-flop 
having a significantly reduced metastable region. An entirely differential 
master-slave flip-flop has the master and slave sections operating on 
opposite phases of a differential clock. The master section has a 
differential data input amplifier with an associated current source 
enabled during one phase of the differential clock and a latch with an 
associated current source enabled during the other phase of the 
differential clock. Inserted between the data input amplifier and its 
associated current source is a common base transistor which introduces a 
delay between the time the differential clock turns off the current source 
and the time the current stops flowing in the data input amplifier. Also 
at the junction of the delay transistor and the current source is inserted 
a plurality of diode-connected transistors to add additional capacitance 
which increases the delay for the turn-off of the data input amplifier. 
Thus, by decreasing the time between turn-off of the data input amplifier 
and the turn-on of the latch, the metastable region is decreased. 
The objects, advantages and novel features of the present invention will be 
apparent from the following detailed description when read in conjunction 
with the appended claims and attached drawing.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring now to FIG. 1 a typical representation for a D-type flip-flop 10 
is shown. The data is input at the D input on the master side 12, whereas 
in the single-sided circuit of the prior art the /D input was tied to a 
fixed voltage Vd as indicated by the dotted line from /D. Various bias and 
supply voltages are applied to the flip-flop 10, such as collector voltage 
Vcc, emitter voltage Vee base reference voltage V, and current source 
reference voltage Vcs. A differential clock is input to the clock inputs C 
and /C with the rising edge of C latching the data into the master side 12 
and the rising edge of /C (falling edge of C) latching the data into the 
slave side 14 at the Q and /Q outputs. In the circuits of the prior art a 
reset, indicated by a dotted line, has been provided at the master side. 
As indicated in FIG. 2 the circuitry within the flip-flop 10 is entirely 
differential, i.e., the /D input is a data input instead of being tied to 
a fixed voltage Vd as in the prior art and the reset of the prior art has 
been deleted. The flip-flop 10 has an input amplifier 16 which receives 
the data input D and /D. The output of the input amplifier 16 is 
transferred to a master latch 18 via master amplifiers 20. A master 
current source 22 provides current for both the input amplifier 16 and the 
master latch 18. A master control switch 24 between the master current 
source 22 and the input amplifier 16 and master latch 18 combination 
determines whether the amplifier or the latch conducts current. The master 
control switch 24 is switched by the differential clock C and /C via 
respective buffer amplifiers 26 and 28. As indicated by dotted lines a 
reset amplifier 30 was inserted between the master control switch 24 and 
the master latch 18 in circuits of the prior art. 
On the slave side 14 the contents of the master latch 18 are received by an 
output amplifier 32 and are transferred to a slave latch 34 via slave 
amplifiers 36. A slave current source 38 provides the current for the 
output amplifier 32 and the slave latch 34 combination via a slave control 
switch 40 which is switched by the differential clock C and /C via the 
buffer amplifiers 26, 28. 
Referring to FIG. 3 when the differential clock C, /C transitions, the 
falling edge of /C turns off the current through the input amplifier 16, 
as indicated at node A, and enables the master latch 18. Due to the 
charging of parasitic and junction capacitances on the master switch 24 
transistors and the current source 22 transistor, particularly the 
collector/base capacitance Ccb, there is a time when current is applied to 
neither node A nor B. It is this period of time which defines the period 
during which operation of the flip-flop 10 is unreliable, i.e., the 
metastable region. To decrease this metastable region it is necessary to 
either speed up the turn-on of the master latch 18 or slow down the 
turn-off of the input amplifier 16, or a combination of both. 
The first step in decreasing the metastable region is to remove the reset 
amplifier 30 from the master latch 18 circuit since the reset amplifier 
serves to introduce a delay into the turn-on of the master latch 18. By 
the same token inserting a delay transistor 42 between the input amplifier 
16 and the master control switch 24 serves to introduce a delay into the 
turn-off of the input amplifier. Additional delay is added by connecting a 
plurality of diode-connected transistors 44 to the junction of the delay 
transistor 42 and the master control switch 24, effectively adding 
additional parasitic collector-base capacitance to delay the turn-off of 
the input amplifier 16. The result is indicated in FIG. 3 where the arrows 
indicate how the turn-off and turn-on times at nodes A and B are shifted, 
resulting in a fast metastable region considerably smaller than that 
attainable using a conventional flip-flop. 
Thus the present invention provides a fast latching flip-flop which reduces 
the metastable region by adding delay into the turn-off of the input 
amplifier through use of a delay transistor and a plurality of 
diode-connected transistors which add parasitic capacitance.