EFFICIENT CACHE USAGE IN AN IMAGE PROCESSING SYSTEM

This disclosure provides systems, methods, and devices for image signal processing that support efficient cache usage in an image processing system. In a first aspect, a method of image processing includes storing, by an image processor, a first portion of a first stripe of a first frame in a cache, the first portion of the first stripe overlapping a second portion of a second stripe of the first frame, reading, by the image processor, a third portion of the second stripe from a memory, reading, by the image processor, the first portion of the first stripe from the cache, and processing, by the image processor, the second stripe using the first portion of the first stripe and the third portion of the second stripe. Other aspects and features are also claimed and described.

TECHNICAL FIELD

Aspects of the present disclosure relate generally to image processing, and more particularly, to enhanced image processing efficiency. Some features may enable and provide improved image processing, including efficient cache usage in an image processing system.

INTRODUCTION

Image capture devices are devices that can capture one or more digital images, whether still images for photos or sequences of images for videos. Capture devices can be incorporated into a wide variety of devices. By way of example, image capture devices may comprise stand-alone digital cameras or digital video camcorders, camera-equipped wireless communication device handsets, such as mobile telephones, cellular or satellite radio telephones, personal digital assistants (PDAs), panels or tablets, gaming devices, computing devices such as webcams, video surveillance cameras, or other devices with digital imaging or video capabilities.

The amount of image data captured by an image sensor has increased through subsequent generations of image capture devices. The amount of information captured by an image sensor is related to a number of pixels in an image sensor of the image capture device, which may be measured as a number of megapixels indicating the number of millions of sensors in the image sensor. For example, a 12-megapixel image sensor has 12 million pixels. Higher megapixel values generally represent higher resolution images that are more desirable for viewing by the user.

The increasing amount of image data captured by the image capture device has some negative effects that accompany the increasing resolution obtained by the additional image data. Additional image data increases the amount of processing performed by the image capture device in determining image frames and videos from the image data, as well as in performing other operations related to the image data. For example, the image data may be processed through several processing blocks for enhancing the image before the image data is displayed to a user on a display or transmitted to a recipient in a message. Each of the processing blocks consumes additional power proportional to the amount of image data, or number of megapixels, in the image capture. The additional power consumption may shorten the operating time of an image capture device using battery power, such as a mobile phone.

Image data loaded from a memory of an image capture device for processing by one or more processing elements of the image capture device, such as by an image signal processor, may be stored in a cache for efficient access by the image signal processor. Cache space of an image signal processor may, however, be limited. With increasing amounts of image data being stored and processed, efficient usage of cache storage has become increasingly important. As one particular example, whole frames may be stored in a cache for processing by multiple cores of an image processor.

BRIEF SUMMARY OF SOME EXAMPLES

In some aspects, an image frame may be divided into multiple vertical sections, referred to herein as stripes, for efficient processing. At least a portion of each stripe may overlap with adjacent stripes to preserve continuity in image processing. A section of a first stripe of a frame that overlaps a section of an adjacent second stripe of the frame may be loaded from memory for processing the stripe and stored in a cache. The overlapping section of the first stripe stored in the cache may then be read from the cache for processing the second stripe of the frame that includes the overlapping section. Thus, instead of reading the overlapping section of the stripe from memory multiple times for processing stripes that include the overlapping portion, the overlapping portion of the stripe may be read from memory a single time, stored in a cache, and read from the cache for processing of a subsequent stripe that includes the overlapping portion of the stripe. After the overlapping section has been read from the cache a final time for processing of a final stripe that includes the overlapping section, the overlapping section stored in the cache may be invalidated, such as forgotten, erased, and/or evicted from the cache. Cache usage efficiency may be further enhanced through invalidation of stripe data stored in the cache after a final read of the stripe data from the cache in other contexts. For example, in performing multi-pass processing using multiple resolutions of an image frame, metadata associated with a stripe of a first resolution of an image frame may be stored in a cache until all stripes of a second resolution of the image frame that depend on the metadata associated with the stripe of the first resolution of the image frame are processed. The metadata associated with the stripe of the first resolution stored in the cache may then be invalidated. Efficiency may be further enhanced through reordering of processing of stripes of different resolutions of a frame, such that all stripes of the second resolution of the frame that depend on metadata associated with the stripe of the first resolution of the frame are processed before processing of another stripe of the first resolution of the frame. As another example, processing using a reference frame, such as motion processing, may include storing a stripe of a reference frame in a cache for use in processing stripes of a current frame being processed using the stripe of the reference frame and invalidating the stripe of the reference frame in the cache based on a greatest motion vector between the reference frame and the current frame.

Efficient cache usage in an image processing system may include storage of overlapping sections of stripes of an image frame in a cache until such sections have been read for processing of a last stripe including the sections, at which point the sections of the stripes stored in the cache will be invalidated. Such storage may enhance cache usage efficiency by reducing a number of write operations to a cache and reducing an amount of cache space used for storage of image stripes. Furthermore, reading an overlapping section of a stripe for processing a second stripe including the overlapping section from the cache rather than from the memory may consume less power and may be performed in less time, reducing power usage and latency. Storage of metadata associated with stripes of a first resolution of an image frame only until processing of stripes of a second resolution of the image frame that depend the metadata is complete may also reduce cache usage, as metadata stored in the cache may be invalidated after a final read of the metadata from the cache. Furthermore, reordering of stripes of a second resolution of an image frame that depend on metadata associated with the stripe of the first resolution of the image frame to be processed sequentially following storage of the metadata in the cache may further reduce cache usage, as the metadata associated with the stripe of the first resolution of the image frame may be stored in the cache for a reduced period of time because stripes of the second resolution of the image frame that depend on the metadata will be prioritized for processing. Invalidating stripes of a reference frame stored in a cache based on a largest motion vector between the reference frame and a currently processed frame may further reduce cache usage, as such stripes may be invalidated after a final read of the stripes from the cache.

In one aspect of the disclosure, a method for image processing includes storing, by an image processor, a first portion of a first stripe of a first frame in a cache, the first portion of the first stripe overlapping a second portion of a second stripe of the first frame, reading, by the image processor, a third portion of the second stripe from a memory, reading, by the image processor, the first portion of the first stripe from the cache, and processing, by the image processor, the second stripe using the first portion of the first stripe and the third portion of the second stripe.

In an additional aspect of the disclosure, an apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to perform operations including storing first portion of a first stripe of a first frame in a cache, the first portion of the first stripe overlapping a second portion of a second stripe of the first frame, reading a third portion of the second stripe from a memory, reading, by the image processor, the first portion of the first stripe from the cache, and processing, by the image processor, the second stripe using the first portion of the first stripe and the third portion of the second stripe.

In an additional aspect of the disclosure, an apparatus includes means for storing a first portion of a first stripe of a first frame in a cache, the first portion of the first stripe overlapping a second portion of a second stripe of the first frame, means for reading a third portion of the second stripe from a memory, means for reading the first portion of the first stripe from the cache, and means for processing the second stripe using the first portion of the first stripe and the third portion of the second stripe.

In an additional aspect of the disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform operations. The operations include storing a first portion of a first stripe of a first frame in a cache, the first portion of the first stripe overlapping a second portion of a second stripe of the first frame, reading a third portion of the second stripe from a memory, reading the first portion of the first stripe from the cache, and processing the second stripe using the first portion of the first stripe and the third portion of the second stripe.

In one aspect of the disclosure, a method for image processing includes storing, by an image processor in a cache, metadata associated with a first stripe of a first resolution of a first frame, processing, by the image processor, a plurality of stripes of a second resolution of the first frame using the metadata, and invalidating the metadata in the cache after processing the plurality of stripes.

In an additional aspect of the disclosure, an apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to perform operations including storing, in a cache, metadata associated with a first stripe of a first resolution of a first frame, processing a plurality of stripes of a second resolution of the first frame using the metadata, and invalidating the metadata in the cache after processing the plurality of stripes.

In an additional aspect of the disclosure, an apparatus includes means for storing, in a cache, metadata associated with a first stripe of a first resolution of a first frame; means for processing a plurality of stripes of a second resolution of the first frame using the metadata, and means for invalidating the metadata in the cache after processing the plurality of stripes.

In an additional aspect of the disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform operations. The operations include storing, in a cache, metadata associated with a first stripe of a first resolution of a first frame, processing a plurality of stripes of a second resolution of the first frame using the metadata, and invalidating the metadata in the cache after processing the plurality of stripes.

In one aspect of the disclosure, a method for image processing includes storing, by an image processor in a cache, a first stripe of a first frame, determining, by the image processor, a value of a greatest motion vector associated with the first frame and a second frame, and invalidating, by the image processor, the first stripe of the first frame in the cache based on the determined value of the greatest motion vector.

In an additional aspect of the disclosure, an apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to perform operations including storing, in a cache, a first stripe of a first frame, determining a value of a greatest motion vector associated with the first frame and a second frame, and invalidating the first stripe of the first frame in the cache based on the determined value of the greatest motion vector.

In an additional aspect of the disclosure, an apparatus includes means for storing, in a cache, a first stripe of a first frame, means for determining a value of a greatest motion vector associated with the first frame and a second frame, and means for invalidating the first stripe of the first frame in the cache based on the determined value of the greatest motion vector.

In an additional aspect of the disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform operations. The operations include storing, in a cache, a first stripe of a first frame, determining a value of a greatest motion vector associated with the first frame and a second frame, and invalidating the first stripe of the first frame in the cache based on the determined value of the greatest motion vector.

Methods of image processing described herein may be performed by an image capture device and/or performed on image data captured by one or more image capture devices. Image capture devices, devices that can capture one or more digital images, whether still image photos or sequences of images for videos, can be incorporated into a wide variety of devices. By way of example, image capture devices may comprise stand-alone digital cameras or digital video camcorders, camera-equipped wireless communication device handsets, such as mobile telephones, cellular or satellite radio telephones, personal digital assistants (PDAS), panels or tablets, gaming devices, computing devices such as webcams, video surveillance cameras, or other devices with digital imaging or video capabilities.

The image processing techniques described herein may involve digital cameras having image sensor and processing circuitry (e.g., application specific integrated circuits (ASICs), digital signal processors (DSP), graphics processing unit (GPU), or central processing units (CPU)). An image signal processor (ISP) may include one or more of these processing circuits and configured to perform operations to obtain the image data for processing according to the image processing techniques described herein and/or involved in the image processing techniques described herein. The ISP may be configured to control the capture of image frames from one or more images sensors and determine one or more image frames from the one or more image sensors to generate a view of a scene in an output image frame. The output image frame may be part of a sequence of image frames forming a video sequence. The video sequence may include other image frames received from the image sensor or other images sensors.

In an example application, the image signal processor (ISP) may receive an instruction to capture a sequence of image frames in response to the loading of software, such as a camera application, to produce a preview display from the image capture device. The image signal processor may be configured to produce a single flow of output image frames, based on images frames received from one or more image sensors. The single flow of output image frames may include image data from an image sensor, binned image data from an image sensor, or corrected image data processed by one or more algorithms within the image signal processor. For example, an image frame obtained from an image sensor, which may have performed some processing on the data before output to the image signal processor, may be processed in the image signal processor by processing the image frame through an image post-processing engine (IPE) and/or other image processing circuitry for performing one or more of the tone mapping, portrait lighting, contrast enhancement, gamma correction, etc. The output image frame from the ISP may be stored in memory and retrieved by an application processor executing the camera application, which may perform further processing on the output image frame to adjust an appearance of the output image frame and reproduce the output image frame on a display for view by the user.

After an output image frame representing the scene is determined by the image signal processor and/or deter mined by the application processor, such as through image processing techniques described in various embodiments herein, the output image frame may be displayed on a device display as a single still as part of a video sequence, saved to a storage device as a picture or a video sequence, transmitted over a network, and/or printed to and output medium. For example, the image signal processor (ISP) may be configured to obtain input frames of image data (e.g., pixel values) from the one or more image sensors, and in turn, produce corresponding output image frames (e.g., preview display frames, still-image captures, frames for video, frames for object tracking, etc.). In other examples, the image signal processor may output image frames to various output devices and/or cameral modules for further processing, such as for 3A parameter synchronization (e.g., automatic focus (AF), automatic white balance (AWB), and automatic exposure control (AEC), producing a video file via the output frames, configuring frames for display, configuring frames for storage, transmitting the frames through a network connection, etc. Generally, the image signal processor (ISP) may obtain incoming frames from one or more image sensors and produce and output a flow of output frames to various output destinations.

In some aspects, the output image frame may be produced by combining aspects of the image correction of the disclosure with other computational photography techniques such as high dynamic range (HDR) photography or multi-frame noise reduction (MFNR). With HDR photography, a first image frame and a second image frame are captured using different exposure times, different apertures, different lenses, and/or other characteristics that may result in improved dynamic range of a fused image when the two image frames are combined. In some aspects, the method may be performed for MFNR photography in which the first image frame and a second image frame are captured using the same or different exposure times and fused to generate a corrected first image frame with reduced noise compared to the captured first image frame.

In some aspects, a device may include an image signal processor or a processor (e.g., an application processor) including specific functionality for camera controls and/or processing, such as enabling or disabling the binning module or otherwise controlling aspects of the image correction. The methods and techniques described herein may be entirely performed by the image signal processor or a processor, or various operations may be split between the image signal processor and a processor, and in some aspects split across additional processors.

The device may include one, two, or more image sensors, such as a first image sensor. When multiple image sensors are present, the image sensors may be differently configured. For sample, the first image sensor may have a larger field of view (FOV) than the second image sensor, or the first image sensor may have different sensitivity or different dynamic than the second image sensor. In one example, the first image sensor may be a wide-angle image sensor, and the second image sensor may be a tele image sensor. In another example, the first sensor is configured to obtain an image through a first lens with a first optical axis and the second sensor is configured to obtain an image through a second lens with a second optical axis different from the first optical axis. Additionally or alternatively, the first lens may have a first magnification, and the second lens may have a second magnification different from the first magnifications. Any of these or other configurations may be part of a lens cluster on a mobile device, such as where multiple image sensors and associated lenses are located in off et locations on a frontside or a backside of the mobile device. Additional image sensors may be included with larger, smaller, or same field of views. The image processing techniques described herein may be applied to image frames captured from any of the image sensors in a multi-sensor device.

In an additional aspect of the disclosure, a device configured for image processing and/or image capture is disclosed. The apparatus includes means for capturing image frames. The apparatus further includes one or more means for capturing data representative of a scene, such as image sensors (including charge-coupled devices (CCDs). Bayer-filter sensors, infrared (IR) detectors, ultraviolet (UV) detectors, complimentary metal oxide-semiconductor (CMOS) sensors) and time of flight detectors. The apparatus may further include one or more means for accumulating and/or focusing light rays into the one or more image sensors (including simple lenses, compound lenses, spherical lenses, and non-spherical lenses). These components may be controlled to capture the first and/or second image frames input to the image processing techniques described herein.

Other aspects, features, and implementations will become apparent is to those of ordinary skill in the art, reviewing the following description of specific, exemplary aspects in conjunction with the accompanying figures. While features may be discussed relative to certain aspects and figures below, various aspects may include one or more of the advantageous features discussed herein. In other words, while one or more aspects may be discussed as having certain advantageous features, on or more of such features also be used in accordance with the various aspects. In similar fashion, while exemplary aspects may be discussed below as device, system, or method aspects, the exemplary aspects may be implemented in various devices, systems, and methods.

The method may be embedded in a computer-readable medium as computer program code comprising instructions that cause a processor to perform the steps of the method. In some embodiments, the processor may be part of a mobile device including a first network adaptor configured to transmit data, such as images or videos in a recording or as streaming data, over a first network connection of a plurality of network connections; and a processor coupled to the first network adaptor and the memory. The processor may cause the transmission of output image frames described herein over a wireless communications network such as a 5G NR communication network.

DETAILED DESCRIPTION

The present disclosure provides systems, apparatus, methods, and computer-readable media that support image processing, including techniques for efficient cache usage in an image processing system. For example, the present disclosure provides systems, apparatus, methods, and computer-readable media that support efficient caching of image stripes in various image processing contexts.

Particular implementations of the subject matter described in this disclosure may be implemented to realize one or more of the following potential advantages or benefits. In some aspects, the present disclosure provides techniques for reduced cache usage when storing overlapping sections of image stripes in a cache until a final read of the stored overlapping sections from the cache is performed. For example, such storage may reduce cache usage through invalidation of the overlapping image stripe data when it is no longer needed in the cache, may reduce a number of write operations to the cache and cache usage by storing the overlapping section in the cache only once, may reduce power usage and latency through reading the stored overlapping image stripe data from the cache instead of from the memory, and may reduce a number of read operations from the memory by reading the overlapping section of the stripes from the memory only once. In some aspects, the present disclosure provides techniques for reduced cache usage when storing image stripe metadata for an image stripe of a first resolution until a final read of the image stripe metadata for processing of image stripes of a second resolution that depend on the image stripe metadata is complete. For example, such storage may reduce cache usage by invalidating the image stripe metadata after a final read of the image stripe metadata. Efficiency may be further increased by scheduling processing of the image stripes of the second resolution of the image frame that depend on the metadata of the image stripe of the first resolution to complete before processing of subsequent stripes of the first resolution. Furthermore, in some aspects, the present disclosure provides techniques for reduced cache usage when storing an image stripe of a reference frame in a cache and invalidating the image stripe of the reference frame based on a greatest motion vector between the reference frame and a current frame. For example, such storage may reduce cache usage by invalidating the image stripe of the reference frame stored in the cache when the image stripe of the reference frame is no longer needed for processing of a current frame.

In the description of embodiments herein, numerous specific details are set forth, such as examples of specific components, circuits, and processes to provide a thorough understanding of the present disclosure. The term “coupled” as used herein means connected directly to or connected through one or more intervening components or circuits. Also, in the following description and for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the teachings disclosed herein. In other instances, well known circuits and devices are shown in block diagram form to avoid obscuring teachings of the present disclosure.

Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. In the present disclosure, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system.

An example device for capturing image frames using one or more image sensors, such as a smartphone, may include a configuration of one, two, three, four, or more camera modules on a backside (e.g., a side opposite a primary user display) and/or a front side (e.g., a same side as a primary user display) of the device. The devices may include one or more image signal processors (ISPs), Computer Vision Processors (CVPs) (e.g., AI engines), or other suitable circuitry for processing images captured by the image sensors. The one or more image signal processors (ISP) may store output image frames (such as through a bus) in a memory and/or provide the output image frames to processing circuitry (such as an applications processor). The processing circuitry may perform further processing, such as for encoding, storage, transmission, or other manipulation of the output image frames.

As used herein, a camera module may include the image sensor and certain other components coupled to the image sensor used to obtain a representation of a scene in image data comprising an image frame. For example, a camera module may include other components of a camera, including a shutter, buffer, or other readout circuitry for accessing individual pixels of an image sensor. In some embodiments, the camera module may include one or more components including the image sensor included in a single package with an interface configured to couple the camera module to an image signal processor or other processor through a bus.

FIG.1shows a block diagram of a device100for performing image capture from one or more image sensors. The device100may include, or otherwise be coupled to, an image signal processor (e.g., ISP112) for processing image frames from one or more image sensors, such as a first image sensor101, a second image sensor102, and a depth sensor140. In some implementations, the device100also includes or is coupled to a processor104and a memory106storing instructions108(e.g., a memory storing processor-readable code or a non-transitory computer-readable medium storing instructions). The device100may also include or be coupled to a display114and components116. Components116may be used for interacting with a user, such as a touch screen interface and/or physical buttons.

Components116may also include network interfaces for communicating with other devices, including a wide area network (WAN) adaptor (e.g., WAN adaptor152), a local area network (LAN) adaptor (e.g., LAN adaptor153), and/or a personal area network (PAN) adaptor (e.g., PAN adaptor154). A WAN adaptor152may be a 4G LTE or a 5G NR wireless network adaptor. A LAN adaptor153may be an IEEE 802.11 WiFi wireless network adapter. A PAN adaptor154may be a Bluetooth wireless network adaptor. Each of the WAN adaptor152, LAN adaptor153, and/or PAN adaptor154may be coupled to an antenna, including multiple antennas configured for primary and diversity reception and/or configured for receiving specific frequency bands. In some embodiments, antennas may be shared for communicating on different networks by the WAN adaptor152, LAN adaptor153, and/or PAN adaptor154. In some embodiments, the WAN adaptor152, LAN adaptor153, and/or PAN adaptor154may share circuitry and/or be packaged together, such as when the LAN adaptor153and the PAN adaptor154are packaged as a single integrated circuit (IC).

The device100may further include or be coupled to a power supply118for the device100, such as a battery or an adaptor to couple the device100to an energy source. The device100may also include or be coupled to additional features or components that are not shown inFIG.1. In one example, a wireless interface, which may include a number of transceivers and a baseband processor in a radio frequency front end (RFFE), may be coupled to or included in WAN adaptor152for a wireless communication device. In a further example, an analog front end (AFE) to convert analog image data to digital image data may be coupled between the first image sensor101or second image sensor102and processing circuitry in the device100. In some embodiments, AFEs may be embedded in the ISP112.

The device may include or be coupled to a sensor hub150for interfacing with sensors to receive data regarding movement of the device100, data regarding an environment around the device100, and/or other non-camera sensor data. One example non-camera sensor is a gyroscope, which is a device configured for measuring rotation, orientation, and/or angular velocity to generate motion data. Another example non-camera sensor is an accelerometer, which is a device configured for measuring acceleration, which may also be used to determine velocity and distance traveled by appropriately integrating the measured acceleration. In some aspects, a gyroscope in an electronic image stabilization system (EIS) may be coupled to the sensor hub. In another example, a non-camera sensor may be a global positioning system (GPS) receiver, which is a device for processing satellite signals, such as through triangulation and other techniques, to determine a location of the device100. The location may be tracked over time to determine additional motion information, such as velocity and acceleration. The data from one or more sensors may be accumulated as motion data by the sensor hub150. One or more of the acceleration, velocity, and/or distance may be included in motion data provided by the sensor hub150to other components of the device100, including the ISP112and/or the processor104.

The ISP112may receive captured image data. In one embodiment, a local bus connection couples the ISP112to the first image sensor101and second image sensor102of a first camera103and second camera105, respectively. In another embodiment, a wire interface couples the ISP112to an external image sensor. In a further embodiment, a wireless interface couples the ISP112to the first image sensor101or second image sensor102.

The first image sensor101and the second image sensor102are configured to capture image data representing a scene in the field of view of the first camera103and second camera105, respectively. In some embodiments, the first camera103and/or second camera105output analog data, which is converted by an analog front end (AFE) and/or an analog-to-digital converter (ADC) in the device100or embedded in the ISP112. In some embodiments, the first camera103and/or second camera105output digital data.

The digital image data may be formatted as one or more image frames, whether received from the first camera103and/or second camera105or converted from analog data received from the first camera103and/or second camera105.

The first camera103may include the first image sensor101and a first lens131. The second camera may include the second image sensor102and a second lens132. Each of the first lens131and the second lens132may be controlled by an associated an autofocus (AF) algorithm (e.g., AF133) executing in the ISP112, which adjusts the first lens131and the second lens132to focus on a particular focal plane located at a certain scene depth. The AF133may be assisted by depth data received from depth sensor140. The first lens131and the second lens132focus light at the first image sensor101and second image sensor102, respectively, through one or more apertures for receiving light, one or more shutters for blocking light when outside an exposure window, and/or one or more color filter arrays (CFAs) for filtering light outside of specific frequency ranges. The first lens131and second lens132may have different field of views to capture different representations of a scene. For example, the first lens131may be an ultra-wide (UW) lens and the second lens132may be a wide (W) lens. The multiple image sensors may include a combination of ultra-wide (high field-of-view (FOV)), wide, tele, and ultra-tele (low FOV) sensors.

Each of the first camera103and second camera105may be configured through hardware configuration and/or software settings to obtain different, but overlapping, field of views. In some configurations, the cameras are configured with different lenses with different magnification ratios that result in different fields of view for capturing different representations of the scene. The cameras may be configured such that a UW camera has a larger FOV than a W camera, which has a larger FOV than a T camera, which has a larger FOV than a UT camera. For example, a camera configured for wide FOV may capture fields of view in the range of 64-84 degrees, a camera configured for ultra-side FOV may capture fields of view in the range of 100-140 degrees, a camera configured for tele FOV may capture fields of view in the range of 10-30 degrees, and a camera configured for ultra-tele FOV may capture fields of view in the range of 1-8 degrees.

In some embodiments, one or more of the first camera103and/or second camera105may be a variable aperture (VA) camera in which the aperture can be adjusted to set a particular aperture size. Example aperture sizes include f/2.0, f/2.8, f/3.2, f/8.0, etc. Larger aperture values correspond to smaller aperture sizes, and smaller aperture values correspond to larger aperture sizes. A variable aperture (VA) camera may have different characteristics that produced different representations of a scene based on a current aperture size. For example, a VA camera may capture image data with a depth of focus (DOF) corresponding to a current aperture size set for the VA camera.

The ISP112processes image frames captured by the first camera103and second camera105. WhileFIG.1illustrates the device100as including first camera103and second camera105, any number (e.g., one, two, three, four, five, six, etc.) of cameras may be coupled to the ISP112. In some aspects, depth sensors such as depth sensor140may be coupled to the ISP112. Output from the depth sensor140may be processed in a similar manner to that of first camera103and second camera105. Examples of depth sensor140include active sensors, including one or more of indirect Time of Flight (iToF), direct Time of Flight (dToF), light detection and ranging (Lidar), mmWave, radio detection and ranging (Radar), and/or hybrid depth sensors, such as structured light sensors. In embodiments without a depth sensor140, similar information regarding depth of objects or a depth map may be determined from the disparity between first camera103and second camera105, such as by using a depth-from-disparity algorithm, a depth-from-stereo algorithm, phase detection auto-focus (PDAF) sensors, or the like. In addition, any number of additional image sensors or image signal processors may exist for the device100.

In some embodiments, the ISP112may execute instructions from a memory, such as instructions108from the memory106, instructions stored in a separate memory coupled to or included in the ISP112, or instructions provided by the processor104. In addition, or in the alternative, the ISP112may include specific hardware (such as one or more integrated circuits (ICs)) configured to perform one or more operations described in the present disclosure. For example, the ISP112may include image front ends (e.g., IFE135), image post-processing engines (e.g., IPE136), auto exposure compensation (AEC) engines (e.g., AEC134), and/or one or more engines for video analytics (e.g., EVA137).

In some embodiments, the ISP112may further include an optical filtering engines (e.g., OFE138). An image pipeline may be formed by a sequence of one or more of the IFE135, IPE136, OFE138, and/or EVA137. In some embodiments, the image pipeline may be reconfigurable in the ISP112by changing connections between the IFE135, IPE136, OFE138, and/or EVA137. The AF133, AEC134, IFE135, OFE138, IPE136, and EVA137may each include application-specific circuitry, be embodied as software or firmware executed by the ISP112, and/or a combination of hardware and software or firmware executing on the ISP112. In some embodiments, for example, the AF133, the AEC134, the IFE,135, the IPE136, the EVA137, and/or the OFE138may each be assigned to one or more cores of the image signal processor112.

The memory106may include a non-transient or non-transitory computer readable medium storing computer-executable instructions as instructions108to perform all or a portion of one or more operations described in this disclosure. The instructions108may include a camera application (or other suitable application such as a messaging application) to be executed by the device100for photography or videography. The instructions108may also include other applications or programs executed by the device100, such as an operating system and applications other than for image or video generation. Execution of the camera application, such as by the processor104, may cause the device100to record images using the first camera103and/or second camera105and the ISP112.

In addition to instructions108, the memory106may also store image frames. The image frames may be output image frames stored by the ISP112. The output image frames may be accessed by the processor104and/or ISP112for further operations. In some embodiments, the device100does not include the memory106. For example, the device100may be a circuit including the ISP112, and the memory may be outside the device100. The device100may be coupled to an external memory and configured to access the memory for writing output image frames for display or long-term storage. In some embodiments, the device100is a system-on-chip (SoC) that incorporates the ISP112, the processor104, the sensor hub150, the memory106, and/or components116into a single package. The device100may further include a cache160. The cache160may, in some embodiments be a cache for storing data for the ISP112. In some embodiments, the cache160may store data for other components, such as processor104. For example, image data may be stored in the cache160for rapid access by the image signal processor112when processing the image data.

In some embodiments, at least one of the ISP112or the processor104executes instructions to perform various operations described herein, including storing image data in and invalidating image data stored in the cache160. For example, at least one of the ISP112or the processor104may execute the techniques described herein for efficient usage of the cache160. In some embodiments, the processor104may include one or more general-purpose processor cores104A-N capable of executing instructions to control operation of the ISP112. For example, the cores104A-N may execute a camera application (or other suitable application for generating images or video) stored in the memory106that activate or deactivate the ISP112for capturing image frames and/or control the ISP112in the application of efficient cache usage during processing of the image frames. The operations of the cores104A-N and ISP112may be based on user input. For example, a camera application executing on processor104may receive a user command to begin a video preview display upon which a video comprising a sequence of image frames is captured and processed from first camera103and/or the second camera105through the ISP112for display and/or storage. Image processing to determine “output” or “corrected” image frames, such as according to techniques described herein, may be applied to one or more image frames in the sequence.

In some embodiments, the processor104may include ICs or other hardware (e.g., an artificial intelligence (AI) engine such as AI engine124or other co-processor) to offload certain tasks from the cores104A-N. The AI engine124may be used to offload tasks related to, for example, face detection and/or object recognition performed using machine learning (ML) or artificial intelligence (AI). The AI engine124may be referred to as an Artificial Intelligence Processing Unit (AI PU). The AI engine124may include hardware configured to perform and accelerate convolution operations involved in executing machine learning algorithms, such as by executing predictive models such as artificial neural networks (ANNs) (including multilayer feedforward neural networks (MLFFNN), the recurrent neural networks (RNN), and/or the radial basis functions (RBF)). The ANN executed by the AI engine124may access predefined training weights for performing operations on user data. The ANN may alternatively be trained during operation of the image capture device100, such as through reinforcement training, supervised training, and/or unsupervised training. In some other embodiments, the device100does not include the processor104, such as when all of the described functionality is configured in the ISP112.

In some embodiments, the display114may include one or more suitable displays or screens allowing for user interaction and/or to present items to the user, such as a preview of the output of the first camera103and/or second camera105. In some embodiments, the display114is a touch-sensitive display. The input/output (I/O) components, such as components116, may be or include any suitable mechanism, interface, or device to receive input (such as commands) from the user and to provide output to the user through the display114. For example, the components116may include (but are not limited to) a graphical user interface (GUI), a keyboard, a mouse, a microphone, speakers, a squeezable bezel, one or more buttons (such as a power button), a slider, a toggle, or a switch.

While shown to be coupled to each other via the processor104, components (such as the processor104, the memory106, the ISP112, the display114, and the components116) may be coupled to each another in other various arrangements, such as via one or more local buses, which are not shown for simplicity. One example of a bus for interconnecting the components is a peripheral component interface (PCI) express (PCIe) bus.

While the ISP112is illustrated as separate from the processor104, the ISP112may be a core of a processor104that is an application processor unit (APU), included in a system on chip (SoC), or otherwise included with the processor104. While the device100is referred to in the examples herein for performing aspects of the present disclosure, some device components may not be shown inFIG.1to prevent obscuring aspects of the present disclosure. Additionally, other components, numbers of components, or combinations of components may be included in a suitable device for performing aspects of the present disclosure. As such, the present disclosure is not limited to a specific device or configuration of components, including the device100.

The exemplary image capture device ofFIG.1may be operated to efficiently store and invalidate image data, such as image frame stripes, stripe metadata, and other image frame data, in the cache160. One example method of processing image frames captured by one or more cameras, such as first camera103and/or second camera105, with efficient cache usage techniques described herein, is shown inFIG.2and described below.

FIG.2is a block diagram illustrating an example data flow path for image data processing in an image capture device according to one or more embodiments of the disclosures. Processor104of system200may communicate with ISP112through a bi-directional bus and/or separate control and data lines. The processor104may control the first camera103through camera control210. The camera control210may be a camera driver executed by the processor104for configuring the first camera103, such as to active or deactivate image capture, configure exposure settings, and/or configure aperture size. Camera control210may be managed by a camera application204executing on the processor104. The camera application204provides settings accessible to a user such that a user can specify individual camera settings or select a profile with corresponding camera settings. Camera control210communicates with the first camera103to configure the first camera103in accordance with commands received from the camera application204. The camera application204may be, for example, a photography application, a document scanning application, a messaging application, or other application that processes image data acquired from the first camera103.

The camera configuration may include parameters that specify, for example, a frame rate, an image resolution, a readout duration, an exposure level, an aspect ratio, an aperture size, etc. The first camera103may apply the camera configuration and obtain image data representing a scene using the camera configuration. In some embodiments, the camera configuration may be adjusted to obtain different representations of the scene. For example, the processor104may execute a camera application204to instruct the first camera103, through camera control210, to set a first camera configuration for the first camera103, to obtain first image data from the first camera103operating in the first camera configuration, to instruct the first camera103to set a second camera configuration for the first camera103, and to obtain second image data from the first camera103operating in the second camera configuration.

In some embodiments in which the first camera103is a variable aperture (VA) camera system, the processor104may execute a camera application204to instruct the first camera103to configure to a first aperture size, obtain first image data from the first camera103, instruct the first camera103to configure to a second aperture size, and obtain second image data from the first camera103. The reconfiguration of the aperture and obtaining of the first and second image data may occur with little or no change in the scene captured at the first aperture size and the second aperture size. Example aperture sizes are f/2.0, f/2.8, f/3.2, f/8.0, etc. Larger aperture values correspond to smaller aperture sizes, and smaller aperture values correspond to larger aperture sizes. That is, f/2.0 corresponds to a larger aperture size than f/8.0.

The image data received from the first camera103may be processed in one or more blocks of the ISP112to determine output image frames230that may be stored in memory106and/or otherwise provided to the processor104. The processor104may further process the image data to apply effects to the output image frames230. Effects may include Bokch, lighting, color casting, and/or high dynamic range (HDR) merging. In some embodiments, the effects may be applied in the ISP112.

The ISP112may process image frames captured by the first camera103and/or stored in the memory106to provide filtering, motion compensation, multi-pass processing, and other image processing techniques, which may enhanced image quality. In performing such operations, the ISP112may store portions of captured image frames in a cache for low-latency access by the ISP112. The caching function212may govern when image frame data is stored in, read from, and invalidated in a cache associated with the ISP112, such as cache160ofFIG.1. For example, the caching function212of the ISP112may control storage of portions of stripes of image frames, or metadata associated with stripes of image frames, until the portions of the stripes, or metadata associated with the stripes, have been read from a cache for a last time. The caching function212of the ISP112may also control invalidation of image frame data and metadata stored in a cahce, processing re-ordering for efficient caching, and other functions described herein.

The output image frames230by the ISP112may include representations of the scene improved by various image processing techniques using reduced caching resources, as described herein. The processor104may display these output image frames230to a user, and the improvements provided by the described processing implemented in the ISP112and/or processor104improve the image quality and the user experience by reducing the appearance of bright and dark regions in the photograph. Furthermore, a user experience may be improved through use of the techniques described herein, such as when performed by the caching function212of the ISP112, through reduced latency and reduced cache usage in image processing.

To facilitate efficient image processing, image frames may be divided into vertical cross-sections, referred to herein as stripes, for processing, such as for optical filtering and/or other image processing. Such stripes may partially overlap to preserve continuity in processing the image frame including the stripes.FIG.3shows an block diagram300of example overlapping stripes302,304of an image frame according to some embodiments of the disclosure. Division of a frame into partially overlapping stripes302,304may facilitate efficient filtering, as filters may sequentially process partially overlapping stripes of an image, rather than processing an entire image frame at a single time. A first stripe302of the image frame may partially overlap with a second stripe304of the image frame. For example, a first portion312and a second portion310of the first stripe302and the second stripe304may overlap. Following processing, the stripes302,304may be output as non-overlapping stripes, such as a first output (O/P) stripe306and a second O/P stripe308, to form a single image frame.

In some embodiments, the stripes302,304may be in a universal bandwidth compression/decompression (UBWC) raw Bayer non-high dynamic range (HDR) format. In some embodiments, the image stripes302,304may be in a UBWC HDR format. The UBWC HDR format image may be generated using a short anchor exposure for a baseline of a fusion process, or another anchor exposure based on a lighting condition of a scene captured in the image. Various stripe widths and overlapping region widths may be used, as such widths and region sizes determined according to a striping algorithm based on image processing pipeline parameters. As one particular example, overlapping region widths may be calculated based on image filters being applied to the image frame.

Caching efficiency during processing of overlapping stripes of an image frame may be enhanced by storing an overlapping portion of multiple stripes in a cache until all stripes sharing the overlapping section have been processed. For example, a processor, such as an image signal processor, may read the first stripe302from a memory at a first time. After reading the first stripe from the memory, the processor may store at least a portion of the first stripe302, such as a portion310,312of the first stripe302that overlaps a portion of the second stripe304, in a cache associated with the processor. Such storage may be performed by issuing a read with allocate command to read the first stripe302from the memory and to allocate an area of the cache for storage of the overlapping portion310,312of the first stripe302and the second stripe304. In some embodiments, the processor may store the non-overlapping portion of the first stripe302in the cache as well.

The overlapping portion310,312of the first stripe302stored in the cache may be maintained in the cache until the overlapping portion310,312is read for processing of the second stripe304. For example, the processor may read the portion310,312of the first stripe302that overlaps with the second stripe304from the cache for processing of the second stripe304by issuing a read with evict command to read the overlapping portion310,312from the cache and invalidate, such as evict, erase, or otherwise forget, the stored overlapping portion310,312from the cache. The processor may also read the second stripe304from the memory. In some embodiments, the processor may read only the portion of the second stripe304from the memory that is not stored in the cache and may read the overlapping portion310,312of the first stripe302and the second stripe304from the cache for processing of the second stripe304. The processor may then process the second stripe304using the overlapping portion310,312read from the cache and the non-overlapping portion of the second frame304read from the memory. Thus, an overlapping portion of multiple stripes may be stored in a cache until the overlapping portion is read, from the cache, for processing of a final image stripe that includes the overlapping portion.

A command format for reading image frame stripe data from a memory may be adjusted to include instructions for allocating or not allocating cache space for storage of portions of a stripe of an image frame.FIG.4shows an example cache allocation command400for writing of portions of stripes of an image frame from a memory to a cache according to some embodiments of the disclosure. For example the command400may include a cache allocation bit402to indicate whether cache space should be allocated for storage of image frame stripe data associated with the command. The command400may also include a sixteen bit height field404, a sixteen bit width field406, a sixteen bit Y coordinate field408, and a sixteen bit X coordinate field410. In some embodiments, the cache allocation command400may be a read command.

The command400may, for example, may be a fetch request and may be transmitted from a port of an image correction and adjustment (ICA) engine, such as an ICA port having a Bayer UBWC or another UBWC format, to a fetch engine (FE). The FE may retrieve information requested by the ICA port and may provide the information to the ICA port via a serial input bus. If a value of the cache allocation bit402is set to 1 or true, cache space may be allocated for storage of an overlapping stripe section. If a value of cache allocation bit402is set to 0 or false, cache space may not be allocated, or may be de-allocated. The cache allocation bit402may be set by an ICA engine associated with the ICA port, and a software interface (SWI) may globally enable/disable an algorithm for setting the cache allocation bit402.

In some examples, only a first and last tile of overlapping slices of an image frame may be cached, rather than an entire overlapping region. A system may, for example, include multiple respective fetch engines associated with respective fetch engine port IDs. For example, for some ports, such as ports of fetch engines operating according to Bayer UBWC or another UBWC format, a SWI will notify an FE of an initial x value and width of a stripe, a left tile cache enable and allocation for the stripe, for storage of a first overlapping left-side tile of the stripe, a number of left-side tiles of the stripe with overlapping pixels, a right cache enable and allocation for the stripe, for storage of a first overlapping right-side tile of the stripe, a number of right-side tiles with overlapping pixels, and an other tile cache enable and allocation for storage of other tiles of the stripe. If the output is linear, such as an output format different from UBWC, then caching may be disabled and overlapping tiles may not be stored in the cache. Otherwise the FE may determine a first and last tile in a stripe and may allocate cache storage space for the first and last tile of the stripe.

FIG.5shows a flow chart of an example method500for processing image data with enhanced cache usage in storing overlapping sections of image frame stripes according to some embodiments of the disclosure. The system200ofFIG.2may be configured to perform the operations described with reference to the method500ofFIG.5to reduce cache usage in processing image frames. Each of the operations described with reference toFIG.5may be performed by one or a combination of the processor104(including cores104A-N or AI engine124) and/or the ISP112.

At block502, an image processor may store a first portion of a first stripe of a first frame in a cache, the first portion of the first stripe overlapping a second portion of a second stripe of the first frame. For example, the image processor may read the first stripe of the first frame from a memory, such as a double data rate (DDR) synchronous dynamic random-access memory (SDRAM), and may store the first stripe of the first frame in the cache. In some embodiments, such storage may include generating a cache allocation command to allocate a first area of the cache for storage of the first portion of the first stripe. In some embodiments, the first portion of the first stripe may include a first tile of the first stripe and a second portion of the second stripe may include a second tile of the second stripe. Such tiles may, for example, be tiles of a UBWC tiled format of the first frame. In some embodiments, the first portion of the first stripe may be stored in the cache after the first portion of the first stripe is read from the memory for processing of the first stripe.

At block504, the image processor may read a third portion of the second stripe from a memory. The third portion of the second stripe may, for example, be a portion of the second stripe that does not overlap with the second portion of the second stripe or the first portion of the first stripe. That is, the second portion of the second stripe may be a portion of the second stripe that does not overlap with the first stripe. In some embodiments, the image processor may read, from the memory, only a portion of the second stripe that is not already stored in the cache.

At block506, the image processor may read the first portion of the first stripe from the cache. For example, the image processor may read the first portion of the first stripe for processing along with the third portion of the second stripe read from the memory. In some embodiments, after the image processor reads the first portion of the first stripe from the cache, the image processor may invalidate the first portion of the first stripe in the cache. Such invalidation may include de-allocating the portion of the cache allocated for storage of the first portion of the first stripe, forgetting the first portion of the first stripe, and/or evicting or deleting the first portion of the first stripe from the cache. For example, after reading the first portion of the first stripe from the cache for processing of a last stripe that includes the first portion of the first stripe, such as the second stripe, the image processor may issue a command, such as a staling command, to invalidate the first portion of the first stripe in the cache. Such invalidation may free cache space for other uses.

At block508, the image processor may process the second stripe using the first portion of the first stripe read from the cache and the third portion of the second stripe read from the memory. For example, the image processor may perform one or more optical filtering operations on the second stripe, the second stripe including the first portion of the first stripe read from the cache and the third portion of the second stripe read from the memory. Thus, overlapping portions of adjacent image stripes may be stored in a cache until a final read of the overlapping portion for processing of a final stripe including the overlapping portion is performed.

In some embodiments, multiple resolutions of an image frame may be processed, such as in multi-pass image processing. The multiple resolutions of a frame may be divided into multiple stripes, as described herein. Processing of stripes of a higher resolution of an image frame may depend on prior processing of stripes of a lower resolution of the image frame. For example, processing of stripes of a higher resolution of an image frame may depend on metadata generated during processing of stripes of the lower resolution of the image frame.FIG.6shows a block diagram of example processing dependencies between different stripes of different resolutions of an image frame according to some embodiments of the disclosure. As one particular example, a first, lowest, resolution606of a frame, such as a 1:16 resolution, may include a single stripe608. A second resolution604of the frame, such as a 1:4 resolution, may include four stripes. Processing of each of the four stripes of the second resolution of the frame may depend on metadata generated in processing the first stripe608of the first resolution606of the frame. A third resolution602of the frame, such as a 1:1 resolution, may include 14 stripes. Processing of stripes612A-C of the third resolution602may depend on metadata generated in processing stripe610A of the second resolution604, and processing of stripes612D-F may depend on metadata generated in processing stripe610B of the second resolution604. Thus, stripes of a second resolution604may be mapped to stripes of a first resolution606on which they depend, and stripes of a third resolution602may be mapped to stripes of the second resolution604on which they depend. To facilitate efficient processing, metadata generated during processing of stripe610A may be stored in a cache and read from the cache for processing each of the dependent stripes612A-C. After the metadata generated during processing of stripe610A is read for a last time for processing of stripe612C, it may be invalidated in the cache, such as de-allocated, forgotten, erased, or evicted. Such invalidation may be performed, for example, by generating a staling notification each time a final stripe of the first resolution602of the image frame dependent on particular metadata is processed.

Cache usage efficiency when performing multi-pass image processing may be further enhanced through ordering of processing of stripes of an image frame based on dependencies between stripes of different resolutions. For example, instead of processing all stripes of the second resolution604before processing all stripes of the third resolution606, processing of stripes of different resolutions may be scheduled in an interleaved pattern based on dependencies.FIG.7shows a block diagram700of example ordering of processing of different stripes of different resolutions of an image frame according to some embodiments of the disclosure. For example, a first resolution706, a second resolution704, and a third resolution702of a first frame may be processed. The first resolution706may include a single stripe708, the second resolution704may include three stripes710A-C, and the third resolution702may include eight stripes712A-G, although different numbers of stripes of different resolutions may also be processed according to the techniques described herein. Processing of the three stripes710A-C of the second resolution704may depend on metadata generated when processing the first stripe708of the first resolution706. Processing of stripes712A-C may depend on metadata generated during processing of stripe710A, and processing of stripes712D-G may depend on metadata generated during processing of stripe710B. Processing of the stripes may be reordered such that dependent stripes are processed sequentially. In particular processing of stripes of different resolutions may be interleaved. For example, stripes712A-C may be scheduled for processing following processing of stripe710A and before processing of stripe710B. Stripes712D-G may be scheduled following processing of stripe710B and before processing of stripe710C. Metadata generated during processing of stripe710A may be stored in a cache for use in processing stripes712A-C until the metadata is read from the cache a final time for processing of stripe712C. Then, the metadata may be invalidated in the cache. For example, after processing of stripe712C, a processor may generate a notification, such as a staling notification, to invalidate the metadata associated with stripe710A. In some embodiments, a processor may wait for a number of notifications to invalidate the data, following storage of the metadata in the cache, before invalidating the metadata from the cache. Such a number may be referred to as a staling distance. In some embodiments, a processor may generate a mapping dependency of stripes of the second resolution704to stripes of the first resolution702.

As one particular example, a processor, such as an image signal processor, may schedule the first stripe708of the first resolution706for processing. The processor may schedule a first stripe710A of the second resolution704for processing after the first stripe708of the first resolution706. Metadata generated during processing of the first stripe710A of the second resolution704may be stored in a cache associated with the processor. The processor may schedule stripes712A-712C of the third resolution702, such as full pass stripes, that depend on metadata generated during processing of the first stripe710A of the second resolution704for processing after the first stripe710A of the second resolution704. The processor may schedule a forget notification for the metadata generated during processing of the first frame710A of the second resolution704to invalidate the metadata stored in the cache after the metadata is no longer needed for processing stripes712A-C. The forget notification may, for example, be a forget notification associated with a particular sub-cache identifier (SCID) associated with the metadata generated during processing of stripes of the second resolution704, such as an SCID set when scheduling the first stripe710A of the second resolution704. The SCID may, for example, identify a location in the cache at which the particular metadata is stored. In some embodiments, the forget notification may be a staling notification. In some embodiments, when the forget notification is generated, the metadata associated with the stripe710A may be invalidated without evicting the data, such as without writing the metadata to a memory. In some embodiments, the forget notification may cause a counter associated with the third resolution, such as a staling counter, to be incremented. For example, after processing of each set of stripes of the third resolution702that depend from the second resolution704, a counter may be incremented in response to a forget notification. The processor may be configured to invalidate the metadata stored in the cache when the counter reaches a predetermined value, such as when the counter increments a threshold number of times following storage of particular metadata associated with a particular stripe in the cache. For example, the processor may be configured to invalidate the metadata generated during processing of the stripe710A when the counter increments two times following storage of the metadata associated with the stripe710A in the cache, such as after processing of stripe712G. When the forget notification is generated a blocking write may be performed on an identified register, such as to update a staling counter.

The processor may be configured to schedule a second stripe710B of the second resolution704after scheduling the set of stripes712A-C of the third resolution702. The processor may be further configured to schedule a second set of stripes712D-G of the third resolution702, which depend on metadata generated during processing of the second stripe710B of the second resolution704, following processing of the second stripe710B of the second resolution704. Likewise, the processor may schedule a forget notification for the metadata associated with the second resolution704, such as a staling notification, for incrementing a counter for metadata associated with the second resolution704. In some embodiments, different queues, such as different queues associated with different resolutions, may be assigned different SCIDs. Thus, for example, an SCID for the first resolution706may be different from an SCID for the second resolution704. Furthermore, a staling distance, such as an amount of increase of a staling counter at which metadata associated with the resolution is invalidated in the cache, may be set to a different value for each SCID. For example, a staling distance associated with a staling counter for the second resolution704may be set to 2, such that when two staling notifications for the SCID associated with the second resolution704are received after metadata generated during processing of a stripe of the second resolution704is stored in the cache the metadata will be invalidated in the cache. A staling distance associated with a staling counter for the first resolution708may be set to 1, such that when one staling notification for the SCID associated with the first resolution706is received after the metadata generated during processing of a stripe of the first resolution706is stored in the cache the metadata will be invalidated in the cache. Thus, staling counters for different resolutions may be independent. The scheduling of processing of stripes and forget notifications may, for example, be performed by firmware executed by the processor.

FIG.8shows a flow chart of an example method800for processing image data with enhanced cache usage in storing metadata of stripes of different resolutions of an image frame according to some embodiments of the disclosure. The system200ofFIG.2may be configured to perform the operations described with reference to the method800ofFIG.8to reduce cache usage and enhance efficiency in processing image frames. Each of the operations described with reference toFIG.8may be performed by one or a combination of the processor104(including cores104A-N or AI engine124) and/or the ISP112.

At block802, an image processor, such as an image signal processor, may store metadata associated with a first stripe of a first resolution of a first image in a cache. The metadata may, for example, be metadata generated during processing of the first stripe of the first resolution. In some embodiments, the image processor may schedule processing of the first stripe of the first resolution to generate the metadata. In some embodiments, the first resolution may be a 1:4 resolution.

At block804, the image processor may process a plurality of stripes of a second resolution of the first frame using the metadata. For example, the processor may determine that the plurality of stripes of the second resolution depend on the metadata associated with the first stripe of the first resolution and may schedule the plurality of stripes for processing after the first stripe of the first resolution and before processing of any other stripes of the first resolution. Processing of the plurality of stripes of the second resolution may, for example, include reading, at a first time, the metadata from the cache, processing a second stripe of the plurality of stripes using the metadata read from the cache at the first time, reading, at a second time, the metadata from the cache, and processing a third stripe of the plurality of stripes using the metadata read from the cache at the second time. In some embodiments, the third stripe may be a last stripe of the plurality of stripes of the second resolution, such as a last stripe of the second resolution that depends on the metadata associated with the first stripe of the first resolution. In some embodiments, the image processor may schedule reading of the metadata from the cache at the second time and may also schedule incrementing of a counter associated with the metadata, after the metadata is read the second time. In some embodiments, the counter may be a staling counter and scheduling incrementing of the counter may include generating a forget notification, such as a staling notification. Scheduling of the incrementing of the counter may, for example, be based on a determination that the third stripe is a last stripe of the plurality of stripes of the second resolution that depend on the metadata. In some embodiments, the second resolution may be a 1:1 resolution.

At block806, the processor may invalidate the metadata in the cache after processing the plurality of the stripes. Invalidating the metadata may include de-allocating the portion of the cache allocated for storage of the first portion of the first stripe and/or deleting the first portion of the first stripe from the cache. In some embodiments, the metadata may be invalidated without evicting the data, such as without writing the metadata to a memory. In some embodiments, invalidating the metadata may be performed based on incrementing the counter associated with the metadata described with respect to block804. For example, invalidating the metadata may be performed based on the counter exceeding a threshold value, such as two or another value. For example, the metadata associated with the first stripe may be invalidated after processing a second plurality of stripes of the second resolution that depend on metadata associated with a second stripe of the first resolution. Thus, processing of stripes of different resolutions of an image frame may be re-ordered to enhance cache usage efficiency.

Cache usage efficiency may be further enhanced through invalidation of stripes of a reference frame stored in a cache for processing stripes of a current frame based on a greatest motion vector between the reference frame and the current frame.FIG.9shows a block diagram900of example processing using a reference image frame according to some embodiments of the disclosure. Such processing may, for example, include processing to enhance a current image frame based on motion detected between a reference image frame and the current image frame. For example, a reference frame908may be input to and processed by an image processing engine902. The reference image frame908, after processing, may be stored in cache. Subsequently, a current frame may be input to the image processing engine902at input904, processed by the image processing engine902using the reference image frame908loaded from the cache, and output at a main output906.

A reference image frame and a current image frame may be divided into stripes, as discussed herein, for efficient processing. For example, as shown inFIG.10, a plurality of stripes1002of a current image frame, associated with a first SCID, may be processed using a plurality of stripes1006of a reference image frame, previously processed by an image processor and stored in a cache. For example, the plurality of stripes of the reference frame may be read as stripes1004from the cache for processing of the current image frame1002image frame. With every stripe of an image processed, a forget notification, such as a staling notification, may be generated by the image processor. The forget notification may cause a counter associated with the stripes of the reference frame stored in the cache to be incremented. When the counter increases a threshold amount after storage of a particular stripe of the reference frame in the cache, the stripe of the reference frame stored in the cache may be invalidated. For example a forget notification associated with an SCID associated with the reference frame may be generated every time a stripe of the reference frame1006or the current frame1002is processed.

To efficiently utilize cache space when processing stripes of a current frame using stripes of a reference frame, stripes of the reference frame stored in the cache may be invalidated based on a greatest motion vector between the reference frame and the current frame. For example, a threshold, such as a staling distance for a counter, such as a staling distance, may be set based on a value of a greatest motion vector between the reference frame and the current frame. Such setting may include activating or deactivating the counter based on the greatest motion vector between the reference frame and the current frame. When the counter is activated and increments a threshold number of times after storage of a stripe of a reference frame in the cache, the stripe of the reference frame may be invalidated in the cache.

A greatest motion vector between the reference frame and the current frame may be determined by determining a motion vector with a greatest value among a plurality of motion vectors calculated by different image processing cores and/or functions. For example, the greatest motion vector may be determined by reading a maximum negative x direction motion vector from each of multiple different image processing algorithms and summing the maximum negative motion vectors for a total maximum negative motion vector. The greatest motion vector may, for example, be a greatest motion vector along an X-axis.

A minimum strip width of the reference frame and the current frame may then be determined. The minimum strip width may, for example, be the same for both the reference frame. Therefore, the minimum strip width determined may be a minimum strip width corresponding to both the reference frame and the current frame. In some embodiments, a determination may be made of whether the maximum motion vector value is greater than two times the minimum stripe width. If so, the counter may be disabled and the stripes of the reference frame may not be invalidated based on the greatest motion vector between the reference frame and the current frame. If not, the counter may be set to a number of stripes of the reference frame and/or the current frame plus three. Thus, as one particular example, a first stripe of the reference frame1006may be invalidated in the cache when a notification1008to increment the counter based on processing of a third stripe of the current frame1002is generated. Likewise, a second stripe of the reference frame1006may be invalidated in the cache when a notification1010to increment the counter based on processing of a fourth stripe of the current frame1002is received. A third stripe of the reference frame1006may be invalidated in the cache when a notification1012to increment the counter based on processing of a fifth stripe of the current frame1002is received.

In some embodiments, a different value, such as three times the minimum stripe width, may be compared with the value of the greatest motion vector. Then, the counter may be set to a number of stripes of the reference frame and/or the current frame plus four. Other numbers of minimum stripes may also be compared with the value of the greatest motion vector for similar calculations.

If the counter is not disabled, every command to write a stripe to the cache may be appended with a notification to increment the counter, such as a staling notification. When the counter increments the threshold number of times following storage of a particular stripe of a reference frame in the cache, such as 26 times, the stripe may be invalidated in the cache. The counter may, in some embodiments, have a size of five bits. In some embodiments, the counter may be stored in the cache.

A number of stripes in an 8 k image frame may be 23, in which case a counter may be set to 26 when a greatest motion vector is compared against a width of two stripes. A number of stripes in an ultra high definition (UHD) image frame may be 14, in which case a counter may be set to 17 when a greatest motion vector is compared against a width of two stripes. A number of stripes in a full high definition (FHD) image frame may be 8, in which case a counter may be set to 11 when a greatest motion vector is compared against a width of two stripes. In some embodiments a maximum value of the counter, such as a maximum staling distance, may be 32. In some embodiments, a maximum value of the counter may be limited to 27 to prevent wrap around conditions. In some embodiments, the threshold values associated with the counter and deactivation and/or activation of the counter may be determined per frame by firmware, such as at a start of processing a frame. Firmware may further set a no self-evict (NSE) value to true.

In some embodiments, if a number of stripes in the current frame or the reference frame is greater than 23, the counter may be disabled and the stripes of the reference frame stored in the cache may not be invalidated based on the counter. In some embodiments, if a downscale or upscale factor changes between a reference frame and a current frame, the counter and caching of the reference frame may be disabled. In some embodiments, the counter and caching of the reference frame may be disabled for processing of video super-resolution (VSR) image frames. In some embodiments, caching of a current frame may be disabled by a UC upon detection of any change in striping, such as a change in stripe width. Upon detection of such a change, all cached reference frame data may be evicted to a memory, such as a double data rate (DDR) synchronous dynamic random-access memory (SDRAM).

FIG.11shows a flow chart of an example method1100for processing image data with enhanced cache usage in storing stripes of a reference frame for processing of stripes of a current frame according to some embodiments of the disclosure. The system200ofFIG.2may be configured to perform the operations described with reference to the method1100ofFIG.11to reduce cache usage and enhance efficiency in processing image frames. Each of the operations described with reference toFIG.11may be performed by one or a combination of the processor104(including cores104A-N or AI engine124) and/or the ISP112.

At block1102, an image processor may store, in a cache, a first stripe of a first frame. The first stripe of the first frame may, for example, be a first stripe of a reference frame. In some embodiments, a counter, such as a staling counter, may be initiated and/or incremented when the first stripe of the first frame is stored in the cache. The first stripe of the first frame may, for example, be stored in the cache after processing of the first stripe of the first frame.

At block1104, the image processor may determine a value of a greatest motion vector associated with the first frame and a second frame. The second frame may, for example, be a current frame. The greatest motion vector may, for example, be a motion vector having a greatest value associated with an x-axis of the motion vector. The determination may, for example, include determining one or more motion vectors between the first and second frames along an x-axis determined by one or more image processing cores or functions. In some embodiments the one or more motion vectors may be summed to determine a greatest motion vector. In some embodiments, the one or more motion vectors may be compared to determine a motion vector with a greatest value along the x-axis to determine the greatest motion vector. In some embodiments the value of the greatest motion vector may be determined at block1104prior to storing the first stripe of the first frame in a cache at block1102.

In some embodiments, a counter associated with the first stripe, such as a staling counter, may be set in accordance with the determined value of the greatest motion vector associated with the first frame and the second frame. For example, a counter may be deactivated if a value of the greatest motion vector along an x-axis is greater than or equal to a width of a threshold number of stripes of the first frame. For example, if the length of the greatest motion vector exceeds a width of two stripes, or another number of stripes, of the first frame, the counter may be deactivated. If the length of the greatest motion vector is below a width of two stripes, the counter may be activated and a threshold value for the counter may be set to a number of stripes in the reference frame plus three. In some embodiments, the counter may be set to a number of stripes of the reference frame plus a different integer value. The different integer value may, for example, be set based on comparing the length of the greatest motion vector against a width of a different number of stripes. The counter may be incremented every time a stripe of the reference frame or the current frame is processed and stored in the cache.

As one particular example, the image processor may read a second stripe of the second frame, such as a stripe of the current frame, from a memory, and may read the first stripe of the first frame, such as the stripe of the reference frame, from the cache. The image processor may then process the second stripe of the second frame using the first stripe of the first frame and may store the second stripe of the second frame in the cache. The image processor may increment the counter associated with the first stripe of the first frame in response to processing the second stripe of the second frame. For example, the image processor may generate a staling notification to increment the counter. In some embodiments incrementing the counter may be triggered by storage of the second stripe of the second frame in the cache or by another operation. In some embodiments a single counter may be used and incremented in accordance with every notification associated with processing of stripes of the first and second frames, and the counter may be monitored to determined when the counter has incremented a threshold number of times following storage of a particular stripe in the cache. For example, the image processor may determine that the counter has exceeded a threshold value associated with the greatest motion vector. Such a determination may trigger the invalidation described with respect to block1106.

At block1106, the image processor may invalidate the first stripe of the first frame in the cache based on the determined value of the greatest motion vector. For example, the image processor may invalidate the first stripe of the first frame in the cache in accordance with activation of a counter based on the determined value of the greatest motion vector and in accordance with the counter incrementing a threshold number of times following storage of the first stripe of the first frame in the cache. Thus, stripes of a reference frame may be invalidated in a cache based on a greatest motion vector between the reference frame and a current frame.

In one or more aspects, techniques for supporting image processing may include additional aspects, such as any single aspect or any combination of aspects described below or in connection with one or more other processes or devices described elsewhere herein. In a first aspect, supporting image processing may include an apparatus configured to perform operations including storing, by an image processor, a first portion of a first stripe of a first frame in a cache, the first portion of the first stripe overlapping a second portion of a second stripe of the first frame, reading, by the image processor, a third portion of the second stripe from a memory, reading, by the image processor, the first portion of the first stripe from the cache, and processing, by the image processor, the second stripe using the first portion of the first stripe and the third portion of the second stripe.

Additionally, the apparatus may perform or operate according to one or more aspects as described below. In some implementations, the apparatus includes a wireless device, such as a UE. In some implementations, the apparatus includes a remote server, such as a cloud-based computing solution, which receives image data for processing to determine output image frames. In some implementations, the apparatus may include at least one processor, and a memory coupled to the processor. The processor may be configured to perform operations described herein with respect to the apparatus. In some other implementations, the apparatus may include a non-transitory computer-readable medium having program code recorded thereon and the program code may be executable by a computer for causing the computer to perform operations described herein with reference to the apparatus. In some implementations, the apparatus may include one or more means configured to perform operations described herein. In some implementations, a method of wireless communication may include one or more operations described herein with reference to the apparatus.

In a second aspect, in combination with the first aspect, the apparatus is further configured to perform operations including reading, by the image processor, the first stripe of the first frame from the memory before storing the first portion of the first stripe in the cache.

In a third aspect, in combination with one or more of the first aspect or the second aspect, the first portion of the first stripe comprises a first tile of the first stripe, and wherein the second portion of the second stripe comprises a second tile of the second stripe.

In a fourth aspect, in combination with one or more of the first aspect through the third aspect, the third portion of the second stripe does not overlap the second portion of the second stripe.

In a fifth aspect, in combination with one or more of the first aspect through the fourth aspect, storing the first portion of the first stripe in the cache comprises generating, by the image processor, a command to allocate a first area of the cache for storage of the first portion of the first stripe.

In a sixth aspect, in combination with one or more of the first aspect through the fifth aspect, a format of the first frame is a universal bandwidth compression/decompression (UBWC) tiled format.

In a seventh aspect, in combination with one or more of the first aspect through the sixth aspect, the apparatus is further configured to perform operations including invalidating, by the image processor, the first portion of the first stripe in the cache after reading the first portion of the first stripe from the cache.

In an eighth aspect, the apparatus may be configured to perform operations including storing, by an image processor in a cache, metadata associated with a first stripe of a first resolution of a first frame, processing, by the image processor, a plurality of stripes of a second resolution of the first frame using the metadata, and invalidating the metadata in the cache after processing the plurality of stripes.

In a ninth aspect, in combination with the eighth aspect, processing the plurality of stripes includes reading, at a first time, the metadata from the cache, processing a second stripe of the plurality of stripes using the metadata read from the cache at the first time, reading, at a second time, the metadata from the cache, and processing a third stripe of the plurality of stripes using the metadata read from the cache at the second time.

In a tenth aspect, in combination with one or more of the eighth aspect through the ninth aspect, the third stripe is a last stripe of the plurality of stripes.

In an eleventh aspect, in combination with one or more of the eighth aspect through the tenth aspect, the apparatus is further configured to perform operations including scheduling, by the image processor, reading of the metadata from the cache, at the second time and scheduling, by the image processor, incrementing of a counter associated with the metadata, after the metadata is read at the second time, wherein invalidating the metadata is performed based on incrementing of the counter.

In a twelfth aspect, in combination with one or more of the eighth aspect through the eleventh aspect, invalidating the metadata is further performed based on the counter exceeding a threshold value.

In a thirteenth aspect, in combination with one or more of the eighth aspect through the eighth aspect, scheduling the incrementing the counter comprises generating a staling notification, and wherein the counter comprises a staling counter.

In a fourteenth aspect, in combination with one or more of the eighth aspect through the thirteenth aspect, the apparatus is further configured to perform operations including scheduling, by the image processor, the first stripe for processing and scheduling, by the image processor, the plurality of stripes for processing after the first stripe.

In a fifteenth aspect, in combination with one or more of the eighth aspect through the fourteenth aspect, the apparatus is further configured to perform operations including determining, by the image processor, that processing the plurality of stripes depends on the metadata associated with the first stripe, wherein scheduling the plurality of stripes for processing after the first stripe is performed based on the determination that processing the plurality of stripes depends on the metadata associated with the first stripe.

In a sixteenth aspect, in combination with one or more of the eighth aspect through the fifteenth aspect, the first resolution is a 1:4 resolution, and wherein the second resolution is a 1:1 resolution.

In a seventeenth aspect, the apparatus is configured to perform operations including storing, by an image processor in a cache, a first stripe of a first frame, determining, by the image processor, a value of a greatest motion vector associated with the first frame and a second frame, and invalidating, by the image processor, the first stripe of the first frame in the cache based on the determined value of the greatest motion vector.

In an eighteenth aspect, in combination with the seventeenth aspect, the greatest motion vector is a motion vector having a greatest value associated with an x-axis.

In a nineteenth aspect, in combination with one or more of the seventeenth aspect through the eighteenth aspect, reading, by the image processor, a second stripe of the second frame from a memory, reading, by the image processor, the first stripe of the first frame from the cache, processing, by the image processor, the second stripe of the second frame using the first stripe of the first frame, incrementing, by the image processor, a counter associated with the first stripe of the first frame in response to processing the second stripe of the second frame, and determining, by the image processor, the counter exceeds a threshold value associated with the greatest motion vector, wherein invalidating, by the image processor, the first stripe of the first frame in the cache based on the determined value of the greatest motion vector is performed based on the counter exceeding the threshold value.

In a twentieth aspect, in combination with one or more of the seventeenth aspect through the nineteenth aspect, the counter comprises a staling counter and wherein incrementing the counter comprises generating a staling notification.

In a twenty-first aspect, in combination with one or more of the seventeenth aspect through the twentieth aspect, the apparatus is further configured to perform operations including determining a number of stripes of the first frame corresponding to the value of the greatest motion vector and adding an integer value to the number of stripes to determine the threshold value.

In a twenty-second aspect, in combination with one or more of the seventeenth aspect through the twenty-first aspect, the integer value is three.

In a twenty-third aspect, in combination with one or more of the seventeenth aspect through the twenty-second aspect, determining a greatest motion vector associated with the first frame and the second frame comprises determining a greatest motion vector of a plurality of motion vectors associated with the first frame and the second frame determined by a plurality of cores of the image processor.

Aspects of the present disclosure are applicable to any electronic device including coupled to, or otherwise processing data from one, two, or more image sensors capable of capturing image frames (or “frames”). The terms “output image frame,” “modified image frame,” and “corrected image frame” may refer to an image frame that has been processed by any of the disclosed techniques to adjust raw image data received from an image sensor. Further, aspects of the disclosed techniques may be implemented for processing image data received from image sensors of the same or different capabilities and characteristics (such as resolution, shutter speed, or sensor type). Further, aspects of the disclosed techniques may be implemented in devices for processing image data, whether or not the device includes or is coupled to image sensors. For example, the disclosed techniques may include operations performed by processing devices in a cloud computing system that retrieve image data for processing that was previously recorded by a separate device having image sensors.

Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present application, discussions using terms such as “accessing,” “receiving,” “sending,” “using,” “selecting,” “determining,” “normalizing,” “multiplying,” “averaging,” “monitoring,” “comparing,” “applying,” “updating,” “meausring,” “deriving,” “settling,” “generating,” or the like, refer to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's registers, memories, or other such information storage, transmission, or display devices. The use of different terms referring to actions of processes of a computer system does not necessarily indicate different operations. For example, “determining” data may refer to “generating” data. As another example, “determining” data may refer data.

The terms “device” and “apparatus” are not limited to one or a specific number of physical objects (such as one smartphone, one camera controller, one processing system, and so on). As used herein, a device may be any electronic device with one or more parts that may implement at least some portions of the disclosure. While the description and examples herein use the “device” to describe various aspects of the disclosure, the term “device” is not limited to a specific configuration, type, or number of objects. As used herein, an apparatus may include a device or a portion of the device for performing the described operations.

Certain components in a device or apparatus described as “means for accessing,” “means for receiving,” “means for sensing,” “means for using,” “means for selecting,” “means for determining,” “means for normalizing,” “means for multiplying,” or other similarly, named terms referring to one or more operations on data, such as image data, may refer to processing circuitry (e.g., application specific integrated circuitys (ASICs), digital signal processors (DSP), graphics processing unit (CPU), central processing unit (CPU), computer vision processor (CVP), or neural signal processor (NSP)), configured to perform the recited function through hardware, software, or a combination of hardware configured by software.

Those of skill in the art that one or more blocks (or operations) describe with reference toFIGS.5,8, and11may be combined with one or more blocks (or operations) described with reference to another of the figures. For example, one or more blocks for operations) ofFIG.5may be with one or more blocks (or operations) ofFIGS.1-2. As another example, one or more blocks associated withFIG.8may be combined with one or more blocks (or operations) associated withFIGS.1-2.

In one or more aspects, the functions described may be implemented in hardware, digital electronic try, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also may be implemented as one or more computer programs, which is one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.

Additionally, a person having ordinary skill in the art will readily appreciate, opposing terms such as “upper” and “lower,” or “front” and back,” or “top” and “bottom,” or “forward” and “backward” are sometimes u for ease of describing the figures, and indicate relative positions corresponding to the orientations of the figure on a properly oriented page, and may not reflect the proper orientation of any device as implemented.

Certain features that are described in this specification in the context of separate implementation also may be implemented in combination in a single implementation. Conversely, various feature that are described in the context of a single implementation also may be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some ca be from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

The term “substantially” is defined as largely, but not necessarily wholly, what is specified (and includes what is specified; for example, substantially 90 degrees includes 90 degrees and substantially parallel includes parallel), as understood by a person of ordinary skill in the art. In any disclosed implementations, the term “substantially” may be substituted with “within [a percentage] of” what is specified, where the percentage includes 0.1, 1, 5, or 10 percent.