Method and system for sharing a receive buffer RAM with a single DMA engine among multiple context engines

A method for sharing a buffer among multiple context engines, is provided. The method includes loading a memory element with a first data sequence. The method further includes loading a corresponding first context information to one of the multiple context engines. Subsequently, a direct memory access engine is loaded with the first data sequence dictated by the first context information. Then, the first data sequence is processed. While the first data sequence is being processed, the method includes loading the context engine with a next context information for a next data sequence contemporaneously with the processing of the first data sequence.

BACKGROUND

Direct memory access (DMA) engines are devices that are capable of temporarily taking control of a bus and performing data transfers between various devices. Such data transfer may occur between memories, memories and devices, and devices. DMA engines enhance system performance by freeing the microprocessor from having to do the transfer of data itself. DMA engines generally take a lot of gates to build, which can take up considerable space of a die area. Therefore, it will be advantageous to minimize the number of DMA engines on a die.

In addition, in cases where receiver buffers are involved, conventional methods normally utilized a combined context/DMA engine per buffer. One of the drawbacks to this method is that when the DMA engine works on data associated with a particular context, no data associated other contexts would be allowed in the buffer. Therefore, the I/O interface would be forced to wait while the data associated with a particular context were drained out of the buffer. Once drained, the next set of data associated with another context are loaded into the buffer before the combined context/DMA engine is configured. This resulted in long delays on the DMA engine data transfer interface.

As can be seen, there is a need for a system and method that allows maximum utilization of both the receive buffer and the DMA data transmission interface.

SUMMARY

Broadly speaking, the present invention fills these needs by providing a method and apparatus that allow buffer to be shared among multiple context engines. This method separates the context engine from the DMA engine, allowing multiple context engines to track different data as they move through the buffer. This allows optimal use of the buffer, DMA engine and its data transmission interface while minimizing slowdowns on the input/output (I/O) interface.

It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, or a device. Several inventive embodiments of the present invention are described below.

In one aspect of the invention, a method for sharing a buffer among multiple context engines, is provided. The method includes loading a memory element with a first data sequence. The method further includes loading a corresponding first context information to one of the multiple context engines. Thereafter, the method proceeds to load a direct memory access engine with the first data sequence dictated by the first context information. Then, the first data sequence is processed. While the first data sequence is being processed, the method includes loading the context engine with a next context information for a next data sequence, contemporaneously with the processing of the first data sequence.

In another aspect of the invention, a system for efficiently transferring data sequence, is provided wherein, the system includes a storage element. The system further includes a context engine configured to direct transfer of the data sequence from the storage element. In addition, the system includes a status machine that tracks the status of the data sequence transfer. Also included in the system is a direct memory access (DMA) engine in communication with the storage element to receive the data sequence from the storage element dictated by a context information stored in the context engine.

Yet another aspect of the invention includes, a system that maximizes data transmission by switching between two context engines. The system includes a buffer configured to receive a data sequence. The system further includes a direct memory access engine in communication with the buffer. The system also includes at least two context engines configured to direct data sequence transfer between the buffer and the direct memory access engine. Further included with the system is an arbiter which is in communication with the context engines and the arbiter arbitrates between the context engines. Based on the arbitration decision, a determination is made as to the corresponding data sequence, which gets loaded to the DMA engine.

DETAILED DESCRIPTION

An invention is described for an apparatus and method for sharing a buffer RAM with a single DMA engine among multiple context engines. The invention allows the DMA engine to pull the data out of a single buffer and switch data between different context engines. When the DMA engine works on a first data sequence associated with a context information stored in a first context engine, the context information associated with the next data sequence may loaded into a second context engine. This way, when the DMA engine finishes working on the first data sequence, the DMA engine may immediately start processing the next data sequence as the DMA engine has the context information readily available. This maximizes the utilization of the receive buffer DMA data transmission interface resulting in low latency.

FIG. 1shows a system that utilizes multiple DMA engines to transfer data. The system includes context memory104, context engines106aand106b, DMA engines108aand108b, buffer102and arbiter110. The data sequence to be transported is loaded into the buffer102. DMA engines108aand108bretrieve the data sequence out of buffer102and move the data sequence to the location directed by the context information stored in context engines106aand106b. In one embodiment, context information may include the address in the memory to which the data sequence is to be sent from the DMA engine. The context information may also include a count, which provides the length of the data sequence. For example, the count may be the number of bits in the data sequence. Thus, the count may act as fence that separates different data sequences within the buffer. One skilled in the art should understand that the context information may also include other information such as pointers, which retain location within buffers106aand106bat which the data sequence for a particular context is kept. Context information for different contexts is stored in context memory104. Context information is passed onto context engines106aand106bas needed.

FIG. 1also shows an arbiter110. Arbiter110arbitrates between the DMA engines108aand108band based on the arbitration result, provides access to an interface (not shown). The interface may be a memory interface through which the data sequence may be transferred to a memory (not shown). Even though this design provide two context engines106aand106b, and two DMA engines108aand108b, a bottleneck occurs from the arbiter110to the interface. Thus, the design does not work as efficiently as it should.

An alternate design for transferring data is shown inFIG. 2, in accordance with an embodiment of the present invention. InFIG. 2, one DMA engine is provided instead of two.FIG. 2, as shown, includes context memory204, buffer202, DMA engine208and context engines206aand206b. As described above, context memory204stores context information for different contexts. Context engines206aand206bmay access the context memory204to obtain different context information for the data sequence in buffer202. The data sequence to be transferred is loaded into buffer202, as indicated by arrow212, and the corresponding context information for the data sequence is loaded into one of context engines206aor206b. In this design, when a first data sequence from buffer202are transferred to the DMA engine208directed by the corresponding context information stored in one of the context engines206aor206b, the context information for the next data sequence in buffer202may be loaded to the second free context engine so that when the DMA engine completes the processing of the first data sequence, the next data sequence is ready for processing. Thus, there is no time being wasted through a bottleneck, as shown with reference toFIG. 1. Moreover, DMA engine208is shared among context engines206aand206b, which also saves the number of gates required for having an extra DMA engine.

FIG. 3shows another design for transferring data in accordance with an embodiment of the present invention. As shown,FIG. 3includes data source304, buffer302, DMA engine310, status machine306, context memory312, and context engine308. Data source304stores a data sequence to be transferred. When the data sequence is being transferred, the data sequence is loaded into buffer302. Simultaneously, the status of the data sequence is sent to the status machine306. Status machine306keeps track of the status of the data sequence transfer. The data sequence transfer from buffer302to the DMA engine310is controlled by the context information stored in the context engine308. Context engine308receives the context information from the context memory312. Status machine306indicates when the data sequence for a particular context information is transferred from buffer302to DMA engine310. Once the data sequence transfer occurs, the context engine308is free to receive the context information for the next data sequence loaded into the buffer. This way, while the DMA engine310processes the transferred data sequence, the context engine308may receive the context information for the next data sequence in the buffer. Once the DMA engine completes the processing of the transferred data sequence, the context information for the next data sequence in the buffer is readily available. Therefore, the next data sequence from the buffer may be loaded to the DMA engine immediately after the DMA engine completes of the processing of the transferred data sequence. This in turn prevents any bottleneck that would have occurred at the data sequence transfer interface. The design described above also saves the number of gates required by reducing the number of context engines, arbiter and DMA engines.

FIG. 4is an alternative design for transferring data using a DMA engine in accordance with an embodiment of the present invention.FIG. 4includes buffer402, context memory404, context engines406aand406b, arbiter408, and DMA engine410. The arbiter408is placed between context engines406aand406band the DMA engine410. In this design, the arbiter408arbitrates between the two context engines and the result of the arbitration determines which one of the context information is used to move the data sequence from the buffer402to DMA engine410. In one embodiment, the arbiter408may be a time stamper, which arbitrates by determining which one of the context engines was loaded with the context information first. In another embodiment, the arbiter408matches the context information in the context engine with the first data sequence that is ready to be sent out of the buffer402to DMA engine410and provides passage to the data sequence that matches. Thus, by having two context engines, while the first context information from the first context engine is being used, the second context engine may be loaded with a second context information for the next data sequence in the buffer. This way, once the DMA engine processes the data sequence corresponding to the first context information, the DMA engine may proceed with the next data sequence in the buffer that is corresponding to the second context information.

FIG. 5shows a host adapter500that includes a system for transferring data using a DMA engine, in accordance with an embodiment of the present invention.FIG. 5includes storage devices502a-502n, buffers504a-504n, arbiter506, DMA engine508, and a memory510. Memory510and storage devices502a-502nare connected to host adapter500. Storage devices502a-502nstore data sequence to be transferred to memory510using DMA engine508. Data sequence is first loaded into buffers504a-504nfrom storage devices502a-502n. Arbiter506arbitrates between the buffers504a-504nand decides on the data sequence from which buffer is to be sent to DMA engine508. In one embodiment arbiter506is a multiplexer. DMA engine508sends the data sequence to memory510via memory interface bus510. This design places the arbiter506before the DMA engine508in order to avoid any traffic jam at the memory interface bus512. In this case, data sequence from only one of the buffers is passed onto the DMA engine508at any given time. Similarly, when the data sequence from one of the buffers504a-504nare processed by the DMA engine508, the context information for the next data sequence in the other buffers may be accessed from context memory514. This eliminates any delay caused by unloading the context information and then reloading the next context information into the context engine.FIG. 5is further shown to include context memory514that stores context information for the different contexts.

FIG. 6is a flow chart of the method of operations involved in moving data using a DMA engine. The method initiates with operation602where the data sequence is loaded into a storage element. In one embodiment the storage element is a buffer. One skilled in the art should understand that the data sequence may be loaded into the storage element via an input/output interface. The interface may be a small computer system interface (SCSI), serial attached SCSI (SAS), serial advanced technology attachment (SATA), internet SCSI (iSCSI), fibre channel (FC), integrated drive electronics (IDE), advanced technology attachment (ATA), etc. The method then advances to operation604, where the context engines are loaded with context information corresponding to the data sequence loaded into the buffer. As described above, the context information may be retrieved from context memory, which stores context information for various contexts. As described above, context information includes the address and count for the data sequence loaded into the storage element. The count could be the number of bits in the data sequence. Context information may also include pointers, which retain the location within the storage element at which the data sequence for a particular context is kept. Context engines are responsible for sending the data sequence to the directed address. The storage element may be configured in a first in first out (FIFO) format necessitating the context engines to finish the data sequence transfer in the order they are activated. As mentioned earlier, the data sequence are transferred to a DMA engine where the data sequence are processed as indicated in operation606. While the data sequence are being processed by the DMA engine, in operation608, the context engines are loaded with the context information for the next set of data sequence that are in the storage element.

Since the context information for the next set of data sequence in the storage element is loaded while the DMA engine process the first set of data sequence, this allows the DMA engine to quickly switch between different context engines. The switching results in maximizing the utilization of the DMA engine data transmission interface and low latency. Similarly, the incorporation of multiple context engines into the design, allows maximum utilization of the storage element. The present invention separates the context engine from the DMA engine, allowing multiple context engines to track different data as they move through the storage element. This allows efficient use of the storage element, DMA engine, and the data transmission interface and minimizes slowdowns on the I/O interface.

While the invention has been disclosed with respect to a limited number of embodiments, numerous modifications and variations will be appreciated by those skilled in the art. It is intended, therefore, that the following claims cover all such modifications and variations that may fall within the true sprit and scope of the invention.