Structure and operating method for nonvolatile memory cell

A structure and operating method for a nonvolatile memory cell. First and second bit lines are disposed on a substrate. A channel is disposed between the first and second bit lines in an active area. First and second selective gates are disposed on the first and second bit lines respectively. An isolation structure is disposed between the first bit line and the first selective gate and between the second bit line and the second selective gate. A control gate is disposed over the first and second selective gates and the channel. An oxide-nitride-oxide (ONO) layer is disposed between the first and second selective gates and the control gate and between the channel and the control gate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to a structure and operating method for a nonvolatile memory cell. In particular, the present invention relates to a nonvolatile memory cell capable of operating at low voltage and its operating method.

2. Description of the Related Art

Memory devices for non-volatile storage of information are currently in widespread use today, in a myriad of applications. A nonvolatile memory is capable of changing its on/off state at the same gate voltage with presence/absence of charge carriers in the charge carrier storage structure. The charge carrier storage structure can be formed by a floating gate electrode or a silicon nitride film. A dielectric carrier trap structure having a silicon nitride film sandwiched between silicon oxide films is known as an oxide-nitride-oxide (ONO) film, and the nonvolatile memory having the dielectric carrier trap structure is called nitride read only memory (NROM).

A traditional NROM is shown in FIG.1. In programming, electrons flowing from the substrate12are trapped in the memory position Maor/and Mbin the silicon nitride layer20near the n-doped region14and16. The silicon nitride layer20is sandwiched between the top oxide layer22and the bottom oxide layer18. In writing data in the silicon nitride layer20near the n-doped region16, that is, the right side, a ground voltage is applied to the n-doped region14, a positive voltage, e.g., 6 V is applied to the n-doped region16, and a high voltage, e.g., 8 V is applied to the control gate24, as shown in Table 1. In this manner, the n-doped regions14and16function as source and drain respectively. These electrons are accelerated in the depletion layer and become hot electrons which pass through the bottom oxide film18and are injected into the silicon nitride film20at a memory position Mb. This writing mode is called channel hot electron (CHE) injection.

In erasing data, as shown in Table 1, a positive voltage, e.g., 7 V is applied to the n-doped region16, and a negative voltage, e.g., −12 V is applied to the control gate24. In this manner, the holes generated by band-to-band tunneling (BTB tunneling) pass through the bottom oxide layer18and are injected into the silicon nitride layer20to neutralize the stored charges at the memory position Mbnear the n-doped region16. This erasing mode is called band-to-band tunneling.

TABLE 1programmingerase(memory(memoryposition Mb)position Mb)Voltage applied to the n-doped region 14Ground(source)Voltage applied to the n-doped region 166 V7 V(drain)Voltage applied to the control gate 248 V−12 V

However, when executing programming and erase, a higher voltage is needed. Thus, high voltage elements are needed in circuit design and complexity of process is increased.

Furthermore, hot electrons and hot holes are generated in programming and erasure. Thus, the reliability of the bottom oxide layer is reduced.

Moreover, when electrons are stored at a position Mbbdifferent from a target memory position Mb, as shown inFIG. 2, the electrons at the changed memory position Mbbcannot be erased by a usual erase operation. For the opposite situation, when holes are injected at a position Mbbdifferent from the predetermined memory position Mb, the electrons at the target memory position Mbcannot be neutralized by the erase operation. No matter which situation occurs, overprogramming will be encountered in the next programming operation. Because the injection positions of electrons and holes are different, after long use, electrons and holes not only cannot be neutralized but will also encounter lateral diffusion.

SUMMARY OF THE INVENTION

In view of the above, it is an object of the present invention to provide a NROM structure having lower voltage and current in programming and erasure, thereby improving the reliability of the bottom oxide layer.

It is another objection of the present invention to provide a NROM structure which can be operated at lower voltage.

It is still another objection of the present invention to provide a NROM structure in which the injection positions of electrons and holes are the same when programming and erasing so as to prevent over programming problem.

According to one aspect of the present invention, a nonvolatile memory cell is provided. A first bit line and a second bit line are disposed in a substrate. A channel is disposed between the first and second bit lines on an active area. A first selective gate and a second selective gate are disposed on the first bit line and the second bit line respectively, wherein bottom corners of the first and second selective gates near the channel are acutely angled. An isolation structure is disposed between the first bit line and the first selective gate and between the second bit line and the second selective gate. A control gate is disposed over the first and second selective gates and the channel perpendicular to the first and second selective gates. An oxide-nitride-oxide (ONO) layer is disposed between the first and second selective gates and the control gate and between the channel and the control gate. The ONO layer has a first memory position and a second memory position near the bottom corners of the first selective gate and the second selective gate respectively.

According to one embodiment of the present invention, the angle of the bottom corners of the first and second selective gates near the channel is about 15˜85°.

When programming the first memory position of the nonvolatile memory cell, a positive voltage is applied to the control gate, the first selective gate and the first bit line, a negative voltage is applied to the second selective gate, and 0V is applied to the second bit line.

When erasing the nonvolatile memory cell, a positive voltage is applied to the first and second selective gates, a negative voltage is applied to the substrate, and the control gate and the first and second bit lines are maintained in a floating state. Alternatively, a positive voltage is applied to the first and second bit lines, and a negative voltage is applied to the first and second selective gates and the control gate, thereby performing an erase operation.

When reading the first memory position of the nonvolatile memory cell, a reading voltage is applied to the second bit line, the first and second selective gate and the control gate, and 0V is applied to the first bit line.

DETAILED DESCRIPTION OF THE INVENTION

In accordance with the related figures, the structure and the operating method for the nitride read only memory (NROM) of the present invention will be explained in detail as follows.

Structure of NROM

The present invention provides a NROM structure, as shown in FIG.3andFIG. 4, whereinFIG. 3is a layout diagram, andFIG. 4is a cross section taken from the VI—VI line located on FIG.3. InFIG. 3, two parallel control gates CG1and CG2, three parallel selective gates BL1, BL2and BL3, and three parallel selective gates SG1, SG2and SG3are shown as an example. A detailed description of the preferred embodiment of the present invention is given in reference to the accompanying drawings.

A cross section of each NROM cell is shown inFIG. 4. Apair of bit lines BL1and BL2, also called embedded bit lines, are disposed in a substrate100. A channel102is disposed between the pair of bit lines BL1and BL2on an active area.

A pair of selective gates SG1and SG2are disposed on the pair of bit lines BL1and BL2respectively, and parallel the pair of bit lines BL1and BL2. The channel102is disposed between the bit line BL1and the bit line BL2in the substrate100, and comprises the area under a part of the pair of selective gates SG1and SG2. The bottom corners120of the pair of selective gates SG1and SG2near the channel102are acutely angled, such as about 15˜85°. Each selective gate SG1or SG2is wider than underlying bit line BL1or BL2. In other words, the elements under each selective gate SG1or SG2comprise a field oxide layer FOX, a part of bit line BL1or BL2and a part of channel102. The selective gates SG1and SG2are polysilicon.

An isolation structure, such as the field oxide layer FOX, is disposed between each bit line BL1or BL2and the corresponding selective gates SG1and SG2. The field oxide layer FOX has a center thickness d1between 630 Å and 670 Å and a side thickness d2between 130 Å and 170 Å.

A control gate CG1is disposed over the selective gates SG1and SG2and the channel102perpendicular to the selective gates SG1and SG2. The control gate CG1is polysilicon.

An oxide-nitride-oxide (ONO) layer110is disposed between the selective gates SG1and SG2and the control gate CG1and between the channel102and the control gate CG1.

The ONO layer110is a stacked structure of bottom oxide layer-silicon nitride layer-top oxide layer, and the bottom oxide layer104, the silicon nitride layer106and the top oxide layer108are about 57˜63 Å, about 47˜53 Å and about 60˜70 Å thick, respectively.

The memory positions Maand Mbare located in the silicon nitride layer106of the ONO layer110near the bottom corners120of the pair of selective gates SG1and SG2.

Programming Operating Method for NROM: Point Discharge Mode

FIG. 5shows a programming operation for NROM according to the preferred embodiment of the present invention.

When programming the memory position Mb(that is right side, the same as shown inFIG. 1) as an example, a positive voltage (+V) is applied to the control gate CG1, the selective gate SG1and the bit line BL1, a negative voltage (−V) is applied to the selective gate SG2and 0V is applied to the bit line BL2. Hence, a higher electric field is created at the bottom corner of the selective gate SG2, resulting in electrons FN tunnelling. The electrons are injected into the silicon nitride layer in the direction shown and are trapped in the memory position Mb. In such case, the threshold voltage (Vt) of the transistor is increased.

Specifically, the positive voltage applied to the control gate CG1, the selective gate SG1and the bit line BL1is about 3˜7 V, and the negative voltage applied to the selective gate SG2is about −3˜−8 V.

Similarly, when programming the memory position Ma(that is left side, the same as shown in FIG.1), the applied voltage of the selective gate SG1and that of the selective gate SG2are changed over, as are the applied voltages of the bit line BL1and bit line BL2. Hence, a higher electric field is created at the bottom corner of the selective gate SG1, resulting in electrons FN tunnelling. The electrons are injected into the silicon nitride layer in the direction shown and are trapped in the memory position Ma.

When programming is carried out by point discharge mode, the electrons are injected into the memory position Maand/or Mbin the silicon nitride layer from the bottom corner of the selective gate SG1and/or SG2. The injecting route of the electrons does not shift, thus, neither do the injecting positions of electrons.

Erase Operating Method for NROM: Point Discharge Mode

FIG. 6shows an erase operation for NROM according to the preferred embodiment of the present invention. A positive voltage (+V) is applied to the selective gates SG1and SG2, a negative voltage (−V) is applied to the substrate Sub, and the control gate CG1and the bit lines BL1and BL2are maintained in a floating state. In such situation, a higher electric field is created at the bottom corner of the selective gates SG1and SG2, resulting in point discharge. The holes are injected into the silicon nitride layer in the direction shown and are trapped in the memory position Maand Mb.

When erasure is carried out by point discharge mode, the holes are injected into the memory position Maand/or Mbin the silicon nitride layer from the bottom corner of the selective gate SG1and/or SG2. The injecting route of the holes does not shift, thus, neither do the injecting positions of electrons, that is, the memory positions Ma and Mb.

Specifically, the positive voltage applied to the selective gates SG1and SG2is about 4˜6 V, and the negative voltage applied to the substrate Sub is about −6˜−8 V.

The injecting routes of the holes generated in the erase operation and that of the electrons generated in the above-mentioned programming operation are the same, both being from the bottom corner of the selective gate SG1and/or SG2into the memory position Maand/or Mbin the silicon nitride layer. Thus, the bottom oxide layer of the ONO layer has good reliability.

Erase Operating Method for NROM: BTB Tunneling Mode

FIG. 7shows an erase operation for NROM according to the preferred embodiment of the present invention. A positive voltage (+V) is applied to the bit lines BL1and BL2, and a negative voltage (−V) is applied to the selective gates SG1and SG2and the control gate CG1. In such situation, holes produced by band-to-band tunneling (BTB tunneling) pass through the bottom oxide layer into the silicon nitride layer to neutralize the charges stored in the memory positions Maand Mb.

Specifically, the positive voltage applied to the bit line BL1and BL2is about 6˜8 V, and the negative voltage applied to the selective gate SG1and SG2and the control gate CG1is about −11˜−13 V.

The injecting routes (from the channel in the substrate into the silicon nitride layer) of the holes generated in the erase operation and of the electrons generated in the above-mentioned programming operation are different. Thus, the bottom oxide layer of the ONO layer has good reliability.

Read Operating Method for NROM

FIG. 8shows a read operation for NROM according to the preferred embodiment of the present invention.

When reading the memory position Mbas an example, the n-doped region under the selective gate SG2functions as source S and the n-doped region under the selective gate SG1functions as drain D. A reading voltage, such as 2˜3 V, is applied to the drain D, the selective gates SG1and SG2and the control gate CG1, and 0 V is applied to the source S. In such situation, a depletion region130is created near the drain D and broadens into the region under the memory position Ma, thus, the read operation is not influenced irrespective of electrons being trapped in the memory position Ma.

When the electrons are trapped in the memory position Mbto be read, the threshold voltage of the transistor is increased, for example, to about 3.5 V. On the contrary, when no electrons are trapped in the memory position Mbto be read, the threshold voltage of the transistor is maintained, for example, about 1.0 V. Hence, the reading voltage is set between the two Vt, preferrably 2˜3 V.

As mentioned above, the NROM structure of the present invention has lower applied voltage and current when executing programming and erase operations. Hence, the reliability of the bottom oxide layer is improved. Furthermore, the NROM can be operated at lower voltage, and high voltage elements are not needed in the circuit design. The circuit design and process are simplified. Moreover, when executing programming and erase operations, the electrons and the holes are injected into the silicon nitride layer at the same position, thus, the electrons or the holes are neutralized without question and overprograming is prevented.

The programming operation for the NROM of the present invention is in point discharge mode and the electrons are injected from the bottom corner of the selective gate into the silicon nitride layer. The erase operation for the NROM of the present invention can be in point discharge mode, in which the holes are injected from the bottom corner of the selective gate into the silicon nitride layer, or in band-to-band tunneling (BTB tunneling) mode, in which the holes are injected from the channel into the silicon nitride layer.