BACK PLANE OF FLAT PANEL DISPLAY AND METHOD OF MANUFACTURING THE SAME

According to an aspect of the present invention, there is provided a back plane for a flat-panel display device and a method of manufacturing the same. The back plane including: a substrate; a gate electrode on the substrate; a first insulation layer on the substrate and covering the gate electrode; a semiconductor layer on the first insulation layer and corresponding to the gate electrode; and a source electrode and a drain electrode on the semiconductor layer and electrically coupled to respective portions of the semiconductor layer. Here, the semiconductor layer includes indium, tin, zinc, and gallium, and an atomic concentration of the gallium is from about 5% to about 15%.

DETAILED DESCRIPTION

The present inventive concept will now will now be described more fully with reference to the accompanying drawings, in which example embodiments of the present inventive concept are shown.

As the present invention allows for various changes and numerous embodiments, example embodiments will be illustrated in the drawings and described in detail in the description. However, this is not intended to limit the present invention to a particular mode of practice, and it is to be appreciated that the present invention encompasses all changes, equivalents, and substitutes that do not depart from the spirit and technical scope thereof. In the description of the present invention, well-known methods will not be described in detail so as not to unnecessarily obscure features of the present invention.

While the terms such as “first” and “second” may be used to describe various components, such components must not be limited to the above terms. The terms are used only to distinguish one component from another. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Also, expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

The terms used in the present application are merely used to describe an embodiment, and are not intended to limit the present invention. Use of singular forms includes plural references as well unless expressly specified otherwise. The terms “comprising”, “including”, and “having” specify the presence of stated features, numbers, steps, operations, elements, components, and/or a combination thereof but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or a combination thereof. When an element is referred to as being “on” or “coupled to” (e.g., electrically coupled or connected to) another element, the element may be directly “on” or “coupled to” the other element or one or more intervening elements may be interposed therebetween.

FIG. 1is a schematic cross-sectional view of a back plane for a flat-panel display device according to an embodiment of the present invention. Referring toFIG. 1, the back plane for a flat-panel display device includes a transistor region2, a storage region3, and an emissive region4. If a flat-panel display device is a top-emission type, the transistor region2and the emissive region4may overlap each other.

In the transistor region2, a thin-film transistor (TFT) is arranged as a driving device. The TFT includes a gate electrode21, an active layer22, and source and drain electrodes23and24. The TFT according to an embodiment of the present invention may be a bottom-gate type in which the gate electrode21is arranged below the active layer22, or a top-contact type in which the source electrode24and the drain electrode23contact the top of the active layer22. Furthermore, material-wise, the TFT may be an oxide semiconductor TFT in which the active layer22includes an oxide semiconductor.

A capacitor Cst is arranged in the storage region3. The capacitor Cst includes a bottom electrode31and a top electrode32, where a first insulation layer10is interposed therebetween. Here, the bottom electrode31may be formed on the same layer and of the same material as the gate electrode21of the TFT. The top electrode32may be formed on the same layer and of the same material as the source and drain electrodes23and24of the TFT.

An organic light emitting device EL is arranged in the emissive region4. The organic light emitting device EL includes a pixel electrode41coupled to either the source electrode24or the drain electrode23of the TFT, a counter electrode40arranged to face the pixel electrode41, and an intermediate layer42, which is interposed between the pixel electrode41and the counter electrode40and includes an organic emissive layer.

According to an embodiment of the present invention, because the emissive region4includes the organic light emitting device EL, the back plane shown inFIG. 1may be used as a back plane for an organic light emitting display device. However, the present invention is not limited thereto. For example, if liquid crystals are arranged between the pixel electrode41and the counter electrode40, the back plane shown inFIG. 1may be used as a back plane for a liquid crystal display device.

FIGS. 2 through 10are schematic cross-sectional diagrams showing a process for manufacturing a back plane for a flat-panel display device according to embodiments of the present invention.

In detail,FIGS. 2 through 4andFIGS. 6(b) through10are schematic cross-sectional diagrams showing a process for manufacturing the back plane for a flat-panel display device as shown inFIG. 1; whereas,FIGS. 5 and 6(a) are schematic cross-sectional diagrams showing a process for manufacturing a back plane for a flat-panel display device according to another embodiment of the present invention.

Hereinafter, the process for manufacturing a back plane for a flat-panel display device will be described in detail by focusing on the transistor region2and the emissive region4, and detailed descriptions of a process for manufacturing the storage region3will be omitted.

First, as shown inFIG. 2, a substrate1is provided. The substrate1may be formed of, for example, a transparent SiO2-based glass material. However, because a flat-panel display device according to an embodiment of the present invention may be a top-emission type, materials for forming the substrate1are not limited thereto. For example, the substrate1may be formed of any of a variety of non-transparent materials, e.g., plastics, metals, etc. Also, the substrate1may be formed of a flexible plastic film or a thin-film glass, such that a flat-panel display may be bent or folded.

A barrier layer, a blocking layer, and/or an auxiliary layer (not shown) (e.g., a buffer layer) may be provided on the top surface of the substrate1to prevent diffusion of impurity ions, to prevent permeation of moisture or outside atmosphere, and to planarize the top surface of the substrate1.

The auxiliary layer may be formed of a silicon oxide (SiO2) and/or a silicon nitride (SiNx) by using any of a variety of deposition methods, such as plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure CVD (APCVD), and low pressure CVD (LPCVD).

Next, as shown inFIG. 3, the gate electrode21is formed on the substrate1. The gate electrode21may be patterned in a masking operation using a first mask (not shown). The first masking operation using the first mask may be performed by using any of a variety of methods including wet etching and dry etching.

The gate electrode21may contain one or more materials selected from among silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), molybdenum-tungsten (MoW), or copper (Cu). However, the present invention is not limited thereto, and the gate electrode21may be formed of other conductive materials, including metals.

The first masking operation as described above forms the gate electrode21on the substrate1.

Referring toFIG. 4, the first insulation layer10is deposited on the structure shown inFIG. 3, which is a resulting structure of the first masking operation, and the semiconductor layer22may be pattern-formed thereon. A second masking operation, as described above, may form the first insulation layer10to cover the gate electrode21and to form the semiconductor layer22on the first insulation layer10in correspondence to the gate electrode21.

The first insulation layer10may be formed of an inorganic insulation layer containing SiNxor SiOxby using PECVD, APCVD, or LPCVD. A portion of the first insulation layer10may be interposed between the semiconductor layer22and the gate electrode21of the transistor region2, and may function as a gate insulation layer of the transistor region2. Furthermore, although not shown inFIG. 4, a portion of the first insulation layer10may be interposed between the bottom electrode31and the top electrode32of the capacitor Cst in the storage region3, and may function as a dielectric layer of the capacitor Cst.

Although formation of the semiconductor layer22is not shown, the semiconductor layer22may be formed by depositing a conductive layer, a photosensitive film thereon, aligning a second mask (not shown) to the first insulation layer10, exposing the photosensitive film by irradiating light in a predetermined wavelength band thereto, and etching the conductive layer other than the semiconductor layer22by using the patterned photosensitive film as an etch stopper.

The semiconductor layer22may include an oxide semiconductor. For example, the semiconductor layer22may include an oxide of a material selected from among Group XII, Group XIII, and Group XIV metal atoms including zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), and hafnium (Hf) and combinations thereof. For example, the semiconductor layer22may contain Ga—Sn—In—Zn—O. The Sn addition may increase mobility of the semiconductor layer22.

The second masking operation may form the semiconductor layer22by using a target including an oxide of In, Zn, and Sn and Ga via sputtering.

Sputtering is an operation in which a target material is formed from a sputtering target having a uniform thickness in correspondence to a magnetic field generated by a magnet unit and the target material is deposited onto a substrate and forms a thin film.

As stated above, fabrication of an oxide-based TFT may embody higher mobility compared to silicon-based semiconductors and may use existing equipment (e.g., equipment for fabricating the silicon-based semiconductors). However, due to a mobility of a threshold voltage due to environmental factors, including light and temperature, reliability of the oxide-based TFT may be unsatisfactory.

Reasons for the mobility of the threshold voltage may include internal defects, such as oxygen vacancy formed in a material used in the semiconductor layer22, and permeation of the outside atmosphere, e.g., hydrogen, moisture. To prevent such defects, the semiconductor layer22may be protected by using an etch stop layer (ESL), or device reliability may be secured by adjusting operation conditions, such as oxygen partial pressure, heat treatment temperature, and sputtering voltage. However, more fundamentally, device reliability may be secured by changing materials used in the semiconductor layer22.

According to an embodiment of the present invention, the semiconductor layer22may include an In—Sn—Zn—O (ITZO) material and may further include Ga. Here, the atomic concentration of Ga may be from about 5% to about 15%. When Ga is contained in the ratio as stated above, carrier mobility of the semiconductor layer22is maintained at an appropriate level, and reliability of the TFT including the semiconductor layer22is improved. As used herein, Ga concentration is an atomic concentration.

If Ga concentration is smaller than about 5%, hole mobility and carrier mobility of the semiconductor layer22vary according to oxygen partial pressure during fabrication. Even a small variation of oxygen partial pressure changes hole mobility and carrier mobility. Therefore, hole mobility and carrier mobility significantly vary according to environmental changes, and hole mobility and carrier mobility of the semiconductor layer22become non-uniform. As a result, reliability of the TFT is deteriorated.

As the Ga concentration increases, hole mobility and carrier mobility become less sensitive to oxygen partial pressure during fabrication. As a result, hole mobility of the semiconductor layer22becomes uniform, and thus, reliability of the TFT is improved.

However, if Ga concentration exceeds about 15%, regardless of the uniformity of hole mobility, electron effective mass of the semiconductor layer22increases, thereby reducing hole mobility. Therefore, it may become difficult to embody a high-performance device.

Accordingly, in embodiments of the present invention, Ga concentration may be from about 5% to about 15%. When the semiconductor layer22contains Ga at a concentration within this range, the semiconductor layer22may secure a sufficient hole mobility and may retain uniform device characteristics even if the fabrication environment slightly varies. Therefore, device reliability may be secured.

Data will be given below with reference toFIGS. 11 and 12regarding characteristics of the semiconductor layer22according to Ga concentration.

Referring now toFIG. 5, a second insulation layer11may be deposited on the structure ofFIG. 4, which is a resulting structure of the second masking operation, and may be patterned. In detail, the second insulation layer11is deposited on the structure ofFIG. 4, and a portion of the second insulation layer11is etched for forming a first hole11aand a second hole11bthat expose portions of the semiconductor layer22. The second insulation layer11may protect the semiconductor layer22. The first hole11aand the second hole11bmay be formed by using any of a variety of methods, including wet etching and dry etching, as long as portions of the semiconductor layer22therebelow are not etched.

A third masking operation, as described above, forms the second insulation layer11, which includes the first hole11aand the second hole11bexposing portions of the semiconductor layer22and which covers the semiconductor layer22, on the first insulation layer10. The third masking operation may be performed for protecting the semiconductor layer22, and thus, may be omitted to simplify the overall process.

Referring toFIG. 6(a), the source electrode24and the drain electrode23may be pattern-formed on the structure ofFIG. 5, which is a resulting structure of the third masking operation. Referring toFIG. 6(a), the source electrode24and the drain electrode23may be formed on the second insulation layer11and may fill the first hole11aand the second hole11b.

FIG. 6(b) shows that, when the third masking operation is omitted, the source electrode24and the drain electrode23are pattern-formed on the structure ofFIG. 4, which is a resulting structure of the second masking operation. Referring toFIG. 6(b), the source electrode24and the drain electrode23are formed on the first insulation layer10, and the source electrode24and the drain electrode23may contact potions of the semiconductor layer22, respectively.

The source electrode24and the drain electrode23may contain one or more materials selected from among silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), molybdenum-tungsten (MoW), or copper (Cu). However, the present invention is not limited thereto, and the source electrode24and the drain electrode23may be formed of any of a variety of conductive materials, including metals.

A fourth masking operation, as described above, forms the source electrode24and the drain electrode23, which contact portions of the semiconductor layer22, on the second insulation layer11. Later operations will be described based onFIG. 6(b) corresponding to the case in which the formation of the second insulation layer11is omitted.

Referring now toFIG. 7, a third insulation layer20, in which a third hole20aexposing a portion of the source electrode24or the drain electrode23is formed. The third insulation layer20may be formed on the structure ofFIG. 6(b), which is a resulting structure of the fourth masking operation.

The third hole20amay be pattern-formed in a masking operation using a fifth mask (not shown). The third hole20amay be formed to electrically connect a pixel electrode, described below, and the TFT in the transistor region2. AlthoughFIG. 7shows that the third hole20ais formed to expose the drain electrode23, the present invention is not limited thereto; for example, the third hole20amay be formed to expose the source electrode24. Furthermore, a shape and location of the third hole20aare not limited to what is shown inFIG. 7.

The third insulation layer20may be formed of one or more organic insulation materials selected from a group consisting of polyimide, polyamide, acrylic resins, benzocyclobutene, and phenol resins by using a method like spin coating. However, the third insulation layer20may not only be formed of organic insulation materials as stated above, but also may be formed of inorganic materials selected from among SiO2, SiNx, Al2O3, CuOx, Tb4O7, Y2O3, Nb2O5, and Pr2O3. Furthermore, the third insulation layer20may have a multi-layer structure in which organic insulation materials and inorganic insulation materials are alternately stacked.

The third insulation layer20is formed to have a sufficient thickness, e.g., a thickness greater than that of the first insulation layer10or the second insulation layer11, and may function as a planarizing layer for planarizing the surface on which pixel electrodes described below will be formed, or may function as a passivation layer for protecting the drain electrode23and the source electrode24in the transistor region2.

A fifth masking operation, as described above, forms the third insulation layer20(in which the third hole20aexposing a portion of the source electrode24or the drain electrode23is formed) on the first insulation layer10to cover the source electrode24and the drain electrode23. If the second insulation layer11is formed in the fourth masking operation, the third insulation layer20may be formed on the second insulation layer11.

Referring now toFIG. 8, the pixel electrode41may be formed on the structure ofFIG. 7, which is a resulting structure of the fifth masking operation. The pixel electrode41may be formed on the third insulation layer20and may be electrically connected to either the source electrode24or the drain electrode23. The pixel electrode41may fill the third hole20aof the third insulation layer20and may be electrically connected to the portion of the source electrode24or the drain electrode23that is exposed by the third hole20a.The pixel electrode41may be pattern-formed in a masking operation using a sixth mask (not shown).

The pixel electrode41may be coupled to either the source electrode24or the drain electrode23via the third hole20a.The pixel electrode41may be formed of any of a variety of materials according to an emission type of an organic light emitting display device. For example, if the organic light emitting display device is a bottom-emission type (in which an image is formed toward the substrate1) or a dual-emission type (in which an image is formed both toward the substrate1and in a direction opposite thereto), the pixel electrode41may be formed of a transparent metal oxide. The pixel electrode41may include one or more materials from among materials including ITO, IZO, ZnO, and In2O3. In this case, although not shown, the pixel electrode41may be designed to not to overlap the transistor region2and the storage region3.

However, if the organic light emitting display device is a top-emission type (in which an image is formed in a direction away from the substrate1), the pixel electrode41may further include a reflective electrode formed of a material for reflecting light. In this case, the pixel electrode41may be designed to partially overlap the transistor region2as shown inFIG. 8.

A sixth masking operation, as described above, forms a pixel electrode41, which fills the third hole20aand is electrically connected to the portion of the source electrode24or the drain electrode23, on the third insulation layer20.

Referring now toFIG. 9, a fourth insulation layer30may be formed on the structure ofFIG. 8, which is a resulting structure of the sixth masking operation. The fourth insulation layer30may be formed to cover edges of the pixel electrode41and may include an opening30aexposing at least a portion of the pixel electrode41. The fourth insulation layer30may be pattern-formed in a masking operation using a seventh mask (not shown).

Referring now toFIG. 10, the intermediate layer42and the counter electrode40may be formed on the structure ofFIG. 9, which is a resulting structure of a seventh masking operation. For example, an eighth masking operation may form the intermediate layer42including an organic light-emitting layer on the portion of the pixel electrode41exposed by the opening30aand may form the counter electrode40to face the pixel electrode41across the intermediate layer42.

The intermediate layer42may be formed as one or more functional layers from among an organic emissive layer (EML), a hole transport layer (HTL), a hole injection layer (HIL), and an electron injection layer (EIL). The intermediate layer42may be stacked in a single-layer structure or a composite structure. The intermediate layer42may be formed of an organic monomer material or an organic polymer material.

If the intermediate layer42is formed of an organic monomer material, a HTL and a HIL are stacked from an EML toward the pixel electrode41, whereas an ETL and an EIL are stacked from the EML toward the counter electrode40. Here, the organic materials may include copper phthalocyanine (CuPC), N,N′-Di(naphthalene-1-yl)-N,N′-diphenyl-benzidine (NPB), tris-8-hydroxyquinoline aluminum (Alq3), etc.

If, however, the intermediate layer42is formed of an organic polymer material, only a HTL may be formed from an EML toward the pixel electrode41. The HTL may be formed on the top of the pixel electrode41using poly-(2,4)-ethylene-dihydroxy thiophene (PEDOT) or polyaniline (PANI) via a method including inkjet printing and spin coating. Here, the organic materials may include poly-phenylenevinylene (PPV)-based organic polymer materials or polyfluorene-based organic polymer material, and a color pattern may be formed via a common method, including inkjet printing, spin coating, or laser thermal transfer.

The EML may form a unit pixel including sub-pixels emitting red, green, and blue lights.

The counter electrode40may be deposited onto the entire substrate1and be formed as a common electrode. In the case of the organic light emitting display device according to the present embodiment, the pixel electrode41may be used as an anode, whereas the counter electrode40may be used as a cathode, or vice versa.

In the embodiment described above, the intermediate layer42is formed in the opening30a,and light-emitting materials are independently formed in respective pixels. However, the present invention is not limited thereto. For example, the intermediate layer42may be formed throughout the fourth insulation layer30regardless of locations of pixels.

For example, the intermediate layer42may be formed as emissive layers, including emissive materials emitting red light, green light, and blue light, and may be stacked in a vertical direction or mixed. Other color combinations are possible, for example, when white light is emitted. Furthermore, a color converting layer or a color filter for converting the emitted white light to light of a predetermined color may be further arranged.

If the organic light emitting display device is a top-emission type (in which an image is formed in a direction away from the substrate1), the counter electrode40is a transparent electrode and the pixel electrode41is a reflective electrode. Here, the reflective electrode may be formed by depositing a metal having a small work function, e.g., Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, or a compound thereof, to have a small thickness. In a back plane for a flat-panel display device according to an embodiment of the present invention, the counter electrode40may be formed as a phototransmissive electrode.

In the masking operations for forming the organic light emitting display device, stacked layers may be removed via dry etching or wet etching. Furthermore, although each of the attached drawings for describing embodiments of the present invention shows one transistor and one capacitor for convenience of explanation, the present invention is not limited thereto, and a plurality of TFTs and a plurality of capacitors may be included. According to an embodiment of the present invention, including a plurality of TFTs and a plurality of capacitors does not increase the number of masking operations.

FIGS. 11-12are graphs showing characteristics of the semiconductor layer22according to Ga concentration.FIG. 11shows graphs illustrating hole mobility characteristics of the semiconductor layer22according to Ga concentration, whereasFIG. 12shows graphs illustrating carrier concentration characteristics of the semiconductor layer22according to Ga concentration. Hereinafter, Ga concentration is atomic concentration.

First, referring toFIG. 11, a graph111corresponds to a case in which oxygen partial pressure is 0% during fabrication of the semiconductor layer22, whereas a graph112corresponds to a case in which oxygen partial pressure is 5% during fabrication of the semiconductor layer22. Hole mobilities of the semiconductor layer22corresponding to different Ga concentrations are shown.

Referring toFIG. 11, when a target for forming the semiconductor layer22contains Ga at 0% concentration, hole mobility of the semiconductor layer22varies significantly according to oxygen partial pressure during the fabrication of the semiconductor layer22. However, when the target for forming the semiconductor layer22contains Ga at about 5% or higher concentration, hole mobility of the semiconductor layer22is constant (or substantially constant) even if oxygen partial pressure varies during the fabrication of the semiconductor layer22. Therefore, because hole mobility of the semiconductor layer22is constant even if oxygen partial pressure varies during the fabrication of the semiconductor layer22, device reliability is improved.

Referring toFIG. 12, a graph114corresponds to a case in which oxygen partial pressure is 0% during fabrication of the semiconductor layer22, whereas a graph115corresponds to a case in which oxygen partial pressure is about 5% during fabrication of the semiconductor layer22. Carrier concentrations of the semiconductor layer22corresponding to different Ga concentrations are shown.

Referring toFIG. 12, when a target for forming the semiconductor layer22contains Ga at 0% concentration, carrier concentration of the semiconductor layer22varies significantly according to oxygen partial pressure during the fabrication of the semiconductor layer22. However, when the target for forming the semiconductor layer22contains Ga at about 5% or higher concentration, carrier concentration of the semiconductor layer22is constant (or substantially constant) even if oxygen partial pressure varies during the fabrication of the semiconductor layer22. Therefore, because carrier concentration of the semiconductor layer22is constant even if oxygen partial pressure varies during the fabrication of the semiconductor layer22, device reliability is improved.

FIG. 13is a graph showing another characteristic according to Ga concentrations. In detail,FIG. 13shows electron effective mass and hole mobility according to Ga concentrations. InFIG. 13, a graph121shows electron effective mass of the semiconductor layer22according to Ga concentration when composition ratio among tin, indium, and zinc is 2:1:3, a graph122shows electron effective mass of the semiconductor layer22according to Ga concentration when composition ratio among tin, indium, and zinc is 2:3:3, and a graph123shows hole mobility of the semiconductor layer22according to Ga concentration when composition ratio among tin, indium, and zinc is 2:3:3.

Electron effective mass may be calculated according to Equation 1 below. Equation 1:

Here, μ may denote mobility, m* may denote electron effective mass, and τ may denote average electron scattering time. Electron effective masses according to respective Ga concentrations may be calculated in a simulation, and mobility may be induced by applying the calculated electron effective masses to Equation 1.

Referring toFIG. 13, the graph121shows that electron effective mass continuously increases as Ga concentration increases, and thus, mobility continuously increases. However, the graph122shows that electron effective mass reaches a predetermined limit value as Ga concentration increases, and the graph123shows that hole mobility decreases as Ga concentration increases.

Referring toFIG. 13, although hole mobility decreases as Ga concentration increases, in an embodiment of the present invention, a suitable (or sufficient) hole mobility may be secured as long as Ga concentration does not exceed about 15%.

Table 1 below shows a result of a simulation regarding electron effective masses according to Ga concentration in ITZO.

Referring to the result of the simulation, it is clear that electron effective mass increases as Ga concentration increases, thereby reducing mobility. When the result of the simulation as shown in Table 1 is reflected to Equation 1, mobilities in the respective cases may be calculated.

According to the report Amorphous Oxide Semiconductors for High-Performance Flexible Thin-Film Transistors (Journal: Jpn. J. Appl. Phys., 45, 4303 (2006), Author: Hideo Hosono), the entire content of which is incorporated herein by reference, the minimum mobility of an amorphous oxide for embodying a high-performance device is at least 10 cm2.V−1.s−1.

However, referring to Table 1 and Equation 1, mobility is 10 cm2. V−1.s−1when Ga concentration is 15%. According to the result of the simulation shown in Table 1, mobility decreases as electron effective mass increases as Ga concentration increases, and thus, it is difficult to guarantee the mobility of 10 cm2.V−1.s−1when Ga concentration exceeds 15%.

Therefore, when Ga concentration of a sputtering target for forming the semiconductor layer22is set to from about 5% to about 15%, and thus, Ga concentration of the semiconductor layer22is set to from about 5% to about 15%, suitable (or sufficient) hole mobility for embodying a hih-performance device may be maintained and reliability of a TFT may be secured.

According to embodiments of the present invention, an organic light emitting display apparatus includes an oxide semiconductor layer including an oxide of indium, tin, and zinc and gallium, thereby exhibiting high mobility and stable electric characteristics. For example, as the oxide semiconductor layer containing an oxide of indium, tin, and zinc and gallium contains gallium at an atomic concentration from about 5% to about 15%, 10 cm2.V−.s−1or higher mobility may be secured. Furthermore, device characteristics do not vary significantly according to environmental variables during fabrication, and thus, reliability of a TFT may be secured.