Switching power supply including threshold based permissions

Aspects of the invention provide a switching power supply that exhibits an improved conversion efficiency. In aspects of the invention, a load condition detecting circuit sets a threshold voltage for determining the magnitude of the load on the DC-DC converter based on the maximum value of the output voltage of the power factor correction converter in a suspended period of the power factor correction converter. An operation permission signal is delivered when a feedback voltage that indicates the magnitude of the load of the DC-DC converter exceeds the threshold voltage. When the feedback voltage exceeds a threshold voltage that is set at a value higher than the threshold voltage, the operation permission signal is delivered.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate to switching power supplies, and, in particular, switching power supplies including power factor correction converters.

2. Description of the Related Art

Power factor correction is used for switching power supplies of power rating over 75 W to provide stability and safety in commercial power systems. Recently, a switching power supply has been proposed in Japanese Unexamined Patent Application Publication No. 2007-288855, for example, having a small-sized and highly efficient power factor correction converter (PFC) and a DC-DC converter that converts a DC voltage obtained by the PFC into an output DC voltage according to the specification of the load. The DC-DC converters employed in such switching power supplies are often quasi-resonance converters (QR) in the case of a rated load of about 100 W because of a little burden on a rectifying diode in the secondary side.

FIG. 7shows a schematic construction of a switching power supply1having a power factor correction converter2and a DC-DC converter3that is a quasi-resonance converter.FIG. 7also shows a rectifying circuit4that rectifies the AC power supplied by the commercial power supply5and delivers to the power factor correction converter2, and a noise filter6interposed between the rectifying circuit4and the commercial power supply5.

The power factor correction converter2comprises an inductor L1connected to the rectifying circuit4, a switching element Q1, and a diode D1. The switching element Q1forms a current path from the rectifying circuit4through the inductor L1in the ON state of the switching element Q1. The diode D1forms a current path from the inductor L1to an output capacitor C2in the OFF state of the switching element Q1. The power factor correction converter2comprises a control circuit IC1that ON/OFF drives the switching element Q1to control the current flowing through the inductor L1thereby obtaining a stable DC voltage Vb.

Resistors R1and R2divide the voltage Vb across the output capacitor C2. The divided voltage is fed back to the control circuit IC1. A shunt resistor R3detects the current flowing through the load of the power factor correction converter2. The operation and effects of the power factor correction converter2as described above are disclosed in detail in Japanese Unexamined Patent Application Publication No. 2010-220330, for example.

The DC-DC converter3that is a quasi-resonance converter basically comprises: an isolating transformer T having a primary winding P1, a secondary winding S1, and an auxiliary winding P2; a switching element Q2connected to the primary winding P1, which receives the output DC voltage Vb of the power factor correction converter2; a resonance capacitor C4connected in parallel with the switching element Q2; and an output capacitor C5connected through a rectifying diode D2to the secondary winding S1of the isolating transformer T. The DC-DC converter3comprises a control circuit IC2that ON/OFF drives the switching element Q2to generate quasi-resonance phenomenon with a leakage inductance of the transformer T and the resonance capacitor C4, thereby obtaining a specified output DC voltage Vo.

The resistances R5and R6divide the output DC voltage Vo across the output capacitor C5. The divided voltage is fed back to the control circuit IC2through a feedback circuit. A shunt resistor R4detects the current flowing through the switching element Q2. The DC-DC converter3detects a ZCD voltage developed on the auxiliary winding P2of the isolating transformer T and controls the turn ON timing of the switching element Q2. The operation and effects of the DC-DC converter3that is a quasi-resonance converter as described above are disclosed in detail in Japanese Unexamined Patent Application Publication No. 2011-015570, for example.

The DC-DC converter3is provided with a load condition detecting circuit7that detects a load condition and delivers an operation permission signal EN for operation of the power factor correction converter2to permit or stop the operation of the power factor correction converter2. The power factor correction converter2is provided with an operation control circuit8that permits or stops operation of the power factor correction converter2according to the operation permission signal EN. The load condition detecting circuit7suspends operation of the power factor correction converter2under a light load condition of an input power lower than 75 W, for example, to eliminate any power loss in the power factor correction converter2. Thus, the overall power conversion efficiency of a switching power supply1is improved.

The load condition detecting circuit7is constructed as shown inFIG. 8, for example, and installed in the control circuit IC2. The load condition detecting circuit7comprises a comparator7b, which is a light load detecting circuit, and a comparator7c, which is a middle load detecting circuit. The light load detecting circuit7bdetermines a light load condition and sets a flip-flop7awhen the feedback voltage FB, which is used for ON/OFF controlling the switching element Q2in the DC-DC converter3, falls below a preset first threshold voltage Vref1. The middle load detecting circuit7cdetermines a middle load condition, which is with an ordinary load, and resets the flip-flop7awhen the feedback voltage FB exceeds a second threshold voltage Vref2, which is larger than Vref1and explained later. The output of the flip-flop7ais used for set/reset control of a flip-flop7eafter delaying processing through a delay circuit7dutilizing charging and discharging of a capacitor Ct. Thus, the operation permission signal EN is obtained as a set output of the flip-flop7e.

The delay circuit7dcomprises the capacitor Ct and a switching element S connected in parallel with the capacitor Ct. When the output of the flip-flop7ais in an H level, the switching element S is in an OFF state to charge the capacitor Ct with a constant current source It. When the output of the flip-flop7ais at an L level, the switching element S is in an ON state to discharge the charges accumulated on the capacitor Ct through the resistor Rt. The load condition detecting circuit7comprises comparators7fand7g. The comparator7fresets the flip-flop7ewhen the charged voltage Vd on the capacitor Ct exceeds a second reference voltage Vth2; and the comparator7gsets the flip-flop7ewhen the charged voltage Vd falls below a first reference voltage Vth1.

FIG. 9illustrates waveforms in operation of the load condition detecting circuit7having the construction described above. When the load Po becomes lighter and the feedback voltage FB drops below the first threshold value Vref1, the flip-flop7ais set. According to the setting of the flip-flop7a, the switching element S in the delay circuit7dturns OFF and the capacitor Ct is charged with a rate determined by the capacitance of the capacitor Ct and the magnitude of the constant current fed by the constant current source It. After a specified period of time Td-off when the charged voltage Vd of the capacitor Ct exceeds the reference voltage Vth2, the flip-flop7eis reset and the operation permission signal EN turns to an L level to control the power factor correction converter2to stop.

After stop of operation of the power factor correction converter2, the output voltage Vb of the power factor correction converter2gradually decreases and then settles down to a voltage determined by the AC voltage Vac supplied by the commercial power supply5. The output voltage Vb of the power factor correction converter2changes periodically with a period of rectification of the AC voltage Vac and an amplitude determined by the magnitude of the load Po and the capacitance of the output capacitor C2.

In this suspended state of operation of the power factor correction converter2, when the load Po becomes heavy, the feedback voltage FB in the DC-DC converter3rises. When the feedback voltage FB exceeds the second threshold voltage Vref2, the flip-flop7ais reset and the charges accumulated on the capacitor Ct in the delay circuit7dare discharged. After a specified period of time Td-on when the charged voltage Vd of the capacitor Ct falls below the reference voltage Vth1, the flip-flop7eis set to turn the operation permission signal EN to an H level. Consequently, operation of the power factor correction converter2is permitted and the power factor correction converter2resumes operation.

In the suspended state of the power factor correction converter2, the DC voltage Vb obtained at the output capacitor C2of the power factor correction converter2changes periodically as described previously with an amplitude determined by the magnitude of the load Po and the capacitance of the output capacitor C2. Accordingly, it has been noted conventionally that the bottom voltage Vb-min of the DC voltage Vb varies depending on the magnitude of the load Po and thus, the second threshold voltage Vref2for the feedback voltage FB has been set based on the minimum of the DC voltage Vb, the bottom voltage Vb-min.

When the AC voltage Vac is lower than the rated voltage, for example 100 V, or in the case of a small capacitance of the output capacitor C2, even through without large variation in the load Po, the feedback voltage FB rises with decrease in the DC voltage Vb as described earlier. Thus, a situation arises that the feedback voltage FB becomes higher than the second threshold voltage Vref2that is set based on the minimum of the DC voltage Vb, the bottom voltage Vb-min. This situation causes erroneous detection of increase in the load Po. Thus there is a problem that distinct detection of the rise of the feedback voltage FB that is caused by the increase in the load Po cannot be assured.

FIG. 10shows a relationship between the feedback voltage FB and the DC voltage Vb depending on the AC voltage Vac in the case of a load Po of a constant value of 30 W, for example. It is shown that the feedback voltage FB increases with decrease in the DC voltage Vb. When the output DC voltage Vb becomes below about 85 V, the feedback voltage FB is always higher than the second threshold voltage Vref2despite the fact that the load Po is in a light load condition of 30 W constant.

The comparator7cdetects this state to reset the flip-flop7a, which in turn sets the flip-flop7eand turns the operation permission signal EN to an H level. Thus, the power factor correction converter2changes into an operating state according to the operation permission signal EN despite no change in the magnitude of the load Po. Therefore, it becomes impossible to perform the intended operation in which when the DC voltage Vb decreases with drop of the AC voltage Vac, the power factor correction converter2resumes operation thereof after detecting increase in the load Po in a suspended state of the power factor correction converter2.

To cope with this problem, the second threshold voltage Vref2could be set relatively high. A high value of the second threshold voltage Vref2, however, makes detection of increased load Po difficult. As a result, when the AC voltage Vac is stable at a sufficiently high value and the operation of the power factor correction converter2is suspended, increase in the load Po may not cause operation of the power factor correction converter2resume. As a consequence, the DC-DC converter3may also fail to adapt to and deal with the increase in the load Po, causing another problem of poor operation of the switching power supply itself. Thus, as has been discussed above, there is a need in the art for an improved switching power supply.

SUMMARY OF THE INVENTION

Embodiments of the invention address these and other needs. Embodiments of the invention provide a switching power supply that does not permit unintended operation of a power factor correction converter2in a light load condition even under a condition of dropped AC voltage, and that starts operation of the power factor correction converter2immediately on an event of rapid increase in the load, thereby ensuring appropriate control of the power factor correction converter2corresponding to the load condition to improve the conversion efficiency of the switching power supply.

Some embodiments include: a power factor correction converter that conducts switching of an input AC voltage to obtain a DC voltage; a DC-DC converter, a quasi-resonance converter, for example, that conducts switching of an output voltage Vb of the power factor correction converter to obtain a specified DC output voltage Vo; and a load condition detecting circuit that delivers an operation permission signal EN to the power factor correction converter corresponding to a load condition of the DC-DC converter and permit or stop operation of the power factor correction converter; wherein the load condition detecting circuit sets a second threshold voltage and a third threshold voltage for determining a magnitude of the load on the DC-DC converter based on the maximum value Vb-max of the output voltage Vb of the power factor correction converter in a suspended state of operation of the power factor correction converter; delivers the operation permission signal EN when a signal indicating the magnitude of the load on the DC-DC converter exceeds the second threshold voltage for a specified period of time in a suspended state of operation of the power factor correction converter; and delivers the operation permission signal EN when the signal indicating the magnitude of the load on the DC-DC converter exceeds the third threshold voltage in a suspended state of operation of the power factor correction converter.

In some embodiments, the load condition detecting circuit comprises a voltage detecting means that detects the maximum value of the output voltage of the power factor correction converter in a suspended state of operation of the power factor correction converter, and the load condition detecting circuit sets the second threshold voltage and the third threshold voltage for determining the magnitude of the load on the DC-DC converter corresponding to the maximum of the output voltage that is detected by the voltage detecting means.

Specifically, in some embodiments, the second threshold voltage and the third threshold voltage are set as threshold voltages for a feedback voltage FB that is used for controlling a DC output voltage in the DC-DC converter, or alternatively, the second threshold voltage and the third threshold voltage are set as threshold voltages for a periodic voltage Vsw that is proportional to a period of time Tonoff of an ON/OFF driving period of an switching element in the DC-DC converter.

In some embodiments, the load condition detecting circuit comprises: a flip-flop that delivers the operation permission signal EN when the flip-flop is reset; a light load detecting circuit that sets the flip-flop when the feedback voltage FB of the DC-DC converter falls below a predetermined first threshold voltage Vref1; a middle load detecting circuit that resets the flip-flop when the feedback voltage FB exceeds, for a specified period of time Tdelay which can be about a half period of the AC voltage or longer, a second threshold voltage Vref2that is higher than the first threshold voltage Vref1and determined based on the maximum value Vb-max of an input voltage of the DC-DC converter; and a heavy load detecting circuit that resets the flip-flop forcedly when the feedback voltage FB exceeds a third threshold voltage that is set at a value higher than the second threshold voltage.

Alternatively, in other embodiments, the load condition detecting circuit comprises: a flip-flop that delivers the operation permission signal EN when the flip-flop is reset; a light load detecting circuit that sets the flip-flop when the periodic voltage Vsw of the DC-DC converter falls below a predetermined first threshold voltage Vref1; a middle load detecting circuit that resets the flip-flop when the periodic voltage Vsw exceeds, for a specified period of time Tdelay which can be about a half period of the AC voltage or longer, a second threshold voltage Vref2that is higher than the first threshold voltage Vref1and determined based on the maximum value Vb-max of an input voltage of the DC-DC converter; and a heavy load detecting circuit that resets the flip-flop forcedly when the periodic voltage exceeds a third threshold voltage that is set at a value higher than the second threshold voltage.

In some embodiments of a switching power supply having the construction described above, the second threshold voltage Vref2for detecting increase in the load Po in a suspended period of the power factor correction converter is determined based on the maximum value Vb-max of the output voltage Vb of the power factor correction converter in a suspended time of the power factor correction converter. The maximum value Vb-max of the output voltage Vb of the power factor correction converter depends neither on the capacitance of the output capacitor of the power factor correction converter nor on varying magnitude of the load Po of the DC-DC converter, but the maximum value Vb-max depends only on the magnitude of the AC voltage Vac.

Thus, in some embodiments, even in the case the feedback voltage FB rises with decrease of the output voltage Vb, since the second threshold voltage Vref2for the feedback voltage FB is set corresponding to the decrease in the output voltage Vb, such an erroneous detection is avoided that the increase in the feedback voltage FB caused by the decrease in the output voltage Vb is recognized incorrectly as increase in the load Po. The load condition detecting circuit of a switching power supply of the invention ensures detection of solely the increase in the feedback voltage FB that is caused by the increase in the load Po.

Also, in some embodiments, in the case the second threshold voltage Vref2is set for the periodic voltage Vsw proportional to the period of time Tonoff of the ON/OFF driving period of the switching element in the DC-DC converter, such an erroneous detection is similarly avoided that the increase in the periodic voltage Vsw caused by the decrease in the output voltage Vb is recognized incorrectly as increase in the load Po. Thus, the load condition detecting circuit of a switching power supply of the invention ensures detection of solely the increase in the periodic voltage Vsw that is caused by the increase in the load Po.

Consequently, it should not occur for the second threshold voltage Vref2to be surpassed by the feedback voltage FB or by the periodic voltage Vsw caused by the decrease in the output voltage Vb due to the drop of the AC voltage Vac in a constant light load condition, although such event may occur when the second threshold voltage Vref2is set based on the minimum value, the bottom voltage Vb-min, of the output voltage Vb. Therefore, the power supply of the invention ensures control of operation and suspension of operation of the power factor correction converter corresponding to the load condition even in the case of drop of the AC voltage Vac, improving the overall conversion efficiency of the switching power supply.

In some embodiments, in the case the load Po increases abruptly, the load condition detecting circuit of the switching power supply of the invention detects rapid increase of the feedback voltage FB or the periodic voltage Vsw utilizing the third threshold voltage Vref3. When the feedback voltage FB or the periodic voltage Vsw exceeds the third threshold voltage Vref3, the operation permission signal EN is delivered forcedly, immediately making the power factor correction converter into operation. Thus, such an event is avoided that the DC-DC converter fails to deal with the abrupt increase in the load Po. Therefore, a switching power supply1, of embodiments of the invention, provides for stable operation.

DETAILED DESCRIPTION

The following describes a switching power supply according to embodiments of the present invention, with reference to the accompanying drawings.

The switching power supply1of some embodiments of the invention has a similar construction as the conventional one shown inFIG. 7. The switching power supply1of the invention comprises a power factor correction converter2, a DC-DC converter3that performs switching operation on the output voltage Vb of the power factor correction converter2to obtain a specified DC output voltage Vo, and a load condition detecting circuit7that delivers an operation permission signal EN to the power factor correction converter2corresponding to the load condition of the DC-DC converter3to control operation and suspension of the power factor correction converter2.

FIG. 1shows a schematic construction of the load condition detecting circuit7installed in the DC-DC converter3, which is a quasi-resonance converter, the load condition detecting circuit7being a characteristic part of the switching power supply1of the invention. Although the load condition detecting circuit7ofFIG. 1performs basically the similar function as the conventional load condition detecting circuit7inFIG. 8, the load condition detecting circuit7in the invention comprises a comparator7hfor detecting a heavy load as well as the comparator7bfor detecting a light load and the comparator7cfor detecting a middle load, which is a normal load.

In addition, the load condition detecting circuit7of embodiments of the invention comprises a delay circuit7ifor delaying the output of the comparator7cfor a specified period of time Tdelay, and an OR circuit7jfor delivering the output of the delay circuit7ior the output of the comparator7hto the reset terminal of the flip-flop7a. Some embodiments include a second threshold voltage Vref2set for the comparator7cand a third threshold voltage Vref3set for the comparator7h, the Vref3being greater than Vref2, are determined based on the maximum value of the output voltage Vb, the peak voltage Vb-max, of the power factor correction converter2.

When the output voltage Vb decreases under the condition of a constant load Po, the feedback voltage FB of the DC-DC converter3rises in order to maintain the specified DC output voltage Vo. As a consequence, the feedback voltage FB would exceed, as described previously, the second threshold voltage Vref2that is set based on the minimum value of the output voltage Vb, the bottom voltage Vb-min, of the power factor correction converter2depending on the load Po.

In contrast, by setting the second and third threshold voltages Vref2and Vref3based on the maximum value of the output voltage Vb, the peak voltage Vb-max as in the invention, the second and third threshold voltages Vref2and Vref3for the feedback voltage FB increases corresponding to the decreased output voltage Vb. Thus the feedback voltage FB that increases with decrease in the output voltage Vb does not exceed the second and third threshold voltages Vref2and Vref3. Therefore, the load condition detecting circuit of the invention ensures detection only of the increase in the feedback voltage FB that is caused by increase in the load Po.

Description is made here about the delay circuit7ifor delaying the output of the comparator7cfor a specified period of time Tdelay. The delay circuit7icomprises a capacitor Ct2, a constant current source It2, a switching element S2, and a comparator7k. The switching element S2is in an OFF state when the output of the comparator7cis at an H level, and the capacitor Ct2is charged by the constant current source It2. The switching element S2is in an ON state when the output of the comparator7cis at an L level, and the capacitor Ct2is discharged through a resistor Rt2. The comparator7kresets the flip-flop7awhen the charged voltage Vb2of the capacitor Ct2, which is charged and discharged in the way as described above, exceeds a reference voltage Vth3. The specified period of time Tdelay is set at about a half period of the AC voltage Vac, which is about 10 ms in the case of 50 Hz AC voltage, for example.

Owing to the delay circuit7ihaving the construction described above, even if the feedback voltage FB temporarily exceeds the threshold voltage Vref2to turn the output of the comparator7cto an H level, the flip-flop7ais not reset as long as the H level does not continue for the specified period of time Tdelay, which is about 10 ms. In other words, if the feedback voltage FB is continuously higher than the second threshold voltage Vref2for the specified period of time Tdelay, the load condition detecting circuit7determines detection of increase in the load Po and reset the flip-flop7a. The reset of the flip-flop7a, through the delay circuit7d, sets the flip-flop7e, and an operation permission signal EN is delivered.

FIG. 2shows operational waveforms of the switching power supply1of the invention comprising the load condition detecting circuit7having the construction described above. When the load Po of the DC-DC converter3becomes light and correspondingly the feedback voltage decreases below the first threshold voltage Vref1, the flip-flop7ais set by the output of the comparator7b, a light load detecting circuit. The setting of the flip-flop7aturns OFF the switching element S in the delay circuit7dand the capacitor Ct is charged by the constant current source It in a rate corresponding to the capacitance thereof and the magnitude of the constant current. After a specified period of time Td-off when the charged voltage Vd of the capacitor Ct exceeds a second reference voltage Vth2, the flip-flop7eis reset to turn the operation permission signal EN to an L level. Thus, the operation of the power factor correction converter2is suspended.

After the stop of operation of the power factor correction converter2, the output voltage Vb of the power factor correction converter2gradually decreases and then, settles to a voltage corresponding to the AC voltage Vac supplied by the commercial power supply5. The output voltage Vb of the power factor correction converter2varies periodically with a period of rectification of the AC voltage Vac and with an amplitude determined by the magnitude of the load Po and the capacitance of the output capacitor C2. As described above, the peak voltage Vb-max of the output voltage Vb depends on the AC voltage Vac and the bottom voltage Vb-min thereof depends on the magnitude of the load Po. In embodiments of the invention, the peak voltage Vb-max of the output voltage Vb is detected and, based on this peak voltage Vb-max, the second threshold voltage Vref2is set as described above.

When the load Po grows heavier in a suspended state of operation of the power factor correction converter2, the feedback voltage FB in the DC-DC converter3rises due to the increase in the load Po. When the feedback voltage FB exceeds the second threshold voltage Vref2, which is set based on the maximum value of the output voltage Vb, the peak voltage Vb-max, as described earlier, the output of the comparator7c, a middle load detecting circuit, turns to an H level. After this H level of the output of the comparator7chas continued for a specified period of time Tdelay that is determined by the delay circuit7i, the output of the delay circuit7iresets the flip-flop7a.

If the feedback voltage FB exceeds the second threshold voltage Vref2only for a period of time shorter than the specified period of time Tdelay that is determined by the delay circuit7i, the capacitor Ct2in the delay circuit7iis discharged at the moment the output of the comparator7creturns to an L level. Thus, no reset signal is delivered from the delay circuit7ito the flip-flop7a. Therefore, even though the feedback voltage FB temporality exceeds the second threshold voltage Vref2, the flip-flop7ais not reset except that this situation lasts for the period of time Tdelay.

When the flip-flop7ais reset through the delay circuit7ithat functions as described above, the capacitor Ct in the delay circuit7dstarts to discharge the charges accumulated thereon. After a period of time Td-on when the charged voltage Vd of the capacitor Ct decreases below the first reference voltage Vth1caused by the discharge of the capacitor Ct, the flip-flop7eis set to turn the operation permission signal EN to an H level. As a result, the power factor correction converter2is permitted to operate and resumes operation thereof.

When the feedback voltage FB exceeds the third threshold voltage Vref3, the comparator7hdetects this event as a rapid increase in the load Po or transition to a heavy load condition and forcedly resets the flip-flop7a. The feedback voltage FB necessarily exceeds the second threshold voltage Vref2. The above described process is illustrated by the waveforms inFIG. 3.

As described above, on detection by the comparator7cthat the feedback voltage FB has exceeded the second threshold voltage Vref2, the flip-flop7ais reset after a specified delay time Tdelay through the delay circuit7i. Thus, a certain period of time, the delay time Tdelay, is needed until the reset of the flip-flop7aafter detection of the feedback voltage FB over the second threshold voltage Vref2. In this respect, when the comparator7hdetects that the feedback voltage FB has exceeded the third threshold voltage Vref3and determines detection of rapid increase in the load Po, the flip-flop7ais immediately set without passing the specified period time Tdelay. Thus, upon determination of detection of a heavy load condition by the comparator7h, the operation permission signal EN is rapidly delivered to resume operation of the power factor correction converter2. Therefore, embodiments of the invention can prevent the undesirable situation in which resume of operation of the power factor correction converter2is delayed and consequently unstable operation of the DC-DC converter3results.

As described above, the load condition detecting circuit7as constructed above sets the second threshold voltage Vref2for the comparator7c, which is a middle load detecting circuit, and the third threshold voltage Vref3for the comparator7h, which is a heavy load detecting circuit, based on the peak voltage Vb-max of the output voltage Vb of the power factor correction converter2. Therefore, even under a condition of dropped AC voltage Vac, the load condition detecting circuit7ensures detection of the increase in the feedback voltage FB caused only by increase in the load Po.

Even if the feedback voltage FB in the DC-DC converter3would rise due to the decrease of the output voltage Vb of the power factor correction converter2corresponding to the decrease in the AC voltage Vac, the erroneous detection should not occur that the feedback voltage rise due to the drop of the AC voltage Vac is recognized as indication of increase in the load Po, because the second and third threshold voltages Vref2and Vref3for the feedback voltage FB are set at high values corresponding to the decrease of the peak voltage Vb-max of the output voltage Vb.

Thus, even when the AC voltage Vac drops, the load condition detecting circuit7catches certainly the variation of the feedback voltage FB that is caused by variation of the load Po and in particular detects the increase in the load Po during a suspended state of the power factor correction converter2without failure. In the event of abrupt increase in the load Po, the flip-flop7ais forcedly set without waiting the specified delay time Tdelay and the operation permission signal EN is immediately delivered to resume operation of the power factor correction converter2. Therefore, generation of power loss is prevented in the power factor correction converter2, enhancing the overall conversion efficiency of embodiments of the switching power supply1.

When the load Po has abruptly increased during the suspended period of operation of the power factor correction converter2, an operation permission signal EN is immediately delivered according to the detection of increase in the load Po by the comparator7h, which is a heavy load detecting circuit, prior to delivery of an operation permission signal EN corresponding to the detection of increase in the load Po by the comparator7c, which is a medium load detecting circuit. Therefore, any trouble is avoided that causes unstable operation of the DC-DC converter3due to delay of resume of operation of the power factor correction converter2.

A load condition detecting circuit can also be constructed as shown inFIG. 4in which the delay circuit7dfor delaying the output of the flip-flop7ainFIG. 1is moved to the previous stage of the flip-flop7aand the operation permission signal EN is obtained directly from the flip-flop7a. In this construction, a delay circuit7mis provided to delay the output of the comparator7hfor the specified period of time Td-on, and the delay circuit7dfor delaying the output of the comparator7bsets the specified period of time Td-off. A delay circuit7ifor delaying the output of the comparator7csets a period of time (Tdelay+Td-on) that is the sum of the specified period of time Td-on and the previously mentioned period of time Tdelay. The thus constructed load condition detecting circuit ofFIG. 4operates similarly to the load condition detecting circuit7ofFIG. 1.

The load condition detecting circuit of the embodiment described thus far determined increase in the load Po by detecting variation of the feedback voltage FB of the DC-DC converter3. With the variation of the load Po, a period of time Tonoff of ON/OFF driving period of the switching element Q2in the DC-DC converter3also varies. Therefore, the increase in the load Po during a suspended period of the power factor correction converter2can be determined according to the period of time Tonoff of the ON/OFF driving period.

In this controlling mode, a periodical voltage Vsw is generated in proportion to the period of time Tonoff of the ON/OFF driving period of the switching element Q2. The second and third threshold voltages Vref2and Vref3for this periodical voltage Vsw are set based on the peak voltage Vb-max. Consequently, these second and third threshold voltages Vref2and Vref3also vary with variation of the DC voltage Vb like in the previous embodiment and are set at high values corresponding to the increase in the periodical voltage Vsw due to decrease in the DC voltage Vb.

The period of time Tonoff of ON/OFF driving period means the period of time from a turning ON moment of the switching element Q2to the first bottom moment in the Vds waveform of the switching element Q2. In the case of the DC-DC converter3of a quasi-resonance converter, bottom skipping control is conducted in order to restrain the upper limit of the switching frequency under a light load condition. In the bottom skip control, the switching element Q2is turned ON after detecting certain times of bottoms of the drain voltage that exhibits resonant oscillation after turning OFF of the switching element Q2. The period of time Tonoff includes the additional time resulted from the bottom skip control.

FIG. 5shows a schematic construction of a load condition detecting circuit7that detects variation of the load Po based on the periodic voltage Vsw. The comparator7binFIG. 5compares the periodic voltage Vsw with the first threshold voltage Vref1and determines a light load condition to suspend operation of the power factor correction converter2. In the suspended state of the power factor correction converter2, the comparator7ccompares the periodic voltage Vsw with the second threshold voltage Vref2and the comparator7hcompares the periodic voltage Vsw with the third threshold voltage Vref3to determines detection of increase in the load Po and deliver an operation permission signal EN to permit operation of the power factor correction converter2.

The load condition detecting circuit7ofFIG. 5comprises AND circuits7o,7p, and7qthat receive the outputs of the comparators7b,7c, and7hcomposing a light load detecting circuit, a middle load detecting circuit, and a heavy load detecting circuit, respectively, and are gate-controlled with bottom control signals Bot-a, Bot-b, and Bot-c, which are described afterwards. The outputs of the AND circuits7o,7p, and7qare delivered to the delay circuits7d,7i, and7mthrough OR circuits7r,7s, and7t. The delay circuits7d,7i, and7malso receive through the OR circuits7r,7s, and7tbottom control signals Bot-d, Bot-e, and Bot-f that are related to the bottom control signals Bot-a, Bot-b, and Bot-c, respectively.

In a quasi-resonance converter, as described previously, the bottom skip control is conducted in order to restrict the minimum value of the ON/OFF period of the switching element Q2in a light load condition. In the bottom skip control, the number of bottoms in the oscillating drain voltage is counted, the drain voltage oscillating associated with oscillating current after turning OFF of the switching element Q2. The switching element Q2is turned ON after the detected number of bottoms reaches a predetermined value under a light load condition. The bottom control signals Bot-a through Bot-f are control signals used in the bottom skip control and become an H level at a predetermined bottom skip number.

The number of bottom skips is set, for example, at zero or one for a heavy load condition, at two or three for a medium load condition, and at four to ten for a light load condition. The number of bottom skips of zero means that the switching element Q2is turned ON detecting the first bottom after turning OFF of the switching element Q2. The number of bottom skips of five means that the switching element Q2is turned ON detecting the sixth bottom after skipping five bottoms since turning OFF of the switching element Q2.

The AND circuit7obecomes active when the DC-DC converter3is in a middle load condition and such a bottom control signal Bot-a is given that becomes an H level at the number of bottom skips of four, for example, delivering a signal that is detected by the comparator7band indicating a light load condition. Consequently, the AND circuit7operforms to set the flip-flop7awhen the load Po transitions from a middle load condition to a light load condition.

The OR circuit7rreceives a bottom control signal Bot-d related to the bottom control signal Bot-a. Specifically, the bottom control signal Bot-d is at an H level for the number of skips of from five to ten. When a light load condition of the load Po is determined by the bottom control signal Bot-d, the flip-flop7ais forcedly set irrespective of detection of the transition from a middle load condition to a light load condition by the comparator7b.

The AND circuit7pbecomes active when the DC-DC converter3is in a light load condition and such a bottom control signal Bot-b is given that becomes an H level at the number of skips of three, for example. Consequently, the AND circuit7ppasses the signal indicating a middle load condition from the comparator7cto the OR circuit7s. In other words, the AND circuit7pperforms to set the flip-flop7awhen the load Po transitions from a light load condition to a middle load condition.

The OR circuit7sreceives a bottom control signal Bot-e related to the bottom control signal Bot-b. Specifically, the bottom control signal Bot-e is set at an H level for the number of skips of two. When a middle load condition of the load Po is determined by the bottom control signal Bot-e, the flip-flop7ais forcedly reset irrespective of detection of the transition from a light load condition to a middle load condition by the comparator7c.

The AND circuit7qbecomes active when the DC-DC converter3is in a light load condition and such a bottom control signal Bot-c is given that becomes an H level at the number of skips of one, for example. Consequently, the AND circuit7qpasses the signal indicating a heavy load condition from the comparator7hto the OR circuit7t. In other words, the AND circuit7qperforms to set the flip-flop7awhen the load Po transitions from a light load condition to a heavy load condition.

The OR circuit7treceives a bottom control signal Bot-f related to the bottom control signal Bot-c. Specifically, the bottom control signal Bot-f is set at an H level for the number of skips of zero or one. When a heavy load condition of the load Po is determined by the bottom control signal Bot-f, the flip-flop7ais forcedly set irrespective of detection of the transition from a light load condition to a heavy load condition by the comparator7h.

The load condition detecting circuit7described above with reference toFIG. 5compares the periodic voltage Vsw to determine increase in the load Po using the second threshold voltage Vref2that is set based on the peak voltage Vb-max of the output voltage Vb of the power factor correction converter2. The load condition detecting circuit7ofFIG. 5also determines the load condition of the DC-DC converter3that is a quasi-resonance converter utilizing the bottom control signals Bot-a through Bot-f, which are employed for controlling the turn ON timing of the switching element Q2in the quasi-resonance converter. The load condition detecting circuit7controls delivery of the operation permission signal EN according to the determination of the load condition, thereby ON/OFF controlling the operation of the power factor correction converter2.

The load condition detecting circuit7having the construction described above consequently does not erroneously determine increase in the load Po observing a rise in the periodic voltage Vsw proportional to the period of time Tonoff of ON/OFF driving of the switching element Q2due to drop of the AC voltage Vac and assures detection of the increase in the Vsw caused by the variation of the load Po. Thus, the load condition detecting circuit7catches the variation of the periodic voltage Vsw caused by the variation of the load Po and ensures detection of the increase in the load Po in the suspended state of the power factor correction converter2. Moreover, since the bottom control signals Bot-a through Bot-f are also used for detecting the variation of the load Po, operation of the power factor correction converter2is controlled appropriately with high reliability.

Embodiments of the switching power supply1provided with the load condition detecting circuit7suspends operation of the power factor correction converter2in a light load condition and, when the load Po increases during the suspended period of the power factor correction converter2, the load condition detecting circuit7resumes operation of the power factor correction converter2. Operation of the power factor correction converter2is appropriately controlled corresponding to the load condition even when the AC voltage Vac is dropped. Therefore, conversion efficiency of the switching power supply1is raised satisfactorily.

FIG. 6shows a relationship between the load Po and the period of time Tonoff of ON/OFF driving period of the switching element Q2varying with variation of the magnitude of the load Po of the DC-DC converter3that generates a specified DC output voltage Vo by switching the output voltage Vb of the power factor correction converter2in the switching power supply1having a power factor correction converter2that delivers an output voltage Vb of 250 Vdc from an input of AC voltage of 90 Vac.

The solid line inFIG. 6shows a characteristic of the DC-DC converter3that is given an output voltage Vb of DC voltage 250 Vdc from the power factor correction converter2in an operating state of the power factor correction converter2. The chain line shows a characteristic of the DC-DC converter3that is given an output voltage Vb of the power factor correction converter2, the voltage Vb being a DC voltage of 127 Vdc obtained by rectifying and smoothing the AC voltage of 90 Vac in a suspended state of the power factor correction converter2.

The load condition detecting circuit7examines the period of time Tonoff of the ON/OFF driving period of the switching element Q2and determines the load condition. According to the determination result, the operation of the power factor correction converter2is suspended and resumed.FIG. 6shows enough width of power hysteresis between an operating state and a suspended state of the power factor correction converter2even in a low AC voltage of 90 Vac. Thus, the power factor correction converter2can be operated under stable control.

More specifically, when the period of time Tonoff of the ON/OFF driving period of the switching element Q2decreases to for example 7.2 μs or shorter with decrease in the load Po in an operating state of the power factor correction converter2, the operation of the power factor correction converter2is suspended. When the period of time Tonoff of the ON/OFF driving period of the switching element Q2increases to for example 8.7 μs or longer with increase in the load Po in a suspended state of the power factor correction converter2, the operation of the power factor correction converter2is resumed. This control of operation of the power factor correction converter2ensures an enough width of the power hysteresis even at a low AC voltage of 90 Vac. Therefore, the power factor correction converter2can be operated under stable ON/OFF control.

As described above concerning the load condition detecting circuit7of a switching power supply according to an embodiment of the present invention, attention is directed in the invention to the fact that the maximum value of the output voltage, the peak voltage Vb-max, of the power factor correction converter2varies corresponding to the input AC voltage Vac in a suspended state of the power factor correction converter2. The second threshold voltage Vref2, which is a threshold value for permitting operation of the power factor correction converter2, is set based on the peak voltage Vb-max, the maximum value of the output voltage Vb.

Consequently, even when the voltage Vac of the AC power supplied to the switching power supply1drops and the output voltage Vb of the power factor correction converter2decreases with this drop of the AC voltage Vac, the switching power supply of the invention ensures detection of the load Po on the DC-DC converter3. Thus, increase in the load Po is detected certainly in a suspended period of the power factor correction converter2to resume operation of the power factor correction converter2. Therefore, the switching power supply1is operated with high efficiency restraining the power loss in the power factor correction converter2to a minimum.

Embodiments of t invention are not limited to the embodiments described thus far. For example, the delay time Tdelay set in the delay circuit7ican be sufficiently set at any period of time not shorter than the half period of the AC voltage Vac. Also the second threshold voltage Vref2that is set corresponding to the varying peak voltage Vb-max of the output voltage Vb can be sufficiently set corresponding to the allowable minimum value of the AC voltage Vac or the bottom voltage Vb-min of the varying output voltage Vb with drop of the AC voltage Vac.

For the DC-DC converter3, a converter other than the quasi-resonance converter, for example, a multi-oscillated current resonant dc-dc converter can be employed similarly in an embodiment of the present invention. Embodiments of the invention can be carried out in various other modifications within spirit and scope of the invention.

Examples of specific embodiments are illustrated in the accompanying drawings. While the invention is described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the above description, specific details are set forth in order to provide a thorough understanding of embodiments of the invention. Embodiments of the invention may be practiced without some or all of these specific details. Further, portions of different embodiments and/or drawings can be combined, as would be understood by one of skill in the art.

This application is based on, and claims priority to, Japanese Patent Application No. 2012-157049, filed on Jul. 13, 2012, contents of which are incorporated herein by reference.