Multi-stack chip size packaging method

In multi-stack chip size packaging a plurality chips, a first chip is electrically interconnected on a top surface of a substrate using a bump. Next, an epoxy is coated on the first chip and is stacked a second chip thereon, wherein the second chip is electrically interconnected to the substrate through an inner lead bonding. A potting solution is coated on the substrate and the second chip and installed thereon a heat spreader and then cured. An encapsulation resin is coated on a bottom surface of the substrate and electrically interconnected a third chip to the bottom surface of the substrate through a bump and an inner lead bump.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to Korean application No. 10-2002-0086406, filed Dec. 30, 2002, the contents of which is incorporated herein in its entirety by reference.

FIELD OF THE INVENTION

The present invention relates to a method of multi-a stack chip size package; and, more particularly, to a method for multi-stack chip size packaging a plurality of chips at both a top and a bottom surface of a substrate to thereby reduce a thickness of the multi-stack chip size package and to enhance a packaging efficiency.

BACKGROUND OF THE INVENTION

FIG. 1illustrates a cross sectional view of a conventional multi-stack chip size package (CSP).

Referring toFIG. 1, a first chip (or die)20is adhered on a substrate10, e.g., a printed circuit board, with an epoxy and a second chip (or die)30is stacked thereon with the epoxy. Bonding pads on the first and the second chip20and30are electrically connected with terminals on the printed circuit board10by conductive wires50. A resin, e.g., an epoxy molding compound (EMC)40is used to mold the first and the second chip20and30, and the electrical connection between the whole package and an another printed circuit board can be achieved by ball grid array using solder balls60.

The drawback of the conventional multi-stack chip size packaged device is that a thickness thereof is to be enlarged, e.g., about 1.4 mm, because of the molding material of the multi-stack CSP, i.e., the resin, to thereby require a long conductive wire50, i.e., a long signal transmission path. Therefore, the characteristics of the multi-stack chip size packaged device are deteriorated and the applicability thereof is also reduced. In addition, heat dissipation thereof is not effective.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide a method for by multi-stack chip size packaging a plurality of chips at both a top and a bottom surface of a substrate to reduce the thickness of the multi-stack chip size package to enhance a packaging efficiency.

In accordance with the present invention, there is provided a method for multi-stack chip size packaging a plurality chips, which including the steps of: electrically interconnecting a first chip into a top surface of a substrate using a bump; stacking a second chip on the first chip, wherein the second chip is electrically interconnected to the substrate through an inner lead bonding; coating an insulating potting solution on the substrate and the second chip and installing thereon a heat spreader and then curing the potting solution; and coating an encapsulation resin on a bottom surface of the substrate and electrically interconnecting a third chip to the bottom surface of the substrate through a bump and a inner lead bump.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A preferred embodiment in accordance with the present invention will now be described with reference to the accompanying drawings.

FIG. 2illustrates a cross sectional view of a multi-stack chip size packaged (CSP) device in accordance with a preferred embodiment of the present invention.FIGS. 3A and 3Bdepict a top and a bottom view of the multi-stack chip sized packaged device in accordance with the preferred embodiment of the present invention.

Referring toFIGS. 2 to 3B, a first chip120, e.g., a flip chip, is electrically interconnected to a top surface of a rigid or flexible substrate10, e.g., a printed circuit board (PCB), through a bump180therebetween. Next, an epoxy is coated on the first chip120and a second chip130is stacked thereon. The second chip130is electrically interconnected to the PCB through an inner lead boding (ILB) scheme170. And then, an insulating potting solution is coated on the second chip130and cured. A heat spreader160is mounted thereon for dissipating heat generated in the chips120and130.

Next, a third chip190, e.g., another flip chip, is electrically interconnected to a bottom surface of the PCB10using a bump80therebetween and an ILB70and then encapsulated by an encapsulation resin100. Finally, a ball grid array S1using solder balls is mounted on the bottom surface of the PCB10.

Therefore, the multi-chip chip size packaged device in accordance with the preferred embodiment of the present invention use the top and the bottom surface of the PCB to thereby enhance a packaging efficiency. Also, by reducing the thickness of the device, e.g., less than 1.0 mm, that is to say, an electrical distance between the chips and the PCB, operational characteristics of the device can be enhanced.