Sideband information over host interface considering link states

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create one or more thresholds for sending sideband information to a host device, determine that a link state is in a state other than L0, retain sideband information until the one or more thresholds is reached, and send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state. The one or more thresholds correspond to a link state between the host device and the data storage device. The thresholds are either based on an amount of sideband information retained, a time of retaining sideband information, or a combination of the amount of sideband information retained and the time of retaining sideband information. The sideband information is retained and sent in a first-in first-out order.

BACKGROUND OF THE DISCLOSURE

Field of the Disclosure

Embodiments of the present disclosure generally relate to data storage devices, such as solid state drives (SSDs), and, more specifically, sending sideband information with respect to link states.

Description of the Related Art

SSDs are connected to their host device through a PCIe interface. The PCIe interface is used to satisfy a required protocol by meeting a given performance requirement. Sideband information, which may not be related directly to host device/data storage device communication, is transferred over the same PCIe interface link. Sideband information may include host memory buffer (HMB) data, debug information, and the like.

Because sideband information is sent on the same link as the host interface (i.e., the PCIe interface), power and link inefficiency may occur since the host device utilizes the same PCIe interface for I/O transfers to the data storage device. Furthermore, when the link is in an inactive state due to power saving requirements, sending sideband information of the link may cause additional link state switches. The additional link state switches may result in a significant power increase since the link state switch causes the system to wake up from the inactive state. Because the system is waking up to only send sideband information, power may be not optimally used.

Therefore, there is a need in the art for a sideband transmission method that takes into account the link state of the interface in order to avoid increasing power consumption.

SUMMARY OF THE DISCLOSURE

The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), and, more specifically, sending sideband information with respect to link states. A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create one or more thresholds for sending sideband information to a host device, determine that a link state is in a state other than L0, retain sideband information until the one or more thresholds is reached, and send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state. The one or more thresholds correspond to a link state between the host device and the data storage device. The thresholds are either based on an amount of sideband information retained, a time of retaining sideband information, or a combination of the amount of sideband information retained and the time of retaining sideband information. The sideband information is retained and sent in a first-in first-out order.

In one embodiment, a data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create one or more thresholds for sending sideband information to a host device, wherein the one or more thresholds correspond to a link state between the host device and the data storage device, determine that link state is in a state other than L0, retain the sideband information until the one or more thresholds is reached, and send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state.

In another embodiment, a data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to activate a timer when first sideband data is delivered to a buffer, accumulate additional sideband data in the buffer, deliver the accumulated sideband data to a host device upon reaching a timing threshold of a plurality of timing thresholds.

In another embodiment, a data storage device includes memory means and a controller coupled to the memory means. The controller is configured to configure one or more thresholds, wherein each of the one or more thresholds corresponds with a link state of a plurality of link states, accumulate sideband information in a buffer, wake up a link between a host device and the data storage device, and send the accumulated sideband information to the host device.

DETAILED DESCRIPTION

The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), and, more specifically, sending sideband information with respect to link states. A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create one or more thresholds for sending sideband information to a host device, determine that a link state is in a state other than L0, retain sideband information until the one or more thresholds is reached, and send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state. The one or more thresholds correspond to a link state between the host device and the data storage device. The thresholds are either based on an amount of sideband information retained, a time of retaining sideband information, or a combination of the amount of sideband information retained and the time of retaining sideband information. The sideband information is retained and sent in a first-in first-out order.

FIG.1is a schematic block diagram illustrating a storage system100in which a host device104is in communication with a data storage device106, according to certain embodiments. For instance, the host device104may utilize a non-volatile memory (NVM)110included in data storage device106to store and retrieve data. The host device104comprises a host DRAM138. In some examples, the storage system100may include a plurality of storage devices, such as the data storage device106, which may operate as a storage array. For instance, the storage system100may include a plurality of data storage devices106configured as a redundant array of inexpensive/independent disks (RAID) that collectively function as a mass storage device for the host device104.

The data storage device106includes a controller108, NVM110, a power supply111, volatile memory112, the interface114, and a write buffer116.

In some examples, the data storage device106may include additional components not shown inFIG.1for the sake of clarity. For example, the data storage device106may include a printed circuit board (PCB) to which components of the data storage device106are mechanically attached and which includes electrically conductive traces that electrically interconnect components of the data storage device106or the like. In some examples, the physical dimensions and connector configurations of the data storage device106may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5” data storage device (e.g., an HDD or SSD), 2.5” data storage device, 1.8” data storage device, peripheral component interconnect (PCI), PCI-extended (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI, etc.). In some examples, the data storage device106may be directly coupled (e.g., directly soldered or plugged into a connector) to a motherboard of the host device104.

Interface114may include one or both of a data bus for exchanging data with the host device104and a control bus for exchanging commands with the host device104. Interface114may operate in accordance with any suitable protocol. For example, the interface114may operate in accordance with one or more of the following protocols: advanced technology attachment (ATA) (e.g., serial-ATA (SATA) and parallel-ATA (PATA)), Fibre Channel Protocol (FCP), small computer system interface (SCSI), serially attached SCSI (SAS), PCI, and PCIe, non-volatile memory express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), or the like. Interface114(e.g., the data bus, the control bus, or both) is electrically connected to the controller108, providing an electrical connection between the host device104and the controller108, allowing data to be exchanged between the host device104and the controller108. In some examples, the electrical connection of interface114may also permit the data storage device106to receive power from the host device104. For example, as illustrated inFIG.1, the power supply111may receive power from the host device104via interface114.

The NVM110may include a plurality of memory devices or memory units. NVM110may be configured to store and/or retrieve data. For instance, a memory unit of NVM110may receive data and a message from controller108that instructs the memory unit to store the data. Similarly, the memory unit may receive a message from controller108that instructs the memory unit to retrieve data. In some examples, each of the memory units may be referred to as a die. In some examples, the NVM110may include a plurality of dies (i.e., a plurality of memory units). In some examples, each memory unit may be configured to store relatively large amounts of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

In some examples, each memory unit may include any type of non-volatile memory devices, such as flash memory devices, phase-change memory (PCM) devices, resistive random-access memory (ReRAM) devices, magneto-resistive random-access memory (MRAM) devices, ferroelectric random-access memory (F-RAM), holographic memory devices, and any other type of non-volatile memory devices.

The NVM110may comprise a plurality of flash memory devices or memory units. NVM Flash memory devices may include NAND or NOR-based flash memory devices and may store data based on a charge contained in a floating gate of a transistor for each flash memory cell. In NVM flash memory devices, the flash memory device may be divided into a plurality of dies, where each die of the plurality of dies includes a plurality of physical or logical blocks, which may be further divided into a plurality of pages. Each block of the plurality of blocks within a particular memory device may include a plurality of NVM cells. Rows of NVM cells may be electrically connected using a word line to define a page of a plurality of pages. Respective cells in each of the plurality of pages may be electrically connected to respective bit lines. Furthermore, NVM flash memory devices may be 2D or 3D devices and may be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller108may write data to and read data from NVM flash memory devices at the page level and erase data from NVM flash memory devices at the block level.

The volatile memory112may be used by controller108to store information. Volatile memory112may include one or more volatile memory devices. In some examples, controller108may use volatile memory112as a cache. For instance, controller108may store cached information in volatile memory112until the cached information is written to the NVM110. As illustrated inFIG.1, volatile memory112may consume power received from the power supply111. Examples of volatile memory112include, but are not limited to, random-access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, and the like)).

Controller108may manage one or more operations of the data storage device106. For instance, controller108may manage the reading of data from and/or the writing of data to the NVM110. In some embodiments, when the data storage device106receives a write command from the host device104, the controller108may initiate a data storage command to store data to the NVM110and monitor the progress of the data storage command. Controller108may determine at least one operational characteristic of the storage system100and store at least one operational characteristic in the NVM110. In some embodiments, when the data storage device106receives a write command from the host device104, the controller108temporarily stores the data associated with the write command in the internal memory or write buffer116before sending the data to the NVM110.

FIG.2is an illustration of a link state flow diagram200, according to certain embodiments. Aspects of the storage system100may be referenced in the description herein for exemplary purposes. The data storage device106includes several link states. For example, the data storage device106may have the following 5 link states: L0, L0s, L1, L2, and L3, where L1includes a L1.1sub-state and a L1.2sub-state. Each of the link states are associated with a distinct operation of the data storage device106. Link states L0, L0s, and L1are considered operational link states and utilize a first range of power, whereas link states L2and L3are considered non-operational link states, utilizing a second range of power, where the first range of power is greater than the second range of power.

An operational link state refers to the ability of the host device104to communicate with the NVM110of the data storage device106. A non-operational link state refers to the inability of the host device104to communicate with the NVM110of the data storage device106due to a shut down or disconnection of a link between the host device104and the controller108. The listed non-operational link states are not intended to be limiting and may include other link states, such as the L1.1and L1.2link states. Furthermore, it is contemplated that more or less link states than the number of link states shown in the link state flow diagram200may be available and more or less low power link states may be applicable to the embodiments described herein.

Link states are numbered sequentially, where higher numbers represent lower power requirements due to a greater number of offline circuits and corresponding higher exit latencies. Furthermore, each link state has an associated power requirement and an exit latency. L0and L0smay require 4.5 W with the lowest exit latency. L1may require less power than L0, such as 3 W, and may have an exit latency equal to or higher than the exit latency of L0. L2may require less power than L1and may have an exit latency equal to or higher than the exit latency of L1. L3may require less power than L2and may have an exit latency equal to or higher than the exit latency of L2. The values for the link states and exit latencies are not intended to be limiting, but to provide an example of possible embodiments.

L0is referred to as a fully operational state, where I/O commands are enabled, and the device may generate interrupts. L0is a link state where the link is operating normally. Interrupts are an automatic transfer of firmware execution due to a system timer or a user command. Link states L0sand L1are also operational states; however, L0sand L1may have a lower functionality than that of L0. For example, L0shas a similar power requirement as that of the L0, but only allows for a serial link in one direction. In the L0slink state, data may be transferred in one direction, but not the other. Thus, when a first device is coupled to a second device through a link, the first device may idle a transmitter of the first device independently and separately of the second device idling a transmitter of the second device, and/or vice-versa.

However, L1allows for a bidirectional serial link and allows for a greater reduction in the power requirement, but has a higher exit latency than that of L0and L0s. In the L1link state, no data is being transferred so key portions of the PCIe transceiver logic may be turned off. Link states L2and L3are non-operational link states have a power requirement less than that of the operational link states. The difference between the L2link state and the L3link state is that power has not been yet removed from the L2link state. Furthermore, the memory devices of the NVM110that are not used are placed in a non-operational link state, L2and L3, to limit the idle power consumption to a minimal value.

In order for I/O commands to occur, the link, such as a data bus, between the host device104and the controller108is woken up and placed into the L0link state. The controller108changes the link state of the link between the host device104and the controller108from the operational link states, such as L0, L0s, or L1, to a different operational link state, such as L0, L0s, or L1, or to a non-operational link state, such as L2or L3, depending on the situation. However, in order for the link to be placed into L2or L3, the link will need to be in link state L2/L3ready, which is a pseudo-state to prepare the component for a loss in power and reference clock(s). The controller108allocates the appropriate amount of power to return all link states L0s, L1, L2, L3into link state L0when a full operational state is required. For example, to return to L0from L2or L3, the link transitions to a transient pseudo-state, LDn, before transitioning to L0. The LDn state may be a fundamental reset state, a hot reset state, or a link disable transmission state by the upstream component (e.g., the host device104).

The link state L1, in some embodiments, includes additional sub-states, L1.1and L1.2, where the link state L1may be referred to as L1.0. The L1sub-states (L1SS), L1.1and L1.2, may require more power for operation than L2and L3; however, the L1SS utilizes less power than the L1.0state. At an L1SS, the link remains operational and requires less power to return to a more operational state, such as L1.0or L0. Furthermore, the L1SS requires less time than the L2and/or the L3link states to return to a full active link state L0.

FIG.3is an illustration of a link state timing diagram300, according to certain embodiments. Aspects of the storage system100may be referenced in the description herein for exemplary purposes. The link state timing diagram300illustrates a scenario where the data storage device106posts sideband information, such as HMB data or debug messages, to the host device104without considering the link state. For example, if the link state is in an inactive state, the data storage device106wakes up the link, transmits the required sideband information, and returns to the inactive link state.

As shown in the link state timing diagram300, the link is transitioned to an inactive state at time A. At time B, the link is transitioned from the inactive state to an active state in order to send sideband information, where the sideband information is sent from time B to time B*. The transition from the inactive state to the active state at time B may be requested by the data storage device106in order to send the sideband information. At time C, the link returns to an inactive state. The time between time B*and time C may be a time to transition the link from the active state to the inactive state, where the power consumption is between a power consumption of the link in an inactive state and the link in an active state. A link in the active state consumes more power than a link in the inactive state.

From time C to time D, the link is in the inactive state. At time D, the link is transitioned from the inactive state to an active state in order to send sideband information, where the sideband information is sent from time D to time D*. At time E, the link returns to an inactive state. The time between time D*and time E may be a time to transition the link from the active state to the inactive state, where the power consumption is between a power consumption of the link in an inactive state and the link in an active state. In one example, the transition from an inactive state to an active state at time B and time D is not initiated by the host device104, but by the data storage device106. Because the link is woken up (e.g., transitioned from an inactive state to an active state) multiple times, where each time the link enters the active state to just send sideband information, a trailing power consumption (e.g., the time between time B*and C), power consumption of the data storage device106may be greater than optimal power consumption.

FIG.4is an illustration of a link state timing diagram400, according to certain embodiments. Aspects of the storage system100may be referenced in the description herein for exemplary purposes. The controller108, in this embodiment, considers the link status prior to triggering any transmissions of sideband information over the link. The controller108includes one or more thresholds for when the sideband information should be emptied or transferred to the host device104. The one or more thresholds may either be time based, capacity based, or a combination of time based and capacity based. When the link is in the inactive state, sideband information is aggregated or retained in a buffer of the controller108. The sideband information is stored in a first-in first-out (FIFO) mechanism, such that the sideband information is sent to the host device104in the order that the sideband information is received and stored in the buffer.

When sideband information is first stored in the buffer, a timer may be started to track how long the sideband information has been stored in the buffer. In one embodiment, the controller108may utilize multiple timers, each timing different sideband information. In another embodiment, the controller108may utilize a single timer to track when the buffer first stores sideband information. Furthermore, the controller108may determine how much sideband information has been stored in the buffer and whether the amount of sideband information has reached or exceeded a threshold of the one or more thresholds. For example, each threshold of the one or more thresholds may be associated with a link state.

From time A to time B, the link state is in an inactive state, where the controller108accumulates sideband information. At time B, a threshold of the one or more thresholds is reached or exceeded causing the controller108to wake up the link in order to transfer the sideband information. At time B*, the controller108has completed sending the sideband information to the host device104and the link returns to an inactive state at time C. Rather than having several small durations for entering and exiting the low power link states, the transactions are merged (i.e., the sideband data is aggregated) so that the data storage device triggers a single wake up (or in cases of an extended period of an inactive state, multiple wake ups) from the inactive state.

When the link is active (either by controller108request or host device104request), sideband information is posted by the controller108as a result of data accumulation or at time elapsed since storing sideband information. In other embodiments, the aggregation of data may be applied to a user data transfer. Thus, power saving may be achieved by avoiding several entry to or exit from low power link states in small durations.

FIG.5is a representational illustration of a first-in first-out (FIFO) pipe500, according to certain embodiments. The FIFO pipe500may be a representational embodiment of a FIFO buffer of a controller, such as the controller108ofFIG.1, configured to store sideband information. The FIFO pipe500has a first threshold502, a second threshold504, a third threshold506, and a fourth threshold508. The number of thresholds is not intended to be limiting, but to provide an example of a possible embodiment. More than or less than the number of thresholds shown is contemplated.

The plurality of thresholds502,504,506,508may be dynamically adjusted during the lifetime of a data storage device, such as the data storage device106ofFIG.1. The dynamic adjustment of one or more of the plurality of thresholds502,504,506,508may be based on a time that the data storage device106has been in use (including inactive time), an input/output parameter based on commands and data received from a host device, such as the host device104ofFIG.1, or transferred to the host device104, a health of one or more blocks of an NVM, such as the NVM110ofFIG.1, and the like. The health of the one or more blocks of the NVM110may be based on a program/erase cycle (PEC) count of one or more blocks, a bit error rate (BER) of one or more blocks, a failed bit count (FBC) of one or more blocks, a temperature variation of one or more blocks, and the like.

Each threshold of the plurality of thresholds corresponds with one or more link states. Table 1 below illustrates one example of a threshold to link state association.

Table 2 below illustrates another example of a threshold to link state association.

TABLE 2THRESHOLDLINK STATETHRESHOLD VALUETHR1 502L0tTHR2 504L0st*QTHR3 506L1t*RTHR4 508L1SS and L2t*S
t refers to a threshold of that sideband information has been stored in the FIFO pipe500. For example, when first sideband information is stored in the FIFO pipe500, the controller108initiates a timer that tracks the time that the first sideband information has been stored in the FIFO pipe500. When the time exceeds a corresponding threshold for the link state, the controller108wakes up the link and posts the sideband information to the host device104. Thus, ensuring that sideband information is not held for an extended period of time internally. In some examples, each link state has the same timing threshold. In other examples, a time duration each timing threshold subsequent time threshold is equal.

Furthermore, when a first link state consumes less power than a second link state, the first link state has a larger threshold value associated with the link state. The larger threshold value may be attributed to retaining more sideband information in order to avoid having to provide more power to wake up the link than a link state with a smaller threshold value. For example, the amount of power to wake up a link from a link state of L1to a link state of L0may be greater than the amount of power to wake up a link from a link state of L0sto a link state of L0. It is to be understood that the phrase “wake up” may refer to adjusting a link state from a lower powered link state to a higher powered link state. Therefore, referring back to Table 1, L is less than M and M is less than N, where L may be an integer value greater than 1. Likewise, referring back to Table 2, Q is less than R and R is less than S, where Q may be a value greater than 1.

It is to be understood that the one or more thresholds may be based on both a size of sideband information retained and a time of retaining sideband information.

Furthermore, sideband information is stored in the FIFO pipe500in order of receiving the sideband information. For example, if sideband information is received in the order of A, B, D, C, E, then the sideband information is stored in the FIFO pipe500in the order of A, B, D, C, E and sent to the host device104in the order of A, B, D, C, E.

FIG.6is a schematic block diagram illustrating a storage system600in which sideband information is sent from a controller606of a data storage device604to a host device602, according to certain embodiments. The data storage device604includes the controller606, which may be the controller108ofFIG.1, and an NVM628, which may be the NVM110ofFIG.1. It is to be understood that the data storage device604may include additional components not shown for simplification purposes.

The controller606includes a host interface module (HIM)608, a sideband information logic unit612, one or more processors626, a command scheduler, an encryption/decryption unit620, an encoder/decoder unit622, and a flash interface module (FIM)624. The HIM608includes one or more direct memory accesses (DMAs)610. The HIM608is configured to receive commands and data from the host device602, such as by fetching the commands and data from a submission queue of a host DRAM, such as the host DRAM138ofFIG.1. Likewise, the HIM608is configured to send data associated with the received commands back to the host device602and post completion messages for the completed commands to a completion queue of the host DRAM138. The one or more DMAs610may allow for access to RAM, such as DRAM or SRAM, or the NVM628without input from the one or more processors626. The one or more processors626provide instructions and processing (e.g., computational) power in order to execute commands and logic.

The sideband information logic unit612includes a sideband information FIFO buffer614, which may be the FIFO pipe500ofFIG.5, and a timer616. The command scheduler618schedules commands (e.g., read commands or write commands) to be executed by the FIM624on the NVM628. The encryption/decryption unit620may be separate units, such that the encryption unit and the decryption unit are a separate components in the controller606. The encryption unit of the encryption/decryption unit620may be configured to encrypt the data in order to provide for improved data security and reliability. Likewise, the decryption unit of the encryption/decryption unit620may decrypt the encrypted data, such that the data may be sent to and read by the host device602.

The encoder/decoder unit622may be separate units, such that the encoder unit and the decoder unit are separate components of the controller606. The encoder unit of the encoder/decoder unit622may be configured to encode the data, where encoding the data may include generating error correction code, parity data, low-density parity-check data for the data. Likewise, the decoder unit of the encoder/decoder unit622may be configured to decode the encoded data in order to determine and correct a number of bit flips or bit errors in the decoded data.

When the link between the host device602and the controller606enters a low power link state (i.e., a link state other than L0, in the current example), sideband information that would normally be sent or posted to the host device602in a size equal to the MPS is sent to the sideband information logic unit612. The sideband information is stored or accumulated in the sideband information FIFO buffer614, where the timer616starts a timer for when the sideband information is first stored or accumulated in the sideband information FIFO buffer614. The sideband information logic unit612, in conjunction with the one or more processors626, determines the link state of the link between the host device602and the controller606. Based on the link state, the sideband information logic unit612determines whether the time of the timer616or the size of sideband information retained equals or exceeds a corresponding threshold for the link state. The thresholds may be the thresholds exemplified in Table 1 and Table 2 above. When the threshold for a corresponding link state is reached or exceeded, the controller606wakes up the link between the controller606and the host device602and flushes the retained sideband information to the host device. In one embodiment, the sideband information flushed may be in a size equal to a multiple of the MPS. In another embodiment, the sideband information flushed is not in a size equal to a multiple of the MPS.

FIG.7is a flow diagram illustrating a method700of sending sideband information with respect to link state, according to certain embodiments. Aspects of the storage system600may be referenced for exemplary purposes. At block702, the controller606creates one or more sideband information thresholds for the sideband information FIFO buffer614. Each threshold of the one or more sideband information thresholds corresponds to one or more link states, where each threshold may be based on a sideband information aggregation size, a time since storing sideband information, or a factor based on a combination of the sideband information aggregation size and a time since storing sideband information. The one or more sideband information thresholds may be dynamically adjusted during the lifespan of the data storage device604.

At block704, a link between controller606and the host device602enters an inactive link state. It is to be understood that an inactive link state may refer to a link state that is not in an L0link state. At block706, a timer is started by the timer616. In one example, the timer may keep track of how long the link has been in an inactive link state. In another example, the timer may be started when sideband information is first accumulated or retained in the sideband information FIFO buffer614. The timer616may keep track of multiple timers. At block708, sideband information is accumulated or retained in the sideband information FIFO buffer614. For example, one timer may be started when sideband information is first stored in the sideband information FIFO buffer614. Another timer may be started at each MPS interval. A timer may be started each time sideband information is stored in the sideband information FIFO buffer614. At block710, the controller606determines the link state and a corresponding threshold of the one or more sideband information thresholds for the determined link state.

At block712, the controller606determines if the determined threshold for the link state of the link has been reached or exceeded. If the determined threshold has been reached or exceeded at block712, then the controller606wakes up the link at block714. At block716, the controller sends the accumulated sideband information from the sideband information FIFO buffer614to the host device602. For example, the sideband information may be sent in a size equal to a multiple of the MPS or in a size equal to the total stored sideband information, where a timer may be updated to keep track of any sideband information remaining in the sideband information FIFO buffer614.

However, if the threshold is not reached at712, then the controller606determines if there has been a change in the link state at block718. For example, the link state may be changed from a L1.0link state to a L1.2link state or from a L1.0link state to an L0link state. If the link state has not changed at block718, the controller606continues to accumulate sideband information at block720. However, if the link state has changed at block718, then the controller606determines if the link state is in an active state, such as in an L0link state, at block722. If the link state is still in an inactive state at block722, then the controller re-determines the link state and the corresponding threshold for the re-determined link state at block710. However, if the link state has changed to an active state at block722, then the sideband information may be sent to the host device602in a size equal to a multiple of the MPS or in a size not equal to a multiple of the MPS.

By aggregating and storing sideband information in a sideband information FIFO buffer while a link between a host device and a controller is not in an L0link state, extra switches between active and inactive link states may be avoided and power may be saved.

In one embodiment, a data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create one or more thresholds for sending sideband information to a host device, wherein the one or more thresholds correspond to a link state between the host device and the data storage device, determine that link state is in a state other than L0, retain the sideband information until the one or more thresholds is reached, and send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state.

An L0sstate is associated with a first threshold. The first threshold is greater than a maximum payload size (MPS). An L1state is associated with a second threshold. The second threshold is greater than the first threshold. An L2state is associated with a third threshold. The third threshold is greater than the second threshold. One or more L1substates are associated with the third threshold. The sideband information is retained and sent in a first-in first-out (FIFO) order. The sideband information is retained in a buffer. The one or more thresholds includes a timing threshold. The one or more thresholds further includes a plurality of retained sideband information thresholds.

In another embodiment, a data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to activate a timer when first sideband data is delivered to a buffer, accumulate additional sideband data in the buffer, deliver the accumulated sideband data to a host device upon reaching a timing threshold of a plurality of timing thresholds.

The timing threshold is dependent on a link state between the host device and the data storage device. An L0sstate is associated with a first timing threshold. An L1state is associated with a second timing threshold. The second timing threshold is greater than the first timing threshold. An L2state is associated with a third timing threshold. The third timing threshold is greater than the second timing threshold. One or more L1substates are associated with the third timing threshold. A difference in time between the first timing threshold, the second timing threshold, and the third timing threshold is equal. Each of the timing thresholds of the plurality of timing thresholds are equal. Each of the timing thresholds of the plurality of timing thresholds are adjusted dynamically.

In another embodiment, a data storage device includes memory means and a controller coupled to the memory means. The controller is configured to configure one or more thresholds, wherein each of the one or more thresholds corresponds with a link state of a plurality of link states, accumulate sideband information in a buffer, wake up a link between a host device and the data storage device, and send the accumulated sideband information to the host device.

Each link state has a corresponding threshold of a plurality of thresholds. A first threshold is less than a second threshold. The first threshold and the second threshold are in a MPS granularity. The first threshold is greater than a first MPS granularity. The first MPS granularity is equal to a MPS. The corresponding threshold is independent of a timing threshold. A first timing threshold for a first link state of the plurality of link states is independent of a second timing threshold for a second link state.