SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

A method includes forming a 2-D semiconductor material layer over a substrate; forming source/drain contacts over source/drain regions of the 2-D semiconductor material layer; and forming a gate structure over a channel region of the 2-D semiconductor material layer. Forming the source/drain contacts includes performing a first deposition process to deposit a first metal layer over the 2-D semiconductor material layer; and after the first deposition process is completed, performing a second deposition process to deposit a second metal layer over the first metal layer, in which the second metal layer has a higher melting point than the first metal layer.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. However, since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.

DETAILED DESCRIPTION

FIGS.1A to8illustrate a method in various stages of fabricating a semiconductor device in accordance with some embodiments of the present disclosure.

Reference is made toFIG.1A. Shown there is a substrate100. In some embodiments, the substrate100may function to provide mechanical and/or structure support for features or structures that are formed in the subsequent steps. These features or structures may be parts or portions of a semiconductor device (e.g. a transistor or a memory device) that may be formed on or over the substrate100.

Generally, the substrate100illustrated inFIG.1Amay include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. An SOI substrate includes an insulator layer below a thin semiconductor layer that is the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include the crystalline semiconductor material silicon, but may include one or more other semiconductor materials such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs and the like), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, and the like) or combinations thereof. The semiconductor materials may be doped or undoped. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates. In some other embodiments, the substrate100may include sapphire (e.g. crystalline Al2O3), e.g. a large grain or a single crystalline layer of sapphire or a coating of sapphire. As another example, the substrate100may be a sapphire substrate, e.g. a transparent sapphire substrate comprising, as an example, α-Al2O3. Other elementary semiconductors like germanium may also be used for substrate100.

A dielectric layer105is formed over the substrate100. In some embodiments, the dielectric layer105may be made of silicon oxide, silicon oxynitride, aluminum oxide, a combination thereof, or another suitable material. In some embodiments, the dielectric layer105includes a high dielectric constant material (high-k material), in accordance with some embodiments. The high-k material includes metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, aluminum oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, another suitable material, or a combination thereof, in accordance with some embodiments. The high-k material includes hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or a combination thereof, in accordance with some embodiments. In some embodiments, the dielectric layer105can be formed by suitable deposition process, such as CVD, PVD, ALD, or the like. In some embodiments, the dielectric layer105has a thickness in a range from about 10 nm to about 100 nm.

A 2-D material layer110is formed over the substrate100. In some embodiments, the 2-D material layer110is in direct contact with top surface of the dielectric layer105. As used herein, consistent with the accepted definition within solid state material art, a “2-D material” may refer to a crystalline material consisting of a single layer of atoms. As widely accepted in the art, “2-D material” may also be referred to as a “mono-layer” material. In this disclosure, “2-D material” and “mono-layer” material are used interchangeably without differentiation in meanings, unless specifically pointed out otherwise. The 2-D material layer110may be 2-D materials of suitable thickness. In some embodiments, a 2-D material includes a single layer of atoms in each of its mono-layer structure, so the thickness of the 2-D material refers to a number of mono-layers of the 2-D material, which can be one mono-layer or more than one mono-layer. The coupling between two adjacent mono-layers of 2-D material includes van der Waals forces, which are weaker than the chemical bonds between/among atoms within the single mono-layer.

In some embodiments, the 2-D material layer110may be 2-D semiconductor (or semiconductive) materials, which are usually few-layer thick and exist as stacks of strongly bonded layers with weak interlayer van der Waals attraction, allowing the layers to be mechanically or chemically exfoliated into individual, atomically thin layers. The 2-D semiconductor materials are promising candidates of the channel, source, and drain materials of transistors. Examples of 2-D semiconductor materials include transition metal dichalcogenides (TMDs), graphene, layered III-VI chalcogenide, graphene, hexagonal Boron Nitride (h-BN), black phosphorus or the like. The 2-D semiconductor may include one or more layers and can have a thickness within the range of about 0.5-100 nm in some embodiments. One advantageous feature of the few-layered 2D semiconductor is the high electron mobility value. In some embodiments, the 2-D material layer110will serve as a channel layer, and thus the 2-D material layer110can also be referred to as a 2-D material channel layer.

FIG.1Billustrates a molecular diagram of a transition metal dichalcogenide compound (e.g., the 2-D material layer110) according to some embodiments of the present disclosure. The one-molecule thick TMD material layer includes atoms1002of a transition metal and atoms904of a chalcogenide. The transition metal atoms1002may form a layer in a middle region of the one-molecule thick TMD material layer, and the chalcogen atoms1004may form a first layer over the middle layer of transition metal atoms1002, and a second layer underlying the middle layer of transition metal atoms1004. The transition metal atoms1002may be W atoms or Mo atoms, while the chalcogen atoms1004may be S atoms, Se atoms, or Te atoms. Throughout the description, the illustrated cross-bonded layers including one layer of transition metal atoms1002and two layers of chalcogen atoms1004in combination are referred to as a mono-layer of TMD. Similar to graphene, transition metal dichalcogenide materials align in generally planar mono-layers. Also similar to graphene, transition metal dichalcogenide materials exhibit high conductivity and carrier mobility.

In some embodiment where the 2-D material layer110is made of TMD mono-layers, the TMD mono-layers may include molybdenum disulfide (MoS2), tungsten disulfide (WS2), tungsten diselenide (WSe2), or the like. In some embodiments, MoS2and WS2may be formed on the 2-D material layer110, using suitable approaches. For example, MoS2and WS2may be formed by micromechanical exfoliation and coupled over the substrate 2-D material layer110, or by sulfurization of a pre-deposited molybdenum (Mo) film or tungsten (W) film over the 2-D material layer110. In alternative embodiments, WSe2may be formed by micromechanical exfoliation and coupled over the 2-D material layer110, or by selenization of a pre-deposited tungsten (W) film over the 2-D material layer110using thermally cracked Se molecules.

In some embodiments, forming of the 2-D material layer110also includes treating the 2-D material layer110to obtain expected electronic properties of the 2-D material layer110. The treating processes include thinning (namely, reducing the thickness of the 2-D material layer110), doping, or straining, to make the 2-D material layer110exhibit certain semiconductor properties, e.g., including direct bandgap.

Reference is made toFIG.2. A mask layer115is formed over the 2-D material layer110for patterning as will be discussed inFIG.3. In some embodiments, the mask layer115is a photoresist. The photoresist may be suitable material used in the art, such as Poly(methyl methacrylate) (PMMA), Poly(methyl glutarimide) (PMGI), Phenol formaldehyde resin (DNQ/Novolac), SU-8, and may be either positive or negative photoresist. The material of mask layer115may be applied as a liquid and, generally, spin-coated to ensure uniformity of thickness.

Reference is made toFIG.3. The mask layer115is patterned, so as to form openings O1in the mask layer115that expose the top surface of the 2-D material layer110. In some embodiments, the mask layer115may be patterned using photolithography patterning processes. The photolithography patterning processes may include photoresist coating, soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, and/or combinations thereof.

Reference is made toFIGS.4A and4B, in whichFIG.4Bis a deposition chamber in accordance with some embodiments of the present disclosure. A first deposition process is performed to form a first metal layer120over the structure ofFIG.3. In greater details, the first metal layer120is formed in the openings O1of the mask layer115and in contact with the top surface of the 2-D material layer110. The first metal layer120may also be formed over the top surface of the mask layer115. Here, the “top surface” of the mask layer115or the 2-D material layer110may be a surface of the mask layer115or the 2-D material layer110distal to the substrate100.

The first deposition process may be formed using an e-gun evaporation deposition chamber as will be described inFIG.4B. For example, a wafer, where the structure ofFIG.3disposed on, may be moved into an e-gun evaporation deposition chamber. Then, the structure is flipped over and is fixed in the e-gun evaporation deposition chamber. An evaporated first metal120E is generated in the e-gun evaporation deposition chamber, and condenses over the structure ofFIG.3to form the first metal layer120.

The evaporated first metal120E and the first metal layer120may be made of a metal including low melting point, such as tin (Sn), bismuth (Bi), indium (In), or other suitable metals. In some embodiments, the first metal layer120may be deposited with a deposition rate in a range from about 0.5 Å/second to about 1.0 Å/second at a high vacuum. For example, the pressure of the e-gun evaporation deposition chamber may be kept lower than 1×10-6torr, such as 1×10-7torr, during the deposition of the first metal layer120. In some embodiments, the first metal layer120has a thickness in a range from about 15 nm to about 25 nm, such as 20 nm in some embodiments. Here, the metal including “low melting point” can be referred to as a metal having a melting point lower than the thermal budget of back-end-of-line (BEOL), such as about 450° C. In some embodiments, the melting point of the low melting point metal may be in a range from about 100° C. to about 300° C.

FIG.4Bis an example of an e-gun evaporation deposition chamber in accordance with some embodiments of the present disclosure. The e-gun evaporation deposition chamber includes a substrate holder1120. In some embodiments, the substrate holder1120has a dome shape, and thus can also be referred to as a substrate dome. The substrate holder1120includes a plurality of slots1122where wafers are disposed. For example, a wafer including the structure ofFIG.3may be flipped over and be placed in one of the slots1122of the substrate holder1120.

The e-gun evaporation deposition chamber further includes a crucible1130filled with metal source1132and an electron source1138(or electron gun). In some embodiments, the electron source1138emits free electrons within the vacuum chamber using a filament. These free electrons are guided by a magnetic field into the crucible1130containing the metal source1132. Energy associated with the free electrons is absorbed by the solid precursor of metal source1132, producing an impact region that experiences a rapid rise in temperature. As a result, a portion of the metal source1132either liquefies or sublimes, liberating vapor into the e-gun evaporation deposition chamber. A shutter1135can open so as to allow evaporation of at least a portion of the metal source1132into the evaporation chamber, the evaporated particles of the metal source1132may condense on the wafers to produce a thin film over the wafers.

The e-gun evaporation deposition chamber further includes a heater1140. In some embodiments, the heater1140is heating means for heating the wafers in the slots1122of the substrate holder1120to an appropriate temperature to improve property such as adhesiveness of the thin film to be vapor deposited on the wafers in the slots1122of the substrate holder1120. The e-gun evaporation deposition chamber further includes a crystal type film thickness meter1145. In some embodiments, the crystal type film thickness meter1145is used to determine whether the film thickness of the thin films formed on the wafers has reached a predetermined required film thickness. The e-gun evaporation deposition chamber further includes a vacuum pump1150. In some embodiments, the vacuum pump1150can create a vacuum environment in the e-gun evaporation deposition chamber, which allows the evaporated particles to travel directly to a deposition target, such as the wafers disposed in the slots1122of the substrate holder1120.

Reference is made toFIG.5. After the first deposition process ofFIG.4Ais completed, a second deposition process is performed to form a second metal layer130over the structure ofFIG.4A. In greater details, the second metal layer130is formed in the openings O1of the mask layer115. The second metal layer130may also be formed over the top surface of the mask layer115.

Similar to the first deposition process, the second deposition process may also be formed using the e-gun evaporation deposition chamber as described inFIG.4B. For example, a wafer, where the structure ofFIG.4Adisposed, may be moved into the e-gun evaporation deposition chamber. Then, the structure is flipped over and is fixed in the e-gun evaporation deposition chamber. An evaporated second metal130E is generated in the e-gun evaporation deposition chamber, and condenses over the structure ofFIG.4Ato form the second metal layer130. The difference between the first deposition process and the second deposition process is that the materials of the metal source (e.g., the metal source1132ofFIG.4B) are different.

The evaporated second metal130E and the second metal layer130may be made of a metal including high melting point, such as gold (Au), platinum (Pt), palladium (Pd), or other suitable metals. In some embodiments, the second metal layer130may be deposited with a deposition rate in a range from about 1.0 Å/second to about 2.0 Å/second at a high vacuum. For example, the pressure of the e-gun evaporation deposition chamber may be kept lower than 1×10-6torr, such as 1×10-7torr, during the deposition of the first metal layer120. In some embodiments, the second metal layer130has a thickness in a range from about 15 nm to about 25 nm, such as 20 nm in some embodiments. Here, the metal including “high melting point” can be referred to as a metal having a melting point higher than the thermal budget of back-end-of-line (BEOL), such as about 450° C. In some embodiments, the melting point of the high melting point metal may be in a range from about 1000° C. to about 1700° C.

In some embodiments, the material of the evaporated first metal120E and the first metal layer120(seeFIG.4A) has a lower melting point than the material of the evaporated second metal130E and the second metal layer130. Accordingly, a higher temperature is needed to change the material of the second metal layer130from solid phase to gas phase (e.g., the evaporated second metal130E) than to change the material of the first metal layer120from solid phase to gas phase (e.g., the evaporated first metal120E). As a result, during the second deposition process ofFIG.5, the high temperature second metal layer130will “re-melt” the first metal layer120ofFIG.4A, and will change the first metal layer120from solid phase to liquid phase (or gas phase). For example, the solid first metal layer120is re-melted to a melted first metal layer122M as shown inFIG.5.

As mentioned above, the second metal layer130has a higher melting point than the first metal layer120(seeFIG.4A). Therefore, when temperature decreases, the material of the second metal layer130will change to solid phase prior to the material of the first metal layer120changes to solid phase. As shown inFIG.5, during the second deposition process, a solid second metal layer130may be formed, while the melted first metal layer122M may be still in a liquid phase (or gas phase) so that the liquid-phase first metal122is flowable on the solid-phase second metal130. Thus, after the melted first metal layer122M turns into solid phase due to cooling down,, the melted first metal layer122M will be conformally coated on surfaces of the second metal layer130. In greater details, in the cross-sectional view ofFIG.5, the melted first metal layer122M is coated on top surface, opposite sidewalls, and bottom surfaces of the second metal layer130. Stated another way, the melted first metal layer122M is coated on at least four sides of the second metal layer130in the cross-sectional view ofFIG.5. Accordingly, the melted first metal layer122M may separate the second metal layer130from sidewalls of the mask layer115. In some embodiments, the first metal layer122has a thickness that is less than a thickness of the first metal layer120(seeFIG.4A), this is because the first metal layer120is re-melted and is coated on a larger surface of the second metal layer130.

Reference is made toFIG.6. After the second deposition ofFIG.5is completed, the second metal layer130and the first metal layer122are formed. In greater details, the melted first metal layer122M ofFIG.5becomes the solid first metal layer122when temperature decreases. That is, during the processes described inFIGS.4A to6, the first metal layer120is first deposited over the substrate via a first deposition process. A second metal layer130is then deposited over the substrate via a second deposition process, while the first metal layer120is re-melted during the second deposition process and becomes the melted first metal layer122M. The melted first metal layer122M then becomes the solid-phase first metal layer122.

Reference is made toFIGS.7A and7B, in whichFIG.7Bis a schematic view ofFIG.7A. The mask layer115is removed. In some embodiments where the mask layer115is a photoresist, the mask layer115may be removed by a lift-off process. Portions of the first metal layer122and the second metal layer130over the top surface of the mask layer115are removed together with the mask layer115, while leaving portions of the first metal layer122and the second metal layer130in the openings O1of the mask layer115remain over the 2-D material layer110. After the mask layer115is removed, metal structures140are formed. In greater details, each of the metal structures140includes the remaining portions of the first metal layer122and the second metal layer130. In some embodiments, the metal structures140may be formed over source/drain portions of the 2-D material layer110and will serve as source/drain contacts in the final transistor device, and thus the metal structures140can also be referred to as source/drain contacts140or source/drain conductive contacts140.

From another view point, each of the metal structures140has an inner portion142and an outer portion144wrapping the inner portion142. That is, the outer portion144covers the top surface, the opposite sidewalls, and the bottom surface of the inner portion142. In some embodiments, each of the metal structures140is a mixture of a first metal and a second metal. For example, the first metal is a material of the first metal layer122, which includes a low melting point metal, such as tin (Sn), bismuth (Bi), indium (In), or other suitable metals. The second metal is a material of the second metal layer130, which includes a high melting point metal, such as gold (Au), platinum (Pt), palladium (Pd), or other suitable metals. In some embodiments, an atomic concentration of the first metal in the outer portion144is greater than an atomic concentration of the second metal in the outer portion144. Moreover, an atomic concentration of the first metal in the inner portion142is lower than an atomic concentration of the second metal in the inner portion142. Stated differently, an atomic concentration of the first metal in the outer portion144is greater than an atomic concentration of the first metal in the inner portion142. Furthermore, an atomic concentration of the second metal in the outer portion144is lower than an atomic concentration of the second metal in the inner portion142. Yet from another view point, along the top surface, the sidewalls, and the bottom surface of each of the metal structures140, an atomic concentration of the first metal is higher than an atomic concentration of the second metal. Furthermore, an atomic concentration of the first metal at a middle portion of each of the metal structures140is lower than an atomic concentration of the second metal at the middle portion of each of the metal structures140.

FIG.7Bis a schematic view ofFIG.7A. InFIG.7B, four metal structures140are illustrated. In some embodiments, each of the metal structures140may extend from the top surface of the 2-D material layer110to the top surface of the dielectric layer105.

Reference is made toFIG.8. A gate structure150is formed over the substrate100and covering a channel portion of the 2-D material layer110. In some embodiments, gate structure150includes a gate dielectric layer152and a gate electrode154over the gate dielectric layer152. In some embodiments, the 2-D material layer110, the gate structure150, and the source/drain contacts140may collectively serve as a transistor.

In greater details, the gate dielectric layer152is formed in contact with the 2-D material layer110and covering the channel region of the 2-D material layer110. Moreover, the gate dielectric layer152is in contact with sidewalls of the first metal layer122of the metal structures140. In some embodiments, because the second metal layer130is wrapped by the first metal layer122, the second metal layer130is separated from the gate dielectric layer152of the gate structure150.

The gate dielectric layer152includes silicon oxide, silicon oxynitride, a combination thereof, or another suitable material. In some embodiments, the gate dielectric layer152includes a high dielectric constant material (high-k material), in accordance with some embodiments. The high-k material includes metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, aluminum oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, another suitable material, or a combination thereof, in accordance with some embodiments. The high-k material includes hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or a combination thereof, in accordance with some embodiments. The gate dielectric layer152is formed using a chemical vapor deposition process or another suitable process.

The gate electrode154can be formed of suitable electrically conductive material, including polysilicon and metal including one or more layers of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, nickel, manganese, silver, palladium, rhenium, iridium, ruthenium, platinum, zirconium, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The gate electrode154may be formed by one or more deposition processes, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (sputtering), electroplating, and/or other suitable method, followed by one or more etching process to pattern the deposited materials of gate electrode154.

In some embodiments where the first deposition process is omitted, namely only the second metal layer (e.g., the second metal layer130) is deposited, the second metal layer having a higher melting point may case thermal damage to the underlying 2-D material layer (e.g., the 2-D material layer110) and will result in a higher contact resistance. In some embodiments where only the second metal layer is deposited, an additional cooling system is disposed on a backside of the wafer to prevent thermal damage from the second metal layer with high temperature. However, this will also result in a poor crystallinity of the second metal layer, and therefore will result in a poor device performance.

On the other hand, in some embodiments where the second deposition process is omitted, namely only the first metal layer (e.g., the first metal layer120) is deposited, although the first metal layer may not cause thermal damage to the underlying structure, cluster effect may be induced during forming the first metal layer, and thus the first metal layer does not adhere well over the substrate and over the 2-D material layer.

In some embodiments of the present disclosure, a method of forming source/drain contacts is provided, in which a first deposition process is performed to deposit a first metal layer (e.g., the first metal layer120), and then a second deposition process is performed to deposit a second metal layer (e.g., the second metal layer130) having a higher melting point than the first metal layer. Accordingly, during the second deposition process, the second metal layer may re-melt the first metal layer, and cause the melted first metal layer (e.g., the melted first metal layer 122 M) coated on surfaces of the second metal layer. The melted first metal layer can act as a buffer layer to prevent the second metal layer from causing thermal damage. Furthermore, the resulting source/drain contacts (e.g., the source/drain contacts140) may include better crystallinity and adhesion, which in turn will lower the contact resistance. Moreover, the source/drain contacts can be formed without using additional cooling system. Accordingly, the device performance may be improved.

FIG.9is an experiment result of a semiconductor device in accordance with some embodiments of the present disclosure. In particular, the experiment result ofFIG.9is obtained from the semiconductor device ofFIG.8, in which the 2-D material layer110ofFIG.8is made of MoS2, the first metal layer122of the source/drain contact140is made of Sn, and the second metal layer130of the source/drain contact140is made of Au. The results show that when drain-voltage VDSis about 1V, the on-current Ionof the device can be up to about 480µA/µm, which is better than the samples which only include the first metal layer122or only include the second metal layer130.

FIG.10is an experiment result of a semiconductor device in accordance with some embodiments of the present disclosure. In particular, the experiment result ofFIG.9is obtained from the semiconductor device ofFIG.8, in which the 2-D material layer110ofFIG.8is made of MoS2, the first metal layer122of the source/drain contact140is made of Sn, and the second metal layer130of the source/drain contact140is made of Au. The results show that the contact resistance of the disclosed source/drain contacts140is down to about 0.84kΩ·µm when the channel length is about 35 nm, the carrier density is about 1×1013cm-2, and without intentional doping of the 2-D material layer110. In comparison, if the source/drain contacts are made of Ni (high melting point), the contact resistance of the source/drain contacts is about 3.3 kΩ·µm when the channel length is about 35 nm.

FIG.11is an experiment result of a semiconductor device in accordance with some embodiments of the present disclosure. In particular, the experiment result ofFIG.9is obtained from the semiconductor device ofFIG.8, in which the 2-D material layer110ofFIG.8is made of MoS2, the first metal layer122of the source/drain contact140is made of Sn, and the second metal layer130of the source/drain contact140is made of Au. The results show that at different temperatures (e.g., 150 K and 300 K), the drain current show linearity when gate voltage increases from 0 to 30V. The high current linearity implies that the interface between the 2-D material layer110and the first metal layer122(e.g., Sn-MoS2interface) has negligible Schottky barrier height, and therefore a low contact resistance at the interface.

FIG.12is an experiment result of a semiconductor device in accordance with some embodiments of the present disclosure. In particular, the experiment result ofFIG.9is obtained from the semiconductor device ofFIG.8, in which the 2-D material layer110ofFIG.8is made of MoS2, the first metal layer122of the source/drain contact140is made of Sn, and the second metal layer130of the source/drain contact140is made of Au. The results show that the electrical property of the disclosed source/drain contacts140is improved at low temperature (e.g., room temperature; RT). However, if the source/drain contacts are made of Ni (high melting point), the electrical property thereof is deteriorated at low temperature (e.g., room temperature; RT). This is because when the source/drain contact140includes Sn and Au, the contact resistance of the source/drain contact140is low, and the overall impedance is channel-dominated. Accordingly, when temperature decreases, the mobility of the device will increase because of less phonon collision under low temperature, and thus the current will increase. However, for Ni source/drain contact, the contact resistance is high, and thus the overall impedance is contact-dominated. Because the carriers in the Ni source/drain contact are conducted by thermal emission, the current will therefore decrease at low temperature, and will result in a high total resistance.

FIGS.13to40illustrate a method in various stages of fabricating a semiconductor device in accordance with some embodiments of the present disclosure.

Reference is made toFIG.13. Shown there is a substrate200. The substrate200may be similar to the substrate100as described inFIGS.1A to8. The substrate200may be doped. For example, the substrate200may be doped with p-type impurities, and thus the substrate200can be referred to as a p-type substrate200.

A photoresist layer205is formed over the substrate200. The photoresist layer205may be suitable material used in the art, such as Poly(methyl methacrylate) (PMMA), Poly(methyl glutarimide) (PMGI), Phenol formaldehyde resin (DNQ/Novolac), SU-8, and may be either positive or negative photoresist.

Reference is made toFIG.14. An exposure process is performed to the photoresist layer205using a mask MA1. In some embodiments, portions of the photoresist layer205are exposed through the mask MA1.

Reference is made toFIG.15. The portions of the photoresist layer205that are exposed during the exposure process are removed through a development process. After the portions of the photoresist layer205are removed, portions of the top surface of the substrate200are exposed by the photoresist layer205.

Reference is made toFIG.16. An etching process is performed to the substrate200, by using the patterned photoresist layer205as an etch mask. As a result, trenches T1are formed in the substrate200. In some embodiments, the substrate200may include a first protrusion portion200A and a second protrusion portion200B, in which the first protrusion portion200A and the second protrusion portion200B are separated by a trench T1.

Reference is made toFIG.17. The photoresist layer205is removed. In some embodiments, the photoresist layer205may be removed by a striping process.

Reference is made toFIG.18. A patterned mask layer208is formed over the first protrusion portion200A and the second protrusion portion200B of the substrate200. In some embodiments, the patterned mask layer208may be a photoresist or may be a hard mask, and may be patterned using suitable photolithography process.

Reference is made toFIG.19. Shallow trenches isolation (STI) structures210are formed in the trenches T1of the substrate200. After the STI structures210are formed, the patterned mask layer208is removed, such that the STI structures210protrudes from top surfaces of the first protrusion portion200A and the second protrusion portion200B of the substrate200. In some embodiments, the STI structures210may be made of oxide, such as silicon oxide (SiO2).

Reference is made toFIG.20. Dielectric layers215are formed over the first protrusion portion200A and the second protrusion portion200B of the substrate200, respectively. In some embodiments, the dielectric layers215may be made of nitride, such as silicon nitride (Si3N4).

Reference is made toFIG.21. A patterned mask217is formed covering the protrusion portion200A of the substrate200, while exposing the protrusion portion200B of the substrate200. Afterwards, a 2-D material layer220is formed over the protrusion portion200B of the substrate200. The 2-D material layer220may be formed by a similar method for forming the 2-D material layer110as discussed inFIGS.1A to8.

Reference is made toFIG.22. After the 2-D material layer220is formed, the patterned mask217is removed, and a patterned mask218is formed covering the 2-D material layer220, while exposing the protrusion portion200A of the substrate200. Afterwards, a 2-D material layer222is formed over the protrusion portion200A of the substrate200. The 2-D material layer222may be formed by a similar method for forming the 2-D material layer110as discussed inFIGS.1A to8. In some embodiments, the 2-D material layers220and222are made of different 2-D materials. For example, the 2-D material layer222is made of WS2, while the 2-D material layer220is made of MoS2. In some embodiments, the 2-D material layer222made of WS2can be used for a P-type device, such as P-FET, while the 2-D material layer220made of MoS2can be used for a N-type device, such as N-FET. In some embodiments, treating processes may be performed to the 2-D material layer222made of WS2to make the 2-D material layer222exhibit different conductivity than the2-D material layer220. The treating processes include thinning (namely, reducing the thickness of the 2-D material layer222), doping, or straining.

Reference is made toFIG.23. After the 2-D material layer222is formed, the patterned mask218is removed. Reference is made toFIG.24. A photoresist layer225is formed over the substrate200and covering the protrusion portions200A and200B of the substrate200.

Reference is made toFIG.25. The photoresist layer225is patterned to form openings O2that exposed portions of the 2-D material layer220and222. In greater details, the openings O2may expose source/drain regions of the 2-D material layers220and222, respectively.

Reference is made toFIG.26. Source/drain contacts230are formed in the openings O2of the photoresist layer225and in contact with the source/drain regions of the 2-D material layers220and222, respectively. In greater details, each of the source/drain contacts230includes a first metal layer232and a second metal layer234. The source/drain contacts230, the first metal layer232, and the second metal layer234may be similar to the source/drain contacts140, the first metal layer122, and the second metal layer130as described inFIGS.1A to8, and the formation method thereof can be similar to the processes as described inFIGS.1A to8.

For example, a first deposition process is performed to deposit the first metal layer232, and then a second deposition process is performed to deposit the second metal layer234having a higher melting point than the first metal layer232. During the second deposition process, the second metal layer234with high deposition temperature may re-melt the first metal layer232, and cause the melted first metal layer232coated on surfaces of the second metal layer234. After the source/drain contacts230are formed, the photoresist layer225is removed by suitable process, such as a lift-off process. In some embodiments, the source/drain contacts230may include thicknesses in a range from about 30 nm to about 60 nm.

Reference is made toFIG.27. Gate dielectric layers235are formed over the exposed portions of the 2-D material layers220and222, respectively. In greater details, the gate dielectric layers235may be in contact with channel regions of the 2-D material layers220and222, and may be in contact with sidewalls of the source/drain contacts230, respectively. In some embodiments, the gate dielectric layers235may be similar to the gate dielectric layer152as described inFIGS.1A to8. The gate dielectric layers235may be formed by suitable deposition process and may be patterned using suitable lithography process. In some embodiments, the gate dielectric layer235has a thickness in a range from about 10 nm to about 100 nm.

Work function metal layers236, gate electrodes237, and hard masks238are formed over the gate dielectric layers235, respectively. In some embodiments, the work function metal layers236, the gate electrodes237, and the hard masks238may be formed by, for example, sequentially depositing materials of the work function metal layers236, the gate electrodes237, and the hard masks238over the substrate200, and patterning the materials to form the work function metal layers236, the gate electrodes237, and the hard masks238.

In some embodiments, each gate dielectric layer235and the overlying work function metal layer236and the gate electrode237can be collectively referred to as a gate structure240. Therefore, one gate structure240is formed over the protrusion portion200A of the substrate200, and one gate structure240is formed over the protrusion portion200B of the substrate200. The 2-D material layer220, the gate structure240, and the source/drain contacts230over the protrusion portion200A of the substrate200may collectively form a first transistor. In some embodiments where the 2-D material layer220is made of MoS2, the first transistor may be a N-type transistor, such as N-FET. The 2-D material layer222, the gate structure240, and the source/drain contacts230over the protrusion portion200B of the substrate200may collectively form a second transistor. In some embodiments where the 2-D material layer222is made of WS2, the first transistor may be a P-type transistor, such as P-FET.

In some embodiments, word function metal layers236are formed over the gate dielectric layers235, respectively. In some embodiments, the work function metal layer236may include an n-type, a p-type work function layers, or combinations thereof to obtain a desired work function value. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. In some embodiments, the gate electrodes237may include tungsten (W). In some other embodiments, the gate electrodes237includes aluminum (Al), copper (Cu) or other suitable conductive material. In some embodiments, hard masks238may be oxide.

A plurality of gate spacers239are disposed on opposite sides of the gate structures240. In some embodiments, the gate spacers239may include SiO2, Si3N4, SiOxNy, SiC, SiCN films, SiOC, SiOCN films, and/or combinations thereof.

Conductive features250are formed in the ILD layer246and contact the source/drain contacts230. In some embodiments, each conductive feature250includes a liner252and a plug254. The liner252is between plug254and the underlying source/drain contacts230. In some embodiments, the liner252assists with the deposition of plug254and helps to reduce diffusion of a material of plug254through the gate spacers239. In some embodiments, the liner252includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or another suitable material. The Plug254includes a conductive material, such tungsten (W), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), or other suitable conductive material.

Reference is made toFIG.28. An etch stop layer (ESL)260is formed over the ILD layer246and the conductive features250. Reference is made toFIG.29. An inter-metal dielectric (IMD) layer265is disposed over the ESL260. The material and the formation method of the ESL260are similar to those of the CESL245. Moreover, the material and the formation method of the IMD layer265are similar to those of the ILD layer246.

Reference is made toFIG.30. The ESL260and the IMD layer265are patterned to form openings O3. Then, a liner270and a metal seed layer275are formed in the openings O3. In some embodiments, the liner270includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or another suitable material. The metal seed layer275may be copper (Cu), cobalt (Co), nickel (Ni), ferrum (Fe), or suitable conductive materials.

Reference is made toFIG.31. A graphene layer280is deposited over the metal seed layer275. The graphene layer280may be formed by epitaxial graphene growth. In some embodiments, a silicon carbide dielectric is used as a seed layer to promote the epitaxial growth of the graphene on the substrate200. In some embodiments, another exemplary technique for forming a graphene layer utilizes CVD (chemical vapor deposition) directly on the substrate200. In some other embodiments, graphene layer may be formed on a backing material (such as an adhesive tape), the backing material can be adhered to the substrate200. Then, the backing material can be removed while leaving the graphene layer on the substrate200. In some other embodiments, graphene is formed by reacting a metal film with silicon carbide to form a metal carbide. The metal carbide is annealed to produce a metal silicide and graphene from the remaining carbon. In yet other exemplary embodiments, graphene layer is deposited using an aqueous solution of graphene oxide.

Reference is made toFIG.32. A filling metal290is deposited over the graphene layer280and fills the openings O3. In some embodiments, the material of the filling metal290may be similar to the metal seed layer275. In some embodiments, the filling metal290may be formed by, for example, PVD, CVD, ALD, electroplating, or suitable processes. In some embodiments, an annealing process may be performed after forming the filling metal290.

Reference is made toFIG.33. A chemical mechanical polishing (CMP) process is performed to remove excessive materials of the filling metal290, the graphene layer280, the metal seed layer275, and the liner270until the IMD layer265is exposed. In some embodiments, the remaining filling metal290, the graphene layer280, the metal seed layer275, and the liner270can be referred to as metal-1 (M1) layer in a back end of line (BEOL) process.

Reference is made toFIG.34. A plurality of graphene layers295are deposited on the remaining filling metal290, the graphene layer280, the metal seed layer275, and the liner270. In some embodiments, the graphene layers295tend to grow on a graphene surface and/or a metal surface rather than on a dielectric surface. As an example inFIG.34, the graphene layers295is selectively formed on the filling metal290, the graphene layer280, the metal seed layer275, and the liner270, while the graphene layers295is not formed on the IMD layer265.

Reference is made toFIG.35. An ESL300, an IMD layer305, an ESL310, and an IMD layer315are formed sequentially over the IMD layer265. The ESLs300and310are similar to the ESL260, the IMD layers305and315are similar to the IMD layer265, and thus relevant details will not be repeated for brevity.

Reference is made toFIG.36. The ESL300, the IMD layer305, the ESL310, and the IMD layer315are patterned to form via openings O4. In some embodiments, the via openings O4are aligned with and expose the graphene layer295. In some embodiments, via openings O4may be formed by, for example, forming a patterned photoresist layer over the IMD layer315, followed by an etching process to remove portions of the ESL300, the IMD layer305, the ESL310, and the IMD layer315, and then removing the photoresist layer.

Reference is made toFIG.37. The ESL310, and the IMD layer315are patterned to form trenches T2that are aligned above via openings O4. In some embodiments, trenches T2may be formed by, for example, forming a patterned photoresist layer over the IMD layer315, followed by an etching process to remove portions of the ESL310, and the IMD layer315, and then removing the photoresist layer.

Reference is made toFIG.38. A liner320, a metal seed layer325, and a graphene layer330are formed sequentially over the IMD layer315and in the via openings O4and the trenches T2. The liner320and the metal seed layer325are similar to the liner270and the metal seed layer275, respectively, and thus relevant details will not be repeated for brevity. The graphene layer330is similar to the graphene layer295, and thus relevant details will not be repeated for brevity.

Reference is made toFIG.39. A filling metal340is deposited over the graphene layer330and fills the via openings O4and trenches T2. The filling metal340is similar to the filling metal290, and thus relevant details will not be repeated herein after.

Reference is made toFIG.40. A chemical mechanical polishing (CMP) process is performed to remove excessive materials of the filling metal340, the graphene layer330, the metal seed layer325, and the liner320until the IMD layer315is exposed. In some embodiments, the remaining filling metal340, the graphene layer330, the metal seed layer325, and the liner320can be referred to as metal-2 (M2) layer in a back end of line (BEOL) process.

FIGS.41A to41Eillustrate semiconductor devices in accordance with some embodiments of the present disclosure. It is noted that some elements described inFIGS.41A to41Emay be similar to those described inFIGS.1A to8, and thus relevant details will not be repeated for brevity.FIGS.41A to41Eare examples of “top gate” semiconductor device, in which source/drain contacts are in direct contact with top surface of a 2-D material channel layer.

Reference is made toFIG.41A. The device includes a substrate400, a dielectric layer405over the substrate400, a 2-D material channel layer410over the substrate400, source/drain contacts420over source/drain regions of the 2-D material channel layer410, and a gate structure430over channel region of the 2-D material channel layer410.

In some embodiments, each of the source/drain contacts420includes a first metal layer422and a second metal layer424. The source/drain contacts420, the first metal layer422, and the second metal layer424may be similar to the source/drain contacts140, the first metal layer122, and the second metal layer130as described inFIGS.1A to8, and the formation method thereof can be similar to the processes as described inFIGS.1A to8.

Reference is made toFIG.41B. The gate structure430incudes a gate dielectric layer432and a gate electrode434over the gate dielectric layer432. In some embodiments, the gate dielectric layer432has a thickness in a range from about 1 nm to about 10 nm. In some embodiments, the gate electrode434does not overlap the source/drain contacts420.

Reference is made toFIG.41C. The gate structure430incudes a gate dielectric layer432and a gate electrode435over the gate dielectric layer432. Different from the gate electrode434ofFIG.41B, the gate electrode435overlaps the source/drain contacts420.

Reference is made toFIG.41D.FIG.41Dis similar toFIG.41B, the difference betweenFIG.41DandFIG.41Bis that a spacer450is disposed between the gate dielectric layer432of the gate structure430and the 2-D material channel layer410. In some embodiments, the spacer450has a thickness in a range from about 0.4 nm to about 0.8 nm. In some embodiments, the spacer450may be made of polymethylmethacrylate (PMMA), polydimethylsiloxane (PDMS), or photoresist (PR).

Reference is made toFIG.41E.FIG.41Eis similar toFIG.41C, the difference betweenFIG.41EandFIG.41Cis that a spacer450is disposed between the gate dielectric layer432of the gate structure430and the 2-D material channel layer410.

FIGS.42A to42Eillustrate semiconductor devices in accordance with some embodiments of the present disclosure. It is noted that some elements described inFIGS.42A to42Emay be similar to those described inFIGS.1A to8, and thus relevant details will not be repeated for brevity.FIGS.42A to42Eare examples of “top gate” semiconductor device, in which source/drain contacts are in contact with edges of a 2-D material channel layer.

Reference is made toFIG.42A. The device includes a substrate500, a dielectric layer505over the substrate500, a 2-D material channel layer510over the substrate500, source/drain contacts520in contact with source/drain regions of the 2-D material channel layer510, and a gate structure530over channel region of the 2-D material channel layer510. In some embodiments, the source/drain contacts520are in contact with the 2-D material channel layer510through edges of the 2-D material channel layer510.

In some embodiments, each of the source/drain contacts520includes a first metal layer522and a second metal layer524. The source/drain contacts520, the first metal layer522, and the second metal layer524may be similar to the source/drain contacts140, the first metal layer122, and the second metal layer130as described inFIGS.1A to8, and the formation method thereof can be similar to the processes as described inFIGS.1A to8.

Reference is made toFIG.42B. The gate structure530incudes a gate dielectric layer532and a gate electrode534over the gate dielectric layer532. In some embodiments, the gate dielectric layer532has a thickness in a range from about 1 nm to about 10 nm. In some embodiments, the gate electrode734does not overlap the source/drain contacts520.

Reference is made toFIG.42C. The gate structure530incudes a gate dielectric layer532and a gate electrode535over the gate dielectric layer532. Different from the gate electrode534ofFIG.42B, the gate electrode535overlaps the source/drain contacts520.

Reference is made toFIG.42D.FIG.42Dis similar toFIG.42B, the difference betweenFIG.42DandFIG.42Bis that a spacer550is disposed between the gate dielectric layer532of the gate structure530and the 2-D material channel layer510. In some embodiments, the spacer550has a thickness in a range from about 0.4 nm to about 0.8 nm. In some embodiments, the spacer750may be made of polymethylmethacrylate (PMMA), polydimethylsiloxane (PDMS), or photoresist (PR).

Reference is made toFIG.42E.FIG.42Eis similar toFIG.42C, the difference betweenFIG.42EandFIG.42Cis that a spacer550is disposed between the gate dielectric layer532of the gate structure530and the 2-D material channel layer510.

FIGS.43A to43Eillustrate semiconductor devices in accordance with some embodiments of the present disclosure. It is noted that some elements described inFIGS.43A to43Emay be similar to those described inFIGS.1A to8, and thus relevant details will not be repeated for brevity.FIGS.43A to43Eare examples of “bottom gate” semiconductor device, in which source/drain contacts are in direct contact with top surface of a 2-D material channel layer.

Reference is made toFIG.43A. The device includes a 2-D material channel layer610, source/drain contacts620disposed on top surface of the 2-D material channel layer610, and a gate structure630disposed on bottom surface of the 2-D material channel layer610.

In some embodiments, each of the source/drain contacts620includes a first metal layer622and a second metal layer624. The source/drain contacts620, the first metal layer622, and the second metal layer624may be similar to the source/drain contacts140, the first metal layer122, and the second metal layer130as described inFIGS.1A to8, and the formation method thereof can be similar to the processes as described inFIGS.1A to8.

Reference is made toFIG.43B. A dielectric layer605is disposed over a substrate600. The gate structure630is disposed over the dielectric layer605. The 2-D material channel layer610is disposed over the gate structure630. The source/drain contacts620are disposed over the 2-D material channel layer610. The gate structure630incudes a gate dielectric layer632and a gate electrode634below the gate dielectric layer632. In some embodiments, the gate dielectric layer632has a thickness in a range from about 1 nm to about 10 nm. In some embodiments, the gate electrode634does not overlap the source/drain contacts620.

Reference is made toFIG.43C. The gate structure630incudes a gate dielectric layer632and a gate electrode635below the gate dielectric layer632. Different from the gate electrode634ofFIG.43B, the gate electrode635overlaps the source/drain contacts620.

Reference is made toFIG.43D.FIG.43Dis similar toFIG.43B, the difference betweenFIG.43DandFIG.43Bis that a spacer650is disposed over the 2-D material channel layer610. In some embodiments, the spacer450has a thickness in a range from about 0.4 nm to about 0.8 nm. In some embodiments, the spacer450may be made of polymethylmethacrylate (PMMA), polydimethylsiloxane (PDMS), or photoresist (PR).

Reference is made toFIG.43E.FIG.43Eis similar toFIG.43C, the difference betweenFIG.43EandFIG.43Cis that a spacer650is disposed is disposed over the 2-D material channel layer610.

FIGS.44A to44Eillustrate semiconductor devices in accordance with some embodiments of the present disclosure. It is noted that some elements described inFIGS.44A to44Emay be similar to those described inFIGS.1A to8, and thus relevant details will not be repeated for brevity.FIGS.44A to44Eare examples of “bottom gate” semiconductor device, in which source/drain contacts are in contact with edges of a 2-D material channel layer.

Reference is made toFIG.44A. The device includes a 2-D material channel layer710, source/drain contacts720disposed on opposite sides of the 2-D material channel layer710, and a gate structure730disposed on bottom surface of the 2-D material channel layer710. In some embodiments, the source/drain contacts720are in contact with the 2-D material channel layer710through edges of the 2-D material channel layer710.

In some embodiments, each of the source/drain contacts720includes a first metal layer722and a second metal layer724. The source/drain contacts720, the first metal layer722, and the second metal layer724may be similar to the source/drain contacts140, the first metal layer122, and the second metal layer130as described inFIGS.1A to8, and the formation method thereof can be similar to the processes as described inFIGS.1A to8.

Reference is made toFIG.44B. A dielectric layer705is disposed over a substrate700. The gate structure730is disposed over the dielectric layer705. The 2-D material channel layer710is disposed over the gate structure730. The source/drain contacts720are disposed on opposite sides of the 2-D material channel layer710. The gate structure730incudes a gate dielectric layer732and a gate electrode734below the gate dielectric layer732. In some embodiments, the gate dielectric layer732has a thickness in a range from about 1 nm to about 10 nm. In some embodiments, the gate electrode734does not overlap the source/drain contacts720.

Reference is made toFIG.44C. The gate structure730incudes a gate dielectric layer732and a gate electrode735below the gate dielectric layer732. Different from the gate electrode734ofFIG.43B, the gate electrode735overlaps the source/drain contacts720.

Reference is made toFIG.44D.FIG.44Dis similar toFIG.44B, the difference betweenFIG.44DandFIG.44Bis that a spacer750is disposed over the 2-D material channel layer710. In some embodiments, the spacer750has a thickness in a range from about 0.4 nm to about 0.8 nm. In some embodiments, the spacer750may be made of polymethylmethacrylate (PMMA), polydimethylsiloxane (PDMS), or photoresist (PR).

Reference is made toFIG.44E.FIG.44Eis similar toFIG.44C, the difference betweenFIG.44EandFIG.44Cis that a spacer750is disposed is disposed over the 2-D material channel layer710.

FIGS.45A to45Eillustrate semiconductor devices in accordance with some embodiments of the present disclosure. It is noted that some elements described inFIGS.45A to45Emay be similar to those described inFIGS.1A to8, and thus relevant details will not be repeated for brevity.FIGS.45A to45Eare examples of “dual gate” semiconductor device, in which source/drain contacts are in contact with top surface of a 2-D material channel layer.

Reference is made toFIG.45A. The device includes a 2-D material channel layer810, source/drain contacts820disposed on top surface of the 2-D material channel layer810, and a gate structure830disposed on top surface of the 2-D material channel layer810, and a gate structure830disposed on bottom surface of the 2-D material channel layer810.

In some embodiments, each of the source/drain contacts820includes a first metal layer822and a second metal layer824. The source/drain contacts820, the first metal layer822, and the second metal layer824may be similar to the source/drain contacts140, the first metal layer122, and the second metal layer130as described inFIGS.1A to8, and the formation method thereof can be similar to the processes as described inFIGS.1A to8.

Reference is made toFIG.45B. A dielectric layer805is disposed over a substrate800. The gate structure840is disposed over the dielectric layer805. The 2-D material channel layer810is disposed over the gate structure840. The source/drain contacts820are disposed over the 2-D material channel layer810. The gate structure830is disposed over the 2-D material channel layer810. The gate structure830incudes a gate dielectric layer832and a gate electrode834over the gate dielectric layer832. The gate structure840incudes a gate dielectric layer842and a gate electrode844below the gate dielectric layer842. In some embodiments, the gate dielectric layers832and842have thicknesses in a range from about 1 nm to about 10 nm. In some embodiments, the gate electrodes834and844do not overlap the source/drain contacts820.

Reference is made toFIG.45C. The gate structure830incudes a gate dielectric layer832and a gate electrode835over the gate dielectric layer832. The gate structure840incudes a gate dielectric layer842and a gate electrode845below the gate dielectric layer842. Different from the gate electrodes834and844ofFIG.45B, the gate electrodes835and845overlap the source/drain contacts820.

Reference is made toFIG.45D.FIG.45Dis similar toFIG.45B, the difference betweenFIG.45DandFIG.45Bis that a spacer850is disposed between the gate dielectric layer832of the gate structure830and the 2-D material channel layer810. In some embodiments, the spacer850has a thickness in a range from about 0.4 nm to about 0.8 nm. In some embodiments, the spacer850may be made of polymethylmethacrylate (PMMA), polydimethylsiloxane (PDMS), or photoresist (PR).

Reference is made toFIG.45E.FIG.45Eis similar toFIG.45C, the difference betweenFIG.45EandFIG.45Cis that a spacer850is disposed between the gate dielectric layer832of the gate structure830and the 2-D material channel layer810.

FIGS.46A to46Eillustrate semiconductor devices in accordance with some embodiments of the present disclosure. It is noted that some elements described inFIGS.46A to46Emay be similar to those described inFIGS.1A to8, and thus relevant details will not be repeated for brevity.FIGS.46A to46Eare examples of “dual gate” semiconductor device, in which source/drain contacts are in contact with edges of a 2-D material channel layer.

Reference is made toFIG.46A. The device includes a 2-D material channel layer910, source/drain contacts920disposed on opposite sides of the 2-D material channel layer910, and a gate structure930disposed on top surface of the 2-D material channel layer910, and a gate structure930disposed on bottom surface of the 2-D material channel layer910. In some embodiments, the source/drain contacts920are in contact with the 2-D material channel layer910through edges of the 2-D material channel layer910.

In some embodiments, each of the source/drain contacts920includes a first metal layer922and a second metal layer924. The source/drain contacts920, the first metal layer922, and the second metal layer924may be similar to the source/drain contacts140, the first metal layer122, and the second metal layer130as described inFIGS.1A to8, and the formation method thereof can be similar to the processes as described inFIGS.1A to8.

Reference is made toFIG.46B. A dielectric layer905is disposed over a substrate900. The gate structure940is disposed over the dielectric layer905. The 2-D material channel layer910is disposed over the gate structure940. The source/drain contacts920are disposed on opposite sides of the 2-D material channel layer910. The gate structure930is disposed over the 2-D material channel layer910. The gate structure930incudes a gate dielectric layer932and a gate electrode934over the gate dielectric layer932. The gate structure940incudes a gate dielectric layer942and a gate electrode944below the gate dielectric layer942. In some embodiments, the gate dielectric layers932and942have thicknesses in a range from about 1 nm to about 10 nm. In some embodiments, the gate electrodes934and944do not overlap the source/drain contacts920.

Reference is made toFIG.46C. The gate structure930incudes a gate dielectric layer932and a gate electrode935over the gate dielectric layer932. The gate structure840incudes a gate dielectric layer942and a gate electrode945below the gate dielectric layer942. Different from the gate electrodes934and944ofFIG.46B, the gate electrodes935and945overlap the source/drain contacts920.

Reference is made toFIG.46D.FIG.46Dis similar toFIG.46B, the difference betweenFIG.46DandFIG.46Bis that a spacer950is disposed between the gate dielectric layer932of the gate structure930and the 2-D material channel layer910. In some embodiments, the spacer950has a thickness in a range from about 0.4 nm to about 0.8 nm. In some embodiments, the spacer950may be made of polymethylmethacrylate (PMMA), polydimethylsiloxane (PDMS), or photoresist (PR).

Reference is made toFIG.46E.FIG.46Eis similar toFIG.46C, the difference betweenFIG.46EandFIG.46Cis that a spacer950is disposed between the gate dielectric layer932of the gate structure930and the 2-D material channel layer910.

Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. A first deposition process is performed to deposit a first metal layer, and then a second deposition process is performed to deposit a second metal layer having a higher melting point than the first metal layer. Accordingly, during the second deposition process, the second metal layer may re-melt the first metal layer, and cause the melted first metal layer coated on surfaces of the second metal layer. An advantage of the present disclosure is that the melted first metal layer can act as a buffer layer to prevent the second metal layer from causing thermal damage. Furthermore, the resulting source/drain contacts may include better crystallinity and adhesion, which in turn will lower the contact resistance. Moreover, the source/drain contacts can be formed without using additional cooling system. Accordingly, the device performance may be improved.

In some embodiments of the present disclosure, a method includes forming a 2-D semiconductor material layer over a substrate; forming source/drain contacts over source/drain regions of the 2-D semiconductor material layer; and forming a gate structure over a channel region of the 2-D semiconductor material layer. Forming the source/drain contacts includes performing a first deposition process to deposit a first metal layer over the 2-D semiconductor material layer; and after the first deposition process is completed, performing a second deposition process to deposit a second metal layer over the first metal layer, in which the second metal layer has a higher melting point than the first metal layer.

In some embodiments, the second deposition process is performed such that the first metal layer is melted, and the melted first metal layer is conformally coated on the second metal layer.

In some embodiments, the gate structure is in contact with the first metal layer and separated from the second metal layer.

In some embodiments, forming the source/drain contacts further includes forming a mask layer over the 2-D semiconductor material layer; patterning the mask layer to form openings in the mask layer that expose the source/drain regions of the 2-D semiconductor material layer; and removing the mask layer after the second deposition process is completed.

In some embodiments, the second deposition process is performed such that the first metal layer is melted, and the melted first metal layer separates the second metal layer from the mask layer.

In some embodiments, the method further includes forming a dielectric layer over the substrate prior to forming the 2-D semiconductor material layer.

In some embodiments, the first metal layer is made of tin (Sn), bismuth (Bi), or indium (In), and the second metal layer is made of gold (Au), platinum (Pt), or palladium (Pd).

In some embodiments of the present disclosure, a method includes forming a 2-D semiconductor material layer over a substrate; forming a patterned mask over the substrate, in which the pattern mask includes openings that expose source/drain regions of the 2-D semiconductor material layer; depositing a first metal in the openings of the patterned mask; after depositing the first metal, depositing a second metal in the openings of the patterned mask; removing the patterned mask, while leaving portions of the first metal and the second metal over the 2-D material layer to form source/drain contacts, in which each of the source/drain contacts includes an inner portion and an outer portion wrapping the inner portion, and an atomic concentration of the first metal at the outer portion is higher than an atomic concentration of the second metal at the outer portion; and forming a gate structure over a channel region of the 2-D semiconductor material layer.

In some embodiments, the first metal has a lower melting point than the second metal.

In some embodiments, the first metal is re-melted during depositing the second metal.

In some embodiments, the atomic concentration of the first metal at the outer portion of each of the source/drain contacts is higher than an atomic concentration of the first metal at the inner portion of each of the source/drain contacts.

In some embodiments, the atomic concentration of the second metal at the outer portion of each of the source/drain contacts is lower than an atomic concentration of the second metal at the inner portion of each of the source/drain contacts.

In some embodiments, an atomic concentration of the first metal at the inner portion of each of the source/drain contacts is lower than an atomic concentration of the second metal at the inner portion of each of the source/drain contacts.

In some embodiments, first and second metal are deposited by an e-gun evaporation process.

In some embodiments of the present disclosure, a device includes a substrate, a 2-D semiconductor material layer over the substrate, a first conductive contact in contact with a first region of the 2-D semiconductor material layer, a second conductive contact in contact with a second region of the 2-D semiconductor material layer spaced apart from the first region of the 2-D semiconductor material layer, a gate structure over the 2-D semiconductor material layer and laterally between the first conductive contact and the second conductive contact. The first conductive contact is a mixture of a first metal and a second metal, and the first metal has a higher atomic concentration in an outer portion of the first conductive contact than in an inner portion of the first conductive contact.

In some embodiments, the second conductive contact is also a mixture of the first metal and the second metal, and the first metal has a higher atomic concentration in an outer portion of the second conductive contact than in an inner portion of the second conductive contact.

In some embodiments, the first metal has a lower melting point than the second metal.

In some embodiments, the first metal is made of tin (Sn), bismuth (Bi), or indium (In), and the second metal is made of gold (Au), platinum (Pt), or palladium (Pd).

In some embodiments, the device further includes a dielectric layer between the substrate and the 2-D semiconductor material layer.

In some embodiments, the gate structure includes a gate dielectric layer extending to top surfaces of the first and second conductive contacts.