MULTI-DIE PANEL-LEVEL HIGH PERFORMANCE COMPUTING COMPONENTS

Panel-level high performance computing (HPC) computing architectures and methods for making the same are disclosed. Panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. Local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. Coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer can have interconnect structures and a local interconnect component. Panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. Panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.

BACKGROUND

As the technological challenges of high-performance computing (HPC) continue to rise, heterogeneous integration scaling has become an important performance enabler. Heterogeneous integration scaling can include components having an increased amount of die, increased interconnect density, increased bandwidth, and improved power efficiency. Accordingly, many different advanced packaging architecture solutions have been deployed.

DETAILED DESCRIPTION

As the technological challenges of high-performance computing (HPC) continue to rise, heterogeneous integration scaling has become an important performance enabler. Heterogeneous integration scaling can include increased interconnect density, increased number of integrated circuit dies per package, increased bandwidth, and improved power efficiency. Accordingly, many different advanced packaging architecture solutions have been deployed to increase planar and three-dimensional (3D) input/output (I/O) wire and area density for higher data bandwidth requirements, and to enable more effective die disaggregation and heterogeneous integration to shorten the time to market. Other technical solutions to the challenges of HPC include 2.5D/3D advanced packaging technologies, such as die embedding and/or employing local interconnect components to provide interconnects between dies (e.g., silicon (Si) interposers or bridges) to enable significantly higher packaged integrated circuit die and I/O counts and density to meet the HPC segment market demands and product performance needs.

Applications that depend on extremely high-performance computing include those that are expected to perform on the order of one zettaflops (1021floating point operations per second). These applications may be referred to as zettascale performance applications. Non-limiting examples of zettascale performance applications include supercomputing, autonomous driving, and machine learning. Realizing platforms capable of zettascale performance presents technological challenges and packaging and system-level architecture innovations are expected to be developed to realize this level of performance. Proposed technical solutions include system-level heterogeneous integration of compute, I/O, memory, power management, and thermal management components. Some available high-performance computing solutions include implementing system-level architectures on a wafer (also referred to as wafer-level system integration, or a wafer-level solution). However, wafer-level system integration incurs several technical challenges. As may be appreciated, wafer-level system integration has packages that are limited in size by the diameter of a wafer. In addition, wafer-level system integration puts one entire system on one wafer; therefore, resolving yield issues for wafer-level solutions may become very challenging.

Embodiments disclosed herein propose a technical solution to the above-described technical problems, in the form of panel-level components (referred to herein individually as a “panel”) and systems comprising the panels or panel-level components. Embodiments of a panel may comprise multiple components (e.g., integrated circuit components) assembled using panel-level manufacturing techniques. As used herein, the term “panel-level” manufacturing techniques refer to manufacturing techniques in which integrated circuit dies are assembled and interconnections between them are formed on a single substrate and/or carrier, creating an overall structure. If the overall structure comprises multiple panels, the overall structure is singulated into individual panels. The overall structure can be packaged (by, for example, overmolding) before singulation or individual panels can be packaged after singulation. In an application, one or more of the panels may be assembled to create a multi-panel structure or panel assembly, as is described in more detail below. Individual panels (as well as multi-panel structures or components) may have an area that is less than, equal to, or larger than, the area of a wafer upon which any of the individual integrated circuit dies of a panel may have been formed.

Embodiments include various panel architectures. The panel architectures comprise interconnect structures (e.g., conductive traces, vias) to route die-level signals to package-level signals and local interconnects to route signals between integrated circuit dies. Some panel architectures comprise a glass layer (or glass core) with dielectric layers located on one or both sides of the glass layer. Other panel architectures do not contain a glass layer. The dielectric layers (along with the glass layer in some embodiments) comprise the interconnects structures. Panel architectures containing and not containing a glass layer can be referred to herein as “core” and “coreless” architectures, respectively. Some panel architectures, including coreless architectures, are assembled upon a glass carrier that provides mechanical stiffness and a flat surface upon which a panel can be fabricated. One benefit of the mechanical stiffness that a glass carrier (or glass reinforcement layer) can provide is limiting the amount of warpage that a panel can undergo during manufacture or in the field. Some panel architectures assembled on a glass carrier can comprise a layer of glass (also referred to herein as a glass reinforcement layer) to provide additional mechanical stiffness to the panel. The thickness of the glass reinforcement layer can be thinner that the glass layer used in core panel architectures. Thus, panels manufactured on a glass carrier and having a glass reinforcement layer can be thinner than other panels having a glass layer and not manufactured using a glass carrier.

The provided panel architectures offer several technological and economic advantages, a first being design support for a panel-level solution with a larger area than available wafer-level (300 mm in diameter wafer-size) solutions; whereas wafer-level integration may limit a packaged HPC solution to an area of about 215 millimeters (mm)×215 mm, in some embodiments, individual panels disclosed herein can reach an area in a range of about 250 mm×250 mm to about 600 mm×600 mm, and in other embodiments, individual panels can exceed an area of 600 mm by 600 mm. Additionally, a single panel can provide a panel-level HPC solution; however, in other embodiments, the individual panels can further be assembled into a larger HPC solution, such as that illustrated inFIG.1.

Other non-limiting examples of advantages of the provided panel architectures include support for design redundancy (by creating a multi-die structure by assembling smaller known good dies (KGDs)), additional mechanical stiffness and capacity for fine pitch geometries supported by the glass reinforcement layer, interconnect structures for die-to-die or chiplet-to-chiplet communication within panels, cavities in the glass reinforcement layer to accommodate discrete device integration (e.g., discrete devices such as deep trench capacitors, capacitors, transistors, magnetic inductor arrays (MIAs), inductors, etc.), flexible thermal management, and flexibility for vertical integration of integrated circuit dies and other components into the panel. Additionally, embodiments may use a glass carrier to provide improved flatness and mechanical stiffness to panels during manufacture and assembly. These concepts are developed in more detail below.

Example embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements. Figures are not necessarily to scale but may be relied on for spatial orientation and relative positioning of features. As may be appreciated, certain terminology, such as “ceiling” and “floor”, as well as “upper,”, “uppermost”, “lower,” “above,” “below,” “bottom,” and “top” refer to directions based on viewing the Figures to which reference is made. Further, terms such as “front,” “back,” “rear,”, “side”, “vertical”, and “horizontal” may describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated Figures describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

As used herein, the term “adjacent” refers to layers or components that are in direct physical contact with each other, with no layers or components in between them. For example, a layer X that is adjacent to a layer Y refers to a layer that is in direct physical contact with layer Y. In contrast, as used herein, the phrase(s) “located on” (in the alternative, “located under,” “located above/over,” or “located next to,” in the context of a first layer or component located on a second layer or component) includes (i) configurations in which the first layer or component is directly physically attached to the second layer (i.e., adjacent), and (ii) component and configurations in which the first layer or component is attached (e.g. coupled) to the second layer or component via one or more intervening layers or components.

Terms modified by the word “substantially” include arrangements, orientations, spacings, or positions that vary slightly from the meaning of the unmodified term. For example, the portion of a first layer or feature that is substantially perpendicular to a second layer or feature can include a first layer or feature that is +/−20 degrees from a second layer or feature, a first surface that is substantially parallel to a second surface can include a first surface that is within several degrees of parallel from the second surface. The amount of variation covered by a term modified by the term “substantially” is indicated throughout for certain arrangements, orientations, spacing, positions, etc. Values modified by the word “about” include values with +/−10% of the described values and values listed as being within a range include those within a range from 10% less than the described lower range limit and 10% greater than the described higher range limit.

As used herein, the term “electronic component” can refer to an active electronic circuit (e.g., processing unit, memory, storage device, FET) or a passive electronic circuit (e.g., resistor, inductor, capacitor).

As used herein, the term “integrated circuit component” can refer to an electronic component configured on a semiconducting material to perform a function. An integrated circuit (IC) component can comprise one or more of any computing system components described or referenced herein or any other computing system component, such as a processor unit (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I/O controller, memory, or network interface controller, and can comprise one or more additional active or passive devices such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

A non-limiting example of an unpackaged integrated circuit component includes a single monolithic integrated circuit die (shortened herein to “die”); the die may include solder bumps attached to contacts on the die. When present on the die, the solder bumps or other conductive contacts can enable the die to be directly attached to a printed circuit board (PCB) or other substrates.

A non-limiting example of a packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate with the integrated circuit dies and package substrate encapsulated in a casing material, such as a metal, plastic, glass, or ceramic. Often the casing includes an integrated heat spreader (IHS); the packaged integrated circuit component often has bumps, leads, or pins attached to the package substrate (either directly or by wires attaching the bumps, leads, or pins to the package substrate) for attaching the packaged integrated circuit component to a printed circuit board (or motherboard or base board) or another component.

The following detailed description is not intended to limit the application and use of the disclosed technologies. It may be evident that the novel embodiments can be practiced without every detail described herein. For the sake of brevity, well-known structures and devices may be shown in block diagram form to facilitate a description thereof.

Embodiments of the provided panel architecture are directed to solving technical issues faced by providing applications with HPC or zettascale performance using panels. In some embodiments, an HPC solution can comprise a single panel of the provided architecture. In other examples, such as illustrated inFIG.1, an HPC solution is achieved with a panel assembly100comprising multiple panels of the provided panel architecture assembled.

In the non-limiting example inFIG.1, panel assembly100comprises four panels (panel102, panel104, panel106, and panel108) assembled, the individual panels may be referred to as “sub-panels,” or “panel quads” or “quarter-panels,” in the case where four panels are assembled to form the panel assembly100. However, the panel assembly100may comprise more or less than four panels and panels arranged in any fashion (e.g., square (e.g., 2×2, 4×4, 6×6), rectangular (e.g., 2×4, 3×5, 4×7)). The panels of the panel assembly100may be attached to a panel-level substrate112. The panel-level substrate112may comprise a printed circuit board, thin-film substrate, or another suitable substrate. In various embodiments and HPC solutions, either an individual panel or the entire panel assembly100can be overmolded with an encapsulant110. The encapsulant110can comprise molding compound, dielectric materials, metal, ceramic, plastic, or a combination thereof.

In various embodiments, individual panels of the panel assembly100may have an area (e.g., a top-down x-y area with reference to the directional axes illustrated inFIG.1), in a range of about 250-300 millimeters×250-300 millimeters. In other embodiments, individual panels of the panel assembly100may have an area in a range of about 450-600 millimeters×450-600 millimeters, or greater. That is, a lateral dimension of a panel (a dimension of the panel orthogonal to the panel's thickness) can be 250-300 mm in some embodiments and 450-600 mm in other embodiments. The individual panels may be smaller or larger in other embodiments. For example, in some embodiments, the lateral dimension of a panel is greater than 250 mm.

Blocks drawn inside each of the panels indicate separate unpackaged integrated circuit dies (e.g., die114, die116, die118, and die120). The unpackaged integrated circuit dies (die114, die116, die118, and die120) may also be referred to as chips, chiplets, chip complexes, or chiplet complexes. While the terms die, chip, and chiplet may be used interchangeably, the term chiplet is sometimes used to refer to an integrated circuit die that implements a subset of the functionality of a larger integrated circuit component, the larger integrated circuit component formed using one or more chiplets connected by inter-die interconnects (e.g., interposers, bridges, local interconnect components, local silicon interconnects). The use of chiplets in integrated circuit components has become attractive as feature sizes have reduced and the demand for high-performance larger integrated circuit components has increased. The approach of assembling multiple known-good dies (chiplets) to form a larger integrated circuit component results in improved manufacturing efficiencies as the overall yield of an integrated circuit component assembled from multiple small chiplets is better than that of an integrated circuit component in which the functionality of the chiplets is implemented on a single large integrated circuit die. Any integrated circuit die, chip, or chiplet can implement any portion of the functionality of any processor unit described or referenced herein.

Although the illustration depicts the chiplets within and among the panels as having uniform dimensions, in practice, chiplet dimensions (lateral dimensions and thickness) and shape can vary among chiplets within a panel and across panels; moreover, the chiplets on a given panel may vary by type/functionality (e.g., compute, memory, I/O, power management (controlling the delivery of power and/or providing power to components)). In the non-limiting example, each of the panels includes 12 dies arranged in an array of 4×3, however other numbers of dies per panel, and other arrangements of dies within a panel are supported. Additionally, the integrated circuit component die area and die height within a given panel may vary. Furthermore, a panel can have any shape, such as a substantially non-circular shape (e.g., substantially square shape, substantially rectangular shape (such as panels102,104,106,108)) or substantially circular shape.

As is described in more detail below, in some embodiments, the panel assembly100may be co-packaged with other electronic components or optical interconnects or waveguides and may support a photonic integrated circuit (PIC) attached or connected to a panel therein. In some embodiments, the other electronic components or PICs may be located external to a panel, such as indicated by location122. In other embodiments, a panel of the panel assembly may have its substrate etched with waveguides and may further include one or more other electronic components or PICs in a keep-out zone of the panel, for example, such as indicated by location124of panel108.

A panel may take the form of a populated or unpopulated panel substrate. Both populated and unpopulated panel substrates are configured (e.g., with appropriate pinouts) to communicatively couple associated integrated circuit die to each other (e.g., via fine pitch redistribution layer, conductive traces, or a local interconnect component, such as a bridge illustrated inFIG.4A).

Cutout line A-A′ provides a reference for intra-panel (i.e., within a panel) architecture discussions in connection withFIGS.2,3,5,6, and13-25. Cutout line B-B′ provides a reference for inter-panel (i.e., between panels) architecture discussions, such as creating a panel assembly, referenced again inFIG.9.

FIG.2provides a simplified cross-sectional illustration of a portion200of a panel as a reference for a general panel architecture discussion, and embodiments illustrated inFIGS.3-9and13-25provide technological improvements to the general panel architecture ofFIG.2, with additional and/or alternative features. Accordingly, many of the components fromFIG.2are reproduced inFIGS.3-9and13-25as is observable with a comparison of shapes, locations, and context.

For example, interconnect structures (vias, conductive traces)228,328,428,528,628,728,828,1328,2228, etc. are analogous; build-up layers (or, alternatively, redistribution layers (RDL) or dielectric layers)222,322,422,522,622,722,822,1322,2222, etc. are analogous; build-up, dielectric or redistribution layers224,324,424,524,624,724,824,1324,2224, etc. are analogous; conductive pads (or contacts)232,332,532,632,1332,2232, etc. are analogous; conductive contacts226,326,526,626,1326,2226, etc. are analogous; upper surface contact layers256,356,1356,2256are analogous; lower surface contact layers260,360,1360,2260are analogous; thermal management solutions209,960,962,1409,1509,2309, are analogous; glass reinforcement layers350,550,650, etc. are analogous; glass cores1351,1451,1551, etc. are analogous; interconnect structures in the form of through-glass vias352,552,652,1352, etc. are analogous, solder resist or dielectric materials212,312,512,612,1312,2212, etc. are analogous; solder resist or dielectric material218,318,518,618,1318,2218, etc. are analogous; micro-channels668,1968,2068, etc., are analogous; local interconnect components234,334,434,534,634,1434,2334,2434, etc., are analogous; waveguides564,1664,2464, etc. are analogous, photonic integrated circuits562,1662a,1662b,1762a,1762b,2462,2562, etc. are analogous, FAUs1621a,1621b,1721a,172b,2421, and2521etc. are analogous, and so on. Further, persons with skill in the art will appreciate that, although some object numbers are omitted in some figures to simplify clutter, objects sharing a same shape, location, and/or context with labeled objects in other figures are analogous (e.g., comprise a same material, have a same dimension, possess a same property).FIGS.3-7and13-25focus on (intra-panel) panel architectures for unpopulated panels andFIGS.8-9describe populating and packaging the panels.

As used herein, “pitch” means the physical distance at which a feature is repeated (e.g., the space from the center of one instance of a feature to the center of an adjacent instance of the feature). For example, on surface203, conductive contacts226have a pitch240and on surface205, conductive pads232have a pitch242.

As used herein “fine pitch” generally means a die-scale pitch, as indicated on surface203, and “coarse pitch” generally means a package-level pitch, as indicated on surface205. Fine pitch dimensions may include a range of about 0.001 mm to about 0.3 mm. In some embodiments, features having a fine pitch have dimensions of about 1 μm (micron) or less. In other embodiments, features having a fine pitch may have dimensions of about 0.5 μm or less. In addition to the conductive contacts that are used to attach integrated circuit dies to a panel, other features in a panel that can have a fine pitch include the vias in one or more RDLs adjacent to the pinouts for integrated circuit dies. Fine pitch geometries are smaller than “coarse pitch” geometries.

As indicated on surface205, “coarse pitch”242generally refers to geometries associated with package-level conductive pads332(or contacts332); the coarse pitch may be a ball grid array (BGA) pitch or a land grid array (LGA) pitch. In various embodiments, a BGA pitch is in a range of about 0.1 mm to about 1 mm, and LGA pitch is in a range of about 0.1 mm to about 1 mm. Additionally, as is generally represented in the Figures, the thickness of conductive traces of RDLs adjacent to the package-level conductive contacts or conductive pads332at surface205may be thicker than the conductive traces in RDLs adjacent to the pinout for integrated circuit dies at surface203.

In some embodiments, the pitch at surface203is smaller than the pitch at surface205, and in some embodiments, the pitch at surface203is the same as the pitch at surface205. Conductive contacts226and conductive pads232can comprise solder, copper, or another suitable metal or other material.

Build-up layers or redistribution layers (RDLs) (e.g.,222,322,422,522,622,722, and822) are referred to herein. Although the figures illustrate two RDL222sub-layers and two RDL224sub-layers, in practice, there can be any number of RDL sub-layers. For example, in server applications, an RDL can comprise up to 10 sub-layers. In various embodiments, an RDL comprises a dielectric material and may include a suitable nitride or oxide, such as silicon dioxide (SiO2), carbon-doped silicon dioxide (C-doped SiO2, also known as CDO or organosilicate glass, which is a material that comprises silicon, oxygen, and carbon), fluorine-doped silicon dioxide (F-doped SiO2, also known as fluorosilicate glass, which is a material that comprises fluorine, silicon, and oxygen), hydrogen-doped silicon dioxide (H-doped SiO2, which is a material that comprises silicon, oxygen, and hydrogen). In some embodiments, an RDL comprises a photo-imagable dielectric (PID). In some embodiments, an RDL comprises an Ajinomoto Build-Up film (often referred to as ABF), which is a material that comprises an organic resin matrix with different types of fillers (for example, silica fillers of different sizes, or hollow fillers of different sizes) to control the coefficient of thermal expansion (CTE) and/or electrical properties of the RDLs (e.g., the dielectric constant (Dk), and/or dissipation factor (insertion loss) (Df)).

In some embodiments, it is advantageous for the RDLs to have a CTE that matches that of integrated circuit dies (e.g., match the CTE of silicon) attached to a panel substrate. In some embodiments, the dielectric material of an RDL can have a CTE that is close (e.g., within 10%) to that of silicon. In other embodiments, the dielectric material of an RDL can be any type of epoxy molding compound. RDLs or build-up layers may include a metal layer comprising conductive traces (or metal lines), metals used for interconnect metals in the RDL include copper or other suitable metal.

Local interconnect components and interconnect structures are referred to herein. As used herein, local interconnect components refer to separately manufactured components that route signals between dies within a panel. In comparison, an external interconnect component could be used to route signals between panels. As used herein, “interconnect structures” can comprise one or more conductive traces, one or more vias, or a combination thereof. The term conductive trace can refer to via contacts, which can be metal lines to which vias connect to and do not comprise a lateral signal routing portion. Interconnect structures can be present in various RDLs, dielectric layers, build-up layers, or glass layers, and can span multiple such layers. Interconnect structures may collectively provide an electrically conductive path from a feature on a first surface203of a panel substrate201to a feature on a second surface205of the panel substrate. In various embodiments, an interconnect structure in a first dielectric layer is attached to an interconnect structure in a second dielectric layer, thereby providing an electrically conductive path through the substrate.

Portion200relates to cutout line A-A′ and includes a substrate201. The substrate201may have a thickness210that is in a range of substantially 0.05 mm to substantially 3 mm, wherein substantially equals +/−10%), and may comprise one or more build-up or redistribution layers214,216,218, and220. Region202, a column on the left of the page, provides signal communication and translation routing (e.g., translating the fine pitch die-level signals to coarser pitch panel-level signals) for die or chiplet204attached at an upper surface203, and on the right, region206provides signal communication and translation routing for die or chiplet208attached at the upper surface203. A solder resist or other dielectric material212on the upper substrate surface may be patterned with a respective pinout (physical arrangement of conductive contacts226at a respective pitch) for individual of one or more chiplets that are part of the portion200. The respective pinouts may comprise individual conductive contacts226arranged as conductive contacts for individual chiplet or die (e.g., die204and die208). In some embodiments, the conductive contacts226are arranged in an upper surface contact layer256as two distinguishable sets with the same pitch (e.g., a die pitch, or fine pitch), however, in other embodiments, the conductive contacts226are arranged as two sets that do not have the same die pitch or fine pitch. Further, the conductive contacts associated with one die may be arranged with more than one pitch. Some signal routing may occur from at least one conductive contact of the first set of conductive contacts226(e.g., die204) to at least one conductive contact of the second set of conductive contacts226(e.g., die208), via the local interconnect component234. Some of the vias228bcan be arranged with a fine pitch to match the pitch of the conductive contacts226.

In various embodiments, RDL222comprises features (e.g., interconnect structures comprising metal lines and vias) having a finer pitch than the pitch of features in RDL224. Thus, RDLs222and224can be considered to translate the tighter pitch of the die pads (that match the pitch of conductive pads226) to the greater pitch of the panel pads (that match the pitch of the conductive pads232). Although RDL222is depicted as comprising two layers, RDL214and RDL216, and RDL224is depicted as comprising two layers, RDL218and RDL220, in practice the number of layers in RDL222and RDL224may vary. Persons with skill in the art may appreciate that the distinctions in the various dielectric or build-up layers attributed to RDL222and RDL224in this discussion have been introduced for illustrative purposes; in a cross-sectional image of the substrate201, such as by a transmission electron microscope (TEM), the layers212,214,216,218, and220may be indistinguishable.

For illustrative purposes, the RDL222comprises interconnect structures228and the RDL224comprises interconnect structures230. The interconnect structures228may be arranged within the RDL214and216to route electrical signals according to a wide variety of applications; in particular, the arrangement is not limited to the configuration of interconnect structures228depicted inFIG.2. In some embodiments, the interconnect structures228may include conductive traces or metal lines (lines) and/or via contacts228aand vias228b. The conductive traces, via contacts, and vias can comprise an electrically conductive material such as a metal (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or combinations thereof). The lines of interconnect structures228amay be arranged to route electrical signals along the surface of a plane that is substantially parallel with the surface203of the substrate201. For example, the lines of interconnect structure228amay route electrical signals in a direction in and out of the page and/or in a direction across the page. The vias228bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate201. Likewise, the interconnect structures230may include conductive traces or lines and/or via contacts230aand or vias230bcomprising an electrically conductive material such as a metal (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or combinations thereof). The lines of interconnect structures230amay be arranged to route electrical signals in a direction that is substantially parallel with the surface203of the substrate201. For example, the lines230amay route electrical signals in a direction in and out of the page and/or in a direction across the page. The vias230bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate201.

Local interconnect component234functions to communicatively couple chiplets204and208. Substrate201may be a portion of a product that is either populated or unpopulated. In various populated embodiments, the components indicated in region290, attached at the upper surface203of the substrate201, may be present. For example, a populated panel substrate may be populated with respective die or chiplets (e.g.,204,208), which may be attached via conductive die bumps238or any solder or hybrid bonding (the bonding of components through bonding (direct attachment) of interconnects and dielectric layers of the components). In some embodiments, a polymer can be used to bond copper conductive contacts (e.g., pads) on the die to copper conductive contacts (e.g.,226) of a panel substrate. In some embodiments, a polymer can also be used to bond solder conductive contacts on the die to solder conductive contacts on a panel substrate. In some embodiments, an inorganic material (e.g., silicon dioxide, silicon nitride) can be used to bond copper conductive contacts of components together. In some embodiments, dies are attached to the substrate201through direct attachment of bumps (e.g., microbumps) attached to both surfaces (e.g., die surface, panel surface). In some embodiments, the chiplets also have underfill applied (not shown) underneath the chiplets and above the surface of the substrate201. A large form factor thermal management solution236comprising a cooling component such as a vapor chamber, heat pipe, heat sink, or liquid-cooled cold plate may be implemented. The thermal management solution is a large form factor solution in that it can be a panel-level thermal management solution (providing cooling to integrated circuit dies of a panel) or a multi-panel thermal management solution (providing cooling to integrated circuit dies of multiple panels). As part of a thermal management solution, a thermal conduction layer interface material (TIM) may be located over the die204,208. The TIM can be any suitable material, such as a silver particle-filled thermal compound, thermal grease, phase change materials, indium foils, or graphite sheets. The thermal management solution can be a conformal solution that accommodates differences in heights of the integrated circuit dies for which the thermal management solution provides cooling. For example, a thermal management solution can comprise a substantially planar cooling component with TIMs of varying thickness between the cooling component and the integrated circuit dies. In another example, the cooling component is non-planar and the profile of the cooling component can vary with the thickness of the integrated circuit dies for which the cooling component provides cooling. In such embodiments, the TIM can be of substantially uniform thickness between the cooling component and the integrated circuit dies of varying thicknesses. Thermal management solutions can also include an integrated heat spreader.FIG.9provides examples of panels with thermal management solutions.

Turning now toFIG.3, an embodiment of the provided panel architecture includes a glass reinforcement layer between dielectric layers or RDLs of the substrate. The simplified cross-sectional illustration of a portion300relates to cutout line A-A′ and includes a substrate301. Substrate301comprises a glass reinforcement layer350sandwiched between dielectric layer or RDL322and dielectric layer or RDL324. In various embodiments, an overall height of the substrate is unchanged (e.g., substantially210,FIG.2) and the RDL322and324are thinned or omitted to accommodate the glass reinforcement layer350, which has a height/thickness380in a range of about 30 microns to 1.5 millimeters, +/−10%. By analogy with objects inFIG.2, RDL322may comprise multiple build-up layers, dielectric layers, or redistribution layers, and RDL324may comprise multiple build-up layers, dielectric layers, or redistribution layers. Also, by analogy, solder resist or other dielectric material312may be patterned with a pinout for respective one or more chiplets that may be attached to the substrate of the panel. The pinout may comprise individual conductive contacts326arranged at a fine pitch, and upper surface contact layer356may also take the form of other embodiments (e.g.,726a,726b), as described in connection withFIG.7. Lower surface contact layer360may also take the form of other embodiments (e.g.,760), as described in connection withFIG.7. Also as mentioned, vias/contacts/traces/pads328,330,360, and332are analogous to counterparts228,230,260, and232. Local interconnect component334is analogous to local interconnect component234. Region302is dedicated to a first die and region306is dedicated to a second die.

Glass reinforcement layer350may comprise glass, (as used herein, glass can be an alkali-free alkaline earth boro-aluminosicilate glass, such as a glass comprising aluminum, oxygen, boron, silicon, and an alkaline-earth metal (e.g., beryllium, magnesium, calcium, strontium, barium, radium, such as a glass comprising SiO2, Al2O3, B2O3, and MgO), or a photosensitive glass (photomachineable or photostructurable glass). In some embodiments, a photosensitive glass can be a glass that belongs to the lithium-silicate family of glass (e.g., a glass comprising lithium, silicon, and oxygen) comprising metallic particles, such as gold, silver, or other suitable metallic particles. Glass reinforcement layer350may comprise multiple glass sheets (in the non-limiting example, three glass sheets,350-1,350-2, and350-3, are illustrated).

Glass reinforcement layer350may contain some or all the interconnect structures to support the signal routing from the contacts326at the die surface (303) of the substrate301to the conductive pads332. The interconnect structures can include vias352in the glass layer350, which may be referred to as through-glass vias (TGVs). The interconnect structures, collectively, provide an electrically conductive path from a feature on a first surface303of a panel substrate301to other features on the first surface303, and/or to the conductive pads332. Individual glass sheets350-1,350-2, and350-3may have a respective dielectric layer (351-1,351-2,351-3) located on a lower surface thereof, to act as an adhesion layer to laminate the glass sheet over/on a layer354of solder resist or dielectric having conductive contacts358and traces therein. While one with skill in the art may appreciate that, in practice, “layer” and “sheet” may be used interchangeably, these concepts are employed here to aid in understanding the embodiment.

In various embodiments, a thickness362of the glass sheets350-1,350-2,350-3may be substantially in a range of 20-150 microns, wherein substantially means +/−5%. In some embodiments, the thickness of any of the glass sheets can be different from that of any other glass sheets in a glass layer. In various embodiments, the dielectric layers351may comprise Ajinomoto Build-up Film (ABF), an epoxy molding compound, any other dielectric layer referenced or described herein, or any other suitable dielectric material. In various embodiments, the dielectric layers351can be substantially 10 microns thick.

A local interconnect component334in the glass reinforcement layer350facilitates communication between two or more chiplets in a portion of a substrate, a panel, and/or a panel assembly100. A local interconnect component334may comprise an interposer (or bridge), or one or more redistribution layers (RDLs). Local interconnect components334can be selectively located in a substrate. That is, in a panel comprising two dies that are connected by a local interconnect component (e.g.,334), the panel can further comprise adjacent dies that are not connected by local interconnect components.

FIG.4Aillustrates a simplified cross-sectional illustration of a first example local interconnect component.FIG.4Ais a simplified cross-sectional illustration of a portion400of a panel substrate comprising RDL422and a first glass sheet450that is a part of a glass layer of the panel. The glass layer450can be a glass reinforcement layer (e.g.,350,550,650) or a glass layer that is part of the glass core in the embodiments inFIGS.13-21. The RDL422comprises two constituent layers (sub-layers)422aand422b. A local interconnect component434(or bridge) is located in the glass sheet450and provides interconnections between a first die attached to conductive contacts406and a second die connected to conductive contacts408(first and second die not shown).

Bridge conductive contacts476are located on a surface474of the local interconnect component434. In various embodiments, the bridge conductive contacts476comprise copper. Local interconnect component434comprises conductive traces480a,480b,480c, and480dlocated in first, second, third, and fourth dielectric layers492,494,496, and498, respectively. The dielectric layers492,494,496, and498further comprise vias478providing connections between conductive traces in different dielectric layers or between a conductive trace and a bridge conductive contact476.

Bridge vias478and bridge conductive traces480may comprise copper or another suitable conductive material and provide electrically conductive paths between the bridge conductive contacts476. The dielectric layers492,494,496,498, and422can be a suitable nitride or oxide, such as silicon dioxide (SiO2), carbon-doped silicon dioxide, fluorine-doped silicon dioxide, hydrogen-doped silicon dioxide, or silicon nitride.

The interconnect structures in the RDL422(conductive traces428aand vias428b) are analogous to interconnect structures328aand328band provide electrically conductive paths from the bridge conductive contacts476to conductive contacts406for a first die or chiplet and to conductive contacts408for a second die or chiplet. Vias452provide a connection from RDL interconnect structures to the bridge conductive pads476. In embodiments where the top surface474of the local interconnect component434is flush with a top surface of the top glass sheet within a glass layer (e.g., surface483), vias452may not be present.

In some embodiments, a region located in one or more dielectric layers above a local interconnect component can comprise interconnect structures that provide an electrically conductive path between dies attached to a panel substrate. For example, a region487in the dielectric layer422comprises conductive traces428cand vias428dproviding an electrically conductive path between one of the conductive contacts406and one of the conductive contacts408. In other embodiments, the region above a local interconnect component does not contain routing that provides an electrically conductive path between adjacent dies. Together, conductive contacts and traces/vias406,428a,428b,428c,428d,452,476,478,480a, and480b, provide electrically conductive paths between the first and second dies, and thus allow the die to be communicatively coupled.

In the example, two of the vias478connect conductive trace480bto480cand480cto bridge pad480d, which in turn is connected to via428eand conductive trace428flocated within the glass layer450. Thus, the local interconnect component434can also provide electrically conductive paths between the first and second dies to conductive traces in the glass layer located below the local interconnect component434.

FIG.4Bis a simplified cross-sectional illustration of a second example local interconnect component. Local interconnect component435comprises a through-silicon via (TSV)452. TSV452provides an electrically conductive path from an interconnect structure (via452) positioned adjacent to the top surface474of the local interconnect component435and an interconnect structure (via454) positioned adjacent to a bottom surface484of the local interconnect component435. In various embodiments, TSVs can comprise copper, tungsten, or another metal.

FIG.4Bfurther illustrates a trench capacitor456located in the local interconnect component435. The trench capacitor456comprises a first terminal (one or more first capacitor conductive traces)458, a second terminal (one or more second capacitor conductive traces)458, and a capacitor dielectric459positioned between the first terminal457and the second terminal458. The first and second terminals457and458comprise one or more conductive traces oriented substantially perpendicular to a top surface of the panel substrate (e.g., upper surface203) in which the local interconnect component435is located. The capacitor dielectric459can comprise any of the dielectrics disclosed herein (e.g., doped or undoped silicon dioxide, silicon nitride) or any other suitable dielectric. The first and second terminals457and458are further connected to conductive traces486of the local interconnect component that allow for connection to the capacitor456by interconnect structures external to the local interconnect component435(e.g., via452). In addition to trench capacitors, a local interconnect component can comprise other types of capacitors, such as planar capacitors.

FIGS.4C and4Dare cross-sectional and top illustrations of a third example local interconnect component. Local interconnect component437comprises a magnetic inductor array (MIA)475. MIA475comprises pads477, vias479, and conductive traces481. The conductive traces481act as inductors and are surrounded by a ferromagnetic material491. The conductive traces481can comprise copper or another suitable metal, the pads477can comprise nickel, palladium, and gold or another suitable metal or alloy, and the ferromagnetic material491can comprise iron or an iron alloy. In some embodiments, the ferromagnetic material491comprises iron or iron alloy microparticles in an epoxy matrix.

In addition to TSVs, capacitors, and inductors (e.g., MIAs), in other embodiments, the local interconnect component434can comprise other passive components, such as resistors and/or active components, such as transistors.

As mentioned above, a local interconnect component located in a panel substrate (such as local interconnect component434embedded within portion400of a panel substrate) can be implemented as a silicon interposer (interposer) or a local silicon interconnect (local interconnect). In some embodiments, the local interconnect component can be an Intel® Embedded Multi-Die Interconnect Bridge (EMIR). In some embodiments, the local interconnect component can be compliant with a Universal Chiplet Interconnect express (UCIe) standard.

Local interconnect components can be manufactured separately from a panel substrate, and then located in, integrated into, or embedded within, the panel substrate. The separate manufacture of a local interconnect component allows for the use of semiconductor manufacturing techniques to create the local interconnect component, thereby creating local interconnect components with internal features (e.g., vias, pads, conductive traces) with geometries (e.g., via width/space, conductive trace width/space/thickness) that can be smaller than the geometries of similar features external to the local interconnect component in a panel substrate.

A local interconnect component can be located in a panel substrate through the formation of a cavity in a panel substrate (e.g., formation of a cavity in a glass layer and/or one or more dielectric layers) at a point during panel manufacture, insertion of the local interconnect component within the panel substrate, and formation of the remainder of the panel substrate. A local interconnect component can be located in a glass layer or one or more RDLs. A local interconnect component can span more than one RDL. An upper surface of an RDL can be flush with an upper surface on an RDL, including an upper surface of an RDL that is part of an upper surface of a panel surface. As such, the phrase “located in” in the context of a local interconnect component located in a glass layer or one or more RDLs can refer to a local interconnect component that is entirely embedded (a glass layer or one or more RDLs are positioned adjacent to all sides of the local interconnect component) or partially embedded (a glass layer or one or more RDLs are positioned adjacent to less than all sides of the local interconnect component).

In some embodiments, a local interconnect providing electrically conductive paths between adjacent die in a panel can be provided by interconnect structures that are part of the one or more RDL layers that provide routing of die-level signals to package-level signals. That is, adjacent die in a panel can be interconnected without the use of a separately manufactured local interconnect component placed in a panel substrate during panel manufacture. Region487inFIG.4A, region1387inFIG.13, region1687inFIG.16, region1987inFIG.19, region2287inFIG.22, and region2487inFIG.24illustrate such local interconnects.

With reference toFIG.5, in various embodiments, the panel assembly100may implement waveguide routing and/or a silicon photonics component, such as a photonic integrated circuit (PIC). The simplified cross-sectional illustration of a portion500relates to cutout line A-A′ and includes a substrate501.FIG.5illustrates a photonic integrated circuit (PIC)562implemented in the panel architecture of portion500of a panel substrate501, implemented directly in the glass reinforcement layer550. The associated waveguide routing564of the PIC562and out of the substrate501can also be implemented directly in the substrate501, also directly in the glass reinforcement layer550.

In these embodiments, the waveguide routing564may be fabricated by laser direct writing in a glass sheet of the glass reinforcement layer550. In an embodiment, a waveguide routing564is an enclosed path formed or etched in the glass reinforcement layer550, having a first end565and a second end567. The waveguide routing564is configured to passively allow light of a specific wavelength or a range of wavelengths to travel therethrough. That is, in operation, the waveguide routing564provides operable communication by receiving light from a first source (such as the PIC562) at the first end565, and passively transmitting the light to the second end567, where it may exit the waveguide routing564(alternatively, the light may travel in the opposite direction through the waveguide routing). In some embodiments, as illustrated, the waveguide routing564has a first end565in operable communication with a PIC562and a second end567at a surface of the glass reinforcement layer. In various embodiments, as illustrated, the second end567may be at a vertically oriented surface, with respect toFIG.5, and in other embodiments, the second end567may be at a laterally oriented surface, with respect toFIG.5. In various embodiments, there may be an optional optical coupling component569added to the surface at the second end567, for attaching an external component to the waveguide routing564. Although indicated inFIG.5as a straight line, in practice, the waveguide routing564may be implemented as a pattern in two or three dimensions, having a uniform diameter and an overall path length that may include curves and/or loops, wherein the overall path length (generally from first end565to second end567) reflects a specific application.

In some embodiments, the waveguide routing564can comprise a dielectric material that has a higher permittivity, and thus a higher index of refraction, than that of the material surrounding the waveguide routing (the glass reinforcement layer550). In some embodiments, the waveguide comprises silicon and oxygen. In some embodiments, a waveguide can comprise a photonic-crystal fiber, a hollow tube with a reflective inner surface (e.g., polished metal or a multilayer film that guides light by Bragg reflection), or small prisms around a hollow pipe that reflects light via internal reflection.

Photonic integrated circuits implement one or more photonic functions and comprise one or more optical components, such as waveguides, lasers, electro-optical modulators, polarizers, photodetectors, and the like. PICs are often used in data communications (such as fiber-optic communication) and sensing applications. Examples of uses for PICs include wavelength division multiplexing (WDM), interferometers, wave modulators, optical transceivers, light detection and ranging (LiDAR) antennas, and the like.

A non-limiting example of an optical component that can be included in a PIC is a silicon micro-ring resonator (MRR), generally referred to herein as a ring resonator structure. The ring resonator structure is a passive structure generally including (i) a compact circular micro-ring structure comprising an optical silicon waveguide that is looped back on itself with a small bend radius to resonate at one or more frequencies referred to as a spectral response, or free spectral range (FSR), and (ii) a linear silicon waveguide located proximate to the micro-ring structure and communicating therewith.

In various embodiments, the micro-ring structure is substantially circular, and the silicon waveguide is substantially linear (i.e., +/−10%) from a circle and +/−10% from linear. In some embodiments, the micro-ring structure may have an oval shape or a shape of a racing track. In some embodiments, the silicon waveguide may include a curve in a region alongside the micro-ring structure, to enhance the coupling effect between the silicon waveguide and the micro-ring structure. In some embodiments of the ring resonator structure, the ring resonator structure further includes an optional second silicon waveguide that is also linear.

In some embodiments, the micro-ring structure may comprise silicon. In some embodiments, the micro-ring structure may comprise a lightly-doped P region, lightly-doped N region, highly-doped P+ region, highly-doped N+ region, intrinsic silicon and silicon dioxide (as a divider between different Si doping regimes when needed). An optics component, such as a PIC, can be embedded within a panel substrate through formation of a cavity in the panel substrate at a point during panel manufacture, insertion of the optics component within the panel substrate, and formation of the remainder of the panel substrate.

When the PIC562is implemented, the number of glass sheets (e.g., individual glass sheets550-1,550-2, and550-3) may be informed by a thickness of the PIC562. For example, for a PIC having a thickness in a range of 300 microns to 1 millimeter, the glass reinforcement layer550should equal the thickness of the PIC, therefore, an associated number of glass layers may be in a range of three to ten.

A non-limiting way to identify a PIC may include visually inspecting both the materials present in a cross-sectional view and the structure and shape of the materials to determine that a ring resonator structure has been implemented. Although, in various embodiments, the ring resonator structure may comprise the same materials as an electronic integrated circuit (e.g., a CMOS (complementary metal-oxide-semiconductor) component), the structure of the ring resonator structure, and its shape employ different doping profiles than a CMOS component. Various embodiments of the ring resonator structure may have a thickness (on a cross-sectional view) of about 220 nanometers.

As shown inFIG.5, in various embodiments, an optional local interconnect component534may also be present in the glass reinforcement layer550. The integration of local interconnect components (e.g.,534) and PICs (e.g.,562) into the glass reinforcement layer of a panel are independent of each other. That is, a panel can comprise one or more local interconnect components and/or one or more PICs.

The waveguide routing564may enable an embedded PIC562to communicate with a fiber array unit (FAU) connector located external to a panel. The FAU connector may be a top side connector, such as a grating coupler, or an edge connector, such as a micro-lens or V-groove. With reference back toFIG.1, in various panel assembly100embodiments, an FAU may be implemented in a panel architecture, e.g., within panel108at location124(see, e.g.,FIG.9, FAU910), or external to a panel, but within the panel assembly, e.g., at location122. Any of the panels or panel assemblies here can have multiple PICs and multiple FAUs.

As illustrated inFIG.6, embodiments of the panel architecture may employ cavities and/or micro-channels in the glass reinforcement layer. The simplified cross-sectional illustration of a portion600relates to cutout line A-A′ and includes a substrate601. Micro-channels668can be added to the glass reinforcement layer650to assist in removing heat from the components of the panel. Micro-channels668are another example of an enclosed pathway formed in the glass reinforcement layer650. Micro-channels668can comprise lateral portions668-1and668-2and a vertical portion668-3. In some embodiments, micro-channel lateral portions are formed on the surface of a glass layer (or glass sheet) by, for example, etching or laser cutting, and micro-channel vertical portions are formed by, for example, drilling through a glass layer (or glass sheet). In some embodiments, micro-channel vertical portions can comprise a through-glass vias of an appropriate diameter to facilitate the flow of a liquid coolant. In other embodiments, lateral portions of the micro-channels668can be located in the interior of a glass layer. The micro-channel vertical portion668-3extends through more than one glass sheet (through650-1and650-2and into650-3). In an embodiment, a micro-channel lateral portion (e.g.,668-2) can be located near a set of conductive contacts, where “near” means at a surface of a glass reinforcement layer located below the conductive contacts. One may appreciate that, although the illustration ofFIG.6is in two dimensions, a three-dimensional characteristic of the design/configuration of the micro-channels668is indicated; for example, lateral portion668-2traverses in front of two TGVs652and behind one TGV652.

Some embodiments have cavities added into the glass reinforcement layer650to act as a pool or a reservoir for a liquid coolant. A cavity,671, when present, may reside in the glass reinforcement layer, and, similar to the micro-channels668, the cavity671may be etched or laser cut into the surface of a glass sheet. In other embodiments, the cavity may be formed in the interior of the glass layer. In embodiments implementing a cavity671and micro-channels668, the micro-channels668may be configured to use the flow of the liquid coolant in a cavity to extract heat from the glass reinforcement layer650. Accordingly, the micro-channels668may have a diameter that is a function of a selected liquid coolant (e.g., water, alcohol, glycol), in that the diameter is selected to accommodate movement of the selected liquid coolant in the anticipated operating temperature of a die located near the micro-channels668. The glass in the glass reinforcement layer650can provide a hermetic seal around the micro-channels668for the liquid coolant flowing closest to a respective die, enhancing cooling functionality for a die.

Substrate601illustrates an optional local interconnect component634, implemented in the glass reinforcement layer650, as described in connection with other embodiments. However, other embodiments of the substrate601and/or resulting panel do not necessarily comprise the optional local interconnect component634. Said differently, a panel can comprise cavities671and/or micro-channels668, without local interconnect components634.

A panel can comprise one or more ports (e.g., at673) to allow for connection to an external liquid-cooled thermal management solution to cool the panel, e.g., by controlling fluid flow into/out of micro-channels668. In various embodiments, the liquid-cooled thermal management solution can comprise a heat exchanger to remove heat from heated liquid coolant exiting the panel, the liquid coolant having absorbed heat generated by the die on the panel, a pump to provide for the circulation of the coolant through the micro-channels, and conduits to connect the panel, heat exchanger, and pump. A liquid-cooled thermal management solution can cool multiple panels. Further, a liquid-cooled thermal management solution can be co-located in the same system as the panel cooled by the liquid-cooled thermal management solution or located external to the system in which the panel is located. For example, in a rack-scale solution, a liquid-cooling thermal management solution can cool panel components located in multiple systems located within a rack. Panels employing micro-channels and cavities may or may not have a large form factor thermal management solution attached to the top of the panel. That is, panels may provide for the removal of heat generated by dies within the panel by thermal management solutions located both below (cavities and/or micro-channels) and above (e.g., a thermal management solution such as a liquid-cooled, vapor chamber, heat fins) the dies.

In manufacturing, embodiments of the panel architecture can be populated and packaged using various techniques. InFIG.7, embodiment700illustrates a solder resist or dielectric layer712having conductive pads726therein, to which solder balls702may be attached at a first or fine pitch, to have die or chiplets attached thereto. In embodiment720, a solder resist or dielectric layer712is shown having pockets706etched therein, to which solder balls708are placed in advance of attaching a die or chiplet. Notably, the pockets706have a tapered wall, being wider at an upper opening and narrower where the pocket meets the conductive contacts. Similarly, the bottom surface of the panel architecture can have exposed second level interconnect (SLI) or conductive contacts732are arranged in a solder resist or dielectric layer718at a greater pitch than the pitch of the conductive contacts, or a BGA or land grid array (LGA) pitch. Solder balls710may be attached to the SLI or conductive contacts732. The examples inFIG.7are non-limiting.

Moving toFIGS.8-9, an example process flow for the panel architecture is provided. The illustrations inFIG.8-9relate to cutout B-B′, in that, chips (chiplets) 1-3 are part of a first panel (“panel 1” inFIG.9, generally analogous to panel106), and chips (chiplets) 4-5 are part of a second panel (“panel 2” inFIG.9, generally analogous to panel108). The process flow illustrated inFIGS.8-9can be used for the embodiments described above in connection withFIGS.3,5-6, and21-25, accordingly, some intra-panel architecture features, such as local interconnect components, are indicated for chips 1-3 and separately for chips 4-5, although, to simplify the drawings, micro-channels and cavities are not depicted. The sequence of operations described in the process flow is non-limiting, operations may be performed in a different order, and operations may be added or subtracted without altering the final product. At a point in manufacturing and packaging, panel 1 and panel 2 will be singulated or cut (at859) apart.

At800, a glass carrier806is employed to build a plurality of panels thereon. The glass carrier806is used to provide a mechanically stiff surface for depositing the respective build-up layers or RDL and solder resist, performing etching, depositing copper or other conductive trace and pad materials, and building up the glass reinforcement layer850, to achieve a panel substrate architecture as described herein. The glass carrier806can also provide a level of flatness that may not be achievable with other types of substrates, such as printed circuit boards comprising organic substrate materials. The flatness provided by a glass carrier can enable the formation of smaller feature sizes (e.g., via width/space, conductive contact width/space), thus enabling the formation of conductive contacts, vias, and other features with a fine pitch. The glass carrier806has an area that is at least the same size as the area of a single panel described herein and may be, for example, 510 mm×515 mm, or larger or smaller as required. The glass carrier806may be an alkali-free alkaline earth boro-aluminosicilate glass, such as a glass comprising aluminum, oxygen, boron, silicon, and an alkaline-earth metal (e.g., beryllium, magnesium, calcium, strontium, barium, radium), such as a glass comprising SiO2, Al2O3, B2O3, and MgO, or a photosensitive glass. The glass carrier806may have a thickness in a range of 0.5 to 2 mm, +/1 10%.

On an upper surface803of the panel architecture (analogous with upper surface203,303,503, and603), conductive contacts808are arranged to attach respective chips or die at locations802-1,802-2,802-3,802-4, and802-5. Conductive contacts808are arranged at a suitable pitch for the respective die to attach (e.g., “die pitch”), therefore, a pitch for conductive contacts at location802-1may be different from a pitch for conductive contacts808at location802-2, and so on. In various embodiments, the conductive contacts808are attached at a fine pitch for a first level interconnect (FLI) with respective die.

Optional embedded structures, such as local interconnect components804-1,804-2, and804-3may be formed at this stage of packaging. Optional cavities671and micro-channels668may be etched at this stage. Additionally, optional waveguides may be etched, and photonics integrated circuits may be embedded at this stage (e.g.,FIG.9, PIC906, waveguides908). Although not depicted for clarity of illustrations, RDL interconnect structures may be implemented directly above local interconnect components.

At835, respective integrated circuit dies, or chips may be attached to (i.e., assembled onto) the panel substrate, as illustrated. As described above, the chips (chip 1, chip 2, chip 3, chip 4, and chip 5) may implement different functionalities, have different heights, have different arrangements of pins (pinouts), have different lateral dimensions, and/or may take up different amounts of cross-sectional area within a panel. Different panels can the same or different numbers of chips. The assembly at835may be referred to as fine-pitch assembly is performed. At835, any soldering technique or hybrid bonding technique may be employed. Various of the chips may be assembled onto the panel substrate using underfill812; and although the underfill812is depicted as uniform, in practice, underfill for individual chips may be different (e.g., underfill under chip 1 may be different from underfill from chip 2, and so on). The embodiment at835may be referred to as a populated panel substrate.

At855, the glass carrier806may be debonded or removed from the populated panel substrate, and the panel substrate may be cut into respective panels (e.g., the four panel quads described initially), as indicated by dashed line859). At855, solder balls857may be attached via a second level interconnect or conductive contacts832at the lower surface, and mechanical contact enabling, such as for LGA attaching, may be performed. Alternatively, solder balls857may be added before cutting the populated panel substrate into respective panels.

Depicted at900, respective large form factor thermal solutions960and962may be added to the individual populated panel substrates (panel 1 and panel 2), and, in various embodiments, an underfill964and966can be added, respectively, under the large form factor thermal solutions960and962. Co-packaged integrated circuit components, such as the FAU910, may be added at930.

Depending on the embodiment, an encapsulant972may be applied/overmolded over the panels, as is illustrated at930for panel 1. At930, in a non-limiting example, the FAU910may be attached to PIC906via waveguide908, becoming part of the panel 2. In other embodiments, co-packaged integrated circuit components may be located external to the panel, above the panel, or vertically stacked with the panel.

In some embodiments, at930, a single packaged multi-die panel (e.g., panel 1) with the herein provided panel architecture is a complete HPC solution for an application. In other embodiments, multiple panels are assembled into a panel assembly, such as panel assembly100ofFIG.1. Embodiment950generally reflects cutout B-B′, illustrating panel 1 and panel 2 assembled onto a panel-level substrate970. The panel-level substrate970can comprise one or more layers, with each layer comprising inorganic or organic dielectric materials (such as any of the dielectric materials disclosed or referenced herein), one or more conductive traces, and one or more vias. The substrate970can provide electrically conductive paths between panels. For example, substrate970comprises conductive traces973and vias974of two substrate layers providing conductive paths connection between conductive contacts976of panel 1 to conductive contacts978of panel 2. The resulting panel assembly at950may provide a complete HPC solution for an application, or the panel assembly from950may further be assembled with other components to provide a complete HPC solution.

FIG.10is an example first method of forming a panel. At1004in a method1000, a first dielectric layer is formed on a glass carrier, the glass carrier having a cross-sectional area of at least 250 millimeters×250 millimeters, the first dielectric layer comprising conductive pads arranged at a first pitch. At1008, a glass layer is formed on the first dielectric layer, the glass layer comprising a local interconnect component. At1012, a second dielectric layer is located on the glass layer, the second dielectric layer comprising conductive contacts arranged at a second pitch, the conductive contacts further arranged into a first set and a second set, the local interconnect component to provide electrical communication between a first conductive contact in the first set and a first conductive contact in the second set. At106, an interconnect structure is located in the glass layer, the interconnect structure to provide electrical communication between a second conductive contact of the first set and one of the conductive pads.

FIG.11is an example second method of forming a panel. At1104a first dielectric layer is formed on a glass carrier, the glass carrier having a cross-sectional area of at least 250 millimeters×250 millimeters, the first dielectric layer comprising conductive pads arranged at a first pitch. At1108, a glass layer is formed on the first dielectric layer, the glass layer comprising a photonic integrated circuit (PIC). At1112, a second dielectric layer is located on the glass layer, the second dielectric layer comprising conductive contacts arranged at a second pitch, the conductive contacts further arranged into a first set and a second set. The PIC is configured to be in electrical communication with a first conductive contact in the first set or the second set. At1116, an interconnect structure is located in the glass layer, the interconnect structure to provide electrical communication between a second conductive contact of the first set and one of the conductive pads.

FIG.12is an example third method of forming a panel. At1204, a first dielectric layer is formed on a glass carrier, the glass carrier having a cross-sectional area of at least 250 millimeters×250 millimeters, the first dielectric layer comprising conductive pads arranged at a first pitch. At1208, a glass layer is formed on the first dielectric layer, the glass layer comprising a micro-channel. At1212, a second dielectric layer is located on the glass layer, the second dielectric layer comprising conductive contacts arranged at a second pitch, the conductive contacts further arranged into a first set and a second set. The micro-channel is configured to have a portion near the first set. At1216, an interconnect structure is located in the glass layer, the interconnect structure to provide electrical communication between a conductive contact of the first set and one of the conductive pads.

The sequence of elements in methods1000,1100, and1200are non-limiting. Operations of the methods may be performed in a different order and operations may be added or subtracted without altering the final product. For example, any of the methods1000,1100, and1200can further comprise attaching a first die to the first set; and attaching a second die to the second set, thereby creating a populated substrate. In a second example, any of the methods1000,1100, and1200can further comprise debonding the glass carrier from the populated substrate; and forming solder bumps on the conductive pads.

FIGS.13-21illustrate simplified cross-sectional views of various “core” panel embodiments in which the panel substrate comprises a glass core. The cross-sectional views relate to the cutout line A-A′ ofFIG.1. The dielectric layers are located on an upper surface of the glass core (between the integrated circuit dies and the glass core) or on upper and bottom surfaces of the glass core. The glass core provides similar functions (signal routing, mechanical stability during manufacture, flat surfaces upon which dielectric layers may be formed) and possesses similar properties (can be comprised of the same material, has a coefficient of expansion close to that of the integrated circuit dies attached to the panel) as the glass reinforcement layer ofFIGS.3,5-6, but as the panel embodiments illustrated inFIG.13-21are not assembled on a glass carrier, the glass cores ofFIGS.13-21can be thicker than the glass reinforcement layers ofFIGS.3,5-6.

FIG.13is a simplified cross-sectional illustration of an example panel substrate portion comprising a glass core. The panel portion1300comprises a glass core1351positioned between a first set of dielectric layers (RDLs, build-up layers)1322(1322a,1322b,1322c,1322d) and a second set of dielectric layers1324(1324a,1324b). The first set of dielectric layers1322are stacked vertically and the second set of the dielectric layers1324are stacked vertically. That is, the individual first dielectric layers1322(e.g.,1322a) are positioned adjacent to another first dielectric layer1322(e.g.,1322b) and the individual second dielectric layers1324(e.g.,1324a) are positioned adjacent to another second dielectric layer1324(e.g.,1324b). The glass core1351comprises a layer of glass1354, encapsulation layers1370and1372, and through-glass vias (TGVs)1352located in the layer1354. The glass core1351has a thickness1380. The encapsulation layers1370and1372comprise dielectric layers1374in which TGV contacts1376are located.

An upper surface contact layer1356comprises a solder resist or other suitable dielectric material1312and conductive contacts1326arranged to correspond to the pinouts of chiplets to be attached to the panel portion1300. The upper surface contact layer1356(and hence, the conductive contacts1326) are located on a top dielectric layer (e.g.,1322a) of the first dielectric layers1322. A set of conductive contacts1326are arranged at a fine pitch. A lower surface contact layer1360comprises a solder resist or other suitable dielectric material1318and conductive contacts1332are arranged to correspond to a desired panel-level pinout. The lower surface contact layer1360(and hence, the conductive contacts1332) is located on a bottom dielectric layer (e.g.,1324b) of the second dielectric layers1324. The set of the conductive contacts1332is arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts1326are arranged.

Dielectric layers1322comprise conductive traces1328aand vias1328b, and dielectric layers1324comprise conductive traces1330aand vias1330b. A local interconnect comprising vias1328band conductive traces1328aincluded in region1387provides an electrically conductive path between a conductive contact1326belonging to a first set of conductive contacts1364to be attached to a first integrated circuit die and a conductive contact1326belonging to a second set of conductive contacts1366to be attached to a second integrated circuit die.

Vias1328band1330bare shown as being tapered, with the narrower ends of the vias located closer to the glass core1351than the wider ends of the vias. These tapers reflect that dielectric layers1322and1324are built up from the glass core1351and that when individual dielectric layers1322and1324are etched to form via holes, they are etched toward the glass core1351. Vias in the dielectric layers of the other panel embodiments comprising a glass core (e.g., vias1428b,1430b,1528b,1530b,1628b,1630b) are similarly tapered.

FIG.14is a simplified cross-sectional illustration of an example panel assembly comprising a panel comprising a glass core and a local interconnect component located in a set of dielectric layers of the panel. The panel assembly1400comprises a panel1403, integrated circuit components1405and1407attached to the panel1403, and a thermal management solution1409. The panel1403comprises a glass core1451positioned between a first set of dielectric layers1422(1422a,1422b,1422c,1422d) and a second set of dielectric layers1424(1424a,1424b). The first set of dielectric layers1422and the second set of dielectric layers1424are stacked vertically. The glass core1451comprises a layer of glass1454, encapsulation layers1470and1472, and through-glass vias (TGVs)1452located in the glass layer1454. The glass core1451has a thickness1480. The encapsulation layers1470and1472comprise dielectric layers1474in which TGV contacts1476are located.

An upper surface contact layer1456comprises a solder resist or other suitable dielectric material1412and conductive contacts1426arranged to correspond to the pinouts of dies1404and1408directly attached to the panel1403. The upper surface contact layer1456(and hence, the conductive contacts1426) is located on a top dielectric layer (e.g.,1422a) of the first dielectric layers1422. A set of the conductive contacts1426are arranged at a fine pitch. A lower surface contact layer1460comprises a solder resist or other suitable dielectric material1418and conductive contacts1432are arranged to correspond to a desired panel-level pinout. The lower surface contact layer1460(and hence, the conductive contacts1432) is located on a bottom dielectric layer (e.g.,1424b) of the second dielectric layers1424. The set of conductive contacts1432is arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts1426are arranged.

Dielectric layers1422comprise conductive traces1428aand vias1428b, and dielectric layers1424comprise conductive traces1430aand vias1430b. A local interconnect component1434provides electrically conductive paths between conductive contacts1426connected to the die1404and a first packaged integrated circuit component1492and conductive contacts1426connected to the die1408and a second packaged integrated circuit component1407.

The integrated circuit dies1404and1408are attached to the panel substrate1401at conductive contacts1426via solder balls1438. In other embodiments, the dies1404and1408can be attached to the panel substrate via other approaches, such as hybrid bonding. The panel1403further comprises solder balls1410attached to the panel substrate1401at conductive contacts1432. In other embodiments, the panel1403does not comprise solder balls1410and the package can attach to other components, such as a printed circuit board, via conductive contacts1432that are pads. The packaged panel1403further comprises an encapsulant1498that enclosed the dies1404and1408and the panel substrate1401.

The integrated circuit components1405and1407are attached to the panel1403via a package-on-package assembly technology in which solder balls1411of the integrated circuit components1405and1407are attached to the through-package vias1415extending through the encapsulant1498and attaching to conductive contacts1426. Panel assembly1400illustrates just one example of how packages can be attached to a packaged panel. Integrated circuit components can be attached to a packaged panel via different approaches in other embodiments.

FIG.15is a simplified cross-sectional illustration of an example panel comprising a glass core with a local interconnect component located in the glass core. The panel1500comprises integrated circuit dies1504a,1504b,1504c,1504d, and1508attached to the panel either directly or indirectly, and a thermal management solution1509. The panel1500comprises a glass core1551positioned between a first set of vertically stacked dielectric layers1522(1522a,1522b,1522c,1522d) and a second set of vertically stacked dielectric layers1524(1524a,1524b). The glass core1551comprises a layer of glass1554, encapsulation layers1570and1572, and through-glass vias (TGVs)1552located in the glass layer1554. The glass core1551has a thickness1580. The encapsulation layers1570and1572comprise dielectric layers1574in which TGV contacts1576are located.

An upper surface contact layer1556comprises a solder resist or other suitable dielectric material1512and conductive contacts1526arranged to correspond to the pinouts of dies1504aand1508directly attached to the panel substrate1501. The upper surface contact layer1556(and hence, the conductive contacts1526) is located on a top dielectric layer (e.g.,1522a) of the first dielectric layers1522. A set of the conductive contacts1526is arranged at a fine pitch. A lower surface contact layer1560comprises a solder resist or other suitable dielectric material1518and conductive contacts1532are arranged to correspond to a desired panel-level pinout. The lower surface contact layer1560(and hence, the conductive contacts1532) is located on a bottom dielectric layer (e.g.,1524b) of the second dielectric layers1524. The set of conductive contacts1532is arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts1526are arranged.

Dielectric layers1522comprise conductive traces1528aand vias1528b, and dielectric layers1524comprise conductive traces1530aand vias1530b. A local interconnect component1534located in the glass layer1554of the glass core1551provides an electrically conductive path between one of the conductive contacts1526connected to the die1504aand one of the conductive contacts connected to the die1508.

The integrated circuit dies1504aand1508are attached to the panel substrate1501at conductive contacts1526via solder balls1538. In other embodiments, the dies1504aand1508can be attached to the panel substrate via other approaches, such as hybrid bonding. The panel1500further comprises solder balls1510attached to the panel substrate1501at conductive contacts1532. In other embodiments, the panel1500does not comprise solder balls1510and the panel can attach to other components, such as a printed circuit board, via conductive contacts1532that are pads.

The integrated circuit dies1504a,1504b,1504c, and1504dare stacked vertically and connected by solder bumps (or microbumps)1519that connect to through-silicon vias (TSVs)1517that extend through dies1504cand1504d. TSVs can comprise copper, carbon nanotubes, graphene nanotubes, or another suitable material. The stacked die1504a-dcan implement various functionality, and in one embodiment, die1504acan be a high bandwidth memory (HBM) controller die that controls HBM dies1504b-d. In other embodiments, die1504acan comprise TSVs1517that connect to conductive contacts1526. Panel1500illustrates one example of how a panel can accommodate vertically stacked integrated circuit dies. Integrated circuit components can be attached panel via different approaches in other embodiments.

FIG.16is a simplified cross-sectional illustration of an example panel comprising a glass core and photonic integrated circuits. The panel1600comprises integrated circuit dies1604and1608, a glass core1651positioned between a first set of vertically stacked dielectric layers1622(1622a,1622b,1622c,1622d), a second set of vertically stacked dielectric layers1624(1624a,1624b), photonics integrated chips1622aand1622b, and a thermal management solution1609. The glass core1651comprises a layer of glass1654, encapsulation layers1670and1673, and through-glass vias (TGVs)1652located in the glass layer1654. The glass core1651has a thickness1680. The encapsulation layers1670and1672comprise dielectric layers1674in which TGV contacts1676are located.

An upper surface contact layer1656comprises a solder resist or other suitable dielectric material1612and conductive contacts1626arranged to correspond to the pinouts of dies1604and1608directly attached to the panel1600. The upper surface contact layer1656(and hence, the conductive contacts1626) is located on a top dielectric layer (e.g.,1622a) of the first dielectric layers1622. A set of the conductive contacts1626is arranged at a fine pitch. A lower surface contact layer1660comprises a solder resist or other suitable dielectric material1618and conductive contacts1632are arranged to correspond to a desired panel-level pinout. The lower surface contact layer1660(and hence, the conductive contacts1632) is located on a bottom dielectric layer (e.g.,1624b) of the second dielectric layers1624. The set of conductive contacts1632are arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts1626are arranged.

Dielectric layers1622comprise conductive traces1628aand vias1628b, and dielectric layers1624comprise conductive traces1630aand vias1630b. A local interconnect comprising vias1628band conductive traces1628aincluded in region1687provides an electrically conductive path between a conductive contact1626attached to die1604and a conductive contact1626attached to die1608.

The integrated circuit dies1604and1608are attached to conductive contacts1626via solder balls1638. In other embodiments, the dies1604and1608can be attached to the conductive contacts1626via other approaches, such as hybrid bonding. The panel1600further comprises solder balls1610attached to conductive contacts1632. In other embodiments, the panel1600does not comprise solder balls1610and the package can attach to other components, such as a printed circuit board, via conductive contacts1632that are pads.

The panel1600comprises photonic integrated circuits (PICs)1662aand1662b. The PICs1662aand1662bare located on the glass layer1654. PIC1662aand1662bare attached to conductive contacts1626associated with dies1604and1608, respectively. The PICs are integrated into the panel1600during panel manufacture and are thus considered to be part of the panel1600. Waveguides1664aand1664bare located in the glass layer1654and are also fabricated during panel manufacture and are thus also considered to be part of the panel1600. Fiber array units1621aand1621bare attached to the panel1600with waveguide1664aproviding a path for optical communication for optical signals to be generated or received by the PIC1662aor the FAU1621aand waveguide1664bproviding a path for optical communication for optical signals to be generated or received by the PIC1662bor the FAU1621b.

FIG.17is a simplified cross-sectional illustration of an example panel comprising a glass core, photonic integrated circuits, and local interconnect component. The panel1700comprises integrated circuit dies1704and1708, a glass core1751positioned between a first set of vertically stacked dielectric layers1722(1722a,1722b,1722c,1722d), a second set of vertically stacked dielectric layers1724(1724a,1724b), and a thermal management solution1709. The glass core1751comprises a layer of glass1754, encapsulation layers1770and1772, and through-glass vias (TGVs)1752located in the glass layer1754. The glass core1751has a thickness1780.

An upper surface contact layer1756comprises a solder resist or other suitable dielectric material1712and conductive contacts1726arranged to correspond to the pinouts of dies1704and1708directly attached to the panel1700. The upper surface contact layer1756(and hence, the conductive contacts1726) is located on a top dielectric layer (e.g.,1722a) of the first dielectric layers1722. A set of the conductive contacts1726are arranged at a fine pitch. A lower surface contact layer1760comprises a solder resist or other suitable dielectric material1718and conductive contacts1732are arranged to correspond to a desired panel-level pinout. The lower surface contact layer1760(and hence, the conductive contacts1732) are located on a bottom dielectric layer (e.g.,1724b) of the second dielectric layers1724. The set of conductive contacts1732is arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts1726are arranged.

Dielectric layers1722comprise conductive traces1728aand vias1728b, and dielectric layers1724comprise conductive traces1730aand vias1730b. A local interconnect component1734provides an electrically conductive path between a conductive contact1726attached to the die1704and a conductive contact attached to the die1708.

The integrated circuit dies1704and1708are attached to conductive contacts1726via solder balls1738. In other embodiments, the dies1704and1708can be attached to the conductive contacts1726via other approaches, such as hybrid bonding. The panel1700further comprises solder balls1710attached to conductive contacts1732. In other embodiments, the panel1700does not comprise solder balls1710and the package can attach to other components, such as a printed circuit board, via conductive contacts1732that are pads.

The panel1700comprises photonic integrated circuits (PICs)1762aand1762b. The PICs1762aand1762bare located on the glass layer1754. PIC1762aand1762bare attached to conductive contacts1726associated with dies1704and1708, respectively. The PICs1762aand1762bare integrated into the panel1700during panel manufacture and are thus considered to be part of the panel1700. Waveguides1764aand1764bare located in the glass layer1754and are also fabricated during panel manufacture and are thus also considered to be part of the panel1700. Fiber array units1721aand1721bare attached to the panel1700with waveguide1764aproviding a path for optical communication for optical signals to be generated or received by the PIC1762aor the FAU1721aand waveguide1764bproviding a path for optical communication for optical signals to be generated or received by the PIC1762bor the FAU1721b.

FIG.18is a simplified cross-sectional illustration of an example panel comprising a glass core, photonic integrated circuits, and local interconnect component located in the glass core. The panel1800comprises integrated circuit dies1804and1808, a glass core1851positioned between a first set of vertically stacked dielectric layers1822(1822a,1822b,1822c,1822d), a second set of vertically stacked dielectric layers1824(1824a,1824b), and a thermal management solution1809. The glass core1851comprises a layer of glass1854, encapsulation layers1870and1872, and through-glass vias (TGVs)1852located in the glass layer1854. The glass core1851has a thickness1880.

An upper surface contact layer1856comprises a solder resist or other suitable dielectric material1812and conductive contacts1826arranged to correspond to the pinouts of dies1804and1808directly attached to the panel1800. The upper surface contact layer1856(and hence, the conductive contacts1826) is located on a top dielectric layer (e.g.,1822a) of the first dielectric layers1822. A set of the conductive contacts1826are arranged at a fine pitch. A lower surface contact layer1860comprises a solder resist or other suitable dielectric material1818and conductive contacts1832are arranged to correspond to a desired panel-level pinout. The lower surface contact layer1860(and hence, the conductive contacts1832) are located on a bottom dielectric layer (e.g.,1824b) of the second dielectric layers1824. The set of conductive contacts1832is arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts1826are arranged.

Dielectric layers1822comprise conductive traces1828aand vias1828b, and dielectric layers1824comprise conductive traces1830aand vias1830b. A local interconnect component1834located in the glass core1851provides an electrically conductive path between a conductive contact1826connected to the die1804and a conductive contact connected to the die1808.

The integrated circuit dies1804and1808are attached to conductive contacts1826via solder balls1838. In other embodiments, the dies1804and1808can be attached to the conductive contacts1826via other approaches, such as hybrid bonding. The panel1800further comprises solder balls1810attached to conductive contacts1832. In other embodiments, the panel1800does not comprise solder balls1810and the package can attach to other components, such as a printed circuit board, via conductive contacts1832that are pads.

The panel1800comprises photonic integrated circuits (PICs)1862aand1862b. The PICs1862aand1862bare located on the glass layer1854. PIC1862aand1862bare attached to conductive contacts1826associated with dies1804and1808, respectively. The PICs are integrated into the panel1800during panel manufacture and are thus considered to be part of the panel1800. Waveguides1864aand1864bare located in the glass layer1854and are also fabricated during panel manufacture and are thus also considered to be part of the panel1800. Fiber array units1821aand1821bare attached to the panel1800with waveguide1864aproviding a path for optical communication for optical signals to be generated or received by the PIC1862aor the FAU1821aand waveguide1864bproviding a path for optical communication for optical signals to be generated or received by the PIC1862bor the FAU1821b.

FIG.19is a simplified cross-sectional illustration of an example panel comprising a glass core with micro-channels and photonic integrated circuits. The panel portion1900comprises a glass core1951positioned between a first set of dielectric layers (RDLs, build-up layers)1922(1922a,1922b,1922c,1922d) and a second set of dielectric layers1924(1924a,1924b). The first set of dielectric layers1922are stacked vertically and the second set of the dielectric layers1924are stacked vertically. The glass core1951comprises a layer of glass1954, encapsulation layers1970and1972, and through-glass vias (TGVs)1952located in the layer1954. The glass core1951has a thickness1980. The encapsulation layers1970and1972comprise dielectric layers1974in which TGV contacts1976are located.

An upper surface contact layer1956comprises a solder resist or other suitable dielectric material1912and conductive contacts1926arranged to correspond to the pinouts of dies1904and1908directly attached to the conductive contacts1926. The upper surface contact layer1956(and hence, the conductive contacts1926) is located on a top dielectric layer (e.g.,1922a) of the first dielectric layers1922. A set of conductive contacts1926is arranged at a fine pitch. A lower surface contact layer1960comprises a solder resist or other suitable dielectric material1918and conductive contacts1932are arranged to correspond to a desired panel-level pinout. The lower surface contact layer1960(and hence, the conductive contacts1932) is located on a bottom dielectric layer (e.g.,1924b) of the second dielectric layers1924. The set of the conductive contacts1932is arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts1926are arranged.

Dielectric layers1922comprise conductive traces1928aand vias1928b, and dielectric layers1924comprise conductive traces1930aand vias1930b. A local interconnect comprising vias1928band conductive traces1928aincluded in region1987provides an electrically conductive path between a conductive contact1926attached to the die1904and a conductive contact1926attached to the die1908.

The integrated circuit dies1904and1908are attached to conductive contacts1926via solder balls1938. In other embodiments, the dies1904and1908can be attached to the conductive contacts1926via other approaches, such as hybrid bonding. The panel1900further comprises solder balls1910attached to conductive contacts1932. In other embodiments, the panel1900does not comprise solder balls1910and the package can attach to other components, such as a printed circuit board, via conductive contacts1932that are pads.

The panel1900comprises photonic integrated circuits (PICs)1962aand1962b. The PICs1962aand1962bare located on the glass layer1954. PIC1962aand1962bare attached to conductive contacts1926associated with dies1904and1908, respectively. The PICs are integrated into the panel1900during panel manufacture and are thus considered to be part of the panel1900. Waveguides1964aand1964bare located in the glass layer1954and are also fabricated during panel manufacture and are thus also considered to be part of the panel1900. Fiber array units1921aand1921bare attached to the panel1900with waveguide1964aproviding a path for optical communication for optical signals to be generated or received by the PIC1962aor the FAU1921aand waveguide1964bproviding a path for optical communication for optical signals to be generated or received by the PIC1962bor the FAU1921b.

As illustrated inFIG.19, in some embodiments, a panel may comprise cavities and/or micro-channels in a glass core. Generally, the inclusion of micro-channels in the glass core of a panel assists in removing heat generated by integrated circuit dies attached to the panel or any heat-generating components located in the panel (such as active components located in a local interconnect component). Micro-channel1968is located in the glass layer1954and can be formed on the surface of the glass layer1954by, for example, etching or laser cutting. In other embodiments, the micro-channel1968can be located in the interior of the glass layer1954. One may appreciate that, although the illustration ofFIG.19is in two dimensions, a three-dimensional characteristic of the design/configuration of the micro-channel1968is indicated by the micro-channel1968being illustrated as traversing in front of several TGVs1952and behind other TGVs1952.

Some panel embodiments with micro-channels can further comprise cavities in the glass core to act as a pool or a reservoir for a liquid coolant. The micro-channels may be configured to use the flow of the liquid coolant in a cavity to extract heat from a glass core. In the panel1900, the glass core1951comprises a cavity1971. The cavity1971may be etched or laser cut into the surface of the glass layer1954. In other embodiments, the cavity may be formed in the interior of the glass layer. A port1973provides for connection to an external liquid-cooled thermal management solution to cool the panel1900, e.g., by controlling fluid flow into/out of micro-channels1968.

FIG.20is a simplified cross-sectional illustration of an example panel comprising a glass core with micro-channels, photonic integrated circuits, and a local interconnect component located in the dielectric layers. The panel2000comprises integrated circuit dies2004and2008, a glass core2051positioned between a first set of vertically stacked dielectric layers2022(2022a,2022b,2022c,2022d), a second set of vertically stacked dielectric layers2024(2024a,2024b), and a thermal management solution2009. The glass core2051comprises a layer of glass2054, encapsulation layers2070and2072, and through-glass vias (TGVs)2052located in the glass layer2054. The glass core2051has a thickness2080.

An upper surface contact layer2056comprises a solder resist or other suitable dielectric material2012and conductive contacts2026arranged to correspond to the pinouts of dies2004and2008directly attached to the panel2000. The upper surface contact layer2056(and hence, the conductive contacts2026) is located on a top dielectric layer (e.g.,2022a) of the first dielectric layers2022. A set of the conductive contacts2026v arranged at a fine pitch. A lower surface contact layer2060comprises a solder resist or other suitable dielectric material2018and conductive contacts2032are arranged to correspond to a desired panel-level pinout. The lower surface contact layer2060(and hence, the conductive contacts2032) is located on a bottom dielectric layer (e.g.,2024b) of the second dielectric layers2024. The set of conductive contacts2032is arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts2026are arranged.

Dielectric layers2022comprise conductive traces2028aand vias2028b, and dielectric layers2024comprise conductive traces2030aand vias2030b. A local interconnect component2034provides an electrically conductive path between a conductive contact2026attached to the die2004and a conductive contact attached to the die2008.

The integrated circuit dies2004and2008are attached to conductive contacts2026via solder balls2038. In other embodiments, the dies2004and2008can be attached to the conductive contacts2026via other approaches, such as hybrid bonding. The panel2000further comprises solder balls2010attached to conductive contacts2032. In other embodiments, the panel2000does not comprise solder balls2010and the package can attach to other components, such as a printed circuit board, via conductive contacts2032that are pads.

The panel2000comprises photonic integrated circuits (PICs)2022aand2022b. The PICs2022aand2022bare located on the glass layer2054. PIC2062aand2062bare attached to conductive contacts2026associated with dies2004and2008, respectively. The PICs2062aand2062bare integrated into the panel2000during panel manufacture and are thus considered to be part of the panel2000. Waveguides2064aand2064bare located in the glass layer2054and are also fabricated during panel manufacture and are thus also considered to be part of the panel2000. Fiber array units2021aand2021bare attached to the panel2000with waveguide2064aproviding a path for optical communication for optical signals to be generated or received by the PIC2062aor the FAU2021aand waveguide2064bproviding a path for optical communication for optical signals to be generated or received by the PIC2062bor the FAU2021b.

The glass core2051comprises a micro-channel2068located in the glass layer2054. The micro-channel2068can be formed on the surface of the glass layer2054by, for example, etching or laser cutting. In other embodiments, the micro-channel2068can be located in the interior of the glass layer2054. One may appreciate that, although the illustration ofFIG.20is in two dimensions, a three-dimensional characteristic of the design/configuration of the micro-channel2068is indicated by the micro-channel2068being illustrated as traversing in front of several TGVs2052and behind other TGVs2052.

The glass core2051further comprises a cavity2071that is connected to the micro-channel2068. The cavity2071may be etched or laser cut into the surface of the glass layer2054. In other embodiments, the cavity may be formed in the interior of the glass layer. A port2073provides for connection to an external liquid-cooled thermal management solution to cool the panel2000, e.g., by controlling fluid flow into/out of micro-channels2068.

FIG.21is a simplified cross-sectional illustration of an example panel comprising a glass core with micro-channels, photonic integrated circuits, and a local interconnect component located in the glass core. The panel2100comprises integrated circuit dies2104and2108, a glass core2151positioned between a first set of vertically stacked dielectric layers2122(2122a,2122b,2122c,2122d), a second set of vertically stacked dielectric layers2124(2124a,2124b), and a thermal management solution2109. The glass core2151comprises a layer of glass2154, encapsulation layers2170and2172, and through-glass vias (TGVs)2152located in the glass layer2154. The glass core2151has a thickness2180.

An upper surface contact layer2156comprises a solder resist or other suitable dielectric material2112and conductive contacts2126arranged to correspond to the pinouts of dies2104and2108directly attached to the panel2100. The upper surface contact layer2156(and hence, the conductive contacts2126) is located on a top dielectric layer (e.g.,2122a) of the first dielectric layers2122. A set of the conductive contacts2126are arranged at a fine pitch. A lower surface contact layer2160comprises a solder resist or other suitable dielectric material2118and conductive contacts2132are arranged to correspond to a desired panel-level pinout. The lower surface contact layer2160(and hence, the conductive contacts2132) is located on a bottom dielectric layer (e.g.,2124b) of the second dielectric layers2124. The set of conductive contacts2132is arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts2126are arranged.

The integrated circuit dies2104and2108are attached to conductive contacts2126via solder balls2138. In other embodiments, the dies2104and2108can be attached to the conductive contacts2126via other approaches, such as hybrid bonding. The panel2100further comprises solder balls2110attached to conductive contacts2132. In other embodiments, the panel2100does not comprise solder balls2110and the package can attach to other components, such as a printed circuit board, via conductive contacts2132that are pads.

The panel2100comprises photonic integrated circuits (PICs)2162aand2162b. The PICs2162aand2162bare located on the glass layer2154. PIC2162aand2162bare attached to conductive contacts2126associated with dies2104and2108, respectively. The PICs are integrated into the panel2100during panel manufacture and are thus considered to be part of the panel2100. Waveguides2164aand2164bare located in the glass layer2154and are also fabricated during panel manufacture and are thus also considered to be part of the panel2100. Fiber array units2121aand2121bare attached to the panel2100with waveguide2164aproviding a path for optical communication between the PIC2162aand the FAU2121aand waveguide2164bproviding a path for optical communication between the PIC2162band the FAU2121b.

The panel2100comprises photonic integrated circuits (PICs)2122aand2122b. The PICs2122aand2122bare located on the glass core2151. PIC2162aand2162bare attached to conductive contacts2126associated with dies2104and2108, respectively. The PICs are integrated into the panel2100during panel manufacture and are thus considered to be part of the panel2100. Waveguides2164aand2164bare located in the glass layer2154and are also fabricated during panel manufacture and are thus considered to be part of the panel2100. Fiber array units2121aand2121bare attached to the panel2100with waveguide2164aproviding a path for optical communication for optical signals to be generated or received by the PIC2162aor the FAU2121aand waveguide2164bproviding a path for optical communication for optical signals to be generated or received by the PIC2162bor the FAU2121b.

The glass core2151comprises a micro-channel2168located in the glass layer2154. The micro-channel2168can be formed on the surface of the glass layer2154by, for example, etching or laser cutting. In other embodiments, the micro-channel2168can be located in the interior of the glass layer2154. One may appreciate that, although the illustration ofFIG.21is in two dimensions, a three-dimensional characteristic of the design/configuration of the micro-channel2168is indicated by the micro-channel2168being illustrated as traversing in front of several TGVs2152and behind other TGVs2152.

The glass core2151further comprises a cavity2171that is connected to the micro-channel2168. The cavity2171may be etched or laser cut into the surface of the glass layer2154. In other embodiments, the cavity may be formed in the interior of the glass layer. A port2173provides for connection to an external liquid-cooled thermal management solution to cool the panel2100, e.g., by controlling fluid flow into/out of micro-channels2168.

The “core” panels and panel assemblies illustrated inFIGS.13-21in which integrated circuit dies are attached to a panel substrate or a panel are merely illustrative. As discussed above, more integrated circuit dies can be attached to or incorporated in a panel or panel assembly than illustrated inFIGS.13-21, and a die attached to a panel can have a lateral dimension, area, height, shape, and/or implement a functionality that is different than that of another die attached to or incorporated in the panel.

The glass core of the embodiments illustrated inFIGS.13-21(e.g., glass core1351,1451,1551) can comprise any glass described or referenced herein or comprise the materials that any of the glasses described or referenced herein layers (e.g., glass reinforcement layers ofFIGS.3,5-6) can comprise. The dielectric layers of the encapsulation layers in the glass core in the embodiments illustrated inFIGS.13-21(e.g., dielectric layers1374,1474,1574) can comprise any dielectric material described or referenced herein. The TGVs in the glass core in the embodiments illustrated inFIGS.13-21(e.g., TGVs1352,1452,1552) can comprise copper or any other suitable metal. In alternative embodiments, a glass core may not comprise TGV contacts (e.g.,1376,1476,1576) and vias in dielectric layers located on either side of the glass core (e.g., vias1328b,1330b,1428b,1430b,1528b,1530b) can attach directly to TGVs.

The upper surface contact layers illustrated inFIGS.13-21(e.g.,1326,1426,1526) can take the form of other upper surface contact layer embodiments, such as those described in connection withFIG.7(e.g.,726a,726b). The lower surface contact layers illustrated in FIGS.13-21(e.g.,1360,1460,1560) can take the form of other lower surface contact layer embodiments, such as those described in connection withFIG.7(e.g., lower surface contact layer embodiment760).

The thermal management solutions illustrated inFIGS.14-21(e.g.,1409,1509,1609) can comprise any cooling component described or referenced herein and be attached to integrated circuit components or integrated circuit dies via thermal interface materials.

The fiber array units illustrated inFIGS.16-21(e.g.,1621a,1621b,1721a,1721b,1821a,1821b) can be attached to a panel during panel manufacture and can be part of an end panel product or be attached to a panel after panel manufacture. Any of the FAUs described or referenced herein can comprise fibers (e.g.,1625,1725,1825) that are part of an optical connection between panels in a system or between panels across different systems.

The micro-channels illustrated inFIGS.19-21(e.g., micro-channels1968,2068,2168) in a glass core layer, the micro-channels can have a diameter that is a function of a selected liquid coolant (e.g., water, alcohol, glycol), in that the diameter is selected to accommodate movement of the selected liquid coolant in the anticipated operating temperature of a die located near the micro-channels. A glass core can provide a hermetic seal around micro-channels for the liquid coolant flowing closest to a respective die, enhancing cooling functionality for a die. Micro-channel ports (e.g.,1973,2073,2173) allow for connection of micro-channels to an external liquid-cooled thermal management solution to cool the panel, e.g., by controlling fluid flow into/out of micro-channels. In various embodiments, the liquid-cooled thermal management solution can comprise a heat exchanger to remove heat from heated liquid coolant exiting the panel, the liquid coolant having absorbed heat generated by the die on the panel, a pump to provide for the circulation of the coolant through the micro-channels, and conduits to connect the panel, heat exchanger, and pump. A liquid-cooled thermal management solution can cool multiple panels.

Further, a liquid-cooled thermal management solution (that comprises micro-channels in a glass core and/or a cooling component attached to one or more integrated circuit components and/or dies attached to a panel or panel assembly) can be co-located in the same system as the panel or panel assembly cooled by the liquid-cooled thermal management solution. In some embodiments, the thermal management solution is located external to the system. For example, in a rack-scale solution, a liquid-cooling thermal management solution can cool panels located in multiple systems within a rack. Panels employing micro-channels and cavities may or may not have a large form factor thermal management solution attached to the top of the panel. That is, panels may provide for the removal of heat generated by dies within the panel by thermal management solutions located both below (cavities and/or micro-channels) and above (e.g., a thermal management solution such as a liquid-cooled, vapor chamber, heat fins) the dies.

The “core” panel embodiments illustrated inFIGS.13-21include various panel features that can be integrated independently into a panel. That is, these panel features are independent of each other and can be mixed and matched to produce “core” panel permutations in addition to those illustrated inFIGS.13-21. These panel features include local interconnects that are integrally formed with the dielectric layers of a panel and provide electrical communication between die in a panel, local interconnect components that are separately manufactured and placed within a panel (either in one or more dielectric layers or a glass core) during panel manufacture and provide electrical communication between die in a panel, PICs, waveguides, vertically stacked packaged or unpackaged dies, and micro-channels (and reservoirs) in the glass core.

FIGS.22-25illustrate simplified cross-sectional views of various “coreless” panel embodiments in which the panel comprises a set of dielectric layers upon which integrated circuit dies are attached but do not comprise a core (such as the glass cores of the “core” panel embodiments). The cross-sectional views relate to the cutout line A-A′ ofFIG.1. Rather than being formed on a core that becomes part of the panel, the dielectric layers in a coreless panel are formed on a glass carrier that provides mechanical stability during panel manufacture and a flat surface enabling the formation of panel features with a fine pitch. The glass carriers used during manufacture are not illustrated inFIGS.22-25. As the coreless panel embodiments do not have a glass core or a glass reinforcement layer, they can be thinner than either of those types of panel embodiments.

FIG.22is a simplified cross-sectional illustration of an example coreless panel. The panel2200comprises integrated circuit dies2204and2208attached to a set of vertically stacked dielectric layers2222, and a thermal management solution2209. An upper surface contact layer2256comprises a solder resist or other suitable dielectric material2212and conductive contacts2226arranged to correspond to the pinouts of dies2204and2208directly attached to the panel2200. The upper surface contact layer2256(and hence, the conductive contacts2226) is located on a top dielectric layer (e.g.,2222a) of the dielectric layers2222. A set of conductive contacts2226are arranged at a fine pitch. A lower surface contact layer2260comprises a solder resist or other suitable dielectric material2218and conductive contacts2232are arranged to correspond to a desired panel-level pinout. The lower surface contact layer2260(and hence, the conductive contacts2232) is located on a bottom dielectric layer (e.g.,2222d) of the dielectric layers2222. The set of the conductive contacts2232is arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts2226are arranged.

Dielectric layers2222comprise conductive traces2228aand vias2228b. A local interconnect comprising vias2228band conductive traces2228aincluded in region2287provides an electrically conductive path between a conductive contact2226attached to integrated circuit die2204and a conductive contact2226attached to second integrated circuit die2208.

The integrated circuit dies2204and2208are attached to conductive contacts2226via solder balls2238. In other embodiments, the dies2204and2208can be attached to the conductive contacts2226via other approaches, such as hybrid bonding. The panel2200further comprises solder balls2210attached to conductive contacts2232. In other embodiments, the panel2200does not comprise solder balls2210and the package can attach to other components, such as a printed circuit board, via conductive contacts2232that are pads.

FIG.23is a simplified cross-sectional illustration of an example coreless panel comprising a local interconnect component. The panel2300comprises integrated circuit dies2304and2308attached to a set of vertically stacked dielectric layers2322, and a thermal management solution2309. An upper surface contact layer2356comprises a solder resist or other suitable dielectric material2312and conductive contacts2326arranged to correspond to the pinouts of dies2304and2308directly attached to the conductive contacts2326. The upper surface contact layer2356(and hence, the conductive contacts2326) is located on a top dielectric layer (e.g.,2322a) of the first dielectric layers2322. A set of the conductive contacts2326are arranged at a fine pitch. A lower surface contact layer2360comprises a solder resist or other suitable dielectric material2318and conductive contacts2332are arranged to correspond to a desired panel-level pinout. The lower surface contact layer2360(and hence, the conductive contacts2332) are located on a bottom dielectric layer (e.g.,2322b) of the dielectric layers2322. The set of conductive contacts2332is arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts2326are arranged.

Dielectric layers2322comprise conductive traces2328aand vias2328b. A local interconnect component2334provides electrically conductive paths between conductive contacts2326attached to the die2304and conductive contacts attached to the die2308.

The integrated circuit dies2304and2308are attached to conductive contacts2326via solder balls2338. In other embodiments, the dies2304and2308can be attached to the conductive contacts2326via other approaches, such as hybrid bonding. The panel2300further comprises solder balls2310attached to the conductive contacts2332. In other embodiments, the panel2300does not comprise solder balls2310and the package can attach to other components, such as a printed circuit board via conductive contacts2332that are pads.

FIG.24is a simplified cross-sectional illustration of an example coreless panel comprising a photonics integrated circuit. The panel2400comprises integrated circuit dies2404and2408attached to a set of vertically stacked dielectric layers2422(1622a,2422b,2422c,2422d), a photonics integrated circuit2462, a waveguide interposer2427, and a thermal management solution2409.

An upper surface contact layer2456comprises a solder resist or other suitable dielectric material2412and conductive contacts2426arranged to correspond to the pinouts of dies2404and2408directly attached to the conductive contacts2526. The upper surface contact layer2456(and hence, the conductive contacts2426) is located on a top dielectric layer (e.g.,2422a) of the dielectric layers2422. A set of the conductive contacts2426are arranged at a fine pitch. A lower surface contact layer2460comprises a solder resist or other suitable dielectric material2418and conductive contacts2432are arranged to correspond to a desired panel-level pinout. The lower surface contact layer2460(and hence, the conductive contacts2432) is located on a bottom dielectric layer (e.g.,2422d) of the dielectric layers2422. The set of conductive contacts2432is arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts2426are arranged.

Dielectric layers2422comprise conductive traces2428aand vias2428b. A local interconnect comprising vias2428band conductive traces2428aincluded in region2487provides an electrically conductive path between a conductive contact2426attached to die2404and a conductive contact2426attached to die2408.

The dies2404and2408are attached to conductive contacts2426via solder balls2438. In other embodiments, the dies2404and2408can be attached to the conductive contacts2426via other approaches, such as hybrid bonding. The panel2400further comprises solder balls2410attached to conductive contacts2432. In other embodiments, the panel2400does not comprise solder balls2410and the package can attach to other components, such as a printed circuit board, via conductive contacts2432that are pads.

Die2404is attached to PIC2462by solder balls2419that are attached to pads2431and2433belonging to the die2404and PIC2462, respectively. Die2404can implement one or more functions, including analog functions implemented with electronic components (such as transistors). In some embodiments, the die2404can control behavior of the PIC and/or act as an interface between the PIC2462and other panel components (e.g., die2408). In the context of communicating with a PIC, the die2404can be referred to as an electronic integrated chip (EIC) and the PIC2462and die2404can together be referred to as a PIC-EIC pair.

The waveguide interposer2427comprises a waveguide2464that provides a path for optical communication for optical signals to be generated or received by the PIC2462or the FAU2421. The waveguide interposer2427can be formed as part of the panel2400during panel assembly.

FIG.25is a simplified cross-sectional illustration of an example coreless panel comprising a photonics integrated circuit and a local interconnect component. The panel2500comprises integrated circuit dies2504and2508attached to a set of vertically stacked dielectric layers2522(2522a,2522b,2522c,2522d), a photonics integrated circuit2562, a waveguide interposer2527, and a thermal management solution2509.

An upper surface contact layer2556comprises a solder resist or other suitable dielectric material2512and conductive contacts2526arranged to correspond to the pinouts of dies2504and2508directly attached to the conductive contacts2526. The upper surface contact layer2556(and hence, the conductive contacts2526) is located on a top dielectric layer (e.g.,2522a) of the dielectric layers2522. A set of the conductive contacts2526are arranged at a fine pitch. A lower surface contact layer2560comprises a solder resist or other suitable dielectric material2518and conductive contacts2532are arranged to correspond to a desired panel-level pinout. The lower surface contact layer2560(and hence, the conductive contacts2532) is located on a bottom dielectric layer (e.g.,2522d) of the dielectric layers2522. The set of conductive contacts2532is arranged at a pitch that is greater than the fine pitch at which a set of the conductive contacts2526are arranged.

Dielectric layers2522comprise conductive traces2528aand vias2528b. A local interconnect component comprising vias2528band conductive traces2528aincluded in region2562provides an electrically conductive path between a conductive contact2526attached to die2504and a conductive contact2526attached to die2508.

The dies2504and2508are attached to conductive contacts2526via solder balls2538. In other embodiments, the dies2504and2508can be attached to the conductive contacts2526via other approaches, such as hybrid bonding. The panel2500further comprises solder balls2510attached to conductive contacts2532. In other embodiments, the panel2500does not comprise solder balls2510and the package can attach to other components, such as a printed circuit board, via conductive contacts2532that are pads.

Die2504is attached to PIC2562by solder balls2519that are attached to pads2531and2533belonging to the die2504and PIC2562, respectively. Die2504can implement one or more functions, including analog functions, implemented with electronic components (such as transistors). In some embodiments, the die2504can control behavior of the PIC and/or act as an interface between the PIC2562and other panel components (e.g., die2508). In the context of communicating with a PIC, the2504can be referred to as an electronic integrated chip (EIC) and the PIC2562and die2504can together be referred to as a PIC-EIC pair.

The waveguide interposer2527comprises a waveguide2564that provides a path for optical communication for optical signals to be generated or received by the PIC2462or the FAU2421. The waveguide interposer2527can be formed as part of the panel2500during panel assembly.

The “coreless” panels and panel portions illustrated inFIGS.22-25are merely illustrative. Again, as previously discussed, more integrated circuit dies can be attached to a panel than illustrated inFIGS.22-25, and a die attached to or incorporated in a panel can have a lateral dimension, area, shape, height, and/or implement a functionality that is different than that of another die attached to or incorporated in the panel.

The upper surface contact layers illustrated inFIGS.22-25(e.g.,2226,2326,2426,2526) can take the form of other upper surface contact layer embodiments, such as those described in connection withFIG.7(e.g.,726a,726b). The lower surface contact layers illustrated inFIGS.22-25(e.g.,2260,2360,2460) illustrated inFIGS.22-25can take the form of other lower surface contact layer embodiments, such as those described in connection withFIG.7(e.g., lower surface contact layer embodiment760).

The thermal management solutions illustrated inFIGS.22-25(e.g.,2209,2309,2409,2509) can comprise any cooling component described or referenced herein and be attached to integrated circuit components or integrated circuit dies via thermal interface materials.

The fiber array units illustrated inFIGS.24-25(e.g.,2421,2521) can be attached to a panel during panel manufacture and can be part of an end panel product or be attached to a panel after panel manufacture. Any of the FAUs described or referenced herein can comprise fibers (e.g.,2425,2525) that are part of an optical connection between panels in a system or between panels across different systems.

The waveguide interposers illustrated inFIGS.24-25(e.g.,2427,2527) can comprise any glass described or referenced herein or comprise the materials that any of the glasses described or referenced herein layers (e.g., glass reinforcement layers ofFIGS.3,5-6) can comprise.

The coreless panel embodiments illustrated inFIGS.22-25include various panel features that can be integrated independently into a panel. The panel features illustrated inFIGS.22-25, along with various other panel features described herein are independent of each other and can be mixed and matched to produce coreless panel permutations in addition to those illustrated inFIGS.22-25. These panel features include local interconnects that are integrally formed with the dielectric layers of a panel and provide electrical communication between dies in a panel, local interconnect components that are separately manufactured and placed within a panel during panel manufacture and provide electrical communication between die in a panel, PICs and waveguide interposers, and vertically stacked packaged or unpackaged dies.

FIG.26is a fourth example method of forming a panel. At2604in the method2600, the following are formed on a glass carrier: a plurality of dielectric layers, individual of the dielectric layers comprising one or more conductive traces and one or more vias; a plurality of first conductive contacts on a top dielectric layer of the dielectric layers; and a plurality of second conductive contacts located on a bottom dielectric layer of the dielectric layers, the first conductive contacts arranged at a first pitch that is less than 100 nm, the second conductive contacts arranged at a second pitch that is greater than the first pitch. At2608, one or more integrated circuit dies are attached to the first conductive contacts. At2612, the glass carrier is removed from the dielectric layers.

The sequence of elements in method2600is non-limiting. Operations of the method2600may be performed in a different order and operations may be added or subtracted without altering the final product. For example, method2600can further comprise etching one or more of the dielectric layers to create a cavity; and locating a bridge in the cavity, the bridge comprising one or more conductive traces and one or more vias.

Various non-limiting embodiments of panel architectures and methods for making the same have been described. The disclosed panel embodiments may enable high performance computing (e.g., zettascale computing) applications using panels that have dimensions exceeding those possible by wafer-level integration. The provided embodiments enable system-level heterogeneous integration of compute, I/O, memory, power management integrated circuit components and dies (which may include vertical stacking of integrated circuit components and dies), and thermal cooling solutions.

FIG.27is a top view of a wafer2700and dies2702that may be included in any of the embodiments disclosed herein. The wafer2700may be composed of semiconductor material and may include one or more dies2702formed on a surface of the wafer2700. After the fabrication of the integrated circuit components on the wafer2700is complete, the wafer2700may undergo a singulation process in which the dies2702are separated from one another to provide discrete “chips” or destined for a packaged integrated circuit component. The individual dies2702, comprising an integrated circuit component, may include one or more transistors (e.g., some of the transistors2840ofFIG.28, discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and/or any other integrated circuit components. In some embodiments, the wafer2700or the die2702may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Additionally, multiple devices may be combined on a single die2702. For example, a memory array formed by multiple memory devices may be formed on a same die2702as a processor unit (e.g., the processor unit3002ofFIG.30) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. In some embodiments, a die2702may be attached to a wafer2700that includes other die, and the wafer2700is subsequently singulated, this manufacturing procedure is referred to as a die-to-wafer assembly technique.

FIG.28is a cross-sectional side view of an integrated circuit2800that may be included in any of the embodiments disclosed herein. One or more of the integrated circuits2800may be included in one or more dies2702(FIG.27). The integrated circuit2800may be formed on a die substrate2802(e.g., the wafer2700ofFIG.27) and may be included in a die (e.g., the die2702ofFIG.27).

The die substrate2802may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The die substrate2802may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate2802may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the die substrate2802. Although a few examples of materials from which the die substrate2802may be formed are described here, any material that may serve as a foundation for an integrated circuit2800may be used. The die substrate2802may be part of a singulated die (e.g., the dies2702ofFIG.27) or a wafer (e.g., the wafer2700ofFIG.27).

The integrated circuit2800may include one or more device layers2804disposed on the die substrate2802. The device layer2804may include features of one or more transistors2840(e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate2802. The transistors2840may include, for example, one or more source and/or drain (S/D) regions2820, a gate2822to control current flow between the S/D regions2820, and one or more S/D contacts2824to route electrical signals to/from the S/D regions2820.

The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor2840is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may comprise a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

The S/D regions2820may be formed within the die substrate2802adjacent to the gate2822of individual transistors2840. The S/D regions2820may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate2802to form the S/D regions2820. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate2802may follow the ion-implantation process. In the latter process, the die substrate2802may first be etched to form recesses at the locations of the S/D regions2820. An epitaxial deposition process may then be conducted to fill the recesses with material that is used to fabricate the S/D regions2820. In some implementations, the S/D regions2820may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions2820may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions2820.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors2840) of the device layer2804through one or more interconnect layers disposed on the device layer2804(illustrated inFIG.28as interconnect layers2806-2810). For example, electrically conductive features of the device layer2804(e.g., the gate2822and the S/D contacts2824) may be electrically coupled with the interconnect structures2828of the interconnect layers2806-2810. The one or more interconnect layers2806-2810may form a metallization stack (also referred to as an “ILD stack”)2819of the integrated circuit2800.

The interconnect structures2828may be arranged within the interconnect layers2806-2810to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures2828depicted inFIG.28. Although a particular number of interconnect layers2806-2810is depicted inFIG.28, embodiments of the present disclosure include integrated circuits having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures2828may include lines2828aand/or vias2828bfilled with an electrically conductive material such as a metal. The lines2828amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate2802upon which the device layer2804is formed. For example, the lines2828amay route electrical signals in a direction in and out of the page and/or in a direction across the page. The vias2828bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate2802upon which the device layer2804is formed. In some embodiments, the vias2828bmay electrically couple lines2828aof different interconnect layers2806-2810together.

The interconnect layers2806-2810may include a dielectric material2826disposed between the interconnect structures2828, as shown inFIG.28. In some embodiments, dielectric material2826disposed between the interconnect structures2828in different ones of the interconnect layers2806-2810may have different compositions; in other embodiments, the composition of the dielectric material2826between different interconnect layers2806-2810may be the same. The device layer2804may include a dielectric material2826disposed between the transistors2840and a bottom layer of the metallization stack as well. The dielectric material2826included in the device layer2804may have a different composition than the dielectric material2826included in the interconnect layers2806-2810; in other embodiments, the composition of the dielectric material2826in the device layer2804may be the same as a dielectric material2826included in any one of the interconnect layers2806-2810.

A first interconnect layer2806(referred to as Metal 1 or “M1”) may be formed directly on the device layer2804. In some embodiments, the first interconnect layer2806may include lines2828aand/or vias2828b, as shown. The lines2828aof the first interconnect layer2806may be coupled with contacts (e.g., the S/D contacts2824) of the device layer2804. The vias2828bof the first interconnect layer2806may be coupled with the lines2828aof a second interconnect layer2808.

The second interconnect layer2808(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer2806. In some embodiments, the second interconnect layer2808may include via2828bto couple the lines2828of the second interconnect layer2808with the lines2828aof a third interconnect layer2810. Although the lines2828aand the vias2828bare structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines2828aand the vias2828bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

The third interconnect layer2810(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer2808according to similar techniques and configurations described in connection with the second interconnect layer2808or the first interconnect layer2806. In some embodiments, the interconnect layers that are “higher up” in the metallization stack2819in the integrated circuit2800(i.e., farther away from the device layer2804) may be thicker that the interconnect layers that are lower in the metallization stack2819, with lines2828aand vias2828bin the higher interconnect layers being thicker than those in the lower interconnect layers.

The integrated circuit2800may include a solder resist material2834(e.g., polyimide or similar material) and one or more conductive contacts2836formed on the interconnect layers2806-2810. InFIG.28, the conductive contacts2836are illustrated as taking the form of bond pads. The conductive contacts2836may be electrically coupled with the interconnect structures2828and configured to route the electrical signals of the transistor(s)2840to external devices. For example, solder bonds may be formed on the one or more conductive contacts2836to mechanically and/or electrically couple an integrated circuit die including the integrated circuit2800with another component (e.g., a printed circuit board). The integrated circuit2800may include additional or alternate structures to route the electrical signals from the interconnect layers2806-2810; for example, the conductive contacts2836may include other analogous features (e.g., posts) that route the electrical signals to external components.

In some embodiments in which the integrated circuit2800is a double-sided die, the integrated circuit2800may include another metallization stack (not shown) on the opposite side of the device layer(s)2804. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers2806-2810, to provide electrically conductive paths (e.g., including conductive lines and vias) between the device layer(s)2804and additional conductive contacts (not shown) on the opposite side of the integrated circuit2800from the conductive contacts2836.

In other embodiments in which the integrated circuit2800is a double-sided die, the integrated circuit2800may include one or more through silicon vias (TSVs) through the die substrate2802; these TSVs may make contact with the device layer(s)2804, and may provide electrically conductive paths between the device layer(s)2804and additional conductive contacts (not shown) on the opposite side of the integrated circuit2800from the conductive contacts2836. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit2800from the conductive contacts2836to the transistors2840and any other components integrated into the die2800, and the metallization stack2819can be used to route I/O signals from the conductive contacts2836to transistors2840and any other components integrated into the die2800.

Multiple integrated circuits2800may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).

FIG.29is a cross-sectional side view of a microelectronic assembly2900that may include any of the embodiments disclosed herein. The microelectronic assembly2900includes multiple integrated circuit components disposed on a circuit board2902(which may be a motherboard, system board, mainboard, etc.). The microelectronic assembly2900may include components disposed on a first face2940of the circuit board2902and an opposing second face2942of the circuit board2902; generally, components may be disposed on one or both faces2940and2942.

In some embodiments, the circuit board2902may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board2902. In other embodiments, the circuit board2902may be a non-PCB substrate. The microelectronic assembly2900illustrated inFIG.29includes a package-on-interposer structure2936coupled to the first face2940of the circuit board2902by coupling components2916. The coupling components2916may electrically and mechanically couple the package-on-interposer structure2936to the circuit board2902, and may include solder balls (as shown inFIG.29), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure2936may include an integrated circuit component2920coupled to an interposer2904by coupling components2918. The coupling components2918may take any suitable form for the application, such as the forms discussed above with reference to the coupling components2916. Although a single integrated circuit component2920is shown inFIG.29, multiple integrated circuit components may be coupled to the interposer2904; indeed, additional interposers may be coupled to the interposer2904. The interposer2904may provide an intervening substrate used to bridge the circuit board2902and the integrated circuit component2920.

The integrated circuit component2920may be a packaged or unpackaged integrated circuit component that includes one or more integrated circuit dies (e.g., the die2702ofFIG.27, the integrated circuit2800ofFIG.28) and/or one or more other suitable components.

The unpackaged integrated circuit component2920comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer2904. In embodiments where the integrated circuit component2920comprises multiple integrated circuit dies, the dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). In addition to comprising one or more processor units, the integrated circuit component2920can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof. A packaged multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).

The interposer2904may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer2904may couple the integrated circuit component2920to a set of ball grid array (BGA) conductive contacts of the coupling components2916for coupling to the circuit board2902. In the embodiment illustrated inFIG.29, the integrated circuit component2920and the circuit board2902are attached to opposing sides of the interposer2904; in other embodiments, the integrated circuit component2920and the circuit board2902may be attached to a same side of the interposer2904. In some embodiments, three or more components may be interconnected by way of the interposer2904.

In some embodiments, the interposer2904may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer2904may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer2904may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer2904may include metal interconnects2908and vias2910, including but not limited to through hole vias2910-1(that extend from a first face2950of the interposer2904to a second face2954of the interposer2904), blind vias2910-2(that extend from the first or second faces2950or2954of the interposer2904to an internal metal layer), and buried vias2910-3(that connect internal metal layers).

In some embodiments, the interposer2904can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer2904comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer2904to an opposing second face of the interposer2904.

The interposer2904may further include embedded devices2914, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer2904. The package-on-interposer structure2936may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board

The integrated circuit assembly2900may include an integrated circuit component2924coupled to the first face2940of the circuit board2902by coupling components2922. The coupling components2922may take the form of any of the embodiments discussed above with reference to the coupling components2916, and the integrated circuit component2924may take the form of any of the embodiments discussed above with reference to the integrated circuit component2920.

The integrated circuit assembly2900illustrated inFIG.29includes a package-on-package structure2934coupled to the second face2942of the circuit board2902by coupling components2928. The package-on-package structure2934may include an integrated circuit component2926and an integrated circuit component2932coupled together by coupling components2930such that the integrated circuit component2926is disposed between the circuit board2902and the integrated circuit component2932. The coupling components2928and2930may take the form of any of the embodiments of the coupling components2916discussed above, and the integrated circuit components2926and2932may take the form of any of the embodiments of the integrated circuit component2920discussed above. The package-on-package structure2934may be configured in accordance with any of the package-on-package structures known in the art.

FIG.30is a block diagram of an example electrical device3000that may include one or more of the embodiments disclosed herein. For example, any suitable ones of the components of the electrical device3000may include one or more of the microelectronic assemblies2900, integrated circuit components2920, integrated circuits2800, integrated circuit dies2702, or structures disclosed herein. A number of components are illustrated inFIG.30as included in the electrical device3000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all the components included in the electrical device3000may be attached to one or more motherboards, mainboards, printed circuit boards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-a-chip (SoC) die. In various embodiments, the electrical device3000is enclosed by, or integrated with, a housing.

Additionally, in various embodiments, the electrical device3000may not include one or more of the components illustrated inFIG.30, but the electrical device3000may include interface circuitry for coupling to the one or more components. For example, the electrical device3000may not include a display device3006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device3006may be coupled. In another set of examples, the electrical device3000may not include an audio input device3024or an audio output device3008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device3024or audio output device3008may be coupled.

The electrical device3000may include a memory3004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory3004may include memory that is located on the same integrated circuit die as the processor unit3002. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

In some embodiments, the electrical device3000can comprise one or more processor units3002that are heterogeneous or asymmetric to another processor unit3002in the electrical device3000. There can be a variety of differences between the processor units3002in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units3002in the electrical device3000.

In some embodiments, the electrical device3000may include a communication component3012(e.g., one or more communication components). For example, the communication component3012can manage wireless communications for the transfer of data to and from the electrical device3000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data using modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

In some embodiments, the communication component3012may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component3012may include multiple communication components. For instance, a first communication component3012may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component3012may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component3012may be dedicated to wireless communications, and a second communication component3012may be dedicated to wired communications.

The electrical device3000may include battery/power circuitry3014. The battery/power circuitry3014may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device3000to an energy source separate from the electrical device3000(e.g., AC line power).

The electrical device3000may include a display device3006(or corresponding interface circuitry, as discussed above). The display device3006may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device3000may include an audio output device3008(or corresponding interface circuitry, as discussed above). The audio output device3008may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.

The electrical device3000may include an audio input device3024(or corresponding interface circuitry, as discussed above). The audio input device3024may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device3000may include a Global Navigation Satellite System (GNSS) device3018(or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device3018may be in communication with a satellite-based system and may determine a geolocation of the electrical device3000based on information received from one or more GNSS satellites, as known in the art.

The electrical device3000may include another output device3010(or corresponding interface circuitry, as discussed above). Examples of the other output device3010may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The electrical device3000may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device3000may be any other electronic device that processes data. In some embodiments, the electrical device3000may comprise multiple discrete physical components. Given the range of devices that the electrical device3000can be manifested as in various embodiments, in some embodiments, the electrical device3000can be referred to as a computing device or a computing system.

Thus, embodiments of an improved via structure for use with the embedded component have been provided. The provided embodiments advantageously enable the use of finer pitch architectures and high-density input/output (I/O) designs in multi-chip packaging.

As used herein, phrases such as “an embodiment,” “various embodiments,” “some embodiments,” and the like, indicate that some embodiments may have some, all, or none of the features described for other embodiments. “First,” “second,” “third,” and the like describe a common object and indicate different instances of like objects being referred to; unless specifically stated, they do not imply a given sequence, either temporally or spatially, in ranking, or any other manner. In accordance with patent application parlance, “connected” indicates elements that are in direct physical or electrical contact with each other and “coupled” indicates elements that co-operate or interact with each other, coupled elements may or may not be in direct physical or electrical contact. Furthermore, the terms “comprising,” “including,” “having,” and the like, are utilized synonymously to denote non-exclusive inclusions.

As used in this application and the claims, a list of items joined by the term “at least one of” or the term “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B, and C. Likewise, the phrase “one or more of A, B and C” can mean A; B; C; A and B; A and C; B and C; or A, B, and C.

As used in this application and the claims, the phrase “individual of” or “respective of” following by a list of items recited or stated as having a trait, feature, etc. means that all the items in the list possess the stated or recited trait, feature, etc. For example, the phrase “individual of A, B, or C, comprise a sidewall” or “respective of A, B, or C, comprise a sidewall” means that A comprises a sidewall, B comprises sidewall, and C comprises a sidewall.

The following examples pertain to additional embodiments of technologies disclosed herein.

Example A1 includes: a first dielectric layer comprising conductive pads arranged at a first pitch; a second dielectric layer located above the first dielectric layer, the second dielectric layer comprising conductive contacts arranged into a first set and a second set, the first set of conductive contacts further arranged at a second pitch; a glass layer located between the first dielectric layer and the second dielectric layer; a local interconnect component located in the glass layer, the local interconnect component to provide electrical communication between a first conductive contact in the first set and a first conductive contact in the second set; and an electrically conductive path between a second conductive contact of the first set to one of the conductive pads, the electrically conductive path comprising an interconnect structure.

Example A2 includes the subject matter of Example A1, wherein the interconnect structure is a first interconnect structure located in the first dielectric layer or second dielectric layer, and wherein the electrically conductive path further comprises a second interconnect structure located in the glass layer and coupled to the first interconnect structure.

Example A3 includes the subject matter of Example A1, wherein the interconnect structure is a first interconnect structure located in the first dielectric layer, wherein the electrically conductive path further comprises a second interconnect structure located in the glass layer and a third interconnect structure located in the second dielectric layer, and wherein the second interconnect structure is configured to couple the first interconnect structure to the third interconnect structure.

Example A4 includes the subject matter of any one of Examples A1-A3, wherein the interconnect structure comprises a conductive trace and a via.

Example A5 includes the subject matter of Example A1, wherein the first dielectric layer comprises more than one sub-layers, individual sub-layers comprising a respective conductive trace and via.

Example A6 includes the subject matter of Example A1, wherein the second dielectric layer comprises more than one sub-layers, individual sub-layers comprising a respective conductive trace and a via.

Example A7 includes the subject matter of Example A1, wherein the glass layer comprises a glass sheet.

Example A8 includes the subject matter of Example A1, wherein the glass layer comprises more than one glass sheet.

Example A9 includes the subject matter of Example A1, wherein the glass layer comprises more than one glass sheets, and respective glass sheets have a thickness in a range of 100-150 microns.

Example A10 includes the subject matter of Example A1, wherein the glass layer has a thickness substantially in a range of 300 microns to 1 millimeter.

Example A11 includes the subject matter of Example A1, wherein the glass layer comprises a glass sheet, and the glass sheet has a dielectric layer located adjacent thereto.

Example A12 includes the subject matter of Example A1, wherein the glass layer comprises a glass sheet having a dielectric layer located adjacent thereto, and the dielectric layer comprises Ajinomoto Build-up Film (ABF).

Example A13 includes the subject matter of Example A1, wherein the glass layer comprises a glass sheet having a dielectric layer located adjacent thereto, and the dielectric layer is substantially 10 microns thick.

Example A14 includes the subject matter of Example A1, wherein the glass layer comprises silicon and oxygen.

Example A15 includes the subject matter of Example A14, wherein the glass layer comprises further comprises aluminum, boron, or an alkaline-earth metal.

Example A16 includes the subject matter of Example A1, wherein the local interconnect component comprises silicon.

Example A17 includes the subject matter of Example A1, wherein the local interconnect component is a redistribution layer.

Example A18 includes the subject matter of any one of Examples A1-A17, further comprising: a first die attached to the first set of conductive contacts; and a second die attached to the second set of conductive contacts.

Example A19 includes the subject matter of any one of Examples A1-A17, further comprising: a first die attached to the first set of conductive contacts; a second die attached to the second set of conductive contacts; and wherein the first die has a first functionality, the second die has a second functionality, the second functionality being different than the first functionality.

Example A20 includes the subject matter of any one of Examples A1-A17, further comprising a first die attached to the first set of conductive contacts; a second die attached to the second set of conductive contacts; and wherein the first die has a different thickness than the second die.

Example A21 includes the subject matter of any one of Examples A18-A20, further comprising an encapsulant located over the first die and second die.

Example A22 includes the subject matter of Example A21, wherein the apparatus is a panel, and further comprising a cooling component located on the panel.

Example A23 includes the subject matter of Example A22, wherein the cooling component includes a heat exchanger.

Example A24 includes the subject matter of Example A21 or Example A22, wherein the apparatus is a first panel, and further comprising a second panel in electrical communication with the first panel.

Example A25 includes the subject matter of Example A24, further comprising: a substrate; the first panel and the second panel being attached to the substrate.

Example A26 includes the subject matter of Example A25, further comprising an electronic component attached to the substrate, the electronic component located external to the first panel and the second panel.

Example A27 includes the subject matter of Example A26, and further comprising: a housing enclosing the panel; and a heat pump connected to the heat exchanger on the panel via conduits.

Example A28 includes the subject matter of any one of Examples A25-A29, further comprising a power management system electronically coupled to the panel.

Example A29 is a method, comprising: forming a first dielectric layer on a glass carrier, the glass carrier having an area of at least 250 millimeters×250 millimeters, the first dielectric layer comprising conductive pads arranged at a first pitch, the first pitch being 100 microns or less; forming a glass layer on the first dielectric layer, the glass layer comprising a local interconnect component; locating a second dielectric layer on the glass layer, the second dielectric layer comprising conductive contacts arranged at a second pitch, the conductive contacts further arranged into a first set and a second set; the local interconnect component to provide electrical communication between a first conductive contact in the first set and a first conductive contact in the second set; and locating an interconnect structure in the glass layer, the interconnect structure to provide electrical communication between a second conductive contact of the first set and one of the conductive pads.

Example A30 includes the subject matter of Example A29, further comprising: attaching a first die to the first set; and attaching a second die to the second set, thereby creating a populated substrate.

Example A31 includes the subject matter of Example A30, further comprising: debonding the glass carrier from the populated substrate; and forming solder bumps on the conductive pads.

Example A32 includes the subject matter of Example A31, further comprising singulating the populated substrate to thereby create a first panel and a second panel.

Example A33 includes the subject matter of Example A32, further comprising attaching a thermal solution to the first panel or the second panel.

Example A34 is an apparatus, comprising: a first dielectric layer comprising conductive pads arranged at a first pitch; a second dielectric layer located above the first dielectric layer, the second dielectric layer comprising conductive contacts arranged into a first set and a second set, the first set of the conductive contacts being arranged at a second pitch that is smaller than the first pitch; a glass layer located between the first dielectric layer and the second dielectric layer, the glass layer comprising a through-glass via; a photonic integrated circuit (PIC) located in the glass layer and in electrical communication with a first conductive contact from the first set; and an electrically conductive path between a second conductive contact from the first set to one of the conductive pads, the electrically conductive path comprising an interconnect structure located in the first dielectric layer or the second dielectric layer.

Example A35 includes the subject matter of Example A34, wherein the PIC comprises a silicon micro-ring resonator.

Example A36 includes the subject matter of Example A34, further comprising waveguides associated with the PIC located in the glass layer.

Example A37 includes the subject matter of any one of Examples A34-A36, wherein the interconnect structure comprises a conductive trace and a via.

Example A38 includes the subject matter of Example A34, wherein the interconnect structure is a first interconnect structure located in the first dielectric layer or second dielectric layer, and wherein the electrically conductive path further comprises a second interconnect structure located in the glass layer and coupled to the first interconnect structure.

Example A39 includes the subject matter of Example A34, wherein the interconnect structure is a first interconnect structure located in the first dielectric layer, wherein the electrically conductive path further comprises a second interconnect structure located in the glass layer and a third interconnect structure located in the second dielectric layer, and wherein the second interconnect structure is configured to couple the first interconnect structure to the third interconnect structure.

Example A40 includes the subject matter of any one of Examples A38-A39, wherein the first dielectric layer comprises more than one sub-layers, individual sub-layers comprising a respective conductive trace and a via.

Example A41 includes the subject matter of any one of Examples A38-A40, wherein the second dielectric layer comprises more than one sub-layers, individual sub-layers comprising a respective conductive trace and a via.

Example A42 includes the subject matter of any one of Examples A34-A41, wherein the glass layer comprises a glass sheet.

Example A43 includes the subject matter of any one of Examples A34-A41, wherein the glass layer comprises more than one glass sheet.

Example A44 includes the subject matter of any one of Examples A34-A41, wherein the glass layer comprises more than one glass sheets, and respective glass sheets have a thickness in a range of 100-150 microns.

Example A45 includes the subject matter of any one of Examples A34-A41, wherein the glass layer has a thickness substantially in a range of 300 microns to 1 millimeter.

Example A46 includes the subject matter of Example A34, wherein the glass layer comprises a glass sheet, and the glass sheet has a dielectric layer located adjacent thereto.

Example A47 includes the subject matter of Example A34, wherein the glass layer comprises a glass sheet having a dielectric layer located adjacent thereto, and the dielectric layer comprises Ajinomoto Build-up Film (ABF).

Example A48 includes the subject matter of Example A34, wherein the glass layer comprises a glass sheet having a dielectric layer located adjacent thereto, and the dielectric layer is substantially 10 microns thick.

Example A49 includes the subject matter of Example A34, wherein the glass layer comprises silicon and oxygen.

Example A50 includes the subject matter of Example A34, wherein the glass layer comprises further comprises aluminum, boron, or an alkaline-earth metal.

Example A51 includes the subject matter of any one of Examples A34-A50, further comprising a local interconnect component located in the glass layer, the local interconnect component to provide electrical communication between a third conductive contact located in the first set to a fourth conductive located in the second set.

Example A52 includes the subject matter of any one of Examples A34-A51, further comprising a first die attached to the first set of conductive contacts and a second die attached to the second set of conductive contacts.

Example A53 includes the subject matter of any one of Examples A34-A51, further comprising: a first die attached to the first set of conductive contacts; a second die attached to the second set of conductive contacts; and wherein the first die has a first functionality, the second die has a second functionality, the second functionality being different than the first functionality.

Example A54 includes the subject matter of any one of Examples A34-A51, further comprising a first die attached to the first set of conductive contacts; a second die attached to the second set of conductive contacts; and wherein the first die has a different thickness than the second die.

Example A55 includes the subject matter of any one of Examples A52-A54, further comprising an encapsulant located over the first die and second die.

Example A56 includes the subject matter of Example A55, wherein the apparatus is a panel, and further comprising a cooling component located on the panel.

Example A57 includes the subject matter of Example A56, wherein the cooling component includes a heat exchanger.

Example A58 includes the subject matter of any one of Examples A56-A57, wherein the apparatus is a first panel, and further comprising a second panel in electrical communication with the first panel.

Example A59 includes the subject matter of Example A58, further comprising: a substrate; the first panel and the second panel being attached to the substrate.

Example A60 includes the subject matter of Example A59, further comprising an electronic component attached to the substrate, the electronic component located external to the first panel and the second panel.

Example A61 includes the subject matter of Example A58, and further comprising: a housing enclosing the first panel; and a heat pump connected to the heat exchanger on the panel via conduits.

Example A62 includes the subject matter of Example A58, further comprising a power management system electronically coupled to the panel.

Example A63 is a method, comprising: forming a first dielectric layer on a glass carrier, the glass carrier having a cross-sectional area of at least 250 millimeters×250 millimeters, the first dielectric layer comprising conductive pads arranged at a first pitch, the first pitch being 100 microns or less; forming a glass layer on the first dielectric layer, the glass layer comprising a photonic integrated circuit (PIC); locating a second dielectric layer on the glass layer, the second dielectric layer comprising conductive contacts arranged at a second pitch, the conductive contacts further arranged into a first set and a second set; the PIC configured to be in electrical communication with a first conductive contact in the first set or the second set; and locating an interconnect structure in the glass layer, the interconnect structure to provide electrical communication between a second conductive contact of the first set and one of the conductive pads.

Example A64 includes the subject matter of Example A63, further comprising: attaching a first die to the first set; and attaching a second die to the second set, thereby creating a populated substrate.

Example A65 includes the subject matter of Example A64, further comprising: debonding the glass carrier from the populated substrate; and forming solder bumps on the conductive pads.

Example A66 includes the subject matter of Example A65, further comprising singulating the populated substrate to thereby create a first panel and a second panel.

Example A67 includes the subject matter of Example A66, further comprising attaching a thermal solution to the first panel or the second panel.

Example A68 is an apparatus, comprising: a first dielectric layer comprising conductive pads arranged at a first pitch; a second dielectric layer located above the first dielectric layer, the second dielectric layer comprising conductive contacts arranged at a second pitch, the conductive contacts further arranged into a first set and a second set; a glass layer located in between the first dielectric layer and the second dielectric layer; a micro-channel located in the glass layer, the micro-channel configured to accommodate a flow of a liquid coolant; and an electrically conductive path between a second conductive contact from the first set or the second set to one of the conductive pads, the electrically conductive path comprising an interconnect structure located in the first dielectric layer, the second dielectric layer, or glass layer.

Example A69 includes the subject matter of Example A68, wherein the micro-channel has a lateral portion near the first set of conductive contacts.

Example A70 includes the subject matter of Example A68, further comprising a cavity located in the glass layer.

Example A71 includes the subject matter of Example A68, wherein the interconnect structure comprises a conductive trace and a via.

Example A72 includes the subject matter of Example A71, wherein the interconnect structure is located in the first dielectric layer.

Example A73 includes the subject matter of Example A72, wherein the interconnect structure is a first interconnect structure, and further comprising a second interconnect structure located in the second dielectric layer, the second interconnect structure coupled to the first interconnect structure via a through-glass via in the glass layer.

Example A74 includes the subject matter of Example A68, wherein the first dielectric layer comprises more than one sub-layers, individual sub-layers comprising a respective conductive trace and via.

Example A75 includes the subject matter of Example A68, wherein the second dielectric layer comprises more than one sub-layers, individual sub-layers comprising a respective conductive trace and via.

Example A76 includes the subject matter of Example A68, wherein the glass layer comprises a glass sheet.

Example A77 includes the subject matter of Example A68, wherein the glass layer comprises more than one glass sheet.

Example A78 includes the subject matter of Example A68, wherein the glass layer comprises more than one glass sheets, and respective glass sheets have a thickness in a range of 100-150 microns.

Example A79 includes the subject matter of Example A68, wherein the glass layer has a thickness substantially in a range of 300 microns to 1 millimeter.

Example A80 includes the subject matter of Example A68, wherein the glass layer comprises a glass sheet, and the glass sheet has a dielectric layer located adjacent thereto.

Example A81 includes the subject matter of Example A68, wherein the glass layer comprises a glass sheet having a dielectric layer located adjacent thereto, and the dielectric layer comprises Ajinomoto Build-up Film (ABF).

Example A82 includes the subject matter of Example A68, wherein the glass layer comprises a glass sheet having a dielectric layer located adjacent thereto, and the dielectric layer is substantially 10 microns thick.

Example A83 includes the subject matter of Example A68, wherein the glass layer comprises silicon and oxygen.

Example A84 includes the subject matter of Example A83, wherein the glass layer comprises further comprises aluminum, boron, or an alkaline-earth metal.

Example A85 includes the subject matter of any one of Examples A68-A84, further comprising a first die attached to the first set of conductive contacts and a second die attached to the second set of conductive contacts.

Example A86 includes the subject matter of any one of Examples A68-A84, further comprising: a first die attached to the first set of conductive contacts; a second die attached to the second set of conductive contacts; and wherein the first die has a first functionality, the second die has a second functionality, the second functionality being different than the first functionality.

Example A87 includes the subject matter of any one of Examples A68-A84, further comprising a first die attached to the first set of conductive contacts; a second die attached to the second set of conductive contacts; and wherein the first die has a different thickness than the second die.

Example A88 includes the subject matter of any one of Examples A65-A87, further comprising an encapsulant located over the first die and second die.

Example A89 includes the subject matter of Example A88, wherein the apparatus is a panel, and further comprising a cooling component located on the panel.

Example A90 includes the subject matter of Example A89, wherein the cooling component includes a heat exchanger.

Example A91 includes the subject matter of any one of Examples A89-A90, wherein the apparatus is a first panel, and further comprising a second panel in electrical communication with the first panel.

Example A92 includes the subject matter of Example A91, further comprising: a substrate; the first panel and the second panel being attached to the substrate.

Example A93 includes the subject matter of Example A92, further comprising an electronic component attached to the substrate, the electronic component located external to the first panel and the second panel.

Example A94 includes the subject matter of Example A93, and further comprising: a housing enclosing the panel; and a heat pump connected to the heat exchanger on the panel via conduits.

Example A95 includes the subject matter of Example A94, further comprising a power management system electronically coupled to the panel.

Example A96 is a method, comprising: forming a first dielectric layer on a glass carrier, the glass carrier having a cross-sectional area of at least 250 millimeters×250 millimeters, the first dielectric layer comprising conductive pads arranged at a first pitch, the first pitch being 100 microns or less; forming a glass layer on the first dielectric layer, the glass layer comprising a micro-channel; locating a second dielectric layer on the glass layer, the second dielectric layer comprising conductive contacts arranged at a second pitch, the conductive contacts further arranged into a first set and a second set; the micro-channel configured to have a portion near the first set; and locating an interconnect structure in the glass layer, the interconnect structure to provide electrical communication between a conductive contact of the first set and one of the conductive pads.

Example A97 includes the subject matter of Example A96, further comprising: attaching a first die to the first set; and attaching a second die to the second set, thereby creating a populated substrate.

Example A98 includes the subject matter of Example A97, further comprising: debonding the glass carrier from the populated substrate; and forming solder bumps on the conductive pads.

Example A99 includes the subject matter of Example A98, further comprising singulating the populated substrate to thereby create a first panel and a second panel.

Example A100 includes the subject matter of Example A99, further comprising attaching a thermal solution to the first panel or the second panel.

Example B1 is an apparatus, comprising: one or more first dielectric layers, individual of the first dielectric layers positioned adjacent to another first dielectric layer; a plurality of first conductive contacts located on a top dielectric layer of the first dielectric layers, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; one or more second dielectric layers, individual second dielectric layers positioned adjacent to another second dielectric layer, individual of the first dielectric layers and individual of the second dielectric layers comprising one or more conductive traces and one or more vias; a plurality of second conductive contacts located on a bottom dielectric layer of the second dielectric layers, the second conductive contacts arranged at a second pitch, the second pitch greater than the first pitch; and a glass core comprising a layer of glass, the glass core positioned between the one or more first dielectric layers and the one or more second dielectric layers, the glass core comprising a through-glass via.

Example B2 comprises the subject matter of Example B1, further comprising an electrically conductive path from a conductive contact of the first set of the first conductive contacts to a conductive contact of the second set of the first conductive contacts, the electrically conductive path comprising a conductive trace of one of the first dielectric layers and a via of one of the first dielectric layers.

Example B3 comprises the subject matter of Example B1, further comprising an electrically conductive path from one of the first conductive contacts to one of the second conductive contacts, the electrically conductive path comprising at least one conductive trace of one of the first dielectric layers, at least one via of one of the first dielectric layers, the through-glass via of the glass core, at least one conductive trace of one of the second dielectric layers, and at least one via of one of the second dielectric layers.

Example B4 is an apparatus, comprising: one or more first dielectric layers, individual first dielectric layers positioned adjacent to another first dielectric layer; a plurality of first conductive contacts located on a top dielectric layer of the first dielectric layers, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; one or more second dielectric layers, individual second dielectric layers positioned adjacent to another second dielectric layer, individual first dielectric layers and individual second dielectric layers comprising one or more conductive traces and one or more vias; a plurality of second conductive contacts located on a bottom dielectric layer of the second dielectric layers, the second conductive contacts arranged at a second pitch, the second pitch greater than the first pitch; a glass core comprising a layer of glass, the glass core positioned between the first dielectric layers and the second dielectric layers, the glass core comprising a through-glass via; and a bridge located in the first dielectric layers or the glass core, the bridge comprising one or more conductive traces and one or more vias, the bridge comprising silicon.

Example B5 comprises the subject matter of Example B4, further comprising an electrically conductive path from a conductive contact of the first set of the first conductive contacts to a conductive contact of the second set of the first conductive contacts, the electrically conductive path comprising a conductive trace of the bridge and a via of the bridge.

Example B6 comprises the subject matter of Example B4, further comprising an electrically conductive path from a first conductive contact to a second conductive contact, the electrically conductive path comprising at least one conductive trace of one of the first dielectric layers, at least one via of one of the first dielectric layers, the through-glass via of the glass core, at least one conductive trace of one of the second dielectric layers, and at least one via of one of the second dielectric layers.

Example B7 comprises the subject matter of Example B4-B6, wherein the bridge spans two or more first dielectric layers.

Example B8 comprises the subject matter of Example B4-B7, wherein the bridge further comprises one or more through-silicon vias.

Example B9 comprises the apparatus of any one of Examples B4-B6, wherein the bridge is located in the glass core.

Example B10 comprises the subject matter of Example B4-B9, wherein the bridge comprises a trench capacitor, the trench capacitor comprising a first capacitor conductive trace, a second capacitor conductive trace, and a capacitor dielectric positioned between the first capacitor conductive trace and the second capacitor conductive trace, the first capacitor conductive trace and the second capacitor conductive trace oriented substantially perpendicular to a surface of the top dielectric layer of the first dielectric layers.

Example B11 comprises the subject matter of Example B4-B10, wherein the bridge further comprises multiple conductive traces, individual of the conductive traces of the bridge surrounded by a ferromagnetic material comprising iron.

Example B12 comprises the subject matter of Example B4-B11, wherein the bridge further comprises transistor.

Example B13 comprises the subject matter of Example apparatus of any one of Examples B1-B12, wherein the first pitch is less than about 1 micron.

Example B14 comprises the subject matter of Example apparatus of any one of Examples B1-B12, wherein the first pitch is less than about 0.5 microns.

Example B15 comprises the subject matter of Example apparatus of any one of Examples B1-B14, wherein the glass core further comprises a waveguide.

Example B16 comprises the subject matter of Example B15, wherein the waveguide is located in the layer of glass, the waveguide comprising a dielectric material having a permittivity greater than a permittivity of the glass.

Example B17 comprises the subject matter of Example B15, wherein the waveguide comprises silicon and oxygen.

Example B18 comprises the subject matter of Example B15, wherein the apparatus further comprises a photonic integrated circuit, the waveguide to provide a path for optical communication for optical signals to be generated or received by the photonic integrated circuit.

Example B19 comprises the subject matter of Example B15, wherein the apparatus further comprises a fiber array unit, the waveguide to provide a path for optical communication for optical signals to be generated or received by the fiber array unit.

Example B20 comprises the subject matter of any one of Examples B1-B19, wherein individual of the vias are tapered, individual of the vias comprising a narrower end and a wider end, the narrower end positioned closer to the glass core than the wider end.

Example B21 comprises the subject matter of Example B1-B20, wherein the glass comprises aluminum, oxygen, boron, silicon, and an alkaline-earth metal.

Example B22 comprises the subject matter of Example B1-B20, wherein the glass comprises silicon, lithium, oxygen, and a metal.

Example B23 comprises the subject matter of Example apparatus of any one of Example B22, wherein the metal is gold or silver.

Example B24 comprises the subject matter of Example B1-B23, wherein the glass core comprises one or more micro-channels.

Example B25 comprises the subject matter of Example B24, wherein the one or more micro-channels comprise one or more lateral portions and one or more vertical portions.

Example B26 comprises the subject matter of Example B25, wherein the through-glass via is a first through-glass via, the one or more vertical portions of the micro-channels comprising a second through-glass via.

Example B27 comprises the subject matter of Example B25, wherein the glass core further comprises a reservoir connected to at least one of the micro-channels.

Example B28 comprises the subject matter of Example B24-B27, the apparatus further comprising a heat exchanger, a pump, and one or more conduits to connect one of the micro-channels to the heat exchanger and/or the pump.

Example B29 comprises the subject matter of Example B1-B28, further comprising a plurality of integrated circuit dies, individual of the integrated circuit dies attached to one or more of the first conductive contacts.

Example B30 comprises the subject matter of Example B29, wherein a lateral dimension of a first one of the integrated circuit dies is different than a lateral dimension of a second one of the integrated circuit dies.

Example B31 comprises the subject matter of Example B29, wherein a thickness of a first one of the integrated circuit dies is different than a thickness of a second one of integrated circuit dies.

Example B32 comprises the subject matter of Example B29, wherein a functionality implemented by a first one of the integrated circuit dies is different than a functionality implemented by a second one of integrated circuit dies.

Example B33 comprises the subject matter of Example B29, wherein one of the integrated circuit dies comprises a plurality of third conductive contacts attached to the first set of first conductive contacts via solder balls.

Example B34 comprises the subject matter of Example B29, wherein one of the integrated circuit dies comprises a plurality of third conductive contacts directly attached to the first set of first conductive contacts.

Example B35 comprises the subject matter of Example B34, wherein the third conductive contacts and the first set of first conductive contacts comprise copper.

Example B36 comprises the subject matter of Example B29, wherein the one of the integrated circuit dies comprises a bottom dielectric layer directly attached to the top dielectric layer of the first dielectric layers.

Example B37 comprises the subject matter of Example B29, wherein a first integrated circuit die of the integrated circuit dies comprises a first surface and a second surface opposite the first surface, the first integrated circuit die attached to the first conductive contacts at the first surface of the first integrated circuit die, the apparatus further comprising an additional integrated circuit die, the additional integrated circuit die attached to the second surface of the first integrated circuit die.

Example B38 comprises the subject matter of Example B29, further comprising: an encapsulant encapsulating the integrated circuit dies, the encapsulant comprising a through-package via; and a packaged integrated circuit component comprising an integrated circuit component attached to the through-package via, the through-package via attached to one of the first conductive contacts.

Example B39 comprises the subject matter of Example B1-B38, wherein the glass core has a lateral dimension of at least 250 mm.

Example B40 comprises the subject matter of Example B1-B38, wherein the glass core has a lateral dimension of at least 400 mm.

Example B41 comprises the subject matter of Example B1-B40, wherein the glass core has a rectangular shape.

Example B42 comprises the subject matter of Example B1-B40, wherein the glass core has a non-circular shape.

Example B43 comprises the subject matter of Example B29-B42, further comprising a cooling component located on one or more of the integrated circuit dies, the cooling component comprising a liquid-cooled cold plate, a vapor chamber, or a heat sink.

Example B44 comprises the subject matter of Example B1-B43 further comprising a housing, the housing containing the first dielectric layers and the second dielectric layers.

Example B45 comprises the subject matter of Example B1-B44 further comprising a power management component.

Example B46 is an apparatus comprising: a plurality of first dielectric layers, individual first dielectric layers positioned adjacent to another first dielectric layer; a plurality of first conductive contacts located on a top dielectric layer of the first dielectric layers, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; a plurality of second dielectric layers, individual second dielectric layers positioned adjacent to another second dielectric layer, individual of the first dielectric layers and individual of the second dielectric layers comprising one or more first conductive traces and one or more first vias; a plurality of second conductive contacts located on a bottom dielectric layer of the second dielectric layers, the second conductive contacts arranged at a second pitch, the second pitch greater than the first pitch; a first glass core comprising a layer of glass, the first glass core positioned between the one or more first dielectric layers and the one or more second dielectric layers, the first glass core comprising a first through-glass via; a plurality of first integrated circuit dies, individual of the first integrated circuit dies attached to one or more of the first conductive contacts; a plurality of third dielectric layers; a plurality of third conductive contacts located on a top dielectric layer of the third dielectric layers; the plurality of third conductive contacts comprising a first set of third conductive contacts and a second set of third conductive contacts; a plurality of fourth dielectric layers, individual of the third dielectric layers and individual of the fourth dielectric layers comprising one or more second conductive traces and one or more second vias; a plurality of fourth conductive contacts located on a surface of a bottom dielectric layer of the fourth dielectric layers; a second glass core comprising a layer of the glass, the second glass core located between the third dielectric layers and the fourth dielectric layers, the second glass core comprising a second through-glass via; a plurality of second integrated circuit dies, individual of the second integrated circuit dies attached to one or more of the third conductive contacts; and a substrate comprising one or more fifth dielectric layers, individual of the fifth dielectric layers comprising one or more conductive traces and one or more vias, an electrically conductive path from one of the second conductive contacts to one or the fourth conductive contacts comprising a conductive trace of one of the fifth dielectric layers and a via of one of the fifth dielectric layers.

Example B47 comprises the subject matter of Example B46, wherein the electrically conductive path is a first electrically conductive path, further comprising a second electrically conductive path from one of the conductive contacts of the first set of the first conductive contacts to one of the conductive contacts of the second set of the first conductive contacts, the second electrically conductive path comprising a conductive trace of one of the first dielectric layers and a via of one of the first dielectric layers.

Example B48 comprises the subject matter of Example B46, wherein the electrically conductive path is a first electrically conductive path, the apparatus further comprising a second electrically conductive path from a first conductive contact to a second conductive contact, the second electrically conductive path comprising at least one conductive trace of the first dielectric layers, at least one via of the first dielectric layers, the first through-glass via of the first glass core, a conductive trace of one of the second dielectric layers, and at least one via of one of the second dielectric layers.

Example B49 is an apparatus comprising: a plurality of first dielectric layers, individual first dielectric layers positioned adjacent to another first dielectric layer; a plurality of first conductive contacts located on a top dielectric layer of the first dielectric layers, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; a plurality of second dielectric layers, individual second dielectric layers positioned adjacent to another second dielectric layer, individual first dielectric layers and individual second dielectric layers comprising one or more first conductive traces and one or more first vias; a plurality of second conductive contacts located on a bottom dielectric layer of the second dielectric layers, the second conductive contacts arranged at a second pitch, the second pitch greater than the first pitch; a first glass core comprising a layer of glass, the first glass core positioned between the first dielectric layers and the second dielectric layers, the first glass core comprising a first through-glass via; a first bridge located in the first dielectric layers or the first glass core, the first bridge comprising one or more conductive traces and one or more vias, the first bridge comprising silicon; a plurality of first integrated circuit dies, individual of the first integrated circuit dies attached to one or more of the first conductive contacts; a plurality of third dielectric layers; a plurality of third conductive contacts located on a top dielectric layer of the third dielectric layers; the plurality of third conductive contacts comprising a first set of third conductive contacts and a second set of third conductive contacts; a plurality of fourth dielectric layers, individual of the third dielectric layers and individual of the fourth dielectric layers comprising one or more second conductive traces and one or more second vias; a plurality of fourth conductive contacts located on a bottom dielectric layer of the fourth dielectric layers; a second glass core comprising a layer of the glass, the second glass core located between the third dielectric layers and the fourth dielectric layers, the second glass core comprising a second through-glass via; and a second bridge located in the third dielectric layers or the second glass core comprising one or more conductive traces and one or more vias, the second bridge comprising silicon; a plurality of second integrated circuit dies, individual of the second integrated circuit dies attached to one or more of the third conductive contacts; and a substrate comprising one or more fifth dielectric layers, individual of the fifth dielectric layers comprising one or more conductive traces and one or more vias, an electrically conductive path from one of the second conductive contacts to one of the fourth conductive contacts comprising one of the conductive traces of the substrate and one of the vias of the substrate.

Example B50 comprises the subject matter of Example B49, wherein the electrically conductive path is a first electrically conductive path, the apparatus further comprising a second electrically conductive path from one of the conductive contacts of the first set of the first conductive contacts to one of the conductive contacts of the second set of the first conductive contacts, the second electrically conductive path comprising a conductive trace of the first bridge and a via of the first bridge.

Example B51 comprises the subject matter of Example B49, wherein the electrically conductive path is a first electrically conductive path, the apparatus further comprising a second electrically conductive path from a first conductive contact to a second conductive contact, the second electrically conductive path comprising at least one conductive trace of the first dielectric layers, at least one via of the first dielectric layers, the first through-glass via of the first glass core, a conductive trace of one of the second dielectric layers, and at least one via of one of the second dielectric layers.

Example B52 comprises the subject matter of Example B46-B51, wherein the number of the first integrated circuit dies is different than the number of the second integrated circuit dies.

Example B53 comprises the subject matter of Example B46-B51, wherein a functionality implemented by the plurality of the first integrated circuit dies is different than a functionality implemented by the plurality of the second integrated circuit dies.

Example B54 comprises the subject matter of Example B46-B51, further comprising a cooling component located on one or more of the first integrated circuit dies and one or more of the second integrated circuit dies, the cooling component comprising a liquid-cooled cold plate, a vapor chamber, or a heat sink.

Example B55 comprises the subject matter of Example B54, wherein the cooling component comprises a liquid-cooled cold plate, the apparatus further comprising a heat exchanger, a pump, and one or more conduits connecting the cooling component to the heat exchanger and/or the pump.

Example B56 comprises the subject matter of Example B46-B55, further comprising a housing, the housing containing the first dielectric layers, the second dielectric layers, and the first integrated circuit dies.

Example B57 comprises the subject matter of Example B46-B56, further comprising a power management component.

Example C1 is an apparatus comprising: a plurality of dielectric layers stacked vertically, individual of the dielectric layers comprising one or more conductive traces and one or more vias; a plurality of first conductive contacts located on a top dielectric layer of the dielectric layers, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; and a plurality of second conductive contacts located on a bottom dielectric layer of the dielectric layers; the second conductive contacts arranged at a second pitch, the second pitch greater than the first pitch, wherein the first pitch is less than about 1 micron and individual of the dielectric layers have a lateral dimension greater than about 250 mm.

Example C2 comprises the subject matter of Example C1, further comprising an electrically conductive path from one of the conductive contacts of the first set of the first conductive contacts to one of the conductive contacts of the second set of the first conductive contacts, the electrically conductive path comprising a conductive trace of the dielectric layers and a via of the dielectric layers.

Example C3 comprises the subject matter of Example C1, further comprising an electrically conductive path from a first conductive contact to a second conductive contact, the electrically conductive path comprising a conductive trace of the dielectric layers and a via of the dielectric layers.

Example C4 is an apparatus, comprising: a plurality of dielectric layers stacked vertically, individual of the dielectric layers comprising one or more conductive traces and one or more vias; a plurality of first conductive contacts located on a top dielectric layer of the dielectric layers, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; a plurality of second conductive contacts arranged on a bottom dielectric layer of the dielectric layers; the second conductive contacts arranged at a second pitch, the second pitch greater than the first pitch; and a bridge located in the one or more dielectric layers, the bridge comprising one or more conductive traces and one or more vias, the bridge comprising silicon.

Example C5 comprises the subject matter of Example C4, further comprising an electrically conductive path from one of the conductive contacts of the first set of the first conductive contacts to one of the conductive contacts of the second set of the first conductive contacts, the electrically conductive path comprising a conductive trace of the bridge and a via of the bridge.

Example C6 comprises the subject matter of Example C4, further comprising an electrically conductive path from a first conductive contact to a second conductive contact, the electrically conductive path comprising a conductive trace of the dielectric layers and a via of one of the dielectric layers.

Example C7 comprises the subject matter of any one of Examples C4-C6, wherein bridge spans two or more dielectric layers.

Example C8 comprises the subject matter of any one of Examples C4-C7, wherein the bridge comprises one or more through-silicon vias.

Example C9 comprises the subject matter of any one of Examples C4-C8, wherein the bridge comprises a trench capacitor, the trench capacitor comprising a first capacitor conductive trace, a second capacitor conductive trace, and a capacitor dielectric positioned between the first capacitor conductive trace and the second capacitor conductive trace, the first capacitor conductive trace and the second conductive trace oriented substantially perpendicular to a surface of the top dielectric layer of the dielectric layers.

Example C10 comprises the subject matter of any one of Examples C4-C9, wherein the bridge further comprises multiple conductive traces, individual of the conductive traces surrounded by a ferromagnetic layer comprising iron.

Example C11 comprises the subject matter of any one of Examples C4-C10, wherein the bridge comprises a field effect transistor.

Example C12 comprises the subject matter of any one of Examples C1-C10, wherein a thickness of the dielectric layers is in the range of 0.5-200 microns.

Example C13 comprises the subject matter of any one of Examples C1-C12, wherein the first pitch is less than about 1 micron.

Example C14 comprises the subject matter of any one of Examples C1-C12, wherein the first pitch is less than about 0.5 microns.

Example C15 comprises the subject matter of any one of Examples C1-C14, further comprising: a photonic integrated circuit; and an interposer comprising a glass and a waveguide to provide a communication path for optical signals to be generated or received by the photonic integrated circuit.

Example C16 comprises the subject matter of Example C15, wherein the waveguide is located in the glass, the waveguide comprising a dielectric material having a permittivity greater than a permittivity of the glass.

Example C17 comprises the subject matter of Example C15, wherein the waveguide comprises silicon and oxygen.

Example C18 comprises the subject matter of Example C15, further comprising an electronic integrated circuit comprising a first set of electronic integrated circuit conductive contacts located on a first surface of the electronic integrated circuit and a second set of electronic integrated circuit conductive contacts located on a second surface of the electronic integrated circuit that is opposite the first surface, the first set of electronic integrated circuit conductive contacts attached to one or more of the first conductive contacts, the photonic integrated circuit comprising one or more photonic integrated circuit conductive contacts, the photonic integrated circuit conductive contacts attached to the second set of electronic integrated circuit conductive contacts.

Example C19 comprises the subject matter of Example C15, wherein the photonic integrated circuit comprises one or more photonic integrated circuit conductive contacts, the photonic integrated circuit conductive contacts attached to one or more of the first conductive contacts.

Example C20 comprises the subject matter of any one of Examples C15-C19, wherein the apparatus further comprises a fiber array unit, the waveguide further to provide a communication path for optical signals to be generated or received by the fiber array unit.

Example C21 comprises the subject matter of any one of Examples C15-C20, wherein the glass comprises aluminum, oxygen, boron, silicon, and an alkaline-earth metal.

Example C22 comprises the subject matter of any one of Examples C1-C21, wherein the glass comprises silicon, lithium, oxygen, and a metal.

Example C23 comprises the subject matter of any one of Example C22, wherein the metal is gold or silver.

Example C24 comprises the subject matter of any one of Examples C1-C23, further comprising a plurality of integrated circuit dies, individual of the dies attached to one or more of the first conductive contacts.

Example C25 comprises the subject matter of Example C24, wherein a lateral dimension of a first one of the integrated circuit dies is different than a lateral dimension of a second one of the integrated circuit dies.

Example C26 comprises the subject matter of Example C24, wherein a thickness of a first one of the integrated circuit dies is different than a thickness of a second one of integrated circuit dies.

Example C27 comprises the subject matter of Example C24, wherein a functionality implemented by a first one of the integrated circuit dies is different than a functionality implemented by a second one of integrated circuit dies.

Example C28 comprises the subject matter of Example C24, wherein one of the integrated circuit dies comprises a plurality of third integrated circuit die conductive contacts attached to the first set of conductive contacts via solder balls.

Example C29 comprises the subject matter of Example C23, wherein one of the integrated circuit dies comprises a plurality of third conductive contacts directly attached to the first set of first conductive contacts.

Example C30 comprises the subject matter of Example C29, wherein the plurality of third integrated circuit dies conductive contacts and the first set of conductive contacts comprise copper.

Example C31 comprises the subject matter of Example C24, wherein the one of the integrated circuit dies comprises a bottom dielectric layer directly attached to the surface of the top layer of the dielectric layers.

Example C32 comprises the subject matter of Example C24, wherein one of the integrated circuit dies comprises a first surface and a second surface opposite the first surface, the one of the integrated circuit dies attached to the first conductive contacts at the first surface of the one of the integrated circuit dies, the apparatus further comprising an additional integrated circuit die, the additional integrated circuit die attached to the second surface of the integrated circuit dies.

Example C33 comprises the subject matter of Example C24, further comprising: an encapsulant encapsulating the integrated circuit dies, the encapsulant comprising a thru-package via; and a packaged integrated circuit component comprising an integrated circuit component conductive contact attached to the thru-package via, the thru-package via attached to one of the first conductive contacts.

Example C34 comprises the subject matter of any one of Examples C1-C33, wherein individual of the dielectric layers have a lateral dimension of at least 250 mm.

Example C35 comprises the subject matter of any one of Examples C1-C33, wherein individual of the dielectric layers have a lateral dimension of at least 400 mm.

Example C36 comprises the subject matter of any one of Examples C1-C35, wherein individual of the dielectric layers have a rectangular shape.

Example C37 comprises the subject matter of any one of Examples C1-C35, wherein individual of the dielectric layers have a non-circular shape.

Example C38 comprises the subject matter of any one of Examples C24-C37, further comprising a cooling component located on one or more of the integrated circuit dies, the cooling component comprising a liquid-cooled cold plate, a vapor chamber, or a heat sink.

Example C39 comprises the subject matter of Example C38, wherein the cooling component comprises a liquid-cooled cold plate, the apparatus further comprising a heat exchanger, a pump, and one or more conduits connecting the cooling component to the heat exchanger and/or the pump.

Example C40 comprises the subject matter of any one of Examples C1-C39 further comprising a housing, the housing containing the dielectric layers.

Example C41 comprises the subject matter of any one of Examples C1-C40 further comprising a power distribution component.

Example C42 is an apparatus comprising: a plurality of first dielectric layers arranged in a stack, individual of the first dielectric layers comprising one or more first conductive traces and one or more first vias; a plurality of first conductive contacts located on a surface of a top dielectric layer of the first dielectric layers; the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; a plurality of second conductive contacts arranged of a surface of a bottom dielectric layer of the first dielectric layers; the second conductive contacts arranged at a second pitch, the second pitch larger than the first pitch; a plurality of first integrated circuit dies, individual of the first integrated circuit dies attached to one or more of the first conductive contacts; a plurality of second dielectric layers arranged in a stack, individual of the second dielectric layers comprising one or more second conductive traces and one or more second vias; a plurality of third conductive contacts located on a surface of a top dielectric layer of the second dielectric layers; the plurality of third conductive contacts comprising a first set of third conductive contacts and a second set of third conductive contacts; a plurality of fourth conductive contacts located on a surface of a bottom dielectric layer of the second dielectric layers; a plurality of second integrated circuit dies, individual of the second integrated circuit dies attached to one or more of the third conductive contacts; and a substrate comprising one or more third dielectric layers, individual of the third dielectric layers comprising one or more conductive traces and one or more vias, an electrically conductive path from one of the second conductive contacts to one of the fourth conductive contacts comprising a conductive trace of the substrate and a via of the substrate.

Example C43 comprises the subject matter of Example C42, wherein the conductive path is a first electrically conductive path, further comprising a second electrically conductive path from one of the conductive contacts of the first set of the first conductive contacts to one of the conductive contacts of the second set of the first conductive contacts, the second electrically conductive path comprising a conductive trace of the first dielectric layers and a via of the first dielectric layers.

Example C44 comprises the subject matter of Example C42, wherein the electrically conductive path is a first electrically conductive path, the apparatus further comprising a second electrically conductive path from a first conductive contact to a second conductive contact, the second electrically conductive path comprising a conductive trace of the first dielectric layers and a via of the first dielectric layers.

Example C45 comprises the subject matter of An apparatus comprising: one or more first dielectric layers stacked vertically, individual of the first dielectric layers comprising one or more first conductive traces and one or more first vias; a plurality of first conductive contacts located on a top dielectric layer of the first dielectric layers, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; a plurality of second conductive contacts arranged on a bottom dielectric layer of the first dielectric layers; the second conductive contacts arranged at a second pitch, the second pitch larger than the first pitch; a first bridge located in the one or more first dielectric layers, the first bridge comprising one or more conductive traces and one or more vias, the bridge comprising silicon; a plurality of first integrated circuit dies, individual of the first integrated circuit dies attached to one or more of the first conductive contacts; one or more second dielectric layers stacked vertically, individual of the second dielectric layers comprising one or more second conductive traces and one or more second vias; a plurality of third conductive contacts located on a top dielectric layer of the second dielectric layers; the plurality of third conductive contacts comprising a first set of third conductive contacts and a second set of third conductive contacts; a plurality of fourth conductive contacts arranged on a bottom dielectric layer of the second dielectric layers; a second bridge located in the second dielectric layers, the second bridge comprising one or more conductive traces and one or more vias, the bridge comprising silicon; and a plurality of second integrated circuit dies, individual of the second integrated circuit dies attached to the one or more of the third conductive contacts; and a substrate comprising one or more third dielectric layers, individual of the third dielectric layers comprising one or more conductive traces and one or more vias, a substrate electrically conductive path from one of the second conductive contacts to one of the fourth conductive contacts comprising one of the conductive traces of the substrate and one of the vias of the substrate.

Example C46 comprises the subject matter of Example C45, wherein the electrically conductive path is a first electrically conductive path, the apparatus further comprising a second electrically conductive path from one of the conductive contacts of the first set of the first conductive contacts to one of the conductive contacts of the second set of the first conductive contacts, the second electrically conductive path comprising a conductive trace of the bridge and a via of the bridge.

Example C47 comprises the subject matter of Example C45, wherein the electrically conductive path is a first electrically conductive path, the apparatus further comprising a second electrically conductive path from a first conductive contact to a second conductive contact, the second electrically conductive path comprising a conductive trace of the first dielectric layers and a via of the first dielectric layers.

Example C48 comprises the subject matter of any one of Examples C42-C47, wherein the number of the first integrated circuit dies is different than the number of the second integrated circuit dies.

Example C49 comprises the subject matter of any one of Examples C42-C47, wherein the functionality implemented by the plurality of the first integrated circuit dies is different than the functionality implemented by the plurality of the second integrated circuit dies.

Example C50 comprises the subject matter of any one of Examples C42-C49, further comprising a cooling component located on one or more of the first integrated circuit dies and one or more of the second integrated circuit dies, the cooling component comprising a liquid-cooled cold plate, a vapor chamber, or a heat sink.

Example C51 comprises the subject matter of Example C50, wherein the cooling component comprises a liquid-cooled cold plate, the apparatus further comprising a heat exchanger, a pump, and one or more conduits connecting the cooling component to the heat exchanger and/or the pump.

Example C52 comprises the subject matter of any one of Examples C42-C51, further comprising a housing, the housing containing the first dielectric layers, the second dielectric layers, and the first integrated circuit dies.

Example C53 comprises the subject matter of any one of Examples C42-C52, further comprising a power distribution component.

Example C54 comprises the subject matter of A method comprising: forming, on a glass carrier: a plurality of dielectric layers, individual of the dielectric layers comprising one or more conductive traces and one or more vias; a plurality of first conductive contacts on a top dielectric layer of the dielectric layers; and a plurality of second conductive contacts located on a bottom dielectric layer of the dielectric layers, the first conductive contacts arranged at a first pitch that is less than 1 micron, the second conductive contacts arranged at a second pitch that is greater than the first pitch; attaching one or more integrated circuit dies to the first conductive contacts; and removing the glass carrier from the dielectric layers.

Example C55 comprises the subject matter of Example C54, further comprising: etching one or more of the dielectric layers to create a cavity; and locating a bridge in the cavity, the bridge comprising one or more conductive traces and one or more vias.

Example C56 comprises the subject matter of Example C55, wherein the first conductive contacts comprise a first set of first conductive contacts and a second set of first conductive contacts, an electrically conductive path from a conductive contact from the first set of first conductive contacts to a conductive contact of the second set of the first conductive contacts comprising a conductive trace of the bridge and a via of the bridge.

Example C57 comprises the subject matter of Example C54, wherein the glass carrier and individual of the dielectric layers have a lateral dimension of at least 250 mm.

Example C58 comprises the subject matter of Example C54, wherein the glass carrier and individual of the dielectric layers have a lateral dimension of at least 400 mm.