Semiconductor device with conductive elements formed over dielectric layers and method of fabrication therefor

An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, and a first current-carrying electrode and a second current-carrying electrode formed over the semiconductor substrate within openings formed in the first dielectric layer. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and a second current-carrying electrode and over the first dielectric layer. A first conductive element is formed over the first dielectric layer, adjacent the control electrode and between the control electrode and the second current-carrying electrode. A second dielectric layer is disposed over the control electrode and over the first conductive element. A second conductive element is disposed over the second dielectric layer and over the first conductive element.

TECHNICAL FIELD

Embodiments of the subject matter described herein relate generally to semiconductor devices with conductive elements and methods for fabricating such devices.

BACKGROUND

Semiconductor devices find application in a wide variety of electronic components and systems. High power, high frequency transistors find application in radio frequency (RF) systems and power electronics systems. Gallium nitride (GaN) device technology is particularly suited for these RF power and power electronics applications due to its superior electronic and thermal characteristics. In particular, the high electron velocity and high breakdown field strength of GaN make devices fabricated from this material ideal for RF power amplifiers and high-power switching applications. Field plates are used to reduce gate-drain feedback capacitance and to increase device breakdown voltage in high frequency transistors. Accordingly, there is a need for semiconductor and, in particular, GaN devices with field plates.

DETAILED DESCRIPTION

The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the words “exemplary” and “example” mean “serving as an example, instance, or illustration.” Any implementation described herein as exemplary or an example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.

In one aspect, a semiconductor device may include a semiconductor substrate that may include an upper surface and a channel, a first dielectric layer disposed over the upper surface of the semiconductor substrate, a first current-carrying electrode and a second current-carrying electrode formed over the semiconductor substrate within openings formed in the first dielectric layer, wherein the first current-carrying electrode and the second current-carrying electrode are electrically coupled to the channel. A control electrode may be formed over the semiconductor substrate and disposed between the first current-carrying electrode and the second current-carrying electrode and over the first dielectric layer, wherein the control electrode may be electrically coupled to the channel, according to an embodiment. In an embodiment, a first conductive element may be formed over the first dielectric layer, adjacent to the control electrode, and between the control electrode and the second current-carrying electrode. A second dielectric layer may be disposed over the control electrode and over the first conductive element, according to an embodiment. In an embodiment, a second conductive element may be disposed over the second dielectric layer and over the first conductive element.

In another aspect, embodiments of the inventive subject matter may include a gallium nitride heterojunction field effect transistor device. An embodiment may include a semiconductor substrate that includes a gallium nitride layer, an upper surface, and a channel. A first dielectric layer may be disposed over the upper surface of the semiconductor substrate, according to an embodiment. In an embodiment, an active region defined by an isolation region, may be formed within the semiconductor substrate. A source electrode and a drain electrode may be formed over the semiconductor substrate within openings formed in the first dielectric layer in the active region, wherein the source electrode and the drain electrode may be electrically coupled to the channel. A gate electrode may be formed over the semiconductor substrate and disposed between the source electrode and the drain electrode and over the first dielectric layer, wherein the gate electrode may be electrically coupled to the channel. According to an embodiment, a first field plate may be formed over the first dielectric layer, adjacent the gate electrode between the gate electrode and the drain electrode, forming a first metal-insulator-semiconductor region under the first field plate. A second dielectric layer may be disposed over the gate electrode and over the first field plate, according to an embodiment. In an embodiment, a second field plate may be disposed over the second dielectric layer and over the first field plate, forming a second metal-insulator-semiconductor region under the second field plate between the gate electrode and the first field plate, and a third metal-insulator-semiconductor region under the second field plate, adjacent the first field plate and between the first field plate and the drain electrode.

In still another aspect, the inventive subject matter may include a method of fabricating a gallium nitride heterojunction field effect transistor device. An embodiment of the method may include forming a semiconductor substrate that includes gallium nitride having an upper surface and a channel and forming a first dielectric layer over the upper surface of the semiconductor substrate. Embodiments of the method may further include forming a source electrode and forming a drain electrode over the semiconductor substrate within openings formed in the first dielectric layer, wherein the source electrode and the drain electrode are electrically coupled to the channel. The method may include forming a gate electrode over the semiconductor substrate between the source electrode and the drain electrode and over the first dielectric layer, according to an embodiment. In an embodiment, the method may include forming a first field plate over the first dielectric layer, adjacent the gate electrode between the gate electrode and the drain electrode, forming a second dielectric layer over the control electrode and over the first field plate, and forming a second field plate over the second dielectric layer and over the first field plate.

FIG.1is a cross-sectional, side view of an exemplary GaN heterojunction field effect transistor (HFET) device100in accordance with an embodiment. In an embodiment, the GaN HFET device100may include a semiconductor substrate110, one or more isolation regions120, an active region125, a first dielectric layer130, a source electrode (generally “first current-carrying electrode”)140, a drain electrode (generally “second current-carrying electrode”)145, a gate electrode150(generally “control electrode”), a first field plate electrode (generally “first conductive element”)160, a second dielectric layer170, and a second field plate180(generally “second conductive element”). As is described more fully below, the GaN HFET device100is substantially contained within the active region125defined by the isolation regions120, with the first dielectric layer130, the source electrode140, drain electrode145, gate electrode150, first field plate160, and second field plate layer180disposed over the semiconductor substrate110.

In an embodiment, the semiconductor substrate110may include a host substrate102, a buffer layer104disposed over the host substrate102, a channel layer106disposed over the buffer layer104, a barrier layer108disposed over the channel layer106, and a cap layer109disposed over the channel layer106. In an embodiment, the host substrate102may include silicon carbide (SiC). In other embodiments, the host substrate102may include other materials such as sapphire, silicon (Si), GaN, aluminum nitride (AlN), diamond, poly-SiC, silicon on insulator, gallium arsenide (GaAs), indium phosphide (InP), and other substantially insulating or high resistivity materials. A nucleation layer (not shown) may be formed on an upper surface103of the host substrate102between the buffer layer104and the host substrate102. In an embodiment, the nucleation layer may include AN. The buffer layer104may include a number of group III-N semiconductor layers and is supported by the host substrate102. Each of the semiconductor layers of the buffer layer104may include an epitaxially grown group III-nitride epitaxial layer. The group-III nitride epitaxial layers that make up the buffer layer104may be nitrogen (N)-face or gallium (Ga)-face material, for example. In other embodiments, the semiconductor layers of the buffer layer104may not be epitaxially grown. In still other embodiments, the semiconductor layers of the buffer layer104may include Si, GaAs, InP, or other suitable materials.

In an embodiment, the buffer layer104may be grown epitaxially over the host substrate102. The buffer layer104may include at least one AlGaN mixed crystal layer having a composition denoted by AlXGa1-XN with an aluminum mole fraction, X, that can take on values between 0 and 1. The total thickness of the buffer layer104with all of its layers may be between about 200 angstroms and about 100,000 angstroms although other thicknesses may be used. A limiting X value of 0 yields pure GaN while a value of 1 yields pure aluminum nitride (AlN). An embodiment may include a buffer layer104disposed over the host substrate and nucleation layer (not shown). The buffer layer104may include additional AlXGa1-XN layers. The thickness of the additional AlXGa1-XN layer(s) may be between about 200 angstroms and about 50,000 angstroms though other thicknesses may be used. In an embodiment, the additional AlXGa1-XN layers may be configured as GaN (X=0) where the AlXGa1-XN is not intentionally doped (NID). The additional AlXGa1-XN layers may also be configured as one or more GaN layers where the one or more GaN layers are intentionally doped with dopants that may include iron (Fe), chromium (Cr), carbon (C) or other suitable dopants that render the buffer layer104substantially insulating or high resistivity. The dopant concentration may be between about 1017cm−3and 1019cm−3though other higher or lower concentrations may be used. The additional AlXGa1-XN layers may be configured with X=0.01 to 0.10 where the AlXGa1-XN is NID or, alternatively, where the AlXGa1-XN is intentionally doped with Fe, Cr, C, or other suitable dopant species. In other embodiments (not shown), the additional layers may be configured as a superlattice where the additional layers include a series of alternating NID or doped AlXGa1-XN layers where the value of X takes a value between 0 and 1. In still other embodiments, the buffer layer104may also include one or more indium gallium nitride (InGaN) layers, with composition denoted InYGa1-YN, where Y, the indium mole fraction, may take a value between 0 and 1. The thickness of the InGaN layer(s) may be between about 50 angstroms and about 2000 angstroms, though other thicknesses may be used.

In an embodiment, a channel layer106may be formed over the buffer layer104. The channel layer106may include one or more group III-N semiconductor layers and may be supported by the buffer layer104. The channel layer106may include an AlXGa1-XN layer where X takes on values between 0 and 1. In an embodiment, the channel layer106is configured as GaN (X=0) although other values of X may be used without departing from the scope of the inventive subject matter. The thickness of the channel layer106may be between about 50 angstroms and about 10,000 angstroms though other thicknesses may be used. The channel layer106may be NID or, alternatively, may include Si, germanium (Ge), C, Fe, Cr, or other suitable dopants. The dopant concentration may be between about 1015cm−3and about 1019cm−3though other higher or lower concentrations may be used. In other embodiments, the channel layer106may include NID or doped InYGa1-YN, where Y, the indium mole fraction, may take a value between 0 and 1.

A barrier layer108may be formed over the channel layer106in accordance with an embodiment. The barrier layer108may include one or more group III-N semiconductor layers and is supported by the channel layer106. In some embodiments, the barrier layer108has a larger bandgap and larger spontaneous polarization than the channel layer106and, when the barrier layer108is in direct contact with the channel layer106, a channel107is created in the form of a two-dimensional electron gas (2-DEG) within the channel layer106near the interface between the channel layer106and barrier layer108. In addition, strain between the barrier layer108and channel layer106may cause additional piezoelectric charge to be introduced into the 2-DEG and channel107. The barrier layer108may include at least one NID AlXGa1-XN layer where X takes on values between 0 and 1. In some embodiments, X may take a value of 0.1 to 0.35, although other values of X may be used. The thickness of the barrier layer108may be between about 50 angstroms and about 1000 angstroms though other thicknesses may be used. The barrier layer108may be NID or, alternatively, may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be between about 1016cm−3and 1019cm−3though other higher or lower concentrations may be used. In an embodiment, an additional AlN interbarrier layer (not shown) may be formed between the channel layer106and the barrier layer108, according to an embodiment. The AlN interbarrier layer may increase the channel charge and improve the electron confinement of the resultant 2-DEG. In other embodiments, the barrier layer108may include indium aluminum nitride (InAlN) layers, denoted InYAl1-YN, where Y, the indium mole fraction, may take a value between about 0.1 and about 0.2 though other values of Y may be used. In the case of an InAlN barrier, the thickness of the barrier layer108may be between about 30 angstroms and about 2000 angstroms though other thicknesses may be used. In the case of using InAlN to form the barrier layer108, the InAlN may be NID or, alternatively, may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be between about 1016cm−3and about 1019cm−3though other higher or lower concentrations may be used.

In an embodiment illustrated inFIG.1, a cap layer109may be formed over the barrier layer108. The cap layer109presents a stable surface for the semiconductor substrate110and serves to protect the surface of the semiconductor substrate110from chemical and environmental exposure incidental to wafer processing. The cap layer109may include one or more group III-N semiconductor layers and is supported by the barrier layer108. In an embodiment, the cap layer109is GaN. The thickness of the cap layer109may be between about 5 angstroms and about 100 angstroms though other thicknesses may be used. The cap layer109may be NID or, alternatively, may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be between about 1016cm3and 1019cm−3though other higher or lower concentrations may be used. Without departing from the scope of the inventive subject matter, it should be appreciated that the choice of materials and arrangement of layers to form semiconductor substrate110is exemplary. It should be appreciated that the inclusion of the host substrate102, the buffer layer104, the channel layer106, the barrier layer108, and the cap layer109into the semiconductor substrate110is exemplary and that the function and operation of the various layers may be combined and may change depending on the materials used in any specific embodiment. For example, in some embodiments (not shown), the cap layer109may be omitted. In other embodiments using N-polar materials (not shown), the channel layer106may be disposed over the barrier layer108to create a 2-DEG and channel107directly beneath an optional cap109and the gate electrode150. Still further embodiments may include semiconductor layers formed from materials including GaAs, gallium oxide (Ga2O3) aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), and aluminum indium arsenide (AlInAs) to form the semiconductor substrate110.

One or more isolation regions120may be formed in the semiconductor substrate110to define an active region125above and along the upper surface103of the host substrate102, according to an embodiment. The isolation regions120may be formed via an implantation procedure configured to damage the epitaxial and/or other semiconductor layers to create high resistivity regions122of the semiconductor substrate110rendering the semiconductor substrate110high resistivity or semi-insulating in those high resistivity regions122while leaving the crystal structure intact in the active region125. In other embodiments, the isolation regions120may be formed by removing one or more of the epitaxial and/or other semiconductor layers of the semiconductor substrate110rendering the remaining layers of the semiconductor substrate110semi-insulating and leaving behind active region125“mesas” surrounded by high resistivity or semi-insulating isolation regions120(not shown). In still other embodiments, the isolation regions120may be formed by removing one or more of the epitaxial and/or other semiconductor layers of the semiconductor substrate110and then using ion implantation to damage and further enhance the semi-insulating properties of the remaining layers of the semiconductor substrate110and leaving behind active region125“mesas” surrounded by high resistivity or semi-insulating isolation regions120that have been implanted (not shown). In an embodiment, a first dielectric layer130may be formed over the active region125and isolation regions120. In an embodiment, the first dielectric layer130may be formed from one or more suitable materials including silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), aluminum nitride (AlN), and hafnium oxide (HfO2), though other substantially insulating materials may be used. In an embodiment, the first dielectric layer130may have a thickness of between 200 angstroms and 1000 angstroms. In other embodiments, the first dielectric layer130may have a thickness of between 50 angstroms and 10000 angstroms, though other thicknesses may be used.

In an embodiment, the source electrode140and the drain electrode145may be formed over and contact source and drain regions142,147formed in semiconductor substrate110in the active region125. The source electrode140and the drain electrode145may be formed inside a source opening132and a drain opening134formed in the first dielectric layer130and may be formed from one or more conductive layers. In some embodiments, ion implantation may be used to form ohmic contact to the channel107to create source and drain regions142,147. In an embodiment, the one or more conductive layers used to form source and drain electrodes140,145may include Ti, Au, Al, molybdenum (Mo), nickel (Ni), Si, Ge, platinum (Pt), or other suitable materials. In an embodiment, the source electrode140and the drain electrode145may be formed over and in contact with the cap layer109. In other embodiments (not shown), one or both of the source electrode140and the drain electrode145may be recessed through the cap layer109and extend partially through the barrier layer108. In an embodiment, the source electrode140and the drain electrode145may be formed from a multi-layer stack. In an embodiment, the multi-layer stack used to form source electrode140and drain electrode145may include an adhesion layer and one or more layers, that when annealed, allows an ohmic contact to form between the channel107and the source and drain regions142,147. In an embodiment, the adhesion layer may include titanium (Ti), tantalum (Ta), silicon (Si), or other suitable materials. In an embodiment, the adhesion layer may have a work function that is below 4.5 electron-volts.

In an embodiment, the gate electrode150may be formed over the semiconductor substrate110in the active region125. The gate electrode150may include a vertical stem152, a first protruding region154coupled to the vertical stem152over the first dielectric layer130and toward the source electrode, according to an embodiment. In an embodiment a second protruding region156may couple to the vertical stem152and may be formed over the first dielectric layer130and toward the drain electrode145, according to an embodiment. In an embodiment, the gate electrode150may be electrically coupled to the channel107through the cap layer109and barrier layer108. Changes to the electric potential applied to the gate electrode150may shift the quasi Fermi level for the barrier layer108with respect to the quasi Fermi level for the channel layer106and thereby modulate the electron concentration in the channel107within the semiconductor substrate110under the gate electrode150. Schottky materials such as Ni, Pd, Pt, iridium (Jr), and Copper (Cu), may be combined with one or more of low stress conductive materials such as Au, Al, Cu, poly Si, or other suitable material(s) in a metal stack to form a gate electrode150for a low-loss Schottky gate electrode150electrically coupled to channel107, according to an embodiment. In an embodiment, the gate electrode150may be formed, wherein the vertical stem152is formed within a gate opening136in the first dielectric layer130.

In an embodiment, the gate electrode150may be characterized by the gate length153within the gate opening136and first and second protruding region lengths158and159where the first and second protruding regions154and156overlay the first dielectric layer130. In an embodiment, the gate length153may be between about 0.1 microns and about 1 micron. In other embodiments, the gate length153may be between about 0.05 microns and about 2 microns, though other suitable dimensions may be used. In an embodiment, the first protruding region length158may be between about 0.1 microns and about 0.5 microns. In other embodiments, the first protruding region length158may be between about 0.05 microns and 2 microns, though other suitable dimensions may be used. In an embodiment, a second protruding region length159may be between about 0.1 microns and about 0.5 microns. In other embodiments, the second protruding region length159may be between 0.1 microns and 2 microns, though other suitable lengths may be used.

Without departing from the scope of the inventive subject matter, numerous other embodiments may be realized. The exemplary embodiment ofFIG.1depicts the gate electrode150as T-shaped with a vertical stem152and first and second protruding regions154and156disposed over the first dielectric layer130. In other embodiments, the gate electrode150may be a square shape with no protruding regions (e.g.154and156) over the first dielectric layers130. In other embodiments (not shown), the gate electrode150may be recessed through the cap layer109and extend partially into the barrier layer108, increasing the electrical coupling of the gate electrode150to the channel107through the barrier layer108. In other embodiments (not shown), the cap layer109may be omitted and the gate electrode150may contact the barrier layer directly (not shown). In still other embodiments, the gate electrode150may be disposed over a gate dielectric that is formed between the gate electrode150and the semiconductor substrate110to form a metal insulator semiconductor field effect transistor (MISFET) device (not shown).

In an embodiment, the first field plate160may be formed over the first dielectric layer, adjacent the gate electrode150, and between the gate electrode150and the drain electrode145. The first field plate160may be characterized by a first field plate length163and by a field plate to gate distance165from the gate electrode150, according to an embodiment. In an embodiment, the first field plate length163may be between about 0.2 microns and about 0.8 microns. In other embodiments, the first field plate length163may be between 0.1 microns and 2 microns, though other suitable lengths may be used. The first field plate to gate distance165may be between about 0.2 microns and about 1 micron. In other embodiments, the first field plate to gate distance165may be between 0.1 microns and 2 microns, though other suitable lengths may be used. A first metal-insulator-semiconductor region167may be created by the first field plate160, the underlying first dielectric layer130and the semiconductor substrate110. In an embodiment, the first metal-insulator-semiconductor region167acts as part of the active device and has a first threshold voltage, dependent on the thickness of dielectric layer130and the amount of charge in channel107. In an embodiment the first threshold voltage may be between −5 volts and −15 V. In other embodiments, the threshold voltage may be between −4 volts and −30 volts. In an embodiment, the second field plate180reduces the electric field between the gate electrode150and the drain electrode145.

In an embodiment, the second dielectric layer170may be disposed over the first dielectric layer130, the source and drain electrodes140and145, the gate electrode150, and the first field plate160. In an embodiment, the second dielectric layer170may include one or more of SiN, SiO2, AN, HfO2, Al2O3, spin on glass, or other suitable insulating materials. In an embodiment, the third second layer170may have a thickness of between about 500 angstroms and about 5000 angstroms. In other embodiments, the second dielectric layer170may have a thickness between about 100 angstroms and about 20000 angstroms.

In an embodiment, the second field plate180may be disposed over the second dielectric layer160and over the gate electrode150and first field plate160. In an embodiment, the second field plate may be formed on the side of the gate electrode150facing the drain electrode145. In an embodiment, the second field plate180may be coupled to the source electrode140. In other embodiments (not shown), the second field plate180may be disposed over the second dielectric layer170, over the gate electrode150, and first field plate160, and may wrap around the gate electrode150and first field plate160on the sides of the gate electrode150that face the source electrode140and the drain electrode145, and extend to and contact the source electrode140.

In an embodiment, the second field plate creates a second metal-insulator-semiconductor region187and a third metal-insulator-semiconductor region189that includes the second field plate, the second dielectric layer170, the first dielectric layer130, and the semiconductor substrate110. The second and third metal-insulator-semiconductor regions187,189acts as parts of the active device and have a second and third threshold voltages, dependent on the thicknesses of dielectric layer130and second dielectric layer170, the amount of charge in channel107, and interface charges that may exist between the dielectric layers themselves and between first dielectric layer130and the semiconductor substrate110. In an embodiment, the second and third threshold voltages may be between −20 volts and −80 V. In other embodiments, the threshold voltage may be between −10 volts and −200 volts. In an embodiment, the second field plate180reduces the electric field and coupling and associated gate-drain capacitance between the gate electrode150and the drain electrode145. In an embodiment, a field plate drain extension182may extend from the portion of the second field plate adjacent the first field plate160facing the drain electrode145toward the drain electrode145by a second field plate drain extension length184. In other embodiments, the lower surface183of the second field plate drain extension182may be in contact with the first dielectric layer130of the gate electrode150where the second protruding region156contacts the first dielectric layer130. In still other embodiments, the lower surface183of the second field plate drain extension182may be above the second protruding region156of the gate electrode150where the second protruding region156contacts the first dielectric layer130. In an embodiment, the second field plate drain extension length184characterizes the overlap of the second field plate180over the second dielectric layer170and the first dielectric layer130. In an embodiment, the second field plate drain extension length184may be between about 0.2 microns and 2 microns. In other embodiments, the second field plate drain extension length184may be between about 0.1 and about 10 microns. Without departing from the scope of the inventive subject matter, the second field plate extension length184may have other longer or shorter lengths. In an embodiment, the second field plate180may be coupled to the same potential as the source electrode140or to a ground potential. In other embodiments, the second field plate180may be coupled to the gate electrode150(not shown). In other, further embodiments, the second field plate180may be coupled to an arbitrary potential (not shown). In an embodiment, source and drain metallization185,186to the source and drain electrodes may be formed using the same conductive layer(s) as the second field plate180.

In an embodiment, GaN HFET device100may be configured as a transistor finger wherein the source electrode140, drain electrode145, gate electrode150, first field plate electrode160, and second field plate electrode180may be configured as elongated elements forming a gate finger (not shown). GaN transistor device100may be defined, in part, by isolation regions130in which a gate width of the gate finger (i.e., a dimension extending along an axis perpendicular to the plane of GaN transistor device100ofFIG.1is significantly larger than the gate length153of the gate electrode150(i.e., a dimension extending along an axis that is perpendicular to the gate width). In some embodiments, the gate width may be between about 50 microns and about 500 microns. In other embodiments, the gate width may be between about 5 microns and about 1000 microns. In some embodiments, it is desired to minimize signal attenuation along the gate finger to maintain a constant potential along first field plate160and second field plate180by electrically coupling first field plate160and second field plate180to a potential at one or more points. In an embodiment, the first field plate160and the second field plate180may be electrically coupled to the same potential as the source electrode140. First field plate160may be connected to the source electrode140using connections formed from extensions of the conductive material used to form first field plate160at one or more ends of device fingers in the isolation region125to the source electrode140(not shown). In some embodiments, conductive regions “straps” that electrically connect the second field plate180to the source electrode140may be formed periodically along the device finger using the same conductive layer used to form the second field plate180. In an embodiment, these conductive straps may be between 0.1 and 5 microns wide and may be placed at a strap-to-strap spacing along the device finger. In an embodiment, the strap-to-strap spacing may be between about 25 microns and about 100 microns, according to an embodiment, though other shorter or longer strap-to-strap spacings may be used. The strap-to-strap spacing may be between about 5 microns and about 200 microns, according to an embodiment, though other shorter or longer strap-to-strap spacings may be used. In other embodiments (not shown), connections of the second field plate180to the source electrode140may be accomplished either by connections from the second field plate180to the source electrode140using the same metal used to form second field plate180or by using another metal layer (e.g. an interconnect layer) at the end of the device finger in the isolated region125. In still other embodiments, connections between the source electrode140and the second field plate180may be accomplished by forming the second field plate180as a solid, continuous connection to the source electrode140(not shown).

FIG.2is a cross-sectional, side view of an exemplary GaN heterojunction field effect transistor (HFET)200in accordance with an embodiment of the inventive subject matter. In an embodiment, the GaN HFET device200may include a semiconductor substrate110, an isolation region120, an active region125, a first dielectric layer130, a source electrode140, a drain electrode145, a gate electrode150, a first field plate160, a second dielectric layer170, and a second field plate280. As is described in connection with the GaN HFET device100ofFIG.1, the GaN HFET device200may be substantially contained within the active region125defined by the isolation region120, with the first dielectric layer130, the source electrode140, drain electrode145, gate electrode150, first field plate160, second dielectric layer170, and second field plate180disposed over the semiconductor substrate110. In an embodiment, a field plate opening272may be created in the second dielectric layer170over the first field plate160. The field plate opening272may allow the second field plate280to contact the first field plate, according to an embodiment. In some embodiments, the field plate opening272is continuous along the entire gate width of GaN HFET device200. In other embodiments, the field plate opening272is formed in distinct regions along the unit gate width (not shown). In these embodiments, a constant connection-to-connection distance may be a fixed value of between about 5 microns and about 500 microns, though other shorter or longer values for the connection-to-connection distance may be used.

The flowchart300ofFIG.3describes embodiments of methods for fabricating semiconductor devices (e.g. GaN HFET devices100,200FIGS.1-2).FIG.3should be viewed alongsideFIGS.3,4,5,6A,6B,6C,6D,7,8,9A,9B,10A, and10Bwhich illustrate cross-sectional, side views of a series of fabrication steps for producing the semiconductor devices ofFIGS.1and2, in accordance with an example embodiment.

In block302ofFIG.3, and as depicted in the step400ofFIG.4, an embodiment of the method may include forming a semiconductor substrate110. In an embodiment, the step400may include providing a host substrate102and forming number of semiconductor layers on or over the host substrate102. In an embodiment, the host substrate102may include SiC, or may include other materials such as sapphire, Si, GaN, AN, diamond, poly-SiC, silicon on insulator, GaAs, InP, or other substantially insulating or high resistivity materials. Forming the semiconductor layers may include forming a nucleation layer (not shown) on or over an upper surface103of the host substrate102, forming a buffer layer104on or over the nucleation layer, forming the channel layer106on or over the buffer layer104, forming the barrier layer108on or over the channel layer106, and forming the cap layer109on or over the barrier layer108. As discussed previously, embodiments of the buffer layer104, the channel layer106, the barrier layer108, and the cap layer109may include materials selected from AlN, GaN, AlGaN, InAlN, InGaN, or other suitable materials. The semiconductor layers104,106,108, and109may be grown using one of metal-organo chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride-vapor phase epitaxy (HVPE) or a combination of these techniques, although other suitable techniques may alternatively be used. Semiconductor substrate110results.

In block304ofFIG.3, and as depicted in a step500ofFIG.5, an embodiment of the method may include forming a first dielectric layer130on or over the semiconductor substrate110. As discussed previously, in an embodiment, the first dielectric layer130may include materials selected from SiN, Al2O3, SiO2, AlN, and HfO2. The first dielectric layer130may be formed using one or more of low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), sputtering, physical vapor deposition (PVD), plasma-enhance chemical vapor deposition (PECVD), MOCVD, MBE, inductively coupled plasma (ICP) deposition, electron-cyclotron resonance (ECR) deposition, or other suitable techniques. In other embodiments, the first dielectric layer130may be formed, in-situ, immediately after and in the same chamber or deposition system (e.g. MOCVD or MBE) as the growth of the semiconductor layers of semiconductor substrate110. Structure501results.

In block306ofFIG.3, and as depicted in steps600,602,604, and606ofFIGS.6A,6B,6C, and6Dan embodiment of the method may include forming source and drain regions142and147in the first dielectric layer130and forming the source and drain electrodes140and145. Referring again toFIG.6Aand step600, an embodiment of the method may include patterning an implant mask610and implanting a dopant species620through an opening615in implant mask610into the semiconductor substrate to form implant regions630within the semiconductor substrate110. Once the implant mask layer is patterned, a dopant species may be implanted through the implant mask layer and into the semiconductor substrate. In an embodiment, Si, Ge,0, or other suitable n-type dopant may be implanted into the semiconductor substrate through the implant mask. Structure601results.

Referring again to block306ofFIG.3and step602and now toFIG.6B, an embodiment of the method may include activating the dopant species to complete the formation of the source and drain regions142and147within the semiconductor substrate110, and then removing the implant mask610. According to an embodiment, the dopant species may be activated by annealing the semiconductor substrate110using an activation anneal at a temperature of between about 900° C. and about 1500° C. Structure603results.

In an embodiment, and referring toFIG.6C, forming the source and drain openings132,134and may include dispensing a resist layer640over the first dielectric layer130and patterning the resist layer640to form resist openings650. In an embodiment, source and drain electrodes140and145may be created by etching through the first dielectric layer130in areas exposed by the resist openings650to form source and drain openings132and134. Etching the first dielectric layer130(e.g. SiN) may include etching using one or more dry and/or wet etch technique(s) such as reactive ion etching (RIE), ICP etching, ECR etching, and wet chemical etching according to an embodiment. Suitable wet-etch chemistries may include hydrofluoric acid (HF), buffered HF, buffered oxide etch (BOE), phosphoric acid (H3PO4), or other suitable wet etchant(s), according to an embodiment. These dry etching techniques may use one or more of sulphur hexafluoride (SF6), di-carbon hexafluoride (C2F6), carbon tetrafluoride (CF4), tri-fluoromethane (CHF3) or other suitable chemistry, to remove SiN, according to an embodiment. In an embodiment, the etchant used to etch the first dielectric130may selectively etch a portion of the first dielectric layer130and then stop on an etch stop layer (not shown) (e.g. Al2O3or AlN). In an embodiment, etching the etch stop layer (e.g. an Al2O3or AlN etch stop layer) may include wet and/or dry etch techniques. In other embodiment(s), dry etching of the etch stop layer (e.g. an AlN or Al2O3etch stop) may include dry etching using suitable techniques (e.g. RIE, ICP, or ECR) in conjunction chlorine-based chemistry such as Cl2, boron trichloride (BCl3), or other suitable dry-etch chemistries. Structure605results.

Referring again to block306ofFIG.3, and step604ofFIG.6C, an embodiment of the method may include forming and patterning source and drain electrodes140and145in source and drain openings132and134. In an embodiment, the method may include depositing a metal layer660over the resist layer640and into the source and drain openings132and134formed by etching the first dielectric layer130exposed in the resist openings650formed in the resist layer640. In an embodiment, the metal layer660may contain one or more metal layers that include Ti, Ta, Al, Mo, Au, Ni, Si, Ge, platinum (Pt), tungsten (W), and or other refractory metals, that when annealed, will form an ohmic contact with the source and drain regions142,147. In an embodiment, the metal layer660may include a stack deposited on the substrate that includes Ti, Al, and Au. In an embodiment, to form the metal layer660, a Ti layer may be disposed over the semiconductor substrate110in the openings650, an Al layer may be disposed over the Ti layer, a barrier layer formed from Mo or other suitable barrier metal such as Ni or tungsten, may be disposed over the Al layer, and an Au layer may be disposed over the barrier layer. In an embodiment, the metal layer660may be deposited by evaporation. In other embodiments, the metal layer660may be deposited by sputtering, PVD, or other suitable deposition techniques. In an embodiment, the Ti layer may be between about 100 angstroms and 200 angstroms thick, the Al layer may be between about 600 angstroms and 1500 angstroms thick, the Mo layer may be between about 200 angstroms and 700 angstroms thick, and the Au layer may be between about 300 angstroms and 1000 angstroms thick. In other embodiments, other metals may be substituted (e.g. Ni or Pt may be added with substituted for Mo or Ta may be added to or substituted for Ti) and other thicknesses may be used. In an embodiment, the resist layer640may be configured in a lift-off profile, wherein the openings of the resist layer640have a retrograde profile, allowing the metal not deposited into resist openings650to “lift off” when dissolved in solvents. In other embodiments (not shown), the source and drain electrodes140and145may be patterned by dry etching. Structure605results.

Referring again to block306ofFIG.3, and as depicted in step606ofFIG.6D, an embodiment of the method may include annealing source and drain electrodes140and145in source and drain openings132and134. In an embodiment, annealing the source and drain electrodes140and145may include an annealing step used to alloy the metal layer660ofFIG.6Cresulting in ohmic contacts to the source and drain regions142and147formed in semiconductor substrate110that form source and drain electrodes140and145. In an embodiment, the annealing step may be accomplished by rapid thermal annealing. In an embodiment, the metal layer660ofFIG.6Cthat remains in source and drain openings132and134ofFIG.6Cmay be alloyed at a temperature of between about 500 degrees Celsius and 700 degrees Celsius for between about 15 seconds and about 60 seconds. In other embodiments the metal layer660ofFIG.6Cmay be annealed at between about 400 degrees Celsius and about 800 degrees Celsius for between about 10 seconds and about 600 seconds, though other higher or lower temperatures and times may be used. In an embodiment, the metal stack used to form metal layer660(e.g. Ti, Al, Mo, and Au) will mix to form the source and drain electrodes140and145. Structure607results.

Without departing from the scope of the inventive subject matter, drain and source electrodes140and145may be formed using alloyed ohmic contacts (not shown). In these embodiments, source and drain regions may not be formed. Rather, ohmic contact to semiconductor substrate110is accomplished by high temperature annealing of the ohmic metals (e.g. Ti, Al, Mo, Au may be used to form metal stack660).

Referring again to block308and step700ofFIG.7, and in an embodiment, the method may include creating isolation regions120. Forming the isolation regions120may include dispensing and patterning a resist mask710over the first dielectric layer130and then defining openings720in the resist mask710. Using ion implantation, a dopant species725(e.g. one or more of oxygen, nitrogen, boron, and helium) may be driven into the semiconductor substrate110to create high resistivity regions122. In an embodiment, the energy and dose of the implant may be configured to create a sufficient amount of damage in the crystal structure of the semiconductor substrate110such that the semiconductor substrate is substantially high resistivity or semi-insulating within the high resistivity regions122of the isolation regions120. In other embodiments (not shown), forming the isolation regions120may include, first, etching some or all of the semiconductor layers in the semiconductor substrate110and then ion implanting to enhance the resistivity in the remaining semiconductor layers and/or the host substrate102. Structure701results.

Referring next to blocks310and312ofFIG.3and step800inFIG.8, in an embodiment, forming the gate electrode and first field plate of the transistor devices100,200ofFIGS.1and2may include forming a gate opening136in the first dielectric layer130. In an embodiment, forming the gate electrode150and the first field plate160may include depositing and patterning a conductive material to form the gate electrode150and the first field plate160. In the embodiment shown, gate electrode150and first field plate160may be fabricated using the same conductive (e.g. metal) layer(s). In other embodiments (not shown), separate metal layers and processing steps may be used to form gate electrode150and first field plate160.

In an embodiment of the method, photo resist or e-beam resist (not shown) may be patterned to create an opening in the resist in a manner analogous to the description given forFIG.6Cand step604. Using the opening created in the resist layer, the first dielectric layer130may be etched to form gate opening136, thus exposing a portion of the upper substrate surface112, according to an embodiment. In an embodiment, one or more layers of gate metal may then be deposited over the opening in the resist to form the gate electrode150over the upper substrate surface112of the substrate110and the first field plate160over the first dielectric layer130. Depositing gate metal to form the gate electrode150and first field plate160may include depositing a multi-layer stack that includes one or more metal layers and/or other suitable materials. A first layer within the multi-stack used to form the gate electrode150and the first field plate160may include Ti, Ni, Pt, Cu, palladium (Pd), Cr, W, Iridium (Ir), poly-silicon or other suitable materials. The first layer may be between about 30 and about 2,000 angstroms in thickness, although other thickness values may be used. One or more layers that act as conductive layers may be deposited over the first layer to form the gate electrode150and first field plate160, according to an embodiment. The conductive layer(s) may include Au, Ag, Al, Cu, Ti or other substantially conductive materials. The conductive layer(s) may be between about 50 and about 20,000 angstroms in thickness, although other thickness values may be used. Optionally, one or more barrier metal layers may be placed between the first layer and the conductive layer(s), where the barrier metal layer(s) may include materials such as Ni, Pt, Cu, Pd, Cr, W, Jr or other substantially refractive materials that act as a barrier between the portion of the first layer that contacts the substrate110and first dielectric layer130and the conductive layer(s). The barrier metal layer(s) may be between about 50 and about 10,000 angstroms in thickness, although other thickness values may be used. In an embodiment, the various layers used to form gate electrode150and first field plate160may be deposited by evaporation, sputtering, PVD, ALD, or other suitable deposition technique(s).

It should be appreciated that other methods may be used to form the gate electrode150and first field plate160without departing from the scope of the inventive subject matter. In methods for fabricating these other embodiments (not shown), the gate electrode150and first field plate160may be formed by patterning a first resist layer to form an opening, etching the first dielectric layer130to create an opening exposing the upper substrate surface212of the substrate110, and then removing the first resist layer. In this embodiment, forming the gate electrode150and first field plate160includes patterning an opening in a second resist layer aligned over the opening created in the first dielectric layer130to expose the upper substrate surface112. The opening in the second resist layer may be smaller or larger than the opening in the first dielectric layer122. In other embodiments, gate metal may be disposed over a gate dielectric such as SiO2, HfO2, Al2O3, or similar materials (not shown). The gate dielectric may be deposited over and above the upper substrate surface112, according to an embodiment. In still other embodiments, the gate electrode150and first field plate160may be formed using gate metal that is deposited over the substrate110and is then defined by patterning photo resist, and then etching the gate metal. In whichever embodiment or method is selected to form gate electrode150and first field plate160, gate metal may then be deposited using the methods described in connection with the formation of gate electrode150shown inFIG.8.

Referring now to block314ofFIG.3,FIGS.9A and9Band steps900,902the method of fabricating the transistor device100and200ofFIGS.1and2may further include depositing and patterning the second dielectric layer170over the source and drain electrodes140,145, the gate electrode150, the first field plate layer and first dielectric layer130of structure801ofFIG.8, according to an embodiment. In an embodiment, the second dielectric layer170may include one of SiN, Al2O3, SiO2, HfO2, ITO, diamond, poly-diamond, AN, BN, SiC, or a combination of these or other insulating materials. The total thickness of the layers used to form the second dielectric layer170may be between about 100 and about 10,000 angstroms in thickness, although other thickness values may be used. The second dielectric layer170may be deposited using LPCVD, PECVD, sputtering, PVD, ALD, Cat-CVD, HWCVD, ECR CVD, CVD, ICP-CVD, a combination of these or other suitable dielectric deposition technique(s).

In an embodiment, additional process steps to etch the second dielectric layer170may be analogous to those used to etch the first dielectric layer130as described in connection withFIG.6C, step604, and may be used to create openings172,174, and178. In an embodiment, the second dielectric layer170may be patterned by placing a resist layer (not shown) over second dielectric layer170, and patterning the resist layer to form openings to portions of the second dielectric layer170over source and drain electrodes140,145. The second dielectric layer170may then be etched through the openings in the resist layer using a technique analogous to the etching of first dielectric layer130, as described in connection withFIG.6C, step604. Accordingly, openings172and174are created in structure901ofFIG.9Aand openings172,174, and178are formed in structure903ofFIG.9B. Structures901and903result.

Referring now to block316ofFIG.3,FIGS.10A and10Band steps1000,1002the method of fabricating the transistor structures of device200ofFIG.2may further include depositing and patterning the second field plate180,280and source and drain metallization185,186over the second dielectric layer170and source and drain electrodes140,145of structure901and903ofFIG.9, according to an embodiment. In an embodiment, forming and patterning the second field plate180,280and source and drain metallization185,186may be accomplished by applying and patterning resist layers (not shown), depositing the second field plate180, source and drain metallization185,186and removing the resist layers and overlying metal outside the second field plate180,280, source and drain metallization185,186, and other structures (e.g. interconnects, not shown) in a lift-off configuration, analogous to step700inFIG.7. In an embodiment, the second field plate metal is formed by depositing one or more adhesion and conductive metal layers into openings (not shown) patterned into resist layers applied to the partially-formed device as described above. In an embodiment, the adhesion layer(s) may be deposited first, followed by deposition of the conductive layer(s). In an embodiment, the adhesion and conductive layers may be deposited in the same deposition step. The adhesion layer(s) may include one of Ti, Ni, Cr or other suitable adhesion layer material(s). The adhesion layer(s) may be between about 50 and about 2,000 angstroms in thickness, although other thickness values may be used. The conductive layer(s) may include Cu, Au, Al, or Ag, although other suitable materials may be used. The conductive layer(s) may be between about 200 and about 40,000 angstroms in thickness, although other thickness values may be used. The adhesion and conductive layers used to form the second field plate metal280may be deposited over and in contact with the second dielectric layer170and the first field plate160, according to an embodiment. In an embodiment, the adhesion layer(s) and conductive layer(s) may be formed by sputtering, evaporation, or electro-plating. In an embodiment, after applying and patterning resist layers and depositing the second field plate180,280, the resist layers and metals deposited over the resist layers and not included with the portions of the second field plate metal that contact the second dielectric layer170, first field plate160are removed using solvents analogous to those described in conjunction step604inFIG.6C. In other embodiments, the second field plate metal may be formed by depositing adhesion and conductive layers that are then patterned by suitable dry or wet chemical etching techniques. Completed transistor devices100,200result.

For the sake of brevity, conventional semiconductor fabrication techniques may not be described in detail herein. In addition, certain terminology may also be used herein for reference only, and thus are not intended to be limiting, and the terms “first”, “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.

The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.