Semiconductor device

A semiconductor device includes, a semiconductor element, a wiring member arranged to sandwich the semiconductor element, a sealing resin body. The semiconductor element has an SBD formed thereon with a base material of SiC which is a wide band gap semiconductor. The semiconductor element has two main electrodes on both surfaces. The wiring member includes (i) a heat sink electrically connected to a first main electrode and (ii) a heat sink and a terminal electrically connected to a second main electrode. The semiconductor device further includes an insulator. The insulator has a non-conducting element made of silicon. The insulator has joints on both of two surfaces for mechanical connection of the heat sinks.

CROSS REFERENCE TO RELATED APPLICATION

The present application is based on and claims the benefit of priority of Japanese Patent Application No. 2019-178858, filed on Sep. 30, 2019, the disclosure of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure generally relates to a semiconductor device.

BACKGROUND INFORMATION

When a wide bandgap semiconductor having a wider bandgap than silicon is used as a base material of the semiconductor element, the element size can be made smaller than that made of silicon. When the element size is reduced, the stress acting on the semiconductor element increases. In view of the above or other points not mentioned, there is a need for further improvements in semiconductor devices.

SUMMARY

According to the disclosed semiconductor device, the semiconductor element has a wide band gap semiconductor as a base material. However, not only the semiconductor element but also an insulator is interposed between the first wiring member and the second wiring member. In such manner, the stress on the semiconductor element during molding of the sealing resin body is reduced because some forces are distributed to the insulator. In such manner, a highly reliable semiconductor device can be provided.

The disclosed aspects in the specification adopt different technical solutions from each other in order to achieve their respective objectives. Reference numerals in parentheses described in claims and this section exemplarily show corresponding relationships with parts of embodiments to be described later and are not intended to limit technical scopes. The objects, features, and advantages disclosed in this specification will become apparent by referring to following detailed descriptions and accompanying drawings.

DETAILED DESCRIPTION

A semiconductor device according to the present embodiment is applied to a power conversion device. The power conversion device is applied to, for example, a vehicle drive system. The power conversion device can be applied to vehicles such as a fuel cell vehicle (FCV), an electric vehicle (EV), and a hybrid vehicle (HV), for example.

First, a schematic configuration of a vehicle drive system is described. As shown inFIG.1, a vehicle drive system1includes a direct current (DC) power supply2, a motor3, and a power conversion device4.

The DC power supply2is, for example, a lithium ion battery, a nickel hydrogen battery, or a fuel cell. The motor3is a three-phase alternating current (AC) type rotating electric machine. The motor3functions as a source of driving force of the vehicle, that is, an electric motor. The power conversion device4performs power conversion between the DC power supply2and the motor3.

Next, the power conversion device4is described. As shown inFIG.1, the power conversion device4includes a converter5, a smoothing capacitor6, and an inverter7. The converter5and the inverter7are power conversion sections. The converter5is a DC-DC converter that converts a DC voltage into a DC voltage having a different voltage value.

A P line, which is a power line on a high potential side, includes a VH line8H and a VL line8L. The VL line8L is connected to a positive terminal of the DC power supply2. The converter5is provided to a position between the VH line8H and the VL line8L, and a potential of the VH line8H is higher than a potential of the VL line8L. An N line9, which is a power line on a low potential side, is connected to a negative terminal of the DC power supply2.

The smoothing capacitor6is connected to a position between the VH line8H and the N line9. The smoothing capacitor6is provided at a position between the converter5and the inverter7, and is connected in parallel with the converter5and the inverter7. The smoothing capacitor6smooths the DC voltage from the converter5, for example, and accumulates electric charges of the DC voltage. The voltage across the smoothing capacitor6becomes a high DC voltage for driving the motor3.

The inverter7is connected to a position between the VH line8H and the N line9. The inverter7converts the DC power boosted by the converter5into the AC power suitable for driving the motor3, and supplies the AC power to the motor3. The inverter6is a DC-AC converter. A three-phase inverter is used as the inverter7. The power conversion device4may further include a filter capacitor (not shown). The filter capacitor is connected to a position between the DC power supply2and the converter5and between the VL line8L and the N line9.

Next, the converter5is described. As shown inFIG.1, the converter5includes a leg10and a reactor11for each of four phases. InFIG.1, reference numerals in parentheses added to the leg10indicate which of a U phase, a V phase, a W phase, and an X phase the relevant leg10belongs to:10(U),10(V),10(W), and10(X). The converter5of the present embodiment does not have a step-down function but has a step-up (i.e., booster) function.

The leg10is connected to a position between the VH line8H and the N line9. The plurality of legs10are connected in parallel with each other. The legs10of respective phases have a common configuration. The leg10is an upper and lower arm circuit in which the upper arm and the lower arm are connected in series at a position between the VH line8H and the N line9. The upper arm of the leg10has a rectifying element whose forward direction is defined as the one from the DC power source2to the smoothing capacitor6side. The lower arm of the leg10has a switching element.

In the present embodiment, the upper arm of the leg10has a Schottky barrier diode12which is a rectifying element and a non-conducting element13. The Schottky barrier diode12may be referred to as SBD12below. The SBD12is formed on a chip having silicon carbide (SiC) as a base material as described later. An anode of the SBD12is connected to the VH line8H.

The non-conducting element13is connected in parallel to the SBD12. The non-conducting element13is an element in which a plurality of diodes (i.e., PN diodes) are connected in series so that their forward directions are opposite to each other among them. The non-conducting element13is formed on a chip having silicon (Si) as a base material as described later. The non-conducting element13includes two PN diodes13aand13b. Anodes of the PN diodes13aand13bare connected to each other. A cathode of the PN diode13ais connected to an anode of the SBD12, and a cathode of the PN diode13bis connected to a cathode of the SBD12.

Due to the structure described above, a forward voltage Vf of the non-conducting element13has a value larger than a forward voltage Vf of the SBD12. Therefore, no electric current flows through the non-conducting element13. Further, the non-conducting element13has a breakdown voltage performance equal to or higher than that of the SBD12. The non-conducting element13is configured not to interfere with the operation of the SBD12under actual use conditions.

On the other hand, the lower arm of the leg10has an n-channel type MOSFET14which is a switching element and a diode15. Like the SBD12, the MOSFET14is formed on a chip having SiC as a base material. A source of the MOSFET14is connected to the N line9. A drain of the MOSFET14is connected to the cathode of the SBD12. The switching operation of the MOSFET14is controlled by a control circuit section (not shown).

The diode15is connected in antiparallel to the MOSFET14. The diode15is formed on a chip having Si as a base material. An anode of the diode15is connected to the drain (of the MOSFET14), and the cathode is connected to the source (of the MOSFET14).

One end of the reactor11is connected to the positive terminal of the DC power supply2via the VL line8L. The other end of the reactor11is connected to a connection point between the upper arm and the lower arm of the leg10, that is, a connection point between the cathode of the SBD12and the drain of the MOSFET14.

For convenience, inFIG.3, the Z direction is UP (and DOWN is the opposite direction). The X direction is RIGHT (and LEFT is the opposite direction). Now, inFIG.2, the Y direction is REAR (and the opposite direction is FRONT). Returning toFIG.3, we are viewing a FRONT side of a cross section of the device (cross sectioned along the III-III line inFIG.2). Next, a semiconductor device that constitutes the converter5is described.FIGS.2to5show a semiconductor device forming the upper arm of the leg10for one phase of the converter5.FIG.5is a diagram in which the sealing resin body is omitted fromFIG.2. Hereinafter, a plate thickness direction of the semiconductor element is referred to as a Z direction, and one direction orthogonal to the Z direction, specifically, a longitudinal direction of the wiring member is referred to as an X direction. Further, a direction orthogonal to both of the Z direction and the X direction is referred to as a Y direction. Unless otherwise specified, a shape in a plan view seen from the Z direction, in other words, a shape on an XY plane defined by the X direction and the Y direction is a planar shape. Further, a plan view seen from the Z direction is simply referred to as a plan view. As shown inFIGS.2to5, the semiconductor device20includes a sealing resin body30, a semiconductor element40, a wiring member50, main terminals60and61, and an insulator70.

InFIG.2, a sealing resin body30seals a part of the other elements that form the semiconductor device20. The rest of the other elements are exposed toward an outside of the sealing resin body30. The sealing resin body30is made of, for example, an epoxy resin. The sealing resin body30is molded by, for example, a transfer molding method. The sealing resin body30has a substantially rectangular parallelepiped shape. As shown inFIG.2, the sealing resin body30has a substantially rectangular shape in a plan view (viewing downward). InFIG.3, the sealing resin body30has bottom surface30aand a top surface30bopposite to the bottom surface30ain the Z direction. The bottom surface30aand the top surface30bare flat surfaces, for example.

The semiconductor element40is formed by a chip having a wide bandgap semiconductor having a wider bandgap than silicon as a base material. The semiconductor element40may be referred to as a semiconductor chip. The wide band gap semiconductor is a semiconductor having a band gap larger than 1.5 eV, for example. The wide band gap semiconductor includes, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

The semiconductor element40has a lower main electrode41and an upper main electrode42disposed on the main surfaces that are arranged in the plate thickness direction, that is, in the Z direction. In the semiconductor element40, an element having a vertical structure is formed so that a main electric current flows between the main electrodes41and42. As described above, the semiconductor element40of the present embodiment is one in which the SBD (Schottky Barrier Diode)12is formed on a chip having SiC as a base material. A cathode electrode is formed as the lower main electrode41on a lower main surface of the semiconductor element40. An anode electrode is formed as the upper main electrode42on an upper main surface opposite to the lower main surface. The main electrode42(i.e., an anode electrode) may also be called as a Schottky electrode. The lower main electrode41corresponds to the first main electrode, and the upper main electrode42corresponds to the second main electrode.

The wiring member50sandwiches the semiconductor element40in the Z direction. The wiring member50is electrically connected to the main electrode. As the wiring member50, for example, a metal plate made of Cu, a Cu alloy, or the like, or a structure in which a conductor is arranged on at least one surface of an insulating base material can be adopted. A direct bonded copper (DBC) substrate is an example of an insulating substrate on which conductors are arranged. The wiring member50of the present embodiment includes heat sinks51and52and a terminal53. The lower heat sink51is arranged on lower side of the semiconductor element40. The lower heat sink51corresponds to the first wiring member. The upper heat sink52and the terminal53are arranged on an upper side of the semiconductor element40. The upper heat sink52and the terminal53are connected via a solder54. The upper heat sink52, the terminal53, and the solder54correspond to the second wiring member.

The heat sinks51and52are metal members made of Cu, Cu alloy or the like. The heat sinks51and52serve to conduct heat of the semiconductor element40to an outside of the semiconductor device20. The heat sinks51and52may also be called a heat dissipation member. The heat sinks51and52have a substantially rectangular plane shape with its longitudinal side arranged along the X direction. The heat sinks51and52include (overlap) the semiconductor element40in a plan view. The heat sinks51and52have similar shapes.

The terminal53is located in the middle of an electric conduction and heat conduction paths between the semiconductor element40(i.e., the main electrode42) and the heat sink52. The terminal53is formed by including a metal material such as Cu or Cu alloy. The terminal53has a columnar body having a substantially rectangular shape in the plan view and having substantially the same size as the main electrode42in the plan view. The terminal53may be referred to as a metal block body or a relay member.

The lower main electrode41of the semiconductor element40is connected to a lower inner surface51aof the heat sink51via a solder55. The upper main electrode42is connected to one end of the terminal53via a solder56. The other end of the terminal53is connected to an inner surface52aof the heat sink52via the solder54described above.

Most of the heat sinks51and52are covered with the sealing resin body30. Lower outer surface51b(of lower heat sink51) and upper outer surface52b(of upper heat sink52) are exposed from the sealing resin body30. The outer surfaces51band52bmay also be referred to as a heat dissipation surfaces or exposed surfaces. The lower outer surface51bis substantially flush with the bottom surface30aof the sealing resin body30, and the upper outer surface52bis substantially flush with the top surface30b.

The left main terminal60electrically connects the lower main electrode41to an external device. The lower heat sink51is located between the left main terminal60and the lower main electrode41. The right main terminal61electrically connects the upper main electrode42to the external device. The upper heat sink52is located between the right main terminal61and the upper main electrode42.

The left main terminal60extends rearward from the lower heat sink51. The right main terminal61extends rearward from the upper heat sink52. Alternatively, the right main terminal61may extend rearward from the terminals53. The main terminals60and61may also be configured as separate members from the corresponding heat sinks51and52, and may be joined thereto as an extension, or may be a single unified construction. In the present embodiment, the main terminals60and61extend from the corresponding heat sinks51and52as respective continuous metal members.

The main terminal60is extended from the heat sink51in the Y direction (rearward) and protrudes from a rear side surface30cof the sealing resin body30toward the outside thereof. The main terminal61extends from the heat sink52in the Y direction, and protrudes to the outside from the same rear side surface30cas the main terminal60. The semiconductor device20further includes a plurality of dummy terminals62. The dummy terminal62is a terminal that has the same structure as a signal terminal162described later, but does not provide an electrical connection function, in other words, a wiring function. The dummy terminals62are NOT electrically connected to the semiconductor element40components, and NOT to the wiring member50. The dummy terminal62is extended in the Y direction and protrudes from a front side surface30dof the sealing resin body30toward the outside thereof. The front side surface30dis a surface opposite to the rear side surface30cin the Y direction.

The dummy terminal62, together with the heat sink51and the main terminal60, is configured as a lead frame which is a common member. The lead frame is a component having different width part to part (e.g., partially thinned). In the lead frame, a heat sink51part is thick, and a main terminal60and dummy terminal62parts are thin. Unnecessary parts of the lead frame, such as tie bars between the dummy terminals, are cut (i.e., removed) after the molding of the sealing resin body30. Note that a heat sink52part is thicker than a main terminal61part in an integrally-provided, continuous metal member of the heat sink52and the main terminal61.

The insulator70is located in the sealing resin body30. The insulator70is sandwiched by the wiring member50together with the semiconductor element40. The insulator70has an insulating function of electrically separating the lower heat sink51from the upper heat sink52. The insulator70has a joint71for mechanically connecting to the lower heat sink51(optionally via solder55), and joint72for mechanically connecting to the solder56, the terminal53and the upper heat sink52.

As described above, the insulator70of the present embodiment has the non-conducting element13formed on the chip having silicon as a base material. The insulator70has the same thickness as the semiconductor element40. The insulator70has substantially the same planar shape and size as the semiconductor element40. That is, the insulator70has almost the same size as the semiconductor element40. The joint71is formed on the surface of the insulator70on a first wiring member side thereof, and the joint72is formed on the surface on a second wiring member side thereof. The joints71and72are metal members provided to establish mechanical connection with the wiring member50. The joint72has substantially the same planar shape and size as the main electrode42.

The second wiring member has two terminals53, and one of the terminals53is arranged at a position overlapping the main electrode42of the semiconductor element40in the plan view. The other one of the terminals53is arranged at a position overlapping the joint72of the insulator70in the plan view. The two terminals53are provided as a common member (i.e., as the same part). The joint71is connected to the inner surface51aof the heat sink51via the solder55. The joint72is connected to one end of the terminal53via the solder56. The upper joint71corresponds to a first joint, and the lower joint72corresponds to a second joint.

As shown inFIG.5, the insulator70is located rightward of the semiconductor element40. The semiconductor element40is arranged in a left region and the insulator70is arranged in a right region with respect to a virtual center line CL of the wiring member50extending perpendicular to the longitudinal direction thereof. Specifically, the insulator70and the semiconductor element40are arranged in substantial mirror symmetry with respect to the center line CL.

As described above, in the semiconductor device20, the sealing resin body30seals the semiconductor element40and the insulator70that form the upper arm of the leg10for one phase. The sealing resin body30integrally seals the semiconductor element40, the insulator70, a part of the heat sink51, a part of the heat sink52, the terminal53, a part of each of the main terminals60and61, and a part of each of the dummy terminals62.

The semiconductor element40is arranged at a position between the heat sinks51and52in the Z direction. (The semiconductor element40is disposed at an in-between position of an arrangement/stack of the heat sinks51and52along the Z direction.) Thereby, the heat of the semiconductor element40can be radiated/dissipated to both sides in the Z direction. The semiconductor device20has a double-sided heat dissipation structure. The outer surface51bof the heat sink51is substantially flush with the bottom surface30aof the sealing resin body30. The outer surface52bof the heat sink52is substantially flush with the top surface30bof the sealing resin body30. Since the outer surfaces51band52bare exposed surfaces, heat dissipation can be improved.

FIG.6is a reference diagram showing a semiconductor device120forming the lower arm of the leg10for one phase of the converter5.FIG.2corresponds toFIG.6. The semiconductor device120has the same configuration as the semiconductor device20. In the semiconductor device120, a semiconductor element140is arranged instead of the semiconductor element40. Further, a semiconductor element145is arranged in place of the insulator70, and the signal terminal162is arranged in place of the dummy terminal62. A sealing resin body130corresponds to the sealing resin body30, and a wiring member150corresponds to the wiring member50. Main terminals160and161correspond to the main terminals60and61. The main terminals160and161protrude toward the outside from a side surface130cof the sealing resin body130.

Like the semiconductor element40, the semiconductor element140uses a wide band gap semiconductor, specifically, SiC as a base material. The MOSFET14described above is formed in the semiconductor element140. The semiconductor element140has main electrodes (not shown) on both sides in the Z direction. One of the main electrodes is a drain electrode and the other one is a source electrode. The drain electrode is soldered to a heat sink (not shown) that forms the wiring member150. The source electrode is connected to the heat sink152via a terminal (not shown). The semiconductor element140is different from the semiconductor element40in the element formed on the chip, but the semiconductor material constituting the base material, the planar shape and size, and the thickness are almost the same as the semiconductor element40.

Like the insulator70, the semiconductor element145uses Si as a base material. The diode15described above is formed in the semiconductor element145. The semiconductor element140has main electrodes (not shown) on both sides in the Z direction. One of the main electrodes is a cathode electrode and the other one is an anode electrode. The cathode electrode is soldered to the same heat sink as the drain electrode. The anode electrode is connected to the same heat sink152as the source electrode via the terminal. Although the semiconductor element145is different from the insulator70in terms of the element formed on the chip, the semiconductor material, the planar shape and the size, and the thickness of the base material are substantially the same as those of the insulator70.

The signal terminal162is an external connection terminal that provides an electrical connection function. The signal terminal162is connected to a pad (not shown) of the semiconductor element140via a bonding wire180. The pad is formed on the same main surface as the source electrode in the semiconductor element140. The signal terminal162protrudes toward the outside from the side surface130dof the sealing resin body130. The side surface130dis a surface opposite to the side surface130c. The structure of the signal terminal162is the same as that of the dummy terminal62. InFIG.6, a portion of the signal terminal162covered with the sealing resin body130and the bonding wire180are indicated by broken lines.

The signal terminal162is formed/provided as a lead frame including (i) a heat sink to which the drain electrode of the semiconductor element140and the cathode electrode of the semiconductor element145are connected, and (ii) the main terminal160. This lead frame is a member (i.e., a common component) common to the (above-described) lead frame including the heat sink51, the main terminal60, and the dummy terminal62that form the semiconductor device20.

Therefore, the semiconductor device20forming an upper arm can be formed by the same manufacturing process using the same member as the semiconductor device120forming a lower arm. This makes it possible to reduce the manufacturing time and cost, for example. Further, the signal terminal162of the semiconductor device120is mounted on a circuit board on which at least a part of the control circuit unit described above is formed. In the present embodiment, the semiconductor device20has the same configuration as the semiconductor device120and has the dummy terminal62. Therefore, the dummy terminal62can be mounted on the circuit board. The semiconductor device20is held on the circuit board by the dummy terminals62.

<Method of Manufacturing Semiconductor Device>

Next, a manufacturing method of the semiconductor device20is described.

First, a connected structure in which the semiconductor element40and the insulator70are sandwiched between or by the wiring members50is formed.

More specifically, (i) a lead frame including the heat sink51, the main terminal60, and the dummy terminal62, and (ii) the heat sink52including a series of the main terminals61are prepared together with the semiconductor element40, the insulator70and the terminal53. Then, the semiconductor element40and the insulator70are disposed on the inner surface51aof the heat sink51via the solder55, respectively. Or, for example, the terminals53, which are pre-soldered on both sides, are disposed on the semiconductor element40with the solder56facing the semiconductor element40side. The terminal53is disposed on the insulator70in the same manner.

The semiconductor device20having a double-sided heat dissipation structure is sandwiched from both sides in the Z direction by a cooler (not shown), for example. Therefore, high parallelism of the surfaces in the Z direction and high dimensional accuracy between the parallel surfaces are required. Therefore, the solder54is configured in an amount capable of absorbing the height variation of the semiconductor device20. That is, a large amount of solder54is disposed. In other words, the solder54is configured to be thicker than the solders55and56. Then, in such an arrangement state, a first reflow is performed. Such arrangement makes it possible to obtain a stacked body in which the semiconductor element40, the insulator70, the heat sink51, and the terminal53are integrally connected to have one body.

Next, the heat sink52is disposed on one surface of a pedestal not shown so that the inner surface52afaces upward. Then, the above-mentioned laminated body is disposed on the heat sink52so that the solder54faces the heat sink52, and a second reflow is performed. In the second reflow, a load is applied in the Z direction from the heat sink51side so that the height of the semiconductor device20has a predetermined height/dimension. For example, by applying a load, a spacer (not shown) is brought into contact with both of the inner surface51aof the heat sink51and one surface of the pedestal. In such manner, the height of the semiconductor device20is set to have the predetermined height.

By performing the second reflow, the stacked body and the heat sink52having a series of the main terminals61are integrated to form a connected structure in one body. The solder54absorbs height variations due to dimensional tolerances of components constituting the semiconductor device20and assembly tolerances.

After forming the connected structure, the sealing resin body30is molded. In the present embodiment, a transfer mold method is adopted. The connected structure is placed in a mold, and the sealing resin body30is molded. In the present embodiment, the sealing resin body30is molded so that the heat sinks51and52are completely covered, and cutting is performed after the molding. The sealing resin body30is cut together with a part of the heat sinks51and52. In such manner, the outer surfaces51band52bare exposed from the sealing resin body30. The outer surface51bis substantially flush with the bottom surface30a, and the outer surface52bis made substantially flush with the top surface30b.

Next, the semiconductor device20can be obtainable by removing a tie bar or the like (not shown).

Note that the sealing resin body30may be molded in a state where the outer surfaces51band52bare pressed against a cavity wall surface of the molding die and brought into close contact with each other. In such case, when the sealing resin body30is molded (i.e., at the time when the molding is complete), the outer surfaces51band52bare (already) exposed from the sealing resin body30. Therefore, cutting after molding is unnecessary. Also, though an example in which reflow is performed twice has been shown above, the present invention is not limited to such example. The connected structure may be formed by one reflow process. Alternatively, the connected structure may be formed by a solder die bonder method or the like without performing reflow.

Summary of First Embodiment

Wide band gap semiconductors such as SiC have characteristics such as higher dielectric breakdown field strength, higher saturation speed, and higher thermal conductivity than Si. Therefore, if the performance is equivalent, the element size can be made smaller than that of Si. In general, when the element size is reduced, so is the heat radiation/dissipation area size, causing difficulty in dissipation of the generated heat. The wide band gap semiconductor has a higher thermal conductivity and a higher thermal rating than Si, thereby allowing/enabling an element size reduction. The cost can also be reduced by reducing the element size.

As described above, the semiconductor device20of the present embodiment includes the semiconductor element40having a wide band gap semiconductor as a base material. The semiconductor element40has a smaller element size than a configuration in which an element having equivalent performance is formed on a chip having Si as a base material.FIGS.7A/7B show a step of filling a mold cavity with a resin30A to form the sealing resin body30. As shown inFIG.7A, when the sealing resin body30is formed so as to cover the outer surfaces51band52bof the heat sinks51and52, for example, a gap between the outer surface52bof the heat sink52and a cavity wall surface80left un-filled with the resin30A may sometimes be formed. In such case, a difference is caused between a force that is applied to the inner surface52aof the heat sink52from the resin30A and a force that is applied to the outer surface52bfrom the resin30A. That is, when the forces on the outer and inner surfaces are inequivalent (i.e., when hydrostatic pressure is not achieved by the forces acting on both surfaces), stress acts on a column portion that mechanically connects the heat sinks51and52. That is, stress acts on the semiconductor element40.

If only the semiconductor element40having a small element size is disposed at a position between the heat sinks51and52, stress concentrates on the semiconductor element40. For example, stress concentrates on the solder joint between the semiconductor element40and the wiring member50. In the present embodiment, the insulator70also functions as a column that mechanically connects the heat sinks51and52, thereby distributing/releasing stress that acts during molding of the sealing resin body30toward the insulator70. Therefore, stress concentration on the semiconductor element40can be suppressed. In such manner, a highly reliable semiconductor device20can be provided.

When the sealing resin body30is molded by bringing the outer surfaces51b,52binto contact with the cavity wall surface80(FIG.7B), a direction of the force received by the inner surface51aof the heat sink51from the resin30A and a direction of the force received by the inner surface52aof the heat sink52from the resin30A are opposite to each other. Therefore, the semiconductor element40is subjected to (i.e., receives) stress in a pulling direction toward both sides in the Z direction. In the present embodiment, since the insulator70is present, the stress that acts at the time of molding the sealing resin body30is distributed toward the insulator70. Therefore, stress concentration on the semiconductor element40can be suppressed. In such manner, a highly reliable semiconductor device20can be provided. InFIGS.7A/7B, the force received by the heat sink receives from the resin is indicated by a white arrow.

In the present embodiment, as the insulator70, the non-conducting element13formed on a chip having Si as a base material is adopted. Therefore, the function of mechanically connecting the wiring members50is achieved, while the operation of the semiconductor element40is not hindered. The non-conducting element13has a structure in which the PN diodes13aand13bare connected in opposite directions, and can be easily formed on a semiconductor substrate.

The arrangement direction of the semiconductor element40and the insulator70is not limited to the above example. For example, the lateral direction of the wiring member50may be set as the arrangement direction. However, the X direction, which is the longitudinal direction of the wiring member50, is set as the arrangement direction. In such manner, it is possible to suppress an increase in the size/volume of the wiring member50, and thus of the semiconductor device20. For example, in the heat sink52, a rotational moment may be generated due to the difference in the forces acting on the inner surface52aand the outer surface52b. The rotational moment is particularly large in the longitudinal direction of the heat sink52, but the rotational moment can be suppressed by making the arrangement direction the longitudinal direction. Also by such arrangement, the stress acting on the semiconductor element40can be reduced.

Particularly, in the present embodiment, the semiconductor element40is arranged in one region in the longitudinal direction with respect to the virtual center line CL of the wiring member50in the longitudinal direction, and the insulator70is arranged in the other region. Therefore, the rotational moment can be effectively cancelled by the semiconductor element40and the insulator70which are located on the left and right sides, for example, in the plan view with respect to the rotation axis.

Although the non-conducting element13is formed by the two PN diodes13aand13b, the non-conducting element13is not limited to such configuration. A configuration in which three or more PN diodes are connected in series may be adopted such that the forward directions of adjacent PN diodes are opposite to each other among the three or more diodes.

The second embodiment is a modification of a preceding embodiment as a basic configuration and may incorporate description thereof. In the preceding embodiment, the area size of the insulator70is made substantially equal to that of the semiconductor element40in a plan view. Also, an example in which only one insulator70is provided is shown. However, the present disclosure is not limited to such an example.

FIGS.8and9show the semiconductor device20of the present embodiment. Similar to the preceding embodiment, one semiconductor element40and one insulator70are arranged between the wiring members50. The area size of the insulator70is larger than the area size of the semiconductor element40in a plan view. In such manner, the area size of the solder joints between the heat sinks51and52and the terminal53that form the wiring member50is larger for a connection portion of the insulator70than a connection portion of the semiconductor element40. The other configuration is the same as that of the preceding embodiment.

Summary of Second Embodiment

In the present embodiment, the insulator70is larger than the semiconductor element40in the plan view, thereby the stress acting on the insulator70is increased as compared with the preceding embodiment. In such manner, the stress acting on the semiconductor element40can be further reduced. Therefore, the reliability of the semiconductor device20can be further improved.

The configuration of the semiconductor device20is not limited to the above example. For example, as in a modification shown inFIG.10, the semiconductor device20may include plural insulators70. InFIG.10, the semiconductor device20includes two insulators70. The two insulators70are arranged side by side in the Y direction. By providing plural insulators70, the number of columns that mechanically connect the heat sink51and the heat sink52increases. This makes it possible to divide and distribute the otherwise-concentrating stress acting on the molding of the sealing resin body30into two columns. It should be noted that the configuration may include three or more insulators70. Further, the arrangement of the plural insulators70is not limited to the example shown inFIG.10. For example, the line of arrangement of the plural insulators70may extend along the X direction.

Further, in the example ofFIG.10, the total area size of the plural insulators70, that is, the sum of the area sizes of the insulators70is larger than the area size of the semiconductor element40. In such manner, the same effects as that of the configuration shown inFIG.8can be obtainable.

The third embodiment is a modification of a preceding embodiment as a basic configuration and may incorporate description thereof. In the preceding embodiment, the non-conducting element13is the insulator70. The insulator is not limited to such component.

FIG.11is a cross-sectional view showing the semiconductor device20of the present embodiment and corresponds toFIG.3. The semiconductor device20includes an insulator70A. The other configuration is the same as that of the first embodiment. The insulator70A has joints71and72on both surfaces of an insulating base material. The insulating base material is formed by using an inorganic material having an electric insulating property such as glass, ceramics, and semiconductors. The non-conducting element13is not formed on the insulator70A, that is, the insulating base material.

The insulator70A has a breakdown voltage equal to or higher than that of the semiconductor element40by using an insulating base material made of an inorganic material. Further, the insulator70A electrically separates (i) the heat sink51, which is the first wiring member, from (ii) the heat sink52, which is the second wiring member, and the terminal53. Therefore, no electric current flows between the first wiring member and the second wiring member through the insulator70A, and the operation of the semiconductor element40is not hindered under the use condition of the semiconductor device20. The insulator70A functions as a pillar that mechanically connects the heat sink51and the heat sink52.

Summary of Third Embodiment

As shown in the present embodiment, the insulator70A may be adoptable to function as an insulator by utilizing the characteristics of the base material. The semiconductor device20including the insulator70A can also achieve the same effects as the semiconductor device20including the insulator70. It may be preferable to use, for the insulator70, a material having a linear expansion coefficient close to that of the base material forming the semiconductor element40.

The configuration of the present embodiment and the configuration of the second embodiment may be combinable. The present embodiment can achieve the same effects as the configuration described in the second embodiment. For example, the area size of the insulator70A may be larger than the area size of the semiconductor element40. Also, the configuration may include plural insulators70A. The total area size of the plural insulators70A may be larger than the area size of the semiconductor element40.

Other Embodiments

The present disclosure in the specification and drawings is not limited to the exemplified embodiments. The present disclosure encompasses the illustrated embodiments as well as modifications of the embodiments by those skilled in the art. For example, the present disclosure is not limited to the combination of parts and/or elements shown in the embodiments. The present disclosure may be implemented in various combinations. The present disclosure may have additional portions that may be added to the embodiments. The present disclosure encompasses omission of components and/or elements of the embodiments. The present disclosure encompasses the replacement or combination of components and/or elements between one embodiment and the other. The disclosed technical scope is not limited to the description of the embodiments. It is to be understood that some technical scopes disclosed are shown by the description of the claims, and further include meanings equivalent to the description of the claims and all modifications within the scope.

The disclosure in the specification, drawings and the like is not limited by the description of the claims. The disclosures in the specification, the drawings, and the like encompass the technical ideas described in the claims, and further extend to a wider variety of technical ideas than those in the claims. Therefore, various technical ideas can be extracted from the disclosure of the specification, the drawings and the like without being limited to the description of the claims.

Although the example in which the semiconductor device20includes the dummy terminal62is shown, the invention is not limited to such example. The dummy terminal62is optional, and may be omitted.

The number and arrangement of the main terminals60and61are not limited to the above example. For example, a configuration may be used in which at least one of the main terminals60and61is provided in plurality.

The circuit configuration of the converter5to which the semiconductor device20is applied is not limited to the above example. The number of phases of the converter5is not limited to polyphase. The number of phases therein may be a single phase. In case of adopting polyphase, the number of phases is not limited to four. In the leg10for one phase, the upper arms may have parallel configuration. For example, a parallel circuit of the SBD12and the non-conducting element13may be provided in two sets, and two sets of such parallel circuit may be connected in parallel with each other. The application target of the semiconductor device20is not limited to the upper arm of the converter5having the booster function.

The number of semiconductor elements40included in the semiconductor device20is not limited to the above example. As described above, when one upper arm is composed of two sets of parallel circuits, two semiconductor elements40and two insulators70(i.e., non-conducting elements13) may be provided.

The configuration described in the present embodiment has a semiconductor element in which a vertical element is formed using a wide band gap semiconductor as a base material, a wiring member arranged to sandwich the semiconductor element, and a sealing resin body for integrally sealing the semiconductor element and the wiring member. In such configuration, by adding an insulator, it is possible to reduce the stress acting on the semiconductor element at the time of molding the sealing resin body thereby provide a highly reliable semiconductor device. The vertical element is not limited to the SBD12described above. The vertical element may also be a switching element such as MOSFET or the like.

In the plan view, the area size of the insulator70(or70A) may be made smaller than the area size of the semiconductor element40. By providing the insulator70(or70A), the stress acting on the semiconductor element40can be reduced as compared with a configuration without having the insulator70/70A.

Although the example in which the second wiring member includes the heat sink52and the terminal53is shown, the present disclosure is not limited to such an example. The terminal53may be omissible. For example, instead of the terminal53, the heat sink52may be provided with a protrusion protruding toward the semiconductor element40.

The example in which the outer surfaces51band52bof the heat sinks51and52are exposed from the sealing resin body30has been shown, but the present invention is not limited to such an example. The outer surfaces51band52bmay be configured not to be exposed from the sealing resin body30.