Shallow trench isolation for end fin variation control

A method of fabricating a fin field effect transistor (FinFET) device and the device are described. The method includes forming a deep STI region adjacent to a first side of an end fin among a plurality of fins and lining the deep STI region, including the first side of the end fin, with a passivation layer. The method also includes depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin, etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap, and depositing gate material, the gate material covering the gap.

BACKGROUND

The present invention relates to a multi-gate, fin-based field effect transistor (FinFET), and more specifically, to hybrid shallow trench isolation (STI) with both shallow and deep STI.

Multi-gate FinFETs require both shallow and deep STIs to prevent leakage current between adjacent devices. Typically, FinFET devices are fabricated by shallow STI formation followed by an active silicon cut process to etch out the active silicon region and form deep STI. Overlay misalignment during this process may cause the end fins to not be completely covered by the polysilicon conductor. As a result, the end fins submerged in the STI without polysilicon deposition may lead to poor short channel control and may potentially lead to leaks.

SUMMARY

According to one embodiment of the present invention, a method of fabricating a fin field effect transistor (FinFET) device including both shallow and deep shallow trench isolation (STI) regions includes forming a deep STI region adjacent to a first side of an end fin among a plurality of fins; lining the deep STI region, including the first side of the end fin, with a passivation layer; depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin; etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap; and depositing gate material, the gate material covering the gap.

According to an embodiment of the invention, a fin field effect transistor (FinFET) device includes a plurality of fins; a plurality of shallow trench isolation (STI) regions, each adjacent pair of the plurality of fins being separated by one of the plurality of STI regions; a deep STI region formed on a first side of an end fin among the plurality of fins; and gate material deposited over the plurality of fins and in the deep STI region, the gate material covering both sides of a fin reveal of each of the plurality of fins and covering the first side of the end fin by filling a gap between the first side of the end fin and a gate oxide layer in the deep STI region.

DETAILED DESCRIPTION

As noted above, formation of multi-gate FinFET devices that includes shallow STI formation followed by an etch process may lead to an asymmetric STI near the end fins. This may result in poor short channel control and may also lead to leakage because the end fins adjacent the deep STI regions may be submerged in or covered by the STI oxide material, instead of the poly-gate material. Accordingly, embodiments of the method of formation of a device and the device described herein relate to using composite STI with silicon oxide and nitride films. The first layer of silicon nitride film creates a gap between the STI oxide and the end fins that is large enough for the gate material (e.g., polysilicon conductor) deposition. As a result, the end fins are completely wrapped around by the gate, ensuring gate control over the channel for the end fins.

FIG. 1is a cross-sectional view of a structure100used in fin and STI formation according to an embodiment of the invention. A passivation layer such as a silicon nitride (SiN) layer120is formed on a substrate110. The SiN layer120may have an exemplary thickness of about 40 nanometers (nm). A layer of an oxide such as undoped silicon glass (USG)130is formed over the SiN layer120. The USG130layer may have an exemplary thickness of about 30 nm. Amorphous silicon (a-Si)160acts as a mandrel that is used to form spacers used in fin formation. The deposition of the mandrel (a-Si160) is followed by lithography which includes deposition of an anti-reflective coating such as an organic dielectric layer (ODL) and patterning using photoresist. After reactive ion etching (RIE) of the a-Si160to form the shapes shown inFIG. 1, silicon dioxide (SiO2)140is deposited. The SiO2140layer may have an exemplary thickness 150 of about 18 nm.

FIG. 2shows a top view of the structure100inFIG. 1following etching to expose the mandrel. In this resulting structure200, asFIG. 2indicates, the SiO2140above the a-Si160is removed. The etching process stops at the USG130layer.FIG. 3is a cross-sectional view of the structure200shown inFIG. 2. As indicated, the fin pitch is defined by the spacing210and may be, for example, 42 nm with the spacer (SiO2140) thickness controlled to 10 nm. In this case, the spacing220may be, for example, 84 nm.FIG. 4is a top view of the structure400that results from a mandrel pull on the structure200shown inFIGS. 2 and 3. The removal via etching of the a-Si160(mandrel) may be referred to as the mandrel pull.FIG. 5is a cross-sectional view of the structure400shown inFIG. 4. The pitch indicated by spacing210and, consequently, the fin spacing is unchanged by the mandrel pull. The USG130layer is unaffected by the mandrel pull.

FIG. 6is a top view of the structure600following deposition and patterning of an organic dielectric layer (ODL)610on the structure400shown inFIGS. 4 and 5.FIG. 7is a cross-sectional view of the structure600shown inFIG. 6. The ODL610is deposited on the USG130layer next to the fin spacers (SiO2140).FIG. 8shows the structure800resulting from a lithography process on the structure600shown inFIGS. 6 and 7to transfer the spacer (SiO2140) pattern into the USG130and SiN layer120. The fin spacers (SiO2140) are removed by the lithography. By depositing the ODL610prior to patterning (as shown inFIGS. 6 and 7), the area of the substrate110below the ODL610is kept intact during reactive ion etching (RIE) of the SiN layer120and the USG130layer, as shown inFIG. 9.

FIG. 9shows the structure900resulting from reactive ion etching of the structure800shown inFIG. 8to form the fins910. The fins910are etched by the RIE process, thereby exposing the region920for STI deposition. The depth of the fins910may be, for example, 100 nm. The SiN layer120and USG130layer are removed and the substrate110that was below the ODL610deposition is left intact. The RIE process to etch the fins910is followed by deposition of a high-aspect-ratio process (HARP) oxide930. The deposition may be achieved by a chemical vapor deposition (CVD) process using tetraethylorthosilicate (TEOS), for example.FIG. 10shows the structure1000resulting from planarization of the structure900shown inFIG. 9. The planarization may be accomplished by a chemical-mechanical planarization (CMP) process, for example. AsFIG. 10illustrates, the planarization process results in a fin region1010for field effect transistors (FETs) and a planar region1020for passive devices (e.g., electrostatic-sensitive device (ESD)).

FIG. 11shows the structure1100resulting from an etch of the structure1000shown inFIG. 10to recess the HARP oxide930, followed by deposition of an oxide film1110. For simplicity, only the fin region1010is shown inFIG. 11, and the planarization region1020is not shown. The fins910are etched to expose the region920for STI deposition. An oxide film1110is deposited over the fins910and region920for STI deposition.FIG. 12shows a structure1200following deposition of an SiN1210layer and an ODL1220on the structure1100shown inFIG. 11. A passivation layer such as silicon nitride (SiN)1210is first deposited. The SiN1210may be deposited with a thickness of 60 nm, for example. The SiN1210is deposited in the exposed portion of the region920for STI deposition. The SiN1210deposition is followed by deposition of an optical planarizing under-layer (OPL) silicon containing anti-reflective coating (SiARC) and resist coating (ODL)1220. The ODL1220may be deposited with a thickness of 200 nm, for example.FIG. 13shows the structure1300following the formation of a deep STI region1310. Following a hardmask etch removing the ODL1220layer from the structure1200shown inFIG. 12, the substrate110in the deep STI region1310is etched to a specified depth. This process may be referred to as a dual-STI active silicon cut process. The remaining region920for STI deposition is the shallow STI region.

At this stage, STI oxide may be deposited in the deep STI region1310in a conventional process that may result in one side of the end fin910abeing covered in the STI oxide and leading to the leakage issues discussed above.FIG. 14shows the result of depositing an STI oxide in the deep STI region of the structure1300shown inFIG. 13. AsFIG. 14indicates, the side of the end fin that is closest to the deep STI region is covered by the STI oxide.FIG. 15shows the structure ofFIG. 14following deposition of gate material. AsFIG. 15illustrates, the gate material cannot cover the side of the end fin closest to the deep STI region because of the STI oxide. According to an embodiment of the invention, STI oxide is not deposited in the deep STI region1310shown inFIG. 13as it is in prior artFIGS. 14 and 15.

FIG. 16shows the structure1400following redeposition of the SiN1210on the structure1300shown inFIG. 13. The SiN1210film covers the bottom and sidewalls of region920for STI deposition and the deep STI region1310. The SiN1210also covers both sides of the fins910, including end fin910a.FIG. 17shows the structure1500following deposition and etch back of an STI oxide1510in the structure1400shown inFIG. 16. AsFIG. 17illustrates, the previously re-deposited SiN1210shields the end fin910afrom the STI oxide1510.

FIG. 18shows the structure1600following anneal and etch back of the SiN1210of the structure1500shown inFIG. 17. The STI oxide1510may first be annealed. The anneal process may be performed at1150degrees Celsius for30minutes, for example. The SiN1210portions may then be etched back through deposition of HARP, for example. AsFIG. 18illustrates, the deposition (re-deposition) of SiN1210prior to the deposition of the STI oxide1510facilitates the formation of the gap1610on the side of the end fin920aon the deep STI region1310side. That is, the portion of the SiN1210between the STI oxide1510and the side of the end fin910a(in the gap1610) is etched to a specified depth. In the example shown byFIG. 18, the depth is such that a same portion of the fins910(including the deep STI region1310side of the end fin910a) is exposed for subsequent deposition of the gate material1710(FIG. 19). That is, the fin reveal on both sides of the end fin910ais the same and, consequently, the channel width on both sides of the end fin910awill be the same. The significance of this gap1610is that it prevents STI oxide1510from covering the end fin920a, thereby mitigating the leakage issues discussed above. At this stage, the structure1600undergoes formation of n-type and p-type wells through implantation of phosphorous or difluoroboron (BF2), respectively, as also indicated inFIG. 18.

FIG. 19shows the structure1700following formation of the gate material1710. The gate material1710may be a polysilicon (polycrystalline silicon). Because of the gap1610created on the deep STI region1310side of the end fin910abetween the STI oxide1510and the end fin910a, the gate material1710fills the gap1610and completely wraps around the end fin910a. As a result, gate control over the channel for the end fin910ais ensured and the potential leakage issues discussed above are avoided.