Data strobe synchronization circuit and method for double data rate, multi-bit writes

A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe pulse responsive to each global data strobe pulse. The control circuit receives a write control signal. When the write control signal becomes active, the control circuit terminates the enable signal applied to the first logic circuit and applies an enable signal to the second logic circuit. The second logic circuit then generates a second data strobe pulse responsive to the next global data strobe pulse. The first and second data strobe pulses are used to latch a data signal in respective flip-flops. The data strobe pulses may latch the data signal in pairs of flip-flops on the leading and trailing edges of the data strobe pulses.

TECHNICAL FIELD

This invention relates to memory devices, and, more particularly to a circuit and method for strobing multiple bits of write data into a double data rate memory device.

BACKGROUND OF THE INVENTION

Memory devices, such as dynamic random access memory (“DRAM”) devices, are commonly used in a wide variety of applications, including personal computers. A great deal of effort has been devoted, and is continuing to be devoted, to increasing the speed at which memory devices are able to read and write data. Initially, memory devices operated asynchronously, and a single set of data were read from or written to the memory device responsive to a set of memory commands. The data bandwidth of memory devices were subsequently increased by reading and writing data in synchronism with a clock signal. Synchronously reading and writing data also allowed for other advances in the data bandwidth of memory devices, such as burst mode and page mode DRAMs, in which a large amount of data could be transferred with a single memory command.

Synchronous memory devices such as DRAMs initially transferred data in synchronism with one edge (either rising or falling) of a clock signal each clock cycle. However, with increases in the widths of data paths in synchronous memory devices, it subsequently became possible to transfer data in synchronism with both the rising edge and the falling edge of each clock cycle. As a result, these “double data rate” (“DDR”) memory devices transferred data twice each clock cycle. When data is read from or written to a DDR memory device, the data registered with both edges of the clock signal are internally transferred in a single read or write operation. Therefore, although DDR memory devices support twice the data bandwidth of a conventional synchronous memory device, they operate internally at the same speed as a conventional memory device. DDR memory devices are able to provide twice the data bandwidth compared to conventional synchronous memory devices because they have internal data paths that are twice as wide as the data paths in conventional memory devices.

In an attempt to further increase the data bandwidth of memory devices, DDR2memory devices have been developed. Date are transferred to or from DDR2memory devices on each edge of two adjacent clock cycles, although, like conventional DDR memory device, data are transferred internally over a relatively wide data path in a single read or write operation. Thus, DDR2memory devices have twice the data bandwidth of conventional DDR memory devices, which are now known as “DDR1” memory devices.

At high operating speeds, the timing of a data strobe (“DS”) signal, which is used to capture write data at data bus terminals can vary somewhat. Therefore, in practice, a data strobe window exists during which data strobe signals are considered valid. The DS window is centered on each edge of a pair of DS pulses and extend before and after each edge by ¼ clock period. During each of these windows, the data applied to a data bus terminal of the memory device must be considered valid.

One problem that may exist with DDR2memory devices is that noise on the DS line in a “preamble” prior to the first DS pulse may be misinterpreted as a DS pulse, particularly where the DS pulse is substantially delayed relative to the data. As a result, the first and second edges of the first DS pulse, (i.e., DS0and DS1) will be interpreted as the third and fourth data strobe transitions DS2and DS3, and the true DS2and DS3transitions will be ignored. Under these circumstances, the incorrect write data may be strobed into the memory device.

There is therefore a need for a circuit and method that is substantially immune to noise on the data strobe line of DDR2memory devices to avoid capturing spurious data.

SUMMARY OF THE INVENTION

A data strobe synchronization circuit generates first data strobe signals responsive to global data strobe signals, but does not generate a second data strobe signal responsive to a global data strobe signal until a write control signal is generated. The data strobe signals are used to store respective samples of a data signal in respective storage devices so that data signal samples obtained responsive to the first data strobe signals are overwritten with data signal samples obtained responsive to subsequent data strobe signals. When the write control signal is generated, the first data strobe signals are no longer generated responsive to the global data strobe signals. As a result, a data signal sample last obtained prior to the write control signal being generated is saved and a data signal sample obtained after the write control signal is saved.

DETAILED DESCRIPTION OF THE INVENTION

One embodiment of a data strobe circuit10that is insensitive to noise on data strobe lines and thus captures write data responsive only to valid data strobes is shown in FIG.1. As explained more fully below, the circuit10operates by strobing data on each transition of a DS pulse on a data strobe DS line, saving the data strobed on the last two transitions prior to a predetermined write command, and saving the data strobed on the first two transitions following the predetermined write command. As a result, any data strobed by noise signals in the preamble are overwritten with correctly strobed data.

With reference toFIG. 1, the data strobe circuit10includes a data strobe input circuit14and a data input latch circuit18. As described in greater detail below, the data strobe input circuit14functions to generate data strobe signals, and the data input latch circuit18uses those strobe signals to latch four bits of write data.

The data input latch circuit18includes 4 flip-flops22,24,26,28each of which includes a data (“D”) input coupled to a respective DQPAD line. The DQPAD lines to of all of the flip-flops22-28are coupled to a common data bus terminal (not shown). The flip-flops22-28are clocked by a respective data strobe signal, DSA, DSAi, DSB, DSBi, where the “i” designates a complement signal. Thus, DSAi is the complement of DSA. As explained below, the DSA, DSAi, DSB and DSBi signals are generated by the data strobe input circuit14. The DSA signal is the data strobe for the first data bit, the DSAi signal is the data strobe for the second data bit, the DSB signal is the data strobe for the third data bit, and the DSBi signal is the data strobe for the fourth data bit. Thus, after all of these data strobe signals have occurred, the collective write data for a single write cycle are captured by the flip-flops22-28.

The first and second write data bits are applied as Ldin0and Ldin1signals to the data inputs of respective flip-flops32,34. The flip-flops32,34are clocked by a Write1signal, which is conventionally generated in DDR2memory devices one clock cycle before the write data are written to an array of memory cells in the memory device. The flip-flops32,34then output respective first and second bits of write data, Din0and Din1, respectively. The third and fourth bits of write data, Din2and Din3, are output directly from the flip-flops26,28at about the same time that the Write1signal becomes active. The flip-flops32,34are used to output the first and second bits of write data to the memory array so that all four bits of write data will be presented to the memory array at substantially the same time.

As mentioned previously, the data input latch circuit18generates the data strobe signals, DSA, DSAi, DSB and DSBi at the proper time, and it does so in a manner that does not result in the capture of data responsive to noise signals. The DSA signal is generated by an inverter40from its complimentary DSAi signal, and the DSB signal is similarly generated by an inverter42from its complimentary DSBi signal. The DSAi and DSBi signals are, in turn, generated by respective logic circuits46,48. The function of the logic circuits46,48is to pass a global data strobe DS signal whenever the logic circuit46,48is enabled by a high enable data strobe input (“EDSIN”) signal and either the logic circuit46or the logic circuit48is selected by a high ENA or ENB signal, respectively.

One embodiment of the logic circuit46,48is illustrated in FIG.2. The logic circuit46,48includes a NAND gate50that is enabled by a high Si input, which, as shown inFIG. 1, is coupled to receive the EDSIN signal. As explained in greater detail below, the EDSIN signal is switched to active high by a write enable signal and is switched to inactive low when 4 bits of data have been captured by the data strobe signals DSA, DSAi, DSB and DSBi, respectively.

The other input to the NAND gate50is coupled to the output of a multiplexer52that receives the data strobe DS signal at its data input and is enabled by an active high MUXN signal and an active low MUXP signal. As shown inFIG. 1, the MUXN signal is active high and the MUXP signal is active low whenever the ENA or ENB signal coupled to the logic circuits46,48, respectively, is active high. Thus, the output of the NAND gate50will be the compliment of the DS signal whenever the EDSIN signal is active high and the respective enable signal ENA or ENB is high. The output of the NAND gate is coupled to the multiplexer input to the NAND gate50by an inverter56so that the output of the NAND gate50will be latched after the multiplexer52is disabled. The latched output of the NAND gate50is reset high when the EDSIN signal transitions low as described below.

Returning toFIG. 1, since the logic circuits46,48, the ENA and ENB signals that enable the logic circuits46,48are generated by a flip-flop60. However, since the active high MUXN for the logic circuit46is coupled to the Qi output of the flip-flop60and the active high MUXN for the logic circuit48is coupled to the Q output of the flip-flop60, the logic circuits46,48are alternatively enabled. More specifically, when the flip-flop60is reset, the logic circuit46is enabled. Setting the flip-flop60then enables the logic circuit48.

The flip-flop60is reset by a high at the output of a NAND gate64, which occurs whenever either input to the NAND gate64is low. An active low enable data strobe ENDSi signal is normally low, so an inverter66normally enables the NAND gate64. The other input to the NAND gate64is coupled to a pulse generator68, which outputs a low-going pulse responsive to a rising edge of the DSBi signal. As explained above, the DSBi signal is generated by the logic circuit48, and it transitions high upon strobing the fourth data bit into the flip-flop28. Thus, the flip-flop60is reset to enable the logic circuit46when the logic circuit48outputs the data strobe signal DSBi to strobe the fourth bit of data.

The flip-flop60is clocked by a DSC signal at the output of a NOR gate70. The signal applied to the data D input of the flip-flop60is the ENA signal that is generated at the Qi output of the flip-flip60. Therefore, the flip-flop60toggles when clocked by the output of the DSC signal. The NOR gate70is enabled by an active low Write2i signal, which is generated 2 clock periods before data are written to a memory array in a memory device containing the data strobe circuit10. When enabled 2 clock periods before a data write operation, the flip-flop60is clocked by a pulse from a pulse generator74, which occurs on the rising edge of the DSAi signal. As explained above, the DSAi signal is used to latch the second bit of data into the flip-flop24. The DSAi signal transitions high when the DS signal applied to the logic circuit46transitions low and the logic circuit46is enabled. Thus, the logic circuit46is initially enabled so that the DSA and DSAi signals are continuously generated from the DS signal. The trailing edges of the DSAi pulses cause the pulse generator74to apply respective pulses to the NOR gate70. However, these pulses are ignored until 2 clock periods before a write operation because the Write2i signal is inactive high. When the Write2i signal becomes active low, the rising edge of the next DSAi pulse causes a DSC pulse to be generated, which toggles the flip-flop60to enable the logic circuit48. The logic circuit48then generates the DSB and DSBi signals from the next two transitions of the DS signal. As previously explained, these DSB and DSBi signals latch the third and fourth bits of data into the flip-flops26,28, respectively. The rising edge of the DSBi signal used to latch the fourth bit of data triggers the pulse generator68to generate a pulse that resets the flip-flop60to again enable the logic circuit46. In summary, when the Write2i signal becomes active, the data strobe circuit10strobes the two bits of data into the flip-flops22,24, respectively, on the last two DS transitions prior to the Write2i signal becoming active. The data strobe circuit10then strobes the next two bits of data into the flip-flops26,28, respectively.

As mentioned above the logic circuits46,48are enabled by an EDSIN signal applied to their Si inputs. The EDSIN signal is generated by a flip-flop80formed by two NOR gates84,86, the output of which is coupled through an inverter90. The flip-flop80is set to enable the logic circuit46,48by applying a high data strobe write enable DSWE signal to the NOR gate84. The flip-flop80is reset to disable the logic circuits46,48and reset their outputs high either applying an active low BRSTi signal to an inverter94or by applying an inactive high ENDSi signal to the NOR gate86. However, as mentioned above, the ENDSi signal is normally active low during the operation of the data strobe circuit10, so the NOR gate86is normally enabled. A low transitioning BRSTi pulse, which resets the flip-flop80, is generated at the output of the pulse generator68whenever the DSBi signal transitions high. As previously explained, this occurs when the fourth bit of data is latched into the flip-flop28. However, since the DSWE is normally high when the data strobe circuit10is active, these BRSTi pulses do not reset the flip-flop80to disable the logic circuits46,48. However, when the data strobe circuit10is to be disabled for a write operation, the DSWE signal transitions low to allow the BRSTi pulse to be generated when the fourth bit of data has been strobed into the flip-flop28.

The operation of the entire data strobe circuit10will now be explained with reference to the timing diagram shown inFIG. 3, which shows various signals present in the circuit ofFIG. 2over a 150 ns time period as indicated at the top of FIG.3.FIG. 3Ashows a clock signal that provides the basic timing for a memory device (not shown) containing the data strobe circuit10of FIG.1.FIG. 3Bshows a data strobe signal DS having several pulse pairs each of which is used for strobing 4 bits of data into the memory device. As further shown inFIG. 3B, a pair of noise pulses occur on the DS line starting at about 115 ns. As explained above, the logic circuit46is initially enabled so that each DS pulse shown inFIG. 3Bcauses a DSA pulse to be generated, as shown in FIG.3C. This DSA pulse latches the first and second data bits into the flip-flops22,24, respectively. When each DSA pulse is generated, the Write2i signal shown inFIG. 3Jis active low so that the falling edge of the DSA pulse (the rising edge of the DSAi pulse) causes a DSC pulse to be generated at the output of the NOR gate70, as shown in FIG.3H. Each of these DSC pulses toggles the flip-flop60, thereby disabling the logic circuit46and enabling the logic circuit48. As a result, the subsequent DS pulse causes a DSB pulse to be generated, as shown In FIG.3D. Each DSB pulse latches the third and fourth data bits into the flip-flops26,28, respectively, and causes a DSR pulse to be generated at the output of the NAND-gate64, as shown in FIG.3I. This DSC pulse resets the flip-flop60, thereby enabling the logic circuit46and disabling the logic circuit48so that the subsequent DS pulse generates a DSA pulse rather than a DSB pulse, as explained above.

The manner in which the data strobe circuit10is insensitive to noise pulses on the data strobe line DS will now be explained with reference toFIGS. 1 and 3. When the noise pulses are generated between 115-120 ns, they each cause a DSA pulse to be generated as shown inFIG. 3C, which latches data into the flip-flops22,24. However, when the first true DS pulse occurs at the 120 ns time, the spurious data latched into the flip-flops22,24is overwritten with data latched by the leading and trailing edges of this DS pulse. Significantly, the noise pulses do not toggle the flip-flop60, which would result in the disabling of the logic circuit46and enabling of the logic circuit48. If the logic circuit48was enabled, the true DS signal would generate a DSB pulse, which would latch the first and second data bits into the flip-flops26,28for the third and fourth data bits. The reason why the noise pulses do not toggle the flip-flop60is that the Write2i signal shown inFIG. 3Jis inactive high when the noise pulses are present. As a result, the falling edge of the DSA signal is not coupled through the nor gate70, and it therefore cannot clock the flip-flop60. Thus, the first DS pulse occurring after the noise pulses causes the first and second data bits to be latched into the flip-flop22,24, and the second DS pulse occurring after the noise pulses causes the third and fourth data bits to be latched into the flip-flops26,28. The data strobe circuit10is thus insensitive to noise pulses in the preamble prior to the first DS pulse.

One embodiment of a memory device using the data strobe circuit10ofFIG. 1or some other embodiment of the invention is shown in FIG.4. The memory device illustrated therein is a synchronous dynamic random access memory (“SDRAM”)100, although the invention can be embodied in other types of synchronous DRAMs, such as packetized DRAMs and RAMBUS DRAMs (RDRAMS”), as well as other types of digital devices. The SDRAM100includes an address register112that receives either a row address or a column address on an address bus114. The address bus114is generally coupled to a memory controller (not shown in FIG.4). Typically, a row address is initially received by the address register112and applied to a row address multiplexer118. The row address multiplexer118couples the row address to a number of components associated with either of two memory arrays120,12depending upon the state of a bank address bit forming part of the row address.

Associated with each of the memory arrays120,122is a respective row address latch126, which stores the row address, and a row decoder128, which applies various signals to its respective array120or122as a function of the stored row address. These signals include word line voltages that activate respective rows of memory cells in the memory arrays120,122. The row address multiplexer118also couples row addresses to the row address latches126for the purpose of refreshing the memory cells in the arrays120,122. The row addresses are generated for refresh purposes by a refresh counter130, which is controlled by a refresh controller132.

After the row address has been applied to the address register112and stored in one of the row address latches126, a column address is applied to the address register112. The address register112couples the column address to a column address latch140. Depending on the operating mode of the SDRAM100, the column address is either coupled through a burst counter142to a column address buffer144, or to the burst counter142which applies a sequence of column addresses to the column address buffer144starting at the column address output by the address register112. In either case, the column address buffer144applies a column address to a column decoder148which applies various signals to respective sense amplifiers and associated column circuitry150,152for the respective arrays120,122.

Data to be read from one of the arrays120,122is coupled to the column circuitry150,152for one of the arrays120,122, respectively. The data is then coupled through a read data path154to a data output register156, which applies the data to a data bus158.

Data to be written to one of the arrays120,122is coupled from the data bus158through a data input register160and a write data path162to the column circuitry150,152where it is transferred to one of the arrays120,122, respectively. The data strobe circuit10is coupled to the data input register160to latch four bits of data sequentially applied to the data bus158responsive to an externally generated data strobe (“DS”) signal. These four bits of data are then coupled through the write data path162to the column circuitry150,152. A mask register164may be used to selectively alter the flow of data into and out of the column circuitry150,152, such as by selectively masking data to be read from the arrays120,122.

The above-described operation of the SDRAM100is controlled by a command decoder104responsive to command signals received on a control bus170. These high level command signals, which are typically generated by a memory controller (not shown in FIG.4), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, which the “*” designating the signal as active low. Various combinations of these signals are registered as respective commands, such as a read command or a write command. The command decoder104generates a sequence of control signals responsive to the command signals to carry out the function (e.g., a read or a write) designated by each of the command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.

FIG. 5shows a computer system200containing the SDRAM100of FIG.4. The computer system200includes a processor202for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor202includes a processor bus204that normally includes an address bus, a control bus, and a data bus, which includes the data strobe signal. In addition, the computer system200includes one or more input devices214, such as a keyboard or a mouse, coupled to the processor202to allow an operator to interface with the computer system200. Typically, the computer system200also includes one or more output devices216coupled to the processor202, such output devices typically being a printer or a video terminal. One or more data storage devices218are also typically coupled to the processor202to allow the processor202to store data in or retrieve data from internal or external storage media (not shown). Examples of typical storage devices218include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor202is also typically coupled to cache memory226, which is usually static random access memory (“SRAM”), and to the SDRAM100through a memory controller230. The memory controller230normally includes the control bus106(FIG. 4) and the address bus114that are coupled to the SDRAM100. The data bus158is coupled from the SDRAM100to the processor bus204either directly (as shown), through the memory controller230, or by some other means.