Semiconductor device

A gate discharge resistor part is connected to the gate of an IGBT (Insulated Gate Bipolar Transistor). A timer circuit has its output connected to the input of the gate discharge resistor part and the input of a gate driving circuit. When an ON signal for driving the IGBT into an ON state stays input over a predetermined time period, the timer circuit outputs an H-level signal to the gate discharge resistor part and gate driving circuit. The gate driving circuit drives the IGBT into the OFF state based on the signal from the timer circuit. The gate discharge resistor part changes its resistance from a value given by a first resistor to a value given by a composite resistance of the first and second resistors.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and more particularly, to a technique of controlling overvoltage generated in an inductive load when forcedly stopping a switching device especially for the sake of protecting the semiconductor device.

2. Description of the Background Art

An ignition system for an internal combustion engine such as an automobile engine has a problem in that a control signal is held “on” due to a misoperation or the like during maintenance, causing a switching device for controlling current in an inductive load (e.g., transformer or load coil) to be kept conducting, which results in degradation in characteristics or breakdown of a semiconductor device itself or load due to heat generation.

Provided to solve this problem is a function of forcedly stopping a switching device using a timer circuit which operates after a lapse of a predetermined time period (approximately several hundred milliseconds) from the start of an ON operation. In other words, it is possible to avoid breakdown of the switching device by means of the timer circuit in the case where an ON signal stays output over a predetermined time period after the start of an ON operation due to a misoperation or the like.

In this case, a forced current interruption in the switching device may generate a great induced electromotive force in an inductive load, causing arc discharge to take place in an ignition coil with timing that a computer for controlling the ignition of an internal combustion engine is not intended to follow.

Accordingly, a ignition system limits a current interruption speed of a switching device to no more than a certain speed to control the degree of an induced electromotive force generated in an inductive load (cf. Japanese Patent Application Laid-Open No. 2002-4991).

Generally, however, output current is not linearly proportional to the gate voltage in a switching device. For instance, in an MOS gate device, output current is proportional to the square of the gate voltage. Therefore, a complicated circuit configuration and adjustment is required in order to control the switching device such that the current interruption speed is limited to no more than a certain speed.

For instance, the invention disclosed by the above-mentioned JP 2002-4991 controls an interruption speed of output current by means of the capacitance charging time. Since a large-capacitance capacitor is required to reduce the interruption speed of output current, it is difficult to reduce the circuit area. Further, an induced electromotive force varies depending on the inductance of an inductive load, which makes it necessary to vary the capacitance of the capacitor depending on the inductance of the inductive load. Therefore, it is difficult to control the induced electromotive force to be a desired clamping voltage without depending on the inductance of the inductive load.

Furthermore, when the potential at a current input terminal rises due to some unusual event while switching device is conducting, output current may increase, which causes damage to the switching device.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a technique of controlling an induced electromotive force generated in an inductive load when forcedly interrupting a switching device, with a simple circuit configuration.

It is another object of the present invention to provide a technique of controlling an induced electromotive force with high accuracy to be a desired clamping voltage irrespective of the inductance of the inductive load when forcedly interrupting the switching device.

It is still another object of the present invention to provide a technique of avoiding combustion of a switching device due to voltage rise at a current input terminal when the switching device is in an ON state.

According to a first aspect of the present invention, a semiconductor device includes a switching device having a current input terminal connected to an inductive load, a clamping device connected between a control terminal and the current input terminal of the switching device, and a discharge resistor part connected between the control terminal of the switching device and a ground potential. The switching device is driven to generate an induced electromotive force in the inductive load. The semiconductor device further includes a timer circuit for outputting a predetermined signal to the discharge resistor part when an ON signal for driving the switching device into an ON state stays input over a predetermined time period. The discharge resistor part changes its resistance to a greater value in response to the predetermined signal.

Since the discharge resistor part increases in resistance even when the switching device is forcedly driven into the OFF state in response to the predetermined signal output from the timer circuit, the switching device is held in the ON state by leakage current flowing through the clamping device, which can avoid abrupt interruption of collector current. Therefore, it is possible to control the degree of induced electromotive force generated in the inductive load without requiring a complicated circuit configuration for gradually interrupting the collector current.

According to a second aspect of the present invention, a semiconductor device includes a switching device having a current input terminal connected to an inductive load, a first clamping device connected between a control terminal and the current input terminal of the switching device, and a discharge resistor part connected between the control terminal of the switching device and a ground potential. The switching device is driven to generate an induced electromotive force in the inductive load. The semiconductor device further includes a timer circuit for outputting a predetermined signal when an ON signal for driving the switching device into an ON state stays input over a predetermined time period, and a second clamping device selectively connected between the control terminal and the current input terminal of the switching device in response to the predetermined signal. The second clamping device has a breakdown voltage smaller than a breakdown voltage in the first clamping device.

Voltage between the control terminal and current input terminal of the switching device can be clamped by the second clamping device at a breakdown voltage smaller than a breakdown voltage in the first clamping device even when the switching device is forcedly driven into the OFF state in response to the predetermined signal output from the timer circuit.

According to a third aspect of the present invention, a semiconductor device includes a switching device having a current input terminal connected to an-inductive load, a first clamping device connected between a control terminal and the current input terminal of the switching device, and a discharge resistor part connected between the control terminal of the switching device and a ground potential. The switching device is driven to generate an induced electromotive force in the inductive load. The semiconductor device further includes a second clamping device having one end connected to the current input terminal of the switching device, a transistor having a current input terminal connected to the other end of the second clamping device and a current output terminal connected to the control terminal of the switching device, a third clamping device having one end connected to the current input terminal of the transistor and the other end connected to the ground potential, and an overvoltage detecting circuit connected to the one end of the third clamping device. The overvoltage detecting circuit outputs a signal for driving the switching device into an OFF state when a breakdown voltage is applied to the third clamping device.

In the case where voltage at the current input terminal rises when the switching device is in the ON state, the switching device is forcedly brought into the OFF state. This can avoid combustion of the switching device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Preferred Embodiment

FIG. 1is a circuit diagram showing a configuration of a semiconductor device according to the present embodiment. A control circuit6has its input connected to an input terminal10and its output connected to the input of a gate driving circuit9. The gate driving circuit9has its output connected to the gate (control terminal) of an IGBT (Insulated Gate Bipolar Transistor)1serving as a switching device.

Upon receipt of an input signal VIN through the input terminal10, the control circuit6controls the input signal VIN in response to a signal sent from a monitoring circuit (not shown) for monitoring the driving status of the IGBT1, to output a control signal to the gate driving circuit9. The gate driving circuit9drives the gate of the IGBT1in response to the control signal.

The IGBT1has its collector (current input terminal) connected to one end of a primary coil constituting a load coil (inductive load)2and the cathode of a Zener diode (clamping device, first clamping device)3, and the emitter of the IGBT1is grounded. The primary coil has the other end connected to a power source12. The Zener diode3has its anode connected to the gate of the IGBT1. A secondary coil of the load coil2has one end connected to the power source12and the other end connected to one end of an ignition coil13. The other end of the ignition coil13is grounded.

The Zener diode3is connected to clamp the collector-emitter voltage in the IGBT1at a predetermined voltage (e.g., approximately 500V) or lower in order to avoid breakdown of the load coil2, and is constructed from Zener diodes connected in several tens of levels each having a breakdown voltage approximately ranging from 7 to 8V.

A resistor4has one end connected to the gate of the IGBT1and the other end connected to the drain of an NMOS transistor11. The source of the NMOS transistor11is grounded. A resistor5is connected between the source and drain of the NMOS transistor11. The resistance of the resistor5is set at such a value that leakage current in the Zener diode3turns the IGBT1on.

An inverter8has its output connected to the gate of the NMOS transistor11, and a timer circuit7has its output connected to the input of the inverter8. The output of the timer circuit7is also connected to the gate driving circuit9. The resistors4,5, inverter8and NMOS transistor11constitute a gate discharge resistor part101(discharge resistor part). The timer circuit7has its input connected to the input terminal10, and receives power from the input signal VIN.

The timer circuit7usually outputs an L-level signal, and upon receipt of an ON signal through the input terminal10, carries out a timing operation. More specifically, in the case where an ON signal stays input due to a misoperation or the like during a maintenance operation, the timer circuit7outputs an H-level signal after a lapse of a predetermined time period from the start of input of the ON signal. In the case where an ON signal does not stay input over a predetermined time period, the timer circuit7continues outputting an L-level signal. That is, the timer circuit7is configured to output a predetermined signal (an H-level signal in the above case) when an ON signal for driving the IGBT1stays input over a predetermined time period.

Next, referring toFIG. 2, a configuration of the gate driving circuit9will be described. A current mirror circuit14has its input connected to the output of the control circuit6, and its output connected to the gate of the IGBT1. An NMOS transistor15has its drain connected to the input of the current mirror circuit14, and its source grounded. The gate of the NMOS transistor15is connected to the output of the timer circuit7.

An operation of the semiconductor device of the above configuration will be described now.FIG. 3is a waveform chart of the operation of the semiconductor device according to the present embodiment. The operation of the semiconductor device is divided into two operations: one in a period during which the timer circuit7outputs an L-level signal which hereinafter will be called “a normal operation”, and the other one in a period during which the timer circuit7outputs an H-level signal which hereinafter will be called “a protecting operation”.

First, the normal operation of the semiconductor device will be described. In an initial state, collector-emitter voltage VCE of the IGBT1is equal to voltage VBof the power source12. Voltage V2of the ignition coil13is also equal to the voltage VB.

When the input signal VIN is caused to transition from the L level (OFF signal) to the H level (ON signal), the gate driving circuit9drives the gate of the IGBT1into H level. Then, the IGBT1transitions from the OFF state to the ON state.

The timer circuit7outputs an L-level signal. The output of the timer circuit7is reversed at the inverter8to be input to the gate of the NMOS transistor11as an H-level signal. Since the NMOS transistor11is brought into the ON state, current flowing in the gate discharge resistor part101flows out from the resistor4to a ground potential through the NMOS transistor11. Therefore, the resistance of the gate discharge resistor part101becomes almost equal to that of the resistor4.

With the transition of the IGBT1to the ON state, the collector-emitter voltage VCE (which hereinafter may be briefly called “voltage VCE”) drops to the ground potential, and collector current IC flowing out from the power source12through the load coil2and IGBT1gradually increases. Thereafter, when the collector current IC increases above a predetermined current value, a current limiting circuit (not shown) operates to limit the current value, causing the voltage VCE to slightly rise.

Next, upon receipt of an OFF signal, the gate driving circuit9drives the gate of the IGBT1to turn into the L level, causing the IGBT1to transition from the ON state to the OFF state. The transition of the IGBT1to the OFF state causes the collector current IC flowing through the load coil2to be abruptly interrupted as indicated by a solid line, following which an induced electromotive force is generated across the load coil2, and the voltage VCE suddenly rises.

As described above, the resistance of the gate discharge resistor part101is equal to that of the resistor4. Therefore, a gate voltage of such a level that causes the IGBT1to transition to the ON state is not generated by current as small as the leakage current flowing through the Zener diode3, and the voltage VCE rises with the IGBT1held in the OFF state.

When the voltage VCE rises above approximately 500V, a reverse current flows through the Zener diode3and resistor4. A voltage given by a product of the reverse current and the resistance of the resistor4is applied to the gate of the IGBT1, causing the IGBT1to transition to the ON state. Then, electric charge is discharged from the load coil2as collector current in the IGBT1. After electric charge is discharged from the load coil2, and the voltage VCE drops to almost the same level as the clamping voltage, the IGBT1transitions again to the OFF state. In this manner, the voltage VCE is clamped at a clamping voltage of approximately 500V by the Zener diode3.

Next, an induced electromotive force generated on the primary coil side is increased in voltage to approximately −30 kV and is conveyed to the secondary coil side, so that arc discharge takes place in the ignition coil13. Then, voltage on the primary coil side and voltage on the secondary coil side of the load coil2drop, so that the voltage VCE and voltage V2in the ignition coil13both become equal to the voltage VB.

Next, the process of the protecting operation of the semiconductor device according to the present embodiment will be described. After a lapse of a predetermined time period since the input signal VIN is turned into an ON signal, the timer circuit7outputs an H-level signal. The signal output from the timer circuit7is reversed at the inverter8, and is input to the gate of the NMOS transistor11as an L-level signal. Upon receipt of the L-level signal, the NMOS transistor11is turned into the OFF state from the ON state. Accordingly, the resistance of the gate discharge resistor part101is equal to a combined resistance of the resistors4and5.

The H-level signal output from the timer circuit7is also input to the NMOS transistor15(seeFIG. 2) of the gate driving circuit9. Then, the NMOS transistor15is turned into the ON state, causing the input of the current mirror circuit14to be grounded. Therefore, the output of the current mirror circuit14(output of the gate driving circuit9) is turned into the L level, causing the IGBT1to transition to the OFF state. The transition of the IGBT1to the OFF state avoids degradation of the IGBT1and load coil2resulting from continuation of the ON state over a predetermined time period.

With the transition of the IGBT1to the OFF state, the collector current IC is gradually interrupted, so that the voltage VCE rises. As described, the resistance of the gate discharge resistor part101is equal to the combined resistance of the resistors4and5as described above. By setting the resistance of the resistor5, the combined resistance is set at such a value that the IGBT1is turned on almost by the leakage current flowing through the Zener diode3. When the voltage VCE rises to approximately 30 V, a gate voltage of sufficient level for holding the IGBT1in the ON state is applied to the gate of the IGBT1. Therefore, even when the gate driving circuit9outputs an L-level signal, the IGBT1does not completely transition to the OFF state, and the collector current IC is gradually reduced as indicated by broken lines. When the collector current IC becomes zero, the IGBT1is completely turned into the OFF state, and the voltage VCE becomes VB.

As described above, controlling the gate voltage applied in the protecting operation by appropriately selecting the resistance of the resistor5limits the voltage VCE not to rise above approximately 30V. Further, as indicated by the broken lines inFIG. 3, the voltage V2in the ignition coil13is also limited not to rise above approximately −3000V, which avoids the occurrence of arc discharge.

Here, the voltage VCE in the protecting operation (referred to as 30V in this example) is assumed to be greater than the voltage VB(assumed to be the nominal voltage 12V of a general-automotive battery in this case) in the power source12and to have such a value that arc discharge dose not take place in the ignition coil13. In other words, the voltage VCE in the protecting operation may be set at a value in accordance with the value of the voltage VBin a system to be used and the like.

FIG. 4is a circuit diagram showing an example of a semiconductor device of the background art of the present invention. As shown inFIG. 4, the semiconductor device of the background art is provided with a resistor16connected in place of the gate discharge resistor part101.

FIG. 5is a circuit diagram showing a configuration of the gate driving circuit9for use in the semiconductor device of the background art. An inverter22has its input connected to the output of the timer circuit7(seeFIG. 4), and its output connected to the gate of an NMOS transistor20. The source of the NMOS transistor20is grounded, and its drain is connected to one end of a current source18and one end of a capacitor21.

The other end of the current source18is connected to a power source not shown, and the other end of the capacitor21is grounded. The one end of the capacitor21is also connected to a minus terminal of a subtracter23. The subtracter23has its plus terminal connected to the output of the control circuit6(seeFIG. 4). The current mirror circuit14has its output connected to the gate of the IGBT1. Here, the subtracter23is a circuit for outputting current in accordance with a potential difference between the plus and minus terminals.

The operation of the semiconductor device of the background art will be described now. In the normal operation, an L-level signal input from the timer circuit7is inverted at the inverter22, and is input to the gate of the NMOS transistor20. Therefore, current flowing out from the current source18flows to the ground potential through the NMOS transistor20. An ON signal output from the control circuit6is directly input to the current mirror circuit14through the subtracter23. The current mirror circuit14amplifies and outputs current output from the subtracter23. In the ON state of the IGBT1, current output from the current mirror circuit14flows through the resistor16, so that voltage of sufficient level for holding the IGBT1in the ON state is applied to the gate of the IGBT1.

When an ON signal stays input through the input terminal10over a predetermined time period, the timer circuit7outputs an H-level signal. Then, the semiconductor carries out the protecting operation. The signal output from the timer circuit7is reversed at the inverter22(seeFIG. 5), and is input to the gate of the NMOS transistor20, causing the NMOS transistor20to transition to the OFF state. When the NMOS transistor20transitions to the OFF state, current flowing out from the current source18gradually charges the capacitor21.

As described above, the capacitor21has its one end connected to the minus terminal of the subtracter23. The subtracter23outputs current in accordance with a potential difference between a control signal output from the control circuit6and a potential at the one end of the capacitor21. Therefore, output current from the subtracter23is gradually reduced. With such reduction, voltage applied to the gate of the IGBT1drops, causing the collector current IC flowing through the IGBT1to be gradually interrupted.

Upon completion of charging of the capacitor21, output current from the subtracter23is reduced to zero. Thus, output current from the current mirror circuit14is also reduced to zero, so that the IGBT1is completely brought into the OFF state, causing an interruption of the collector current IC. Since the collector current IC is gradually interrupted, a great induced electromotive force is not generated at the load coil2, which avoids the occurrence of arc discharge in the ignition coil13.

As described above, the semiconductor device of the background art employs the subtracter23and capacitor21to control an interruption speed of output current from the gate driving circuit9by a charging speed of the capacitor21, and is configured to limit an interruption speed of the collector current IC to such a speed that a great induced electromotive force is not generated.

Accordingly, the gate driving circuit9has a complicated configuration including the current source18, capacitor21, subtracter23and the like. To sufficiently reduce the interruption speed of the collector current IC, the capacitor21needs to be increased in capacitance, making it difficult to reduce the circuit area of the semiconductor device.

Further, the interruption speed of the collector current IC is controlled by the degree of capacitance of the capacitor21, making it necessary to set the capacitance of the capacitor21in accordance with the number of turns of the load coil2.

Furthermore, in the case where power for driving the subtracter23needs to be obtained from the input signal VIN, power supplied to the subtracter23may be reduced due to ground lift or the like, which may cause the subtracter23not to operate.

In the present embodiment, it is not necessary to control the interruption speed of output current from the gate driving circuit9, and output current is simply interrupted when an H-level signal is input from the timer circuit7. Since there is no need to use a capacitor, the circuit area can be reduced.

The resistance of the resistor5is adjusted to control voltage applied to the gate of the IGBT1, so that the degree of a clamping voltage for clamping the voltage VCE can be controlled. In other words, the voltage VCE can be clamped at a desired clamping voltage irrespective of the inductance of the load coil2to be used.

The present embodiment employs the NMOS transistor11to constitute the gate discharge resistor part101, however, a PMOS transistor24may be employed instead as shown inFIG. 6.

FIG. 6shows an exemplary configuration in which the gate discharge resistor part101includes the PMOS transistor24. A buffer45has its input connected to the output of the timer circuit7, and its output connected to the gate of the PMOS transistor24. The resistor4is inserted between the source and drain of the PMOS transistor24. The PMOS transistor24has its source connected to the gate of the IGBT1, and its drain grounded. In the present embodiment, a resistor of great resistance is used as the resistor4, and a resistor of small resistance is used as the resistor5. Other configuration is the same as that of the semiconductor device shown inFIG. 1, repeated explanation of which is thus omitted here. The operation is also the same as that of the configuration shown inFIG. 1, explanation of which is omitted here.

In the above configuration, an IGBT is used as a switching device, however, the present invention is also applicable to a semiconductor device using a power MOSFET or the like. Further, the circuit area can be reduced by forming the components except the load coil2on the same semiconductor substrate.

Second Preferred Embodiment

FIG. 7is a circuit diagram showing a configuration of a semiconductor device according to the present embodiment. A Zener diode28(second clamping device) has its cathode connected to the collector of the IGBT1and its anode connected to the source of a PMOS transistor27and one end of a resistor29. The PMOS transistor27has its drain connected to the gate of the IGBT1. A breakdown voltage in the Zener diode28is set at the same value as the Zener diode3.

The resistor29has the other end connected to the gate of the PMOS transistor27and the drain of an NMOS transistor26. The source of the NMOS transistor26is grounded. A buffer circuit25has its output connected to the gate of the NMOS transistor26and its input connected to the output of the timer circuit7.

Since other configuration is the same as that described in the first preferred embodiment, similar components are indicated by the same reference numbers, and repeated explanation is omitted here.

The operation of the semiconductor device according to the present embodiment will be described now. In the normal operation, an L-level signal output from the timer circuit7is input to the gate of the NMOS transistor26through the buffer circuit25. Thus, the NMOS transistor26is in the OFF state. The PMOS transistor27is not turned on, and the Zener diode28is not connected between the gate and collector of the IGBT1. Therefore, the gate-collector voltage in the IGBT1is clamped by the Zener diode3. Then, the voltage VCE rises up to about the same level as the clamping voltage in the Zener diode3, so that discharge takes place at the ignition coil13.

In the protecting operation, upon receipt of an H-level signal from the timer circuit7, the NMOS transistor26is brought into the ON state. The gate of the PMOS transistor27is grounded through the NMOS transistor26, bringing the NMOS transistor27into the ON state. Therefore, the Zener diodes28and3are connected in parallel between the gate and collector of the IGBT1.

In the protecting operation, leakage current flowing through the Zener diodes28and3flows into the resistors4and5, causing the IGBT1to be held in the ON state. As a result, similarly to the semiconductor device according to the first preferred embodiment, the collector-emitter voltage VCE is clamped at a desired clamping voltage, which avoids the occurrence of arc discharge in the ignition coil13.

The semiconductor device according to the present embodiment achieves the following effects in addition to similar effects achieved by the first preferred embodiment.

The configuration according to the first preferred embodiment ensures a gate voltage necessary for turning on the IGBT1only by leakage current flowing through the Zener diode3. It is therefore necessary to set the resistance of the resistor5at a great value.

In the present embodiment, leakage current flowing through the Zener diode28is added to leakage current flowing through the Zener diode3, allowing the resistance of the resistor5to be set lower than in the first preferred embodiment. Therefore, the circuit area can be reduced more than in the first preferred embodiment.

In the above configuration, an IGBT is used as a switching device, however, the present invention is also applicable to a semiconductor device using a power MOSFET or the like. Further, the circuit area can be reduced by forming the components except the load coil2on the same semiconductor substrate.

Third Preferred Embodiment

FIG. 8is a circuit diagram showing a configuration of a semiconductor device according to the present embodiment. In the present embodiment, the resistor (discharge resistor part)16is connected to the gate of the IGBT1in place of the gate discharge resistor part101. The Zener diode28is configured to have a breakdown voltage equal to a desired clamping voltage (e.g., approximately 30V) for clamping the voltage VCE.

Since other configuration is the same as that described in the second preferred embodiment, similar components are indicated by the same reference numbers, and repeated explanation is omitted here.

The operation of the semiconductor device according to the present embodiment will be described now. In the normal operation, an L-level signal output from the timer circuit7is input to the gate of the NMOS transistor26through the buffer circuit25. The NMOS transistor26is brought into the OFF state, and the gate of the PMOS transistor27is not grounded through the NMOS transistor26, thus brought into the OFF state.

Therefore, the collector-emitter voltage VCE is clamped by the Zener diode3. That is, the voltage VCE can rise up to approximately 500V, causing the ignition coil13to carry out arc discharge.

Next, in the protecting operation, an H-level signal is output from the timer circuit7. Upon receipt of the signal output from the timer circuit7, the IGBT1is driven into the OFF state, which avoids degradation of the IGBT1and load coil2resulting from continuation of the ON state.

The output of the timer circuit7is also input to the gate of the NMOS transistor26through the buffer circuit25, causing the NMOS transistor26to transition to the ON state. The gate of the PMOS transistor27is grounded through the NMOS transistor26, and is brought into the ON state. As a result of the transition of the PMOS transistor27to the ON state, the Zener diode28is connected between the gate and collector of the IGBT1through the PMOS transistor27.

A breakdown voltage in the Zener diode28is set lower than that of the Zener diode3. Thus, when the IGBT1is brought into the OFF state, the collector-emitter voltage VCE is clamped at a clamping voltage which is almost determined by the Zener diode28.

Since the first and second preferred embodiments utilize leakage current in the Zener diodes, it is difficult to set a desired clamping voltage under temperature conditions of wide range.

In the present embodiment, a desired clamping voltage can easily be achieved under temperature conditions of wide range by appropriately selecting a breakdown voltage in the Zener diode28.

In the present embodiment, the PMOS transistor27is connected to the Zener diode28, however, an NMOS transistor30may be employed instead of the PMOS transistor27as shown inFIG. 9.

In the circuit configuration shown inFIG. 9, the NMOS transistor30has its drain connected to the anode of the Zener diode28and its source grounded. One end of a resistor31and the output of a buffer32are connected to the gate of the NMOS transistor30. The other end of the resistor31is connected to the gate of the IGBT1. The output of the timer circuit7is connected to the input of the buffer32. Other configuration is the same as that shown inFIG. 8, repeated explanation of which is thus omitted here.

The operation will be described now. In the normal operation, an L-level signal is output from the timer circuit7, and is input to the gate of the NMOS transistor30through the buffer32. Then, the NMOS transistor30is brought into the OFF state, and the gate-collector voltage in the IGBT1is clamped by the Zener diode3in the normal operation.

Next, when an ON signal stays input to the gate of the IGBT1over a predetermined time period, the timer circuit7outputs an H-level signal. Then, the NMOS transistor30transitions to the ON state, causing the Zener diode28to be connected between the gate and collector of the IGBT1.

Since the breakdown voltage in the Zener diode28is set lower than that of the Zener diode3. The gate-collector voltage in the IGBT1is clamped by the Zener diode28in the protecting operation. Appropriately selecting the breakdown of the Zener diode28, the clamping voltage in the protecting operation can be set at a desired value with high accuracy.

In the above configuration, an IGBT is used as a switching device, however, the present invention is also applicable to a semiconductor device using a power MOSFET or the like. Further, the circuit area can be reduced by forming the components except the load coil2on the same semiconductor substrate.

Fourth Preferred Embodiment

FIG. 10is a circuit diagram showing a configuration of a semiconductor device according to the present embodiment. A PNP transistor (first transistor)37has its emitter connected to the cathode of the Zener diode3and its collector (current input terminal) connected to the base of an NPN transistor (second transistor)38and the cathode of a Zener diode36. The PNP transistor37has its base connected to the collector of the NPN transistor38, and the NPN transistor38has its emitter (current output terminal) connected to one end of a resistor39. The other end of the resistor39is grounded.

Here, the PNP transistor37and NPN transistor38constitute a thyristor, and the resistor39is provided to prevent latch-up of the thyristor. Further, the PNP transistor37may be constructed using a parasitic PNP transistor of the IGBT1as disclosed in Japanese Patent Application Laid-Open No. 2000-183341.

A Zener diode35has its cathode connected to the anode of the Zener diode36and its anode connected to the cathode of a Zener diode34. The Zener diode34has its anode connected to one end of the resistor29, the drain (current output terminal) of the PMOS transistor (third transistor, transistor)27and the cathode of a Zener diode33(third clamping device). The anode of the Zener diode33is grounded.

Since other configuration is the same as that described in the third preferred embodiment, similar components are indicated by the same reference numbers, and repeated explanation is omitted here.

The operation of the semiconductor device according to the present embodiment will be described now. First, the process of the normal operation will be described. Upon receipt of an ON signal through the input terminal10, the IGBT1transitions from the OFF state to the ON state. At this time, the timer circuit7outputs an L-level signal, bringing the NMOS transistor26into the OFF state.

With the transition of the IGBT1to the ON state, the collector current IC gradually flows out from the power source12through the IGBT1. At this time, part of the collector current IC becomes emitter current in the NPN transistor37, causing the thyristor including the NPN transistor37and PNP transistor38to transition to the ON state. Then, current flows to the ground potential through the NPN transistor37, PNP transistor38and resistor39.

Next, the transition of the IGBT1to the OFF state causes the collector current IC to be abruptly interrupted, so that the collector-emitter voltage VCE rises. At this time, current does not flow into the PNP transistor37because of the abrupt interruption of the collector current IC, bringing the thyristor into the OFF state. Therefore, the Zener diodes33to36are disconnected from the semiconductor device when the IGBT1is in the OFF state. This causes the voltage VCE to be clamped by the Zener diode3. When the voltage VCE rises up to about the same level as the clamping voltage in the Zener diode3, arc discharge takes place in the ignition coil13.

Next, the protecting operation according to the present embodiment will be described. When an ON signal stays input over a predetermined time period, the timer circuit7outputs an H-level signal. The output of the timer circuit7is input to the gate of the NMOS transistor26through the gate driving circuit9and buffer circuit25.

Upon receipt of the H-level signal from the timer circuit7, the NMOS transistor26is brought into the OFF state, and the gate of the PMOS transistor27is grounded through the NMOS transistor26, thus bought into the ON state. As a result, the Zener diodes34to36are connected between the gate and collector of the IGBT1through the PNP transistor37.

Further, upon receipt of the H-level signal from the timer circuit7, the gate driving circuit9drives the IGBT1into the OFF state. Therefore, the collector current IC is abruptly interrupted, causing the collector-emitter voltage VCE to rise.

As described above, the Zener diodes34to36are connected between the gate and collector of the IGBT1through the PNP transistor37. The PNP transistor37is in the ON state, and therefore has a collector voltage (a base voltage in the NPN transistor38) nearly equal to the collector-emitter voltage VCE in the IGBT1. Therefore, the voltage VCE is clamped at a breakdown voltage of the Zener diodes34to36. The number of levels of Zener diodes used here may be varied in accordance with a desired voltage value.

Current flowing through the Zener diodes34to36is limited by the thyristor including the NPN transistor37and PNP transistor38. Therefore, the Zener diodes34to36are not broken down due to large current.

In the semiconductor device according to the present embodiment, the circuit area can be reduced by using a parasitic PNP transistor of the IGBT1as the PNP transistor37.

In the semiconductor device according to the second preferred embodiment, a rise in the collector-emitter voltage VCE in the OFF operation of the IGBT1causes a high voltage to be applied between the source and drain of the PMOS transistor27. Therefore, a PMOS transistor of high breakdown voltage needs to be used as the PMOS transistor27, which causes an increase in circuit area.

In the present embodiment, voltage applied to the PMOS transistor27is limited by the Zener diode33to no more than the breakdown voltage in the Zener diode33. Thus, a PMOS transistor of low breakdown voltage can be used as the PMOS transistor27. As a result, the circuit area can be reduced.

In the above configuration, an IGBT is used as a switching device, however, the present invention is also applicable to a semiconductor device using a power MOSFET or the like. Further, the circuit area can be reduced by forming the components except the load coil2on the same semiconductor substrate.

Fifth Preferred Embodiment

FIG. 11is a circuit diagram showing a configuration of a semiconductor device according to the present embodiment. An overvoltage detecting circuit40has its input connected to the cathode of the Zener diode33and its output input to the gate driving circuit9.

Since other configuration is the same as that described in the fourth preferred embodiment, similar components are indicated by the same reference numbers, and repeated explanation is thus omitted here.

FIG. 12is a circuit diagram showing a configuration of the overvoltage detecting circuit40. One end of a resistor44and the cathode of the Zener diode33are connected to the plus terminal of a comparator42. The other end of the resistor44is grounded.

A reference power source43is connected to the minus terminal of the comparator42. The voltage in the reference power source43is set at a value smaller than the breakdown voltage in the Zener diode33. The comparator42has its output connected to the input of a latch circuit41, and the latch circuit41has its output input to the gate driving circuit9.

Referring toFIG. 13, the operation of the semiconductor device according to the present embodiment will be described now. In the case where the voltage VCE is not greater than a breakdown voltage given by the Zener diodes33to36(e.g., approximately 30V) during the ON operation of the IGBT1, voltage input to the plus terminal of the comparator42becomes approximately zero volts, which is lower than a reference voltage. As a result, the comparator42outputs an L-level signal. The latch circuit41also continues outputting an L-level signal.

When some unusual event occurs to cause the collector-emitter voltage VCE to rise above the breakdown voltage given by the Zener diodes33to36(e.g., approximately 30V) during the ON operation of the IGBT1, current flows out from the collector of the IGBT1to the Zener diode33and resistor44through the PNP transistor37and Zener diodes34to36. As a result, voltage equal to the breakdown voltage in the Zener diode33is input to the plus terminal of the comparator42.

When the voltage input to the plus terminal of the comparator42exceeds the reference voltage, the comparator42outputs an H-level signal. Upon receipt of the output from the comparator42, the latch circuit41outputs an H-level signal. Then, the latch circuit41continues outputting the H-level signal even when the voltage VCE drops.

Upon receipt of the output from the overvoltage detecting circuit40(i.e., the output from the comparator42), the gate driving circuit9drives the IGBT1into the OFF state. Other operation is the same as that described in the third preferred embodiment, explanation of which is thus omitted here.

In the case where the voltage VCE rises when the IGBT1is in the ON state, large collector current IC flows into the IGBT1, which may cause thermal breakdown of the IGBT1.

In the present embodiment, in the case where the overvoltage detecting circuit40detects a reverse conducting voltage in the Zener diode33before the timer circuit7outputs an H-level signal, the gate driving circuit9outputs an OFF signal, causing the IGBT1to transition to the OFF state. This avoids breakdown of the IGBT1due to combustion.

In the above configuration, an IGBT is used as a switching device, however, the present invention is also applicable to a semiconductor device using a power MOSFET or the like. Further, the circuit area can be reduced by forming the components except the load coil2on the same semiconductor substrate.

In the present embodiment, the overvoltage detecting circuit40is added to the configuration described in the fourth preferred embodiment (seeFIG. 10), however, this is not a restrictive example, and the present embodiment is also applicable to another configuration. It is only required that the one end of the overvoltage detecting circuit40be connected to the cathode of the Zener diode33and that the IGBT1be driven into the OFF state by the output of the overvoltage detecting circuit40. Even if other configuration is different, similar effects are achieved.