Coreless substrate and manufacturing method thereof

The present invention discloses a method for manufacturing a coreless substrate. The method comprises the steps of (a) forming an insulating layer on one side of a metal sheet; (b) forming a via hole on the insulating layer for electrical connection between the metal sheet and the other side; and (c) forming a plurality of protruded function pads by etching the metal sheet. The coreless substrate and manufacturing method thereof in accordance with the present invention have the signal delivery characteristic that is improved by eliminating the inner via hole.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed to a substrate, more specifically to a coreless substrate and a manufacturing method thereof.

2. Description of the Related Art

As mobile phones, personal digital assistants (PDA), thin film transistor liquid crystal displays (TFT LCD) and many other electronic devices get smaller these days, the semiconductor devices that are installed in these devices are also getting smaller, thinner and lighter.

To keep up with this trend, flexible printed circuit boards (FPC), such as tape carrier packages (TCP) and chips on film (COF), in which a circuit pattern is formed on a base film, are used as a circuit board. Used for a semiconductor device package is the TAB (tape automated bonding) method, by which a pre-formed bump electrode and a circuit pattern, which is formed on a tape circuit board, are collectively bonded to a semiconductor device and the semiconductor device is mounted on the tape circuit board.

In the prior art, in order to reduce the warpage of a high-performance package substrate, a copper clad laminate core (epoxy-resin-impregnated glass fiber fabric, both sides of which are adhered with a copper foil) with a thickness of about 0.8 mm is used. In other words, the semiconductor package substrate of the prior art is a copper clad laminate on which a build-up layer is additionally formed.

FIG. 1is the sectional view of a semiconductor package substrate with a thick core layer in accordance with the prior art. Referring toFIG. 1, the semiconductor package substrate of the prior art comprises a core layer110of the copper clad laminate (CCL), a circuit130and an interstitial via hole120.

The core layer110of the CCL is generally about 400 μm˜800 μm thick, and the insulating layer laminated on the core layer110of the CCL is about 30 μm˜40 μm thick. Using a thick core layer110of the CCL may reduce the warpage problem but is hardly feasible for reducing the size of the inner via hole (IVH), which is imperative for making a high-performance package substrate. The diameter for the IVH, for electrical connection between the layers, is about 100 μm. This kind of IVH is usually formed by use of a CNC drill.

FIG. 2is a graph illustrating the noise corresponding to the diameter of an IVH formed on the semiconductor-package substrate. Referring toFIG. 2, the x-axis indicates the frequency of the signal (unit: GHz) while the y-axis indicates the noise (unit: dB).

In the frequency band of a general signal, which is 0˜6 GHz, the smaller the radius of the IVH is, the smaller the noise becomes. Thus, the diameter of the IVH must be reduced in order to improve the signal delivery characteristic of the package substrate. With a thick CCL core, however, forming a small-diameter IVH is technically very difficult. Since the IVH is formed using a CNC drill, the diameter of which is about 100 μm˜350 μm, there is limitation to how much the diameter can be reduced. Although reducing the diameter is possible, the process is very costly.

SUMMARY OF CERTAIN INVENTIVE ASPECTS

The present invention provides a coreless substrate, and a manufacturing method thereof, whose signal delivery characteristic is improved by eliminating the IVH.

The present invention also provides a coreless substrate, and a manufacturing method thereof, in which the IVH becomes thin by eliminating the core layer.

In addition, the present invention provides a coreless substrate, and a manufacturing method thereof, which can perform various functions through a single process because various function pads can be formed using a metal sheet.

Other technical objects of the present invention shall be easily understood through the following description.

An aspect of the present invention can feature a method for manufacturing a coreless substrate. The method comprises: (a) forming an insulating layer on one side of a metal sheet; (b) forming a via hole on the insulating layer for electrical connection between the metal sheet and the other side; and (c) forming a plurality of protruded function pads by etching the metal sheet.

The method can further comprise: (d) coupling the metal sheet to another metal sheet by use of an adhesive; and (e) separating the metal sheet from the adhesive. The step (d) can precede the step (a), and the step (e) can follow the step (c).

The adhesive can be adhered to the border of the two metal sheets, and the metal sheets can be separated from the adhesive by cutting off the border of the metal sheets in the step (e).

In the step (b), a circuit having a pattern can be formed on the insulating layer, and the via hole can electrically connect the circuit and the metal sheet.

The method can further comprise the step of (f) forming a solder resist on the insulating layer to protect the surface of the substrate.

The method can further comprise the step of (g) treating the surface on the function pads, using a metal.

The metal for surface treatment can be Ni or Au.

The function pads can comprise a stiffener.

The function pads can comprise a solder ball pad.

The function pads can comprise a thermal pad.

Another aspect of the present invention can feature a coreless substrate comprising: a plurality of function pads, etched from a metal sheet and having a protruded shape; an insulating layer, the insulating layer being formed on one side of the function pads, a circuit corresponding to a pattern being formed on the insulating layer, a via hole being formed on the insulating layer to electrically connect the function pads and the circuit; and a solder resist, being formed on the insulating layer to protect the surface of the insulating layer.

A circuit having a pattern can be formed on the insulating layer, and the via hole can electrically connect the circuit and the function pads.

The coreless substrate can further comprise a metal, which is surface-treated on the function pads.

The surface-treating metal can be Ni or Au.

The function pads can comprise a stiffener.

The function pads can comprise a solder ball pad.

The function pads can comprise a thermal pad.

DETAILED DESCRIPTION OF CERTAIN INVENTIVE EMBODIMENTS

Hereinafter, a preferred embodiment of the coreless substrate and the manufacturing method thereof in accordance with the present invention will be described in detail with reference to the accompanying drawings. In referencing the accompanying drawings, identical elements are given the same reference numerals, regardless of their figure numbers, and any redundant description thereof will be omitted. The substrate described hereinafter includes any substrate for delivering an electrical signal. For example, the substrate in accordance with the present invention can comprise a rigid substrate, a flex substrate, an LTCC substrate, a single-side/multi-side/multilayer substrate and a substrate for packing a semiconductor (e.g. BGA, FBGA and TBGA). Hereinafter, a semiconductor package substrate for bonding a flip chip will be described.

Generally, in order to reduce the diameter of an IVH, it is necessary to use a thinner CCL core. However, reducing the thickness of the CCL core while maintaining the present flip chip substrate structure causes warpage. Therefore, the present invention provides a package substrate structure that does not cause warpage regardless of the diameter of the IVH by realizing a structure without the CCL core, unlike the conventional package substrate structure. For this, the present invention utilizes an etched dummy metal plate, which can carry out both the role of stiffener and the role of enhancing the solder joint strength.

FIG. 3is a diagram illustrating the process of manufacturing a coreless semiconductor package substrate in accordance with a preferred embodiment of the present invention. It is possible to use both one metal sheet and two metal sheets to form an insulating layer and a circuit on one side of the metal sheet. In the description below, the insulating layer and the circuit are formed on two sides of the metal sheets320(1) and320(2) that are coupled using the adhesive310.

Referring to step (a), two metal sheets320(1) and320(2) are adhered to both sides of the adhesive310. The thickness of the metal sheet can be about 0.1˜0.2 mm, and can be determined according to the role of the function pad, which will be formed later.

In the process of manufacturing a multilayer printed circuit board, the circuit (i.e. inner layer circuit or outer layer circuit) is formed through the additive method, subtractive method or semi-additive method.

In the additive method, the circuit is formed on a printed circuit board by selectively depositing a conductive material on an insulating substrate through electroless plating or electrolytic plating to plate the conductive material on the insulating substrate and form a conductive pattern. The additive method is classified as the full-additive method and the semi-additive method, depending on the presence of a seed layer for electrolytic copper plating.

In the subtractive method, the circuit is formed on a printed circuit board by selectively etching off unnecessary portions other than the conductive material from the metal-coated insulating substrate. It is also called the “tent and etch” method because the area in which the conductive pattern is to be formed through photo resist and the inside of the hole are tented and etched. Although the semi-additive method is described hereinafter, it shall be evident that the present invention is by no means restricted to the semi-additive method.

Referring to step (b), two metal sheets320(1) and320(2) are formed on both sides of the adhesive310, and insulating layers330(1) and330(2) are stacked on one metal sheet320(1). At least one blind via hole (BVH) is formed on each of the insulating layers330(1) and330(2) for electrical connection between the layers. The via holes on the insulating layers330(1) and330(2) can be formed by use of a C02 laser or Yag laser, and therefore are smaller than the inner via holes described earlier. Then, the texturing and electroless copper plating can be performed. In addition, a solder resist350is formed in the upper part of the insulating layer330(2) in order to protect the surface of the substrate or insulating layer330(2). In other words, after testing the outer layer and measuring the scale, the solder resist350exposure film is designed and manufactured. Then, the solder resist350is pre-processed, that is, the surface of the copper foil is made rough by brush-grinding such that the solder resist350ink is better adhered to the substrate. Then, the solder resist350is coated; the solder resist350is exposed using the solder resist350exposure film adaptively designed in the previous step; the solder resist350ink is removed through a developing process; and a number of post-processes, including surface treatment and electric/final test, are carried out. Although a plurality of insulating layers330(1) and330(2) are described, a single insulating layer can be used in the present invention.

Referring to step (c), the metal sheets320(1) and320(2) are separated from the adhesive310. The adhesive310, therefore, may be made from elements that are easily adhered to and separated from the metal sheets320(1) and320(2). For this reason, the adhesive310may be a thermal release tape, which can be separated by heat. The coating process of solder resist350, described above, can be performed either before or after separating the metal sheets320(1) and320(2).

Referring to step (d), a variety of function pads are formed by etching the metal sheet320in accordance with a predetermined pattern. The function pad can be a variety of pads, including a stiffener, solder ball pad and thermal release pad.

Referring to step (e), the surface can be treated using the metal surrounding the variety of function pads formed by etching the metal sheet320. The surface treatment metal can be Ni and Au, and can be plated through an electrolytic plating process. For the package substrate for bonding a flipchip, a bumping process can be added later.

Here, the following general method of manufacturing a substrate can be added: An inner-layer base material that meets the product specification is cut, and a predetermined internal circuit pattern is formed using a dry film and a working film. Here, the inner layer can be scrubbed, an inner layer dry film can be laminated, and the inner layer can be exposed/developed. Then, prior to bonding the inner layer, on which the circuit pattern is formed, to the outer layer, a brown (black) oxide process is carried out in order to strengthen the adhesion. That is, the surface of a copper foil is chemically oxidized to enhance the surface roughness such that the lamination results in better adhesion. Then, by laminating the inner-layer substrate and a prepreg, prelamination and lamination processes are carried out. Then, the laminated inner layer substrate and the prepreg are vacuum pressed. It is possible that the laminated inner layer substrate and the prepreg are hot pressed or cool pressed, instead of being vacuum pressed. The resin and copper foil are trimmed from the comers of the panel, and an X-ray target drilling process, in which a hole is made at a target guide mark on the inner layer circuit, is carried out in preparation of a drilling process. Then, the drilling process is carried out for electric conduction between the layers of the substrate. Here, a computer numerical control (CNC) method can be used for the drilling process. Then, the outer layer is coated with the dry film and the working film in order to form a circuit pattern, exposed to a light of a predetermined intensity for a predetermined duration, and the unirradiated areas are developed in an etching process.

The general manufacturing process of a flipchip BGA package is as follows: (a) An aluminum pad is formed on a semiconductor chip and is covered with a protective layer. (b) Through a sputtering process, a metal layer is formed and is connected to the pad. (c) A photo resist is laminated such that only the pad area is open. (d) The pad area, in which the photo resist is open, is lead-plated. (e) The covered photo resist is removed. (f) The metal film outside the lead-plated area is etched off. (g) The plated lead is heated to be made round. (h) A bump chip made through the above steps is spliced to a flipchip BGA substrate. To splice the contact pad of the bump chip with the contact pad of the flipchip BGA substrate, the substrate is heated to a high temperature in a reflow device to melt the lead. Then through an underfill process, resin is filled between the flipchip BGA substrate and the chip.

FIG. 4shows a diagram of an adhesive used in the manufacturing of a coreless semiconductor package substrate in accordance with another preferred embodiment of the present invention. Referring toFIG. 4, the sectional view, which can replaceFIG. 3(a), shows an adhesive410and metal sheets420(1) and420(2).

The adhesive is applied on the border of the two metal sheets420(1) and420(2), and by cutting off the border, the metal sheets420(1) and420(2) can be separated from the adhesive410. The adhesive may be applied to a portion or the entire area of the border of the metal sheets420(1) and420(2). If the adhesive410is applied to a portion of the border of the metal sheets420(1) and420(2), it becomes easy to separate the metal sheets420(1) and420(2) from the adhesive410. If the adhesive410is applied to the entire area of the border of the metal sheets420(1) and420(2), the metal sheets420(1) and420(2) are better adhered to the adhesive410. Moreover, since the adhesive410is applied only to the border of the metal sheets420(1) and420(2), the metal sheets420(1) and420(2) can be separated from the adhesive410by cutting off the border of the metal sheets420(1) and420(2). This provides a wider range of selection of the adhesive. Since the adhesive does not need to be separated from the metal sheets, for example, an adhesive that is not easily separated from the metal sheets can be used. For this kind of tape, which is not easily separated by heat (i.e. not a thermal release tape), a general adhesive tape, a paste-type adhesive, a plating-layer-using adhesive or other varieties can be used.

So far, the manufacturing process generally illustrating a coreless substrate and a manufacturing method thereof has been described. Hereinafter, particular embodiments of the coreless substrate and manufacturing method thereof in accordance with the present invention will be described with reference to the accompanying drawings. Four major embodiments, depending on the uses of the function pad, will be described.

FIG. 5is a sectional view of a coreless semiconductor package substrate with a variety of function pads in accordance with a first preferred embodiment of the present invention. Referring toFIG. 5, the semiconductor package comprises stiffener metals520(1),520(2) and520(3), insulating layers530(1) and530(2), a via hole, a solder resist550, a surface-treating metal560, a thermal pad570and solder ball pads580(1),580(2) and580(3). The function pads can include the stiffener metals520(1),520(2) and520(3), the thermal pad570and the solder ball pads580(1),580(2) and580(3).

To form the function pads, i.e. the stiffener metals520(1),520(2) and520(3), the thermal release pad570and the solder ball pads580(1),580(2) and580(3), the metal dummy plate formed on the bottom of the substrate is exposed, developed and etched, and the dry film is peeled off. Here, several varieties of function pads can be formed simultaneously through a series of processes.

The stiffener metals520(1),520(2) and520(3) prevent the package substrate from warping. The thermal pad570can effectively release and remove the heat generated from the semiconductor chip. Function pads having solder ball pads580(1),580(2) and580(3) can have higher solder joint strength, owing to the non-solder mask fined structure. Since the present invention mounts the stiffener metals520(1),520(2) and520(3) on the opposite side of where the semiconductor chip is mounted, it is easier to mount a decoupling capacitor.

FIG. 6is a sectional view of a semiconductor package substrate without a core and stiffeners in accordance with a second preferred embodiment of the present invention. Referring toFIG. 6, the semiconductor package comprises insulating layers630(1) and630(2), a via hole640, a solder resist650, a surface-treating metal660, thermal pad670and solder ball pad680(1),680(2) and680(3). The function pads can include the thermal pad670and the solder ball pads680(1),680(2) and680(3). Hereinafter, the difference from the first preferred embodiment will be described.

Comparing with the first preferred embodiment, the function pads formed on the semiconductor package substrate of the second preferred embodiment does not have the stiffener metals520(1),520(2) and520(3). That is, by eliminating the stiffener metals520(1),520(2) and520(3) from the etching process, the second preferred embodiment can achieve a fine pitch on the function pads. Thus, the function pads of the second preferred embodiment comprises only the thermal pad670and the solder ball pads580(1),580(2) and580(3). Here, if necessary, the thermal pad670may be also eliminated from the etching process.

FIG. 7is a sectional view of a soldered coreless semiconductor package substrate in accordance with a third preferred embodiment of the present invention. Referring toFIG. 7, the semiconductor package comprises insulating layers730(1) and730(2), a via hole740, a solder resist750, a function pad770and solder balls790(1),790(2) and790(3).

The case of the function pad770being coupled to the mother board by soldering is illustrated here. According to the prior art, the electrode pad being soldered is located between solder resists, and thus the bonding is hardly stable. The present invention, however, performs the soldering by use of a protruded function pad770, making the bonding very stable.

FIG. 8is a sectional view of a coreless semiconductor package substrate coupled to a mother board by a paste in accordance with a fourth preferred embodiment of the present invention. Referring toFIG. 8, the semiconductor package comprises insulating layers830(1) and830(2), a via hole840, a solder resist850, function pads820(1),820(2),820(3) and870and a conductive paste880.

The case of the semiconductor package being coupled to the substrate by use of the conductive paste880is illustrated here. By using the protruded function pads820(1),820(2),820(3) and870formed on the semiconductor package, the semiconductor can be securely coupled to the substrate. The conductive paste880can be an anisotropic conductive paste.

As described above, the coreless substrate and manufacturing method thereof in accordance with the present invention have the signal delivery characteristic that is improved by eliminating the IVH.

The coreless substrate and manufacturing method thereof in accordance with the present invention can make the IVH thin by eliminating the core layer.

In addition, the coreless substrate and manufacturing method thereof in accordance with the present invention can perform various functions through a single process because various function pads can be formed using a metal sheet.

Although certain preferred embodiments of the present invention have been described, anyone of ordinary skill in the art to which the invention pertains should be able to understand that a large number of modifications and permutations are possible within the spirit and scope of the invention and its equivalents, which shall only be defined by the claims, appended below.