A received analog input signal is applied to a programmable amplifier. The amplifier is controlled by digital signals and by preselected gain of its individual stages to provide an analog signal corresponding to the received input signal. The digital signals are provided by digital signal means in accordance with the analog signal from the programmable amplifier and as such correspond to the logarithm of the received input signal.

BACKGROUND OF THE INVENTION 
Field of the Invention 
The apparatus of the present invention relates to converters in general 
and, more particularly, to an analog-to-digital converter. 
SUMMARY OF THE INVENTION 
A logarithmic analog digital converter includes a programmable amplifier 
adapted to receive an analog input signal. The programmable amplifier is 
responsive to digital signals for providing an analog output corresponding 
to a received analog signal. The digital signals are provided by a digital 
signal network, which also provides them as the digital output 
corresponding logarithmically to the received analog signal, in accordance 
with the analog output from the programmable amplifier. 
The objects and advantages of the invention will appear more fully 
hereinafter, from a consideration of the detailed description which 
follows, taken together with the accompanying drawings wherein one 
embodiment is illustrated by way of example. It is to be expressly 
understood, however, that the drawings are for illustrative purposes only 
and are not to be constructed as defining the limits of the invention.

DESCRIPTION OF THE INVENTION 
Referring to FIG. 1, amplifiers 3A through 3H, in cooperation with switches 
5A through 5H, comprise a programmable amplifier. Amplifiers 3A through 3H 
have predetermined gains as follows: 1, 256, 16, 4, 2, 1.414, 1,189 and 
1.0905 or as expressed in powers of two: 2.sup.0 2.sup.8, 2.sup.4, 
2.sup.2, 2.sup.1, 2.sup.1/2, 2.sup.1/4 and 2.sup.1/8. It should be noted 
that amplifier 3A, having a gain of unity, is used to invert a negative 
signal to a positive signal and as such may be located either as the input 
amplifier of the programmable amplifier or as the output amplifier; it is 
shown in this particular embodiment as the input amplifier. Amplifier 3A 
has an analog input signal E.sub.1 applied to its input. 
Switches 5A through 5H are electronic switches which are equivalent to 
single pole, double throw switches. The output of each amplifier is 
connected to one input of a corresponding switch having the same suffix as 
the amplifier. Each amplifier with the exception of the input amplifier 3A 
has its input connected to the output of a switch having a suffix which 
precedes its own suffix by one letter. Each switch of switches 5B through 
5H, has another input connected to the output of a switch having a suffix 
which precedes its own suffix by one letter. Another input of switch 5B 
has input signal E.sub.1 applied to it. Thus the output of amplifier 3B 
and the other input of switch 5B are connected to the output of switch 5A. 
Each switch of switches 5A through 5H is controlled by a corresponding 
digital signal of digital signals DA through DH, having two letters; the 
latter letter corresponding to the suffix of the switch it controls. 
Switch 5H provides an analog signal E.sub.o which corresponds to input 
signal E.sub.i. The digital signals are provided by digital signal means 
10 which also provides them as digital outputs corresponding to the 
logarithm of input signal E.sub.i. Digital signal means 10 provides an end 
of conversion signal and receives an external start signal. Referring to 
FIG. 2, an electronic single pole, double throw switch 13 in digital 
signal means 10 has a reference voltage V, of 1.044 v ts, although a 
voltage of 1.00 volts may be used, applied to one input and has another 
input connected to ground. Switch 13 is controlled, as hereinafter 
explained, to initially provide an output corresponding to a zero voltage 
and to provide the reference voltage V as an output thereafter. The output 
from switch 13 is provided to a comparator 14 where the output is compared 
with signal E.sub.o from switch 5H. When the output from switch 13 
corresponds to a zero voltage, comparator 14 is in effect determining the 
polarity of input signal E.sub.i. 
Comparator 14 provides an output corresponding to the comparison to D 
inputs of a plurality of flip-flops 17A through 17H which provides digital 
signals DA through DH, respectively. Digital signal means 10 also includes 
a pulse source 20 providing pulses P to a shift register 25. Shift 
register 25 provides pulses QA through QH in sequence to C and S inputs of 
flip-flops 17A through 17H, respectively, so that as one Q pulse ends the 
next Q pulse starts. A received start signal is applied to reset input R 
of flip-flops 17A through 17H and to shift register 25 to reset the 
flip-flops and shift register 25. Shift register 25 also provides the end 
of conversion signal which disables pulse source 20 to prevent the further 
providing of Q pulses. 
Pulses QB through QC are provided to an OR gate 26 whose output controls 
switch 13. OR gate 26 provides a low level output to switch 13 when 
register 25 does not provide pulses QB through QH. Thus, pulses QB through 
QH pass through OR gate 26 so that in effect, OR gate 26 provides a high 
level output to switch 13 causing switch 13 to pass reference voltage V to 
comparator 14. 
In operation signal E.sub.1 is applied to amplifier 3A and to switch 5A. 
When a start pulse is received by signal means 10, flip-flop 17A through 
17H and shift register 25 are reset. The end of conversion output from 
shift register 25 goes to a low logic level which enables pulse source 20 
to provide shift pulses P to register 25. The first pulse QA from shift 
register 25 is applied to the C and the S inputs of flip-flop 17A. Since, 
at this point, all of the digital signals DA through DH are at a low logic 
level, input signal E.sub.i passes through switches 5A through 5H and is 
provided as signal E.sub.o to comparator 14. Due to the operation of 
switch 13, comparator 14 compares it with ground which in effect 
determines its polarity. 
When signal E.sub.i is positive, comparator 14 provides its output at a low 
logic level to the D input of switches 17A through 17H. Since the output 
from comparator 14 is at a low logic level, the termination of pulse QA 
from register 25 has no effect on flip-flop 17A so that digital signal DA 
remains at a low logic level. When input signal E.sub.i is negative, the 
output from comparator 14 is applied to flip-flop 17A at a high logic 
level and the termination of pulse QA triggers it to a set state. 
Flip-flop 17A provides digital signal DA at a high logic level indicating 
polarity of the input signal as being negative and controlling switch 5A 
to pass the output from amplifier 3A instead of input signal E.sub.i. 
Since amplifier 3A is an inverting unity gain amplifier, its only effect 
is to invert signal E.sub.i so that for the remainder of the operation the 
output from switch 5H will be positive. 
By way of example let us assume that signal E.sub.i corresponds to a value 
of a 0.01 volt. As noted before signal E.sub.i is passed through amplifier 
3A to invert it. The output from amplifier 3A is passed by switch 5A to 
switch 5B and to amplifier 3B. Pulse QB causes flip-flop 17B to provide 
digital signal DB at a low level output so that switch 5B passes the 
output from amplifier 3B. The amplifier output is passed through all of 
the remaining switches 5C through 5H so that output E.sub.o has a value of 
2.56. Since pulse QB also causes switch 13 to pass reference voltage V to 
comparator 14. Since E.sub.o is greater than the reference voltage, 
comparator 14 provides its output at a high level so that upon the 
termination of pulse QB flip-flop 17B flips back to its previous state so 
that the signal is not amplified by amplifier 3B. Upon the occurrence of 
the pulse QC, switch 5 is controlled by signal DC to pass the amplified 
output of amplifier 3C which corresponds to 0.16 volts which pass through 
the remaining switches 5D through 5H and 13 to comparator 14. Since 0.16 
is less than the reference voltage the output from the comparator 14 goes 
to a low level so that when pulse QC is terminated flip-flop 17C remains 
in the same state and switch 5C continues to pass the amplified signals 
from amplifier 3C. The sequence is continued and we will find that upon 
the completion of the sequence the following digital signals would be at a 
high level DC, DD, DF and DH which correspond to the word 10110.101 which 
in turn corresponds to the value of -6.6438. The converter gives the 
correct results for the best seven digit representation. Upon the 
completion of pulse QH from shift register 25, register 25 provides an end 
of conversion signal at a high level which is also applied to pulse source 
20 disabling it to stop the pulses from being applied to shift register 
25. 
The apparatus of the present invention as hereinbefore described is a 
logarithmic analog-to-digital converter. The converter includes a 
programmable amplifier providing an analog signal in accordance with 
digital signals corresponding to an input signal. The converter of the 
present invention may be used to replace, or lieu of, the combination of a 
floating point amplifier and a linear analog-to-digital converter. What is 
claimed is: