Semiconductor device and method of manufacturing the same

A semiconductor device includes a capacitor including a lower electrode an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes ABO3 where ‘A’ is a first metal element and ‘B’ is a second metal element having a work function greater than that of the first metal element. The dielectric layer includes CDO3 where ‘C’ is a third metal element and ‘D’ is a fourth metal element. The lower electrode includes a first layer and a second layer which are alternately and repeatedly stacked. The first layer includes the first metal element and oxygen. The second layer includes the second metal element and oxygen. The dielectric layer is in contact with the lower electrode at a first contact surface the first contact surface corresponding to the second layer.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0174171, filed on Dec. 24, 2019, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Some example embodiments relate to a semiconductor and, more particularly, to a semiconductor device and/or a method of manufacturing the same.

Semiconductor devices are widely used in an electronic industry because of their small sizes, multi-functional characteristics, and/or low manufacturing costs. Semiconductor devices have been highly integrated with the development of the electronic industry. Widths of patterns included in semiconductor devices have been reduced to increase the integration density of semiconductor devices. In particular, as a design rule of a semiconductor memory device such as dynamic random access memory (DRAM) is being reduced, a range of capacitance, e.g. a standard deviation and/or an inter-quartile range and/or a difference between a maximum value and a minimum value of a capacitance, may be increased by oxidation of a lower electrode of a capacitor. Thus, there is desire for a structure of a semiconductor memory device and a method which are capable of reducing the difference of the capacitance.

SUMMARY

Some example embodiments of inventive concepts may provide a semiconductor device capable of reducing a leakage current of a capacitor and/or a method of manufacturing the same.

Alternatively or additionally, some example embodiments of inventive concepts may also provide a semiconductor device capable of improving reliability and/or a method of manufacturing the same.

According to some example embodiments, a semiconductor device may include a capacitor including a lower electrode an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes ABO3where ‘A’ is a first metal element and ‘B’ is a second metal element having a work function greater than that of the first metal element. The dielectric layer includes CDO3where ‘C’ is a third metal element and ‘D’ is a fourth metal element. The lower electrode includes a first layer and a second layer which are alternately and repeatedly stacked. The first layer includes the first metal element and oxygen. The second layer includes the second metal element and oxygen. The dielectric layer is in contact with the lower electrode at a first contact surface the first contact surface corresponding to the second layer.

According to some example embodiments, a semiconductor device may include a capacitor including a lower electrode, an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes a first metal element, a second metal element, and oxygen. The dielectric layer includes a third metal element, a fourth metal element, and oxygen. The lower electrode includes a first layer and a second layer which are alternately and repeatedly stacked; the first layer includes the first metal element and oxygen. The second layer includes the second metal element and oxygen. The first metal element is at least one of Sr, Ba, La, or Ca, and the second metal element is at least one of Ru, Mo, Jr, Co, or Ni. The dielectric layer contacts the lower electrode at a first contact surface, the first contact surface corresponding to the second layer.

According to some example embodiments, a semiconductor device may include a first conductive line buried in an upper portion of a substrate, the first conductive line extending in a first direction, an active portion in the upper portion of the substrate, the active portion defined by a device isolation pattern, the active portion including a first dopant region and a second dopant region which are separated from each other with the first conductive line interposed between the first dopant region and the second dopant region, a second conductive line on the substrate, the second conductive line extending in a second direction intersecting the first direction, the second conductive line connected to the first dopant region, a contact connected to the second dopant region, and a capacitor connected to the second dopant region through the contact. The capacitor includes a lower electrode, an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes ABO3where ‘A’ is a first metal element and ‘B’ is a second metal element having a work function greater than that of the first metal element, the dielectric layer includes CDO3where ‘C’ is a third metal element and ‘D’ is a fourth metal element. The lower electrode includes a first layer and a second layer which are alternately and repeatedly stacked, the first layer includes the first metal element and oxygen the second layer includes the second metal element and oxygen. The dielectric layer contacts the lower electrode at a first contact surface of the lower electrode, the first surface corresponding to the second layer.

According to some example embodiments, a method of manufacturing a semiconductor device may include forming a lower electrode on a substrate, forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer. The forming of the lower electrode comprises performing a lower electrode-forming cycle a plurality of times, and the lower electrode-forming cycle comprises a process of depositing a first layer and a process of depositing a second layer. The process of depositing the first layer includes supplying a first metal element source, and supplying an oxygen source. The process of depositing the second layer includes supplying a second metal element source, and supplying the oxygen source. The process of depositing the second layer ends the forming of the lower electrode.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

A semiconductor device and a method of manufacturing the same according to some example embodiments of inventive concepts will be described hereinafter in detail with reference to the accompanying drawings.

FIG.1is a cross-sectional view illustrating a capacitor according to some example embodiments of inventive concepts.FIG.2is an enlarged view of a region ‘Q’ ofFIG.1.FIG.3is a plan view of a first layer.FIG.4is a plan view of a second layer.FIG.5is a plan view of a third layer.FIG.6is a plan view of a fourth layer.

Referring toFIGS.1and2, a capacitor CAP may include a lower electrode10, an upper electrode50, and a dielectric layer30between the lower and upper electrodes10and50. The upper electrode50may be spaced apart from the lower electrode10in a Z direction. For example, the capacitor CAP may be provided on a substrate (not illustrated), the lower electrode10may be adjacent to the substrate, and the upper electrode50may be spaced apart from the substrate with the lower electrode10interposed therebetween. For example, the lower electrode10, the dielectric layer30and the upper electrode50may be sequentially stacked on the substrate in the Z direction. As used herein, the X direction, the Y direction, and the Z direction may correspond to different directions relative to one another, and use of the X direction, the Y direction, and the Z direction does not necessarily indicate a relation to a ground, e.g. to a flat surface relative to the earth. For example, the Z direction may extend in a direction perpendicular to, or parallel to, a flat surface relative to the earth. As another example, the lower electrode10may be conformal to another surface, such as to a base electrode.

Referring toFIG.2, the lower electrode10may include a first compound including a first metal element M1, a second metal element M2, and at least one oxygen atom OA. For example, the lower electrode10may be a ternary compound expressed by a chemical formula of ABO3. Here, ‘A’ may correspond to the first metal element M1, and ‘B’ may correspond to the second metal element M2. The first compound may have a perovskite crystal structure, for example a structure having two cations of different sizes (e.g. ‘A’ and ‘B’, along with an anion (e.g. O3). For example, the first metal element M1may be disposed at each of eight corners of a unit cell, and the second metal element M2may be disposed at a center of the unit cell. The oxygen atom OA may be disposed at each of centers of six faces of the unit cell. A ratio of the first metal element M1:the second metal element M2:the oxygen atom OA may be 1:1:3 in the unit cell. The lower electrode10may have a ferromagnetic property. A thickness of the lower electrode10may range from about 50 Å (5 nm) to about 100 Å (10 nm).

The lower electrode10may include atomic layers such as a first layer L1and a second layer L2which are alternately and repeatedly stacked in the Z direction. As illustrated inFIG.3, the first layer L1may be parallel to an XY plane and may be formed of the first metal element M1and the oxygen atom OA. The first layer L1may correspond to a {100} plane of the lower electrode10. The first metal element M1may be disposed at each of lattice points, and the oxygen atom OA may be disposed at a center of a face of the unit cell which is formed by four first metal elements M1. A ratio of the first metal element M1to the oxygen atom OA in the first layer L1may be 1:1.

As illustrated inFIG.4, the second layer L2may be parallel to the XY plane and may be formed of the second metal element M2and the oxygen atom OA. The second layer L2may correspond to the {100} plane of the lower electrode10. The second metal element M2may be disposed at the center of the unit cell. The oxygen atom OA may be disposed at each of the centers of the faces included in/constituting/corresponding to the unit cell (or at each of centers of edges of the unit cell in a plan view). A ratio of the second metal element M2to the oxygen atom OA in the second layer L2may be 1:2.

A work function of the second metal element M2may be greater than that of the first metal element M1. For example, the work function of the first metal element M1may be less than 4 eV. The work function of the second metal element M2may be greater than 4.5 eV and less than 6 eV. For example, the first metal element M1may be at least one of Sr, Ba, La, or Ca. The second metal element M2may be at least one of Ru, Mo, Jr, Co, or Ni. For example, the first compound may be, but not limited to, SrRuO3, SrCoO3, SrMoO3, CaRuO3, BaRuO3, or (B a, Sr)RuO3.

The dielectric layer30may include a second compound including a third metal element M3, a fourth metal element M4, and an oxygen atom OA. For example, the dielectric layer30may be or include a ternary compound expressed by a chemical formula of CDO3. Here, ‘C’ may correspond to the third metal element M3, and ‘D’ may correspond to the fourth metal element M4. The second compound may have the perovskite crystal structure. For example, the third metal element M3may be disposed at each of eight corners of a unit cell, and the fourth metal element M4may be disposed at a center of the unit cell. The oxygen atom OA may be disposed at each of centers of six faces of the unit cell. A ratio of the third metal element M3:the fourth metal element M4:the oxygen atom OA may be 1:1:3 in the unit cell. The dielectric layer30may have a paraelectric and/or a ferroelectric property. A thickness of the dielectric layer30may range from about 50 Å (5 nm) to about 100 Å (10 nm).

The dielectric layer30may include a third layer L3and a fourth layer L4which are alternately and repeatedly stacked in the Z direction. As illustrated inFIG.5, the third layer L3may be parallel to the XY plane and may be formed of the third metal element M3and the oxygen atom OA. The third layer L3may correspond to a {100} plane of the dielectric layer30. The third metal element M3may be disposed at each of lattice points, e.g. each of lattice points of a unit cell, and the oxygen atom OA may be disposed at a center of a face of the unit cell which is formed by four third metal elements M3. A ratio of the third metal element M3to the oxygen atom OA in the third layer L3may be 1:1.

As illustrated inFIG.6, the fourth layer L4may be parallel to the XY plane and may be formed of the fourth metal element M4and the oxygen atom OA. The fourth layer L4may correspond to the {100} plane of the dielectric layer30. The fourth metal element M4may be disposed at the center of the unit cell. The oxygen atom OA may be disposed at each of the centers of the faces included in/constituting/corresponding to the unit cell (or at each of centers of edges of the unit cell in a plan view). A ratio of the fourth metal element M4to the oxygen atom OA in the fourth layer L4may be 1:2.

A work function of the fourth metal element M4may be greater than that of the third metal element M3. For example, the work function of the third metal element M3may be less than 4 eV. The work function of the fourth metal element M4may be greater than 4.0 eV and less than 4.5 eV. For example, the third metal element M3may be at least one of Ba, Sr, or Ca. The fourth metal element M4may be at least one of Ti, Zr, or Hf. For example, the second compound may be, but not limited to, BaTiO3, (Ba,Sr)TiO3(BST), SrTiO3, (Ba,Sr)(Zr,Ti)O3(BSZTO), Sr(Zr,Ti)O3(SZTO), Ba(Zr,Ti)O3(BZTO), (Ba,Sr)ZrO3(BSZO), SrZrO3, or BaZrO3. Alternatively or additionally, the third metal element M3may be an element (e.g., Pb) of which a work function is greater than 4 eV and less than that of the fourth metal element M4. In this case, the second compound may be or include Pb(Zr,Ti)O3(PZT) or (Pb,La)(Zr,Ti)O3(PLZT).

A work function of the fourth layer L4corresponding to an oxide layer of the fourth metal element M4may be greater than a work function of the third layer L3corresponding to an oxide layer of the third metal element M3. For example, when the fourth layer L4is TiO2and the third layer L3is SrO, the work function (about 6.33 eV) of the fourth layer L4may be greater than the work function (about 3.18 eV) of the third layer L3. For example, the work function of the fourth layer L4may range from about 5.0 eV to about 6.5 eV.

The upper electrode50may include a metal layer including at least one of a noble metal (e.g., Pt, Jr, or Ru), Ti, or W. In some example embodiments, the upper electrode50may be formed of the same ternary compound as the lower electrode10. In some example embodiments, the upper electrode50may include a heterogeneous semiconductor material such as silicon-germanium.

An interface IF may exist between the lower electrode10and the dielectric layer30. The interface IF may be or correspond to a region in which a first contact surface CS1corresponding to a top surface of the lower electrode10is in contact, e.g. in direct and/or atomic contact, with a second contact surface CS2corresponding to a bottom surface of the dielectric layer30. The first contact surface CS1and the second contact surface CS2may be spaced apart from each other in terms of a lattice but may be in contact with each other in terms of a macro scale.

The first contact surface CS1of the lower electrode10may be the {100} plane. The first contact surface CS1may be one of the first and second layers L1and L2having the greater work function. As illustrated inFIG.2, the first contact surface CS1may be or correspond to the second layer L2. The second layer L2may consist of (or consist essentially of, or include) the second metal element M2and the oxygen atom OA and may be expressed by BO2. The first layer L1may consist of (or consist essentially of, or include) the first metal element M1and the oxygen atom OA and may be expressed by AO. A work function of an oxide (e.g., BO2) of the second metal element M2may be greater than that of an oxide (e.g., AO) of the first metal element M1.

For example, a work function of the second layer L2corresponding to an oxide layer of the second metal element M2may be greater than a work function of the first layer L1corresponding to an oxide layer of the first metal element M1. For example, when the second layer L2is RuO2and the first layer L1is SrO, the work function (about 5.16 eV) of the second layer L2may be greater than the work function (about 2.55 eV) of the first layer L1. The second contact surface CS2of the dielectric layer30may be one, having a small work function, of the third and fourth layers L3and L4. For example, the second contact surface CS2may be or correspond to the third layer L3.

FIG.7is a conceptual view illustrating an interface between a lower electrode and a dielectric layer according to a comparative example. Referring toFIG.7, a first contact surface CS1of a lower electrode10may be or correspond to the first layer L1in the comparative example.

When the dielectric layer30is formed of the ternary compound having the perovskite crystal structure, a dielectric constant of the dielectric layer30may be increased as compared with a binary compound such as ZrO2. As a result, a capacitance of the capacitor may be increased. If the lower electrode10is formed of a binary compound, crystallinity of the dielectric layer30may be reduced by lattice mismatch between the lower electrode10and the dielectric layer30formed of the ternary compound, and thus a dielectric constant of the dielectric layer30may be deteriorated. A work function of a ternary compound dielectric layer may be less than that of a binary compound dielectric layer, and thus a conduction band offset (CBO) value between the ternary compound dielectric layer and a lower electrode may be less than about 1.0 eV. Thus, a leakage current of a capacitor may be increased. However, according to the some example embodiments of inventive concepts, the first contact surface CS1of the lower electrode10may be the second layer L2of which the work function is greater than that of the first layer L1, and thus a CBO value may be increased to about 2.0 eV or more. As a result, a leakage current of the capacitor according to the some example embodiments of inventive concepts may be reduced as compared with the case in which the first contact surface CS1is the first layer L1like the comparative example ofFIG.7, and thus the reliability of the semiconductor device may be improved.

FIG.8is a process flowchart illustrating a method of forming a capacitor, according to some example embodiments of inventive concepts.FIG.9is a conceptual view illustrating a deposition apparatus for forming layers according to some example embodiments of inventive concepts.FIG.10is a timing diagram illustrating a supply cycle of process gases for forming a lower electrode according to some example embodiments of inventive concepts.FIG.11is a timing diagram illustrating a supply cycle of process gases for forming a dielectric layer according to some example embodiments of inventive concepts.

Referring toFIGS.8and9, a deposition apparatus1000may include a deposition chamber21. For example, the deposition apparatus1000may be or include an atomic layer deposition (ALD) apparatus. The deposition apparatus1000may also include a chuck/platen/stage22which is provided in the deposition chamber21and upon which a substrate WF is loaded, and a shower head23which is used to supply gases such as reaction gases into the deposition chamber21. The stage22may include a heater25therein to maintain the substrate WF at a desired and/or specific temperature. High radio frequency (HRF) power28of 13.56 MHz and/or 27 MHz may be applied to the shower head23(and/or a top electrode connected to the shower head23) and the stage22may be grounded, and thus plasma may be formed between the shower head23and the stage22. In some example embodiments, when the plasma is formed, low radio frequency (LRF) power29of 5 MHz or less (e.g., 400 kHz to 500 kHz) may be additionally applied to the shower head23and/or the top electrode as desired/needed.

Process gases may be supplied into the deposition chamber21through the shower head23. In some example embodiments, the shower head23may be connected to a first metal element source11, a second metal element source12, a third metal element source13, a fourth metal element source14, and an oxygen source16through one or more of supply lines. A carrier gas supply unit15may be connected to the shower head23. The first metal element source11, the second metal element source12, the third metal element source13, the fourth metal element source14and the oxygen source16may be supplied to the shower head23through individual supply lines separated from each other. Alternatively, at least portions of the individual supply lines may overlap, e.g. be common, with each other. The first to fourth metal element sources11,12,13and14may be or include sources of different elements from each other. Alternatively, when kinds of at least some of the first to fourth metal elements described above are the same as each other, at least some of the first to fourth metal element sources11,12,13and14may be sources of substantially the same element. For example, when the first metal element M1is the same as the third metal element M3, the first metal element source11and the third metal element source13may be substantially the same source.

A carrier gas supplied from the carrier gas supply unit15may carry another source and/or a precursor into the deposition chamber21. The carrier gas may enable purging of an unreacted material and/or reaction byproducts in the deposition chamber21to the outside of the deposition chamber21through the use of a vacuum pump. The carrier gas may be or include an inert gas such as helium (He) or neon (Ne) and/or may be a gas having very low reactivity, such as nitrogen (N2) or carbon dioxide (CO2). However, example embodiments of inventive concepts are not limited thereto. At least a portion of a supply line of the carrier gas supply unit15may overlap with the supply lines of the first metal element source11, the second metal element source12, the third metal element source13, the fourth metal element source14and the oxygen source16. Alternatively, the supply line of the carrier gas supply unit15may be separated from the supply lines of the first metal element source11, the second metal element source12, the third metal element source13, the fourth metal element source14and the oxygen source16.

A substrate WF may be loaded on the stage22in the deposition chamber21(S100). The substrate WF may be a wafer, such as a 200 mm or 300 mm diameter wafer. A plurality of sources may be supplied into the deposition chamber21to form a lower electrode on the substrate WF (S200). The process of forming the lower electrode may be completed after the lower electrode is formed to have a specific and/or desired thickness, and then, a first thermal treatment process may be performed (S300). The process of forming the lower electrode will be described hereinafter in more detail.

Referring toFIGS.1to4and8to10, the lower electrode10may be formed on the substrate WF (e.g., the wafer) (S200). The formation of the lower electrode10may be performed like and/or according to the timing diagram ofFIG.10. The formation of the lower electrode10may include a plurality of first cycles CL1. The first cycle CL1may include a process SC1of forming the first layer L1(hereinafter, referred to as a first process SC1) and a process SC2of forming the second layer L2(hereinafter, referred to as a second process SC2).

The first process SC1may include a process S101of supplying the first metal element source11, a first purge process P1, a first supplying process S102of the oxygen source16, and a second purge process P2, which are sequentially performed. The first layer L1which consists of (or consists essentially of, or includes) the first metal element M1(such as in a gaseous-phase) and the oxygen atom OA and substantially corresponds to an (atomic) monolayer may be formed by the first process SC1. As disclosed herein, a monolayer may mean a layer having a structure in which atoms are two-dimensionally arranged. The second process SC2may include a process S103of supplying the second metal element source12, a third purge process P3, a second supplying process S104of the oxygen source16, and a fourth purge process P4, which are sequentially performed. The second layer L2which consists of (or consists essentially of, or includes) the second metal element M2and the oxygen atom OA and substantially corresponds to an (atomic) monolayer may be formed by the second process SC2. A source gas not reacting with the wafer in the process immediately before each of the first to fourth purge processes P1, P2, P3and P4may be exhausted to the outside of the deposition chamber21by each of or at least some of the first to fourth purge processes P1, P2, P3and P4. The first cycle CL1may be performed a plurality of times to form the lower electrode10in which the first layer L1and the second layer L2are alternately and repeatedly stacked.

The first metal element source11may include at least one of Sr, Ba, La, or Ca. For example, the first metal element source11may be a strontium (Sr) source. The strontium source may include a cyclopenta-based ligand and/or a ketoimine-based ligand. The second metal element source12may include at least one of Ru, Mo, Jr, Co, or Ni. For example, the second metal element source12may be a ruthenium (Ru) source. The ruthenium source may include a β-diketonate-based ligand. For example, the oxygen source16may include O2and/or O3.

In the first process SC1, the process S101of supplying the first metal element source11may be performed for a time t01. For example, the time t01may range from about 7 seconds to about 15 seconds. In the second process SC2, the process S103of supplying the second metal element source12may be performed for a time t03. For example, the time t03may range from about 3 seconds to about 7 seconds. For example, the process S101of supplying the first metal element source11may be longer than the process S103of supplying the second metal element source12. Each of the first to fourth purge processes P1, P2, P3and P4may be performed for a time of about 15 seconds to about 25 seconds. The first supplying process S102of the oxygen source16may be performed for a time t02. For example, the time t02may range from about 15 seconds to about 25 seconds. The second supplying process S104of the oxygen source16may be performed for a time t04. For example, the time t04may range from about 15 seconds to about 25 seconds. During the first cycle CL1for forming the lower electrode10, a chamber temperature may be maintained at a temperature of about 300 degrees Celsius to about 500 degrees Celsius. During the first cycle CL1for forming the lower electrode10, a pressure in the chamber may range from about 1 Torr (133 Pascal) to about 3 Torr (400 Pascal).

The formation of the lower electrode10may be started at a start point ts1of an initial first cycle CL1sand may be ended at an end point te1of the last first cycle CL1e. The initial first cycle CL1sincluding the start point ts1is started from the first process SC1of the first and second processes SC1and SC2inFIG.10. Alternatively, the initial first cycle CL1smay be started from the second process SC2. In the last first cycle CL1eincluding the end point te1, a last supplied metal element source may be the second metal element source12. For example, the last first cycle CL1emay be ended by the second process SC2of the first and second processes SC1and SC2. As a result, the first contact surface CS1of the lower electrode10described with reference toFIGS.1and2may be or correspond to the second layer L2.

After the end point te1, the first thermal treatment process (S300) may be performed. The first thermal treatment process (S300) may be performed in-situ in the deposition chamber21. However, some example embodiments of inventive concepts are not limited thereto; for example, the substrate WF may be thermally treated in another chamber. The metal element sources may not be supplied during the first thermal treatment process (S300). The first thermal treatment process (S300) may be performed at a temperature of about 300 degrees Celsius to about 600 degrees Celsius. A crystallinity of the lower electrode10may be increased by the first thermal treatment process (S300).

The dielectric layer30may be formed on the lower electrode10(S400). The formation of the dielectric layer30may be performed like or in a manner corresponding to the timing diagram ofFIG.11. The formation of the dielectric layer30may include a plurality of second cycles CL2. The second cycle CL2may include a process SC3of forming the third layer L3(hereinafter, referred to as a third process SC3) and a process SC4of forming the fourth layer L4(hereinafter, referred to as a fourth process SC4).

The third process SC3may include a process S201of supplying the third metal element source13, a fifth purge process P5, a third supplying process S202of the oxygen source16, and a sixth purge process P6, which are sequentially performed. The third layer L3which consists of (or consists essentially of, or includes) the third metal element M3and the oxygen atom OA and substantially corresponds to a monolayer may be formed by the third process SC3. The fourth process SC4may include a process S203of supplying the fourth metal element source14, a seventh purge process P7, a fourth supplying process S204of the oxygen source16, and an eighth purge process P8, which are sequentially performed. The fourth layer L4which consists of (or consists essentially of, or includes) the fourth metal element M4and the oxygen atom OA and corresponds to substantially a monolayer may be formed by the fourth process SC4. The second cycle CL2may be performed a plurality of times to form the dielectric layer30in which the third layer L3and the fourth layer L4are alternately and repeatedly stacked. The third metal element source13may include at least one of Sr, Ba, La, or Ca. The fourth metal element source14may include at least one of Ti, Zr, or Hf. For example, the fourth metal element source14may include TiCl4.

In the third process SC3, the process S201of supplying the third metal element source13may be performed for a time t05. For example, the time t05may range from about 7 seconds to about 15 seconds. In the fourth process SC4, the process S203of supplying the fourth metal element source14may be performed for a time t07. For example, the time t07may range from about 3 seconds to about 7 seconds. In other words, the process S201of supplying the third metal element source13may be longer than the process S203of supplying the fourth metal element source14. Each of the fifth to eighth purge processes P5, P6, P7and P8may be performed for a time of about 15 seconds to about 25 seconds. The third supplying process S202of the oxygen source16may be performed for a time t06. For example, the time t06may range from about 15 seconds to about 25 seconds. The fourth supplying process S204of the oxygen source16may be performed for a time t08. For example, the time t08may range from about 15 seconds to about 25 seconds. During the second cycle CL2for forming the dielectric layer30, a chamber temperature may be maintained at a temperature of about 300 degrees Celsius to about 500 degrees Celsius. During the second cycle CL2for forming the dielectric layer30, a pressure in the chamber may range from about 1 Torr (133 Pascal) to about 3 Torr (400 Pascal).

The formation of the dielectric layer30may be started at a start point ts2of an initial second cycle CL2sand may be ended at an end point of the last second cycle. The initial second cycle CL2sincluding the start point ts2may be started by the third process SC3of the third and fourth processes SC3and SC4. For example, in the initial second cycle CL2sincluding the start point ts2, an initially supplied metal element source may be the third metal element source13. As a result, the second contact surface CS2of the dielectric layer30described with reference toFIGS.1and2may be or correspond to the third layer L3. Alternatively, the initial second cycle CL2sincluding the start point ts2may be started from the fourth process SC4of the third and fourth processes SC3and SC4. As a result, the second contact surface CS2may be or correspond to the fourth layer L4.

After the formation of the dielectric layer30is completed, a second thermal treatment process (S500) may be performed. The second thermal treatment process (S500) may be performed in-situ in the deposition chamber21. However, some example embodiments of inventive concepts are not limited thereto. The metal element sources may not be supplied during the second thermal treatment process (S500). The second thermal treatment process (S500) may be performed at a temperature of about 300 degrees Celsius to about 600 degrees Celsius. Alternatively, the second thermal treatment process (S500) may be omitted. Thereafter, a process of forming the upper electrode50may be performed.

FIG.12is a plan view illustrating a semiconductor memory device including a capacitor according to some example embodiments of inventive concepts.FIGS.13to19are cross-sectional views taken along lines A1-A2and B1-B2ofFIG.12to illustrate a method of manufacturing a semiconductor memory device including a capacitor, according to some example embodiments of inventive concepts.

In the following example embodiments, the capacitor used as a storage portion of a semiconductor memory device will be described as an example. However, the capacitor according to some example embodiments of inventive concepts is not limited to the storage portion of the semiconductor memory device but may be used as a non-memory element such as a decoupling structure.

Referring toFIGS.12and13, a device isolation pattern302may be disposed in a substrate301to define active portions ACT. The substrate301may be or include a semiconductor substrate, such as a single-crystal silicon wafer that has been lightly doped, e.g. lightly doped with boron. Each of the active portions ACT may have an isolated shape when viewed in a plan view. Each of the active portions ACT may have a bar shape extending in a third direction D3when viewed in a plan view. Each of the active portions ACT may correspond to a portion of the substrate301, which is surrounded by the device isolation pattern302when viewed in a plan view.

Word lines WL may intersect the active portions ACT. The word lines WL may be respectively disposed in grooves formed in the device isolation pattern302and the active portions ACT. The word lines WL may be parallel to a first direction D1intersecting the third direction D3. The word lines WL may include a conductive material. A gate dielectric layer307may be disposed between the word line WL and an inner surface of the groove. The gate dielectric layer307may include at least one of a thermal oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material.

A first dopant region312amay be disposed in each of the active portions ACT between a pair of the word lines WL, and a pair of second dopant regions312bmay be disposed in both edge regions of each of the active portions ACT, respectively. The first and second dopant regions312aand312bmay be doped with, for example, N-type dopants such as phosphorus and/or arsenic. The first dopant region312amay correspond to a common drain region, and the second dopant regions312bmay correspond to source regions. Each of the word lines WL and the first and second dopant regions312aand312badjacent thereto may constitute (e.g. correspond to) a transistor, and may act as, function as, or correspond to an access transistor for accessing a storage element of a DRAM cell; however, example embodiments are not limited thereto.

Top surfaces of the word lines WL may be lower than top surfaces of the active portions ACT. A word line capping pattern310may be disposed on each of the word lines WL. The word line capping patterns310may have line shapes extending in a longitudinal direction of the word lines WL and may cover the top surfaces of the word lines WL. The word line capping patterns310may include, for example, silicon nitride.

An interlayer insulating pattern305may be disposed on the substrate301. The interlayer insulating pattern305may be formed of a single or multi-layer including at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

Upper portions of the substrate301, the device isolation pattern302and the word line capping pattern310may be partially recessed to form a first recess region R1. Bit lines BL may be disposed on the interlayer insulating pattern305. The bit lines BL may intersect the word line capping patterns310and the word lines WL. As illustrated inFIG.12, the bit lines BL may extend in a second direction D2intersecting the first and third directions D1and D3. Each of the bit lines BL may include a poly-silicon pattern330, an ohmic pattern331, and a metal-containing pattern332, which are sequentially stacked. The poly-silicon pattern330may include poly-silicon doped or not doped with dopants. The ohmic pattern331may include a metal silicide. The metal-containing pattern332may include at least one of a metal (e.g., tungsten, titanium, and/or tantalum) or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride). A bit line capping pattern337may be disposed on each of the bit lines BL. The bit line capping pattern337may include an insulating material such as silicon nitride. The bit line capping patterns337may include the same, or different materials from that of the word line capping patterns310.

A bit line contact DC may be disposed in the first recess region R1intersecting the bit line BL. The bit line contact DC may include poly-silicon doped or not doped with dopants, such as boron. The bit line contact DC may be electrically connected to the first dopant region312aand may electrically connect the first dopant region312ato the bit line BL.

A filling insulation pattern341may be disposed in the first recess region R1in which the bit line contact DC is not disposed. The filling insulation pattern341may have a single-layered or multi-layered structure including at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

Storage node contacts BC may be disposed between a pair of the bit lines BL adjacent to each other, as illustrated inFIG.12. The storage node contacts BC may be spaced apart from each other. The storage node contacts BC may include poly-silicon doped (e.g. doped with boron) or not doped with dopants.

A bit line spacer including first and second spacers321and325spaced apart from each other by an air gap AG may be disposed between the bit line BL and the storage node contact BC. The first spacer321may cover a sidewall of the bit line BL and a sidewall of the bit line capping pattern337. The second spacer325may be adjacent to the storage node contact BC. The first spacer321may extend to cover a sidewall of the bit line contact DC and a sidewall and a bottom surface of the first recess region R1. The first spacer321and the second spacer325may include the same material. For example, the first spacer321and the second spacer325may include silicon nitride. Alternatively, the air gap AG may not be provided, but a third spacer may be provided between the first spacer321and the second spacer325.

A storage node ohmic layer309may be disposed on the storage node contact BC. The storage node ohmic layer309may include a metal silicide, such as tungsten silicide (WSix). A diffusion barrier pattern311amay cover the storage node ohmic layer309, the first and second spacers321and325, and the bit line capping pattern337. The diffusion barrier pattern311amay include a metal nitride such as titanium nitride and/or tantalum nitride. A landing pad LP may be disposed on the diffusion barrier pattern311a. The landing pad LP may include a metal-containing material such as tungsten. An upper portion of the landing pad LP may cover a top surface of the bit line capping pattern337and may have a width greater than that of the storage node contact BC. A center of the landing pad LP may be shifted from a center of the storage node contact BC in the first direction D1, as illustrated inFIG.12. One upper sidewall of the bit line capping pattern337may overlap with the landing pad LP and may be covered with a third spacer327. A second recess region R2may be formed at another upper sidewall of the bit line capping pattern337.

A first capping pattern358amay be provided between adjacent landing pads LP. The first capping pattern358amay have a liner shape, and a space surrounded thereby may be filled with a second capping pattern360a. Each of the first and second capping patterns358aand360amay include a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and/or a porous layer. The first capping pattern358aand the second capping pattern360amay fill the second recess region R2.

An etch stop layer370may be formed on the landing pads LP, the first capping pattern358aand the second capping pattern360a. A first mold layer372, a support layer374and a second mold layer376may be formed on the etch stop layer370. For example, each of the etch stop layer370and the support layer374may be formed of a silicon nitride layer. Each of the first and second mold layers372and376may be formed of a material having an etch selectivity with respect to the support layer374. For example, each of the first and second mold layers372and376may be formed of a silicon oxide layer.

Referring toFIGS.12and14, the second mold layer376, the support layer374, the first mold layer372and the etch stop layer370may be sequentially patterned to form electrode holes EH exposing the landing pads LP, respectively. A conductive layer may be formed to fill the electrode holes EH, and an etch-back process and/or a chemical mechanical polishing (CMP) process may be performed on the conductive layer to remove the conductive layer disposed on the second mold layer376and to form base electrodes SE in the electrode holes EH, respectively. The base electrode SE may include a metal nitride. For example, the base electrode SE may have a single-layered or multi-layered structure including at least one of TiN, WN, TaN, HfN, ZrN, TiAlN, TaSiN, TiSiN, TaAlN, TiBN, TiON, TiAlON, TiCN, TiAlCN, or TiSiCN.

A third mask pattern378may be formed on the second mold layer376. The third mask pattern378may have a plurality of openings378h. Each of the openings378hmay expose top surfaces of the base electrodes SE adjacent to each other and the second mold layer376between the base electrodes SE.

Referring toFIGS.12and15, an anisotropic etching process (such as a dry etching process) may be performed using the third mask pattern378as an etch mask to remove the second mold layer376exposed by the opening378hand the support layer374thereunder. Thus, a support pattern374amay be formed, and the first mold layer372under the opening378hmay be exposed.

Referring toFIGS.12and16, the third mask pattern378may be removed to expose the second mold layer376. The first and second mold layers372and376may be removed by an isotropic etching process to expose surfaces of the base electrode SE, the support pattern374aand the etch stop layer370.

Referring toFIGS.12and17, lower electrodes10may be formed on exposed surfaces of the base electrodes SE. The lower electrodes10on the base electrodes SE may be separated from each other. For example, the process of forming the lower electrodes10may include a process of removing portions deposited between the base electrodes SE to expose the etch stop layer370. The lower electrodes10may cover sidewalls and top surfaces of the base electrodes SE. The lower electrodes10may be substantially the same as the lower electrode10described with reference toFIGS.1to11and may be formed by substantially the same method as the lower electrode10ofFIGS.1to11. Referring toFIG.17, the lower electrode10may be conformal to a shape of the base electrode SE; for example, the lower electrode10may be deposited in a manner to follow the shape of the base electrode SE.

Referring toFIGS.12and18, a dielectric layer30may be formed to cover the lower electrodes10. The dielectric layer30may cover a plurality of the lower electrodes10in common. The dielectric layer30may be substantially the same as the dielectric layer30described with reference toFIGS.1to11and may be formed by substantially the same method as the dielectric layer30ofFIGS.1to11. Referring toFIG.16, the dielectric layer30may be conformal to a shape of the lower electrode10; for example, the dielectric layer30may be deposited in a manner to follow the shape of the lower electrode10.

Referring toFIGS.12and19, an upper electrode50may be formed on the dielectric layer30. The upper electrode50may be substantially the same as the upper electrode50described with reference toFIGS.1to11and may be formed by substantially the same method as the upper electrode50ofFIGS.1to11. Referring toFIG.19, the upper electrode may be conformal to a shape of the dielectric30and/or may entirely fill the openings. A semiconductor memory device having a capacitor CAP including the base electrode SE, the lower electrode10, the dielectric layer30and the upper electrode50may be formed by the formation of the upper electrode50. Other processes (not illustrated) may include planarization of the top surfaces of the upper electrode50, e.g. planarization by etch-back and/or CMP processes. The capacitor CAP may act as, function as, or correspond to a storage element for a DRAM cell; however, example embodiments are not limited thereto.

According to the some example embodiments of inventive concepts, the contact surface of the lower electrode, which is in contact with the dielectric layer, may be controlled to reduce a leakage current of the semiconductor device and to improve the reliability of the semiconductor device.

While inventive concepts have been described with reference to example embodiments, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made without departing from the spirits and scopes of the inventive concepts. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scopes of inventive concepts are to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.