ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

BACKGROUND

Advances in semiconductor technology have increased the demand for semiconductor devices with higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and nano-sheet field effect transistors (NSFETs). Such scaling down has increased the complexity of semiconductor device manufacturing processes.

DETAILED DESCRIPTION

As used herein, the term “vertical” means nominally perpendicular to the surface of a substrate.

Fins associated with fin field effect transistors (finFETs) or gate-all-around (GAA) FETs can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes, including a datable-patterning process or a multi-patterning process. Double-patterning and multi-patterning processes can combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

Technology advances in the semiconductor industry drive the pursuit of integrated circuits (IC)s having higher device density, higher performance, and lower cost. In the course of the IC evolution, fin structures have been adopted to implement various three dimensional (3D) field-effect transistors (FETs), such as fin-type field effect transistor (FinFET) and gate-all-around (GAA) FETs, to achieve ICs with higher device densities. Additionally, a vertical dielectric structure, which is also referred to herein as a “hybrid fin,” can be placed between two laterally adjacent fin structures to separate metal gate lines between transistors within the IC. For example, the hybrid fin's upper portion can be formed through the metal gate lines of two laterally adjacent fin structures to form an electrical isolation between the adjacent fin structures. However, as transistor size shrinks, the separation between laterally adjacent fin structures is reduced. The reduced separation between two lateral adjacent fin structure can result in voids in the upper portion of the hybrid fins. The voids in the upper portion of the hybrid fins can degrade the isolation between two laterally adjacent fin structures, thus degrading the IC manufacturing's yield.

The present disclosure is directed to a fabrication method and an isolation structure (e.g., hybrid fin) formed between two laterally adjacent fin structures on a substrate. The lower portion of the isolation structure can be made of a first dielectric layer, and the upper portion of the isolation structure can be made of a second dielectric layer. The second dielectric layer can have a greater dielectric constant than the first dielectric layer. For example, both first and second dielectric layers can include silicon, where the second dielectric layer can further include a metal element, such as hafnium, and oxygen. The second dielectric layer can be selectively removed, via an etching process, over the first dielectric layer to connect the gate metal lines formed over the two laterally adjacent fin structures. Further, the second dielectric layer can be a seamless layer (e.g., the second dielectric layer does not have voids). Hence, the isolation structure with both the upper and lower portions can sufficiently isolate the two laterally adjacent fin structures. A benefit of the present disclosure, among others, is to reduce or eliminate the voids in the isolation structure to separate the gate metal line connection between fin structures, thus avoiding transistor failures within the IC.

A semiconductor device100having an isolation structure140formed over a substrate102is described with reference toFIG.1, according to some embodiments,FIG.1illustrates an isometric view of semiconductor device100, according to some embodiments. Semiconductor device100can be included in a microprocessor, memory cell, or other integrated circuit (IC).

Semiconductor device100can include multiple fin structures108formed over substrate102. Each fin structure108can extend along an x-axis and traverse along a y-axis. Further, each of fin structures108can have a height H108formed over substrate102and be laterally in the y-direction) separated from one another by a separation S108. In some embodiments, height H108can be from about 120 nm to about 170 nm. If height H108is less than the above-noted lower limits, semiconductor device100may not provide sufficient driving current for the IC. If height H108is greater than the above-noted upper limits, fin structure108's mechanical strength ma not support fin structure108's structural integrity (e.g., fin structure108may collapse.) In some embodiments, separation S108can be from about 20 nm to about 50 nm. If separation S108is less than the above-noted lower limits, the parasitic capacitance between two laterally (e.g., in the y-direction) adjacent fin structures108may be increased to degrade semiconductor device100's speed. If separation S108is greater than the above-noted upper limits, semiconductor device100may not meet the fin pitch requirement determined by the respective technology node (e.g., fin pitch may be required to be less than about 60 nm for a 22 nm technology node). In some embodiments, a ratio of height H108to separation S108can be from about 2 to about 9. If the ratio of height H108to separation S108is less than the above-noted lower limits, semiconductor device100may not meet the fin pitch requirement determined by the respective technology node (e.g., fin pitch may be required to be less than about 60 nm for a 22 nm technology node). If the ratio of height H108to separation S108is greater than the above-noted upper limits, fin structure108's mechanical strength may not support fin structure108's structural integrity (e.g., fin structure108may collapse.)

Fin structure108can include a first portion traversed by gate structure110(discussed below) and a second portion laterally (e.g., in the y-direction) adjacent to the first portion. In some embodiments, fin structure108's first and second portions can be a channel region and a source/drain (S/D) region of a transistor of semiconductor device100. Each of fin structure108's first and second portions can be made of a material similar to substrate102, such as a material having a lattice constant substantially close to (e.g., lattice mismatch within 5%) that of substrate102. In some embodiments, fin structure108's first and/or second portions can be made of a material identical to substrate102. Each of fin structure108's first and second portions can be un-doped, doped with p-type dopants, doped with n-type dopants, or doped with intrinsic dopants. In some embodiments, fin structure108's first and second portions can be doped with dopants with different doping type (e.g., n-type or p-type) from one another.

Semiconductor device100can further include a gate structure110that wraps around one or more fin structures108. Gate structure110can have a height H110, such as from about 80 nm to about 110 nm. Gate structure110can include a gate dielectric layer (not shown inFIG.1) and a gate electrode (not shown inFIG.1) disposed on the gate dielectric layer. The gate dielectric layer can include any suitable dielectric material, such as a low-k dielectric material and a high-k dielectric material, with any suitable thickness, such as from about 1 nm to about 5 nm, that can provide channel modulation for fin structure108. In some embodiments, the term “low-k dielectric material” can refer to a dielectric material with a dielectric constant less than about 3.9. In some embodiments, the low-k dielectric material for the gate dielectric can include silicon oxide or silicon nitride. In some embodiments, the term “high-k dielectric material” can refer to a dielectric material with a dielectric constant greater than about the dielectric constant of the low-k dielectric material. For example, the dielectric constant of the high-k dielectric material can be greater than about 3.9. In some embodiments, the high-k dielectric material for the gate dielectric can include hafnium oxide, aluminum oxide, or the combination thereof. Based on the disclosure herein, other materials and thicknesses for the gate dielectric layer are within the spirit and scope of this disclosure.

The gate electrode of gate structure110can include any suitable conductive material that provides a suitable work function to modulate fin structure108. In some embodiments, the gate electrode can include titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, copper, or nickel. Based on the disclosure herein, other materials for the gate electrode are within the spirit and scope of this disclosure.

Gate structure110can further include a gate spacer (not shown inFIG.1) formed over the gate electrode and/or the gate dielectric layer. In some embodiments, the gate spacer can be further formed over fin structure108's side surface (not shown inFIG.1). The gate spacer can be made of any suitable dielectric material, such as the low-k dielectric material and the high-k dielectric material. Based on the disclosure herein, other materials for the gate spacer are within the spirit and scope of this disclosure.

Semiconductor device100can further include shallow trench isolation (STI) regions138to provide electrical isolation between fin structures108. Also, STI regions138can provide electrical isolation between fin structures108and neighboring active and passive elements (not shown inFIG.1) integrated with or deposited on substrate102. STI regions138can include insulating layers with a suitable height H138, such as from about 40 nm to about 60 nm, disposed on substrate102and between fin structures108. In some embodiments, the term “insulating layer” can refer to a layer that functions as an electrical insulator (e.g., a dielectric layer). In some embodiments, the insulating layer for STI region138can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, or a high-k dielectric material. Based on the disclosure herein, other materials and thicknesses for STI region138are within the spirit and scope of this disclosure.

Semiconductor device100can further include an isolation structure140disposed between two laterally (e.g., in the y-direction) adjacent fin structures108. Accordingly, isolation structure140's width W140can be less than separation S108between the two laterally (e.g., in the y-direction) adjacent fin structures108. In some embodiments, isolation structure140's width W140can be from about 10 nm to about 40 nm. Isolation structure140can further horizontally (e.g., in the x-direction) extend through gate structure110that travers isolation structure140's two laterally (e.g., in the y-direction) adjacent fin structures108. In some embodiments, isolation structure140can electrically isolate gate structure110that is traversed by isolation structure140. Accordingly, a segment of gate structure110on one fin structure108can be electrically insulated from another segment of gate structure110on the laterally (e.g., in the y-direction) fin structure108by isolation structure140.

Isolation structure140can include a first dielectric layer140L disposed over STI region138. First dielectric layer140L can be made of a tow-k dielectric material to electrically, isolate the two laterally adjacent fin structures108placed at opposite sides of isolation structure140. In some embodiments, the tow-k dielectric material for first dielectric layer140L can be a metal-free dielectric material, such as silicon oxide and silicon nitride. In some embodiments, first dielectric layer140L can embed void structure140V. In some embodiments, the lateral (e.g., in the y-direction) a separation between void structure140V and one of the isolation structure140's two laterally (e.g., in the y-direction) adjacent fin structures108can be substantially equal to another separation between void structure140V and another of the isolation structure140's two laterally (e.g., in the y-direction) adjacent fin structures108.

First dielectric layer140L can horizontally (e.g., in the x-direction) extend through a bottom portion of the gate structure140that traverses the isolation structure140's two laterally adjacent fin structures108, where an upper portion of the gate structure140can be formed over first dielectric layer140L. For example, the gate structure110that is extended through by first dielectric layer140L can have a height H110, where gate structure110's height H110can be greater than first dielectric layer140L's height H140L. In some embodiments, first dielectric layer140L's height H140Lcan be from about 50 nm to about 80 nm. In some embodiments, first dielectric layer140L's width can be substantially equal to width W140, where a ratio of first dielectric layer140L's height to width W140can be from about 1.2 to about 8 or from about 2 to about 5. If the ratio of the height to width W140is less than the above-noted lower limits, the fin pitch of semiconductor device100may not be sufficient to accommodate first dielectric layer140L (e.g., fin pitch may be required to be less than about 60 nm for a 22 nm technology node). If the ratio of the height H140L, to width W140is greater than the above-noted upper limits, first dielectric layer140L may collapse due to first dielectric layer140L's limited mechanical strength.

In some embodiments, isolation structure140can further include a second dielectric layer140U disposed over first dielectric layer140L. Second dielectric layer140U can be made of a high-k dielectric material, such as a metal oxide, to electrically isolate the two laterally adjacent fin structures108placed at opposite sides of isolation structure140. Accordingly, first dielectric layer140L and second dielectric layer140U can have different etching selectivity from each other. In some embodiments, the term “etching selectivity” can refer to the ratio of the etch rates of two materials under a same etching condition. In some embodiments, second dielectric layer140U can be made of an oxide material that includes a metallic element, silicon, and oxygen. In some embodiments, second dielectric layer140U can be made of a cross-linked mixture (e.g., polymer2108shown inFIG.21) of a metal oxide and a silicon oxide. In some embodiments, second dielectric layer140U can be made of a metal oxide doped with a dopant. The dopant doped in the metal oxide of second dielectric layer140U can be silicon, germanium, aluminum, a transition metal, or a rare-earth metal. The dopant (e.g., silicon and/or germanium) doped in the metal oxide of second dielectric layer140U can have the atomic concentration of the silicon doped in the metal oxide can be from about 4% to about 20%. If the atomic concentration of the dopant is less than the above-noted lower limits, second dielectric layer140U's dielectric constant may be too high to cause an increased parasitic capacitance in semiconductor device100. If the atomic concentration of the dopant is greater than the above-noted lower limits, there may not have sufficient etching selectivity between first dielectric layer140L and second dielectric layer140U to connect gate structure110between two laterally (e.g., in the y-direction) fin structures108(discussed in method200). In some embodiments, second dielectric layer140U can be a seamless dielectric layer (e.g., second dielectric layer140U does not embed void structures) to ensure an sufficient electrical isolation between the isolation structure140's two laterally adjacent fin structures108.

Second dielectric layer140U can horizontally (e.g., in the x-direction) extend through the gate structure140that traverses the isolation structure140's two laterally adjacent fin structures108. Further, second dielectric layer140U can have a height H140Uformed over first dielectric layer140L that allows second dielectric layer140U being formed over the gate structure140that traverses the isolation structure140's two laterally adjacent fin structures108. Accordingly, isolation structure140's height (e.g., equal to the sum of first dielectric layer140L's height H140Land second dielectric layer140U's height H140U) can be greater than gate structure110's height H110. In some embodiments, second dielectric layer140U's height H140Ucan be from about 15 nm to about 40 nm. In some embodiments, a ratio of isolation structure140's height (e.g., the sum of heights H140Land H140U) to gate structure110's height H110can be from about 1.1 to about 2.0. If the ratio of isolation structure140's height (e.g., the sum of heights H140Land H140U) to gate structure110's height H110is less than the above-noted lower limits, second dielectric layer140U may not provide an sufficient isolation between isolation structure140's two laterally (e.g., in the y-direction) adjacent fin structures108. If the ratio of isolation structure140's height (e.g., the sum of heights H140Land H140U) to gate structure110's height H110is greater than the above-noted upper limits, isolation structure140may collapse due to isolation structure140's limited mechanical strength. In some embodiments, second dielectric layer140U's width can be substantially equal to width W140.

In some embodiments, a ratio of isolation structure140's height (e.g., the sum of heights H140Land H140U) to isolation structure140's width W140can be from about 2 to about 11. If the ratio of isolation structure140's height (e.g., the sum of heights H140Land H140U) to isolation structure140's width W140is less than the above-noted lower limits, semiconductor device100may not meet the fin pitch requirement determined by the respective technology node (e.g., fin pitch may be required to be less than about 60 nm for a 22 nm technology node). If the ratio of isolation structure140's height (e.g., the sum of heights H140Land H140U) to isolation structure140's width W140is greater than the above-noted upper limits, isolation structure140may collapse due to isolation structure140's limited mechanical strength.

In some embodiments, a ratio of second dielectric layer140U's height H140Uto first dielectric layer140L's height H140Lcan be from about 0.15 to about 0.8. If the ratio of height H140Uto height H140Lis less than the above-noted lower limits, first dielectric layer140L may be damaged during the process of forming gate structure110(discussed below at operation220), thus causing the failure the electrical short in semiconductor device100. If the ratio of height H140Uto height H140Lis greater than the above-noted upper limits, the parasitic capacitance between isolation structure140's two laterally (e.g., in the y-direction) fin structures108can be too high to degrade semiconductor device100's speed.

Semiconductor device100can further include an interlayer dielectric (ILD) layer118to provide electrical isolation to structural elements it surrounds or covers, such as fin structure108and gate structure110. ILD layer118can include any suitable dielectric material to provide electrical insulation, such as silicon oxide, silicon dioxide, silicon oxycarbide, silicic n oxynitride, silicon oxy-carbon nitride, and silicon carbonitride. ILD layer118can have any suitable thickness, such as from about 50 nm to about 200 nm, to provide electrical insulation. Based on the disclosure herein, other insulating materials and thicknesses for ILD layer118are within the scope and spirit of this disclosure.

FIG.2is a flow diagram of an example method200for fabricating semiconductor device100, according to some embodiments. For illustrative purposes, the operations illustrated inFIG.2will be described with reference to the example fabrication process for fabricating semiconductor device100as illustrated inFIGS.3-27.FIGS.3-18,20, and22-27are cross-sectional views along line B-B ofFIG.1at various stages of its fabrication, according to some embodiments.FIGS.19and21illustrate chemical formula of isolation structure140's material at various stages of its fabrication, according to some embodiments. Operations can be performed in a different order or not performed depending on specific applications. It should be noted that method200may not produce a complete semiconductor device100. Accordingly, it is understood that additional processes can be provided before, during, and after method200, and that some other processes may only be briefly described herein. Further, the discussion of elements inFIGS.1-27with the same annotations applies to each other, unless mentioned otherwise.

Referring toFIG.2, in operation205, multiple fin structures are formed on a substrate. For example, as shown inFIG.3, fin structures108with separation S108can be formed on substrate102. The process of forming fin structures108can include (i) forming, using a lithography process, multiple patterned hard mask layers342with separation S108and over substrate102, (ii) etching portions of substrate102through patterned hard mask layers342to form recess structures301with height H108over substrate102, and (iii) forming STI region138with height H138in recess structures301and over the etched substrate102using a deposition process and an etch back process. In some embodiments, hard mask layer342can be made of a low-k dielectric material, such as silicon oxide and silicon nitride. The etching of the portions of substrate102can include a dry etch, a wet etch process, or a combination thereof. The dry etch process for etching substrate102can include using etchants with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBR3), or an iodine-containing gas. The wet etch process for etching substrate102can include etching in diluted hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia, a solution containing hydrofluoric acid (HF), nitric acid (HNO3), or acetic acid (CH3COOH).

Referring toFIG.2, in operation210, a first isolation structure is formed between each of the multiple fin structures. For example, as shown inFIG.6, first dielectric layer140L can be formed between two laterally (e.g., in the y-direction) adjacent fin structures108with reference toFIGS.4-6. The process of forming first dielectric layer140L can include depositing a seed layer, such as seed layer402(shown inFIG.4), over side surfaces of fin structures108of the structure ofFIG.3. Seed layer402can be made of any suitable semiconductor material, such as silicon germanium, that can be selectively deposited on a semiconductor surface (e.g., over fin structure108's side surfaces) over a dielectric surface (e.g., STI region138's top surface), using any suitable deposition process, such as a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process. In some embodiments, seed layer402formed over two opposite sides of fin structures108can be merged with each other, and therefore seed layer402can be in contact with a top surface and side surfaces of patterned hard mask layers342.

In some embodiments, the process of depositing the seed layer can further include forming a capping layer404(shown inFIG.4) over seed layer402using a selective deposition process. In some embodiments, capping layer404can be a semiconductor material that is different from seed layer402, where the respective selective deposition process can be a CVD process or an ALD process. In some embodiments, capping layer404can be a dielectric material, such as silicon oxide and silicon nitride, where the respective selective deposition process can include a silylation process and a deposition process. The silylation process can form a layer of inhibitor material (not shown inFIG.4) over the exposed dielectric surfaces (e.g., STI regions138's top surface) in recess structures301. Because the layer of inhibiting material can inhibit the nucleation of depositing the dielectric materials for capping layer404, the deposition of the dielectric materials for capping layer404can be delayed or inhibited over STI regions138. Therefore, the above-noted selective deposition process can selectively form capping layer404over seed layer402. In some embodiments, the chemical agent applied by the silylation process can include dimethylsilane (DMS), trimethylsilane (TMS), dimethytaminotrimethylsilane (DMA-TMS), octadecyltrichlorosilane (OTS), florooctyltriclorosilane (FOTS), dichlorodimethylsilane (DMDCS), trimethylsilydiethylamine (TMSDEA), trimethylsilylacetylene (TMSA), (chloromethyl)dimethylchlorosilane (CMDMCS), (chloromethyl)dimethylsilane (CMDMS), hexamethyldisilazane MUDS), tert-Butyldimethylsilane (TBDMS), octamethylcyclotetrasilaxane (OMCTS), bis(dimethylamino)dimethylsilane (DMADMS), or trimethylchlorosilane (TMCS). In some embodiments, the process of forming seed layer402and/or forming capping layer404can define recess structure301's width WHO (later becoming isolation structure140's width W140after method200).

Referring toFIG.5, the process of forming first dielectric layer140L can include forming a dielectric material540in recess structures301and over seed layer402(or over capping layer404) of the structure ofFIG.4using a deposition process, such as a CVD process, an ALD process, a high-density-plasma (HDP) CVD process, a high aspect-ratio process (HARP), and a spin-on process. Dielectric material540can be made of identical material of first dielectric layer140L discussed inFIG.1. In some embodiments, the process for forming dielectric material540can have a substantially equal deposition rates at the proximities of recess structure301's top and bottom (e.g., a conformal deposition process) to form void structures140V (shown inFIG.5) in portions of dielectric material540in recess structures301. In some embodiments, the process for forming dielectric material540can have higher deposition rates proximate to recess structure301's top than proximate to recess structure301's bottom to form void structures140V (shown inFIG.5) in portions of dielectric material540in recess structures301. In some embodiment, the process for forming dielectric material540can have a greater deposition rates proximate to recess structure301's bottom than proximate to recess structure301's top to eliminate void structures140V.

Referring toFIG.6, the process of forming first dielectric layer140L can further include etching hack dielectric material540to define first dielectric layer140L. The process of etching back dielectric material540can include performing a polishing process, such as a chemical mechanical polishing (CMP) process, to planarize top surfaces of dielectric material.540with hard mask layers342, with seed layer402, and/or with capping layer404. The process of etching back dielectric material540can further include performing an etching process to remove portions of the planarized dielectric material540to form recess structures601between two laterally adjacent fin structures. After the etch back process, the resulting first dielectric layer140L can have height H140Lbetween first dielectric layer140L's and STI regions138.

Referring toFIG.2, in operation215, a second isolation structure is formed over the first isolation structure. For example, as shown inFIG.13, second dielectric layer140U can be formed over first dielectric layer140L. In some embodiments, operation215can include performing a doping process to dope a spin-coated metal oxide to form second dielectric layer140U with reference toFIGS.7-13(a doping mode). In some embodiments, operation215can include performing a laminate coating process to form second dielectric layer140U with reference toFIGS.13and14-17(a laminate mode). In some embodiments, operation215can include performing a spin-coating process to coat a metal silicate material to form second dielectric layer140U with reference toFIGS.13and18-21(a hybrid mode).

Referring toFIGS.7and8, in the doping mode and with reference toFIGS.7-13, operation215can include performing a sol-gel or a metalorganic frame process to spin-coat or dip-coat a flowable dielectric material to fill recess structures601ofFIG.6. The flowable dielectric material can include a metal oxide colloid. In some embodiments, the metal oxide colloid can include zirconium oxide (ZrOx), hafnium oxide (HfOx), aluminum oxide (AlOx), or the combination thereof, where the metal oxide colloid's chemical formula can include the metallic elements of zirconium (Zr), hafnium (Hf), aluminum, a refractory metal, or a rare-earth metal.

The sol-gel or metalorganic frame process can further include performing an annealing process on substrate102to remove the solvent from the coated flowable dielectric material to form a metal oxide layer740(shown inFIG.7and/orFIG.8) over first dielectric layer140L and over fin structures108. The annealing process can be performed at a temperature from about 50° C. to about 250° C. or from about 80° C. to about 200° C. with a suitable ambient gas environment, such as nitrogen and oxygen. If the temperature of the annealing process is less than the above-noted lower limits, the annealing process may not remove the solvent from the flowable dielectric material. If the temperature of the annealing process is greater than the above-noted upper limits, method200may not able to dope silicon element (discussed below) in metal oxide layer740to form second dielectric layer140U to lower the dielectric constant of isolation structure140, thus causing a high parasitic capacitance in semiconductor device100. Further, the annealing process can be performed with a suitable time duration from about 30 seconds to about 180 seconds or from about 60 seconds to about 120 seconds. If the time duration of the annealing process is less than the above-noted lower limits, the annealing process may not remove the solvent from the flowable dielectric material. If the time duration of the annealing process is greater than the above-noted upper limits, method200may not meet the manufacturing throughput requirement to fabricate semiconductor device100, thus increasing the production cost of semiconductor device100.

In some embodiments, as shown inFIG.7, metal oxide layer740formed by a cycle of the sol-gel process can have a bottom thickness d740Lover first dielectric layer140L and a top thickness d740Uover fin structure108(e.g., a single cycle of the sol-gel process does not fill recess structure601). Because the sol-gel process can direct the flowable dielectric material flowing towards recess structures601, the resulting oxide layer740's bottom thickness d740L(e.g., about 10 nm) can be greater than top thickness d740U(e.g., about 5 nm). In some embodiments, as shown inFIG.8, one or more cycles of the sol-gel process can be performed to spin-coat or dip-coat the flowable dielectric material to fill recess structures601ofFIG.6to form metal oxide layer740with a suitable thickness t740, such as about 50 nm, over fin structures108. Because each of the one or more cycles of the sol-gel process can direct the flowable dielectric material flowing towards recess structures601, the resulting metal oxide layer740can be a seamless (e.g., without void structures) dielectric layer in recess structure601.

Referring toFIGS.9-11, in the doping mode, operation215can further include (i) planarizing, via a CMP process,FIG.8's metal oxide layer740to formFIG.9's metal oxide layer740with height H140Uand be coplanar with hard mask layers342, (ii) forming, via a lithography process, hard mask layers1002(shown inFIG.10) over fin structures108, seed layers402, and/or capping layers404, and (iii) performing a doping process to provide dopants1102(shown inFIG.11) in metal oxide layer740. Dopant1102can include silicon, germanium, and/or aluminum that can reduce second dielectric layer140L's dielectric constant after operation215. The doping process can include a diffusion process or an implantation process to drive dopants1102into metal oxide layer740and hard mask layer1002. In some embodiments, as shown inFIG.11, dopant1102in metal oxide layer740and hard mask layer1002can include a peak doping concentration with a bandwidth defined by a full width of about 50%, about 70%, or about 90% of the peak doping concentration. In some embodiments, in the doping mode, operation215can further include forming a layer of dielectric material (e.g., an oxide layer; not shown inFIG.9) over the structure ofFIG.9before forming hard mask layers1002.

Referring toFIGS.12and13, in the doping mode, operation215can further include (i) removing hard mask layers1002via an etching process (shown inFIG.12), and (ii) performing an annealing process to activate dopants1102in metal oxide layer740and crystallize metal oxide layer740to form second dielectric layer140U (shown inFIG.13) over first dielectric layer140L. The annealing process for activating dopants1102in metal oxide layer740and crystallizing metal oxide layer740can include a rapid thermal annealing process and/or a furnace annealing process with suitable time durations. In some embodiments, the time duration of the furnace annealing process can be at least about 5 times, at least about 10 times, at least about 20 times, at least about 50 times, or at least about 100 times greater than the time duration of the rapid thermal annealing process. In some embodiments, the annealing process for activating dopants1102in metal oxide layer740and crystallizing metal oxide layer740can be a rapid thermal annealing process with a suitable time duration from about 10 seconds to about 30 seconds. In some embodiments, to provide a sufficient thermal energy to activate dopants1102in metal oxide layer740and crystallize metal oxide layer740, the annealing process for activating dopants1102in metal oxide layer740and crystallizing metal oxide layer740can be a furnace annealing process with a time duration greater than the time duration of the annealing process (e.g., for removing the solvent from the coated flowable dielectric material) performed with respect toFIG.7and/orFIG.8. For example, the annealing process for activating dopants1102in metal oxide layer740and crystallizing metal oxide layer740can be a furnace annealing process with a time duration from 10 minutes to about 100 minutes or from 30 minutes to about 90 minutes. If the time duration of the furnace annealing process is less than the above-noted lower limits, the furnace annealing process may not crystallize metal oxide layer740and/or distribute dopants1102in metal oxide layer740. If the time duration of the furnace annealing process is greater than the above-noted upper limits, isolation structure140formed by method200may become porous, thus causing a leakage current in semiconductor device100.

Further, the annealing process can be performed at a temperature greater than the temperature of the annealing process performed with respect toFIG.7and/orFIG.8to provide a sufficient thermal energy to activate dopants1102in metal oxide layer740and crystallize metal oxide layer740. For example, the annealing process can be performed at a temperature from about 550° C. to about 950° C., from about 600° C. to about 900° C., from about 700° C. to about 900° C., or from about 750° C. to about 900° C. with a suitable ambient gas environment, such as nitrogen and oxygen. If the temperature of the annealing process is less than the above-noted lower limits, the annealing process may not crystallize metal oxide layer740or distributing dopants1102in metal oxide layer740. If the temperature of the annealing process is greater than the above-noted upper limits, isolation structure140formed by method200may become porous, thus causing a leakage current in semiconductor device100.

Referring toFIGS.14-16, in the laminate mode and with reference toFIGS.13and14-17, operation215can include performing a cyclic sol-gel process to spin-coat or dip-coat flowable dielectric material stack to fill recess structures601ofFIG.6. For example, the cyclic sol-gel process can include a first sol-gel process to coat a first flowable dielectric material to form a first oxide layer1440(shown inFIG.14) over the structure ofFIG.6. The cyclic sol-gel process can further include a second sol-gel process to coat a second flowable dielectric material to form a second oxide layer1540(shown inFIG.15) over first oxide layer1440. The first flowable dielectric material can be different from the second flowable dielectric material. Accordingly, first oxide layer1440can be a different material from second oxide layer1540. In some embodiments, the first flowable dielectric material can be a metal-contained colloid (e.g., identical to the metal oxide colloid discussed with respect toFIG.7and/orFIG.8), and the second flowable dielectric material can be a metal-free colloid (e.g., PFOTES or FTES). Accordingly, first oxide layer1440can be a metal oxide layer, and second oxide layer1540can be a low-k oxide layer (e.g., silicon oxide). The cyclic sol-gel process can be repeatedly performed until recess structures601are filled by the stack of first oxide layer1440and second oxide layer1540(shown inFIG.16). In some embodiments, to provide a metal-rich top surface for second dielectric layer140U (e.g., for increasing etching selectivity between second dielectric layer140U and first dielectric layer140L; discussed at operation220), the last cycle of the cyclic sol-gel process can only include the first sol-gel process to form a top metal oxide layer1440as illustrated atFIG.16.

Similar to the sol-gel process discussed with respect toFIG.7and/orFIG.8, the cyclic sol-gel process performed with respect toFIGS.14-16can include performing an annealing process on substrate102to remove solvents from the coated first and second flowable dielectric materials to form first oxide layer1440and second oxide layer1540over one another. The annealing process for the cyclic sol-gel process (e.g., each of the first and second sol-gel processes) can be performed at a temperature from about 50° C. to about 250° C. or from about 80° C. to about 200° C. with a suitable ambient gas environment, such as nitrogen and oxygen. If the temperature of the annealing process is less than the above-noted lower limits, the annealing process may not remove the solvent from the first and second flowable dielectric materials. If the temperature of the annealing process is greater than the above-noted upper isolation structure140formed by method200may become porous; thus causing a leakage current in semiconductor device100. Further, the annealing process can be performed with a suitable time duration from 30 seconds to about 180 seconds or from 60 seconds to about 120 seconds. If the time duration of the annealing process is less than the above-noted lower limits, the annealing process may not remove the solvent from the first and second flowable dielectric materials. If the time duration of the annealing process is greater than the above-noted upper limits, method200may not meet the manufacturing throughput requirement to fabricate semiconductor device100, thus increasing the production cost of semiconductor device100.

Similar to the sol-gel process discussed with respect toFIG.7and/orFIG.8, first oxide layer1440formed by a cycle of the first sol-gel process can have a bottom thickness d1440L(shown inFIG.14) outside recess structure601and a top thickness d1440U(shown inFIG.14) over fin structure108. Because the first sol-gel process can direct the first flowable dielectric material flowing towards recess structures601, the resulting first oxide layer1440's bottom thickness d1440Labout 10 nm) can be greater than top thickness d1440U(e.g., about 5 nm). Similarly, second oxide layer1540formed by a single cycle of the second sol-gel process can have a bottom thickness d1540L(shown inFIG.15) outside recess structure601and a top thickness d1540U(shown inFIG.15) over fin structure108. Because the second sol-gel process can direct the second flowable dielectric material flowing towards recess structures601, the resulting second oxide layer1540's bottom thickness d1540L(e.g., about 10 nm) can be greater than top thickness d1540U(e.g., about 5 mu). Because each cycle of the cyclic sol-gel process can direct the first and second flowable dielectric materials flowing towards recess structures601, the resulting stack of first oxide layer1440and second oxide layer1540can be a seamless (e.g., without void structures) dielectric stack in recess structure601.

Referring toFIG.17, in the laminate mode, operation215can further include (i) performing an annealing process to cross-link first oxide layers1440and second oxide layers1540of the structure ofFIG.16to form second dielectric layer140U (shown inFIG.17) over first dielectric layer140L and over fin structures108, and (ii) planarizing, via a CMP process,FIG.17's second dielectric layer140U to formFIG.13's second dielectric layer140U with height H140Uand be coplanar with hard mask layers342. In some embodiments, the term “cross-linking a first and second materials” can refer to (i) forming a covalent bond between the first and the second materials, or (ii) blending the first and second materials. The annealing process for cross-linking first oxide layers1440and second oxide layers1540can include a rapid thermal annealing process and/or a furnace annealing process with suitable time durations. In some embodiments, the annealing process for cross-linking first oxide layers1440and second oxide layers1540can be a rapid thermal annealing process with a suitable time duration from about 10 seconds to about 30 seconds. In some embodiments, to provide a sufficient thermal energy to cross-link first oxide layers1440and second oxide layers1540, the annealing process for cross-linking first oxide layers1440and second oxide layers1540can be a furnace annealing process with a time duration greater than the time duration of the annealing process (e.g., for removing the solvent from the coated flowable dielectric material) performed with respect toFIGS.14-16. For example, the annealing process for cross-linking first oxide layers1440and second oxide layers1540can be a furnace annealing process with a time duration from 10 minutes to about 100 minutes or from 30 minutes to about 90 minutes. If the time duration of the furnace annealing process is less than the above-noted lower limits, the furnace annealing process may not cross-link first oxide layers1440and second oxide layers1540. If the time duration of the furnace annealing process is greater than the above-noted upper limits, isolation structure140formed by method200may become porous, thus causing a leakage current in semiconductor device100.

Further, the annealing process for cross-linking first oxide layers1440and second oxide layers1540can be performed at a temperature greater than the temperature of the annealing process performed with respect toFIGS.14-16to provide a sufficient thermal energy to cross-link first oxide layers1440and second oxide layers1540. For example, the annealing process for cross-linking first oxide layers1440and second oxide layers1540can be performed at a temperature from about 550° C. to about 950° C., from about 600° C. to about 900° C., from about 700° C. to about 900° C., or from about 750 CC to about 900° C. with a suitable ambient gas environment, such as nitrogen and oxygen. If the temperature of the annealing process is less than the above-noted lower limits, the annealing process may not cross-link first oxide layers1440and second oxide layers1540. If the temperature of the annealing process is greater than the above-noted upper limits, isolation structure140formed by method200may become porous, thus causing a leakage current in semiconductor device100.

Referring toFIGS.18and19, in the hybrid mode and with reference toFIGS.13and17-20, operation215can include performing a sol-gel process to spin-coat or dip-coat a flowable monomer material to form a metal-silicate layer1840(shown inFIG.18) in recess structures601ofFIG.6. In some embodiments, the flowable monomer material can include a mixture of a metal-R monomer material1902(shown inFIG.19) and a silicon-R monomer material1904(shown inFIG.19). In some embodiments, the terms “-R” inFIGS.18and20can refer to a functional group that includes hydrocarbon or hydroxycarbanyl (e.g., CxHyor O—CxHy). In some embodiments, metal-R monomer material1902can be Zr—[O—CH3]4. In some embodiments, silicon-R monomer material1904can be Si—[O—CH3]4. In some embodiments, the flowable monomer material can include both silicon and a metallic element, such as metal-Si—R or Si-metal-R monomers1906and1908(shown inFIG.19). In some embodiments, monomer1906can be Zr—[O—CH3]3Si[CH3]3. In some embodiments, monomer1908can be Si—[O—CH3]3Zr[CH3]3. Because the sol-gel process can direct the flowable monomer material flowing towards recess structures601, the resulting metal-silicate layer1840can be a seamless (e.g., without void structures) dielectric layer in recess structure601.

Similar to the sol-gel process discussed with respect toFIG.7and/orFIG.8, the sol-gel process performed with respect toFIG.18can include performing an annealing process on substrate102to remove solvents to enhance the hydroxylation reaction of coated flowable monomer materials to form metal-silicate layer1840. The annealing process for the sol-gel process can be performed at a temperature from about 50° C. to about 250° C. or from about 80° C. to about 200° C. with a suitable ambient gas environment, such as nitrogen and oxygen. If the temperature of the annealing process is less than the above-noted lower limits, the annealing process may not remove the solvent from the flowable monomer material. If the temperature of the annealing process is greater than the above-noted upper limits, isolation structure140formed by method200may become porous, thus causing a leakage current in semiconductor device100. Further, the annealing process can be performed with a suitable time duration from 30 seconds to about 180 seconds or from 60 seconds to about 120 seconds. If the time duration of the annealing process is less than the above-noted lower limits, the annealing process may not remove the solvent from the flowable monomer materials. If the time duration of the annealing process is greater than the above-noted upper limits, method200may not meet the manufacturing throughput requirement to fabricate semiconductor device100, thus increasing the production cost of semiconductor device100.

Referring toFIGS.20and21, in the hybrid mode, operation215can further include performing a hydroxylation enhancement process on substrate102to increase hydroxyl groups in the flowable monomer material to form hydroxylation monomer layer2040(shown inFIG.20) over first dielectric layer1401, and over fin structures108. In some embodiments, as shown inFIG.21, hydroxylation monomer layer2040can include a hydroxyl-metal monomer2102, a hydroxyl-silicon monomer2104, or a hydroxyl-metal-silicon monomer2106. The temperature of the hydroxylation enhancement process can be performed at a temperature greater than the temperature of the solvent-removal annealing process performed with respect toFIG.18to provide a sufficient thermal energy to increase hydroxyl groups in the flowable monomer material to form hydroxylation monomer layer2040. For example; the annealing process for the hydroxylation enhancement process can be performed at a temperature from about 250° C. to about 600° C., from about 300° C. to about 600° C., from about 300° C. to about 550° C., or from about 300° C. to about 500° C. with a suitable ambient gas environment, such as nitrogen and oxygen. If the temperature of the hydroxylation enhancement process is less than the above-noted lower limits, the annealing process may not introduce hydroxyl metal-O—Si in the flowable monomer material to form hydroxylation monomer layer2040. If the temperature of the hydroxylation process is greater than the above-noted upper limits, isolation structure140formed by method200may become porous, thus causing a leakage current in semiconductor device100.

In some embodiments, the hydroxylation enhancement process for increasing hydroxyl groups in the flowable monomer material to form hydroxylation monomer layer2040can be a rapid thermal annealing process with a suitable time duration from about 10 seconds to about 30 seconds. In some embodiments, to provide a sufficient thermal energy to increase hydroxyl groups in the flowable monomer material to form hydroxylation monomer layer2040, the hydroxylation enhancement process can be a furnace annealing process with a time duration greater than the time duration of the annealing process (e.g., for removing the solvent from the coated flowable dielectric material) performed with respect toFIG.18. For example, the hydroxylation enhancement process can be a furnace annealing process with a time duration from 10 minutes to about 100 minutes or from 30 minutes to about 90 minutes. If the time duration of the furnace annealing process is less than the above-noted lower limits, the furnace annealing process may not increase hydroxyl groups in the flowable monomer material to form hydroxylation monomer layer2040. If the time duration of the furnace annealing process is greater than the above-noted upper limits, isolation structure140formed by method200may become porous, thus causing a leakage current in semiconductor device100.

In the hybrid mode, operation215can further include (i) performing an annealing process on the structure ofFIG.20to cross-link hydroxylation monomer layer2040(e.g., cross-link one another of hydroxyl-metal monomer2102, hydroxyl-silicon monomer2104, and/or hydroxyl-metal-silicon monomer2106to form second dielectric layer140U which chemical formula can be represented by polymer2108) to form second dielectric layer140U ofFIG.17over first dielectric layer140L and over fin structures108, and (ii) planarizing, via a CMP process,FIG.20's second dielectric layer140U to formFIG.13's second dielectric layer140U with height, and be coplanar with hard mask layers342. The annealing process for cross-linking hydroxylation monomer layer2040can include a rapid thermal annealing process and/or a furnace annealing process with suitable time durations. In some embodiments, the annealing process for cross-linking hydroxylation monomer layer2040can be a rapid thermal annealing process with a suitable time duration from about 10 seconds to about 30 seconds. In some embodiments, to provide a sufficient thermal energy to cross-link hydroxylation monomer layer2040, the annealing process for cross-linking hydroxylation monomer layer2040can be a furnace annealing process with a time duration greater than the time duration of the furnace annealing process (e.g., for removing the solvent from the coated flowable dielectric material) performed with respect toFIG.18. For example, the annealing process for cross-linking hydroxylation monomer layer2040can be a furnace annealing process with a time duration from 10 minutes to about 100 minutes or from 30 minutes to about 90 minutes. If the time duration of the furnace annealing process is less than the above-noted lower limits, the furnace annealing process may not cross-link hydroxylation monomer layer2040. If the time duration of the furnace annealing process is greater than the above-noted upper limits, isolation structure140formed by method200may become porous, thus causing a leakage current in semiconductor device100.

Further, the annealing process for cross-linking hydroxylation monomer layer2040can be performed at a temperature greater than the temperature of the annealing process performed with respect toFIG.18to provide a sufficient thermal energy to cross-link first hydroxylation monomer layer2040. For example, the annealing process for cross-linking first hydroxylation monomer layer2040can be performed at a temperature from about 550° C. to about 950° C., from about 600° C. to about 900° C., from about 700° C. to about 900° C., or from about 750° C. to about 900° C. with a suitable ambient gas environment, such as nitrogen and oxygen. If the temperature of the annealing process is less than the above-noted lower limits, the annealing process may not cross-link hydroxylation monomer layer2040. If the temperature of the annealing process is greater than the above-noted upper limits, isolation structure140formed by method200may become porous, thus causing a leakage current in semiconductor device100.

Referring toFIG.2, in operation220, a gate structure is formed on the multiple fin structures, where the gate structure can be segmented by the second isolation structure. For example, as shown inFIG.26or27, gate structure110can be formed over fin structures108and segmented by second dielectric layer140L with reference toFIGS.22-27.

Referring toFIG.22, operation220can begin with (i) forming a sacrificial gate structure (not shown inFIGS.13and22) overFIG.13's fin structures108, overFIG.13's first dielectric layers140L, and overFIG.13's second dielectric layer140U, (ii) forming ILD layer118(not shown inFIGS.13and22) coplanar with the sacrificial gate structure, (iii) removing the sacrificial gate structure to expose hard mask layers342and second dielectric layers140L as illustrated inFIG.13, (iv) removing, via an etching process, hard mask layers342from the structure ofFIG.13, and (v) removing, via another etching process, seed layer402and capping layer404from the structure ofFIG.13to expose fin structures108, first dielectric layer140L, second dielectric layers140U. The etching process of removing seed layer402and capping layer404can have a higher etching rate towards seed layer402and capping layer404and a lower etching rate towards fin structure108. For example, fin structure108, seed layer402, and capping layer404can be made of silicon, silicon germanium, and silicon nitride, respectively, where the etching process can remove silicon germanium (e.g., seed layer402) and silicon nitride (capping layer404) at a greater etching rate and remove silicon (e.g., fin structure108) at a lower etching rate. In some embodiments, the etching process of removing seed layer402can selectively remove seed layer402over capping layer404and over fin structures108. Accordingly, as shown inFIG.23, after removing seed layer402, capping layer404can remain over sidewalls of first dielectric layer140L and second dielectric layer140U.

Referring toFIGS.24and25, operation220can further include (i) forming, via a lithography process, a hard mask layer2402(shown inFIG.24) to mask one of the first dielectric layer140L and second dielectric layer140U (e.g., masking isolation structure140-Right shown inFIG.24) and expose another of the first dielectric layer140L and second dielectric layer140U (e.g., exposing isolation structure140-Left shown inFIG.24), and (ii) removing, via a selective etching process, isolation structure140-Left's second dielectric layer140U over isolation structure140-Left's first dielectric layer140L (shown inFIG.25). Accordingly, after the above-noted selective etching process, isolation structure140-Left's top surface can be vertically (e.g., in the z-direction) lower than adjacent fin structures108's top surfaces (e.g., the sum of first dielectric layer140L's height H140Land STI region138's height H138can be less than fin structure108's height H108.) Further, after the above-noted selective etching process, isolation structure140-Right's top surface can be vertically (e.g., in the z-direction) higher than adjacent fin structures108's top surfaces (e.g., the sum of first dielectric layer140L's height H140L, second dielectric layer140U's height H140U, and STI region138's height H138can be greater than fin structure108's height H108).

Referring toFIG.26, operation220can further include forming (i) depositing a gate dielectric material over the structure of24, (ii) depositing a gate electrode material over the gate dielectric material, and (iii) etching back, via a CMP process and an etching process, the deposited gate dielectric material and the gate electrode material to form gate structure110with height H110. As shown inFIG.25, after forming gate structure110, isolation structure140-Left's top surface can be vertically (e.g., in the z-direction) lower than gate structure110(e.g., first dielectric layer140L's height H140Lcan be less than gate structure110's height H110). Further, after forming gate structure110, isolation structure140-Right's top surface can be vertically (e.g., in the z-direction) higher than gate structure110(e.g., the sum of first dielectric layer140L's height H140L, second dielectric layer140U's height H140Ucan be greater than gate structure110's height H110). In some embodiments, the previously discussed operations ofFIGS.24-26can be performed on the structure ofFIG.23to result in the structure ofFIG.27. In some embodiments, as shown inFIG.27, isolation structure140-Right's capping layer404can be formed through gate structure110.

The present disclosures provides an exemplary isolation structure and a method for forming the same. The isolation structure can be disposed between two laterally adjacent fin structures and to isolate metal lines on the two laterally adjacent fin structures. The method for forming the isolation structure can include depositing a first layer of dielectric material between the two adjacent fin structures. The method for forming the isolation structure can further include performing a spin-coating process to coat a flowable oxide material over the first layer of dielectric material. The flowable oxide material can include a flowable metal oxide material, a flowable silicon oxide material, a carbon-silicon monomer material, or a carbon-silicon-metal monomer material. The process of spin-coating can further include annealing the coated flowable oxide material to form a second layer of dielectric material that contains silicon-metal-oxide. By, incorporating silicon into the second layer of dielectric material, the second layer of dielectric material's dielectric constant to be reduced, thus reducing the parasitic capacitance coupling between the two laterally adjacent fin structures. Further, since the process of spin-coating can fill in the space between two laterally adjacent fin structure, the second layer of dielectric material can be a seamless layer free from voids (e.g., the second layer of dielectric material does not have voids). A benefit of the seamless second layer of dielectric material of the isolation structure, among others, is to provide a sufficient isolation and a reduced parasitic capacitance between the adjacent fin structures, thus improving the yield and performance of the ICs.

In some embodiments, a semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

In some embodiments, a method can include forming a fin structure over a substrate, forming a first layer of dielectric material adjacent to the fin structure, forming a second layer of dielectric material with a first thickness over the fin structure and a second thickness over the first layer of dielectric material, and replacing the second layer of dielectric material with a third layer of dielectric material. The first layer of dielectric material can include a void.

In some embodiments, a method can include forming first and second fin structures over a substrate, forming a first layer of dielectric material between the first and second fin structures, forming a second layer of dielectric material with a first thickness over the first and second fin structures and a second thickness greater than the first thickness over the first layer of dielectric material, and replacing the second layer of dielectric material with a third layer of dielectric material. The first layer of dielectric material can include a void. The second layer of dielectric material can be seamless.