Semiconductor device

Provided is a semiconductor device having as many input/output pads as possible using a chip having a small number of input/output pads. The semiconductor device includes a substrate including first and second extending input/output pads, a first memory structure disposed on the substrate and including first connecting input/output pads, a second memory structure disposed on the first memory structure and including second connecting input/output pads, and a wiring structure formed on lateral surfaces of the first and second memory structures and connecting the first and second connecting input/output pads and the first and second extending input/output pads, respectively; wherein the wiring structure includes a first wiring connecting the first connecting input/output pads and the first extending input/output pad and a second wiring connecting the first connecting input/output pads and the second extending input/output pad, and the second wiring is offset relative to the first wiring.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2014-0068419 filed on Jun. 5, 2014 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which in its entirety are herein incorporated by reference.

BACKGROUND

1. Technical Field

The present inventive concepts relates to a semiconductor device.

2. Description of the Related Art

In semiconductor devices, bandwidth is typically used in measuring performance of a memory. The bandwidth is proportional to a frequency, which may correspond to a speed of the memory, and is also proportional to the number of input/output pads of the memory. Many studies are related with development of methods for increasing the frequency, but there is a limit in increasing the frequency. Therefore, to enhance the memory performance, increasing the number of input/output pads, rather than increasing the frequency, is taken into consideration.

A wide input/output (I/O) device is a type of memory device having a plurality of input/output pads.

SUMMARY

According to an aspect of the present inventive concepts, there is provided a semiconductor device including a substrate including first and second extending input/output pads, a first memory structure disposed on the substrate and including first connecting input/output pads, a second memory structure disposed on the first memory structure and including second connecting input/output pads, and a wiring structure formed on lateral surfaces of the first and second memory structures and connecting the first and second connecting input/output pads and the first and second extending input/output pads respectively, wherein the wiring structure includes a first wiring connecting the first connecting input/output pads and the first extending input/output pad and a second wiring connecting the first connecting input/output pads and the second extending input/output pad, and the second wiring is offset relative to the first wiring.

The first memory structure includes a plurality of memory chips.

The plurality of memory chips include a first memory chip and a second memory chip disposed on the first memory chip, the first connecting input/output pads include a first input/output pad included in the first memory chip and a second input/output pad included in the second memory chip, and the second memory chip includes a through via passing through the second memory chip and connecting the first and second input/output pads.

The plurality of memory chips include a first memory chip and a second memory chip disposed on the first memory chip, the first connecting input/output pads include a first input/output pad included in the first memory chip and a second input/output pad included in the second memory chip, and the first wiring connects the first extending input/output pad and the first and second input/output pads.

The semiconductor device may further comprising a third memory structure disposed on the first memory structure and including a third connecting input/output pad, wherein the extending input/output pads include a third extending input/output pad, the wiring structure further includes a third wiring connecting the third connecting input/output pad and the third extending input/output pad, and the third wiring is offset relative to the first and second wirings along edges of the first to third memory structures.

The substrate further includes an extending power pad connected to a power supply and an extending ground pad that is grounded, the first memory structure further includes a power pad and a ground pad, the wiring structure further includes a power wiring connecting the power pad and the extending power pad and a ground wiring connecting the ground pad and the extending ground pad, and the power wiring or the ground wiring are disposed between the first and second wirings.

The first input/output pad is positioned at an edge of the first memory structure and the first memory structure is electrically connected to the first input/output pad and further includes a center pad centrally positioned in the first memory structure.

The semiconductor device may further comprising an interposer positioned between the substrate and the first memory structure, wherein the interposer includes first and second interposer pads to which the first and second wirings are connected, respectively, and first and second extending interposer pads to which the first and second extending input/output pads are connected, respectively, the first and second interposer pads are arranged at a first distance, the first and second extending interposer pads are arranged at a second distance, and the second distance is greater than or equal to the first distance.

The wiring structure includes a plurality of protrusion parts coupled to the first and second memory structures, and the protrusion parts are brought into contact with the first and second connecting input/output pads, respectively.

The wiring structure includes a bonding wire.

According to another aspect of the present inventive concepts, there is provided a semiconductor device including a substrate including first and second extending input/output pads, a first memory structure disposed on the substrate and including a first input/output pad, a second memory structure disposed on the first memory structure and including a second input/output pad connected to the first input/output pad, a third memory chip disposed on the second memory chip and including a third input/output pad, a fourth memory chip disposed on the third memory chip and including a fourth input/output pad connected to the third input/output pad, a first connection part formed on lateral surfaces of the first and second chips and electrically connecting the first and second input/output pads and the first extending input/output pad, and a second connection part formed on lateral surfaces of the first to fourth chips and electrically connecting the third and fourth input/output pads and the second extending input/output pad, wherein the first to fourth memory chips are disposed to overlap with the first to fourth input/output pads, and the second extending input/output pad is positioned farther from the third and fourth input/output pads than the first extending input/output pad.

The second memory chip further includes a through via connecting the first and second input/output pads to each other.

Each of the first to fourth memory chips includes a dynamic random access memory (DRAM).

The semiconductor device may further comprising a connection unit including first and second connection parts, wherein the connection unit includes protrusion parts inserted into at least a portion in a space between the first to fourth memory chips.

The first connection part includes a bonding wire.

DETAILED DESCRIPTION OF THE EMBODIMENTS

It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

First, a semiconductor device according to a first embodiment of the present inventive concepts will be described with reference toFIGS. 1 to 3.

FIG. 1is a conceptual perspective view for explaining a configuration of a semiconductor device according to an embodiment of the present inventive concepts,FIG. 2is a conceptual front view for explaining a semiconductor device according to an embodiment of the present inventive concepts andFIG. 3is a partially cut-away side view for explaining a semiconductor device according to an embodiment of the present inventive concepts.

Referring toFIG. 1, the semiconductor device1includes a substrate200, a stack structure100and a wiring structure300.

The substrate200may be formed of a silicon (Si) substrate, a silicon on insulator (SOI) substrate, a gallium arsenic (GaAs) substrate, a ceramic substrate, a quartz substrate, a rigid substrate such as a glass substrate for display, or a flexible plastic substrate made of polyimide, polyester, polycarbonate, polyethersulfone, polymethylmethacrylate, polyethylene naphthalate, or polyethyleneterephthalate.

The substrate200may include extending input/output pads210and220on its top surface. The extending input/output pads210and220may be plurally provided. The extending input/output pads210and220may be separated from each other. The extending input/output pads210and220may be formed of conductors. The extending input/output pads210and220may be connected to wirings to serve as nodes that facilitate an electrical connection with another part.

The extending input/output pads210and220may be arranged in one direction from a lateral surface of the stack structure100. The respective extending input/output pads210and220may be disposed to be spaced a first distance w1 apart from other extending input/output pads210and220adjacent thereto. The extending input/output pads210and220may include a first extending input/output pad210aand a second extending input/output pad210b.

The stack structure100may be configured such that a plurality of memory chips100a, . . . , and100rare stacked. The number of the plurality of memory chips100a, . . . , and100ris not particularly limited. The stack structure100may be configured such that the plurality of memory chips100a, . . . , and100rare aligned and stacked. In an embodiment, the plurality of memory chips100a, . . . , and100rmay be all of the same type. The memory chips100a, . . . , and100rmay be, for example, DRAMs, but not limited thereto.

The input/output pad110may plurally exist on one of the memory chips100a, . . . , and100r. In an embodiment, the number of input/output pad110plurally existing on one of the memory chips100a, . . . , and100rmay be smaller than the number of the extending input/output pads210and220. Each of the input/output pads110may be spaced a second distance w2 apart from other input/output pads110adjacent thereto. The second space w2 may be greater than the first space w1.

The second space w2 may be equal to or greater than a multiplication product of the first space w1 and the number of memory structures100-0, . . . , and100-8. Accordingly, the second space w2 may be predefined according to the configuration of the stack structure100. Therefore, the second space w2 can be adjusted according to the number of memory structures100-0, . . . , and100-8of the stack structure100. In an embodiment, the second space w2 may be adjusted according to the first space w1. Here, in a case where the second space w2 is first taken into consideration, the first space w1 may also be adjusted.

Referring toFIG. 3, the first memory structure100-0may be disposed on the substrate200. The second memory structure100-1may be stacked on the first memory structure100-0. The other memory structures100-2, . . . , and100-8may be stacked on the second memory structure100-1.

The first memory structure100-0includes first connecting input/output pads116qand116rand the second memory structure100-1includes first connecting input/output pads116oand116p. The first connecting input/output pads116qand116rare pads for inputting/outputting signals from/to the first memory structure100-0and the first connecting input/output pads116oand116pre pads for inputting/outputting signals from/to the second memory structure100-1.

The first memory structure100-0may include a first memory chip100rand a second memory chip100q. The first memory chip100rmay be disposed on the substrate200and the second memory chip100qmay be disposed on the first memory chip100r. The first memory chip100rmay include a first input/output pad116rand the second memory chip100qmay include a second input/output pad116q. The first memory chip100rand the second memory chip100qmay be stacked such that the first input/output pad116rand the second input/output pad116qoverlap with each other.

The first input/output pad116rmay be connected to the second input/output pad116q. The second memory chip100qmay include a first through via120qconnecting the first input/output pad116rand the second input/output pad116q. The first through via120qmay be formed while passing through the second memory chip100q. The first through via120qmay be a through silicon via (TSV), but not limited thereto.

The second memory structure100-1may include a third memory chip100pand a fourth memory chip100o. The third memory chip100pmay be disposed on the second memory chip100qand the fourth memory chip100omay be disposed on the third memory chip100p. The third memory chip100pmay include a third input/output pad116pand the fourth memory chip100omay include a fourth input/output pad116o. The third memory chip100pand the fourth memory chip100omay be stacked such that the third input/output pad116pand the fourth input/output pad116ooverlap with each other.

The third input/output pad116pmay be connected to the fourth input/output pad116o. The fourth memory chip100omay include a second through via120oconnecting the third input/output pad116pand the fourth input/output pad116o. The second through via120omay be formed while passing through the second memory chip100q. The second through via120omay be a through silicon via (TSV), but not limited thereto.

Referring again toFIGS. 1 and 3, the wiring structure300may be formed at a position where the lateral surface of the stack structure100is covered. In an embodiment, the wiring structure300may be positioned between the extending input/output pads210and220and the stack structure100.

In an embodiment, the first connecting input/output pads116qand116rof the first memory structure100-0and the first connecting input/output pads116oand116pof the second memory structure100-1may have the same horizontal position at different vertical levels, which is because the first memory structure100-0and the second memory structure100-1are aligned to then be stacked. In an embodiment, horizontal position of the first extending input/output pad210amay overlap with or may be relatively close to the first connecting input/output pads116qand116rand the first connecting input/output pads116oand116prather than a horizontal position of the second extending input/output pad210b. The horizontal position of the second extending input/output pad210bmay be farther from horizontal positions of the first connecting input/output pads116qand116rand the second input/output pad116qthan horizontal position of the first extending input/output pad210a. Therefore, the first wiring310rmay be formed without a bent portion or may be curved to a relatively small extent. The second wiring310pmay be curved to a greater extent than the first wiring310r. Therefore, the second wiring310pmay be offset relative to the first wiring310rdue to the bent portion. The bent portions of the first wiring310rand the second wiring310pmay be perpendicularly curved or may be diagonally curved at an obtuse angle. That is to say, shapes of the bent portions of the first wiring310rand the second wiring310pmay be bent without limitation if only they are offset from each other.

Referring toFIG. 3, the first wiring310rmay be electrically connected to the first connecting input/output pads116qand116r. The first wiring310rmay be connected to the first input/output pad116r, but aspects of the present inventive concepts are not limited thereto. The first wiring310rmay be connected to the second input/output pad116q. That is to say, since the first input/output pad116rare connected to the second input/output pad116q, there is no limitation in the connection relationship between the first wiring310rand the second input/output pad116qas long as the first wiring310ris electrically connected to the first input/output pad116rand the second input/output pad116q. In an embodiment, the first wiring310rmay also be connected to both of the first input/output pad116rand the second input/output pad116q.

In the illustrated embodiment, two memory structures are exemplified. However, the number of memory structures may be increased without limitation, as shown. Therefore, according to the present embodiment, a plurality of memory structures may be provided, or one of the plurality of memory structures may include two or more memory chips.

In the semiconductor device, a small number of input/output pads may be provided in one memory chip. However, the respective input/output pads may be branched through a plurality of stack structures to then connect the branched input/output pads to the extending input/output pads, thereby achieving the same effect as in a case where many input/output pads are provided. Therefore, since the number of input/output pads can be increased using chips fabricated at low cost, like in a wide I/O device, the semiconductor device1may have a relatively high bandwidth, compared to a memory device having the same capacity.

In addition, since a memory structure includes a plurality of memory chips, the number of the plurality of memory chips can be adjusted according to numbers of input/output terminals and extending input/output terminals. Therefore, the capacity and the number of extending input/output terminals are reciprocally adjusted, thereby increasing the degree of freedom of choice. That is to say, the semiconductor device having a desired capacity and including a desired number of input/output terminals can be easily fabricated.

A semiconductor device according to an embodiment of the present inventive concepts will be described with reference toFIG. 4.

FIG. 4is a partially cut-away side view for explaining a semiconductor device according to an embodiment of the present inventive concepts.

Referring toFIG. 4, in the semiconductor device2according to an embodiment of the present inventive concepts, a first wiring310rand a second wiring310pare bonding wires.

One end of the first wiring310rmay be bonded to first connecting input/output pads116qand116r. The one end of the first wiring310rmay be bonded to the first input/output pad116ror the second input/output pad116q. Since the first input/output pad116rand the second input/output pad116qare electrically connected, the first wiring310rmay be connected to either the first input/output pad116ror the second input/output pad116q. The first wiring310rmay be a wire formed of a conductor. The first wiring310rmay be, for example, a metal wire. The other end of the first wiring310rmay be bonded to a first extending input/output pad210a.

One end of the second wiring310pmay be bonded to the first connecting input/output pads116oand116p. The one end of the second wiring310pmay be bonded to a third input/output pad116por a fourth input/output pad116o. Since the third input/output pad116pand the fourth input/output pad116oare electrically connected, the second wiring310pmay be connected to either the third input/output pad116por the fourth input/output pad116o. The second wiring310pmay be a wire formed of a conductor. The second wiring310pmay be, for example, a metal wire. The other end of the second wiring310pmay be bonded to the second extending input/output pad210b.

Since the second extending input/output pad210bis positioned farther from horizontal positions of the first to fourth input/output pads than the first extending input/output pad210a, the second wiring310pmay be offset relative to the first wiring310r.

A semiconductor device according to an embodiment of the present inventive concepts will be described with reference toFIG. 5. In an embodiment described with reference toFIG. 5, first and second through vias are not provided and a bonding wire of a wiring structure is connected to all of the first to fourth input/output pads.

FIG. 5is a partially cut-away side view for explaining a semiconductor device according to an embodiment of the present inventive concepts.

Referring toFIG. 5, in the semiconductor device3, a first wiring310rmay connect a first extending input/output pad210ato first connecting input/output pads116qand116r. Here, the first wiring310rmay be connected to the first input/output pad116rand may also be connected to the second input/output pad116qas well. That is to say, the first wiring310rmay have multiple branches or may include initially separated multiple bonding wires.

In the semiconductor device3, a second wiring310pmay connect a second extending input/output pad210bto first connecting input/output pads116oand116p. Here, the second wiring310pmay be connected to a third input/output pad116pand may also be connected to a fourth input/output pad116oas well. That is to say, the second wiring310pmay have multiple branches or may include initially separated multiple bonding wires.

Since the second extending input/output pad210bis positioned farther from horizontal positions of first to fourth input/output pads than the first extending input/output pad210a, the second wiring310pmay be offset relative to the first wiring310r.

In the semiconductor device3, it is not necessary to provide a through via between chips. That is to say, a structure for connecting first memory chip100rand a second memory chip100qin a first memory structure100-0and a structure for connecting a third memory chip100pand a fourth memory chip100oin a second memory structure100-1may be provided. Therefore, a wiring process for piercing a via passing through a chip and filling the via with a conductor is simply repeated, thereby increasing the efficiency of the fabrication process while reducing the fabrication cost.

A semiconductor device according to an embodiment of the present inventive concepts will be described with reference toFIGS. 6 to 8. In an embodiment described with reference toFIGS. 6 to 8, a wiring structure is a bonding wire.

FIG. 6is a conceptual perspective view for explaining a configuration of a semiconductor device according to an embodiment of the present inventive concepts,FIG. 7is a conceptual front view for explaining a semiconductor device according to an embodiment of the present inventive concepts, andFIG. 8is an enlarged view for specifically explaining a center pad of a semiconductor device according to an embodiment of the present inventive concepts.

Referring toFIG. 6, in the semiconductor device4, input/output pads110may be positioned at edges of memory chips100a, . . . , and100r. In such a case, the input/output pads110are easily connected to a wiring structure300formed on lateral surfaces of the input/output pads110, thereby increasing the efficiency while reducing the cost during a wiring process.

FIG. 7is a plan view taken in a direction ‘A’ ofFIG. 6.

Referring toFIG. 7, in the semiconductor device4, each of the memory chips100a, . . . , and100rmay include a center pad150.

The center pad150may include input/output pads, a power pad and a ground pad of each of the memory chips100a, . . . , and100r. That is to say, the memory chips100a, . . . , and100rcan be fabricated with high process efficiency by allowing various kinds of pads to concentrate on a narrow region at the time of fabricating the memory chips100a, . . . , and100r. A center address pad140for applying addresses of the memory chips100a, . . . , and100rmay also be provided around the center pad150.

FIG. 8is an enlarged view illustrating the center pad shown inFIG. 7.

Referring toFIG. 8, the center pad150may include center input/output pads122,124,126, and128, a center power pad152′ and a center ground pad154′. The center input/output pads122,124,126, and128are separated from each other, while the center power pad152′ and the center ground pad154′ are connected to each other.

Referring back toFIG. 7, the center pad150is directly connected to an internal memory device. However, as described above, since pads are positioned at an edge of the stack structure100, the pads are redistributed. That is to say, as shown inFIG. 7, the center pad150may be connected to the input/output pads110, the power pad and the ground pad positioned at the edges of the memory chips100a, . . . , and100r. The connection mechanism may include input/output redistribution lines152,154,156and158, a power redistribution line152′ and a ground redistribution line154′. The center address pad140may be redistributed in an edge address pad130by address redistribution lines.

In the semiconductor device4, the center pad150is redistributed to the edges of the memory chips100a, . . . , and100r, thereby increasing the efficiency of the semiconductor device4while reducing the fabrication cost of a wiring structure300on lateral surfaces of the stack structure100.

In an embodiment disclosed with reference toFIG. 9, first and second wirings are curved without bent portions.

FIG. 9is a conceptual front view for explaining a semiconductor device according to an embodiment of the present inventive concepts.

Referring toFIG. 9, in the semiconductor device5, the first wiring310rand the second wiring310pmay be curved. The first wiring310rand the second wiring310pmay be conductors formed within a wiring structure300.

In the semiconductor device5, since the first wiring310rand the second wiring310pare formed without bent portions, they may have lower resistance than a wiring with a bent portion and the first wiring310rand the second wiring310pcan maintain constant resistance without a resistance difference between wirings along the wiring extending direction. In addition, since a constant distance between wirings can be easily maintained, a risk of occurrence of short-circuit in each wiring can be reduced.

InFIG. 9, the memory structures100-0, . . . , and100-8each in pair corresponding to each of the memory chips100a, . . . , and100rare illustrated, but aspects of the present inventive concepts are not limited thereto.

In an embodiment described with reference toFIG. 10, the semiconductor device further includes a power wiring and a ground wiring.

FIG. 10is a conceptual front view for explaining a semiconductor device according to an embodiment of the present inventive concepts.

Referring toFIG. 10, a substrate200includes an extending power ground pad212. The extending power ground pad212may be an extending power pad connected to a power supply or a grounded extending ground pad.

Each of memory chips100a, . . . , and100rincludes power ground pads116a′, . . . , and116r′. The power ground pads116a′, . . . , and116r′ may be power pads connected to the extending power pad or ground pads connected to the extending ground pad.

A wiring structure300includes a power ground wiring310′ connecting the extending power ground pads212and the power ground pads116a′, . . . , and116r′. The power ground wiring310′ may be a power wiring connecting the power pads and the extending power pads or a ground wiring connecting the ground pads and the extending ground pads.

The power ground wiring310′ may be disposed between wirings connecting the input/output pads110, including a first wiring310rand a second wiring310p, and the extending input/output pads210and220. The power ground wiring310′ may be gradually offset in the same manner with the first wiring310rand the second wiring310p. That is to say, a power ground wiring116q′ of the second memory chip100qmay be offset relative to a power ground wiring116r′ of the first memory chip100r.

InFIG. 10, the memory structures100-0, . . . , and100-8each corresponding to one of the memory chips100a, . . . , and100rare illustrated, but aspects of the present inventive concepts are not limited thereto.

A semiconductor device according to an embodiment of the present inventive concepts will be described with reference toFIG. 11. In an embodiment described with reference toFIG. 11, the semiconductor device further includes an interposer.

FIG. 11is a conceptual perspective view for explaining a configuration of a semiconductor device according to an embodiment of the present inventive concepts.

Referring toFIG. 11, the semiconductor device7further includes an interposer400.

The interposer400may be an intermediate structure for establishing electrical connections between a substrate200and the memory chips100a, . . . , and100r. The interposer400may include, but not limited to, silicon.

The interposer400may be formed on the substrate200. The interposer400may be disposed under a stack structure100. That is to say, the interposer400may be positioned between the substrate200and the stack structure100.

The interposer400may include interposer pads410and an extending interposer pads420. In detail, the interposer pads410may be formed on a top surface of the interposer400. The interposer pads410may correspond to wirings310and320of a wiring structure300in a one-to-one relationship. That is to say, first ends of the wrings310and320may be connected to input/output pads110of each of memory chips100a, . . . , and100rand second ends of the wrings310and320may be connected to the interposer pads410. Here, the wrings310and320may be connected to the respective interposer pads410. The interposer pads410may be spaced a third distance w3 apart from other interposer pads410that are closest thereto.

The extending interposer pads420may correspond to the interposer pads410in a one-to-one relationship. The extending interposer pads420may be formed on the top surface of the interposer400, like the interposer pads410. The extending interposer pad420may be spaced a fourth distance w4 apart from other interposer pads410that are closest thereto. The fourth distance w4 may be greater than the third distance w3. That is to say, the extending interposer pads420may be arranged in a greater interval than the interposer pads410.

The extending interposer pads420may correspond to the extending input/output pads210and220in a one-to-one relationship. That is to say, the plurality of extending interposer pads420may be connected to different extending input/output pads210and220among the plurality of extending input/output pads210and220, respectively.

In the present inventive concepts, memory chips100a, . . . , and100rmay be positioned only at edges of the input/output pads110, or centrally positioned memory chips100a, . . . , and100rmay be redistributed to the edges of the input/output pads110, but aspects of the present inventive concepts are not limited thereto.

The semiconductor device7, further including the interposer400, may increase a distance between the wrings310and320. If the distance between the wrings310and320is too small, interference between the wrings310and320may occur, deteriorating the reliability of the semiconductor device7. Therefore, like the semiconductor device7, the distance between the wrings310and320is increased by employing the interposer400, thereby reducing a probability of interference occurring between the wirings310and320and ultimately increasing the reliability of the semiconductor device.

A semiconductor device according to an embodiment of the present inventive concepts will be described with reference toFIGS. 12 and 13. In an embodiment described with reference toFIGS. 12 and 13, a wiring structure exists within a stack structure and the stack structure is offset to be stacked.

FIG. 12is a conceptual perspective view for explaining a configuration of a semiconductor device according to an embodiment of the present inventive concepts andFIG. 13is a front view for explaining a semiconductor device according to an embodiment of the present inventive concepts.

Referring toFIGS. 12 and 13, in the semiconductor device8, a substrate200includes extending input/output pads210and220and extending power ground pads212positioned under a stack structure100. That is to say, the stack structure100may cover the extending input/output pads210and220and the extending power ground pad212.

The respective memory chips100a, . . . , and100hmay be horizontally offset relative to the directly underlying memory chips100b, . . . , and100ito then be stacked one on another. An offsetting distance may be the sixth distance w6. As the result of the offsetting, each of the memory chips100a, . . . , and100imay be shifted only one space at a time to then be aligned such that the input/output pads116a,116a-1, . . . , and116a-8overlap with the dummy input/output pads116bto116i,116b-1to116i-1, . . . , and116b-8to116i-8. Therefore, a distance between the bottommost memory chip100iand the topmost memory chip100amay be the fifth distance w5. The fifth distance w5 may be equal to a multiplication product of the sixth distance w6 and the number of memory chips100a, . . . , and100i. In a case where the memory structures100-0, . . . , and100-8include a plurality of memory chips100a, . . . , and100i, instead of one of the memory chips100a, . . . , and100i, the number of memory structures100-0, . . . , and100-8is multiplied with the sixth distance w6 to yield the fifth distance w5.

The respective memory chips100a, . . . , and100imay be horizontally offset relative to the directly underlying memory chips100a, . . . , and100ito then be stacked one on another. An offsetting distance may be the sixth distance w6. As the result of the offsetting, each of the memory chips100a, . . . , and100imay be shifted only one space at a time to then be aligned such that the power ground pads116a′,116a-1′, . . . , and116a-8′ overlap with the dummy power ground pads116b′ to116i′,116b-1′ to116i-1′, . . . , and116b-8′ to116i-8′.

The input/output pads116a,116a-1, . . . , and116a-8and the power ground pads116a′,116a-1′, . . . , and116a-8′ may be spaced a seventh distance w7 apart from on the memory chip100a, . . . ,100i. In addition, the power ground pads116a′,116a-1′, . . . , and116a-8′ may be spaced the seventh distance w7 apart from the dummy input/output pads116b, . . . , and116b-8, respectively. The seventh distance w7 may be half the fifth distance w6, but aspects of the present inventive concepts are not limited thereto, so long as a sum of a distance between each of the input/output pads116a,116a-1, . . . , and116a-8and each of the power ground pads116a′,116a-1′, . . . , and116a-8′ and a distance between each of the power ground pads116a′,116a-1′, . . . , and116a-8′ and each of the dummy input/output pads116b, . . . , and116b-8is equal to the sixth distance w6.

Through vias formed while passing through the chips may be through silicon vias (TSVs), but not limited thereto.

In the semiconductor device8, the input/output pad and the extending input/output pad are connected with the shortest distance, thereby considerably improving the wiring efficiency. In addition, since power and ground lines are disposed between each of input/output lines, a probability of occurrence of interference and short-circuit between the input/output lines may be greatly reduced. Therefore, many extending input/output pads can be provided with a small number of input/output pads. In addition, since signals are transmitted over the shortest distance, power efficiency can be improved and a risk of signal loss can also be reduced.

InFIGS. 12 and 13, the memory structures100-0, . . . , and100-8each corresponding to one of the memory chips100a, . . . , and100iare illustrated, but aspects of the present inventive concepts are not limited thereto. That is to say, the memory structures100-0, . . . , and100-8may include a plurality of memory chips100a, . . . , and100i. In this case, the memory chips100a, . . . , and100iincluded in the same memory structure100-0, . . . ,100-8may be stacked without being offset and may be vertically connected to each other without being shifted.

A semiconductor device9according to an embodiment of the present inventive concepts will be described with reference toFIG. 14. In an embodiment described with reference toFIG. 14, through vias are diagonally formed and a stack structure is not offset.

FIG. 14is a conceptual front view for explaining a configuration of a semiconductor device according to an embodiment of the present inventive concepts.

In the semiconductor device9an embodiment of the present inventive concepts, it is not necessary to provide an offset in stacking the memory chips, thereby increasing processing efficiency. In addition, since the stack structure100occupies a reduced volumetric area, the integration level of the semiconductor device9can be improved.

InFIG. 14, the memory structures100-0, . . . , and100-8each corresponding to one of the memory chips100a, . . . , and100iare illustrated, but aspects of the present inventive concepts are not limited thereto. That is to say, the memory structures100-0, . . . , and100-8may include a plurality of memory chips100a, . . . , and100i. In this case, the memory chips100a, . . . , and100iincluded in the same memory structure100-0, . . . ,100-8may include vertical through vias without diagonal through vias. That is to say, diagonal through vias are provided between each of the memory structures100-0, . . . , and100-8and vertical through vias may be provided within the same memory structure100-0, . . . ,100-8.

FIG. 15is a block diagram illustrating an example electronic system including semiconductor devices according to some embodiments of the present inventive concepts.

Referring toFIG. 15, the electronic system2900may include a controller2910, an input/output device (I/O)2920, a memory2929, an interface2940and a bus2950. The controller2910, the I/O2920, the memory2929, and/or the interface2940may be connected to one another through the bus2950. The bus2950may correspond to a path through which data moves. The controller2910may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements capable of functions similar to those of these elements. The I/O2920may include a keypad, a keyboard and a display. The memory2929may store data and/or commands. The memory2929may include semiconductor devices according to some embodiments of the present inventive concepts. The memory2929may include a DRAM. The interface2940may perform functions of transmitting data to a communication network or receiving data from a communication network. The interface2940may be wired or wireless. For example, the interface2940may include an antenna or a wired/wireless transceiver, and so on.

The electronic system2900may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or any type of electronic device capable of transmitting and/or receiving information in a wireless environment.

FIG. 16is a block diagram illustrating an example memory card employing a memory including semiconductor devices according to some embodiments of the present inventive concepts.

Referring toFIG. 16, a memory3010including semiconductor devices may be employed to a memory card3000. The memory card3000may include a memory controller3020controlling data exchange between a host3030and the memory3010. A static random access memory (SRAM)3021may be used as a working memory of a central processing unit (CPU)3022. A host interface3023may include a protocol for exchanging data by allowing the host3030to access the memory card3000. An error correction code3024may be used to detect errors of the data read from the memory3010. A memory interface3025may interface with the memory3010. The CPU3022may perform the overall control operation associated with the data exchange of the memory controller3020.

FIGS. 17 and 18illustrate an example semiconductor system to which semiconductor devices according to some embodiments of the present inventive concepts can be employed.

FIG. 17illustrates an example in which a semiconductor device according to an embodiment of the present inventive concepts is applied to a tablet PC, andFIG. 18illustrates an example in which a semiconductor device according to an embodiment of the present inventive concepts is applied to a notebook computer. It is obvious to one skilled in the art that the semiconductor devices according to some embodiments of the present inventive concepts may also be applied to other IC devices not illustrated herein.