Data coincidence detecting circuit

A data coincidence detecting circuit including a register for receiving n-bit data, a counter for counting up until 2.sup.n to compare the n-bit data with it, a comparator for comparing the outputs of the register and the outputs of the counter, respectively to generate a coincidence detecting signal, a mask portion connected to the output of the comparator for masking the period from a time point when the n-bit data is input to a time point when the input of data ends, and a logic circuit for logically adding the output of the mask portion and the output of the comparator to output the result.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a data coincidence detecting circuit, and 
more particularly to a data coincidence detecting circuit composed of a 
MOS device. 
2. Description of the Related Art 
A data coincidence detecting circuit detects the coincidence of data 
provided by a clock with data written in a register. In a conventional 
data coincidence detecting circuit, when n-bits of data are written into a 
register regardless of the order of data, the coincidence detection may 
occur while the data is being written. In other words, the test for data 
coincidence can be performed before all of the bits of data are written 
into the register to be compared. 
BACKGROUND OF THE INVENTION 
FIG. 1 (Prior Art) is a schematic diagram illustrating a conventional data 
coincidence detection circuit. The conventional data coincidence detecting 
circuit comprises a register 10, a counter 20 and a comparator 30. 
The register 10 has four latches 11, 12, 13 and 14. One latch corresponds 
to one bit of data (e.g. the LSB of data is loaded into latch 11 and the 
MSB of data is loaded into latch 14). 
The comparator 30 has four one-bit "exclusive or" (XOR) logic gates 31, 32, 
33 and 34. Each XOR logic gate corresponds to a particular latch (e.g. the 
MSB latch 11 corresponds to XOR gate 31 and the LSB latch 14 corresponds 
to the XOR gate 34). 
The counter 20 has four T flip flops 21, 22, 23 and 24. Each flip flop 
corresponds to one latch and one XOR gate (e.g. the MSB T flip flop 21 
corresponds to the LSB latch 11 and XOR gate 31 and the MSB T flip flop 24 
corresponds to the LSB latch 14 and XOR gate 34). 
The register 10 stores 4 bits of data. The counter 20 generates four bits 
of data to be compared to the data stored in the register 10. The four 
bits of data generated by the counter 20 is a four bit number. The number 
increases sequentially over time. The comparator compares the data 
supplied by the register 10 and the counter 20 and generates a coincidence 
signal when the data is the same. 
The four latches 11, 12, 13 and 14 within the register 10 latch write 
signals D1, D2, D3 and D4 in response to respective enable signals EN1, 
EN2, EN3 and EN4. 
The four T flip flops 21, 22, 23 and 24 within the counter 20 are reset in 
response to a reset signal R. A clock signal CK synchronizes the four T 
flip flops. The T flip flops 21, 22, 23 and 24 output signals Q1, Q2, Q3 
and Q4 respectively. 
The four XOR gates 31, 32, 33 and 34 within the comparator 30 compare the 
respective outputs of register 10 with the outputs Q1, Q2, Q3 and Q4 of 
counter 20. All of the outputs of each XOR gates are logically NORED in a 
NOR gate 35. A coincidence detection signal is generated by the NOR gate 
35 when all of the outputs of the four XOR gates are logic level low "0". 
FIG. 1B is a timing diagram illustrating the operation of the conventional 
data coincidence detecting circuit shown in FIG. 1A. The T flip flops 21, 
22, 23 and 24 in the counter 20 are reset when a logic level low "0" reset 
signal R is applied to the T flip flops. Thereafter when the reset signal 
goes to logic level high "1", the flip flops count up from "0000" to 
"1111" in response to a clock signal CK. Data sets of 4 bits are loaded 
into the 4-bit register 10 sequentially having a time delay .tau..sub.4 
minus .tau..sub.3 between the loading of separate bits. Enable signal EN1 
enables latch 11, thereby latching the first bit of data. Enable signal 
EN2 subsequently enables the latching of the second bit of data, etc. For 
example, the loading of data "0010" into register 10 starts at time 
.tau..sub.1, and continues until time .tau..sub.5. The time which elapses 
between time .tau..sub.1 and .tau..sub.5 is referred to as the data load 
period. At time .tau..sub. 2, the output data of register 10 is "0010" and 
the output of counter 20 is "0010". Therefore, the output of comparator 30 
goes to logic level high "1" indicating data coincidence. An error in the 
output data occurs between the times of .tau..sub.3 and .tau..sub.4 
because of the changing state of data bits D2 and D3 when loaded. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a data coincidence 
circuit which masks the n-bit data writing periods from beginning to end, 
thereby performing coincidence detection after all of the desired data has 
been written into storage registers (i.e. all n-bits of the data have been 
written into the register to be compared).

DETAILED DESCRIPTION OF THE INVENTION 
FIG. 2 is a schematic diagram showing the preferred embodiment of the data 
coincidence detecting circuit of the present invention. The data 
coincidence detecting circuit has a register 10, a counter 20, a 
comparator 30, a mask portion 40 and a logic circuit 50. The register 10, 
counter 20 and comparator 30 perform the same tasks and are organized in 
the same manner as described with reference to FIG. 1A. The mask portion 
40 and the logic circuit 50 mask the data load period. 
The mask portion 40 has two NOR gates 41 and 42. The output of each NOR 
gate is input to the other NOR gate (i.e. the output of NOR gate 41 is 
input to NOR gate 42 and the output of NOR gate 42 is input to NOR gate 
41). NOR gate 42 receives enable signal EN4 as a second input. Enable 
signal EN1 is a second input into NOR gate 41. Finally, the output of NOR 
gate 41 is supplied to the logic circuit 50. 
The logic circuit 50 has a NAND gate 51 receiving an input from the NOR 
gate 41 and the NOR gate 35 in the comparator 30. An inventer 52 receives 
the output of NAND gate 51 and generates the output signal OUTPUT of the 
data coincidence detecting circuit. 
FIG. 3A is a schematic diagram showing exemplary latch circuits used in the 
register 10. Input Di (i=1-4) flows through a CMOS transmission gate 60, 
and inverters 61 and 62 (respective to signal flow) to output OUTP. A 
feedback loop takes the signal output by the inverter 61 and feeds it back 
to the inverter's 61 input. The feedback loop has an inverter 63 and a 
CMOS transmission gate 64 (respective to signal flow). The CMOS 
transmission gate 60 transmits input signal Di (i=1-4) in response to an 
enable signal ENi (i=1-4). The two inverters 61 and 62 connected in series 
buffer the signal output by the transmission gate 60. The CMOS 
transmission gate 64 transmits the output of the inverter 63 to the 
inverter 61 in response to an inverted enable signal ENi (i=1-4). Enable 
signal ENBi (i=1-4) is the complement (not shown) of Enable signal ENi 
(i=1-4). The inverter 63 and CMOS transmission gate 64 latch the output 
from transmission gate 60. 
FIG. 3B is a schematic diagram showing exemplary T flip flop circuits used 
in the counter 20. A NAND gate 70 receives the reset signal R and a 
feedback signal. The feedback signal is generated by an inverter 71, a 
CMOS transmission gate 72, an inverter 73 and a CMOS transmission gate 74 
(respective to signal flow). A first small feedback loop takes the signal 
output by the inverter 73 and feeds it back to the inverter's 73 input. 
The first small feedback loop has an inverter 77 and a CMOS transmission 
gate 78 (respective to signal flow). A second small feedback loop takes 
the signal output by the NAND gate 70 and feeds it back to the NAND gate's 
70 input. The second signal feedback loop has an inverter 75 and a CMOS 
transmission gate 76 (respective to signal flow). The T flip flop circuit 
uses the NAND gate 70 and inverter 71 to reset output Qi (i=1-4) by reset 
signal R. The CMOS transmission gate 72 and inverter 73 transmit the 
output of the inverter 71 in response to clock signal CK. The CMOS 
transmission gate 76 connected to one input of the NAND gate 70 
simultaneously latches the output of the inverter 75 (which inverts the 
output of NAND gate 70). The CMOS transmission gate 78 connected to the 
input of the inverter 73 latches the output of the inverter 77 (which 
inverts the output of inverter 73) in response to inverted clock signal 
CKB. The inverted clock signal CKB is the complement (not shown) of the 
clock signal CK. 
FIG. 3C is a schematic diagram showing exemplary bit comparator circuits 
used in the comparator 30. The exemplary comparator used in this 
illustration is an XOR gate. The XOR gate has a NOR gate 80 for receiving 
first and second inputs IN1 and IN2, and a NOR gate 82 for receiving and 
outputting the outputs of NOR gate 80 and AND gate 81. 
FIG. 4 is a timing diagram illustrating the operation of the data 
coincidence detecting circuit. When a logic low "0" reset signal R is 
applied to the flip flops 21, 22, 23 and 24, these flip flops are reset. 
Afterwards, when the reset signal R goes to logic level high "1", the flip 
flops count up from "0000" to "1111" in response to the clock signal CK. 
If the LSB enable signal EN1 is logic level high "1" and the MSB enable 
signal EN4 is logic level low "0" the output of NOR gate 41 stays logic 
level low "0". Therefore, the output of the NAND gate 51 is logic level 
high "1". Inverter 52 complements the logic level high "1", so a logic 
level low "0" is output by the data coincidence detection circuit. If the 
MSB enable signal EN4 is logic level high "1" and the LSB enable signal 
EN1 is logic level low "0" the output of NOR gate 41 goes to logic level 
high "1". Therefore, the output of the NAND gate 51 is the logic level 
output by the nor gate 35. The signal output from the NAND gate 51 is 
inverted by the inverter 52. Therefore, when the outputs of all of the bit 
comparators 31, 32, 33 and 34 are logic level low "0", the output signal 
OUTPUT is logic level high "1", thereby identifying data coincidence. 
Accordingly, with an additional circuit for receiving n-bit data in a 
register in a specified order and masking the data load, the data 
coincidence detecting circuit of the present invention is capable of 
generating an errorless and precise data coincidence signal. 
While the present invention has been particularly shown and described with 
reference to particular embodiments thereof, it will be understood by 
those skilled in the art that various changes in form and details may be 
effected therein without departing from the spirit and scope of the 
invention as defined by the appended claims.