Method and apparatus for channel equalization with a digital FIR filter using a pseudo random sequence

A method and apparatus are provided for channel equalization with a digital finite impulse response (DFIR) filter using a pseudo random sequence. A readback signal of a pseudo random bit sequence is obtained. Samples are obtained from the readback signal of the pseudo random bit sequence. Tap gradients are calculated responsive to the obtained samples. The tap weights of the digital finite impulse response (FIR) filter are modified responsive to the calculated tap gradients. Dibit samples and error samples are obtained from the readback signal of the pseudo random bit sequence and applied to a tap gradients calculator. Tap gradients are calculated by a bitwise multiplier and accumulation tap gradient calculation circuit. An attenuation function attenuates the calculated tap gradients by a programmable attenuation value.

FIELD OF THE INVENTION

The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for channel equalization with a digital finite impulse response (DFIR) filter using a pseudo random sequence in a direct access storage device (DASD) data channel.

DESCRIPTION OF THE RELATED ART

Direct access storage devices (DASDs) often incorporating stacked, commonly rotated rigid magnetic disks are used for storage of data in magnetic form on the disk surfaces. Data is recorded in concentric, radially spaced data information tracks arrayed on the surfaces of the disks. Transducer heads driven in a path toward and away from the drive axis write data to the disks and read data from the disks. Typically servo information is provided on one or more disk surfaces for reading by the transducer heads for accurately and reliably positioning transducer heads on the disk surfaces at a specific location to read and write data.

In today's disk drives the readback signal typically is equalized using a finite impulse response (FIR) filter. There are numerous algorithms used to find the FIR tap weights that will result in giving the optimum channel equalization. A need exists for an improved method for channel equalization with a digital FIR filter. In current DASD data channels, channel equalization typically is achieved using extensive software algorithms. The known software algorithms are very time consuming, both during manufacture and use of the disk drive.

In earlier generations of DASD data channels, a common method of equalization used a method to reduce the Mean Square Error (MSE) of the equalized samples. Earlier designs suffered accuracy from noisy read back signals inherent in the channel.

A need exists for an improved method and apparatus for channel equalization with digital finite impulse response (DFIR) filter. A need exists for an improved equalization method that will eliminate the need for extensive software programs, as well as save time during manufacturing programming.

SUMMARY OF THE INVENTION

A principal object of the present invention is to provide a method and apparatus for channel equalization with a digital finite impulse response (DFIR) filter using a pseudo random sequence. Other important objects of the present invention are to provide such method and apparatus for channel equalization with a digital finite impulse response (DFIR) filter using a pseudo random sequence substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.

In brief, a method and apparatus are provided for channel equalization with a digital finite impulse response (DFIR) filter using a pseudo random sequence. A readback signal of a pseudo random bit sequence is obtained. Samples are obtained from the readback signal of the pseudo random bit sequence. Tap gradients are calculated responsive to the obtained samples. The tap weights of the digital finite impulse response (DFIR) filter are modified responsive to the calculated tap gradients.

In accordance with features of the invention, dibit samples and error samples are obtained from the readback signal of the pseudo random bit sequence and applied to a tap gradients calculator. Tap gradients are calculated by a bitwise multiplier and accumulation tap gradient calculation circuit. An attenuation function attenuates the calculated tap gradients by a programmable attenuation value.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Having reference now to the drawings, inFIG. 1, there is shown a direct access storage device (DASD) data channel for implementing methods for channel equalization with a digital finite impulse response (DFIR) filter in accordance with the preferred embodiment generally designated by the reference character100. Direct access storage device (DASD)100includes a direct equalization control function122for channel equalization with a digital finite impulse response (DFIR) filter in accordance with the preferred embodiment.

Data to be written is applied to an encoder102for providing a modulation coded output having predefined run length constraints. A precoder104follows the encoder102described by a 1/(1⊕D2) operation where D is a unit delay operator and the symbol ⊕ is used to represent modulo-2 addition. Modulo-2 addition can be thought of as an exclusive or operation. A PRML precomp106coupled to the precoder104provides a modulated binary pulse signal applied to a write circuit108that provides the modulated write current for writing to the disk surface. As shown inFIG. 1, direct access storage device (DASD)100includes a recorded disk110that is spun at constant speed and a recording head112that is positioned on a given track for reading information stored on that track. An analog read signal is obtained by head112described by the (1-D2) operation. The readback signal r(t) is highpass-filtered by an arm electronic (AE) module114, and its filtered output is applied to a variable gain amplifier (VGA)116. The amplified read signal is applied to an analog-to-digital converter (ADC)118that provides, for example, such as 64 possible 6-bit sampled values. The samples of the ADC118are applied to an equalizer120, such as a 10 tap digital finite impulse response (DFIR) filter120. The filtered signal from the DFIR filter120is applied to a detector (not shown) to provide a detected data output.

The samples of the ADC118are applied to a direct equalization control function122of the preferred embodiment. Direct equalization control function122of the preferred embodiment provides modified tap weights to the DFIR filter120for accurate channel equalization in accordance with the preferred embodiment.

In accordance with features of the preferred embodiment, a pseudo-random bit sequence (PRBS) waveform is written to the disk110. A readback signal consisting of a predefined number of bits, such as a 127 bit PRBS signal is readback from the disk110for implementing DFIR filter120equalization in accordance with the preferred embodiment.

The direct equalization (DEQ) method of the preferred embodiment iteratively modifies tap weights for DFIR filter120, for example, a 10-tap digital FIR filter120using the sampled dibit response of the PR4 system. A 127-bit pseudo-random bit sequence (PRBS) is used in this method to deconvolve and sample the PR4 dibit response. The dibit samples as well as a sampled error response are used to calculate the gradients for each tap weight of the DFIR filter120. These tap gradients are then used to modify the tap weights in such a manner as to better equalize the DFIR filter120.

In accordance with features of the preferred embodiment, channel equalization with the digital FIR (DFIR) filter120uses DASD internal circuitry, reduces user interaction, and greatly reduces programming time during manufacturing as compared to known equalization techniques. The method of the preferred embodiment accurately implements channel equalization with the digital FIR filter120, both quickly and effectively. The method of the preferred embodiment uses a zero-forcing method. This method utilizes a super-averaging of the waveform samples, this combined with the mathematical de-convolution of the dibit response, results in a generally noise free set of samples. The noise free samples are then used for further digital manipulation, and result in more accurate equalization. This design uses a proportional value of the tap gradients to modify the taps, eliminating thresholds. This method also eliminates the need for extensive software programs for channel equalization with the DFIR filter120, as well as save time during manufacturing programming as compared to known equalization techniques.

In accordance with features of the preferred embodiment, direct equalization control function122is an iterative method. Direct equalization control function122of the preferred embodiment utilizes the pseudo-random bit sequence (PRBS) that is written onto the hard disk110. When this sequence waveform is read back the unequalized sample stream are mathematically de-convolved inside the read channel to produce a set of samples that represent the dibit response of a PR4 system. These dibit samples, along with equalized error of the waveform samples, are then correlated to generate gradients for each tap weight used in the digital FIR filter120. Proportional amounts of these gradients are then added to each tap weight to modify each tap in a direction of better equalization.

This method utilizes three major steps in each iteration including dibit extraction; tap gradient calculation; and tap value modification. Unique features of the direct equalization control function122include the use of a pseudo-random bit sequence to extract the dibit points as well as the error points; the use of programmable proportional tap gradients to modify taps; an automatic shut off when equalization is complete; and user programmability.

Referring now toFIG. 2, there is shown an exemplary direct equalization control function122of the preferred embodiment. Direct equalization control function122includes a control circuit202receiving a GEM_GOOD_RD signal and generating a plurality of control signals labeled INC_READ_CNT; INC_GEM_PRBS_SEED; and INC_ITERATION_CNT. Direct equalization control function122includes a PRBS seed generation circuit204receiving a programmable start seed and generating a GEM start seed.

DASD100includes a General Error Measurement (GEM) facility205for error detection and the GEM circuitry is used to generate the dibit and error samples as further described below. Direct equalization control function122uses the pseudo-random bit sequence (PRBS) that is written repeatedly throughout a sector on the hard drive disk110. Data channel circuitry reads this PRBS pattern back, and digitizes the unequalized signal with the ADC118.

Dibit extraction can be described by the following equations, where:
Xinsta=Un-Equalized Sample
Einsta=Error in the Equalized PR4 Sample
N*PRBSlen=Integer multiple of PRBS length, (N*127 bits in this case).
Xdibit⁢a⁢=Δ⁢∑t=0N*PRBSlen⁢Xinst⁢t*PRBSt+a(1)Edibit⁢a⁢=Δ⁢∑t=0N*PRBSlen⁢Einst⁢t*PRBSt+a(2)

The dibit waveform points, (Xdibita), referred to as SRP or Sampled Response Points, for DASD100 consists of 12 samples, (a=0,1,2,3 . . . 7). While the ERP, Error Response Points (Edibita), consists of 21 samples, (a=0,1,2,3 . . . 16). A complete data read of the PRBS must be done to extract each point of the SRP and ERP. This equates to 33 individual reads per iteration. Notice that, for each read, the a-index refers to a phase shift of one bit in the PRBS pattern. This phase shifting is done by programming the system to start at a different seed for every read. The seed is incremented for each subsequent read to extract all the SRP samples. The seed is then returned to the original starting seed and incremented through the sequence again to extract the ERP samples. Note that the first samples extracted for SRP and ERP start with the same seed value provided by the PRBS seed generation circuit204. At the end of the iteration the seed is returned to the original programmed seed and is ready for the first read of the next iteration.

In order to extract consistent SRP and ERP, it is necessary to distinguish between a good and bad read. The window of accumulation must be continuous and GEM circuit205applies the GEM_GOOD_RD signal to the control circuit202of the direct equalization control function122to indicate a good read.

The GEM circuit205applies a SRP input to a SRP storage array206, such as 8×11-bit storage array, and applies an ERP input to an ERP storage array208, such as 17×10-bit storage array.

A read count210is coupled to an iteration count212and also is coupled to the SRP storage array206and ERP storage array208. After a successful read, the control circuit202sends a pulse to the read count210to increment its value. The read count210is a basic 6-bit primitive polynomial counter that starts with a value of 111111. The read count210is decoded and the decodes are used to route the incoming GEM values to proper storage array elements of the SRP storage array206and ERP storage array208. When the read count210reaches a predefined value, the loading of the SRP storage array206and ERP storage array208is complete and a tap gradient calculation count214is started. When the gradient calculations are complete, the read count210is reset to its original starting value and is ready for a next iteration set of read values.

The tap gradient calculation count214provides an enable input to a SRP multiplexer216coupled to the SRP storage array206and an ERP multiplexer218coupled to the ERP storage array208. Direct equalization control function122performs tap gradient calculations with a multiplier220having inputs coupled to the SRP multiplexer216and the ERP multiplexer218and an output of multiplier220coupled to an accumulator222. The calculated tap gradient outputs for each tap of the accumulator222are attenuated according to a programmable attenuation setting, selected by the user by a proportional gradient attenuation224.

Once all SRP and ERP samples are extracted and stored in the SRP storage array206and the ERP storage array208, the tap gradients are computed. The gradient calculations can be described by the following correlation equation, where:
CORRlen=Correlation length, (the number of SRP's extracted=12).
i=Number of Taps in DFIR, (i=10).
▽⁢⁢TAPi⁢=Δ⁢∑t=0CORRlen⁢Xdibit⁢t*Edibit⁢t+i(3)

The tap gradient calculation count214, such as, a 7-bit binary up counter is used to decode which pair of SRP and ERP samples is sent to the multiplier220and accumulator222. The gradient calculator formed by multiplier220and accumulator222consists of, for example, a 10-bit by 11-bit two's compliment multiplier220followed by a 24-bit accumulator222. The stored SRP and ERP samples are routed to the multiplier220in pairs according to equation 3. After the appropriate samples have been correlated, the resulting tap gradient is then attenuated by proportional gradient attenuation224and used to modify the tap weight.

The final step in this method is to modify the tap weights. Once the gradient is calculated for a specific tap, a programmable attenuation factor is applied by proportional gradient attenuation block224and this new value is added directly to the tap weight by a taps modifications block226. Tap modifications using the attenuated gradient are implemented as soon as a gradient is calculated. The existing tap value is loaded into a temporary tap weight register230. The value is modified, simply by adding or subtracting based on the gradient sign in the taps modifications block226and loaded into the real tap weight register228. In order to be more accurate during the modifications, each tap weight is expanded to a 12-bit representation. Of those 12 bits only the top 8 bits are sent to the DFIR filter120as the final tap value by a real taps block228. There is a 3-bit setting used by proportional gradient attenuation block224that controls the magnitude by which the tap gradients are attenuated, before the gradient is used to modify the taps. This value is basically a division factor, where the higher the setting the more attenuation is applied. The following table 1 gives the relative divisor value.

After the tap modifications are complete the iteration is complete, and new SRP and ERP extractions can start over again using the newly modified tap weights.

In operation, the control circuit202receives the GEM_GOOD_RD signal from GEM circuit205and creates a master good read pulse that is one XTAL period wide. This pulse drives the rest of the sequential logic which increments, decrements, loads and resets various logic throughout the entire direct equalization control function122. The control circuit202also creates signal pulses that start the post iteration activities. After the last read of the iteration, the tap gradient calculation counter214is started. This counter214is decoded to control the flow of ERP and SRP samples to the gradient calculator formed by multiplier220and accumulator222, as well as create the control pulses for other iteration activities. These include incrementing the iteration counter212at the end of the iteration, loading of the temporary tap registers230, and loading of the new real tap registers228when modifications are complete, as well as, indicating the iteration is done and the time is right to reset the read counter210and PRBS seed generation204for the next iteration. The iteration count212is a 9-bit counter representing the number of iterations that have been performed. The iteration count212is updated during the post iteration period by the INC_ITERATION_CNT output of the control circuit202. The iteration count212is compared with a programmable maximum iteration setting and when the maximum number of iterations is reached, the direct equalization control function122shuts off.

Direct equalization control function122sets itself apart from previous equalization designs in several ways. The first is the use of a pseudo-random bit sequence to deconvolve the dibit response. Second is the use of an iterative, zero-forcing algorithm instead of the mean square error method used in previous designs. Another is the use of programmable gradient attenuation function224to modify tap weights, instead of thresholds. This allows taps with larger gradients to move in their desired direction faster than taps with smaller gradients. One other unique feature is the flexibility of the circuit to shut itself off when equalization is complete.