Display apparatus and method of driving display panel using the same

A display apparatus includes: a display panel including: a gate line; a data line; and a pixel electrically connected to the gate line and the data line, and to display a normal image and a compensation image; a gate driver to output a gate signal to the gate line; a data driver to output a data voltage to the data line; and a power voltage generator to vary a level of a gate power voltage based on a compensation duty ratio corresponding to a ratio between a display duration of the normal image and a display duration of the compensation image.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0031861, filed on Mar. 16, 2020, in the Korean Intellectual Property Office (KIPO), the entire content of which is incorporated by reference herein.

BACKGROUND

Aspects of example embodiments of the present disclosure relate to a display apparatus, and a method of driving a display panel using the display apparatus. More particularly, example embodiments of the present disclosure relate to a display apparatus for enhancing a display quality, and a method of driving a display panel using the display apparatus.

2. Description of the Related Art

Generally, a display apparatus includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver, a data driver, an emission driver, and a driving controller. The gate driver outputs gate signals to the gate lines. The data driver outputs data voltages to the data lines. The emission driver outputs emission signals to the emission lines. The driving controller controls the gate driver, the data driver, and the emission driver.

When the display panel displays a moving image (e.g., a movie image), an afterimage of a previous frame image may be generated so that the image may be displayed as if dragged. To reduce or prevent the afterimage, a black image may be inserted between frame images. However, when the black image is inserted between the frame images, a charging rate may decrease due to insufficient charging time of the frame image.

SUMMARY

One or more example embodiments of the present disclosure are directed to a display apparatus for varying a gate power voltage based on a duty ratio of a compensation image to enhance a display quality.

One or more example embodiments of the present disclosure are directed to a method of driving the display panel using the display apparatus.

According to one or more example embodiments of the present disclosure, a display apparatus includes: a display panel including: a gate line; a data line; and a pixel electrically connected to the gate line and the data line, and configured to display a normal image and a compensation image; a gate driver configured to output a gate signal to the gate line; a data driver configured to output a data voltage to the data line; and a power voltage generator configured to vary a level of a gate power voltage based on a compensation duty ratio corresponding to a ratio between a display duration of the normal image and a display duration of the compensation image.

In an example embodiment, the gate power voltage may be a first gate power voltage corresponding to a high level of the gate signal.

In an example embodiment, the compensation duty ratio may be a ratio of the display duration of the compensation image to a sum of the display duration of the normal image and the display duration of the compensation image, and the power voltage generator may be configured to increase the first gate power voltage as the compensation duty ratio increases.

In an example embodiment, the gate power voltage may be a second gate power voltage corresponding to a low level of the gate signal.

In an example embodiment, the compensation duty ratio may be a ratio of the display duration of the compensation image to a sum of the display duration of the normal image and the display duration of the compensation image, and the power voltage generator may be configured to decrease the second gate power voltage as the compensation duty ratio increases.

In an example embodiment, the normal image may be displayed based on grayscale data of input image data, and the compensation image may be displayed regardless of the grayscale data of the input image data.

In an example embodiment, the compensation image may be a black image.

In an example embodiment, the display apparatus may further include a driving controller configured to control an operation of the gate driver and an operation of the data driver. The driving controller may include: a compensation image insertion enable determiner configured to enable and disable a compensation image insertion; and a compensation duty ratio determiner configured to determine the compensation duty ratio, and output the compensation duty ratio to the power voltage generator, when the compensation image insertion is enabled.

In an example embodiment, the power voltage generator may be configured to vary the level of the gate power voltage based on the compensation duty ratio and a luminance weight for varying a luminance of input image data according to the compensation duty ratio.

In an example embodiment, the luminance weight may be increased when the compensation duty ratio increases.

In an example embodiment, the gate power voltage may be a first gate power voltage corresponding to a high level of the gate signal.

In an example embodiment, the compensation duty ratio may be a ratio of the display duration of the compensation image to a sum of the display duration of the normal image and the display duration of the compensation image, the power voltage generator may be configured to increase the first gate power voltage as the compensation duty ratio increases, and the power voltage generator may be configured to increase the first gate power voltage as the luminance weight increases.

In an example embodiment, the gate power voltage may be a second gate power voltage corresponding to a low level of the gate signal.

In an example embodiment, the compensation duty ratio may be a ratio of the display duration of the compensation image to a sum of the display duration of the normal image and the display duration of the compensation image, the power voltage generator may be configured to decrease the second gate power voltage as the compensation duty ratio increases, and the power voltage generator may be configured to decrease the second gate power voltage as the luminance weight increases.

In an example embodiment, the display apparatus may further include a driving controller configured to control an operation of the gate driver and an operation of the data driver. The driving controller may include: a compensation image insertion enable determiner configured to enable and disable a compensation image insertion; a compensation duty ratio determiner configured to determine the compensation duty ratio, and output the compensation duty ratio to the power voltage generator, when the compensation image insertion is enabled; a luminance weight enable determiner configured to enable and disable applying of the luminance weight; and a luminance weight determiner configured to determine the luminance weight, and output the luminance weight to the power voltage generator, when the applying of the luminance weight is enabled.

According to one or more example embodiments of the present disclosure, a method of driving a display panel, includes: determining a level of a gate power voltage based on a compensation duty ratio corresponding to a ratio between a display duration of a normal image and a display duration of a compensation image; generating a gate signal based on the gate power voltage; outputting the gate signal to a gate line; and outputting a data voltage to a data line based on input image data.

In an example embodiment, the gate power voltage may be a first gate power voltage corresponding to a high level of the gate signal, the compensation duty ratio may be a ratio of the display duration of the compensation image to a sum of the display duration of the normal image and the display duration of the compensation image, and the first gate power voltage may be increased as the compensation duty ratio increases.

In an example embodiment, the gate power voltage may be a second gate power voltage corresponding to a low level of the gate signal, the compensation duty ratio may be a ratio of the display duration of the compensation image to a sum of the display duration of the normal image and the display duration of the compensation image, and the second gate power voltage may be decreased as the compensation duty ratio increases.

In an example embodiment, the normal image may be displayed based on grayscale data of the input image data, and the compensation image may be displayed regardless of the grayscale data of the input image data.

In an example embodiment, the level of the gate power voltage may be determined based on the compensation duty ratio and a luminance weight for varying a luminance of the input image data according to the compensation duty ratio.

According to one or more example embodiments of the present disclosure, in the display apparatus and the method of driving the display panel, a compensation image may be inserted between normal images so that an image drag due to an instantaneous afterimage, which may occur due to a moving picture response time, may be prevented or substantially prevented.

In addition, according to one or more example embodiments of the present disclosure, a gate power voltage may be varied based on the duty ratio of the compensation image so that a decrease of a charging rate of the normal image and a display defect due to the decrease of the charging rate may be prevented or substantially prevented when the compensation image is inserted between the normal images. The charging rate of the normal image may be compensated so that the display quality of the display panel may be enhanced.

DETAILED DESCRIPTION

FIG.1is a block diagram illustrating a display apparatus according to an example embodiment of the present disclosure.

Referring toFIG.1, the display apparatus includes a display panel100, and a display panel driver. The display panel driver includes a driving controller (e.g., a timing controller)200, a gate driver (e.g., a scan driver)300, a gamma reference voltage generator400, and a data driver500. The display panel driver further includes a power voltage generator600.

In some embodiments, for example, the driving controller200and the data driver500may be integrally formed with each other. In some embodiments, for example, the driving controller200, the gamma reference voltage generator400, and the data driver500may be integrally formed with each other. A driving module including at least the driving controller200and the data driver500, which may be integrally formed with each other, may be referred to as a timing controller embedded data driver (TED).

The display panel100has a display region at (e.g., in or on) which an image is displayed, and a peripheral region adjacent to the display region. For example, the peripheral region may at least partially surround (e.g., around a periphery of) the display region.

The display panel100includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels P connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D1, and the data lines DL extend in a second direction D2crossing the first direction D1.

In the present example embodiment, the display panel100may be an organic light emitting display panel including an organic light emitting element. However, the present disclosure is not limited thereto, and in another example embodiment, the display panel100may be a liquid crystal display panel including a liquid crystal molecule.

The driving controller200receives input image data IMG and an input control signal CONT from an external apparatus. In some embodiments, the input image data IMG may include red image data, green image data, and blue image data. In some embodiments, the input image data IMG may include white image data. In some embodiments, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. In some embodiments, the input control signal CONT may further include a vertical synchronizing signal and a horizontal synchronizing signal.

The driving controller200generates the second control signal CONT2for controlling an operation of the data driver500based on the input control signal CONT, and outputs the second control signal CONT2to the data driver500. The second control signal CONT2may include a horizontal start signal and a load signal.

The driving controller200generates the data signal DATA based on the input image data IMG. The driving controller200outputs the data signal DATA to the data driver500.

The driving controller200generates the third control signal CONT3for controlling an operation of the gamma reference voltage generator400based on the input control signal CONT, and outputs the third control signal CONT3to the gamma reference voltage generator400.

The gate driver300generates gate signals for driving the gate lines GL in response to the first control signal CONT1received from the driving controller200. The gate driver300outputs the gate signals to the gate lines GL. For example, the gate driver300may sequentially output the gate signals to the gate lines GL. In some embodiments, for example, the gate driver300may be integrated on the display panel100. For example, the gate driver300may be mounted on the display panel100.

The gamma reference voltage generator400generates a gamma reference voltage VGREF in response to the third control signal CONT3received from the driving controller200. The gamma reference voltage generator400provides the gamma reference voltage VGREF to the data driver500. The gamma reference voltage VGREF may have a value corresponding to a level of the data signal DATA.

In an example embodiment, the gamma reference voltage generator400may be disposed at (e.g., in or on) the driving controller200, or at (e.g., in or on) the data driver500.

The data driver500receives the second control signal CONT2and the data signal DATA from the driving controller200, and receives the gamma reference voltages VGREF from the gamma reference voltage generator400. The data driver500converts the data signal DATA into data voltages having an analog type using the gamma reference voltages VGREF. The data driver500outputs the data voltages to the data lines DL.

The power voltage generator600may generate a power voltage for driving at least one of the display panel100, the driving controller200, the gate driver300, the gamma reference voltage generator400, and the data driver500.

For example, the power voltage generator600may output a first pixel power voltage ELVDD and a second pixel power voltage ELVSS, which are applied to the pixels P of the display panel100, to the display panel100.

For example, the power voltage generator600may generate a gate power voltage for determining a level of the gate signal, and may output the gate power voltage to the gate driver300. The power voltage generator600may generate a first gate power voltage VGH for determining a high level of the gate signal, and a second gate power voltage VGL for determining a low level of the gate signal. The power voltage generator600may output the first gate power voltage VGH and the second gate power voltage VGL to the gate driver300. As described in more detail below, in some embodiments, the power voltage generator600may vary a level of the gate power voltage (e.g. VGH and/or VGL) based on a compensation duty ratio BD received from the driving controller200.

FIG.2is a conceptual diagram illustrating image frames of an image displayed on the display panel100ofFIG.1.

Referring toFIGS.1and2, the display panel100displays an image in a unit of a frame. The display panel100displays a first frame image in a first frame FRAME1, and a second frame image different from the first frame image in a second frame FRAME2.

In the present example embodiment, the display panel100may display normal images IMAGE1and IMAGE2, and a compensation image BLACK. The normal images IMAGE1and IMAGE2may be displayed based on grayscale data of the input image data IMG. On the other hand, the compensation image BLACK may be displayed regardless of the grayscale data of the input image data IMG.

The compensation image BLACK may be inserted between the normal images IMAGE1and IMAGE2so that an image drag due to an instantaneous afterimage, which may occur due to a moving picture response time, may be prevented or substantially prevented. For example, the compensation image BLACK may be a low luminance image. For example, the compensation image BLACK may be a black image.

The power voltage generator600may vary a level of the gate power voltage (e.g. VGH and/or VGL) based on a compensation duty ratio BD determined based on a ratio between a display duration DU1of the normal image IMAGE1and a display duration DU2of the compensation image BLACK. For example, the compensation duty ratio BD may refer to a ratio of the display duration DU2of the compensation image BLACK to a sum (e.g., DU1+DU2) of the display duration DU1of the normal image IMAGE1and the display duration DU2of the compensation image BLACK.

FIG.3is a block diagram illustrating the driving controller200ofFIG.1in more detail.

Referring toFIGS.1to3, the driving controller200may include a compensation image insertion enable determiner (e.g., a BI enable determiner)220, and a compensation duty ratio determiner (e.g., a BI duty determiner)240. The compensation image insertion enable determiner220may enable and disable the compensation image insertion. For example, the compensation image insertion enable determiner220may generate a compensation image insertion signal BI having an enable level when the compensation image BLACK is to be inserted (e.g., when consecutive images to be displayed are moving images), and may provide the compensation image insertion signal BI to the compensation duty ratio determiner240. When the compensation image insertion signal BI is enabled, the compensation duty ratio determiner240may determine the compensation duty ratio BD, and may output the compensation duty ratio BD to the power voltage generator600. The driving controller200may determine to insert the compensation image BLACK between the normal images or not based on the input image data IMG. When the driving controller200determines that the input image data IMG causes the image drag due to the instantaneous afterimage, the driving controller200may determine to insert the compensation image BLACK between the normal images. Alternatively, it is determined to insert the compensation image BLACK between the normal images or not by user settings.

For example, the compensation duty ratio determiner240may output the compensation duty ratio BD to a gate power voltage generator620of the power voltage generator600.

The gate power voltage generator620may vary a level of the gate power voltage (e.g. VGH and/or VGL) based on the compensation duty ratio BD.

FIG.4is a circuit diagram illustrating an example of the pixel P of the display panel100ofFIG.1.FIG.5is a conceptual diagram illustrating a charging rate of a data voltage VD charged at the pixel P ofFIG.1.

Referring toFIGS.1to5, the pixel P includes a first pixel switching element (e.g., a first pixel switching transistor) T1, a second pixel switching element (e.g., a second pixel switching transistor) T2, a storage capacitor CS, and the organic light emitting element (e.g., an organic light emitting diode) OLED.

The first pixel switching element T1may be a thin film transistor. The first pixel switching element T1includes a control electrode connected to the gate line GL, an input electrode connected to the data line DL, and an output electrode connected to a control electrode of the second pixel switching element T2.

The control electrode of the first pixel switching element T1may be a gate electrode. The input electrode of the first pixel switching element T1may be a source electrode. The output electrode of the first pixel switching element T1may be a drain electrode.

The second pixel switching element T2may be a thin film transistor. The second pixel switching element T2includes a control electrode connected to the output electrode of the first pixel switching element T1, an input electrode to which the first pixel power voltage ELVDD is applied, and an output electrode connected to a first electrode of the organic light emitting element OLED.

The control electrode of the second pixel switching element T2may be a gate electrode. The input electrode of the second pixel switching element T2may be a source electrode. The output electrode of the second pixel switching element T2may be a drain electrode.

A first end of the storage capacitor CS is connected to the input electrode of the second pixel switching element T2. A second end of the storage capacitor CS is connected to the output electrode of the first pixel switching element T1.

The first electrode of the organic light emitting element OLED is connected to the output electrode of the second pixel switching element T2. The second pixel power voltage ELVSS is applied to the second electrode of the organic light emitting element OLED.

The first electrode of the organic light emitting element OLED may be an anode electrode. The second electrode of the organic light emitting element OLED may be a cathode electrode.

The pixel P receives the gate signal GS, the data voltage VD, the first pixel power voltage ELVDD, and the second pixel power voltage ELVSS, and may emit the organic light emitting element OLED having a luminance corresponding to the data voltage VD to display an image.

When a charging rate of the data voltage VD is insufficient, the organic light emitting element OLED may not display an image with a desired luminance. For example, when the compensation image BLACK is inserted between the normal images IMAGE1and IMAGE2to reduce the instantaneous afterimage due to the moving picture response time, the charging rate of the normal image IMAGE1may not be sufficient.

As shown inFIG.5, the charging rate CHR of the data voltage VD may be determined based on a waveform of a pulse of the gate signal GS, a waveform of a pulse of the data voltage VD, a timing of the pulse of the gate signal GS, and a timing of the pulse of the data voltage VD. InFIG.5, the charging rate CHR of the data voltage VD may be represented as an overlapped portion of the pulse of the gate signal GS and the pulse of the data voltage VD.

FIG.6is a graph illustrating a current ISW of the switching element ofFIG.4according to the first gate power voltage VGH.FIG.7is a graph illustrating the charging rate of the data voltage VD charged at the pixel P ofFIG.1according to the first gate power voltage VGH.FIG.8is a graph illustrating the first gate power voltage VGH according to the compensation duty ratio BD determined by the compensation duty ratio determiner240ofFIG.3.FIG.9is a graph illustrating the charging rate of the data voltage VD charged at the pixel P ofFIG.1according to the compensation of the first gate power voltage VGH inFIG.8.

Referring toFIGS.1to9, in the present example embodiment, the gate power voltage generator620may vary the first gate power voltage VGH based on the compensation duty ratio BD. For example, in some embodiments, as the compensation duty ratio BD increases, the gate power voltage generator620may increase the first gate power voltage VGH.

As shown inFIGS.4,5and6, when the first gate power voltage VGH increases, a switching transistor current ISW flowing through the input electrode and the output electrode of the first pixel transistor T1increases.

Thus, as shown inFIG.7, when the first gate power voltage VGH increases, the charging rate of the data voltage VD may increase.

Generally, when the compensation duty ratio BD increases, the charging time of the data voltage VD decreases so that the charging rate of the data voltage VD may be reduced (e.g., without VGH compensation). Accordingly, as shown inFIG.8, when the compensation duty ratio BD increases, the gate power voltage generator620may increase the first gate power voltage VGH (e.g., with VGH compensation). Thus, as shown inFIG.9, the charging rate of the data voltage VD may be compensated due to the increase of the first gate power voltage VGH (e.g., with VGH compensation).

FIG.10is a graph illustrating a waveform of a gate signal GS applied to the pixel P ofFIG.1according to the second gate power voltage VGL.FIG.11is a graph illustrating the charging rate of the data voltage VD charged at the pixel P ofFIG.1according to the second gate power voltage VGL.FIG.12is a graph illustrating the second gate power voltage VGL according to the compensation duty ratio BD determined by the compensation duty ratio determiner240ofFIG.3.FIG.13is a graph illustrating the charging rate of the data voltage VD charged at the pixel P ofFIG.1according to the compensation of the second gate power voltage VGL inFIG.12.

Referring toFIGS.1to5and10to13, in the present example embodiment, the gate power voltage generator620may vary the second gate power voltage VGL based on the compensation duty ratio BD. For example, in some embodiments, as the compensation duty ratio BD increases, the gate power voltage generator620may decrease the second gate power voltage VGL. When a polarity of the second gate power voltage VGL is defined as a negative polarity, as the compensation duty ratio BD increases, the gate power voltage generator620may increase an absolute value |VGL| of the second gate power voltage VGL.

As shown inFIG.10, as the second gate power voltage VGL decreases, the falling time of the waveform of the gate signal GS may decrease. A second falling time of the gate signal GS when the gate signal GS decreases from a high level to a second level VGL2may be shorter than a first falling time of the gate signal GS when the gate signal GS decreases from the high level to a first level VGL1. A third falling time of the gate signal GS when the gate signal GS decreases from the high level to a third level VGL3may be shorter than the second falling time of the gate signal GS when the gate signal GS decreases from the high level to the second level VGL2.

When the falling time of the waveform of the gate signal GS is shorter, the gate signal GS may be decreased lower than a threshold voltage VTH of the first pixel transistor T1faster so that the switching characteristics of the first pixel transistor T1may be enhanced. When the switching characteristics of the first pixel transistor are enhanced, the charging rate of the data voltage VD may increase.

Generally, when the compensation duty ratio BD increases, the charging time of the data voltage VD decreases so that the charging rate of the data voltage VD may be reduced (e.g., without |VGL| compensation). Accordingly, as shown inFIG.12, when the compensation duty ratio BD increases, the gate power voltage generator620may decrease the second gate power voltage VGL or may increase the absolute |VGL| of the second gate power voltage (e.g., with |VGL| compensation). Thus, as shown inFIG.13, the charging rate of the data voltage VD may be compensated due to the decrease of the second gate power voltage VGL or the increase of the absolute value |VGL| of the second gate power voltage (e.g., with |VGL| compensation).

As described with reference toFIGS.5to9, in some embodiments, the power voltage generator600may vary the level of the first gate power voltage VGH according to the compensation duty ratio BD. As described with reference toFIGS.10to13, in some embodiments, the power voltage generator600may vary the level of the second gate power voltage VGL according to the compensation duty ratio BD. In an example embodiment, the power voltage generator600may vary both the levels of the first gate power voltage VGH and the second gate power voltage VGL according to the compensation duty ratio BD.

According to the present example embodiment, the compensation image BLACK is inserted between the normal images IMAGE1and IMAGE2so that an image drag due to an instantaneous afterimage, which may occur due to a moving picture response time, may be prevented or substantially prevented.

In addition, the gate power voltage (VGH and/or VGL) is varied based on the duty ratio BD of the compensation image BLACK so that the decrease of the charging rate of the normal image IMAGE1and the display defect due to the decrease of the charging rate may be prevented or substantially prevented when the compensation image BLACK is inserted between the normal images IMAGE1and IMAGE2. The charging rate of the normal image IMAGE1is compensated so that the display quality of the display panel100may be enhanced.

FIG.14is a block diagram illustrating a display apparatus according to an example embodiment of the present disclosure.FIG.15is a block diagram illustrating a driving controller200ofFIG.14;

The display apparatus and the method of driving the display panel according to the present example embodiment is the same or substantially the same as the display apparatus and the method of driving the display panel described with reference toFIGS.1to13, except for the structures of the driving controller200and the power voltage generator600, and the operations of the driving controller200and the power voltage generator600. Thus, the same reference numerals will be used to refer to the same or substantially the same elements or parts (e.g., like or similar elements or parts) as those described in the embodiments ofFIGS.1to13, and redundant description thereof may not be repeated.

Referring toFIGS.2and4to15, the display apparatus includes a display panel100, and a display panel driver. The display panel driver includes a driving controller (e.g., a timing controller)200, a gate driver (e.g., a scan driver)300, a gamma reference voltage generator400, and a data driver500. The display panel driver further includes a power voltage generator600.

In the present example embodiment, the display panel100may display normal images IMAGE1and IMAGE2, and a compensation image BLACK. The normal images IMAGE1and IMAGE2may be displayed based on grayscale data of the input image data IMG. On the other hand, the compensation image BLACK may be displayed regardless of the grayscale data of the input image data IMG.

The power voltage generator600may vary the level of the gate power voltage (e.g. VGH and/or VGL) based on the compensation duty ratio BD determined based on a ratio between a display duration DU1of the normal image IMAGE1and a display duration DU2of the compensation image BLACK. In addition, the power voltage generator600may vary the level of the gate power voltage (e.g. VGH and/or VGL) based on a luminance weight LW for varying a luminance of the input image data IMG according to the compensation duty ratio BD. Herein, the compensation duty ratio BD may refer to a ratio of the display duration DU2of the compensation image BLACK to a sum (e.g., DU1+DU2) of the display duration DUI of the normal image IMAGE1and the display duration DU2of the compensation image BLACK. The luminance weight LW may be a gain multiplied to the input image data IMG to increase the luminance of the image. For example, when the luminance weight LW is 1.2, the input image data IMG may be increased by 20%.

The driving controller200may include a compensation image insertion enable determiner (e.g., a BI enable determiner)220, and a compensation duty ratio determiner (e.g., a BI duty determiner)240. The compensation image insertion enable determiner220may enable and disable the compensation image insertion. For example, the compensation image insertion enable determiner220may generate a compensation image insertion signal BI having an enable level when the compensation image BLACK is to be inserted (e.g., when consecutive images to be displayed are moving images), and may provide the compensation image insertion signal BI to the compensation duty ratio determiner240. When the compensation image insertion signal BI is enabled, the compensation duty ratio determiner240may determine the compensation duty ratio BD, and may output the compensation duty ratio BD to the power voltage generator600(e.g., to the gate power voltage generator620).

In the present example embodiment, the driving controller200may further include a luminance weight enable determiner260and a luminance weight determiner280. The luminance weight enable determiner260may enable and disable the applying of the luminance weight LW. For example, the luminance weight enable determiner260may generate a luminance weight enable signal LE having an enable level when the luminance weight LW is to be applied (e.g., when a luminance amount of the image to be displayed exceeds a threshold value) according to the compensation duty ratio BD, and may provide the luminance weight enable signal LE to the luminance weight determiner280. When the luminance weight enable signal LE is enabled, the luminance weight determiner280may determine the luminance weight LW, and may output the luminance weight LW to the power voltage generator600. The driving controller200may determine to apply the luminance weight LW or not based on the compensation duty ratio BD. Alternatively, it is determined to apply the luminance weight LW or not by user settings.

The compensation duty ratio determiner240may output the compensation duty ratio BD to the gate power voltage generator620of the power voltage generator600. The luminance weight determiner280may output the luminance weight LW to the gate power voltage generator620of the power voltage generator600.

The gate power voltage generator620may vary a level of the gate power voltage (e.g. VGH and/or VGL) based on the compensation duty ratio BD and the luminance weight LW.

When the charging rate of the data voltage VD is insufficient, the organic light emitting element OLED may not display an image having a desired luminance. For example, when the compensation image BLACK is inserted between the normal images IMAGE1and IMAGE2to reduce the instantaneous afterimage due to the moving picture response time, the charging rate of the normal image IMAGE1may not be sufficient.

When the compensation duty ratio BD increases, the luminance weight LW may increase. To compensate the decrease of the charging rate due to the compensation duty ratio BD, the driving controller200may amplify a luminance of the input image data IMG using the luminance weight LW.

However, when the level of the data voltage VD increases due to the increase of the luminance weight LW, a rising time of the waveform of the data voltage VD may increase due to the increase of the level of the data voltage VD. Accordingly, the desired data voltage VD may not be sufficiently charged. Thus, when the applying of the luminance weight LW is enabled, an additional compensation of the gate power voltage (e.g. VGH and/or VGL) may be desired.

FIG.16is a graph illustrating the gate power voltage (e.g. VGH and/or VGL) according to the luminance weight LW determined by the luminance weight determiner280ofFIG.15.FIG.17is a graph illustrating the charging rate of the data voltage VD charged at the pixel P according to the compensation of the gate power voltage (e.g. VGH and/or VGL) inFIG.16.

Referring toFIGS.2and4to17, generally, when the luminance weight LW increases, the charging load of the data voltage VD increases so that the desired charging rate of the data voltage VD may not be guaranteed (e.g., without gate power voltage compensation). Accordingly, as shown inFIG.16, when the luminance weight LW increases, the gate power voltage generator620may increase the first gate power voltage VGH and/or may decrease the second gate power voltage VGL (or increase the absolute value |VGL| of the second gate power voltage) (e.g., with gate power voltage compensation). Thus, as shown inFIG.17, the charging rate of the data voltage VD may be compensated due to the increase of the first gate power voltage VGH and/or the decrease of the second gate power voltage VGL (e.g., with gate power voltage compensation).

The power voltage generator600of the present example embodiment inFIGS.16and17may selectively vary one of the level of the first gate power voltage VGH or the level of the second gate power voltage VGL. In other embodiments, the power voltage generator600of the present example embodiment inFIGS.16and17may vary both the levels of the first gate power voltage VGH and the second gate power voltage VGL.

FIG.18is a graph illustrating the gate power voltage (e.g. VGH and/or VGL) according to the compensation duty ratio BD determined by the compensation duty ratio determiner240and the luminance weight LW determined by the luminance weight determiner280ofFIG.15.FIG.19is a graph illustrating the charging rate of the data voltage VD charged at the pixel P according to the compensation of the gate power voltage (e.g. VGH and/or VGL) inFIG.18.

Referring toFIGS.2and4to19, when the compensation duty ratio BD increases, the gate power voltage generator620may increase the level of the first gate power voltage VGH. When the luminance weight LW increases, the gate power voltage generator620may increase the level of the first gate power voltage VGH.

When the compensation duty ratio BD increases, the gate power voltage generator620may decrease the level of the second gate power voltage VGL (or increase the absolute value |VGL| of the level of the second gate power voltage). When the luminance weight LW increases, the gate power voltage generator620may decrease the level of the second gate power voltage VGL (or increase the absolute value |VGL| of the level of the second gate power voltage).

As shown inFIGS.18and19, when the gate power voltage (e.g. VGH and/or VGL) is compensated based on the compensation duty ratio BD and the luminance weight LW, the charging rate of the data voltage VD may further increase when compared to the case where the gate power voltage (e.g. VGH and/or VGL) is compensated only based on the compensation duty ratio BD.

According to the present example embodiment, the compensation image BLACK is inserted between the normal images IMAGE1and IMAGE2so that an image drag due to an instantaneous afterimage, which may occur due to a moving picture response time, may be prevented or substantially prevented.

In addition, the gate power voltage (e.g., VGH and/or VGL) is varied based on the duty ratio BD of the compensation image BLACK and the luminance weight LW so that the decrease of the charging rate of the normal image IMAGE1and the display defect due to the decrease of the charging rate may be prevented or substantially prevented when the compensation image BLACK is inserted between the normal images IMAGE1and IMAGE2. The charging rate of the normal image IMAGE1is compensated so that the display quality of the display panel100may be enhanced.

According to one or more example embodiments of the present disclosure described above, the display quality of the display panel may be enhanced.

Although some example embodiments have been described, those skilled in the art will readily appreciate that various modifications are possible in the example embodiments without departing from the spirit and scope of the present disclosure. It will be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless otherwise described. Thus, as would be apparent to one of ordinary skill in the art, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. In the claims, means-plus-function clauses, if any, are intended to cover the structures described herein as performing the recited function, and not only structural equivalents, but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed herein, and that various modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the spirit and scope of the present disclosure as defined in the appended claims, and their equivalents.