Enhanced cascade field effect transistor

A field-effect transistor (FET) includes a fin, an insulator region, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or more lightly doped than the first and second regions. The interior region of the fin is formed as a superlattice of layers of first and second materials alternating vertically. The insulator layer extends around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the gate are configured to generate an inhomogeneous electrostatic potential within the interior region, the inhomogeneous electrostatic potential cooperating with physical properties of the superlattice to cause scattering of charge carriers sufficient to change a quantum property of such charge carriers to change the ability of the charge carriers to move between the first and second materials.

FIELD

The present invention relates generally to semiconductor devices, and more particularly, to field effect transistors.

BACKGROUND

The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is by far the most common transistor in digital circuits. Because billions of MOSFETs can be included in a memory chip or microprocessor, developments of MOSFET technology often involve the reduction in size or scaling of MOSFET devices while maintaining performance characteristics.

The scaling of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has reached sub-10 nm range. However, further reducing the transistor size is challenged by the power consumption. To address this, a smaller subthreshold swing (SS) is the key to reducing the supply voltage and the subthreshold leakage current. The SS of a MOSFET is generally a characterization of the amount of voltage necessary to change the current flow by a decade. A reduced supply voltage and a reduced subthreshold leakage current are essential for low power electronics.

The SS of conventional MOSFETs is fundamentally limited to a minimum of 60 mV/decade. However, there have been proposed devices that promise a subthreshold swing of less than 60 mV/decade. These are devices based on impact ionization, ferroelectric dielectrics, mechanical gates and band-to-band tunneling. Tunneling field effect transistors (TFETs) are particularly promising since they do not suffer from delays caused by positive feedback that is common in the other device concepts. However, despite many predictions of outstanding TFET performance and more than a decade of considerable research efforts worldwide, most experimental TFETs underperform conventional MOSFETs. TFETs with an SS below 60 mV/decade and a sufficiently large ON current have not been demonstrated.

There is evidence that the TFET-typical switching mechanism by tuning the alignment of valence and conduction band is insufficient to maintain a sufficient ON current and low SS: Incoherent scattering mechanisms such as Auger recombination, electron scattering on phonons and impurities are supporting the band tail formation that eventually spoils a rapid switching behavior.

There exists a need, therefore, for an improvement to field effect transistor (FET) and TFET performance that reduces the impact of the band tail formation on the leakage current and increases the ON/OFF current density ratio significantly.

SUMMARY

At least some of the embodiments described herein address the above-stated need by introducing a FET device that incorporates additional switching mechanisms. The FET device uses tuned electrostatic potential across a superlattice to exploit such mechanisms.

A first embodiment is a field-effect transistor (FET) that includes a fin, an insulator region, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or more lightly doped than the first region and the second region. The interior region of the fin is formed as a superlattice of layers of first and second materials alternating vertically. The insulator layer extends around the interior region. The at least one gate is formed on at least a portion of the insulator region. The insulator layer and the at least one gate are configured to generate an inhomogeneous electrostatic potential within the interior region, the inhomogeneous electrostatic potential cooperating with physical properties of the superlattice to cause scattering of charge carriers sufficient to change a quantum property of such charge carriers to change the ability of the charge carriers to move between the first and second materials.

The use of the inhomogeneous electric field to change the ability of the charge carriers to move between the first and second materials can be used as an additional switching mechanism for current flow between the first region and the second region, which enhances the general switching mechanisms already present in FETs.

DETAILED DESCRIPTION

FIG. 1shows a perspective view of an exemplary embodiment of a cascade FET10according to a first embodiment of the invention.FIG. 2shows a cutaway view taken along line II-II ofFIG. 1, andFIG. 3shows a cutaway view taken along line III-III ofFIG. 1. It will be appreciated that the relative sizes of layers and regions may be exaggerated for clarity of exposition.

With simultaneous reference toFIGS. 1 to 3, the FET10is disposed on a buried oxide layer14, which in turn is disposed above a substrate12. The FET10in this embodiment includes a fin22, an insulator region16, and upper and lower gates18,20, respectively. The fin22has a doped first region30, a doped second region32, and an interior region24between the first region30and the second region32. The interior region24is covered by the insulator16and/or gates18, and20inFIG. 1, but is shown inFIGS. 2 and 3. The interior region24is formed of a superlattice having alternating layers24a,24b.

The alternating layers24a,24bof the interior region/superlattice24alternate in the vertical or z-direction, which is perpendicular the current flow direction or y-direction. As will be discussed in further detail, the alternating layers24a,24bare layers of different materials, wherein particles (i.e. charge carriers) carry a measurable property (e.g. quantum characteristic) that is different in the two materials. For example, the measurable property may be energy, momentum, spin, chirality, or being in the valence or conduction band. This measurable property should be a property that effectively does not change during the coherent propagation of the particle in its respective layer24aor24b.

In general, the two materials may be selected from two different semiconductors, for example, InAs and GaSb, or alternatively may be based on the same semiconductor, but have been treated in a way that causes quantum characteristics of the particles in alternating layers to differ. In other words, the quantum property of the starting semiconductor material may be tuned to form layers of alternating quantum properties. For example, the two materials of the alternating layers may be the same semiconductor base, but are lightly doped in alternating layers in different ways. In another alternative, the same semiconductor base material be used to form a lattice of alternating layers having alternating spin characteristics, using an antiferromagnetic oxide, not shown, surrounding the device10to induce alternating spin. The alternating spin is based on the respective spin polarization of the antiferromagnetic oxides that induces that polarization to the closest particular layers24aor24b. Nevertheless, the use of different semiconductor base materials in alternating layers24a,24bis a flexible and useful way to achieve alternating layers of materials having particles with at least one different quantum characteristic that may be manipulated to provide the cascade switching mechanisms described below in connection withFIGS. 4 and 5.

In any event, the alternating layers may be made from InAs and GaSb, InAs and AlSb, InAs and GaInSb, InAsSb and InSb, InAlN and GaN, AlGaAs and AlAs, AlGaAs and GaAs, or ZnSe and ZnTe. In other embodiments, the superlattice is formed from metal dichalcogenides, phosphorene, graphene, silicone, germanene, stanine, MoS2/MoTe2, SiGe/Si, metal oxide, group IV semiconductor material, group III/V semiconductor material, or group II/VI semiconductor material.

The layers24a,24bare undoped, or lightly doped in comparison the first region30and the second region32. Each of the first region30and second region32may serve as a source or a drain of the FET10. The interior region/superlattice24serves as the channel of the FET10. It will be appreciated that the FET10will typically also include conductive source and drain contacts, not shown, but which are operably coupled to the first region30and second region32.

The interior region24is surrounded by the insulator layer16, also referred to herein as a dielectric spacer, in a manner not unlike a traditional fin FET. The dielectric spacer16has a top layer16athat extends laterally across (in the x-direction) and adjacent to the top surface of the interior region24, a bottom layer16bthat extends laterally across and adjacent to the bottom surface of the interior region24, and sides16cand16dthat extend down (in the z-direction) and adjacent to opposite sides of the interior region24of the fin22. In this embodiment, the top layer16a, bottom layer16band side layers16c,16dhave uniform thicknesses. As will be discussed below, however, such thicknesses may be varied to achieve desired wave function switching behavior in the FET10.

The first gate18and the second gate20may suitably be formed from metal or from a heavily doped semiconductor material. In this embodiment, the first gate18extends over the top layer16aof the dielectric spacer16, and the second gate20extends over a lower portion of the dielectric spacer16. To this end, the first gate18is an-inverted U-shaped conductive element that extends laterally (in the x-direction) over and against the top layer16aof the dielectric spacer16and partly down each side layer16c,16dof the dielectric spacer16. Similarly, the second gate20is a U-shaped conductive element that extends laterally (in the x-direction) under and against the bottom layer16bof the dielectric spacer16and partly up each side of the dielectric spacer16.

In this embodiment, the upper gate18and the lower gate20have different thicknesses, or at least are configured to provide a non-homogeneous electrostatic potential within the interior region24in a switchable manner. In general, depending on whether a sufficient switching voltage is present on the upper gate18and lower gate20, the dielectric spacer or insulator layer16and the gates18,20are configured to generate an inhomogeneous electrostatic potential within the interior region that cooperates with physical properties of the superlattice24to cause scattering of charge carriers sufficient to change a quantum property of such charge carriers. This change in the quantum property of the charge carriers changes the ability of the charge carriers to move between the first and second materials, e.g. between the layers24a,24b.

Specifically, as discussed above, the two materials of the alternating layers24a,24bhost particles that can propagate and carry a measurable property (e.g. energy, momentum, spin, chirality, being in valence or conduction band etc.) that effectively does not change during the propagation in each respective material of the FET10. As also discussed above, this measurable property (i.e. quantum characteristic) of the particles in the materials of the alternating layers24a,24bhas to differ. As a result, the particles (i.e. charge carriers) have to change this property when they transfer from one layer24ato the other24b(and vice versa). Given that the particles cannot change the property in each layer24a,24balone, the property change has to happen during the transfer between the layers24a,24b. Typically, this change involves scattering on a third particle type. For instance, for electrons or holes, the third particle type can be collective oscillations of atoms (i.e. phonons).

Such scattering is proportional to the overlap of the particle wave functions in each of the two materials (i.e. layers24a,24b). This overlap is switchable between the delocalized and localized wave functions.

An example of this phenomenon is shown inFIGS. 4 and 5. In the example ofFIGS. 4 and 5, the quantum characteristic of the two layers24a,24bis whether the charge carriers are in the conduction band or valence band. In this example, the superlattice of the interior portion24is configured as a type II superlattice, and the switching operation of the FET is based on tunneling, such as in a TFET. However, it will be appreciated that principles of localized and delocalized wave functions discussed below may readily be adapted to other quantum characteristics with proper materials selection and tuning of the electrostatic potential imposed by the gate subjected to an ON voltage.

In particular,FIG. 4shows a graph of the band structure profile (and wave function) in the ON-state of the FET10. The alternating layers24a,24bof the FET10in this TFET example have alternating band offsets which lead to the superlattice Type II typical alternating conduction band profile50, and valence band profile52. In this setting, the electronic states of conduction and valence band form minibands54,56, respectively, that are delocalized over the total extent of the FET in z-direction.

As demonstrated byFIG. 4, the thicknesses of the individual layers24a,24bof the superlattice24define the confinement energies of the valence and conduction band states. The energy of these states determines which states are occupied and therefore contribute to the FET10operation. In the ON state, the energies of all occupied electron states in the conduction band (similar for the hole states in the valence band) lie within an energy window of 25 meV, i.e. they are effectively degenerate within the thermal broadening at room temperature.

Other temperatures require different energy windows (following kBT) that allow them to form minibands in the conduction and valence band (seeFIG. 4). Miniband states are delocalized across the total height of the superlattice24and correspondingly, the overlap between the valence and conduction band wave functions is large (seeFIG. 4). In this situation, tunneling between conduction and valence band is pronounced, due to the strong overlap of wave functions and the resulting strong scattering between them, due to the energy alignment similar to standard FETs, and due to stronger pronounced band tails (compared to nanowires) that are typical of ultrathin body (UTB) configurations. The band tails significantly support tunneling between bands. Also, the density of states in UTB minibands is larger than in nanowires which further boosts the current density in this ON state.

FIG. 5shows the wave function and band profile in the OFF-state of the FET10. The alternating layers24a,24bof the FET10have alternating band offsets which lead to the superlattice Type II typical alternating band profile (60,62inFIG. 5). In this setting, the superlattice structure faces a finite electric field in z-direction that adds to the material-given alternating conduction and valence band profiles. The electronic states of conduction and valence band are localized within individual layers In the OFF state, the energies of electron and hole like states64,66in the conduction and valence band60,62, respectively are separated by more than 25 meV. Then the electrons and holes are confined in individual layers, as shown inFIG. 5.

Since the materials of these layers24a,24bare chosen to be a type II superlattice, the electron and hole wave functions are localized in distinct material layers. This results in a suppressed (OFF) source-drain current density: The small or negligible overlap of electron and hole wave functions makes a direct tunneling between the bands very unlikely. This is part of normal TFET operation. However, this small band-to-band tunneling probability in this embodiment is further reduced due to the fact the layers24a,24beffectively operated as a set of nanowires. In other words, the isolated layers24a,24bof the superlattice24act like nanowires with a reduced density of states and reduced band tails. The smaller density of states can cause less possible current density. The effective band gap of nanowire states is larger than that of the minibands in the UTB-like ON configuration thanks to the enhanced quantum mechanical confinement of nanowires. This again reduces the tunneling current in the OFF state of the FET10.

The switching between minibands (ON state ofFIG. 4) and nanowire-like isolated layer states (OFF state ofFIG. 5) is done with an applied electric field perpendicular to the transport direction, via gates18,20. This mechanism is frequently used in cascade devices, as discussed, for example, in Jirauschek, C. & Kubis, T. Modeling techniques for quantum cascade lasers.Appl. Phys. Rev.1, (2014), and Bai, Y., Slivken, S., Kuboya, S., Darvish, S. R. & Razeghi, M. Quantum cascade lasers that emit more light than heat.Nat. Photonics4, 99 (2010), both of which are incorporated herein by reference.

The respective energy shift of conduction and valence bands of individual layers depends on their relative position within that field in the z-direction. Depending on the desired switching configuration, i.e. whether the ON state is achieved with vanishing or with a finite gate field, the layers24a,24bhave equal (for ON at 0 gate field) or different (for ON at finite gate field) thicknesses and accordingly equal or different confinement energies. In any case, whether the state energies are equal or different in the field free case, the inhomogeneous potential in the z-direction, caused by the configuration of the gate18,20in this embodiment, allows to tune the states to either all match in energy (ON state) or to differ by more than the thermal broadening (OFF state). The conduction and valence minibands of the n-type and p-type materials have to be aligned in the ON state and misaligned in the OFF state to synchronize the cascade switching and the FET switching and benefit from constructive interference of both effects.

Referring again generally toFIGS. 1 to 3, as discussed above, the inhomogeneous electrostatic potential provided by the gates18,20(in the ON state) cooperates with physical properties of the superlattice24to change the overlap of the wave functions of the first and second materials24a,24bin comparison to the absence of the inhomogeneous electrostatic potential (the OFF state), sufficient to change the conductance between the doped first region and the doped second region. In one example, the inhomogeneous electrostatic potential (i.e. from the gate18,20) cooperates with the physical properties of the superlattice24to cause scattering of the charge carriers on phonons. In another embodiment, roughness at boundaries between the layers24a,24bcooperates with the inhomogeneous electrostatic potential to cause scattering of the charge carriers. More specifically, the inhomogeneous electrostatic potential creates delocalization of the wave functions, which in turn cooperates with the rough interfaces to cause scattering.

In yet another embodiment, the impurities in at least one of the first and second layers24a,24bof the superlattice24cooperates with the inhomogeneous electrostatic potential to cause scattering of the charge carriers. More specifically, the inhomogeneous electrostatic potential creates delocalization of the wave functions, which in turn cooperates with the impurities to cause scattering.

The cascade FET10otherwise has some overlapping attributes with known fin FET designs, such as that disclosed in U.S. Patent Application publication no. 2015/0340489, which is incorporated herein by reference. However, the FET has substantial differences from prior art fin FET and other FET designs, including the features described above.

Another example of using scattering of particles to ensure passage between layers of the superlattice24(e.g. when a gate potential is applied) is described in conjunction withFIG. 6.FIG. 6shows a graph of the conduction band minimum as a function of the lateral position between the doped first region30and the doped second region32, with the interface80representing schematically the interfaces within the internal portion24between layers24aand24b. InFIG. 6, the materials are selected such that region30has that conduction band minimum at the F point and region32at the X point. As discussed above, the layers24aare of the same material as the doped first region30, and the layers24bare of the same material as the doped second region32, and thus the interface30includes the vertical transitions between adjacent layers24a,24b.

The electronic property that is changed in the transition between materials of layers24aand24binFIG. 6is the conduction band valley the electrons are located in. The assumption, which is based on the selection of the materials used for layers24a,24b(and regions30,32respectively), is that the material of layer24a/region30has the conduction band minimum in the Gamma point ΓA, whereas the material of layer24b/region32has the Gamma valley ΓBhigher in energy than the X valley XB. The band alignment between the two materials gives a step at the material interface80.

Because of this step function, Gamma electrons of the material of layer24a/region30cannot propagate into the Gamma valley of the material of layer24b/region32due to the potential barrier maintained by the band offset between those two materials. Moreover, the Gamma electrons of the material of layer24a/region30can only enter the lower X valley of the material of layer24b/region32, and hence maintain a finite transistor current, when those Gamma electrons change their momentum during the transition at the interface80. The scattering probability for that momentum change depends on the wave function overlap is therefore subject to the wave function switching similar to that described above in connection withFIGS. 4 and 5.

More specifically,FIG. 7shows a graph of the valley band structure profile of the FET10in the ON state wherein the wave function is delocalized in the layers24a,24b, and thus allows the Gamma electrons to change their momentum via incoherent scattering to move through the boundary80.FIG. 7is thus analogous toFIG. 4of the TFET example.FIG. 7shows a typical alternating gamma valley band profile90, and x valley band profile92. In this setting, the electronic states of gamma valley and x valley bands form minibands94,96, respectively, that are delocalized over the total extent of the FET in z-direction. The delocalized wave functions shown inFIG. 7enhance movement electrons between the layers24a,24b. Note again that the standard FET operation adds to the switching of the device10.

As discussed above, in order to switch the wave functions as shown inFIGS. 4 and 5, an inhomogeneous electrostatic potential must be applied to the layers24a,24bin the ON state, and no electrostatic potential (or some other electrostatic potential) is applied to the layers24a,24bin the off state. To this end, the first gate18and the second gate20have different thicknesses, or at least are configured to provide a non-homogeneous electric field and electrostatic potential within the interior region24when a gate voltage is applied thereto.

Referring to the general operation of the device, the FET10operates to controllably allow current to flow from a source to drain depending on whether a voltage is applied to the first gate18and second gate20. The FET10operates to switchably convey current, in part, like a traditional FET. Thus, in a traditional N-type FET10, the application of a gate voltage greater than a threshold (VG>VTH) to the first gate18and second gate20causes current to flow between the first region30(e.g. source) and the second region32(e.g. drain). When no gate voltage is present (VG=0), then little or no current (e.g. leakage current) flows between the first region30and the second region32. In a P-type FET10, then current flows in the absence of gate voltage (VG=0) and little or no current flows when the gate voltage exceeds a threshold (VG>VTH).

In contrast to a traditional FET, however, the FET10has additional operational features as discussed above. In general, the additional switching mechanisms described above in connection withFIGS. 4 and 5augment the switching mechanism of traditional FET operation. When the gate voltage is applied, the gates18,20expose the superlattice24to an inhomogeneous electrostatic potential. Because of the selection of the first and second materials of the superlattice, the inhomogeneous electrostatic potential changes the wave functions of the charge carriers. The changed wave function is delocalized within the layers24a,24b, which increases the probability of the charge carriers scattering such that the conservation of the quantum characteristics (which are different in charge carriers of the two layers) that would otherwise prevent charge carriers moving between layers is reduced to allow movement between layers24a,24b. This increases current flow from the first region30to the second region32.

At least some advantageous features of the FET10arise from the fact that the FET is inhomogeneous perpendicular to the transport direction, or in other words, the z-direction. As a result, the ON voltage applied to the gate can operate to cause the delocalized wave functions in the superlattice24as illustrated inFIG. 4, which in turn can change the wave function overlap to enhance current flow.

Because the cascade-switching effect of the FET occurs in the superlattice of the interior region24, alternative embodiments may be implemented in which the source and/or drain may include part of all of the superlattice. The superlattice can extend to the doped source and drain regions or alternatively, the source and/or the drain region can consist of the respective homogeneous materials. Similarly, the extent of the doping regions can vary as well.

In still other embodiments, the geometry of the gates18,20and/or the insulator/dielectric16can be varied, so long as they impose an inhomogeneity in the electrostatic potential within the undoped (or lightly doped) region24under the gate18,20(SeeFIG. 2) that switches between the profiles shown inFIGS. 4 and 5. InFIG. 1, the gate is formed of two gate segments18,20having different (i.e. non-symmetrical) geometries. However, the inhomogeneity of the electrostatic potential may be effectuated using a single gate structure having an asymmetrical design and/or a dielectric layer having an asymmetrical design along the vertical dimension. By way of non-limiting example,FIG. 8shows a device110that is the same as the FET10except that the gate118is a single structure that surrounds the interior region24(not shown inFIG. 8) and has a vertically inhomogeneous shape. In this embodiment, the gate118has a thin top layer118a, a thin bottom layer118b, two thicker side layers (one not shown),118d, and chamfered edges between the side layers118dand the top layer118.

In another non-limiting example,FIG. 9shows a FET210that has the same structure as the FET10ofFIG. 1except that both the insulation (dielectric) layer216and the gate218have a non-homogeneous shape. The insulation layer216has wider side and top portions, and chamfered corners between the sides and the top portions. The single piece gate218has an outer perimeter that is rectangular, and an inner perimeter that is conformal to the shape of the insulation layer216. It will be appreciated that in the embodiments described herein, the gate structures are formed directly on the dielectric layers.

FIG. 10shows yet a different embodiment of a FET310which the shape of the fin has been modified to have a trapezoidal shape, forming trapezoidal fin322. The fin322has tapered sides in the first region330, the second region332, and the interior region, not shown, but which has the same layered structure the interior24ofFIGS. 2 and 3, and is disposed under the gate318. The insulation layer316conforms to the trapezoidal shape of the fin322, but has an external perimeter that is the same as the insulation layer16ofFIG. 1. The remaining elements of the FET310are similar to those of the FET10ofFIG. 1. Another way to vary the geometry of the superlattice itself can be to vary the thickness of the individual superlattice layers. Referring toFIG. 1, the thickness of layers24acan differ from each other, and/or the thickness of layers24bcan differ from each other.

As discussed above, the superlattice24can have alternating layers24a,24bof InAs/GaSb, InAs/AlSb, InAs/GaInSb, InAsSb/InSb, InAlN/GaN, AlGaAs/AlAs, AlGaAs/GaAs, ZnSe/ZnTe, SiGe/Si. In addition, alloys of these materials can serve the purpose of this technology as well. It will further be appreciated that 2D material superlattices of various growth orientations can potentially form superlattices. Known 2D materials are all transition metal dichalcogenides, phosphorene, graphene, silicene, germanene, and stanene. Varying their layer symmetry and thickness may allow to tune the band structures of heterojunctions to superlattices having alternate layers with alternate wave functions. Known examples are for type 2 band alignment are MoS2/MoTe2. Even homojunctions can form interlayer (type 2) excitons depending on the material details, as discussed in Wang, K.-C. et al. Control of interlayer physics in 2H transition metal dichalcogenides.J. Appl. Phys.122, 224302 (2017).

The FET10and other FETs described herein may readily be fabricated using known standard transistor fabrication processes. To this end, all of layers of the FET10are aligned with the growth direction (e.g. bottom up). In other words, each layer gets grown on top of the layers underneath. Areas where we want to have a specific material being grown will get defined with inverter masks.

The above-describe embodiments are merely exemplary. Those of ordinary skill in the art may readily devise their own modifications and implementations that incorporate the principles of the present invention and fall within the spirit and scope thereof.