FIELD EFFECT TRANSISTOR WITH BACKSIDE SOURCE/DRAIN

A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

BACKGROUND

The present disclosure relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present disclosure relates to fabrication methods and resulting structures for field effect transistors (FETs) with a backside source/drain (S/D) for complementary metal oxide semiconductor (CMOS) technologies.

In certain semiconductor device fabrication processes, many semiconductor devices, such as n-type field effect transistors (nFETs) and p-type field effect transistors (pFETs), may be fabricated on a single wafer. Non-planar transistor device architectures (e.g., fin-type FETs (FinFETs), gate all around (GAA) FETs, nanowire FETs, nanosheet FETs, or the like) can provide increased device density and increased performance over planar transistors. As semiconductor integrated circuits (ICs) and/or chips become smaller, the implementation of stacked nanostructure channels in semiconductor devices has increased. Nanosheets or nanowires generally refer to two-dimensional nanostructures with a thickness range on the order of about 1 nanometer (nm) to about 100 nm, and they can serve as FET channels and facilitate the fabrication of non-planar semiconductor devices having a reduced footprint compared to conventional planar-type semiconductor devices. For example, nanosheet transistors, in contrast to conventional planar FETs, include a gate stack that wraps around the full perimeter of multiple stacked nanosheet channels for a reduced device footprint and improved control of channel current flow. Nanosheet transistor configurations may enable fuller depletion in the nanosheet channel regions and reduce short-channel effects. Accordingly, nanosheets and nanowires are seen as feasible options for CMOS technology at 3 nm node and beyond.

SUMMARY

In an embodiment of the present disclosure, a semiconductor device is presented. The semiconductor device includes an insulating layer and a transistor upon the insulating layer. The transistor includes one or more channel regions, a first source or drain (S/D) region, and a second S/D region. The first S/D region is located upon the insulating layer and is connected to the one or more channel regions. The second S/D region includes a conduit liner upon the insulating layer. The conduit liner is connected to the one or more regions. The second S/D region further includes an inner column within the conduit liner. The inner column extends below a top surface of the insulating layer.

In an embodiment of the present disclosure, a method of forming a semiconductor device is presented. The method includes forming a first source or drain (S/D) region upon an insulating layer and contacting respective first ends of one or more channel regions. The method further includes forming a second S/D region upon the insulating layer and contacting respective second ends of the one or more channel regions. The method further includes forming a S/D conduit liner by forming an inner opening through the second S/D region. The inner opening extends below an upper surface of the insulating layer. The method further includes forming a S/D inner column within the inner opening.

In an embodiment of the present disclosure, a transistor is presented. The transistor includes a one or more channel regions and one gate around each of the one or more channel regions. The transistor further includes a first source or drain (S/D) region connected to each of the one or more channel regions. The transistor further includes a second S/D region. The second S/D region includes a conduit liner connected to each of the one or more channel regions and an inner column internal to the conduit liner that extends below a bottom surface of the gate.

DETAILED DESCRIPTION

The present disclosure describes nanostructure FET devices, such as a nanosheet GAA FET, and methods of fabrication the FET devices. In particular, the present disclosure describes a nanostructure FET that includes a backside S/D. In certain examples, the backside S/D is associated with an internal epitaxially grown S/D.

The flowcharts and cross-sectional diagrams in the Figures illustrate methods of fabricating FET devices, according to various embodiments. In some alternative implementations, the fabrication steps may occur in a different order that that which is noted in the Figures, and certain additional fabrication steps may be implemented between the steps noted in the Figures. Moreover, any of the layered structures depicted in the Figures may contain multiple sublayers.

Turning now to an overview of technologies that are more specifically relevant to aspects of the present disclosure, a metal-oxide-semiconductor field-effect transistor (MOSFET) may be used for amplifying or switching electronic signals. The MOSFET has a source electrode, a drain electrode, and a metal oxide gate electrode. The metal gate portion of the metal oxide gate electrode is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or high-k dielectric, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the current path from the source to the drain is an open circuit (“off”) or a resistive path (“on”). N-type field effect transistors (nFET) and p-type field effect transistors (pFET) are two types of complementary MOSFETs. The nFET includes n-doped source and drain junctions and uses electrons as the current carriers. The pFET includes p-doped source and drain junctions and uses holes as the current carriers. Complementary metal oxide semiconductor (CMOS) is a technology that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions. As mentioned above, hole mobility on the pFET may have an impact on overall device performance.

The wafer footprint of an FET is related to the electrical conductivity of the channel material. If the channel material has a relatively high conductivity, the FET can be made with a correspondingly smaller wafer footprint. A known method of increasing channel conductivity and decreasing FET size is to form the channel as a nanostructure. For example, a GAA nanosheet FET provides a relatively small FET footprint by forming the channel region as a series of nanosheets. In a known GAA configuration, a nanosheet GAA FET includes a source region, a drain region and stacked nanosheet channels between the source and drain regions. Semiconductor nanosheet FET devices typically include one or more suspended nanosheets that serve as the channel. A gate surrounds the stacked nanosheet channels and regulates electron flow through the nanosheet channels between the source and drain regions. GAA nanosheet FETs are fabricated by forming alternating layers of channel nanosheets and sacrificial nanosheets. The sacrificial nanosheets are released from the channel nanosheets before the FET device is finalized. For n-type FETs, the channel nanosheets are typically silicon (Si) and the sacrificial nanosheets are typically silicon germanium (SiGe). For p-type FETs, the channel nanosheets can be SiGe and the sacrificial nanosheets can be Si. In some implementations, the channel nanosheet of a p-type FET can be SiGe or Si, and the sacrificial nanosheets can be Si or SiGe. Forming the GAA nanosheets from alternating layers of channel nanosheets formed from a first type of semiconductor material (e.g., Si for n-type FETs, and SiGe for p-type FETs) and sacrificial nanosheets formed from a second type of semiconductor material (e.g., SiGe for n-type FETs, and Si for p-type FETs) provides superior channel electrostatics control, which is necessary for continuously scaling gate lengths down to seven (7) nanometer CMOS technology and below.

In certain nanostructure FET devices, it has been difficult to integrate a backside S/D contact to contact the S/D from the backside of the semiconductor device. For example, in known nanostructure FET devices, a sacrificial S/D contact is initially formed prior to forming an associated S/D thereupon. Subsequently, the sacrificial S/D contact, may be removed and replaced with a backside S/D contact. The removal of the sacrificial S/D contact is difficult and increases semiconductor device fabrication complexity. Therefore, it may be desirable to fabricate nanostructure FET structures with a backside S/D and/or an associated backside S/D contact without an associated sacrificial S/D contact.

Referring now to the drawings in which like numerals represent the same or similar elements and initially toFIG.1, this figure depicts a top-down view and cross-sectional views of a semiconductor device100at an intermediate stage of the fabrication process, according to embodiments.

The semiconductor device100may be formed over a substrate structure. The substrate structure may be a bulk-semiconductor substrate. In one example, the bulk-semiconductor substrate may be a silicon-containing material. Illustrative examples of silicon-containing materials suitable for the bulk-semiconductor substrate include, but are not limited to, silicon, silicon germanium, silicon germanium carbide, silicon carbide, polysilicon, epitaxial silicon, amorphous silicon, and multi-layers thereof. Although silicon (Si) is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed, such as, but not limited to, gallium arsenide, gallium nitride, cadmium telluride, zinc selenide, and III-V compound semiconductors and/or II-VI compound semiconductors. III-V compound semiconductors are materials that include at least one element from Group III of the Periodic Table of Elements and at least one element from Group V of the Periodic Table of Elements. II-VI compound semiconductors are materials that include at least one element from Group II of the Periodic Table of Elements and at least one element from Group VI of the Periodic Table of Elements. In another implementation, as depicted, the substrate structure includes a substrate102and an insulator layer104. The substrate102may be comprised of any other suitable material(s) that those listed above and the insulator layer104may be a dielectric layer, such as an oxide, and may be referred to as a buried oxide (BOX) layer. The dielectric layer may be any suitable dielectric, oxide, or the like, and it may electrically isolate the nanostructures from the bottom substrate102.

As shown inFIG.1, after initial fabrication processing, semiconductor device100may include a substrate102, an insulator layer104, a nanosheet stack that includes semiconductor layers108and sacrificial layers106, a sacrificial gate116, a gate hardmask118, a gate spacer120, and inner spacers122.

The insulator layer104may formed on the substrate102. Thus, in various examples, substrate102is provided, insulator layer104is deposited over substrate102, and then the nanosheet stack is formed over the insulator layer104. Alternatively, the initial substrate may be an insulator on substrate, such as a SiGeOI (SiGe on insulator substrate), a SOI (Silicon on insulator substrate, or the like).

The nanosheet stack may be formed by forming alternating sacrificial layers and active semiconductor layers. In certain examples, the first one of the sacrificial layers is initially formed directly on an upper surface of the insulator layer104. In other examples, certain layers may be formed between the upper surface of the insulator layer104and the first one of the sacrificial layers. In an example, the sacrificial layer is composed of silicon-germanium (e.g., SiGe, where the Ge ranges from about 25-40%). Next, an active semiconductor layer is formed on an upper surface of the first one of the sacrificial layers. In an example, the active semiconductor layer is composed of silicon. Several additional layers of the sacrificial layer and the active semiconductor layer are alternately formed. In the example illustrated, there are a total of three sacrificial layers106and three active semiconductor layers108that are alternately formed to form the nanosheet stack. However, it should be appreciated that any suitable number of alternating layers may be formed. Although it is specifically contemplated that the sacrificial layers can be formed from SiGe and that the active semiconductor layers can be formed from Si, it should be understood that any appropriate materials can be used instead, as long as the two semiconductor materials have etch selectivity with respect to one another. As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. The alternating semiconductor materials can be deposited by any appropriate mechanism. It is specifically contemplated that the first and second semiconductor materials (i.e., of the sacrificial layers and the active semiconductor layers) can be epitaxially grown from one another, but alternate deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition, are also contemplated.

In certain embodiments, the sacrificial layers have a vertical thickness ranging, for example, from approximately 3 nm to approximately 20 nm. In certain embodiments, the active semiconductor layers have a vertical thickness ranging, for example, from approximately 3 nm to approximately 10 nm. Although six total layers are associated with the depicted semiconductor structure100, it should be appreciated that the nanosheet stack can include any suitable number of layers. Although the range of 3-20 nm is cited as an example range of thickness, other thickness of these layers may be used. In certain examples, certain of the sacrificial layers or the active semiconductor layers may have different thicknesses relative to one another. Therefore, multiple epitaxial growth processes can be performed to form the alternating sacrificial layers and the active semiconductor layers.

In certain embodiments, it may be desirable to have a small vertical spacing (VSP) between adjacent nanosheet layers in a stack of nanosheets to reduce the parasitic capacitance and to improve circuit speed. For example, the VSP (the distance between the bottom surface of a first nanosheet layer and the top surface of an adjacent second nanosheet layer) may range from 5 nm to 15 nm. However, the VSP must be of a sufficient value to accommodate the gate stack that will be formed in the spaces created by later removal of the sacrificial layers106.

In some implementations, a mask layer (not shown) is formed on the uppermost active semiconductor layer. The mask layer may be comprised of any suitable material(s) known to one of skill in the art. The mask layer is patterned and used to perform the nanosheet patterning process. In the nanosheet patterning process, any suitable material removal process (e.g., reactive ion etching or RIE) may be used to remove the various layers of the nanosheet stack down to the level of the insulator layer104. Following the patterning process to the nanosheet stacks, thereby forming sacrificial layers106and semiconductor layers108, respectively, the mask is removed.

Subsequently, a sacrificial gate116is formed on the sacrificial gate oxide layer by any suitable deposition and/or patterning processes known to one of skill in the art. In one example, the sacrificial gate116is formed by depositing a thin SiO2sacrificial gate oxide layer, followed by depositing a layer of amorphous silicon (a-Si) as the sacrificial gate116. The sacrificial gate116may be composed of polycrystalline silicon (poly silicon), amorphous silicon, and/or an oxide, such as, SiO2. A gate hardmask118is also formed on a top side of the sacrificial gate116. The gate hardmask118is formed for subsequent nanosheet patterning. The gate hardmask118can be composed of various nitride materials including, but not limited to, a nitride, an oxide, silicon nitride (SiN), and/or a combination of a nitride material and an oxide material. In certain embodiments the sacrificial gate116extends into and out of the page to wrap around the edges of the nanosheet stack, and the subsequent removal of the sacrificial gate116allows an access point for later removal of the sacrificial layers. In certain examples, gate patterning may be performed by first patterning the gate hardmask118and then using the patterned gate hardmask118to etch the sacrificial gates116. For clarity, the combined structure of the sacrificial gate116and gate hardmask118may be referred to herein as a sacrificial gate structure121.

Subsequently, spacer120(or spacer layer) is formed on the sidewalls of the patterned sacrificial gate116and the gate hardmask118. In certain examples, the spacer120is also formed over the sacrificial oxide layer.

Subsequently, the semiconductor device100is subjected to a directional reactive ion etch (RIE) process, which can remove portions of the sacrificial layers106not covered by the sacrificial gate116(and the sacrificial gate hardmask118) and the spacer120. The RIE can use a boron-based chemistry or a chlorine-based chemistry, for example, which selectively recesses the exposed portions sacrificial layers106without significantly removing the active semiconductor layers108.

Subsequently, inner spacers122are added in the recesses that were previously formed into the sacrificial layers106. In certain embodiments, after the formation of the inner spacers122, an isotropic etch process is performed to create outer vertical edges to the inner spacers122that align with outer vertical edges of the active semiconductor layers108. In certain embodiments, the material of the inner spacer122is a dielectric material such as SiN, SiO, SiBCN, SiOCN, SiCO, etc.

Referring now toFIG.2, this figure depicts cross-sectional views of the semiconductor device100after additional fabrication operations where source/drain (S/D) regions124are formed over the sidewalls of neighboring nanosheet stacks and over the insulator layer104and where interlayer dielectric (ILD)126is formed over the S/D regions124and over the insulator layer104.

The S/D region124may be formed by epitaxially growing a source/drain epitaxial region within the recess or opening between neighboring nanostructure stacks. In some examples, S/D region124is formed by in-situ doped epitaxial growth. In some embodiments, the S/D region124epitaxial growth may overgrow above the upper surface of the semiconductor device100.

Suitable n-type dopants include but are not limited to phosphorous (P), and suitable p-type dopants include but are not limited to boron (B). The use of an in-situ doping process is merely an example. For instance, one may instead employ an ex-situ process to introduce dopants into the source and drains. Other doping techniques can be used to incorporate dopants in the bottom source/drain region. Dopant techniques include but are not limited to, ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, in-situ epitaxy growth, or any suitable combination of those techniques. In preferred embodiments, the S/D epitaxial growth conditions that promote in-situ Boron doped SiGe for p-type transistor and phosphorus or arsenic doped silicon or Si:C for n-type transistors. The doping concentration in the S/D region124can be in the range of 1×1019cm−3to 2×1021cm−3, or preferably between 2×1020cm−3to 7×1020cm−3.

In certain implementations, the S/D region124may be partially recessed such that an upper portion of the S/D region124are removed. For example, the upper portion of the one or more S/D regions124may be etched or otherwise removed. The etch may be timed or otherwise controlled to stop the removal of the one or more S/D regions124such that the top surface of the remaining one or more S/D regions124is above the upper surface of the topmost active semiconductor layer108.

The ILD126may be formed on the one or more S/D regions124. The ILD126may be formed by depositing a dielectric material, upon S/D regions124and upon insulator layer104. The ILD126can be any suitable material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials. Any known manner of forming the ILD126can be utilized. The ILD126can be formed using, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD.

In an example, the ILD126may be formed to a thickness above the top surface of the semiconductor device100and subsequently etched back such that the top surface of the ILD126is coplanar with a top surface of the sacrificial gate structure121and/or a top surface of spacer(s)120. In another example, another planarization process, such as a CMP, may be performed to create a planar surface for the semiconductor device100.

Referring now toFIG.3, this figure depicts cross-sectional views of the semiconductor device100after additional fabrication operations where a mask140is formed over ILD, over the sacrificial gate structure121and/or over spacer120, mask140is patterned creating an opening therein over a second S/D region124which will be electrically connected to backside of the wafer in subsequent processes. The mask140can be a photolithography mask, hardmask, or the like, and may be composed of various nitride materials including, but not limited to, on OPL, a nitride, an oxide, silicon nitride (SiN), and/or a combination of a nitride material and an oxide material. In certain examples, mask140patterning may be performed by conventional lithography and etch process and then using the patterned gate mask140to etch or remove portions of ILD126, the second S/D region124, and insulator layer104to form backside S/D trench142, as depicted inFIG.4. For clarity, patterning of mask140may form an opening therein with a central axis125that is inline or internal to a perimeter or footprint of the second S/D region124. In one example, as depicted, central axis125may be coincident or substantially coincident with a center axis, bisector, or the like, of the second S/D region124.

Referring now toFIG.4, this figure depicts cross-sectional views of the semiconductor device100after additional fabrication operations where backside S/D trench142is formed through the ILD126, the second S/D124, and insulator layer104generally below the opening within mask140. For example, the etching can include a dry etching process in which one or more chemical etchants are used to remove portions of ILD126, the second S/D124, and insulator layer104that are not protected by the patterned mask140. As shown inFIG.4, in some examples, a perimeter portion of the second S/D region124may be retained. In such examples, retention of perimeter portion of the second S/D region124may result from the type of etching technique utilized, generally resulting in sloped backside S/D trench142sidewalls (as opposed to vertical trench sidewalls). In examples, the top surface of substrate102may be utilized as an etch stop, whereby a portion of the top surface103of substrate102may be exposed by backside S/D trench142. The retained perimeter portion of the second S/D region124may effectively form a conduit liner or hollow structure (e.g., a hollow column, tube, or the like) that is a full 360-degree perimeter or structure or a partial (not a full 360-degree) perimeter or structure (with reference to the top-down view) to the internal hollow recess therein. For clarity, the conduit liner may be the full 360-degree perimeter or structure (with reference to the top-down view) to the internal hollow recess when the backside S/D trench142is vertically aligned with the center of the second S/D region124and when the diameter or width dimension(s) of the S/D trench142are smaller than the associated second S/D region124, respectively. Similarly, the conduit liner may take the form of the partial 360-degree perimeter or structure (with reference to the top-down view) to the internal hollow recess when the backside S/D trench142is misaligned with the center of the second S/D region124and/or when the diameter or width dimension(s) of the S/D trench142is larger than the associated second S/D region124.

It should be appreciated that during the removal of ILD126, the second S/D region124, and insulator layer104, appropriate etchants are used, or other etch parameters are selected, to retain the spacers120, etc. The etching processes can have etching parameters that can be tuned, such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. Dry etching processes can include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses can include Tetrafluoromethane (CF4), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and helium (He), and Chlorine trifluoride (ClF3). Dry etching can also be performed anisotropically using such mechanisms as DRIE (deep reactive-ion etching). Chemical vapor etching can be used as a selective etching method, and the etching gas can include hydrogen chloride (HCl), Tetrafluoromethane (CF4), and gas mixture with hydrogen (H2). Chemical vapor etching can be performed by CVD with suitable pressure and temperature.

Referring now toFIG.5, this figure depicts cross-sectional views of the semiconductor device100after additional fabrication operations where S/D region144is formed within backside S/D trench142. The S/D region144forms either a source or a drain, respectively, to each neighboring nanostructure stacks. The S/D region144may be formed by epitaxially growing a source/drain epitaxial region within the backside S/D trench142. In some examples, S/D region144is formed by in-situ doped epitaxial growth. In some examples, the S/D region144epitaxial growth may overgrow above the upper surface of the second S/D region124. The S/D region144may be the same material relative to the second S/D region124. Alternatively, the S/D region144may be a different material (e.g., different material entirely, different atomic weight of an element of the same material, or the like) relative to the second S/D region124. In some examples, S/D region144may be epitaxially grown from the top surface103of substrate102that is exposed by backside S/D trench142. As such, a bottom surface of S/D region144is generally below a bottom surface of the S/D regions124.

For clarity, as depicted, the second S/D structure may resultantly consist of the conduit liner, perimeter shell, tube, or the like, effectively formed by the second S/D region124with an inner column (S/D region144), therein that, at least, extends below the second S/D region124and may also extend above the second S/D region124. The inner column or S/D region144may directly contact the second S/D region124, such that there is no additional electrical impedance between the S/D region144and the second S/D region124.

In certain implementations, the S/D region144may be partially recessed such that an upper portion of the S/D region144is removed. For example, the upper portion S/D regions144may be etched or otherwise removed. The etch may be timed or otherwise controlled to stop the removal of the S/D regions144such that the top surface of the S/D region144is below the upper surface of the second S/D region124. In these examples, the top surface of S/D region144may still be above the upper surface of the topmost active semiconductor layer108.

Referring now toFIG.6, this figure depicts top-down and cross-sectional views of the semiconductor device100after additional fabrication operations where ILD126is formed within the remaining backside S/D trench142, gate hardmask118is removed, and gate cut150regions are formed within the sacrificial gate116.

The ILD126may be formed within the remaining backside S/D trench142, generally filling the backside S/D trench142. The ILD126may be formed by depositing a dielectric material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials. Any known manner of forming the ILD126can be utilized. The ILD126can be formed using, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD.

Gate hardmask118may be removed by a planarization process, such as a CMP, that results in a planar upper surface for the semiconductor device100. For example, after the planarization process, the top surfaces of spacers120, the top surfaces of sacrificial gates116, and the top surface of ILD126may be coplanar.

Gate cut150regions physically and at least partially electrically separates the gate structure (e.g., electrically and physical separates the sacrificial gates116). Initially, gate cut150regions may be formed by forming a gate cut trench by removing portion(s) of sacrificial gates116, gate spacers120, within the location of the gate cut region stopping at the top surface of isolation layer104or substrate102. The undesired portions of these applicable material(s) may be removed removal techniques such as e.g., depositing and patterning a gate cut mask, lithography, etching, or the like.

Subsequently, gate cut150region is formed within the gate cut trench. Gate cut region150may be a dielectric material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials.

In an example, gate cut150region may be connected to and separate a first gate of a p-type nanostructure GAA FET from a second gate of a n-type nanostructure GAA FET. In another example, gate cut150region may be connected to and separate a first gate of a p-type nanostructure GAA FET from a second gate of a p-type nanostructure GAA FET. In another example, gate cut150region may be connected to and separate a first gate of a n-type nanostructure GAA FET from a second gate of a n-type nanostructure GAA FET.

Referring now toFIG.7, this figure is a cross-sectional view of semiconductor device100after additional fabrication operations where the sacrificial gate116is removed, the sacrificial oxide layer is removed, the sacrificial layers106are removed, and replacement gate structure135is formed in place thereof.

The sacrificial gate116is removed by any suitable material removal process known to one of skill in the art. For example, such removal may be accomplished by an etching process which may include a dry etching process such as, for example, reactive ion etching, plasma etching, ion etching or laser ablation. The etching can further include a wet chemical etching process in which one or more chemical etchants are used to remove portions of the blanket layers that are not protected by the patterned photoresist. Then, the sacrificial layers106are removed (or released). Thus, there are void spaces between the active semiconductor layers108due to the removal of the sacrificial layers106. It should be appreciated that during the removal of the sacrificial gate116, the sacrificial oxide layer, and the sacrificial layers106, appropriate etchants are used that do not significantly remove material of active semiconductor layers108. The dry and wet etching processes can have etching parameters that can be tuned, such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. Dry etching processes can include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses can include Tetrafluoromethane (CF4), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and helium (He), and Chlorine trifluoride (ClF3). Dry etching can also be performed anisotropically using such mechanisms as DRIE (deep reactive-ion etching). Chemical vapor etching can be used as a selective etching method, and the etching gas can include hydrogen chloride (HCl), Tetrafluoromethane (CF4), and gas mixture with hydrogen (H2). Chemical vapor etching can be performed by CVD with suitable pressure and temperature.

Replacement gate structure135may be formed by initially forming an interfacial layer (not shown) on the interior surfaces of the spacer120and the interior surfaces of the active semiconductor layers108and the inner spacers122. Then, a high-K layer (not shown) is formed to cover the surfaces of exposed surfaces of the interfacial layer130. The high-K layer can be deposited by any suitable techniques, such as ALD, CVD, metal-organic CVD (MOCVD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, or other suitable techniques. A high-K dielectric material is a material with a higher dielectric constant than that of SiO2, and can include e.g., LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfSiO, (Ba,Sr)TiO3(BST), Al2O3, Si3N4, oxynitrides (SiON), or other suitable materials. The high-K layer can include a single layer or multiple layers, such as metal layer, liner layer, wetting layer, and adhesion layer. In other embodiments, the high-K layer can include, e.g., Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, or any suitable materials.

Replacement gate structure135may be further formed by depositing a work function metal (WFM) gate134(or replacement gate). The WFM gate134can be comprised of metals, such as, e.g., copper (Cu), cobalt (Co), aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), nitride (N) or any combination thereof. The metal can be deposited by a suitable deposition process, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), plating, thermal or e-beam evaporation, or sputtering. In various exemplary embodiments, the height of the WFM gate134can be reduced by chemical-mechanical polishing (CMP) and/or etching. Therefore, the planarization process can be provided by CMP. Other planarization process can include grinding and polishing. In general, the work function metal (WFM) gate134sets the threshold voltage (Vt) of the device, a high-K gate dielectric material separating the WFM gate134from the nanostructure channel (i.e., active semiconductor layers108), and other metals that may be desired to further fine tune the effective work function (eWF) and/or to achieve a desired resistance value associated with current flow through the gate stack in the direction parallel to the plane of the nanostructure channel.

The ILD126may be formed upon the top surface of the semiconductor device100, as depicted inFIG.7. The ILD126may be formed by depositing a dielectric material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials. Any known manner of forming the ILD126can be utilized. The ILD126can be formed using, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD.

Subsequently, S/D contact160is formed by forming a S/D contact trench within ILD126and depositing conductive material within the S/D contact trench over a first S/D region124.

S/D contact160may consist of a silicide liner, such as Ni, NiPt or Ti, etc, a metal adhesion liner, such as TiN, TaN, etc., and a conductive metal fill, such as Al, Ru, W, Co, Cu, etc. The formation of S/D contact160may include etching the ILD126to form via openings, deposition of material(s), and performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess portions of the conductive barrier layer and the conductive material. Subsequently, the top surface of S/D contact160and the top surface of ILD126may be coplanar. S/D contact160may be formed during middle of the line (MOL) processes.

BEOL structure(s)162include metallization levels, associated metallization dielectric layers, VIAs that connect the metallization feature(s) within the metallization levels with an underlying device or structure, and/or conductive bonding pads, or the like. BEOL structure(s)162include at least a conductive wire, conductive trace, conductive plane, or the like, that is formed over S/D contact160making electrical contact therewith. In some examples, there may be 5 metal levels M0-M4within BEOL structure(s)162. In some examples, there may be more than 10 metal levels M0-Mxwithin BEOL structure(s)162. In some examples, S/D contact160may contact and connect the source or drain (i.e., S/D region124) of the first nanostructure GAA FET to a trace, power plane, or the like located within the lowest metal level M0.

Upon completion of BEOL structure(s)162, carrier wafer164may be bonded or otherwise attached to the top surface or front side of BEOL structure(s)162, as depicted. Carrier wafer164may be attached to semiconductor device100by any carrier bonding technique.

For clarity, semiconductor device100may undergo similar processes, utilized to fabricate S/D contact160, to form a gate contact, such that the gate contact may contact and extend vertically upward from WFM gate134and may connect with a wiring feature within metal levels M0-Mxwithin BEOL structure(s)162.

Referring now toFIG.9, this figure is a cross-sectional view of semiconductor device100after additional fabrication operations where the wafer is flipped for backside processing, and then substrate102is removed. The substrate102may be removed by any removal technique, such as a combination of wafer grinding, CMP, dry and wet etch. Removal of substrate102exposes the bottom surface105of insulator layer104and a bottom surface145of S/D region144.

Referring now toFIG.10, this figure is a cross-sectional view of semiconductor device100after additional fabrication operations, where ILD170is formed upon the exposed bottom surface105of insulator layer104and upon the exposed bottom surface145of S/D region144.

The ILD170may be formed by depositing a dielectric material, upon insulator layer104and upon S/D region144. The ILD170can be any suitable material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials. Any known manner of forming the ILD170can be utilized. The ILD170can be formed using, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD.

Referring now toFIG.11, this figure is a cross-sectional view of semiconductor device100after additional fabrication operations, where S/D contact172is formed.

Backside S/D contact172is formed by forming a S/D contact trench within ILD170and depositing conductive material within the S/D contact trench over a S/D region144. The S/D contact trench may expose the entire bottom surface145of S/D contact144. The S/D contact trench may expose a portion of the bottom surface105of insulator layer104that immediately surrounds the S/D region144(e.g., insulator layer104is used as an etch stop, etc.). S/D contact172may directly contact at least the exposed bottom surface145of S/D region144. Further, S/D region172may directly contact both the exposed bottom surface145of S/D region144and the exposed portion of the bottom surface105of insulator layer104that immediately surrounds the S/D region144.

The backside S/D contact172may consist of a silicide liner, such as Ni, NiPt or Ti, etc., a metal adhesion liner, such as TiN, TaN, etc., and a conductive metal fill, such as Al, Ru, W, Co, Cu, etc. In some examples, S/D contact172may be a contact feature, such as a vertical interconnect access (VIA) to a backside rail180, shown inFIG.12, such as a backside wiring line, backside power plane, or the like. The formation of the backside S/D contact172may include etching the ILD170to form via openings, forming a blanket conductive barrier layer extending into the via openings, depositing a metallic or conductive material over the blanket conductive barrier layer, and performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess portions of the conductive barrier layer and the conductive material. Subsequently, the bottom surface of S/D contact172and the bottom surface of ILD170may be coplanar.

In some examples, the thickness of ILD170may be chosen to achieve a predetermined adequate dimension between the top surface of S/D contact172and WFM gates134to prevent or substantially prevent electrical shorting therebetween.

Referring now toFIG.12, this figure is a cross-sectional view of semiconductor device100after additional fabrication operations, where ILD170is formed (e.g., thickened, etc.), backside rail180is formed, and backside power distribution network (BSPDN)182is formed.

The ILD170may be formed upon the bottom surface of the semiconductor device100, as depicted inFIG.11. The ILD170may be formed by depositing a dielectric material, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials. Any known manner of forming the ILD170can be utilized. The ILD170can be formed using, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD.

Subsequently, backside rail180is formed by forming a backside rail trench within ILD170and depositing conductive material within the backside rail trench over S/D contact172. The backside rail trench may expose the entire bottom surface of S/D contact172and may further create a surface of ILD170that is coplanar with or substantially coplanar with the bottom surface of S/D contact172. Backside rail180may directly contact at least the exposed bottom surface of S/D contact172.

Backside rail180may consist of a metal, such as copper, aluminum, tungsten, cobalt, metal alloys thereof, or the like. In some examples, backside rail180may be a power plane (e.g., VDD power plane, VSS power plane, etc.). Backside rail180may include a conductive region and a conductive barrier layer(s) between the sidewalls and upper surfaces of the conductive regions and the ILD170. The conductive barrier layer(s) may be formed of titanium, titanium nitride, tantalum, tantalum nitride, cobalt, a combination thereof, or the like. The conductive regions may be formed of metals such as copper, aluminum, tungsten, cobalt, alloys thereof, or the like. The formation of backside rail180may include etching the ILD170to form a power plane opening, forming a blanket conductive barrier layer extending into the power plane opening, depositing a metallic or conductive material over the blanket conductive barrier layer, and performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess portions of the conductive barrier layer and the conductive material. Subsequently, the bottom surface of backside rail180and the bottom surface of ILD170may be coplanar. BSPDN182includes known power distribution network features and/or structures to adequately provide power to backside rail180.

For clarity, as depicted, semiconductor device100includes a nanostructure GAA FET with a first region (i.e., source or drain regions such as first S/D region124) and associated S/D contact160upon a top surface of the first source or drain region. The S/D contact160is electrically connected to a BEOL wiring feature generally above the nanostructure GAA FET. The nanostructure GAA FET further includes a second region (i.e., drain or source region such as second S/D region124), associated S/D region144, and associated S/D contact172upon a bottom surface of the associated S/D region144. The S/D contact172is electrically connected to a backside rail180generally below the nanostructure GAA FET.

Alternatively, semiconductor device100includes a nanostructure GAA FET with a first region (i.e., source or drain region such as first S/D region124), associated first S/D region144, and associated first S/D contact172upon a bottom surface of the associated first S/D region144. The first S/D contact172is electrically connected to a first backside rail180generally below the nanostructure GAA FET. The nanostructure GAA FET further includes a second region (i.e., drain or source region such as second S/D region124), associated second S/D region144, and associated second S/D contact172upon a bottom surface of the associated second S/D region144. The second S/D contact172is electrically connected to a second backside rail180generally below the nanostructure GAA FET.

As such, in accordance with the embodiments, semiconductor device includes one or more backside S/D contact(s) (i.e., one or more S/D contact(s)172) that are respectively electrically connected to a backside power rail180and to a S/D region144.

Referring now toFIG.13, this figure is a cross-sectional view of semiconductor device100after alternative fabrication operations where S/D contact172is formed. In this alternative fabrication operation, the S/D contact trench within ILD170may be formed sequentially. For example, an initial S/D contact trench may be formed by etching with an etch stop set at the may the bottom surface of insulator layer104. Next, another etching process may recess S/D region144. The etchant chosen may not be entirely selective to the material of insulator layer104, which may result in some etching of insulator layer104and arced insulator layer104sidewalls173within the S/D contact trench. These sequential etching operations may result in the dimensions of the S/D contact trench at the ILD170and insulator layer104planar intersection being greater than the dimensions of the S/D contact trench at the top of the S/D contact trench (i.e., at the bottom surface of the recessed S/D region144). The arced sidewalls173may have a top-down view radius or diameter that is smallest at the top of the S/D contact172and may increase in relation to the depth of the S/D contact172, as depicted. In this manner, the S/D contact172has a small top-down view radius or diameter upper surface to reduce a likelihood of electrical shorting between the S/D contact172and neighboring WFM gate134with a relatively larger top-down view radius or diameter lower surface to promote metal or conductive material filling of the associated S/D contact trench.

FIG.14depicts a process200of fabricating semiconductor device100that includes a backside S/D contact172, according to embodiments. Process200begins at block202with patterning a nanostructure stack, forming a sacrificial gate structure around the nanostructure stack, forming a gate spacer around the sacrificial gate structure, directionally recessing the sacrificial nanostructure layers of the nanostructure stack that are under the gate spacer, and forming inner spacers within the recesses formed by the directional spacing. The fabrication operations of block202may result in semiconductor device100that includes features or structures as depicted inFIG.1.

At block204, a first S/D region and a second S/D region are formed on either side of the nanostructure stack. For example, a first S/D region124is formed on one sidewall of the nanostructure stack and a second S/D region124is formed on the opposing sidewall of the nanostructure stack. In some examples, ILD126may be formed upon the first S/D region124and the second S/D region124. The fabrication operations of block204may result in semiconductor device100that includes features or structures as depicted inFIG.2.

At block206, a backside opening is formed through the second S/D region. For example, backside S/D trench142is formed from a top surface of the semiconductor device100(i.e., frontside) through ILD126, through the second S/D region124, and through insulator layer104. The fabrication operations of block206may result in semiconductor device100that includes features or structures as depicted inFIG.4.

At block208, a third S/D region is formed within the backside opening through the second S/D region. For example, a S/D region144is formed within backside S/D trench142. The S/D region144may directly contact the inner sidewall(s) of the second S/D region124that are formed by the backside S/D trench142. In some examples, ILD126may be formed upon the S/D region144. The fabrication operations of block208may result in semiconductor device100that includes features or structures as depicted inFIG.5.

At block210, the sacrificial gate structure is removed, the sacrificial nanostructure layers within the nanostructure stack are removed, and the active semiconductor layers (i.e., the nanostructure channels) are exposed. For example, sacrificial gate116is removed, sacrificial layers106are removed, and active semiconductor layers108are exposed. At block212, a replacement gate structure is formed around the nanostructure channels. For example, WMF gate134is formed around the active semiconductor layers108. The fabrication operations of blocks210and212may result in semiconductor device100that includes features or structures as depicted inFIG.7.

At block214, a first S/D contact is formed above or over the first S/D region, BEOL structures are formed over the first S/D contact, and a carrier wafer is attached to the top surface or front side of the semiconductor device100. For example, S/D contact160is formed upon and contacts the top surface of the first S/D region124. BEOL structures162are formed over the S/D contact160, and carrier wafer164is attached. The fabrication operations of block214may result in semiconductor device100that includes features or structures as depicted inFIG.8.

At block216, at least the bottom surface of the third S/D region is exposed from the backside. For example, substrate102may be removed and replaced with ILD170. A backside S/D contact trench may be formed within ILD170that exposes at least the bottom surface of S/D region144. The fabrication operations of block216may result in semiconductor device100that includes features or structures as depicted inFIG.11.

At block218, a second S/D contact is formed below the third S/D region, a backside power rail is formed below the second S/D contact, and/or a BSPSN is formed below the backside power rail. For example, S/D contact172may be formed within the backside S/D contact trench, backside rail180may be formed upon and below the S/D contact172, and BSPDN182may be formed upon and below the backside rail180. The fabrication operations of block218may result in semiconductor device100that includes features or structures as depicted inFIG.12.