Display device and method for fabricating same

In a display region of an active matrix substrate, an interlayer insulating film made of a photosensitive organic insulating film, an insulating film different from the interlayer insulating film, and a plurality of pixel electrodes formed on a surface of the interlayer insulating film are provided. In a non-display region of the active matrix substrate, a lead line extended from the display region is formed. In a formation region for a sealing member, the interlayer insulating film is removed, the insulating film is provided to cover part of the lead line, and the sealing member is formed directly on a surface of the insulating film.

TECHNICAL FIELD

The present invention relates to display devices and methods for fabricating the same.

BACKGROUND ART

In recent years, development in thin display devices such as liquid crystal display devices and organic EL display devices has been rapidly advanced. In many cases, these thin display devices include active matrix substrates on which switching elements each configured to drive associated one of a plurality of pixels are provided to the pixels in order to enhance display quality.

That is, a display device includes the active matrix substrate as described above and a counter substrate disposed to face the active matrix substrate and bonded to the active matrix substrate via a frame-like sealing member. The display device has a display region surrounded by the sealing member and a non-display region around the outer periphery of the display region.

In a region of the active matrix substrate which will serve as the display region, for example, thin film transistors (TFTs) serving as switching elements are each provided to an associated one of a plurality of pixels. The TFTs include a semiconductor layer made of, for example, amorphous silicon (a-Si). Moreover, each pixel includes a pixel electrode connected to the TFT.

On the other hand, in a region of the active matrix substrate which will serve as the non-display region, a plurality of terminals are formed outside the sealing member. External circuits are connected to the plurality of terminals. Moreover, each terminal is formed at an end portion of a lead line extended from the display region.

FIG. 59is an enlarged cross-sectional view illustrating a vicinity of a sealing member of a conventional display device. As illustrated inFIG. 59, a sealing member103is disposed between an active matrix substrate101and a counter substrate102. On the active matrix substrate101, a lead line104is formed in a formation region for the sealing member103. The lead line104is covered with a gate insulating film105and a protection film106so that the lead line104is protected. Moreover, an interlayer insulating film107made of a photosensitive organic insulating film is formed on the gate insulating film105and the protection film106. Although not shown, the interlayer insulating film107is also formed in the display region. On a surface of the interlayer insulating film107in the display region, pixel electrodes are formed. On the other hand, in the formation region for the sealing member103, the sealing member103is formed on the surface of the interlayer insulating film107.

Here, when an active matrix substrate including a plurality of a-Si TFTs formed thereon is fabricated, for example, a process using five masks is known. In the process using five masks, a gate material layer is patterned by using a first mask, and an a-Si layer is patterned by using a second mask. Further, a source material layer is patterned by using a third mask, and a photosensitive organic insulating film is patterned by using a fourth mask. By using the photosensitive organic insulating film as a mask, an insulating film such as a gate insulating film is etched. Then, an indium tin oxide (ITO) film which will serve as a pixel electrode is patterned by using a fifth mask.

Thus, in the formation region for the sealing member, in order to form the gate insulating film and the protection film which protect the lead line, an interlayer insulating film made of the photosensitive organic insulating film has to be left on the gate insulating film and the protection film.

However, in the display device described above, outside moisture permeates via an interface between the sealing member and the interlayer insulating film into a region surrounded by the sealing member (i.e., toward the display region), which leads to a problem where display quality is impaired, thereby reducing display reliability.

To address this problem, Patent Document 1 discloses that in the formation region for the sealing member, a groove is formed in the interlayer insulating film, and the sealing member is formed in the groove and on a surface of the interlayer insulating film at both sides of the groove. This configuration aims to prevent the permeation of moisture via the interface between the sealing member and the interlayer insulating film.

CITATION LIST

Patent Document

PATENT DOCUMENT 1: Japanese Patent Publication No. 2004-53815

SUMMARY OF THE INVENTION

Technical Problem

However, even when the permeation of moisture via the interface between the sealing member and the interlayer insulating film is reduced as in the display device disclosed in Patent Document 1, outside moisture may still permeate into the display region surrounded by the sealing member because the interlayer insulating film itself has moisture permeability.

The present invention was devised in view of the above-discussed problems. It is an objective of the present invention to ensure prevention of permeation of outside moisture into a region surrounded by a sealing member while a lead line is protected in a formation region for the sealing member.

Solution to the Problem

To achieve the objective above, a display device according to the present invention is directed to a display device including: an active matrix substrate; a counter substrate disposed to face the active matrix substrate; and a frame-like sealing member disposed between the active matrix substrate and the counter substrate, a display region being formed within the frame of the sealing member, and a non-display region including a formation region for the sealing member being formed around an outer periphery of the display region.

In the display region of the active matrix substrate, an interlayer insulating film made of a photosensitive organic insulating film, an insulating film different from the interlayer insulating film, and a plurality of pixel electrodes formed on a surface of the interlayer insulating film and arranged in a matrix pattern are provided, in the non-display region of the active matrix substrate, a lead line extended from the display region is formed, and in the formation region for the sealing member, the interlayer insulating film is removed, the insulating film is provided to cover part of the lead line, and the sealing member is directly formed on a surface of the insulating film.

Moreover, a method for fabricating a display device according to the present invention is directed to a method for fabricating a display device by bonding an active matrix substrate to a counter substrate via a frame-like sealing member.

The method includes: forming a first conductive film having a predetermined pattern on a substrate by using a first mask; forming a first insulating film covering the first conductive film on the substrate; forming a semiconductor layer having a predetermined pattern on the first insulating film by using a second mask; forming a second conductive film having a predetermined pattern on the first insulating film by using a third mask; forming an interlayer insulating film made of a photosensitive organic insulating film having a predetermined pattern by using a fourth mask to cover part of the first insulating film on which the semiconductor layer and the second conductive film have been formed; etching part of the first insulating film by using the interlayer insulating film as a mask; forming a transparent electrode having a predetermined pattern on the interlayer insulating film by using a fifth mask, wherein in the forming the first conductive film, part of the first conductive film is formed in a region in which the sealing member is to be formed, in the forming the semiconductor layer, part of the semiconductor layer is formed in the region in which the sealing member is to be formed, in the forming the interlayer insulating film, the interlayer insulating film on the semiconductor layer is removed in the region in which the sealing member is to be formed, in the etching part of the first insulating film, the first insulating film in the region in which the sealing member is to be formed is etched by using the semiconductor layer as a mask, in the forming the transparent electrode, the semiconductor layer in the region in which the sealing member is to be formed is removed by etching simultaneously with the forming the transparent electrode; and providing the sealing member on the first insulating film from which the semiconductor layer has been removed.

Moreover, a method for fabricating a display device according to the present invention is directed to a method for fabricating a display device by bonding an active matrix substrate to a counter substrate via a frame-like sealing member.

The method includes: forming a first conductive film having a predetermined pattern on a substrate by using a first mask; forming a first insulating film covering the first conductive film; forming a semiconductor layer having a predetermined pattern on the first insulating film by using a second mask; forming a second conductive film having a predetermined pattern on the first insulating film by using a third mask; forming an interlayer insulating film made of a photosensitive organic insulating film having a predetermined pattern by using a fourth mask to cover part of the first insulating film on which the semiconductor layer and the second conductive film have been formed; etching part of the first insulating film by using the interlayer insulating film as a mask; forming a common electrode having a predetermined pattern on a surface of the interlayer insulating film by using a fifth mask; forming a second insulating film having a predetermined pattern by using a sixth mask to cover the common electrode; forming a pixel electrode having a predetermined pattern by using a seventh mask on a surface of the second insulating film, wherein in the forming the semiconductor layer, the semiconductor layer is removed in a region in which the sealing member is to be formed, in the etching the part of the first insulating film, the first insulating film on the first conductive film is removed in the region in which the sealing member is to be formed, in forming the second insulating film, part of the second insulating film is formed to cover the first conductive film in the region in which the sealing member is to be formed; and providing the sealing member directly on a surface of the second insulating film in the region in which the sealing member is to be formed.

Advantages of the Invention

According to the present invention, for a display device including an active matrix substrate, a counter substrate disposed to face the active matrix substrate, and a frame-like sealing member disposed between the active matrix substrate and the counter substrate, it is possible to ensure prevention of permeation of outside moisture into a region surrounded by the sealing member while a lead line is protected in a formation region for the sealing member.

DESCRIPTION OF EMBODIMENTS

Embodiments of the present invention will be described in detail below with reference to the drawings. The present invention is not limited to the following embodiments.

First Embodiment of Invention

FIGS. 1-23illustrate a first embodiment of the present invention.

FIG. 1is an enlarged cross-sectional view illustrating a vicinity of a sealing member of a display device of the first embodiment.FIG. 2is a cross-sectional view illustrating a pixel electrode formed by using a fifth mask of the first embodiment.FIG. 3is a cross-sectional view illustrating configurations of a COG terminal section and a FPC terminal section formed by using the fifth mask of the first embodiment.FIG. 4is a cross-sectional view illustrating a configuration of a sealing member formation region of the first embodiment.FIGS. 5-22are cross-sectional views illustrating fabrication processes of the display device of the first embodiment.FIG. 23is a cross-sectional view schematically illustrating a configuration of a liquid crystal display device of the first embodiment.

In the first embodiment, a liquid crystal display device will be described as an example of the display device according to the present invention. As illustrated inFIG. 23, a liquid crystal display device1includes a TFT substrate11serving as an active matrix substrate, a counter substrate12disposed to face the TFT substrate11, and a frame-like sealing member13disposed between the TFT substrate11and the counter substrate. Between the TFT substrate11and the counter substrate12, a liquid crystal layer14is disposed and sealed by the sealing member13.

A display region15is formed within the frame of the sealing member13, and a non-display region16including a formation region20for the sealing member13is formed around the outer periphery of the display region15. In the display region15, a plurality of pixels each of which is a unit of display are formed in a matrix pattern.

At a side of the TFT substrate11opposite to the counter substrate12, a backlight unit (not shown) serving as an illuminating device is disposed. The liquid crystal display device1is configured to selectively transmit light of the backlight unit therethrough to provide transmissive display.

As illustrated inFIG. 1, the counter substrate12includes a glass substrate21serving as a transparent substrate, and the glass substrate21includes a counter electrode22formed on a surface facing TFT substrate11. The counter electrode22is formed from a transparent conductive film made of, for example, ITO.

As illustrated inFIGS. 2-4, the TFT substrate11includes a glass substrate30serving as a transparent substrate, and in the display region15, TFTs31, auxiliary capacitor sections32, connection sections33, COG terminal sections34, and FPC terminal sections35are formed on the glass substrate30.

Moreover, in the display region15of the TFT substrate11, an interlayer insulating film42made of a photosensitive organic insulating film, a gate insulating film38which is an insulating film different from the interlayer insulating film42, and a plurality of pixel electrodes43formed on a surface of the interlayer insulating film42and arranged in a matrix pattern are provided, wherein each of the pixel electrodes43is connected to a different one of the plurality of thin film transistor sections (TFTs)31. The gate insulating film38is formed from an inorganic insulating film made of, for example, silicon nitride. Moreover, the pixel electrodes43are formed from a transparent conductive film made of, for example, ITO.

On the other hand, as illustrated inFIGS. 1 and 4, a lead line44extended from the display region15is formed in the non-display region16of the TFT substrate11. In the formation region20for the sealing member13, the interlayer insulating film42is removed, the gate insulating film38is disposed to cover part of the lead line44, and the sealing member13is formed directly on a surface of the gate insulating film38.

Each TFT31includes a gate electrode37formed on the glass substrate30, the gate insulating film38covering the gate electrode37, a semiconductor layer39formed on the surface of the gate insulating film38, and drain and source electrodes40covering part of the semiconductor layer39. The drain and source electrodes40are covered with a protection film41and the interlayer insulating film42. The protection film41is formed from an inorganic insulating film made of, for example, silicon nitride.

The semiconductor layer39is made of an oxide semiconductor, for example, In—Ga—Zn—O (IGZO). Such an oxide semiconductor includes highly ionic bonds, and a difference in electron mobility between crystalline and amorphous substances is small. Thus, relatively high electron mobility is obtained even in an amorphous state. Moreover, the advantage that an amorphous film can be easily formed by, for example, sputtering at a room temperature is also provided.

As illustrated inFIG. 2, each auxiliary capacitor section32includes a first electrode48and a second electrode47facing each other with the gate insulating film38provided therebetween. The first electrode48is made of a gate material, and is formed on the glass substrate30. The second electrode47is made of a source material, and is formed on the surface of the gate insulating film38. Moreover, the second electrode47is connected to the pixel electrode43via a contact hole45penetrating the protection film41and the interlayer insulating film42.

Each connection section33includes a connect layer51connecting a gate material layer49to a source material layer50. The gate material layer49is formed on the glass substrate30. The source material layer50is formed on the surface of the gate insulating film38. The connect layer51is made of ITO, and is formed in a contact hole52penetrating the protection film41and the interlayer insulating film42.

As illustrated inFIG. 3, each of the COG terminal sections34and the FPC terminal sections35includes a gate material layer55formed on the glass substrate30, a semiconductor material layer56, and an ITO layer57. The semiconductor material layer56is formed on the surface of the gate insulating film38. The ITO layer57is formed on a surface of the semiconductor material layer56, and is connected to the gate material layer55via a contact hole58formed to penetrate the gate insulating film38.

Next, a method for fabricating the liquid crystal display device1will be described.

The liquid crystal display device1is fabricated by bonding the TFT substrate11to the counter substrate12via the frame-like sealing member13. The present invention has a particular feature in a step of fabricating the TFT substrate11, and thus the step of fabricating the TFT substrate11will be described in detail.

(Step of Forming Gate Material Layer)

First, by using a first mask, a gate material layer37,44,48,49,55which is a first conductive film having a predetermined pattern is formed on the glass substrate30by photolithography. The gate material layer37,44,48,49,55has a layered structure composed of, for example, an Al layer, a Ti layer, and a TiN layer.

That is, as illustrated inFIG. 5, on the glass substrate30, a gate electrode37is formed in a formation region for the TFT31. Moreover, a first electrode48is formed in a formation region for an auxiliary capacitor section32, and a gate material layer49is formed in a formation region for a connection section33. Further, as illustrated inFIG. 6, a gate material layer55is formed in formation regions for a COG terminal section34and a FPC terminal section35. Furthermore, as illustrated inFIG. 7, part of the gate material layer37,44,47,49,55forms a lead line44in a region20in which the sealing member13is to be formed.

(Step of Forming Gate Insulating Film)

Next, as illustrated inFIGS. 8-10, a gate insulating film38as a first insulating film covering the gate material layer (the gate electrode37, the first electrode48, the gate material layer49,55, the lead line44) is formed on the glass substrate30.

(Step of Forming Semiconductor Layer)

Next, as illustrated inFIGS. 8-10, by using a second mask, a semiconductor layer39,56,60having a predetermined pattern is formed on the gate insulating film38by photolithography.

That is, a semiconductor layer39is formed in the formation region for the TFT31, and a semiconductor material layer56is formed in the formation regions for the COG terminal section34and the FPC terminal section35. Moreover, a semiconductor layer60which is part of the semiconductor layer39,56,60is formed in the region in which the sealing member13is to be formed. The semiconductor layer39,56,60is made of an oxide semiconductor, for example, IGZO.

(Step of Forming Source Material Layer)

Next, as illustrated inFIGS. 11-13, by using a third mask, a source material layer40,47,50which is a second conductive film having a predetermined pattern is formed on the gate insulating film38by photolithography. The source material layer40,47,50has, for example, a layered structure composed of a Ti layer, a MoN layer, an Al layer, and a MoN layer, a layered structure composed of a Ti layer, an Al layer, and a Ti layer, or a layered structure composed of a Cu layer, a Ti layer, a Cu layer, and a Mo layer.

That is, drain and source electrodes40are formed in the formation region for the TFT31, a second electrode47is formed in the formation region for the auxiliary capacitor section32, and a source material layer50is formed in the formation region for the connection section33.

Next, as illustrated inFIGS. 14-16, by using a fourth mask, an interlayer insulating film42having a predetermined pattern is formed by photolithography to cover part of the gate insulating film38on which the semiconductor layer39,56,60and the source material layer40,47,50have been formed. The interlayer insulating film42is formed from a photosensitive organic insulating film made of, for example, an acrylic organic resin.

That is, a material layer of a protection film41and a material layer of the interlayer insulating film42are stacked in this order on the entire surface of the glass substrate30including the region20in which the sealing member13is to be formed. The protection film41is formed from an inorganic insulating film made of, for example, silicon nitride. After that, by photolithography by using the fourth mask, the material layer of the interlayer insulating film42is removed in the region20in which the sealing member13is to be formed and in the regions in which the COG terminal section34and the FPC terminal section35are to be formed, a contact hole45is formed in the region in which the auxiliary capacitor section32is to be formed, and a contact hole52is formed in the region in which the connection section33is to be formed. In this way, the interlayer insulating film42on the semiconductor layer60is removed in the region20in which the sealing member13is to be formed.

(Step of Etching Gate Insulating Film)

Then, as illustrated inFIGS. 17-19, part of the gate insulating film38is etched by using the interlayer insulating film42as a mask. Here, the protection film41is also etched simultaneously with the gate insulating film38.

As illustrated inFIG. 17, in the region in which the auxiliary capacitor section32is to be formed, the protection film41is etched in the contact hole45, and in the region in which the connection section33is to be formed, the protection film41and the gate insulating film38are etched in the contact hole52. Moreover, as illustrated inFIG. 18, in the regions in which the COG terminal section34and the FPC terminal section35are to be formed, the protection film41is removed, and the gate insulating film38exposed from the semiconductor material layer56is etched. Moreover, as illustrated inFIG. 19, in the region20in which the sealing member13is to be formed, the protection film41is removed, and the gate insulating film38exposed from the semiconductor layer60is etched.

As described above, in this step, in addition to the interlayer insulating film42, the semiconductor layer60and the semiconductor material layer56can be used as a mask to etch the gate insulating film38.

(Step of Forming Transparent Electrode)

Next, as illustrated inFIGS. 20-22, a transparent conductive layer62made of, for example, ITO is formed over the entire surface of the glass substrate30.

Subsequently, as illustrated inFIGS. 2-4, by using a fifth mask, photolithography is performed on the transparent conductive layer62, thereby forming a pixel electrode43as a transparent electrode having a predetermined pattern and a connect layer51on the interlayer insulating film42.

That is, as illustrated inFIG. 2, the pixel electrode43is formed in the formation region for the TFT31and the formation region for the auxiliary capacitor section32, and the connect layer51is formed in the formation region for the connection section33. Moreover, an ITO layer57is formed in the formation regions for the COG terminal section34and the FPC terminal section35.

In this step, etching is performed by using an etchant containing, for example, oxalic acid, salt iron, etc. Thus, the semiconductor layer60in the region20in which the sealing member13is to be formed can be removed by etching simultaneously with the formation of the pixel electrode43. Moreover, in the formation region for the COG terminal section34, the semiconductor material layer56and the transparent conductive layer62can be simultaneously etched to separate adjacent terminals from each other. Thus, the TFT substrate11is fabricated.

(Step of Forming Sealing Member)

Next, in the formation region20in which the sealing member13is to be formed and in which the semiconductor layer60has been removed, the sealing member13is provided on the gate insulating film38. Here, the sealing member13is provided directly on the surface of the gate insulating film38. Within the frame of the sealing member13, a liquid crystal material is supplied by dropping, and then the TFT substrate11is bonded to the counter substrate12via the sealing member13and the liquid crystal layer14. Thus, the liquid crystal display device1is fabricated.

—Advantages of First Embodiment—

Thus, according to the first embodiment, the lead line44can be protected by being covered with the gate insulating film38in the formation region20for the sealing member13, and additionally, it is possible to ensure the prevention of the permeation of outer moisture into the region surrounded by the sealing member13because the interlayer insulating film42having moisture permeability is removed from the formation region20for the sealing member13. Additionally, in etching the transparent conductive layer62, the semiconductor layer60, which is provided to leave the gate insulating film38in the formation region20for the sealing member13, can be removed simultaneously with the transparent conductive layer62. Thus, an increase in the number of steps can be avoided. As a result, a reduction in display quality can be prevented while fabrication costs are reduced.

Second Embodiment of Invention

FIGS. 24-36illustrate a second embodiment of the present invention. In the following embodiments, the same reference numerals as those shown inFIGS. 1-23are used to represent equivalent elements, and the detailed explanation thereof will be omitted in some cases.

FIG. 24is an enlarged cross-sectional view illustrating a vicinity of a sealing member of a display device of the second embodiment.FIG. 25is a cross-sectional view illustrating a pixel electrode formed by using a seventh mask of the second embodiment.FIG. 26is a cross-sectional view illustrating configurations of a COG terminal section and a FPC terminal section formed by using the seventh mask of the second embodiment.FIG. 27is a cross-sectional view illustrating a configuration of a sealing member formation region of the second embodiment.FIGS. 28-36are cross-sectional views illustrating fabrication processes of the display device of the second embodiment.

As illustrated inFIGS. 24 and 27, a liquid crystal display device1of the second embodiment includes an lead line44, wherein in a formation region20for a sealing member13, the lead line44is covered with an insulating film38,67including a gate insulating film38and a second protection film67formed on a surface of the gate insulating film38. The sealing member13is formed directly on a surface of the second protection film67.

Moreover, as illustrated inFIG. 25, a TFT substrate11of the second embodiment includes a common electrode65and a pixel electrode43serving as transparent electrodes made of, for example, ITO formed on an interlayer insulating film42. That is, the common electrode65is formed on a surface of the interlayer insulating film42, and the common electrode is covered with the second protection film67. Moreover, the pixel electrode43is formed on the surface of the second protection film67. In this way, capacitance is provided by the pixel electrode43and the common electrode65with a high aperture ratio being maintained.

Moreover, in a formation region for a connection section33, a first connect layer66made of the same ITO material as the common electrode65is formed in a contact hole52. In the contact hole52the first connect layer66is covered with the second protection film67and a second connect layer68made of the same ITO material as the pixel electrode43. Moreover, in formation regions for a COG terminal section34and a FPC terminal section35, an ITO layer69is disposed between a semiconductor material layer56and an ITO layer57.

Next, a method for fabricating the liquid crystal display device1will be described.

The liquid crystal display device1is fabricated by bonding the TFT substrate11to a counter substrate12via the frame-like sealing member13. The present invention has a particular feature in a step of fabricating the TFT substrate11, and thus the step of fabricating the TFT substrate11will be described in detail.

First, in a similar manner as in the first embodiment, a step of forming a gate material layer, a step of forming a gate insulating film, a step of forming a semiconductor layer, a step of forming a source material layer, a step of forming an interlayer insulating film, and a step of etching the gate insulating film are performed.

(Step of Forming Gate Material Layer)

First, as illustrated inFIGS. 5-7, by using a first mask, a gate material layer37,44,48,49,55which is a first conductive film having a predetermined pattern is formed on a glass substrate30by photolithography. The gate material layer37,44,48,49,55has a layered structure composed of, for example, an Al layer, a Ti layer, and a TiN layer.

That is, as illustrated inFIG. 5, on the glass substrate30, a gate electrode37is formed in a formation region for a TFT31. Moreover, a first electrode48is formed in a formation region for an auxiliary capacitor section32, and a gate material layer49is formed in a formation region for a connection section33. Further, as illustrated inFIG. 6, a gate material layer55is formed in formation regions for a COG terminal section34and a FPC terminal section35. Furthermore, as illustrated inFIG. 7, part of the gate material layer37,44,48,49,55forms a lead line44in a region20in which the sealing member13is to be formed.

(Step of Forming Gate Insulating Film)

Next, as illustrated inFIGS. 8-10, a gate insulating film38as a first insulating film covering the gate material layer (the gate electrode37, the first electrode48, the gate material layer49,55, the lead line44) is formed on the glass substrate30.

(Step of Forming Semiconductor Layer)

Next, as illustrated inFIGS. 8-10, by using a second mask, a semiconductor layer39,56,60having a predetermined pattern is formed on the gate insulating film38by photolithography.

That is, a semiconductor layer39is formed in the formation region for the TFT31, and the semiconductor material layer56is formed in the formation regions for the COG terminal section34and the FPC terminal section35. Moreover, a semiconductor layer60which is part of the semiconductor layer39,56,60is formed in the region in which the sealing member13is to be formed. The semiconductor layer39,56,60is made of an oxide semiconductor, for example, IGZO.

(Step of Forming Source Material Layer)

Next, as illustrated inFIGS. 11-13, by using a third mask, a source material layer40,47,50which is a second conductive film having a predetermined pattern is formed on the gate insulating film38by photolithography. The source material layer40,47,50has, for example, a layered structure composed of a Ti layer, a MoN layer, an Al layer, and a MoN layer, a layered structure composed of a Ti layer, an Al layer, and a Ti layer, or a layered structure composed of a Cu layer, a Ti layer, a Cu layer, and a Mo layer.

That is, drain and source electrodes40are formed in the formation region for the TFT31, a second electrode47is formed in the formation region for the auxiliary capacitor section32, and a source material layer50is formed in the formation region for the connection section33.

Next, as illustrated inFIGS. 14-16, by using a fourth mask, an interlayer insulating film42having a predetermined pattern is formed by photolithography to cover part of the gate insulating film38on which the semiconductor layer39,56,60and the source material layer40,47,50have been formed. The interlayer insulating film42is formed from a photosensitive organic insulating film made of, for example, an acrylic organic resin.

That is, a material layer of a protection film41and a material layer of the interlayer insulating film42are stacked in this order over the entire surface of the glass substrate30including the region20in which the sealing member13is to be formed. The protection film41is formed from an inorganic insulating film made of, for example, silicon nitride. After that, by photolithography by using the fourth mask, the material layer of the interlayer insulating film42is removed in the region20in which the sealing member13is to be formed and the regions in which the COG terminal section34and the FPC terminal section35are to be formed, a contact hole45is formed in the region in which the auxiliary capacitor section32is to be formed, and a contact hole52is formed in the region in which the connection section33is formed. In this way, the interlayer insulating film42on the semiconductor layer60is removed in the region20in which the sealing member13is to be formed.

(Step of Etching Gate Insulating Film)

Then, as illustrated inFIGS. 17-19, part of the gate insulating film38is etched by using the interlayer insulating film42as a mask. Here, the protection film41is also etched simultaneously with the gate insulating film38.

As illustrated inFIG. 17, in the region in which the auxiliary capacitor section32is to be formed, the protection film41is etched in the contact hole45, and in the region in which the connection section33is to be formed, the protection film41and the gate insulating film38are etched in the contact hole52. Moreover, as illustrated inFIG. 18, in the regions in which the COG terminal section34and the FPC terminal section35are to be formed, the protection film41is removed, and the gate insulating film38exposed from the semiconductor material layer56is etched. Moreover, as illustrated inFIG. 19, in the region20in which the sealing member13is to be formed, the protection film41is removed, and the gate insulating film38exposed from the semiconductor layer60is etched.

As described above, in this step, in addition to the interlayer insulating film42, the semiconductor layer60and the semiconductor material layer56can be used as a mask to etch the gate insulating film38.

(Step of Forming Transparent Electrode)

This step and subsequent steps of the second embodiment are different from those of the first embodiment.

As illustrated inFIGS. 28-30, a transparent conductive layer72made of, for example, ITO is formed over the entire surface of the glass substrate30.

Subsequently, as illustrated inFIGS. 31-33, by using a fifth mask, photolithography is performed on the transparent conductive layer72, thereby forming a common electrode65as a transparent electrode having a predetermined pattern and a first connect layer66on the interlayer insulating film42.

That is, as illustrated inFIG. 31, the common electrode65is formed in the formation region for the TFT31and the formation region for the auxiliary capacitor section32, and the first connect layer66is formed in the formation region for the connection section33. Moreover, an ITO layer69is formed in the formation regions for the COG terminal section34and the FPC terminal section35.

In this step, etching is performed by using an etchant containing, for example, oxalic acid, salt iron, etc. Thus, the semiconductor layer60in the region20in which the sealing member13is to be formed can be removed by etching simultaneously with the formation of the common electrode65. Moreover, in the formation region for the COG terminal section34, the semiconductor material layer56and the transparent conductive layer72can be simultaneously etched to separate adjacent terminals from each other.

(Step of Forming Second Protection Film)

Next, as illustrated inFIGS. 34-36, by using a sixth mask, a second protection film67serving as a second insulating film having a predetermined pattern is formed to cover the common electrode65.

That is, as illustrated inFIG. 34, the second protection film67covering the common electrode65is formed in the formation region for the TFT31and the formation region for the auxiliary capacitor section32. In the contact hole45, the first electrode48is exposed from the second protection film67. On the other hand, in the contact hole52, the first connect layer66is covered with the second protection film67. Moreover, as illustrated inFIG. 35, the second protection film67is removed in the formation regions for the COG terminal section34and the FPC terminal section35.

In this step, in the region20in which the sealing member13is to be formed, part of the second protection film67is formed on the gate insulating film38. That is, as illustrated inFIG. 36, in the formation region20for the sealing member13, the second protection film67is stacked on the surface of the gate insulating film38.

(Step of Forming Pixel Electrode)

Next, as illustrated inFIGS. 25-27, by using a seventh mask, a pixel electrode43having a predetermined pattern is formed on the surface of the second protection film67.

That is, as illustrated inFIG. 25, the pixel electrode43is formed in the formation region for the TFT31and the formation region for the auxiliary capacitor section32, and a second connect layer68is formed in the formation region for the connection section33. As a result, the pixel electrode43is connected to the first electrode48in the contact hole45. Moreover, an ITO layer57is formed in the formation regions for the COG terminal section34and the FPC terminal section35. Thus, the TFT substrate11is fabricated.

(Step of Forming Sealing Member)

Next, in the formation region20in which the sealing member13is to be formed and in which the semiconductor layer60has been removed, the sealing member13is provided on the gate insulating film38and the second protection film67. Here, the sealing member13is provided directly on the surface of the second protection film67. Within the frame of the sealing member13, a liquid crystal material is supplied by dropping, and then the TFT substrate11is bonded to the counter substrate12via the sealing member13and the liquid crystal layer14. Thus, the liquid crystal display device1is fabricated.

—Advantages of Second Embodiment—

Thus, according to the second embodiment, the lead line44can be protected by being covered with the gate insulating film38and the second protection film67in the formation region20for the sealing member13, and additionally, it is possible to ensure the prevention of the permeation of outer moisture into the region surrounded by the sealing member13because the interlayer insulating film42having moisture permeability is removed from the formation region20for the sealing member13. Additionally, in etching the transparent conductive layer72, the semiconductor layer60, which is provided to leave the gate insulating film38in the formation region20for the sealing member13, can be removed simultaneously with the transparent conductive layer72in etching the transparent conductive layer72. Thus, an increase in the number of steps can be avoided. As a result, a reduction in display quality can be prevented while fabrication costs are reduced.

Additionally, since the transparent common electrode65facing the pixel electrode43is formed, capacitance is provided by the pixel electrode43and the common electrode65, allowing the display quality to be further improved while the aperture ratio is increased.

Third Embodiment of Invention

FIGS. 37-58illustrate a third embodiment of the present invention.

FIG. 37is an enlarged cross-sectional view illustrating a vicinity of a sealing member of a display device of the third embodiment.FIG. 38is a cross-sectional view illustrating a pixel electrode formed by using a seventh mask of the third embodiment.FIG. 39is a cross-sectional view illustrating configurations of a COG terminal section and a FPC terminal section formed by using the seventh mask of the third embodiment.FIG. 40is a cross-sectional view illustrating a configuration of a sealing member formation region of the third embodiment.FIGS. 41-58are cross-sectional views illustrating fabrication processes of the display device of the third embodiment.

As illustrated inFIGS. 37 and 40, a liquid crystal display device1of the third embodiment includes a lead line44formed directly on a surface of a second protection film67in a formation region20for a sealing member13with a gate insulating film38being removed.

Moreover, as illustrated inFIG. 38, a TFT substrate11of the third embodiment includes a common electrode65and a pixel electrode43serving as transparent electrodes made of, for example, ITO, formed on an interlayer insulating film42. That is, the common electrode65is formed on a surface of the interlayer insulating film42, and the common electrode is covered with the second protection film67. Moreover, the pixel electrode43is formed on the surface of the second protection film67. In this way, capacitance is provided by the pixel electrode43and common electrode65with a high aperture ratio being maintained.

Moreover, in a formation region for a connection section33, a first connect layer66made of the same ITO material as the common electrode65is formed in a contact hole52. In the contact hole52, the first connect layer66is covered with the second protection film67and a second connect layer68made of the same ITO material as the pixel electrode43.

Moreover, in formation regions for a COG terminal section34and a FPC terminal section35, an ITO layer69is disposed between a semiconductor material layer56and an ITO layer57.

Next, a method for fabricating the liquid crystal display device1will be described.

The liquid crystal display device1is fabricated by bonding the TFT substrate11to a counter substrate12via the frame-like sealing member13. The present invention has a particular feature in a step of fabricating the TFT substrate11, and thus the step of fabricating the TFT substrate11will be described in detail.

(Step of Forming Gate Material Layer)

First, as illustrated inFIGS. 5-7, by using a first mask, a gate material layer37,44,48,49,55which is a first conductive film having a predetermined pattern is formed on a glass substrate30by photolithography. The gate material layer37,44,48,49,55has a layered structure composed of, for example, an Al layer, a Ti layer, and a TiN layer.

That is, as illustrated inFIG. 5, on the glass substrate30, a gate electrode37is formed in a formation region for a TFT31. Moreover, a first electrode48is formed in a formation region for an auxiliary capacitor section32, and a gate material layer49is formed in a formation region for a connection section33. Further, as illustrated inFIG. 6, a gate material layer55is formed in formation regions for a COG terminal section34and a FPC terminal section35. Furthermore, as illustrated inFIG. 7, part of the gate material layer37,44,48,49,55forms a lead line44in a region20in which the sealing member13is to be formed.

(Step of Forming Gate Insulating Film)

Next, as illustrated inFIGS. 41-43, a gate insulating film38as a first insulating film covering the gate material layer (the gate electrode37, the first electrode48, the gate material layer49,55, the lead line44) is formed on the glass substrate30.

(Step of Forming Semiconductor Layer)

Next, as illustrated inFIGS. 41-43, by using a second mask, a semiconductor layer39,56having a predetermined pattern is formed on the gate insulating film38by photolithography.

That is, a semiconductor layer39is formed in the formation region for the TFT31, and a semiconductor material layer56is formed in the formation regions for the COG terminal section34and the FPC terminal section35. The semiconductor layer39,56,60is made of an oxide semiconductor, for example, IGZO. On the other hand, in the region in which the sealing member13is to be formed, a semiconductor layer corresponding to the semiconductor layer60in the first and second embodiments is removed to expose the gate insulating film38.

(Step of Forming Source Material Layer)

Next, as illustrated inFIGS. 44-46, by using a third mask, a source material layer40,47,50which is a second conductive film having a predetermined pattern is formed on the gate insulating film38by photolithography. The source material layer40,47,50has, for example, a layered structure composed of a Ti layer, a MoN layer, an Al layer, and a MoN layer, a layered structure composed of a Ti layer, an Al layer, and a Ti layer, or a layered structure composed of a Cu layer, a Ti layer, a Cu layer, and a Mo layer.

That is, drain and source electrodes40are formed in the formation region for the TFT31, a second electrode47is formed in the formation region for the auxiliary capacitor section32, and a source material layer50is formed in the formation region for the connection section33.

Next, as illustrated inFIGS. 47-49, by using a fourth mask, an interlayer insulating film42having a predetermined pattern is formed by photolithography to cover part of the gate insulating film38on which the semiconductor layer39,56and the source material layer40,47,50have been formed. The interlayer insulating film42is formed from a photosensitive organic insulating film made of, for example, an acrylic organic resin.

That is, a material layer of a protection film41and a material layer of the interlayer insulating film42are stacked in this order over the entire surface of the glass substrate30including the region20in which the sealing member13is to be formed. The protection film41is formed from an inorganic insulating film made of, for example, silicon nitride. After that, by photolithography by using the fourth mask, the material layer of the interlayer insulating film42is removed in the region20in which the sealing member13is to be formed and the regions in which the COG terminal section34and the FPC terminal section35are to be formed, a contact hole45is formed in the region in which the auxiliary capacitor section32is to be formed, and a contact hole52is formed in the region in which the connection section33is formed. In this way, the interlayer insulating film42on the semiconductor layer60is removed in the region20in which the sealing member13is to be formed.

(Step of Etching Gate Insulating Film)

Then, as illustrated inFIGS. 50-52, part of the gate insulating film38is etched by using the interlayer insulating film42as a mask. Here, the protection film41is also etched simultaneously with the gate insulating film38.

As illustrated inFIG. 50, in the region in which the auxiliary capacitor section32is to be formed, the protection film41is etched in the contact hole45, and in the region in which the connection section33is to be formed, the protection film41and the gate insulating film38are etched in the contact hole52. Moreover, as illustrated inFIG. 51, in the regions in which the COG terminal section34and the FPC terminal section35are to be formed, the protection film41is removed, and the gate insulating film38exposed from the semiconductor material layer56is etched. Moreover, as illustrated inFIG. 52, in the region20in which the sealing member13is to be formed, the gate insulating film38and the protection film41on the lead line44is removed by etching.

As described above, in this step, in addition to the interlayer insulating film42, the semiconductor layer60and the semiconductor material layer56can be used as a mask to etch the gate insulating film38.

(Step of Forming Transparent Electrode)

Next, as illustrated inFIGS. 28-30, a transparent conductive layer72made of, for example, ITO is formed over the entire surface of the glass substrate30.

Subsequently, as illustrated inFIGS. 53-55, by using a fifth mask, photolithography is performed on the transparent conductive layer72, thereby forming a common electrode65as a transparent electrode having a predetermined pattern and a first connect layer66on the interlayer insulating film42.

That is, as illustrated inFIG. 53, the common electrode65is formed in the formation region for the TFT31and the formation region for the auxiliary capacitor section32, and the first connect layer66is formed in the formation region for the connection section33. Moreover, an ITO layer69is formed in the formation regions for the COG terminal section34and the FPC terminal section35.

In this step, etching is performed by using an etchant containing, for example, oxalic acid, salt iron, etc. Thus, the semiconductor layer60in the region20in which the sealing member13is to be formed can be removed by etching simultaneously with the formation of the common electrode65. Moreover, in the formation region for the COG terminal section34, the semiconductor material layer56and the transparent conductive layer72can be simultaneously etched to separate adjacent terminals from each other.

(Step of Forming Second Protection Film)

Next, as illustrated inFIGS. 56-58, by using a sixth mask, a second protection film67serving as a second insulating film having a predetermined pattern is formed to cover the common electrode65.

That is, as illustrated inFIG. 56, the second protection film67covering the common electrode65is formed in the formation region for the TFT31and the formation region for the auxiliary capacitor section32. In the contact hole45, the first electrode48is exposed from the second protection film67. On the other hand, in the contact hole52, the first connect layer66is covered with the second protection film67. Moreover, as illustrated inFIG. 57, the second protection film67is removed in the formation regions for the COG terminal section34and the FPC terminal section35.

In this step, in the region20in which the sealing member13is to be formed, part of the second protection film67is formed to cover the lead line44. That is, as illustrated inFIG. 58, in the formation region20for the sealing member13, the second protection film67is stacked on the surfaces of the glass substrate30and the lead line44.

(Step of Forming Pixel Electrode)

Next, as illustrated inFIGS. 38-40, by using a seventh mask, a pixel electrode43having a predetermined pattern is formed on the surface of the second protection film67.

That is, as illustrated inFIG. 38, the pixel electrode43is formed in the formation region for the TFT31and the formation region for the auxiliary capacitor section32, and a second connect layer68is formed in the formation region for the connection section33. As a result, the pixel electrode43is connected to the first electrode48in the contact hole45. Moreover, an ITO layer57is formed in the formation regions for the COG terminal section34and the FPC terminal section35. Thus, the TFT substrate11is fabricated.

(Step of Forming Sealing Member)

Next, in the formation region20in which the sealing member13is to be formed, the sealing member13is provided directly on the surface of the second protection film67. Within the frame of the sealing member13, a liquid crystal material is supplied by dropping, and then the TFT substrate11is bonded to the counter substrate12via the sealing member13and the liquid crystal layer14. Thus, the liquid crystal display device1is fabricated.

—Advantages of Third Embodiment—

Thus, according to the third embodiment, the lead line44can be protected by being covered with the second protection film67in the formation region20for the sealing member13, and additionally, it is possible to ensure the prevention of the permeation of outer moisture into the region surrounded by the sealing member13because the interlayer insulating film42having moisture permeability is removed from the formation region20for the sealing member13. Additionally, an increase in the number of steps can be avoided. As a result, a reduction in display quality can be prevented while fabrication costs are reduced.

Additionally, since the transparent common electrode65facing the pixel electrode43is formed, capacitance is provided by the pixel electrode43and the common electrode65, allowing the display quality to be further improved while the aperture ratio is increased.

Other Embodiments

Although in the first to third embodiments, a liquid crystal display device has been described as an example, the present invention is not limited to this. Alternatively, the present invention is, in a similar manner, applicable to other thin display devices such as organic EL display devices.

Moreover, the present invention is not limited to the first to third embodiments, but the present invention includes configurations obtained by accordingly combining the first the third embodiments.

INDUSTRIAL APPLICABILITY

As described above, the present invention is useful for display devices and method for fabricating the same.

DESCRIPTION OF REFERENCE CHARACTERS