Patterned carrier wafers and methods of making and using the same

An apparatus is provided, comprising: a wafer having a first planar surface and a second surface opposite the first surface. The second surface includes a plurality of recesses. Each recess includes a plurality of sidewalls and a lower surface and is configured to receive a semiconductor device. The plurality of sidewalls of each recess is configured to align the semiconductor device and constrain the semiconductor device from moving in a direction parallel to the second surface.

TECHNICAL FIELD

The present disclosure generally relates to semiconductor devices, and more particularly relates to patterned carrier wafers and method of using the same in semiconductor device manufacturing and testing.

BACKGROUND

Following their manufacture, semiconductor devices may be tested for functionality in a probe operation in which temporary electrical connections between a semiconductor device and a test apparatus are made. Performing these probe operations on a large number of semiconductor devices in an automated process can present a number of challenges. One such challenge involves the automated placement of semiconductor devices into an arrangement suitable for use by a testing apparatus, and another involves preventing the loss of alignment (i.e., preventing the movement) of the semiconductor devices during a probe operation that could prevent the automated pickup of the semiconductor devices for further processing after the probe operation is complete.

DETAILED DESCRIPTION

In the following description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with semiconductor devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology.

Specific details of several embodiments of semiconductor devices are described below. The term “semiconductor device” generally refers to a solid-state device that includes a semiconductor material. A semiconductor device can include, for example, a semiconductor substrate, wafer, or die that is singulated from a wafer or substrate. Throughout the disclosure, semiconductor devices are generally described in the context of semiconductor dies; however, semiconductor devices are not limited to semiconductor dies.

The term “semiconductor device package” can refer to an arrangement with one or more semiconductor devices incorporated into a common package. A semiconductor package can include a housing or casing that partially or completely encapsulates at least one semiconductor device. A semiconductor device package can also include an interposer substrate that carries one or more semiconductor devices and is attached to or otherwise incorporated into the casing. The term “semiconductor device assembly” can refer to an assembly of one or more semiconductor devices, semiconductor device packages, and/or substrates (e.g., interposer, support, or other suitable substrates). The semiconductor device assembly can be manufactured, for example, in discrete package form, strip or matrix form, and/or wafer panel form. As used herein, the terms “vertical,” “lateral,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor device or device assembly in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to or closest to, respectively, the top of a page than another feature or portion of the same feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation.

As discussed above, the placement of semiconductor devices before a probe operation (e.g., into an arrangement on a carrier apparatus) and the subsequent pickup of the semiconductor devices after the probe operation can present an engineering challenge, which is further compounded by the need to perform these functions on a large number of devices in an automated fashion.FIG. 1shows one conventional approach to these challenges, involving the placement of semiconductor devices on a film frame into an arrangement expected by a test apparatus. Utilizing a film frame to secure semiconductor devices that are probed by a test apparatus (e.g., which are subjected to the pressures of a test probe making robust physical and electrical contact with the probe pads thereof) can, due to the lack of rigid support provided by the film, prevent the automated pickup of those of the semiconductor devices that have moved during the probe operation.

To address this and other challenges, embodiments of the present technology provide a patterned carrier wafer having a first planar surface and a second surface opposite the first surface. The second surface includes a plurality of recesses. Each recess includes a plurality of sidewalls and a lower surface and is configured to receive a semiconductor device. The plurality of sidewalls of each recess is configured to align the semiconductor device and constrain the semiconductor device from moving in a direction parallel to the second surface.

FIGS. 1A-1Eis a simplified diagram of a process flow for fabricating a patterned carrier wafer and testing semiconductor devices therewith in accordance with one embodiment of the present technology. As can be seen with reference toFIG. 1A, the process flow begins with a wafer110, such as a silicon wafer or a glass wafer, of a thickness suitable for supporting semiconductor devices during a probe operation (e.g., having a thickness between 500 μm and 1300 μm). As shown inFIG. 1B, a layer of patterned photoresist120or other mask material can be formed over wafer110, using conventional photolithography techniques. The patterned photoresist120includes a plurality of openings corresponding to the recesses130shown to have been formed inFIG. 1C, by a suitable etching or other material removal process. The recesses have a size and shape corresponding to the semiconductor devices that the patterned carrier wafer110will be used to test.

As can be seen with reference toFIG. 1D, an adhesive140can be disposed in each of the recesses130to facilitate the attachment of semiconductor devices for testing. According to one embodiment, the adhesive can be a laser debondable adhesive, such as 3M™ Light-To-Heat-Conversion Release Coating (LTHC), Tokyo Ohka Kogyo's TZNR-CTRL9 or US244, and the like. After disposing the semiconductor devices150to be tested in the corresponding recesses130, as shown inFIG. 1E, the adhesive140can be cured (e.g., by exposure to an ultraviolet light source) to reliably secure the semiconductor devices150in position for a test operation. As the sidewalls of the recesses130constrain the semiconductor devices150from lateral movement, and the adhesive140secures the semiconductor devices150to the lower surface of the recesses130, the testing operation can be conducted without displacing the semiconductor devices150from the positions in which a subsequent processing apparatus (e.g., configured to remove the semiconductor devices150with a picking mechanism) expects them to be.

Although in the foregoing example, a patterned carrier wafer is shown in which recesses are formed in a bulk material of the wafer, in other embodiments of the present technology, other approaches to patterning a carrier wafer may be employed. For example,FIGS. 2A-2Dare simplified diagrams of a process flow for fabricating a patterned carrier wafer and testing semiconductor devices therewith in accordance with one embodiment of the present technology. As can be seen with reference toFIG. 2A, the process flow begins with a wafer210, such as a silicon wafer or a glass wafer, of a thickness suitable for supporting semiconductor devices during a probe operation. As shown inFIG. 2B, a layer of patterned photoresist220or other mask material can be formed over wafer210, using conventional photolithography techniques. The patterned photoresist220includes a plurality of recesses230having a size and shape corresponding to the semiconductor devices that the patterned carrier wafer210will be used to test.

As can be seen with reference toFIG. 2C, an adhesive240can be disposed in each of the recesses230to facilitate the attachment of semiconductor devices for testing. After disposing the semiconductor devices250to be tested in the corresponding recesses230, as shown inFIG. 2D, the adhesive240can be cured (e.g., by exposure to an ultraviolet light source) to reliably secure the semiconductor devices250in position for a test operation. As the sidewalls of the recesses230constrain the semiconductor devices250from lateral movement, and the adhesive240secures the semiconductor devices250to the lower surface of the recesses230, the testing operation can be conducted without displacing the semiconductor devices250from the positions in which a subsequent processing apparatus (e.g., configured to remove the semiconductor devices250with a picking mechanism) expects them to be.

In accordance with one embodiment of the present technology, to facilitate the placement of semiconductor devices into corresponding recesses in a patterned semiconductor wafer, alignment marks can be patterned onto the wafer (e.g. in the same patterning operation by which the recesses, or the mask used for subsequently forming the recesses, is patterned). By way of example,FIG. 3is a simplified plan view of a patterned carrier wafer300in accordance with an embodiment of the present technology. As can be seen with reference toFIG. 3, patterned carrier wafer300includes a plurality of recesses310, and can include one or more alignment marks, such as alignment marks320, configured to facilitate the alignment of semiconductor devices with corresponding ones of the plurality of recesses310in a placement and/or picking operation.

FIG. 4is a flow chart illustrating a method of forming a patterned carrier wafer in accordance with an embodiment of the present technology. The method includes providing a patterned carrier wafer including a recess having a shape corresponding to the semiconductor device (box410). The method can further include disposing a debondable adhesive in the recess (box420), disposing the semiconductor device in the recess (box430) and curing the debondable adhesive (box440). The method can further include performing a probe operation on the semiconductor device (box450) and debonding the debondable adhesive (box460).

FIG. 5is a flow chart illustrating a method of forming a patterned carrier wafer in accordance with an embodiment of the present technology. The method includes providing a wafer (box510), forming a mask layer over the wafer (box520), and patterning the mask layer to form a plurality of recesses (box530), wherein each recess includes a plurality of sidewalls and a lower surface, wherein each recess is configured to receive a semiconductor device, and wherein the plurality of sidewalls of each recess is configured to align the semiconductor device and constrain the semiconductor device from moving in a direction parallel to the second surface.