Adaptive joint linearization, equalization and delay alignment for a wideband power amplifier

A feedforward linearizer includes a signal cancellation circuit and an error cancellation circuit. The signal cancellation circuit includes a tap delay line, that delay the input signal by a predetermined time delay so as to provide several delayed versions of the input signal. Each delayed version of the input signal is weighted by a tap coefficient. The weighted signals are then added together and fed to the power amplifier. The tap coefficients are derived such that the signals traveling through the upper and lower branch of the signal cancellation loop are aligned and that the output signal of the power amplifier is equalized.

FIELD OF THE INVENTION
 This invention relates to a wideband power amplifier and specifically to an
 amplifier having a feed-forward linearizer arrangement employing digital
 signal processing techniques for performing joint linearization,
 equalization and delay alignment.
 BACKGROUND OF THE INVENTION
 In many radio frequency, RF, applications power amplifiers are employed to
 amplify high frequency signals. Because the RF amplifiers are biased to
 provide substantially high output power, they exhibit nonlinear responses
 to some degree. Consequently, in response to an increase in the output
 signal power, such RF amplifiers generate intermodulation IM components,
 which may have frequencies that are outside a desired frequency band.
 One solution to eliminate the consequences of the nonlinear response of the
 amplifier is to employ multiple amplifiers each configured to amplify a
 predetermined carrier signal. For example, in a mobile communications
 environment, the base station sends multiple carrier signals in accordance
 with time division multiple access (TDMA) scheme, or in accordance with
 code division multiple access (CDMA) scheme. Each carrier frequency in
 TDMA scheme corresponds to one of the users in a specifiable cell.
 Furthermore, each pseudocode in CDMA scheme corresponds to one of the
 users in a specifiable cell. Because the base station has to communicate
 with many users in the corresponding cell, the intermodulation IM
 components increase with the number of the users. Thus, the use of a
 separate amplifier for each carrier signal substantially eliminates the
 generation of intermodulation IM components. However, this approach is
 costly and may not be commercially feasible in many applications.
 Another approach is to employ an analog linearizer, such as 10 as
 illustrated in FIG. 1. For purposes of illustrating the operation of
 linearizer 10, it is assumed that a two-tone signal is provided to the
 linearizer. Basically, a radio frequency signal represented by frequency
 components 22 is fed to a power amplifier 12. Amplifier 12 generates
 additional intermodulation IM frequency components 24 because of its
 nonlinear response characteristics. Signal components 22' correspond to an
 amplified version of signal components 22. The function of linearizer 10
 is to substantially eliminate frequency components 24, as explained in
 more detail below.
 Linearizer 10 includes a signal cancellation circuit 26 coupled to an error
 cancellation circuit 28. Signal cancellation circuit 26 has an upper
 branch that includes power amplifier 12, and a lower branch that provides
 the input signal of the linearizer to an input port of an adder 16 via a
 delay element 15. The other input port of adder 16 is configured to
 receive the output signal generated by power amplifier 12, via an
 attenuator 14. As a result, the output port of adder 16 provides signal
 components 24', which correspond to the attenuated version of
 intermodulation IM frequency components 24. The purpose of delay element
 15 is to assure that the input signal provided to adder 16 through the
 lower branch is aligned with the input signal provided through the upper
 branch.
 Error cancellation circuit 28 also includes an upper branch that is
 configured to provide the output signal generated by amplifier 12 to an
 adder 20 via a delay element 17. The lower branch of error cancellation
 circuit 28 includes an amplifier 18, which is configured to receive the
 attenuated intermodulation components 24'. Amplifier 18 generates an
 amplified version of signal 24' which is substantially equal to
 intermodulation component 24. As a result, the output port of adder 20
 provides signal components 22' without the distortion caused by amplifier.
 The purpose of delay element 17 is to assure that the signal provided
 through the lower branch is aligned with the direct signal provided in the
 upper branch.
 The feedforward linearizer described in FIG. 1 has some disadvantages. For
 example, it is not able to adapt to signal changes. Furthermore, for
 wide-band input signals in the microwave frequency range, adjusting the
 delay in delay elements 15 and 17 is difficult. A small delay misalignment
 may lead to serious signal distortion. In order to provide a delay
 alignment between the upper and lower branches of the two cancellation
 circuits, some linearizers have been suggested that attempt to align the
 signal by trial and error during the operation. These linearizers employ a
 delay adjuster to achieve the intended delay alignment. However, the trial
 and error approach provides only limited accuracy and may lead to
 unacceptable output signal response.
 For signals or the microwave frequency range, the bandwidth accommodated by
 power amplifier 12 is relatively small. Amplifiers that accommodate a
 large bandwidth are expensive. Thus, equalization for the power amplifier
 is required to increase the operating bandwidth so that the frequency
 response of the power amplifier is substantially flat. The prior art
 feedforward linearizers direct all the linear distortion caused by delay
 misalignment and the non-linear distortions caused by of the power
 amplifier to the auxiliary amplifier in the error cancellation loop. The
 auxiliary amplifier is designed as a class A amplifier. The distortion
 generated by the auxiliary amplifier itself is not recoverable. Thus, a
 high-accuracy class A amplifier that handles high power input is required
 in the error cancellation loop, which is expensive and difficult to
 design.
 Thus, there is a need for a feedforward linearizer that employs an
 effective digital signal processing technique that provides delay
 alignment and equalization to suppress intermodulation components, by an
 arrangement that is both effective and economical.
 SUMMARY OF THE INVENTION
 In accordance with one embodiment of the invention, a feedforward
 linearizer includes a signal cancellation circuit and an error
 cancellation circuit. The signal cancellation circuit includes a tap delay
 line, that delay the input signal by a predetermined time delay so as to
 provide several delayed versions of the input signal. Each delayed version
 of the input signal is weighted by a tap coefficient. The weighted signals
 are then added together and fed to the power amplifier. The tap
 coefficients are derived such that the signals traveling through the upper
 and lower branch of the signal cancellation loop are aligned and that the
 output signal of the power amplifier is equalized.
 The error cancellation circuit also includes a tap delay line, that delays
 the error signal to the error cancellation circuit by a predetermined time
 delay so as to provide several delayed versions of the error cancellation
 input signal. Each delayed version of the error cancellation input signal
 is weighted by a tap coefficient. The weighted signals are then added
 together and fed to an auxiliary amplifier. The tap coefficients in the
 error cancellation circuit are derived such that the signals traveling
 through the upper and lower branch of the error cancellation circuit are
 aligned.
 In accordance with one embodiment of the invention, the tap coefficients
 are derived such that substantially no equalization for the auxiliary
 amplifier is achieved.

DETAILED DESCRIPTION OF THE DRAWINGS
 FIG. 2a illustrates a wideband power amplifier feed-forward linearizer 60
 in accordance with one embodiment of the invention, although the invention
 is not limited in scope in that respect.
 Linearizer 60 includes a signal cancellation circuit or loop 86 and an
 error cancellation loop or circuit 88. Each of the cancellation circuits
 86 and 88 have two branches. Thus, signal cancellation circuit 86 includes
 a first signal cancellation branch that contains an amplifier 62, which is
 configured to receive an input signal V.sub.m, via a tap delay circuit
 120. Input signal V.sub.m is also diverted to a second signal cancellation
 branch via signal splitter 122 and a delay element 124.
 The output port of power amplifier 62 provides an output signal V.sub.u and
 is coupled to an attenuator 64 having an attenuation factor r, via a
 splitter 90. The output port of attenuator 64 is coupled to an adder 68.
 The other input port of adder 68 is configured to receive the input signal
 V.sub.m, via delay element 124 in the second signal cancellation branch.
 The output port of adder 68 provides an error signal V.sub.d to error
 cancellation circuit 88.
 As stated before, in the background of the invention, a small delay
 mismatch between the time that signal V.sub.m is provided to adder 68
 through the first and second branch of the signal cancellation loop can
 cause substantial degradation in the performance of the linearizer. To
 this end, tap delay circuit 120 is employed to provide delay alignment and
 equalization in accordance with one embodiment of the invention.
 Delay circuit 120 includes a plurality of tap delay elements 112 that are
 configured to provide a predetermined delay .tau. to signal V.sub.m. Thus,
 an input port of tap delay element 112a is configured to receive input
 signal V.sub.m. An output port of tap delay element 112a is coupled to an
 input port of the following tap delay element 112b, and so forth. As will
 be explained in more detail later, the number of tap delay elements
 depends, among other things, on the delay mismatch .tau..sub..alpha.,
 which is the delay difference between the upper and lower branches of the
 signal cancellation circuit.
 Delay circuit 120 also includes a plurality of multipliers, such as 92, 94
 and 96, which are configured to receive signal V.sub.m, a first delayed
 version of input signal V.sub.m after it has been delayed by delay element
 112a, and a second delayed version of input signal V.sub.m after it has
 been delayed by delay element 112b, and so forth. Each multiplier is
 configured to receive tap coefficients .alpha..sub.i, wherein i is the
 index relating to the number of the tap delay element that provides a
 delayed version of V.sub.m to the multiplier. An output port of
 multipliers 92, 94 and 96 is coupled to an adder 130. The output port of
 adder 130 is in turn coupled to an input port of power amplifier 72.
 The output port of power amplifier 62 is also coupled to a first error
 cancellation branch of linearizer 60 via signal splitter 90. The first
 error cancellation branch includes a delay element 132 and an error
 cancellation adder 74 adapted to receive a delayed version of signal
 V.sub.u at one of its input ports. The second error cancellation branch of
 linearizer 60 includes a tap delay circuit 134 that is configured to
 receive the error signal V.sub.d at its input port. The output port of tap
 delay circuit 134 is coupled to an input port of an auxiliary amplifier
 72. The output port of auxiliary amplifier 72 is coupled to the other
 input port of adder 74. In accordance with one embodiment of the
 invention, the output port of adder 74 provides the output signal of
 linearizer 60.
 Delay circuit 134 also includes a plurality of multipliers, such as 98, 102
 and 104, which are configured to receive the error signal V.sub.d, a first
 delayed version of input signal V.sub.d after it has been delayed by delay
 element 108a, and a second delayed version of input signal V.sub.d after
 it has been delayed by delay element 108b. Each multiplier is configured
 to receive a tap coefficient .beta..sub.i, wherein i is the index relating
 to the number of the tap delay element that provides a delayed version of
 V.sub.d to the multiplier. An output port of multipliers 98, 102 and 104
 is coupled to an adder 70. The output port of adder 70 is in turn coupled
 to the input port of auxiliary amplifier 72.
 A digital signal processor 76 is configured to receive input signal,
 V.sub.m, error signal, V.sub.d, and the output signal V.sub.o. The digital
 signal processor as illustrated in FIG. 2b, in accordance with one
 embodiment of the invention, includes a down converter circuit 84, which
 is configured to shift the frequency range of signals, V.sub.m, V.sub.d,
 and V.sub.o into the baseband frequency range, although the invention is
 not limited in scope in that respect. For example, a separate down
 converter circuit, in accordance with another embodiment of the invention,
 first shifts the frequencies to the baseband range, and then provides the
 down converted signal to digital signal processor 76.
 The output port of down converter circuit 84 is coupled to a digital signal
 processing circuit 80, via an analog-to-digital converter 92. Signal
 processing circuit 80 is configured to perform the necessary calculations
 to generate tap coefficients .alpha..sub.i and .beta..sub.i and provide
 them respectively via multiplexers 140 and 142 to tap delay circuits 120
 and 134.
 As will be explained in more detail hereinafter, the arrangement of tap
 delay circuit 120 provides for a delay alignment and equalization at the
 same time in the signal cancellation circuit. Furthermore, the arrangement
 of tap delay circuit 134 provides for a delay alignment in the error
 cancellation circuit.
 The output signal of adder 130 can be written as
 ##EQU1##
 wherein L is the number of tap delay elements 112, .alpha..sub.i are tap
 coefficients, 1/T is the sampling rate determined by the capabilities of
 digital signal processor 76, .tau. is the tap delay for each tap delay
 element 112. In accordance with one embodiment of the invention the tap
 delay is chosen to be inversely proportional to the input signal bandwidth
 to achieve equalization. It is noted that for wideband input signals
 V.sub.m, T is substantially larger than .tau.. Thus, in accordance with
 one embodiment of the invention, digital signal processor 76 receives L+1
 samples of V.sub.m at times t=kT-i.tau., wherein i=0, 1, . . . , L at each
 sampling. Digital signal processing circuit 80 employs a least mean square
 (LMS) algorithm to calculate the tap coefficients .alpha..sub.i based on
 the following recursive equation:
EQU .alpha..sub.i (k+1)=.alpha..sub.i (k)-.mu..sub..alpha. V.sub.d (kT)V*.sub.m
 (kT-i.tau.), i=0, 1, . . . L, (2)
 where .mu..sub..alpha. is the step size for the algorithm, and V*.sub.m is
 the complex conjugate of input signal V.sub.m. It is noted that
 coefficients .alpha..sub.i are derived such that error signal V.sub.d (kT)
 has substantially no correlation with input signal and its delayed
 versions, V.sub.m (kT-i.tau.) for I=0, 1, . . . , L. As will be explained
 in more detail hereinafter, the solution to equation (2) in accordance
 with a least mean square algorithm provides both delay alignment and
 equalization at the same time.
 Thus, the converged solution .alpha..sub.i to equation (2) may be
 deconvolved to two components, the first referred to as .alpha..sub.d,i,
 and the second referred to as components .alpha..sub.e,i, wherein
 .alpha..sub.d,i are the desired tap coefficients when power amplifier 62
 requires no equalization, and components .alpha..sub.e,i are the desired
 tap coefficients when there is no delay misalignment between the two
 branches of signal cancellation circuit 86. It is also assumed that the
 delay difference between the two branches is .tau..sub..alpha. when delay
 alignment is required.
 Therefore, the intent is to adjust the tap coefficients .alpha..sub.d,i, to
 introduce a delay .tau..sub..alpha., in a branch, other than the one that
 is generating an extra delay .tau..sub..alpha., which compensates for the
 existing delay between the two branches. Therefore, it is desired that the
 impulse response of the delay tap element to be
 .delta.(t+.tau..sub..alpha.), where .delta.(.) is an impulse function. The
 frequency response of .delta.(t+.tau..sub..alpha.) is
 e.sup.-j2.pi..function..tau..alpha., where .function. denotes the
 frequency. Since all the signals under consideration are band-limited
 signals, the frequency response may be truncated by a window without
 affecting the performance of the tap delay line. The truncated frequency
 response can be written as e.sup.-j2.pi..function..tau..alpha.
 .PI.(.function./.function..sub.c), wherein .function..sub.c is the
 bandwidth of the signals and .PI.(.) Is a rectangular box function,
 defined as .PI.(x)=1 if .vertline.x.vertline.&lt;1/2 and .PI.(x)=0 otherwise.
 The inverse Fourier transform of .PI.(.function./.function..sub.c) equals
 to (1/.tau.) Sinc (t/.tau.), wherein .tau. is defined as
 .tau.=1/.function..sub.c, which is the tap delay amount in each tap delay
 element 112, and sinc (x)=(sin .pi.x)/.pi.x. Therefore, the inverse
 Fourier transform of
 e.sup.-j2.pi..function..tau..alpha..PI.(.function./.function..sub.c),
 equals to (1/.tau.) Sinc ((t+.tau..sub..alpha.)/.tau.), which is
 proportional to Sinc (i+.tau..sub..alpha. /.tau.) after sampling. Thus,
 assuming that power amplifier 62 does not require equalization, the
 optimal tap coefficients for a delay alignment are given by
EQU .alpha..sub.d,i =Sinc (i+.tau..sub..alpha. /.tau.), i=-.infin., . . .
 .infin., (3)
 wherein .tau..sub..alpha. is the delay difference between the upper and the
 lower branches of the signal cancellation circuit. The optimal tap
 coefficients .alpha..sub.c,i for equalization with no delay misalignment,
 is determined by the characteristics and operating range of power
 amplifier 62. The overall tap coefficients for delay circuit 120 is
 obtained as the convolution of .alpha..sub.d,i and .alpha..sub.e,i.
 The number of tap delay elements 112 among other things depends on the
 ratio of .pi..sub..alpha. /.tau.. Thus if this ratio is close to an
 integer, .alpha..sub.d,i will quickly converge to zero as
 .vertline.i.vertline. increases. Thus, .alpha..sub.i may be truncated by a
 small window and use only a small number of taps.
 The solution for error cancellation circuit 88 is described hereinafter.
 The signal V.sub.d provided by tap delay circuit 134 in error cancellation
 circuit 88 can be written as
 ##EQU2##
 where M delay elements 108 are employed in the tap delay circuit and
 .beta..sub.i is the corresponding tap coefficient, associated with each
 delay element 108. At each sampling, M+1 samples of V.sub.d are taken at
 t=kT-i.tau., i=0, 1, . . . , M.
 In accordance with one embodiment of the invention, as explained above in
 reference with the signal cancellation loop, digital signal processor
 derives tap coefficients .beta..sub.i such that the error signal V.sub.d
 (kT) remains uncorrelated to the input signal V.sub.m (kT). In order to
 make the output signal V.sub.o (kT) of linearizer 60 fully correlated to
 input signal V.sub.m (kT), digital signal processor 76 controls the tap
 coefficients .beta..sub.i in the error cancellation circuit 88 such that
 the output signal V.sub.o (kT) is substantially uncorrelated with the
 error signal V.sub.d (kT). To accomplish this purpose a conventional least
 mean square algorithm for the error cancellation circuit 88 will cause
 output signal V.sub.o (kT) to be uncorrelated with not only V.sub.d (kT),
 but also to each error sample V.sub.d (kT), V.sub.d (kT+.tau.), . . . ,
 V.sub.d (kT+M.tau.). However, this solution may not be acceptable for some
 design specifications, because not only the error signal is substantially
 canceled, but some of the undistorted signal will be canceled also. It is
 noted that the least mean square algorithm employed for the signal
 cancellation loop also causes the error signal V.sub.d (kT) to become
 uncorrelated to V.sub.m (kT-i.tau.) for i=0, 1, . . . , L. However, this
 solution does not degrade the performance of linearizer 60.
 In order to make V.sub.o (kT) only uncorrelated to V.sub.d (kT) and still
 align the delay misalignment between the upper and lower branches of the
 error cancellation circuit, digital signal processor 76 employs a
 constrained version of a least mean square algorithm in accordance with
 one embodiment of the invention, although the invention is not limited in
 scope in this aspect. Thus, the least mean square algorithm employs a
 constraint such that the tap coefficients .beta..sub.i can only be updated
 within the subset where .beta..sub.i takes the form as
 ##EQU3##
 where the variable t represents the delay adjustment and c is a complex
 variable. Thus, in accordance with one embodiment of the invention,
 equation (5) provides for delay alignment between the two branches of the
 error cancellation circuit without canceling undistorted signals. It is
 noted that a least mean square algorithm that employs a constraint as
 specified in equation (5) will not provide for equalization. However,
 unlike power amplifier 62, auxiliary amplifier 72 is designed to perform
 acceptably without the need for equalization because of the relatively low
 power of V.sub.d.
 It is also noted that equation (5) suggests that there are three degrees of
 freedom relating to variable c.sub.r, c.sub.i, t, that may be employed to
 update coefficients .beta..sub.i, where c.sub.r, c.sub.i are respectively
 the real and imaginary parts of complex variable c in equation (5). The
 coefficient updates as measured by a least mean square algorithm are
EQU p(k)=.mu..sub..beta. V.sub.o (kT)[V.sub.d (kT)V.sub.d (kT-.tau.) . . .
 V.sub.d (kT-M.tau.)]* (6)
 wherein p(k) is a vector update, .mu..sub..beta. is the step size employed
 by the least mean square algorithm. Thus, in accordance with one
 embodiment of the invention in order to determine the solutions based on
 the constraint specified in equation (5) the least mean square coefficient
 updates in equation (6) are projected on the subset defined in equation
 (5) before updating tap coefficients .beta..sub.i. The constrained
 solution can be expressed as
 ##EQU4##
 Assume .DELTA.w(k) for a variable w is defined as [.DELTA.c.sub.r (k),
 .DELTA.c.sub.i (k), .DELTA.t(k)].sup.T, and is given by
 ##EQU5##
 wherein (.).sup.+ denotes the pseudo-inverse
EQU .beta.(k)=[Re (.beta.) Im (.beta.)].sup.r and .beta.=[.beta..sub.0 (k),
 .beta..sub.1 (k), . . . .beta..sub.M (k)].
 Thus, the matrix applying pseudo-inverse in equation (9)
 [.differential..beta.(k)/2w], is a (2M+2).times.3 matrix and can be
 expanded as
 ##EQU6##
 FIG. 3 illustrates a flow chart illustrating the steps accomplished by
 digital signal processing circuit 80 in accordance with one embodiment of
 the invention, although the invention is not limited in scope in that
 respect. At step 200, processing circuit 80 initializes the values of
 .alpha..sub.i (0), .beta..sub.i (0), c(0) and t(0). At step 210,
 processing circuit 80 obtains the next available baseband input signals
 V.sub.m, and error signal V.sub.d.
 At step 212, processing circuit 80 employs a least mean square algorithm to
 track the tap coefficients .alpha..sub.i as explained in accordance with
 equation (2). At step 214, the update values of tap coefficients
 .alpha..sub.i are applied to delay circuit 120. The least mean square
 algorithm continues its estimation through an infinite loop of steps 210,
 212 and 214 to track the variation of the input signal statistics and
 other environmental factors.
 At the same time, processing circuit 80 determines at step 216 whether the
 value of tap coefficients .alpha. has been stabilized. At step 218
 processing circuit 80 proceeds to obtain tap coefficients .beta..sub.i for
 delay circuit 134 by obtaining the next available baseband value of
 V.sub.d and V.sub.o respectively. At step 220 processing circuit 80
 calculates the updated values p(k) in accordance with equation (6). At
 step 222 processing circuit determines whether the delay adjustment
 variable, representing the delay difference between the upper and lower
 branches of error cancellation circuit 88, has been stabilized. If not,
 digital signal processing circuit 80 goes to step 224 and calculates
 .DELTA.w in equation (9). Thereafter, processing circuit 80 goes to step
 228 to update .beta. in equation (8) and apply the updated tap
 coefficients to delay circuit 134. If however, at step 222, processing
 circuit 80 determines that parameter t has been stabilized, processing
 circuit 80 goes to step 226 and calculates .DELTA.w in equation (9) with
 the condition that .DELTA.t=0. It is noted that the third column of matrix
 10 will be set to zero leading to a simple calculation. Thereafter the
 processing circuit goes to step 228 as described before. Again, steps 218
 through 228 form an infinite loop to track the variation of the input
 signal statistics and other environmental factors.
 Thus, in accordance with one embodiment of the invention, processing
 circuit 80 provides both equalization and delay adjustment in the signal
 cancellation circuit and provide delay adjustment in the error
 cancellation circuit. As discussed in reference with simulation results
 illustrated in FIGS. 4 through 6, linearizer 60 provides a remarkable
 response.
 FIGS. 4(a) through 4(d) illustrate simulation results of linearizer 60 in
 accordance with one embodiment of the invention as described above. For
 this simulation, the input signal consists of eight tones with unit
 amplitude which are placed 300 kHz apart one after another. The central
 frequency is 900 Mhz. Temperature and other environmental factors are
 assumed to be constant. The power amplifier model employed in the
 simulation contains both linear and nonlinear distortions and can be
 described by a polynomial,
 ##EQU7##
 wherein .tau. is set to be the reciprocal of the signal bandwidth. For both
 cancellation circuits, a delay misalignment of .tau./3 is assumed.
 Furthermore, each delay circuit 120 and 134 employs seven tap delay
 elements.
 FIGS. 4(a) -4(d) illustrated the performance of the system in accordance
 with one embodiment of the invention. FIGS. 5(a)-5(b) illustrate the
 performance of an equivalent algorithm with the tap delay circuit replaced
 by a single-tap vector modulator, and the assumption that there are no
 delay mismatches between the upper and lower branches of both the
 cancellation circuits. FIGS. 6(a) and 6(d) illustrate the performance of
 an equivalent algorithm with the tap delay circuit replaced by a
 single-tap vector modulator and the assumption that there is no distortion
 but there are delay mismatches between the upper and lower branches of
 both the cancellation circuits.
 It is noted that in accordance with the principles of the present
 invention, it is possible to reduce the power of the distortion signals
 going through the auxiliary amplifier, and correct delay misalignments.
 While only certain features of the invention have been illustrated and
 described herein, many modifications, changes or equivalents will now
 occur to those skilled in the art. It is therefore, to be understood that
 the appended claims are intended to cover all such modifications and
 changes that fall within the true spirit of the invention.