Light detection apparatus, photoelectric conversion system, and movable body

A light detection apparatus according to an embodiment includes a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type, a third semiconductor region having the first conductivity type, and a circuit unit configured to count the number of generation times of an avalanche current, wherein a reverse bias voltage for causing avalanche multiplication of the signal charge is applied to the second semiconductor region and the third semiconductor region, and the signal charge is accumulated in the first semiconductor region when the potential barrier is formed, wherein the control unit controls the height of the potential barrier.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a light detection apparatus, a photoelectric conversion system, and a movable body. The invention particularly relates to a light detection apparatus including a single photon avalanche diode (SPAD).

Description of the Related Art

A light detection apparatus including a SPAD has been known. The SPAD is an element configured to count the number of incident photons by detecting an avalanche current that has been generated upon incidence of a single photon on an avalanche diode (hereinafter, referred to as an AD). A reverse bias voltage having a magnitude higher than or equal to a breakdown voltage is applied to the AD, and a current is multiplied by avalanche multiplication. The light detection apparatus including the SPAD counts the number of occurrences when the current multiplied by the avalanche multiplication (hereinafter, referred to as “an avalanche current”) exceeds a threshold.

U.S. Patent Application Publication No. 2009/0184384 describes a SPAD. Generation of a signal charge by photon incidence and avalanche multiplication of the generated signal charge are performed in the same region in the SPAD described in U.S. Patent Application Publication No. 2009/0184384. Specifically, the generation of the signal charge and the avalanche multiplication are performed in a depletion layer where only an electric field in a direction towards a charge collection region is generated. In accordance with the above-described configuration, the avalanche current is generated immediately when the signal charge is generated. However, for this reason, application of a reverse bias voltage having such a magnitude that the avalanche multiplication occurs is regularly performed during an incident light detection period in the SPAD according to U.S. Patent Application Publication No. 2009/0184384.

The AD performs not only the avalanche multiplication of the signal charge generated by the photon incidence but also avalanche multiplication of a charge generated due to a factor different from the photon incidence (hereinafter, referred to as an “unwanted charge”) in some cases. When the avalanche multiplication of the unwanted charge occurs, this becomes a cause of noise.

In general, as a reverse bias voltage to be applied to a P-N junction is higher, the generated amount of a leak current or the like becomes higher. For this reason, as a reverse bias voltage to be applied to the P-N junction is higher, the unwanted charge that may become a noise source is more likely to be generated. In addition, a generation source of the unwanted charge (such as a crystal defect) generally exists in the entirety of a semiconductor substrate, and the generation source of the unwanted charge also exists in a region where the avalanche multiplication occurs.

In the AD in which the generation of the signal charge and the avalanche multiplication are performed in the same region as in the SPAD according to U.S. Patent Application Publication No. 2009/0184384, when the incident light detection period is lengthened, a period in which the application of the large reverse bias voltage is performed is accordingly lengthened. As a result, there is a possibility that the avalanche multiplication of the generated unwanted charge occurs, and the number of detections thereof may be increased. Therefore, an issue occurs that the noise is likely to increase in the SPAD according to U.S. Patent Application Publication No. 2009/0184384.

SUMMARY OF THE INVENTION

A light detection apparatus according to an aspect of the present invention includes a first semiconductor region having a first conductivity type in which carriers having a first polarity that is the same polarity as that of a signal charge are set as majority carriers, a second semiconductor region having a second conductivity type in which carriers having a second polarity are set as majority carriers, and a third semiconductor region having the first conductivity type where the signal charge is transferred from the first semiconductor region, wherein a reverse bias voltage for causing avalanche multiplication of the signal charge is applied to the second semiconductor region and the third semiconductor region, a potential barrier having a height lower than the reverse bias voltage with respect to the signal charge in the first semiconductor region is formed between the first semiconductor region and the third semiconductor region, and the signal charge is accumulated in the first semiconductor region by forming the potential barrier, wherein the light detection apparatus comprises a control unit configured to transfer the signal charge in the first semiconductor region to the third semiconductor region in a manner that the height of the potential barrier is controlled, and a circuit unit configured to count the number of generation times of an avalanche current generated by the avalanche multiplication.

DESCRIPTION OF THE EMBODIMENTS

According to the following exemplary embodiments, an example in which an electron is used as a signal charge will be described. According to the following exemplary embodiments, a semiconductor region having a first conductivity type in which carriers having a first polarity are set as majority carriers is an N-type semiconductor region, and a semiconductor region having a second conductivity type in which carriers having a second polarity are set as majority carriers is a P-type semiconductor region. However, exemplary embodiments of the present invention in which a hole is used as the signal charge are also established. In this case, the N type and the P type are inverted.

In addition, a photoelectric conversion unit in the following descriptions refers to a pixel in the case of an imaging sensor. However, application of the exemplary embodiments of the present invention is not limited to the imaging sensor, and therefore the term “photoelectric conversion unit” is used.

First Exemplary Embodiment

First, a photoelectric conversion unit included in a light detection apparatus will be described.FIGS. 1A to 1Cschematically illustrate a cross sectional structure of a photoelectric conversion unit70. As illustrated inFIGS. 1A to 1C, the photoelectric conversion unit70includes an N-type semiconductor region1(first semiconductor region), a P-type semiconductor region2(second semiconductor region), an N-type semiconductor region3(third semiconductor region), and an N-type semiconductor region12(seventh semiconductor region). The N-type semiconductor region1and the P-type semiconductor region2constitute a photodiode (PD) configured to convert light into a signal charge and accumulate the signal charge. The P-type semiconductor region2, the N-type semiconductor region3, and the N-type semiconductor region12constitute an avalanche diode (AD). As will be described below, the photoelectric conversion unit70takes a first state in which the signal charge is accumulated in the PD and a second state in which the signal charge accumulated in the PD is transferred to the AD. Avalanche multiplication is caused by the transferred signal charge in an AD section during at least part of a period in the second state.

The photoelectric conversion unit70further includes a P-type semiconductor region9formed on a semiconductor surface and a P-type semiconductor region10and a P-type semiconductor region11for separating the mutual adjacent photoelectric conversion units.

Arrangements for these semiconductor regions in the cross sectional structure are as illustrated inFIG. 1Aand the like. In particular, the N-type semiconductor region1is surrounded by the P-type semiconductor regions2,9, and10(fourth semiconductor region). The P-type semiconductor region2is arranged at least partially between the N-type semiconductor region1and the N-type semiconductor region3. The N-type semiconductor region12has a lower impurity concentration than the N-type semiconductor region3and is also arranged between the P-type semiconductor region2and the N-type semiconductor region3. At least part of the N-type semiconductor region12forms an avalanche multiplication section. It should be noted that light is incident from an upper side ofFIGS. 1A to 1C.

A potential control section5is connected to the N-type semiconductor region3. The potential control section5applies a potential (electric potential) Vn to the N-type semiconductor region3. A potential control section6is connected to the P-type semiconductor region11. The potential control section6applies a potential Vp to the P-type semiconductor region11. The potential Vp may also be supplied to the P-type semiconductor regions2,9, and10via the P-type semiconductor region11. In the state illustrated inFIG. 1A, the N-type semiconductor region1is electrically floating.

A potential distribution inside the semiconductor substrate is determined by the above-described arrangements of the respective semiconductor regions, impurity concentration distributions of the respective semiconductor regions, and potentials applied to the potential control section5and the potential control section6. Therefore, when the potentials applied to the potential control section5and the potential control section6are controlled, the first state and the second state described above can be switched. A potential state that will be described below is realized. In particular, the above-described arrangements of the respective semiconductor regions and the impurity concentration distributions of the respective semiconductor regions may be adjusted at the time of designing of the light detection apparatus so as to cause the avalanche multiplication precisely at the time of the signal charge transfer.

InFIGS. 1A to 1CandFIGS. 2A to 2C, a height of a potential barrier formed between the N-type semiconductor region1and the N-type semiconductor region3is changed by changing the potential applied to the N-type semiconductor region3. With this configuration, the period in which the signal charge is accumulated in the N-type semiconductor region1(corresponding to the above-described first state) and the period in which the signal charge is transferred from the N-type semiconductor region1to the N-type semiconductor region3(corresponding to the above-described second state) are controlled. To make a principle of the operations more easily understandable, the fixed electric potential Vp is applied to the P-type semiconductor region2inFIGS. 1A to 1C.

FIG. 1Aillustrates the photoelectric conversion unit70in a state in which the signal charge is accumulated in the N-type semiconductor region1, andFIG. 2Aillustrates a potential along IIA-IIA inFIG. 1A.

First, the potential Vn applied to the potential control section5is higher than the potential Vp applied by the potential control section6. That is, a state is established in which a reverse bias is applied to the P-N junction. A depletion layer extends in the vicinity of a P-N junction surface. An edge of the depletion layer is illustrated by a broken line inFIGS. 1A to 1C. As illustrated inFIG. 1A, a neutral region exists in part of the P-type semiconductor region2. A large number of holes corresponding to the majority carriers of the P-type semiconductor region in the neutral region in the P-type semiconductor region2. For this reason, a potential in the neutral region in the P-type semiconductor region2is substantially the same as the applied potential Vp in the potential control section6. It should be noted that the neutral regions also respectively remain in the P-type semiconductor regions11,10, and9.

First, in a dark state, that is, in a case where the signal charge does not exist, the depletion layer extends in the entirety of the N-type semiconductor region1inFIG. 1A. At this time, a reverse bias voltage that is so-called “depletion voltage” is generated at least between the neutral region in the P-type semiconductor region2(neutral region in the other P-type semiconductor region existing in the surrounding) and the N-type semiconductor region1. In other words, a potential barrier equivalent to a voltage obtained by adding a built-in potential between the P-N junctions in the surrounding to the depletion voltage is caused with respect to the signal charge (electron) existing in the N-type semiconductor region1. Therefore, the potential barrier with respect to the electron in the N-type semiconductor region1is formed between the N-type semiconductor region1and the N-type semiconductor region3in the potential distribution along IIA-IIA as illustrated inFIG. 2A. It should be noted that the depletion voltage of the above-described PD is typically at the same level as a depletion voltage of a PD in an imaging sensor such as a complementary metal-oxide semiconductor (CMOS) sensor or a charge-coupled device (CCD), that is, it may be considered that the depletion voltage is approximately 1 V to 2 V.

InFIG. 1A, the potential Vn applied to the N-type semiconductor region3is set as Vn0. As described above, the potential Vn0 is higher than the potential Vp applied to the potential control section6. Therefore, a reverse bias equivalent to a difference between the potential Vn0 and the potential Vp is applied to the P-N junction between the P-type semiconductor regions2and11and the N-type semiconductor regions3and12. The depletion layer in accordance with the reverse bias also extends in the P-type semiconductor region2and the P-type semiconductor region11. In this state ofFIG. 1A, the potential Vn0 at which the avalanche multiplication is not caused is basically set at the P-N junction of the AD formed by the P-type semiconductor region2and the N-type semiconductor regions3and12. The signal charge generated by the light incidence is accumulated in the N-type semiconductor region1.

FIG. 1Billustrates a state in which the potential Vn applied to the N-type semiconductor region3is changed from Vn0 to Vn1 that is higher than Vn0.

Vn1 is a higher potential than Vn0, and Vp is fixed. For this reason, a higher reverse bias as compared with the case inFIG. 1Ais applied to the P-N junction between the P-type semiconductor regions2and11and the N-type semiconductor regions3and12. In response to this, the depletion layer in the P-type semiconductor region2is widened as compared with the case inFIG. 1A. As a result, when the potential Vn is Vn1, the depletion layer in the P-type semiconductor region2in the surrounding of the N-type semiconductor region1and the depletion layer in the P-type semiconductor region2in the surrounding of the N-type semiconductor region3are coupled to each other. In other words, the depletion layer is in a continuously extending state from the N-type semiconductor region1up to the N-type semiconductor region3.

A potential at the depleting part in the P-type semiconductor region2is lower than a potential in the neutral region in the P-type semiconductor region2(substantially the same as Vp). This is because influences by the potential Vn applied to the N-type semiconductor region3are affected. Therefore, in the potential distribution along IIB-IIB inFIG. 1B, as illustrated inFIG. 2B, the height of the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3is lowered as compared with the case inFIG. 1A.

At this time, almost the entire surrounding of the N-type semiconductor region1is surrounded by the neutral regions in the P-type semiconductor regions2,9, and10. The applied potential Vp of the potential control section6is fixed. For this reason, a potential at a center of the N-type semiconductor region1hardly changes. Therefore, as described above, the height of the potential barrier with respect to the N-type semiconductor region1can be locally lowered.

InFIG. 1B, in a case where the signal charge is accumulated in the N-type semiconductor region1, the signal charge starts to be transferred to the N-type semiconductor region3beyond the potential barrier. At this time, a reverse bias voltage to such an extent that the avalanche multiplication is caused is preferably set between the N-type semiconductor region3and the P-type semiconductor region2.

After the continuous depletion layer is formed, the potential barrier is gradually lowered in accordance with the change of the potential Vn applied to the N-type semiconductor region3from Vn1 to a potential Vn2 that is higher than Vn1. The width of the depletion layer formed in the P-type semiconductor region2also changes in accordance with the change of the potential Vn.

FIG. 1Cillustrates a state in which the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3almost disappears.FIG. 2Cillustrates a potential along IIC-IIC inFIG. 1C. At this time, the potential Vn2 is applied to the N-type semiconductor region3. In the state ofFIG. 1C, all the signal charges accumulated in the N-type semiconductor region1are transferred to the N-type semiconductor region3. That is, complete depletion transfer can be performed.

A voltage used for the above-described complete depletion transfer is decreased as the impurity concentration in the P-type semiconductor region2is lower, and in contrast, the voltage is increased as the impurity concentration in the P-type semiconductor region2is higher. The impurity concentrations in the P-type semiconductor region2and the N-type semiconductor region12are set such that a reverse bias is generated to such an extent that the avalanche multiplication is caused in the P-type semiconductor region2and the N-type semiconductor region3during at least part of the period in which the signal charge is transferred as described above.

It should be noted that, in the dark state, it is considerable that the potential in the N-type semiconductor region1changes to some extent when the change fromFIG. 1BtoFIG. 1Coccurs. However, since the P-type semiconductor region2is closer to the N-type semiconductor region3where the potential Vn is supplied than the N-type semiconductor region1, the P-type semiconductor region2is more affected by the influences by the change of the potential Vn. The potential at the depleted part in the P-type semiconductor region2is more likely to be changed. As a result, the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3can be eliminated.

According to the present exemplary embodiment, inFIG. 1C, a state is established in which the neutral region remains in the P-type semiconductor region9and the P-type semiconductor region10. In accordance with this configuration, since the potential Vp can be supplied to a large part of the surrounding of the N-type semiconductor region1, the change of the potential in the N-type semiconductor region1can be suppressed to be small inFIG. 2BandFIG. 2C. Therefore, even when the change amount of the potential Vn is small, the complete transfer of the charges can be performed. It should be noted that the entirety of the P-type semiconductor region9or the P-type semiconductor region10may be depleted in the progress of the change of the potential Vn from Vn0 to Vn2.

As described above, the height of the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3can be controlled by controlling the potential Vn. Therefore, the light detection apparatus according to the present exemplary embodiment can selectively implement the operation for accumulating the signal charge in the N-type semiconductor region1and the operation for transferring the signal charge from the N-type semiconductor region1to the N-type semiconductor region3with this configuration.

Herein, the descriptions have been provided that the avalanche multiplication is preferably caused when the signal charge is transferred inFIG. 1B. However, while the potential Vn changes from Vn0 to Vn2, a timing of the application of the reverse bias at which the avalanche multiplication is caused and a timing of the coupling of the depletion layer in the P-type semiconductor region2(that is, a timing when the potential barrier starts to be lowered) may be shifted from each other. Either the timing of the application of the reverse bias at which the avalanche multiplication is caused or the timing of the coupling of the depletion layer in the P-type semiconductor region2may be ahead of the other timing. A saturated charge amount in the N-type semiconductor region1may be determined by the potential barrier at the time of a bias condition when signal detection can be started by the avalanche multiplication.

In the above-described explanation, the example in which the potential Vn applied to the potential control section5is controlled has been described. On the other hand, to change the height of the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3, the potential Vp applied to the P-type semiconductor region2may be changed while the potential Vn is fixed. According to the present exemplary embodiment, the height of the potential barrier is changed by changing Vp. In this case too, the period in which the signal charge is accumulated in the N-type semiconductor region1and the period in which the signal charge is transferred from the N-type semiconductor region1to the N-type semiconductor region3can be controlled.

A case where Vp is changed will be described with reference toFIGS. 3A to 3CandFIGS. 4A to 4C. To facilitate the descriptions, it is assumed inFIGS. 3A to 3Cthat a fixed positive potential VDD is applied to the N-type semiconductor region.

FIG. 3Aillustrates the photoelectric conversion unit70in a state in which the signal charge is accumulated in the N-type semiconductor region1, andFIG. 4Aillustrates a potential along IVA-IVA inFIG. 3A. InFIG. 3A, a potential difference for the depletion voltage is caused between the P-type semiconductor region2and the N-type semiconductor region1. At this time, Vp is set as Vp0. As illustrated inFIG. 3A, since the surrounding of the N-type semiconductor region1is surrounded by the P-type semiconductor region2, the potential in the N-type semiconductor region1changes following the change of the potential in the P-type semiconductor region2.

The potential change in a case where Vn is fixed and Vp is changed in this manner has been described. However, the potential distribution inside the semiconductor region is determined by a relative relationship between the potential of the potential control section5and the potential of the potential control section6. Therefore, which one of the potential in the P-type semiconductor region2and the potential in the N-type semiconductor region3is changed to perform the control only depends on which one of the potentials will be simply set as a reference, and this is an equivalent configuration for P-N junction elements of the PD and the AD. For this reason, the explanations with reference toFIGS. 1A to 1CandFIGS. 2A to 2Care basically applied toFIGS. 3A to 3CandFIGS. 4A to 4C. Hereinafter, only main points in the respective drawings will be described.

FIG. 3Billustrates a state in which the depletion layer in the P-type semiconductor region2in the surrounding of the N-type semiconductor region1and the depletion layer in the P-type semiconductor region2in the surrounding of the N-type semiconductor region3continuously extend.FIG. 4Billustrates a potential along IVB-IVB inFIG. 3B. At this time, the potential Vp1 that is lower than Vp0 is applied to the P-type semiconductor region2. This state is similar to the state described with reference toFIG. 1BandFIG. 2B, and the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3is being lowered. At this time, since almost the entire surrounding of the N-type semiconductor region1is surrounded by the neutral region in the P-type semiconductor region2, the potential in the N-type semiconductor region1changes by approximately the same amount as Vp. As a result, the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3is being lowered.

FIG. 3Cillustrates a state in which the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3disappears.FIG. 4Cillustrates a potential along IVC-IVC inFIG. 3C. At this time, the potential Vp2 that is lower than Vp1 is applied to the P-type semiconductor region2. Similarly as in the explanations with reference toFIG. 1CandFIG. 2C, in the state ofFIG. 3C, all the signal charges accumulated in the N-type semiconductor region1are transferred to the N-type semiconductor region3. That is, the complete depletion transfer can be performed.

Hereinafter, a case will be described where the photoelectric conversion unit70described above is used as the light detection apparatus, in particular, an imaging apparatus.

The light detection apparatus according to the first exemplary embodiment of the present invention will be described with reference toFIGS. 1A to 1CtoFIG. 9.

FIG. 5is a schematic diagram illustrating the light detection apparatus according to the present exemplary embodiment.FIG. 6is a cross sectional view of the light detection apparatus along VI-VI inFIG. 5.FIG. 7is an equivalent circuit diagram of a light detection element80included in the light detection apparatus.FIG. 8is a timing chart for describing an operation of the photoelectric conversion unit70.FIG. 9illustrates a change of a potential in a signal transfer operation of the light detection element.

The light detection apparatus is constituted by laminating a plurality of substrates as illustrated inFIG. 5andFIG. 6. For example, the light detection apparatus is constituted by laminating a substrate100including the plurality of photoelectric conversion units70and a substrate110including a counter circuit and an inverter circuit which will be described below on each other. The photoelectric conversion unit70, the counter circuit, and the inverter circuit constitute the light detection element80. That is, a circuit group constituting the single light detection element80is arranged while being separated into the substrate100and the substrate110. With this configuration, increase in the area of the light detection apparatus in the plane view can be avoided while increase in speed or scale of a digital circuit including the counter circuit is realized.

It should be noted that a plurality of photoelectric conversion units and counter circuits may be arranged in parallel on a single substrate. As an alternative to the above-described configuration, the entirety of the light detection element80may be arranged on the single substrate.

According to the present exemplary embodiment, a first surface of the substrate100is a light incidence surface. InFIGS. 1A to 1C,FIGS. 3A to 3C, andFIG. 6, a surface on an upper side among two surfaces included in the substrate100is the first surface. That is, the light is incident on the light detection apparatus from the upper side inFIGS. 1A to 1C,FIGS. 3A to 3C, andFIG. 6. In a case where the exemplary embodiment of the present invention is applied to the imaging apparatus, as illustrated inFIG. 6, optical members such as a color filter130and a micro lens120are arranged at a side of the first surface of the substrate100, that is, a side of the light incidence surface. A gate electrode of a transistor and a metallic wiring layer are arranged at a side of a second surface opposite to the first surface of the substrate100. The substrate110is located at a side of the second surface of the substrate100with respect to the substrate100. In the following descriptions, a side where light is incident is set as an upper side, and an opposed side is set as a lower side.

As illustrated inFIG. 6, the substrate100and the substrate110are affixed to each other on a junction surface. The junction surface is constituted by a metal such as copper and an insulator such as an oxide film. The metal constituting the junction surface may also constitute wiring that connects an element arranged on the substrate100such as the photoelectric conversion unit70to a circuit arranged on the substrate110such as a counter.

As illustrated inFIG. 7, the light detection element80includes the photoelectric conversion unit70, an inverter circuit7functioning as a wave shaping unit, and a counter circuit8. The light detection apparatus includes the plurality of light detection elements80. For this reason, as explained with reference toFIG. 5, the photoelectric conversion unit70is arranged on the substrate100. In accordance with this, the plurality of inverter circuits7and the plurality of counter circuits8are arranged on the substrate110.

The photoelectric conversion unit70includes a photoelectric conversion section60(corresponding to the above-described PD) and a charge multiplication section50(corresponding to the above-described AD). The photoelectric conversion section60and the charge multiplication section50are respectively indicated by circuit symbols of diodes. An anode of the photoelectric conversion section60and an anode of the charge multiplication section50are connected to each other. In other words, the anode of the photoelectric conversion section60and the anode of the charge multiplication section50constitute a common node. The potential control section6is connected to the common node. According to the present exemplary embodiment, when the potential control section6controls a potential applied to the common node, the period in which the signal charge is accumulated in the photoelectric conversion section60and the period in which the accumulated signal charge is transferred to the charge multiplication section50are switched.

As illustrated inFIGS. 3A to 3CandFIG. 6, a cathode of the photoelectric conversion section60is constituted by the N-type semiconductor region1. The anode of the photoelectric conversion section60and the anode of the charge multiplication section50are constituted by the P-type semiconductor region2. A cathode of the charge multiplication section50is constituted by the N-type semiconductor regions3and12. According to the present exemplary embodiment, a state in which the signal charge is transferred from the cathode of the photoelectric conversion section60to the cathode of the charge multiplication section50and a non-transfer state are controlled by controlling the potential applied from the potential control section6to the electric the P-type semiconductor region2. For this reason, according to the present exemplary embodiment, the P-type semiconductor region2and the potential control section6correspond to a control unit. It should be noted that it is sufficient when the potential control section6has a function for performing the above-described potential control, and the specific circuit configuration is not particularly limited. For this reason, an exemplification thereof will be omitted herein.

The charge multiplication section50is an AD configured to perform multiplication of a photocurrent by performing the avalanche multiplication of the signal charge transferred from the cathode of the photoelectric conversion section60in the period in which the signal charge is transferred from the cathode of the photoelectric conversion section60to the cathode of the charge multiplication section50. Although the detail will be described below, when a single signal charge among a plurality of signal charges generated in the photoelectric conversion section60is transferred to the charge multiplication section50in a state in which application of a reverse bias voltage is performed to such an extent that electron avalanche is formed, the signal charge is accelerated by an electric field generated by the N-type semiconductor region3and the P-type semiconductor region2. Then, a current based on the plurality of electrons (and holes) is generated.

As described above, during at least part of the period in which the signal charge is transferred from the cathode of the photoelectric conversion section60to the cathode of the charge multiplication section50, the reverse bias voltage to such an extent that the electron avalanche is caused is applied to the charge multiplication section50. In other words, the reverse bias voltage having a magnitude higher than or equal to a breakdown voltage is applied to the charge multiplication section50during at least part of the period in which the signal charge is transferred. At this time, the charge multiplication section50basically operates in a Geiger mode. Therefore, the avalanche multiplication of the signal charge occurs. For example, inFIG. 7, the positive power source potential VDD is applied to the potential control section5, and the negative potential Vp is applied to the potential control section6. The potential VDD is supplied to the cathode of the charge multiplication section50through a resistance4in a state in which the avalanche current is not generated. For this reason, VDD−Vp becomes the reverse bias voltage applied to the charge multiplication section50.

The resistance4is connected to the potential control section5and the cathode of the charge multiplication section50. An operational relationship between the resistance4and the charge multiplication section50will be described. When the single signal charge is transferred to the charge multiplication section50in the period in which the reverse bias voltage to such an extent that the electron avalanche is caused is applied to the charge multiplication section50, multiplication of the photocurrent occurs by the avalanche multiplication. A current obtained by the signal charge after the multiplication flows to a connection node of the charge multiplication section50, the inverter circuit7, and the resistance4. The potential at the cathode of the charge multiplication section50decreases due to voltage drop based on this current, the electron avalanche is not formed in the charge multiplication section50. With this configuration, the avalanche multiplication in the charge multiplication section50stops. Thereafter, since the potential VDD of the potential control section5is supplied to the cathode of the charge multiplication section50via the resistance4, the potential supplied to the cathode of the charge multiplication section50returns to the potential VDD. That is, the operating region of the charge multiplication section50is set in the Geiger mode again.

One of roles of the resistance4is to temporarily stop the avalanche multiplication by the signal charge and to set the operative region of the charge multiplication section50in the Geiger mode again immediately after the stop.

The potential at the cathode of the charge multiplication section50decreases by the avalanche current by transferring the signal charge to the charge multiplication section50. Since the cathode of the charge multiplication section50is connected to the inverter circuit7, an output of the inverter circuit7becomes a Low level when the potential at the cathode is higher than the threshold of the inverter circuit7. On the other hand, the output of the inverter circuit7becomes a High level when the potential at the cathode is lower than the threshold of the inverter circuit7. That is, the output of the inverter circuit7is binarized. As a result, a rectangular pulse is output from the inverter circuit7in accordance with the presence of the signal charge that has been transferred from the N-type semiconductor region1to the N-type semiconductor region3and subjected to the avalanche multiplication.

The inverter circuit7is connected to a circuit unit configured to count the number of generation times of the avalanche current such as, for example, the counter circuit8. The counter circuit8counts the number of pulses output from the inverter circuit7and outputs an accumulated count value. That is, when the pulse from the inverter circuit7is received, the counter circuit8changes the count value. As described above, the inverter circuit7generates the pulse on the basis of the presence or absence of the avalanche current generated by the avalanche multiplication. The counter circuit8counts the number of generation times of the avalanche current generated when at least one signal charge is transferred to the charge multiplication section50and also the avalanche multiplication is caused.

Next, the avalanche multiplication caused in the charge multiplication section50will be described. As described above, the charge multiplication section50includes the N-type semiconductor region3, the N-type semiconductor region12, and the P-type semiconductor region2, and the N-type semiconductor region including the N-type semiconductor region3and the N-type semiconductor region12and the P-type semiconductor region2constitute the P-N junction.

The reverse bias voltage for causing the avalanche multiplication in the charge multiplication section50is applied to the P-N junction in the charge multiplication section50during at least part of the period in which the signal charge is transferred from at least the photoelectric conversion section60. That is, a high electric field for accelerating the charge to such an extent that the avalanche multiplication is caused is generated in the depletion layer in the vicinity of the P-N junction in the charge multiplication section50.

When one signal charge among the plurality of signal charges generated in the photoelectric conversion section60and accumulated is transferred to the depletion layer of the charge multiplication section50, the single signal charge is accelerated by the above-described high electric field. With this configuration, a current based on the plurality of electrons (and holes), that is, an avalanche current is generated.

As already described, the voltage applied to the charge multiplication section50is controlled by controlling the potential applied to the N-type semiconductor region3or the P-type semiconductor region2.

Hereinafter, the drive of the photoelectric conversion unit70will be described. In the following descriptions, it is assumed that the positive power source potential VDD is applied to the potential control section5, and the negative potential Vp is applied to the potential control section6, that is, the operation described with reference toFIGS. 3A to 3CandFIGS. 4A to 4Cis performed.

FIG. 8is a timing chart for describing the drive of the photoelectric conversion unit70. InFIG. 8, the horizontal axis indicates the time, and the vertical axis indicates the potential Vp applied by the potential control section6.

A time when the potential Vp is the potential Vp0 corresponds to a time when the charge multiplication section50is in a non-avalanche state. That is, the height of the potential barrier is restricted to a range where the avalanche multiplication of the signal charge is not caused. That is, the potential Vp0 is set such that the reverse bias voltage applied to the charge multiplication section50becomes lower than a minimum voltage for causing the avalanche multiplication. The potential barrier is formed between the N-type semiconductor region1and the N-type semiconductor region3when the potential Vp is the potential Vp0. For example, Vp0 is −18 V.

The potential control section6performs control such that the potential Vp is gradually decreased from the potential Vp0. When the potential Vp becomes lower than or equal to the potential Vp3, a state is established in which the charge multiplication section50causes the avalanche multiplication. In other words, in a case where the potential Vp is lower than or equal to the potential Vp3, the reverse bias voltage applied to the charge multiplication section50is higher than the breakdown voltage.

When the potential Vp is gradually decreased from the potential Vp0, the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3is lowered. When the potential Vp reaches Vp2, the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3disappears. In this state, all the signal charges accumulated in the photoelectric conversion section60are transferred to the charge multiplication section50. For example, Vp3 is −20 V, and Vp2 is −25 V.

It should be noted that, according to the present exemplary embodiment, the potential Vp2 at which the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3disappears is lower than the minimum potential Vp3 at which the avalanche multiplication is caused by the reverse bias voltage applied to the charge multiplication section50. That is, when the potential Vp is decreased from Vp0, first, the charge multiplication section50is set in an avalanche state. Thereafter, the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3disappears. This situation has been already described with reference toFIGS. 3A to 3CandFIGS. 4A to 4C.

As illustrated inFIG. 7, the photoelectric conversion unit70has a “signal accumulation operation period” in which the signal charge is accumulated in the photoelectric conversion section60and a “signal transfer operation period” in which the signal charge generated by the photoelectric conversion section60is transferred to the charge multiplication section50and read out.

During the signal accumulation operation period, Vp is Vp0, corresponding to the state illustrated inFIG. 3AandFIG. 4A. During the signal transfer operation period, the potential Vp is lower than Vp0 and also higher than or equal to Vp2, corresponding to the state illustrated inFIG. 3BandFIG. 4Band alsoFIG. 3CandFIG. 4C. The potential Vp is gradually decreased from Vp0 to Vp2 to transfer the signal charge during the signal transfer operation period. The signal transfer operation period includes a period in which the charge multiplication section50is in the non-avalanche state and a period in which the charge multiplication section50is in the avalanche state and the transferred signal charge is read out. The period of the non-avalanche state is a period in which the potential Vp is lower than the potential Vp0 and higher than the potential Vp3. The period in which the avalanche state is established and the transferred signal charge is read out is a period in which the potential Vp is lower than or equal to the potential Vp3. As illustrated inFIG. 8, the period in which the potential Vp is lower than or equal to the potential Vp3 is set as a “signal readout operation period”.

During the signal readout operation period, the signal charges accumulated in the N-type semiconductor region1at a point in time when Vp=Vp3 is established are transferred to the N-type semiconductor region3and read out in a period in which Vp changes from Vp3 to Vp2. Since the plurality of signal charges are accumulated in the N-type semiconductor region1, the potential is gradually changed from Vp3 to Vp2. That is, the change from Vp3 to Vp2 takes a predetermined period of time, and the potential is gradually decreased. When the plurality of signal charges are transferred to the charge multiplication section50substantially at the same time, count loss may occur since the number of counts by the counter circuit8becomes 1. In contrast to this, when the potential is gradually decreased, the plurality of signal charges are hardly transferred at the same time, the count loss hardly occurs. The potential is preferably changed in a slope manner as illustrated inFIG. 8but may also be changed in a step manner.

FIG. 9illustrates the change of the potential Vp during the signal transfer operation period, and the change of the potential in the N-type semiconductor region3and the change of the output potential of the inverter circuit7based on the change of the potential Vp. InFIG. 9, T1, T2, T3, T4, and T5indicate timings when the signal charge is transferred from the N-type semiconductor region1to the N-type semiconductor region3. That is,FIG. 9represents a situation where five signal charges in total are transferred. As described above, the charge multiplication section50is set in the avalanche state upon application of the potential lower than or equal to Vp3.

InFIG. 9, at the point T1in time, Vp does not yet reach Vp3. The inverter circuit7shapes the waveform when the potential in the N-type semiconductor region3is higher than or equal to a predetermined potential. For example, the predetermined potential is V3 inFIG. 9. When the potential lower than or equal to V3 is detected, the inverter circuit7shapes the waveform.

The signal charge transferred at T1causes an impact ionizing current to some extent, but the potential lower than or equal to V3 is not obtained. At T1, since the potential in the N-type semiconductor region3does not reach the potential at which the waveform is shaped by the inverter circuit7, the inverter circuit7does not shape the waveform. Therefore, the counter circuit8does not perform counting.

InFIG. 9, at T2, T3, T4, and T5when Vp becomes the potential lower than Vp3, the respective signal charges to be transferred cause the avalanche current to set the potential in the N-type semiconductor region3to be lower than or equal to V3. Therefore, a count pulse is generated at the output of the inverter circuit7and counted in the counter circuit8.

As may be understood from the above-described explanation, the period in which Vp changes from Vp0 to Vp2 is the signal transfer operation period in which the charge is transferred from the N-type semiconductor region1to the N-type semiconductor region3. The other period becomes the signal accumulation operation period in which the signal charge is accumulated in the N-type semiconductor region1. The period in which Vp changes from Vp3 to Vp2 in the signal transfer operation period is the signal readout operation period in which the charge transferred from the N-type semiconductor region1to the N-type semiconductor region3is counted as the signal charge. It should be noted that, to be precise, the signal accumulation is also performed in parallel with the signal transfer when the light incidence occurs even during the signal transfer operation period. On the other hand, during the signal accumulation operation period, only the signal accumulation is performed, and the signal transfer is not performed. It should be noted that a timing when the signal charge is actually started to be transferred in the signal transfer operation period illustrated inFIG. 8corresponds to a timing when Vp falls slightly below Vp0, and the signal transfer operation period may partially include a period in which the signal is not transferred in some cases. InFIG. 9, a case where the potential of Vp at which the signal transfer starts is higher than Vp3 is assumed, and the transfer also occurs at the timing T1, but the potential of Vp at which the signal transfer is actually started may be lower than Vp3 in some cases.

Next, the effects of the present exemplary embodiment will be described. The photoelectric conversion unit70according to the present exemplary embodiment takes the first state in which the signal charge is accumulated in the photoelectric conversion section60and the second state in which the avalanche multiplication is caused by the signal charge transferred from the photoelectric conversion section60to the charge multiplication section50. In accordance with the above-described configuration, a probability that an unwanted charge is counted can be reduced.

The signal charge is accumulated in the photoelectric conversion section60during the signal accumulation operation period. Thereafter, the signal charge is counted during at least part of the signal transfer operation period. While the signal charge is accumulated in the photoelectric conversion section60in these periods, the generated signal charge does not need to be counted. For this reason, the high reverse bias at which the avalanche multiplication is caused does not need to be applied to the photoelectric conversion section60. Therefore, the signal charge can be accumulated in a state in which the generation of the unwanted charge is suppressed as compared with a case where the high reverse bias is regularly applied to the region where the signal charge is generated. Thereafter, the period in which the accumulated signal charges is read out is separately prepared, and as a result, the probability that the unwanted charge is counted can be reduced.

In one operation example according to the present exemplary embodiment, during the signal accumulation operation period, the reverse bias voltage for setting the charge multiplication section50in the non-avalanche state is applied to the charge multiplication section50. With this configuration, the avalanche multiplication is not caused even when the unwanted charge is generated in the charge multiplication section50or the unwanted charge enters the charge multiplication section50in this period. For this reason, the probability can be reduced that more unwanted charges generated by the high electric field in the charge multiplication section50than the case of the low electric field are counted as noise. Therefore, the generation of the noise can be further reduced as compared with the related-art light detection apparatus that uses the avalanche multiplication such as the related-art SPAD in which many unwanted charges are generated by the application of the high electric field during the entire operation period, and also the generated unwanted charges are regularly counted. It should be noted that a voltage comparable with or lower than the reverse bias of the photoelectric conversion section60(depletion voltage in the N-type semiconductor region1) may be applied to the charge multiplication section50as the reverse bias voltage for setting the charge multiplication section50in the non-avalanche state during the signal accumulation operation period.

In another operation example, the reverse bias voltage at which the charge multiplication section50is set in the avalanche state may be regularly applied to the charge multiplication section50. In this case, the light detection element is configured in a manner that the avalanche current generated by the unwanted charge during a period other than the signal transfer operation period is not to be counted. A method of avoiding the counting of the avalanche current includes setting the inverter circuit7to be inactive, resetting the counter circuit8at the beginning of the signal readout period, or the like. In this case too, since the accumulation of the signal charge is performed in the photoelectric conversion section60that is separated from the charge multiplication section50, the probability that the unwanted charge is counted can be reduced as described above.

To further increase the effects of the present exemplary embodiment, the signal readout operation period is preferably short. According to the present exemplary embodiment, the unwanted charge generated in the charge multiplication section50or the lower surface of the substrate100is counted only during the signal readout operation period. During the signal accumulation operation period, even when the unwanted charge is generated in the charge multiplication section50or the lower surface of the substrate100, the unwanted charge is not accumulated in the N-type semiconductor region1because of the potential barrier by the P-type semiconductor region2and flows off to the N-type semiconductor region3without being counted. The signal readout operation period is preferably shorter than the signal accumulation operation period as described above, but in a case where the incident light is to be detected in a very short period of time, the signal accumulation operation period may be shorter than the signal readout operation period.

On the other hand, when the unwanted charge is generated on the upper surface of the substrate100, the unwanted charge may be accumulated in the N-type semiconductor region1, and the unwanted charge may be counted during the signal readout operation period. In contrast to this, the reverse bias applied to the N-type semiconductor region1is lower than the reverse bias applied to the charge multiplication section50in the avalanche state. In the related-art SPAD, the photoelectric conversion is also performed in the AD where a dark current generation speed is high because of the application of the high voltage. Therefore, according to the present exemplary embodiment, the photoelectric conversion section (PD) to which only the low reverse bias voltage is applied where the generation of the dark current can be thus suppressed is separated from the high electric field section (AD). For this reason, a period in which an unwanted dark electron generated in the AD is counted can be shortened as compared with the related art, and the unwanted charges can be reduced as compared with the related-art SPAD.

The dark current generation on the upper surface of the substrate100can be suppressed by an element structure. This is the same situation where the dark current is accumulated in the photodiode of the CMOS sensor, and the dark current is suppressed by use of a buried-type photodiode in the CMOS sensor. The generation of the dark current can be suppressed when the above-described buried-type photodiode is adopted as one of exemplary embodiments.

Hereinafter, descriptions will be provided on how the unwanted charges caused by the dark current or the like are reduced as one of additional effects attained by the present exemplary embodiment.

As illustrated inFIGS. 1A to 1CandFIGS. 3A to 3C, the N-type semiconductor region1is surrounded by the P-type semiconductor regions2,9, and10and has the buried structure similarly as in the photoelectric conversion section of pixels in the so-called CMOS sensor. Since the generation source of the unwanted charge particularly exists on the surface of the substrate100, when the N-type semiconductor region1is spaced from the surface of the substrate100, it is possible to establish a state in which the dark current is hardly generated. For this reason, the P-type semiconductor region9is set to have a concentration at which a semiconductor interface section is not depleted. As described above, in a case where the impurity concentration in the P-type semiconductor region2is set to be low for the complete depletion transfer, the impurity concentration in the P-type semiconductor region9may be higher than the impurity concentration in the P-type semiconductor region2as a result in some cases. Since the P-type semiconductor region10is arranged on a side surface of the N-type semiconductor region1, crosstalk between the adjacent photoelectric conversion units70can be reduced.

It should be noted that, according to the present exemplary embodiment, the P-type semiconductor region9constituting part of the surface of the substrate100is arranged on the upper surface of the N-type semiconductor region1. The configuration is not limited to this, and a negative fixed charge film may be arranged on the upper surface of the N-type semiconductor region1, and a hole accumulation layer may be formed in the vicinity of the upper surface of the substrate100in the N-type semiconductor region1. In this case too, the dark current is hardly generated. For example, hafnium oxide, aluminum oxide, tantalum oxide, and the like can be used as the negative fixed charge film.

As illustrated inFIG. 10, the P-type semiconductor region90may be arranged on part of the lower surface of the substrate100. With this configuration, the unwanted charge generated on the lower surface of the substrate100is recombined in the P-type semiconductor region90, and the dark currents themselves generated on the lower surface of the substrate100can be reduced.

According to the present exemplary embodiment, the signal charge is transferred by decreasing the potential applied to the P-type semiconductor region2and increasing the reverse bias voltage. The configuration is not limited to this, and as described with reference toFIGS. 1A to 1CandFIGS. 2A to 2C, the signal charge may be transferred by increasing the potential in the N-type semiconductor region3and increasing the reverse bias voltage. Even in a case where the photoelectric conversion unit70described above is used, the effects of the present invention can be attained.

According to the present exemplary embodiment, the P-type semiconductor region2is continuously arranged on the lower surface of the N-type semiconductor region1. That is, the P-type semiconductor region2is arranged on the entire surface of the lower surface of the N-type semiconductor region1. With this configuration, the potential barrier in the P-type semiconductor region2is likely to be formed, and the signal charge is likely to be accumulated in the N-type semiconductor region1. The P-type semiconductor region2is set to have an appropriate concentration such that this potential barrier becomes sufficiently low at the time of the signal transfer. The configuration is not limited to this, and a gap may be partially provided in the P-type semiconductor region2as long as the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3is formed. For example, the gap may be provided between a first portion of the second semiconductor region2and a second portion of the second semiconductor region2in a region overlapped with the N-type semiconductor region3in the plane view. An N-type semiconductor region may be arranged in the gap in the P-type semiconductor region2. This N-type semiconductor region may have an impurity concentration comparable with that of the N-type semiconductor region1or that of the N-type semiconductor region12or have an impurity concentration different from those impurity concentrations.

The potential Vp does not need to be slowly changed depending on cases during the signal transfer operation period according to the present exemplary embodiment. For example, in a case where only the presence or absence of light incidence is detected or the like, the potential Vp may be abruptly changed from Vp0 to Vp2 even when the plurality of signal charges are accumulated. For this reason, it is sufficient when at least two values are set for the potential Vp.

According to the present exemplary embodiment, the charge multiplication section50is set in the non-avalanche state during the signal accumulation operation period. With this configuration, power consumption in a case where intense light is incident can be reduced as compared with the related-art SPAD. That is, since a signal charge generation speed is significantly increased in the SPAD in a case where the intense light is incident, a state is almost established in which the avalanche current continues flowing. The power consumption is increased by this current, and also, a so-called pileup state is established in which the counting of the signal charge is not much performed. Therefore, even when the intense light is incident in the operation according to the exemplary embodiment of the present invention, the time when the state is almost established in which the avalanche current continues flowing is limited to only the signal readout period. Thus, the noise reduction effects and also the power consumption reduction effects are increased as the signal readout period is shorter as compared with the signal accumulation operation period.

On the other hand, it has been described that the inverter circuit7and the counter circuit8may be set as OFF by setting the charge multiplication section50in the avalanche state during the signal accumulation operation period. When the intense light is incident in the above-described operation, the N-type semiconductor region1corresponding to the signal charge accumulation section reaches saturation to cause the signal charges to overflow, and the state is almost established in which the avalanche current continues flowing also at the time of the signal accumulation operation. Thus, the power consumption is comparable with the related-art SPAD in this operation. However, the noise reduction effects are attained.

According to the present exemplary embodiment, the inverter circuit7is substantially a comparator having a threshold at V3. Therefore, the comparator may be used instead of the inverter circuit7. In addition, another circuit that performs conversion into a predetermined physical quantity in proportion to the number of counts such as, for example, a charge amount and stores the physical quantity may be used as the counter.

Second Exemplary Embodiment

The light detection apparatus according to a second exemplary embodiment of the present invention is an imaging sensor constituted by disposing a plurality of photoelectric conversion units of the exemplary embodiment of the present invention.

FIG. 11is an equivalent circuit diagram of the light detection apparatus according to the present exemplary embodiment. An operation of the light detection apparatus according to the present exemplary embodiment is basically the same as the first exemplary embodiment, but the circuit part is illustrated in slightly more detail thanFIG. 7to describe respective operation modes as the light detection apparatus. InFIG. 11, the same parts as those inFIG. 7are assigned with the same reference numerals, and descriptions thereof are omitted.

All the configurations of the photoelectric conversion unit70(the photoelectric conversion section60and the charge multiplication section50), the potential control section6, and the resistance4are the same as those of the first exemplary embodiment. For this reason, all the descriptions with regard to those elements according to the first exemplary embodiment will be used for the present exemplary embodiment.

An inverter that can select ON and OFF by a switch is used as the light detection apparatus according to the present exemplary embodiment.

As illustrated inFIG. 11, the light detection apparatus according to the present exemplary embodiment includes a P-type metal-oxide semiconductor (MOS) transistor15, a P-type MOS transistor16, and an N-type MOS transistor13. An input terminal14for supplying a predetermined potential and determining a constant current amount is connected to the transistor13. An input terminal17for controlling ON and OFF of the transistor16is connected to a gate of the transistor16.

As illustrated inFIG. 11, a gate of the transistor15is connected to the cathode of the charge multiplication section50. A drain of the transistor15is connected to a drain of the transistor13. A source of the transistor13is grounded, and a constant current is supplied to the drain of the transistor15via the transistor13. A source of the transistor15is connected to a drain of the transistor16. A source of the transistor16is connected to the potential control section5to which the positive power source potential VDD is supplied. Since the transistor16operates as a switch, when the transistor16is in an ON state, the positive power source potential VDD is supplied to the source of the transistor15. The potential at the cathode of the charge multiplication section50is supplied to the gate of the transistor15. When a potential at the gate of the transistor15exceeds a predetermined threshold, a count pulse is output, and the count pulse is input to the counter circuit8.

An input terminal18controls resetting of the counter circuit8. The counter circuit8may be reset by the input terminal18before the signal readout operation period.

MOS transistors for outputting bit information are connected to respective bits of the counter circuit8. In the present specification, the MOS transistors connected to the respective bits are collectively referred to as a MOS transistor group19.

An input terminal20is connected to gates of the MOS transistor group19for switching and controls ON and OFF of the MOS transistor group19. The pieces of bit information of the counter circuit8from the respective MOS transistors of the MOS transistor group19are output from output terminals21,22,23, and24at the same time.

For the sake of convenience for the descriptions, inFIG. 11, the bit count of the counter circuit8is set as 4, and the number of switches of the MOS transistor group19is set as 4, but the actual bit count may be set as a much higher number. On the other hand, one switch may be used, and the respective bit information of the counter circuit8may be output in series.

FIG. 12is an overall view of the light detection apparatus. For the sake of convenience for the descriptions, the light detection elements25are disposed in two rows and two columns Each of the light detection elements25includes a circuit illustrated inFIG. 11. It should be noted that the light detection element25is equivalent to a pixel in the imaging sensor.

The light detection apparatus includes a vertical scanning circuit26configured to sequentially select rows. The light detection apparatus also includes a first row selecting line27that is output from the vertical scanning circuit26to be connected to the input terminals20of the light detection elements25disposed in the first row and a second row selecting line28that is output from the vertical scanning circuit26to be connected to the input terminals20of the light detection elements25disposed in the second row. The light detection apparatus also includes four vertical output lines29which are respectively connected to the output terminals21,22,23, and24of the light detection elements25in the first column and from which the respective pieces of bit information of the counter circuits8of the respective pixels in the first column are output. The light detection apparatus also includes four vertical output lines30which are respectively connected to the output terminals21,22,23, and24of the pixels in the second column and from which the respective pieces of bit information of the counter circuits8of the respective pixels in the second column are output. The light detection apparatus also includes preamplifiers31connected to the respective vertical output lines. The light detection apparatus also includes a horizontal scanning circuit32configured to sequentially select respective columns where outputs of the four preamplifiers in the respective columns are output at the same time. The preamplifier outputs in the respective columns are sequentially output from output terminals33,34,35, and36in accordance with the horizontal scanning circuit32.

Although those are not directly illustrated inFIG. 12, the potential control sections5, the potential control sections6, the input terminals14, the input terminals17, and the input terminals18included in the respective light detection elements25are respectively connected commonly in all the light detection elements.

FIG. 13is a timing chart for describing an operation mode including a global electronic shutter function. The horizontal axis is a temporal axis.FIG. 13illustrates a change of the potential of the potential control section6.FIG. 13also illustrates a state in which the input terminal17, the input terminal18, the first row selecting line27, and the second row selecting line28are controlled to be High or Low.

When the input terminal17is at a Low level, the inverter that detects the avalanche current when the P-type MOS transistor16becomes conductive is set in an operative state. In contrast to this, when the input terminal17is at a High level, the inverter is set in a non-operative state.

When the input terminal18is at the High level, the counter circuit8is set in the operative state. When the input terminal18is at the Low level, all the bits of the counter circuit8are reset to establish a state in which the count value of the counter circuit8is zero.

FIG. 13illustrates 1 frame period corresponding to a period in which signals for constituting a single frame are generated in the respective light detection elements25to perform signal output. According to the present exemplary embodiment, the signal generation includes the accumulation of the signal charge by the photoelectric conversion section60, the transfer of the signal charge from the photoelectric conversion section60to the charge multiplication section50, the multiplication of the signal charge by the charge multiplication section50, the counting operation by the counter circuit8, and the like.

According to the present exemplary embodiment, the signal accumulation operation periods in the plurality of light detection elements25that perform the signal output during mutually different periods are matched with each other. A so-called global electronic shutter operation is performed.

As illustrated inFIG. 13, in a period in which the signals for the n-th frame are generated, that is, a frame period for the n-th frame, the signals for the (n−1)-th frame corresponding to the previous frame are output. As the signal output operation, the count value based on the accumulated signal charges is output from the counter circuit8to the vertical output line. At this time, the count values are sequentially output row by row. Specifically, while the first row selecting line27is at High, the count value of the counter circuit8of the light detection element25in the first row in the first column is output to the vertical output line29. In addition, during the same period, the count value of the counter circuit8of the light detection element25in the first row in the second column is output to the vertical output line30. Those count values are output by the horizontal scanning circuit32from the output terminals33,34,35, and36in the stated order of the first column and the second column. Similarly, while the second row selecting line28is High, the count values of the counter circuits8of the light detection elements25in the second row are output from the output terminals33,34,35, and36.

After the data output in this previous frame is ended, the input terminal18turns to the Low level, and all the counter circuits8are reset. The resetting of the counter circuits8may be performed before the signal readout operation in the next frame (the n-th frame) is started.

According to the present exemplary embodiment, as illustrated inFIG. 13, the 1 frame period includes a plurality of signal accumulation operation periods and a plurality of signal transfer operation periods. The signal accumulation operation period and the signal transfer operation period are respectively similar to those described according to the first exemplary embodiment. Although not illustrated in the drawing, at least part of the signal transfer operation period is the signal readout operation period.

According to the present exemplary embodiment, after one signal transfer operation period is ended, a predetermined interval elapses, and the next signal accumulation operation period is then started. That is, the 1 frame period may also include a period that is not contributed to the signal generation. When the period that is not contributed to the signal generation is included, while sampling of a subject is performed over a long period of time, an exposure period (shutter speed) can be shortened. Therefore, even when an excessively bright subject is captured, an appropriate signal amount is obtained, and an image hardly having overexposed highlights can be obtained.

The signal accumulation operation and the signal transfer operation will be specifically described. When the input terminal17is at the High level, that is, when the inverter is in the OFF state, the potential of the potential control section6becomes Vp2, and the charges accumulated in the cathodes of the photoelectric conversion sections60in all the pixels are discharged to the cathodes of the charge multiplication sections50. During this period, even when the avalanche multiplication is caused by the charges transferred to the charge multiplication sections50, counting is not performed. With this configuration, resetting of the signal charges is performed in the photoelectric conversion sections60of all the pixels, and thereafter, the first signal accumulation operation is started.

Next, the input terminal17is set at the Low level, and the potential of the potential control section6is gradually changed from Vp0 to Vp2 to perform the first signal transfer operation. After a predetermined time has then elapsed, resetting of the second signal charge, the second signal accumulation operation, and the second signal transfer operation are performed similarly as in the first respective operations.

The 1 frame period thus ends here, and the output of the count values of the counter circuits in all the pixels during this frame period is performed at the beginning of the next frame period.

The plurality of signal transfer operations are performed, but the counter circuit8is not reset during the operations. Therefore, the signals obtained in the plurality of signal transfer operations are added to each other in the counter circuit. That is, the signals held in the counter circuits8of the respective light detection elements25are additional signals for the first and second operations and signals for constituting one image (frame).

The resetting of the signal charges is performed twice during the 1 frame in the operation illustrated inFIG. 13, and an effective light reception period in which the effective counting is performed as the signal corresponds to the first and second signal accumulation operation periods and the first and second signal transfer operation periods.

When the photoelectric conversion section60is reset in the midcourse of the 1 frame period, a so-called electronic shutter operation is exercised in which the effective light reception period is set to be shorter than the 1 frame period. In this case too, since the signal accumulation operation periods of all the photoelectric conversion sections60are matched with each other, the global electronic shutter is realized.

InFIG. 13, the signal accumulation operations and the plurality of signal readout operations corresponding to the signal accumulation operations are performed twice, but the above-described operations may be performed once or may also be performed three times or more.

According to the present exemplary embodiment, the plurality of signal accumulation operations and the plurality of signal transfer operations corresponding to the signal accumulation operations are performed. With this configuration, the saturated signal charges of the light detection element25can be set to be large. The saturated signals in the single signal accumulation and signal transfer operation are determined by a saturated charge amount of the photoelectric conversion section60(maximum charge amount that can be accumulated). When the signal accumulation and the signal transfer operation are repeatedly performed plural times to add the counts in the counter circuit8, the signal charge exceeding the saturated charge amount of the photoelectric conversion section60can be counted as one frame signal.

The effective light reception period is distributed while a certain gap period is inserted therebetween during the 1 frame period. When the number of distributions of the signal accumulation operation is increased, the probability that a signal at the time of light emission is missed is reduced in a case where a subject that flashes in a certain cycle is captured, and a natural image can be obtained. In a case where an incident light intensity is weak, the resetting operation of the signal charges of the photoelectric conversion section60may also be avoided. In this case, all the periods of the 1 frame becomes the effective light reception period.

The above-described global electronic shutter function according to the second exemplary embodiment will be compared with the related-art sensor.

The CCD has the electronic shutter function, but an issue of a pseudo signal from another pixel occurs during the signal transfer operation period. The CMOS sensor originally has an issue that the signal accumulation timings in the respective rows are shifted from each other little by little, and the electronic shutter function itself is difficult. The CMOS sensor that includes a memory in the pixel and has the electronic shutter function has also been developed, but the issue of the pseudo signal still occurs.

In this regard, a digital memory is used, and also switching control of the avalanche multiplication can be performed in the imaging sensor according to the second exemplary embodiment. Thus, the nearly complete global electronic shutter involving no pseudo signal can be realized. That is, after necessary signal information is stored in the digital memory, the probability that the unwanted pseudo signal is involved can be nearly completely eliminated.

The global electronic shutter involving no pseudo signal can also be realized by a sensor constituted by two-dimensionally disposing the related-art SPADs, but the signal detection operation needs to be paused or the counting operation needs to be paused during the data output period for the digital memory of the pixel. This is because, in general, the data output of the memory is performed at a different timing for each row as described according to the second exemplary embodiment. Since the signal is counted by the incident light also during the data output period of the digital memory in the related-art SPAD that includes no signal accumulation section, when the signal detection and the counting operation are also performed during the data output period of the memory, the signal accumulation timing is shifted for each row. When the 1 frame is 10 ms, and the data output is 3 ms, the signal detection period needs to be set as 7 ms at the longest.

Therefore, according to the second exemplary embodiment, the accumulation of the signal charge and the output of the count value obtained by being read out by the counter circuit8in the previous frame can be performed in parallel in the 1 frame. Therefore, the frame time is not wasted. When the 1 frame is 10 ms, the effective light reception period for the signal can also be set as 10 ms at the longest.

As described above, according to the second exemplary embodiment, it is possible to realize the imaging sensor having the complete electronic shutter function in which the high signal-to-noise ratio is obtained and also the loss of the frame time does not occur.

Third Exemplary Embodiment

FIG. 14is an equivalent circuit diagram illustrating the light detection apparatus according to a third exemplary embodiment of the present invention. InFIG. 14, the same parts as those inFIG. 7are assigned with the same reference numerals, and redundant descriptions are omitted.

As illustrated inFIG. 14, the plurality of photoelectric conversion units40are connected to a common vertical output line37in the light detection apparatus according to the present exemplary embodiment. An N-type MOS transistor38is connected between a cathode of the charge multiplication section and the vertical output line37and controls the transfer of the signal charges. An input terminal39applies a control pulse to a gate of the N-type MOS transistor38. InFIG. 14, two photoelectric conversion units40are connected to the vertical output line37, but three or more photoelectric conversion units40may be connected to the common vertical output line. According to the present exemplary embodiment, the vertical output line to which the plurality of photoelectric conversion units40are connected is connected to the resistance4and the inverter circuit7.

The signal readout operation is performed in the photoelectric conversion unit40where a High pulse is applied to the input terminal39among the plurality of photoelectric conversion units40connected to the vertical output line37. The signal readout operation is not performed in the photoelectric conversion unit40where a pulse applied to the input terminal39is Low among the plurality of photoelectric conversion units40connected to the vertical output line37.

When the High pulse is applied to the input terminal39, the resistance4and the cathode of the charge multiplication section become electrically conductive through the N-type MOS transistor38. Therefore, when the potential of the potential control section6is gradually changed from Vp0 to Vp2, the signal transfer operation as described according to the first exemplary embodiment is performed. After the signal transfer operation is ended, the signal accumulation operation is started.

On the other hand, when the input terminal39remains at Low, since the potential from the potential control section5to the cathode of the charge multiplication section50is not supplied, the height of the potential barrier is not changed even when the potential of the potential control section6becomes Vp2. Therefore, the accumulated signal charges remain in the cathode of the photoelectric conversion section60without being transferred to the charge multiplication section50.

When the plurality of photoelectric conversion units40connected to the vertical output line37are sequentially selected to perform the signal readout operations, the operations of the respective photoelectric conversion units40can be performed. To select one photoelectric conversion unit40, the High pulse is applied to the input terminal39of the single photoelectric conversion unit40, and the input terminals39of the other photoelectric conversion units40are kept at the Low level.

To constitute the light detection apparatus according to the present exemplary embodiment as the imaging sensor, for example, while circuit systems illustrated inFIG. 14are set as a group unit (one column), a plurality of same circuit systems are disposed. A direction in which the plurality of circuit systems are disposed is a direction (row) intersecting with the direction in which the two photoelectric conversion units40are disposed inFIG. 14. With this configuration, the photoelectric conversion units40are two-dimensionally disposed. When the photoelectric conversion units40are sequentially selected in units of row to perform the signal readout operations, the light detection apparatus can operate as the imaging sensor. It should be noted that, as a configuration in which the plurality of circuit systems ofFIG. 14are disposed in one column, that is, a configuration including a plurality of count circuits corresponding to the number of plural vertical output lines37per column of the two-dimensionally disposed photoelectric conversion units, an imaging sensor configuration in which readout can be performed in a plurality of rows at the same time may also be adopted.

In the above-described operation of the two-dimensional imaging sensor, the signal accumulation times for the respective rows can be set to be the same, but start timings for the signal accumulation operations are shifted little by little for the respective readout selection rows. This corresponds to a so-called rolling shutter operation. In this case, concurrency of imaging timings is lost as compared with the global electronic shutter operation. Thus, in accordance with the light detection apparatus according to the present exemplary embodiment, the plurality of photoelectric conversion units40commonly use the resistance4, the potential control section5, the inverter circuit7, and the counter circuit8. Therefore, it becomes easier to form the resistance4, the potential control section5, the inverter circuit7, and the counter circuit8on the same semiconductor substrate as the photoelectric conversion unit40without forming those on the semiconductor substrate separate from the photoelectric conversion unit40as in the first exemplary embodiment. Thus, an advantage is attained that costs for manufacturing the sensor are suppressed to be lower than that of the first and second exemplary embodiments.

It should be noted that a configuration may also be adopted in which the resistances4, the potential control sections5, and the inverter circuits7are respectively arranged with respect to the respective photoelectric conversion units, and outputs are performed from the selected respective inverter circuits7to the vertical output line, and only the counter circuit8is commonly used.

As described above, in accordance with the light detection apparatus according to the third exemplary embodiment of the present invention, since the plurality of photoelectric conversion units40can commonly use the counter circuit8that a requires a substantial scale, it becomes possible to avoid the higher costs of the light detection apparatus.

It should be noted that various exemplary embodiments are conceivable other than the above-described exemplary embodiments. For example, the modes applied to the imaging apparatus have been mainly described according to the above-described exemplary embodiments. The configuration is not limited to this, and as in an autofocus sensor of a camera, an operation is also conceivable where the signal charge accumulation amount of the photoelectric conversion unit is monitored in the course of the signal accumulation operation, and the photoelectric conversion unit is reset when the signal charge accumulation amount reaches a predetermined level. Characteristics of signal nondestructive readout of the sensor according to the exemplary embodiment of the present invention are applied to this configuration.

A related-art SPAD operation mode and an operation mode according to the exemplary embodiment of the present invention can also be switched. The related-art SPAD operation mode is basically an operation mode in which the signal accumulation operation is not performed, and the potential of the potential control section6is fixed at Vp2, readout and counting of the signal charge are regularly performed by the charge multiplication. In a case where the exemplary embodiment of the present invention is applied to the imaging sensor as in the second exemplary embodiment, for example, in a case where the unwanted charges are few because the 1 frame period is short, the related-art SPAD operation is performed, and in a case where the 1 frame period is long, the operation mode according to the exemplary embodiment of the present invention can be selected.

In addition, according to the present exemplary embodiment, the accumulation operation periods are matched to each other in all the light detection elements. The configuration is not limited to this, and the signal accumulation operation period in one light detection element25may be included in the signal accumulation operation period in the other light detection element25. This is applied, for example, to a case where a length of the accumulation operation period varies for each row in high dynamic range (HDR) drive or the like.

Fourth Exemplary Embodiment

FIG. 15is a schematic cross sectional view of the photoelectric conversion unit of the light detection apparatus according to a fourth exemplary embodiment of the present invention. InFIG. 15, the same parts as those inFIGS. 1A to 1CandFIGS. 3A to 3Care assigned with the same reference numerals, and redundant descriptions are omitted. Since the resistance4, the potential control section5, the inverter circuit7, and the counter circuit8are the same as those of the exemplary embodiments described thus far, the descriptions thereof are omitted. The light detection apparatus according to the present exemplary embodiment is different from the first exemplary embodiment in that the height of the potential barrier is controlled by a gate electrode43.

As illustrated inFIG. 15, according to the present exemplary embodiment, the photoelectric conversion section60constituted by the P-type semiconductor region42, the N-type semiconductor region44, and the N-type semiconductor region41which will be described below and the charge multiplication section50constituted by the P-type semiconductor region46and the N-type semiconductor region3are arranged next to each other in a direction parallel to the upper surface of the semiconductor substrate. The N-type semiconductor region1is arranged between the photoelectric conversion section60and the charge multiplication section50. The P-type semiconductor region48(sixth semiconductor region) is arranged between the N-type semiconductor region44of the photoelectric conversion section60and the N-type semiconductor region1. The gate electrode43is arranged in a region overlapped with the P-type semiconductor region48and the N-type semiconductor region1in the plane view.

The signal charges accumulated in the N-type semiconductor region44are transferred to the N-type semiconductor region1by controlling the potential supplied to the gate electrode43. The height of the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3is also controlled by controlling the potential supplied to the gate electrode43. When the predetermined potential such as the ground potential is supplied to the P-type semiconductor region46arranged between those, the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3is formed.

The P-type semiconductor region42having a higher impurity concentration than the impurity concentration in the P-type semiconductor region48is arranged in the semiconductor interface section corresponding to an upper section of the N-type semiconductor region44. The P-type semiconductor region42and the N-type semiconductor region44constitute the PD of the buried type.

The N-type semiconductor region41having a lower impurity concentration than the N-type semiconductor region44is arranged on a lower surface of the N-type semiconductor region44. It should be noted that the N-type semiconductor region41may be a P-type semiconductor region having a lower impurity concentration than the P-type semiconductor region9. A location where the signal charge generated by the incident light is mainly the N-type semiconductor region41(fifth semiconductor region).

The P-type semiconductor region45(eighth semiconductor region) is arranged in a region that is not overlapped with the gate electrode43between the N-type semiconductor region1and the P-type semiconductor region46in the plane view and also that constitutes part of the upper surface of the semiconductor substrate. As described above, the unwanted charge is likely to be generated on the surface of the semiconductor substrate. When the P-type semiconductor regions42and45are arranged in a region constituting a part of the upper surface of the semiconductor substrate, and also the impurity concentrations thereof are high concentrations, depletion in the semiconductor interface section is impeded, the generation speed of the unwanted charge, that is, the generation speed of the dark current can be significantly decreased.

The P-type semiconductor region46is arranged between the N-type semiconductor region1and the N-type semiconductor region3. The potential barrier by the P-type semiconductor region46is formed between the N-type semiconductor region1and the N-type semiconductor region3. A predetermined potential such as a ground potential is supplied to the P-type semiconductor regions46,9,42, and48.

An element separator47constituted by an insulator is arranged in the surrounding of the photoelectric conversion unit including the photoelectric conversion section60and the charge multiplication section50in the plane view. The P-type semiconductor region48for separating the respective photoelectric conversion units is arranged below the element separator47.

FIG. 16illustrates an operation based on a change of the potential supplied to the gate electrode43according to the present exemplary embodiment.FIG. 16illustrates a situation where, when the potential of the gate electrode43is set as Vtx, the signal transfer operation and the signal accumulation operation are controlled by changing the potential Vtx.FIGS. 17A to 17Cillustrate changes of a potential along a broken line D-D′ inFIG. 15which is caused by the change of the potential of the gate electrode43during the signal transfer operation period. The change of the height of the potential barrier which is caused by the change of Vtx will be described with reference toFIG. 16andFIGS. 17A to 17C.

First, the potential Vtx is controlled to a first potential VL. The generated signal charge is accumulated in the N-type semiconductor region44while the potential Vtx applied to the gate electrode43is the first potential VL. That is, a period in which the potential Vtx applied to the gate electrode43is the first potential VL corresponds to the signal accumulation operation period.

The potential at this time is illustrated inFIG. 17A. The first potential VL is set so as to form the potential barrier between the N-type semiconductor region44and the N-type semiconductor region1. Since the gate electrode43, the P-type semiconductor region48, and an insulating film that is not illustrated in the drawing between them constitute the MOS structure, the potential in the P-type semiconductor region48below the gate electrode43may be controlled by the potential of the gate electrode43.

As illustrated inFIG. 16, to start the signal transfer operation, the potential Vtx applied to the gate electrode43changes from the first potential VL to a second potential VH. Thereafter, the potential Vtx gradually changes from the second potential VH to the first potential VL. Since the signal charge is an electron, the second potential VH is a potential higher than the first potential VL.

FIG. 17Cillustrates a potential when the potential Vtx is the second potential VH. The potential in the P-type semiconductor region48(and the N-type semiconductor region1) is decreased as compared with a time when the potential Vtx is the first potential VL. For this reason, the potential barrier formed between the N-type semiconductor region44and the N-type semiconductor region1disappears. As a result, the signal charge accumulated in the N-type semiconductor region44is transferred to the N-type semiconductor region1. It should be noted that the potential in the P-type semiconductor region46hardly receives influences of the potential of the gate electrode43. For this reason, as a result of the relative decrease in the potential in the N-type semiconductor region1, the potential barrier is formed between the N-type semiconductor region1and the N-type semiconductor region3. Therefore, the signal charge transferred to the N-type semiconductor region1is held in the N-type semiconductor region1.

When the potential Vtx applied to the gate electrode43is decreased from the second potential VH towards the first potential VL, as illustrated inFIG. 17B, the potential of the N-type semiconductor region1and the potential of the P-type semiconductor region48are increased. Accordingly, the potential barrier by the P-type semiconductor region46is lowered. Therefore, the signal charge is transferred from the N-type semiconductor region1to the N-type semiconductor region3. According to the present exemplary embodiment, the potential Vtx gradually changes from the second potential VH to the first potential VL. In accordance with the above-described configuration, similarly as in the first exemplary embodiment, the signal charge held in the N-type semiconductor region1can be transferred one by one.

Similarly as in the P-type semiconductor region2and the N-type semiconductor region3described according to the first exemplary embodiment, a reverse bias sufficient enough to generate the avalanche multiplication is applied between the P-type semiconductor region46and the N-type semiconductor region3. Therefore, when the signal charge is transferred to the N-type semiconductor region3, the avalanche multiplication is generated by the same operation as the first exemplary embodiment, and the signal charge is counted.

As described above, the N-type semiconductor region1where the signal charge is accumulated does not need to be provided with the photoelectric conversion function. In the above-described case too, similarly as in the first exemplary embodiment, the probability that the unwanted charge is counted can be reduced.

Since the operation is controlled by the potential of the gate electrode43according to the fourth exemplary embodiment, the drive is more easily controlled than the first exemplary embodiment.

Similarly as in the first exemplary embodiment, the charge multiplication section50may be set in the avalanche state only during the readout operation period by controlling the voltage applied to the N-type semiconductor region3, for example. As an alternative to the above-described configuration, since an electrode potential other than the gate electrode43is fixed as much as possible, the inverter circuit7and the counter circuit8may be set in a pause state during a period other than the readout operation while the charge multiplication section50is normally kept in the avalanche state.

In the case of the former configuration, the reduction effects of the unwanted charge, that is, the reduction effects of the noise are attained, and the power reduction effects upon the intense light incidence are also attained. In the case of the latter configuration, the noise reduction effects are attained.

According to the present exemplary embodiment, since the photoelectric conversion section60and the charge multiplication section50are not laminated in a vertical direction in the light detection apparatus unlike the first exemplary embodiment, a surface on a side where the gate electrode43is arranged may be set as the light incidence surface, or a surface on a side opposite to the side where the gate electrode is arranged 43 may also be set as the light incidence surface with regard to the light incidence.

As described above, according to the fourth exemplary embodiment of the present invention, it is possible to realize the light detection apparatus in which the drive is more facilitated and which has the high signal-to-noise ratio and also the excellent transfer performance.

Fifth Exemplary Embodiment

FIG. 18is a schematic cross sectional view of the photoelectric conversion unit of the light detection apparatus according to a fifth exemplary embodiment of the present invention. InFIG. 18, the same parts as those inFIGS. 17A to 17Care assigned with the same reference numerals, and redundant descriptions are omitted. Since the resistance4, the potential control section5, the inverter circuit7, and the counter circuit8are the same as those of the exemplary embodiments described thus far, the descriptions thereof are omitted. The light detection apparatus according to the present exemplary embodiment is different from the fourth exemplary embodiment in that the N-type semiconductor region44is not arranged, and the signal charge is directly transferred from the N-type semiconductor region1to the N-type semiconductor region3. In the light detection apparatus according to the present exemplary embodiment, light may be incident from the side where the gate electrode43is arranged, and light may be incident from the opposite side.FIG. 18illustrates a structure in a case where light is incident from the side opposite to the side where the gate electrode43is arranged.

As illustrated inFIG. 18, according to the present exemplary embodiment, the photoelectric conversion section60and the charge multiplication section50are arranged in a direction in parallel to the lower surface of the semiconductor substrate.

The P-type semiconductor region46is arranged between the N-type semiconductor region1of the photoelectric conversion section60and the N-type semiconductor region3of the charge multiplication section50. The gate electrode43is arranged so as to be overlapped with the P-type semiconductor region46in the plane view. The height of the potential barrier in the vicinity of the semiconductor interface immediately below the gate electrode43between the N-type semiconductor region1and the N-type semiconductor region3is controlled by controlling the potential supplied to the gate electrode43.

First, in a case where the potential Vtx applied to the gate electrode43is the first potential VL, the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3is formed. In other words, the first potential VL is set so as to form the potential barrier between the N-type semiconductor region1and the N-type semiconductor region3. The period in which the potential Vtx is the first potential VL is the signal accumulation operation period.

To start the signal transfer operation, the potential Vtx applied to the gate electrode changes from the first potential VL to the second potential VH. With this configuration, the potential in the vicinity of the semiconductor interface section of the P-type semiconductor region46is decreased. For this reason, the potential barrier formed between the N-type semiconductor region1and the N-type semiconductor region3disappears. As a result, in a case where the potential Vtx applied to the gate electrode43is the second potential VH, the signal charges accumulated in the N-type semiconductor region1are transferred to the N-type semiconductor region3.

According to the present exemplary embodiment, the potential Vtx gradually changes from the first potential VL to the second potential VH. In accordance with the above-described configuration, similarly as in the first exemplary embodiment, the signal charge held in the N-type semiconductor region1can be transferred one by one.

Similarly as in the P-type semiconductor region2and the N-type semiconductor region3described according to the first exemplary embodiment, the reverse bias sufficient enough to generate the avalanche multiplication is applied between the P-type semiconductor region46and the N-type semiconductor region3during the signal transfer operation period. Therefore, in the course of the transfer of the signal charge to the N-type semiconductor region3, the number of generation times of the avalanche multiplication is counted by the same operation as the first exemplary embodiment. Then, the potential applied to the N-type semiconductor region3is set such that the avalanche multiplication is not generated during the accumulation operation period. It should be noted that, during the signal accumulation operation, the operation of the inverter circuit or the counter circuit may be turned off while application of such a voltage that the avalanche multiplication is generated is kept.

According to the present exemplary embodiment, a light shielding film52made of a metal is formed in a region overlapped with the charge multiplication section50on the upper surface of the semiconductor substrate. With this configuration, a situation can be avoided where the signal charge is generated in the charge multiplication section50and read out by the counter circuit.

In addition, according to the present exemplary embodiment, a negative fixed charge film51is arranged on the upper surface of the substrate. This is because the depletion in the semiconductor substrate interface section is avoided to reduce the dark current.

Sixth Exemplary Embodiment

An imaging system according to the present exemplary embodiment will be described with reference toFIG. 19. The components similar to the light detection apparatus according to the above-described respective exemplary embodiments are assigned with the same reference symbols, and descriptions thereof will be omitted or simplified.FIG. 19is a block diagram illustrating a schematic configuration of the imaging system according to the present exemplary embodiment.

The light detection apparatus described according to the above-described respective exemplary embodiments can be applied to various imaging systems functioning as an imaging apparatus201inFIG. 19. A digital still camera, a digital camcorder, a security camera, a copier, a facsimile device, a mobile phone, an on-vehicle camera, an observation satellite, and the like are exemplified as the applicable imaging system. A camera module including an optical system such as a lens and the imaging apparatus is also included in the imaging system. A block diagram of the digital still camera is exemplified inFIG. 19as an example of these devices.

An imaging system200exemplified inFIG. 19includes the imaging apparatus201, a lens202for forming an optical image of a subject on the imaging apparatus201, a diaphragm204for causing the amount of light to pass through the lens202to be variable, and a barrier206for protecting the lens202. The lens202and the diaphragm204are an optical system in which light is focused on the imaging apparatus201. The imaging apparatus201is the light detection apparatus described according to the first to fifth exemplary embodiments and converts the optical image formed by the lens202into image data.

The imaging system200also includes a signal processing unit208configured to perform processing on an output signal output from the imaging apparatus201. The signal processing unit208performs analog-to-digital conversion for converting an analog signal output by the imaging apparatus201into a digital signal. The signal processing unit208also performs an operation for outputting the image data by performing various corrections and compressions when necessary in addition to the analog-to-digital conversion. An analog-to-digital conversion unit corresponding to part of the signal processing unit208may be formed on the semiconductor substrate where the imaging apparatus201is provided or may also be formed another semiconductor substrate different from that for the imaging apparatus201. In addition, the imaging apparatus201and the signal processing unit208may be formed on the same semiconductor substrate.

The imaging system200further includes a memory unit210configured to temporarily store the image data and an external interface unit (external I/F unit)212for communicating with an external computer or the like. The imaging system200further includes a recording medium214such as a semiconductor memory for recording or reading out imaging data and a recording medium control interface (recording medium control I/F unit)216for performing recording or readout with respect to the recording medium214. It should be noted that the recording medium214may be built in the imaging system200or may also be detachably attached.

The imaging system200further includes an overall control and calculation unit218configured to perform various calculations and control the entirety of the digital still camera, and a timing generation unit220configured to output various timing signals to the imaging apparatus201and the signal processing unit208. Herein, the timing signals and the like may be input from the outside, and it is sufficient when the imaging system200includes at least the imaging apparatus201and the signal processing unit208configured to process an output signal from the imaging apparatus201.

The imaging apparatus201outputs an imaging signal to the signal processing unit208. The signal processing unit208implements predetermined signal processing on the imaging signal output from the imaging apparatus201and outputs the image data. The signal processing unit208generates an image by using an imaging signal.

In accordance with the application of the light detection apparatus according to the above-described respective exemplary embodiments, it is possible to realize the stably highly sensitive imaging system that may obtain the image having the satisfactory quality with the high saturated signal amount.

Seventh Exemplary Embodiment

An imaging system and a movable body according to the present exemplary embodiment will be described with reference toFIGS. 20A and 20B.

FIG. 20Aschematically illustrates an example of an imaging system related to on-vehicle camera. An imaging system300includes an imaging apparatus functioning as a light detection apparatus310. The light detection apparatus (imaging apparatus)310is the light detection apparatus described in any one of the first to fifth exemplary embodiments. The imaging system300includes an image processing unit312configured to perform image processing on plural pieces of image data obtained by the light detection apparatus310and a parallax calculation unit314configured to calculate a parallax (phase difference of parallax images) from the plural pieces of image data obtained by the imaging system300. The imaging system300also includes a distance measurement unit316configured to calculate a distance to a target on the basis of the calculated parallax and a collision determination unit318configured to determine whether there is a possibility that a collision may occur on the basis of the calculated distance. Herein, the parallax calculation unit314and the distance measurement unit316are examples of a distance information obtaining unit configured to obtain distance information to a target object. That is, the distance information is information related to parallax, a de-focus amount, a distance to the target object, and the like. The collision determination unit318may determine the collision probability by using any one of these pieces of distance information. The distance information obtaining unit may be realized by dedicatedly designed hardware or a software module. The distance information obtaining unit may also be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like and may be realized by a combination of these.

The imaging system300is connected to a vehicle information obtaining apparatus320and can detect vehicle information such as a vehicle speed, a yaw rate, and a rudder angle. A control ECU330functioning as a control apparatus configured to output a control signal for generating braking force to a vehicle is connected to the imaging system300on the basis of the determination result in the collision determination unit318. The imaging system300is also connected to an alarm apparatus340configured to issue an alarm to a driver on the basis of the determination result in the collision determination unit318. For example, in a case where a collision probability is high as the determination result of the collision determination unit318, the control ECU330performs vehicle control for avoiding the collision or alleviating damages by applying brake, returning an accelerator, and suppressing an engine output. The alarm apparatus340issues an alarm to a user by emitting an alarm such as sound, displaying alarm information on a screen of a car navigation system or the like, and supplying vibration to a seat belt or steering, for example.

According to the present exemplary embodiment, surrounding of the vehicle such as, for example, a forward area or a backward area is captured by the imaging system300.FIG. 20Billustrates an imaging system in a case where the forward area in front of the vehicle (imaging range350) is captured. The vehicle information obtaining apparatus320transmits an instruction to the imaging system300or the light detection apparatus310so as to perform a predetermined operation. In accordance with the above-described configuration, ranging accuracy can be further improved.

An example of the control for avoiding the collision with the other vehicle has been described above, but the technology can be applied to control for following the other vehicle to perform automated driving, control for the automated driving without drifting from a lane, or the like. Furthermore, the imaging system can be applied to not only the vehicle such as an automobile but also a movable body (movable apparatus) such as, for example, a vessel, aircraft, or industrial robot. In addition, the imaging system can be widely applied to not only the movable body but also a device using object recognition such as an intelligent transport system (ITS).

Modified Examples

Not only the above-described exemplary embodiments but also various modifications can be made with regard to the present invention. For example, exemplary embodiments of the present invention also include an example in which part of the configurations according to any one of the exemplary embodiments is added to the other exemplary embodiment and an example in which the configuration is replaced with part of the configuration according to the other exemplary embodiment.

It should be noted that the above-described exemplary embodiments are all merely examples of the specified configurations for carrying out the present invention, and the technical scope of the present invention is not be restrictively interpreted by these exemplifications. That is, the exemplary embodiments of the present invention can be carried out in various modes without departing from its technical concept or its main features.

Advantages Effects of Invention

According to the exemplary embodiments of the present invention, it is possible to reduce the noise in the light detection apparatus that uses the SPAD, in particular, the light detection apparatus that accumulates and outputs the signal charge.

This application claims the benefit of Japanese Patent Application No. 2018-175251, filed Sep. 19, 2018, which is hereby incorporated by reference herein in its entirety.