Microelectronic devices including an oxide material between adjacent decks, electronic systems, and related methods

A microelectronic device includes decks comprising alternating levels of a conductive material and an insulative material, the decks comprising pillars including a channel material extending through the alternating levels of the conductive material and the insulative material, a conductive contact between adjacent decks and in electrical communication with the channel material of the adjacent decks, and an oxide material between the adjacent decks, the oxide material extending between an uppermost level of a first deck and a lowermost level of a second deck adjacent to the first deck. Related electronic systems and methods of forming the microelectronic device and electronic systems are also disclosed.

TECHNICAL FIELD

Embodiments disclosed herein relate to microelectronic devices and electronic systems including an oxide material between decks of alternating levels of insulative material and conductive material, and to related methods. More particularly, embodiments of the disclosure relate to microelectronic devices and electronic systems comprising memory strings extending through decks of alternating levels of insulative material and conductive material and including an oxide material that does not exhibit charge trapping characteristics, and to related methods of forming the microelectronic devices and electronic systems.

BACKGROUND

A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). To meet demands for higher capacity memories, designers continue to strive for increasing memory density, (i.e., the number of memory cells for a given area of an integrated circuit die). One way to increase memory density is to reduce the feature size of individual memory cells. However, as the feature size decreases, the thickness of different portions of the memory cell, such as a tunnel dielectric material, may also exhibit a similar decrease in size. A tunnel dielectric material having a low thickness may result in an increased risk of failure of the tunnel dielectric material and charge leakage from a storage node of the memory cell.

Another proposal for increasing memory density in non-volatile memory devices is to utilize vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array includes semiconductor pillars extending through openings in tiers of conductive structures (e.g., word lines, control gates) and dielectric materials at each junction of the semiconductor pillars and the conductive structures. Such a configuration permits a greater number of transistors to be located in a unit of die area by building the array upwards (e.g., longitudinally, vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors. As the demand for higher densities of memory cells increases, the semiconductor pillars are patterned to have a smaller pitch between adjacent pillars. In addition, multiple decks comprising the tiers of conductive structures and dielectric materials may be patterned one over the other to facilitate an increased number of memory cells in the device.

DETAILED DESCRIPTION

The illustrations included herewith are not meant to be actual views of any particular systems, microelectronic devices, electronic systems, or memory cells, but are merely idealized representations that are employed to describe embodiments herein. Elements and features common between figures may retain the same numerical designation except that, for ease of following the description, reference numerals begin with the number of the drawing on which the elements are introduced or most fully described.

The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments described herein. However, a person of ordinary skill in the art will understand that the embodiments disclosed herein may be practiced without employing these specific details. Indeed, the embodiments may be practiced in conjunction with conventional fabrication techniques employed in the semiconductor industry. In addition, the description provided herein does not form a complete description of a microelectronic device or an electronic system, or a complete description of a process flow for fabricating the microelectronic device or electronic system. The structures described below do not form complete microelectronic devices or electronic systems. Only those process acts and structures necessary to understand the embodiments described herein are described in detail below. Additional acts to form a complete microelectronic device or electronic system may be performed by conventional techniques.

The materials described herein may be formed by conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). Alternatively, the materials may be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. The removal of materials may be accomplished by any suitable technique including, but not limited to, etching, abrasive planarization (e.g., chemical-mechanical planarization), or other known methods unless the context indicates otherwise.

As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” are in reference to a major plane of a substrate (e.g., base material, base structure, base construction, etc.) in or on which one or more structures and/or features are formed and are not necessarily defined by Earth's gravitational field. A “lateral” or “horizontal” direction is a direction that is substantially parallel to the major plane of the substrate, while a “longitudinal” or “vertical” direction is a direction that is substantially perpendicular to the major plane of the substrate. The major plane of the substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.

According to embodiments described herein, a microelectronic device includes decks comprising alternating levels of a conductive material (which may also be characterized as access lines (e.g., word lines) or gate electrodes) and an insulative material (e.g., a dielectric material). Pillars of a channel material may extend through the decks and may form strings of memory cells. For example, memory cells may be located at an intersection proximate the channel material and at least some of the levels of the conductive material. One or more of a dielectric material (e.g., one or more of a tunnel dielectric material, a charge trapping material, a charge blocking material, or another material) may be located between the channel material and at least some of the levels of the conductive material. Another conductive material (e.g., an electrode material) may be located proximate to some of the dielectric materials. In some embodiments, the electrode material is located between dielectric materials. Memory cells associated with different levels of the conductive material may be isolated from one another at least by the intervening level of the insulative material.

A conductive contact electrically couples the channel material of one deck to the channel material of an adjacent deck. In some embodiments, the volume between the adjacent decks is free of charge trapping materials, such as silicon nitride. For example, an insulative material, such as an oxide material (e.g., silicon dioxide), may be located between the adjacent decks. The oxide material may facilitate decoupling between the channel material between adjacent pillars. The oxide material may extend from one deck to an adjacent deck and may electrically isolate the conductive contacts electrically coupling the channel materials of the adjacent decks. In some embodiments, the oxide material substantially fills the volume between the adjacent decks and between conductive contacts of adjacent pillars. In other embodiments, the oxide material lines the conductive contacts and at least a portion of one of the decks (e.g., an insulative material of at least one of the decks). Another electrically conductive material is adjacent to the oxide material and fills the remaining volume between the adjacent decks and between the oxide material lining adjacent conductive contacts.

The oxide material may reduce or prevent electrical coupling between adjacent pillars proximate a location between the adjacent decks. The oxide material may comprise a material that is not prone to charge trapping (e.g., electron trapping) and associated de-trapping of charges. Due, at least in part, to the presence of the oxide material, the pillars including the strings of memory cells may exhibit improved device performance, such as reduced read write bias and an increased operating window compared to conventional memory cells. In some embodiments including the conductive material adjacent to the oxide material, the conductive material may reduce or prevent interactions between the channel materials of adjacent pillars. In some embodiments, the conductive material may improve string current of the string of memory cells and may also improve gate induced drain leakage (GIDL).

FIG. 1Ais a simplified cross-sectional view of a microelectronic device100, in accordance with embodiments of the disclosure. The microelectronic device100may include a first deck103adjacent to (e.g., over) a base material102and a second deck105adjacent to (e.g., over) the first deck103. The base material102may comprise a substrate or a construction upon which additional materials are formed. The base material102may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode, or a metal electrode on a semiconductor substrate having one or more layers, structures or regions formed thereon. The base material102may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates and silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The base material102may be doped or undoped.

The first deck103and the second deck105may each independently comprise alternating levels of an insulative material110and a conductive material112. For example, the microelectronic device100may include tiers107, each tier107comprising an insulative material110and a conductive material112.

AlthoughFIG. 1Aillustrates that the microelectronic device100includes only two decks103,105, the disclosure is not so limited. In other embodiments, the microelectronic device100includes more than two decks103,105, such as three decks, four decks, six deck, eight decks, or another number of decks. In addition, althoughFIG. 1Aillustrates that the first deck103and the second deck105include three tiers107, the disclosure is not so limited. In other embodiments, the first deck103and the second deck105may each individually comprise more than at least about 32 tiers107or alternating levels of conductive material112and insulative material110, such as at least about 64 tiers107, at least about 128 tiers107, or even at least about 256 tiers107. In some embodiments, the first deck103and the second deck105comprise the same number of tiers107. In other embodiments, the first deck103includes a different number of tiers107than the second deck105.

A source104, such as a source region, may be located between the base material102and the first deck103. An etch stop material106may be adjacent to the source104and a conductive material108may be adjacent to the etch stop material106.

The source104may include, for example, a semiconductor material doped with one of P-type conductivity materials or N-type conductivity materials. As used herein, an N-type conductivity material may include, for example, polysilicon doped with at least one N-type dopant (e.g., arsenic ions, phosphorous ions, antimony ions). As used herein, a P-type conductivity material may include, for example, polysilicon doped with at least one P-type dopant (e.g., boron ions). In some embodiments, the source104includes N-type conductivity materials. In other embodiments, the source104comprises tungsten, tungsten silicide, or another material.

The etch stop material106may comprise, for example, one or more of aluminum oxide (Al2O3), titanium dioxide (TiO2), silicon carbide doped with nitrogen (SiCN), aluminum nitride, aluminum oxynitride, silicon carbide, or another material. In some embodiments, the etch stop material106comprises aluminum oxide. The etch stop material106may be formulated and configured to exhibit an etch selectivity with respect to the materials of the first deck103and the second deck105(e.g., with respect to the insulative materials110and the conductive materials112). During formation of the first deck103and the second deck105, portions of the insulative material110and the conductive material112of the respective first deck103and second deck105may be removed without substantially removing the etch stop material106.

The insulative material110may comprise a dielectric material, such as, for example, silicon dioxide, or other dielectric materials.

The conductive material112may comprise an electrically conductive material, such as one or more of the materials described above with reference to the conductive material108. In some embodiments, the conductive material112comprises polysilicon. In some embodiments, the conductive material112has the same composition as the conductive material108. The conductive material112may also be referred to herein as access lines (e.g., word lines) or gate electrodes.

With continued reference toFIG. 1A, pillars125comprising a channel material120may extend through the first deck103and the second deck105. The channel material120may be in electrical communication with the source104. The channel material120may include a semiconductor material, such as, for example, polysilicon. In some embodiments, the channel material120comprises P-type polysilicon. In other embodiments, the channel material120comprises a metal oxide semiconductor material. In some embodiments, the channel material120comprises polysilicon. The channel material120may be electrically isolated from the conductive material108and the conductive material115by an insulative material145. The insulative material145may comprise a dielectric material. For example, the insulative material145may comprise one or more of phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, a nitride material, (e.g., silicon nitride (Si3N4)), an oxynitride (e.g., silicon oxynitride), another gate dielectric material, a dielectric carbon nitride material (e.g., silicon carbon nitride (SiCN)), or a dielectric carboxynitride material (e.g., silicon carboxynitride (SiOCN)).

Memory cells130may be located at intersections between the channel material120and the conductive materials112. The memory cells130may comprise, for example, a dielectric material124(which may also be referred to as a tunnel dielectric material) between the channel material120and an electrode material126(which may also be referred to as a gate electrode, a floating gate, or a gate), and an other dielectric material128(which may also be referred to as a charge storage material) around at least a portion of the electrode material126. In some embodiments, the memory cell130may be referred to herein as a “floating gate” memory cell. As will be described with reference toFIG. 1C, the memory cells130may include other materials and may be referred to herein as “charge trapping” memory cells.

The dielectric material124may include, for example, a tunnel oxide material. In some embodiments, the dielectric material124comprises silicon dioxide. However, the disclosure is not so limited and the dielectric material124may comprise another material, such as one or more of the materials described above with reference to the insulative material145. In some embodiments, the dielectric material124comprises the same material composition as the insulative material145. AlthoughFIG. 1Aillustrates the dielectric material124only on sides proximate the conductive materials112and not in contact with or located on sides of the insulative materials110, the disclosure is not so limited. In other embodiments, the dielectric material124extends continuously through the entire first deck103and the entire second deck105to the conductive contact132. In some embodiments, the dielectric material124may be grown on the electrode material126, such as by an in-situ steam generation (ISSG) process to selectively oxidize exposed portions of the electrode material126.

The other dielectric material128may include a charge trapping material, such as an oxide-nitride-oxide (ONO) structure. For example, the other dielectric material128may comprise a first oxide material, a silicon nitride material adjacent to the first oxide material, and a second oxide material adjacent to the silicon nitride material. The first oxide material and the second oxide material may include silicon dioxide, hafnium oxide, zirconium oxide, or another material. In some embodiments, the first oxide material and the second oxide material have the same material composition. In some embodiments, the first oxide material and the second oxide material comprise silicon dioxide. In some embodiments, the other dielectric material128may also be referred to as an interpoly dielectric (IPD) material.

FIG. 1Bis a simplified cross-sectional view of the microelectronic device100taken along section line B-B ofFIG. 1A. The pillars125may include a circular cross-sectional shape. In some embodiments, the channel material120may surround the electrically insulative material122and may exhibit a circular cross-sectional shape. The dielectric material124may surround the channel material120and may be located between the channel material120and the electrode material126. The other dielectric material128may be located between the electrode material126and the conductive material112.

Referring back toFIG. 1A, another conductive material115may be formed adjacent to the insulative material110of the uppermost tier107. The conductive material115may comprise a so-called select gate drain (SGD) material. The conductive material115may comprise one or more of the materials described above with reference to the conductive material108. In some embodiments, the conductive material115has the same material composition as the conductive material108. An insulative material114may be formed adjacent to the conductive material115. The insulative material114may be patterned and conductive contacts116(which may also be referred to herein as conductive plugs) may be adjacent to and in electrical communication with the channel material120. A conductive line118(e.g., data line, bit line) may be adjacent to and in electrical communication with the conductive contacts116.

In some embodiments, the channel material120may exhibit a bulge140at a location between the first deck103and the second deck105. A distance D1between opposing portions of the bulge140(e.g., the diameter of the channel material120at the bulge140) may be greater than a distance between opposing portions of the channel material120at other portions of the channel material120. In other words, the channel material120may have a larger diameter proximate the bulge140relative to other locations of the channel material120.

The bulge140may be a result of the method of forming the microelectronic device100, such as the method of forming the channel materials120to extend through the first deck103and the second deck105and forming the conductive contacts132between the first deck103and the second deck105.

The conductive contacts132may electrically couple the channel material120of a pillar125of the first deck103to the channel material120of a corresponding pillar125of the second deck105. In other words, the channel material120of the first deck103may be in electrical communication with the channel material120of the second deck105through the conductive contact132. The conductive contacts132may comprise an electrically conductive material. In some embodiments, the conductive contacts132comprise polysilicon. In some embodiments, the conductive contacts132comprise the same material composition as the conductive materials112.

The conductive contacts132may include protruding portions134which extend farther (up and down in the view shown inFIG. 1A) from an underlying insulative material110than other portions (e.g., central portions) of the respective conductive contact132. In some embodiments, a distance D2between opposite sides of the conductive contacts132at a location proximate the underlying insulative material is less than a distance D3between opposing protruding portions134of the respective conductive contact132.

An oxide material136may be located between the first deck103and the second deck105. The oxide material136may comprise an electrically insulative material. In some embodiments, the oxide material136comprises a material that does not exhibit charge trapping (e.g., electron trapping) and de-trapping properties. For example, the oxide material136is free of (e.g., substantially free of) silicon nitride. In other words, the microelectronic device100may not include silicon nitride at locations between the first deck103and the second deck105.

The oxide material136may comprise one or more of silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, an oxynitride (e.g., silicon oxynitride), aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, molybdenum oxide, or a spin-on dielectric (SOD) (e.g., hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), a polyimide, polytetrafluoroethylene (PTFE), a spin-on polymer). The oxide material136may exclude silicon nitride. In some embodiments, the oxide material136comprises silicon dioxide. In some embodiments, at least a portion of the volume between the first deck103and the second deck105may include one or more voids. The one or more voids may be filled with one or more of oxygen, nitrogen, air, helium, or another gas. In some embodiments, the one or more voids is filled with oxygen and nitrogen.

The oxide material136may directly contact the first deck103and the second deck105. In some embodiments, the oxide material136directly contacts an insulative material110of the first deck103and an insulative material110of the second deck105(such as where the second deck105does not include the etch stop material106). For example, the oxide material136may be located directly between an uppermost insulative material110of the first deck103and a lowermost insulative material110of the second deck105. In some embodiments, the oxide material136may directly contact the uppermost insulative material110of the first deck103and the lowermost insulative material110of the second deck105. In other embodiments, the oxide material136directly contacts an insulative material110of the first deck103and directly contacts the etch stop material106in contact with an insulative material110of the second deck105. In some embodiments, at least a portion of the oxide material136is located laterally directly between the conductive contacts132of adjacent pillars125. AlthoughFIG. 1Ahas been described and illustrated as including the oxide material136directly contacting the uppermost insulative material110of the first deck105and the etch stop material106of the second deck103, the disclosure is not so limited. In other embodiments, the oxide material136may directly contact an uppermost conductive material of the first deck103and a lowermost conductive material112of the second deck105(or the etch stop material106of the second deck105). In some such embodiments, the oxide material136is the only material intervening between portions of the uppermost conductive material112of the first deck103and the lowermost conductive material112of the second deck105. In some embodiments, the oxide material136directly contacts the channel material proximate the bulge140.

The oxide material136may have a thickness T1within a range from about 50 nm to about 200 nm, such as from about 50 nm to about 75 nm, from about 75 nm to about 100 nm, from about 100 nm to about 150 nm, or from about 150 nm to about 200 nm. In some embodiments, the thickness T is about 100 nm.

In some embodiments, the thickness T1of the oxide material136may be greater than a thickness of the levels of the insulative material110. In some embodiments, the thickness T1of the oxide material136is greater than the thickness of the levels of the conductive material112. For example, each level of insulative material110may have a thickness T2within a range from about 20 nm to about 10 nm to about 50 nm, such as from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, from about 30 nm to about 40 nm, or from about 40 nm to about 50 nm. Each level of conductive material112may have a thickness T3within a range from about 10 nm to about 50 nm, such as from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, from about 30 nm to about 40 nm, or from about 40 nm to about 50 nm. In some embodiments, the thickness T1of the oxide material136may be greater than a thickness of each of the tiers107(i.e., the sum of the thickness T2and the thickness T3).

In some embodiments, the oxide material136may reduce or prevent (e.g., substantially prevent) coupling of the channel materials120of adjacent pillars125at locations between the first deck103and the second deck105or at locations proximate the oxide material136. In addition, the oxide material136may comprise a material composition formulated and configured to exhibit a reduced degree of charge trapping than conventional materials that are used between adjacent deck structures. For example, conventional microelectronic devices may include a silicon nitride material between adjacent decks. Due to the large space between the adjacent decks and, in particular, the large space between conductive materials112of the adjacent decks (e.g., an uppermost conductive material112of the first deck103and a lowermost conductive material112of the second deck105, which may be spaced from each other at least by an uppermost insulative material110of the first deck103, a lowermost insulative material110of the second deck105, and the oxide material136between the first deck103and the second deck105), the silicon nitride material may trap charges (e.g., electrons) that may cause one pillar125including the channel material120to couple to adjacent pillars125. In some instances, when a first pillar125is selected for programming (writing) and a second pillar125is inhibited, such as by applying a potential of about 0 V to the channel material120of the first pillar125and applying a potential (e.g., about 10 V) to the channel material120of the second pillar125, electrons may become trapped in such a silicon nitride material located between adjacent decks between the first pillar125and the second pillar125. The trapped charges (e.g., electrons) in the silicon nitride material may affect a threshold voltage of the memory cells130and may reduce the operating (e.g., read) window of the memory cells130.

In addition, charges may not become trapped in the oxide material136. By way of comparison, conventional microelectronic devices may include silicon nitride or other materials between the first deck103and the second deck105, which materials may trap charges and couple to the bulges140, which may be present in the channel material120due to various processing conditions (e.g., deposition of various materials, etching acts, cleaning acts) used to form the pillars125. In other words, the bulges140may couple to a charge trapping material between the adjacent decks in conventions devices. Further, the protruding portions134of the conductive contact132may exhibit a relatively higher electric field (such as by an increase in current density) than other portions of the conductive contact132. In conventional microelectronic devices, the high field at the protruding portions134may facilitate injection of electrons or other charges into a silicon nitride material proximate the conductive contact132during use and operation of the microelectronic device100. Injection of electrons or other charges may result in a reduced operating window for the memory cells130.

Forming the oxide material136to include a material composition that does not trap charges (e.g., electrons) may reduce or prevent charge trapping within the channel material120, such as proximate the bulges140and at locations proximate the protruding portions134. Accordingly, the microelectronic device100may include pillars125including strings of memory cells130exhibiting a larger operating window than in conventional microelectronic devices because the adjacent pillars125do not couple to one another.

AlthoughFIG. 1Ahas been described and illustrated as including a particular type of memory cell130(e.g., floating gate memory cells), the disclosure is not so limited.FIG. 1Cis a simplified cross-sectional view of a memory cell150that may be present in the microelectronic device100ofFIG. 1Ain place of the memory cells130(FIG. 1A). The memory cells150may comprise a so-called charge trapping material. In some such embodiments, the associated microelectronic device100may comprise a charge trapping NAND. The memory cells150may be referred to herein as a “charge trapping” memory cell.

FIG. 1Cis a simplified cross-sectional view of a memory cell150that may be used interchangeably with the memory cells130ofFIG. 1A, in accordance with embodiments of the disclosure. The memory cell150may include a dielectric material152(e.g., a tunnel dielectric material), a charge trapping material154, and a charge blocking material156between the channel material120and the conductive material112. The charge trapping material154may be located directly between the dielectric material152and the charge blocking material156. In some embodiments, the dielectric material152directly contacts the channel material120and the charge trapping material154. The charge blocking material156may directly contact and may be located directly adjacent to the charge trapping material154and the conductive material112.

AlthoughFIG. 1Ahas been described and illustrated as including the oxide material136between the first deck103and the second deck105, the disclosure is not so limited. In other embodiments, one or more other materials may be located between the first deck103and the second deck105.FIG. 2is a simplified cross-sectional view of a microelectronic device200in accordance with embodiments of the disclosure. The microelectronic device200may be substantially the same as the microelectronic device100ofFIG. 1A, except that the microelectronic device200may include one or more additional materials between the first deck103and the second deck105.

The microelectronic device200includes an oxide material160between the first deck103and the second deck105to electrically isolate adjacent conductive contacts132from each other. In some embodiments, the oxide material160may not substantially fill an entire volume between the first deck103and the second deck105, such as a volume between the etch stop material106proximate the second deck105and an upper insulative material110of the first deck103. In some embodiments, a remaining portion of the volume between the first deck103and the second deck105may be filled with one or more gases, such as one or more of oxygen, nitrogen, air, helium, or another gas. In some embodiments, the one or more voids is filled with oxygen and nitrogen. In other embodiments, a conductive material162may also be located between adjacent pillars125and electrically isolated from the adjacent pillars125and the associated conductive contact132at least by the oxide material160.

In some embodiments, the oxide material160may comprise an oxide liner around sidewalls of the conductive contacts132and sidewalls of the channel material120located between the first deck103and the second deck105. In some embodiments, the oxide material160may be adjacent to (e.g., conformally overlie) the conductive contact132, the sidewalls of the channel material120located between the first deck103and the second deck105, and an uppermost insulative material110of the first deck103. The oxide material160may be adjacent to the bulge140of the channel material120and the protruding portions134of the conductive contacts132.

The oxide material160may be adjacent to surfaces of an insulative material110of the first deck103and may be adjacent to surfaces of the conductive contacts132and the channel material120to a surface of the etch stop material106. In other embodiments, the oxide material160extends adjacent to the surfaces of the conductive contacts132and the channel material120to a surface of an insulative material110of the second deck105. As discussed above with reference toFIG. 1Aand the oxide material136, the oxide material160may be located directly between an uppermost insulative material110of the first deck103and a lowermost insulative material110of the second deck105. In some embodiments, the oxide material136may directly contact the uppermost insulative material110of the first deck103and the lowermost insulative material110of the second deck105. In other embodiments, the oxide material160directly contacts an insulative material110of the first deck103and directly contacts the etch stop material106in contact with an insulative material110of the second deck105. In some embodiments, at least a portion of the oxide material160is located laterally directly between the conductive contacts132of adjacent pillars125. In some such embodiments, spaces between the oxide material160on the conductive contacts132of adjacent pillars125may be separated by a void. The void may be filled with one or more gases or may be filled with the conductive material162. AlthoughFIG. 1Ahas been described and illustrated as including the oxide material160directly contacting the uppermost insulative material110of the first deck103and the etch stop material106of the second deck105, the disclosure is not so limited. In other embodiments, the oxide material160may directly contact an uppermost conductive material of the first deck103and a lowermost conductive material112of the second deck105(or the etch stop material106of the second deck105).

The oxide material160may comprise the same materials described above with reference to the oxide material136(FIG. 1A). In some embodiments, the oxide material160comprises silicon dioxide.

The conductive material162may be adjacent to the oxide material160and may fill a remaining volume between the first deck103and the second deck105. The conductive material162may be adjacent to surfaces of the oxide material160adjacent to the first deck103and be adjacent to the oxide material160extending adjacent to the conductive contacts132and the channel material120. The conductive material162may extend from the oxide material160adjacent to the first deck103to the etch stop material106adjacent to the second deck105. In other embodiments, the conductive material162extends from the oxide material160to an insulative material110of the second deck105.

The conductive material162may include an electrically conductive material. In some embodiments, the conductive material162comprises polysilicon. The conductive material162may be doped with one or more of boron, phosphorus, arsenic, antimony, or another material. In other embodiments, the conductive material162comprises tungsten. The conductive material162may, in some embodiments, comprise the same material composition as the conductive contacts132.

The microelectronic device200may exhibit reduced charge trapping within the channel material120such as proximate the bulges140and at locations proximate the protruding portions134. In addition, the conductive material162may facilitate shielding between adjacent pillars125and the channel materials120of adjacent pillars125. In other words, the conductive material162between adjacent pillars125may reduce or prevent interactions between the channel material120of adjacent pillars125.

In some embodiments, the conductive material162may improve string current of the string of memory cells130and may also improve gate induced drain leakage (GIDL). The conductive material162may be in electrical communication with a conductive contact located in a so-called stair-step structure of the microelectronic device. In use and operation, a voltage may be applied to the conductive material162proximate, for example, the channel material120of a selected memory string or an unselected memory string.

Accordingly, in at least some embodiments, a microelectronic device comprises decks comprising alternating levels of a conductive material and an insulative material, the decks comprising pillars including a channel material extending through the alternating levels of the conductive material and the insulative material, a conductive contact between adjacent decks and in electrical communication with the channel material of the adjacent decks, and an oxide material between the adjacent decks, the oxide material extending between an uppermost level of a first deck and a lowermost level of a second deck adjacent to the first deck.

FIG. 3AthroughFIG. 3Dare simplified cross-sectional views illustrating a method of forming the microelectronic device100ofFIG. 1A, in accordance with embodiments of the disclosure. Referring toFIG. 3A, the first deck103(FIG. 1A) may be formed adjacent to the base material102, the source104, the etch stop material106, and the conductive material108to form a semiconductor structure300. The alternating levels of the insulative material110and the conductive material112of the first deck103may be formed adjacent to the conductive material108.

After forming the levels of the insulative material110and the conductive material112, openings may be formed through the levels of the insulative material110and the conductive material112and the conductive material108to expose portions of the etch stop material106. The exposed portions of the etch stop material106may be removed through the openings to expose portions of the source104. For example, in some embodiments, portions of the insulative material110, the conductive material112, and the conductive material108may be removed to form the openings by one removal act while a second removal act may be used to remove the portions of the etch stop material106.

In some embodiments, such as in so-called “gate first” processes, the memory cells130may be formed by removing portions of the conductive material112to form recesses. The other dielectric material128may be formed in the recesses and adjacent to the remaining portions of the conductive material112. The electrode material126may be formed adjacent to the other dielectric material128and the dielectric material124may be formed adjacent to the electrode material126. After forming the dielectric material124, the channel material120may be formed adjacent sides of the openings to form the memory cells130. In some embodiments, after forming the channel material120, the electrically insulative material122may be formed adjacent the channel material120.

After forming the channel material120and the electrically insulative material122, portions of the channel material120and the electrically insulative material122may be removed from surfaces of the uppermost insulative material110.

A silicon nitride material170may be formed adjacent to the exposed (e.g., the uppermost) insulative material110. Referring toFIG. 3B, openings may be formed through the silicon nitride material170to expose the channel material120. A conductive material may be formed in the openings and in electrical communication with the channel material120to form the conductive contacts132. The conductive contacts132are illustrated inFIG. 3AthroughFIG. 3Dwithout the protruding portions134(FIG. 1A). However, the conductive contacts132may include the protruding portions134. An etch stop material172having an etch selectivity relative to the silicon nitride material170may be formed adjacent to the conductive contacts132.

Referring toFIG. 3C, substantially all of the silicon nitride material170may be removed to expose portions of the insulative material110. The insulative material110may exhibit an etch selectivity relative to the silicon nitride material170. After removing the silicon nitride material170, the conductive contacts132and the etch stop material172may remain adjacent to (e.g., over) the channel material120.

With reference toFIG. 3D, the oxide material136may be formed adjacent to the semiconductor structure300, such as adjacent to (e.g., over) the insulative material110and adjacent to (e.g., on sides of) the conductive contacts132and the etch stop material172. In some embodiments, after forming the oxide material136, the semiconductor structure300may be exposed to a chemical mechanical planarization (CMP) process to expose portions of the etch stop material172through the oxide material136. AlthoughFIG. 3Dillustrates that the oxide material136is formed directly on the uppermost insulative material110, the disclosure is not so limited. In other embodiments, the oxide material136is formed directly on the uppermost conductive material112.

After forming and planarizing the oxide material136, the second deck105(FIG. 1A) may be formed adjacent to the semiconductor structure300. For example, the etch stop material106(FIG. 1A) may be formed adjacent to the oxide material136, and a stack of alternating levels of the insulative material110and conductive material112may be formed adjacent to the semiconductor structure300. The second deck105may be formed in the same manner as formation of the first deck103(FIG. 1A). For example, openings may be formed in the stack of alternating levels of insulative material110and conductive material112, portions of the conductive material112may be removed to form recesses, the other dielectric material128may be formed in the recesses, the electrode material126may be formed adjacent to the other dielectric material128, the dielectric material124may be formed adjacent to the electrode material126, and the channel material120may be formed adjacent to the dielectric material124.

After forming the pillars125(FIG. 1A), the conductive contacts116may be formed through the insulative material114and adjacent to (e.g., over) the pillars125and in electrical communication with the channel material120of the second deck105(FIG. 1A). The conductive line118may be formed in electrical communication with the conductive contacts116.

AlthoughFIG. 3AthroughFIG. 3Dillustrates forming the semiconductor structure300to include the oxide material136to fill the volume between the first deck103(FIG. 1A) and the second deck105(FIG. 1A), the disclosure is not so limited. Referring toFIG. 3CandFIG. 4, after removing the silicon nitride material170(FIG. 3B), the oxide material160may be conformally formed adjacent to (e.g., over, on sides of) the conductive contacts132and the etch stop material172, if present. For example, the oxide material160may form a liner over the uppermost insulative material110, the conductive contacts132, and the etch stop material172. The oxide material160may be formed by, for example, one or more of CVD, ALD, plasma enhanced ALD, PVD, PECVD, or LPCVD.

After forming the oxide material160, the conductive material162may be formed adjacent to surfaces of the oxide material160and the semiconductor structure400may be exposed to a CMP process. The second deck105(FIG. 2) may be formed adjacent to the conductive material162as described above with reference toFIG. 3Dto form the microelectronic device200described with reference toFIG. 2.

AlthoughFIG. 3AthroughFIG. 3DandFIG. 4have been described as a gate first process, the disclosure is not so limited. In other embodiments, the microelectronic devices100,200may be formed by a so-called “replacement gate” process. In some such embodiments, rather than forming the stack to include alternating levels of the insulative material110and the conductive material112as described above with reference toFIG. 3A, a stack comprising alternating levels of the insulative material110and an other insulative material may be formed adjacent to the conductive material108(e.g., the conductive materials112ofFIG. 3Amay be replaced with the other insulative material). The other insulative material may comprise an electrically insulative material exhibiting an etch selectivity relative to the insulative material110, such as silicon nitride. Openings may be formed through the stack of alternating levels of the insulative material110and the other insulative material and through the conductive material108and the etch stop material106. A channel material may be formed in the openings, such as in an entirety of the opening or at least on sidewalls of the opening. In some embodiments, a dielectric material (e.g., silicon dioxide) may fill a remainder of the opening. Additional openings through the alternating levels of the insulative material and the other insulative material may be formed to expose the source104. The other insulative material may be selectively removed relative to the insulative material110to form recesses between adjacent levels of the insulative material110. After removing the other insulative material, memory cells130may be formed in the another openings, such as by forming a dielectric material (e.g., a charge storage material) in the recesses, forming an electrode material adjacent to the charge storage material, and forming an insulative material in the remaining portion of the another openings. In other embodiments, the other dielectric material128is formed in the recesses, the electrode material126is formed adjacent to the other dielectric material128, and the dielectric material124is formed adjacent to the electrode material126. The microelectronic device may be completed as described above.

Accordingly, in at least one embodiment, a method of forming a microelectronic device comprises forming a first deck comprising a channel material extending through a stack of alternating levels of a first material and a second material, forming a nitride material adjacent to the first deck, forming openings in the nitride material and conductive contacts in the openings, removing the nitride material, forming an oxide material adjacent to the conductive contacts, and forming a second deck adjacent to the oxide material, the second deck comprising alternating levels of a first material and a second material.

Microelectronic devices (e.g., the microelectronic devices100,200) including the oxide material136or the oxide material160and the conductive material162between the first deck103and the second deck105in accordance with embodiments of the disclosure may be used in embodiments of electronic systems of the disclosure. For example,FIG. 5is a block diagram of an illustrative electronic system503according to embodiments of disclosure. The electronic system503may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPAD® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system503includes at least one memory device505. The memory device505may include, for example, an embodiment of a microelectronic device previously described herein (e.g., microelectronic devices100,200) including an oxide material (e.g., the oxide material136or the oxide material160) between adjacent decks (e.g., the first deck103, the second105) comprising a material that does not trap charges.

The electronic system503may further include at least one electronic signal processor device507(often referred to as a “microprocessor”). The electronic signal processor device507may, optionally, include an embodiment of a microelectronic device previously described herein (e.g., the microelectronic devices100,200). The electronic system503may further include one or more input devices509for inputting information into the electronic system503by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system503may further include one or more output devices511for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device509and the output device511may comprise a single touchscreen device that can be used both to input information to the electronic system503and to output visual information to a user. The input device509and the output device511may communicate electrically with one or more of the memory device505and the electronic signal processor device507.

With reference toFIG. 6, depicted is a processor-based system600. The processor-based system600may include various electronic devices manufactured in accordance with embodiments of the present disclosure. The processor-based system600may be any of a variety of types such as a computer, pager, cellular phone, personal organizer, control circuit, or other electronic device. The processor-based system600may include one or more processors602, such as a microprocessor, to control the processing of system functions and requests in the processor-based system600. The processor602and other subcomponents of the processor-based system600may include microelectronic devices (e.g., microelectronic devices100,200) manufactured in accordance with embodiments of the present disclosure.

The processor-based system600may include a power supply604in operable communication with the processor602. For example, if the processor-based system600is a portable system, the power supply604may include one or more of a fuel cell, a power scavenging device, permanent batteries, replaceable batteries, and rechargeable batteries. The power supply604may also include an AC adapter; therefore, the processor-based system600may be plugged into a wall outlet, for example. The power supply604may also include a DC adapter such that the processor-based system600may be plugged into a vehicle cigarette lighter or a vehicle power port, for example.

Various other devices may be coupled to the processor602depending on the functions that the processor-based system600performs. For example, a user interface606may be coupled to the processor602. The user interface606may include input devices such as buttons, switches, a keyboard, a light pen, a mouse, a digitizer and stylus, a touch screen, a voice recognition system, a microphone, or a combination thereof. A display608may also be coupled to the processor602. The display608may include an LCD display, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or a combination thereof. Furthermore, an RF sub-system/baseband processor610may also be coupled to the processor602. The RF sub-system/baseband processor610may include an antenna that is coupled to an RF receiver and to an RF transmitter (not shown). A communication port612, or more than one communication port612, may also be coupled to the processor602. The communication port612may be adapted to be coupled to one or more peripheral devices614, such as a modem, a printer, a computer, a scanner, or a camera, or to a network, such as a local area network, remote area network, intranet, or the Internet, for example.

The processor602may control the processor-based system600by implementing software programs stored in the memory. The software programs may include an operating system, database software, drafting software, word processing software, media editing software, or media playing software, for example. The memory is operably coupled to the processor602to store and facilitate execution of various programs. For example, the processor602may be coupled to system memory616, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. The system memory616may include volatile memory, non-volatile memory, or a combination thereof. The system memory616is typically large so that it can store dynamically loaded applications and data. In some embodiments, the system memory616may include microelectronic devices, such as the microelectronic devices (e.g., the microelectronic devices100,200) described above, or a combination thereof.

The processor602may also be coupled to non-volatile memory618, which is not to suggest that system memory616is necessarily volatile. The non-volatile memory618may include one or more of STT-MRAM, MRAM, read-only memory (ROM) such as an EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with the system memory616. The size of the non-volatile memory618is typically selected to be just large enough to store any necessary operating system, application programs, and fixed data. Additionally, the non-volatile memory618may include a high-capacity memory such as disk drive memory, such as a hybrid-drive including resistive memory or other types of non-volatile solid-state memory, for example. The non-volatile memory618may include microelectronic devices, such as the microelectronic devices (e.g., the microelectronic devices100,200) described above, or a combination thereof.

Accordingly, in at least some embodiments, an electronic system comprises a first deck and a second deck. Each of the first deck and the second deck comprise a stack of alternating levels of conductive material and insulative material, and pillars comprising a channel material extending through the alternating levels of the conducive material and the insulative material. The electronic system further comprises conductive contacts between the channel material of the pillars of the first deck and the channel material of the pillars of the second deck, and an oxide material adjacent to the conductive contacts and between the first deck and the second deck.