Method and apparatus for an LNA with high linearity and improved gain control

An LNA comprising an input stage to amplify an input signal. The input stage has a high linear transconductance that has reduced gain variations in response to changes in process and environmental conditions.

TECHNICAL FIELD

An aspect of the invention relates to Metal Oxide Semiconductor Field Effect Transistor (MOSFET) amplifiers.

BACKGROUND

There is a growing demand for mobility in today's world. The rapid progress in the wireless industry makes the ubiquitous connection possible. Radio Frequency (RF) transceivers are important components for wireless devices. The majority of the RF ICs used in the wireless communication were implemented using either GaAs or silicon bipolar technologies. Not until recently, when the continuous scaling of CMOS technology brought the cutoff frequency (fT) of MOS transistors up to multi-tens of GHz, were such circuits built in CMOS technology possible. The advantage of using Complementary Metal-Oxide-Semiconductor (CMOS) RF is that it can be integrated with digital functions easily. As a result, it is possible to incorporate the whole system on one single chip which yields low cost, small form factor wireless devices. A Low Noise Amplifier (LNA) is an important building block in the wireless transceiver. For LNAs, the gain linearity applied to a signal is an important operating characteristic, especially when the incoming signal is large. Under that condition, amplification by the LNA actually could be greater or smaller than one, and the noise contribution from the LNA may be negligible compared to the input signal. In fact, the linearity of the LNA becomes the most important figure of merit. Gain linearity is generally characterized as a 1 dB compression point or third order Input Intercept Point (IIP3). The gain linearity is typically related to the transconductance of a MOSFET in an input stage of the amplifier. For example, the transconductance of a MOSFET operating in the saturation region is constant only when the input signal is small. When the input signal is large, the transconductance may vary as a function of the input signal, leading to nonlinear amplification of the signal. Source degeneration may be employed at lower frequencies to increase the linearity of the input stage. However, at higher frequencies source degeneration may not be effective due to the large parasitic capacitance of the device. Also, source degeneration may increase power consumption due to the relative low gm/Id for the MOSFET in comparison with a bipolar device. In addition, Gain control is also very important in practical applications since the gain of the LNA could vary with process and temperature if not properly controlled.

SUMMARY

An LNA comprising an input stage to amplify an input signal. The LNA being particularly suitable for amplifying large input signals. The input stage includes a linearized transconductance and has reduced gain variations in response to changes in process and environmental conditions.

DETAILED DESCRIPTION

FIG. 1shows an aspect of a wireless transceiver10for communicating information. The wireless transceiver10may include a Low Noise Amplifier (LNA)12for amplifying an input signal. An input signal14to the LNA12may be amplified by a linear input stage18constructed in accordance with the principles of the invention. A bias circuit16may supply bias signals to the linear input stage18in accordance with the principles of the invention. The LNA12preferably includes both the bias circuit16and the linear input stage18. However, the LNA12may include the bias circuit16combined with a conventional linear input stage, or the linear input stage18combined with a conventional bias circuit. An output stage20may provide further amplification of the input signal.

A mixer22may combine the amplified input signal with a Radio Frequency (RF) LO signal24. A filter26and amplifier23may filter and amplify the combined signal, and mix the generated signal with an Intermediate Frequency (IF) LO signal. An analog-to-digital converter (ADC)28may convert the mixed signal to a digital signal for further processing.

A digital-to-analog converter27may convert a digital signal to an analog signal for transmission by a transmitter25.

FIG. 2Bshows an aspect of an NMOS implementation210of the LNA input stage200. The resistance of a first device212is modulated in response to an input signal vin. An NMOS transistor214in combination with an amplifier216provides a low impedance at the junction of the NMOS transistor214and the first device212.

FIG. 2Cshows an aspect of another NMOS implementation220of the LNA input stage210. Here, the resistance of a first NMOS transistor222is modulated in response to an input signal vin. The first NMOS transistor is biased into the triode region. A second NMOS transistor224in combination with an amplifier226provide a low impedance at the junction of the first and second NMOS transistors222and224.

FIG. 2Dshows an aspect of an amplifier30for amplifying an input signal in accordance with the principles of the LNA input stage200. Here, a linear input stage32may include an upper MOSFET, MB,34and a lower MOSFET, MA,36connected in a cascode configuration. The input impedance of the upper MOSFET34at the junction of the upper and lower MOSFETs34and36, may be made low relative to the lower MOSFET36by controlling the relative sizes of the upper and lower MOSFETs34and36. The linear input stage32is preferably constructed as an integrated circuit using Complementary Metal Oxide Semiconductor (CMOS) technology, but other circuit technologies may also be used including discrete MOSFETs. Both NMOS and PMOS devices may be used. An input signal is AC coupled through a capacitor40to the gate of the lower MOSFET36. A bias circuit38biases the upper MOSFET34into the saturation region and the lower MOSFET36into the triode region. Here, the lower MOSFET36acts as a variable resistor changing conductance in linear proportion to changes in the input signal. The impedance of the junction of MOSFETs34and36may be made lower by selecting the transconductance, gm, of the upper MOSFET34to be larger than both gdsand gmof the lower MOSFET36so that Vds of the lower MOSFET36remains relatively constant over changes in the input signal. For example, an input switch ratio defined as the ratio of the size of the upper MOSFET34to the size of the lower MOSFET36may be selected to be at least four, so that gmof the upper MOSFET34is greater than both the gdsand gmof the lower MOSFET. One aspect of the invention recognizes that if the Vds of the lower MOSFET36is maintained relatively constant and the lower MOSFET36is biased into the triode region, then the output current of the lower MOSFET36will be linearly proportional to the input signal. The following derivation illustrates that for a device in deep triode region:Id=⁢μ⁢⁢C⁢⁢WL⁡[(Vgs-Vth)⁢⁢Vds-12⁢⁢Vds2],gds=⁢∂Id∂Vds=μ⁢⁢C⁢⁢WL⁡[(Vgs-Vth)-Vds]≈β⁢⁢(Vgs-Vt),⁢where⁢⁢β=μ⁢⁢C⁢⁢WL,
the output AC current is as follows:
iout=νdsgds=β(Vgs−Vt)νds
Which shows that ioutmay be a linear function of the input signal, leading to an increase in linearity. The amount of linearity achieved may be controlled by adjusting the ratio of the upper MOSFET size to the lower MOSFET size. A load resistor39may be connected to the upper MOSFET34. Another way of looking at it is to view the lower MOSFET36as a normal MOSFET which has its own transconductance gm. The following derivation illustrates that the linearity of gmmay be dependent on Vds for a MOSFET operated in the triode region.Id=μ⁢⁢C⁢⁢WL⁡[(Vgs-Vth)⁢⁢Vds-12⁢⁢Vds2],
thus the transconductance of the device is,gm=μ⁢⁢C⁢⁢WL⁢⁢Vds=β⁢⁢Vds

The sensitivity of gm to variations in the input signal may be reduced by reducing the sensitivity of Vds to variations in the input signal, thereby increasing the linearity of the amplification.

However, since β is function of process and temperature variation, the gain of the amplifier may vary too. One way to reduce that sensitivity is to bias the input stage so that βVds is less sensitive to environmental variations.

FIG. 3shows an aspect of a bias circuit50for a linear input stage. The bias circuit50may control the variation of the linear input stage transconductance to reduce sensitivity to process, environmental effects such as temperature, and power. The bias circuit50includes an upper MOSFET, M2,52connected to a lower MOSFET M1,54. The upper MOSFET52is operated in the saturation region and the lower MOSFET is operated in the triode region. A third MOSFET, M3,56operates to bias the lower MOSFET52into the triode region. To set the bias to the lower MOSFET52, the magnitude of the current, I3, flowing through M356may be controlled as well as controlling the physical characteristics of M356such as size. For example, if I3is selected to equal I1(the current flowing through M1), then a bias switch ratio defined as the ratio of the size of M356to the size of M154should be selected to be at least greater than one, and preferably greater than 1.4. A resistor58connected from the gate of M156decouples the input signal from the bias circuit50.

FIG. 4shows an aspect of an amplifier59including a bias circuit60connected to a linear input stage82. The bias circuit60is similar in function to bias circuit50with corresponding elements in the range of62to68. The linear input stage82is similar in function to linear input stage32with corresponding elements in the range of84to86. The amplifier59advantageously combines the benefits of both the linear input stage82and the bias circuit60. An input signal may be AC coupled through a capacitor60to the gate of the lower MOSFET86. A load resistor88may be connected to the upper MOSFET84to obtain an output from the drain of the upper MOSFET84.

The following derivation may be used to select the devices for the linear input stage82and the bias circuit60of a preferred embodiment, and demonstrate how the gm of the input stage is controlled to be less sensitive to environmental variations. The linear input stage transconductance, gmAmay be as follows: gmA=βVds,A=β(Vb−Vdsat,B−Vth,B) where Vbis the voltage from the gate of MB to ground.

For discussion purpose, let's assume(WL)2=(WL)B,(WL)1=(WL)A,
and I1=I2, then Vdsa,2=Vdsat,Band Vth,2=Vth,B, the transconductance of MA becomes; gmA=β(Vb−Vdsat,2−Vth,2)=βVds,1. I1is not limited to any specific ratio of I2as long as the ratio of (W/L)1to (W/L)Aand (W/L)2to (W/L)Bare properly scaled so that the current densities are about the same for those devices. The ratio of the size of M2to the size of M1should be approximately equal to the ratio of the size of MB to the size of MA.

For the same reason, let's assume I3=I1, and(WL)1=X·(WL)3,
where X≧1.0 and preferably 1.4. Then M1is also in the triode region, and if M1in deep triode region, Vgs−Vth>>Vds/2, then I1≈β(Vgs,1−Vth,1)Vds,1gm⁢⁢A=β⁢⁢Vds,1=β⁢⁢I1β⁢⁢(Vgs,1-Vth,1)=I3(Vgs,1-Vth,3)=gm,3/2.

If current I3is a constant gm bias current which is;Ids=Aβ,
where A can be chosen to only depend on an external resistor value and ratio of two transistors [1], then, gmA=gm,3/2=√{square root over (2*I3*β)}/2=√{square root over (A/2)} which is a constant.

Here, I3does not have to equal I1, instead “X”, the ratio of the size of M3to the size of M1, can be set to a predetermined value and the ratio of I3to I1varied. Also, the ratios(WL)1
and(WL)3
may be varied to bias M1into the triode region.

FIG. 5shows an aspect of an operation for generating a linear input stage. Starting at block100, a semiconductor die is provided. At block102, a first MOSFET having a predetermined size is formed. At block104, a second MOSFET having a size greater than the first MOSFET is formed. At block106, the second MOSFET is connected in cascode with the first MOSFET. At block108, the first MOSFET is biased into the triode region. At block110, the second MOSFET is biased into the saturation region. At block112, an input signal is applied to the gate of the first MOSFET causing a change in Idof the MOSFETs that is approximately a linear function of the AC voltage applied to the first MOSFET gate.

FIG. 6shows an aspect of an operation for biasing a linear input stage. Starting at blocks120and122, first and second MOS devices are provided. At block124, the ratio of the first MOS device size to the second MOS device is selected to be a predetermined value, Rb. At block126, the second MOS device is connected in cascode with the first MOS device. At block128, the first MOS device is biased into the triode region. At block130, the second MOS device is biased into the saturation region such as by connecting the gate and drain of the second MOS device together. At block132, a linear input stage having “A” and “B” MOS devices is provided. At block134, the ratio of the “A” MOS size to the “B” MOS size is selected to be about Rb. At block136, the first and second MOS devices are connected to the linear input stage.