Digital calibration of transmit digital to analog converter full scale current

A method and apparatus for a method of calibrating a transmit digital to analog converter full-scale current. The method comprises generating a tuned reference current and then calibrating the tuned reference current to a selected value in order to produce a predetermined current value. The calibration further comprises dividing a reference voltage input over a resistor string. A band gap current is then generated using the divided reference voltage input. A tuned current output is then produced from a current steering digital to analog converter with the tuned output current stored in a register. The reference current for the transmit DAC is then generated based on the stored tuned output current.

FIELD

The present disclosure relates generally to digital calibration of a transmit digital to analog converter (DAC) full-scale current, and more particularly, to calibrate the reference current of the transmit DAC to provide a full-scale output current that is accurate within predefined limits.

BACKGROUND

Wireless communication devices have become smaller and more powerful as well as more capable. Increasingly users rely on wireless communication devices for mobile phone use as well as email and Internet access. At the same time, devices have become smaller in size. Devices such as cellular telephones, personal digital assistants (PDAs), laptop computers, and other similar devices provide reliable service with expanded coverage areas. Such devices may be referred to as mobile stations, stations, access terminals, user terminals, subscriber units, user equipments, and similar terms.

A wireless communication system may support communication for multiple wireless communication devices at the same time. In use, a wireless communication device may communicate with one or more base stations by transmissions on the uplink and downlink. Base stations may be referred to as access points, Node Bs, or other similar terms. The uplink or reverse link refers to the communication link from the wireless communication device to the base station, while the downlink or forward link refers to the communication from the base station to the wireless communication devices.

Wireless communication systems may be multiple access systems capable of supporting communication with multiple users by sharing the available system resources, such as bandwidth and transmit power. Examples of such multiple access systems include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, wideband code division multiple access (WCDMA) systems, global system for mobile (GSM) communication systems, enhanced data rates for GSM evolution (EDGE) systems, and orthogonal frequency division multiple access (OFDMA) systems.

Mobile devices require an accurate current to correctly operate the device. In particular, an accurate current is needed for modem operation, which provides for calling and other advanced features. As chips become more complex, with more features combined within one die, such as the system on chip (SoC), both layout and current control become more challenging. An additional challenge is that more features must be routed using a limited number of pins, which makes device testing more difficult as many tests require the same output pins.

Mobile devices are also becoming increasingly popular, with many relying on them in place of conventional landlines. With increase use and popularity, it is important to test and produce mobile devices in the most expeditious and cost-effective manner. One area that currently limits automation is calibrating the reference current of the transmit digital to analog converter (DAC). At present, the reference current is calibrated using cumbersome analog and digital techniques to calibrate the current. These current techniques are designed to ensure a full-scale output current at a specified value, typically 2 mA. The transmit DAC output current full-scale value must be accurate within a specified value, and often requires very high precision of +/−1%. This accuracy may vary depending on the device and the operating system. A SoC may require this level of accuracy because the reference current generation may be done on the mobile station modem (MSM) side, (inside the transmit DAC) function, without any knowledge of information from the SoC system. Because the MSM may include process variations arising from variations from the incorporated resistors it is necessary to calibrate the full-scale output current on the transmit DAC. The variation in those resistors may be quite significant and require considerable individual adaptation in order to generate a reference current of the desired level of accuracy.

Previously, this variation was addressed by selectively blowing fuses to correct the on-chip resistor to match a known, external golden resistor. Once the resistor is tuned, it is then used as part of the band gap current generation circuit that generates a band gap reference current. A current mirror circuit would then be used with different multiplication ratios to multiply the input band gap current to the desired final reference current for the transmit DAC.

An alternate method also used previously involved blowing fuses to match a known, external golden resistor. Once the resistor is tuned, it is then used as part of a voltage circuit (V2I) to generate an accurate reference current. A current mirror circuit is then used with different multiplication ratios to multiply the reference current to the final desired reference current for the transmit DAC.

Each of the above methods has disadvantages. The methods require both hands-on digital and analog techniques that require individual adjustment on each chip. This increases time and cost. The methods may also require additional pins for testing and require routing traces to resistors that must be located nearby for greatest accuracy, which adversely affects the circuit board size and may also result in temperature hot spots on the circuit board. These methods also provide only limited gain adjustment and lack precision.

There is a need in the art for a method of digitally calibrating the reference current input of the transmit DAC to provide an accurate current within specified bounds.

SUMMARY

Embodiments contained in the disclosure provide a method of calibrating a transmit digital to analog converter full-scale current. The method comprises generating a tuned reference current and then calibrating the tuned reference current to a selected value in order to produce a predetermined current value. The calibration further comprises dividing a reference voltage input over a resistor string. A band gap current is then generated using the divided reference voltage input. A tuned current output is then produced from a current steering digital to analog converter with the tuned output current stored in a register. The reference current for the transmit DAC is then generated based on the stored tuned output current.

A further embodiment provides an apparatus for calibrating a transmit digital to analog converter full-scale current. The apparatus includes a device current driver amplifier and a current amplifier that is connected to the device current driver amplifier. The apparatus also includes a resistor string, a current steering digital to analog converter (DAC) that is connected to the current amplifier, and a current mirror.

A still further embodiment provides an apparatus for calibrating a transmit digital to analog converter full-scale current. The apparatus comprises: means for generating a tuned reference current and means for calibrating the tuned reference current to a selected value to produce a predetermined current value. The means for calibration further comprises: means for dividing a reference voltage input over a resistor string; means for generating a band gap current using the divided reference voltage input; means for producing a tuned current output from a current steering digital to analog converter; means for storing the tuned output from the tuned current steering digital to analog converter in a register; and means for generating the reference current for the transmit digital to analog converter based on the stored tuned output current.

A yet further embodiment provides a non-transitory computer readable media that includes program instructions, which when executed by a processor cause the processor to perform a method comprising the steps of: generating a tuned reference current and calibrating the tuned reference current to a selected value to produce a predetermined current value. The step of calibrating the tuned reference current to a selected value to produce a predetermined current value further comprises: dividing a reference voltage input over a resistor string; generating a band gap current using the divided reference voltage input; producing a tuned current output from a current steering digital to analog converter; storing the tuned output current from the tuned current steering digital to analog converter in a register; and generating the reference current for the transmit digital to analog converter based on the stored tuned output current.

DETAILED DESCRIPTION

Furthermore, various aspects are described herein in connection with an access terminal and/or an access point. An access terminal may refer to a device providing voice and/or data connectivity to a user. An access wireless terminal may be connected to a computing device such as a laptop computer or desktop computer, or it may be a self-contained device such as a cellular telephone. An access terminal can also be called a system, a subscriber unit, a subscriber station, mobile station, mobile, remote station, remote terminal, a wireless access point, wireless terminal, user terminal, user agent, user device, or user equipment. A wireless terminal may be a subscriber station, wireless device, cellular telephone, PCS telephone, cordless telephone, a Session Initiation Protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), a handheld device having wireless connection capability, or other processing device connected to a wireless modem. An access point, otherwise referred to as a base station or base station controller (BSC), may refer to a device in an access network that communicates over the air-interface, through one or more sectors, with wireless terminals. The access point may act as a router between the wireless terminal and the rest of the access network, which may include an Internet Protocol (IP) network, by converting received air-interface frames to IP packets. The access point also coordinates management of attributes for the air interface.

Other aspects, as well as features and advantages of various aspects, of the present invention will become apparent to those of skill in the art through consideration of the ensuring description, the accompanying drawings and the appended claims.

FIG. 1illustrates a multiple access wireless communication system100according to one aspect. An access point102(AP) includes multiple antenna groups, one including104and106, another including108and110, and an additional one including112and114. InFIG. 1, only two antennas are shown for each antenna group, however, more or fewer antennas may be utilized for each antenna group. Access terminal116(AT) is in communication with antennas112and114, where antennas112and114transmit information to access terminal116over downlink or forward link118and receive information from access terminal116over uplink or reverse link120. Access terminal122is in communication with antennas106and108, where antennas106and108transmit information to access terminal122over downlink or forward link124, and receive information from access terminal122over uplink or reverse link126. In a frequency division duplex (FDD) system, communication link118,120,124, and126may use a different frequency for communication. For example, downlink or forward link118may use a different frequency than that used by uplink or reverse link120.

Each group of antennas and/or the area in which they are designed to communicate is often referred to as a sector of the access point. In an aspect, antenna groups are each designed to communicate to access terminals in a sector of the areas covered by access point102.

In communication over downlinks or forward links118and124, the transmitting antennas of an access point utilize beamforming in order to improve the signal-to-noise ration (SNR) of downlinks or forward links for the different access terminals116and122. Also, an access point using beamforming to transmit to access terminals scattered randomly through its coverage causes less interference to access terminals in neighboring cells than an access point transmitting through a single antenna to all its access terminals.

An access point may be a fixed station used for communicating with the terminals and may also be referred to as a Node B, an evolved Node B (eNB), or some other terminology. An access terminal may also be called a mobile station, user equipment (UE), a wireless communication device, terminal or some other terminology. For certain aspects, either the AP102, or the access terminals116,122may utilize the techniques described below to improve performance of the system.

FIG. 2shows a block diagram of an exemplary design of a wireless communication device200. In this exemplary design, wireless device200includes a data processor210and a transceiver220. Transceiver220includes a transmitter230and a receiver250that support bi-directional wireless communication. In general, wireless device200may include any number of transmitters and any number of receivers for any number of communication systems and any number of frequency bands.

In the transmit path, data processor210processes data to be transmitted and provides an analog output signal to transmitter230. Within transmitter230, the analog output signal is amplified by an amplifier (Amp)232, filtered by a lowpass filter234to remove images caused by digital-to-analog conversion, amplified by a VGA236, and upconverted from baseband to RF by a mixer238. The upconverted signal is filtered by a filter240, further amplified by a driver amplifier,242and a power amplifier244, routed through switches/duplexers246, and transmitted via an antenna249.

In the receive path, antenna248receives signals from base stations and/or other transmitter stations and provides a received signal, which is routed through switches/duplexers246and provided to receiver250. Within receiver250, the received signal is amplified by an LNA252, filtered by a bandpass filter254, and downconverted from RF to baseband by a mixer256. The downconverted signal is amplified by a VGA258, filtered by a lowpass filter260, and amplified by an amplifier262to obtain an analog input signal, which is provided to data processor210.

FIG. 2shows transmitter230and receiver250implementing a direct-conversion architecture, which frequency converts a signal between RF and baseband in one stage. Transmitter230and/or receiver250may also implement a super-heterodyne architecture, which frequency converts a signal between RF and baseband in multiple stages. A local oscillator (LO) generator270generates and provides transmit and receive LO signals to mixers238and256, respectively. A phase locked loop (PLL)272receives control information from data processor210and provides control signals to LO generator270to generate the transmit and receive LO signals at the proper frequencies.

FIG. 2shows an exemplary transceiver design. In general, the conditioning of the signals in transmitter230and receiver250may be performed by one or more stages of amplifier, filter, mixer, etc. These circuits may be arranged differently from the configuration shown inFIG. 2. Some circuits inFIG. 2may also be omitted. All or a portion of transceiver220may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. For example, amplifier232through power amplifier244in transmitter230may also be implemented on an RFIC. Driver amplifier242and power amplifier244may also be implemented on another IC external to the RFIC.

Data processor210may perform various functions for wireless device200, e.g., processing for transmitter and received data. Memory212may store program codes and data for data processor210. Data processor210may be implemented on one or more application specific integrated circuits (ASICs) and/or other ICs.

Embodiments described herein address calibrating the reference current input of a transmit DAC using a combination of analog and digital techniques, so that the transmit DAC full-scale output current is at an accurate preselected level, such as 2 mA. The embodiments described herein provide very accurate current, and may be within ±0/5% for a 2 mA current. The methods also correct for a wide range of resistor variation, and may achieve ±64% range correction with minimal hardware. The range achieved may depend on the number of bits used. This reduces the amount of hardware needed. The methods provide more accurate full-scale output current and allow automation of the current reference for the final transmit DAC current.

Instead of tuning the resistor string or “ladder” to achieve a more accurate current, embodiments described herein use a current steering DAC to generate a tuned reference current. This tuned reference current is then calibrated to a selected value, such that the final transmit DAC full-scale current is the desired value. The programming range may be automatically resized according to the tuned value. A simple resistor is used along with a current steering DAC. This final output current is measured on input to a golden resistor.

A further advantage is that the techniques described are highly programmable because digital tuning of the tuned value is provided, with 0/1 dB steps in the DAC full-scale output. The techniques are implemented as a digital feature that automatically resizes the programming range according to the tuned value. In addition, because the DAC output pins are reused during the calibration, package pins are saved for other uses.

The method also is capable of a wide range of gain adjustment, which may be from +1.5 dB to −19.5 dB with 0.1 step sizes, with the range indicating how much resistor variation may be corrected. The gain range may be determined by distributing the gain adjustment in three places: 6 dB steps in the resistor ladder, 3 dB steps in the NMOS current mirror, and +1.5 dB steps in the IFS DAC. NEED DEFINITION OF IFS. This flexibility also results in a saving of area and power efficiency, when compared with more traditional approaches.

FIG. 3illustrates an embodiment of the apparatus for performing the method of digital calibration of transmit DAC converter full-scale current. The full-scale current calibrating system300, includes a device current driver amplifier302connected to current amplifier312. This current driver amplifier302is trying to apply a reference voltage to resistor string304A-D, thus creating a current that is proportional to the resistor string. Resistor string304may move in 6 dB steps, however, depending on application, different steps may be selected. Current amplifier312is connected to IFS DAC314. IFS DAC314is controlled by the digital logic306. The IFS DAC314creates a replica of the current generated in the resistor ladder string304and this replica is controlled by digital code to produce a tuned current. Because the code is digital it may be changed to produce finer gain steps, and need only be changed by a few least significant bits (LSB) to accommodate this. Tuned current from IFS DAC314is input to current mirror308, which incorporates transistor310.

Band gap current is generated using the V2I circuit by driving the voltage reference (VREF) over the resistor string304A-D. The reference current forms the unit currents inside the current steering (IFS)DAC314and is controlled by the V2I circuit composed of operational amplifier302and resistor string304.

IFS DAC314takes eight bits of digital input, which represents the tuned value. This tuned value is then stored in a fuse register306. The tuned current is then used by current mirror308to generate the reference current for the transmit DAC. The current mirror308, which is an NMOS current mirror, achieves −3 dB steps at any gain setting. Resistor string304A-D achieves −6 dB steps at any gain setting. The resistor values may be scaled to produce 6 dB step sizes, which are beyond the range of the IFS DAC314. However, for different step sizes different resistor string values may be selected without departing from the scope of the method described herein. The IFS DAC314provides +1.5 dB to −1.5 dB gains at any gain setting selected. Temperature compensation for the V2I reference current is provided due to the finite TiN resistor temperature coefficient.

FIG. 4illustrates the digital encoding system with a digital decoder, according to an embodiment described herein.FIG. 4also provides a detailed circuit implementation of the concept presented inFIG. 2. The circuit,400, includes the device current amplifier312and resistor string304A-D, which comprise the V2I circuit. Device current driver amplifier302is connected to transistor312. Transistor312inputs to most significant bit (MSB) device402(devices1-7) and404(8thdevice). MSB transistor402is connected to switches420A and420B. Switch420A provides an input to current mirror426. Switch420B provides an input to operational amplifier422. 8thMSB transistor404provides inputs to transistors408,410,412,414,416, and418. Each of these transistors is in turn connected to two switches, respectively420C and420D,420# and420F,420G,420H,420J, and420K,420L, and420M and420N and420P. Digital decoder424provides 7:1 MSB input and least significant bit (LSB) (4:0) input to the switch series.

In operation, eight bits are used for tuning, with three MSB bits implemented as thermometer decoding, with the remaining five bits used in a binary fashion. The 8thMSB is split using a current splitter with cascode devices. The +voltage side current is the output of the DAC representing the tuned current. The −voltage side current is directed to ground. The over the air (OTA) for the LSB is needed to maintain the differential non-linearity (DNL) error accuracy of the LSB splitter section.

FIG. 5shows the simulation results of digital calibration of transmit DAC full-scale current, in accordance with embodiments described herein. The left diagram illustrates the maximum and minimum type errors seen over a range of +1.5 dB to −1.5 dB without correction. In contrast, the right diagram shows the +1.5 dB to −1.5 dB scale with correction.

A further embodiment provides automatic digital correction for process variations. The unit current inside the IFS DAC may vary with resistor process variation. This arises because of the V2I reference current. As a result, the LSB size changes with each process corner. Changing the code by a determined number of LSBs causes the current to change in each process corner. However, it would be desirable to eliminate the process corner, and this may be done by digitally correcting the LSB size by scaling the digital input. When the digital input is scaled to account for the process corner, the gain steps of 1 dB, or other selected value, will hold through process variation corners of the resistor. The formula, implemented digitally is:

FIG. 6shows an embodiment that provides for reuse of the DAC output pins for calibration. The assembly,600, includes self-bias circuit602, which is connected to the V2I circuit604. The VwI circuit604is connected to IFS DAC606. The IFS DAC606receives input from the digital module608and outputs to NMOS current mirror614. The digital module608is controlled by the comparator610, which compares its two inputs: one is a predetermined reference voltage Vtune and the other is the sensed voltage on Qp node through the Qp switch612. The Qp switch612receives its input from the printed circuit board (PCB) board routing, which is connected directly at the golden resistor632. N-channel metal oxide semiconductor (NMOS) current mirror614provides input to P-channel metal oxide semiconductor (PMOS) MSB DAC616, which is coupled with PMOS LSM DAC618. PMOS LSB DAC616provides inputs to an attenuator, Z,626, DCC624, and resistor ladder R2R620. The voltage reference buffer Vref622is also connected to R2R620. R2R620and DCC624provide inputs to attenuator626. Attenuator626provides two current outputs, ip and im to package routing630and the PCB624, respectively. Package routing632is the golden resistor used in establishing the full-scale calibration current for the transmit DAC. Resistor636is connected to PCB634.

FIG. 6also illustrates how the DAC output pins may be reused for calibration. The calibration requires access to external golden resistor632. The DAC outputs are used for the calibration, in contrast to current techniques, which require additional pins be available. To perform the calibration, the DAC is set at maximum code and all of the current flows out of the ip node. The Ip nodes is connected to golden resistor632. The Qp node is then used to sense the voltage at the external resistor632. The Q output is turned off during the calibration. After calibration the comparison between the actual and desired output current is made and any changes are implemented. This layout provides the benefit of avoiding incurring additional resistance from the package and PSB634trace routing and ensures an accurate sense of the external resistor value.

FIG. 7depicts a further embodiment that provides temperature compensation for the DAC reference current (Iref) due to the on-chip resistor having a high temperature coefficient. Resistors may have a negative temperature coefficient. As the temperature increases the resistance decreases and thus the current increases. This requires that an additional current be created that behaves similarly. This additional current is then subtracted out to create a stable reference current. Assembly700includes a V2I circuit comprised of amplifier702, which provides input to transistor704. Complementary to absolute temperature (CTAT) current iCTAT is created as a result of applying a band gap voltage input to resistor712. A second output of amplifier712provides input to resistor R2,710. Transistor704is connected in parallel with transistor076. Transistor706is also connected to R2710. The output of R2710is connected to diodes714and716, which are in series. The IFS DAC708receives a replica of the current flowing in the transistor704and transistor706. The on-chip resistor has a high negative temperature coefficient (−ve). The reference current generated from the V2I circuit will display a CTAT behavior because of that −ve temperature coefficient. In order to generate a band gap current, a proportional to absolute temperature (PTAT) current must be added to the CTAT current. A simple method is given by the formula: (Vbandgap−Vbe)=VPTAT. VPTAT applied on resistor701inFIG. 7generates a compensating current to remove the temperature coefficient of the current generated by Vbandgap/R1. Resistor R27-1may be scaled appropriately to the temperature coefficient of the R1resistor512. Using the method and apparatus described herein provides a correction of 2-3% of the temperature coefficient of the resistor. The value of the correction naturally depends on the components selected and the design goals.

FIG. 8is a flowchart of a method of calibrating a transmit DAC full-scale current. The method,800begins when a tuned reference current is generated in step802. The tuned reference current is then calibrated to a value selected based on a pre-determined current value in step804.

FIG. 9is a flowchart of a further embodiment of a method of calibrating a transmit DAC full-scale current. The method,900begins with step902. In step902a band gap current is generated in a voltage circuit. This band gap current is produced by dividing a reference voltage input over a resistor string in step904. In step906a tuned current output is produced using a current steering DAC. This tuned current output is then stored in step908. The reference current is then generated based on the tuned output current in step910.