Page buffer circuit of flash memory device with reduced consumption power

A page buffer circuit of a flash memory device has small consumption power. The page buffer circuit utilizes different voltages are supplied to the latch circuits in the standby and normal modes to reduce consumption power in the standby mode.

TECHNICAL FIELD

This patent relates to flash memory devices and more particularly, to a page buffer circuit of a flash memory device.

DISCUSSION OF RELATED ART

Flash memory devices are usually configured to conduct operations of reading, programming, and erasing data therein. And, the flash memory devices employ page buffers to program or read a large amount of data in a short time. Therefore, the programming or reading operation of the flash memory device is carried out in the unit of page by means of the page buffers.

FIG. 1is a diagram of a page buffer circuit used in a conventional flash memory device. The page buffer circuit10is constructed of a bitline selection circuit11, a precharging circuit P11, a main register circuit12, a cache register circuit13, and pass circuit N17˜N21. The main register circuit12includes a main latch circuit14and NMOS transistors N11˜N13. The cache register circuit13includes NMOS transistors N14˜N16. As referred to inFIG. 1, voltages VCC and VSS are input each to the main latch circuit14and the cache latch circuit15as operation voltages.

FIG. 2is a diagram showing the main latch circuit (or cache latch circuit) ofFIG. 1in detail. Referring toFIG. 2, the main latch circuit14(or the cache latch circuit15) includes PMOS transistors P31and P32, and NMOS transistors N31and N32. Sources of the PMOS transistors P31and P32are coupled to the voltage VCC, a node D1is coupled to a drain of the PMOS transistor P31and a gate of the PMOS transistor P32. Further, a node D2is connected to a gate of the PMOS transistor P31and a drain of the PMOS transistor P32. Sources of the NMOS transistors N31and N32are connected to the voltage VSS, and the node D1is coupled to a drain of the NMOS transistor N31and a gate of the NMOS transistor N32. The node D2is connected to a gate of the NMOS transistor N31and a drain of the NMOS transistor N32. The node D1receives or outputs a signal QBb or QAb, and the node D2receives a signal QB or QA. But, when the flash memory device including the page buffer10is being both in standby and normal modes, the nodes D1and D2receive the voltage VCC and VSS as operation voltages for the main latch circuit14and the cache latch circuit15.

Meanwhile, signals at the nodes D1and D2in the main latch circuit14and the cache latch circuit15, QBb or QAb, and QB or QA, are set on predetermined voltage levels. In detail, for example, when the signal of the node D2, QB or QA, is fixed to voltage VSS, the signal of the node D1, QBb or QAb, is fixed to the voltage level VCC. As a result, the PMOS transistor P31and the NMOS transistor N32are turned on while the PMOS transistor P32and the NMOS transistor N31are turned off. Here, through the PMOS and NMOS transistors, P32and N31, which are being turned-off, a leakage current ILwould be generated. Finally, although it needs to minimize the leakage current in the standby mode, the leakage current by the main latch circuit14and the cache latch circuit15causes increasing consumption power in the page buffer10.

SUMMARY OF THE INVENTION

A page buffer circuit of a flash memory device with small consumption power in a standby mode, supplying different power source voltages each to latch circuits in standby and normal modes.

A page buffer of a flash memory device may include a bitline selection circuit connecting one of at least two bitlines to a sensing node in response to bitline selection signals; a cache register circuit storing a program data signal during a programming operation; a main register circuit storing a first state data signal corresponding to a read data signal received from one of the two bitlines through the sensing node in a reading operation, in response to a main latch signal, or storing a second state data signal corresponding to the program data signal received from the cache register circuit through the sensing node in a programming operation; and a power supply circuit providing first and second voltages to the main register circuit and the cache register circuit as operation voltages in an active mode, and providing a third voltage to the main register circuit and the cache register circuit as operation voltages in a standby mode.

The page buffer further may include a precharge circuit charging the sensing node up to a predetermined voltage level in response to a precharge control signal; a first switch transferring the program data signal from the cache register circuit to the main register circuit through the sensing node in the programming operation, in response to a first control signal, and disconnecting the cache register circuit from the sensing node in the reading operation; a second switch transferring an inverse data signal of the second state data signal from the main register circuit to one of the two bitlines connected to the sensing node through the bitline selection circuit in a second control signal during the programming operation; and a third switch transferring an inverse data signal of the first state data signal from the main register circuit to a Y-gate circuit in response to a third control signal during the reading operation.

The third voltage may be lower than the first voltage and higher than the second voltage.

The main register circuit may include a sensing circuit generating the first state data signal in response to the main latch signal and the read data signal, or generating the second state data signal in response to the main latch signal and the program data signal; a main latch circuit, connected to the sensing circuit through a first node, holding the first or second state data signal received through the first node and transferring an inverse data signal of the first state data signal or an inverse data signal of the second state data signal to a second node; and a main latch rest circuit initializing the main latch circuit in response to a main latch reset signal. The first and second nodes have different voltage levels from each other in the active mode, while the first and second nodes have the same voltage level in the standby mode.

The cache register circuit may include a cache latch circuit, connected between a third node and a fourth node, holding the program data signal received through the third node and transferring an inverse data signal of the program data signal to the fourth node, or holding the program data signal and transferring the inversed data signal of the program data signal to the third node; and a cache latch rest circuit, connected to the cache latch circuit through the third node, initializing the cache latch circuit in response to a cache latch reset signal. The third and fourth nodes have different voltage levels from each other in the active mode, while the third and fourth nodes have the same voltage level in the standby mode.

The main latch circuit may include a first inverter having an output terminal connected to the first node and an input terminal connected to the second node, receiving the operation voltages through fifth and sixth nodes; and a second inverter having an input terminal connected to the first node and an output terminal connected to the second node, receiving the operation voltages through the fifth and sixth nodes. The cache latch circuit comprise: a third inverter having an output terminal connected to the third node and an input terminal connected to the fourth node, receiving the operation voltages through seventh and eighth nodes; and a fourth inverter having an input terminal connected to the third node and an output terminal connected to the fourth node, receiving the operation voltages through the seventh and eighth nodes.

The power supply circuit may include a first switch connected among the fifth node, the seventh node, and the first voltage, and being turned on or off in response to a first selection control signal; a second switch connected among the sixth node, the eighth node, and the second voltage, and being turned on or off in response to the first selection control signal; a third switch connected among the fifth node, the seventh node, and the third voltage, and being turned on or off in response to a second selection control signal; and a fourth switch connected among the sixth node, the eighth node, and the third voltage, and being turned on or off in response to the second selection control signal.

In the active mode, the first selection control signal may be enabled while the second selection may be disabled. In the standby mode, the first selection control signal may be disabled while the second selection may be enabled. The first and second switches may be turned on when the first selection control signal is enabled, while the third and fourth switches are turned on when the second selection control signal is enabled.

DETAILED DESCRIPTION

Various embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numerals refer to like elements throughout the specification.

FIG. 3is a diagram illustrating a page buffer circuit of a flash memory device.

Referring toFIG. 3, the page buffer circuit100may include a bitline selection circuit110, a main register circuit120, a cache register circuit130, a power supply circuit140, a precharging circuit P101, and switches N107˜N111. Here, the precharging circuit P101may be implemented by a PMOS transistor, and the switches N107˜N111may be constructed of NMOS transistors. Hereinafter, the precharging circuit P101will be referred to as the PMOS transistor and the switches N107˜N111will be referred to as NMOS transistors. The bitline selection circuit110connects one of bitlines BLe and BLo to a sensing node SO in response to a bitline selection signal BSLe and BSLo. The main register circuit120may include a sensing circuit121, a main latch circuit122, and a main latch reset circuit N101. The sensing circuit121includes NMOS transistors N102and N103. The sensing circuit121generates a first state data signal QB1bin response to a main latch signal MLCH and a read data signal RD received through the sensing node SO, or generates a second state data signal QB2bin response to the main latch signal MLCH and a program data signal QA1or QA2received through the sensing node SO.

The main latch circuit122holds the first state data signal QB1bor the second state data signal QB2bwhich is received from the sensing circuit121, and outputs an inverse data signal QB1of the first state data signal QB1bor an inverse data signal QB2of the second state data signal QB2b. The main latch reset circuit N101initializes the main latch circuit122in response to a main latch reset signal MRST.

The cache register circuit130may include a cache latch circuit131and a cache latch reset circuit N104. The cache latch circuit131holds the program data signal QA1breceived through the NMOS transistor N107when the NMOS transistor N107is turned on, or holds the program data signal QA2received through the NMOS transistor N108when the NMOS transistor N108is turned on. The cache latch circuit131holds the program data signal QA1band outputs the inverse data signal QA1, or holds the program data signal QA2and outputs the inverse data signal QA2b. The cache latch reset circuit N104initializes the cache latch circuit131in response to a cache latch reset signal CSET. The cache register circuit130may further include a cache read control circuit132. The cache read control circuit132does not operate in the normal mode of the page buffer100. During the read operation with using the cache latch circuit131, the cache read control circuit132operates in response to a cache latch signal CLCH.

The PMOS transistor P101precharges the sensing node SO to the voltage VCC in response to a precharge control signal PRECHb. The NMOS transistor N109is turned on or off in response to a control signal PDUMP. The NMOS transistor N109may be turned on during the programming operation. The NMOS transistor N109turned on to the inverse data signal QA1or the program data signal QA2from the cache latch circuit131to the main register circuit120through the sensing node SO, or turned off to disconnect the cache latch circuit131from the sensing node SO.

The NMOS transistor N110outputs the inverse data signal QB2, which is received from the main latch circuit122, to one of the bitlines BLe and BLo connected to the sensing node SO through bitline selection circuit110in the programming mode. The NMOS transistor N111outputs the inverse data signal QB1from the main latch circuit122to the Y-gate circuit200in response to a third control signal PBDO during the reading mode.

The power supply circuit140provides the voltages VCC and VSS for the main register circuit122and the cache register circuit131as operation voltages in response to the selection control signals SCTL1and SCTL2in the active mode. The power supply circuit140also provides a voltage VCC/2 for the main register circuit122and the cache register circuit131as operation voltages in response to the selection control signals SCTL1and SCTL2in the standby mode.

FIG. 4is a diagram illustrating a main latch circuit, a cache latch circuit, and a power supply circuit shown inFIG. 3. it will be described about detailed constructions and operations in the main latch circuit122, the cache latch circuit131, and the power supply circuit140.

Referring toFIG. 4, the main latch circuit122may include inverters123and124. A node N1is commonly connected to an output terminal of the inverter123and an input terminal of the inverter124. A node N2is commonly connected to an input terminal of the inverter123and an output terminal of the inverter124. The inverter124outputs the inverse data signal QB1of the first state data signal or the inverse data signal QB2of the second state data signal to the node N2in response to the first state data signal QB1bor the second state data signal QB2b. The inverter123may be a PMOS transistor P151and an NMOS transistor N151. The inverter124may be a PMOS transistor P152and an NMOS transistor N152. The operation voltages are supplied to the inverters123and124by way of nodes N3and N4.

The cache latch circuit131may include inverters133and134. A node N5is commonly connected to an output terminal of the inverter133and an input terminal of the inverter134. A node N6is commonly connected to an input terminal of the inverter133and an output terminal of the inverter134. The inverter134outputs the inverse data signal QA1to the node N6in response to the program data signal QA1binput through the node N5. The inverter133outputs the inverse data signal QA2bto the node N5in response to the program data signal QA2input through the node N6. The inverter133may be a PMOS transistor P161and an NMOS transistor N161. The inverter134may be a PMOS transistor P162and an NMOS transistor N162. The operation voltages are supplied to the inverters133and134by way of nodes N7and N8.

The power supply circuit140may be switches SW1˜SW4. The switch SW1is connected among the nodes N3and N7, and the voltage VCC, being turned on or off in response to the selection control signal SCTL1. The switch SW2is connected among the nodes N4and N8, and the voltage VSS, being turned on or off in response to the selection control signal SCTL1. The switch SW3is connected among the nodes N3and N7, and the voltage VCC/2, being turned on or off in response to the selection control signal SCTL2. The switch SW4is connected among the nodes N4and N8, and the voltage VCC/2, being turned on or off in response to the selection control signal SCTL2.

Next, it will be described about operations in the main latch circuit122, the cache latch circuit131, and the power supply circuit140during the active and standby modes.

First, in the active mode, the selection control signal SCTL1is enabled while the selection control signal SCTL2is disabled. After then, the switches SW1and SW2are turned on in response to the selection control signal SCTL1while the switches SW3and SW4are turned off in response to the selection control signal SCTL2. As a result, the nodes N3and N7are supplied with the voltage VCC while the nodes N4and N8are supplied with the voltage VSS. In other words, the voltages VCC and VSS are supplied to the main latch circuit122and the cache latch circuit131as the operation voltages. During this, the nodes N1and N2are different from each other in voltage level, and the nodes N5and N6are also different from each other in voltage level. For instance, when the nodes N1and N5are set on the voltage VCC, the nodes N2and N6are established on the voltage VSS.

Next, in the standby mode, the selection control signal SCTL1is disabled while the selection control signal SCTL2is enabled. After then, the switches SW1and SW2are turned off in response to the selection control signal SCTL1while the switches SW3and SW4are turned on in response to the selection control signal SCTL2. As a result, the nodes N3, N4, N7and N8are all supplied with the voltage VCC/2. In other words, the voltages VCC/2 are supplied to the main latch circuit122and the cache latch circuit131as the operation voltages. During this, the nodes N1, N2, N5and N6are maintained on the voltage level of VCC/2. For instance, in the main latch circuit122, the nodes N1and N2are supplied with the voltage VCC/2 when the PMOS transistor151and the NMOS transistor N152are turned on while the PMOS transistor152and the NMOS transistor N151are turned off. As the voltage levels of the nodes N1and N2are the voltage level VCC/2, as same as those of the nodes N3and N4, there is no leakage current through the PMOS transistor P152and the NMOS transistor N151those are turned on. Thus, the page buffer100is able to reduce consumption power by the leakage current in the standby mode.

As stated above, it is possible to reduce consumption power in the page buffer circuit during the standby mode, for which the latch circuits are supplied with different power voltages from each other in the standby and normal modes.