Dynamic circuit using exclusive states

The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion without compromising area or speed. The invention further improves speed of the adders by cutting the latch delay while not requiring complex clocking.

FIELD OF THE INVENTION

The invention relates to dynamic circuits.

BACKGROUND

Dynamic circuits are not robust under noisy condition. For example, a typical dynamic domino circuit uses a half or full latch to hold its dynamic nodes. However, under noisy conditions, these nodes can couple to noise and lose their data. Thus, a need exists for a dynamic domino circuit that is robust under noisy condition.

As another example, in many kinds of dynamic adders, inversion of carry that is required at the end of the carry chain is either accomplished by using a static inverter (extra gate delay) followed by static circuits, or having a separate chain of logic to generate carry bar (area penalty). For a really fast implementation, four chains of logic (g, ˜g, p, ˜p) are needed, thereby consuming a lot of area. Thus, a need exists for a dynamic adder that does not use a static inverter that causes extra gate delay A further need exists for a dynamic adder that does not consume a lot of area.

Furthermore, in most dynamic adders, a latch is required at the output to preserve the generated sum during circuit precharge. A need exists to improve the speed of the adders by cutting the latch delay while not requiring complex clocking.

SUMMARY

The invention provides a dynamic domino circuit that is robust under noisy condition. The invention provides a dynamic adder that does not use a static inverter that causes extra gate delay. The invention also provides a dynamic adder that does not consume a lot of area. The invention also improves speed of the adders by cutting the latch delay while not requiring complex clocking.

Preferably, a dynamic circuit includes a logic portion and three dynamic output portions, each of which having a dynamic node for holding data. A first and a second transistors have their gates coupled to the first dynamic node. The first transistor has its drain coupled to the second dynamic node, and the second transistor has its drain coupled to the third dynamic node. A third and a fourth transistors have their gates coupled to the second dynamic node. The third transistor has its drain coupled to the first dynamic node, and the fourth transistor has its drain coupled to the third dynamic node. A fifth and a sixth transistors having their gates coupled to the third dynamic node. The fifth transistor has its drain coupled to the first dynamic node, and the sixth transistor has its drain coupled to the second dynamic node.

DETAILED DESCRIPTION

Reference is made in detail to the preferred embodiments of the invention. While the invention is described in conjunction with the preferred embodiments, the invention is not intended to be limited by these preferred embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, as is obvious to one ordinarily skilled in the art, the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so that aspects of the invention will not be obscured.

Referring now toFIG. 1, a dynamic domino circuit100is shown in accordance with one embodiment of the invention. Circuit100comprises of a logic portion10coupled to three dynamic output portions120,130and140. Dynamic output portion120is used for holding data for the propagate signal (p). Dynamic output portion130is used for holding data for the generate signal (g). Dynamic output portion140is used for holding data for the kill signal (k).

Referring still toFIG. 1, dynamic output portion120comprises an inverter121, transistors122and123, and dynamic node124. Dynamic output portion130comprises an inverter131, transistors132and133, and dynamic node134. Dynamic output portion140comprises an inverter141, transistors142and143, and dynamic node144.

Transistors132and142are coupled to dynamic node124. Transistors122and143are coupled to dynamic node134. Transistor123and133are coupled to dynamic node144. Assume dynamic nodes124,134and144are mutually exclusive. That is to say, one and only one dynamic node among nodes124,134and144will be at logic zero when the clock is high. As such, when dynamic node124holds a logic zero, dynamic node134holds a logic one and dynamic node144holds a logic one. Similarly, when dynamic node134holds a logic zero, dynamic node124holds a logic one and dynamic node144holds a logic one. Also similarly, when dynamic node144holds a logic zero, dynamic node124holds a logic one and dynamic node134holds a one.

This exclusive property can be used to ensure that the dynamic nodes124,134and144will recover fully from noise. Specifically, as an example, a logic zero being held on dynamic node124turns on transistor132to provide a current to ensure that a logic one is held in dynamic node134. As such, if a noise spike occurs at dynamic node134to change the logic one held therein into a logic zero, the current supplied by transistor132recovers the logic one at dynamic node134. Also, a logic zero being held on dynamic node124turns on transistor142to provide a current to ensure that a logic one is held in dynamic node144. As such, if a noise spike occurs at dynamic node144to change the logic one held therein into a logic zero, the current supplied by transistor142recovers the logic one at dynamic node144. As understood herein, the idea of noise recoverability applies not only to circuit100, but to any class of dynamic circuit that uses exclusive signals.

Continuing withFIG. 1, the same theory holds when node134is being held at logic zero and nodes124and134are being held at logic one. The same theory also holds when node144is being held at logic zero and nodes124and134are being held at logic one.

Referring now toFIG. 2, a portion of a carry chain205of a dynamic adder200is shown in accordance with one embodiment of the invention. Each of dynamic circuits211–217is used to generate successive levels of propagate (p), generate (g), and kill (k) signals. Each set of p, g, and k at each level is mutually exclusive. True dynamic inversion at any point in carry chain205can be achieved as a simple function of true terms.

In one embodiment of the invention, the terms k, p, g can be defined as:k (carry out termination/kill)=>−A & −Bp (carry out propagation)=>A^B or A+Bg (carry out generation)=>A & B
where A and B are inputs such as A0, B0, A1, B1, A2, B2, A3, B3, as referenced inFIG. 2.

As an example, referring still toFIG. 2, consider nodes k0, g0, and p0as shown. Inversion of each of these nodes can be implemented in the form of the following simple equations:
˜p0=g0+k0,
˜g0=p0+k0, and
˜k0=g0+p0,
Similar equations apply for inversion at all other levels of carry chain205.

Also, for i>j>k,
gk(i:k)=gk(i:j)+gp(i:j)+gk(j−1:k)
gp(i:k)=gp(i:j)+gp(j−1:0)
gg(i:k)=gg(i:j)+gp(i:j)+gg(j−1:k)
Group level inversions can be accomplished as a function of true terms as follows:
˜gk(i:k)=gp(i:k)+gg(i:k)
˜gp(i:k)=gg(i:k)+gk(i:k)
˜gg(i:k)=gp(i:k)+gk(i:k)

In this embodiment, the terms k, p, g are mutually exclusive and the terms gk, gp, gg are mutually exclusive. By using exclusivity nature of the terms k/p/g and gk/gp/gg, inversion of signals can be expressed in terms of monotonic signals.

By using true terms to generate complements, a common problem in dynamic signal inversion is circumvented. In a regular dynamic circuit, inversion is frequently implemented by demorganization all the way to the beginning of carry chain205. In so doing, four terms (generate (g), generate bar (˜g), propagate (p), and propagate bar (˜p)) are required per dynamic circuit. On the other hand, by using only three terms rather than the conventional four terms, more area can be saved.

Referring now toFIG. 3A, a final stage of a dynamic adder300is shown in accordance with one embodiment of the invention. A sum stage mux circuit340is coupled to a dynamic logic310and a dynamic carry chain320. A latch350is built into mux circuit340such that no additional delay is introduced in the critical path of adder300. Controlling inputs sel331and ˜sel332are used both as selection signals for mux circuit340and also as a clock for latch350.

Referring now toFIG. 3B, a detailed diagram of mux circuit340is shown in accordance with one embodiment of the invention. As shown, mux circuit340includes latch350coupled to input d0361, input d1362, sel331and ˜sel332. When the clock is high, dynamic nodes sel331and ˜sel332evaluate to their respective logic, thereby functioning as select inputs to mux circuit340. When the clock is low, sel331and ˜sel332precharge to logic zero, thereby cutting off transmission gates371and372. In turn, latch350will hold the state of mux circuit340for the remainder of the clock cycle. As such, a latch has been implemented with neither additional delay nor any complex clocking.