TRANSISTOR DEVICE HAVING CHARGE COMPENSATING FIELD PLATES IN-LINE WITH BODY CONTACTS

A semiconductor device is described. The semiconductor device includes: a plurality of stripe-shaped gates formed in a semiconductor substrate; a plurality of needle-shaped field plate trenches formed in the semiconductor substrate between neighboring ones of the stripe-shaped gates; an insulating layer on the semiconductor substrate; and a plurality of contacts extending through the insulating layer and contacting field plates in the needle-shaped field plate trenches. The contacts have a width that is less than or equal to a width of the needle-shaped field plate trenches, as measured in a first lateral direction which is transverse to a lengthwise extension of the stripe-shaped gates. In the first lateral direction, the contacts are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches. Methods of producing the semiconductor device are also described.

BACKGROUND

Low RDSON(on-state resistance) and low energy switching are key parameters for low voltage MOSFET (metal-oxide-semiconductor field-effect transistor) devices. Some low voltage MOSFET devices include charge compensating field plates for realizing lower RDSONand lower energy switching. The challenge with such devices is to accommodate the source contact, MOS gate, body contact, conducting channel, and charge compensating field plate in the smallest possible cell pitch.

For low voltage MOSFET devices below 40V, a stripe trench structure is typically used with the MOS gate arranged on top of the charge compensating field plate. For medium voltage MOSFETs at 60V and above, a cellular structure with needle field plate provides for an 80% increase in available conduction area compared to equivalent geometry stripe trench designs. In both cases, 2 alignment tolerances are needed to ensure reliable body contact placement which increases cell pitch correspondingly.

Thus, there is a need for an improved power transistor device needle-shaped field plates with reduced cell pitch.

SUMMARY

According to an embodiment of a semiconductor device, the semiconductor device comprises: a plurality of stripe-shaped gates formed in a semiconductor substrate; a plurality of needle-shaped field plate trenches formed in the semiconductor substrate between neighboring ones of the stripe-shaped gates; an insulating layer on the semiconductor substrate; and a plurality of contacts extending through the insulating layer and contacting field plates in the needle-shaped field plate trenches, wherein the contacts have a width that is less than or equal to a width of the needle-shaped field plate trenches, as measured in a first lateral direction which is transverse to a lengthwise extension of the stripe-shaped gates, wherein in the first lateral direction, the contacts are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches.

According to another embodiment of a semiconductor device, the semiconductor device comprises: a semiconductor substrate; a plurality of stripe-shaped gates formed in the semiconductor substrate, each stripe-shaped gate comprising a gate electrode separated from the semiconductor substrate by a gate dielectric; a plurality of needle-shaped field plate trenches formed in the semiconductor substrate between neighboring ones of the stripe-shaped gates, each needle-shaped field plate trench comprising a field plate separated from the semiconductor substrate by an insulator; source regions of a first conductivity type adjoining body contact regions of a second conductivity type in the semiconductor substrate between neighboring ones of the stripe-shaped gates; an insulating layer on the semiconductor substrate; and a plurality of contacts extending through the insulating layer and contacting the field plates in the needle-shaped field plate trenches, the source regions, and the body contact regions, wherein the contacts have a width that is less than or equal to a width of the needle-shaped field plate trenches, as measured in a first lateral direction which is transverse to a lengthwise extension of the stripe-shaped gates, wherein in the first lateral direction, the contacts are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches such that a cell pitch of the semiconductor device is independent of the contacts.

According to an embodiment of a method of producing a semiconductor device, the method comprises: forming a plurality of needle-shaped field plate trenches in a semiconductor substrate, each needle-shaped field plate trench comprising a field plate separated from the semiconductor substrate by an insulator; forming a plurality of stripe-shaped gates in the semiconductor substrate, each stripe-shaped gate comprising a gate electrode separated from the semiconductor substrate by a gate dielectric, the needle-shaped field plate trenches being disposed between neighboring ones of the stripe-shaped gates; forming source regions of a first conductivity type adjoining body contact regions of a second conductivity type in the semiconductor substrate between neighboring ones of the stripe-shaped gates; forming an insulating layer on the semiconductor substrate; and forming a plurality of contacts that extend through the insulating layer and contact the field plates in the needle-shaped field plate trenches, the source regions, and the body contact regions, wherein the contacts have a width that is less than or equal to a width of the needle-shaped field plate trenches, as measured in a first lateral direction which is transverse to a lengthwise extension of the stripe-shaped gates, wherein in the first lateral direction, the contacts are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches such cell pitch of the semiconductor device is independent of the contacts.

DETAILED DESCRIPTION

The embodiments described provide a semiconductor device having needle-shaped field plates that provide charge compensation and which are in-line with the device body contacts, and corresponding methods of producing the semiconductor device. The body contacts have a width that is less than or equal to a width of the trenches that include the needle-shaped field plates. Also, the body contacts are spaced apart from stripe-shaped gates of the semiconductor device by the same or greater distance than the needle-shaped field plate trenches. Such a configuration allows for a single set of alignment and critical dimension (CD) tolerances between the gate and field plate to be accommodated within the cell pitch where the term ‘cell pitch’ as used herein means the distance across the contact and stripe gates (e.g., W_g+2Sp_fp+W_fp in the figures). Providing the maximum dimension, with alignment tolerance, of the body contact is less than the dimension of the field plate needle, such that the contact alignment and CD variation does not require an additional increase in the cell pitch, thus yielding reduced cell pitch where the term ‘cell pitch’ as used herein means the distance between repeated transistor cells of the semiconductor device. The stripe-shaped gates may be trench or planar gates, as described in more detail later.

Described next with reference to the figures are embodiments of the semiconductor device and corresponding methods of production.

FIG. 1Aillustrates a partial top plan view of a trench gate semiconductor device100having a body contact configuration that allows for a reduced cell pitch which in turn yields reduced RDSON.FIG. 1Billustrates a cross-sectional view of the trench gate semiconductor device100along the line labeled A-A′ inFIG. 1A.FIG. 1Cillustrates a cross-sectional view of the trench gate semiconductor device100along the line labeled B-B′ inFIG. 1A.

The semiconductor device100may be a low voltage MOSFET device below 40V. The semiconductor device100instead may be a medium voltage MOSFET, e.g., at 40V and above. Other device types may utilize the body contact teachings described herein, such as but not limited to IGBTs (insulated gate bipolar transistors), HEMTs (high-electron mobility transistors), etc.

The semiconductor device100includes a semiconductor substrate102. The semiconductor substrate102may include one or more of a variety of semiconductor materials that are used to form semiconductor devices such as power MOSFETs, IGBTs, HEMTs, etc. For example, the semiconductor substrate102may include silicon (Si), silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), and the like. The semiconductor substrate102may be a bulk semiconductor material or may include one or more epitaxial layers grown on a bulk semiconductor material. In one embodiment, the semiconductor device100is a depletion mode transistor device with aggressive feature size reductions.

The semiconductor device100further includes stripe-shaped gate trenches104formed in the semiconductor substrate102and needle-shaped field plate trenches106formed in the semiconductor substrate102between neighboring ones of the stripe-shaped gate trenches104. The term ‘needle-shaped’ as used herein means a trench structure that is narrow and long in a depth-wise direction (z direction inFIGS. 1B and 1C) of the semiconductor substrate102. For example, the needle-shaped field plate trenches106may resemble a needle, column or spicule in the depth-wise direction of the semiconductor substrate102. The term ‘stripe-shaped’ as used herein means a structure having a longest linear dimension in a direction (y direction inFIG. 1A) transverse to the depth-wise direction of the semiconductor substrate102.

In one embodiment, the needle-shaped field plate trenches106are arranged in an orthogonal array in that from a top plan view, the needle-shaped field plate trenches106lie at right angles with respect to one another, e.g., as shown inFIG. 1A. However, the needle-shaped field plate trenches106may be arranged in other (non-orthogonal) configurations.

A field plate108is disposed in each needle-shaped field plate trench106and separated from the surrounding semiconductor substrate102by an insulator110such as a field dielectric, an air gap, a vacuum gap, etc. In a similar manner, a gate electrode112is disposed in each stripe-shaped gate trench104and separated from the surrounding semiconductor substrate102by a gate dielectric114.

The needle-shaped field plate trenches106may extend deeper into the semiconductor substrate102than the stripe-shaped gate trenches104, e.g., as shown inFIG. 1B. The field plates108and the gate electrodes112may be made from any suitable electrically conductive material such as but not limited to polysilicon, metal, metal alloy, etc. The field plates108and the gate electrodes112may comprise the same or different electrically conductive material. In the case of a solid material as the insulator110, the insulator110and the gate dielectric114may comprise the same or different electrically insulative material, e.g., SiOx and may be formed by one or more common processes such as but not limited to thermal oxidation and/or deposition.

An insulating layer116is formed on the semiconductor substrate102. The insulating layer116is not shown inFIG. 1Ato provide an unobstructed view of the underlying structures. In one embodiment, the insulating layer116is an interlayer dielectric (ILD) such as but not limited to SiOx, SiN, etc. The insulating layer116may include one or more sublayers, e.g., a stack of one or more layers of SiOx and one or more layers of SiN.

The semiconductor device100further includes body contacts118extending through the insulating layer116. The locations of the body contacts118are defined by openings119in the insulating layer116. The body contacts118are in contact with the field plates108in the needle-shaped field plate trenches106. The body contacts118are in-line with the field plate trenches106and shown as dashed rectangles inFIG. 1Ato provide an unobstructed view of the underlying structure. The body contacts118may be made from any suitable electrically conductive material such as but not limited to polysilicon, metal, metal alloys, metal compounds such as titanium silicide and titanium nitride, etc.

The body contacts118have a width ‘W_c’ that is less than or equal to a width ‘W_fp’ of the needle-shaped field plate trenches106, as measured in a first lateral direction (x direction inFIGS. 1A through 1C) which is transverse to a lengthwise extension (y direction inFIG. 1A) of the stripe-shaped gate trenches104. According to the example shown inFIGS. 1A and 1B, W_c<W_fp. For example, W_c may be in a range of 100 to 300 nm and W_fp may be in a range of 200 to 400 nm.

In the first lateral direction (x direction inFIGS. 1A through 1C), the body contacts118are also spaced apart from the stripe-shaped gate trenches104by a same or greater distance (Sp_c ≥Sp_fp) than the needle-shaped field plate trenches106. Accordingly, the cell pitch of the semiconductor device100is not influenced by Sp_c. As a result, cell pitch is defined by the gate width (W_g), the field plate width W_fp, and the field plate-to-gate spacing Sp_fp. According to the example shown inFIGS. 1A and 1B, Sp_c >Sp_fp. For example, Sp_fp may be in a range of 20 to 50 nm and Sp_c may be about 80 nm.

As shown inFIG. 1A, the body contacts may be stripe-shaped. According to this embodiment, the field plates108in the needle-shaped field plate trenches106disposed between neighboring stripe-shaped gate trenches104are contacted by the same body contact118. For example, inFIG. 1A, the 3 leftmost field plates108are contacted by the leftmost body contact118, the 3 middle field plates108are contacted by the middle body contact118, and the 3 rightmost field plates108are contacted by the rightmost body contact118.

The semiconductor transistor device100may also include a gate interconnect structure (not shown) that interconnects the individual gate electrodes112in the stripe-shaped gate trenches104. For example, the gate interconnect structure may include electrically conductive lines separated from the semiconductor substrate102by the insulating layer116and conductive vias extending through the insulating layer116for connecting the overlying electrically conductive lines to the gate electrodes in the underlying stripe-shaped gate trenches104. The electrically conductive lines and the conductive vias of the gate interconnect structure may be formed within the insulating layer116, allowing for scaling down to lower voltage nodes.

The semiconductor transistor device100may further include a field plate interconnect structure electrically isolated from the gate interconnect structure and which includes the body contacts118. The field plate interconnect structure and the gate interconnect structure may be at different electric potentials. For example, the field plate interconnect structure may be at source potential and the gate interconnect structure may be at gate potential.

In the case of a transistor device, the body contacts118may also contact both source regions120of a first conductivity type and adjoining body contact regions124of a second conductivity type formed in the semiconductor substrate102between neighboring ones of the stripe-shaped gate trenches104. The body contact regions124have a higher average doping concentration than body regions122of the second conductivity type. The body contact regions124provide an ohmic connection between the body regions122and an overlying metallization layer126, via the body contacts118. In the embodiments described herein, the first conductivity is n-type and the second conductivity type is p-type for an n-channel device whereas the first conductivity is p-type and the second conductivity type is n-type for a p-channel device.

In the first lateral direction (x direction inFIGS. 1A through 1C), the body contact regions124may be spaced apart from the stripe-shaped gate trenches104by a same or greater distance (Sp_bc ≥Sp_fp) than the needle-shaped field plate trenches106. According to the example shown inFIGS. 1A through 1C, Sp_bc>Sp_fp. For example, Sp_bc may be about 60 nm.

The body contact regions124may be implanted through the openings119in the insulating layer116that define the location of the body contacts118. The body contact regions124may be buried below the front main surface101of the semiconductor substrate102, e.g., as shown inFIG. 1C.

The body contacts118to the source regions120and body contact regions124do not add to cell pitch, since the body contacts118have the same or smaller width (W_c≤W_fp) than the needle-shaped field plate trenches106. Accordingly, cell pitch is defined by the spacing Sp_fp between the stripe-shaped gate trenches104and the needle-shaped field plate trenches106.

According to the embodiment illustrated inFIGS. 1A through 1C, the semiconductor device100is a vertical transistor device in that the primary current flow path for the device100is between the two main opposing surfaces101,103of the semiconductor substrate102. Accordingly, source and drain terminals S, D are disposed at opposite sides of the semiconductor substrate102. In the case of a vertical device, transistor channel regions form in the body regions122along the stripe-shape gate trenches104in the vertical direction (z direction inFIGS. 1Band1C) when a suitable voltage is applied to the gate electrodes112, as indicated by the dashed downward facing arrows inFIGS. 1B and 1C.

FIG. 2illustrates a partial top plan view of a trench gate semiconductor device200having a contact configuration that allows for a reduced cell pitch, according to another embodiment. The embodiment shown inFIG. 2is similar to the embodiment shown inFIGS. 1A. Different, however, each of the field plates108in the needle-shaped field plate trenches106is contacted by a different one of the body contacts118. That is, instead of the same body contact118being in contact with each field plate108interposed between a pair of neighboring stripe-shaped gate trenches104as shown inFIG. 1A, each field plate108is instead contacted by a separate body contact118as shown inFIG. 2. According to this embodiment, more than one body contact118is provided between each neighboring pair of stripe-shaped gate trenches104. The body contacts118are square shaped inFIG. 2but may have another shape such as but not limited to circular, hexagonal, rectangular, etc.

FIGS. 3A and 3Billustrate respective partial cross-sectional views of a trench gate semiconductor device300having a contact configuration that allows for a reduced cell pitch, according to another embodiment. The cross-sectional view inFIG. 3Acorresponds to the line labelled A-A′ inFIG. 1AorFIG. 2. The cross-sectional view inFIG. 3Bcorresponds to the line labelled B-B′ inFIG. 1AorFIG. 2. Accordingly, the semiconductor device300illustrated inFIGS. 3A and 3Bmay have a single body contact118between each neighboring pair of stripe-shaped gate trenches104as shown inFIG. 1Aor more than one body contact118between each neighboring pair of stripe-shaped gate trenches104as shown inFIG. 2.

According to the embodiment illustrated inFIGS. 3A and 3B, the stripe-shaped gate trenches104may also include both a gate electrode112separated from the semiconductor substrate102by a gate dielectric114and a shielding electrode302below and insulated from the gate electrode114by a field dielectric304. The shielding electrodes302shield the gate electrodes112from drain (D) potential. The field dielectric304and the gate dielectric114may comprise the same or different electrically insulative material, e.g., SiOx and may be formed by one or more common processes such as but not limited to thermal oxidation and/or deposition.

FIGS. 4A and 4Billustrate respective partial cross-sectional views of a trench gate semiconductor device400having a contact configuration that allows for a reduced cell pitch, according to another embodiment. The cross-sectional view inFIG. 4Amay correspond to the line labelled A-A′ inFIG. 1AorFIG. 2. The cross-sectional view inFIG. 3Bmay correspond to the line labelled B-B′ inFIG. 1AorFIG. 2. Accordingly, the semiconductor device400illustrated inFIGS. 4A and 4Bmay have a single body contact118between each neighboring pair of stripe-shaped gate trenches104as shown inFIG. 1Aor more than one body contact118between each neighboring pair of stripe-shaped gate trenches104as shown inFIG. 2.

According to the embodiment illustrated inFIGS. 4A and 4B, the needle-shaped field plate trenches106are bottle-shaped with a narrower upper part402and a wider lower part404. The insulator110in the needle-shaped field plate trenches106and that separates the field plates108from the semiconductor substrate102may be narrower/thinner (T1) in the narrower upper part402of the needle-shaped field plate trenches106and wider/thicker (T2) in the wider lower part404of the needle-shaped field plate trenches106. The stripe-shaped gate trenches104may be placed closer to the needle-shaped field plate trenches106by narrowing/thinning the insulator110in the upper part402of the needle-shaped field plate trenches106as shown inFIG. 3A, further reducing cell pitch.

The device embodiment shown inFIGS. 4A and 4Bmay be combined with the device embodiments shown inFIGS. 3A and 3B. That is, the semiconductor device400shown inFIGS. 4A and 4Bmay include both a gate electrode112and a shielding electrode302in the stripe-shaped gate trenches104.

Heretofore, semiconductor device embodiments have been described in the context of trench gates, i.e., gates formed in trenches etched into a semiconductor substrate. However, the embodiments illustrated inFIGS. 1A through 4Bmay be adapted to planar gate devices by replacing the trench gate structures with planar gate structures. With a planar gate structure, the device gates are formed on the front main surface of a semiconductor substrate instead of in trenches etched into the substrate. Exemplary embodiments of planar gate devices are described next in more detail with reference toFIGS. 5A through 7.

FIG. 5Aillustrates a partial top plan view of a planar gate semiconductor device500having a body contact configuration that allows for a reduced cell pitch which in turn yields reduced RDSON.FIG. 5Billustrates a cross-sectional view of the planar gate semiconductor device500along the line labeled A-A′ inFIG. 5A.FIG. 5Cillustrates a cross-sectional view of the planar gate semiconductor device500along the line labeled B-B′ inFIG. 5A.

The embodiment shown inFIGS. 5A through 5Cis similar to the embodiment illustrated inFIGS. 1A through 1C. Different, however, the semiconductor device500shown inFIGS. 5A through 5Chas stripe-shaped planar gates502instead of stripe-shaped trench gates104. The stripe-shaped planar gates502each include a stripe-shaped gate electrode112separated from the front main surface101of the semiconductor substrate102by a gate dielectric114, as shown inFIGS. 5B and 5C. The dashed lines inFIGS. 5B and 5Cindicate the current path which has a horizontal component along the gate dielectric114and a vertical component in the drift zone504of the device500.

The gate width W_g may be different for the planar gate arrangement compared to the trench gate arrangement. Advantageously, the body proximity to the planar gates502is less likely to affect the threshold voltage (Vt) of the device500but more likely to pinch off the vertical conduction channel. Hence, Sp_bc may be more critical for a trench gate arrangement because Sp_bc can influence the channel more strongly than in a planar gate arrangement. Accordingly, Sp_c may be smaller for a planar gate arrangement because Sp_bc could be smaller. In general, one or more of the parameter ranges described above for W_g, Sp_fp, W_fp, Sp_c, and Sp_bc may be adjusted accordingly depending on whether a planar gate arrangement or a trench gate arrangement is implemented.

The needle-shaped field plate trenches106for the planar gate device500may be fabricated as shown inFIG. 5Bor instead may have a bottle shape (narrower upper part402and wider lower part404) as shown inFIG. 4A. The planar gate arrangement yields a direct current path down the centre of the semiconductor mesas as indicated by the vertical component of the dashed lines inFIG. 5B and 5C. Such a directed current path allows for a wider field plate implementation since the conduction path does not have to curve around the wider portion of the field plates108. Accordingly, the bottle-shaped field plate implementation shown inFIG. 4Amay be used instead of the field-plate configuration shown inFIG. 5B. Separately or in combination, the planar gate semiconductor device500may have a single body contact118between each neighboring pair of stripe-shaped planar gates502as shown inFIG. 5Aor more than one body contact118between each neighboring pair of stripe-shaped planar gates502as shown inFIG. 2.

FIG. 6illustrates a partial cross-sectional view of a planar gate502. According to this embodiment, the planar gate502has a split-gate configuration. That is, the stripe-shaped gate electrode112is divided into two separate sections112′,112″ separated from one another by an insulating spacer600such as an oxide, nitride, etc. The insulating spacer600may also cover the sidewalls of the gate electrode sections112′,112″.

FIG. 7illustrates a partial cross-sectional view of a planar gate502, according to another embodiment. Silicide700is formed on the upper part of each exposed semiconductor region, including the part of the source regions120unprotected by the spacer600and the top side of the stripe-shaped gate electrode112in the case polysilicon is used for the gate electrode material.

The semiconductor devices100,200,300,400,500described herein may be produced by: forming stripe-shaped planar or trench gates104/502and needle-shaped field plate trenches106in a semiconductor substrate102; forming source regions120, body regions122and adjoining body contact regions124in the semiconductor substrate102between neighboring ones of the stripe-shaped gates104/502; forming an insulating layer116on the semiconductor substrate102; forming body contacts118that extend through the insulating layer116and contact field plates108in the needle-shaped field plate trenches106, the source regions120, and the body contact regions124; and forming a metallization layer126on the insulating layer116and in electrical connection with the body contacts118.

In one embodiment, one or more epitaxial layers are grown on a base semiconductor material to form the semiconductor substrate102. The needle-shaped field plate trenches106are then formed in the semiconductor substrate102, followed by the stripe-shaped gates104/502. The body regions122and the source regions120are then formed in the semiconductor substrate102between neighboring ones of the stripe-shaped gates104/502, e.g., by implantation of dopants of the opposite conductivity type and subsequent annealing. The insulating layer116is then formed on the semiconductor substrate102and openings119are formed in the insulating layer116. The openings119define the location of the body contacts118.

Dopants of the second conductivity type are implanted into the semiconductor substrate102through the openings119in the insulating layer116and subsequently annealed to form the body contact regions124. The openings119in the insulating layer116are then filled with an electrically conductive material to form the body contacts118. The metallization layer126is then deposited on the insulating layer116and in contact with the body contacts118. The metallization layer126may comprise any suitable metal or metal alloy such as but not limited to Al, Cu, AlCu, etc. In another embodiment, the stripe-shaped gates104/502are formed before the needle-shaped field plate trenches106. Still other processing sequences may be employed to form the semiconductor devices100,200,300,400,500described herein.

In each case, the body contacts118have a width W_c that is less than or equal to the width W_fp of the needle-shaped field plate trenches106, as measured in a first lateral direction (x direction inFIGS. 1A through 5C) which is transverse to a lengthwise extension (y direction inFIGS. 1A, 2 and 5A) of the stripe-shaped gate trenches104. In the first lateral direction, the body contacts118are also spaced apart from the stripe-shaped gates104/502by a same or greater distance (Sp_c≥Sp_fp) than the needle-shaped field plate trenches106.

Since the body contacts118have a width W_c that is less than or equal to the width W_fp of the needle-shaped field plate trenches106, the body contact implants do not overlap the edge of the needle-shaped field plate trenches106. Accordingly, cell pitch control is reduced to one alignment tolerance. That is, the body contacts118reside within the footprint of the needle-shaped field plate trenches106and the body contact implants occur through openings119in the insulating layer116that define the body contact locations.

A semiconductor device, comprising: a plurality of stripe-shaped gates formed in a semiconductor substrate; a plurality of needle-shaped field plate trenches formed in the semiconductor substrate between neighboring ones of the stripe-shaped gates; an insulating layer on the semiconductor substrate; and a plurality of contacts extending through the insulating layer and contacting field plates in the needle-shaped field plate trenches, wherein the contacts have a width that is less than or equal to a width of the needle-shaped field plate trenches, as measured in a first lateral direction which is transverse to a lengthwise extension of the stripe-shaped gates, wherein in the first lateral direction, the contacts are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches.

The semiconductor device of example 1, wherein the contacts also contact both source regions of a first conductivity type and body contact regions of a second conductivity type formed in the semiconductor substrate between neighboring ones of the stripe-shaped gates.

The semiconductor device of example 2, wherein in the first lateral direction, the body contact regions are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches.

The semiconductor device of any of examples 1 through 3, wherein the contacts are stripe-shaped, and wherein the field plates in the needle-shaped field plate trenches disposed between neighboring stripe-shaped gates are contacted by the same stripe-shaped contact.

The semiconductor device of any of examples 1 through 4, wherein each of the field plates in the needle-shaped field plate trenches is contacted by a different one of the contacts.

The semiconductor device of any of examples 1 through 5, wherein the stripe-shaped gates each comprise a gate electrode separated from the semiconductor substrate by a gate dielectric in a trench and a shielding electrode below and insulated from the gate electrode in the trench.

The semiconductor device of any of examples 1 through 6, wherein the needle-shaped field plate trenches are bottle-shaped with a narrower upper part and a wider lower part.

The semiconductor device of example 7, wherein an insulator in the needle-shaped field plate trenches and that separates the field plates from the semiconductor substrate is thinner in the narrower upper part of the needle-shaped field plate trenches and thicker in the wider lower part of the needle-shaped field plate trenches.

The semiconductor device of any of examples 1 through 8, wherein the width of the contacts is less than the width of the needle-shaped field plate trenches as measured in the first lateral direction.

The semiconductor device of any of examples 1 through 5 and 7 through 9, wherein the stripe-shaped gates are planar gates each comprising a gate electrode separated from a first main surface of the semiconductor substrate by a gate dielectric.

The semiconductor device of example 10, wherein the planar gates have a split-gate configuration with each gate electrode divided into two separate sections separated from one another by an insulating spacer.

EXAMPLE 12. The semiconductor device of example 10 or 11, wherein the gate electrodes comprise polysilicon and silicide is formed on a top side of the gate electrodes.

A semiconductor device, comprising: a semiconductor substrate; a plurality of stripe-shaped gates formed in the semiconductor substrate, each stripe-shaped gate comprising a gate electrode separated from the semiconductor substrate by a gate dielectric; a plurality of needle-shaped field plate trenches formed in the semiconductor substrate between neighboring ones of the stripe-shaped gates, each needle-shaped field plate trench comprising a field plate separated from the semiconductor substrate by an insulator; source regions of a first conductivity type adjoining body contact regions of a second conductivity type in the semiconductor substrate between neighboring ones of the stripe-shaped gates; an insulating layer on the semiconductor substrate; and a plurality of contacts extending through the insulating layer and contacting the field plates in the needle-shaped field plate trenches, the source regions, and the body contact regions, wherein the contacts have a width that is less than or equal to a width the needle-shaped field plate trenches, as measured in a first lateral direction which is transverse to a lengthwise extension of the stripe-shaped gates, wherein in the first lateral direction, the contacts are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches such that a cell pitch of the semiconductor device is independent of the contacts.

The semiconductor device of example 13, wherein in the first lateral direction, the body contact regions are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches.

The semiconductor device of example 13 or 14, wherein the contacts are stripe-shaped, and wherein both the field plates in the needle-shaped field plate trenches and the body contact regions disposed between neighboring stripe-shaped gates are contacted by the same stripe-shaped contact.

The semiconductor device of any of examples 13 through 15, wherein each of the field plates in the needle-shaped field plate trenches is contacted by a different one of the contacts, and wherein each of the body contact regions is contacted by a different one of the contacts.

The semiconductor device of any of examples 13 through 16, wherein each of the stripe-shaped gates is a trench gate that further comprise a shielding electrode below and insulated from the corresponding gate electrode in a trench.

The semiconductor device of any of examples 13 through 17, wherein the needle-shaped field plate trenches are bottle-shaped with a narrower upper part and a wider lower part.

The semiconductor device of example 18, wherein the insulator is thinner in the narrower upper part of the needle-shaped field plate trenches and thicker in the wider lower part of the needle-shaped field plate trenches.

The semiconductor device of any of examples 13 through 19, wherein the width of the contacts is less than the width of the needle-shaped field plate trenches as measured in the first lateral direction.

The semiconductor device of any of examples 13 through 16 and 18 through 20, wherein each of the stripe-shaped gates is a planar gate with the gate electrode separated from a first main surface of the semiconductor substrate by the gate dielectric.

A method of producing a semiconductor device, the method comprising: forming a plurality of needle-shaped field plate trenches in a semiconductor substrate, each needle-shaped field plate trench comprising a field plate separated from the semiconductor substrate by an insulator; forming a plurality of stripe-shaped gates in the semiconductor substrate, each stripe-shaped gate comprising a gate electrode separated from the semiconductor substrate by a gate dielectric, the needle-shaped field plate trenches being disposed between neighboring ones of the stripe-shaped gates; forming source regions of a first conductivity type adjoining body contact regions of a second conductivity type in the semiconductor substrate between neighboring ones of the stripe-shaped gates; forming an insulating layer on the semiconductor substrate; and forming a plurality of contacts that extend through the insulating layer and contact the field plates in the needle-shaped field plate trenches, the source regions, and the body contact regions, wherein the contacts have a width that is less than or equal to a width of the needle-shaped field plate trenches, as measured in a first lateral direction which is transverse to a lengthwise extension of the stripe-shaped gates, wherein in the first lateral direction, the contacts are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches such cell pitch of the semiconductor device is independent of the contacts.

The method of example 21, wherein in the first lateral direction, the body contact regions are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches.

The method of example 22 or 23, wherein the contacts are stripe-shaped, and wherein both the field plates in the needle-shaped field plate trenches and the body contact regions disposed between neighboring stripe-shaped gates are contacted by the same stripe-shaped contact.

The method of any of examples 22 through 24, wherein each of the field plates in the needle-shaped field plate trenches is contacted by a different one of the contacts, and wherein each of the body contact regions is contacted by a different one of the contacts.

The method of any of examples 22 through 25, wherein the needle-shaped field plate trenches are formed as bottle-shaped with a narrower upper part and a wider lower part.

The method of example 26, wherein forming the needle-shaped field plate trenches so as to be bottle-shaped comprises forming the insulator thinner in the narrower upper part of the needle-shaped field plate trenches and thicker in the wider lower part of the needle-shaped field plate trenches.