Method of fabricating a semiconductor device having a plug

A method of fabricating a semiconductor device, the method includes forming gate patterns on a substrate, recessing the substrate between the gate patterns, thereby forming a first resulting structure including recesses, forming a gate spacer layer on an entire surface of the first resulting structure including the gate patterns, etching the gate spacer layer at a bottom of the recess, and forming a plug on the recess, thereby forming a second resulting structure including the plug.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present invention claims priority of Korean patent application number 10-2007-0064497, filed on Jun. 28, 2007, which is incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor fabrication technology and, more particularly, to a method of forming a landing plug contact of a semiconductor device.

As a semiconductor device becomes highly integrated, a space between gate patterns gets narrower so that a substrate portion for a landing plug contact, which is formed between the gate patterns, gets smaller. Since cell contact resistance continuously increases as a contact area decreases, a technology to reduce the cell contact resistance is necessary.

Accordingly, a pre-selective epitaxial growth (SEG) plug process has been used. In the pre-SEG plug process, an SEG plug having a given thickness is formed between the gate patterns before the landing plug contact is formed. After forming a gate spacer at sidewalls of the gate pattern before a formation of a cell spacer, a substrate is exposed by using the gate spacer as an etching barrier layer and the SEG plug is formed on the exposed substrate. Since a contact open area increases as much as a thickness of the cell spacer, the cell contact resistance decreases.

Meanwhile, in order to secure refresh characteristics of the semiconductor device, a technology of a recessed gate structure has been suggested, which is a 3D gate structure formed by recessing a region under the gate pattern to increase a channel length.

However, since there is no isolation layer which electrically insulates the recessed lower portion of the gate pattern from the SEG plug, an electrical short between the recess region and the SEG plug may occur (seeFIG. 1). Such a phenomenon gets worse when an overlay of the gate pattern is done in the opposite direction to that of the recess region by misalignment.

If the thickness of the gate spacer is increased to solve such a limitation, there is a side effect in that a cell contact open area is reduced. Even in this case, there exists no isolation layer between the recess region and the SEG plug, an electrical insulation cannot be secured.

SUMMARY OF THE INVENTION

The present invention is directed to providing a method of fabricating a semiconductor device capable of reducing cell contact resistance.

Also, the present invention is directed to providing a method of fabricating a semiconductor device capable of electrically insulating a recess region of a gate pattern from a selective epitaxial growth (SEG) plug when the SEG plug is applied.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the methods includes forming gate patterns over a substrate; forming a recess in the substrate between the gate patterns, thereby forming a first resulting structure including the recess; forming a gate spacer layer on an entire surface of the first resulting structure including the gate patterns; etching the gate spacer layer at a bottom of the recess; and forming a plug on the recess, thereby forming a second resulting structure including the plug.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method includes forming gate patterns over a substrate having a cell area and a peripheral area; forming a recess in the substrate between the gate patterns in the cell area, thereby forming a first resulting structure; forming a gate spacer layer on an entire surface of the first resulting structure including the recess; forming a mask pattern on the gate spacer layer in the peripheral area; etching the gate spacer layer at a bottom of the recess in the cell area; and forming a plug on the recess.

According to a further aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method includes forming gate patterns over a substrate having a cell area and a peripheral area, thereby forming a first resulting structure; forming a first gate spacer layer on an entire surface of the first resulting structure including the gate patterns; forming a mask pattern on the first gate spacer layer in the peripheral area; etching the first gate spacer layer to expose the substrate between the gate patterns in the cell area; forming a recess in the exposed substrate; removing the mask pattern, thereby forming a second resulting structure; forming a second gate spacer layer on an entire surface of the second resulting structure including the recess; etching the second gate spacer layer at a bottom of the recess in the cell area; and forming a plug on the recess in the cell area, thereby forming a third resulting structure including the plug.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 2A to 2Fillustrate cross-sectional views of a method of fabricating a semiconductor device according to a first embodiment of the present invention.

As shown inFIG. 2A, an isolation layer12is formed on a substrate11. Here, the substrate11can be a semiconductor substrate where a dynamic random access memory (DRAM) process is performed, and the isolation layer12, which is used to define an active region, can be formed by using a shallow trench isolation (STI) process.

The substrate11is selectively etched in a given depth to form a recess region13. Here, the recess region13increases a channel length to improve refresh characteristics. Although the recess region13having a U-shape is illustrated inFIG. 2A, the recess region13can also have any one of a bulb shape, a pin shape or a saddle shape.

A gate pattern15, a portion of which is buried in the recess region13and the remaining portion of which protrudes from an upper portion of the substrate11, is formed. A gate insulation layer14is formed on the substrate11including the recess region13before the gate pattern15is formed. Here, the gate pattern15can have a stacked structure including a first gate electrode15A, a second gate electrode15B and a gate hard mask15C. The first gate electrode15A can be a polysilicon, the second gate electrode15B can be a metal or a metal silicide and the gate hard mask15C can be a nitride layer.

The substrate11between the gate patterns15is etched in a given depth to be recessed. The recessed portion of the substrate11includes a plug region16in which a landing plug contact is to be formed. The plug region16is formed to have a depth which does not affect a junction. The depth of the plug region16can be approximately 50 Å to approximately 500 Å.

As shown inFIG. 2B, a gate spacer layer17is formed on an entire surface of the resulting structure including the plug region16. Here, the gate spacer layer17can be formed to have a thickness ranging from approximately 80 Å to approximately 150 Å, considering thickness loss caused by a subsequent spacer etching process and post-etch treatment. In this case, the gate spacer layer17having a thickness ranging from approximately 30 Å to approximately 50 Å remains on sidewalls of the gate patterns15after the subsequent spacer etching process and post-etch treatment are performed. Thus, a sufficient electrical insulation between a selective epitaxial growth (SEG) plug and the recess region13is possible.

As shown inFIG. 2C, the gate spacer layer17is etched to expose the substrate11at the bottom of the plug region16. The gate spacer layer17may be etched by an etch-back process, leaving the gate spacer layer17on the sidewalls of the gate pattern15. Hereinafter, the gate spacer layer17remaining on the sidewalls of the gate pattern15will be referred as a gate spacer17A. Even in case that misalignment between the gate pattern15and the recess region13occurs, the electrical insulation between the recess region13and the subsequent SEG plug is secured because the gate spacer17A remains at sidewalls of the plug region16.

As shown inFIG. 2D, a first plug18is formed on the plug region16. The first plug18can be an SEG plug formed through a selective epitaxial growth process. Further, the first plug18can be formed to have a thickness ranging from approximately 200 A to approximately 300 A. Also, a post-etch treatment (cleaning) can be performed before the first plug18is formed.

Since the first plug18is formed before formation of a subsequent cell spacer, a substrate contact area can be increased as much as the thickness of the cell spacer, thereby reducing cell contact resistance. Also, a gap-fill margin can be secured as much as a height of the first plug18when a subsequent insulation layer is formed.

As shown inFIG. 2E, a cell spacer layer19is formed on the entire surface of the resulting structure including the first plug18. Here, the cell spacer layer19is used to prevent the penetration of impurities into the substrate11and the first plug18from a subsequent insulation layer. The cell spacer layer19can be formed out of a nitride layer.

Then, an insulation layer20is formed to fill all spaces between the gate patterns15on the cell spacer layer19. Here, the insulation layer20is used for the insulation between the gate patterns15. The insulation layer20can be formed out of a boron phosphorus silicate glass (BPSG) having an excellent gap-fill margin. Subsequently, the insulation layer20is planarized until the cell spacer layer19is exposed.

As shown inFIG. 2F, a contact hole is formed to expose the first plug18between the gate patterns15and then a conductive layer is formed and planarized to form a second plug21.

In detail, a mask pattern is formed on the insulation layer20to define a region in which a landing plug contact is to be formed between the gate patterns15and the contact hole is formed to expose the first plug18using a self-aligned contact etching process. Through the self-aligned contact etching process, the cell spacer layer19remains at sidewalls of the gate pattern15. Hereinafter, the cell spacer layer19remaining at the sidewalls of the gate patterns15after the self-aligned contact etching process will be referred to as a cell spacer pattern19A. Then, the conductive layer is formed on the first plug18to fill in the space between the gate patterns15and is planarized until the gate hard mask15C is exposed so as to form the second plug21. Here, the conductive layer can be a polysilicon and the planarization is carried out by an etch-back process or a chemical-mechanical polishing (CMP). The first and second plugs18and21include a landing plug contact.

FIGS. 3A to 3Fillustrate cross-sectional views of a method of fabricating a semiconductor device according to a second embodiment of the present invention.

As shown inFIG. 3A, an isolation layer32is formed on a substrate31. Here, the substrate31can be a semiconductor substrate where a DRAM process is performed, and the isolation layer32, which is used to define an active region, can be formed by using a shallow trench isolation (STI) process.

The substrate31is selectively etched in a given depth to form a recess region33. Here, the recess region33increases a channel length to improve refresh characteristics. Although the recess region33having a U-shape is illustrated inFIG. 3A, the recess region13can also have any one of a bulb shape, a pin shape or a saddle shape.

Then, a gate pattern35, a portion of which is buried in the recess region33and the remaining portion of which protrudes from an upper portion of the substrate31, is formed. A gate insulation layer34can be formed on the substrate31including the recess region33before the gate pattern35is formed. The gate pattern35can have a stacked structure including a first gate electrode35A, a second gate electrode35B and a gate hard mask35C. The first gate electrode35A can be a polysilicon, the second gate electrode35B can be a metal or a metal silicide and the gate hard mask35C can be a nitride layer.

Then, the substrate31between the gate patterns35is etched in a given depth to be recessed. The recessed portion of the substrate31comprises a plug region36in which a landing plug contact is to be formed. The plug region36is formed to have a depth which does not affect a junction. The depth of the plug region36can be approximately 50 A to approximately 500 A.

As shown inFIG. 3B, a gate spacer layer37is formed on the entire surface of the resulting structure including the plug region36. Here, the gate spacer layer37can be formed to have a thickness ranging from approximately 80 A to approximately 150 A, considering thickness loss caused by a subsequent spacer etching process and post-etch treatment. In this case, the gate spacer layer37having a thickness ranging from approximately 30 A to approximately 50 A remains on sidewalls of the gate patterns35after the subsequent spacer etching process and post-etch treatment are performed. Thus, a sufficient electrical insulation between a subsequent selective epitaxial growth (SEG) plug and the recess region33is possible.

Subsequently, an etching barrier layer38is formed on the gate spacer layer37. Here, the etching barrier layer38formed on the upper portion of the gate pattern35is thicker than that formed at the sidewalls of the gate pattern35. The etching barrier layer38can be formed to have a thickness on the upper portion of the gate pattern35ranging from approximately 300 A to approximately 800 A. The etching barrier layer38can be formed of plasma enhanced undoped silicate glass (PE-USG).

As shown inFIG. 3C, the gate spacer layer37is etched to expose the substrate31at the bottom of the plug region36. Although a portion of the etching barrier layer38can be lost during the process of etching the gate spacer layer37, a given thickness of the etching barrier layer38remains on the upper portion and the sidewalls of the gate pattern35so that the loss of the gate spacer layer37is prevented and only the substrate31at the bottom of the plug region36is selectively exposed. Also, in case that the gate spacer layer37is damaged so as to expose the gate hard mask35C, the etching barrier layer38prevents the gate hard mask35C from loss by an excessive etching.

Particularly, even in case that misalignment between the gate pattern35and the recess region33occurs, only the substrate31at the bottom of the plug region36is selectively exposed and a gate spacer37A remains at sidewalls of the plug region36. Thus, the electrical insulation between the recess region33and the SEG plug is secured.

As shown inFIG. 3D, a first plug39is formed on the plug region36. The first plug39can be an SEG plug formed through a selective epitaxial growth process, and it can be formed to have a thickness ranging from approximately 200 A to approximately 300 A. Also, a post-etch treatment (cleaning) can be performed before the first plug39is formed. Further, the etching barrier layer38can be either entirely removed by the post-etch treatment or left intact since it is an insulation layer and it does not affect the subsequent processes.

Since the first plug39is formed before formation of a subsequent cell spacer, a substrate contact area can be increased as much as the thickness of the cell spacer, thereby reducing cell contact resistance. Also, a gap-fill margin can be secured as much as a height of the first plug39when a subsequent insulation layer is formed.

As shown inFIG. 3E, a cell spacer layer40is formed on the entire surface of the resulting structure including the first plug39. Here, the cell spacer layer40is used to prevent the penetration of impurities into the substrate31and the first plug39from a subsequent insulation layer. The cell spacer layer40can be formed out of a nitride layer.

Then, the insulation layer41is formed to fill all spaces between the gate patterns35on the cell spacer layer40. Here, the insulation layer41is used for the insulation between the gate patterns35. The insulation layer41can be formed out of a boron phosphorus silicate glass (BPSG) having an excellent gap-fill margin. Subsequently, the insulation layer41is planarized until the cell spacer layer40is exposed.

As shown inFIG. 3F, a contact hole is formed to expose the first plug39between the gate patterns35and then a conductive layer is formed and planarized to form a second plug42.

In detail, a mask pattern is formed on the insulation layer41to define a region where a landing plug contact is to be formed between the gate patterns35and the contact hole is formed to expose the first plug39using a self-aligned contact etching process. Through the self-aligned contact etching process, the cell spacer layer40remains at sidewalls of the gate pattern35. Hereinafter, the remained cell spacer layer40remaining at the sidewalls of the gate pattern35after the self-aligned contact etching process will be referred to as a cell spacer pattern40A. Then, the conductive layer is formed on the first plug39to fill in the space between the gate patterns35and is planarized until the gate hard mask35C is exposed so as to form the second plug42. Here, the conductive layer can be a polysilicon and the planarization can be carried out by an etch-back process or a chemical-mechanical polishing (CMP). The first and second plugs39and42include a landing plug contact.

FIGS. 4A to 4Fillustrate cross-sectional views of a method of fabricating a semiconductor device according to a third embodiment of the present invention.

As shown inFIG. 4A, an isolation layer52is formed on a cell area of a substrate51having the cell area and a peripheral area. Here, the substrate51can be a semiconductor substrate where a dynamic random access (DRAM) process is performed, and the isolation layer52, which is used to define an active region, can be formed using a shallow trench isolation (STI) process.

The substrate51is selectively etched in a given depth to form a recess region53. Here, the recess region53increases a channel length to improve refresh characteristics. Although the recess region53having a U-shape is illustrated inFIG. 4A, the recess region53can also have any one of a bulb shape, a pin shape or a saddle shape.

Then, a gate pattern55, a portion of which is buried in the recess region53and the remaining portion of which protrudes from an upper portion of the substrate51, is formed. A gate insulation layer54can be formed on the substrate51including the recess region53before the gate pattern55is formed. The gate pattern55can have a stacked structure including a first gate electrode55A, a second gate electrode55B and a gate hard mask55C. The first gate electrode55A can be a polysilicon, the second gate electrode55B can be a metal or a metal silicide and the gate hard mask55C can be a nitride layer.

Then, the substrate51between the gate patterns55in the cell area is etched in a given depth to be recessed. The recessed portion of the substrate51comprises a plug region56in which a landing plug contact is to be formed. The plug region56is formed to have a depth which does not affect a junction. The depth of the plug region56can be approximately 50 A to approximately 500 A. A mask pattern can be formed to cover the peripheral area to selectively recess the space between the gate patterns55only in the cell area. The mask pattern can be removed after the plug region56is formed in the cell area.

As shown inFIG. 4B, a gate spacer layer57is formed on the entire surface in the cell area including the plug region56and the peripheral area. Here, the gate spacer layer57can be formed to have a thickness ranging from approximately 80 A to approximately 150 A, considering thickness loss caused by a subsequent spacer etching process and post-etch treatment. In this case, the gate spacer layer57having a thickness ranging from approximately 30 A to approximately 50 A remains on sidewalls of the gate patterns55after the subsequent spacer etching process and post-etch treatment are performed. Thus, a sufficient electrical insulation between a subsequent selective epitaxial growth (SEG) plug and the recess region53is possible.

Then, a mask pattern58is formed on the gate spacer57in the peripheral area. Here, the mask pattern58is used to protect the peripheral area at the time of etching the gate spacer57. The mask pattern58can be formed out of a photoresist layer.

As shown inFIG. 4C, the gate spacer layer57in the cell area is etched to expose the substrate51at the bottom of the plug region56. The gate spacer layer57is etched by an etch-back process, leaving the gate spacer layer57on the sidewalls of the gate pattern55. Hereinafter, the gate spacer layer57remaining on the sidewalls of the gate pattern55will be referred to as the gate spacer57A. Even in case that misalignment between the gate pattern55and the recess region53occurs, the electrical insulation between the recess region53and the SEG plug is secured because the gate spacer57A remains at sidewalls of the plug region56. Also, the peripheral area is protected by the mask pattern58at the time of etching the gate spacer57.

As shown inFIG. 4D, a first plug59is formed on the plug region56. The first plug59can be an SEG plug formed through a selective epitaxial growth (SEG) process, and it can be formed to have a thickness ranging from approximately 200 A to approximately 300 A. Also, a post-etch treatment (cleaning) can be performed before the first plug59is formed.

Since the first plug59is formed before formation of a subsequent cell spacer, a substrate contact area can be increased as much as the thickness of the cell spacer, thereby reducing cell contact resistance. Also, a gap-fill margin can be secured as much as a height of the first plug59when a subsequent insulation layer is formed.

The mask pattern58is removed before or after the first plug59is formed. If the mask pattern58is formed out of a photoresist layer, it can be removed with an oxygen strip.

As shown inFIG. 4E, a cell spacer layer60is formed on the entire surface of the resulting structure including the first plug59. Here, the cell spacer layer60is used to prevent the penetration of impurities into the substrate51and the first plug59from a subsequent insulation layer. The cell spacer layer60can be formed out of a nitride layer.

Then, an insulation layer61is formed to fill all spaces between the gate patterns55on the cell spacer layer60. Here, the insulation layer61is used for the insulation between the gate patterns55. The insulation layer61can be formed out of a boron phosphorus silicate glass (BPSG) having an excellent gap-fill margin. Subsequently, the insulation layer61can be planarized until the cell spacer layer60is exposed.

As shown inFIG. 4F, a contact hole is formed to expose the first plug59between the gate patterns55and then a conductive layer is formed and planarized to form a second plug62.

In detail, a mask pattern is formed on the insulation layer61to define a region in which a landing plug contact is to be formed between the gate patterns55and the contact hole is formed to expose the first plug59using a self-aligned contact etching process. Through the self-aligned contact etching process, the cell spacer layer60in active region remains at sidewalls of the gate pattern55. Hereinafter, the cell spacer layer60remaining at the sidewalls of the gate patterns55after the self-aligned contact etching process will be referred to as a cell spacer pattern60A. Then, the conductive layer is formed on the first plug59to fill in a space between the gate patterns55and is planarized until the gate hard mask55C is exposed so as to form the second plug62. Here, the conductive layer can be a polysilicon and the planarization is carried out by an etch-back process or a chemical-mechanical polishing (CMP). The first and second plugs59and62comprise a landing plug contact.

FIGS. 5A to 5Fillustrate cross-sectional views of a method of fabricating a semiconductor device according to a fourth embodiment of the present invention.

As shown inFIG. 5A, an isolation layer72is formed on a cell area of a substrate71having the cell area and a peripheral area. Here, the substrate71can be a semiconductor substrate where a dynamic random access memory (DRAM) process is performed, and the isolation layer72, which is used to define an active region, can be formed using a shallow trench isolation (STI) process.

The substrate71is selectively etched in a given depth to form a recess region73. Here, the recess region73increases a channel length to improve refresh characteristics. Although the recess region73having a U-shape is illustrated inFIG. 5A, the recess region73can also have any one of a bulb shape, a pin shape or a saddle shape.

Then, a gate pattern75, a portion of which is buried in the recess region73and the remaining portion of which protrudes from an upper portion of the substrate71, is formed. A gate insulation layer74can be formed on the substrate71including the recess region73before the gate pattern75is formed. The gate pattern75can have a stacked structure including a first gate electrode75A, a second gate electrode75B and a gate hard mask75C. The first gate electrode75A can be a polysilicon, the second gate electrode75B can be a metal or a metal silicide and the gate hard mask75C can be a nitride layer.

A first gate spacer layer and an oxide layer for a spacer are formed on the entire surface of the resulting structure including the gate pattern75. Then, the first gate spacer layer and the oxide layer for the spacer in the peripheral area are etched to form a sidewall protection layer at sidewalls of the gate pattern75in the peripheral area. The sidewall protection layer in the peripheral area may have a stacked structure including the first gate spacer76A and the oxide layer77. The first gate spacer76A has a thickness ranging from approximately 10 A to approximately 60 A to endure a subsequent wet etching process to remove the oxide layer in the cell area. The first gate spacer76A can be formed out of a nitride layer.

Then, a first mask pattern78is formed in the peripheral area. Here, the first mask pattern78is used to protect the peripheral area at the time of removing the oxide layer formed in the cell area and forming a plug region. The first mask pattern78can be formed out of a photoresist layer.

The oxide layer in the cell area is removed by a wet etching process. At this time, the first gate spacer layer of a nitride layer formed under the oxide layer prevents loss of the substrate71and the gate pattern75in the cell area by the wet etching process.

The first gate spacer layer between the gate patterns75is etched to expose the substrate71. Thus, the first gate spacer only remains at the sidewalls of the gate pattern75. Hereinafter, the first gate spacer layer which remains at the sidewalls of the gate pattern75in the cell area will be referred to as a first gate spacer pattern76B.

Then, the substrate71exposed between the gate patterns75is recessed in a given depth. The recessed portion of the substrate71comprises the plug region79in which a landing plug contact is to be formed. The plug region79is formed to have a depth which does not affect a junction. The depth of the plug region79can be approximately 50 A to approximately 500 A.

As shown inFIG. 5B, the first mask pattern78is removed. If the first mask pattern78is a photoresist layer, it can be removed with an oxygen strip.

Subsequently, a second gate spacer layer80is formed on the entire surface in the cell area including the plug region79and the peripheral area. Here, the second gate spacer layer80can be formed to have a thickness ranging from approximately 80 A to approximately 150 A, considering thickness loss caused by a subsequent spacer etching process and post-etch treatment. In this case, the second gate spacer layer80having a thickness ranging from approximately 30 A to approximately 50 A remains on sidewalls of the gate patterns75after the subsequent spacer etching process and post-etch treatment are performed. Thus, a sufficient electrical insulation between a selective epitaxial growth (SEG) plug and the recess region73is possible. Also, since the total thickness of the first and second gate spacers76B and80is equal to the thickness of the conventional gate spacer, stacking the first and second gate spacers76B and80does not affect or reduce a unit cell area.

Then, an etching barrier layer81is formed on the second gate spacer layer80. Here, the etching barrier layer81formed on the upper portion of the gate pattern75is thicker than that formed at the sidewalls of the gate pattern75in the cell area. The thickness of the etching barrier layer81formed on the upper portion of the gate pattern75can range from approximately 300 A to approximately 800 A. The etching barrier layer81can be formed of a plasma enhanced undoped silicate glass (PE-USG). In the peripheral area, a pattern density is low so that the space between the gate patterns75is wide. Thus, the etching barrier layer81formed on the second gate spacer80in the peripheral area has a uniform thickness.

As shown inFIG. 5C, the second gate spacer layer80in the cell area is etched to expose the substrate71at the bottom of the plug region79. Even in case that misalignment between the gate pattern75and the recess region73occurs, the electrical insulation between the recess region73and the SEG plug is secured because the second gate spacer layer80remains at sidewalls of the plug region79. Although a portion of the etching barrier layer81can be lost during the process of etching the second gate spacer layer80, a given thickness of the etching barrier layer81remains on the upper portion and at the sidewalls of the gate pattern75so that the loss of the second gate spacer layer80is prevented and only the substrate71at the bottom of the plug region79is selectively exposed. Also, in case that the second gate spacer layer80is damaged so that the gate hard mask75C is exposed, the etching barrier layer81prevents the gate hard mask75C from loss by an excessive etching. Hereinafter, the second gate spacer layer80remaining at the sidewalls of the gate patterns75after the second gate spacer etching will be referred to as a second gate spacer pattern80A.

Then, a first plug82is formed on the plug region79. The first plug82can be an SEG plug formed through the SEG process, and it can be formed to have a thickness ranging from approximately 200 A to approximately 300 A. Also, a post-etch treatment (cleaning) can be performed before the first plug82is formed. The etching barrier layer81can be either entirely removed by the post-etch treatment or left intact since it is an insulation layer and it does not affect subsequent processes.

Since the first plug82is formed before formation of a subsequent cell spacer, a substrate contact area can be increased as much as the thickness of the cell spacer, thereby reducing cell contact resistance. Also, a gap-fill margin can be secured as much as a height of the first plug82when a subsequent insulation layer is formed.

As shown inFIG. 5D, a cell spacer layer83is formed on the entire surface of a second resulting structure including the first plug82. Here, the cell spacer layer83is used to prevent the penetration of impurities into the substrate71and the first plug78from a subsequent insulation layer. The cell spacer layer83can be formed out of a nitride layer.

Then, the insulation layer84is formed to fill all spaces between the gate patterns75on the cell spacer layer83. Here, the insulation layer84is used for the insulation between the gate patterns75. The insulation layer84can be formed out of a boron phosphorus silicate glass (BPSG) having an excellent gap-fill margin.

Subsequently, the insulation layer84can be planarized until the cell spacer layer83on the second gate spacer pattern80A is exposed.

As shown inFIG. 5E, a contact hole is formed to expose the first plug82between the gate patterns75in the cell region, and then a conductive layer is formed and planarized to form a second plug85.

In detail, a mask pattern is formed on the insulation layer84to define a region in which a landing plug contact is to be formed between the gate patterns75and the contact hole is formed to expose the first plug82using a self-aligned contact etching process. Through the self-aligned contact etching process, the cell spacer layer83remains at sidewalls of the gate pattern75. Hereinafter, the cell spacer layer83remaining at the sidewalls of the gate patterns75after the self-aligned contact etching process will be referred to as a cell spacer pattern83A. Then, the conductive layer is formed on the first plug82to fill in the space between the gate patterns75and is planarized until the gate hard mask75C is exposed so as to form the second plug85. Here, the conductive layer can be a polysilicon and the planarization is carried out by an etch-back process or a chemical-mechanical polishing. The first and second plugs82and85comprise a landing plug contact.

FIG. 6illustrates a micrographic view of a semiconductor device according to the present invention.

Referring toFIG. 6, a gate spacer is formed at sidewalls of a recessed plug region between gate patterns. Even in a case that misalignment between the gate pattern and a recess region occurs, the electrical insulation between the recess region and the SEG plug is secured because the gate spacer is formed at the sidewalls of the plug region.

The present invention forms a first plug before formation of a cell spacer to increase a contact area between a substrate and the plug, thereby reducing cell contact resistance. Also, the present invention secures a gap-fill margin as much as a height of the first plug at the time of forming an insulation layer which fills in the space between gate patterns.

Further, the present invention forms a gate spacer after forming recessed plug regions between the gate patterns so that the gate spacer remains at sidewalls of the plug regions and thereby securing the electrical insulation between the recess region of the gate pattern and the plug is secured even in case that misalignment between the gate pattern and the recess region occurs.

While the present invention has been described with respect to the specific embodiments, the above embodiment of the present invention is illustrative and not limitative. It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.