Functional blocks implemented by 3D stacked integrated circuit

A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die having an array of non-volatile memory partitions, a volatile memory die having an array of volatile memory partitions, and a processing logic die having an array of processing logic partitions. The non-volatile memory die, the volatile memory die, and the processing logic die are stacked. The non-volatile memory die, the volatile memory die, and the processing logic die can be arranged to form an array of functional blocks, and at least two functional blocks can each include a different data processing function that reduces the computation load of a controller.

FIELD OF THE TECHNOLOGY

At least some embodiments disclosed herein relate to three-dimensional integrated circuits (3D ICs) in general, and more particularly, but not limited to three-dimensional stacked integrated circuits (3D SICs).

BACKGROUND

A 3D IC is an integrated circuit built by stacking silicon dies and interconnecting them vertically so that a combination of the dies is a single device. With a 3D IC, electrical paths through the device can be shortened by its vertically layout, which creates a device that can be faster and has a smaller footprint than similar ICs arranged side-by-side. 3D ICs can be generally grouped into 3D SICs, which refers to stacked ICs with through-silicon via interconnects (TSVs), and monolithic 3D ICs, which are generated using fabrication processes to realize 3D interconnects at the local levels of the on-chip wiring hierarchy as set forth by the International Technology Roadmap for Semiconductors (ITRS). Using the fabrication processes to realize the 3D interconnects can produce direct vertical interconnects between device layers. Monolithic 3D ICs are built in layers on a single wafer that is diced into separate 3D ICs.

3D SICs can be produced by three known general methods: a die-to-die, die-to-wafer, or a wafer-to-wafer method. In a die-to-die method, electronic components are generated on multiple dies. Then, the dies are aligned and bonded. A benefit of a die-to-die method is that each die can be tested before aligned and bonded with another die. In a die-to-wafer method, electronic components are generated on multiple wafers. One of the wafers can be diced and then aligned and bonded on to die sites of another wafer, accordingly. In a wafer-to-wafer method, electronic components are generated on multiple wafers, which are then aligned, bonded, and diced into separate 3D ICs.

A TSV is a vertical electrical connection that can pass through a die. TSVs can be a central part to increasing performance in 3D packages and 3D ICs. With TSVs, compared to alternatives for connecting stacked chips, the interconnect and device density can be substantially higher, and the length of the connections can be shorter.

DETAILED DESCRIPTION

At least some aspects of the present disclosure are directed to functional blocks implemented by a 3D SIC. Also, in general, aspects of the present disclosure are directed to functional blocks implemented by a 3D IC.

In general, a 3D IC is an integrated circuit manufactured by stacking silicon wafers or dies and interconnecting them in a first direction (such as vertically) using, for instance, TSVs or Cu—Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and a smaller footprint than conventional two-dimensional devices.

In some embodiments, TSVs can be used, which makes the 3D ICs embodiments that are considered 3D SICs. Embodiments as 3D ICs or as 3D SICs can be created to be heterogeneous, e.g. combining different memory type layers and/or one or more processing layers into a single IC stack. Alternative embodiments of 3D SICs can include monolithic 3D ICs.

Embodiments using monolithic 3D ICs are created in layers on a single semiconductor wafer that is then diced into 3D ICs. These embodiments are advantageous in that there is no need for aligning, thinning, bonding, or TSVs. Although the disclosure herein is mostly focused on 3D SIC embodiments, it is to be understood that the embodiments disclosed herein are not limited to 3D SIC embodiments. Some embodiments can be a monolithic 3D IC instead of a 3D SIC. In such example embodiments, the overall structure of the 3D IC can be similar; however, the interconnects of a monolithic 3D IC includes fabricated vias instead of TSVs.

As for producing 3D SIC embodiments, such embodiments can be generated by a die-to-die, a die-to-wafer, or a wafer-to-wafer production method. In a die-to-die method, thinning and TSV creation may be done before or after bonding in the production method. An example advantage of die-to-die methods is that each component die can be tested before stacking it with other dies. Also, each die can be separately binned for production. In a die-to-wafer method, similar to a wafer-to-wafer method, thinning and TSV creation are performed either before or after bonding. But, an advantage of die-to-wafer over wafer-to-wafer is that additional dies may be added to a stack before dicing, and a die can be tested before adding it to a wafer. In wafer-to-wafer, each wafer may be thinned before or after bonding, and connections are either built into the wafers before bonding or else created in the stack after bonding. With wafer-to-wafer methods, the TSVs can pass through the silicon substrates between active layers and/or between an active layer and an external bond pad. A disadvantage of a wafer-to-wafer method is that a defect in one chip causes a defect in the entire stacked output of the method.

Chip scaling processes are slowly improving in-part because of power-density constraints and interconnects are not becoming faster while transistors are becoming faster in general. 3D ICs address both of these example scaling problems by stacking two-dimensional dies and connecting the dies in a third dimension. Such stacking can possibly make communications between chips faster, compared to a horizontal arrangement of ICs. Also, 3D ICs can provide other possible benefits over horizontally arranging chips, including: a smaller footprint, shorter interconnects, reduced power consumption, circuit security through obscurity, and increased bandwidth.

3D ICs provide greater functionality into a smaller two-dimensional space by taking advantage of adding functionality in layers of a third dimension, and costs can be saved by partitioning a large chip into multiple smaller dies with 3D stacking. To put it another way, the 3D IC manufacturing can be more modular than conventional processes of producing a chip with an array of ICs. Also, 3D ICs can be generated with layers that are created with different processes or different types of wafers, which increases design options. Also, increased connectivity expands design options.

Another advantage is that 3D ICs reduce power consumption by keeping a signal within the device. Shorter electrical connections in two different directions (e.g., horizontally and vertically) also reduce power consumption by producing less parasitic capacitance for example. Reducing the power budget also leads to less heat generation.

Also, 3D ICs can achieve security through obscurity because the stacked die structure complicates attempts to reverse engineer the overall circuitry. Also, sensitive or critical functions can be divided amongst layers of the 3D IC to further conceal such functions. Some embodiments can even have a layer or die dedicated to monitoring or security of the other layers. This is analogous to a firewall layer, where a separate die of the 3D IC provides a hardware firewall for dies to be monitored at runtime. This can be done to protect parts or the entire stack of chips against attacks.

The fundamental structural arrangement of 3D ICs increases bandwidth by allowing large numbers of vias between the dies or layers that in combination can provide much more bandwidth than a conventional bus. Additionally, a set of functional blocks of the 3D SIC can act like a group of separate computers that are networked or clustered. Different functional blocks can have different types of processing units. And, the different types of functional blocks can be complimentary. And, the more related a functional block is to another block the more beneficial it is to locate two functional blocks next to each other. For example, a first block can provide a first data processing operation and a neighboring second block can provide a second data processing operation in a common multiple operation data processing method. Such features can greatly reduce the load of a controller of computerized system. For instance, such features can reduce the load of a central processing unit (CPU).

In embodiments where the blocks are implemented by a 3D SIC, the use of TSVs can make it advantageous to reduce each functional block to one function so that the benefits of TSVs are fully realized. In such embodiments, the functionality of the 3D IC can be increased by increasing the number of functional blocks in the 3D IC and not the number of functions that a single functional block can perform. This way, the TSV or another type of interconnect of a 3D SIC can be used to its full potential.

A TSV is an electrical connection that can pass completely through a silicon wafer or die. With TSVs, interconnections and device density is substantially higher than with conventional interconnections between die. And, length of the connections between die is shorter than conventional interconnections.

Some embodiments can have TSVs added to the 3D IC structure via-first TSV fabrication. This is a process where the TSVs are fabricated before the components, e.g., transistors, capacitors, and resistors, are patterned onto the wafer. Some embodiments use via-middle TSV fabrication where TSVs are fabricated after the individual devices are patterned but before the metal layers are added to a die or a stack of dies. And, some embodiments use via-last TSV fabrication where TSVs are fabricated after or during the addition of metal layers.

In addition to the way in which TSVs are added to the 3D IC, the layout and design of the TSVs can vary between embodiments described herein. For example, differences in partitioning granularity of functional elements of the dies of the 3D IC can cause variation in the design and layout of TSVs. Some embodiments have gate level partitioning using TSVs and other embodiments have block level partitioning. Gate level partitioning using TSVs is less practical than block level partitioning; thus, to increase the benefit of having more TSVs, functional sub-elements partitioned within a functional block can be connected via TSVs. This can be a middle ground solution.

In some embodiments, a stack of chips or die can have a processing logic integrated circuit (IC), in addition to memory ICs, such as 3D XPoint memory (3DXP) and dynamic random access memory (DRAM) ICs. Units of processing logic, 3DXP and DRAM can be connected to form a functional block, such as by TSVs. Different functional blocks can be configured differently on demand and/or operate substantially independently from each other in one 3D SIC or, in general, in one 3D IC. The processing logic implements frequently used functions and/or data intensive functions, such that even though the processing logic IC may not have the processing power of a CPU, its advantage in better data access can provide a better overall performance in implementing selected functions. Multiple functional blocks (e.g., multiple column functional blocks within a 3D SIC or 3D IC) can run in parallel and reduce the computation load on the CPU.

As mentioned, in some embodiments, the processing logic IC or die does not have a full array of processing cores that a typical CPU would have. But, in such embodiments, the processing logic implements frequently used functions and/or data intensive functions; thus, having potential to relieve the CPU of significant processing duties and enhancing the performance of the CPU. In such embodiments, a functional block cannot execute a complete set of multifunctional instructions on its own. Therefore, the functional block and the remainder of the 3D IC can be connected to a CPU, and the CPU may instruct the function block to do a task it is configured to do. For example, a functional block of example embodiments can be configured to decrypt, by its processing logic IC, the data stored in its non-volatile memory IC, and insert the decrypted data into its volatile memory to be communicated to the CPU for further processing by CPU. Also, the CPU can provide a request to the volatile memory of a functional block to request the block to generate a result of a certain function, and the CPU can also provide a follow-up request to retrieve the result from the functional block. For instance, the request for generation of the result can be provided from the CPU to the functional block in the form of a write command, and the request to retrieve the result can be provided from the CPU to the functional block in the form of a read command.

FIG. 1illustrates a front view of a 3D SIC100having multiple non-volatile memory dies102and104, a volatile memory die108, and a processing logic die106in accordance with some embodiments of the present disclosure. As shown, the dies are parallel to each other. The 3D SIC100also has functional blocks110,112, and114(as shown inFIG. 1) as well as functional blocks210,212,214,220,222, and224(as shown inFIGS. 2-5) that traverse and are perpendicular to the multiple non-volatile memory dies102and104, the volatile memory die108, and the processing logic die106. The 3D SIC100also has TSVs116, TSVs118, and TSVs120that connect the dies respectively. TSVs116are shown in between and connecting the non-volatile memory die102to the non-volatile memory die104. TSVs118are shown in between and connecting the non-volatile memory die104to the processing logic die106. TSVs120are shown in between and connecting the processing logic die106to the volatile memory die108. It is to be understood that all the TSVs described herein pass through the dies described herein even thought this may not be clear from the drawings. For example, TSVs116, TSVs118, and TSVs120are parts of single TSVs passing through the dies of the 3D SIC100.

The 3D SIC100also has interconnects122,124,126, and128, which are shown as embedded in the dies respectively. Interconnects122are shown embedded in the non-volatile memory dies102. Interconnects124are shown embedded in the non-volatile memory dies104. Interconnects126are shown embedded in the processing logic die106. And, interconnects128are shown embedded in the volatile memory die108. The interconnects122,124,126, and128can be perpendicular to the TSVs116,118, and120(as shown inFIG. 1and as shown partially inFIG. 5).

It is to be understood that interconnects described herein, such as interconnects122,124,126, and128, refer to interconnections between components of a chip or die (e.g., copper or metal interconnects, interconnect traces, etc.). The interconnects can include interconnects in the metallization layer of a die or chip.

As depicted, in some embodiments, a 3D SIC can have multiple non-volatile memory dies. In some embodiments, the non-volatile memory dies are slower than the volatile memory dies. Specifically, the non-volatile memory dies have less bandwidth (e.g., the maximum amount of data the die can transfer each second) than the volatile memory dies. The non-volatile memory dies can include 3DXP dies or any other type of electrically addressed memory system die, e.g., a EPROM die, flash memory die, ferroelectric RAM, and magnetoresistive RAM. Each non-volatile memory die can have an array of non-volatile memory partitions. Each partition of the array of non-volatile memory partitions can include an array of non-volatile memory cells and each cell can have a corresponding address.

FIG. 2illustrates a top view of the non-volatile memory die102having multiple non-volatile memory partitions204a,204b,204c,204d,204e,204f,204g,204h, and204iin accordance with some embodiments of the present disclosure. The partitions can be arranged in second direction (i.e., perpendicular to the direction of the stacking of the dies of the 3D IC). Each of the partitions204a,204b,204c,204d,204e,204f,204g,204h, and204ihas multiple non-volatile memory elements. Each of the partitions illustrated inFIG. 2shows nine non-volatile memory element clusters206. And, each of the non-volatile memory element clusters206shows nine non-volatile memory elements208. Thus, each of the partitions illustrated inFIG. 2has eighty-one memory elements208. However, it is to be understood that the depiction of eighty-one memory elements is for convenience sake and that in some embodiments each partition could have up to at least a billion memory elements. To put it another way, the number of memory elements per non-volatile memory partition can be enormous and vary greatly. Also, it is to be understood that non-volatile memory die102and non-volatile memory die104are similar or exactly the same with respect to structure and design.

A 3DXP IC (also known as a 3D XPoint memory IC) uses transistor-less memory elements, each of which has a memory cell and a corresponding address (as well as an optional selector and the cell and optional selector can be stacked together as a column). In examples with memory elements, the memory elements can be connected via two perpendicular layers of interconnects (as shown but not labeled inFIG. 2), where one layer is above the memory elements and the other layer is below the memory elements. Each memory element can be individually selected at a cross point of one interconnect on each of the two layers of interconnects (e.g., see cross point209shown inFIG. 2). Each cross point has an address or is addressable or selectable such as by an address decoder of the 3DXP IC, the 3D IC, or a group of ICs of the 3D IC. 3DXP devices are fast and non-volatile and can be used as a unified memory pool for processing and storage.

As mentioned, the non-volatile memory dies102and104can be 3DXP dies. Some advantages of using a 3DXP die as the non-volatile memory die of the 3D SIC100include that it is bit addressable by an address decoder. An address decoder (not shown in the drawings) used with an embodiment described herein can be a binary decoder that has two or more inputs for address bits and one or more outputs for device selection signals. When the address for a particular device or IC appears on the address inputs, the decoder asserts the selection output for that device or IC. A dedicated, single-output address decoder can be incorporated into each device or IC on an address bus, or a single address decoder can serve multiple devices or ICs.

Also, the 3D SIC can have a volatile memory die (such as a DRAM die or a static random access memory (SRAM) die) including an array of volatile memory partitions. Each partition of the array of volatile memory partitions can include an array of volatile memory cells and each cell can have a corresponding address.

FIG. 3illustrates a top view of the volatile memory die108having multiple volatile memory partitions304a,304b,304c,304d,304e,304f,304g,304h, and304iin accordance with some embodiments of the present disclosure. The partitions can be arranged in a second direction (i.e., perpendicular to the direction of the stacking of the dies of the 3D IC). Each of the partitions304a,304b,304c,304d,304e,304f,304g,304h, and304ihas multiple volatile memory elements. Each of the partitions illustrated inFIG. 3shows nine volatile memory element clusters306. And, each of the volatile memory element clusters306shows nine volatile memory elements308. Thus, each of the partitions illustrated inFIG. 3has eighty-one memory elements308. However, it is to be understood that the depiction of eighty-one memory elements is for convenience sake and that in some embodiments each partition could have up to at least a billion memory elements. To put it another way, the number of memory elements per volatile memory partition can be enormous and vary greatly.

The 3D SIC can also have a processing logic die having an array of processing logic partitions. Each partition can have a separate field-programmable gate array (FPGA) or another type of processing logic device. The processing logic die can include a controller unit and an arithmetic/logic unit. For instance, the arithmetic/logic unit can include an FPGA.

FIG. 4illustrates a top view of the processing logic die106having multiple processing logic partitions404a,404b,404c,404d,404e,404f,404g,404h, and404iin accordance with some embodiments of the present disclosure.FIG. 4shows each of the partitions404a,404b,404c,404d,404e,404f,404g,404h, and404ihaving a separate FPGA406. As shown, each of the nine FPGAs406illustrated inFIG. 4has thirty-two input/output blocks408and sixteen logic blocks410. Also,FIG. 4shows programable or non-programable interconnects412between the input/output blocks408and the logic blocks410of each of the nine FPGAs406. It is to be understood that the depiction of the amount of input/output units and logic units of an FPGA406is for convenience sake and that in some embodiments each FPGA of a partition could have more or less input/output units and logic units depending on the embodiment of the corresponding functional block. Also, even thoughFIG. 4shows one FPGA per partition, it is to be understood that each processing logic partition can have multiple FPGAs in other embodiments of the 3D SIC or the processing logic die. To put it another way, the number of specific parts of the processing logic die can vary greatly.

FIGS. 2, 3, and 4also show the functional blocks110,112,114,210,212,214,220,222, and224of the 3D SIC100.FIG. 2shows a top view of respective sections of the functional blocks at the non-volatile memory die102.FIG. 3shows a top view of respective sections of the functional blocks at the volatile memory die108.FIG. 4shows a top view of respective sections of the functional blocks at the processing logic die106.

FIGS. 2, 3, and 4also show the interconnects122,128, and126interconnecting the non-volatile memory partitions, the volatile memory partitions, and the processing logic partitions respectively. Thus, the interconnects122,128, and126are also shown interconnecting the functional blocks of the 3D SIC100at each layer of the 3D SIC. Specifically, as shown inFIG. 2, the interconnects122interconnect the non-volatile memory partitions204a,204b,204c,204d,204e,204f,204g,204h, and204iof the non-volatile memory die102. As shown inFIG. 3, the interconnects128interconnect the volatile memory partitions304a,304b,304c,304d,304e,304f,304g,304h, and304iof the volatile memory die108. And, as shown inFIG. 4, the interconnects126interconnect the processing logic partitions404a,404b,404c,404d,404e,404f,404g,404h, and404iof the processing logic die106.

In the 3D SIC, the non-volatile memory die, the volatile memory die, and the processing logic die are stacked in a first direction (such as vertically), and the processing logic die can be stacked in between the non-volatile memory die and the volatile memory die. The 3D SIC can also have an array of functional blocks which are made up from the dies of the 3D SIC. To put it another way, the non-volatile memory die, the volatile memory die, and the processing logic die are arranged to form the array of functional blocks. At least two functional blocks of the array of functional blocks each can include a different data processing function that reduces the computation load of a controller—such reducing the computational load of a CPU. Each functional block of the array of functional blocks can include a respective column of the 3D SIC. A respective column of the 3D SIC can include a respective non-volatile memory partition of the array of non-volatile memory partitions, a respective volatile memory partition of the array of volatile memory partitions, and a respective processing logic partition of the array of processing logic partitions. A respective processing logic partition can be stacked in the first direction in between a respective non-volatile memory partition and a respective volatile memory partition.

FIG. 5illustrates a perspective view of the 3D SIC100illustrated inFIG. 1having multiple non-volatile memory dies102and104, volatile memory die108, and processing logic die106in accordance with some embodiments of the present disclosure.FIG. 5shows perspective views of the non-volatile memory dies102and104, the volatile memory die108, and the processing logic die106and how the dies are stacked in a first direction (e.g., vertically), and how the processing logic die can be stacked in between the non-volatile memory dies and the volatile memory die.FIG. 5also shows the array of functional blocks completely in that all the functional blocks110,112,114,210,212,214,220,222, and224of the 3D SIC100are depicted.

It is to be understood that the number of functional blocks of a 3D SIC can vary depending on the embodiment of the 3D SIC. Each functional block of the array of functional blocks illustrated inFIGS. 1-5can include a respective column of the 3D SIC100, as shown. And, as shown by the combination ofFIGS. 1-5, a column of the 3D SIC, having a single functional block, can include a respective non-volatile memory partition of the array of non-volatile memory partitions, a respective volatile memory partition of the array of volatile memory partitions, and a respective processing logic partition of the array of processing logic partitions. Also, shown by the combination of these drawings, a respective processing logic partition can be stacked in a first direction (e.g., vertically) in between a respective non-volatile memory partition and a respective volatile memory partition.

In some embodiments, each of two abutting functional blocks of the array of functional blocks can have different particular data processing functions that are commonly used together for a greater particular data processing function. Particular data processing functions can include fundamental processes of a CPU, such as decoding processes of a decode operation of CPU.

Embodiments of the 3D IC or at least a group of functional blocks of some embodiments can function as an instruction decoder for a CPU. This way the CPU can reserve resources for fetching and execution operations, when connected to such embodiments of the 3D IC.

Particular data processing functions can also include functions of an arithmetic logic unit of a CPU, such as integer arithmetic and bitwise logic operations. This way the CPU can reserve resources by delegating arithmetic logic unit operations to such embodiments of the 3D IC.

Also, embodiments of the 3D IC or at least a group of functional blocks of some embodiments can function as different types of encoders and/or decoders besides those usually hardwired or programmed into a CPU. For example, embodiments of the 3D IC or at least a group of functional blocks of some embodiments can function as an encryption block wherein the 3D IC or at least a group of functional blocks have a cipher that can generate a ciphertext. Also, embodiments can function as a decryption block. In one embodiment, one or more blocks of the 3D IC can be dedicated to encryption and other one or more blocks of the same 3D IC can be dedicated to decryption. Also, embodiments of the 3D IC or at least a group of functional blocks of some embodiments can function as one or more data processing intensive operations, such as data intensive operations of a type of machine learning.

The 3D SIC can also include a first set of TSVs that connect the respective non-volatile memory partition and the respective processing logic partition in the respective column of the 3D SIC (e.g., TSVs118as shown inFIGS. 1 and 5) as well as a second set of TSVs that connect the respective volatile memory partition and the respective processing logic partition in the respective column of the 3D SIC (e.g., TSVs120as shown inFIGS. 1 and 5).

In some embodiments, processing logic die can include a control unit and an arithmetic/logic unit, and each of the memory ICs can include storage parts that are addressable by an address decoder and/or have predefined addresses. In such embodiments, the control unit is connected with the storage parts of the memory ICs and the arithmetic/logic unit is connected with the storage parts of the memory ICs and/or the parts of the IC are connected to the storages parts of the memory ICs via an address decoder.

In some embodiments including the control unit and the arithmetic/logic unit, the control unit is configured to, during an instruction time, get instructions from the volatile memory IC of the 3D IC and decode the instructions and direct data to be moved from the volatile memory IC to the arithmetic/logic unit according to at least part of the instructions. And, the arithmetic/logic unit can be configured to, during an execution time, execute the at least part of the instructions and store a result of the execution of the at least part of the instructions in a non-volatile memory IC of the 3D IC.

In such embodiments, the arithmetic/logic unit is given control and performs the actual operation on the data. The combination of instruction time and execution time can be a machine cycle of the 3D IC, and in some embodiments, the control unit can direct, during the execution time, the volatile memory IC and/or the non-volatile memory IC to release the result to an output device or a storage device external of the apparatus. In some embodiments, connections between the control and arithmetic/logic units and the memory units of the memory ICs are connections that can be TSVs. To put it another way, the control unit can be connected in a first direction (e.g., vertically), by a plurality of electrical connections, with the memory elements of the memory ICs and the arithmetic/logic unit is connected in the first direction, by a plurality of electrical connections, with the memory elements of the memory ICs.

The memory cells and logic units of each IC or die of the 3D IC can be connected to each other by a plurality of electrical connections in a second direction that is orthogonal to the first direction (e.g., a horizontal direction). For example, the 3D SIC can also include a first set of interconnects that connect non-volatile memory partitions of the array of non-volatile memory partitions in the second direction (e.g., interconnects122as shown inFIGS. 1 and 2), a second set of interconnects that connect volatile memory partitions of the array of volatile memory partitions in the second direction (e.g., interconnects128as shown inFIGS. 1 and 3), and a third set of interconnects that connect processing logic partitions of the array of processing logic partitions in the second direction (e.g., interconnects126as shown inFIGS. 1 and 4). In some embodiments having the three sets of interconnects, an interconnect of the first set of interconnects only connects a non-volatile memory partition of the array of non-volatile memory partitions to another non-volatile memory partition directly next to the non-volatile memory partition (e.g., see interconnects122as shown inFIGS. 1 and 2). Also, in such embodiments, an interconnect of the second set of interconnects only connects a volatile memory partition of the array of volatile memory partitions to another volatile memory partition directly next to the volatile memory partition (e.g., see interconnects128as shown inFIGS. 1 and 3). And, an interconnect of the third set of interconnects only connects a processing logic partition of the array of processing logic partitions to another processing logic partition directly next to the processing logic partition (e.g., see interconnects126as shown inFIGS. 1 and 4).

Some exemplary embodiments of the 3D SIC includes a processing logic die, a 3DXP die, and a DRAM die, with the processing logic die being stacked between the 3DXP die and the DRAM die. In such exemplary embodiments, a set of TSVs interconnect the processing logic die, the 3DXP die, and the DRAM die. In such exemplary embodiments or some other exemplary embodiments, the 3D SIC includes a 3DXP die having an array of non-volatile memory partitions, with each partition of the array of non-volatile memory partitions having an array of non-volatile memory cells. In such embodiments, a volatile memory die has an array of volatile memory partitions, with each partition of the array of volatile memory partitions having an array of volatile memory cells. Also, in such embodiments, a processing logic die is included and has an array of processing logic partitions. And, the 3DXP die, the volatile memory die, and the processing logic die are stacked a first direction (e.g., vertically) with the processing logic die stacked in between the 3DXP die and the volatile memory die. Further, such embodiments of the 3D SIP can include a first set of TSVs that connect a respective non-volatile memory partition and a respective processing logic partition in a respective column of the 3D SIC. And, such embodiments can include a second set of TSVs that connect a respective volatile memory partition and the respective processing logic partition in the respective column of the 3D SIC.

The 3D SIC can also have multiple non-volatile memory dies (as shown inFIGS. 1 and 5). For example, the 3D SIC can include a second non-volatile memory die can include a second array of non-volatile memory partitions. And, each partition of the second array of non-volatile memory partitions can have an array of non-volatile memory cells. In embodiments where the 3D SIC has multiple non-volatile memory dies, the non-volatile memory dies (such as the first and second non-volatile memory dies) can be grouped together such that the processing logic die is in between the volatile memory die and the group of non-volatile memory dies (as shown inFIGS. 1 and 5).

In some embodiments of the 3D SIC, each functional block the 3D SIC can have a respective communications interface (i.e., a respect port) configured to communicatively couple the block to a bus so that each block can operate in parallel and independently of the other. Additionally or alternatively, groups of at least two functional blocks of the 3D SIC each share a respective communications interface configured to communicatively couple the at least two functional blocks to a bus, so that each group of at least two functional blocks can operate in parallel and independently of another group of at least two functional blocks. Additionally, or alternatively, the 3D SIC can have one or more universal communications interfaces (i.e., one or more universal ports) configured to communicatively couple any one or all of the functional blocks of the 3D SIC to a bus.

FIG. 6illustrates a block diagram of an example computer system600in which embodiments of the present disclosure can operate. As shown inFIG. 6, the computer system600includes the 3D SIC100that includes a communications interface602(or also referred to as port602). The communications interface602is communicatively coupled to a bus604of the computer system600. The bus604is communicatively coupled to a controller of the computer system600(e.g., a CPU of the system600) as well as a main memory608and network interface610of the computer system600. As shown inFIG. 6, the network interface610communicatively couples the computer system600to a computer network612.

The computer system600can be or include a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that computerized system. Further, while a single computer system600is illustrated, the term “computer system” shall also be taken to include any collection of computer systems. The bus604can be or include multiple buses. The controller606represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Controller606can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a FPGA, a digital signal processor (DSP), network processor, or the like. The main memory608can be a read-only memory (ROM), flash memory, DRAM such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), and/or SRAM.

Referring toFIGS. 1 and 6, in some embodiments, the port602can be configured to communicatively couple the volatile memory die108to the bus604. In such an arrangement, the controller606can delegate data processing functions to the 3D SIC100via the bus604and the volatile memory die108. The delegated data processing functions can be data intensive functions or commonly used functions of the controller606. As mentioned, in some embodiments, the processing logic IC or die does not have a full array of processing cores that a typical CPU would have. But, in such embodiments, the processing logic can implement frequently used functions and/or data intensive functions; thus, having potential to relieve the CPU of significant processing duties and enhancing the performance of the CPU. Also, in the depicted embodiments, a functional block cannot execute complete set of multifunctional instructions on its own. Therefore, a functional block and the remainder of the 3D SIC100can be connected to a controller (such as a CPU) and the controller can instruct the function block to do a task it is configured to do.

For example, a functional block of example embodiments can be configured to decrypt, by its processing logic partition, the data stored in its corresponding non-volatile memory partition, and insert the decrypted data into its corresponding volatile partition to be communicated to the controller for further processing by controller.

Also, in general, the controller can provide a request to the volatile memory partition of a functional block to request the block to generate a result of a certain function, and the controller can also provide a second or follow-up request to retrieve the result from the functional block. For instance, the request for generation of the result can be provided from the controller to the functional block in the form of a write command, and the request to retrieve the result can be provided from the controller to the functional block in the form of a read command.

FIG. 7illustrates a flow diagram of an example method700in which embodiments of the 3D SIC (e.g., 3D SIC100ofFIGS. 1-6) can interact with a controller (e.g., controller606ofFIG. 6) via a bus (e.g., bus604ofFIG. 6).

The method700in general can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. Although shown in a particular sequence or order and performed by particular hardware/software, unless otherwise specified, the order and hardware/software of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order and/or by different hardware/software, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible as well.

Specifically, the method700can be performed by at least the non-volatile memory die102and/or the non-volatile memory die104, the processing logic die106, the volatile memory die108, and the controller606(as illustrated inFIG. 7). At block701, the controller606communicates a request, via a bus. The request of the controller606is configured to instruct the 3D SIC to generate a result of a particular data processing function. Such a request can be delivered to the 3D SIC via a write command of the controller606. For example, if a write command is used by the controller606to make the request, then the request is sent to the selected volatile memory partition of the volatile memory die108. Alternatively, an execute command can be used by the controller606to make the request, and in such instances the request can be directly sent to the selected processing logic partition of the processing logic die106.

At block702, the volatile memory die108receives the request via the bus. The volatile memory die108can be configured to receive, from the bus through the port602, the request of the controller. In addition to being configured to instruct the 3D SIC to generate a result of a particular data processing function, the request can include at least one input parameter of the particular data processing function. At block704, the volatile memory die108stores the request and communicates the request to the processing logic die106. The volatile memory die108can be configured to store the request in at least one volatile partition of the volatile memory die.

At block706, the stored request is received by the processing logic die. And, at block706, the at least one input parameter of the particular data processing function can be received by the at least one processing logic partition through a TSV connecting the at least one volatile partition of the volatile memory die and the at least one processing logic partition.

At block708, the processing logic die generates the result accordingly to the stored request. At least one processing logic partition of the processing logic die106can include the particular data processing function and the particular data processing function can generate the result according to the stored request and the at least one input parameter of the particular data processing function. The particular data processing function can be hardwired into the at least one processing logic partition of the processing logic die. Alternatively, the particular data processing function can be configured, by the controller606or another controller, in the at least one processing logic partition of the processing logic die temporarily. For example, the particular data processing function can be implemented by a FPGA configurable by the controller606or another controller.

At block710, the processing logic die106communicates the result to the non-volatile memory die102and/or the non-volatile memory die104. The processing logic die106can be configured to communicate the generated result of the particular data processing function to the non-volatile memory die via a TSV connecting at least one non-volatile partition of the non-volatile memory die and the at least one processing logic partition.

At block712, the non-volatile memory die102and/or the non-volatile memory die104receives and stores the result that is communicated from the processing logic die106. The non-volatile memory die102and/or the non-volatile memory die104can be configured to store the generated result in at least one non-volatile partition and communicate the stored result to the processing logic die106upon the processing logic die requesting the stored result. The processing logic die106requesting the stored result can be in response to the volatile memory die108requesting the stored result which can be in response to the controller606requesting the stored result via the bus604.

The processing logic die106can be configured to retrieve the stored result from the non-volatile memory die via a TSV connecting the at least one non-volatile partition and the at least one processing logic partition. And, the 3D SIC can be configured to communicate the retrieved result to the volatile memory die via a TSV connecting the at least one volatile partition and the at least one processing logic partition. The volatile memory die can be configured to receive and store the retrieved result in the at least one volatile partition, and communicate, via the port, the stored retrieved result to the bus according to a second request of the controller, when the second request of the controller is configured to instruct the 3D SIC to retrieve a result generated by the particular data processing function. In some examples, where a read command is used by the controller606to make the second request, the second request is sent to the selected volatile memory partition of the volatile memory die108.

With respect toFIG. 7, at block714a, the controller communicates the second request that is configured to instruct the 3D SIC to retrieve a result generated by the particular data processing function. At block714b, the second request is received, stored, and sent to the processing logic die106, by the volatile memory die108. At block714c, the second request is received, stored, and forwarded to the non-volatile memory die102and/or the non-volatile memory die104, by the processing logic die106.

At block716, in response to block714c, the non-volatile memory die102and/or the non-volatile memory die104communicates the stored result to the processing logic die106. At block718, the processing logic die106receives the retrieved result, and at block720, the processing logic die106communicates the retrieved result to the volatile memory die108. The processing logic die106can be configured to retrieve the stored result from the non-volatile memory die via the TSV connecting the at least one non-volatile partition and the at least one processing logic partition. And, the processing logic die106can be configured to communicate the retrieved result to the volatile memory die via the TSV connecting the at least one volatile partition and the at least one processing logic partition.

At block722, the volatile memory die108receives and stores the retrieved result sent from the processing logic die106. At block724, the retrieved result is then communicated to the controller606, by the volatile memory die108. The volatile memory die can be configured to receive and store the retrieved result in the at least one volatile partition as well as be configured to communicate, via the port, the stored retrieved result to the bus according to a second request of the controller configured to instruct the 3D SIC to retrieve a result generated by the particular data processing function.

At block726, the controller606receives the retrieved result. The retrieve result can be used by the controller606for another processing step or outputted by the controller to another device.

In such embodiments, at least two of a volatile partition, a non-volatile partition, and a processing logic partition can be in the same one or more columns of the 3D SIC. For example, a volatile partition, a non-volatile partition, and a processing logic partition used together can be in the same one or more columns of the 3D SIC. Also, in some embodiments, each of two abutting functional blocks of the array of functional blocks can have different sub-particular data processing functions of the particular data processing function.

A particular data processing function (such as the particular data processing function described with the method700) can include a fundamental process of the controller606. For example, if the controller606is a CPU, the fundamental process can be a decoding process of the decode operation of a CPU. The processing logic die106can be programmed or hardwired as a decoder for a CPU or at least a common part or data intensive part of a decoder for a CPU. This way a CPU can reserve resources for fetching and execution operations, when connected to the 3D SIC100.

The particular data processing function can also include the processing logic providing at least part of the functionality of an arithmetic logic unit of a CPU and such functionality can be programmed or hardwired into the processing logic die106. And, abutting partitions of the processing logic die106can provide sub-operations of an arithmetic logic unit such as different integer arithmetic and bitwise logic operations. This way the CPU can reserve resources by delegating arithmetic logic unit operations to the 3D SIC100.

Also, the processing logic die106can function as different types of encoders and/or decoders besides those usually hardwired or programmed into a CPU. For example, with embodiments of the 3D SIC100or at least a group of functional blocks of some embodiments, the 3D SIC100can provide an encryption function wherein the 3D IC or at least a group of functional blocks have a cipher hardwired or programmed into the processing logic die106so that the die can generate a ciphertext and then the ciphertext can be stored immediately in the non-volatile memory die102and/or the non-volatile memory die104of the 3D SIC100for subsequent retrieval by the controller606. And, the processing logic die106or partitions of the die can function as a decryption algorithm. In one embodiment, one or more blocks of the 3D SIC100can be dedicated to encryption and other one or more blocks of the 3D IC can be dedicated to decryption.

Also, the 3D SIC100or at least a group of functional blocks of some embodiments can function as one or more certain data processing intensive operations, such as selected data intensive operations of a type of machine learning. And, data intensive operations that are immediately preceding or following each other in a machine learning algorithm or another type of complex computerized algorithm can be implemented by blocks of the 3D SIC100that are abutting each other. Thus, speeding up the transitional time between operations of an algorithm as well as providing other benefits such as reduced power consumption.

In some embodiments, a first memory IC of a 3D IC can provide non-volatile storage parts when the apparatus is powered on. Each non-volatile storage part of the non-volatile storage parts stores a bit while receiving power or not while receiving power. Also, a second memory IC of the 3D IC can provide volatile storage parts when the apparatus is powered on. Each volatile storage part of the volatile storage parts stores a bit only while receiving power. In such embodiments, electrical connections of the 3D IC that are in a second direction that is orthogonal to the first direction (e.g., a horizontal direction) can communicatively couple first storage parts of the first memory IC to each other and second storage parts of the second memory IC to each when the apparatus is powered on. And, electrical connections in a first direction (e.g., vertically) of the 3D IC can communicatively couple a control unit and an arithmetic/logic unit of a processing logic IC of the 3D IC to the storage parts of the first and second memory ICs to control use the storage parts, when the apparatus is powered on.

In such embodiments, during a machine cycle of the 3D IC, the control unit can get instructions from the first memory IC and/or the second memory IC during the instruction time of the machine cycle. And, during a machine cycle of the 3D IC the control unit or a decoder controlled by the control unit can decode the instructions and direct data to be moved from the first memory IC and/or the second memory IC to the arithmetic/logic unit according to at least part of the instructions during the instruction time. Also, during a machine cycle, the arithmetic/logic unit can execute the at least part of the instructions during the execution time of the machine cycle, and store a result of the execution of the at least part of the instructions in the first memory IC and/or the second memory IC during the execution time. Further, during a machine cycle, the control unit can direct the first memory IC and/or the second memory IC to release the result to an output device or a storage device external to the apparatus during the execution time.

In one example system of some embodiments, the system can include a first functional block that includes a first processing logic IC, a first memory IC, and a second memory IC. The first processing logic IC, the first memory IC, and the second memory IC can be arranged in a first direction (e.g., vertically) as a stack of ICs to form the first functional block. The system can also include a second functional block that can include a second processing logic IC, a third memory IC, and a fourth memory IC. The second processing logic IC, the third memory IC, and the fourth memory IC can be arranged in the first direction as a stack of ICs to form the second functional block. The system can also include at least one bus or an interconnect that communicatively couples the first functional block and the second functional block.

In such an example system, the first and second functional blocks are each configured differently from each other for different respective data processing functions. The data processing functions can be different frequently used functions and/or data intensive functions, such that even though each processing logic IC of a block may not have the processing power of a CPU, its advantage in improved (e.g., closer) data access to non-volatile and volatile memory so that it can provide a better overall performance in implementing selected functions. Each functional block of the first and second functional blocks can configurable on demand by a controller (e.g., a CPU) that is connected to the functional blocks via a wired and/or wireless bus. Each functional block of the first and second functional blocks can be configured to reduce the computation load of the controller. The configuration of each functional block of the first and second functional blocks can include on demand configuration of the respective processing logic IC of the functional block. Each functional block of the first and second functional blocks can be configured to operate independently from each other. Each functional block of the first and second functional blocks is configured to operate in parallel to provide parallel data processing.

In one example method of some embodiments implemented by multiple functional blocks of one or more 3D ICs, a functional block of the multiple functional blocks can perform a first data processing function that includes a processing logic IC controlling storage and retrieval of data to and from first and second memory ICs. The functional block can also be changed on demand (such as by a CPU), so that the functional block is configured to perform a second data processing function. The functional block can also perform the second data processing function that includes the processing logic IC controlling storage and retrieval of data to and from the first and second memory ICs in a different way from the way the processing logic IC controls storage and retrieval of data to and from the first and second memory ICs during the first data processing function. In such an example method, each functional block of the multiple functional blocks includes a respective processing logic IC, a respective first memory IC, and a respective second memory IC, and the respective processing logic IC, the respective first memory IC, and respective the second memory IC are arranged in a first direction (e.g., vertically) as a stack of ICs to form the functional block.