GAA LDMOS STRUCTURE FOR HV OPERATION

A gate-all-around (GAA) high voltage transistor of the laterally double-diffused metal-oxide semiconductor (LDMOS) type has a loop-shaped gate electrode disposed below a surface of a semiconductor substrate. The loop-shaped gate electrode surrounds a vertical channel formed by a first source/drain region, a body region, and a diffusion region. The first source/drain region is on top, the body region is in the middle, and the diffusion region is underneath. A loop-shaped shallow trench isolation (STI) region surrounds the loop-shaped gate electrode. The diffusion region begins inside the loop-shaped gate electrode, extends under the loop-shaped gate electrode and the loop-shaped STI region, and rises outside the loop-shaped STI region to join with a second source/drain region. This structure allows pitch to be reduced by 40% or linear drive current to be doubled in comparison to an asymmetric NMOS transistor providing otherwise equivalent functionality.

BACKGROUND

The integrated circuit (IC) manufacturing industry has experienced exponential growth over the last few decades. As ICs have evolved, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased while geometry size (i.e., the smallest component that can be created) has generally decreased. Another development is BCD technology which is a combination of bipolar junction transistor (BJT) technology, complementary metal-oxide-semiconductor (CMOS) technology, and double-diffused metal-oxide-semiconductor (DMOS) technology. BCD technology allow logic, analog, and power devices to be formed on a single semiconductor chip. BCD technology creates challenges in its needs for process compatibility and for limiting the proliferation of process steps.

DETAILED DESCRIPTION

The present disclosure provides a novel gate-all-around (GAA) high voltage transistor of the lateral double-diffused metal-oxide semiconductor (LDMOS) type that can be produced with minimal modifications to an exiting BCD process sequence. The novel GAA LDMOS transistor provides a substantial improvement in linear drive current for a given chip area. Pitch may be reduced by 40% or linear drive current doubled in comparison to an asymmetric N-channel metal-oxide semiconductor (NMOS) transistor providing otherwise equivalent functionality.

The novel GAA LDMOS features a loop-shaped gate electrode disposed below a surface of a semiconductor substrate. The loop-shaped gate electrode surrounds a vertical channel formed by an inner source/drain region, a body region, and a diffusion region. The inner source/drain region is surrounded by the loop-shaped gate electrode. The body region is below the inner source drain region. The diffusion region extends from below the body region, goes under the loop-shaped gate electrode, and rises to join with an outer source/drain region that is outside the loop-shaped gate electrode. In some embodiments, a shallow trench isolation (STI) region surrounds the loop-shaped gate electrode, and the diffusion region extends under the STI region as well as the loop-shaped gate electrode.

In some embodiments, the loop-shaped gate electrode has square-sided horizontal cross-sections. In some embodiments, the loop-shaped gate electrode has circular-sided horizontal cross-sections. Other shapes are possible provided the loop-shaped gate electrode surrounds an island of semiconductor substrate that provides the body region in which the vertical channel forms. The loop-shaped gate electrode is separated from the vertical channel by the width of a gate dielectric. The circular-sided structure may provide the highest efficiency. The square-sided structure may provide nearly the same efficiency and may be easier to form from a processing standpoint.

In some embodiments the loop-shaped gate electrode is in a gate stack with a gate dielectric. In some embodiments, a bottom of the gate stack is level with a bottom of the STI region. In some embodiments, a bottom of the gate stack is offset above the level of the bottom of the STI region. The vertical channel begins above the level of the bottom of the gate stack and so is even further displaced from the bottom of the STI region. Making the STI region run deeper than the gate stack and the channel facilitates giving the GAA transistor a high breakdown voltage while remaining compact.

In a process according to some aspects of the present disclosure, a loop-shaped STI region is formed in a semiconductor substrate. An etch process removes an inner portion of the STI region and to form a loop-shaped trench. The loop-shaped trench is lined with a gate oxide then filled to form the loop-shaped gate electrode. Ion implantations defines the body region, the inner source/drain region, and the outer source/drain region.

The loop-shaped STI region may have a sidewall that is sloped at a first angle relative to a surface normal of the semiconductor substrate. In some embodiments, the loop-shaped gate electrode has an inner sidewall that is also sloped at the first angle. In some embodiments, the loop-shaped gate electrode may have an outer sidewall that is sloped at a second first angle relative to the surface normal and the second angle is distinct from the first angle. These features may be the result of a process according to the present disclosure.

In some embodiments, the loop-shaped gate electrode has an upper surface that is recessed relative to an upper surface of the semiconductor substrate. In some embodiments, the gate dielectric and the loop-shaped gate electrode, which are disposed below a surface of the semiconductor substrate, are formed a gate stack from which are also formed gates that are disposed above the surface of the semiconductor substrate. In some embodiments, patterning the gate electrodes that are disposed above the upper surface of the semiconductor substrate includes an etch process that causes the loop-shaped gate electrode to be recessed below the upper surface. Forming these gates simultaneously reduces the number of processing steps.

FIG.1illustrates a cross-sectional view of an IC device101A including a GAA transistor125A according to some embodiments of the present disclosure. The GAA transistor125A includes a source region118, a loop-shaped gate electrode109A, and a drain region127. The drain region127is outside the loop-shaped gate electrode109A. The source region118is inward of the loop-shaped gate electrode109A. An STI region107, which is also loop-shaped, surrounds the loop-shaped gate electrode109A and is disposed between the loop-shaped gate electrode109A and the drain region127.

A gated path of conduction from the source region118to the drain region127includes a source extension region135, a body region137, and a drift region139. The body region137provides a channel129between a first PN junction128and a second PN junction131. A gate dielectric layer111separates the loop-shaped gate electrode109A from the channel129. The channel129is substantially vertical. The first PN junction128is between the N-doped source extension region135and the P-doped body region137. The second PN junction is between the P-doped body region137and the N-doped drift region139.

The drift region139extends from the channel129to the N+-doped drain region127and includes a portion139A that is directly beneath the body region137, a portion139B that extends underneath the loop-shaped gate electrode109A and the STI region107, and a portion139C that rises outside the loop-shaped gate electrode109A and the STI region107to meet the drain region127. The source extension region135is optional. A body contact region117, which is P+doped, may be butted with the source region118, which is N+doped. The body contact region117communicates with the body region137and therefore the channel129.

The term “loop-shaped” means having a shape that goes all around an interior in the manner of a cylinder. The loop-shaped object separates an interior area from an exterior area. The loop may follow the path of a circle, an oval, a square, a rectangle, a hexagon, any other polygon, or an irregular shape. However, shapes providing an interior aspect ratio near 1:1 (circle or square) provide the best performance. In some embodiments, the interior aspect ratio (maximum distance across the interior to the minimum distance across the interior) is about 5:1 or less. In some embodiment, the interior aspect ratio is about 2:1 or less. In some embodiments, the interior aspect ratio is about 1:1.

FIG.2provides a plan view200illustrating an embodiment in which the loop-shaped gate electrode109A is square-sided. The cross-sectional view ofFIG.1corresponds to the line A-A′ of plan view200. The inner side of the loop-shaped gate electrode109A is the side that comes closest to the channel129(seeFIG.1). The longest distance across the interior is from corner-to-corner in a horizontal cross-section adjacent the channel129. The shortest distance across is from side-to-opposite side. This gives the loop-shaped gate electrode109A in the embodiment of plan view200an aspect ratio of about 1.4 to 1.

FIG.3provides a plan view300illustrating an embodiment in which the loop-shaped gate electrode109A is cylindrical. The plan view300also has a line A-A′ to which the cross-sectional view ofFIG.1may alternately correspond. In the embodiment of plan view300, the inner side of the loop-shaped gate electrode109A is circular and has an aspect ratio of 1:1.

Returning toFIG.1, the body contact region117, the source region118, the source extension region135, the body region137, the drift region139, and the drain region127are all provided by doped areas of a semiconductor substrate143. The semiconductor substrate143includes a buried N-layer145and an upper semiconductor layer147. The upper semiconductor layer147has N-type doping and includes the drift region139. The buried N-layer145separates the upper semiconductor layer147from a bulk region of the semiconductor substrate143which may have p-type doping. It will be appreciated that the doping types of all the structure inFIG.1may be reversed. In addition, the source region118may be operated as a drain and the drain region127may be operated as a source with or without reversing the doping types.

An interlevel dielectric (ILD) layer123above the semiconductor substrate143may contain contact plugs that connect with the electrodes of the GAA transistor125A. These may include a source contact plug115, a gate contact plug113, and a drain contact plug105. The source contact plug115may connect with both the source region118and the body contact region117. The gate contact plug113connects to the loop-shaped gate electrode109A. The drain contact plug105connects with the drain region127.

In some embodiments, a height H1of the STI region107is from about 0.1 μm to about 3 μm. In some embodiments, the height H1is from about 0.3 μm to about 1 μm. Increasing the height H1increases the breakdown voltage of the GAA transistor125A. A height H1of about 0.3 μm or greater may be selected to achieve a breakdown voltage of about 20 V or more. In some embodiments, the width Wi of the STI region107is from about 0.3 μm to about 10 μm. In some embodiments, the width W1is from about 1μm to about 3 μm. Increasing the width W1also increases the breakdown voltage of the GAA transistor125A. A width Wi of about 1 μm or greater may be selected to achieve the breakdown voltage of about 20 V or more.

A height H2of the channel129may be less than the height H1of the STI region107. In some embodiments, the height H2is from about 5% to about 100% the height H1. In some embodiments, the height H2is from about 10% to about 90% the height H1. In some embodiments, the height H2is from about 20% to about 50% the height H1. The height H2affects threshold voltage, resistance, and other characteristics of the GAA transistor125A.

When a higher threshold voltage is desired, it is advantageous to keep the loop-shaped gate electrode109A from descending too far below the second PN junction131. In some embodiments, a height difference H3between the second PN junction131and the bottom of the loop-shaped gate electrode109A is kept small. In some embodiments, the height H3is 40% or less the height H2. In some embodiments, the height H3is 20% or less the height H2.

In order to control the height H3, the loop-shaped gate electrode109A may be shorter than the STI region107and not extend to the bottom of the STI region107. In some embodiments, a height H4of a bottom of the loop-shaped gate electrode109A over a bottom of the STI region107is at least about 10% the height H1of the STI region107. In some embodiments, the height H4is at least about 25% the height H1. In some embodiments, the height H4is at least about 50% the height H1.

The loop-shaped gate electrode109A may have an upper surface121that is recessed below an upper surface119of the semiconductor substrate143. The recess may relate to a processing method that facilitates forming the GAA transistor125A within the parameters of a BCD process.

FIG.4illustrates a cross-sectional view of an IC device101B including a GAA transistor125B according to another embodiment of the present disclosure. The GAA transistor125B does not include a butted source but is otherwise like the GAA transistor125B. The GAA transistor125B is generally a lower voltage device than the GAA transistor125A. For example, the GAA transistor125B may be a 5V transistor and the GAA transistor125A may have a threshold voltage greater than 5V. In some embodiments, the GAA transistor125B include an inner terminal region118B that is configured to operate as a drain and an outer terminal region127B that is configured to operate as a source.

FIG.5illustrates a cross-sectional view of an IC device101C including a GAA transistor125C according to another embodiment of the present disclosure. The GAA transistor125C may be like the GAA transistor125A except that the GAA transistor125C has a loop-shaped gate electrode109C that extends nearly to the bottom of the STI region107. The loop-shaped gate electrode109C is displaced from alignment with the bottom of the STI region107by a width of the gate dielectric layer111.

FIG.6illustrates a cross-sectional view of an IC device101D including a GAA transistor125D according to another embodiment of the present disclosure. The GAA transistor125D may be like the GAA transistor125C except that the GAA transistor125C does not include the STI region107(seeFIG.5). The GAA transistor125D may have a loop-shaped gate electrode109D that is separated from the drain region127by the width of the gate dielectric layer111. The structure of the GAA transistor125D is suitable for a 5V transistor or the like but would generally have a lower threshold voltage than a transistor having the structure of the GAA transistor125A of the GAA transistor125C.

FIG.7illustrates a layout for an IC device101E according to some embodiments of the present disclosure. Any of the IC devices101A-D could have the same layout as the IC device101E. The IC device101E includes a high voltage device area703and a core device area705. The high voltage device area703include high voltages device such as the GAA transistors125A-125D. High voltage devices include 5V transistors and may include higher voltage devices. The core device area includes logic and I/O devices. These may include devices that operate at 3.3V and devices that operate at 1.8V. The high voltage device area703and a core device area705are surrounded by an electrostatic discharge (ESD) protection structure701and are separated by a distance W2, which may be about 1 μm or more.

FIG.8provides a cross-sectional view of an array800of GAA transistors125A that may be in the high voltage device area703of the IC device101E ofFIG.7. As illustrated, adjacent GAA transistors125A may share drain regions127. Sharing drain regions127reduces a pitch of the array800. The array800is surrounded by an isolation structure801.

FIG.9provides a cross-sectional view900of the array800according to an embodiment in which the isolation structure801is provided by a deep trench isolation (DTI) structure901. The cross-sectional view900is taken along the line B-B′ ofFIG.8. As shown inFIG.9, the DTI structure901extends from an upper surface119of the semiconductor substrate143to a depth that is greater than or equal to a depth of the buried N-layer145.

FIG.10provides a cross-sectional view1000of the array800according to an embodiment in which the isolation structure801is provided by diodes including a PN junction1001formed between the upper semiconductor layer147and a bulk region of the semiconductor substrate143. In this example, the buried N-layer145does not extend beyond the array800.

FIGS.11through20are cross-sectional view illustrations exemplifying a method according to the present disclosure of forming a GAA transistor according to the present disclosure. WhileFIGS.11through20are described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS.11through20are not limited to the method but rather may stand alone separate from the method.FIGS.11through20are described as a series of acts. The order of these acts may be altered in other embodiments. WhileFIGS.11through20illustrate and describe a specific set of acts, some may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. While the method ofFIGS.11through20is illustrated forming the GAA transistor125A in the IC device101A ofFIG.1, the method may be used to form other GAA transistors in other IC devices.

As shown by the cross-sectional view1100ofFIG.11, the method may begin with providing the semiconductor substrate143with the buried N-layer145and the upper semiconductor layer147. The semiconductor substrate143may be a bulk semiconductor substrate, an SOI substrate, the like, or some other suitable semiconductor substrate. The upper semiconductor layer147may be an epitaxial layer grown on the semiconductor substrate143. The upper semiconductor layer147and the semiconductor substrate143may each be or comprise silicon, a group III-V semiconductor substrate, some other suitable semiconductor, the like, a combination of the foregoing, or any other suitable semiconductors. A bulk region of the semiconductor substrate143may be lightly p-doped. The upper semiconductor layer147may be lightly n-doped. Lightly doped may be doping to a concentration in the range from 1014/cm3to 1017/cm3. As mentioned previously, the doping types may be reversed.

As shown by the cross-sectional view1200ofFIG.12, the method continues with forming trenches1201. Forming the trenches1201may include forming a mask1203on the upper surface119and etching. The mask1203and other masks shown in the method ofFIGS.11-20may be a photolithographic mask or a hard mask formed using photolithography. The etch process may be a dry etch such as a plasma etch or any other suitable process. As a result of the etch process, sidewalls1205of the trenches1201may form at an angle θ1with respect to a perpendicular (a surface normal) of the upper surface119. After the etch process, the mask1203may be stripped.

As shown by the cross-sectional view1300ofFIG.13, the trenches1201may be filled with dielectric to form STI regions107. The dielectric may be a silicon oxide, the like, or any other suitable dielectric. The dielectric may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), the like, or any other suitable process. After depositing, excess dielectric may be removed by a planarization process. The planarization process may be chemical mechanical polishing (CMP). The STI regions107have sidewalls1301that form the angle θ1with respect to (a surface normal of) the upper surface119.

As shown by the cross-sectional view1400ofFIG.14, a mask1403may be formed and used to etch a trench1401in the STI regions107. The etch process may be an etch that selectively removes the material of the STI regions107without removing the material of the upper semiconductor layer147. The etch may be a wet etch or a dry etch. In some embodiments, the etch is a dry etch. The resulting trench1401may have a first sidewall1405that makes the angle θ1with respect to the upper surface119and a second sidewall1407that forms a second angle θ2with respect to the upper surface119. The angle θ2may be distinct from the angle θ1due to the differences in process and materials. The trench1401surrounds an island1409of semiconductor material.

As shown by the cross-sectional view1500ofFIG.15the trenches1401may be lined with the gate dielectric layer111then filled with conductive material1501. The gate dielectric layer111may be or comprise silicon oxide, a high k dielectric, the like, some other suitable dielectric(s), or any combination of the foregoing. The conductive material1501may be or comprise doped polysilicon, metal, the like, some other suitable conductive material, or a combination of the foregoing. In some embodiments the conductive material1501is doped polysilicon. In some embodiments the conductive material1501comprises a metal and the gate dielectric layer111is a high κ dielectric. In some embodiments, the gate dielectric layer111and the conductive material1501form a high voltage gate stack. In some embodiments, the gate dielectric layer111is formed by oxidation, in which case the gate dielectric layer111forms selectively on exposed surfaces of the upper semiconductor layer147. In some embodiments, the gate dielectric layer111is formed by deposition. The deposition process may be atomic layer deposition (ALD), CVD, PVD, the like, or a combination of the foregoing. The conductive material1501may be deposited or grown. Examples of processes that may be suitable include, ALD, CVD, PVD, electroplating, and electroless plating.

As shown by the cross-sectional view1600ofFIG.16, a process may be carried out to remove portions of the conductive material1501that are outside the area of the trenches1401and define the loop-shaped gate electrode109A from the conductive material1501. The loop-shaped gate electrode109A has a first sidewall1601that forms the angle θ1with respect to the upper surface119and a second sidewall1603that forms the second angle θ2with respect to the upper surface119.

In some embodiments the removal process is CMP, in which case the upper surface121of the loop-shaped gate electrode109A will be approximately flush with the upper surface119. In other embodiment like the one illustrated the process is an etch process. In some of these other embodiments, the etch process is a gate definition process that is carried out with a mask (seeFIGS.21-22, described more fully below) whereby portions of the conductive material1501remain above the upper surface119in locations other than the area shown to provide gates for devices distinct from the GAA transistor125A ofFIG.1or the like. The etch process may remove unmasked portions of the gate dielectric layer111from the upper surface119. In some embodiments, the etch process comprises one or more steps of plasma etching. The etch process leaves the upper surface121recessed below the upper surface119.

As shown by the cross-sectional view1700ofFIG.1700, a mask1701may be formed and ion implantation is carried out to provide p-type doping for the body region137. In some embodiments the doping provides a dopant concentration in the range from 1015/cm3to 1018/cm3. In some embodiments, the ion implantation provides shallow p-wells for bipolar junction transistors in areas that are not shown. In some embodiments, the ion implantation provides deep p-wells for NMOS transistors (not shown) in CMOS structures (not shown) within the core device area705(seeFIG.7). In other embodiments the p-type doping for the body region137is done separately and is tuned for GAA transistors according to the present disclosure.

As shown by the cross-sectional view1800ofFIG.1800, a mask1801may be formed and ion implantation carried out to provide heavy n-type doping for the source region118and the drain region127. In some embodiments, the doping provides a dopant concentration in the range from 1020/cm3or greater. In some embodiments, the ion implantation also provides sources and drains for NMOS transistors (not shown) in the core device area705(seeFIG.7). The source extension region135may be formed by diffusion of dopants from the source region118. Diffusion may be induced by thermal annealing. Alternatively, the source extension region135may be produced by another ion implantation using a higher energy level and a lower amount of dopant.

As shown by the cross-sectional view1900ofFIG.1900, a mask1901may be formed and ion implantation carried out to provide heavy p-type doping for the body contact region117. In some embodiments, the doping provides a dopant concentration in the range from 1020/cm3or greater. In some embodiments, the ion implantation also provides sources and drains for PMOS transistors (not shown) in the core device area705(seeFIG.7). In some embodiments, the ion implantation is tailored specifically to provide desired characteristics for the GAA transistor125A.

As shown by the cross-sectional view2000ofFIG.2000, the ILD layer123may be formed above the semiconductor substrate143followed by formation of a mask2007and using that mask to etch holes2001,2003, and2005through the ILD layer123. The ILD layer123may be silicon oxide, a low k dielectric, the like, or some other suitable dielectric. The ILD layer123may be formed by ALD, CVD, the like, or any other suitable process. In some embodiments, the ILD layer123is formed from tetraethyl orthosilicate (TEOS). The holes2001,2003, and2005may be filled with conductive material followed by planarization to form the source contact plug115, the gate contact plug113, and the drain contact plug105respectively as shown inFIG.1.

FIGS.21and22illustrate an embodiment of the foregoing method. In this embodiment a high voltage gate is formed in a device area2103simultaneously with the formation of the GAA transistor. The cross-sectional view2100ofFIG.21extends the cross-sectional view1500ofFIG.15to show that the gate dielectric layer111and the conductive material1501form a gate stack2101in the device area2103. The cross-sectional view2200ofFIG.22extends the cross-sectional view1600ofFIG.16to show that a mask2203allows the same etch that defines the loop-shaped gate electrode109A from the conductive material1501also defines a gate2201from the gate stack2101.

FIG.23presents a flow chart for a process2300that may be used to form an IC device having a GAA transistor according to the present disclosure. While the process2300ofFIG.23is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts are required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

The process2300may begin with act2301, forming a first loop-shaped trench in a semiconductor. The cross-sectional view1200ofFIG.12provides an example. The trench1201is loop-shaped in the sense that it surrounds an island1207of semiconductor. Loop-shaped is not restricted to any narrow sense of being circular or cylindrical but is meant in the broader sense of being present about a 360 degree perimeter. For example, the STI region107as shown by the plan view ofFIG.2is loop-shaped.

The process continues with act2303, filling the first loop-shaped trench with dielectric to form a loop-shaped STI region. The cross-sectional view1300ofFIG.13provides an example. The process of filling the trench may include both deposition and planarization. Other STI regions that are not loop-shaped may be formed simultaneously with the loop-shaped STI region.

The process continues with act2305, etching a second loop-shaped trench. The second loop-shaped trench is etched out of the loop-shaped STI region. The cross-sectional view1400ofFIG.14provides an example. The island of semiconductor surrounded by the ring-shapes STI region may provide an inner sidewall for the second loop-shaped trench. The inner sidewall of the second loop-shaped trench may have a slope that is a mirror image of a slope in an outer sidewall of the first loop-shaped structure. The STI region may provide an outer sidewall for the second loop-shaped trench. A slope of the outer sidewall of the second loop-shaped trench may be at a distinct angle from that of the inner sidewall of the second loop-shaped trench.

The process continues with act2307, forming a gate stack. The gate stack fills the second loop-shaped trench. The cross-sectional views1500and2100ofFIGS.15and21provide examples. The gate stack includes a gate dielectric layer and a gate electrode layer. In some embodiments, the gate stack is a high k metal (HKMG) gate stack.

The process continues with act2309, etching to define a loop-shaped gate electrode from the ring shaped gate stack. The cross-sectional views1600and2200ofFIGS.16and22provide examples. In some embodiments, the etch process causes the loop-shaped gate electrode to be recessed below an upper surface of the semiconductor substrate. In some embodiments, the etch process is maskless in the area of the GAA transistor. In some embodiments, a mask is formed for the etch process and the etch process defines a gate electrode for a device that has a gate electrode above a surface of the semiconductor substrate.

The process continues with act2311, ion implantation. Ion implantation may include a series of steps. The cross-sectional views1700-1900ofFIGS.17-19provide an example. The ion implantation provides source and drain regions from the GAA transistor. In some embodiments, the ion implantation forms a body contact region that is butted with an inner terminal (source or drain) region for the GAA transistor. In some embodiments, the ion implantation produces a well that provides a channel for the GAA transistor. In some embodiment, one or more of these implants provides wells or contact regions for other high voltage devices including bipolar junction devices. In some embodiment, one or more of these implants provides wells or contact regions for CMOS devices in a core, I/O, or logic region apart from a high voltage region that contains the GAA transistor.

The process continues with act2313, back-end-of-line (BEOL) processing. BEOL processing begins with the formation of contact plugs for the source region, the drain region, and the gate electrode of the GAA transistor. The cross-sectional view2000ofFIG.20together withFIG.1provides an example. BEOL processing forms a metal interconnect over the semiconductor substrate.

Some aspects of the present disclosure relate to an IC device having a transistor. The transistor has a loop-shaped gate electrode, a first source/drain region, a second source/drain region, and a channel that are doped regions of a semiconductor substrate. The loop-shaped gate electrode is separated from the channel by a gate dielectric layer and is below an upper surface of the semiconductor substrate. The channel is surrounded by the loop-shaped gate electrode and the second source/drain region is outside the loop-shaped gate electrode. In some embodiments the loop-shaped gate electrode is inside a loop-shaped STI region.

In some embodiments, the loop-shaped STI region has approximately the same depth as the loop-shaped gate electrode. In other embodiments, the loop-shaped STI region goes deeper than the loop-shaped gate electrode. The some embodiments, the loop-shaped STI region is slanted with an angle that mirrors that of an inner sidewall of the loop-shaped gate electrode. In some embodiments, an inner sidewall of the loop-shaped gate electrode is inclined with respect to a surface normal of the upper surface by a first angle and an outer sidewall of the loop-shaped gate electrode is inclined with respect to the surface normal by a second angle that is distinct from the first angle. In some embodiments, a top of the loop-shaped gate electrode is recessed below a surface of the substrate. In some embodiments, a contact for the body of the transistor is butted with the first source/drain region. In some embodiments, the transistor has a high-k dielectric and a metal gate. In some embodiments, the loop-shaped gate electrode has an inner side with a circular horizontal cross-section. In some embodiments, the loop-shaped gate electrode has an inner side with a rectangular or square horizontal cross-section.

Some aspects of the present disclosure relate to an IC device comprising an STI region and a transistor. The transistor has, an inner terminal region, a channel, an outer terminal region, a gate electrode, and a drift region. The inner terminal region is above the channel and the gate electrode surrounds the channel. The STI region surrounds the gate electrode. The outer terminal region is outside a periphery of the STI region. The drift region begins underneath the channel, goes underneath the STI region, and extends to the outer terminal region. One of the inner terminal region and the outer terminal region is operative as a source, the other as a drain. In some embodiments, the transistor is form directly over a buried N-layer in a semiconductor substrate. In some embodiments the transistor is in an array that is surrounded by a DTI region that extends down to the buried N-layer. In some embodiments, the array N-well that extends from a surface of the semiconductor substrate to the buried N-layer.

Some aspects of the present disclosure relate to a method of forming an IC device comprising a transistor. The method includes forming a loop-shaped shallow trench isolation (STI) region within a semiconductor substrate, etching away a portion of the loop-shaped STI region to form a loop-shaped trench comprising an outer sidewall that is provided by the STI region and an inner sidewall that is provided by the semiconductor substrate, forming a gate oxide on the inner sidewall, filling the trench with a conductive material, doping a portion of the semiconductor substrate that has a first doping type and is disposed within the loop-shaped STI region to form a well having a second doping type, and doping a portion of the semiconductor substrate directly over the well to form a heavily doped region having the first doping type. In some embodiments, the well has a depth that is less than a depth of the STI region. In some embodiments, the conductive material is deposited to fill the trench followed by an etch process that causes the conductive material to be recessed within the loop-shaped trench. In some embodiments, the etch process leave a masked portion of the conductive material to form a gate electrode that is above the surface of the semiconductor substrate.