DIELECTRIC CRACK SUPPRESSION FABRICATION AND SYSTEM

An integrated circuit with a first conductive region, a second conductive region, a plurality of dielectric layers of a first material type between the first conductive region and the second conductive region, and at least one dielectric layer of a second material type, between a first dielectric layer in the plurality of dielectric layers of a first material type and a second dielectric layer in the plurality of dielectric layers of the first material type. Each dielectric layer of a first material type has a thickness in a range from 0.5 μm to 5.0 μm, and the at least one dielectric layer of a second material type is not contacting a metal and has a thickness less than 2.0 μm, and the second material type differs from the first material type in at least one of compression stress or elements in the first material type as compared to elements in the second material type.

CROSS-REFERENCE TO RELATED APPLICATION

Not applicable.

BACKGROUND

The examples relate to semiconductor fabrication, for example with respect to forming relatively thick dielectric structures, such as in integrated circuit (IC) high voltage isolation capacitors and transformers.

Isolation devices in ICs are often constructed from relatively thick dielectric layers, or by a stack of such layers, for example in contemporary processes having total thickness greater than 8 μm. While the total stack thickness typically provides sufficient electrical isolation, the dielectric stack layers typically are deposited with compressive stress that can cause the underlying silicon substrate (wafer) containing the devices to bow or warp excessively, potentially rendering the wafer unable to be processed to completion. To address this, the dielectric deposition process can be modified to reduce the stress of all or some of the dielectric layers in the stack, thereby lowering the overall wafer bow impact. Lower stress dielectric films, however, are more prone to form and propagate cracks during semiconductor wafer processing or die singulation where a rotating diamond embedded saw blade is used to cut through the thick dielectric stack to separate the individual die from the large die array contained within the wafer. Lower stress dielectrics, particularly silicon dioxide, are also more susceptible to moisture absorption, which can degrade the dielectric quality and cause poor high voltage isolation performance.

Accordingly, there may be a need to provide improved thick oxide stacks, and this document provides examples that may improve on certain of the above concepts, as detailed below.

SUMMARY

An integrated circuit is described, comprising a first conductive region, a second conductive region, and a plurality of dielectric layers of a first material type between the first conductive region and the second conductive region. Each dielectric layer of a first material type has a thickness in a range from 0.5 μm to 5.0 μm. The integrated circuit further comprises at least one dielectric layer of a second material type, between a first dielectric layer in the plurality of dielectric layers of a first material type and a second dielectric layer in the plurality of dielectric layers of the first material type and not contacting a metal, wherein the at least one dielectric layer of a second material type has a thickness less than 2.0 μm and wherein the second material type differs from the first material type in at least one of compression stress or elements in the first material type as compared to elements in the second material type.

Other aspects are also described and claimed.

DETAILED DESCRIPTION

FIG.1is a cross-sectional partial view of a semiconductor structure100, in a relatively early fabrication stage. Ultimately, the semiconductor structure100will provide one or more thick dielectric stacks, for example of 8 μm or more, in an IC die. As one example, the IC die may provide an isolation capacitor, as may be used in a high voltage application. As another example, the IC die may provide a transformer. These may be standalone components or either may be in larger functional ICs. Additionally, each may be singularly packaged or combined with one or more other die within a package, forming for example a multi-chip module (MCM) and/or a small outline IC (SOIC). Still further, examples are provided with dielectric stack improvement, as may be implemented at one or more levels in an IC, for example between the semiconductor substrate and a first metal layer (sometimes referred to as M1 or metal-1), and/or between higher metal layers (e.g., between metal-1 and metal-2, or higher).

The semiconductor structure100includes a semiconductor substrate102, for example formed of silicon. For sake ofFIG.1and later figures, x-z coordinate dimensions are also illustrated, with the x-dimension generally considered horizontal and the z-dimension generally considered vertical. The directional references are for purposes of relative placement, but such terms are not intended to be restrictive as the device may be rotated in space and thereby change absolute, but not relative, references. A first pre-metal dielectric (PMD) layer104is formed adjacent the semiconductor substrate102, whereFIG.1and later figures show the device as vertical and with generally horizontal layering, so the first PMD layer104is illustrated above, and in contact with, the semiconductor substrate102. In an example, the first PMD layer104is a plasma enhanced chemically vapor deposited (PECVD) oxide formed from a tetraethyl orthosilicate (TEOS) precursor, hereafter referred to simply as TEOS. The TEOS may be low stress, having a compressive stress between −10 and −80 MPa (e.g., −20 MPa). The use of low stress material may be preferred, particularly where TEOS or other dielectrics are implemented in relatively thick layers (or serve as layers that combine to form a stack), as thick, higher compressive stress layers, can create undesirable levels of wafer bow, which exceed the limits that can be tolerated by typical wafer fabrication processing equipment. The first PMD layer104thickness, shown inFIG.1and later figures in the z-dimension, may vary, for example in the range of 0.5 μm to 5.0 μm thick (e.g., 3 μm). Notably, the thickness of the first PMD layer104, as well as its stress, could cause cracks to form in the layer, that is, a relatively thin stack can crack, even at relatively lower stress. Responsive to these considerations, a first thin intermediate dielectric layer106is formed above and in contact with the first PMD layer104. In an example, the thin intermediate dielectric layer106is silicon oxynitride, having the form of SiOaNb, where a=b or where both a and b can be unequal to one another, and where each of a and b is in a range from 2.0 to 3.6. Varying a and b allows different examples with respective tuning of material properties, including the compressive strength of the silicon oxynitride. Further in an example, the processing parameters (e.g., radio frequency, bias conditions, pressure) may be adjusted to tune the compressive stress of the SiOaNbof the thin intermediate dielectric layer106to be in the range of 0 MPa to −170 MPa. The thickness of the first thin intermediate dielectric layer106may vary, for example in the range of 0.1 and 0.5 μm thick (e.g., 0.3 μm). The thickness of the thin intermediate dielectric layer106can be approximately 5% to 20% (e.g., 10%) of the thickness of the first PMD layer104. Additionally or alternatively, the thickness of the thin intermediate dielectric layer106can be chosen in absolute terms, rather than relative to the thicker PMD layer, in all events such that the composition of the bulk of the dielectric stack, that includes both the first PMD layer104and the first thin intermediate dielectric layer106, is nearer to that of the first PMD layer104, in order to avoid any material change to the electrical performance of the stack, for example to avoid affecting leakage, capacitance, breakdown, and the like.

FIG.2is a cross-sectional partial view of theFIG.1semiconductor structure100, following additional fabrication. A second PMD layer108is formed above the first thin intermediate dielectric layer106. In an example, the second PMD layer108is of the same material (TEOS), and also may be of the low compressive stress, and thickness (e.g., 3 μm), of the first PMD layer104. Further, whileFIG.2(and others) show only a limited amount of the horizontal space of the stack, or just the stack alone but not other components affixed to or within the semiconductor substrate102, note in an example that across the entirety of the structure, including potentially beyond that which is shown, the thin intermediate dielectric layer106does not physically contact any metal, in the z-dimension either above or below those layers, for example by contacting a horizontal metal layer, or in the x-dimension laterally, for example by contacting a vertical metal via or contact. A second thin intermediate dielectric layer110is formed above the second PMD layer108. In an example, the second thin intermediate dielectric layer110is of the same material (SiOaNb), and may be of the same compressive stress and thickness (e.g., 0.3 μm), as the first thin intermediate dielectric layer106. In an example, the second thin intermediate dielectric layer110also does not physically contact metal, in either the x-dimension or the z-dimension.

Continuing inFIG.2, the same pairing of PMD layer and thin dielectric layer is again repeated above and adjacent the preceding structure. Specifically, a third PMD layer112is formed above and in contact with the second thin intermediate dielectric layer110. In an example, the third PMD layer112is of the same material (TEOS), and also may be the same compressive stress and thickness (e.g., 3 μm), as the first PMD layer104. A third thin intermediate dielectric layer114is formed above and in contact with the third PMD layer112. In an example, the third thin intermediate dielectric layer114is of the same material (SiOaNb), and may be of the same compressive stress and thickness (e.g., 0.3 μm), as the first thin intermediate dielectric layer106. Additionally, the third thin dielectric layer114, again across the entirety of the structure including beyond that which is shown does not physically contact any metal, in either the z-dimension or the x-dimension.

FIG.3is a cross-sectional partial view of theFIG.2semiconductor structure100, following additional fabrication. A fourth PMD layer116is formed above and in contact with the third thin intermediate dielectric layer114. In an example, the fourth PMD layer116is of the same material (TEOS), and also may be the same compressive stress, as the first PMD layer104, but it may be of a lesser thickness, for example a thickness of 2 μm. Accordingly, at this point, a person of skill in the art will appreciate that for each of the first, second, and third thin intermediate dielectric layers106,110, and114, it physically abuts a first and second dielectric (e.g., PMD) layer, where the first and second dielectric layer is of a same material, or includes the same elements (e.g., silicon, oxygen, carbon and hydrogen, such as in TEOS; silicon and oxide, such as in silicon dioxide; carbon, silicon, oxygen, and fluorine, such as in organosilicon), where in examples those elements do not include nitrogen, and at least one of the first and second dielectric layers has a thickness of at least 2 μm, while the other dielectric layer has a thickness of 0.5 μm or greater, so that combined the two dielectric layer have a thickness of 2.5 μm or greater. Accordingly, in each instance, the thin intermediate dielectric layer separates what otherwise could be a continuous stack of dielectric of those first and second dielectric layers. As further discussed later, the inclusion of any of the thin intermediate dielectric layers106,110, and114(and others, discussed later) reduces the possibility of cracking through a combined thickness of the layer above and below it, or of the combined thickness of all of the PMD layers, as each thin intermediate dielectric layer serves also as a crack stop, as between otherwise adjacent thicker (e.g., TEOS) layers.

CompletingFIG.3, other aspects are shown as an example of an implemented device. For example, a fourth thin intermediate dielectric layer118may be formed above and in contact with the fourth PMD layer116. In an example, the fourth thin intermediate dielectric layer118is of the same material (SiOaNb), and may be of the same compressive stress and thickness (e.g., 0.3 μm), as the first thin intermediate dielectric layer106. A first silicon nitride (SiN) layer120, which in an alternative example may be TEOS, is formed above and in contact with the fourth thin intermediate dielectric layer118. While four thin intermediate layers and four PMD layers are shown, the number of thin intermediate layers may be as few as one or greater than four. For example, a thin intermediate layer may be located for every 0.5 to 3.0 μm of PMD layer thickness. In an example, the first SiN layer120may have a thickness of 0.65 μm, and can provide benefits in connection with electric fields, particularly near corners, of nearby metals. Additionally, a first metal layer122(e.g., M1 or metal-1) is formed above and in contact with the first SiN layer120. In an example, the first metal layer122may be formed by depositing or sputtering, patterning, and an etching a metal layer (e.g., aluminum), and with the resultant metal layer thickness in a range from 0.5 μm to 3.0 μm. Given the preceding, the layers between the first metal layer122and the substrate102cumulatively provide a dielectric thickness of over 11.0 μm, which reduces the impact of parasitic capacitance occurring between the first metal layer122and a conductive region (including a charged region) of the substrate102. Lastly inFIG.3, a first high stress TEOS layer124is formed above and preferably conforming to and covering the top corners and sidewalls of the first metal layer122. The first high stress TEOS layer124may have a compressive stress between −80 and −150 MPa (e.g., −120 MPa). High stress TEOS used in this manner reduces the amount of moisture absorption into the film adjacent the metal layer122, thereby mitigating potential problems (e.g., high voltage failures) that otherwise might arise from elevated moisture levels. In an example, the first high stress TEOS layer124has a thickness between 0.5 μm and 3.0 μm (e.g., 1.0 μm). In alternate examples, the first high stress TEOS layer124can be a layer of high density plasma (HDP) oxide, which also has high compressive stress.

FIG.4is a cross-sectional partial view of theFIG.3semiconductor structure100, following additional fabrication. Particularly, above the first high stress TEOS layer124, a second stack of thick insulation is formed, again including alternating layers of low stress TEOS separated by a thinner nitrogen-containing layer (e.g., SiOaNb). Specifically, a first inter-level dielectric (ILD) layer126is formed above and in contact with the first high stress TEOS layer124. In an example, the first ILD layer126is of the same material (TEOS), low compressive stress, and thickness (e.g., 3.0 μm) as the first PMD layer104. A fifth thin intermediate dielectric layer128is formed above and in contact with the first ILD layer126. In an example, the fifth thin intermediate dielectric layer128is of the same material (SiOaNb), compressive stress, and thickness (e.g., 0.3 μm) as the first thin intermediate dielectric layer106. Further, a second ILD layer130is formed above and in contact with the fifth thin intermediate dielectric layer128. In an example, the second ILD layer126is of the same material (TEOS), and may be of the same low compressive stress and thickness (e.g., 3.0 μm), as the first PMD layer104. A sixth thin intermediate dielectric layer132may be formed above and in contact with the second ILD layer130. In an example, the sixth thin intermediate dielectric layer132is of the same material (SiOaNb), compressive stress, and thickness (e.g., 0.3 μm) as the first thin intermediate dielectric layer106. While two ILD layers and two thin intermediate dielectric layers are shown, additional iterations of an ILD layer and a thin intermediate dielectric layer may also be formed.

Continuing inFIG.4, a second SiN layer134, which in an alternative example is TEOS, is formed above and in contact with the sixth thin intermediate dielectric layer132. In an example, the second SiN layer134, like the first SiN layer124, may have a thickness of 0.65 μm. A second metal layer136(sometimes referred to as M2 or metal-2 in a standalone device, but could be higher metal layer in an IC with functional circuitry) is formed above and in contact with the second SiN layer134. In an example, the second metal layer136may be formed in a same manner as the first metal layer122, and with the resultant metal layer thickness of up to 3.0 μm. Accordingly, the layers between the second metal layer136and the first metal layer122, excluding the second SiN layer134, cumulatively provide a dielectric thickness of approximately 8.3 μm, to create a galvanic high voltage isolation capacitor between the second metal layer136and the first metal layer122. Further, the inclusion of the thin intermediate dielectric layers128and132also reduces the possibility of cracking through the entire thickness, as each thin intermediate dielectric layer serves also as a crack stop, as between otherwise adjacent thicker (e.g., TEOS) layers. Also inFIG.4, a second high stress TEOS or high density plasma (HDP) oxide layer138is formed above and preferably conforming to and covering the top corners and sidewalls of the second metal layer136. The second high stress TEOS or HDP oxide layer138may be thicker than (e.g., 1.4 μm), but may have a same compressive stress as, the first high stress TEOS layer124, reducing the amount of moisture accumulation in the film directly adjacent to the second metal layer136. An additional protective oxide or overcoating may be formed above the second high stress TEOS layer138, for example with a layer140of low stress SiOaNb. While not shown, an opening also may be formed through the layer140and the TEOS layer138, so as to provide electrical contact to the second metal layer136. Alternatively, the second metal layer136, and also the semiconductor substrate102, may be left floating, where the semiconductor structure100provides a capacitively coupled high voltage capacitor; additional details in this regard are shown in co-owned U.S. patent application Ser. No. 16/435,095, filed Jun. 7, 2019 and published as U.S. Patent Publication 20190378892 on Dec. 12, 2019, which is hereby fully incorporated herein by reference.

Given the preceding,FIG.4further identifies that the semiconductor structure100includes generally a first dielectric stack142between two conductive regions, with theFIG.4example conductive regions being the first metal layer122and the semiconductor substrate102(including a charged portion thereof), and a second dielectric stack144between two conductive regions, with theFIG.4example conductive regions being the second metal layer136and the first metal layer122. In alternative examples, one or both of stacks142and144may be included. Each respective stack142and144includes plural thicker layers of a first dielectric type and between those thicker layers is an adjacent (e.g., physically abutting) thinner layer of a second dielectric type. Accordingly, within each stack142and144, the included thinner and different dielectric creates a dielectric dissimilar interface, which provides a stop to cracks that otherwise may occur (e.g., vertically in the orientation shown) through thicker dielectric layers. In an example, the inclusion of nitrogen in the thinner dielectric, for example in the form of SiOaNb, may reduce moisture presence in that material and accordingly at its interface with the abutting thicker low stress TEOS layer. Reducing moisture likewise may reduce crack propagation in the same area, so accordingly the interface reduces the risk of vertical crack propagation in the stack (either142or144), while also facilitating sufficient electrical isolation. Further, in an alternative example, the dissimilar interface might be provided by an alternative combination of materials for the thicker (PMD or ILD) layer versus the thinner intermediate layer. As an example, again using low compressive stress TEOS for the thicker layers as shown theFIGS.1-4, a high stress (e.g.,−80 MPa<stress<−170 MPa) TEOS may be used for the thinner intermediate layers. While the high stress TEOS does not include nitrogen, the higher stress nature creates an interface with the lower stress thicker TEOS which may serve to inhibit cracks or at least stop them from extending a distance greater than the thickness of the thicker low stress TEOS (e.g., 2.0 to 5.0 μm).

FIG.5is a simplified illustration of a wafer assembly500, including a plural number (e.g., four) of the semiconductor structures100on the substrate102. To the left and right of each individual semiconductor structure100, a cut line502is shown. Each cut line502represents a position where a cut is made, typically using a specialized mechanical saw and saw blade, to separate (singulate) each individual semiconductor structure100from the other(s), once all fabrication steps are complete. Each then-singulated semiconductor structure100provides a separate IC die, which may be packaged alone or in combination with one or more other IC die. For sake of simplification,FIG.5illustrates the area around each cut line502as vacant, but in actuality that area may be filled with other materials, including for example isolation oxides, polyimide, and/or lateral extensions of the layers of each semiconductor structure100. Prior to singulation, the wafer assembly500may be scribed in the area of each cut line502, to reduce the probability of cracks forming in any of the semiconductor structures100during subsequent sawing or cutting. The scribe can form a trench, for example in any overlying protective dielectric layer (not separately shown). Thereafter, the cutting saw or the like is advanced in the trench and along the cut line502.

The above-described cutting is one of various potential causes of cracks through the thick oxides of any of the semiconductor structures100. Indeed, in some prior art IC die, the die components may include a so-called scribe seal, or multiple scribe seals, which are typically formed of metal stacks that span most or all of the layer stack and are included around the die edge periphery. For example, the scribe seal may span between successive metal and tungsten (W) via layers (e.g., metal-1 to metal-2, or so forth). Accordingly, the metal stack also can serve a conductive path purpose between different metal layers within each IC die. Examples of such scribe seals may be found in co-owned U.S. Pat. No. 11,069,627, issued Jun. 20, 2021, which is hereby fully incorporated herein by reference. Additionally, the metal and W-via scribe seal adds crack propagation protection, for example as against lateral cracks that may otherwise occur between die components during saw for singulation. In contrast, the wafer assembly500is without such metal and W-via scribe seal stacks, for example where each of the semiconductor structures100is of a particular device type, such as theFIG.1-4isolation capacitor, and so that inter-metal layer connections are not implemented. Accordingly, in the examples illustrated, the scribe area does not include metal, so that none of the thin intermediate dielectric layers contacts a metal. Accordingly, the crack inhibiting features obtained from the above-described combination of layers may be exceedingly beneficial, for examples that do not include the augmentation of metal scribe seals. Moreover, the inclusion of crack inhibiting features may reduce cracks arising from other fabrication considerations. For example, cracks also might occur during fabrication processing when particles that fall on the wafer become embedded under thick dielectrics and create nucleation sites for crack propagation. The example inclusion of thinner layers also can inhibit cracks generated from such fall-on particles, or potentially other crack causes incurred in normal fabrication processing.

Additional alternative examples include variations in the materials, and layering, that may be used as a substitute for various above-described thin intermediate dielectric layers (e.g.,106,110,114, and so forth). In one example, the value of a in SiOaNbis reduced to zero, so that one or more of the thin intermediate dielectric layers is formed from SiN (silicon nitride). In another example, the thin intermediate dielectric layer does not contact any conductive or semiconductor material (e.g., the thin intermediate dielectric layer contacts only other dielectric material). In another example, the thin intermediate dielectric layer is formed from an alternative dielectric, including an insulator that does not include nitrogen, for example as either aluminum oxide or titanium oxide. In still another example, the thin intermediate dielectric layer may be implemented as a stack that includes plural layers. For example,FIG.6is a cross-sectional view of an alternative thin intermediate dielectric layer600, again as may be used as a substitute for the first thin intermediate dielectric layer106(and/or for others, such as110,114, etc.). The alternative thin intermediate dielectric layer600is a multi-layered structure, including a first layer602, a second layer604, and a third layer606, each of a material consistent with other thin intermediate dielectric layers described herein, and with the total thickness of the multi-layered structure also being in the range of 0.1 and 0.5 μm thick (e.g., 0.3 μm). For example, each of the first, second, and third layers602,604, and606may be 0.1 μm thick, so that in total the first alternative thin intermediate dielectric layer600is 0.3 μm thick. Further, in one example, the material of the first layer602and the third layer606may be the same, while the material of the second layer604, between the first and third layers602and606, is different. For example, the first and third layers602and606may be silicon oxynitride, while the second layer is silicon nitride, in which case all such layers include nitride. With this material selection, the outer material-to-material interface between the first alternative thin intermediate dielectric layer600and an abutting thicker dielectric layer (e.g., the first and second PMD layers104and108), is the same both above and below the first alternative thin intermediate dielectric layer600, for example with the interface having silicon oxynitride abutting TEOS. As still another alternative, the thin intermediate dielectric layer600can remain a multi-layered structure, including only two of the three-illustrated layers of the first layer602, the second layer604, and the third layer606, again with a combined thickness being in the range of 0.1 and 0.5 μm thick (e.g., 0.3 μm), for example with each layer including nitrogen, but one of the two layers having otherwise some different element(s). For example, a first of the two layers could be silicon oxynitride, while a second of the two layers is silicon nitride.

FIG.7is a cross-sectional view of an IC transformer700that implements crack suppression consistent with portions of the above description. The IC transformer700is constructed with a semiconductor substrate702, for example formed of silicon. A first PMD layer704is formed adjacent the semiconductor substrate702, where the first PMD layer may be TEOS, and of a low compressive stress between −10 and −80 MPa (e.g., −20 MPa). A first metal layer706(M1 or metal-1) is formed above and in contact with the first PMD layer704, which may be aluminum and with a thickness in the range of 0.3 μm and 0.7 μm (e.g., 0.5 μm). A first ILD layer708is formed above the first PMD layer704and also extending above the first metal layer706. In a second metal layer (M2), a first coil structure710and a first contact pad712are formed. The coil structure710may be, for example, a figure-8 coil, which is not shown in detail so as to simplify the drawing, but which generally includes a first winding shown in part inFIG.7as the first coil structure710, and with a spiral surrounding a first contact, a second winding with a spiral surrounding a second contact, and a conductor connecting the first and second winding. A portion of the first coil structure710may be connected to the first metal layer706by a first metal via714, and the first contact pad712also may be connected to the first metal layer706by a second metal via716. The transformer700also includes a second coil structure718, formed higher in the z-dimension, for example as part of a third metal layer (M3), the third metal layer also including a second contact pad720, with an electrical connection722, shown by a dashed line inFIG.7rather than expressly showing a conductor, connecting the second contact pad720to the second coil structure718. The second coil structure718also may be a figure 8-coil, with a spiral surrounding a first contact, a second winding with a spiral surrounding a second contact, and a conductor connecting the first and second winding.

An ILD layer stack724is formed generally between the first coil structure710and the second coil structure718, thereby forming an insulator through which a magnetic field may be coupled between the two coil structures710and718, and whereby the voltage difference between the two coil structures710and718can be large (e.g., 1,000 volts or higher). The ILD layer stack724includes plural layers, collectively having a thickness in a range from 16.0 μm to 20.0 μm. Within the ILD layer stack724may be an etch stop dielectric layer726, so that a tapered edge728can be edged proximate a portion of the transformer700, while stopping on the etch stop dielectric layer726, for example without, or before, reaching the first contact pad712. The ILD layer stack724also may include one or more layered combinations, as in the case of the above-described semiconductor structure100, of relatively thicker dielectric layers (e.g., TEOS) separated by a thinner, for example nitrogen-containing, dielectric layer; a first example of this combination is shown in the z-dimension above the etch stop dielectric layer726, where there is shown a first TEOS layer730above the etch stop dielectric layer726, a first relatively thin nitrogen-containing layer732above the first TEOS layer730, and a second TEOS layer734above the first relatively thin nitrogen-containing layer730. The relatively thicker first and second TEOS layers730and734may have a thickness in the range of 0.5 μm to 5.0 μm, with one of the layers being 0.5 μm or greater, and the other being 2.0 μm or greater, while the relatively thin nitrogen-containing layer730has a thickness in the range of 0.1 μm to 0.5 μm. Additionally, the relatively thin nitrogen-containing layer730does not contact metal (e.g., in either the z-dimension or the x-dimension). The ILD layer stack724includes a second example of the same combination, namely, the second TEOS layer734, above which is formed a thinner nitrogen-containing layer736that does not contact metal, above which is formed a thicker third TEOS layer738, where again the relatively thicker second and third TEOS layers734and738may have a thickness in the range of 0.5 μm to 5.0 μm, with one of the layers being 0.5 μm or greater, and the other being 2.0 μm or greater. Finally, the ILD layer stack724may include an additional layer (or layers)740, between the third TEOS layer738and both the second coil structure718and the second contact pad720.

Given the preceding, the transformer700benefits from a relatively thick dielectric, here in the form of the ILD layer stack724, with that stack providing the desirable dielectric function (here, a medium to separate magnetically coupled inductor coils) while also including crack mitigation in the stack. Crack mitigation is implemented by dividing or implementing the dielectric stack using plural layers, including within those layers one or more material-differentiating and relatively thin (e.g., nitrogen-containing) layers. Additionally, while not shown, a person of skill in the art will appreciate that the transformer700may include other layers, such as protective oxide or overcoat insulators and elements, such as electrical connection through solder ball and bond wires.

From the above, one skilled in the art should appreciate that examples are provided for IC semiconductor fabrication, for example with respect to improving thick dielectric stacks. Such examples provide various benefits, some of which are described above and including still others. For example, layer thickness may vary, and layer position, while shown as directly contacting in various example examples, may be separated in some instances by additional materials. As a final example, additional modifications are possible in the described examples, and other examples are possible, within the scope of the following claims.