INTEGRATED CIRCUIT PACKAGE WITH AN INTERPOSER FORMED FROM A REUSABLE CARRIER SUBSTRATE

An integrated circuit package includes an interposer and an integrated circuit die. The interposer is formed from a layer of semiconductor material that is separated from a bulk portion of a semiconductor substrate, and the integrated circuit die is coupled to the interposer. Vias in the interposer can be formed in the thin layer of semiconductor material removed from the semiconductor substrate, and therefore can be scaled down significantly in size. Such reduced-size, through-interposer vias can be etched and filled much more cost-effectively and result in greatly reduced parasitic capacitance in the integrated circuit package.

DETAILED DESCRIPTION

FIG. 1is a schematic cross-sectional view of a IC package100, arranged according to one embodiment of the invention. IC package100includes integrated circuit (IC) chips101and102coupled to an interposer120, a packaging substrate130, and an over-molding140formed over IC chips101and102. IC package100is configured to electrically and mechanically connect IC chips101,102, and any other logic or memory ICs coupled to interposer120to a printed circuit board or other mounting substrate (not shown) external to IC package100. In addition, IC package100protects IC chips101and102from ambient moisture and other contamination and minimizes mechanical shock and stress thereon.

Each of IC chips101and102may be a semiconductor die singulated from a separately processed semiconductor substrate, such as a central processing unit (CPU), a graphics processing unit (GPU), an application processor or other logic device, a memory chip, a global positioning system (GPS) chip, a radio frequency (RF) transceiver chip, a Wi-Fi chip, a system-on-chip, or any other semiconductor chip that is suitable for mounting on interposer120. Thus, IC chips101and102may include any IC chips that may benefit from being assembled together in a single microelectronic package. Moreover, inFIG. 1, IC package100is shown with two IC chips, but in other embodiments IC package100may be configured with more or fewer IC chips. Thus, in some embodiments, IC package100may be configured as a system-on-chip and may include a heterogeneous assortment of IC chips.

In some embodiments, IC chip101may be logic chip, such as a CPU or GPU, and IC chip102may be a memory chip associated with IC chip101. IC chips101and102may be coupled to interposer120using solder microbumps or any other technically feasible approach. In some embodiments, an underfill material129is used to protect the electrical connections between IC chips101and102and interposer120, and in other embodiments, underfill material129is not used. InFIG. 1, IC chip101is depicted with underfill material129and IC chip102is depicted without underfill material129.

IC chips101and102are electrically connected or otherwise coupled to each other with electrical interconnects formed in an interconnect layer121formed on interposer120. The electrical interconnects of interconnect layer121are configured to electrically connect or otherwise couple IC chips101and102to each other and to through-interposer vias122, which are formed in interposer120and are described below. These electrical interconnects may include ground, power, and signal connections to each of IC chips101and102, and can be formed on interposer120using various wafer-level deposition, patterning, and etching processes, i.e., processes that are performed on a complete semiconductor wafer or other substrate. In this way, interconnect layer121can be formed simultaneously on a complete semiconductor substrate for a plurality of IC packages, and the semiconductor substrate is subsequently singulated into individual interposer elements, such as interposer120, with interconnect layer121already formed thereon. IC package100may be formed using one such singulated interposer element.

In some embodiments, the electrical interconnects of interconnect layer121are formed using one or more deposition, patterning, and etching techniques used for forming the interconnects between the transistors of an integrated circuit formed on a semiconductor substrate. Thus, in such embodiments, interconnect layer121may include one or more levels of electrical interconnects, such as electroplated copper (Cu) or sputtered aluminum (Al), that are formed in alternating layers of a non-organic dielectric material, such as silicon dioxide. Interconnect layer121may further include a final passivation layer for protecting the top layer of electrical interconnects, and may be bumped with a conductive material, such as solder, for making electrical connections directly to IC chips101and102. Interconnect layer121and through-interposer vias122effectively provide very short electrical connections between IC chips101and102and to an external packaging substrate.

Interposer120includes an intermediate semiconductor layer or structure that provides electrical connections between IC chips101and102, any other IC chips mounted on interposer120, and any technically feasible mounting substrate. For example, the mounting substrate may be a packaging substrate included in IC package100, such as packaging substrate130, or a printed circuit board external to IC package100. Generally, interposer120may be electrically coupled to mounting substrate130with through-interposer vias122using any technically feasible electrical connection known in the art, including a ball-grid array (BGA), a pin-grid array (PGA), and the like.

According to embodiments of the invention, interposer120is formed from a layer of semiconductor material that has been removed from a semiconductor substrate, such as an interposer carrier substrate. A process by which interposer120is formed from such a substrate is described below in conjunction with FIGS.2and3A-3I. In some embodiments, interposer120is a monocrystalline silicon material removed from a silicon substrate. In other embodiments, interposer120may be a layer of any semiconductor material that can be removed from a semiconductor substrate, including germanium, gallium arsenide, silicon carbide, silicon-germanium alloys, and the like.

Interposer120is formed from a layer of semiconductor material that is separated from a substrate rather than by grinding down a semiconductor substrate to a targeted thickness via a thinning process. Consequently, interposer120can be much thinner than a silicon interposer formed by such a thinning process. This is because a cleave plane can be formed in a semiconductor substrate at a precisely controlled depth, the depth of the cleave plane defining the thickness of the layer of semiconductor material removed from the substrate and therefore the thickness of interposer120. Thus, a thickness125of interposer120can be selected to be as thin as one micron, or one hundred nanometers, or even less. A process by which such a cleave plane can be formed in a semiconductor substrate at a precisely controlled depth is described below in conjunction withFIG. 2andFIGS. 3A-3I.

In contrast, the formation of a silicon interposer by thinning a silicon substrate generally involves thinning the silicon substrate from a starting thickness of 750 to 800 microns down to a final thickness of about 50 to 100 microns, the thinning process ultimately exposing the through-silicon vias formed therein so that a conductive pathway is provided entirely through the silicon interposer. Thinning of a silicon substrate to less than 50 microns is problematic, since the substrate can be easily cracked during thinning and subsequent handling.

The difficulties associated with precisely thinning a silicon substrate down to a thickness of 100 microns or less are manifold. First, the thinning process is time-consuming and costly, typically involving multiple steps, including grinding, chemical-mechanical polishing, and silicon etching. Second, the thinning process is difficult to control, since the actual thickness of the silicon substrate is difficult to determine accurately while material is being removed therefrom. Third, handling silicon substrates thinned to 100 microns or less without cracking the substrate is challenging. Consequently, the silicon substrate being thinned usually undergoes the additional process steps of bonding to a silicon or glass carrier prior to thinning and debonding from the carrier after thinning, the carrier being used as a mechanism for handling the substrate. Furthermore, even when the silicon interposer is successfully thinned and de-bonded from the carrier without damage, the final thickness of the silicon interposer is generally much thicker than a layer of semiconductor material separated at a cleave plane from a semiconductor substrate. For example, a layer of semiconductor material removed from a semiconductor substrate at a cleave plane can have a thickness of one micron or less, which is one or more orders of magnitude thinner than a silicon substrate thinned down to 50 to 100 microns.

Through-interposer vias122are microvias formed through interposer120, and may be configured to electrically couple IC chips101and102to a packaging substrate included in IC package100or to a printed circuit board external to IC package100. Thus, rather than being 50 to 100 microns deep and having a diameter of 5-10 microns, which is typical for through-silicon vias formed in a silicon interposer formed by a thinning process, through-interposer vias122may be from 10 nm to 1 micron in diameter. Consequently, through-interposer vias122can be formed in interposer120using standard integrated circuit fabrication processes, including the patterning, etching, and filling processes used to form submicron interconnects in an integrated circuit. For example, in some embodiments, a typical process for forming a contact in an integrated circuit may be used to form through-interposer vias122, which is a well-known, easily controlled, and reliable process.

Because thickness125can be 10 microns, 1 micron, or less, openings for through-interposer vias122can be formed quickly in interposer120. Furthermore, because the aspect ratio of these openings can be selected to be relatively low, for example less than about 10:1, these openings can be filled quickly and reliably, for example, with aluminum, copper, tungsten (W), and the like. Moreover, the volume of each of through-interposer vias122is advantageously much less than the typical volume of through-silicon vias formed in a silicon interposer formed by a thinning process. For example, when interposer120has a thickness125of 100 nm, a through-interposer via122with a diameter of 100 nm has a volume that is approximately ten million time less than that of a through-silicon via having a diameter of 10 microns and a depth of 100 microns. Less conductive material in through-interposer vias122results in less parasitic capacitance during operation of IC chips101and102. In addition, less volume of conductive material in through-interposer vias122results in less stresses in IC package100caused by thermal mismatch between the conductive material and interposer120. Thus, in some embodiments, IC package100can be configured without exclusion zones for through-interposer vias122. In other words, through-interposer vias122can be positioned very close to transistors and other semiconductor devices in IC package100without significantly affecting the performance of these semiconductor devices.

Packaging substrate130can be a rigid and thermally insulating substrate on which interposer120is mounted and provides IC package100with structural rigidity. Electrical connections133provide electrical connections between interposer120and packaging substrate130, and may be any technically feasible electrical connection known in the art, for example C4 bumps formed on either substrate120or packaging substrate130. In some embodiments, packaging substrate130is a laminate substrate and is composed of a stack of insulative layers or laminates that are built up on the top and bottom surfaces of a core layer. Packaging substrate130also provides an electrical interface for routing input and output signals and power between IC chips101and102and electrical connections131. Electrical connections131provide electrical connections between IC package100and a printed circuit board or other mounting substrate external to IC package100. Electrical connections131may be any technically feasible chip package electrical connection known in the art, including a ball-grid array (BGA), a pin-grid array (PGA), and the like. Packaging substrate also includes vias and interconnects132that route input and output signals and power between electrical connections131and electrical connections133.

Overmolding140is formed on interposer120and encapsulates IC chips101and102. Overmolding140may be an injection-molded component formed from a mold compound using an injection molding process. The material of overmolding140is selected to protect IC chips101and102from mechanical damage, exposure to moisture, and other ambient contamination. Overmolding140can also act as a stiffener to reduce warpage. In some embodiments, overmolding140can be configured so that IC chips101and102are not covered, in order to add a heatsink or heatspreader directly to IC chips101and/or102for effective heat removal. Alternatively, overmolding140can be planarized using a chemical-mechanical polishing process to remove molding material covering IC chips101and102and facilitate the addition of a heatsink or heatspreader directly to IC chips101and/or102for effective heat removal.

FIG. 2sets forth a flowchart of method steps for forming an integrated circuit package, according to an embodiment of the invention. Although the method steps are described with respect to IC package100ofFIG. 1, persons skilled in the art will understand that performing the method steps, in any order, to form other configurations of IC package is within the scope of the invention.FIGS. 3A-3Isequentially illustrate the results of steps201-210ofFIG. 2.

The method200begins at step201, where an oxide layer301is formed on a top surface305of a semiconductor substrate320, such as a wafer formed from silicon, germanium, gallium arsenide, silicon carbide, a silicon-germanium alloy, etc. In some embodiments, semiconductor substrate320is formed as a monocrystalline semiconductor material. Oxide layer301may be formed by a deposition process, such as chemical vapor deposition, or by an oxidation process, in which semiconductor substrate320is exposed to an oxygen-containing gas or vapor at an elevated temperature and oxide layer301is formed from the material of semiconductor substrate320. Oxide layer301can act as an ion implant mask and has a thickness302that is selected to prevent channeling of implantation ions in semiconductor substrate320during an ion implantation process, i.e., the traveling of implantation ions along grain boundaries of semiconductor substrate320to an unwanted depth. In some embodiments, thickness302is selected based on ion implantation parameters such as implantation energy, what ions310are implanted into semiconductor substrate320, and the material of oxide layer301.

In step202, ions310are implanted into semiconductor substrate320through oxide layer301and top surface305to form a cleave plane303at a depth304in semiconductor substrate320. Cleave plane303is a weakened interface layer in semiconductor substrate320that is substantially parallel to top surface305and can be used to separate a top layer321from semiconductor substrate320in a subsequent process step, e.g., step210of method200. In embodiments in which semiconductor substrate320is a monocrystalline silicon wafer and top surface305corresponds to a principle crystallographic plane, e.g., a [1-0-0] plane, cleave plane303generally also corresponds to a principle crystallographic plane, thereby greatly facilitating cleaving of top layer321from semiconductor substrate320. In some embodiments, ions310include hydrogen (H) ions, although in other embodiments other ions may be implanted in step202to form cleave plane303.

Ions310are implanted into semiconductor substrate320at a dose selected to form a targeted concentration of ions310in cleave plane303. For example, in embodiments in which hydrogen ions are implanted in cleave plane303, the targeted concentration of ions310in cleave plane303may be from 1016to 1020atoms/cm3. Such a concentration of hydrogen atoms can sufficiently weaken silicon-silicon bonds in semiconductor substrate320so that top layer321can be separated from semiconductor substrate320at cleave plane303in a controlled exfoliation process. Furthermore, the depth304at which ions310come to rest in semiconductor substrate320can be precisely selected with the ion implantation energy used in step202. For example, hydrogen ions implanted at 50 to 150 KeV in step202may form cleave plane303at depth304of 0.5 to 1 micron below surface305of semiconductor substrate320. By closely controlling the ion implantation energy of ions310in step202, a tight distribution330of ions310results in a spike in concentration at a targeted depth, e.g., depth304. As shown inFIG. 2B, the tails331of distribution330indicate very low concentration of ions310after step202throughout semiconductor substrate320except at depth304. In some embodiments, the ion implantation of hydrogen ions form gaseous microbubbles along cleave plane303.

In optional step203, semiconductor substrate320is thermally annealed at a sufficient temperature and for a sufficient time to form silicon-hydrogen bonds in cleave plane303between hydrogen ions implanted in step202and silicon present in semiconductor substrate320. Thus, the formation and linkage of regions of brittle silicon hydride is promoted in cleave plane303. In this way, an intermittent or substantially contiguous layer of material307can be formed in cleave plane303that is mechanically weaker than the surrounding material of semiconductor substrate320, as shown inFIG. 3C. For example, in some embodiments, semiconductor substrate320is thermally annealed at 400 to 600° C. in step203.

In step204, oxide layer301is removed from surface305using any technically feasible wet etch or dry etch process, as shown inFIG. 3D. The removal of oxide layer301may facilitate formation of apertures in semiconductor substrate320in step205. In addition, an oxide layer or other dielectric layer may be deposited in step204that can be used as part of interconnect layer121.

In step205, apertures306are formed in semiconductor substrate320, as shown inFIG. 3E. Apertures306are formed through cleave plane303, so that through-interposer vias formed in apertures306are exposed when top layer321is separated from semiconductor substrate320. Apertures306may be formed in step205using semiconductor patterning and etching techniques known in the art, such as reactive ion etching (RIE).

In step206, apertures306are first lined with a layer of insulating dielectric123, for example using a chemical vapor deposition process, and then filled with an electrically conductive material308, such as electroplated copper, sputtered aluminum, tungsten deposited via chemical vapor deposition, and the like, as shown inFIG. 3F. In some embodiments, a seed layer, a barrier layer, or other conformal layer of conductive material may be deposited in apertures306prior to the process of filling apertures306with electrically conductive material308. When apertures306are filled with electrically conductive material308, through-interposer vias122are formed in top layer321, although in step206through-interposer vias122do not yet form an electrically conductive path through top layer321. After top layer321is removed from semiconductor substrate320, as described below, through-interposer vias122provide such electrically conductive paths.

In step207, insulating dielectric123is prepared for the mounting of IC chips101and102on semiconductor substrate320, as shown inFIG. 3G. Specifically, one or more layers of electrical interconnects may be formed on semiconductor substrate320, such as interconnect layer121. Interconnect layer121may be formed using various wafer-level deposition, patterning, and etching processes known in the art, and may be configured to electrically couple IC chips101and102to each other and to electrically conductive material308in one or more of the apertures306. In some embodiments, different layers of electrical interconnects in interconnect layer121are formed within non-organic dielectric films that are deposited on a surface of semiconductor substrate320. For example, in some embodiments, insulating dielectric123is patterned, etched, and filled using conventional dual damascene metal deposition processes to form interconnect layer121. A chemical-mechanical polishing process may then be used after such processes are used to form an interconnect layer in interconnect layer121. The above processes may be repeated for additional interconnect layer in interconnect layer121, the final interconnect layer including top layer pads for electrical connection to IC chips101and102.

In step208, IC chips101and102are mounted on semiconductor substrate320and electrically coupled to electrically conductive material308in one or more of the apertures306formed in semiconductor substrate320, as shown inFIG. 3H. For example, IC ships101and102may be mechanically and electrically coupled to semiconductor substrate320with solder microbumps in a reflow process or other thermal process, such as thermal compression non-conductive paste (TCNCP).

In step209, overmolding140is formed on semiconductor substrate320to encapsulate IC chips101and102, as shown inFIG. 3I. Overmolding140may be an injection-molded component formed by injecting a suitable molten material, such as a molding compound, into a mold cavity or chase using techniques known in the art. The mold cavity may be formed with a removable mold assembly (not shown inFIG. 1for clarity) coupled to interposer120. After cooling and hardening of the molding compound and removal of the mold assembly, the injected molding compound forms overmolding140as shown inFIG. 1. In some embodiments, overmolding140for a plurality of IC packages can be formed simultaneously with a single mold assembly prior to singulation of IC package100. The material of overmolding140is selected to protect IC chips101and102from mechanical damage, exposure to moisture, and other ambient contamination. In some embodiments, overmolding140can be planarized using a chemical-mechanical polishing process to remove molding material covering IC chips101and102and facilitate the addition of a heatsink or heatspreader directly to IC chips101and/or102for effective heat removal.

In step210, top layer321is removed from semiconductor substrate320, thereby forming interposer120and exposing through-interposer vias122on bottom surface309of interposer120, as shown inFIG. 3J. Various methods may be used to separate top layer321from semiconductor substrate320in step210. For example, in one embodiment, a room-temperature mechanical fracturing process may be used involving application of a pressurized air burst that initiates a separation fracture between top layer321and the remaining portion of semiconductor substrate320, the separation fracture rapidly propagating through cleave plane303. In another embodiment, a thermal process is used to separate top layer321from semiconductor substrate320, in which heating of semiconductor substrate320to a sufficient temperature causes pressure in hydrogen microbubbles in cleave plane303to build to a magnitude that separates top layer321from semiconductor substrate320. Moreover, use of any other technically feasible technique to separate top layer321from semiconductor substrate320at cleave plane303falls within the scope of the invention. Therefore, thickness304of top layer321can be very precisely controlled and a targeted thickness for interposer120can be reliably achieved. Semiconductor substrate320can then be polished and re-used to form another interposer.

After interposer120is formed by the separation of top layer321from semiconductor substrate320and through-interposer vias122are exposed, a low-temperature dielectric can be deposited on bottom surface309, e.g., at a temperature less than about 200° C. The dielectric layer can then be patterned, etched, filled, and planarized, using standard techniques, to form a bottom-side pad layer for the attachment of C4 bumps and subsequent mounting of top layer321onto a packaging substrate, such as packaging substrate130inFIG. 1. Standard flip-chip ball-grid array (FCBGA) assembly processes may be used for attachment to the packaging substrate.

Interposer120is formed in method200by removing top layer321from semiconductor substrate320rather than by grinding down a semiconductor substrate to a desired thickness. Thus, when method200is used to form interposer120, the typical inspections that a silicon interposer undergoes after each step of a thinning process may be avoided, thereby simplifying the fabrication process. Inspections that may no longer be necessary when method200is used to form a silicon interposer include thickness measurements of the silicon interposer, crack detection, inspection for mechanical damage to the silicon substrate caused by the debonding or thinning processes, inspection for residual bonding adhesive or other foreign matter, etc.

In some embodiments, prior to the material removal process in step210, a glass or silicon carrier may be bonded to overmolding140to facilitate separation of top layer321from semiconductor substrate320. In other embodiments, overmolding140can serve as an adequate mechanism by which semiconductor substrate320is handled during such separation.

FIG. 4illustrates a computing device in which one or more embodiments of the present invention can be implemented. Specifically,FIG. 4is a block diagram of a computing device400with an IC package420configured according to an embodiment of the present invention. As shown, computer system400includes a memory410and an IC package420that is coupled to memory410. Computer system400may be a desktop computer, a laptop computer, a smartphone, a digital tablet, a personal digital assistant, or other technically feasible computing device. Memory410may include volatile, non-volatile, and/or removable memory elements, such as random access memory (RAM), read-only memory (ROM), a magnetic or optical hard disk drive, a flash memory drive, and the like. IC package420may be substantially similar in organization and operation to IC package100, described above in conjunction withFIG. 1, and may include a CPU, a GPU, an application processor or other logic device, a system-on-chip, or any other IC chip-containing device.

In sum, an embodiment of the invention sets forth an IC package that includes an interposer formed from a layer of semiconductor material separated from a substrate and methods of manufacturing the same. Because in such an embodiment the interposer can be formed from a thin layer of semiconductor material that is separated from a substrate and not by a substrate thinning process, vias formed through the interposer can be scaled down significantly in size. Such reduced-size micro vias can be etched and filled much more cost-effectively and result in greatly reduced parasitic capacitance in the integrated circuit package. Moreover, the interposer in such an embodiment can be advantageously fabricated without using imprecise and difficult-to-control thinning operations.