Apparatus and method to prevent the unsettling of a quiescent, low output channel caused by ground bounce induced by neighboring output channels

A method of controlling the ill-effects of ground bounce in a CMOS device, according to the present invention, comprises increasing the impedance between (1) the output line of a quiescent channel that is already at a low state, and (2) the local ground within the CMOS device; the increased impedance occurring when a ground bounce condition caused by an adjacent channel within the CMOS device would otherwise cause the output of the quiescent channel to be dragged high.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The invention relates generally to digital CMOS (Complimentary Metal Oxide 
Semiconductor) circuits and more particularly to digital circuit design 
techniques in semiconductor devices which reduce output ringing in very 
fast CMOS output configurations. 
2. Description of the Prior Art 
The need for increasing levels of throughput and the resulting improved 
performance in today's CMOS systems requires high speed and high dynamic 
drive current that interface chips to circuit boards or backplanes. The 
high speed and high current drive levels can be easily achieved by modern 
submicron CMOS processing, but there are a few undesirable side effects. 
Higher rates of change (di/dt) in all switching transistors result from the 
much faster slewing of the internal nodes in current technology devices. 
Output devices are designed to handle high levels of output current and 
the consequential di/dt can be exceedingly high. Some devices that have 
many of their outputs switching simultaneously can experience di/dt levels 
of 500 milliamps per nanosecond in their common ground or Vcc leads. A 
certain amount of inductance in these leads is unavoidable and significant 
voltages can be developed across relatively small inductive reactances 
when di/dt levels are high. The "lead" inductance often referred to in 
this connection usually includes the combination of bonding wire and 
package pin inductances. 
FIG. 1 shows a prior art CMOS output driver arrangement and shows the 
package lead inductances as L.sub.1 -L.sub.3 and an external load 
capacitance C.sub.L that is fifty picofarads. Transistors N.sub.1 (NMOS) 
and P.sub.1 (PMOS) are designed to be large enough to source or sink about 
100 mA. The typical high-speed CMOS chip has many such drivers that all 
share the same on-chip power and ground rails. A particular area of 
concern is the case where most of the outputs switch from logic HIGH to 
LOW by turning on transistors N.sub.1. This will generate a voltage 
fluctuation of the on-chip ground compared to the system ground. This 
condition is commonly known as "ground bounce." Too severe a ground bounce 
will cause false level transitions in both the driving and driven devices. 
Less severe ground bounce will decrease noise immunity, because positive 
ground bounce robs from Voltage Input High (V.sub.ih) margins and negative 
ground bounce cuts into Voltage Input Low (V.sub.IL) margins. Ground 
bounce effects are sensitive to process, temperature, and operating 
voltage variations. "Fast" processes, low temperatures, and high operating 
voltages can each increase ground bounce effects. Device speed, a dominant 
parameter, is the worst at the opposite extremes: slow processes, high 
temperatures, and low operating voltages. Testing for speed receives so 
much attention at its worst case extremes, that the worst case extremes 
for ground bounce are often ignored. 
In FIG. 2, the positive half cycle ground bounce that peaks at "A" 
primarily results from the rate of change of current (di/dt) of one buffer 
times the ground lead inductance L.sub.1 times the number of buffers 
simultaneously switching their respective N.sub.1 devices to ON. The di/dt 
rate is determined by the rate at which the gate voltage (V.sub.g) to 
source voltage (V.sub.s) of N.sub.1 changes (dV.sub.gs /dt). During the 
first part of the output fall time, the ground voltage rises while the 
output voltage (V.sub.o) falls. This forces N.sub.1 into its linear region 
of operation. Transistor N.sub.1 then is the equivalent of a resistor 
having a resistance R.sub.on, and that can be as high as a few tens of 
ohms for a high-speed buffer. For the remainder of the output voltage 
excursion, the equivalent circuit of the output can be treated as if it 
were a resonant L-C-R circuit consisting of the ground and output lead 
inductance (L.sub.1 and L.sub.3), the load capacitance C.sub.L, and the 
total loop resistance which includes R.sub.on. The resonant frequency is 
determined by the net values of inductance and capacitance, while the 
damping is determined by the inductance and the total resistance of the 
loop. If L.sub.1 is large enough and R.sub.on is small enough, the ground 
bounce will oscillate through several Cycles, as shown in FIG. 2. False 
triggering can be caused if point "C" exceeds a logic HIGH. The whole of a 
device's noise margin can also be exceeded if the peak at point "A" (in a 
device having quiescent output at a logic LOW) rises higher than the input 
threshold of a circuit driven by the quiet output. 
The prior art has attempted to correct ground bounce. Different approaches 
have been tried, but practically all have achieved less than a complete 
solution. The most common work-around solution has been to slow down the 
positive going rate-of-change of Vgs by inserting an appropriate delay 
network between Vg and the gate of N.sub.1. If N.sub.1 has a slow enough 
positive rise, then the amplitudes of points "A", "B", and "C" in FIG. 2 
will be reduced. However, in order to have a significant ground bounce 
reduction, a buffer driving a fifty picofarad load might have to slow its 
HIGH to LOW transition from one and a half nanoseconds to six nanoseconds. 
The exact amount of slowdown required depends on the package pin 
inductances and the number of outputs that might be simultaneously 
switching. A delay that is enough for the case when all outputs are 
switching will be excessive for cases when fewer than that number are 
switching. With some devices now having as many as 32 outputs, the ground 
bounce solutions chosen can have a major influence in a device's high 
speed performance. 
Another common technique employed to control ground bounce involves 
distributing the current running through pull-down devices. Multiple 
pulldown devices each handle a reduced portion of the whole current and 
are successively turned on via a delay chain. Consider the prior art found 
in U.S. Pat. No. 4,785,201 by Martinez. The circuit of Martinez uses a 
P-type Metal Oxide Semiconductor (PMOS) pull-up transistor and a N-type 
Metal Oxide Semiconductor (NMOS) pull-down transistor as a pair of strong 
driving elements. (The parasitic, but "unavoidable series inductance to 
system ground" is shown as a discrete inductor, and a matching inductor to 
V.sub.cc.) A PMOS pull-up transistor and a NMOS pull-down transistor form 
a pair of weak driving elements. The weaker pair are designed to turn on 
prior to the stronger pair via delays introduced by a pair of inverter 
transistors. The main idea is that the large current spike created when a 
large lumped device is turned on will be decreased in intensity if a 
previously activated weaker device dissipates some of the initial 
discharge energy. The gain of the stronger devices can be slightly lower 
than would otherwise be required. The U.S. Pat. No. of Bolar et al., 
4,638,187, avoids using a PMOS pull-down as a weaker device, and instead 
uses another NMOS pulldown transistor. This weaker pull-down transistor 
has a smaller gain than the main NMOS pull-down. The delay is introduced 
by an R-C network that includes a resistor (and stray capacitance), 
instead of an inverter chain. U.S. Pat. No. 4,777,389, by Wu et al., 
discloses a circuit that essentially uses the same current distribution as 
above, but uses a different method of achieving the delay for the second, 
stronger pull-down transistor. The delay in turning on the second, 
stronger pull-down transistor results from a closed loop control that 
waits for the high to low transition of the output to reach a certain 
level before a pull-down transistor is activated. This assures an adequate 
time spacing between the two current spikes. None of the prior art above 
directly monitor or control the particular electrical parameter that 
results in ground bounce, namely, the time rate of change of the pull-down 
current (di/dt). The sensitivities to process, temperature, and operating 
voltage also go largely neglected. The U.S. Pat. No. 4,622,482, of Ganger, 
directs itself to limiting the output voltage slew rate in 
telecommunications applications. A pair of fixed capacitors, and a pair of 
constant current sources, are each used to perform slew rate limiting and 
to insure linearity. Several undesirable consequences result from the 
implementation. Biasing circuits are required to provide N-bias and P-bias 
potentials, thereby requiring an accurate source externally and therefore 
extra I/O pins. Alternatively, internally generated biases would 
necessitate generators with large static DC currents to sustain a 
reasonable noise rejection ratio. A complementary pair of push-pull 
transistors and are never mutually exclusive because their gates are not 
pulled completely up to Vdd or down to Vss when intended to be off. This 
results in large leakage currents that are usually unacceptable in digital 
circuits. And since the push-pull transistors are never quite off, 
parasitic capacitive coupling in their gates to Vdd and Vss will cause the 
push-pull transistors to amplify any high-frequency noise on the Vdd and 
Vss supply rails. Slew-rate control is confined only to the saturation 
region of the output transistors when static biasing is used. Since the 
value of capacitors do not change to accommodate the push-pull transistors 
transition from their saturation region to their linear region, the 
linearity control fails at this stage and throughout the linear region of 
operation. The capacitive coupling provided by capacitors will couple any 
output transition back to the gate of the supposedly off transistor to 
cause it to turn on. While the resulting current contention has the effect 
of further limiting the voltage slew rate of the output, it inadvertently 
dumps even more transient and DC current to Vss, which actually increases 
ground bounce in digital circuits. 
Lien, et al., in U.S. Pat. No. 4,933,574, disclose a BiCMOS output driver 
that is intended to maximize switching speed and to minimize ground 
bounce. A bipolar transistor in the output is not permitted to go into 
saturation. A pair of transistors, connected in an inverter configuration, 
develop a signal that indicates when the bipolar transistor pulls-down the 
output below a predetermined point. Three gate delay times after the 
output falls below a second predetermined level, a second transistor in 
parallel with the bipolar transistor is switched. 
The prior art has more-or-less been directed at controlling ground bounce 
for channels that are actively switching their outputs from high to low. 
The popular technique, described above, is to use two output pull-down 
transistors to ease up on the rate of output slew from high to low. What 
is needed is a solution that addresses the problem of quiescent channels 
that are already low and become unsettled by local ground bounce induced 
by a neighboring output channel. The present invention provides such a 
solution. Two output pull-down transistors in parallel decouple the 
quiescent, low channel from a local ground by turning-off the output 
transistor with the lower R.sub.on resistance, during positive swings of 
the local ground caused by ground bounce. 
SUMMARY OF THE PRESENT INVENTION 
It is therefore an object of the present invention to provide a circuit 
that eliminates the deleterious effects of ground bounce without having to 
slow down the operation of high-speed CMOS drivers. 
Briefly, a first embodiment of the present invention is a CMOS device 
having many output channels at least one of which channel comprises (1) a 
high sink current driver, with an R.sub.on of about ten ohms, that is ON 
only during the time the output is falling and still a logic HIGH, (2) an 
AND gate, and (3) a second sink transistor having an R.sub.on of about 5K 
ohms, all of which are combined into an output buffer such that the output 
of the AND-gate switches LOW when the voltage at the output of the buffer 
drops below about 1.5 volts. At that threshold, the high current sink 
transistor turns off, leaving the weaker, second sink transistor ON to 
pull the output of the buffer LOW. Any tendency of the output of the 
buffer to ring HIGH above the threshold of the AND gate will be clamped by 
the high sink current transistor. 
A second embodiment comprises the first embodiment, but with the 
elimination of the AND gate, and instead a Schottky diode between the 
first sink transistor and the output. When a system connected to the 
output has been driven low, a ground bounce in the CMOS device severe 
enough to lift the local ground inside the CMOS device positive more than 
a few hundred millivolts will reverse bias the Schottky diode. The 
clamping of the output to local ground will thereby be released and the 
output cannot be dragged high by transients on the local ground. A third 
embodiment comprises the above Schottky diode in an otherwise standard 
output buffer arrangement. 
A method of controlling the ill-effects of ground bounce in a CMOS device, 
according to the present invention, comprises increasing the impedance 
between (1) the output line of a quiescent channel that is already at a 
low state, and (2) the local ground within the CMOS device; the increased 
impedance occurring when a ground bounce condition caused by an adjacent 
channel within the CMOS device would otherwise cause the output of the 
quiescent channel to be dragged high. 
An advantage of the present invention is that ground bounce peaks are 
effectively clipped and false triggering in nearby associated circuits is 
reduced or completely eliminated. 
Another advantage of the present invention is large output sink currents 
(I.sub.OL) can be obtained without exacerbating ground bounce. 
These and other objects and advantages of the present invention will no 
doubt become obvious to those of ordinary skill in the art after having 
read the following detailed description of the preferred embodiments which 
are illustrated in the various drawing figures.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
As illustrated in FIG. 3, a first embodiment of the present invention is a 
CMOS device 10 comprised of a relatively large PMOS pull-up transistor 12 
(P.sub.1) having drain 14 tied to drain 16 of a relatively large NMOS 
pull-down transistor 18 (N.sub.1). A relatively small NMOS pull-down 
transistor 20 (N.sub.2) has its drain 22 connected to drain 16 such that 
the sinking current of device 10 is split between transistors 18 and 20 
when both are turned on. (Sinking current is that current that flows to 
pull the output lower toward system ground; sourcing current is that 
current that pulls the output higher toward Vcc.) The R.sub.on of 
transistor 18 is about ten to forty ohms and the R.sub.on of transistor 20 
is about 1,000 to 10,000 ohms. The current through transistor 18 will 
therefore be greater than the current through transistor 20. An AND-gate 
24 controls gate 26 of transistor 18. Preferably, AND-gate 24 comprises 
transistors that have been sized for minimum delay in driving the large 
gate capacitance of transistor 18. For FIG. 4, discussed below, ground 
bounce is measured at a point 28 that is common to the sources of 
transistors 18 and 20 and inductor L.sub.1. Point 28 represents a local 
ground common to all channels within device 10. The bottom of L.sub.1 and 
C.sub.L are at system ground. Inductances L.sub.1 -L.sub.3 represent the 
respective lead inductances of the integrated circuit, bonding wires, and 
leads associated with device 10. The output load of device 10 is 
represented by a capacitive load C.sub.L of approximately fifty 
picofarads. Transistor 12 can alternatively be an NMOS type transistor 
connected in a source follower mode. A suitable inverter is included to 
invert the buffer input signal to the gate of the gate of the NMOS source 
follower. 
FIG. 4 shows that the output voltage (V.sub.output) of device 10 responds 
to the input voltage (V.sub.input) in a more controlled way than was the 
case in FIG. 2. The ground bounce at point 28 continues its gyrations from 
peaks "A" to "B" to "C", but V.sub.output does not track it because the 
output is no longer locked to point 28 by transistor 18. When V.sub.input 
takes a step to HIGH as indicated in FIG. 4, both transistors 18 and 20 
will be turned on hard. The output V.sub.output will fall to about 1.5 
volts where AND-gate 24 will turn-off transistor 26 by dropping gate 26 to 
LOW. Since the ON resistance (R.sub.on) of transistor 20 is about 1,000 to 
10,000 ohms, V.sub.output will be over damped and the tendency for the 
output to ring will be suppressed. 
The AND-gate 24 may experience a shift during adjacent-channel-induced 
ground bounce in its minimum V.sub.ih (logic on ) upwards during the swing 
of point 28 through peak "A". For this reason, the V.sub.ih of AND-gate 24 
should be set lower than if AND-gate 24 was a stand-alone five volt logic 
element. It is also advantageous to have a lower V.sub.ih to cut short the 
positive swing of the output going high as a consequence of N.sub.1 and 
N.sub.2 clamping the output to point 28 while point 28 swings up through 
peak "A". If the output voltage swing does not signal AND-gate 24 to 
switch until the output has swung as high as a standard V.sub.ih, then the 
action of AND-gate 24 would come too late. The embodiments described below 
may be preferable for these reasons. 
FIG. 5 is a second embodiment of the present invention which is a CMOS 
device 40 comprised of a relatively large PMOS pull-up transistor 42 
(P.sub.1) having drain 44 tied through Schottky diode SD1 to drain 46 of a 
large NMOS pull-down transistor 48 (N.sub.1). A small NMOS pull-down 
transistor 20 (N.sub.2) has its drain 52 connected to drain 44 such that 
the sinking current at the output of device 40 is split (albeit unevenly) 
between transistors 48 and 50 when both are turned on. The R.sub.on of 
transistor 48 is about ten to forty ohms and the R.sub.on of transistor 50 
is about 1,000 to 10,000 ohms. The current through transistor 48 will 
therefore be greater than the current through transistor 50. The output 
load of device 40 is represented, as above, by a capacitive load C.sub.L 
of approximately fifty picofarads. The principal difference between device 
10 and device 40 is the addition of Schottky diode SD1 in the latter and 
the AND gate elimination. A Schottky diode type is preferred over an 
ordinary silicon diode type because the switching speed is faster and the 
forward bias voltage is lower for the Schottky diode. Forward bias 
voltages are on the order of a few hundred millivolts. 
The action of Schottky diode SD1 helps keep a quiescent channel that is 
already at a logic low from becoming unsettled in sympathy with nearby 
channels generating large ground bounce voltages. Schottky diode SD1 will 
increase its impedance beginning immediately with any movement of drain 46 
of transistor 48 toward Vcc. Such a movement will cause the forward bias 
voltage across Schottky diode SD1 to fall short of what is needed to 
sustain a current. A still further swing toward Vcc will, at some point, 
cause Schottky diode SD1 to reverse bias. This, of course, will put 
Schottky diode SD1 in its maximum impedance condition. The output of 
device 40 will tend to resist ground bounce induced swings due to the 
capacitive effects of C.sub.L. In prior art circuits, this inertia to stay 
at ground (once low) was overcome deliberately by P.sub.1 switching on, 
and unintentionally by N.sub.1 dragging the output along with the local 
ground's ground bounce excursions. Here, the inertia to stay at ground is 
used to bridge the short time needed to reapply the sinking current 
actions of N.sub.1 and N.sub.2, sometime after ground bounce peaks "A" or 
"C" (FIG. 4). 
FIG. 6 shows how the benefits of Schottky diode SD1 alone can be usefully 
employed. A third embodiment of the present invention is a device 60 that 
differs from the prior art of FIG. 1 in that a Schottky diode SD1 has been 
placed in series with the drain of transistor N.sub.1. The explanation 
given for the circuit behavior of Schottky diode SD1 in FIG. 5 applies 
here as well. 
FIG. 7 illustrates a fourth embodiment of the present invention and is most 
like the first embodiment described above. Buffer 70 comprises 
current-source transistor Pl and three current-sink transistors N.sub.1 
N.sub.2, and N.sub.3. A first AND-gate 84 drives the gate 86 of transistor 
N.sub.1. A second AND-gate 88 drives the gate of transistor N.sub.3 and 
has an inverted version of the output of buffer 70 by virtue of inverter 
90. Transistor N.sub.1 is large and is driven on and off by AND-gate 84. 
("Large" means the transistor is able to sustain a relatively larger 
current through its channel and has a lower ON resistance, R.sub.on.) 
Transistor N.sub.2 is comparatively small. The difference is that a 
transistor N.sub.3 and a diode D1 are in parallel with N1. Transistor N3 
is large and is only turned-on when the output is low and the input is 
high. Buffer 70 has a lower impedance to within one diode drop of ground, 
compared to that of buffer 10. This is mainly due to the fact that 
transistor N3 is large compared to N2. Surge current through diode D1 is 
minimized by delaying the turn-on of transistor N3 until the buffer output 
is low. Preferably, the peak currents through diode D1 should be minimized 
because an ordinary diode can inject minority carriers into a CMOS 
substrate when forward biased and that can result in latch-up. The above 
Schottky diode implementation above has the advantage of naturally 
avoiding minority carrier injection. 
The first through fourth embodiments of the present invention, described 
above, have in common the ability to increase the impedance between the 
top of the current sink transistor N.sub.1 and the output to load C.sub.L 
when the bottom of Current sink transistor N.sub.1 swings sufficiently 
positive. For example, the portion of the ground bounce waveform, labelled 
"A" in FIG. 4, can rise higher than a quiescent voltage that had been 
established on the output (assuming the output was low). If a low 
impedance path exists between the local ground and the output, then the 
output will be dragged high in sympathetic movement with the ground bounce 
caused by adjacent channels. The embodiments described above each prevent 
the output from being dragged high by increasing the impedance between 
local ground and the output. The embodiments comprising the Schottky diode 
in crease impedance by reverse biasing SD1. 
Although the present invention has been described in terms of the presently 
preferred embodiments, it is to be understood that the disclosure is not 
to be interpreted as limiting. Various alterations and modifications will 
no doubt become apparent to those skilled in the art after having read the 
above disclosure. Accordingly, it is intended that the appended claims be 
interpreted as covering all alterations and modifications as fall within 
the true spirit and scope of the invention.