Semiconductor memory device using dynamic data shift redundancy system and method of relieving failed area using same system

A semiconductor memory device comprises a plurality of submacros mutually connected via global data lines. Each of the submacros includes a first and a second memory block, and a memory block control circuit arranged between the first and second memory blocks. The memory block control circuit includes a DQ buffer block connected to the first memory block via first complementary data lines and connected to the second memory block via second complementary data lines. It also includes a dynamic data shift redundancy circuit block connected to the DQ buffer block via local data lines and operative to relieve the first and second memory blocks.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2007-238855, filed on Sep. 14, 2007, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device comprising a redundancy circuit for relieving a failed data line.

2. Description of the Related Art

There have been redundancy systems in semiconductor memory devices such as DRAMs to replace a failed cell with a redundancy cell as known in the art. A conventional common fixed data shift redundancy system comprises DQ buffer blocks operative to amplify data and fixed data shift redundancy circuit blocks in each relief target memory block. Namely, the ability of a fixed data shift redundancy circuit block is limited to relieve only one memory block (one relief area) (Patent Document 1: JP 2004-118920A).

Expansion of submacros in the conventional system requires the DQ buffer block and the fixed data shift redundancy circuit block to be arranged in each relief area, which presses the chip area. A reduction in the number of DQ buffer blocks inside the DRAM for the purpose of reducing the area increases the relief areas and lowers the relief efficiency as a problem.

SUMMARY OF THE INVENTION

In an aspect the present invention provides a semiconductor memory device, comprising a plurality of submacros mutually connected via global data lines, each of the submacros including a first and a second memory block, and a memory block control circuit arranged between the first and second memory blocks, the memory block control circuit including a DQ buffer block connected to the first memory block via first complementary data lines and connected to the second memory block via second complementary data lines, and a dynamic data shift redundancy circuit block connected to the DQ buffer block via local data lines and operative to relieve the first and second memory blocks.

In another aspect the present invention provides a semiconductor memory device, comprising: a first and a second memory block; a DQ buffer block connected to the first memory block via first complementary data lines and connected to the second memory block via second complementary data lines; and a dynamic data shift redundancy circuit block connected to the DQ buffer block via local data lines and operative to relieve the first and second memory blocks in accordance with information of one bit in an arbitrary address received from external.

In yet another aspect the present invention provides a semiconductor memory device, comprising a plurality of submacros each including a first and a second memory block, a certain one of the submacros, independent of the other of the submacros, including a DQ buffer block connected to the first memory block via first complementary data lines and connected to the second memory block via second complementary data lines, and a dynamic data shift redundancy circuit block connected to the DQ buffer block via local data lines and operative to relieve the first and second memory blocks.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The embodiments of the invention will now be described with reference to the drawings.

FIG. 1shows a configuration of the major part of a DRAM according to one embodiment of the present invention. A memory area comprises a plurality of submacros (SUBMAC<0>, <1>)1,2. The submacros1,2are connected to submacro control circuits (SUBMACCTL<0>, <1>)3,4operative to control these submacros, respectively. The submacros1,2are provided with a common interface unit (I/F)5for information communications with external. The interface unit5is connected to the plurality of submacros1,2through a plurality of global data lines GLDA. The global data lines GLDA include a plurality of global write data lines WD and a plurality of global read data lines RD. The interface unit5is connected to the submacro control circuits3,4via an address command latch circuit (ADDCOMLTC)6. The address command latch circuit6has a function of latching an address signal and a command signal received from external and sending the address signal and the command signal to the submacro control circuits3,4.

The submacros1,2comprise a first relief area <0> or a first memory block (MEM<0>)11, and a second relief area <1> or a second memory block (MEM<1>)12. It also comprises a DQ buffer block (SDQB)7and a dynamic data shift redundancy circuit block (SRDB)8, which are arranged between the memory blocks11,12and shared by the memory blocks11,12. The DQ buffer block7amplifies data signals on a plurality of complementary data lines DQt/c<0>, <1> connected to the memory blocks11,12. The dynamic data shift redundancy circuit block8dynamically selects a relief area and relives the memory blocks11,12during DRAM operation.

Inside the submacros1,2, the plurality of global data lines GLDA are connected to the dynamic data shift redundancy circuit block8. The dynamic data shift redundancy circuit block8is connected to the DQ buffer block7through a plurality of local data lines LODA. The DQ buffer block7is connected to the memory block11via the plurality of complementary data lines DQt/c<0>. The DQ buffer block7is connected to the memory block12via the plurality of complementary data lines DQt/c<1>.

A specific 1-bit address ADDIN<i>=0 fed from external is assigned to the relief area <0>. A specific 1-bit address ADDIN<i>=1 fed from external is assigned to the relief area <1>.

FIGS. 2A,2B are block diagrams showing a more detailed configuration of the shared DQ buffer block, the dynamic data shift redundancy circuit block8and periphery circuits thereof.

The shared DQ buffer block7includes a plurality of shared DQ buffers (SDQB)70,71,72corresponding to the complementary data lines DQt/c<0>, <1>. The memory blocks11,12include a plurality of sense amplifier circuits (S/A[n]−[n+2])110,111,112,120,121,122operative to amplify signals read out of internal memory cells and signals to be written in internal memory cells.

The dynamic data shift redundancy circuit block8includes a plurality of dynamic data shift redundancy circuits81each having a write switch (WSW[n])811. The shown example makes it possible to switch among three complementary data lines DQt/c per relief area. A local data-in signal LDIN[n] from the interface unit5is latched at a write data latch (WDLTC[n])9in accordance with a write data latch timing clock WDCLK. The write data latch9is connected to the write switch811via global write data lines WD[n]. The output of the write switch811is connected to three shared DQ buffers70,71,72via three local write data lines LWD[n]−[n+2]. The shared DQ buffers70-72are connected to sense amplifier circuits110-112via the complementary data lines DQt/c<0> and connected to sense amplifier circuits120-122via the complementary data lines DQt/c<1>. The sense amplifier circuits110-112and120-122are connected to a plurality of memory cells via the complementary bit lines BLt/c. Although omitted fromFIGS. 2A and 2Bto give attention to the write switch WSW[n], there are write switches WSW[n+1], WSW[n+2] corresponding to the DQ buffers SDQB[n+1], SDQB[n+2] in practice.

The following description is given to write operation in the DRAM thus configured according to the present embodiment.

InFIG. 2A, data fed from external via the interface unit5to be written in a memory cell is latched at the write data latch9as the local data-in signal LDIN[n]. The data latched in the write data latch9is transferred via the global write data lines WD[n] to the write switch811.

The relief area <0> or the memory block11may be accessed as shown inFIG. 2A. In this case, the complementary bit lines BLt/c<0> connected to the sense amplifier circuits110,111include failed points as shown with marks “×” in the figure. Accordingly, the write switch811selects the shared DQ buffer72connected to the sense amplifier circuit112having no failed point.

The relief area <1> or the memory block12may be accessed as shown inFIG. 2B. In this case, the complementary bit lines BLt/c<1> connected to the sense amplifier circuit120include a failed point as shown with a mark “×” in the figure. Accordingly, the write switch811selects the shared DQ buffer71connected the sense amplifier circuit121located closer to the left side of the sense amplifier circuits121,122having no failed point.

FIG. 3is a block diagram showing in detail an internal configuration of one of plural dynamic data shift redundancy circuits (SRD)81contained in the dynamic data shift redundancy circuit block8, the input/output of signals, and relations between other characteristic circuit blocks, in write operation. Inside the dynamic data shift redundancy circuit81, the write switch811is connected to a leftward shift determination multiplexer circuit (MUXWSL)812for write via a leftward shift determination signal line WSFTL for write. The write switch811is also connected to a rightward shift determination multiplexer circuit (MUXWSR)813for write via a rightward shift determination signal line WSFTR for write. There are failed address latches (FLTC<0>, <1>)814,815operative to store failed address information associated with relief areas. As areas relieved by one dynamic data shift redundancy circuit81are always only 2 in number, the failed address latches814,815are present only 2 in number. In this case, the failed address latch814holds the failed address information on the relief area <0> and the failed address latch815holds the failed address information on the relief area <1>. The leftward shift determination multiplexer circuit812for write is given failed address data signals from the failed address latches814,815via failed address data lines FADDL<0:1>. The rightward shift determination multiplexer circuit813for write is given failed address data signals from the failed address latches814,815via failed address data lines FADDR<0:1>.

The leftward shift determination multiplexer circuit812for write and the rightward shift determination multiplexer circuit813for write are connected to the output of an address latch (ADDTLC)13via a relief area selection signal line WSEL<0:1> for write. The address latch13latches an address ADDIN received from external in synchronization with a rise edge of an address latch timing clock ADDCLK.

Write data is fed as a data-in signal DIN into the interface unit5and then sent to the DQ buffers70-72as the local data-in signal LDIN, the global write data signal WD, and the local write data signal LWD in order as described earlier.

FIG. 4shows detailed circuitry of the leftward shift determination multiplexer circuit812for write and the rightward shift determination multiplexer circuit813for write. The leftward shift determination multiplexer circuit812for write and the rightward shift determination multiplexer circuit813for write each comprise two clocked inverters CLKINV<0:1> and one inverter INV. The outputs of the two clocked inverters CLKINV<0:1> are connected to the input of the inverter INV. The output of the inverter INV in the leftward shift determination multiplexer circuit812for write is connected to a leftward shift determination signal line WSFTL for write. A failed address data signal FADDL for MUXWSL and a relief area selection signal WSEL for write are fed into one clocked inverter CLKINV. The output of the inverter INV in the rightward shift determination multiplexer circuit813for write is connected to a rightward shift determination signal line WSFTR for write. A failed address data signal FADDR for MUXWSR and a relief area selection signal WSEL for write are fed into one clocked inverter CLKINV.

When the relief area <0> is selected, the relief area selection signal WSEL<0> for write becomes ‘H’ and the relief area selection signal WSEL<1> for write becomes ‘L’ in the leftward shift determination multiplexer circuit812for write. In this case, the clocked inverter CLKINV<0> provides the inverted information of the failed address data signal FADDL<0> for MUXWSL and the clocked inverter CLKINV<1> becomes the high-impedance state, which exerts no influence on operation of the circuit. As a result, the leftward shift determination signal line WSFTL for write is given the bit information associated with the failed address data signal FADDL<0> for MUXWSL as it is.

When the relief area <1> is selected on the other hand, the relief area selection signal WSEL<1> for write becomes ‘H’ and the relief area selection signal WSEL<0> for write becomes ‘L’. In this case, the clocked inverter CLKINV<1> provides the inverted information of the failed address data signal FADDL<1> for MUXWSL and the clocked inverter CLKINV<0> becomes the high-impedance state, which exerts no influence on operation of the circuit. As a result, the leftward shift determination signal line WSFTL for write is given the bit information associated with the failed address data signal FADDL<1> for MUXWSL as it is.

The rightward shift determination multiplexer circuit813for write operates in a similar manner though it is omitted from the following description.

In accordance with the combination of the leftward shift determination signal line WSFTL for write and the rightward shift determination signal line WSFTR for write, the write switch811selects among the selection-intended shared DQ buffers70-72.

In this way, the leftward shift determination multiplexer circuit812for write and the rightward shift determination multiplexer circuit813for write transmit the information about the failed address data signal FADDL for MUXWSL and the failed address data signal FADDR for MUXWSR to the write switch811to control the write switch811in accordance with the accessed relief area (memory block).

During DRAM operation, either the relief area <0> or the relief area <1> is always selected. Accordingly, it is not caused in this state that neither the relief area <0> nor the relief area <1> is selected and that both are selected.

As described above in detail with the use ofFIG. 3, the device is structured to receive the global write data signal WD at the write switch811. In addition, the write data latch WDLTC is arranged closer to the interface unit5than the write switch811. Thus, operation of the write switch811is given a temporal margin, which is described with the use ofFIG. 5.

FIG. 5shows timing of transitions of the signals inFIG. 3, with a margin caused in a period of time after the point of change in the rightward shift determination signal line WSFTR for write (or the leftward shift determination signal line WSFTL for write) until the determination of the global write data signal WD (that is, a time shown with the arrow of the solid line in the figure). It is sufficient for the write switch811to finish the shift until the global write data signal WD becomes determined. The global write data signal WD, though, has a longer wiring length and a larger parasitic capacity. Accordingly, it takes time to make the global write data signal WD determined. Therefore, the write operation of DRAM does not rate-determine the shift operation of the write switch811in that structure, which can realize fast DRAM operation.

Further, areas relived by one dynamic data shift redundancy circuit block8can be determined always only 2 in number such that 1-bit information of the address ADDIN<i> fed from external is assigned as it is to specify the relief area <0:1>. As a result, the control of decoding the address ADDIN at the address decoder is not required before the address latch13latches the address ADDIN fed from external. Thus, the write operation of DRAM can be prevented from rate determining in accordance with the time of decoding the address ADDIN at the address decoder. In a word, even if the time shown with the dashed-line arrow inFIG. 5(the time after the input to the address ADDIN until the address latch) is short, the address latch13can latch the address ADDIN at a desired rise edge of the address latch timing clock. Thus, the margin of the set-up time can be improved and fast DRAM operation can be achieved.

FIG. 6is a block diagram showing in detail an internal configuration of one of plural dynamic data shift redundancy circuits82contained in the dynamic data shift redundancy circuit block8, the input/output of signals, and relations between other characteristic circuit blocks, in read operation. Inside the dynamic data shift redundancy circuit82, a read switch (RSW)821is connected to a leftward shift determination multiplexer circuit (MUXRSL)822for read via a leftward shift determination signal line RSFTL for read. The read switch821is also connected to a rightward shift determination multiplexer circuit (MUXRSR)823for read via a rightward shift determination signal line RSFTR for read. The leftward shift determination multiplexer circuit822for read is connected to the failed address latches814,815via failed address data lines FADDL<0:1> for MUXRSL. The rightward shift determination multiplexer circuit822for read is connected to the failed address latches814,815via failed address data lines FADDR<0:1> for MUXRSR.

FIG. 7shows detailed circuitry of the leftward shift determination multiplexer circuit822for read and the rightward shift determination multiplexer circuit823for read. This circuitry is similar to that for write shown inFIG. 4, which includes the relief area selection signal line WSEL for write, the leftward shift determination signal line WSFTL for write, and the rightward shift determination signal line WSFTR for write. These lines are replaced inFIG. 7with a relief area selection signal line RSEL for read, a leftward shift determination signal line RSFTL for read, and a rightward shift determination signal line RSFTR for read.

These leftward shift determination multiplexer circuit822for read and rightward shift determination multiplexer circuit823for read are connected to a relief area selection latch (RSELLTC)14for read via relief area selection signal lines RSEL<0:1> for read. The relief area selection latch14is connected to a DQB control (DQCTL)15via SDQB control signal lines QSE<0:1>. The DQ control15is connected to the shared DQ buffers70-72via the SDQB control signal lines QSE<0:1> to control timing of read operation of the shared DQ buffers70-72with SDQB control signals QSE<0:1>. The DQ control15is connected to the address latch13via an address line ADD. The DQ control15operates in synchronization with a rise edge of the DQ control timing clock DQCLK. The address latch13latches an address ADDIN received from external in synchronization with a rise edge of an address latch timing clock ADDCLK.

The shared DQ buffers70-72are connected to the read switch811through local read data lines LRD. The read switch811is connected to a read data latch (RDLTC)10via global read data lines RD. The read data latch10is connected to the interface unit5via local data-out signal lines LDOUT. The data read out to outside the DRAM or a data-out signal DOUT is provided to external from the interface unit5. The read data latch10latches a global read data signal RD in synchronization with a rise edge of a read data latch timing clock RDCLK. Read data is provided to external as the local data read data signal LRD, the global read data signal RD, and the local data-out signal LDOUT, and the data-out signal DOUT in order.

In this way, the SDQB control signals QSE<0:1> for use in control of timing of read operation of the DQ buffers70-72already shared can be used to generate the relief area selection signal RSEL<0:1> for read. Thus, the additional circuit is only the relief area selection latch14for read, which can avoid the circuit and control to be complicated.

FIGS. 8A and 8Bshow macro-size expansion methods. In the DRAM of the present invention, the expansion unit is a submacro SUBMAC. It is structured to have DQ buffer blocks SDQBB and dynamic data shift redundancy circuit blocks SRDB, which are shared per expansion unit. The areas to be relived by each dynamic data shift redundancy circuit block SRDB include only 2 memory blocks contained inside the expansion unit. Accordingly, macro-size expansion can be achieved with an increase in the number of submacros SUBMAC, each of which is the expansion unit. Further, the use of the leftward shift determination multiplexer circuit MUXWSL for write and the rightward shift determination multiplexer circuit MUXWSR for write and of the leftward shift determination multiplexer circuit MUXRSL for read and the rightward shift determination multiplexer circuit MUXRSR for read allows the relief area to be selected with only 1 bit of the address ADDIN<i> fed from external. For example, the expansion of macros from the size ofFIG. 8Ato the size ofFIG. 8Bonly requires 2 submacros SUBMAC to be added and stacked, each of which is the expansion unit, and accordingly can realize DRAMs with excellent expandability. In this case, it is required to increase 2 in the number of the submacro control circuits SUBMACCTL. InFIG. 8, though, the submacro control circuits SUBMACCTL and the address command latches ADDCOMLTC are not essential and accordingly omitted from the figure.

In contrast, in the structures shown inFIGS. 9A and 9B, the dynamic data shift redundancy circuit block SRDB relieves all relief areas. In this case, if the submacros SUBMAC inFIGS. 9A and 9Bare increased in number to expand the size, the bits in the address ADDIN required for selecting the relief area are increased in number (requiring more extra ADDIN<k> thanFIG. 9A). This results in a larger size of the address decoder ADDDEC, which leads to an additional delay. The memory blocks contained in one submacro SUBMAC may be increased in number to expand the macro-size as shown inFIG. 9C. This results in a much larger size of the address decoder ADDDEC, which leads to an additional delay. In addition, the lengths of the complementary data lines DQt/c are elongated to result in a lowered speed. Therefore, the macro structure is extremely poor in expandability.

With this regard, the present invention makes it possible to reduce the number of bits in the address required for selecting the relief area and expand the memory size while keeping fast accessibility.