Self calibrating digital-to-analog converter

A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fL based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fL with a high frequency clock having a constant frequency fH. A memory is included to store at least two counter values generating by comparing fL and fH once when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority under 35 U.S.C. § 119 of China application no. 202111008434.2, filed on 31 Aug. 2021, the contents of which are incorporated by reference herein.

BACKGROUND

A digital-to-analog converter (DAC) is a circuit that converts a digital signal into an analog signal. An analog-to-digital converter (ADC) performs the reverse function. There are several DAC architectures; the suitability of a DAC for a particular application is determined by figures of merit including: resolution, maximum sampling frequency and others. In principle, a digital signal is inputted to a DAC and the DAC outputs an accurate output voltage. In reality, the accuracy of the output voltage is subject to gain, offset and nonlinear errors from the DAC and other components in the signal chain. The DAC circuit should compensate for these errors in order to get an accurate output voltage. This error correction can be implemented with external components and post-manufacture trimming. Digital calibration modifies the input sent to the DAC such that the gain, offset and nonlinear errors are taken into account thus removing the need for external components and trimming. Modern systems require high accuracy of digital to analog conversion. DAC is typically implemented using resistor networks. For higher accuracy, the resistors should match. However, due to factors such as process variations, it is difficult to fabricate substantially matching resistors. A high accuracy precision DAC is typically used to fine-tune gain and offset, and minimizes other non-linearity. Therefore, it becomes the precision DAC that makes a signal precise as the DAC calibrates the signal. Similar to any analog circuit, there are many non-idealities associated with DACs. The main source of direct-current (DC) errors in a DAC are offset error (OE), gain (GE), and integral non-linearity (INL).

SUMMARY

In one embodiment, a self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fLbased on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fLwith a high frequency clock having a constant frequency fH. A memory is included to store at least two counter values generating by comparing fLand fHonce when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.

In some examples, the self-calibrating DAC further includes a one-hot decoder to convert input MSB bits to a decoded output in which only one bit is high. The one-hot decoder is configured to be used only during the calibration mode. A unary or thermometer decoder is configured to be used during a normal mode of operation of the DAC. The resistance to frequency converter including a resonance circuit that is configured to use a resistance of the LSB side resistor network or the MSB side resistor network to generate the frequency fLcorresponding to a connected resistance value of the LSB side resistor network or the MSB side resistor network. The monitor is configured to generate the first counter value by comparing fLwith fHwhen resistors of the LSB side resistor network are electrically connected to the LSB input bits and resistors of the MSB side resistor network are floating. The monitor is further configured to generate a second counter value by comparing fLwith fHwhen the resistors of the LSB side resistor network are floating and only one resistor of the MSB side resistor network is electrically connected with the MSB side input bits using a one-hot decoder on MSB side. The comparator is configured to compare the first counter value with the second counter value to generate an up or down signal. The trimming controller is configured to continuously generate a trimming signal to trim the only one resistor of the MSB side resistor network and to generate a new second counter value after each trimming step until the new counter value is equal to or within a predefined range from the first counter value.

In another example, a method for self-calibrating a digital-to-analog converter (DAC) including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network, is disclosed. The method includes (a) electrically connecting resistors in the LSB side resistor network with LSB segment of an digital input signal, (b) electrically disconnecting resistors in the MSB side resistor network from MSB segment of the digital input signal, (c) generating a low frequency signal corresponding to a resistance of the LSB side resistor network, (d) calculating a first counter value by comparing the low frequency signal with a constant high frequency signal and storing the first counter value, (e) disconnecting the LSB side resistor network and connecting only one resistor of the MSB side resistor network using a one-hot decoder that outputs a code with only one high bit, (f) generating the low frequency signal corresponding to a resistance of the MSB side resistor network, (g) calculating a second counter value by comparing the low frequency signal with the constant high frequency signal and storing the second counter value and (h) generating a trimming signal to trim the only one resistor of the MSB side resistor network based on a comparison of the first counter value and the second counter value.

In some examples, step (h) is repeated until the second counter value becomes equal to the first counter value or comes within a predefined range from the first counter value. The method further includes repeating step (e) by connecting a next only one resistor in the MSB side resistor network and floating all other resistors in the MSB side resistor network. Steps (f) to (h) may be repeated for other resistors in the MSB side resistor network, one by one. The low frequency signal is generated using a resonance network that uses a connected resistance of either the LSB side resistor network or a resistance of one resistor in the MSB side resistor network selected by an output of the one-hot decoder. In some embodiments, the frequency of the constant high frequency signal is at least 100 times the frequency of the low frequency signal.

Note that figures are not drawn to scale. Not all components of the improved ground switch are shown. The omitted components are known to a person skilled in the art.

DETAILED DESCRIPTION

Many well-known manufacturing steps, components, and connectors have been omitted or not described in details in the description so as not to obfuscate the present disclosure.

A precision transmitter/receiver system typically includes high-resolution digital-to-analog converters (DAC) and analog-to-digital converters (ADC). For example, in industrial input/output applications, it's becoming more demanding to have a ˜16-bit accurate transmitting path and a greater than 20-bit accurate receiving path integrated in a single-chip solution. The most common DAC architectures are R string- or R2R ladder-based topologies. In some examples, both topologies may be used in a DAC. For example, R2R ladder may be used to implement least significant bits and R string topology may be used for most significant bits. The biggest contributor to integral non-linearity (INL) for these DACs is mismatches in resistors used in ladder and string formats. INL refers to the deviation between the ideal output of a DAC and the actual output of a DAC. Many analog processes include a high-precision resistor to design ladders and string. As the demand for higher accuracy keeps increasing, having a high-precision resistor is insufficient. To address this concern, additional design, layout, and trimming techniques are being employed to counter the effect of these mismatches in resistors.

The embodiments described herein uses RC to frequency conversion to derive a counter value for a selected most significant bit (MSB) resistor in the DAC resistor network and trimming the selected resistor based on a comparison of a counter value derived from least significant bit (LSB) resister network. Typically, an on-chip analog to digital converter (ADC) is required for the calibration of a DAC. However, the embodiments described here do not need an ADC for the calibration of the DAC. Thus, the calibration system described herein may result in a smaller die size. The embodiments described herein uses frequency to detect unit resistance variations. Using trimmable resistors, these variations are corrected and the resistors are matched.

FIG.1a Digital to Analog Converter (DAC) calibration system100. The DAC calibration system includes a DAC102that includes a resistor network. At least some of the resistors in the resistor network are trimmable. A RC (resistor-capacitor) to frequency converter104is included to generate a signal with a frequency fL. A monitor106is included to derive a counter value by comparing the signal with frequency fLwith a higher frequency signal with frequency fH. In some example, the monitor106may include a frequency divider circuit to divide fHby fLto derive a counter value. The higher frequency signal may be the on-chip clock signal. In some examples, a local higher frequency signal may be generated to be used for the DAC calibration. The frequency fHneeds to be substantially higher than the frequency fL. A higher value of fHwill provide a better accuracy of calibration due to increased granularity. In some examples, fLmay be in KHz range while fHmay be in MHz.

The DAC calibration system100may be fabricated along with the DAC102on a same chip. The DAC calibration system100further includes a memory108. The memory108may be a temporary or a permanent memory (e.g., a volatile or a non-volatile memory). A non-volatile memory is the memory that retains the stored data between the power on cycles. The memory108is used for storing counter values generated by the monitor106. A comparator110is included to compare the stored counter values. The output of the comparator110is inputted to a trimming controller112. The input to the trimming controller112may be an up or down signal. The trimming controller112generates a trimming signal to vary the resistance of a resistor in the resistor network of the DAC. The calibration process may be performed at the power on event, at the first power on, at configurable intervals or the calibration process may be triggered from an external system. VDACrepresents the analog output of the DAC102. In some examples, there may be a switch at the DAC output. The switch may be turned off by a calibration active signal, that is, the DAC output may be disabled during the calibration mode.

In some examples, MSB and LSB bits may not be equal. Assuming for example, LSB=N bits and MSB=M bits. Ideally, the resistance of the LSB segment RLSB_eqwhen all LSB resistors are electrically connected to the digital input lines should be equal to the value of each of the MSB resistors. However, it may be difficult to achieve this equivalence due factors such as process variations. The resistance mismatch in the order of ½Nor ½N+1may be permissible. However, the fabrication process may not guarantee a mismatch smaller than the permissible values, especially when the value of N is higher.

FIG.2shows the RC to frequency converter104that includes a capacitor resonance circuit114including one or more capacitors. The resistance of DAC (RDAC) when coupled with the capacitor of the capacitor resonance circuit114may form a RC resonance (in combination with parasitic inductance or additional inductance that may be included in the RC to frequency converter104) circuit to generate frequency fLcorresponding to RDAC. The frequency fHchanges with the changes in RDAC. Hence, a resistance variation may be detected by measuring fH(e.g., by dividing fHby fLto derive a counter value).

FIG.3shows an internal resistor network representation of the DAC102. As shown, the resistance of the LSB lines when switches SLSBs are ON thus RLSBs are coupled with the LSB inputs is represented as RLSB_eq. and the switches SLSBs are represented as SLSB_eqas if there is only one LSB bit. A binary or unary decoder may be used at LSB input side. On the MSB input side, the MSB inputs are coupled with a unary and one-hot decoder120. The unary or thermometer decoder may be used during the normal operational mode of the DAC when the calibrate signal is not active and a one-hot decoder may be used during the calibration mode when the calibrate signal is active. One-hot decoder is a circuit that, for a given input digital signal, outputs a digital code in which only one bit is 1 in the entire word. The unary or thermometer decoder may output an increasing digital output.

In some implementations, such as in R string implementation, the MSB side input lines may include 2Mnumber of resisters where M is the width of the MSB segment of the input digital signal. Table150ofFIG.4shows example values of the output of a thermometer decoder and a one-hot decoder for a three MSB bit input signal. Note that, three MSB bit signal is selected only for the purpose explanation in that the usage of the DAC calibration system100are not limited to three bit input signals. The MSB side resistor network may include trimmable resistors RMSB_1to RMSB_2M−1. The resistors RMSB_1to RMSB_2M−1are configured to be trimmed by control signals CTRL1to CTRL2M−1 respectively. The control signals are generated by the trimming controller112based on the input from the comparator110. The resistor network includes switches SMSB1to SMSB2M−1.

During the calibration mode, in some examples, the switches SMSB1to SMSB2M−1are turned off to float the MSB side resistors RMSB_1to RMSB_2M−1and the switch SLSB_eqis turned on (i.e., the LSB side resistors are electrically connected to the LSB input bits, in some example through a decoder). The RC to frequency converter104generate a signal having a frequency fLthat is a function of the resistance RLSB_eq. A first counter value is calculated by the monitor106using a high frequency clock of frequency fH. The first counter value is stored in the memory108. Subsequently, the switch SLSB_eqis turned off (thus floating the LSB side resistors) and the output of the one-hot decoder is applied to the MSB side input lines. Because the output of the one-hot decoder includes only one high bit, only one of the switches SMSB1to SMSB2M−1is on at a time. The frequency fL is measured by the monitor106as described above and a second counter value is calculated. The second counter value is stored in the memory108. The comparator110compares the first counter value and the second counter value and generates CTRLx (x=1 to 2M−1) to trim the resistor RMSB_xand the second counter value may be generated again based on the trimmed RMSB_x. The trimming loop may continue until the second counter value comes within a preconfigured threshold near the first counter value. The degree of closeness of the second counter value to the first counter value is proportional to the accuracy of the DAC102. The x may start at 1 or at 2M−1 or any arbitrary bit and may go up or down from the starting point depending on the starting point. The calculation of the second counter value and trimming of the RMSB_xmay be repeated for all MSB bits by changing the input signal as depicted in the table150ofFIG.4.

FIG.5depicts a flow chart of a method200for DAC self-calibration. Accordingly, at step202, the LSB side resistors are electrically connected to the LSB input bits and the MSB side resistors are floated by electrically disconnecting the MSB side resistors from the MSB input bits. At step204, based on the combined resistance of the LSB side resistors, the signal of frequency fLis generated by the RC to frequency converter104. In some embodiments, a terminal resistor may be coupled with the LSB side resistor network and the terminal resistor is electrically coupled with the LSB side resistors only during the calibration mode and RLSB_eqincludes the value of the terminal resistor. The frequency fLis a function of the value of the connected resistance with the capacitance of the RC to frequency converter104. At step206, a first counter value is calculated, in one example, by dividing a constant high frequency fHsignal that may be an on chip clock signal. At step208, the first counter value is stored in a volatile or non-volatile memory. At step210, the LSB side resistors (and the terminal resistor, if present) are floated by electrically disconnecting the LSB side resistors from the LSB input bit(s). At step212, using the one-hot decoder, connecting Nth bit MSB resistor to the corresponding input bit line and floating all other MSB side resistors. At step214, generate the frequency fLusing the RC to frequency converter104. At step216, a second counter value is calculated, for example, by dividing fHby fL. and similar to the first counter value, the second counter value is stored in the memory108At step218, the first counter value and the second counter value are compared by the comparator110that may output an up or down signal based on the comparison of the two values. Based on the output of the comparator110, the trimming controller112generates a control signal CTRL1. . . CTRLM−1 to trim the MSB resistor. The trimming loop for the MSB resistor may continue to loop till the second counter value comes within a predefined range from the first counter value. At step220, using the next output of the one-hot decoder, a next MSB resistor is selected to be trimmed and steps212to220are repeated until all MSB side resisters are trimmed.

Some or all of these embodiments may be combined, some may be omitted altogether, and additional process steps can be added while still achieving the products described herein. Thus, the subject matter described herein can be embodied in many different variations, and all such variations are contemplated to be within the scope of what is claimed.