Semiconductor device and manufacturing method thereof

A semiconductor device includes an isolation layer, first and second fin structures, a gate structure and a source/drain structure. The isolation layer is disposed over a substrate. The first and second fin structures are disposed over the substrate, and extend in a first direction in plan view. Upper portions of the first and second fin structures are exposed from the isolation layer. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The source/drain structure is formed on the upper portions of the first and second fin structures, which are not covered by the first gate structure and exposed from the isolation layer, and wraps side surfaces and a top surface of each of the exposed first and second fin structures. A void is formed between the source/drain structure and the isolation layer.

TECHNICAL FIELD

The disclosure relates to a semiconductor integrated circuit, and more particularly to a semiconductor device having an epitaxial source/drain (S/D) structure and its manufacturing process.

BACKGROUND

As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (Fin FET) and the use of a metal gate structure with a high-k (dielectric constant) material. The metal gate structure is often manufactured by using gate replacement technologies, and sources and drains are formed by using an epitaxial growth method.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.” Further, in the following fabrication process, additional operations can be provided before, during, and after the processes, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIG. 1is an exemplary perspective view of a semiconductor FET device having a fin structure (Fin FET).

The Fin FET devices include, among other features, a substrate10, a fin structure20, a isolation insulating layer30and a gate structure40. In this embodiment, the substrate10is a silicon substrate. Alternatively, the substrate10may comprise another elementary semiconductor, such as germanium; a compound semiconductor including IV-IV compound semiconductors such as SiC and SiGe, III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In one embodiment, the substrate10is a silicon layer of an SOI (silicon-on insulator) substrate. Amorphous substrates, such as amorphous Si or amorphous SiC, or insulating material, such as silicon oxide may also be used as the substrate10. The substrate10may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity).

One or more fin structures20are disposed over the substrate10. The fin structure20may be made of the same material as the substrate10and may continuously extend from the substrate10. In this embodiment, the fin structure is made of Si. The silicon layer of the fin structure20may be intrinsic, or appropriately doped with an n-type impurity or a p-type impurity.

InFIG. 1, one fin structure20is disposed over the substrate10. However, the number of the fin structures is not limited to one. The numbers may be more than one. In addition, one or more dummy fin structures may be disposed adjacent both sides of the fin structure20to improve pattern fidelity in patterning processes. The width of the fin structure20is in a range from about 5 nm to about 40 nm in some embodiments, and is in a range from about 7 nm to about 12 nm in other embodiments. The height of the fin structure20is in a range from about 100 nm to about 300 nm in some embodiments, and is in a range from about 50 nm to 100 nm in other embodiments.

The lower part of the fin structure20under the gate structure40may be referred to as a well region, and the upper part of the fin structure20may be referred to as a channel region. Under the gate structure40, the well region is embedded in the isolation insulating layer30, and the channel region protrudes from the isolation insulating layer30. A lower part of the channel region may also be embedded in the isolation insulating layer30to a depth of about 1 nm to about 5 nm.

The height of the well region is in a range from about 60 nm to 100 nm in some embodiments, and the height of the channel region is in a range from about 40 nm to 60 nm, and is in a range from about 38 nm to about 55 nm in other embodiments.

Further, spaces between the fin structures and/or a space between one fin structure and another element formed over the substrate10are filled by the isolation insulating layer30(or so-called a “shallow-trench-isolation (STI)” layer) including an insulating material. The insulating material for the isolation insulating layer30may include one or more layers of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material. The isolation insulating layer is formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. In the flowable CVD, flowable dielectric materials instead of silicon oxide may be deposited. Flowable dielectric materials, as their name suggest, can “flow” during deposition to fill gaps or spaces with a high aspect ratio. Usually, various chemistries are added to silicon-containing precursors to allow the deposited film to flow. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include a silicate, a siloxane, a methyl silsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS), a perhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silyl-amine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multiple-operation process. After the flowable film is deposited, it is cured and then annealed to remove un-desired element(s) to form silicon oxide. When the un-desired element(s) is removed, the flowable film densifies and shrinks. In some embodiments, multiple anneal processes are conducted. The flowable film is cured and annealed more than once. The flowable film may be doped with boron and/or phosphorous.

FIG. 2is an exemplary plan view of a Fin FET device after the gate structures are formed according to one embodiment of the present disclosure.FIGS. 3A-3Dshow exemplary cross sectional views along line X1-X1(FIG. 3A), Y1-Y1(FIG. 3B), X2-X2(FIG. 3C) and Y2-Y2(FIG. 3D) ofFIG. 2.

As shown inFIGS. 2 and 3A-3D, a first fin structure20A and a second fin structure20B are formed over the substrate10.

To fabricate fin structures according to one embodiment, a mask layer is formed over a substrate. The mask layer is formed by, for example, a thermal oxidation process and/or a chemical vapor deposition (CVD) process. The substrate10is, for example, a p-type silicon or germanium substrate with an impurity concentration in a range from about 1×1015cm−3to about 1×1016cm−3. In other embodiments, the substrate is an n-type silicon or germanium substrate with an impurity concentration in a range from about 1×1015cm−3to about 1×1016cm−3. The mask layer includes, for example, a pad oxide (e.g., silicon oxide) layer and a silicon nitride mask layer in some embodiments.

The pad oxide layer may be formed by using thermal oxidation or a CVD process. The silicon nitride mask layer may be formed by a physical vapor deposition (PVD), such as a sputtering method, a CVD, plasma-enhanced chemical vapor deposition (PECVD), an atmospheric pressure chemical vapor deposition (APCVD), a low-pressure CVD (LPCVD), a high density plasma CVD (HDPCVD), an atomic layer deposition (ALD), and/or other processes.

The thickness of the pad oxide layer is in a range from about 2 nm to about 15 nm and the thickness of the silicon nitride mask layer is in a range from about 2 nm to about 50 nm in some embodiments. A mask pattern is further formed over the mask layer. The mask pattern is, for example, a resist pattern formed by lithography operations.

By using the mask pattern as an etching mask, a hard mask pattern of the pad oxide layer and the silicon nitride mask layer is formed. The width of the hard mask pattern is in a range from about 5 nm to about 40 nm in some embodiments. In certain embodiments, the width of the hard mask patterns is in a range from about 7 nm to about 12 nm.

By using the hard mask pattern as an etching mask, the substrate10is patterned into fin structures by trench etching using a dry etching method and/or a wet etching method. The width of the fin structures is in a range from about 4 nm to about 15 nm in some embodiments and a space between two fin structures is in a range from about 10 nm to about 50 nm in some embodiments.

After the fin structures20A and20B are formed, the isolation insulating layer30is formed in spaces between the fin structures and/or a space between one fin structure and another element formed over the substrate10. The isolation insulating layer30may also be called a “shallow-trench-isolation (STI)” layer. The insulating material for the isolation insulating layer30may include one or more layers of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material. The isolation insulating layer is formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. In the flowable CVD, flowable dielectric materials instead of silicon oxide may be deposited. Flowable dielectric materials, as their name suggest, can “flow” during deposition to fill gaps or spaces with a high aspect ratio. Usually, various chemistries are added to silicon-containing precursors to allow the deposited film to flow. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include a silicate, a siloxane, a methyl silsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS), a perhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silyl-amine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multiple-operation process. After the flowable film is deposited, it is cured and then annealed to remove un-desired element(s) to form silicon oxide. When the un-desired element(s) is removed, the flowable film densifies and shrinks. In some embodiments, multiple anneal processes are conducted. The flowable film is cured and annealed more than once. The flowable film may be doped with boron and/or phosphorous.

The insulating layer30is first formed in a thick layer so that the fin structures are embedded in the thick layer, and the thick layer is recessed so as to expose the upper portions of the fin structures20A and20B. After or before recessing the isolation insulating layer30, a thermal process, for example, an anneal process, may be performed to improve the quality of the isolation insulating layer30. In certain embodiments, the thermal process is performed by using rapid thermal annealing (RTA) at a temperature in a range from about 900° C. to about 1050° C. for about 1.5 seconds to about 10 seconds in an inert gas ambient, such as an N2, Ar or He ambient.

After the insulating layer30is formed, a first gate structure40A and a second gate structure40B are formed over the fin structures20A and20B.

To fabricate the gate structures, a dielectric layer and a poly silicon layer are formed over the isolation insulating layer30and the exposed fin structures, and then patterning operations are performed so as to obtain gate structures including a gate pattern43made of poly silicon and a dielectric layer45. In some embodiments, the polysilicon layer is patterned by using a hard mask and the hard mask remains on the gate pattern43as a cap insulating layer47. The hard mask (cap insulating layer47) includes one or more layers of insulating material. The cap insulating layer47includes a silicon nitride layer formed over a silicon oxide layer in some embodiments. In other embodiments, the cap insulating layer47includes a silicon oxide layer formed over a silicon nitride layer. The insulating material for the cap insulating layer47may be formed by CVD, PVD, ALD, e-beam evaporation, or other suitable process. In some embodiments, the dielectric layer45may include one or more layers of silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectrics. In some embodiments, a thickness of the dielectric layer45is in a range from about 2 nm to about 20 nm, and in a range from about 2 nm to about 10 nm in other embodiments. In some embodiments, a thickness of the gate structures is in a range from about 50 nm to about 400 nm in some embodiments, and is in a range from about 100 nm to 200 nm in other embodiments.

In the present embodiment, a gate replacement technology is employed. Accordingly, the gate pattern43and the dielectric layer45are a dummy gate electrode and a dummy gate dielectric layer, respectively, which are subsequently removed.

Further, gate sidewall spacers54are formed on both sidewalls of the gate structures40A,40B, and fin sidewall spacers52are also formed on both sidewalls of the fin structures20A,20B. The sidewall spacers54,52include one or more layers of insulating material, such as SiO2, SiN, SiON, SiOCN or SiCN, which are formed by CVD, PVD, ALD, e-beam evaporation, or other suitable process. A low-k dielectric material may be used as the sidewall spacers. The sidewall spacers54,52are formed by forming a blanket layer of insulating material and performing anisotropic etching. As shown inFIG. 3B, the upper surfaces of the fin structures20A,20B are exposed. In one embodiment, the sidewall spacer layers are made of silicon nitride based material, such as SiN, SiON, SiOCN or SiCN. In one embodiment, the space S1between the fin structures20A and20B with the sidewall spaces is in a range from about 5 nm to about 30 nm.

Then, as shown inFIGS. 4A and 4B, the upper portions of the gate sidewall spacers54and the fin sidewall spacers52are partially removed (recessed).FIG. 4Ais an exemplary cross sectional view corresponding to line X1-X1ofFIG. 2, andFIG. 4Bis an exemplary cross sectional view corresponding to line Y1-Y1ofFIG. 2.

By using an anisotropic dry etching operation, the upper portions of the gate sidewall spacers54and the fin sidewall spacers52are partially removed (recessed). The recessed amount H1is in a range from about 10 nm to about 50 nm.

During this etching, the upper portions of the fin structures20A,20B are also slightly etched. Accordingly, the height of the fin structures20A,20B are reduced by the amount of H2.

Then, as shown inFIGS. 5A-5C, source/drain structures60are formed over the exposed upper portions of the fin structures20A,20B.FIG. 5Ais an exemplary cross sectional view corresponding to line X1-X1ofFIG. 2,FIG. 5Bis an exemplary cross sectional view corresponding to line Y1-Y1ofFIG. 2, andFIG. 5Cis an exemplary cross sectional view corresponding to line X2-X2ofFIG. 2.

The source/drain structures60are made of one or more layers of semiconductor material having a different lattice constant than the fin structures (channel regions). When the fin structures are made of Si, the source/drain structures60include SiP, SiC or SiCP for an n-channel Fin FET and SiGe or Ge for a p-channel Fin FET. The source/drain structures60are epitaxially formed over the upper portions of the fin structures20A,20B. Due to the crystal orientation of the substrate formed into the fin structures20A,20B (e.g., (100) plane), the source/drain structures60grow laterally and have a diamond-like shape. In one embodiment, the amount H2is set smaller than the lateral growth amount of the source/drain structures60. The lateral growth amount measured from the center of the fin structure is in a range from about S1to about 1.4×S1(see,FIG. 3B).

The source/drain epitaxial layer60may be grown at a temperature of about 600 to 800° C. under a pressure of about 80 to 150 Torr, by using a Si containing gas such as SiH4, Si2H6, SiCl2H2and a dopant gas, such as PH3. The source/drain structure for an n-channel FET and the source/drain structure for a p-channel FET may be formed by separate epitaxial processes.

As shown inFIG. 5B, since the upper portions of the fin structures20A,20B protrude from the isolation insulating layer30and the fin sidewall spacers52, the source/drain structures are formed on side surfaces and a top surface of the upper portions of the first and second fin structures20A and20B. As shown inFIG. 5A, the source/drain structures60grow above the uppermost portion of the fin structures20A,20B.

Further, due to the relatively small space between the fin structures, the source/drain structure formed over the first fin structure20A and the source/drain structure formed over the second fin structure20B are merged such that a void or a gap (an air gap)65is formed by the merged second source/drain structures60, the isolation insulating layer30, one of the gate sidewall spacers54of the first gate structure40A and one of the gate sidewall spacers of the second gate structure40B.

The height H3of the void65from the surface of the isolation insulating layer30is in a range from about 10 nm to about 40 nm in some embodiments.

Then, as shown inFIGS. 6A and 6B, a silicide layer70is formed over the source/drain structures60.FIG. 6Ais an exemplary cross sectional view corresponding to line X1-X1ofFIG. 2, andFIG. 6Bis an exemplary cross sectional view corresponding to line Y1-Y1ofFIG. 2.

After the source/drain structures60are formed, a metal material, such as Ni, Ti, Ta and/or W, is formed over the source/drain structures60, and an annealing operation is performed to form a silicide layer70. In other embodiments, a silicide material, such as NiSi, TiSi, TaSi and/or WSi, is formed over the source/drain structures60, and an annealing operation may be performed. The annealing operation is performed at a temperature of about 250° C. to about 850° C. The metal material or the silicide material is formed by CVD or ALD. The thickness of the silicide layer70is in a range from about 4 nm to about 10 nm in some embodiments. Before or after the annealing operations, the metal material or the silicide material formed over the isolation insulating layer30, the cap isolation layer47and the sidewall spacers52,54are selectively removed, by using a wet etching process.

Then, as shown inFIGS. 7A and 7B, a metal gate structure is formed and subsequently, a contact plug is formed.FIG. 7Ais an exemplary cross sectional view corresponding to line X1-X1ofFIG. 2, andFIG. 7Bis an exemplary cross sectional view corresponding to line Y1-Y1ofFIG. 2.

After forming the silicide layer70, the dummy gate structures (dummy gate electrode43and dummy gate dielectric layer45) are removed and replaced with a metal gate structures (metal gate electrode90and gate dielectric layer95).

In certain embodiments, a first interlayer dielectric layer is formed over the dummy gate structures and a planarization operation, such as a chemical mechanical polishing (CMP) process or an etch-back process, is performed to expose the upper surface of the dummy gate electrode43. Then, the dummy gate electrode43and the dummy gate dielectric layer45are removed, by appropriate etching processes, respectively, to form a gate opening. Metal gate structures including a gate dielectric layer95and metal gate electrode90are formed in the gate openings.

The gate dielectric layer95may be formed over an interface layer (not shown) disposed over the channel layer of the fin structures20A,20B. The interface layer may include silicon oxide or germanium oxide with a thickness of 0.2 nm to 1.5 nm in some embodiments. In other embodiments, the thickness of the interface layer is in a range about 0.5 nm to about 1.0 nm.

The gate dielectric layer95includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. The gate dielectric layer is formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), or other suitable methods, and/or combinations thereof. The thickness of the gate dielectric layer is in a range from about 1 nm to about 10 nm in some embodiments, and may be in a range from about 2 nm to about 7 nm in other embodiments.

In certain embodiments of the present disclosure, one or more work function adjustment layers (not shown) may be interposed between the gate dielectric layer95and the metal gate electrode90. The work function adjustment layer is made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-channel Fin FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function adjustment layer, and for the p-channel Fin FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer.

After depositing appropriate materials for the metal gate structures, planarization operations such as a CMP are performed.

Then, a second interlayer dielectric layer85is formed over the formed metal gate structure. In some embodiments, an insulating layer80, functioning as a contact etching stop layer, is formed over the formed metal gate structure and then the second interlayer dielectric layer85is formed.

The insulating layer80is one or more layers of insulating material. In one embodiment, the insulating layer80is made of silicon nitride formed by CVD.

By using a patterning operation including lithography, contact holes are formed in the second interlayer dielectric layer85and the insulating layer80, so as to expose source and drain structures60with the silicide layer70. Then, the contact hole is filled with a conductive material, thereby forming a contact plug100. The contact plug100may include a single layer or multiple layers of any suitable metal such as Co, W, Ti, Ta, Cu, Al and/or Ni and/or nitride thereof.

After forming the contact plug, further CMOS processes are performed to form various features such as additional interlayer dielectric layer, contacts/vias, interconnect metal layers, and passivation layers, etc.

FIG. 8is an exemplary cross sectional view of a Fin FET device according to another embodiment of the present disclosure. In the embodiment ofFIG. 8, three fin structures are disposed over the substrate and two voids65are formed in the spaces between adjacent two fin structures.

FIGS. 9A-11Bshow exemplary cross sectional views of various stages for manufacturing a Fin FET device according to another embodiment of the present disclosure. In this embodiment, the timing of forming the silicide layer is different from the above embodiment. The configuration, materials or operations the same as or similar to those in the above embodiment may be employed in this embodiment, and the detailed explanation thereof may be omitted.

After forming the source/drain structures60as shown inFIGS. 5A-5C, the metal gate structures90,95, the insulating layer80(contact etching stop layer) and the interlayer dielectric layer85are formed, without forming a silicide layer, as shown inFIGS. 9A and 9B.FIG. 9Ais an exemplary cross sectional view corresponding to line X1-X1ofFIG. 2, andFIG. 9Bis an exemplary cross sectional view corresponding to line Y1-Y1ofFIG. 2.

Then, as shown inFIGS. 10A and 10B, contact holes105are formed in the insulating layer80and the interlayer dielectric layer85to expose the upper surface of the source/drain structures60, and then a silicide layer75is formed on the upper surface of the source/drain structures60.FIG. 10Ais an exemplary cross sectional view corresponding to line X1-X1ofFIG. 2, andFIG. 10Bis an exemplary cross sectional view corresponding to line Y1-Y1ofFIG. 2.

After forming the silicide layer75, the conductive material is formed in the contact holes105, thereby forming contact plugs100, as shown inFIGS. 11A and 11B.FIG. 11Ais an exemplary cross sectional view corresponding to line X1-X1ofFIG. 2, andFIG. 11Bis an exemplary cross sectional view corresponding to line Y1-Y1ofFIG. 2.

After forming the contact plugs, further CMOS processes are performed to form various features such as additional interlayer dielectric layer, contacts/vias, interconnect metal layers, and passivation layers, etc.

In the present disclosure, since a void is formed between the source/drain epitaxial layer and the isolation insulting layer (STI), a parasitic capacitance at the source/drain structure can be reduced.

In accordance with one aspect of the present disclosure, in a method of manufacturing a semiconductor device including a Fin FET, a first fin structure and a second fin structure are formed over a substrate. The first and second fin structures extend in a first direction in plan view. An isolation insulating layer is formed over the substrate so that lower portions of the first and second fin structures are embedded in the isolation insulating layer and upper portions of the first and second fin structures are exposed from the isolation insulating layer. A gate structure is formed over parts of the first and second fin structure. The gate structure includes a gate pattern, a dielectric layer disposed between the gate pattern and the first and second fin structures, a cap insulating layer disposed over the gate pattern. The gate structure extends in a second direction crossing the first direction in plan view. Gate sidewall spacers are formed on sidewalls of the gate structure. Upper portions of the gate sidewall spacers are recessed. A first source/drain structure is formed over the first fin structure not covered by the gate structure and the gate sidewall spacers, and a second source/drain structure is formed over the second fin structure not covered by the gate structure and the gate sidewall spacers. In the recessing the upper portions of the gate sidewall spacers, upper portions of the first and second fin structures not covered by the gate structure are also recessed. In the forming the first source/drain structure, the first source/drain structure is formed on side surfaces and a top surface of the recessed first and second fin structures. The first and second source/drain structures are merged such that a void is formed between the merged first and second source/drain structures and the isolation insulating layer.

In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device including a Fin FET, a first fin structure and a second fin structure are formed over a substrate. The first and second fin structures extend in a first direction in plan view. An isolation insulating layer is formed over the substrate so that lower portions of the first and second fin structures are embedded in the isolation insulating layer and upper portions of the first and second fin structures are exposed from the isolation insulating layer. A first gate structure and a second gate structure are formed over parts of the first and second fin structure. Each of the first and second gate structures includes a gate pattern, a dielectric layer disposed between the gate pattern and the first and second fin structures, a cap insulating layer disposed over the gate pattern. The first and second gate structures extend in a second direction crossing the first direction in plan view. First gate sidewall spacers are formed on sidewalls of the first gate structure, and second gate sidewall spacers are formed on sidewalls of the second gate structure. Upper portions of the first and second gate sidewall spacers are recessed. A first source/drain structure is formed over the first fin structure not covered by the first and second gate structures and the first and second gate sidewall spacers, and a second source/drain structure is formed over the second fin structure not covered by the first and second gate structures and the first and second gate sidewall spacers. In the recessing the upper portions of the first and second gate sidewall spacers, upper portions of the first and second fin structures not covered by the first and second gate structures are also recessed. In the forming the first source/drain structure, the first source/drain structure is formed on side surfaces and a top surface of the recessed first and second fin structures. The first and second source/drain structures are merged such that a void formed by the merged first and second source/drain structures, the isolation insulating layer, one of the first gate sidewall spacers and one of the second gate sidewall spacers, the one of the first gate sidewall spacers facing the one of the second gate sidewall spacers.

In accordance with another aspect of the present disclosure, a semiconductor device includes an isolation insulating layer, a first fin structure and a second fin structure, a first gate structure, and a source/drain structure. The isolation insulating layer is disposed over a substrate. Both the first fin structure and the second fin structure are disposed over the substrate. The first and second fin structures extend in a first direction in plan view. Upper portions of the first and second fin structures are exposed from the isolation insulating layer. The first gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The source/drain structure is formed on the upper portions of the first and second fin structures, which are not covered by the first gate structure and exposed from the isolation insulating layer, and wrapping side surfaces and a top surface of each of the exposed first and second fin structures. A void is formed between the source/drain structure and the isolation insulating layer.