Voltage regulation system for integrated circuit

An integrated circuit (IC) with voltage regulation includes high power and low power domains, low and high voltage regulators and a low power regulator. The low voltage regulator powers the high and low power domains when the IC is in a HIGH power mode. The low power regulator receives a voltage from a high voltage regulator and powers the low power domain when the IC is in a LOW power mode. The IC includes a switching module that disconnects the low voltage regulator from the low power domain when the output voltage of the high voltage regulator is lower than a threshold voltage during power-up and connects the low voltage regulator to the low power domain when the voltage regulated by the high voltage regulator exceeds the threshold voltage.

BACKGROUND OF THE INVENTION

The present invention relates generally to integrated circuits, and, more particularly, to a voltage regulation system for an integrated circuit.

Many integrated circuits (ICs) today including system-on-chips (SoCs) integrate various digital and analog components on a single chip. Such ICs also include different power domains including high and low power domains. The high power domain includes components that operate when the IC is in a HIGH power mode and are powered down when the IC is in a LOW power mode. The low power domain includes components that operate when the IC is in the HIGH and LOW power modes. ICs with multiple power domains require multiple power supplies that are served by voltage regulators. The voltage regulators provide different voltages to the components in the high and low power domains based on the IC mode of operation.

FIG. 1is a schematic block diagram of a conventional integrated circuit (IC)100that is operable in both HIGH and LOW power modes and includes a low voltage regulator102(hereinafter “LV regulator”), a high voltage regulator104(hereinafter “HV regulator”), a low power low voltage regulator106(hereinafter “LP_LV regulator”), a low power domain108, a high power domain110, and a switch112. The LV and HV regulators102and104are connected to an external power supply (not shown). The switch112is connected between the LV regulator102and the low power domain108. The LV regulator102provides a first regulated voltage VLVto both the low and high power domains108and110when the IC100is in the HIGH power mode and is switched off when the IC100is in the LOW power mode. The HV regulator104generates a second regulated voltage VHVwhen the IC100is in either of the HIGH or LOW power modes. The LP_LV regulator106receives the second regulated voltage VHVand provides a third regulated voltage VLP—LVto the low power domain108when the IC100is in the LOW power mode. The LP_LV regulator106is an internal low power regulator implemented using a p-type, metal-oxide semiconductor (PMOS) transistor114having its source and body terminals connected together. An intrinsic diode116is formed between the drain and source or body terminals of the PMOS transistor114. In order to avoid undesirable circuit behavior, the intrinsic diode116is usually kept reverse biased (e.g., VLP—LV<VHV).

The low power domain108functions in both the HIGH and LOW power modes, while the high power domain110functions in the HIGH power mode and is powered down in the LOW power mode. The switch112is closed when the IC100is in the HIGH power mode, which allows the LV regulator102to provide the first regulated voltage VLVto the low power domain108.

In both the HIGH and LOW power modes, the first regulated voltage VLVis lower than the second regulated voltage VHV. Therefore, the intrinsic diode116is reverse biased because its body terminal is at a higher potential than its drain terminal. However, conditions such as power-on-reset (POR), sudden failure, and accidental resets may cause the IC100to reset, causing the IC100to power-on and transition to the HIGH power mode (referred to as power-up). During power-up, the output voltage of the LV regulator102may reach a steady-state voltage level before the output voltage of the HV regulator104. Therefore, the output voltage of the LV regulator102may be higher than the output voltage of the HV regulator104for a transient period. Since the switch112is closed during power-up, the intrinsic diode116in the LP_LV regulator106is forward biased, causing a short-circuit path between the LV and HV regulators102and104, by way of the switch112and the LP_LV regulator106. When such a condition occurs, a high supply current is drawn from the LV regulator102, which can damage some internal components of the IC100.

One technique to overcome the aforementioned problem is to employ a specific power sequence. Power sequencing controls the order in which the LV and HV regulators102and104are powered up or down. However, power sequencing is not always desirable because it requires complex applications to prevent the aforementioned problem. Another known technique entails applying a high voltage to a well region of the PMOS transistor114, which renders the intrinsic diode116non-conductive and thus prevents the short-circuit path. However, applying this high voltage increases power consumption of the IC100.

Therefore, it would be advantageous to have a voltage regulating system in an integrated circuit that avoids damaging internal components of the integrated circuit caused by the aforementioned problem.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

In an embodiment of the present invention, an integrated circuit (IC) capable of operating in HIGH and LOW power modes is provided. The IC includes low and high power domains, first, second and third voltage regulators, and a switching module. The first voltage regulator regulates a voltage provided to the low and high power domains at a first voltage level when the IC is in the HIGH power mode and is switched off when the IC is in the LOW power mode. The second voltage regulator generates a voltage that is regulated at a second voltage level and operates when the IC is in either the HIGH or LOW power modes. The third voltage regulator is connected between the second voltage regulator and the low power domain. The third voltage regulator receives the voltage regulated by the second voltage regulator and regulates a voltage provided to the low power domain at a third voltage level when the IC is in the LOW power mode and is switched off when the IC is in the HIGH power mode. The switching module is connected to the second voltage regulator, and between the first voltage regulator and the low power domain. The switching module receives and compares the voltage regulated by the second voltage regulator with a threshold voltage, and connects the first voltage regulator to the low power domain when the voltage regulated by the second voltage regulator exceeds the threshold voltage.

In another embodiment of the present invention, an integrated circuit includes low and high power domains, first, second and third voltage regulators, a voltage monitor module, a safe-state module, and a power switch module. The IC is capable of operating in HIGH and LOW power modes. The first voltage regulator regulates a voltage provided to the low and high power domains at a first voltage level when the IC is in the HIGH power mode and is switched off when the IC is in the LOW power mode. The second voltage regulator generates a voltage that is regulated at a second voltage level and operates when the IC is in the HIGH and LOW power modes. The third voltage regulator is connected between the second voltage regulator and the low power domain. The third voltage regulator receives the voltage regulated by the second voltage regulator and regulates a voltage provided to the low power domain at a third voltage level when the IC is in the LOW power mode, and is switched off when the IC is in the HIGH power mode. The voltage monitor module is connected to the second voltage regulator and receives and compares the voltage regulated by the second voltage regulator with a threshold voltage and generates a voltage monitor signal when the voltage regulated by the second voltage regulator exceeds the threshold voltage. The safe-state module is connected to the voltage monitor module and receives the voltage monitor signal, a first control signal, and a selected voltage level, and generates a safe-state signal. The power-switch module is connected to the safe-state module and between the first voltage regulator and the low power domain. The power-switch module connects the first voltage regulator to the low power domain based on the safe-state signal.

In yet another embodiment of the present invention, an integrated circuit is provided that includes low and high power domains, first, second and third voltage regulators, first and second comparators, a first logic gate, a level-shifter, a first logic circuit, an n-channel metal oxide semiconductor (NMOS) transistor, a first transistor, and a supply selector module. The IC is capable of operating in HIGH and LOW power modes. The first voltage regulator regulates a voltage provided to the low and high power domains at a first voltage level when the IC is in the HIGH power mode and is switched off when the IC is in the LOW power mode. The second voltage regulator generates a voltage that is regulated at a second voltage level and operates when the IC is in the HIGH and LOW power modes. The third voltage regulator is connected between the second voltage regulator and the low power domain. The third voltage regulator receives the voltage regulated by the second voltage regulator and regulates a voltage provided to the low power domain at a third voltage level in the LOW power mode and is switched off in the HIGH power mode. The first comparator receives a first threshold voltage and the voltage regulated by the second voltage regulator and generates a first voltage monitor signal when the voltage regulated by the second voltage regulator exceeds the first threshold voltage. The second comparator receives a second threshold voltage and a first node voltage obtained at a node between the low power domain and the third voltage regulator, and generates a second voltage monitor signal when the first node voltage exceeds the second threshold voltage. The level-shifter is connected to the low power domain, and receives a reference signal and level shifts a voltage level of the reference signal from the third voltage level to the second voltage level. The first logic gate receives the second voltage monitor signal and the level-shifted reference signal and generates a first control signal. The first logic circuit receives the first voltage monitor signal and the first control signal and generates a second control signal. The NMOS transistor has a source terminal connected to ground and a body terminal connected to its the source terminal. A gate terminal of the NMOS transistor is connected to the first logic circuit for receiving the second control signal and generating a safe-state signal at its drain terminal. The first transistor has a source terminal connected to the first voltage regulator, a drain terminal connected to the low power domain, and a gate terminal connected to the drain terminal of the NMOS transistor. The first transistor receives the safe-state signal at its gate terminal from the drain terminal of the NMOS transistor, and connects the first voltage regulator to the low power domain based on the safe-state signal. The supply selector module is connected to the source and drain terminals of the first transistor, and selects and provides a higher one of the voltages at the source and drains terminals of the first transistor as the selected voltage to the drain terminal of the NMOS transistor by way of a pull-up resistor and the body terminal of the first transistor.

Various embodiments of the present invention provide a system for regulating voltage in an IC. The IC includes low and high power domains, first, second and third voltage regulators, and a switching module. The IC is capable of operating in HIGH and LOW power modes. The first voltage regulator is a low voltage regulator and regulates a voltage provided to the low power and high power domains at a first voltage level in the HIGH power mode and is switched off in the LOW power mode. The second voltage regulator is a high voltage regulator and generates a voltage that is regulated at a second voltage level, greater than the first voltage level, and operates in the HIGH and LOW power modes. The third voltage regulator receives the voltage regulated by the high voltage regulator and regulates a voltage provided to the low power domain at a third voltage level in the LOW power mode and is switched off in the HIGH power mode. During conditions such as power-on-reset (POR), sudden failure, and accidental resets, the IC resets and powers-on and transitions to the HIGH power mode (known as power-up). During power-up, the voltage regulated by the low voltage regulator may ramp up faster than the voltage regulated by the high voltage regulator. When this occurs, the output voltage level of the low voltage regulator is higher than that of the high voltage regulator for a brief time period until the voltage regulated by the high voltage regulator exceeds the voltage regulated by the low voltage regulator. The switching module receives and compares the voltage regulated by the high voltage regulator with a threshold voltage that is substantially equal to the first voltage level. When the output voltage of the high voltage regulator is less than the threshold voltage, the switching module disconnects the low voltage regulator from the low power domain and prevents an intrinsic diode of the third voltage regulator from being forward biased. This technique consumes less power than conventional techniques. When the voltage regulated by the high voltage regulator exceeds the threshold voltage, the switching module connects the low voltage regulator to the low power domain.

Referring now toFIG. 2, a schematic block diagram of an integrated circuit (IC)200in accordance with an embodiment of the present invention is shown. The IC200includes a first voltage regulator202(hereinafter low voltage or LV regulator), a second voltage regulator204(hereinafter high voltage or HV regulator), a third voltage regulator206(hereinafter low power or LP_LV regulator”), low and high power domains208and210, and a switching module212. The LP_LV regulator206is a low power regulator including a PMOS transistor214having its source and body terminals connected together. An intrinsic diode216is formed between the drain and body terminals of the PMOS transistor214. In order to avoid undesirable circuit behavior, the intrinsic diode216is reverse-biased.

The IC200operates in HIGH and LOW power modes. In the HIGH power mode, both the low and high power domains208and210are operational, and the LV regulator202provides a first regulated voltage VLV(at a first voltage level) to the low power domain208by way of the switching module212, and directly to the high power domain210. On the other hand, in the LOW power mode, the low power domain208is operational and the high power domain210is power-gated (switched off) by switching off the LV regulator202and disconnecting the high power domain210from the low power domain208using the switching module212. The HV regulator204generates a second regulated voltage VHV(at a second voltage level). The LP_LV regulator206receives the second regulated voltage VHVand generates a third regulated voltage VLP—LV(at a third voltage level), which it provides to the low power domain208. The PMOS transistor214has its source and body terminals connected to the HV regulator204and its drain terminal connected to the low power domain208.

The switching module212includes a voltage monitor module218, a safe-state module220and a power-switch module222. The voltage monitor module218includes a first comparator224, which has a first input terminal connected to the HV regulator204for receiving the output voltage of the HV regulator204and a second input terminal connected to a first bandgap voltage source (not shown) for receiving a first threshold voltage V1. In one embodiment, the magnitude of the first threshold voltage V1is substantially equal to the first voltage level. In another embodiment, the first threshold voltage V1may be marginally lower than the first voltage level such that the difference between the first voltage level and the first threshold voltage V1is less than a turn-on voltage of the intrinsic diode216. In yet another embodiment, the first threshold voltage V1may be greater than the first regulated voltage VLV. For example, if the first voltage level is 1.25V and the turn-on voltage of the intrinsic diode216is 200 mV, i.e., 0.2V, then the magnitude of the first threshold voltage V1can be greater than 1.23V and it may attain a magnitude as high as 2.7V, which is the minimum operational value of the output voltage of the HV regulator204.

The first comparator224generates a first voltage monitor signal VVM1—B—HVat its output terminal. The voltage monitor module218is powered by the HV regulator204. If the HV regulator204is mistakenly turned OFF, i.e., when the second regulated voltage VHVis not available, the first voltage monitor signal VVM1—B—HVis pulled down to a ground level (logic low state). In another embodiment of the present invention, the voltage monitor module218may include a power-on-reset (POR) circuit.

A second comparator226has a first input terminal connected to a node A, which is at a junction between the low power domain208, the LP_LV regulator206and the switching module212, for receiving a first node voltage VA, and a second input terminal connected to a second bandgap voltage source (not shown), for receiving a second threshold voltage V2. The magnitude of the second threshold voltage V2is marginally lower than the first and third voltage levels. For example, if the first and third voltage levels are 1.25 v, then the second threshold voltage V2is about 0.9 v. The second comparator226generates a second voltage monitor signal VVM2—B—HVat its output terminal. A level-shifter228receives a reference signal VCLOSE—LVfrom the low power domain208and shifts a voltage level of the reference signal VCLOSE—LVfrom the third voltage level to the second voltage level. A first logic gate230has an input terminal connected to the output of the second comparator226for receiving the second voltage monitor signal VVM2—B—HV, and an inverted input terminal connected to the output of the level-shifter228for receiving the level-shifted reference signal VCLOSE—LV. The first logic gate230generates a first control signal VCLOSEat its output terminal.

The safe-state module220includes a first logic circuit232and an NMOS transistor234. The first logic circuit232has a first input terminal connected to the output terminal of the first comparator circuit224for receiving the first voltage monitor signal VVM1—B—HVand a second input terminal connected to the output terminal of the first logic gate230for receiving the first control signal VCLOSE. The first logic circuit232generates a second control signal VCLOSE—HVat its output terminal. The NMOS transistor234has a gate terminal connected to the output terminal of the first logic circuit232for receiving the second control signal VCLOSE—HV, a source terminal connected to ground, and a drain terminal connected to the power-switch module222as well as to a pull-up resistor236for receiving a selected voltage level VMAX. The drain terminal of the NMOS transistor234generates a safe-state signal VCLOSE—B—LV. The safe-state module220is powered by the HV regulator204. If the HV regulator204is turned OFF accidentally, i.e., when the second regulated voltage VHVis not available, the second control signal VCLOSE—HVis pulled down to ground level (logic low state). In an embodiment of the present invention, the first logic circuit232is an AND gate.

The power-switch module222includes a power-switch238and a supply selector module240. In the present embodiment, the power-switch238comprises a PMOS transistor. The power-switch238has a gate terminal connected to the drain terminal of the NMOS transistor234for receiving the safe-state signal VCLOSE—B—LV, a source terminal connected to the LV regulator202, and a drain terminal connected to the low power domain208. The supply selector module240is connected to the source and drain terminals of the power-switch238. The supply selector module240selects and provides a higher of the voltages between the source and drain terminals of the power-switch238as the selected voltage level VMAXto the safe-state module220as well as to a body terminal of the power-switch238.

FIG. 3shows a plurality of timing diagrams illustrating the voltage regulated by the LV and HV regulators202and204, the first threshold voltage V1, the first voltage monitor signal VVM1—B—HV, the first node voltage VA, the second threshold voltage V2, the second voltage monitor signal VVM2—B—HV, the reference signal VCLOSE—LV, the first control signal VCLOSE—LVthe second control signal VCLOSE—HV, the safe-state signal VCLOSE—B—LVand the selected voltage level VMAX. When the IC200is in the LOW and HIGH power modes, the intrinsic diode216is reverse biased. Conditions such as power-on-reset (POR), sudden failure, and accidental resets may cause the IC200to reset, causing the IC200to power-on and transition to the HIGH power mode (referred to as power-up). During power-up, both the LV and HV regulators202and204are reset. The output voltage of the LV regulator202starts ramping up at time T0and reaches the first voltage level (i.e., the first regulated voltage VLV) at time T1. The output voltage of the HV regulator204starts ramping up between time T1and T2and reaches the second voltage level (i.e., the second regulated voltage VHV) at time T5.

From T0to T2, the output voltage of the LV regulator202is higher than the output voltage of the HV regulator204. Until time T3, the output voltage of the HV regulator204is less than the first threshold voltage V1. The first input terminal of the first comparator circuit224receives the output voltage of the HV regulator204and the second input terminal of the first comparator circuit224receives the first threshold voltage V1. Since the output voltage of the HV regulator204is less than the first threshold voltage V1during T0to T3, the first comparator circuit224generates a logic low first voltage monitor signal VVM1—B—HV. The first logic circuit232receives the logic low first voltage monitor signal VVM1—B—HVand generates a logic low second control signal VCLOSE—HVat its output terminal. Since the first voltage monitor signal VVM1—B—HVis low, the output of the first logic circuit232is independent of the first control signal VCLOSEreceived at the second input terminal of the first logic circuit232. The gate terminal of the NMOS transistor234receives the logic low second control signal VCLOSE—HV. As a result, the NMOS transistor234is turned off its drain terminal is pulled up to the selected voltage level VMAXdue to the pull-up resistor232. Thus, from time T0to T3, the second control signal VCLOSE—HVis low and the safe-state signal VCLOSE—B—LVis at the selected voltage level VMAX, as shown inFIG. 3. Since the gate terminal of the power-switch238receives the logic high safe-state signal VCLOSE—B—LV, which is at the selected voltage level VMAX, the drain terminal of the power-switch238is at high impedance. Therefore, the power-switch238is turned OFF (meaning the NMOS transistor is open). Thus, the LV regulator202is disconnected from the low power domain208and the LP_LV regulator206from time T0to T3, and the intrinsic diode216remains reverse biased.

After time T3, the output voltage of the HV regulator204becomes higher than the first threshold voltage V1, which causes the first comparator circuit224to generate a logic high first voltage monitor signal VVM1—B—HV.

At time T3, the IC200starts operating in the HIGH power mode. The LP_LV regulator206is turned OFF when the IC200is powering-up and is in the HIGH power mode. Since the power-switch is open, the first node voltage VAis at ground level and thus is less than the second threshold voltage V2so the second comparator circuit226generates a logic low second voltage monitor signal VVM2—B—HV. The first logic gate230receives the logic low second voltage monitor signal VVM2—B—HVand generates a logic high first control signal VCLOSE. The first logic circuit232receives the logic high first voltage monitor signal VVM1—B—HVand the logic high first control signal VCLOSEand generates a logic high second control signal VCLOSE—HV. The logic high second control signal VCLOSE—HVis inverted to a logic low safe-state signal VCLOSE—B—LVby the NMOS transistor234. As the gate terminal of the power-switch238receives the logic low safe-state signal VCLOSE—B—LV, the power-switch238is turned ON. The drain terminal of the power-switch238is pulled up to the first voltage level of the source terminal of the power-switch238. Therefore, at time T3, the LV regulator202is connected to the low power domain208as the power-switch238starts conducting. Thus, the power-switch238is closed at time T3. Since the first regulated voltage VLVis less than the output voltage of the HV regulator204, the intrinsic diode216is reverse-biased.

From time T3to T4, the power-switch238remains closed and the first node voltage VAstarts increasing to the first voltage level. At time T4, the first node voltage VAexceeds the second threshold voltage V2. Therefore, the second comparator circuit226generates a logic high second voltage monitor signal VVM2—B—HV. The logic high second voltage monitor signal VVM2—B—HVindicates that the reference signal VCLOSE—LVgenerated by the low power domain208is valid and may be used to control the state of the power-switch238. The low power domain208generates a logic high reference signal VCLOSE—LVwhen the IC200operates in the HIGH power mode. The level-shifter228shifts the logic high reference signal VCLOSE—LV. The first logic gate230receives the level-shifted logic high reference signal VCLOSE—LVand the logic high second voltage monitor signal VVM2—B—HVand generates a logic high first control signal VCLOSE. The first logic circuit232receives the logic high first voltage monitor signal VVM1—B—HVand the logic high first control signal VCLOSEand generates a logic high second control signal VCLOSE—HV. The logic high second control signal VCLOSE—HVis inverted by the NMOS transistor234to the logic low safe-state signal VCLOSE—B—LV. As the gate terminal of the power-switch238receives the logic low safe-state signal VCLOSE—B—LV, the power-switch238remains ON. The drain terminal of the power-switch238remains at the first voltage level of the source terminal of the power-switch238. As shown inFIG. 3, from time T4to T6, even though the voltage levels of the voltage regulated by the HV regulator204, the first voltage monitor signal VVM1—B—HV, the first node voltage VA, the second voltage monitor signal VVM2—B—HV, the reference signal VCLOSE—LVthe first control signal VCLOSE, and the second control signal VCLOSE—LVare changing, the logic states of these signals remain constant. Thus, the power-switch238remains ON and continues conducting. That is, the NMOS transistor238remains closed from time T4to T6.

At time T6, the IC200begins operating in the LOW power mode and the LV regulator202is turned OFF. Thus, the output voltage of the LV regulator202drops to zero. Since the IC200is in the LOW power mode, the LP_LV regulator206is turned ON and provides the third regulated voltage VLP—LVat the third voltage level to the low power domain208. Therefore, after time T6, the first node voltage VAis at the third voltage level. Since the first node voltage VAexceeds the second threshold voltage V2, the second comparator circuit226generates the logic high second voltage monitor signal VVM2—B—HV. Since the IC200is in the LOW power mode, the low power domain208generates a logic low reference signal VCLOSE—LV. The level-shifter228shifts the logic low reference signal VCLOSE—LV. The first logic gate230receives the level-shifted logic low reference signal VCLOSE—LVand the logic high second voltage monitor signal VVM2—B—HVand generates a logic low first control signal VCLOSE. The first logic circuit232receives the logic high first voltage monitor signal VVM1—B—HVand the logic low first control signal VCLOSEand generates a logic low second control signal VCLOSE—HV. The gate terminal of the NMOS transistor234receives the logic low second control signal VCLOSE—HV. The NMOS transistor234is turned off and its drain terminal is pulled up to the selected voltage level VMAX. The gate terminal of the power-switch238receives the logic high safe-state signal VCLOSE—B—LVwhich is at the selected voltage level VMAXand therefore, the power-switch238is turned OFF. Thus, when the IC200operates in the LOW power mode, the power-switch238is open and the high power domain210is disconnected from the low power domain208after time T6.

When the IC200transitions from the LOW power mode to the HIGH power mode, the LP_LV regulator206is turned off and the LV regulator202is turned ON. Since the IC200is in the HIGH power mode, the low power domain208generates a logic high reference signal VCLOSE—LV. Therefore, the first control signal VCLOSEis at logic high state. As a result, the second control signal VCLOSE—HVis at logic high state, which is inverted to the logic low safe-state signal VCLOSE—B—LV. The gate terminal of the power-switch238receives the logic low safe-state signal VCLOSE—B—LV. Therefore, the power-switch238is turned ON (closed) and the high power domain210is connected to the low power domain208. If the HV regulator204is turned OFF accidentally during power-up and the second regulated voltage VHVis unavailable, the first voltage monitor signal VVM1—B—HVand the second control signal VCLOSE—HVare pulled down to ground level (logic low). The NMOS transistor234inverts the logic low second control signal VCLOSE—HVto the logic high safe-state signal VCLOSE—B—LV, which turns OFF the power-switch238. Thus, if the HV regulator204is turned OFF, the power-switch238is open, which ensures that the power-switch is open when the IC200powers-up.

It will be understood by those of skill in the art that the switching module212is an exemplary embodiment and may be replaced with a suitable equivalent switching arrangement that is capable of connecting and disconnecting the LV regulator202from the low power domain208. In an embodiment of the present invention, the first threshold voltage V1may be equal to the first voltage level.

It will be further understood by those of skill in the art that the same logical function may be performed by different arrangements of logic gates, or that logic circuits operate using either positive or negative logic signals. Therefore, variations in the arrangement of some of the logic gates described above should not be considered to depart from the scope of the present invention.