Semiconductor memory module

A semiconductor memory module includes a wiring board in or on which at least a number of data line runs are conducted in a respective width of k bits and which exhibits a number of memory ranks which in each case have n memory chips, and at least one signal driver/control chip (hub), a k-bit-wide data line run in each case connecting a memory chip from each memory rank to the signal driver/control chip (hub) and four or eight memory ranks in each case being arranged distributed on the top and bottom of the wiring board along the associated data line run in such a manner that, in operation, the load is distributed along the respective data line run.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 USC §119 to German Application No. 103 39 891.0, filed on Aug. 29, 2003, and titled “Semiconductor Memory Module,” and to German Application No. DE 10 2004 040 459.3, filed Aug. 20, 2004, and titled “Semiconductor Memory Module,” the entire contents of which are hereby incorporated by reference.

FIELD OF THE INVENTION

The invention relates to a semiconductor memory module including a wiring board in or on which at least a number of data line runs are conducted in a respective width of k bits, and, more particularly, the memory board of the semiconductor memory module exhibits a number of memory ranks which in each case include n memory chips, and at least one signal driver/control chip (hub), a k-bit-wide data line run in each case connecting a memory chip from each memory rank to the signal driver/control chip (hub).

BACKGROUND

In a “buffered DIMM”, i.e., a DIMM semiconductor memory module on which there is a signal driver/control chip (hub) as is currently planned for DDR2and DDR3semiconductor memory modules, two ranks per semiconductor memory module are normally arranged. A rank comprises the quantity of memory chips, which is necessary for occupying the bus width to the controller, which can be a processor, a chip set or also the signal driver/control chip on the semiconductor memory module. The bus width is normally 64 bits (72 bits incl. ECC). With this organization, 16 (or 18 with ECC) chips with 4 bits data width or 8 (or 9 with ECC) chips with 8 bits data width are needed for one rank.

A maximum of two ranks have been used on one DIMM. In the new “buffered DIMMs,” in which the data lines DQ from the controller are also buffered, it makes sense to implement, in deviation from the previous principle, a DIMM including 4 ranks with eight-bit-wide memory chips. Among other things, the required power of the DRAM memory chips plays an important role here. The problem with a DIMM with four ranks is that the load of four individual chips (two chips stacked above one another) occurs per DQ line. Due to this high loading, the planned high speeds, for example, 800 MBit/s, can only be achieved with difficulty.

A×4-based DIMM with two ranks has 18 stacked chips. In each “stacked device”, two 4-bit-wide chips are installed. The lower 18 chips closer to the wiring board form one rank and the outside (upper) 18 chips form a second rank. If this arrangement is expanded to a ×8-based DIMM with 4 ranks, a structure shown diagrammatically in theFIG. 11Ais obtained. The structure shown inFIG. 11Ais symmetric to a center plane of symmetry A which divides a wiring board1into a left- and right-hand half. At equally spaced-apart positions Pos1, Pos2, Pos3, Pos4to the left and to the right of the center plane of symmetry A, in each case two memory chips5are stacked above one another (stacked devices) on the top and bottom O, U of the DIMM module. In addition, there are ECC chips at position O (which are not designated in greater detail). The memory chips of the stacked devices are connected to a signal driver/control chip (hub)4via a number of wiring planes of the wiring board1. Of the lines connecting the memory chips to the hub chip, 8-bit-wide data line runs are shown here, which are connected to the stacked-up memory chips at junction points designated by 3 inside vias2which pass through the entire wiring board1. A first 8-bit-wide data line run leads to a first and second memory chip pair in the position Pos1next to the plane of symmetry A, in each case on the top O and bottom U of the wiring board1. In the same manner, a second to fourth 8-bit-wide data line run connects second, third and fourth memory chip pairs in each case on the top and bottom O, U of the wiring board1to the hub chip4. As mentioned, four ranks R1–R4are provided on this DIMM module. The chips of the first and second rank R1, R2are arranged on the top O of the wiring board1according toFIG. 11A. The chips of the third and fourth rank R3, R4being arranged on the bottom U of the wiring board1. Per rank, these are eight memory chips, apart from the two ECC chips and the hub chip4, which have an 8-bit data organization.

FIG. 11Bshows a diagrammatic side view of an extension of the concept shown inFIG. 11A, which provides eight ranks R1–R8and X8memory chips with four memory chips stacked in them (the side to the left of the center plane of symmetry A has been omitted for simplification since, of course, it is symmetric to the right-hand side).

In these embodiments according toFIGS. 11A and 11B, the total load is bunched at one point at the end of a DQ line. Due to the high capacitive load, a very poor edge steepness, and thus a small eye opening, is thus achieved. By reducing the impedance of the conductor track, for example by widening it, this effect could be reduced. However, the widening of the conductor tracks needed for this is very difficult or even impossible since they would have to be widened to such an extent that a layout can only be made with difficulty or at higher costs since, for example, additional wiring planes of the wiring board are needed.

A semiconductor memory module has the memory ranks distributed on the top and bottom of the wiring board for thermal reasons. Two memory chips on the front and back of a memory module are in each case connected by a data line run, called a channel. The memory module has four data line runs which in each case connect two memory chips on the front and two memory chips on the back of the memory module.

Also known is to arrange a semiconductor memory modules with approximately equal spacing along a databus.

A semiconductor memory module which, in comparison with conventional semiconductor memory modules, can allow a higher speed with a simple without additional added costs is desirable.

SUMMARY

By distributing the associated DRAMs, an improved signal quality and faster speed is possible. In the structure of the memory module proposed, it is no longer two or four ranks which are used for each side, as explained previously in relation toFIGS. 11A and 11B, all ranks are distributed.

A semiconductor memory module has memory ranks arranged distributed, i.e., distributed along the respective data line run such that, in operation, the load is distributed along the respective data line run.

The memory chips are, for example, DRAM chips and the semiconductor memory module is, for example, a DIMM module. In this exemplary semiconductor memory module, the respective bit width can be k=8. Eight memory chips are arranged per rank and the number of data line runs being 8, for example. Using this concept, for example, four or even eight ranks can be arranged distributed on the semiconductor memory module.

With this structure of the data memory module, a data line run (DQ) is conducted on one side of the semiconductor memory module. Moreover, no through-plated holes are needed for conducting the respective data line run.

The load, which has hitherto been bunched at the end of a DQ line and disturbs the signal integrity, can be distributed over the length of the data line run DQ and compensated for by a “loaded transmission line” concept. In this “loaded transmission line” concept, the input capacity of a memory chip is used such that the impedance is matched due to the additional capacitive load on the transmission line. In the state of the art, the normal conductor track impedance would usually be increased by reducing the conductor track width over a particular length by the DRAM ball of the “ball grid array”. Due to the capacitive load of the DRAM contact, a passing wave again sees the original lower impedance. The capacitive load of a DRAM can be embedded into the transmission line.

The structure of the semiconductor circuit module, the load at the end of the DQ line is relatively lower. In the area in which the DRAM contacts are located, routing is possible with a relatively lower conductor bandwidth and a relatively low impedance is still obtained.

DETAILED DESCRIPTION

In general, in a semiconductor memory module according to the invention, memory chips on the top and bottom O, U of the wiring board are arranged in positions which in each case have the same distance from one another, such that two or four memory chips with different ranks are stacked above one another on the top O and bottom U in each position. These stacked memory chips are in each case connected to the same data line run.

Due to the skilled arrangement of the memory chips on the top and bottom of the wiring board, a respective data line run is conducted (routed) on one side, i.e., the top or bottom of the wiring board, as a result of which a respective data line run does not need any vias to the other side of the wiring board. In contrast, blind holes with much lower parasitic capacitances are adequate.

In a first exemplary embodiment, shown diagrammatically inFIG. 1, of a semiconductor memory module according to the invention, the four ranks, R1, R2, R3, R4are distributed to positions1and3and2and4.

As in the case of the example explained initially in relation toFIG. 11Aof a conventional semiconductor memory module, the semiconductor memory module shown diagrammatically inFIG. 1is also symmetric to a center plane of symmetry A. On the left and right of this plane of symmetry A, eight memory chips12, which in each case have a stacked pair of memory chips, are arranged in four identically spaced-apart positions Pos1, Pos2, Pos3, Pos4on the wiring board10(DIMM wiring substrate). In each stacked memory chip12, the two memory chips are allocated to two different ranks R1and R2and R3and R4. In addition, there are two ECC chips and one signal driver/control chip or hub11on the wiring board10. The memory chip pairs or memory chips12are arranged on the top O and on the bottom U of the wiring board10, such that there is in each case one memory chip pair of in each case the first and second rank R1, R2in the first and second position Pos1, Pos2and in each case one memory chip pair of the third and fourth rank R3, R4in the third and fourth position Pos3and Pos4. As mentioned, the arrangement is symmetric to the center plane of symmetry A and as can be seen fromFIG. 1, it is also symmetric to a second plane of symmetry B intersecting the center of the semiconductor memory module in its longitudinal direction on the top O and bottom U. With this arrangement, the memory chip pairs in the second and fourth position Pos2, Pos4are in each case connected on the top and bottom O, U and in each case to the left and to the right of the plane of symmetry A in each case to a first, fourth, fifth and eighth data line run L1, L4, L5and L8. Furthermore, the memory chip pairs or chips in the first and third position Pos1, Pos3are in each case connected to a second, third, sixth and seventh data line run L2, L3, L6and L7in each case on the top and bottom O and U and to the left and to the right of the center plane of symmetry A with this arrangement. a1indicates a virtual length of the first, fourth, fifth and eighth data line run L1, L4, L5and L8and each indicates a virtual length of the second, third, sixth and seventh data line run L2, L3, L6and L7. It can be seen fromFIG. 1that the load is distributed approximately uniformly over the respective data line runs. As already mentioned, vias through the entire thickness of the wiring board10become unnecessary with this arrangement and blind hole connections designated by13are sufficient.

The Table 1 shown inFIG. 8specifies the arrangement shown inFIG. 1of the memory chips12in the positions Pos1–Pos4, the distribution of the ranks R1–R4, and the signal junction points of the respective memory chips to the eight-bit-wide DQ line runs L1–L4in each case on the top O and bottom U on the right-hand side, i.e., to the right of the center plane of symmetry A of the wiring board10in table form.

In another exemplary embodiment of a memory module according to the invention, shown inFIG. 2, the arrangement of the memory chip pairs or memory chips12on the wiring board10is, in principle, the same as in the first exemplary embodiment shown inFIG. 1and explained above. In distinction from the first exemplary embodiment, the memory chips12in the first and fourth position Pos1, Pos4are in each case connected on the top and bottom O, U and to the left and to the right of the plane of symmetry A to a first, fourth, fifth and eighth data line run (only the right-hand part of the semiconductor memory module is shown due to the symmetry with respect to the plane of symmetry A). In addition, the memory chip pairs or memory chips12in the second and third position Pos2, Pos3are in each case connected on the top and bottom O, U and to the left and to the right of the center axis of symmetry A in each case to a second, third, sixth and seventh data line run, the first and fourth data line run L1and L4and the fifth and eighth data line run (not shown) in each case having a virtual length a1and a second and third data line run L2, L3and the sixth and seventh data line run, not shown, in each case having a virtual length a2.

Table 2 inFIG. 9shows for the second exemplary embodiment described above, the arrangement of the memory chips12in positions Pos1–Pos4, the distribution of the ranks R1, R2, R3, R4, the connection of the memory chips in each case to the 8-bit-wide DQ line runs L1, L2, L3and L4on the top O and bottom U on the right-hand side, i.e., to the right of the center plane of symmetry A of the wiring board10in table form.

Table 2 shows in the second exemplary embodiment of the semiconductor module, that there is also a symmetry of the arrangement and of the connection to the data line runs with respect to the longitudinal plane of symmetry B. Furthermore, the semiconductor memory module illustrated inFIG. 2has the same advantages as the first exemplary embodiment illustrated byFIG. 1since a “loaded transmission line” concept is implemented and no vias passing through the entire wiring board10are needed.

In the third exemplary embodiment of a semiconductor memory module according to the invention, illustrated inFIG. 3, the arrangement of the memory chips12is changed compared with the first and second exemplary embodiments shown inFIGS. 1 and 2. According toFIG. 3namely, the memory chip pairs of the memory chips12are in each case arranged on the top O and bottom U of the wiring board10to the left and to the right of the center plane of symmetry A dividing the wiring board10into two identical halves, in such a manner that on the top and bottom O, U in the first and third position Pos1, Pos2, in each case one memory chip pair12of the first and second rank R1, R2is located and in the second and fourth position Pos2, Pos4in each case one memory chip pair12of in each case the third and fourth rank R3, R4is located, and the memory chips12in the third and fourth position Pos3, Pos4on the top and bottom O, U and above and below the center plane of symmetry B are in each case connected to a first and fourth data line run, and to a fifth and eighth data line run (not shown) to the left of the center plane of symmetry A. In addition, the memory chip pairs or memory chips12in the first and second position Pos1, Pos2on the top and bottom O, U and to the left and to the right of the center plane of symmetry A of the wiring board10are in each case connected to a second and third data line run L2, L3and to a sixth and seventh data line run (not shown) to the left of the center plane of symmetry A.

Table 3 inFIG. 10shows, for the third exemplary embodiment shown inFIG. 3, the arrangement of the memory chip pairs or memory chips12in each case in positions Pos1–Pos4, the distribution of the ranks R1–R4and the connection of the memory chip pairs to the individual 8-bit-wide DQ line runs L1–L4in each case on the top and bottom in table form. In this third exemplary embodiment too, the arrangement is symmetric with respect to the longitudinal plane of symmetry B. In the third exemplary embodiment, through-connections or vias are no longer needed according toFIG. 3, and, instead, it is possible to manage with blind-hole connections13since a respective DQ line run can be routed on one side, i.e., the top or bottom of the semiconductor memory module.

According toFIG. 4, which diagrammatically illustrates a fourth exemplary embodiment (only the part of the semiconductor memory module located to the right of the center plane of symmetry A has been shown for simplification), eight ranks R1–R8are distributed such that a data line run (8 bits wide) L1, L2and, respectively, L3, L4can be conducted on one side, i.e., the top O or the bottom U of the wiring board10. As a result, a through-via between the top O and the bottom U is no longer needed. If a data line run L1, L2and L3, L4can be run on the surface of the top or bottom, a blind-hole connection is no longer needed. If the data line run L1, L2and L3, L4is conducted on the inner signal layers, a blind-hole connection13with relatively lower parasitic capacitances is sufficient. In the exemplary embodiment shown inFIG. 4, the eight ranks are in each case divided over the second and fourth position Pos2, Pos4and the first and third position Pos1, Pos3. In this arrangement, the memory chips in the second and fourth position Pos2, Pos4are connected by a first data line run L1and the memory chips in the first and third position Pos1, Pos3are connected by a second data line run L2on the top O of the wiring board10, whereas the memory chips in the first and third position Pos1, Pos3are connected by a third data line run L3and the memory chips in the second and fourth position Pos2, Pos4are connected by a fourth data line run L4on the bottom U.

In the fifth exemplary embodiment shown inFIG. 5, which is a variant of the exemplary embodiment shown inFIG. 4, the eight ranks R1–R8are in each case divided over the first and fourth position Pos1, Pos4and the second and third position Pos2, Pos3, and on the top O of the wiring board10, the memory chips in the first and fourth position Pos1, Pos4are connected by a first data line run L1and the memory chips in the second and third position are connected by a second data line run L2, whereas the memory chips on the bottom U of the wiring board10in the second and third position Pos2, Pos3are connected by a third data line run L3and those in the first and fourth position are connected by a fourth data line run L4.

Since the side located to the left of the center plane of symmetry A is symmetric to the right-hand side, what has been described above correspondingly applies to the fifth to eighth data line run L5–L8(not shown) (compareFIG. 1). What has been described previously with regard to the through-vias between top and bottom and the possible omission of blind hole connections also applies to the left-hand side, not shown, of the fifth exemplary embodiment shown inFIG. 5.

In the sixth exemplary embodiment shown inFIG. 6, the eight ranks R1–R8are in each case divided over the first and second position Pos1, Pos2and the third and fourth position Pos3, Pos4. On the top O of the wiring board10, a first data line run L1connects the memory chips in the third and fourth position Pos3, Pos4and a second data line run L2connects the memory chips in the first and second position, whereas on the bottom U, a third data line run connects the memory chips in the first and second position and a fourth data line run L4connects the memory chips in the third and fourth position Pos3, Pos4. Since the sixth exemplary embodiment shown inFIG. 6also is a variant of the fourth and fifth exemplary embodiment shown inFIGS. 4 and 5, what has been described above correspondingly applies to the left-hand side (not shown) of the semiconductor memory module.

The seventh exemplary embodiment of a semiconductor memory module according to the invention, shown diagrammatically inFIGS. 7A(in a side view) and7B (in a top view) also distributes eight ranks R1–R8in each case on the top and bottom O and U of the wiring board10along the associated data line runs L1–L4(L5–L8, not shown, on the left-hand side of the plane of symmetry A), so that, in operation, the load is distributed along the respective data line run. In deviation from the fourth to sixth exemplary embodiments, shown inFIGS. 4 to 6, not four but only two semiconductor memory chips are stacked above one another in a memory chip in the concept shown inFIGS. 7A and 7B. Compared with four memory chips being stacked in one memory chip, this concept achieves better heat distribution. The seventh exemplary embodiment shown inFIGS. 7A and 7Bspecifies one of a number of variants of the distribution of memory chips having two stacked memory chips, and thus of the memory ranks, along the associated data line run because, similarly to the fourth to sixth exemplary embodiment (compareFIGS. 4–6), the arrangement of the memory chips in the four positions Pos1–Pos4can be varied whilst retaining the effect of load distribution in operation along the respective data line run.

Referring toFIGS. 7A and 7B, it is shown that on the top and bottom O, U of the wiring board10to the left and to the right of a center plane of symmetry A, dividing the former into two symmetric halves, in each case a first to fourth position Pos1, Pos2, Pos3, Pos4are provided for the memory chips12in this order, beginning from the center plane of symmetry A, and on the top and bottom O, U, in the first and second position Pos1, Pos2, in each case a first, second, third and fourth memory chip121,123,124with in each case two memory chips and, in the third and fourth position Pos3, Pos4, in each case a fifth, sixth, seventh and eighth memory chip125,126,127,128having in each case two memory chips are arranged.

As shown, the distribution of the eight ranks R1–R8in the seventh exemplary embodiment according toFIGS. 7A and 7Bis such that on the wiring board10, the first and third memory chip121,123in each case have two memory chips of first and second rank R1, R2and are arranged in each case to the side next to the second and fourth memory chip122,124in each case exhibiting two memory chips of third and fourth rank R3, R4, whereas the fifth and seventh memory chip125,127in each case exhibit two memory chips of fifth and sixth rank R5, R6and are in each case arranged to the side next to the sixth and eighth memory chip126,128exhibiting in each case two memory chips of the seventh and eighth rank R7, R8, the first, second, fifth and sixth memory chips121,122,125,126on the top and bottom O, U and to the left and to the right of the center plane of symmetry A being connected in each case by a first, fourth, fifth and eighth data line run L1, L4, L5, L8and the third, fourth, seventh and eighth memory chips123,124,127,128on the top and bottom O, U and to the left and to the right of the center plane of symmetry A in each case being connected by a second, third, sixth and seventh data line run L2, L3, L6, L7.

For the exemplary embodiments described above, it holds true that, if the data line runs can be routed on the outside of the wiring board (top or bottom), neither vias nor blind holes are needed.