APPARATUS WITH THINNING-BASED ALIGNMENT MARK AND METHODS OF MANUFACTURING THE SAME

Methods, apparatuses, and systems related to a semiconductor structure having a thinning-based alignment mark. The alignment mark may be formed by causing structural an alteration within a thickness of an initial semiconductor wafer and then thinning the initial semiconductor wafer. The thinning process may lead to a different removal rate of the altered portion and a corresponding mark at the end of the thinning process. The resulting mark may be used to identify a relative location of circuits on the thinned wafer for subsequent processing or bonding.

TECHNICAL FIELD

The disclosed embodiments relate to devices, and, in particular, to semiconductor devices with alignment marks for locating and aligning circuits and methods of manufacturing the same.

BACKGROUND

The current trend in semiconductor fabrication is to manufacture smaller and faster devices with a higher density of components for computes, cell phones, pagers, personal digital assistants, and many other products. However, decrease in circuit size can lead to certain challenges during manufacturing processes. For example, locating circuits, such as in aligning and attaching wafers or surface mounting devices, becomes increasingly difficult as the circuits decrease in size.

DETAILED DESCRIPTION

In the following description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with semiconductor devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology.

Several embodiments of semiconductor devices, packages, assemblies, or combinations thereof in accordance with the present technology can include initially forming one or more alignment marks within the silicon of the semiconductor wafer and then surfacing/exposing the buried alignment marks during a wafer thinning process. In some embodiments, the resulting alignment marks can be used for wafer-to-wafer bonding that joins at least two silicon wafers together to create a single, integrated device. The exposed alignment marks can be used to align the separate wafers, thereby accurately connecting the electrical circuits and connections between the bonded wafers.

In some embodiments, the wafer manufacturing process can include application of a stealth laser dicing to alter or intentionally damage a portion of the silicon buried under a top/front surface of the silicon wafer and under the pattern circuitry. The damaged portion of silicon would have a different refractive index compared to other portions of silicon. The stealth laser dicing technique is a highly efficient and precise process that allows the laser to focus at a targeted depth to create an imperfection or a structural alteration in the subsurface silicon. In one or more embodiments, the depth of the imperfection/alteration can correspond to a targeted thickness of the silicon wafer (e.g., ranging between 1 μm to 2 μm, with a tolerance between 0.25 μm and 0.5 μm). Additionally, stealth laser dicing can alter the silicon without producing any significant damage to the wafer overall (e.g., localized alteration/damage) since it is a low-stress process.

The laser can be applied during a front-side manufacturing process. For example, the stealth laser can be applied using one or more openings in masks used to form active circuitry components on the front side of the wafer. By performing the laser-based marking during the front-side processing (via, e.g., a shared mask/pattern), the manufacturing process can increase the accuracy in placing the marks relative to the active circuitry. In other words, the markings can consistently and accurately identify the relative locations of the active circuits.

The wafer manufacturing process can include subsequently exposing the altered/damaged portion of the silicon during a wafer thinning process. Backside portions of the wafer can be removed, such as using a dry etch process, until the remaining wafer is reduced to have the targeted thickness. During the thinning process, the altered portions of the silicon can react faster than the non-altered portions of the silicon. As a result, the wafer thinning process can remove the laser-altered portions faster than the remaining portions, thereby creating depressions in the backside surface at the laser-marked locations. For example, thinning by dry etching can be by sulfur hexafluoride (SF6) or another similar inorganic compound. The SF6will weaken the bonds of the silicon oxide, reducing the thickness of the wafer. Use of the thinning process to expose the alignment marks is beneficial. For example, thinning can improve yield by reducing the amount of stress applied on the wafer during the alignment process. Reducing stress on the wafer will reduce the risk of breaking or damaging the wafer. Additionally, thinning can also improve accuracy during the alignment process. Because thinning reduces the distance between the alignment marks and the device layer, the accuracy of the alignment will improve. Moreover, thinning will also reduce the amount of reflection that occurs during the alignment process. Reflection can interfere with the alignment marks of the wafers, making it difficult to accurately align the wafers, thus thinning can alleviate this problem.

FIG.1AandFIG.1Billustrate a semiconductor wafer100having alignment marks102thereon in accordance with embodiments of the technology.FIG.1Aillustrates a perspective view of the wafer100.FIG.1Billustrates a partial cross sectional view taken along a dashed line1A-1A ofFIG.1A. Referring toFIG.1AandFIG.1Btogether, the wafer100can have the alignment marks102formed using a marking device104(e.g., a laser device, such as a stealth laser).

The wafer100can have circuits106(e.g., integrated circuits) formed on an active side112. The alignment marks102can be on or detectable through a passive side (e.g., a backside) opposite the active side112. The wafer100can have a target thickness116measured between the active side112and the passive side114. In some embodiments, the target thickness116can be 5 μm or less (e.g., 2 μm, 1 μm, or less). In other embodiments, the target thickness can be 100 nm or less (e.g., 20 nm or less).

As described in detail below, the wafer100can be manufactured based on forming the alignment marks102or corresponding structural alterations buried within an initial wafer120(e.g., between the active side112and an initial backside of the initial wafer120). The initial wafer120can have an initial thickness126(e.g., as measured between the active side112and the initial backside) greater than the target thickness116. As an illustrative example, the marking device104can cause the structural alterations (e.g., structural weaknesses) at a targeted depth (e.g., a depth equivalent to the target thickness116) within the initial thickness126. The marking device104can include a stealth laser configured to focus at the targeted depth below the active surface. The structural alterations can further have a predetermined shape and/or lateral dimensions.

Subsequently, the initial wafer120can be thinned, such as by removing a backside portion thereof using an etching process, to form the wafer100. The etching process can cause the structural alterations to etch at a different/faster rate than other non-altered portions. Accordingly, the previously buried alignment marks102can surface or form as indentations in the backside/passive side114of the wafer100. In some embodiments, the resulting indentations can correspond to the alignment marks102. In other embodiments, the indentations can be filled with a contrast material (e.g. dielectric material having a unique color) to provide increased visibility/detectability. Once exposed, the alignment marks102can be used to accurately align the circuits106to circuits on another structure, such as another wafer targeted to be bonded to the wafer100.

In some embodiments, the alignment marks102(e.g., results generated from the process of stealth dicing and dry etching) can be used to align at least two homogenous wafers (e.g., DRAM wafers) or heterogenous wafers (e.g., DRAM wafer and logic wafer). Further, the alignment marks102may be formed on the periphery of the chip, and therefore, can also be used when placing the chip onto a waver (C2W).

In some embodiments, the formation of the alignment marks102can occur during frontside processing of the wafer100. In other words, the buried alignment marks102can be formed during, as a part of, or after forming the circuits106. For example, the buried alignment marks102can be formed using a marking mask aligned with a circuit forming mask or using a designated opening on the circuit forming mask.

The buried alignment marks102can be formed using energy from one or more marking devices104. In such embodiments, the marking devices104can be positioned above the wafer100. A mask previously used to form the circuits106on the surface of the wafer100can further include openings for delivering the energy produced by the marking devices104. The marking devices104can be configured or tuned to focus at a predetermined depth below the active side112of the wafer100. Once the marking devices104activate, the energy can pass through the top/front surface of the wafer100and focus at the predetermined depth and location. The focused energy can create an imperfection/alteration at the targeted location. The resulting imperfection or altered/weakened portion is the alignment mark102, and it can be created at or a threshold location from a target depth under the mask opening. In certain embodiments, the targeted depth of the alignment mark102is between 1 μm and 2 μm.

FIG.2-FIG.7illustrate example phases for a manufacturing process in accordance with embodiments of the technology.FIG.2illustrates a cross sectional view of a semiconductor structure200(e.g., a wafer) in accordance with embodiments of the technology. The semiconductor structure200can correspond to the initial wafer120ofFIG.1Bhaving the initial thickness126greater than the target thickness116ofFIG.1B.

The structure200can have a mask202over the active side112thereof. In some embodiments, the mask202can be used to form the circuits106ofFIG.1Bor a portion thereof. In other embodiments, the mask202can be aligned with another mask used to form the circuits106. Accordingly, the mask202can have marking openings204at designated/fixed locations relative to the circuits106.

The marking devices104can apply stimulus or energy (e.g., focusable laser) through the marking openings204of the mask202to form buried marks212. The marking devices104can form the buried marks212by altering the structural and/or the compositional material of the structure200. The marking devices104can form the buried marks212below the active side112(e.g., top surface), such as at a marking depth214. The marking depth214can correspond to the target thickness116(e.g., at the same depth/location as or within a threshold distance of the planned backside of the passive side114ofFIG.1B). In some embodiments, the marking devices104can be configured or tuned to focus at the marking depth214below the top surface. Also, the buried marks212can have a targeted vertical dimension that corresponds to (1) a depth for the resulting mark and/or (2) a variability or a tolerance level associated with the target thickness116.

In addition to the targeted depth, the marking openings204and the corresponding buried marks212can be located at targeted lateral locations on the semiconductor wafer. For example, the buried marks212can be formed in or relative to scribe regions, active die regions, or the like for post-singulation detection.

FIG.3illustrates a cross sectional view of an intermediate structure300(e.g., a bonded structure) in accordance with embodiments of the technology. The structure300can have the structure200(e.g., the initial wafer120ofFIG.1B) attached or bonded to a carrier wafer302. In some embodiments, the structure300can be wafer bonded to the carrier wafer302to enhance structural support for the initial wafer120. In other words, the carrier wafer302can be electrically isolated from the circuits106ofFIG.1Bon the initial wafer120. Instead, the carrier wafer302can be bonded to the initial wafer120to provide additional rigidity and structural integrity for the initial wafer120during subsequent manufacturing processes. For example, by bonding the carrier wafer302to the initial wafer120, the carrier wafer302can prevent structural damages to the initial wafer120during and after thinning.

In some embodiments, the initial wafer120can have a cover over the active side112ofFIG.1Band the circuits106. The initial wafer120can be bonded to the carrier wafer302after forming the alignment marks102under the active side112and/or the circuits106. In some embodiments, once the wafer100with the buried alignment marks102is bonded to the carrier wafer202, the carrier wafer202can act as a support to the wafer100during the wafer thinning process to surface or expose the buried alignment marks.

FIG.4illustrates a cross sectional view of an intermediate structure400in accordance with embodiments of the technology. The intermediate structure400can represent a result of thinning the initial wafer120ofFIG.3from the structure300ofFIG.3. The thinning process can remove a back portion of the initial wafer120using a dry etching process, a mechanical etching or polishing process, a chemical or wet etching process, and/or the like. The thinning process can proceed until the initial thickness126ofFIG.1Bof the initial wafer120is reduced to target thickness116. As a result, the wafer100can be formed or remain bonded to the carrier wafer302, and the thinning process can establish the backside/passive side114of the wafer100.

The thinning process can further form exposed marks404, such as depressions, on the passive side114of the wafer302. The exposed marks404can correspond to the buried marks212ofFIG.2. In other words, the exposed marks404can result from exposing and/or otherwise physically manipulating the buried marks212. For example, the etching process can cause additional or increased removal of structurally altered portions in comparison to other portions of the initial wafer120. The additional/increased removal can remove the buried marks212and form the depressions that correspond to the exposed marks404.

The resulting depressions or the exposed marks404can have one or more physical traits indicative of the initial structural alteration and the subsequent accelerated removal. For example, the exposed marks404can have side walls that are more linear or gradual as a result of the laser-based alteration in comparison to other marks formed directly on the passive side after the thinning process, such as by etching through a mask applied to the thinned passive side. Also, the exposed marks404can have relatively smoother side walls or bottom walls in comparison to other marks having cracks or uneven edges indicative of being formed by applying pressure or force on the thinned passive side. Moreover, the exposed marks404may have side walls that have a different slope or shape compared to other marks formed by directly applying laser to the thinned passive side.

In addition to the different physical traits, the exposed marks404can provide greater accuracy and consistency in its relative location to the active circuit in comparison to other marks formed on the thinned backside. Conventional alignment marks are formed by a step or a process separate from the formation of the circuits, thereby introducing an additional source for error, inaccuracy, and inconsistency. In contrast, the exposed marks404can be formed by applying the external stimuli (e.g., the laser) during or as a part of the frontside processing to form the circuits, such as using one or more masks used for the circuit formation as a common reference. Accordingly, the exposed marks404can have increased accuracy and consistency in their locations relative to the integrated circuit on the wafer.

FIG.5illustrates a cross sectional view of an intermediate structure500in accordance with embodiments of the technology. The structure500can correspond to a result of filling the exposed marks404ofFIG.4with contrast material (e.g., colored or otherwise detectable filler material) to form filled marks504. The contrast material can be applied and then shaped (e.g., buffed via a chemical mechanical polishing (CMP) process) to form the filled marks504. The filled marks504can represent the alignment marks102ofFIG.1B. In other embodiments, the exposed marks404without the filler can represent the alignment marks102.

FIG.6illustrates a cross sectional view of an intermediate structure600in accordance with embodiments of the technology. The structure600can have a first semiconductor wafer602bonded to a second semiconductor wafer604. The first wafer602, the second wafer604, or both can have alignment marks102ofFIG.1B. In other words, the first wafer602, the second wafer604, or both can result from the process described above usingFIG.2throughFIG.5. The wafers602and604can be bonded using one or more wafer bonding techniques, such as direct bonding, hybrid bonding, oxide bonding, and the like.

In bonding the wafers, the manufacturer or a corresponding system can use the alignment marks102on one or both of the wafers to control a relative positioning of the wafers. In other words, the method for bonding the wafers can include aligning the wafers using the alignment marks102on one or both of the wafers. Accordingly, the alignment marks102can increase the accuracy in the relative positions of the circuits on the bonded wafers and increase the likelihood that the electrical connections are formed as intended, thereby reducing bonding failures and any associated reworks and losses. In some embodiments, the alignment marks102(e.g., results generated from the process of stealth dicing and dry etching) can be used to align at least two homogenous wafers (e.g., DRAM wafers) or heterogenous wafers (e.g., DRAM wafer and logic wafer). Additionally or alternatively, the alignment marks102may be formed on the periphery of the chip or singulation locations (e.g., at or relative to the scribe regions), and therefore, can also be used when placing the chip onto a waver (C2W).

For illustrative purposes,FIG.6shows the wafers bonded at the front sides. However, it is understood that the wafers can be bonded differently, such as front-to-back or back-to-back. For other relative arrangements, one or more of the circuits can have vias or other vertical connections that extend across the thickness of the wafer to connection pads/locations. The alignment marks102can be used to relatively locate such connection pads/locations and ensure that they contact and are connected to targeted locations on the other wafer.

In some embodiments, the bonded wafers can be configured to form memory devices. For example, one of the wafers can be an array wafer that includes data storage cells in its circuits, and another of the wafers can be a control (CMOS) wafer with circuits configured to operate or control the wafer circuits.

The dashed lines inFIG.6can represent a singulation or dicing process for the bonded wafers or the structure600.FIG.7illustrates a cross sectional view of a semiconductor device700in accordance with embodiments of the technology. The device700can represent one of the singulated devices resulting from cutting, sawing, or otherwise dicing the structure600ofFIG.6. Accordingly, the device700can include a first die702bonded to a second die704. The dies702and704can have circuits on active sides thereof.

In some embodiments, the first die702, the second die704, or both can have the alignment marks102on backsides thereof. Both the bonding and the alignment marks102can be remnants or byproducts of the wafer-level processing described above. Additionally or alternatively, the alignment marks102can be placed at designated locations about the device700, such as to provide identifiable locations relative to one or more circuits on the device700. The alignment marks102can be further utilize to position the device700and/or one or more portions thereof relative to other circuits, such as during a mounting process. Also, the alignment marks102can provide reference locations for the circuits, such as for identifying and processing manufacturing defects within the device700.

The device700can include a memory device, such as a Dynamic Random-Access Memory (DRAM), a NAND Flash memory, other volatile or non-volatile memory, a combination memory, or the like. For example, one of the first dies702or the second die704can include memory array(s) configured to store and provide access to data. The other of the first dies702or the second die704can include the control circuitry (e.g., CMOS) configured to control storage of and manage the data at the memory array and/or control access to the stored data. The control circuitry can include input/output circuitry, command and/or address processing circuitry, power management circuitry, clock or coordination circuitry, and/or the like.

FIG.8is a flow diagram illustrating an example method800of manufacturing an apparatus in accordance with an embodiment of the present technology. The example method800can be for manufacturing the wafer100ofFIG.1B, the bonded structure600ofFIG.6, the device700ofFIG.7, or a combination thereof. For example, the method800can include forming and utilizing the alignment marks102ofFIG.1B.

The method800can include providing an initial semiconductor wafer (e.g., the initial wafer120ofFIG.1BandFIG.2) as illustrated at block802. The initial wafer can have the initial thickness126ofFIG.2.

The method800can include, at block804, forming circuits (e.g., the circuits106ofFIG.1B) on the initial wafer. The circuits can be formed by doping, shaping, and electrically connecting various portions. Circuits, such as transistors, capacitors, diodes, and the like, can be formed using one or more masks to deposit dopants to, deposit, and/or remove various materials and portions on the active side112ofFIG.1Bof the initial wafer.

The method800can include forming buried alterations (e.g., the buried marks212ofFIG.2) under the active/top side of the initial wafer as illustrated at block806. For example, the method800can include using the marking devices104ofFIG.1AandFIG.2(e.g., stealth laser) to form the buried marks212at the marking depth214ofFIG.2. The marking devices104can use the mask202and provide the energy into the initial wafer through the marking opening204. The marking devices104can be configured or tuned to focus the energy at the marking depth214. The marking devices104can cause or form structural or compositional alterations at the marking depth214and according to the location of the marking opening204. Accordingly, the marking devices104can cause or form structural or compositional alterations that correspond to the buried mark212.

At block808, the initial wafer can be bonded to a carrier wafer. For example, the initial wafer120ofFIG.3can be bonded to the carrier wafer302ofFIG.3to provide structural support for the initial wafer120during subsequent manufacturing processes.

At block810, the initial wafer can be thinned. The back portions of the initial wafer can be removed or etched away as illustrated at block812. The etching process can thin the wafer to the target thickness116ofFIG.1Busing one or more etching processes as described above.

At block814, the method800can include exposing or forming marking indentations, such as the exposed marks404ofFIG.4. The exposed marks404can result from the increased etch rate or additional removal at the buried marks212ofFIG.2. As described above, the structural alterations can lead to an increased etch rate/removal at the buried marks212, thereby forming the indentations or the exposed marks404on the passive side114of the resulting wafer100ofFIG.4.

In some embodiments, the indentations (e.g., the exposed marks404) can be filled as illustrated at block816. For example, contrasting material may be used to fill the exposed marks404, thereby forming the filled marks504ofFIG.5as described above.

The thinned and marked wafer can be bonded to another functional wafer as illustrated at block820. For example, the first wafer602ofFIG.6can be bonded to the second wafer604ofFIG.6as described above. Also, one or more of the wafers can be detached from corresponding carrier wafers. In bonding the wafers, the method800can include aligning the wafers using the alignment marks102(e.g., the exposed marks404and/or the filled marks504) on one or more of the wafers. The alignment marks102can be positioned relative to other marks on another wafer and/or one or more reference locations apart from the wafers.

The method800can further include forming bonded dies as illustrated at block824, such as by dicing or cutting the bonded wafers as described above. The resulting device700ofFIG.7can have semiconductor devices/dies that are bonded to each other via wafer-level processing.

FIG.9is a schematic view of a system that includes an apparatus in accordance with embodiments of the present technology. Any one of the semiconductor devices described above with reference toFIGS.1-8can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system990shown schematically inFIG.9. The system990can include a semiconductor device900(“device900”) (e.g., a semiconductor device, package, and/or assembly), a power source992, a driver994, a processor996, and/or other subsystems or components998. The device900can include features generally similar to those devices described above. The resulting system990can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions. Accordingly, representative systems990can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and appliances. Components of the system990may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system990can also include remote devices and any of a wide variety of computer-readable media.

This disclosure is not intended to be exhaustive or to limit the present technology to the precise forms disclosed herein. Although specific embodiments are disclosed herein for illustrative purposes, various equivalent modifications are possible without deviating from the present technology, as those of ordinary skill in the relevant art will recognize. In some cases, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. Although steps of methods may be presented herein in a particular order, alternative embodiments may perform the steps in a different order. Similarly, certain aspects of the present technology disclosed in the context of particular embodiments can be combined or eliminated in other embodiments. Furthermore, while advantages associated with certain embodiments of the present technology may have been disclosed in the context of those embodiments, other embodiments can also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages or other advantages disclosed herein to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein, and the invention is not limited except as by the appended claims.

Throughout this disclosure, the singular terms “a,” “an,” and “the” include plural referents unless the context clearly indicates otherwise. Similarly, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the terms “comprising,” “including,” and “having” are used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of other features are not precluded. Reference herein to “one embodiment,” “an embodiment,” “some embodiments” or similar formulations means that a particular feature, structure, operation, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present technology. Thus, the appearances of such phrases or formulations herein are not necessarily all referring to the same embodiment. Furthermore, various particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.