Package on package (PoP) integrated device comprising a capacitor in a substrate

Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

BACKGROUND

Various features relate to a package on package (PoP) integrated device comprising a capacitor in a substrate.

FIG. 1illustrates a conventional package on package (PoP) integrated device. As shown inFIG. 1, the integrated device100includes a first package102and a second package104. The first package102includes a first substrate106, a first die (e.g., chip)108, a first set of solder balls116, a first set of interconnects118, and a capacitor120. The first substrate106may include traces and/or vias (both of which are not shown). The second package104includes a second substrate105, a second die107, a third die109, a second set of solder balls115, a first set of wire bonding117, and a second set of wire bonding119. The second substrate105may include traces and/or vias (both of which are not shown). The second package104is positioned above the first package102.

The first die108is coupled to a first surface (e.g., top surface) of the first substrate106through the first set of interconnects118. The first set of solder balls116is coupled to a second surface (e.g., bottom surface) of the first substrate106. The first substrate106includes a set of traces and/or vias that may electrically connect to the first die108and/or the first set of solder balls116. The capacitor120is a surface mounted passive device on a surface of the substrate106.

The second die107and the third die109are coupled to a first surface (e.g., top surface) of the second substrate105. The second die107is electrically coupled to the traces and/or vias of the second substrate105through the first set of wire bonding117. The third die109is electrically coupled to the traces and/or vias of the second substrate105through the second set of wire bonding119. The second set of solder balls115is coupled to a second surface (e.g., bottom surface) of the second substrate105.

One major drawback of the package on package (PoP) configuration shown inFIG. 1is that it creates an integrated device with a form factor that may be too large for the needs of mobile computing devices. For example, the location of the capacitor120may limit how small the integrated device can be. This may result in a package that is either too large and/or too thick. That is, the PoP configuration shown inFIG. 1may be too thick and/or have a surface area that is too large to meet the needs and/or requirements of mobile computing devices.

Therefore, there is a need for an integrated device that includes an improved PoP configuration. Ideally, such an integrated device will have a better form factor, while at the same time meeting the needs and/or requirements of mobile computing devices. Moreover, such an improved PoP configuration would provide better integrated device performance (e.g., better signal, better channel, better electrical speed performance).

SUMMARY

Various features, apparatus and methods described herein provide a package on package (PoP) integrated device comprising several solder resist layers.

A first example provides an integrated device that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation layer. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

According to an aspect, the capacitor includes one of at least a plate capacitor and/or an embedded package substrate (EPS) capacitor.

According to one aspect, the first redistribution portion includes a redistribution interconnect.

According to an aspect, the first encapsulation layer includes a through encapsulation via.

According to one aspect, the first encapsulation layer includes a photo-etchable material.

According to an aspect, the substrate is a hybrid substrate that includes a first dielectric layer and a second dielectric layer. In some implementations, the second dielectric layer has a second k value that is substantially greater than the first k value of the first dielectric layer.

According to one aspect, the integrated device includes a first redistribution interconnect, a first through encapsulation via (TEV), a first via, a first pad, a second TEV, and a second redistribution interconnect. The first redistribution interconnect is in the first redistribution portion. The first redistribution portion is coupled to the first die through a first die interconnect. The first through encapsulation via (TEV) is in the first encapsulation layer. The first TEV is coupled to the first redistribution interconnect. The first via is in the substrate. The first via is coupled to the first TEV. The first pad is in the substrate. The first pad is coupled to the first via. The second TEV is in the second encapsulation layer. The second TEV is coupled to the first pad. The second redistribution interconnect is in the second redistribution portion. The second redistribution interconnect is coupled to the second TEV.

According to an aspect, the integrated device is one of at least a package and/or package on package (POP) device.

According to one aspect, the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

A second example provides a method for fabricating an integrated device. The method provides a substrate that includes a first surface, a second surface, and a capacitor. The method couples a first die to the first surface of the substrate. The method forms a first encapsulation layer that encapsulates the first die. The method forms a first redistribution portion on the first encapsulation layer. The method couples a second die to the second surface of the substrate. The method forms a second encapsulation layer that encapsulates the second die. The method forms a second redistribution portion on the second encapsulation layer.

According to an aspect, the capacitor includes one of at least a plate capacitor and/or an embedded package substrate (EPS) capacitor.

According to one aspect, forming the first redistribution portion includes forming a redistribution interconnect.

According to an aspect, forming the first encapsulation layer includes forming a through encapsulation via.

According to one aspect, the first encapsulation layer includes a photo-etchable material.

According to an aspect, providing the substrate includes providing a hybrid substrate that includes a first dielectric layer and a second dielectric layer. In some implementations, the second dielectric layer has a second k value that is substantially greater than the first k value of the first dielectric layer.

According to one aspect, the method forms a first redistribution interconnect in the first redistribution portion such that the first redistribution portion is coupled to the first die through a first die interconnect. The method forms a first through encapsulation via (TEV) in the first encapsulation layer such that the first TEV is coupled to the first redistribution interconnect. The method forms a first via in the substrate such that the first via is coupled to the first TEV. The method forms a first pad in the substrate such that the first pad is coupled to the first via. The method forms a second TEV in the second encapsulation layer such that the second TEV is coupled to the first pad. The method forms a second redistribution interconnect in the second redistribution portion such that the second redistribution interconnect is coupled to the second TEV.

According to an aspect, the integrated device is one of at least a package and/or package on package (POP) device.

According to one aspect, the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

DETAILED DESCRIPTION

Overview

Some features pertain to an integrated device (e.g., integrated package device, package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer. In some implementations, the capacitor includes one of at least a plate capacitor and/or an embedded package substrate (EPS) capacitor. In some implementations, the substrate is a hybrid substrate that includes a first dielectric layer and a second dielectric layer. In some implementations, the second dielectric layer has a second k value that is substantially greater than the first k value of the first dielectric layer. In some implementations, the first redistribution portion includes a redistribution interconnect. In some implementations, the first encapsulation layer includes a through encapsulation via (TEV). In some implementations, the first encapsulation layer includes a photo-etchable material.

Terms and Definitions

An interconnect is an element or component that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a redistribution metal layer, and/or an under bump metallization (UBM) layer. In some implementations, an interconnect is an electrically conductive material that provides an electrical path for a signal (e.g., data signal, ground signal, power signal). An interconnect may include more than one element/component.

Exemplary Package on Package (PoP) Integrated Device that Includes a Capacitor in a Substrate

FIG. 2illustrates an exemplary package on package (PoP) integrated device200that includes a capacitor in a substrate. As shown inFIG. 2, the integrated device200(e.g., integrated package device) includes a first die202, a second die206, a substrate210, a first encapsulation layer220, a second encapsulation layer230, a first redistribution portion240, and a second redistribution portion250.

The substrate210includes a dielectric layer212, a via214, a pad216, a first capacitor217and a second capacitor219. In some implementations, the substrate210is a laminate substrate. The substrate210includes a first surface (e.g., top surface) and a second surface (e.g., bottom surface). In some implementations, the dielectric layer212may include several dielectric layers. In some implementations, the dielectric layers may be the same material. The via214is coupled to the pad216. In some implementations, the combination of the via214and the pad216traverses from the first surface of the substrate210to the second surface of the substrate210. In some implementations, the via214and/or the pad216is a form of an interconnect that traverses the substrate210.

In some implementations, the first capacitor217is a first plate capacitor. In some implementations, the second capacitor219is a second plate capacitor219. In some implementations, a plate capacitor is defined by two interconnects separated by a gap. In some implementations, the gap is defined by one or more dielectric layers. The first and second capacitors217and219are further described in detail below inFIG. 3.

The first die202includes a back side and a front side (e.g., active side). The front side is coupled to a set of die interconnects204. The set of die interconnects204may be one of at least pads and/or pillars in some implementations. The back side of the first die202is coupled to the first surface of the substrate210. In some implementations, a bonding agent (e.g., glue) is used to couple the back side of the first die202to the first surface of the substrate210. As shown inFIG. 2, the back side of the first die202is facing the substrate210while the front side (e.g., active side) of the first die202is facing away from the substrate210.

The first encapsulation layer220encapsulates the first die202and the set of die interconnects204. In some implementations, the first encapsulation layer220is one of at least a mold, a polymer, and/or a photo-etchable material. In some implementations, a photo-etchable material is a material that may be etched through a photo etching process. The first encapsulation layer220includes a set of interconnects222. In some implementations, the set of interconnects222is one of at least a through encapsulation via (TEV) and/or a through mold via (TMV). In some implementations, the set of interconnects222traverses from a first surface (e.g., top surface) of the first encapsulation layer220to a second surface (e.g., bottom surface) of the first encapsulation layer220.FIG. 2illustrates that a portion of the set of interconnects222in the first encapsulation layer220is coupled to the via214in the substrate210.

The first redistribution portion240is coupled to the first surface of the first encapsulation layer220. The first redistribution portion240includes a second dielectric layer242and a first set of redistribution interconnects244. In some implementations, the first redistribution portion240may include more than one set of redistribution interconnects. The first set of redistribution interconnects244is coupled to the set of die interconnects204and the set of interconnects222. In some implementations, the second dielectric layer242includes one or more dielectric layers.

The second die206includes a back side and a front side (e.g., active side). The front side is coupled to a set of interconnects208. The set of interconnects208may be one of at least pads and/or pillars in some implementations. The back side of the second die206is coupled to the second surface of the substrate210. In some implementations, a bonding agent (e.g., glue) is used to couple the back side of the second die206to the second surface of the substrate210. As shown inFIG. 2, the back side of the second die206is facing the substrate210while the front side (e.g., active side) of the second die206is facing away from the substrate210.

The second encapsulation layer230encapsulates the second die206and the set of interconnects208. In some implementations, the second encapsulation layer230is one of at least a mold, a polymer, and/or a photo-etchable material. In some implementations, a photo-etchable material is a material that may be etched through a photo etching process. The second encapsulation layer230includes a set of interconnects232and a set of interconnects209. In some implementations, the set of interconnects232is one of at least a through encapsulation via (TEV) and/or a through mold via (TMV). In some implementations, the set of interconnects232traverses from a first surface (e.g., top surface) of the second encapsulation layer230to a second surface (e.g., bottom surface) of the second encapsulation layer230.FIG. 2illustrates that a portion of the set of interconnects232in the second encapsulation layer230is coupled to the pad216in the substrate210. In some implementations, the set of interconnects209is one of at least a through encapsulation via (TEV) and/or a through mold via (TMV). The set of interconnects209is coupled to the set of interconnects208.

The second redistribution portion250is coupled to the first surface of the second encapsulation layer230. The second redistribution portion250includes a third dielectric layer252, a second set of redistribution interconnects254, a third set of redistribution interconnects256, and a set of under bump metallization (UBM) layers258. In some implementations, the second redistribution portion250may include one, two, or more than two sets of redistribution interconnects. The first set of redistribution interconnects254is coupled to the set of interconnects209and the set of interconnects232. In some implementations, the third dielectric layer252includes one or more dielectric layers.

A set of solder balls260is coupled to the set of UBM layers258. In some implementations, the UBM layers258are optional. In such instances, the set of solder balls260may be directly coupled to one of the redistribution interconnects.

FIG. 3illustrates a close-up view of a portion of the substrate210ofFIG. 2. As shown inFIG. 3, the substrate210includes the dielectric layer212, the via214, the pad216, the first capacitor217and the second capacitor219. In some implementations, the substrate210is a laminate substrate. The substrate210includes a first surface (e.g., top surface) and a second surface (e.g., bottom surface). In some implementations, the dielectric layer212may include several dielectric layers. The via214is coupled to the pad216. In some implementations, the combination of the via214and the pad216traverses from the first surface of the substrate210to the second surface of the substrate210. In some implementations, the via214and/or the pad216is a form of an interconnect that traverses the substrate210.

It should be noted that the substrate210may include additional interconnects (e.g., traces, vias), which are not shown for the purpose of clarity. These un-shown (or not visible) interconnects may couple the capacitors217and/or219to the via214and/or pad216in some implementations. In some implementations, at least one of the capacitors217and/or219may be electrically coupled to at least the first die202and/or the second die206. For example, the capacitor217may be electrically coupled to the first die202through the via214, the interconnect222, the interconnect244, and/or the interconnect204. Similarly, the capacitor217may be electrically coupled to the second die206through the via214, the pad216, the interconnect232, the interconnect254, the interconnect208, and/or the interconnect209.

In some implementations, the first capacitor217is a first plate capacitor. As shown inFIG. 3, the first capacitor217includes a first via302, a first interconnect304, a second interconnect306, and a second via308. In some implementations, the first via302is a first terminal of the first capacitor217. In some implementations, the first interconnect304is a first plate of the first capacitor217. In some implementations, the second interconnect306is a second plate of the first capacitor217. In some implementations, the second via308is a second terminal of the first capacitor217. In some implementations, the first interconnect304and the second interconnect306are at least substantially parallel to each other. As shown inFIG. 3, the first interconnect304and the second interconnect306are separated by a gap and/or spacing. The gap and/or spacing is filled with a layer of the dielectric layer212. In some implementations, each of the first and second vias302and308may include one or more vias, or a combination of interconnects, vias, and/or pads.

In some implementations, the second capacitor219is a second plate capacitor. As shown inFIG. 3, the second capacitor219includes a third via312, a third interconnect314, a fourth interconnect316, and a fourth via318. In some implementations, the third via312is a first terminal of the second capacitor219. In some implementations, the third interconnect314is a first plate of the second capacitor219. In some implementations, the fourth interconnect316is a second plate of the second capacitor219. In some implementations, the fourth via318is a second terminal of the second capacitor219. In some implementations, the third interconnect314and the fourth interconnect316are at least substantially parallel to each other. As shown inFIG. 3, the third interconnect314and the fourth interconnect316are separated by a gap and/or spacing. The gap and/or spacing is filled with a layer of the dielectric layer212. In some implementations, each of the third and fourth vias312and318may include one or more vias, or a combination of interconnects, vias, and/or pads.

In some implementations, the second capacitor219is a second plate capacitor219. In some implementations, a plate capacitor is defined by two interconnects separated by a gap. In some implementations, the gap is defined by one or more dielectric layers.

It should be noted that the substrate210may include additional interconnects (e.g., traces, vias), which are not shown for the purpose of clarity. These un-shown (or not visible) interconnects may couple the capacitors217and/or219to the via214and/or pad216in some implementations. For example, the interconnect306and/or the via308may be coupled to the via214through one or more interconnects (e.g., trace and/or via) in the substrate210. Similarly, in some implementations, the via302and/or the interconnect304may be coupled to the via214and/or the pad216through one or more interconnects (e.g., trace and/or via) in the substrate210.

Exemplary Package on Package (PoP) Integrated Device that Includes a Capacitor in a Hybrid Substrate

FIG. 4illustrates an exemplary package on package (PoP) integrated device400that includes a capacitor in a hybrid substrate. As shown inFIG. 4, the integrated device400(e.g., integrated package device) includes a first die402, a second die406, a substrate410, a first encapsulation layer420, a second encapsulation layer430, a first redistribution portion440, and a second redistribution portion450.

The substrate410includes a first dielectric layer412, a second dielectric layer413, a third dielectric layer415, a via414, a pad416, a first capacitor417and a second capacitor419. In some implementations, the substrate410is a hybrid laminate substrate. In some implementations, the third dielectric layer415has a high k value, relative to the k value of the first dielectric layer412and/or the second dielectric layer413. For example, the third dielectric layer415may have a k value that is about at least 2 times greater than the k value of the first dielectric layer412and/or the second dielectric layer413. In some implementations, the substrate410may include more than three dielectric layers.

The substrate410includes a first surface (e.g., top surface) and a second surface (e.g., bottom surface). The via414is coupled to the pad416. In some implementations, the combination of the via414and the pad416traverses from the first surface of the substrate410to the second surface of the substrate410. In some implementations, the via414and/or the pad416is a form of an interconnect that traverses the substrate410.

It should be noted that the substrate410may include additional interconnects (e.g., traces, vias), which are not shown for the purpose of clarity. These un-shown (or not visible) interconnects may couple the capacitors417and/or419to the via414and/or pad416in some implementations. In some implementations, at least one of the capacitors417and/or419may be electrically coupled to at least the first die402and/or the second die406. For example, the capacitor417may be electrically coupled to the first die402through the via414, the interconnect422, the interconnect444, and/or the interconnect404. Similarly, the capacitor417may be electrically coupled to the second die406through the via414, the pad416, the interconnect432, the interconnect454, the interconnect408, and/or the interconnect409.

In some implementations, the first capacitor417is a first plate capacitor. In some implementations, the second capacitor419is a second plate capacitor419. In some implementations, a plate capacitor is defined by two interconnects separated by a gap. In some implementations, the gap is defined by one or more dielectric layers. The first and second capacitors417and419are further described in detail below inFIG. 5.

The first die402includes a back side and a front side (e.g., active side). The front side is coupled to a set of die interconnects404. The set of die interconnects404may be one of at least pads and/or pillars in some implementations. The back side of the first die402is coupled to the first surface of the substrate410. In some implementations, a bonding agent (e.g., glue) is used to couple the back side of the first die402to the first surface of the substrate410. As shown inFIG. 4, the back side of the first die402is facing the substrate410while the front side (e.g., active side) of the first die402is facing away from the substrate410.

The first encapsulation layer420encapsulates the first die402and the set of die interconnects404. In some implementations, the first encapsulation layer420is one of at least a mold, a polymer, and/or a photo-etchable material. In some implementations, a photo-etchable material is a material that may be etched through a photo etching process. The first encapsulation layer420includes a set of interconnects422. In some implementations, the set of interconnects422is one of at least a through encapsulation via (TEV) and/or a through mold via (TMV). In some implementations, the set of interconnects422traverses from a first surface (e.g., top surface) of the first encapsulation layer420to a second surface (e.g., bottom surface) of the first encapsulation layer420.FIG. 4illustrates that a portion of the set of interconnects422in the first encapsulation layer420is coupled to the via414in the substrate410.

The first redistribution portion440is coupled to the first surface of the first encapsulation layer420. The first redistribution portion440includes a fourth dielectric layer442and a first set of redistribution interconnects444. In some implementations, the first redistribution portion440may include more than one set of redistribution interconnects. The first set of redistribution interconnects444is coupled to the set of die interconnects404and the set of interconnects422. In some implementations, the fourth dielectric layer442includes one or more dielectric layers.

The second die406includes a back side and a front side (e.g., active side). The front side is coupled to a set of interconnects408. The set of interconnects408may be one of at least pads and/or pillars in some implementations. The back side of the second die406is coupled to the second surface of the substrate410. In some implementations, a bonding agent (e.g., glue) is used to couple the back side of the second die406to the second surface of the substrate410. As shown inFIG. 4, the back side of the second die406is facing the substrate410while the front side (e.g., active side) of the second die406is facing away from the substrate410.

The second encapsulation layer430encapsulates the second die406and the set of interconnects408. In some implementations, the second encapsulation layer430is one of at least a mold, a polymer, and/or a photo-etchable material. In some implementations, a photo-etchable material is a material that may be etched through a photo etching process. The second encapsulation layer430includes a set of interconnects432and a set of interconnects409. In some implementations, the set of interconnects432is one of at least a through encapsulation via (TEV) and/or a through mold via (TMV). In some implementations, the set of interconnects432traverses from a first surface (e.g., top surface) of the second encapsulation layer430to a second surface (e.g., bottom surface) of the second encapsulation layer430.FIG. 4illustrates that a portion of the set of interconnects432in the second encapsulation layer430is coupled to the pad416in the substrate410. In some implementations, the set of interconnects409is one of at least a through encapsulation via (TEV) and/or a through mold via (TMV). The set of interconnects409is coupled to the set of interconnects408.

The second redistribution portion450is coupled to the first surface of the second encapsulation layer430. The second redistribution portion450includes a fifth dielectric layer452, a second set of redistribution interconnects454, a third set of redistribution interconnects456, and a set of under bump metallization (UBM) layers458. In some implementations, the second redistribution portion450may include one, two, or more than two sets of redistribution interconnects. The first set of redistribution interconnects454is coupled to the set of interconnects409and the set of interconnects432. In some implementations, the fifth dielectric layer452includes one or more dielectric layers.

A set of solder balls460is coupled to the set of UBM layers458. In some implementations, the UBM layers458is optional. In such instances, the set of solder balls460may be directly coupled to one of the redistribution interconnects.

FIG. 5illustrates a close-up view of a portion of the substrate410ofFIG. 4. As shown inFIG. 5, the substrate410includes the first dielectric layer412, the second dielectric layer413, the third dielectric layer415, the via414, the pad416, the first capacitor417and the second capacitor419. In some implementations, the substrate410is a laminate substrate. The substrate410includes a first surface (e.g., top surface) and a second surface (e.g., bottom surface). The via414is coupled to the pad416. In some implementations, the combination of the via414and the pad416traverses from the first surface of the substrate410to the second surface of the substrate410. In some implementations, the via414and/or the pad416is a form of an interconnect that traverses the substrate410.

In some implementations, the first capacitor417is a first plate capacitor. As shown inFIG. 5, the first capacitor417includes a first via502, a first interconnect504, a second interconnect506, and a second via508. In some implementations, the first via502is a first terminal of the first capacitor417. In some implementations, the first interconnect504is a first plate of the first capacitor417. In some implementations, the second interconnect506is a second plate of the first capacitor417. In some implementations, the second via508is a second terminal of the first capacitor417. In some implementations, the first interconnect504and the second interconnect506are at least substantially parallel to each other. As shown inFIG. 5, the first interconnect504and the second interconnect506are separated by a gap and/or spacing. The gap and/or spacing is filled with a layer of the third dielectric layer415. In some implementations, the use of the third dielectric layer415increases the capacitance of the first capacitor417. In some implementations, each of the first and second vias502and508may include one or more vias, or a combination of interconnects, vias, and/or pads.

In some implementations, the second capacitor419is a second plate capacitor. As shown inFIG. 5, the second capacitor419includes a third via512, a third interconnect514, a fourth interconnect516, and a fourth via518. In some implementations, the third via512is a first terminal of the second capacitor419. In some implementations, the third interconnect514is a first plate of the second capacitor419. In some implementations, the fourth interconnect516is a second plate of the second capacitor419. In some implementations, the fourth via518is a second terminal of the second capacitor419. In some implementations, the third interconnect514and the fourth interconnect516are at least substantially parallel to each other. As shown inFIG. 5, the third interconnect514and the fourth interconnect516are separated by a gap and/or spacing. The gap and/or spacing is filled with a layer of the third dielectric layer415. In some implementations, the use of the third dielectric layer415increases the capacitance of the second capacitor419. In some implementations, each of the third and fourth vias512and518may include one or more vias, or a combination of interconnects, vias, and/or pads.

In some implementations, the second capacitor419is a second plate capacitor419. In some implementations, a plate capacitor is defined by two interconnects separated by a gap. In some implementations, the gap is defined by the third dielectric layer415.

It should be noted that the substrate410may include additional interconnects (e.g., traces, vias), which are not shown for the purpose of clarity. These un-shown (or not visible) interconnects may couple the capacitors417and/or419to the via414and/or pad416in some implementations. For example, the interconnect506and/or the via508may be coupled to the via414through one or more interconnects (e.g., trace and/or via) in the substrate410. Similarly, in some implementations, the via502and/or the interconnect504may be coupled to the via414and/or the pad416through one or more interconnects (e.g., trace and/or via) in the substrate410.

Exemplary Package on Package (PoP) Integrated Device that Includes an Embedded Package Substrate (EPS) Capacitor in a Substrate

FIG. 6illustrates an exemplary package on package (PoP) integrated device600that includes a capacitor in a substrate. As shown inFIG. 6, the integrated device600(e.g., integrated package device) includes a first die602, a second die606, a substrate610, a first encapsulation layer620, a second encapsulation layer630, a first redistribution portion640, and a second redistribution portion650.

The substrate610includes a dielectric layer612, a via614, a pad616, a capacitor618. In some implementations, the substrate610is a laminate substrate. The substrate610includes a first surface (e.g., top surface) and a second surface (e.g., bottom surface). In some implementations, the dielectric layer612may include several dielectric layers. In some implementations, the dielectric layers may be the same material. The via614is coupled to the pad616. In some implementations, the combination of the via614and the pad616traverse from the first surface of the substrate610to the second surface of the substrate610. In some implementations, the via614and/or the pad616is a form of an interconnect that traverse the substrate610.

In some implementations, the capacitor618is an embedded package substrate (EPS) capacitor. The capacitor618is further described in detail below inFIG. 7.

The first die602includes a back side and a front side (e.g., active side). The front side is coupled to a set of die interconnects604. The set of die interconnects604may be one of at least pads and/or pillars in some implementations. The back side of the first die602is coupled to the first surface of the substrate610. In some implementations, a bonding agent (e.g., glue) is used to couple the back side of the first die602to the first surface of the substrate610. As shown inFIG. 6, the back side of the first die602is facing the substrate610while the front side (e.g., active side) of the first die602is facing away from the substrate610.

The first encapsulation layer620encapsulates the first die602and the set of die interconnects604. In some implementations, the first encapsulation layer620is one of at least a mold, a polymer, and/or a photo-etchable material. In some implementations, a photo-etchable material is a material that may be etched through a photo etching process. The first encapsulation layer620includes a set of interconnects622. In some implementations, the set of interconnects622is one of at least a through encapsulation via (TEV) and/or a through mold via (TMV). In some implementations, the set of interconnects622traverses from a first surface (e.g., top surface) of the first encapsulation layer620to a second surface (e.g., bottom surface) of the first encapsulation layer620.FIG. 6illustrates that a portion of the set of interconnects622in the first encapsulation layer620is coupled to the via614in the substrate610.

The first redistribution portion640is coupled to the first surface of the first encapsulation layer620. The first redistribution portion640includes a second dielectric layer642and a first set of redistribution interconnects644. In some implementations, the first redistribution portion640may include more than one set of redistribution interconnects. The first set of redistribution interconnects644is coupled to the set of die interconnects604and the set of interconnects622. In some implementations, the second dielectric layer642includes one or more dielectric layers.

The second die606includes a back side and a front side (e.g., active side). The front side is coupled to a set of interconnects608. The set of interconnects608may be one of at least pads and/or pillars in some implementations. The back side of the second die606is coupled to the second surface of the substrate610. In some implementations, a bonding agent (e.g., glue) is used to couple the back side of the second die606to the second surface of the substrate610. As shown inFIG. 6, the back side of the second die606is facing the substrate610while the front side (e.g., active side) of the second die606is facing away from the substrate610.

The second encapsulation layer630encapsulates the second die606and the set of interconnects608. In some implementations, the second encapsulation layer630is one of at least a mold, a polymer, and/or a photo-etchable material. In some implementations, a photo-etchable material is a material that may be etched through a photo etching process. The second encapsulation layer630includes a set of interconnects632and a set of interconnects609. In some implementations, the set of interconnects632is one of at least a through encapsulation via (TEV) and/or a through mold via (TMV). In some implementations, the set of interconnects632traverses from a first surface (e.g., top surface) of the second encapsulation layer630to a second surface (e.g., bottom surface) of the second encapsulation layer630.FIG. 6illustrates that a portion of the set of interconnects632in the second encapsulation layer630is coupled to the pad616in the substrate610. In some implementations, the set of interconnects609is one of at least a through encapsulation via (TEV) and/or a through mold via (TMV). The set of interconnects609is coupled to the set of interconnects608.

The second redistribution portion650is coupled to the first surface of the second encapsulation layer630. The second redistribution portion650includes a third dielectric layer652, a second set of redistribution interconnects654, a third set of redistribution interconnects656, and a set of under bump metallization (UBM) layers658. In some implementations, the second redistribution portion650may include one, two, or more than two sets of redistribution interconnects. The first set of redistribution interconnects654is coupled to the set of interconnects609and the set of interconnects632. In some implementations, the third dielectric layer652includes one or more dielectric layers.

It should be noted that the substrate610may include additional interconnects (e.g., traces, vias), which are not shown for the purpose of clarity. These un-shown (or not visible) interconnects may couple the capacitor618to the via614and/or pad616in some implementations. In some implementations, the capacitor618may be electrically coupled to at least the first die602and/or the second die606. For example, the capacitor618may be electrically coupled to the first die602through the via614, the interconnect622, the interconnect644, and/or the interconnect604. Similarly, the capacitor618may be electrically coupled to the second die606through the via614, the pad616, the interconnect632, the interconnect654, the interconnect608, and/or the interconnect609.

A set of solder balls660is coupled to the set of UBM layers658. In some implementations, the UBM layers658are optional. In such instances, the set of solder balls660may be directly coupled to one of the redistribution interconnects.

FIG. 7illustrates a close-up view of a portion of the substrate610ofFIG. 6. As shown inFIG. 7, the substrate610includes the dielectric layer612, the via614, the pad616, the capacitor618, a dielectric layer702, a first via704, a first interconnect706, a second via714, and a second interconnect716. In some implementations, the substrate610is a laminate substrate. The substrate610includes a first surface (e.g., top surface) and a second surface (e.g., bottom surface). In some implementations, the dielectric layer612may include several dielectric layers. The via614is coupled to the pad616. In some implementations, the combination of the via614and the pad616traverses from the first surface of the substrate610to the second surface of the substrate610. In some implementations, the via614and/or the pad616is a form of an interconnect that traverses the substrate610.

In some implementations, the capacitor618is an embedded package substrate (EPS) capacitor. As shown inFIG. 7, the capacitor618is at least partially surrounded by the dielectric layers612and702. The capacitor618includes a set of interconnects (e.g., pads, pillar), which are coupled to the first and second interconnects706and716.

It should be noted that the substrate610may include additional interconnects (e.g., traces, vias), which are not shown for the purpose of clarity. These un-shown (or not visible) interconnects may couple the capacitor618to the via614and/or pad616in some implementations. For example, the via704and/or the interconnect706may be coupled to the via614through one or more interconnects (e.g., trace and/or via) in the substrate610. Similarly, in some implementations, the via714and/or the interconnect716may be coupled to the via614and/or the pad616through one or more interconnects (e.g., trace and/or via) in the substrate610.

Exemplary Sequence for Providing/Fabricating a Substrate that Includes a Capacitor

In some implementations, providing/fabricating a substrate with a capacitor includes several processes.FIG. 8(which includesFIGS. 8A-8B) illustrates an exemplary sequence for providing/fabricating a substrate that includes a capacitor. In some implementations, the sequence ofFIGS. 8A-8Bmay be used to provide/fabricate the substrate ofFIGS. 2, 3, 4, 5, and/or other substrates in the present disclosure. However, for the purpose of simplification,FIGS. 8A-8Bwill be described in the context of providing/fabricating the substrate ofFIG. 4orFIG. 5.

It should be noted that the sequence ofFIGS. 8A-8Bmay combine one or more stages in order to simplify and/or clarify the sequence for providing a substrate. In some implementations, the order of the processes may be changed or modified.

Stage1ofFIG. 8A, illustrates a state after a carrier800is provided. In some implementations, the carrier800is provided by a supplier. In some implementations, the carrier800is fabricated (e.g., formed). In some implementations, the carrier800may be a substrate and/or a wafer.

Stage2illustrates a state after a first metal layer802is provided (e.g., formed) on the carrier800. Specifically, stage2illustrates a state after the first metal layer802is formed over a first surface of the carrier800. In some implementations, providing the first metal layer802may include forming the first metal layer802and selectively etching portions of the first metal layer802to define one or more interconnects (e.g., form one or more pads, vias, traces). In some implementations, the first metal layer802is plated on the carrier800using a plating process. Examples of plating processes are described inFIGS. 12-17.

Stage3illustrates a state after a first dielectric layer804is provided on the carrier800.

Stage4illustrates a state after a second metal layer806is provided (e.g., formed) on the first dielectric layer804. Specifically, stage4illustrates a state after the second metal layer806is formed over a first surface of the first dielectric layer804. In some implementations, providing the second metal layer806may include forming the second metal layer806and selectively etching portions of the second metal layer806to define one or more interconnects (e.g., form one or more pads, vias, traces). In some implementations, the second metal layer806is plated on the first dielectric layer804using a plating process. In some implementations, some portions of the second metal layer806may be coupled to some portions of the first metal layer802.

Stage5illustrates a state after a second dielectric layer808is provided on the first dielectric layer804.

Stage6illustrates a state after a third metal layer810is provided (e.g., formed) on the second dielectric layer808. Specifically, stage6illustrates a state after the third metal layer810is formed over a first surface of the second dielectric layer808. In some implementations, providing the third metal layer810may include forming the third metal layer810and selectively etching portions of the third metal layer810to define one or more interconnects (e.g., form one or more pads, vias, traces). In some implementations, the third metal layer810is plated on the second dielectric layer808using a plating process. In some implementations, some portions of the third metal layer810may be coupled to some portions of the second metal layer806.

Stage7illustrates a state after a third dielectric layer812is provided on the second dielectric layer808. In some implementations, the third dielectric layer812is made of a different material than the second dielectric layer808. In some implementations, the third dielectric layer812has a k value that is substantially higher than the k value of the second dielectric layer808. It should be noted that in some implementations, the third dielectric layer812may be the same material as the second dielectric layer808.

Stage8ofFIG. 8B, illustrates a state after a fourth metal layer814is provided (e.g., formed) on the third dielectric layer808. Specifically, stage8illustrates a state after the fourth metal layer814is formed over a first surface of the third dielectric layer812. In some implementations, providing the fourth metal layer814may include forming the fourth metal layer814and selectively etching portions of the fourth metal layer814to define one or more interconnects (e.g., form one or more pads, vias, traces). In some implementations, the fourth metal layer814is plated on the third dielectric layer812using a plating process. In some implementations, some portions of the fourth metal layer814may be coupled to some portions of the third metal layer810.

Stage9illustrates a state after a fourth dielectric layer816is provided on the third dielectric layer812.

Stage10illustrates a state after a fifth metal layer818is provided (e.g., formed) on the fourth dielectric layer816. Specifically, stage10illustrates a state after the fifth metal layer818is formed over a first surface of the fourth dielectric layer816. In some implementations, providing the fifth metal layer818may include forming the fifth metal layer818and selectively etching portions of the fifth metal layer818to define one or more interconnects (e.g., form one or more pads, vias, traces). In some implementations, the fifth metal layer818is plated on the fourth dielectric layer816using a plating process. In some implementations, some portions of the fifth metal layer818may be coupled to some portions of the fourth metal layer814.

Stage11illustrates a state after a fifth dielectric layer820is provided on the fourth dielectric layer816.

Stage12illustrates a state after at least one cavity821is formed in at least one of the dielectric layers. As shown at stage12, the cavity821is formed over a pad822(which is part of the first metal layer802). The cavity traverses, the first, second, third, fourth and fifth dielectric layers804,808,812,816, and820. In some implementations, the cavity821is formed using a laser etching process (e.g., laser ablation).

Stage13illustrates a state after the cavity821is filled with a metal material to define an interconnect824. In some implementations, the interconnect824is a via that is coupled to the pad822. Different implementations may use different processes to fill the cavity821. In some implementations, a plating process is used. In some implementations, the cavity821is filled with a conducting paste.

Stage14illustrates a state after the carrier800is removed (e.g., etched away), leaving behind the substrate830that includes a first capacitor840and a second capacitor850.

Exemplary Sequence for Providing/Fabricating a Substrate that Includes an Embedded Package Substrate (EPS) Capacitor

In some implementations, providing/fabricating a substrate with an embedded package substrate (EPS) capacitor includes several processes.FIG. 9(which includesFIGS. 9A-9B) illustrates an exemplary sequence for providing/fabricating a substrate that includes an EPS capacitor. In some implementations, the sequence ofFIGS. 9A-9Bmay be used to provide/fabricate the substrate ofFIGS. 6, 7, and/or other substrates in the present disclosure. However, for the purpose of simplification,FIGS. 9A-9Bwill be described in the context of providing/fabricating the substrate ofFIG. 6orFIG. 7.

It should be noted that the sequence ofFIGS. 9A-9Bmay combine one or more stages in order to simplify and/or clarify the sequence for providing a substrate. In some implementations, the order of the processes may be changed or modified.

Stage1ofFIG. 9A, illustrates a state after a carrier900is provided. In some implementations, the carrier900is provided by a supplier. In some implementations, the carrier900is fabricated (e.g., formed). In some implementations, the carrier900may be a substrate and/or a wafer.

Stage2illustrates a state after a first metal layer902is provided (e.g., formed) on the carrier900. Specifically, stage2illustrates a state after the first metal layer902is formed over a first surface of the carrier900. In some implementations, providing the first metal layer902may include forming the first metal layer902and selectively etching portions of the first metal layer902to define one or more interconnects (e.g., form one or more pads, vias, traces). In some implementations, the first metal layer902is plated on the carrier900using a plating process. Examples of a plating process are described inFIGS. 12-17.

Stage3illustrates a state after a first dielectric layer904is provided on the carrier900.

Stage4illustrates a state after a second dielectric layer908is provided on the first dielectric layer904.

Stage5illustrates a state after a cavity909is formed in at least one of the dielectric layers. As shown in stage5, the cavity909is formed in the second dielectric layer908and at least part of the first dielectric layer904.

Stage6illustrates a state after en embedded package substrate (EPS) capacitor910is provided in the cavity909. The EPS capacitor910includes terminals (e.g., pads). The terminals of the EPS capacitor910face away from the carrier900.

Stage7illustrates a state after a third dielectric layer912is provided on the EPS capacitor910in the cavity909. In some implementations, the third dielectric layer912is made of a same or different material than the second dielectric layer908and/or the first dielectric layer904.

Stage8ofFIG. 9B, illustrates a state after a second metal layer914is provided (e.g., formed) on the third dielectric layer912. Specifically, stage8illustrates a state after the second metal layer914is formed over a first surface of the third dielectric layer912and/or the second dielectric layer908. In some implementations, providing the second metal layer914may include forming the second metal layer914and selectively etching portions of the second metal layer914to define one or more interconnects (e.g., form one or more pads, vias, traces). In some implementations, the second metal layer914is plated on the third dielectric layer912and/or the second dielectric layer908using a plating process. In some implementations, some portions of the second metal layer914may be coupled to some portions of the terminals of the EPS capacitor910.

Stage9illustrates a state after a fourth dielectric layer916is provided on the third dielectric layer912and the second dielectric layer908.

Stage10illustrates a state after a third metal layer918is provided (e.g., formed) on the fourth dielectric layer916. Specifically, stage10illustrates a state after the third metal layer918is formed over a first surface of the fourth dielectric layer916. In some implementations, providing the third metal layer918may include forming the third metal layer918and selectively etching portions of the third metal layer918to define one or more interconnects (e.g., form one or more pads, vias, traces). In some implementations, the third metal layer918is plated on the fourth dielectric layer916using a plating process. In some implementations, some portions of the third metal layer918may be coupled to some portions of the second metal layer914.

Stage11illustrates a state after a fifth dielectric layer920is provided on the fourth dielectric layer916.

Stage12illustrates a state after at least one cavity921is formed in at least one of the dielectric layers. As shown at stage12, the cavity921is formed over a pad922(which is part of the first metal layer902). The cavity traverses, the first, second, fourth, and fifth dielectric layers904,908,916, and920. In some implementations, the dielectric layer923may represent the first, second, fourth, and fifth dielectric layers904,908,916, and920. In some implementations, the cavity921is formed using a laser etching process (e.g., laser ablation).

Stage13illustrates a state after the cavity921is filled with a metal material to define an interconnect924. In some implementations, the interconnect924is a via that is coupled to the pad922. Different implementations may use different processes to fill the cavity921. In some implementations, a plating process is used. In some implementations, the cavity921is filled with a conducting paste.

Stage14illustrates a state after the carrier900is removed (e.g., etched away), leaving behind the substrate930that includes the EPS capacitor910.

Exemplary Sequence for Providing/Fabricating a Package-on Package (PoP) Integrated Device Comprising a Substrate that Includes a Capacitor

In some implementations, providing/fabricating a package-on-package (PoP) integrated device that includes a substrate with a capacitor includes several processes.FIG. 10(which includesFIGS. 10A-10C) illustrates an exemplary sequence for providing/fabricating a PoP integrated device that includes a substrate with a capacitor. In some implementations, the sequence ofFIGS. 10A-10Cmay be used to provide/fabricate the integrated device ofFIGS. 2, 4, 6, and/or other integrated devices in the present disclosure. However, for the purpose of simplification,FIGS. 10A-10Cwill be described in the context of providing/fabricating the integrated device ofFIG. 4.

It should be noted that the sequence ofFIGS. 10A-10Cmay combine one or more stages in order to simplify and/or clarify the sequence for providing an integrated device. In some implementations, the order of the processes may be changed or modified.

Stage1ofFIG. 10A, illustrates a state after a substrate1000that includes a capacitor is provided. In some implementations, the substrate1000is similar to the substrate210ofFIG. 2, the substrate410ofFIG. 4, or the substrate610ofFIG. 6, described above. In some implementations, the substrate1000is provided by a supplier. In some implementations, the substrate1000is fabricated (e.g., formed). The substrate1000includes a via1001and a pad1003. The via1001is coupled to the pad1003.

Stage2illustrates a state after an interconnect1005is provided (e.g., formed) on the substrate1000. Specifically, the interconnect1005is provided over the via1001. In some implementations, the interconnect1005is a via (e.g., through encapsulation via, through mold via). The interconnect1005may be formed on the substrate through one or more plating processes.

Stage3illustrates a state after a first die1002is provided and coupled to a first surface (e.g., top surface) of the substrate1000. The first die1002may include a back side and a front side (e.g., active side). In some implementations, the back side of the first die1002is coupled to the first surface of the substrate1000using a bonding agent (e.g., glue).

Stage4illustrates a state after a first encapsulation layer1004is provided (e.g., formed) on the first surface of the substrate1000. The first encapsulation layer1004covers the first die1002and at least some of the interconnect1005.

Stage5illustrates a state after a first redistribution interconnect1006is provided (e.g., formed) on the first encapsulation layer1004. In some implementations, the first redistribution interconnect1006is formed by forming one or more metal layers and selectively etching portions of the one or more metal layers. The first redistribution interconnect1006is coupled to the via1001and the first die1002.

Stage6illustrates a state after a first dielectric layer1008is provided (e.g., formed) on the first encapsulation layer1004and the first redistribution interconnect1006.

Stage7ofFIG. 10B, illustrates a state after a second die1012is provided and coupled to a second surface (e.g., bottom surface) of the substrate1000. The second die1012may include a back side and a front side (e.g., active side). In some implementations, the back side of the second die1012is coupled to the second surface of the substrate1002using a bonding agent (e.g., glue). In some implementations, the substrate1002may be flipped upside down before the second die1012is coupled to the second surface of the substrate1000.

Stage8illustrates a state after a second encapsulation layer1014is provided (e.g., formed) on the second surface of the substrate1000. The second encapsulation layer1014covers the second die1012. In some implementations, the second encapsulation layer1014is photo-etchable material.

Stage9illustrates a state after a first cavity1015and a second cavity1017are formed in the second encapsulation layer1014. Different implementations may use different processes for forming the cavities. In some implementations, a laser etching process (e.g., laser ablation) is used to form the cavities. In some implementations, a photo-etching process is used to form the cavities. As shown at stage9, the cavity1015is formed on the pad1003, and the cavity1017is formed on an interconnect (e.g., pad, pillar) of the second die1012.

Stage10illustrates a state after the first cavity1015and the second cavity1017are filled with an electrically conductive material to form an interconnect1016, and an interconnect1018, respectively. In some implementations, the interconnect1016is a via (e.g., through encapsulation via, through mold via). In some implementations, the interconnect1018is a via (e.g., through encapsulation via, through mold via).

Stage11illustrates a state after a second redistribution interconnect1020is provided (e.g., formed) on the second encapsulation layer1014. In some implementations, the second redistribution interconnect1020is formed by forming one or more metal layers and selectively etching portions of the one or more metal layers. The second redistribution interconnect1020may be coupled to the interconnect1005and the second die1012.

Stage12ofFIG. 10C, illustrates a state after a second dielectric layer1022is provided (e.g., formed) on the second encapsulation layer1014and the second redistribution interconnect1020.

Stage13illustrates a state after a third redistribution interconnect1024is provided (e.g., formed) on the second dielectric layer1022. In some implementations, the third redistribution interconnect1024is formed by forming one or more metal layers and selectively etching portions of the one or more metal layers. The third redistribution interconnect1024may be coupled to at least some of the second redistribution interconnect1020. In some implementations, portions of the second dielectric layer1022may be selectively etched before providing (e.g., forming) the third redistribution interconnect1024.

Stage14illustrates a state after a third dielectric layer1026is provided (e.g., formed) on the second dielectric layer1022and the third redistribution interconnect1024. State14also illustrates a state after an under bump metallization (UBM) layer1028is provided on the third dielectric layer1026. In some implementations, the UBM layer1028is formed by forming one or more metal layers and selectively etching portions of the one or more metal layers. The UBM layer1028may be coupled to at least some of the third redistribution interconnect1024. In some implementations, portions of the third dielectric layer1026may be selectively etched before providing (e.g., forming) the UBM layer1028.

Stage15illustrates a state after a set of solder balls1030are coupled to the UBM layer1028. In some implementations, the UBM layer1028may be optional. In which case, the set of solder balls1030may be directly coupled to the third redistribution interconnect1024.

FIGS. 10A-10Cillustrates an example of providing/fabricating an integrated device (e.g., integrated package device) that includes a capacitor. In some implementations, the integrated may be fabricated in a different manner. For example, in some implementations, stages2-6may be repeated on the other side of the substrate1000to fabricate the integrated device instead of using stages7-12shown inFIGS. 10A-10C. That is, stages2-6illustrate how a first die, a first encapsulation layer, and a first redistribution portion are provided and/or formed on a first side (e.g., top side) of the substrate. In some implementations, stages2-6may be repeated to provide and/or form a second die, a second encapsulation layer, and a second redistribution portion on a second side (e.g., bottom side) of the substrate. In some implementations, stages13-15may remain the same even when stages2-6are repeated.

Exemplary Flow Diagram of a Method for Providing/Fabricating a Package-on Package (PoP) Integrated Device Comprising a Substrate that Includes a Capacitor

In some implementations, providing/fabricating a package-on-package (PoP) integrated device that includes a substrate with a capacitor includes several processes.FIG. 11illustrates an exemplary flow diagram for a method for providing/fabricating a PoP integrated device that includes a substrate with a capacitor. In some implementations, the method ofFIG. 11may be used to provide/fabricate the integrated device ofFIGS. 2, 4, 6, and/or other integrated devices in the present disclosure. It should be noted that the method ofFIG. 11may combine one or more steps in order to simplify and/or clarify the sequence for providing an integrated device. In some implementations, the order of the processes may be changed or modified.

The method provides (at1105) a substrate that includes a capacitor. In some implementations, the capacitor is embedded in the substrate. In some implementations, the capacitor is one of at least a plate capacitor and/or an embedded package substrate (EPS) capacitor.FIGS. 3, 5, and 7illustrate examples of substrates that include capacitors. In some implementations, the substrate is a laminate substrate and/or hybrid substrate. In some implementations, a hybrid substrate may include at least two different dielectric layers of different materials, one of which has k value that is substantially higher than the k value of the other dielectric layer. The substrate may includes interconnects, such as traces, pads and/or vias.FIGS. 8-9, and stage1ofFIG. 10Aillustrate examples of providing a substrate that includes a capacitor.

The method couples (at1110) a first die to a first surface of the substrate. In some implementations, the first die has a back side and front side (e.g., active side). In some implementations, the method couples the back side of the first die to the first surface of the substrate using a bonding agent (e.g., glue). Stage3ofFIG. 10Aillustrates an example of coupling a first die.

The method provides (at1115) a first encapsulation layer on the substrate. In some implementations, the first encapsulation layer is a photo-etchable material. In some implementations, providing the first encapsulation layer includes forming the first encapsulation layer on the first surface of the substrate and the first die. In some implementations, one or more interconnects (e.g., vias) may be formed in the first encapsulation layer. The interconnects may be formed before or after the first encapsulation layer is formed on the substrate. Stage4ofFIG. 10Billustrates an example of providing a first encapsulation layer.

The method provides (at1120) a first redistribution portion. The first redistribution portion may include one or more dielectric layers and one or more redistribution interconnects. In some implementations, providing the first redistribution portion includes forming one or more dielectric layers and one or more redistribution interconnects on the first encapsulation layer. In some implementations, the redistribution interconnects may couple the first die to interconnects in the first encapsulation layer. Stages5-6ofFIG. 10Billustrate an example of providing a first redistribution portion.

The method couples (at1125) a second die to a second surface of the substrate. In some implementations, the second die has a back side and front side (e.g., active side). In some implementations, the method couples the back side of the second die to the second surface of the substrate using a bonding agent (e.g., glue). Stage7ofFIG. 10Billustrates an example of coupling a second die.

The method provides (at1130) a second encapsulation layer on the substrate. In some implementations, the second encapsulation layer is a photo-etchable material. In some implementations, providing the second encapsulation layer includes forming the second encapsulation layer on the second surface of the substrate and the second die. In some implementations, one or more interconnects (e.g., vias) may be formed in the second encapsulation layer. The interconnects may be formed before or after the second encapsulation layer is formed on the substrate. Stages8-10ofFIG. 10Billustrate an example of providing a second encapsulation layer.

The method provides (at1135) a second redistribution portion. The second redistribution portion may include one or more dielectric layers and one or more redistribution interconnects. In some implementations, providing the second redistribution portion includes forming one or more dielectric layers, one or more redistribution interconnects, and/or one or more under bump metallization (UBM) layers on the second encapsulation layer. In some implementations, the redistribution interconnects may couple the second die to interconnects in the second encapsulation layer. Stage11ofFIG. 10Bto stage14ofFIG. 10Cillustrate an example of providing a second redistribution portion.

The method then provides (at1140) a set of solder balls. In some implementations, providing the set of solder balls includes coupling the set of solder balls to an under bump metallization (UBM) layer in the second redistribution portion or a redistribution interconnect in the second redistribution portion. Stage15ofFIG. 10Cillustrates an example of providing a set of solder balls.

Exemplary Interconnects with Seed Layers

Various interconnects (e.g., traces, vias, pads) are described in the present disclosure. These interconnects may be formed in the substrate, the encapsulation layer, and/or the redistribution portion of an integrated device (e.g., integrated package device). In some implementations, these interconnects may includes one or more metal layers. For example, in some implementations, these interconnects may include a first metal seed layer and a second metal layer. The metal layers may be provided (e.g., formed) using different plating processes. Below are detailed examples of interconnects (e.g., traces, vias, pads) with seed layers and how these interconnects may be formed using different plating processes.

FIG. 12illustrates a detailed profile view of a metal layer formed using a semi-additive patterning (SAP) process. Specifically,FIG. 12illustrates a first dielectric layer1202, a second organic dielectric layer1204, a first seed layer1220, and a second metal layer1222. The first seed layer1220is a metal layer (e.g., TiCu, TiWCu). In some implementations, the first seed layer1220is formed by a first deposition process (e.g., physical vapor deposition (PVD) or plating process). The second metal layer1222is formed by a second deposition process (e.g., plating process). The second metal layer1222includes a first metal portion layer1222aand a second metal portion layer1222b. In some implementations, the first metal portion layer1222ais a metal trace. In some implementations, the second metal portion1222bis a via/via structure. As shown inFIG. 12, the first seed layer1220is formed in a base portion of the second metal layer1222.FIG. 12illustrates that the first seed layer1220is not formed in the side planar portion of the second metal layer1222. More specifically,FIG. 12illustrates that the first seed layer1220is formed on the base portion (e.g., bottom portion) of the second metal layer1222, but not on the boundary side portions of the second metal layer1222. As described above, the second metal layer1222includes a first metal portion layer1222aand a second metal portion layer1222b. The first seed layer1220is formed on the base portion of both the first metal portion layer1222aand the second metal portion layer1222b. The first seed layer1220is formed on the side portion/wall of the second metal portion layer1222b(e.g., side portion/wall of the via/via structure), but not on the side portion/wall boundary of the first metal portion layer1222a. The metal layers may be formed using a semi-additive patterning (SAP) process. As mentioned above,FIGS. 14-15illustrate an example of a semi-additive patterning (SAP) process in some implementations.

FIG. 13illustrates a detailed profile view of a metal layer formed using a damascene process. Specifically,FIG. 13illustrates a first dielectric layer1302(e.g., inorganic dielectrics, polymer), a second dielectric layer1304(e.g., inorganic dielectrics, polymer), a first seed layer1320, a second metal layer1322, a third seed layer1340, and a fourth metal layer1342. The first seed layer1320and/or the third seed layer1340are metal layers (e.g., TiTiN/Cu, TaTaN/Cu). In some implementations, the first seed layer1320and/or the third seed layer1340are formed by a first deposition process (e.g., chemical vapor deposition (CVP) or physical vapor deposition (PVD)). The second metal layer1322and/or the fourth metal layer1342are formed by a second deposition process (e.g., plating process). As shown inFIG. 13, the first seed layer1320is formed in a base horizontal planar portion and a side planar portion (e.g., vertical planar portion) of the second metal layer1322. Similarly, the third seed layer1340is formed in a base horizontal planar portion and a side planar portions (e.g., vertical planar portions) of the fourth metal layer1342. As mentioned above,FIGS. 16-17illustrate an example of a damascene process in some implementations.

FIG. 14illustrates a sequence for forming an interconnect using a semi-additive patterning (SAP) process to provide and/or form an interconnect (e.g., trace, via) in one or more dielectric layer(s). As shown inFIG. 14, stage1illustrates a state of an integrated device (e.g., substrate) after a dielectric layer1402is provided (e.g., formed). In some implementations, stage1illustrates that the dielectric layer1402includes a first metal layer1404. The first metal layer1404is a seed layer in some implementations. In some implementations, the first metal layer1404may be provided (e.g., formed) on the dielectric layer1402after the dielectric layer1402is provided (e.g., received or formed). Stage1illustrates that the first metal layer1404is provided (e.g., formed) on a first surface of the dielectric layer1402. In some implementations, the first metal layer1404is provided by using a deposition process (e.g., PVD, CVD, plating process).

Stage2illustrates a state of the integrated device after a photo resist layer1406(e.g., photo develop resist layer) is selectively provided (e.g., formed) on the first metal layer1404. In some implementations, selectively providing the resist layer1406includes providing a first resist layer1406on the first metal layer1404and selectively removing portions of the resist layer1406by developing (e.g., using a development process). Stage2illustrates that the resist layer1406is provided such that a cavity1408is formed.

Stage3illustrates a state of the integrated device after a second metal layer1410is formed in the cavity1408. In some implementations, the second metal layer1410is formed over an exposed portion of the first metal layer1404. In some implementations, the second metal layer1410is provided by using a deposition process (e.g., plating process).

Stage4illustrates a state of the integrated device after the resist layer1406is removed. Different implementations may use different processes for removing the resist layer1406.

Stage5illustrates a state of the integrated device after portions of the first metal layer1404are selectively removed. In some implementations, one or more portions of the first metal layer1404that is not covered by the second metal layer1410is removed. As shown in stage5, the remaining first metal layer1404and the second metal layer1410may form and/or define an interconnect1412(e.g., trace, vias, pads) in an integrated device and/or a substrate. In some implementations, the first metal layer1406is removed such that a dimension (e.g., length, width) of the first metal layer1404underneath the second metal layer1410is smaller than a dimension (e.g., length, width) of the second metal layer1410, which can result in an undercut, as shown at stage5ofFIG. 14. In some implementations, the above mentioned processes may be iterated several times to provide and/or form several interconnects in one or more dielectric layers of an integrated device and/or substrate.

FIG. 15illustrates a flow diagram for a method for using a (SAP) process to provide and/or form an interconnect in one or more dielectric layer(s). The method provides (at1505) a dielectric layer (e.g., dielectric layer1402). In some implementations, providing the dielectric layer includes forming the dielectric layer. In some implementations, providing the dielectric layer includes forming a first metal layer (e.g., first metal layer1404). The first metal layer is a seed layer in some implementations. In some implementations, the first metal layer may be provided (e.g., formed) on the dielectric layer after the dielectric layer is provided (e.g., received or formed). In some implementations, the first metal layer is provided by using a deposition process (e.g., physical vapor deposition (PVD) or plating process).

The method selectively provides (at1510) a photo resist layer (e.g., a photo develop resist layer1406) on the first metal layer. In some implementations, selectively providing the resist layer includes providing a first resist layer on the first metal layer and selectively removing portions of the resist layer (which provides one or more cavities).

The method then provides (at1515) a second metal layer (e.g., second metal layer1410) in the cavity of the photo resist layer. In some implementations, the second metal layer is formed over an exposed portion of the first metal layer. In some implementations, the second metal layer is provided by using a deposition process (e.g., plating process).

The method further removes (at1520) the resist layer. Different implementations may use different processes for removing the resist layer. The method also selectively removes (at1525) portions of the first metal layer. In some implementations, one or more portions of the first metal layer that is not covered by the second metal layer are removed. In some implementations, any remaining first metal layer and second metal layer may form and/or define one or more interconnects (e.g., trace, vias, pads) in an integrated device and/or a substrate. In some implementations, the above mentioned method may be iterated several times to provide and/or form several interconnects in one or more dielectric layers of an integrated device and/or substrate.

Exemplary Damascene Process

FIG. 16illustrates a sequence for forming an interconnect using a damascene process to provide and/or form an interconnect in a dielectric layer. As shown inFIG. 16, stage1illustrates a state of an integrated device after a dielectric layer1602is provided (e.g., formed). In some implementations, the dielectric layer1602is an inorganic layer (e.g., inorganic film).

Stage2illustrates a state of an integrated device after a cavity1604is formed in the dielectric layer1602. Different implementations may use different processes for providing the cavity1604in the dielectric layer1602.

Stage3illustrates a state of an integrated device after a first metal layer1606is provided on the dielectric layer1602. As shown in stage3, the first metal layer1606provided on a first surface of the dielectric later1602. The first metal layer1606is provided on the dielectric layer1602such that the first metal layer1606takes the contour of the dielectric layer1602including the contour of the cavity1604. The first metal layer1606is a seed layer in some implementations. In some implementations, the first metal layer1606is provided by using a deposition process (e.g., physical vapor deposition (PVD), Chemical Vapor Deposition (CVP) or plating process).

Stage4illustrates a state of the integrated device after a second metal layer1608is formed in the cavity1604and a surface of the dielectric layer1602. In some implementations, the second metal layer1608is formed over an exposed portion of the first metal layer1606. In some implementations, the second metal layer1608is provided by using a deposition process (e.g., plating process).

Stage5illustrates a state of the integrated device after the portions of the second metal layer1608and portions of the first metal layer1606are removed. Different implementations may use different processes for removing the second metal layer1608and the first metal layer1606. In some implementations, a chemical mechanical planazation (CMP) process is used to remove portions of the second metal layer1608and portions of the first metal layer1606. As shown in stage5, the remaining first metal layer1606and the second metal layer1608may form and/or define an interconnect1612(e.g., trace, vias, pads) in an integrated device and/or a substrate. As shown in stage5, the interconnect1612is formed in such a way that the first metal layer1606is formed on the base portion and the side portion(s) of the second metal layer1610. In some implementations, the cavity1604may include a combination of trenches and/or holes in two levels of dielectrics so that via and interconnects (e.g., metal traces) may be formed in a single deposition step, In some implementations, the above mentioned processes may be iterated several times to provide and/or form several interconnects in one or more dielectric layers of an integrated device and/or substrate.

FIG. 17illustrates a flow diagram of a method for forming an interconnect using a damascene process to provide and/or form an interconnect in a dielectric layer. The method provides (at1705) a dielectric layer (e.g., dielectric layer1602). In some implementations, providing a dielectric layer includes forming a dielectric layer. In some implementations, providing a dielectric layer includes receiving a dielectric layer from a supplier. In some implementations, the dielectric layer is an inorganic layer (e.g., inorganic film).

The method forms (at1710) at least one cavity (e.g., cavity1604) in the dielectric layer. Different implementations may use different processes for providing the cavity in the dielectric layer.

The method provides (at1715) a first metal layer (e.g., first metal layer1606) on the dielectric layer. In some implementations, the first metal layer is provided (e.g., formed) on a first surface of the dielectric later. In some implementations, the first metal layer is provided on the dielectric layer such that the first metal layer takes the contour of the dielectric layer including the contour of the cavity. The first metal layer is a seed layer in some implementations. In some implementations, the first metal layer1606is provided by using a deposition process (e.g., PVD, CVD or plating process).

The method provides (at1720) a second metal layer (e.g., second metal layer1608) in the cavity and a surface of the dielectric layer. In some implementations, the second metal layer is formed over an exposed portion of the first metal layer. In some implementations, the second metal layer is provided by using a deposition process (e.g., plating process). In some implementations, the second metal layer is similar or identical to the first metal layer. In some implementations, the second metal layer is different than the first metal layer.

The method then removes (at1725) portions of the second metal layer and portions of the first metal layer. Different implementations may use different processes for removing the second metal layer and the first metal layer. In some implementations, a chemical mechanical planazation (CMP) process is used to remove portions of the second metal layer and portions of the first metal layer. In some implementations, the remaining first metal layer and the second metal layer may form and/or define an interconnect (e.g., interconnect1612). In some implementations, an interconnect may include one of at least a trace, a via, and/or a pad) in an integrated device and/or a substrate. In some implementations, the interconnect is formed in such a way that the first metal layer is formed on the base portion and the side portion(s) of the second metal layer. In some implementations, the above mentioned method may be iterated several times to provide and/or form several interconnects in one or more dielectric layers of an integrated device and/or substrate.

Exemplary Electronic Devices

FIG. 18illustrates various electronic devices that may be integrated with any of the aforementioned integrated device, semiconductor device, integrated circuit, die, interposer, package or package-on-package (PoP). For example, a mobile telephone1802, a laptop computer1804, and a fixed location terminal1806may include an integrated device1800as described herein. The integrated device1800may be, for example, any of the integrated circuits, dice, packages, package-on-packages described herein. The devices1802,1804,1806illustrated inFIG. 18are merely exemplary. Other electronic devices may also feature the integrated device1800including, but not limited to, mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers or any other device that stores or retrieves data or computer instructions, or any combination thereof.

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another—even if they do not directly physically touch each other.

The various features of the invention described herein can be implemented in different systems without departing from the invention. It should be noted that the foregoing aspects of the disclosure are merely examples and are not to be construed as limiting the invention. The description of the aspects of the present disclosure is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.