Method for fabricating a semiconductor device

A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of semiconductor technology, and in particular to an improved method of manufacturing a magneto-resistive random access memory (MRAM) device.

2. Description of the Prior Art

MRAM is a non-volatile random access memory technology that could replace the dynamic random access memory (DRAM) as the standard memory for computing devices. In MRAM devices, the spin of electrons is used to indicate the presence of a “1” or “0.” MRAM devices comprise conductive lines (wordlines and bitlines) positioned in a different direction, e.g., perpendicular to one another in different metal layers, the conductive lines sandwiching a resistive memory element comprising a magnetic stack or magnetic tunnel junction (MTJ), which functions as a magnetic memory cell. A current flowing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic polarity into a certain direction along the wire or conductive line. A current flowing through the other conductive line induces the magnetic field and can partially turn the magnetic polarity, also. Digital information, represented as a “0” or “1,” is storable in the alignment of magnetic moments. The resistance of the magnetic memory cell depends on the moment's alignment. The stored state is read from the magnetic memory cell by detecting the component's resistive state.

The MTJ of the MRAM device typically comprises a first magnetic layer, a tunnel insulator formed over the first magnetic layer, and a second magnetic layer formed over the tunnel insulator. The first magnetic layer and the second magnetic layer each typically comprise one or more layers of magnetic materials and/or metal materials, for example. The first magnetic layer may comprise a seed layer of Ta and/or TaN, an antiferromagnetic layer such as PtMn disposed over the seed layer, and one or more magnetic material layers comprising CoFe, NiFe, CoFeB, Ru, other materials, or combinations thereof disposed over the antiferromagnetic layer, as examples. The first magnetic layer is also referred to as a fixed layer because its magnetic polarity is fixed. The second magnetic layer may comprise one or more magnetic material layers comprising CoFe, NiFe, CoFeB, other magnetic material layers, or combinations thereof, as examples. The second magnetic layer is also referred to as a free layer because its magnetic polarity changes when the magnetic memory cell is written to. The tunnel insulator may comprise a thin insulator such as Al2O3or semiconductive materials, as examples.

One of the challenges in forming MRAM devices during Back End of Line (BEOL) processing lies in the lithographic alignment of MTJs to the metal level beneath. Current approach to alignment for MTJ stacks is to introduce topography into the alignment mark area of the underlying metal level that can be seen through the MTJ. However, the chemical mechanical polishing (CMP) prior to MTJ stack deposition that is associated with this technique can lead to dishing, this making the alignment more difficult.

SUMMARY OF THE INVENTION

One object of the present invention is to provide an improved method of manufacturing a semiconductor device to solve the above-mentioned shortcomings and shortcomings of the prior art.

One aspect of the invention provides a method for fabricating a semiconductor device.

A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.

According to some embodiments, the polish stop layer is a tantalum nitride layer and the barrier layer is a titanium nitride layer.

According to some embodiments, the bottom electrode layer is a tantalum nitride layer.

According to some embodiments, a thickness of the polish stop layer is smaller than a thickness of the bottom electrode layer.

According to some embodiments, the thickness of the polish stop layer ranges between 20 and 60 angstroms and the thickness of the bottom electrode layer ranges between 100 and 200 angstroms.

According to some embodiments, after depositing the bottom electrode layer on the second dielectric layer and the via plug, the method further comprises: polishing the bottom electrode layer.

According to some embodiments, after the bottom electrode layer is conformally deposited on the second dielectric layer and the via plug, a magnetic tunnel junction (MTJ) stack layer is formed on the bottom electrode layer. A top electrode layer is then deposited on the MTJ stack layer. The top electrode layer, the MTJ stack layer and the bottom electrode layer are patterned, thereby forming magnetic memory element on the via plug.

According to some embodiments, the top electrode layer comprises a tantalum layer.

According to some embodiments, the MTJ stack layer comprises a reference layer, a tunnel barrier layer, and a free layer.

According to some embodiments, a nitrogen-doped carbide (NDC) layer is formed between the first dielectric layer and the second dielectric layer.

Another aspect of the invention provides a method for fabricating a semiconductor device. A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening and an alignment mark trench are formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening and the alignment mark trench. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A remaining portion of the tungsten layer within the alignment mark trench constitutes a recessed feature. A bottom electrode layer is conformally deposited on the second dielectric layer, the via plug and the recessed feature.

According to some embodiments, the polish stop layer is a tantalum nitride layer and the barrier layer is a titanium nitride layer.

According to some embodiments, the bottom electrode layer is a tantalum nitride layer.

According to some embodiments, a thickness of the polish stop layer is smaller than a thickness of the bottom electrode layer.

According to some embodiments, the thickness of the polish stop layer ranges between 20 and 60 angstroms and the thickness of the bottom electrode layer ranges between 100 and 200 angstroms.

According to some embodiments, after depositing the bottom electrode layer on the second dielectric layer, the via plug and the recessed feature, the method further comprises: polishing the bottom electrode layer.

According to some embodiments, after the bottom electrode layer is deposited, a magnetic tunnel junction (MTJ) stack layer is formed on the bottom electrode layer. A top electrode layer is then deposited on the MTJ stack layer. The top electrode layer, the MTJ stack layer and the bottom electrode layer are patterned, thereby forming magnetic memory element on the via plug.

According to some embodiments, the top electrode layer comprises a tantalum layer.

According to some embodiments, the MTJ stack layer comprises a reference layer, a tunnel barrier layer, and a free layer.

According to some embodiments, a nitrogen-doped carbide (NDC) layer is formed between the first dielectric layer and the second dielectric layer.

DETAILED DESCRIPTION

In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

Please refer toFIG. 1toFIG. 7.FIG. 1toFIG. 7are schematic diagrams showing an exemplary method for forming an integrated circuit device1, for example, a magnetic tunnel junction (MTJ) device, according to an embodiment of the present invention. As shown inFIG. 1, a substrate100such as a semiconductor substrate is provided. An alignment mark region101, a MTJ forming region102, and a non-MTJ region103are defined on the substrate100. A first dielectric layer110, such as an ultra-low dielectric constant (ultra-low k or ULK) layer, is deposited on the substrate100. At least one conductive pattern112, for example, copper damascene or dual damascene structures, may be disposed in the first dielectric layer110within the MTJ forming region102. For illustration purposes, three exemplary conductive patterns112are shown in the figures. Two of the three exemplary conductive patterns112are disposed within the MTJ forming region102.

According to one embodiment, a nitrogen-doped carbide (NDC) layer120may be deposited on the first dielectric layer110. According to one embodiment, the NDC layer120may have a thickness of about 200˜400 angstroms, but is not limited thereto. A second dielectric layer130such as a tetraethylorthosilicate (TEOS) oxide layer is then deposited over the NDC layer120, the first dielectric layer110and the at least one conductive pattern112. According to one embodiment, the second dielectric layer130may have a thickness of about 1000˜2000 angstroms, but is not limited thereto.

Subsequently, an alignment mark trench131and at least one via opening132are formed in the second dielectric layer130and the NDC layer120within the alignment mark region101and the MTJ forming region102, respectively. For illustration purposes, two exemplary via openings132are shown in the figures. Each of the two exemplary via openings132exposes a portion of each of the two exemplary conductive patterns112within the MTJ forming region102. The process of forming the alignment mark trench131and the via openings132in the second dielectric layer130and the NDC layer120may involve lithographic processes and etching processes known in the art.

As shown inFIG. 2, a polish stop layer141is then conformally deposited on the second dielectric layer130and within the via openings132and the alignment mark trench131. According to one embodiment, for example, the polish stop layer141may be a tantalum nitride (TaN) layer. According to one embodiment, the polish stop layer141may have a thickness of about 20-60 angstroms, but is not limited thereto. The polish stop layer141conformally covers the interior surfaces of the via openings132and the alignment mark trench131.

Subsequently, a barrier layer142is conformally deposited on the polish stop layer141. According to one embodiment, for example, the barrier layer may be a titanium nitride (TiN) layer. After the formation of the barrier layer142, a tungsten layer143is then conformally deposited on the barrier layer142. At this point, the via openings132may be completely filled with the polish stop layer141, the barrier layer142, and the tungsten layer143.

As shown inFIG. 3, subsequently, a chemical mechanical polishing (CMP) process is performed to polish the tungsten layer143and the barrier layer142until the polish stop layer141on the second dielectric layer is exposed, thereby forming a via plug152in each via opening132. A remaining portion143aof the tungsten layer143within the alignment mark trench101constitutes a recessed feature151. According to one embodiment, the CMP process has high selectivity for polishing the tungsten layer143and the barrier layer142relative to the polish stop layer141. For example, the CMP process may have a W:TiN:TaN selectivity ratio of 1:1:0.1. At this point, the top surface of the second dielectric layer130is still covered by the polish stop layer141.

As shown inFIG. 4, another CMP process may be performed to polish the polish stop layer141, the second dielectric layer130, the via plug152, and the tungsten layer143within the alignment mark trench101. After the CMP process, the remaining thickness of the second dielectric layer130may be about 1200 angstroms, for example. According to one embodiment, a bottom electrode layer161is then conformally deposited on the second dielectric layer130, the via plugs152and the recessed feature151.

According to one embodiment, for example, the bottom electrode layer161may be a tantalum nitride (TaN) layer. According to one embodiment, for example, the bottom electrode layer161may have a thickness ranging between 100 and 200 angstroms, for example, about 170 angstroms. In order to meet the roughness specification of the bottom electrode layer161, after depositing the bottom electrode layer161on the second dielectric layer130, the via plugs152and the recessed feature151, another CMP process may be performed to planarize the bottom electrode layer161. According to one embodiment, a thickness of the polish stop layer141is smaller than a thickness of the bottom electrode layer161.

As shown inFIG. 5, after the bottom electrode layer161is planarized, a magnetic tunnel junction (MTJ) stack layer S may be deposited on the bottom electrode layer161. According to one embodiment, for example, the MTJ stack layer S may comprise a seed layer162on the bottom electrode layer161, a magnetic reference (or “pinned”) layer163on the seed layer162, a tunnel barrier layer164on the magnetic reference layer163, a magnetic free layer165on the tunnel barrier layer164, and a capping layer166on the free layer165. A top electrode layer167is then deposited on the MTJ stack layer S. According to one embodiment, for example, the top electrode layer167comprises a tantalum (Ta) layer and may have a thickness of about 600 angstroms, but not limited thereto.

According to one embodiment, a silicon nitride hard mask layer171is deposited on the top electrode layer167and a silicon oxide hard mask layer172is deposited on the silicon nitride hard mask layer171. According to one embodiment, for example, the silicon nitride hard mask layer171may have a thickness of about 300 angstroms and the silicon oxide hard mask layer172may have a thickness of about 1400 angstroms, but not limited thereto. According to one embodiment, an organic dielectric layer (ODL)173and a bottom anti-reflective layer (BARC)174may be deposited on the silicon oxide hard mask layer172.

As shown inFIG. 6, a lithographic process and an etching process are carried out to pattern the top electrode layer167into top electrodes167t. For example, a photoresist pattern180is formed on the BARC174. An anisotropic dry etching process may be performed to etch the BARC174, the ODL173, the silicon oxide hard mask layer172, the silicon nitride hard mask layer171, and the top electrode layer167not covered by the photoresist pattern180. Subsequently, the remaining photoresist pattern180may be stripped off.

As shown inFIG. 7, an ion beam etching (IBE) process is then performed to pattern the magnetic tunnel junction (MTJ) stack layer S and the bottom electrode layer161into MTJ elements SS and bottom electrodes161b, thereby forming a magnetic memory element MS on each via plug152. After the IBE process is performed, a concave or curved top surface130tof the second dielectric layer130is formed around the magnetic memory element MS.

FIG. 8toFIG. 11are schematic diagrams showing an exemplary method for forming an integrated circuit device1a, for example, a magnetic tunnel junction (MTJ) device, according to another embodiment of the present invention, wherein like numeral numbers and labels designate like layers, regions or elements. As shown inFIG. 8, according to another embodiment, after the tungsten layer143is deposited as depicted inFIG. 2, a bottom electrode layer161is then conformally deposited on the second dielectric layer130, the via plugs152and the recessed feature151. According to one embodiment, for example, the bottom electrode layer161may be a TaN layer. According to one embodiment, for example, the bottom electrode layer161may have a thickness ranging between 100 and 200 angstroms, for example, about 170 angstroms. Subsequently, the bottom electrode layer161may be subjected to a CMP process to reduce the surface roughness of the bottom electrode layer161.

The following process steps are similar with that as depicted throughFIG. 5toFIG. 7. As shown inFIG. 9, after the bottom electrode layer161is planarized, an MTJ stack layer S may be deposited on the bottom electrode layer161. According to one embodiment, for example, the MTJ stack layer S may comprise a seed layer162on the bottom electrode layer161, a magnetic reference layer163on the seed layer162, a tunnel barrier layer164on the magnetic reference layer163, a magnetic free layer165on the tunnel barrier layer164, and a capping layer166on the free layer165. A top electrode layer167is then deposited on the MTJ stack layer S. According to one embodiment, for example, the top electrode layer167comprises a Ta layer and may have a thickness of about 600 angstroms, but not limited thereto.

According to one embodiment, a silicon nitride hard mask layer171is deposited on the top electrode layer167and a silicon oxide hard mask layer172is deposited on the silicon nitride hard mask layer171. According to one embodiment, for example, the silicon nitride hard mask layer171may have a thickness of about 300 angstroms and the silicon oxide hard mask layer172may have a thickness of about 1400 angstroms, but not limited thereto. According to one embodiment, ODL173and BARC174may be deposited on the silicon oxide hard mask layer172.

As shown inFIG. 10, a lithographic process and an etching process are carried out to pattern the top electrode layer167into top electrodes167t. For example, a photoresist pattern180is formed on the BARC174. An anisotropic dry etching process may be performed to etch the BARC174, the ODL173, the silicon oxide hard mask layer172, the silicon nitride hard mask layer171, and the top electrode layer167not covered by the photoresist pattern180. Subsequently, the remaining photoresist pattern180may be stripped off.

As shown inFIG. 11, an IBE process is then performed to pattern the MTJ stack layer S and the bottom electrode layer161into MTJ elements SS and bottom electrodes161b, thereby forming a magnetic memory element MS on each via plug152. After the IBE process is performed, a concave or curved top surface130tof the second dielectric layer130is formed around the magnetic memory element MS.

It is advantageous to use the present invention because the introduction of the polish stop layer141prior to the deposition of the barrier layer142, the integrity of the remaining portion143aof the tungsten layer143within the alignment mark trench101can be maintained, which increases the process window of the subsequent lithographic processes. The dishing during the tungsten CMP process is overcome and the within die (WID) loading is significantly improved.