Structure and method for detecting defects in BEOL processing

A test structure and method for monitoring process uniformity. Embodiments of the invention include test structures having a first metallization layer, a second metallization layer formed above the first metallization layer, a defect-generating region in a first metallization layer, a defect-dispersing region in the second metallization layer above the defect-generating region; and a defect-detecting region in the second metallization layer adjacent to the defect-dispersing region. The defect-generating region of the exemplary embodiment may have zero pattern density, uniform non-zero pattern density, or non-uniform non-zero pattern density. The defect-detecting region may include a test pattern such as, a comb-serpentine structure. Embodiments may include more than one defect-generating region, more than one defect-dispersing region, or more than one defect-detecting region. Embodiments may further include methods of manufacturing said test structures and methods of utilizing said test structures to monitor back end processes and determine if such processes are within specification limits.

BACKGROUND

The present invention generally relates to semiconductor devices, and specifically to a structure for detecting defects that may occur while forming back-end-of-the-line structures.

In the manufacture of semiconductor devices, process-induced physical defects in back-end manufacturing processes may cause electrical defects, such as shorts and opens that interfere with device performance and therefore decrease yield. One such process-induced defect is residual material which arises when excess material deposited in back-end structures is not completely removed by a planarization process such as chemical-mechanical planarization (CMP). For example, process-induced defects can occur due to a non-uniform pattern density which leads to a non-uniform polish.

As the dimensions of semiconductor devices have steadily decreased, it has become increasingly difficult to monitor the presence of defects on the devices directly. One approach for addressing these defects has been the fabrication of test structures during the relevant manufacturing process that may be easily examined, either electrically or optically, for defects. The test structures are manufactured at the same time and by the same manufacturing processes, so that by determining defect concentrations on the test structures, it may be possible to approximate the defect concentration of the actual semiconductor devices.

Typically, these test structures are located in the space between the chips (referred to as the kerf) and are not located in the chip area (i.e. not within the chip die) itself. However, defect concentration may not be uniform across a chip. Moreover, some test structures rely on their proximity to the defect source to be able to detect certain kinds of defects. Therefore, it may be advantageous to construct test structure consisting of a potential defect-generating region, a defect-dispersing region and a defect-sensing region that may be located throughout the chip area.

BRIEF SUMMARY

The present invention relates to a test structure that may be used to detect defects formed in back-end structures of semiconductor devices and methods of forming said test structures. According to at least one exemplary embodiment, a test structure may include a first metallization layer, a second metallization layer formed above the first metallization layer, a defect-generating region formed in a first metallization layer, a defect-dispersing region formed in the second metallization layer above the defect-generating region; and a defect-detecting region formed in the second metallization layer adjacent to the defect-dispersing region. The defect-generating region of the exemplary embodiment may have zero pattern density, uniform non-zero pattern density, or non-uniform non-zero pattern density.

Exemplary embodiments may further include methods of forming test structures including a defect-generating region, a defect-dispersing region and a defect-detecting region.

Exemplary embodiments may further include methods of using test structures including a defect-generating region, a defect-dispersing region and a defect-detecting region to determine the uniformity of back-end processes such as chemical-mechanical planarization.

DETAILED DESCRIPTION

Referring toFIGS. 1A-1G, one mechanism of generating process-induced defects is described, where non-uniform planarization of a first metallization layer causes defects in a second metallization layer formed above the first metallization layer. Referring toFIG. 1A, first metallization layer110may be formed by depositing a first dielectric layer111and a second dielectric layer112on the surface of preceding structure101(for example, a preceding metallization layer or microelectronic device), etching first dielectric layer111and second dielectric layer112to form recess regions (not shown), and depositing a liner113and metal fill114in the recess regions to form back-end features (such backend features may include, for example, via or line115, as depicted inFIG. 1B). The details of structure101have been omitted for illustrative simplicity.

Referring toFIG. 1B, the structure ofFIG. 1Amay then be planarized, for example by CMP, to remove the excess material of liner113and metal fill114. However, the planarization process sometimes results in non-uniform polishing, where some excess material of liner113and/or metal fill114, such as residue sheet120, remains on the top surface of second dielectric layer112. Due to the nature of the planarization polish, defects such as residue sheet120are more likely to occur in areas where first metallization layer110has a low pattern density. Pattern density of the first metallization layer110may be defined as the top-down area of back-end features such as via115in a given area of first metallization layer110divided by the overall top-down area of the given area. As will be seen inFIG. 1C-1G, the presence of residue sheet120may result in physical and/or electrical defects when a second metallization layer130is then formed on first metallization layer110.

Referring toFIG. 1C, second metallization layer130may be formed by first depositing a third dielectric layer131and a fourth dielectric layer132on the surface of the structure ofFIG. 1B. Referring toFIG. 1D, residue sheet120may be exposed when third dielectric layer131and a fourth dielectric layer132are etched to form recess regions140aand140bfor back-end features of the second metallization layer130. As depicted inFIG. 1E, residue sheet120can then be lifted from the surface of first metallization layer110and relocated across the surface of the structure by processes such as a wet clean. When residue sheet120is relocated to the area of recess region140a, defects may occur that may reduce device performance and yield. For example, as shown inFIG. 1F, residue sheet120may block recess region140awhile liner141and metal fill142are deposited on the structure ofFIG. 1E. As depicted inFIG. 1G, when excess material of liner141and/or metal fill142(FIG. 1F) is polished away, recess region140amay remain empty or partially filled. This empty recess region would represent an open in the metal structure of second metallization layer130. Residues such as residue sheet120may also cause defects through other mechanisms, such as causing shorts by bridging two unconnected back-end features of the same or different metallization layers. Accordingly, a test structure may be provided to detect process-induced physical defects such as residue metal, which may lead to electrical defects, such as shorts and opens. As used in this application, the term generic “defect” pertains to both electrical defects, such as shorts and opens, and/or to physical defects such as residual material. The physical defects may or may not lead to an electrical defect.

Exemplary embodiments of the present invention include a test structure including a first metallization layer and a second metallization layer capable of detecting the defects resulting from non-uniform planarization of the first metallization layer, as detailed inFIG. 1A-1G. Embodiments may include, as part of the first metallization layer, a defect-generating region, and, as part of the second metallization layer, a defect-dispersing region and a defect-detecting region. The defect-generating region is designed to accurately simulate the process conditions used to form actual back-end structures of the same metallization layer, such as those depicted inFIGS. 1A-1B. Defect-detecting region is a structure formed in the second metallization layer capable of detecting the defects formed by the defect-generating region in the first metallization layer. Defect-dispersing region is a structure formed in the second metallization capable of transporting the defects formed by the defect-generating region from the defect-generating region to the defect-detecting region. By incorporating a defect-dispersing region near the defect-detecting region as part of the test structure, the test structure is no longer required to be located near structures that independently generate physical defects, such as the kerf, in order to function reliably. Therefore, test structures according to embodiments of the present invention may be capable of being located wherever necessary to monitor relevant manufacturing processes throughout the chip area.

FIGS. 2A-2Idepict a process of manufacturing an exemplary embodiment of the test structure of the present invention, including a defect-generating region213(FIG. 2B), a defect-dispersing region230(FIG. 2F), and a defect-detecting region240(FIG. 2F).

Referring toFIG. 2A, a first metallization layer210, including a first dielectric layer211and a second dielectric layer212, is formed above a preceding structure201, such as a preceding metallization layer or microelectronic device. The details of preceding structure201have been omitted for illustrative simplicity.

FIGS. 2B-2Eillustrate a process by which defect-generating region213may be formed as part of first metallization layer210. Referring toFIG. 2B, defect-generating region213may be formed by etching first metallization layer210to form recess regions214a-214c. The top-down area of recess regions214a-214cdivided by the top-down area of defect-generating region213defines the pattern density of defect-generating region213.

Referring toFIG. 2C, recess regions214a-214c(FIG. 2B) of defect-generating region213are filled with metal by depositing metal layers214and215on the top surface of the structure ofFIG. 2B.

Referring toFIG. 2D, the structure ofFIG. 2Cis planarized, using, for example, CMP, to remove excess material from metal layers214(FIG. 2C) and 215(FIG. 2C) to form metal features216a-216cas part of defect-generating region213. If the planarization is not uniform, residue sheets217aand217bmay remain on the surface of first metallization layer210.

FIGS. 2E-2Iillustrate a process by which defect-dispersing region230and defect-detecting region240may be formed as part of a second metallization layer220. Referring toFIG. 2E, second metallization layer220, including a third dielectric layer221and a fourth dielectric layer222, may be formed above first metallization layer210.

Referring toFIG. 2F, second metallization layer220may be etched to form recess regions231and241a-241f. Recess regions241a-241fare formed as part of defect-detecting region240and, once filled with metal, may form the test pattern of defect-detecting region240(discussed later in more detail in conjunction withFIG. 3B). Recess region231may be formed as part of defect-dispersing region230, above defect-generating region213. While forming recess region231as part of defect-dispersing region230, physical defects, such as residue sheets217aand217b, resulting from uneven polishing of first metallization layer210inFIG. 2D, may be exposed.

Referring toFIG. 2G, residue sheets217aand217b, now exposed during the formation of defect-dispersing region230, may be dispersed across the surface of the structure by processes such as a wet clean, and land in a manner that blocks off some recess regions241a-241fin defect-detecting region240, such as recess regions241aand241cin the depicted embodiment.

Referring toFIG. 2H, metal layers251and252are then deposited on the top surface of the structure ofFIG. 2Gto fill recess regions231and241a-241f. Because recess regions241aand241care blocked by residue sheets217aand217b, recess regions241aand241cremain empty.

Referring toFIG. 2I, excess metal from layers251(FIG. 2H) and 252(FIG. 2H) is removed, for example, by CMP, to form metal features232and242a-242d. Subsequently, defect-detecting region240may be tested for defects. Because recess regions241aand241cremain empty, electrical tests will reveal resistances different than expected along paths passing through recess regions241aand241c, such that an unexpected resistance indicates the presence of one or more defects in defect-detecting region240. Further, optical inspection may also reveal defects present in defect-detecting region240caused by residue sheets resulting from uneven polishing defect-generating region213of first metallization layer210and exposed by the formation of defect-dispersing region230. Therefore, by determining the defect concentration of defect-detecting region240, it is possible to determine information regarding the uniformity of the planarization process in defect-generating region213.

By using the combination of a defect-generating region, a defect-dispersing region, and a defect-detecting region as discussed above in conjunction withFIGS. 2A-2I, a test structure according to one embodiment of the invention may be capable of being located throughout the chip area.

FIGS. 3A-3Eillustrate in more detail how the defect-generating region, the defect-dispersing region, and the defect-detecting region may be configured. As depicted inFIGS. 3A-3E, test structure300includes a defect-detecting region323(FIG. 3A) and a defect-dispersing region324(FIG. 3A) in a second metallization layer320(FIG. 3A), and a defect-generating region325(FIGS. 3C-3E) in a first metallization layer310formed below second metallization layer320(FIGS. 3C-3E).

Referring toFIG. 3A, according to one embodiment, defect-dispersing region324may consist of a metal line (not shown inFIG. 3A) formed in second metallization layer320surrounding defect-detecting region323. Preferably the metal line is wide, more preferably, about 1 micron. Defect-detecting region323may be adjacent to defect-dispersing region324, meaning there are no other features present in second metallization layer324between defect-detecting region323and defect-dispersing region324. Defect-detecting region323may or may not abut defect-dispersing region324. Defect-detecting region323may include a test pattern such as the comb-serpentine structure301depicted inFIG. 2B, where two interlocking comb structures302and303are separated by a serpentine structure304. The various lines of comb structures302and303and serpentine structure304may correspond to metal features242a-242dof defect-detecting region240depicted inFIG. 2I(as well as recess regions241aand241c, where defects interfere with the formation of the test pattern. By forming electrical connections to various contacts (not shown) along comb structures302and303and serpentine structure304, it is possible to determine the presence of defects by comparing the expected resistance between two contacts to the measured resistance. For example, a higher than expected resistance may indicate the presence of an open (such as recess regions241aand241c, depicted inFIG. 2I) along a continuous path. The presence of defects in defect-detecting region323may also be determined by other methods such as optically with a microscope, either manually or by an automated process. Other embodiments may include other test patterns, such as a via chain. Other embodiments of test structures with various defect-dispersing region324and defect-detecting region323configurations are described later in conjunction withFIGS. 6-9. The further description of test structure300inFIGS. 3C-3Emay also apply to the alternate embodiments explained later in conjunction withFIGS. 6-9.

FIGS. 3C-3Eare various cross sectional views ofFIG. 3Aalong line A-A′, which depict the defect-generating region325underneath defect-dispersing region324. As illustrated, according to some embodiments, defect-generating region325may have, for example, a zero pattern density (FIG. 3C), a uniform non-zero pattern density (FIG. 3D), or a non-uniform non-zero pattern density (FIG. 3E). The various pattern densities associated with a particular defect-generating region may reflect the pattern density of a region of the circuit monitored by the corresponding test structure. For example, a low pattern density region of a circuit being tested may include a test structure including a defect-generating region having a zero pattern density (FIG. 3C). Alternatively, higher pattern density regions of a circuit being tested may include a test structure including defect-generating regions having non-zero pattern density (e.g.,FIG. 3DorFIG. 3E).

Referring toFIG. 3C, an embodiment of the test structure at a cross-section along line A-A′ ofFIG. 3Ais shown. the exemplary test structure300may include the defect-dispersing region324and the defect-detecting region323(not shown in this cross-section) formed in a second metallization layer320(further including third dielectric layer321and fourth dielectric layer322, equivalent to second metallization layer220ofFIGS. 2A-2I). Second metallization layer320is above a first metallization layer310(further including first dielectric layer311and second dielectric layer312, equivalent to a first metallization layer210ofFIGS. 2A-2I). InFIG. 3C, first metallization layer310includes defect-generating region325, which has a zero pattern density (i.e., there are no metal features present) directly under the defect-dispersing region324. Because defect density may increase as pattern density decreases, the exemplary embodiment ofFIG. 2Cmay be used to determine the maximum defect density of a given planarization process.

Referring toFIG. 3D, another embodiment of the test structure at a cross-section along line A-A′ ofFIG. 3Ais shown. Here, the features are as described in conjunction withFIG. 3C, with the exception that first metallization layer310now includes defect generating region325with a uniform non-zero pattern density in the region under defect-dispersing region234, as indicated by the metal features340. The metal features340may be lines, vias, or any other feature known in the art and correspond to metal features216a-216cofFIG. 2D. The pattern density as depicted inFIG. 3Dis uniform, meaning the spacing between the metal features240are the same and the width of each metal feature240is the same. The pattern density may be minimum pitch or greater. Those skilled in the art will recognize that the numerical value of the minimum pitch will vary with technology node and device level. The width of the metal feature may be minimum CD (critical dimension) or larger. Those skilled in the art will recognize that the numerical value of the CD will vary with technology node and device level. By having a uniform pattern density underneath the defect-dispersing region, a test structure may be used to determine the expected defect concentration for that given pattern density. A field of test structures may then be employed, each with different but uniform pattern densities, to determine a correlation between pattern density and defect concentration.

Referring toFIG. 3E, another embodiment of the test structure at a cross-section along line A-A′ ofFIG. 3Ais shown. Here, the features are as described in conjunction withFIGS. 3C and 3D, with the exception that the first metallization layer310now includes defect generating region325with non-uniform non-zero pattern density in the region under defect-dispersing region324as indicated by the metal features340. As depicted inFIG. 3E, the spacing between each metal feature340is different while the width of each metal feature340is the same. Alternatively, pattern density may vary due to varying width of the metal features340while the spacing between metal features340stayed the same or varied (not shown). In addition, when viewing top down, there may be rows of metal features which may have the same or different metal widths and/or lengths, as well as different spacing between rows (not shown). A non-uniform pattern density underneath the defect-dispersing region may allow a single test structure to monitor a planarization process at different pattern densities by determining where on the defect-detecting region defects are found and correlating that location to the pattern density of the surrounding defect-dispersing region.

By using the test structures ofFIGS. 2A-3E, a planarization process, such as the process depicted inFIG. 1Dmay be monitored according to the operational flowchart ofFIG. 4. The monitoring process begins at step410by forming a first metallization layer having a defect-generating region with a predetermined pattern density, for example, as depicted inFIGS. 2A-2D. In step420, a second metallization layer containing a at least one defect-detecting region and at least one defect-dispersing region is formed on top of the first metallization layer, as depicted, for example, inFIGS. 2E-2I.

In step430, the defect-detecting region is then tested or inspected for defects, for example optically or by measuring the electrical resistance between different points of the defect-detecting region. In step440, the number of defects identified in step430is correlated to the uniformity of the planarization process for the predetermined pattern density. The graph ofFIG. 5Adepicts a possible relationship between the number of defects detected and the non-uniformity of the CMP process, where an increase in defect concentration correlates to an exponentially greater non-uniformity.

In step450, the number of defects is compared to a predetermined number of acceptable defects to determine if the planarization process is within specification limits. The graph ofFIG. 5Bdepicts the number of defects for a given pattern density of an acceptable and an unacceptable CMP process. By comparing the number of defects identified in step430to the acceptable defect levels ofFIG. 5B, it can be determined if the CMP process is within specification limits (i.e., defect levels of the test structure do not exceed a predetermined maximum value).

For example, it may be determined that, for a given CMP process, a test structure may produce an acceptable level of defects for each pattern density, graphically depicted as curve E ofFIG. 5B. For example, a test structure with a pattern density A may produce a maximum number of defects B while remaining within specification limits. If the number of defects determined in step430for a test structure with a pattern density A is less than B, then the CMP process is within specification limits. If, however, the number of defects is greater than B, then the CMP process is outside the pre-determined specification limits.

Referring toFIGS. 6-9, several other embodiments of the present invention including alternate configurations of the defect-dispersing region and/or defect-detecting region are depicted. In these alternate embodiments, the features are as described in conjunction withFIGS. 3A-3E, with the exception that the embodiments depicted inFIGS. 6-9include multiple defect-dispersing regions and/or defect-detecting regions.

Referring toFIG. 6, in other embodiments, the defect-dispersing region may include several smaller, non-contiguous regions. Further, the defect-dispersing region or regions may not fully surround the defect-detecting region. For example, the exemplary embodiment ofFIG. 3A-3Eincludes two defect-dispersing subregions620aand620bsurrounding a single defect-detecting region610. Each defect-dispersing region may have may be formed above the same defect-generating region, or separate defect-generating regions, which may or may not have similar pattern densities (not shown). Each defect-dispersing may be of the same approximate dimensions, as are defect-dispersing regions620aand620bof the depicted embodiments, or may be different dimensions with one defect-dispersing region being longer and/or wider than the other.

Referring toFIG. 7, the defect-detecting region may further include several discrete defect-detecting subregions710aand710b. By varying the pattern density underneath defect-dispersing region720, defect-detecting-subregions710aand710bmay independently test defect concentration resulting from different pattern densities. Further, defect-detecting-subregions710aand710bmay include the same or different test patterns, in the same or different orientations.

As depicted inFIGS. 8-9, some embodiments may include both multiple discrete defect-detecting regions (810a-810d,910a-910c) and multiple discrete defect-dispersing regions (820a-820d,910a-910c) to allow for greater flexibility in monitor defect frequency under varying conditions.