Period signal generation circuits

A period signal generation circuit includes a period signal generator configured to alternately charge and discharge a control node according to a level of the control node to generate a period signal, a discharge controller configured to discharge a first current having a constant value from the control node in response to a temperature signal and discharge a second current varying according to an internal temperature thereof from the control node in response to the temperature signal, and a tester configured to control a charging speed and a discharging speed of the control node.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2012-0056372, filed on May 25, 2012, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full.

BACKGROUND

In general, semiconductor memory devices may be categorized as either volatile or nonvolatile memory devices. While the volatile memory devices lose their stored data when power is interrupted, the nonvolatile memory devices retain their stored data even when power is interrupted. Volatile memory devices include dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. A unit cell of the SRAM devices may include a flip flop circuit (e.g., two cross-coupled inverters) and two switching elements. Thus, the SRAM cells may stably store their data as long as power is supplied. Meanwhile, a unit cell of the DRAM devices may include a cell transistor acing as a switching element and a cell capacitor acting as a data storage element. If the cell transistor is turned on, the cell capacitor will be charged through the cell transistor to store a data bit in the capacitor.

In the DRAM devices, leakage currents may occur through the cell transistors even though the cell transistors are turned off. Thus, the data (e.g., charges) stored in the capacitors may be lost as the time elapses. Thus, the cell capacitors need to be periodically recharged to retain their stored data.

The refresh operation may be categorized as either an auto-refresh operation or a self-refresh operation. The auto-refresh operation may be executed by refresh commands outputted from a memory controller, and the self-refresh operation may be executed by self-refresh signals which are internally generated in the DRAM devices.

The self-refresh operation may be periodically executed according to a refresh cycle time determined in the DRAM devices. The refresh cycle time may be determined by a data retention time corresponding to a maximum time that the cell capacitors can retain a minimum charge which is required to read a correct logic data. The data retention time may be influenced by leakage current characteristics of the cell transistors and the leakage current characteristics of the cell transistors may vary according to an internal temperature of the DRAM devices. Thus, the data retention time may be affected by the internal temperature of the DRAM devices.

As leakage currents increase with an increase of the internal temperature of the DRAM devices, the data retention time decreases with the increase of the internal temperature, and vice versa. Thus, a refresh circuit should be designed such that the refresh cycle time varies according to an internal temperature of the DRAM devices. That is, the refresh cycle time should be reduced to ensure successful operations of the DRAM device as the internal temperature of the DRAM device increases. On the other hand, the refresh cycle time should be increased to reduce the power consumption of the DRAM device as the internal temperature of the DRAM device decreases. Conventional DRAM devices include period signal generation circuits to control the refresh cycle time according to the internal temperature thereof.

FIG. 1is a block diagram illustrating a conventional period signal generation circuit.

As illustrated inFIG. 1, the conventional period signal generation circuit includes a first oscillator11, a second oscillator12, a temperature sensor13and a selection output unit14. The first oscillator11generates a first oscillating signal OSC1having a steady period (e.g., a constant cycle time) regardless of an internal temperature of the period signal generation circuit. The second oscillator12generates a second oscillating signal OSC2whose period varies according to the internal temperature. The temperature sensor13generates a temperature signal TS which transitions from one level to another level at a predetermined temperature. The selection output unit14receives the first and second oscillating signals OSC1and OSC2in response to the temperature signal TS and outputs a period signal PSRF. The selection output unit14outputs the first oscillating signal OSC1as the period signal PSRF when the temperature signal TS is generated at a temperature below the predetermined temperature. On the other hand, the selection output unit14outputs the second oscillating signal OSC2as the period signal PSRF when the temperature signal TS is generated at a temperature over the predetermined temperature.

As described above, the period signal PSRF outputted from the conventional period signal generation circuit uses the first oscillating signal OSC1at a temperature below the predetermined temperature, and the second oscillating signal OSC2at a temperature over the predetermined temperature. Thus, if a refresh cycle time is determined by the period signal PSRF, the refresh cycle time may be uniform or constant at a temperature below the predetermined temperature and the refresh cycle time may vary with a temperature when the temperature is higher than the predetermined temperature.

The selection output unit14may function as a comparator. That is, the selection output unit14may compare the period of the first oscillating signal OSC1with the period of the second oscillating signal OSC2in response to the temperature signal TS and may output any one of the first and second oscillating signals OSC1and OSC2as the period signal PSRF. Thus, the conventional period signal generation circuit requires two oscillators continuously generating oscillating signals with different characteristics. Moreover, when a difference between the periods of the first and second oscillating signals OSC1and OSC2is small, the selection output unit14acting as a comparator may malfunction and output a wrong oscillating signal.

SUMMARY

An embodiment of the present invention relates to a period signal generation circuit includes a control node, a period signal generator, a discharge controller, and a tester. The period signal generator is configured to generate a period signal by alternately charging and discharging the control node according to a potential level of the control node. The discharge controller is configured to discharge a first current having a substantially constant value from the control node in response to a temperature signal and discharge a second current varying according to an internal temperature thereof from the control node in response to the temperature signal. The tester is configured to control a charging speed or a discharging speed, or both, of the control node.

In an embodiment, the period signal generation circuit is part of a semiconductor memory device and the period signal is used to refresh memory cells in the semiconductor memory device. The semiconductor memory device is provided in a package and the internal temperature corresponds to a temperature within the package.

In an embodiment, a period signal generation circuit includes a period signal generator configured to generate a period signal by alternately charging and discharging a control node according to a level of the control node, a discharge controller configured to discharge a first current having a constant value from the control node in response to a temperature signal and discharge a second current varying according to an internal temperature thereof from the control node in response to the temperature signal, and a tester configured to control a charging speed and a discharging speed of the control node.

In another embodiment, a period signal generation circuit includes a period signal generator configured to generate a period signal by alternately charging and discharging a control node according to a level of the control node, a discharge controller configured to generate a first current and a second current discharged from the control node, and a tester configured to control a charging speed and a discharging speed of the control node. A total current of the first and second currents is substantially constant when an internal temperature of the discharge controller is below a predetermined temperature, and the total current of the first and second currents varies with the internal temperature when the internal temperature is equal to or over the predetermined temperature.

DETAILED DESCRIPTION

Embodiments of the present invention will be described hereinafter with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present invention.

FIG. 2illustrates a configuration of a period signal generation circuit according to an embodiment of the present invention.

As illustrated inFIG. 2, a period signal generation circuit according to the present embodiment may be configured to include a period signal generator2, a discharge controller3and a tester4.

The period signal generator2may include a first reference voltage generator21, a comparator22, a driver23and a buffer24. The first reference voltage generator21may generate a first reference voltage signal VREF1having a first reference voltage with a constant level. The comparator22may compare a signal (e.g., a voltage signal) induced at a control node ND_CTR with the first reference voltage signal VREF1to generate a comparison signal COM. The buffer24is configured to buffer the comparison signal COM to generate a period signal PSRF. The buffer may be a plurality of inverters and/or other components suitable for buffering and generating the period signal PSRF.

In an embodiment, the comparison signal COM is enabled initially to have a logic “low” state when the voltage of the control node ND_CTR has a lower level than the first reference voltage signal VREF1. Accordingly, a periodic signal PSRF is in a logic “low” state. The driver23receives the comparison signal COM having a logic “low” state to turn on the PMOS in the driver23for pulling up the voltage of the control node ND_CTR to a power supply voltage. As a result, the comparison signal COM is enabled to have a logic “high” state and the periodic signal PSRF having a logic “high” state is outputted. The PMOS of the driver23receives the logic “high” state and is turned off. The voltage of the control node ND_CTR is decreased until the voltage ND_CTR has a lower level than the first reference voltage signal VREF1, due to discharged currents from the control node ND_CTR as described below. Then, the comparison signal COM is enabled to have the logic “low” state once again. The periodic signals PSRF of “high” and “low” signals are generated in this manner.

The discharge controller3is configured to discharge the charges stored in the control node ND_CTR as needed. In an embodiment, the discharge controller3may include a temperature sensor31, a second reference voltage generator32, a first discharger33and a second discharger34. The temperature sensor31may generate an output signal which transitions from one level to another level at a predetermined temperature. For example, the temperature sensor31may generate a temperature signal TS which transitions from a logic “high” state to a logic “low” state when an internal temperature of the period signal generation circuit reaches the predetermined temperature (e.g., 45 degrees Celsius) from a low temperature below the predetermined temperature. In other words, the temperature signal TS may have a logic “high” state when an internal temperature of the refresh circuit is below a predetermined temperature (e.g., 45 degrees Celsius) and may have a logic “low” state when the internal temperature of the refresh circuit is equal to or greater than the predetermined temperature. The second reference voltage generator32may generate a second reference voltage signal VREF2having a variable voltage level that linearly varies according to a variation in the internal temperature or a constant voltage level regardless of a variation in the internal temperature. The first discharger33may discharge a first current I1, which is constant regardless of a variation in the internal temperature, from the control node ND_CTR in response to the second reference voltage signal VREF2. The second discharger34may discharge a second current I2, which is nonlinearly increased as the internal temperature increases, from the control node ND_CTR.

In an operation, one of the first and second dischargers33and34may selectively operate according to the temperature signal TS to discharge the charges stored in the control node ND_CTR. That is, the first discharger33may operate to generate the first current I1from the control node ND_CTR when the temperature signal TS has a logic “high” state (e.g., when the internal temperature is below 45 degrees Celsius), and the second discharger34may operate to generate the second current I2from the control node ND_CTR when the temperature signal TS has a logic “low” state (e.g., when the internal temperature is equal to or greater than 45 degrees Celsius).

The tester4is configured to control a charging speed and a discharging speed of the control node ND_CTR. In an embodiment, the tester4may include a test signal generator41and a time constant setting portion42. The test signal generator41may generate a first test signal TM1and a second test signal TM2in response to a test enable signal TM_EN. For example, if the test enable signal TM_EN is enabled to have a logic “high” state, the test signal generator41may generate the first and second test signals TM1and TM2which are sequentially counted. On the other hand, if the test enable signal TM_EN is disabled to have a logic “low” state, the test signal generator41may generate the first and second test signals TM1and TM2having a logic “high” state. Accordingly, the first and second test signals TM1and TM2are sequentially counted from a logic “low, low” state to “high, high” state. The time constant setting portion42may control a charging speed that the voltage of the control node ND_CTR is pulled up to have a power supply voltage according to a time constant which is set by the first and second test signals TM1and TM2. In addition, the time constant setting portion42may control a discharging speed that the voltage of the control node ND_CTR is pulled down by the discharge controller3. The time constant may correspond to an RC delay time which is determined by a resistance value (R) and a capacitance value (C) of the time constant setting portion42connected to the control node ND_CTR. That is, the time constant represents a time required for the voltage of the control node ND_CTR to reach about 63.2% of its maximum voltage value. The logic levels of the test enable signal TM_EN, the first test signal TM1and the second test signal TM2may not be limited to the above descriptions. That is, in some embodiments, the test enable signal TM_EN, the first test signal TM1and the second test signal TM2may be set to have diverse logic levels which are different from those described in the above embodiment.

Configurations of the second reference voltage generator32, the first discharger33and the second discharger34will be described more fully hereinafter with reference toFIGS. 3,4,5and6.

As illustrated inFIG. 3, the second reference voltage generator32may be configured to include a first current source321, a second current source322, a reference voltage driver323, a linearity controller324, and resistors R321and R322. The first current source321may operate as a constant current source in response to a voltage of a node ND321and a voltage of a node ND322, thereby supplying charges to the node ND321. In an embodiment, the first current source321includes two sets of two PMOS transistors connected in series. The node ND321and the node ND322are electrically connected to a gate of the upper PMOS transistors3211and3212and of the lower PMOS transistors3213and3214of each set, respectively.

The second current source322may operate as a constant current source in response to a voltage of a node ND323, thereby discharging the node ND322. In an embodiment, the second current source322includes two NMOS resistors3221and3222. The left NMOS transistor3221of the second current source322is a saturated MOS transistor whose gate is connected to the node ND323. The right NMOS transistor3222is electronically connected to a ground voltage through the resistor R322. The node ND321and the node ND322are electrically connected by the resistor R321.

The reference voltage driver323is configured to output the second reference voltage signal VREF2. In an embodiment, the reference voltage driver323includes two PMOS transistors connected in series. The linearity controller324may be electrically connected to an output node of the reference voltage driver323. The second reference voltage signal VREF2may be outputted from a node ND324between the reference voltage driver323and the linearity controller324, i.e., via the output node of the reference voltage driver323. In an embodiment, the linearity controller324includes a diode element3241composed of a saturated MOS transistor.

In an operation, the NMOS transistor3222in the second current source322connecting the node ND322and the resistor R322may operate in the weak inversion mode and a current flowing through the NMOS transistor3222may be increased in proportion to the internal temperature. Because a level of the current flowing through the NMOS transistor3222may be substantially the same as a level of a variable current entering into the output node ND324of the second reference voltage, the level of the variable current entering into the node ND324may be also increased in proportion to the internal temperature. The level of the current flowing through the reference voltage driver323via the node ND324may be adjusted by changing the resistor R322and the beta ratio of the NMOS transistors3221and3222in the second current source322.

On the other hand, a level of the variable current discharged from the output node ND324of the second reference voltage through the saturated MOS transistor3241may be increased in proportion to the internal temperature, because the threshold voltage of the saturated MOS transistor3241is decreased with an increase of the internal temperature. A slope of the variable current discharged from the output node ND324may be controlled by adjusting a size (e.g., a ratio of a channel width to a channel length) of the saturated MOS transistor3241.

As a result, when the levels of the variable currents discharged from and entering into the output node ND324are substantially equal to each other, a level of the second reference voltage signal VREF2may be maintained constant regardless of a variation in the internal temperature. When the level of the variable current discharged from the output node ND324is smaller than that of the variable current entering into the output node ND324, the second reference voltage signal VREF2outputted from the second reference voltage generator32is increased in proportion to the internal temperature, and vice versa. In this way, the second reference voltage signal VREF2outputted from the second reference voltage generator32may have a constant voltage level regardless of the variation in the internal temperature, or a variable voltage level that varies linearly with the internal temperature.

FIG. 4illustrates the first discharger33that is configured to generate the first current I1when the internal temperature is below a predetermined temperature (e.g., 45 degrees Celsius) according to an embodiment of the present invention. The first discharger33may be configured to include a switching portion331and an activating portion332. The switching portion331may include NMOS transistors N331, N332and N333which are turned on when the second reference voltage signal VREF2is applied to gates of the NMOS transistors N331, N332and N333. When the second reference voltage signal VREF2is applied to the gates of the NMOS transistors N331, N332and N333, charges stored in the control node ND_CTR may be discharged through the NMOS transistors N331, N332and N333to generate the first current I1flowing from the control node ND_CTR toward a node ND331. When the temperature signal TS has a logic “high” state representing that the internal temperature is below the predetermined temperature (e.g., 45 degrees Celsius), the activating portion332may electrically connect the node ND331to a ground voltage terminal to activate the operation of the switching portion331. As a result, the first discharger33may generate the first current I1which is from the charges discharged from the control node ND_CTR when the internal temperature is below a predetermined temperature.

FIG. 5illustrates the second discharger34that is configured to generate the second current I2when the internal temperature is equal to or greater than the predetermined temperature (e.g., 45 degrees Celsius) according to an embodiment of the present invention. The second discharger34may be configured to include a diode portion341and an activating portion342. The diode portion341may include saturated NMOS transistors N341, N342and N343which are serially connected to each other, thereby providing an electrical path connected to the control node ND_CTR. The charges stored in the control node ND_CTR may be discharged through the saturated NMOS transistors N341, N342and N343to generate the second current I2flowing from the control node ND_CTR toward a node ND341when the temperature signal TS has a logic “low” state representing that the internal temperature is equal to or greater than the predetermined temperature. The activating portion342may electrically connect the node ND341to a ground voltage terminal to activate the operation of the diode portion341when the temperature signal TS is “low” since it is converted to “high” by the inverter IV341. That is, the second discharger34may generate the second current I2based on the charges discharged from the control node ND_CTR when the internal temperature is equal to or greater than the predetermined temperature (e.g., 45 degrees Celsius).

Referring toFIG. 6, the first current I1discharged through the first discharger33and the second current I2discharged through the second discharger34may be plotted as a function of the internal temperature. That is, the first current I1may be constant or uniform regardless of a variation in the internal temperature. However, in some embodiments, the first current I1may linearly increase or decrease according to a variation in the internal temperature. The second current I2may nonlinearly vary with the internal temperature.

FIG. 7illustrates a configuration of the time constant setting portion42according to an embodiment of the present invention. The time constant setting portion42may be configured to set a time constant of the time constant setting portion42by controlling charging and discharging speeds of the control node ND_CTR. The time constant setting portion42may include a first capacitance setting portion421and a second capacitance setting portion422which are connected to the control node ND_CTR in parallel. The first capacitance setting portion421may include an NMOS transistor N421, a metal option unit M421and a capacitor C421which are serially connected to each other. The NMOS transistor N421may electrically connect the control node ND_CTR to a node ND421and may operate as a switching element which is turned on in response to the first test signal TM1. The metal option unit M421may electrically connect the node ND421to a node ND422, and the capacitor C421may electrically connect the node ND422to a ground voltage terminal. Similarly, the second capacitance setting portion422may also include an NMOS transistor N422, a metal option unit M422and a capacitor C422which are serially connected to each other. The NMOS transistor N422may electrically connect the control node ND_CTR to a node ND423and may operate as a switching element which is turned on in response to the second test signal TM2. The metal option unit M422may electrically connect the node ND423to a node ND424, and the capacitor C422may electrically connect the node ND424to a ground voltage terminal.

During a test mode, if the test enable signal TM_EN is “high,” the first and second test signals TM1and TM2are sequentially counted from a logic “low, low” state to “high, high” state. In response to a combination of the levels of the first and second test signals TM1and TM2, the NMOS transistors N421and N422whose gates are electrically connected to the first and second test signals TM1and TM2respectively are turned on or off. As a result, a time constant of the time constant setting portion42may be changed by electrically connecting or disconnecting the capacitors C421and C422to the control node ND_CTR. After the test mode, when both the first and second test signals TM1and TM2have a logic “high” state, electrical connections in the metal option units M421and M422may be adjusted to generate an appropriate combination of the levels of the first and second test signals TM1and TM2for setting a predetermined time constant of the time constant setting portion42.

The number of the test signals TM1and TM2are not limited to the example provided above. In other embodiments, a different number of the test signals may be used to adjust a time constant of the time constant setting portion42. In these cases, the number of capacitance setting portions in the time constant setting portion42may be different from that described in the above embodiment.

The operations of the period signal generation circuit for generating the period signal PSRF will be described in more detail hereinafter for a case where the internal temperature is below the predetermined temperature (e.g., 45 degrees Celsius) and a case where the internal temperature equal to or over the predetermined temperature (e.g., 45 degrees Celsius).

First, if the internal temperature is below the predetermined temperature (e.g., 45 degrees Celsius), the temperature signal TS may have a logic “high” state. The activating portion332of the first discharger33(seeFIG. 4) is enabled while the activating portion342of the second discharger34(seeFIG. 5) is not enabled. In such a case, the control node ND_CTR may be charged by the activation of the driver23(seeFIG. 2) if the voltage of the control node ND_CTR is lower than the first reference voltage (a voltage of the first reference voltage signal VREF1) and may be discharged by the activation of the first discharger33if the voltage of the control node ND_CTR is higher than the first reference voltage (a voltage of the first reference voltage signal VREF1). Since the first current I1flowing through the first discharger33is constant if the internal temperature is below the predetermined temperature, a level transition period of the comparison signal COM may be constant. Accordingly, the period (e.g., a cycle time) of the period signal PSRF may be constant when the internal temperature is below the predetermined temperature (e.g., 45 degrees Celsius), as illustrated inFIG. 8.

Next, if the internal temperature is equal to or greater than the predetermined temperature (e.g., 45 degrees Celsius), the temperature signal TS may have a logic “low” state. The activating portion342of the second discharger34(seeFIG. 5) is enabled while the activating portion332of the first discharger33(seeFIG. 4) is not enabled. In such a case, the control node ND_CTR may be charged by the activation of the driver23if the voltage of the control node ND_CTR is lower than the first reference voltage (a voltage of the first reference voltage signal VREF1) and may be discharged by the activation of the second discharger33if the voltage of the control node ND_CTR is higher than the first reference voltage (a voltage of the first reference voltage signal VREF1). The second current I2flowing through the second discharger34may be nonlinearly (e.g., exponentially) increased as the internal temperature increases over the predetermined temperature. Thus, a level transition period of the comparison signal COM may be nonlinearly reduced as the internal temperature increases over the predetermined temperature. Therefore, the period (e.g., a cycle time) of the period signal PSRF may be nonlinearly reduced as the internal temperature increases over the predetermined temperature (e.g., 45 degrees Celsius), as illustrated inFIG. 8.

The period signal PSRF generated in the period signal generation circuit described above may be applicable to self-refresh circuits or other circuits that periodically operate. The period signal generation circuit according to an embodiment of the present invention may be realized without circuits for generating a plurality of oscillation signals and for comparing the plurality of the oscillation signals. Thus, the period signal generation circuit may be simplified to increase the integration density thereof. In addition, the period signal generation circuit according to an embodiment of the present invention may operate without comparison of oscillating signals, thereby preventing malfunction resulted from comparison of the plurality of oscillation signals having similar periods. As a result, the period signal generation circuit according to the present embodiment may stably operate.

Moreover, the period signal generation circuit according to the present embodiment may execute a test operation by which a charging speed and/or a discharging speed of the control node ND_CTR can be controlled. Thus, the period (e.g., a cycle time) of the period signal may be readily adjusted without changing a circuit design. That is, as illustrated inFIG. 8, the period (e.g., a cycle time) of the period signal may be adjusted by increasing the period of the period signal by “X1” or decreasing the period of the period signal by “X2” according to a combination of the levels of the first and second test signals TM1and TM2during a test mode. After the test mode, the period (e.g., a cycle time) of the period signal may be adjusted by changing the connections of the metal option units M421and M422(seeFIG. 7).

FIG. 9illustrates a configuration of a period signal generation circuit according to another embodiment of the present invention.

As illustrated inFIG. 9, a period signal generation circuit according to the present embodiment may be configured to include a period signal generator5, a discharge controller6and a tester7.

The period signal generator5may include a first reference voltage generator51, a comparator52, a driver53and a buffer54. The first reference voltage generator51may generate a first reference voltage signal VREF1having a first reference voltage with a constant level. The comparator52may compare a signal (e.g., a voltage signal) induced at a control node ND_CTR with the first reference voltage signal VREF1to generate a comparison signal COM. The buffer54is configured to buffer the comparison signal COM to generate a period signal PSRF. The buffer54may be a plurality of inverters and/or other components suitable for buffering and generating the period signal PSRF. The period signal generator5may have the same configuration as the period signal generator2illustrated inFIG. 2. Thus, to avoid duplicate explanation, further detailed descriptions to the period signal generator5will be omitted in this embodiment.

The discharge controller7is configured to discharge the charges stored in the control node ND_CTR as needed. In an embodiment, the discharge controller6may include a second reference voltage generator61, a first discharger62and a second discharger63. The second reference voltage generator61may generate a second reference voltage signal VREF2having a variable voltage level that linearly increases or decreases according to variation of the internal temperature. The first discharger62may generate a first current I1, which is discharged from the control node ND_CTR, in response to the second reference voltage signal VREF2. The first current I1may linearly decrease as the internal temperature increases. The second discharger63may generate a second current I2, which is discharged from the control node ND_CTR. The second current I2may nonlinearly increase as the internal temperature increases.

In an operation, both the first and second dischargers62and63may simultaneously operate in response to an enable signal EN to generate the first and second currents I1and I2from the control node ND_CTR. The enable signal EN may be enabled to have a logic “high” state, thereby generating a period signal PSRF. When the internal temperature is below a predetermined temperature (e.g., 45 degrees Celsius), a sum of the first and second currents I1and I2may be substantially constant. This is because the second current I2shows an approximately linear behavior when the internal temperature is below the predetermined temperature. In this region, the second current I2is increased linearly when the internal temperature increases. As the first current I1is decreased linearly as the internal temperature increases in the same region, the sum of the first and second currents I1and I2may be constant if the linearly decreasing slope of the first current I1matches the correspondingly increasing slope of the second current I2. On the other hand, when the internal temperature is equal to or greater than the predetermined temperature (e.g., 45 degrees Celsius), the sum of the first and second currents I1and I2may be nonlinearly increased as the internal temperature increases. This is because the second current I2increases nonlinearly with a faster rate (e.g., exponentially) than the linearly decreasing rate of the first current I1so that the nonlinearly increasing behavior of the second current I2dominates the linearly decreasing behavior of the first current, when the internal temperature increases over the predetermined temperature. The second reference voltage generator61may have the same configuration as the second reference voltage generator32illustrated inFIG. 3. Thus, to avoid duplicate explanation, further detailed descriptions to the second reference voltage generator61will be omitted in this embodiment.

The tester7may include a test signal generator71and a time constant setting portion72. The test signal generator71may generate a first test signal TM1and a second test signal TM2in response to a test enable signal TM_EN. If the test enable signal TM_EN has an enabling state (e.g., a logic high) during a test mode, the test signal generator71may generate the first and second test signals TM1and TM2which are sequentially counted from a logic “low, low” state to “high, high” state. If the test enable signal TM_EN has non-enabling state (e.g., a logic low) after the test mode, the test signal generator71may generate the first and second test signals TM1and TM2having a logic “high” state. The time constant setting portion72may control a charging speed in such a way that the voltage of the control node ND_CTR is pulled up to have a power supply voltage according to a time constant which is set by a combination of the first and second test signals TM1and TM2. In addition, the time constant setting portion72may control a discharging speed in such a way that the voltage of the control node ND_CTR is pulled down by the discharge controller6. As will be understood by those skilled in art, the logic levels of the test enable signal TM_EN, the first test signal TM1and the second test signal TM2are not limited to the above examples. The time constant setting portion72may have the same configuration as the time constant setting portion42illustrated inFIG. 7. Thus, to avoid duplicate explanation, further detailed descriptions to the time constant setting portion72will be omitted in this embodiment.

Configurations of the first discharger62and the second discharger63will be described more fully hereinafter with reference toFIGS. 10,11and12.

FIG. 10illustrates the first discharger62that is configured to include a switching portion621and an activating portion622according to an embodiment of the present invention. The switching portion621may include NMOS transistors N621, N622and N623which are turned on when the second reference voltage signal VREF2is applied to gates of the NMOS transistors N621, N622and N623. When the second reference voltage signal VREF2is applied to the gates of the NMOS transistors N621, N622and N623, charges stored in the control node ND_CTR may be discharged through the NMOS transistors N621, N622and N623to generate the first current I1flowing from the control node ND_CTR towards a node ND621. In an embodiment, the first current I1may be linearly decreased when a level of the second reference voltage signal VREF2decreases with an increase of the internal temperature. When the enable signal EN has a logic “high” state, the activating portion622may electrically connect the node ND621to a ground voltage terminal to activate the operation of the switching portion621. As a result, the first discharger62may generate the first current I1from the charges discharged from the control node ND_CTR when the enable signal EN has the logic “high” state.

FIG. 11illustrates the second discharger63that is configured to generate the second current I2when the enable signal EN has the logic “high” state according to an embodiment of the present invention. The second discharger63may be configured to include a diode portion631and an activating portion632. The diode portion631may include saturated NMOS transistors N631, N632and N633which are serially connected to each other, thereby providing an electrical path connected to the control node ND_CTR. The charges stored in the control node ND_CTR may be discharged through the saturated NMOS transistors N631, N632and N633to generate the second current I2from the control node ND_CTR towards a node ND631. In an embodiment, the second current I2may be nonlinearly increased as the internal temperature increases because the threshold voltages of the saturated NMOS transistors N631, N632, and N633are decreased. When the enable signal EN enable signal EN has a logic “high” state, the activating portion632may electrically connect the node ND631to a ground voltage terminal to activate the operation of the diode portion631. As a result, the second discharger72may generate the second current I2from the charges discharged from the control node ND_CTR when the enable signal EN has the logic “high” state.

Referring toFIG. 12, the first current I1discharged through the first discharger33and the second current I2discharged through the second discharger34may be plotted as a function of the internal temperature. That is, the first current I1may linearly decrease as the internal temperature increases, and the second current I2may nonlinearly (e.g., exponentially) increase as the internal temperature increases. A sum (e.g., a total current Itot) of the first and second currents I1and12may be substantially constant when the internal temperature is below the predetermined temperature (e.g., 45 degrees Celsius). This is because the second current I2shows an approximately linear behavior when the internal temperature is below the predetermined temperature. In this region, the second current I2is increased linearly when the internal temperature increases. As the first current I1is decreased linearly as the internal temperature increases in the same region, the sum of the first and second currents I1and I2may be constant if the linearly decreasing slope of the first current I1matches the correspondingly increasing slope of the second current I2. On the other hand, the total current Itot(i.e., the sum of the first and second currents I1and I2) may be nonlinearly increased as the internal temperature increases over the predetermined temperature (e.g., 45 degrees Celsius). This is because the second current I2increases nonlinearly with a faster rate (e.g., exponentially) than the linearly decreasing rate of the first current I1so that the nonlinearly increasing behavior of the second current I2dominates the linearly decreasing behavior of the first current, when the internal temperature increases over the predetermined temperature.

The operations of the period signal generation circuit according to the present embodiment will be described in more detail hereinafter when the internal temperature is below the predetermined temperature (e.g., 45 degrees Celsius) and when the internal temperature is equal to or over the predetermined temperature (e.g., 45 degrees Celsius).

First, when the internal temperature is below the predetermined temperature (e.g., 45 degrees Celsius), the control node ND_CTR may be charged by the activation of the driver53(seeFIG. 9) if the voltage of the control node ND_CTR is lower than the first reference voltage (a voltage of the first reference voltage signal VREF1) and may be discharged by the activation of the first and second dischargers62and63(seeFIG. 9) if the voltage of the control node ND_CTR is higher than the first reference voltage (a voltage of the first reference voltage signal VREF1). When the internal temperature is below the predetermined temperature (e.g., 45 degrees Celsius), the total current Itot(i.e., the sum of the first and second currents I1and I2) discharged by the first and second dischargers62and63(seeFIG. 9) may be substantially constant. Thus, the period signal PSRF may be constant when the internal temperature is below the predetermined temperature.

Next, when the internal temperature is equal to or over the predetermined temperature (e.g., 45 degrees Celsius), the total current Itot(i.e., the sum of the first and second currents I1and I2) discharged by the first and second dischargers62and63(see FIG.9) may be nonlinearly increased as the internal temperature increases. Since a level transition period of the period signal PSRF is inversely proportional to the total current Itot, the period (e.g., a cycle time) of the period signal PSRF may be nonlinearly reduced as the internal temperature increases over the predetermined temperature (e.g., 45 degrees Celsius).

The period signal PSRF generated in the period signal generation circuit described above may be applicable to self-refresh circuits or other circuits that periodically operate. The period signal generation circuit according to an embodiment of the present invention may be implemented without any temperature sensors or circuits for generating a plurality of oscillation signals and for comparing the plurality of oscillation signals. Thus, the period signal generation circuit may be simplified to increase the integration density thereof. Further, the period signal generation circuit according to the embodiment of the present embodiment may operate without comparison of oscillating signals, thereby preventing a malfunction resulted from comparing the oscillating signals having similar periods. As a result, the period signal generation circuit according to the present embodiment may stably operate.

Moreover, the period signal generation circuit according to the embodiment of the present invention may execute a test operation that can control a charging speed and/or a discharging speed of the control node ND_CTR. Thus, the period (e.g., a cycle time) of the period signal may be more readily adjusted without changing a circuit design.