POWER DOWN CIRCUIT AND POWER DOWN METHOD

A power down circuit and a power down method are provided. The power down circuit includes a holding circuit and a comparator. The holding circuit is coupled to receive a first power signal. The holding circuit is configured to hold the first power signal to generate a second power signal. The comparator is coupled to the holding circuit. The comparator is configured to compare the first power signal and the second power signal to determine whether the first power signal is dropped to be lower than a first threshold voltage.

BACKGROUND

1. Technical Field

The disclosure generally relates to a circuit and a method, in particular, to a power down circuit and a power down method.

2. Description of Related Art

In various applications, a sensing circuit for detecting power down inside an electronic device is required because a power down sequence should be performed accordingly. More particularly, it usually takes a certain period of time for executing the power down sequence, so the power down circuit should be able to be work for the certain period of time under the power down environment to ensure that the power down sequence can be completed. Further, this power down sequence can also ensure the data and settings stored in the system to settle before another reboot. Therefore, a stable power down circuit is crucial in many applications.

SUMMARY

Accordingly, the disclosure is directed to a power circuit and a power method for providing a stable power down signal.

The power down circuit of the disclosure includes a holding circuit and a comparator. The holding circuit is coupled to receive a first power signal. The holding circuit is configured to hold the first power signal to generate a second power signal. The comparator is coupled to the holding circuit. The comparator is configured to compare the first power signal and the second power signal to determine whether the first power signal is dropped to be lower than a first threshold voltage.

The power down method of the disclosure includes holding a first power signal to generate a second power signal; and comparing the first power signal and the second power signal to generate a comparison result on determining whether the first power signal is dropped to be lower than a first threshold voltage.

DESCRIPTION OF THE EMBODIMENTS

FIG.1illustrates a block diagram of a power down circuit1according to some embodiments of the present disclosure. The power down circuit1may be applied in an electronic device that is driven by a first power signal VPP1. When the electronic device is powered down, electric power for driving the electronic device will be cut out causing the first power signal VPP1to drop. The power down circuit1is utilized for sensing whether the first power voltage VPP1is powered down, and to generate a power down signal VPD accordingly to inform necessary circuit components inside the electronic device such information. Therefore, when it is detected by the power down circuit1that the first power signal VPP1is lower than a first predetermined voltage, the power down signal VPD may be accordingly switched to an enabled voltage level and maintained for a predetermined time length, such that a power down sequence may be performed to the electronic device driven by the first power voltage VPP1according to the power down signal VPD. In some embodiments, the power down circuit1is configured to maintain the power down signal VPD greater than or equal to an enabled voltage level for a predetermined time length, ensuring that the power down sequence may completed within such period of time.

The power down circuit1includes a holding circuit10, a comparator11, and a buffer circuit12. The holding circuit10is coupled to receive the first power signal VPP1. The holding circuit10is configured to hold and store the first power signal VPP1and output the stored first power signal VPP1as a second power signal VPP2. In some embodiments, the holding circuit10is configured to hold the second power signal above a second threshold voltage for the predetermined time length after the first power down signal VPP1is dropped to be lower than a first threshold voltage. In other words, the holding circuit10is capable of storing the first power voltage VPP1for the predetermined time length to delay and slow down a falling speed of the outputted second power voltage VPP2.

The comparator11is coupled to the holding circuit11. The comparator11is configured to compare the first power voltage VPP1and the second power voltage VPP2to generate a comparison result Comp. Specifically, the first power voltage VPP1and the second power voltage VPP2are respectively provided to a negative input end and a positive input end of the comparator. Therefore, when the first power voltage VPP1is dropped to be lower than the first threshold voltage, the comparator11may generate the comparison result Comp at an enabled voltage level. More particularly, the comparator is driven by the second power voltage VPP2rather than the first power voltage VPP1, so when it is determined, by the comparator11, that the first power voltage VPP1is lower than the first threshold voltage, the second power voltage VPP2is provided at an output end of the comparator11as the comparison result Comp.

The buffer circuit12is coupled to the comparator11. The buffer circuit12is configured to buffer the comparison result Comp to generate power down signal VPD. The buffer circuit12is driven by the second power signal VPP2, so when the first power voltage VPP1is dropped to be lower than the first threshold voltage, the buffer circuit12may output the second power voltage VPP2at an output end of the buffer circuit12.

In operation, when the electronic device of which the power down circuit disposed is powered down and the electric power for driving the first power voltage VPP1is cut, the first power voltage VPP1is dropped rapidly. In order to ensure that there is enough time for the electronic device to execute the power down sequence, the power down circuit1stores energy from the first power voltage VPP1, so the falling speed of the second power voltage VPP2may be slowed down by the holding circuit10and the generated second power voltage VPP2has a gentler declination which is kept above the second threshold voltage for the predetermined time length. When the comparator11senses that the first power signal VPP1is less than the second power signal VPP2, the comparator11may switch the comparison result CR to the enabled voltage level by providing the second power signal VPP2at the output end. At last, when the buffer circuit12senses that the comparison result CR is increased to be greater than a threshold voltage of the buffer circuit12, the buffer circuit12controls the power down signal VPD to change from low to high by providing the second power signal VPP2as the power down signal VPD as well.

Overall, the power down circuit1stores charge and energy of the first power down signal VPP1, such that the power down circuit1may generate the second power signal VPP2which has a slower and gentler declination when the first power signal VPP1is dropped. Then, the comparator11uses the stored second power signal VPP2as a reference rather than a fixed reference voltage in the comparison with the first power voltage VPP1. That avoids the comparator11from generating the erroneous comparison result CR due to the fact that the fixed reference voltage might by affected by the power down. Further, since the comparator11and the buffer circuit12are driven by the second power signal VPP2which is still kept high for the predetermined time length when the first power signal VPP1is down, this provides a more stable power condition for the power down circuit1such that the generated down signal VPD has a stronger driving force when the first power signal VPP1is already down.

FIG.2illustrates a schematic of a power down circuit2according to some embodiments of the present disclosure. The power down circuit2includes a holding circuit20, a comparator21, and a buffer circuit22.

The holding circuit20is coupled to receive a first power signal VPP1, and configured to hold the first power signal VPP1to generate a second power signal VPP2. In such embodiment, the holding circuit20includes a resistor R0and a capacitor C0. The resistor R0has a first end coupled to receive the first power signal VPP1and a second end coupled to an output end of the holding circuit20. The capacitor C0has a first end coupled to the second end of the resistor R0, and a second end coupled to a reference ground voltage VSS. The second power signal VPP2is generated at a node between the resistor R0and the capacitor C0. More particularly, the holding circuit20stores the charge of the first power voltage VPP1on the capacitor C0through the resistor R0. The resistor R0ensures a lower discharge current from the capacitor C0when the first power voltage VPP1is dropped rapidly, thereby preserving the second power voltage VPP2on the top plate of the capacitor C0a slower declination.

The comparator21includes a transistor P0. In such embodiment, the transistor P0is a p-type transistor with a source being coupled to receive the second power signal VPP2, a drain being coupled to a reference ground voltage VSS through a resistor R2, and a gate coupled to the first power voltage VPP1through a resistor R1. The transistor P0is configured to compare voltages received at its gate and source. When the gate voltage is lower than the source by a threshold voltage of the transistor P0, the transistor P0is turned on (i.e., conductive) by the first and second power voltages VPP1, VPP2, so a current is flowing through the comparator21and provided at the drain of the transistor P0. Thus, the comparison result Comp is generated based on a voltage across the resistor R2resulted from the current flowing through.

The buffer circuit22includes transistors N1, N2, P1, P2. The transistors are coupling as two inverters coupled in series. The comparison result Comp is fed to the inverter chain to generate the power down signal VPD output buffering. Particularly, the buffer circuit22is driven by the second power signal VPP2, so when the comparison result Comp shows that the first power voltage VPP1is less than the first threshold voltage, the second power signal VPP2may pull up the power down signal VPD to be the same as the second power signal VPP2.

Overall, the power down circuit2provides implementations on how the holding circuit20, the comparator21, and the buffer circuit22are implemented. The power down circuit2hold the first power signal VPP1for generating the second power signal VPP2, and thus provides a more stable power source for the power down circuit2when the first power signal VPP1is already down.

FIG.3illustrates a schematic of a power down circuit3according to some embodiments of the present disclosure. The power down circuit3inFIG.3is similar to the power down circuit2inFIG.2except that the holding circuit20in the power down circuit2is replaced by a hold circuit30inFIG.3, so the same circuit components are labeled by the same symbols.

The holding circuit30includes an active resistor300and an active capacitor301. The active resistor300includes a plurality of transistors PS0-PSN coupled in series. All gates of the transistors PS0-PSN are coupled to receive the reference ground voltage VSS, so the transistors PS0-PSN are all biased the fixed reference ground voltage VSS to function equivalently as a resistor. On the other hand, the active capacitor301includes a transistor PC0coupled between the active resistor300and the reference ground voltage VSS. A gate of the transistor PC0is coupled to the active resistor300, and source and drain of the transistor PC0are coupled to the reference ground voltage VSS, so the transistor PC0is functioning as a capacitor between the active resistor300and the reference ground voltage VSS.

Overall, the power down circuit3provides implementations on how the holding circuit30is realized active devices. By using the active resistor and the active capacitor, the holding circuit30can be integrated with other semiconductor devices more easily since they are fabricated by the same manufacturing process.

FIG.4illustrates a flow chart of a power down method according to some embodiments of the present disclosure. The power down method may be implemented by anyone of the power down circuits1,2,3, inFIGS.1,2,3. The power down method includes steps S400, S401.

In step S400, a first power signal VPP1is held to generate a second power signal VPP2. Particularly, the first power signal VPP1is held by a holding circuit, such that the generated second power signal VPP2may be greater than a second threshold voltage when the first power voltage VPP1is dropped to be lower than a first threshold voltage. In other words, the second power signal is maintained at a voltage level higher than the second threshold voltage even if the first power voltage VPP1is dropped.

In step S401, the first power signal and the second power signal are compared to generate a comparison result based a determination that whether the first power signal is dropped to be lower than a first threshold voltage. Specifically, when the first power voltage VPP1is dropped, the comparison with the first power voltage VPP1using the second power voltage VPP2as the reference is performed, and such configuration ensures a stabler and reliable comparison by preventing the reference to be affected by the power down. As a result, the comparison result CR showing whether the first power voltage VPP1is down may be generated accordingly.

In operation, when an electronic device is powered down and the electric power for driving the first power voltage VPP1is cut, the first power voltage VPP1is dropped rapidly. In order to ensure that there is enough time for the electronic device to execute the power down sequence, the first power voltage VPP1may be stored by the holding circuit to generate the second power voltage VPP2, such that the falling speed of the second power voltage VPP2may be slowed down and the generated second power voltage VPP2may have a gentler declination slope. The first and second voltages VPP1, VPP2are compared by a comparator to generate the comparison result CR, and then the comparison result CR is fed into a buffer circuit to generate a power down signal. Both the comparator and the buffer circuit are driven by the second power voltage which is kept above the second threshold voltage for the predetermined time length, so the comparator and the power down circuit can be operated using a stronger power source even if the first power signal VPP1is down.

In summary, the power down circuit and the power down method of various embodiments of the present disclosure store the power signal. Further, the stored power signal is used as a reference to compare with the original power signal to determine whether the power is down. The stored power signal is held high for the predetermined time length which provides a stabler and stronger driving force for the power down circuit and the better time margin to perform the power down sequence.