CMOS current controlled delay element using cascoded complementary differential amplifiers with replicated bias clamp

A cascoded cmos differential delay element is described. The delay element provides a controlled delay useful in forming voltage controlled oscillators or other circuits. The delay element provides high gain enabling it to be useful in multistage delay element circuits. The circuit described includes cascoded complementary differential amplifiers and replicated bias clamps.

BACKGROUND OF THE INVENTION 
This invention relates to electronic circuits. In particular, the invention 
relates to integrated circuits which provide controllable delay functions, 
for example, in voltage controlled oscillators. 
In the design of many digital systems, time delay elements are required 
which provide a controlled and repeatable delay to "time" an event. 
"Timing" in this sense means that a specific time delay should occur prior 
to a next event. One such example is in the design of systems employing 
serial data communication. In such systems, voltage controlled delay 
elements can be used to help encode information or decode information 
supplied over the serial data channel. An example of such a system is 
described in commonly-assigned copending U.S. patent application Ser. No. 
08/254,326, filed Jun. 6, 1994, entitled "High Speed Serial Link for Fully 
Duplexed Data Communication," by Deog-Kyoon Jeong. 
Many forms of delayed locked loops (DLL) and phase locked loops (PLL) use a 
string of delay elements that are connected in a feedback arrangement to 
create an oscillator. The frequency of oscillation is a function of the 
individual delay times of the delay elements. In other words, as an event 
propagates through the chain of delay elements, each element delays the 
event by a controllable period, or a set time, before the next element is 
triggered, in turn creating further delay. 
There are several attributes desirable in a delay element. Sufficient gain 
is important because an input signal must be regenerated at an output of 
the delay element with enough fidelity to be useful for subsequent stages. 
Repeatability is also important, that is, for a given set of conditions 
such as process parameters, temperature, supply voltages, control 
voltages, etc., the delay should be the same. Another desirable feature of 
delay elements is wide range. Because various combinations of 
manufacturing variables are possible, a wider range of control allows 
compensation for a wider range of manufacturing variations. High speed is 
also important. As overall integrated circuit technology improves the 
speed of communications and computing, the required controlled delays, in 
turn, become shorter. For example, a phase locked loop integrated circuit 
may recover a clock signal from a data stream generated by a network link. 
The clock is at the bit rate of the incoming data and requires an internal 
oscillator in the phase lock loop circuit of the receiver to run at that 
frequency. As a result of continuing improvements in semiconductor 
technology, the frequency has increased from rates in the megaHertz range 
to the gigaHertz range. Thus, high speed can be an important attribute of 
a delay element. 
Another important attribute is rejection of exogenous noise. Noise has the 
deleterious effect of reducing almost all of the good attributes of a 
delay element. Too much noise can cause erroneous trigger events, thereby 
degrading gain, fidelity, and repeatability. Furthermore, delay is 
increased as power decreases. Nodal impedances increase, making circuits 
more susceptible to coupled noise. Therefore, signal-to-noise ratios are 
decreased as delays are increased. Noise is also affected by speed in 
another manner. In PLL or DLL circuits, noise can be considered as 
represented by an injected phase error. Thus, for a set amount of noise 
coupled to the controls of the delay element, delay elements with faster 
speed have the highest phase error percentage. In other words, the 
injected phase error is a higher percentage of the overall period of 
oscillation for circuits operating at higher speeds, rather than lower 
speeds. 
SUMMARY OF THE INVENTION 
An embodiment of this invention provides an improved delay element for a 
voltage controlled oscillator, or other application. The delay element 
provides high gain, a wide operating range, high speed, and noise 
rejection. An important aspect of the invention is the cascading of two 
complementary differential amplifiers. The use of the differential 
amplifiers helps minimize sensitivity to power supply noise which was 
reflected in the output signals of prior art delay elements. 
In one embodiment, a circuit according to this invention includes a high 
potential source, a low potential source, and a first differential 
amplifier connected to first and second input nodes to receive first and 
second input signals, and connected to first and second output nodes for 
supplying first and second output signals. A second differential amplifier 
is cascoded with the first differential amplifier, by being connected to 
the first and second input nodes to also receive the first and second 
input signals, and to the first and second output nodes for also supplying 
the first and second output signals. A first transistor having a control 
electrode coupled to receive a first bias signal, is coupled between the 
first differential amplifier and the high potential source; and a second 
transistor having a control electrode coupled to receive a second bias 
signal, is coupled between the second differential amplifier and the low 
potential source. In this manner the current through the first and second 
transistors controls the delay element.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS 
FIG. 1 illustrates a prior art voltage controlled oscillator. As shown in 
FIG. 1, the oscillator is made up of a series of delay elements 8, 10, 12, 
14 and 16 which are serially connected, and coupled between a high and a 
low potential source (not shown) to power each element. The output 
terminals 15, 18 of the last delay element 16 are cross-coupled to the 
input terminals of the first delay element 8. A start-up circuit (not 
shown) will place the first stage element 8 in one state or the other to 
begin the oscillations. In operation, the frequency of oscillation of the 
circuit shown in FIG. 1 is set by a control voltage input (not shown) to 
each of the stages. The important aspect of the operation of the circuit 
shown in FIG. 1 is that it oscillates. The output of each delay stage 8 is 
received by the subsequent delay stage 10, in turn causing the output of 
the subsequent stage to change and thereby change the input conditions for 
the next delay stage 12. This process is repeated, creating an oscillating 
signal within the circuit. By providing connections to the conductors 
between stages, or to the output terminals 15 or 18, the oscillating 
signal can be used to control other circuitry (not shown). 
FIG. 2 is a circuit schematic illustrating in more detail the internal 
structure of one of the prior art delay elements, for example, delay 
element 12. The two input signals to the circuit shown in FIG. 2 are 
designated IN, and received on input terminals 20 and 21. The two output 
signals, designated OUT, are supplied at nodes 23 and 24. As shown by FIG. 
1, nodes 20 and 21 are connected to the receive output signals from delay 
element 10, while the output signals on nodes 23 and 24 are connected to 
provide input signals to delay element 14. 
The circuit shown in FIG. 2 includes pmos transistors P1, P2, P3 and P4. 
Pmos transistors P1 and P2 are connected between a potential supply 
V.sub.DD and node 23, while pmos transistors P3 and P4 are connected 
between potential supply V.sub.DD and node 24. Nmos transistors N1 and N2 
are connected between nodes 23 and 24 and node 27, respectively. The input 
terminals 20 and 21 are connected to the control electrodes of transistors 
N1 and N2, respectively. Finally, a bias signal V.sub.BIAS controlling 
nmos transistor N3 provides a current sink for node 27. 
The circuit shown in FIG. 2 includes a dashed box 30 surrounding a portion 
of the circuit. In this portion of the circuit, transistor P3 is connected 
as a diode, and transistor P4 connected to another bias supply V.sub.BIAS. 
Connecting the transistors in this manner provides a passive load for the 
output node 24, and can be viewed as an approximation to providing a 
resistor R.sub.L, as indicated toward the right-hand side of FIG. 2. At 
low currents, the passive resistor R.sub.L becomes too large, and 
generates large amounts of thermal noise onto nodes 23 and 24. Also a 
large resistor R.sub.L makes nodes 23 and 24 more sensitive to coupled 
noise from the power supplies or other sources. Another problem with the 
circuit shown in FIG. 2 is that it is gain limited. 
For the circuit shown in FIG. 2, gain is expressed as: 
EQU Av=g.sub.mn R.sub.L (1) 
where: 
Av is the voltage gain V.sub.out /V.sub.in, and 
g.sub.mn is the transconductance of the nmos differential pair 
Because: 
EQU g.sub.mn =k(W/L)(V.sub.gs -V.sub.t) (2) 
where: 
k is a process constant 
W is the gate width 
L is the gate length 
V.sub.gs is the gate to source voltage, and 
V.sub.t is the threshold voltage (nmos) 
FIG. 3 is a circuit schematic illustrating a preferred embodiment of the 
invention. The circuit shown in FIG. 3 provides two cascoded complementary 
differential amplifiers. One differential amplifier consists of parallel 
connected pmos transistor P8 and pmos transistor P9. The other 
differential amplifier consists of parallel connected nmos transistor pair 
N8 and N9. A first input signal to the cascoded differential amplifiers is 
connected to the commonly coupled control gates of transistors P8 and N8. 
A complementary input signal to the cascoded differential amplifiers is 
connected to the commonly coupled control gates of transistors P9 and N9. 
As shown, the cascoded amplifiers are connected between an upper potential 
supply V.sub.DD and a lower potential supply GND. The potential supplies 
are coupled to the differential amplifiers through biasing transistors P10 
and N10. Pmos transistor P10 has its control electrode connected to 
receive a bias signal V.sub.BIAS -P, while nmos transistor has its control 
electrode connected to receive bias signal V.sub.BIAS -N. The output 
terminals for the circuit are terminals 40 and 41. As shown, one output 
terminal is coupled in common to transistors P8 and N8, and the other 
output terminal is coupled in common to transistors P9 and N9. The output 
terminals are designated OUT. 
Also shown in FIG. 3 are two optional clamp circuits. A first clamp circuit 
consisting of transistor P12 and transistor N12 is connected between nodes 
40 and 44, while a second clamp circuit consisting of transistors N14 and 
P14 is connected between nodes 41 and 45. These clamps are discussed in 
more detail below. 
The V.sub.BIAS signal shown in FIG. 3 is used to bias both the P channel 
transistor P10 and the N transistor N10 the same. The output voltage is 
set to be midway between the two bias voltages so that it occurs at the 
transition point where both transistors are in the saturated region. It is 
also desirable that the N and P channel devices shown in FIG. 3 have the 
same transconductance. To achieve this, the N channel devices N8 and N9 
will be roughly half as big as the P channel devices P8 and P9. 
For the circuit shown in FIG. 3, 
EQU Av=(g.sub.mp +g.sub.mn).multidot.(rop.parallel.ron) (3) 
where: 
g.sub.mp is the pmos differential pair transconductance 
g.sub.mn is the nmos differential pair transconductance 
rop is the small signal pmos gate length modulation resistance 
ron is the small signal nmos gate length modulation resistance 
.parallel. means in parallel 
The gain of the circuit shown in FIG. 3 will be much higher than the gain 
of the circuit shown in FIG. 2. Noise rejection from the power supply 
(V.sub.DD) is enhanced because the sources of both differential amplifiers 
in FIG. 3 are fed by current sinks, and are not connected directed to the 
power supplies. 
As mentioned above, in a preferred embodiment of the invention additional 
clamp circuits are added, as also shown in FIG. 3. Each clamp circuit 
consists of a pair of pmos and nmos transistors tied between an input 
terminal and an output terminal, where the pair has a common gate bias 
V.sub.COM. This bias is a replicated voltage for the transition voltage at 
which the input voltage equals the output voltage. In addition to 
adjusting the operating point, the clamp limits the excursions of the 
output nodes by shunting excess current during extreme differential input 
voltage situations. The clamps limit the output voltage excursions to a 
threshold voltage above and below C.sub.COM. If it is desired to make the 
delay element shown in FIG. 3 have a smaller swing and thus a shorter 
delay, the clamp is made smaller. Other clamp options are also possible, 
for example, a pair of Schottky diodes could be used to limit the 
excursions of the clamped nodes 40 and 44, and 41 and 45. Thus, the clamp 
helps make the delay of the stage more predictable and controllable. 
To the first order, the voltage swing at the output of the circuit shown in 
FIG. 3 is: 
EQU V.sub.oh =C.sub.COM +V.sub.tp (4) 
EQU V.sub.ol =C.sub.COM -V.sub.tn (5) 
where: 
C.sub.COM is the replicated bias level 
V.sub.tp is the pmos transistor threshold voltage 
V.sub.tn is the nmos transistor threshold voltage 
Assuming that: 
EQU V.sub.tn =V.sub.tp =V.sub.t =0.8 volts (6) 
then the output excursion will be 1.6 volts. Thus, the delay of the stage 
will be approximately: 
EQU t.sub.d =I.sub.O .multidot.(V.sub.t /C.sub.t) (7) 
where: 
I.sub.O is the matched tail currents of each differential pair 
V.sub.t is the threshold voltage 
C.sub.t is the nodal capacitance 
FIG. 4 is a circuit schematic illustrating the manner in which the common 
voltage C.sub.COM is generated. As shown in FIG. 4, a first pmos 
transistor P16, a second pmos transistor P17, a first nmos transistor N16 
and a second nmos transistor N17 are all serially connected between a 
higher potential V.sub.DD and a lower potential ground. The gates of P16 
and N16 are connected to receive the appropriate bias voltage V.sub.BIAS. 
These are the same bias voltages applied to the transistors P10 and N10 in 
FIG. 3, and function to make the transconductance of the transistors 
substantially equal. The gates of transistors N17 and P17 are tied 
together and to the node 48 between them. The potential of node 48 is used 
as the common voltage. This is the voltage supplied to the clamp circuits 
shown in FIG. 3. 
The foregoing has been a description of several embodiments of the 
invention, in particular, embodiments using and not using clamp circuits 
to provide a more reliable uniform delay element, for example in voltage 
control oscillators. These embodiment were presented for purposes of 
explanation. The scope of the invention is defined by the appended claims 
in light of their full scope of equivalents.