DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

A display apparatus includes a substrate including a display area and a non-display area, an organic insulating layer on the substrate, a first sub-pixel electrode on the organic insulating layer in the display area, a conductive bank layer including a first opening overlapping the first sub-pixel electrode, and a first conductive layer and a second conductive layer having different etch selectivities from each other, an insulating layer between the first sub-pixel electrode and the conductive bank layer, the insulating layer including an opening overlapping the first opening, a first intermediate layer on the first sub-pixel electrode, a first opposite electrode on the first intermediate layer, and a first inorganic barrier layer on the first opposite electrode. The conductive bank layer includes an inner exhaust opening around the first opening and overlapping the organic insulating layer, and the insulating layer includes an exhaust opening overlapping the inner exhaust opening.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2023-0009026 filed on Jan. 20, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

Display apparatuses are used to visually display data. The display apparatuses may provide images by using light-emitting diodes. The use of display apparatuses is becoming increasingly diverse, and as a result, various designs to improve the quality have been attempted.

It is to be understood that this background of the technology section is, in part, intended to provide useful background for understanding the technology. However, this background of the technology section may also include ideas, concepts, or recognitions that were not part of what was appreciated by those skilled in the pertinent art prior to a corresponding effective filing date of the subject matter disclosed herein.

2. Description of the Related Art

One or more embodiments relate to a display apparatus and a method of manufacturing the same.

SUMMARY

One or more embodiments include a display apparatus and a method of manufacturing the same.

According to one or more embodiments, a display apparatus may include a display area and a non-display area, an organic insulating layer disposed on a substrate, a first sub-pixel electrode disposed on the organic insulating layer in the display area, a conductive bank layer disposed on the first sub-pixel electrode and including a first opening overlapping the first sub-pixel electrode, the conductive bank layer further including a first conductive layer and a second conductive layer having different etch selectivities from each other, an insulating layer disposed between the first sub-pixel electrode and the conductive bank layer, the insulating layer including an opening overlapping the first opening, a first intermediate layer disposed on the first sub-pixel electrode through the first opening in the conductive bank layer and the opening in the insulating layer, a first opposite electrode disposed on the first intermediate layer, and a first inorganic barrier layer disposed on the first opposite electrode, wherein the conductive bank layer may further include an inner exhaust opening spaced apart from the first opening and overlapping the organic insulating layer, and the insulating layer further includes an exhaust opening overlapping the inner exhaust opening.

The second conductive layer of the conductive bank layer may be disposed on a top surface of the first conductive layer, and the second conductive layer may include a tip protruding from a point at which a side surface of the first conductive layer facing the inner exhaust opening meets a bottom surface of the second conductive layer.

The display apparatus may further include a second sub-pixel electrode adjacent to the first sub-pixel electrode, a second intermediate layer disposed on the second sub-pixel electrode through a second opening in the conductive bank layer overlapping the second sub-pixel electrode and an opening in the insulating layer overlapping the second opening, a second opposite electrode disposed on the second intermediate layer, and a second inorganic barrier layer disposed on the second opposite electrode, wherein the inner exhaust opening in the conductive bank layer and the exhaust opening in the insulating layer may be between the first sub-pixel electrode and the second sub-pixel electrode.

The inner exhaust opening in the conductive bank layer and the exhaust opening in the insulating layer may respectively overlap a first dummy intermediate layer including a same material as a material of the second intermediate layer and a first dummy opposite electrode including a same material as a material of the second opposite electrode.

The first dummy intermediate layer may be in direct contact with the organic insulating layer through the inner exhaust opening in the conductive bank layer and the exhaust opening in the insulating layer.

The organic insulating layer may include a groove overlapping the inner exhaust opening in the conductive bank layer and the exhaust opening in the insulating layer.

The display apparatus may further include a second dummy intermediate layer disposed on the tip and separated from the first dummy intermediate layer, and a second dummy opposite electrode disposed on the second dummy intermediate layer and separated from the first dummy opposite electrode.

The second dummy intermediate layer may include a same material as a material of the first dummy intermediate layer, and the second dummy opposite electrode may include a same material as a material of the first dummy opposite electrode.

The inner exhaust opening in the conductive bank layer and the exhaust opening in the insulating layer may overlap the second inorganic barrier layer, and the second inorganic barrier layer may be separated from the first inorganic barrier layer.

The display apparatus may further include a common voltage supply line arranged in the non-display area, wherein the conductive bank layer may extend to the non-display area and may be electrically connected to the common voltage supply line through a contact hole formed in the organic insulating layer.

The conductive bank layer may further include an outer exhaust opening overlapping the organic insulating layer in the non-display area.

The insulating layer may include an inorganic insulating material.

According to one or more embodiments, a display apparatus includes a display area and a non-display area, an organic insulating layer disposed on a substrate, a first sub-pixel electrode disposed on the organic insulating layer in the display area, a conductive bank layer including a first conductive layer and a second conductive layer having different etch selectivities from each other, a first opening overlapping the first sub-pixel electrode, and an inner exhaust opening spaced apart from the first opening, an insulating layer between the first sub-pixel electrode and the conductive bank layer, the insulating layer including an opening overlapping the first opening and an exhaust opening overlapping the inner exhaust opening, a first intermediate layer disposed on the first sub-pixel electrode through the first opening in the conductive bank layer and the opening in the insulating layer, a first opposite electrode disposed on the first intermediate layer, and a common voltage supply line arranged in the non-display area, wherein the conductive bank layer extends to the non-display area and is electrically connected to the common voltage supply line.

The conductive bank layer may further include an outer exhaust opening overlapping the organic insulating layer in the non-display area.

The outer exhaust opening may include a first outer exhaust opening, and a second outer exhaust opening disposed adjacent to a contact hole that electrically connects the conductive bank layer to the common voltage supply line, wherein the first outer exhaust opening is closer to the display area than the second outer exhaust opening.

The outer exhaust opening may include an overhang structure.

The second conductive layer of the conductive bank layer may be disposed on a top surface of the first conductive layer, and the second conductive layer may include a tip protruding toward the inner exhaust opening from a point at which a side surface of the first conductive layer facing the inner exhaust opening meets a bottom surface of the second conductive layer.

The display apparatus may further include a second sub-pixel electrode adjacent to the first sub-pixel electrode, a second intermediate layer disposed on the second sub-pixel electrode through a second opening in the conductive bank layer overlapping the second sub-pixel electrode and the opening in the insulating layer overlapping the second opening, and a second opposite electrode disposed on the second intermediate layer, wherein the inner exhaust opening in the conductive bank layer and the exhaust opening in the insulating layer may be between the first sub-pixel electrode and the second sub-pixel electrode.

The inner exhaust opening in the conductive bank layer and the exhaust opening in the insulating layer may respectively overlap a first dummy intermediate layer including a same material as a material of the second intermediate layer and a first dummy opposite electrode including a same material as a material of the second opposite electrode.

The first dummy intermediate layer may be in direct contact with the organic insulating layer through the inner exhaust opening in the conductive bank layer and the exhaust opening in the insulating layer.

The display apparatus may further include a second dummy intermediate layer disposed on the tip and including a same material as a material of the first dummy intermediate layer, and a second dummy opposite electrode disposed on the second dummy intermediate layer and including a same material as a material of the first dummy opposite electrode.

The display apparatus may further include a first inorganic barrier layer disposed on the first opposite electrode, and a second inorganic barrier layer separated from the first inorganic barrier layer and disposed on the second opposite electrode, wherein the inner exhaust opening in the conductive bank layer and the exhaust opening in the insulating layer may overlap the second inorganic barrier layer.

The organic insulating layer may include a groove overlapping the inner exhaust opening in the conductive bank layer and the exhaust opening in the insulating layer.

The insulating layer may include an inorganic insulating material.

The display apparatus may further include an insulating protection layer between the insulating layer and the conductive bank layer, wherein the insulating protection layer may include an opening overlapping the first opening, and the insulating protection layer may include an insulating material having an etch selectivity different from an etch selectivity of the insulating layer.

DETAILED DESCRIPTION OF THE EMBODIMENTS

When an element, such as a layer, is referred to as being “on,” “connected to,” or “electrically connected to” another element or layer, it may be directly on, connected to, or electrically connected to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly electrically connected to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Also, when an element is referred to as being “in contact” or “contacted” or the like to another element, the element may be in “electrical contact” or in “physical contact” with another element; or in “indirect contact” or in “direct contact” with another element. Further, the X-axis, the Y-axis, and the Z-axis may not be limited to three axes of a rectangular coordinate system, such as the x, y, and z axes, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to one another, or may represent different directions that may not be perpendicular to one another.

For the purposes of this disclosure, “at least one of A and B” may be construed as A only, B only, or any combination of A and B. Also, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. A description that a component is “configured to” perform a specified operation may be defined as a case where the component is constructed and arranged with structural features that can cause the component to perform the specified operation.

Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the disclosure, and should not be interpreted in an ideal or excessively formal sense unless clearly so defined herein. Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

FIG.1is a perspective view schematically illustrating a display apparatus1according to an embodiment. Referring ofFIG.1, the display apparatus1may include a display area DA and a non-display area NDA outside the display area DA. The display area DA may display an image through a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3, which may be arranged in the display area DA. The non-display area NDA may be an area that may be outside the display area DA and does not display an image, and may completely surround the display area DA. A driver or the like that provides electrical signals or power to the display area DA may be arranged in the non-display area NDA. A pad, which may be an area to which an electronic element or a printed circuit board may be electrically connected, may be arranged in the non-display area NDA.

In an embodiment,FIG.1illustrates that the display apparatus1has a polygonal shape (e.g., a rectangular shape) in which the length of the display area DA in the x direction may be less than the length of the display area DA in the y direction, but in an embodiment, the display apparatus1may have a polygonal shape (e.g., a rectangular shape) in which the length of the display area DA in the y direction may be less than the length of the display area DA in the x direction. AlthoughFIG.1illustrates that the display area DA has a substantially rectangular shape, the disclosure may not be limited thereto. In an embodiment, the display area DA may have various shapes, such as an N-gonal shape (where N may be a natural number greater than or equal to 3), a circular shape, or an elliptical shape.FIG.1illustrates that the display area DA has corners have a shape including vertices at which straight lines intersect with each other, but in an embodiment, the display area DA may have corners having a round polygonal shape.

The display apparatus1may be used in portable electronic apparatuses, such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigations, and ultra mobile PCs (UMPCs). Also, the display apparatus1may be used in various products, such as televisions, laptops, monitors, billboards, and Internet of things (IoT) devices. The display apparatus1may also be applied in electronic apparatuses, such as smart watches, watch phones, glasses-type displays, and head mounted displays (HMDs). The display apparatus1according to an embodiment may also be used in dashboards of automobiles, center information displays (CIDs) on the center fascia or dashboards of automobiles, room mirror displays replacing side mirrors of automobiles, and display screens on the rear sides of front seats to serve as entertainment devices for backseat passengers of automobiles.

FIG.2is a schematic diagram of an equivalent circuit diagram schematically illustrating a light-emitting diode LED corresponding to each of a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3of a display apparatus1ofFIG.1and a sub-pixel circuit PC electrically connected to the light-emitting diode LED according to an embodiment.

Referring toFIG.2, a light-emitting diode LED may be electrically connected to a sub-pixel circuit PC, and the sub-pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. A sub-pixel electrode (e.g., an anode) of the light-emitting diode LED may be electrically connected to the first transistor T1, and an opposite electrode (e.g., a cathode) of the light-emitting diode LED may be electrically connected to a common voltage supply line10and configured to receive a voltage corresponding to a common voltage ELVSS.

The second transistor T2may be configured to transmit a data signal Dm input through a data line DL to the first transistor T1in response to a scan signal Sgw input through a scan line GW. The storage capacitor Cst may be electrically connected to the second transistor T2and to a driving voltage line PL, and may be configured to store a voltage corresponding to a difference between a voltage received from the second transistor T2and a driving voltage ELVDD supplied to the driving voltage line PL.

The first transistor T1may be electrically connected to the driving voltage line PL and the storage capacitor Cst, and may be configured to control a driving current Idflowing from the driving voltage line PL to the light-emitting diode LED according to a voltage value stored in the storage capacitor Cst. The light-emitting diode LED may be configured to emit light having a certain luminance according to the driving current Id. AlthoughFIG.2illustrates that the sub-pixel circuit PC includes two transistors and one storage capacitor, the disclosure may not be limited thereto. A sub-pixel circuit PC of a display apparatus1according to an embodiment may instead include three or more transistors and may instead include two or more capacitors.

FIG.3is a schematic cross-sectional view of a display apparatus1according to an embodiment.FIG.3illustrates a structure corresponding to a first light-emitting diode LED1included in the display apparatus1.FIG.4is a schematic cross-sectional view schematically illustrating a stack structure of the first light-emitting diode LED1included in the display apparatus1, according to an embodiment.

Referring toFIG.3, a display area DA of the display apparatus1may include the first light-emitting diode LED1on a substrate100. The first light-emitting diode LED1may include a first sub-pixel electrode1210, a first intermediate layer1220on the first sub-pixel electrode1210, and a first opposite electrode1230on the first intermediate layer1220, and may be configured to emit first color light.

The substrate100may include glass or polymer resin. The substrate100may include a structure in which a base layer and an inorganic barrier layer each including polymer resin may be stacked on each other. Examples of the polymer resin may be polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate, cellulose triacetate (TAC), cellulose acetate propionate (CAP), or a combination thereof.

The first light-emitting diode LED1may be electrically connected to a first sub-pixel circuit PC1between the substrate100and the first light-emitting diode LED1. The first sub-pixel circuit PC1may include a transistor and a storage capacitor as described above with reference toFIG.2. In an embodiment,FIG.3illustrates a first transistor T1and a storage capacitor Cst of the first sub-pixel circuit PC1.

A buffer layer110may be between the substrate100and the first transistor T1. The buffer layer110may prevent impurities from penetrating into a semiconductor layer of a transistor. The buffer layer110may include an inorganic insulating material, such as silicon nitride, silicon oxynitride, silicon oxide, or a combination thereof, and may include a single layer or multiple layers including the inorganic insulating material described above.

The first transistor T1may include a first semiconductor layer120on the buffer layer110, and a first gate electrode140overlapping a channel region of the first semiconductor layer120. The first semiconductor layer120may include a silicon-based semiconductor material, for example, polysilicon. As another example, the first semiconductor layer120may include an oxide-based semiconductor layer. The first semiconductor layer120may include a channel region, and a first region and a second region respectively on both sides of the channel region. The first region and the second region may be regions that include or may be conductive with impurities at a higher concentration than the channel region. One of the first region and the second region may correspond to a source region, and the other thereof may correspond to a drain region.

A gate insulating layer130may be between the first semiconductor layer120and the first gate electrode140. The gate insulating layer130may include an inorganic insulating material, such as silicon nitride, silicon oxynitride, silicon oxide, or a combination thereof and may include a single layer or multiple layers including the inorganic insulating material described above.

A first interlayer insulating layer150may be disposed on the first gate electrode140. The first interlayer insulating layer150may include an inorganic insulating material, such as silicon nitride, silicon oxynitride, silicon oxide, or a combination thereof and may include a single layer or multiple layers including the inorganic insulating material described above.

A source electrode160and a drain electrode162may be electrically connected to the source region and the drain region of the first semiconductor layer120, respectively. A first organic insulating layer170may be disposed on the source electrode160and the drain electrode162. The first organic insulating layer170may include an organic insulating material. The source electrode160and the drain electrode162may each include aluminum (Al), copper (Cu), and/or titanium (Ti), and may each include a single layer or multiple layers including the material described above.

The storage capacitor Cst may include at least two capacitor electrodes overlapping each other. In an embodiment,FIG.3illustrates a first capacitor electrode on a same layer as the first semiconductor layer120, a second capacitor electrode on a same layer as the first gate electrode140, and a third capacitor electrode on a same layer as the source electrode160and/or the drain electrode162.

A connection metal CM may be disposed on the first organic insulating layer170, and the first sub-pixel electrode1210of the first light-emitting diode LED1may be electrically connected to the connection metal CM through a contact hole formed in a second organic insulating layer190. The connection metal CM may electrically connect the first sub-pixel circuit PC1to the first sub-pixel electrode1210of the first light-emitting diode LED1. The first organic insulating layer170may include an organic insulating material, such as acryl, benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), or a combination thereof. The connection metal CM may include aluminum (Al), copper (Cu), titanium (Ti), or a combination thereof and may include a single layer or multiple layers including the material described above.

In an embodiment, the first sub-pixel electrode1210of the first light-emitting diode LED1may be electrically connected (e.g., directly electrically connected) to the first sub-pixel circuit PC1. In an embodiment, multiple connection metals CM disposed on different layers from each other may be between the first sub-pixel electrode1210of the first light-emitting diode LED1and the first sub-pixel circuit PC1. The first sub-pixel electrode1210of the first light-emitting diode LED1and the first sub-pixel circuit PC1may be electrically connected to each other through the connection metals CM.

The first sub-pixel electrode1210of the first light-emitting diode LED1may be disposed on the second organic insulating layer190. The second organic insulating layer190may include an organic insulating material, such as acryl, BCB (Benzocyclobutene), HMDSO (Hexamethyldisiloxane), or a combination thereof.

The first sub-pixel electrode1210may include metal and/or conductive oxide. For example, the first sub-pixel electrode1210may include a reflection layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or any compound or combination thereof, and a layer disposed below and/or above the reflection layer and including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), or a combination thereof. In an embodiment, the first sub-pixel electrode1210may have a structure in which an ITO layer, an Ag layer, and an ITO layer may be sequentially stacked on each other in this stated order.

A conductive protection layer113may be disposed on the first sub-pixel electrode1210. The conductive protection layer113may overlap the outer portion of the first sub-pixel electrode1210and may include an opening overlapping the inner portion of the first sub-pixel electrode1210. Throughout the disclosure, the expression “outer portion (or peripheral portion) of A” indicates “a portion of A including an edge of A,” and the expression “inner portion of A” indicates “another portion of A” surrounded by the outer portion (or peripheral portion) of A.

The conductive protection layer113may prevent the first sub-pixel electrode1210from being damaged by materials used in various processes (e.g., an etching process or an ashing process) included in the process of manufacturing the display apparatus1. The conductive protection layer113may include at least one conductive oxide selected from ITO, IZO, indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), ZnO, aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO).

The conductive protection layer113may extend beyond the edge of the first sub-pixel electrode1210. The conductive protection layer113may be in contact with the top surface of the insulating layer disposed below the first sub-pixel electrode1210, for example, the top surface of the second organic insulating layer190, while covering the edge of the first sub-pixel electrode1210. In an embodiment, the conductive protection layer113may cover the edge of the first sub-pixel electrode1210, but may not extend to the top surface of the second organic insulating layer190below the first sub-pixel electrode1210. For example, the edge of the conductive protection layer113may be located on substantially the same line (e.g., a vertical line) as the edge of the first sub-pixel electrode1210.

A conductive bank layer300may be disposed on the first sub-pixel electrode1210with the insulating layer115therebetween. The conductive bank layer300may include a first opening300OP1passing through the conductive bank layer300in the thickness direction of the conductive bank layer300. The first opening300OP1of the conductive bank layer300may overlap the first sub-pixel electrode1210.

The insulating layer115may electrically insulate the conductive bank layer300from the first sub-pixel electrode1210. The insulating layer115may be disposed on the entire substrate100. For example, the insulating layer115may be in direct contact with the top surface of the second organic insulating layer190, on which the conductive protection layer113does not exist, while covering the overlapping structure of the first sub-pixel electrode1210and the conductive protection layer113. The insulating layer115may cover the side surfaces of the first sub-pixel electrode1210and the conductive protection layer113. The insulating layer115may include an inorganic insulating material. In a case where the insulating layer115includes an inorganic insulating material, a deterioration in quality of the light-emitting diode due to gas emitted from the insulating layer, which includes the organic insulating material, during the process of manufacturing the display apparatus1may be prevented or minimized, compared to a case where the insulating layer115includes an organic insulating material.

The insulating layer115may include an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof and may have a single-layer or multilayer structure including the inorganic insulating material described above. The insulating layer115may include an opening115OP1overlapping the first sub-pixel electrode1210and the first opening300OP1of the conductive bank layer300. A width W1of the opening115OP1of the insulating layer115may be less than a width of the first opening300OP1. For example, the width W1of the opening115OP1of the insulating layer115may be less than the width of the opening in the first conductive layer310and less than the width of the opening in the second conductive layer320.

An insulating protection layer400may be between the conductive bank layer300and the insulating layer115. The insulating protection layer400may prevent the first sub-pixel electrode1210from being damaged by gas or liquid materials used in various processes (e.g., an etching process or an ashing process) included in the process of manufacturing the display apparatus1.

The insulating protection layer400may include an amorphous inorganic insulating material, such as silicon oxide and/or silicon nitride. The insulating protection layer400may include a material having an etch selectivity different from etch selectivities of the conductive protection layer113, the insulating layer115, and the conductive bank layer300among the inorganic insulating materials described above. The insulating protection layer400may have a molecular structure different from that of the conductive protection layer113and may have a chemical resistance different from that of the conductive protection layer113. The insulating protection layer400may prevent the etchant from damaging the first sub-pixel electrode1210while passing through a crystal structure of the conductive protection layer113(e.g., a pinhole in the conductive protection layer113) in an etching process (e.g., wet etching) for forming an overhang structure of the conductive bank layer300in the process of manufacturing the display apparatus1.

The insulating protection layer400may include an opening400OP1overlapping with opening115OP1of insulating layer115, the first opening300OP1of the conductive bank layer300, and/or the first sub-pixel electrode1210. A width W2of the opening400OP1of the insulating protection layer400may be greater than the width W1of the opening115OP1of the insulating layer115.

The first intermediate layer1220may be in direct contact with the first sub-pixel electrode1210through the opening115OP1of the insulating layer115. For example, the inner portion of the first intermediate layer1220may overlap and contact the first sub-pixel electrode1210, and the outer portion of the first intermediate layer1220may extend above the insulating layer115and overlap and contact the insulating layer115. The first intermediate layer1220between the first opposite electrode1230and the first sub-pixel electrode1210may emit first color light. The width W1of the opening115OP1of the insulating layer115may correspond to the width of an emission area of the first light-emitting diode LED1.

The first intermediate layer1220may include a first emission layer1222, as illustrated inFIG.4. The first intermediate layer1220may also include a common layer between the first sub-pixel electrode1210and the first emission layer1222and/or between the first emission layer1222and the first opposite electrode1230. Hereinafter, the common layer between the first sub-pixel electrode1210and the first emission layer1222may be referred to as a first common layer1221, and the common layer between the first emission layer1222and the first opposite electrode1230may be referred to as a second common layer1223.

The first emission layer1222may include a high molecular weight organic material or a low molecular weight organic material that emits certain color light (red light, green light, or blue light). In an embodiment, the first emission layer1222may include an inorganic material or quantum dots. The first common layer1221may include a hole transport layer (HTL) and/or a hole injection layer (HIL). The second common layer1223may include an electron transport layer (ETL) and/or an electron injection layer (EIL). The first common layer1221and the second common layer1223may each include an organic material. The first opposite electrode1230may include a conductive material having a low work function. For example, the first opposite electrode1230may include a (semi)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), any alloy thereof, or a combination thereof. As another example, the first opposite electrode1230may further include a layer including ITO, IZO, ZnO, In2O3, or a combination thereof on the (semi)transparent layer including the material described above.

As illustrated inFIG.3, the inner portion of the first opposite electrode1230may overlap the first intermediate layer1220and the first sub-pixel electrode1210, and the outer portion of the first opposite electrode1230may extend above the insulating layer115and overlap the insulating layer115. The width of the first opposite electrode1230may be greater than the width of the first intermediate layer1220. In other words, the outer portion of the first opposite electrode1230may extend beyond the edge of the first intermediate layer1220and may be in direct contact with the conductive bank layer300. For example, as illustrated inFIG.3, the outer portion of the first opposite electrode1230may be in direct contact with a portion of the side surface (e.g., a lower portion of the side surface) of the first conductive layer310of the conductive bank layer300. The first opposite electrode1230may be protected by a first capping layer1240disposed thereon. The first capping layer1240may include an organic material or an inorganic material. The outer portion of the first capping layer1240may extend beyond the edge of the first opposite electrode1230. The outer portion of the first capping layer1240may be in direct contact with the conductive bank layer300while covering the edge of the first opposite electrode1230.

The conductive bank layer300may include conductive layers having different etch selectivities from each other. In an embodiment, the conductive bank layer300may include a first conductive layer310, and a second conductive layer320on the first conductive layer310. The first conductive layer310and the second conductive layer320may include metals having different etch selectivities from each other. In an embodiment, the first conductive layer310may include aluminum (Al), and the second conductive layer320may include titanium (Ti). AlthoughFIG.3illustrates that the conductive bank layer300includes two conductive layers, the disclosure may not be limited thereto. In an embodiment, the conductive bank layer300may further include a third conductive layer below the first conductive layer310, in addition to the first conductive layer310and the second conductive layer320on the first conductive layer310.

The thickness of the first conductive layer310may be greater than the thickness of the second conductive layer320. In an embodiment, the thickness of the first conductive layer310may be greater than about 5 times and less than about 10 times the thickness of the second conductive layer320. In some embodiments, the thickness of the first conductive layer310may be greater than or equal to about six times, greater than or equal to about seven times, or greater than or equal to about eight times the thickness of the second conductive layer320. In an embodiment, the thickness of the first conductive layer310may be about 0.5 μm to about 1 μm, and the thickness of the second conductive layer320may be about 0.03 μm to about 0.15 μm.

The conductive bank layer300may include an overhang structure. For example, the second conductive layer320of the conductive bank layer300may form an overhanging structure by protruding more than the first conductive layer310toward the first opening300OP1of the conductive bank layer300. In other words, the second conductive layer320may include a tip T protruding in one direction (e.g., a lateral direction or a direction facing the first opening300OP1) from a point CP at which the bottom surface of the second conductive layer320meets the side surface of the first conductive layer310.

The first intermediate layer1220may be formed by a deposition process. In case that the conductive bank layer300has an overhang structure, a material for forming the first intermediate layer1220may be deposited on the first sub-pixel electrode1210as illustrated inFIG.3, and may also be deposited on the top surface of the conductive bank layer300as illustrated inFIG.3. The material deposited on the first sub-pixel electrode1210may correspond to the first intermediate layer1220, and the material deposited on the top surface of the conductive bank layer300may correspond to a first dummy intermediate layer1220D.

Like the first intermediate layer1220, the first opposite electrode1230and the first capping layer1240may each be formed by deposition. A first dummy opposite electrode1230D and a first dummy capping layer1240D may be disposed on the top surface of the conductive bank layer300. The first dummy opposite electrode1230D may be disposed on the first dummy intermediate layer1220D, and the first dummy capping layer1240D may be disposed on the first dummy opposite electrode1230D.

A first inorganic barrier layer1510may overlap and cover the first light-emitting diode LED1. The first inorganic barrier layer1510may include at least one inorganic insulating material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and may be formed by chemical vapor deposition. The first inorganic barrier layer1510has relatively better step coverage than the first intermediate layer1220and the first opposite electrode1230, and thus, may not be separated or disconnected by the overhang structure of the conductive bank layer300. The first inorganic barrier layer1510may continuously overlap and cover the top surface and the side surface of the conductive bank layer300and the first light-emitting diode LED1.

Hereinafter, for convenience of description, first to fifth portions of the first inorganic barrier layer1510will be described. For example, the first inorganic barrier layer1510may include a first portion1510aoverlapping the first light-emitting diode LED1, a second portion1510bon the top surface of the conductive bank layer300, for example, the top surface of the tip T, a third portion1510con the bottom surface of the tip T of the conductive bank layer300, a fourth portion1510dbetween the second portion1510band the third portion1510c,and a fifth portion1510ebetween the first portion1510aand the third portion1510c.The fifth portion1510emay overlap the side surface of the first conductive layer310, and may overlap the outer portion of the first intermediate layer1220, the outer portion of the first opposite electrode1230, and the outer portion of the first capping layer1240. The first portion1510aand the fifth portion1510emay be integral with each other, the fifth portion1510eand the third portion1510cmay be integral with each other, the third portion1510cand the fourth portion1510dmay be integral with each other, and the fourth portion1510dand the second portion1510bmay be integral with each other.

In a schematic cross-sectional view, the fourth portion1510dof the first inorganic barrier layer1510may have a shape protruding in the protruding direction of the tip T (e.g., a lateral direction or a direction perpendicular to the z direction). For example, as illustrated inFIG.3, the fourth portion1510dof the first inorganic barrier layer1510may include a surface round in the protruding direction of the tip T (e.g., a lateral direction or a direction perpendicular to the z direction). In other words, in a schematic cross-sectional view, the fourth portions1510dof the first inorganic barrier layer1510may be located on both sides of an imaginary vertical line passing through the center of the first light-emitting diode LED1, and the separation area between the fourth portions1510dmay overlap the emission area of the first light-emitting diode LED1. The width W3of the separation area may be greater than the width of the emission area of the first light-emitting diode LED1, for example, the width W1of the opening115OP1of the insulating layer115. InFIG.3, the separation area between the fourth portions1510dmay correspond to the width of the area surrounded by the fourth portion1510din a plan view (in case that projected in a direction perpendicular to the top surface of the substrate100). In other words, in case that viewed in a plan view (in case that viewed from a direction perpendicular to the top surface of the substrate100), the fourth portion1510dmay have a closed loop shape that surrounds the emission area.

FIG.5is a plan view illustrating a portion of a display apparatus1according to an embodiment. A conductive bank layer300may include openings corresponding to first to third sub-pixels P1, P2and P3arranged in a display area DA, for example, first to third openings300OP1,300OP2, and300OP3. The first to third openings300OP1,300OP2, and300OP3may be spaced apart from each other, and the conductive bank layer300may have a net structure in a plan view. Referring toFIG.5, first to third light-emitting diodes LED1, LED2, and LED3may be respectively arranged in the first to third openings300OP1,300OP2, and300OP3of the conductive bank layer300. The first to third light-emitting diodes LED1, LED2, and LED3may respectively correspond to the first to third sub-pixels P1, P2and P3. The first to third light-emitting diodes LED1, LED2, and LED3may be arranged to have a diamond PenTile™ structure as illustrated inFIG.5, but the disclosure may not be limited thereto. The first to third light-emitting diodes LED1, LED2, and LED3may be variously arranged to have a stripe or mosaic structure.

In the conductive bank layer300, an opening300OG (hereinafter referred to as an inner exhaust opening) may be between two light-emitting diodes selected from the first to third light-emitting diodes LED1, LED2, and LED3. As illustrated inFIG.5, the inner exhaust opening300OG may be between the third light-emitting diodes LED3adjacent to each other and between the first light-emitting diode LED1and the second light-emitting diode LED2adjacent to each other. In other words, the inner exhaust opening300OG may be between the four light-emitting diodes adjacent to each other (for example, the two third light-emitting diodes LED3adjacent to each other, the first light-emitting diode LED1, and the second light-emitting diode LED2). As illustrated inFIG.5, the inner exhaust opening300OG may be between four light-emitting diodes selected from multiple light-emitting diodes, but may not be between the other four light-emitting diodes. However, the disclosure may not be limited thereto. In an embodiment, one inner exhaust opening300OG may be arranged for every four light-emitting diodes selected from the light-emitting diodes. In an embodiment, one inner exhaust opening300OG may instead be arranged for every N adjacent light-emitting diodes selected from multiple light-emitting diodes (where N may be a natural number of 2, 3, or 5 or more).

FIGS.6and7are respectively schematic cross-sectional views of a portion of the display apparatus1taken along line VI-VI′ ofFIG.5, according to an embodiment. Referring toFIG.6, the first light-emitting diode LED1and the second light-emitting diode LED2on a substrate100may be adjacent to each other in the display area DA. The first light-emitting diode LED1and the second light-emitting diode LED2may be electrically connected to a first sub-pixel circuit PC1and a second sub-pixel circuit PC2, respectively. The first sub-pixel circuit PC1may be the same as described above with reference toFIG.3, and the second sub-pixel circuit PC2may have substantially the same structure as the first sub-pixel circuit PC1.

A structure of the first light-emitting diode LED1, a structure in which a conductive bank layer300has a tip T around a first opening300OP1, structures of a conductive protection layer113, an insulating layer115, an insulating protection layer400, and a first inorganic barrier layer1510on the first light-emitting diode LED1may be the same as described above with reference toFIG.3. The second light-emitting diode LED2may include substantially the same structure as the first light-emitting diode LED1described above with reference toFIG.3, but may emit color light different from that of the first light-emitting diode LED1. The second light-emitting diode LED2may include a second sub-pixel electrode2210, a second intermediate layer2220on the second sub-pixel electrode2210, and a second opposite electrode2230on the second intermediate layer2220, and may be configured to emit second color light different from the first color light.

The second intermediate layer2220may be in direct contact with the second sub-pixel electrode2210through the opening in the insulating layer115. For example, the inner portion of the second intermediate layer2220may overlap and contact the second sub-pixel electrode2210through the opening in the insulating layer115, and the outer portion of the second intermediate layer2220may extend above the insulating layer115and overlap and contact the insulating layer115. Similar to the first intermediate layer1220, the second intermediate layer2220may include a second emission layer, a first common layer, and a second common layer.

As illustrated inFIG.6, the inner portion of the second opposite electrode2230may overlap the second intermediate layer2220and the second sub-pixel electrode2210, and the outer portion of the second opposite electrode2230may extend above the insulating layer115and overlap the insulating layer115. The width of the second opposite electrode2230may be greater than the width of the second intermediate layer2220. In other words, the outer portion of the second opposite electrode2230may extend beyond the edge of the second intermediate layer2220and may be in direct contact with the conductive bank layer300. As illustrated inFIG.6, the outer portion of the second opposite electrode2230may be in direct contact with a portion of the side surface (e.g., a lower portion of the side surface) of the first conductive layer310of the conductive bank layer300. The second opposite electrode2230may be protected by a second capping layer2240disposed thereon. The second capping layer2240may include an organic material or an inorganic material. The outer portion of the second capping layer2240may be in direct contact with the conductive bank layer300while covering the edge of the second opposite electrode2230.

The conductive bank layer300may include an overhang structure around the second opening300OP2. For example, the second conductive layer320of the conductive bank layer300may form an overhanging structure by protruding more than the first conductive layer310toward the second opening300OP2of the conductive bank layer300. In other words, the second conductive layer320may include a tip T protruding in one direction (e.g., a lateral direction or a direction facing the second opening300OP2).

The second intermediate layer2220may be formed by a deposition process. In case that the conductive bank layer300has an overhang structure, a material for forming the second intermediate layer2220may be deposited on the second sub-pixel electrode2210as illustrated inFIG.6, and may be deposited on the top surface of the conductive bank layer300. The material deposited on the second sub-pixel electrode2210may correspond to the second intermediate layer2220, and the material deposited on the top surface of the conductive bank layer300may correspond to a second-first dummy intermediate layer2220D.

Like the second intermediate layer2220, the second opposite electrode2230and the second capping layer2240may each be formed by deposition. A second-first dummy opposite electrode2230D and a second-first dummy capping layer2240D may be disposed on the top surface of the conductive bank layer300. The second-first dummy opposite electrode2230D may be disposed on the second-first dummy intermediate layer2220D, and the second-first dummy capping layer2240D may be disposed on the second-first dummy opposite electrode2230D.

A second inorganic barrier layer2510may overlap and cover the second light-emitting diode LED2. The second inorganic barrier layer2510may include at least one inorganic insulating material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and may be formed by chemical vapor deposition. The second inorganic barrier layer2510may be separated and spaced apart from the first inorganic barrier layer1510.

The second inorganic barrier layer2510has relatively better step coverage than the second intermediate layer2220and the second opposite electrode2230, and thus, may not be separated or disconnected by the overhang structure of the conductive bank layer300. The second inorganic barrier layer2510may continuously overlap and cover the top surface, side surface, and bottom surface of the tip T around the second opening300OP2, the side surface of the first conductive layer310facing the second opening300OP2, and the second light-emitting diode LED2.

The conductive bank layer300may include an inner exhaust opening300OG between the first light-emitting diode LED1and the second light-emitting diode LED2adjacent to each other. In other words, the inner exhaust opening300OG of the conductive bank layer300may be between the first sub-pixel electrode1210of the first light-emitting diode LED1and the second sub-pixel electrode2210of the second light-emitting diode LED2.

The inner exhaust opening300OG of the conductive bank layer300may provide a passage through which gas emitted from the second organic insulating layer190may be discharged. Impurities included in the insulating layer, for example, the second organic insulating layer190, may be discharged to the outside through the inner exhaust opening300OG of the conductive bank layer300while being vaporized in the process of manufacturing the display apparatus1. In case that there is no inner exhaust opening300OG of the conductive bank layer300, gas generated by the second organic insulating layer190may affect the surrounding light-emitting diodes, for example, the first or second light-emitting diode LED1or LED2, which may cause defects of the corresponding organic light-emitting diode. However, according to the disclosure, the problems described above may be solved by forming the inner exhaust opening300OG.

In case that the insulating layer115includes an inorganic insulating material, the inorganic insulating material does not pass the vaporized impurities. Accordingly, the insulating layer115may also include an opening115OG (hereinafter referred to as an exhaust opening). In other words, the exhaust opening115OG of the insulating layer115may be between the first sub-pixel electrode1210of the first light-emitting diode LED1and the second sub-pixel electrode2210of the second light-emitting diode LED2, and may overlap the inner exhaust opening300OG of the conductive bank layer300. In some embodiments, the width of the exhaust opening115OG of the insulating layer115may be less than the width of the inner exhaust opening300OG of the conductive bank layer300.

The insulating protection layer400between the conductive bank layer300and the insulating layer115may also include an opening400OG (seeFIG.10H) overlapping the inner exhaust opening300OG of the conductive bank layer300. The width of the opening400OG (seeFIG.10H) of the insulating protection layer400may be greater than the width of the exhaust opening115OG of the insulating layer115.

The conductive bank layer300may include a tip AT protruding toward the inner exhaust opening300OG. For example, the second conductive layer320may include the tip AT protruding toward the inner exhaust opening300OG from a point CPG at which the bottom surface of the second conductive layer320meets the side surface of the first conductive layer310. In other words, the conductive bank layer300may include the tip AT protruding toward the inner exhaust opening300OG from the side surface of the first conductive layer310facing the inner exhaust opening300OG.

In the process of depositing the second intermediate layer2220, a second-second dummy intermediate layer2220D′ may be formed by depositing a material for forming the second intermediate layer2220on the second organic insulating layer190through the inner exhaust opening300OG of the conductive bank layer300and the exhaust opening115OG of the insulating layer115. A second-first dummy intermediate layer2220D may be formed by depositing the material for forming the second intermediate layer2220on the tip AT around the inner exhaust opening300OG, and a dummy intermediate layer may also be formed by depositing the material on the top surface of the insulating layer115below the tip AT. The second-first dummy intermediate layer2220D deposited on the top surface of the conductive bank layer300may be separated and spaced apart from the second-second dummy intermediate layer2220D′ deposited on the second organic insulating layer190through the inner exhaust opening300OG of the conductive bank layer300. The second-second dummy intermediate layer2220D′ deposited through the inner exhaust opening300OG of the conductive bank layer300and the exhaust opening115OG of the insulating layer115may be in direct contact with the second organic insulating layer190.

Similar to the second-second dummy intermediate layer2220D′, in the deposition process of forming the second opposite electrode2230, the second-second dummy opposite electrode2230D′ may be formed by depositing a material for forming the second opposite electrode2230on the second-second dummy intermediate layer2220D′ through the inner exhaust opening300OG of the conductive bank layer300and the exhaust opening115OG of the insulating layer115. The second-second dummy capping layer2240D′ may be formed by depositing a material for forming the second capping layer2240on the second-second dummy opposite electrode2230D′ through the inner exhaust opening300OG of the conductive bank layer300and the exhaust opening115OG of the insulating layer115. The stack structure of the second-second dummy intermediate layer2220D′, the second-second dummy opposite electrode2230D′, and the second-second dummy capping layer2240D′ may overlap the inner exhaust opening300OG of the conductive bank layer300and the exhaust opening115OG of the insulating layer115.

The second inorganic barrier layer2510may overlap the inner exhaust opening300OG as well as the second light-emitting diode LED2. The stack structure of the second-second dummy intermediate layer2220D′, the second-second dummy opposite electrode2230D′, and the second-second dummy capping layer2240D′ may overlap the second inorganic barrier layer2510.

In an embodiment, as illustrated inFIG.6, a portion of the second inorganic barrier layer2510on the second light-emitting diode LED2may extend toward the inner exhaust opening300OG and overlap the inner exhaust opening300OG of the conductive bank layer300and the exhaust opening115OG of the insulating layer115, and may overlap the second-second dummy intermediate layer2220D′, the second-second dummy opposite electrode2230D′, and the second-second dummy capping layer2240D′ located in the exhaust opening115OG of the insulating layer115. In other words, a first portion of the second inorganic barrier layer2510overlapping the second light-emitting diode LED2and a second portion of the second inorganic barrier layer2510overlapping the stack structure of the second-second dummy intermediate layer2220D′, the second-second dummy opposite electrode2230D′, and the second-second dummy capping layer2240D′ through the inner exhaust opening300OG may be integral with each other.

In an embodiment, as illustrated inFIG.7, a first portion2510A of the second inorganic barrier layer2510overlapping the second light-emitting diode LED2may be separated from a second portion2510B of the second inorganic barrier layer2510overlapping the stack structure of the second-second dummy intermediate layer2220D′, the second-second dummy opposite electrode2230D′, second-second dummy capping layer2240D′. Like the second inorganic barrier layer2510as illustrated inFIG.7, the stack structure of the second-first dummy intermediate layer2220D, the second-first dummy opposite electrode2230D, and the second-first dummy capping layer2240D between the inner exhaust opening300OG and the second opening300OP2may also be separated.

In other words, the stack structure of the second-first dummy intermediate layer2220D, the second-first dummy opposite electrode2230D, and the second-first dummy capping layer2240D on the tip AT around the inner exhaust opening300OG, and the second portion2510B of the second inorganic barrier layer2510may be separated and spaced apart from the stack structure of the second-first dummy intermediate layer2220D, the second-first dummy opposite electrode2230D, and the second-first dummy capping layer2240D on the tip T around the second opening300OP2, and the first portion2510A of second inorganic barrier layer2510. Foreign matters, such as moisture, may penetrate through the second-first dummy intermediate layer2220D, the second-first dummy opposite electrode2230D, the second-first dummy capping layer2240D, and/or the second inorganic barrier layer2510. However, in the case of having the structure as illustrated inFIG.7, the penetration of the foreign matters may be blocked more effectively.

FIG.8is a schematic cross-sectional view illustrating a portion of a display apparatus1according to an embodiment, andFIGS.9A to9Care schematic cross-sectional views illustrating a groove190G of a second organic insulating layer190in the display apparatus1, according to an embodiment. InFIGS.9A to9C, a second dummy intermediate layer, a second dummy opposite electrode, and a second dummy capping layer in the groove190G of the second organic insulating layer190may be omitted for convenience of description.

According to the embodiment described above with reference toFIG.6, the top surface of the second organic insulating layer190may be illustrated as being exposed through the inner exhaust opening300OG of the conductive bank layer300and the exhaust opening115OG of the insulating layer115, but the disclosure may not be limited thereto. As illustrated inFIG.8, the second organic insulating layer190may include a groove190G overlapping an inner exhaust opening300OG of a conductive bank layer300and an exhaust opening115OG of an insulating layer115. The depth of the groove190G of the second organic insulating layer190may be less than the thickness of the second organic insulating layer190.

A stack structure of a second-second dummy intermediate layer2220D′, a second-second dummy opposite electrode2230D′, and a second-second dummy capping layer2240D′ may be arranged in the groove190G of the second organic insulating layer190. The second-second dummy intermediate layer2220D′ may be in direct contact with the second organic insulating layer190. For example, the second-second dummy intermediate layer2220D′ may be in direct contact with the top surface of the second organic insulating layer190corresponding to the groove190G. The top surface of the second organic insulating layer190corresponding to the groove190G may be regarded as the bottom surface of the groove190G. AlthoughFIG.8illustrates that the thickness of the stack structure of the second-second dummy intermediate layer2220D′, the second-second dummy opposite electrode2230D′, and the second-second dummy capping layer2240D′ may be substantially equal to the depth of the groove190G, but the disclosure may not be limited thereto. In an embodiment, the thickness of the stack structure of the second-second dummy intermediate layer2220D′, the second-second dummy opposite electrode2230D′, and the second-second dummy capping layer2240D′ may be less than the depth of the groove190G. In such a scenario, the second inorganic barrier layer2510may be in direct contact with a portion of the side surface of the groove190G.

The groove190G of the second organic insulating layer190may have various shapes in a schematic cross-sectional view. For example, as illustrated inFIG.9A, the side surface of the groove190G may include portions having different slopes from each other. For example, the side surface of the groove190G may include a first side surface190S1that may be tapered forward and has a first tilt angle α, and a second side surface190S2that may be tapered forward and has a second tilt angle β. In some embodiments, the first tilt angle α of the first side surface190S1may be greater than the second tilt angle β of the second side surface190S2.

In an embodiment, the groove190G of the second organic insulating layer190may have an inversely tapered side surface190S1in a schematic cross-sectional view as illustrated inFIG.9B. For example, the width of the upper portion of the groove190G of the second organic insulating layer190may be less than the width of the lower portion of the groove190G of the second organic insulating layer190. In other words, the width of the groove190G gradually increase from the upper portion to the lower portion thereof.

In an embodiment, as illustrated in the schematic cross-sectional view ofFIG.9C, the width (e.g., the width of the upper portion) of the groove190G of the second organic insulating layer190may be greater than the width (e.g., the width of the lower portion) of the exhaust opening115OG of the insulating layer115. The insulating layer115may include a protruding portion115P extending beyond the groove190G. The protruding portion115P extending onto the groove190G may form an overhang structure.

As illustrated inFIGS.8and9A to9C, in case that the second organic insulating layer190has the groove190G, the groove190G of the second organic insulating layer190may act as a sort of anchor. Accordingly, delamination of the second inorganic barrier layer2510and layers therebelow may be prevented.

FIGS.10A to10Iare schematic cross-sectional views schematically illustrating a process of manufacturing a display apparatus, according to an embodiment. Referring toFIG.10A, a first sub-pixel circuit PC1and a second sub-pixel circuit PC2may be formed on a substrate100. A buffer layer110may be formed on the substrate100prior to the formation of the first sub-pixel circuit PC1and the second sub-pixel circuit PC2. A specific structure of the first sub-pixel circuit PC1and the second sub-pixel circuit PC2, a gate insulating layer130, a first interlayer insulating layer150, a first organic insulating layer170, a connection metal CM, and a second organic insulating layer190may be the same as described above with reference toFIG.3.

The first sub-pixel electrode1210and the second sub-pixel electrode2210may be formed on the second organic insulating layer190. The first sub-pixel electrode1210and the second sub-pixel electrode2210may each include metal and/or conductive oxide. For example, as described above with reference toFIG.3, the first sub-pixel electrode1210and the second sub-pixel electrode2210may each include a reflection layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, any compound thereof, or a combination thereof, and a layer disposed below and/or above the reflection layer and including ITO, IZO, ZnO, or In2O3, or a combination thereof.

The conductive protection layer113may cover each of the first sub-pixel electrode1210and the second sub-pixel electrode2210. In an embodiment, the conductive protection layer113may extend beyond the edge of each of the first sub-pixel electrode1210and the second sub-pixel electrode2210. The conductive protection layer113may extend to the top surface of the second organic insulating layer190while covering the edge of each of the first sub-pixel electrode1210and the second sub-pixel electrode2210. In an embodiment, the conductive protection layer113may instead be disposed only on the first sub-pixel electrode1210and the second sub-pixel electrode2210, and may not extend to the top surface of the second organic insulating layer190.

The conductive protection layer113on the first sub-pixel electrode1210and the conductive protection layer113on the second sub-pixel electrode2210may have an isolated shape while being spaced apart from each other in the display area DA. As described above with reference toFIG.3, the conductive protection layer113may include conductive oxide, such as ITO, IZO, IGZO, ITZO, ZnO, AZO, GZO, ZTO, GTO, FTO, or a combination thereof.

Referring toFIG.10B, an insulating layer115may be formed. The insulating layer115may cover edges of the stack structure of the first sub-pixel electrode1210and the conductive protection layer113and edges of the stack structure of the second sub-pixel electrode2210and the conductive protection layer113. The insulating layer115may include an opening115OP1overlapping the first sub-pixel electrode1210and the conductive protection layer113and an opening115OP2overlapping the second sub-pixel electrode2210and the conductive protection layer113. The insulating layer115may also include an exhaust opening115OG between the first sub-pixel electrode1210and the second sub-pixel electrode2210. The second organic insulating layer190may be exposed through the exhaust opening115OG.

Thereafter, an insulating protection layer400may be formed on the insulating layer115. The insulating protection layer400may include a material having an etch selectivity different from etch selectivities of the conductive protection layer113and the insulating layer115. For example, the insulating protection layer400may include an inorganic insulating material. In an embodiment, the conductive protection layer113may include conductive oxide, such as IGZO. The insulating layer115may include an inorganic insulating material (e.g., an amorphous inorganic insulating material), such as silicon nitride. The insulating protection layer400may instead include silicon oxide. The thickness of the insulating protection layer400may be less than the thickness of the insulating layer115. The insulating protection layer400may be in contact (e.g., direct contact) with the top surface of the conductive protection layer113through the openings115OP1and115OP2of the insulating layer115. The insulating protection layer400may include a hole400H overlapping the exhaust opening115OG of the insulating layer115.

Referring toFIG.10C, conductive layers corresponding to the conductive bank layer300may be formed on the insulating protection layer400. In an embodiment,FIG.10Cillustrates a first conductive layer310, and a second conductive layer320on the first conductive layer310. The first conductive layer310and the second conductive layer320may include conductive materials having different etch selectivities from each other. In an embodiment, the first conductive layer310may include aluminum (Al), and the second conductive layer320may include titanium (Ti). The thickness of the first conductive layer310may be greater than or equal to about six times, greater than or equal to about seven times, or greater than or equal to about eight times the thickness of the second conductive layer320. In an embodiment, the thickness of the first conductive layer310may be about 0.5 μm to about 1 μm, and the thickness of the second conductive layer320may be about 0.03 μm to about 0.15 μm.

AlthoughFIG.10Cillustrates that the conductive bank layer300includes two conductive layers, the disclosure may not be limited thereto. In an embodiment, the conductive bank layer300may instead further include a third conductive layer below the first conductive layer310, in addition to the first conductive layer310and the second conductive layer320on the first conductive layer310.

As shown inFIG.10C, a first photoresist PR1having a first opening area POP1may be formed on the conductive bank layer300. The first opening area POP1of the first photoresist PR1may overlap the first sub-pixel electrode1210.

Referring toFIG.10D, a portion of the second conductive layer320and a portion of the first conductive layer310may be removed by using the first photoresist PR1as a mask. A portion of the second conductive layer320and a portion of the first conductive layer310may be removed by dry etching. During the etching process, the insulating protection layer400and the conductive protection layer113may protect the first sub-pixel electrode1210therebelow.

By removing a portion of the second conductive layer320and a portion of the first conductive layer310, an opening320OP1passing through the second conductive layer320and overlapping the first sub-pixel electrode1210may be formed in the second conductive layer320, and an opening310OP1passing through the first conductive layer310and overlapping the first sub-pixel electrode1210may be formed in the first conductive layer310.

Referring toFIG.10E, an overhang structure may be formed in the conductive bank layer300. For example, the first conductive layer310may be further etched by etching. The etching may be performed so that an opening310OP2having a width greater than that of the opening310OP1in the first conductive layer310formed in the process ofFIG.10Dmay be formed in the first conductive layer310.

In some embodiments, the opening310OP2of the first conductive layer310may have a shape in which the width decreases toward the bottom. For example, the width of the upper side of the opening310OP2of the first conductive layer310may be greater than the width of the lower side of the opening310OP2. In other words, the side surface of the first conductive layer310facing the opening310OP2may include a forward tapered slope. The opening310OP2of the first conductive layer310and the opening320OP1of the second conductive layer320on the first sub-pixel electrode1210may correspond to the first opening300OP1of the conductive bank layer300described above with reference toFIGS.6to8.

In some embodiments, the opening310OP2of the first conductive layer310may be formed by wet etching. Because the first conductive layer310and the second conductive layer320include metals having different etch selectivities from each other, a portion of the first conductive layer310may be removed in the wet etching process, and the opening310OP2of the first conductive layer310having a width greater than that of the opening320OP1of the second conductive layer320may be formed. The insulating protection layer400and the conductive protection layer113may protect the first sub-pixel electrode1210during the etching process of forming the opening310OP2of the first conductive layer310.

As a comparative example, in case that the insulating protection layer400does not exist, an etchant may damage the first sub-pixel electrode1210through microholes (e.g., pinholes, etc.) in the conductive protection layer113in the etching process (e.g., wet etching) of forming the overhang structure of the conductive bank layer300. However, in an embodiment, because the insulating protection layer400overlaps the first sub-pixel electrode1210and the conductive protection layer113, the problems described above may be prevented or minimized. Thereafter, the first photoresist PR1may be removed.

Referring toFIG.10F, after the first opening300OP1of the conductive bank layer300is formed, an opening400OP1may be formed by removing a portion of the insulating protection layer400. The opening400OP1of the insulating protection layer400may be formed by etching, for example, dry etching.

Thereafter, an opening113OP1may be formed by removing a portion of the conductive protection layer113through the opening400OP1of the insulating protection layer400. The opening113OP1of the conductive protection layer113may be formed by an etching process (e.g., wet etching) different from the etching process used to form the opening400OP1of the insulating protection layer400. Because the etch selectivity of the conductive protection layer113may be different from the etch selectivity of the insulating protection layer400, the etching process of forming the opening400OP1of the insulating protection layer400and the etching process of forming the opening113OP1of the conductive protection layer113may be performed independently or separately.

Referring toFIG.10G, a first intermediate layer1220and a first opposite electrode1230may be formed. A stack structure of the first sub-pixel electrode1210, the first intermediate layer1220, and the first opposite electrode1230may correspond to a first light-emitting diode LED1. In some embodiments, the first intermediate layer1220and the first opposite electrode1230may each be formed by a deposition process, such as a thermal evaporation process.

Because the first intermediate layer1220and the first opposite electrode1230may be deposited without a separate mask, a deposition material for forming the first intermediate layer1220and a deposition material for forming the first opposite electrode1230may completely cover the display area DA. The deposition material for forming the first intermediate layer1220and the deposition material for forming the first opposite electrode1230, which are deposited on the first sub-pixel electrode1210, may form the first intermediate layer1220and the first opposite electrode1230, respectively. The deposition material for forming the first intermediate layer1220and the deposition material for forming the first opposite electrode1230, which are deposited on the tip T of the conductive bank layer300, may form the first dummy intermediate layer1220D and the first dummy opposite electrode1230D, respectively. The first intermediate layer1220and the first dummy intermediate layer1220D may be separated and spaced apart from each other, and the first opposite electrode1230and the first dummy opposite electrode1230D may be separated and spaced apart from each other. The first intermediate layer1220and the first dummy intermediate layer1220D may include the same material and/or the same number of sub-layers (e.g., a first common layer, an emission layer, and a second common layer). The first opposite electrode1230and the first dummy opposite electrode1230D may include the same material.

The outer portion of the first opposite electrode1230including the edge of the first opposite electrode1230may extend beyond the edge of the first intermediate layer1220and may be in direct contact with the side surface of the first conductive layer310. The first conductive layer310may be electrically connected to the first opposite electrode1230.

The first capping layer1240may be formed on the first opposite electrode1230. Like the first opposite electrode1230, the first capping layer1240may be deposited without a separate mask. A portion of the deposition material for forming the first capping layer1240may form the first dummy capping layer1240D disposed on the first dummy opposite electrode1230D on the conductive bank layer300.

Thereafter, a first inorganic barrier layer1510may be formed on the first light-emitting diode LED1. The first inorganic barrier layer1510may include at least one inorganic insulating material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and may be formed by chemical vapor deposition. The first inorganic barrier layer1510may be continuously formed to overlap the top surface and the side surface of the conductive bank layer300and the top surface of the first opposite electrode1230.

Thereafter, a second photoresist PR2may be formed on the first inorganic barrier layer1510. In case that a portion of the first inorganic barrier layer1510, a portion of the first dummy capping layer1240D, a portion of the first dummy opposite electrode1230D, and a portion of the first dummy intermediate layer1220D which do not overlap the second photoresist PR2are removed by using the second photoresist PR2as a mask, the first dummy capping layer1240D, the first dummy opposite electrode1230D, and the first dummy intermediate layer1220D may be located around the first light-emitting diode LED1as illustrated inFIG.10G. Thereafter, the second photoresist PR2may be removed.

Referring toFIG.10H, a photoresist (not shown) including an opening area overlapping the second sub-pixel electrode2210and an opening area between the first sub-pixel electrode1210and the second sub-pixel electrode2210may be formed. A second opening300OP2and an inner exhaust opening300OG may be formed in the conductive bank layer300by using the photoresist as a mask.

Like the first opening300OP1and the second opening300OP2, the inner exhaust opening300OG of the conductive bank layer300may have an overhang structure. The overhang structure of the inner exhaust opening300OG of the conductive bank layer300may be formed in the same process as the overhang structure of the second opening300OP2.

Thereafter, an opening400OP2may be formed by etching a portion of the insulating protection layer400overlapping the second opening300OP2of the conductive bank layer300, and an exhaust opening400OG may be formed by etching a portion of the insulating protection layer400overlapping the inner exhaust opening300OG of the conductive bank layer300. The insulating protection layer400may be etched by dry etching.

In some embodiments, a portion of the second organic insulating layer190may also be removed. For example, a groove190G may be formed in the second organic insulating layer190by removing a portion of the second organic insulating layer190overlapping the exhaust opening115OG of the insulating layer115and the exhaust opening400OG of the insulating protection layer400. The groove190G of the second organic insulating layer190may have the same structure as described above with reference toFIGS.9A to9C.

Referring toFIG.10I, a second intermediate layer2220and a second opposite electrode2230may be formed. Because the second intermediate layer2220and the second opposite electrode2230may be deposited without a separate mask, a deposition material for forming the second intermediate layer2220and a deposition material for forming the second opposite electrode2230may be completely formed in the display area DA.

A stack structure of the second sub-pixel electrode2210, the second intermediate layer2220, and the second opposite electrode2230may correspond to a second light-emitting diode LED2. In some embodiments, the second intermediate layer2220and the second opposite electrode2230may each be formed by a deposition process, such as a thermal evaporation process.

Due to the overhang structure around the second opening300OP2of the conductive bank layer300, the second intermediate layer2220and the second opposite electrode2230on the second sub-pixel electrode2210may be separated and spaced apart from the second-first dummy intermediate layer2220D and the second-first dummy opposite electrode2230D on the top surface of the conductive bank layer300. The second-second dummy intermediate layer2220D′ and the second-second dummy opposite electrode2230D′ arranged in the groove190G in the inner exhaust opening300OG of the conductive bank layer300may be separated and spaced apart from the second-first dummy intermediate layer2220D and the second-first dummy opposite electrode2230D on the tip AT of the overhang structure around the inner exhaust opening300OG of the conductive bank layer300.

In the second opening300OP2and at a location corresponding to second light-emitting element LED2, the outer portion of the second opposite electrode2230including the edge of the second opposite electrode2230may extend beyond the edge of the second intermediate layer2220and may be in direct contact with the side surface of the first conductive layer310. The first conductive layer310may be electrically connected to the second opposite electrode2230. A second capping layer2240may be formed on the second opposite electrode2230. Like the second opposite electrode2230, the second capping layer2240may be deposited without a separate mask. A portion of the deposition material for forming the second capping layer2240may form a second-first dummy capping layer2240D on the second-first dummy opposite electrode2230D external to the opening300OP2.

Thereafter, a second inorganic barrier layer2510may be formed on the second light-emitting diode LED2. The second inorganic barrier layer2510may include at least one inorganic insulating material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and may be formed by chemical vapor deposition. The second inorganic barrier layer2510may be formed to completely cover the display area DA. For example, the second inorganic barrier layer2510may be formed to overlap the inner exhaust opening300OG of the conductive bank layer300. The second inorganic barrier layer2510may overlap the groove190G, the second-second dummy intermediate layer2220D′ and the second-second dummy opposite electrode2230D′ formed in the groove190G.

A third photoresist PR3may be formed. Thereafter, a portion of the second inorganic barrier layer2510, a portion of the second-first dummy capping layer2240D, a portion of the second-first dummy opposite electrode2230D, and a portion of the second-first dummy intermediate layer2220D which do not overlap the third photoresist PR3may be removed. As illustrated inFIG.10I, the second-first dummy capping layer2240D, the second-first dummy opposite electrode2230D, and the second-first dummy intermediate layer2220D may be disposed on the tip T around the second light-emitting diode LED2. In case that the third photoresist PR3is removed, the structure illustrated inFIG.8may be obtained.

FIG.11is a plan view of a display apparatus1according to an embodiment. Referring toFIG.11, the display apparatus1may include a display area DA and a non-display area NDA. A planar shape of the display apparatus1may be a shape of a substrate100. For example, the expression “the display apparatus1includes the display area DA and the non-display area NDA” may mean that the substrate100includes the display area DA and the non-display area NDA. The display area DA may provide an image through light-emitting diodes arranged in the display area DA, and thus, may correspond to an image plane of the display apparatus1.

A common voltage supply line10configured to provide a common voltage ELVSS to opposite electrodes (e.g., cathodes) of the light-emitting diodes arranged in the display area DA and a driving voltage supply line20configured to provide a driving voltage ELVDD to a pixel circuit may be arranged in the non-display area NDA. The driving voltage supply line20may be electrically connected to the driving voltage line (see PL ofFIG.2) arranged in the display area DA. The common voltage supply line10may have a shape that partially surrounds the display area DA. For example, the common voltage supply line10may have a closed loop shape with one side corresponding to first side100aopen.

FIG.12is an enlarged plan view illustrating a region XII of the display apparatus1ofFIG.11according to an embodiment. Referring toFIG.12, the common voltage supply line10may be arranged in the non-display area NDA, and a conductive layer210arranged in the non-display area NDA may overlap the common voltage supply line10.

A conductive bank layer300may extend to the non-display area NDA. The conductive bank layer300may overlap the conductive layer210and the common voltage supply line10in the non-display area NDA. The conductive bank layer300may include an exhaust opening300OGP (hereinafter referred to as an outer exhaust opening) for discharging gas generated from a second organic insulating layer190overlapping the conductive bank layer300in the non-display area NDA. The outer exhaust opening300OGP of the conductive bank layer300may include first outer exhaust openings300OGP1relatively close to the display area DA and second outer exhaust openings300OGP2relatively far from the display area DA. The second outer exhaust openings300OGP2may overlap the common voltage supply line10. Contact holes CNT for electrical connection between the conductive bank layer300and the common voltage supply line10may be arranged adjacent to the second outer exhaust openings300OGP2.

A valley structure VY may be formed between the first outer exhaust openings300OGP1and the second outer exhaust openings300OGP2. The valley structure VY may indicate an area from which a portion of the organic insulating layer between the substrate (see100ofFIG.6) and the first and second sub-pixel electrodes1210and2210; for example, a portion of each of the first organic insulating layer170and the second organic insulating layer190may be removed in the depth direction.

A built-in circuit DPC may be between the valley structure VY and the display area DA or between the common voltage supply line10and the display area DA. The built-in circuit DPC may correspond to a driver (e.g., a scan driver, etc.) configured to provide electrical signals or power to the display area DA, and may include multiple transistors. The built-in circuit DPC may be between the substrate (see100ofFIG.6) and the conductive layer210in the thickness direction (e.g., z direction). The built-in circuit DPC may overlap the conductive layer210and/or the conductive bank layer300in the non-display area NDA. The conductive layer210may be formed in a same process as the first and second sub-pixel electrodes1210and2210described above with reference toFIG.6

A partition wall or banks PW configured to control the flow of materials (e.g., monomers) for forming an organic encapsulation layer may be arranged in the non-display area NDA. The organic encapsulation layer may cover the display area DA and an edge of the organic encapsulation layer may be located adjacent to the banks PW. In some embodiments, the banks PW may overlap the common voltage supply line10.

FIG.13Ais a plan view illustrating the first outer exhaust opening300OGP1and surroundings thereof inFIG.12,FIG.13Bis a plan view illustrating the second outer exhaust opening300OGP2and surroundings thereof inFIG.12,FIG.14Ais a schematic cross-sectional view of the first outer exhaust opening300OGP1taken along line XIIIa-XIIIa′ ofFIG.13A, andFIG.14Bis a schematic cross-sectional view of the second outer exhaust opening300OGP2taken along line XIIIb-XIIIb′ ofFIG.13B. Referring toFIGS.13A and14A, gas included in the second organic insulating layer190below the conductive bank layer300may be discharged to the outside through the first outer exhaust opening300OGP1. The conductive bank layer300may include a tip PT (hereinafter referred to as an outer tip) protruding toward the first outer exhaust opening300OGP1.

Layers below the conductive bank layer300may include holes overlapping the first outer exhaust opening300OGP1. For example, the conductive protection layer113may include a hole (see113H1ofFIG.13A) overlapping the first outer exhaust opening300OGP1, and the conductive layer210may include a hole (see210H1ofFIG.13A) overlapping the first outer exhaust opening300OGP1. The conductive layer210may include the same material as the first and second sub-pixel electrodes1210and2210described above with reference toFIG.6and may be formed in the same process as the first and second sub-pixel electrodes1210and2210described above with reference toFIG.6.

In some embodiments, the second organic insulating layer190below the conductive bank layer300may include a groove190GP overlapping the first outer exhaust opening300OGP1. The groove190GP of the second organic insulating layer190in the non-display area NDA may have the same structure as the groove190G in the display area described above with reference toFIGS.9A to9C.

A width of the first outer exhaust opening300OGP1may be less than the width of the hole113H1of the conductive protection layer113, and the width of the hole113H1of the conductive protection layer113may be less than the width of the hole210H1of the conductive layer210. The width of the hole of the insulating protection layer400may be less than the width of the hole113H1of the conductive protection layer113. The width of the first outer exhaust opening300OGP1may correspond to the width of the opening defined by the outer tip PT.

Referring toFIGS.13B and14B, gas included in the second organic insulating layer190below the conductive bank layer300may be discharged to the outside through the second outer exhaust opening300OGP2. The conductive bank layer300may include a tip PT (hereinafter referred to as an outer tip) protruding toward the second outer exhaust opening300OGP2. Contact holes CNT for electrical connection between the conductive bank layer300and the common voltage supply line10may be arranged adjacent to the second outer exhaust openings300OGP2. The conductive bank layer300may be electrically connected to the common voltage supply line10through the contact holes CNT formed in the second organic insulating layer190.

Layers below the conductive bank layer300may include holes overlapping the second outer exhaust opening300OGP2and the contact holes CNT. For example, the conductive protection layer113may include a hole (see113H2ofFIG.13B) overlapping the contact hole CNT and the second outer exhaust opening300OGP2, and the conductive layer210may include a hole (see210H2ofFIG.13B) overlapping the contact hole CNT and the second outer exhaust opening300OGP2. In some embodiments, the second organic insulating layer190below the conductive bank layer300may include a groove190GP overlapping the second outer exhaust opening300OGP2. The groove190GP of the second organic insulating layer190in the non-display area NDA may have the same structure as the groove190G in the display area described above with reference toFIGS.9A to9C.

A width of the second outer exhaust opening300OGP2may be less than the width of the hole113H2of the conductive protection layer113, and the width of the hole113H2of the conductive protection layer113may be less than the width of the hole210H2of the conductive layer210. The width of the second outer exhaust opening300OGP2may correspond to the width of the opening defined by the outer tip PT.

As described above with reference toFIGS.6to8, the first opposite electrode1230and the second opposite electrode2230may be electrically connected to the conductive bank layer300through the first opening300OP1and the second opening300OP2of the conductive bank layer300, respectively. As illustrated inFIG.12, the conductive bank layer300in the display area DA may extend to the non-display area NDA and may be electrically connected to the common voltage supply line10. Accordingly, the first opposite electrode1230and the second opposite electrode2230may be electrically connected to the common voltage supply line10via the conductive bank layer300.

The inorganic barrier layer510may cover the first outer exhaust opening300OGP1and the second outer exhaust opening300OGP2. The inorganic barrier layer510covering each of the first outer exhaust opening300OGP1and the second outer exhaust opening300OGP2may include the same material as the second inorganic barrier layer2510described above with reference toFIGS.6and7.

FIG.15is an enlarged plan view of a portion XV ofFIG.11. Referring toFIGS.11and15, the conductive bank layer300may extend to the non-display area NDA. The conductive bank layer300may extend to overlap each of the common voltage supply line10and the driving voltage supply line20in the non-display area NDA. The conductive bank layer300may include a first outer exhaust opening300OGP1between a first side100aof the substrate100and the display area DA.

As described above with reference toFIGS.11and12, the conductive layer (see210ofFIG.12) may extend to the non-display area NDA along the remaining sides of the substrate100excluding the first side100a.As illustrated inFIG.15, the conductive layer210may not be arranged in a region of the non-display area NDA between the first side100aof the substrate100and the display area DA. Similarly, the conductive protection layer (see113ofFIG.6) may not be arranged in the region of the non-display area NDA between the first side100aof the substrate100and the display area DA.

AlthoughFIG.12illustrates that contact holes (see CNT ofFIG.12) for electrical connection between the conductive bank layer300and the common voltage supply line10may be formed along the remaining sides of the substrate100excluding the first side100a,contact holes may not be between the first side100aof the substrate100and the display area DA, as illustrated inFIG.15.

As described above with reference toFIGS.11and12, the first outer exhaust openings300OGP1and the second outer exhaust openings300OGP2may be arranged along the remaining sides of the substrate100excluding the first side100a,and the first outer exhaust openings300OGP1may be between the first side100aof the substrate100and the display area DA. In other words, the second outer exhaust opening300OGP2may not be between the first side100aof the substrate100and the display area DA.

Unlike that illustrated inFIG.15, according to an embodiment, contact holes for electrical connection between the conductive bank layer300and the common voltage supply line10may be further between the first side100aof the substrate100and the display area DA. In other words, in an embodiment, not only the first outer exhaust openings300OGP1but also the structure of the second outer exhaust openings300OGP2and the contact holes CNT described above with reference toFIGS.12and13Bmay be between the first side100aof the substrate100and the display area DA.

According to an embodiment, in the display apparatus including the conductive bank layer, gas may be readily discharged from the organic insulating layer between the substrate and the conductive bank layer. These effects may be only examples and the scope of the disclosure may not be limited by such effects.