Form Factor Adapter for Information Handling System Add-In Cards

Add-in card (AIC) adapters or sleeve adapters, suitable for use with information handling system chassis defining one or more AIC bays suitable for receiving a first AIC form factor, convert the bay into two or more sleeve-defined bays. Each sleeve bay is suitable for receiving a different and typically smaller form factor. For example, a chassis with an Enterprise and Data Center Standard Form Factor (EDSFF) E5 double wide bay may include a sleeve adapter defining two E5 single wide sleeve bays, each of which is suitable for receiving a corresponding E5 single wide AIC form factor. In another example, a sleeve adapter may be configured to convert an E5 double wide bay into one or more sleeve bays configured for a legacy CEM form factor. Sleeve adapters may route a subset of PCIe data lanes associated with a bay to each sleeve bay defined by the sleeve adapter.

TECHNICAL FIELD

The present disclosure pertains to information handling system and, more specifically, information handling system features for accommodating add-in cards (AICs).

BACKGROUND

Many server class and other types of information handling systems include one or more AICs that provide peripheral devices including, as example, network interface controllers (NICs), host bus adapters (HBAs), data processing units (DPUs), etc. and graphics processing units (GPUS). AICs generally include a printed circuit board (PCB), which is populated with various components and sized in accordance with a standardized form factor and a commercially significant percentage of AICs are designed for use with a Peripheral Component Interconnect express (PCIe) expansion bus.

FIG.1depicts PCIe-compliant AICs including card electromechanical (CEM) AICs101and EDSFF AICs102. For the sake of comparison, the AICs depicted inFIG.1are approximately, if not precisely, to scale. The CEM AICs101illustrated inFIG.1represent four different CEM form factors including a low profile form factor101-1, a full height half length (FHHL) form factor101-2, a full height, three-quarter length (FH3/4L) form factor101-3, and a full height, full length (FHFL) form factor101-4. The EDSFF AICs102ofFIG.1illustrate a proposed, but not yet finalized version of an E5 form factor102-1, an Open Compute Project (OCP) form factor102-2, and an E3 long form factor102-3.

While the use of numerous CEM form factors beneficially accommodates a variety of system configurations and solutions, it has also undesirably increased chassis complexity and differentiation.FIG.2, which depicts six distinct chassis configurations201-1through201-6for a 2U rack mount server for a single CPU platform such as, captures a portion of this complexity at least because each chassis201depicted inFIG.2accommodates a different combination of CEM AICs. This complexity is only likely to increase as the various EDSFF form factors become increasingly prevalent.

SUMMARY

The chassis complexity described above is addressed by AIC adapters, referred to herein as sleeve adapters, suitable for use in conjunction with disclosed information handling systems chassis wherein a chassis defines one or more larger AIC bays suitable for receiving a larger AIC form factor and each sleeve adapter converts the AIC bay into two or more sleeve-defined bays, referred to herein simply as sleeve bays, each of which is suitable for receiving a different and typically smaller AIC form factor. As an example, a system chassis may include or define one or more E5 double wide bays wherein at least one of the E5 double wide bays includes a sleeve adapter defining two E5 single wide sleeve bays, each of which is suitable for receiving a corresponding E5 single wide AIC form factor. In another example, a sleeve adapter may be configured to convert an E5 double wide bay into two or more CEM bays, each of which accommodates a corresponding CEM AIC form factor. As an example, the E5 double wide bay of the previous example may receive a sleeve adapter configured to convert the bay into two low profile (LP) CEM sleeve bays, each of which is suitable for receiving an LP CEM AIC.

Each chassis bay may be suitable for receiving a first plurality of data I/O signals and each sleeve adapter may be configured to route subsets of the first plurality of data signals to each of the two or more sleeve bays. If a chassis bay is configured to support, as an example, 32 PCIe data lanes, a sleeve adapter defining N sleeve bays may be configured to route32/N data channels to each of the N sleeve bays. For the previously mentioned sleeve adapter defining two sleeve bays, the sleeve adapter may be configured to route16lanes to each sleeve bay. For a sleeve adapter defining four sleeve bays, the sleeve adapter may route eight data lanes to each sleeve bay.

In another illustrative example, the chassis bay may be implemented to accommodate an AIC with an EDSFF form factor and the sleeve adapter may be configured to accommodate one or more AICs having a CEM form factor. Examples of these such embodiments may include an E5 double wide chassis bay and a sleeve adapter defining two CEM low profile (LP) AICs or a sleeve adapter defining at least one and possibly multiple CEM FHHL AICs.

Thus, disclosed information handling chassis define one or more AIC bays including at least one AIC bay configured to accommodate a first AIC form factor. Disclosed systems may further include a sleeve adapter received in the first AIC bay, defining two or more sleeve bays including a first sleeve bay configured to accommodate a second form factor AIC, i.e., an AIC with a second type of form factor, different than the first form factor. Each sleeve adapter may include a sleeve adapter shell and a routing means to route signals from a connector for the first type of form factor to appropriate signals on a connector for the second type of AIC form factor. As suggested in at least some of the preceding examples, the first form factor may an E5 double wide (2T) form factor and the second form factor standard may be any of the following form factors: an EDSFF E5 single wide (1T) form factor, an EDSFF E3 form factor, an EDSFF E1 or OCP form factor, and a CEM form factor. Thus, numerous sleeve adapters can be created wherein each sleeve adapter allows conversion of a larger bay and its larger PCIe lane count for other EDSFF family form factor or for at least some of the smaller legacy CEM AICs.

DETAILED DESCRIPTION

Exemplary embodiments and their advantages are best understood by reference toFIGS.1-11, wherein like numbers are used to indicate like and corresponding parts unless expressly indicated otherwise.

Additionally, an information handling system may include firmware for controlling and/or communicating with, for example, hard drives, network circuitry, memory devices, I/O devices, and other peripheral devices. For example, the hypervisor and/or other components may comprise firmware. As used in this disclosure, firmware includes software embedded in an information handling system component used to perform predefined tasks. Firmware is commonly stored in non-volatile memory, or memory that does not lose stored data upon the loss of power. In certain embodiments, firmware associated with an information handling system component is stored in non-volatile memory that is accessible to one or more information handling system components. In the same or alternative embodiments, firmware associated with an information handling system component is stored in non-volatile memory that is dedicated to and comprises part of that component.

Throughout this disclosure, a hyphenated form of a reference numeral refers to a specific instance of an element and the un-hyphenated form of the reference numeral refers to the element generically. Thus, for example, “device12-1” refers to an instance of a device class, which may be referred to collectively as “devices12” and any one of which may be referred to generically as “a device12”.

As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication, mechanical communication, including thermal and fluidic communication, thermal, communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

Referring now to the drawings,FIGS.3,4, and5depict an exemplary sequence for implementing disclosed features for mitigating chassis complexity. As depicted inFIG.3, a 2U rack mount server300includes a chassis301defining three EDSFF E5 double wide bays302-1,302-2, and302-3, each of which is empty or unpopulated. AlthoughFIG.3illustrates the specific example of E5 double wide bay bays302, disclosed subject matter is applicable to chassis bays other than E5 bays. Similarly, althoughFIG.3illustrates a 2U rack mount server300, disclosed subject matter is applicable to10, 4U and other suitable server configurations.

FIG.4illustrates a sleeve adapter304inserted or otherwise installed in the first empty bay (302-1) of the rack mount server illustrated inFIG.3. The illustrated sleeve adapter304includes a sleeve shell306, defining sleeve-adapted bays, referred to herein simply as sleeve bays310, of which two are shown inFIG.4, i.e., sleeve bays310-1and310-2. Each sleeve bay310is configured to be suitable for receiving an AIC form factor other than the AIC form factor associated with the empty chassis bays302depicted inFIG.3. Continuing with the example of EDSFF E5 double wide bays302, sleeve bays310defined by sleeve adapter304may comprise E5 single wide sleeve adapters, i.e., sleeve adapters configured to receive E5 single wide AICs. Again, however, although the drawings illustrate specific implementations, disclosed subject matter is not limited to the depicted implementations and it will be readily appreciated by those of ordinary skill in the field of server chassis design that sleeve bays310may be sized and otherwise configured to accommodate form factors other than the E5 single wide form factors and that sleeve adapter304may define more than the two sleeve bays310illustrated inFIG.4.

FIG.5depicts the illustrated 2U rack server300after an E5 single wide device320has been inserted or otherwise installed into the E5 single wide sleeve bay310-1ofFIG.4. AlthoughFIG.5illustrates one of the available sleeve bays (310-2) empty and one of the sleeve bays populated with a device implemented on suitable form factor, disclosed subject matter encompasses a readily imaginable implementation and configuration in which both of the sleeve bays310ofFIG.4have been populated with devices of a suitable form factor.

Embodiments of disclosed subject matter may provide a plurality of data signals such as 8, 16, or 32 PCIe data lanes to each chassis bay302and, in at least some embodiments, the previously referenced wiring and circuitry means within each sleeve adapters304may route a subset of the chassis bay's data lanes to the corresponding sleeve bay310. In the case of a chassis bay302that receives 32 PCIe data lanes and a sleeve adapter304that defines two sleeve bays310, sleeve adapter310may include data channel routing means for routing 16 of the 32 data lanes to the first sleeve bay310-1and the remaining 16 data lanes to the second sleeve bay310-2. For implementations (not depicted in the figures) of sleeve adapters304that might define four or eight sleeve bays, each sleeve adapter may include data channel routing means for routing distinct subsets of eight or four data lanes to each sleeve bay310.

Thus,FIG.3throughFIG.5illustrate a single 2U rack mount server chassis301deployed to accommodate at least two configurations including a first configuration in which one of the server's AIC bays is populated with a single E5 double wide x32 AIC form factor device and further including a second configuration in which the same chassis bay is provisioned with an adapter sleeve defining two sleeve bays each of which maybe populated with two x16 E5 single wide form factor devices.

Referring now toFIG.6, another configuration of the rack mount server300ofFIGS.3-5is depicted to illustrate desirable configuration flexibility enabled by disclosed sleeve adapter subject matter. As depicted inFIG.6, the three E5 double wide bays302of the illustrated server300have each been provisioned with a different type of sleeve adapter304. Specifically, the first bay302-1of server300, like the first bay302-1depicted inFIG.5, is depicted provisioned with a sleeve adapter304defining a pair of E5 single wide sleeve bays310configured to accommodate a corresponding pair of E5 single wide AIC form factor devices, which are omitted fromFIG.6for greater clarity. The second bay302-2of server300is depicted provisioned with a sleeve adapter304-2defining four sleeve bays410each of which is configured to accommodate a corresponding E3 thin form factor AIC, again not shown inFIG.6, while the third bay302-3of server300is illustrated provisioned with a third sleeve adapter304-3defining two E3 thick sleeve bays510, each of which is suitable for accommodating an E3 thick AIC form factor device. Thus, a single type of chassis bay302is leveraged to accommodate three different configurations of AICs and, in each configuration, the chassis bay's data lanes are distributed among each of the sleeve bays310,410,510defined by the applicable sleeve adapters304-1,304-2and304-3.

The server configurations illustrated inFIGS.3,4,5, and6all feature E5 double wide chassis bays and sleeve bays configured to accommodate another EDSFF form factor. In other embodiments, the chassis bays302may accommodate form factors from one family of form factors while the sleeve bays defined by the sleeve adapters may accommodate AIC form factors from a different family. In at least one such embodiment in which the E5 double wide chassis bays depicted inFIG.3-6are again used, the sleeve adapters304may include one or more sleeve adapters defining one or more sleeve bays configured to accommodate one or more types of legacy AICs including legacy CEM AICs such as LP CEM AICs and FHHL CEM AICs. Still other configurations may accommodate customer or non-standard configurations which, for purposes of this disclosure may refer to implementations that accommodate forms factors other than CEM and EDSFF form factors.

Turning now toFIG.7, eight different AIC configurations of a single double wide E5 chassis bay, such as the chassis bays302ofFIG.3, are depicted to illustrate flexibility of disclosed sleeve adapters in accommodating cross-family configurations in which, for example, a sleeve adapter enables an EDSFF chassis bay to accept and accommodate a non-EDSFF form factor AIC as well as custom configurations in which, for example, an EDSFF bay accommodates one or more devices that are not implemented with a form factor that is neither an EDSFF form factor nor a CEM form factor.

Specifically, the illustrated AIC configurations for the exemplary E5 double wide a double wide bay302include: a first configuration701-1in which an adapter sleeve704-1defines two E5 single wide sleeve bays710-1, a second configuration701-2in which an adapter sleeve704-2defines four E3 thin sleeve bays710-2, a third configuration701-3in which an adapter sleeve704-3defines two E3 thick sleeve bays710-3, a fourth configuration701-4in which an adapter sleeve704-4defines twelve E1 sleeve bays710-4, a fifth configuration701-5in which an adapter sleeve704-5defines two LP CEM sleeve bays710-5, a sixth configuration701-6in which an adapter sleeve704-6defines at least one and depending upon final dimensions of the E5 form factor, two FHHL CEM sleeve bays710-6, a seventh configuration701-7in which an adapter sleeve adapter704-7defines six E1 sleeve bays710-7and an additional sleeve bay720-7for a redundant array of independent disks (RAID) controller, and an eighth configuration701-8in which an adapter sleeve704-8defines four E3 thin sleeve bays710-8and an additional sleeve bay720-8for a boot optimized RAID controller such as a boot optimized storage solution (BOSS) RAID solution from Dell Technologies.

Turning now toFIG.8, a side elevation view of an exemplary chassis bay302and a sleeve adapter304defining four E3 thin sleeve bays310-1through310-4is presented. The sleeve adapter304ofFIG.8includes a sleeve adapter frame804, defining the physical surfaces of sleeve bays310, and connection means801for routing signals provided to chassis bay302to each AICs received in a sleeve bay310. Sleeve adapter frame804may be comprised of sheet metal or another suitable material.

Chassis bay302is illustrated inFIG.8with a side portion of chassis301removed to reveal signal routing means801implemented, inFIG.8, with electrically conductive cables connecting contacts, including data lane contacts, of an EDSFF E5 connector810with contacts, including data lane contacts, of EDSFF E3 thin connectors820within each E3 thin sleeve bay310.

FIG.9illustrates a plan view of an exemplary chassis bay302and a sleeve adapter304defining an FHHL CEM sleeve bay310suitable for receiving an FHHL CEM AIC830and a corresponding riser card832for receiving a connector edge834of FHHL CEM card830. The illustrated sleeve adapter304includes routing means801comprising one or more electrically conductive cables connecting contacts, including data lane contacts, of the EDSFF E5 connector810with suitable corresponding contacts of the riser card832. As depicted inFIG.9, the illustrated sleeve adapter includes routing means801connecting the FHHL CEM riser card832to the EDSFF connector810for the 85 chassis bank.

FIG.10, similar toFIG.9, illustrates an adapter sleeve304defining a sleeve bay310suitable for an LP CEM AIC840and a corresponding riser card842for receiving a connector edge844of LP CEM card840. As depicted inFIG.10, the illustrated sleeve adapter includes routing means801connecting LP CEM riser card842to the E5 EDSFF connector810.

Thus, in each of the sleeve adapters illustrated inFIGS.8,9, and10, the depicted sleeve adapters include sleeve adapter shells providing the physical outline of the corresponding sleeve bays, as well as routing means for coupling the signals provided to the chassis bay to each of the sleeve adapter connectors.

Referring now toFIG.11, any one or more of the elements illustrated inFIG.1throughFIG.10may be implemented as or within an information handling system exemplified by the information handling system1100illustrated inFIG.11. The illustrated information handling system includes one or more general purpose processors or central processing units (CPUs)1101communicatively coupled to a memory resource1110and to an input/output hub1120to which various I/O resources and/or components are communicatively coupled. The I/O resources explicitly depicted inFIG.11include a network interface1140, commonly referred to as a NIC (network interface card), storage resources1130, and additional I/O devices, components, or resources1150including as non-limiting examples, keyboards, mice, displays, printers, speakers, microphones, etc. The illustrated information handling system1100includes a baseboard management controller (BMC)1160providing, among other features and services, an out-of-band management resource which may be coupled to a management server (not depicted). In at least some embodiments, BMC1160may manage information handling system1100even when information handling system1100is powered off or powered to a standby state. BMC1160may include a processor, memory, an out-of-band network interface separate from and physically isolated from an in-band network interface of information handling system1100, and/or other embedded information handling resources. In certain embodiments, BMC1160may include or may be an integral part of a remote access controller (e.g., a Dell Remote Access Controller or Integrated Dell Remote Access Controller) or a chassis management controller.