Information handling system with display device interface supporting dynamic configuration of link data rate

A method of configuring a display device interface (DDI) detects a trigger signal, generated by a display device. If the trigger signal is associated with a power on event, a full configuration of the DDI is performed, including loading display device capability information provided by the display device into DDI configuration registers and setting one or more DDI configuration parameters accordingly. If the trigger signal is associated with resume event, rather than a power on event, a modified fast link resume operation may be performed to route the trigger signal to a controller configured to explicitly write display device capability information to the appropriate DDI configuration registers before setting the corresponding DDI configuration parameter accordingly. The DDI may include a re-timer, between the DDI source and sink, configured to snoop the explicit write transaction such that the re-timer configuration is also updated.

TECHNICAL FIELD

The present disclosure relates to information handling system display devices and, more specifically, the configuration of display device interfaces for embedded displays.

BACKGROUND

Many information handling systems, including desktop, laptop, and notebook computer systems, include a display device for displaying video content, still images, computer generated graphics, and so forth. In such systems, a display device interface (DDI) coordinates the communication of pixel data from a video information source on the host system to a video information sink such as the display device. One pervasive DDI referenced herein is the DisplayPort family of DDI standards. DDIs may encompass physical and electrical characteristics of the host-display transport as well as protocols for formatting and communicating pixel data. DDIs are generally able to support different configurations. As one of numerous possible examples, a DDI may support two or more maximum data transfer rates. Accordingly, it is important to ensure that the DDI source and the DDI sink recognize compatible configurations. In addition, because display devices consume significant power when active, display devices are routinely put to sleep or powered down and must be fully or partially re-configured when restored. Accordingly, DDIs typically perform a significant number of configuration operations, which may include numerous register read/write operations and potentially timing consuming link training operations.

In a platform, such as a notebook computer, that includes an embedded display, it may be reasonable to anticipate comparatively fewer display device reconfigurations because the display device does not generally change. Accordingly, DDI developers may wish to implement streamlined protocols for embedded applications. As an example, the DisplayPort family of DDI standards includes a companion standard, appropriately referred to as embedded DisplayPort (eDP), intended for embedded-display platforms. An example of protocol streamlining supported in eDP is a feature referred to as fast link training. Fast link training permits platform firmware corresponding to the DDI source port to assume that the DDI configuration is static during any given power interval. Under this assumption, eDP fast link training permits the source port to re-use specified configuration settings, rather than mandating a full configuration of the transport based on display device capabilities received from the DDI sink port. While fast link training may potentially improve performance when a sleeping display device transitions from a sleep state, it may be necessary or desirable to supplement fast link functionality to include explicit configuration updates.

SUMMARY

In accordance with subject matter disclosed in the following description, a disclosed method for configuring a DDI may detect a trigger signal generated by a display device. If the trigger signal is associated with a power on event, a full configuration of the DDI is performed, including loading display device capability information provided by the display device into DDI configuration registers and setting one or more DDI configuration parameters accordingly. If the trigger signal is associated with resume event, rather than a power on event, a modified fast link resume operation may be performed to route the trigger signal to a controller configured to explicitly write display device capability information to the appropriate DDI configuration registers before setting the corresponding DDI configuration parameter. The DDI may include a re-timer, between the DDI source and sink, configured to snoop the explicit write transaction such that the re-timer configuration is also updated.

The display device interface configuration parameter(s) may include a link data rate parameter indicative of a maximum rate of transferring data via the DDI. The display device may be an embedded display device and the DDI may comprise an embedded DisplayPort (eBD) interface, including a unidirectional eDP main link for transporting video data from source to sin, a bidirectional eDP aux channel over which the source may discover capabilities of the sink, and a hot plug detect (HPD) signal generated by the display device to signal either a power on event or a resume event. The embedded display device may be a ultra-high definition (UHD) display device requiring a high bit rate (HBR) transport including, as a non-limiting example, an HBR3 transport with an 8.1 Gbps link rate. The controller and the re-timer device may both be coupled to a system management bus and the controller may perform the explicit write transaction as a system management bus transaction.

DETAILED DESCRIPTION

Exemplary embodiments and their advantages are best understood by reference toFIGS. 1-4, wherein like numbers are used to indicate like and corresponding parts unless expressly indicated otherwise.

Additionally, an information handling system may include firmware for controlling and/or communicating with, for example, hard drives, network circuitry, memory devices, I/O devices, and other peripheral devices. For example, the hypervisor and/or other components may comprise firmware. As used in this disclosure, firmware includes software embedded in an information handling system component used to perform predefined tasks. Firmware is commonly stored in non-volatile memory, or memory that does not lose stored data upon the loss of power. In certain embodiments, firmware associated with an information handling system component is stored in non-volatile memory that is accessible to one or more information handling system components. In the same or alternative embodiments, firmware associated with an information handling system component is stored in non-volatile memory that is dedicated to and comprises part of that component.

For the sake of brevity, the word “platform” may be used in this description in lieu of the term “information handling system.”

Throughout this disclosure, a hyphenated form of a reference numeral refers to a specific instance of an element and the un-hyphenated form of the reference numeral refers to the element generically. Thus, for example, “device 12-1” refers to an instance of a device class, which may be referred to collectively as “devices 12” and any one of which may be referred to generically as “a device 12”.

As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication, mechanical communication, including thermal and fluidic communication, thermal, communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

Referring now toFIG. 1, an information handling system100, also referred to herein simply as platform100, in accordance with disclosed subject matter is illustrated.

As depicted inFIG. 1, platform100includes a central processing unit (CPU)101with an integrated graphics processing unit (GPU)110and a system memory105. CPU101is further coupled to a chipset150, which provides interconnects for various peripheral devices and expansion busses including, in the illustrated embodiment, a non-volatile storage resource identified as nonvolatile memory express (NVMe)160, A Wi-Fi radio/antenna/adapter170, a network interface card (NIC)180, an embedded controller190, and a flash memory resource identified as BIOS112.

The platform100depicted inFIG. 1further includes an embedded display device120, including a UHD display panel121attached to a timing controller (TCON)122. The embedded display device120ofFIG. 1connects to and communicates with a video source device over DDI130. As depicted inFIG. 1, GPU110is the video source for embedded display device120. The DDI130illustrated inFIG. 1includes a transport132between a source port131integrated within GPU130and a sink port133integrated within TCON122.

The DDI130employed in the depicted platform may be an embedded-specific or embedded-optimized interface. In at least one embodiment, DDI130is compliant with eDP version 1.4a (eDP1.4a) or later. The eDP 1.4a standard defines a main link comprising four unidirectional data lanes, each of which must comply with an 8.1 Gbps transfer rate standard referred to as high bit rate version 3 (HBR3). To ensure adequate signal integrity at display device120for HBR3 and beyond, the illustrated DDI130incorporates a signal repeater135connected between source port131and sink port133. Repeaters suitable for use in the illustrated DDI130include, as non-limiting examples, a PS8463E re-timer and a PS8461E mux/re-timer from Parade Technologies. Other embodiments may employ re-timers from a different vendor, a limiting or linear re-driver, or another suitable type of repeater.

AlthoughFIG. 1illustrates platform100with a particular combination and configuration of components and devices, other embodiments may incorporate numerous variations that will be readily recognized by those of ordinary skill in the field of microprocessor based system design. As an example, althoughFIG. 1illustrates a CPU101with an integrated GPU110, other embodiments may feature a GPU110that is not integrated within CPU101. As another example, although the DDI source port131illustrated inFIG. 1is integrated within GPU11, the DDI source may be integrated within chipset150or may be part of a distinct display controller device in other embodiments.

As suggested in the preceding description, platform110may employ a DDI130supporting one or more embedded-specific features including, as a non-limiting example, a fast link configuration feature. The flow diagram ofFIG. 2illustrates a conventional fast link configuration method200. The illustrated fast link configuration method200begins with the display device in a low or no power state (block202) including, for purposes of illustration, the S3 power state in a Microsoft Windows environment. The display device remains in the low/no power state until a trigger signal is generated (block204) in response to an event and the trigger signal indicates the display device is transitioning from the low/no power state to a working state such as the S0 state in a Microsoft Windows environment. Upon detecting the trigger signal at block204, the illustrated method200determines (block210) what type of event resulted in the trigger signal. In at least some embodiments, the platform distinguishes between two event types, namely, a power on event and a resume power event. As suggested by its name, a power on event may occur when the device is in a powered off state and a power switch, button, or other form of actuator is pressed, engaged, or otherwise asserted. A resume power event may refer to any event that transitions the display device from a standby mode to a working mode. Examples may include a keyboard click, mouse click, mouse movement, a wake on LAN (WOL) event, etc. In at least some embodiments, a duration of the trigger signal may distinguish between power on events and resume power events. Other embodiments may distinguish between event types based on other criteria.

If the trigger signal detected in block204is associated with a power on event, the method200illustrated inFIG. 2performs (block212) a full configuration of the DDI. For purposes of this disclosure, a full configuration includes a determination of one or more of the sink device's capabilities including the data transfer rates, also known as link rates, supported by the sink device. In eBD-compliant embodiments, the source device may learn the sink device's supported link rates by reading from one or more specifically designated DisplayPort Configuration Data (DPCD) registers. After determining the applicable capabilities of the sink device, the full configuration operation of block212may then access a different DPCD register to set the source device's link rate.

If the platform determines in block210that the trigger signal is associated with a resume power event, the illustrated method200may perform (block214) a fast configuration of the DDI. In at least some implementations, the fast configuration in block214may omit a determination of the sink device's capabilities before setting the link rate.

Following the applicable DDI configuration, method200may proceeds to a working state during which the platform may display (block220) content corresponding to video data received through DDI130and the platform may remain in this state until the display device is powered off or put to sleep following an explicit interrupt or based on a timeout condition wherein no video content has been delivered to the sink for some specified duration.

Unfortunately, the fast configuration of block214may result in an improperly configured DDI that fails to display video content properly. As an example, if the DDI includes a re-timer or another type of repeater device, such as the repeater135illustrated inFIG. 1, repeater135may monitor or “snoop” configuration transactions executed by the one or both of the interface endpoints to determine settings required for the configuration of the repeater itself. If the applicable embedded-optimized DDI standard does not mandate a determination of the sink's capabilities following a resume power event, there may be no configuration transaction for the repeater to snoop and this can result in a repeater configuration that is incompatible with the configuration of one or both endpoints.

Referring now toFIG. 3, a flow diagram for a DDI configuration method referred to herein as modified fast configuration method300is illustrated. The illustrated method300begins, like method200ofFIG. 2begins, with the embedded display device in a low or no power state at block302, where the display device remains until a trigger signal indicating (block304) that the display device power state is transiting to a working state, e.g., a Microsoft Windows S0 state. In at least one eDP-based embodiment of method300, the HPD signal generated by each eDP-compliant embedded display device is leveraged for use as the trigger signal. Method300may then determine (block310) whether the trigger signal indicates a resume power event or a power on event. Again, as discussed above regardingFIG. 2, platform100may, in eDP-compatible implementations, recognize two different types of HPD triggers including a short HPD trigger corresponding to a resume power event and a long HPD trigger corresponding to a power on event.

If the platform determines that the trigger signal detected in box304corresponds to a power on signal, the illustrated performs a full configuration (block312). The full configuration illustrated inFIG. 3includes detecting (block320) sink device capabilities, setting (block322) the link rate and configuring (block324) the repeater in accordance with the sink capabilities detected in block322. The detecting of sink device capabilities in block322may include reading certain predetermined DPCD registers. In at least some implementations, the DPCD registers read during operation320include DPCD registers 0x00010 through 0x0001F.

If the trigger detected in block304corresponds to a resume power event, the illustrated method300performs modified fast link operations314. The modified fast link operations illustrated inFIG. 3include waking (block330) repeater135. In an embodiment illustrated inFIG. 4and described in more detail below, the HPD signal, which is routed to repeater135, is used to wake up repeater135. The HPD signal is also routed to an embedded controller, which is coupled to repeater135. In at least one embodiment, the embedded controller and the repeater are both connected to a system management (SM) bus and, in response to the HPD signal being asserted, the embedded control is configured to write (block332) values into the repeater's link rate DPCD registers, e.g., at 0x0010 through 0x001F. After the repeater's DPCD registers have been written, the link rate may be set (block334).

Following the configuration of the repeater through either the full configuration operations312or the modified fast link operations314, the illustrated method300displays available content (block340) until the display device is powered off or goes to sleep (block342), at which point, method300returns to the low/no power state of block302.

FIG. 4illustrates an eDP-based example configuration for carrying out the method300illustrated inFIG. 3. As depicted, the DDI130includes a unidirectional main link401and a bidirectional auxiliary channel402extending from source port131to sink port133. The repeater135ofFIG. 1has been implemented, inFIG. 4, with a re-timer405. Re-timers may provide wider bandwidth and better quality than a re-driver or another type of repeater. The HDP signal403generated by UHD panel121and delivered to source port131is also routed to embedded controller190. A bus404, to which embedded controller190and re-timer405are both connected, enables embedded controller190to write data into configuration registers, e.g., DPCD registers, of re-timer405. In at least one embodiment, bus404is implemented as an SM bus or another type of I2C bus.