Integrated circuit die having a split solder pad

An integrated circuit die having at least two bond pads, a redistribution layer, the redistribution layer including at least one solder pad including comprising two portions arranged to enable an electrical connection between each other by a same solder ball placed on the solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad at least two redistribution wires, each one connecting one of the two portions to one of the two bond pads, a first bond pad connected via a first redistribution wire to a first portion of the solder pad being dedicated to digital ground and a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to analog ground.

This application claims priority from European patent application No. 16184545.8 filed Aug. 17, 2016, the entire disclosure of which is hereby incorporated herein by reference.

FIELD OF THE INVENTION

The invention relates to a pad for a solder ball, called solder pad, in a redistribution layer of an integrated circuit die.

BACKGROUND OF THE INVENTION

An integrated circuit (IC) die (also called chip) is classically put into a protective package acting as a mechanical interface between said integrated circuit die and a printed circuit board (PCB). A very large number of different types of package exist, which are basically separated into two main techniques.

In the traditional wire-bond packaging technique, illustrated inFIGS. 1 and 2, an integrated circuit die10is placed into a protective package12and bond pads9of said integrated circuit die10are connected to pins11of said protective package12via tiny bond wires13. These pins11are in turn connected to tracks14of a printed circuit board15.

In the more recent flip-chip technique, illustrated inFIG. 3, the integrated circuit die10is directly connected to the printed circuit board15via solder balls16(or solder bumps). In this technique, solder balls16are placed onto solder pads17of the integrated circuit die10. Then, the integrated circuit die10is flipped and placed onto the printed circuit board15, the solder balls establishing electrical connections between the solder pads17and the tracks14. As can be seen inFIG. 4, such an integrated circuit die10comprises an extra metal layer, called redistribution layer (RDL). The redistribution layer comprises redistribution wires18connecting the solder pads17to the input/output bond pads14of the integrated circuit die10. As it is classically practiced, two bond pads20,21are dedicated to the digital ground (VSS) and the analog ground (AVSS). Inconveniently, the digital ground is particularly noisy because of the high frequency content of digital signals.

Thus, in a mixed digital/analog radiofrequency (RF) integrated circuit packaged with the flip-chip technique, in order to keep the noise from transferring from the noisy digital ground to the analog ground while minimizing the number of solder balls used, a same solder pad19is connected to both the VSS bond pad20and the AVSS bond pad21via two RDL wires22,23. When a solder ball30(cf. FIG.5) is placed onto the solder pad19and grounded via a printed circuit board track24, the AVSS bond pad21is isolated from the VSS bond pad20at high (radio) frequencies, for instance at 2.4 GHz. It is to be noted that the isolation does not work at low frequencies. This is because each wire22,23has an inductance in the order or a few nano-Henry, which is an important value at Giga-Hertz but would be equivalent to a short at low frequencies.

FIG. 5shows an example of such a case. As it can be seen, the integrated circuit die10comprises a bond pad25constituting an input for a signal received by an antenna26. The antenna26is electrically connected to a track27of the printed circuit board15, and said track27is electrically connected to the antenna input25via a solder ball28. A low-noise amplifier (LNA)29is included on the integrated circuit die10, so as to amplify the antenna signal. More specifically, a positive terminal of the LNA29is connected to the antenna bond pad25, and a negative terminal of the LNA29is connected to the AVSS bond pad21. Thanks to the isolation of the AVSS bond pad21from the VSS bond pad20(chip-grounded) via the solder ball30, only the antenna signal is amplified by the LNA29, not the noise from the digital ground.

To serve a multitude of applications, integrated circuits may be designed for both flip-chip and wire-bond packaging techniques. However, using the integrated circuit die of FIG.4with a wire-bond package may be problematic. For instance, FIG.6shows the integrated circuit die10of FIG.5packaged with a wire-bond technique. In this case, noise isolation is performed via two bond-wires31,32that connect the AVSS bond pad21and the VSS bond pad20to the track27(grounded) of the printed circuit board15. It is inconvenient that this isolation is degraded by the RDL wires22,23that connect the VSS bond pad20and the AVSS bond pad21, since noise may be transmitted from the VSS bond pad20to the AVSS bond pad21through these RDL wires22,23.

SUMMARY OF THE INVENTION

Therefore, it is challenging to offer an integrated circuit die that may be used with both flip-chip and wire-bond packaging techniques while saving solder balls and enabling a good noise isolation between the AVSS and the VSS bond pads.

Hence, the invention relates to an integrated circuit die as defined in claim1.

If the VSS bond pad is connected to the first portion, and the AVSS bond pad is connected to the second portion, the VSS bond pad and the AVSS bond pad are only in electrical contact with each other when a solder ball is placed onto the solder pad. As a result, with a traditional wire-bond package, there is no risk to transmit noise from the VSS to the AVSS bond pad.

In an embodiment, the solder pad is made of two demi-disks.

The invention also relates to an electronic system as defined in claim3.

The invention also relates to an electronic system as defined in claim4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 7shows an integrated circuit die10′ similar to the integrated circuit die10ofFIG. 4, with the difference that the solder pad19′ linked to the VSS bond pad20and the AVSS bond pad21via the redistribution wires22,23is split in half. More precisely, the solder pad19′ comprises a first portion33and a second portion34facing each other, each having a shape of a demi-disk. The first portion33is connected to the VSS bond pad20via the redistribution wire22, and the second portion34is connected to the AVSS bond pad21via the redistribution wire23. When no solder ball is placed onto the solder pad19′, the first portion33and the second portion34are not in electrical contact with each other. However, when a solder ball is placed onto the solder pad19′, the first portion33and the second portion34become in electrical contact with each other.

The key feature of the invention is that the electrical connections between the bond pads linked to the different portions are different depending on whether a solder ball is placed on the solder pad19′ or not. As a consequence, as illustrated inFIG. 8, when the die10′ is packaged with wire-bonds and used in the circuit previously detailed in reference toFIG. 6, there is no electrical connection between the AVSS bond pad21and the VSS bond pad20via the redistribution layer, hence no noise transmission from the digital ground to the analog ground.

Naturally, the portions33,34may have another shape or be laid out differently on the die10′, as long as a single solder ball can establish an electrical contact between them.