Varactor device with backside contact

An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.

The present disclosure is generally related to variable capacitor (varactor) devices.

II. DESCRIPTION OF RELATED ART

Advances in technology have resulted in smaller and more powerful computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless telephones such as mobile and smart phones, tablets and laptop computers that are small, lightweight, and easily carried by users. These devices can communicate voice and data packets over wireless networks. Further, many such devices incorporate additional functionality such as a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such devices can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these devices can include significant computing capabilities.

Wireless telephones and other electronic devices may include passive components, such as inductors, resistors, and capacitors, which may facilitate transmission and reception of signals in a network. The passive components may be configured to perform functions including tuning, filtering, impedance matching, and gain control. To illustrate, a transceiver of an electronic device may include a variable capacitor (varactor). The electronic device may adjust a capacitance of the varactor to tune the transceiver to receive and transmit signals associated with a particular frequency band. In some implementations, operation of a varactor may deviate substantially from “ideal” varactor behavior, which may reduce performance of the transceiver. For example, capacitance of a varactor may change non-linearity with respect to a time-varying input voltage from the bias of the varactor set by a direct current (DC) bias voltage. In this case, capacitance of the varactor may be imprecisely controlled, which may reduce device performance (e.g., due to increased current dissipation caused by poor tuning of the varactor, or increased non-linearity to distort signal).

A varactor device may include a first contact positioned on a front side of a substrate and a second contact (e.g., a backside contact) positioned on a backside of the substrate. Use of the backside contact may reduce an impedance associated with the varactor device, which may improve device signal loss and operation. To illustrate, a radio frequency (RF) signal may be conducted via a signal path between the first contact and the second contact, and the signal path may have a shorter length (and less impedance) as compared to an RF signal path of a varactor that uses two front-side contacts through semiconductor material. Thus, use of the backside contact may reduce attenuation of the RF signal. In a particular embodiment, the varactor device is integrated within a transceiver.

The varactor device may further include a third contact and a fourth contact. The third contact and the fourth contact may be responsive to a bias voltage to change a size of one or more depletion regions of the varactor device. By changing the size of a depletion region, a width of the signal path of the varactor device may be changed, enabling control of the capacitance of the varactor. In this example, a width of a “plate” of a capacitive region of the varactor device may be adjusted, which may enable more precise capacitance control as compared to a device that adjusts only a distance between “plates” of a capacitive region.

In addition, the RF signal and the bias voltage may be separately applied to the varactor device using the first contact, the third contact, and the fourth contact. For example, instead of applying both an RF signal and a bias voltage to a single pair of contacts, the RF signal may be applied to the first contact, and the bias voltage may be applied to the third contact and to the fourth contact. Separately applying an RF signal and a bias voltage may improve response linearity as compared to a two-port varactor device that applies both an RF signal and a bias voltage to a single pair contacts. For example, use of the third contact and the fourth contact may enable more precise biasing control by avoiding “mixing” of an RF signal and a bias voltage (which can cause nonlinearity of device operation).

In a particular embodiment, an apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.

In another particular embodiment, a method includes providing a signal to a first contact of a varactor device. The first contact is located on a first side of a substrate. The method further includes conducting the signal through a signal path between the first contact and a second contact of the varactor device. The second contact is located on a second side of the substrate, and the second side is opposite the first side.

In another particular embodiment, an apparatus includes means for providing a first signal to a capacitive region of a varactor device. The means for providing the first signal is located on a first side of a substrate. The apparatus further includes means for receiving a second signal from the capacitive region. The means for receiving the second signal is located on a second side of the substrate, and the second side is opposite the first side.

In another particular embodiment, a computer-readable medium stores instructions that are executable by a processor to initiate operations. The operations include forming a first contact of a varactor device. The first contact is located on a first side of a substrate. The operations further include forming a second contact of the varactor device. The second contact is located on a second side of the substrate, and the second side is opposite the first side. A signal path of the varactor device is located between the first contact and the second contact.

One particular advantage provided by at least one of the disclosed embodiments is reduced RF signal attenuation at a varactor device. For example, use of a backside contact may reduce a length of a signal path between contacts of the varactor device, thus reducing impedance and signal loss. Another particular advantage provided by at least one of the disclosed embodiments is reduced contact resistance. For example, a high-conductivity material of the backside contact may reduce contact resistance. Another particular advantage provided by at least one of the disclosed embodiments is enhanced linearity of response to a bias voltage. For example, by changing a size of a depletion region of the varactor device, capacitance of the varactor device may be controlled more accurately (and more linearly) as compared to other varactors. Other aspects, advantages, and features of the present disclosure will be described or become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.

V. DETAILED DESCRIPTION

Particular examples are described below with reference to the drawings. Similar or common features are designated by common reference numbers throughout the description and the drawings.

Referring toFIG. 1, a particular illustrative embodiment of a variable capacitor (varactor) device is depicted and generally designated100. The varactor device100may be integrated within an electronic device, such as within a transceiver, as an illustrative example. To further illustrate, the transceiver (e.g., a receiver front-end of the transceiver) may include one or more varactor devices corresponding to the varactor device100. The transceiver may utilize the one or more varactor devices to tune to receive and transmit one or more signals that are conveyed using a particular frequency or frequency band. In this example, the one or more varactors may have a frequency response that filters received signals, such as by suppressing or reducing certain low-frequency signal components.

The varactor device100includes a first contact102, a second contact104, a third contact122, and a fourth contact124. The varactor device100further includes a substrate105, a dielectric material110(e.g., a gate oxide material, such as a silicon dioxide material), and a buried oxide (BOX) layer118. Depending on the particular fabrication process, the varactor device100may include a support layer, such as a “handle” silicon layer120(e.g., a bulk silicon layer). The substrate105may be a silicon substrate, a glass substrate, or a silicon-on-insulator substrate, as illustrative examples. In the example ofFIG. 1, the substrate105, the BOX layer118, and the handle silicon layer120may form a silicon-on-insulator (SOI) structure. Depending on the particular fabrication process, the handle silicon layer120may be removed or substantially removed from the varactor device100during fabrication of the varactor device100(e.g., using an etch process or a grinding process).

The substrate105includes a first side (e.g., a front-side) and a second side (e.g., a backside). For example, a first surface126of the substrate105may define the first side, and a second surface of the substrate105may define the second side. InFIG. 1, the first contact102, the third contact122, and the fourth contact124are located on the first side of the substrate105, and the second contact104is located on the second side of the substrate105. The first side is opposite to the second side. AlthoughFIG. 1illustrates that the third contact122is located on the first side of the substrate105, it is noted that in another implementation the contacts104,122may both be placed on the second side of the substrate105.

The substrate105may include a signal path112that is configured to conduct signals from the first port132and the first contact102to the second contact104and the second port134. The first contact102, the dielectric material110, and the signal path112may form a capacitive region140.

The substrate105may have a complementary metal-oxide-semiconductor (CMOS) configuration that includes doped regions. To illustrate, the substrate105may include a first highly doped region106and a second highly doped region108. In a particular implementation, the first highly doped region106is an n-type region that includes one or more n-type materials (e.g., n+ materials), and the second highly doped region108is a p-type region that includes one or more p-type materials (e.g., p+ materials). In another example, both the first highly doped region106and the second highly doped region108are n-type regions that include one or more n-type materials (e.g., n+ materials), such as described further with reference toFIG. 2.

The varactor device100may be implemented as a CMOS device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET) type device. For example, the first highly doped region106may correspond to a drain terminal of the MOSFET type device, and the second highly doped region108may correspond to a source terminal of the MOSFET type device. The dielectric material110and the first contact102may correspond to a gate terminal (or “gate stack”) of the MOSFET type device. Alternatively, the varactor device100may be implemented using one or more other materials and/or processes.

During operation, a signal150may be applied to the first port132(e.g., from another device via a connection not shown inFIG. 1). The signal150may be a radio frequency (RF) signal. The signal150may be an alternating current (AC) signal. The signal150may be applied to the signal path112of the varactor device100via the first contact102and the dielectric material110. For example, the ports132,134may be AC coupled via the capacitive region140. Application of the signal150may create a depletion region114(e.g., an insulating region that is substantially free of charge carriers) within the substrate105due to a charge carrier diffusion effect.

A capacitance of the capacitive region140may be changed using one or more control signals, such as using a bias voltage152(e.g., a DC signal). For example, a size of the depletion region114may be adjusted using the bias voltage152, which may change the capacitance of the capacitive region140. To further illustrate, the first contact102may correspond to a first charge accumulation region (or a first “plate”) of the capacitive region140, and the signal path112may correspond to a second “plate” of the capacitive region140. The first plate and the second plate are separated by the dielectric material110. By adjusting the bias voltage152, a width of the depletion region114may be increased or decreased. In this case, a plate area of the second plate is changed, which modifies capacitance of the capacitive region140(because the capacitance is proportional to the plate area). As used herein, “width” of the depletion region114may refer to a horizontal extent of the depletion region114relative to the orientation ofFIG. 1(e.g., an extent between the first highly doped region106and the signal path112). As used herein, “height” of the depletion region114may refer to a vertical extent of the depletion region114relative to the orientation ofFIG. 1(e.g., an extent between the dielectric material110and the BOX layer118).

The capacitive region140may filter the signal150to generate a signal154. For example, the capacitive region140may filter out certain frequency components of the signal150to generate the signal154, such as by filtering out a direct current (DC) frequency component of the signal150.

Depending on the particular implementation, the fourth contact124may be biased using a second bias voltage (not shown) that is different than the bias voltage152. In some implementations, the fourth contact124may be coupled to a ground node via the fourth port138. In another example, the fourth contact124is biased using the bias voltage152. For example, the contacts122,124may be connected via a common node, such as described further with reference toFIG. 2.

FIG. 1illustrates that a varactor device100may have a four-port configuration. The four-port configuration may improve response linearity during operation. For example, by applying the signal150and the bias voltage152to different ports, “mixing” of the signal150and the bias voltage152is reduced or avoided. In a device that “mixes” the signal150and the bias voltage152, the signal150may occasionally have a large magnitude that “overrides” the bias voltage152, resulting in a nonlinear effect in some cases.FIG. 1illustrates that a nonlinear effect can be mitigated or avoided using a multi-port configuration, thus improving response linearity of the varactor device100and increasing a quality metric (e.g., Q-factor) associated with the varactor device100.

Further, adjusting the width of the depletion region114may improve device performance as compared to a device that modulates a “plate distance” between capacitive regions. To illustrate, a device may change a height of a depletion region that forms beneath a dielectric. In this example, the width of the depletion region and a width of the dielectric may be substantially “fixed,” and the device may change a height of the depletion region to adjust capacitance of the capacitive region. Changing the height of the depletion region in this manner may increase capacitance by modifying a “plate distance” associated with the capacitive region (because capacitance is inversely proportional to plate distance) and may also increase impedance of the signal path. Thus, a resistance-capacitance (RC) product associated with the device may vary. The varactor device100ofFIG. 1may achieve a stable RC product using an “area-tuning” technique. For example, by increasing the width of the depletion region114(and decreasing “plate” area), capacitance of the varactor device is decreased, while impedance of the signal path112is increased (by reducing a channel width of the signal path112). As a result, an RC product of the varactor device100may remain substantially constant during operation of the varactor device100, which may improve device performance (e.g., by increasing response linearity).

Referring toFIG. 2, a particular illustrative embodiment of the varactor device100ofFIG. 1is depicted and generally designated200. In the example ofFIG. 2, the varactor device200includes a node202connecting the third contact122and the fourth contact124. The third contact122and the fourth contact124may be responsive to the bias voltage152via the node202. The varactor device200may include a capacitive region240formed by the first contact102, the dielectric material110, and a signal path212. In the example ofFIG. 2, each of the highly doped regions106,108may correspond to n-type regions that include one or more n-type materials (e.g., n+ materials).

During operation, a width of the signal path212is defined by the depletion region114and by a depletion region214. For example, by controlling the bias voltage152, widths of the depletion regions114,214can be adjusted. Adjusting widths of the depletion regions114,214changes capacitance of the capacitive region240. During operation, the signal150may be “filtered” based on the capacitance to generate the signal154.

The example ofFIG. 2illustrates that a varactor device200may include multiple depletion regions. Widths of the depletion regions can be controlled to adjust a capacitance of the varactor device, which may enable greater capacitance tuning (e.g., a greater range of capacitance values).

Referring toFIG. 3, a particular illustrative embodiment of a method is depicted and generally designated300. The method300may be performed at a varactor device, such as at the varactor device100ofFIG. 1and/or the varactor device200ofFIG. 2.

The method300includes providing a signal to a first contact of the varactor device, at302. The first contact is located on a first side of a substrate. As an example, the signal may correspond to the signal150, and the first contact may correspond to the first contact102. The substrate may correspond to the substrate105, and the first side may correspond to a front-side of the substrate105.

The method300further includes conducting the signal through a signal path between the first contact and a second contact of the varactor device, at304. The second contact is located on a second side of the substrate, and the second side is opposite the first side. As an example, the signal path may correspond to the signal path112, and the second contact may correspond to the second contact104.

In a particular embodiment, the signal (e.g., the signal150) is an RF signal. The method300may further include generating a filtered RF signal at the second contact. The filtered RF signal may correspond to the signal154.

Conducting the signal may include filtering the signal based on a capacitance associated with the varactor device. To illustrate, the capacitance of the capacitive region140or the capacitance of the capacitive region240may be based on a width of the depletion region114. In this example, the method300may further include biasing the third contact using a bias voltage (e.g., the bias voltage152) to adjust the width of the depletion region114(which may occur prior to providing the signal to the first contact and/or while the signal is provided to the first contact).

In some implementations, the method300may further include biasing a fourth contact of the varactor device using the bias voltage to adjust a width of a second depletion region. The fourth contact may correspond to the fourth contact124, and the second depletion region may correspond to the depletion region214. In this case, the capacitance of the capacitive region240is based further on the width of the depletion region214.

In an illustrative embodiment, the method300is performed at a mobile device that includes the varactor device. In this case, the method300may include receiving the signal via a communication network using an antenna of the mobile device (prior to providing the signal to the first contact). An illustrative mobile device is described further with reference toFIG. 5.

The method300ofFIG. 3enables improved operation of a varactor device. For example, by providing a signal to a signal path between contacts of the varactor device on opposite sides of a substrate, impedance is reduced. In this case, a length of the signal path112ofFIG. 1may have less impedance as compared to another varactor device. Thus, signal attenuation is reduced, which may enhance signal quality and enable better reception of signals within a communication network, as an illustrative example. Further, use of separate contacts (e.g., the first contact102and the third contact122ofFIG. 1) for a signal and a bias voltage may improve bias control and linearity of device response.

Referring toFIG. 4, a particular illustrative embodiment of a method of fabricating a varactor device is depicted and generally designated400. The varactor device may correspond to the varactor device100ofFIG. 1and/or the varactor device200ofFIG. 2.

The method400includes initiating a front-end of line (FEOL) process associated with a silicon-on-insulator (SOI) structure, at402. The SOI structure includes a substrate (e.g., the substrate105), a buried oxide (BOX) layer (e.g., the BOX layer118), and a handle silicon layer (e.g., the handle silicon layer120).

The method400further includes forming a dielectric material on the substrate, at404. For example, the dielectric material110may be formed on the substrate105using an oxide growth process, as an illustrative example.

The method400further includes forming a first contact of a varactor device, at406. The first contact is located on the first side (e.g., a front side) of the substrate. As an example, the first contact may correspond to the first contact102.

The method400further includes initiating a back-end of line (BEOL) process associated with the SOI structure, at408. For example, BEOL operations may be initiated after FEOL operations that include forming transistors and other circuitry.

Prior to initiating the BEOL process, a passivation layer may be applied to a front-side of the SOI structure. The passivation layer may comprise a spin-on material or a deposited material, such as an oxide or boron phosphorous-doped silicate glass (BPSG). The passivation layer may provide electrical and mechanical protection to front-side components during the BEOL process. The passivation layer may include silicon oxide, silicon nitride, or polyimide, as illustrative examples.

The method400further includes bonding a support material at a first side of the substrate, at410. The support material may include a front-side wafer, such as a front-side handle wafer or substrate. The support material may enable rotation of the SOI structure, such as in order to expose a backside of the SOI structure. For example, fabrication equipment of a fabrication system may rotate the SOI structure using the support material, which may enable backside fabrication processes.

The method400further includes removing the handle silicon layer of the SOI structure, at412. The handle silicon layer may be removed using an etch process or a grinding process, as illustrative examples. In an illustrative implementation, the BOX layer118is etch resistant to a first etch process used to etch the handle silicon layer120. In this case, the BOX layer118may function as an etch stop during removal of the handle silicon layer120.

The method400further includes etching the BOX layer, at414. Etching the BOX layer defines a region, such as an etched region in which a contact is to be formed. The BOX layer may be etched using a second etch process (e.g., a wet etch process or a dry etch process) that is different than the first etch process. In an alternate embodiment, a backside photolithography process may be applied to the BOX layer to define the region.

The method400further includes forming a second contact of the varactor device (e.g., within the region), at416. The second contact is located on a second side (e.g., a backside) of the substrate, and the second side is opposite the first side. A signal path (e.g., the signal path112) of the varactor device is located between the first contact and the second contact. The signal path may include a portion of the substrate (e.g., a silicon portion, which may include a p-type material).

After forming the second contact, the method400may optionally include removing the support material, such as using an etch process or a grinding process. For example, the SOI structure may be re-rotated to expose the front-side of the SOI structure, and the support material may be removed using an etch process or a grinding process. After removing the support material, one or more other components of the varactor devices100,200may be formed (e.g., the contacts122,124). In other embodiments, the one or more components may be formed during the FEOL process (e.g., the contacts122,124may be formed prior to initiating the BEOL process).

The method400enables efficient fabrication of a varactor device that includes a backside contact. For example, the method400may be performed using relatively inexpensive SOI and/or CMOS materials and processes. Further, a varactor device formed using the method400may exhibit improved operation, such as via reduced signal path impedance between a front-side contact and a backside contact of the varactor device.

One or more operations of the method400may be initiated, controlled, or performed by an electronic device. The electronic device may include a field-programmable gate array (FPGA) device, an application-specific integrated circuit (ASIC), a processing unit such as a central processing unit (CPU), a digital signal processor (DSP), a controller, another hardware device, a firmware device, or any combination thereof. In a particular embodiment, a computer-readable medium stores instructions that are executable by a processor to initiate the operations of the method400.

Referring toFIG. 5, a particular illustrative embodiment of a device is depicted and generally designated500. In a particular embodiment, the device500is a mobile device that operates to communicate via a wireless communication network.

The device500includes a processor510, such as a digital signal processor (DSP). The processor510is coupled to a memory532. The processor510may read and write instructions566and/or data568at the memory532. For example, the processor510may store the instructions566and/or the data568at the memory532. As another example, the processor510may access the instructions566and/or the data568from the memory532.

FIG. 5also shows a display controller526that is coupled to the processor510and to a display528. A coder/decoder (CODEC)534can also be coupled to the processor510. A speaker536and a microphone538can be coupled to the CODEC534.

The device500may include a radio frequency (RF) interface590. The RF interface590may be connected to an antenna542and to the processor510. The RF interface590includes a varactor device592that includes a backside contact (and at least one front-side contact). The varactor device592may correspond to one or both of the varactor devices100,200, and the backside contact may correspond to the second contact104.

In a particular embodiment, the processor510, the display controller526, the memory532, the CODEC534, and the RF interface590are included in a system-in-package or system-on-chip device522. In a particular embodiment, an input device530and a power supply544are coupled to the system-on-chip device522. Moreover, in a particular embodiment, as illustrated inFIG. 5, the display528, the input device530, the speaker536, the microphone538, the antenna542, and the power supply544are external to the system-on-chip device522. However, each of the display528, the input device530, the speaker536, the microphone538, the antenna542, and the power supply544can be coupled to a component of the system-on-chip device522, such as to an interface or to a controller.

In a particular embodiment, the varactor device592is integrated within a front-end of a transceiver of the RF interface590. For example, a capacitance of the varactor device592may be adjusted in order to tune to a particular frequency (or frequency band) in order to receive or transmit a signal594using the particular frequency (or frequency band). The signal150may be based on the signal594. For example, the signal594may be processed by the RF interface590(e.g., by amplifying the signal594at a power amplifier stage of the RF interface590) to generate the signal150. The instructions566may be executable by the processor510to cause the RF interface590to tune to receive signals via the frequency (or frequency band) using the varactor device592. Alternatively or in addition, a varactor device described herein may be integrated within another component or device, such as within the CODEC534, the power supply544, or a transmitter of the RF interface590, as illustrative examples. For example, a varactor device may be used as a filter device of the CODEC534, the power supply544, or a transmitter of the RF interface590(e.g., to filter high-frequency “noise” signal components). In these examples, device operation may be improved by improving linearity of device response using one or more techniques described herein.

In connection with embodiments described herein, an apparatus includes means (e.g., the first contact102) for providing a first signal (e.g., the signal150) to a capacitive region (e.g., the capacitive region140) of a varactor device (e.g., any of the varactor devices100,200, and592). The means for providing the first signal is located on a first side of a substrate (e.g., the substrate105). The apparatus further includes means (e.g., the second contact104) for receiving a second signal (e.g., the signal154) from the capacitive region. The means for receiving the second signal is located on a second side of the substrate, and the second side is opposite the first side. In an illustrative embodiment, the apparatus further includes means (e.g., the third contact122and/or the fourth contact124) for biasing the varactor device using a bias voltage (e.g., the bias voltage152).

The foregoing disclosed devices and functionalities described with respect toFIGS. 1-5may be designed and configured into computer files (e.g. RTL, GDSII, GERBER, etc.) stored on computer readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into dies and packaged into chips. The chips can then be employed in devices, such as devices within the electronic device500ofFIG. 5.FIG. 6depicts a particular illustrative embodiment of an electronic device manufacturing process600.

Referring toFIG. 6, physical device information602is received at the manufacturing process600, such as at a research computer606. The physical device information602may include design information specifying a varactor device that includes a backside contact. The varactor device may correspond to any of the varactor devices100,200, and592, and the backside contact may correspond to the second contact104.

The physical device information602may indicate one or more physical parameters, material characteristics, and structure information entered via a user interface604coupled to the research computer606. The research computer606includes a processor608, such as one or more processing cores, coupled to a computer readable medium, such as a memory610. The memory610may store computer readable instructions that are executable to cause the processor608to transform the physical device information602to comply with a file format and to generate a library file612.

In a particular embodiment, the library file612includes at least one data file including the transformed design information. For example, the library file612may specify a library of semiconductor devices including a varactor device that includes a backside contact. The varactor device may correspond to any of the varactor devices100,200, and592, and the backside contact may correspond to the second contact104.

The library file612may be used in conjunction with the EDA tool620at a design computer614. The design computer614includes a processor616(e.g., one or more processing cores) coupled to a memory618. The EDA tool620may include processor executable instructions stored at the memory618to enable a user of the design computer614to design a circuit including one or more of the varactor devices100,200, and592. For example, a user of the design computer614may enter circuit design information622via a user interface624coupled to the design computer614. The circuit design information622may include design information representing at least one physical property of one or more of the varactor devices100,200, and592. To illustrate, the circuit design information622may identify particular circuits and relationships to other elements in a circuit design, positioning information, feature size information, interconnection information, or other information representing a physical property of a device (e.g., a semiconductor device).

The design computer614may be configured to transform the design information (including the circuit design information622) to comply with a file format. To illustrate, the file format may include a database binary file format representing planar geometric shapes, text labels, and other information related to a circuit layout in a hierarchical format, such as a Graphic Data System (GDSII) file format. The design computer614may be configured to generate a data file including the transformed design information, such as a GDSII file626. The GDSII file626may include information describing a varactor device that includes a backside contact (in addition to other circuits or information). The varactor device may correspond to any of the varactor devices100,200, and592, and the backside contact may correspond to the second contact104.

The GDSII file626may be received at a fabrication process628to manufacture any of the varactor devices100,200, and592according to transformed information in the GDSII file626. For example, a device manufacture process may include providing the GDSII file626to a mask manufacturer630to create one or more masks, such as masks to be used with photolithography processing, illustrated as a representative mask632. The mask632may be used during the fabrication process to generate one or more wafers634, which may be tested and separated into dies, such as a representative die636. The die636includes a circuit having any of the varactor devices100,200, and592.

To further illustrate, a processor634and a memory635may initiate and/or control the fabrication process628. The memory635may include instructions, such as computer-readable instructions or processor-readable instructions. The instructions may be executable by a processor, such as the processor634. The instructions may be executable by the processor634to initiate operations of the method400ofFIG. 4. In a particular embodiment, the instructions are executable by the processor634to perform operations including forming a first contact (e.g., the first contact102) of a varactor device (e.g., any of the varactor devices100,200, and592). The first contact is located on a first side of a substrate (e.g., the substrate105). The operations further include forming a second contact (e.g., the second contact104) of the varactor device. The second contact is located on a second side of the substrate, and the second side is opposite the first side. A signal path (e.g., the signal path112or the signal path212) of the varactor device is located between the first contact and the second contact.

The fabrication process628may be implemented by a fabrication system that is fully automated or partially automated. For example, the fabrication process628may be automated according to a schedule. The fabrication system may include fabrication equipment (e.g., processing tools) to perform one or more operations to form a device. For example, the fabrication equipment may be configured to deposit one or more materials, epitaxially grow one or more materials, conformally deposit one or more materials, apply a hardmask, apply an etching mask, perform etching, perform planarization, and/or perform a wafer cleaning process, etc.

The fabrication system may have a distributed architecture (e.g., a hierarchy). For example, the fabrication system may include one or more processors, such as the processor634, one or more memories, such as the memory635, and/or one or more controllers that are distributed according to the distributed architecture. The distributed architecture may include a high-level processor that controls or initiates operations of one or more low-level systems. For example, a high-level processor may include one or more processors, such as the processor634, and the low-level systems may each include or may be controlled by one or more corresponding controllers. A particular controller of a particular low-level system may receive one or more instructions (e.g., commands) from a particular high-level system, may issue sub-commands to subordinate modules or process tools, and may communicate status data back to the particular high-level system. Each of the one or more low-level systems may be associated with one or more corresponding pieces of fabrication equipment (e.g., processing tools). In a particular embodiment, the fabrication system may include multiple processors that are distributed in the fabrication system. For example, a controller of a low-level system component may include a processor, such as the processor634.

Alternatively, the processor634may be a part of a high-level system, subsystem, or component of the fabrication system. In another embodiment, the processor634initiates or controls distributed processing operations associated with multiple levels and components of a fabrication system.

Thus, the processor634may access processor-executable instructions that, when executed by the processor634, cause the processor634to initiate or control formation of a device. The device may include one or more materials formed using one or more doping tools, such as a molecular beam epitaxial growth tool, a flowable chemical vapor deposition (FCVD) tool, a conformal deposition tool, and/or a spin-on deposition tool. During fabrication of the device, one or more materials may be removed (e.g., etched) from the device using one or more removal tools, such as a chemical removal tool, a reactive gas removal tool, a hydrogen reaction removal tool, a planarization tool, and/or a standard clean 1 type removal tool.

The executable instructions included in the memory635may enable the processor634to initiate or control formation of a device or structure described herein. For example, the executable instructions may enable the processor634to initiate or control formation of the any of the varactor devices100,200, and592.

The die636may be provided to a packaging process638where the die636is incorporated into a representative package640. For example, the package640may include the single die636or multiple dies, such as a system-in-package (SiP) arrangement. The package640may be configured to conform to one or more standards or specifications, such as Joint Electron Device Engineering Council (JEDEC) standards.

Information regarding the package640may be distributed to various product designers, such as via a component library stored at a computer646. The computer646may include a processor648, such as one or more processing cores, coupled to a memory650. A printed circuit board (PCB) tool may be stored as processor executable instructions at the memory650to process PCB design information642received from a user of the computer646via a user interface644. The PCB design information642may include physical positioning information of a packaged device on a circuit board. The packaged device may correspond to the package640, and the package640may include any of the varactor devices100,200, and592.

The computer646may be configured to transform the PCB design information642to generate a data file, such as a GERBER file652, with data that includes physical positioning information of a packaged semiconductor device on a circuit board, as well as layout of electrical connections, such as traces and vias. The packaged semiconductor device may correspond to the package640and may include any of the varactor devices100,200, and592. In other embodiments, the data file generated by the transformed PCB design information may have a format other than a GERBER format.

The GERBER file652may be received at a board assembly process654and may be used to create PCBs, such as a representative PCB656, manufactured in accordance with the design information stored within the GERBER file652. For example, the GERBER file652may be uploaded to one or more machines to perform various steps of a PCB production process. The PCB656may be populated with electronic components including the package640to form a representative printed circuit assembly (PCA)658.

The PCA658may be received at a product manufacture process660and integrated into one or more electronic devices, such as a first representative electronic device662and a second representative electronic device664. As an illustrative, non-limiting example, the first representative electronic device662, the second representative electronic device664, or both, may be selected from the group of a mobile device, a computer, a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), or a fixed location data unit, into which any of the varactor devices100,200, and592may be integrated. As another illustrative, non-limiting example, one or more of the electronic devices662and664may include mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. It should be appreciated that the disclosure is not limited to these illustrated devices.

A device that includes any of the varactor devices100,200, and592may be fabricated, processed, and incorporated into an electronic device, as described in the illustrative process600. One or more aspects of the embodiments described herein may be included at various processing stages, such as within the library file612, the GDSII file626, and the GERBER file652, as well as stored at the memory610of the research computer606, the memory618of the design computer614, the memory650of the computer646, the memory of one or more other computers or processors (not shown) used at the various stages, such as at the board assembly process654. One or more aspects of the embodiments described herein may be incorporated into one or more other physical embodiments such as the mask632, the die636, the package640, the PCA658, other products such as prototype circuits or devices (not shown), or any combination thereof. Although various representative stages of production from a physical device design to a final product are depicted, in other embodiments fewer stages may be used or additional stages may be included. Similarly, the process600may be performed by a single entity or by one or more entities performing various stages of the process600.

A conductive region described herein may include a silicon material (e.g., polycrystalline silicon) or a metal, such as copper (Cu) or aluminum (Al), tungsten (W), or one or more alloys thereof. To illustrate, the first contact102may include polycrystalline silicon or a metal (e.g., tungsten), as illustrative examples. The second contact104may include a metal, such as copper (Cu) or aluminum (Al), which may be deposited or formed during a BEOL process (e.g., instead of a tungsten material that is deposited or formed using a FEOL process). Thus, by forming the second contact104during a BEOL process, the second contact104may include a low-resistivity material (e.g., copper) not typically utilized in connection with a FEOL process. Thus, signal path resistance and signal loss is reduced as compared to a device that forms each varactor contact using a FEOL process. It is noted that one or more materials described herein may include a thin film material that is deposited using a thin film deposition process.

In a particular embodiment and as illustrated in the examples ofFIGS. 1 and 2, the first contact102and the second contact104may be substantially aligned in order to reduce a signal path length. The reduced signal path length may reduce impedance of the signal path, thus lowering signal attenuation. In other applications, the first contact102and the second contact104may be offset or partially offset (e.g., as a result of circuit design parameters, design rules, fabrication process, etc.).

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. For example, one or more operations of the method400ofFIG. 4may be initiated, controlled, or performed using a processor that executes instructions. A software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of non-transient storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a computing device or a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.