Control method and device employing primary side regulation in a quasi-resonant AC/DC flyback converter without analog divider and line-sensing

A primary-side controlled high power factor, low total harmonic distortion, quasi resonant converter converts an AC mains power line input to a DC output for powering a load, such as a string of LEDs. The AC mains power line input is supplied to a transformer that is controlled by a power switch. A device for controlling a power transistor of a power stage includes a shaper circuit including a first current generator configured to output a first current responsive to a bias voltage signal and to generate a reference voltage signal based on the first current. A bias circuit includes a second current generator configured to output a second current responsive to a compensation voltage signal and to generate the bias voltage based on the second current. An error detection circuit includes a third current generator configured to output a third current responsive to the reference voltage signal and to generate the compensation voltage signal based on the third current. A driver circuit has a first input configured to receive the reference voltage signal and having an output configured to drive the power transistor.

BACKGROUND

Technical Field

The present disclosure relates generally to converters and, more particularly, to control devices and methods for quasi-resonant AC/DC flyback converters.

Description of the Related Art

Converters, and particularly offline drivers of light emitting diode (LED) based lamps for bulb replacement, are often desired to have a power factor greater than 0.9, low total harmonic distortion (THD) and safety isolation. At the same time, for cost reasons, it is desirable to regulate the output DC current generated by such a converter as required for proper LED driving without utilizing a closed feedback loop between a primary side and a secondary side of the converter. In this way, a current sensing element, a voltage reference and an error amplifier on the secondary side, as well as an opto-isolator or optocoupler to transfer the generated error signal from the secondary side to a control circuit on the primary side, are no longer required. This is referred to as opto-less regulation. In addition to opto-less regulation, recently considerable emphasis has been given to the total harmonic distortion (THD) of the ac input current caused by such a converter, and in some geographical areas achieving THD<10% is becoming a market requirement.

High-power-factor (high-PF) flyback converters are able to meet power factor and isolation specifications with a simple and inexpensive power stage. In a high-PF flyback converter, like in any high-PF converter topology, there is no energy reservoir capacitor after an input rectifier bridge that receives an AC mains input voltage. Thus, the voltage output from the rectifier bridge, which is the input voltage to the power stage of the converter, is a rectified sinusoid. To achieve a high-PF and low-THD, the input current to the rectifier bridge must be sinusoidal-like and must track the AC mains input voltage supplied to the rectifier bridge, thus originating a time-dependent input-to-output power flow. As a result, the output current from the rectifier bridge contains a large AC component at twice the frequency of the AC mains input voltage.

A quasi-resonant (QR) flyback converter has a power switch turn-on that is synchronized to the instant a transformer of the converter demagnetizes (i.e. the secondary current has become zero), normally after an appropriate delay. This allows the turn-on to occur in the valley of the drain voltage ringing that follows the demagnetization, which is often termed “valley-switching.” Typically, peak current mode control is used, so the turn-off of the power switch is determined by a current sense signal reaching the value programmed into a control loop that regulates the output voltage or current from the converter.

In markets such as the LED lighting market, the current trend is to provide compact and low cost solutions for converters for driving LEDs, while at the same time maintaining high performance in terms of LED current regulation, power factor PF, distortion THD and efficiency. For example, converters may be contained in products that need to meet specific performance criteria such as those set forth in Energy STAR specifications. In the LED lighting market, these converters are typically QR flyback converters that include analog divider circuitry that is usually a non-negligible portion in terms of silicon area of an integrated circuit containing the converter circuitry. This increases the cost and complexity of such a QR flyback converter. In addition, such a QR flyback converter typically includes line-sensing circuitry to sense the instantaneous rectified AC mains input voltage supplied to the converter. The power loss in such line-sensing circuitry may be, for example, 10 mW-15 mW. Some of the latest market requirements, such as EU COC Ver.5 and US DOE February 2014, specify total power consumption for the entire converter to be lower than 75 mW-100 mW in a no-load condition. As a result, the power loss in the line-sensing circuitry may no longer be considered insignificant or negligible. There is a need for improved QR flyback converter circuits and methods to satisfy current market requirements.

BRIEF SUMMARY

One embodiment of the present disclosure is a quasi-resonant (QR) flyback converter having a sinusoidal input current in order to achieve low total harmonic distortion THD and high power factor (Hi-PF) and implanting control using only quantities available on the primary side of the converter.

According to one embodiment of the present disclosure, a primary-side controlled high power factor, low total harmonic distortion, quasi resonant flyback converter converts an AC mains power line input to a DC output for powering a load, such as a string of LEDs. The AC mains power line input is supplied to a transformer that is controlled by a power switch.

In one embodiment, a device for controlling a power transistor of a power stage includes a shaper circuit including a first current generator configured to output a first current responsive to a bias voltage signal and to generate a reference voltage signal based on the first current. A bias circuit includes a second current generator configured to output a second current responsive to a compensation voltage signal and to generate the bias voltage based on the second current. An error detection circuit includes a third current generator configured to output a third current responsive to the reference voltage signal and to generate the compensation voltage signal based on the third current. A driver circuit has a first input configured to receive the reference voltage signal and having an output configured to drive the power transistor.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1is a schematic of a primary-controlled Hi-PF QR Flyback converter implementing a prior art primary-side control method.

FIGS. 2A and 2Bare timing diagrams illustrating key waveforms in the flyback converter ofFIG. 1during operation of the converter.

FIG. 3is a schematic of a primary-controlled Hi-PF QR flyback converter according to one embodiment of the present disclosure.

FIGS. 4A and 4Bare timing diagrams illustrating key waveforms in the flyback converter ofFIG. 3during operation of the converter.

FIG. 5is a timing diagram showing simulation results for the flyback converter ofFIG. 3for an input voltage Vac=115 Vac.

FIG. 6is a timing diagram showing simulation results for the flyback converter ofFIG. 3for an input voltage Vac=230 Vac.

FIGS. 7A and 7Bare graphs showing simulation results comparing the total harmonic distortion (THD) of the flyback converters ofFIGS. 1 and 3inFIG. 7Aand comparing the power factor PF of the two convertersFIG. 7B.

FIG. 8is a graph showing simulation results comparing regulation of the average output current provided by the flyback converters ofFIGS. 1 and 3.

DETAILED DESCRIPTION

FIG. 1is a schematic of a conventional hi-PF QR flyback converter100that will now be described to provide a better understanding of such a converter before discussing hi-PF QR flyback converters according to embodiments of the present disclosure. On the primary side, the QR flyback converter100includes a controller102, a bridge rectifier104having inputs106coupled to an AC mains power line that supplies an AC mains input voltage Vac(θ), an input capacitor Cin, a voltage divider Ra-Rbcoupled to the bridge rectifier104, a primary winding Lpand an auxiliary winding Lauxof a transformer108, a power switch M coupled to the transformer108and controlled by controller102, a sensing resistor Rscoupled in series with the power switch M to provide a sensed voltage to the controller indicating a current flowing through the power, a zero-crossing detection resistor RZCDcoupled to the auxiliary winding Laux, and a clamp circuit109connected across the primary winding Lpto clamp a leakage inductance of the primary winding.

On the secondary side of the converter100, secondary winding Lsof the transformer108has one end connected to a secondary ground GND2and the other end connected to the anode of a diode D having the cathode connected to the positive plate of a capacitor Coutthat has its negative plate connected to the secondary ground. The converter100provides an output voltage Voutthat supplies power to a load110, which inFIG. 1is a set of series-connected LEDs, although other loads could be supplied with electrical power by the converter100.

The controller102has a reference voltage estimation circuit116that is configured to produce a reference voltage VcsREF(θ) and includes a bias circuit118and a shaper circuit120. The controller102also includes a driver circuit121having a PWM comparator122, a set-reset (SR) flip-flop124, an OR gate126, and driver127configured to drive the power switch M. The PWM comparator122includes an inverting input that receives the reference voltage VCSREF(θ), a non-inverting input that receives a sense voltage VCSfrom the sense resistor Rs, and an output that provide a reset signal to a reset input R of the flip-flop124. The flip-flop124also includes a set input S coupled to an output of the OR gate126, and an output that is coupled to an input of the driver127.The OR gate126also has first and second inputs coupled to respective outputs of a starter block128and a zero current detection (ZCD) block130. The OR gate126provides a set signal to the set input S of the SR flip flop when the ZCD block130detects that a falling edge of an auxiliary voltage Vauxas applied through a resistor RZCSgoes below a threshold, or when the starter block128produces a start signal to initiate a switching cycle. The transformer108includes an auxiliary coil as shown inFIG. 1which generates the auxiliary voltage Vaux. The starter block128outputs a signal at power-on when no signal is available on the input of the ZCD block130and prevents the converter100from getting “stuck” in the event the signal on the input of the ZCD block130is lost for any reason. The ZCD block130also generates a freewheeling signal FW that is high during demagnetization of the transformer108, as shown inFIG. 2A, and is used by the reference voltage estimation circuit116to generate a B(θ) signal, as will be described in more detail below.

FIGS. 2A and 2Bare timing diagrams illustrating key waveforms in the flyback converter100ofFIG. 1during operation, with the waveforms inFIG. 2Abeing on a switching period time scale and the waveforms inFIG. 2Bbeing on an AC mains power line cycle time scale. The freewheeling signal FW is high during demagnetization (i.e., energy stored in the primary winding Lpis transferred to the secondary winding Ls) of the transformer108and is low otherwise. Thus, as seen inFIG. 2A, the FW signal is low during a delay time TRduring which a secondary current Is(t,θ) through the secondary winding Ls has gone to zero. This delay time TRin the quasi-resonant (QR) flyback converter100is the delay between the instant the transformer108demagnetizes (i.e. a secondary current Is(t,θ) equals zero) and the turning ON of the power switch M. The FW signal stays low during the magnetic energy storage phase when the power switch M is turned ON and a primary current Ip(t,θ) flows through the primary winding Lpto thereby store magnetic energy in the primary winding.

The shaper circuit120has a first current generator140, a resistor Rt1coupled to an output of the first current generator140, a switch132that switchably couples the resistor Rt1to ground, and a capacitor Ct1coupled between the output of the current generator140and ground. The first current generator140has an input coupled to a supply voltage terminal Vcc and a control terminal coupled to the voltage divider Ra-Rbvia a pin MULT. The first current generator140produces a current ICH1(θ) based on a value of the voltage generated by the voltage divider Ra-Rband present on the MULT pin. The switch132is controlled by the output Q of the flip-flop124and thereby connects the capacitor Ct1in parallel with the switched resistor Rt1when the power switch M is ON.

The bias circuit118includes a second current generator142having an input coupled to the supply terminal Vcc, a control terminal coupled to the output of the first current generator140, and an output at which the second current generator produces a current ICH(θ). A second switched resistor Rtis switchably coupled to the output of the second current generator142by a switch134configured to connect the resistor Rtto the second current generator142under the control of the signal FW provided by the ZCD block130. The signal FW is high when the current is flowing in the secondary winding Ls. Another switch144is coupled to the output of the second current generator142and is configured to connect the output of the second current generator142to ground when the ZCD block130drives a signalFW, which is the complement or inverted version of the signal FW, high, indicating no current is flowing in the secondary winding Lsas seen inFIG. 2A.

The reference voltage estimation circuit116also includes a divider block146having a first input that receives a signal A(θ) from the shaper circuit120, a second input that receives the signal B(θ) from the bias circuit118, and an output at which the divider provides the reference voltage VcsREF(θ). The signal A(θ) is generated by the first current generator140acting on the switched resistor Rt1and capacitor Ct1. The current Ich1(θ) produced by the current generator140is proportional to a rectified input voltage Vin(θ) produced at the voltage divider Ra-Rb and supplied to the current generator140through the MULT pin. The divider ratio Rb/(Ra+Rb) of the voltage divider Ra-Rb will be denoted as Kp herein. The resistor Rt1is connected in parallel to the capacitor Ct1by the switch132when the signal Q of the SR flip flop124is high, i.e. during the on-time of the power switch M, and is disconnected when the signal Q is low, i.e. during the off-time of the power switch M. The voltage developed across the capacitor Ct1is A(θ) and is fed to the first input of the divider block146. The current generator140, capacitor Ct1, resistor Rt1and switch132collectively form the shaper circuit120, which is termed a “shaper” circuit because the circuit changes the shape of the current programming signal.

In the flyback converter100ofFIG. 1, a capacitor CTis coupled to a pin CT of the controller102and is assumed to be large enough so that the AC component (at twice the AC mains input line frequency fL) of the B(θ) signal is negligible, at least to a first approximation, with respect to the DC component BO of the B(θ) signal. As a result, the divider block146provides the reference voltage VcsREF(θ) that is the division of the A(θ) signal generated by the shaper circuit120by the B(θ) signal generated by the bias circuit118.

The inverting input of the PWM comparator122receives the reference voltage VcsREF(θ) the non-inverting input receives the voltage Vcs(t, θ), which is the voltage sensed across the sense resistor Rs that is a voltage proportional to the instantaneous current Ip(t, θ) flowing through the primary winding Lp and the power switch M when the power switch is turned ON. Assuming the power switch M is initially turned ON, the current through the primary winding Lp will be ramping up and so will the voltage across the resistor Rs. When the voltage Vcs(t,θ) across the sense resistor Rs equals the reference voltage VcsREF(θ), the PWM comparator122drives its output to reset the PWM latch or SR flip-flop124, causing the SR flip-flop to drive its output Q low to thereby turn OFF the power switch M. Therefore, the reference voltage VcsREF(θ) provided by the divider block146determines the peak value of the primary current Ip(t, θ) that, as a result, will be enveloped as the A(θ) signal.

After the power switch M is switched OFF, the energy stored in the primary winding Lp is transferred by magnetic coupling to the secondary winding Ls and then transferred to the output capacitor Cout and the load110until the secondary winding Ls is completely demagnetized. At this point, the diode D opens (i.e., turns OFF) and the drain node of the power switch M, which while the secondary winding Ls and the diode D were conducting was fixed at a voltage Vin(θ)+VR, is in a floating or high impedance state. The voltage VR is the reflected voltage, which is the output voltage Vout across the secondary winding Ls times the primary-to-secondary turns ratio n=Np/Ns of the transformer108. The reflected voltage VR would tend to eventually reach the instantaneous input voltage Vin(θ) through a damped ringing due to a parasitic capacitance that starts resonating with the primary winding Lp. The quick fall of the drain voltage of the power switch M that follows demagnetization of the transformer108is coupled through the auxiliary winding Laux and the resistor RZCDto the pin ZCD of the controller102. The ZCD block130is coupled to the ZCD pin and generates a pulse every time the ZCD block detects a negative-going edge falling below a threshold, and this pulse is applied through the OR gate126to set the PWM latch124and thereby turn ON the power switch M, starting a new switching cycle of the flyback converter100. The OR gate126allows the output of the “STARTER” block to also initiate a switching cycle by applying a signal through the OR gate to set the PWM latch124. As previously described, this serves at power-on when no signal is available on the ZCD pin input and prevents the converter100from getting stuck in case the signal on the ZCD input is lost for any reason.

As shown inFIG. 2Athe OFF-time of the power switch M is the sum of the time TFW(θ) during which the primary winding Lp is discharged and a time TRduring which the secondary winding Ls current has gone to zero. As a result, the switching period T(θ) of the flyback converter100is therefore given by:
T(θ)=TON(θ)+TFW(θ)+TR(Eqn. 1)
where θ can be considered ε(0, π).

A fundamental assumption for the following analysis is that T(θ)<<(Rt1×Ct1)<<1/fL. In this way, on the one hand the switching frequency ripple across capacitor Ct1is negligible while on the other hand the current Ich1(θ) can be considered constant within each switching cycle. This being assumed, it is possible to find the A(θ) signal or voltage developed across capacitor Ct1by charge balance according to:

The current Ich1(θ) is provided by the current generator140and it can be expressed as:
Ich1(θ)=gm1Kp(VPKsin θ)  (Eqn. 3)
where gm1is the current-to-voltage gain of the current generator140that generates the current Ich1(θ).

Solving for A(θ) voltage and considering Eqn. 3:

The current ICH(θ) provided by the current generator140that is used to generate the B(θ) signal can be expressed as:
ICH(θ)=GMA(θ)  (Eqn. 5)
where GMis the current-to-voltage gain of the current generator142that generates the current ICH(θ).

Now considering the capacitor CTby charge balance, it is possible to find the voltage B(θ) developed across the capacitor CTas follows:

Solving the previous expression for B(θ) and considering Eqns. (4) and (5):

The capacitor CTis assumed to be large enough so that the AC component (at twice the AC mains input line frequency fL) of the voltage B(θ) is negligible with respect to its DC component B0, which is defined as:

Considering the voltage-second balance for the Flyback converter's transformer, the primary on time TON(θ) and secondary on time TFW(θ) can be expressed by the following relationship:
VIN(θ)TON(θ)=n(VOUT+VF)TFW(θ)  (Eqn. 9)
where VFis the forward drop on the diode D.

Solving Eqn. 9 and considering that Kv=VPK/VR, where VR=n(VOUT+VF), the ratio between TFW(θ) and TON(θ) times results in the following:

Combining Eqns. (8) and (10) the DC component of the signal B(θ) results as follows:

Combining Eqns. (11) and (4) the expression for the voltage reference VcsREF(θ) results as follows:

VcsREF⁡(θ)=KD⁢A⁡(θ)B⁡(θ)≈KD⁢A⁡(θ)B0=KD⁢2GM⁢RT⁢Kv⁢sin⁢⁢θ⁢T⁡(θ)TON⁡(θ)(Eqn.⁢12)
where KDis the voltage divider gain and it is dimensionally a voltage.

Considering that the peak primary current Ipkp(θ) can be expressed as:

Ipkp⁡(θ)=VcsREF⁡(θ)Rs(Eqn.⁢13)
then the peak secondary current Ipks(θ) can be calculated by combing Eqns. (13) and (12) and considering that the secondary current is n=Np/Ns times the primary current:

Since the cycle-by-cycle secondary current Is(t,θ) is the series of triangles shown for this waveform inFIG. 2A, the average value of the secondary current Is(t,θ) in a switching cycle is:

The dc output current Iout is the average of Io(θ) over a line half-cycle:

Finally, combining Eqns. (16) and (10), the average output current Ioutfrom the converter100is given as:

Equation (17) states that the DC output current Ioutfrom the converter100depends only on external, user-selectable parameters (n, Rs) and on internally fixed parameters (GM, RT, KD) and does not depend on the output voltage Vout, or on the root mean square (RMS) input voltage Vin(θ) or on the switching frequency fSW(θ)=1/T(θ).

The input current Iin(θ) to the converter100is found by averaging the primary current Ip(t,θ), which is the series of triangles for the Ip(t,θ) current inFIG. 2Aover a switching cycle of the converter. From Eqns. (12) and (13), the input current Iin(θ) is given by:

Equation (18) shows that the input current Iin(θ) is a pure sinusoid in all operating conditions so the converter100has ideally a unity power factor and zero harmonic distortion of the input current (i.e., PF=1 and THD=0).

From the above description of the hi-PF QR flyback converter100, it is seen that this converter is hi-PF and low THD converter and utilizes a control algorithm that is able to regulate the DC output current and voltage using primary-side control (i.e., using only operational quantities available on the primary side of the converter. This is opto-less control, as previously discussed. Thus, while this control scheme advantageously provides QR operation mode with opto-less primary-side control and a hi-PF and low THD, the control scheme utilizes the line-sensing circuitry formed by the voltage divider including resistors Ra and Rb, which has a relatively significant power consumption, and also utilizes the analog divider block146, which occupies a relatively large portion or area of an integrated circuit in which the controller102is formed. The flyback converter100ofFIG. 1is described in detail in U.S. patent application Ser. No. 14,572,627, which is incorporated herein by reference in its entirety to the extent the disclosure of this application is not inconsistent with the disclosure of the present application.

As a result of these drawbacks of the flyback converter100as described above with reference toFIGS. 1 and 2, the present disclosure is directed to primary-side control techniques for a QR flyback converter that do not require such line-sensing circuitry and analog divider circuitry while still providing hi-PF and low THD operation, as will now be described in more detail.

Referring to Eqn. (16) above, the DC output current Ioutif a QR flyback converter can be expressed, by combining Eqns. (16), (15), (13) and (14), as follows:

Equation (19) shows that the DC output current Ioutcan be regulated using only quantities available on the primary side of the flyback converter and without an analog divider block146(FIG. 1) if the quantity on the right-hand side of Eqn. (19) is constant, which means independent of the output voltage Vout, the RMS input voltage Vin(θ) and from the switching frequency fSW(θ)=1/T(θ)). The second consideration is based on the transformer voltage-second balance as set forth in Eqn. (9) that can be expressed as:

TFW⁡(θ)TON⁡(θ)=Vin⁡(θ)n⁡(VOUT+VF)(Eqn.⁢20)
which shows that the shape of the input voltage Vin(θ) needed to achieve high-PF and low-THD can be estimated without using line-sensing circuitry by generating a voltage proportional to the ratio between the free-wheeling time TFw(θ) and the ON-time TON(θ) of the power switch M, as will now be described in detail with reference toFIGS. 3-8.

FIG. 3is a schematic of a primary-controlled Hi-PF QR flyback converter300including a controller302for controlling the converter without line-sensing circuitry or an analog divider circuit according to one embodiment of the present disclosure.FIGS. 4A and 4Bare timing diagrams illustrating key waveforms generated in the flyback converter300during operation and will be discussed in more detail below. InFIG. 4Athe designated waveforms or signals are on a switching period time scale along the horizontal axis while inFIG. 4Bthe waveforms are on an AC mains line cycle time scale on the horizontal axis.

In the flyback converter300ofFIG. 3, components304-310correspond to the components104-110previously described with reference to the converter100ofFIG. 1. Thus, for the sake of brevity, the detailed operation of these components304-310will not again be discussed in detail with reference to the converter300ofFIG. 3. Other components of the converter300are also the same as those in the converter100ofFIG. 1, such as zero current detection resistor RZCD, input capacitor Cin, power switch M and sense resistor Rs, for example. The detailed individual operation of all such components will also not again be provided with reference toFIG. 3. Finally, the same is even true of some components of the controller302, which executes a different control method to control the operation of the converter300than does the controller102ofFIG. 1. For example, the controller302includes a driver circuit312including components314-324having the same structure and functionality as corresponding components in the driver circuit121ofFIG. 1. The individual operation of these components314-324has thus effectively been described with reference to the driver circuit121ofFIG. 1and will not again be described in detail with reference to the driver circuit312ofFIG. 3. InFIG. 3, all the components external to the controller302may be considered the power stage of the flyback converter300.

While the driver circuit312of the controller302has the same structure and operation as the driver circuit121of the controller102ofFIG. 1, the controller302further includes a reference voltage estimation circuit326having a different structure and different operation than the voltage reference circuit116in the controller102ofFIG. 1, as will now be described in more detail. In operation, the reference voltage estimation circuit326generates a first reference voltage VcsREF(θ) that is supplied to the inverting input of the PWM comparator314of the driver circuit312. The reference voltage estimation circuit326includes a shaper circuit328having the same structure as the shaper circuit120ofFIG. 1. More specifically, the shaper circuit328includes a first current generator330that supplies a first current Ich1(θ) to a node332on which the first reference voltage VcsREF(θ) is generated. This first current Ich1(θ) has a value that is based on a voltage VG(θ) generated by a bias circuit that will be described in more detail below. A resistor Rt1is coupled in series with a switch SW1between the node332and ground, with the switch being controlled by the output signal Q provided by the PWM latch316. A capacitor Ct1is also coupled between the node332and ground and is charged by the current Ich1(θ) from the first current generator330to generate the reference voltage VcsREF(θ) on the node332. When the output signal Q is activated or turned ON to thereby turn ON the power switch M, the Q signal also closes the switch SW1to thereby discharge the capacitor Ct1through the resistor Rt1and reduce the reference voltage VcsREF(θ).

The reference voltage estimation circuit326further includes a bias circuit334that generates the voltage VG(θ) that is supplied to the current generator330to set the value of the first current Ich1(θ). The bias circuit334includes a second current generator336that generates a second current a current Ich2(θ) that is supplied through one of a pair of complementary switches SW3to a node338. The second current Ich2(θ) has a value that is based on a compensation signal VCOMP(θ) generated by other circuitry in the controller302that will be described in more detail below. A resistor Rt2is coupled in series with a switch SW4between the node338and ground, with the switch SW4being controlled by the output signal Q from the PWM latch316.

A capacitor Ct2is also coupled between the node338and ground and is charged by the current Ich2(θ) from the second current generator336when the FW signal generated by the ZCD block322closes the one of the complementary switches SW3connected between the second current generator336and the node338. In this situation, the current Ich2(θ) from the second current generator336charges the capacitor Ct2to generate the voltage VG(θ) on the node338. When the output signal Q is activated or turned ON to thereby turn ON the power switch M, the Q signal also closes the switch SW4to thereby discharge the capacitor Ct2through the resistor Rt2and reduce the voltage VG(θ). The other one of the complementary switches SW3is coupled between the second current generator336and ground and is controlled by theFWsignal, namely the inverted version or complement of the FW signal generated by the ZCD block322). TheFWsignal goes high when no current is flowing in the secondary winding Ls, which is seen through the FW signal illustrated inFIG. 4A.

Finally, the controller302includes other circuitry that generates the compensation signal VCOMP(θ) as previously mentioned. This other circuitry includes a third current generator340having a control terminal coupled to the node332to receive the reference voltage VcsREF(θ). The third current generator340generates a third current Ich3(θ) having a value based on the value of the reference voltage VcsREF(θ). The third current Ich3(θ) is supplied through one of a pair of complementary switches SW2to charge a node342, with this switch being controlled by the FW signal from the ZCD block322. A resistor Rt3is coupled between the node342and ground and generates a comparison voltage VCT(θ) on the node342responsive to the third current Ich3(θ) when the corresponding one of the complementary switches SW2is closed, which occurs when the FW signal is high indicating current is flowing in the secondary winding Ls. The other one of the complementary switches SW2is coupled between the third current generator340and ground and, when the signalFWis active high, which occurs when FW is low when no current is flowing through the secondary winding Ls, this switch sinks the current Ich3(θ) from the third current generator to ground.

A transconductance error amplifier344has an inverting input coupled to the node342which, in turn, is also coupled to a CT pin of the controller302. A capacitor Ct3is coupled to the CT pin and thus to the node342and is assumed to be large enough so that an AC component at twice the AC mains line frequency fLof the comparison voltage VCT(θ) on the node342is negligible with respect to a DC component this voltage, as will be described in more detail below. A non-inverting input of the transconductance error amplifier344receives an internal reference voltage VREFand generates an output current based on the differential voltage across the inverting and non-inverting inputs of the amplifier. Thus, the transconductance error amplifier344generates an output current having a value based on the difference between the voltage on the node342and the reference voltage VREF. The output current from the transconductance amplifier344charges a compensation capacitor CCOMPto thereby generate the compensation signal CCOMP(θ) on the output the transconductance amplifier. The compensation capacitor CCOMPis coupled to a COMP pin of the controller302, with the COMP pin being coupled to the output of the transconductance amplifier344as seen inFIG. 3.

In the embodiment ofFIG. 3, the controller302is formed in an integrated circuit having the pins CT, COMP, GND, GD, and ZCD coupled to the circuitry of the controller as shown, some of which have been discussed in the above description. Within the controller302, the transconductance error amplifier344, current generator340, switches SW2and resistor Rt3may collectively be considered an error detection circuit346. The capacitors Ct3and CCOMP, although external to the integrated circuit in the embodiment ofFIG. 3, may also be considered to be part of the error detection circuit346. The same is true for the sense resistor Rs, which may be considered part of the driver circuit312that was previously described above.

The theory of operation of the controller302in controlling the overall operation of the flyback converter300will now be described in more detail with reference toFIGS. 3, 4A and 4B. Considering the voltage VCOMP(θ) generated on the output of the transconductance error amplifier344, the capacitor CCOMPis assumed to be large enough so that the AC component at twice the line frequency fLof the voltage VCOMP(θ) is negligible with respect to the DC component VCOMP0, at least to a first approximation. The DC componentVCOMP0of the voltage VCOMP(θ) is defined as:
VCOMP0=gmC[VREF−VCT(θ)]  (Eqn. 21)
where gmCis the current-to-voltage gain of the transconductance error-amplifier344, the voltage VREFis the internal voltage reference, and the comparison voltage VCT(θ) is the voltage developed across the capacitor Ct3.

The capacitor Ct2is charged through the current Ich2(θ) from the second current generator336when the signal FW is high, i.e. during transformer's demagnetization, and the capacitor Ct2is discharged through the resistor Rt2resistor when the signal Q is high, i.e. during the on-time of the power switch M. A fundamental assumption for the present analysis is that T(θ)<<Rt2×Ct2<<1/fL. In this way, on the one hand the switching frequency ripple across the capacitor Ct2is negligible and on the other hand the current Ich2(θ) can be considered constant within each switching cycle. Using these assumptions, it is possible to find the voltage VG(θ) developed across the capacitor Ct2by charge balance as follows:

Ich⁢⁢2⁡(θ)⁢TFW⁡(θ)=VG⁡(θ)Rt⁢⁢2⁢TON⁡(θ)(Eqn.⁢22)
The current Ich2(θ) provided by the current generator336can be expressed as:
Ich2(θ)=gm2VCOMP0(Eqn. 23)
where gm2is the current-to-voltage gain of the current generator336. Solving Eqn. (22) for the voltage VG(θ), and considering the Eqns. (10) and (23), it can be shown that the voltage VG(θ) is given by the following:
VG(θ)=gm2Rt2VCOMP0KVsin θ  (Eqn. 24)

The resistor Rt1is connected in parallel to the capacitor Ct1when the signal Q is high, i.e. during the on-time of the power switch M, and is disconnected when the signal Q is low, i.e. during the off-time of the power switch M. The voltage developed across the capacitor Ct1is the current sensed reference voltage VcsREF(θ) and is supplied to the inverting input of the PWM comparator314. The current generator330that generates current Ich1(θ), capacitor Ct1, resistor Rt1plus the switch SW1is referred to as the shaper circuit328as mentioned above since the circuit changes the shape of the current programming signal.

The current Ich1(θ) provided by the current generator330can be expressed as:
Ich1(θ)=gm1Vg(θ)  (Eqn. 25)
where gm1is the current-to-voltage gain of the current generator330that generates the current Ich1(θ) and the voltage VG(θ) is the voltage developed across the capacitor Ct2.

The same previous assumption is also considered to apply to the shaper circuit328, namely T(θ)<<Rt1×Ct1<<1/fL. In this way, on the one hand the switching frequency ripple across the capacitor Ct1is negligible while on the other hand the current Ich1(θ) can be considered constant within each switching cycle. Using these assumptions, it is possible to find the voltage VcsREF(θ) developed across the capacitor Ct1by charge balance as follows:

Ich⁢⁢1⁡(θ)⁢T⁡(θ)=(VcsREF⁡(θ)Rt⁢⁢1)⁢TON⁡(θ).(Eqn.⁢26)
Solving for the voltage VcsREF(θ) in Eqn. (26) and considering Eqns. (24) and (25), it can shown that:

The input current IIN(θ) of the flyback converter300can be found by averaging the primary current Ip(t,θ) through the primary winding LPand switch M, where this primary current has a peak value expressed by

Ipkp⁡(θ)=VCS,REF⁡(θ)RS
and, talking into consideration Eqn. (27), the input current may be expressed as:

IIN⁡(θ)=12⁢Ipkp⁡(θ)⁢TONT⁡(θ)=VCOMP⁢⁢0⁢gm1⁢Rt⁢⁢1⁢gm2⁢Rt⁢⁢2⁢KV2⁢RS⁢sin⁢⁢θ(Eqn.⁢28)
The Eqn. (28) shows that the controller302ofFIG. 3implements a control method that achieves a sinusoidal input current IIN(θ), which as previously discussed means that the converter300ideally has a power factor PF=1 and distortion THD=0 in the constant-current primary-controlled Hi-PF QR flyback converter300without using the line-sensing circuitry (e.g., the voltage divider formed by the resistors Ra, Rb inFIG. 1).

In the controller302, the current generator340that generates the current Ich3(θ) that is used to generate the comparison voltage VCT(θ) signal, and this current can be expressed as:
Ich3(θ)=GMVCS,REF(θ)  (Eqn. 29)
where GMis the current-to-voltage gain of the current generator340. Now considering the capacitor Ct3by charge balance, it is possible to find the comparison voltage VCT(θ) developed across the capacitor Ct3as follows:

Ich⁢⁢3⁡(θ)⁢TFW⁡(θ)=VCT⁡(θ)Rt⁢⁢3⁢T⁡(θ)(Eqn.⁢30)
Solving Eqn. (30) for the comparison voltage VCT(θ) and then considering Eqn. (27), it can be shown that:

Similar to the prior approach ofFIG. 1, the capacitor Ct3is assumed to be large enough so that the AC component at twice the AC mains input line frequency fLof the comparison voltage VCT(θ) is negligible with respect to its DC component VCT0, at least to a first approximation. The DC component VCT0is then given by:

Now considering the voltage-second balance for the transformer308of the flyback converter as expressed in Eqn. (10), the DC component VCT0can be shown to be given by:

VCS,REF⁡(θ)=2GM⁢Rt⁢⁢3⁢VREFKV⁢sin⁢⁢θ⁢T⁡(θ)TON⁡(θ)(Eqn.⁢35)
If the same mathematical operations are performed for Eqn. (14), the peak secondary current Ipks(θ) of the flyback converter300can be calculated starting from Eqn. (35) as follows:

Since the cycle-by-cycle secondary current Is(t,θ) is the series of triangles shown inFIG. 4Afor this signal, the average value of this secondary current in a switching cycle is given by:

The DC output current Ioutof the flyback converter300is the average of the current I0(θ) over a main line half-cycle and is given by:

Finally, combining Eqns. (38) and (10) the average output current of the flyback converter is shown to be:

The Eqn. (39) shows the control method implemented by the controller302ofFIG. 3, the DC output current Ioutdepends only on external, user-selectable parameters, namely the turns ratio n of the transformer308and the sense resistor Rs, and on internally fixed parameters (GM, Rt3, VREF) and does not depend on the output voltage Vout, or on the RMS of the input voltage Vin(θ), or on the switching frequency fSW(θ)=1/T(θ). As a result, the control method implemented by controller302, in addition to providing ideally unity power factor PF=1 and zero harmonic distortion (THD=0) of the input current IIN(θ), also controls the flyback converter300to provide a regulated output current Ioutusing only quantities available on the primary side of the converter, and without using an analog divider and line-sensing circuitry as were utilized in the converter100ofFIG. 1.

The control method implemented by the controller302ofFIG. 3has been tested and validated with PSIM simulations, where PSIM is an electronic circuit simulation software package that is specifically designed specifically for use in simulating power electronics circuits. The timing diagrams resulting from some of these simulations are shown inFIGS. 5 and 6.FIG. 5shows a simulation where the input voltage Vac(θ) is 115 VAC whileFIG. 6shows a simulation where the input voltage is 230 VAC. As seen in these simulations, there is a very low level of distortion of the input current (around 2.8% at Vin=115 Vac, around 3.2% at Vin=230 Vac) due to an input EMI filter and the non-idealities considered both in the power circuit and the control circuit of the converter300.FIGS. 7A and 7Bare graphs showing simulation results for the converter300in comparison to the converter100, withFIG. 7Ashowing a comparison of the THD levels of the two converters andFIG. 7Bshowing a comparison of the power factor PF of the two converters.FIG. 8is a graph showing simulation results comparing regulation of the average output current Ioutof the flyback converters300and100and illustrates that the converter300provides regulation that is just as good as the converter100but without requiring the line-sensing and analog divider circuitry to do so, as discussed above.