Chassis security switch

Apparatus that can detect chassis tamper events are disclosed. One apparatus includes a chassis including a secure area housing a secure element within the chassis and a security switch coupled between the chassis and the secure area. The security switch includes a switch and a processor in which the switch is configured to mechanically trigger to a tamper state from a non-tamper state in response to a chassis tamper event occurring between the chassis and the secure area and to be electrically reset to the non-tamper state from the tamper state in response to receiving a reset signal from the processor. Methods and computer program products that can perform chassis tamper event and switch reset functions for the apparatus are also disclosed.

FIELD

The subject matter disclosed herein relates to device security and more particularly relates to a security switch for a device chassis.

DESCRIPTION OF THE RELATED ART

Unauthorized tampering with a device can present a number of issues for an owner of the device. Specifically, an unauthorized entity can access sensitive and/or secure elements and/or data in a device by opening the chassis of the device to access the sensitive and/or secure elements and/or data housed therein.

Conventional solutions to detect whether the chassis of a device has been tampered with typically require that a security mechanism have at least auxiliary power supplied to it for the security mechanism to detect a chassis tamper event. While conventional security mechanisms can detect chassis tamper events, there are drawbacks to such security mechanisms.

A drawback to conventional security mechanisms is that a chassis tamper event can only be detected when power is being supplied to the security mechanism. Another related drawback to conventional security mechanisms is that because a chassis tamper event cannot be detected when power is not being supplied to the security mechanism, conventional security mechanisms consider a loss of power a chassis tamper event even though a chassis tamper may not have occurred because there is no way of knowing whether a chassis tamper event occurred during a power loss. Therefore, to ensure that a chassis tamper event did not occur, a loss of power situation is treated, by default, as a chassis tamper event.

BRIEF SUMMARY

Apparatus that can detect a chassis tamper event are disclosed. Methods and computer program products that can perform chassis tamper event and switch reset functions for the apparatus are also disclosed.

In one embodiment, an apparatus includes a chassis including a secure area housing a secure element within the chassis and a security switch coupled between the chassis and the secure area. The security switch includes a switch and a processor in which the switch is configured to mechanically trigger to a tamper state from a non-tamper state in response to a chassis tamper event occurring between the chassis and the secure area and to be electrically reset to the non-tamper state from the tamper state in response to receiving a reset signal from the processor. Methods and computer program products that can perform chassis tamper event and switch reset functions for the apparatus are also disclosed.

A method, in one embodiment, includes receiving, by a processor, a trigger signal from a switch that a tamper state of the switch has been mechanically triggered from a non-tamper state to the tamper state in response to a chassis tamper event occurring between a chassis and a secure area housing a secure element. The method further includes transmitting, by the processor, a reset signal to the switch to electrically reset the switch from the tamper state to the non-tamper state.

In one embodiment, a program product includes a computer-readable storage medium that stores code executable by a processor. The executable code, in certain embodiments, includes code to receive a trigger signal from a switch that a tamper state of the switch has been mechanically triggered from a non-tamper state to the tamper state in response to a chassis tamper event occurring between a chassis and a secure area housing a secure element. The executable code, in some embodiments, further includes code to transmit a reset signal to the switch to electrically reset the switch from the tamper state to the non-tamper state.

DETAILED DESCRIPTION

Any combination of one or more computer-readable media may be utilized. The computer-readable medium/media may include one or more computer-readable storage media. The computer-readable storage medium/media may be a storage device storing the code. The storage device may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, holographic, micromechanical, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing.

Reference throughout this specification to one embodiment, an embodiment, or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases in one embodiment, in an embodiment, and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment, but mean one or more but not all embodiments unless expressly specified otherwise. The terms including, comprising, having, and variations thereof mean including but not limited to, unless expressly specified otherwise. An enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise. The terms a, an, and the also refer to one or more unless expressly specified otherwise.

In addition, as used herein, the term set can mean one or more, unless expressly specified otherwise. The term sets can mean multiples of or a plurality of one or mores, ones or more, and/or ones or mores consistent with set theory, unless expressly specified otherwise.

With reference now to the drawings,FIG. 1is a schematic block diagram of one embodiment of an apparatus100(and/or system) that includes chassis tamper event detection. The apparatus100can include any suitable apparatus and/or component that includes and/or can include a chassis102. Examples of an apparatus100include, but are not limited to, an information handling device (e.g., a computing device, a computing system, and/or a computing network), one or more computer system and/or network components (e.g., a computer server, a router, a network switch, etc.), one or more computing device components (e.g., a monitor/display, a touch screen, a keyboard, a mouse, a touch pad, a trackball, a joystick, a camera, a printer, a router, a switch, etc.), a cellular telephone, a personal digital assistant (PDA), a smart device (e.g., a smart watch, etc.), a wearable device, and/or an internet of things (IoT) device, among other systems, devices, and/or components that can include a chassis102that are possible and contemplated herein.

In various embodiments, the apparatus100includes an information handling device. In some embodiments, the information handling device includes a laptop computing device. In other embodiments, the information handling device includes a desktop computing device. In still other embodiments, the information handling device can include a combination laptop computing device and desktop computing device.

At least in the illustrated embodiment, the apparatus100includes, among other components, a chassis102, a secure area104that houses one or more secure elements106, a security switch108, and an input/output (I/O) device110. The chassis102may include any suitable structure and/or material that can house the secure area104, the secure element(s)106, the security switch108, and the I/O device110, among other components that can be housed within a chassis102that are possible and contemplated herein.

In various embodiments, the chassis102is closed and/or sealed. In certain embodiments, the chassis102is openable and/or re-sealable. In alternative embodiments, the chassis102is not openable and/or re-sealable.

The secure area104may include any suitable area that can house, store, and/or include any type of sensitive, private, secret, classified, important, proprietary, and/or confidential element(s) and/or data. At least in the illustrated embodiment, the secure area houses one or more secure elements106.

A secure element106may include any suitable type of sensitive, private, secret, classified, important, proprietary, and/or confidential element(s), component(s), device(s), and/or data. In certain embodiments, the secure element106includes the motherboard of a computing device, among other types of elements, devices, and/or components that are possible and contemplated herein. In additional embodiments, the motherboard includes one or more sensitive, private, secret, classified, important, proprietary, and/or confidential elements, components, and/or devices (e.g., one or more memory devices, one or more I/O devices, one or more buses, and/or one or more processing devices, etc., among other elements, components and/or devices that are possible and contemplated herein). In further additional embodiments, the one or more elements, components, and/or devices on the motherboard include(s) and/or store(s) one or more types of sensitive, private, secret, classified, important, proprietary, and/or confidential data and/or material(s).

In some embodiments, the sensitive, private, secret, classified, important, proprietary, and/or confidential data and/or material(s) are related to the apparatus100and/or to the operations/functions of the apparatus100. In additional or alternative embodiments, the sensitive, private, secret, classified, important, proprietary, and/or confidential data and/or material(s) are related to one or more components, devices, and/or systems, and/or to the operations/functions thereof, that are external to the apparatus100.

In certain embodiments, the sensitive, private, secret, classified, important, proprietary, and/or confidential data and/or material(s) are related to the entity that owns and/or controls the apparatus100. In additional or alternative embodiments, the sensitive, private, secret, classified, important, proprietary, and/or confidential data and/or material(s) are related to one or more entities associated with and/or in competition with the entity that owns and/or controls the apparatus100. In further additional or alternative embodiments, the sensitive, private, secret, classified, important, proprietary, and/or confidential data and/or material(s) are related to one or more entities not associated with and/or that are external to the entity that owns and/or controls the apparatus100.

A security switch108may include any suitable structure that can detect a mechanical tamper event on a chassis and be electrically reset. That is, the security switch108may include any suitable structure that can be mechanically triggered (e.g., tripped from a non-tamper state to a tamper state) and any suitable circuitry that can electrically reset the mechanically triggerable structure (e.g., reset from the tamper state to the non-tamper state).

In various embodiments, the security switch108includes a re-settable latching switch, which can include any suitable electrically re-settable latching switch and/or structure that can perform the functions of a latching switch and that can be electrically reset. In certain embodiments, the security switch108includes a re-settable latching electromechanical push button switch.

Some embodiments of the security switch108include a pull-up resistor circuit, as illustrated inFIG. 2A. In the example embodiment illustrated inFIG. 2A, a pull-up resistor circuit implemented as a security switch108A includes a voltage source (e.g., a +5V source) coupled to a resistor R1, which can include any suitable resistance in the range of about 2 kΩ to about 4.7 kΩ, among other sized ranges, ranges, and/or resistances that are possible and contemplated herein. The resistor R1is further coupled to a node202and the node202is coupled to a switch S1and a controller204A, and the switch S1is further coupled to ground GND.

The switch S1, in various embodiments, includes a re-settable latching electromechanical push button switch. In certain embodiments, the latching electromechanical push button switch is mechanically triggered (e.g., tripped from a non-tamper state to a tamper state) by the chassis102being opened and electrically reset (e.g., reset from the tamper state to the non-tamper state) by the controller204A, as discussed elsewhere herein.

The controller204A includes one or more processing devices (e.g., processor(s)) for executing instructions in one or more applications configured to cause the controller204A to perform tamper security operations, among other operations that are possible and contemplated herein. In various embodiments, the tamper security operations comprise receiving (e.g., from the switch S1) a trigger signal indicating that a chassis tamper event has occurred and/or has been detected, notifying a user (e.g., via I/O device110) of the chassis tamper event, receiving one or more authentication inputs from a user (e.g., via I/O device110), validating the authentication input(s) to verify that a user is an authorized user, and electrically resetting the switch S1(e.g., via a reset signal) in response to receiving one or more instructions and/or commands from an authorized user, each of which is discussed elsewhere herein.

Additional embodiments of the security switch108include a pull-down resistor circuit, as illustrated inFIG. 2B. In the example embodiment illustrated inFIG. 2B, a pull-down resistor circuit implemented as a security switch108B includes a voltage source (e.g., a +5V source) coupled to a switch S2.

The switch S2, in various embodiments, includes a re-settable latching electromechanical push button switch. In certain embodiments, the latching electromechanical push button switch is mechanically triggered (e.g., tripped from a non-tamper state to a tamper state) by the chassis102being opened and electrically reset (e.g., reset from the tamper state to the non-tamper state) by a controller204B, as discussed elsewhere herein.

The switch S2is coupled to a node202B. In addition, the node202B is coupled to the controller204B and to a resistor R2.

The controller204B includes one or more processing devices (e.g., processor(s)) for executing instructions in one or more applications configured to cause the controller204B to perform tamper event security operations, among other operations that are possible and contemplated herein. In various embodiments, the tamper security operations comprise receiving (e.g., from the switch S2) a trigger signal indicating that a chassis tamper event has occurred and/or has been detected, notifying a user (e.g., via I/O device110) of the chassis tamper event, receiving one or more authentication inputs from a user (e.g., via I/O device110), validating the authentication input(s) to verify that a user is an authorized user, and electrically resetting the switch S2(e.g., via a reset signal) in response to receiving one or more instructions and/or commands from an authorized user, each of which is discussed elsewhere herein.

The resistor R2, which can include any suitable resistance in the range of about 4.7 kΩ to about 4.7 kΩ, among other sized ranges, ranges, and/or resistances that are possible and contemplated herein. As shown, the resistor R2is further coupled to ground GND.

As illustrated inFIG. 1, the security switch108is physically coupled to the chassis102via a physical coupling112A. In addition, the security switch108is physically coupled to the secure area104and/or the secure element106via a physical coupling112B. In other words, the security switch108is physically coupled between the chassis102and the secure area104and/or the secure element106via physical couplings112A and112B, respectively.

The physical couplings112A and112B may include any suitable type of physical coupling that is known or developed in the future that can attach and/or couple the security switch108to and/or between the chassis102and the secure area104and/or the secure element106. In various embodiments, the physical couplings112A and112B may include any suitable type of physical coupling that can physically trigger the security switch108to indicate that a tamper event has occurred in response to the chassis102being opened and/or compromised.

In certain embodiments, the chassis102being opened and/or compromised (e.g., a tamper event) can be defined as the chassis102being opened and/or the chassis102being opened greater than a predetermined amount (e.g., any suitable amount greater than zero millimeters (0 mm), among other situations indicative of the chassis102being opened and/or compromised (e.g., a tamper event) that are possible and contemplated herein. In additional or alternative embodiments, the chassis102being opened and/or compromised (e.g., a tamper event) can be defined as the chassis102and the secure area104and/or the secure element106being separated from one another and/or the chassis102and the secure area104and/or the secure element106being separated from one another greater than a predetermined amount (e.g., any suitable amount greater than 0 mm), among other situations indicative of the chassis102being opened and/or compromised (e.g., a tamper event) that are possible and contemplated herein.

The physical triggering of the security switch108indicative of a tamper event may be manifest via any suitable type of indicator. In some embodiments, the physical triggering of the security switch108indicative of a tamper event is manifest via a push button trigger on the security switch108(e.g., a button on switch S1or S2being depressed, released, actuated, opened or closed, etc.).

In some embodiments, the physical trigger opens (e.g., shorts to GND) the switch S1or closes the switch S2. In this manner, a tamper event can be indicated, detected, and/or determined by the controller204A or204B in response to the controller204A or204B failing to detect a voltage (or detecting a logic low or logic 0) at the node202A or202B, respectively.

In other embodiments, the physical trigger closes the switch S1or opens (e.g., shorts to the voltage source (+5V)) the switch S2. In this manner, a tamper event can be indicated, detected, and/or determined by the controller204A or204B in response to the controller204A or204B detecting a voltage (or detecting a logic high or logic 1) at the node202A or202B, respectively.

Controller(s)204A and/or204B may include any suitable controller and/or controlling device that is known or developed in the future. In certain embodiments, the controller(s)204A and/or204B includes a microcontroller or microcontroller unit (MCU). As discussed previously, the controller(s)204A and/or204B can include one or more processing devices (e.g., processor(s)) for executing instructions in one or more applications configured to cause the controller(s)204A and/or204B to perform tamper event security operations.

With reference toFIG. 3A,FIG. 3Aillustrates one embodiment of a controller300A corresponding to the controller(s)204A and/or204B. At least in the illustrated embodiment, the controller300A includes, among other components, a tamper event module302and a reset module304A.

A tamper event module302may include any suitable hardware and/or software that can detect and/or determine a tamper event on chassis102(e.g., a chassis tamper event). In various embodiments, the tamper event module302can monitor a switch S1or S2and detect and/or determine a tamper event on chassis102based on a voltage and/or a logic condition at a node (e.g., node(s)202A and/or202B) coupled to the switch S1or S2.

In certain embodiments, the tamper event module302is configured to detect and/or determine that chassis102has experienced a tamper event in response to the node202A or202B including a voltage, as discussed elsewhere herein. In additional or alternative embodiments, the tamper event module302is configured to detect and/or determine that chassis102has experienced a tamper event in response to the node202A or202B including a logic high or a logic 1, as discussed elsewhere herein.

In some embodiments, the tamper event module302is configured to detect and/or determine that chassis102has experienced a tamper event in response to the node202A or202B failing to include a voltage (e.g., 0V), as discussed elsewhere herein. In additional or alternative embodiments, the tamper event module302is configured to detect and/or determine that chassis102has experienced a tamper event in response to the node202A or202B including a logic low or a logic 0, as discussed elsewhere herein.

A reset module304A may include any suitable hardware and/or software that can electrically reset a security switch108(e.g., a physical and/or mechanical switch). The reset module304A may electrically reset a physical and/or mechanical switch (e.g., a security switch108) using any suitable technique that is known or developed in the future. In various embodiments, the reset module304A can electrically reset a physical and/or mechanical switch by selectively opening (or shorting) or closing the physical and/or mechanical switch after the physical and/or mechanical switch has been tripped and/or triggered.

In certain embodiments, the reset module304A is configured to reset the switch S1of a pull-up resistor circuit forming a security switch108A by opening (or shorting to GND) the switch S1. In alternative embodiments, the reset module304A is configured to reset the switch S1of a pull-up resistor circuit forming a security switch108A by closing the switch S1.

In other embodiments, the reset module304A is configured to reset the switch S2of a pull-down resistor circuit forming a security switch108B by opening (or shorting to the +5V source) the switch S1. In alternative embodiments, the reset module304A is configured to reset the switch S2of a pull-down resistor circuit forming a security switch108B by closing the switch S2.

Referring now toFIG. 3B,FIG. 3Billustrates another embodiment of a controller300B corresponding to the controller(s)204A and/or204B. The controller300B includes a tamper event module302similar to the controller300A discussed elsewhere herein. At least in the illustrated embodiment, the controller300B further includes, among other components, an I/O module306, an authentication module308, a reset module304B, and a security module310.

An I/O module306may include any suitable hardware and/or software that can enable the controller300B to communicate with a user. In various embodiment, the I/O module306is able to communicate with the user via the I/O device110.

In some embodiments, the I/O module306is configured to notify a user that a chassis tamper event has been detected and/or determined by the tamper event module302. In additional or alternative embodiments, the I/O module306is configured to notify a user that one or more secure elements106has/have been turn OFF by the security module310, as discussed elsewhere herein.

In certain embodiments, the I/O module306is configured to prompt a user to provide one or more authentication inputs so that the security switch108can be reset and/or to turn ON the one or more secure elements106has/have been turn OFF by the security module310, as discussed elsewhere herein. The authentication input(s) can include any suitable user input that can identify the user as an authorized user. Example authentication inputs can include, but are not limited to, a password, a biometric input, and/or a pattern input, etc., among other user inputs capable of identifying the user as an authorized user that are possible and contemplated herein. The I/O module306is further configured to receive the user input(s) and transmit the user input(s) to the authentication module308.

An authentication module308may include any suitable hardware and/or software that can verify one or more user inputs to authenticate that a user is an authorized user. The authentication module308can verify that a user is an authorized user based on one or more received user inputs using any suitable verification technique and/or method that is known of developed in the future. In various embodiments, the authentication module308can verify that a user is an authorized user by matching one or more current user inputs to a stored set of verified user inputs, among other verification techniques and/or methods that are possible and contemplated herein.

In some embodiments, the authentication module308is configured to transmit a verification signal to the reset module304B in response to verifying that the user is an authorized user. In additional embodiments, the authentication module308is further configured to transmit the verification signal to the security module310in response to verifying that the user is an authorized user. In certain embodiments, the authentication module308is configured to do nothing and/or continue to wait for a user to be authenticated as an authorized user in response to determining that the current user is not an authorized user (e.g., the current user input(s) do not match the stored set of verified user inputs).

A reset module304B may include any suitable hardware and/or software that can electrically reset a security switch108(e.g., a physical and/or mechanical switch). The reset module304B may electrically reset a physical and/or mechanical switch (e.g., a security switch108) using any suitable technique that is known or developed in the future. In various embodiments, the reset module304B can electrically reset a physical and/or mechanical switch by selectively opening (or shorting) or closing the physical and/or mechanical switch after the physical and/or mechanical switch has been tripped and/or triggered.

In certain embodiments, the reset module304B is configured to reset the switch S1of a pull-up resistor circuit forming a security switch108A by opening (or shorting to GND) the switch S1. In alternative embodiments, the reset module304A is configured to reset the switch S1of a pull-up resistor circuit forming a security switch108A by closing the switch S1.

In other embodiments, the reset module304B is configured to reset the switch S2of a pull-down resistor circuit forming a security switch108B by opening (or shorting to the +5V source) the switch S1. In alternative embodiments, the reset module304A is configured to reset the switch S2of a pull-down resistor circuit forming a security switch108B by closing the switch S2.

In some embodiments, the reset module304B is configured to receive the verification signal from the authentication module308. In further embodiments, the reset module304B is further configured to reset the security switch108in response to receiving the verification signal from the authentication module308.

A security module310may include any suitable hardware and/or software that can control the one or more secure elements106in the apparatus100. In various embodiments, the security module310is configured to selectively turn ON and OFF the secure element(s)106in the apparatus100.

In some embodiment, the security module310is configured to turn OFF one or more of the secure element(s)106in response to the tamper event module302detecting and/or determining that the chassis has experienced a tamper event. In additional or alternative embodiments, the security module310is configured to turn ON the one or more secure elements106that were previously turned OFF in response to the security switch108being reset by reset module304B and/or a user being verified as an authorized user by the authentication module308. In further additional or alternative embodiments, the security module310is configured to receive the verification signal from the authentication module308and turn ON the one or more secure elements106that were previously turned OFF in response to receiving the verification signal from the authentication module308.

As further illustrated inFIG. 1, the security switch108is coupled to and/or in communication with the secure element(s)106and the I/O device110via a bus114(e.g., a wired and/or wireless bus). The I/O device110may include any suitable input/output device that is known or developed in the future that can allow and/or enable the controllers204A,204B,300A, and/or300B to communicate and/or exchange data (e.g., send and receive signals and/or data). Examples of an I/O device110include, but are not limited to, a keyboard, a monitor, a touchscreen, a mouse, a trackball, and a joystick, etc., among other types of input/output devices that are possible and contemplated herein.

FIG. 4is a schematic flow chart diagram illustrating one embodiment of a chassis security method400for an apparatus100. At least in the illustrated embodiment, the method400begins by a controller204A,204B,300A, or300B (e.g., one or more processors) receiving a trigger signal from a switch (e.g., switch S1or S2) in a security switch108indicating that a tamper state of the switch S1or S2has been mechanically triggered and/or tripped (block402). In some embodiments, the tamper state of the switch S1or S2, in some embodiments, indicates that a chassis102has experienced a chassis tamper event. In other words, the chassis102has been opened and/or compromised.

The method400further includes the controller204A,204B,300A, or300B (e.g., one or more processors) transmitting a reset signal to the switch S1or S2to reset the switch S1or S2(block404). The switch S1or S2may be reset using any of the reset techniques and/or methods discussed elsewhere herein. In some embodiments, the reset signal is transmitted to the switch S1or S2in response to receiving a user input to reset the switch S1or S2.

FIG. 5is a schematic flow chart diagram illustrating another embodiment of a chassis security method500for an apparatus100. At least in the illustrated embodiment, the method500begins by a controller204A,204B,300A, or300B (e.g., one or more processors) receiving a trigger signal from a switch (e.g., switch S1or S2) in a security switch108indicating that a tamper state of the switch S1or S2has been mechanically triggered and/or tripped (block502). In some embodiments, the tamper state of the switch S1or S2, in some embodiments, indicates that a chassis102has experienced a chassis tamper event. In other words, the chassis102has been opened and/or compromised.

In response to the trigger signal, the controller204A,204B,300A, or300B turns OFF one or more secure elements106(block504) and notifies a user of the chassis tamper event (block506). The controller204A,204B,300A, or300B receives one or more authentication inputs from the user (block508) and verifies whether the user is an authorized user (block510). The user can be verified as an authorized user using any of the techniques and/or method discussed elsewhere herein.

The controller204A,204B,300A, or300B then turns ON the one or more secure elements106in response to verifying that the user is an authorized user (block512). In further response to verifying that the user is an authorized user, the controller204A,204B,300A, or300B transmits a reset signal to the switch S1or S2to reset to the switch S1or S2(block514). The switch S1or S2may be reset using any of the reset techniques and/or methods discussed elsewhere herein.

FIG. 6is a schematic flow chart diagram illustrating yet another embodiment of a chassis security method600for an apparatus100. At least in the illustrated embodiment, the method500begins by a controller204A,204B,300A, or300B (e.g., one or more processors) receiving a trigger signal from a switch (e.g., switch S1or S2) in a security switch108indicating that a tamper state of the switch S1or S2has been mechanically triggered and/or tripped (block602). In some embodiments, the tamper state of the switch S1or S2, in some embodiments, indicates that a chassis102has experienced a chassis tamper event. In other words, the chassis102has been opened and/or compromised.

In response to the trigger signal, the controller204A,204B,300A, or300B turns OFF one or more secure elements106(block604) and notifies a user that the secure element(s)106is/are turned OFF (block606). The controller204A,204B,300A, or300B receives one or more authentication inputs from the user (block608) and verifies whether the user is an authorized user (block610). The user can be verified as an authorized user using any of the techniques and/or method discussed elsewhere herein.

The controller204A,204B,300A, or300B then turns ON the one or more secure elements106in response to verifying that the user is an authorized user (block612). In further response to verifying that the user is an authorized user, the controller204A,204B,300A, or300B transmits a reset signal to the switch S1or S2to reset to the switch S1or S2(block614). The switch S1or S2may be reset using any of the reset techniques and/or methods discussed elsewhere herein.

FIG. 7is a schematic flow chart diagram illustrating still another embodiment of a chassis security method700for an apparatus100. At least in the illustrated embodiment, the method700begins by a controller204A,204B,300A, or300B (e.g., one or more processors) receiving a trigger signal from a switch (e.g., switch S1or S2) in a security switch108indicating that a tamper state of the switch S1or S2has been mechanically triggered and/or tripped (block702). In some embodiments, the tamper state of the switch S1or S2, in some embodiments, indicates that a chassis102has experienced a chassis tamper event. In other words, the chassis102has been opened and/or compromised.

In response to the trigger signal, the controller204A,204B,300A, or300B turns OFF one or more secure elements106(block704), notifies a user of the chassis tamper event (block706), and notifies the user that the secure element(s)106is/are turned OFF (block708). The controller204A,204B,300A, or300B receives one or more authentication inputs from the user (block710) and verifies whether the user is an authorized user (block712). The user can be verified as an authorized user using any of the techniques and/or method discussed elsewhere herein.

The controller204A,204B,300A, or300B then turns ON the one or more secure elements106in response to verifying that the user is an authorized user (block714). In further response to verifying that the user is an authorized user, the controller204A,204B,300A, or300B transmits a reset signal to the switch S1or S2to reset to the switch S1or S2(block716). The switch S1or S2may be reset using any of the reset techniques and/or methods discussed elsewhere herein.

FIG. 8is a schematic flow chart diagram illustrating an embodiment of a chassis security method800for an apparatus100. At least in the illustrated embodiment, the method800begins by a controller204A,204B,300A, or300B (e.g., one or more processors) monitoring a switch S1or S2(block802) to detect and/or determine whether the switch S1and S2has experienced a mechanical trigger indicative of a chassis tamper event (block804).

In response to the switch S1and S2not experiencing a mechanical trigger (e.g., a “NO” in block804), the controller204A,204B,300A, or300B continues monitoring the switch S1or S2(return806). In response to the switch S1and S2experiencing a mechanical trigger (e.g., a “YES” in block804), the controller204A,204B,300A, or300B turns OFF one or more secure elements106(block808) and sends a notification to the user (block810). The notification can notify the user of the chassis tamper event and/or notify the user that the secure element(s)106is/are turned OFF.

The controller204A,204B,300A, or300B receives one or more authentication inputs from the user (block812) and verifies whether the user is an authorized user (block814). The user can be verified as an authorized user using any of the techniques and/or method discussed elsewhere herein.

In response to the user not being verified as an authorized user (e.g., a “NO” in block814), the controller204A,204B,300A, or300B does nothing and/or waits to receive one or more authentication inputs in block812(return816). In response to the user being verified as an authorized user (e.g., a “YES” in block814), the controller204A,204B,300A, or300B turns ON the one or more secure elements106(block818).

The controller204A,204B,300A, or300B can then transmit a reset signal to the switch S1or S2to reset to the switch S1or S2(block820). The switch S1or S2may be reset using any of the reset techniques and/or methods discussed elsewhere herein. The controller204A,204B,300A, or300B then returns to monitoring the switch S1or S2in block802(return822).

The various embodiments disclosed herein allow and/or enable a chassis tamper event to be detected both when the apparatus100has power and when the apparatus does not have power. Because the apparatus100can detect a chassis tamper event when the apparatus100does not have power, the various embodiments disclosed herein may not consider a power loss state as a chassis tamper event.