Semiconductor memory device

A semiconductor memory device including memory cells, formed by a pair of multi-emitter transistors each having a collector and a base which are cross connected to each other and arranged in row and column directions, and read-out transistors, each having an emitter which is commonly connected to one of the emitters of the multi-emitter transistors, wherein the read-out transistors are arranged in each column. The multi-emitter transistors and the read out transistors are formed in patterns and the characteristics of both the multi-emitter and read-out transistors have the same variation due to a dispersion of the patterns caused by the manufacturing process.

FIELD OF THE INVENTION 
The present invention relates to a semiconductor memory device; more 
particularly to an improvement in a semiconductor memory device having 
memory cells formed by a pair of multi-emitter transistors, each having a 
collector and a base cross-connected to each other, and read-out 
transistors having emitters connected to one of the emitters of the 
multi-emitter transistors. 
BACKGROUND OF THE INVENTION 
With an increase in the memory capacity of a semiconductor memory device, 
the size of the memory cells forming the semiconductor memory device has a 
tendency to decrease. When the size of the memory cells is decreased, 
characteristics of the transistors which form the memory cells are 
affected by a dispersion of the transistors caused by the manufacturing 
process. For example, as the width of a window for an electrode, such as 
an emitter electrode varies, or the size of the window for an electrode 
varies, due to the manufacturing process, the forward current of the diode 
between the base and emitter of the transistor varies. If the position of 
the window for the electrode is not at the correct position, the base 
resistance of the transistor varies. When the characteristics of the 
transistors which form the memory cells vary due to the manufacturing 
process, as mentioned above, sometimes, information stored in the memory 
cells cannot be read out or, the information may be destroyed. 
SUMMARY OF THE INVENTION 
An object of the present invention is to provide a semiconductor memory 
device which is not affected by a variation in the characteristics of the 
transistors. Another object of the present invention is to provide a 
semiconductor memory device which avoids a decrease in the margin of 
circuit operation due to a dispersion of the characteristics of the 
transistors caused during the manufacturing process. 
The above mentioned objects can be achieved by a semiconductor memory 
device having memory cells, formed by a pair of multi-emitter transistors, 
each having a collector and a base which are cross-connected to each other 
are arranged in row and column directions, and read-out transistors having 
an emitter commonly connected to one of the emitters of the multi-emitter 
transistors arranged in a row direction. The multi-emitter transistors and 
the read-out transistors are formed by patterns having the same 
characteristic variation due to a dispersion of the patterns caused during 
the manufacturing process. 
Further features and advantages of the present invention will be apparent 
from the ensuing description with reference to the accompanying drawings 
to which, however, the scope of the invention is in no way limited.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
FIG. 1 is a circuit diagram of a conventional semiconductor memory device 
including a plurality of memory cells MC.sub.11, MC.sub.12, . . . arranged 
in a row direction and a column direction as illustrated in FIG. 1. 
Referring to FIG. 1, WD.sub.1, WD.sub.2, . . . denote row selection means 
for selecting the memory cells MC.sub.11, MC.sub.12 . . . arranged in the 
row direction, and B.sub.1, B.sub.2, . . . BT.sub.11, BT.sub.12 . . . 
denote column selection means for selecting the memory cells MC.sub.11, 
MC.sub.12 . . . arranged in the column direction. Read-out transistors 
TR.sub.11, TR.sub.12, TR.sub.21, TR.sub.22, . . . are provided in each 
column so as to read out information stored in the memory cells MC.sub.11, 
MC.sub.12 . . . . These read-out transistors TR.sub.11, TR.sub.12, 
TR.sub.21, TR.sub.22 . . . are also used for writing information into the 
memory cells MC.sub.11, MC.sub.12 . . . , RWC denotes a read and write 
circuit. As is well known, the memory cells MC.sub.11, MC.sub.12 are 
formed by multi-emitter transistors TC.sub.1 and TC.sub.2 which form a 
flip-flop circuit. Emitters TC.sub.12, TC.sub.22 of the multi-emitter 
transistors TC.sub.1 and TC.sub.2 are connected to a current source i for 
holding the information in the memory cells, and emitters TC.sub.11, 
TC.sub. 21 of the multi-emitter transistors TC.sub.1, TC.sub.2 are 
connected to bit lines B.sub.11 and B.sub.12 respectively. 
An operation of the circuit illustrated in FIG. 1 is as described below. 
If the row selection means WD.sub.1 and the column selection means B.sub.1 
are selected, the memory cell MC.sub.11 is selected. If the transistor 
TC.sub.1 is in an ON state and the transistor TC.sub.2 is in an OFF state, 
a current which flows from the emitter TC.sub.12 to the current source i 
is changed to a current which flows from the emitter TC.sub.11 to the bit 
line B.sub.11. An emitter of the read out transistor TR.sub.11 is coupled 
to the emitter TC.sub.11 of the transistor TC.sub.1 and an emitter of the 
read-out transistor TR.sub.12 is coupled to the emitter TC.sub.21 of the 
transistor TC.sub.2 so as to operate as a current switch. Therefore, the 
current from the emitter TC.sub.11 of the transistor TC.sub.1 flows in the 
bit line B.sub.11 and the current from the emitter of the read-out 
transistor TR.sub.12 flows in the bit line B.sub.12. Accordingly, the 
collector of the read-out transistor TR.sub.11 is placed at a high 
potential level and the collector of the read-out transistor TR.sub.12 is 
placed at a low potential level, so that the content of the memory cell 
MC.sub.11 is read out by the read and write circuit RWC. 
In the semiconductor memory device illustrated in FIG. 1, the transistors 
TC.sub.1 and TC.sub.2 and the read-out transistors TR.sub.11 and TR.sub.12 
have emitters which are coupled respectively and operated as a current 
switch. However, the characteristics of the transistors TC.sub.1, TC.sub.2 
and the read-out transistors TR.sub.11, TR.sub.12 vary during the 
manufacturing process. For example, if the size of the window for an 
emitter electrode varies during the manufacturing process, the forward 
current through the base and the emitter of the transistors TC.sub.1, 
TC.sub.2, TR.sub.11, TR.sub.12 disperses, or if the window for the 
electrode is not at the correct position, the base resistance or the 
current amplification factor disperses. If the characteristics of the 
read-out transistors TR.sub.11, TR.sub.12 and the transistors TC.sub.1, 
TC.sub.2 in the memory cell MC.sub.11 are different, it may not always be 
possible to correctly read out information stored in the memory cells and 
the information may even be destroyed. 
FIG. 2 is a circuit diagram of one embodiment of the semiconductor memory 
device according to the present invention, and referring to FIG. 2, 
portions corresponding to portions illustrated in FIG. 1 are designated by 
the same symbols as those used in FIG. 1. 
The circuit illustrated in FIG. 2 is different from the circuit illustrated 
in FIG. 1, in that the read-out transistors T.sub.11, T.sub.12 are formed 
by a multi-emitter transistors, and the emitters Te.sub.11, Te.sub.12 of 
the read-out transistors T.sub.11, T.sub.12, respectively, are connected 
to the bit lines B.sub.11 and B.sub.12, respectively, and the emitters 
Te.sub.12, Te.sub.22 of the read-out transistors T.sub.11, T.sub.12, 
respectively are connected to bit lines B.sub.21, B.sub.22, respectively. 
In the circuit illustrated in FIG. 2, the read-out transistors TR.sub.11, 
TR.sub.12, TR.sub.21, TR.sub.22 illustrated in FIG. 1 are replaced by the 
multi-emitter transistors T.sub.11 and T.sub.12, and therefore, the 
operation of the circuit illustrated in FIG. 2 is quite similar to the 
circuit illustrated in FIG. 1. Therefore, the operation of the circuit 
illustrated in FIG. 2 is omitted herein. 
FIG. 3A illustrates a plan view of one embodiment of the transistors used 
in the circuit illustrated in FIG. 2, and FIG. 3B is a cross-sectional 
view along line A--A of FIG. 3A. In FIG. 3A, the relationship between the 
memory cells MC.sub.11, MC.sub.12, the read-out transistors T.sub.11, 
T.sub.12 and the bit lines B.sub.11, B.sub.12, B.sub.21, B.sub.22, are 
illustrated. Referring to FIG. 3A, e.sub.11, e.sub.21, e.sub.12 and 
e.sub.22 in the read-out transistors T.sub.11 and T.sub.12 correspond, 
respectively, to emitters Te.sub.11, Te.sub.21, Te.sub.12, Te.sub.22 of 
the transistors T.sub.11 and T.sub.12 ; and b and c in the transistors 
T.sub.11 and T.sub.12 respectively denote a base and collector of the 
transistors T.sub.11 and T.sub.12. The symbols E.sub.11, E.sub.12, 
E.sub.21 and E.sub.22 in the memory cell MC.sub.11 correspond to the 
emitters TC.sub.11, TC.sub.12, TC.sub.21 and TC.sub.22 of the transistors 
TC.sub.1, TC.sub.2, respectively; and B and C in the memory cell MC.sub.11 
correspond to the base and the collector of the transistors TC.sub.1 and 
TC.sub.2 respectively. Further, in FIG. 3A, SBD denotes a Shottky Barrier 
diode, and R denotes a resistor. 
Referring to FIG. 3B, 11 denotes a substrate, 12 denotes a buried layer, 13 
denotes an isolation region, 14 denotes a collector region, 15 denotes an 
insulation layer, 16 denotes a Shottky Barrier diode corresponding to the 
SBD of FIG. 3A, 17 denotes a base region, 17a denotes a base electrode 
corresponding to the base B of FIG. 3A, 18 denotes an emitter region, 18a 
denotes an emitter electrode corresponding to one of the emitters E.sub.11 
or E.sub.12 of FIG. 3A, and 19 denotes a resistor corresponding to the 
resistor R of FIG. 3A. 
A major advantage of the construction illustrated in FIG. 3A is 
compensation of the variation of the distance between the base B and the 
emitter E.sub.21 in the cell MC.sub.11 and a variation of the distance 
between the base B and the emitter E.sub.11 of the memory cell MC.sub.12. 
As can be understood from FIG. 3A, the construction of each of the 
transistors TC.sub.1 and TC.sub.2 in the memory cells MC.sub.11 and 
MC.sub.12 is the same as that of one of the read-out transistors T.sub.11 
and T.sub.12. Therefore, if the position or size of the electrode window 
varies due to the dispersion caused by the manufacturing process, so that 
the characteristics of the transistor vary, the construction of the 
read-out transistors T.sub.11 and T.sub.12 becomes equivalent to the 
construction of the transistors TC.sub.1, TC.sub.2 which form the memory 
cells MC.sub.11 and MC.sub.12, so that a variation in the characteristics 
of the transistors can be compensated for. More particularly, the 
variation in the base resistance, due to the distance between the base and 
the emitter, of the read-out transistor T.sub.11, having an emitter 
e.sub.21 connected to the bit line B.sub.21, becomes equivalent to the 
variation of the base resistance of the transistors in the memory cells, 
which have emitters commonly connected to the bit line B.sub.21. 
Furthermore, the transistors, which have emitters commonly connected to 
the bit line B.sub.12, are varied in a similar fashion. Therefore, read 
out of the information is not disadvantageously affected, and destruction 
of the information can be prevented. 
FIG. 4A illustrates a plan view of another embodiment of the transistors 
used in the circuit illustrated in FIG. 2 and FIG. 4B is a cross-sectional 
view along line B--B of FIG. 4A. Referring to FIGS. 4A and 4B, portions 
corresponding to portions illustrated in FIGS. 3A and 3B are designated by 
the same symbols. 
The advantage of the construction illustrated in FIG. 4A is in compensation 
for the dispersion of the current amplification factor of the transistor 
due to the position of the emitter near an isolation region. As can be 
understood from FIG. 4A, the construction of the transistors in the memory 
cells MC.sub.11 and MC.sub.12 are the same as the read-out transistors 
T.sub.11 and T.sub.12. Therefore, if the position of the emitter varies 
due to the dispersion caused by the manufacturing process, so that the 
current amplification factor of the transistor varies, the construction of 
the read-out transistors T.sub.11 and T.sub.12 becomes equivalent to the 
construction of the transistors which form the memory cells MC.sub.11, 
MC.sub.12 . . . having emitters commonly connected to the same bit line as 
the read-out transistors T.sub.11 and T.sub.12, and the variation of the 
current amplification factor of the transistors can be compensated for. 
Therefore, read-out of information is not disadvantageously affected, and 
destruction of the information can be prevented. 
As mentioned above, a semiconductor memory device includes a plurality of 
memory cells arranged in row and column directions, selection means for 
selecting the row and the column and read-out transistors which are 
provided in each column for reading out the information stored in the 
memory cells. According to the features of the present invention, the 
read-out transistors and the transistors in the memory cells, which have 
emitters commonly connected to a common bit line, are formed by the same 
construction. Therefore, if the characteristics of the transistors vary 
due to the manufacturing process, the characteristics of the transistors 
in the memory cells can provide the same characteristics as the read-out 
transistors so that neither a read out nor a storage of the information in 
the memory cells is adversely affected. 
In the embodiment illustrated in FIG. 2, the emitters Te.sub.11, Te.sub.12, 
Te.sub.21 and Te.sub.22 of the read-out transistors T.sub.11 and T.sub.12 
are connected to the column bit lines B.sub.11, B.sub.12, B.sub.21 and 
B.sub.22, respectively. However, it is understood that the effect of the 
present invention can be expected in a case when a transistor having one 
emitter is used as the read-out transistor, the emitters of which are 
connected to a column bit line of the memory matrix such as the bit line 
B.sub.11, and the multi-emitter transistors are used as the read-out 
transistors the emitters of which are connected two column bit lines such 
as the bit lines B.sub.12 and B.sub.21.