Method for manufacturing semiconductor device having dual gate dielectric layer

Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0026721, filed on Mar. 15, 2012, the entirety of which is incorporated by reference herein.

FIELD

The inventive concept relates to methods for manufacturing a semiconductor device having a dual gate dielectric layer including gate dielectric layers having thicknesses that are different from each other.

BACKGROUND

A semiconductor device may include gate dielectric layers respectively having thicknesses different from each other by a replacement metal gate (RMG) process called a “gate last process.” A high-voltage region may need a relatively thick gate dielectric layer and a low-voltage region may need a relatively thin gate dielectric layer. The semiconductor device including the gate dielectric layers having different thicknesses may be manufactured in the high-voltage region and the low-voltage region by the gate last process.

SUMMARY

In accordance with various aspects of the inventive concept, there are provided methods for manufacturing a semiconductor device having improved reliability of transistors thereof.

In one aspect, a method for manufacturing a semiconductor device may include: providing a substrate including a first region and a second region; forming a first gate dielectric layer having a first thickness on the substrate; forming an interlayer insulating layer on the substrate, the interlayer insulating layer including a first trench exposing the first gate dielectric layer of the first region and a second trench exposing the first gate dielectric layer of the second region; forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches; forming a mask pattern covering the second trench of the second region on the sacrificial layer; removing the sacrificial layer in the first region using the mask pattern as an etch mask to form a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench; removing the first gate dielectric layer of the bottom of the first trench to expose the substrate; removing the mask pattern; removing the sacrificial pattern; forming a second gate dielectric layer having a second thickness on the bottom of the first trench; and forming a gate electrode on each of the first gate dielectric layer and the second gate dielectric layer.

Forming the interlayer insulating layer, including the first trench and the second trench, may comprise forming a first dummy gate pattern on the first gate dielectric layer of the first region, forming a second dummy gate pattern on the first gate dielectric layer of the second region, forming an the interlayer insulating layer exposing top surfaces of the first dummy gate pattern and the second dummy gate pattern, and removing the first dummy gate pattern and the second dummy gate pattern.

The method further comprises forming a spacer on a sidewalls of each of the first and second dummy gate patterns.

The method may further comprise forming a high-k dielectric material between each of the gate electrodes and each of the first and second gate dielectric layers.

The sacrificial layer may include at least one of a silicon oxide layer, a silicon nitride layer, a poly-crystalline silicon layer, and a metal layer.

The sacrificial layer may be formed by an atomic layer deposition (ALD) method.

Removing the sacrificial layer in the first region using the mask pattern as the etch mask may be performed using a solution including at least one of hydrogen fluoride, phosphoric acid, sulfuric acid, hydrogen peroxide, ammonium hydroxide, hydrogen chloride, and amine.

Removing the first gate dielectric layer of the bottom of the first trench to expose the substrate may be performed by a chemical oxide removal (COR) method using a HF gas and a NH3 gas, or a chemical etching by plasma (CEP) method using NH3 and NF3 remote plasma.

The mask pattern may be formed of a photoresist.

Removing the mask pattern may be performed using an organic stripper, sulfuric acid, or a mixture solution of sulfuric acid and hydrogen peroxide.

The method may include forming a chemical oxide layer on the substrate exposed by the first trench when the mask pattern is removed and removing the chemical oxide layer simultaneously with the sacrificial pattern when the sacrificial pattern is removed.

The method may include forming the first gate dielectric layer by a dry oxidation method or a radical oxidation method.

The method may include forming the second gate dielectric layer by a chemical oxidation method.

The first thickness of the first gate dielectric layer may be greater than the second thickness of the second gate dielectric layer.

The gate electrode may include at least one of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, copper, aluminum and any combination thereof.

Removing the sacrificial pattern may be performed simultaneously with the formation of the second gate dielectric layer having the second thickness on the bottom of the first trench.

The method may include forming the sacrificial layer of titanium nitride, wherein forming the second gate dielectric layer may be performed using a solution including ammonium hydroxide and hydrogen peroxide or a solution including ozone.

In another aspect, a method for manufacturing a semiconductor device may include: providing a substrate including a first region and a second region; forming a first gate dielectric layer having a first thickness on the substrate; forming an interlayer insulating layer on the substrate, the interlayer insulating layer including a first trench exposing the first gate dielectric layer of the first region and a second trench exposing the first gate dielectric layer of the second region; forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches; forming a mask pattern covering the second trench of the second region on the sacrificial layer; removing the sacrificial layer in the first region using the mask pattern as an etch mask to form a sacrificial pattern covering the second trench; removing the mask pattern; removing the first gate dielectric layer of the bottom of the first trench using the sacrificial pattern as an etch mask to expose the substrate; forming a second gate dielectric layer having a second thickness on the bottom of the first trench; and forming a gate electrode on each of the first gate dielectric layer and the second gate dielectric layer.

The method may further comprise forming a high-k dielectric material between each of the gate electrodes and each of the first and second gate dielectric layers.

In still another aspect, a method for manufacturing a semiconductor device may include: providing a substrate including a first region and a second region; forming a first gate dielectric layer having a first thickness on the substrate; forming an interlayer insulating layer on the substrate, the interlayer insulating layer including a first trench exposing the first gate dielectric layer of the first region and a second trench exposing the first gate dielectric layer of the second region; forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches; forming a mask pattern covering the second trench of the second region on the sacrificial layer; removing the sacrificial layer in the first region using the mask pattern as an etch mask to form a sacrificial pattern; removing an upper portion of the first gate dielectric layer of the bottom of the first trench to form a second gate dielectric layer having a second thickness smaller than the first thickness; and forming a gate electrode on each of the first gate dielectric layer and the second gate dielectric layer.

According to another aspect of the invention, provided is a method for manufacturing a semiconductor device having a dual gate dielectric layer. The method includes: providing a substrate including first and second regions; forming a first gate dielectric layer having a first thickness on the substrate; forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions; forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches; forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench; forming a second gate dielectric layer having a second thickness on the bottom of the first trench; removing the sacrificial pattern; and forming a gate electrode on each of the first and second gate dielectric layers.

The second dielectric layer may be thinner than the first dielectric layer.

The method may further comprise forming a high-k dielectric material between each of the gate electrodes and each of the first and second gate dielectric layers.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The exemplary embodiments in accordance with the inventive concept will now be described hereinafter with reference to the accompanying drawings. Various advantages and features of the inventive concept and methods of achieving them will be apparent from the following exemplary embodiments. It should be noted, however, that the inventive concept is not limited to the following exemplary embodiments, and may be implemented in various forms. In the drawings, embodiments of the inventive concept are not limited to the specific examples provided herein and are exaggerated for clarity.

Additionally, the embodiments presented in the detailed description will be described with respect sectional views provided in the drawings, which are provided as ideal exemplary views of semiconductor devices in accordance with the inventive concept. Accordingly, shapes presented in the exemplary views may be modified according to manufacturing techniques and/or allowable errors. Therefore, the inventive concept is not limited to the specific exemplary views provided in the figure or the shapes shown therein, but may include other shapes that may be the result of or dictated by various manufacturing processes. Areas exemplified in the drawings have general properties, and should not be construed as limiting the scope of the inventive concept.

Methods for manufacturing a semiconductor device according to various embodiments of the inventive concept will be described with reference toFIGS. 1 to 16.FIGS. 1 through 8,9A,10A, and11through16are cross-sectional views illustrating a method for manufacturing a semiconductor device according to some embodiments of the inventive concept. For the purposes of ease and convenience, source/drain regions formed in a substrate and metal interconnection layers disposed over transistors are omitted in the drawings. However, those skilled in the art will readily understand and appreciate the presence of source/drain regions in a transistor.

Referring to the embodiment ofFIG. 1, a substrate110is provided. The substrate110may be a silicon substrate, for example, a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In other embodiments, the substrate110may include a material different from the silicon substrate. As examples, the substrate110may include germanium, indium antimonide, lead-tellurium compound, indium-arsenic, indium phosphide, gallium-arsenic, or gallium antimonide.

The substrate110may include a first region I and a second region II. The first region I and the second region II may have electrical characteristics different from each other, respectively. For example, the first region I may be a region in which a transistor operated by a low-voltage is formed, and the second region II may be a region in which a transistor operated by a high-voltage is formed. Therefore, the voltage of the second region II is higher than the voltage of the first region I.

Device isolation layers120may be formed at a boundary of the first and second regions I and II. In the present embodiment, a device isolation layer120is formed in each of the first region I and the second region II, respectively.

Referring to the embodiment ofFIG. 2, a first gate dielectric layer130is formed on the substrate110. The first gate dielectric layer130may be formed using a dry oxidation method or a radical oxidation method, as an example. The dry oxidation method or the radical oxidation method may use an oxygen (O2) gas and a hydrogen (H2) gas to form a silicon oxide layer having a thickness (T1) within a range of about 25 Å to about 38 Å. Particularly, the first gate dielectric layer130may be a silicon oxide layer having a thickness of about 33 Å. The radical oxidation method may reduce a formation time of the first gate dielectric layer130as compared with that of the dry oxidation method.

Referring to the embodiment ofFIG. 3, first and second dummy gate patterns131and132are formed on the first gate dielectric layer130. The first and second dummy gate patterns131and132may be formed in the first and second regions I and II, respectively. Portions of the first gate dielectric layer130beyond the first and second dummy gate patterns131and132may be removed or not be removed.FIG. 3illustrates the embodiment wherein the first gate dielectric layer130beyond the first and second dummy gate patterns131and132has been removed. The first and second dummy gate patterns131and132may be formed of a semiconductor material, for example, poly-crystalline silicon.

A spacer133may be formed on sidewalls of each of the first and second dummy gate patterns131and132. The spacer133may be formed of a silicon nitride layer and/or a silicon oxynitride layer, as examples. However, in some embodiments, the spacer133may not be formed, e.g., to streamline a manufacturing process.

Referring to the embodiments ofFIGS. 4 and 5, an interlayer insulating layer140may be formed to cover the dummy gate patterns131and132formed in the first and second regions I and II. The interlayer insulating layer140may be a silicon oxide layer formed by a high-density plasma (HDP) method or a flowable chemical vapor deposition (FCVD) method, as examples. The interlayer insulating layer140may be planarized to expose top surfaces of the first and second dummy gate patterns131and132, as shown inFIG. 5. The planarization of the interlayer insulating layer140may be performed using an etch-back process or a chemical mechanical polishing (CMP) process, as examples.

Referring to the embodiment ofFIG. 6, the first and second dummy gate patterns131and132are removed to form a first trench151and a second trench152in the first region I and the second region II, respectively. Accordingly, the first gate dielectric layer130may be exposed in both regions.

Referring to the embodiment ofFIG. 7, a sacrificial layer155is conformally formed to cover a top surface interlayer insulating layer140, sidewalls and a bottom of the first trench151, and sidewalls and a bottom of the second trench152. Thus, the sacrificial layer155may be formed on the first gate dielectric layer130at the bottoms of the first and second trenches151,152. The sacrificial layer155may be formed using an atomic layer deposition (ALD) method or a chemical vapor deposition (CVD) method, as examples. In the presently preferred embodiment, the sacrificial layer155may be formed by the ALD method. When the sacrificial layer155is formed using the ALD method, the sacrificial layer155may be more conformally formed on the sidewalls and the bottoms of the first and second trenches151and152.

In various embodiments, the sacrificial layer155may include at least one of a silicon oxide layer, a silicon nitride layer, a poly-crystalline silicon layer, and a metal layer. The metal layer may include titanium, titanium nitride, tantalum, and/or a tantalum nitride, examples.

Referring to the embodiments ofFIGS. 8 and 9A, a mask pattern160may be formed on the sacrificial layer155of the second region II to cover the second trench152. As shown inFIG. 9A, the sacrificial layer155of the first region I may be removed using the mask pattern160as an etch mask thereby exposing the first gate dielectric layer130of the bottom of the first trench151. For example, the sacrificial layer155of the first region I may be removed by a solution including at least one of hydrogen fluoride, phosphoric acid, sulfuric acid, hydrogen peroxide, ammonium hydroxide, hydrogen chloride, and amine. As a result of such etching, the sacrificial layer155is patterned to form a sacrificial pattern156in the second region II.

The mask pattern160may be formed of photoresist. In various embodiments, a portion of the mask pattern160may further extend into the first region I. Alternatively, in other embodiment, a width of the mask pattern160may be limited in order to cover only the second trench152. In other words, in various embodiments, the width of the mask pattern160may be changed within a range which is able to expose the sacrificial layer155disposed on the sidewall and the bottom of the first trench151of the first region I.

Referring to the embodiment ofFIG. 10A, the first gate dielectric layer130at the bottom of the first trench151is removed using the mask pattern160and the interlayer insulating layer130as etch masks to expose the substrate110in the first trench I.

The removal of the first gate dielectric layer130in the first trench151may be performed by a chemical oxide removal (COR) method using a HF gas and a NH3gas, or a chemical etching by plasma (CEP) method using NH3and NF3remote plasma, as examples. As a result, an exposed top surface of the interlayer insulating layer140may be partially etched.

Referring to the embodiment ofFIG. 11, the mask pattern160in the second region II is removed to expose the sacrificial pattern156. The mask pattern160may be removed using an organic stripper, sulfuric acid, or a high temperature SPM (sulfuric acid (H2SO4)+hydrogen peroxide (H2O2) mixture) process, as examples. Oxygen atoms included in a solution of the high temperature SPM process may react with silicon atoms of the substrate110exposed by the first trench151in the first region I. Thus, a chemical oxide layer170may be formed. Since the chemical oxide layer170may have a poor quality, it may be unsuitable to be used as a gate dielectric layer of a transistor. Thus, it is preferable to remove the chemical oxide layer170.

Referring to the embodiment ofFIG. 12, the sacrificial pattern156in the second region II is removed to expose the first gate dielectric layer130of the bottom of the second trench152in the second region II. The chemical oxide layer170may be removed by the process used to remove the sacrificial pattern156. Alternatively, the chemical oxide layer170may be removed by an additional process, before the sacrificial pattern156is removed.

The sacrificial pattern156may be removed by a solution including at least one of hydrogen fluoride, phosphoric acid, sulfuric acid, hydrogen peroxide, ammonium hydroxide, hydrogen chloride, and amine.

If the sacrificial layer155is formed of a poly-crystalline silicon layer, the sacrificial pattern156may be effectively removed by ammonium hydroxide and/or amine. The amine may include tetramethylammonium hydroxide (TMAH), tetraethylammonium hydroxide (TEAH), or tetrapropylammonium hydroxide (TPAH).

Referring to the embodiment ofFIG. 13, a second gate dielectric layer180is formed on the bottom of the first trench151in the first region I. The second gate dielectric layer180is thinner than the first gate dielectric layer130formed in the second region II. That is, the second dielectric layer180can have a thickness T2that is less than the thickness of the first gate dielectric layer T1. Thus, if T1is about 38 Å, T2may be less that about 38 Å. The second gate dielectric layer180may be formed using a chemical oxidation formation method, as an example.

Referring to the embodiment ofFIG. 14, a high-k dielectric material185may be formed on the first and second gate dielectric layers130and180. The high-k dielectric material185may include at least one of a hafnium oxide, a hafnium-silicon oxide, a lanthanum oxide, a zirconium oxide, a zirconium-silicon oxide, a tantalum oxide, a titanium oxide, a barium-strontium-titanium oxide, a barium-titanium oxide, a strontium-titanium oxide, a lithium oxide, an aluminum oxide, a lead-scandium-tantalum oxide, and a lead-zinc niobate.

Referring to the embodiment ofFIG. 15, a gate electrode layer190is formed on the high-k dielectric material185. If the high-k dielectric material185is not formed, the gate electrode layer190may be formed on the second gate dielectric layer180at the bottom of the first trench151, the first gate dielectric layer130at the bottom of the second trench152, and the top surface of the interlayer insulating layer140.

Referring to the embodiment ofFIG. 16, the gate electrode layer190and the high-k dielectric material185are planarized until the interlayer insulating layer140is exposed. As a result, a gate electrode192is formed in each of the first and second trenches151and152, respectively. The planarization process used on the gate electrode layer190may be performed using an etch-back process or a chemical mechanical polishing (CMP) process, as examples. The gate electrode layer190may include at least one of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, copper, aluminum and any combination thereof.

Another embodiment method for manufacturing a semiconductor device according to aspects of the inventive concept will be described with reference to the embodiments ofFIGS. 9A,9B,10B,12, and13. For the purposes of ease and convenience, differences between the present embodiment and the aforementioned embodiments will be mainly described hereinafter.

Referring to the embodiment ofFIG. 9Aagain, the sacrificial layer155of the first region I is removed using the mask pattern160as an etch mask to form the sacrificial pattern156exposing the first gate dielectric layer130of the bottom of the first trench151.

Referring to the embodiments ofFIGS. 9B and 10B, after the mask pattern160ofFIG. 9Ais removed, the exposed first gate dielectric layer130of the bottom of the first trench151of the first region I is removed using the sacrificial pattern156and the interlayer insulating layer140as etch masks to expose the substrate110at the bottom of the first trench151.

Referring again to the embodiments ofFIGS. 12 and 13, the sacrificial pattern156inFIG. 9Bis removed and then the second gate dielectric layer180, which is thinner than the first gate dielectric layer130, is formed on the bottom of the first trench151. Subsequent processes may be the same as described in the aforementioned some embodiments, such as those described with respect toFIGS. 14 through 16.

As described above, in various embodiments, if the mask pattern160is removed such that the substrate110at the bottom of the first trench151is exposed, the chemical oxide layer170may be formed on the exposed surface of the substrate110. (e.g., seeFIG. 11) However, according to the present embodiment, since the mask pattern160is removed such that the substrate110is not exposed, it is possible to prevent oxygen atoms in the solution removing the mask pattern160from reacting with silicon atoms the exposed substrate110. As a result, formation of the chemical oxide layer170may be prevented.

Another embodiment of a method for manufacturing a semiconductor device according to aspects of the inventive concept will be described with reference to the embodiments ofFIGS. 9A and 10C. For the purposes of ease and convenience, differences between the present embodiment and the aforementioned embodiments will be mainly described.

Referring toFIGS. 9A and 10C, after the sacrificial pattern156exposing the first gate dielectric layer130under the first trench151is formed as illustrated inFIG. 9A, an upper portion of the first gate dielectric layer130under the first trench151is etched to form a second gate dielectric layer180that is thinner than the first gate dielectric layer130at the bottom of the second trench152in the second region II.

The process used for etching the upper portion of the first gate dielectric layer130in the first trench151may be a wet etching process using an etch solution including hydrogen fluoride or a dry etching process using hydrogen and/or chlorine, as examples. The process used for etching the upper portion of the first gate dielectric layer130in the first trench151may be performed wherein the mask pattern160exists as illustrated inFIG. 9A. Alternatively, after the mask pattern160is removed, the upper portion of the first gate dielectric layer130under the first trench151may be etched using the sacrificial pattern156and the interlayer insulating layer140as etch masks.

Another embodiment of a method for manufacturing a semiconductor device according to aspects of the inventive concept will be described with reference to the embodiments ofFIGS. 10B and 13. For the purposes of ease and convenience, differences between the present embodiment and the aforementioned embodiment will be mainly described.

Referring to the embodiments ofFIGS. 10B and 13, the substrate110under the first trench110is exposed and then the second gate dielectric layer180is formed wherein the sacrificial pattern156is not removed. The sacrificial pattern156may be removed simultaneously with formation of the second gate dielectric layer180. For example, if the sacrificial pattern156is formed of a titanium nitride and the second gate dielectric layer180is formed using a solution including ammonium hydroxide and hydrogen peroxide or a solution including ozone, the sacrificial pattern156may be removed at the same time as the formation of the second gate dielectric layer180. In this case, it is possible to reduce manufacturing cost of the semiconductor device by process simplification.

According to the embodiments described above, the gate dielectric layers having better quality may be formed when transistors including the gate dielectric layers having different thicknesses from each other are formed on the substrate110in first and second regions I and II using a gate last process.

In some embodiments, the solution used for removing the mask pattern160may not be in contact with the substrate. Thus, it is possible to prevent the formation of the chemical oxide layer170caused by the reaction between the oxygen atoms in the solution removing the mask pattern160and the silicon atoms of the exposed substrate.

According to embodiments of the inventive concept, it is possible to decrease or prevent deterioration of reliability of transistors including the gate dielectric layers having different thicknesses from each other in a high-voltage region and a low-voltage region.