Method of manufacturing semiconductor device

Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2013-0137882, filed on Nov. 13, 2013, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Example embodiments relate to methods of manufacturing a semiconductor device, and more particularly, to methods of manufacturing a semiconductor device that includes a plurality of contacts (or contact patterns) and a plurality of interconnection lines (or interconnection patterns) located thereon.

As the integration of a semiconductor device increases, a design rule for the components of the semiconductor device decreases. Thus, a process of forming a plurality of contacts (or contact patterns) and a plurality of interconnection lines (or interconnection patterns) on the contacts in a highly-scaled semiconductor device is becoming increasingly complex and difficult. For example, a photo process margin between contacts and/or a photo process margin between interconnection lines in a highly-scaled semiconductor device are being reduced.

SUMMARY

Example embodiments provide a semiconductor device manufacturing method that may increase a photo process margin between contacts and/or a photo process margin between interconnection lines in a highly-miniaturized semiconductor device manufacturing process.

According to an example embodiment, a method of manufacturing a semiconductor device may include forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and spaced apart from each other in a first direction and a second direction perpendicular to the first direction, the etch control portion surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively short in the first direction and relatively side in the second direction.

Each of the isolated contact filling portions may be formed to have different first-directional distances between one side of each of the interconnection patterns to a boundary of a corresponding one of the contact holes in the second direction. One of the first-directional distance of the isolated contact filling portions along a virtual center line of the corresponding one of the contact holes may be greater than other one of the first-directional distances of the isolated contact filling portions along a virtual line in parallel with and spaced apart from the virtual center line.

The forming the isolated contact filling portions and the etch control layer may include forming the contact holes in the support layer, the contact holes being spaced apart from each other in the first direction and the second direction, depositing a contact interconnection layer on the support layer to fill the contact holes to form the isolated contact filling portions and the etch control portion.

The method may further include forming, before the forming of the isolated contact filling portions, a plurality of buried interconnection patterns on the support layer, the buried interconnection patterns extending in the first direction and being spaced apart from each other in the second direction such that the isolated contact filling portions to be subsequently formed are arranged between the buried interconnection patterns.

The forming interconnection patterns may include forming a mask pattern on the interconnection layer, the mask pattern being relatively narrow in the first direction and relatively wide in the second direction, and forming the interconnection pattern by etching the interconnection layer, the isolated contact filling portions, and the etch control portion by using the mask pattern as an etch mask while controlling an etch rate of the isolated contact filling portions by the etch control portion.

The interconnection pattern on the isolated contact filling portions may be formed such that first-directional distances between first-directional center points along the second direction and one side of the interconnection pattern are equal in the second direction. The interconnection pattern may include a first interconnection portion formed by etching the isolated contact filling portions and a second interconnection portion that is formed by etching the interconnection layer. The isolated contact filling portions and the etch control portion may be formed of a same material.

According to an example embodiment, a method of manufacturing a semiconductor device may include forming a plurality of word lines on a substrate, the word line extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, forming an interlayer insulating layer on the word lines and the substrate; forming direct contact holes between the word lines by etching the interlayer insulating layer and the substrate, the direct contact holes spaced apart from each other in the first direction and the second direction, forming isolated contact filling portions filling the direct contact holes and an etch control portions that surrounding the isolated contact patterns by depositing a contact interconnection layer, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming a bit line and a direct contact pattern on the direct contact holes and the interlayer insulating layer by photo-etching the interconnection layer, the isolated contact filling portions, and the etch control portion, the bit line and the direct contact pattern being relatively narrow in the first direction and relatively wide in the second direction.

Each of the isolated contact filling portions may be formed to have different first-directional distances between one side of at least one of the bit line and points at a boundary of a corresponding one of the direct contact holes in the second direction.

One of the first-directional distance of the isolated contact filling portions along a virtual center line of the corresponding one of the contact holes may be greater than other one of the first-directional distances of the isolated contact filling portions along a virtual non-center line in parallel with and spaced apart from the virtual center line.

The direct contact holes may be formed in parallel to the bit line in the second direction. The direct contact holes may be formed to incline with respect to one side of the bit line in the first direction.

A buried contact may be formed at one side of the bit line and the direct contact in the first direction.

According to an example embodiment, a method of manufacturing a semiconductor device may include forming a lower interconnection layer including isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes formed in a support layer and spaced apart from each other in a first direction and a second direction perpendicular to the first direction, the etch control portion covering the isolated contact filling portions, forming an upper interconnection layer on the lower interconnection layer, and forming interconnection patterns extending in the second direction by patterning the upper and lower interconnection layers, while controlling an etch rate of the isolated contact filling portions by the etch control portion.

First-directional distances between one side of each of the interconnection patterns to a boundary of a corresponding one of the contact holes may be different in the second direction.

One of the first-directional distance of the isolated contact filling portions along a virtual center line of the corresponding one of the contact holes may be greater than the other one of the first-directional distances of the isolated contact filling portions along a virtual line in parallel with and spaced apart from the virtual center line.

The etch control portion may cover at least one of top surfaces and side surfaces of the isolated contact filling portions and the isolated contact filling portions and the etch control portion may be formed of a same material.

DETAILED DESCRIPTION

Various example embodiments will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey example embodiments to those of ordinary skill in the art.

It will be understood that when an element is referred to as being “connected to” another element, it may be directly connected to the other element or intervening elements may be present. Likewise, it will be understood that when an element is referred to as being “on” another element, it may be directly on the other element or intervening elements may be present. Also, in the drawings, the structures or sizes of elements are exaggerated for clarity and convenience of description, and portions irrelevant to the description are omitted. Like reference numerals denote like elements throughout the specification and drawings.

Referring toFIGS. 1A to 1E, buried interconnection patterns11may be formed on a support layer10. The support layer10may be, for example, a silicon substrate. When the support layer10is a substrate, an insulating layer, for example, an oxide layer may be further formed on the support layer10. The support layer10may be an insulating layer.

As illustrated inFIG. 1E, the buried interconnection patterns11may extend in a first direction (X-axis direction) and may be spaced apart from each other in a second direction (Y-axis direction) that is perpendicular to the first direction. The buried interconnection patterns11may be word line patterns in the semiconductor device. In some cases, the buried interconnection patterns11may not be formed.

An interlayer insulating layer12may be formed on the support layer10and the buried interconnection patterns11. The interlayer insulating layer12may be formed on the support layer10, on the buried interconnection patterns11, and between the buried interconnection patterns11. The interlayer insulating layer12may be formed of, for example, an oxide layer. The interlayer insulating layer12may be formed to insulate the buried interconnection patterns11and upper interconnection patterns that will be formed later.

A first lower interconnection layer14may be formed on the interlayer insulating layer12. The first lower interconnection layer14may be formed on the support layer10. The first lower interconnection layer14may be formed of a conductive layer, for example, a metal layer. The first lower interconnection layer14may be formed of a doped polysilicon layer.

Referring toFIGS. 2A to 2E, a mask pattern16may be formed on the first lower interconnection layer14. The mask pattern16may be a photoresist pattern that is formed by a photo process. For example, the mask pattern16may be formed by forming a photoresist layer on the lower contact interconnection layer14and exposing and developing the photoresist layer.

By using the mask pattern16as an etch mask, the first lower interconnection layer14, the interlayer insulating layer12, and the support layer10may be sequentially etched to form a plurality of contact holes18. The contact holes18may be formed to expose one surface of the interlayer insulating layer12and/or the support layer10.

As illustrated inFIG. 2E, the contact holes18may be spaced apart from each other in the first direction (X-axis direction) and the second direction (Y-axis direction). Also, as illustrated inFIG. 2E, the contact holes18may be spaced apart from each other in the first direction (X-axis direction) and the second direction (Y-axis direction) while being formed between the buried interconnection patterns11. AlthoughFIGS. 2A and 2Cillustrate that the contact holes18are formed in the support layer10by etching an upper portion of the support layer10, the contact holes18may be formed on the support layer10by stopping the etching at a surface of the support layer10.

Referring toFIGS. 3A to 3E, the mask pattern16may be removed. Thereafter, a second lower interconnection layer may be formed on the first lower interconnection layer14to fill the contact holes18. The second lower interconnection layer may be formed on the support layer10. The second lower interconnection layer may be formed of a conductive layer, for example, a metal layer. The second contact interconnection layer may be formed of a doped polysilicon layer. After the forming of the second lower interconnection layer, the second lower interconnection layer may be etched back.

InFIGS. 3A to 3E, a resultant structure of the first lower interconnection layer14and second lower interconnection layer are collectively illustrated and referred to as a lower interconnection layer24″. The lower interconnection layer24may be formed on the interlayer insulating layer12to fill the contact holes18.

As illustrated inFIGS. 3A, 3C, and 3E, the lower interconnection layer24may include isolated contact filling portions20and an etch control portion22. The isolated contact filling portions20may refer to a portion of the lower interconnection layer24that fills the contact holes18. The isolated contact filling portions20may be located on the support layer10, and be spaced apart and isolated from each other in the first direction and the second direction. The etch control portion22may cover the isolated contact filling portions20. The isolated contact filling portions20and the etch control layer22may be formed of the same material.

The etch control portion22may refer to a portion of the lower interconnection layer24that does not fill the contact holes18. As will be described later, when forming the isolated contact filling portions20by patterning the lower interconnection layer24, the etch control portion22may serve to control an etch rate of the isolated contact filling portions20such that a profile of one sidewall of an interconnection pattern to be formed is vertical in a cross-sectional view and linear in a plan view.

Subsequently, an upper interconnection layer25aand a capping layer25bmay be formed on the lower interconnection layer24. In some cases, the capping layer25bmay not be formed. The upper interconnection layer25aand the capping layer25bmay be formed on the isolated contact filling portions20and the etch control portion22. The upper interconnection layer25amay be formed of a conductive layer. For example, the interconnection layer25amay be formed of a tungsten layer. The capping layer25bmay be formed of an insulating layer. For example, the capping layer25bmay be formed of a nitride layer. InFIG. 3E, the upper interconnection layer25aand the capping layer25bare not illustrated for convenience′ sake.

Referring toFIGS. 4A to 4E, the capping layer25B, the upper interconnection layer25a, and the lower interconnection layer24may be photo-etched to form interconnection patterns30and capping patterns29on the support layer10. For example, the capping layer25b, the upper interconnection layer25a, the isolated contact filling portions20, and the etch control portion22may be photo-etched to form the interconnection patterns30on the support layer10.

The interconnection patterns30and the capping patterns29may be formed by the following process.

For example, a mask pattern32may be formed on the capping layer25bto be relatively narrow in the first direction and to be relatively wide in the second direction. The mask pattern32may be a photoresist pattern that is formed by a photo process. For example, the mask pattern32may be formed by forming a photoresist layer (not illustrated) on the capping layer25band exposing and developing the photoresist layer. The capping patterns29and the interconnection patterns30may be formed by etching the capping layer25b, the interconnection layer25a, the isolated contact filling portions20, and the etch control portion22by using the mask pattern32as an etch mask while controlling an etch rate of the isolated contact filling portions20by the etch control portion22.

As illustrated inFIG. 4E, the interconnection patterns30may be formed to be relatively narrow in the first direction and to be relatively wide in the second direction. InFIG. 4E, the capping pattern29is not illustrated for convenience′ sake. Each of the interconnection patterns30may be divided into a lower interconnection portion26formed by etching the lower interconnection layer24and an upper interconnection layer28formed by etching the upper interconnection layer25a.

Due to the etch control portion22in the lower interconnection layer24, a profile of one sidewall of the interconnection pattern30may be vertical in a cross-sectional view and linear in the second direction in a plan view. This will be described with reference toFIG. 4F.

InFIGS. 4E and 4F, the capping pattern29is not illustrated for convenience′ sake. Referring toFIG. 4F, the isolated contact filling portions20included in the interconnection patterns30may be formed to have different internal distances along the second direction (e.g., Y-axis direction) to a side wall of the contact holes18. For example, an internal distance d1 between one side of the isolated contact filling portions20to a sidewall of the contact hole18along a virtual center line C1in the first direction (e.g., X-axis direction) may be greater than an internal distance d2 between the same side of the isolated contact filling portions20and the side wall of the contact hole18along a horizontal line C2other than the virtual center line C1.

Accordingly, when the isolated contact filling portions20are etched to form a lower portion of each of the interconnection patterns30, the etch control portion22may serve to control an etch rate of the isolated contact filling portions20. When no etch control portion22is used in the etching of the isolated contact filling portions20, protrusion patterns38may be formed at sides of the interconnection patterns30as represented by a reference numeral “38” inFIG. 4F. When the protrusion pattern38is formed at a side of the interconnection pattern30, the protrusion pattern38may short-circuits the interconnection pattern30with an adjacent conductive pattern36that may be formed at one side of a corresponding isolated contact filling portion20.

As described above, according to some example embodiments, the etch control portion22may be used to control an etch rate of the isolated contact filling portions20. When the isolated contact filling portions20fill the contact holes18, the etch control portion22may be additionally formed. Accordingly, the profile of sidewalls of the interconnection patterns30may be vertical in a cross-sectional view and linear in the second direction in a plan view. Accordingly, a photo process margin between contacts (or the isolated contact filling patterns) and a photo process margin between interconnection lines (or the interconnection patterns) in a highly-scaled semiconductor device may be increased. Also, a short-circuit problem between the interconnection patterns30and the adjacent conductive patterns36may be reduced or solved.

Hereinafter, an example embodiment of applying the manufacturing method ofFIGS. 1 to 4to an actual semiconductor device will be described. However, Example embodiments are not limited to the following example embodiment.

FIG. 5is a schematic layout diagram of a semiconductor device for illustrating a method of manufacturing a semiconductor device according to an example embodiment.

Referring toFIG. 5, a semiconductor device100according to an example embodiment may include a plurality of active regions ACT. The active regions ACT may be defined by an isolation layer114(seeFIG. 6A) formed on a substrate110(seeFIG. 6A). As the design rule of a semiconductor device decreases, the active region ACT may be disposed in a bar shape of a diagonal line or oblique line as illustrated inFIG. 5.

A plurality of word lines WL or gate lines, which extend in parallel to each other in the first direction (X-axis direction) across the active regions ACT and are spaced apart from each other in the second direction, may be disposed on the active regions ACT. The word lines WL may be disposed equidistantly. The width of the word line WL and/or the distance between the word lines WL may be determined according to a design rule. A plurality of bit lines BL, which extend in parallel to each other in the second direction (Y-axis direction) perpendicular to the word lines WL, may be disposed on the word lines WL. The bit lines BL may be disposed equidistantly. The width of the bit line BL and/or the distance between the bit lines BL may be determined according to a design rule.

The bit lines BL may be disposed in parallel to each other with a pitch of about 3 F therebetween. Also, the word lines WL may be disposed in parallel to each other with a pitch of about 2 F therebetween. Herein, F may refer to a minimum lithographic feature size. When the bit lines BL and the word lines WL are disposed with such a pitch therebetween, the memory device may include memory cells having a unit cell size of about 6 F2.

The semiconductor device100may include various contact arrays formed on the active regions ACT, for example, a direct contact DC, a buried contact BC, and a landing pad LP. The direct contact DC may refer to a contact that connects the active region ACT to the bit line BL, and the buried contact BC may refer to a contact that connects the active region ACT to a bottom electrode of a capacitor (not illustrated).

The buried contact BC and the active region ACT may have a very small contact area therebetween. Accordingly, the landing pad LP, which is conductive, may be introduced to increase at least one of a contact area of the active region ACT and a contact area of the bottom electrode of the capacitor. For example, the landing pad LP may be disposed at least between the active region ACT and the buried contact BC and between the buried contact BC and the bottom electrode of the capacitor. By increasing the contact area by introducing the landing pad LP, a contact resistance between the active region ACT and the bottom electrode of the capacitor may be reduced.

In the semiconductor device100, the direct contact DC may be disposed at a center portion of the active region ACT, and the buried contact BC may be disposed at both end portions of the active region ACT. Because the buried contact BC is disposed at both end portions of the active region ACT, the landing pad LP may be disposed to partially overlap with the buried contact BC while being adjacent to both ends of the active region ACT.

The word line WL may be formed in a buried structure in the substrate110of the semiconductor device100, and may be disposed across the active region ACT between the direct contacts DC and/or the buried contacts BC. As illustrated inFIG. 5, if two word lines WL are disposed across one active region ACT and the active region ACT is disposed in the shape of a diagonal line or oblique line, the active region ACT may have a desired (or alternatively, predetermined) angle of less than about 90° with respect to the word line WL.

The direct contact DC and the buried contact BC may be disposed symmetrically, and thus may be disposed on a straight line along the X axis and the Y axis. Unlike the direct contact DC and the buried contact BC, the landing pad LP may be disposed in a zigzag configuration L1in the second direction (Y-axis direction) in which the bit line BL extends. Also, the landing pad LP may be disposed to overlap with the same side portion of each bit line BL in the first direction (X-axis direction) in which the word line WL extends. For example, each of the landing pads LP on the first line may overlap with a left side surface of the corresponding bit line BL, and each of the landing pads LP on the second line may overlap with a right side surface of the corresponding bit line BL.

FIGS. 6A to 13Dare cross-sectional views for illustrating a method of manufacturing the semiconductor device illustrated inFIG. 5.

Referring toFIGS. 6A to 6E, an isolation trench112may be formed in a substrate110, and an isolation layer114may be formed in the isolation trench112. An active region116may be defined in the substrate110by the isolation layer114. As illustrated inFIGS. 5 and 6, the active region116may have an island shape having a minor axis and a major axis, and may be disposed in the shape of a diagonal line or oblique line to have an angle of less than about 90° with respect to a word line124to be formed at an upper portion thereof.

The substrate110may include silicon (Si), for example, crystalline Si, polycrystalline Si, or amorphous Si. In some example embodiments, the substrate110may include germanium (Ge), or a compound semiconductor (e.g., SiGe, silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). In some example embodiments, the substrate110of the semiconductor device100may include a conductive region, for example, a doped well or a doped structure.

The isolation layer114may be formed of one insulating layer, or the isolation layer114may include an outer insulating layer114A and an inner insulating layer114B as illustrated inFIGS. 6B to 6D. The outer insulating layer114A and the inner insulating layer114B may be formed of different materials. For example, the outer insulating layer114A may be formed of an oxide layer, and the inner insulating layer114B may be formed of a nitride layer. However, the configuration of the isolation layer114is not limited thereto. For example, the isolation layer114may be formed in a multilayer structure including a combination of at least three types of insulating layers.

A plurality of word line trenches118may be formed at the substrate110. The word line trenches118may extend in parallel to each other, and may have a linear shape extending across the active region116. As illustrated inFIG. 6B, in order to form the word line trench118having a trench portion formed at a bottom surface thereof, the isolation layer114and the substrate110may be etched by separate etching processes such that the etched depth of the isolation layer114is different from the etched depth of the substrate110.

The resulting structure including the word line trench118may be cleaned, and then a gate dielectric layer122, a word line124, and a buried insulating layer126may be sequentially formed in the word line trench118. Because the buried insulating layer126is formed on the word line124, the configuration and shape of the buried insulating layer126may be identical to the configuration and shape of the word line124as illustrated inFIG. 6E.

In some example embodiments, after forming the word line124, by using the word line124as a mask, dopant ions may be implanted into the substrate110at both sides of the word line124to form a source and drain regions (not shown) at a top surface of the active region116. A direct contact DC may be connected to the source region. In other example embodiments, the dopant ion implantation process for forming the source and drain regions may be performed before the forming of the word line124.

A top surface124T of the word line124may be lower than a top surface110T of the substrate110and/or a bottom surface of the word line124may have an uneven shape as illustrated inFIG. 6B. A saddle fin structure transistor (saddle FINFET) may be formed at the active region116. In some example embodiments, the word line124may be formed of at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), and tungsten silicon nitride (WSiN).

The gate dielectric layer122may be formed of at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, oxide/nitride/oxide (ONO), and a high-k dielectric layer that has a higher dielectric constant than a silicon oxide layer. For example, the gate dielectric layer122may have a dielectric constant of about 10 to about 25. In some example embodiments, the gate dielectric layer122may be formed of at least one of hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). Also, the gate dielectric layer122may be formed of HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2.

An interlayer insulating layer132may be formed on the buried insulating layer126, the substrate110, and the isolation layer114. The interlayer insulating layer132may be formed to expose the buried insulating layer126. As illustrated inFIG. 6E, the interlayer insulating layer132may be formed to extend along one side of the buried insulating layer126in the first direction (X-axis direction). The interlayer insulating layer132may be formed of an oxide layer. In some cases, the interlayer insulating layer132may be formed of, for example, tetraethylorthosilicate (TEOS), high density plasma (HDP), or boro-phospho silicate glass (BPSG). The interlayer insulating layer132may have a thickness of about 200 Å to about 400 Å.

As illustrated inFIGS. 6B to 6E, the buried insulating layer126may be recessed to form a groove133. In this case, a top surface126T of the buried insulating layer126may be lower than the top surface110T of the substrate110. When the buried insulating layer126is recessed, a channel length may be increased. In some example embodiments, the buried insulating layer126may not be recessed. Thus, the top surface126T of the buried insulating layer126may be located at substantially the same level as the top surface110T of the substrate110. The buried insulating layer126may be formed of, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or any combinations thereof. In the plan view ofFIG. 6E, the hatches of the cross-sectional views ofFIGS. 6A to 6Dare discriminated for convenience′ sake.

Referring toFIGS. 7A to 7E, a first lower interconnection layer210is formed on the interlayer insulating layer132and the buried insulating layer126. The first contact interconnection layer210may be formed on the interlayer insulating layer132and the buried insulating layer126. The first lower interconnection layer210may be formed to fill the groove133.

The first lower interconnection layer210may be formed of a conductive layer, for example, a metal layer. The first lower interconnection layer210may be formed of a doped polysilicon layer. InFIG. 7E, a reference numeral “134” (hereinafter, referred to as a buried insulating layer pattern) may denote a portion of the first lower interconnection layer210that is formed on the buried insulating layer126on the word line WL.

Referring toFIGS. 8A to 8E, a mask pattern212is formed on the first lower interconnection layer210. The mask pattern212may be a photoresist pattern that is formed by a photo process. For example, the mask pattern212may be formed by forming a photoresist layer (not illustrated) on the first lower interconnection layer210and exposing and developing the photoresist layer.

By using the mask pattern212as an etch mask, the first lower interconnection layer210, the interlayer insulating layer132, and substrate110may be etched to form a plurality of contact holes130H. The contact holes130H may be formed to expose one surface of the interlayer insulating layer132and/or the substrate110.

As illustrated inFIG. 8E, the contact holes130H may be spaced apart from each other in the first direction (X-axis direction) and the second direction (Y-axis direction). Also, as illustrated inFIG. 8E, the contact holes130H may be spaced apart from each other in the first direction (X-axis direction) and the second direction (Y-axis direction) while being formed between the buried insulating layer patterns134. The contact holes130H may expose the source region (not shown) of the active region116.

Referring toFIGS. 9A to 9E, the mask pattern212may be removed. Thereafter, a second lower interconnection layer may be formed on the first lower interconnection layer210to fill the contact holes130H. The second lower interconnection layer may be formed on the substrate110. After forming the second lower interconnection layer, the second lower interconnection layer may be etched back. The second lower interconnection layer may be formed of a conductive layer, for example, a metal layer. The second lower interconnection layer may be formed of a doped polysilicon layer.

InFIGS. 9A to 9E, a resultant structure of the first lower interconnection layer210and the second lower interconnection layer are collectively illustrated and collectively referred to as a lower interconnection layer “218a”. The lower interconnection layer218amay be formed on the interlayer insulating layer132and the buried insulating layer126to fill the contact holes130H.

As illustrated inFIGS. 3A, 3C, and 3E, the lower interconnection layer218amay include isolated contact filling portions214and an etch control portion216. The isolated contact filling portions214may refer to a portion of the lower interconnection layer214that fills the contact holes130H. The isolated contact filling portions214may be located on the substrate110and spaced apart and isolated from each other in the first direction and the second direction. The etch control portion216may cover the isolated contact filling portions214. The isolated contact filling portions214may refer to a portion of the lower interconnection layer218athat fills the contact holes130H.

The etch control portion216may refer to a portion of the lower interconnection layer218athat does not fill the contact holes130H. As will be described later, when forming the isolated contact filling patterns214by patterning the lower interconnection layer218a, the etch control layer216may serve to control an etch rate of the isolated contact filling patterns214such that a profile of one sidewall of an interconnection pattern to be formed is vertical in a cross-sectional view.

Subsequently, upper interconnection layers144aand146aand a capping layer148amay be formed on the lower interconnection layer218a. The upper interconnection layers144aand146amay be formed on the isolated contact filling portions214and the etch control portion216. The upper interconnection layers144aand146amay be formed of a conductive layer. The upper interconnection layers144aand146amay be formed of, for example, a tungsten layer. As illustrated in the drawings, the upper interconnection layers144aand146amay have a multilayer structure, for example, a stack structure in which a tungsten nitride layer144aand a tungsten layer146aare sequentially stacked. The capping layer148amay be formed of an insulating layer. For example, the capping layer148amay be formed of a nitride layer. InFIG. 9E, the upper interconnection layers144aand146aand the capping layer148aare not illustrated for convenience′ sake.

Referring toFIGS. 10A to 10F, the capping layer148a, the upper interconnection layers144aand146a, and the second contact interconnection layer218amay be photo-etched to form a bit line, a direct contact pattern135, and a capping pattern148on the substrate110. For example, the capping layer148a, the upper interconnection layers144aand146a, the isolated contact filling portions214, and the etch control portion216may be photo-etched to form the bit line145, the direct contact pattern135, and a capping pattern148on the substrate110.

The bit line145, the direct contact pattern135, and the capping pattern148may be formed by the following process.

For example, a mask pattern (not illustrated) including a photoresist pattern formed by a photo process may be formed on the capping layer148a. For example, the mask pattern may be formed by using a photoresist layer (not illustrated) on the capping layer148aand exposing and developing the photoresist layer. By using the mask pattern as an etch mask, the capping layer148a, the upper interconnection layers144aand146a, the isolated contact filling portions214, and the etch control portion216may be etched to form the bit line145, the direct contact pattern135, and the capping pattern148. The bit line145and the direct contact pattern135may constitute an interconnection pattern.

The bit line145may be formed by patterning the upper interconnection layers144aand146aand the lower interconnection layer218a. Thus, the bit line145may be formed of a stack of the upper interconnection patterns144aand146aand the lower interconnection pattern218, for example, a stack of a doped polysilicon layer, a tungsten nitride layer, and a tungsten layer. As illustrated inFIGS. 10E and 10F, the bit line145may be formed to be relatively narrow in the first direction and be relatively wide in the second direction. InFIG. 10E, the capping pattern148is not illustrated for convenience′ sake.

The bit line145may be included in a bit line structure140. The bit line structures140may be arranged in parallel to each other in the first direction (X-axis direction ofFIG. 5) on the interlayer insulating layer132and the direct contact pattern135. The bit line structure140may be installed to extend in the first direction. Each of the bit line structures140may include the bit line145and the capping pattern148that covers a top surface of the bit line145. The bit line145may be electrically connected to the direct contact pattern135. The capping pattern148may be formed of, for example, a silicon nitride layer. The thickness of the capping pattern148may be greater than the thickness of the bit line145.

The direct contact pattern135may be formed by etching the isolated contact filling portions214of the lower interconnection layer218a. The direct contact pattern135may be electrically connected to the source region (now shown) of the active region116. Due to the etch control portion216in the lower interconnection layer218a, a profile of one sidewall of the direct contact pattern135may be vertical in a cross-sectional view and linear in the second direction in a plan view. This has already been described with reference toFIG. 4F, and thus a description thereof will be omitted herein.

Referring toFIG. 10E, the direct contact holes130H may be formed in parallel to the bit line145in the second direction as illustrated inFIGS. 5 and 8E. As illustrated inFIG. 10F, a direct contact hole DC may be formed to incline with respect to the bit line BL. Even when the direct contact hole DC is inclined with respect to the bit line BL, a profile of one sidewall of the direct contact pattern135may have a vertical shape.

Referring toFIGS. 11A to 11D, a multilayer spacer150may be formed at both sidewalls of the bit line structure140. An insulating liner152may be formed to cover the exposed top surface and sidewalls of the bit line structure140and the exposed surface of the interlayer insulating layer132and fill a portion of the direct contact hole130H. The insulating liner152may be used as a protection layer for protecting the bit line structure140. The insulating liner152may be formed of, for example, a silicon nitride layer. The insulating liner152may be formed to have a thickness of, for example, about 30 Å to about 80 Å.

Subsequently, a first spacer154may be formed to cover the insulating liner152on both sidewalls of the bit line structure140. The first spacer154may be formed of, for example, silicon oxide (as an example of oxide), silicon germanium (SiGe) compound, or polymer. However, the material of the first spacer154is not limited thereto. The first spacer154may be formed of a material that has an etch selectivity with respect to the insulating liner152. For example, the first spacer154may be formed of an insulating material or a conductive material. The first spacer154may be formed of silicon oxide.

A second spacer156may be formed to have a desired (or alternatively, predetermined) thickness on the first spacer154. The second spacer156may be formed of a different material than the first spacer154. In an example embodiment, the second spacer156may be formed of, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. In an example embodiment, the first spacer156may be formed of silicon nitride. The second spacer156may be formed to have a thickness of about 20 Å to about 100 Å. The insulating liner152, the first spacer154, and the second spacer156may constitute the multilayer spacer150that surrounds both sidewalls of the bit line structure140.

Subsequently, an insulating layer170may be formed on the buried insulating layer126. The insulating layer170may be, for example, an oxide insulating layer. The insulating layer170may serve as a fence that surrounds both sides of a buried contact BC. Thereafter, a buried contact180may be formed at one side of the bit line structure140and at one side of the insulating layer170. The buried contact180may be formed of, for example, doped polysilicon. In some cases, the buried contact180may be formed of metal, metal silicide, metal nitride, or any combinations thereof. The buried contact180may include a buried layer (not illustrated) and a conductive layer that is formed on the buried layer. In some embodiments, the buried layer may be formed in a Ti/TiN stack structure.

When the buried contact180is formed of a metal material, a metal silicide layer (not illustrated) may be formed between the buried contact180and the active region116. For example, the metal silicide layer may be a cobalt (Co) silicide layer. However, the metal silicide layer is not limited to the cobalt silicide layer. For example, the metal silicide layer may be formed of a material selected from various types of metal silicide.

Referring toFIGS. 12A to 12D, an upper portion of the buried contact180may be removed by an etch-back process to form a groove (not illustrated). A metal layer190may be formed to fill the groove formed by the etch-back process and cover a top surface of the multilayer spacer150. The metal layer190may include a metal silicide layer (not illustrated) at a contact portion with respect to the buried contact180. For example, the metal silicide layer may be a cobalt silicide layer. However, the metal silicide layer is not limited to a cobalt silicide layer.

The metal layer190may include a buried layer (not shown), an inner metal layer (not shown), and an upper metal layer (not shown). The buried layer may cover an inner wall of the groove, the bit line structure140, and the top surface of the multilayer spacer150. The inner metal layer may fill the groove on the buried layer. The upper metal layer may cover the bit line structure140and the top surface of the multilayer spacer150on the buried layer. In some example embodiments, the buried layer may be formed in, for example, a Ti/TiN stack structure. Also, in some example embodiments, at least one of the inner metal layer and the upper metal layer may include tungsten.

Referring toFIGS. 13A to 13C, a mask pattern (not illustrated) may be formed on the metal layer190, and by using the mask pattern as an etch mask, the metal layer190and a portion of the bit line structure140thereunder may be etched to form a plurality of landing pads190athat are connected to the buried contact180.

Like the landing pad LP illustrated inFIG. 5, the mask pattern may have an island shape. Accordingly, while forming the landing pads190aby using the mask pattern as an etch mask, a landing pad groove Glp may be formed as illustrated, and the landing pads190amay be isolated from each. Also, a side surface of the bit line structure140may be exposed by the landing pad groove Glp.

As illustrated, in the process of forming the landing pad groove Glp, a right side surface of the capping pattern148may be removed, and an upper portion of the multilayer spacer150on a right sidewall of the capping pattern148may be removed. Accordingly, the landing pad190amay have a structure that covers a left portion of the capping pattern148and the multilayer spacer150on a left sidewall of the capping pattern148. Alternatively, the landing pads arranged on another line adjacent to the line I-I′ ofFIG. 5may have a structure that covers a right portion of the capping pattern148and the multilayer spacer150on a right sidewall of the capping pattern148.

Like the landing pad LP ofFIG. 5, the landing pad190amay be disposed along the second direction (Y-axis direction) in a zigzag configuration L1(seeFIG. 5) that alternately covers the multilayer spacer150on the left sidewall of the bit line structure140and the multilayer spacer150on the right sidewall of the bit line structure140, and the landing pad190may have a structure that covers the multilayer spacer150formed on the same sidewall of each bit line structure140. After the forming of the landing pads190a, the mask pattern may be removed.

After the removing of the mask pattern, a capping insulating layer (not illustrated) may be formed to fill the landing pad groove Glp and cover a top surface of the landing pad190a. The capping insulating layer may be formed of, for example, an oxide or nitride insulating material.

After forming the capping insulating layer, a plurality of capacitors (not illustrated) may be formed to be electrically connected to the landing pads190aafter passing through the capping insulating layer. The bit line145and the landing pad190amay correspond respectively to the bit line BL and the landing pad LP illustrated inFIG. 5, and the buried contact180and the direct contact135may correspond respectively to the buried contact BC and the direct contact DC illustrated inFIG. 5.

FIG. 14illustrates a system including a semiconductor device manufactured according to an example embodiment.

Referring toFIG. 14, a system1000according to the present example embodiment may include a controller1010, an input/output device1020, a memory device1030, and an interface1040. The system1000may be, for example, a mobile system or a system that transmits or receives information. In some example embodiments, the mobile system may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card.

The controller1010may control an execution program in the system1000. The controller1210may include, for example, a microprocessor, a digital signal processor, or a microcontroller. The input/output device1020may be used to input or output data of the system1000. By using the input/output device1020, the system1000may be connected to an external device, for example, a personal computer or a network to exchange data with the external device. The input/output device1020may be, for example, a keypad, a keyboard, or a display device.

The memory device1030may store codes and/or data for operation of the controller1010, or store data processed by the controller1010. The memory device1030may include a semiconductor device according to example embodiments. For example, the memory device1030may include at least one of the semiconductor devices that are manufactured by the above-described methods.

The interface1040may be a data transmission path between the system1000and other external devices. The controller1010, the input/output device1020, the memory device1030, and the interface1040may communicate with each other through a bus1050.

The system1000according to the present example embodiment may be used, for example, in mobile phones, MP3 players, navigation devices, portable multimedia players (PMPs), solid state disks (SSDs), or household appliances.

FIG. 15illustrates a memory card including a semiconductor device manufactured according to an example embodiment.

Referring toFIG. 15, a memory card1100according to the present example embodiment may include a memory device1110and a memory controller1120. The memory device1110may store data. In some example embodiments, the memory device1110may have nonvolatile characteristics that may retain stored data even when power supply thereto is interrupted. The memory device1110may include at least one of the semiconductor devices that are manufactured by the above-described methods.

The memory controller1120may read data stored in the memory device1110or may store data in the memory device1110, in response to a read/write request of a host1130. The memory controller1120may include at least one of the semiconductor devices that are manufactured by the above-described methods.