Programmable frequency divider providing a fifty-percent duty-cycle output over a range of divide factors

A divider circuit determines whether an input factor (N) is an even number or an odd number. If N is an even number then the input clock is divided by N/2 to generate an intermediate clock. The intermediate clock is further divided by two to generate a div-by-2 clock, which is provided as the output clock with fifty percent duty cycle. If N is an odd number, the input clock is divided by (N/2−0.5) in a first duration and by (N/2+0.5) in a second duration to generate the intermediate clock, which is then divided by two to generate the div-by-2 clock. A delayed clock is generated from the div-by-2 clock, wherein the delayed clock lags the div-by-2 clock by half cycle duration of the input clock. The div-by-2 clock and the delayed clock are combined to generate the output clock with fifty percent duty cycle.

PRIORITY CLAIM

The instant patent application claims priority from co-pending India provisional patent application entitled, “FRACTIONAL-N FEEDBACK DIVIDER (DIVN) AND INTEGER-N FEEDFORWARD DIVIDER (DIVO)”, Application Number: 3361/CHE/2015, Filed: 2 Jul. 2015, naming as inventors Perdoor et al, and is incorporated in its entirety herewith, to the extent not inconsistent with the content of the instant application.

BACKGROUND

Technical Field

Embodiments of the present disclosure relate generally to frequency dividers, and specifically to a programmable frequency divider providing a fifty-percent duty-cycle output over a range of divide factors.

Related Art

A frequency divider receives a periodic input signal and generates a periodic output signal with a frequency that is less than or equal to the frequency of the input signal. The ratio of the frequency of the output signal to that of the input signal is referred to as the divide factor, and is normally an integer. The divide factor may be programmable (i.e., selectable) via corresponding input(s) to the frequency divider, and a frequency divider may be designed to support a range of divide factors from a lowest limit to a highest limit.

The duty cycle of a periodic signal is generally the ratio of the active duration (e.g., duration of logic high) to the period of the periodic signal. It may be desirable that the duty cycle of the output signal of a programmable frequency divider be (a fixed) fifty-percent for all divide factors in the supported range of divide factors, irrespective of the specific frequencies of the input or output signals.

Several aspects of the present disclosure are directed to a programmable frequency divider providing a fifty-percent duty-cycle output over a range of divide factors.

DETAILED DESCRIPTION

A divider circuit provided according an aspect of the present disclosure first determines whether an input factor (N) is an even number or an odd number. If the input factor (N) is an even number then the input clock is divided by N/2 to generate an intermediate clock. The intermediate clock is further divided by a factor of 2 to generate a div-by-2 clock, which is provided as the output clock.

On the other hand if the input factor (N) is an odd number, the frequency of the input clock by (N/2−0.5) in a first duration and by (N/2+0.5) in a second duration to generate the intermediate clock. The intermediate clock is divided by a factor of 2 to generate the div-by-2 clock. A delayed clock is generated from the div-by-2 clock, wherein the delayed clock lags the div-by-2 clock by half cycle duration of the input clock. The div-by-2 clock and the delayed clock are combined to generate the output clock.

2. Example Device

FIG. 1is a block diagram of an example device in which a frequency divider implemented according to several aspects of the present disclosure can be used. Phase locked loop (PLL)100(which can be used as a frequency synthesizer) ofFIG. 1is shown containing phase frequency detector (PFD)110, charge pump120, low-pass filter (LPF)130, voltage controlled oscillator (VCO)140, frequency divider150, delta-sigma modulator (DSM)160, logic block170and integer divider180. PLL100may be implemented as an integer-only PLL or a fractional PLL (as noted below), and may be implemented in integrated circuit (IC) form. It must be understood that while implementation of frequency divider150as described below may provide several advantages in the context of a PLL, frequency divider150may also be deployed as a stand-alone unit, or in other contexts as well.

It is first noted that each of frequency divider150and integer divider180operates to divide the frequency of a corresponding input clock to generate an output clock. For the sake of clarity, the number by which frequency divider150divides its input clock (Fvco) is termed ‘divide ratio’, while the number by which integer divider180divides its input clock (also Fvco) is termed ‘divide factor’. Further, frequency divider150, being in the feedback path of PLL100, may be viewed as a ‘feedback’ divider. Integer divider180may be viewed as a ‘feedforward’ divider.

VCO140generates an output signal Fvco (VCO clock) on path145, with the frequency of Fvco being determined by the (instantaneous) magnitude of voltage received on path134.

Frequency divider150receives Fvco as an input, divides the frequency of Fvco by a divide ratio, and provides the frequency-divided signal as a feedback signal Ffb on path151.

Logic block170receives a user input (e.g., from a user or a processing block, not shown) on path171, with the user input representing the number by which Fvco is to be divided to generate Ffb. When PLL100is implemented as a fractional PLL, block170forwards the fractional portion of the user input (on path171) to DSM160on path176, and the integer portion of the number (on path171) to frequency divider150on path175. DSM160generates (in one of several known ways) a sequence of divide values corresponding to (or representing) the fractional part. DSM160forwards the numbers in the sequence successively (one number per cycle of reference frequency101, with the sequence repeating after the last number in the sequence is forwarded) to frequency divider150on path165. Frequency divider150determines the divide ratio per cycle (i.e., the divide ratio to be obtained in each cycle) of reference frequency101by adding the inputs received (on paths175and165) corresponding to the cycle. Alternatively, such addition may be performed in a separate block, not shown, which would then provide the sum to frequency divider150. Thus, when fractional division of Fvco is desired, frequency divider150successively divides Fvco by values in a sequence, such that the effective average frequency of Ffb equals the desired fraction of Fvco. When PLL100is implemented as an integer-only PLL, DSM160is not implemented, and block170forwards the integer number received on path171to frequency divider150on path175, the integer number itself representing the divide ratio. In an alternative embodiment, the input received on path171represents a desired output frequency (for Fvco), and block170computes the corresponding divide ratio based on input171.

PFD110receives as inputs, a reference frequency Fref on path101and feedback signal Ffb on path151, and operates to generate error signals UP and DOWN on respective paths112U and112D. The ON (active) durations of error signals UP and DOWN are proportional to the amount of phase by which Fref leads or lags Ffb respectively. Reference frequency Fref may be generated by an oscillator (not shown) contained within PLL100, or provided external to PLL100.

Charge pump120converts the UP and DOWN outputs of PFD110to charge (provided on path123). Path123may be single-ended or differential, depending on whether charge pump120is designed to provide a single-ended or differential output. While signals UP and DOWN have been noted as being applied to charge pump120, signals derived from UP and /DOWN (e.g., logical inverse of the signals) may instead be applied to charge pump120depending on the specific design of charge pump120. LPF130is a low-pass filter and rejects frequency variations at node123above a certain cut-off limit. LPF130converts the low-pass-filtered charge to a voltage134. VCO140generates Fvco with a frequency that is dependent on the magnitude of voltage.

Integer divider180receives a divide factor (also referred to as ‘input factor (N)’ herein, which is an integer) on path182(which may, for example, be provided by a user or a processing block, not shown) and Fvco on path145as inputs, and generates a final output clock181(Final-out) whose frequency equals the frequency of Fvco divided by the divide factor. Integer divider180may be designed to support a range of divide factors. It may desirable that integer divider180provide Final-out with a duty cycle of 50%, irrespective of the divide factor. Several aspects of the present disclosure are directed to such an integer divider, as described in detail below. However, the building blocks used to implement integer divider180are first described next.

FIG. 2Ais a block diagram of a frequency-dividing unit that is used in building an integer divider (e.g.,180) according to aspects of the present disclosure. Two or more of such units as unit200ofFIG. 2Amay be cascaded (connected in series) to obtain an integer divider which supports a desired range of divide factors. In the embodiment ofFIG. 2A, frequency-dividing unit200is a divider which can divide an input signal by 2 or 3, as controlled by corresponding signals, described below. Only a brief description of unit200(with reference also to the timing diagram ofFIG. 2B) is provided herein, as the design of such unit is well-known in the relevant arts. For more details of unit200, the reader is referred to the MIT OPEN COURSEWARE lecture notes identified as “6.976 High Speed Communication Circuits and Systems, Lecture 14, High Speed Frequency Dividers” By Michael Perrott, Massachusetts Institute of Technology.

Frequency-dividing unit200is shown containing AND gates210,220,240and270, latches230,250,280and290, and inverters260and295. Frequency-dividing unit200receives an input signal Clk-in (201), and generates an output signal Clk-out (299) whose frequency is either half, or one-third of the frequency of Clk-in. Other signals shown inFIG. 2Aand/orFIG. 2Binclude nc (235) and Mod-in (209), Mod-out (211), n12(234), div3b (267), n22(289) and clkob (291). Nc is a control signal (binary signal) provided as input to frequency-dividing unit200, and which determines if frequency-dividing unit200is to be allowed to divide by 3 at all (or divide by 2 only). Mod-in is a mode control signal received from another unit (not shown), and determines when (i.e., at what time instant) frequency-dividing unit200is to divide by 3. Mod-out (211) is a mode control signal generated by frequency-dividing unit200, and may be connected as an input to a previous stage (not shown). The other signals noted above are signals internal to frequency-dividing unit200.

As may be observed fromFIG. 2B, in the interval t21to t23, frequency-dividing unit200operates as a divide-by-2 unit, while in the interval t23to t25frequency-dividing unit200operates as a divide-by-3 unit. In interval t22-t23, signals nc and Mod-in are high, and cause frequency-dividing unit200to divide by 3 in the interval between t23and t25. Mod-in transitions to logic low at t23, and thereafter, nc transitions to logic low at t24and remains at logic low. In response, frequency-dividing unit200operates as a divide-by-2 unit from t25. By appropriate control of nc and Mod-in, frequency-dividing unit200can be made to operate as a divide-by-2 or divide-by-3 unit.

By connecting multiple ones of units such as a frequency-dividing unit200in series (i.e., in a cascade), corresponding ranges of divide factors between an input signal and an output signal are achieved. As an example, a cascade of three units such as frequency-dividing unit200forming a frequency divider300is shown inFIG. 3A, and the timing diagram of3B shows the corresponding waveforms when a divide factor of 15 is desired.

InFIG. 3A, three units, each identical to frequency-dividing unit200, are used in a cascade. Clk-0(309) is the input signal, and is provided as input to the first unit200-1. Unit200-1receives as input a mode control signal308(Mod-1) from the next (higher) stage (or unit)200-2, and a control signal307(Nc-0). Depending on the value of Nc-0, unit200-1performs only divide-by-2 division or divide-by-3 once in a divide cycle (explained below) and divide-by-2 the rest of the divide cycle. Unit200-1provides a divided clock Clk-1(312) and a mode control signal311(Mod-0) as outputs.

Unit200-2receives Clk-1(312) as an input clock. Unit200-2receives as input a mode control signal318(Mod-2) from the next (higher) stage200-3, and a control signal317(Nc-1). Depending on the value of Nc-1, unit200-1performs only divide-by-2 division or divide-by-3 once in a divide cycle and divide-by-2 the rest of the divide cycle. Unit200-2provides a divided clock Clk-2(322) and mode control signal308(Mod-1) as outputs.

Unit200-3receives Clk-2(322) as an input clock. Unit200-3, being the ‘highest’ unit, the mode control signal328(Mod-3) provided as input to unit200-3is tied to logic high. Unit200-3receives a control signal327(Nc-2). Depending on the value of Nc-2, unit200-3performs only divide-by-2 division or divide-by-3 once in a divide cycle and divide-by-2 the rest of the divide cycle. Unit200-3provides a divided clock Clk-3(332) and mode control signal318(Mod-2) as outputs. Control signals Nc-0, Nc-1and Nc-2, each of which is a binary signal, may be received from a unit external to divider300(and based on user inputs, for example), and their values determine the specific divide factor to be used by divider300. Input terminals307,317and327together represent the “divide input” of divider300. Unit200-1is the ‘lowest’ (first) unit, while200-3is the ‘highest’ unit.

Referring toFIG. 3B, a ‘divide cycle’ refers to the duration of one cycle of the clock output of the highest operative unit (the term highest operative unit is clarified in sections below). Thus, in the example ofFIGS. 3A and 3B, a divide cycle is the duration t31to t34, also equal to one period of Clk-3(332). In the example ofFIG. 3A, it is assumed that each of Nc-0, Nc-1and Nc-2is set to logic high (one). Therefore, each of stages/units200-1,200-2and200-3divides-by-3 once in a divide cycle. Clk-1(312) divides-by-3 in interval t31-t32, Clk-2(322) divides-by-3 in interval t31-t33, and Clk-3always divides by 3. The values for the waveforms shown inFIG. 3Brepeat after t34. Clk-3(332) has a frequency that is 1/15 of that of Clk-1. The general expression that specifies the divide factors that can be obtained by divider300is: [23+(Nc-2) 22+(Nc-1) 21+(Nc-0) 20]. By appropriate selection of Nc-2, Nc-1and Nc-0, a divide factor in the range 8 to 15 (both inclusive) can be obtained. In general, with a cascade of ‘k’ units/stages, a range of [2k, 2k+1−1] can be obtained.

Thus, for example with eight cascaded stages (and assuming all eight stages are operated), a divide range of [256, 511] can be obtained, and such a cascade is illustrated inFIG. 4. InFIG. 4are shown buffer410, and divide-by-⅔ units420through490(each identical to frequency-dividing unit200ofFIG. 2) contained in integer divider180, in an embodiment of the present disclosure.

Buffer410receives Fvco (145inFIG. 1) which represents the input signal whose frequency is to be divided by a desired divide factor. Buffer410provides additional drive to Fvco, and generates a corresponding differential signal CK0n/CK0p (across terminals412and413), and which has the same frequency as Fvco. Each of units420-490receives a corresponding clock signal, control signal (nc) and a mode control signal as inputs, and generates a divided clock signal and a mode control signal. The corresponding connections are shown inFIG. 4, and are briefly summarized below.

Unit420receives Ck0n (412) and Ck0p (413) as an input clock. Unit420receives as input a mode control signal432(MD1) from the next higher stage unit430, and a control signal421(Nc0). Depending on the value of Nc0, unit420performs only divide-by-2 division or divide-by-3 once in a divide cycle and divide-by-2 the rest of the divide cycle. Unit420provides a divided clock CK1(423) and mode control signal422(MD0) as outputs. The rest of the units operate similarly, with signals434(CK2),445(CK3),456(CK4),467(CK5),478(CK6),489(CK7) and499(CK8) being the respective clock output signals of units430,440,450,460,470,480and490, and which are provided as inputs to the corresponding next higher unit. Units430-490receive respective control signals431(Nc1),441(Nc2),451(Nc3),461(Nc4),471(Nc5),481(Nc6) and491(Nc7). Units430-490receive respective mode control signals443(Md2),454(MD3)465(MD4),476(MD5),487(MD6),498(MD7) and497(MD8). Input terminals421,431,441,451,461,471,481and491together represent the “divide input” of integer divider180. Control signals Nc0through Nc7, each of which is a binary signal, is generated by logic unit850ofFIG. 8C. Logic unit850receives input factor N on path182, determines whether N is even or odd, and generates signals Nc0through Nc7with corresponding binary values (representing a corresponding derived divide factor) based on whether the N is odd or even (further described below). Logic unit850may be designed in a known way.

InFIG. 4, MD8(497) is shown tied to logic high (Vdd/power supply). This implies that all the divide units420-490are operational (i.e., powered-ON and used in operation of integer divider180), with420being the first unit and490being the highest unit. Since eight units are used, the possible divide range is [256, 511]. If divide factors less than 256 are also desired (in addition to the range [256, 511], one or more of the higher units need to be switched off (or not used even if powered-ON), and the resulting highest (rightmost in the cascade of units) mode control signal should be tied to logic high. To illustrate, assuming only the first seven units420-480are operated, with unit490switched off (or not used), then MD7(498) needs to be tied to logic high. With such an arrangement a divide range of [128, 255] is obtained.

Similarly, with only the first six units (420through470) operational (480and490being switched off or not used), then MD6(487) is tied to logic high. With such an arrangement a divide range of [64, 127] is obtained. Similarly, with only the first five units (420through460) operational (470,480and490being switched off or not used), MD5(476) is tied to logic high. With such an arrangement a divide range of [32, 63] is obtained. In the example ofFIG. 4and the corresponding timing diagram ofFIG. 5(described below), it is assumed that integer divider180is designed to support (only) a range of [32, 511], 32 being the lowest divide factor (lowest limit) and511being the highest divide factor (highest limit) that frequency divider is designed to provide. It may be noted that by extending the same logic as above, even lower values of divide factors may be obtained. However, it is assumed herein that integer divider180is designed to only provide the range [32, 511], and various portions of integer divider180may be fixed by design to support only that range.

FIG. 5is a timing diagram illustrating waveforms at various nodes of integer divider180implemented as shown inFIG. 4, for some arbitrary large value of divide factor. CK8(499) has the desired frequency Fvco/divide factor (although not shown clearly inFIG. 5). Each of the mode control signals MD0-MD7also has a frequency that equals (Fvco/divide factor). However, the duty cycle of none of CK8and MD0-MD7is guaranteed to equal to 50%. As noted above, it may be desirable to provide the final output clock181of PLL100with a duty-cycle of fifty-percent. For example, the circuit/component receiving Final-out (181) may be designed such that it can operate correctly only if Final-out has a fifty-percent duty cycle. A fifty-percent duty cycle for Final-out (181) may also be required by standards to which PLL100may be required to comply with.

According to an aspect of the present disclosure, rather than using the divide factor directly (i.e., rather than dividing Fvco directly by the divide factor), a pair of ‘derived’ divide factors are used to successively (and repeatedly) divide the frequency of Fvco. The values of the pair depend on whether the divide factor (182) is odd or even. The resulting MD0is then further processed to generate Final-out181with a duty cycle equal to 50% irrespective of the value of the divide factor. The description is continued next with an illustration of the manner in which such 50% duty cycle for Final-out is achieved.

FIG. 6is a flow chart illustrating the manner in which the frequency of an input clock is divided to obtain an output clock with a fifty-percent duty cycle irrespective of the divide factor, in an embodiment of the present disclosure. The flowchart is described with respect toFIG. 1, in particular, integer divider180, merely for illustration. However, many of the features can be implemented in other environments also without departing from the scope and spirit of several aspects of the present disclosure, as will be apparent to one skilled in the relevant arts by reading the disclosure provided herein.

In step610, integer divider180receives an input factor (N) by which input clock (Fvco) is to be divided. The input factor is an integer. In the embodiment ofFIG. 1, the input factor (N) is received on path182. Control then passes to step620.

In step620, integer divider180determines if N is an even integer or odd integer. If N is an even integer, control passes to step630. If N is an odd integer, control passes to step650.

In step630, integer divider180divides the frequency of the input clock by N/2 in each of a first duration and a second duration to generate an intermediate clock. The second duration starts immediately after the end of the first duration. The first duration and the second duration repeat, with integer divider180continuously repeating the division by N/2 in each of the corresponding first and second durations. Thus, the two ‘derived’ divide factors are each N/2. The division results in the generation of an intermediate clock. Control then passes to step640.

In step640, integer divider180divides the frequency of the intermediate clock by a factor of two to generate final-out (181), which may be viewed as the output clock of PLL100. Control then passes to step699, in which the flowchart ends.

In step650, integer divider180divides the frequency of the input clock by (N/2−(0.5)) in a first duration, and by (N/2+(0.5)) in a second duration. The second duration starts immediately after the end of the first duration. The first duration and the second durations repeat, with integer divider180continuously repeating the division by (N/2−(0.5)) and (N/2+(0.5)) in the respective first and second durations. Thus, the two ‘derived’ divide factors are (N/2−(0.5)) and (N/2+(0.5)). The division results in the generation of an intermediate clock. Although integer divider180is noted above as dividing first by (N/2−(0.5)) and then by (N/2+(0.5)), the sequence can also be flipped. i.e., integer divider180can divide by (N/2−(0.5)) in the first duration, and then by (N/2+(0.5)) in the second duration. Control then passes to step660.

In step660, integer divider180divides the frequency of the intermediate clock by a factor of two to generate a divided-by-two (div-by-2) clock. Control then passes to step670.

In step670, integer divider180delays the div-by-2 clock (of step660) by a duration equal to a half-cycle of the input clock (Fvco) to generate a delayed clock. Control then passes to step680.

In step680, integer divider180combines the div-by-2 clock and the delayed clock to generate the output clock, i.e., Final-out (181). Control then passes to step699, in which the flowchart ends. While described in terms of a series of successive steps, when implemented in hardware form, one or more of the steps may execute concurrently.

The operations of the flowchart as described above enable integer divider180to generate Final-out (181) with a duty-cycle of fifty-percent for all values of N within the range of divide factors supported by the design of integer divider180, and are illustrated further with examples below.

It is noted first that while any of CK8and MD0-MD7can be used (by processing suitably in a manner similar to that described below with respect to MD0), using MD0to generate Final-out181is the best choice when noise in Final-out181is of concern. This is because CK8and MD0-MD7are generated from FVCO using more logic operations compared to MD0. Generally, noise in a signal is more if more logic operations have to be performed to obtain the signal. Also, MD0can to be re-synchronized with Fvco145before further processing to generate Final-out (181) with fifty-percent duty cycle.

It is also noted that inFIG. 7AandFIG. 7B(as well asFIG. 5), the edges of MD0(422) are shown as coinciding with falling edges of Fvco. However, depending on the specific hardware implementation of integer divider180, edges of MD0(422) may instead coincide with rising edges of Fvco. When edges of MD0(422) coincide with falling edge of Fvco, then FF820ofFIG. 8B(described below) is implemented as a rising-edge triggered flip flop. However, when the implementation is such that edges of MD0(422) coincide with falling edge of Fvco, FF820ofFIG. 8Bis implemented instead as a falling-edge triggered flip-flop. Further, it is noted here that while Fvco is indicated in the Figures as being single-ended, Fvco may also be implemented as a differential signal. When Fvco is implemented as a differential signal, then Fvco-p and Fvco-n represent the positive and negative nodes of Fvco. The waveform at Fvco-n is the same as that of Fvco shown in the Figures, and the waveform at Fvco-p is the inverse of that at Fvco-n.

FIG. 7Ais a timing diagram illustrating corresponding waveforms when the divide factor N (received on path182) is an even integer. As an example, assuming N equals 100, then a logic unit850in integer divider180programs Nc0through Nc4(ofFIG. 4) with corresponding binary values to cause integer divider180to divide by 50 (i.e., N/2) for 50 cycles of Fvco. Units470,480and490ofFIG. 4are non-operative or unused for a divide by 50. InFIG. 7A, the duration from t71to t72represents 50 cycles of Fvco. Since integer divider180divides by 50 in interval t71-t72(one ‘first duration’), one cycle of MD0is obtained in interval t71-t72, as may be observed fromFIG. 7A.

Since N is even, integer divider180does not change the settings of Nc0through Nc4for a ‘second duration’ t72-t23. It may be observed fromFIG. 7Athat the second duration t72-t73immediately follows the first duration (t71-t72). Integer divider180divides Fvco again by 50 (i.e., N/2) for the next 50 cycles of Fvco, and another cycle of MD0is obtained in the second interval. Thus, the two derived divide factors when N is even are the same (50 in the example). The first duration and second duration are repeated, with integer divider180set to divide by 50 in each of the durations. MD0, thus generated, may be viewed as an ‘intermediate clock’, and is provided to a divide-by-2 circuit.FIG. 8Ashows one well-known implementation of a divide-by-2 circuit. Flip-flop (FF)810has its data (D) input connected to Qbar (logical complement of output Q of FF810). The clock input of FF810is connected to MD0. The output (Q) of FF810provides a ‘divided-by-2’ (div-by-2) clock MD0/2 (710). Therefore, MD0/2 (710) has a frequency that is 1/100 that of Fvco. When N is even, MD0/2 is provided as the output clock (i.e., Final-out (181)) of integer divider180.

FIG. 7Bis a timing diagram illustrating corresponding waveforms when the divide factor (N) (received on path182) is an odd integer. As an example, assuming N equals 101, then logic unit850in integer divider180programs Nc0through Nc4(FIG. 4) with corresponding binary values to cause integer divider180to divide by 50 (i.e., N/2−(0.5)) for one divide cycle. InFIG. 7B, the duration from t75to t76represents 50 cycles of Fvco. Since integer divider180divides by 50 in interval t75-t76(one ‘first duration’), one cycle of MD0(422) is obtained in interval t75-t76.

Logic unit850in integer divider180then programs Nc0through Nc4(FIG. 4) with corresponding binary values to cause integer divider180, starting at t76, to divide by 51 (i.e., N/2+(0.5)) for one divide cycle. Thus, integer divider180divides Fvco by 51 for the next 51 cycles of Fvco, and another cycle of MD0(422) is obtained in interval t76-t78second interval. Interval t76-t77represents 50 cycles of Fvco, and interval t77-t78represents once cycle of Fvco. Thus, the two derived divide factors when N is odd are unequal (50 and 51 in the example). The first duration and second duration are repeated, with integer divider180set to divide by 50 in each of the first durations and by 51 in each of the second durations. MD0is provided to a divide-by-2 circuit (such as ofFIG. 8A, for example) to obtain MD0/2 (710).

It may be observed that the duty cycle of MD0/2 (as inFIG. 7B) when N is odd does not equal 50%. Therefore, a ‘delayed’ clock (720) derived from MD0/2 (710), and delayed by half-clock cycle duration of Fvco with respect to MD0/2 (710), is generated. The delayed clock (720) and the intermediate clock (MD0/2) (710) are combined (representing a logical OR function) to generate clock730having 50% duty-cycle, which is then provided as output clock (Final-out181) of integer divider180.

FIG. 8Bis a block diagram of a circuit implemented within integer divider180to generate Final-out (181) from MD0/2 (710), in an embodiment of the present disclosure. The diagram is shown containing flip-flop (FF)820, OR gate830and multiplexer (MUX)840. MD0/2 (710) is provided to the input (D) of FF820. Fvco is provided to the clock input of FF820. FF820is a negative edge-triggered flip-flop. Delayed clock720is generated at the output (Q) of FF820.

OR gate830receives MD0/2 and delayed clock720as inputs, and provides, on path730, the result of a logical OR operation on the two inputs. It should be appreciated that the logical OR operation represents an example approach to combining MD0/2 and delayed clock720, and various other alternative approaches will be apparent to one skilled in the relevant arts by reading the disclosure provided herein. It may be further appreciated that OR gate830represents a combining circuit realized in the form of a logic gate.

MUX840receives the signal on path730and MD0/2 (710) as inputs, and forwards the corresponding one of the two inputs as Final-out (181) based on the binary value of a control input received on path841. Control signal841is generated by logic unit850, based on whether the input factor (N) (received on path182) is even or odd. It is noted that when integer divider180divides Fvco by (N/2+(0.5)) in the first duration, and then by (N/2−(0.5)) in the second duration, OR gate830is replaced by a NAND gate (which is another example of a combining circuit), with all other components and connections ofFIG. 8Bremaining the same.

Thus, the output clock181(Final-out) of integer divider180is generated to always have a duty-cycle of 50%. It is noted here that, although integer divider180is described in the context of a PLL, integer divider180may also be deployed as a stand-alone unit (for example, as an integrated circuit), or in combination with other types of devices.

FIG. 9is a diagram of a circuit implemented within integer divider180to generate Final-out (181) from MD0/2 (710), in another embodiment of the present disclosure.FIG. 9is shown containing flip-flops910and920, NOR gates930and940, and P-type MOS (PMOS transistor210) transistors960and970, and N-type MOS (NMOS) transistors981,982,983,984,991,992,993and994. It is assumed in the description below that Fvco is implemented as a differential signal, with Fvco-n (911) and Fvco-p (921) representing the negative and positive components of Fvco. As noted above, the waveform at Fvco-n (911) is the same as that of Fvco shown in the figures, and the waveform at Fvco-p921is the inverse of that at Fvco-n911. The gate of NMOS981is tied to ground, and hence NMOS981is always OFF. Flip-flop910is clocked by Fvco-n (911), while flip-flop920is clocked by Fvco-p (921). Hence the signal on node922is delayed with respect to the signal on node913by a duration equal to a half-cycle of MD0/2 (710).

When the divide factor N is even, signal841is at logic low (logic zero). As a result, node953is at logic high (logic one), node931is at logic low, and NMOS992is OFF. NOR gate940operates as an inverter. The gate terminal of NMOS982receives MD0/2, while the gate terminal of NMOS991receives the logical inverse of MD0/2. Therefore, node181(Final-out) is logically equivalent to MD0/2, as is required when divide factor N is even.

When the divide factor N is odd, signal841is at logic high. As a result, node941is at logic low, and NMOS991is OFF. NOR gate930operates as an inverter. The gate terminal of NMOS982receives MD0/2, while the gate terminal of NMOS992receives a delayed MD0/2 (MD0/2 delayed by half a cycle of Fvco). Final out (181) is provided as the logical OR result of the signals on nodes912and931.

Since Fvco-p is applied to the gate terminals of NMOS984and NMOS994, output Final-out181is generated at the active edge (rising edge here) of Fvco-p, and is therefore resynchronized with respect to Fvco. Further, such re-synchronization with respect to Fvco is provided at the final stage of generation of Final-out (181), rather than prior to OR gate830and MUX840, as in the implementation ofFIG. 8B. Therefore, the circuit ofFIG. 9provides final-out (181) with less jitter/noise than the implementation ofFIG. 8B. Flip-flop910is provided to prevent race-around conditions (since Fvco-p is applied for final re-synchronization).

It is to be understood that the specific components and interconnections shown inFIG. 9are provided merely by way of example, and modifications to the circuit ofFIG. 9would be apparent to one skilled in the relevant arts upon reading the disclosure herein. For example, each of PMOS960and970can be replaced with resistors, while also removing the cross-coupling connections961and971. Thus, PMOS960and970may instead be simply viewed as pull-up components that serve to connect each of nodes968and979to Vdd. As another example, logic gates940,950and930can be replaced by other types of logic gates, while also making suitable changes to connections to/from the inputs/outputs of those gates. Similarly, flip-flops910and920can be replaced by other types of memory elements.

PLL100incorporating frequency divider180implemented as described above can be used as part of a system as described next.

FIG. 10is a block diagram of a system in which a PLL with an integer divider (such as180) implemented according to aspects of the present disclosure can be used. System1000is shown containing signal processing block1080, crystal oscillator1050and PLL100. Signal processing block1080is in turn shown containing filter1010, analog to digital converter (ADC)1020and processing block1030.

Filter1010, which may be an anti-aliasing filter of system100, receives an analog signal on path1001, and provides a filtered signal (low-pass or band-pass filtered) to ADC1020. ADC1020receives a sampling clock on path181(Final-out) from PLL100, and generates digital codes representing the magnitude of the received filter signal at time instances (e.g., rising edges) specified by sampling clock181. Processing block1030receives the digital codes, and processes the digital codes in a desired manner (for example for signal processing applications).

Crystal oscillator1050generates reference frequency101at a fixed (desired) frequency. PLL100receives a divide ratio (integer or fractional) on path171, and a divide factor on path182. PLL100generates sampling clock181at a frequency determined by the divide ratio171and reference frequency101, as well as divide factor182.

While in the illustrations ofFIGS. 1 through 10, although various pairs of terminals/nodes are shown with direct connections, it should be appreciated that additional components (as suited for the specific environment) may also be present in the path between each pair of terminals/nodes. When there is a current path (with or without additional components) between any pair of terminals/nodes, the pair is said to be “electrically coupled”. On the other hand, when a node is “connected to” or “directly connected to” another node (of a pair), it means that there are no intervening components between the pair of nodes, and the two nodes are effectively a single node or the connection between them is an electrical short (zero or very low resistance).

Further, it should be appreciated that the specific type of transistors (such as NMOS, PMOS, etc.) noted above are merely by way of illustration. However, alternative embodiments using different configurations and transistors will be apparent to one skilled in the relevant arts by reading the disclosure provided herein. For example, NMOS transistors and PMOS transistors may be swapped, while also interchanging the connections to power and ground terminals. Accordingly, in the instant application, the power and ground terminals are referred to as constant reference potentials, the source (emitter) and drain (collector) terminals (through which a current path is provided when turned ON and an open path is provided when turned OFF) of transistors are termed as current terminals, and the gate (base) terminal is termed as a control terminal.