Tuning programmable logic devices for low-power design implementation

A method of operating a programmable logic device includes the steps of using a full VDD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full VDD supply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced VDD supply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.

FIELD OF THE INVENTION

The present invention relates to the regulation of the supply voltage provided to unused and/or inactive blocks in a programmable logic device to achieve lower power consumption. More specifically, the present invention relates to selectively reducing the operating voltage of various sections of an integrated circuit device in order to reduce the leakage current and/or increase the performance of the device.

RELATED ART

Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), have a significantly higher static power consumption than dedicated logic devices, such as standard-cell application specific integrated circuits (ASICs). A reason for this high static power consumption is that for any given design, a PLD only uses a subset of the available resources. The unused resources are necessary for providing greater mapping flexibility to the PLD. However, these unused resources still consume static power in the form of leakage current. Consequently, PLDs are generally less likely to be used in applications where low static power is required.

It would therefore be desirable to have a PLD having a reduced static power consumption.

Programmable logic devices (PLDs) also have a significantly higher dynamic power consumption than dedicated logic devices because the PLD resources (logic and routing) are designed with a fixed level of performance, regardless of the requirements of the specific application being implemented by the PLD. Most PLD applications do not require the maximum hardware speed for some (or even all) parts of the PLD. As a result, “timing slack” exists in different parts of the PLD. In fact, the timing critical part of a PLD design typically represents a very small portion of the whole design. In circuit design, higher speed circuits generally consume more power, both dynamic and static. Consequently, the parts of the PLD that are not operated at the maximum hardware speed represent an inefficient use of power.

It would therefore be desirable to improve the power efficiency of a programmable logic device by taking advantage of the timing slack present in different parts of a PLD design.

SUMMARY

In accordance with one embodiment of the present invention, unused and/or inactive resources in a PLD are disabled to achieve lower power consumption.

One embodiment of the present invention provides a method of operating a PLD, which includes the steps of enabling the resources of the PLD that are used in a particular circuit design, and disabling the resources of the PLD that are unused or inactive. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternately, the step of disabling can include regulating (e.g., reducing) a supply voltage applied to the unused or inactive resources.

In accordance with one embodiment, the step of disabling can be performed in response to configuration data bits stored by the PLD. These configuration data bits can be determined during the design of the circuit to be implemented by the PLD. That is, during the design, the design software is able to identify unused resources of the PLD, and select the configuration data bits to disable these unused resources.

The step of disabling can also be performed in response to user-controlled signals. These user-controlled signals can be generated in response to observable operating conditions of the PLD. For example, if certain resources of the operating PLD are inactive for a predetermined time period, then the user-controlled signals may be activated, thereby causing the inactive resources to be disabled.

In accordance with another embodiment, a PLD includes a first voltage supply terminal that receives a first supply voltage, a plurality of programmable logic blocks, and a plurality of switch elements, wherein each switch element is coupled between one of the programmable logic blocks and the first voltage supply terminal. A control circuit coupled to the switch elements provides a plurality of control signals that selectively enable or disable the switch elements. The control circuit can be controlled by a plurality of configuration data values stored by the PLD and/or a plurality of user-controlled signals.

In an alternate embodiment, each of the switch elements can be replaced by a switching regulator. In this embodiment, the operating voltage applied to different blocks of the PLD may be adjusted in view of the timing slack available in these blocks. That is, a block with a large amount of timing slack can be operated at a lower voltage, thereby causing the block to operate at a slower speed, which is acceptable within the parameters of the PLD design. The lower operating voltage advantageously reduces the leakage current in the block. Blocks with a small amount of timing slack are operated at a higher voltage, thereby enabling these blocks to operate at the required high speed.

In accordance with one embodiment, the switching regulator can be a high-voltage n-channel transistor having a drain coupled to the VDDvoltage supply and a source coupled to the programmable logic block. The gate of the high voltage transistor is coupled to receive a control voltage from a corresponding control circuit. The control circuit determines whether the corresponding programmable logic block is in an active or inactive state in response to user controlled signals and/or configuration data bits. When the programmable logic block is active, the control circuit applies a high control voltage VBOOST, which is greater than the VDDsupply voltage, to the gate of the high voltage transistor, such that the full VDDsupply voltage is applied to the programmable logic block. When the programmable logic block is inactive, the control circuit applies a low control voltage VSTANDBY, which is less than the VDDsupply voltage, to the gate of the high voltage transistor, such that a voltage of about one half the VDDsupply voltage is applied to the programmable logic block. A feedback mechanism can be employed to ensure that the voltage applied to the programmable logic block is precisely equal to one half the VDDsupply voltage.

In accordance with another embodiment, a method of operating a programmable logic device includes the steps of using a full VDDsupply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed during design time and/or run time, in order to determine the maximum available timing slack in each active block. Active blocks having a relatively small timing slack are grouped in the first set, and are coupled to receive the full VDDsupply voltage. As a result, the active blocks in the first set receive a voltage high enough to enable these blocks to meet the timing requirements of the PLD design.

Active blocks having a relatively large timing slack are grouped in the second set, and are coupled to receive the reduced VDDsupply voltage. As a result, the active blocks in the second set exhibit reduced power consumption (as a result of operating in response to the reduced VDDsupply voltage). In addition, the active blocks in the second set meet the timing requirements of the PLD design, in spite of operating in response to the reduced VDDsupply voltage, because of the large timing slack initially present in these blocks. As a result, operating the active blocks in the second set at the reduced VDDsupply voltage does not adversely affect the overall speed of the programmable logic device.

The reduced VDDsupply voltage can be supplied in various manners, including, but not limited to, variable voltage switching regulators, or a separate voltage supply. The application of the full VDDvoltage supply or the reduced VDDvoltage supply can be controlled by configuration data bits and/or user control signals.

DETAILED DESCRIPTION

In accordance with one embodiment of the present invention, unused and inactive resources in a programmable logic device (PLD), such as a field programmable gate array (FPGA), are disabled to achieve lower static power consumption. The present invention includes both an enabling software flow and an enabling hardware architecture, which are described in more detail below. Unused resources of the PLD can be disabled when designing a particular circuit to be implemented by the PLD (hereinafter referred to as “design time”). In addition, resources of the PLD that are temporarily inactive can be disabled during operation of the PLD (hereinafter referred to as “run time”).

FIG. 1is a flow diagram100illustrating a conventional design flow used for PLDs. Initially, a user designs a circuit to be implemented by the PLD (Step101). This user design is described in a high-level specification, such as Verilog or VHDL. The high-level specification is first synthesized to basic logic cells available on the PLD (Step102). A place and route process then assigns every logic cell and wire in the design to some physical resource in the PLD (Step103). The design is then converted into a configuration bit stream, in a manner known to those of ordinary skill in the art (Step104). The configuration bit stream is then used to configure the device by setting various on-chip configuration memory cells (Step105). While modern design flows may be much more complex, they all involve the basic steps defined by flow diagram100.

In accordance with the present invention, unused resources of the PLD are identified during the design time, following the place and route process (Step103). These unused resources are then selectively disabled during the design time. As described below, there are several ways to disable the unused resources. By selectively disabling the unused resources at design time, significant static power reduction may be achieved with no performance penalty.

FIG. 2is a flow diagram200illustrating a design flow in accordance with one embodiment of the present invention. Similar steps in flow diagrams100and200are labeled with similar reference numbers. Thus, flow diagram200includes Steps101–105of flow diagram100, which are described above. In addition, flow diagram200includes the step of disabling unused resources in the PLD (Step201). This step of disabling unused resources is performed after the place and route process has been completed in Step103, and before the configuration bit stream is generated in Step104. As described in more detail below, the unused resources are disabled by disabling predetermined programmable logic blocks of the PLD.

In another embodiment, further power savings are obtained by disabling temporarily inactive resources of the configured PLD during run time. Often, the entire design or parts of the design are temporarily inactive for some period of time. If the inactive period is sufficiently long, it is worthwhile to disable the inactive resources to reduce static power consumption. In a preferred embodiment, the decision of when to disable a temporarily inactive resource is made by the designer. In this embodiment, the user logic is provided access to a disabling mechanism, which enables the inactive resources to be disabled dynamically.

There are a number of techniques to disable resources in a PLD. In accordance with one embodiment, the PLD is logically subdivided into a plurality of separate programmable logic blocks. As described below, each programmable logic block may comprise one or more of the resources available on the programmable logic device. Switch elements are used to couple each of the programmable logic blocks to one or more associated voltage supply terminals (e.g., VDDor ground). The switch elements are controlled to perform a power-gating function, wherein unused and/or inactive programmable logic blocks are disabled (e.g., prevented from receiving power or receiving a reduced power). Preferably, only one of the voltage supply terminals (VDDor ground) is power-gated, thereby reducing the speed and area penalties associated with the switch elements. When the switch elements are controlled to de-couple the associated programmable logic blocks from the associated supply voltage, these programmable logic blocks are effectively disabled, thereby dramatically reducing the static power consumption of these blocks.

FIG. 3is a block diagram of a conventional PLD300having four programmable logic blocks301–304, which are all powered by the same off-chip VDDvoltage supply305. Note that all four programmable logic blocks301–304are coupled to receive the VDDsupply voltage during normal operating conditions, even if some of these blocks are not used in the circuit design.

FIG. 4is a block diagram of a PLD400in accordance with one embodiment of the present invention. Similar elements inFIGS. 3 and 4are labeled with similar reference numbers. Thus, PLD400includes programmable logic blocks301–304and VDDvoltage supply305. In addition, PLD400includes switch elements401–408, and control circuit409. In the described embodiment, switch elements401–404are implemented by PMOS power-gating transistors451–454, respectively, and switch elements405–408are implemented by NMOS power-gating transistors455–458, respectively. In other embodiments, switch elements401–408may be any switch known to those ordinarily skilled in the art. Control circuit409is implemented by inverters411–414, NOR gates421–424, configuration memory cells431–434, and user logic input terminals441–444.

NOR gates421–424and inverters411–414are configured to generate power-gating control signals SLEEP1–SLEEP4and SLEEP#1–SLEEP#4in response to the configuration data values CD1–CD4stored in configuration memory cells431–434, respectively, and the user control signals UC1–UC4provided on user logic input terminals441–444, respectively.

For example, NOR gate421is coupled to receive configuration data value CD1from configuration memory cell431and user control signal UC1from user logic input terminal441. If either the configuration data value CD1or the user control signal UC1is activated to a logic high state, then NOR gate421provides an output signal (SLEEP#1) having a logic “0” state. In response, inverter411, which is coupled to the output terminal of NOR gate421, provides an output signal (SLEEP1) having a logic “1” state.

The SLEEP1signal is applied to the gate of PMOS power-gating transistor451, which is coupled between block301and the VDDvoltage supply terminal. The SLEEP#1signal is applied to the gate of NMOS power-gating transistor455, which is coupled between block301and the ground voltage supply terminal. The logic “0” state of the SLEEP#1signal causes NMOS power-gating transistor455to turn off, thereby de-coupling block301from the ground supply voltage terminal. Similarly, the logic “1” state of the SLEEP1signal causes PMOS power-gating transistor451to turn off, thereby de-coupling block301from the VDDsupply voltage terminal. De-coupling block301from the VDDand ground supply voltage terminals effectively disables block301, thereby minimizing the static leakage current in this block.

If both the configuration data value CD1and the user control signal UC1are de-activated to a logic low state, then NOR gate421provides a SLEEP#1signal having a logic “1” state, and inverter411provides a SLEEP1signal having a logic “0” state. The logic “1” state of the SLEEP#1signal causes NMOS power-gating transistor455to turn on, thereby coupling block301to the ground supply voltage terminal. Similarly, the logic “0” state of the SLEEP1signal causes PMOS power-gating transistor451to turn on, thereby coupling block301to the VDDsupply voltage terminal. Coupling block301to the VDDand ground supply voltage terminals effectively enables block301.

Programmable logic block302may be enabled and disabled in response to configuration data value CD2and user control signal UC2, in the same manner as block301. Similarly, programmable logic block303may be enabled and disabled in response to configuration data value CD3and user control signal UC3, in the same manner as block301. Programmable logic block304may be enabled and disabled in response to configuration data value CD4and user control signal UC4, in the same manner as block301.

As described above, when a programmable logic block is used and active, the associated power-gating transistors are turned on. Conversely, when a programmable logic block is unused or inactive, the associated power gating transistors are turned off. The SLEEP1—SLEEP4and SLEEP#1—SLEEP#4signals can be controlled by the configuration data values CD1–CD4stored by configuration memory cells431–434, which are best suited for disabling the associated blocks at design time. If a block is not disabled at design time, this block can be disabled at run time by the user control signals UC1–UC4, which may be generated by the user logic, or by other means.

In accordance with another embodiment of the present invention, some blocks have multiple supply voltages. In this case all of the supply rails should be power-gated to achieve maximum power reduction. In accordance with another embodiment, only one switch element may be associated with each block. That is, the blocks are power-gated by decoupling the block from only one power supply terminal, and not both the VDDand ground supply voltage terminals, thereby conserving layout area.

The granularity of the power-gated programmable logic blocks can range from arbitrarily small circuits to significant portions of the PLD. The decision concerning the size of each programmable logic block is made by determining the desired trade-off between power savings, layout area overhead of the switch elements and the control circuit, and speed penalty. In a FPGA, each programmable logic block may be selected to include one or more configuration logic blocks (CLBs), input/output blocks (IOBs), and/or other resources of the FPGA (such as block RAM, processors, multipliers, adders, transceivers).

Another way to disable a programmable logic block is by scaling down the local supply voltage to the block as low as possible, which dramatically reduces the power consumption of the block. To scale down the local supply voltage in this manner, each independently controlled programmable logic block is powered by a separate switching regulator.

FIG. 5is a block diagram of a PLD500that implements switching regulators in accordance with one embodiment of the present invention. Similar elements inFIGS. 3 and 5are labeled with similar reference numbers. Thus, PLD500includes programmable logic blocks301–304and VDDvoltage supply305. In addition, PLD500includes switching regulators501–504, which are coupled between blocks301–304, respectively, and VDDvoltage supply305. Switching regulators501–504are controlled by control circuits511–514, respectively. In the described embodiment, switching regulators501–504reside on the same chip as blocks301–304. However, in other embodiments, these switching regulators can be located external to the chip containing blocks301–304. Switching regulators501–504can be programmably tuned to provide the desired supply voltages to the associated programmable logic blocks301–304. For example, switching regulator501can provide a full VDDsupply voltage to programmable logic block301when this block is used and active. However, switching regulator501can further be controlled to provide a reduced voltage (e.g., some percentage of the VDDsupply voltage) to programmable logic block301when this block is unused or inactive. This reduced voltage may be predetermined (by design or via testing) depending on the desired circuit behavior. For example, this reduced voltage may be the minimum voltage required to maintain the state of the associated blocks. The power consumption of block301is significantly reduced when the supplied voltage is reduced in this manner.

Switching regulators501–504are controlled in response to the configuration data values C1–C4stored in configuration memory cells511–514, respectively, and the user control signals U1–U4provided on user control terminals521–524, respectively. A configuration data value (e.g., C1) having an activated state will cause the associated switching regulator (e.g., switching regulator501) to provide a reduced voltage to the associated programmable logic block (e.g., block301). Similarly, a user control signal (e.g., U2) having an activated state will cause the associated switching regulator (e.g., switching regulator502) to provide a reduced voltage to the associated programmable logic block (e.g., block502). A configuration data value (e.g., C3) and an associated user control signal (e.g., U3) both having have deactivated states will cause the associated switching regulator (e.g., switching regulator503) to provide the full VDDsupply voltage to the associated programmable logic block (e.g., block503).

In accordance with one embodiment, configuration data values C1–C4may be selected at design time, such that reduced voltages are subsequently applied to unused blocks during run time. User control signals U1–U4may be selected during run time, such that reduced voltages are dynamically applied to inactive blocks at run time. Techniques for distributing multiple programmable down-converted voltages using on-chip switching voltage regulators are described in more detail in U.S. patent application Ser. No. 10/606,619, “Integrated Circuit with High-Voltage, Low-Current Power Supply Distribution and Methods of Using the Same” by Bernard J. New et al., which is hereby incorporated by reference.

In the embodiment ofFIG. 5, the granularity of the voltage scaled programmable logic blocks301–304should be fairly large because the overhead associated with switching regulators501–504is significant. In an FPGA, each programmable logic block301–304would most likely be divided into several clusters of configuration logic blocks (CLBs). The exact size of each programmable logic block may be determined by the desired trade-off among power savings, layout area overhead of the switching regulators, and the speed penalty.

FIG. 6is a block diagram of PLD500, which shows switching regulators501–504in accordance with one embodiment of the present invention. Switching regulators501–504include control blocks601–604, respectively, and high-voltage n-channel transistors611–614, respectively. High-voltage n-channel transistors611–614can tolerate high voltages and may have relatively thick gate dielectric layers (e.g., 50 to 60 Angstroms) and relatively wide channel regions. In some embodiments, the gate dielectric thickness of the high-voltage n-channel transistors611–614is approximately 4 to 6 times thicker than the gate dielectric thickness used in the programmable logic blocks301–304. The drain of each of n-channel transistors611–614is coupled to the VDDvoltage supply305. The gates of n-channel transistors611–614are coupled to receive the control voltages VC1–VC4, respectively, from the corresponding control blocks601–604. The source of each of n-channel transistors611–614is configured to provide an operating voltage V1–V4, respectively, to programmable logic blocks301–304, respectively. The source of each n-channel transistor611–614is also coupled to the corresponding control block601–604in a feedback configuration.

Each of n-channel transistors611–614forms a power switch between the VDDsupply voltage305and the associated programmable logic block. Thick oxide n-channel transistors611–614are used to implement the power switches to ensure that a high voltage, herein referred to as VBOOST, can be applied to the gates of n-channel transistors611–614when the associated programmable logic block is active. The high voltage VBOOSTincreases the drive current of n-channel transistors611–614. In accordance with one embodiment, the high voltage VBOOSTis about 2 to 2.5 times greater than VDD. When the high voltage VBOOSTis applied to the gate of one of transistors611–614, the corresponding operating voltage V1–V4is pulled up to the full VDDsupply voltage.

When a programmable logic block (e.g., programmable logic block301) is inactive, the associated operating voltage (e.g., V1) is reduced. The operating voltage applied to the associated programmable logic block is preferably selected to be high enough to retain data stored in this programmable logic block. In one embodiment, the operating voltage is reduced to a voltage that is about one half the VDDsupply voltage. The operating voltage is reduced by applying a low voltage VSTANDBYto the gate of the corresponding n-channel transistor (e.g., transistor611). In one embodiment, the low voltage VSTANDBYis about 80 to 100 percent of the VDDsupply voltage.

In accordance with one embodiment, each of control blocks601–604is independently controlled to provide either the high voltage VBOOSTor the low voltage VSTANDBYto the associated n-channel transistor611–614.

For example, control block601is configured to receive the user control signal U1and the configuration data value C1, which have been described above. If both the user control signal U1and the configuration data value C1are deactivated, then control block601provides a control voltage VC1equal to the high voltage VBOOSTto the gate of n-channel transistor611. As a result, an operating voltage V1equal to the VDDsupply voltage is applied to programmable logic block301.

However, if either user control signal U1or configuration data value C1is activated, then control block601provides a control voltage VC1equal to the low voltage VSTANDBYto the gate of n-channel transistor611. As a result, an operating voltage V1approximately equal to one half the VDDsupply voltage is applied to programmable logic block301.

To ensure that the operating voltage V1applied to programmable logic block301has a value of ½ VDDwhen the VSTANDBYvoltage is applied to the gate of transistor611, the control block601may include a feedback mechanism that adjusts the low voltage VSTANDBYsignal until the operating voltage V1is precisely equal to ½ VDD, or any other desired voltage.

It is well known that the gate current through a transistor typically increases by an order of magnitude for every 0.3 Volt increase in the VDDsupply voltage. It is therefore expected that reducing the operating voltage of a programmable logic block by half (½ VDD) will reduce the gate current through the transistors present in the programmable logic block by an order of magnitude or more. At the same time, the sub-threshold leakage of these transistors will also decrease with the reduced operating voltage. Based on earlier generation technology, the leakage current may be reduced by 70% or more when reducing the operating voltage to ½ VDD. Simulation of a ring oscillator shows that the ring oscillator will operate properly at the lower operating voltage (½ VDD). It can be expected the associated logic block will retain stored data using the lower operating voltage. Therefore, the proposed switching regulators are capable of achieving more than 70% reduction in leakage current without a significant increase in area penalty and without sacrificing desired functionality.

In accordance with yet another embodiment of the present invention, the operating voltages applied to different blocks of a PLD are tuned based on application-specific timing characteristics to achieve a more power-efficient design implementation. Both the hardware architecture necessary to enable the tuning and the software flow used to perform the tuning are described below. The tuning may be performed at design time to optimize resources that have timing slacks, or at runtime to exploit periods of low workload.

It can be determined at design time, after the place and route steps, which parts of the PLD design have timing slacks. Programmable logic blocks with timing slacks are faster than what is necessary to meet the timing requirements of the PLD design. These blocks may be tuned to be slower, such that their timing slacks are reduced or eliminated, without negatively impacting the timing requirements of the overall design. The methods by which the programmable logic blocks are tuned also lower the power consumption of these blocks, thereby achieving a significant power reduction with no timing penalty. In essence, tuning the chip in this manner customizes the programmable logic device to meet the timing requirements of the PLD design, thereby resulting in a more power-efficient design mapping.

FIG. 7is a flow diagram700illustrating a design flow in accordance with the operating voltage tuning embodiment of the present invention. Similar steps in flow diagrams100and700are labeled with similar reference numbers. Thus, flow diagram700includes Steps101–105of flow diagram100, which are described above. In addition, flow diagram700includes the step of performing a timing analysis on the PLD design (Step701). This timing analysis identifies the delays along various paths of the PLD design. This timing analysis may be performed after the place and route process has been completed in Step103.

After the timing analysis is complete, all paths having significant timing slacks are identified along with the amount of slacks they possess. In one embodiment, the timing slacks may be identified by comparing the expected delay of the path with the critical delay of the path. That is, the paths having timing slacks of N% or more of the critical delay are identified (Step702). For example, in a synchronous design where the critical delay is 10 ns, all paths more than 20% faster than the critical delay are identified. As a result, all paths with delay of 8 ns or less are identified. These paths can all be slowed by at least 2 ns without impacting the timing of the overall design.

The minimum operating voltage for each block is then determined (Step703). In accordance with one embodiment, a translation table is used (Step704), wherein the translation table provides a minimum operating voltage in response to a particular timing slack. Note that for larger timing slacks, the minimum operating voltage will be lower.

Following the identification of paths with significant timing slacks, each independently tunable programmable logic block in the device is examined to determine the maximum amount of acceptable delay increase, which corresponds to the minimum timing slack among all of the paths in the programmable logic block (Step703). Then, the minimum timing slack for each programmable logic block is converted to a minimum operating voltage by performing a lookup operation in a timing/voltage translation table (Step704). The timing/voltage translation table can be populated via chip testing. The entries in the translation table may take the format of “X ns decrease in speed requires a supply voltage adjustment by Y Volts”.

After the minimum operating voltage for each programmable logic block has been determined, the configuration bit stream is generated in Step104. The configuration bit stream is generated such that the configuration bit stream applies the minimum operating voltages as determined in Step704. As described in more detail below, the minimum operating voltages can be applied by setting the supply voltages to various programmable logic blocks of the PLD in response to the configuration data bits. The PLD is then configured in response to the configuration bit stream (Step105).

In an enhanced version of the above-described embodiment, an initial timing analysis is performed prior to the place and route operation (Step103), based on estimated delays of the various paths. The place and route step is then guided to group paths with significant timing slacks in to the same independently tunable block.

FIG. 8is a block diagram of a PLD800in accordance with the present embodiment of the invention. PLD800includes programmable logic blocks801–804, high voltage (VDD—H) supply805, low voltage (VDD—L) supply806, control circuit809and switch elements851–858. In the described embodiment, switch elements851–858are implemented by PMOS power-gating transistors. Control circuit809is implemented by inverters811–814, NOR gates821–824, configuration memory cells831–834, and user logic input terminals841–844. The high voltage supply805is configured to provide a full VDDsupply voltage, which is designated VDD—H. The low voltage supply806is configured to provide a reduced VDDsupply voltage, which is designated VDD—L. The VDD—L supply voltage is less than the VDD—H supply voltage by a selected percentage. For example, the VDD—L supply voltage may be 80 percent of the VDD—H supply voltage.

NOR gates821–824and inverters811–814are configured to generate the high voltage select signals Sel_H1–Sel_H4and the low voltage select signals Sel_L1–Sel_L4, in response to the configuration data values CD1–CD4stored in configuration memory cells831–834, respectively, and the user control signals UC1–UC4provided on user logic input terminals841–844, respectively.

For example, NOR gate821is coupled to receive configuration data value CD1from configuration memory cell831and user control signal UC1from user logic input terminal841. If either the configuration data value CD1or the user control signal UC1is activated to a logic high state (indicating that a substantial timing slack exists in programmable logic block801, and that the VDD—L voltage supply806should be coupled to this block801), then NOR gate821provides a low voltage select signal Sel_L1having a logic “0” state. In response, inverter811, which is coupled to the output terminal of NOR gate821, provides a high voltage select signal Sel_H1having a logic “1” state.

The logic “0” Sel_L1signal is applied to the gate of PMOS voltage select transistor852, thereby turning on this transistor and coupling programmable logic block801to the VDD—L voltage supply806. The logic “1” Sel_H1signal is applied to the gate of PMOS voltage select transistor851, thereby turning off this transistor and isolating programmable logic block801from the VDD—H voltage supply805. As a result, programmable logic block801operates in response to the VDD—L supply voltage, VDD—L, thereby minimizing the leakage current in this block.

If both the configuration data value CD1and the user control signal UC1are de-activated to a logic low state, (indicating that no substantial timing slack exists in programmable logic block801, and that the VDD—H voltage supply805should be coupled to this block801), then NOR gate821provides a low voltage select signal Sel_L1having a logic “1” state. In response, inverter811provides a high voltage select signal Sel_H1having a logic “0” state.

The logic “0” Sel_H1signal is applied to the gate of PMOS voltage select transistor851, thereby turning on this transistor and coupling programmable logic block801to the VDD—H voltage supply805. The logic “1” Sel_L1signal is applied to the gate of PMOS voltage select transistor852, thereby turning off this transistor and isolating programmable logic block801from the VDD—L voltage supply806. As a result, programmable logic block801operates in response to the VDD—H supply voltage, thereby enabling this block to operate at the required speed.

Programmable logic block802is coupled to the VDD—H voltage supply805or the VDD—L voltage supply806in response to configuration data value CD2and user control signal UC2, in the same manner as block801. Similarly, programmable logic block803is coupled to the VDD—H voltage supply805or the VDD—L voltage supply806in response to configuration data value CD3and user control signal UC3, in the same manner as block801. Programmable logic block804is coupled to the VDD—H voltage supply805or the VDD—L voltage supply806in response to configuration data value CD4and user control signal UC4, in the same manner as block801.

The Sel_H1–Sel_H4and Sel_L1–Sel_L4signals can be controlled by the configuration data values CD1–CD4stored by configuration memory cells831–834, which are best suited for coupling the associated blocks to the VDD—L voltage supply806at design time. If a block is not coupled to the VDD—L voltage supply806at design time, this block can be coupled to the VDD—L voltage supply806at run time by the user control signals UC1–UC4, which may be generated by the user logic.

In accordance with another embodiment, a tunable programmable logic device is implemented by enabling local supply voltage scaling. In this scheme, each independently tunable programmable logic block is powered by a separate variable-voltage switching regulator. The programmable logic blocks are tuned by configuring the regulators to adjust the operating voltages applied to the programmable logic blocks. When the operating voltage of a programmable logic block is scaled down, the block becomes slower, and the dynamic and static power consumed by the block are dramatically reduced.

FIG. 9is a block diagram of a PLD900that implements variable voltage switching regulators in accordance with the present embodiment of the invention. PLD900includes programmable logic blocks901–904, VDDvoltage supply905, configuration memory cell sets911–914, user control terminal sets921–924, and variable voltage switching regulators931–934. Voltage regulators931–934are configured to provide operating voltages to programmable logic blocks901–904, respectively, in response to the VDDsupply voltage. Each of voltage regulators931–934independently may select one of two or more possible operating voltages in response to the configuration data bits stored in configuration memory cell sets911–914, respectively. For example, if configuration memory cell set911includes two configuration memory cells (N=2), then voltage regulator931may provide operating voltages equal to VDD, 0.95VDD, 0.9VDDor 0.85 VDDin response to the configuration data bits stored in configuration memory cell set911. Other numbers of configuration memory cells and other operating voltages can be provided in other embodiments.

It is further possible to tune PLD900dynamically (during runtime) to exploit variations in the application's workload or performance requirements. Many user designs go through periods of low workload, during which the affected blocks may be tuned to lower speed and lower power. The tuning is preferably initiated by the user design, since the user has the best knowledge of when extended periods of low workload will occur. One way to enable dynamic scaling of local voltages is through dynamic reconfiguration of the programmable regulators using techniques described by Brandon J. Blodget et al., “Reconfiguration of a Programmable Logic Device Using Internal Control,” U.S. patent application Ser. No. 10/377,857.

In accordance with one embodiment, the user may implement such an adjustment by varying the N signals provided on the user control terminal set921, or by rewriting the desired configuration memory bits into configuration memory cell set911. The other variable voltage switching regulators932–934are controlled in the same manner as voltage regulator931.

In the described embodiment, variable voltage switching regulators931–934reside on the same chip as programmable logic blocks901–904. However, in other embodiments, these voltage regulators931–934can be located external to the chip containing blocks901–904.

Moreover, although the examples illustrate a PLD divided into four blocks, it should be understood that the PLD can be divided into arbitrary number of blocks, and each block can be of arbitrary granularity. In the embodiment ofFIG. 9, the granularity of the voltage scaled programmable logic blocks901–904should be fairly large because the overhead associated with variable voltage switching regulators931–934is significant. In an FPGA, each programmable logic block901–904would most likely be divided into several clusters of configuration logic blocks (CLBs). The exact size of each programmable logic block is determined by the desired trade-off between power savings and the layout area overhead of the switching regulators. Techniques for distributing multiple programmable voltages by using on-chip switching voltage regulators are described by Bernard J. New et al., in “Integrated Circuit With High-Voltage, Low-Current Power Supply Distribution And Methods Of Using The Same,” U.S. patent application Ser. No. 10/606,619.

Communication across programmable logic blocks having different operating voltages does not require special attention if the voltage difference is relatively small. However, when signals propagate from a low voltage block to a high voltage block, even small voltage differences can lead to significant DC current leakage in the high-voltage block due to transistors that are not completely turned off. To eliminate such DC current leakage, and to facilitate communication across two blocks of arbitrarily different voltages, level-shifters should be used as interfacing logic. To reduce area and speed overhead, level-shifters can be integrated into flip-flops, which are typically present on the programmable logic device.

FIG. 10is a circuit diagram of a level-shifting flip-flop1000, for use in accordance with one embodiment of the present invention. Flip-flop1000includes inverters1001–1004, complementary pass gates1011–1012, p-channel transistors1021–1022, and n-channel transistors1031–1034. Inverters1001–1003and complementary pass gates1011–1012operate in response to the VDD—L supply voltage. When the CLK# signal is high (CLK is low), inverter1001is enabled to route the inverse of the input data value D to inverter1002. Note that the input data value D is defined at the VDD—L voltage level. Inverter1003and complementary pass gates1011–1012are disabled by the low CLK signal at this time.

When the CLK signal transitions to a logic high state (CLK# is low), inverter1001is disabled and inverter1003is enabled, thereby allowing the data value D to be latched into cross-coupled inverters1002–1003. The logic low CLK# signal disables n-channel transistors1033and1034. The high CLK signal also enables complementary pass gates1011–1012, thereby applying the data value D and the inverse data value D# to the gates of n-channel transistors1031and1032, respectively. As a result, the data value D or the inverse data value D# turns on one of n-channel transistors1031or1032. For example, if the data value D has a logic low state, then n-channel transistor1031is turned off and n-channel transistor1032is turned on. Turned on transistor1032pulls down the gate voltage of p-channel transistor1021to ground, thereby turning on this transistor1021. Turned on transistor1021applies the VDD—H voltage to the gate of p-channel transistor1022(thereby turning this transistor off), and to the input terminal of inverter1004(which provides a logic low Q output signal). Note that the Q output signal has been translated to the VDD—H voltage level. When the CLK signal transitions to a logic low state (CLK# is high), the n-channel transistors1033–1034turn on, thereby latching the data value D until the next rising edge of the CLK signal. Level-shifting flip flop1000is described in more detail by M. Takahashi et al., “A 60 mW MPEG4 Video Codec using Clustered Voltage Scaling with Variable Supply-Voltage Scheme,” Journal of Solid State Circuits, vol. 33, no. 11, pp. 1772–1780, November 1998.

Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to a person skilled in the art. For example, although the described embodiments included four programmable logic blocks, it is understood that other numbers of blocks can be used in other embodiments. Thus, the invention is limited only by the following claims.