Borderless contacts for dual-damascene interconnect process

For multiple layer interconnections using copper, the top interconnection layer and the via hole to the bottom layer are self-aligned on at least one side. The self-alignment eliminates the need for providing a border for the contact of the via hole to the interconnection. The self-alignment is accomplished by using a nitride mask, which defines one side of both the via hole and the interconnection. After the top surface of the copper interconnection is planarized, another layer of copper interconnection can be superimposed over the first interconnection in a similar manner.

BACKGROUND 
This invention relates to interconnection system for semiconductor 
integrated Circuits--in particular to multilayer interconnections. 
In the development of interconnection system for very large scale 
integration (VLSI) circuits, the devices have been shrunk to sub-micron 
dimensions. The speed of sub-micron transistors is very high, such that 
the speed of an integrated circuit (IC) is now limited by the 
interconnection rather than the transistor itself 
What limits the speed of the interconnection is the finite resistivity of 
the interconnection material. Traditionally, aluminum has been used in the 
past. However the resistivity of aluminum is higher than copper. 
Therefore, the trend today for high speed IC development is to use copper 
as interconnections. Another trend today for high packing density is to 
use multiple layer interconnections for complicated ICs. 
One promising approach is the "dual damascene" interconnection technique, 
where a contact and an interconnection via hole are masked and etched in 
succession in oxide layers. The contact plug and the interconnection which 
buries the via hole are formed with one single metal deposition and single 
chemical-mechanical planarization process. The process is especially 
suitable for copper interconnection, because the copper cannot be readily 
etched by plasma, which is widely used for other etching processes in IC 
fabrication. 
There are other process integration problems in fabricating this dual 
damascene interconnection. The difficulty arises when the second 
interconnection is masked and patterned after the first via hole for 
contacting the bottom is masked and patterned. Since the upper contact of 
the via hole invariably overlaps the interconnecting line, the photoresist 
for patterning the interconnection fills up the opening for the via hole 
in the oxide completely. During exposure, the photoresist in the opening 
experiences different focusing from the photoresist on top of the oxide 
due to the different amount of photoresist development and due to 
unevenness of the photoresist, the resultant interconnection pattern is 
distorted and dimensional control is very difficult. The problem also 
exists when the mask sequence is reversed. 
Furthermore, in circuit design, a margin must be allowed around the contact 
of the upper via hole plug. Otherwise, the etched interconnection pattern 
may miss the contact. When a border is made around the contact to allow 
for misalignment, the density of the IC is compromised. 
Another problem of using copper is atom migration due to diffusion. 
SUMMARY 
An object of this invention is to minimize the dimension of damascene 
interconnection for integrated circuits. Another object of this invention 
is to minimize the dimensional distortion for via holes and 
interconnections. Another object of this invention is to provide multiple 
layer damascene interconnections. Still another object of this invention 
is to simplify the damascene interconnection process. A further object of 
this invention is to provide diffusion barrier against copper atom 
migration. 
These objects are achieved by aligning at least one side of the 
interconnection with the via hole connecting the interconnection to the 
bottom substrate. Self-alignment eliminates the need to provide a border 
to the contact between the via hole and the interconnection to prevent 
misalignment. The self-alignment is accomplished by using a nitride mask 
which serves to define at least one side of both the via hole and the 
interconnection. The nitride also serves as a diffusion barrier against 
copper atom migration. 
Multiple layer interconnection can be added the first interconnection is a 
similar manner.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
The approach is to fabricate a damascene interconnection with a contact via 
hole and the interconnection self-aligned on at one side. Nitride layer is 
used to define the pattern for both the via hole and the interconnection. 
The nitride also serves as CMP polishing stop as well as a etch stop 
during the etching step for processing a second layer of interconnection. 
The processing steps for a single layer of copper interconnection is shown 
in FIGS. 1a 1g. 
1) On an in-process wafer substrate 10 with or without a first level metal 
interconnection is deposited a thick layer of oxide 11 (1-1.5 .mu.m) and a 
thin layer of nitride 12 (300-600 Angstroms) in succession as shown in 
FIG. 1a. 
2) A photo-mask for the copper interconnection is used to open a window 14 
and pattern the nitride for interconnection into two sections 12' and 12" 
with photoresist 13 as shown in FIG. 1b. Because of the difference in etch 
rate, the etching stops at the top surface of the oxide layer. 
3) After the photoresist 13 is stripped, a second masking step is performed 
using a second photoresist 13' to pattern the via hole 15 as shown in FIG. 
1c. The via pattern is oversized so that only one or more sides are 
defined by the via mask and the other sides to be defined by a 
metallization pattern in the nitride layer. 
4) The via hole 15 is etched through with the fill thickness of the oxide 
11 with reactive ion etching (RIE) as shown in FIG. 1c. 
5) The second photoresist 13' is stripped. Using the nitride pattern 12' 
and 12" as a mask, the oxide layer 11' is etched a half way through its 
thickness to become a thinner oxide layer 11'b for the interconnection 
pattern as shown in FIG. 1d. 
6) After depositing a barrier layer 16' and 16" of titanium nitride (TiN) 
of 500 Angstroms, copper 17 is electroplated in the cavities in the oxide 
until it is overfilled over the top of the structure as shown in FIG. 1e. 
This 17 layer serves both as an interconnection and a via contact to the 
bottom substrate 10. Note that the left side of the interconnection 17a 
and the left side of the via hole 17b are self-aligned. Thus there is no 
need to provide a border of the contact area of the via hole to the 
interconnection to prevent misalignment. 
7) The overfilled metal is polished off using the chemical mechanical 
planarization (CMP) technique until the copper surface 14 is planarized 
with surfaces 16' and 16" of the nitride layer. 
8) A thin barrier layer 18 of TiN is then deposited selectively by 
electrodeless deposition on the top metal surface as shown in FIG. 1g. 
Note that the nitride layer 12" serves to define one side of both the via 
pattern 117b and the interconnection 17a. The nitride also serves as a 
diffusion barrier against copper atom migration. The nitride layer further 
acts as a etch stop when more metal layers are fabricated of the structure 
in FIG. 1g. 
A second embodiment of this present for two metal layers of interconnection 
is shown in FIGS. 2a-2d. The process is as follows: 
1) On an in-process wafer with first metal interconnection 20 already in 
place, a four layered dielectric film stack of oxide 21 (0.7-1.0 .mu.m), a 
thin nitride layer 22 (300-600 Angstroms), a second oxide layer 27 
(0.7-1.0 .mu.m) and a second nitride layer 28 (300-600 Angstroms) are 
deposited in succession as shown in FIG. 2a. 
2) A photo-masking step for the second metal interconnection is applied, 
and the second nitride layer 28 is etched with plasma to open a window 30 
for subsequent second metal interconnection. The photoresist pattern 29', 
29" is then hardened with ultra-violet light. as shown in FIG. 2b. 
3) A second photo-masking 32', 32" step for the via hole 31 is applied over 
the first photoresist pattern. The via hole pattern is oversized, so that 
only one side (the right-hand side in FIG. 2c) or more sides are defined 
by the via hole mask. The other sides (such as the left-hand side in FIG. 
2c) are defined by the previous second metal interconnection mask, and is 
therefore self-aligned. 
4) A The via hole 31 is etched through the full thickness of the four 
layered stack of second nitride layer 28", second oxide layer 27, the 
first nitride layer 22 and first oxide layer 21 with reactive ion etching 
(RIE), changing the etching chemicals at layer boundaries until the top of 
the first metal lines 20 is reached as shown in FIG. 2c. 
5) Both photoresist patterns 32', 32" and 29', 29" are stripped. Using the 
top nitride layer 28' and 28" as a mask, the interconnection pattern is 
etched in the top oxide 27 to become oxide layers 27' and 27" until the 
top surface of the middle nitride 22' is reached as shown in FIG. 2d. 
6) The rest of the steps are the same as the first embodiment for the 
single layer 
This second embodiment has the further advantage over the first embodiment 
in that the etch step in FIG. 2d stops at the nitride layer 22' in the 
middle of the dielectric. The thickness of the second metal 
interconnection, which is equal to the oxide 27' thickness plus the 
nitride 28' thickness, is precisely defined. 
While the preferred embodiments of the invention have been shown and 
described, it will be apparent to those skilled in the art that various 
modifications may be made in the embodiments without departing from the 
spirit of the present invention. Such modifications are all within the 
scope of this invention.