IC STRUCTURES WITH IMPROVED BONDING BETWEEN A SEMICONDUCTOR LAYER AND A NON-SEMICONDUCTOR SUPPORT STRUCTURE

Embodiments of the present disclosure relate to methods of fabricating IC devices with IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure, as well as resulting IC devices, assemblies, and systems. An example method includes providing a semiconductor material over a semiconductor support structure and, subsequently, depositing a first bonding material on the semiconductor material. The method further includes depositing a second bonding material on a non-semiconductor support structure such as glass or mica wafers, followed by bonding the face of the semiconductor material with the first bonding material to the face of the non-semiconductor support structure with the second bonding material. Using first and second bonding materials that include silicon, nitrogen, and oxygen (e.g., silicon oxynitride or carbon-doped silicon oxynitride) may significantly improve bonding between semiconductor layers and non-semiconductor support structures compared to layer transfer techniques.

BACKGROUND

DETAILED DESCRIPTION

Overview

For purposes of illustrating IC devices and assemblies with IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure as described herein, it might be useful to first understand phenomena that may come into play in certain IC arrangements. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

Non-semiconductor support structures (e.g., glass, mica, sapphire, etc.) provide unique advantages for forming IC circuits of semiconductor devices (e.g., transistors) on, compared to conventional semiconductor substrates. For example, non-semiconductor support structures may have lower dielectric constants than those of conventional semiconductor substrates (e.g., lower than about 11), which may advantageously decrease various parasitic effects associated with the IC device, since such parasitic effects are typically proportional to the dielectric constant of the surrounding medium. Many types of semiconductor materials that could serve as a foundation for forming IC circuits of semiconductor devices cannot be directly grown on non-semiconductor support structures. Examples of such semiconductor materials include III-N materials (e.g., GaN, AlGaN, InGaN, and so on), substantially monocrystalline silicon (Si), germanium (Ge), or SiGe, and so on. Rather, their fabrication could involve high-temperature growth processes (e.g., epitaxial growth processes) to grow target semiconductor materials on semiconductor support structures (e.g., semiconductor substrates), followed by a layer transfer process where a layer of a semiconductor material grown on a semiconductor support structure is transferred onto a non-semiconductor support structure. In such fabrication approaches, attachment of a semiconductor layer to a non-semiconductor support structure may rely simply on molecular interactions between the semiconductor layer and the non-semiconductor support structure.

While fabrication approaches as described above could be suitable in many settings, there are also potential drawbacks. For example, inventors of the present disclosure realized that delamination of the semiconductor layers from the non-semiconductor support structures may occur with time, compromising performance of IC devices and assemblies.

Embodiments of the present disclosure relate to methods of fabricating IC devices with IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure, as well as resulting IC devices, assemblies, and systems. An example method includes providing (e.g., epitaxially growing) a semiconductor material over a semiconductor support structure and, subsequently, depositing a first bonding material on the semiconductor material. The method further includes depositing a second bonding material on a support structure of a non-semiconductor material (i.e., on a non-semiconductor support structure) having a dielectric constant that is smaller than a dielectric constant of silicon (e.g., on a glass or a mica wafer), followed by bonding the face of the semiconductor material with the first bonding material to the face of the non-semiconductor support structure with the second bonding material. Using first and second bonding materials that include silicon, nitrogen, and oxygen (e.g., silicon oxynitride), e.g., bonding materials that include carbon, silicon, nitrogen, and oxygen (e.g., carbon-doped silicon oxynitride) may significantly improve bonding between semiconductor layers and non-semiconductor support structures, compared to layer transfer techniques described above. IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure may be used in many applications, e.g., as chiplets for power delivery, where semiconductor materials such as GaN or other III-N materials may be used to form IC devices (e.g., transistors) of voltage regulator circuits. In some embodiments, non-semiconductor support structures may be glass support structures, and may include any type of glass materials, since glass has dielectric constants in a range between about 5 and 10.5. However, in other embodiments, non-semiconductor support structures may include materials other than glass, e.g., mica or sapphire, as long as those materials have sufficiently low dielectric constants.

In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, a term “interconnect” may be used to describe any element formed of an electrically conductive material for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In general, the “interconnect” may refer to both conductive lines/wires (also sometimes referred to as “lines” or “metal lines” or “trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). In general, a term “conductive line” may be used to describe an electrically conductive element isolated by a dielectric material typically comprising an interlayer low-k dielectric that is provided within the plane of an IC chip. Such conductive lines are typically arranged in several levels, or several layers, of metallization stacks. On the other hand, the term “conductive via” may be used to describe an electrically conductive element that interconnects two or more conductive lines of different levels of a metallization stack. To that end, a via may be provided substantially perpendicularly to the plane of an IC chip or a support structure over which an IC structure is provided and may interconnect two conductive lines in adjacent levels or two conductive lines in not adjacent levels. A term “metallization stack” may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC chip.

In another example, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die,” the term “insulating” means “electrically insulating,” the term “conducting” means “electrically conducting,” unless otherwise specified. Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “an electrically conductive material” may include one or more electrically conductive materials. If used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide. Furthermore, the term “connected” may be used to describe a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” may be used to describe either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” may be used to describe one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value, e.g., within +/−5% of a target value or within +/−1% of a target value, based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art.

In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.

Various devices and assemblies illustrated in the present drawings do not represent an exhaustive set of IC devices with IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure as described herein, but merely provide examples of such devices. In particular, the number and positions of various elements shown in the present drawings is purely illustrative and, in various other embodiments, other numbers of these elements, provided in other locations relative to one another may be used in accordance with the general architecture considerations described herein. Further, the present drawings are intended to show relative arrangements of the elements therein, and the devices and assemblies of these figures may include other elements that are not specifically illustrated (e.g., various interfacial layers). Similarly, although particular arrangements of materials are discussed with reference to the present drawings, intermediate materials may be included in the IC devices and assemblies of these figures. Still further, although some elements of the various cross-sectional views are illustrated in the present drawings as being planar rectangles or formed of rectangular solids, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of the IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure as described herein.

Various IC assemblies with IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure as described herein may be implemented in, or associated with, one or more components associated with an IC or/and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

Example IC Devices and Methods

FIG.1provides a schematic block illustration of an example IC structure100with improved bonding between a semiconductor layer and a non-semiconductor support structure, according to some embodiments of the present disclosure. As shown inFIG.1, in general, the IC structure100may include a non-semiconductor support structure110, a bonding material120, and a semiconductor layer130that includes a semiconductor material.

In some embodiments, the non-semiconductor support structure110may include a glass material, e.g., a glass substrate, a glass die, a glass wafer or a glass chip. Examples of glass materials include silicon oxide materials, possibly doped with elements and compounds such as boron, carbon, aluminum, hafnium oxide, e.g., in doping concentrations of between about 0.01% and 10%. In other embodiments, the non-semiconductor support structure110may include other solid materials having a dielectric constant lower than that of Si, e.g., lower than about 10.5. In some embodiments, the non-semiconductor support structure110may include mica, sapphire, or other non-semiconductor materials. A thickness of the non-semiconductor support structure110may be of any value for the non-semiconductor support structure110to provide mechanical stability for the IC structure100and, possibly, to support inclusion of various devices for further reducing the parasitic effects in the IC structure100. In some embodiments, the non-semiconductor support structure110may have a thickness between about 0.2 micrometer (micron) and 1000 micron, e.g., between about 0.5 and 5 micron, or between about 1 and 3 micron. Although a few examples of materials from which the non-semiconductor support structure110may be formed are described here, any material with sufficiently low dielectric constant that may serve as a foundation to which the semiconductor layer130may be bonded using the bonding material120, as described herein, falls within the spirit and scope of the present disclosure.

The semiconductor layer130may include a semiconductor material, and, in particular, a plurality of semiconductor devices fabricated based on the semiconductor material. While the semiconductor layer130is described herein as including a semiconductor material, the semiconductor material may include a plurality of different semiconductor materials. For example, in some embodiments, the semiconductor layer130may include different portions of different semiconductor materials, e.g., to enable formation of transistors with different threshold voltages. For example, the semiconductor layer130may include an area of a first semiconductor material and another area of a second semiconductor material, where the first semiconductor material is a relatively high-bandgap semiconductor material such as GaN, while the second semiconductor material is a lower bandgap semiconductor material such as Si, Ge, or SiGe. In another example, in some embodiments, at least portions of the semiconductor layer130may include layers of different semiconductor materials. For example, the semiconductor layer130may include a layer of a III-N semiconductor channel material and a layer of polarization material that forms a heterojunction with the III-N semiconductor channel material, for forming III-N transistors as known in the art.

In various embodiments, the semiconductor layer130may include semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the semiconductor layer130may include a monocrystalline semiconductor. In some embodiments, the semiconductor layer130may have a thickness between about 5 and 10000 nanometers, including all values and ranges therein, e.g., between about 10 and 500 nanometers, between about 10 and 200 nanometers, or about between 10 and 100 nanometers.

In some embodiments, the semiconductor layer130may be an upper layer of a semiconductor support structure (e.g., the semiconductor layer130may include silicon, e.g., an upper layer of silicon of a silicon substrate). Thus, in some implementations, the semiconductor layer130may be viewed as a part of the semiconductor support structure over which it is disposed, or as a part of the crystalline semiconductor upper part of such support structure. In some embodiments, an intermediate layer may be included as an insulating layer, such as an oxide isolation layer, over the semiconductor support structure and the semiconductor layer130may be provided over the oxide isolation layer, in a silicon-on-insulator (SOI) manner.

In some embodiments, the semiconductor layer130may be/include an intrinsic IV or III-V semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, nominal impurity dopant levels may be present within the semiconductor layer130, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the semiconductor layer130may be relatively low, for example below about 1015dopants per cubic centimeter (cm−3), and advantageously below 1013cm−3.

In some embodiments, the semiconductor layer130may include a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In some embodiments, the semiconductor layer130may include a binary, ternary, or quaternary III-V compound semiconductor that is an alloy of two, three, or even four elements from groups III and V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth.

In some embodiments, the improved bonding method as described herein may be used to provide layers of III-N semiconductor materials onto non-semiconductor support structures. In such embodiments, the semiconductor layer130may include a III-N semiconductor material. In some embodiments, the III-N semiconductor material of the semiconductor layer130may be formed of a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of nitrogen (N). In some embodiments, the III-N semiconductor material of the semiconductor layer130may be a binary, ternary, or quaternary III-N compound semiconductor that is an alloy of two, three, or even four elements from group III of the periodic table (e.g., boron, aluminum, indium, gallium) and nitrogen.

In general, the III-N semiconductor material of the semiconductor layer130may be composed of various III-N semiconductor material systems including, for example, N-type or P-type III-N materials systems, depending on whether the III-N semiconductor material is an N-type or a P-type transistor. For some N-type transistor embodiments, the semiconductor layer130may advantageously include an III-N material having a high electron mobility, such as, but not limited to, GaN. In some embodiments, the III-N semiconductor material may be a ternary III-N alloy, such as InGaN, or a quaternary III-N alloy, such as AlInGaN, in any suitable stoichiometry. For some other exemplary N-type transistor embodiments, the semiconductor layer130may advantageously include an III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the semiconductor layer130may include a ternary III-V alloy, such as InGaAs or GaAsSb. For some InxGa1-xAs fin embodiments, In content in the semiconductor layer130may be between 0.6 and 0.9, and advantageously at least 0.7 (e.g., In0.7Ga0.3As).

For exemplary P-type transistor embodiments, the semiconductor layer130may advantageously include a group IV material having a high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. For some exemplary embodiments, the semiconductor layer130may have a Ge content between 0.6 and 0.9, and advantageously is at least 0.7.

In some embodiments, the semiconductor layer130may include a thin-film semiconductor material, in which embodiments the transistors formed in the semiconductor layer130could be thin-film transistors (TFTs). A TFT is a special kind of a field-effect transistor (FET), made by depositing a thin film of an active semiconductor material, as well as a dielectric layer and metallic contacts, over a support structure that may be a non-conducting (and non-semiconducting) support structure. During operation of a TFT, at least a portion of the active semiconductor material forms a channel of the TFT, and, therefore, the thin film of such active semiconductor material is referred to herein as a “TFT channel material.” This is different from conventional, non-TFT, transistors where the active semiconductor channel material is typically a part of a semiconductor substrate, e.g., a part of a silicon wafer. In various such embodiments, the semiconductor layer130may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, the semiconductor layer130may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc.

In some embodiments, the semiconductor layer130may include IGZO. IGZO-based devices have several desirable electrical and manufacturing properties. IGZO has high electron mobility compared to other semiconductors, e.g., in the range of 20-50 times than amorphous silicon. Furthermore, amorphous IGZO (a-IGZO) transistors are typically characterized by high band gaps, low-temperature process compatibility, and low fabrication cost relative to other semiconductors. IGZO can be deposited as a uniform amorphous phase while retaining higher carrier mobility than oxide semiconductors such as zinc oxide. Different formulations of IGZO include different ratios of indium oxide, gallium oxide, and zinc oxide. One particular form of IGZO has the chemical formula InGaO3(ZnO)5. Another example form of IGZO has an indium:gallium:zinc ratio of 1:2:1. In various other examples, IGZO may have a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and/or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). IGZO can also contain tertiary dopants such as aluminum or nitrogen.

The plurality of semiconductor devices that may be formed in the semiconductor layer130may include transistors, diodes, and other devices that have active portions (e.g., channel regions of transistors) formed of the semiconductor material of the semiconductor layer130. For example, the semiconductor layer130may include transistors, where portions of the semiconductor material of the semiconductor layer130form channel regions of the transistors. In various embodiments, such transistors may be planar transistors or non-planar transistors (e.g., FinFETs, nanoribbon transistors, nanowire transistors, etc.). In some embodiments, the transistors formed in the semiconductor layer130may form IC circuits of different functionality, such as voltage regulator circuits, power delivery circuits, compute logic circuits, memory circuits, etc. In some embodiments, the semiconductor layer130may further include a plurality of interconnects for routing signals and/or power to, from, and between various semiconductor devices implemented in the semiconductor layer130.

The bonding material120between the non-semiconductor support structure110and the semiconductor layer130may be a material that includes silicon, nitrogen, and oxygen (e.g., the bonding material120may be silicon oxynitride), where the atomic percentage of any of these materials may be at least 1%, e.g., between about 1% and 50%, indicating that these elements are added deliberately, as opposed to being accidental impurities which are typically in concentration below about 0.1%. In some embodiments, the bonding material120may be carbon-doped, e.g., a carbon-doped silicon oxynitride (e.g., SiOCN), where the atomic percentage of carbon may be between about 0.001% and 10%. In some embodiments, a thickness of the bonding material120may be between about 1 and 10 nanometers, e.g., between about 2 and 8 nanometers, or between about 4 and 6 nanometers, e.g., around 5 nanometers.

FIG.2provides a flow diagram of an example method200of fabricating an IC structure with improved bonding between a semiconductor layer and a non-semiconductor support structure, according to some embodiments of the present disclosure. The method200may be used to fabricate the IC structure100as shown inFIG.1.FIGS.3A-3Fillustrate IC structures300as example results of various processes of the method200shown inFIG.2, according to some embodiments of the present disclosure. In particular, each ofFIGS.3A-3Fillustrates a cross-section of the IC structure300taken along the y-z plane of the reference coordinate system x-y-z shown inFIG.1. A number of elements labeled inFIGS.3A-3Fwith reference numerals are illustrated in these figures with different patterns, with a legend showing the correspondence between the reference numerals and patterns being provided at the bottom of each drawing page containingFIGS.3A-3F.

The example fabrication method shown inFIGS.2and3may include other operations not specifically shown inFIGS.2and3, such as various cleaning or planarization operations as known in the art. For example, in some embodiments, any of the layers of the IC structure may be cleaned prior to, after, or during any of the processes of the fabrication method described herein, e.g., to remove oxides, surface-bound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using e.g., a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g., using hydrofluoric acid (HF)). In another example, the top surfaces of the IC structures described herein may be planarized prior to, after, or during any of the processes of the fabrication method described herein, e.g., to remove overburden or excess materials. In some embodiments, planarization may be carried out using either wet or dry planarization processes, e.g., planarization be a chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.

As shown inFIG.2, the method200may begin with a process202that includes forming a semiconductor layer over a semiconductor support structure. An IC structure300A, shown in FIG.3A, illustrates an example result of performing the process202. As shown inFIG.3A, the IC structure300A may include a semiconductor support structure302, an intermediate layer304, and a semiconductor layer306. In some embodiments, the intermediate layer304may be absent and the semiconductor layer306may be provided directly over the semiconductor support structure302. The semiconductor layer306may include any of the materials described with reference to the semiconductor layer130, as, in a later stage of the method200, at least a portion of the semiconductor layer306will form the semiconductor layer130of an IC structure with improved bonding as described herein. Forming the semiconductor layer306in the process202may include epitaxially growing the semiconductor layer306over the intermediate layer304or over the semiconductor support structure302.

In some embodiments, the intermediate layer304may include an insulator, and the semiconductor material306may include silicon (e.g., epitaxially grown silicon, e.g., crystalline silicon) and, together, the semiconductor support structure302, the intermediate layer304, and the semiconductor material306may form a SOI substructure. In case the semiconductor layer306includes a III-N semiconductor material, the intermediate layer304may include a buffer material. In some embodiments, the buffer material may be a layer of a semiconductor material that has a band gap larger than that of the III-N semiconductor material of the semiconductor layer306. Furthermore, a properly selected semiconductor for the buffer material may enable better epitaxy of the III-N semiconductor material thereon, e.g., it may improve epitaxial growth of the III-N semiconductor material in terms of a bridge lattice constant or amount of defects. For example, a semiconductor that includes aluminum, gallium, and nitrogen (e.g., AlGaN) or a semiconductor that includes aluminum and nitrogen (e.g., AlN) may be used as the buffer material when the semiconductor layer306is a semiconductor that includes gallium and nitrogen (e.g., GaN). Other examples of materials for the buffer material of the intermediate layer304may include materials typically used as ILD, described above, such as oxide isolation layers, e.g., silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride. In various embodiments, the intermediate layer304may have a thickness between about 100 and 5000 nanometers, including all values and ranges therein, e.g., between about 200 and 1000 nanometers, or between about 250 and 500 nanometers.

The semiconductor support structure302may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the semiconductor support structure302may be a crystalline substrate formed using a bulk silicon. In other implementations, the semiconductor support structure302may be formed using alternate materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide, or other combinations of group III-V materials (i.e., materials from groups III and V of the periodic system of elements), group II-VI (i.e., materials from groups II and IV of the periodic system of elements), or group IV materials (i.e., materials from group IV of the periodic system of elements). In some embodiments, the semiconductor support structure302may be non-crystalline. In some embodiments, the semiconductor support structure302may be a printed circuit board (PCB) substrate. Although a few examples of materials from which the semiconductor support structure302may be formed are described here, any material that may serve as a foundation upon which the semiconductor layer130as described herein may be built falls within the spirit and scope of the present disclosure.

The method200may then proceed with a process204that includes depositing a bonding material over the semiconductor layer formed in the process202. An IC structure300B, shown inFIG.3B, illustrates an example result of performing the process204. As shown inFIG.3B, the IC structure300B may include a bonding material308, deposited over the semiconductor layer306. The bonding material308may include any of the materials described with reference to the bonding material120. In some embodiments, a thickness of the bonding material308may be about half of the thickness described above with respect to the bonding material120. In various embodiments, the bonding material308may be deposited in the process204using techniques such as, but not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or physical vapor deposition (PVD) (e.g., evaporative deposition, magnetron sputtering, or e-beam deposition.

The method200may also include a process206that includes depositing a bonding material over a non-semiconductor support structure. An IC structure300C, shown inFIG.3C, illustrates an example result of performing the process206. As shown inFIG.3C, the IC structure300C may include the bonding material308as described above, deposited over a non-semiconductor support structure310. The non-semiconductor support structure310may include any of the non-semiconductor support structures described with reference to the non-semiconductor support structure110. In some embodiments, the bonding material308deposited over the non-semiconductor support structure310in the process206may have substantially the same material composition and/or the same thickness as the bonding material308deposited over the semiconductor layer306in the process204. In other embodiments, material compositions and/or thicknesses of the bonding materials30deposited in the processes204and206may be different. Although the process206is shown inFIG.2to be after the process204, in various embodiments, the process206may be performed before, after, or simultaneously with any portions of the processes202and204.

The method200may then proceed with a process208that includes bonding the faces of the semiconductor layer and the non-semiconductor support structure that have bonding materials thereon together. An IC structure300D, shown inFIG.3D, illustrates an example result of performing the process208. As shown inFIG.3D, the IC structure300D may be formed by flipping the IC structure300B over and bonding it to the top of the IC structure300C, so that the bonding material308deposited over the semiconductor layer306in the process204is brought in contact with and bonded to the bonding material308deposited over the non-semiconductor support structure310in the process206. During the bonding of the process208, the IC structures300B and300C may be brought together in this manner, possibly while applying a suitable pressure and heating up the assembly to a suitable temperature (e.g., to moderately high temperatures, e.g., between about 50 and 200 degrees Celsius) for a duration of time, thus forming an IC structure300E as shown inFIG.3E, with the bonded materials308deposited in the processes204and206being adjoined together, providing an adhesive interface that ensures attachment of the semiconductor layer306and the non-semiconductor support structure310to one another. The use of the bonding material308as described herein makes the IC structure300E have improved bonding between the semiconductor layer306and the non-semiconductor support structure302, compared to what may be achievable using layer transfer techniques.

The method200may also, optionally, include a process210in which some or all of the semiconductor support structure used in the process202may be removed. An IC structure300F, shown inFIG.3F, illustrates an example result of performing the process210. As shown inFIG.3F, the semiconductor support structure302and the intermediate layer304may be removed in the process210. In some embodiments, such removal may be performed using any suitable thinning/polishing processes as known in the art, to reveal the semiconductor layer306. At this point, the non-semiconductor support structure310may provide the mechanical stability to the microelectronic assembly of the IC structure300F.

FIG.3Ffurther illustrates that, in some embodiments, ICs312may be included in the semiconductor layer306. The ICs312may include any suitable IC devices formed based on the semiconductor layer306. For example, one or more of the ICs312may include voltage regulator circuits. Although not specifically shown inFIG.3F, the semiconductor layer306may further include a plurality of interconnects to/from/between the ICs312.

IC structures300E and300F are some examples of how the IC structure100may be implemented. In general, the IC structure100with improved bonding between a semiconductor layer and a non-semiconductor support structure as disclosed herein may be included in any suitable electronic device.FIGS.4-6illustrate various examples of devices and components that may include one or more IC structures100.

FIG.4is a cross-sectional side view of an IC package2200that may include an IC structure with improved bonding between a semiconductor layer and a non-semiconductor support structure in accordance with any of the embodiments disclosed herein, e.g., that may include any embodiments of the IC structure100, described herein. In some embodiments, the IC package2200may be a system-in-package (SiP).

As shown inFIG.4, the IC package2200may include a package substrate2252. The package substrate2252may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, etc.), and may have conductive pathways extending through the dielectric material between the face2272and the face2274, or between different locations on the face2272, and/or between different locations on the face2274. For example, the package substrate2252may include conductive contacts2263that are coupled to conductive pathways2262through the package substrate2252, allowing circuitry within the dies2256and/or the interposer2257to electrically couple to various ones of the conductive contacts2264(or to other devices included in the package substrate2252, not shown).

The IC package2200may include an interposer2257coupled to the package substrate2252via conductive contacts2261of the interposer2257, first-level interconnects2265(e.g., die-to-package substrate (DTPS) interconnects), and the conductive contacts2263of the package substrate2252. The first-level interconnects2265illustrated inFIG.4are solder bumps, but any suitable first-level interconnects2265may be used. In some embodiments, no interposer2257may be included in the IC package2200; instead, any of the dies2256may be coupled directly to the conductive contacts2263at the face2272by first-level interconnects2265, as is shown inFIG.4with the die2256shown in the middle.

The IC package2200may include one or more dies2256coupled to the interposer2257via conductive contacts2254of the dies2256, first-level interconnects2258(e.g., die-to-die (DTD) interconnects), and conductive contacts2260of the interposer2257. The conductive contacts2260may be coupled to conductive pathways (not shown) through the interposer2257, allowing circuitry within the dies2256to electrically couple to various ones of the conductive contacts2261(or to other devices included in the interposer2257, not shown). The first-level interconnects2258illustrated inFIG.4are solder bumps, but any suitable first-level interconnects2258may be used. As used herein, a “conductive contact” may refer to a portion of electrically conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

The IC package2200may also include an IC structure2250, coupled to the package substrate2252by the first-level interconnects2265similar to how the interposer2257or any of the dies2256may be coupled to the package substrate2252. The IC structure2250may be the IC structure100according to any embodiments described herein. To that end, the semiconductor layer306, the bonding material308, and the non-semiconductor support structure310are individually labeled inFIG.4. In some embodiments, one or more of the dies2256may be coupled to the IC structure2250using first-level interconnects2258. For example, the IC structure2250may include conductive contacts2261on the face of the IC structure2250that is closest to the package substrate2252, and further include conductive contacts2260on the face of the IC structure2250that is farthest away from the package substrate2252. The conductive contacts2261of the IC structure2250and the first-level interconnects2265coupled to these conductive contacts may couple the IC structure2250to the conductive contacts2263at the face2272of the package substrate2252. The conductive contacts2260of the IC structure2250and the first-level interconnects2258coupled to these conductive contacts may couple the IC structure2250to the conductive contacts2254at the opposing face of the die2256. In some embodiments, through-vias2255may be coupled between some of the conductive contacts2261of the IC structure2250and some of the conductive contacts2260of the IC structure2250. The through-vias2255may be used to provide power from the package substrate2252and/or from the second-level interconnects2270to the die2256coupled to the IC structure2250. The through-vias2255may be formed in the IC structure2250after the bonding using the bonding material308has been performed. In some embodiments, a pitch of the through-vias2255may be between about 5 and 70 micrometers, e.g., between about 25 and 50 micrometers. Formation of the through-vias2255may create local stresses, so it may be advantageous to arrange the through-vias2255at a certain minimum distance from one another to ensure structural stability of the IC structure100(e.g., of the IC structure2250). In some embodiments, cross-sectional dimensions (e.g., diameters or widths) of the through-vias2255are between about 7 and 11 micrometers, e.g., about 9 micrometers. In some embodiments, the cross-sectional dimensions of the through-vias2255may be between about 35% and 65%, e.g., between about 45% and 55%, of the pitch of the vias. Although not specifically shown inFIG.4, the semiconductor layer306may include one or more ICs312as described above, e.g., in order to perform voltage regulation before providing power and/or signals from the package substrate2252and/or from the second-level interconnects2270to the die2256coupled to the IC structure2250. In such implementations, the IC structure2250may be a chiplet for power delivery to the die2256that is coupled to the IC structure2250. One or more of the through-vias2255may be coupled to any of the ICs312that may be included in the semiconductor layer306of the IC structure2250. In some embodiments, the semiconductor layer306may be closer to the die2256than the non-semiconductor support structure302(i.e., the non-semiconductor support structure302may be closer to the package substrate2252than the semiconductor layer306). In some embodiments, any of the dies2256may include one or more of the IC structures100with improved bonding between a semiconductor layer and a non-semiconductor support structure in accordance with any of the embodiments disclosed herein.

In some embodiments, an underfill material2266may be disposed between the package substrate2252and the interposer2257around the first-level interconnects2265, and a mold compound2268may be disposed around the dies2256, the interposer2257, and the IC structure2250, and in contact with the package substrate2252. In some embodiments, the underfill material2266may be the same as the mold compound2268. Example materials that may be used for the underfill material2266and the mold compound2268are epoxy mold materials, as suitable. Second-level interconnects2270may be coupled to the conductive contacts2264. The second-level interconnects2270illustrated inFIG.4are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects2270may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects2270may be used to couple the IC package2200to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference toFIG.5.

In embodiments in which the IC package2200includes multiple dies2256, the IC package2200may be referred to as a multi-chip package (MCP). The dies2256may include circuitry to perform any desired functionality. For example, one or more of the dies2256may be logic dies (e.g., silicon-based dies), and one or more of the dies2256may be memory dies (e.g., high bandwidth memory), including embedded logic and memory devices as described herein. In some embodiments, any of the dies2256may include one or more IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure, e.g., as discussed above; in some embodiments, at least some of the dies2256may not include any of the IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure.

The IC package2200illustrated inFIG.4may be a flip chip package, although other package architectures may be used. For example, the IC package2200may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package2200may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although three dies2256are illustrated in the IC package2200ofFIG.4, an IC package2200may include any desired number of the dies2256. An IC package2200may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face2272or the second face2274of the package substrate2252, or on either face of the interposer2257, or on either face of the IC structure2250. More generally, an IC package2200may include any other active or passive components known in the art.

FIG.5is a cross-sectional side view of an IC device assembly2300that may include components having one or more IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure in accordance with any of the embodiments disclosed herein, e.g., that may include any embodiments of the IC structure100, described herein. The IC device assembly2300includes a number of components disposed on a circuit board2302(which may be, e.g., a motherboard). The IC device assembly2300includes components disposed on a first face2340of the circuit board2302and an opposing second face2342of the circuit board2302; generally, components may be disposed on one or both faces2340and2342. In particular, any suitable ones of the components of the IC device assembly2300may include any of one or more IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure in accordance with any of the embodiments disclosed herein; e.g., any of the IC packages discussed below with reference to the IC device assembly2300may take the form of any of the embodiments of the IC package2200discussed above with reference toFIG.4(e.g., may include one or more IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure).

The IC device assembly2300illustrated inFIG.5includes a package-on-interposer structure2336coupled to the first face2340of the circuit board2302by coupling components2316. The coupling components2316may electrically and mechanically couple the package-on-interposer structure2336to the circuit board2302, and may include solder balls (e.g., as shown inFIG.5), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure2336may include an IC package2320coupled to an interposer2304by coupling components2318. The coupling components2318may take any suitable form for the application, such as the forms discussed above with reference to the coupling components2316. The IC package2320include one or more IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure as described herein. Although a single IC package2320is shown inFIG.5, multiple IC packages may be coupled to the interposer2304; indeed, additional interposers may be coupled to the interposer2304. The interposer2304may provide an intervening substrate used to bridge the circuit board2302and the IC package2320. Generally, the interposer2304may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer2304may couple the IC package2320(e.g., a die) to a BGA of the coupling components2316for coupling to the circuit board2302. In the embodiment illustrated inFIG.5, the IC package2320and the circuit board2302are attached to opposing sides of the interposer2304; in other embodiments, the IC package2320and the circuit board2302may be attached to a same side of the interposer2304. In some embodiments, three or more components may be interconnected by way of the interposer2304.

The interposer2304may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer2304may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer2304may include metal interconnects2308and vias2310, including but not limited to through-silicon vias (TSVs)2306. The interposer2304may further include embedded devices2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer2304. The package-on-interposer structure2336may take the form of any of the package-on-interposer structures known in the art. Descriptions provided for the interposer2304are also applicable to the interposer2257of the IC package2200, shown inFIG.4.

The IC device assembly2300may include an IC package2324coupled to the first face2340of the circuit board2302by coupling components2322. The coupling components2322may take the form of any of the embodiments discussed above with reference to the coupling components2316, and the IC package2324may take the form of any of the embodiments discussed above with reference to the IC package2320.

The IC device assembly2300illustrated inFIG.5includes a package-on-package structure2334coupled to the second face2342of the circuit board2302by coupling components2328. The package-on-package structure2334may include an IC package2326and an IC package2332coupled together by coupling components2330such that the IC package2326is disposed between the circuit board2302and the IC package2332. The coupling components2328and2330may take the form of any of the embodiments of the coupling components2316discussed above, and the IC packages2326and2332may take the form of any of the embodiments of the IC package2320discussed above. The package-on-package structure2334may be configured in accordance with any of the package-on-package structures known in the art.

FIG.6is a block diagram of an example computing device2400that may include one or more components with one or more IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure in accordance with any of the embodiments disclosed herein, e.g., that may include any embodiments of the IC structure100, described herein. Any of the components of the computing device2400may include an IC package2200as described with reference toFIG.4. Any of the components of the computing device2400may include an IC device assembly2300as described with reference toFIG.5.

A number of components are illustrated inFIG.6as included in the computing device2400, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device2400may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-chip (SoC) die.

Additionally, in various embodiments, the computing device2400may not include one or more of the components illustrated inFIG.6, but the computing device2400may include interface circuitry for coupling to the one or more components. For example, the computing device2400may not include a display device2406, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device2406may be coupled. In another set of examples, the computing device2400may not include an audio input device2418or an audio output device2408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device2418or audio output device2408may be coupled.

In some embodiments, the communication chip2412may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip2412may include multiple communication chips. For instance, a first communication chip2412may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip2412may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip2412may be dedicated to wireless communications, and a second communication chip2412may be dedicated to wired communications.

The computing device2400may include battery/power circuitry2414. The battery/power circuitry2414may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device2400to an energy source separate from the computing device2400(e.g., AC line power).

The computing device2400may include a display device2406(or corresponding interface circuitry, as discussed above). The display device2406may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device2400may include an audio output device2408(or corresponding interface circuitry, as discussed above). The audio output device2408may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device2400may include an audio input device2418(or corresponding interface circuitry, as discussed above). The audio input device2418may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device2400may include a GPS device2416(or corresponding interface circuitry, as discussed above). The GPS device2416may be in communication with a satellite-based system and may receive a location of the computing device2400, as known in the art.

The computing device2400may include an other output device2410(or corresponding interface circuitry, as discussed above). Examples of the other output device2410may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

SELECT EXAMPLES

Example 1 provides an IC device that includes an IC structure that includes a support structure of a non-semiconductor material having a dielectric constant that is smaller than a dielectric constant of silicon (e.g., a glass support structure); a semiconductor layer, wherein a portion of the semiconductor layer includes a semiconductor material; and a bonding material between the support structure and the semiconductor layer, wherein the bonding material includes silicon, nitrogen, and oxygen, e.g., the bonding material is silicon oxynitride.

Example 2 provides the IC device according to example 1, wherein the bonding material further includes carbon, e.g., the bonding material is carbon-doped silicon oxynitride. The atomic percentage of carbon may be between about 0.001% and 10%.

Example 3 provides the IC device according to any one of the preceding examples, where a thickness of the bonding material is between about 1 and 10 nanometers, e.g., between about 2 and 8 nanometers, or between about 4 and 6 nanometers, e.g., around 5 nanometers.

Example 4 provides the IC device according to any one of the preceding examples, where the semiconductor layer includes a plurality of transistors, where channel regions of the transistors include portions of the semiconductor material.

Example 5 provides the IC device according to example 4, where the plurality of transistors form voltage regulator circuitry.

Example 6 provides the IC device according to any one of the preceding examples, where each of the support structure and the semiconductor layer includes a first face and a second face, the second face being opposite the first face, the bonding material is between the second face of the support structure and the second face of the semiconductor layer, and the IC structure further includes a plurality of vias that extend between the first face of the support structure and the first face of the semiconductor layer. Such vias may be used to deliver power from a further IC component (e.g., a package substrate or a carrier substrate), coupled to the first face of the support structure, to another die coupled to the first face of the semiconductor layer.

Example 7 provides the IC device according to example 6, where a pitch of the vias is between about 5 and 70 micrometers, e.g., between about 25 and 50 micrometers.

Example 8 provides the IC device according to examples 6 or 7, where cross-sectional dimensions (e.g., diameters or widths) of the vias are between about 7 and 11 micrometers, e.g., about 9 micrometers. In some embodiments, the cross-sectional dimensions of these vias may be between about 35% and 65%, e.g., between about 45% and 55%, of the pitch of the vias.

Example 9 provides the IC device according to any one of examples 6-8, further including a die, coupled to the first face of the semiconductor layer by DTD interconnects, where at least one of the vias is coupled to at least one of the DTD interconnects.

Example 10 provides the IC device according to example 9, further including a package substrate, coupled to the first face of the support structure by DTPS interconnects, where at least one of the vias coupled to one of the DTD interconnects is also coupled to one of the DTPS interconnects.

Example 11 provides the IC device according to example 10, where a pitch of the DTPS interconnects is larger than a pitch of the DTD interconnects.

Example 12 provides the IC device according to any one of the preceding examples, where the semiconductor material includes a III-N semiconductor material.

Example 13 provides the IC device according to any one of the preceding examples, where the semiconductor material includes germanium.

Example 14 provides the IC device according to any one of the preceding examples, where the semiconductor material includes silicon and germanium (e.g., SiGe).

Example 15 provides the IC device according to any one of the preceding examples, where the semiconductor layer includes a plurality of portions with different semiconductor materials, where the semiconductor material is one of the different semiconductor materials in one of the portions.

Example 16 provides the IC device according to example 15, where a first portion of the plurality of portions includes a III-N semiconductor material, and a second portion of the plurality of portions includes silicon germanium or germanium.

Example 17 provides an IC package that includes an IC device; and a further IC component, coupled to the IC device, where the IC device may be an IC device according to any one of the preceding examples.

Example 18 provides the IC package according to example 17, where the further IC component includes one of a package substrate, an interposer, or a further IC die.

Example 19 provides the IC package according to examples 17 or 18, where the IC package includes, or is a part of, at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.

Example 20 provides the IC package according to any one of examples 17-19, where the IC device includes, or is a part of, at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.

Example 21 provides an electronic device that includes a carrier substrate; and one or more of the IC device according to any one of the preceding examples and the IC package according to any one of the preceding examples, coupled to the carrier substrate.

Example 22 provides the electronic device according to example 21, where the carrier substrate is a motherboard.

Example 23 provides the electronic device according to example 21, where the carrier substrate is a PCB.

Example 24 provides the electronic device according to any one of examples 21-23, where the electronic device is a wearable electronic device (e.g., a smart watch) or handheld electronic device (e.g., a mobile phone).

Example 25 provides the electronic device according to any one of examples 21-24, where the electronic device further includes one or more communication chips and an antenna.

Example 26 provides the electronic device according to any one of examples 21-25, where the electronic device is an RF transceiver.

Example 27 provides the electronic device according to any one of examples 21-25, where the electronic device is one of a switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, or a downconverter of an RF communications device, e.g., of an RF transceiver.

Example 28 provides the electronic device according to any one of examples 21-25, where the electronic device is a computing device.

Example 29 provides the electronic device according to any one of examples 21-28, where the electronic device is included in a base station of a wireless communication system.

Example 30 provides the electronic device according to any one of examples 21-28, where the electronic device is included in a user equipment device (i.e., a mobile device) of a wireless communication system.

Example 31 provides a method of fabricating an IC device. The method includes providing a semiconductor material over a semiconductor support structure; depositing a first bonding material on the semiconductor material; depositing a second bonding material on a support structure of a non-semiconductor material having a dielectric constant that is smaller than a dielectric constant of silicon (e.g., a glass support structure); and bonding a face of the semiconductor material with the first bonding material to a face of the support structure of the non-semiconductor material with the second bonding material, where each of the first and second bonding materials includes silicon, nitrogen, and oxygen, e.g., the bonding materials include silicon oxynitride.

Example 32 provides the method according to example 31, further including: after the bonding, removing the semiconductor support structure.

Example 33 provides the method according to example 31, wherein removing the semiconductor support structure includes polishing or grinding away the semiconductor support structure until the semiconductor material is exposed.

Example 34 provides the method according to any one of examples 31-33, a thickness of the first bonding material or a thickness of the second bonding material is between about 0.5 and 5 nanometers, e.g., between about 1 and 4 nanometers, or between about 2 and 3 nanometers, e.g., around 2.5 nanometers.

Example 35 provides the method according to any one of examples 31-34, where the non-semiconductor support structure includes glass.

Example 36 provides the method according to any one of examples 31-35, where the non-semiconductor support structure includes mica.

Example 37 provides the method according to any one of examples 31-36, further including processes for forming the IC device according to any one of the preceding examples (e.g., for forming the IC device according to any one of examples 1-16).