Dual trench rectifier and method for forming the same

A structure of dual trench rectifier comprises of the following elements. A plurality of trenches are formed parallel in an n− epitaxial layer on an n+ semiconductor substrate and spaced with each other by a mesa. A plurality of recesses are formed on the mesas. Each the trench has a trench oxide layer formed on the sidewalls and bottom thereof, and a first poly silicon layer is filled therein to form MOS structures. Each the recess has a recess oxide layer formed on the sidewalls and bottom thereof, and a second poly silicon layer is filled therein to form MOS structures. A plurality of p type bodies are formed at two sides of the MOS structures in recesses. A top metal is formed above the semiconductor substrate for serving as an anode. A bottom metal is formed beneath the semiconductor substrate for serving as a cathode.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device, and more particularly to a new structure of dual trench rectifier diode and the method for forming the same.

BACKGROUND OF THE INVENTION

The Schottky diode is an important power device and is widely applied for power supply switch, motor control, telecom switch, industrial automation, electrical automation, etc., and several high speed power switches. The very important position of Schottky diode is due to its good performance. For instance, the leakage current of the Schottky diode at reverse bias is acceptable even though it is larger than that of typical PN type diodes; the forward voltage drop is low; the reverse recovery time (tRR) is very short; and the resistance reaches about 250 voltages at reverse bias. However, the leakage current of Shottky diode is higher than that of PN type diodes, and the leakage current is unstable and increasing following the increasing reverse bias because the image charge potential barrier is lower. Another drawback is that the reliability of the metal-semiconductor junction is decreasing when temperature is increasing, thereby to lower the capability of Schottky diode bearing forward and reverse impulse.

There are many methods for manufacturing the dual trench rectifiers in prior art. One of them is a Taiwan patent application with serial number 101140637 proposed by the inventor of this application.

Referring toFIG. 1, the structure of a well known trench rectifier includes an active area15A and an end area15T. Several trenches are formed in the active area15A of an n− epitaxy layer105on a heavy doped n+ semiconductor substrate100. A trench oxide layer10G is formed on the bottom and sidewalls of each trench. A polysilicon layer is then filled fully in the trenches. The mesas between two trenches are formed with p+ heavy doped areas20, like two small ears hanging on the two upper sidewalls of the mesa adjacent to the trenches. A metal silicide60is formed on the polysilicon layer40and the mesas. A top metal layer80is formed for serving as an anode which connects the active area15A and extends to cover a portion of the end area15T. The end area15T includes a big trench. An oxide layer10, a sidewall polysilicon40S and a trench gate oxide10G are formed on the big trench. Another metal layer is formed on the lower surface of the heavy doped n+ semiconductor substrate100for serving as a cathode.

SUMMARY OF THE INVENTION

The present invention provides a new structure of dual trench MOS rectifier and the method for forming the same. First, a trench etching process is performed to form trenches in an n− epitaxial layer on a heavy doped n+ semiconductor substrate. Then, a thermal oxidation process is performed to form a trench oxide layer. After, a first polysilicon layer is deposited to fill fully and cover the trenches.

An etching back process or a chemical mechanical polishing (CMP) process is applied to remove the first polysilicon layer and the oxide layer over mesas. Then, a photoresist pattern is formed to define the locations of recesses, and an etching process is performed to form the recesses by using the photoresist pattern as an etching mask. After forming the recesses, the photoresist pattern is removed and a process for forming a recess oxide layer is performed. A second polysilicon layer is then deposited and etched back to remove the second polysilicon layer over the mesas.

An ion implanting procedure is applied to implant p type conductive ions into the mesas. After, the oxide layer on the mesas is removed, and a process for forming a top metal layer is performed.

In the second embodiment of the present invention, the steps before forming and etching back the second polysilicon layer are same as that in the first embodiment. Then, a photoresist pattern is formed to define rows of MOS structures and ion implanted areas. The photoresist pattern is applied as a mask to remove the exposed second polysilicon layer. After, a first ion implanting procedure is performed to implant p type conductive ions into the mesas. The oxide layer on the mesas is removed, and a procedure for forming the top metal layer is performed.

In the first embodiment of the present invention, the structure of the dual trench MOS rectifier is to form a plurality of trenches parallel in n− epitaxial layer on the heavy doped n+ semiconductor substrate, wherein each the trench includes the trench oxide layer formed on the bottom and sidewalls thereof The plurality of recesses are formed in the n− epitaxial layer of the mesas and are divided by the mesas, wherein the plurality of recesses includes the recess oxide layer formed on the bottom and sidewalls thereof A first polysilicon layer doped with a conductive impurity is formed to fill fully the trenches, and a second polysilicon layer doped with a conductive impurity is formed to fill fully the recesses. A plurality of p type bodies (ion implanted areas) are formed in the n− epitaxil layer below the mesas at two sides of the MOS structures. A top metal layer is blanketed to cover the first and second polysilicon layers, the p type ion implanted areas on the semiconductor substrate for serving as an anode, and a bottom metal layer is formed beneath the heavy doped n+ semiconductor substrate to serve as a cathode.

The structure disclosed in the second embodiment is similar to that illustrated in the first embodiment of the present invention. The difference is that the second polysilicon layer is formed in the recesses and overfilled to cover the mesas, thereby higher than the recess oxide layer on the first polysilicon layer of the trenches. The second polysilicon layer is patterned to form rows of MOS structures perpendicular to the trenches, wherein the MOS structures includes the second polysilicon layer, the recess oxide layer and the epitaxial layer. The p type bodies are formed in the n− epitaxial layer below the mesas adjacent to the MOS structures.

The present invention also discloses varied designs of the two above embodiments. In the varied designs, the p type bodies below the mesas further include two heavy doped n type conductive ion areas.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention discloses a dual trench MOS rectifier. Please refer to the top view shown inFIG. 2aand the cross-sectional views shown inFIG. 11AtoFIG. 11C. The symbol “#” of FIG. #A, FIG. #B and FIG. #C means the number of figures, and the capital letters A, B and C after the symbol “#” correspond with the lines A-A′, B-B′ and C-C′ shown in top views of Figs. For best understanding of the detailed structures, the top metal layer180is not shown in the top views. The relations between the top metal layer180and other elements and the detailed structures of devices are shown in the cross sectional views.

In the first embodiment of the present invention, the dual trench MOS rectifier comprised of the following elements. A plurality of trenches115formed parallel in an n− epitaxial layer105on a heavy doped n+ semiconductor substrate100. Each the trench115has a trench oxide layer120formed on a bottom and sidewalls thereof A plurality of recesses125are formed spaced by a distance in the n− epitaxial layer105below mesas118. Each the recess125has a recess oxide layer127formed on a bottom and sidewalls thereof A first polysilicon layer130with a conductive impurity formed in the plurality of trenches115, and a second polysilicon layer140with a conductive impurity formed and filled full in the plurality of recesses125to form MOS structures. The MOS structures include the second polysilicon layer140, the recess oxide layer127and the n− epitaxial layer105. A plurality of p type bodies (ion implanted areas)135are formed in the n− epitaxial layer105below the mesas118at two sides of the MOS structures. A top metal layer180is formed on top of the first and second polysilicon layers and P type bodies for serving as an anode, and a bottom metal layer190is formed beneath the heavy doped n+ semiconductor substrate for serving as a cathode.

A varied design of the first embodiment is that each the p type body135includes two n+ ion implanted areas145which are applied to lower the initial bias VF. Please refer to the top view shown inFIG. 2band the cross sectional views shown inFIG. 13AtoFIG. 13C.

In the second embodiment, referring to the top view shown inFIG. 3aand the cross sectional views shown inFIG. 16AtoFIG. 16C. The second polysilicon layer140doped with a conductive impurity is formed in and overfilled the recesses125to cover the mesas, thereby to be higher than the recess oxide layer127on the first polysilicon layer130of the trenches115. The second polysilicon layer140is then patterned to form rows of MOS structures perpendicular to the trenches115. The rows of the MOS structures include the second polysilicon layer140, the recess oxide layer127and the n− epitaxial layer105. A plurality of p type bodies135are formed in the n− epitaxial layer105below the mesas118adjacent to the MOS structures. A top metal layer180is formed on the MOS structures and the p type bodies135for serving as an anode, and a bottom metal layer190is formed beneath the heavy doped n+ semiconductor substrate100for serving as a cathode.

A varied design of the second embodiment is that the p type bodies135further include two n+ ion implanted areas145, as illustrated in the top view shown inFIG. 3band the cross sectional views shown inFIG. 18AtoFIG. 18C.

The detailed process is illustrated as follows. It is noted that the minus sign “−” following n or p means lightly doped and the plus sign “+” means heavy doped.

Please refer to the cross sectional view shown inFIG. 4, which illustrate that the n+ semiconductor substrate100with heavy doped n type impurity includes an n− epitaxial layer105with lightly doped n type impurity. A dry etching process is performed to form the plurality trenches115by using the photoresist pattern as an etching mask (not shown) or using a hard mask (not shown) as well known in prior art.

Then, a thermal oxidation process is performed to form the trench oxide layer120on the bottom and sidewalls of the trenches115. This step can also fix the damage occurred in the etching step before.

Please refer toFIG. 5, the first polysilicon layer130with a conductive impurity is deposited and doped to fill fully and cover the trenches115. Then, an etching back procedure or a chemical mechanical polishing (CMP) process is applied to remove the first polysilicon layer130over the mesas118until the upper surface of the n− epitaxial layer105of the mesas118is exposed.

Then, referring toFIG. 6AandFIG. 6B, which illustrate respectively the cross sectional views perpendicular to the directions of the trenches115at two different locations. After etching back, the photoresist pattern122is formed to define the locations of recesses. The recesses are formed on the mesas118between the trenches115along the A-A′ line shown inFIG. 2a, and the photoresist pattern122is applied to provide protection along the B-B′ line shown inFIG. 2b.

A plasma etching process is performed to form the recesses125in the mesas118by using the photoresist pattern122as an etching mask. Referring toFIG. 7AandFIG. 7B, which illustrate respectively the cross sectional views perpendicular to the directions of the trenches115.FIG. 7Cillustrates the cross sectional view along the directions of the trenches115. After the photoresist is removed, a thermal oxidation process is performed to form the recess oxide layer127on the bottom and sidewalls of the recesses125and on the upper surface of the mesas adjacent to the recesses125and on the first polysilicon layer130. It is noted that the recess oxide layer is thinner than the trench oxide layer120.

The second polysilicon layer140is deposited and doped with a conductive impurity to overfill all the recesses125.FIG. 8AtoFIG. 8Cshow the cross sectional views along three lines A-A′, B-B′ and C-C′ shown inFIG. 2a.

Then, as shown inFIG. 9AtoFIG. 9C, an etching back process or a chemical mechanical polishing (CMP) process is applied to remove the second polysilicon layer140over the mesas118until the recess oxide layer127on the mesas118is removed and the upper surface of the n− epitaxial layer105of the mesas118is exposed, for forming the MOS structures in the recesses125.

Please refer toFIG. 10AtoFIG. 10C. An ion implanting procedure is performed to implant totally the p type conductive ions, to form p type bodies135below the mesas118adjacent to the MOS structures. The dosage of implanted ions causes the concentration of n type ions in the p type bodies135higher than that in the n− epitaxial layer105about 1 to 3 orders in magnitudes, such as 1E12-1E14/cm2. The energy of implanting is about 10 keV-1000 keV. Then, a buffer solution or a diluted HF solution is applied to remove the oxide layer on the planar surface.

Please refer to cross sectional views shown inFIG. 11AtoFIG. 11C. The top metal layer180is formed. A self-aligned metal silicide process is performed before forming the top metal layer180. For example, a sputtering process is performed to deposit Ti/TiN, and then an RTA or a wet etching is applied to remove the unreacted metal layer. The top metal layer180generally includes one to three compositional layers, such as TiNi/Ag, TiW/Al or Al, etc.

The varied design of the first embodiment is to form two n+ areas (n type heavy doped areas) in the p type body135.FIG. 12AtoFIG. 12Cillustrate the photoresist pattern masks are applied for ion implanting.FIG. 13AtoFIG. 13Cillustrate the cross sectional views of the final structures of the p type body135including two n+ ion implanted areas145.

In the second embodiment of the present invention, the steps before etching back the second polysilicon layer140are same as those in the first embodiment, as shown inFIG. 4toFIG. 8. After, the following steps are performed.

The photoresist pattern142is formed to define the second polysilicon layer140. Then, the second polysilicon layer140is etched by plasma using the photoresist pattern142as an etching mask to define the MOS structures. The rows of MOS structures include the second polysilicon layer140, the recess oxide layer127and the n− epitaxial layer105. As shown inFIG. 3AandFIG. 14AtoFIG. 14C, the second polysilicon layer140along the B-B′ line is removed, and the second polysilicon layer140along the A-A′ line is protected by the photoresist pattern142. The photoresist pattern along C-C′ line is as shown inFIG. 14C. The structure after etching is shown as inFIG. 14AtoFIG. 14C.

The photoresist pattern142is removed, and then an ion implanting is performed to totally implant the p type conductive ions, to form p type bodies135below the mesas adjacent to the rows of MOS structures. The dosage of ion implanting is same as that in the first embodiment.

Please refer toFIG. 16AtoFIG. 16C, the buffer solution or diluted HF solution is applied to remove the oxide layer on the planar surface completely. The top metal layer180is then formed. The method of forming the top metal layer180is same as that in the first embodiment.

The second embodiment can also be varied as aforementioned to the first embodiment. The n+ conductive impurity is implanted in two sides of each p type body135.FIG. 17AtoFIG. 17Cillustrate the photoresist pattern for ion implanting.FIG. 18AtoFIG. 18Cillustrate the cross sectional views after forming the top metal layer180.

The present invention has following advantages. Comparing to the traditional trench rectifier, the dual trench rectifier provided by the present invention has the MOS structures formed in the trenches and the MOS structures formed in the recesses, thereby to eliminate the Schottky contact and lower reverse leakage current considerably. Besides, the oxide layer of the MOS structures formed in the recesses is thin enough to lower the initial bias VF. Further, the n+ heavy ion implanted areas145are formed at two sides of p type bodies135adjacent to the rows of the MOS structures can reduce the initial bias in advance. On the other hand, the reverse leakage current can be effectively lowered, and the carrying current can be increased on the same size of the planar area because the structures formed in the trenches and the recesses.

The preferred embodiments of the invention have been set forth as above description, however the spirit and scope of the present invention are not limited to the aforementioned embodiments. It is easy for those who with ordinary skill in the art to understand and have modifications of the disclosed embodiments for the same purpose.

Therefore, the appended claims are intended to cover all embodiments which do not depart from the spirit and scope of the invention.