Solid-state imaging device and imaging apparatus utilizing a dynamic bias current for reduced power consumption

A solid-state imaging device includes: a sensor unit; a vertical scanning unit and a horizontal scanning unit; column amplifier units provided at respective vertical signal lines corresponding to columns in the sensor unit and amplifying signal charges read out to the vertical signal lines; a bias current adjustment unit controlling current flowing in the vertical signal lines by changing bias current of the column amplifier units; a signal processing unit processing signal charges read out to the vertical signal lines and amplified at the column amplifier units into image signals to be outputted; an output unit to which signals outputted from the signal processing unit are supplied; a drive signal generation unit supplying drive signals to the vertical scanning unit, the horizontal scanning unit, the signal processing unit and the output unit; and an input unit supplying plural drive mode signals to the drive signal generation unit.

CROSS REFERENCE TO RELATED APPLICATIONS

The present invention contains subject matter related to Japanese Patent Application JP 2007-046497 filed in the Japanese Patent Office on Feb. 27, 2007, the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a solid-state imaging device applied to, for example, an image input system, and an imaging apparatus using the same.

2. Description of the Related Art

As an imaging apparatus using a solid-state imaging device, a digital camera, a PC camera, an optical mouse, a portable TV telephone and the like are developed in recent years. These apparatuses require low voltage and low power consumption from the point of increasing the battery operating time or miniaturization, in addition to from the point of image quality. Since a CCD sensor has difficulties in the above points, a MOS-type solid-state imaging device is often applied. The MOS-type solid-state imaging device has characteristics such as single power supply, lower power consumption, system-on-chip, and further has large degree of freedom in reading out. For example, it is possible to output only part of an image (cutting operation) or output image information discontinuously (thinning-out operation).

A MOS-type solid-state imaging device in related arts will be explained with reference toFIG. 6.

InFIG. 6, a MOS-type solid-state imaging device1includes a sensor unit2in which many unit pixels including photo diodes performing photoelectric conversion and MOS switches are arranged in a matrix state, a vertical scanning circuit3and a horizontal scanning circuit4driving the sensor unit2, a CDS (Correlated Double Sampling)/signal holding circuit5receiving signals of a row of pixels in the sensor unit2, an output amplifier6, a timing generator circuit7generating pulses for operating respective units of the vertical scanning circuit3, the horizontal scanning circuit4, the CDS/signal holding circuit5and the output amplifier6and a serial interface8(refer to JP-A-2002-209149 (Patent Document 1)).

Vertical scanning lines10from the vertical scanning circuit3are commonly connected to pixels of respective rows in the sensor unit2, and vertical scanning pulses φV [φV1, φV2, . . . φVn] are simultaneously supplied from the vertical scanning circuit3to pixels of respective rows through the vertical scanning lines10. Vertical signal lines11are commonly connected to pixels of respective columns in the sensor unit2, and the respective vertical signal lines11are connected to a horizontal signal line12through the CDS/signal holding circuit5. The horizontal signal line12is connected to the input side of the output amplifier6. The horizontal scanning circuit4supplies horizontal scanning pulses φH[φH1, φH2, . . . φHn] for selecting pixel signals from the CDS/signal holding circuit5and outputting them to the horizontal signal line12to horizontal switches of the CDS/signal holding circuit5. Serial data is supplied to the serial interface8from the outside. A synchronizing signal and a clock signal are supplied to the serial interface8and the timing generator circuit7from the outside.

In the above CMOS-type solid-state imaging device1, the serial interface8receives data from the outside, controlling the operation of the timing generator circuit7according to the data. The timing generator circuit7generates drive pulses for operating the vertical scanning circuit3, the horizontal scanning circuit4, the CDS/signal holding circuit5and the output amplifier6according to data, supplying them to respective units. The sensor unit2is scanned by the vertical scanning circuit3, that is to say, rows of pixels are sequentially selected by the vertical selection pulses φV [φV1, φV2, . . . φVn] from the vertical scanning circuit3, and pixel signals in the selected (scanned) row are outputted to the CDS/signal holding circuit5through the vertical signal lines11. The CDS/signal holding circuit5receives the signals of a row and holds the signals whose offset components peculiar to respective pixels (correspond to fixed-pattern noise components) are subtracted. Then, the horizontal switches are sequentially turned on by the horizontal scanning pulses φH [φH1, φH2, . . . φHn] from the horizontal scanning circuit4and pixel signals of a row held in the CDS/signal holding circuit5are sequentially read out to the output amplifier6through the horizontal signal line12. The signals are amplified in the output amplifier6to be outputted to an output terminal “t out” as analog signals.

SUMMARY OF THE INVENTION

The power consumption of the above MOS-type solid-state imaging device1is approximately a fifth part of the power consumption of the CCD solid-state imaging device. To mount the device on portable devices, it is necessary to further reduce the power consumption. There is a problem that, when the number of pixels increases and an output rate (that is, drive frequency of the horizontal scanning circuit) becomes high, the power consumption also increases.

Concerning the power consumption of the MOS-type solid-state imaging device, the power consumption in the pixel unit is one tenth or less as compared with the CCD pixels, therefore, it can be almost negligible. Even in digital parts (the serial interface8, the timing generator circuit7, the vertical scanning circuit3, the horizontal scanning circuit4and the like), the power consumption is relatively low, and is the highest at the output amplifier6which is the analog circuit. Particularly, as the number of pixels increases, the drive frequency increases, therefore, the frequency characteristic of the output amplifier6have to be increased accordingly. In order to increase the frequency characteristic in the analog circuit, it is necessary that bias current flows a lot, which causes further increase of power consumption. When the number of pixels increases and the output rate becomes high, there is a problem that random noise in the output circuit also increases.

In related arts, a bias current adjustment unit adjusting bias current with respect to the output amplifier is provided, thereby realizing low power consumption in the output amplifier.

It is important to use a sensor which can make transfer at high speed such as a column ADC-type (circuit performing A/D conversion by each column) image sensor for increasing speed as compared with a column CDS-type image sensor in related arts. Though horizontal transfer of the column ADC-type image sensor is performed at high speed as it is digital transfer, vertical transfer thereof is analog transfer, therefore, the speed is reduced by settling in the column ADC. In order to increase the speed of analog vertical transfer, it is necessary to increase the current amount flowing in vertical signal lines to control stabilizing time (settling time) of signals to the minimum.

However, to increase the current amount causes the increase of power consumption, in addition, as the whole power consumption increases, an imaging chip has heat, heat current is generated and enters into photodiodes in the sensor unit to cause the increase of noise current (dark current).

Thus, it is desirable to provide a solid-state imaging device and the imaging apparatus using the same which realizes speed-up as well as reduction of noise, while controlling power consumption lower than the related arts by controlling current in vertical signal lines according to drive modes and switching the settling time.

According to an embodiment of the invention, a solid-state imaging device includes a sensor unit in which plural pixels are arranged, a vertical scanning unit and a horizontal scanning unit scanning pixels in the sensor unit, column amplifier units provided at respective vertical signal lines corresponding to columns in the sensor unit and amplifying signal charges read out to the vertical signal lines, a bias current adjustment unit controlling current flowing in the vertical signal lines by changing bias current of the column amplifier units, a signal processing unit processing signal charges read out to the vertical signal lines and amplified at the column amplifier units into image signals to be outputted, an output unit to which signals outputted from the signal processing unit are supplied, a drive signal generation unit supplying drive signals to the vertical scanning unit, the horizontal scanning unit, the signal processing unit and the output unit, and an input unit supplying plural drive mode signals to the drive signal generation unit, in which current flowing in the vertical signal lines is controlled by changing bias current supplied from the bias current adjustment unit to the column amplifier units by drive signals outputted from the drive signal generation unit according to the plural drive mode signals.

According to an embodiment of the invention, an imaging apparatus includes a solid-state imaging device imaging a subject, imaging optical system guiding incident light from the subject to the solid-state imaging device, a signal processing unit processing output signals from the solid-state imaging device, in which the solid-state imaging device has a sensor unit in which plural pixels are arranged, a vertical scanning unit and a horizontal scanning unit scanning pixels in the sensor unit, column amplifier units provided at respective vertical signal lines corresponding to columns in the sensor unit and amplifying signal charges read out to the vertical signal lines, a bias current adjustment unit controlling current flowing in the vertical signal lines by changing bias current of the column amplifier units, a signal processing unit processing signal charges read out to the vertical signal lines and amplified at the column amplifier units into image signals to be outputted, an output unit to which signals outputted from the signal processing unit are supplied, a drive signal generation unit supplying drive signals to the vertical scanning unit, the horizontal scanning unit, the signal processing unit and the output unit and an input unit supplying plural drive mode signals to the drive signal generation unit, and in which current flowing in the vertical signal lines is controlled by changing bias current supplied from the bias current adjustment unit to the column amplifier units by drive signals outputted from the drive signal generation unit according to the plural drive mode signals.

In a solid-state imaging device and an imaging apparatus using the same according to the embodiments of the invention, it is configured that bias current in the column amplifier units provided at respective columns in the sensor unit is changed by the bias current adjustment unit according to operation modes, thereby controlling the current amount flowing in vertical signal lines of respective columns to switch the settling time, as a result, low power consumption and speed-up can be realized at the same time as well as noise reduction can be possible.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

Hereinafter, a solid-state imaging device according to a first embodiment of the invention will be explained with reference toFIG. 1. The solid-state imaging device according to embodiments of the invention is not limited to the embodiment explained below.

FIG. 1is a configuration diagram showing a solid-state imaging device, namely, a MOS-type solid-state imaging device according to the first embodiment of the invention.

A MOS-type solid-state imaging device21according to the embodiment of the invention includes a sensor unit22in which many unit pixels including photodiodes performing photoelectric conversion and MOS switch elements are arranged in a matrix state, a vertical scanning circuit23and a horizontal scanning circuit24which drive the sensor unit22, a column ADC unit (corresponds to a signal processing unit)25receiving pixel signals of one row outputted to respective vertical signal lines of the sensor unit22in parallel, a digital output unit26connected to the column ADC unit25, a timing generator circuit (corresponding to a drive signal generation unit)27generating pulses for operating respective units and a serial interface28, and further includes, a dividing circuit29which divides a clock to generate a clock signal for the timing generator circuit27based on instruction data inputted in the serial interface28and a bias current adjustment unit30controlling the current amount flowing in vertical signal lines33of respective columns based on a timing pulse signal outputted from the timing generator circuit27.

The serial interface28and the dividing circuit29form an input unit.

In the sensor unit22, vertical scanning lines32from the vertical scanning circuit23are commonly connected to pixels of each row and vertical scanning pulses φV [φV1, φV2, . . . φVn] are supplied to pixels of respective rows from the vertical scanning circuit23through the vertical scanning lines32. Further, vertical signal lines33are commonly connected to pixels of each column in the sensor unit22, and respective vertical signal lines33are connected to a horizontal signal line34through the column ADC unit25. The horizontal signal line34is connected to the input side of the digital output unit26. Horizontal switching elements are provided corresponding to respective pixel columns in the column ADC unit25, and horizontal scanning pulses φH [φH1, φH2, . . . φHn] are supplied to the horizontal switching elements from the horizontal scanning circuit24.

The column ADC unit25includes column amplifier units25aprovided to respective vertical signal lines33corresponding to columns of the sensor unit22, amplifying signal charges read out to the vertical signal lines33as well as controlling the current amount flowing in the vertical signal lines33of respective columns by bias current supplied from the bias current adjustment unit30according to operation modes, CDS (Correlated Double Sampling) units25bprovided to respective columns and performing noise removal by finding the difference between the reset level and the signal level of respective pixels, an AGC (Auto Gain Control) function and an analog/digital (A/D) conversion function, in which pixel signals converted into digital amounts in the column ADC unit25are transferred to the digital output unit26at high speed by the horizontal scanning circuit24to be outputted.

Serial data is inputted to the serial interface28from the outside. The serial data is data which prescribes drive modes of the sensor unit22which will be described later. To the serial interface28and the dividing circuit29, a synchronizing signal and a clock signal are inputted, for example, from the outside.

The timing generator circuit27is formed so as to generate timing pulses of plural drive modes corresponding to plural drive mode described later. Necessary pulses for operating respective units of the vertical scanning circuit23, the horizontal scanning circuit24, the column ADC unit25, the digital output unit26and the bias current adjustment unit30are supplied from the timing generator circuit27. The dividing circuit29is formed so as to divide a clock signal according to instructions from the serial interface unit28to be inputted in the timing generator circuit27. Instructions of the serial interface28are inputted to the dividing circuit29and the timing generator circuit27. The bias current adjustment unit30entirely changes bias current applied to the column amplifier units25aaccording to plural drive modes, thereby controlling current flowing in the vertical signal lines33of respective columns.

Next, the operation of the MOS-type solid-state imaging device21according to the embodiment will be explained.

Serial data according to drive modes of the sensor unit22is inputted into the serial interface28to perform mode selection. The data according to the drive mode is decoded in the serial interface28and inputted into the dividing circuit29and the timing generator circuit27. The dividing circuit29divides the clock signal inputted, for example, from the outside according to the instruction (instruction based on the selected drive mode) from the serial interface28and inputs the divided clock signal to the timing generator circuit27by synchronizing it with the synchronizing signal.

The timing generator circuit27receives the clock signal from the dividing circuit29and data from the serial interface28and generates timing pulses according to the selected drive mode to input them into respective units of the vertical scanning circuit23, the horizontal scanning circuit24, the column ADC circuit25, the digital output unit26and the bias current adjustment circuit30.

The bias current adjustment circuit30entirely switches bias current supplied to column amplifier units25aprovided at each vertical signal line33of the column ADC unit25according to the operation mode, thereby controlling current flowing in the vertical signal lines33of respective columns. The gain of the column amplifier units25amay be a positive gain or a negative gain, and in the case of the negative gain, for example, a source follower circuit in pixels is an example. In addition, switching of bias current with respect to the column amplifier units25ais performed during a reading period, namely, a horizontal blanking period in one horizontal period.

The clock signal divided according to the drive mode based on the instruction from the serial interface28is supplied from the timing generator circuit27to the bias current adjustment unit30. Particularly in the case of drive mode in which a drive frequency is high, bias current supplied from the bias current adjustment unit30to the column amplifier units25aof respective columns is switched to bias current having a value according to the drive mode in which the drive frequency is high. Accordingly, sufficient current flows in the vertical signal lines33and high speed transfer such as 240 fps can be realized.

Through large current is necessary at the time of high-speed transfer, large current is necessary only at the time of start of transfer. It is possible to switch bias current at the timing such that large current is applied during transfer, for example, for a half of the transfer time, and that half current thereof is applied for the rest of time, thereby realizing high-speed transfer and low power consumption at the same time.

In a low-speed drive mode, there is sufficient settling time, therefore, bias current to the column amplifier units25acan be switched to lower current by the bias current adjustment unit30in the same way, thereby reducing power consumption in the column amplifier units.

The sensor unit22is driven by the vertical scanning circuit23. That is, a row of pixels is selected by the vertical selection pulse φV selected according to the drive mode from the vertical scanning circuit23and pixel signals of the selected one row are outputted to the column ADC unit25through the vertical signal line33. In the column ADC unit25, correlated double sampling is performed at the CDS unit25b, receiving the signals of one row, and signals obtained by subtracting offset components peculiar to respective pixels (corresponding to fixed-pattern noise) are held. Then, the horizontal switching elements are sequentially turned on by the selected horizontal scanning pulse φH from the horizontal scanning circuit24, pixel signals of one row held in the column ADC unit25are A/D converted and read out by the digital output unit26through the horizontal signal line34. The digital output unit26converts image signals inputted in serial from the column ADC unit25into parallel signals to be outputted from the output terminal toutas digital signals.

The solid-state imaging device21shown in the above first embodiment includes column amplifier units25aprovided at respective columns and the bias current adjustment unit30adjusting bias current of the amplifier units25a, changing bias current of the column amplifier units25aaccording to plural drive modes by the bias current adjustment unit30, therefore, low power consumption and speed-up can be realized at the same time.

According to the first embodiment, as low power consumption can be realized, it is possible to prevent generation of heat current and to reduce dark current in the solid-state imaging device. Particularly, when the solid-state imaging device21of the embodiment is mounted on portable devices and the like, power consumption can be drastically reduced as well as random noise in the drive mode in which the clock frequency is low can be reduced. Since the random noise can be reduced, image quality in drive modes in the low drive frequency such as a thinning-out mode, a cutting mode, and a low-speed whole pixel readout mode, that is, so-called S/N ratio, dynamic range and the like can be improved.

Next, a specific example of the bias current adjustment unit adjusting bias current of the column amplifier units25aprovided at respective columns will be explained with reference toFIG. 2andFIG. 3.

A bias current adjustment unit301shown inFIG. 2is formed by applying a current mirror circuit. The bias current adjustment unit301includes first, second and third MOS transistors Q1, Q2and Q3, one main electrode of the first MOS transistor Q1is connected to a power supply Vdd through a resistance R which is a constant current source, respective gate electrodes of the first, second, and third MOS transistors Q1, Q2and Q3are commonly connected to one another, and the midpoint between the one main electrode of the first MOS transistor Q1and the resistance R is connected to gate electrodes of respective MOS transistor Q1, Q2and Q3. The other main electrode of the second MOS transistor Q2is connected in series to one main electrode of a MOS transistor Q4for a first switch, and the other main electrode of the third MOS transistor Q3is connected in series to one main electrode of a MOS transistor Q5for a second switch. The respective other main electrodes of the MOS transistors Q4, Q5for the first and second switches and the other main electrode of the first MOS transistor Q1are grounded, and one main electrodes of the second and third MOS transistors Q2, Q3are commonly connected to be connected to a bias current output terminal tB. In the example, a selection signal P1is supplied from the timing generator circuit27to a gate electrode of the MOS transistor Q4for the first switch, and a selection signal P2is supplied from the timing generator circuit27to a gate electrode of the MOS transistor Q5for the second switch. The respective selection signals P1, P2are formed by binary pulses having the high level and the low level, respectively.

The resistance R, the first MOS transistor Q1, the second MOS transistor Q2and the MOS transistor Q4for the first switch form a current mirror circuit. Also, the resistance R, the first MOS transistor Q1, the third MOS transistor Q3and the MOS transistor Q5for the second switch form a current mirror circuit.

In the bias current adjustment unit301, current is decided at the resistance R, and the current value is folded at the current mirror circuit to be outputted to the terminal tB as bias current. Four kinds of bias current including current “0” can be outputted by properly combining gate widths of the second and third MOS transistors Q2, Q3. For example, in the case that the gate width of the second MOS transistor Q2is made to be the same as the gate width of the first MOS transistor Q1, and the gate width of the third MOS transistor Q3is made to be double of the gate width of the first MOS transistor Q1, a unit of bias current flows when the MOS transistor Q4for the first switch is turned on, and double bias current flows when the MOS transistor Q4for the first switch is turned off and the MOS transistor Q5of the second switch is turned on, and triple bias current flows when the both MOS transistors Q4, Q5for switches are turned on. Four kinds of bias current can be applied including standby (a state when the both MOS transistors Q4, Q5for switches are off: bias current “0”).

The way of taking the gate width of the MOS transistors Q1, Q2and Q3has degree of freedom. According to such circuit configuration, bias current can be changed by properly inputting the selection signals P1, P2from the timing generator circuit27, and bias current of the column amplifier units25acan be switched. When adding a circuit shown by dashed lines inFIG. 2, bias current can be changed to eight kinds of current.

A bias current adjustment unit302shown inFIG. 3also applies a current mirror circuit. The bias current adjustment unit302includes a first n-channel MOS transistor Q11, a second n-channel MOS transistor Q12, further, a first p-channel MOS transistor Q13and a second p-channel MOS transistor Q14to be constant current sources. One main electrode of the first MOS transistor Q11is connected to a power supply VDD through the first and second p-channel MOS transistors Q13, Q14which are connected in parallel to each other, gate electrodes of the first and second MOS transistors Q11, Q12are commonly connected to each other, and the midpoint between one main electrode of the first MOS transistor Q11and the P-channel MOS transistors Q13, Q14is connected to gate electrodes of both n-channel MOS transistors Q11, Q12. The other main electrodes of the first and second n-channel MOS transistors Q11, Q12are grounded and one main electrode of the second n-channel MOS transistor Q12is connected to a bias current output terminal tB. In the example, a selection signal P1is supplied from the timing generator circuit27to the gate electrode of the first p-channel MOS transistor Q13and a selection signal P2is supplied from the timing generator circuit27to the gate electrode of the second p-channel MOS transistor Q14. The respective selection signal P1and P2are formed by binary pulses having the high level and the low level, respectively.

In the bias current adjustment unit302, current is decided at the p-channel MOS transistors Q13, Q14in which a threshold is properly adjusted, and the current value is folded at the current mirror circuit to be outputted at the terminal tB as bias current. Then, the gate widths of the first and second p-channel MOS transistors Q13, Q14are properly set, two kinds of selection signals P1, P2from the timing generator circuit27are selectively inputted to the p-channel MOS transistors Q13, Q14, thereby controlling current flowing in the p-channel MOS transistors Q13, Q14, as a result, current flowing in the second n-channel MOS transistor Q12will be 2×2=4 kinds, and four kinds of bias current including current “0” can be outputted.

Second Embodiment

FIG. 4is a configuration diagram showing a MOS-type solid-state imaging device according to a second embodiment of the invention.

In a solid-state imaging device41shown in the second embodiment, the same numerals and signs are put to components which are the same as the solid-state imaging device21of the first embodiment shown inFIG. 1and the explanation thereof will be omitted. The explanation will be made, focusing on points different fromFIG. 1.

The solid-state imaging device41shown in the second embodiment is different fromFIG. 1in a point that a bias current adjustment unit42is provided, which controls the current amount flowing in vertical signal lines33of respective columns separately based on a timing pulse signal from the timing pulse generator circuit27.

The bias current adjustment unit42includes column amplifier units42aprovided at respective vertical signal lines33of respective columns and amplifying signal charges read out to the vertical signal lines33, and bias current applied to the respective column amplifier units42ais adjusted separately by the bias current adjustment unit42which is switched according to a drive mode signal, thereby controlling the current amount flowing in the vertical signal lines33of respective columns.

The column ADC unit25includes a CDS (Correlated Double Sampling) function provided at respective columns and performing noise removal by finding difference between the reset level and the signal level of respective pixels, an AGC (Auto Gain Control) function and an analog/digital (A/D) conversion function, and pixel signals converted into digital amounts in the column ADC unit25are transferred to the digital output unit26by the horizontal scanning circuit24at high speed to be outputted.

The above solid-state imaging device41shown in the second embodiment differs from the first embodiment in the point that bias current applied to the respective column amplifier units42ais adjusted by the bias current adjustment unit42separately, thereby controlling current amounts flowing in the vertical signal lines33of respective columns, however, it is the same as the first embodiment in the point that the bias current of the column amplifier units25ais changed according to the drive mode signal. Therefore, the same operation and effect as the first embodiment can be obtained also in the solid-state imaging device41shown in the second embodiment.

Third Embodiment

Next, an example in which the solid-state imaging device shown in the embodiment is applied to an imaging apparatus such as a video camera or a camera built in a cellular phone which is capable of taking moving pictures will be explained with reference toFIG. 5.

InFIG. 5, an imaging apparatus50includes a solid-state imaging device51, an optical system52guiding incident light from a subject to the solid-state imaging device51, a signal processing unit53processing output signals from the solid-state imaging device51, a drive circuit54driving the solid-state imaging device51, a display unit55including a liquid crystal display device and the like displaying image data processed by the signal processing unit53and a recording unit56recording image data processed by the signal processing unit53in recording media.

In the imaging apparatus50, the solid-state imaging devices51shown in the respective embodiments are used as the solid-state imaging device51.

The drive circuit54supplies drive signals controlling transfer operation of the solid-state imaging device51and shutter operation of a shutter device (not shown) built in the solid-state imaging device51. Charge transfer of the solid-state imaging device51is performed by drive signals (timing signals) supplied from the drive circuit54. The signal processing unit53performs various signal processing. The image data to which signal processing was performed is stored in the storage media in the recording unit56and outputted to the display unit55to be displayed as images.

According to such imaging apparatus, low power consumption and speed-up can be realized at the same time by using the solid-state imaging device according to the above embodiments as well as generation of heat current can be prevented and dark current in the solid-state imaging device can be reduced because the low power consumption is realized, as a result, imaging pictures having high image quality can be obtained and the imaging apparatus of high image quality can be provided.