Current sensing and background calibration to match two resistor ladders

In one embodiment, a first resistor ladder includes a first voltage across the first resistor ladder. A second resistor ladder includes a second voltage across the second resistor ladder. A third resistor ladder includes a third voltage across the third resistor ladder. The calibrator receives the first voltage and third voltage and adjusts a current through the third resistor ladder to adjust the third voltage based on the received first voltage and third voltage. A buffer is configured to provide buffering for the third resistor ladder from the second resistor ladder. The third voltage of the third resistor ladder is stable even though the second voltage of the second resistor ladder is changing.

BACKGROUND

Particular embodiments generally relate to resistor ladders and more specifically to calibration of resistor ladders.

Analog circuit designs require matching of two or more resistor ladders. A user calculates the variations and matching parameters of a given process and also a layout of the physical resistors in a minimum area allowed by the calculation. However, often a large area requirement for the resistor ladders is required especially when matching between several ladders.

It is also difficult to match two ladders with different resistance values especially when the ratio between the two ladders is large. In one example, a unit resistor is created and other resistor ladders are built using different series or parallel combinations of the unit resistor. However, this approach is not area efficient due to the interface and contact portions of the unit resistor.

One way to overcome the above problems is to build one precision master resistor ladder and have the other resistor ladders be imprecise ladders that match the master ladder through calibration. Problems arise in the calibration when the resistor ladders are continuously disturbed by being part of a signal path or by dynamic events. For example, the calibration may be inaccurate when the resistor ladders are disturbed.

FIG. 1depicts a conventional system100. System100includes a first resistor ladder102aand a second resistor ladder102b. First resistor ladder102ais a master resistor ladder. Second resistor ladder102bis a slave resistor ladder. The master resistor ladder is a precise ladder and the slave resistance ladder is an imprecise ladder.

Second resistor ladder102bis matched with first resistor ladder102a. For example, the voltage across second resistor ladder102b, VB, is a fixed ratio of the voltage across first resistor ladder102a, VA.

A calibrator104is configured to calibrate the current through second resistor ladder102bto achieve the desired voltage ratio. Calibrator104senses the voltage VBacross second resistor ladder102band adjusts the current using a current source106such that VBis adjusted to the fixed ratio with respect to VA. However, when second resistor ladder102bis part of the signal path or is frequently subject to dynamic events, calibrator104has a hard time measuring the voltage of second resistor ladder102breliably. The calibration thus becomes inaccurate.

SUMMARY

Particular embodiments provide calibration of resistor ladders. In one embodiment, a first resistor ladder includes a first voltage across the first resistor ladder. A second resistor ladder includes a second voltage across the second resistor ladder. A third resistor ladder includes a third voltage across the third resistor ladder. The calibrator receives the first voltage and third voltage and adjusts a current through the third resistor ladder to adjust the second voltage based on the received first voltage and third voltage. A buffer is configured to provide buffering for the third resistor ladder from the second resistor ladder. The third voltage of the third resistor ladder is stable even though the second voltage of the second resistor ladder is changing.

In one embodiment, an apparatus is provided that comprises: a first resistor ladder including a first voltage across the first resistor ladder; a second resistor ladder including a second voltage across the second resistor ladder; a third resistor ladder including a third voltage across the third resistor ladder; a buffer configured to buffer the third resistor ladder from disturbances in the second resistor ladder; and a calibrator configured to receive the first voltage and the third voltage and adjust a current through the third resistor ladder to adjust the third voltage based on the received first voltage and the received third voltage, wherein the second voltage is calibrated to a voltage ratio with the first voltage by the current adjustment.

In one embodiment, the noise through the second resistor ladder due to an event is attenuated by the buffer.

In one embodiment, the second resistor ladder is in a signal path, wherein the third resistor ladder is buffered from disturbances resulting from the second resistor ladder being in the signal path.

In one embodiment, the buffer comprises a cascode device.

In one embodiment, a method is provided that comprises: receiving a first voltage across a first resistor ladder; receiving a third voltage across a third resistor ladder, wherein the third voltage being received is buffered from disturbances in a second resistor ladder; and adjusting a current through the third resistor ladder to adjust the third voltage to be a first voltage ratio of the first voltage to the third voltage, wherein the adjustment of the current adjusts a second voltage across the second resistor ladder to be a second voltage ratio of the first voltage to the second voltage.

In one embodiment, the current through the second resistor ladder is substantially quiescent.

In one embodiment, the current through the second resistor ladder is buffered from disturbances in the third resistor ladder.

DETAILED DESCRIPTION

An overview of an ADC architecture that uses the calibration is described first. Then, the calibration of the resistor ladders is described. It will be understood that the calibration may be used in other systems.

Overview of ADC Architecture

FIG. 2depicts an ADC architecture400according to one embodiment. In one embodiment, architecture400is used for ultra high-speed, medium-to-high resolution applications. Although these applications are described, architecture400may be used in other applications that require an analog-to-digital conversion. In one embodiment, architecture400is a two-step subranging ADC architecture.

Architecture400converts an analog input signal to a digital output signal. The analog input signal is received at a first track-and-hold stage (T/H)402a. Track-and-hold stage402ais configured to track the analog input signal for a part of a clock cycle, T, and store an input voltage for another part of the clock cycle. For example, the analog input signal may be tracked for T/2 and the input voltage is stored for another T/2. The stored input voltage is for a sample of the analog input signal.

A coarse ADC404receives the input voltage and performs a comparison of the input voltage to a plurality of coarse references received from a coarse digital-to-analog converter (DAC)406.

In one embodiment, coarse DAC406includes a coarse reference ladder408, a switch matrix410, and a buffer412. Coarse reference ladder408is separated from a fine reference ladder414through buffer412. The separation allows for independent optimization of coarse reference ladder408and fine reference ladder414, which will be described in more detail below.

Coarse reference ladder408may include a plurality of resistors and a plurality of taps. The plurality of taps provide the plurality of coarse references to coarse ADC404. The coarse references may be different reference voltage levels.

Coarse ADC404compares the input voltage to the coarse references to determine a coarse decision. The coarse decision may select a coarse reference for a subrange in which the input voltage resides. For example, coarse ADC404may choose a midpoint in between a subrange of voltages.FIG. 3shows a conceptual example of the subranges according to one embodiment. A plurality of subranges502a-502dare shown and a plurality of coarse references are provided. For example, the coarse references may be 1-5V. Coarse ADC2-404compares the input voltage to coarse references and selects which range of values in which the input voltage resides. For example, the input voltage may reside at a point506in subrange502c. Coarse ADC2-404then selects subrange502c. The voltage selected may be a midpoint508in subrange502c. By selecting the midpoint, a slight quantization error, Eqis introduced. As will be explained below, the fine references are used to refine the quantization error using the fine references.

Referring back toFIG. 2, the coarse decision is the result of comparisons between the input voltage and the coarse references. For example, comparators in coarse ADC404may compare the input voltage with the different coarse references. Each comparator outputs a logic output based upon the comparison. The value of the logic output is based on whether the coarse reference is higher or lower than the input voltage. For example, a comparator may output a value of 0 if the input voltage has a value that is lower than the coarse reference. Also, a comparator outputs a “1” value if the input voltage has a value higher than the coarse reference. A coarse encoder414receives the logic output from the comparators and determines a first digital code. The first digital code is a digital representation of the input voltage.

A switch in switch matrix410is closed such that a coarse reference for subrange3-502selected by coarse ADC404is sent to fine reference ladder414through buffer412. Buffer412separates coarse reference ladder408from fine reference ladder414.

The coarse reference is sent to fine reference ladder414. Fine reference ladder414uses the coarse reference to generate a plurality of fine references for a fine ADC416. The plurality of fine references may be within the subrange selected by coarse ADC404. For example, referring toFIG. 3, a plurality of fine references are provided in between 3V-4V. A fine reference corresponding to the input voltage is then determined.

Fine ADC416receives the plurality of fine references and an input voltage from second track-and-hold stage402b. For example, second track-and-hold stage402btracks the input voltage starting at a T/2 period after the tracking period for first track-and-hold stage402aand stores the input voltage starting at a T/2 period after the storing period for first track-and-hold stage402a. By using two track-and-hold stages402aand402b, the fine ADC decision may be extended an extra T/2 period. This allows an extended settling time for coarse reference ladder408and fine reference ladder414. This concept will be described in more detail below.

Referring back toFIG. 2, fine ADC416compares the fine references to the input voltage. In one embodiment, comparators of fine ADC416output logic outputs of comparisons of the fine references and the input voltage. For example, a 0 or 1 may be output depending on the comparison. A comparator may output a value of 0 if the input voltage has a value that is lower than the reference. Also, a comparator outputs a “1” value if the input voltage has a value higher than the reference.

A fine encoder418receives the logic outputs of the comparison and determines a second digital code. The second digital code is a digital representation of the input voltage.

Digital error correction logic420receives the first digital code from coarse encoder414and the second digital code from fine encoder418. The first digital code may be received through a flip-flop422. Flip-flop422may delay the first digital code because of the decision by fine ADC416being delayed by a T/2 period.

Digital error correction logic420may include an adder. The adder may add the first digital code and the second digital code to produce a digital output. Additionally, digital error correction logic420may weight and error correct the first digital code and the second digital code. In one embodiment, the first digital code may be used to determine the most significant bits (MSB) of the digital output. The second digital code may be used to refine the least significant bits (LSB) of the digital output. The digital output may be a binary code or any other type of code that represents the sample of the analog input in the digital domain.

Coarse reference ladder408and the use of additional track and hold stages402aand402bin architecture400will now be described in more detail. After which, the calibration of fine reference ladder414and reference precharging will be described.

Coarse Reference Ladder

Particular embodiments provide two reference ladders for coarse reference ladder408. Although two coarse reference ladders are described, any number of coarse reference ladders may be used.FIG. 4depicts another example of the subranging ADC reference ladders according to one embodiment. Coarse reference ladder2-408includes a coarse ADC reference ladder602and a coarse DAC ladder604. By using two separate ladders, coarse DAC ladder604may be free of loading from comparators in coarse ADC2-404. Additional bandwidth may be gained by coarse DAC ladder608.

In addition to separating coarse reference ladder2-408into coarse ADC reference ladder602and coarse DAC ladder604, fine reference ladder2-414is separated from coarse reference ladder2-408through buffer2-412. This allows separate implementation and optimization of coarse ADC reference ladder602, coarse DAC ladder604, and fine reference ladder2-414.

Coarse ADC reference ladder602is static. Coarse ADC reference ladder602provides a number of reference voltages (e.g., the coarse references) between the voltages Vrtopand Vrbot. The reference voltages provided to coarse ADC2-404do not change making coarse ADC reference ladder602static.

Coarse DAC ladder604is dynamic. Each time coarse ADC2-404selects a different subrange, a different coarse reference is provided to fine ADC2-416. By using two separate ladders, coarse DAC ladder604can settle faster from a previous voltage level to the voltage level selected as the subrange. For example, coarse DAC ladder604is free of loading from comparators in coarse ADC2-404, which allows coarse DAC ladder604to settle faster. Additionally, coarse DAC ladder604may be implemented with a low impedance, high speed design in contrast to coarse ADC reference ladder602, which may be implemented in a high impedance, slow speed design. Coarse ADC reference ladder602is static and may not need to be a high speed design. By using a high impedance design, coarse ADC reference ladder602consumes less power. However, the high speed design allows coarse DAC ladder604to settle faster to set up the fine references based on the subrange selected by coarse ADC2-404.

Coarse DAC ladder604is also separated from fine reference ladder2-414by buffer2-412. The use of buffer2-412instead of coarse DAC ladder604to drive fine reference ladder2-414prevents a large loading from fine ADC2-416on coarse DAC ladder604. For example, loading from the comparators found in fine ADC2-416is prevented. This improves settling speed and slew rate of coarse DAC ladder604.

Fine reference ladder2-414is dynamic because different fine references are being selected based on the subrange selected by coarse ADC2-404. When different subranges are selected, the fine references are at different voltage levels and this causes shifts in voltage at fine reference ladder2-414. However, because fine reference ladder2-414is separated from coarse DAC ladder604by buffer2-412, coarse DAC ladder604is not disturbed by the change in voltage levels at fine reference ladder2-414.

Fine reference ladder2-414may also be floating in that there may not need to be a fixed resistance ratio between fine reference segments and coarse reference segments. A reference segment may be a unit resistor between taps of coarse reference ladder2-408or fine reference ladder2-414. Coarse reference ladder2-408or fine reference ladder2-414may each include multiple unit resistors that divide the ladder into the different voltage subranges. The unit resistors of floating fine reference segments may be implemented in different orientations and sizes from coarse reference ladder2-408. Calibration is used to match unit resistors of fine reference ladder4-414to coarse reference ladder4-408, which will be described below. Conventionally, a fixed resistance ratio between coarse reference ladder2-408and fine reference ladder2-414lead to ultra low resistance segments in a high-speed design if coarse reference ladder2-408uses low resistance segments. The very low resistance values may lead to parasitic effects. Also, physical implementation of low resistance segments may require large areas and have other process parasitics (e.g., interface and contacts resistance). Using floating fine references avoids these problems as low impedance resistors may be used but very small resistor segments can be avoided.

Fine reference ladder2-408may be floating, but the voltage of fine reference ladder2-414is a fixed ratio of the voltage for coarse reference ladder2-408. A calibration is used to ensure that the voltage ratio is fixed between fine reference ladder2-414and coarse reference ladder2-414. Accordingly, very small resistor segments that are used in coarse DAC ladder604do not need to be used in fine reference ladder2-414. More details of the calibration of fine reference ladder2-414will be described below.

Example Implementation of ADC Architecture Using Multiple Track and Hold Stages

FIG. 5depicts a more detailed example of ADC architecture2-400according to one embodiment. A first track-and-hold stage2-402aincludes an amplifier702a, a switch704a, and a capacitor706a. Although this implementation of track-and-hold stage2-402ais described, other implementations may be appreciated. Capacitor706ais used to store the input voltage. Switch704ais toggled between the track stage and the hold stage. The switch may be closed to charge capacitor706aand then opened when the voltage is stored.

A second track-and-hold stage includes an amplifier702b, switch704b, and capacitor706b. Amplifier702bis gain matched with amplifier702c. The matching ensures that the input voltage that is being input into coarse ADC2-404is matched with the voltage being tracked and stored by track-and-hold stage2-402b.

Coarse DAC2-406includes coarse ADC reference ladder4-602and coarse DAC ladder4-604. Coarse DAC4-406and coarse DAC ladder6-604each include a plurality of unit resistors. 31 coarse taps of coarse ADC reference ladder6-602in between the unit resistors are provided to coarse ADC4-404. However, any number of coarse taps may be used. In this case, architecture400may be a 7-bit resolution ADC.

Coarse ADC (CADC)2-404receives a clocking signal, strobec. At each clock cycle, coarse ADC2-404makes a coarse decision. For example, when a coarse reference is selected by coarse ADC2-404, coarse encoder (CENC)2-426provides a control signal to switches708included in switch matrix2-410to close one of the switches corresponding to the coarse reference selected. In one embodiment, a 32-bit signal is sent to open or close switches708.

The selected coarse reference is sent through a buffer702dfrom coarse DAC ladder6-604. A buffer702eis gain matched with buffer702d. This ensures that the input voltage into fine ADC2-416from buffer702eis gain matched with the reference selected by coarse ADC2-404.

A plurality of fine taps and a plurality of fine switches712are included in fine reference ladder2-414. In one example, based on the signal received, different switches in fine reference ladder2-414are closed to send31fine references to fine ADC2-416. Fine ADC2-416may also receive the input voltage from buffer702e.

Fine ADC (FADC)2-416makes a fine decision at each clock cycle of a clocking signal, strobef. For example, fine ADC2-416outputs logic outputs from comparisons of the input voltage and the fine references. Fine encoder2-418uses the logic outputs to determine a second digital code. Digital correction logic2-420receives the second digital code and the first digital code through a flip-flop2-422. The first digital code may be used to determine the 5 most significant bits for the digital output and the second digital code may be used to refine the 5 least significant bits of the first digital code. For example, digital correction logic420combines and error corrects the first digital code and second digital code into a 7-bit digital output.

FIG. 6depicts a timing diagram for architecture2-400described inFIG. 5according to one embodiment. Because two track-and-hold stages2-404aand2-404bare used, additional time for reference settling is provided. Conventionally, the coarse decision, fine reference bit encoding, and fine reference settling are all are done in half of a clock cycle T/2. However, in particular embodiments, this total time is extended by another half clock period ˜T/2 to be approximately a full clock period before fine ADC2-416needs to start making a comparison.

At802and804, the signals for first track-and-hold stage2-404aand second track-and-hold stage2-402bare shown. First track-and-hold stage2-404atracks and holds a sample for a clock period, T, and then second track-and-hold stage2-402btracks and holds the same sample for another clock period, T. For example, first track-and-hold stage2-402atracks and holds a new sample S1and then second track-and-hold stage2-402btracks and holds the new sample. While first track and hold stage2-402ais tracking the new sample S1, second track and hold stage2-402bis holding a current sample S0. The delay in tracking and holding between first track-and-hold stage2-402aand second track-and-hold stage2-402bis approximately T/2.

At806,808, and810, the signals for coarse ADC2-404, coarse DAC2-406, and fine ADC2-416are shown, respectively. Coarse ADC2-404makes a coarse decision at812for the sample S1. The fine references need to be set up after the coarse decision is made. That is, coarse DAC reference ladder4-604settles. Additionally, a precharge of the output of coarse DAC ladder4-604is performed at814. A time period shown at816shows the time taken to make the coarse decision.

Fine ADC2-416then makes a fine decision for the sample S1at818. Thus, instead of determining the first digital code and the second digital code, respectively, within consecutive T/2 periods, the fine decision time is extended to another T/2 period. That is, the coarse decision determination starts in a first T/2 period, a second T/2 period passes, and the fine decision determination is started after the second T/2 period. As shown at820, fine reference ladder2-414settles and makes the fine decision in a second time period. Fine ADC2-416has approximately a full clock period before fine ADC2-416has to start a comparison to determine the fine decision after the coarse decision determination starts. This allows the ADC conversion rate to be higher.

Architecture2-400is described in co-pending U.S. patent application Ser. No. 12/684,735 entitled “Two-Step Subranging ADC Architecture”, filed concurrently, the contents of which is incorporated herein in its entirety for all purposes.

Calibration of Fine Reference Ladder

FIG. 7depicts an example of calibration of reference ladders according to one embodiment. The calibration is described with respect to coarse reference ladder2-408and fine reference ladder2-414; however, it will be understood that the calibration described herein may be used with respect to other designs. For example, other designs that require multiple reference ladders may use the calibration described. Also, although reference ladders that provide references are discussed, the calibration may be used on any resistor ladders.

In one embodiment, a master reference ladder900is part of coarse reference ladder2-408. For example, master reference ladder may be a reference segment (unit resistor) that is selected as the subrange by coarse ADC2-404. Master reference ladder900is a precise ladder. For example, master reference ladder900is built using larger valued unit resistors, RA, where a voltage, VA, is stable across the unit resistor RA.

Fine reference ladder2-414includes a first fine reference ladder902and a second fine reference ladder904. Second fine reference ladder904may be a separate part of or included in fine reference ladder2-414. Second fine reference ladder904includes a unit resistor, RCand first fine reference ladder902includes a unit resistor, RB. Unit resistor RBincludes one or more unit resistors RC.

Second fine reference ladder904is separated from first fine reference ladder902using a buffer component906. For example, buffer component906may be one or more cascode devices. Buffer906attenuates noise from a signal path that is from coarse reference ladder2-408to first fine reference ladder902. Because first fine reference ladder902is in the signal path, it may produce noise. Buffer906provides a high-impedance shielding from the signal path that may filter or attenuate the noise from first fine reference ladder902.

Dynamic events occur at first fine reference ladder902that may cause the noise. For example, the voltage VBmay be dynamically changing. In one example, as different subranges are selected in fine reference ladder2-414, different voltage levels are across first fine reference ladder902. In contrast, the voltage VCis not changing and second reference ladder904is quiet compared to first reference ladder902. Because of the shielding from buffer906, the current through second fine reference ladder904is also almost quiescent and is isolated from dynamic events at first fine reference ladder902because any noise from the events is absorbed by buffer906.

A calibrator908performs a calibration of voltages across second fine reference ladder904and master reference ladder900. The quiet voltage across second fine reference ladder904can also be used to calibrate the voltage across first fine reference ladder902. Using a quiet voltage instead of a noisy voltage provides a more accurate calibration. In one embodiment, calibrator908uses a low-offset, low speed calibration loop in the background to perform the calibration.

Calibrator908senses the voltage VCfrom second fine reference ladder904at a sense port910. Also, calibrator908senses the voltage across the whole or a segment of first reference ladder2-408at a reference port912. The voltage VAis a multiple k1of VC, where k1is a constant. Calibrator908adjusts the current to adjust VCto be multiple k1of VA. For example, the current may be adjusted using a current source910.

First fine reference ladder902and second fine reference ladder904are matched together using a fixed ratio. For example, first reference ladder902is built using units of second fine reference ladder904, or vice versa. If a unit resistor, RC, is used in second fine reference ladder904, first fine reference ladder902is built using multiple unit resistors of RC.

By using multiple units of RC, the voltage VBmay be a fixed ratio of VA. For example, the voltage VCis:
VC=k1VA
If first fine reference ladder902and second fine reference ladder904having good matching, then:
VB=k2VC=k2k1VA=k3VA
Thus, VBis a fixed ratio of VA, where k1, k2, and k3are constants.

Accordingly, first fine reference ladder902may be matched to coarse reference ladder2-408through the calibration. First fine reference ladder902and second fine reference ladder904may be implemented using different orientation and size resistors from coarse reference ladder2-408. Also, matching is kept over all corners and long term drifts using background calibration without disturbing the signal path or having calibration affected by the signal path.

FIG. 8shows a more detailed example of architecture2-400according to one embodiment. As shown, coarse DAC ladder4-604includes a plurality of unit resistors RA. Second fine reference ladder7-904includes a unit resistor RCand first fine reference ladder7-902includes a plurality of unit resistors RC. As discussed above, coarse ADC2-404receives an input voltage and selects a coarse reference. A subrange3-502in coarse DAC ladder4-604is selected to send the coarse reference to fine reference ladder2-414through buffer5-702d. Buffer component7-906is coupled to a circuit such that it attenuates noise from first fine reference ladder9-902. A current based on a voltage level of the coarse reference is sent to buffer7-702. The voltage VAis a voltage drop across a unit resistor of coarse DAC ladder6-604. The voltage VBis matched to a fixed ratio of the selected voltage VAusing the calibration.

The voltage VAis sent to calibrator7-908. Calibrator7-908also senses the voltage VCacross second fine reference ladder7-904. Calibrator7-908calibrates the current across fine reference ladder2-414using current source7-910. As discussed above, the voltage VBis calibrated to a multiple VA.

FIG. 9depicts a simplified flowchart1100of a method for calibrating reference ladders according to one embodiment. At1102, calibrator7-908receives a first voltage across master reference ladder7-900. At1104, calibrator7-908receives a second voltage across second fine reference ladder7-904. The second voltage being received is buffered from disturbances in a third reference ladder.

At1106, calibrator7-908adjusts a current through second fine reference ladder7-904to adjust the second voltage to be a first voltage ratio with the first voltage. The adjustment of the current adjusts a third voltage across first fine reference ladder7-902to be a second voltage ratio of the first voltage to the third voltage.

Reference Precharge

Referring back toFIG. 2, in one embodiment, a pre-charge of the voltage level at the output of switch matrix410is provided. The voltage level is pre-charged to a level of the input voltage. This allows the movement of the voltage at the output of switch matrix410to be performed more quickly. For example, the previous voltage level at the output of switch matrix410may be the voltage of the last analog input sample. The voltage level needs to be moved from the previous voltage level to the coarse reference selected by coarse ADC404. For example, the coarse reference selected by coarse ADC404is the input voltage plus a quantization error Eq. The quantization error Eqis the error from the closest digital code that approximates the input voltage.

A time period is taken where coarse ADC404is making the coarse decision. During this time period, the voltage level at the output of switch matrix410may be pre-charged to the input voltage (Vin). When the coarse decision is made, the voltage only needs to be changed to Vin+Eq. For example, the selected coarse reference is a voltage that is for a subrange that includes input voltage. Thus, if it is known the output of switch matrix410will be around Vin+Eq, the output of switch matrix410may be pre-charged to the input voltage V. The adjusting of the input voltage Vinmay be performed faster because adjusting an Eqamount is a much smaller adjustment than from the previous sample's voltage level.

As shown inFIG. 4, a switch424is provided to allow the precharge of the output of switch matrix4-410. Switch424may be closed to precharge the output of switch matrix410while coarse ADC404is making the coarse decision. When the coarse decision is made, switch424is opened to allow the output of switch matrix410to settle to Vin+Eq. In this case, a switch in switch matrix410is closed and the coarse reference is sent to buffer4-412.

FIG. 5also shows the precharge according to one embodiment. As shown, switch2-424is used to precharge output lines of coarse DAC4-604. When coarse ADC is making the coarse decision, switch2-424may be closed and switches708may be open. This allows input lines710to be precharged to the input voltage Vin. In one embodiment, all input lines710are precharged. Thus, when the coarse reference is selected, the selected input line710is precharged. When the coarse decision is made, a switch708is closed to send the coarse reference to fine reference ladder2-414. Also, switch2-424is opened to allow the selected input line710to settle to Vin+Eq.

FIG. 10depicts a waveform showing the pre-charge of an output of switch matrix2-410according to one embodiment. At1202, the voltage at the output of switch matrix2-410is V1. This is the voltage of the previous input voltage sample. At1204, coarse ADC2-404is strobed. At this point, coarse ADC2-404may start to make a coarse decision. For example, at1206, coarse ADC2-404performs a comparison of the input voltage and the plurality of coarse references. At1208, the first digital code is determined based on the comparison. The first digital code is used to select a switch in switch matrix2-410.

The output of switch matrix2-410is pre-charged during a period at1206. When a switch is selected, instead of the voltage at the output of switch matrix2-410being at V1, the voltage is substantially around Vin. The voltage then needs to settle at the coarse reference of the input voltage Vinplus the coarse quantization error Eq.

The use of the pre-charge is described in more detail in co-pending U.S. patent application Ser. No. 12/684,760 entitled “Reference Pre-Charging for Two-Step Subranging ADC Architecture”, filed on Jan. 8, 2010, the contents of which is incorporated herein in its entirety for all purposes.

Method Using Particular Embodiments

FIG. 11depicts a simplified flowchart1300of a method for converting an analog input signal to a digital output signal according to one embodiment. At1302, first track and hold stage2-402atracks and stores an input voltage for a sample of an analog input signal. At1304, coarse reference ladder2-408provides a plurality of coarse references. In one embodiment, coarse reference ladder2-408includes first coarse ADC reference ladder4-602and second coarse reference ladder4-604.

At1306, coarse ADC2-404receives the input voltage from first track and hold stage2-402aand the plurality of coarse references. At1308, coarse ADC2-404performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output based on the first comparison. At1310, switch matrix2-410closes a switch corresponding to a coarse reference based on the coarse output. An input line has been precharged to the input voltage.

At1312, second track and hold stage402btracks and stores the input voltage. At1314, fine reference ladder2-414receives the coarse reference from the coarse reference ladder and provides a plurality of fine references. The plurality of fine references are determined based on the coarse reference. At1316, fine ADC2-416receives the input voltage from second track and hold stage2-402band the plurality of fine references. At1318, fine ADC2-416performs a second comparison of the input voltage and the plurality of fine references. At1320, fine ADC2-416outputs a fine output based on the second comparison. At1322, a digital output is output for the sample of the analog input signal based on the coarse output and the fine output.

The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the invention as defined by the claims.