Transmitter and control method for transmitting and calibrating a phase signal and an amplitude signal

A transmitter for transmitting and calibrating a phase signal and an amplitude signal. The transmitter comprises a phase modulation path, an amplitude modulation path, and a control unit. The phase modulation path transmits the phase signal. The amplitude modulation path transmits the amplitude signal. The control unit delays the signal on at least one of the phase modulation path and the amplitude modulation.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a transmitter and a control method, and more particularly to a transmitter and a control method for transmitting and calibrating a phase signal and an amplitude signal.

2. Description of the Related Art

FIG. 1is a schematic diagram of a conventional transmitter. The conventional transmitter100comprises mixers110,120, a local oscillator (LO)130, an adder140, a power amplifier150, a surface acoustic wave (SAW)160, and an antenna170. The mixer110mixes I digital baseband data SIwith a first carrier provided by the LO130. The mixer120mixes Q digital baseband data SQwith a second carrier provided by the LO130. The phase difference of the first carrier and the second carrier is 90°. The adder140adds the mixed signals. The power amplifier150amplifies the output signal of the adder140. The SAW160processes the amplified signal and transmits the processed result via the antenna170.

BRIEF SUMMARY OF THE INVENTION

Transmitters are provided. An exemplary embodiment of a transmitter, which transmits and calibrates a phase signal and an amplitude signal, comprises a phase modulation path, an amplitude modulation path, and a control unit. The phase modulation path transmits the phase signal. The amplitude modulation path transmits the amplitude signal. The control unit delays the signal on at least one of the phase modulation path and the amplitude modulation path.

Another exemplary embodiment of a transmitter comprises a first filter, a second filter, and a control unit. The first filter generates a phase signal according to a first signal. The second filter generates an amplitude signal according to a second signal. The control unit delays at least one of the first and the second signals.

A control method for a transmitter is provided. An exemplary embodiment of a control method for transmitting and calibrating a phase signal and an amplitude signal is described in the following. A phase modulation path is provided for transmitting the phase signal. An amplitude modulation path is provided for transmitting the amplitude signal. The signal on at least one of the phase modulation path and the amplitude modulation path is delayed.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2is a schematic diagram of an exemplary embodiment of a polar transmitter. The transmitter200is capable of transmitting and calibrating a phase signal φ(t) and an amplitude signal A(t). In this embodiment, the transmitter200comprises a phase modulation path210, an amplitude modulation path220, and a control unit230. The phase modulation path210transmits the phase signal φ(t). The amplitude modulation path220transmits the amplitude signal A(t). The control unit230delays the signal on at least one of the phase modulation path210and the amplitude modulation path220.

The transmitter200further comprises a calibration unit240and a digital modulator250. In a calibration mode, the calibration unit240provides a calibration signal SD1to the phase modulation path210and provides a calibration signal SD2to the amplitude modulation path220. In this embodiment, the calibration signal SD1is the same as the calibration signal SD2.

Different delays may be introduced on the phase modulation path210and the amplitude modulation path220, resulting in delay mismatch between the output signals. In the calibration mode, the control unit230is utilized to detect the difference of delay between the calibration signals SD1and SD2that have passed through the two paths210and220. In one embodiment, the control unit230adjusts a delay factor according to the difference between the calibration signals SD1and SD2such that the signal on at least one of the phase modulation path210and the amplitude modulation path220is delayed. Since delay on at least one of the phase modulation path210and the amplitude modulation path220is compensated, the signals on the phase modulation path210and the amplitude modulation path220are synchronous. When the calibration signals SD1and SD2are synchronous, the control unit230stops detecting the difference between the calibration signals SD1and SD2and maintains the delay factor.

In a normal mode, the digital modulator250converts I digital baseband data251and Q digital baseband data252into the phase signal φ(t) and the amplitude signal A(t). The phase modulation path210transmits the phase signal φ(t). The amplitude modulation path220transmits the amplitude signal A(t). Since the delay factor of the control unit230is adjusted, the phase signal φ(t) and the amplitude signal A(t) can simultaneously arrive to a combiner260in the normal mode. The combiner260combines the phase signal φ(t) and the amplitude signal A(t) to generate a radio frequency (RF) signal SRF.

The control unit230comprises a delay module231and a detection module232. In the calibration mode, the detection module232detects the difference of delays between the signals on the phase modulation path210and the amplitude modulation path220and generates an adjustment signal SADJaccording to the detection result. When the signals on the phase modulation path210and the amplitude modulation path220are synchronous, the detection module232stops detecting the difference and maintains the adjustment signal SADJ. The delay module231delays the signal on at least one of the phase modulation path210and the amplitude modulation path220according to the adjustment signal SADJ. In this embodiment, the delay module231delays the signal on the amplitude modulation path220according to the adjustment signal SADJ.

Generally, delay is easily introduced by a filter. In this embodiment, the detection module232detects the output signal Vtof a filter (not shown) disposed on the phase modulation path210and the output signal VLof a filter (such as222) disposed on the amplitude modulation path220.

FIG. 3Ais a schematic diagram of an exemplary embodiment of the detection module. The detection module232comprises differential generators311,312, comparators321,322, and a flip-flop331. The differential generator311transmits the output signal VLinto differential signals VL+and VL−. The differential generator312transmits the output signal Vtinto differential signals Vt+and Vt−. The differential signals VL+and VL−refer to a first differential pair. The differential signals Vt+and Vt−refer to a second differential pair. The comparator321compares the differential signals Vt+and Vt−and transmits the compared result to the flip-flop331. The comparator322compares the differential signals VL+and VL−and transmits the compared result to the flip-flop331. The flip-flop331generates the adjustment signal SADJaccording to the compared results.

In this embodiment, the flip-flop331is a D-type flip-flop. The output signal of the comparator321is transmitted to the input terminal D of flip-flop331. The output signal of the comparator322is transmitted to the clock terminal CLK of flip-flop331. When the output signal of the comparator322is changed from a low level to a high level, the adjustment signal SADJfollows the output signal of the comparator321.

FIG. 3Bis a waveform diagram of an exemplary embodiment of the output signals of the comparators321and322. The label PM shown inFIG. 3Brepresents the output signal of the comparator321and the label AM represents the output signal of the comparator322. When the output signal of the comparator322is changed from a low level to a high level, since the output signal of the comparator321is at a high level, the output signal (such as adjustment signal SADJ) of flip-flop331is at a high level. Referring toFIG. 3C, when the output signal of the comparator322is changed from the low level to the high level, since the output signal of the comparator321is at a low level, the output signal of flip-flop331is at a low level.

FIG. 3Dis a schematic diagram of another exemplary embodiment of the detection module. The detection module232comprises voltage generators313and314, comparators321′ and322′, and a flip-flop331′. The voltage generator313receives the output signal Vtand generates a divided signal

12⁢Vt.
The comparator321′ compares the output signal Vtand a divided signal

12⁢Vt.
The divided signal

12⁢Vt
is served as a threshold voltage such that comparator321′ converts the output signal Vtfrom a sine wave to a rectangular wave. The voltage generator314receives the output signal VLand generates the divided signal

12⁢VL.
The comparator322′ compares the output signal VLand the divided signal

12⁢VL.
The divided signal

12⁢VL
is served as a threshold voltage such that comparator322′ converts the output signal VLfrom a sine wave to a rectangular wave. The flip-flop331generates the adjustment signal SADJaccording to the compared results of the comparators321′ and322′.

In this embodiment, the voltage generator313comprises a switch SW6, a capacitor C1, and resistors R1and R2, but is not limited. The switch SW6is controlled by a control signal SC1such that the capacitor C1receives the output signal Vtor the capacitor C1is connected to the resistors R1and R2in parallel. First, the output signal Vtis transmitted to the capacitor C1. Then, the capacitor C1is connected to the resistors R1and R2. Since the resistors R1and R2are connected to act as a voltage divider, the divided signal

Similarly, the voltage generator314comprises a switch SW7, a capacitor C2, and resistors R3and R4, but is not limited. The switch SW7is controlled by a control signal SC2such that the capacitor C2receives the output signal VLor the capacitor C2is connected to the resistors R3and R4in parallel. First, the output signal VLis transmitted to the capacitor C2. Then, the capacitor C2is connected to the resistors R3and R4. Since the resistors R3and R4are connected to act as a voltage divider, the divided signal

Referring toFIG. 2, in the calibration mode, the phase modulation path210refers to the path from the compensation filter2112to the SDM2121and the PLL2122. In the normal mode, the phase modulation path210can further include the differentiator2111. In this embodiment, the differentiator2111and the compensation filter2112are included in a process unit211. The process unit211can enhance certain high frequency portion of the signal on the phase modulation path210by the compensation filter2122. In the normal mode, the differentiator2111differentiates the phase signal φ(t) and the compensation filter2112enhances certain high frequency portion of the signal on the phase modulation path210. In the calibration mode, the compensation filter2112enhances certain high frequency portion of the calibration signal SD1. In some embodiments, the compensation filter2112can be omitted.

In this embodiment, the fractional-N PLL212comprises a sigma-delta modulator (SDM)2121and a phase-locked loop (PLL)2122. The SDM2121modulates the output signal of the process unit211to generate a modulated signal SMOD. The PLL2122operates according to the modulated signal SMOD.

FIG. 4is a schematic diagram of an exemplary embodiment of a PLL. The PLL2122comprises a phase-frequency detector (PFD)411, a charge pump (CP)412, a low pass filter (LPF)413, a voltage control oscillator (VCO)414, and a frequency divider (FD)415. The PFD411detects the phase difference between a reference frequency FREFand a feedback frequency FFB2. The CP412transforms the phase difference into a pump current ICP. The LPF413transforms the pump current ICPinto the output signal Vt. The VCO414generates a feedback frequency FFB1according to the output signal Vt. The FD415divides the feedback frequency FFB1according to the modulated signal SMODto generate the feedback frequency FFB2. The detection module232detects the output signal Vtof the LPF413to obtain the amount of delay of phase modulation path.

Referring toFIG. 2, the amplitude modulation path220comprises a digital-to analog converter (DAC)221and a filter222. The DAC221transforms the signal on the amplitude modulation path220, and then the signal is filtered by the filter222. In the calibration mode, the DAC221transforms the calibration signal SD1and the filter222filters the transformed calibration signal to generate the output voltage VL. In the normal mode, the DAC221transforms the amplitude signal and the filter222filters the transformed amplitude signal.

Referring toFIG. 2, in one embodiment, the transmitter200can have switches SW1˜SW5. In the calibration mode, the switches SW1and SW2switch to the calibration unit240such that the phase modulation path210receives the calibration signal SD1and the amplitude modulation path220receives the calibration signal SD2. In this mode, the switch SW3switches to the detection module232such that the output voltage VLis transmitted to the detection module232. The SW4is turned off and the SW5is turned on such that the output voltage Vtis transmitted to the detection module232.

In the normal mode, the switches SW1and SW2switch to the digital modulator250such that the phase modulation path210and the amplitude modulation path220respectively receive the phase signal φ(t) and the amplitude signal A(t). At this time, the switch SW3switches to the combiner260. The SW4is turned on and the SW5is turned off. Thus, the combiner260receives and combines the signals on the phase modulation path210and the amplitude modulation path220to generate the RF signal SRF.

FIGS. 5˜7are schematic diagrams of other exemplary embodiments of the transmitter.FIGS. 5˜7are similar toFIG. 1except for the position of the delay module231. Referring toFIG. 5, the delay module231is coupled between the DAC221and the filter222. Referring toFIG. 6, the delay module231is coupled between the differentiator2111and the compensation filter2112. Referring toFIG. 7, the delay module231is coupled between the process unit211and the fractional-N PLL212.

FIG. 8is a flowchart of an exemplary embodiment of a control method. The control method is utilized in a transmitter to transmit and calibrate a phase signal and an amplitude signal. First, a phase modulation path is provided to transmit the phase signal (step S810). An amplitude modulation path is provided to transmit the amplitude signal (step S820). In a calibration mode, a calibration unit provides a first calibration signal and a second calibration signal to the phase modulation path and the amplitude modulation path, respectively.

The signal on at least one of the phase modulation path and the amplitude modulation path is delayed (step S830). The signals on the phase modulation path and the amplitude modulation path may be delayed by the elements of the phase modulation path and the amplitude modulation path. When the phase modulation path and the amplitude modulation path respectively receive a first calibration signal and a second calibration signal, the first calibration signal maybe slower or faster than the second calibration signal. For example, if the second calibration signal is faster than the first calibration signal, the second calibration signal is delayed. Thus, the first and the second calibration signals are synchronous.

Since the signal on the amplitude modulation path is delayed, if a phase signal is provided to the phase modulation path and an amplitude signal is provided to the amplitude modulation path, the phase signal and the amplitude signal are synchronous. In one embodiment, I/Q data is modulated by a phase-amplitude modulator to separate out the phase and the amplitude signals.

Referring toFIG. 2, the control unit230is utilized to determine which signal is faster. In the calibration mode, the detection module232detects the difference of the first and the second calibration signals and then generates an adjustment signal SADJaccording to the detection result. The delay module231delays at least one of the first and the second calibration signals according to the adjustment signal SADJ. InFIGS. 2 and 5, the delay module231delays the signal on the amplitude modulation path220. InFIGS. 6 and 7, the delay module231delays the signal on the phase modulation path210.

When the first and the second calibration signals are synchronous, the detection module232stops detecting the difference and maintains the adjustment signal SADJ. Since the delay level of the detection module232is maintained, the signals on the phase modulation path210and the amplitude modulation path220are synchronous.

Generally, when the phase modulation path or the amplitude modulation path comprises a filter. Delay is easily introduced into the filter. Thus, in the calibration mode, the detection module232detects the filtered signals. In one embodiment, the detection module232transforms the filtered signals into differential pairs and then generates an adjustment signal SADJaccording to the differential pairs.

Since the signals on the phase modulation path and the amplitude modulation path may be delayed by the elements of the phase modulation path and the amplitude modulation path, calibration signals are first provided to the phase modulation path and the amplitude modulation path. Then, the signals on the phase modulation path and the amplitude modulation path are detected to determine which calibration signal is faster. Then, the faster calibration signal is delayed by a delay module such that the calibration signals on the phase modulation path and the amplitude modulation path are synchronous.