Memory controller and memory system including the same having interface controllers generating parity bits

A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.

PRIORITY STATEMENT

A claim of priority is made under 35 U.S.C. §119 to Korean Patent Application No. 10-2009-0047105, filed on May 28, 2009, in the Korean Intellectual Property Office, the subject matter of which is hereby incorporated by reference.

BACKGROUND

The present disclosure relates to semiconductor memory devices, and more particularly, to a memory controller of a semiconductor memory device and a memory system including the memory controller.

Semiconductor memory devices are memory devices implemented using a semiconductor, such as silicon. Semiconductor memory devices are classified as volatile memory devices or nonvolatile memory devices.

The volatile memory devices lose stored data when the power supply is interrupted. Examples of the volatile memory devices include static random access memory (SRAM) devices, dynamic random access memory (DRAM) devices, and synchronous dynamic random access memory (SDRAM) devices. The nonvolatile memory devices retain stored date even when the power supply is interrupted. Examples of the nonvolatile memory devices include read-only memory (ROM) devices, programmable read-only memory (PROM) devices, erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, magnetic random access memory (MRAM) devices, resistive random access memory (RRAM) devices, and ferroelectric random access memory (FRAM) devices. The flash memory devices are classified as NOR-type flash memory devices or NAND-type flash memory devices.

A semiconductor memory is connected to a memory controller. The memory controller provides an interface between a host and the semiconductor memory. The memory controller is configured to control an operation of the semiconductor memory.

SUMMARY

Embodiments of the inventive concept provide a memory controller capable of detecting an error in data transmission, and a memory system including the memory controller.

In embodiments of the inventive concept, a memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.

Each of the first and second interface controllers may be configured to generate at least one parity bit corresponding to the received data and to transmit the received data and the corresponding at least one parity bit to the internal block.

Each of the first and second interface controllers may be configured to receive at least one external parity bit corresponding to the received data. A section for transmission of the received at least one external parity bit and a section for transmission of the generated at least one parity bit may have an overlapping section on a signal path in each of the first and second interface controllers.

The internal block may include first and second signal paths, the received data being transmitted on the first signal path with a first parity bit and the received data being transmitted on the second signal path with a second parity bit. The first signal path and the second signal path may have an overlapping section.

The overlapping section may include a data discontinuity block. The data discontinuity block may be an interface for exchanging data with an external device, a data unit setting block, a data encoding/decoding circuit or a storage circuit, for example.

The internal block may include a first parity control block configured to receive first data and at least one first parity bit from the first interface controller and decode the received at least one parity bit, and a data encoding/decoding block configured to encode the received first data and decode the encoded first data. The first parity control block may be further configured to check the decoded first data according to the received at least one parity bit.

The internal block may further include a second parity control block configured to generate at least one second parity bit based on the encoded first data and transmit the encoded first data and the generated at least one second parity bit to the second interface controller.

The second parity control block may be further configured to receive second data and at least one third parity bit from the second interface controller and decode the received at least one third parity bit. The data encoding/decoding block may be further configured to decode the received second data and encode the decoded second data. The second parity control block may be further configured to check the encoded second data according to the received at least one third parity bit.

The first parity control block may be further configured to generate at least one fourth parity bit based on the decoded second data and transmit the decoded second data and the generated at least one fourth parity bit to the first interface controller.

In further embodiments of the inventive concept, a memory system includes a memory device and a controller configured to control the memory device. The controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.

The memory device and the controller may compose a solid state drive (SSD) or a memory card.

In further embodiments of the inventive concept, a memory controller includes a first signal path configured to transmit data with at least one first parity bit, and a second signal path configured to transmit the data with at least one second parity bit. The first and second signal paths have an overlapping section.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which illustrative embodiments are shown. The inventive concept, however, may be embodied in various different forms, and should not be construed as being limited only to the illustrated embodiments. Rather, these embodiments are provided as examples, to convey the inventive concept to one skilled in the art. Accordingly, known processes, elements, and techniques are not described with respect to some of the embodiments. Throughout the drawings and written description, like reference numerals will be used to refer to like or similar elements.

FIG. 1is a block diagram of a memory system10, according to an embodiment of the inventive concept.

Referring toFIG. 1, the memory system10includes a controller100and a memory device200, according to an embodiment of the inventive concept.

The controller100is connected to a host and the memory device200. The controller100is configured to access the memory device200in response to a request from the host. For example, the controller100may be configured to control read/write/erase operations of the memory device200. As another example, the controller100may be configured to provide an interface between the memory device200and the host. As another example, the controller100may be configured to drive firmware for controlling the memory device200. The controller100is described in detail below with reference toFIG. 2.

The memory device200may include a memory cell array for storing data, a read/write circuit for reading/writing data from/in the memory cell array, an address decoder for decoding an address received from an external device and transferring the same to the read/write circuit, and a control logic circuit for controlling overall operation of the memory device200. For example, the memory device may include a volatile memory device such as SRAM, DRAM and SDRAM, a flash memory device, such as ROM, PROM, EPROM and EEPROM, or a nonvolatile memory device such as PRAM, MRAM, RRAM and FRAM. The memory device200will be described in detail below with reference toFIG. 15.

The controller100and the memory device200may be integrated into one semiconductor device. For example, the controller100and the memory device200may be integrated into one semiconductor device to constitute a memory card, such as a PC card (e.g., PCMCIA (Personal Computer Memory Card International Association)), a compact flash card (CF), a smart media card (SM/SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC and MMCmicro), a SD card (e.g., SD, miniSD, microSD and SDHC), or a universal flash storage (UFS).

As another example, the controller100and the memory device200may be integrated into one semiconductor device to constitute a solid state drive (SSD). The SSD may include a storage device configured to store data in a semiconductor memory. When the memory system10is used as an SSD, the operation speed of the host connected to the memory system10may increase significantly.

As another example, the memory system10may be applicable to computers, portable computers, UMPCs (Ultra Mobile PCs), workstations, net-books, PDAs, portable computers, web tablets, wireless phones, mobile phones, smart phones, digital cameras, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, devices capable of transmitting/receiving information in wireless environments, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, or one of various components constituting a computing system (e.g., an SSD and a memory card).

As another example, the memory device200or the memory system10may be mounted in various types of packages. Examples of packages that may include the memory device200or the memory system10include Package on Package (PoP), Ball Grid Arrays (BGA), Chip Scale Packages (CSP), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), and Wafer-level Processed Stack Package (WSP).

FIG. 2is a block diagram illustrating an embodiment of the controller100ofFIG. 1, according to an embodiment.

Referring toFIG. 2, the controller100includes a host interface110, a host interface controller120, an internal block130, a memory interface controller140, and a memory interface150.

The host interface110is configured to exchange data with an external device, such as the host, for example. The host interface110includes a protocol for communication with the host. For example, the host interface110may include one of various interface protocols, such as USB (Universal Serial Bus), MMC (Multimedia Card), PCI (Peripheral Component Interface), PCI-E (PCI-Express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (Small Computer Small Interface), ESDI (Enhanced Small Disk Interface), and IDE (Integrated Drive Electronics). The host interface110may communicate with the host on the basis of the protocol.

The host interface110is configured to exchange a first parity bit P1with the external device. For example, the host interface110may be configured to exchange a first parity bit P1with the host. The first parity bit P1may be based on the protocol of the host interface110, and the first parity bit P1may correspond to the data exchanged with the host. Although “parity bit” is used throughout this description, the term is intended to include one or more parity bits associated with data, or a parity scheme, without departing from the scope of the present teachings.

The host may transfer data and the first parity bit P1corresponding to the data to the host interface110, for example. The host interface110is configured to output the data and the first parity bit P1, received from the host, to the host interface controller120. The host interface110is also configured to receive data and a first parity bit P1corresponding to the data from the host interface controller120. The host interface110may transfer the data and the first parity bit P1, received from the host interface controller120, to the host.

The host interface controller120is configured to exchange data and a first parity bit P1with the host interface110. The host interface controller120is also configured to exchange data and a second parity bit P2corresponding to the data with the internal block130. The host interface controller120is configured to use the received first or second parity bit P1or P2to detect an error in the received data. For example, the host interface controller120is configured to use the received first or second parity bit P1or P2to detect and correct an error in the received data. The host interface controller120is configured to generate the first or second parity bit P1or P2on the basis of the received data. The host interface controller120will be described below in detail with reference toFIGS. 3 and 4.

The internal block130is configured to receive data and the second parity bit P2from the host interface controller120. The internal block130is configured to output the received data and the second parity bit P2to the memory interface controller140. For example, the internal block130may include a buffer.

The memory interface controller140is configured to exchange data and the second parity bit P2with the internal block130. The memory interface controller140is also configured to exchange data and a third parity bit P3corresponding to data with the memory interface150. The memory interface controller140is configured to use the received second or third parity bit P2or P3to detect an error in the received data. The memory interface controller140is configured to use the received second or third parity bit P2or P3to detect and correct an error in the received data. The memory interface controller140is also configured to generate the second or third parity bit P2or P3on the basis of the received data. The memory interface controller140will be described below in detail with reference toFIGS. 5 and 6.

The memory interface150is configured to exchange data and the third parity bit P3with the memory interface controller140. The memory interface150is also configured to exchange data and the third parity bit P3with an external device. For example, the memory interface150may be configured to exchange data and the third parity bit P3with the memory device200. The memory interface150includes a protocol for communication with the memory device200. For example, when the memory device200is a NAND flash memory device, the memory interface150includes a NAND protocol.

As illustrated inFIG. 2, data and a first parity bit P1are transferred through the host interface110to the host interface controller120. It is understood that the host interface110and the host interface controller120form a first signal path for transmission of the data and the first parity bit P1. An error in the data on the first signal path may be detected using the first parity bit P1.

Data and a second parity bit P2are transmitted from the host interface Controller120through the internal block130to the memory interface controller140. That is, the host interface controller120, the internal block130, and the memory interface controller140from a second signal path for transmission of the data and the second parity bit P2. An error in the data on the second signal path may be detected using the second parity bit P2.

Data and a third parity bit P3are transmitted through the memory interface150from the memory interface controller140. That is, the memory interface controller140and the memory interface150form a third signal path for transmission of the data and the third parity bit P3. An error in the data on the third signal path may be detected using the third parity bit P3.

As illustrated inFIG. 2, the first signal path for transmission of the first parity bit P1and the second signal path for transmission of the second parity bit P2overlap each other in the host interface controller120. Likewise, the second signal path for transmission of the second parity bit P2and the third signal path for transmission of the third parity bit P3overlap each other in the memory interface controller140. The first to third parity bits P1˜P3may be used to detect an error in data on the signal path from the host interface110to the memory interface150.

FIGS. 3 and 4are block diagrams illustrating the host interface controller120ofFIG. 2, according to an embodiment.

Referring toFIGS. 2 to 4, the host interface controller120includes an internal block121, a second parity control block123, and a first parity control block125.

The internal block121provides a channel between the host interface110and the internal block130. For example, the host interface110may operate in synchronization with the operation speed of the host, and the internal block130may operate in synchronization with an internal clock of the controller100. The operation speed of the host and the operation speed of the internal block130may be different from each other. In an embodiment, the internal block121may perform a buffer operation between a data input/output (I/O) operation synchronized with the operation speed of the host and a data I/O operation synchronized with the operation speed of the internal block130.

In the depicted embodiment, the internal block121includes a first-in first-out (FIFO) unit, for example. Data input in synchronization with the operation speed of the host may be sequentially stored in the FIFO unit, and the data stored in the FIFO unit may be sequentially output in synchronization with the operation speed of the internal block130. Likewise, data input in synchronization with the operation speed of the internal block130may be sequentially stored in the FIFO unit, and the data stored in the FIFO unit may be sequentially output in synchronization with the operation speed of the host.

Generally, the second parity control block123is configured to receive data from an external device and to generate a parity bit corresponding to the received data. The second parity control block123is also configured to receive data and a parity bit corresponding to the data from the external device and to detect an error in the received data by means of the received parity bit. For example, the second parity control block123may be configured to detect/correct an error in the received data by means of the received parity bit. In the depicted embodiment, the parity bit generated/used by the second parity control block123is second parity bit P2.

Generally, the first parity control block125is configured to receive data from an external device and to generate a parity bit corresponding to the received data. The first parity control block125is also configured to receive data and a parity bit corresponding to the data from the external device and to detect an error in the received data by means of the received parity bit. For example, the first parity control block125may be configured to detect/correct an error in the received data by means of the received parity bit. In the depicted embodiment, the parity bit generated/used by the first parity control block125is a first parity bit P1.

Data received from the host are stored in the FIFO unit through the second parity control block123. The data stored in the FIFO unit are transferred through the first parity control block125to the internal block130. Data received from the internal block130are stored in the FIFO unit through the first parity control block125. The data stored in the FIFO unit are transferred through the second parity control block123to the host interface110.

A process for transferring data from the host through the host interface controller120to the internal block130is described below with reference toFIG. 3.

The host interface controller120is configured to receive data and a first parity bit P1through the host interface110from the host. For example, the first parity bit P1may be a parity bit according to the protocol for communication of the controller100with the host.

The second parity control block123is configured to receive the data and the first parity bit P1from the host interface110. The second parity control block123is configured to generate a second parity bit P2corresponding to the received data on the basis of the received data. That is, the second parity control block123is configured to encode the received data. Together with the received data, the first and second parity bits P1and P2are transferred from the second parity control block123to the internal block121.

The first parity control block125is configured to receive the data and the first and second parity bits P1and P2from the internal block121. The first parity control block125is configured to detect an error in the received data by means of the received first parity bit P1. For example, the first parity control block125is configured to detect/correct an error in the received data by means, of the received first parity bit P1. That is, the first parity control block125is configured to decode the received data by means of the received first parity bit P1.

When detecting an error in the received data, the first parity control block125may generate an error report message. For example, the error report message may be transferred to a processor (not illustrated) of the controller100. The processor of the controller100performs a predetermined operation in response to the error report message. As another example, the error report message may be transferred to the host. The host performs a predetermined operation in response to the error report message.

For example, if an error is detected in the received data and the detected error is within a correctable range, the first parity control block125uses the received first parity bit P1to correct the error in the received data. If an error is detected in the received data and the detected error is outside the correctable range, the first parity control block125outputs an error report message. If an error is not detected in the received data or if a detected error is corrected, the first parity control block125outputs the second parity bit P2and the data. The second parity bit P2and the data are transferred to the internal block130.

A process for transferring data from the internal block130through the host interface controller120to the host is described below with reference toFIG. 4.

The host interface controller120is configured to receive data and a second parity bit P2from the internal block130.

The first parity control block125is configured to receive the data and the second parity bit P2from the internal block130. The first parity control block125is configured to generate a first parity bit P1corresponding to the received data on the basis of the received data. That is, the first parity control block125is configured to encode the received data. Together with the received data, the first and second parity bits P1and P2are transferred from the first parity control block125to the internal block121.

The second parity control block123is configured to receive the data and the first and second parity bits P1and P2from the internal block121. The second parity control block123is configured to detect an error in the received data by means of the received second parity bit P2. For example, the second parity control block123is configured to detect/correct an error in the received data by means of the received second parity bit P2. That is, the second parity control block123is configured to decode the received data by means of the received second parity bit P2.

When detecting an error in the received data, the second parity control block123may generate an error report message. For example, the error report message may be transferred to a processor (not illustrated) of the controller100. The processor of the controller100performs a predetermined operation in response to the error report message. As another example, the error report message may be transferred to the host. The host performs a predetermined operation in response to the error report message.

For example, if an error is detected in the received data and the detected error is within a correctable range, the second parity control block123uses the received second parity bit P2to correct the error in the received data. If an error is detected in the received data and the detected error is outside the correctable range, the second parity control block123outputs an error report message. If an error is not detected in the received data or a detected error is corrected, the second parity control block123outputs the first parity bit P1and the data. The first parity bit P1and the data are transferred through the host interface110to the host.

Data input to the internal block121including the FIFO unit are stored in the FIFO unit prior to output. That is, the input data and the output data of the internal block121including the FIFO unit are discontinuous. It will be understood that the internal block121is a data discontinuity block. The data discontinuity block indicates that the input data and the output data of the block are discontinuous. That is, an input terminal and an output terminal of the data discontinuity block are not directly connected through the signal path. For example, in the internal block121, the input data are stored in the FIFO unit and the data stored in the FIFO unit are output.

When the input data and the output data are discontinuous, an error may occur in the data discontinuity block. For example, when the data stored in the FIFO unit are output, the data output sequence of the FIFO unit may change due to the influence of noise or an error in hardware or software. When the data output sequence of the FIFO unit changes, the output data of the FIFO unit may contain an error. Likewise, the data stored in the FIFO unit may be inverted due to the influence of noise or an error in hardware or software. When the data stored in the FIFO unit are inverted, the output data of the FIFO unit may contain an error.

As described with reference toFIGS. 3 and 4, the first parity bit P1is used to detect an error in the data transmitted from the second parity control block123through the internal block121to the first parity control block125. The second parity bit P2is used to detect an error in the data transmitted from the first parity control block125through the internal block121to the second parity control block123.

It will be understood that an error detection section using a specific parity bit is a section capable of detecting an error in the section by means of the parity bit. In this case, an error detection section using the second parity bit P2includes the second parity control block123and the internal block121, and an error detection section using the first parity bit P1includes the internal block121and the first parity control block125. That is, the error detection sections using the first and second parity bits P1and P2overlap each other in the internal block121.

Data received from the host interface110are stored in the FIFO unit of the host interface controller120, and an error in the data is detected after the data are output from the FIFO unit. Data received from the internal block130are stored in the FIFO unit of the host interface controller120, and an error in the data is detected after the data are output from the FIFO unit.

That is, when the error detection sections using the first and second parity bits P1and P2overlap each other in the internal block121, an error in the internal block121can be detected as described with reference toFIGS. 3 and 4. In other words, an error in the data discontinuity block (e.g., the FIFO unit) can be detected by overlapping the error detection sections.

FIGS. 5 and 6are block diagrams illustrating the memory interface controller140ofFIG. 2, according to an embodiment.

Referring toFIGS. 2,5and6, the memory interface controller140includes an internal block141, a third parity control block143, and a second parity control block145.

The internal block141provides a channel between the memory interface150and the internal block130. For example, the memory interface150may operate in synchronization with the operation speed of the memory device200, and the internal block130may operate in synchronization with an internal clock of the controller100. The operation speed of the memory device200and the operation speed of the internal block130may be different from each other. The internal block141may perform a buffer operation between a data I/O operation synchronized with the operation speed of the memory device200and a data I/O operation synchronized with the operation speed of the internal block130.

For example, in the depicted embodiment, the internal block141includes a FIFO unit. Data input in synchronization with the operation speed of the memory device200may be sequentially stored in the FIFO unit. The data stored in the FIFO unit may be sequentially output in synchronization with the operation speed of the internal block130. Likewise, data input in synchronization with the operation speed of the internal block130may be sequentially stored in the FIFO unit. The data stored in the FIFO unit may be sequentially output in synchronization with the operation speed of the memory device200.

Generally, the third parity control block143is configured to receive data from an external device and to generate a parity bit corresponding to the received data. The third parity control block143is also configured to receive data and a parity bit corresponding to the data from an external device and to detect an error in the received data by means of the received parity bit. For example, the third parity control block143may be configured to detect/correct an error in the received data by means of the received parity bit. In the depicted embodiment, the parity bit generated/used by the third parity control block143is third parity bit P3.

Generally, the second parity control block145is configured to receive data from an external device and to generate a parity bit corresponding to the received data. The second parity control block145is also configured to receive data and a second parity bit P2corresponding to the data from an external device and detect an error in the received data by means of the received second parity bit P2. For example, the second parity control block145may be configured to detect/correct an error in the received data by means of the received second parity bit P2.

Data received from the memory device200are stored in the FIFO unit through the second parity control block145. The data stored in the FIFO unit are transferred through the third parity control block143to the internal block130. Data received from the internal block130are stored in the FIFO unit through the third parity control block143. The data stored in the FIFO unit are transferred through the second parity control block145to the memory interface150.

A process for transferring data from the internal block130through the memory interface controller140to the memory device200will be described below with reference toFIG. 5.

The memory interface controller140is configured to receive data and a second parity bit P2from the internal block130. For example, the second parity bit P2may be a parity bit generated by the second parity control block123described with reference toFIGS. 3 and 4.

The third parity control block143is configured to receive the data and the second parity bit P2from the internal block130. The third parity control block143is configured to generate a third parity bit P3corresponding to the received data on the basis of the received data. That is, the third parity control block143is configured to encode the received data. Together with the received data, the second and third parity bits P2and P3are transferred from the third parity control block143to the internal block141.

The second parity control block145is configured to receive the data and the second and third parity bits P2and P3from the internal block141. The second parity control block145is configured to detect an error in the received data by means of the received second parity bit P2. For example, the second parity control block145is configured to detect/correct an error in the received data by means of the received second parity bit P2. That is, the second parity control block145is configured to decode the received data by means of the received second parity bit P2.

When detecting an error in the received data, the second parity control block145may generate an error report message. For example, the error report message may be transferred to a processor (not illustrated) of the controller100. The processor of the controller100performs a predetermined operation in response to the error report message. As another example, the error report message may be transferred to the host. The host performs a predetermined operation in response to the error report message.

For example, if an error is detected in the received data and the detected error is within a correctable range, the second parity control block145uses the received second parity bit P2to correct the error in the received data. If an error is detected in the received data and the detected error is outside the correctable range, the second parity control block145outputs an error report message. If an error is not detected in the received data or a detected error is corrected, the second parity control block145outputs the third parity bit P3and the data. The third parity bit P3and the data are transferred through the memory interface150to the memory device200. The third parity bit P3and the data are written in the memory device200. For example, the third parity bit P3may be generated according to the protocol for communication between the controller100and the memory device200.

A process for transferring data from the memory device200through the memory interface controller140to the internal block130is described below with reference toFIG. 6.

The memory interface controller140is configured to receive data and a third parity bit P3from the memory device200. For example, the data and the third parity bit P3read from the memory device200are received by the memory interface controller140.

The second parity control block145is configured to receive the data and the third parity bit P3from the memory interface150. The second parity control block145is configured to generate a second parity bit P2corresponding to the received data on the basis of the received data. That is, the second parity control block145is configured to encode the received data. Together with the received data the second and third parity bits P2and P3are transferred from the second parity control block145to the internal block141.

The third parity control block143is configured to receive the data and the second and third parity bits P2and P3from the internal block141. The third parity control block143is configured to detect an error in the received data by means of the received third parity bit P3. For example, the third parity control block143is configured to detect/correct an error in the received data by means of the received third parity bit P3. That is, the third parity control block143is configured to decode the received data by means of the received third parity bit P3.

When detecting an error in the received data, the third parity control block143generates an error report message. For example, the error report message may be transferred to a processor (not illustrated) of the controller100. The processor of the controller100performs a predetermined operation in response to the error report message. As another example, the error report message may be transferred to the host. The host performs a predetermined operation in response to the error report message.

For example, if an error is detected in the received data and the detected error is within a correctable range, the third parity control block143uses the received third parity bit P3to correct the error in the received data. If an error is detected in the received data and the detected error is outside the correctable range, the third parity control block143outputs an error report message. If an error is not detected in the received data or a detected error is corrected, the third parity control block143outputs the second parity bit P2and the data. The second parity bit P2and the data are transferred to the internal block130.

As described with reference toFIGS. 5 and 6, the second parity bit P2is used to detect an error in the data transmitted from the third parity control block143through the internal block141to the second parity control block145. The third parity bit P3is used to detect an error in the data transmitted from the second parity control block145through the internal block141to the third parity control block143.

An error detection section using the third parity bit P3includes the third parity control block143and the internal block141, and an error detection section using the second parity bit P2includes the internal block141and the second parity control block145. That is, the error detection sections using the second and third parity bits P2and P3overlap each other in the internal block141.

Data received from the memory interface150are stored in the FIFO unit of the memory interface controller140, and an error in the data is detected after the data are output from the FIFO unit. Data received from the internal block130are stored in the FIFO unit of the memory interface controller140, and an error in the data is detected after the data are output from the FIFO unit.

That is, when the error detection sections using the second and third parity bits P2and P3overlap each other in the internal block141, an error in the internal block141can be detected as described with reference toFIGS. 5 and 6. In other words, an error in the data discontinuity block can be detected by overlapping the error detection sections.

Referring toFIGS. 2 to 6, the first parity bit P1may be used to detect an error generated in the host interface110and the host interface controller120. The third parity bit P3may be used to detect an error generated in the memory interface150and the memory interface controller140. The second parity bit P2may be used to detect an error generated in the host interface controller120, the internal block130and the memory interface controller140.

The host interface controller120and the memory interface controller140are configured to exchange the parity bit (e.g., the second parity bit P2) with the internal block130and to detect an error in the internal block130by means of the exchanged parity bit (e.g., the second parity bit P2). In particular, the error detection sections overlap each other in the internal block121of the host interface controller120and the internal block141of the memory interface controller140. Thus, it is possible to detect an error in the internal block121of the host interface controller120and the internal block141of the memory interface controller140. The efficiency of detecting an error in the section between the host interface controller120and the memory interface controller140, which are data discontinuity blocks, is improved. That is, the reliability of the controller100is improved.

FIG. 7is a block diagram of a memory system20, according to an embodiment of the inventive concept.

Referring toFIG. 7, the memory system20includes a memory device200, a controller300, and a random access memory (RAM)500.

The memory device200is configured to communicate with the controller300. The memory device200will be described in detail below with reference toFIG. 11.

The controller300is configured to communicate with the memory device200and the RAM500. The controller300is configured to store data in the memory device200. The controller300will be described in detail below with reference toFIG. 8.

The RAM500is configured to communicate with the controller300. The RAM500may include a volatile RAM or a nonvolatile RAM. An operation of the RAM500will be described in detail below with reference toFIG. 8.

The RAM500is depicted separate from the controller300and the memory device200inFIG. 7. However, the RAM500is not limited to this configuration, and may be implemented as one of the internal components of the controller300, for example.

It is understood that the memory device200, the controller300and the RAM500may constitute a memory card or a solid state drive (SSD), as described with reference toFIG. 1.

FIG. 8is a block diagram illustrating the controller300and the RAM500ofFIG. 7, according to an embodiment.

Referring toFIG. 8, the controller300is configured to communicate with the RAM500.

The controller300includes a host interface310, a host interface controller320, an internal block330, a memory interface controller340, and a memory interface350.

The host interface310, the host interface controller320and the memory interface350are configured substantially the same as the host interface110, the host interface controller120and the memory interface150described with reference toFIGS. 1 to 6. Thus, the detailed description will not be repeated for conciseness.

The memory interface controller340is configured to communicate with the internal block330and the memory interface350. The memory interface controller340is also configured to exchange data and a fifth parity bit P5with the internal block330and to exchange data and a third parity bit P3with the memory interface350. With the exception of exchanging the fifth parity bit P5with the internal block330, the memory interface controller340is configured substantially the same as the memory interface controller140described above with reference toFIGS. 1 to 6. For example, the memory interface controller340is configured to include a fifth parity control block instead of the second parity control block145described with reference toFIGS. 1 to 6.

The internal block330is configured to communicate with the host interface controller320and the memory interface controller340. The internal block330is configured to exchange data and a second parity bit P2with the host interface controller320. The internal block330is configured to exchange data and a fifth parity bit P5with the memory interface controller340. That is, the internal block330generates a parity bit (e.g., the fifth parity bit P5or the second parity bit P2) on the basis of received data, and checks an error in the received data by means of a received parity bit (e.g., the second parity bit P2or the fifth parity bit P5).

The internal block330includes an interface331. The interface331includes an interface for communication with the RAM500. For example, data received from the memory device200are stored in the RAM500through the interface331. The data stored in the RAM500may be transferred through the interface331to the host. Also, data received from the host may be stored in the RAM500through the interface331. The data stored in the RAM500may be transferred through the interface331to the memory device200. That is, the RAM500operates as a buffer memory between the host and the memory device200.

For example, when a data request is received from the host, it is determined whether the requested data are present in the RAM500. If the requested data are present in the RAM500, the corresponding data are transferred from the RAM500through the interface331to the host. If the requested data are not present in the RAM500, the corresponding data are stored in the RAM500through the interface331from the memory device200. The corresponding data may then be transferred from the RAM500through the interface331to the host. That is, the RAM500operates as a cache memory.

As described above, the data read from the memory device200are stored in the RAM500, and the data stored in the RAM500are transferred to the host. Also, the data received from the host are stored in the RAM500, and the data stored in the RAM500are transferred to the memory device200. That is, the RAM500and/or the interface331may be considered data discontinuity blocks.

The error detection sections may overlap each other in the RAM500to detect an error in the RAM500or the interface331, which may be data discontinuity blocks.

For example, inFIG. 8, a first parity bit P1may be used to detect an error generated in the host interface310and the host interface controller320. A third parity bit P3may be used to detect an error generated in the memory interface350and the memory interface controller340. A second parity bit P2may be used to detect an error generated in the host interface controller320and the internal block330. A fifth parity bit P5may be used to detect an error generated in the memory interface controller340and the internal block330. A fourth parity bit P4may be used to detect an error generated in the internal block330and the RAM500.

FIG. 9is a block diagram illustrating the interface331and the RAM500ofFIG. 8, according to an embodiment.

Referring toFIG. 9, the interface331includes an interface block332, a first parity block333, and a second parity block336.

The interface block332is configured to communicate with the first parity block333, the second parity block336and the RAM500. The interface block332is configured to exchange data and a fourth parity bit P4with the first parity block333, to exchange data and the fourth parity bit P4with the second parity block336, and to exchange data and the fourth parity bit P4with the RAM500. The interface block332is also configured to selectively provide a channel between the first parity block333and the RAM500and a channel between the second parity block336and the RAM500. For example, the interface block332includes a protocol for communication with the RAM500.

The first parity block333is configured to communicate with the host interface controller320and the interface block332. The first parity block333is configured to exchange data and a second parity bit P2with the host interface controller320, and to exchange data and a fourth parity bit P4with the interface block332. The first parity block333includes a fourth parity control block334and a second parity control block335.

The fourth parity control block334is configured to generate the fourth parity bit P4on the basis of the data received from the host interface controller320. The data and the second and fourth parity bits P2and P4are transferred to the second parity control block335. The fourth parity control block334is also configured to detect an error in the data received from the second parity control block335, by means of the fourth parity bit P4received from the second parity control block335.

The second parity control block335is configured to detect an error in the data received from the fourth parity control block334, by means of the second parity bit P2received from the fourth parity control block334. The second parity control block335is configured to generate a second parity bit P2on the basis of the data received from the interface block332. The data and the second and fourth parity bits P2and P4are transferred to the fourth parity control block334.

The second parity block336is configured to communicate with the memory interface controller340and the interface block332. The second parity block336is configured to exchange data and a fifth parity bit P5with the memory interface controller340. The second parity block336is configured to exchange data and a fourth parity bit P4with the interface block332. The second parity block336includes a fourth parity control block337and a fifth parity control block338.

The fourth parity control block337is configured to generate the fourth parity bit P4on the basis of the data received from the memory interface controller340. The data and the fourth and fifth parity bits P4and P5are transferred to the fifth parity control block338. The fourth parity control block337is also configured to detect an error in the data received from the fifth parity control block338, by means of the fourth parity bit P4received from the fifth parity control block338.

The fifth parity control block338is configured to detect an error in the data received from the fourth parity control block337, by means of the fifth parity bit P5received from the fourth parity control block337. The fifth parity control block338is also configured to generate a fifth parity bit P5on the basis of the data received from the interface block332. The data and the fourth and fifth parity bits P4and P5are transferred to the fourth parity control block337.

In summary, the second parity bit P2may be used to detect an error generated between the host interface controller320and the interface331, which are data discontinuity blocks. The fifth parity bit P5may be used to detect an error generated between the interface331and the memory interface controller340, which are data discontinuity blocks. The fourth parity bit P4may be used to detect an error generated in the interface331and the RAM500, which are data discontinuity blocks. That is, errors generated between the data discontinuity blocks are detected separately from other error detection sections. Thus, the efficiency of detecting an error generated in the host interface controller320, the interface331, the RAM500and the memory interface controller340is improved, and the reliability of the controller300is improved.

It is understood that at least one error detection section may be omitted if the error rate of the host interface controller320, the interface331and the RAM500, which are data discontinuity blocks, is lower than a predetermined value. For example, data and a second parity bit P2may be exchanged between the host interface controller120and the memory interface controller140, as described with reference toFIGS. 1 to 6. The second parity bit P2may be used to detect errors generated between the host interface controller120and the memory interface controller140, including errors generated in the interface331and the RAM500.

FIG. 10is a block diagram illustrating the RAM500and another embodiment300′ of the controller300ofFIG. 7.

Referring toFIG. 10, the controller300′ includes a host interface310, a host interface controller320, an internal block330′, a memory interface controller340′, and a memory interface350.

The host interface310, the host interface controller320and the memory interface350are configured substantially the same as described above with reference toFIGS. 7 to 9. Thus, the detailed description will not be repeated for conciseness.

With the exception of exchanging data and a fourth parity bit P4with the internal block330′, the memory interface controller340′ operates substantially the same as the memory interface controller340described above with reference toFIGS. 7 to 9. For example, the memory interface controller340′ is configured to include a fourth parity control block instead of the second parity control block145described with reference toFIGS. 1 to 6.

The internal block330′ is configured to exchange data and a second parity bit P2with the host interface controller320. The internal block330′ is configured to exchange data and a fourth parity bit P4with the memory interface controller340′. The internal block330′ includes an interface331′ configured to communicate with the RAM500.

FIG. 11is a block diagram illustrating the interface331′ and the RAM500ofFIG. 10, according to an embodiment.

Referring toFIG. 11, the interface331′ includes an interface block332′, a fourth parity control block334′, and a second parity control block336′.

The fourth parity control block334′ receives data and a second parity bit P2from the host interface controller320. The fourth parity control block334′ generates a fourth parity bit P4on the basis of the received data. The data and the second and fourth parity bits P2and P4are stored in the RAM500through the interface block332′.

The second parity control block336′ receives the data and the second and fourth parity bits P2and P4through the interface block332′ from the RAM500. The second parity control block336′ detects an error in the received data by means of the received second parity bit P2. The data and the fourth parity bit P4are transferred to the memory interface controller340′.

The second parity control block336′ receives data and a fourth parity bit P4from the memory interface controller340′. The second parity control block336′ generates a second parity bit P2on the basis of the received data. The data and the second and fourth parity bits P2and P4are stored in the RAM500through the interface block332′.

The fourth parity control block334′ receives the data and the second and fourth parity bits P2and P4through the interface block332′ from the RAM500. The fourth parity control block334′ detects an error in the received data by means of the received fourth parity bit P4. The data and the second parity bit P2are transferred to the host interface controller320.

As described with reference toFIGS. 10 and 11, the second parity bit P2is used to detect an error in a data transmission section between the host interface controller320and the internal block330′. The fourth parity bit P4is used to detect an error in a data transmission section between the memory interface controller340′ and the internal block330′. The error detection section using the second parity bit P2and the error detection section using the fourth parity bit P4overlap each other in the internal block330′.

The error detection using the second parity bit P2is performed after the data and the second parity bit P2pass through the interface block332′ and the RAM500, which are data discontinuity blocks. The error detection using the fourth parity bit P4is performed after the data and the fourth parity bit P4pass through the interface block332′ and the RAM500, which are data discontinuity blocks. That is, an error generated in the data discontinuity blocks may be detected by overlapping the error detection sections in the data discontinuity blocks. Thus, the reliability of the controller300′ is improved.

FIG. 12is a block diagram illustrating a controller400, which may be included as the controller100ofFIG. 1, according to an embodiment.

Referring toFIG. 12, the controller400includes a host interface410, a host interface controller420, an internal block430, a memory interface controller440, and a memory interface450.

The host interface410, the host interface controller420and the memory interface450are configured substantially the same as the host interface110, the host interface controller120and the memory interface150described above with reference toFIGS. 1 to 6. Thus, the detailed description will not be repeated for conciseness.

With the exception of exchanging data and a fourth parity bit P4with the internal block430, the memory interface controller440is configured substantially the same as the memory interface controller140described above with reference toFIGS. 1 to 6. For example, the memory interface controller440is configured to include a fourth parity control block instead of the second parity control block145described with reference toFIGS. 1 to 6.

The internal block430is configured to exchange data and a second parity bit P2with the host interface controller420. The internal block430is also configured to exchange data and a fourth parity bit P4with the memory interface controller440.

The internal block430is configured to generate a fourth parity bit P4on the basis of the data received from the host interface controller420. The data and the fourth parity bit P4are transferred to the memory interface controller440. The internal block430is configured to detect an error in the data received from the host interface controller420, by means of the second parity bit P2received from the host interface controller420.

The internal block430is also configured to generate a second parity bit P2on the basis of the data received from the memory interface controller440. The data and the second parity bit P2are transferred to the host interface controller420. The internal block430is configured to detect an error in the data received from the memory interface controller440, by means of the fourth parity bit P4received from the memory interface controller440.

FIG. 13is a block diagram illustrating the internal block430ofFIG. 12, according to an embodiment.

Referring toFIG. 13, the internal block430includes a data discontinuity block431, a fourth parity control block433, and a second parity control block435.

The data discontinuity block431is a block configured to process data discontinuously. For example, the data discontinuity block431may include a storage circuit configured to store data, such as a FIFO unit, a QUEUE unit, a register, a stack, a latch, a memory or an interface to a memory.

For example, the data discontinuity block431may include a circuit configured to normalize data. For example, the data discontinuity block431may include an interface configured to exchange data with the host in a first unit (e.g., a data access unit of the host) and exchange data with the memory device200in a second unit (e.g., a data access unit of the memory device200). That is, the data discontinuity block431may include a data unit setting block (or circuit) which normalizes data exchanged with the host in a first data unit and data exchanged with the memory device200in a second data unit. The first unit may include a sector and a cluster, and the second unit may include a sector, a cluster, and page.

For example, the data discontinuity block431may include data conversion circuits, such as data encoding/decoding circuits and/or data encryption circuits. Also, for example, the data discontinuity block431may include an interface for communicating with an external RAM, as described with reference toFIGS. 7 to 11.

The fourth parity control block433is configured to exchange data and a second parity bit P2with the host interface controller420. The fourth parity control block433is also configured to exchange the data and second and fourth parity bits P2and P4with the data discontinuity block431.

The fourth parity control block433is configured to generate a fourth parity bit P4on the basis of the data received from the host interface controller420. The data and the second and fourth parity bits P2and P4are transferred to the data discontinuity block431. The fourth parity control block433is configured to detect an error in the data received from the data discontinuity block431, by means of the fourth parity bit P4received from the data discontinuity block431.

The second parity control block435is configured to exchange data and a fourth parity bit P4with the memory interface controller440. The second parity control block435is also configured to exchange data and second and fourth parity bites P2and P4with the data discontinuity block431.

The second parity control block435is configured to generate a second parity bit P2on the basis of the data received from the memory interface controller440. The data and the second and fourth parity bits P2and P4are transferred to the data discontinuity block431. The second parity control block435is configured to detect an error in the data received from the data discontinuity block431, by means of the second parity bit P2received from the data discontinuity block431.

That is, the error detection section using the second parity bit P2and the error detection section using the fourth parity bit P4overlap each other in the data discontinuity block431. Thus, an error generated in the data discontinuity block431can be detected, and the reliability of the controller400is improved.

As described above, an error generated between the data discontinuity blocks may be detected separately from other error detection sections. Also, the error detection sections may be configured to overlap each other in the data discontinuity blocks. It is understood that the configurations of the error detection sections of the controller100/300/400may be selected on the basis of the error rate in the data discontinuity block.

For example, in the data discontinuity block, the sequence or information of the received data may be changed prior to output. In this case, it may be impossible to check an error in the output data by means of the parity bit received from the previous block.

Also, it is assumed that a parity bit and data are received from the previous block and the received data are encoded using an encryption technique. In this case, it may be impossible to detect an error in the encoded data by means of the parity bit received from the previous block. An encoding/decoding operation incapable of detecting a data error by means of the parity bit received from the previous block will be referred to as a discontinuous encoding/decoding operation. Also, a block performing a discontinuous encoding/decoding operation will be referred to as a discontinuous encoder/decoder.

FIG. 14is a block diagram illustrating internal block430′ as another embodiment of the internal block430ofFIG. 12.

Referring toFIG. 14, the internal block430′ includes a data discontinuity block431′, a second parity control block433′, and a fourth parity control block435′. The data discontinuity block431′ includes a discontinuous encoder437′ and a discontinuous decoder439′.

A process for transferring data from the host interface controller420through the internal block430′ to the memory interface controller440is described below.

The second parity control block433′ receives data and a second parity bit P2from the host interface controller420. The second parity control block433′ may check an error in the received data by means of the received second parity bit P2.

The second parity control block433′ outputs the received data as first data Data1. The first data Data1are transferred to the discontinuous encoder437′. The discontinuous encoder437′ encodes the received first data Data1discontinuously, and outputs the discontinuously encoded first data Data1as second data Data2. The second data Data2are transferred to the fourth parity control block435′ and the discontinuous decoder439′. The fourth parity control block435′ generates a fourth parity bit P4on the basis of the received second data Data2. The fourth parity control block435′ transfers the second data Data2and the fourth parity bit P4to the memory interface controller440.

The discontinuous decoder439′ receives the second data Data2from the discontinuous encoder437′. The discontinuous decoder439′ decodes the received second data Data2, and outputs the decoded second data Data2as first data Data1. The first data Data1are transferred to the second parity control block433′. The second parity control block433′ detects an error in the received first data Data1by means of the received second parity bit P2.

A process for transferring data from the memory interface controller440through the internal block430′ to the host interface controller420is described below.

The fourth parity control block435′ receives data and a fourth parity bit P4from the memory interface controller440. The fourth parity control block435′ may detect an error in the received data by means of the received fourth parity bit P4. The fourth parity control block435′ outputs the received data as second data Data2. The second data Data2are transferred to the discontinuous decoder439′.

The discontinuous decoder439′ decodes the received second data Data2, and outputs the decoded second data Data2as first data Data1. The first data Data1are transferred to the second parity control block433′ and the discontinuous encoder437′.

The second parity control block433′ generates a second parity bit P2on the basis of the received first data Data1. The second parity control block433′ transfers the first data Data1and the second parity bit P2to the host interface controller420.

The discontinuous encoder437′ receives the first data Data1from the discontinuous decoder439′. The discontinuous encoder437′ encodes the received first data Data1. The discontinuous encoder437′ outputs the encoded first data Data1as second data Data2. The second data Data2are transferred to the fourth parity control block435′.

The fourth parity control block435′ receives the second data Data2from the discontinuous encoder437. The fourth parity control block435′ detects an error in the second data Data2received from the discontinuous encoder437′ by means of the fourth parity bit P4received from the memory interface controller440.

As described above, the discontinuously encoded data are discontinuously decoded prior to error check. The discontinuously decoded data are discontinuously encoded prior to error check. Thus, the error detection sections may overlap each other in the discontinuous encoder/decoder. The error detection performance of the controller400and the reliability of the controller400are improved

FIG. 15is a block diagram illustrating the memory device200ofFIG. 1, according to an embodiment.

Referring toFIG. 15, the memory device200includes a memory cell array210, an address decoder220, a read/write circuit230, and a control logic circuit240.

The memory cell array210is connected through word lines WL to the address decoder220and is connected through bit lines BL to the read/write circuit230. The memory cell array210may include multiple memory cells, for example, where rows of the memory cells are connected to the word lines WL and columns of the memory cells are connected to the bit lines BL. For example, the memory cells may be configured to store one or more bits per cell. Also, the memory cell array210may include multiple semiconductor memory cells.

The address decoder220is connected through the word lines WL to the memory cell array210. The address decoder220operates in response to the control of the control logic circuit240. The address decoder220receives an address ADDR from an external device. For example, the address ADDR may be received from the controller100/300/400, described above with reference toFIGS. 1 to 14.

The address decoder220decodes a row address among the received addresses ADDR to select the word lines WL. The address decoder220decodes a column address among the received addresses ADDR and transfers the same to the read/write circuit230. The address decoder220may include a row decoder, a column decoder, and an address buffer, for example.

The read/write circuit230is connected through the bit lines BL to the memory cell array210. The read/write circuit230is configured to exchange data with an external device. For example, the read/write circuit230may exchange data with the controller100/300/400, described above with reference toFIGS. 1 to 14.

The read/write circuit230operates in response to the control of the control logic circuit240. The read/write circuit230receives the decoded column address from the address decoder220to select the bit lines BL.

The read/write circuit230may receive data from an external device and write the received data in the memory cell array210, and/or read data from the memory cell array210and output the read data to an external device. Also, the read/write circuit230may read data from a first storage region of the memory cell array210and write the read data in a second storage region of the memory cell array210. The read/write circuit230may also perform a copy-back operation.

The read/write circuit230may include a page buffer, a column selection circuit, and a data buffer, for example. Also, the read/write circuit230may include a sense amplifier, a write driver, a column selection circuit, and a data buffer, for example.

The control logic circuit240is connected to the address decoder220and the read/write circuit230. The control logic circuit240controls an overall operation of the memory device200. The control logic circuit240operates in response to a control signal CTRL received from an external device. For example, the control signal CTRL may be received from the controller100/300/400, described above with reference to

The memory device200may be configured to store data in semiconductor memory cells, on a storage medium such as a disk-type storage, and/or on an optical disk, for example.

FIG. 16is a block diagram illustrating a memory system30, which may be included as the memory system10ofFIG. 1, according to an embodiment.

Referring toFIG. 16, the memory system30includes a controller100/300/400and a memory device200.

The controller100/300/400is configured to operate substantially the same as described above with reference toFIGS. 1 to 14.

The memory device200includes multiple memory chips. The memory chips form multiple memory chip groups. Each of the memory chip groups has a channel for communication with the controller100/300/400. For example, it is illustrated inFIG. 16that the memory device200communicates with the controller100/300/400through ‘k’ channels. Each of the memory chips may be configured substantially the same as described above with reference toFIG. 15.

It is understood that the controller100/300/400and the memory device200may constitute a memory card or a solid state drive (SSD), as described above with reference toFIG. 1.

FIG. 17is a block diagram of a computing system600, including the memory system10,20or30ofFIG. 1,7or16, according to an embodiment.

Referring toFIG. 17, a computing system600according to an embodiment of the inventive concept includes a central processing unit (CPU)610, a random access memory (RAM)620, a user interface630, a power supply640, and a memory system10/20/30.

The memory system10/20/30is electrically connected through a system bus650to the CPU610, the RAM620, the user interface630, and the power supply640. Data, which are provided through the user interface630or processed by the CPU610, are stored in the memory system10/20/30. The memory system10/20/30includes a controller100/300/400and a memory device200, as discussed above.

When the memory system10/20/30is provided for a solid state drive (SSD), the booting speed of the computing system600may increase substantially. Although not illustrated inFIG. 17, it would be apparent to one skilled in the art that the computing system600may further include an application chipset, a camera image processor, and the like.

According to embodiments of the inventive concept, the controller100/300/400has one or more error detection sections, and the error detection sections overlap each other in the data discontinuity block of the controller100/300/400. Thus, an error in the data discontinuity section can be detected, improving the reliability of the controller100/300/400.

According to embodiments of the inventive concept, the controller100/300/400has one or more error detection sections, and an error in the data discontinuity block can be detected separately from other error detection sections. Thus, an error in the data discontinuity section can be detected, improving the reliability of the controller100/300/400.

The reliability of the controller100/300/400increases with an increase in the number of error detection sections in the controller100/300/400. On the other hand, the complexity of the controller100/300/400increases with an increase in the number of error detection sections in the controller100/300/400. Thus, the number of error detection sections in the memory controller100/300/400may be selected considering the desired reliability and complexity of the memory controller100/300/400.

According to the inventive concept described above, the memory controller is able to detect an error in data transmission, thus improving its reliability.

The above-disclosed subject matter is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the spirit and scope of the inventive concept. While the present inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present teachings. Therefore, it should be understood that the above embodiments are not limiting, but illustrative.