Nonvolatile memory device and method of fabricating the same

This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove. The electric resistance of the pipe connection gate electrode may be greatly reduced without an increase in a substantial height by forming the metal silicide layer buried in the substrate under the pipe connection gate electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2012-0091116, filed on Aug. 21, 2012, which is incorporated herein by reference in its entirety.

BACKGROUND

Exemplary embodiments of the present invention relate to a nonvolatile memory device and a method of fabricating the same, and more particularly, to a three-dimensional (3D) structured nonvolatile memory device in which a plurality of memory cells are stacked in a vertical direction over a substrate and a method of fabricating the same.

2. Description of the Related Art

A nonvolatile memory device retains stored data although the power is not supplied. A variety of nonvolatile memory devices, such as flash memory, are being widely used.

As the improvement of the degree of integration of two-dimensional (2-D) structured nonvolatile memory devices with memory cells that are formed over a semiconductor substrate in the form of a single layer has reached the limit, there has been proposed a 3-D structured nonvolatile memory device in which a plurality of memory cells is formed along channel layers in a vertical direction over a semiconductor substrate. More particularly, the 3-D structured nonvolatile memory device is mainly divided into a structure having a straight-line type channel layer and a structure having a U-shaped channel layer.

In the structure having a U-shaped channel layer, a pipe connection transistor is used to couple memory cell strings. However, there is a concern in that electric resistance may increase, because the gate electrode of the pipe connection transistor (hereinafter referred to as a pipe connection gate electrode) is mainly made of polysilicon. In particular, an increase in the height of the pipe connection gate electrode to reduce the electric resistance of the pipe connection gate electrode may be limited in a subsequent process.

SUMMARY

Exemplary embodiments of the present invention are directed to a nonvolatile memory device in which the electric resistance of a pipe connection gate electrode may be greatly reduced without an increase in a substantial height, because a metal silicide layer is buried in a substrate under the pipe connection gate electrode and a method for fabricating the same.

In accordance with an embodiment of the present invention, a nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove.

In accordance with another embodiment of the present invention, a method of fabricating a nonvolatile memory device may include forming a groove by selectively etching a substrate, forming a metal silicide layer within the groove, forming a conductive layer for a gate electrode, in which has at least one or more sacrificial layer patterns, over a substrate in which the metal silicide layer is formed, and forming a pipe connection gate electrode by selectively etching the conductive layer for a gate electrode.

DETAILED DESCRIPTION

The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. It should be readily understood that the meaning of “on” and “over” in the present disclosure should be interpreted in the broadest manner such that not only means “directly on” something but also include the meaning of “on” something with an intermediate feature or a layer therebetween, and that “over” not only means the meaning of “over” something may also include the meaning it is “over” something with no intermediate feature or layer therebetween (i.e., directly on something).

FIGS. 1 to 19are cross-sectional views illustrating a nonvolatile memory device and a method of fabricating the same in accordance with embodiments of the present invention. In particular,FIG. 19is a cross-sectional view illustrating the nonvolatile memory device in accordance with an embodiment of the present invention, andFIGS. 1 to 18are cross-sectional views illustrating an example of intermediate process steps for fabricating the nonvolatile memory device ofFIG. 19.

Referring toFIG. 1, a first isolation insulating layer105is formed on a substrate100including a cell region C and a peripheral region P. The substrate100may be a semiconductor substrate, such as single crystalline silicon, and the substrate100may include specific underlying structures (not shown). Furthermore, the first isolation insulating layer105may include an oxide-based or nitride-based material.

A first hard mask pattern110through which part of a region where a pipe connection gate electrode to be described later will be formed is exposed is formed on the first isolation insulating layer105. A first groove G1is formed by etching the first isolation insulating layer105and the substrate100in the cell region C using the first hard mask pattern110as an etch mask.

The first hard mask pattern110may include one or more selected from the group that includes an oxide-based or nitride-based material, polysilicon an amorphous carbon layer (ACL), and a bottom anti-reflective coating (BARC) layer. In particular, the first groove G1is a space in which the bottom of the pipe connection gate electrode will be buried and may be separated by a block.

Referring toFIG. 2, a second isolation insulating layer115is formed on the entire surface of the substrate100in which the first groove G1is formed. The second isolation insulating layer115may be formed by depositing an oxide-based or nitride-based material using an atomic layer deposition (ALD) or chemical vapor deposition (CVD) method.

Referring toFIG. 3, a semiconductor layer120is formed on the second isolation insulating layer115. The semiconductor layer120includes a semiconductor material, such as silicon (Si) which may form a compound by a reaction with metal. The semiconductor layer120may be formed by depositing polysilicon, for example, to a thickness that fully fills the first groove G1using an ALD or CVD method.

Referring toFIG. 4, a polishing process, such as chemical mechanical polishing (CMP), is performed until a top surface of the first hard mask pattern110is exposed. The second isolation insulating layer115and the semiconductor layer120remaining within the first groove G1as a result of this process are hereinafter referred to as a second isolation insulating layer pattern115A and a semiconductor layer pattern120A, respectively.

Referring toFIG. 5, the first isolation insulating layer105is exposed by removing the first hard mask pattern110. In order to remove the first hard mask pattern110, an etch process using an etch selectivity with the second isolation insulating layer pattern115A and the semiconductor layer pattern120A may be performed.

Referring toFIG. 6, a metal layer125is formed on the entire surface of the substrate100including the semiconductor layer pattern120A. The metal layer125may be formed by depositing metal, for example, one or more selected from the group that includes cobalt (Co) tungsten (W), nickel (Ni), titanium (Ti), platinum (Pt), and palladium (Pd) which may form a compound by a reaction with a semiconductor material, such as silicon (Si).

Referring toFIG. 7, the substrate100in which the metal layer125is formed is annealed. The annealing process may be performed using a rapid thermal annealing (RTA) or furnace annealing method. As a result of this process, an upper part of the semiconductor layer pattern120A, that is in contact with the metal layer125, is silicided, thereby forming a metal silicide layer130.

The metal silicide layer130may include cobalt silicide (CoSix) tungsten silicide (WSix), nickel silicide (NiSix) titanium silicide (TiSix), platinum silicide (PtSix), or palladium silicide (PdSix). In particular, a region where the metal silicide layer130is formed may be limited within the first groove G1. Accordingly, the characteristics of a memory layer to be described later may not deteriorate, because the metal silicide layer130is formed.

Referring toFIG. 8, a strip process of removing the metal layer125remaining without a reaction in the annealing process is performed. In order to remove the remaining metal layer, a mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2), that is, a sulfuric acid and hydro-peroxide mixture (SPM) may be used. After the strip process, an additional annealing process may be performed.

Referring toFIG. 9, a first conductive layer135for gate electrodes is formed on the results in which the metal layer125is removed. The first conductive layer135for gate electrodes may be formed by depositing a conductive material, such as doped polysilicon, using an ALD or CVD method.

A second hard mask pattern140through which regions where sacrificial layer patterns to be described later will be formed are exposed is formed on the first conductive layer135for gate electrodes, Second grooves G2are formed by etching the first conductive layer135for gate electrodes in the cell region C using the second hard mask pattern140as an etch mask. The second hard mask pattern140may comprise one or more selected from the group that includes an oxide-based or nitride-based material, polysilicon, an ACL, and a BARC layer.

Referring toFIG. 10, after removing the second hard mask pattern140, sacrificial layer patterns145buried in the respective second grooves G2are formed. The sacrificial layer patterns145are removed in a subsequent process, thus functioning to provide spaces where pipe channel holes will be formed. The sacrificial layer patterns145may include a material having an etch rate different from an etch rate of a second conductive layer for gate electrodes, first material layers, second material layers, which will be described later, and the first conductive layer110for gate electrodes. Furthermore, each of the sacrificial layer patterns145may have an island form that has a long axis in the direction of the cross section ofFIG. 9and a short axis in a direction crossing the cross section ofFIG. 9. A plurality of the sacrificial layer patterns145may be arranged in a matrix form when seen from a plane parallel to the substrate100.

A second conductive layer150for gate electrodes is formed on the first conductive layer135for gate electrodes and the sacrificial layer patterns145. The second conductive layer150for gate electrodes may be formed by depositing a conductive material, such as doped polysilicon, using an ALD or CVD method.

Referring toFIG. 11, a third hard mask pattern155covering regions where a pipe connection gate electrode and peripheral gate electrodes to be described later will be formed is formed on the second conductive layer150for gate electrodes. Trenches T1through which the first isolation insulating layer105is exposed are formed by etching the second conductive layer150and the first conductive layer135using the third hard mask pattern155as an etch mask.

The third hard mask pattern155may include one or more selected from the group that includes an oxide-based or nitride-based material, polysilicon, an ACL, and a BARC layer. Meanwhile, the first conductive layers135for gate electrodes and the second conductive layers150for gate electrodes separated by the trenches T1are hereinafter referred to as first conductive layer patterns135A for gate electrodes and second conductive layer patterns150A for gate electrodes.

As a result of this process, the pipe connection gate electrode and the peripheral gate electrodes are formed in the cell region C and the peripheral region P, respectively. The pipe connection gate electrode and the peripheral gate electrodes have a form in which the first conductive layer patterns135A and the second conductive layer patterns150A are sequentially stacked. In particular, the pipe connection gate electrode may include the metal silicide layer130, which is in contact with the bottom of the first conductive layer pattern135A for gate electrodes, and the semiconductor layer pattern120A in the cell region C. Furthermore, the pipe connection gate electrode may be separated on a block basis.

Referring toFIG. 12, after removing the third hard mask pattern155, first burial insulating layers160are formed within the trenches T1. The first burial insulating layers160may be formed by depositing an oxide-based or nitride-based material to a thickness that fills the trenches T1and then performing a polishing process, such as chemical mechanical polishing (CMP), until a top surface of the second conductive layer patterns150A for gate electrodes is exposed.

Referring toFIG. 13, a plurality of first material layers165and a plurality of second material layers170are alternately stacked over the second conductive layer patterns150A for gate electrodes and the first burial insulating layers160. A structure in which the plurality of first material layers165and the plurality of second material layers170are alternately stacked is hereinafter referred to as a stack structure, for convenience of description. Meanwhile, the first material layers165may be disposed at the top and bottom of the stack structure. The cross section ofFIG. 13illustrates that the number of second material layers170is nine, but this is only illustrative. The number of second material layers170may be less than or greater than nine.

In the present embodiment, the first material layer165may be an interlayer insulating layer, and the second material layer170may be a sacrificial layer that is removed in a subsequent process, thus providing a space where a cell gate electrode will be formed. In this case, the first material layer165may include an oxide-based material, and the second material layer170may include a material having an etch rate different from an etch rate of the first material layer165, for example, a nitride-based material.

However, the present invention is not limited to the above examples. In another embodiment, the first material layer165may be an interlayer insulating layer, and the second material layer170may be a conductive layer for a cell gate electrode. In this case, the first material layer165may include an oxide-based material, and the second material layer170may include a conductive material, such as polysilicon. In yet another embodiment, the first material layer165may be a sacrificial layer that provides a space where an interlayer insulating layer will be formed, and the second material layer170may be a conductive layer for a cell gate electrode. In this case, the first material layer165may include undoped polysilicon, and the second material layer170may include a conductive material, such as doped polysilicon.

Referring toFIG. 14, pairs of main channel holes H1through which the sacrificial layer patterns145are exposed are formed by selectively etching the stack structure and the second conductive layer patterns150A for gate electrodes. Each of the main channel holes H1may have a circular or oval shape when viewed from a plane parallel to the substrate100, and each of the pairs of main channel holes H1may be placed in each of the sacrificial layer patterns145.

The sacrificial layer patterns145exposed by the pairs of main channel holes H1are removed. In order to remove the sacrificial layer patterns145, a wet etch process using an etch selectivity with the pipe connection gate electrode and the stack structure may be performed. As a result of this process, pipe channel holes H2, each coupling a pair of the main channel holes H1are formed in the respective spaces from which the sacrificial layer patterns145are removed.

Referring toFIG. 15, a memory layer175and a channel layer180are sequentially formed on the inner walls of the pairs of main channel holes H1and the pipe channel holes H2. The memory layer175may be formed by depositing a charge blocking layer, a charge trap layer, and a tunnel insulating layer sequentially.

The tunnel insulating layer is for charge tunneling and may include an oxide layer, for example. The charge trap layer is configured to store data by trapping charges, and the charge trap layer may include a nitride layer, for example. The charge blocking layer is configured to preclude charges within the charge trap layer from moving externally. The charge blocking layer may include an oxide layer, for example. That is, the memory layer175may have a triple structure of Oxide-Nitride-Oxide (ONO) layers.

Furthermore, the channel layer180may be formed by depositing a semiconductor material, such as polysilicon, and may be divided into a main channel layer within the main channel hole H1and a pipe channel layer within the pipe channel hole H2. In particular, the main channel layer may be used as the channel of a memory cell or a select transistor, and the pipe channel layer may be used as the channel of a pipe connection transistor. Meanwhile, in the present embodiment, the channel layer180is illustrated as being formed to a thickness that fully fills the main channel holes H1and the pipe channel holes H2, but the present invention is not limited thereto. In another embodiment, the channel layer180may be formed to a thickness that does not fully fill the main channel holes H1and the pipe channel holes H2.

Referring toFIG. 16, slits T2are formed by selectively etching the stack structure on both sides of each of the main channel holes H1. Each of the slits T2separates the first material layers165and the second material layers170of the cell region C in a line form. The slit T2may be extended in a direction crossing the cross section ofFIG. 16, and a plurality of the slits T2may be arranged in parallel. Meanwhile, as a result of this process, the first burial insulating layers160may be partially etched, and the separated first material layers165and the separated second material layers170are hereinafter referred to as first material layer patterns165A and second material layer patterns170A, respectively.

Referring toFIG. 17, the second material layer patterns170A of the cell region C exposed by the formation of the slits T2are removed. In order to remove the second material layer patterns170A, a wet etch process using an etch selectivity with the first material layer patterns165A may be performed.

Referring toFIG. 18, cell gate electrodes185are formed in the spaces from which the second material layer patterns170A are removed. The cell gate electrodes185may be formed by the following process.

First, a conductive layer (not shown) for the cell gate electrodes is formed to a thickness that fills the spaces from which the second material layer patterns170A are removed by conformably depositing a conductive material, such as metal or metal nitride, using an ALD or CVD method. The conductive layer for the cell gate electrodes is etched until the sides of the first material layer patterns165A are exposed, with the result that the conductive layer is separated for each layer, and the cell gate electrode185is formed between the first material layer patterns165A.

Next, second burial insulating layers190are formed within the slits T2. The second burial insulating layers190may be formed by depositing an oxide-based or nitride-based material to a thickness that fills the slits T2and then performing a polishing process, such as CMP, until a top surface of the first material layer patterns165A is exposed.

Referring toFIG. 19, a second interlayer insulating layer195is formed on the results in which the second burial insulating layers190are formed. The second interlayer insulating layer195may be formed by depositing an oxide-based or nitride-based material.

First contact plugs200, which are coupled with the respective channel layers180in the cell region C, configured to penetrate the second interlayer insulating layer195, are formed. Second contact plugs205, which are coupled with the junction (not shown) of the substrate100in the peripheral region P, configured to penetrate the second interlayer insulating layer195, the stack structure, the first burial insulating layer160, and the first isolation insulating layer105, are formed. The first and the second contact plugs200and205may include a conductive material, such as doped polysilicon, metal, or metal nitride.

In accordance with the above-described fabrication method, the nonvolatile memory device in accordance with the embodiment of the present invention, such as that shown inFIG. 19, may be fabricated.

Referring toFIG. 19, the nonvolatile memory device in accordance with the embodiment of the present invention includes the pipe connection gate electrode configured to have a bottom buried in the groove formed in the substrate100having the cell region C and the peripheral region P, the first isolation insulating layers105and the second isolation insulating layer pattern115A interposed between the pipe connection gate electrode and the substrate100, the channel layers180each configured to include one or more pipe channel layers formed within the pipe connection gate electrode and a pair of the main channel layers connected with the pipe channel layer and extended in a direction substantially perpendicular to the substrate100, the plurality of first material layer patterns165A and the plurality of cell gate electrodes185alternately stacked along the main channel layers, the memory layer175interposed between the cell gate electrodes185, the pipe connection gate electrode, and the channel layer180, the first contact plugs200connected to the top of the channel layers180, the peripheral gate electrodes over the first isolation insulating layers105in the peripheral region P, and the second contact plugs205connected with the substrate100on both sides of the peripheral gate electrodes.

Here, the pipe connection gate electrode may include the first and the second conductive layer patterns135A and150A for gate electrodes, the metal silicide layer130formed within the groove, and the semiconductor layer pattern120A configured to be in contact with the metal silicide layer130under the metal silicide layer130in the cell region C that is separated on a block basis. The peripheral gate electrode may include the first and the second conductive layer patterns135A and150A for gate electrodes in the peripheral region P.

Meanwhile, the channel layer180may have a U shape, and the memory layer175may surround the channel layer180. Furthermore, the cell gate electrodes185may surround the sides of the main channel layers and extend in a direction crossing the cross section ofFIG. 19. In particular, the substantial height of the pipe connection gate electrode may not be increased, because the bottom of the pipe connection gate electrode other than regions separated by a block is buried in the substrate100.

In accordance with the nonvolatile memory device and the method for fabricating the same in accordance with the embodiments of the present invention, the electric resistance of the pipe connection gate electrode may be greatly reduced without an increase in a substantial height by forming the metal silicide layer buried in the substrate under the pipe connection gate electrode.