Integrated circuit current mirror

An integrated current mirror circuit in which a compensation transistor is added in each stage of the mirror to compensate for the base-substrate leakage currents of the other transistors in the mirror circuit and to keep the circuit operative even at high temperatures and low current levels. Each compensation transistor is matched with the other transistors in its stage and has its collector-emitter circuit connected between a voltage source terminal and the common base connection of the other transistors. The base of each compensation transistor is unconnected to the remainder of the circuit but exhibits a base-substrate leakage current which is employed in the compensation scheme.

BACKGROUND OF THE INVENTION 
Field of the Invention 
This invention relates to integrated circuit current mirror circuits, and 
more particularly to current mirrors with means for compensating for the 
effects of current leakages to the circuit substrate. 
Description of the Prior Art 
It is often required, especially in bias current cancellation circuits, 
that very accurate low current sources be generated within an intergrated 
circuit. This is conventionally achieved by the use of a "current mirror" 
composed of lateral PNP transistors. A problem with this approach is that 
lateral PNP transistors of the standard bipolar type exhibit base leakage 
currents to the substrate which cause inaccuracies and even complete 
malfunction at high temperatures. 
A conventional type of current mirror circuit is shown in FIG. 1. A 
two-stage current mirror is shown, the second stage being employed to 
greatly increase the output impedance of the mirror in order to limit 
changes in output current with changes in output termination voltage. The 
first stage consists of a current reference transistor Q1 which is matched 
and has a common base connection with a pair of slave transistors Q2 and 
Q3. The second stage is formed in a similar manner, with a current 
reference transistor Q4 matched and having a common base connection with 
slave transistors Q5 and Q6. The collector-emitter circuits Q4, Q5 and Q6 
are connected respectively in circuit with the collector-emitter circuits 
of Q1, Q2 and Q3. 
An NPN current source transistor Q7 has its collector-emitter circuit 
connected to the collector of Q4, and is biased so as to produce a desired 
reference current I1 which is directed through Q4 and Q1. (With a single 
stage current mirror Q7 would be connected directly to Q1.) The emitters 
of first stage transistors Q1, Q2 and Q3 are all connected in common to a 
positive voltage source bus, while the collectors of Q5 and Q6 provide 
output currents I2 and I3 which mirror I1. The circuit is shown as having 
two outputs, but additional outputs could be added by providing additional 
slave transistor pairs in the same manner as Q2/Q5 and Q3/Q6. 
Current supply transistors Q8 and Q9 are provided respectively in the first 
and second stages to supply the base and leakage currents of the reference 
and slave transistors. With the exception of Q7, all of the transistors 
described are of the PNP type. The emitter of Q8 is connected to the 
common base connection of Q1, Q2, Q3, its collector is connected to a 
negative voltage supply terminal, and its base is connected to the 
collector of Q1; Q9 is similarly connected in the second stage of Q4, Q5 
and Q6. 
In the integrated circuit implementation of bipolar transistors such as 
Q1-Q9 on a substrate, each of the transistors is characterized by a 
base-to-substrate leakage current (I.sub.L). Neglecting the leakage 
currents and the base currents of Q8 and Q9, and assuming that Q1-Q6 are 
identical (i.e., that they have the same current gain and base-emitter 
voltage at a given current), then the collector current of Q4 will be 
equal to I1, and the collector current of Q1 will be equal to I1 (1+1/b), 
where b is the PNP current gain. Since Q1, Q2 and Q3 are identical, Q2 and 
Q3 will also have collector currents equal to I1 (1+1/b). Q4, Q5 and Q6 
are also identical, so that their collector currents are also equal; 
hence, I1=I2=I3. 
The presence of Q8 and Q9 causes a small error in the current matching 
between the slave and reference transistors. However, this error is 
inversely proportional to b.sup.2, and with a typical b of about 50 for 
PNP transistors can be neglected. A more serious problem occurs due to the 
base-substrate leakage of the PNP transistors, modeled as I.sub.L current 
sources in FIG. 1. At low temperatures this leakage current may be only a 
few picoamps and unlikely to cause problems, but at high temperatures of 
about 125.degree. C. I.sub.L is about 1 to 2 nanoamps. 
The emitter current of Q8 is equal to the combined base currents of Q1, Q2 
and Q3, while the emitter current of Q9 is equal to the combined base 
currents of Q4, Q5 and Q6, or about 3 I.sub.1 /b in both cases. Since 
there are 3 base-substrate current leakages at the emitters of Q8 and Q9, 
the emitter currents of those transistors become negative if the leakage 
current is greater than I.sub.1 /b. This turns Q8 and Q9 off, and the 
current mirror no longer functions. In this event the output currents I2 
and I3 are approximately equal to bI.sub.L, and are not controlled by I1. 
Taking typical values for I.sub.L of 2 nanoamps and for b of 50, this 
turn-off situation occurs when I1 is less than 100 nanoamps. 
Even if Q8 and Q9 do not turn off, their base leakage currents will cause 
errors at the collectors of reference current transistors Q1 and Q4. The 
overall error in I2 and I3 will be about 2I.sub.L /I1, or about 4% when 
I.sub.L equals 2 nanoamp and I1 equals 100 nanoamps. The base leakage 
current of current source Q7 introduces a further error. 
SUMMARY OF THE INVENTION 
In view of the above problems associated with the prior art, it is an 
object of this invention to provide a novel and improved current mirror 
circuit which alleviates the prior art problem of current supply 
transistor turn-off at high temperatures. 
Another object is the provision of a novel and improved current mirror 
circuit capable of compensating for the base-substrate leakage currents of 
the current supply transistors. 
Another object is the provision of such a current mirror circuit which also 
compensates for the base-substrate current leakage of the NPN current 
source transistor. 
In the realization of these objects, a bipolar compensation transistor is 
connected in each stage of a conventional current mirror circuit with its 
collector-emitter circuit connected between the voltage supply terminal 
for the other stage transistors, and the common base connection of those 
transistors. The base of the compensation transistor is unconnected to the 
remainder of the current mirror circuit, and provides a leakage current to 
the substrate. The compensation transistor is matched with the other 
transistors in the current mirror so that its collector-emitter current 
supplied to the common base connection of the reference and slave 
transistors is of sufficient magnitude to maintain the current supply 
transistor in a conductive state, independent of the current through the 
reference and slave transistors. 
When the compensation transistor is substantially identical to the current 
supply transistor, it supplies a current to the latter transistor which 
substantially compensates for that transistor's base leakage current. The 
base area of the compensation transistor can also be increased by an 
amount substantially equal to the collector area of the NPN current source 
transistor to provide an additional compensation current which compensates 
for the NPN transistor's collector-leakage current.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT 
FIG. 2 is a schematic diagram of an integrated circuit current mirror 
circuit which incorporates the present invention. The basic elements of 
this two-stage current mirror, comprising reference current transistors Q1 
and Q4, slave transistors Q2, Q3, Q5 and Q6, current source transistor Q7 
and current supply transistors Q8 and Q9, are the same as in the prior art 
current mirror circuit depicted in FIG. 1, and are identified by the same 
reference numerals. In addition, the circuit of FIG. 2 shows a unique way 
of alleviating the problems of both current supply transistor turn-off at 
high temperatures, and of errors due to the base-substrate leakage 
currents of the current supply transistors. The solution of these problems 
requires the addition of only two extra transistors, one for each stage of 
the mirror. Bipolar PNP transistor Q10 is added to the first stage and is 
matched with the other transistors Q1, Q2, Q3, Q8 of that stage, while 
bipolar PNP transistor Q11 is added to the second stage and is matched 
with the other transistors Q4, Q5, Q6, Q9 of that stage. Q10 has its 
emitter connected to the positive voltage supply terminal and its 
collector connected to the common base connection of Q1, Q2 and Q3. Its 
base is unconnected to the remainder of the current mirror circuit, but 
exhibits the same leakage current I.sub.L as the other transistors in the 
stage. Similarly, the emitter of Q11 is connected to the positive voltage 
supply terminal, while its collector is connected to the common base 
connection of Q4, Q5 and Q6. The base of Q11 is also unconnected to the 
remainder of the current mirror circuit, and also exhibits a 
base-substrate leakage current I.sub.L. 
Due to the matching with the other transistors, the collector currents of 
Q10 and Q11 are equal to bI.sub.L, where b is the common current gain 
characteristic of all the PNP transistors. The collector currents of Q10 
and Q11 flow through the common base connections of their respective 
stages and into the emitters of Q8 and Q9, respectively. Q8 and Q9 already 
support the base currents and the base-substrate leakage currents of Q1, 
Q2, Q3 and Q4, Q5, Q6, respectively. These currents may be expressed as 
-3I.sub.L +3I1/b for each transistor. The addition of the collector 
currents of Q10 and Q11 brings the emitter currents of Q8 and Q9 to 
bI.sub.L -3I.sub.L +3I1/b. If b is greater than 3, which is almost always 
the case, the emitter currents of Q8 and Q9 remain positive independent of 
I1 or I.sub.L, preventing Q8 and Q9 from turning off. This effectively 
solves the turn-off problem described above. 
Since the (-3I.sub.L +3I1/b) components of the Q8 and Q9 emitter currents 
are generally small compared to the bI.sub.L current component from 
compensation transistors Q10 and Q11, the base currents of Q8 and Q9 are 
approximately equal to bI.sub.L /b, or I.sub.L. This current is of the 
same magnitude but opposite polarity to the base-leakage currents at the 
bases of Q8 and Q9. A first order cancellation of those base-leakage 
currents is thus achieved. The addition of compensation transistors Q10 
and Q11 thus resolves to a great extent both the current supply transistor 
turn-off and base-substrate leakage current error problems. The described 
circuit has been found to be capable of operating with currents below 10 
nanoamps at a temperature of 125.degree. C. without encountering the 
turn-off problem. 
Additional current outputs can be generated in the circuit of FIG. 2 by 
adding transistor pairs connected in a similar manner to Q2/Q5 and Q3/Q6. 
A practical limit is reached, however, when the emitter currents of Q8 and 
Q9 become high enough for their base currents to produce a significant 
error. 
The above circuit can also significantly reduce an error factor associated 
with NPN current source transistor Q7. Reference current I1 is generated 
at the collector of Q7, but Q7 will have its own substrate leakage current 
which is added to the collector current of Q4, causing an error. This 
error can be compensated by increasing the base area of Q11 by an amount 
equal to the collector area of Q7. This adds an extra I.sub.L to the base 
current of Q9 which approximately cancels the leakage current of Q7. 
While a specific embodiment of the invention has been shown and described, 
numerous variations and modifications thereof will occur to those skilled 
in the art. For example, the invention is applicable to a single stage 
current mirror as well as the two-stage mirror described. Accordingly, it 
is intended that the invention be limited only in terms of the appended 
claims.