Non-planar MOS structure with a strained channel region

An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.

FIELD

Embodiments of the invention relate to a transistor structure and in particular to a non-planar transistor structure that incorporates a strained channel.

BACKGROUND

Traditional planar metal oxide semiconductor (MOS) transistor technology is approaching fundamental physical limits for certain transistor features past which it will be necessary to employ alternate materials, processing techniques, and/or transistor structure to support continued transistor performance improvement according to Moore's Law.

One such paradigm shift is a non-planar MOS structure. One particular non-planar MOS structure is a non-planar tri-gate transistor. A tri-gate transistor employs a three-dimensional gate structure that permits electrical signals to conduct along the top of the transistor gate and along both vertical sidewalls of the gate. The conduction along three sides of the gates enables, among other improvements, higher drive currents, faster switching speeds, and shorter gate lengths, simultaneously increasing the performance of the transistor while occupying less substrate area versus a planar MOS structure. The tri-gate structure further decreases the amount of current leakage, a problem to which ever shrinking planar MOS devices are prone, by improving the short channel characteristics of the transistor.

Another paradigm shift involves using strained semiconductor material for various portions of a transistor. Adding tensile or compressive strain to a semiconductor (depending on the particular application) lattice increases the carrier mobility within the strained semiconductor. In particular, for an NMOS device imparting tensile strain to a semiconductor increases the electron mobility (i.e., dominant charge carrier in an NMOS device). The increased carrier mobility in turn allows for higher drive current and corresponding faster switching speeds.

DETAILED DESCRIPTION

Embodiments of a non-planar MOS transistor structure with a strained channel region will be described. Reference will now be made in detail to a description of these embodiments as illustrated in the drawings. While the embodiments will be described in connection with these drawings, there is no intent to limit them to drawings disclosed herein. On the contrary, the intent is to cover all alternatives, modifications, and equivalents within the spirit and scope of the described embodiments as defined by the accompanying claims.

Simply stated, an embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length, gate width, and operating voltage versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.

FIG. 1illustrates a cross section of a silicon on insulator (SOI) substrate. SOI substrates are well known in the art to increase transistor performance by, among other features, reducing the capacitance that develops in a junction capacitance layer between impurity layers (e.g, impurity doped source and drain regions of a planar MOS structure) and a substrate. For example, in an embodiment, substrate100comprises silicon. Atop substrate100is a buried oxide101. In an embodiment, the buried oxide comprises silicon dioxide. Atop the buried oxide101is silicon102. Commercially available, the SOI substrates generally include silicon102layers that are approximately 500 angstroms thick. An embodiment, to further reduce the junction capacitance area, planarizes and polishes (e.g., by chemical mechanical polishing or CMP) the silicon102to approximately between 20 and 100 angstroms. It is to be understood, however, that the SOI combination of substrate100, buried oxide101and silicon102may also be prepared by separation by implanted oxygen (SIMOX), bonded and etched back (BESOI) or hydrogen implant before BESOI process (Smart Cut) as is understood in the art.

FIG. 2illustrates the substrate100cross section ofFIG. 1including strained silicon germanium201and silicon202prior to Smart Cut transfer of each to silicon201as is well known in the art and has been developed by SOITEC. A particular application of the Smart Cut method involves growing a layer of strained silicon germanium201on silicon202as a separate substrate that includes a large sacrificial silicon202layer as illustrated byFIG. 2. A high dose (i.e., 1017/cm2) of hydrogen is implanted to a depth either in the silicon202adjacent to the strained silicon germanium201or to a depth within the silicon germanium layer201as illustrated by hydrogen implant203(shown deposited within silicon202). The separate substrate comprised of silicon202and strained silicon germanium201is brought into contact with the substrate100that includes buried oxide101and silicon102. In particular, the surfaces of silicon102and strained silicon germanium201are joined by chemical hydrophobic bonding after a high temperature anneal. Said differently, the strained silicon germanium201bonds by covalent forces to the silicon102. In an embodiment, the anneal is approximately between 800° C. and 900° C. for approximately 1 hour. The anneal further produces, based on the high dose hydrogen implant203in silicon202, an in-depth weakened layer of silicon202. As the bonding forces between the silicon102and strained silicon germanium201are stronger than what the in-depth hydrogen implant203weakened region of silicon202can support, the sacrificial portion of silicon202(or of silicon germanium201and silicon202if the hydrogen implant203resides in the silicon germanium201) can be cleaved, leaving behind the structure illustrated byFIG. 3. In an embodiment, the remaining silicon202(or silicon germanium201) may be chemically mechanically polished to form a suitable silicon202(or silicon germanium201) surface for subsequent processing steps.

Silicon and germanium have the same lattice structure; however, the lattice constant of germanium is 4.2% greater than the lattice constant of germanium (the lattice constant of silicon is 5.43 angstroms while the lattice constant of germanium is 5.66 angstroms). A silicon germanium alloy Si1-x,Gexx=0.0 to 1.0, has a monotonically increasing lattice constant a x increases from 0.0 to 1.0. Depositing a thin layer of silicon over silicon germanium produces, as the underlying silicon germanium lattice structure coerces the lattice thinly deposited layer of silicon, a silicon layer with tensile strain as the smaller silicon lattice aligns with the larger silicon germanium lattice. Similarly, a thin silicon germanium layer can be grown with compressive strain on a layer of silicon. However, as the deposited layers of strained materials thicken, they tend to relax to their intrinsic lattice structure.

FIG. 4illustrates the substrate100cross section ofFIG. 3following a high temperature, long duration anneal. In an embodiment, the anneal is approximately between 800° C. and 1100° C. for approximately 1 second to 3 hours. In an anneal of an embodiment, the temperature is approximately 1000° C. and the duration is approximately 2 hours. During the high temperature, long duration anneal, the germanium in the strained silicon germanium201diffuses into the silicon102and silicon202. As the germanium diffuses to an approximate constant concentration throughout the strained silicon201, silicon102, and silicon202, it forms relaxed silicon germanium401. No longer compressively strained by adjacent silicon, the lattice constant of the relaxed silicon germanium401increases based on the germanium concentration in the relaxed silicon germanium401. In an embodiment, the relaxed silicon germanium401has a germanium concentration range of approximately 5% to 80% (i.e., approximately 5% to 80% of the silicon lattice sites are occupied by germanium). In an embodiment, the relaxed silicon germanium401has a germanium concentration approximately 15%. The relaxed silicon germanium401may, based on the pre-anneal doping of silicon102, strained silicon germanium201, silicon202, or a combination thereof (or in an embodiment, a separate relaxed silicon germanium401doping process) may be p-doped with any p-dopant known in the art. The p-dopant concentration level of a relaxed silicon germanium401embodiment may be approximately between undoped and 6*1019/cm3. In an embodiment, the p-type dopant concentration level of relaxed silicon germanium401is approximately 1017/cm3.

FIG. 5illustrates a cross section of the substrate100ofFIG. 4following the lithographic patterning of the relaxed silicon germanium401to form a relaxed silicon germanium fin501. The relaxed silicon germanium fin501may be patterned by any method known in the art to pattern silicon germanium. In an embodiment, the relaxed silicon germanium fin is patterned by any dry silicon etch process known in the art. Following the lithographic patterning, relaxed silicon germanium fin501of an embodiment has an approximately rectangular cross section as the lithographic patterning is substantially anisotropic and creates substantially vertical relaxed silicon germanium fin501sidewalls. In a further embodiment, though not illustrated, the relaxed silicon germanium fin501has a substantially trapezoidal cross section, with its top surface spanning a smaller lateral distance than its base adjacent to the buried oxide101. For both the substantially rectangular and substantially trapezoidal embodiments, the relaxed silicon germanium fin501comprises a top and two sidewalls whose width and height dimensions are approximately between 25% and 100% of the transistor gate length, and can have any shape from substantially tall and thin to substantially short and wide. In yet further embodiments, also not illustrated, the relaxed silicon germanium fin501has other geometrical cross sections that may include additional sidewalls or may be substantially hemispherical.

FIG. 6illustrates a cross section of the substrate100ofFIG. 5following the deposition of strained silicon601. As noted above, the lattice constant of the relaxed silicon germanium fin501is larger than the lattice constant of silicon. When a thin layer of silicon is formed atop the relaxed silicon germanium fin501, provided the silicon has a sufficiently small thickness, the silicon lattice will align with the relaxed silicon germanium fin501lattice to form strained silicon601. As the relaxed silicon germanium fin501lattice constant is larger than that of silicon, the subsequently formed strained silicon601exhibits tensile strain as the smaller silicon lattice stretches to conform with the relaxed silicon germanium fin501lattice. As noted, the tensile strain increases the carrier mobility in the strained silicon601that comprises the channel region of a non-planar MOS transistor of an embodiment.

Strained silicon601can be deposited by any method known in the art to deposit crystalline silicon. In an embodiment, the strained silicon601is deposited with selective epitaxy such that the silicon grows only on the surface of the relaxed silicon germanium fin401and not on the surface of the buried oxide101exposed during the pattering of relaxed silicon germanium fin501. For example, in an embodiment a low pressure chemical vapor deposition process of an embodiment utilizes silane (SiH4), disilane (Si2H4), dichlorol silane (SiH2Cl2), and trichlorol silane (SiHCl3) as a silicon source and HCL as an etching gas for selective growth. In an embodiment, the pressure of the deposition chamber is approximately between 500 millitorr and 500 torr, the temperature of the substrate 100 is approximately between 400° C. and 1100° C., and the total precursor gas flow rate is approximately between 10 sccm and 1000 sccm. It is to be understood that the deposition conditions may vary depending on the size of the deposition chamber. It is to be further understood that the epitaxial deposition forms substantially a single crystal stained silicon601.

In an embodiment, the strained silicon601is doped with a p-type dopant. In an embodiment the p-type dopant concentration level of strained silicon601ranges from approximately undoped to 6*1019/cm3. It is to be understood that the strained silicon601may be doped by any doping method known in the art. In particular, the strained silicon601may be doped in situ during its deposition by incorporating dopant precursors in the low pressure chemical deposition process of an embodiment. The strained silicon601may alternatively be doped by out diffusion or implant.

As noted, the cross section of the relaxed silicon germanium fin501of an embodiment has a top and two sidewalls. It is important to note that the strained silicon601be deposited on the top and on both sidewalls of relaxed silicon germanium fin501with substantially uniform thickness for each surface. The strained silicon601of an embodiment on the top and sidewalls has a substantially uniform thickness of approximately between 2 nanometers and 10 nanometers In an embodiment, the strained silicon601thickness is approximately between 4 and 5 nanometers. In an embodiment, the strained silicon601thickness permits deeply depleted or fully depleted channel conditions as is understood in the art.

FIG. 7illustrates a cross section of the substrate100ofFIG. 6following the deposition of a gate dielectric701and gate702to illustrate a non-planar, tri-gate transistor cross section. In an embodiment, gate dielectric701comprises silicon dioxide. In a further embodiment, gate dielectric701comprises a high dielectric constant material like hafnium oxide, hafnium silicate, lanthanum oxide, lanthanum aluminate, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantanate, or lead zinc niobate. The gate dielectric701may be deposited my any method known in the art to deposit a gate dielectric701material.

In an embodiment, the gate dielectric701deposition is a blanket deposition. Following the deposition of gate dielectric701, a gate702is deposited. In an embodiment the gate702comprises polysilicon, polysilicon with a layer of metal at the high-k gate dielectric701interface, or a complete metal gate. In an embodiment, the gate702deposition is a blanket deposition. In an embodiment for which the gate dielectric701and gate702depositions are blanket depositions, each is etched to expose areas of strained silicon601that will thereafter form the source and drain of the tri-gate non-planar transistor of an embodiment. Of note is that the gate702and underlying gate dielectric701of an embodiment extend over all sides (in an embodiment, the top and both sidewalls) of the relaxed silicon germanium fin501including strained silicon601formed thereon.

In an alternate embodiment (not illustrated), the gate702is only adjacent to the sidewalls of the relaxed silicon germanium fin501and does not extend across the top of the relaxed silicon germanium fin501. The strained silicon601may be formed over the entire exposed surface (i.e., top and both sidewalls) of the relaxed silicon germanium fin501or may just be formed on the two sidewalls of the silicon germanium fin501. Similarly, the gate dielectric701may be formed over the entire exposed surface (i.e., top and both sidewalls) of the strained silicon601formed atop the relaxed silicon germanium fin501or may just be formed on the two sidewalls of strained silicon601. With such an arrangement, the non-planar transistor of an embodiment resembles a FinFET including strained silicon601channel regions.

FIG. 8is an illustration of a perspective view of the substrate100ofFIG. 7including buried oxide101, relaxed silicon germanium fin501, strained silicon601, gate dielectric701and gate702. In an embodiment, the blanket deposition of gate dielectric701and gate702have been etched to expose the relaxed silicon germanium fin501as described above. It is to be understood that one relaxed silicon germanium fin501can operate for many gates702and one gate702may operate with many relaxed silicon germanium fins501to create an array of non-planar, tri-gate MOS transistors.

FIG. 9is an illustration of the perspective view ofFIG. 8including an implant901to form a source902and a drain903. Well known in the art to form a source and drain for a MOS transistor, the implant901(e.g., an n-type dopant implant for an NMOS device) further decreases the contact resistivity between both the source902and drain903with subsequently fabricated metal contacts to improve the performance of the non-planar, tri-gate MOS transistor of an embodiment.

The resulting structure of an embodiment is a non-planar, tri-gate MOS transistor that includes a strained silicon601channel. As noted, the tensile strain on the strained silicon601lattice increases the electron and hole mobility within the strained silicon601lattice to fabricate an NMOS device with improved performance characteristics. Further, in an embodiment, the strained silicon601thickness permits deeply depleted or fully depleted conditions to mitigate leakage current while the NMOS device is in an off state (i.e., enhancement mode with zero gate voltage).

One skilled in the art will recognize the elegance of an embodiment as it combines a non-planar MOS transistor structure with a strained channel material to improve transistor performance.