Method for manufacturing thin film transistor display array with dual-layer metal line

A method for manufacturing a thin film transistor (“TFT”) array includes providing a substrate, a patterned first metal layer on the substrate including a plurality of first conductive lines and a plurality of second conductive lines disposed orthogonal to the first conductive lines, an insulating layer over the patterned first metal layer, a patterned silicon layer, a patterned passivation layer over the patterned silicon layer, and a patterned doped silicon layer and a patterned second metal layer over the patterned passivation layer, filling exposed portions of the patterned silicon layer and exposed portions of the first conductive lines and the second conductive lines, where the patterned second metal layer includes a plurality of third conductive lines and a plurality of fourth conductive lines, each of which corresponding respectively to one of the plurality of first conductive lines and the plurality of second conductive lines.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. 10/687,759, filed Oct. 20, 2003 and U.S. patent application Ser. No. 11/131,084, filed May 17, 2005, each of which being incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION

The present invention relates generally to thin film transistors (“TFTs”), and more particularly, to a method for manufacturing TFT arrays.

With the progress in semiconductor manufacturing techniques, the panel size of flat panel display devices such as liquid crystal display (“LCD”) devices has been increasing rapidly. As a result, the conductive lines in a flat panel device have gained a considerable increase in length, adversely resulting in an undesirable resistor-capacitor (“RC”) delay. Such an RC delay may severely impact the performance of the flat panel device. For LCD TVs having a 37-inch or greater panel size, the RC delay within the scan lines has been found to adversely affect the display quality. One of conventional methods to address the RC delay issue proposes a two-sided driving scheme, wherein both sides of a panel are provided with drivers in order to offset or alleviate the RC delay. However, this method requires additional driving integrated circuits (“ICs”), and in turn the additional cost for packaging these ICs. Consequently, it is desirable to have a method for manufacturing TFT arrays that is able to reduce RC delay in the conductive lines in the TFT arrays without compromising the driving scheme.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to a method for manufacturing thin film transistor (“TFT”) arrays including dual-layer conductive lines that obviate one or more problems resulting from the limitations and disadvantages of the prior art.

In accordance with an embodiment of the present invention, there is provided a method for manufacturing a thin film transistor (“TFT”) array that comprises providing a substrate, forming a patterned first metal layer on the substrate, the patterned first metal layer including a plurality of first conductive lines and a plurality of second conductive lines disposed orthogonal to the first conductive lines, each of the first conductive lines including a plurality of gate electrodes, each of the gate electrodes being disposed near an intersection of one of the first conductive lines and one of the second conductive lines, forming an insulating layer over the patterned first metal layer, forming a patterned silicon layer, forming a patterned passivation layer over the patterned silicon layer and the patterned first metal layer, exposing portions of the patterned silicon layer and a portion of each one of the first conductive lines and each one of the second conductive lines, and forming a patterned doped silicon layer and a patterned second metal layer over the patterned passivation layer, filling the exposed portions of the patterned silicon layer and the exposed portions of the first conductive lines and the second conductive lines, the patterned second metal layer including a plurality of third conductive lines and a plurality of fourth conductive lines, each of which corresponding respectively to one of the plurality of first conductive lines and one of the plurality of second conductive lines.

Also in accordance with the present invention, there is provided a method for manufacturing a thin film transistor (“TFT”) array that comprises providing a substrate, forming a patterned first metal layer on the substrate, the patterned first metal layer including a plurality of first conductive lines and a plurality of second conductive lines disposed orthogonal to the first conductive lines, each of the first conductive lines including a plurality of gate electrodes, each of the gate electrodes being disposed near an intersection of one of the first conductive lines and one of the second conductive lines, forming an insulating layer over the patterned first metal layer, forming a patterned silicon layer, forming a patterned passivation layer over the patterned silicon layer and the patterned first metal layer, exposing portions of the patterned silicon layer and portions of each of the first conductive lines and the second conductive lines, doping impurity into the exposed portions of the patterned silicon layer, and forming a patterned second metal layer over the patterned passivation layer, filling the exposed portions of patterned silicon layer and the exposed portions of the first conductive lines or second conductive lines, the patterned second metal layer including a plurality of third conductive lines and a plurality of fourth conductive lines, each of which corresponds respectively to one of the plurality of first conductive lines and one of the plurality of second conductive lines of the patterned first metal layer.

Further in accordance with the present invention, there is provided a method for manufacturing a thin film transistor (“TFT”) array that comprises providing a substrate, forming a patterned first metal layer on the substrate, the patterned first metal layer including a plurality of first conductive lines and a plurality of second conductive lines disposed orthogonal to the first conductive lines, each of the second conductive lines including a plurality of branch lines separated from each other, forming an insulating layer over the patterned first metal layer, forming a patterned silicon layer over the insulating layer, exposing portions of each of the first conductive lines and the branch lines of each of the second conductive lines of the patterned first metal layer, forming a patterned second metal layer over the patterned silicon layer, filling the exposed portions of each of the first conductive lines and the exposed branch lines of each of the second conductive lines, the patterned second metal layer including a plurality of third conductive lines and a plurality of fourth conductive lines, each of which corresponding respectively to one of the plurality of first conductive lines and one of the plurality of second conductive lines of the patterned first metal layer.

Additional features and advantages of the present invention will be set forth in portion in the description which follows, and in portion will be obvious from the description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1A to 1Jare diagrams illustrating a method for manufacturing a thin film transistor (“TFT”) array in accordance with a first embodiment of the present invention.FIG. 1Ais a cross-sectional view along the direction AA of a top view illustrated inFIG. 1B. Referring toFIG. 1A, a substrate10, made of glass or resin, for example, is provided. Preferably the thickness of the substrate10ranges from approximately 0.3 to 0.7 mm (millimeter) but could be thinner or thicker. Next, a patterned first metal layer11is formed on the substrate10by forming a layer of first metal on the substrate10by, for example, a conventional physical vapor deposition (“PVD”), sputtering or some other suitable process, followed by a conventional patterning and etching process, using a first mask. Referring toFIG. 1B, the patterned first metal layer11includes a plurality of first conductive lines11-1substantially in parallel with each other, and a plurality of second conductive lines11-2substantially orthogonal to the first conductive lines11-1. Each of the first conductive lines11-1includes gate electrodes11-3. Each of the gate electrodes11-3is disposed near an intersection of one of the first conductive lines11-1and one of the second conductive lines11-2. Suitable materials for the first metal layer include but are not limited to TiAlTi, MoAlMo, CrAlCr, MoW, Cr and Cu. Preferably, the thickness of gate electrodes11-1ranges from approximately 1000 to 2000 Å (angstrom) but could be some other thickness. Each of the first conductive lines11-1eventually becomes a main line of a dual-layer wire, and each of the second conductive lines11-2eventually becomes branch lines of a dual-layer wire. A dual-layer or multi-layer wire structure has been disclosed in U.S. patent application Ser. No. 10/687,759, filed Oct. 20, 2003 and U.S. patent application Ser. No. 11/131,084, filed May 17, 2005, which are herein incorporated by reference.

Referring toFIGS. 1C and 1D, an insulation layer13is formed on the patterned first metal layer11by, for example, a conventional chemical vapor deposition (“CVD”) process or some other suitable process. Suitable materials for the insulation layer13include silicon nitride, silicon oxide and silicon oxynitride. Preferably, the thickness of the insulation layer13ranges from approximately 2500 to 4000 Å. Next, a patterned silicon layer14is formed on the insulation layer13by forming a layer of silicon by, for example, a conventional CVD or some other suitable process, followed by a conventional patterning and etching process, using a second mask. The patterned silicon layer14defines an active region disposed over each of the gate electrodes11-1. The patterned silicon layer14comprises an amorphous silicon layer or a polycrystalline silicon layer. Preferably, the thickness of the patterned silicon layer14ranges from approximately 500 to 3000 Å but could be other thickness.

Referring toFIGS. 1E and 1F, a patterned passivation layer15is formed over the insulation layer13and the patterned silicon layer14by forming a layer of insulating material such as oxide or nitride by, for example, a conventional CVD process or other suitable process followed by a conventional patterning and etching process, using a third mask. The patterned passivation layer15exposes the first conductive lines11-1, the second conductive lines11-2and the patterned silicon layer14through trenches16-1,16-2and16-3, respectively. Each of the active regions is formed with a pair of trenches16-3, which define a source region and a drain region for a corresponding TFT transistor Preferably, the thickness of the patterned passivation layer15ranges from approximately 3000 to 5000 Å.

Each of the trenches16-1disposed over one of the first conductive lines11-1is separated from an adjacent trench16-1disposed over the same one conductive line by a distance denoted as “a”. In the first embodiment, the ratio of a length “b” of a trench to the distance “a” ranges from approximately 2 to 20. Likewise, each of the trenches16-2disposed over one of the second conductive lines11-2is separated from an adjacent trench16-2disposed over the same one second conductive line16-2by a distance denoted as “p”. In the first embodiment, the ratio of a length “q” of the trench16-2to the distance “p” ranges from approximately 2 to 20.

Referring toFIGS. 1G and 1H, a patterned doped silicon layer17and a patterned second metal layer18are formed over the patterned passivation layer15, filling the trenches16-1,16-2and16-3. The patterned silicon layer17and patterned second metal layer18are formed by forming a layer of heavily-doped n-type (n+) silicon by, for example, a conventional CVD process and then forming a layer of second metal on the n+ silicon layer by, for example, a conventional PVD process, followed by a conventional patterning and etching process, using a fourth mask. Suitable materials for the second metal layer include but are not limited to TiAlTi, MoAlMo, CrAlCr, MoW, Cr and Cu. Preferably, the thickness of the patterned doped silicon layer17is approximately 500 Å but could be other thicker or thinner. Preferably, the thickness of the patterned second metal layer18ranges from approximately 1000 to 3000 Å.

The patterned second metal layer18includes a plurality of third conductive lines18-1and a plurality of fourth conductive lines18-2orthogonal to the third conductive lines18-1. Each of the third conductive lines18-1eventually becomes a branch line of a dual-layer wire, and each of the fourth conductive lines18-2eventually becomes a main line of a dual-layer wire. The third conductive lines18-1of the patterned second metal layer18are electrically connected to the first conductive lines11-1of the patterned first metal layer11through the trenches16-1to form a dual-layer wire, i.e., a dual-layer scan line for the TFT array. The fourth conductive lines18-2of the patterned second metal layer18are electrically connected to the second conductive lines11-2of the patterned first metal layer11through the trenches16-2to form a dual-layer wire, i.e., a dual-layer data line for the TFT array. The ratio of the length of a branch line corresponding to a main line to the distance between the branch line and an immediately adjacent branch line corresponding to the same main line ranges from approximately 2 to 20.

Referring toFIGS. 1I and 1J, a patterned pixel electrode layer19is formed by forming a layer of conductive material, for example, indium tin oxide (“ITO”) over the patterned second metal layer18and the patterned passivation layer15by a conventional PVD process followed by a conventional patterning and etching process, using a fifth mask. The patterned pixel electrode layer19serves as pixel electrodes for the TFT array. Preferably, the thickness of the patterned conductive layer ranges from approximately 500 to 1000 Å.

FIG. 2is a cross-sectional diagram illustrating a method for manufacturing a TFT array in accordance with a second embodiment of the present invention. Referring toFIG. 2, also referring toFIGS. 1A to 1E, a first mask is used to define the patterned first metal layer11. Next, a layer of insulating material13is formed over the patterned first metal layer11. A second mask is used to define the patterned silicon layer14. A passivation layer15is formed over the patterned silicon layer14and insulating material13. A patterned pixel electrode layer29such as an ITO layer is formed on the passivation layer by a conventional PVD process followed by a conventional patterning and etching process, using a third mask. Then, the passivation layer15is patterned by performing a conventional patterning and etching process, using a forth mask, exposing portions of the patterned silicon layer14and portions of the patterned first metal layer11-1and11-2. Subsequently, the patterned n+ silicon layer17and the patterned second metal layer18are formed over the patterned pixel electrode layer29and the patterned passivation layer15, using a fifth mask.

Alternatively, referring toFIG. 2and alsoFIGS. 1A to 1E, first, second and third masks may be used to define the patterned first metal layer11, the patterned silicon layer14and the patterned passivation layer25, respectively. A patterned pixel electrode layer29is formed over the patterned passivation layer25by forming a layer of conductive material such as ITO by a conventional PVD process followed by a conventional patterning and etching process, using a fourth mask. Subsequently, the patterned n+ silicon layer17and the patterned second metal layer18are formed over the patterned pixel electrode layer29and the patterned passivation layer25, using a fifth mask.

FIG. 3is a schematic diagram illustrating a method for manufacturing a TFT array in accordance with a third embodiment of the present invention. Referring toFIG. 3, a patterned first metal layer31includes a plurality of first conductive lines31-1and a plurality of second conductive lines31-2. Instead of a single, continuous trench such as the trench16-2illustrated inFIG. 1F, a plurality of contact holes36-2are formed in each of the second conductive lines31-2between two adjacent first conductive lines31-1. Likewise, a plurality of contact holes36-1may be formed in each of the first conductive lines31-1between two adjacent second conductive lines31-2.

FIGS. 4A to 4Jare diagrams illustrating a method for manufacturing a thin film transistor (“TFT”) array in accordance with a fourth embodiment of the present invention.FIG. 4Ais a cross-sectional view along the direction BB of a top view illustrated inFIG. 4B. Referring toFIG. 4A, a substrate40, made of glass or resin, for example, is provided. A patterned first metal layer41is formed on the substrate40by forming a layer of metal on the substrate40by a conventional PVD process followed by a conventional patterning and etching process, using a first mask. The patterned first metal layer41includes a plurality of first conductive lines41-1substantially in parallel with each other, and a plurality of second conductive lines41-2substantially orthogonal to the first conductive lines41-1. Each of the first conductive lines41-1includes gate electrodes41-3. Each of the gate electrodes41-3is disposed near an intersection of one of the first conductive lines41-1and one of the second conductive lines41-2. Each of the first conductive lines41-1eventually becomes a main line of a dual-layer wire, and each of the second conductive lines41-2eventually becomes branch lines of a dual-layer wire.

Referring toFIGS. 4C and 4D, an insulation layer43is formed on the patterned first metal layer41by a conventional CVD process or some other suitable process. Next, a patterned silicon layer44is formed on the insulation layer43by forming a layer of silicon by, for example, a conventional CVD, laser annealing or some other suitable process, followed by a conventional patterning and etching process, using a second mask, which defines an active region disposed over each of the gate electrodes41-1. The patterned silicon layer44comprises one of an amorphous silicon layer or a polycrystalline silicon layer.

Referring toFIGS. 4E and 4F, a patterned passivation layer45is formed over the insulation layer43and the patterned silicon layer44by forming a layer of insulating material by a conventional CVD process followed by a conventional patterning and etching process, using a third mask and a photoresist layer. The patterned passivation layer45exposes the first conductive lines41-1, second conductive lines41-2and the patterned silicon layer44through trenches46-1,46-2and46-3, respectively. The remaining photoresist layer42is used as a mask for doping n-type or p-type impurity into the patterned silicon layer44by, for example, a conventional implanting process or other suitable process. The photoresist layer defines a first diffused region44-1and a second diffused region44-2, i.e., source and drain or vice versa, for each TFT transistor. The remaining photoresist layer42is then stripped off.

Each of the trenches46-1disposed over one of the first conductive lines41-1is separated from an adjacent trench disposed over the same one conductive line by a distance “a”. In the fourth embodiment, the ratio of a length “b” of a trench to the distance “a” ranges from approximately 2 to 20. Likewise, each of the trenches46-2disposed over one of the second conductive lines41-2is separated from an adjacent trench disposed over the same one conductive line by a distance “p”. In the fourth embodiment, the ratio of the length “q” of a trench to the distance “p” ranges from approximately 2 to 20.

Referring toFIGS. 4G and 4H, a patterned second metal layer48is formed over the patterned passivation layer45, filling the trenches46-1,46-2and46-3. The second metal layer48is formed by forming a layer of metal by a conventional PVD process followed by a conventional patterning and etching process, using a fourth mask.

The patterned second metal layer48includes a plurality of third conductive lines48-1and a plurality of fourth conductive lines48-2orthogonal to the third conductive lines48-1. Each of the third conductive lines48-1eventually becomes branch lines of a dual-layer wire, and each of the fourth conductive lines48-2eventually becomes a main line of a dual-layer wire. The third conductive lines48-1of the patterned second metal layer48are electrically connected to the first conductive lines41-1of the patterned first metal layer11through the trenches46-1to form a dual-layer wire, i.e., a dual-layer scan line for the TFT array. The fourth conductive lines48-2of the patterned second metal layer48are electrically connected to the second conductive lines41-2of the patterned first metal layer41through the trenches46-2to form a dual-layer wire, i.e., a dual-layer data line for the TFT array. The ratio of the length of a branch line corresponding to a main line to the distance between the branch line and an immediately adjacent branch line corresponding to the same main line ranges from approximately 2 to 20.

Referring toFIGS. 4I and 4J, a patterned pixel electrode layer49is formed by forming a layer of conductive material such as ITO over the patterned second metal layer48and patterned passivation layer45by a conventional PVD process followed by a conventional patterning and etching process, using a fifth mask. The patterned pixel electrode layer49serves as pixel electrodes for the TFT array.

FIG. 5is a cross-sectional diagram illustrating a method for manufacturing a TFT array in accordance with a fifth embodiment of the present invention. Referring toFIG. 5, also referring toFIGS. 4A to 4E, a first mask is used to define the patterned first metal layer41. Next, a layer of insulating material43is formed over the patterned silicon layer44. A second mask is used to defined the patterned silicon layer44. A passivation layer55is formed over the patterned silicon layer44and insulating material43. A patterned pixel electrode layer59such as an ITO film is formed on the passivation layer55by a conventional PVD process followed by a conventional patterning and etching process, using a third mask, which serves as pixel electrodes for the TFT array. Then, the passivation layer55is patterned by performing a conventional patterning and etching process, using a fourth mask, exposing portions of the patterned silicon layer44and portions of the patterned first metal layer41-1and41-2. Next, the patterned silicon layer44is doped with n-type or p-type impurity by a conventional implantation process, using the same fourth mask. Subsequently, the patterned second metal layer48is formed over the patterned conductive layer59and the patterned passivation layer55, using a fifth mask.

Alternatively, referring toFIG. 5and alsoFIGS. 4A to 4E, first, second and third masks are used to define the patterned first metal layer41, the patterned silicon layer44and the patterned passivation layer55, respectively. Next, the patterned silicon layer44is doped with n-type or p-type impurity by a conventional implanting process, using the same third mask. The patterned pixel electrode layer59is formed over the patterned passivation layer55by forming a layer of conductive material such as ITO by a conventional PVD process followed by a conventional patterning and etching process, using a fourth mask. Subsequently, the patterned second metal layer48is formed over the patterned pixel electrode layer59and the patterned passivation layer55, using a fifth mask.