RANK INTERLEAVING FOR SYSTEM META MODE OPERATIONS IN A DYNAMIC RANDOM ACCESS MEMORY (DRAM) MEMORY DEVICE

This disclosure provides systems, methods, and devices for memory systems that support processing data and metadata within a memory of a memory device. In a first aspect, a method of controlling a memory device includes executing a first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion; and executing a second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank. Other aspects and features are also claimed and described.

TECHNICAL FIELD

Aspects of the present disclosure relate generally to computer information systems, and more particularly, to memory systems for storing data. Some features may enable and provide improved memory capabilities for processing data and metadata stored in the same memory device.

INTRODUCTION

A computing device (e.g., a laptop, a mobile phone, etc.) may include one or several processors to perform various computing functions, such as telephony, wireless data access, and camera/video function, etc. A memory system is an important component of the computing device. The processors may be coupled to the memory system to perform the aforementioned computing functions. For example, the processors may fetch instructions from the memory system to perform the computing functions and/or to store within the memory system temporary data involved in performing these computing functions.

BRIEF SUMMARY OF SOME EXAMPLES

In some aspects, different types of information, such as data and metadata, may be stored in a same memory of the memory system in order to enhance efficiency of operation of a memory system. In particular, both data and associated metadata may be stored in a same row of a memory in a system meta mode. Furthermore, a memory system may include multiple ranks of memory for storing data and metadata, such as multiple blocks or divisions of the storage capacity of the memory. To facilitate efficient use of limited memory bandwidth, data access operations, such as operations to read data or metadata from and/or read and/or write metadata to multiple ranks of a memory system may be interleaved. Such interleaving may, for example, include initiating a first data access operation for a first rank and, subsequently, initiating a second data access operation for a second rank. Such interleaving may include performing at least a portion of a data access operation of a first rank of the memory system in parallel with at least a portion of a second data access operation of a second rank of a second rank of the memory system. In particular, operations to access metadata at one rank of the memory system may be performed in parallel with operations to access data at another rank of the memory system.

Particular implementations of the subject matter described in this disclosure may be implemented to realize one or more of the following potential advantages or benefits. Interleaving of data access operations for different ranks of a memory system may enhance an efficiency of usage of cache and bus capacity of the memory system. In some aspects, such interleaving may provide cache access efficiency of up to and exceeding eighty-six percent.

These aspects may be embodied as a sequence of commands transmitted from a host to a memory system. The commands transmitted by the host may include commands to read capabilities from the memory system, set configurations in the memory system, read data at one or more specified addresses from the memory system, and/or write data at one or more specified addresses to the memory system.

An apparatus in accordance with at least one embodiment includes a memory system configured to communicate with a host. The memory system may include one or more memory controllers configured to control a memory device. For example, the memory device may include a memory array configured to store data. The one or more memory controllers may be configured to provide the data stored in the memory array to the host for further processing by the processor or other components of the host. The one or more memory controllers may also be configured to receive data from the host for storage in the memory device, such as in the memory array. In some embodiments, the memory device may include a plurality of volatile memory cells organized in rows and columns, such as in a dynamic random access memory (DRAM) or static random access memory (SRAM). In other embodiments, the memory device may include a plurality of non-volatile memory cells or a mixture of volatile and non-volatile memory cells.

An apparatus in accordance with at least one other embodiment includes a host device with one or more memory controllers configured to communicate with a memory system to receive data stored in the memory array and/or to store data in the memory array. The host device may be, for example, a user equipment (UE) device such as a cellular phone, a tablet computing device, a personal computer, a server, a smart watch, or an internet of things (IoT) device.

In one aspect of the disclosure, a method for operating a memory device includes receiving, by the one or more memory controllers, a first request for a memory device and a second request for the memory device; executing, by the one or more memory controllers, the first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion; and executing, by the one or more memory controllers, the second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank.

In an additional aspect of the disclosure, an apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to receive and schedule operations for execution by a multi-rank memory device. The processor may be a processor, controller, or other logic circuitry in a host. The processor may alternatively be a controller embedded in a memory device. The processor is further configured to perform the operations described herein.

In an additional aspect of the disclosure, an apparatus includes means for receiving, by the one or more memory controllers, a first request for a memory device and a second request for the memory device; means for executing, by the one or more memory controllers, the first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion; and means for executing, by the one or more memory controllers, the second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank.

In an additional aspect of the disclosure, an apparatus includes one or more memory controllers of a memory system. The one or more memory controllers are configured to perform operations including receiving, by the one or more memory controllers, a first request for a memory device and a second request for the memory device, executing, by the one or more memory controllers, the first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion, and executing, by the one or more memory controllers, the second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank.

In an additional aspect of the disclosure, an apparatus includes a host device configured to communicate with a memory module through a channel. The host device includes one or more memory controllers coupled to the channel. The one or more memory controllers are configured to perform operations including receiving, by the one or more memory controllers, a first request for a memory device and a second request for the memory device, executing, by the one or more memory controllers, the first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion, and executing, by the one or more memory controllers, the second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank.

An apparatus in accordance with at least one embodiment includes a memory configured to communicate with a host. The memory may include a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions. In some aspects, registers of a memory device may be configured to separately store data and metadata in different sets of registers. The metadata registers may temporarily store information during transmission between a host device and a memory device for retrieval from a memory array of the memory device in response to a read command or storage in the memory array of the memory device in response to a write command.

In one aspect of the disclosure, a memory device includes a memory array comprising a first portion and a second portion; and a memory input/output (I/O) module. The memory I/O module may be coupled to the memory array, configured to communicate with a host through a channel comprising a plurality of connections including at least one data connection and at least one non-data connection, and comprised of at least one first register and at least one second register. The memory I/O module may be configured to perform operations including receiving data from the host via the at least one data connection into the at least one first register; receiving metadata from the host via the at least one non-data connection into the at least one second register; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. The memory I/O module may also be configured to perform operations including retrieving data from the first portion of the memory array into the at least one first register; retrieving metadata from the second portion of the memory array into the at least one second register; transmitting the data to the host via the at least one data connection from the at least one first register; and transmitting the metadata to the host via the at least one non-data connection from the at least one second register.

In an additional aspect of the disclosure, an apparatus, such as a wireless device, includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to communicate with the memory system through a one or more memory controllers coupled to a channel that couples the processor to the memory system. The processor may be a processor, controller, or other logic circuitry in a host.

In an additional aspect of the disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform operations described herein regarding aspects of the disclosure.

Memory systems in the present disclosure may be embedded within a processor on a semiconductor die or be part of a different semiconductor die. The memory systems may be of various kinds. For example, the memory may be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash, or NOR flash, etc.

Methods and apparatuses are presented in the present disclosure by way of non-limiting examples of Low-Power Double Data Rate (LPDDR) Synchronous Dynamic Random Access Memory (SDRAM). For example, the LPDDR memory operating in accordance with LPDDR specification promulgated by Joint Electronic Device Engineering Council (JEDEC). One such LPDDR specification may be LPDDR5. Another such LPDDR specification may be LPDDR6.

The term error-correcting code or codes (ECC or ECCs) in the present disclosure may refer to error detection, error correcting, or error detection and correcting codes. The ECCs are not be limited to a particular type of coding. In some examples, the ECCs may include Hamming codes and/or parity codes.

Other aspects, features, and implementations will become apparent to those of ordinary skill in the art, upon reviewing the following description of specific, exemplary aspects in conjunction with the accompanying figures. While features may be discussed relative to certain aspects and figures below, various aspects may include one or more of the advantageous features discussed herein. In other words, while one or more aspects may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with the various aspects. In similar fashion, while exemplary aspects may be discussed below as device, system, or method aspects, the exemplary aspects may be implemented in various devices, systems, and methods.

The method may be embedded in a computer-readable medium as computer program code comprising instructions that cause a processor to perform the steps of the method. In some embodiments, the processor may be part of a mobile device including a first network adaptor configured to transmit data, such as images or videos in a recording or as streaming data, over a first network connection of a plurality of network connections. The processor may be coupled to the first network adaptor and a memory for storing data to support the processing and communications operations performed by the processor. The network adaptor may support communication over a wireless communications network such as a 5G NR communication network. The processor may cause the transmission of data stored in memory over the wireless communication network.

DETAILED DESCRIPTION

The present disclosure provides systems, apparatus, methods, and computer-readable media that support data processing, including techniques for supporting communication of data between a host and a memory device. The host may transmit data and accompanying metadata for storage in a memory array of the memory device. The memory device may include registers for receiving a copy of the metadata stored in the memory array prior to transmitting data and associated metadata to the host in response to a read command and accumulating the metadata sent by the host with data for writing to the memory array. Metadata registers of the memory device may be organized to associate metadata with the data without using two separate addresses for the data and metadata. Examples of metadata for storage with the data include error correction codes (ECCs) to protect the data from errors and/or signatures to protect the data from tampering. Metadata may, however, be used for more than protection of the data. To enhance efficiency and reduce cost of memory systems, both data and metadata may be stored in a same memory array of a memory system in a system meta mode. In some aspects, data and metadata may be stored in a same row, or page, of a memory array of the memory system, with a portion of the row, or page, allocated for data storage and a portion of the row, or page, allocated for metadata storage. Accessing metadata stored in a same row, or page, of a memory as data may reduce an amount of memory bandwidth available for reading and/or writing data, as metadata access operations may utilize bandwidth that would otherwise be available for reading data from and/or writing data to the memory. In some cases, 20-30% of memory utilization may be lost, with only an approximate maximum of 55% of DDR bandwidth being used for reading and writing data. Such reductions in efficiency may be attributed, at least in part, to metadata write operations being primarily partial writes, which may utilize a substantial portion of read/write bandwidth of the memory device including the memory array. To facilitate more efficient reading and writing of data and metadata from memories configured in a system meta mode, metadata and data may be read from the memory array or written to the memory array by interleaving operations between ranks of the memory device to reduce the overhead associated with reading and/or writing additional metadata bits into the memory array.

Particular implementations of the subject matter described in this disclosure may be implemented to realize one or more of the following potential advantages or benefits. In some aspects, the present disclosure provides a reduction in overhead by allowing metadata operations in one rank of the memory device to overlap data operations in another rank of the memory device. Such reduction may enhance an efficiency of operation of memory devices, allowing for data and metadata to be more rapidly read and written.

As demands grow for the computing device to perform more functions with increasing speed, errors with data stored in a memory may grow as well. Errors may grow as data stored in memories and transferred between blocks increases. One example of protecting from such errors is the use of error correction codes (ECCs) associated with data. Schemes to improve error detection/correction in accessing a memory, without overburdening a host or the memory, are advantageous to improve system performance. ECC may be attached during transmission over channels, such as with link ECC. ECC may also be attached for storage into the memory array, such as with system ECC. In some examples, end-to-end system ECC may be implemented in a host by adding large density on-chip SRAM to store in-line ECC parity bits for certain data to enhance overall data reliability. However, such high-density on-chip SRAM is very expensive in terms of overall system cost, and high-density SRAM is susceptible to soft errors associated with SRAM cells. ECC data is one example of metadata that may be stored with data in one or more ranks of a memory system.

An example memory device that may incorporate aspects of this disclosure, including performing transactions (e.g., read operations and/or write operations) in multiple ranks of a memory device in an interleaved manner to reduce the impact of accessing metadata, is shown inFIG.1.FIG.1illustrates an apparatus100incorporating a host110, memories150, and channels190coupling the host110and the memories150. The apparatus100may be, for example, a device among computing systems (e.g., servers, datacenters, desktop computers), mobile computing device (e.g., laptops, cell phones, vehicles, etc.), Internet of Things devices, virtual reality (VR) systems, augmented reality (AR) systems, automobile systems (e.g., driver assistance systems, autonomous driving systems), image capture devices (e.g., stand-alone digital cameras or digital video camcorders, camera-equipped wireless communication device handsets, such as mobile telephones, cellular or satellite radio telephones, personal digital assistants (PDAs), panels or tablets, gaming devices, computing devices such as webcams, video surveillance cameras, or other devices with digital imaging or video capabilities), and/or multimedia systems (e.g., televisions, disc players, streaming devices,).

The host110may include at least one processor, such as central processing unit (CPU), graphic processing unit (GPU), digital signal processor (DSP), multimedia engine, and/or neural processing unit (NPU). The host110may be configured to couple and to communicate to the memories150(e.g., memories150-1to150-4), via channels190(e.g., channels190-1to190-4), in performing the computing functions, such as one of data processing, data communication, graphic display, camera, AR or VR rendering, image processing, neural processing, etc. For example, the memories150-1to150-4may store instructions or data for the host to perform the computing functions.

The host110may include a memory controller130, which may include controller PHY modules134-1to134-4. Each of the controller PHY modules134-1to134-4may be coupled to a respective one of the memories150-1to150-4via respective channels190-1to190-4. In some embodiments, each of the controller PHY modules134-1to134-4may be different memory controllers130-1to130-4, respectively. For ease of reference, read and write are referenced from a perspective of the host110. For example, in a read operation, the host110may receive via one or more of the channels190-1-190-4data stored from one or more of the memories150-1to150-4. In a write operation, the host110may provide via one or more of the channels190-1-190-4data to be written into one or more of the memories150-1-150-4for storage. The memory controller130may be configured to control various aspects, such as logic layers, of communications to and from the memories150-1-150-4. The controller PHY modules134-1-134-4may be configured to control electrical characteristics (e.g., voltage levels, phase, delays, frequencies, etc.) of signals provided or received on the channels190-1-190-4, respectively.

In some examples, the memories150-1-150-4may be LPDDR DRAM (e.g., LPDDR5, LPDDR6). In some examples, the memories150-1-150-4may be different kinds of memory, such as one LPDDR5, one LPDDR6, one Flash memory, and one SRAM, respectively. The host110, the memories150-1-150-4, and/or the channels190-1-190-4may operate according to an LPDDR (e.g., LPDDR5, LPDDR6) specification. In some examples, each of the channels190-1-190-4may include 16 bits of data (e.g., 16 DQs). In some examples, each of the channels190-1-190-4may operate on 32 bits of data (e.g., 32 DQs). InFIG.1, four channels are shown, however the apparatus100may include more or less channels, such as 8 or 16 channels.

Additional details of an aspect of the embodiment of the apparatus100for providing access to a memory system (such as one of memories150-1-150-4including logic and control circuit) are shown inFIG.2.FIG.2illustrates a configuration of the host110, a memory system250FIG.2illustrates another representation of the apparatus100having the host110, the memory system250, and the channel190ofFIG.1. The channel190between host110and the memory system250may include a plurality of connections, some of which carry data (e.g., user data or application data) and some of which carry non-data (e.g., addresses and other signaling information). For example, non-data connections in channel190may include a data clock (e.g., WCK) used in providing data to the respective memory system250and a read data strobe (e.g., RDQS) used in receiving data from the respective memory system250, on a per byte basis. The channel190may further include command and address (e.g., CA[0:n]) and associated CA clock to provide commands (e.g., read or write commands) to the memory system250.

The host110may include at least one processor120, which may include a CPU122, a GPU123, and/or an NPU124. The host110may further include a memory controller130having a controller PHY module134. The memory controller130may couple to the at least one processor120via a bus system115in performing the various computing functions. The term “bus system” may provide that elements coupled to the “bus system” may exchange information therebetween, directly or indirectly. In different embodiments, the “bus system” may encompass multiple physical connections as well as intervening stages such as buffers, latches, registers, etc. A module may be implemented in hardware, software, or a combination of hardware and software.

The memory controller130may send and/or receive blocks of data to other modules, such as the at least one processor120and/or the memory system250. The memory system250may include a memory controller180with a memory I/O module160(e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage levels, phase, delays, frequencies, etc.) to provide or to receive signals on connections of the channel190. For example, memory I/O module160may be configured to capture (e.g., to sample) data, commands, and addresses from the host110via the channel190and to output data to the host110via the channel190. Example techniques for communicating on the channel190between the memory I/O module160and the memory controller130are shown in the examples ofFIG.3A,FIG.3B,FIG.4A, andFIG.4B.

The memory system250may further include a memory array175, which may include multiple memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, Flash memory cells) that store values. The host110may read data stored in the memory array175and write data into the memory array175, via the channel190and the memory I/O module160. The memory array175may be divided into a plurality of banks with each bank organized as a plurality of pages. In some aspects, the memory array175may be divided into a plurality of ranks. For example, each rank may include one or more banks, with each bank including one or more pages.

Application or user data may be processed by the processor120and the memory controller130instructed to store and/or retrieve such data from the memory system250. For example, data may be generated during the execution of an application, such as a spreadsheet program that computes values based on other data. As another example, data may be generated during the execution of an application by receiving user input to, for example, a spreadsheet program. As a further example, data may be generated during the execution of a gaming application, which generates information regarding a representation of a scene rendered by a three-dimensional (3-D) application.

The host110is coupled to the memory system250via the channel190, which is illustrated for a byte of data, DQ[0:7]. The channel190and signaling between the host110and the memory system250may be implemented in accordance with the JEDEC DRAM specification (e.g., LPDDR5, LPDDR6). As illustrated, the channel190includes signal connections of the DQs, a read data strobe (RDQS), a data mask (DM), a data clock (WCK), command and address (CA[0:n]), and command and address clock (CK). The host110may use the read data strobe RDQS to strobe (e.g., to clock) data in a read operation to receive the data on the DQs. The memory system250may use the data mask DM to mask certain parts of the data from being written in a write operation. The memory system250may use the data clock WCK to sample data on the DQs for a write operation. The memory system250may use the command and address clock CK to clock (e.g., to receive) the CAs. A signal connection for each of the signaling may include a pin at the host110, a pin at the memory system250, and a conductive trace or traces electrically connecting the pins. The conductive trace or traces may be part of a single integrated circuit (IC) on a silicon chip containing the processor120and the memory system250, may be part of a package on package (POP) containing the processor120and the memory system250, or may be part of a printed circuit board (PCB) coupled to both the processor120and the memory system250. In some aspects, a channel190between a host110and a memory system250may include 12 DQ pins, for twelve bits of data DQ[11:0] and no DM pins. Both data and metadata may be transferred on DQ pins, for thirty-two bytes of data and four bytes of metadata in 24 beats (24BL). In some cases, such as when ECC metadata is being transferred via the channel190, only two bytes of the four available bytes may be transferred, as ECC may include 2 bytes of metadata per 32 bytes of data.

The memory system250may include a memory I/O module160(e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage levels, phase, delays, frequencies, etc.) to provide or to receive signals on the channel190. For example, memory I/O module160may be configured to capture (e.g., to sample) data, commands, and addresses from the host110via the channel190and to output data to the host110via the channel190.

Information transmitted across the channel190may be stored in registers in the memory I/O module160of the memory150as a temporary or short-term storage location prior to longer-term storage in the memory array175. The memory I/O module160may include first and second registers for storing the data (e.g., user data or application data) and metadata, respectively. As one example, a plurality of metadata registers181A-N may store the metadata. The contents of registers181A-N may then be transferred to memory array175. In some embodiments, the contents of registers181A-N may be transferred shortly after receipt in a serial manner to complete individual write commands. In some embodiments, the contents of registers181A-N may be accumulated from multiple write commands received at the memory150and the metadata transferred to the memory array175when certain criteria are met. The data is then written to the first portion of the memory array automatically without any additional write commands from the host. Some example configurations for the metadata registers181A-N are shown inFIGS.5A-BandFIG.6.

The metadata registers181A-N may be associated with memory addresses of the memory array175according to different techniques. One example memory address mapping is shown inFIG.5A. Certain addresses in a page may be assigned for metadata, such as by carving-out column space corresponding to 0x3C-0x3F. The metadata registers181A-N may include n metadata registers dedicated to each column location, and each one of the n registers dedicated to each column location may be dedicated to one of n banks. That is, column space 0x3C has a first set518A of n meta data registers, column space 0x3D has a second set518B of n metadata registers, column space 0x3E has a third set518C of n meta data registers, and column space 0x3F has a fourth set518D of n metadata registers. The metadata registers181A-N may have a total of 4n registers in this example configuration. In another example, shown inFIG.5B, the metadata registers181A-N may include a single register per bank, totaling n registers for n banks. Thus, the metadata registers181A-N may include a single set of metadata registers520, and the column spaces 0x3C-0x3F may be associated with the single set of n metadata registers520rather than with separate sets of metadata registers per each column space. Use of a single set of metadata registers for column spaces 0x3C-0x3F may reduce a memory die size overhead through use of a single metadata register per bank.

Returning toFIG.2, the memory system250may further include a memory array175, which may include multiple memory cells (e.g., DRAM memory cells) that store information. For example, each page of each bank of the memory array175may include multiple cells. The host110may read data stored in the memory array175and write data into the memory array175via the channel190. Moreover, the memory array175may be configured to store metadata such as ECCs (e.g., system or array ECCs) associated with the stored data.

Operations according to some embodiments of this disclosure for storing and retrieving information from memory array175may be performed by controlling signals on individual lines of the channel190. Example embodiments of signaling for a write operation are shown and described with reference toFIG.3AandFIG.3B. Example embodiments of signaling for a read operation are shown and described with reference toFIG.4AandFIG.4B.

FIG.3AandFIG.3Billustrate waveforms of transfer of data through an example channel in a write operation in accordance with certain aspects of the present disclosure. The command and address clock, CK, may be a differential signal having CK_t and CK_c signal connections. The data clock WCK may be a differential signal having WCK0_t and WCK0_c signal connections. The read data strobe RDQS may be a differential signal having RDQS_t and RDQS_c signal connections. The data mask is labeled DM0to indicate that DM0 corresponds to a lower byte of DQs (DQ[0:7]). At T0 (rising edge of CK_c and falling edge of CK_t), a CAS command may be provided by the host110for a write operation to the memory system250. At T1, a write command may be provided by the host110to the memory system250.

After a time period write latency (WL), the host110may toggle the data clock WCK0_t and WCK0_c to provide the memory system250with clocking for receiving data for write, on the DQ signal connections. At Tc0-Tc2, the memory system250may receive 16 bytes of data serially, on each of the DQ[0:7] signal connections and clocked by the data clock WCK0_t and WCK0_c. The memory system250may receive 16 bits of the data mask DM0 serially (e.g., based on the data clock WCK0_t and WCK0_c) to mask certain portions of the received data from the write operation. In some examples, the 16 bytes of data and 16 bits of the data mask DM0 may be received by the memory system250, with each bit of the data mask DM0 masking a corresponding byte of the received data. At Tc0-Tc2, the RDQS_t signal connection may be a Hi-Z condition. In a read operation, the RDQS_t signal connection may be configured to provide a read data strobe (RDQS) from the memory system250to the host110.

FIG.4AandFIG.4Billustrate waveforms for transfer of data through an example channel in a read operation in accordance with certain aspects of the present disclosure. The command and address clock, CK, may be a differential signal having CK_t and CK_c signal connections. The data clock WCK may be a differential signal having WCK0_t and WCK0_c signal connections. The read data strobe RDQS may be a differential signal having RDQS_t and RDQS_c signal connections. The data mask is labeled DM0 to indicate that DM0 corresponds to a lower byte of DQs (DQ[0:7]). At T0 (rising edge of CK_c and falling edge of CK_t), a CAS command may be provided by the host110for a read operation to the memory system250. At T1, a read command may be provided by the host110to the memory system250.

After a time period read latency (RL), the memory system250may toggle the read data strobe RDQS to provide the host110with clocking to receive data for the read operation on the DQ signal connections. At Tc0-Tc2, the host110may receive 16 bytes of data serially, on each of the DQ[0:7] signal connections and clocked by the read data strobe RDQS_t and RDQS_c. Thus, in the example, 16 bytes of data are received by the host110.

At Tc0-Tc2, the data mask DM0 signal connection may be in a Hi-Z condition. In a write operation, the DM signal connection may be configured to provide a data mask from the host110to the memory system250, which is clocked by WCK0_t and WCK0_c.

In system meta mode one or more of the following may occur during operation of the memory device including the first die608and the second die612: metadata are transferred along with data, metadata are collocated with data in same row, metadata registers are introduced to transfer metadata to/from the DDR row, and/or metadata registers are controlled by new RD_meta and WR_meta commands, which may also be referred to as READ META and WRITE META commands. The RD_meta command may, for example, be used to read metadata from the memory arrays associated with the ranks604A-B to the metadata registers of logic602A-B, and the WR_meta command may, for example, be used to write metadata from the metadata registers of logic602A-B to the memory arrays associated with the ranks604A-B. Thus, as discussed herein, the memory device including the first die608and the second die612may be configured in a system meta mode for storage of related data and metadata in a same row of a memory array, such as a memory array associated with the first rank604A or a memory array associated with the second rank604B, of the memory device. One example of row access operations for operating the memory device including the first die608and the second die612in system meta mode is shown inFIG.7.FIG.7is a flow chart illustrating a method700of accessing rows in a memory device according to one or more aspects of the disclosure. At block702, a row of a memory array, such as a memory array associated with a first rank, may be activated. At block704, a determination may be made of whether a next data access operation, such as a next read or write operation, includes metadata loaded in a metadata register, such as a metadata register of logic602A, of a memory device. If the metadata has not been loaded to the metadata register, the memory device may, at block706, read metadata to the metadata register from the memory array. The memory device may then, at block708, perform the next data access operation. If the metadata has already been read to the metadata register, the memory device may proceed from the determination at block704to performing the data access operation at block708. At block710, a determination may be made of whether a previous data access operation was a final data access operation for the row. If the previous data access operation708was not the last data access operation for the row, then the method may repeat blocks704,706, and/or708for a remaining data access operation for the row. If the previous data access operation708was a last data access operation, a determination may be made at block712of whether all metadata registers associated with the memory array are clean. The metadata registers may be referred to as clean, for example, when the contents of the metadata registers have been written to the memory array and dirty when the contents of the metadata registers have not yet been written to the memory array. If the metadata registers are determined not to be clean at block712, a next dirty metadata register may be written to the memory array at block714. The method may then return to block712, and blocks712and714may be repeated until a determination is made that all metadata registers associated with the memory array are clean. When a determination is made, at block712, that all of the metadata registers are clean, the memory device may proceed to a pre-charge operation at block716. Thus, when data and metadata are stored in a same row of a memory array in a system meta mode, data and metadata may be read from and/or written to the memory of the device.

Storing metadata in the same memory device as the corresponding data can result in reduced performance. Metadata is smaller in size (e.g., number of bits) than the corresponding data, which results in some inefficiencies in accessing the metadata. For example, when the metadata size is smaller than the word size of the memory device, storing metadata may require reading a word to retrieve the previously stored metadata, modifying a portion of the metadata word, and writing the combined previously-stored metadata and new metadata. Thus, a write operation of the metadata may also include performing a read operation and other processing. Thus, writing metadata to a memory, such as a DDR memory, configured to operate in a system meta mode can significantly reduce the useable bandwidth. For example, a stream of write 64 bytes (WR 64B) operations at random addresses of a DDR memory without metadata access can utilize close to 100% of the DDR bandwidth. When metadata are accessed, each WR 64B operation will require an additional read 32 bytes (RD 32B) operation for the metadata, an operation to update the4B of metadata corresponding to the 64 B data and then a WR 32 B operation to store the updated metadata back into the memory array. Reading of metadata in conjunction with data write command is a function of the metadata being stored in the same row as the data in the system meta mode. Consequently, the DDR bandwidth required to access data and metadata stored in a system meta mode may be twice the bandwidth required to access data stored separately from metadata. Furthermore, READ to WRITE bus turnaround further reduces DDR access efficiency by approximately 20%. Consequently, the usable DDR bandwidth may be reduced by up to and, in some cases, exceeding 30% when operating in a system meta mode. Thus, in some cases, DDR bandwidth utilization when metadata are accessed with regular READ and WRITE commands may be approximately 50%-60% compared to 70%-80% when metadata are not accessed. Use of system meta mode commands, READ META and WRITE META, to read and write metadata may not remedy such issues when a single rank is accessed as a bandwidth of an internal bus, such as610A or610B ofFIG.6, may be limited in a similar way.

Inefficiencies that arise when a memory system is operating in a system meta mode, with data and metadata stored in a same row or page of a memory of the memory system, can be reduced by interleaving operations between banks of a multi-rank memory device, such as a device with two ranks (dual rank), four ranks (quad rank), or eight ranks (octal rank). For example, with reference toFIG.6, as metadata accesses with READ META or WRITE META commands do not transfer data on the external bus606but only on the internal bus610A-B conflict between metadata accesses and data accesses can be reduced or eliminated by accessing data in a first rank while accessing metadata in a second rank. As one example, with reference toFIG.6, data stored in the first rank604A may be accessed by logic602A via bus610A while metadata stored in the second rank604B is accessed via the second bus610B.

In one example interleaving operation, a first request and a second request may be interleaved between a first rank and a second rank in a memory device. Thus, interleaving requests to different memory ranks, as described herein, may refer to initiating requests in an interleaved fashion, with a request to a first rank being initiated, followed by initiation of a request to a second rank. In some aspects, a request to the first rank may be initiated following initiation of the request to the second rank. Thus, requests to different ranks may be interleaved. In some aspects, such interleaving may include initiation of the request to the second rank prior to completion of the request to the first rank and/or initiation of a second request to the first rank prior to completion of the request to the second rank. An example operation for a memory controller, such as the memory controller of the host device and/or the memory controller of the memory device for interleaving operations between ranks is described inFIG.8.FIG.8is a flow chart illustrating a method800of interleaving operations between ranks of a memory device according to one or more aspects of the disclosure. At block802, a memory controller may receive a first request for a memory device and a second request for the memory device. The first request may, for example, be a first data access request. In particular, the first request may, for example, be a first request to read data and metadata from or write data and metadata to a first rank of the memory device, such as a first memory array associated with a first rank of the memory device. Likewise, the second request may, for example, be a second data access request and may be a second request to read data and metadata from or write data and metadata to a second rank of the memory device, such as a second memory array associated with a second rank of the memory device. In some aspects, the memory controller may be configured to access the memory device in a system meta mode. In some aspects, the memory device may include a plurality of DRAM modules, and the memory controller may be configured to access the DRAM modules by storing data in a first portion of memory locations and storing metadata in a second portion of memory locations. In some aspects, the metadata may include ECC metadata. In some aspects, the memory device may include an LPDDR memory module, and the memory controller may be configured to communicate with the LPDDR memory module. In some aspects, the memory controller may be connected to a write buffer to allow a write request to be scheduled efficiently without conflicting with a next request in the same rank.

At block804, the memory controller may execute the first request in a first rank of the memory device during a first time period. The first time period may, for example, comprise a first data access portion and a first metadata access portion. For example, in response to a first request to access data and metadata stored in a first rank of the memory device, the memory device may, during a first portion of a first time period, access the data stored in the first rank of the memory device and, during a second portion of the first time period, access the metadata stored in the first rank of the memory device.

At block806, the memory controller may execute the second request in a second rank of the memory device during a second time period. The second time period may, for example, include a second data access portion and a second metadata access portion. For example, in response to a second request to access data and metadata stored in a second rank of the memory device, the memory device may, during a first portion of a second time period, access the data stored in the first rank of the memory device and, during a second portion of the second time period, access the metadata stored in the first rank of the memory device. In executing the first request and the second request, the memory controller may interleave the first request and the second request between the first rank and the second rank. For example, to interleave the first request and the second request, the memory controller may perform one or more operations according to the first request in parallel with one or more operations according to the second request. As one particular example, the execution of the second request by the memory controller may be timed such that at least one of (1) the first data access portion of the first time period at least partially overlaps with the second metadata access portion of the second time period or (2) the first metadata access portion of the first time period at least partially overlaps with the second data access portion of the second time period. Thus, the memory controller may execute the first and second requests that metadata access at one memory rank is performed in parallel with data access at another memory rank.

In some aspects, the first request may comprise a write operation, and the second request may comprise a read operation. The first data access portion of the first request may comprise a first data write in the first rank and the second metadata access portion may comprise a first metadata read in the second rank. The first and second requests may be timed by the memory controller such that the first data write in the first rank at least partially overlaps the first metadata read in the second rank in time. In some aspects, the first time period during which the first request is executed may further comprise a third metadata access portion, comprising a first metadata write operation in the first rank. In some aspects, the first request may thus comprise a request for a first metadata read operation in the first rank, a request for a first data read or write operation in the first rank, and a request for a first metadata write operation in the first rank. The first metadata write operation in the first rank may at least partially overlap the second data access portion of the second time period in the second rank. In some aspects, executing the first request in the first rank may include opening a minimum number of banks in the first rank for executing the first request.

In some aspects, the memory controller may execute a third request in the first rank of the memory device during a third time period after the first time period. Executing the first request in the first rank may include accessing a first set of banks in the first rank and executing the third request in the first rank may comprise accessing a second set of banks in the first rank, mutually exclusive of the first set of banks. Metadata access operations, such as metadata read or metadata write operations, in a rank of a memory may overlap, in time, any metadata or data access operations, such as metadata or data read or metadata or data write operations, in another rank of the memory.

FIG.9is a block diagram illustrating interleaved operations involving data and metadata between ranks of a memory device according to one or more aspects of the disclosure. A first portion of a series of interleaved operations950may include a first time period910, a second time period920, and a third time period930, along with other time periods for interleaved operations for reading and writing data and metadata. The first time period910may include a first metadata access portion912for performing a first metadata access operation, a first data access portion914for performing a first data access operation, and a further metadata access portion916for performing a further metadata access operation. The second time period920may include a second metadata access portion922for performing a second metadata access operation and a second data access portion924for performing a second data access operation. The third time period930may include a third metadata access portion932for performing a third metadata access operation and a third data access portion934for performing a third data access operation. Interleaving the operations of time periods910,920, and930may be performed by arranging operations such that an operation of the first time period910accesses a first rank (RANK0), an operation of the second time period920accesses a second rank (RANK1), and an operation of the third time period930accesses the first rank (RANK0). The first time period910, in this example corresponding to a write operation, may include a first portion for reading metadata in portion912, a second portion for writing of data in portion914, and a third portion for writing of metadata corresponding to the read metadata and the written data in portion916. The second time period920, in this example corresponding to a read operation, may include a first portion for reading metadata in portion922and a second portion for reading data in portion924.

Interleaving between ranks of a memory device may be scheduled to allow metadata operations to at least partially overlap with data operations within the same memory device by performing the overlapping operations on different ranks. Operations of the second time period920may be scheduled such that the data access portion914and the metadata access portion916of the first time period910at least partially overlap with the metadata access portion922of the second time period920. Although the example interleaving between time periods910and920is between a write operation on RANK 0 and a read operation on RANK 1, the interleaving may be applied to other arrangements of operations. For example, data access portion924of the second time period920may overlap with metadata access portion916of the first time period910and metadata access portion932of the third time period930, when the memory controller is scheduling two read operations as the second time period920and the third time period930. The memory controller130may also schedule operations on the same rank, such as operations910and930, such that the pages activated for each of the operations between back-to-back operations on a single rank are mutually exclusive. The scheduling of mutually exclusive pages on a single rank may be performed when time periods910and930are close enough in time such that the pages accessed in the first time period910cannot be closed prior to opening pages accessed in the third time period930. This is especially important when the first operation is a set of write operations and the second operation a set of read operations. The memory controller may be configured to avoid scheduling write operations on banks that may be used by a subsequent set of read operations. A write scheduler of the memory controller can predictively schedule such read and write operations through use of a write buffer organized in 32 queues making information regarding subsequent operations available to the memory controller in the respective banks. Thus, the memory controller may be able to determine which banks are likely to be subject to upcoming read operations within a particular time threshold and avoid scheduling such banks for write operations that would conflict with the upcoming read operations. In scheduling interleaved read and write operations, when a read operation is performed on data, a memory controller may be configured to schedule commands to read metadata prior to commands to read associated data, although such commands may be scheduled contemporaneously. Likewise, when a write operation is performed on data, the memory controller may be configured to schedule commands to read metadata prior to commands to write data. Furthermore, when a write operation is performed on data, the memory controller may be configured to schedule commands to write associated metadata after commands to write data. However, in some cases the memory controller may schedule commands to write the data and commands to write the metadata to occur contemporaneously. As shown inFIG.9a time of transition between a write data operation and a read data operation may be referred to as a tW2R_DR, a time of transition between a read data operation and a write data operation may be referred to a tR2W_DR. and a time of transition between a read data operation and a subsequent read data operation may be referred to as a tR2R_DR.

In some embodiments, a rank selection bit hashing may be performed to distribute incoming DDR operations across the two or more ranks, further enhancing efficiency. Interleaving batches of DRAM accesses between ranks may facilitate high DDR utilization in presence of metadata accesses, such as when a memory is configured to operate in a system meta mode. The memory controller may include a queue of operations waiting to be scheduled to the DRAM. The memory controller may schedule batches of read operations and batches of write operations. The batches should be scheduled alternately in different ranks. The transaction queue may contain transactions for multiple ranks, such as for two ranks in devices with two memory ranks, to allow the memory controller to select operations for a batch to be performed on a different rank after scheduling a batch of operations in a first rank. As one example, bits used to select the rank can be positioned just below the row bits, for example bit15in a dual rank DRAM system as shown in the first portion1002and the second portion1004of the physical address bit assignment mapping ofFIG.10. As another example, a rank bit may be hashed with a row bit to further randomize a distribution of access operations across the ranks, as shown in the first portion1100and the second portion1110of the table for hashing for address mapping ofFIGS.11A-B. For example, as shown inFIGS.11A-B. a poly37 hash may be used to derive a hash matrix from primitive polynomials over GF(2): x5+x2+1.

In some embodiments, write operations may be accumulated in a buffer and subsequently evicted to the memory controller in a DRAM efficient order. An example block diagram1200,1220of a write buffer and a write scheduler for efficient scheduling of write operations is shown inFIGS.12A-B. A write buffer1202may, for example, be a partition of a system cache organized as a set of queues with one queue par bank per rank. For example, a write buffer for an LPDDR5 or LPDDR6 dual rank system may include 32 queues, as shown in the write buffer1202ofFIG.12A. A write transaction may be received by the write buffer1202and placed in a queue. A write scheduler1204may schedule write operations from the write buffer1202, such as by selecting a batch of write operations for a rank different from a previous batch rank, minimizing a number of banks activated during a batch of write operations, and enacting a preference for write operations for banks that do not conflict with pending read operations. With such organization, the write scheduler1204may simultaneously observe candidate write operations in every bank and may select write transactions that can be scheduled in a desired rank with maximum efficiency and without penalizing a read operation already present in the memory controller. The write scheduler1204may transmit one or more selected buffered write commands to a memory controller of the memory device, such as a memory controller of a DRAM device.

A wireless communications device may include a memory system as illustrated in at leastFIG.1andFIG.2and configured to receive and output data, including ECC or other metadata, from the memory array and interleave operations on different ranks of the memory device comprising the memory array to reduce overhead associated with storing metadata in the memory array with the data. The memory system according to any of the aspects disclosed herein, may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, or avionics systems.

In one or more aspects, techniques for memory storage and retrieval may include additional aspects, such as any single aspect or any combination of aspects described below or in connection with one or more other processes or devices described elsewhere herein. In a first aspect, supporting data operations may include an apparatus configured to perform operations including receiving, by one or more memory controllers, a first request for a memory device and a second request for the memory device, executing, by the one or more memory controllers, the first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion, and executing, by the one or more memory controllers, the second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank.

Additionally, the apparatus may perform or operate according to one or more aspects as described below. In some implementations, the apparatus includes a wireless device, such as a UE. In some implementations, the apparatus includes a remote server, such as a cloud-based computing solution, which receives image data for processing to determine output image frames. In some implementations, the apparatus may include at least one processor, and a memory coupled to the processor. The processor may be configured to perform operations described herein with respect to the apparatus. In some other implementations, the apparatus may include a non-transitory computer-readable medium having program code recorded thereon and the program code may be executable by a computer for causing the computer to perform operations described herein with reference to the apparatus. In some implementations, the apparatus may include one or more means configured to perform operations described herein. In some implementations, a method of wireless communication may include one or more operations described herein with reference to the apparatus. In some implementations, the apparatus may comprise one or more memory controllers configured to perform operations described herein with respect to the apparatus. In some implementations, the apparatus may comprise a host device configured to communicate with a memory module through a channel. The host device may include one or more memory controllers coupled to the channel and configured to perform the operations described wherein with respect to the apparatus.

In a second aspect, in combination with the first aspect, the execution of the second request by the one or more memory controllers is timed such that at least one of (1) the first data access potion at least partially overlaps with the second metadata access portion or (2) the first metadata access portion at least partially overlaps with the second data access portion.

In a third aspect, in combination with one or more of the first aspect or the second aspect, the first request comprises a write operation and the second request comprises a read operation, and the first data access portion of the first request comprises a first data write in the first rank and the second metadata access portion comprises a first metadata read in the second rank, where the first data write in the first rank at least partially overlaps the first metadata read in the second rank

In a fourth aspect, in combination with one or more of the first aspect through the third aspect, the first time period further comprises a third metadata access portion comprising a first metadata write in the first rank, and the first metadata write in the first rank at least partially overlaps the second data access portion of the second time period in the second rank.

In a fifth aspect, in combination with one or more of the first aspect through the fourth aspect, executing the first request in the first rank comprises opening a minimum number of banks in the first rank for executing the first request.

In a sixth aspect, in combination with one or more of the first aspect through the fifth aspect, the apparatus is further configured to perform operations comprising executing. by the one or more memory controllers, a third request in the first rank of the memory device during a third time period after the first time period, wherein executing the first request in the first rank comprises accessing a first set of banks in the first rank and executing the third request in the first rank comprises accessing a second set of banks mutually exclusive of the first set of banks.

In a seventh aspect, in combination with one or more of the first aspect through the sixth aspect, the one or more memory controllers are configured to access the memory device in a system meta mode.

In an eighth aspect, in combination with one or more of the first aspect through the seventh aspect, the memory device comprises a plurality of dynamic random access memory (DRAM) modules and the one or more memory controllers are configured to access the DRAM modules by storing data in a first portion of memory locations and storing metadata in a second portion of memory locations.

In a ninth aspect, in combination with one or more of the first aspect through the eighth aspect, the metadata comprises error correction codes (ECCs).

In a tenth aspect, in combination with one or more of the first aspect through the ninth aspect, the one or more memory controllers are configured to communicate with a low power double data rate (LPDDR) memory module.

In the description of embodiments herein, numerous specific details are set forth, such as examples of specific components, circuits, and processes to provide a thorough understanding of the present disclosure. The term “coupled” as used herein means connected directly to or connected through one or more intervening components or circuits. Also, in the following description and for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the teachings disclosed herein. In other instances, well known circuits and devices are shown in block diagram form to avoid obscuring teachings of the present disclosure.

Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. In the present disclosure, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system.

The terms “device” and “apparatus” are not limited to one or a specific number of physical objects (such as one smartphone, one camera controller, one processing system, and so on). As used herein, a device may be any electronic device with one or more parts that may implement at least some portions of the disclosure. While the description and examples herein use the term “device” to describe various aspects of the disclosure, the term “device” is not limited to a specific configuration, type, or number of objects. As used herein, an apparatus may include a device or a portion of the device for performing the described operations.

Certain components in a device or apparatus described as “means for accessing,” “means for receiving,” “means for sending,” “means for using,” “means for selecting,” “means for determining,” “means for normalizing,” “means for multiplying,” or other similarly-named terms referring to one or more operations on data, such as image data, may refer to processing circuitry (e.g., application specific integrated circuits (ASICs), digital signal processors (DSP), graphics processing unit (GPU), central processing unit (CPU)) configured to perform the recited function through hardware, software, or a combination of hardware configured by software.

Those of skill in the art that one or more blocks (or operations) described with reference to the figures included with this description may be combined with one or more blocks (or operations) described with reference to another of the figures. For example, one or more blocks (or operations) ofFIG.3A-3Bmay be combined with one or more blocks (or operations) ofFIG.1orFIG.2. As another example, one or more blocks (or operations) ofFIGS.7orFIG.8may be combined with one or more blocks (or operations) ofFIG.1,FIG.2,FIG.3A,FIG.3B,FIG.4A,FIG.4B,FIGS.5A-B, orFIG.6.

Additionally, a person having ordinary skill in the art will readily appreciate, opposing terms such as “upper” and “lower,” or “front” and back,” or “top” and “bottom,” or “forward” and “backward” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of any device as implemented.

As used herein, the term “coupled to” in the various tenses of the verb “couple” may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element B), to operate certain intended functions. In the case of electrical components, the term “coupled to” may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween). In some examples, the term “coupled to” mean a transfer of electrical energy between elements A and B, to operate certain intended functions.

In some examples, the term “electrically connected” mean having an electric current or configurable to having an electric current flowing between the elements A and B. For example, the elements A and B may be connected via resistors, transistors, or an inductor, in addition to a wire, trace, or other electrically conductive material and components. Furthermore, for radio frequency functions, the elements A and B may be “electrically connected” via a capacitor.

The term “substantially” is defined as largely, but not necessarily wholly, what is specified (and includes what is specified; for example, substantially 90 degrees includes 90 degrees and substantially parallel includes parallel), as understood by a person of ordinary skill in the art. In any disclosed implementations, the term “substantially” may be substituted with “within [a percentage] of” what is specified, where the percentage includes 0.1, 1, 5, or 10 percent.