SEMICONDUCTOR DEVICE

A semiconductor device is provided. The semiconductor device includes a substrate, a gate strip, a source doped region and a body doped region. The substrate has an active region. The gate strip is disposed on the substrate within the active region. The gate strip extends along a first direction. The source doped region is located in the active region and adjacent to a first side of the gate strip along the first direction. The body doped region is located in the active region and adjacent to the first side of the gate strip. The body doped region and the source doped region have opposite conductivity types. The body doped region has a first length along a second direction that is different from the first direction, wherein the first length gradually changes along the first direction.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a semiconductor device, and, in particular, to a power metal-oxide-semiconductor field effect transistor (MOSFET) device.

Description of the Related Art

Battery-operated electronic systems such as notebook personal computers, personal digital assistants, and wireless communication devices often use power metal-oxide-semiconductor (MOS) devices as low on-resistance (Ron) electronic switches for distributing battery power. For battery-operated applications, low on-resistance can be particularly important to ensure as little power consumption on the battery as possible. This ensures a long battery life. However, the problems of increased on-resistance become significant in high-density power MOS devices.

Thus, a novel power MOS electronic device is needed.

BRIEF SUMMARY OF THE INVENTION

An embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a gate strip, a source doped region and a body doped region. The substrate has an active region. The gate strip is disposed on the substrate within the active region. The gate strip extends along a first direction. The source doped region is located in the active region and adjacent to a first side of the gate strip along the first direction. The body doped region is located in the active region and adjacent to the first side of the gate strip. The body doped region and the source doped region have opposite conductivity types. The body doped region has a first length along a second direction that is different from the first direction. The first length gradually changes along the first direction.

An embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a gate strip, a source doped region and a body doped region. The substrate of a first conductivity type has an active region. The gate strip is disposed on the substrate within the active region. The gate strip extends along a first direction. The source doped region of a second conductivity type is located in the active region and adjacent to a first side of the gate strip. The body doped region of the first conductivity type is located in the active region and adjacent to the first side of the gate strip. The body doped region has least one edge close to the first side of the first gate strip. An extended line of the edge of the body doped region meets the first side of the first gate strip. An angle between the extended line and the first side of the first gate strip is an acute angle.

In addition, an embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a gate strip, a source doped region and a body doped region. The substrate of a first conductivity type has an active region. The gate strip is disposed on the substrate within the active region. The gate strip extends along a first direction. The source doped region of a second conductivity type is disposed in the active region and adjacent to a first side of the gate strip. The body doped region of the first conductivity type is disposed in the active region and adjacent to the first side of the gate strip. Ratios of widths of the body doped region to widths of the source doped region in cross-sectional views along lines in the first direction are gradually increased along a direction away from the first gate strip.

DETAILED DESCRIPTION OF THE INVENTION

FIGS.1and3-5are schematic layouts of semiconductor devices500A,500B,500C and500D in accordance with some embodiments of the disclosure.FIG.2Ais a cross-sectional view of the semiconductor device500A along the A-A′ line ofFIG.1in accordance with some embodiments of the disclosure.FIG.2Bis a cross-sectional view of the semiconductor device500A along the B-B′ line ofFIG.1in accordance with some embodiments of the disclosure.FIG.2Cis a cross-sectional view of the semiconductor device500A along the C-C′ line ofFIG.1in accordance with some embodiments of the disclosure.FIG.2Dis a cross-sectional view of the semiconductor device500A along the D-D′ line ofFIG.1in accordance with some embodiments of the disclosure.FIG.2Eis a cross-sectional view of the semiconductor device500A along the E-E′ line ofFIG.1in accordance with some embodiments of the disclosure.FIGS.1and3-5only show some features for illustration, and the remaining features may be shown in the cross-sectional views ofFIGS.2A-2E. InFIG.1and the following figures, directions100and110may be referred to as a channel length direction and a channel width direction, respectively.

In some embodiments, the semiconductor device500A includes a power metal-oxide-semiconductor field effect transistor (MOSFET) device. As shown inFIG.1, the semiconductor device500A including four unit cells550may arrange as an array in a direction100with a pitch P1. In some embodiments, any two of the adjacent unit cells550may be in mirror symmetry. In addition, any two of the adjacent unit cells550may have the common-source or common-drain arrangement. It should be noted that the number of the unit cells550of the semiconductor device500A is merely an embodiment and not limited to the disclosed embodiment. In some embodiments, the unit cell550of the semiconductor device500A includes a substrate200, a gate strip210, a source doped region214, a body doped region216and a drain doped region218.

As shown inFIG.1, the substrate200has an active region300surrounded by an isolation feature (not shown). In some embodiments, the substrate200includes a semiconductor wafer or a silicon on insulator (SOI) wafer. The substrate200may be doped with dopants having a first conductivity type. When the first conductivity type is p-type, the substrate200is a p-type substrate. Alternatively, when the first conductivity type is n-type, the substrate200is an n-type substrate.

The unit cell550of the semiconductor device500A further includes a well region202formed in the substrate200within the active region300. In some embodiments, the well region202may be doped with dopants having the first conductivity type. When the semiconductor device500A is an NMOS, the substrate200is, for example, a P-type substrate, the well region202is, for example, a P-type well region. In some embodiments, the doping concentration of the well region202is greater than the doping concentration of the substrate200.

The gate strip210is disposed on the substrate200within the active region300, In some embodiments, the gate strip210extends substantially along the direction110. As shown inFIG.1, the gate strip210may have a first side210S1and a second side210S2along the direction110. In addition, the second side210S2is opposite to the first side210S1. In some embodiments, the gate strip210includes a gate insulating layer2101and a gate electrode layer210G. The gate insulating layer2101is formed on the substrate200. The gate electrode layer210G is formed on the gate insulating layer2101. In addition, spacers211are formed on the first side210S1and the second side210S2of the gate strip210. In some embodiments, a silicide feature (not shown) is formed on a top surface of the gate electrode layer210G.

The source doped region214and the drain doped region218are located in the substrate200within the active region300. The source doped region214and the drain doped region218are formed adjacent to the first side21051and the second side210S2of the gate strip210along the direction110, respectively. In some embodiments, the source doped region214and the drain doped region218may be doped with dopants having a second conductivity type opposite to the first conductivity type. For example, when the well region202is p-type, the source doped region214and the drain doped region218are n-type.

As shown inFIGS.1,2A-2C, the body doped region216is located in the substrate200within the active region300. The body doped region216and the source doped region214are arranged side by side and adjacent to the first sides210S1of the gate strips210of the adjacent unit cells550. In the unit cell550, the body doped regions216is adjacent to the source doped region214along the direction110. Furthermore, the body doped regions216and the source doped regions214are alternatively arranged along the direction110. The body doped region216may be provided as a pick-up dope region for the well region202. In some embodiments, both the body doped region216and the well region202have the same conductivity type (e.g., the first conductivity type). In addition, the body doped region216and the source doped region214have opposite conductivity types. For example, when the well region202is p-type and the source doped region214is n-type, the body doped region216is p-type. In some embodiments, the dopant concentration of the body doped region216is greater than that of the well region202.

In some embodiments, the body doped region216between the gate strips210of the adjacent unit cells550may have a polygonal shape (e.g., a triangular shape, a diamond shape shown inFIG.1, a pentagonal shape, a hexagonal shape shown inFIGS.3and4, a heptagonal shape, an octagonal shape shown inFIG.5or another suitable polygonal shape) in a top view shown inFIGS.1and3-5. In some other embodiments, the body doped region216between the gate strips210of the adjacent unit cells550may have polygonal shape with rounded corners.

As shown inFIG.1, the body doped region216has edges216B1,216B2,216B3and216B4, which may collectively serve as a boundary216B between the body doped region216and the source doped region214. However, the number of the edges of the body doped region216is not limited to the disclosure embodiments. The body doped region216may have least one edge close to the first side210S1(or the second side210S2) of the adjacent gate strip210. In addition, the edge of the body doped region216may meet the first side210S1(or the second side210S2) of the adjacent gate strip210. Alternatively, an extended line of the edge of the body doped region216may fully overlap the corresponding edge and meet the first side210S1(or the second side210S2) of the adjacent gate strip210. For example, in the semiconductor device500A, the body doped region216may have two edges216B1and216B4meeting the first side210S1of the adjacent gate strip210of the right unit cell550. In addition, the body doped region216may have two edges216B2and216B3meeting the first side210S1of the left gate strip210of left right unit cell550. In some embodiments, an angle θA1between the edge216B1of the body doped region216and the first side210S1of the right gate strip210is an acute angle. An angle θA2between the edge216B2of the body doped region216and the second side210S2of the left gate strip210is an acute angle. An angle θA3between the edge216B3of the body doped region216and the second side210S2of the left gate strip210is an acute angle. An angle θA4between the edge216B4of the body doped region216and the first side210S1of the right gate strip210is an acute angle. That is to say, the edges216B1,216B2,216B3and216B4(or the extended lines of the edges216B1,216B2,216B3and216B4) meeting the first side210S1or the second side210S2of the adjacent gate strip210may extend in directions that are not parallel to the directions100and110. Therefore, merely corner portions of the body doped region216would overlap the adjacent gate strips210. For example, the body doped region216merely has two opposite corners216C1and216C2overlapping the adjacent gate strips210. The overlapping area between the body doped region216and the adjacent gate strips210may be reduced. In some embodiments, a portion of the boundary216B between the body doped region216and the source doped regions214of the adjacent unit cells550may be V-shape or U-shape (or inversed V-shape or U-shape) in a top view as shown inFIG.1.

As shown inFIGS.1and2A-2C, in the direction110, the body doped region216may be composed of a center portion216C and two end portions216E. The center portion216C is located between the two end portions216E along the direction110. In addition, the body doped region216has a length L1along the direction100. In some embodiments, the length L1gradually changes along the direction110. For example, the length L1of the body doped region216may gradually be reduced from the center portion216C to the two end portions216E along the direction110, as shown inFIGS.2A-2B. That is to say, the body doped region216is tapered from the center portion216C to the two end portions216E. In some embodiments, the length L1has a maximum value at the center portion216C of the body doped region216. The maximum value of the length L1may be equal to the distance between the spacers211of the adjacent gate strips210, as shown inFIGS.1and2A.

As shown inFIGS.1,2D and2E, the body doped region216has a width W1along the direction110. In some embodiments, the width W1gradually changes along the direction100. For example, the width W1of the body doped region216gradually increases along the direction100away from the gate strip210, as shown inFIGS.2D and2E. That is to say, the body doped region216is tapered toward to the gate strip210along the direction100. In some embodiments, the width W1has a minimum value at a position closest to the adjacent gate strip210, as shown inFIGS.1and2D. In addition, the width W1may have a maximum value at a central position between the gate strips210of the adjacent unit cells550along the direction100, as shown inFIGS.1and2E.

As shown inFIG.1, the source doped region214is arranged adjacent to the body doped region216and the first sides210S1of the gate strips210of the adjacent unit cells550. In some embodiments, the source doped region214between the adjacent body doped regions216along the direction110and between the gate strips210of the adjacent unit cells550along the direction100may be hourglass-shaped in a top view as shown inFIG.1.

As shown inFIGS.1,2B and2C, in the direction110, the source doped region214may have two end portions214E and a center portion214C between the two end portions214E. The center portion214C of the source doped region214is connected (adjacent) to the end portions216E of the adjacent body doped regions216. In other words, the center portion216C of the body doped region216is connected (adjacent) to the end portions214E of the adjacent source doped regions214. In addition, the source doped region214has a second length L2along the direction100. In some embodiments, the second length L2gradually changes along the direction110. For example, the second length L2of the source doped region214may gradually be reduced from the center portion214C to the two end portions214E along the direction110, as shown inFIGS.1,2B and2C. For example, the source doped region214in the unit cell550is tapered from the center portion214C to the two end portions214E. In some embodiments, the length L2has a maximum value at the center portion214C of the source doped region214. The maximum value of the length L2may be equal to the distance between the adjacent spacers211, as shown inFIGS.1and2C. In addition, the maximum value of the length L2may be equal to the maximum value of the length L1, as shown inFIGS.2A and2C.

As shown inFIGS.1,2D and2E, the source doped region214has a width W2along the direction110. In some embodiments, the width W2gradually changes along the direction100. For example, the width W2of the source doped region214gradually reduces along the direction100away from the gate strip210, as shown inFIGS.2D and2E. That is to say, the body doped region216is tapered away from the gate strip210along the direction100. In some embodiments, the width W2may have a maximum value at a position closest to the gate strip210, as shown inFIG.2D. When the semiconductor device500A, for example, a NMOS, is operated (e.g., turns on), the current flows through the channel is increased. In some embodiments, the width W2has a minimum value at the central position between the adjacent gate strips210along the direction110, as shown inFIG.2E. In some embodiments, the width W1of the body doped region216at a position closest to the gate strip210is less than the width W2at a position closest to the same gate strip210, as shown inFIG.2E.

In some embodiments, ratios of the widths W1of the body doped region216to the widths W2of the source doped region214in the cross-sectional views along the lines in the direction110(e.g., the cross-sectional views along the D-D′ and E-E′ lines in the direction110shown inFIGS.2D and2E) are gradually increased along the direction100away from the gate strip210. As shown inFIG.2D, the ratio of the width W1of the body doped region216to the width W2of the source doped region214in the cross-sectional view along the D-D′ line in the direction110and closest to the gate strip210is less than 1. In other words, the width W1of the body doped region216is less than the width W2of the source doped region214in the cross-sectional view along the D-D′ line in the direction110and closest to the gate strip210, as shown inFIG.2D.

As shown inFIGS.2A-2C, the semiconductor device500A further includes lightly-doped regions212located in the substrate200within the active region300. The lightly-doped regions212are formed adjacent to the first side210S1and the second side210S2of the gate strip210. In addition, the lightly-doped regions212are formed adjacent to the source doped region214and the drain doped region218and extend below the spacers211along the direction100. In some embodiments, the lightly-doped region212may be doped with dopants having a second conductivity type opposite to the first conductivity type. For example, when the well region202is p-type, the lightly-doped region212is n-type. In addition, the dopant concentration of the lightly-doped region212is less than those of the source doped region214and the drain doped region218.

As shown inFIGS.1and2A-2E, the semiconductor device500A further includes body contacts226, source contacts224and drain contacts228disposed on the substrate200within the body doped region216, the source doped region214and the drain doped region218. The body contacts226and the source contacts224are disposed at the central position between the first sides210S1of the gate strips210of the adjacent unit cells550along the direction100. In addition, the drain contacts228are disposed at the central position between the second sides210S2of the gate strips210of the adjacent unit cells550along the direction100. As shown inFIG.1, the body contacts226and the source contacts224are alternatively arranged along the direction110by a pitch P2according the design rule. In addition, the drain contacts228are arranged along the direction110by the pitch P2. The source contact224is disposed close to one of the end portions216E of the body doped region216. In some embodiments, the width W1of the body doped region216has a maximum value at a position where the body contact226is located, as shown inFIG.2E. In addition, the width W1of the body doped region216has the maximum value greater than the pitch P2and less than two time as much as the pitch P2(i.e., P2<W1<2P2). If the maximum value of the width W1of the body doped region216is less than the pitch P2, the current flowing through the body contact226would be reduced. If the width W1of the body doped region216is greater than two time as much as the pitch P2, the adjacent body doped regions216would be connected to each other, so that there would be no enough space for arranging the source doped region214and the source contact224within the source doped region214. In some embodiments, the width W2of the source doped region214has a minimum value at a position where the source contact224is located, as shown inFIG.2E. In some embodiments, the ratio of the width W1of the body doped region216to the width W2of the source doped region214in the cross-sectional view along the line crossing the body contact226and the source contact224in the direction110is greater than 1 and less than 2. In other words, the width W1of the body doped region216is greater than the width W2of the source doped region214in the cross-sectional view along the line crossing the body contact226and the source contact224in the direction110, as shown inFIG.2E.

FIG.3is a schematic layout of a semiconductor device500B in accordance with some embodiments of the disclosure. Elements of the embodiments hereinafter, that are the same or similar as those previously described with reference toFIGS.1and2A-2Care not repeated for brevity. As shown inFIG.3, the difference between the semiconductor device500A and the semiconductor device500B is that the semiconductor device500B includes a body doped region236with a hexagonal shape. In some embodiments, the body doped region236includes a boundary236B including edges236B1,236B2,236B3,236B4,236B5and236B6. The edges236B1,236B3,236B4and236B6may meet the first sides210S1of the gate strips210of the adjacent unit cells550. In some embodiments, an angle θB1between the edge236B1and the first side210S1of the right gate strip210is an acute angle. An angle θB2between the edge236B3and the second side210S2of the left gate strip210is an acute angle. An angle θB3between the edge236B4and the second side210S2of the left gate strip210is an acute angle. An angle θB4between the edge236B6and the first side210S1of the right gate strip210is an acute angle. In addition, the body doped region236merely has two opposite corners236C1and236C2overlapping the gate strips210of the adjacent unit cells550.

FIG.4is a schematic layout of a semiconductor device500C in accordance with some embodiments of the disclosure. Elements of the embodiments hereinafter, that are the same or similar as those previously described with reference toFIGS.1,2A-2C and3are not repeated for brevity. As shown inFIG.4, the difference between the semiconductor device500A and the semiconductor device500C is that the semiconductor device500C includes a body doped region246with a hexagonal shape. In some embodiments, the body doped region246a boundary246B including edges246B1,246B2,246B3,246B4,246B5and246B6. The body doped region246does not overlap the adjacent gate strips210at all. In addition, extended lines246E1,246E2,246E4and246E5of the edges246B1,246B2,246B4and246B5of the body doped region246may meet the first side210S1(or the second side210S2) of the adjacent gate strips210. In some embodiments, an angle θC1between the extended line246E1and the first side210S1of the right gate strip210is an acute angle. An angle θC2between the extended line246E2and the second side210S2of the left gate strip210is an acute angle. An angle θC3between the extended line246E4and the second side210S2of the left gate strip210is an acute angle. An angle θC4between the extended line246E5and the first side210S1of the right gate strip210is an acute angle.

FIG.5is a schematic layout of a semiconductor device500D in accordance with some embodiments of the disclosure. Elements of the embodiments hereinafter, that are the same or similar as those previously described with reference toFIGS.1,2A-2C and3-4are not repeated for brevity. As shown inFIG.4, the difference between the semiconductor device500A and the semiconductor device500D is that the semiconductor device500D includes a body doped region256with an octagonal shape. In some embodiments, the body doped region256including edges256B1,256B2,256B3,256B4,256B5,256B6,256B7and256B8does not overlap the adjacent gate strips210. In addition, extended lines256E1,246E3,256E5and256E7of the edges256B1,256B32,256B5and256B7of the body doped region256may meet the first side210S1(or the second side210S2) of the adjacent gate strips210. In some embodiments, an angle θD1between the extended line2546E1and the first side210S1of the right gate strip210is an acute angle. An angle θD2between the extended line256E3and the second side210S2of the left gate strip210is an acute angle. An angle θD3between the extended line256E5and the second side210S2of the left gate strip210is an acute angle. An angle θD4between the extended line256E7and the first side210S1of the right gate strip210is an acute angle.

In the conventional power MOS device, the body doped region and the source doped region of opposite conductivities are arranged at the same side of the gate strip extending along the channel width direction. The body doped region and the source doped region are arranged side-by-side along the channel width direction and have a slit-shape extending along the channel length direction. The sides of the body doped region are perpendicular or parallel to the adjacent side of the gate strip extending along the channel width direction. In other words, all sides of the body doped region should extend parallel to the channel length direction (i.e. the direction100) or the channel width direction (i.e., the direction110). Therefore, the sides of the conventional body doped region and the adjacent side of the gate strip would meet at an angle of 90 degrees or a multiple of 90 degrees. In addition, the slit-shaped body doped region has at least an edge portion (including two corner portions) partially overlapping the adjacent gate strip according to the design rule. The dopant of the body doped region of the conductivity opposite that of the source doped region may diffuse into the gate strip, thereby causing increased on-resistance (Ron) and partially turn-on problems. Compared with the conventional power MOS device with the slit-shaped body doped region, the body doped region of the semiconductor device in the same area is designed to have at least one oblique edge meeting the first side (or the second side) of the adjacent gate strip. Alternatively, the body doped region of the semiconductor device may not overlap the adjacent gate strip and an extended line of the oblique edge of the body doped region may meet the first side (or the second side) of the adjacent gate strip. Therefore, an angle between the oblique edge of the body doped region (or the extended line of the oblique edge of the body doped region) and the first side (or the second side) of the adjacent gate strip is an acute angle (greater than 90 degrees and less than 180 degrees). In other words, the oblique edge of the body doped region (or the extended line of the oblique edge of the body doped region) that meets the first side (or the second side) of the adjacent gate strip may extend in a direction that is not parallel to the channel length direction (i.e. the direction100) or the channel width direction (i.e., the direction110). The portion of the body doped region overlapping the adjacent gate strip may have a reduced area. The source doped region may have a maximum width (e.g., the width W2shown inFIG.2D) in the channel width direction (i.e., the direction110) at the position closest to the adjacent gate strip. When the semiconductor device, for example, a NMOS, is operated (e.g., turns on), the current flows through the channel (illustrated as dotted arrows shown inFIGS.1and3-5) is increased. Therefore, the semiconductor device may have a reduced on-resistance (Ron) and an increased on-state current (Ion).