TECHNOLOGIES FOR THIN FILM RESISTORS IN VIAS

Techniques for thin-film resistors in vias are disclosed. In the illustrative embodiment, thin-film resistors are formed in through-glass vias of a glass substrate of an interposer. The thin-film resistors do not take up a significant amount of area on a layer of the interposer, as the thin-film resistor extends vertically through a via rather than horizontally on a layer of the interposer. The thin-film resistors may be used for any suitable purpose, such as power dissipation or voltage control, current control, as a pull-up or pull-down resistor, etc.

BACKGROUND

Modern integrated circuits may have a large number of conductive traces connecting different components in the integrated circuit. In some cases, an interposer may be used to spread traces of an integrated circuit to a wider pitch or reroute connections. The integrated circuit and/or the interposer may include components such as resistors or capacitors, either as bulk components mounted on a surface or as components formed as part of a layer.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring toFIGS.1-3, in one embodiment, an illustrative system100includes a circuit board, an interposer104, and one or more integrated circuit components106.FIG.2shows a cross-sectional view of the system100taken along perspective2shown inFIG.1, andFIG.3shows a cross-sectional view of the system100taken along perspective3shown inFIG.1. As shown inFIG.2, the illustrative interposer104includes a first dielectric layer, a substrate204, and a second dielectric layer206.

In the illustrative embodiment, several through-substrate vias are defined in the substrate204. In the illustrative embodiment, the substrate204is glass, and the through-substrate vias are through-glass vias. Some or all of the through-substrate vias include a thin-film resistor208defined around an outer wall of the vias, and the through-substrate vias may have a dielectric plug filler212positioned inside the thin-film resistor208. In some cases, a trace210may connect two through-substrate vias, as shown inFIG.2. The trace210may allow for two or more thin-film resistors208to be connected in series or parallel. The trace210may be made of the same material as the thin-film resistor208, or the trace210may be made of another conductive material such as copper.

The thin-film resistors208may be connected to pads214positioned on top of or on bottom of the through-substrate via. A via216may connect the pads214to the top or bottom surface of the interposer104. It should be appreciated that, as used herein, the “top surface,” “bottom surface,” etc., of components such as the interposer104is an arbitrary designation used for clarity and does not denote a particular required orientation for manufacture or use.

The interposer104may be connected to a circuit board102and/or one or more integrated circuit components106through one or more coupling components218. In the illustrative embodiment, coupling components218are solder balls. In other embodiments, the coupling components218may be embodied as pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. The circuit board102and/or the one or more integrated circuits may include contacts220or other pads, pins, traces, etc., that connect to the coupling components218. The interposer104may change the pitch of connections or reroute connections from the coupling components218connected to the circuit board102to the coupling components218connected to one or more integrated circuit components106. In some embodiments, the interposer104may provide one or more connections from one integrated circuit component106to another integrated circuit component106.

In the illustrative embodiment, the circuit board102is a fiberglass board made of glass fibers and a resin, such as FR-4. In other embodiments, any suitable circuit board102may be used. In some embodiments, another component may be mated with the bottom side of the interposer104, such as an integrated circuit component, a substrate, another interposer, etc. Each of the dielectric layers202,206may be any suitable material, such as silicon oxide.

The integrated circuit component106may be any integrated circuit component, such as a processor, a memory die, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a graphics processing unit (GPU), and/or the like.

In the illustrative embodiment, the substrate204of the interposer104is glass. The substrate204may be, e.g., silicon oxide, fused silica, borosilicate glass, ion-exchange glass, etc. In other embodiments, the substrate204of the interposer may be a different material, such as silicon, sapphire, a ceramic material, an organic material, etc. The pads214and/or the vias216may be made of any suitable conductive material, such as copper.

In the illustrative embodiment, the thin-film resistor208may be formed from a high-resistivity conductive material, such as titanium nitride, tantalum nitride, ruthenium oxide, aluminum oxide, etc. As used herein, a thin-film resistor is made of a material that has a resistivity of 10−6-1014Ω·cm, unless explicitly noted otherwise. The thin-film resistor208may have any resistivity in that range, such as 1-1,000 μΩ·cm. The thin-film resistor208may have any suitable dimensions, such as a height of 200 micrometers to 3 millimeters. The thin-film resistor208may have any suitable thickness, such as 10-5,000 nanometers. In some embodiments, the thin-film resistor208may fully fill the via. The via in which the thin-film resistor208is defined may have any suitable diameter, such as 50-500 micrometers. The via in which the thin-film resistor208is defined may have any suitable aspect ratio (i.e., height/diameter ratio), such as 1-20. The dimensions of the thin-film resistor may depend on a desired resistance, such as an equivalent series resistance (ESR) requirement, a voltage requirement, a current requirement, etc.

The thin-film resistor208may be used for any suitable purpose, such as power dissipation or voltage control, current control, as a pull-up or pull-down resistor, etc. In some embodiments, the thin-film resistors208may be used to move power delivery or voltage stepdown closer to an integrated circuit component106. It should be appreciated that the thin-film resistors208do not take up a significant amount of area on a layer of the interposer104, as the thin-film resistor208extends vertically through a via rather than horizontally on a layer of the interposer104.

The plug filler212may be any suitable material, such as silicon oxide, silicon nitride, a polymer, etc. In the illustrative embodiment, the vias in which the thin-film resistors208is defined has a circular cross-section, as shown inFIG.3. In other embodiments, the vias may have any suitable shape, such as a square, a rectangle, an ellipse, etc.

In the illustrative embodiment, the interposer104has two layers, a top layer and a bottom layer. In other embodiments, the interposer104may include additional layers between the top layer and the bottom layer.

Referring now toFIG.4, in one embodiment, a method400for creating thin-film resistors in through-substrate vias is shown.FIGS.5-11show cross-sectional views of the interposer104that correspond to different stages of the method400. The method400begins in block402, in which through-substrate vias502are created in a substrate204of an interposer104, as shown inFIG.5. In the illustrative embodiment, the substrate204is glass, and the vias502are created using, e.g., laser drilling or by laser treating the substrate204and then removing the treated portion with hydrofluoric acid or other chemical treatment.

In block404, a thin film602is grown on the substrate204. In the illustrative embodiment, the thin film602is grown using atomic layer deposition. In other embodiments, the thin film602may be grown using physical layer deposition, chemical layer deposition, etc. In some embodiments, such as atomic layer deposition, the thin film602may be applied at a temperature over 300° C., such as a temperature up to 500-800° C. In other embodiments, the thin film602may be applied using, e.g., low-temperature chemical vapor deposition, low-temperature atomic layer deposition, etc.

In block406, the vias502are filled in with a plug filler212, as shown inFIG.7. The plug filler212may be any suitable material, such as silicon oxide, silicon nitride, a polymer, etc. In some embodiments, the plug filler212may be applied using, e.g., jet printing, a squeegee process, chemical vapor deposition, physical vapor deposition, etc.

In block408, the excess thin film602and excess plug filler212on some or all of the surfaces of the substrate204are removed, as shown inFIG.8. The excess thin film602and excess plug filler212may be removed in any suitable manner, such as planarization, etching, etc., In some embodiments, some parts of the thin film602may be protected from etching using lithographic patterning of a mask, such as traces210. In other embodiments, the traces210may be added after the excess thin film602is removed. In such embodiments, the traces210may cover the plug filler212. In some embodiments, additional thin film may be grown over some or all of the excess plug filler212. The additional thin film cap over the excess plug filler212may have any suitable width, such as the same width as the via, the same width as the pad214, or wider than the pad214.

In block410, pads902are formed over the thin-film resistors208in the vias, as shown inFIG.9. The pads902may be formed in any suitable manner, such as electroless plating. In some embodiments, nucleation sites made of, e.g., platinum may be deposited, and copper pads902may be grown on the nucleation sites.

In block412, dielectric layers202,206are formed on the substrate204, as shown inFIG.10. The dielectric layers202,206may be, e.g., silicon oxide. In block414, vias216are formed through the dielectric layers202,206to the pads214, as shown inFIG.11. After any other standard packing processes that are to be applied, the interposer104may then be mated with, e.g., a circuit board102, integrated circuit components106, etc.

FIG.12is a top view of a wafer1200and dies1202that may be included in any of the systems disclosed herein. The wafer1200may be composed of semiconductor material and may include one or more dies1202having integrated circuit structures formed on a surface of the wafer1200. The individual dies1202may be a repeating unit of an integrated circuit product that includes any suitable integrated circuit. After the fabrication of the semiconductor product is complete, the wafer1200may undergo a singulation process in which the dies1202are separated from one another to provide discrete “chips” of the integrated circuit product. The die1202may include one or more transistors (e.g., some of the transistors1340ofFIG.13, discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and/or any other integrated circuit components. In some embodiments, the wafer1200or the die1202may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die1202. For example, a memory array formed by multiple memory devices may be formed on a same die1202as a processor unit (e.g., the processor unit1602ofFIG.16) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. Various ones of the systems disclosed herein may be manufactured using a die-to-wafer assembly technique in which some dies114are attached to a wafer1200that include others of the dies114, and the wafer1200is subsequently singulated.

FIG.13is a cross-sectional side view of an integrated circuit device1300that may be included in any of the systems disclosed herein. One or more of the integrated circuit devices1300may be included in one or more dies1202(FIG.12). The integrated circuit device1300may be formed on a die substrate1302(e.g., the wafer1200ofFIG.12) and may be included in a die (e.g., the die1202ofFIG.12). The die substrate1302may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The die substrate1302may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate1302may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the die substrate1302. Although a few examples of materials from which the die substrate1302may be formed are described here, any material that may serve as a foundation for an integrated circuit device1300may be used. The die substrate1302may be part of a singulated die (e.g., the dies1202ofFIG.12) or a wafer (e.g., the wafer1200ofFIG.12).

The integrated circuit device1300may include one or more device layers1304disposed on the die substrate1302. The device layer1304may include features of one or more transistors1340(e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate1302. The transistors1340may include, for example, one or more source and/or drain (S/D) regions1320, a gate1322to control current flow between the S/D regions1320, and one or more S/D contacts1324to route electrical signals to/from the S/D regions1320. The transistors1340may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors1340are not limited to the type and configuration depicted inFIG.13and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon, nanosheet, or nanowire transistors.

FIGS.14A-14Dare simplified perspective views of example planar, FinFET, gate-all-around, and stacked gate-all-around transistors. The transistors illustrated inFIGS.14A-14Dare formed on a substrate1416having a surface1408. Isolation regions1414separate the source and drain regions of the transistors from other transistors and from a bulk region1418of the substrate1416.

FIG.14Ais a perspective view of an example planar transistor1400comprising a gate1402that controls current flow between a source region1404and a drain region1406. The transistor1400is planar in that the source region1404and the drain region1406are planar with respect to the substrate surface1408.

FIG.14Bis a perspective view of an example FinFET transistor1420comprising a gate1422that controls current flow between a source region1424and a drain region1426. The transistor1420is non-planar in that the source region1424and the drain region1426comprise “fins” that extend upwards from the substrate surface1428. As the gate1422encompasses three sides of the semiconductor fin that extends from the source region1424to the drain region1426, the transistor1420can be considered a tri-gate transistor.FIG.14Billustrates one S/D fin extending through the gate1422, but multiple S/D fins can extend through the gate of a FinFET transistor.

FIG.14Cis a perspective view of a gate-all-around (GAA) transistor1440comprising a gate1442that controls current flow between a source region1444and a drain region1446. The transistor1440is non-planar in that the source region1444and the drain region1446are elevated from the substrate surface1428.

FIG.14Dis a perspective view of a GAA transistor1460comprising a gate1462that controls current flow between multiple elevated source regions1464and multiple elevated drain regions1466. The transistor1460is a stacked GAA transistor as the gate controls the flow of current between multiple elevated S/D regions stacked on top of each other. The transistors1440and1460are considered gate-all-around transistors as the gates encompass all sides of the semiconductor portions that extends from the source regions to the drain regions. The transistors1440and1460can alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors depending on the width (e.g., widths1448and1468of transistors1440and1460, respectively) of the semiconductor portions extending through the gate.

Returning toFIG.13, a transistor1340may include a gate1322formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material.

The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor1340is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

The S/D regions1320may be formed within the die substrate1302adjacent to the gate1322of individual transistors1340. The S/D regions1320may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate1302to form the S/D regions1320. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate1302may follow the ion-implantation process. In the latter process, the die substrate1302may first be etched to form recesses at the locations of the S/D regions1320. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions1320. In some implementations, the S/D regions1320may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions1320may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions1320.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors1340) of the device layer1304through one or more interconnect layers disposed on the device layer1304(illustrated inFIG.13as interconnect layers1306-1310). For example, electrically conductive features of the device layer1304(e.g., the gate1322and the S/D contacts1324) may be electrically coupled with the interconnect structures1328of the interconnect layers1306-1310. The one or more interconnect layers1306-1310may form a metallization stack (also referred to as an “ILD stack”)1319of the integrated circuit device1300.

The interconnect structures1328may be arranged within the interconnect layers1306-1310to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures1328depicted inFIG.13. Although a particular number of interconnect layers1306-1310is depicted inFIG.13, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures1328may include lines1328aand/or vias1328bfilled with an electrically conductive material such as a metal. The lines1328amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate1302upon which the device layer1304is formed. For example, the lines1328amay route electrical signals in a direction in and out of the page and/or in a direction across the page. The vias1328bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate1302upon which the device layer1304is formed. In some embodiments, the vias1328bmay electrically couple lines1328aof different interconnect layers1306-1310together.

The interconnect layers1306-1310may include a dielectric material1326disposed between the interconnect structures1328, as shown inFIG.13. In some embodiments, dielectric material1326disposed between the interconnect structures1328in different ones of the interconnect layers1306-1310may have different compositions; in other embodiments, the composition of the dielectric material1326between different interconnect layers1306-1310may be the same. The device layer1304may include a dielectric material1326disposed between the transistors1340and a bottom layer of the metallization stack as well. The dielectric material1326included in the device layer1304may have a different composition than the dielectric material1326included in the interconnect layers1306-1310; in other embodiments, the composition of the dielectric material1326in the device layer1304may be the same as a dielectric material1326included in any one of the interconnect layers1306-1310.

A first interconnect layer1306(referred to as Metal 1 or “M1”) may be formed directly on the device layer1304. In some embodiments, the first interconnect layer1306may include lines1328aand/or vias1328b,as shown. The lines1328aof the first interconnect layer1306may be coupled with contacts (e.g., the S/D contacts1324) of the device layer1304. The vias1328bof the first interconnect layer1306may be coupled with the lines1328aof a second interconnect layer1308.

The second interconnect layer1308(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer1306. In some embodiments, the second interconnect layer1308may include via1328bto couple the lines1328of the second interconnect layer1308with the lines1328aof a third interconnect layer1310. Although the lines1328aand the vias1328bare structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines1328aand the vias1328bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

The third interconnect layer1310(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer1308according to similar techniques and configurations described in connection with the second interconnect layer1308or the first interconnect layer1306. In some embodiments, the interconnect layers that are “higher up” in the metallization stack1319in the integrated circuit device1300(i.e., farther away from the device layer1304) may be thicker that the interconnect layers that are lower in the metallization stack1319, with lines1328aand vias1328bin the higher interconnect layers being thicker than those in the lower interconnect layers.

The integrated circuit device1300may include a solder resist material1334(e.g., polyimide or similar material) and one or more conductive contacts1336formed on the interconnect layers1306-1310. InFIG.13, the conductive contacts1336are illustrated as taking the form of bond pads. The conductive contacts1336may be electrically coupled with the interconnect structures1328and configured to route the electrical signals of the transistor(s)1340to external devices. For example, solder bonds may be formed on the one or more conductive contacts1336to mechanically and/or electrically couple an integrated circuit die including the integrated circuit device1300with another component (e.g., a printed circuit board). The integrated circuit device1300may include additional or alternate structures to route the electrical signals from the interconnect layers1306-1310; for example, the conductive contacts1336may include other analogous features (e.g., posts) that route the electrical signals to external components. The conductive contacts1336may serve as the conductive contacts220or216, as appropriate.

In some embodiments in which the integrated circuit device1300is a double-sided die, the integrated circuit device1300may include another metallization stack (not shown) on the opposite side of the device layer(s)1304. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers1306-1310, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s)1304and additional conductive contacts (not shown) on the opposite side of the integrated circuit device1300from the conductive contacts1336. These additional conductive contacts may serve as the conductive contacts220or216, as appropriate.

In other embodiments in which the integrated circuit device1300is a double-sided die, the integrated circuit device1300may include one or more through silicon vias (TSVs) through the die substrate1302; these TSVs may make contact with the device layer(s)1304, and may provide conductive pathways between the device layer(s)1304and additional conductive contacts (not shown) on the opposite side of the integrated circuit device1300from the conductive contacts1336. These additional conductive contacts may serve as the conductive contacts220or216, as appropriate. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device1300from the conductive contacts1336to the transistors1340and any other components integrated into the die1300, and the metallization stack1319can be used to route I/O signals from the conductive contacts1336to transistors1340and any other components integrated into the die1300.

Multiple integrated circuit devices1300may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).

FIG.15is a cross-sectional side view of an integrated circuit device assembly1500that may include any of the interposers104disclosed herein. The integrated circuit device assembly1500includes a number of components disposed on a circuit board1502(which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly1500includes components disposed on a first face1540of the circuit board1502and an opposing second face1542of the circuit board1502; generally, components may be disposed on one or both faces1540and1542.

In some embodiments, the circuit board1502may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board1502. In other embodiments, the circuit board1502may be a non-PCB substrate. In some embodiments the circuit board1502may be, for example, the circuit board102. The integrated circuit device assembly1500illustrated inFIG.15includes a package-on-interposer structure1536coupled to the first face1540of the circuit board1502by coupling components1516. The coupling components1516may electrically and mechanically couple the package-on-interposer structure1536to the circuit board1502, and may include solder balls (as shown inFIG.15), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. The coupling components1516may serve as the coupling components illustrated or described for any of the substrate assembly or substrate assembly components described herein, as appropriate.

The package-on-interposer structure1536may include an integrated circuit component1520coupled to an interposer1504by coupling components1518. The coupling components1518may take any suitable form for the application, such as the forms discussed above with reference to the coupling components1516. Although a single integrated circuit component1520is shown inFIG.15, multiple integrated circuit components may be coupled to the interposer1504; indeed, additional interposers may be coupled to the interposer1504. The interposer1504may provide an intervening substrate used to bridge the circuit board1502and the integrated circuit component1520. The interposer1504may be embodied as any interposer104disclosed herein.

The integrated circuit component1520may be a packaged or unpacked integrated circuit product that includes one or more integrated circuit dies (e.g., the die1202ofFIG.12, the integrated circuit device1300ofFIG.13) and/or one or more other suitable components. A packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate with the integrated circuit dies and package substrate encapsulated in a casing material, such as a metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component1520, a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer1504. The integrated circuit component1520can comprise one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I/O controller, memory, or network interface controller. In some embodiments, the integrated circuit component1520can comprise one or more additional active or passive devices such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

In embodiments where the integrated circuit component1520comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).

In addition to comprising one or more processor units, the integrated circuit component1520can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.

Generally, the interposer1504may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer1504may couple the integrated circuit component1520to a set of ball grid array (BGA) conductive contacts of the coupling components1516for coupling to the circuit board1502. In the embodiment illustrated inFIG.15, the integrated circuit component1520and the circuit board1502are attached to opposing sides of the interposer1504; in other embodiments, the integrated circuit component1520and the circuit board1502may be attached to a same side of the interposer1504. In some embodiments, three or more components may be interconnected by way of the interposer1504.

In some embodiments, the interposer1504may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer1504may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer1504may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer1504may include metal interconnects1508and vias1510, including but not limited to through hole vias1510-1(that extend from a first face1550of the interposer1504to a second face1554of the interposer1504), blind vias1510-2(that extend from the first or second faces1550or1554of the interposer1504to an internal metal layer), and buried vias1510-3(that connect internal metal layers).

In some embodiments, the interposer1504can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer1504comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer1504to an opposing second face of the interposer1504.

The interposer1504may further include embedded devices1514, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer1504. The package-on-interposer structure1536may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board

The integrated circuit device assembly1500may include an integrated circuit component1524coupled to the first face1540of the circuit board1502by coupling components1522. The coupling components1522may take the form of any of the embodiments discussed above with reference to the coupling components1516, and the integrated circuit component1524may take the form of any of the embodiments discussed above with reference to the integrated circuit component1520.

The integrated circuit device assembly1500illustrated inFIG.15includes a package-on-package structure1534coupled to the second face1542of the circuit board1502by coupling components1528. The package-on-package structure1534may include an integrated circuit component1526and an integrated circuit component1532coupled together by coupling components1530such that the integrated circuit component1526is disposed between the circuit board1502and the integrated circuit component1532. The coupling components1528and1530may take the form of any of the embodiments of the coupling components1516discussed above, and the integrated circuit components1526and1532may take the form of any of the embodiments of the integrated circuit component1520discussed above. The package-on-package structure1534may be configured in accordance with any of the package-on-package structures known in the art.

FIG.16is a block diagram of an example electrical device1600that may include one or more of the interposers104disclosed herein. For example, any suitable ones of the components of the electrical device1600may include one or more of the integrated circuit device assemblies1500, integrated circuit components1520, integrated circuit devices1300, or integrated circuit dies1202disclosed herein, and may interface with any of the interposers104disclosed herein. A number of components are illustrated inFIG.16as included in the electrical device1600, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device1600may be attached to one or more motherboards mainboards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the electrical device1600may not include one or more of the components illustrated inFIG.16, but the electrical device1600may include interface circuitry for coupling to the one or more components. For example, the electrical device1600may not include a display device1606, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device1606may be coupled. In another set of examples, the electrical device1600may not include an audio input device1624or an audio output device1608, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device1624or audio output device1608may be coupled.

The electrical device1600may include a memory1604, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory1604may include memory that is located on the same integrated circuit die as the processor unit1602. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, the electrical device1600can comprise one or more processor units1602that are heterogeneous or asymmetric to another processor unit1602in the electrical device1600. There can be a variety of differences between the processing units1602in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units1602in the electrical device1600.

In some embodiments, the electrical device1600may include a communication component1612(e.g., one or more communication components). For example, the communication component1612can manage wireless communications for the transfer of data to and from the electrical device1600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

In some embodiments, the communication component1612may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component1612may include multiple communication components. For instance, a first communication component1612may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component1612may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component1612may be dedicated to wireless communications, and a second communication component1612may be dedicated to wired communications.

The electrical device1600may include battery/power circuitry1614. The battery/power circuitry1614may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device1600to an energy source separate from the electrical device1600(e.g., AC line power).

The electrical device1600may include a display device1606(or corresponding interface circuitry, as discussed above). The display device1606may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device1600may include an audio output device1608(or corresponding interface circuitry, as discussed above). The audio output device1608may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.

The electrical device1600may include an audio input device1624(or corresponding interface circuitry, as discussed above). The audio input device1624may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device1600may include a Global Navigation Satellite System (GNSS) device1618(or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device1618may be in communication with a satellite-based system and may determine a geolocation of the electrical device1600based on information received from one or more GNSS satellites, as known in the art.

The electrical device1600may include an other output device1610(or corresponding interface circuitry, as discussed above). Examples of the other output device1610may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The electrical device1600may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device1600may be any other electronic device that processes data. In some embodiments, the electrical device1600may comprise multiple discrete physical components. Given the range of devices that the electrical device1600can be manifested as in various embodiments, in some embodiments, the electrical device1600can be referred to as a computing device or a computing system.

As used in any embodiment herein, the term “module” refers to logic that may be implemented in a hardware component or device, software or firmware running on a processor, or a combination thereof, to perform one or more operations consistent with the present disclosure. Software may be embodied as a software package, code, instructions, instruction sets and/or data recorded on non-transitory computer readable storage mediums. Firmware may be embodied as code, instructions or instruction sets and/or data that are hard-coded (e.g., nonvolatile) in memory devices. As used in any embodiment herein, the term “circuitry” can comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry such as computer processors comprising one or more individual instruction processing cores, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. Modules described herein may, collectively or individually, be embodied as circuitry that forms a part of one or more devices. Thus, any of the modules can be implemented as circuitry. A computing system referred to as being programmed to perform a method can be programmed to perform the method via software, hardware, firmware or combinations thereof.

The computer-executable instructions or computer program products as well as any data created and used during implementation of the disclosed technologies can be stored on one or more tangible or non-transitory computer-readable storage media, such as optical media discs (e.g., DVDs, CDs), volatile memory components (e.g., DRAM, SRAM), or non-volatile memory components (e.g., flash memory, solid-state drives, chalcogenide-based phase-change non-volatile memories). Computer-readable storage media can be contained in computer-readable storage devices such as solid-state drives, USB flash drives, and memory modules. Alternatively, the computer-executable instructions may be performed by specific hardware components that contain hardwired logic for performing all or a portion of disclosed methods, or by any combination of computer-readable storage media and hardware components.

The computer-executable instructions can be part of, for example, a dedicated software application or a software application that is accessed via a web browser or other software application (such as a remote computing application). Such software can be read and executed by, for example, a single computing device or in a network environment using one or more networked computers. Further, it is to be understood that the disclosed technology is not limited to any specific computer language or program. For instance, the disclosed technologies can be implemented by software written in C++, Java, Perl, Python, JavaScript, Adobe Flash, or any other suitable programming language. Likewise, the disclosed technologies are not limited to any particular computer or type of hardware.

As used in this application and in the claims, a list of items joined by the term “and/or” can mean any combination of the listed items. For example, the phrase “A, B and/or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. As used in this application and in the claims, a list of items joined by the term “at least one of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. Moreover, as used in this application and in the claims, a list of items joined by the term “one or more of” can mean any combination of the listed terms. For example, the phrase “one or more of A, B and C” can mean A; B; C; A and B; A and C; B and C; or A, B, and C.

EXAMPLES

Example 1 includes a device comprising a substrate comprising a first layer; a second layer; and one or more vias that extend from the first layer to the second layer, wherein, for individual vias of the one or more vias, a thin-film resistor is defined in the corresponding via.

Example 2 includes the subject matter of Example 1, and wherein individual vias of the one or more vias have a height/diameter ratio of at least 8.

Example 3 includes the subject matter of any of Examples 1 and 2, and wherein, for individual vias of the one or more vias, the thin-film resistor has a thickness between 20 and 100 nanometers.

Example 4 includes the subject matter of any of Examples 1-3, and further including a trace on the first layer, the trace connecting the thin-film resistors of two of the one or more vias.

Example 5 includes the subject matter of any of Examples 1-4, and further including a circuit board coupled to the one or more vias on the first layer; and an integrated circuit component coupled to the one or more vias on the second layer.

Example 6 includes the subject matter of any of Examples 1-5, and wherein the integrated circuit component is a processor.

Example 7 includes the subject matter of any of Examples 1-6, and wherein, for individual vias of the one or more vias, the thin-film resistor comprises titanium and nitrogen.

Example 8 includes the subject matter of any of Examples 1-7, and wherein, for individual vias of the one or more vias, the thin-film resistor comprises tantalum and nitrogen.

Example 9 includes the subject matter of any of Examples 1-8, and wherein, for individual vias of the one or more vias, the thin-film resistor comprises ruthenium and oxygen.

Example 10 includes the subject matter of any of Examples 1-9, and wherein, for individual vias of the one or more vias, the thin-film resistor comprises aluminum and oxygen.

Example 11 includes the subject matter of any of Examples 1-10, and wherein the substrate comprises silicon and oxygen.

Example 12 includes the subject matter of any of Examples 1-11, and wherein the substrate comprises silicon.

Example 13 includes a device comprising a substrate comprising a first layer; a second layer; and one or more vias that extend from the first layer to the second layer, wherein, for individual vias of the one or more vias, a resistive layer having a resistivity between 1 and 1,000 microohm-centimeters is defined in the corresponding via.

Example 14 includes the subject matter of Example 13, and wherein individual vias of the one or more vias have a height/diameter ratio of at least 8.

Example 15 includes the subject matter of any of Examples 13 and 14, and wherein, for individual vias of the one or more vias, the resistive layer has a thickness between 20 and 100 nanometers.

Example 16 includes the subject matter of any of Examples 13-15, and further including a trace on the first layer, the trace connecting the resistive layers of two of the one or more vias.

Example 17 includes the subject matter of any of Examples 13-16, and further including a circuit board coupled to the one or more vias on the first layer; and an integrated circuit component coupled to the one or more vias on the second layer.

Example 18 includes the subject matter of any of Examples 13-17, and wherein the integrated circuit component is a processor.

Example 19 includes the subject matter of any of Examples 13-18, and wherein, for individual vias of the one or more vias, the resistive layer comprises titanium and nitrogen.

Example 20 includes the subject matter of any of Examples 13-19, and wherein, for individual vias of the one or more vias, the resistive layer comprises tantalum and nitrogen.

Example 21 includes the subject matter of any of Examples 13-20, and wherein, for individual vias of the one or more vias, the resistive layer comprises ruthenium and oxygen.

Example 22 includes the subject matter of any of Examples 13-21, and wherein, for individual vias of the one or more vias, the resistive layer comprises aluminum and oxygen.

Example 23 includes the subject matter of any of Examples 13-22, and wherein the substrate comprises silicon and oxygen.

Example 24 includes the subject matter of any of Examples 13-23, and wherein the substrate comprises silicon.

Example 25 includes a device comprising a substrate comprising a first layer; a second layer; and means for connecting the first layer to the second layer, wherein the means for connecting the first layer to the second layer has a resistivity between 1 and 1,000 microohm-centimeters.

Example 26 includes the subject matter of Example 25, and wherein the means for connecting the first layer to the second layer has a height/diameter ratio of at least 8.

Example 27 includes the subject matter of any of Examples 25 and 26, and wherein the means for connecting the first layer to the second layer has a thickness between 20 and 100 nanometers.

Example 28 includes the subject matter of any of Examples 25-27, and further including a trace on the first layer, the trace connecting the means for connecting the first layer to the second layer.

Example 29 includes the subject matter of any of Examples 25-28, and further including a circuit board coupled to the means for connecting the first layer to the second layer on the first layer; and an integrated circuit component coupled to the means for connecting the first layer to the second layer on the second layer.

Example 30 includes the subject matter of any of Examples 25-29, and wherein the integrated circuit component is a processor.

Example 31 includes the subject matter of any of Examples 25-30, and wherein the means for connecting the first layer to the second layer comprises titanium and nitrogen.

Example 32 includes the subject matter of any of Examples 25-31, and wherein the means for connecting the first layer to the second layer comprises tantalum and nitrogen.

Example 33 includes the subject matter of any of Examples 25-32, and wherein the means for connecting the first layer to the second layer comprises ruthenium and oxygen.

Example 34 includes the subject matter of any of Examples 25-33, and wherein the means for connecting the first layer to the second layer comprises aluminum and oxygen.

Example 35 includes the subject matter of any of Examples 25-34, and wherein the substrate comprises silicon and oxygen.

Example 36 includes the subject matter of any of Examples 25-35, and wherein the substrate comprises silicon.

Example 37 includes a method comprising forming one or more vias in a substrate; and growing a thin film in the one or more vias in the substrate, wherein the thin film has a resistivity between 1 and 1,000 microohm-centimeters.

Example 38 includes the subject matter of Example 37, and wherein the substrate is glass, wherein growing the thin film in the one or more vias comprises growing the thin film in the one or more vias using atomic layer deposition at a temperature over 300° C.