Semiconductor device having gate structures to reduce the short channel effects

A semiconductor device comprises a semiconductor substrate on an insulating layer; and a second gate that is located on the insulating layer and is embedded at least partially in the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a void within the semiconductor substrate, with the insulating layer being exposed by the void; and forming a second gate, with the void being filled with at least one part of the second gate. It facilitates the reduction of the short channel effects, resistances of the source and drain regions, and parasitic capacitances.

BENEFIT CLAIMS

This application is a US National Stage of International Application No. PCT/CN2011/000336 filed Mar. 2, 2011, which claims the benefit of CN 201010223858.6, filed Jul. 1, 2010

FIELD OF THE INVENTION

The present invention relates to the field of semiconductor technology, and particularly, to a semiconductor device and a method for forming the same.

BACKGROUND OF THE INVENTION

With the continued scaling of the channel length of MOSFETs (Metal Oxide Field-effect Transistors), a series of effects, which are ignorable in a long-channel MOSFET, are becoming more and more significant and are even becoming a dominant factor in affecting performance These effects are collectively referred to as the short-channel effects. The short-channel effects tend to deteriorate the electrical performance of a device, for example, causing the problems of reducing the threshold voltage of a gate, increasing the power consumption, reducing the signal to noise ratio, etc.

In order to control the short-channel effects, more impurity elements (such as phosphorus, boron, etc.) have to be doped into a channel, but this tends to lead to the reduced carrier mobility in the channel of the device. Moreover, there is a problem that it is difficult to control the distribution abruptness of the impurities doped into the channel, which tends to cause severe short-channel effects. The traditional SiGe PMOS strained silicon technology also encounters bottleneck problems, making it difficult to provide stronger strain for the channel. Furthermore, in aspects of the thickness of a gate oxide dielectric, there is also a bottleneck problem that it is difficult for the speed of reducing the gate oxide thickness to keep pace with that of reducing the gate width, and the leakage current in the gate dielectric becomes larger and larger. In addition, the critical dimensions are decreasing continuously, causing the resistance of the source/drain regions to increase continuously and the power consumption of the device to become higher and higher.

Currently, the dominant thinking in the industry is to improve the traditional planar device technology, trying to reduce the thickness of the channel region and to eliminate the electrical neutral layer under the depletion layer in the channel so that the depletion layer in the channel can fill up the whole channel region, which is the so-called fully depleted (FD) device while the traditional planar devices belong to the partially depleted (PD) devices.

However, in order to fabricate the fully depleted device, an extremely thin thickness of the channel silicon layer is required. The traditional manufacturing process, particularly the traditional bulk silicon-based manufacturing process, has difficulties in fabricating a structure meeting such requirements, or the costs are high. Even for the newly developed SOI (Silicon-On-Insulator) process, it is still difficult to control the thickness of the channel silicon layer at a relatively thin level. Regarding how to realize the fully depleted device, the focus of R&D efforts is turning to a 3-dimensional device structure, i.e., to a fully depleted dual-gate or tri-gate technology.

The 3-dimensional device structure (also referred to as a vertical device in some documents) refers to a device structure in which the cross section of the source/drain region and that of the gate are not in the same plane, which substantially belongs to a FinFet (Fin Field-effect Transistor) structure.

After turning to the 3-dimensional device structure, the channel region is no longer contained in the bulk silicon or SOI, and rather, it becomes independent from these structures. Therefore, the fully depleted channel with extremely thin thickness can be fabricated by means of etching, etc.

FIG. 1shows a 3D semiconductor device which has been proposed, the semiconductor device comprising: a semiconductor substrate20that is located on an insulating layer10; source and drain regions30abutting first opposite sides22of the semiconductor substrate20; gates40that are located on second sides24of the semiconductor substrate20, which are adjacent to the first sides22(a gate dielectric layer and a work function metal layer sandwiched between the gates40and the semiconductor substrate20are not shown in the figure). In this case, in order to reduce the resistances of the source and drain regions, the edge of the source and drain regions30may be expanded, i.e., the width of the source or drain region30(along the xx′ direction) is larger than the thickness of the semiconductor substrate20. Therefore, with the increase of the width (d) of the source and drain regions30, the parasitic capacitances between the source or drain region30and the gate40, and between the source or drain region30and the semiconductor substrate20increase, thus increasing the resistance-capacitance delay or decreasing the alternative current performance of the device.

SUMMARY OF THE INVENTION

In order to solve the above mentioned problems, the present invention provides a semiconductor device and a method for forming the same, which facilitate the reduction of the short-channel effects, the resistances of the source and drain regions, and the parasitic capacitances.

The semiconductor device as provided by the present invention comprises:

a semiconductor substrate on an insulating layer;

source and drain regions abutting first opposite sides of the semiconductor substrate;

first gates, which are located on second opposite sides of the semiconductor substrate; and

a second gate, which is located on the insulating layer and is embedded at least partly in the semiconductor substrate;

wherein, the second gate comprises:

a floating gate on the semiconductor substrate, wherein a first dielectric layer is sandwiched between the floating gate and the semiconductor substrate;

a control gate on the floating gate, wherein a second dielectric layer is sandwiched between the control gate and the floating gate.

Optionally, a channel layer and a mask layer are formed between the top part of the first dielectric layer and the semiconductor substrate, and the channel layer is formed between the semiconductor substrate and the mask layer.

Optionally, the channel layer has a thickness of 5 nm to 40 nm in a direction perpendicular to the second sides.

Optionally, in a direction perpendicular to the insulating layer, the first gate or the floating gate covers at least the channel layer.

Optionally, the material of the floating gate and/or the control gate is one of TiN, TiAlN, TaN or TaAlN, or a combination thereof.

Optionally, the material of the first dielectric layer and/or the second dielectric layer is one of hafnium-based oxides.

Optionally, the first sides are perpendicular to the second sides.

Optionally, the semiconductor device further comprises a semiconductor assistant substrate, wherein the upper surface of the semiconductor assistant substrate is lower than the upper surface of the semiconductor substrate, the semiconductor assistant substrate abuts the first sides, and the source and drain regions are formed on the semiconductor assistant substrate.

Optionally, the semiconductor assistant substrate contains Si. For a PMOS device, the source and drain regions are Sii_xGex; and for an NMOS device, the source and drain regions are Si:C.

Optionally, in the Sii_xGex, X has a value ranging from 0.1 to 0.7.

Optionally, in the Si:C, the value of the atomic number percentage of C is in a range of 0.2% to 2%.

The method for forming the semiconductor device as provided by the present invention comprises:

forming a semiconductor base structure on an insulating layer;

forming source and drain regions abutting first opposite sides of the semiconductor base structure;

forming first gates, which are located on second opposite sides of the semiconductor base structure;

removing a part of material within the semiconductor base structure to form a void in the semiconductor base structure, with the insulating layer being exposed by the void; and

forming a second gate, with the void being filled with at least one part of the second gate;

wherein, the step of forming the second gate comprises:

forming a floating gate on the semiconductor base structure, wherein a first dielectric layer is sandwiched between the floating gate and the semiconductor base structure; and

forming a control gate on the floating gate, wherein a second dielectric layer is sandwiched between the control gate and the floating gate.

Optionally, the step of forming the semiconductor base structure comprises:

forming on the insulating layer a first semiconductor layer, a stopper layer, a patterned sacrifice layer, a patterned protection layer, and a first sidewall spacer surrounding the patterned sacrifice layer and the protection layer;

patterning the stopper layer and the first semiconductor layer with the first sidewall spacer as a mask;

defining areas for the source and drain regions and removing the first sidewall spacer, the protection layer, and the sacrifice layer, so as to expose the stopper layer;

forming a second sidewall spacer surrounding the protection layer and the sacrifice layer;

the source and drain regions abut first opposite sides of the patterned first semiconductor layer;

the first gates are located on second opposite sides of the patterned first semiconductor layer; and

the step of forming the void within the semiconductor base structure comprises:

removing the protection layer, the sacrifice layer and the first semiconductor layer with the first sidewall spacer and the second sidewall spacer as the mask, the material of the stopper layer being different from the materials of the protection layer,

the sacrifice layer, the first semiconductor layer, the first sidewall spacer and the second sidewall spacer.

Optionally, the first sides are perpendicular to the second sides.

Optionally, in the direction perpendicular to the second sides, the first sidewall spacer has a thickness of 5 nm to 40 nm.

Optionally, the step of forming the source and drain regions comprises:

after forming the semiconductor base structure, removing the stopper layer located in the areas for the source and drain regions and the first semiconductor layer of a partial thickness, so as to form a source/drain base layer; and

forming a second semiconductor layer on the source/drain base layer.

Optionally, the first semiconductor layer contains Si. For a PMOS device the second semiconductor layer is Si1-xGex; and for an NMOS device, the second semiconductor layer is Si:C.

Optionally, in the Si1-xGex, X has a value ranging from 0.1 to 0.7.

Optionally, in the Si:C, the value of the atomic number percentage of C is in a range of 0.2% to 2%.

Optionally, before forming the second semiconductor layer on the source/drain base layer, the method further comprises performing a first ion implantation in a direction towards the first sides, so as to form a diffusion region and a halo.

Optionally, the step of forming the first gates comprises:

forming a gate stack before defining the areas for the source and drain regions, with the gate stack covering at least the patterned first semiconductor layer in a direction perpendicular to the insulating layer.

Optionally, the material of the floating gate and/or the control gate is one of TiN, TiAIN, TaN or TaAIN, or a combination thereof.

Optionally, the material of the first dielectric layer and/or the second dielectric layer is one of hafnium-based oxides.

Compared with the prior art, by employing the technical solution as provided by the present invention, it has the following advantages.

By forming the second gate embedded at least partially in the semiconductor substrate, for a semiconductor substrate having a channel region of the same thickness as that in prior art, the distance between the first gates formed on second sides of the semiconductor substrate can be increased, which further increases the distance h′ between a first gate and the source/drain region, thus facilitating the reduction of parasitic capacitances. Furthermore, due to the introduction of the second gate, provided that the height of the semiconductor substrate is kept constant, the lateral area of the semiconductor substrate having a channel region of the same thickness as that in prior art is increased, and so is the cross sectional area of the source/drain region abutting the semiconductor substrate (because of the increase of the width d′ of the source/drain region), thus facilitating a further reduction of the resistances of the source and drain regions. Moreover, by introducing the second gate, a division region is formed between the source and drain regions, which facilitates the reduction of short-channel effects. Still further, since the second gate is embedded at least partially in the semiconductor substrate, the use of the channel layer close to the first gate is facilitated; and, for the second gate, the thickness range of the first dielectric layer and/or the second dielectric layer therein can be larger. In addition, by using the semiconductor device according to the present invention, the first gates can be used as a switch, and the second gate can be used to realize data storage functions.

By forming the sacrifice layer on the semiconductor layer which is on the insulating layer, with the first and second sidewall spacers surrounding the sacrifice layer, and then using the first and second sidewall spacers as a hard mask to form the semiconductor substrate in a self alignment manner, the number of the masks needed can be reduced and the process can be refined. Moreover, by having the first gates or the floating gate cover at least the channel layer in a direction perpendicular to the insulating layer, the effective area of the channel region can be increased and the carrier mobility in the channel region can be enhanced.

By forming the semiconductor assistant substrate and then forming source and drain regions on the semiconductor assistant substrate, the source and drain regions can be formed by an epitaxial process. In the case that the semiconductor assistant substrate contains Si, for a PMOS device, the material of the source and drain regions can be Si1-xGex, and for an NMOS device, the material of the source and drain regions can be Si:C, which facilitates the utilizing of the source and drain regions to adjust the stress in the channel, so as to increase the carrier mobility in the channel.

When using the epitaxial process to form the source and drain regions, a source/drain base layer (a crystal seed layer, which can be the residual first semiconductor layer of the partial thickness) needs to be formed before forming the source and drain regions. After the source/drain base layer has been formed, the first semiconductor layer on the first sides of the semiconductor substrate will be partially exposed, and thus, a first ion implantation can be performed along a direction towards the first sides, so as to form a doped region in the channel of the device (such as a diffusion region and a halo). This facilitates practical operations and a reduction of the distance between adjacent semiconductor substrates, thus reducing the area of the device and the manufacturing costs.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following disclosure provides various embodiments or examples for realizing the technical solutions provided by the present invention. Although parts and arrangements in the particular examples will be described hereinafter, they are merely taken as examples and not intended to limit the present invention.

In addition, in the present invention, reference numerals and/or letters can repeated in the different embodiments. Such repetitions are for the purpose of simplicity and clarity, and they do not indicate the relationships between various embodiments and/or arrangements discussed.

The present invention provides examples of various particular processes and/or materials; however, the alternative applications of other processes and/or other material, which one skilled in the art would appreciate, obviously do not depart from the protective scope claimed for the present invention. It needs to emphasize that the mutual relationships between various structures described in this document include necessary extensions made due to the needs of these processes or manufacturing procedures, for example, the term “perpendicular” means that the difference between the angle between two planes and 90° is within the scope permissible by the processes or manufacturing procedures. In addition, in this document, the term “connected to” means a direct contact between two structures, and the term “located on•••” means that other structures may be intervened between two structures.

As shown inFIG. 2, a semiconductor device according to the present invention comprises a semiconductor substrate120that is located on an insulating layer100; source and drain regions140abutting first opposite sides126of the semiconductor substrate120; first gates160located on second opposite sides128of the semiconductor substrate120; and a second gate located on the insulating layer100and embedded at least partially in the semiconductor substrate120. The second gate comprises a floating gate124on the semiconductor substrate120, wherein a first dielectric layer123is sandwiched between the floating gate124and the semiconductor substrate120; and a control gate130on the floating gate125, wherein a second dielectric layer125is sandwiched between the control gate130and the floating gate124.

By forming the second gate embedded at least partially in the semiconductor substrate120, for a semiconductor substrate120having a channel region of the same thickness as that in prior art, the distance between the first gates160formed on second sides128of the semiconductor substrate120can be increased, which further increases the distance between a first gate160and the source/drain region140, thus facilitating the reduction of parasitic capacitances. Furthermore, due to the introduction of the second gate, provided that the height of the semiconductor substrate120is kept constant, the lateral area of the semiconductor substrate120having a channel region of the same thickness as that in prior art is increased, and so is the cross sectional area of the source/drain region140abutting the semiconductor substrate120(because of the increased width of the source/drain region140), thus facilitating a further reduction of the resistances of the source and drain regions140. Moreover, by introducing the second gate, a division region is formed between the source and drain regions140, and it facilitates the reduction of short-channel effects. Still further, since the second gate is embedded at least partially in the semiconductor substrate120, the use of the channel layer close to the first gate160is facilitated; and, and for the second gate, the thickness range of the first dielectric layer123and/or the second dielectric layer125therein can be larger. In addition, by using the semiconductor device according to the present invention, the first gates160can be used as a switch, and the second gate can be used to realize data storage functions.

The semiconductor substrate120may be silicon formed on the insulating layer100, with doped regions (such as diffusion regions and halos) already formed in the semiconductor substrate120to provide a channel region for the device. In one embodiment of the semiconductor device, a channel layer and a mask layer are formed between the semiconductor substrate120and the top part of the first dielectric layer123, and the channel layer is formed between the semiconductor substrate120and the mask layer. The material of the channel layer may be silicon (in which a doped region has already been formed), and in a direction perpendicular to the second sides, the channel layer has a thickness of 5 nm to 40 nm. The material of the mask layer may be silicon nitride, or a stack of silicon oxide and silicon nitride. The first sides may be perpendicular to the second sides.

The semiconductor device may further comprise a semiconductor assistant substrate122abutting a first side126, and the source/drain region140may be formed on the semiconductor assistant substrate122. As an example, the material of the semiconductor assistant substrate122may also be silicon, and then the source/drain region140may be formed on the semiconductor assistant substrate122using an ion implantation process. In addition, the upper surface of the semiconductor assistant substrate122may be lower than the upper surface of the semiconductor substrate120. In this description, the upper surface refers to the side surface of the semiconductor assistant substrate122or the semiconductor substrate120parallel to the insulating layer100. Then, the source/drain region140may be formed on the semiconductor assistant substrate122using an epitaxial process. In the case that the semiconductor assistant substrate122contains Si, for a PMOS device, the material of the source/drain region140may be Si1-xGex(X has a value ranging from 0.1 to 0.7 and may be adjusted flexibly depending on the need of the process, such as 0.2, 0.3, 0.4, 0.5, or 0.6, and unless specified otherwise in this document, X may be the same values as described here, which will not described redundantly); and for an NMOS device, the material of the source/drain regions140may be Si:C (the atomic number percentage of C may be in a range of 0.2% to 2%, such as 0.5%, 1% or 1.5%, the content of C may be adjusted flexibly depending on the need of the process, and unless specified in this document, the atomic number percentage of C may be the same values as described here, which will not described redundantly). Thus, the source/drain region140may be utilized to further adjust the stress in the channel region, so as to increase the carrier mobility in the channel region.

The first gate160may be formed on the second side128through a stack of a gate dielectric layer162and a work function metal layer164. Each of the gate dielectric layer162, the first dielectric layer123, and the second dielectric layer125may be a hafnium-based oxide, such as one of HfO2, HfSiO, HfSiON, HfTaO, HfSiO, or HfZrO, or a combination thereof. The work function metal layer164may include one of TiN, TiAIN, TaN or TaAIN, or a combination thereof. The first gate160may be a metal gate, preferably a polycrystalline silicon gate for a better control of process. The material of the floating gate and/or the control gate may be one of TiN, TiAlN, TaN, or TaAlN, or a combination thereof, and preferably TiN for facilitating the process integration.

In a direction perpendicular to the insulating layer100, the first gate160or the floating gate124covers at least the channel layer, facilitating the increase of the effective area of the channel region and in turn enhancing the carrier mobility in the channel region.

The present invention also provides the method for forming the semiconductor device.

First, as shown inFIGS. 3 and 4, on an silicon-on-insulator (the silicon layer therein is the first semiconductor layer, the first semiconductor layer may also be other semiconductors, the silicon-on-insulator comprises an insulating layer202and a silicon layer204formed sequentially on a substrate200, the substrate200is preferably a silicon substrate), a stopper layer206(it can be silicon oxide), a sacrifice layer208(it can be an amorphous silicon), and a protection layer220(it can be silicon carbide) are sequentially formed, and as shown inFIGS. 5 and 6. Then, the protection layer220and the sacrifice layer208are patterned. The patterning operation may be performed using an etching process, and the etching operation stops on the stopper layer206. Next, as shown inFIGS. 7 and 8, a first sidewall spacer240is formed surrounding the patterned protection layer220and the patterned sacrifice layer208. The material of the first sidewall spacer240may be silicon nitride, and the first sidewall spacer240may be formed using an etching back process. In this case, the first sides may be perpendicular to the second sides.

The thickness of the silicon layer204may be 50 nm to 100 nm, for example, 60 nm, 70 nm, 80 nm or 90 nm. The thickness of the stopper layer206may be 5 nm to 20 nm, for example, 8 nm, 10 nm, 15 nm or 18 nm. The thickness of the sacrifice layer208may be 30 nm to 80 nm, for example, 40 nm, 50 nm, 60 nm or 70 nm. The thickness of the protection layer220may be 20 nm to 50 nm, for example, 25 nm, 30 nm, 35 nm or 40 nm. In a direction perpendicular to the second sides, the thickness of the first sidewall spacer240may be 5 nm to 40 nm, for example, 10 nm, 20 nm, 25 nm or 30 nm.

Then, as shown inFIGS. 9 and 10, the stopper layer206and the silicon layer204are patterned with the first sidewall spacer240as a mask, and the patterning may be performed using an etching process which stops on the insulating layer202. Next, as shown inFIGS. 11 and 12, areas for the source and drain regions are defined, and the first sidewall spacer240, the protection layer220, and the sacrifice layer208located in the areas are removed, so as to expose the stopper layer206(a hard mask222may be formed on the areas which are not the source or drain region, the hard mask222may be formed on the protection layer220in the above mentioned step, the hard mask may be removed in an appropriate step, for example, after exposing the stopper layer220in the source and drain regions). At the same time, the side surfaces (not shown in the figures) of the protection layer220and the sacrifice layer208adjacent to the source/drain region are exposed. Next, as shown inFIGS. 13 and 14, a second sidewall spacer242(which may be silicon nitride) is formed to surround the protection layer220, the sacrifice layer208, the patterned stopper layer206, and the patterned silicon layer204. By now, a semiconductor base structure has been formed. Next, after the source and drain regions and the first gate have been formed, the protection layer220, the sacrifice layer208, the stopper layer206, and the silicon layer204are removed with the first sidewall spacer240and the second sidewall spacer242as a mask (namely, the protection layer220, the sacrifice layer208, the stopper layer206, and the silicon layer204covered by the first sidewall spacer240or the second sidewall242spacer, are not removed), so as to expose the insulating layer202. Now, a void has been formed. Then, a second gate is formed, such that the void is filled with at least one part of the second gate. Thus, the semiconductor device is formed. By forming the semiconductor base structure in a self alignment manner (which will form the semiconductor substrate later), the number of masks needed can be reduced and the processing can be refined. The thickness of the second sidewall spacer242may be 7 nm to 20 nm, such as 10 nm, 15 nm, or 18 nm.

It needs to emphasize that the first gate (actually, it is a gate stack comprising the gate; the gate stack may comprise a stack of a gate dielectric layer, a work function metal layer, and a polycrystalline silicon layer; and the polycrystalline silicon layer may also be replaced with a stack of metal layers) may be formed after patterning the stopper layer and the silicon layer, and before exposing the stopper layer located in the areas for the source and drain regions.

Particularly, as shown inFIG. 15, after patterning the stopper layer206and the silicon layer204(as shown inFIGS. 9 and 10), a gate stack (in which the gate stack comprises a gate dielectric layer262, a work function metal layer264and a gate material layer260which are accumulated in succession, the gate dielectric layer262may select a hafnium-based oxide, such as one of Hf02, HfSiO, HfSiON, HfTaO, HfSiO or HfZrO, or a combination thereof; the work function metal layer264may comprise one of TiN, TiAIN, TaN or TaAIN, or a combination thereof; and the gate material layer260may be metal, preferably polycrystalline silicon) is formed on the insulating layer202. Subsequently, the gate stack is planarized to expose the protection layer220. Furthermore, an assistant mask layer is formed covering the gate stack and the protection layer220. The assistant mask layer may be a stack of dielectric layers of different materials, for example, if the material of the protection layer220and the first sidewall spacer240is silicon nitride, the assistant mask layer may be a silicon oxide layer (a first assistant mask layer282)-silicon nitride layer (a second assistant mask layer284)-silicon oxide layer (a third assistant mask layer286).

After the above steps, when seen from a top view, there is only a silicon oxide layer on the substrate based on which the above mentioned structures are formed. After that, it also needs to remove the assistant mask layer and the gate stack in the areas for the source and drain regions before the formation of the semiconductor base structure. The above mentioned method for forming the first gates is a result of manufacturing process integration by comprehensive considerations, and the following description is based thereon. It needs to point out that the first gates may also be formed by using other methods, and the first gates may also be formed after forming the source and drain regions. According to the teachings provided by the present invention, one skilled in the art will be able to form the first gates in a flexible way, which will not be described redundantly.

The thickness of the gate dielectric layer262may be 2 nm to 3 nm, for example, 2.5 nm. Further, an interfacial oxide layer may be formed before forming the gate dielectric layer262, and the thickness of the interfacial oxide layer may be 0.2 nm to 0.7 nm, for example, 0.5 nm, which is not shown in the figure. The thickness of the work function metal layer264may be 3 nm to 10 nm, for example, 5 nm or 8 nm. The thickness of the gate material layer260may be 50 nm to 100 nm, for example, 60 nm, 70 nm, 80 nm or 90 nm. The thickness of the first assistant mask layer282may be 2 nm to 5 nm, for example, 3 nm or 4 nm. The thickness of the second assistant mask layer284may be 10 nm to 20 nm, for example, 12 nm, 15 nm or 18 nm. The thickness of the third assistant mask layer286may be 10 nm to 20 nm, for example, 12 nm, 15 nm or 18 nm. The thickness of the source/drain base layer may be 5 nm to 20 nm, for example, 10 nm or 15 nm.

In practice, as shown inFIG. 16, after forming the semiconductor base structure, the stopper layer206and the silicon204of a partial thickness in the areas for the source and drain regions are removed (the first assistant mask286, i.e., a silicon oxide layer on the gate stack is also removed), so as to form a source/drain base layer (i.e., a semiconductor assistant substrate). The thickness of the source/drain base layer may be 5 nm to 20 nm, for example, 10 nm or 15 nm. Then, as shown inFIG. 17, a first ion implantation is performed along a direction (the direction denoted by the arrows in the figure) towards the first sides (the first sides are the exposed surface of the silicon layer after removing a partial thickness), so as to form a diffusion region and a halo in the silicon layer204. Compared with performing the first ion implantation along a direction towards the second sides as in the prior art, it is more easy to implement the operations provided by the invention in practice, and the distance between adjacent semiconductor base structures may be reduced, thus reducing the areas occupied by the device and the manufacturing costs. The processing particularities of the first ion implantation, such as the implant energy, the implant dose, the number of times of implantation, and the dopants, may all be adjusted flexibly depending on the design of the device, which will not be described redundantly. Next, as shown inFIGS. 18 and 19, after forming a second semiconductor layer244on the source/drain base layer by an epitaxial method (for a PMOS device, the material of the second semiconductor layer244is Si1-xGexand the doping dose may be 1×1019/cm3 to 1×1021/cm3; and for an NMOS device, the material of the second semiconductor layer244is Si:C and the doping dose may be 1×1019/cm3 to 1×1021/cm3), the source/drain region is formed. The source and drain regions can be used to further adjust the stress in the channel region, so as to increase the carrier mobility in the channel region. In addition, the source and drain regions may also be formed not by removing the silicon layer204of a partial thickness after removing the stopper layer206in the source and drain regions. Instead, they may be formed by conducting an ion implantation in the silicon layer204.

Next, a void is formed. Firstly, as shown inFIGS. 20 and 21, a first dielectric layer290(such as silicon oxide) is formed and planarized, and a second assistant mask layer284in the assistant mask layer is exposed. The second assistant mask layer284may be exposed by CMP (Chemical Mechanical Polishing). Subsequently, as shown inFIGS. 22 and 23, the assistant mask layer in which the residual second assistant mask layer284(a silicon nitride layer), the residual first assistant mask layer282(a silicon oxide layer), and the gate stack of a partial thickness are removed, so as to form first gates266. In the direction of the thickness of the silicon layer204, the first gates266covers at least the silicon layer204(for forming a channel) for increasing the effective area of the channel of the device and further for increasing the carrier mobility in the channel. After this step, the protection layer220of a residual thickness still remains. Next, as shown inFIGS. 24 and 25, a second dielectric layer292(such as silicon oxide for reducing the damage of the existing structure when removing the protection layer220to form the void) is formed. The second dielectric layer292exposes the protection layer220but covers the first sidewall240and the second sidewall242. The above operation may be performed by depositing the second dielectric layer292and then carrying out a CMP process on the second dielectric layer292. Then, as shown inFIGS. 26 and 27, by using the second dielectric layer292as a mask, the protection layer220, the sacrifice layer208, the stopper layer206, and the silicon layer204are removed to expose the insulting layer202, so as to form a void300. It needs to be pointed out that, it is due to the protection of the second dielectric layer292that the formation of the void300has a smaller impact on other structures, but the shape of the void300is determined by the existence of the first sidewall240and the second sidewall242. Therefore, to some extent, the first sidewall240and the second sidewall242also function as a mask. Since the void300is formed after having formed the source and drain regions, the counter forces on the source and drain regions imposed by the silicon layer204(the first semiconductor layer), the stopper layer206, and the sacrifice layer208which are originally filled in the void300disappear, the loss of the stress in the source and drain regions becomes smaller.

Next, as shown inFIG. 28, after forming the void300, a floating gate dielectric layer223(i.e., a first dielectric layer) is formed, A deposition process may be used to form the floating gate dielectric layer223, and the floating gate dielectric layer223covers the bottom wall (i.e., the insulating layer202is exposed by the void) and sidewalls (which comprise the first semiconductor layer204abutting the insulating layer202, the stopper layer206abutting the first semiconductor layer204, and the first sidewall240or the second sidewall242abutting the stopper layer206) of the void300, and the second dielectric layer292.

Subsequently, as shown inFIG. 29, a floating gate320is formed on the floating gate dielectric layer223by using an etching back process, so as to fill the cavity300.

The floating gate320may be formed of a metal material, such as one of TiN, TiAIN, TaN or TaAIN, or a combination thereof, and preferably TiN for facilitating the process integration. In the direction perpendicular to the insulating layer202, the floating gate covers at least the first semiconductor layer204, facilitating the increase of the effective area of the channel region and in turn increasing the carrier mobility in the channel region.

After that, as shown inFIG. 30, a control gate dielectric layer225(i.e., a second dielectric layer) and a control gate230are formed. The control gate dielectric layer225covers the floating gate dielectric layer223and the floating gate320, and the control gate230abuts the control gate dielectric layer225adjacent to the floating gate320and the floating gate dielectric layer223. A deposition process may be adopted to form the control gate dielectric layer225, and the control gate230may be etched to have any pattern according to the design requirements (then, it is necessary to use the hard mask232formed on the control gate230). Next, as shown inFIG. 31, by using the hard mask232, the second dielectric layer292, and the floating gate dielectric layer223and the control gate dielectric layer225which cover the second dielectric layer292, are removed, thus exposing the first gate266and the source and drain regions244. It needs to be pointed out that, although in the embodiment shown in the figures, the floating gate dielectric layer223abuts the control gate dielectric layer225, but in other embodiments, according to the processing needs, the floating gate dielectric layer223and the control gate dielectric layer225may not abut each other (not shown).

After that, as shown inFIG. 32, a protective sidewall spacer234is formed. The protective sidewall234surrounds the structure obtained after removing the second dielectric layer292, and the floating gate dielectric layer223and the control gate dielectric layer225which cover the second dielectric layer292. A metal layer is formed on the first gate266and the source and drain regions244and is subjected to a heat treatment operation, and then the unreacted part of the metal layer is removed, so as to form a metal silicide layer246(namely, a contact region for reducing the contact resistance when forming the subsequent metal interconnection) on the first gate266and the source and drain regions244.

In this case, the thickness of the floating gate dielectric layer223may be 2 nm to 15 nm, for example, 5 nm, 8 nm, 10 nm, or 12 nm. The thickness of the floating gate320may be 3 nm to 10 nm, for example, 5 nm or 8 nm. The thickness of the control gate dielectric layer225may be 2 nm to 15 nm, for example, 5 nm, 8 nm, 10 nm, or 12 nm. The thickness of the control gate230may be 3 nm to 10 nm, for example, 5 nm or 8 nm. The floating gate dielectric layer223and/or the control gate dielectric layer225may be a hafnium-based oxide, for example, one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO or HfZrO, or a combination thereof.

Moreover, the application scope of the present invention is not limited to processes, structures, manufacturing, substance composition, means, methods and steps of the particular embodiments described in the specification. According to the disclosure of the present invention, one skilled in the art would readily understand that for processes, structures, manufacturing, substance composition, means, methods or steps currently existing or to be developed in future, when they perform the substantially same functions as that of the respective embodiments described in the present invention or produce the substantially same effects, they can be applied according to the teachings of the present invention, without departing from the protective scope claimed for the present invention.