Digital television transmission and receiving apparatus and method using 1/4 rate coded robust data

Provided is a Vestigial Side Band Digital Television (DTV) transmitter/receiver based on Advanced Television System Committee A/53. The invention provides DTV transmitter/receiver having a dual stream structure through generation of robust data which has a transmission rate a fourth as fast as that of normal data, and a method thereof. The DTV transmitter includes: input means for receiving digital video data stream including normal and robust data; encoding means for performing ¼ rate coding on the digital video data stream so that one bit can be transmitted through two symbols; and transmitting means for modulating/transmitting output signals of the encoding means. This invention can reduce SNR and satisfy TOV of robust data by performing additional FEC on robust data, transmitting/receiving ¼ rate coded robust data, which are capable of transmitting one-bit data for two symbols, and improving decoding ability of an equalizer and a trellis decoder of a DTV receiver.

TECHNICAL FIELD

The present invention relates to a Vestigial Side Band (VSB) digital television (DTV) transmitter and receiver based on a DTV standard A/53 of the Advanced Television System Committee (ATSC), and a method thereof. More particularly, it relates to a DTV transmitter and receiver having a double stream structure by generation of robust data having a transmission rate of a fourth as fast as normal data, and a method thereof.

BACKGROUND ART

The standards of the Advanced Television System Committee (ATSC) suggest to use a signal obtained by modulating 12 independent data streams, which are trellis encoded and time-multiplexed, into 10.76 MHz-rate 8-level Vestigial Side Band (VSB) symbol streams to transmit High Definition Television (HDTV) broadcasting through a terrestrial broadcasting channel. The frequency band of the signal is transformed into a frequency band of 6 MHz which corresponds to a standard Very High Frequency (VHF) or Ultrahigh Frequency (UHF) terrestrial television channel. Signals of the corresponding channel are broadcasted at a data rate of 19.39 Mbps. Detailed technology on the ATSC DTV standards and A/53 are available at http://www.atsc.org/.

FIG. 1is a block diagram showing a conventional DTV transmitter. As shown, data inputted into a transmitter100are serial data streams formed of 188-byte Moving Picture Experts Group (MPEG) compatible data packets, each of which includes a synchronous byte and 187-byte payload data. The inputted data are randomized in a data randomizer101and each packet is encoded to include 20-byte parity information for forward error correction (FEC), FEC-Reed Solomon (RS) coding, ⅙ data field interleaving, and ⅔ trellis coding.

That is, according to the ATSC standards, the data randomizer101performs XOR on the payload data bytes and a pseudo random binary sequence (PRBS) having a maximum length of 16 bits, which is initialized at a starting field of a data field.

In the RS encoder103receiving the outputted randomized data, data having a total of 207 bytes are generated for each data segment by adding 20 RS parity bytes for FEC to the 187 bytes.

The randomization and FEC are not performed on synchronous bytes corresponding to a segment synchronous signal among the inputted packet data.

Subsequently, data packets included in consecutive segments of each field are interleaved in a data interleaver105, and the interleaved data packets are interleaved again and encoded in a trellis encoder107. The trellis encoder107generates a stream of a data symbol expressed in three bits by using two inputted bits. One bit of the inputted two bits is pre-coded and the other bit is 4-state trellis encoded into two bits. The three bits finally outputted are mapped to an 8-level symbol. The trellis encoder107includes 12 parallel trellis encoders and precoders to generate 12 interleaved/coded data sequences.

The 8-level symbol are combined in a multiplexer (MUX)109with segment and field synchronization bit sequences117from a synchronization unit (not shown) to form a transmission data frame. Subsequently, a pilot signal is added in a pilot adder111. Symbol streams go through VSB suppressed-carrier modulation in a VSB modulator113. An 8-VSB symbol stream of a baseband is finally converted into a radio frequency (RF) signal in an RF converter115and then transmitted.

FIG. 2is a block diagram describing a conventional DTV receiver200. As illustrated, a channel for the RF signal transmitted from the transmitter100is selected in a tuner201of the receiver200. Then, the RF signal goes through intermediate frequency (IF) filtering in an IF filter and detector203and a synchronous frequency is detected. A synchronous (sync) and timing recovery block215detects a synchronous signal and recovers a clock signal.

Subsequently, a National Television Systems Committee (NTSC) interference signal is removed from the signal through a comb filter in an NTSC filter205, and equalized and phase-tracked in an equalizer and phase tracker207.

An encoded data symbol removed of multi-path interference goes through trellis decoding in a trellis decoder209. The decoded data symbol is deinterleaved in a data deinterleaver211. Subsequently, the data symbol is RS decoded in an RS decoder213and derandomized in a data derandomizer217. This way, the MPEG compatible data packet transmitted from the transmitter100can be restored.

FIG. 3is a diagram illustrating a transmission data frame exchanged between the transmitter ofFIG. 1and the receiver ofFIG. 2. As illustrated in the drawing, a transmission data frame includes two data fields and each data field is formed of 313 data segments.

The first data segment of each data field is a synchronous signal, i.e., a data field synchronous signal, which includes a training data sequence used in the receiver200. The other 312 data segments include a 188-byte transport packet and 20-byte data for FEC, individually. Each data segment is formed of data included in a couple of transmission packets due to data interleaving. In other words, the data of each data segment correspond to several transmission packets.

Each data segment is formed of 832 symbols. The first four symbols are binary and they provide data segment synchronization. A data segment synchronous signal corresponds to a synchronous byte, which is the first byte among the 188 bytes of the MPEG compatible data packet. The other 828 symbols correspond to 187 bytes of the MPEG compatible data packet and 20 bytes for FEC. The 828 symbols are transmitted in the form of an 8-level signal, and each symbol is expressed in three bits. Therefore, 2,484 bits (=828 symbols×3 bits/symbol) are transmitted per data segment.

However, transmission signals of a conventional 8-VSB transceiver are distorted in indoor and mobile channel environments due to variable channel and multipath phenomena, and this degrades reception performance of the receiver.

In other words, transmitted data are affected by various channel distortion factors. The channel distortion factors include a multipath phenomenon, frequency offset, phase jitter and the like. To compensate for the signal distortion caused by the channel distortion factors, a training data sequence is transmitted every 24.2 ms, but a change in multipath characteristics and Doppler interference exist even in the time interval of 24.2 ms that the training data sequences are transmitted. Since an equalizer of the receiver does not have a convergence speed fast enough to compensate for the distortion of receiving signals, which occurs by the change in multipath characteristics and the Doppler interference, the receiver cannot perform equalization precisely.

For this reason, the broadcasting program reception performance of 8-VSB DTV broadcast is lower than that of an analog broadcast and reception is impossible in a mobile receiver. Even if reception is possible, there is a problem that a signal-to-noise ratio (SNR) satisfying Threshold of Visibility (TOV) increases.

To solve the problems, International publication Nos. WO 02/080559 and WO 02/100026, and U.S. Patent Publication No. US2002/019470 disclose technology for transmitting robust data to any one among 4-level symbols, e.g., {−7,−5,5,7} or {−7,−3,3,7}, the technology which will be referred to as P-2VSB.

Also, Korean Patent Application No. 2003-0000512 discloses a technology for transmitting robust data to any one of four-level symbols {−7,−1,3,5} or {−5,−3,1,7}, which will be referred as E-4VSB hereafter.

Also, Korean Patent Application No. 2004-0022688 discloses a technology for transmitting robust data to any one of 8-level symbol {−7,−5,−3,−1,1,3,5,7}, which will be referred to as E-8VSB hereafter.

According to the above method, however, the transmission rate of robust data is a half of that of normal data. That is, one symbol transmits one-bit data. Although the transmitted robust data show a better reception performance than normal data, it is still hard to secure data reception in a poor channel environment such as an environment where a user is walking or moving.

DISCLOSURE

Technical Problem

It is, therefore, an object of the present invention, which is developed to resolve the problems, to provide a Digital Television (DTV) transmitter and receiver that can improve decoding performance in an equalizer and a trellis decoder of a receiver and lower the Signal-to-Noise Ratio (SNR) satisfying Threshold of Visibility (TOV) of robust data by performing additional Forward Error Correction (FEC) on the robust data and transmitting one-bit data on two symbols, and a method thereof.

The other objects and advantages of the present invention can be easily recognized by those of ordinary skill in the art of the present invention from the drawing, detailed description, and claims of the present specification.

Technical Solution

In accordance with one aspect of the present invention, there is provided a digital television (DTV) transmitter, which includes: an input means for receiving a digital video data stream including normal data and robust data; an encoding means for performing ¼ rate coding on the digital video data stream so that one bit can be transmitted through two symbols of a first symbol R1 and a second symbol R2; and a transmitting means for modulating and transmitting an output signal of the encoding means.

The encoding means includes a plurality of multiplexers and generates the first symbol R1 and the second symbol R2 sequentially with respect to one-bit robust data by a control bit for multiplexers.

The encoding means performs ¼ rate coding based on a P-2VSB method and maps the first symbol R1 and the second symbol R2 to one symbol of {−7,−5,5,7}, individually.

Also, the encoding means performs ¼ rate coding based on an E-4VSB method and maps the first symbol R1 and the second symbol R2 to one symbol of {−7,−1,3,5}, individually.

Also, the encoding means performs ¼ rate coding based on an E-4VSB method and maps the first symbol R1 and the second symbol R2 to one symbol of {−5,−3,1,7}, individually.

Also, the encoding means performs ¼ rate coding based on an E-4VSB method and maps the first symbol R1 to one symbol of {−7,−1,3,5} and the second symbol R2 to one symbol of {−5,−3,1,7}.

Also, the encoding means performs ¼ rate coding based on an E-4VSB method and maps the first symbol R1 to one symbol of {−5,−3,1,7} and the second symbol R2 to one symbol of {−7,−1,3,5}.

Also, the encoding means performs ¼ rate coding based on a E-8VSB method and maps the first symbol R1 and the second symbol R2 to one symbol of {−7,−5,−3,−1,1,3,5,7}, individually.

The encoding means performs ¼ rate coding by using four registers. The encoding means includes: a robust encoder for coding the one-bit robust data into two-bit data according to the state of two registers D0and D1; and a trellis encoder for performing standard trellis coding on the two-bit data and outputting the symbols R1 and R2 having one level respectively among predetermined levels expressed in three bits Z2, Z1and Z0according to the state of two registers D2and D3.

Values of the registers D0and D1of the robust encoder can be changed when the robust encoder generates the first symbol R1, and the values can be maintained when the robust encoder generates the second symbol R2.

In accordance with another aspect of the present invention, there is provided a DTV receiver, which includes: a receiving means for receiving a transmission signal including normal data and robust data and converting the received transmission signal into a baseband signal; an equalizing means for determining a symbol level of the transmission signal; a trellis decoding means for performing trellis decoding on the symbol whose level has been determined; and

a decoding means for outputting a digital video data stream with respect to the trellis decoded signal, wherein the trellis decoding means performs ¼ rate decoding on the robust data so that one bit can be extracted with respect to two symbols of a first symbol R1 and a second symbol R2.

In accordance with another aspect of the present invention, there is provided a DTV transmitting method, which includes the steps of: a) receiving a digital video data stream including normal data and robust data; b) performing ¼ rate coding on the digital video data stream so that one bit is transmitted through two symbols of first and second symbols R1 and R2; and c) modulating and transmitting output signals of the coding step b).

In accordance with another aspect of the present invention, there is provided a DTV receiving method, which includes the steps of: a) receiving a transmission signal including normal data and robust data and converting the received transmission signal into a baseband signal; b) determining a symbol level of the transmission signal, which is called equalization; c) performing trellis decoding on the symbol whose level has been determined; and d) outputting a digital video data stream with respect to the trellis decoded signal, wherein ¼ rate decoding is performed on the robust data in the trellis decoding step c) in such a manner that one bit is extracted for two symbols of a first symbol R1 and a second symbol R2.

Advantageous Effects

As described above, the present invention can reduce a signal-to-noise ratio (SNR) satisfying a Threshold of Visibility (TOV) by performing additional Forward Error Correction (FEC) on robust data and transmitting and receiving ¼-rate-coded robust data to transit one-bit data on two symbols and thus improving decoding performance in an equalizer and a trellis decoder of a receiver.

BEST MODE FOR THE INVENTION

Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, which is set forth hereinafter. If it is considered that further description on the prior art may blur the points of the present invention, the description will not be provided. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4is a block diagram showing a Digital Television (DTV) transmitter in accordance with an embodiment of the present invention. As shown, the transmitter400includes: a first multiplexer401, a data randomizer403, a Reed Solomon (RS) encoder405, a robust interleaver/packet formatter407, a data interleaver409, a robust encoder411, a robust data processor413, a trellis encoder415, a second multiplexer417, and a pilot adder/modulator/Radio Frequency (RF) converter419.

The data randomizer403, the RS encoder405, the data interleaver409, the trellis encoder415, the second multiplexer417, and a pilot adder/modulator/RF converter419are the same as the conventional data randomizer101, the RS encoder103, the data interleaver105, the trellis encoder107, the multiplexer109, and a pilot adder111, the Vestigial Side Band (VSB) modulator113, and the RF converter115, which were described with reference toFIG. 1.

The first multiplexer401multiplexes a normal data packet421and a robust data packet423under the control of a robust data flag signal425.

A normal data packet421and a robust data packet423are serial data streams formed of 188-byte Moving Picture Experts Group (MPEG) compatible data packets and they have the same attributes, but the robust data packet includes an information packet and a null packet. A null packet includes arbitrary data, for example, “0,” having a null packet header.

The robust data flag signal425is generated in an external device (not shown) based on the ratio of robust data to normal data in a field, i.e., the Number of Robust Data Packets (NRP), and the coding rate of the robust data. The other compositional elements of the transmitter400including the first multiplexer401can check out whether data processed currently by using the robust data flag signal425are robust data.

In the equation 1, NRP denotes the number of robust segments occupied by robust data packets for each data field, that is, the Number of Robust data Packets in a frame. As described above, the NRP is a value including all the number of information packet and null packets and it has a range of 0 to 312. Also, U signifies a union of two sets, and s denotes a data segment number in a data field and s has a range of 0 to 311.

In accordance with another embodiment, the position of a robust data packet can be defined as an equation 2.
RPI=312/NRP
RPP=floor(RPI×r)  Eq. 2

In the equation 2, RPI stands for Robust Data Packet Interval and RPP denotes Robust Data Packet Position. Floor(*) is a decimal cutting operation, which means an operation cutting out a decimal number, for converting an arbitrary number * into an integer value, and a value r has a range of 0 to NRP.

The normal data packet421and the robust data packet423multiplexed in the first multiplexer401are randomized in the data randomizer403, and each packet is encoded to include a 20-byte parity information for Forward Error Correction (FEC) in the RS encoder405. In the RS encoder405, data having a total of 207 bytes, which are transmitted for each data segment, are generated by adding 20 RS parity bytes for FEC to the 187-byte data. A robust data flag does not go through the randomization and RS encoding. If a robust data packet is RS encoded and 20 RS parity bytes are added, a robust data flag is marked for the added RS parity bytes.

Subsequently, the normal and robust data packets which are included in consecutive segments of each data field and RS-coded are inputted to the robust interleaver/packet formatter407and only robust data including information packet are interleaved based on a robust data flag. The interleaved robust data are reconstructed into a 207-byte packet according to the robust data coding rate, and the reconstructed robust data packet is multiplexed with the normal data packet. The normal data packet has a predetermined delay to be multiplexed with the robust data packet.

FIG. 5is a block diagram depicting a robust interleaver and a packet formatter ofFIG. 4. As illustrated, the robust interleaver/packet formatter407includes a robust data interleaver501, a packet formatter503, and a third multiplexer505.

The robust data interleaver501interleaves only a robust data packet based on a robust data flag signal.FIG. 6is a diagram describing a robust data interleaver ofFIG. 5. As shown, the robust data interleaver501receives signals on a byte basis with respect to a robust data packet only among data packets inputted from the RS encoder405, performs interleaving to transmit the robust data to the packet formatter503. Also, the robust data interleaver501has parameters M=3, B=69 and N=207, and forms the interleaved packet out of data from 69 different packets at maximum. Among the robust data packets, a null packet is abandoned and the interleaving is performed only on the information packets.

The packet formatter503shown inFIG. 5processes the robust data interleaved in the robust data interleaver501. The packet formatter503receives 184 bytes from the robust data interleaver501and generates four 207-byte data blocks with respect to the 184-byte robust data. Herein, four bits of each byte of the generated 207-byte data block, for example, LSB(6,4,2,0), corresponds to the inputted robust data. The other four bits, for example, MSB (7,5,3,1), are set up with arbitrary values. Meanwhile, in each of the generated 207-byte data blocks, the byte positions that do not correspond to the 184-byte robust data are filled with header-byte data or arbitrary information data to be used for RS parity bytes, which will be described later on.

Subsequently, the packet formatter503adds a header corresponding to a null packet to the first three bytes of each 207-byte data block. Then, the packet formatter503generates a 207-byte packet by adding 20 bytes, each of which is formed of arbitrary information, for example, “0,” to each data block. The 20-byte arbitrary information is replaced with RS parity information in the robust data processor413, which will be described later.

All the other vacant byte positions can be filled with bytes of the 184-byte robust data sequentially. The packet formatter503checks out whether a position corresponds to a parity byte position, before it adds robust data bytes to each newly generated 207-byte data block. If the position does not correspond to a parity byte, a robust data byte is placed in the position. If the position corresponds to a parity byte, the byte position is skipped and the next byte position is checked. The process is repeated until all the robust data bytes are placed in the newly generated 207-byte data block.

Therefore, if robust-interleaved two robust data packets (2×207 bytes) are inputted into the packet formatter503, the packet formatter503outputs 9 packets (9×207 bytes), each of which is formed of robust data bytes, header bytes, and arbitrary information bytes for RS parity bytes. The outputted 9 packets include 46-bytes of the robust data inputted to the packet formatter503, individually.

Meanwhile, the positions of arbitrary data bytes for RS parity bytes with respect to each packet are determined based on an equation 3.
m=(52×n+(smod 52))mod 207  Eq. 3

Herein, m denotes an output byte number, i.e., a parity byte position of a packet extended into 207 bytes; n denotes an input byte, i.e., a byte number in each packet, and it ranges from 0 to 206; s denotes a segment corresponding to robust data in a data field, i.e., a packet number, and it ranges from 0 to 311. The parity byte positions, i.e., the value m, can be calculated in the range of 187 to 206 only with respect to the value n so that the positions of 20 parity packets for each packet should correspond to the last 20 bytes of the packet. In short, the value n corresponds to the last 20 bytes of a packet.

A third multiplexer505ofFIG. 5multiplexes a robust data packet and a normal data packet, which are outputted from the packet formatter503, based on a robust data flag. The operation of the third multiplexer505is the same as that of the first multiplexer401.

Referring toFIG. 4again, the data interleaver409interleaves data packets within consecutive segments of each data field on a byte basis to scramble the sequential order of a robust data flag and normal/robust data stream based on the ATSC A/53 standards and outputs scrambled data. The data interleaver409has a similar structure to the robust data interleaver501(seeFIG. 6, M=4, B=52 and N=208).

FIG. 7is a diagram illustrating a robust encoder ofFIG. 4in detail. As shown, the robust encoder411specifically includes a plurality of identical robust encoding units411ato411lin parallel. The robust encoder411performs trellis interleaving on the interleaved normal/robust data and the interleaved robust data flag and performs coding on the trellis-interleaved normal/robust data based on the trellis-interleaved robust data flag. The normal/robust data outputted from the data interleaver409are inputted into the 12 robust encoding units411ato411lsequentially on a byte basis, and two-bit normal/robust data expressed as X1′ and X2′ are coded into two-bit normal/robust data symbols expressed as X1and X2. For example, an input bit X2′ is a code word of MSB(7,5,3,1) and an input bit X1′ is a code word of LSB(6,4,2,0). As described above, although the MSB(7,5,3,1) and the LSB(6,4,2,0) of normal data all include information data, the LSB(6,4,2,0) of robust data includes information data and the MSB(7,5,3,1) of robust data includes arbitrary values.

The normal data symbols among data symbols coded in the robust encoding unit411is inputted to the trellis encoder415by bypassing the robust data processor413, and robust data symbols are inputted to the trellis encoder415through the robust data processor413. In this process, the data symbols coded in the 12 robust encoding units411ato411lare inputted into the trellis encoder415or the robust data processor413sequentially to thereby performing the trellis interleaving entirely.

Referring toFIG. 4, the trellis encoder415is the same as the trellis encoder defined in the current ATSC A/53 Standards. Although not illustrated in the drawing, the trellis encoder415, too, is formed of a plurality of identical trellis encoding units, for example, 12 identical trellis encoding units connected in parallel, just as the robust encoder411. The normal data symbols X1and X2inputted into the trellis encoder415after bypassing the robust data processor413or the robust data symbols X1and X2inputted into the trellis encoder415through the robust data processor413are inputted into the 12 trellis encoding units, and the trellis encoder415performs trellis encoding on the inputted symbols X1and X2into 8-level symbols. The 8-level symbols obtained by being encoded in the 12 trellis encoding units are inputted into the second multiplexer417sequentially. This way, the trellis encoding is carried out entirely.

FIG. 8is a diagram describing a robust encoder and a trellis encoder ofFIG. 4. Since the robust data processor413to be described later processes only robust data,FIG. 8exemplifies conceptual connection between a robust encoding unit #0411aand a trellis encoding unit #0415a.

As defined in the current ATSC A/53 Standards, the trellis encoder415includes a pre-coding block, a trellis encoding block, and a symbol mapping block. The pre-coding block and the trellis encoding block include one and two registers (D) for storing symbol delay values, for example, 12 symbol delay values, respectively.

The robust encoding unit #0411acodes two-bit normal/robust data X1′ and X2′ inputted from the data interleaver409into two-bit normal/robust data symbols X1and X2, and the trellis encoding unit #0415aoutputs 8-level signals to the second multiplexer417based on symbols Z0, Z1and Z2obtained by performing trellis encoding on the two-bit normal/robust data symbols X1and X2.

A method for coding robust data by using the robust encoder411and the trellis encoder415is already suggested by the Phillips Company and the Electronics and Telecommunications Research Institute (ETRI).

FIG. 9is a block diagram describing P-2VSB coding of robust data which is suggested by the Philips Company.

As described above, a robust encoder911outputs the trellis-encoded symbols Z0, Z1and Z2in four levels of {−7,−5,5,7} by equalizing the coded values Z2and Z1of a trellis encoder915obtained through a precoder remover based on the value X1′ between the inputted signals X1′ and X2′.

FIGS. 10 and 11are block diagrams showing robust data trellis coding in E-4VSB method which is suggested by the ETRI. A robust encoder1011ofFIG. 10estimates a coded value Z0of a trellis encoder1015and makes the coded values Z2and Z1of the trellis encoder1015have the same value based on the value of an input signal X1′, when the value Z0is 0.

Also, the robust encoder1011codes robust data in such a manner that the coded values Z2and Z1of the standard trellis encoder have values inverse to each other, when the coded value Z0of the trellis encoder1015is 1 and, thus, the level of symbols outputted from the trellis encoder1015is {−7,−1,3,5}.

A robust encoder1111ofFIG. 11estimates a coded value Z0of a trellis encoder1115and makes the coded values Z2and Z1of the trellis encoder1115have values inverse to each other based on the value of an input signal X1′, when the value Z0is 0.

Also, the robust encoder1111codes robust data in such a manner that the coded values Z2and Z1of the standard trellis encoder have the same value, when the coded value Z0of the trellis encoder1115is 1 and, thus, the level of symbols outputted from the trellis encoder1115is {−5,−3,1,7}.

FIGS. 12 and 13are block diagrams illustrating robust data E-8VSB coding which is suggested by the ETRI.

As shown inFIGS. 12 and 13, an input signal X1′ is coded by adding registers for generating robust data to robust encoders1211and1311.

The robust data are coded to have a total of 16 states including the robust encoders1211and1311and the trellis encoders1215and1315so that the level of output symbol value of the trellis encoder1115should become the same as the standard 8-VSB, i.e., {−7,−5,−3,−1,1,3,5,7}.

The aforementioned P-2VSB, E-4VSB and E-8VSB robust data generation methods transmit one-bit data through one symbol at a data transmission rate a half as fast as normal data. The present invention improves the performance of the receiver by performing additional Forward Error Correction (FEC) on the robust data and transmitting/receiving ¼-rate coded robust data so that one-bit data can be transmitted through two symbols.

FIG. 14is a block diagram describing ¼ rate coding applied to the P-2VSB of the Phillips Company in accordance with an embodiment of the present invention.

As illustrated in the drawing, registers D0and D1for generating robust data are added to a robust encoder1411and input data X1′ are coded by using four registers D0, D1, D2and D3. When the multiplexer selects an R1 input based on a control bit R1/R2 with respect to the one-bit input data X1′, one symbol is outputted from a trellis encoder1415. When the multiplexer selects an R2 input, another symbol is outputted from the trellis encoder1415. When the first symbol R1 is generated, the values of the registers D0and D1can be changed. However, when the second symbol R2 is generated, the values are maintained. The output signal and subsequent state of the trellis encoder1415based on the input data X1′ are as shown in Tables 1 and 2, respectively.

Table 1 shows two output symbols according to input of robust data. The R1 indicates the first symbol and the R2 indicates the second symbol. Table 2 shows the state after the generation of two symbols upon the input of robust data. The 16 states S of Table 1 and 2 including the current state and the subsequent state are calculated based on an equation 4. The definitions of R1 and R2 and subsequent state are the same in the other embodiments.
S=D0×8+D1×4+D2×2+D3  Eq. 4

Meanwhile, the state values of the registers D0and D1additionally used to generate robust data are not changed when normal data are inputted. The output signals based on input and the subsequent state are as shown in Tables 3 and 4, respectively.

When ¼ rate robust data which are 16-state trellis coded are generated in the present embodiment, a trellis decoder and a signal level determiner can be designed based on the Tables 1 and 2 to thereby improve the performance of the receiver.

FIG. 15is a block diagram describing ¼ rate coding applied to the P-2VSB of the Phillips Company in accordance with another embodiment of the present invention. It shows a structure ofFIG. 14with switched D0and D1.

As illustrated in the drawing, registers D0and D1for generating robust data are added to a robust encoder1511, and input data X1′ are coded by using four registers D0, D1, D2and D3. When the multiplexer selects an R1 input based on a control bit R1/R2 with respect to the one-bit input data X1′ based on a control bit R1/R2, one symbol is outputted from a trellis encoder1515and, when the multiplexer selects an R2 input, another symbol is outputted from the trellis encoder1515. When the first symbol R1 is generated, the values of the registers D0and D1can be changed. However, when the second symbol R2 is generated, the values are maintained. The output signals and subsequent state of the trellis encoder1515based on the input data X1′ are as shown in Tables 5 and 6, respectively.

Meanwhile, the state values of the registers D0and D1additionally used to generate robust data are not changed when normal data are inputted. The output signals based on input and the subsequent state are as shown in Tables 3 and 4, respectively.

When ¼ rate robust data which are 16-state trellis coded are generated in the present embodiment, a trellis decoder and a signal level determiner can be designed based on the Tables 5 and 6 to thereby improve the performance of the receiver.

FIG. 16is a block diagram describing ¼ rate coding applied to the P-2VSB of the Phillips Company in accordance with yet another embodiment of the present invention.

As illustrated in the drawing, registers D0and D1for generating robust data are added to a robust encoder1611, and input data X1′ are coded by using four registers D0, D1, D2and D3. When the multiplexer selects an R1 input with respect to one-bit input data X1′ based on a control bit R1/R2, one symbol is outputted from a trellis encoder1615and, when the multiplexer selects an R2 input, another symbol is outputted from the trellis encoder1615. When the first symbol R1 is generated, the values of the registers D0and D1can be changed. However, when the second symbol R2 is generated, the values are maintained. The output signals and subsequent state of the trellis encoder1615based on the input data X1′ are as shown in Tables 7 and 8, respectively.

Meanwhile, the state values of the registers D0and D1additionally used to generate robust data are not changed when normal data are inputted. The output signals based on input and the subsequent state are as shown in Tables 3 and 4, respectively.

When ¼ rate robust data which are 16-state trellis coded are generated in the present embodiment, a trellis decoder and a signal level determiner can be designed based on the Tables 7 and 8 to thereby improve the performance of the receiver.

FIG. 16also has a case where the positions of the registers D0and D1switched with each other, just as the cases ofFIGS. 14 and 15. When the positions of the registers D0and D1are switched inFIG. 16, the characteristics can be described based on the following Tables 9 and 10, respectively.

FIG. 17is a block diagram describing ¼ rate coding applied to the E-4VSB of the ETRI having an output signal of {−7,−1,3,5} in accordance with an embodiment of the present invention.

As illustrated in the drawing, registers D0and D1for generating robust data are added to a robust encoder1711, and input data X1′ are coded by using four registers D0, D1, D2and D3. When the multiplexer selects an R1 input with respect to the one-bit input data X1′ based on a control bit R1/R2, one symbol is outputted from a trellis encoder1715and, when the multiplexer selects an R2 input, another symbol is outputted from the trellis encoder1715. When the first symbol R1 is generated, the values of the registers D0and D1can be changed. However, when the second symbol R2 is generated, the values are maintained. The output signals and subsequent state of the trellis encoder1715based on the input data X1′ are as shown in Tables 11 and 12, respectively.

Meanwhile, the state values of the registers D0and D1additionally used to generate robust data are not changed when normal data are inputted. The output signals based on input and the subsequent state are as shown in Tables 3 and 4, respectively.

When ¼ rate robust data which are 16-state trellis coded are generated in the present embodiment, a trellis decoder and a signal level determiner can be designed based on the Tables 11 and 12 to thereby improve the performance of the receiver.

The structure ofFIG. 17also has a case where the positions of the registers D0and D1are switched with each other, just as the structures ofFIGS. 14 and 15. When the positions of the registers D0and D1are switched inFIG. 17, the characteristics can be described based on the following Tables 13 and 14.

FIG. 18is a block diagram describing ¼ rate coding applied to the E-4VSB of the ETRI having an output signal of {−5,−3,1,7} in accordance with an embodiment of the present invention.

As illustrated in the drawing, registers D0and D1for generating robust data are added to a robust encoder1811, and input data X1′ are coded by using four registers D0, D1, D2and D3. When the multiplexer selects an R1 input with respect to the one-bit input data X1′ based on a control bit R1/R2, one symbol is outputted from a trellis encoder1815and, when the multiplexer selects an R2 input, another symbol is outputted from the trellis encoder1815. When the first symbol R1 is generated, the values of the registers D0and D1can be changed. However, when the second symbol R2 is generated, the values are maintained. The output signals and subsequent state of the trellis encoder1815based on the input data X1′ are as shown in Tables 15 and 16, respectively.

Meanwhile, the state values of the registers D0and D1additionally used to generate robust data are not changed when normal data are inputted. The output signals based on input and the subsequent state are as shown in Tables 3 and 4, respectively.

When ¼ rate robust data which are 16-state trellis coded are generated in the present embodiment, a trellis decoder and a signal level determiner can be designed based on the Tables 15 and 16 to thereby improve the performance of the receiver.

The structure ofFIG. 18also has a case where the positions of the registers D0and D1are switched with each other, just as the structures ofFIGS. 14 and 15. When the positions of the registers D0and D1are switched inFIG. 18, the characteristics can be described based on the following Tables 17 and 18.

FIG. 19is a block diagram describing ¼ rate coding applied to the E-4VSB of the ETRI having an output signal of {−7,−1,3,5} and {−5,−3,1,7} optionally in accordance with an embodiment of the present invention.

As illustrated in the drawing, registers D0and D1for generating robust data are added to a robust encoder1911, and input data X1′ are coded by using four registers D0, D1, D2and D3. When the multiplexer selects an R1 input with respect to the one-bit input data X1′ based on a control bit R1/R2, one symbol is outputted from a trellis encoder1915and, when the multiplexer selects an R2 input, another symbol is outputted from the trellis encoder1915. When the first symbol R1 is generated, the values of the registers D0and D1can be changed. However, when the second symbol R2 is generated, the values are maintained. When the first symbol R1 is coded to be mapped to one of {−7,−1,3,5} and the second symbol is coded to be mapped to one of {−5,−3,1,7}, the output signals and subsequent state of the trellis encoder1915based on the input data X1′ are as shown in Tables 19 and 20, respectively.

Conversely, when the first symbol R1 is coded to be mapped to one of {−5,−3,1,7} and the second symbol is coded to be mapped to one of {−7,−1,3,5}, the output signals and subsequent state of the trellis encoder1915based on the input data X1′ are as shown in Tables 21 and 22, respectively.

Meanwhile, the state values of the registers D0and D1additionally used to generate robust data are not changed when normal data are inputted. The output signals based on input and the subsequent state are as shown in Tables 3 and 4, respectively.

When ¼ rate robust data which are 16-state trellis coded are generated in the present embodiment, a trellis decoder and a signal level determiner can be designed based on the Tables 19, 20, 21 and 22 to thereby improve the performance of the receiver.

The structure ofFIG. 19also has a case where the positions of the registers D0and D1are switched with each other, just as the structures ofFIGS. 14 and 15. When the positions of the registers D0and D1are switched inFIG. 19, the characteristics can be described based on the following Tables 23, 24, 25 and 26. Tables 23 and 24 show a case where the first symbol R1 is coded to be mapped to one of {−7,−1,3,5} and the second symbol R2 is coded to be mapped to one of {−5,−3,1,7}, respectively. Tables 25 and 26 show a case where the first symbol R1 is coded to be mapped to one of {−5,−3,1,7} and the second symbol R2 is coded to be mapped to one of {−7,−1,3,5}, respectively.

FIG. 20is a block diagram describing ¼ rate coding applied to the E-4VSB of the ETRI having an output signal of {−7,−1,3,5} in accordance with another embodiment of the present invention.

As illustrated in the drawing, registers D0and D1for generating robust data are added to a robust encoder2011and input data X1′ are coded by using four registers D0, D1, D2and D3. When the multiplexer selects an R1 input with respect to the one-bit input data X1′ based on a control bit R1/R2, one symbol is outputted from a trellis encoder2015and, when the multiplexer selects an R2 input, another symbol is outputted from the trellis encoder2015. When the first symbol R1 is generated, the values of the registers D0and D1can be changed. However, when the second symbol R2 is generated, the values are maintained. The output signals and subsequent state of the trellis encoder2015based on the input data X1′ are as shown in Tables 27 and 28, respectively.

Meanwhile, the state values of the registers D0and D1additionally used to generate robust data are not changed when normal data are inputted. The output signals based on input and the subsequent state are as shown in Tables 3 and 4, respectively.

When ¼ rate robust data which are 16-state trellis coded are generated in the present embodiment, a trellis decoder and a signal level determiner can be designed based on the Tables 11 and 12 to thereby improve the performance of the receiver.

The structure ofFIG. 20also has a case where the positions of the registers D0and D1are switched with each other, just as the structures ofFIGS. 14 and 15. When the positions of the registers D0and D1are switched inFIG. 20, the characteristics can be described based on the following Tables 29 and 30.

FIG. 21is a block diagram describing ¼ rate coding applied to the E-4VSB of the ETRI having an output signal of {−5,−3,1,7} in accordance with another embodiment of the present invention.

As illustrated in the drawing, registers D0and D1for generating robust data are added to a robust encoder2111, and input data X1′ are coded by using four registers D0, D1, D2and D3. When the multiplexer selects an R1 input with respect to the one-bit input data X1′ based on a control bit R1/R2, one symbol is outputted from a trellis encoder2115and, when the multiplexer selects an R2 input, another symbol is outputted from the trellis encoder2115. When the first symbol R1 is generated, the values of the registers D0and D1can be changed. However, when the second symbol R2 is generated, the values are maintained. The output signals and subsequent state of the trellis encoder2115based on the input data X1′ are as shown in Tables 31 and 32, respectively.

Meanwhile, the state values of the registers D0and D1additionally used to generate robust data are not changed when normal data are inputted. The output signals based on input and the subsequent state are as shown in Tables 3 and 4, respectively.

When ¼ rate robust data which are 16-state trellis coded are generated in the present embodiment, a trellis decoder and a signal level determiner can be designed based on the Tables 31 and 32 to thereby improve the performance of the receiver.

The structure ofFIG. 21also has a case where the positions of the registers D0and D1are switched with each other, just as the structures ofFIGS. 14 and 15. When the positions of the registers D0and D1are switched inFIG. 17, the characteristics can be described based on the following Tables 33 and 34.

FIG. 22is a block diagram describing ¼ rate coding applied to the E-4VSB of the ETRI having an output signal of {−7,−1,3,5} and {−5,−3,1,7} optionally in accordance with another embodiment of the present invention.

As illustrated in the drawing, registers D0and D1for generating robust data are added to a robust encoder2211, and input data X1′ are coded by using four registers D0, D1, D2and D3. When the multiplexer selects an R1 input with respect to the one-bit input data X1′ based on a control bit R1/R2, one symbol is outputted from a trellis encoder2215and, when the multiplexer selects an R2 input, another symbol is outputted from the trellis encoder2215. When the first symbol R1 is generated, the values of the registers D0and D1can be changed. However, when the second symbol R2 is generated, the values are maintained. When the first symbol R1 is coded to be mapped to one of {−7,−1,3,5} and the second symbol R2 is coded to be mapped to one of {−5,−3,1,7}, the output signals and subsequent state of the trellis encoder2215based on the input data X1′ are as shown in Tables 35 and 36, respectively.

Conversely, when the first symbol R1 is coded to be mapped to one of {−5,−3,1,7} and the second symbol is coded to be mapped to one of {−7,−1,3,5}, the output signals and subsequent state of the trellis encoder2215based on the input data X1′ are as shown in Tables 37 and 38, respectively.

Meanwhile, the state values of the registers D0and D1additionally used to generate robust data are not changed when normal data are inputted. The output signals based on input and the subsequent state are as shown in Tables 3 and 4, respectively.

When ¼ rate robust data which are 16-state trellis coded are generated in the present embodiment, a trellis decoder and a signal level determiner can be designed based on the Tables 35, 36, 37 and 38 to thereby improve the performance of the receiver.

The structure ofFIG. 22also has a case where the positions of the registers D0and D1are switched with each other, just as the structures ofFIGS. 14 and 15. When the positions of the registers D0and D1are switched inFIG. 22, the characteristics can be described based on the following Tables 39, 40, 41 and 42.

Tables 39 and 40 show a case where the first symbol R1 is coded to be mapped to one of {−7,−1,3,5} and the second symbol R2 is coded to be mapped to one of {−5,−3,1,7}, respectively. Tables 41 and 42 show a case where the first symbol R1 is coded to be mapped to one of {−5,−3,1,7} and the second symbol R2 is coded to be mapped to one of {−7,−1,3,5}, respectively.

FIG. 23is a block diagram describing ¼ rate coding applied to the E-8VSB of the ETRI in accordance with an embodiment of the present invention.

As illustrated, input data X1′ are coded by using four registers D0, D1, D2and D3of a robust encoder2311. When the multiplexer selects an R1 input with respect to the one-bit input data X1′ based on a control bit R1/R2, one symbol is outputted from a trellis encoder2315and, when the multiplexer selects an R2 input, another symbol is outputted from the trellis encoder2315. When the first symbol R1 is generated, the values of the registers D0and D1can be changed. However, when the second symbol R2 is generated, the values are maintained. The data X1and X2generated from the input data X1′ are used as input data for the trellis encoder2315for generating the first symbol R1, and they are used as input data for the trellis encoder2315for generating the next second symbol R2 after being stored in a memory. The output signals and subsequent state of the trellis encoder2315based on the input data X1′ are as shown in Tables 43 and 44, respectively.

Meanwhile, the state values of the registers D0and D1additionally used to generate robust data are not changed when normal data are inputted. The output signals based on input and the subsequent state are as shown in Tables 3 and 4, respectively.

When ¼ rate robust data which are 16-state trellis coded are generated in the present embodiment, a trellis decoder and a signal level determiner can be designed based on the Tables 43 and 44 to thereby improve the performance of the receiver.

The structure ofFIG. 23also has a case where the positions of the registers D0and D1are switched with each other, just as the structures ofFIGS. 14 and 15. When the positions of the registers D0and D1are switched inFIG. 23, the characteristics can be described based on the following Tables 45 and 46.

FIG. 24is a block diagram describing ¼ rate coding applied to the E-8VSB of the ETRI in accordance with another embodiment of the present invention.

As illustrated, input data X1′ are coded by using four registers D0, D1, D2and D3of a robust encoder2411. When the multiplexer selects an R1 input with respect to one-bit input data X1′ based on a control bit R1/R2, one symbol is outputted from a trellis encoder2415and, when the multiplexer selects an R2 input, another symbol is outputted from the trellis encoder2415. When the first symbol R1 is generated, the values of the registers D0and D1can be changed. However, when the second symbol R2 is generated, the values are maintained. The data X1and X2generated from the input data X1′ are used as input data for the trellis encoder2415for generating the first symbol R1, and they are used as input data for the trellis encoder2415for generating the next second symbol R2 after being stored in a memory. The output signals and subsequent state of the trellis encoder2415based on the input data X1′ are as shown in Tables 47 and 48, respectively.

Meanwhile, the state values of the registers D0and D1additionally used to generate robust data are not changed when normal data are inputted. The output signals based on input and the subsequent state are as shown in Tables 3 and 4, respectively.

When ¼ rate robust data which are 16-state trellis coded are generated in the present embodiment, a trellis decoder and a signal level determiner can be designed based on the Tables 47 and 48 to thereby improve the performance of the receiver.

The structure ofFIG. 24also has a case where the positions of the registers D0and D1are switched with each other, just as the structures ofFIGS. 14 and 15. When the positions of the registers D0and D1are switched inFIG. 24, the characteristics can be described based on the following Tables 49 and 50.

FIG. 25is a block diagram describing a robust data processor ofFIG. 4. As illustrated, the robust data processor413includes a trellis deinterleaver2501, a data deinterleaver2503, an RS encoder2505, and a data interleaver2507. The robust data X1and X2and a robust data flag which are outputted from the robust encoder411go through trellis deinterleaving and data deinterleaving in the trellis deinterleaver2501and the data deinterleaver2503and reassembled in the form of a packet.

As described above, 20-byte arbitrary information is added to the 207-byte data block generated in the packet formatter503, and the RS encoder2505replaces the 20-byte arbitrary information with RS parity information. The robust data packet with the RS parity information therein is interleaved in the data interleaver2507and outputted to the trellis encoder415on a byte basis.

Referring toFIG. 4again, in the second multiplexer417, normal data and robust data are combined with a segment synchronization bit sequence and a field synchronization bit sequence, which are transmitted from a synchronization unit (not shown), to thereby generate a transmission data frame. Subsequently, a pilot signal is added in the pilot adder. A symbol stream is modulated into VSB-suppressed carrier in a VSB modulator. An 8-VSB symbol stream of a baseband is converted into a radio frequency signal in an RF converter after all and transmitted.

FIG. 26is a diagram showing a field synchronous segment of a data frame transmitted by the transmitter ofFIG. 4. As shown in the drawing, a segment transmitted from the transmitter400is basically the same as the segment of the ATSC A/53 Standards. If any, in a reserved area corresponding to the last 104 symbols of a segment, 92 symbols except precode 12 symbols contains information for restoring the robust data packet. The information for restoring the robust data packet includes an NRP (refer to equation 1), which is a ratio of robust data to normal data in a field, a coding rate of the robust data, e.g., ½ or ¼, and a robust data coding method. As to be described later, a receiver suggested in the embodiment of the present invention generates a robust data flag out of the information for restoring the robust data packet, and constitutional elements of the receiver can check out whether currently processed data are robust data or not by using the robust data flag.

FIG. 27is a block diagram illustrating a DTV receiver in accordance with an embodiment of the present invention. As shown, a receiver2700includes a tuner2701, an IF filter and detector2703, an NTSC filter2705, an equalizer2707, a trellis decoder2709, a data deinterleaver2711, a packet formatter/robust deinterleaver2713, an RS decoder2715, a data derandomizer2717, a demultiplexer2719, a synch and timing recovery block2721, a field synch decoder2723, and a controller2725.

The tuner2701, the IF filter and detector2703, the NTSC filter2705, the data deinterleaver2711, the RS decoder2715, the synch and timing recovery block2721perform the same functions as the tuner201, the IF filter and detector203, the NTSC filter205, the data deinterleaver211, the RS decoder213, and the synch and timing recovery block215.

The field synch decoder2723receives a segment of a data frame illustrated inFIG. 26, restores the robust data packet restoring information in the reserved area, which includes information on the ratio of robust data to normal data in a field, information on the coding rate of the robust data, and information on a robust data coding method, and transmits it to the controller2725.

FIG. 28is a block diagram showing a controller ofFIG. 27. As shown, the controller2725includes a normal/robust data identifying flag generator2801, a data interleaver2803, a trellis interleaver2805, a delay buffer2807, and a delay calculator2809.

The normal/robust data identifying flag generator2801generates a robust data flag by using the robust data packet restoring information transmitted from the field synch decoder2723.

The generated robust data flag goes through a bit-unit data interleaving and trellis interleaving based on the ATSC A/53 in the data interleaver2803and the trellis interleaver2805and the interleaved robust data flag is transmitted to the equalizer2707and the trellis decoder2709. The robust data flag included in the data frame transmitted from the transmitter400is already interleaved through the data interleaving and the trellis interleaving, the equalizer2707and the trellis decoder2709performs equalization and trellis decoding based on the interleaved robust data flag obtained from the data interleaving and the trellis interleaving.

Meanwhile, the delay buffer2807receives the robust data flag generated in the normal/robust data identifying flag generator2801and transmits the robust data flag to the packet formatter/robust deinterleaver2713in consideration of delay generated while data are processed in the trellis decoder2709and the data deinterleaver2711. Also, the delay buffer2807transmits the robust data flag to the data derandomizer2717, the demultiplexer2719, and the delay calculator2809, individually, in consideration of delay generated while data are processed in the packet formatter/robust deinterleaver2713.

The delay calculator2809calculates delay time of a robust data packet by using the robust data flag, which is obtained in consideration of delay with respect to normal data generated while robust data are processed in the packet formatter/robust deinterleaver2713and transmitted from the delay buffer2807, and the robust data packet restoring information, which is transmitted from the field synch decoder2723, and transmits the calculated delay time to the data derandomizer2717.

The data derandomizer2717is synchronized with a field synchronous signal of a data frame and performs derandomization. The robust data packet restoring information transmitted from the field synch decoder2723includes information on the position of the robust data packet in the data frame. However, the packet formatter/robust deinterleaver2713can process only a robust data packet and, particularly, the deinterleaving process carried out in the robust deinterleaver delays the robust data packet by a few packets.

The delay calculator2809calculates delay time with respect to the robust data packet based on the received robust data packet restoring information and the robust data flag to compensate for the delay with respect to the robust data packet and transmits the delay time to the data derandomizer2717. The data derandomizer2717derandomizes a normal data packet and a robust data packet based on the received robust data flag and the delay time with respect to the robust data packet.

For example, when the nthnormal data packet is derandomized, the next robust data packet to be derandomized is not the (n+1)throbust data packet but it can be the kthrobust data packet (k<n). The delay of the robust data packet is longer than that of the normal data packet, because the delay caused by restoring the original packet in the packet formatter/robust deinterleaver2713is included. Therefore, the data derandomizer2717should perform the derandomization in consideration of the delay.

FIG. 29is a block diagram describing a packet formatter and a robust deinterleaver ofFIG. 27, andFIG. 30is a diagram illustrating a robust data deinterleaver ofFIG. 29. The packet formatter and a robust data deinterleaver are operated in opposite to the robust interleaver/packet formatter407of the transmitter400illustrated inFIG. 5. That is, it removes RS parity (20 bytes) and header bytes (3 bytes) included in the robust data segment (207 bytes) inputted from the data deinterleaver2711and generates robust data packets including information data and null packets. Thus, when a robust data segment having 9 packets (9×207 bytes) is inputted into a packet formatter2901, the packet formatter2901outputs four robust data packets which are formed of information data and five null packets formed of null data. Subsequently, a robust data deinterleaver2903receives the robust data packets inputted from the packet formatter2901on a byte basis, performs deinterleaving, and transmits the robust data packets to a multiplexer2905. During the deinterleaving, null packets among the robust data packets are abandoned and the deinterleaving is carried out only on information packets. A normal data packet has a predetermined delay to be thereby multiplexed with a robust data packet.

The multiplexed normal data packet and robust data packet are transmitted to the RS decoder2715. The RS decoder2715performs RS decoding with respect to each packet and transmits the resultant to the data derandomizer2717.

With reference toFIG. 25again, the demultiplexer2719demultiplexes the normal data packet and the robust data packet based on the robust data flag and outputs them in a form of a serial data stream formed of a 188-byte MPEG compatible data packet.

For the equalizer2707, a known determiner, which is known as a slicer, or a trellis decoder with a trace back of zero (0) is used. The equalizer2707equalizes a received signal based on the interleaved robust data flag obtained from the bit-unit data interleaving and the trellis interleaving based on the ATSC A/53 and transmitted from the controller2725. The signal level of normal data is determined from the 8 levels of {−7,−5,−3,−1,1,3,5,7} as it used to be conventionally, and the signal level of robust data is determined from 4 or 8 levels of {−7,−5,5,7}, {−7,−1,3,5}, {−5,−3,1,7} and {−7,−5,−3,−1,1,3,5,7} according to the coding method in the robust encoder411of the transmitter400.

A robust data signal can be used as decision data used to update a tap coefficient of the equalizer2707. Since precise signal level determination increases a convergence speed of the equalizer, it can improve reception performance for robust data as well as normal data in a Doppler environment.

With respect to a normal data signal, the trellis decoder2709performs trellis decoding on an 8-level signal {−7,−5,−3,−1,1,3,5,7}, which is the same as the conventional technology. With respect to a robust data signal, it performs trellis decoding inversely according to the P-2VSB, E-4VSB or E-8VSB coding method used in the robust encoder411of the transmitter400.

The trellis decoder2709generates one-bit information out of two symbols. For example, when determined signal levels are (5,5) and (7,7) sequentially inFIG. 14, the trellis decoder2709confirms that corresponding informations are 0 and 1 by performing the trellis decoding based on the Table 1 and 2.

According to the present invention, the 8-VSB receiver based on the ATSC A/53 can receive a normal data packet and it can provide backward compatibility by processing a robust data packet as a null packet.

INDUSTRIAL APPLICABILITY

The technology of the present invention can be applied to a DTV transmission/reception system.