Multiple integrated circuit control

In an implementation of multiple integrated circuit control, a multiple integrated circuit controller initiates and controls data transactions between the multiple integrated circuit controller and integrated circuits. A data link communicates the data transactions between the multiple integrated circuit controller and the integrated circuits, and a clock signal link communicates a clock signal generated by the multiple integrated circuit controller to the integrated circuits. The multiple integrated circuit controller includes a first push-pull driver to drive the data transactions on the data link and includes a second push-pull driver to drive the clock signal on the clock signal link.

BACKGROUND

A bus is a network topology or communication circuit by which devices and/or components attached to the bus send and receive data. In an electronic or imaging device, for example, components of the device that are attached to the bus each have a unique address, or identity, by which a particular component can recognize data and/or a communication intended for the component. Imaging devices, such as printing devices and all-in-one devices that scan, print, and copy, have motors, motor drivers, power supplies, memory devices, and any one or more other similar components that are interfaced within a device by an integrated circuit. The integrated circuits interface the components for signal and data communications via a bus network within a device.

DETAILED DESCRIPTION

Multiple integrated circuit control can be implemented as an interface to control multiple integrated circuits, and in an embodiment, is implemented with only a data signal and a clock signal. In an implementation, a multiple integrated circuit controller initiates and controls clock timing and data transactions between the multiple integrated circuit controller and integrated circuits. A data link communicates the data transactions between the multiple integrated circuit controller and the integrated circuits, and a clock signal link communicates a clock signal generated by the multiple integrated circuit controller to the integrated circuits.

Multiple integrated circuit control provides a simple, low-cost interface between multiple integrated circuits to initiate and control data transactions, circuit functions, and component operation. In an embodiment, a multiple integrated circuit controller is coupled to multiple integrated circuits, such as component interface circuits in an electronic device. The data transactions are communicated via shared data signal connections between the multiple integrated circuit controller and the integrated circuits.

FIG. 1illustrates an example of a single-ended interface circuit100in which an embodiment of multiple integrated circuit control can be implemented. A multiple integrated circuit controller102is implemented to control any number of integrated circuits104(1-N). The integrated circuits can be any number of component interface circuits, such as in an electronic or imaging device. For example, an integrated circuit104may be implemented to interface any one or more of motors, motor drivers, power supplies, supervisory circuits, analog to digital converters, general purpose input/outputs, dedicated circuits, memory devices, and any other similar components and devices in an electronic or imaging device. An example of an imaging device is described below with reference to an embodiment of a printing device700shown inFIG. 7. Printing device700includes examples of components and devices that may have an integrated circuit interface which can be controllably coupled to the multiple integrated circuit controller102.

The multiple integrated circuit controller102includes a clock signal output106, a data input108, and a data output110. Each of the integrated circuits104(1-N) include a unique address112(1-N), respectively, that is a static input114(1-N) to define each integrated circuit. Additionally, each of the integrated circuits104(1-N) include a clock input116, a data input118, and a data output120. A data input118and a data output120for an integrated circuit104share a common data channel.

A data bus122links the multiple integrated circuit controller102to each of the integrated circuits104(1-N). In an implementation, the data bus122is a two-wire control data bus that includes a clock signal link124and a data link126. The clock output106of the multiple integrated circuit controller102is coupled to each clock input116(1-N) of the integrated circuits104(1-N) via the clock signal link124. In this embodiment, the data link126operates as a two-way data communication link (e.g., is bi-directional). The data input108of the multiple integrated circuit controller102is coupled to each data output120of the integrated circuits104(1-N) via the data link126, and the data output110of the multiple integrated circuit controller102is coupled to each data input118(1-N) of the integrated circuits104(1-N) also via the data link126. Timing of the system100is controlled to enable one data transaction at any one time to reduce the likelihood of overlapping or interfering data transactions.

The clock signal (e.g., clock output106) is generated and timing of the system100is controlled by the multiple integrated circuit controller102. The multiple integrated circuit controller102includes a push-pull driver128to drive the clock signal106on the clock signal link124. Additionally, data transactions are initiated and controlled by the multiple integrated circuit controller102and the integrated circuits104(1-N) respond to commands from the multiple integrated circuit controller102. The multiple integrated circuit controller102also includes a push-pull driver130to drive a data transaction on the data link126, and includes a data receiver132to receive a data transaction from the data link126.

For a write data transaction to a first integrated circuit104(1), the multiple integrated circuit controller102initiates a communication of write data from the multiple integrated circuit controller102to the integrated circuit104(1) via the data link126. Additionally, for a read data transaction from a second integrated circuit104(2), the multiple integrated circuit controller102initiates a communication of read data from the integrated circuit104(2) to the multiple integrated circuit controller102via the data link126. The multiple integrated circuit controller102initiates and controls the write data transaction and the read data transaction via the two-way data link126.

FIG. 2illustrates an example of a low voltage differential signaling interface circuit200in which an embodiment of multiple integrated circuit control can be implemented. A multiple integrated circuit controller202is implemented to control any number of integrated circuits204(1-N). The integrated circuits can be any number of component interface circuits, such as in an electronic or imaging device as described above with reference toFIG. 1.

The multiple integrated circuit controller202includes a clock signal output206, a data input208, and a data output210. Each of the integrated circuits204(1-N) include a unique address212(1-N), respectively, that is a static input214(1-N) to define each integrated circuit. Additionally, each of the integrated circuits204(1-N) include a clock input216, a data input218, and a data output220.

A data bus222links the multiple integrated circuit controller202to each of the integrated circuits204(1-N). In an implementation, the data bus122includes a differential clock signal link224and a differential data link226. The clock output206of the multiple integrated circuit controller202is coupled to each clock input216(1-N) of the integrated circuits204(1-N) via the differential clock signal link224. In this embodiment, the differential data link226operates as a two-way data communication link. The data input208of the multiple integrated circuit controller202is coupled to each data output220(1-N) of the integrated circuits204(1-N) via the differential data link226. Further, the data output210of the multiple integrated circuit controller202is coupled to each data input218(1-N) of the integrated circuits204(1-N) also via the differential data link226.

The clock signal (e.g., clock output206) is generated and timing of the system200is controlled by the multiple integrated circuit controller202to enable one data transaction at any one time to reduce the likelihood of overlapping or interfering data transactions. The multiple integrated circuit controller202includes a differential driver228to drive the clock signal206on the differential clock signal link224. In this embodiment, the differential clock signal link communicates the clock signal as a low-voltage differential clock signal from the multiple integrated circuit controller202to the integrated circuits204(1-N). Additionally, data transactions are initiated and controlled by the multiple integrated circuit controller202and the integrated circuits204(1-N) respond to commands from the multiple integrated circuit controller202. The multiple integrated circuit controller202also includes a differential driver230to drive a data transaction on the differential data link226, and includes a differential data receiver232to receive a data transaction from the shared differential data link226.

In this embodiment, the differential data link226communicates data between the multiple integrated circuit controller202and the integrated circuits204(1-N) as low-voltage differential data signal(s). For example, for a write data transaction to a first integrated circuit204(1), the multiple integrated circuit controller202initiates a communication of write data from the multiple integrated circuit controller202to the integrated circuit204(1) via the differential data link126. Additionally, for a read data transaction from a second integrated circuit204(2), the multiple integrated circuit controller202initiates a communication of read data from the integrated circuit204(2) to the multiple integrated circuit controller202via the differential data link226.

FIG. 3illustrates an embodiment of timing diagrams300for continuous clock timing302and pulsed clock timing304when data306is communicated between a multiple integrated circuit controller and an integrated circuit (e.g., between multiple integrated circuit controller202and an integrated circuit204via data link226as shown inFIG. 2). The following description and examples reference the exemplary components of the low voltage differential signaling interface circuit200shown inFIG. 2for illustration only and is not so limited. The following description and examples may also be described with reference to the single-ended interface circuit100shown inFIG. 1.

A clock signal, such as from clock output206of multiple integrated circuit controller202to clock inputs216(1-N) of each of the integrated circuits204(1-N), can be generated by the multiple integrated circuit controller202as a continuous clock signal302or can be generated as a pulsed clock signal304. After a data communication (e.g., a data bit transfer), indicated at308and after clock cycle twenty-two (22), the continuous clock signal302continues to cycle at310while the pulsed clock signal304goes idle (e.g., low for single ended system100or zero (“0”) for differential system200) at312. The pulsed clock304can be implemented to reduce electromagnetic interference generated by the clock signal.

In an embodiment, a data transaction is communicated during twenty-two (22) clock cycles as shown for the continuous clock timing302and the pulsed clock timing304. A data communication306includes several components of data bits and, in this example, includes:Start indication314is three (3) bits which initiates on a rising edge of the clock signal (e.g., continuous clock signal302or pulsed clock signal304);TID (target identifier)316is three (3) bits which identifies a particular integrated circuit (e.g., a target device);CNTL (control)318is eight (8) bits which indicates or identifies a unique action, process, or data transaction (e.g., read, write, etc.) for the identified integrated circuit (e.g., the target device);CPTY (control parity)320is one (1) bit plus one (1) bit for bus turnaround and is an odd parity value corresponding to the target identifier (TID)316and the control (CNTL)318values;Data322is communicated as sixteen (16) bits from the sending device to the receiving device (e.g., to the target device);DPTY (data parity)324is one (1) bit plus (1) bit for bus turnaround and is an odd parity value corresponding to the data322and which is communicated by the sending device to the receiving device;DACK (data acknowledgment)326is two (2) bits plus one (1) bit for bus turnaround. The receiving device communicates the data acknowledgement to the sending device to indicate a successful reception of the data322and the data parity (DPTY)324values;Stop indication328is three (3) bits which indicates a data transaction completion and is a communication from the sending device to the receiving device to acknowledge reception of a valid data acknowledgement (DACK)326; andIDLE (e.g.,308) is three (3) bits plus one (1) bit for bus turnaround and is the idle time on the bus before another data transaction is initiated. The multiple integrated circuit controller202drives a zero bit on the data bus222during the idle308.

The data bits (e.g., of data communication306) are transferred on each edge of a clock signal (e.g., clock signals302and304) so that operating frequencies are reduced and to enable efficient use of available bandwidth. This protocol enables controlling the multiple integrated circuits204(1-N) with only one clock signal and one data signal. The protocol also enables the data error checking and recovery from a corrupted data transaction.

Each of the integrated circuits204(1-N) monitor a respective data input218and clock input216. When an integrated circuit204detects a start indication314, it next receives the target identifier (TID)316which is compared to the respective integrated circuit device identifier (e.g., address212). A start indication314is driven by the multiple integrated circuit controller202. An integrated circuit204identified by the target identifier (TID)316is the target device with which the multiple integrated circuit controller202has initiated a data transaction.

The target identifier (TID)316is three (3) bits in this described embodiment which allows eight (8) unique addresses that integrated circuits204can utilize. However, multiple integrated circuit control is not so limited. The target identifier (TID)316can be implemented with any number of data bits to allow addressing any number of integrated circuits (e.g.,204(1) to204(N)).

The control component (CNTL)318defines an operation for the target device (e.g., the identified integrated circuit204) and includes a read/write bit to indicate which device is the sending device and which is the receiving device for a data transaction. In an embodiment, an integrated circuit204determines an operation according to the control component (CNTL)318from a value that is maintained, such as with a memory component. The control parity (CPTY)320is communicated by the multiple integrated circuit controller202to the target device (e.g., the identified integrated circuit204), and the data parity (DPTY)324is communicated by the sending device to the receiving device. In one embodiment, the control parity (CPTY)320and the data parity (DPTY)324are set such that the received value is odd (i.e., single bit odd parity). In another implementation, the error check can be implemented with a checksum, or with any number of other different error checking techniques.

For a write data transaction, the multiple integrated circuit controller202communicates data to a target or receiving device (e.g., an integrated circuit204identified by the target identifier (TID)316). Thus, the multiple integrated circuit controller204is the sending device which communicates the data322, the data parity (DPTY)324, and the stop indication328to the receiving device. The receiving device communicates the data acknowledgement (DACK)326and then responds according to the data after receiving the valid stop indication328.

In an implementation of a write data transaction, the multiple integrated circuit controller202drives the start indication314, the target identifier (TID)316, the control (CNTL)318, and the control parity (CPTY)320values on the data link226. The integrated circuits204(1-N) detect the start indication314and decode the target identifier (TID)316, control (CNTL)318, and control parity (CPTY)320values. In an event that a received control parity (CPTY)320value matches the calculated value for the target identifier (TID)316and control (CNTL)318values, and the target identifier (TID)316value matches an integrated circuit “device ID”, then the identified integrated circuit is the target or receiving device for the data transaction.

The multiple integrated circuit controller202waits for one (1) clock edge to begin communicating the data322and the data parity (DPTY)324values. The target device receives these values and checks the calculated data parity (DPTY)324value against the received data322and data parity (DPTY)324values. If these values match, the target device responds with a data acknowledgement (DACK)326. If these values do not match, the target device aborts the data transaction. The multiple integrated circuit controller202detects the data acknowledgement (DACK)326response from the target device and if an invalid data acknowledgement (DACK)326response is detected, the multiple integrated circuit controller202aborts the data transaction.

If the multiple integrated circuit controller202detects a valid data acknowledgement (DACK)326, however, then the controller202responds with a stop indication328. The target device checks for the stop indication328and, if the stop indication328is not detected, then the target device aborts the data communication and discards the received control (CNTL)318and data322values. If a valid stop indication328is detected, the target device responds as required based on the contents of the control (CNTL)318and data322values. The multiple integrated circuit controller202then drives the data bus222idle (e.g., idle value308) until the beginning of a next data transaction.

For a read data transaction, a target device (e.g., an integrated circuit204identified by the target identifier (TID)316) communicates the data322to the multiple integrated circuit controller202. Thus, the target device is the sending device that generates the data322, data parity (DPTY)324, and stop indication328values. The multiple integrated circuit controller202is the receiving device that generates the data acknowledgement (DACK)326value.

In an implementation of a read data transaction, the multiple integrated circuit controller202drives the start indication314, the target identifier (TID)316, the control (CNTL)318, and the control parity (CPTY)320values on the data link226. The integrated circuits204(1-N) detect the start indication314and decode the target identifier (TID)316, control (CNTL)318, and control parity (CPTY) values. In an event that a received control parity (CPTY)320value matches the calculated value for the target identifier (TID)316and control (CNTL)318values, and the target identifier (TID)316value matches the target device “device ID”, then the sending device is the target device for the data transaction.

The sending device (e.g., an integrated circuit204identified as the target device by the target identifier (TID)316) waits for one (1) clock edge to begin communicating the data322and data parity (DPTY)324values. The receiving device (e.g., the multiple integrated circuit controller202) receives these values and checks the calculated data parity (DPTY)324value against the received data322and data parity (DPTY)324values. If these values match, the receiving device responds with a data acknowledgement (DACK)326. If these values do not match, the receiving device aborts the data transaction. The sending device detects the data acknowledgement (DACK)326response from the receiving device and if an invalid data acknowledgement (DACK)326response is detected, the sending device aborts the data transaction.

If the sending device detects a valid data acknowledgement (DACK)326, however, then the sending device responds with a stop indication328. The receiving device checks for the stop indication328and, if the stop indication328is not detected, the receiving device aborts the data transaction and discards the received data322. If a valid stop indication328is detected, the receiving device loads the received data322and drives the data bus222idle (e.g., idle value308) until the beginning of a next data transaction.

In an embodiment of multiple integrated circuit control, the error checking increases reliability for data communication via a data bus (e.g., data bus122or222shown inFIGS. 1 and 2). For a data transaction between a sending device and a receiving device (e.g., from the multiple integrated circuit controller202to an integrated circuit204, or vice-versa), the two devices error check the data transaction to verify that the data was communicated, received, and not corrupted. If one or the other device detects a data communication error, the multiple integrated circuit controller202can re-initiate the data transaction.

FIG. 4illustrates an embodiment of a multiple integrated circuit control system400that includes a first integrated circuit402and additional integrated circuits404(1-N) in an implementation of multiple integrated circuit control. The integrated circuit402includes a multiple integrated circuit controller, such as controller102shown inFIG. 1in a single-ended interface circuit100, or controller202shown inFIG. 2in a low voltage differential signaling interface circuit200. Multiple integrated circuit controller102/202executes computer executable instructions initiated from processor406. In an embodiment, the integrated circuit402can be implemented in an electronic and/or imaging device, such as an integrated circuit of the exemplary printing device700shown inFIG. 7, for operational control and data transactions within the device.

In an embodiment, the integrated circuit402may be implemented as an application-specific integrated circuit (ASIC) and includes the processor406which can be implemented as any of microprocessors, controllers, and the like which process various instructions (e.g., computer executable instructions) to control the operation of integrated circuit402and the associated components. Each of the integrated circuits404(1-N) include an address408(1-N), respectively, that can be received as a unique address114/214.

A data bus410links the multiple integrated circuit controller102/202to each of the integrated circuits404(1-N). In one implementation, the data bus410includes a clock signal link412and a data link414, such as in the single-ended interface circuit100shown inFIG. 1. In another implementation, the data bus410includes a differential clock signal link412and a differential data link414, such as in the low voltage differential signaling interface circuit200shown inFIG. 2.

The clock output of the multiple integrated circuit controller102/202is coupled to a clock input of the integrated circuits404(1-N) via the clock signal link412. The data input/output of the multiple integrated circuit controller102/202is coupled to a data input/output of the integrated circuits404(1-N) via the data link414.

In an embodiment of multiple integrated circuit control, the bus timing as detected by the multiple integrated circuit controller102/202is different than the timing detected by the integrated circuits404(1-N). This improves bus reliability and the timing on the data bus410. The multiple integrated circuit controller102/202generates the clock signal which appears more accurate to the controller than to the integrated circuits404(1-N) that can only respond to detected clock signal edges. Additionally, the integrated circuits404(1-N) detect a clock signal that is skewed in time relative to the clock signal that the multiple integrated circuit controller102/202generates.

The multiple integrated circuit controller102/202receives data returned from a receiving device the controller102/202has generated a clock edge and the edge has traveled the length of data bus410, which may be cable or wire connection. The receiving device receives the edge of the clock signal and communicates a component of the data transaction (e.g., data306) via the data bus410which reverse travels the length of data bus410back to the controller102/202. This may cause the data arrival at the controller102/202to be skewed relative to the clock signal that it generated. An integrated circuit404detects the data and the clock signal after each is communicated together one length of data bus410. Thus, the data signal and the clock signal may substantially coincide (e.g., are not skewed in time relative to each other). Accordingly, the controller102/202and the integrated circuits404(1-N) implement a different timing to achieve the desired timing detected at the devices.

The multiple integrated circuit controller102/202drives the data approximately mid cycle of a clock signal high or low which enables a position of the data signal to be either advanced or delayed relative to the center of the clock signal. This allows for a desired setup and hold time for an integrated circuit404to achieve increased bus performance. The integrated circuit404then samples the data on the next clock edge.

An integrated circuit404drives the data on each clock edge and the controller102/202samples the data just before it drives the next clock edge. This allows an increased amount of time for the integrated circuit404to receive the clock signal and drive the new data to the controller102/202before the controller102/202samples the data and drives the next clock edge. The time duration that the controller102/202waits after sampling the data to drive the next clock signal can be determined by data hold times at the controller102/202.

A method for multiple integrated circuit control may be described in the general context of computer executable instructions. Generally, computer executable instructions include routines, programs, objects, components, data structures, and the like that perform particular function(s) or implement data type(s). Furthermore, a method for multiple integrated circuit control can be implemented in any suitable hardware, software, firmware, or combination thereof.

FIG. 5illustrates a method500for an embodiment of multiple integrated circuit control that can be implemented to control data transactions between a multiple integrated circuit controller and one or more integrated circuits. The order in which the method is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method.

At block502, a clock signal is communicated from the multiple integrated circuit control to the integrated circuits via a first data link. For example, a clock signal (e.g., clock output106of multiple integrated circuit controller102inFIG. 1) can be communicated to the integrated circuits104(1-N) as clock inputs116(1-N), respectively, via the clock signal link124. The clock signal106can be driven on the data link126with the push-pull driver128of the multiple integrated circuit control102. Further, a clock signal (e.g., clock output206of multiple integrated circuit controller202inFIG. 2) can be communicated as a low voltage differential clock signal to the integrated circuits204(1-N) as clock inputs216(1-N), respectively, via the differential clock signal link224. The clock signals can be communicated as a continuous clock signal302(FIG. 3) or as a pulsed clock signal304to the integrated circuits.

At block504, data transactions are controlled between the multiple integrated circuit control and one or more of the integrated circuits via a second data link. For example, the multiple integrated circuit controller202is configured to control a write data transaction from the controller202to a first integrated circuit204(1) via the differential data link226, and is further configured to control a read data transaction from a second integrated circuit204(2) to the controller,202also via the differential data link226.

At block506, data is communicated between the multiple integrated circuit control and one or more of the integrated circuits via the second data link. For example, data306(FIG. 3) can be communicated as write data from the multiple integrated circuit controller102to an integrated circuit104via the data link126and/or data306can be communicated as read data from an integrated circuit104to the multiple integrated circuit controller102also via the data link126. Further, data306can be communicated as a low voltage differential data signal via the differential data link226between the multiple integrated circuit controller202and an integrated circuit204.

FIG. 6illustrates a method600for an embodiment of multiple integrated circuit control that can be implemented to control a data transaction between a multiple integrated circuit controller and an integrated circuit. The order in which the method is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method.

At block602, a data transaction start indication is communicated from a multiple integrated circuit control to integrated circuits. For example, the multiple integrated circuit controller202communicates a data transaction start indication314to the integrated circuits204(1-N). At block604, a unique target identifier is communicated to initiate the data transaction with an integrated circuit that is identified by the unique target identifier. For example, the multiple integrated circuit controller202communicates a unique target identifier (TID)316to the integrated circuits204(1-N), one of which is identified by the unique target identifier (TID)316.

At block606, control data is communicated to define the data transaction with the identified integrated circuit. For example, the multiple integrated circuit controller202communicates a control (CNTL)318to the identified integrated circuit204to define the data transaction, such as a read data transaction, a write data transaction, and the like. At block608, a control parity bit is communicated for the unique target identifier and for control data error checking at the identified integrated circuit. For example, the multiple integrated circuit controller202communicates a control parity (CPTY)320to the identified integrated circuit204.

At block610, the data is communicated between the multiple integrated circuit control and the identified integrated circuit. For example, if the data322is communicated from the multiple integrated circuit controller202to the identified integrated circuit204, then the controller202is a data sending device and the identified integrated circuit204is a data receiving device. If, however, the data322is communicated from the identified integrated circuit204to the controller202, then the controller202is the data receiving device and the identified integrated circuit204is the data sending device.

At block612, a data parity bit is communicated for data error checking at the data receiving device (e.g., the sending device communicates the data parity bit to the receiving device). For example, the sending device communicates a data parity (DPTY)324to the receiving device. At block614, a data acknowledgement is communicated from the data receiving device to the data sending device to indicate receipt of the data and the data parity bit. For example, the receiving device communicates a data acknowledgement (DACK)326to the sending device. At block616, a data transaction stop indication is communicated from the data sending device to the data receiving device to indicate receipt of the data acknowledgement. For example, the sending device communicates a stop indication322to the receiving device.

FIG. 7illustrates various components of an embodiment of a printing device700in which multiple integrated circuit control can be implemented. General reference is made herein to one or more printing devices, such as printing device700. As used herein, “printing device” means any electronic device having data communications, data storage capabilities, and/or functions to render printed characters, text, graphics, and/or images on a print media. A printing device may be a printer, fax machine, copier, plotter, and the like. The term “printer” includes any type of printing device using a transferred imaging medium, such as ejected ink, to create an image on a print media. Examples of such a printer can include, but are not limited to, inkjet printers, electrophotographic printers, plotters, portable printing devices, as well as all-in-one, multi-function combination devices.

Printing device700includes a print engine702that includes mechanisms arranged to selectively apply an imaging medium such as liquid ink, toner, and the like to a print media in accordance with print data corresponding to a print job. The print media can include any form of media used for printing such as paper, plastic, fabric, Mylar, transparencies, and the like, and different sizes and types such as 8½×11, A4, roll feed media, etc. Printing device700also includes various electrical hardware704which may include a multiple integrated circuit controller102/202, an integrated circuit104/204, any of the various components of an embodiment of the single-ended interface circuit100shown inFIG. 1, and any of the various components of an embodiment of the low voltage differential signaling interface circuit200shown inFIG. 2.

Printing device700may include one or more processors706(e.g., any of microprocessors, controllers, and the like) which process various instructions (e.g., computer executable instructions) to control the operation of printing device700and to communicate with other electronic and computing devices. Further, printing device700can be implemented with one or more memory components708, examples of which include random access memory (RAM), a disk drive, and non-volatile memory (e.g., any one or more of a ROM, flash memory, EPROM, EEPROM, etc.). The one or more memory components maintain information and data related to operational aspects of printing device700, as well as application program(s)710which can be executed on processor(s)706to initiate and/or implement a method for an embodiment of multiple integrated circuit control.

Although embodiments of multiple integrated circuit control have been described in language specific to structural features and/or methods, it is to be understood that the subject of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as exemplary implementations of multiple integrated circuit control.