Methods of forming conductive jumper traces

Methods of forming conductive jumper traces for semiconductor devices and packages. Substrate is provided having first, second and third trace lines formed thereon, where the first trace line is between the second and third trace lines. The first trace line can be isolated with a covering layer. A conductive layer can be formed between the second and third trace lines and over the first trace line by a depositing process followed by a heating process to alter the chemical properties of the conductive layer. The resulting conductive layer is able to conform to the covering layer and serve to provide electrical connection between the second and third trace lines.

TECHNICAL FIELD

The present disclosure relates in general to semiconductor devices, more particularly, to methods of forming conductive jumper traces for semiconductor devices and packages.

BACKGROUND

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly can refer to both a single semiconductor device and multiple semiconductor devices.

SUMMARY

Methods of forming conductive jumper traces for semiconductor devices and packages. In one embodiment, a method of forming conductive jumper traces for semiconductor devices and packages includes: (a) providing a substrate and (b) forming first, second and third trace lines over the substrate, where the first trace line is between the second trace line and the third trace line. Next, the method includes: (c) isolating the first trace line with a covering layer and (d) forming a conductive layer between the second trace line and the third trace line. The forming step (d) includes the following sub-steps: (i) depositing the conductive layer having a first state and (ii) heating the conductive layer from the first state to a second state, where the second state is different than the first state. The resulting conductive layer is able to conform to the covering layer and operable to provide electrical connection between the second trace line and the third trace line.

In one embodiment, the forming step (b) further includes forming a fourth trace line over the substrate, where the fourth trace line is adjacent the first trace line and between the second trace line and the third trace line. In another embodiment, the isolating step (c) includes isolating the fourth trace line with the covering layer. In one embodiment, the method further includes: mounting an integrated circuit die over the substrate, where the integrated circuit die is adjacent at least one of the second trace line and the third trace line, and coupling the integrated circuit die to at least one of the second trace line and the third trace line with a connective material. The connective material allows the integrated circuit die to be in communication with the at least one of the second trace line and the third trace line. In one embodiment, the mounting step and the coupling step can be performed at the same time as the forming step (b) or after the forming step (b). In one embodiment, the depositing step (i) of the forming step (d) includes depositing the conductive layer including at least one of silver (Ag), platinum (Pt), gold (Au), copper (Cu), carbon nanotube (CNT), graphene, organic metal, and mixtures thereof. In another embodiment, the method further includes treating the second trace line and the third trace line with hydrophilic plasma prior to the forming step (d).

In one embodiment, a method of forming conductive jumper traces for semiconductor devices and packages includes: (a) providing a substrate and (b) forming first, second, third and fourth trace lines over the substrate, where the first trace line is adjacent the fourth trace line and both lines are in between the second trace line and the third trace line. Next, the method includes: (c) isolating the first trace line and the fourth trace line with a covering layer and (d) forming a conductive layer between the second trace line and the third trace line. The forming step (d) includes the following sub-steps: (i) depositing the conductive layer having a first state and (ii) heating the conductive layer from the first state to a second state, the second state different than the first state. The resulting conductive layer is able to conform to the covering layer and operable to provide electrical connection between the second trace line and the third trace line.

In one embodiment, the method further includes: mounting an integrated circuit die over the substrate, where the integrated circuit die is adjacent at least one of the second trace line and the third trace line, and coupling the integrated circuit die to at least one of the second trace line and the third trace line with a connective material. The connective material allows the integrated circuit die to be in communication with the at least one of the second trace line and the third trace line. In one embodiment, the mounting step and the coupling step can be performed at the same time as the forming step (b) or after the forming step (b). In one embodiment, the depositing step (i) of the forming step (d) includes depositing the conductive layer including at least one of silver (Ag), platinum (Pt), gold (Au), copper (Cu), carbon nanotube (CNT), graphene, organic metal, and mixtures thereof. In another embodiment, the method further includes treating the second trace line and the third trace line with hydrophilic plasma prior to the forming step (d).

In one embodiment, a method of forming conductive jumper traces for semiconductor devices and packages includes: (a) providing a substrate, and (b) forming first, second and third trace lines over the substrate, where the first trace line is between the second trace line and the third trace line. Next, the method includes: (c) isolating a portion of the first trace line with a first covering layer, and (d) forming a first conductive layer between the second trace line and the third trace line. The forming step (d) includes the following sub-steps: (i) depositing the first conductive layer having a first state and (ii) heating the first conductive layer from the first state to a second state, where the second state is different than the first state. The resulting conductive layer is able to conform to the first covering layer and operable to provide electrical connection between the second trace line and the third trace line. Next, the method includes: (e) isolating a portion of the first conductive layer with a second covering layer and (f) forming a second conductive layer over the second covering layer. The forming step (f) includes the following sub-steps: (i) depositing the second conductive layer having a third state and (ii) heating the second conductive layer from the third state to a fourth state, where the fourth state is different than the third state. The resulting second conductive layer is able to conform to the second covering layer.

In one embodiment, the forming step (b) further includes forming a fourth trace line over the substrate, where the fourth trace line is adjacent the first trace line and between the second trace line and the third trace line. In another embodiment, the isolating step (c) includes isolating a portion of the fourth trace line with the first covering layer. In yet another embodiment, the forming step (b) further includes: forming a fourth trace line over the substrate, and connecting the second conductive layer from the fourth trace line and at least one of the first trace line, the second trace line and the third trace line. In one embodiment, the method further includes: mounting an integrated circuit die over the substrate, where the integrated circuit die is adjacent at least one of the second trace line and the third trace line, and coupling the integrated circuit die to at least one of the second trace line and the third trace line with a connective material. The connective material allows the integrated circuit die to be in communication with the at least one of the second trace line and the third trace line.

In one embodiment, the mounting step and the coupling step can be performed at the same time as the forming step (b) or after the forming step (b). In another embodiment, the depositing step (i) of the forming step (d) includes depositing the first conductive layer including at least one of silver (Ag), platinum (Pt), gold (Au), copper (Cu), carbon nanotube (CNT), graphene, organic metal, and mixtures thereof, and the depositing step (i) of the forming step (f) includes depositing the second conductive layer including at least one of silver (Ag), platinum (Pt), gold (Au), copper (Cu), carbon nanotube (CNT), graphene, organic metal, and mixtures thereof. In yet another embodiment, the method further includes treating the second trace line and the third trace line with first hydrophilic plasma prior to the forming step (d), and treating the second covering layer with second hydrophilic plasma prior to the forming step (f).

Other variations, embodiments and features of the present disclosure will become evident from the following detailed description, drawings and claims.

DETAILED DESCRIPTION OF THE DISCLOSURE

It will be appreciated by those of ordinary skill in the art that the embodiments disclosed herein can be embodied in other specific forms without departing from the spirit or essential character thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive.

The present disclosure is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the disclosure is described in terms of the best mode for achieving the disclosure's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. In one embodiment, the portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. In another embodiment, the portion of the photoresist pattern not subjected to light, i.e., the negative photoresist, is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

Patterning is the basic operation by which portions of the top layers on the semiconductor wafer surface are removed. Portions of the semiconductor wafer can be removed using photolithography, photomasking, masking, oxide or metal removal, photography and stenciling, and microlithography. Photolithography includes forming a pattern in reticles or a photomask and transferring the pattern into the surface layers of the semiconductor wafer. Photolithography forms the horizontal dimensions of active and passive components on the surface of the semiconductor wafer in a two-step process. First, the pattern on the reticle or masks is transferred into a layer of photoresist. Photoresist is a light-sensitive material that undergoes changes in structure and properties when exposed to light. The process of changing the structure and properties of the photoresist occurs as either negative-acting photoresist or positive-acting photoresist. Second, the photoresist layer is transferred into the wafer surface. The transfer occurs when etching removes the portion of the top layers of semiconductor wafer not covered by the photoresist. The chemistry of photoresists is such that the photoresist remains substantially intact and resists removal by chemical etching solutions while the portion of the top layers of the semiconductor wafer not covered by the photoresist is removed. The process of forming, exposing, and removing the photoresist, as well as the process of removing a portion of the semiconductor wafer can be modified according to the particular resist used and the desired results.

In negative-acting photoresists, photoresist is exposed to light and is changed from a soluble condition to an insoluble condition in a process known as polymerization. In polymerization, unpolymerized material is exposed to a light or energy source and polymers form a cross-linked material that is etch-resistant. In most negative resists, the polymers are polyisopremes. Removing the soluble portions (i.e. the portions not exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the opaque pattern on the reticle. A mask whose pattern exists in the opaque regions is called a clear-field mask.

In positive-acting photoresists, photoresist is exposed to light and is changed from relatively nonsoluble condition to much more soluble condition in a process known as photosolubilization. In photosolubilization, the relatively insoluble resist is exposed to the proper light energy and is converted to a more soluble state. The photosolubilized part of the resist can be removed by a solvent in the development process. The basic positive photoresist polymer is the phenol-formaldehyde polymer, also called the phenol-formaldehyde novolak resin. Removing the soluble portions (i.e. the portions exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the transparent pattern on the reticle. A mask whose pattern exists in the transparent regions is called a dark-field mask.

After removal of the top portion of the semiconductor wafer not covered by the photoresist, the remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

FIG. 1illustrates electronic device50having a chip carrier substrate or printed circuit board (PCB)52with a plurality of semiconductor packages mounted on its surface. Electronic device50can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1for purposes of illustration.

Electronic device50can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device50can be a subcomponent of a larger system. For example, electronic device50can be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, electronic device50can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.

For the purpose of illustration, several types of first level packaging, including bond wire package56and flipchip58, are shown on PCB52. Additionally, several types of second level packaging, including ball grid array (BGA)60, bump chip carrier (BCC)62, dual in-line package (DIP)64, land grid array (LGA)66, multi-chip module (MCM)68, quad flat non-leaded package (QFN)70, and quad flat package72, are shown mounted on PCB52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB52. In some embodiments, electronic device50includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIGS. 2a-2cshow exemplary semiconductor packages.FIG. 2aillustrates further detail of DIP64mounted on PCB52. Semiconductor die74includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die74. Contact pads76are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die74. During assembly of DIP64, semiconductor die74is mounted to an intermediate carrier78using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads80and bond wires82provide electrical interconnect between semiconductor die74and PCB52. Encapsulant84is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating semiconductor die74or bond wires82.

FIG. 2billustrates further detail of BCC62mounted on PCB52. Semiconductor die88is mounted over carrier90using an underfill or epoxy-resin adhesive material92. Bond wires94provide first level packaging interconnect between contact pads96and98. Molding compound or encapsulant100is deposited over semiconductor die88and bond wires94to provide physical support and electrical isolation for the device. Contact pads102are formed over a surface of PCB52using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads102are electrically connected to one or more conductive signal traces54in PCB52. Bumps104are formed between contact pads98of BCC62and contact pads102of PCB52.

InFIG. 2c, semiconductor die58is mounted face down to intermediate carrier106with a flipchip style first level packaging. Active region108of semiconductor die58contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region108. Semiconductor die58is electrically and mechanically connected to carrier106through bumps110.

BGA60is electrically and mechanically connected to PCB52with a BGA style second level packaging using bumps112. Semiconductor die58is electrically connected to conductive signal traces54in PCB52through bumps110, signal lines114, and bumps112. A molding compound or encapsulant116is deposited over semiconductor die58and carrier106to provide physical support and electrical isolation for the device. The flipchip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die58to conduction tracks on PCB52in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die58can be mechanically and electrically connected directly to PCB52using flipchip style first level packaging without intermediate carrier106.

FIG. 3ashows a semiconductor wafer120with a base substrate material122, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of semiconductor die or components124is formed on wafer120separated by a non-active, inter-die wafer area or saw street126as described above. Saw street126provides cutting areas to singulate semiconductor wafer120into individual semiconductor die124.

FIG. 3bshows a cross-sectional view of a portion of semiconductor wafer120. Each semiconductor die124has a back surface128and active surface130containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface130to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die124may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing.

FIG. 4is a semiconductor package400having a conductive jumper trace known in the art. In this package400, a semiconductor die or device88can be mounted over a carrier or substrate90via an adhesive92similar to that described above. The semiconductor device88can be attached directly to the substrate90or to the substrate via a dielectric layer or solder resist136. The semiconductor device88includes a top contact pad96that can be connected to various contact pads102on the surface of the substrate90via a bond wire94. In this example, the surface of the substrate90includes at least four contact pads102a,102b,102c,102dalthough it is understood that there can be fewer or more contact pads102as necessary. The contact pads102can be protected by a covering layer136such as solder resist or dielectric material, which can protect or isolate the contact pads102as necessary. In this instance, each contact pad102a,102b,102c,102dcan be isolated from one another. In these prior art semiconductor packages400, forming conductive jumper traces using bond wires94can be challenging when the conductive jumper traces are required to traverse such a long distance. For instance, the bond wire94is required to jump across at least three other contact pads102a,102b,102cin order to make electrical connection with the farthest contact pad102d. Not only is there great costs associated with long bond wires94, but reliability and throughput of the wiring process become challenging as more and more jumper bond wires94are required.

FIG. 5is a semiconductor package500having a conductive jumper trace according to one embodiment of the present disclosure. This example is substantially similar to that of the prior art with the exception that the bond wire94has been reduced according to the present disclosure. In some instance, the bond wire94may be completely eliminated. The reduction increases reliability and reduces costs associated with consuming long bond wire material.

In the currently disclosed semiconductor package500, a semiconductor die or device88can be mounted over a carrier or substrate90with an adhesive92similar to that described above. The device88can be directly attached to the substrate90or on a solder resist layer136. The semiconductor device88includes a top contact pad96that can be connected to various contact pads102on the surface of the substrate90via a bond wire94. In this instance, the top contact pad96of the semiconductor device88is connected to the contact pad102aclosest to the semiconductor device88. The next two contact pads102b,102care insulated by a covering layer136such as solder resist or dielectric material. A conductive layer180can be conformally formed over the covering layer136to provide electrical connection between the closest contact pad102aand the farthest contact pad102d. The result is increased throughput and reliability as well as decreased cost with the conductive layer180serving or functioning as the conductive jumper trace.

The conductive layer180can be formed by a direct writing process including the likes of screen printing or electro-hydro dynamic (EHD) dispensing. Screen printing involves the use of a paste material, screen mesh, an emulsion material and application of force via an applicator with the substrate held by a nest. On the other hand, EHD dispensing involves the use of an electric field to dispense droplets from a nozzle. In one embodiment, formation of the conductive layer180includes the likes of inkjet printing technology, which can be continuous or on demand, and can be carried out in vertical or horizontal fashion. The use of inkjet printing to form the conductive layer180may provide visible and conductive metal lines that are halogen free. The ink material that is involved may be of an organic metal or a silver complex. The formation of the conductive layer180as well as the improved conductive jumper trace will be discussed in more detail below.

FIGS. 6A-6Bare top-down and cross-sectional views of a semiconductor package600having a conductive jumper trace according to one embodiment of the present disclosure.FIG. 6Ais a top-down view of the semiconductor package600whileFIG. 6Bis a cross-sectional view through A-A of the semiconductor package600. As shown, the semiconductor package600includes a substrate90having a plurality of trace lines54formed thereon. The substrate90can be a semiconductor wafer or a chip carrier similar to those described above. After providing the substrate90, trace lines54can be formed thereon by deposition or other processes as described above. In one embodiment, four trace lines54a,54b,54c,54dare formed over the substrate90although it is understood that there can be more or fewer trace lines54as necessary. In this embodiment, a first trace line54bcan be formed adjacent a fourth trace line54c, where the first trace line54band the fourth trace line54care formed between the second trace line54aand the third trace line54d. In another embodiment, the fourth trace line54cmay not be necessary with the first trace line54bbetween the second trace line54aand the third trace line54d, the three trace lines54a,54b,54dformed over the substrate90.

The first trace line54band the fourth trace line54ccan be electrically isolated from the second trace line54aand the third trace line54dby a covering layer136as best illustrated inFIG. 6B. Similarly, if only three trace lines54were present, the first trace line54bcan likewise be electrically isolated from the second trace line54aand the third trace line54d, also by a covering layer136. The covering layer136can be an insulating layer or a protecting layer. The covering layer136can be dielectric material or solder resist. In some embodiments, the covering layer136can be an encapsulation material, an underfill or molding material such as an epoxy compound. In other embodiments, the covering layer136can also provide magnetic isolation or protection. The covering layer136can extend to other parts of the package600.

When the first trace line54bor the first trace line54band the fourth trace line54chave been electrically isolated or insulated, a conductive layer180can be formed between the second trace line54aand the third trace line54dby an inkjet deposition (e.g., printing) process. In other embodiments, the conductive layer180can be formed by screen printing or EHD dispensing. This conductive layer180can serve as a conductive jumper trace by providing electrical connection between the second trace line54aand the third trace line54d. The inkjet deposition process involves depositing a conductive material, dispersing or allowing conductive material to disperse, and heating or curing of the conductive material to solidify the conductive material. In the alternative, the screen printing or EHD dispensing processes include depositing a conductive material having a first material state, where the first material state includes liquid, viscous or paste form. The conductive liquid or paste need not go through the dispersion or spreading process but instead can be heated from the first material state to a second material state, where the second material state is different from the first material state. The second material state may include solid, crystal or sintered form. In some embodiments, the first material state may have an initial profile while the second material state may have a final profile where the final profile is different from the initial profile. The difference in the profile may be a result of the heating or curing process which may drive out the fluid or viscous material in the liquid or paste causing the conductive material to undergo shrinkage into a more solid or sintered form.

The conductive layer180, formed of the conductive material in ink, paste, or liquid form, can be conformally formed over the covering layer136. In other words, the conductive material is able to follow the shape or contour of the covering layer136including any angles and crevices thereof, and fill in any of such openings or recesses as necessary in forming the conductive layer180. In some embodiments, terminal openings160A,160B may be formed about the ends of the conductive layer180to ensure conformity and reliability of the conductive material. These terminal openings160A,160B may be formed as solder mask openings similar to the solder mask opening218for the terminal ends of the trace lines54. In other embodiments, the package600may include through-silicon vias (TSVs) or backside vias220and backside trace lines224allowing electrical connections to be made to the other side of the substrate90. The step-by-step detail of forming the semiconductor package600having the conductive jumper trace will become more apparent in subsequent figures and discussion.

FIGS. 7A-7B to 10A-10Bare top-down and cross-sectional views of a process flow for forming the semiconductor package600ofFIGS. 6A-6B.FIG. 7Ais a top-down view of a substrate90having a plurality of trace lines54formed thereon whileFIG. 7Bis a cross-sectional view through A-A of the substrate90and the trace lines54. Like above, the substrate90can be a semiconductor wafer or a chip carrier, where trace lines54can be formed over the substrate90by the deposition processes described above. In one embodiment, four trace lines54a,54b,54c,54dcan be formed over the substrate90where a first trace line54bis formed adjacent a fourth trace line54c, where the first trace line54band the fourth trace line54care in between the second trace line54aand the third trace line54d. In another embodiment, three trace lines54a,54b,54dare formed over the substrate90where a first trace line54bis formed between the second trace line54aand the third trace line54d. Backside traces224and backside vias220can be formed on the opposite side of the substrate90. In other words, backside traces224and backside vias220can be formed on the side opposite the trace lines54(not shown in the cross-sectional view ofFIG. 7B). For example, the first trace line54bcan be routed to the backside of the substrate90through the backside via220and the backside trace line224at a terminal end of the first trace line54bas best illustrated inFIG. 7A.

FIG. 8Ais a top-down view ofFIG. 7Ahaving a covering layer136formed thereon whileFIG. 8Bis a cross-sectional view through A-A ofFIG. 8A. As shown, the covering layer136can be formed over the trace lines54. In one embodiment, the covering layer136is shown to be insulating or isolating the first trace line54band the fourth trace line54calthough it is understood that the covering layer136can also insulate or isolate only the first trace line54b. In some embodiments, although the covering layer136is shown isolating the entire trace line54b,54c, it is also possible that the covering layer136need only isolate portions of the trace line54b,54cas necessary. Specifically, portion of the trace line54b,54cwhich will come into contact with the conductive material180may be isolated so as to prevent shorting across the trace lines54. In other embodiments, the covering layer136may isolate portions of the second trace line54aand the third trace line54dalthough this need not be the case. In other words, the covering layer136need not extend the size of the substrate90but can be limited to only the relevant portions of the first trace line54band/or the fourth trace line54cin between the second trace line54aand the third trace line54d.

The covering layer136, as discussed above, can be formed of dielectric material or solder resist. The solder resist may be formed by deposition and photolithography, among other suitable techniques. Likewise, a dielectric material can be formed by deposition, lithography and etching to arrive at the desired pattern. The covering layer136may also be an encapsulation material such as underfill or molding compound including, for example, epoxy molding compound. The covering layer136helps to facilitate formation of the conductive layer180as will become more apparent in subsequent figures and discussion. In some embodiments, the covering layer136can be formed at the same time as the solder mask opening218for the terminal ends of the trace lines54as well as the terminal openings160A,160B for the electrical connections between the second trace line54aand the third trace line54d.

FIG. 9Ais a top-down view ofFIG. 8Ashowing the beginning steps of forming a conductive layer180andFIG. 9Bis a cross-sectional view through A-A ofFIG. 9A. As shown, after forming the covering layer136over the first trace line54band/or the fourth trace line54c, a conductive material for forming a conductive layer180can be deposited and formed thereon to provide electrical connection between the second trace line54aand the third trace line54d. By using the covering layer136as an insulator, the subsequently formed conductive layer180is able to serve its function as a conductive jumper trace that jumps or hops across one or more trace lines54.

As discussed above, the conductive layer180can be formed over the covering layer136electrically connecting the trace lines54a,54dvia an inkjet printing process. The formation of the conductive material for the conductive layer180starts with an inkjet head162, which may be provided over the desired area of interest. The inkjet head162can deliver a resolution of 1,200 dots per inch (DPI) although other inkjet heads162with other resolution may be utilized. Upon passing over the desired area, a nozzle164from the inkjet head162may cause inkjet droplets166to be deposited onto the covering layer136. The inkjet droplets166may also be deposited or dropped into the terminal openings160A,160B as well as adjacent the second trace line54aand the third trace line54d. The inkjet droplets166may also be deposited over the covering layer136forming a path that connects the second trace line54aand the third trace line54d. The inkjet droplets166, containing an ink material, may subsequently be formed into the desired conductive layer180. In this example, the deposition can be accomplished via gravity. In other instances, the deposition can be carried out via other suitable mechanical and/or electrical assistance including the likes of an electric field, for example.

The number of nozzles164on the inkjet head162can vary. For example, there can be a total of 2,048 nozzles164providing a coverage width of about 43 millimeters. The nozzles164and the head162may have a writing speed of about 200 millimeters per second. The number of droplets166can be varied depending on the desired thickness and/or width of the conductive material180to be achieved. For example, the number of droplets166can vary between about 1 droplet to about 10 droplets, or greater than 10 droplets166. The inkjet droplet166may have a diameter of anywhere from about 3 microns to about 12 microns depending on the viscosity and the volume of the ink being consumed. Meanwhile, the thickness of the conductive layer180formed may be about 3 microns thick, or thinner than 3 microns, or thicker than 3 microns. In this instance, the amount of ink can be about 1 picoliter. Because of the plurality of nozzles164and the speed at which the head162can process a substrate, inkjet printing throughput can be on the matter of seconds per strip of devices.

In one embodiment, the inkjet droplet166may be a conductive material180in ink or liquid form. The types of conductive material180that can be in liquid or ink form include silver (Ag), platinum (Pt), gold (Au), copper (Cu), carbon nanotube (CNT), graphene, organic metal, or mixtures thereof. In another embodiment, the inkjet droplet166that ultimately forms the conductive layer180may be a conductive polymeric material with metallic properties.

In another embodiment, instead of using inkjet printing and inkjet droplet166, conductive material180may be deposited in paste form and that deposition can be made by screen printing or EHD dispensing. The paste may have material properties similar to the inkjet droplet166disclosed above including without limitation silver (Ag) paste, platinum (Pt) paste, gold (Au) paste or copper (Cu) paste, to name a few.

In one embodiment, prior to the depositing or dropping of the inkjet droplet166step as shown inFIG. 9B, the surfaces of the substrate90including that of the covering layer136and the trace lines54a,54din the terminal openings160A,160B may be treated with a hydrophilic plasma process. Treating the covering layer136and the trace lines54a,54din the terminal openings160A,160B with hydrophilic plasma may raise the surface energy of the covering layer136and the trace lines54a,54din the terminal openings160A,160B leading to increased spreading out of the conductive ink.

After the inkjet droplets166have been sitting on the covering layer136and pooling about the terminal openings160A,160B, the droplets166may begin to disperse or spread out. Because of the low viscosity (<100 centipoise), the inkjet droplet166is able to spread out to cover the desired surface area. For example, the inkjet droplet166may have an initial area upon deposition. Over time, the inkjet droplet166may disperse or be allowed to disperse thereby arriving at a final area. In one embodiment, the final area may be greater than the initial area. In another embodiment, the final area may be configured by the terminal openings160A,160B. In other words, the terminal openings160A,160B may serve as the pool or deep end of the pool thereby pooling or allowing the droplets166to pool around the terminal openings160A,160B. This can be best illustrated inFIG. 10Band will be discussed further below. The dispersion process of the droplets166may be further enhanced if the covering layer136and the trace lines54a,54din the terminal openings160A,160B had been subjected to the hydrophilic plasma process as discussed above, which helps to raise the surface energy and enhance the dispersion process.

In another embodiment, if the screen printing or EHD dispensing is utilized, no dispersion step would be necessary as the desired profile may be formed after the deposition step.

After deposition and optional dispersion of the conductive material180, a heating process may be carried out to further sinter the material. In one embodiment, the heating process may include oven or ultra-violet curing or both. The heating process may also include a reflow process for purposes of sintering the conductive particles that are in the conductive ink or paste material180. Once heated or cured, the conductive material180, formed over the covering layer136, may serve to provide electrical connection between the second trace line54aand the third trace line54d.

FIGS. 10A-10Bare the top-down and cross-sectional views of the semiconductor package600ofFIGS. 6A-6Bwith a conductive layer as a conductive jumper trace according to one embodiment of the present disclosure.FIG. 10Ais a top-down view whileFIG. 10Bis a cross-sectional view through A-A ofFIG. 10A.FIGS. 10A-10Bare substantially similar to that ofFIGS. 9A-9Bexcept that the inkjet droplets166have completely filled the terminal openings160A,160B and are confined to the desired layout (e.g., shape and size) of the conductive layer180. Once the deposited droplets166or conductive material180have achieved the desired dispersion, if necessary, the conductive material180may be heated or cured as discussed above to arrive at the targeted conductive layer180. Although shown to have an elongated cylindrical structure from the top view, the conductive layer180can take on any polygonal shape as necessary. In addition, the conductive layer180can substantially conform to the shape or outline of the structures underneath. In some embodiments, the conductive layer180can conform to the shape of the covering layer136as well as the shape of the trace lines54a,54d. In this example, both the covering layer136and the trace lines54a,54dhave substantially rectangular cross-sectional shapes although it is understood that because of the depositing and dispensing process in liquid or paste form, the conductive layer180can contour to any shapes including without limitation circular, spherical or square.

In one embodiment, an integrated circuit die88can be mounted over the substrate90adjacent the solder mask opening218similar to that shown inFIG. 5. In this example, the integrated circuit die88can be attached to the covering layer136like a solder resist with an adhesive92. The solder mask opening218can include contact pads102which are in electrical communication with the trace lines54. In one example, the integrated circuit die88can be adjacent to and electrically coupled to the second trace line54a. In another example, the integrated circuit die88can be adjacent to and electrically coupled to the third trace line54d. In some embodiments, the integrated circuit die88can be connected to at least one of the second trace line54aor the third trace line54dwith a connective material94. In one example, the connective material94includes a bond wire which can extend from the contact pad96of the integrated circuit die88to the contact pad102within the solder mask opening218, the contact pad102being in electrical communication with the trace lines54.

In one embodiment, the integrated circuit die88can be connected to at least one of the second trace line54aor the third trace line54dwith a connective material94. In some embodiments, the connective material94can be an interconnect structure such as a metal line or solder bump. The connectivity allows the integrated circuit die88to be in communication with at least one of the second trace line54aor the third trace line54d. More specifically, the connectivity allows the integrated circuit die88to be in communication with both trace lines54a,54deven though the integrated circuit die88is only directly connected to one of the trace lines54a,54d. In other words, if the integrated circuit die88is mounted over the substrate90adjacent to and connected to the second trace line54awith a connective material94or an interconnect structure94, the conductive jumper trace or conductive layer180allows the integrated circuit die88to also be in communication with the third trace line54d. The additional connectivity is provided by the conductive layer180which jumps over the trace lines54b,54cwithout shorting all trace lines54. In the alternative, if the integrated circuit die88is mounted over the substrate90adjacent to and connected to the third trace line54dwith a connective material94or an interconnect structure94, the conductive jumper trace or conductive layer180allows the integrated circuit die88to also be in communication with the second trace line54a.

Although the mounting and connecting of the integrated circuit die88are discussed toward the end of the processes inFIGS. 10A-10B, the mounting and connecting of the integrated circuit die88can be performed earlier in the processing steps. In one example, the mounting and connecting of the integrated circuit die88can take place after the forming of trace lines54inFIGS. 7A-7B. In another example, the mounting and connecting of the integrated circuit die88can take place before the forming of the covering layer136inFIGS. 8A-8B. In some embodiments, the covering layer136may also cover portions of the integrated circuit die88, if such integrated circuit die88was mounted over the substrate106before the formation of the covering layer136. In yet another embodiment, the mounting and connecting of the integrated circuit die88can take place at the same time as the forming of trace lines54inFIGS. 7A-7B. In other words, the integrated circuit die88can be optionally mounted over the substrate106before the trace lines54are formed, or the integrated circuit die88can be connected to the trace lines54at the same time as the trace lines54are formed or shortly thereafter.

FIGS. 11A-11B to 12A-12Bare top-down and cross-sectional views of a process flow for forming a semiconductor package700having a conductive jumper trace according to one embodiment of the present disclosure.FIGS. 11A-11Bare continued from those ofFIGS. 10A-10BwhereFIG. 11Ais a top-down view whileFIG. 11Bis a cross-sectional view through A-A ofFIG. 11A.

As shown in the cross-sectional view ofFIG. 11B, trace lines54formed over the substrate90can be isolated with a covering layer136. Specifically, the two inner trace lines54b,54ccan be isolated with a first covering layer136. Although shown to include two trace lines54b,54c, it is understood that the first covering layer136need only isolate or insulate one trace line (54bor54c). Next, a first conductive layer180can be formed over the first covering layer136as shown and discussed above and in the earlier figures.

In general, formation of the first conductive layer180over the first covering layer136includes depositing the conductive material180, optionally allowing the conductive material180to disperse from an initial area to a final area, where the final area is greater than the initial area, and heating or curing the conductive material into a solid form. In the alternative, if screen printing or EHD dispensing is utilized, the conductive liquid or paste may be deposited having a first material state, where the first material state includes liquid, viscous or paste form. The conductive liquid or paste need not go through the dispersion or spreading process but instead can be heated from the first material state to a second material state, where the second material state is different from the first material state. The second material state may include solid, crystal or sintered form. In some embodiments, the first state may have an initial profile while the second state may have a final profile where the final profile is different from the initial profile. The difference in the profile may be a result of the heating or curing process which may drive out the fluid or viscous material in the liquid or paste causing the conductive material to undergo shrinkage into a more solid or sintered form.

The conductive ink, paste or liquid used in the formation of the conductive material180may include silver (Ag) complexes, platinum (Pt) complexes, gold (Au) complexes, copper (Cu) complexes, carbon nanotube (CNT), graphene, organic metal, or additives and mixtures thereof. The conductive ink, paste or liquid may also be an organic polymer with metallic properties. In some embodiments, the covering layer136may be treated with hydrophilic plasma prior to deposition of the conductive material180to enhance the dispersing process, as necessary.

Next, a portion of the first conductive layer180can be isolated with a second covering layer236, the second covering layer236being formed in a similar manner with similar material as that of the first covering layer136, and other insulating or protective material described above. Although the second covering layer236as shown is substantially over the first covering layer136and more specifically limited to that of the fourth trace line54c, it is understood that the second covering layer236can take on any shape or size as necessary to isolate or prevent shorting of the first conductive layer180to any portions of the trace lines54not meant to be electrically connected thereto.

FIGS. 12A-12Bare top-down and cross-sectional views of a semiconductor package700having two conductive layers or dual conductive jumper traces according to one embodiment of the present disclosure.FIGS. 12A-12Bare continued from those ofFIGS. 11A-11BwhereFIG. 12Ais a top-down view whileFIG. 12Bis a cross-sectional view through A-A ofFIG. 12A. After the second covering layer236has been formed over and isolating a portion of the first conductive layer180, a second conductive layer280may subsequently be formed over the second covering layer236. The second conductive layer280may be formed with similar manner/material as that of the first conductive layer180, or with other conductive materials as described above. During the formation process of the second conductive layer280, terminal openings260A,260B may be formed on trace lines54to limit or provide a relief region for the second conductive material280to accumulate similar to that described above for the terminal openings160A,160B. In some instances, the terminal openings160,260may also be referred to as via openings or recesses or trench formations.

In one embodiment, the second conductive layer280can be formed by depositing the second conductive layer280, optionally dispersing the second conductive layer280, and heating the second conductive layer280. Once formed, the second conductive layer280can conform to the second covering layer236similar to that of the first conductive layer180conforming to the first covering layer136. In this instance, the second conductive layer280is able to provide electrical connection between the first trace line54band a fifth trace line54e. Although electrical connection is shown to be made to the fifth trace line54eby the second conductive layer280, the second conductive layer280can also provide electrical connection to any isolated portions of the other trace lines54a,54b,54c,54dso long as electrical connection is desired. In other words, although the second conductive layer280as shown connects the fifth trace line54eto the first trace line54b, the second conductive layer280can also connect the fifth trace line54eto either the second trace line54bor the third trace line54cor both trace lines54b,54cas necessary. In some embodiments, the second conductive layer280need not connect the first trace line54band the fifth trace line54ebut instead can connect the first trace line54bto the second trace line54aor the third trace line54dor the fourth trace line54cor any combinations thereof.

In some embodiments, the second conductive layer280can connect the fifth trace line54eto three trace lines54b,54a,54d. In other embodiments, the second conductive layer280can make a variety of electrical connections as necessary and desired, and that such connections can take place between two trace lines or among three or more trace lines as necessary. In these instances, the trace lines54need not be continuous (e.g., fifth trace line54eand the third trace line54dappear to be aligned with a break in between). The same behavior or connection trend may also go for that of the first conductive layer180. Furthermore, the covering layers136,236can come in a variety of sizes and shapes and need not be circular or spherical as shown in the figures as long as it is capable of covering or protecting a portion or all of the trace lines54to prevent undesired shorting.

FIG. 13is a top-down view of a prior art semiconductor package300having conductive jumper traces known in the art. In this package300, the integrated circuit die88can be mounted about a center of the package300with a plurality of cross-wire bonds380serving as the conductive jumper traces. As discussed herein, such wire bonds380may require extensive length of wire bonds leading to added cost as well as slow throughput due to having to form each wire bond380individually for making the conductive jumper trace. Furthermore, bond wire reliability can also become a concern as bond lengths increase and the number of bond wires increase.

FIG. 14is a top-down view of a semiconductor package800having conductive jumper traces according to one embodiment of the present disclosure. In one embodiment, the integrated circuit die88can be mounted about a center of the package800. However, in this instance, cross-wire bonds380can be eliminated with the use of dual conductive jumper traces according to the semiconductor package700shown inFIGS. 12A-12B. Furthermore, single conductive jumper traces according to the semiconductor packages600shown inFIGS. 10A-10Bcan also be utilized resulting in a semiconductor package800having mostly straight-forward (e.g., no crossing over or jumping over) and short wire bonds380. The result is that wire bonds380need not cross over nor do they need to function as jumper traces extending a long distance or travel path. The currently disclosed embodiments can achieve cost savings as well as increased reliability and throughput of the semiconductor packaging processes.

FIG. 15is a flow diagram900of the methods of forming conductive jumper traces in semiconductor devices and packages. In one embodiment, a method of forming conductive jumper traces for semiconductor packages includes providing a substrate as indicated in step902. Next, a plurality of trace lines can be formed over the substrate including forming first, second and third trace lines, where the first trace line is between the second trace line and the third trace line in step904. In some embodiments, four or more trace lines can be formed in step904. Next, a first trace line can be isolated with a covering layer in step906. Electrical connection can be made between the second trace line and the third trace line by forming a conductive layer (e.g., jumper trace) in step908. The conductive layer can be formed by depositing the conductive layer (910), where the conductive layer includes at least one of silver (Ag), platinum (Pt), gold (Au), copper (Cu), carbon nanotube (CNT), graphene, organic metal, or mixtures thereof. Optionally, the conductive layer can disperse or be allowed to disperse or spread such that the conductive layer conforms to the covering layer (912). In one embodiment, to enhance the dispersion step, the trace lines may be treated with hydrophilic plasma916prior to the depositing and dispersing steps910,912. Last but not least, the conductive layer can be heated or cured in a heating step (914) to solidify the conductive layer thus allowing the conductive layer to provide electrical connection between the second trace line and the third trace line.

In one embodiment, the depositing step910can be done such that the conductive material is at a first material state. The first material state includes liquid, viscous or paste form, among others. The first material state may also include an initial or first profile. Subsequently, the heating step914can be performed to alter or transform the conductive material from the first material state to a second material state, where the second material state is different from the first material state. The second material state includes solid, crystal or sintered form, among others. The second material state may also include a final or second profile, the final or second profile being different from the initial or first profile. This may be as a result of the heating step914which may cause shrinkage of the conductive ink, droplet, liquid or paste. Regardless, the conductive material can be formed without a lithographic process involving the coating and removal of a photoresist material. Furthermore, the conductive material can be formed without the use of a traditional metallization process in which the material is deposited and formed as is.

In one embodiment, during the forming trace lines step904, a fourth trace line can be formed over the substrate, the fourth trace line being adjacent the first trace line. This fourth trace line can also be between the second trace line and the third trace line. Similarly, during the isolating covering layer step906, the fourth trace line can also be isolated by the covering layer.

In one embodiment, after the forming trace lines step904, an integrated circuit die can be mounted over the substrate in step918. The integrated circuit die can be amounted adjacent to either the second trace line or the third trace line. Subsequently, the integrated circuit die can be coupled to either the second trace line or the third trace line with a connective material in step920. For example, if the integrated circuit die is adjacent the second trace line, the integrated circuit die can be electrically coupled or connected to the second trace line with a bond wire or a suitable interconnect structure (e.g., metal line, solder bump). In the alternative, if the integrated circuit die is adjacent the third trace line, the integrated circuit die can be electrically coupled or connected to the third trace line with a bond wire or a suitable electrical interconnect structure. Because of the conductive jumper trace or conductive layer, by connecting the integrated circuit die to only either the second or third trace line will allow the integrated circuit die to be in communication with the other trace line that the integrated circuit die is not directly connected to. In other words, if the integrated circuit die is adjacent to and connected to the second trace line with an interconnect structure, the conductive jumper trace or conductive layer will allow the integrated circuit die to be in communication with the third trace line, and vice versa.

In another embodiment, although the mounting and connecting steps918,920are shown to be performed after the forming step904, in some embodiments, the mounting and connecting steps918,920can be performed or carried out at the same time as the forming step904.

In one embodiment, a method of forming conductive jumper traces for semiconductor packages includes providing a substrate as indicated in step902. Next, a plurality of trace lines can be formed over the substrate including forming first, second, third and fourth trace lines, where the first trace line is adjacent the fourth trace line, and where both of these lines are between the second trace line and the third trace line in step904. Next, the first trace line and the fourth trace line can be isolated with a covering layer in step906. Electrical connection can be made between the second trace line and the third trace line by forming a conductive layer (e.g., jumper trace) in between in step908. The conductive layer can be formed by depositing the conductive layer (910), where the conductive layer includes at least one of silver (Ag), platinum (Pt), gold (Au), copper (Cu), carbon nanotube (CNT), graphene, organic metal, or mixtures thereof. Optionally, the conductive layer can disperse or be allowed to disperse or spread such that the conductive layer conforms to the covering layer (912). In one embodiment, to enhance the dispersion step, the trace lines may be treated with hydrophilic plasma916prior to the depositing and dispersing steps910,912. Last but not least, the conductive layer can be heated or cured in a heating step (914) to solidify the conductive layer thus allowing the conductive layer to provide electrical connection between the second trace line and the third trace line.

In some embodiments, the conductive material or layer can be formed over the covering layer in step908, the formation steps include: depositing the conductive material (910), optionally dispersing or allowing the conductive material to disperse from an initial area to a final area, where the final area is greater than the initial area (912), and heating of the conductive material (914).

Like above, in another embodiment, after the forming trace lines step904, an integrated circuit die can be mounted over the substrate in step918. The integrated circuit die can be amounted adjacent to either the second trace line or the third trace line. Subsequently, the integrated circuit die can be coupled to either the second trace line or the third trace line with a connective material in step920. Because of the conductive jumper trace or conductive layer, by connecting the integrated circuit die to only either the second or third trace line will allow the integrated circuit die to be in communication with the other trace line that the integrated circuit die is not directly connected to. And like above, although the mounting and connecting steps918,920are shown to be performed after the forming step904, in some embodiments, the mounting and connecting steps918,920can be performed or carried out at the same time as the forming step904.

In one embodiment, a method of forming conductive jumper traces for semiconductor packages includes providing a substrate as indicated in step902. Next, a plurality of trace lines can be formed over the substrate including forming first, second and third trace lines, where the first trace line is between the second trace line and the third trace line in step904. Next, the first trace line can be isolated with a first covering layer in step906. Electrical connection can be made between the second trace line and the third trace line by forming a first conductive layer (e.g., jumper trace) in between in step908. The first conductive layer can be formed by depositing the first conductive layer (910), where the first conductive layer includes at least one of silver (Ag), platinum (Pt), gold (Au), copper (Cu), carbon nanotube (CNT), graphene, organic metal, or mixtures thereof. Optionally, the first conductive layer can disperse or be allowed to disperse or spread such that the first conductive layer conforms to the first covering layer (912). In one embodiment, to enhance the dispersion step, the trace lines can be treated with hydrophilic plasma916prior to the depositing and dispersing steps910,912. Last but not least, the first conductive layer can be heated or cured in a heating step (914) to solidify the first conductive layer thus allowing the first conductive layer to provide electrical connection between the second trace line and the third trace line.

In one embodiment, a portion of the first conductive layer can be isolated with a second covering layer in step1006. The second covering layer can be formed of the same or similar material and in the same or similar manner as that of the first covering layer in step906. After isolating a portion of the first conductive layer with a second covering layer in step1006, a second conductive layer can be formed over the second covering layer in step1008. The second conductive layer can be formed of the same or similar material and in the same or similar manner as that of the first conductive layer in step908. For instance, the second conductive layer can be formed by depositing the second conductive layer (1010), where the second conductive layer includes at least one of silver (Ag), platinum (Pt), gold (Au), copper (Cu), carbon nanotube (CNT), graphene, organic metal, or mixtures thereof. Optionally, the second conductive layer can disperse or be allowed to disperse or spread such that the second conductive layer conforms to the second covering layer (1012). In one embodiment, to enhance the dispersion step, the second covering layer can be treated with hydrophilic plasma1016prior to the depositing and dispersing steps1010,1012. Last but not least, the second conductive layer can be heated or cured in a heating step (1014) to solidify the second conductive layer.

In one embodiment, the second conductive layer or material can be deposited over the second covering layer such that the second conductive layer is deposited as at a third material state during the depositing step1010. The third material state may be similar to that of the first state to include liquid, viscous or paste form, among others. The third material state may also include a third profile, which can be substantially similar to that of the first or initial profile. Next, the second conductive layer can be heated at the heating step1014bypassing the dispersing step1012to transform the second conductive layer from the third material state to a fourth material state, where the fourth material state is different from the third material state. The fourth material state may be similar to that of the second material state to include solid, crystal or sintered form, among others. The fourth material state may also include a fourth profile, the fourth profile being different from the third profile but may be substantially similar to that of the final or second profile. Like with the first conductive layer, the second conductive layer can be formed without a lithographic process involving the coating and removal of a photoresist material. Furthermore, the second conductive layer can be formed without the use of a traditional metallization process in which the material is deposited and formed as is.

In one embodiment, the method includes forming a fourth trace line over the substrate and connecting the second conductive layer to the fourth trace line and at least one of the first trace line, the second trace line and the third trace line. In another embodiment, during the forming trace lines step904, a fourth trace line can be formed over the substrate, the fourth trace line being adjacent the first trace line. This fourth trace line can also be between the second trace line and the third trace line. Similarly, during the isolating covering layer step906, the fourth trace line can also be isolated by the covering layer.

Like above, in another embodiment, after the forming trace lines step904, an integrated circuit die can be mounted over the substrate in step918. The integrated circuit die can be amounted adjacent to either the second trace line or the third trace line. Subsequently, the integrated circuit die can be coupled to either the second trace line or the third trace line with a connective material in step920. Because of the conductive jumper trace or conductive layer, by connecting the integrated circuit die to only either the second or third trace line will allow the integrated circuit die to be in communication with the other trace line that the integrated circuit die is not directly connected to. And like above, although the mounting and connecting steps918,920are shown to be performed after the forming step904, in some embodiments, the mounting and connecting steps918,920can be performed or carried out at the same time as the forming step904.

The currently disclosed embodiments are able to produce higher processing throughput by reducing the number of processing steps. In addition, wire bonding processes can be reduced or eliminated and cost savings can also be achieved as the amount of bond wires used can also be cut back. These embodiments may eliminate the use of cross-wires with insulations or coatings, especially in instances where long crossing wires may be required. Furthermore, yields of bond wires will improve as the bond wires can be made shorter and bond wire layouts can be simplified by removing long and/or crossed wires similar to that shown inFIG. 14. In some instances, the substrate pattern or design may also be relaxed. Furthermore, although one conductive jumper trace and two conductive jumper traces are shown, it is understood that there can be more conductive jumper traces as necessary without compromising the topography of the package.

Although the current description has been described in detail with reference to several embodiments, additional variations and modifications exist within the scope and spirit of the disclosure.