METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

A method of fabricating a semiconductor package is provided, including providing a carrier provided having a circuit layer and a blocking member, forming on the carrier an encapsulating layer having a first surface and a second surface opposing the first surface and encapsulating the circuit layer and the blocking member, with the first surface coupled with the carrier, and removing the carrier and the blocking member to form in the encapsulating layer via the first surface thereof an opening for an electronic component to be received therein. Before the electronic component is disposed in the opening, the circuit layer and the electronic component can be tested in advance, in order to retire the defectives. Therefore, as a defective electronic component is prevented from being disposed in the opening, no defective semiconductor package will be fabricated.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to packaging processes, and, more particularly, to a semiconductor package and a method of fabricating the same.

2. Description of Related Art

As the semiconductor industry advances, the demand for electronic products with light weight, low-profile, high integration and high functionality increases. Apart from a ball grid array (BGA) being developed to accommodate the needs for high integration and miniaturization, a flip chip (FC) package has been developed. A chip having an integrated circuit is directly embedded in a packaging substrate, to eliminate the use of wire bonding. As a result, such a package can have its overall size greatly reduced and electrical functionality increased.

As shown inFIG. 1, a conventional embedded semiconductor package1is shown, which comprises: a core layer10having opposing first and second surfaces10aand10band an opening100penetrating the first and second surfaces10aand10b, a chip11accommodated in the opening100, a circuit build-up structure13formed on the first and second surfaces10aand10bof the core layer10and on the chip11, and a solder mask layer16formed on the circuit build-up structure13.

The chip11has an active surface11aand a non-active surface11b. A plurality of electrode pads110are formed on the active surface11a. The opening100is filled by an adhesive material12, so as to position the chip11in the opening100.

The circuit build-up structure13has at least one dielectric layer130, a circuit layer131formed on the dielectric layer130, and a plurality of conductive vias132formed in the dielectric layer130and electrically connected with the electrode pads100and the circuit layer131.

The solder mask layer16has a plurality of openings160, allowing a portion of a surface of the circuit layer131to be exposed therefrom and function as conductive pads that can be electrically connected with electronic devices.

However, the conventional semiconductor package1, since having the core layer10, has its overall structure increased in thickness, thereby making it difficult to conform the low-profile requirement.

In addition, in the method of fabricating a conventional semiconductor package1, the chip11must be embedded before making the circuit buildup structure13, which is then followed by a test. Therefore, when the semiconductor package1is found to be defective, regardless which of the chip11, the circuit build-up structure13or the core layer10is defective, the whole semiconductor package1is abandoned. This undesirably causes wastage of materials and also increases the production cost.

Moreover, the chip11is electrically connected to external electronic components through the circuit layer131, leading to prolonged signal pathway and reduced electrical functionality of the semiconductor package1.

Therefore, there is an urgent need to solve the foregoing problems.

SUMMARY OF THE INVENTION

In order to achieve the foregoing objectives, the present invention provides a semiconductor package, comprising: an encapsulating layer, having a first surface, a second surface opposing the first surface, and at least one opening formed via the first surface of the encapsulating layer; a circuit layer formed and embedded in the encapsulating layer via the first surface of the encapsulating layer; and at least one electronic component disposed in the opening and being exposed from the first surface.

In an embodiment, the opening is not in communication with the second surface.

In an embodiment, the electronic component is not exposed from the second surface.

The present invention further provides a method of fabricating a semiconductor package, comprising: providing a carrier having a circuit layer; forming at least one blocking member on the carrier; forming on the carrier an encapsulating layer that has a first surface coupled to the carrier and a second surface opposing the first surface, and encapsulates the circuit layer and the blocking member; removing the carrier and the blocking member, allowing an opening to be formed in the encapsulating via the first surface thereof layer; and disposing at least one electronic component in the opening.

In an embodiment, the blocking member is formed by electro-plating or printing method.

In an embodiment, the encapsulating layer is formed by molding or lamination. The encapsulating layer is made of a molding compound, a dielectric layer or an optic insulative material.

In an embodiment, the method further comprises forming on the second surface of the encapsulating layer a circuit structure that is electrically connected with the circuit layer. In an embodiment, the method further comprises forming an insulative protecting layer on the second surface of the encapsulating layer such that a portion of the circuit structure is exposed from the insulative protecting layer. In an embodiment, the circuit structure has a plurality of conductive pillars formed in the encapsulating layer and electrically connecting the circuit structure to the circuit layer. The conductive pillars are formed by forming a plurality of through holes in the encapsulating layer via the second surface thereof by mechanical drilling or exposure and development methods, and filling the through holes with the conductive materials.

In an embodiment, the method further comprises forming an insulative protecting layer on the first surface of the encapsulating layer, allowing a portion of the circuit layer to be exposed from the insulative protecting layer.

In an embodiment, the method further comprises disposing on the first surface of the encapsulating layer a stacking member that is electrically connected with the circuit layer or electronic devices.

In an embodiment, the method further comprises disposing a stacking member on the second surface of the encapsulating layer.

In an embodiment, the method further comprises forming a redistribution structure on the first surface of the encapsulating layer and the circuit layer or on the second surface.

Accordingly, the semiconductor package and the method of fabricating the same according to present invention eliminate the use of a conventional core layer. Therefore, the semiconductor package has a reduced overall thickness and a reduced overall cost.

In addition, through forming a blocking member in the encapsulating layer, which is then removed to form an opening, the circuit layer and the electronic component can be individually tested to discard the defectives in advance of placing the electronic component, so as to prevent the material wastage problem that the entire semiconductor package is always abandoned if being defecture.

Moreover, the electronic component can be directly electrically connected with the stacking member without the need of a circuit layer, hence the signal pathway can be reduced and the electrical functionality can be enhanced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention is described in the following with specific embodiments, so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention from the disclosure of the present invention.

It should be noted that all the drawings are not intended to limit the present invention. Various modification and variations can be made without departing from the spirit of the present invention. Further, terms, such as “upper”, “left”, “right”, “first”, “second” and “one” etc., are merely for illustrative purpose and should not be construed to limit the scope of the present invention.

FIGS. 2A to 2Gare cross-sectional views showing a method of fabricating a coreless semiconductor package2according to the present invention.

As shown inFIG. 2A, a carrier29having an attaching layer290is provided, and a circuit layer23is formed on the attaching layer290of the carrier29.

In an embodiment, the carrier29is a metal board, a semiconductor wafer, or a glass board, and the attaching layer290is a release film, an adhesive material, an insulating material, or a composite material such as a foil having a seed layer.

In an embodiment, the carrier29is defined with a placement area A, and the circuit layer23is formed outside the placement area A.

In an embodiment, the circuit layer23comprises a plurality of conductive traces231and a plurality of conductive pads230, and the circuit layer23can be formed by, but not limited to, an electro-plating method or other methods.

As shown inFIG. 2B, a blocking member28is formed on the attaching layer290within the placement area A of the carrier29.

In an embodiment, the blocking member28is formed by an electro-plating method, or by a screen printing method and made of polymers.

As shown inFIG. 2C, an encapsulating layer20is formed on the attaching layer290to encapsulate the circuit layer23and the blocking member28, and the circuit layer23is embedded in the encapsulating layer20.

In an embodiment, the encapsulating layer20has a first surface20aand a second surface20bopposing the first surface20a, and the first surface20ais attached to the attaching layer290.

In an embodiment, the encapsulating layer20is formed by a molding or lamination process, and the encapsulating layer20is made of, but not limited to, a molding compound, a dielectric material or a photo-imageable dielectric material.

A conductive layer24is formed on the second surface20bof the encapsulating layer20for a subsequent process of forming the circuit to be performed. In an embodiment, the conductive layer24such as a copper coil is pressed on the second surface20bof the encapsulating layer20, and then the conductive layer24and the encapsulating layer20are combined to be coupled onto the attaching layer290. Alternatively, after the encapsulating layer20is pressed onto the attaching layer290, the conductive layer24is formed on the encapsulating layer20.

In another embodiment, the conductive layer24is formed on the second surface20bof the encapsulating layer20by a sputtering process.

As shown inFIG. 2D, through the conductive layer24, a circuit structure25is formed on the second surface20bof the encapsulating layer20by an electro-plating process, and the circuit structure25has conductive pillars250formed in the encapsulating layer20and electrically connected with the conductive pads230of the circuit layer23. In an embodiment, the conductive pillars250are formed by forming through holes in the encapsulating layer20via the second surface20bthereof by a laser process, and filling the through holes with a conductive material, or using a photo-imageable dielectric material to make the encapsulating layer20and through exposure and development processes to form the conductive material in the through holes.

As shown inFIG. 2E, the excessive portion of the conductive layer24, along with the carrier29, the attaching layer290and the blocking member28are removed, allowing an opening200to be formed in the encapsulating layer20via the first surface20acorresponding in position to the placement area A.

In an embodiment, a portion of the circuit structure25outside of the conductive traces layer24is removed, i.e., the remaining portion of the circuit structure25under the conductive traces layer24is retained.

As shown inFIG. 2F, an insulative protecting layer26such as a solder mask layer is formed on first and second surfaces20aand20bof the encapsulating layer20. The insulative protecting layer26has a plurality of openings260, allowing a portion of a surface of the conductive pads230and the circuit structure25(acting as conductive pads251) to be exposed therefrom, for connecting with external electronic devices.

As shown inFIG. 2G, at least one electronic component21is disposed in the opening200, and the opening200is filled with an adhesive material22, such that the electronic component21is held in position in the opening200.

In an embodiment, the electronic component21can be an active component, a passive component, or a combination thereof. The active component can be a semiconductor chip, and the passive component can be a resistor, a capacitor and an inductor. In an embodiment, the electronic component21is a passive component, and has electrodes210formed on the left and right sides thereof.

In an embodiment, the electronic component21is electrically connected to the circuit layer23via a wire bonding method.

In the latter processes, as shown inFIG. 3, the circuit layer23(i.e., the conductive pads230) and the electrodes210of the electronic component21can be coupled to a stacking member30via a plurality of conductive elements27, such as a solder material or a copper pillar, to form a stacked packaging unit3.

In an embodiment, the stacking member30is a semiconductor chip, a chip wafer, an interposer or a package.

In other embodiments, other electronic devices can be coupled to the second surface20bof the encapsulating layer20and the circuit structure25.

As shown inFIG. 4, after the excessive portion of conductive layer24is removed, a redistribution structure40is formed on the second surface20bof the encapsulating layer20by a redistribution layer (RDL) process. The redistribution structure40is electrically connected with the circuit structure25. Subsequently, an insulative protecting layer26is formed on the redistribution structure40, with a portion of a surface of the redistribution structure40being exposed, for other external components to be coupled thereto in subsequent processes.

Alternatively, as shown inFIG. 5, after the carrier29, the attaching layer290and the blocking member28are removed, a redistribution layer (RDL) process is performed to form a redistribution structure50on the first surface20aof the encapsulating layer20, and after the redistribution structure50is electrically connected with the circuit layer23, the insulative protecting layer26is formed on the redistribution structure50, with a portion of a surface of the redistribution structure50being exposed, for other external components to be coupled thereto in subsequent processes. In an embodiment, the redistribution structure50does not cover the opening200, allowing the electronic component21to be placed in subsequent processes.

In an embodiment, the redistribution structures40and50have, respectively, at least one circuit part401,405and at least one dielectric layer400,500, which are interstacked with the circuit part401,405. The dielectric layer400,500is formed on the encapsulating layer20, and the circuit par401,501is used for electrical connection.

The semiconductor package2according the present invention does not have a core layer, such that the thickness of the overall structure, as well as the cost can be reduced.

Moreover, in the method of fabricating the semiconductor package according to present invention, a space is reserved for the electronic component21to be accommodated therein. That is, an opening200for accommodating the electronic component21is formed after a blocking member28formed in the encapsulating layer20is removed. Before the electronic component21is accommodated in the opening200, the circuit layer23(or the circuit structure25) and the electronic component21can be individually tested in advance to discard the defectives, such that the material wastage problem due to that the entire semiconductor package2needs to be discarded whenever a defective semiconductor package2is found can be prevented, thereby saving the overall cost.

Further, the electronic component21and the stacking member30can be directly electrically connected, without the need of a circuit layer23, such that the signal pathway of the stacked package unit3is reduced, and the electrical functionality of the stacked package unit3is increased.

The present invention further provides a semiconductor package2, comprising: an encapsulating layer20, a circuit layer23, and at least one electronic component21.

The encapsulating layer20has a first surface20a, a second surface20bopposing the first surface20a, and at least one opening200formed in the encapsulating layer20via the first surface20athereof. In an embodiment, the opening200is free from being connected to the second surface20b. In an embodiment, the encapsulating layer20is made of a molding compound, a dielectric material or a photo-imageable dielectric material.

The circuit layer23is formed and embedded in the encapsulating layer20via the first surface20aof the encapsulating layer20.

The electronic component21is disposed in the opening200, and exposed from the first surface20a, but not the second surface20b. The electronic component21is an active component, a passive component, or a combination thereof.

In an embodiment, the semiconductor package2further comprises a circuit structure25formed in the second surface20bof the encapsulating layer20and electrically connected with the circuit layer23. In another embodiment, the semiconductor package2further comprises an insulative protecting layer26formed on the second surface20bof the encapsulating layer20, with a portion of a surface of the circuit structure25being exposed.

In an embodiment, the semiconductor package2further comprises an insulative protecting layer26, formed in the first surface20aof the encapsulating layer20, with a portion of a surface of the circuit layer23being exposed.

In an embodiment, the semiconductor package2further comprises a plurality of conductive elements27disposed on a portion of a surface of the circuit layer23.

In an embodiment, the semiconductor package2further comprises a plurality of conductive elements27disposed on the electronic component21.

In an embodiment, a stacking member30is disposed on the first surface20aof the encapsulating layer20, and electrically connected to the circuit layer23or the electronic component21.

In an embodiment, a stacking member30is disposed on the second surface20bof the encapsulating layer20, and electrically connected to the circuit structure25.

In an embodiment, the semiconductor package4further comprises a redistribution structure40formed on the second surface20bof the encapsulating layer20.

In an embodiment, the semiconductor package5further comprises a redistribution structure50formed on the first surface20aof the encapsulating layer20.

In summary, the semiconductor package and the method of fabricating the same according to the present invention involve using a coreless design to reduce the thickness of the overall structure of the package, so as to reach the objective of low-profile and reduced cost.

Before the electronic components is placed in the predetermined space, the circuit layer and the electronic component can be individually tested, to discard the defectives, so as to prevent the entire semiconductor package being abandoned, causing wastage of materials.

Moreover, disposing the electronic component after disposing wires allows the electronic component to be directly electrically connected to the stacking member, without a need of a circuit layer. Hence, the signal pathway can be reduced so as to increase the electrical functionality.