Input buffer and semiconductor device including the same

An input buffer includes a control circuit that generates first control signals depending on a signal type of at least one input signal. The input buffer also includes a receiver that generates at least one output signal of a predetermined signal type from the at least one input signal and the first control signals. Thus, for a semiconductor device using a plurality of such input buffers, interface circuits of application circuits communicating with the semiconductor device are eliminated, thereby minimizing power consumption and layout area.

BACKGROUND OF THE INVENTION

This application claims priority to Korean Patent Application No. 2003-0094264, filed on Dec. 20, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

1. Field of the Invention

The present invention relates generally to input buffers, more particularly, to an input buffer generating an output signal of a predetermined signal type regardless of the signal type of at least one input signal.

2. Description of the Related Art

FIG. 1shows a system100including a conventional multi-port/multi-media semiconductor device150and a circuit block110. The circuit block110includes a plurality of application circuits such as an audio input circuit111, a video input circuit115, a digital media processing circuit119, an audio output circuit127, and a video output circuit131. Such circuits111,115,119,127, and121may be implemented as separate semiconductor chips.

The audio input circuit111, the video input circuit115, the digital media processing circuit119, the audio output circuit127, the video output circuit131, and the multi-port/multi-media semiconductor device150each use unique signal levels to exchange data with external devices. A signal level characterizes a signal type defined by a direct current (DC) reference level and a swing width about the DC reference level (hereinafter referred to as “a reference level and a swing width”).

Examples of conventional signal types include a transistor-transistor logic (TTL) level, a complementary metal oxide semiconductor device (CMOS) level, a stub series transceiver logic (SSTL) level, a Rambus signal logic (RSL) level, and a differential Rambus signaling (DRSL) level. As interfacing speed increases, the swing width is reduced.

To input and output data at high speed, the audio input circuit111, the video input circuit115, the digital media processing circuit119, the audio output circuit127, the video output circuit131, and the multi-port/multi-media semiconductor device150include input/output (I/O) interfaces113,117,121,123, and125, respectively. Each of the I/O interfaces113,117,121,123, and125converts a signal level of an input signal to a signal level processed by the corresponding application circuit. Each of the I/O interfaces113,117,121,123, and125may be implemented as separate chips.

For example, assume that a signal level (or a signal system) of a signal output from the video input circuit115(processing a video signal Vin) is different from that used in the semiconductor device150. In that case, the I/O interface117which is a transmitting circuit of the video input circuit115converts the signal level and the amplitude of the signal from the video input circuit. The converted signal is transmitted to the semiconductor device150via a channel. Then, an input buffer151of the semiconductor device150converts the signal level and amplitude of the signal input via the channel into those processed by the semiconductor device150.

Similarly, the I/O interface113of the audio input circuit111(processing an audio signal Ain) converts the level and the amplitude of a signal from the audio input circuit111. The I/O interface113of the audio input circuit111transmits such a converted signal to the input buffer151of the semiconductor device150.

The digital media processing circuit119exchanges signals with the semiconductor device150via the I/O interfaces121,123, and125, which are transmitting/receiving circuits. Each of the I/O interfaces121,123, and125converts the level and the amplitude of input and output signals.

The audio output circuit127and the video output circuit131process signals from an output buffer157of the semiconductor device150. The audio output circuit127and the video output circuit131also output an audio output signal Aout and a video output signal Vout, respectively.

In this manner in the prior art, the application circuits111,115,119,127, and131and the semiconductor device150using different signal levels require additional chips,113,117,121,123,125,151,153,155, and157for interfacing with each-other to exchange signals at high speed. As the number of application circuits exchanging signals with the multi-port/multi-media semiconductor device150increases, the number of interfacing chips converting different signal levels also increases, resulting in an increase in the cost of the entire system.

Thus, a mechanism is desired for decreasing the number of interfacing chips during signal exchange between application circuits and the semiconductor device150.

SUMMARY OF THE INVENTION

Accordingly, an input buffer of the present invention generates an output signal of a predetermined signal type (such as of the CMOS swing type) regardless of the signal type of an input signal.

In an aspect of the present invention, such an input buffer includes a control circuit that generates first control signals depending on a signal type of at least one input signal. In one example embodiment of the present invention, the signal type of the at least one input signal indicates a reference level and a swing width of the at least one input signal. The input buffer also includes a receiver that generates at least one output signal of a predetermined signal type from the at least one input signal and the first control signals.

In another aspect of the present invention, the input buffer also includes a program circuit for generating second control signals indicating the signal type of the at least one input signal. In that case, the control circuit receives the second control signals to generate the first control signals from the second control signals.

In one example embodiment of the present invention, the program circuit includes a plurality of fuses. Each fuse is cut or not cut when programming the signal type of the at least one input signal into the program circuit.

In another embodiment of the present invention, the program circuit includes at least one register for generating and storing the second control signals from a MRS (mode register set) signal when programming the signal type of the at least one input signal into the program circuit.

In yet another embodiment of the present invention, the receiver includes a plurality of current sources. Each of the current sources is turned on or off depending on the first controls signals, for generating the output signal of the predetermined signal type.

In one example embodiment of the present invention, the predetermined signal type of the output signal is of a CMOS swing type.

In a further embodiment of the present invention, the control circuit includes a bias voltage generator that generates bias voltages and a driver that generates the first control signals from the bias voltages and the second control signals generated by the program circuit.

In another embodiment of the present invention, an input buffer includes a control circuit that generates control signals indicating a first common voltage of input signals. In addition, the input buffer includes a receiver for generating an output signal of a second common voltage from the input signals and the control signals.

In one example embodiment of the present invention, the receiver includes a differential amplifier that generates the output signal from the input signals and the control signals. The receiver also includes a first group of current sources coupled between a first voltage source and a first terminal of the differential amplifier. Each of the first group of current sources is turned off or on to source current to the first terminal, depending on the control signals. Additionally, the receiver includes a second group of current sources coupled between a second voltage source and a second terminal of the different amplifier. Each of the second group of current sources is turned off or on to sink current from the second terminal, depending on the control signals.

In this manner, the input buffer generates an output signal of a predetermined signal type (such as the CMOS swing type) regardless of the signal type of the input signals. Thus, for a semiconductor device using a plurality of such input buffers, interface circuits of application circuits communicating with the semiconductor device are eliminated, thereby minimizing power consumption and layout area.

The figures referred to herein are drawn for clarity of illustration and are not necessarily drawn to scale. Elements having the same reference number inFIGS. 1,2,3,4,5,6,7, and8refer to elements having similar structure and/or function.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2shows a system200including a multi-port/multi-media semiconductor device230according to an embodiment of the present invention. Referring toFIG. 2, the system200includes a circuit block210with application circuits that interface with the multi-port/multi-media semiconductor device230.

The circuit block210includes an audio input circuit211, a video input circuit213, a digital media processing circuit215, an audio output circuit217, and a video output circuit219. In an aspect of the present invention, such application circuits211,213,215,217, and219do not require additional chips (for example, the I/O interfaces113and117illustrated inFIG. 1) to interface with the semiconductor device230.

Each of the audio input circuit211, the video input circuit213, and the digital media processing circuit215generates at least one respective signal. For an example embodiment of the present embodiment, it is assumed that each of the audio input circuit211, the video input circuit213, and the digital media processing circuit215generates respective differential signals INx/INBx (x is a different natural number for each of the application circuits211,213, and215).

For example, the video input circuit213receives and processes a video signal Vin and outputs first differential input signals IN1/INB1to a first input buffer2401of the semiconductor device230. Similarly, the audio input circuit211receives and processes an audio signal Ain and outputs second differential input signals IN2/INB2to a second input buffer2402of the semiconductor device230.

In the example ofFIG. 2, the digital media processing circuit215generates a plurality of pairs of differential input signals including third differential input signals IN3/INB3through mthdifferential input signals INm/INBm, with m being a natural number. The digital media processing circuit215transmits each of the third differential input signals IN3/INB3through the mthdifferential input signals INm/INBm to a respective one of the third through mth,2403, . . . , and240minput buffers of the semiconductor device230. Other signals to be processed by the digital media processing circuit215may be input to the digital media processing circuit215.

In this manner, each of the differential input signals, IN1/INB1, IN2/INB2, IN3/INB3, . . . and INm/INBm is transmitted to a respective one of the inputs buffers2401,2402,2403, . . . and240m.As shown by example in Table 1, the first through mthdifferential input signals, IN1/INB1, IN2/INB2, IN3/INB3, . . . and INm/INBm, are each of a respective signal type having a respective reference level and respective swing width.

TABLE 1Input SignalsDC Reference Level (V)Swing Width based on DC LevelIN1/INB11.65 V±150 mVIN2/INB21.40 V±400 mVIN3/INB30.90 V±600 mVINm/INBm0.15 V±150 mV
For example according to Table 1, the first differential input signals IN1/INB1swing between 1.50V and 1.80V, and the mthdifferential input signals INm/INBm swing between 0V and 0.30V.

The semiconductor device230inFIG. 2includes first through mthinput buffers2401through240mand an output buffer2. Circuits unnecessary for describing the technical features of the present invention are not shown in the drawings.

Each of the input buffers2401,2402,2403, . . . , and240mreceives a respective one of the differential input signals IN1/INB1, IN2/INB2, IN3/INB3, . . . and INm/INBm to generate a respective output signal of a predetermined signal type, such as the signal type with a CMOS swing. In addition, each of the input buffers2401,2402,2403, . . . , and240mreceives respective program control signals. Such program control signals are programmed into each of the input buffers2401,2402,2403, . . . , and240mas will be further described herein.

Each of the mode program circuits3001,3002,3003, . . . , and300mreceives a respective mode program signal indicating a respective signal type of respective input signals input to the respective one of the receivers5001,5002,5003, . . . , and500m.The respective mode program signal indicates the respective DC reference level and the respective swing width for the respective signal type of such respective input signals. Each of the mode program circuits3001,3002,3003, . . . , and300mgenerates respective second control signals REG<0:n−1> and REG<n:2n−1> from the respective mode program signals for the respective one of the input buffers2401,2402,2403, . . . and240m.

In one embodiment of the present invention, the respective mode program signals are programmed into each of the input buffers2401,2402,2403, . . . and240m.Referring to a block diagram inFIG. 7for example, the first mode program circuit3001includes a set of 2n fuse circuits701,702, . . . , and72nthat generates bits REG1[0], REG1[2], . . . , and REG1[2n−1] of the second control signals. Each one of the fuse circuits701,702, . . . , and72nincludes a respective fuse,801,802, . . . , and82nthat is cut or not cut for dictating the logic level of the respective one of the control signal bits REG1[0], REG1[2], . . . , and REG1[2n−1].

Implementation of such fuse circuits are individually known to one of ordinary skill in the art of electronics. In this manner, the respective mode program signals are programmed into the fuses801,802, . . . , and82nthat are each cut or not cut for indicating the signal type of the respective input signals corresponding to the mode program circuit3001. Similarly, each of the other mode program circuits3002,3003, . . . , and300malso includes similar respective fuse circuits with fuses that are each cut or not cut for indicating the signal type of the respective input signals corresponding to each of the mode program circuits3002,3003, . . . , and300m.

Alternatively, referring to a block diagram inFIG. 8for example, the first mode program circuit3001includes a register901for generating and storing the 2n bits of the second control signals REG1<0:2n−1> after such 2n bits are indicated from a MRS (mode register set) signal. The MRS signal may be provided by an external device such as a host system for example. Similarly, each of the other mode program circuits3002,3003, . . . , and300malso includes a similar respective register for generating and storing the respective second control signals from a respective MRS signal.

Each of the mode control circuits4001,4002,4003, . . . , and400mgenerates respective first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb in response to the respective second control signals REG<0:n−1> and REG<n:2n−1> within each input buffer. For example, within each mode control circuit, the respective voltage of each of the respective first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb is determined by the respective second control signals REG<0:n−1> and REG<n:2n−1>.

Each of the receivers5001,5002,5003, . . . , and500mgenerates a respective output signal of the predetermined signal type from the respective differential input signals IN/INB and the respective second control signals REG<0:n−1> and REG<n:2n−1>. In one embodiment of the present invention, the predetermined signal type of the respective output signal for each of the receivers5001,5002,5003, . . . , and500mis of the CMOS swing type.

The signal type of CMOS swing is individually known to one of ordinary skill in the art of electronics. Such a signal type is suitable for processing by the semiconductor device230. Thus, each of the receivers5001,5002,5003, . . . , and500mgenerates a respective output signal with CMOS swing regardless of the signal type of the respective differential input signals IN/INB.

The output buffer2outputs signals processed by the semiconductor device230to the audio output circuit217and the video output circuit219. The audio output circuit217and the video output circuit219process the signals output from the output buffer2and generate an audio output signal Aout and a video output signal Vout, respectively.

FIG. 3shows a block diagram of the first mode control circuit4001ofFIG. 2. Each of the other mode control circuits4002,4003, . . . , and400mis also implemented in a similar manner, in one embodiment of the present invention.

Referring toFIG. 3, the first mode control circuit4001includes a bias voltage generator243and a driver4100. The bias voltage generator243generates a first bias voltage Vppb, a second bias voltage Vnnb, a third bias voltage Vpb, and a fourth bias voltage Vnb. Each of the bias voltages Vppb, Vnnb, Vpb, and Vnb may be different from each-other. For example, the first bias voltage Vppb is 1.2V, the second bias voltage is Vnnb is 0.5V, the third bias voltage Vpb is 1.0V, and the fourth bias voltage Vnb is 0.7V.

FIG. 4shows an example implementation of the driver4100ofFIG. 3which includes a plurality of inverters, in an example embodiment of the present invention. The driver4100receives the first, second, third, and fourth bias voltages Vppb, Vnnb, Vpb, and Vnb from the bias voltage generator243. In addition, the driver4100receives the second control signals REG1<0:2n−1> from the first mode program circuit3001.

The driver4100then generates the first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb from the bias voltages Vppb, Vnnb, Vpb, and Vnb and the second control signals REG1<0:2n−1>.FIG. 4illustrates generation of the first control signals Vppb<0:n−1> and Vnnb<0:n−1> at the output nodes401,403, . . . ,405,411,413, . . . ,415of the plurality of inverters ofFIG. 4. One inverter is used for generating one of the bits of Vppb<0:n−1> and Vnnb<0:n−1> inFIG. 4. The first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb are transmitted to input terminals of the first receiver5001.

Each of the other mode control circuits4002,4003, . . . , and400mmay also be implemented in a similar manner to the first mode control circuit4001ofFIGS. 3 and 4to generate respective first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb from the bias voltages Vppb, Vnnb, Vpb, and Vnb and the respective second control signals REG<0:2n−1> for each of the input buffers2401,2402,2403, . . . , and240m.

FIG. 5is a circuit diagram of the first receiver5001ofFIG. 2. Each of the other receivers5002,5003, . . . , and500mis also implemented in a similar manner, in one embodiment of the present invention.

Referring toFIG. 5, PMOS transistors505,507, and509are connected between a voltage source VDD and a node519. A PMOS transistor502is connected between the voltage source VDD and a node517, and a PMOS transistor511is connected between the voltage source VDD and a node520.

When a β ratio (i.e., a ratio of the channel length to the channel width) of the PMOS transistor505is 1 (X1), the β ratio of the PMOS transistor507is 2(X2), and the β ratio of the PMOS transistor509is 4(X2). Thus, the β ratios of the PMOS transistors505,507, and509increase geometrically in one embodiment of the present invention. However, the β ratio of each of the PMOS transistors505,507and509is not limited thereto for purposes of the present invention.

One of the first control signals (Vppb<0>) is input to a gate of each of the PMOS transistors502,505, and511. Another one of the first control signals (Vppb<1>) is input to a gate of the PMOS transistor507. Another one of the first control signals (Vppb<2>) is input to a gate of the PMOS transistor509.

A PMOS transistor503is connected between the node519and a node537, and one of the differential input signals IN (IN1for the first receiver5001) is input to a gate of the PMOS transistor503. An NMOS transistor523is connected between the node517and a node539, and the same one of the differential input signal IN (IN1for the first receiver5001) is input to a gate of the NMOS transistor523.

A PMOS transistor513is connected between the node519and a node540, and the other of the differential input signals INB (INB1for the first receiver5001) is input to a gate of the PMOS transistor513. An NMOS transistor533is connected between a node520and a node539, and the same one of the differential input signals (INB1for the first receiver5001) is input to a gate of the NMOS transistor533.

A PMOS transistor501and an NMOS transistor521are connected in series between the node517and the node537. A PMOS transistor515and an NMOS transistor535are connected in series between the node520and a node540.

One of the first control signals (Vpb) is input to each of the PMOS transistors501and515, and another one of the first control signals (Vnb) is input to a gate of each of the NMOS transistors521and535.

An NMOS transistor522is connected between the node537and a ground voltage source VSS, and an NMOS transistor531is connected between the node540and the ground voltage source VSS. Each of NMOS transistors525,527, and529is connected between the node539and the ground voltage source VSS.

One of the first control signals (Vnnb<0>) is input to a gate of each of the NMOS transistors522,525, and531. Another one of the first control signals (Vnnb<1>) is input to a gate of the NMOS transistor527, and another one of the first control signals (Vnnb<2>) is input to a gate of the NMOS transistor529.

The respective output signal Vout1for the first input buffer2401is generated at a node coupling the PMOS transistor515and the NMOS transistor535. The output signal Vout1swings between the voltages VDD and VSS, to generate the output signal Vout1that is of the CMOS swing type in one embodiment of the present invention. However, the present invention may be practiced with any other voltages instead of VDD and/or VSS such that the output signal Vout1is of any other predetermined signal type.

When the β ratio of the NMOS transistor525is 1 (X1), the β ratio of the NMOS transistor527is 2(X2), and the β ratio of the NMOS transistor529is 4(X2), in one embodiment of the present invention. Thus, the β ratios of the NMOS transistors525,527, and529increase geometrically in one embodiment of the present invention. However, the β ratio of each of the NMOS transistors525,527and529is not limited thereto.

Each of the PMOS and NMOS transistors505,507,509,525,527, and529, is a current source inFIG. 5. A respective level of current flowing through each of the PMOS and NMOS transistors505,507,509,525,527, and529is controlled by a respective one of the first control signals Vppb<0>, Vppb<1>, Vppb<2>, Vnnb<0>, Vnnb<1>, and Vnnb<2> coupled to the gate of such a transistor. By controlling the level of current that flows through each of the PMOS and NMOS transistors505,507,509,525,527, and529, a common-mode level of the first receiver5001is adjusted.

In this manner, the first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb indicate the signal type and thus a first common mode voltage of the differential input signals IN/INB to the receiver5001. The receiver5001uses such first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb to generate the output signal Vout1having a second common mode voltage of the CMOS swing type (or any other predetermined signal type) from the input signals IN/INB and such first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb.

Each of the other receivers5002,5003, . . . , and500mmay also be implemented in a similar manner as the first receiver5001ofFIG. 5to generate a respective output signal Vout from the respective input signals IN/INB and the respective first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb for each of the input buffers2401,2402,2403, . . . , and240m.

FIG. 6is a block diagram of a multi-port/multi-media semiconductor device230according to another embodiment of the present invention. Referring toFIGS. 2 and 6, the multi-port/multi-media semiconductor device230includes first through mthinput buffers2401,2402,2403, . . . , and240mand a bias voltage generator245. The bias voltage generator245ofFIG. 6generates a plurality of bias voltages Vppb, Vnnb, Vpb, and Vnb that is shared among the first through mthinput buffers2401,2402,2403, . . . , and240m.

Each of the registers3001′,3002′,3003′, . . . , and300m′receives a respective one of program control signals MRS1, MRS2, MRS3, . . . , and MRSm to generate a respective set of second control signals REG1<0:2n−1>, REG2<:2n−1>, REG3<0:2n−1>, . . . , and REGm<0:2n−1>. Each of the program control signals MRS1, MRS2, MRS3, . . . , and MRSm may be a MRS (mode register set) signal or a digital control signal.

Each of the drivers4001′,4002′,4003′, . . . , and400m′is implemented similarly to the driver4100ofFIG. 4, in one embodiment of the present invention. Each of the drivers4001′,4002′,4003′, . . . , and400m′receives a respective set of second control signals REG<0:2n−1> and the bias voltages Vppb, Vnnb, Vpb, and Vnb from, the bias voltage generator245. Using such signals, each of the drivers4001′,4002′,4003′, . . . , and400m′generates a respective set of first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb for each of the input buffers2401,2402,2403, . . . , and240m.

Each of the receivers5001,5002,5003, . . . , and500mofFIG. 6is implemented similarly to the receiver5001ofFIG. 5, in one embodiment of the present invention. Thus, each of the receivers5001,5002,5003, . . . , and500mreceives respective differential input signals IN/INB and a respective set of first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb that control the current sources within the receiver to generate a respective output signal Vout that is of the CMOS swing type (or any other predetermined signal type). As a result, each of the output signals Vout of the receivers5001,5002,5003, . . . , and500mis of the predetermined signal type (such as CMOS swing type) regardless of the signal type of the differential input signals to each of the input buffers2401,2402,2403, . . . , and240m.

Each of the output signals Vout1, Vout2, Vout3, . . . , and Voutm is input to a latch (not shown) synchronized with a system clock signal transmitted to the multi-port/multi-media semiconductor device230.

Table 2 illustrates the logic state of the second control signals REG<0:5> when “n” is 3 in the expression “2n−1” for each of different signal types of the differential input signals IN/INB. Here, “L” denotes a logic low, and “H” denotes a logic high.

Referring to Tables 1 and 2, andFIGS. 2 through 5, assume for example that the first input signals IN1/INB1are of the TMDS signal type with a DC reference level of 1.65 and with a swing width of ±150 mV. The manufacturer of the semiconductor device230determines such a signal type of the first input signals IN1/INB1from the specifications.

In that case, the first mode program circuit3001is programmed based on such a DC reference level and swing width of the first input signals IN1/INB1. A program control signal for programming the first mode program circuit3001may be input from a source outside the semiconductor device230. The MRS signal may be used as the program control signal. Alternatively, the first mode program circuit3001may be programmed by cutting or not cutting each of a plurality of fuses.

The first mode program circuit3001generates the second control signals REG<0:5> with logic states as indicated in Table 2 for the case when the input signals IN/INB are of the TMDS signal type. The driver4100generates the first control signals Vppb<0:2> and Vnnb<0:2> based on the logic states of the second control signals REG<0:5>.

The first mode program circuit3001or the first mode control circuit4001generates the bias voltages Vpb and Vnb and outputs the bias voltages Vpb and Vnb to the first receiver5001, in one embodiment of the present invention. The first receiver5001receives the first input signals IN1/INB1and the first control signals Vppb<0:2>, Vnnb<0:2>, Vpb, and Vnb and generates the first output signal Vout1which swings between voltage levels VDD and VSS (i.e., for CMOS swing).

For another example, assume that the first input signals IN1/INB1are of the RSL signal type with a DC reference level of 1.4 and with a swing width of ±400 mV. In that case, the first mode program circuit3001is programmed based on such a DC reference level and swing width of the first input signals IN1/INB1. Accordingly, the first mode program circuit generates the second control signals REG<0:5> indicating the signal type of the input signals IN1/INB1.

Thereafter, the first mode control circuit4001generates the first control signals Vppb<0:2>, Vppn<0:2>, Vpb, and Vnb in response to the second control signals REG<0:5> and transmits the first control signals Vppb<0:2>, Vppn<0:2>, Vpb, and Vnb to the first receiver5001. The first receiver5001receives the first input signals IN1/INB1and the first control signals Vppb<0:2>, Vppn<0:2>, Vpb, and Vnb to generate the first output signal Vout1which also swings between voltage levels VDD and VSS (i.e., for CMOS swing).

Similarly, those of ordinary skill in the art would understand the operations of the first input buffer2401when the first input signals IN1/INB1are of the SSTL signal type or the LVDS signal type.

Example operations of the first through mthinput buffers2401through240mwill now be described with reference to Tables 1 and 2, andFIGS. 4 and 6. Assume for example that the first input signals IN1/INB1are of the TMDS signal type, the second input signals IN2/INB2are of the RSL signal type, the third input signals IN3/INB3are of the SSTL signal type, and the mthinput signals INm/INBm are of the LVDS signal type.

In that case, each of the registers3001′ through300m′is programmed depending on the respective DC reference level and swing width of the respective signal type of the respective input signals IN/INB as indicated by a respective one of the program control signals MRS1through MRSm. In addition, each of the registers3001′ through300m′outputs a respective set of second control signals REG<0:2n−1> indicating the signal type of the respective input signals IN/INB.

Each of the drivers4001′ through400m′receives the respective set of second control signals REG<0:2n−1> and the bias voltages Vppb, Vnnb, Vpb, and Vnb to generate a respective set of first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb. The respective set of first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb indicates the signal type and thus a first common mode voltage of the differential input signals IN/INB to each of the receivers5001through500m.Each of the receivers5001through500muses such first control signals Vppb<0:n−1>, Vnnb<0:n−1>, Vpb, and Vnb to generate a respective output signal Vout of a predetermined signal type (such as the CMOS swing type) regardless of the signal type of the differential input signals IN/INB.

In this manner, each of the input buffers2401,2402,2403, . . . , and240mgenerates a respective output signal Vout of a predetermined signal type (such as the CMOS swing type) regardless of the signal type of the respective input signals IN/INB. Thus, referring toFIGS. 1 and 2, interface circuits of application circuits communicating with the semiconductor device230using the input buffers2401,2402,2403, . . . , and240mof the present invention are eliminated, thereby minimizing power consumption and layout area.