Negative bias charge pump

The present invention concerns an apparatus generally comprising a plurality of pump stages each implemented on an independent well. The plurality of pump stages may each be configured to generate an output voltage. The plurality of pump stages may be serially connected such that a body bias voltage input of one stage is received from the output voltage of a previous stage.

FIELD OF THE INVENTION

The present invention relates to a method and/or architecture for implementing a charge pump generally and, more particularly, to a method and/or architecture for implementing a negative bias charge pump.

BACKGROUND OF THE INVENTION

A charge pump circuit can generate a high voltage pump output from a single input. Multiple charge pump circuits can be implemented serially to provide increasing voltages. Conventional negative charge pump circuits are built from a clock and capacitor circuit. Ideally, the serially implemented negative charge pump circuits can provide a (VDD Vth) increase at each output for a GND to VDD voltage potential. However, conventional charge pump circuits implement a single substrate (i.e., a single well) for multiple charge pump circuits. The source node voltage is degraded by increasing Vth which is caused by the increased body bias. As subsequent charge pump circuits are added, the source node voltage is degraded due to increasing body bias voltage. Since conventional negative charge pump circuits have high body bias voltage, the output voltage is limited. Additionally, negative charge pump circuits are limited by the technology in which they are implemented. For example, one could not implement a positive charge pump with a P-type substrate and without a twin well process.

Conventional charge pump circuits implement multiple stages in a single substrate. The bulks of each of the transistors within the stages acquire a large body bias voltage. Additionally, for each consecutive stage, a higher body bias voltage builds. For example, a source node can be at approximately 2VDD, while a ground node may have 2.5 volts of body bias voltage. The body bias voltage can degrade a threshold voltage of the conventional charge pump circuits. The body bias voltage can degrade voltage level of a charge pump output. The body bias voltages cause diminishing returns of conventional charge pump circuits. Conventional charge pump circuits can require ten or more stages to provide the desired return. The absolute negative voltage capable of being generating by conventional charge pump circuits is limited by body bias voltage.

SUMMARY OF THE INVENTION

The present invention concerns an apparatus generally comprising a plurality of pump stages each implemented on an independent well. The plurality of pump stages may each be configured to generate an output voltage. The plurality of pump stages may be serially connected such that a body bias voltage input of one stage is received from the output voltage of a previous stage.

The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a negative bias charge pump that may (i) provide increasing levels of negative output voltage, (ii) allow a relatively large negative output voltage to be developed from a smaller negative bias voltage and/or (iii) implement an independent well for each negative charge pump circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1 , a block diagram of a circuit 100 is shown in accordance with a preferred embodiment of the present invention. The circuit 100 may provide increasing levels of negative output voltage. The circuit 100 may allow a negative charge pump circuit to generate a relatively large negative output voltage from a smaller negative bias voltage. However, the circuit 100 may require an initialization circuit (to be described in more detail in connection with FIG. 4 ).

The circuit 100 generally comprises a number of charge pumps (or stages) 102 a - 102 n . In one example, the stages 102 a - 102 n may be implemented as negative bias charge pump circuits. Each of the stages 102 a - 102 n may be implemented with an independent substrate (e.g., an independent well). However, another appropriate number of stages may be implemented in a substrate in order to meet the criteria of a particular implementation. For example, a number of stages may be implemented in a first substrate and another number of stages may be implemented in a second substrate. However, a minimized number of stages implemented per substrate may provide improved reduced body bias voltage. The circuit 100 may have an input 104 that may receive a signal (e.g., VSS), an input 106 that may receive a number of clock signals (e.g., CLK 1 ), an input 108 that may receive a number of clock signals (e.g., CLK 2 ) and an output 110 that may present a signal (e.g., N(VDD Vth), where Vth is a mos threshold voltage and N is an integer equal to the number of stages). In one example, the signal N(VDD Vth) may be implemented as an output voltage that may be generated in response to the signal VSS. The signals N(VDD Vth) and VSS may be implemented as a voltage on a node, a voltage level, or other appropriate input/output signal in order to meet the criteria of a particular implementation.

The stage 102 a may have an input 112 a that may receive a voltage (e.g., the signal VSS), an input 114 a that may receive a clock signal (e.g., the signal CLK 1 ) and an output 116 a that may generate an output voltage (e.g., (VDD Vth)). The remaining stages 102 b - 102 n may have similar inputs and outputs. For example, the stage 102 b may have an input 112 b that may receive the signal (VDD Vth), an input 114 b that may receive the clock signal CLK 2 and an output 116 b that may generate a voltage (e.g., 2(VDD Vth)). The stage 102 n may have an input 112 n that may receive the signal 2(VDD Vth), an input 114 n that may receive the clock signal CLK 1 and an output that may generate the voltage N(VDD Vth).

The circuit 100 may implement each of the charge pump circuits 102 a - 102 n on electrically separate substrates (e.g., separate wells). However, more than one stage 102 a - 102 n may be implemented on a single substrate. The circuit 100 may allow the charge pump circuits 102 a - 102 n to utilize the output voltage of a previous charge pump circuit as a bias voltage (e.g., well bias voltage) for a succeeding charge pump circuit. For example, the charge pump circuit 102 a may provide the output voltage (VDD Vth) that may be presented to the charge pump circuit 102 b . Ideally, each succeeding stage 102 a - 102 n may have an output voltage equal to an output voltage of the previous stage 102 a - 102 n plus the bias voltage (e.g., (VDD Vth). For example, if the bias voltage (VDD Vth) is 3 volts, an ideal circuit with six charge pump stages 102 a - 102 n may generate a 18 volt output.

Referring to FIG. 2 , a detailed schematic of the stage 102 a is shown. Each of the stages 102 b - 102 n may have a similar implementation as the stage 102 a . The charge pump 102 a may be implemented on an electrically independent substrate (e.g., an independent well) from the other stages 102 b - 102 n . The stage 102 a generally comprises a transistor 120 , a transistor 122 , a capacitor 124 and a capacitor 126 . The stage 102 a generally comprising the input 112 a , the input 114 a 1 , the input 114 a 2 and the output 116 a. The input 112 a may receive the voltage VSS, the input 114 a 1 may receive the clock signal CLK 1 . The input 114 a 2 may receive the clock signal CLK 1 b and the output 116 a may present the signal (VDD Vth). In one example, the clock signal CLK 1 b may be implemented as a complement of the clock signal CLK 1 . The clock signal CLK 1 and the clock signal CLK 1 b may be implemented as non-overlapping clock signals. For example, the clock signals CLK 1 and CLK 1 b may active and/or non-active portions at the same time (e.g., inverted, but no skew).

The signal CLK 1 may be presented to a first side of the capacitor 126 . A second side of the capacitor 126 may be coupled to a source of the transistor 120 and a gate of the transistor 122 . A bulk of the transistor 120 and a bulk of the transistor 122 may be coupled to the node VSS. Additionally, a drain of the transistor 120 and a drain of the transistor 122 may be coupled to the node VSS. The complement clock signal CLK 1 b may be presented to a first side of the capacitor 124 . A second side of the capacitor 124 may be coupled to a gate of the transistor 120 , the node VDD and a source of the transistor 122 .

Each of the transistors 120 and 122 may be implemented in an independent well. The transistors 120 and 122 may be implemented in a single, double or triple well process substrate. However, each stage 102 a - 102 n may be required to have a unique bias voltage. Each of the stages 102 a - 102 n may implement an output of the previous stage to bias the bulk of the next stage. The circuit 100 may tie the bias voltage to the source voltage of a next stage, to reduce body bias voltage to the source.

Referring to FIG. 3 , a detailed schematic of the circuit 100 is shown. The circuit 100 may implement an output voltage of a previous charge pump circuit (e.g., (VDD Vth) from the stage 102 a ) as an input bias voltage for a succeeding charge pump circuit (e.g., the stage 102 b ). For example, the charge pump 102 b may receive the bias voltage (VDD Vth) as an input from the charge pump 102 a . Similarly, the charge pump circuit 102 n may receive the bias voltage 2(VDD Vth) as an input for the charge pump 102 b.

Referring to FIG. 4 , a block diagram of the circuit 100 implemented with an initialization circuit 200 is shown. The initialization circuit 200 may receive a signal (e.g., RESET). The signal RESET may control the initialization circuit 200 . Additionally, the initialization circuit 200 may be coupled to a number of output nodes of the stages 102 a - 102 n (e.g., A, B and C). The initialization circuit 200 may be initialized in response to the signal RESET.

An assertion (e.g., high or 1 ) on the signal RESET may bring a potential of the nodes A, B and C to ground. The signal RESET may initialize each well of the stages 102 a - 102 n to ground. However, when the signal RESET is de-asserted (e.g., low or 0 ) the potential on the nodes A, B and C may be driven by each respective stage 102 a - 102 n.

The various signals are generally on (e.g., a digital HIGH, or 1) or off (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) accordingly to meet the design criteria of a particular implementation.

Conventional charge pump circuits may have diminishing returns on a pumped voltage output due to increasing body bias voltage. For example, a conventional implementation of six charge pump stages with an internal bias voltage of 3 volts may have approximately a 10 volt output instead of an ideal 18 volt output. The circuit 100 may provide an improved negative bias voltage charge pump circuit that may have an increased return over conventional approaches. For example, the circuit 100 with a bias voltage of 3V and six stages may have an output in the range of 15V to 16V.

The negative charge pump stages 102 a - 102 n may implement the clock signals CLK 1 and CLK 2 and the capacitors 124 a - 124 n and 126 a - 126 n to generate an increased negative voltage. The particular clocking phases of the clock signals CLK 1 and CLK 2 may allow the circuit 100 to generate a negative voltage at the output node N(VDD Vth). A particular negative output voltage may be determined by a particular number of implemented stages 102 a - 102 n . For example, a single negative charge pump with a GND to (VDD Vth) potential may generate an output voltage level that may be twice that of (VDD Vth).

Each stage 102 a - 102 n may be implemented with an independent well. Since the circuit 100 may not have negative voltages on a single substrate, the stages 102 a - 102 n may implement an output of the previous stage to bias the bulk of the next stage. The circuit 100 may tie the bias voltage to the source voltage of a next stage, to reduce body bias voltage to the source.

The circuit 100 may be implemented for a number of specific applications. For example, to generate a 20 volt output, a 15 volt output or similar negative voltage with a 3 volt supply is nearly impossible with conventional charge pumps. The circuit 100 may allow such voltage generation. Additionally, conventional charge pump circuits may generate up to 100 millivolts of body bias voltage effect from each successive stage and may require 20 or 30 more stages than the charge pump circuit 100 to generate a comparable negative voltage.

The circuit 100 may implement a negative charge pump design that may provide an independent well for each stage. The circuit 100 may allow the bias voltage of each succeeding negative charge pump circuit to be the output voltage of the previous negative charge pump circuit.