A flip-flop circuit including a first logic circuit, a first master latch, a second master latch, and a slave latch is provided. The first logic circuit operates a logic operation on a selecting signal and a clock signal to generate a first control signal. The first master latch receives a data signal according to the first control signal and latches the data signal according to the selecting signal and the clock signal. The second master latch receives a scan data signal according to the selecting signal and the clock signal, wherein an output terminal of the second master latch is directly connected to an output terminal of the first master latch. The slave latch latches a signal on the output terminals of the first and second master latches for generating an output signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 104135538, filed on Oct. 29, 2015. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a flip-flop circuit, and particularly relates to a flip-flop circuit capable of decreasing a setup time.

Description of Related Art

In a design of a digital integrated circuit (IC), a flip-flop circuit is a commonly used register. In a chip level design, a scanning type flip-flop is usually applied in the design of a clock tree. In an application requiring a high-speed computation (for example, a high-speed central processing unit), in order to make the flip-flop circuit to satisfy the demand of the high-speed computation, to effectively decrease a setup time of the flip-flop circuit becomes an important demand.

In the conventional technical field, the flip-flop circuit may receive a data signal, and implement a data latch operation through a plurality of transmission gates. Generally, the flip-flop includes two latches connected in series, and the transmission gates in the latches may implement the data latch operation through complementary turning on or off operations. On the other hand, in order to decrease the setup time of the flip-flop circuit, in the conventional technique, a phase difference between a clock signal and an inverted clock signal in the flip-flop circuit can be adjusted for implementation. However, such method prolongs a CK to Q delay of a clock terminal to an output terminal of the flip-flop circuit.

SUMMARY OF THE INVENTION

The invention is directed to a flip-flop circuit, which may effectively decrease a required setup time.

The invention provides a flip-flop circuit including a first logic circuit, a first master latch, a second master latch, and a slave latch. The first logic circuit receives a selecting signal and a clock signal, and operates a logic operation on the selecting signal and the clock signal to generate a first control signal. The first master latch is coupled to the first logic circuit and receives the first control signal. The first master latch receives the clock signal and a data signal, and receives the data signal according to the first control signal, and latches the data signal according to the clock signal and the selecting signal. The second master latch receives the selecting signal, the clock signal and a scan data signal, and latches the scan data signal according to the selecting signal and the clock signal, where an output terminal of the second master latch is directly connected to an output terminal of the first master latch. The slave latch is coupled to the output terminals of the first master latch and the second master latch, and latches a signal on the output terminals of the first and second master latches according to the clock signal for generating an output signal.

According to the above descriptions, by setting the first logic circuit at a front end of the first master latch, and using the first control signal generated by the first logic circuit for controlling a time point that the first master latch receives the data signal, the time point that the first master latch receives the data signal can be directly controlled through a variation of a voltage level of the clock signal, which may effectively decrease the demand of the setup time of the flip-flop circuit. More importantly, the first master latch of the invention is maintained to latch the data signal according to the clock signal and the selecting signal, and the CK to Q delay of the clock terminal to the output terminal thereof is not prolonged.

DESCRIPTION OF EMBODIMENTS

Referring toFIG. 1,FIG. 1is a schematic diagram of a flip-flop circuit according to an embodiment of the invention. The flip-flop circuit200includes a first master latch210, a second master latch220, a slave latch230and a logic circuit240. The logic circuit240receives a selecting signal SEL and a clock signal CK, and operates a logic operation on the selecting signal SEL and the clock signal CK to generate a control signal CTRL1. The first master latch210is coupled to the logic circuit240. The first master latch210receives the control signal CTRL1generated by the logic circuit240, and receives a data signal D, the clock signal CK and the selecting signal SEL. The first master latch210receives the data signal D according to the control signal CTRL1, and latches the data signal D according to the clock signal CK and the selecting signal SEL.

The second master latch220receives the selecting signal SEL, the clock signal CK and a scan data signal SD. The second master latch220latches the scan data signal SD according to the selecting signal SEL and the clock signal CK. It should be noted that an output terminal of the second master latch220is directly connected to an output terminal OE of the first master latch210.

The slave latch230is coupled to the output terminals of the first master latch210and the second master latch220. The slave latch230receives and latches a signal on the output terminals of the first and second master latches210and220according to the clock signal CK and the selecting signal SEL for generating an output signal OUT.

In view of the operation detail, the selecting signal SEL is used for indicating to turn on one of the first master latch210and the second master latch220to perform the data latch operation of the data signal D or the scan data signal SD. For example, when the selecting signal SEL is in a first logic level (for example, a logic low level), the first master latch210is turned on to perform the data latch operation on the data signal D, and the second master latch220is turned off without performing the data latch operation. Comparatively, when the selecting signal SEL is in a second logic level (for example, a logic high level), the second master latch220is turned on to perform the data latch operation on the scan data signal SD, and the first master latch210is turned off without performing the data latch operation.

It should be noted that the logic circuit240operates the logic operation on the selecting signal SEL and the clock signal CK to generate the control signal CTRL1. The control signal CTRL is provided to the first master latch210to serve as a basis for receiving the data signal D. Compared to the clock signal CK, the selecting signal SEL has a relatively stable logic level, and according to the above description, when the selecting signal SEL is in the first logic level, and a logic level of the clock signal CK is gradually transited from the second logic level to the first logic level, at the moment that the logic level of the clock signal CK is transited to the first logic level, the first master latch210may opportunely receive the data signal D according to the correspondingly generated control signal CTRL, and performs the latch operation on the data signal D according to the clock signal CK and the selecting signal SEL. In this way, a setup time of the flip-flop circuit200is effectively reduced.

On the other hand, in the present embodiment, the clock signal CK and the selecting signal SEL used for implementing the latch operation of the data signal D are not changed, and therefore a CK to Q delay of a clock terminal to an output terminal of the flip-flop circuit200is not prolonged.

Referring toFIG. 2,FIG. 2is a circuit diagram of a flip-flop circuit according to an embodiment of the invention. The flip-flop circuit300includes a first master latch310, a second master latch320, a slave latch330and a logic circuit340. In the present embodiment, the logic circuit340includes logic gates NR1and ND1. The logic gate NR1is a NOR gate, and the logic gate ND1is a NAND gate. The logic gate NR1receives the selecting signal SEL and a clock signal CK1, and the logic gate ND1receives an inverted signal SELB of the selecting signal SEL and an inverted signal CKB of the clock signal CK1. The logic circuit340generates a control signal CTRL1with the logic high level and an inverted signal CTRL1B of the control signal CTRL1with the logic low level when the selecting signal SEL is in the logic low level and the clock signal CK1is transited to the logic low level. Comparatively, in case that the selecting signal SEL and the clock signal CK1are not simultaneously in the logic low level, the logic circuit340generates the control signal CTRL1with the logic low level and the inverted signal CTRL1B thereof with the logic high level.

The first master latch310includes a tri-state inverter311, inverters INV11and INV12and transmission gates TG11and TG12. The tri-state inverter311has a data input terminal DI and enable terminals E1and E2. The data input terminal DI receives the data signal D, and the enable terminals E1and E2respectively receive the control signal CTRL1and CTRL1B. The tri-state inverter311is composed of transistors M311-M314connected in series, where a first terminal of the transistor M311receives a power voltage VDD, a second terminal thereof is coupled to a first terminal of the transistor M312, and a control terminal of the transistor M311is the enable terminal E2. A second terminal of the transistor M312is coupled to a first terminal of the transistor M313, a second terminal of the transistor M313is coupled to a first tell final of the transistor M314, and control terminals of the transistors M312and M313are coupled to the data input terminal DI. Moreover, a second terminal of the transistor M314is coupled to a reference ground terminal GND, and a control terminal thereof is the enable terminal E1.

In the tri-state inverter311, the second terminal of the transistor M312is an output terminal of the tri-state inverter311. The output terminal of the tri-state inverter311is further coupled to an input terminal of the inverter INV11, and an output terminal of the inverter INV11is coupled to an input terminal of the transmission gate TG11. Moreover, an output terminal of the transmission gate TG11is the output terminal OE of the first master latch310, and is coupled to an input terminal of the inverter INV12. An output terminal of the inverter INV12is coupled to an input terminal of the transmission gate TG12, and an output terminal of the transmission gate TG12is coupled to the input terminal of the inverter INV11. The transmission gate TG11is turned on/off according to the selecting signal SEL and the inverted signal SELB thereof, and the transmission gate TG12is turned on/off according to the clock signal CK1and the inverted signal CKB thereof.

In view of the operation detail, when the selecting signal SEL is maintained to the logic low level, and at the moment that the clock signal CK1is transited to the logic low level, the logic circuit340generates the control signal CTRL1and the inverted signal CTRL1B thereof with the logic high level. Meanwhile, the tri-state inverter311may receive the data signal D on the data input terminal DI, and transmits the data signal D to the internal of the first master latch310, i.e. the input terminal of the inverter INV11. Meanwhile, through the turned on transmission gate TG11and the inverter INV12, the latch operation on the data signal D can be smoothly implemented when the clock signal CK1is transited to the logic high level.

It should be noticed that compared to the conventional technique, the output terminal of the tri-state inverter311of the present embodiment is directly connected to the inverter INV11, and none transmission gate is disposed therebetween, such that the number of circuit components between the data input terminal DI and the output terminal OE of the first master latch310is decreased to effectively mitigate a transmission delay of the data signal D occurred therebetween. Moreover, by using the logic circuit340to integrate the selecting signal SEL and the clock signal CK1to generate the control signal CTRL1, and controlling a time point that the tri-state inverter311receives the data signal D through the control signal CTRL1, the demand of the setup time is effectively decreased.

It should be noted that in the present embodiment, through inverters INV51and INV52connected in series, the inverted signal CKB and the clock signal CK1can be sequentially produced according to the clock signal CK. Through an inverter INV53, the inverted signal SELB can be produced according to the selecting signal SEL.

In view of the second master latch320, the second master latch320includes a tri-state inverter321, inverters INV21and INV22and transmission gates TG21, TG22and TG23. The tri-state inverter321is composed of transistors M321-M324connected in series, where a first terminal of the transistor M321receives the power voltage VDD, a second terminal thereof is coupled to a first terminal of the transistor M322, and a control terminal of the transistor M321receives the inverted signal SELB of the selecting signal SEL. A second terminal of the transistor M322is coupled to a first terminal of the transistor M323, a second terminal of the transistor M323is coupled to a first terminal of the transistor M324, and control terminals of the transistors M322and M323are coupled to each other to receive the scan data signal SD. Moreover, a second terminal of the transistor M324is coupled to the reference ground terminal GND, and a control terminal thereof receives the selecting signal SEL.

The second terminal of the transistor M322forms an output terminal of the tri-state inverter321, and the output terminal of the tri-state inverter321is further coupled to an input terminal of the transmission gate TG21. Moreover, an output terminal of the transmission gate TG21is coupled to an input terminal of the inverter INV21, and an output terminal of the inverter INV21is coupled to an input terminal of the transmission gate TG22. An output terminal of the transmission gate TG22is coupled to an input terminal of the inverter INV22, and forms an output terminal of the second master latch320. The output terminal of the second master latch320is directly connected to the output terminal OE of the first master latch310. Moreover, an output terminal of the inverter INV22is coupled to an input terminal of the transmission gate TG23, and an output terminal of the transmission gate TG23is coupled to the output terminal of the transmission gate TG21. In the present embodiment, the transmission gates TG21and TG23are turned on/off according to the clock signal CK1, and turning on/off states of the transmission gates TG21and TG23are opposite to each other. The transmission gate TG22is turned on/off according to the selecting signal SEL.

In view of the slave latch330, the slave latch330includes transmission gates TG31and TG32and inverters INV31and INV32. An input terminal of the transmission gate TG31is coupled to the output terminal OE of the first master latch310, and an output terminal of the transmission gate TG31is coupled to an input terminal of the inverter INV31. An output terminal of the inverter INV31is coupled to an input terminal of the inverter INV32, and an output terminal of the inverter INV32is coupled to an input terminal of the transmission gate TG32, and an output terminal of the transmission gate TG32is coupled to the output terminal of the transmission gate TG31. The transmission gates TG31and TG32are turned on/off according to the clock signal CK1, and turning on/off states of the transmission gates TG31and TG32are opposite to each other. The output terminal of the inverter INV31can be an output terminal of the slave latch330and is used for producing the output signal OUT.

In the present embodiment, the flip-flop circuit300may further include an inverter INV31. An input terminal of the inverter INV41receives the output signal OUT and produces an inverted output signal OUTB. The logic levels of the inverted output signal OUTB and the latched data signal D or the scan data signal SD are the same.

Referring toFIG. 3AandFIG. 3B,FIG. 3AandFIG. 3Bare different implementations of the logic circuit according to the embodiments of the invention. InFIG. 3A, the logic circuit410includes a logic gate ND2and an inverter INV411. The logic gate ND2is a NAND gate, and receives the inverted signals SELB and CKB. The logic gate ND2generates the inverted signal CTRL1B of the control signal CTRL1according to the inverted signals SELB and CKB. An input terminal of the inverter INV411is coupled to an output terminal of the logic gate ND2, and generates the control signal CTRL1according to the inverted signal CTRL1B.

The logic circuit420ofFIG. 3Bis a variation of the logic circuit410ofFIG. 3A, in which the logic gate AD1is an AND gate, and the logic gate AD1receives the inverted signals SELB and CKB, and generates the control signal CTRL1according to the inverted signals SELB and CKB. An input terminal of the inverter INV421is coupled to an output terminal of the logic gate AD1, and the inverter INV421generates the inverted signal CTRL1B according to the control signal CTRL1.

According to the implementations ofFIG. 3AandFIG. 3B, it can be easily known that the logic circuit of the invention may have a plurality of implementations. Those people with basic capability in logic design art should understand that the same logic operation result can be implemented through a plurality of different logic gate combinations. For example, the AND gate can be replaced by the NOR gate and a plurality of inverters, the OR gate can be replaced by the NAND gate and a plurality of inverters. Therefore, the implementations ofFIG. 3AandFIG. 3Bare not necessary implementation of the invention, and are not used for limiting an implementation scope of the invention.

Referring toFIG. 4,FIG. 4is a schematic diagram of another implementation of the second master latch according to an embodiment of the invention. InFIG. 4, a logic circuit510is configured at a front end of the second master latch520. Compared to the embodiment ofFIG. 2, one transmission gate is omitted in the second master latch520. In view of an implementation detail, the logic circuit510includes a logic gate OR1and an inverter INV51. The logic gate OR1is an OR gate, and receives the inverted signal SELB and the clock signal CK1. The logic gate OR1generates an inverted signal CTRL2B of a control signal CTRL2according to the inverted signal SELB and the clock signal CK1. An input terminal of the inverter INV511is coupled to an output terminal of the logic gate OR1, and the inverter INV511generates the control signal CTRL2according to the inverted signal CTRL2B.

Moreover, the second master latch520includes a tri-state inverter521, inverters INV521, INV522and transmission gates TG521and TG522. The tri-state inverter521is composed of four transistors M51-M54connected in series, where control terminals of the transistors M52and M53receive the scan data signal SD, and control terminals of the transistors M51and M54respectively receive the inverted signal CTRL2B and the control signal CTRL2. An output terminal of the tri-state inverter521is coupled to an input terminal of the inverter INV521, and an output terminal of the inverter INV521is coupled to an input terminal of the transmission gate TG521. An output terminal of the transmission gate TG521is coupled to an input terminal of the inverter INV522and is directly connected to the output terminal OE of the first master latch. An output terminal of the inverter INV522is coupled to an input terminal of the transmission gate TG522, and an output terminal of the transmission gate TG522is coupled to the input terminal of the inverter INV521.

In the present embodiment, by integrating the selecting signal SEL and the clock signal CK1through the logic circuit510, when the flip-flop circuit performs the data latch operation on the scan data signal SD, the required setup time can also be effectively decreased, so as to improve the working efficiency of the flip-flop circuit.

In summary, by setting the logic circuit at the front end of the first master latch, and using the logic circuit to integrate the selecting signal and the clock signal to generate the control signal, the control signal is used for controlling the time point that the first master latch receives the data signal, so as to effectively decrease the setup time required by the flip-flop circuit. Moreover, according to the above mechanism, the CK to Q delay of the clock terminal to the output terminal of the flip-flop circuit is not prolonged, so as to effectively improve the working efficiency of the flip-flop circuit.