Integrating metal-insulator-metal capacitors with fabrication of vertical field effect transistors

Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.

TECHNICAL FIELD

This disclosure relates generally to semiconductor fabrication techniques and, in particular, techniques for fabricating MIM (metal-insulator-metal) capacitors.

BACKGROUND

Capacitors are passive circuit components that are utilized in integrated circuitry of a semiconductor chip for various purposes. For example, capacitors can be utilized to decouple power supplies, to form memory elements, to form RC delay circuits, or provide various other circuit functions. While many types of capacitor structures can be utilized, MIM capacitors are commonly used for analog, microwave, and radio frequency (RF) applications. In general, planar MIM capacitors are comprised of two metallic plates separated by an insulator layer. The fabrication of planar MIM capacitors using conventional CMOS technologies requires multiple lithographic masking steps, which is time consuming and expensive. In this regard, the amount and complexity of additional processing steps that are incorporated as part of a semiconductor process flow to fabricate MIM capacitors should be minimized to reduce the fabrication costs and processing time for constructing semiconductor chips. In addition, since planar MIM capacitors typically occupy a relatively large footprint of die area, there is a need for small footprint, high capacitance MIM capacitor structures for highly-integrated advanced semiconductor chip applications.

SUMMARY

Embodiments of the invention include semiconductor devices comprising MIM capacitor devices that are integrated with vertical field effect transistor (FET) devices, as well as methods for integrating MIM capacitor formation as part of a semiconductor process flow for fabricating vertical FET devices.

For example, one embodiment includes a semiconductor device which comprises a first vertical FET device formed in a first device region of a substrate, a second vertical FET device formed in a second device region of the substrate, and a capacitor device formed in a third device region of the substrate. The first vertical FET device comprises a first vertical semiconductor fin, and a first gate structure disposed around sidewalls of the first vertical semiconductor fin, wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode. The second vertical FET device comprises a second vertical semiconductor fin, and a second gate structure disposed around sidewalls of the second vertical semiconductor fin, wherein the second gate structure comprises a second gate dielectric layer and a second gate electrode. The capacitor device comprises a first capacitor electrode, a second capacitor electrode, and a capacitor insulator layer disposed between the first and second capacitor electrodes. The first gate electrode of the first FET device and the first capacitor electrode of the capacitor device are formed from a same first layer of conductive material. The second gate electrode of the second FET device and the second capacitor electrode of the capacitor device are formed from a same second layer of conductive material. The second gate dielectric layer of the second FET device and the capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.

Another embodiment includes a method for fabricating a semiconductor device. The method comprises:

forming a substrate comprising a lower source/drain layer disposed between a base semiconductor substrate and a layer of semiconductor material;

patterning the layer of semiconductor material to form at least a first vertical semiconductor fin and a second vertical semiconductor fin;

forming trench isolation regions through portions of the lower source/drain layer and into the semiconductor substrate to define a plurality of device regions comprising a first device region, a second device region, and a third device region, wherein the first device region comprises the first vertical semiconductor fin and a first lower source/drain region, and wherein the second device region comprises the second vertical semiconductor fin and a second lower source/drain region;

concurrently forming (i) a first gate structure surrounding sidewalls of the first vertical semiconductor fin in the first device region, and (ii) a first capacitor electrode in the third device region, wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode, wherein the first gate electrode and the first capacitor electrode are concurrently formed from a same first layer of conductive material by depositing and patterning said same first layer of conductive material; and

concurrently forming (i) a second gate structure surrounding sidewalls of the second vertical semiconductor fin in the second device region, (ii) a capacitor insulator layer on the first capacitor electrode and (iii) a second capacitor electrode on the capacitor insulator layer in the third device region, wherein the second gate structure comprises a second gate dielectric layer and a second gate electrode; wherein the second gate dielectric layer and the capacitor insulator layer are concurrently formed from a same conformal layer of dielectric material by depositing and patterning said same conformal layer of dielectric material, and wherein the second gate electrode and the second capacitor electrode are concurrently formed from a same second layer of conductive material by depositing and patterning said same second layer of conductive material.

Other embodiments will be described in the following detailed description of embodiments, which is to be read in conjunction with the accompanying figures.

DETAILED DESCRIPTION

Embodiments of the invention will now be described in further detail with regard to semiconductor devices comprising MIM capacitor devices that are integrated with vertical FET devices, as well as methods for integrating MIM capacitor formation as part of a FEOL (front-end-of-line) process flow for fabricating vertical FET devices. As explained in further detail below, semiconductor fabrication techniques according to embodiments of the invention enable MIM capacitor devices to be readily fabricated within an FEOL layer using CMOS process modules of a FEOL process flow to construct vertical FET devices. The exemplary semiconductor process flows described herein allow integration of MIM capacitor devices with vertical FET devices for technology nodes of 7 nm and beyond.

It is to be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic illustrations that are not drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.

Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings. It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error is present, such as 1% or less than the stated amount. Further, the term “vertical” or “vertical direction” as used herein denotes a Z-direction of the XYZ Cartesian coordinates shown in the drawings, and the terms “horizontal,” or “horizontal direction,” or “lateral direction” as used herein denotes an X-direction and/or Y-direction of the XYZ Cartesian coordinates shown in the drawings.

FIGS. 1A and 1Bare schematic views of a semiconductor device100comprising MIM capacitor devices that are integrated with vertical FET devices, according to an embodiment of the invention.FIG. 1Ais a schematic cross-sectional view (X-Z plane) of the semiconductor device100along line1A-1A as shown inFIG. 1B, andFIG. 1Bis a schematic top plan view of the semiconductor device100along an X-Y plane and direction as shown by line1B-1B inFIG. 1A. Referring toFIG. 1A, the semiconductor device100comprises a base semiconductor substrate102, a lower source/drain layer104, trench isolation regions120, a plurality of vertical semiconductor fins111,112,113, and114, a lower insulating spacer125, a first gate structure130, a second gate structure140, a MIM capacitor device150, insulating regions155, upper source/drain regions162and164, an upper insulating spacer165, a first ILD layer170, a second ILD layer180, and source/drain contacts182and185. It is to be understood that the term “source/drain region” as used herein means that a given source/drain region can be either a source region or a drain region, depending on the application or circuit configuration.

In the example embodiment shown inFIGS. 1A and 1B, the semiconductor device100comprises a plurality of different device regions including, for example, a first vertical FET device region R1(or first device region), a second vertical FET device region R2(or second device region), and a MIM capacitor device region R3(or third device region). The device regions R1, R2, and R3are defined by the trench isolation regions120. The trench isolation regions120are formed through the lower source/drain layer104and into the semiconductor substrate102to define separate lower source/drain regions104-1and104-2for the vertical FET devices in the first and second device regions R1and R2. As shown inFIG. 1A, the lower insulating spacer125serves to electrically insulate the lower source/drain regions104-1and104-2from the gate structures130and140, respectively, as well as electrically insulate the MIM capacitor device150from the underlying portion of the lower source/drain layer104within the third device region R3. The upper insulating spacer165serves to electrically insulate the upper source/drain regions162and164from the gate structures130and140, respectively. The insulating regions155serve to electrically insulate the gate structures140and150and the MIM capacitor device150from surrounding structures.

The first device region R1comprises at least one vertical FET device which comprises the vertical semiconductor fins111and112, the lower source/drain region104-1, the upper source/drain regions162, and the gate structure130. The gate structure130comprises a conformal gate dielectric layer132A and a gate electrode134A. As collectively shown inFIGS. 1A and 1B, the conformal gate dielectric layer132A is formed on the sidewalls of the vertical semiconductor fins111and112, and the gate electrode134A comprises conductive material (e.g., metal) that is disposed around the sidewalls of the vertical semiconductor fins111and112. The vertical semiconductor fins111and112are commonly connected at one end to the lower source/drain region104-1with the separate upper source/drain regions162epitaxially grown on opposing ends of vertical semiconductor fins111and112. The vertical source/drain contacts182(outlines shown in phantom inFIG. 1Bas dashed lines) are commonly connected to each of the upper source/drain regions162. In this configuration, the vertical semiconductor fins111and112comprise two FET channel segments that are connected in parallel, with a common gate structure130, to collectively form a single, multi-fin vertical FET device in the first device region R1.

Similarly, second device region R2comprises at least one vertical FET device which comprises the vertical semiconductor fins113and114, the lower source/drain region104-2, the upper source/drain regions164, and the gate structure140. The gate structure140comprises a conformal gate dielectric layer142A and a gate electrode144A. As collectively shown inFIGS. 1A and 1B, the conformal gate dielectric layer142A is formed on the sidewalls of the vertical semiconductor fins113and114, and the gate electrode144A comprises conductive material (e.g., metal) that is disposed around the sidewalls of the vertical semiconductor fins113and114. The vertical semiconductor fins113and114are commonly connected at one end to the lower source/drain region104-2with the separate upper source/drain regions164epitaxially grown on opposing ends of vertical semiconductor fins113and114. The vertical source/drain contacts184(outlines shown in phantom inFIG. 1Bas dashed lines) are commonly connected to each of the upper source/drain regions164. In this configuration, the vertical semiconductor fins113and114comprise two FET channel segments that are connected in parallel, with a common gate structure140, to collectively form a single, multi-fin vertical FET device in the second device region R2.

In the third device region R3, the MIM capacitor device150comprises a first capacitor electrode134B, a second capacitor electrode144B, and a capacitor insulator layer142B disposed between the first and second capacitor electrodes134B and144B. As collectively shown inFIGS. 1A and 1B, the first capacitor electrode134B comprises a plurality of parallel vertical fins E1, E2, and E3, which are commonly connected at one end to an elongated vertical fin segment E4. Similarly, the second capacitor electrode144B comprises a plurality of parallel vertical fins E5, E6, E7, and E8, which are commonly connected at one end to an elongated vertical fin segment E9. In the example embodiment shown inFIGS. 1A and 1B, the first and second capacitor electrodes134B and144B comprise interdigitated comb-like electrode structures wherein the parallel vertical fins E1, E2, E3, E5, E6, E7, and E8are disposed in an overlapped, interdigitated configuration.

As is known in the art, the capacitance of the MIM capacitor device150is (i) directly proportional to the surface area (A) of the overlapping parallel vertical fins E1, E2, E3, E5, E6, E7, and E8of the first and second capacitor electrodes134B and144B, (ii) directly proportional to the dielectric constant of the dielectric material of the capacitor insulator layer142B, and (iii) inversely proportional to the thickness of the capacitor insulator layer142B. In this regard, a relatively large capacitance can be achieved in a relatively small capacitor footprint region (X-Y area) by implementing a MIM capacitor device structure (such as shown inFIGS. 1A and 1B) with an interdigitated vertical fin configuration.

As further shown inFIG. 1B, a plurality of vertical device contacts186A (outlines shown in phantom inFIG. 1Bas dashed lines) are formed through the insulating layers165,170and180(FIG. 1A) in alignment with, and in contact to, the segment E4of the first capacitor electrode134B. In addition, a plurality of vertical device contacts186B (outlines shown in phantom inFIG. 1Bas dashed lines) are formed through the insulating layers165,170and180(FIG. 1A) in alignment with, and in contact to, the segment E9of the second capacitor electrode144B. It is to be understood that the shapes and layout configurations of the various vertical contacts182,184,186A, and186B shown inFIG. 1Bare merely illustrative embodiments, and that other shapes and layout configurations of vertical contacts can be implemented. In addition, while not specifically shown inFIGS. 1A and 1B, vertical gate contacts would be formed through the insulating layers165,170and180in contact with the gate electrodes134A and144A of the respective gate structures140and150, and vertical source/drain contacts would be formed through the various layers in contact with the lower source/drain regions104-1and104-2in the vertical FET device regions R1and R2.

As noted above, semiconductor fabrication techniques according to embodiments of the invention implement an integrated process flow that enables the MIM capacitor device150in the third device region R3to be fabricated are part of the FEOL process modules that are used to construct the vertical FET devices in the first and second device regions R1and R2. In one example embodiment of the invention, the vertical FET devices formed in the first device region R1comprise high performance, low power, vertical FET devices that are fabricated with thin, high-k gate dielectric layers, while the vertical FET devices formed in the second device region R2comprise high power (high current) vertical FET devices with relatively thicker gate dielectric layers (e.g., silicon oxide) that can withstand time-dependent dielectric breakdown (TDDB) and other gate failure mechanisms that may result from high power applications. For example, the vertical FET device in the first device region R1may be a standard logic transistor which requires better gate control and low current flow, while the vertical FET device in the second device region may be an input/output (I/O) transistor which requires a larger current flow.

In one embodiment, a FEOL process flow is implemented in which the gate electrode134A of the gate structure130of the vertical FET device in the first device region R1and the first capacitor electrode134B of the MIM capacitor device150in the third device region R3are concurrently formed from a same layer of conductive material134(e.g.,FIG. 7) using a FEOL process module (e.g.,FIGS. 7, 8, 9A, and 9B) that comprises depositing and patterning the same layer of conductive material134to form the gate electrode134A and the first capacitor electrode134B. In addition, the FEOL process flow comprises a process module (e.g.,FIGS. 10, 11, and12) in which the gate dielectric gate layer142A of the gate structure140of the vertical FET device in the second device region R2and the capacitor insulator layer142B of the MIM capacitor device150in the third device region R3are concurrently formed from a same layer of dielectric material142(e.g.,FIG. 10) by depositing and pattering the same layer of dielectric material142. Moreover, the FEOL process flow comprises a process module in which the gate electrode144A of the gate structure140of the vertical FET device in the second device region R2and the second capacitor electrode144B of the MIM capacitor device150in the third device region R3are concurrently formed from a same layer of conductive material144(e.g.,FIG. 11) using a FEOL process module (e.g.,FIGS. 11, 12 and 13) that comprises depositing and patterning the same layer of conductive material144to form the gate electrode144A and the second capacitor electrode144B.

Methods for fabricating the semiconductor device100shown inFIGS. 1A and 1Bwill now be discussed in further detail with reference toFIG. 2throughFIG. 18, which schematically illustrate the semiconductor device100at various stages of fabrication. To begin,FIG. 2is a schematic cross-sectional side view of the semiconductor device at an intermediate stage of fabrication in which a lower source/drain layer104, a monocrystalline semiconductor layer106, and a hardmask layer108are formed on a semiconductor substrate102. The monocrystalline semiconductor layer106has a vertical height H (or thickness) which defines a height of vertical semiconductor fins that are subsequently formed by patterning the monocrystalline semiconductor layer106. The hardmask layer108comprise an insulating material, such as silicon nitride, which is patterned to form an etch hardmask that is used to pattern the monocrystalline semiconductor layer106in a subsequent process module. While the semiconductor substrate102is generically illustrated inFIG. 2, the semiconductor substrate102may comprise one of different types of semiconductor substrate structures.

For example, in one embodiment, the semiconductor substrate102may comprise a bulk semiconductor substrate formed of, e.g., silicon, or other types of semiconductor substrate materials that are commonly used in bulk semiconductor fabrication processes such as germanium, silicon-germanium alloy, silicon carbide, silicon-germanium carbide alloy, or compound semiconductor materials (e.g. III-V and II-VI). Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. In another embodiment, the semiconductor substrate102may comprise an active semiconductor layer (e.g., silicon layer, SiGe layer, III-V compound semiconductor layer, etc.) of a SOI (silicon on insulator) substrate, which comprises an insulating layer (e.g., oxide layer) disposed between a base substrate layer (e.g., silicon substrate) and the active semiconductor layer102in which active circuit components are formed as part of a FEOL layer.

The lower source/drain layer104and the monocrystalline semiconductor layer106are formed using known techniques and materials. For example, in one embodiment, the lower source/drain layer104comprises a doped epitaxial semiconductor layer that is epitaxially grown on a surface of the semiconductor substrate102, and the monocrystalline semiconductor layer106comprises an epitaxial semiconductor layer that is epitaxially grown on a surface of the lower source/drain layer104. In one embodiment, the monocrystalline semiconductor layer106is undoped. In another embodiment, the monocrystalline semiconductor layer106is lightly doped with doping concentration, for example, of less than 5×1018/cm3. As explained in further detail below, the lower source/drain layer104is subsequently patterned to form the lower source/drain regions104-1and104-2of the vertical FET devices in the respective device regions R1and R2, and the undoped monocrystalline semiconductor layer106is subsequently patterned to form the vertical semiconductor fins111,112,113and114of the vertical FET devices, as shown inFIGS. 1A and 1B.

The type of epitaxial semiconductor material that is used to form the lower source/drain layer104will vary depending on various factors including, but not limited to, the type of semiconductor material used to grow the monocrystalline semiconductor layer106(lattice-matched semiconductor materials), the device type (e.g., n-type or p-type) of the vertical FET devices, etc. For example, for n-type vertical FET devices, the lower source/drain layer104may comprise a doped epitaxial silicon (Si) material, and for p-type vertical FET devices, the lower source/drain layer104may comprise a doped epitaxial silicon-germanium (SiGe) layer. Moreover, in one embodiment, the undoped monocrystalline semiconductor layer106may comprise an undoped single crystal Si layer. The lower source/drain layer104and the monocrystalline semiconductor layer106can be formed with other types of semiconductor materials (e.g., III-V compound semiconductor materials) which are commonly used to form source/drain regions and vertical semiconductor fins for vertical FET devices.

Furthermore, the lower source/drain layer104can be doped using known techniques. For example, in one embodiment, the lower source/drain layer104is in-situ doped wherein dopants are incorporated into the lower source/drain layer104during epitaxial growth of the lower source/drain layer104using a dopant gas such as, for example, a boron-containing gas such as BH3for pFETs or a phosphorus or arsenic containing gas such as PH3or AsH3for nFETs. In another embodiment, dopants can be incorporated in the lower source/drain layer104after the epitaxy process using doping techniques such as ion implantation.

In yet another embodiment, the lower source/drain layer104can be formed without epitaxy. For example, the lower source/drain layer104can be formed by adding dopants into a surface of the semiconductor substrate102(to a target depth which defines a thickness of the lower source/drain layer104) using doping techniques such as ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, etc. The monocrystalline semiconductor layer106is then epitaxially grown on the lower source/drain layer104. The doping concentration in the lower source/drain layer104can be in a range from about 1×1019/cm3to about 4×1021/cm3. In some embodiments, the lower source/drain layer104may comprise different materials in different device regions, e.g., a first material for n-type vertical FET devices, and another material for p-type vertical FET devices. Similarly, the monocrystalline semiconductor layer106may comprise different materials in different device regions, e.g., a first material for n-type vertical FET devices, and another material for p-type vertical FET devices.

In another embodiment of the invention, the lower source/drain layer104can be formed by ion implantation of dopants into the surface of the semiconductor substrate102to form a buried doped layer at a target level below the surface of the semiconductor substrate102. For example, in this embodiment, the various layers102,104and106may represent an upper surface of a undoped monocrystalline silicon substrate, wherein the lower source/drain layer104is formed by implanting dopants at one or more ion implantation energies which are sufficient to form the lower source/drain layer104within a range of target depths below the surface of the semiconductor substrate layer (wherein the range of target depths define the initial thickness (H) of the undoped monocrystalline layer106). A thermal anneal process can be performed following the ion implantation process to recrystallize portions of the semiconductor substrate which may be partially damaged by the ion implantation, as is known in the art.

Next,FIG. 3is a schematic cross-sectional side view of the semiconductor structure ofFIG. 2after patterning the hardmask layer108to form an etch hardmask108-1, and patterning the monocrystalline semiconductor layer106using an image of the etch hardmask108-1to form an array of vertical semiconductor fins110. In the example embodiment, the array of vertical semiconductor fins110comprises the vertical semiconductor fins111and112formed in the first device region R1and the vertical semiconductor fins113and114formed in the second device region R2. The hardmask layer108may be patterned using known techniques including, but not limited to, standard photolithography techniques or sidewall image transfer (SIT) techniques, etc. A directional dry etch process (e.g., Reactive Ion Etch (RIE)) is then performed using the etch hardmask108-1to etch exposed portions of the monocrystalline semiconductor layer106down to the lower source/drain layer104, and to slightly recess exposed surfaces of the lower source/drain layer104.

As shown inFIG. 3, in one embodiment, the vertical semiconductor fins111,112,113, and114in the first and second device regions R1and R2are patterned to have the same width (W) and pitch (P) throughout the regions R1and R2, as well as the same length L in the Y-direction. In addition, the vertical semiconductor fins111,112,113, and114are formed with a height H which, as noted above, is defined by the thickness of the monocrystalline semiconductor layer106. In one example embodiment, the width W of the vertical semiconductor fins111,112,113, and114is in a range of about 5 nm to about 20 nm, the length L of the vertical fins111,112,113, and114is in a range of about 50 nm to about 1000 nm, and the pitch P of the vertical semiconductor fins111and112in the first device region R1, and the pitch P of the vertical semiconductor fins113and114in the second device region R2, is in a range of about 20 nm to about 100 nm. Further, the height H of the vertical semiconductor fins111,112,113and114is in a range of about 30 nm to about 100 nm.

A next stage of the fabrication process comprises forming trench isolation regions (e.g., shallow trench isolation regions or deep trench isolation regions), as schematically illustrated inFIG. 4. In particular,FIG. 4is a schematic cross-sectional side view of the semiconductor structure ofFIG. 3after forming the trench isolation regions120to define and isolate the different device regions R1, R2, and R3. In one embodiment of the invention, the trench isolation regions120are formed by a process which comprises forming an etch mask (e.g., photoresist mask) with openings that define images of trenches that are etched down through lower source/drain layer104into the semiconductor substrate layer102, depositing a layer of insulating material, such as silicon oxide, to fill the trenches, and then recessing the layer of insulating material down to the recessed surface of the lower source/drain layer104, to thereby form the trench isolation regions120shown in FIG.4. In another embodiment, the trench isolation regions120are formed with multiple insulating materials, e.g., forming a silicon nitride liner to line the trenches, and filling remaining portions of the trenches with silicon oxide material. A shown inFIG. 4, the trench isolation regions120extend into the substrate102below the lower source/drain layer104, thereby patterning the lower source/drain layer104to form the separate lower source/drain regions104-1and104-2of the vertical FET devices in the device regions R1and R2, and to isolate a remaining portion of the lower source/drain layer104within the third device region R3.

Next,FIG. 5is a schematic cross-sectional side view of the semiconductor structure ofFIG. 4after forming the lower insulating spacer125. In one embodiment, the lower insulating spacer125is formed by depositing a layer of dielectric material such as SiO2, SiN, SiBCN or SiOCN, or some other type of low-k dielectric material that is commonly used to form insulating spacers for vertical FET devices. In one embodiment, the lower insulating spacer125has a thickness that is substantially equal to a vertical recess depth of the lower source/drain layer104such that an upper surface of the lower insulating spacer125is substantially level with bottom surfaces of the vertical semiconductor fins111,112,113, and114. The lower insulating spacer125may be formed using a directional deposition process in which the dielectric/insulating material is directly deposited on lateral surfaces, or by blanket depositing the dielectric/insulating material followed by planarizing and recessing the dielectric/insulating material, using well-known deposition and etching techniques.

In particular, in one embodiment, the lower insulating spacer125is formed of insulating material, such as silicon oxide, which is selectively deposited on lateral surfaces of the semiconductor structure using a directional deposition process (e.g., Gas Cluster Ion Beam (GCIB)). The directional deposition process serves to primarily deposit insulating material on the lateral surfaces of the semiconductor structure (e.g., on the recessed surface of the lower source/drain layer104), while limiting or preventing deposition of insulating material on the vertical surfaces (e.g., sidewall surfaces of the vertical semiconductor fins111,112,113, and114). Any insulating material that is deposited on the upper lateral surfaces of the etch hardmask108-1are etched away in a subsequent planarizing process.

In another embodiment of the invention, the lower insulating spacer125can be formed as part of the process module for fabrication the trench isolation regions120. In particular, after etching the trenches in the layers104and102, a layer of insulating material (e.g., silicon oxide) is deposited and planarized down to the upper surfaces of the etch hardmask108-1. Then, the planarized surface of the insulating material layer is recessed using a suitable etch process until the recessed surface of the insulating material layer reaches a target thickness above the lower source/drain layer104, thereby concurrently forming the lower insulating spacer125and the trench isolation regions120using the same oxide material. With this process, a timed etch process is utilized to recess the layer of insulating material down to a target level which, for example, is substantially level with the bottom surfaces of the vertical semiconductor fins111,112,113, and114.

A next phase of the semiconductor fabrication process comprises an integrated process module for forming the gate structure130(e.g., metal gate structure) for the vertical FET device in the first device region R1together with the first capacitor electrode134B of the MIM capacitor150in the third device region R3, using a process flow as schematically illustrated inFIGS. 6-9B. In particular,FIG. 6is a schematic cross-sectional side view of the semiconductor structure ofFIG. 5after depositing a first conformal layer of dielectric material132over the surface of the semiconductor structure. In one embodiment, the first conformal layer of dielectric material132is formed by depositing one or more conformal layers of high-k dielectric material having a dielectric constant k of about 3.9 or greater.

For example, the first conformal layer of dielectric material132can include silicon oxide, silicon nitride, silicon oxynitride, boron nitride, high-k materials, or any combination of these materials. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k gate dielectric material may further include dopants such as lanthanum, aluminum. In one embodiment of the invention, the first conformal layer of dielectric material132is formed with a thickness in a range of about 0.5 nm to about 5.0 nm (or more preferably, in a range of about 0.5 nm to about 2.5 nm), which will vary depending on the target application. The first conformal layer of dielectric material132is deposited using known methods such as atomic layer deposition (ALD), for example, which allows for high conformality of the gate dielectric material.

In another embodiment, a thin conformal layer of work function metal (WFM) may be deposited over the first conformal layer of dielectric material132prior to depositing a layer of conductive material to form a gate electrode. In this regard, in one embodiment, the conformal layer of dielectric material132shown inFIG. 6would comprise a high-k gate stack structure comprising a thin conformal layer of dielectric material and a thin conformal WFM layer. The thin conformal WFM layer can be formed of one or more types of metallic materials, including, but not limited to, TiN, TaN, TiAlC, Zr, W, Hf, Ti, Al, Ru, Pa, TiAl, ZrAl, WAl, TaAl, HfAl, TiAlC, TaC, TiC, TaMgC, or other work function metals or alloys that are commonly used to obtain target work functions which are suitable for the type (e.g., n-type or p-type) of vertical FET devices that are to be formed. The conformal WFM layer is deposited using known methods such as ALD, chemical vapor deposition (CVD), etc. In one embodiment, the conformal WFM layer is formed with a thickness in a range of about 2 nm to about 5 nm.

Next,FIG. 7is a schematic cross-sectional side view of the semiconductor structure ofFIG. 6after depositing a first layer of conductive material134over the first conformal layer of dielectric material132. In one embodiment, the first layer of conductive material134is formed by depositing a metallic material such as tungsten, or any other suitable metallic material such as titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold, etc. In other embodiments, the first layer of conductive material134may be a conductive material including, but not limited to, a doped semiconductor material (e.g., polycrystalline or amorphous silicon, germanium, silicon germanium, etc.), a conducting metallic compound material (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotube, conductive carbon, graphene, or any suitable combination of such conductive materials. The first layer of conductive material134may further comprise dopants that are incorporated during or after deposition. The first layer of conductive material134is deposited using a suitable deposition process, for example, CVD, plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), plating, thermal or e-beam evaporation, sputtering, etc. In another embodiment, the first layer of conductive material134can serve as a WFM layer, in which case a separate conformal WFM layer is not deposited over the first conformal layer of dielectric material132prior to depositing the first layer of conductive material134.

Next,FIG. 8is a schematic cross-sectional side view of the semiconductor structure ofFIG. 7after planarizing the surface of the semiconductor structure down to the etch hardmask108-1and forming a first cut mask136over the planarized surface of the semiconductor structure. The first cut mask136is formed with an image that defines the gate electrode134A of the gate structure130of the vertical FET device in the first device region R1, and the first capacitor electrode134B of the MIM capacitor device150in the third device region R3. The first layer of conductive material134and the first conformal layer of dielectric material132are patterned using the image of the first cut mask136, as schematically illustrated inFIGS. 9A and 9B.

In particular,FIG. 9Ais a schematic cross-sectional side view of the semiconductor structure ofFIG. 8after patterning the first layer of conductive material134and the first conformal layer of dielectric material132using the first cut mask136to form the gate structure130(comprising the gate dielectric layer132A and the gate electrode134A) in the first device region R1, and the first capacitor electrode134B in the third device region R3.FIG. 9Bis a schematic top plan view (X-Y plane) of the semiconductor structure ofFIG. 9A, andFIG. 9Ais a cross-sectional side view (X-Z plane) of the semiconductor structure taken along line9A-9A inFIG. 9B. The patterning process is performed by etching away exposed portions of the first layer of conductive material134and the first conformal layer of dielectric material132in the second and third device regions R2and R3down the lower insulating spacer125.

As shown inFIGS. 9A and 9B, the etch process results in the formation of the gate structure130of the vertical FET device in the first region R1, wherein the gate structure130comprises the conformal gate dielectric layer132A disposed on the sidewalls of the vertical semiconductor fins111and112, and the gate electrode134A disposed around the sidewalls of the vertical semiconductor fins111and112. In addition, the etch process results in the removal of the portions of the first conformal layer of dielectric material132and the first layer of conductive material134in the second device region R2to expose the vertical semiconductor fins113and114. Further, the etch process results in the patterning of the first capacitor electrode134B comprising the various vertical fin segments E1, E2, E3, and E4. As shown inFIG. 9A, following the etch process, portions of the first conformal layer of dielectric material132which are covered by the first capacitor electrode134B remain in the third device region R3.

A next phase of the semiconductor fabrication process implements an integrated process module to concurrently form the gate structure140(e.g., metal gate structure) of the vertical FET device in the second device region R2and the capacitor insulator layer142B and the second capacitor electrode144B of the MIM capacitor device150in the third device region R3, using a process flow as schematically illustrated inFIGS. 10˜13. In particular, as an initial step,FIG. 10is a schematic cross-sectional side view of the semiconductor structure ofFIG. 9Aafter depositing a second conformal layer of dielectric material142over the surface of the semiconductor structure. The second conformal layer of dielectric material142is subsequently patterned to form the gate dielectric layer142A of the gate structure140of the vertical FET device in the second device region R2, and the capacitor insulator layer142B of the MIM capacitor device150in the third device region R3. In one embodiment, the second conformal layer of dielectric material142is formed of silicon oxide or a high-k dielectric material which is suitable for the given application. In one embodiment, the second conformal layer of dielectric material142is formed with a thickness in a range of about 5 nm or greater (e.g., about 5 nm to about 20 nm), which is thicker than the first conformal layer of dielectric material132that forms the gate dielectric layer132A of the gate structure130of the vertical FET device in the first device region R1.

Next,FIG. 11is a schematic cross-sectional view of the semiconductor structure ofFIG. 10after depositing a second layer of conductive material144over the second conformal layer of dielectric material142. In one embodiment, the second layer of conductive material144is formed of the same or similar material(s) as the first layer of conductive material134which forms the gate electrode134A and the first capacitor electrode134B. For example, the second layer of conductive material144may comprise a metallic material such as tungsten, or any other suitable metallic material such as titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold, etc. In other embodiments, the second layer of conductive material144may be a conductive material including, but not limited to, a doped semiconductor material, a conducting metallic compound material, etc. The second layer of conductive material144may further comprise dopants that are incorporated during or after deposition. The second layer of conductive material144is deposited using a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, sputtering, etc.

FIG. 12is a schematic cross-sectional side view of the semiconductor structure ofFIG. 11after planarizing (e.g., CMP) the surface of the semiconductor structure down to the etch hardmask108-1to remove overburden portions of the second layer of conductive material144and the second conformal layer of dielectric material142, and forming a second cut mask146over the planarized surface of the semiconductor structure. In particular, as shown inFIG. 12, the second cut mask146comprises openings146-1that are aligned with, or substantially overlap, the trench isolation regions120. The planarizing process ofFIG. 12results in patterning the second conformal layer of dielectric material142to concurrently form the gate dielectric layer142A of the gate electrode140of the vertical FET device in the second device region R2and the capacitor insulator layer142B of the MIM capacitor device150in the third device region R3.

FIG. 13is a schematic cross-sectional side view of the semiconductor structure ofFIG. 12after patterning the second layer of conductive material144using an image of the second cut mask146to form trenches144-1in the second layer of conductive material144which define the gate electrode144A in the second device region R2and the second capacitor electrode144B in the third device region R3. In particular, the portions of the second layer of conductive material144that are exposed through the openings146-1of the second cut mask146are anisotropically etched down (e.g., using RIE) to the second conformal layer of dielectric material142to concurrently form the gate electrode144A and the second capacitor electrode144B.

FIGS. 14A and 14Bare schematic views of the semiconductor structure ofFIG. 13after filling the trenches144-1with insulating material to form the insulating regions155which serve to electrically insulate the gate electrodes134A and144A, and the second capacitor electrode144B from surrounding structures.FIG. 14Bis a schematic top plan view (X-Y plane) of the semiconductor structure ofFIG. 14A, andFIG. 14Ais a cross-sectional side view (X-Z plane) of the semiconductor structure taken along line14A-14A inFIG. 14B. In one embodiment, the insulating regions155are formed by blanket depositing a layer of insulation material (e.g., silicon oxide) to fill the trenches144-1with insulating material, followed by a CMP process to remove the overburden portion of the insulating material and planarize the surface of the semiconductor structure down to the etch hardmask108-1, resulting in the semiconductor structure shown inFIGS. 14A and 14B.

As shown inFIGS. 14A and 14B, the patterning of the second layer of conductive material144results in the formation of the gate electrode144A in the second device region R2and the formation of the second capacitor electrode144B in the third device region R3, wherein the second capacitor electrode144B comprises the vertical fin segments E5, E6, E7, E8, and E9. The first and second capacitor electrodes134B and144B comprise comb-like electrode structures with parallel vertical fin segments of the first and second capacitor electrodes134B and144B disposed in an overlapped, interdigitated configuration. In addition, a remaining portion of the second conformal layer of dielectric material142which surrounds the sidewalls of the vertical semiconductor fins113and114serve as the gate dielectric layer142A of the gate structure140of the vertical FET device in the second device region R2, and a remaining portion of the second conformal layer of dielectric material142disposed between the first and second capacitor electrodes134B and144B serves as the capacitor insulator layer142B of the MIM capacitor device150in the third device region R3.

A next phase of the semiconductor fabrication process comprises forming the upper insulating spacer165and the upper source/drain regions162and164of the semiconductor device100as shown inFIGS. 1A and 1B, using a process flow as schematically illustrated inFIGS. 15-18. As an initial step,FIG. 15is a schematic cross-sectional side view of the semiconductor structure ofFIG. 14Aafter recessing upper surfaces of the gate structures130and140, the MIM capacitor device150, and the insulating regions155to a target level that defines a gate length Lg of the vertical FET devices in the first and second device regions R1and R2. The recess process is performed using, for example, an RIE process having an etch chemistry which is suitable to etch the conductive and insulating materials selective to the etch hardmask108-1. In one example embodiment as shown inFIG. 15, the upper surfaces of the gate structures130and140are recessed to a depth that is below an upper surface of the vertical semiconductor fins111,112,113, and114.

Next,FIG. 16is a schematic cross-sectional side view of the semiconductor structure ofFIG. 15after forming the upper insulating spacer165on the recessed surfaces of the gate electrodes130and140, the insulating regions155, and the MIM capacitor device150, and forming the first ILD layer170on the upper insulating spacer165. In one embodiment, the upper insulating spacer165is formed by depositing a layer of dielectric material such as SiO2, SiN, SiBCN or SiOCN, or some other type of low-k dielectric material that is commonly used to form insulating spacers for vertical FET devices. In one embodiment, the upper insulating spacer165can be formed using a directional deposition process in which the dielectric/insulating material is directly deposited on lateral surfaces. In one embodiment, the first ILD layer170is formed of an insulating material, such as a silicon oxide, which has etch selectivity with respect to the material forming the etch hardmask108-1. The first ILD layer170can be formed by blanket depositing a layer of insulating material (e.g., silicon oxide) over the surface of the semiconductor structure, and then planarizing the surface of the semiconductor structure down to the upper surface of the etch hardmask108-1, resulting in the intermediate structure shown inFIG. 16.

Next,FIG. 17is a schematic cross-sectional side view of the semiconductor structure ofFIG. 16after removing the etch hardmask108-1to expose upper surfaces of the vertical semiconductor fins111,112,113, and114on which the upper source/drain regions are epitaxially grown in the first and second device regions R1and R2. The etch hardmask108-1can be removed using any suitable dry or wet etch process with an etch chemistry that is configured to etch the material of the hardmask108-1selective to the materials of the first ILD layer170and the vertical semiconductor fins111,112,113, and114. Following removal of the etch hardmask108-1, the upper source/drain regions162and164are epitaxially grown on the exposed upper portions of the vertical semiconductor fins111,112,113, and114in the first and second device regions R1and R2, resulting in the intermediate semiconductor structure schematically illustrated inFIG. 18.

In one embodiment, the upper source/drain regions162and164are formed by epitaxially growing doped semiconductor layers (e.g., doped SiGe) on the exposed upper portions of the vertical semiconductor fins111,112,113, and114using known selective growth techniques in which the epitaxial material is not grown on the exposed surface of the first ILD layer170. The type of epitaxial semiconductor material that is used to form the upper source/drain regions162and164will vary depending on various factors including, but are not limited to, the type of material of the vertical semiconductor fins111,112,113, and114, the device type (e.g., n-type or p-type) of the vertical FET devices to be formed in the device regions R1and R2, etc.

In some embodiments, the source/drain regions162and164may be in-situ doped during epitaxial growth by adding a dopant gas to the source deposition gas (i.e., the Si-containing gas). Exemplary dopant gases may include a boron-containing gas such as BH3for pFETs or a phosphorus or arsenic containing gas such as PH3or AsH3for nFETs, wherein the concentration of impurity in the gas phase determines its concentration in the deposited film. In an alternate embodiment, the upper source/drain regions162and164can be doped ex-situ using, for example, ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, etc. In one non-limiting embodiment, the doping concentration can range from about 1×1019/cm3to about 4×1021/cm3.

Following the formation of the semiconductor structure shown inFIG. 18, any known sequence of processing steps can be implemented to fabricate the semiconductor integrated circuit device as shown inFIGS. 1A and 1B, the details of which are not needed to understand embodiments of the invention. Briefly, by way of example, referring back toFIG. 1A, after forming the upper source/drain regions162and164, a FEOL process and MOL (middle of the line) process are continued to (i) form the second ILD layer180, (ii) pattern the second ILD layer180to form trenches and/or via openings to expose the upper source/drain regions162and164, and to (iii) fill the trenches and/or via openings with conductive material to form the vertical source/drain contacts182and184.

In addition, vertical contacts (not shown) to the lower source/drain regions104-1and104-2and the gate structures130and140in the device regions R1and R2, and the vertical contacts186A and186B (FIG. 1B) to the respective first and second capacitor electrodes134B and144B in the third device region R3can be formed either concurrently, or separately, with the formation of the vertical source/drain contacts182and184using the same or similar fabrication methods. Following formation of the vertical device contacts, a BEOL (back end of line) interconnect structure is formed to provide connections to/between the vertical FET devices, the MIM capacitor(s), and other active or passive devices that are formed as part of the FEOL layer in the different device regions.

It is to be understood that the methods discussed herein for integrating MIM capacitor formation as part of a FEOL process flow for fabricating vertical FET devices can be incorporated within semiconductor processing flows for fabricating other types of semiconductor devices and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.