DISPLAY DEVICE AND MOBILE ELECTRONIC DEVICE INCLUDING THE SAME

According to an embodiment, a display device may include a display panel, a plurality of flexible films attached to a side of the display panel, and a circuit board electrically connected to the display panel through the flexible films. Each of the flexible films may include a first display driver IC (DDI) and a second DDI spaced apart from each other on a surface of the flexible film, a first common line electrically connecting an input pad and the first DDI, a second common line branching from the first common line and extending under the first DDI to bypass the first DDI, a third common line electrically connecting the second common line and the second DDI, a first independent line electrically connecting the input pad and the first DDI, and a second independent line electrically connecting the input pad and the second DDI.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2023-0131133 filed on Sep. 27, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

The disclosure relates to a display device and a mobile electronic device including the same.

2. Description of the Related Art

As the information society develops, demands for display devices for displaying images are increasing in various forms. For example, display devices are applied to various electronic devices such as smartphones, digital cameras, notebook computers, navigation devices, and smart televisions.

Display devices are increasingly equipped with display panels with high resolution and high pixels per inch (PPI) specifications according to user demand. Accordingly, research and development are being conducted on driving circuits for driving display panels. For example, chip on film (COF) package technology having a multi-chip structure has been proposed for display panels of about 200 PPI or more. The COF package technology having the multi-chip structure places multiple integrated circuit (ICs) on a flexible film to place many driver ICs in a limited space (panel width).

However, the COF package technology having the multi-chip structure has difficulty in securing a pad pitch, thus resulting in high process difficulty and reduced yield and reliability.

SUMMARY

Aspects of the disclosure provide a display device which can increase yield and reliability by readily securing a pad pitch while placing multiple integrated circuits on a flexible film and a mobile electronic device including the display device.

According to an embodiment of the disclosure, a display device may include a display panel, a plurality of flexible films attached to a side of the display panel, and a circuit board electrically connected to the display panel through the plurality of flexible films. Each of the plurality of flexible films may include a first display driver IC (DDI) and a second DDI spaced apart from each other on a surface of the flexible film, a first common line electrically connecting an input pad and the first DDI, a second common line branching from the first common line and extending under the first DDI to bypass the first DDI, a third common line electrically connecting the second common line and the second DDI, a first independent line electrically connecting the input pad and the first DDI, and a second independent line electrically connecting the input pad and the second DDI.

Each of the plurality of flexible films may include a first metal layer adjacent to a front surface of the flexible film and a second metal layer adjacent to a rear surface of the flexible film, and the first DDI and the second DDI may be disposed on the front surface of the flexible film.

In each of the plurality of flexible films, the input pad may be disposed adjacent to a side of the flexible film and may be disposed on the front surface of the flexible film, an output pad may be disposed adjacent to another side of the flexible film and may be disposed on the rear surface of the flexible film, and the first DDI may be disposed between the input pad and the second DDI.

In each of the plurality of flexible films, the first common line and the third common line may be disposed in the first metal layer, and the second common line may be disposed in the second metal layer.

In each of the plurality of flexible films, the first common line and the third common line may be electrically connected through a plurality of through holes penetrating portions of the flexible film to connect the first metal layer and the second metal layer.

In each of the plurality of flexible films, the plurality of through holes may include a first through hole in which the first common line and an end of the second common line are electrically connected, and a second through hole in which the third common line and another end of the second common line are electrically connected.

In each of the plurality of flexible films, the first independent line may be electrically connected to the first DDI through the first metal layer.

In each of the plurality of flexible films, the second independent line may be electrically connected to the second DDI through the first metal layer and the second metal layer.

Each of the plurality of flexible films may include a plurality of bypass lines disposed on opposing front and rear surfaces of the flexible film to bypass the first DDI and the second DDI.

In each of the plurality of flexible films, the first DDI may drive a plurality of first subpixels disposed in a first display area of the display panel, the second DDI may drive a plurality of second subpixels disposed in a second display area adjacent to the first display area, and a circuit included in the first DDI and a circuit included in the second DDI may be the same.

Each of the plurality of flexible films may include a first metal layer adjacent to a front surface of the flexible film, wherein the first DDI and the second DDI may be disposed on the front surface of the flexible film.

In each of the plurality of flexible films, the input pad may be disposed adjacent to a side of the flexible film and may be disposed on the front surface of the flexible film, an output pad may be disposed adjacent to another side of the flexible film and may be disposed on a rear surface of the flexible film, and the first DDI may be disposed between the input pad and the second DDI.

The first through third common lines and the first and second independent lines in each of the plurality of flexible films may be disposed in the first metal layer.

The second common line in each of the plurality of flexible films may pass between a plurality of bumps of the first DDI attached to the front surface of the flexible film.

The second independent line in each of the plurality of flexible films may pass between a plurality of bumps of the first DDI attached to the front surface of the flexible film.

According to an embodiment of the disclosure, a mobile electronic device may include a display panel, a plurality of flexible films attached to a side of the display panel, and a circuit board electrically connected to the display panel through the plurality of flexible films. Each of the plurality of flexible films may include a first DDI and a second DDI spaced apart from each other on a surface of the flexible film, a first common line electrically connecting an input pad and the first DDI, a second common line branching from the first common line and extending under the first DDI to bypass the first DDI, a third common line electrically connecting the second common line and the second DDI, a first independent line electrically connecting the input pad and the first DDI, and a second independent line electrically connecting the input pad and the second DDI.

Each of the plurality of flexible films may include a first metal layer adjacent to a front surface of the flexible film and a second metal layer adjacent to a rear surface of the flexible film, and the first DDI and the second DDI may be disposed on the front surface of the flexible film.

In each of the plurality of flexible films, the input pad may be disposed adjacent to a side of the flexible film and may be disposed on the front surface of the flexible film, an output pad may be disposed adjacent to another side of the flexible film and may be disposed on the rear surface of the flexible film, and the first DDI may be disposed between the input pad and the second DDI.

In each of the plurality of flexible films, the first common line and the third common line may be disposed in the first metal layer, and the second common line may be disposed in the second metal layer.

Each of the plurality of flexible films may be penetrated by a plurality of through holes in which the first common line and the third common line may be electrically connected and in which the first metal layer and the second metal layer may be electrically connected.

However, aspects of the disclosure may not be restricted to the one set forth herein. The above and other aspects of the disclosure will become more apparent to one of ordinary skill in the art to which the disclosure pertains by referencing the detailed description of the disclosure given below.

DETAILED DESCRIPTION OF THE EMBODIMENTS

When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Further, the X-axis, the Y-axis, and the Z-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z axes, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another.

For the purposes of this disclosure, “at least one of A and B” may be construed as A only, B only, or any combination of A and B. Also, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

FIG.1is an exploded perspective view of a display device10according to an embodiment.

Referring toFIG.1, the display device10according to the embodiment may be applied to mobile electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). The display device10according to the embodiment may be applied as a display portion of a television, a notebook computer, a monitor, a billboard, or an Internet of things (IoT) device. The display device10according to the embodiment may be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). The display device10according to the embodiment may be applied to a dashboard of a vehicle, a center fascia of a vehicle, a center information display (CID) disposed on a dashboard of a vehicle, a room mirror display replacing side mirrors of a vehicle, or a display disposed on the back of a front seat as for entertainment for rear-seat passengers of a vehicle.

Referring toFIG.1, the display device10according to the embodiment may include an upper set cover100, a lower set cover102, a display panel110, source driving circuits121, flexible films122, source circuit boards140, first cables150, a control circuit board160, a power circuit171, and a timing control circuit170.

In the specification, the terms “above”, “top”, and “upper surface” refer to a direction in which a second substrate112may be disposed with respect to a first substrate111of the display panel110, for example, a third direction (Z-axis direction), and the terms “below,” “bottom”, and “lower surface” may be a direction opposite to the third direction (Z-axis direction). The terms “left,” “right,” “upper” and “lower” refer to directions when the display panel110may be viewed in a plan view. For example, “left” refers to a first direction (X-axis direction), “right” refers to a direction opposite to the first direction (X-axis direction), “upper” refers to a second direction (Y-axis direction), and “lower” refers to a direction opposite to the second direction (Y-axis direction),

The upper set cover100may be placed to cover edges of an upper surface of the display panel110. The upper set cover100may cover a non-display area of the display panel110excluding a display area. In case that the source circuit boards140, the first cables150, and the control circuit board160are disposed under the display panel110due to the bending of the flexible films122, the lower set cover102may cover the source circuit boards140, the first cables150, and the control circuit board160.

A length of the lower set cover102in the second direction (Y-axis direction) may be greater than a length of a bottom chassis180in the second direction (Y-axis direction) or may be substantially equal to the length of the bottom chassis180in the second direction (Y-axis direction). The upper set cover100and the lower set cover102may be made of plastic or metal or may include both plastic and metal.

The display panel110may be rectangular in a plan view. For example, the display panel110may have a rectangular planar shape having long sides extending in the first direction (X-axis direction) and short sides extending in the second direction (Y-axis direction) as illustrated inFIG.2. Each corner where a long side extending in the first direction (X-axis direction) meets a short side extending in the second direction (Y-axis direction) may be right-angled or may be rounded with a curvature (e.g., predetermined or selectable curvature). The planar shape of the display panel110may not be limited to the rectangular shape and may also be other polygonal shapes, a circular shape, or an oval shape.

Although the display panel110may be formed approximately flat inFIG.1, the specification may not be limited to this case. The display panel110may also include a curved portion bent with a curvature (e.g., predetermined or selectable curvature),

The display panel110may include the first substrate111and the second substrate112. The second substrate112may face a first surface of the first substrate111. The first substrate111and the second substrate112may be rigid or flexible. The first substrate111may be made of glass or plastic. The second substrate112may be made of glass, plastic, an encapsulation film, or a barrier film. The second substrate112may be omitted. In case that the first substrate111and the second substrate112may be made of plastic, the plastic may be polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. The encapsulation film or the barrier film may be a film in which multiple inorganic layers may be stacked on each other.

The display panel110may be an organic light emitting display panel using an organic light emitting diode including a first electrode, an organic light emitting layer and a second electrode, an inorganic light emitting display panel using an inorganic light emitting diode including a first electrode, an inorganic semiconductor layer and a second electrode, or a quantum dot light emitting display panel including a quantum dot light emitting diode including a first electrode, a quantum dot light emitting layer and a second electrode.

The display panel110may be described below as an organic light emitting display panel including a thin-film transistor layer TFTL, a light emitting element layer EML, a filler FL, a light wavelength conversion layer QDL, and a color filter layer CFL between the first substrate111and the second substrate112. The first substrate111may be a thin-film transistor substrate on which the thin-film transistor layer TFTL, the light emitting element layer EML and a thin-film encapsulation layer TFEL may be formed, the second substrate112may be a color filter substrate on which the light wavelength conversion layer QDL and the color filter layer CFL may be formed, and the filler FL may be disposed between the thin-film encapsulation layer TFEL of the first substrate111and the light wavelength conversion layer QDL of the second substrate112.

The second substrate112of the display panel110may be omitted, and a thin-film encapsulation layer may be disposed on the light emitting element layer EML. The filler FL may be omitted, and the light wavelength conversion layer QDL and the color filter layer CFL may be disposed on the thin-film encapsulation layer.

A side of each of the flexible films122may be disposed on the first surface of the first substrate111of the display panel110, and another side may be attached onto a surface of one of the source circuit boards140. Specifically, since the first substrate111may be larger in size than the second substrate112, a side of the first substrate111may be exposed without being covered by the second substrate112. The flexible films122may be attached to the exposed side of the first substrate111which may not be covered by the second substrate112. Each of the flexible films122may be attached onto the first surface of the first substrate111and the surface of one of the source circuit boards140by using an anisotropic conductive film.

Each of the flexible films122may be a flexible film such as a tape carrier package or a chip on film. The flexible films122may be bent toward the bottom of the first substrate111. Although eight flexible films122may be attached onto the first substrate111of the display panel110inFIG.1, the number of flexible films122may not be limited to eight in the specification.

The source driving circuits121may be disposed on a surface of each of the flexible films122. The source driving circuits121may be formed as integrated circuits. Each of the source driving circuits121converts digital video data into analog data voltages according to a source control signal of the timing control circuit170and supplies the analog data voltages to data lines of the display panel110through a flexible film122. The source driving circuits121may be referred to as display driver ICs (DDIs).

The display panel110may include scan lines intersecting the data lines and pixels disposed in areas defined by the data lines and the scan lines. The scan lines may receive scan signals from a scan driver formed on the display panel110. The scan driver may include multiple thin-film transistors and generate scan signals according to a scan control signal of the timing control circuit170. Each of the pixels may be electrically connected to at least one data line and at least a scan line and may receive a data voltage of the data line in case that a scan signal is supplied to the scan line.

Each of the source circuit boards140may be electrically connected to the control circuit board160through the first cables150. Each of the source circuit boards140may include first connectors151afor connection to the first cables150. The source circuit boards140may be flexible printed circuit boards or printed circuit boards. The first cables150may be flexible cables.

The control circuit board160may be electrically connected to the source circuit boards140through the first cables150. To this end, the control circuit board160may include second connectors152for connection to the first cables150.

Although four first cables150connect the source circuit boards140and the control circuit board160inFIG.1, the number of first cables150may not be limited to four in the specification. Although two source circuit boards140are illustrated inFIG.1, the number of source circuit boards140may not be limited to two in the specification.

In case that the number of flexible films122is small, the source circuit boards140may be omitted. The flexible films122may be connected (e.g., directly connected) to the control circuit board160.

The timing control circuit170may be disposed on a surface of the control circuit board160. The timing control circuit170may be formed as an integrated circuit. The timing control circuit170may receive digital video data and timing signals from a system on chip of a system circuit board and generate a source control signal for controlling the timings of the source driving circuits121according to the timing signals.

The power circuit171may be disposed on the surface of the control circuit board160. The power circuit171may be formed as an integrated circuit. The power circuit171may generate voltages desirable for driving the display panel110from main power received from the system circuit board and supply the generated voltages to the display panel110. For example, the power circuit171may generate a high-potential voltage, a low-potential voltage and an initialization voltage for driving organic light emitting elements and supply the generated voltages to the display panel110. The power circuit171may generate and supply driving voltages for driving the source driving circuits121, the timing control circuit170, etc.

The system on chip may be mounted on the system circuit board electrically connected to the control circuit board160through a flexible cable and may be formed as an integrated circuit. The system on chip may be a processor of a smart television, a central processing unit (CPU) or graphics card of a computer or notebook, or an application processor of a smartphone or tablet PC. The system circuit board may be a flexible printed circuit board or a printed circuit board.

Although the display device10according to the embodiment may be illustrated as a medium/large display device including multiple source driving circuits121inFIG.1, the specification may not be limited to this case. For example, the display device10according to the embodiment may also be a small display device including one source driving circuit121. The flexible films122, the source circuit boards140, and the first cables150may be omitted. The source driving circuits121and the timing control circuit170may be integrated into one integrated circuit and then attached onto one flexible circuit board or attached onto the first substrate111of the display panel110. Examples of the medium/large display device include monitors and televisions, and examples of the small display device include smartphones and tablet PCs.

FIG.2is a bottom view illustrating an example of the display panel110in case that the flexible films122inFIG.1are unfolded.FIG.3is a bottom view illustrating an example of the display panel110to which the bottom chassis180may be coupled in case that the flexible films122inFIG.1are bent toward the bottom of the bottom chassis180.

Referring toFIGS.2and3, the first surface of the first substrate111and a first surface of the second substrate112may face each other. A pixel array layer113(seeFIG.4) may be disposed between the first surface of the first substrate111and the first surface of the second substrate112. The pixel array layer113may include multiple pixels PX1through PX3which emit light.

A heat dissipation film (not illustrated) may be disposed on a second surface of the first substrate111. The heat dissipation film may include a metal layer having high thermal conductivity, such as graphite, silver (Ag), copper (Cu) or aluminum (Al).

The flexible films122may be bent toward the bottom of the bottom chassis180and attached to the source circuit boards140on a surface of the bottom chassis180. The source circuit boards140and the control circuit board160may be disposed on the surface of the bottom chassis180and may be electrically connected to each other through the first cables150.

The timing control circuit170and the power circuit171may be disposed on the control circuit board160.

FIG.4is a schematic cross-sectional view illustrating an example of the first substrate111, the second substrate112, and the pixel array layer113of the display panel110.

Referring toFIG.4, the display panel110may include the first substrate111, the second substrate112, and the pixel array layer113. The pixel array layer113may include the thin-film transistor layer TFTL and the light emitting element layer EML.

A buffer layer302may be formed on a surface of the first substrate111which faces the second substrate112. The buffer layer302may be formed on the first substrate111to protect thin-film transistors335and light emitting elements from moisture introduced through the first substrate111which may be vulnerable to moisture penetration. The buffer layer302may be composed of multiple inorganic layers stacked alternately on each other. For example, the buffer layer302may be a multilayer in which one or more inorganic layers selected from a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, and SiON may be alternately stacked on each other. The buffer layer302may also be omitted.

The thin-film transistor layer TFTL may be formed on the buffer layer302. The thin-film transistor layer TFTL includes the thin-film transistors335, a gate insulating layer336, an interlayer insulating film337, a protective layer338, and a planarization layer339.

The thin film transistors335may be formed on the buffer layer302. Each of the thin-film transistors335includes an active layer331, a gate electrode332, a source electrode333, and a drain electrode334. InFIG.4, each of the thin-film transistors335may be formed as a top-gate type in which the gate electrode332may be located above the active layer331. However, it should be noted that the specification may not be limited to this case. For example, each of the thin-film transistors335may also be formed as a bottom-gate type in which the gate electrode332may be located below the active layer331or a double-gate type in which the gate electrode332may be located both above and below the active layer331.

The active layers331may be formed on the buffer layer302. The active layers331may be made of a silicon-based semiconductor material or an oxide-based semiconductor material. A light shielding layer may be formed between the buffer layer302and the active layers331to block external light from entering the active layers331.

The gate insulating layer336may be formed on the active layers331. The gate insulating layer336may be an inorganic layer, for example, a SiOxlayer, a SiN, layer, or a multilayer composed of these layers.

The gate electrodes332and gate lines may be formed on the gate insulating layer336. Each of the gate electrodes332and the gate lines may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (AI), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), alloys thereof, or a combination thereof.

The interlayer insulating film337may be formed on the gate electrodes332and the gate lines. The interlayer insulating film337may be an inorganic layer, for example, a SiOxlayer, a SiN, layer, or a multilayer composed of these layers.

The source electrodes333, the drain electrodes334, and data lines may be formed on the interlayer insulating film337. Each of the source electrodes333and the drain electrodes334may be electrically connected to an active layer331through a contact hole penetrating the gate insulating layer336and the interlayer insulating film337. Each of the source electrodes333, the drain electrodes334and the data lines may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), alloys thereof, or a combination thereof.

The protective layer338for insulating the thin-film transistors335may be formed on the source electrodes333, the drain electrodes334, and the data lines. The protective layer338may be an inorganic layer, for example, a SiO, layer, a SiN, layer, or a multilayer composed of these layers.

The planarization layer339may be formed on the protective layer338to planarize steps due to the thin-film transistors335. The planarization layer339may be made of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or a combination thereof.

The light emitting element layer EML may be formed on the thin-film transistor layer TFTL. The light emitting element layer EML includes the light emitting elements and a pixel defining layer344.

The light emitting elements and the pixel defining layer344may be formed on the planarization layer339. The light emitting elements may be organic light emitting devices. Each of the light emitting elements may include an anode341, a light emitting layer342, and a cathode343.

The anodes341may be formed on the planarization layer339. The anodes341may be electrically connected to the drain electrodes334of the thin-film transistors335through contact holes penetrating the protective layer338and the planarization layer339.

The pixel defining layer344may be formed on the planarization layer339and may cover edges of the anodes341to define pixels. For example, the pixel defining layer344may serve as a pixel defining layer for defining subpixels PX1through PX3. Each of the subpixels PX1through PX3may be an area in which the anode341, the light emitting layer342and the cathode343may be sequentially stacked on each other so that holes from the anode341and electrons from the cathode343may combine together in the light emitting layer342to emit light.

The light emitting layer342may be formed on the anodes341and the pixel defining layer344. The light emitting layer342may be an organic light emitting layer. The light emitting layer342may emit light having a short wavelength, such as blue light or ultraviolet light. The blue light may have a peak wavelength range of about 450 to about 490 nm, and the ultraviolet light may have a peak wavelength range of less than about 450 nm. The light emitting layer342may be a common layer common to all of the subpixels PX1through PX3. The display panel110may include the light wavelength conversion layer QDL for converting short-wavelength light such as blue light or ultraviolet light emitted from the light emitting layer342into red light, green light and blue light and the color filter layer CFL for transmitting each of the red light, green light and the blue light.

The light emitting layer342may include a hole transporting layer, a light emitting layer, and an electron transporting layer. The light emitting layer342may be formed in a tandem structure of two or more stacks. A charge generating layer may be formed between the stacks.

The cathode343may be formed on the light emitting layer342. The cathode343may be formed to cover the light emitting layer342. The cathode343may be a common layer common to all pixels.

The light emitting element layer EML may be formed as a top emission type which emits light toward the second substrate112, for example, in an upward direction. The anodes341may be made of a metal material having high reflectivity, such as a stacked structure (Ti/Al/Ti) of aluminum and titanium, a stacked structure (ITO/Al/ITO) of aluminum and indium tin oxide, an APC alloy, or a stacked structure (ITO/APC/ITO) of an APC alloy and indium tin oxide. The APC alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). The cathode343may be made of a transparent conductive material (TCO) that can transmit light, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag) or an alloy of Mg and Ag. In case that the cathode343is made of a semi-transmissive conductive material, light output efficiency may be increased by a microcavity.

An encapsulation layer345may be formed on the light emitting element layer EML. The encapsulation layer345serves to prevent oxygen or moisture from permeating into the light emitting layer342and the cathode343. To this end, the encapsulation layer345may include at least one inorganic layer. The inorganic layer may be made of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, or a combination thereof. The encapsulation layer345may further include at least one organic layer. The organic layer may be formed to a sufficient thickness to prevent particles from penetrating the encapsulation layer345and entering the light emitting layer342and the cathode343. The organic layer may include any one of epoxy, acrylate, urethane acrylate, or a combination thereof.

The color filter layer CFL may be disposed on a surface of the second substrate112which faces the first substrate111. The color filter layer CFL may include a black matrix360and color filters370.

The black matrix360may be formed on the surface of the second substrate112. The black matrix360may not overlap the subpixels PX1through PX3and may overlap the pixel defining layer344. The black matrix360may include black dye capable of blocking light or an opaque metal material.

The color filters370may overlap the subpixels PX1through PX3. A first color filter371may overlap a first subpixel PX1, a second color filter372may overlap a second subpixel PX2, and a third color filter373may overlap a third subpixel PX3. The first color filter371may be a first-color light transmitting filter that transmits light of a first color, the second color filter372may be a second-color light transmitting filter that transmits light of a second color, and the third color filter373may be a third-color light transmitting filter that transmits light of a third color. For example, the first color may be red, the second color may be green, and the third color may be blue, but the specification may not be limited thereto. The peak wavelength range of red light transmitted through the first color filter371may be in a range of about 620 to about 750 nm, the peak wavelength range of green light transmitted through the second color filter372may be in a range of about 500 to about 570 nm, and the peak wavelength range of blue light transmitted through the third color filter373may be in a range of about 450 to about 490 nm.

Edges of two adjacent color filters may overlap the black matrix360. Therefore, the black matrix360can prevent color mixing that occurs in case that light emitted from the light emitting layer342of any one subpixel travels to a color filter of an adjacent subpixel.

An overcoat layer may be formed on the color filters370to planarize steps due to the color filters370and the black matrix360. The overcoat layer may also be omitted.

The light wavelength conversion layer QDL may be disposed on the color filter layer CFL. The light wavelength conversion layer QDL may include a first capping layer351, a first wavelength conversion layer352, a second wavelength conversion layer353, a third wavelength conversion layer354, a second capping layer355, an interlayer organic film356, and a third capping layer357.

The first capping layer351may be disposed on the color filter layer CFL. The first capping layer351may prevent moisture or oxygen from permeating into the first wavelength conversion layer352, the second wavelength conversion layer353and the third wavelength conversion layer354from the outside through the color filter layer CFL. The first capping layer351may be made of an inorganic layer such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, or a combination thereof.

The first wavelength conversion layer352, the second wavelength conversion layer353and the third wavelength conversion layer354may be disposed on the first capping layer351.

The first wavelength conversion layer352may overlap the first subpixel PX1. The first wavelength conversion layer352may convert short-wavelength light such as blue light or ultraviolet light emitted from the light emitting layer342of the first subpixel PX into light of the first color. To this end, the first wavelength conversion layer352may include a first base resin, first wavelength shifters, and first scatterers.

The first base resin may be a material having high light transmittance and superior dispersion characteristics for the first wavelength shifters and the first scatterers. For example, the first base resin may include an organic material such as epoxy resin, acrylic resin, cardo resin, imide resin, or a combination thereof.

The first wavelength shifters may convert or shift the wavelength range of incident light. The first wavelength shifters may be quantum dots, quantum rods, or phosphors. In case that the first wavelength shifters may be quantum dots, they may have a specific band gap according to their composition and size as semiconductor nanocrystalline materials. Thus, the first wavelength shifters may absorb incident light and then emit light having a unique wavelength. The first wavelength shifters may have a core-shell structure including a core containing a nanocrystal and a shell surrounding the core. Examples of the nanocrystal that forms the core include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, and combinations thereof. The shell may serve as a protective layer for maintaining semiconductor characteristics by preventing chemical denaturation of the core and/or as a charging layer for giving electrophoretic characteristics to the quantum dot. The shell may be a single layer or a multilayer. The shell may be, for example, a metal or non-metal oxide, a semiconductor compound, or a combination thereof.

The first scatterers may have a refractive index different from that of the first base resin and may form an optical interface with the first base resin. For example, the first scatterers may be light scattering particles. For example, the first scatterers may be metal oxide particles such as titanium oxide (TiO2), silicon oxide (SiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O)3), zinc oxide (ZnO), tin oxide (SnO2), or a combination thereof. The first scatterers may be organic particles such as acrylic resin or urethane resin.

The first scatterers may scatter incident light in random directions without substantially changing the wavelength of the light transmitted through the first wavelength conversion layer352. Accordingly, the length of the path of the light transmitted through the first wavelength conversion layer352may be increased, thereby increasing the color conversion efficiency of the first wavelength shifters.

The first wavelength conversion layer352may overlap the first color filter371. Therefore, a portion of short-wavelength light such as blue light or ultraviolet light provided from the first subpixel PX1may pass through the first wavelength conversion layer352as is without being converted into light of the first color by the first wavelength shifters. However, the short-wavelength light such as blue light or ultraviolet light incident on the first color filter371without being converted by the first wavelength conversion layer352cannot pass through the first color filter371. On the other hand, light of the first color into which the short-wavelength light has been converted by the first wavelength conversion layer352can pass through the first color filter371and proceed toward the second substrate112.

The second wavelength conversion layer353may overlap the second subpixel PX2. The second wavelength conversion layer353may convert short-wavelength light such as blue light or ultraviolet light emitted from the light emitting layer342of the second subpixel PX2into light of the second color. To this end, the second wavelength conversion layer353may include a second base resin, second wavelength shifters, and second scatterers. The second base resin, the second wavelength shifters and the second scatterers of the second wavelength conversion layer353may be substantially the same as those of the first wavelength conversion layer353, and thus a detailed description thereof may be omitted. In case that the first wavelength shifters and the second wavelength shifters are quantum dots, a diameter of the second wavelength shifters may be smaller than that of the first wavelength shifters.

The second wavelength conversion layer353may overlap the second color filter372. Therefore, a portion of short-wavelength light such as blue light or ultraviolet light provided from the second subpixel PX2can pass through the second wavelength conversion layer353as is without being converted into light of the second color by the second wavelength shifters. However, the short-wavelength light such as blue light or ultraviolet light incident on the second color filter372without being converted by the second wavelength conversion layer353cannot pass through the second color filter372. On the other hand, light of the second color into which the short-wavelength light has been converted by the second wavelength conversion layer353can pass through the second color filter372and proceed toward the second substrate112.

The third wavelength conversion layer354may overlap the third subpixel PX3. The third wavelength conversion layer354may convert short-wavelength light such as blue light or ultraviolet light emitted from the light emitting layer342of the third subpixel PX3into light of the third color. To this end, the third wavelength conversion layer354may include a third base resin and third scatterers. The third base resin and the third scatterers of the third wavelength conversion layer354may be substantially the same as those of the first wavelength conversion layer352, and thus a detailed description thereof is omitted.

The third wavelength conversion layer354may overlap the third color filter373. Therefore, short-wavelength light such as blue light or ultraviolet light provided from the third subpixel PX3can pass through the third wavelength conversion layer354as is, and the light that passes through the third wavelength conversion layer354can pass through the third color filter373and proceed toward the second substrate112.

The second capping layer355may be disposed on the first wavelength conversion layer352, the second wavelength conversion layer353, the third wavelength conversion layer354, and the first capping layer351exposed without being covered by the wavelength conversion layers352through354. The second capping layer355prevents moisture or oxygen from permeating into the first wavelength conversion layer352, the second wavelength conversion layer353and the third wavelength conversion layer354from the outside. The second capping layer355may be made of an inorganic layer such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, or a combination thereof.

The interlayer organic film356may be disposed on the second capping layer355. The interlayer organic film356may be a planarization layer for planarizing steps due to the wavelength conversion layers352through354. The interlayer organic film356may be made of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or a combination thereof.

The third capping layer357may be disposed on the interlayer organic film356. The third capping layer357may be made of an inorganic layer such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, or a combination thereof.

The filler FL may be disposed between the thin-film encapsulation layer TFEL disposed on the first substrate111and the third capping layer357disposed on the second substrate112. The filler FL may be made of a material having a buffer function. For example, the filler FL may be made of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or a combination thereof.

A sealing material for bonding the first substrate111and the second substrate112together may be disposed in the non-display area of the display panel110. When seen in a plan view, the filler FL may be surrounded by the sealing material. The sealing material may be glass frit or a sealant.

According to the embodiment illustrated inFIG.4, the first through third subpixels PX1through PX3may emit short-wavelength light such as blue light or ultraviolet light. Light of the first subpixel PX1may be converted into light of the first color by the first wavelength conversion layer352and then output through the first color filter371. Light of the second subpixel PX2may be converted into light of the second color by the second wavelength conversion layer353and then output through the second color filter372. Light of the third subpixel PX3may be output through the third wavelength conversion layer354and the third color filter373. Therefore, white light can be output.

According to the embodiment illustrated inFIG.4, each of the subpixels PX1through PX3may be formed as a top emission type which emits light toward the second substrate112, for example, in the upward direction. Therefore, the heat dissipation film including an opaque material such as graphite or aluminum may be disposed on another surface of the first substrate111.

FIG.5is a layout view of a front portion of a flexible film122according to an embodiment.FIG.6is a layout view of a rear portion of the flexible film122according to the embodiment.

Referring toFIGS.5and6, the display device according to the embodiment may include multiple flexible films122attached to a side of the display panel110, and multiple DDIs may be disposed on each flexible film122. For example, a first DDI511and a second DDI512may be disposed on one flexible film122.

According to an embodiment, each flexible film122may include the first DDI511and the second DDI512spaced apart from each other on a surface of the flexible film122. Each of the first DDI511and the second DDI512drives a portion of the display area of the display panel110. For example, the first DDI511drives first subpixels disposed in a first display area of the display panel110. The second DDI512drives second subpixels disposed in a second display area adjacent to the first display area.

According to an embodiment, the first DDI511and the second DDI512may have the same circuitry. For example, a circuit included in the first DDI511and a circuit included in the second DDI512may be the same. For example, the first DDI511and the second DDI512may be parts that drive different display areas of the display panel110but have the same circuitry. Therefore, signals or power input to the first DDI511may be the same as signals or power input to the second DDI512. Signals or power output from the first DDI511may be the same as signals or power output from the second DDI512. However, the driving timing of the first DDI511may be different from the driving timing of the second DDI512. Therefore, some of the signals input to the first DDI511may be independent of the signals input to the second DDI512.

According to an embodiment, each flexible film122may include common lines for supplying signals or power to be commonly input to the first DDI511and the second DDI512disposed on the flexible film122. Each flexible film122may include independent lines for supplying signals or power to be independently input to the first DDI511and the second DDI512disposed on the flexible film122. In the specification, the term “common line” may be replaced with a term such as, but not limited to “first line”. In the specification, the term “independent line” may be replaced with a term such as, but not limited to, “second line”.

According to an embodiment, the power or signals input to each of the first DDI511and the second DDI512through lines (i.e., common lines or independent lines) provided in each flexible film122may include IC logic power, gamma power, sensing reference power, a clock signal, option signals, and control signals. Among these, the gamma power, the sensing reference power, and the clock signal may be power or signals commonly input to the first DDI511and the second DDI512. Such common power or common signals may be input to the first DDI511and the second DDI512through common lines provided in each flexible film122. In an electronic device according to an embodiment, common signals or power among the signals or power input to multiple DDIs (e.g., the first DDI511and the second DDI512) disposed on each flexible film122may be transmitted through a line. Therefore, the number of lines and pads in the flexible film122can be reduced.

The structures and forms of common lines according to an embodiment will now be described in detail.

According to an embodiment, each flexible film122includes the first DDI511and the second DDI512, and the first DDI511and the second DDI512may be spaced apart from each other. The first DDI511may be disposed between an input pad522of the flexible film122and the second DDI512.

In the flexible film122, the input pad522may be disposed on a side of the flexible film122, and output pads622may be disposed on another side of the flexible film122.

The input pad522of the flexible film122receives power or signals to be input to the first DDI511and the second DDI512. Bypass input pads521may be disposed on both sides of the input pad522, respectively. The bypass input pads521may receive signals that bypass the flexible film122without being input to the first DDI511and the second DDI512.

The output pads622of the flexible film122receive signals or power output from the first DDI511and the second DDI512and transmit the received signals or power to the display panel110. Bypass output pads621may be respectively disposed on both sides of each of the output pads622. The bypass output pads621may transmit signals that bypass the flexible film122without being input to the first DDI511and the second DDI512.

According to an embodiment, one or more common lines5221and one or more independent lines5223and5222may be disposed between the input pad522and the first DDI511and/or between the input pad522and the second DDI512.

According to an embodiment, the common lines5221may include first common lines5221a,second common lines5221b,and third common lines5221c.Of the independent lines5223and5222, the second independent line5222may include three portions5222a,5222b,and5222c.

The first common lines5221amay be disposed between the input pad522and the first DDI511and connect the input pad522and the first DDI511. The second common lines5221bbranch from the first common lines5221aand extend under the first DDI511to bypass the first DDI511. The third common lines5221cmay be electrically connected to the second common lines5221band connect the second common lines5221band the second DDI512.

The first independent line5223may be disposed between the input pad522and the first DDI511and may connect the input pad522and the first DDI511. The second independent line5222may be disposed between the input pad522and the second DDI512and may connect the input pad522and the second DDI512. A portion (5222b) of the second independent line5222may extend to bypass the bottom of the first DDI511.

As illustrated inFIGS.5and6, the flexible film122according to the embodiment may have a multilayer structure including multiple metal layers. For example, each flexible film122may include a first metal layer adjacent to a front surface of the flexible film122and a second metal layer adjacent to a rear surface of the flexible film122. Each of the first metal layer and the second metal layer may include lines for transmitting signals or power. For example,FIG.5illustrates lines included in the first metal layer, and the illustrated lines may serve as lines for transmitting signals or power.FIG.6illustrates lines included in the second metal layer, and the illustrated lines may serve as lines for transmitting signals or power.

According to an embodiment, as illustrated inFIG.5, the first common lines5221aand the third common lines5221cmay be disposed in the first metal layer. The second common lines5221bmay be disposed in the second metal layer as illustrated inFIG.6. Each flexible film122may include through holes CT21and CT22in which the second common lines5221bdisposed in the second metal layer and each of the first common lines5221aand the third common lines5221cdisposed in the first metal layer may be electrically connected. The through holes CT21and CT22penetrate portions of the flexible film122and connect the first metal layer and the second metal layer.

According to an embodiment, the through holes CT21and CT22may include first through holes CT21in which the first common lines5221aand ends of the second common lines5221bmay be electrically connected, and second through holes CT22in which the third common lines5221cand the other ends of the second common lines5221bmay be electrically connected. Therefore, among the signals or power input to multiple DDIs (e.g., the first DDI511and the second DDI512) disposed on each flexible film122, common signals or power may be input to the first DDI511via the input pad522and the first common lines5221a. Among the signals or powers input to the DDIs (e.g., the first DDI511and the second DDI512) disposed on each flexible film122, the common signals or power may be input to the second DDI512via the input pad522, the first common lines5221a,the first through holes CT21, the second common lines5221b,the second through holes CT22, and the third common lines5221c. The first through holes CT21may be disposed between the first DDI511and the input pad522, and the second through holes CT22may be disposed between the first DDI511and the second DDI512.

Power or signals for independently controlling the first DDI511and the second DDI512may be individually input to the first DDI511and the second DDI512through the independent lines5223and5222. The first independent line5223may be disposed between the input pad522and the first DDI511to connect the first DDI511and the input pad522to each other. A first portion5222aof the second independent line5222may be electrically connected to a second portion5222bof the second independent line5222disposed in the second metal layer through a through hole CT31disposed between the input pad522and the first DDI511. The second portion5222bof the second independent line5222may be electrically connected to a third portion5222cof the second independent lines5222disposed in the first metal layer via a through hole CT32disposed between the first DDI511and the second DDI512. The third portion5222cof the second independent line5222may extend from the through hole CT32to the second DDI512and thus may transmit independent power or signals to the second DDI512.

According to an embodiment, bypass lines5211aand5211bthat bypass the first DDI511and the second DDI512may be respectively disposed on both sides of each flexible film122. Some of the bypass lines5211aand5211bconnect the bypass input pads521and the bypass output pads621to each other through the first metal layer. Some of the bypass lines5211aand5211bconnect the bypass input pads521and the bypass output pads621to each other through the first metal layer and the second metal layer. Through holes CT11may be included that electrically connect the first metal layer and the second metal layer of bypass lines5211aand5211b.

Signals or power output from each of the first DDI511and the second DDI512may be transmitted to the output pads622of each flexible film122through output lines OL1and OL2provided in the flexible film122. The output lines OL1and OL2may include first output lines OL1which transmit signals or power output from the first DDI511to the output pads622and second output lines OL2which transmit signals or power output from the second DDI512to the output pads622. Each of the first output lines OL1and the second output lines OL2may extend through the first metal layer and the second metal layer. For example, a first portion of each of the first output lines OL1may be electrically connected to the first DDI511in the first metal layer and may be electrically connected to a second portion disposed in the second metal layer through a through hole CT41. For example, a first portion of each of the second output lines OL2may be electrically connected to the second DDI512in the first metal layer and may be electrically connected to a second portion disposed in the second metal layer through a through hole CT42.

FIG.7is a layout view of a front portion of a flexible film122according to an embodiment.FIG.8is a schematic diagram illustrating a second independent line5222passing between bumps BM of a DDI according to an embodiment.

The embodiment ofFIGS.7and8is different from the embodiment ofFIGS.5and6in that the flexible film122includes a single metal layer. Therefore, only the features that are different from those of the embodiment ofFIGS.5and6will be described below with reference toFIGS.7and8.

Referring toFIGS.7and8, the flexible film122according to the embodiment may have a single metal layer structure including a single metal layer. For example, each flexible film122may include a first metal layer adjacent to a front surface of the flexible film122. The first metal layer may include lines for transmitting signals or power. For example,FIGS.7and8illustrate lines included in the first metal layer, and the illustrated lines may serve as lines for transmitting signals or power.

According to an embodiment, a first common line5221a,a second common line5221b, and a third common line5221cmay be disposed in the first metal layer. A first independent line5223and a second independent line5222may be disposed in the first metal layer. Bypass lines5211may be disposed in the first metal layer.

The first common line5221amay be disposed between a first DDI511and an input pad522to connect the first DDI511and the input pad522. For example, an end of the first common line5221amay be electrically connected to the input pad522, and another end of the first common line5221amay be electrically connected to a bump BM of the first DDI511on the bottom of the first DDI511. The second common line5221bmay pass under the first DDI511. The second common line5221bmay extend from the bump BM of the first DDI511, to which the first common line5221amay be electrically connected, toward a second DDI512. Here, the second common line5221bmay extend to pass between bumps BM disposed on the bottom of the first DDI511. The third common line5221cmay be disposed between the first DDI511and the second DDI512to connect the second common line5221band the second DDI512. For example, an end of the third common line5221cmay be electrically connected to the second common line5221b,and another end of the third common line5221cmay be electrically connected to a bump BM of the second DDI512.

InFIG.8, BA1represents a first bump array BA1which refers to first bumps BM included in each of the first DDI511and the second DDI512. BA2represents a second bump array BA2which refers to second bumps BM included in each of the first DDI511and the second DDI512. As illustrated, the first bump array BA1and the second bump array BA2may be arranged parallel to each other. The first bump array BA1may be disposed relatively closer to the input pad522than the second bump array BA2. The second bump array BA2may be disposed relatively closer to an output pad622than the first bump array BA1.

Referring toFIG.8, an end of the first common line5221amay be electrically connected to the input pad522, and another end of the first common line5221amay be electrically connected to the first bump array BA1on the bottom of the first DDI511. The second common line5221bmay pass under the first DDI511. The second common line5221bmay extend from a bump BM of the first DDI511, to which the first common line5221amay be electrically connected, toward the second DDI512. Here, the second common line5221bmay extend to pass between the bumps BM of the second bump array BA2of the first DDI511.

The first independent line5223and the second independent line5222for independently transmitting signals or power to the first DDI511and the second DDI512may be arranged as follows. The first independent line5223may be disposed between the first DDI511and the input pad522to connect the first DDI511and the input pad522to each other. The second independent line5222may connect the second DDI512and the input pad522to each other via the bottom of the first DDI511. For example, a first portion5222aof the second independent line5222may be disposed between the first DDI511and the input pad522, a second portion5222bof the second independent line5222may pass between the bumps BM of the first DDI511on the bottom of the first DDI511, and a third portion5222cof the second independent line5222may be disposed between the first DDI511and the second DDI512.

Referring toFIG.8, the second independent line5222may extend to the second DDI512via the bottom of the first DDI511. Here, the second independent line5222may pass between the bumps BM of the first bump array BA1of the first DDI511and between the bumps BM of the second bump array BA2of the first DDI511.

According to a display device and a mobile electronic device including the same according to embodiments, it may be possible to readily secure a pad pitch while placing multiple integrated circuits on one flexible film, thereby increasing yield and reliability.

According to a display device and a mobile electronic device including the same according to embodiments, it may be possible to readily secure a pad pitch while placing multiple integrated circuits on one flexible film, thereby increasing yield and reliability.

However, the effects of the disclosure may not be restricted to the one set forth herein. The above and other effects of the disclosure will become more apparent to one of daily skill in the art to which the disclosure pertains by referencing the claims.