Spread spectrum clock generator and method

In one form, a spread spectrum clock generator includes an oscillator and a digital modulator. The oscillator has a control input for setting an output frequency, and an output for providing a clock output signal. The digital modulator is responsive to the clock output signal to provide a control code to the control input of the oscillator as a periodic signal with a plurality of discrete steps, wherein the digital modulator provides said control code at each of said plurality of discrete steps for substantially a predetermined time.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to clock generator circuits, and more particularly to spread spectrum clock generator circuits.

BACKGROUND

Some electronic components are susceptible to faulty operation in the presence of high levels of electromagnetic interference (EMI). EMI is any unwanted signal transmitted by electromagnetic induction or electromagnetic radiation that affects an electrical circuit. There are many potential sources of EMI such as digital clock signals in microprocessors and microcontrollers, periodic signals used in switched mode power supplies, local oscillator signals used in radio circuits to tune radio frequency (RF) signals, periodic noise from induction motors, and the like.

Several different standards bodies in different jurisdictions around the world define acceptable levels of generated EMI for a certified product. In order to reduce EMI below these standardized levels, circuit designers have sometimes used spread spectrum clock signals. Instead of having a constant frequency, spread spectrum clock signals have frequencies that vary over a certain range to reduce the radiated energy at any given frequency to below the standardized level. In order to efficiently implement spread spectrum, it is desirable to spread the energy of the clock signal as uniformly as possible over the desired range. One known technique to spread the spectrum over the desired range is to vary the frequency of the clock signal using a lower frequency triangular wave signal. While spreading the clock frequency using a triangular wave signal theoretically yields a perfectly uniform frequency spectrum, it becomes less than perfect when implemented using practical circuits and to improve the spreading, known techniques are often expensive in terms of circuit area and cost.

In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1illustrates in partial block diagram and partial schematic form a spread spectrum clock generator100known in the prior art. Spread spectrum clock generator100includes generally an oscillator110, a counter120, and a current source130. Oscillator110has a control input, and an output for providing a clock output signal labeled “CLKOUT”. Oscillator110includes a current source112having a first terminal connected to a power supply voltage terminal labeled “VDD”, and a second terminal connected to the control input of oscillator110. Counter120has an input connected to the output of oscillator110, and an output. Current source110has a first terminal connected to VDD, a second terminal connected to the control input of oscillator110, and a control input connected to the output of counter120.

Spread spectrum clock generator100uses oscillator110to generate the CLKOUT signal, but has a control input that allows for spreading the frequency of the CLKOUT signal over a range to reduce peak EMI. Oscillator110includes a relaxation oscillator that charges a capacitor (not shown inFIG. 1) using the combination of a fixed current source112and a variable current source130. By making the current provided by variable current source130a fraction of the current provided by current source112, spread spectrum clock generator100provides the CLKOUT signal at a frequency that varies over a range that is small compared to the frequency of the CLKOUT signal. Counter120counts clocks of oscillator110to provide a digital ramp signal to current source130. Thus counter120sweeps the current of current source130, and thus the frequency of oscillator110, over a range in which the frequency increases until counter120reaches its maximum count, and then returns to its starting count.

Spread spectrum clock generator100, however, does not spread EMI ideally over the desired range because counter120counts in response to the output of oscillator110itself. When oscillator110is oscillating faster due to the current added by current source130, counter120counts faster and when oscillator110is oscillating slower due to the current added by current source130, counter120counts slower. Thus spread spectrum clock generator100spends more time on the lower end of the frequency range and has higher EMI at the low end of the frequency range. Since EMI is measured as the highest EMI over the desired frequency range, spread spectrum clock generator100is not as efficient in spreading EMI as it could be.

FIG. 2illustrates in partial block diagram and partial schematic form another spread spectrum clock generator200known in the prior art. Spread spectrum clock generator200includes generally an oscillator210labeled “OSCILLATOR #1”, an oscillator220labeled “OSCILLATOR #2”, a counter230, and a current source240. Oscillator210has a control input, and an output for providing the CLKOUT signal. Oscillator210includes a current source212having a first terminal connected to VDD, and a second terminal connected to the control input of oscillator210. Oscillator220has an output for providing another clock signal. Counter230has an input connected to the output of oscillator220, and an output. Current source240has a first terminal connected to VDD, a second terminal connected to the control input of oscillator210, and a control input connected to the output of counter230.

Spread spectrum clock generator200operates similarly to spread spectrum clock generator100ofFIG. 1, except that it uses a second oscillator220to generate a signal for clocking counter230. Because counter230is connected to a separate oscillator, its input clock is not affected by the spreading and the sweep provided by current source240is uniform. However spread spectrum clock generator200requires an additional oscillator, which increases circuit area and cost as well as power consumption.

Counter230can be implemented by a ramp counter, but in order to reduce the abrupt change in frequency that would otherwise occur when the frequency of counter230is reduced from the high end of the range to the low end of the range, spread spectrum clock generator200can further include an intervening circuit that causes the direction of counting to reverse when counter230reaches its peak value. However this digital ramp waveform introduces some EMI peaking at the high and low ends of the range of frequencies, limiting the EMI reduction over the range. In order to overcome this distortion in the frequency characteristic and make the spread spectrum EMI reduction more uniform, another known design compensates for this problem.

FIG. 3illustrates in block diagram form yet another spread spectrum clock generator300known in the prior art. Spread spectrum clock generator300includes generally a phase locked loop310, and a signal generator320. Phase locked loop310includes a phase and frequency detector311labeled “PFD”, a charge pump312labeled “CP”, a loop filter313labeled “LF”, a voltage controlled oscillator (VCO)314, and a multi-modulus divider315. Phase and frequency detector311has a reference clock input for receiving a reference clock signal labeled “REF_CLK”, a loop clock input, and an output. Charge pump312has an input connected to the output of phase and frequency detector311, and an output. Loop filter313has an input connected to the output of charge pump312, and an output. VCO314has an input connected to the output of loop filter313, and an output for providing an output clock signal labeled “OUTPUT”. Multi-modulus divider315has a signal input connected the output of VCO314, a control input, and an output connected to the loop clock input of phase and frequency detector311.

Signal generator320includes generally a slope modulator330and a division modulator340. Slope modulator330includes an up/down slope counter332and a sigma-delta (ΣΔ) modulator334. Slope counter332has a modulation select control input for receiving a 2-bit modulation type select signal, a clock input connected to the output of multi-modulus divider315, an 8-bit count output, and a sign bit output labeled “SIGN”. ΣΔ modulator334has a signal input connected to the count output of slope counter332, a clock input connected to the output of multi-modulus divider315, and an output for providing a single bit output signal. Division modulator340includes an up/down division counter342and a sigma-delta (ΣΔ) modulator344. Division counter342has a signal input connected to the output of ΣΔ modulator334, a clock input connected to the output of multi-modulus divider315, a control input for receiving the sign output of slope counter332, a waveform shape input for receiving parameters labeled “α” and “β”, an output select input for receiving a 14-bit output select signal, and a 14-bit count output. ΣΔ modulator344has a signal input connected to the count output of division counter342, a clock input connected to the output of multi-modulus divider315, and an output connected to the control input of multi-modulus divider315.

Spread spectrum clock generator300is used to create a modulation profile that overcomes the peaking at the high and low frequencies caused by using a triangular waveform. Spread spectrum clock generator300uses a modified triangular waveform as disclosed in U.S. Pat. No. 5,488,627. This waveform is in the shape of a triangular wave and its cubic, and has a similar shape to the chocolate candy sold under the trademark “Hershey's Kiss” sold by the Hershey Company of Hershey, Pa. Thus the waveform exhibits characteristics somewhat opposite those of a triangular waveform near its high and low voltages.

In the frequency domain, spread spectrum clock generator300has an EMI spectrum that peaks but is flat throughout the middle of the desired frequency range, but exhibits variable attenuation at the edges of the band. In addition, it does not exhibit peaking at the sidebands and thus is more efficient in limiting EMI over the desired frequency range.

However spread spectrum clock generator300is complex and requires a large circuit area and cost and relatively high power consumption. PLL310is significantly more complex than a simple relaxation oscillator, requiring a digital phase and frequency detector311, a charge pump312, a voltage controlled oscillator314, and a multi-modulus divider315. In addition, slope modulator330and division modulator340are used to create the “Hershey's Kiss” waveform. It would be desirable to have the benefits of the relatively-flat EMI spectrum provided by spread spectrum clock generator300but without the complexity that results in increased circuit area and cost. Such a clock generator will now be described.

FIG. 4illustrates in block diagram form a spread spectrum clock generator400according to an embodiment of the present invention. Spread spectrum clock generator includes an oscillator410, a digital modulator420, and a divider430. Oscillator410has a control input for setting an output frequency, and an output for providing the CLKOUT signal. Digital modulator420has an input connected to the output of oscillator410, a trim input for receiving an oscillator trim signal labeled “OSC_TRIM”, and an output for providing a 6-bit control code to the control input of oscillator410. Divider430has a clock input connected to the output of oscillator410, a control input for receiving a control signal labeled “SELECT FREQUENCY”, and an output for providing a clock signal labeled “CLKOUT2”.

Oscillator410has a nominal base frequency but varies the base frequency according to the 6-bit control code received from digital modulator420. As will be shown, oscillator410can be implemented as a simple relaxation oscillator rather than a complex phase locked loop.

Digital modulator420receives the CLKOUT signal from the output of oscillator410and uses it to clock its internal operations. However digital modulator420does not divide the CLKOUT signal and use the divided CLKOUT signal to change the frequency over the desired spreading range like spread spectrum clock generator100ofFIG. 1. Rather it provides the 6-bit control code to sequence through a set of offset values to the nominal value of the CLKOUT signal, and alters the number of cycles that it uses to provide the control code in a given state to ensure it provides each unique value of the digital code for substantially a predetermined time. As used herein, digital modulator420provides each unique value for substantially a predetermined time by counting a number of cycles of the CLKOUT signal corresponding to its phase such that the elapsed time is approximately equal to same time for each phase. A digital modulator circuit that provides this function with a small circuit area will be described below.

Divider430is an output divider used to provide CLKOUT2at a variety of output frequencies useful for the application circuit to which spread spectrum clock generator400is connected. It divides the CLKOUT signal by a divider value indicated, directly or indirectly, by the SELECT FREQUENCY signal. In turn the SELECT FREQUENCY signal may be formed in a variety of ways, such as by programmable fuses at factory test, by receiving an input value at startup, by the value of an external resistor, etc. For example if the CLKOUT signal has a frequency is 8.4 megahertz (MHz), and the SELECT FREQUENCY indicates a divider of 14, then the CLKOUT2signal is 600 kHz, whereas if SELECT FREQEUNCY indicates a divider of 42, then the CLKOUT2signal is 200 kHz.

As will be seen, spread spectrum clock generator400provides highly efficient EMI spreading over the desired range, but without significant circuit complexity and with the use of only a single oscillator, which itself is relatively simple.

FIG. 5illustrates in partial block diagram and partial schematic form a relaxation oscillator500suitable for use as oscillator410ofFIG. 4. Relaxation oscillator500includes generally two circuit structures510and520labeled “STRUCTURE A” and “STRUCTURE B” that are used to define the high time and the low time, respectively, of the CLKOUT signal, a demultiplexer530, a fixed current source540, a digitally controlled current source550, and a control circuit560.

Circuit structure510includes a capacitor511, a comparator512, and a switch513. Capacitor511has a first terminal connected to a positive power supply voltage terminal labeled “AVDD”, and a second terminal. AVDD is a supply voltage high enough for the proper operation of analog circuitry and will typically be higher than the power supply voltage for the digital circuitry. Comparator512has an inverting input connected to the second terminal of capacitor511, a non-inverting input terminal for receiving a reference voltage labeled “REF”, and an output terminal for providing a set signal labeled “S”. Switch513has a first terminal connected to AVDD, a second terminal connected to the second terminal of capacitor511, and a true control terminal for receiving a signal labeled “ON-SW”.

Circuit structure520includes a capacitor521, a comparator522, and a switch523. Capacitor521has a first terminal connected to AVDD, and a second terminal. Comparator522has an inverting input connected to the second terminal of capacitor521, a non-inverting input terminal for receiving reference voltage REF, and an output terminal for providing a reset signal labeled “R”. Switch523has a first terminal connected to AVDD, a second terminal connected to the second terminal of capacitor521, and a complementary control terminal for receiving signal ON-SW.

Demultiplexer530has an input terminal, a first output terminal connected to the second terminal of capacitor511, a second output terminal connected to the second terminal of capacitor521, and a select input for receiving signal ON-SW. Fixed current source540has a first terminal connected to the input terminal of demultiplexer530, and a second terminal connected to ground. Digitally controlled current source550has a first terminal connected to the input terminal of demultiplexer530, a second terminal connected to ground, and a control terminal for receiving the 6-bit CONTROL CODE from digital modulator420.

Control circuit560includes a set-reset (SR) flip-flop562, and an inverter564. SR flip-flop562has an S input connected to the output of comparator512, a reset input connected to the output of comparator522, and an output for providing the ON-SW signal. Inverter564has an input connected to the output of SR flip-flop562, and an output for providing the CLKOUT signal.

Relaxation oscillator500uses two similar circuits, STRUCTURE A and STRUCTURE B, to determine the ramp up and the ramp down time of a triangle wave. Capacitors511and521are matched to provide uniform rise and fall time and a duty cycle of the CLKOUT signal of about 50%. During one phase when ON-SW is high, switch513is closed to set the voltage at the second terminal of capacitor511equal to AVDD. Switch523is open, and demultiplexer530selects the second output. The rate at which capacitor521charges determines the low time of the CLKOUT signal, and this rate is set by the current set by the combination of fixed current source54and variable current source550. Current source550operates as a digital-to-analog converter that transforms the binary CONTROL CODE into a corresponding current using, for example, switched binarily weighted current sources.

During the other phase when ON-SW is low, switch523is closed to set the voltage at the second terminal of capacitor521equal to AVDD. Switch513is open, and demultiplexer530selects the first output. The rate at which capacitor511charges determines the high time of the CLKOUT signal, and this rate is set by the current set by the combination of fixed current source54and variable current source550.

In other embodiments, any of a number of well known relaxation oscillators can be used, including a relaxation oscillator that uses the same current source to control both charging and discharging of a single capacitor.

FIG. 6illustrates in block diagram form a digital modulator600suitable for use as digital modulator420ofFIG. 4. Digital modulator600includes generally a fixed time counter610, a counter phase circuit620, and a code generator circuit630. Fixed time counter610has a clock input for receiving the CLKOUT signal, a control input for receiving a timeout value labeled “TIMEOUT VALUE”, and an output for providing a signal labeled “TIMEOUT”. Counter phase circuit620has an input connected to the output of fixed time counter610, and an output for providing a 4-bit counter phase value. Code generator circuit630has a first input connected to the output of counter phase circuit620, a second input for receiving the OSC_TRIM signal, a first output for providing the TIMEOUT VALUE, and a second output connected to the control input of the oscillator for providing a 6-bit DIGITAL CODE.

Fixed time counter610provides the TIMEOUT signal after it counts approximately a predetermined time, which is a time close to the predetermined time but is not exactly so because it is limited by the frequency of the CLKOUT signal. Code generator circuit630adjusts the TIMEOUT VALUE in response to the counter phase, which corresponds to a different frequency of the CLKOUT signal. If oscillator410is relatively slow because of the spread spectrum frequency modulation, then fixed time counter610times out after a fewer number of cycles. Conversely, if oscillator410is relatively fast because of the spread spectrum frequency modulation, then fixed time counter610times out after a greater number of cycles. Fixed time counter610activates the TIMEOUT signal to represent the completion of one discrete step of the digital spread spectrum modulation after the predetermined time.

Counter phase circuit620is a simple state machine that cycles through a series of states corresponding to different discrete steps of the CLKOUT signal. In the illustrated embodiment, counter phase circuit620is itself a binary counter that has sixteen states and provides a 4-bit output signal to lookup table630.

In one form, code generator circuit630is implemented using a lookup table that uses the counter phase encoded on the 4-bit output of counter phase circuit620to index into a set of stored values in lookup table630. Each of the stored values includes a pair of values, one for the TIMEOUT VALUE and another for the DIGITAL CODE corresponding to the counter phase. When the base frequency of oscillator410and the EMI spreading requirements are known, lookup table630can be implemented as a small read-only memory (ROM), which is very efficient in terms of circuit area. In another embodiment in which spread spectrum clock generator400is used in an integrated circuit that can be programmed for different environments with different clock frequencies, lookup table630can be implemented as a one-time programmable ROM to allow the characteristics to be programmed.

In another form, code generator circuit630is implemented using a digital finite state machine. In this embodiment, the TIMEOUT VALUE can be calculated as a linear combination of the DIGITAL CODE and the OSC_TRIM signal.

Another aspect of digital modulator600is that code generator circuit630receives the OSC_TRIM signal to allow the base frequency of oscillator410to be calibrated after the integrated circuit is manufactured to compensate for processing variations. In one embodiment, code generator circuit630adds an offset value indicated by the OSC_TRIM signal to the DIGITAL CODE that will allow the base frequency of oscillator420to be offset by a small percentage of the desired frequency of the CLKOUT signal that compensates for foreseeable manufacturing variations. In this case, a small adder circuit having six or fewer bits can be used.

In one embodiment, counter phase circuit620also receives the OSC_TRIM signal, and uses the OSC_TRIM signal to vary the number of states it cycles through to keep the modulation depth of spread spectrum clock generator600substantially fixed, despite processing variations. If the OSC_TRIM signal is smaller, then counter phase circuit620employs a smaller digital amplitude of the counter phase (a fewer number of discrete steps). Conversely, if the OSC_TRIM signal is larger, then counter phase circuit620employs a larger digital amplitude of the counter phase (a greater number of discrete steps).

FIG. 7illustrates a timing diagram700showing the operation of spread spectrum clock generator400ofFIG. 4. InFIG. 7, the horizontal axis represents time in microseconds (pec), and the vertical axis represents the frequency of CLKOUT in megahertz (MHz). In this example, the nominal base frequency of CLKOUT is 8.4 MHz, but due to the spreading action of spread spectrum clock generator400, the frequency varies between about 7.728 MHz and about 9.072 MHz, or about ±8% (referred to as a modulation depth of 8%). Timing diagram700shows one complete cycle of a triangle wave710implemented using 15 discrete steps. As shown waveform710starts at 0 μsec at a middle level720corresponding to the base frequency of 8.4 MHz, and ramps up to a largest frequency step730of 9.072 MHz in 7 discrete steps, then ramps down to a smallest frequency750of 7.728 MHz in 14 discrete steps, and then returns to the nominal base frequency of 8.4 MHz in 7 discrete steps. The complete frequency modulation cycle spans 2500 μsec to provide 400 Hz modulation. The ramp from the largest frequency to the smallest frequency takes place in 14 steps, and the ramp from the smallest back to the largest takes place in 14 steps, and thus one complete cycle has 28 discrete steps. Each step lasts for 2500 μsec/28=89.29 μsec, shown as a time labeled “t1”.

Digital modulator600can accurately implement this system as follows. Lookup table640provides the TIMEOUT VALUE as a count of the number of cycles of oscillator410at the frequency of the current oscillator phase that would approximate 89.29 μsec. It does so using an even divider to simplify the logic. The values required for each counter phase are shown in TABLE I below:

In the frequency domain, digital modulator600produces an EMI spectrum that has a large number of closely spaced discrete tones that define the EMI level. In another embodiment, digital modulator600could dither between adjacent pairs of discrete frequency steps to provide a more uniform EMI spectrum, but at the expense of increasing circuit complexity and size.

Digital modulator600is very small in terms of circuit area because it uses only compact digital circuitry. A practical implementation of fixed time counter610to implement these divide ratios requires only about 1,000 logic gates, which allows fixed time counter610to be relatively small using modern CMOS integrated circuit technology. Along with the re-use of oscillator410, spread spectrum clock generator400avoids spreading the EMI more heavily to lower frequencies using known single-oscillator designs, but requires a much smaller circuit area compared to the “Hershey's Kiss” spread spectrum oscillator300ofFIG. 3.

Note that steps710and720correspond to the +2 phase and are encountered twice during the frequency modulation cycle, like all other intermediate steps. However the largest step730and the smallest step750occur only once during the frequency modulation cycle, causing a slight distortion in the EMI spectrum. Accordingly in one embodiment, digital modulator400could be modified slightly to repeat the count values for the largest step730(corresponding to the +7 phase) and the smallest step750(corresponding to the −7 phase).

FIG. 8illustrated in partial block diagram and partial schematic form a DC-DC converter800using a spread spectrum clock generator such as spread spectrum clock generator400ofFIG. 4. DC-DC converter800includes generally a controller chip810, a high side switch820, a low side switch830, an inductor840, a load850, and a feedback circuit860. Controller chip810includes a pulse width modulator (PWM) switching regulator as well as a variety of other circuits useful in DC-DC power supplies that are not shown inFIG. 8. Controller chip810includes an oscillator circuit811using a spread spectrum clock generator, an error amplifier812, a PWM latch813, a high side driver814, a delay element815, and a low-side driver816. Oscillator circuit811has two outputs including a first output for providing a square wave clock signal, and a second output for providing a ramp signal. Error amplifier812has a non-inverting input connected to the first output of oscillator811, an inverting input connected to a feedback terminal labeled “FB”, and an output. PWM latch813has a set (S) input connected to the first output of oscillator circuit811, a reset (R) input connected to the output of error amplifier812, and an output (Q). Driver814is a non-inverting driver that has an input connected to the Q output of PWM latch813, and an output. Delay element815has an input connected to the Q output of PWM latch813, and an output. Driver815is an inverting driver that has an input connected to the output of delay element815, and an output.

Transistor820has a drain for receiving an input voltage labeled “VIN”, a gate connected to the output of driver814, and a source. Transistor830has a drain connected to the source of transistor820, a gate connected to the output of driver816, and a source connected to ground. Inductor840has a first terminal connected to the source of transistor820and the drain of transistor830, and a second terminal for providing an output voltage labeled “VOUT”. Load850has a first terminal connected to the second terminal of inductor840, and a second terminal connected to ground. Feedback circuit860includes resistors862and864. Resistor862has a first terminal for receiving VOUT, and a second terminal connected to the FB terminal of controller chip810. Resistor864has a first terminal connected to the second terminal of resistor862, and a second terminal connected to ground.

In operation, controller chip810changes the duty cycle of the high side driver and the low side driver in response to a difference between the ramp signal provided by oscillator811and the voltage on the FB pin. The voltage on the FB pin in turn is a voltage proportional to VOUT as determined by the values of resistors862and864. High side switch820and low side switch830are on the input side of inductor840, and thus DC-DC converter800operates as a buck converter. Controller chip810uses an oscillator based on a spread spectrum clock generator as described herein such as spread spectrum clock generator400ofFIG. 4. Thus controller chip810is compact and inexpensive to the user.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true scope of the claims. For example the spread spectrum clock generator can be used in a variety of electronic products such as microcontrollers, switch mode power supplies, and the like. Moreover the triangular wave signal could be replaced with a similar signal having a uniform amplitude over a period, such as an asymmetric triangular wave or a sawtooth wave. While the relaxation oscillator disclosed herein is compact, it could be replaced by other oscillator designs. Based on the requirements of the application, the discrete triangle wave ofFIG. 7could be used, or the waveform could be modified to improve EMI spreading by correcting the small distortion at the extreme high and low frequencies.

Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.