Methods and systems to convert a pulse power demand to a constant power draw

Methods and systems to translate a pulse power demand of a pulse load to a constant power draw, and to maintain a desired peak output voltage over time. A power converter (PC) provides power from a power source to a charge store, which provides pulse power to the load. A PC controller continuously monitors an output current of the PC and an output voltage of the charge store, and controls the PC to draw constant power from the source, at a level indicated by a power command. A peak voltage controller periodically adjusts the power command, such as to compensate for time-varying effects, based on a peak voltage reference and the output voltage of the charge store measured at times of synchronization pulses. The peak voltage controller generates the synchronization pulses based on rising edges of a pulse current, or receives the synchronization pulses from the radar system controller.

BACKGROUND

1. Technical Field

Disclosed herein are methods and systems to regulate a power converter to draw a constant power level from a power source to a charge store, which provides pulsed power to a pulse load such as a radar system, and methods and systems to maintain a desired peak output voltage of the charge store such as to accommodate time-varying effects.

2. Related Art

A radar system presents periodic and instantaneously-high current pulse loads to a power source or an upstream power bus.

The pulse load may result in large ripple currents on the power source or upstream power bus, which may impact power quality for other loads. Where the power source includes a generator, such as with ship-based, tactical, or transportable radar, large ripple currents may cause instability and mechanical stresses on the generator.

SUMMARY

Disclosed herein are methods and systems to translate a pulse power demand of a pulse load, such as a radar system, to a constant power draw from a power source.

Also disclosed herein are methods and systems to maintain a desired peak output voltage to the pulse load over time, such as to compensate for time-varying effects that might otherwise alter the peak output voltage over time. Time-varying effects may include temperature changes and/or component aging.

A system may include a charge store to provide power to a pulse load, such as a radar system. The system may further include a power converter (PC) to provide power from a power source to the charge store, and a PC controller to continuously control the PC to draw constant power from the power source. The PC controller may control the PC based on a sensed output current of the PC, a sensed output voltage of the charge store, and a power command, which may represent a desired average power level.

The system may further include a peak voltage controller to periodically adjust the power command to maintain a peak output voltage substantially equal to a peak voltage reference.

The peak voltage controller may determine the peak output voltage based on the sensed output voltage of the charge store in synchronization to the start of the load pulse. The synchronization pulse may be generated on the rising edges of the pulse load current, or may be provided by the radar system controller.

The peak voltage controller may periodically adjust the power command at a frequency of the pulse load.

The peak voltage controller may vary an adjustment step size based on a magnitude of a difference between the peak output voltage and the peak voltage reference, and may adjust the power command by one of multiple step-sizes based on the magnitude of the difference.

The peak voltage controller may include a field-programmable gate array (FPGA) to compare the peak output voltage to one or more reference values.

Methods and systems disclosed herein are not limited to the above-summary.

In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.

DETAILED DESCRIPTION

FIG. 1is a block diagram of a system100to convert a pulse power demand of a pulse load104to a constant power draw from a power source102.

For illustrative purposes, pulse load104is described herein with reference to a radar system. Pulse load104is not, however, limited to a radar system.

Power source102may include an alternating current (AC) source, and may include and AC/DC converter to convert AC power to direct current (DC) power.

System100includes a charge store108to provide pulsed power to radar system104. Charge store108may include a capacitive storage system.

System100further includes a power converter (PC)106to provide power from power source102to charge store108.

Pulse loading from radar system104may impart a triangular ripple voltage on top of a DC voltage at110, having a ripple frequency equal to a pulse repetition frequency of a transmitted pulse train of radar system104.

System100further includes a PC controller114, including a constant power controller (CPC)116to control PC106to convert the pulse power demand of radar system104to a constant power demand on power source102. PC106and PC controller114may protect source102from otherwise adverse effects of the pulsed loading of charge store108.

InFIG. 1, CPC116provides a PC control122based on a sensed voltage124(Vcap) of charge store108, a sensed current126(Iout_sensed) output from PC106, and a desired or reference power level, illustrated here as a power command118(Vpout_2_cmd).

CPC116may adjust PC control122to increase the output current of PC106when Vcap decreases, and to decrease the output current of PC106when Vcap increases, in order to maintain output power of PC106substantially equal to Vpout_2_cmd.

Power command118may be based on a power command120(Vpout_1_cmd), which may represent a desired average power level. Power command120may correspond to the average power level for the next set of transmitted pulses for the radar system104, and may be uploaded or received from a radar system controller.

Transmit pulses of radar system104may have constant and/or variable pulse widths. For both constant and variable pulse widths, when duty cycle of the transmit pulses is maintained constant, the power averaged over each pulse repetition interval is constant. When the power delivered by PC106is constant, the power drawn from power source102is also constant. The duty cycle of repetitive transmit pulses may be expressed as:

Where the pulse width and/or pulse repetition interval of radar system104change, power command120(Vpout_1_cmd) may change as well, such as described further below. When power command120is changed, a corresponding response time of system100is determined by a control bandwidth of PC106.

InFIG. 1, PC controller114further includes a peak voltage controller130to generate an adjustment control128(Vpout_adjust), to maintain a desired peak output voltage of charge store108. PC controller114further includes a module132to adjust Vpout_1_cmd based on Vpout_adjust. Peak voltage controller130is described further below with reference toFIGS. 3 and 4.

FIG. 2is a block diagram of system100, including an example implementation of PC controller114.

InFIG. 2, CPC116includes a divider202to determine a desired current command204(Iout_cmd) as:
Iout_cmd=Vpout—2_cmd/Vcap,  EQ. (2)
where Vpout_2_cmd is the desired power command represented by a voltage level.

CPC116further includes a subtractor206to provide an error or difference208based on a difference between Iout_cmd and Iout_sensed.

CPC116further includes a current compensator210to adjust PC control122to reduce difference208, to maintain the power of PC106substantially equal to Vpout_2_cmd.

Peak voltage controller130is now described.

InFIG. 1, peak voltage controller130controls Vpout_adjust 128 so that Vcap returns to a peak voltage reference value just prior to each new load pulse. When Vcap is too low, Vpout_adjust is increased. If Vcap is still too low at the next synch pulse, Vpout_adjust is further adjusted. This may be repeated until Vcap is at the peak voltage reference value. Conversely, when Vcap is above the peak voltage reference value, Vpout_adjust may be reduced.

Peak voltage controller130may compensate for time-varying effects that may impact peak voltage of charge store108. Time-varying effects may result from environmental changes (e.g., temperature change) and/or component aging. As a result of such effects, the desired output power of PC106may not correspond to power command120.

Peak voltage controller130may update adjustment control128(Vpout_adjust) once per transmit period of radar system104. Vpout_adjust may thus be corrected or adjusted more frequently for short pulse repetition intervals than for long pulse repetition intervals. For extremely short pulse repetition intervals it may be desirable to update adjustment control128(Vpout_adjust) less frequently due to bandwidth limitations of the controls. The determination of the adjustment should be performed in sync with the start of a new transmit pulse.

CPC116may be implemented substantially with analog circuit components, whereas peak voltage controller130may include analog components, digital components, and/or combinations thereof.

FIG. 3is a block diagram of system100, including an example implementation of peak voltage controller130.

InFIG. 3, peak voltage controller130includes synchronizer circuitry302to generate sync pulses310to indicate times at which Vcap is at a peak voltage. Synchronizer circuitry302generates sync pulses310based on rising edges of a sensed pulse current134(Ipulse_sensed). Synchronizer circuitry302may, for example, include a limiter circuit304to output an indication306when Ipulse_sensed exceeds a threshold value that corresponds to the beginning of a transmit pulse of radar system104. Circuitry302further includes a register308, such as a flip-flop, to register indication306as synch pulse310to a control system312.

Alternatively, sync pulses310coincident with the start of the transmit pulse may be provided by radar system104.

Control system312determines a peak voltage of Vcap based on a value of Vcap coincident with a sync pulse310, compares the peak voltage to one or more reference values, and selectively adjusts Vpout_adjust based on a the comparison(s).

Peak voltage controller130may help to support long pulse operation for a variety of transmit intervals. For a long pulse, the output voltage of charge store108may droop before the end of the pulse. Peak voltage controller130ensures that that charge store108is always recharged to the same level, which ensures that all consecutive long pulse profiles will be the same, even if the output voltage droops. In other words, regulation of the peak output voltage helps to maintain quality of pulses during long pulse width transmissions, and provides consecutive long pulses with substantially identical energy.

Control system312may vary an adjustment step size of Vpout_adjust based on a magnitude of a difference between Vcap and a desired or peak voltage reference, and may adjust Vpout_adjust by one of multiple selectable step-sizes based on the magnitude of the difference, such as described below with reference toFIG. 4.

FIG. 4is a depiction of logical operations400, which may be implemented by control system312inFIG. 3.

in[2] corresponds to an existing value of Vpout_adjust inFIG. 3; and

out[0] corresponds to a new or updated value of Vpout_adjust inFIG. 3.

As described below, logical operations400maintain the peak voltage of Vcap between values of 32.75 and 33.25 (i.e., for a peak voltage reference value of 33). Methods and systems disclosed herein are not, however, limited to the examples ofFIG. 4.

At402, out[0] (Vpout_adjust), is initialized to 0. This may be performed upon a system initialization or power-up.

At404, when in[1] (sync pulse310) is below a sync pulse threshold value, a value n is set to 1 to indicate an that sync pulse310is inactive.

At406, when in[1] (sync pulse310) is above the sync pulse threshold value, n is set to 2 to indicate that sync pulse310is active.

In the example ofFIG. 4, the synch pulse threshold value is set to 0.9. Methods and systems disclosed herein are not, however, limited to these examples.

When n=2 (i.e., synch pulse310is active), one or more of408through422are performed as described below.

At408, when Vcap is greater than a reference value of 33.25, Vpout_adjust is decremented by a step size of 0.5.

At410, when Vcap is greater than a reference value of 34, Vpout_adjust is decremented by a step size of 1.0.

At412, when Vcap is greater than a reference value of 35, Vpout_adjust is decremented by a step size of 1.5.

At414, when Vcap is greater than a reference value of 36, and Vpout_adjust is above zero, Vpout_adjust is reset to zero.

In other words, when Vcap exceeds the peak voltage reference value of 33, and as the magnitude of the difference between Vcap and the peak voltage reference value of 33 increases, Vpout_adjust is decremented with increasing step sizes. When the magnitude of the difference exceeds a difference threshold of 36−33=3, Vpout_adjust is reset to zero regardless of the existing value of Vpout_adjust. The difference threshold may correspond to an over-voltage condition, such as described further below.

Similarly, at416through420, when Vcap is below the peak voltage reference value of 33, and as the magnitude of the difference between Vcap and the peak voltage reference value of 33 increases, Vpout_adjust is incremented with increasing step sizes (i.e., 0.5, 1.0, or 1.5). When the magnitude of the difference exceeds a second difference threshold of 33−30=3, Vpout_adjust is reset to zero regardless of the existing value of Vpout_adjust. The second difference threshold may correspond to an under-voltage condition.

Control system312may be implemented with integrated circuit (IC) logic, which may include a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and/or other IC devices. Control system312may further include an analog-to-digital converter (ADC) to quantize Vcap for comparison to one or more reference values, and may include a digital-to-analog converter (DAC) to output Vpout_adjust as an analog control.

As described further above with reference toFIG. 1, pulsed loading from radar system104may impart a ripple voltage on top of a DC voltage at110, having a frequency equal to a pulse repetition frequency of a transmitted pulse train of radar system104. System100may include a voltage regulator (VR)112to reduce and or eliminate the ripple voltage from the pulsed power provided to radar system104.

As further described above, charge store108serves as an energy reservoir to provide pulse energy or power to radar system104. Where a larger triangle ripple is allowed on capacitors of charge store108, less capacitance is needed to provide the pulse energy. A maximum allowable ripple may be set based on a maximum voltage rating of the capacitors and an allowable input voltage range of VR112to maintain a regulated output. Total capacitance of charge store108may be determined based on the energy requirement of the longest anticipated pulse duration.

VR112may include a linear voltage regulator, and PC106may include a switching-based DC/DC converter such as described below with reference toFIG. 5. Alternatively, VR112and PC106may each include a switching-based DC/DC converter.

A switching frequency of a DC/DC converter is typically much higher than the ripple frequency due to radar pulse repetition frequency.

A power draw from power source102may be more stable where PC106and VR112are implemented as switching DC/DC converters, relative to a situation where VR112is implemented as a linear regulator. A switching DC/DC converter implementation of VR112may provide greater overall system efficiency.

Where VR112is implemented as a switching DC/DC converter, power command120may remain constant when the pulse width of radar transmissions change, provided that the duty cycle of the radar transmission is constant and an efficiency of the switching DC/DC converter is constant.

In a linear voltage regulator, average losses change with load pulse width. Thus, where VR112includes a linear regulator, the average voltage into the linear regulator varies as the pulse width varies. In order to maintain a constant power draw from power source102while maintaining a constant peak output voltage of charge store108, power command120(Vpout_1_cmd) should change with changes in the load pulse width, even where the duty cycle of the pulse load is constant.

FIG. 5is a block diagram of system100, where PC106includes a switching DC/DC converter.

InFIG. 5, PC106includes a switch circuit502and a gate driver504to control on and off times of switch circuit502, such as with a pulse width modulated (PWM) control506. The output current of PC106is determined by a duty cycle of PWM control506, which may be expressed as:
Duty Cycle=(502 ON Time)/(502 ON time+502 OFF time).  EQ. (3)

Gate driver504is controllable with a gate driver control508. In the example ofFIG. 5, system100includes a comparator510to generate gate driver control508based on a difference a control518and a sensed current512of PC106.

Control518may correspond to PC control122, or may be generated from a combination of PC control122and one or more other controls.

For example, inFIG. 5, system100further includes an over-voltage protection (OVP) loop514, which may be implemented as a relatively fast-acting or instantaneously-active loop. When Vcap reaches an OVP threshold, OVP loop514activates to provide an OVP control516to reduce the current output of PC106. In this example, control518is generated based on a combination of PC control122and OVP control516.

The OVP threshold may be set so that under normal operation, with relatively small differences between the desired output power of PC106and the actual output power of PC106, OVP loop514is not activated. A voltage rating, and hence a voltage derating requirement of capacitors of charge store108may also be considered in setting the OVP threshold.

Where PC controller114includes peak voltage controller130(FIGS. 1,2, and3), the OVP threshold may be set higher than the peak voltage reference. In this example, OVP loop514may be activated to prevent Vcap from exceeding the OVP threshold, while peak voltage controller130continues to adjust Vpout_adjust to bring the peak value of Vcap to the peak voltage reference value.

FIG. 6is a block diagram of a simulation environment600, including a simulator model601and a PC controller614. PC controller614includes a constant power controller (CPC)616and peak voltage controller130. Simulator model601may be implemented to exercise and/or evaluate one or more features of PC controller614.

Simulator model601includes a current source602in place of power source102and PC106. Simulator model601further includes a linear voltage regulator612and a pulse load604. Current source602may be implemented and/or simulated as an ideal current source, and pulse load604may simulate a radar system. Pulse load604is controllable with commands638to provide variable and/or multiple pulse loads or profiles.

FIGS. 7 through 25are timing diagrams generated for simulation environment600, in which a first repetitive pulse train640is applied at time t=zero, and a second repetitive pulse train642is applied at time t=2.017 seconds. First pulse train640has a pulse width slightly longer than a maximum pulse width that PC controller614can support without accruing a voltage droop. Second pulse train642has a pulse width that is sufficiently long to cause relatively significant droop in an output voltage646to linear regulator612. In this example, two different power commands638are issued, one at time=0, the other at time t=2.017 seconds, corresponding to the two pulse profiles. Methods and systems disclosed herein are not, however, limited to these examples.

FIGS. 7 through 14are timing diagrams generated with peak voltage controller130disabled to preclude adjustments for peak voltage errors.FIGS. 7 through 14include curves for ideal conditions in which power commands638are configured to support the desired load pulses (blue curves).FIGS. 7 through 14further include curves for non-deal, or error conditions in which power commands638are issued to provide 10% less power than needed to achieve the desired pulses (red curves). Each ofFIGS. 7 through 14is addressed below.

FIG. 7is a timing diagram700of pulse load current from time t=0 to time t=4 seconds, including an Ipulse_ideal702, for which commands match the desired load condition, and an Ipulse_error704, for which commands give 10% less average power than the desired load condition.

FIG. 8is a timing diagram800of output voltage to pulse load from time t=0 to time t=4 seconds, including a Vout_ideal802and a Vout_error804.

FIG. 9is a timing diagram900of voltage into linear regulator from time t=0 to time t=4 seconds, including a Vin_linreg_ideal902and a Vin_linreg_error904.

FIG. 10is a timing diagram1000of current delivered from power converter to charge store and linear regulator from time t=0 to time t=4 seconds, including an Ideliver_ideal1002and an Ideliver_error1004.

FIG. 11is an expanded view of timing diagram700, centered about pulse profile transition time t=2.017 seconds.

FIG. 12is an expanded view of timing diagram800, centered about pulse profile transition time t=2.017 seconds.

FIG. 13is an expanded view of timing diagram900, centered about pulse profile transition time t=2.017 seconds.

FIG. 14is an expanded view of timing diagram1000, centered about pulse profile transition time t=2.017 seconds.

The ideal and error curves ofFIGS. 7 through 14illustrate error in the current pulse provided to load604when peak voltage controller130is disabled.

FIGS. 15 through 25are timing diagrams generated with peak voltage controller130enabled to provide adjustments for peak voltage errors.FIGS. 15 through 22include curves for ideal conditions in which power commands638are configured to provide desired load pulses (blue curves).FIGS. 15 through 22further include curves for non-deal conditions in which power commands638are issued to provide 10% less power than needed to achieve the desired pulses, and for which peak voltage controller130provides correction for peak voltage discrepancies (green curves).

FIG. 15is a timing diagram1500of pulse load current, including an Ipulse_ideal1502and an Ipulse_corrected1504.

FIG. 16is a timing diagram1600of output voltage to pulse load, including a Vout_ideal1602and a Vout_corrected1604.

FIG. 17is a timing diagram1700of voltage into linear regulator, including a Vin_linreg_ideal1702and a Vin_linreg_corrected1704.

FIG. 18is a timing diagram1800of current delivered from power converter to charge store and linear regulator, including an Ideliver_ideal1802and an Ideliver_corrected1804.

FIG. 19is an expanded view of timing diagram1500, centered about pulse profile transition time t=2.017 seconds.

FIG. 20is an expanded view of timing diagram1600, centered about pulse profile transition time t=2.017 seconds.

FIG. 21is an expanded view of timing diagram1700, centered about pulse profile transition time t=2.017 seconds.

FIG. 22is an expanded view of timing diagram1800, centered about pulse profile transition time t=2.017 seconds.

It can be seen fromFIGS. 15 through 22that, after about 1 second, the power command has been adjusted to correct for peak voltage error and the corrected curves match the ideal curves.

It can further be seen fromFIGS. 15 through 22that, at time 2.017 seconds when the second power command is issued with the 10% error, the adjustment command is already at the correct value and no error is seen for the second set of pulses. The 10% instantaneous error is an exaggeration of real operational conditions, because variations due to temperature or aging will typically occur relatively slowly over time rather than instantaneously.FIGS. 15 through 22thus illustrate that methods and systems disclosed herein may be implemented to adjust

the power command in a time period of about one second to correct for an instantaneous application of a command with a 10% error.

FIGS. 23,24, and25are timing diagrams to contrast power delivered to the pulse load and power drawn from the input power source, from t=1.8 seconds to t=2.3 seconds.

FIG. 24is a timing diagram2400, including current delivered from power converter to charge store and linear regulator (Ideliver_ideal)2202ofFIG. 22, and charge store voltage/input voltage to linear regulator (Vin_linreg_corrected)2104ofFIG. 21.

FIG. 25is a timing diagram2500, including Power_out2504, determined as

FIGS. 23 through 25illustrate a stable and constant power draw.

FIGS. 7 through 25were generated with control loop bandwidths of a DC/DC converter and linear regulator612modeled as infinite. In practice, some power ripple may be drawn from the power source, which will be determined by the loop bandwidths.

FIG. 26is a flowchart of a method2600of converting a pulse power demand to a constant power demand. Method2600may be implemented with system100as described in one or more examples herein. Method2600is not, however, limited to the examples of system100.

At2602, power is provided from a source to a charge store, under control of a power converter (PC), such as described above with respect to charge store108and PC106.

At2604, pulsed power is provided from the charge store to a load, such as described above with respect to charge store108and load104.

At2606, output power of the PC is continuously monitored relative to a power command, and the PC is controlled as needed to maintain the output power at a level indicated by the power command, such as described above with respect to CPC116.

The continuous monitoring and controlling at2606may include dividing a sensed output voltage of the charge store by the power command to provide a current command, determining a difference between the current command and a sensed output current of the power converter, and adjusting an output current command to the power converter, as needed, to reduce and/or minimize any difference.

At2608, a peak output voltage of the charge store is periodically monitored relative to a peak voltage reference, and the power command is selectively adjusted (i.e., adjusted as needed) to reduce and/or minimize any difference between the peak output voltage and the peak voltage reference, such as described above with respect to peak voltage controller130.

The periodically adjusting at1606may include determining the peak output voltage of charge store based on the sensed output voltage of the charge store at times of synchronization pulses.

The synchronization pulses may be generated from the rising edges of a sensed pulse current provided to the load. Alternatively, the synchronization pulses may be provided by a control system associated with the load.

The periodically monitoring and selective adjusting at2608may be performed at a frequency of the pulsed power provided to the load, or a lower frequency.

The selective adjusting at2608may include varying an adjustment and/or selecting one of multiple step-sizes based on a magnitude of the difference between the peak output voltage and the peak voltage reference, such as described above with reference toFIG. 4.

Returning toFIG. 1, system100may be implemented as a forward voltage mode converter with peak current mode control. System100is not, however, limited to forward voltage mode converters. Rather, system100may be implemented with one or more of a variety of converter topologies and/or with an average current mode control.

PC106and VR112represent corresponding first and second stages of a two-stage power topology, which may be similar to a power factor correction (PFC) design that utilizes two power stages. For a PFC function, an input current is shaped to match a sinusoidal input voltage, mimicking a current profile of a resistor thereby producing a high power factor. In order to achieve input characteristics of a resistor, the output voltage of the first power stage has a high sinusoidal ripple component, and the second power stage provides a regulated voltage to the load. Methods and systems disclosed herein may be implemented to provide similar characteristics as a PFC in that the current draw mimics that of a resistor. Since the radar system104is powered by DC voltage, the desired current is DC, even though a load profile of radar system104includes relatively large pulse currents. As with a PFC design, the output voltage of charge store108(i.e., the voltage at110), may also be relatively large. For a radar application, the delta voltage or delta charge provides an energy reservoir to support the pulse load.

A constant power draw from power source102may also be achieved by replacing PC106with a relatively large inductor and capacitor filter. In such a situation, PC controller114may permit the large inductor to be omitted, without alteration of charge store108, provided that VR122is not altered. Elimination of the inductor may provide weight and size savings. For high power radar systems with low pulse repetition frequencies, the size of this inductor is typically very large and heavy, elimination of which may provide significant savings in weight and size.

One or more features disclosed herein may be implemented in hardware, software, firmware, and combinations thereof, including discrete and integrated circuit logic, field programmable gate arrays (FPGAs), application specific integrated circuit (ASIC) logic, and microcontrollers, and may be implemented as part of a domain-specific integrated circuit package, and/or a combination of integrated circuit packages.

Software may include a computer readable medium encoded with a computer program including logic or instructions to cause a processor to perform one or more functions in response thereto. The computer readable medium may include a transitory and/or non-transitory medium. The processor may include a general purpose instruction processor, a controller, a microcontroller, and/or other instruction-based processor.

Methods and systems are disclosed herein with the aid of functional building blocks illustrating functions, features, and relationships thereof. At least some of the boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed.

While various embodiments are disclosed herein, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail may be made therein without departing from the spirit and scope of the methods and systems disclosed herein. Thus, the breadth and scope of the claims should not be limited by any of the examples disclosed herein.