Oscillator signal generation with spur mitigation in a wireless communication device

Techniques for generating oscillator signals in a wireless communication device are described. A phase-locked loop (PLL) may be used to generate an oscillator signal for a selected frequency channel. Different PLL settings may be used for the blocks in the PLL for different frequency channels. The different PLL settings may be for different PLL loop bandwidths, different amounts of charge pump current, different frequency equations associated with different sets of high and low divider ratios, different frequency division schemes associated with different prescaler ratios and/or different integer divider ratios, high side or low side injection for a super-heterodyne receiver or transmitter, and/or different supply voltages for one or more circuit blocks such as an oscillator. A suitable set of PLL settings may be selected for each frequency channel such that adverse impact due to spurs can be mitigated.

BACKGROUND

The present disclosure relates generally to electronics, and more specifically to techniques for generating oscillator signals in a wireless communication device.

A wireless communication device (e.g., a cellular phone) may have a transmitter and a receiver to support two-way radio communication with a wireless communication system. For data transmission, the transmitter may upconvert an output baseband signal with one or more transmit local oscillator (LO) signals to obtain an upconverted signal. The transmitter may further filter and amplify the upconverted signal to obtain an output radio frequency (RF) signal and may then transmit this signal via a wireless channel to base stations in the wireless system. For data reception, the receiver may receive signals from base stations and obtain a received RF signal. The receiver may amplify, filter and downconvert the received RF signal with one or more receive LO signals to obtain an input baseband signal. The LO signals may be generated based on oscillator signals, which may be generated by oscillators within the wireless device.

The wireless device typically includes various analog circuits to condition analog signals in the transmitter and receiver. The analog circuits may include amplifiers, mixers, filters, phase-locked loops (PLLs), LO generators, etc. The analog circuits may operate on analog signals with small signal levels. Hence, the analog circuits should be exposed to as little noise as possible in order to preserve signal quality and achieve good performance.

The wireless device also typically includes digital circuitry to digitally process data being transmitted and/or received. The digital circuitry may include processors, memories, controllers, etc., which may operate based on clocks. Digital circuits typically have large signal swings and generate lots of digital noise including spurs. A spur is an undesired signal at a specific frequency or tone and generated within the wireless device. Spurs may be generated by clocks, by mixing between clocks and oscillator signals, etc. The spurs from the digital circuits may have large levels because of the large and sharp signal swings of the digital circuits.

The spurs from the digital circuits may degrade the performance of the analog circuits in various manners. First, the oscillator signals used to generate the LO signals for frequency conversion by the analog circuits may contain the spurs, which may then degrade a desired signal being received or transmitted. Second, the spurs may mix with out-of-band signal components and generate inband noise that may degrade the signal-to-noise ratio (SNR) of the desired signal. Third, the spurs may appear at the receiver inputs and/or transmitter outputs in a frequency band of interest due to substrate or package coupling paths when the analog and digital circuits are integrated in the same integrated circuit (IC) and thereby degrade the SNR of the desired signal.

To mitigate the adverse effects due to spurs, the analog circuits may be isolated from the digital circuits, which may then reduce the coupling of the spurs from the digital circuits to the analog circuits. This isolation may be achieved by (i) implementing the analog and digital circuits on separate printed circuit boards or separate sections of a printed circuit board or (ii) implementing the analog circuits on one or more analog integrated circuit (IC) dies and implementing the digital circuits on one or more digital IC dies. However, it may be difficult to achieve the desired amount of isolation or to even predict the amount of isolation that can be achieved due to limitations of design tools. Furthermore, it may be desirable to integrate the analog and digital circuits (e.g., on the same IC die) in order to reduce size and cost. Thus, techniques that can mitigate the adverse effects of spurs are highly desirable.

SUMMARY

Techniques for generating oscillator signals in a wireless communication device with non-uniform frequency programming in order to mitigate the deleterious effects of spurs are described herein. A PLL may be used to generate an oscillator signal for a selected frequency channel. The PLL may include a phase frequency detector, a charge pump, a loop filter, and a divider. With non-uniform frequency programming, different PLL settings may be used for the various blocks in the PLL for different frequency channels. In general, a PLL setting may be for any parameter affecting the generation of an oscillator signal. A suitable set of PLL settings may be selected for each frequency channel such that the adverse effects of spurs can be mitigated and good performance can be achieved for the frequency channel.

In an aspect, different PLL loop bandwidths may be supported, and a suitable PLL loop bandwidth may be selected for each frequency channel. A narrow loop bandwidth may be selected when spurs are outside of the loop bandwidth in order to attenuate the spurs. A wider loop bandwidth may be used when spurs outside the loop bandwidth are not present at problematic frequencies in order to better suppress non-spurious noise sources, such as an oscillator. The loop bandwidth may be varied, e.g., by adjusting the amount of charge pump current.

In another aspect, different frequency equations may be supported, and a suitable frequency equation may be selected for each frequency channel. The different frequency equations may be associated with different sets of high and low divider ratios in a fractional-N divider. Different spurs and/or different spur levels may be present for different frequency equations. A frequency equation with good performance in terms of spurs may be selected for each frequency channel.

In yet another aspect, different frequency division schemes may be supported, and a suitable frequency division scheme may be selected for each frequency channel. The different frequency division schemes may be associated with different prescaler ratios and/or different integer divider ratios. Different spurs and/or different spur levels may be present for different frequency division schemes. A frequency division scheme with good performance in terms of spurs may be selected for each frequency channel.

In yet another aspect, either high side or low side injection may be selected for a frequency channel in a super-heterodyne receiver or transmitter. An LO signal is at a frequency higher than the selected frequency channel for high side injection and lower than the selected frequency channel for low side injection. High side and low side injection may be associated with different spurs and/or different spur levels. Either high side or low side injection may be selected based on performance in terms of spurs.

In yet another aspect, different supply voltages may be supported for a given circuit block, and a suitable supply voltage may be selected for the circuit block for each frequency channel. In one design, different supply voltages may be used for an oscillator. A high supply voltage may be used to increase the oscillator signal swing, which may reduce the adverse effects due to spurs. A low supply voltage may be used when large spurs are not present in order to save power.

The different PLL settings may also be for other parameters. Various aspects and features of the disclosure are described in further detail below.

DETAILED DESCRIPTION

FIG. 1shows a wireless communication device110capable of communicating with different wireless communication systems and networks. The terms “system” and “network” are often used interchangeably. In the example shown inFIG. 1, wireless device110may be capable of communicating with a wireless wide area network (WWAN)120, a wireless local area network (WLAN)130, a wireless personal area network (WPAN)140, a satellite positioning system (SPS)150, and a broadcast system160. In general, wireless device110may be capable of communicating with any number, any type, and any combination of one or more systems and networks.

WWAN120provides communication coverage for a large geographic area such as, e.g., a city, a state, or an entire country. WWAN120may be a Code Division Multiple Access (CDMA) network, a Time Division Multiple Access (TDMA) network, a Frequency Division Multiple Access (FDMA) network, an Orthogonal Frequency Division Multiple Access (OFDMA) network, a Single-Carrier FDMA (SC-FDMA) network, etc. A CDMA network may implement a radio technology such as cdma2000, Universal Terrestrial Radio Access (UTRA), etc. cdma2000 covers IS-2000, IS-95 and IS-856 standards. UTRA includes Wideband-CDMA (W-CDMA) and other variants of CDMA. A TDMA network may implement a radio technology such as Global System for Mobile Communications (GSM), Digital Advanced Mobile Phone System (D-AMPS), etc. An OFDMA system may implement a radio technology such as Evolved UTRA (E-UTRA), Ultra Mobile Broadband (UMB), IEEE 802.16 (WiMAX), IEEE 802.20, Flash-OFDM®, etc. UTRA and E-UTRA are part of Universal Mobile Telecommunication System (UMTS). 3GPP Long Term Evolution (LTE) is an upcoming release of UMTS that uses E-UTRA. These various networks, radio technologies, and standards are known in the art.

WLAN130provides communication coverage for a medium geographic area such as, e.g., a building, a home, etc. WLAN130may implement a radio technology such as any in the IEEE 802.11 family of standards, Hiperlan, etc. WPAN140provides communication coverage for a small geographic area. WPAN140may implement Bluetooth, which is a short-range radio technology adopted as IEEE 802.15 standard.

Satellite positioning system150may be the United States Global Positioning System (GPS), the Russian GLONASS system, the European Galileo system, or some other satellite positioning system. GPS is a constellation of 24 well-spaced satellites plus some spare satellites that orbit the earth. Each GPS satellite transmits an encoded signal that allows receivers on earth to accurately estimate their positions based on measurements for a sufficient number of satellites (typically four) and the known locations of these satellites. Broadcast system160may be a MediaFLO system, a Digital Video Broadcasting for Handhelds (DVB-H) system, an Integrated Services Digital Broadcasting for Terrestrial Television Broadcasting (ISDB-T) system, a Digital Multimedia Broadcasting (DMB) system, or some other broadcast system.

Wireless device110may be stationary or mobile and may also be referred to as a mobile station, a user equipment, a terminal, a station, a subscriber unit, etc. Wireless device110may be a cellular phone, a personal digital assistant (PDA), a wireless modem, a handheld device, a laptop computer, a cordless phone, etc. As shown inFIG. 1, wireless device110may communicate two-way with base stations122in WWAN120, an access point132in WLAN130, and/or a headset142in WPAN140at any given moment. Wireless device110may also receive signals from satellites152in SPS150and/or a broadcast station162in broadcast system160at any given moment. Wireless device110may process a received signal and/or generate a transmit signal for each system based on the radio technology used by that system.

FIG. 2shows a block diagram of a design of wireless device110. In this design, wireless device110includes a transceiver214having a receiver220aand a transmitter230afor WWAN120, a receiver220band a transmitter230bfor WLAN130, a receiver220cand a transmitter230cfor WPAN140, a receiver220dfor SPS150, and a receiver220efor broadcast system160. Each receiver220may process a received signal for an associated system and provide an input baseband signal to a digital processor250. Each transmitter230may receive an output baseband signal from digital processor250and generate a transmit signal for an associated system. An antenna switch module212couples receivers220athrough220eand transmitters230athrough230cto antennas210aand210b. Module212may include one or more switches, duplexers, diplexers, etc., to route the received signals from antennas210to receivers220and to route the transmit signals from transmitters230to antennas210. In general, wireless device110may include any number of antennas, any number of receivers, and any number of transmitters for any number of systems and frequency bands.

Digital processor250may include various processing units for data transmission and reception and for other functions. For example, digital processor250may include one or more digital signal processors (DSPs), reduced instruction set computer (RISC) processors, central processing units (CPUs), etc. A controller/processor260may control the operation at wireless device110. A memory262may store program codes and data for wireless device110. Data processor250, controller/processor260, and/or memory262may be implemented on one or more application specific integrated circuits (ASICs) and/or other ICs.

A reference oscillator268generates a reference signal having a frequency of fref, which is relatively precise. Oscillator268may be a crystal oscillator (XO), a voltage controlled crystal oscillator (VCXO), a temperature-compensated crystal oscillator (TCXO), a voltage-controlled TCXO (VC-TCXO), or some other type of oscillator. Frequency synthesizers270receive the reference signal and generate oscillator signals. LO generators272receive the oscillator signals from frequency synthesizers270and generate LO signals for receivers220and transmitters230. Frequency synthesizers270may include any number of PLLs to generate any number of oscillator signals. A clock generator274also receives the reference signal and generates clocks for digital processor250, controller/processor260, and memory262. All or part of receivers220athrough220e, transmitters230athrough230c, oscillator268, frequency synthesizers270, and/or LO generators272may be implemented on one or more radio frequency integrated circuits (RFICs), mixed-signal ICs, ASICs, etc.

In general, a transmitter or a receiver may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency converted between radio frequency (RF) and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for a receiver. In the direct-conversion architecture, which is also referred to as a zero-IF (ZIF) architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements.

Each system may operate on one or more frequency channels in one or more frequency bands. A frequency channel may also be referred to as a CDMA channel, an RF channel, etc. For cdma2000, each frequency channel has a bandwidth of 1.23 MHz and a center frequency located at 30 KHz raster or increment. For W-CDMA, each frequency channel has a bandwidth of 3.84 MHz and a center frequency located at 200 KHz raster. For GSM, each frequency channel has a bandwidth of 200 KHz and a center frequency located at 200 KHz raster. The center frequency and bandwidth of each frequency channel may be dependent on the system.

FIG. 3shows a block diagram of a design of a direct-conversion receiver220x, which may be used for any one of receivers220athrough220einFIG. 2. Within receiver220x, a low noise amplifier (LNA)310amplifies a received signal VRXfrom antenna switch module212and provides an amplified signal. A filter312filters the amplified signal to pass signal components in a frequency band of interest and to remove out-of-band noise and undesired signals. A mixer314frequency downconverts the filtered signal with an LO signal VRX—LOfrom LO generators272and provides a downconverted signal. The frequency of the LO signal, fRX—LO, is selected such that a desired signal in a selected frequency channel is downconverted to baseband or near-baseband.

A variable gain amplifier (VGA)316amplifies the downconverted signal with a variable gain and provides a signal having a desired signal level. A lowpass filter318filters the signal from VGA316to pass the desired signal in the selected frequency channel and to remove noise and undesired signals that may be generated by the downconversion process. An amplifier (Amp)320amplifies and buffers the signal from filter318and provides an input baseband signal VINto digital processor250.

FIG. 4shows a block diagram of a design of a super-heterodyne receiver220y, which may also be used for any one of receivers220athrough220einFIG. 2. Within receiver220y, a received signal VRXis amplified by an LNA410, filtered by a filter412, and downconverted from RF to IF by a mixer414with a first LO signal VRX—LO1from LO generators272. The frequency of the first LO signal, fRX—LO1, may be selected such that a desired signal in a selected frequency channel is downconverted to a specific IF frequency.

The IF signal from mixer414is amplified by a VGA416, filtered by a filter418, and downconverted from IF to baseband or near baseband by a mixer420with a second LO signal VRX—LO2from LO generators272. The frequency of the second LO signal, fRX—LO2, is dependent on the IF frequency. The downconverted signal from mixer420is filtered by a filter422and amplified by an amplifier424to obtain an input baseband signal VIN, which is provided to digital processor250.

FIG. 5shows a block diagram of a design of a direct-conversion transmitter230x, which may be used for any one of transmitters230athrough230cinFIG. 2. Within transmitter230x, an output baseband signal VOUTis amplified by an amplifier510, filtered by a lowpass filter512to remove images caused by digital-to-analog conversion, amplified by a VGA514, and upconverted from baseband to RF by a mixer516with an LO signal VTX—LOfrom LO generators272. The upconverted signal is filtered by a bandpass filter518to remove images caused by the frequency upconversion and further amplified by a power amplifier (PA)520to generate a transmit signal VTX.

FIG. 6shows a block diagram of a design of a super-heterodyne transmitter230y, which may also be used for any one of transmitters230athrough230cinFIG. 2. Within transmitter230y, an output baseband signal VOUTis amplified by an amplifier610, filtered by a lowpass filter612, amplified by a VGA614, and upconverted from baseband to IF by a mixer616with a first LO signal VTX—LO1from LO generators272. The IF signal is filtered by a filter618, amplified by a VGA620, and upconverted from IF to RF by a mixer622with a second LO signal VTX—LO2from LO generators272. The upconverted signal is filtered by a bandpass filter624and further amplified by a power amplifier626to generate a transmit signal VTX.

FIGS. 3 through 6show some example transmitter and receiver designs. In general, the conditioning of the signals in a transmitter or a receiver may be performed by one or more stages of amplifier, filter, mixer, etc. These circuit blocks may be arranged differently from the configurations shown inFIGS. 3 through 6. Furthermore, other circuit blocks not shown inFIGS. 3 through 6may be used to condition the signals in the transmitter and receiver. Some circuit blocks inFIGS. 3 through 6may also be omitted. For example, filters312and412inFIGS. 3 and 4may be omitted, and the output of the LNAs may be coupled directly to the mixers.

FIG. 7shows a block diagram of a design of a frequency synthesizer700, which may be used for frequency synthesizers270inFIG. 2. Frequency synthesizer700includes a PLL702and a VCO740. VCO740generates a VCO signal having a frequency of fVCO, which is determined by a control signal VCTRLfrom a loop filter730in PLL702.

Within PLL702, a divider750divides the VCO signal in frequency by a factor of Rkand provides a feedback signal. In general, Rkmay be an integer or non-integer value and may be determined as described below. A phase-frequency detector (PFD)710receives the reference signal from oscillator268and the feedback signal from divider750. Detector710compares the phases of the two signals and provides a detector signal that indicates the phase difference/error between the two signals. A charge pump720generates an error signal ICPthat is proportional to the detected phase error. Loop filter730filters the error signal and provides the control signal for VCO740. Loop filter730adjusts the control signal such that the phase and frequency of the feedback signal is locked to the phase and frequency of the reference signal. Loop filter730has a frequency response that may be selected to achieve the desired closed-loop response for PLL702. For example, the frequency response of loop filter730may be selected based on a tradeoff between acquisition and tracking performance and noise performance.

An LO generator760may be used for LO generators272inFIG. 2. LO generator760may receive the VCO signal from VCO740and provide an LO signal having a frequency of fLO. LO generator760may include a buffer, a divider, a quadrature splitter, etc. In one design, VCO740operates at the LO frequency, so that fVCO=fLO. In another design, VCO740operates at S times the LO frequency, so that fVCO=S·fLO, and the VCO signal may be divided in frequency by an integer factor of S to obtain the LO signal.

A voltage regulator770may generate a supply voltage VDD—VCOfor VCO740, a supply voltage VDD—DIVfor divider750, and possibly other supply voltages for other blocks within frequency synthesizer700. In general, voltage regulator770may generate any number of supply voltages for any number of blocks within frequency synthesizer700.

FIG. 7shows an example design of PLL702and frequency synthesizer700. PLL702and frequency synthesizer700may also include different and/or additional blocks. Each block within PLL702may be implemented with digital circuits, analog circuits, or a combination of both.

In the design shown inFIG. 7, various blocks within PLL702or frequency synthesizer700may be controlled based on respective controls to achieve good performance. A PFD_Control may adjust the gain of phase frequency detector710. A CP_Control may adjust the amount of current via current sources722aand722bwithin charge pump720, which would vary the gain of the charge pump. An LF_Control may adjust the values of circuit components (e.g., capacitors) within loop filter730. A VCO_Control may adjust the values of circuit components (e.g., capacitors) within VCO740to achieve the desired frequency of oscillation. A Divider_Control may select a suitable overall divider ratio Rkand determine the configuration of divider750, as described below. A VR_Control may set the supply voltages for VCO740, divider750, etc. In general, a frequency synthesizer may include one or more controls for one or more blocks within the frequency synthesizer. A frequency synthesizer may include all or a subset of the controls shown inFIG. 7and may also include other controls not shown inFIG. 7.

FIG. 7shows frequency synthesizer700and LO generator760for generating one VCO signal and one LO signal, respectively. Multiple frequency synthesizers and multiple LO generators760may be used to generate multiple VCO signals and multiple LO signals at the same time. For example, two frequency synthesizers700may be used to generate two VCO signals, and two LO generators may be used to generate two LO signals at frequencies of fRX—LO1and fRX—LO2for super-heterodyne receiver220yinFIG. 4. LO frequency fRX—LO1may be variable and dependent on the selected frequency channel whereas LO frequency fRX—LO2may be at a fixed IF frequency. In general, any number of frequency synthesizers700and any number of LO generators760may be used to generate any number of VCO signals and any number of LO signals, which may be for any number of receivers and transmitters.

Frequency synthesizer700may support multiple frequency channels for one or more systems and one or more frequency bands. Each frequency channel has a specific center frequency. Frequency synthesizer700may be controlled to generate the proper VCO signal, which may be used by LO generator760to generate the LO signal at the proper frequency and with the desired characteristics for the selected frequency channel. For example, the desired VCO frequency fVCOmay be obtained by choosing the proper overall divider ratio Rkfor divider750. The desired VCO signal characteristics may be obtained by controlling the gain of phase frequency detector710, the amount of current in charge pump720, the component values of loop filter730, the configuration of divider750, and/or the supply voltages for VCO740, divider750, etc.

The analog and digital circuits in wireless device110may be implemented in close proximity to one another. For example, the analog and digital circuits may be implemented on the same printed circuit board or the same IC die. As IC fabrication technology improves, it may be possible to design high-frequency (e.g., GHz) analog circuits with complementary metal oxide semiconductor (CMOS) technology, which has been used primarily for digital circuits. This may then allow for integration of the analog and digital circuits on the same IC die. However, the digital circuits typically generate lots of spurs, which may couple to the analog circuits via substrate and/or other mechanisms. The spurs may adversely impact the performance of the analog circuits and make it difficult to integrate the analog circuits with the digital circuits.

Spurs may be generated within wireless device110in various manners. Spurs may be generated by clocks within wireless device110and may appear at harmonics of these clocks. For example, clocks may be generated based on the reference signal from oscillator268, and spurs at harmonics of frefmay be prevalent within wireless device110. Higher-frequency clocks (e.g., in the hundreds of MHz) may be generated by clock generator274and provided to digital processor250and other digital circuits. Spurs may then be present at harmonics of the higher-frequency clocks. Spurs may also be generated by the mixing of clock harmonics and VCO frequencies. For example, spurs may be generated at frequencies of fVCO±n·fref, where n is the n-th harmonic of the reference signal. If the LO frequency is obtained by dividing the VCO frequency by a factor of S, then spurs may be generated at frequencies of fVCO/S±n·fref. Wireless device110may thus have fixed spurs at specific frequencies (e.g., at clock harmonics) as well as channel-dependent spurs at frequencies determined based on the VCO frequency fVCOand the configuration of the PLL for the selected frequency channel.

Frequency programming refers to the programming of various blocks within a PLL or a frequency synthesizer to obtain the desired frequency and characteristics for a VCO signal. The PLL may support multiple frequency channels and may be programmed in similar manner for all supported frequency channels. For example, all frequency channels may have the same settings for all blocks within the PLL except for the overall divider ratio Rkin divider750. In this case, some of the supported frequency channels may observe excessive degradation due to spurs while other frequency channels may not experience spur problems.

In an aspect, non-uniform frequency programming may be used to avoid spurs or to reduce spur levels for the frequency channels supported by wireless device110. With non-uniform frequency programming, different settings may be used for the blocks within a PLL or a frequency synthesizer for different frequency channels. A suitable set of PLL settings may be selected for each frequency channel such that the adverse effects due to spurs can be mitigated and good performance can be achieved for the frequency channel. Non-uniform frequency programming may be supported with one or more of the following:Use of different PLL loop bandwidths,Use of different frequency equations,Use of different frequency division schemes,Use of high side or low side injection for super-heterodyne architecture, andUse of different supply voltages for blocks within the frequency synthesizer.

In an aspect, the PLL loop bandwidth may be adjusted based on the frequency location of the spurs. The PLL may be designed to have a nominal loop bandwidth (e.g., tens of KHz), which may be selected based on a tradeoff between acquisition and tracking performance and noise performance. If spurs are located outside of the loop bandwidth, then the loop bandwidth may be reduced to achieve more rejection of the spurs. A smaller loop bandwidth may be obtained by decreasing the gain of phase frequency detector710, decreasing the amount of current from charge pump720, selecting a larger capacitor value for loop filter730, etc. Conversely, if spurs located within the loop bandwidth are due to direct coupling of spurs to the VCO, then the loop bandwidth may be increased to reduce the inband gain from the VCO, which may then reduce the spur levels. A larger loop bandwidth may be obtained by increasing the gain of phase frequency detector710, increasing the amount of current from charge pump720, selecting a smaller capacitor value for loop filter730, etc. A suitable loop bandwidth may be selected for each frequency channel based on the spurs observed for that frequency channel. The loop bandwidth selection may be based on computer simulation, empirical measurement, field testing, etc.

FIG. 8shows a block diagram of a divider750a, which is a design of divider750within PLL702inFIG. 7. Within divider750a, an integer divider810divides the VCO signal in frequency by an integer factor of Mk, which may be equal to 1, 2, 3, 4, etc. Divider ratio Mkmay be configurable for frequency channel k and may be selected by an M_Select signal. A switch812routes the output of divider810to one of T prescalers814athrough814tbased on a P_Select signal, where T may be any integer value. Each prescaler814may divide the signal from divider810in frequency by a factor of either U or U+1 at any given moment, where U may be different for different prescalers. For example, prescaler814amay divide by either 8 or 9 (for U1=8), and so on, and prescaler814tmay divide by either 4 or 5 (for UT=4). A multiplexer (Mux)816routes a prescaled signal from the selected prescaler814to a fractional-N divider818. The prescaled signal has a frequency of fPRE, which may be expressed as:

fPRE=fVCOMk·Pk,Eq⁢⁢(1)
where fVCOis the frequency of the VCO signal, and

Pkis the prescaler ratio for the prescaler selected for frequency channel k.

The VCO signal may be used by LO generator760to generate the LO signal at the LO frequency. The LO frequency fLOis dependent on the center frequency of frequency channel k and may correspond to fRX—LOfor LO signal VRX—LOinFIG. 3, fRX—LO1for LO signal VRX—LO1inFIG. 4, fTX—LOfor LO signal VTX—LOinFIG. 5, or fTX—LO2for LO signal VTX—LO2inFIG. 6.

The prescaler ratio Pkis dependent on the divider ratios Ukand Uk+1 of the selected prescaler as well as the percentage of time that each divider ratio is used. For example, if the selected prescaler for frequency channel k divides by Uk+1 for V out of W cycles and divides by Ukfor the remaining W−V cycles, then the prescaler ratio may be given as Pk=Uk+V/W. V and W may be fixed values or may be dependent on frequency channel k.

Divider818divides the prescaled signal from multiplexer816in frequency by an integer factor of either NLor NHbased on a divider select signal from a sigma-delta modulator830. Divider818may divide by NLsome of the time and by NHthe remaining time to obtain the desired frequency for the feedback signal.

In one design, a divider control unit832receives the selected frequency channel and determines a divider ratio Nkfor divider818, which may be expressed as:

The divider ratio Nkfor frequency channel k ranges between integer values of NLand NH, or NL≦Nk≦NH. The divider ratio Nkmay be expressed based on NLand NHas follows:
Nk=(1−Frack)·NL+Frack·NH,  Eq (3)
where Frackis the percentage of time to use NH, and (1−Frack) is the percentage of time to use NL. Frackmay be determined as follows:

Frack=(Nk-NLNH-NL).Eq⁢⁢(4)
For example, if Nk=NH, then Frack=1, NHis used all the time, and NLis not used.

Divider control unit832may receive an N_Select signal that indicates the values of NLand NHfor frequency channel k. Unit832may determine Frackas shown in equation (4) and then quantize Frackto L bits. L may be selected to achieve the desired frequency resolution and may be equal to 10, 16, 23, etc. Unit832provides the L-bit Frackto sigma-delta modulator830.

Sigma-delta modulator830receives the L-bit Frackand generates the divider select signal for divider818. In one design, the divider select signal is a 1-bit control that instructs divider818to divide by either NLor NH. For example, a logic low (‘0’) on the divider select signal may correspond to divide by NL, and a logic high (‘1’) on the divider select signal may correspond to divide by NH. The percentage of ones on the divider select signal is determined by Frack. However, the ones are distributed on the divider select signal in a manner such that quantization noise is shifted to higher frequencies and good phase noise characteristic is achieved for the VCO signal from VCO740.FIG. 8shows the use of sigma-delta modulator830to select between NLand NHfor divider818. The selection of NLor NHfor divider818may also be made in other manners.

FIG. 9shows a block diagram of a divider750b, which is another design of divider750within PLL702inFIG. 7. Within divider750b, a switch910routes the VCO signal to one of T divider chains912athrough912t. Each divider chain912includes an integer divider914that divides by an integer value of M, a prescaler916that divides by either U or U+1, and a fractional-N divider918that divides by either NLor NH. A multiplexer920provides a signal from the selected divider chain912as the feedback signal.

In one design, the prescaler ratio Pkand the divider ratio Nkfor frequency channel k may be jointly determined, as follows:

Zk=Nk·Pk=fVCOMk·fref,Eq⁢⁢(5)
where Zkis a combined divider ratio for both prescaler916and fractional-N divider918in the selected divider chain912for frequency channel k. Zkmay range between integer values of ZLand ZH, or ZL≦Zk≦ZH. ZLmay be defined as ZL=NL+Uk, and ZHmay be defined as ZH=NH+Uk+1. ZLand ZHmay also be defined in other manners.

The combined divider ratio Zkmay be expressed based on ZLand ZHas follows:
Zk=(1−Frack)·ZL+Frack·ZH,  Eq (6)
where Frackis the percentage of time to use ZH, and (1−Frack) is the percentage of time to use ZL. Frackmay be determined as follows:

A divider control unit932may receive the frequency channel and the N_Select signal for frequency channel k. Unit932may determine Frackas shown in equation (7) and then quantize Frackto L bits. A sigma-delta modulator930may receive the L-bit Frackfrom unit930and generate the divider select signal for both prescaler916and divider918in the selected divider chain912.

FIGS. 8 and 9show two example designs of divider750. In general, divider750may be implemented with various designs having a fixed or configurable integer divider, a fixed or configurable prescaler, and a fixed or configurable fractional-N divider. The integer divider, prescaler, and fractional-N divider for each frequency channel may be controlled together or separately.

In another aspect, multiple frequency equations may be defined for each supported frequency channel. Combining equations (1) through (3), a frequency equation may be expressed as:
fVCO=Mk·Pk·[(1−Frack)·NL+Frack·NH]·fref·  Eq (8)

Similarly, combining equations (5) and (6), a frequency equation may be expressed as:
fVCO=Mk·[(1−Frack)·ZL+Frack·ZH]·fref·  Eq (9)

Multiple frequency equations may be defined for each frequency channel with different sets of values for NLand NHin equation (8) or different sets of values for ZLand ZHin equation (9). In one design, if N=└Nk┘ where “└ ┘” is a floor operator, then a first frequency equation may be defined with NL=N and NH=N+1, a second frequency equation may be defined with NL=N and NH=N+2, a third frequency equation may be defined with NL=N−1 and NH=N+1, a fourth frequency equation may be defined with NL=N−1 and NH=N+2, etc. As an example, if Nk=8.7 for the design inFIG. 8, then N=8 and a first frequency equation may be defined with divider818dividing by either 8 or 9, a second frequency equation may be defined with divider818dividing by either 8 or 10, a third frequency equation may be defined with divider818dividing by either 7 or 10, and a fourth frequency equation may be defined with divider818dividing by either 7 or 11. In general, different frequency equations may be defined for different values of delta between NLand NH, or Δ=NH−NL, where Δ is equal to 1, 2, 3 and 4 in the design above. For each frequency equation, the percentage of time to divide by NLand the percentage of time to divide by NHare determined by Frack, which is dependent on the divider ratio Nkas well as the values of NLand NH. The values of NLand NHfor the selected frequency channel may be indicated by the N_Select signal, which may be provided to unit832and divider818.

In another design, sigma-delta modulator830or930receives the L-bit Frackfrom divider control unit832or932and generates a Q-bit divider select signal for divider818or918, where Q may be any integer value greater than one. Divider818or918may divide the prescaled signal by one of 2Qpossible integer divider ratios, as determined by the Q-bit divider select signal. Different frequency equations may be defined for different values of Q. Different frequency equations may also be defined in other manners.

Different frequency equations may provide different performance with respect to spurs. In one design, one frequency equation (e.g., with Δ=1) may be used as a default frequency equation. For each frequency channel observing excessive degradation due to spurs with the default frequency equation, each of the remaining frequency equations may be evaluated. The frequency equation that provides the best performance with respect to spurs and possibly other factors may be selected for the frequency channel. Performance may be quantified by various metrics such as SNR, error vector magnitude (EVM), bit error rate (BER), packet error rate (PER), etc. EVM is a measure of magnitude and phase errors of modulation symbols due to errors in a transmit LO signal, where the errors may be due to spurs. In general, phase noise of the LO signal may be worse for larger values of Δ at certain offset frequencies, but the improvement due to mitigation of spurs may more than offset the degradation in phase noise and may improve performance.

In yet another aspect, different frequency division schemes may be available, and a suitable frequency division scheme may be selected for each frequency channel. A frequency division scheme includes a specific value for each divider ratio used to divide the VCO signal in frequency. In the designs shown inFIGS. 8 and 9, the overall divider ratio Rkfor frequency channel k may be expressed as:

A frequency division scheme is defined by a specific value for each of the divider ratios Mk, Pkand Nk. Different frequency division schemes may be defined with different sets of values for Mk, Pkand Nkfor a given value of Rk. In one design, T different frequency division schemes may be defined with T prescaler ratios P1through PT. Nkmay be modified accordingly for each prescaler ratio. As an example, for a given VCO frequency fVCO, prescaler ratios of 8/9 and 4/5 result in different prescaled signal frequencies fPRE, which in turn result in different divider ratios Nk. In another design, different frequency division schemes may be defined with different integer divider ratios Mk. A larger value of Mkresults in the selected prescaler operating at a lower frequency, which may save power. In general, different frequency division schemes may be defined for frequency channel k with different values of Pkand/or different values of Mk. For each set of values for Pkand Mk, Nkmay be selected to obtain the desired overall divider ratio Rkfor frequency channel k.

Different frequency division schemes may have different spurs and/or different spur levels. A frequency division scheme may be selected for each frequency channel to achieve good performance for that frequency channel. In one design, a set of default values may be used for Pkand Mk. For each frequency channel observing excessive degradation due to spurs with the default set of values for Pkand Mk, other possible sets of values for Pkand Mkmay be evaluated. The frequency division scheme that provides good performance (e.g., the lowest spur levels) may be selected for the frequency channel.

In yet another aspect, either a high side LO signal or a low side LO signal may be used for frequency conversion in a super-heterodyne receiver or transmitter to avoid spurs. For super-heterodyne receiver220yinFIG. 4, the received signal may be downconverted from RF to IF by mixer414with the LO signal VRX—LO1. The frequency of this LO signal is higher than the selected frequency channel for high side injection and is lower than the selected frequency channel for low side injection. The frequency of the LO signal for high side and low side injection may be expressed as:
fRX—LO1—HS=fCH+fIF, and
fRX—LO1—LS=fCH−fIF,  Eq (11)
where fIFis the IF frequency,

fCHis the center frequency of the selected frequency channel,

fRX—LO1—HSis the LO frequency for high side injection, and

fRX—LO1—LSis the LO frequency for low side injection.

High side and low side LO signals may be obtained by selecting appropriate values for the overall divider ratio Rk. For each frequency channel, the spur levels with the high side LO signal may be compared against the spur levels with the low side LO signal. The LO signal with lower spur levels may be selected for the frequency channel.

In yet another aspect, different supply voltages may be used for VCO740, divider750, and/or other blocks in PLL700in order to mitigate the adverse effects of spurs. VCO740may be operated at one of multiple possible supply voltages, e.g., 1.8 Volts (V), 2.0 V, 2.2 V, etc. A low supply voltage may save power whereas a high supply voltage may increase VCO signal swing. A system may have stringent specifications at certain offset frequencies, e.g., 400 KHz and 1.8 MHz for GSM. When large spurs are located far away from the PLL loop bandwidth, adjusting the PLL loop bandwidth may have marginal impact. Instead, increasing the supply voltage for VCO740may increase the VCO signal swing, which may then sharpen the transition edges of the VCO signal and reduce the effects due to the spurs. A larger VCO supply voltage may be used when needed, e.g., when spurs of sufficiently high levels are located within frequency ranges with stringent specifications. A lower VCO supply voltage may be used in other scenarios to save power. In general, the VCO signal swing may be adjusted by adjusting the VCO supply voltage, a VCO bias current, a bias resistor with a fixed VCO supply voltage, etc., or any combination thereof.

All or part of divider750may be operated at one of multiple possible supply voltages. The integer divider, prescaler, fractional-N divider, sigma-delta modulator and/or divider control unit may be sources of large spurs. For each block that may be a source of large spurs, the supply voltage for that block may be controlled to reduce the magnitude of the spurs generated by the block. Variable supply voltages may be applied to the integer divider, prescaler, fractional-N divider, sigma-delta modulator, divider control unit, or any combination thereof. The variable supply voltages may be dependent on the selected frequency channel.

FIG. 10shows a design of a table1000of PLL settings for different frequency channels with non-uniform frequency programming. Table1000may be generated for all frequency channels supported by wireless device110and may include one entry or rows for each supported frequency channel. A frequency channel may be for the downlink (receiver) or uplink (transmitter) in a specific system. Table1000may also include columns for different PLL settings, which may be for circuit blocks within a PLL as well as circuit blocks (e.g., VCO) external to the PLL. In the design shown inFIG. 10, table100includes one column for PLL loop bandwidth, one column for frequency equation (e.g., divider ratios NLand NHas shown in table1000, or divider ratios ZLand ZH), one column for frequency division scheme (e.g., divider ratios Mkand Pk), one column to indicate low side or high side injection, one column for overall divider ratio Rk, and one column for VCO supply voltage. For each frequency channel, a suitable value may be selected for the parameter(s) in each column to achieve good performance for that frequency channel. For each frequency channel, the desired PLL loop bandwidth may be obtained via the PFD_Control for phase frequency detector710, the CP_Control for charge pump720, and/or the LF_Control for loop filter730.

For each frequency channel, the overall divider ratio Rkmay be selected to obtain the desired LO frequency. For a super-heterodyne receiver or transmitter, Rkmay also be selected based on whether high side or low side injection is selected for the frequency channel. For each frequency channel, the divider ratios NLand NH(or ZLand ZH) may be obtained based on the frequency equation selected for that frequency channel from among all available frequency equations. For each frequency channel, the divider ratios Pkand/or Mkmay be obtained based on the frequency division scheme selected for that frequency channel from among all available frequency division schemes. The values of NL, NH, Pkand Mkmay be provided to divider750via the Divider_Control. For each frequency channel, the VCO supply voltage may be selected from among multiple available supply voltages, and the selected supply voltage may be indicated by the VR_Control.

FIG. 10shows a design of a table that may be used to store PLL settings for different frequency channels with non-uniform frequency programming. The low side or high side injection column and the overall divider ratio column may be omitted since the information in these columns may be incorporated in the divider ratios NL, NH, Pkand Mk. In general, the PLL settings for the supported frequency channels may be stored using any data structure.

FIG. 11shows a design of a process1100for generating an oscillator signal, e.g., a VCO signal. A frequency channel may be selected from among multiple frequency channels (block1112). Each frequency channel may be associated with a set of PLL settings for at least one parameter in addition to overall divider ratio Rk, which may be inherently different for different frequency channels. The multiple frequency channels may be associated with at least two different sets of PLL settings. A set of PLL settings for the selected frequency channel may be determined, e.g., from a frequency programming table such as table1000inFIG. 10(block1114). The oscillator signal for the selected frequency channel may be generated based on the set of PLL settings (block1116).

The set of PLL settings for the selected frequency channel may comprise a setting selecting one of multiple PLL loop bandwidths. One or more blocks within the PLL may be set to achieve a PLL loop bandwidth for the selected frequency channel. The set of PLL settings for the selected frequency channel may comprise a setting selecting one of multiple different amounts of charge pump current. A control signal for a VCO may be generated based on the amount of charge pump current for the selected frequency channel.

The set of PLL settings for the selected frequency channel may comprise a divider setting selecting one of multiple frequency equations, which may be associated with different sets of high and low divider ratios. A divider may be programmed with a set of high and low divider ratios for the selected frequency channel. The divider may then divide the oscillator signal in frequency based on this set of high and low divider ratios.

The set of PLL settings for the selected frequency channel may comprise a frequency division setting selecting one of multiple frequency division schemes for dividing the oscillator signal in frequency. The multiple frequency division schemes may be associated with different prescaler ratios, different integer divider ratios, etc. The oscillator signal may be divided in frequency based on a prescaler ratio and/or an integer divider ratio for the selected frequency channel.

The set of PLL settings for the selected frequency channel may comprise a setting selecting either high side or low side injection for an LO signal, which may be generated based on the oscillator signal. The LO signal may be generated at a frequency higher than the selected frequency channel if high side injection is selected or at a frequency lower than the selected frequency channel if low side injection is selected.

The set of PLL settings for the selected frequency channel may comprise a setting selecting one of multiple supply voltages for a circuit block such as a VCO, a divider, etc. A supply voltage chosen for the selected frequency channel may be generated and applied to the circuit block. The set of PLL settings for the selected frequency channel may comprise a setting for a bias current control for the circuit block. The bias current control chosen for the selected frequency channel may be generated and applied to the circuit block. In general, a PLL setting may select one of multiple biasing schemes for a circuit block, and the multiple biasing schemes may correspond to different supply voltages, or different bias currents, or both for the circuit block.

The sets of PLL settings for the multiple frequency channels may also be for different and/or additional parameters.

The oscillator signal generation techniques described herein may provide certain advantages. First, by using different PLL settings for different frequency channels, the adverse effects due to spurs may be mitigated, and good performance may be achieved for each frequency channel. Second, the techniques may allow for integration of digital and analog circuits on the same IC die, which may reduce cost, size, etc.

In another aspect, non-uniform frequency programming may be used to control the operation of the transmitters and/or receivers in wireless device110. Various parameters of a transmitter or a receiver may be controlled based on the selected frequency channel. For a receiver, the LNA bias current and/or gain, mixer bias current and/or gain, filter bandwidth, VGA gain, etc., may be set based on the selected frequency channel. For a transmitter, the PA bias current and/or gain, mixer bias current and/or gain, filter bandwidth, VGA gain, etc., may be set based on the selected frequency channel. With non-uniform frequency programming, different settings may be used for the blocks within the transmitter or receiver for different frequency channels. A suitable set of transceiver settings may be selected for each frequency channel to achieve good performance for that frequency channel. Each frequency channel may thus be associated with a set of transceiver settings for at least one parameter in the transmitter or receiver in addition to overall divider ratio Rk. The different frequency channels may be associated with at least two different sets of transceiver settings. The set of transceiver settings for a selected frequency channel may be applied to the transmitter or receiver.

The techniques described herein may be implemented by various means. For example, the techniques may be implemented in hardware, firmware, software, or a combination thereof. For a hardware implementation, the various blocks described herein may be implemented on one or more ASICs, DSPs, digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, electronic devices, other electronic units designed to perform the functions described herein, a computer, or a combination thereof.

The circuits described herein (e.g., frequency synthesizers270and700, LO generators272and760, PLL702, etc.) may be implemented on an IC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB), etc. The circuits may also be fabricated with various IC process technologies such as CMOS, N-channel MOS (N-MOS), P-channel MOS (P-MOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

Certain aspects of the techniques may be implemented with firmware and/or software (e.g., modules such as procedures, functions, etc.) that perform the functions described herein. The firmware and/or software instructions/code may be stored in a memory (e.g., memory262inFIG. 2) and executed by a processor (e.g., processor260). The memory may be implemented within the processor or external to the processor. The firmware and/or software instructions/code may also be stored in a computer/processor-readable medium such as random access memory (RAM), read-only memory (ROM), non-volatile random access memory (NVRAM), programmable read-only memory (PROM), electrically erasable PROM (EEPROM), FLASH memory, floppy disk, compact disc (CD), digital versatile disc (DVD), magnetic or optical data storage device, etc. The instructions/code may be executable by one or more processors and may cause the processor(s) to perform certain aspects of the functionality described herein.

An apparatus implementing the techniques described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.