Semiconductor device

A first p+-type region in contact with a bottom of a gate trench is disposed in a striped shape extending along a first direction that is orthogonal to a second direction along which the gate trench extends in a striped shape, as viewed from a front surface of a silicon carbide substrate. As a result, trench gate MOSFETs are disposed in parallel at a predetermined cell pitch along the first direction. A flat SBD is disposed at a predetermined cell pitch along the second direction. The cell pitch of the trench gate MOSFET and the cell pitch of the flat SBD may be set independently of each other.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2018-042674, filed on Mar. 9, 2018, the entire contents of which are incorporated herein by reference.

BACKGROUND

Embodiments discussed herein relate to a semiconductor device.

2. Description of the Related Art

Conventionally, to realize low ON resistance in a vertical metal oxide semiconductor field effect transistor (MOSFET) that uses silicon carbide (SiC), a trench gate structure is employed that structurally facilitates low ON resistance characteristics as compared to a planar gate structure in which a MOS gate is provided in a flat plate shape on a front surface of a semiconductor substrate (hereinafter, silicon carbide substrate (semiconductor chip)) containing silicon carbide. The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed at the front surface of the silicon carbide substrate, enabling reduction of the ON resistance by shortening cell pitch (repetition interval of a unit cell (constituent unit of an element)).

Further, a Schottky barrier diode (SBD) is disposed in a flat plate shape on the front surface of the silicon carbide substrate disposed with the trench gate MOSFET, whereby degradation of a parasitic pn junction diode (body diode) formed by a pn junction of a base region and a drift region of the trench gate MOSFET may be suppressed (for example, refer to Japanese Laid-Open Patent Publication No. 2008-021930). A structure of a conventional trench gate MOSFET will be described in which, on the front surface of the silicon carbide substrate in which a trench gate MOSFET is disposed in this manner, a SBD (hereinafter, flat SBD) is disposed in a flat plate shape, whereby the flat SBD is built into the same silicon carbide substrate.

FIGS. 7 and 8are cross-sectional views of an example of a structure of a conventional silicon carbide semiconductor device.FIGS. 7 and 8depict cross-sectional views of the structure at cutting line AA-AA′ inFIG. 9. InFIGS. 7 and 8, examples are depicted in which in the conventional silicon carbide semiconductor device depicted, the flat SBD142is disposed at mutually differing cell pitches P112, P112′. Configuration (structure of the unit cell of a trench gate MOSFET141, structure of the unit cell of the flat SBD142) excluding the cell pitch P112of the flat SBD142is similar inFIGS. 7 and 8.FIG. 9is a plan view of a layout when main parts inFIGS. 7 and 8are viewed from a front surface of the semiconductor substrate.FIG. 9depicts a layout of a gate trench107and first to third p+-type regions121to123inFIGS. 7 and 8.

The conventional silicon carbide semiconductor device depicted inFIGS. 7 and 8has a configuration in which at a front surface of a silicon carbide substrate110that contains silicon carbide, a trench (hereinafter, gate trench)107in which a MOS gate of the trench gate MOSFET141is embedded is disposed at a predetermined pitch P101, and between adjacent gate trenches107, a unit cell of the trench gate MOSFET141or a unit cell of the flat SBD142is disposed. The unit cell of the trench gate MOSFET141and the unit cell of the flat SBD142are disposed at predetermined cell pitches (indicated by reference characters P111and P112inFIG. 7, and reference characters P111′ and P112′ inFIG. 8), respectively. The silicon carbide substrate110is an epitaxial substrate in which an n−-type silicon carbide layer131constituting an n−-type drift region102is formed by epitaxial growth on an n+-type starting substrate101containing silicon carbide.

The trench gate MOSFET141has a p-type base region104, an n+-type source region105, and a p+-type contact region106between adjacent gate trenches107(in a mesa region103a). A single unit cell of the trench gate MOSFET141is configured by a region between centers of the adjacent gate trenches107; the p-type base region104, the n+-type source region105, and the p+-type contact region106being between the centers of the adjacent gate trenches107. The p+-type region121is in contact with a bottom of the gate trench107. In the mesa region103a, the second and the third p+-type regions122,123are each selectively disposed separated from the p+-type region121.

The second and the third p+-type regions122,123are disposed separated from the gate trench107. Further, the second p+-type region122is disposed separated from the p-type base region104and opposes the p+-type contact region106along a depth direction Z. The third p+-type region123is disposed between the p-type base region104and the second p+-type region122, and is in contact with the p-type base region104, the p+-type contact region106, and the second p+-type region122. In the mesa region103ain which the flat SBD142is disposed, the p-type base region104, the n+-type source region105, the p+-type contact region106, and the third p+-type region123are not provided, and an n-type current diffusion region103is exposed at the front surface (surface on a side of the silicon carbide substrate110having the n−-type silicon carbide layer131) of the silicon carbide substrate110.

A single unit cell of the flat SBD142is configured by a Schottky junction of the n-type current diffusion region103and a conductive layer112disposed on the front surface of the silicon carbide substrate110, in a region between the first p+-type regions121. The gate trench107is disposed in parallel at the predetermined pitch P101along a direction (hereinafter, first direction) X parallel to the front surface of the silicon carbide substrate110. Further, the gate trench107(darkly hatched part), as viewed from the front surface of the silicon carbide substrate110, is disposed in a striped layout extending along a direction (hereinafter, second direction) Y parallel to the front surface of the silicon carbide substrate110and orthogonal to the first direction X (refer toFIG. 9).

The first to the third p+-type regions121to123(lightly hatched parts), similarly to the gate trench107, are disposed along the first direction X, in a striped layout extending along the second direction Y, as viewed from the front surface of the silicon carbide substrate110. In this manner, the trench gate MOSFET141and the flat SBD142are disposed at predetermined cell pitches (reference characters P111, P112inFIG. 7, and reference characters P111′, P112′ inFIG. 8) along the first direction X. Reference numeral111is a conductive layer forming an ohmic contact with the n+-type source region105and with the p+-type contact region106. Reference numerals113,114, and115are an interlayer insulating film, a front electrode, and a rear electrode, respectively.

Further, as depicted inFIG. 7, a unit cell of the trench gate MOSFET141and a unit cell of the flat SBD142are disposed repeatedly alternating along the first direction X. In this case, the cell pitch P111of the trench gate MOSFET141is 2 times the pitch P101of the gate trench107(P111=2×P101). The cell pitch P112of the flat SBD142is substantially equal to the pitch P101of the gate trench107(P112≈P101).

As depicted inFIG. 8, for every 2 unit cells of the trench gate MOSFET141disposed adjacently along the first direction X, 1 unit cell of the flat SBD142is disposed adjacently along the first direction X. In this case, the cell pitch P111of the trench gate MOSFET141′ is 3/2 times the pitch P101of the gate trench107(P111′=(3/2)×P101). The cell pitch P112′ of the flat SBD142is substantially 2 times the pitch P101of the gate trench107(P112′≈2×P101).

When the cell pitch P111of the trench gate MOSFET141′ is smaller (refer toFIG. 8), ON resistance of the trench gate MOSFET141decreases. When the cell pitch P112of the flat SBD142is smaller (refer toFIG. 7), operation starting current of a p-intrinsic-n (pin) diode of the trench gate MOSFET141increases, the pin diode being formed by pn junctions between the p-type base region104and the n−-type drift region102and the n+-type starting substrate101. As a result, a degradation suppression effect of a body diode (parasitic pn junction diode formed by a pn junction between the p-type base region104and the n−-type drift region102) of the trench gate MOSFET141improves.

As a conventional trench gate MOSFET, a device has been proposed that realizes reduced loss and suppression of degradation of a body diode by a normally-off junction FET (JFET) disposed on a same semiconductor substrate as a trench gate MOSFET being operated so that only reflux current flows in the JFET (for example, refer to Japanese Laid-Open Patent Publication No. 2015-162579 (paragraphs 0022, 0050, and 0109; FIG. 5)).

As a conventional trench gate MOSFET having a SBD built into the same silicon carbide substrate, a device has been proposed that reduces the cell pitch of a trench gate MOSFET and realizes reduced ON resistance by embedding only a metal layer in a trench provided separated from a gate trench and by forming at the bottom of the trench, a Schottky junction between an n-type drift region and the metal layer (for example, refer to Japanese Laid-Open Patent Publication No. 2017-055005 (paragraphs 0037 and 0126; FIG. 5)).

SUMMARY

According to an embodiment of the present invention, a semiconductor device includes a semiconductor substrate of a first conductivity type and containing a semiconductor material having a bandgap wider than that of silicon; a plurality of trenches provided a predetermined depth from a front surface of the semiconductor substrate, the plurality of trenches being provided at a predetermined pitch along a first direction parallel to the front surface of the semiconductor substrate; a gate electrode provided in the trench, via a gate insulating film; a first semiconductor region of a second conductivity type provided spanning between adjacent trenches of the plurality of trenches, in a first mesa region between the adjacent trenches; a second semiconductor region of the first conductivity type selectively provided in the first semiconductor region; a MOS gate structure constituted by the gate insulating film, the gate electrode, the first semiconductor region and the second semiconductor region; a conductive layer sandwiched between adjacent trenches of the plurality of trenches and provided on a surface of a second mesa region excluding the first mesa region; a Schottky barrier diode configured by a Schottky junction of the conductive layer and the semiconductor substrate; a third semiconductor region of the second conductivity type selectively provided in the semiconductor substrate, the third semiconductor region in contact with bottoms of the plurality of trenches; a fourth semiconductor region of the second conductivity type selectively provided between the first semiconductor region and the third semiconductor region, the fourth semiconductor region being provided in contact with the first semiconductor region and the third semiconductor region, and separated from the plurality of trenches; a first electrode electrically connected to the first semiconductor region, the second semiconductor region, and the conductive layer; and a second electrode provided at a rear surface of the semiconductor substrate. The plurality of trenches are disposed in a striped shape extending along a second direction orthogonal to the first direction and parallel to the front surface of the semiconductor substrate. The third semiconductor region is disposed in a striped shape extending along the first direction.

In the embodiment, one unit cell of the MOS gate structure is provided in one first mesa region. The unit cell of the MOS gate structure is disposed at a predetermined pitch along the first direction.

In the embodiment, a unit cell of the Schottky barrier diode is disposed at a predetermined pitch along the second direction.

In the embodiment, for every two of the first mesa regions disposed adjacently to each other along the first direction, one of the second mesa regions is disposed.

In the embodiment, the semiconductor device further includes a fifth semiconductor region of the first conductivity type provided in a surface layer of the front surface of the semiconductor substrate, the fifth semiconductor region reaching a position deeper from the front surface of the semiconductor substrate than are the bottoms of the plurality of trenches, the fifth semiconductor region having an impurity concentration higher than an impurity concentration of the semiconductor substrate. The first semiconductor region, the third semiconductor region, and the fourth semiconductor region are disposed in the fifth semiconductor region.

DESCRIPTION OF EMBODIMENTS

First, problems associated with the related arts will be described. In the described conventional silicon carbide semiconductor device, when the cell pitch P111of the trench gate MOSFET141′ is reduced (refer toFIG. 8), the cell pitch P112′ of the flat SBD142increases. On the other hand, when the cell pitch P112of the flat SBD142is reduced (refer toFIG. 7), the cell pitch P111of the trench gate MOSFET141increases. Therefore, reduction of the ON resistance of the trench gate MOSFET141and improvement of the degradation suppression effect of the body diode have a tradeoff relationship.

A semiconductor device according to an embodiment is configured using as a semiconductor material, a semiconductor material (wide bandgap semiconductor material) that has a bandgap wider than that of silicon (Si). Hereinafter, a structure of the semiconductor device according to the embodiment will be described taking, as an example, a case in which silicon carbide (SiC) is used as a semiconductor material.FIG. 1is a plan view of a layout when main parts of a silicon carbide semiconductor device according to the embodiment are viewed from a front surface of a semiconductor substrate.FIG. 1depicts a layout of a gate trench7and first and second p+-type regions (third and fourth semiconductor regions)21,22inFIGS. 2 and 3.FIG. 2is a cross-sectional view of the structure at cutting line A-A′ inFIG. 1.FIG. 3is a cross-sectional view of the structure at cutting line B-B′ inFIG. 1.

The silicon carbide semiconductor device according to the embodiment depicted inFIGS. 1 to 3has a structure in which on a front surface of a semiconductor substrate (silicon carbide substrate (semiconductor chip))10containing silicon carbide and in which a trench gate MOSFET41is disposed, a SBD (flat SBD)42is disposed in a flat plate shape. The silicon carbide substrate10is an epitaxial substrate in which an n−-type silicon carbide layer31constituting an n−-type drift region2is formed by epitaxial growth on a front surface of an n+-type starting substrate1containing silicon carbide.

The n−-type silicon carbide layer31has a surface layer (surface layer of the front surface of the silicon carbide substrate10) on a first side that is opposite a second side facing toward the n+-type starting substrate1. An n-type region (hereinafter, n-type current diffusion region (fifth semiconductor region))3is provided to a depth shallower from the front surface of the silicon carbide substrate10than is a depth to which the n−-type silicon carbide layer31is provided. The n-type current diffusion region3is a so-called current spreading layer (CSL) that reduces carrier spreading current. The n-type current diffusion region3is provided uniformly parallel to the front surface of the silicon carbide substrate10.

A part (i.e., a part between the n-type current diffusion region3and the n+-type starting substrate1) of the n−-type silicon carbide layer31excluding the n-type current diffusion region3is the n−-type drift region2. A p-type base region (first semiconductor region)4, an n+-type source region (second semiconductor region)5, a p+-type contact region6, and a trench (gate trench)7of the trench gate MOSFET41, and the first and the second p+-type regions21,22are each selectively provided in the n-type current diffusion region3. Without providing the n-type current diffusion region3, the n−-type silicon carbide layer31entirely may be set as the n−-type drift region2, and the p-type base region4, the n+-type source region5, the p+-type contact region6, the gate trench7, and the first and the second p+-type regions21,22may be provided in the n−-type drift region2.

The gate trench7is provided from the front surface of the silicon carbide substrate10, to a depth shallower than a depth to which the n-type current diffusion region3is provided. The gate trench7is disposed at a predetermined pitch P1along a direction (first direction) X parallel to the front surface of the silicon carbide substrate10. Further, as viewed from the front surface of the silicon carbide substrate10, the gate trench7(darkly hatched part) is disposed in a striped layout parallel to the front surface of the silicon carbide substrate10and extending along a direction (hereinafter, second direction) Y orthogonal to the first direction X (refer toFIG. 1).

In the gate trench7, a gate electrode9is provided via a gate insulating film8. A MOS gate of the trench gate MOSFET41is constituted by the gate trench7, the gate insulating film8, and the gate electrode9. Between adjacent gate trenches7is a mesa region3aand in each mesa region3a, a unit cell of the trench gate MOSFET41or a unit cell of the flat SBD42is disposed.

In the mesa region (first mesa region)3ain which the trench gate MOSFET41is disposed, the p-type base region4, the n+-type source region5, and the p+-type contact region6are disposed. A MOS gate structure is constituted by the p-type base region4, the n+-type source region5, the p+-type contact region6, and the MOS gate (the gate trench7, the gate insulating film8, and the gate electrode9). The p-type base region4is provided spanning between the adjacent gate trenches7and opposes the gate electrodes9, across the gate insulating films8at side walls of the gate trenches7.

The n+-type source region5and the p+-type contact region6are each selectively provided in the p-type base region4and are exposed at the front surface of the silicon carbide substrate10. The n+-type source region5opposes the gate electrodes9, across the gate insulating films8at the side walls of the gate trenches7. The p+-type contact region6may penetrate the p-type base region4in the depth direction Z. The depth direction Z is a direction from the front surface of the silicon carbide substrate10, toward a rear surface.

One unit cell of the trench gate MOSFET41is configured by a region between the gate trenches7that are adjacent to each other across the p-type base region4, the n+-type source region5, and the p+-type contact region6. The unit cell of the trench gate MOSFET41is disposed in parallel at a predetermined cell pitch P11along the first direction X. In other words, in each of the mesa regions3ain which the trench gate MOSFET41is disposed, 1 unit cell of the trench gate MOSFET41is disposed.

The cell pitch P11of the trench gate MOSFET41is set to be as small as possible. For example, along the first direction X, for every two of the mesa regions3adisposed adjacently to each other and in each of which a unit cell of the trench gate MOSFET41is disposed, one of the mesa regions3ain which a unit cell of the flat SBD42is disposed may be disposed. In this case, the cell pitch P11of the trench gate MOSFET41is 3/2 times the pitch P1of the gate trench7(P11=(3/2)×P1).

The p+-type region21(light hatching), as viewed from the front surface of the silicon carbide substrate10, is disposed in a striped layout extending along the first direction X (refer toFIG. 1). In other words, each linear part21aformed by the striped layout of the first p+-type region21is disposed so as to be substantially orthogonal to the striped layout of the gate trenches7and oppose all of the gate trenches7in the depth direction Z, selectively contacting bottoms of the gate trenches7.

The linear parts21aof the first p+-type region21are disposed separated from the p-type base region4. The second p+-type region22is selectively provided between the linear parts21aof the first p+-type region21and the p-type base region4. The second p+-type region22is in contact with the p-type base region4(when the p+-type contact region6penetrates the p-type base region4in the depth direction Z, the p-type base region4and the p+-type contact region6) and the first p+-type region21.

The second p+-type region22, for example, opposes the p+-type contact region6in the depth direction Z. The second p+-type region22is disposed separated from the gate trench7and is disposed only in the mesa regions3ain which the trench gate MOSFET41is disposed. The second p+-type region22, for example, is disposed only between the linear parts21aof the first p+-type region21and the p-type base region4and is disposed at a predetermined interval along the second direction Y. InFIG. 1, the second p+-type region22is indicated by a dotted line.

The flat SBD42is configured by a Schottky junction of the n-type current diffusion region3and a conductive layer12disposed on the front surface of the silicon carbide substrate10. The p-type base region4, the n+-type source region5, the p+-type contact region6, and the second p+-type region22are not provided in the mesa region (second mesa region)3ain which the flat SBD42is disposed. Further, in the mesa region3ain which the flat SBD42is disposed, the n-type current diffusion region3is exposed at the front surface of the silicon carbide substrate10(surface on a side of the silicon carbide substrate10having the n−-type silicon carbide layer31).

A cell pitch P12of the flat SBD42is determined by a width of the linear parts21aof the first p+-type region21and an arrangement interval (pitch) along the second direction Y. A reason for this is that spreading resistance of the first p+-type region21greatly affects electrical characteristics of the flat SBD42. Therefore, a direction along which the unit cells of the flat SBD42are disposed in parallel (the second direction Y) is orthogonal to a direction (the first direction X) along which the unit cells of the trench gate MOSFET41are disposed in parallel.

In the mesa regions3ain which the trench gate MOSFET41is disposed, on the front surface of the silicon carbide substrate10, a conductive layer11is provided forming an ohmic contact with the p+-type contact region6and the n+-type source region5exposed at a contact hole13a. The conductive layer11functions as a source electrode of the trench gate MOSFET41. The conductive layer11, for example, as viewed from the front surface of the silicon carbide substrate10, is disposed in a linear shape extending along the second direction Y (refer toFIG. 1). InFIG. 1, in the mesa regions in which the trench gate MOSFET41and the flat SBD42are disposed, respectively, a region between two dotted lines coarser than those of the second p+-type region22depicted between the gate trenches7are the conductive layers11,12.

In the mesa region3ain which the flat SBD42is disposed, on the front surface of the silicon carbide substrate10, the conductive layer12is provided, forming a Schottky contact with the n-type current diffusion region3exposed at a contact hole13b. The conductive layer12functions as the source electrode of the trench gate MOSFET41. The conductive layer11, for example, as viewed from the front surface of the silicon carbide substrate10, is disposed in a linear shape extending along the second direction Y. The conductive layer12, for example, as viewed from the front surface of the silicon carbide substrate10, is disposed in a linear shape extending along the second direction Y (refer toFIG. 1).

The contact holes13a,13b, for example, as viewed from the front surface of the silicon carbide substrate10, are each disposed in a linear shape extending along the second direction Y. On the front surface of the silicon carbide substrate10, a front electrode (first electrode)14is provided so as to be embedded in the contact holes13a,13b. The front electrode14is in contact with the conductive layers11,12, is electrically connected to the conductive layers11,12, and is electrically insulated from the gate electrode9by an interlayer insulating film13. A rear electrode (second electrode)15is provided at the rear surface (rear surface of the n+-type starting substrate1) of the silicon carbide substrate10overall. The rear electrode15is electrically connected to the n+-type starting substrate1constituting an n+-type drain region.

As described, according to a first embodiment, the first p+-type region in contact with the bottoms of the gate trenches is disposed in a striped shape extending along a direction (first direction) orthogonal to a direction (second direction) along which the gate trenches provided in a striped shape extend, as viewed from the front surface of the silicon carbide substrate. As a result, the trench gate MOSFET may be disposed in parallel at a predetermined cell pitch along the first direction and the flat SBD may be disposed in parallel at a predetermined cell pitch along the second direction. Therefore, the cell pitch of the trench gate MOSFET and the cell pitch of the flat SBD may be set independently of each other. As a result, the cell pitch of the trench gate MOSFET may be reduced, reducing the ON resistance of the trench gate MOSFET and enabling the cell pitch of the flat SBD to be reduced and the degradation suppression effect of the body diode of the trench gate MOSFET to be improved. Therefore, the tradeoff relationship of reduction of the ON resistance of the trench gate MOSFET and improvement of the degradation suppression effect of the body diode may be improved.

A relationship of the ON resistance of the trench gate MOSFET41and the operation starting current of the body diode was verified. The body diode of the trench gate MOSFET41is a parasitic pin diode formed by pn junctions between the p-type base region4of the trench gate MOSFET41and the n−-type drift region2and the n+-type starting substrate1.FIG. 4is a characteristics diagram depicting the relationship of the ON resistance of the trench gate MOSFET and the operation starting current of the body diode, in the silicon carbide semiconductor device according to the embodiment.

The relationship of the ON resistance of the trench gate MOSFET41and the operation starting current of the body diode in the above silicon carbide semiconductor device according to the embodiment (hereinafter, first example) is depicted inFIG. 4. Further, inFIG. 4, a relationship of the ON resistance of the trench gate MOSFET141and operation starting current of the body diode in the conventional silicon carbide semiconductor device (hereinafter, conventional example, refer toFIGS. 7 to 9) is depicted. The conventional example is similar to the first example, excluding arrangement of the unit cell of the flat SBD142, which differs from the arrangement in the first example.

From the results depicted inFIG. 4, in the first example, it was confirmed that when the ON resistance of the trench gate MOSFET41is equal to the ON resistance of the trench gate MOSFET141in the conventional example (for example, sample51of the first example and sample52of the conventional example), the operation starting current of the body diode of the trench gate MOSFET41may be higher than the operation starting current of the body diode of the trench gate MOSFET141of the conventional example. In other words, it was confirmed that as compared to the conventional example, in the first example, a direction (direction indicated by arrow C inFIG. 4(direction upward toward left)) of improvement of the tradeoff relationship between reducing the ON resistance of the trench gate MOSFET41and improving the degradation suppression effect of the body diode, was changeable.

InFIG. 4, while only one sample (sample51) of the first example is depicted, it was confirmed that in the first example, the ON resistance of the trench gate MOSFET41decreases as the cell pitch P11of the trench gate MOSFET41is reduced (refer toFIG. 5described hereinafter), and suppression of the degradation of the body diode of the trench gate MOSFET41increases as the cell pitch P12of the flat SBD42is reduced (refer toFIG. 6described hereinafter). In addition, for samples of the first example other than the sample51, it was confirmed that effects similar to those of the sample51of the first example are obtained.

A relationship of the cell pitch P11of the trench gate MOSFET41and ON resistance was verified.FIG. 5is a characteristics diagram depicting a relationship of the cell pitch of trench gate MOSFET and ON resistance in the silicon carbide semiconductor device according to the embodiment. InFIG. 5, the cell pitch P11(=the cell pitch P11of the trench gate MOSFET41/the pitch P1of the gate trench7) of the trench gate MOSFET41with respect to the pitch P1of the gate trench7is indicated along a horizontal axis while the ON resistance of the trench gate MOSFET41is indicated along a vertical axis.

The relationship of the cell pitch P11of the trench gate MOSFET41and ON resistance in the above silicon carbide semiconductor device according to the embodiment (hereinafter, second example) is depicted inFIG. 5. The trench gate MOSFET41has a breakdown voltage of 1200V (1200V-class). The breakdown voltage (withstand voltage) is a voltage limit at which errant operation or damage of an element does not occur. During measurement of the ON resistance of the trench gate MOSFET41, a pn junction temperature Tj of the n−-type drift region2and the p-type base region4of the trench gate MOSFET41was room temperature (RT), for example, about 25 degrees C.

From the results depicted inFIG. 5, in the second example, it was confirmed that as the cell pitch P11of the trench gate MOSFET41is reduced, the ON resistance may be reduced.

A relationship of the cell pitch P12of the flat SBD42and the operation starting current of the body diode of the trench gate MOSFET41was verified.FIG. 6is a characteristics diagram depicting a relationship of the cell pitch of the flat SBD and drain current density at the start of operation of the body diode of the trench gate MOSFET, in the silicon carbide semiconductor device according to the embodiment. InFIG. 6, the cell pitch P12(=the cell pitch P12of the flat SBD42/the pitch P1of the gate trench7) of the flat SBD42with respect to the pitch P1of the gate trench7is depicted along a horizontal axis and the drain current density at the start of operation of the body diode of the trench gate MOSFET41is depicted along a vertical axis.

The relationship of the cell pitch P12of the flat SBD42and the operation starting current of the body diode of the trench gate MOSFET41in the silicon carbide semiconductor device according to the embodiment (hereinafter, third example) is depicted inFIG. 6. The trench gate MOSFET41had a breakdown voltage of 1200V. During measurement of the operation starting current of the body diode of the trench gate MOSFET41, the pn junction temperature Tj of the n−-type drift region2and the p-type base region4of the trench gate MOSFET41was 175 degrees C.

From the results depicted inFIG. 6, it was confirmed that in the third example, as the cell pitch P12of the flat SBD42is reduced, the operation starting current of the body diode of the trench gate MOSFET41may be increased.

In the foregoing, the present invention may be modified within a range not departing from the spirit of the invention. For example, in the embodiment above and the examples, dimensions, impurity concentrations, etc. of components are variously set according to necessary specifications. Further, in the embodiment above, while a case is described where an epitaxial substrate is used in which an epitaxial layer is deposited on the semiconductor substrate (starting substrate), without limitation hereto, for example, all regions configuring the device may be diffusion regions formed by ion implantation in the semiconductor substrate.

Further, while the present invention is described taking a MOSFET as an example, without limitation hereto, the present invention is applicable to a MOS semiconductor device such as an insulated gate bipolar transistor (IGBT), a rectification semiconductor device such as a Schottky barrier diode (SBD), etc. Further, the present invention achieves similar effects even when a wide bandgap semiconductor material (for example, gallium (Ga)) other than silicon carbide is used. Further, the present invention is similarly implemented when conductivity types (n-type, p-type) are reversed.

According to the present invention, the cell pitch of the MOS gate structure (trench gate MOSFET) and the cell pitch of the Schottky barrier diode (flat SBD) may be set independently of each other.

The semiconductor device according to the present invention achieves an effect in that the tradeoff relationship between reducing the ON resistance of the trench gate MOSFET having the flat SBD built into the same semiconductor substrate and improving the degradation suppression effect of the body diode, may be improved.

As described, the semiconductor device according to the present invention is useful for MOS semiconductor devices having a trench gate structure with a flat SBD built into a single semiconductor substrate and is particularly suitable for MOS silicon carbide semiconductor devices having a trench gate structure.