Adaptive active bias compensation technique for power amplifiers

A power amplifier circuit (10) for a TDMA transmitter. The amplifier circuit (10) includes an FET amplifier (14), a current sensing resistor (24) that senses the quiescent drain current of the FET amplifier (14), and a switch (26) coupled across the sensing resistor (24). When data transmission bursts are being amplified by the amplifier circuit (10), a switch signal closes the switch (26) to bypass the sensing resistor (24) so that it does not dissipate power and reduce the efficiency of the amplifier circuit (10). When the data transmission is between data bursts, the switch signal opens the switch (26) to allow a voltage drop across the sensing resistor (24). The voltage drop is measured to determine the quiescent drain current of the FET amplifier (14) to maintain the drain current at the desirable operating point.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to a power amplifier circuit employing a technique for maintaining the amplifier's operating point constant over time and, more particularly, to a power amplifier circuit employing a current sensing resistor that is switched into the power amplifier circuit when the amplifier circuit is in a quiescent state to measure and maintain the small signal gain and linearity of the amplifier constant over time.

2. Discussion of the Related Art

Communications systems that transmit RF signals carrying information typically employ power amplifiers to amplify the transmit signal so that it has enough power to be received and deciphered by a receiver at a distant location. Digital communication systems of this type typically have highly complex and highly precise modulation waveforms in order to maximize utilization and revenue from precisely assigned radio frequency band allocations. Thus, the specifications of a digital communications system and its associated components usually are very strict. For example, precise spectral control must be maintained in the system over varying operating conditions and environments and over the system life.

Power amplifiers are among the most critical components of a digital communications system because they directly affect the linearity, distortion and spectral control of the transmit signal. Nonlinearities within the power amplifier introduce signal harmonics, inter-modulation products and other distortions and spurious counterparts of the RF signal being transmitted that cause interfering signals to other frequency channels. Additionally, the power amplifiers must maintain a constant small signal gain (SSG) despite the fluctuations in loading, drive and device aging that may act on the amplifier. In particular, for the commonly employed laterally diffused metal oxide semiconductor (LDMOS) transistor amplifier, the SSG will vary as the quiescent drain current of the amplifier changes due to amplifier aging and temperature changes.

Because it is necessary that the SSG performance of a power amplifier remains constant over the transmitter circuit lifetime, which may be years, various techniques are known in the art to ensure that the SSG remains constant. For example, because most of the drift in the quiescent drain current of the amplifier occurs during the initial 10-20 hours of operation, it is known in the art to set the quiescent drain current of the amplifier at a value higher than the desired operation point of the amplifier, and then allow the quiescent current to drift into the nominal operating condition after several hours of operation. However, not only will the power amplifier circuit operate outside of its desired operating point at the beginning of the amplifier's life when the drift in the quiescent current is greatest, the amplifier quiescent current will also continue to drift past the desired operating point towards the end of its useful life. This results in a less than optimum performance at the beginning and towards the end of the amplifier's life.

It has heretofore also been known to “bum in” an amplifier at the beginning to allow the quiescent drain current of the amplifier to stabilize prior to setting the operating point of the amplifier. However, this is an expensive alternative in a high volume production environment because many amplifiers are required to be burned in for several hours, significantly increasing cost of production. Also, the “bum in” technique does not affect the drift of the SSG towards the end of the amplifier's useful life.

Some amplifier circuits employ active DC bias compensation to maintain the SSG constant throughout the life of the amplifier. For example, some power amplifier circuits incorporate a low value sensor resistor in series with the drain or collector supply of the output of the transistor amplifier. The resistor is typically part of a current mirror within a feedback loop in the amplifier circuit that sets the gate voltage of the transistor amplifier, or base current for bipolar applications, which sets the quiescent drain current of the transistor amplifier. Alternatively, the amplifier circuit may employ an analog-to-digital (A/D) converter to measure the voltage across the sensor resistor, and a microcontroller to set the gate voltage, and hence the quiescent drain current of the transistor amplifier.

Due to the small value of the sensor resistor, these amplifier circuits employing an active DC bias typically have poor accuracy. A larger sensor resistor improves accuracy, but degrades the efficiency of the amplifier circuit during operation due to the power dissipated in the sensor resistor. In the case of the more elaborate approach of using A/D converters and microcontrollers, the cost of monitoring, measuring and controlling the quiescent drain current while the power amplifier is in operation is difficult and expensive. In all cases, the sensor resistor reduces the maximum output power of the amplifier, thereby degrading the linearity of the amplifier.

SUMMARY OF THE INVENTION

In accordance with the teachings of the present invention, a power amplifier circuit is disclosed for a TDMA transmitter. The amplifier circuit employs an FET amplifier and a current sensing element, such as a resistor, that senses the quiescent drain current of the amplifier. The amplifier circuit also includes a switch coupled across the current sensing resistor that is responsive to a switch signal identifying when TDMA data transmission bursts are being amplified by the amplifier circuit. When the data transmission bursts are being amplified by the amplifier circuit, the switch signal closes the switch to bypass the current sensing resistor so that it does not dissipate power and reduce the efficiency and linearity of the amplifier circuit during data transmission. When the data transmission is between bursts, the switch signal opens the switch to provide a voltage potential across the sensing resistor that is indicative of the quiescent drain current of the FET amplifier. The sensed voltage is applied to a gated sample and hold circuit that compares the sensed voltage to a reference voltage. In one embodiment, the sensed voltage is level translated prior to being applied to the sample and hold circuit. The difference between the reference voltage and the sensed voltage is used to adjust a DC bias signal applied to the gate terminal of the FET amplifier to maintain the drain current or SSG of the amplifier at the desirable operating point over time.

Additional objects, advantages and features of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The following discussion of the embodiments of the invention directed to a power amplifier circuit that provides selective quiescent drain current sensing at the drain terminal of an MOSFET amplifier is merely exemplary in nature, and is in no way intended to limit the invention or its applications or uses.

FIG. 1is schematic block diagram of a power amplifier circuit10, according to an embodiment of the present invention. The amplifier circuit10can be employed in a transmitter associated with a digital communications system, and particularly a time division multiple access (TDMA) digital communications system, where packets of digital data are transmitted in bursts as determined by a TDMA coding system, as is well understood to those skilled in the art. In the amplifier circuit10, a TDMA digital base-band circuit of the transmitter is represented at reference number12. The TDMA circuit12provides a signal to the amplifier circuit10indicating when the transmitter is transmitting data, and when the transmitter is in a quiescent state between data transmission bursts.

The amplifier circuit10includes a power amplifier14that amplifies an RF signal including digital data modulated thereon applied to an RF input port16. The amplified RF signal is output on an RF output port18to be transmitted. Capacitors C1and C2are DC blocking capacitors that prevent DC signals in the circuit10from propagating into the ports16and18. Capacitors C3and C4are filtering capacitors that reduce switching noise. In this embodiment, the power amplifier14is an LDMOS field effect transistor (FET) amplifier, well known to those skilled in the art. However, in other embodiments, the amplifier14may be other FETs, such as metal semiconductor field effect transistors (MESFETs), junction field effect transistors (JFETs), GaAs FETs, as well as bipolar transistors. The RF signal to be amplified is applied to a gate terminal of the FET amplifier14that correspondingly changes the current flow at a drain terminal of the FET amplifier14to amplify the signal. The source terminal of the FET amplifier14is coupled to ground. Inductors L1and L2operate as RF chokes (RFC) that serve to isolate the RF signals from the ports16and18and the digital portions of the circuit10.

A DC bias voltage, discussed below, is applied to the gate terminal of the FET amplifier14through the inductor L1. According to the invention, the amplifier circuit10senses the quiescent current at the drain terminal of the FET amplifier14only at those times when no data bursts are being amplified, and thus does not suffer from the limitations of the prior art discussed above. When the quiescent current is measured, it is used to adjust the DC bias applied to the FET amplifier14to provide adaptive selection of the DC bias that enables stabilization of the SSG over time, and effectively compensates for the normal aging characteristics due to Vgsdrift and transistor variations due to temperature. Because the sensing element, discussed below, is by-passed during data bursts, no losses in the DC power distribution is incurred during data transmission. Therefore, maximum DC to RF efficiency is realized.

According to the invention, a current sensing element24, here a resistor, is employed to provide a voltage drop that is indicative of the drain current of the FET amplifier14. A switch26is provided across the sensing element24that acts as a shunt to bypass the current flow around the sensing element24. The switch26can be any switch suitable for the purposes discussed herein, for example, a P-channel MOSFET, a bipolar transistor, or a mechanical relay. As will be discussed in detail below, the switch26is closed when the data bursts are being amplified by the circuit10so that the current flow travels around the element24and there is no voltage drop across the sensing element24. Between data bursts, the switch26is open so that the current flow travels through the sensing element24and there is a voltage drop across the sensing element24that is indicative of the quiescent current at the drain terminal of the FET amplifier14. A signal from the TDMA circuit12controls the switch26so that it is opened and closed at the proper time.

The circuit10includes an optional voltage level translator28that may be required depending on the DC voltage potential Vdd used by the circuit10. The level translator28can be any circuit suitable for the purposes described herein, such as an active current mirror circuit or a resistive divider network. The level translator28provides an equivalent or proportional voltage to that across the sensing element24to a voltage level referenced, to ground potential. Particularly, because the sensing element24is directly coupled to the DC supply input at Vdd, the voltage at the sensing element24may be relatively high, 24-28 volts in one embodiment. However, the DC bias applied to the gate terminal of the FET amplifier14may be relatively low, 3-5 volts in one embodiment.

The level translated voltage from the level translator28is applied to a gated sample and hold circuit34. The sample and hold circuit34forces the translated voltage as close as possible to a reference voltage from a voltage reference source32by a negative feedback through the amplifier circuit10. The reference voltage can be any convenient level, sourced from a stable source such as a bandgap reference if a constant quiescent current is desired, or a thermally varying source, if gain compensation over temperature is desired. The feedback regulates the current through the sensing element24, which sets the quiescent drain current of the FET amplifier14. In this implementation, the TDMA circuit12also provides the necessary timing for the transfer of the updated bias levels to the DAC, discussed below. Altematively, the proper sequencing could be generated internally in the sample and hold circuit34.

The level translated voltage and the reference voltage are applied to a comparator30within the sample and hold circuit34. The comparator30can be any comparator suitable for the purposes described herein. The comparator30outputs a logic level that is dependent on the difference between the translated voltage and the reference voltage that is applied to a digital counter38. In an alternate embodiment, the counter38could be replaced with a digital potentiometer.

If the translated voltage is greater than the reference voltage, then the output of the comparator30configures the digital counter38to be decremented by the TDMA circuit12. If the translated voltage is less than the reference voltage then the output of the comparator30configures the counter38to be incremented by the TDMA circuit12. This allows the circuit34to vary the current DC bias signal applied to the gate terminal of the FET amplifier14until the desired quiescent drain current at the drain terminal of the FET amplifier14is attained based on the relationship of the translated voltage across the sensing element24to the reference voltage.

The count value from the counter38is applied to a digital-to-analog (DAC) converter36that converts the digital count value to an analog signal that represents the new proper DC bias voltage for the FET amplifier14that would cause the FET amplifier14to generate the desired quiescent drain current or SSG. Changes to the count values occur only between RF transmission bursts. During transmissions, the TDMA circuit12prevents the DAC36from updating the DC bias, which would otherwise cause distortion. Thus, the sequence of operation of the sample and hold circuit34is the comparator30first compares the reference voltage to the level translated voltage, then at the next clock cycle the counter38is updated, and then at the next clock cycle the DAC36is updated, which allows the DAC36to update the gate voltage of the FET amplifier14between transmission bursts.

In an alternate embodiment, the sample and hold circuit34could be an analog system, employing, for example, a loop filter with a switched capacitor type sample and hold device.

Because the sensing element24is only switched into the circuit between data bursts, it does not act as a lossy element during data transmission, and does not dissipate power during transmission of data that affects the amplifier circuits efficiency. Because the quiescent drain current is very small, in order to get an accurate representation of the drain current, it would be desirable to provide a large resistor for the sensing element24to provide a large voltage drop across it. Therefore, the value of the resistor sensing element24can be made larger than those typically employed in the prior art. For example, in the know systems, values on the order of 0.1 ohms or less would be employed as a compromise between being able to sense quiescent currents, which may typically be in the 600 to 800 milliamp range, but not dissipate excessive power during transmission burst where peak currents may typically be in the 6 amp range. In the implementation of the invention, much larger values, such as 1-10 ohms, could be readily used. Because it can be made relatively large, a larger voltage drop is provided across the sensing element24which increases the accuracy for providing the desired quiescent drain current. This lessens the sensitivity of the sensing element24to noise in the circuit10. Thus, more accurate sensing of the drain current can be achieved in the amplifier circuit10than could be achieved in the known amplifier circuits that employed active current sensing of the quiescent current.