Display device subpixel activation patterns

A display device includes a data driver, a multiplexer, and a multiplexer controller. The data driver outputs a data voltage through output buffers. The multiplexer distributes each of the data voltages output by the output buffers to data lines in a time division manner in response to first to control signals. The multiplexer controller sequentially outputs control signals in a time division manner. Each control signal transitions to a gate ON voltage during a prior horizontal period and maintains the gate ON voltage for an intended horizontal period.

BACKGROUND

This application claims the priority benefit of Korean Patent Application No. 10-2016-0158735 filed on Nov. 25, 2016, which is hereby incorporated herein by reference for all purposes as if fully set forth herein.

TECHNICAL FIELD

The present disclosure relates to a display device which consumes less power.

DESCRIPTION OF THE RELATED ART

A flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting display device, and the like. In a flat panel display device, data lines and gate lines are disposed to intersect with each other, and regions in which a data line and the gate line intersect with each other is defined as a single subpixel. A plurality of subpixels is formed in a panel. In order to drive each subpixel, a video data signal desired to be displayed is supplied to the data lines and a gate pulse is sequentially supplied to the gate lines. The video data signal is supplied to subpixels of a display line to which the gate pulse is supplied, and as all the data lines are sequentially scanned by the gate pulse, video data is displayed.

The video data signal provided to the data lines is generated by a data driver, and the data driver outputs a data voltage through a source channel connected to the data line. In order to reduce the number of source channels, a structure in which a plurality of data lines are connected to one source channel and a data voltage output to the source channel is supplied to the data lines in a time division manner using a multiplexer is used. The multiplexer includes switches selectively connecting the source channel and the plurality of data lines, and the switches are turned on in response to a control signal to connect the source channel and one data line.

As resolution of a display panel is increased, a time period during which a data voltage is supplied to one horizontal line is shortened, and accordingly, an output period of control signals for controlling switches is also shortened. Specifically, a period during which control signals from the multiplexer are reversed from a gate ON voltage to a gate OFF voltage or from a gate OFF voltage to a gate ON voltage is shortened. When reversing of a voltage level of control signals (e.g., transition) very frequently over a short period of time, a circuit section generating the control signal consumes a large amount of power.

Also, as subpixel density is increased, a period during which control signals controlling the multiplexer maintain the gate ON voltage is so short that a data charge rate is shortened.

BRIEF SUMMARY

According to an aspect of the present disclosure, a display device may include a display panel, a data driver, a multiplexer, and a multiplexer controller. N number of color subpixels may be disposed on the display panel (N is an integer of 2 or greater). The data driver may output data voltages to be supplied to the N number of color subpixels, through output buffers. The multiplexer may distribute each of the data voltages output by the output buffers to N number of data lines in a time division manner in response to first to N control signals. The multiplexer controller may sequentially output a first control signal to an N number control signal during a first horizontal period, and sequentially output the N number control signal to the first control signal during a second horizontal period. One of I number of control signals maintaining a gate ON voltage at a time when a first horizontal period expires may maintain the gate ON voltage for a predetermined period of time after a second horizontal period starts (I is an integer equal to or less than N).

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Like reference numerals refer to like elements throughout. In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, one skilled in the art will understand that the disclosure may be practiced without these specific details. In other instances, well known structures associated with electronic components and fabrication techniques have not been described in detail to avoid unnecessarily obscuring the descriptions of the embodiments of the present disclosure.

As used in the specification and the appended claims, the use of “correspond,” “corresponds,” and “corresponding” is intended to describe a ratio of or a similarity between referenced objects. The use of “correspond” or one of its forms should not be construed to mean the exact shape or size.

The present disclosure is directed to a display device with a set control signal timing. The display device includes color subpixels that are driven according to a set of control signals from a multiplexer. The multiplexer can provide various patterns of control signals, and in one embodiment provides gate control signals in a first sequence and then in a second sequence opposite the first sequence. This may result in reduced switching time and power as no gate signal switching is done at the beginning and end of the sequence.

In a gate driver of the present disclosure, switches may be implemented as transistors having a structure of n-type or p-type metal oxide semiconductor field effect transistors (MOSFETs). In the embodiments described hereinafter, an n-type transistor will be described, but the present disclosure is not limited thereto. For example, other types of transistors (e.g., P-type MOSFETs, BJTs, and TFETs) or any other switches may also be used. In the present disclosure, outputting control signals refers to a state in which the corresponding control signals are in a gate ON voltage state. That is, gate ON voltage of the switches as n type transistors correspond to a high potential voltage and outputting or applying control signals refers to a state in which corresponding control signals are in a high potential voltage state.

FIG. 1is a view illustrating a display device according to an embodiment of the present disclosure, andFIG. 2is a view illustrating an example of a subpixel illustrated inFIG. 1.

Referring toFIGS. 1 and 2, the display device of the present disclosure includes a display panel100, a timing controller200, a gate driver300, a data driver400, a multiplexer500, and a multiplexer controller600.

The display panel100, including a subpixel array in which subpixels are disposed in a matrix form, displays input image data. As illustrated inFIG. 2, the subpixel array includes a thin film transistor (TFT) array formed on a lower substrate, a color filter array formed on an upper substrate, and liquid crystal cells Clc. The TFT array includes a data line DL and a gate line GL crossing the data line DL, a TFT formed at a crossing between the data line DL and the gate line GL, a subpixel electrode1connected to the TFT, a storage capacitor Cst, and the like. The color filter array includes a black matrix and a color filter. A common electrode2may be formed on the lower substrate or upper substrate. Liquid crystal cells Clc are driven by an electric field between the subpixel electrode1to which a data voltage is supplied and the common electrode2to which a common voltage Vcom is supplied.

The timing controller200may receive digital video data RGB from an external host and receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a main clock CLK, and the like. The timing controller200transmits the digital video signal RGB to the data driver400. The timing controller200generates a source timing control signal for controlling an operation timing of the data driver400using the timing signals Vsync, Hsync, DE, and CLK and gate timing control signals ST, GCLK, and MCLK for controlling an operation timing of a level shifter and a shift register of the gate driver300.

The gate driver300outputs a gate pulse Gout using a gate timing control signal. The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE). The gate start pulse (GSP) indicates a starting line for the gate driver300to output a first gate pulse Gout. The gate shift clock (GSC) is a clock for shifting the gate start pulse (GSP). The gate output enable (GOE) sets an output period of the gate pulse Gout. The gate driver300may be implemented in the form of a gate-in-panel (GIP) including a combination of TFTs on the display panel100.

The data driver400converts image data provided from the timing controller200into a data voltage.

FIG. 3is a view illustrating a configuration of a data driver. Referring toFIG. 3, the data driver400includes a register unit410, a first latch420, a second latch430, a digital-to-analog converter (DAC)440, and an output unit450. The register unit410samples RGB digital video data bits of the input image using data control signals SSC and SSP provided from the timing controller200, and provides the sampled digital video data bits to the first latch420. The first latch420samples and latches the digital video data bits according to clocks sequentially provided from the register unit410, and simultaneously outputs the latched data. The second latch430latches data provided from the first latch420and simultaneously outputs latched data in response to a source output enable signal SOE. The DAC440converts video data input from the second latch unit430into a gamma compensation voltage GMA to generate an analog video data voltage. The output unit450provides an analog type data voltage ADATA output from the DAC440to the data lines DL during a low logical period of the source output enable signal SOE. The output unit450may be implemented as an output buffer outputting a data voltage using a low potential voltage GND and a voltage received through a high potential input terminal, as driving voltages.

The multiplexer500distributes data voltages output from output buffers to the plurality of data lines DL in a time division manner. InFIG. 1, an embodiment is depicted in which 3m number of data lines DL are connected to each output buffer. However, the number of data lines connected to the output buffers is not limited thereto. In some embodiments, the multiplexer is any switching device capable of selecting coupling an input to one or more of a plurality of outputs. In one embodiment the switching device is a switch having an input contact, an output contact, and a gate or state controller.

FIG. 4is a view illustrating a structure of multiplexers and subpixel arrays according to a first embodiment of the present disclosure, andFIG. 5is a view illustrating a timing of control signals and a gate pulse according to the first embodiment of the present disclosure.

Referring toFIGS. 4 and 5, the display panel100includes red subpixels R, green subpixels G, and blue subpixels B disposed in parallel in each pixel line HL. The subpixels disposed in each pixel line receive a gate pulse GS1through the gate line GL. For example, subpixels P disposed in a first pixel line HL1receive a first gate pulse GS1through a first gate lines GL1. Also, subpixels P disposed in a second pixel line HL2receive a second gate pulse GS2through a second gate line GL2, and subpixels P disposed in a third pixel line HL3receive a third gate pulse GS3through a third gate line GL3.

In some embodiments, the different color subpixels R, G, and B are disposed in a repeating pattern. For example, in the last sequence, the red subpixels R are disposed in a (3m−2)th column line (CL[3m−2]), the green pixels G are disposed in a (3m−1)th column line (CL [3m−1]), and the blue subpixels B are disposed in a 3mth column line (CL3m). In this example, red subpixels R are disposed in a first column line CL1and a fourth column line CL4. Green pixels G are disposed in a second column line CL2and a fifth column line CL5. Also, blue subpixels B are disposed in a third column line CL3and a sixth column line CL6.

The data driver400outputs a data voltage to three subpixels positioned in one pixel line HL during every horizontal period H. For example, a first output buffer BUF1of the data driver400sequentially outputs a data voltage applied to R11, G12, and G13during a first scan period t1 of the first horizontal period 1stH. In this embodiment, R (or B or B)xy represents a color and a position of a subpixel. That is, Rab refers to a red subpixel positioned in a horizontal line a and a column line b. Thus, R11refers to a red subpixel positioned in a first column line CL1in the first pixel line HL1. Also, inFIG. 5, Data1illustrates subpixels to which a data voltage output by the first output buffer BUF1is applied. Also, the first horizontal period 1H may be defined as a period during which a data voltage is supplied to the subpixels P disposed in one pixel line HL. The data driver400supplies the data voltage to three subpixels during the first horizontal period 1H in a time division manner. Each of the first to third scan periods t1 to t3 of each horizontal period is defined as a period during which a data voltage applied to one subpixel P is output.

The multiplexer500distributes data voltages, which are output by the output buffers BUF, to a plurality of data lines. The multiplexer500according to the first embodiment distributes a data voltage output by the first output buffer BUF1to first to third data lines DL1to DL3in a time division manner. To this end, the multiplexer500includes first to third switches M1, M2, and M3. The first switch M1is turned on in response to a first control signal Mux1to connect the first output buffer BUF1and the first data line DL1. The second switch M2is turned on in response to a second control signal Mux2to connect the first output buffer and the second data line DL2, and the third switch M3is turned on in response to a third control signal Mux3to connect the first output buffer BUF1and the third data line DL3.

The multiplexer (switch) controller600outputs the first to third control signals in a time division manner during one horizontal period H. The multiplexer controller600may sequentially output the first, second, and third control signals Mux1, Mux2, and Mux3or sequentially output the third, second, and first control signals Mux3, Mux2, and Mux1, during one horizontal period. For example, the multiplexer controller600sequentially outputs the first to third control signals Mux1to Mux3during the first horizontal period 1stH and sequentially outputs the third to first control signals Mux3to Mux1during a second horizontal period 2ndH.

The first to third control signals Mux1to Mux3are sequentially output during each horizontal period H in which the gate pulse GS maintains a gate ON voltage. For example, during the first horizontal period 1H, the first gate pulse GS1maintains the gate ON voltage and the first to third control signals Mux1to Mux3are sequentially output.

As a result, the subpixel R11is charged during the first scan period t1 of the first horizontal period 1stH, the subpixel G12is charged during the second scan period t2 of the first horizontal period 1stH, and the subpixel B13is charged during the third scan period t3 of the first horizontal period 1stH.

Also, the subpixel B23is charged during a first scan period t1 of a second horizontal period 2ndH, the subpixel G22is charged during a second scan period t2 of the second horizontal period 2ndH, and the subpixel R21is charged during a third scan period t3 of the second horizontal period 2ndH.

In this manner, in the first embodiment, the third control signal Mux3is output during the final period of the first horizontal period 1stH and the first period of the second horizontal period 2ndH. That is, the number of times the third control signal Mux3is reversed to a gate ON voltage and the number of times the third control signal Mux3is reversed to a gate OFF voltage from the first horizontal period 1stH to the second horizontal period 2ndH are one time, respectively. Similarly, the number of times the first control signal Mux1is reversed to a gate ON voltage and the number of times the first control signal Mux1is reversed to a gate OFF voltage from the second horizontal period 2ndH to the third horizontal period 3rdH are one time, respectively.

As a result, overall transition number of the control signals Mux1to Mux3output by the multiplexer controller600is reduced, and thus, power consumption of the multiplexer controller600is reduced.

FIG. 6is a view illustrating a timing of control signals according to a second embodiment of the present disclosure. InFIG. 6, a timing diagram for driving the multiplexers and the pixel array illustrated inFIG. 4is illustrated. Detailed descriptions of the same components of the embodiment illustrated inFIG. 6as those illustrated inFIG. 5will be omitted.

Referring toFIG. 6, the second control signal Mux2is output before the second scan period t2 starts, and the third control signal Mux3is output before the third scan period t3 starts. For example, the second control signal Mux2is output when the first scan period t1 starts, and the third control signal Mux3is output when the second scan period t2 starts. As a result, the control signals Mux1to Mux3output to be adjacent to each other overlap in at least portions thereof. For example, the first control signal Mux1and the second control signal Mux2partially overlap, and the second control signal Mux2and the third control signal Mux3partially overlap.

In this manner, since the control signals Mux1to Mux3according to the second embodiment extend in an output period maintained by the gate ON voltage, a sufficient charge period of the data voltage may be secured.

In the first embodiment, a period for charging data may be shortened due to delay of the control signals Mux1to Mux3. For example, as illustrated inFIG. 7, when the second control signal Mux2output during the second scan period t2 of the first horizontal period 1stH is delayed by an RC delay, a period during which data can be charged is “tc2”.

In contrast, since the second control signal Mux2according to the second embodiment is output before the second scan period t2, although it is delayed by the RC delay, the second control signal Mux2may have the gate ON voltage at a time when the second scan period t2 starts. As a result, the second control signal Mux2according to the second embodiment may charge the data voltage during the second scan period t2. In this manner, the control signals Mux1to Mux3according to the second embedment may sufficiently secure a turn-on period of the switches M1to M6to prevent a reduction in a charge time of the data voltage.

FIG. 8is a view illustrating a structure of pixel arrays and multiplexers according to the second embodiment of the present disclosure, andFIG. 9is a timing diagram of control signals and gate pulses according to a third embodiment of the present disclosure. Detailed descriptions of the same components of the embodiment illustrated inFIG. 8as those of the embodiment described above will be omitted.

Referring toFIGS. 8 and 9, subpixels include a white subpixel W, a red subpixel R, a green subpixel G, and a blue subpixel B.

In odd-numbered pixel lines HL1and HL3, W, R, G, and B subpixels are sequentially disposed, and in even-numbered pixel lines HL2and HL4, G, B, W, and R subpixels are sequentially disposed. Thus, the W, R, G, and B subpixels disposed in parallel in each pixel line may form a unit pixel. Alternately, W, R, G, and B subpixels disposed in 2×2 unit may form a unit pixel. In image rendering of the display panel, one unit pixel may be used as a reference or two adjacent subpixels may be used as a reference.

The multiplexer500distributes data voltages, which are output by the output buffers BUFs, to a plurality of data lines. The multiplexer500distributes a positive (+) polarity data voltage, which is output by the first output buffer BUF1, to a first data line DL1, a third data line DL3, a sixth data line DL6, and an eight data line DL8in a time division manner. Also, the multiplexer500distributes a negative (−) polarity data voltage, which is output by the second output buffer BUF2, to a second data line DL2, a fourth data line DL4, a fifth data line DL5, and a seventh data line DL7in a time division manner. To this end, the multiplexer500includes first to eighth switches M1to M8.

The first switch M1is turned on in response to the first control signal Mux1to connect the first output buffer BUF1to the first data line DL1. The third switch M3is turned on in response to the third control signal Mux3to connect the first output buffer BUF1to the third data line DL3. The sixth switch M6is turned on in response to the second control signal Mux2to connect the first output buffer BUF1to the sixth data line DL6. The eighth switch M8is turned on in response to the fourth control signal Mux4to connect the first output buffer BUF1to the eighth data line DL8.

The second switch M2is turned on in response to the second control signal Mux2to connect the second output buffer BUF2to the second data line DL2. The fourth switch M4is turned on in response to the fourth control signal Mux4to connect the second output buffer BUF2to the fourth data line DL4. The fifth switch M5is turned on in response to the first control signal Mux1to connect the second output buffer BUF2to the fifth data line DL5. The seventh switch M7is turned on in response to the third control signal Mux3to connect the second output buffer BUF2to the seventh data line DL7.

The multiplexer controller600outputs the first to fourth control signals Mux1to Mux4in a time division manner during one horizontal period 1H. The multiplexer controller600may sequentially output the first control signal Mux1to the fourth control signal Mux4or sequentially output the fourth control signal Mux4to the first control signal Mux1during one horizontal period. For example, the multiplexer controller600may sequentially output the first control signal Mux1to the fourth control signal Mux4during a first horizontal period 1stH and sequentially output the fourth control signal Mux4to the first control signal Mux1during a second horizontal period 2ndH.

Within one horizontal period 1H, the first control signal Mux1to the fourth control signal Mux4are output during one scan period 1t. Within each horizontal period H, each of first to fourth scan periods t1 to t4 is defined as a period during which a data voltage applied to one subpixel P is output.

The data driver400outputs data voltages having the opposite polarities through mutually adjacent output buffers. For example, the data driver400may output a positive (+) polarity data voltage to the output buffer BUF1and output a negative (−) polarity data voltage to the second output buffer BUF2.

The data driver400outputs a data voltage to one pixel line HL during each horizontal period H. InFIG. 9, Data1represents subpixels to which a data voltage output by the first output buffer BUF1is applied, and Data2represents subpixels to which a data voltage output by the second output buffer BUF2is applied. That is, the first output buffer BUF1of the data driver400sequentially outputs a data voltage supplied to subpixels positioned in a first column line CL1, a sixth column line CL6, a third column line CL3, and an eighth column line CL8during each horizontal period H. The second output buffer BUF2sequentially outputs a data voltage supplied to subpixels positioned in a fifth column line CL5, a second column line CL2, a seventh column line CL7, and a fourth column line CL4during each horizontal period H.

As a result, a subpixel W11and a subpixel W15are charged during a first scan period t1 of the first horizontal period 1stH. A subpixel R16and a subpixel R12are charted during a second scan period t2 of the first horizontal period 1stH. A subpixel G13and a subpixel G17are charged during a third scan period t3 of the first horizontal period 1stH. A subpixel B18and a subpixel B14are charged during a fourth scan period t4 of the first horizontal period 1stH.

Also, before a data voltage is applied to the data line DL, the control signals Mux are output as a gate ON voltage. For example, during the second scan period t2, the data driver400outputs a data voltage applied to the subpixel R16and the subpixel R12. The subpixel R16receives the data voltage through the sixth data line DL6, and the sixth data line DL6is connected to the first output buffer BUF1through the sixth switch M6. The second control signal Mux2controlling the sixth switch M6is output as a gate ON voltage before the second scan period t2. Thus, although the second control signal Mux2is delayed, the sixth switch M6may be turned on at a timing when the second scan period t2 starts. As a result, a data charge period may be prevented from being shortened.