Digital slew rate limiter

A circuit may include a detector, an approximator, a look-up table, a scaler, and an integrator. The detector may generate a first difference signal and a second different signal based on an input and an output. The approximator may generate, using a one's complement operation, an index based on approximated modulus values of the first difference signal and the second difference signal. The look-up table may select one of a plurality of scaling factors based upon the index. The scaler may adjust the first difference signal and the second difference signal based on the selected scaling factor. The integrator may generate the output based on the adjusted first difference signal and the adjusted second difference signal.

BACKGROUND

In circuits such as op-amps, it may be desirable to limit the rate of change (or slew rate) in a signal to reduce or prevent distortions in the signal. To do so, the circuit may detect when a signal may be changing (increasing or decreasing) too quickly, and adjust the signal (for example, by reducing the amplitude) to limit the slew rate of the signal.

At lower clock speeds, slew rate may be easily limited, because the low clock speed signal may be detected and adjusted by a slew rate limiting circuit running at relatively higher clock speed. However, as the clock speed of the signals sought to be slew rate limited increases in new technologies, such as in high speed wireless transmitters and receivers, it may become increasingly difficult to implement higher clock speeds for slew rate limiting circuits. Complex slew rate limiting circuits may lose signal integrity and fidelity at high clock speeds.

Thus, there is a need for improved slew rate limiting circuit capable of good performance for a high speed signal with minimal loss of signal integrity.

DETAILED DESCRIPTION

According to an embodiment, as illustrated inFIG. 1, a circuit100may include a detector110, an approximator120, a look-up table130, a scaler140, and an integrator150. The detector110may generate a first difference signal and a second different signal based on an input190and an output195. The approximator120may generate, using a one's complement operation, an index based on approximated modulus values of the first difference signal and the second difference signal. The look-up table130may select one of a plurality of scaling factors based upon the index. The scaler140may adjust the first difference signal and the second difference signal based on the selected scaling factor. The integrator150may generate the output based on the adjusted first difference signal and the adjusted second difference signal.

The detector110may generate a first difference signal and a second different signal based on an input190and an output195. The output195may represent the slew rate adjusted or limited signal of the input190. The input190and the output195each may include I and Q signal components. The first difference signal may represent the difference signal of the I signal component. The second difference signal may represent the difference signal of the Q signal component. The detector110may include a summation circuit for each of I and Q signal components. The detector110may include a digital summation circuit which generates the difference signals by subtracting the components of the output195from the corresponding components of the input190.

The approximator120may generate, using a one's complement operation, an index based on approximated modulus values of the first difference signal and the second difference signal. The approximator120may receive the first difference signal and the second difference signal from the detector110. The approximator120may truncate the first difference signal and the second difference signal, by for example, taking only the upper or most significant bits (MSB's) out of all of the bits (for example, the upper 6 bits of 16 bit long value) of each of the first difference signal and the second difference signal. The approximator120may perform a one's complement operation on each of the truncated versions of the first difference signal and the second difference signal. The one's complement operation may invert all the individual bit values of the truncated versions of the first difference signal and the second difference signal. In doing so, the approximator120approximates the absolute or modulus values of each of the first difference signal and the second difference signal very rapidly. The one's complement operation may be implemented simply using multiple logic inverters, and this operation may be done very quickly (less than 1 clock cycle of the circuit100to resolve the result), without the need to use additional buffers to calculate carry-over bits. The approximator120may take the approximate modulus values of the first difference signal and the second difference signal, and form an index. The index may be a digital value that include bits from both the approximate modulus values of the first difference signal and the second difference signal, for example, 6 bits from each of the approximate modulus values of the first difference signal and the second difference signal to form a 12 bit index.

The look-up table130may select one of a plurality of scaling factors based upon the index. The look-up table130may receive the index from the approximator120, and look up and select a corresponding scaling factor among a plurality of scaling factors stored inside the look-up table130. The plurality of scaling factors may be pre-programmed into the look-up table130. The look-up table130may include or may be implemented in one of a read only memory (ROM), a random access memory (RAM), a block random access memory (BRAM), a erasable programmable read only memory (EPROM), a electrically erasable programmable read only memory (EEPROM), a Flash Memory, and a programmably logic array (PLA).

The scaler140may adjust the first difference signal and the second difference signal based on the selected scaling factor. The scaler140may receive the selected scaling factor from the look-up table130. The scaler140may optionally adjust the first difference signal and the second difference signal based on an offset142. The offset142may be a value stored in a memory, a buffer, or a register. For fast operation, the offset142may be preferably stored in a register in circuit100. The scaler140may multiply, using a multiplier146, the first difference signal and the second difference signal with the selected scaling factor. The scaler140may multiply, using a multiplier146, the first difference signal and the second difference signal based on an offset142added to the selected scaling factor via an adder144. Multiplier146may use rounding to approximate the result of multiplication quickly, for example, by rounding the input operands of multiplier146, and/or using modified Booth's algorithm, etc. In doing so, the circuit100may perform slew rate limiting rapidly.

The integrator150may generate the output based on the adjusted first difference signal and the adjusted second difference signal. The integrator150may receive the adjusted first difference signal and the adjusted second difference signal from the scaler140, and add the previous values of the components of the output195to the corresponding adjusted first difference signal and the adjusted second difference signal. For example, the integrator150may hold the previous values of the I and Q components of the output195in buffers152. In a current clock period, the integrator150calculates the values of the output195for the current clock period by adding, using summer154the previous values of the I and Q components of the output195to corresponding adjusted first difference signal and the adjusted second difference signal. In doing so, the integrator150generates the output195, which may be slew rate limited or adjusted. The circuit100may generate the output corresponding to the first difference signal and the second difference signal in less than one clock period of the circuit after the detector generating the first difference signal and the second difference signal.

FIG. 2illustrates an embodiment of a circuit200with pipelining.

As illustrated inFIG. 2, according to an embodiment, a circuit200may include a detector210, an approximator220, a look-up table230, a scaler240, and an integrator250, similar to the circuit100inFIG. 1. The detector210may generate a first difference signal and a second different signal based on an input290and an output295. The approximator220may generate, using a one's complement operation, an index based on approximated modulus values of the first difference signal and the second difference signal. The look-up table230may select one of a plurality of scaling factors based upon the index. The scaler240may adjust the first difference signal and the second difference signal based on the selected scaling factor. The integrator250may generate the output based on the adjusted first difference signal and the adjusted second difference signal.

Similar to the circuit100inFIG. 1, the circuit200may include offset242, adder244, multiplier246, and summer254.

According to an embodiment, the circuit200may further include multiple buffers212,248,260, as well as the buffer252, to form a pipelining architecture to pipeline the processing and slew rate limiting of signals. Specifically for example, buffers may be included in detector210, scaler240, and integrator250, as well as between detector210and scaler240, such that various signals at different branches of the circuit200may be synchronized to ensure correctness of data and minimize delays.

For example, multiplier246may generate the adjusted first difference signal and the adjusted second difference signal for a previous clock period, and buffer252may output the corresponding output295for a previous clock period. Both of these sets of signals may be fed back to detector210to represent the unresolved output295for the current clock period. The detector210may receive these signals and subtract them from the buffered signal of input290for the current clock period. This effectively eliminates the need to wait for the multiplier246and integrator250to resolve calculation of output295for the current clock period. That is, while the integrator250is resolving its calculation of the output295for the current clock period, the input290for the current clock period may be simultaneously staged through the detector210, the approximator220, the look-up table230, and part of scaler240, to have data ready for next clock period for multiplier246and integrator250.

Additionally, detector210may include a negative rounding constant214to be added to each of the components of input290. Integrator250may include a positive rounding constant258to be added to each of the components at summer254. The detector210and the integrator250may add the respective rounding constants214and258to respective signal values, and may round the results to reduce number of bits for simplicity of calculation, further speeding up the circuit200.

As illustrated inFIG. 3, a method300may include block310, generating, by a detector, a first difference signal and a second different signal based on an input and an output.

At block320, generating, by an approximator using a one's complement operation, an index based on approximated modulus values of the first difference signal and the second difference signal.

At block330, selecting, by a look-up table, one of a plurality of scaling factors based upon the index.

At block340, adjusting, by a scaler, the first difference signal and the second difference signal based on the selected scaling factor.

At block350, generating, by an integrator, the output based on the adjusted first difference signal and the adjusted second difference signal.

It is appreciated that the disclosure is not limited to the described embodiments, and that any number of scenarios and embodiments in which conflicting appointments exist may be resolved.