ACCELERATED EMULATION DEVICE BACKEND SOFTWARE UPDATE WITH SHORT DOWNTIME

Systems and methods are presented that reduce the downtime of communication when updating backend software of an accelerated emulation system. In at least one embodiment, by first transferring the context of the running software to the updated software and rebuilding the context map for the communication and programming the context in the accelerated emulated device, downtime can be reduced by only enabling the new software and disabling the original software after the context map has been rebuilt as the last stage of execution.

TECHNICAL FIELD

At least one embodiment pertains to processing networking packets and Input/Output (I/O) operations used to perform and facilitate cloud computing and accelerating virtualization applications.

BACKGROUND

Updating or replacing emulation device backend software can require significant downtime. The amount of memory, time, or computing resources used to update or replace emulation device backend software can be improved.

DETAILED DESCRIPTION

FIG.1illustrates an example software based emulation system100in which aspects of various embodiments can be implemented. In this example, when operating a virtualization system a hypervisor110, such as a Quick Emulator (QEMU), and a virtual machine (VM)112may be used. Virtual machine includes one or more virtual devices114,116, also known as VirtIO virtual function (VF) block (blk) devices and VirtIO VF network (net) devices. VirtIO is an abstraction layer over devices in a para-virtualized hypervisor, and an I/O virtualization framework. VirtIO is treated as an industry specification that supports vendor agnostic devices. VirtIO is a standard specification in virtualization and can generally be used with any suitable hardware. A core feature of VirtIO is Virtqueue (VQ) abstraction. A VQ is a queue where Scatter-Gather (SG) lists, a list of physical addresses and length couples, are posted by guest driver to be used by hypervisor. Posted SGs are used to send data to hypervisor, while input SGs are used to receive data from hypervisor. A device of virtual machine can use one or more queues, such as VQs. A VirtIO blk device is a simple virtual block device. A VirtIO net device is a simple virtual networking device. Frontend (FE) VirtIO driver in user space120VM places read, write, and other requests onto VQ, so that backend (BE) VirtIO driver (in service VM space) can process them accordingly. Communication between FE and BE is based on VirtIO kick and notify mechanism. VirtIO VF blk and VirtIO VF net devices are located inside virtual machines and are emulated by virtual machine software. Virtual machine software can also be known as a representor object or a controller. Generally, two options are used for emulation of VirtIO VF blk and VirtIO VF net devices by virtual machine software.

Emulation device backend software can be updated or replaced as required. In order to exchange backend software, software processes generally must be stopped to allow information to be transferred and rebuilt from current software to new software. New software processes can then be started to resume processes. This process requires downtime of the processes, which can cause unwanted lag and higher application downtime to complete the software replacement.

A modern computer operating system may segregate virtual memory into user space and kernel space130. This separation provides memory protection and hardware protection from malicious or errant software behavior. User space is memory area where application software and some drivers execute. Kernel space is reserved for running privileged operating system kernel, kernel extensions, and most device drivers. A hypervisor, such as a QEMU is a computer process which separates a computer operating system from host physical hardware. There are generally, two types of hypervisors. A first type is a hosted hypervisor, which means that it runs on a conventional operating system just like other computer programs. A second type is a native or bare metal hypervisor that is running directly on a host hardware. Virtual machine software runs in vhost user space backend. Virtual machine software emulates VirtIO VF blk and VirtIO VF net devices and communicates with QEMU, which is a hypervisor of second type. A QEMU is a generic machine and user space emulator and virtualizer. A QEMU is capable of emulating a complete machine in software without any need for hardware virtualization support. When QEMU hypervisor makes a query of what devices are connected, how many queues are present, queue configuration, etc., all of information is supplied from user space.

As shown inFIG.1, a primary option utilizes an emulation process within user space, using a vhost user space backend140. Vhost user space backend connects to a real storage or a real physical network170, which can be any suitable storage or network. Vhost user space backend is able to connect, send packets, and perform storage I/O. However, this emulation option requires a high number of hops, or steps in travel of a signal, for transferring information. This high number of hops leads to increased processing time. For example, vhost user space backend may be required to communicate with kernel160to send packets to physical network. With these two or three hops, there will be higher latency, higher packets, and further time losses.

A secondary option, which is used to reduce number of hops compared to primary option, connects QEMU hypervisor directly to kernel and bypasses connecting to vhost user space backend in user space of primary option. Connecting QEMU hypervisor to vhost kernel net150in kernel space allows signals to move faster from kernel to real storage or real physical network. Accordingly, kernel is able to communicate directly to real storage or real physical network I/O. While secondary option continues is commonly used for this benefit, both options are relatively slow because in either option QEMU hypervisor central processing unit (CPU) must be used to perform work of performing I/O or sending packets to real storage or real physical network. In order to reduce inefficiency inherent in both primary and secondary options, a data processing unit (DPU) or SmartNIC may incorporated to amount of work performed by QEMU hypervisor CPU. A SmartNIC is a type of network interface controller (NIC) card and programmable accelerator that makes data center networking, security, and storage efficient and flexible. SmartNICs offload a growing array of tasks from server CPUs needed to manage modern distributed applications.

FIG.2illustrates an example DPU based accelerated emulation system200in which aspects of various embodiments can be implemented. In this example, a bare metal server210operates to perform emulation with one or more interface devices provided to bare metal server. Interface devices are not able to be incorporated into environment200because environment200is configured for virtualization and is unable to interface with a physical device to receive virtual functions (VF) or physical functions (PF). Configurations using a bare metal server require connecting a physical device, such as a PCI device, to server. A physical device connects directly to bare metal server using DPU or SmartNIC260. In some embodiments, a bare metal server is connected to DPU or SmartNIC which provides a networking device (VirtIO net) and a block device (VirtIO blk) that QEMU hypervisor212and bare metal server can use.

A user space backend does not exist in this configuration, and therefore function of VHOST user space backend is included in a processing subsystem of DPU or SmartNIC. DPU or SmartNIC exists in an additional embedded system250, which can be separate from kernel space230and user space220, with only host kernel and/or hypervisor kernel240existing in kernel space. In order to create VirtIO devices in DPU or SmartNIC, a VirtIO emulation software process262runs in DPU or SmartNIC. VirtIO emulation software supplies PF and VF to PCI device for bare metal server, or VirtIO emulation software supplies PF and VF for a QEMU hypervisor stack system such as example ofFIG.1, to QEMU hypervisor. In certain embodiments, QEMU hypervisor may be running inside bare metal server, where QEMU hypervisor receives from PCI device PF and VF created by VirtIO emulation software. DPU or SmartNIC, and associated VirtIO emulation software, may not be informed of whether QEMU hypervisor in bare metal server is running, or only bare metal server is running without QEMU hypervisor running. As a software process, VirtIO emulation software may implement any number of functions and related systems included in primary option or secondary option depicted inFIG.1.

Several advantages may be gained using either environment100or environment200with VirtIO emulation software process operating as part of DPU or SmartNIC. When emulation is ran as a software process, software can be upgraded while traffic is running. In at least one embodiment, an in-service software upgrade can be performed to correct bugs that are present in current software. In other embodiments, new features or a new security patch may need to be corrected in current software. Performing in-service upgrades of emulation software was not possible in primary option or secondary option using previous methods, because software was running as a kernel and therefore entire kernel must be updated. In these examples, all virtual machines (VMs) may be required to be stopped. In most examples, there are hundreds of VMs running that are all supplied by a single kernel. In order to perform a bug fix, all VMs must be migrated to another server or be powered down, which will take an extended period of time. This requirement to stop VMs and extended time for process are primary limitations of secondary option. Primary option also includes these limitations, but is generally already considered obsolete in light of secondary option. Regarding primary option, traditionally entire user space process must be restarted to perform a software upgrade and an in-service upgrade of software is not possible. However, as described further herein a process for updating software while traffic is running of primary option is possible.

FIG.3illustrates an example process300for transferring control to an alternate emulation software process that can be utilized in accordance with various embodiments. It should be understood for this and other processes discussed herein that there can be additional, alternative, or fewer steps performed in similar or alternative orders, or in parallel, within the scope of the various embodiments unless otherwise stated. In this example, emulation software process may be hosted on a processing unit of a virtual environment embedded system302. In order to upgrade or replace emulation software process, an alternate version of emulation software process may be deployed into processing unit304. Emulation software process can be upgraded by starting new software process after taking over from current software process. Context information is migrated from current software to new software306and operations are shut down that are running to facilitate one or more VirtIO PCI device. VirtIO PCI device transports packets through a number of VQs, which are present in current software. In order to complete an update, all VQs of current software are shut down and each VQ state in one round are saved. Context information and VQ in saved states are sent to new software process. Context information sent to new software may include queue data and device context for any number of devices. Based on migrated context information, one or more context maps are built in alternate emulation software process308. Length of time for this process to complete can often take from about 500 milliseconds up to a few seconds, depending on number of VQs that are transferred to new software. For example, if one queue takes 100 milliseconds, then 32 queues can take 3.2 seconds to migrate. These lengths of time are generally acceptable for most applications and upgrade process is used in many instances. Traditionally, control of communication from emulation software process to alternate emulation software process will be transferred, and then information migration and context map building would be completed. However, according to an improved embodiment as disclosed herein, control of communication from emulation software process to alternate emulation software process may be transferred after information has been migrated and context maps have been built510, greatly reducing down time.

FIG.4Aillustrates an example process400for using context maps to enable an alternate emulation software process to control device communications that can be utilized in accordance with various embodiments. It should be understood for this and other processes discussed herein that there can be additional, alternative, or fewer steps performed in similar or alternative orders, or in parallel, within the scope of the various embodiments unless otherwise stated. In this example, an alternative embodiment is contemplated in order to perform in-service upgrades and/or replacement of emulation software. In certain embodiments, support library software may need to be upgraded, but any suitable software may be upgraded as needed. Traditional process as disclosed above requires stopping all VQs in current software, migrating all stopped VQs to new software, and then starting new software with migrated VQs. An improved process may first query context information and VQ information from running hardware accelerator backend device402. Improved process may next query context information and VQ information from current software404. Then process may migrate queried context information and VQ information to new software406. Next, improved process may build context maps based on migrated context information408. Improved process may then program context map in accelerated hardware backend device410. Finally, improved process may re-create all context information and VQ information in new software while current software is still running412.

FIG.4Billustrates an example process450for continuing using context maps to enable an alternate emulation software process to control device communications that can be utilized in accordance with various embodiments. It should be understood from this and other processes discussed herein that there can be additional, alternative, or fewer steps performed in similar or alternative orders, or in parallel, within the scope of the various embodiments unless otherwise stated. In this example, after improved process may program context map in accelerated hardware backend device, improved process may first suspend hardware acceleration backend device452. Second, improved process may query the transient device context map from the hardware acceleration backend device454. Then, improved process may transfer transient device context map to alternate emulation software process456. Next, improved process may transfer control of communications by a device to the alternate emulation software process458. Improved process may then program transient device context map in the hardware acceleration backend device460. Finally, improved process may resume alternate acceleration data path.

FIG.4Cillustrates another example process480for continuing using context maps to enable an alternate emulation software process to control device communications that can be utilized in accordance with various embodiments. It should be understood from this and other processes discussed herein that there can be additional, alternative, or fewer steps performed in similar or alternative orders, or in parallel, within the scope of the various embodiments unless otherwise stated. In this example, the process may migrate queried transient device context map to an alternate emulation software process482. After migration is complete, transient context of migrated transient device context becomes the primary context484. This may happen automatically as part of the migration or may require processing to complete. Finally, process may determine that primary context is present after migration, and may determine that transient device context is absent after migration486.

Current software in control of device provides enough detail to new software to allow new software to build context for software execution and take control of device. In some embodiments, new software prepares some or all contexts before execution in an inactive, or INIT (FREEZE), state. Context information that is transferred may include backend connections, I/O context such as blk, device VQ contexts, or any other relevant information. This alternative process therefore allows for dual representors to exist for an emulated device. In an embodiment, current software and new software may control communication of an emulation object. Emulation object holds all emulation type information and controls emulation-specific settings. Emulation object may communicate with any device that is suitable, including but not limited to block devices such as VirtIO or NVMe, VirtIO network devices or any other network device, VirtIO crypto device or any other crypto device, GPU devices, and PCI emulated devices. Nonvolatile memory express (NVMe) is a storage access and transport protocol for flash and solid-state drives (SSDs) that delivers high throughput and fast response times. QEMU may provide NVMe emulation.

FIG.5illustrates an example control transfer500in which aspects of various embodiments can be implemented. In this example two control managers, or two control objects, can control a single device in order to prepare to update software. Typically, in order to control an object, such as PCI device510, only one control manager controls a device as a master. As shown, PCI device may be controlled by two device managers, current software520and new software530. In some embodiments, current software in control of device is able to decode what software should control device and when to change control. Current software reads all values of current queues and related properties. Current software shares this information that has been read or is being read to new software while current software is still running. New software sets up required information and process to take over control of device, before new software has control of device. Eventually current software completes a transfer of a number of configurations to be performed to control device to new software, but current software will not enable configurations. Enablement of some or all configurations will occur by new software after current software transfer control. When new software is fully prepared to take control of a device, new software can indicate to current software to suspend VQs. Once VQs have been suspended, new software takes control of emulated device and restarts VQs.

This process is applicable to both VirtIO net devices and VirtIO blk devices. Additionally, common code, such as software, firmware, firmware verification, and any other suitable code, can be reused. Common code can also be reused for device emulation object management and MSI-X mapping. Process to perform in-service upgrades of emulation software is also meant to be as stateless as possible in both software and firmware. In addition to aiding upgrade of software, use of a DPU or SmartNIC as discussed can also be used to replace, downgrade, and correct bugs in software, or used in any other suitable implementation. In any implementation, new software may decide algorithms and resources to utilize, such as when controlling devices and creating objects. Created objects can include context and context maps which hold information and state of emulated device and queues. Context maps are used by data path acceleration engines and are built using efficient cores. Context maps support accelerations engines for emulation context information. Context maps may be built in alternate emulation software process based on migrated context information.

Enablement of configurations by new software can begin immediately after object creation in new software. Object creation is generally a slow procedure which sets up configurations and processes in hardware and firmware required to control device. In order to reduce time for upgrading software, object creation is completed before enablement and transferring control. At a last moment after object creation, object enablement within new software is performed. Object enablement is a fast procedure, because object enablement does not require allocating any special memory or any hardware objects. Change of control of a device can be prepared using two control objects. Device is then enabled on new software and old objects on current software are disabled. New software takes over control of all of objects one by one, from current or old software. In certain embodiments, if more than one device is controlled, each device may be migrated in succession, or one at a time, from current software to new software. In certain embodiments, ownership of context control for an emulated device may be transferred from current software to new software when current software relinquishes control, which may happen implicitly. In other embodiments, ownership of context control for an emulated device may be transferred from current software to new software when instructions are received from current software to give ownership to new software.

Use of a SmartNIC or a DPU to decrease total downtime for an in-service software upgrade can be used with any number of hardware and software configurations. In order to transition state of emulated objects from current software to new software, one option includes having current software and new software communicate and exchange messages over any suitable sharing system, such as socket, TCPIP, filesharing, or memory sharing, and transfer state information from current software to new software. In another example, a separate software upgrade program operates along with current software and new software. Software upgrade program communicates with both current software and new software. For instance, software upgrade program makes a query to current software for current state information. Software upgrade program then communicates to new software all queried state information, which can then be set up. Software upgrade program acts as manager or master between current software and new software. Accordingly, SmartNIC or a DPU can be used in conjunction or in place of either system to decrease downtime.

FIG.6illustrates an example communication structure600in which aspects of various embodiments can be implemented. In this example, for a given PCI device, in order to upgrade to new software, emulation software transfers at least two primary types of information. Information must be transferred because a PCI device can only be controlled by a single software at a given time. One primary type of information to be transferred is doorbells. Doorbells are typically communication information sent from a guest or a hypervisor or a bare metal system to a device. A doorbell indicates that there are packets available to send or receive. Doorbells can be handled only by a single software entity. Therefore, either current software or new software either must control doorbells, because doorbells cannot be controlled by both software at the same time. In order to accommodate this requirement, all information needed to handle doorbells is setup primitively in new software, while current software is still active and in control of device. When new software is prepared to take over control, doorbell handling control is transferred from old software to new software. In other words, PCI Memory-mapped I/O (MMIO) read/write handling is transferred from old software to new software.

A secondary type of information that must be transferred to upgrade software is MSI-X resources, such as MSI-X interrupts. MSI-X interrupts must be generated, which is usually performed by a single entity. In some embodiments, generation of MSI-X resources is only controlled by one entity at a time. When control of a device is transferred from current software to new software, generation of MSI-X interrupts is transferred from current software to new software.

Generally, downtime required to upgrade software, including both transfer time and enablement time, without use of a DPU or SmartNIC would be from about 500 milliseconds up to about 3.2 seconds depending on number of queues. Total downtime for a device controlled by current software upgraded to new software may be total of downtime required to suspend VQs by current software and downtime required to resume VQs by new software. In some embodiments, using a DPU or SmartNIC to preemptively transfer and setup required information in new software, a large portion of downtime setting up resources is reduced. With use of a DPU or SmartNIC to upgrade software, enablement of configurations by new software is still a linear amount of time based on number of queues, but enablement time generally only ranges from about 100 nanosecond to about 500 nanoseconds. Since enablement time is small, the total amount of time to migrate device handling from old software to new software can be less than about 10 milliseconds to about 100 milliseconds including both transfer time and enablement time. For instance, with 16 VQs, a VirtIO controller software upgrade would have less than about 100 milliseconds of I/O downtime.

Still referring toFIG.6, emulation doorbell context maps650,660include a number of context information652,662for a queue. In some examples, queue is a VQ, which sends and receives packets or sends a block I/O. A queue is mapped to a doorbell handling object, such as a completion queue. For example, when a PCI write is required, a completion entry is entered in completion queue, requesting PCI write to be completed. A continuous query notification (CQN) may register queries with database of doorbell handling object. Current software maps may queue to doorbell handling object. Additionally, currently emulated device610sends emulation device context information, including primary context630and transient context634, to memory management unit (MMU) database context map640. Additionally, the context information sent from the currently emulated device may include doorbells, MSI-X resources, PCIe memory mapped registers, IOBAR registers, transient queue, and I/O context information. After migration, new software620uses this migrated queue context information and emulation device context information sets642upon enablement, to control queue, and can then map queue and send emulation device context information to MMU database context map. In certain embodiments, all PCI accesses, including doorbells and MSI-X, are moved from current emulation device to new emulation device in last stage of set up. In certain embodiments, device MSI-X resource creation can be performed dynamically. In some instances, major firmware resources may be anchored to device emulation objects, instead of emulated devices. Additionally, firmware can generate information to all representor objects in stateless manner.

PCIe emulated devices and associated acceleration devices and firmware may generate asynchronous events to multiple representors. When the device emulation firmware is running in a stateless mode, current and alternate software will synchronize the state transitions and event handling based on active-active or active-passive mode. When the device emulation firmware is running in failover mode, where there may be a single control point, firmware will be generating asynchronous event only to the active representor.

Inference and Training Logic

FIG.7Aillustrates inference and/or training logic715used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic715are provided below in conjunction withFIGS.7A and/or7B.

In at least one embodiment, inference and/or training logic715may include, without limitation, a code and/or data storage705to store backward and/or output weight and/or input/output data corresponding to neurons or layers of a neural network trained and/or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and/or data storage705stores weight parameters and/or input/output data of each layer of a neural network trained or used in conjunction with one or more embodiments during backward propagation of input/output data and/or weight parameters during training and/or inferencing using aspects of one or more embodiments. In at least one embodiment, training logic715may include, or be coupled to code and/or data storage705to store graph code or other software to control timing and/or order, in which weight and/or other parameter information is to be loaded to configure, logic, including integer and/or floating point units (collectively, arithmetic logic units (ALUs). In at least one embodiment, code, such as graph code, loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which the code corresponds. In at least one embodiment, any portion of code and/or data storage705may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and/or data storage705may be internal or external to on one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and/or data storage705may be cache memory, DRAM, SRAM, non-volatile memory (e.g., Flash memory), or other storage. In at least one embodiment, choice of whether code and/or data storage705is internal or external to a processor, for example, or comprised of DRAM, SRAM, Flash or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and/or inferencing functions being performed, batch size of data used in inferencing and/or training of a neural network, or some combination of these factors.

In at least one embodiment, code and/or data storage701and code and/or data storage705may be separate storage structures. In at least one embodiment, code and/or data storage701and code and/or data storage705may be same storage structure. In at least one embodiment, code and/or data storage701and code and/or data storage705may be partially same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and/or data storage701and code and/or data storage705may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

In at least one embodiment, inference and/or training logic715may include, without limitation, one or more arithmetic logic unit(s) (“ALU(s)”)710, including integer and/or floating point units, to perform logical and/or mathematical operations based, at least in part on, or indicated by, training and/or inference code (e.g., graph code), a result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in an activation storage720that are functions of input/output and/or weight parameter data stored in code and/or data storage701and/or code and/or data storage705. In at least one embodiment, activations stored in activation storage720are generated according to linear algebraic and or matrix-based mathematics performed by ALU(s)710in response to performing instructions or other code, wherein weight values stored in code and/or data storage705and/or code and/or data storage701are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and/or data storage705or code and/or data storage701or another storage on or off-chip.

In at least one embodiment, ALU(s)710are included within one or more processors or other hardware logic devices or circuits, whereas in another embodiment, ALU(s)710may be external to a processor or other hardware logic device or circuit that uses them (e.g., a co-processor). In at least one embodiment, ALUs710may be included within a processor's execution units or otherwise within a bank of ALUs accessible by a processor's execution units either within same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and/or data storage701, code and/or data storage705, and activation storage720may be on same processor or other hardware logic device or circuit, whereas in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage720may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. Furthermore, inferencing and/or training code may be stored with other code accessible to a processor or other hardware logic or circuit and fetched and/or processed using a processor's fetch, decode, scheduling, execution, retirement and/or other logical circuits.

In at least one embodiment, activation storage720may be cache memory, DRAM, SRAM, non-volatile memory (e.g., Flash memory), or other storage. In at least one embodiment, activation storage720may be completely or partially within or external to one or more processors or other logical circuits. In at least one embodiment, choice of whether activation storage720is internal or external to a processor, for example, or comprised of DRAM, SRAM, Flash or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and/or inferencing functions being performed, batch size of data used in inferencing and/or training of a neural network, or some combination of these factors. In at least one embodiment, inference and/or training logic715illustrated inFIG.7Amay be used in conjunction with an application-specific integrated circuit (“ASIC”), such as Tensorflow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, inference and/or training logic715illustrated inFIG.7amay be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware, such as field programmable gate arrays (“FPGAs”).

FIG.7billustrates inference and/or training logic715, according to at least one or more embodiments. In at least one embodiment, inference and/or training logic715may include, without limitation, hardware logic in which computational resources are dedicated or otherwise exclusively used in conjunction with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, inference and/or training logic715illustrated inFIG.7bmay be used in conjunction with an application-specific integrated circuit (ASIC), such as Tensorflow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, inference and/or training logic715illustrated inFIG.7bmay be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware or other hardware, such as field programmable gate arrays (FPGAs). In at least one embodiment, inference and/or training logic715includes, without limitation, code and/or data storage701and code and/or data storage705, which may be used to store code (e.g., graph code), weight values and/or other information, including bias values, gradient information, momentum values, and/or other parameter or hyperparameter information. In at least one embodiment illustrated inFIG.7b, each of code and/or data storage701and code and/or data storage705is associated with a dedicated computational resource, such as computational hardware702and computational hardware706, respectively. In at least one embodiment, each of computational hardware702and computational hardware706comprises one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and/or data storage701and code and/or data storage705, respectively, result of which is stored in activation storage720.

In at least one embodiment, each of code and/or data storage701and705and corresponding computational hardware702and706, respectively, correspond to different layers of a neural network, such that resulting activation from one “storage/computational pair701/702” of code and/or data storage701and computational hardware702is provided as an input to “storage/computational pair705/706” of code and/or data storage705and computational hardware706, in order to mirror conceptual organization of a neural network. In at least one embodiment, each of storage/computational pairs701/702and705/706may correspond to more than one neural network layer. In at least one embodiment, additional storage/computation pairs (not shown) subsequent to or in parallel with storage computation pairs701/702and705/706may be included in inference and/or training logic715.

Data Center

FIG.8illustrates an example data center800, in which at least one embodiment may be used. In at least one embodiment, data center800includes a data center infrastructure layer810, a framework layer820, a software layer830, and an application layer840.

In at least one embodiment, as shown inFIG.8, data center infrastructure layer810may include a resource orchestrator812, grouped computing resources814, and node computing resources (“node C.R.s”)816(1)-816(N), where “N” represents any whole, positive integer. In at least one embodiment, node C.R.s816(1)-816(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input/output (“NW I/O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s from among node C.R.s816(1)-816(N) may be a server having one or more of above-mentioned computing resources.

In at least one embodiment, resource orchestrator812may configure or otherwise control one or more node C.R.s816(1)-816(N) and/or grouped computing resources814. In at least one embodiment, resource orchestrator812may include a software design infrastructure (“SDI”) management entity for data center800. In at least one embodiment, resource orchestrator may include hardware, software or some combination thereof.

In at least one embodiment, as shown inFIG.8, framework layer820includes a job scheduler822, a configuration manager824, a resource manager826and a distributed file system828. In at least one embodiment, framework layer820may include a framework to support software832of software layer830and/or one or more application(s)842of application layer840. In at least one embodiment, software832or application(s)842may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer820may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may use distributed file system828for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler822may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center800. In at least one embodiment, configuration manager824may be capable of configuring different layers such as software layer830and framework layer820including Spark and distributed file system828for supporting large-scale data processing. In at least one embodiment, resource manager826may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system828and job scheduler822. In at least one embodiment, clustered or grouped computing resources may include grouped computing resource814at data center infrastructure layer810. In at least one embodiment, resource manager826may coordinate with resource orchestrator812to manage these mapped or allocated computing resources.

In at least one embodiment, software832included in software layer830may include software used by at least portions of node C.R.s816(1)-816(N), grouped computing resources814, and/or distributed file system828of framework layer820. The one or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software.

In at least one embodiment, application(s)842included in application layer840may include one or more types of applications used by at least portions of node C.R.s816(1)-816(N), grouped computing resources814, and/or distributed file system828of framework layer820. One or more types of applications may include, but are not limited to, any number of a genomics application, a cognitive compute, and a machine learning application, including training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.) or other machine learning applications used in conjunction with one or more embodiments.

In at least one embodiment, any of configuration manager824, resource manager826, and resource orchestrator812may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions may relieve a data center operator of data center800from making possibly bad configuration decisions and possibly avoiding underused and/or poor performing portions of a data center.

Such components can be used to update backend software and may be trained to infer downtime requirement.

Computer Systems

In at least one embodiment, computer system900may include, without limitation, processor902that may include, without limitation, one or more execution units908to perform machine learning model training and/or inferencing according to techniques described herein. In at least one embodiment, computer system900is a single processor desktop or server system, but in another embodiment, computer system900may be a multiprocessor system. In at least one embodiment, processor902may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor902may be coupled to a processor bus910that may transmit data signals between processor902and other components in computer system900.

In at least one embodiment, processor902may include, without limitation, a Level 1 (“L1”) internal cache memory (“cache”)904. In at least one embodiment, processor902may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor902. Other embodiments may also include a combination of both internal and external caches depending on particular implementation and needs. In at least one embodiment, a register file906may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and an instruction pointer register.

In at least one embodiment, execution unit908, including, without limitation, logic to perform integer and floating point operations, also resides in processor902. In at least one embodiment, processor902may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit908may include logic to handle a packed instruction set909. In at least one embodiment, by including packed instruction set909in an instruction set of a general-purpose processor, along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in processor902. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using a full width of a processor's data bus for performing operations on packed data, which may eliminate a need to transfer smaller units of data across that processor's data bus to perform one or more operations one data element at a time.

In at least one embodiment, execution unit908may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system900may include, without limitation, a memory920. In at least one embodiment, memory920may be a Dynamic Random Access Memory (“DRAM”) device, a Static Random Access Memory (“SRAM”) device, a flash memory device, or another memory device. In at least one embodiment, memory920may store instruction(s)919and/or data921represented by data signals that may be executed by processor902.

In at least one embodiment, a system logic chip may be coupled to processor bus910and memory920. In at least one embodiment, a system logic chip may include, without limitation, a memory controller hub (“MCH”)916, and processor902may communicate with MCH916via processor bus910. In at least one embodiment, MCH916may provide a high bandwidth memory path918to memory920for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH916may direct data signals between processor902, memory920, and other components in computer system900and to bridge data signals between processor bus910, memory920, and a system I/O interface922. In at least one embodiment, a system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH916may be coupled to memory920through high bandwidth memory path918and a graphics/video card912may be coupled to MCH916through an Accelerated Graphics Port (“AGP”) interconnect914.

In at least one embodiment, computer system900may use system I/O interface922as a proprietary hub interface bus to couple MCH916to an I/O controller hub (“ICH”)930. In at least one embodiment, ICH930may provide direct connections to some I/O devices via a local I/O bus. In at least one embodiment, a local I/O bus may include, without limitation, a high-speed I/O bus for connecting peripherals to memory920, a chipset, and processor902. Examples may include, without limitation, an audio controller929, a firmware hub (“flash BIOS”)928, a wireless transceiver926, a data storage924, a legacy I/O controller923containing user input and keyboard interfaces925, a serial expansion port927, such as a Universal Serial Bus (“USB”) port, and a network controller934. In at least one embodiment, data storage924may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

In at least one embodiment,FIG.9illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments,FIG.9may illustrate an exemplary SoC. In at least one embodiment, devices illustrated inFIG.9may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of computer system900are interconnected using compute express link (CXL) interconnects.

Such components can be used to update backend software and may be trained to infer downtime requirement.

FIG.10is a block diagram illustrating an electronic device1000for utilizing a processor1010, according to at least one embodiment. In at least one embodiment, electronic device1000may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

In at least one embodiment, system1000may include, without limitation, processor1010communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor1010coupled using a bus or interface, such as a 1° ° C. bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3), or a Universal Asynchronous Receiver/Transmitter (“UART”) bus. In at least one embodiment,FIG.10illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments,FIG.10may illustrate an exemplary System on a Chip (“SoC”). In at least one embodiment, devices illustrated inFIG.10may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components ofFIG.10are interconnected using compute express link (CXL) interconnects.

In at least one embodiment,FIG.10may include a display1024, a touch screen1025, a touch pad1030, a Near Field Communications unit (“NFC”)1045, a sensor hub1040, a thermal sensor1046, an Express Chipset (“EC”)1035, a Trusted Platform Module (“TPM”)1038, BIOS/firmware/flash memory (“BIOS, FW Flash”)1022, a DSP1060, a drive1020such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”), a wireless local area network unit (“WLAN”)1050, a Bluetooth unit1052, a Wireless Wide Area Network unit (“WWAN”)1056, a Global Positioning System (GPS)1055, a camera (“USB 3.0 camera”)1054such as a USB 3.0 camera, and/or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”)1015implemented in, for example, LPDDR3 standard. These components may each be implemented in any suitable manner.

In at least one embodiment, other components may be communicatively coupled to processor1010through components discussed above. In at least one embodiment, an accelerometer1041, Ambient Light Sensor (“ALS”)1042, compass1043, and a gyroscope1044may be communicatively coupled to sensor hub1040. In at least one embodiment, thermal sensor1039, a fan1037, a keyboard1046, and a touch pad1030may be communicatively coupled to EC1035. In at least one embodiment, speaker1063, headphones1064, and microphone (“mic”)1065may be communicatively coupled to an audio unit (“audio codec and class d amp”)1062, which may in turn be communicatively coupled to DSP1060. In at least one embodiment, audio unit1064may include, for example and without limitation, an audio coder/decoder (“codec”) and a class D amplifier. In at least one embodiment, SIM card (“SIM”)1057may be communicatively coupled to WWAN unit1056. In at least one embodiment, components such as WLAN unit1050and Bluetooth unit1052, as well as WWAN unit1056may be implemented in a Next Generation Form Factor (“NGFF”).

Such components can be used to update backend software and may be trained to infer downtime requirement.

Processors

FIG.11is a block diagram of a processing system, according to at least one embodiment. In at least one embodiment, system1100includes one or more processors1102and one or more graphics processors1108, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors1102or processor cores1107. In at least one embodiment, system1100is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

In at least one embodiment, system1100can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system1100is a mobile phone, smart phone, tablet computing device or mobile Internet device. In at least one embodiment, processing system1100can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In at least one embodiment, processing system1100is a television or set top box device having one or more processors1102and a graphical interface generated by one or more graphics processors1108.

In at least one embodiment, one or more processors1102each include one or more processor cores1107to process instructions which, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores1107is configured to process a specific instruction set1109. In at least one embodiment, instruction set1109may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). In at least one embodiment, processor cores1107may each process a different instruction set1109, which may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core1107may also include other processing devices, such a Digital Signal Processor (DSP).

In at least one embodiment, processor1102includes cache memory1104. In at least one embodiment, processor1102can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor1102. In at least one embodiment, processor1102also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores1107using known cache coherency techniques. In at least one embodiment, register file1106is additionally included in processor1102which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). In at least one embodiment, register file1106may include general-purpose registers or other registers.

In at least one embodiment, one or more processor(s)1102are coupled with one or more interface bus(es)1110to transmit communication signals such as address, data, or control signals between processor1102and other components in system1100. In at least one embodiment, interface bus1110, in one embodiment, can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, interface1110is not limited to a DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory busses, or other types of interface busses. In at least one embodiment processor(s)1102include an integrated memory controller1116and a platform controller hub1130. In at least one embodiment, memory controller1116facilitates communication between a memory device and other components of system1100, while platform controller hub (PCH)1130provides connections to I/O devices via a local I/O bus.

In at least one embodiment, memory device1120can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In at least one embodiment memory device1120can operate as system memory for system1100, to store data1122and instructions1121for use when one or more processors1102executes an application or process. In at least one embodiment, memory controller1116also couples with an optional external graphics processor1112, which may communicate with one or more graphics processors1108in processors1102to perform graphics and media operations. In at least one embodiment, a display device1111can connect to processor(s)1102. In at least one embodiment display device1111can include one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device1111can include a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

In at least one embodiment, platform controller hub1130enables peripherals to connect to memory device1120and processor1102via a high-speed I/O bus. In at least one embodiment, I/O peripherals include, but are not limited to, an audio controller1146, a network controller1134, a firmware interface1128, a wireless transceiver1126, touch sensors1125, a data storage device1124(e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device1124can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, touch sensors1125can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver1126can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface1128enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, network controller1134can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples with interface bus1110. In at least one embodiment, audio controller1146is a multi-channel high definition audio controller. In at least one embodiment, system1100includes an optional legacy I/O controller1140for coupling legacy (e.g., Personal System 2 (PS/2)) devices to system. In at least one embodiment, platform controller hub1130can also connect to one or more Universal Serial Bus (USB) controllers1142connect input devices, such as keyboard and mouse1143combinations, a camera1144, or other USB input devices.

In at least one embodiment, an instance of memory controller1116and platform controller hub1130may be integrated into a discreet external graphics processor, such as external graphics processor1112. In at least one embodiment, platform controller hub1130and/or memory controller1116may be external to one or more processor(s)1102. For example, in at least one embodiment, system1100can include an external memory controller1116and platform controller hub1130, which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with processor(s)1102.

Inference and/or training logic715are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic715are provided below in conjunction withFIGS.7aand/or7b8b. In at least one embodiment portions or all of inference and/or training logic715may be incorporated into graphics processor1500. For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in a graphics processor. Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated inFIG.8A or8B. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of a graphics processor to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

Such components can be used to update backend software and may be trained to infer downtime requirement.

FIG.12is a block diagram of a processor1200having one or more processor cores1202A-1202N, an integrated memory controller1214, and an integrated graphics processor1208, according to at least one embodiment. In at least one embodiment, processor1200can include additional cores up to and including additional core1202N represented by dashed lined boxes. In at least one embodiment, each of processor cores1202A-1202N includes one or more internal cache units1204A-1204N. In at least one embodiment, each processor core also has access to one or more shared cached units1206.

In at least one embodiment, internal cache units1204A-1204N and shared cache units1206represent a cache memory hierarchy within processor1200. In at least one embodiment, cache memory units1204A-1204N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where a highest level of cache before external memory is classified as an LLC. In at least one embodiment, cache coherency logic maintains coherency between various cache units1206and1204A-1204N.

In at least one embodiment, processor1200may also include a set of one or more bus controller units1216and a system agent core1210. In at least one embodiment, one or more bus controller units1216manage a set of peripheral buses, such as one or more PCI or PCI express busses. In at least one embodiment, system agent core1210provides management functionality for various processor components. In at least one embodiment, system agent core1210includes one or more integrated memory controllers1214to manage access to various external memory devices (not shown).

In at least one embodiment, one or more of processor cores1202A-1202N include support for simultaneous multi-threading. In at least one embodiment, system agent core1210includes components for coordinating and operating cores1202A-1202N during multi-threaded processing. In at least one embodiment, system agent core1210may additionally include a power control unit (PCU), which includes logic and components to regulate one or more power states of processor cores1202A-1202N and graphics processor1208.

In at least one embodiment, processor1200additionally includes graphics processor1208to execute graphics processing operations. In at least one embodiment, graphics processor1208couples with shared cache units1206, and system agent core1210, including one or more integrated memory controllers1214. In at least one embodiment, system agent core1210also includes a display controller1211to drive graphics processor output to one or more coupled displays. In at least one embodiment, display controller1211may also be a separate module coupled with graphics processor1208via at least one interconnect, or may be integrated within graphics processor1208.

In at least one embodiment, a ring based interconnect unit1212is used to couple internal components of processor1200. In at least one embodiment, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques. In at least one embodiment, graphics processor1208couples with ring interconnect1212via an I/O link1213.

In at least one embodiment, I/O link1213represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module1218, such as an eDRAM module. In at least one embodiment, each of processor cores1202A-1202N and graphics processor1208use embedded memory modules1218as a shared Last Level Cache.

In at least one embodiment, processor cores1202A-1202N are homogenous cores executing a common instruction set architecture. In at least one embodiment, processor cores1202A-1202N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores1202A-1202N execute a common instruction set, while one or more other cores of processor cores1202A-1202N executes a subset of a common instruction set or a different instruction set. In at least one embodiment, processor cores1202A-1202N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. In at least one embodiment, processor1200can be implemented on one or more chips or as an SoC integrated circuit.

Inference and/or training logic715are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic715are provided below in conjunction withFIGS.7aand/or7b. In at least one embodiment portions or all of inference and/or training logic715may be incorporated into processor1200. For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in graphics processor1212, graphics core(s)1202A-1202N, or other components inFIG.12. Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated inFIG.7A or7B. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor1200to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

Such components can be used to update backend software and may be trained to infer downtime requirement.

Virtualized Computing Platform

FIG.13is an example data flow diagram for a process1300of generating and deploying an image processing and inferencing pipeline, in accordance with at least one embodiment. In at least one embodiment, process1300may be deployed for use with imaging devices, processing devices, and/or other device types at one or more facilities1302. Process1300may be executed within a training system1304and/or a deployment system1306. In at least one embodiment, training system1304may be used to perform training, deployment, and implementation of machine learning models (e.g., neural networks, object detection algorithms, computer vision algorithms, etc.) for use in deployment system1306. In at least one embodiment, deployment system1306may be configured to offload processing and compute resources among a distributed computing environment to reduce infrastructure requirements at facility1302. In at least one embodiment, one or more applications in a pipeline may use or call upon services (e.g., inference, visualization, compute, AI, etc.) of deployment system1306during execution of applications.

In at least one embodiment, some of applications used in advanced processing and inferencing pipelines may use machine learning models or other AI to perform one or more processing steps. In at least one embodiment, machine learning models may be trained at facility1302using data1308(such as imaging data) generated at facility1302(and stored on one or more picture archiving and communication system (PACS) servers at facility1302), may be trained using imaging or sequencing data1308from another facility(ies), or a combination thereof. In at least one embodiment, training system1304may be used to provide applications, services, and/or other resources for generating working, deployable machine learning models for deployment system1306.

In at least one embodiment, model registry1324may be backed by object storage that may support versioning and object metadata. In at least one embodiment, object storage may be accessible through, for example, a cloud storage (e.g., cloud1226ofFIG.12) compatible application programming interface (API) from within a cloud platform. In at least one embodiment, machine learning models within model registry1324may uploaded, listed, modified, or deleted by developers or partners of a system interacting with an API. In at least one embodiment, an API may provide access to methods that allow users with appropriate credentials to associate models with applications, such that models may be executed as part of execution of containerized instantiations of applications.

In at least one embodiment, training pipeline1304(FIG.13) may include a scenario where facility1302is training their own machine learning model, or has an existing machine learning model that needs to be optimized or updated. In at least one embodiment, imaging data1308generated by imaging device(s), sequencing devices, and/or other device types may be received. In at least one embodiment, once imaging data1308is received, AI-assisted annotation1310may be used to aid in generating annotations corresponding to imaging data1308to be used as ground truth data for a machine learning model. In at least one embodiment, AI-assisted annotation1310may include one or more machine learning models (e.g., convolutional neural networks (CNNs)) that may be trained to generate annotations corresponding to certain types of imaging data1308(e.g., from certain devices). In at least one embodiment, AI-assisted annotations1310may then be used directly, or may be adjusted or fine-tuned using an annotation tool to generate ground truth data. In at least one embodiment, AI-assisted annotations1310, labeled clinic data1312, or a combination thereof may be used as ground truth data for training a machine learning model. In at least one embodiment, a trained machine learning model may be referred to as output model1316, and may be used by deployment system1306, as described herein.

In at least one embodiment, a training pipeline may include a scenario where facility1302needs a machine learning model for use in performing one or more processing tasks for one or more applications in deployment system1306, but facility1302may not currently have such a machine learning model (or may not have a model that is optimized, efficient, or effective for such purposes). In at least one embodiment, an existing machine learning model may be selected from a model registry1324. In at least one embodiment, model registry1324may include machine learning models trained to perform a variety of different inference tasks on imaging data. In at least one embodiment, machine learning models in model registry1324may have been trained on imaging data from different facilities than facility1302(e.g., facilities remotely located). In at least one embodiment, machine learning models may have been trained on imaging data from one location, two locations, or any number of locations. In at least one embodiment, when being trained on imaging data from a specific location, training may take place at that location, or at least in a manner that protects confidentiality of imaging data or restricts imaging data from being transferred off-premises. In at least one embodiment, once a model is trained—or partially trained—at one location, a machine learning model may be added to model registry1324. In at least one embodiment, a machine learning model may then be retrained, or updated, at any number of other facilities, and a retrained or updated model may be made available in model registry1324. In at least one embodiment, a machine learning model may then be selected from model registry1324—and referred to as output model1316—and may be used in deployment system1306to perform one or more processing tasks for one or more applications of a deployment system.

In at least one embodiment, a scenario may include facility1302requiring a machine learning model for use in performing one or more processing tasks for one or more applications in deployment system1306, but facility1302may not currently have such a machine learning model (or may not have a model that is optimized, efficient, or effective for such purposes). In at least one embodiment, a machine learning model selected from model registry1324may not be fine-tuned or optimized for imaging data1308generated at facility1302because of differences in populations, robustness of training data used to train a machine learning model, diversity in anomalies of training data, and/or other issues with training data. In at least one embodiment, AI-assisted annotation1310may be used to aid in generating annotations corresponding to imaging data1308to be used as ground truth data for retraining or updating a machine learning model. In at least one embodiment, labeled data1312may be used as ground truth data for training a machine learning model. In at least one embodiment, retraining or updating a machine learning model may be referred to as model training1314. In at least one embodiment, model training1314—e.g., AI-assisted annotations1310, labeled clinic data1312, or a combination thereof—may be used as ground truth data for retraining or updating a machine learning model. In at least one embodiment, a trained machine learning model may be referred to as output model1316, and may be used by deployment system1306, as described herein.

In at least one embodiment, deployment system1306may include software1318, services1320, hardware1322, and/or other components, features, and functionality. In at least one embodiment, deployment system1306may include a software “stack,” such that software1318may be built on top of services1320and may use services1320to perform some or all of processing tasks, and services1320and software1318may be built on top of hardware1322and use hardware1322to execute processing, storage, and/or other compute tasks of deployment system1306. In at least one embodiment, software1318may include any number of different containers, where each container may execute an instantiation of an application. In at least one embodiment, each application may perform one or more processing tasks in an advanced processing and inferencing pipeline (e.g., inferencing, object detection, feature detection, segmentation, image enhancement, calibration, etc.). In at least one embodiment, an advanced processing and inferencing pipeline may be defined based on selections of different containers that are desired or required for processing imaging data1308, in addition to containers that receive and configure imaging data for use by each container and/or for use by facility1302after processing through a pipeline (e.g., to convert outputs back to a usable data type). In at least one embodiment, a combination of containers within software1318(e.g., that make up a pipeline) may be referred to as a virtual instrument (as described in more detail herein), and a virtual instrument may leverage services1320and hardware1322to execute some or all processing tasks of applications instantiated in containers.

In at least one embodiment, a data processing pipeline may receive input data (e.g., imaging data1308) in a specific format in response to an inference request (e.g., a request from a user of deployment system1306). In at least one embodiment, input data may be representative of one or more images, video, and/or other data representations generated by one or more imaging devices. In at least one embodiment, data may undergo pre-processing as part of data processing pipeline to prepare data for processing by one or more applications. In at least one embodiment, post-processing may be performed on an output of one or more inferencing tasks or other processing tasks of a pipeline to prepare an output data for a next application and/or to prepare output data for transmission and/or use by a user (e.g., as a response to an inference request). In at least one embodiment, inferencing tasks may be performed by one or more machine learning models, such as trained or deployed neural networks, which may include output models1316of training system1304.

In at least one embodiment, tasks of data processing pipeline may be encapsulated in a container(s) that each represents a discrete, fully functional instantiation of an application and virtualized computing environment that is able to reference machine learning models. In at least one embodiment, containers or applications may be published into a private (e.g., limited access) area of a container registry (described in more detail herein), and trained or deployed models may be stored in model registry1324and associated with one or more applications. In at least one embodiment, images of applications (e.g., container images) may be available in a container registry, and once selected by a user from a container registry for deployment in a pipeline, an image may be used to generate a container for an instantiation of an application for use by a user's system.

In at least one embodiment, developers (e.g., software developers, clinicians, doctors, etc.) may develop, publish, and store applications (e.g., as containers) for performing image processing and/or inferencing on supplied data. In at least one embodiment, development, publishing, and/or storing may be performed using a software development kit (SDK) associated with a system (e.g., to ensure that an application and/or container developed is compliant with or compatible with a system). In at least one embodiment, an application that is developed may be tested locally (e.g., at a first facility, on data from a first facility) with an SDK which may support at least some of services1320as a system (e.g., system1200ofFIG.12). In at least one embodiment, because DICOM objects may contain anywhere from one to hundreds of images or other data types, and due to a variation in data, a developer may be responsible for managing (e.g., setting constructs for, building pre-processing into an application, etc.) extraction and preparation of incoming data. In at least one embodiment, once validated by system1300(e.g., for accuracy), an application may be available in a container registry for selection and/or implementation by a user to perform one or more processing tasks with respect to data at a facility (e.g., a second facility) of a user.

In at least one embodiment, developers may then share applications or containers through a network for access and use by users of a system (e.g., system1300ofFIG.13). In at least one embodiment, completed and validated applications or containers may be stored in a container registry and associated machine learning models may be stored in model registry1324. In at least one embodiment, a requesting entity—who provides an inference or image processing request—may browse a container registry and/or model registry1324for an application, container, dataset, machine learning model, etc., select a desired combination of elements for inclusion in data processing pipeline, and submit an imaging processing request. In at least one embodiment, a request may include input data (and associated patient data, in some examples) that is necessary to perform a request, and/or may include a selection of application(s) and/or machine learning models to be executed in processing a request. In at least one embodiment, a request may then be passed to one or more components of deployment system1306(e.g., a cloud) to perform processing of data processing pipeline. In at least one embodiment, processing by deployment system1306may include referencing selected elements (e.g., applications, containers, models, etc.) from a container registry and/or model registry1324. In at least one embodiment, once results are generated by a pipeline, results may be returned to a user for reference (e.g., for viewing in a viewing application suite executing on a local, on-premises workstation or terminal).

In at least one embodiment, to aid in processing or execution of applications or containers in pipelines, services1320may be leveraged. In at least one embodiment, services1320may include compute services, artificial intelligence (AI) services, visualization services, and/or other service types. In at least one embodiment, services1320may provide functionality that is common to one or more applications in software1318, so functionality may be abstracted to a service that may be called upon or leveraged by applications. In at least one embodiment, functionality provided by services1320may run dynamically and more efficiently, while also scaling well by allowing applications to process data in parallel (e.g., using a parallel computing platform1230(FIG.12)). In at least one embodiment, rather than each application that shares a same functionality offered by a service1320being required to have a respective instance of service1320, service1320may be shared between and among various applications. In at least one embodiment, services may include an inference server or engine that may be used for executing detection or segmentation tasks, as non-limiting examples. In at least one embodiment, a model training service may be included that may provide machine learning model training and/or retraining capabilities. In at least one embodiment, a data augmentation service may further be included that may provide GPU accelerated data (e.g., DICOM, RIS, CIS, REST compliant, RPC, raw, etc.) extraction, resizing, scaling, and/or other augmentation. In at least one embodiment, a visualization service may be used that may add image rendering effects—such as ray-tracing, rasterization, denoising, sharpening, etc.—to add realism to two-dimensional (2D) and/or three-dimensional (3D) models. In at least one embodiment, virtual instrument services may be included that provide for beam-forming, segmentation, inferencing, imaging, and/or support for other applications within pipelines of virtual instruments.

In at least one embodiment, where a service1320includes an AI service (e.g., an inference service), one or more machine learning models may be executed by calling upon (e.g., as an API call) an inference service (e.g., an inference server) to execute machine learning model(s), or processing thereof, as part of application execution. In at least one embodiment, where another application includes one or more machine learning models for segmentation tasks, an application may call upon an inference service to execute machine learning models for performing one or more of processing operations associated with segmentation tasks. In at least one embodiment, software1318implementing advanced processing and inferencing pipeline that includes segmentation application and anomaly detection application may be streamlined because each application may call upon a same inference service to perform one or more inferencing tasks.

In at least one embodiment, hardware1322may include GPUs, CPUs, graphics cards, an AI/deep learning system (e.g., an AI supercomputer, such as NVIDIA's DGX), a cloud platform, or a combination thereof. In at least one embodiment, different types of hardware1322may be used to provide efficient, purpose-built support for software1318and services1320in deployment system1306. In at least one embodiment, use of GPU processing may be implemented for processing locally (e.g., at facility1302), within an AI/deep learning system, in a cloud system, and/or in other processing components of deployment system1306to improve efficiency, accuracy, and efficacy of image processing and generation. In at least one embodiment, software1318and/or services1320may be optimized for GPU processing with respect to deep learning, machine learning, and/or high-performance computing, as non-limiting examples. In at least one embodiment, at least some of computing environment of deployment system1306and/or training system1304may be executed in a datacenter one or more supercomputers or high performance computing systems, with GPU optimized software (e.g., hardware and software combination of NVIDIA's DGX System). In at least one embodiment, hardware1322may include any number of GPUs that may be called upon to perform processing of data in parallel, as described herein. In at least one embodiment, cloud platform may further include GPU processing for GPU-optimized execution of deep learning tasks, machine learning tasks, or other computing tasks. In at least one embodiment, cloud platform (e.g., NVIDIA's NGC) may be executed using an AI/deep learning supercomputer(s) and/or GPU-optimized software (e.g., as provided on NVIDIA's DGX Systems) as a hardware abstraction and scaling platform. In at least one embodiment, cloud platform may integrate an application container clustering system or orchestration system (e.g., KUBERNETES) on multiple GPUs to enable seamless scaling and load balancing.

FIG.14is a system diagram for an example system1400for generating and deploying an imaging deployment pipeline, in accordance with at least one embodiment. In at least one embodiment, system1400may be used to implement process1300ofFIG.13and/or other processes including advanced processing and inferencing pipelines. In at least one embodiment, system1400may include training system1304and deployment system1306. In at least one embodiment, training system1304and deployment system1306may be implemented using software1318, services1320, and/or hardware1322, as described herein.

In at least one embodiment, system1400(e.g., training system1304and/or deployment system1306) may implemented in a cloud computing environment (e.g., using cloud1426). In at least one embodiment, system1400may be implemented locally with respect to a healthcare services facility, or as a combination of both cloud and local computing resources. In at least one embodiment, access to APIs in cloud1426may be restricted to authorized users through enacted security measures or protocols. In at least one embodiment, a security protocol may include web tokens that may be signed by an authentication (e.g., AuthN, AuthZ, Gluecon, etc.) service and may carry appropriate authorization. In at least one embodiment, APIs of virtual instruments (described herein), or other instantiations of system1400, may be restricted to a set of public IPs that have been vetted or authorized for interaction.

In at least one embodiment, various components of system1400may communicate between and among one another using any of a variety of different network types, including but not limited to local area networks (LANs) and/or wide area networks (WANs) via wired and/or wireless communication protocols. In at least one embodiment, communication between facilities and components of system1400(e.g., for transmitting inference requests, for receiving results of inference requests, etc.) may be communicated over data bus(ses), wireless data protocols (Wi-Fi), wired data protocols (e.g., Ethernet), etc.

In at least one embodiment, training system1304may execute training pipelines1404, similar to those described herein with respect toFIG.13. In at least one embodiment, where one or more machine learning models are to be used in deployment pipelines1410by deployment system1306, training pipelines1404may be used to train or retrain one or more (e.g. pre-trained) models, and/or implement one or more of pre-trained models1406(e.g., without a need for retraining or updating). In at least one embodiment, as a result of training pipelines1404, output model(s)1316may be generated. In at least one embodiment, training pipelines1404may include any number of processing steps, such as but not limited to imaging data (or other input data) conversion or adaption In at least one embodiment, for different machine learning models used by deployment system1306, different training pipelines1404may be used. In at least one embodiment, training pipeline1404similar to a first example described with respect toFIG.13may be used for a first machine learning model, training pipeline1404similar to a second example described with respect toFIG.13may be used for a second machine learning model, and training pipeline1404similar to a third example described with respect toFIG.13may be used for a third machine learning model. In at least one embodiment, any combination of tasks within training system1304may be used depending on what is required for each respective machine learning model. In at least one embodiment, one or more of machine learning models may already be trained and ready for deployment so machine learning models may not undergo any processing by training system1304, and may be implemented by deployment system1306.

In at least one embodiment, output model(s)1316and/or pre-trained model(s)1406may include any types of machine learning models depending on implementation or embodiment. In at least one embodiment, and without limitation, machine learning models used by system1400may include machine learning model(s) using linear regression, logistic regression, decision trees, support vector machines (SVM), Naïve Bayes, k-nearest neighbor (Knn), K means clustering, random forest, dimensionality reduction algorithms, gradient boosting algorithms, neural networks (e.g., auto-encoders, convolutional, recurrent, perceptrons, Long/Short Term Memory (LSTM), Hopfield, Boltzmann, deep belief, deconvolutional, generative adversarial, liquid state machine, etc.), and/or other types of machine learning models.

In at least one embodiment, training pipelines1404may include AI-assisted annotation, as described in more detail herein with respect to at leastFIG.14B. In at least one embodiment, labeled data1312(e.g., traditional annotation) may be generated by any number of techniques. In at least one embodiment, labels or other annotations may be generated within a drawing program (e.g., an annotation program), a computer aided design (CAD) program, a labeling program, another type of program suitable for generating annotations or labels for ground truth, and/or may be hand drawn, in some examples. In at least one embodiment, ground truth data may be synthetically produced (e.g., generated from computer models or renderings), real produced (e.g., designed and produced from real-world data), machine-automated (e.g., using feature analysis and learning to extract features from data and then generate labels), human annotated (e.g., labeler, or annotation expert, defines location of labels), and/or a combination thereof. In at least one embodiment, for each instance of imaging data1308(or other data type used by machine learning models), there may be corresponding ground truth data generated by training system1304. In at least one embodiment, AI-assisted annotation may be performed as part of deployment pipelines1410; either in addition to, or in lieu of AI-assisted annotation included in training pipelines1404. In at least one embodiment, system1400may include a multi-layer platform that may include a software layer (e.g., software1318) of diagnostic applications (or other application types) that may perform one or more medical imaging and diagnostic functions. In at least one embodiment, system1400may be communicatively coupled to (e.g., via encrypted links) PACS server networks of one or more facilities. In at least one embodiment, system1400may be configured to access and referenced data from PACS servers to perform operations, such as training machine learning models, deploying machine learning models, image processing, inferencing, and/or other operations.

In at least one embodiment, a software layer may be implemented as a secure, encrypted, and/or authenticated API through which applications or containers may be invoked (e.g., called) from an external environment(s) (e.g., facility1302). In at least one embodiment, applications may then call or execute one or more services1320for performing compute, AI, or visualization tasks associated with respective applications, and software1318and/or services1320may leverage hardware1322to perform processing tasks in an effective and efficient manner.

In at least one embodiment, deployment system1306may execute deployment pipelines1410. In at least one embodiment, deployment pipelines1410may include any number of applications that may be sequentially, non-sequentially, or otherwise applied to imaging data (and/or other data types) generated by imaging devices, sequencing devices, genomics devices, etc.—including AI-assisted annotation, as described above. In at least one embodiment, as described herein, a deployment pipeline1410for an individual device may be referred to as a virtual instrument for a device (e.g., a virtual ultrasound instrument, a virtual CT scan instrument, a virtual sequencing instrument, etc.). In at least one embodiment, for a single device, there may be more than one deployment pipeline1410depending on information desired from data generated by a device. In at least one embodiment, where detections of anomalies are desired from an MRI machine, there may be a first deployment pipeline1410, and where image enhancement is desired from output of an MRI machine, there may be a second deployment pipeline1410.

In at least one embodiment, an image generation application may include a processing task that includes use of a machine learning model. In at least one embodiment, a user may desire to use their own machine learning model, or to select a machine learning model from model registry1324. In at least one embodiment, a user may implement their own machine learning model or select a machine learning model for inclusion in an application for performing a processing task. In at least one embodiment, applications may be selectable and customizable, and by defining constructs of applications, deployment and implementation of applications for a particular user are presented as a more seamless user experience. In at least one embodiment, by leveraging other features of system1400—such as services1320and hardware1322—deployment pipelines1410may be even more user friendly, provide for easier integration, and produce more accurate, efficient, and timely results.

In at least one embodiment, deployment system1306may include a user interface1413(e.g., a graphical user interface, a web interface, etc.) that may be used to select applications for inclusion in deployment pipeline(s)1410, arrange applications, modify or change applications or parameters or constructs thereof, use and interact with deployment pipeline(s)1410during set-up and/or deployment, and/or to otherwise interact with deployment system1306. In at least one embodiment, although not illustrated with respect to training system1304, user interface1414(or a different user interface) may be used for selecting models for use in deployment system1306, for selecting models for training, or retraining, in training system1304, and/or for otherwise interacting with training system1304.

In at least one embodiment, pipeline manager1412may be used, in addition to an application orchestration system1428, to manage interaction between applications or containers of deployment pipeline(s)1410and services1320and/or hardware1322. In at least one embodiment, pipeline manager1412may be configured to facilitate interactions from application to application, from application to service1320, and/or from application or service to hardware1322. In at least one embodiment, although illustrated as included in software1318, this is not intended to be limiting, and in some examples pipeline manager1412may be included in services1320. In at least one embodiment, application orchestration system1428(e.g., Kubernetes, DOCKER, etc.) may include a container orchestration system that may group applications into containers as logical units for coordination, management, scaling, and deployment. In at least one embodiment, by associating applications from deployment pipeline(s)1410(e.g., a reconstruction application, a segmentation application, etc.) with individual containers, each application may execute in a self-contained environment (e.g., at a kernel level) to increase speed and efficiency.

In at least one embodiment, each application and/or container (or image thereof) may be individually developed, modified, and deployed (e.g., a first user or developer may develop, modify, and deploy a first application and a second user or developer may develop, modify, and deploy a second application separate from a first user or developer), which may allow for focus on, and attention to, a task of a single application and/or container(s) without being hindered by tasks of another application(s) or container(s). In at least one embodiment, communication, and cooperation between different containers or applications may be aided by pipeline manager1412and application orchestration system1428. In at least one embodiment, so long as an expected input and/or output of each container or application is known by a system (e.g., based on constructs of applications or containers), application orchestration system1428and/or pipeline manager1412may facilitate communication among and between, and sharing of resources among and between, each of applications or containers. In at least one embodiment, because one or more of applications or containers in deployment pipeline(s)1410may share same services and resources, application orchestration system1428may orchestrate, load balance, and determine sharing of services or resources between and among various applications or containers. In at least one embodiment, a scheduler may be used to track resource requirements of applications or containers, current usage or planned usage of these resources, and resource availability. In at least one embodiment, a scheduler may thus allocate resources to different applications and distribute resources between and among applications in view of requirements and availability of a system. In some examples, a scheduler (and/or other component of application orchestration system1428) may determine resource availability and distribution based on constraints imposed on a system (e.g., user constraints), such as quality of service (QoS), urgency of need for data outputs (e.g., to determine whether to execute real-time processing or delayed processing), etc.

In at least one embodiment, services1320leveraged by and shared by applications or containers in deployment system1306may include compute services1416, AI services1418, visualization services1420, and/or other service types. In at least one embodiment, applications may call (e.g., execute) one or more of services1320to perform processing operations for an application. In at least one embodiment, compute services1416may be leveraged by applications to perform super-computing or other high-performance computing (HPC) tasks. In at least one embodiment, compute service(s)1416may be leveraged to perform parallel processing (e.g., using a parallel computing platform1430) for processing data through one or more of applications and/or one or more tasks of a single application, substantially simultaneously. In at least one embodiment, parallel computing platform1430(e.g., NVIDIA's CUDA) may enable general purpose computing on GPUs (GPGPU) (e.g., GPUs1422). In at least one embodiment, a software layer of parallel computing platform1430may provide access to virtual instruction sets and parallel computational elements of GPUs, for execution of compute kernels. In at least one embodiment, parallel computing platform1430may include memory and, in some embodiments, a memory may be shared between and among multiple containers, and/or between and among different processing tasks within a single container. In at least one embodiment, inter-process communication (IPC) calls may be generated for multiple containers and/or for multiple processes within a container to use same data from a shared segment of memory of parallel computing platform1430(e.g., where multiple different stages of an application or multiple applications are processing same information). In at least one embodiment, rather than making a copy of data and moving data to different locations in memory (e.g., a read/write operation), same data in same location of a memory may be used for any number of processing tasks (e.g., at a same time, at different times, etc.). In at least one embodiment, as data is used to generate new data as a result of processing, this information of a new location of data may be stored and shared between various applications. In at least one embodiment, location of data and a location of updated or modified data may be part of a definition of how a payload is understood within containers.

In at least one embodiment, AI services1418may be leveraged to perform inferencing services for executing machine learning model(s) associated with applications (e.g., tasked with performing one or more processing tasks of an application). In at least one embodiment, AI services1418may leverage AI system1424to execute machine learning model(s) (e.g., neural networks, such as CNNs) for segmentation, reconstruction, object detection, feature detection, classification, and/or other inferencing tasks. In at least one embodiment, applications of deployment pipeline(s)1410may use one or more of output models1316from training system1304and/or other models of applications to perform inference on imaging data. In at least one embodiment, two or more examples of inferencing using application orchestration system1428(e.g., a scheduler) may be available. In at least one embodiment, a first category may include a high priority/low latency path that may achieve higher service level agreements, such as for performing inference on urgent requests during an emergency, or for a radiologist during diagnosis. In at least one embodiment, a second category may include a standard priority path that may be used for requests that may be non-urgent or where analysis may be performed at a later time. In at least one embodiment, application orchestration system1428may distribute resources (e.g., services1320and/or hardware1322) based on priority paths for different inferencing tasks of AI services1418.

In at least one embodiment, shared storage may be mounted to AI services1418within system1400. In at least one embodiment, shared storage may operate as a cache (or other storage device type) and may be used to process inference requests from applications. In at least one embodiment, when an inference request is submitted, a request may be received by a set of API instances of deployment system1306, and one or more instances may be selected (e.g., for best fit, for load balancing, etc.) to process a request. In at least one embodiment, to process a request, a request may be entered into a database, a machine learning model may be located from model registry1324if not already in a cache, a validation step may ensure appropriate machine learning model is loaded into a cache (e.g., shared storage), and/or a copy of a model may be saved to a cache. In at least one embodiment, a scheduler (e.g., of pipeline manager1412) may be used to launch an application that is referenced in a request if an application is not already running or if there are not enough instances of an application. In at least one embodiment, if an inference server is not already launched to execute a model, an inference server may be launched. Any number of inference servers may be launched per model. In at least one embodiment, in a pull model, in which inference servers are clustered, models may be cached whenever load balancing is advantageous. In at least one embodiment, inference servers may be statically loaded in corresponding, distributed servers.

In at least one embodiment, inferencing may be performed using an inference server that runs in a container. In at least one embodiment, an instance of an inference server may be associated with a model (and optionally a plurality of versions of a model). In at least one embodiment, if an instance of an inference server does not exist when a request to perform inference on a model is received, a new instance may be loaded. In at least one embodiment, when starting an inference server, a model may be passed to an inference server such that a same container may be used to serve different models so long as inference server is running as a different instance.

In at least one embodiment, during application execution, an inference request for a given application may be received, and a container (e.g., hosting an instance of an inference server) may be loaded (if not already), and a start procedure may be called. In at least one embodiment, pre-processing logic in a container may load, decode, and/or perform any additional pre-processing on incoming data (e.g., using a CPU(s) and/or GPU(s)). In at least one embodiment, once data is prepared for inference, a container may perform inference as necessary on data. In at least one embodiment, this may include a single inference call on one image (e.g., a hand X-ray), or may require inference on hundreds of images (e.g., a chest CT). In at least one embodiment, an application may summarize results before completing, which may include, without limitation, a single confidence score, pixel level-segmentation, voxel-level segmentation, generating a visualization, or generating text to summarize findings. In at least one embodiment, different models or applications may be assigned different priorities. For example, some models may have a real-time (TAT<1 min) priority while others may have lower priority (e.g., TAT<10 min). In at least one embodiment, model execution times may be measured from requesting institution or entity and may include partner network traversal time, as well as execution on an inference service.

In at least one embodiment, transfer of requests between services1320and inference applications may be hidden behind a software development kit (SDK), and robust transport may be provide through a queue. In at least one embodiment, a request will be placed in a queue via an API for an individual application/tenant ID combination and an SDK will pull a request from a queue and give a request to an application. In at least one embodiment, a name of a queue may be provided in an environment from where an SDK will pick it up. In at least one embodiment, asynchronous communication through a queue may be useful as it may allow any instance of an application to pick up work as it becomes available. Results may be transferred back through a queue, to ensure no data is lost. In at least one embodiment, queues may also provide an ability to segment work, as highest priority work may go to a queue with most instances of an application connected to it, while lowest priority work may go to a queue with a single instance connected to it that processes tasks in an order received. In at least one embodiment, an application may run on a GPU-accelerated instance generated in cloud1426, and an inference service may perform inferencing on a GPU.

In at least one embodiment, visualization services1420may be leveraged to generate visualizations for viewing outputs of applications and/or deployment pipeline(s)1410. In at least one embodiment, GPUs1422may be leveraged by visualization services1420to generate visualizations. In at least one embodiment, rendering effects, such as ray-tracing, may be implemented by visualization services1420to generate higher quality visualizations. In at least one embodiment, visualizations may include, without limitation, 2D image renderings, 3D volume renderings, 3D volume reconstruction, 2D tomographic slices, virtual reality displays, augmented reality displays, etc. In at least one embodiment, virtualized environments may be used to generate a virtual interactive display or environment (e.g., a virtual environment) for interaction by users of a system (e.g., doctors, nurses, radiologists, etc.). In at least one embodiment, visualization services1420may include an internal visualizer, cinematics, and/or other rendering or image processing capabilities or functionality (e.g., ray tracing, rasterization, internal optics, etc.).

In at least one embodiment, hardware1322may include GPUs1422, AI system1424, cloud1426, and/or any other hardware used for executing training system1304and/or deployment system1306. In at least one embodiment, GPUs1422(e.g., NVIDIA's TESLA and/or QUADRO GPUs) may include any number of GPUs that may be used for executing processing tasks of compute services1416, AI services1418, visualization services1420, other services, and/or any of features or functionality of software1318. For example, with respect to AI services1418, GPUs1422may be used to perform pre-processing on imaging data (or other data types used by machine learning models), post-processing on outputs of machine learning models, and/or to perform inferencing (e.g., to execute machine learning models). In at least one embodiment, cloud1426, AI system1424, and/or other components of system1400may use GPUs1422. In at least one embodiment, cloud1426may include a GPU-optimized platform for deep learning tasks. In at least one embodiment, AI system1424may use GPUs, and cloud1426—or at least a portion tasked with deep learning or inferencing—may be executed using one or more AI systems1424. As such, although hardware1322is illustrated as discrete components, this is not intended to be limiting, and any components of hardware1322may be combined with, or leveraged by, any other components of hardware1322.

In at least one embodiment, AI system1424may include a purpose-built computing system (e.g., a super-computer or an HPC) configured for inferencing, deep learning, machine learning, and/or other artificial intelligence tasks. In at least one embodiment, AI system1424(e.g., NVIDIA's DGX) may include GPU-optimized software (e.g., a software stack) that may be executed using a plurality of GPUs1422, in addition to CPUs, RAM, storage, and/or other components, features, or functionality. In at least one embodiment, one or more AI systems1424may be implemented in cloud1426(e.g., in a data center) for performing some or all of AI-based processing tasks of system1400.

In at least one embodiment, cloud1426may include a GPU-accelerated infrastructure (e.g., NVIDIA's NGC) that may provide a GPU-optimized platform for executing processing tasks of system1400. In at least one embodiment, cloud1426may include an AI system(s)1424for performing one or more of AI-based tasks of system1400(e.g., as a hardware abstraction and scaling platform). In at least one embodiment, cloud1426may integrate with application orchestration system1428leveraging multiple GPUs to enable seamless scaling and load balancing between and among applications and services1320. In at least one embodiment, cloud1426may tasked with executing at least some of services1320of system1400, including compute services1416, AI services1418, and/or visualization services1420, as described herein. In at least one embodiment, cloud1426may perform small and large batch inference (e.g., executing NVIDIA's TENSOR RT), provide an accelerated parallel computing API and platform1430(e.g., NVIDIA's CUDA), execute application orchestration system1428(e.g., KUBERNETES), provide a graphics rendering API and platform (e.g., for ray-tracing, 2D graphics, 3D graphics, and/or other rendering techniques to produce higher quality cinematics), and/or may provide other functionality for system1400.

FIG.15Aillustrates a data flow diagram for a process1500to train, retrain, or update a machine learning model, in accordance with at least one embodiment. In at least one embodiment, process1500may be executed using, as a non-limiting example, system1500ofFIG.15. In at least one embodiment, process1500may leverage services and/or hardware as described herein. In at least one embodiment, refined models1512generated by process1500may be executed by a deployment system for one or more containerized applications in deployment pipelines.

In at least one embodiment, model training1514may include retraining or updating an initial model1504(e.g., a pre-trained model) using new training data (e.g., new input data, such as customer dataset1506, and/or new ground truth data associated with input data). In at least one embodiment, to retrain, or update, initial model1504, output or loss layer(s) of initial model1504may be reset, or deleted, and/or replaced with an updated or new output or loss layer(s). In at least one embodiment, initial model1504may have previously fine-tuned parameters (e.g., weights and/or biases) that remain from prior training, so training or retraining1514may not take as long or require as much processing as training a model from scratch. In at least one embodiment, during model training1514, by having reset or replaced output or loss layer(s) of initial model1504, parameters may be updated and re-tuned for a new data set based on loss calculations associated with accuracy of output or loss layer(s) at generating predictions on new, customer dataset1506.

In at least one embodiment, pre-trained models1506may be stored in a data store, or registry. In at least one embodiment, pre-trained models1506may have been trained, at least in part, at one or more facilities other than a facility executing process1500. In at least one embodiment, to protect privacy and rights of patients, subjects, or clients of different facilities, pre-trained models1506may have been trained, on-premise, using customer or patient data generated on-premise. In at least one embodiment, pre-trained models1306may be trained using a cloud and/or other hardware, but confidential, privacy protected patient data may not be transferred to, used by, or accessible to any components of a cloud (or other off premise hardware). In at least one embodiment, where a pre-trained model1506is trained at using patient data from more than one facility, pre-trained model1506may have been individually trained for each facility prior to being trained on patient or customer data from another facility. In at least one embodiment, such as where a customer or patient data has been released of privacy concerns (e.g., by waiver, for experimental use, etc.), or where a customer or patient data is included in a public data set, a customer or patient data from any number of facilities may be used to train pre-trained model1506on-premise and/or off premise, such as in a datacenter or other cloud computing infrastructure.

In at least one embodiment, when selecting applications for use in deployment pipelines, a user may also select machine learning models to be used for specific applications. In at least one embodiment, a user may not have a model for use, so a user may select a pre-trained model to use with an application. In at least one embodiment, pre-trained model may not be optimized for generating accurate results on customer dataset1506of a facility of a user (e.g., based on patient diversity, demographics, types of medical imaging devices used, etc.). In at least one embodiment, prior to deploying a pre-trained model into a deployment pipeline for use with an application(s), pre-trained model may be updated, retrained, and/or fine-tuned for use at a respective facility.

In at least one embodiment, a user may select pre-trained model that is to be updated, retrained, and/or fine-tuned, and this pre-trained model may be referred to as initial model1504for a training system within process1500. In at least one embodiment, a customer dataset1506(e.g., imaging data, genomics data, sequencing data, or other data types generated by devices at a facility) may be used to perform model training (which may include, without limitation, transfer learning) on initial model1504to generate refined model1512. In at least one embodiment, ground truth data corresponding to customer dataset1506may be generated by training system1304. In at least one embodiment, ground truth data may be generated, at least in part, by clinicians, scientists, doctors, practitioners, at a facility.

In at least one embodiment, AI-assisted annotation may be used in some examples to generate ground truth data. In at least one embodiment, AI-assisted annotation (e.g., implemented using an AI-assisted annotation SDK) may leverage machine learning models (e.g., neural networks) to generate suggested or predicted ground truth data for a customer dataset. In at least one embodiment, a user may use annotation tools within a user interface (a graphical user interface (GUI)) on a computing device.

In at least one embodiment, user1510may interact with a GUI via computing device1508to edit or fine-tune (auto)annotations. In at least one embodiment, a polygon editing feature may be used to move vertices of a polygon to more accurate or fine-tuned locations.

In at least one embodiment, once customer dataset1506has associated ground truth data, ground truth data (e.g., from AI-assisted annotation, manual labeling, etc.) may be used by during model training to generate refined model1512. In at least one embodiment, customer dataset1506may be applied to initial model1504any number of times, and ground truth data may be used to update parameters of initial model1504until an acceptable level of accuracy is attained for refined model1512. In at least one embodiment, once refined model1512is generated, refined model1512may be deployed within one or more deployment pipelines at a facility for performing one or more processing tasks with respect to medical imaging data.

In at least one embodiment, refined model1512may be uploaded to pre-trained models in a model registry to be selected by another facility. In at least one embodiment, his process may be completed at any number of facilities such that refined model1512may be further refined on new datasets any number of times to generate a more universal model.

FIG.15Bis an example illustration of a client-server architecture1532to enhance annotation tools with pre-trained annotation models, in accordance with at least one embodiment. In at least one embodiment, AI-assisted annotation tools1536may be instantiated based on a client-server architecture1532. In at least one embodiment, annotation tools1536in imaging applications may aid radiologists, for example, identify organs and abnormalities. In at least one embodiment, imaging applications may include software tools that help user1510to identify, as a non-limiting example, a few extreme points on a particular organ of interest in raw images1534(e.g., in a 3D MRI or CT scan) and receive auto-annotated results for all 2D slices of a particular organ. In at least one embodiment, results may be stored in a data store as training data1538and used as (for example and without limitation) ground truth data for training. In at least one embodiment, when computing device1508sends extreme points for AI-assisted annotation, a deep learning model, for example, may receive this data as input and return inference results of a segmented organ or abnormality. In at least one embodiment, pre-instantiated annotation tools, such as AI-Assisted Annotation Tool1536B inFIG.15B, may be enhanced by making API calls (e.g., API Call1544) to a server, such as an Annotation Assistant Server1540that may include a set of pre-trained models1542stored in an annotation model registry, for example. In at least one embodiment, an annotation model registry may store pre-trained models1542(e.g., machine learning models, such as deep learning models) that are pre-trained to perform AI-assisted annotation on a particular organ or abnormality. These models may be further updated by using training pipelines. In at least one embodiment, pre-installed annotation tools may be improved over time as new labeled data is added.

At least one embodiment of the disclosure can be described in view of the following clauses:1. A computer-implemented method, comprising:hosting an emulation software process running in a processing unit of a virtual environment embedded system, the emulation software process controlling communication of a device;deploying an alternate version of the emulation software process into the processing unit;migrating context information from the running emulation software process to the alternate emulation software process;building, based on the migrated context information, one or more context maps in the alternate emulation software process; andtransferring, after the one or more context maps have been built, control of the communication from the emulation software process to the alternate emulation software process.2. The computer-implemented method of claim1, further comprising:initiating the transferring of control of the communication from the emulation software process to the alternate emulation software process upon relinquishment of control by the emulation software process.3. The computer-implemented method of claim1, further comprising:initiating the transfer of control of the communication from the emulation software process to the alternate emulation software process upon instructions from the emulation software process.4. The computer-implemented method of claim1, further comprising:indicating, using the alternate emulation software process, suspension of the running emulation software process upon completion of the context map.5. The computer-implemented method of claim1, wherein the context information includes one or more backend connections and one or more I/O context.6. The computer-implemented method of claim1, wherein the processing unit is a DPU or a SmartNIC.7. The computer-implemented method of claim1, wherein the emulation software process communicates with one or more of a block device, a file system device, a network device, a crypto device, a GPU device, or a PCI emulated device.8. The computer-implemented method of claim1, further comprising:preparing the one or more context maps in an inactive state.9. The computer-implemented method of claim1, wherein the context information includes queue data.10. The computer-implemented method of claim1, wherein the context information includes device context of one or more devices.11. The computer-implemented method of claim1, further comprising:determining, using the alternate emulation software process, one or more algorithms and at least one resource to use before control is transferred.12. A system, comprising:one or more processors; andmemory including instructions that, when executed by the one or more processors, cause the system to:query context information from a running emulation software process in a processing unit of a virtual environment embedded system;migrate the queried context information to an alternate emulation software process in the processing unit of the virtual environment embedded system;build, based on the migrated context information, one or more context maps in the alternate emulation software process; andtransfer, from the emulation software process to the alternate emulation software process, control of communications with an device, the communications directed by the migrated context information.13. The computer-implemented method of claim12, further comprising:support, using the context maps, acceleration engines for the context information.14. The computer-implemented method of claim12, further comprising:initiate transfer of communication control upon relinquishment of the control by the emulation software process.15. The computer-implemented method of claim12, further comprising:initiate transfer of communication control upon receipt of instructions from the emulation software process.16. A processor, comprising:one or more circuits to:query context information from a running emulation software process in a processing unit of a virtual environment embedded system;migrate the queried context information to an alternate emulation software process in the processing unit of the virtual environment embedded system;build, based on the migrated context information, one or more context maps in the alternate emulation software process; andtransfer, from the emulation software process to the alternate emulation software process, control of communications by a device, the communications directed by the migrated context information.17. The processor of claim16, wherein the context information includes at least one of doorbells, MSI-X resources, PCIe memory mapped registers, IOBAR registers, transient queue, and I/O context information.18. The processor of claim16, wherein the emulation software process and the alternate emulation software process are configured to control communications by the device.19. The processor of claim16, wherein the queried context information is migrated in a stateless manner.20. The processor of claim16, wherein the circuits are further to control, using the alternate emulation software process, communications by one or more additional devices.

In at least one embodiment, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip. In at least one embodiment, multi-chip modules may be used with increased connectivity which simulate on-chip operation, and make substantial improvements over utilizing a conventional central processing unit (“CPU”) and bus implementation. In at least one embodiment, various modules may also be situated separately or in various combinations of semiconductor platforms per desires of user.

In at least one embodiment, referring back toFIG.13, computer programs in form of machine-readable executable code or computer control logic algorithms are stored in main memory1304and/or secondary storage. Computer programs, if executed by one or more processors, enable system1300to perform various functions in accordance with at least one embodiment. In at least one embodiment, memory1304, storage, and/or any other storage are possible examples of computer-readable media. In at least one embodiment, secondary storage may refer to any suitable storage device or system such as a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (“DVD”) drive, recording device, universal serial bus (“USB”) flash memory, etc. In at least one embodiment, architecture and/or functionality of various previous figures are implemented in context of CPU1302, parallel processing system1312, an integrated circuit capable of at least a portion of capabilities of both CPU1302, parallel processing system1312, a chipset (e.g., a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.), and/or any suitable combination of integrated circuit(s).

In at least one embodiment, architecture and/or functionality of various previous figures are implemented in context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and more. In at least one embodiment, computer system1300may take form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (“PDA”), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device, a television, workstation, game consoles, embedded system, and/or any other type of logic.

In at least one embodiment, parallel processing system1312includes, without limitation, a plurality of parallel processing units (“PPUs”)1314and associated memories1316. In at least one embodiment, PPUs1314are connected to a host processor or other peripheral devices via an interconnect1318and a switch1320or multiplexer. In at least one embodiment, parallel processing system1312distributes computational tasks across PPUs1314which can be parallelizable—for example, as part of distribution of computational tasks across multiple graphics processing unit (“GPU”) thread blocks. In at least one embodiment, memory is shared and accessible (e.g., for read and/or write access) across some or all of PPUs1314, although such shared memory may incur performance penalties relative to use of local memory and registers resident to a PPU1314. In at least one embodiment, operation of PPUs1314is synchronized through use of a command such as _syncthreads( ), wherein all threads in a block (e.g., executed across multiple PPUs1314) to reach a certain point of execution of code before proceeding.

In at least one embodiment, one or more techniques described herein utilize a oneAPI programming model. In at least one embodiment, a oneAPI programming model refers to a programming model for interacting with various compute accelerator architectures. In at least one embodiment, oneAPI refers to an application programming interface (API) designed to interact with various compute accelerator architectures. In at least one embodiment, a oneAPI programming model utilizes a DPC++ programming language. In at least one embodiment, a DPC++ programming language refers to a high-level language for data parallel programming productivity. In at least one embodiment, a DPC++ programming language is based at least in part on C and/or C++ programming languages. In at least one embodiment, a oneAPI programming model is a programming model such as those developed by Intel Corporation of Santa Clara, CA.

In at least one embodiment, oneAPI and/or oneAPI programming model is utilized to interact with various accelerator, GPU, processor, and/or variations thereof, architectures. In at least one embodiment, oneAPI includes a set of libraries that implement various functionalities. In at least one embodiment, oneAPI includes at least a oneAPI DPC++ library, a oneAPI math kernel library, a oneAPI data analytics library, a oneAPI deep neural network library, a oneAPI collective communications library, a oneAPI threading building blocks library, a oneAPI video processing library, and/or variations thereof.

In at least one embodiment, a oneAPI DPC++ library, also referred to as oneDPL, is a library that implements algorithms and functions to accelerate DPC++ kernel programming. In at least one embodiment, oneDPL implements one or more standard template library (STL) functions. In at least one embodiment, oneDPL implements one or more parallel STL functions. In at least one embodiment, oneDPL provides a set of library classes and functions such as parallel algorithms, iterators, function object classes, range-based API, and/or variations thereof. In at least one embodiment, oneDPL implements one or more classes and/or functions of a C++ standard library. In at least one embodiment, oneDPL implements one or more random number generator functions.

In at least one embodiment, a oneAPI math kernel library, also referred to as oneMKL, is a library that implements various optimized and parallelized routines for various mathematical functions and/or operations. In at least one embodiment, oneMKL implements one or more basic linear algebra subprograms (BLAS) and/or linear algebra package (LAPACK) dense linear algebra routines. In at least one embodiment, oneMKL implements one or more sparse BLAS linear algebra routines. In at least one embodiment, oneMKL implements one or more random number generators (RNGs). In at least one embodiment, oneMKL implements one or more vector mathematics (VM) routines for mathematical operations on vectors. In at least one embodiment, oneMKL implements one or more Fast Fourier Transform (FFT) functions.

In at least one embodiment, a oneAPI data analytics library, also referred to as oneDAL, is a library that implements various data analysis applications and distributed computations. In at least one embodiment, oneDAL implements various algorithms for preprocessing, transformation, analysis, modeling, validation, and decision making for data analytics, in batch, online, and distributed processing modes of computation. In at least one embodiment, oneDAL implements various C++ and/or Java APIs and various connectors to one or more data sources. In at least one embodiment, oneDAL implements DPC++ API extensions to a traditional C++ interface and enables GPU usage for various algorithms.

In at least one embodiment, a oneAPI deep neural network library, also referred to as oneDNN, is a library that implements various deep learning functions. In at least one embodiment, oneDNN implements various neural network, machine learning, and deep learning functions, algorithms, and/or variations thereof.

In at least one embodiment, a oneAPI collective communications library, also referred to as oneCCL, is a library that implements various applications for deep learning and machine learning workloads. In at least one embodiment, oneCCL is built upon lower-level communication middleware, such as message passing interface (MPI) and libfabrics. In at least one embodiment, oneCCL enables a set of deep learning specific optimizations, such as prioritization, persistent operations, out of order executions, and/or variations thereof. In at least one embodiment, oneCCL implements various CPU and GPU functions.

In at least one embodiment, a oneAPI threading building blocks library, also referred to as oneTBB, is a library that implements various parallelized processes for various applications. In at least one embodiment, oneTBB is utilized for task-based, shared parallel programming on a host. In at least one embodiment, oneTBB implements generic parallel algorithms. In at least one embodiment, oneTBB implements concurrent containers. In at least one embodiment, oneTBB implements a scalable memory allocator. In at least one embodiment, oneTBB implements a work-stealing task scheduler. In at least one embodiment, oneTBB implements low-level synchronization primitives. In at least one embodiment, oneTBB is compiler-independent and usable on various processors, such as GPUs, PPUs, CPUs, and/or variations thereof.

In at least one embodiment, a oneAPI video processing library, also referred to as oneVPL, is a library that is utilized for accelerating video processing in one or more applications. In at least one embodiment, oneVPL implements various video decoding, encoding, and processing functions. In at least one embodiment, oneVPL implements various functions for media pipelines on CPUs, GPUs, and other accelerators. In at least one embodiment, one VPL implements device discovery and selection in media centric and video analytics workloads. In at least one embodiment, oneVPL implements API primitives for zero-copy buffer sharing.

In at least one embodiment, a oneAPI programming model utilizes a DPC++ programming language. In at least one embodiment, a DPC++ programming language is a programming language that includes, without limitation, functionally similar versions of CUDA mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, a DPC++ programming language may include a subset of functionality of a CUDA programming language. In at least one embodiment, one or more CUDA programming model operations are performed using a oneAPI programming model using a DPC++ programming language.

In at least one embodiment, any application programming interface (API) described herein is compiled into one or more instructions, operations, or any other signal by a compiler, interpreter, or other software tool. In at least one embodiment, compilation comprises generating one or more machine-executable instructions, operations, or other signals from source code. In at least one embodiment, an API compiled into one or more instructions, operations, or other signals, when performed, causes one or more processors such as graphics processors2800, graphics cores1800, parallel processor2000, processor2300, processor core2300, or any other logic circuit further described herein to perform one or more computing operations.

It should be noted that, while example embodiments described herein may relate to a CUDA programming model, techniques described herein can be utilized with any suitable programming model, such HIP, oneAPI, and/or variations thereof.

In at least one embodiment, an arithmetic logic unit is a set of combinational logic circuitry that takes one or more inputs to produce a result. In at least one embodiment, an arithmetic logic unit is used by a processor to implement mathematical operation such as addition, subtraction, or multiplication. In at least one embodiment, an arithmetic logic unit is used to implement logical operations such as logical AND/OR or XOR. In at least one embodiment, an arithmetic logic unit is stateless, and made from physical switching components such as semiconductor transistors arranged to form logical gates. In at least one embodiment, an arithmetic logic unit may operate internally as a stateful logic circuit with an associated clock. In at least one embodiment, an arithmetic logic unit may be constructed as an asynchronous logic circuit with an internal state not maintained in an associated register set. In at least one embodiment, an arithmetic logic unit is used by a processor to combine operands stored in one or more registers of the processor and produce an output that can be stored by the processor in another register or a memory location.

In at least one embodiment, as a result of processing an instruction retrieved by the processor, the processor presents one or more inputs or operands to an arithmetic logic unit, causing the arithmetic logic unit to produce a result based at least in part on an instruction code provided to inputs of the arithmetic logic unit. In at least one embodiment, the instruction codes provided by the processor to the ALU are based at least in part on the instruction executed by the processor. In at least one embodiment combinational logic in the ALU processes the inputs and produces an output which is placed on a bus within the processor. In at least one embodiment, the processor selects a destination register, memory location, output device, or output storage location on the output bus so that clocking the processor causes the results produced by the ALU to be sent to the desired location.

In the scope of this application, the term arithmetic logic unit, or ALU, is used to refer to any computational logic circuit that processes operands to produce a result. For example, in the present document, the term ALU can refer to a floating point unit, a DSP, a tensor core, a shader core, a coprocessor, or a CPU.

Although descriptions herein set forth example implementations of described techniques, other architectures may be used to implement described functionality, and are intended to be within scope of this disclosure. Furthermore, although specific distributions of responsibilities may be defined above for purposes of description, various functions and responsibilities might be distributed and divided in different ways, depending on circumstances.