Digital high speed acquisition system for phase locked loops

Disclosed is a signal generator that includes a memory to store tuning voltage values and offset voltage values. An adder/subtractor circuit is coupled to the memory to produce a sum and a difference of the tuning and offset voltages. A comparator circuit is coupled to the adder/subtractor circuit to receive a digitized voltage controlled oscillator tuning voltage and to compare the digitized voltage controlled oscillator tuning voltage to the sum and difference of the tuning and offset voltages to produce a window bounded by the sum and difference of the tuning and offset voltages. The comparator circuit is further configured to generate control signals. A steering current circuit is coupled to the comparator circuit to receive the control signals from the comparator circuit and to control a steering current based on the control signals.

BACKGROUND

The present disclosure is directed generally to a frequency synthesizer. A high speed acquisition system for phase locked loops to reduce component count and improve performance over a wide temperature range is disclosed in commonly owned U.S. Pat. No. 10,141,943, which is herein incorporated by reference in its entirety. The disclosed phase locked loop (PLL) has a low value of loop bandwidth and consequently low phase noise at large offsets from the carrier and may be brought into lock in a much shorter time than that normally set by the loop bandwidth. The time taken for a PLL to change frequency is inversely proportional to its loop bandwidth. Although wide loop bandwidth degrades the signal phase noise at large frequency offsets from the carrier, the digital high speed acquisition system for phase locked loops provides high speed tuning in low phase noise microwave PLLs as described hereinbelow.

SUMMARY

In one aspect, the present disclosure provides a signal generator. The signal generator comprising a memory to store tuning voltage (Vm) values and offset voltage (Vo) values; an adder circuit coupled to the memory, the adder circuit to produce a sum of a tuning voltage and an offset voltage (Vm+Vo); a subtractor circuit coupled to the memory, the subtractor circuit to produce a difference of the tuning voltage and the offset voltage (Vm−Vo); a comparator circuit coupled to the adder and the subtractor circuits, the comparator circuit configured to receive a digitized voltage controlled oscillator tuning voltage (Vt) and to compare the digitized voltage controlled oscillator (VCO) tuning voltage (Vt) to the sum of the tuning voltage and the offset voltage (Vm+Vo) and the difference of the tuning voltage and the offset voltage (Vm−Vo) and to produce a window bounded by (Vm+Vo) and (Vm−Vo), the comparator circuit further configured to generate control signals; and a steering current circuit coupled to the comparator circuit to receive the control signals from the comparator circuit and to control a steering current based on the control signals.

In another aspect, the present disclosure provides a method of generating a signal. The method comprises receiving, by a processor/logic, a request to output a new frequency; generating, by a phase-lock-loop (PLL) circuit, a new analog tuning voltage corresponding to the new frequency; loading, by the processor/logic into a comparator, a new digital tuning voltage (Vt); loading, by the processor/logic from a memory into an adder/subtractor circuit, a new tuning voltage (Vm) corresponding to the value of the new frequency; loading, by the processor/logic from the memory into the adder/subtractor circuit, a new offset voltage (Vo); computing, by the comparator, logical mathematical decisions based on the new digital tuning voltage (Vt), the new tuning voltage (Vm), and the new offset voltage (Vo); controlling, by a steering current circuit coupled to the comparator, a steering current into or out of the PLL circuit; and generating, by the PLL circuit, a tuning voltage based on the steering current.

In another aspect, the present disclosure provides a signal generator. The signal generator comprising a processor/logic; a memory coupled to the processor/logic, the memory stores digital tuning voltage and offset voltage values; an adder/subtractor circuit coupled to the memory; a comparator coupled to the adder/subtractor circuit; a steering current circuit coupled to the comparator; and a phase-lock-loop (PLL) circuit coupled to the memory and the steering current circuit, the PLL circuit further comprising: a programmable counter; a loop filter comprising a loop filter capacitor, a loop filter coupled to the steering current circuit; a phase comparator/detector circuit; and a voltage controlled oscillator (VCO); wherein the processor/logic is configured to: receive a request to output a new frequency; generate, by a phase-lock-loop (PLL) circuit, a new analog tuning voltage corresponding to the new frequency; load into the comparator a new digital tuning voltage (Vt); load from a memory into an adder/subtractor circuit, a new tuning voltage (Vm) corresponding to the value of the new frequency; load from the memory into the adder/subtractor circuit a new offset voltage (Vo); wherein the comparator is configured to compute logical mathematical decisions based on the new digital tuning voltage (Vt), the new tuning voltage (Vm), and the new offset voltage (Vo); wherein the steering current circuit is configured to control steering current into or out of the PLL circuit; and wherein the PLL circuit is configured to generate a tuning voltage based on the steering current.

DESCRIPTION

FIG. 1illustrates a signal generator100comprising a frequency synthesizer150according to one aspect of the present disclosure. In various aspects, the frequency synthesizer150is a digitally realized high speed acquisition system for a phase locked loop comprising a digitally controlled signal source with a fast switching phase-locked loop circuit122(PLL). The PLL circuit122is configured to rapidly change frequency while minimizing loop bandwidth, jitter, and phase noise at large offsets from a reference oscillator. In one aspect, the signal generator100comprises a voltage controlled oscillator308(VCO). The VCO308receives a tuning voltage112(Vt) characterized across the required tuning range with temperature as a parameter. Tuning voltage data is stored in a fast access, non-volatile memory202(e.g. MRAM). The tuning voltage data stored in the memory202includes frequency tuning codes (also referred to as tuning voltage Vm) and frequency offset codes (also referred to as offset voltage Vo) paged by temperature and PLL codes. A PLL code is a frequency select digital word that is applied to a programmable N frequency divider of the PLL circuit122. Input code commands are used to change the output frequency of the signal generator100. The input codes select digital words stored in the memory202that represent the desired output frequency of the signal generator100. The VCO308may be an HMC732LC4B wideband millimeter microwave integrated circuit (MMIC) VCO with buffer amplifier operable from 6-12 GHz available from Analog Devices.

When the PLL circuit122is operating and a command to change frequency is received (when the loop division ratio is changed) the tuning voltage112(Vt) extant at the VCO308tuning port is compared to the stored (previously characterized) tuning voltage (Vm) value stored in memory202.

This comparison indicates the direction in which the tuning voltage112(Vt) must be “steered” in order to reach the stored value corresponding to the target frequency defined by the input code. Frequency offset codes are applied to an adder104and frequency tuning codes are applied to a subtractor106. The output of the adder104is the tuning voltage112(Vt) plus an offset (VTune+VOffset) and the output of the subtractor106is the tuning voltage112(Vt) minus the offset (VTune−VOffset). These outputs are applied to a comparator circuit306which tunes up or tunes down the tuning voltage112(Vt) or disables the tuning voltage112(Vt) applied to the VCO308tuning port. The output of the VCO308is the desired RF frequency123(fo). The output frequency123(fo) is fed back to an analog-to-digital converter309(ADC), which provides a digital word (Vtune) representing the tuning voltage112(Vt) to the comparator circuit306.

A PLL circuit122loop filter includes an auxiliary charge pump circuit which charges or discharges the primary PLL circuit122timing capacitor depending on the required steering direction.

When the VCO308tuning voltage112(Vt) arrives at a value close to that corresponding to the target frequency defined by the input code the auxiliary charge pump is disabled and the PLL circuit122locks normally.

The signal generator100can be implemented with reduced component count and provides improved performance over a wide temperature range. The signal generator100includes a PLL circuit122having a low value of loop bandwidth and consequently low phase noise at large offset from the carrier that can be brought into lock in a much shorter time that that normally set by the loop bandwidth. Although wide loop bandwidth tends to degrade the signal phase noise at large frequency offsets from the carrier, the signal generator100provides increased tuning speed in a low phase noise microwave PLL circuit122as described in more detail hereinbelow.

The comparator circuit306is coupled to a steering current circuit118and the PLL circuit122. The comparator circuit306compares the digital tuning voltage (Vtune) received from the ADC309to first and second reference threshold voltage values and controls the direction of a steering current into or out of a loop filter capacitor of the PLL circuit122based on the value of the digital word (Vtune) representing the tuning voltage112(Vt). Charging and discharging the loop filter capacitor with the steering current increases the speed at which the PLL circuit122reaches a locked condition after a new output frequency is selected by the input code. The input code may be generated by a user or a machine (e.g., another circuit, processor, logic, etc.) to change the output frequency123(fo) to a new specified output frequency123(fo′). The comparator circuit306may be implemented as a logic circuit and in one aspect, may be implemented as a field programmable gate array (FPGA), for example.

In one aspect, the PLL circuit122may be implemented by a LMX2492 500 MHz to 14 GHz wideband, low noise fractional N PLL with ramp/chirp generation, by Texas Instruments Inc. A processor/logic circuit101may comprise a general purpose digital processor, controller, microcontroller, discrete logic devices, programmable logic array (PGA), field programmable logic array (FPGA) and/or combinations thereof.

In one aspect, during operation, a processor/logic circuit101continuously monitors the PLL circuit122lock detect output and for a request to change the output frequency123(fo). The request may be initiated manually by a user or may be provided by a machine (e.g., another circuit, processor, logic, PGA, FPGA, etc.). When the processor/logic circuit101detects a frequency change request, the processor/logic circuit101loads a new frequency input code into the memory202. The input code is a digital value that is approximately the same value as the digitized form of the tuning voltage112(Vt) applied to the VCO308portion of the PLL circuit122to set the output frequency123(fo) to a specific desired output frequency123(fo).

FIG. 2illustrates a signal generator300comprising a frequency synthesizer according to one aspect of the present disclosure. The signal generator300comprises a memory202coupled to an adder/subtractor circuit302, which is coupled to an offset memory304and a comparator circuit306. The comparator circuit306is coupled to a current steering current circuit118, which is coupled to the PLL circuit122and a PLL control circuit318. The memory202receives a frequency select address204and provides a frequency select digital word102to the PLL control circuit318and provides the tuning voltage (Vm) value stored in the memory202and offset voltage (Vo) value stored in the offset memory304to the adder/subtractor circuit302.

The PLL circuit122comprises a PLL control circuit318, a loop filter320(e.g., an active low pass filter), and a VCO308. In one aspect, the VCO308may be implemented separately with an RFVC1843 5V InGaP MMIC VCO with an integrated frequency divider providing additional fo/2 and fo/4 outputs by RF Micro Devices (RFMD). The VCO308, which may be any form of electronically tuned oscillator, feeds the signal output port123with a signal at some frequency fo. A portion of the output signal123(fo) is fed to a programmable N frequency divider316whose output frequency will be equal to fo/N. The divider output fo/N is fed to a phase/frequency detector314(PFD) together with a reference signal fretwhich may be derived from a reference oscillator310. The output frequency123(fo) of the VCO308is the output of the signal generator300. The reference oscillator310may comprise a crystal reference oscillator that generates a reference frequency (fx). The reference frequency (fx) is applied to a fixed counter312(R divider circuit). A sample of the output frequency123(fo) is applied to the programmable counter316(N divider circuit) via a directional coupler or signal splitter. The output of the programmable counter316is fed to a phase comparator/detector314together with the output of the fixed counter312, which is a reference signal derived from the reference frequency (fx) generated by the crystal reference oscillator310. The value of the loop divisor (N) of the programmable counter316is controlled by the frequency control word102. The phase comparator/detector314output signal121(fref) output in the form of a pulse width modulated waveform at the reference frequency (fref) is fed to the input of the loop filter320via a switch S3, which is electronically activated when a control input is driven low (logic 0), as described hereinbelow.

The switch S3is coupled to the input of an operational amplifier active low pass loop filter320to the VCO tuning port thereby closing the PLL circuit122. The loop filter320comprises an operational amplifier circuit306with a loop filter capacitor C1inserted in the feedback loop. A resistor R3may be provided between the loop filter capacitor C1and the negative input of the amplifier circuit306. A passive low pass filter comprising R4and C2may be coupled between the output of the amplifier circuit306and the VCO308. The low pass filtered output of the loop filter320is the tuning voltage112(Vt), which is applied to the tuning port of the VCO308to produce the output frequency123(fo). Provision is made to switch a steering current120(Isc) into or out of the loop filter capacitor C1via two high speed, low resistance analog switches S1, S2, as described hereinbelow, to increase the switching speed of the PLL circuit122. The PLL circuit122acts to maintain the output frequency fo=N×fret, where fref=fx/R

The ADC309is coupled to the tuning port of the VCO308and the tuning voltage112(Vt) is applied to the input of the ADC309and produces a digital output word representing the value of the tuning voltage112(Vt) extant at the VCO308tuning port.3. A small “offset value” (Vo) is both added to and subtracted from the stored value of the tuning voltage (Vm) corresponding to the target frequency to produce two digital values (Vm+Vo) and (Vm−Vo). A digitized version of the tuning voltage112(Vt) is output by the ADC309. The digitized value of the tuning voltage112(Vt) is compared to (Vm+Vo) and (Vm−Vo) to define a “window” bound by (Vm+Vo) and (Vm−Vo). The controller digital circuit (e.g., FPGA) of the comparator circuit306is configured to compute three logical mathematical decisions as follows:
A=Vt≥(Vm+Vo);
B=Vt≤(Vm−Vo); and
C=(Vm−Vo)≤Vt≤(Vm+Vo).

Three electronic switches S1, S2, and S3are controlled by the logic outputs114,116,117of the comparator circuit306based on these decisions. If A=1, S1is closed and S2and S3are open, and the VCO308tuning voltage112(Vt) ramps down. If B=1, S2is closed and S1and S3are open, and the VCO308tuning voltage112(Vt) ramps up. If C=1, S3is closed and S1and S2are open and at this state, the VCO308tuning voltage112(Vt base d) is within a “window” bounded by (Vm+Vo) and (Vm−Vo). The PLL circuit122will close and will force the VCO308tuning voltage112(Vt) to the exact value to that required to generate a “target frequency.”

The operation of the steering current circuit118is controlled by the logic outputs114,116of the comparator circuit306and are used as conditions for controlling the PLL circuit122. The steering current circuit118comprises two high speed, low resistance electronically activated analog switches S1, S2that are activated when their control input is driven low (logic 0). Only one of the switches S1, S2may be activated at a given time. For example, when the first logic output114is low (logic 0) the first switch S1is activated (closed) and when the first logic output114is high (logic 1) the first switch S1is deactivated (open). Similarly, when the second logic output116is low (logic 0) the second switch S2is activated (closed) and when the second logic output116is high (logic 1) the second switch S2is deactivated (open). A first resistor R1is connected in series with the first switch S1when the first switch S1is activated to switch a steering current120into the loop filter capacitor C1to charge the loop filter capacitor C1. A second resistor R2is connected in series with the second switch S2when the second switch S2is activated to switch a steering current120out of the loop filter capacitor C1to discharge the loop filter capacitor C1. The magnitude of the charging steering current120is set by R1and the magnitude of the discharging steering current120is set by R2. In some aspects, the magnitude of the charging and discharging steering currents120may be the same or different depending on the values of the resistors R1and R2. In one aspect, the analog switches S1and S2may be implemented with a 7SB384 Bus Switch advanced high-speed line switch in ultra-small footprint by ON Semiconductor.

A third high speed low resistance electronically activated analog switch S3is provided to apply the phase comparator/detector signal121(fref) to the PLL circuit122when activated by a logic 0 at logic output117. The comparator circuit306outputs a logic 0 on logic output117when both logic outputs114,116are high (logic 1). A logic 0 on logic output117activates (closes) the third switch S3to apply the phase comparator/detector signal121(fref) to the input of the loop filter320. It will be appreciated that when both logic outputs114,116are high (logic 1) both switches S1and S2are deactivated (open) and at this state, the VCO308tuning voltage112(Vt) is within the “window” bounded by (Vm+Vo) and (Vm− Vo). When both the first and second switches S1, S2are deactivated (open), the switches S1and S2decouple the steering current120from the loop filter capacitor C1such that no steering current120flows into or out of the loop filter capacitor C1. The third switch S3, on the other hand, is activated (closed) to couple the phase comparator/detector signal121(fref) to the input of the loop filter320.

TABLE 1 is a truth table summarizing the operation of the window comparator110and the steering current circuit118.

Under steady state conditions the PLL circuit122will be locked and the output frequency123(fo) is expressed as:

fo=N×fxR=N×frefEq.⁢1
where N is the divisor of the programmable counter316, as controlled by the frequency control word102, and R is the divisor of the fixed counter312.

The PLL circuit122VCO308is characterized over the required operating frequency range over temperature. A table of frequency versus tuning voltage (Vm) is created in the electronic digital memory202, which may be a random access memory (RAM), an in one aspect may be a magneto-resistive random-access memory (MRAM).

During operation, when the PLL circuit122is commanded to a new frequency, the following process will be executed:

1. The PLL circuit122N programmable counter316is programmed to the new “target frequency.”

3. A small “offset value” (Vo) is both added to and subtracted from the stored value of tuning voltage Vmcorresponding to the target frequency to produce two digital values (Vm+Vo) and (Vm−Vo).

4. The digital value output by the ADC (Vt) is compared to (Vm+Vo) and (Vm−Vo).

5. Three mathematical decisions are made in the controller FPGA of the comparator circuit306: logically A=Vt≥(Vm+Vo), B=Vt≤(Vm−Vo) and C=(Vm−Vo)≤Vt≤(Vm+Vo).

7. If C=1 S3is closed, S1and S2are open; this state indicates that the VCO308tuning voltage112(Vt) is within the “window” bounded by (Vm+Vo) and (Vm−Vo). The PLL circuit122will close and will force the VCO308tuning voltage112(Vt) to the exact value that is required to generate the “target frequency.”

FIG. 3is a logic flow diagram400for operating the signal generator comprising a frequency synthesizer described inFIGS. 1 and 2according to one aspect of the present disclosure. The logic flow diagram400will be described in combination with the hardware circuits described inFIGS. 1 and 2. Accordingly, with reference now toFIGS. 1-3, the processor/logic circuit101monitors402the status of the PLL circuit122lock detect. When the processor/logic circuit101determines404that the PLL circuit122is locked406, the processor/logic circuit101continues to monitor402the status of the PLL circuit122lock detect.

When the processor/logic circuit101determines404that the PLL circuit122is not locked, the processor/logic circuit101monitors408the select input and determines410if a change frequency is requested. If not, the processor/logic circuit101registers412a fault. If a change frequency is requested, the processor/logic circuit101loads414a new value to the programmable N frequency divider316. The processor/logic circuit101loads416a new tuning voltage Vmfrom the memory304and offset voltage Vofrom the offset memory304into the adder/subtractor circuit302to determine the (Vm+Vo) and (Vm−Vo) values. The comparator circuit306compares418the tuning voltage Vtto (Vm+Vo) and to (Vm−Vo) determines420whether Vtis high and determines422whether Vtis low.

If Vtis neither high nor low, then Vtis within the “window” bounded by (Vm+Vo) and (Vm−Vo), the comparator circuit306opens424switches S1and S2and closes426switch S3as shown inFIG. 4and continues to monitor402the PLL circuit122lock detect until the PLL circuit122lock detect indicates that the PLL circuit122is unlocked.

If Vtis determined420to be high, the processor/logic circuit101opens428switch S3and closes switch S1, as shown inFIG. 5, to enable current to flow into432C1and ramps down434the tuning voltage Vt. The processor/logic circuit101continues to compare418the tuning voltage Vtto (Vm+Vo) and to (Vm−Vo).

If Vtis determined422to be low, the processor/logic circuit101opens428switch S3and closes switch S2, as shown inFIG. 6, to enable current to flow out of440C1and ramps up442the tuning voltage Vt. The processor/logic circuit101continues to compare418the tuning voltage Vtto (Vm+Vo) and to (Vm−Vo).

FIGS. 4-6illustrate the operation of the steering current circuit118based on the comparison of the actual tuning voltage112(Vt) and the desired tuning voltage (Vm) stored in the memory202plus or minus the offset voltage (Vm+Vo) and (Vm−Vo) stored in the offset memory304. An oscillator310feeds a reference signal Foutto the frequency reference input (Refin) to the PLL circuit122. The RF input of the PLL circuit122(RFin) receives the output frequency123(fo) of the VCO308. The PLL circuit122provides the output signal121(fref) output in the form of a pulse width modulated waveform at the reference frequency (fref) is fed to the input of the loop filter320via the switch S3. The steering current circuit118charges or discharges capacitor C1of the loop filter to steer up or steer down the actual tuning voltage (Vt).

FIG. 4illustrates the signal generator300when the actual tuning voltage112(Vt) is within the “window” bounded by (Vm+Vo) and (Vm−Vo). In this state, the comparator circuit306opens424switches S1and S2and closes426switch S3as shown in and continues to monitor402the PLL circuit122lock detect until the PLL circuit122lock detect indicates that the PLL circuit122is unlocked.

FIG. 5illustrates the signal generator300when the actual tuning voltage (Vt) is high and the processor/logic circuit101opens switch S3and closes switch S1to enable current to flow into C1and ramps down the actual tuning voltage (Vt).

FIG. 6illustrates the signal generator300when the actual tuning voltage (Vt) is low and the processor/logic circuit101opens switch S3and closes switch S2to enable current to flow out of C1and ramps up the actual tuning voltage (Vt).

As used throughout this disclosure and in particular with reference toFIGS. 1-3, a processor/logic circuit101for controlling the signal generator100,300may comprise one or more processor circuits or processing units, one or more memory circuits and/or storage circuit component(s) and one or more input/output (I/O) circuit devices. Additionally, the processor/logic circuit101comprises a bus that allows the various circuit components and devices to communicate with one another. The bus represents one or more of any of several types of bus structures, including a memory bus or memory controller using any of a variety of bus architectures. The bus may comprise wired and/or wireless buses.

The processor/logic circuit101may be responsible for executing various software programs such as system programs, applications programs, and/or modules to provide computing and processing operations. The processor/logic101may be responsible for performing various data communications operations transmitting and receiving data information over one or more wired or wireless communications channels. The processor/logic circuit101may include any suitable processor architecture and/or any suitable number of processors in accordance with this disclosure. In one aspect, the processor/logic circuit101may be implemented using a single integrated processor.

The processor/logic circuit101may be implemented as a host central processing unit (CPU) using any suitable processor circuit or logic device (circuit), such as a as a general purpose processor and/or a state machine. The processor/logic circuit101also may be implemented as a chip multiprocessor (CMP), dedicated processor, embedded processor, media processor, input/output (I/O) processor, co-processor, microprocessor, controller, microcontroller, application specific integrated circuit (ASIC), field programmable gate array (FPGA), programmable logic device (PLD), or other processing device in accordance with the described embodiments.

In various aspects, the processor/logic may be implemented as a microcontroller comprising one or more processors (e.g., microprocessor, microcontroller) coupled to at least one memory202. The memory202stores machine executable instructions that when executed by the processor/logic circuit101, cause the processor/logic circuit101to execute machine instructions to implement various processes described herein. The processor/logic circuit101may be any one of a number of single or multi-core processors known in the art. The memory202may comprise volatile and non-volatile storage media. The processor/logic circuit101may include an instruction processing unit and an arithmetic unit. The instruction processing unit may be configured to receive instructions from the memory202of this disclosure.

The processor/logic circuit101may be implemented using combinational logic circuits. The combinational logic circuits can be configured to implement various processes described herein. The processor/logic circuit101may comprise a finite state machine comprising a combinational logic circuit configured to receive data, process the data, and provide an output of the signal generator100,200,300.

The processor/logic circuit101may comprise a sequential logic circuit configured to control aspects of the signal generator100,200,300. The sequential logic circuit or the combinational logic circuit can be configured to implement various processes described herein. The sequential logic circuit may comprise a finite state machine. The sequential logic circuit may comprise a combinational logic circuit, at least one memory circuit, and a clock, for example. The at least one memory circuit can store a current state of the finite state machine. In certain instances, the sequential logic circuit may be synchronous or asynchronous. The combinational logic circuit is configured to receive data associated with the surgical instrument or tool from an input, process the data, and provide an output of the signal generator100,200,300. In other aspects, the circuit may comprise a combination of a processor and a finite state machine to implement various processes herein. In other aspects, the finite state machine may comprise a combination of a combinational logic circuit and a sequential logic circuit.

As shown, the processor/logic circuit101may be coupled to the memory202and/or storage component(s) through a memory bus. The memory bus may comprise any suitable interface and/or bus architecture for allowing the processor/logic circuit101to access the memory202and/or storage component(s). Although the memory202and/or storage component(s) may be shown as being separate from the processor/logic circuit101for purposes of illustration, it is worthy to note that in various aspects some portion or the entire memory202and/or storage component(s) may be included on the same integrated circuit as the processor/logic circuit101. Alternatively, some portion or the entire memory202and/or storage component(s) may be disposed on an integrated circuit or other medium (e.g., hard disk drive) external to the integrated circuit of the processor/logic circuit101.

The memory202and/or storage component(s) represent one or more computer-readable media. The memory202and/or storage component(s) may be implemented using any computer-readable media capable of storing data such as volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. The memory202and/or storage component(s) may comprise volatile media (e.g., random access memory (RAM)) and/or nonvolatile media (e.g., read only memory (ROM), Flash memory, optical disks, magnetic disks and the like). The memory202and/or storage component(s) may comprise fixed media (e.g., RAM, ROM, a fixed hard drive, etc.) as well as removable media (e.g., a Flash memory drive, a removable hard drive, an optical disk, etc.). Examples of computer-readable storage media may include, without limitation, RAM, dynamic RAM (DRAM), Double-Data-Rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory (e.g., NOR or NAND flash memory), content addressable memory (CAM), polymer memory (e.g., ferroelectric polymer memory), phase-change memory, ovonic memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic or optical cards, or any other type of media suitable for storing information.

While various details have been set forth in the foregoing description, it will be appreciated that the various aspects of the techniques for operating a frequency synthesizer may be practiced without these specific details. One skilled in the art will recognize that the herein described components (e.g., operations), devices, objects, and the discussion accompanying them are used as examples for the sake of conceptual clarity and that various configuration modifications are contemplated. Consequently, as used herein, the specific exemplars set forth and the accompanying discussion are intended to be representative of their more general classes. In general, use of any specific exemplar is intended to be representative of its class, and the non-inclusion of specific components (e.g., operations), devices, and objects should not be taken limiting.

For conciseness and clarity of disclosure, selected aspects of the foregoing disclosure have been shown in block diagram form rather than in detail. Some portions of the detailed descriptions provided herein may be presented in terms of instructions that operate on data that is stored in one or more computer memories or one or more data storage devices. Such descriptions and representations are used by those skilled in the art to describe and convey the substance of their work to others skilled in the art. In general, an algorithm refers to a self-consistent sequence of steps leading to a desired result, where a “step” refers to a manipulation of physical quantities and/or logic states which may, though need not necessarily, take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It is common usage to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. These and similar terms may be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities and/or states.

Unless specifically stated otherwise as apparent from the foregoing disclosure, it is appreciated that, throughout the foregoing disclosure, discussions using terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the processor system's registers and memories into other data similarly represented as physical quantities within the processor system memories or registers or other such information storage, transmission or display devices.

In some instances, one or more elements may be described using the expression “coupled” and “connected” along with their derivatives. It should be understood that these terms are not intended as synonyms for each other. For example, some aspects may be described using the term “connected” to indicate that two or more elements are in direct physical or electrical contact with each other. In another example, some aspects may be described using the term “coupled” to indicate that two or more elements are in direct physical or electrical contact. The term “coupled,” however, also may mean that two or more elements are not in direct contact with each other and yet still co-operate or interact with each other. It is to be understood that depicted architectures of different components contained within, or connected with, different other components are merely examples, and that in fact many other architectures may be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated also can be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality, and any two components capable of being so associated also can be viewed as being “operably couplable,” to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components, and/or wirelessly interactable, and/or wirelessly interacting components, and/or logically interacting, and/or logically interactable components, and/or electrically interacting components, and/or electrically interactable components, and/or optically interacting components, and/or optically interactable components.

It is worthy to note that any reference to “one aspect,” “an aspect,” “one form,” or “a form” means that a particular feature, structure, or characteristic described in connection with the aspect is included in at least one aspect. Thus, appearances of the phrases “in one aspect,” “in an aspect,” “in one form,” or “in a form” in various places throughout the specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more aspects.

The following references are incorporated herein by reference: Phase Locked Loops Principles and Practice, Paul V. Brennan, McGraw Hill 1996; U.S. Pat. No. 3,755,758 to D. Leeson; Frequency Synthesis, Jerzy Gorski-Popiel, John Wiley & Sons 1975; Frequency Synthesizers Theory and Design, Vadim Manassewitsch, John Wiley & Sons 1980; Phaselock Techniques, Floyd Gardner, John Wiley & Sons 1966; Operational Amplifiers, G. Clayton & S. Winder Newnes 2000; YIG Resonators and Filters, J. Helszian, John Wiley & Sons 1985. All of the above-mentioned U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, non-patent publications referred to in this specification and/or listed in any Application Data Sheet, or any other disclosure material are incorporated herein by reference, to the extent not inconsistent herewith. As such, and to the extent necessary, the disclosure as explicitly set forth herein supersedes any conflicting material incorporated herein by reference. Any material, or portion thereof, that is said to be incorporated by reference herein, but which conflicts with existing definitions, statements, or other disclosure material set forth herein will only be incorporated to the extent that no conflict arises between that incorporated material and the existing disclosure material.

Various aspects of the subject matter described herein are set out in the following numbered examples:

A signal generator, comprising of the tuning voltage and the offset voltage (Vm−Vo); a comparator circuit coupled to the adder and the subtractor circuits, the comparator circuit configured to receive a digitized voltage controlled oscillator tuning voltage (Vt) and to compare the digitized voltage controlled oscillator (VCO) tuning voltage (Vt) to the sum of the tuning voltage and the offset voltage (Vm+Vo) and the difference of the tuning voltage and the offset voltage (Vm−Vo) and to produce a window bounded by (Vm+Vo) and (Vm−Vo), the comparator circuit further configured to generate control signals; and a steering current circuit coupled to the comparator circuit to receive the control signals from the comparator circuit and to control a steering current based on the control signals.

The signal generator of Example 1, wherein the comparator circuit is configured to compute three logical decisions as follows: a first logical decision given by A=Vt≥(Vm+Vo); a second logical decision given by B=Vt≤(Vm−Vo); and a third logical decision given by C=(Vm−Vo)≤Vt≤(Vm+Vo).

The signal generator of Example 2, wherein: a true outcome of the first logical decision causes the comparator circuit to output a first control signal to the steering current circuit to steer the steering current in a first direction; a true outcome of the second logical decision causes the comparator circuit to output a second control signal to the steering current circuit to steer the steering current in a second direction opposite the first direction; and a true outcome of the third logical decision causes the comparator circuit to output a third control signal to the steering current circuit to disable the steering current.

The signal generator of any one of Example 1-3, wherein the steering current circuit comprises a first electronic switch S1controlled by the first control signal, a second electronic switch S2controlled by the second control signal, and a third electronic switch S3controlled by the third control signal.

The signal generator of any one of Examples 1-4, further comprising: a phase-locked loop (PLL) circuit coupled to the comparator circuit and the steering current circuit, wherein the PLL circuit comprises a loop filter comprising a loop filter capacitor; wherein the true outcome of the first logical decision causes the comparator circuit to output the first control signal to the steering current circuit to charge the loop filter capacitor with the steering current; and wherein the true outcome of the second logical decision causes the comparator circuit to output the second control signal to the steering current circuit to discharge the loop filter capacitor with the steering current.

The signal generator of any one of Examples 1-5, further comprising a PLL control circuit coupled to the PLL circuit, the PLL control circuit comprising a phase comparator/detector coupled to the third electronic switch, the phase comparator/detector configured to output a reference frequency signal; wherein true outcome of the third logical decision causes the comparator circuit to output a third control signal to the steering current circuit to couple the reference frequency signal to the loop filter.

The signal generator of any one of Examples 1-6 further comprising an analog-to-digital converter (ADC) coupled to the comparator circuit and to the loop filter, wherein the ADC is configured to: receive an analog VCO tuning voltage from the loop filter; convert the analog VCO tuning voltage to the digitized VCO tuning voltage (Vt); and provide the digitized VCO tuning voltage (Vt) to the comparator circuit; wherein the comparator circuit is configured to utilize the digitized VCO tuning voltage (Vt) to compute the three logical decisions.

The signal generator of any one of Examples 1-7, wherein the tuning voltage (Vm) values and the offset voltage (Vo) values stored in the memory are paged by temperature.

A method of generating a signal, the method comprising: receiving, by a processor/logic, a request to output a new frequency; generating, by a phase-lock-loop (PLL) circuit, a new analog tuning voltage corresponding to the new frequency; loading, by the processor/logic into a comparator, a new digital tuning voltage (Vt); loading, by the processor/logic from a memory into an adder/subtractor circuit, a new tuning voltage (Vm) corresponding to the value of the new frequency; loading, by the processor/logic from the memory into the adder/subtractor circuit, a new offset voltage (Vo); computing, by the comparator, logical mathematical decisions based on the new digital tuning voltage (Vt), the new tuning voltage (Vm), and the new offset voltage (Vo); controlling, by a steering current circuit coupled to the comparator, a steering current into or out of the PLL circuit; and generating, by the PLL circuit, a tuning voltage based on the steering current.

The method of Example 9, further comprising: loading, by the processor/logic, a frequency control word corresponding to the new frequency into the PLL circuit; and converting, by an analog-to-digital converter (ADC), the new analog tuning voltage to a new digital tuning voltage (Vt).

The method of any one of Examples 9-10, further comprising: comparing, by the comparator, the new digital tuning voltage (Vt) to the sum of the new tuning voltage (Vm) and the new offset voltage (Vo); and comparing, by the comparator, the new digital tuning voltage (Vt) to the difference of the new tuning voltage (Vm) and the new offset voltage (Vo).

The method of anyone of Examples 9-11, further comprising: determining, by the comparator, that the new digital tuning voltage (Vt) is greater than or equal to the sum of the new tuning voltage (Vm) and the new offset voltage (Vo); controlling, by the steering current circuit, the steering current into the PLL circuit; and ramping down, by the PLL circuit, the analog tuning voltage.

The method of any one of Examples 9-12, further comprising: determining, by the comparator, that the new digital tuning voltage (Vt) is less than or equal to the difference of the new tuning voltage (Vm) and the new offset voltage (Vo); controlling, by the steering current circuit, the steering current out of the PLL circuit; and ramping up, by the PLL circuit, the analog tuning voltage.

The method of any one of Examples 9-13, further comprising: determining, by the comparator, that the new digital tuning voltage (Vt) is greater than or equal to the difference of the new tuning voltage (Vm) and the new offset voltage (Vo) and is less than or equal to the sum of the new tuning voltage (Vm) and the new offset voltage (Vo); and disabling, by the steering current circuit, the steering current from flowing into or out of the PLL circuit.

The method of any one of Examples 9-14, wherein the memory comprises a tuning voltage memory to store tuning voltage and an offset voltage memory to store offset voltage.

A signal generator, comprising: a processor/logic; a memory coupled to the processor/logic, the memory stores digital tuning voltage and offset voltage values; an adder/subtractor circuit coupled to the memory; a comparator coupled to the adder/subtractor circuit; a steering current circuit coupled to the comparator; and a phase-lock-loop (PLL) circuit coupled to the memory and the steering current circuit, the PLL circuit further comprising: a programmable counter; a loop filter comprising a loop filter capacitor, a loop filter coupled to the steering current circuit; a phase comparator/detector circuit; and a voltage controlled oscillator (VCO); wherein the processor/logic is configured to: receive a request to output a new frequency; generate, by a phase-lock-loop (PLL) circuit, a new analog tuning voltage corresponding to the new frequency; load into the comparator a new digital tuning voltage (Vt); load from a memory into an adder/subtractor circuit, a new tuning voltage (Vm) corresponding to the value of the new frequency; load from the memory into the adder/subtractor circuit a new offset voltage (Vo); wherein the comparator is configured to compute logical mathematical decisions based on the new digital tuning voltage (Vt), the new tuning voltage (Vm), and the new offset voltage (Vo); wherein the steering current circuit is configured to control steering current into or out of the PLL circuit; and wherein the PLL circuit is configured to generate a tuning voltage based on the steering current.

The signal generator of Example 16, further comprising an analog-to-digital converter (ADC); wherein the processor/logic is configured to load a frequency control word corresponding to the new frequency into the PLL circuit; and wherein the ADC is configured to convert the new analog tuning voltage to a new digital tuning voltage (Vt).

The signal generator of any one of Examples 16-17, wherein the comparator is configured to: compare the new digital tuning voltage (Vt) to the sum of the new tuning voltage (Vm) and the new offset voltage (Vo); and compare the new digital tuning voltage (Vt) to the difference of the new tuning voltage (Vm) and the new offset voltage (Vo).

The signal generator of any one of Examples 16-18, wherein the comparator is configured to determine that the new digital tuning voltage (Vt) is greater than or equal to the sum of the new tuning voltage (Vm) and the new offset voltage (Vo); wherein the steering current circuit is configured to control the steering current into the PLL circuit; and wherein the PLL circuit is configured to ramp down the analog tuning voltage.

The signal generator of any one of Examples 16-18, further comprising: wherein the comparator is configured to determine that the new digital tuning voltage (Vt) is less than or equal to the difference of the new tuning voltage (Vm) and the new offset voltage (Vo); wherein the steering current circuit is configured to control the steering current out of the PLL circuit; and wherein the PLL circuit is configured to ramp up the analog tuning voltage.

The signal generator of any one of Examples 16-18, further comprising: wherein the comparator is configured to determine that the new digital tuning voltage (Vt) is greater than or equal to the difference of the new tuning voltage (Vm) and the new offset voltage (Vo) and is less than or equal to the sum of the new tuning voltage (Vm) and the new offset voltage (Vo); and wherein the steering current circuit is configured to disable the steering current from flowing into or out of the PLL circuit.