Semiconductor device and operating method thereof

Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to an integrated circuit (IC) technology, and particularly to a semiconductor device and an operating method thereof.

2. Description of Related Art

A laterally double-diffused metal oxide semiconductor (LDMOS) transistor is a power source device commonly used in semiconductor processes. A LDMOS transistor can provide a higher breakdown voltage (Vbd) and has a lower on-resistance (Ron) during operation, and hence, it is normally used as a high voltage device in power management IC. As electron products become more digitized and miniaturized, the demands for voltage accuracy, stability and device durability increase.

However, as the dimension of a LDMOS transistor is getting decreased, the distance between components is getting shorter. Therefore, the gate-induced drain leakage (GIDL) current of the device is often observed, and the noise from the substrate becomes serious. High GIDL current and high substrate noise result in the operation failure of the LDMOS transistor and accordingly reduce the performance of the device.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor device, in which a dummy gate is disposed between the gate and the drain region for reducing the GIDL current, and a deep well region is disposed between the substrate and each well region for reducing the noise from the substrate.

The present invention further provides an operating method of the semiconductor device. The semiconductor device is a five-terminal device and can be operated without a GIDL current and a substrate noise.

The present invention provides a semiconductor device including a substrate of a first conductivity type, a first well region of the first conductivity type, a second well region of a second conductivity type, a gate, source and drain regions of the second conductivity type, a dummy gate and a first deep well region of the second conductivity type. The first well region is disposed in the substrate. The second well region is disposed in the substrate proximate to the first well region. The gate is disposed on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is disposed in the first well region at one side of the gate. The drain region is disposed in the second well region at another side of the gate. The dummy gate is disposed on the substrate between the gate and the drain region. The first deep well region disposed in the substrate and surrounding the first and second well regions.

According to an embodiment of the present invention, the semiconductor device further includes a second deep well region of the first conductivity type disposed in the substrate between the first deep well region and each of the first and second well regions.

According to an embodiment of the present invention, a doping concentration of the first and second deep well regions is greater than a doping concentration of the first and second well regions.

According to an embodiment of the present invention, the semiconductor device further includes at least one doped region of the second conductivity type, disposed in the first deep well region, and at least one isolation structure, disposed in the substrate between the doped region and the source region or the drain region.

According to an embodiment of the present invention, the first well region is in contact with the second well region.

According to an embodiment of the present invention, the first well region and the second well region are separated by a distance.

According to an embodiment of the present invention, the semiconductor device further includes an isolation structure disposed in the substrate between the first and second well regions.

According to an embodiment of the present invention, a salicide-free region is present between the gate and the dummy gate.

According to an embodiment of the present invention, the semiconductor device further includes a salicide layer disposed on surfaces of the gate and the source and drain regions.

According to an embodiment of the present invention, the salicide layer is further disposed on a surface of the dummy gate.

According to an embodiment of the present invention, the gate includes amorphous silicon, polysilicon, metal, metal silicide or a combination thereof.

According to an embodiment of the present invention, the dummy gate includes amorphous silicon, polysilicon, metal, metal silicide or a combination thereof.

According to an embodiment of the present invention, the dummy gate is a floating gate.

The present invention further provides an operation of the said semiconductor device, which includes applying a first voltage to the drain region, applying a second voltage to the first deep well region, and applying a third voltage to the substrate.

According to an embodiment of the present invention, the second voltage is greater than the third voltage but less than the first voltage.

According to an embodiment of the present invention, the first voltage is about 5V and the third voltage is about zero.

According to an embodiment of the present invention, the operating method further includes applying a fourth voltage to the source region, and applying a fifth voltage to the gate.

According to an embodiment of the present invention, the fourth voltage is about zero, and the fifth voltage is about 2.5V.

According to an embodiment of the present invention, the dummy gate is a floating gate.

According to an embodiment of the present invention, the second deep well region is floating.

In view of the above, by disposing a dummy gate between the gate and the drain region and arranging a deep well region between the substrate and each well region, the GIDL current of the device can be reduced and the noise from the substrate can be decreased. Therefore, the malfunction of the device can be prevented, and the performance of the device can be significantly improved.

DESCRIPTION OF EMBODIMENTS

FIG. 1is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

The following embodiments in which the first conductivity type is P-type and the second conductivity type is N-type is provided for illustration purposes, and are not to construed as limiting the scope of the present invention. The P-type dopant includes boron, and the N-type dopant includes arsenic or phosphorous. It is appreciated by persons skilled in the art that the first conductivity type can be N-type and the second conductivity type can be P-type.

Referring toFIG. 1, the semiconductor device10of the invention includes a substrate100of a first conductivity type, a first well region102of the first conductivity type, a second well region104of a second conductivity type, a gate106, source and drain regions108and110of the second conductivity type, a dummy gate112and a first deep well region114of the second conductivity type.

The substrate100can be a P-type semiconductor substrate, such as a P-type silicon substrate. The first well region102can be a P-type lightly doped (P−) region. The second well region104can be an N-type lightly doped (N−) region. The first well region102and the second well region104are disposed in the substrate100and proximate to each other. In this embodiment, the first well region102is in contact with the second well region104. The doping concentration of the first well region102and ranges from about 1×1012to 2×1013atom/cm2. The doping concentration of the second well region104ranges from about 5×1012to 3×1013atom/cm2. Besides, the doping concentration of the first well region102can be the same or different from that of the second well region104.

The gate106is disposed on the substrate100and covers a portion of the first well region102and a portion of the second well region104. The gate106includes a gate dielectric layer105and a conductive layer107. The gate dielectric layer105includes silicon oxide, silicon nitride, silicon oxynitride, a high-k material with a dielectric constant greater than 4, or a combination thereof. The high-k material can be metal oxide, such as HfO2, ZrO2, Al2O3, TiO2, La2O3, Y2O3, Gd2O3, Ta2O5or a combination thereof. The conductive layer107includes amorphous silicon, undoped or doped polysilicon, metal (e.g. W, Al or Cu), or a combination thereof.

The source and drain regions108and110can be N-type heavily doped (N+) regions. The source region108is disposed in the first well region102at one side of the gate106. The drain region110is disposed in the second well region104at another side of the gate106.

The dummy gate112is disposed on the substrate100between the gate106and the drain region110. In this embodiment, the dummy gate112includes a gate dielectric layer111and a conductive layer113. The gate dielectric layer111includes silicon oxide, silicon nitride, silicon oxynitride, a high-k material with a dielectric constant greater than 4, or a combination thereof. The high-k material can be metal oxide, such as includes HfO2, ZrO2, Al2O3, TiO2, La2O3, Y2O3, Gd2O3, Ta2O5or a combination thereof. The conductive layer113includes amorphous silicon, undoped or doped polysilicon, metal (e.g. W, Al or Cu), or a combination thereof. Besides, in terms of the process availability, the gate dielectric layer111can have the same material and thickness with those of the gate dielectric layer105, and the conductive layer113can have the same material and thickness with those of the gate dielectric layer107. However, the present invention is not limited thereto. In another embodiment, the gate dielectric layers105and111can have different thicknesses and materials. Similarly, the conductive layers107and113can have different thicknesses and materials. For example, the conductive layer107can include doped polysilicon, while the conductive layer113can include amorphous silicon.

Herein, since the dummy gate112is a floating gate, the materials and number of layers thereof are trivial. In other words, the materials and layers of the dummy gate112can be adjusted upon the process availability.

Besides, in this embodiment, the dummy gate112and the drain region110are separated by a distance, as shown in the semiconductor device10ofFIG. 1, but the present invention is not limited by this. In another embodiment, the borderline of the dummy gate112can be aligned with the borderline of the drain region110, as shown in the semiconductor device20ofFIG. 2. In yet another embodiment (not shown), the dummy gate112and the drain region110can be partially overlapped.

The first deep well region114can be an N-type doped region. The first deep well region114is disposed in the substrate100and surrounds the first and second well regions102and104. In this embodiment, the first deep well region114surrounds the first and second well regions102and104but is not in contact with the first and second well regions102and104. Besides, the first deep well region114has a doping concentration greater than that of the first and second well regions102and104. For example, the doping concentration of the first deep well region114ranges from about 1×1013to 5×1013atom/cm2.

The semiconductor device10further includes a salicide layer109at least disposed on the surfaces of the conductive layer107and the source and drain regions108and110for decreasing the junction resistances of the conductive layer107and the source and drain regions108and110. The salicide layer109on the conductive layer107can be regarded as a component constituting the gate106. The salicide layer109includes metal silicide, such as WSi, TiSi, CoSi, MoSi, NiSi, PdSi or PtSi. In an embodiment, the salicide layer109is further disposed on the surface of the conductive layer113and can be regarded as a component constituting the dummy gate112, as shown inFIG. 1. In another embodiment, no salicide layer is disposed on the surface of the dummy gate112, as shown inFIG. 2.

It is noted that a salicide-free region130is present between the gate106and the dummy gate112. Specifically, a salicide block (SAB) layer is present in the salicide-free region130during the formation of the sailicide layer109, so as to prevent formation of a salicide layer on the surface of the second well region104between the gate106and the dummy gate112. The salicide-free region130and the floating dummy gate112of the invention play an important role in lowering the electric field between the gate106and the drain region110, thereby reducing the GIDL current.

The semiconductor device10further includes a second deep well region116of the first conductivity type disposed in the substrate100between the first deep well region114and each of the first and second well regions102and104. The second deep well region116can be a P-type doped region. In this embodiment, the second deep well region116surrounds and contacts the first and second well regions102and104. Besides, the second deep well region116and the first deep well region114can contact with each other (as shown inFIG. 1) or can be separated from one another (not shown). In addition, the doping concentration of the first deep well region114can be the same or different from that of the second deep well region116. Besides, the second deep well region116has a doping concentration greater than that of the first and second well regions102and104. For example, the doping concentration of the second deep well region116ranges from about 2×1013to 5×1013atom/cm2. Herein, the first and second deep well regions114and116are disposed between the substrate100and each of the first and second well regions102and104, and such configuration can effectively reduce the noise from the substrate100.

The semiconductor device100further includes at least one doped region118of the second conductivity type and at least one isolation structure120. Each doped region118can be an N-type heavily doped (N+) region. In this embodiment, two doped regions118are disposed in the first deep well region114and have a doping concentration greater than that of the first deep well region114. For example, the doping concentration of the doped regions118ranges from about 5×1013to 3×1015atom/cm2. In an embodiment, the salicide layer109can be further disposed on the surfaces of the doped regions118, so as to reduce the junction resistances of the first deep well region114and the doped regions118. Besides, two isolation structures120are disposed in the substrate100, one of the isolation structures120is located between one of the doped regions118and the source region108, and the other of the isolation structures120is located between the other of the doped regions118and the drain region110. Each isolation structure120can be a shallow trench isolation (STI) structure. Each isolation structure120includes silicon oxide, and the depth thereof is substantially the same as, greater than or less than the depth of the first and second well regions102and104.

The embodiment ofFIG. 1in which the first well region102is disposed in contact with the second well region104is provided for illustration purposes, and is not construed as limiting the present invention. In another embodiment, the first well region102and the second well region104can be separated by a distance. As shown inFIG. 3, the semiconductor device30can further includes an isolation structure140disposed in the substrate100between the first and second well regions102and104. The isolation structure140can be a shallow trench isolation (STI) structure. The isolation structure140includes silicon oxide and the depth thereof is substantially the same as, greater than or less than the depth of the first and second well regions102and104.

Besides, the second deep well region116is an optional component and can be omitted from the semiconductor device. As shown inFIG. 4, in the semiconductor device40, the first deep well region114is the only component disposed in the substrate100for reducing the substrate noise. Specifically, the first deep well region114surrounds but keeps a distance from the first and second well regions102and104.

In another embodiment, the isolation structure140can be further included in the device while the second deep well region116can be omitted from the device, as shown in the semiconductor device50ofFIG. 5.

The operating method of the invention is described below in reference to the semiconductor device10ofFIG. 1. As shown inFIG. 1, the operating method of the invention includes applying a first voltage V1to the drain region110, applying a second voltage V2to the first deep well region114, and applying a third voltage V3to the substrate100. Herein, the second voltage V2is greater than the third voltage V3but less than the first voltage V1. For example, the first voltage V1is about 5V, the third voltage V3is about zero (grounded), and the second voltage V2is about 2.5V. Besides, the first deep well region114and the doped regions118are in contact with each other and have the same conductivity type, and thus, the second voltage V2can be applied to the doped regions118with a higher doping concentration, so as to reduce the junction resistances.

The operation method further includes applying a fourth voltage V4to the source region108, and applying a fifth voltage V5to the gate106. The fourth voltage V4is about zero (grounded), and the fifth voltage V5is about 2.5V.

Herein, the dummy gate109and the second deep well region116are floating, so the semiconductor device10can be regarded as a five-terminal device with terminals of the source region108, the gate106, the drain region110, the substrate100and the first deep well region114. The operating voltages applied to the terminals are provided only for illustration purposes and are not construed as limiting the present invention.

In summary, in the semiconductor device of the invention, a dummy gate is disposed between the gate and the drain region, and a deep well region is disposed between the substrate and each well region. By such disposition, the GIDL current of the device can be reduced and the noise from the substrate can be decreased. Therefore, the malfunction of the device can be prevented, and the performance of the device can be significantly improved.

The present invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be defined by the following claims.