Electrostatic discharge protection device and electronic device having the same

In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2014-0174759, filed on Dec. 8, 2014 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

1. Technical Field

Exemplary embodiments in accordance with principles of inventive concepts relate to electrostatic discharge (ESD) protection technology, and more particularly to an ESD protection device and an electronic device including the ESD protection device.

2. Description of the Related Art

As the size of semiconductor devices decrease and the density of semiconductor devices increases, an ESD protection device, which protects the semiconductor device from damage caused by an ESD, becomes more important.

Conventionally, a diode, a resistor, and a transistor are generally used in an ESD protection device. More recently, a silicon controlled rectifier (SCR) is widely used as an ESD protection device.

However, when the holding voltage of the SCR is lower than an operational voltage of the semiconductor device, the semiconductor device may not operate correctly.

SUMMARY

Some exemplary embodiments are directed to provide an electrostatic discharge (ESD) protection device that has a high holding voltage.

Some exemplary embodiments are directed to provide an electronic device including the ESD protection device.

According to exemplary embodiments, an electrostatic discharge (ESD) protection device includes a semiconductor substrate, a first well, a second well, a first impurity region, a second impurity region, a third impurity region, and a fourth impurity region. The first well is formed in the semiconductor substrate, and has a first conductivity type. The second well is formed in the semiconductor substrate, contacts the first well, and has a second conductivity type. The first impurity region is formed in the first well, has the first conductivity type, and is electrically connected to a first electrode pad. The second impurity region is formed in the first well, is spaced apart from the first impurity region in a direction of the second well, has the second conductivity type, and is electrically connected to the first electrode pad. The third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. The fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

In exemplary embodiments, the ESD protection device may further include a fifth impurity region. The fifth impurity region may be formed in the second well, be spaced apart from the fourth impurity region in a direction of the first well, have the second conductivity type, and be electrically floated.

An impurity concentration of the fifth impurity region may be higher than an impurity concentration of the second well.

A holding voltage of the ESD protection device may be determined based on a width of the fifth impurity region.

The ESD protection device may further include a sixth impurity region and a gate. The sixth impurity region may be formed at a boundary region between the first well and the second well, have the second conductivity type, and is electrically floated. The gate may be formed above the semiconductor substrate between the second impurity region and the sixth impurity region, and be electrically connected to the first electrode pad.

An impurity concentration of the sixth impurity region may be higher than an impurity concentration of the second well.

Impurity concentrations of the first impurity region and the fourth impurity region may be substantially the same, and impurity concentrations of the second impurity region, the third impurity region, the fifth impurity region, and the sixth impurity region may be substantially the same.

The first impurity region and the fourth impurity region may be formed at the same time by a same ion implantation process, and the second impurity region, the third impurity region, the fifth impurity region, and the sixth impurity region may be formed at the same time by a same ion implantation process.

In exemplary embodiments, the ESD protection device may further include a fifth impurity region. The fifth impurity region may be formed in the first well, be spaced apart from the second impurity region in a direction of the second well, have the first conductivity type, and be electrically floated.

An impurity concentration of the fifth impurity region may be higher than an impurity concentration of the first well.

A holding voltage of the ESD protection device may be determined based on a width of the fifth impurity region.

The ESD protection device may further include a sixth impurity region and a gate. The sixth impurity region may be formed at a boundary region between the first well and the second well, have the first conductivity type, and be electrically floated. The gate may be formed above the semiconductor substrate between the fourth impurity region and the sixth impurity region, and be electrically connected to the second electrode pad.

An impurity concentration of the sixth impurity region may be higher than an impurity concentration of the first well.

Impurity concentrations of the second impurity region and the third impurity region may be substantially the same, and impurity concentrations of the first impurity region, the fourth impurity region, the fifth impurity region, and the sixth impurity region may be substantially the same.

The second impurity region and the third impurity region may be formed at the same time by a same ion implantation process, and the first impurity region, the fourth impurity region, the fifth impurity region, and the sixth impurity region may be formed at the same time by a same ion implantation process.

In exemplary embodiments, the first conductivity type may correspond to n-type, and the second conductivity type may correspond to p-type.

The first electrode pad may be coupled to a supply voltage, and the second electrode pad may be coupled to a ground voltage.

In exemplary embodiments, the first conductivity type may correspond to p-type, and the second conductivity type may correspond to n-type.

The first electrode pad may be coupled to a ground voltage, and the second electrode pad may be coupled to a supply voltage.

According to exemplary embodiments, an ESD protection device includes a semiconductor substrate, a first well, a second well, a first impurity region, a second impurity region, a third impurity region, a fourth impurity region, a fifth impurity region, a sixth impurity region, and a gate. The first well is formed in the semiconductor substrate, and has a first conductivity type. The second well is formed in the semiconductor substrate, contacts the first well, and has a second conductivity type. The first impurity region is formed in the first well, has the first conductivity type, and is electrically connected to a first electrode pad. The second impurity region is formed in the first well, is spaced apart from the first impurity region in a direction of the second well, has the second conductivity type, and is electrically connected to the first electrode pad. The third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. The fourth impurity region is formed in the second well, is spaced apart from the third impurity region in a direction of the first well, has the first conductivity type, and is electrically connected to the second electrode pad. The fifth impurity region is formed in the second well, is spaced apart from the fourth impurity region in a direction of the first well, has the second conductivity type, and is electrically floated. The sixth impurity region is formed at a boundary region between the first well and the second well, has the second conductivity type, and is electrically floated. The gate is formed above the semiconductor substrate between the second impurity region and the sixth impurity region, and is electrically connected to the first electrode pad.

In exemplary embodiments, an impurity concentration of the fifth impurity region and an impurity concentration of the sixth impurity region may be higher than an impurity concentration of the second well.

In exemplary embodiments, a holding voltage of the ESD protection device may be determined based on a width of the fifth impurity region.

In exemplary embodiments, impurity concentrations of the first impurity region and the fourth impurity region may be substantially the same, and impurity concentrations of the second impurity region, the third impurity region, the fifth impurity region, and the sixth impurity region may be substantially the same.

In exemplary embodiments, the first impurity region and the fourth impurity region may be formed at the same time by a same ion implantation process, and the second impurity region, the third impurity region, the fifth impurity region, and the sixth impurity region may be formed at the same time by a same ion implantation process.

In exemplary embodiments, the first conductivity type may correspond to n-type, and the second conductivity type may correspond to p-type.

The first electrode pad may be coupled to a supply voltage, and the second electrode pad may be coupled to a ground voltage.

In exemplary embodiments, the first conductivity type may correspond to p-type, and the second conductivity type may correspond to n-type.

The first electrode pad may be coupled to a ground voltage, and the second electrode pad may be coupled to a supply voltage.

According to exemplary embodiments, an electronic device includes a functional block and an ESD protection device. The functional block is coupled between a supply voltage pad, which is coupled to a supply voltage, and a ground voltage pad, which is coupled to a ground voltage, and operates using the supply voltage. The ESD protection device is coupled between the supply voltage pad and the ground voltage pad. The ESD protection device includes a semiconductor substrate, a first well, a second well, a first impurity region, a second impurity region, a third impurity region, and a fourth impurity region. The first well is formed in the semiconductor substrate, and has a first conductivity type. The second well is formed in the semiconductor substrate, contacts the first well, and has a second conductivity type. The first impurity region is formed in the first well, and has the first conductivity type. The second impurity region is formed in the first well, is spaced apart from the first impurity region in a direction of the second well, and has the second conductivity type. The third impurity region is formed in the second well, and has the second conductivity type. The fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated. When the first conductivity type corresponds to n-type and the second conductivity type corresponds to p-type, the first impurity region and the second impurity region are electrically connected to the supply voltage pad, and the third impurity region is electrically connected to the ground voltage pad. When the first conductivity type corresponds to p-type and the second conductivity type corresponds to n-type, the first impurity region and the second impurity region are electrically connected to the ground voltage pad, and the third impurity region is electrically connected to the supply voltage pad.

According to exemplary embodiments, an electronic device includes a functional block and an ESD protection device. The functional block is coupled to a supply voltage pad, which is coupled to a supply voltage, a ground voltage pad, which is coupled to a ground voltage, and a data input/output pad, and communicates data through the data input/output pad using the supply voltage. The ESD protection device is coupled between the data input/output pad and the ground voltage pad. The ESD protection device includes a semiconductor substrate, a first well, a second well, a first impurity region, a second impurity region, a third impurity region, and a fourth impurity region. The first well is formed in the semiconductor substrate, and has a first conductivity type. The second well is formed in the semiconductor substrate, contacts the first well, and has a second conductivity type. The first impurity region is formed in the first well, and has the first conductivity type. The second impurity region is formed in the first well, is spaced apart from the first impurity region in a direction of the second well, and has the second conductivity type. The third impurity region is formed in the second well, and has the second conductivity type. The fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated. When the first conductivity type corresponds to n-type and the second conductivity type corresponds to p-type, the first impurity region and the second impurity region are electrically connected to the data input/output pad, and the third impurity region is electrically connected to the ground voltage pad. When the first conductivity type corresponds to p-type and the second conductivity type corresponds to n-type, the first impurity region and the second impurity region are electrically connected to the ground voltage pad, and the third impurity region is electrically connected to the data input/output pad.

In exemplary embodiments in accordance with principles of inventive concepts, an electrostatic discharge protection device includes an avalanche breakdown device including first and second wells of different conductivity types formed adjacent to one another in a substrate and configured to conduct with positive feedback through parasitic bipolar transistors when pads connected to the wells reverse-bias the wells to a breakdown voltage level; and a high-concentration impurity region formed in one well and positioned to reduce the current gain of one of the parasitic bipolar transistors to increase a holding voltage of the avalanche breakdown device.

In exemplary embodiments in accordance with principles of inventive concepts, an electrostatic discharge protection device includes a high-concentration impurity region is positioned to partially determine the holding voltage of the avalanche breakdown device according to its proximity to a high-concentration impurity region formed in the well other than the well in which it is formed.

In exemplary embodiments in accordance with principles of inventive concepts, an electrostatic discharge protection device includes a high-concentration impurity region formed at a boundary between the first and second wells to decrease the breakdown voltage level.

In exemplary embodiments in accordance with principles of inventive concepts, an electrostatic discharge protection device includes a gate that, in combination with the high concentration impurity region formed at the boundary between the first and second wells and a high concentration impurity region of the same conductivity type as that formed at the boundary forms metal oxide semiconductor transistor to reduce the breakdown voltage level.

In exemplary embodiments in accordance with principles of inventive concepts, a portable electronic device includes an electrostatic discharge protection device that includes an avalanche breakdown device including first and second wells of different conductivity types formed adjacent to one another in a substrate and configured to conduct with positive feedback through parasitic bipolar transistors when pads connected to the wells reverse-bias the wells to a breakdown voltage level; and a high-concentration impurity region formed in one well and positioned to reduce the current gain of one of the parasitic bipolar transistors to increase a holding voltage of the avalanche breakdown device.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which some exemplary embodiments are shown. Inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present inventive concept to those skilled in the art. Like reference numerals refer to like elements throughout this application.

In exemplary embodiments in accordance with principles of inventive concepts, an electrostatic discharge protection device includes an avalanche breakdown device including first and second wells of different conductivity types formed adjacent to one another in a substrate and configured to conduct with positive feedback through parasitic bipolar transistors when pads connected to the wells reverse-bias the wells to a breakdown voltage level.

A high-concentration impurity region may be formed in one well and positioned to reduce the current gain of one of the parasitic bipolar transistors to increase a holding voltage of the avalanche breakdown device.

A high-concentration impurity region may be positioned to partially determine the holding voltage of the avalanche breakdown device according to its proximity to a high-concentration impurity region formed in the well other than the well in which it is formed.

A high-concentration impurity region may formed at a boundary between the first and second wells to decrease the breakdown voltage level.

A gate that, in combination with the high concentration impurity region formed at the boundary between the first and second wells and a high concentration impurity region of the same conductivity type as that formed at the boundary may be included to form metal oxide semiconductor transistor to reduce the breakdown voltage level.

In exemplary embodiments in accordance with principles of inventive concepts, a portable electronic device may include an electrostatic discharge protection device that includes an avalanche breakdown device including first and second wells of different conductivity types formed adjacent to one another in a substrate and configured to conduct with positive feedback through parasitic bipolar transistors when pads connected to the wells reverse-bias the wells to a breakdown voltage level.

A high-concentration impurity region may be formed in one well and positioned to reduce the current gain of one of the parasitic bipolar transistors to increase a holding voltage of the avalanche breakdown device.

A high-concentration impurity region may be positioned to partially determine the holding voltage of the avalanche breakdown device according to its proximity to a high-concentration impurity region formed in the well other than the well in which it is formed.

A high-concentration impurity region may formed at a boundary between the first and second wells to decrease the breakdown voltage level.

A gate that, in combination with the high concentration impurity region formed at the boundary between the first and second wells and a high concentration impurity region of the same conductivity type as that formed at the boundary may be included to form metal oxide semiconductor transistor to reduce the breakdown voltage level.

FIG. 1is a cross-sectional view of an exemplary embodiment of an electrostatic discharge (ESD) protection device in accordance with principles of inventive concepts.

Referring toFIG. 1, an ESD protection device100includes a semiconductor substrate SUB101, a first well110, a second well120, a first impurity region131, a second impurity region132, a third impurity region133, a fourth impurity region134, a fifth impurity region135, a sixth impurity region136, and a gate GPOLY140.

The first well110is formed in the semiconductor substrate101and is of a first conductivity type (also referred to herein as conductive type).

The second well120is formed in the semiconductor substrate101to contact the first well110and is of a second conductivity type.

In some exemplary embodiments, the first conductivity type may correspond to n-type, and the second conductivity type may correspond to p-type. In such exemplary embodiments, the first well110may correspond to an n-well and the second well120may correspond to a p-well.

Hereinafter, the first conductivity type is assumed to be n-type and the second conductivity type is assumed to be p-type.

In this exemplary embodiment, first impurity region N+131is formed in the first well110and is n-type. In some exemplary embodiments, an impurity concentration of the first impurity region131may be higher than an impurity concentration of the first well110.

In this exemplary embodiment, second impurity region P+132is formed in the first well110; is spaced apart from the first impurity region131in a direction of the second well120, and is p-type. In some exemplary embodiments, an impurity concentration of the second impurity region132may be higher than an impurity concentration of the second well120.

In this exemplary embodiment, third impurity region P+133is formed in the second well120and is p-type. In some exemplary embodiments, an impurity concentration of the third impurity region133may be higher than the impurity concentration of the second well120.

In this exemplary embodiment, fourth impurity region N+134is formed in the second well120, is spaced apart from the third impurity region133in a direction of the first well110, and is n-type. In some exemplary embodiments, an impurity concentration of the fourth impurity region134may be higher than the impurity concentration of the first well110.

In this exemplary embodiment, fifth impurity region P+135is formed in the second well120, is spaced apart from the fourth impurity region134in a direction of the first well110, and is p-type. In some exemplary embodiments, an impurity concentration of the fifth impurity region135may be higher than the impurity concentration of the second well120.

In this exemplary embodiment, sixth impurity region P+136is formed at a boundary region between the first well110and the second well120, is spaced apart from the second impurity region132and the fifth impurity region135, and is p-type. In some exemplary embodiments, an impurity concentration of the sixth impurity region136may be higher than the impurity concentration of the second well120.

In some exemplary embodiments, the first impurity region131and the fourth impurity region134may be formed at the same time by the same ion implantation process. In such exemplary embodiments, the impurity concentrations of the first impurity region131and the fourth impurity region134may be substantially the same.

In some exemplary embodiments, the second impurity region132, the third impurity region133, the fifth impurity region135, and the sixth impurity region136may be formed at the same time by a same ion implantation process. In such exemplary embodiments, the impurity concentrations of the second impurity region132, the third impurity region133, the fifth impurity region135, and the sixth impurity region136may be substantially the same.

In exemplary embodiments, gate140is formed above the semiconductor substrate101between the second impurity region132and the sixth impurity region136. In some exemplary embodiments, the gate140may include polysilicon.

The first impurity region131, the second impurity region132, and the gate140may be electrically connected to a first electrode pad ESD_HIGH151. The third impurity region133and the fourth impurity region134may be electrically connected to a second electrode pad ESD_LOW152.

The fifth impurity region135and the sixth impurity region136may be electrically floated.

In exemplary embodiments, in operation, first electrode pad151may be coupled to a relatively high voltage, and the second electrode pad152may be coupled to a relatively low voltage. In some exemplary embodiments, the first electrode pad151may be coupled to a supply voltage, and the second electrode pad152may be coupled to a ground voltage. In other exemplary embodiments, the first electrode pad151may be coupled to a data input/output pin, and the second electrode pad152may be coupled to the ground voltage.

As will be described in greater detail later, when an ESD event occurs such that a plurality of positive charges (or, simply, positive charge) flow in the ESD protection device100through the first electrode pad151, the ESD protection device100may be turned on to discharge the positive charges to the second electrode pad152.

FIG. 2is a diagram illustrating a bipolar junction transistor (BJT) parasitically formed in the ESD protection device ofFIG. 1.FIG. 3is a circuit diagram illustrating an equivalent circuit of the ESD protection device ofFIG. 1.

Referring toFIG. 2, a PNP bipolar junction transistor (BJT)161may be parasitically formed in the ESD protection device100. An emitter of the PNP BJT161may correspond to the second impurity region132, a base of the PNP BJT161may correspond to the first well110, and a collector of the PNP BJT161may correspond to the second well120and the third impurity region133.

In addition, an NPN BJT162may be parasitically formed in the ESD protection device100. A collector of the NPN BJT162may correspond to the first impurity region131and the first well110, a base of the NPN BJT162may correspond to the second well120, and an emitter of the NPN BJT162may correspond to the fourth impurity region134.

InFIG. 2, the resistance of the first well110is represented as an n-well resistor Rnw, and the resistance of the second well120is represented as a p-well resistor Rpw.

In this manner, an equivalent circuit of the ESD protection device100ofFIG. 1may be represented as a circuit diagram ofFIG. 3.

Hereinafter, operation of the ESD protection device100will be described with reference toFIGS. 1 to 3.

When an ESD event occurs, positive charge may flow in the ESD protection device100through the first electrode pad151. Because the positive charge is transferred to the first well110, an electric potential of the first well110may increase as the amount of positive charge flowing in the ESD protection device100through the first electrode pad151increases. Therefore, the first well110and the second well120may be in a reverse biased state. When the electric potential of the first well110increases such that an electric potential difference between the first well110and the second well120reaches a breakdown voltage, an avalanche breakdown may occur at a junction of the first well110and the second well120.

When the avalanche breakdown occurs, electron-hole pairs may be generated and holes of the electron-hole pairs may be transferred to the second well120to increase an electric potential of the second well120. When the electric potential of the second well120increases such that an electric potential difference between the second well120and the fourth impurity region134becomes greater than a threshold voltage of the NPN BJT162, the NPN BJT162may be turned on.

When the NPN BJT162is turned on, a current may flow from the first electrode pad151to the second electrode pad152through the first impurity region131, the first well110, the second well120, and the fourth impurity region134. While the current flows through the first well110, a voltage drop may occur at the first well110by the n-well resistor Rnw. Therefore, the electric potential of the first well110may become lower than an electrical potential of the second impurity region132, such that the PNP BJT161may be turned on.

When the PNP BJT161is turned on, a current may flow from the first electrode pad151to the second electrode pad152through the second impurity region132, the first well110, the second well120, and the third impurity region133. While the current flows through the second well120, a voltage drop may occur at the second well120by the p-well resistor Rpw. Therefore, the electric potential of the second well120may be maintained higher than an electrical potential of the fourth impurity region134, such that the NPN BJT162may be turned on more strongly.

As described above, when an ESD event occurs such that positive charge flows in the ESD protection device100through the first electrode pad151, the PNP BJT161and the NPN BJT162may be maintained in a turned on state through positive feedback. Therefore, when the ESD event occurs such that positive charge flows in the ESD protection device100through the first electrode pad151, the ESD protection device100may be turned on to discharge the positive charge to the second electrode pad152.

A conventional silicon controlled rectifier (SCR) does not include the fifth impurity region135, the sixth impurity region136, and the gate140.

As will be described in greater detail below, a triggering voltage of the conventional SCR is relatively high and a holding voltage of the conventional SCR is relatively low. Unlike a conventional SCR, the ESD protection device100according to exemplary embodiments of inventive concepts may include the sixth impurity region136, which is formed at a boundary region between the first well110and the second well120, and, because the impurity concentration of the sixth impurity region136is higher than the impurity concentration of the second well120, the breakdown voltage, at which an avalanche breakdown occurs at a junction of the first well110and the second well120, may decrease because of the sixth impurity region136. As a result, the triggering voltage of the ESD protection device100may be lower than that of a conventional ESD protection device.

In addition, the ESD protection device100according to exemplary embodiments may include the gate140, which is formed above the semiconductor substrate101between the second impurity region132and the sixth impurity region136, and is electrically connected to the first electrode pad151. Because the second impurity region132, the sixth impurity region136, and the gate140form a metal oxide semiconductor (MOS) transistor, the breakdown voltage, at which an avalanche breakdown occurs at a junction of the first well110and the second well120, may be similar to a breakdown voltage of the MOS transistor. As such, a triggering voltage of an ESD protection device100in accordance with principles of inventive concepts may further decrease.

In addition, the ESD protection device100according to exemplary embodiments may include the fifth impurity region135, which is formed in the second well120to be spaced apart from the fourth impurity region134in a direction of the first well110. As a result, a distance between the first well110and the fifth impurity region135may be smaller than a distance between the first well110and the third impurity region133. As such, when the PNP BJT161is turned on, a portion of the current, which flows from the first electrode pad151to the second electrode pad152through the second impurity region132, the first well110, the second well120, and the third impurity region133, may be leaked to the fifth impurity region135, such that a current gain of the PNP BJT161may decrease. Because the holding voltage of the ESD protection device100is inversely proportional to the current gain of the PNP BJT161, the holding voltage of the ESD protection device100may increase.

FIG. 4is a graph illustrating voltage-current characteristics of an ESD protection device in accordance with principles of inventive concepts such as that of the exemplary embodiment ofFIG. 1.

InFIG. 4, the x-axis represents a voltage of the first electrode pad151, and the y-axis represents a current flowing from the first electrode pad151to the ESD protection device100.

InFIG. 4, first graph A represents voltage-current characteristics of a conventional SCR, and second graph B represents voltage-current characteristics of ESD protection device100in accordance with principles of inventive concepts.

As illustrated inFIG. 4, the conventional SCR, which does not include the fifth impurity region135, the sixth impurity region136, and the gate140, has a relatively high triggering voltage Vt1and a relatively low holding voltage Vh1. On the other hand, the ESD protection device100in accordance with principles of inventive concepts has a relatively low triggering voltage Vt2and a relatively high holding voltage Vh2.

As the width of the fifth impurity region135increases, the amount of current leaked to the fifth impurity region135among the current flowing from the first electrode pad151to the second electrode pad152through the second impurity region132, the first well110, the second well120, and the third impurity region133when the PNP BJT161is turned on may increase. Therefore, as the width of the fifth impurity region135increases, the current gain of the PNP BJT161may decrease such that the holding voltage of the ESD protection device100may increase.

Similarly, as the width of the fifth impurity region135decreases, the amount of current leaked to the fifth impurity region135among the current flowing from the first electrode pad151to the second electrode pad152through the second impurity region132, the first well110, the second well120, and the third impurity region133when the PNP BJT161is turned on may decrease. Therefore, as the width of the fifth impurity region135decreases, the current gain of the PNP BJT161may increase such that the holding voltage of the ESD protection device100may decrease.

Therefore, in accordance with principles of inventive concepts, the holding voltage of the ESD protection device100may be established, based on the width of the fifth impurity region135.

FIG. 5is a graph illustrating a variation of a holding voltage of the ESD protection device ofFIG. 1according to the width of a fifth impurity region.

InFIG. 5, the x-axis represents a voltage of the first electrode pad151, and the y-axis represents a current flowing from the first electrode pad151to the ESD protection device100.

InFIG. 5, a first graph C represents a holding voltage of the ESD protection device100when the width of the fifth impurity region135is relatively short (or small), and a second graph D represents a holding voltage of the ESD protection device100when the width of the fifth impurity region135is relatively long (or large).

As illustrated inFIG. 5, the holding voltage of the ESD protection device100in accordance with principles of inventive concepts may increase as the width of the fifth impurity region135increases, and the holding voltage of the ESD protection device100may decrease as the width of the fifth impurity region135decreases.

As described above with reference toFIGS. 1 to 5, because the ESD protection device100according to exemplary embodiments includes the fifth impurity region135, the sixth impurity region136, and the gate140, the ESD protection device100may have a relatively low triggering voltage and a relatively high holding voltage. In addition, the holding voltage of the ESD protection device100may be adjusted by controlling the width of the fifth impurity region135.

FIG. 6is a cross-sectional view of an exemplary embodiment of an ESD protection device in accordance with principles of inventive concepts.

Referring toFIG. 6, an ESD protection device200includes a semiconductor substrate SUB201, a first well210, a second well220, a first impurity region231, a second impurity region232, a third impurity region233, a fourth impurity region234, a fifth impurity region235, a sixth impurity region236, and a gate GPOLY240.

The first well210is formed in the semiconductor substrate201and is of a first conductivity type.

The second well220is formed in the semiconductor substrate201to contact the first well210and is of a second conductivity type.

In some exemplary embodiments, the first conductivity type may be a p-type, and the second conductivity type may be an n-type. In such exemplary embodiments, the first well210may be a p-well, and the second well220may be an n-well.

Hereinafter, the first conductivity type is assumed to be p-type, and the second conductivity type is assumed to be n-type.

The first impurity region P+231is formed in the first well210and is of p-type. In some exemplary embodiments, an impurity concentration of the first impurity region231may be higher than an impurity concentration of the first well210.

The second impurity region N+232is formed in the first well210, is spaced apart from the first impurity region231in a direction of the second well220and is of n-type. In some exemplary embodiments, an impurity concentration of the second impurity region232may be higher than an impurity concentration of the second well220.

The third impurity region N+233is formed in the second well220and is of n-type. In some exemplary embodiments, an impurity concentration of the third impurity region233may be higher than the impurity concentration of the second well220.

The fourth impurity region P+234is formed in the second well220, is spaced apart from the third impurity region233in a direction of the first well210, and is of p-type. In some exemplary embodiments, an impurity concentration of the fourth impurity region234may be higher than the impurity concentration of the first well210.

The fifth impurity region N+235is formed in the second well220, is spaced apart from the fourth impurity region234in a direction of the first well210, and is of n-type. In some exemplary embodiments, an impurity concentration of the fifth impurity region235may be higher than the impurity concentration of the second well220.

The sixth impurity region N+236is formed at a boundary region between the first well210and the second well220, is spaced apart from the second impurity region232and the fifth impurity region235, and is of n-type. In some exemplary embodiments, an impurity concentration of the sixth impurity region236may be higher than the impurity concentration of the second well220.

In some exemplary embodiments, the first impurity region231and the fourth impurity region234may be formed at the same time by in the same ion implantation process. As a result, the impurity concentrations of the first impurity region231and the fourth impurity region234may be substantially the same.

In some exemplary embodiments, the second impurity region232, the third impurity region233, the fifth impurity region235, and the sixth impurity region236may be formed at the same time by a same ion implantation process and, as a result, the impurity concentrations of the second impurity region232, the third impurity region233, the fifth impurity region235, and the sixth impurity region236may be substantially the same.

The gate240is formed above the semiconductor substrate201between the second impurity region232and the sixth impurity region236. In some exemplary embodiments, the gate240may include polysilicon.

The first impurity region231, the second impurity region232, and the gate240may be electrically connected to a first electrode pad ESD_LOW251. The third impurity region233and the fourth impurity region234may be electrically connected to a second electrode pad ESD_HIGH252.

The fifth impurity region235and the sixth impurity region236may be electrically floated.

The first electrode pad251may be coupled to a relatively low voltage, and the second electrode pad252may be coupled to a relatively high voltage. In some exemplary embodiments, the first electrode pad251may be coupled to a ground voltage, and the second electrode pad252may be coupled to a supply voltage. In other exemplary embodiments, the first electrode pad251may be coupled to the ground voltage, and the second electrode pad252may be coupled to a data input/output pin.

As will be described in greater detail later, when an ESD event occurs such that positive charge flows in the ESD protection device200through the second electrode pad252, the ESD protection device200may be turned on to discharge the positive charge to the first electrode pad251.

FIG. 7is a diagram illustrating a BJT parasitically formed in the ESD protection device ofFIG. 6.FIG. 8is a circuit diagram illustrating an equivalent circuit of the ESD protection device ofFIG. 6.

Referring toFIG. 7, a PNP BJT261may be parasitically formed in the ESD protection device200. An emitter of the PNP BJT261may correspond to the fourth impurity region234, a base of the PNP BJT261may correspond to the second well220, and a collector of the PNP BJT261may correspond to the first well210and the first impurity region231.

Additionally, an NPN BJT262may be parasitically formed in the ESD protection device200. A collector of the NPN BJT262may correspond to the third impurity region233and the second well220, a base of the NPN BJT262may correspond to the first well210, and an emitter of the NPN BJT262may correspond to the second impurity region232.

In the exemplary embodiment ofFIG. 7, resistance of the first well210is represented as a p-well resistor Rpw, and resistance of the second well220is represented as an n-well resistor Rnw.

Therefore, an equivalent circuit of the ESD protection device200ofFIG. 6may be represented as a circuit diagram ofFIG. 8.

Hereinafter, an exemplary operation of the ESD protection device200will be described with reference toFIGS. 6 to 8.

When an ESD event occurs, positive charge may flow in the ESD protection device200through the second electrode pad252. Because the positive charge is transferred to the second well220, an electric potential of the second well220may increase according to the amount of positive charge flowing in the ESD protection device200through the second electrode pad252increases. As a result, the first well210and the second well220may be in a reverse biased state. When the electric potential of the second well220increases such that an electric potential difference between the first well210and the second well220reaches a breakdown voltage, an avalanche breakdown may occur at a junction of the first well210and the second well220.

When the avalanche breakdown occurs, electron-hole pairs may be generated and holes of the electron-hole pairs may be transferred to the first well210to increase an electric potential of the first well210. When the electric potential of the first well210increases such that an electric potential difference between the first well210and the second impurity region232becomes greater than a threshold voltage of the NPN BJT262, the NPN BJT262may be turned on.

When the NPN BJT262is turned on, a current may flow from the second electrode pad252to the first electrode pad251through the third impurity region233, the second well220, the first well210, and the second impurity region232. While the current flows through the second well220, a voltage drop may occur at the second well220across the n-well resistor Rnw. As a result, the electric potential of the second well220may become lower than an electrical potential of the fourth impurity region234, such that the PNP BJT261may be turned on.

When the PNP BJT261is turned on, a current may flow from the second electrode pad252to the first electrode pad251through the fourth impurity region234, the second well220, the first well210, and the first impurity region231. While the current flows through the first well210, a voltage drop may occur at the first well210across the p-well resistor Rpw. As a result, the electric potential of the first well210may be maintained at a higher potential than the electrical potential of the second impurity region232, with the result that the NPN BJT262may be turned on more strongly.

As described above, when an ESD event occurs, resulting in positive charge flow in the ESD protection device200through the second electrode pad252, the PNP BJT261and the NPN BJT262may be maintained in a turned on state through positive feedback. As a result, when the ESD event occurs, resulting in positive charge flow in the ESD protection device200through the second electrode pad252, the ESD protection device200may be turned on to discharge positive charge to the first electrode pad251.

A conventional silicon controlled rectifier (SCR) does not include the fifth impurity region235, the sixth impurity region236, and the gate240and, as will be described in greater detail below, a triggering voltage of a conventional SCR is relatively high and a holding voltage of a conventional SCR is relatively low.

In contrast, an ESD protection device in accordance with principles of inventive concepts, such as ESD protection device200according to exemplary embodiments may include the sixth impurity region236, which is formed at a boundary region between the first well210and the second well220. Because the impurity concentration of the sixth impurity region236is higher than the impurity concentration of the second well220, the breakdown voltage, at which an avalanche breakdown occurs at a junction of the first well210and the second well220, may decrease because of the sixth impurity region236. As a result, a triggering voltage of the ESD protection device200may decrease, in accordance with principles of inventive concepts.

Additionally, in an ESD protection device in accordance with principles of inventive concepts, such as ESD protection device200according to exemplary embodiments may include the gate240, which is formed above the semiconductor substrate201between the second impurity region232and the sixth impurity region236, and is electrically connected to the first electrode pad251. Because the second impurity region232, the sixth impurity region236, and the gate240form a metal oxide semiconductor (MOS) transistor, the breakdown voltage, at which an avalanche breakdown occurs at a junction of the first well210and the second well220, may be similar to a breakdown voltage of the MOS transistor. As a result, a triggering voltage of the ESD protection device200may further decrease.

Furthermore, an ESD protection device in accordance with principles of inventive concepts, such as the ESD protection device200according to exemplary embodiments may include the fifth impurity region235, which is formed in the second well220to be spaced apart from the fourth impurity region234in a direction of the first well210. As a result, a distance between the first well210and the fifth impurity region235may be smaller than a distance between the first well210and the third impurity region233. As a result, when the NPN BJT262is turned on, a portion of the current, which flows from the second electrode pad252to the first electrode pad251through the third impurity region233, the second well220, the first well210, and the second impurity region232, may be leaked to the fifth impurity region235, so that a current gain of the NPN BJT262may decrease. Because a holding voltage of the ESD protection device200is inversely proportional to the current gain of the NPN BJT262, the holding voltage of the ESD protection device200may increase.

As a width of the fifth impurity region235increases, the amount of a current leaked to the fifth impurity region235among the current flowing from the second electrode pad252to the first electrode pad251through the third impurity region233, the second well220, the first well210, and the second impurity region232when the NPN BJT262is turned on may increase. Therefore, as the width of the fifth impurity region235increases, the current gain of the NPN BJT262may decrease and, as a result, the holding voltage of the ESD protection device200may increase.

Similarly, as a width of the fifth impurity region235decreases, the amount of current leaked to the fifth impurity region235among the current flowing from the second electrode pad252to the first electrode pad251through the third impurity region233, the second well220, the first well210, and the second impurity region232when the NPN BJT262is turned on may decrease. As a result, as the width of the fifth impurity region235decreases, the current gain of the NPN BJT262may increase such that the holding voltage of the ESD protection device200may decrease and the holding voltage of the ESD protection device200may be determined based on the width of the fifth impurity region235.

The ESD protection device200ofFIG. 6is the same as the ESD protection device100ofFIG. 1except that conductivity types of the first well210, the second well220, the first impurity region231, the second impurity region232, the third impurity region233, the fourth impurity region234, the fifth impurity region235, and the sixth impurity region236of the ESD protection device200ofFIG. 6are opposite to conductivity types of the first well110, the second well120, the first impurity region131, the second impurity region132, the third impurity region133, the fourth impurity region134, the fifth impurity region135, and the sixth impurity region136of the ESD protection device100ofFIG. 1, respectively. Therefore, voltage-current characteristics of the ESD protection device200may be similar to voltage-current characteristics of the ESD protection device100illustrated inFIGS. 4 and 5.

FIG. 9is a cross-sectional view of an ESD protection device according to exemplary embodiments.

Referring toFIG. 9, an ESD protection device300includes a semiconductor substrate SUB301, a first well310, a second well320, a first impurity region331, a second impurity region332, a third impurity region333, and a fourth impurity region334.

The first well310is formed in the semiconductor substrate301and has a first conductivity type.

The second well320is formed in the semiconductor substrate301to contact the first well310and has a second conductivity type.

In some exemplary embodiments, the first conductivity type may be n-type, and the second conductivity type may be p-type. In such exemplary embodiments, the first well310may be an n-well, and the second well320may be a p-well.

For the following description, the first conductivity type is assumed to be n-type, and the second conductivity type is assumed to be p-type.

The first impurity region N+331is formed in the first well310and is of n-type. In some exemplary embodiments, an impurity concentration of the first impurity region331may be higher than an impurity concentration of the first well310.

The second impurity region P+332is formed in the first well310, is spaced apart from the first impurity region331in a direction of the second well320, and is of p-type. In some exemplary embodiments, an impurity concentration of the second impurity region332may be higher than an impurity concentration of the second well320.

The third impurity region P+333is formed in the second well320, and is of p-type. In some exemplary embodiments, an impurity concentration of the third impurity region333may be higher than the impurity concentration of the second well320.

The fourth impurity region N+334is formed in the second well320, is located in a direction of the first well310from the third impurity region333and contacts the third impurity region333, and is of n-type. In some exemplary embodiments, an impurity concentration of the fourth impurity region334may be higher than the impurity concentration of the first well310.

The first impurity region331and the second impurity region332may be electrically connected to a first electrode pad ESD_HIGH351. The third impurity region333may be electrically connected to a second electrode pad ESD_LOW352.

The fourth impurity region334may be electrically floated.

The first electrode pad351may be coupled to a relatively high voltage, and the second electrode pad352may be coupled to a relatively low voltage. In some exemplary embodiments, the first electrode pad351may be coupled to a supply voltage, and the second electrode pad352may be coupled to a ground voltage. In other exemplary embodiments, the first electrode pad351may be coupled to a data input/output pin, and the second electrode pad352may be coupled to the ground voltage.

As will be described in greater detail later, when an ESD event occurs such that positive charge flows in the ESD protection device300through the first electrode pad351, the ESD protection device300may be turned on to discharge the positive charges to the second electrode pad352.

FIG. 10is a diagram illustrating a BJT parasitically formed in the ESD protection device ofFIG. 9.FIG. 11is a circuit diagram illustrating an equivalent circuit of the ESD protection device ofFIG. 9.

Referring toFIG. 10, a PNP BJT361may be parasitically formed in the ESD protection device300. An emitter of the PNP BJT361may correspond to the second impurity region332, a base of the PNP BJT361may correspond to the first well310, and a collector of the PNP BJT361may correspond to the second well320and the third impurity region333.

In addition, an NPN BJT362may be parasitically formed in the ESD protection device300. A collector of the NPN BJT362may correspond to the first impurity region331and the first well310, a base of the NPN BJT362may correspond to the second well320, and an emitter of the NPN BJT362may correspond to the fourth impurity region334.

InFIG. 10, resistance of the first well310is represented as an n-well resistor Rnw, and resistance of the second well320is represented as a p-well resistor Rpw and an equivalent circuit of the ESD protection device300ofFIG. 9may be represented as a circuit diagram ofFIG. 11.

As illustrated inFIG. 10, the fourth impurity region334, which corresponds to the emitter of the NPN BJT362, may not be electrically connected to the second electrode pad352directly but, rather, may be electrically connected to the second electrode pad352through the third impurity region333, which contacts the fourth impurity region334. The third impurity region333of p-type and the fourth impurity region334of n-type, which contact each other, may operate as a diode. As a result, as illustrated inFIG. 11, the equivalent circuit of the ESD protection device300ofFIG. 9may include a diode370coupled between the emitter of the NPN BJT362and the second electrode pad352.

Hereinafter, operation of the ESD protection device300will be described with reference toFIGS. 9 to 11.

When an ESD event occurs, positive charge may flow in the ESD protection device300through the first electrode pad351. Because the positive charge is transferred to the first well310, an electric potential of the first well310may increase as the amount of positive charge flowing in the ESD protection device300through the first electrode pad351increases. As a result, the first well310and the second well320may be in a reverse biased state. When the electric potential of the first well310increases such that an electric potential difference between the first well310and the second well320reaches a breakdown voltage, an avalanche breakdown may occur at a junction of the first well310and the second well320.

When the avalanche breakdown occurs, electron-hole pairs may be generated and holes of the electron-hole pairs may be transferred to the second well320to increase an electric potential of the second well320. When the electric potential of the second well320increases such that an electric potential difference between the second well320and the fourth impurity region334becomes greater than a threshold voltage of the NPN BJT362, the NPN BJT362may be turned on.

When the NPN BJT362is turned on, a current may flow from the first electrode pad351to the second electrode pad352through the first impurity region331, the first well310, the second well320, the fourth impurity region334, and the third impurity region333. While the current flows through the first well310, a voltage drop may occur at the first well310across the n-well resistor Rnw. As a result, the electric potential of the first well310may become lower than an electrical potential of the second impurity region332, such that the PNP BJT361may be turned on.

When the PNP BJT361is turned on, a current may flow from the first electrode pad351to the second electrode pad352through the second impurity region332, the first well310, the second well320, and the third impurity region333. While the current flows through the second well320, a voltage drop may occur at the second well320across the p-well resistor Rpw. As a result, the electric potential of the second well320may be maintained higher than an electrical potential of the fourth impurity region334, such that the NPN BJT362may be turned on more strongly.

As described above, when an ESD event occurs such that positive charge flows in the ESD protection device300through the first electrode pad351, the PNP BJT361and the NPN BJT362may be maintained in a turned on state through a positive feedback. As a result, when the ESD event occurs such that positive charge flows in the ESD protection device300through the first electrode pad351, the ESD protection device300may be turned on to discharge the positive charges to the second electrode pad352.

As described above with reference toFIGS. 10 and 11, because the ESD protection device300includes the diode370coupled between the emitter of the NPN BJT362and the second electrode pad352, a current gain of the NPN BJT362may decrease because of the diode370. As a result, a holding voltage of the ESD protection device300may increase.

FIG. 12is a cross-sectional view of an exemplary embodiment of the ESD protection device ofFIG. 9.

Referring toFIG. 12, an ESD protection device300amay include a fifth impurity region335, a sixth impurity region336, and a gate GPOLY340in addition to elements of the ESD protection device300ofFIG. 9.

The fifth impurity region P+335may be formed in the second well320, may be spaced apart from the fourth impurity region334in a direction of the first well310, and may be of p-type. In some exemplary embodiments, an impurity concentration of the fifth impurity region335may be higher than the impurity concentration of the second well320. The fifth impurity region335may be electrically floated.

The sixth impurity region P+336may be formed at a boundary region between the first well310and the second well320, may be spaced apart from the second impurity region332and the fifth impurity region335, and may be of p-type. In some exemplary embodiments, an impurity concentration of the sixth impurity region336may be higher than the impurity concentration of the second well320. The sixth impurity region336may be electrically floated.

In some exemplary embodiments, the first impurity region331and the fourth impurity region334may be formed at the same time by a same ion implantation process and, as a result, the impurity concentrations of the first impurity region331and the fourth impurity region334may be substantially the same.

In some exemplary embodiments, the second impurity region332, the third impurity region333, the fifth impurity region335, and the sixth impurity region336may be formed at the same time by a same ion implantation process and as a result, the impurity concentrations of the second impurity region332, the third impurity region333, the fifth impurity region335, and the sixth impurity region336may be substantially the same.

The gate340may be formed above the semiconductor substrate301between the second impurity region332and the sixth impurity region336. In some exemplary embodiments, the gate340may include polysilicon. The gate340may be electrically connected to the first electrode pad351.

The fifth impurity region335, the sixth impurity region336, and the gate340included in the ESD protection device300aofFIG. 12may have the same structure as the fifth impurity region135, the sixth impurity region136, and the gate140included in the ESD protection device100ofFIG. 1. As a result, effects of the fifth impurity region335, the sixth impurity region336, and the gate340on the ESD protection device300aofFIG. 12may have the same as effects of the fifth impurity region135, the sixth impurity region136, and the gate140on the ESD protection device100ofFIG. 1.

That is, as described above with reference toFIGS. 1 to 5, the sixth impurity region336and the gate340may decrease a breakdown voltage, at which an avalanche breakdown occurs at a junction of the first well310and the second well320. As a result, a triggering voltage of the ESD protection device300amay decrease.

In addition, the fifth impurity region335may decrease a current gain of the PNP BJT361and, as a result, a holding voltage of the ESD protection device300amay increase.

In addition, as a width of the fifth impurity region335increases, the current gain of the PNP BJT361may decrease such that the holding voltage of the ESD protection device300amay increase. Similarly, as the width of the fifth impurity region335decreases, the current gain of the PNP BJT361may increase such that the holding voltage of the ESD protection device300amay decrease. As a result, the holding voltage of the ESD protection device300amay be determined based on the width of the fifth impurity region335.

As described above with reference toFIGS. 9 to 12, the ESD protection device300aaccording to exemplary embodiments may have a relatively low triggering voltage and a relatively high holding voltage. In addition, the holding voltage of the ESD protection device300amay be adjusted by controlling the width of the fifth impurity region335.

FIG. 13is a cross-sectional view of an ESD protection device according to exemplary embodiments.

Referring toFIG. 13, an ESD protection device400includes a semiconductor substrate SUB401, a first well410, a second well420, a first impurity region431, a second impurity region432, a third impurity region433, and a fourth impurity region434.

The first well410is formed in the semiconductor substrate401and has a first conductivity type.

The second well420is formed in the semiconductor substrate401to contact the first well410and has a second conductivity type.

In some exemplary embodiments, the first conductivity type may correspond to p-type, and the second conductivity type may correspond to n-type. In this case, the first well410may correspond to a p-well, and the second well420may correspond to an n-well.

Hereinafter, in this exemplary embodiment the first conductivity type is assumed to be p-type, and the second conductivity type is assumed to be n-type.

The first impurity region P+431is formed in the first well410and is of p-type. In some exemplary embodiments, an impurity concentration of the first impurity region431may be higher than an impurity concentration of the first well410.

The second impurity region N+432is formed in the first well410, is spaced apart from the first impurity region431in a direction of the second well420, and is of n-type. In some exemplary embodiments, an impurity concentration of the second impurity region432may be higher than an impurity concentration of the second well420.

The third impurity region N+433is formed in the second well420and is of n-type. In some exemplary embodiments, an impurity concentration of the third impurity region433may be higher than the impurity concentration of the second well420.

The fourth impurity region P+434is formed in the second well420, is located in a direction of the first well410from the third impurity region433and contacts the third impurity region433, and is of p-type. In some exemplary embodiments, an impurity concentration of the fourth impurity region434may be higher than the impurity concentration of the first well410.

The first impurity region431and the second impurity region432may be electrically connected to a first electrode pad ESD_LOW451. The third impurity region433may be electrically connected to a second electrode pad ESD_HIGH452.

The fourth impurity region434may be electrically floated.

The first electrode pad451may be coupled to a relatively low voltage, and the second electrode pad452may be coupled to a relatively high voltage. In some exemplary embodiments, the first electrode pad451may be coupled to a ground voltage, and the second electrode pad452may be coupled to a supply voltage. In other exemplary embodiments, the first electrode pad451may be coupled to the ground voltage, and the second electrode pad452may be coupled to a data input/output pin.

As will be described in greater detail later, when an ESD event occurs such that positive charge flows in the ESD protection device400through the second electrode pad452, the ESD protection device400may be turned on to discharge the positive charge to the first electrode pad451.

FIG. 14is a diagram illustrating a BJT parasitically formed in the ESD protection device ofFIG. 13.FIG. 15is a circuit diagram illustrating an equivalent circuit of the ESD protection device ofFIG. 13.

Referring toFIG. 14, a PNP BJT461may be parasitically formed in the ESD protection device400. An emitter of the PNP BJT461may correspond to the fourth impurity region434, a base of the PNP BJT461may correspond to the second well420, and a collector of the PNP BJT461may correspond to the first well410and the first impurity region431.

Additionally, an NPN BJT462may be parasitically formed in the ESD protection device400. A collector of the NPN BJT462may correspond to the third impurity region433and the second well420, a base of the NPN BJT462may correspond to the first well410, and an emitter of the NPN BJT462may correspond to the second impurity region432.

InFIG. 14, resistance of the first well410is represented as a p-well resistor Rpw, and resistance of the second well420is represented as an n-well resistor Rnw. As a result, an equivalent circuit of the ESD protection device400ofFIG. 13may be represented as a circuit diagram ofFIG. 15.

As illustrated inFIG. 14, the fourth impurity region434, which corresponds to the emitter of the PNP BJT461, may not be electrically connected to the second electrode pad452directly but may instead be electrically connected to the second electrode pad452through the third impurity region433, which contacts the fourth impurity region434. The third impurity region433of n-type and the fourth impurity region434of p-type, which contact each other, may operate as a diode. As a result, as illustrated inFIG. 15, the equivalent circuit of the ESD protection device400ofFIG. 13may include a diode470coupled between the emitter of the PNP BJT461and the second electrode pad452.

Hereinafter, operation of an ESD protection device in accordance with principles of inventive concepts, such as the ESD protection device400, will be described with reference toFIGS. 13 to 15.

When an ESD event occurs, positive charge may flow in the ESD protection device400through the second electrode pad452. Because the positive charge is transferred to the second well420, an electric potential of the second well420may increase as the amount of positive charge flowing in the ESD protection device400through the second electrode pad452increases. As a result, the first well410and the second well420may be in a reverse biased state. When the electric potential of the second well420increases such that an electric potential difference between the first well410and the second well420reaches a breakdown voltage, an avalanche breakdown may occur at a junction of the first well410and the second well420.

When the avalanche breakdown occurs, electron-hole pairs may be generated and holes of the electron-hole pairs may be transferred to the first well410to increase an electric potential of the first well410. When the electric potential of the first well410increases such that an electric potential difference between the first well410and the second impurity region432becomes greater than a threshold voltage of the NPN BJT462, the NPN BJT462may be turned on.

When the NPN BJT462is turned on, a current may flow from the second electrode pad452to the first electrode pad451through the third impurity region433, the second well420, the first well410, and the second impurity region432. While the current flows through the second well420, a voltage drop may occur at the second well420across the n-well resistor Rnw. As a result, the electric potential of the second well420may become lower than an electrical potential of the fourth impurity region434, such that the PNP BJT461may be turned on.

When the PNP BJT461is turned on, a current may flow from the second electrode pad452to the first electrode pad451through the third impurity region433, the fourth impurity region434, the second well420, the first well410, and the first impurity region431. While the current flows through the first well410, a voltage drop may occur at the first well410by the p-well resistor Rpw. As a result, the electric potential of the first well410may be maintained higher than an electrical potential of the second impurity region432, such that the NPN BJT462may be turned on more strongly.

As described above, when an ESD event occurs such that positive charge flow in the ESD protection device400through the second electrode pad452, the PNP BJT461and the NPN BJT462may be maintained in a turned on state through positive feedback. As a result, when the ESD event occurs such that positive charge flow in the ESD protection device400through the second electrode pad452, the ESD protection device400may be turned on to discharge the positive charge to the first electrode pad451.

As described above with reference toFIGS. 14 and 15, because the ESD protection device400includes the diode470coupled between the emitter of the PNP BJT461and the second electrode pad452, a current gain of the PNP BJT461may decrease because of the diode470and, as a result, a holding voltage of the ESD protection device400may increase.

FIG. 16is a cross-sectional view of an exemplary embodiment of the ESD protection device ofFIG. 13.

Referring toFIG. 16, an ESD protection device400amay further include a fifth impurity region435, a sixth impurity region436, and a gate GPOLY440from the ESD protection device400ofFIG. 13.

The fifth impurity region N+435may be formed in the second well420, may be spaced apart from the fourth impurity region434in a direction of the first well410, and may be of n-type. In some exemplary embodiments, an impurity concentration of the fifth impurity region435may be higher than the impurity concentration of the second well420. The fifth impurity region435may be electrically floated.

The sixth impurity region N+436may be formed at a boundary region between the first well410and the second well420, may be spaced apart from the second impurity region432and the fifth impurity region435, and may be of n-type. In some exemplary embodiments, an impurity concentration of the sixth impurity region436may be higher than the impurity concentration of the second well420. The sixth impurity region436may be electrically floated.

In some exemplary embodiments, the first impurity region431and the fourth impurity region434may be formed at the same time by a same ion implantation process and, as a result, the impurity concentrations of the first impurity region431and the fourth impurity region434may be substantially the same.

In some exemplary embodiments, the second impurity region432, the third impurity region433, the fifth impurity region435, and the sixth impurity region436may be formed at the same time by a same ion implantation process and, as a result, the impurity concentrations of the second impurity region432, the third impurity region433, the fifth impurity region435, and the sixth impurity region436may be substantially the same.

The gate440may be formed above the semiconductor substrate401between the second impurity region432and the sixth impurity region436. In some exemplary embodiments, the gate440may include polysilicon. The gate440may be electrically connected to the first electrode pad451.

The fifth impurity region435, the sixth impurity region436, and the gate440included in the ESD protection device400aofFIG. 16may have the same structure as the fifth impurity region235, the sixth impurity region236, and the gate240included in the ESD protection device200ofFIG. 6. As a result, effects of the fifth impurity region435, the sixth impurity region436, and the gate440on the ESD protection device400aofFIG. 16may have the same as effects as those of the fifth impurity region235, the sixth impurity region236, and the gate240on the ESD protection device200ofFIG. 6.

That is, as described above with reference toFIGS. 6 to 8, the sixth impurity region436and the gate440may decrease a breakdown voltage, at which an avalanche breakdown occurs at a junction of the first well410and the second well420and, consequently, a triggering voltage of the ESD protection device400amay decrease.

In addition, the fifth impurity region435may decrease a current gain of the NPN BJT462and, consequently, a holding voltage of the ESD protection device400amay increase.

In addition, as a width of the fifth impurity region435increases, the current gain of the NPN BJT462may decrease such that the holding voltage of the ESD protection device400amay increase. Similarly, as the width of the fifth impurity region435decreases, the current gain of the NPN BJT462may increase such that the holding voltage of the ESD protection device400amay decrease. As a result, the holding voltage of the ESD protection device400amay be determined based on the width of the fifth impurity region435.

As described above with reference toFIGS. 13 to 16, the ESD protection device400aaccording to exemplary embodiments may have a relatively low triggering voltage and a relatively high holding voltage. In addition, the holding voltage of the ESD protection device400amay be adjusted by controlling the width of the fifth impurity region435.

FIG. 17is a cross-sectional view of an ESD protection device according to exemplary embodiments.

Referring toFIG. 17, an ESD protection device500includes a semiconductor substrate SUB501, a first well510, a second well520, a first impurity region531, a second impurity region532, a third impurity region533, and a fourth impurity region534.

The first well510is formed in the semiconductor substrate501and has a first conductivity type.

The second well520is formed in the semiconductor substrate501to contact the first well510and has a second conductivity type.

In some exemplary embodiments, the first conductivity type may correspond to p-type, and the second conductivity type may correspond to n-type. In such exemplary embodiments, the first well510may correspond to a p-well, and the second well520may correspond to an n-well.

Hereinafter, in this exemplary embodiment, the first conductivity type is assumed to be p-type, and the second conductivity type is assumed to be n-type.

The first impurity region P+531is formed in the first well510and is of p-type. In some exemplary embodiments, an impurity concentration of the first impurity region531may be higher than an impurity concentration of the first well510.

The second impurity region N+532is formed in the first well510, is spaced apart from the first impurity region531in a direction of the second well520, and is of n-type. In some exemplary embodiments, an impurity concentration of the second impurity region532may be higher than an impurity concentration of the second well520.

The third impurity region N+533is formed in the second well520and is of n-type. In some exemplary embodiments, an impurity concentration of the third impurity region533may be higher than the impurity concentration of the second well520.

The fourth impurity region P+534is formed in the second well520, is located in a direction of the first well510from the third impurity region533and contacts the third impurity region533, and is of p-type. In some exemplary embodiments, an impurity concentration of the fourth impurity region534may be higher than the impurity concentration of the first well510.

The first impurity region531and the second impurity region532may be electrically connected to a first electrode pad ESD_LOW551. The third impurity region533may be electrically connected to a second electrode pad ESD_HIGH552.

The fourth impurity region534may be electrically floated.

The first electrode pad551may be coupled to a relatively low voltage, and the second electrode pad552may be coupled to a relatively high voltage. In some exemplary embodiments, the first electrode pad551may be coupled to a ground voltage, and the second electrode pad552may be coupled to a supply voltage. In other exemplary embodiments, the first electrode pad551may be coupled to the ground voltage, and the second electrode pad552may be coupled to a data input/output pin.

As will be described in greater detail later, when an ESD event occurs such that positive charge flows in the ESD protection device500through the second electrode pad552, the ESD protection device500may be turned on to discharge the positive charges to the first electrode pad551.

FIG. 18is a diagram illustrating a BJT parasitically formed in the ESD protection device ofFIG. 17.FIG. 19is a circuit diagram illustrating an equivalent circuit of the ESD protection device ofFIG. 17.

Referring toFIG. 18, a PNP BJT561may be parasitically formed in the ESD protection device500. An emitter of the PNP BJT561may correspond to the fourth impurity region534, a base of the PNP BJT561may correspond to the second well520, and a collector of the PNP BJT561may correspond to the first well510and the first impurity region531.

In addition, an NPN BJT562may be parasitically formed in the ESD protection device500. A collector of the NPN BJT562may correspond to the third impurity region533and the second well520, a base of the NPN BJT562may correspond to the first well510, and an emitter of the NPN BJT562may correspond to the second impurity region532.

InFIG. 18, resistance of the first well510is represented as a p-well resistor Rpw, and resistance of the second well520is represented as an n-well resistor Rnw. An equivalent circuit of the ESD protection device500ofFIG. 17may be represented as a circuit diagram ofFIG. 19.

As illustrated inFIG. 18, the fourth impurity region534, which corresponds to the emitter of the PNP BJT561, may not be electrically connected to the second electrode pad552directly, but may instead be electrically connected to the second electrode pad552through the third impurity region533, which contacts the fourth impurity region534. The third impurity region533of n-type and the fourth impurity region534of p-type, which contact each other, may operate as a diode. As a result, as illustrated inFIG. 19, the equivalent circuit of the ESD protection device500ofFIG. 17may include a diode570coupled between the emitter of the PNP BJT561and the second electrode pad552.

Hereinafter, operation of an ESD protection device in accordance with principles of inventive concepts, such as ESD protection device500will be described with reference toFIGS. 17 to 19.

When an ESD event occurs, positive charge may flow in the ESD protection device500through the second electrode pad552. Because the positive charge is transferred to the second well520, an electric potential of the second well520may increase as an amount of the positive charges flowing in the ESD protection device500through the second electrode pad552increases. As a result, the first well510and the second well520may be in a reverse biased state. When the electric potential of the second well520increases such that an electric potential difference between the first well510and the second well520reaches a breakdown voltage, an avalanche breakdown may occur at a junction of the first well510and the second well520.

When the avalanche breakdown occurs, electron-hole pairs may be generated and holes of the electron-hole pairs may be transferred to the first well510to increase an electric potential of the first well510. When the electric potential of the first well510increases such that an electric potential difference between the first well510and the second impurity region532becomes greater than a threshold voltage of the NPN BJT562, the NPN BJT562may be turned on.

When the NPN BJT562is turned on, current may flow from the second electrode pad552to the first electrode pad551through the third impurity region533, the second well520, the first well510, and the second impurity region532. While the current flows through the second well520, a voltage drop may occur at the second well520across the n-well resistor Rnw. As a result, the electric potential of the second well520may become lower than an electrical potential of the fourth impurity region534, such that the PNP BJT561may be turned on.

When the PNP BJT561is turned on, a current may flow from the second electrode pad552to the first electrode pad551through the third impurity region533, the fourth impurity region534, the second well520, the first well510, and the first impurity region531. While the current flows through the first well510, a voltage drop may occur at the first well510across the p-well resistor Rpw. As a result, the electric potential of the first well510may be maintained higher than an electrical potential of the second impurity region532, such that the NPN BJT562may be turned on more strongly.

As described above, when an ESD event occurs such that positive charge flow in the ESD protection device500through the second electrode pad552, the PNP BJT561and the NPN BJT562may be maintained in a turned on state through positive feedback. As a result, when the ESD event occurs such that positive charge flow in the ESD protection device500through the second electrode pad552, the ESD protection device500may be turned on to discharge the positive charges to the first electrode pad551.

As described above with reference toFIGS. 18 and 19, because the ESD protection device500includes the diode570coupled between the emitter of the PNP BJT561and the second electrode pad552, a current gain of the PNP BJT561may decrease because of the diode570and, as a result, a holding voltage of the ESD protection device500may increase.

FIG. 20is a cross-sectional view of an exemplary embodiment of an ESD protection device in accordance with principles of inventive concepts, such as that ofFIG. 17.

Referring toFIG. 20, an ESD protection device such as device500amay further include a fifth impurity region535, a sixth impurity region536, and a gate GPOLY540from the ESD protection device500ofFIG. 17.

The fifth impurity region P+535may be formed in the first well510, may be spaced apart from the second impurity region532in a direction of the second well520, and may be of p-type. In some exemplary embodiments, an impurity concentration of the fifth impurity region535may be higher than the impurity concentration of the first well510. The fifth impurity region535may be electrically floated.

The sixth impurity region P+536may be formed at a boundary region between the first well510and the second well520, may be spaced apart from the fourth impurity region534and the fifth impurity region535, and may be of p-type. In some exemplary embodiments, an impurity concentration of the sixth impurity region536may be higher than the impurity concentration of the first well510. The sixth impurity region536may be electrically floated.

In some exemplary embodiments, the second impurity region532and the third impurity region533may be formed at the same time by a same ion implantation process and, as a result, the impurity concentrations of the second impurity region532and the third impurity region533may be substantially the same.

In some exemplary embodiments, the first impurity region531, the fourth impurity region534, the fifth impurity region535, and the sixth impurity region536may be formed at the same time by a same ion implantation process and, as a result, the impurity concentrations of the first impurity region531, the fourth impurity region534, the fifth impurity region535, and the sixth impurity region536may be substantially the same.

The gate540may be formed above the semiconductor substrate501between the fourth impurity region534and the sixth impurity region536. In some exemplary embodiments, the gate540may include polysilicon. The gate540may be electrically connected to the second electrode pad552.

The fifth impurity region535, the sixth impurity region536, and the gate540included in the ESD protection device500aofFIG. 20may have the same structure as the fifth impurity region135, the sixth impurity region136, and the gate140included in the ESD protection device100ofFIG. 1. As a result, effects of the fifth impurity region535, the sixth impurity region536, and the gate540on the ESD protection device500aofFIG. 20may have the same as effects as those of the fifth impurity region135, the sixth impurity region136, and the gate140on the ESD protection device100ofFIG. 1.

That is, as described above with reference toFIGS. 1 to 5, the sixth impurity region536and the gate540may decrease a breakdown voltage, at which an avalanche breakdown occurs at a junction of the first well510and the second well520. As a result, a triggering voltage of the ESD protection device500amay decrease.

In addition, the fifth impurity region535may decrease a current gain of the PNP BJT561. As a result, a holding voltage of the ESD protection device500amay increase.

In addition, as a width of the fifth impurity region535increases, the current gain of the PNP BJT561may decrease such that the holding voltage of the ESD protection device500amay increase. Similarly, as the width of the fifth impurity region535decreases, the current gain of the PNP BJT561may increase such that the holding voltage of the ESD protection device500amay decrease. As a result, the holding voltage of the ESD protection device500amay be determined based on the width of the fifth impurity region535.

As described above with reference toFIGS. 17 to 20, the ESD protection device500aaccording to exemplary embodiments may have a relatively low triggering voltage and a relatively high holding voltage. In addition, the holding voltage of the ESD protection device500amay be adjusted by controlling the width of the fifth impurity region535.

FIG. 21is a cross-sectional view an exemplary embodiment of an ESD protection device in accordance with principles of inventive concepts.

Referring toFIG. 21, an ESD protection device600includes a semiconductor substrate SUB601, a first well610, a second well620, a first impurity region631, a second impurity region632, a third impurity region633, and a fourth impurity region634.

The first well610is formed in the semiconductor substrate601and has a first conductivity type.

The second well620is formed in the semiconductor substrate601to contact the first well610and has a second conductivity type.

In some exemplary embodiments, the first conductivity type may correspond to n-type, and the second conductivity type may correspond to p-type. In such embodiments, the first well610may correspond to an n-well, and the second well620may correspond to a p-well.

Hereinafter, in this exemplary embodiment the first conductivity type is assumed to be n-type, and the second conductivity type is assumed to be p-type.

The first impurity region N+631is formed in the first well610and is of n-type. In some exemplary embodiments, an impurity concentration of the first impurity region631may be higher than an impurity concentration of the first well610.

The second impurity region P+632is formed in the first well610, is spaced apart from the first impurity region631in a direction of the second well620, and is of p-type. In some exemplary embodiments, an impurity concentration of the second impurity region632may be higher than an impurity concentration of the second well620.

The third impurity region P+633is formed in the second well620and is of p-type. In some exemplary embodiments, an impurity concentration of the third impurity region633may be higher than the impurity concentration of the second well620.

The fourth impurity region N+634is formed in the second well620, is located in a direction of the first well610from the third impurity region633and contacts the third impurity region633, and is of n-type. In some exemplary embodiments, an impurity concentration of the fourth impurity region634may be higher than the impurity concentration of the first well610.

The first impurity region631and the second impurity region632may be electrically connected to a first electrode pad ESD_HIGH651. The third impurity region633may be electrically connected to a second electrode pad ESD_LOW652.

The fourth impurity region634may be electrically floated.

The first electrode pad651may be coupled to a relatively high voltage, and the second electrode pad652may be coupled to a relatively low voltage. In some exemplary embodiments, the first electrode pad651may be coupled to a supply voltage, and the second electrode pad652may be coupled to a ground voltage. In other exemplary embodiments, the first electrode pad651may be coupled to a data input/output pin, and the second electrode pad652may be coupled to the ground voltage.

As will be described in greater detail later, when an ESD event occurs such that positive charge flows in the ESD protection device600through the first electrode pad651, the ESD protection device600may be turned on to discharge the positive charges to the second electrode pad652.

FIG. 22is a diagram illustrating a BJT parasitically formed in the ESD protection device ofFIG. 21.FIG. 23is a circuit diagram illustrating an equivalent circuit of the ESD protection device ofFIG. 21.

Referring toFIG. 22, a PNP BJT661may be parasitically formed in the ESD protection device600. An emitter of the PNP BJT661may correspond to the second impurity region632, a base of the PNP BJT661may correspond to the first well610, and a collector of the PNP BJT661may correspond to the second well620and the third impurity region633.

In addition, an NPN BJT662may be parasitically formed in the ESD protection device600. A collector of the NPN BJT662may correspond to the first impurity region631and the first well610, a base of the NPN BJT662may correspond to the second well620, and an emitter of the NPN BJT662may correspond to the fourth impurity region634.

InFIG. 22, resistance of the first well610is represented as an n-well resistor Rnw, and resistance of the second well620is represented as a p-well resistor Rpw.

As a result, an equivalent circuit of the ESD protection device600ofFIG. 21may be represented as a circuit diagram ofFIG. 23.

As illustrated inFIG. 22, the fourth impurity region634, which corresponds to the emitter of the NPN BJT662, may not be electrically connected to the second electrode pad652directly but, rather, may be electrically connected to the second electrode pad652through the third impurity region633, which contacts the fourth impurity region634. The third impurity region633of p-type and the fourth impurity region634of n-type, which contact each other, may operate as a diode. As a result, as illustrated inFIG. 23, the equivalent circuit of the ESD protection device600ofFIG. 21may include a diode670coupled between the emitter of the NPN BJT662and the second electrode pad652.

Hereinafter, operation of the ESD protection device600will be described with reference toFIGS. 21 to 23.

When an ESD event occurs, positive charge may flow in the ESD protection device600through the first electrode pad651. Because positive charge is transferred to the first well610, an electric potential of the first well610may increase as an amount of positive charge flowing in the ESD protection device600through the first electrode pad651increases. As a result, the first well610and the second well620may be in a reverse biased state. When the electric potential of the first well610increases such that an electric potential difference between the first well610and the second well620reaches a breakdown voltage, an avalanche breakdown may occur at a junction of the first well610and the second well620.

When the avalanche breakdown occurs, electron-hole pairs may be generated and holes of the electron-hole pairs may be transferred to the second well620to increase an electric potential of the second well620. When the electric potential of the second well620increases such that an electric potential difference between the second well620and the fourth impurity region634becomes greater than a threshold voltage of the NPN BJT662, the NPN BJT662may be turned on.

When the NPN BJT662is turned on, a current may flow from the first electrode pad651to the second electrode pad652through the first impurity region631, the first well610, the second well620, the fourth impurity region634, and the third impurity region633. While the current flows through the first well610, a voltage drop may occur at the first well610across the n-well resistor Rnw. As a result, the electric potential of the first well610may become lower than an electrical potential of the second impurity region632, such that the PNP BJT661may be turned on.

When the PNP BJT661is turned on, a current may flow from the first electrode pad651to the second electrode pad652through the second impurity region632, the first well610, the second well620, and the third impurity region633. While the current flows through the second well620, a voltage drop may occur at the second well620across the p-well resistor Rpw. As a result, the electric potential of the second well620may be maintained higher than an electrical potential of the fourth impurity region634, such that the NPN BJT662may be turned on more strongly.

As described above, when an ESD event occurs such that positive charge flows in the ESD protection device600through the first electrode pad651, the PNP BJT661and the NPN BJT662may be maintained in a turned on state through a positive feedback. As a result, when the ESD event occurs such that positive charge flow in the ESD protection device600through the first electrode pad651, the ESD protection device600may be turned on to discharge the positive charges to the second electrode pad652.

As described above with reference toFIGS. 22 and 23, because the ESD protection device600includes the diode670coupled between the emitter of the NPN BJT662and the second electrode pad652, a current gain of the NPN BJT662may decrease because of the diode670and, as a result, a holding voltage of the ESD protection device600may increase.

FIG. 24is a cross-sectional view of an exemplary of the ESD protection device ofFIG. 21.

Referring toFIG. 24, an ESD protection device600amay further include a fifth impurity region635, a sixth impurity region636, and a gate GPOLY640from the ESD protection device600ofFIG. 21.

The fifth impurity region N+635may be formed in the first well610, may be spaced apart from the second impurity region632in a direction of the second well620, and may be of n-type. In some exemplary embodiments, an impurity concentration of the fifth impurity region635may be higher than the impurity concentration of the first well610. The fifth impurity region635may be electrically floated.

The sixth impurity region N+636may be formed at a boundary region between the first well610and the second well620, may be spaced apart from the fourth impurity region634and the fifth impurity region635, and may be of n-type. In some exemplary embodiments, an impurity concentration of the sixth impurity region636may be higher than the impurity concentration of the first well610. The sixth impurity region636may be electrically floated.

In some exemplary embodiments, the second impurity region632and the third impurity region633may be formed at the same time by a same ion implantation process and, as a result, the impurity concentrations of the second impurity region632and the third impurity region633may be substantially the same.

In some exemplary embodiments, the first impurity region631, the fourth impurity region634, the fifth impurity region635, and the sixth impurity region636may be formed at the same time by a same ion implantation process and, as a result, the impurity concentrations of the first impurity region631, the fourth impurity region634, the fifth impurity region635, and the sixth impurity region636may be substantially the same.

The gate640may be formed above the semiconductor substrate601between the fourth impurity region634and the sixth impurity region636. In some exemplary embodiments, the gate640may include polysilicon. The gate640may be electrically connected to the second electrode pad652.

The fifth impurity region635, the sixth impurity region636, and the gate640included in the ESD protection device600aofFIG. 24may have the same structure as the fifth impurity region235, the sixth impurity region236, and the gate240included in the ESD protection device200ofFIG. 6. As a result, effects of the fifth impurity region635, the sixth impurity region636, and the gate640on the ESD protection device600aofFIG. 24may be the same as effects of the fifth impurity region235, the sixth impurity region236, and the gate240on the ESD protection device200ofFIG. 6.

That is, as described above with reference toFIGS. 6 to 8, the sixth impurity region636and the gate640may decrease a breakdown voltage, at which an avalanche breakdown occurs at a junction of the first well610and the second well620and, as a result, a triggering voltage of the ESD protection device600amay decrease.

In addition, the fifth impurity region635may decrease a current gain of the NPN BJT662and, as a result, a holding voltage of the ESD protection device600amay increase.

In addition, as a width of the fifth impurity region635increases, the current gain of the NPN BJT662may decrease such that the holding voltage of the ESD protection device600amay increase. Similarly, as the width of the fifth impurity region635decreases, the current gain of the NPN BJT662may increase such that the holding voltage of the ESD protection device600amay decrease. As a result, the holding voltage of the ESD protection device600amay be determined based on the width of the fifth impurity region635.

As described above with reference toFIGS. 21 to 24, the ESD protection device600aaccording to exemplary embodiments may have a relatively low triggering voltage and a relatively high holding voltage. In addition, the holding voltage of the ESD protection device600amay be adjusted by controlling the width of the fifth impurity region635.

FIG. 25is a block diagram illustrating an electronic device according to exemplary embodiments.

Referring toFIG. 25, an electronic device700includes a functional block710and an ESD protection device720.

The functional block710is coupled between a supply voltage pad VDD_P, which is coupled to a supply voltage VDD, and a ground voltage pad GND_P, which is coupled to a ground voltage GND. The functional block710operates using the supply voltage VDD. In some exemplary embodiments, the functional block710may include at least one of an application processor, a data input/output circuit, a logic circuit, and a memory device.

The ESD protection device720is coupled between the supply voltage pad VDD_P and the ground voltage pad GND_P. When an ESD event occurs such that positive charge flow in the ESD protection device720through the supply voltage pad VDD_P, the ESD protection device720may be turned on to discharge the positive charges to the ground voltage pad GND_P.

The ESD protection device720may be implemented with an ESD protection device in accordance with principles of inventive concepts, such as one of the exemplary ESD protection devices,100ofFIG. 1, the ESD protection device200ofFIG. 6, the ESD protection device300ofFIG. 9, the ESD protection device400ofFIG. 13, the ESD protection device500ofFIG. 17, and the ESD protection device600ofFIG. 21.

When the ESD protection device720is implemented with an ESD protection device in accordance with principles of inventive concepts, such as one of the ESD protection device100ofFIG. 1, the ESD protection device300ofFIG. 9, and the ESD protection device600ofFIG. 21, the first electrode pad151,351, and651of the ESD protection device100, the ESD protection device300, and the ESD protection device600may correspond to the supply voltage pad VDD_P and the second electrode pad152,352, and652of the ESD protection device100, the ESD protection device300, and the ESD protection device600may correspond to the ground voltage pad GND_P.

When the ESD protection device720is implemented with an ESD protection device in accordance with principles of inventive concepts, such as one of the ESD protection device200ofFIG. 6, the ESD protection device400ofFIG. 13, and the ESD protection device500ofFIG. 17, the first electrode pad251,451, and551of the ESD protection device200, the ESD protection device400, and the ESD protection device500may correspond to the ground voltage pad GND_P and the second electrode pad252,452, and552of the ESD protection device200, the ESD protection device400, and the ESD protection device500may correspond to the supply voltage pad VDD_P.

Structures and operations of the ESD protection device100ofFIG. 1, the ESD protection device200ofFIG. 6, the ESD protection device300ofFIG. 9, the ESD protection device400ofFIG. 13, the ESD protection device500ofFIG. 17, and the ESD protection device600ofFIG. 21are described above with reference toFIGS. 1 to 24. As a result, detailed description about the ESD protection device720will not be repeated here.

In some exemplary embodiments, the electronic device700may be portable electronic device, such as a smart phone, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, a laptop computer, etc.

FIG. 26is a block diagram illustrating an electronic device according to exemplary embodiments.

Referring toFIG. 26, an electronic device800includes a functional block810and an ESD protection device820.

The functional block810is coupled to a supply voltage pad VDD_P, which is coupled to a supply voltage VDD, a ground voltage pad GND_P, which is coupled to a ground voltage GND, and a data input/output pad I/O_P. The functional block810communicates data DQ through the data input/output pad I/O_P using the supply voltage VDD. In some exemplary embodiments, the functional block810may include at least one of an application processor, a data input/output circuit, a logic circuit, and a memory device.

The ESD protection device820is coupled between the data input/output pad I/O_P and the ground voltage pad GND_P. When an ESD event occurs such that positive charge flow in the ESD protection device820through the data input/output pad I/O_P, the ESD protection device820may be turned on to discharge the positive charges to the ground voltage pad GND_P.

The ESD protection device820in accordance with principles of inventive concepts may be implemented with one of the exemplary ESD protection device100ofFIG. 1, the ESD protection device200ofFIG. 6, the ESD protection device300ofFIG. 9, the ESD protection device400ofFIG. 13, the ESD protection device500ofFIG. 17, and the ESD protection device600ofFIG. 21, for example.

When the ESD protection device820in accordance with principles of inventive concepts is implemented with one of the exemplary ESD protection device100ofFIG. 1, the ESD protection device300ofFIG. 9, and the ESD protection device600ofFIG. 21, the first electrode pad151,351, and651of the ESD protection device100, the ESD protection device300, and the ESD protection device600may correspond to the data input/output pad I/O_P and the second electrode pad152,352, and652of the ESD protection device100, the ESD protection device300, and the ESD protection device600may correspond to the ground voltage pad GND_P.

When the ESD protection device820in accordance with principles of inventive concepts is implemented with one of the exemplary ESD protection device200ofFIG. 6, the ESD protection device400ofFIG. 13, and the ESD protection device500ofFIG. 17, the first electrode pad251,451, and551of the ESD protection device200, the ESD protection device400, and the ESD protection device500may correspond to the ground voltage pad GND_P and the second electrode pad252,452, and552of the ESD protection device200, the ESD protection device400, and the ESD protection device500may correspond to the data input/output pad I/O_P.

Structures and operations of the ESD protection device100ofFIG. 1, the ESD protection device200ofFIG. 6, the ESD protection device300ofFIG. 9, the ESD protection device400ofFIG. 13, the ESD protection device500ofFIG. 17, and the ESD protection device600ofFIG. 21are described above with reference toFIGS. 1 to 24. As a result, detailed description of the ESD protection device820will not be repeated here.

In some exemplary embodiments, the electronic device800may be a portable electronic device, such as a smart phone, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, a laptop computer, etc.

The foregoing is illustrative of inventive concepts and is not to be construed as limiting thereof. Although exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of inventive concepts. Accordingly, all such modifications are intended to be included within the scope of inventive concepts as defined in the claims. As a result, it is to be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limited to the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims.