Methods of forming graphene contacts on source/drain regions of FinFET devices

One illustrative method disclosed herein includes forming a gate structure above a portion of a fin and performing a first epitaxial growth process to form a silicon-carbide (SiC) semiconductor material above the fin in the source and drain regions of a FinFET device. In this example, the method also includes performing a heating process so as to form a source/drain graphene contact from the silicon-carbide (SiC) semiconductor material in both the source and drain regions of the FinFET device and forming first and second source/drain contact structures that are conductively coupled to the source/drain graphene contact in the source region and the drain region, respectively, of the FinFET device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to the manufacturing of semiconductor devices, and, more specifically, to various methods of forming graphene contacts on source/drain regions of FinFET devices, and the resulting FinFET device structures.

2. Description of the Related Art

In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each transistor device comprises laterally spaced apart drain and source regions that are formed in a semiconductor substrate, a gate electrode structure positioned above the substrate and between the source/drain regions, and a gate insulation layer positioned between the gate electrode and the substrate. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region and current flows from the source region to the drain region.

A conventional FET is a planar device. To improve the operating speed of planar FETs, and to increase the density of planar FETs on an integrated circuit product, device designers have greatly reduced the physical size of planar FETs over the past decades. More specifically, the channel length of planar FETs has been significantly decreased, which has resulted in improving the switching speed and in lowering operation currents and voltages of planar FETs. However, decreasing the channel length of a planar FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the planar FET as an active switch is degraded.

FIG. 1Ais a perspective view of an illustrative prior art FinFET semiconductor device10that is formed above a semiconductor substrate12at an intermediate point during fabrication. In this example, the FinFET device10includes three illustrative fins14, an isolation material15(e.g., silicon dioxide), a simplistically depicted gate structure16, a sidewall spacer18and a gate cap layer20. The gate structure16is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device10. The gate structure16may be formed using either so-called “gate last” or “replacement gate” manufacturing techniques. The fins14have a three-dimensional configuration: a height H, a width W and an axial length L. The direction of current travel when the device10is operational, i.e., the gate length (GL) of the device10, corresponds to the direction of the axial length L of the fins14. The portions of the fins14covered by the gate structure16are the channel regions of the FinFET device10, while the portions of the fins14positioned laterally outside of the spacers18are part of the source/drain regions of the device10. Although not depicted, the portions of the fins14in the source/drain regions may have additional epi semiconductor material formed thereon.

FIG. 1Bis a perspective view of yet another illustrative prior art FinFET semiconductor device10A that is formed above a semiconductor substrate30. In this example, the FinFET device10A includes three illustrative fins32, an isolation material34, a simplistically depicted gate structure36, a sidewall spacer38and a gate hard mask40. The fins32have a three-dimensional configuration: a height H, a width W and an axial length L. In this example, the fins32are comprised of a substrate fin portion32A and an alternative fin material portion32B, e.g., SiGe, SiC, etc. The substrate fin portion32A may be made of silicon, i.e., the same material as the substrate30, and the alternative fin material portion32B may be made of a material other than the substrate material, such as, for example, a compressively stressed silicon-germanium material for a PFET device or a tensile stressed silicon-carbide material for an NFET device. Such alternative materials are formed in an effort to increase the current carrying capabilities of the FinFET devices.

Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to increase the drive current per footprint of the device. Also, in a FinFET, the improved gate control through multiple gates on a narrow, fully-depleted semiconductor fin significantly reduces the short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins14,32, i.e., the vertically oriented sidewalls and the top upper surface of the fin (for a tri-gate device), form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device with a single fin, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.

Over recent years, due to the improvements in the performance of transistor devices, one limiting factor relating to the operating speed of the final integrated circuit product is no longer the individual transistor elements but the electrical performance of the complex wiring system that is formed above the device level that includes the actual semiconductor-based circuit elements. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements or “wiring” for the circuits cannot be formed or positioned at the same level that contains the actual circuit elements such as transistors. Rather, the electrical wiring for the integrated circuit products is comprised of several metallization layers positioned over the device level. Such metallization layers generally include metal-containing lines providing the intra-level electrical connections, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.

Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, a first end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end that is connected to a respective metal line in the metallization layer by a conductive via. Such vertical contact structures are considered to be “device-level” contacts or simply “contacts” within the industry, as they contact the “device” that is formed in the silicon substrate. The contact structures may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. In other applications, the contact structures may be line-type features, e.g., source/drain contact structures.

Another problem with continued scaling of transistor devices is that the electrical resistance between the conductive device-level contacts and the transistor element is becoming a larger portion of the overall electrical resistance. Traditionally, metal silicide layers or regions are formed in the source/drain regions of a device and on the gate electrode of a device in order to reduce electrical contact resistance where contact will be made by a device level contact. The typical steps performed to form metal silicide regions are: (1) depositing a layer of refractory metal (e.g., nickel, platinum, etc.); (2) performing an initial heating process causing the refractory metal to react with underlying silicon-containing material; (3) performing an etching process to remove unreacted portions of the layer of refractory metal; and (4) performing an additional heating process to form the final phase of the metal silicide. In other cases, a metal silicide region may be formed by depositing a thin liner of metal, such as Ti or NiPt, depositing a TiN barrier on the liner and depositing a low-resistance conducting metal, such as W, on the barrier. The silicide is formed between the liner and conducting metal during the thermal process that occurs when the conducting metal is deposited. As such, no additional refractory metal stripping process is needed.

Ideally, the contact area between the metal silicide layer or region and the underlying silicon or epi semiconductor material (in the source/drain region) could simply be increased. In the case of FinFET devices that have additional epi semiconductor material formed on the fins in the source/drain regions of the device, this could theoretically be accomplished by forming the additional epi material on the fins in an un-merged condition, i.e., a situation where there is no contact between additional epi material on adjacent fins, and thereafter forming an individual metal silicide layer that wraps around each of the separated epi materials. In practice, this is a very difficult task for several reasons. First, when epi semiconductor material is grown on a fin, it is very difficult to control the thickness of the epi semiconductor material. Thus, the epi material may unintentionally be merged together, thereby preventing the formation of the wrap-around metal silicide layers. One possible solution to avoid such unintended fin merger would be to form the epi material on the fin to a very small thickness to virtually assure that unintended fin merger does not occur. The drawbacks to this approach are that such a very small volume of epi material will tend to increase the overall resistance and such a thin layer of epi material may be substantially consumed by the metal silicide material and/or damaged during the contact formation process.

The present disclosure is directed to various methods of forming graphene contacts on source/drain regions of FinFET devices, and the resulting FinFET device structures, that may solve or reduce one or more of the problems identified above.

SUMMARY OF THE INVENTION

Generally, the present disclosure is directed to various methods of forming graphene contacts on source/drain regions of FinFET devices, and the resulting FinFET device structures. One illustrative method disclosed herein includes, among other things, forming a FinFET device by forming a fin in a semiconductor substrate comprised of a first semiconductor material, forming a gate structure above a portion of the fin and performing a first epitaxial growth process to form a silicon-carbide (SiC) semiconductor material above the fin in the source and drain regions of the FinFET device, the silicon-carbide semiconductor material being a different semiconductor material than the first semiconductor material of the substrate. In this example, the method also includes performing a heating process so as to form a source/drain graphene contact from the silicon-carbide semiconductor material in both the source and drain regions of the FinFET device and forming first and second source/drain contact structures that are conductively coupled to the source/drain graphene contact in the source region and the drain region, respectively, of the FinFET device.

Another illustrative method disclosed herein includes, among other things, forming a FinFET device by forming a fin in a substrate comprised of a first semiconductor material, forming a gate structure above a portion of the fin, performing a first epitaxial growth process to form a source/drain epi semiconductor material on the fin, wherein the source/drain epi semiconductor material is different from the first semiconductor material of the substrate, and performing a second epitaxial growth process to form a silicon-carbide (SiC) semiconductor material above the source/drain epi semiconductor material in the source and drain regions of the FinFET device, the silicon-carbide (SiC) semiconductor material being different than the first semiconductor material of the substrate. In this example, the method further includes performing a heating process so as to form a source/drain graphene contact from the silicon-carbide (SiC) semiconductor material in both the source and drain regions of the FinFET device and forming first and second source/drain contact structures that are conductively coupled to the source/drain graphene contact in the source region and the drain region, respectively, of the FinFET device.

One illustrative method disclosed herein for forming a CMOS integrated circuit product comprised of a PMOS FinFET device and an NMOS FinFET includes, among other things, forming first and second fins in a substrate comprised of a first semiconductor material, the first and second fins being formed for the PMOS FinFET device and the NMOS FinFET device, respectively, forming first and second gate structures above a portion of the first and second fins, respectively, forming a first source/drain epi semiconductor material on the first fin in the source and drain regions of the PMOS FinFET device, wherein the first source/drain epi semiconductor material is different from the first semiconductor material of the substrate, and forming a second source/drain epi semiconductor material on the second fin in the source and drain regions of the NMOS FinFET device, wherein the second source/drain epi semiconductor material is different from the first and the first source/drain epi semiconductor materials. In this example, the method also includes forming a silicon-carbide (SiC) semiconductor material on and in contact with the first source/drain epi semiconductor material in the source and drain regions of the PMOS FinFET device and on and in contact with the second source/drain epi semiconductor material in the source and drain regions of the NMOS device, the silicon-carbide (SiC) semiconductor material being different than the first semiconductor material of the substrate, performing a heating process so as to form a source/drain graphene contact from the silicon-carbide (SiC) semiconductor material in both the source and drain regions of both the PMOS and NMOS FinFET devices, and forming a plurality of source/drain contact structures, each of which is conductively coupled to one of the source/drain graphene contacts.

DETAILED DESCRIPTION

The present disclosure is directed to various methods of forming graphene contacts on source/drain regions of FinFET devices, and the resulting FinFET device structures. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the methods disclosed herein may be employed in manufacturing a variety of different devices, including, but not limited to, logic devices, memory devices, etc. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.

As will be appreciated by those skilled in the art after a complete reading of the present application, various doped regions, e.g., source/drain regions, halo implant regions, well regions and the like, for the devices are not depicted in the attached drawings. Of course, the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. The various components and structures of the integrated circuit product100disclosed herein may be formed using a variety of different materials and by performing a variety of known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, spincoating techniques, etc. The thicknesses of these various layers of material may also vary depending upon the particular application. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.

FIGS. 2A-2Upresent various views of various embodiments of a FinFET device100(comprised of two illustrative fins) that may be formed using the methods disclosed herein. The drawings also include a simplistic plan view of the device100(in the upper right corner) that depicts the location where various cross-sectional views depicted in the following drawings will be taken. More specifically, the view “X-X” is a cross-sectional view taken through a source/drain region of the device100in a direction that is transverse to the long axis of the fins, i.e., in a direction that is substantially parallel to the gate width (GW) direction of the device100, the view “Y-Y” is a cross-sectional view that is taken through the space between the fins in a direction that is substantially parallel to the gate length direction (GL—i.e., the current transport direction) of the device100, and the view “Z-Z” is a cross-sectional view that is taken through the long axis of a single fin transverse to the long axis of the gate structure, i.e., in the current transport or gate length direction of the device.

In the examples depicted herein, the FinFET device100will be formed in and above a semiconductor substrate102. The substrate102may have a variety of configurations, such as a silicon-on-insulator (SOI) or silicon-germanium-on-insulator (SGOI) that includes a bulk semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. Alternatively, the substrate102may have a simple bulk configuration. The substrate102may be made of silicon or it may be made of materials other than silicon. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials.

FIG. 2Adepicts the device100at a point in fabrication wherein several process operations have been performed. First, a patterned etch mask104, e.g., a combination of a silicon dioxide layer (e.g., a pad oxide) and a silicon nitride layer (e.g., a pad nitride), was formed above the substrate102. In some cases, the pad oxide layer (not separately shown) may be omitted if desired. Thereafter, one or more etching processes were performed through the patterned etch mask104so as to define a plurality of fin-formation trenches105in the substrate102. This results in the formation of a plurality of fins106defined from the substrate material. The illustrative FinFET device100disclosed herein will be depicted as being comprised of two illustrative fins106. However, as will be recognized by those skilled in the art after a complete reading of the present application, the methods and devices disclosed herein may be employed when manufacturing FinFET devices having any number of fins. With respect of view X-X, the fins106extend laterally into and out of the drawing page in the current transport direction of the device100and into what will become the source/drain regions of the device100.

With continuing reference toFIG. 2A, the overall size, shape and configuration of the fin-formation trenches105and the fins106may vary depending on the particular application. The depth and width of the trenches105may vary depending upon the particular application. In one illustrative embodiment, based on current day technology, the overall depth (relative to the upper surface of the substrate102) of the trenches105may range around about 100 nm. In the illustrative examples depicted in the attached figures, the trenches105and the fins106will be simplistically depicted as having generally rectangular portions and sections. In an actual real-world device, the sidewalls of the fin-formation trenches105may be somewhat tapered, although such tapering is not depicted in the drawings. Thus, the size and configuration of the fin-formation trenches105and the fins106, and the manner in which they are made, should not be considered a limitation of the present invention. For ease of disclosure, only the substantially rectangular-shaped trenches105and fins106having a substantially rectangular-shaped cross-sectional configuration will be depicted in the drawings.

FIG. 2Bdepicts the FinFET device100after a layer of insulating material109was formed so as to over-fill the trenches105between the fins106. That is, the layer of insulating material109was formed such that its upper surface109S is positioned above the patterned masking layer104. The layer of insulating material109may be comprised of, for example, silicon dioxide, a HARP oxide, HDP oxide, flowable oxide, etc.

FIG. 2Cdepicts the FinFET device100after one or more CMP processes were performed to remove portions of the layer of insulating material109and the patterned hard mask layer104. These processes result in the layer of insulating material109having a polished surface109X and in the exposure of the upper surface106S of the fins106.

FIG. 2Ddepicts the FinFET device100after a timed, recess etching process was performed to remove a portion of the layer of insulating material109. The recess etching process was performed for a sufficient duration such that the layer of insulating material109has a recessed upper surface109R that is positioned at a desired height level within the trenches105. This recess etching process exposes the desired final fin height of the fins106for the device100.

The next major process operation involves the formation of a gate structure for the device100. The methods disclosed herein may be employed in cases where the gate structure is manufactured using any desired technique, e.g., using so-called “gate first” or “replacement gate” manufacturing techniques. By way of illustration only, the gate structure for the FinFET device100will be depicted as being formed using a replacement gate process. Accordingly,FIG. 2Edepicts the device100after a sacrificial gate insulation layer110, a sacrificial gate structure116and a gate cap (hard mask) layer118were formed on the device100and patterned. In one embodiment, the sacrificial gate insulation layer110may be a thermally grown layer of silicon dioxide, the sacrificial gate structure116may be made of a material such as polysilicon or amorphous silicon, while the gate cap layer118may be made of a material such as silicon nitride. The thickness of these materials may vary depending upon the particular application.FIG. 2Edepicts the device100after the material of the sacrificial gate structure116and the material of the gate cap layer118were patterned using traditional masking and etching techniques. Also shown inFIG. 2Eis a simplistically depicted sidewall spacer121that was formed adjacent the patterned sacrificial gate structure116and the patterned gate cap layer118. The sidewall spacer121was formed by depositing a layer of spacer material (e.g., silicon nitride) and thereafter performing an anisotropic etching process. The spacer121may be of any desired thickness.

FIG. 2Fdepicts the FinFET device100after additional source/drain epi semiconductor material122was formed on portions of the fins106positioned laterally outside of the spacers121, i.e., around and above the three sides of the fins106that are positioned above the recessed surface109R of the layer of insulating material109. The source/drain epi semiconductor material122may be formed by performing traditional epitaxial semiconductor growth processes. The source/drain epi semiconductor material122may be comprised of a variety of different materials and different source/drain epi semiconductor materials122may be formed on different type devices, e.g., silicon (Si), silicon germanium (SiGe), etc., for PMOS devices, silicon, silicon-carbide (SiC), etc., for NMOS devices. In other applications, the source/drain epi semiconductor material122may be the same material for both types of devices, e.g., silicon for both the N and P type devices. As will be appreciated by those skilled in the art after a complete reading of the present application, the silicon-carbide material referenced herein may take a variety of forms, e.g., 3C—SiC, carbon-doped silicon, hydrogen-rich carbon-doped silicon, amorphous silicon-carbide or polycrystalline silicon-carbide. Thus, as used in this detailed description and in the attached claims, the term “silicon-carbide” shall be understood to mean any of the above forms of silicon-carbide material.

In one embodiment, the source/drain epi semiconductor material122may be made of a semiconductor material that is different than the semiconductor material of the substrate102. The source/drain epi semiconductor material122also may exhibit a variety of configurations. In the example depicted inFIG. 2F, the source/drain epi semiconductor material122has a diamond-like cross-sectional configuration (view X-X) that is a function of the crystallographic orientation of the material of the substrate102and the orientation of the fins106. Of course, the source/drain epi semiconductor material122may have a variety of other configurations other than the diamond-like cross-sectional configuration depicted inFIG. 2F.

With continuing reference toFIG. 2F, the source/drain epi semiconductor material122may be formed in such a manner so as to result in so-called “merged” or “unmerged” source/drain regions or fins depending on the duration of the epi growth process around the fins106.FIG. 2Fdepicts an unmerged condition, i.e., a situation where there is no contact between additional source/drain epi semiconductor materials122on the adjacent fins. In other applications, the source/drain epi semiconductor material122may be further “embedded” (a situation not shown in the drawings) by recessing the fins106in the source/drain regions to a depth slightly below the upper surface of the recessed layer of insulating material109and thereafter growing the source/drain epi semiconductor material122on the recessed fins106. Even with the embedded construction, the source/drain epi semiconductor material122is still considered to be formed above the fins106.

With continuing reference toFIG. 2F, at this point, in traditional fabrication processes, a layer of metal silicide would be formed on the source/drain epi semiconductor material122so as to reduce the contact resistance between the source/drain epi semiconductor material122and the device-level source/drain contact structure (not shown) that will be formed to establish electrical contact to the source/drain region. However, forming an individual metal silicide layer that wraps around each of the separated (unmerged) source/drain epi semiconductor material regions122is a very difficult task for several reasons. First, when the source/drain epi semiconductor material122is grown on a fin, it is very difficult to control the thickness of the source/drain epi semiconductor material122. Thus, the source/drain epi material may unintentionally be merged together, thereby preventing the formation of the wrap-around metal silicide layers. One possible solution to avoid such unintended fin merger would be to form the source/drain epi material122on the fin to a very small thickness to virtually assure that unintended fin merger does not occur. The drawbacks to this approach are that such a very small volume of source/drain epi material122will tend to increase the overall resistance and such a thin layer of source/drain epi material122may be substantially consumed by the metal silicide material and/or damaged during the contact formation process. To solve these problems, the inventor has developed a unique method that involves the formation of graphene contacts on the source/drain regions of FinFET devices, thereby eliminating the need to form such metal silicide layers.

FIG. 2Gdepicts the FinFET device100after an additional silicon-carbide (SiC) (as defined above) epi semiconductor material124was grown on the source/drain epi semiconductor material122, around and above the fins106. In one illustrative embodiment, the additional silicon-carbide (SiC) epi semiconductor material124may be grown on the epi semiconductor material122for both the N and P type devices formed on the integrated circuit product. As noted above, the source/drain epi semiconductor material122for an N-type device may be the same or different semiconductor material than the source/drain epi semiconductor material122formed on a P-type device. In other applications, after the formation of the source/drain epi semiconductor material(s)122and after formation of appropriate patterned masking layers (not shown), the additional silicon-carbide (SiC) epi semiconductor material124may be grown on only one type of transistor device formed on the product, e.g., only on the P-type devices or only on the N-type devices. The silicon-carbide (SiC) epi semiconductor material124may be formed by performing traditional epitaxial semiconductor growth processes, and it may be relatively thin, e.g., 2-4 nm. The silicon-carbide (SiC) epi semiconductor material124will generally conform to the configuration of the source/drain epi semiconductor material122. In one embodiment, the silicon-carbide (SiC) epi semiconductor material124may be made of a semiconductor material that is different than the semiconductor material of the substrate102. In one particular example, the silicon-carbide (SiC) epi semiconductor material124(as defined above) may be formed on both the silicon-germanium (SiGe) source/drain epi semiconductor material regions122of a PMOS device and the silicon-carbide (SiC) source/drain epi semiconductor material regions122of an NMOS device. In the case of the NMOS device, the additional layer of silicon-carbide (SiC) (as defined above) epi semiconductor material124is positioned on the silicon-carbide (SiC) source/drain epi semiconductor material regions122.

However, in some applications, the formation of the silicon-carbide epi semiconductor material124may not be required. For example, in some applications, the source/drain epi semiconductor material122may be made of silicon-carbide, e.g., for N-type devices. In that situation, the methods disclosed herein may be employed to form graphene contacts on only the devices where the source/drain epi semiconductor material122may be made of silicon-carbide, e.g., the N-type devices, while an appropriate hard mask layer covers the other devices, e.g., P-type devices.

FIG. 2Hdepicts the device100after a heating process was performed so as to thermally decompose a portion of the silicon-carbide epi semiconductor material124and thereby form graphene contacts126from the silicon-carbide (SiC) epi semiconductor material124. An enlarged view of one of the fins in the source/drain region of the device is depicted inFIG. 2H. The heating process was performed so as to sublimate silicon atoms in the above-described silicon-carbon epi semiconductor material124so as to thereby form the graphene contacts126. The graphene contacts126may be very thin, e.g., one or two monolayers thick. The graphene contacts126will generally conform to the configuration of the epi semiconductor material124(when it is present) or to the epi semiconductor material122when the additional epi silicon-carbide (SiC) semiconductor material124is not formed.

In one illustrative embodiment, for example, when the additional epi silicon-carbide (SiC) semiconductor material124is comprised of an amorphous silicon-carbide material, the additional epi silicon-carbide (SiC) semiconductor material124may be formed using the methods disclosed in the article by Peng et. al., entitled “Direct Transformation of Amorphous Silicon Carbide into Graphene Under Low Temperature and Ambient Pressure,”Scientific Reports, published Jan. 28, 2013, which is hereby incorporated by reference in its entirety. In general, the methods involve using a chlorination method under relatively mild reaction conditions of relatively low temperature, e.g., about 600-800° C. and the ambient pressure in chlorine (Cl2) atmosphere. The heating of the product may be accomplished by performing relatively rapid heating processes, such as an RTA process or a laser anneal process. As a specific example, the product may be placed in a process chamber in an atmosphere comprised of substantially pure helium (He). Thereafter, chlorine may be introduced into the process chamber and the product may thereafter be heated to the desired temperature at some point and thus exposed to a He/Cl2atmosphere for sufficient time to allow formation of the graphene material to the desired thickness, e.g., about 1-5 minutes. In one embodiment, the reaction may be stopped by flushing the process chamber with substantially pure helium gas while maintaining the temperature at about 800° C. for about 1-5 minutes so as to remove the residual chlorine. Thereafter, the process chamber may be allowed to cool to room temperature, about 25° C., in a substantially pure helium environment. In some applications, the heating process may be performed in a furnace wherein the 1-5 minute times mentioned above may be increased, e.g., to a duration of about 1 hour.

Of course, the process conditions and duration may vary depending upon a variety of factors, such as, for example, the thickness of the silicon-carbide (SiC) epi semiconductor material124. The heating process may be performed using a variety of different types of heating tools and techniques, e.g., laser annealing, RTA chamber, etc. In one example, prior to performing the heating process, all areas of the device other than the source/drain regions where the epi semiconductor material124is present, would be masked. Thereafter, a laser annealing process could be performed to scan the particular areas of the substrate where graphene formation is required so as to form the graphene contacts126. As noted above, an RTA process could also be performed.

The graphene contacts126have a significantly lower resistance as compared to traditional metal silicide regions that are normally formed on the source/drain regions, which will help to reduce the overall electrical performance of the resulting FinFET device100. The formation of the graphene contacts126from the epi semiconductor material124(e.g., silicon-carbide) is essentially a sublimation process wherein the silicon atoms evaporate and the carbon atoms in the carbon-rich surface of the epi semiconductor material124collapse and reconstruct in the form of graphene films. Additionally, the formation of graphene on the epi semiconductor material124by sublimation in an argon atmosphere may result in the formation of two types of monolayer graphene with different shapes. For example, relatively long graphene sheets may form along, for example, triple bilayer SiC steps, while relatively narrow graphene ribbons may form by following the surface of a single bilayer SiC height. The relationship between the growth mechanisms and initial surface morphology indicates the effects of H2etching on the formation of graphene. That is, reducing the number of single bilayer SiC steps with H2etching tends to result in better graphene formation.

After the formation of the graphene contacts126, traditional manufacturing techniques may be employed to complete the fabrication of the device100. Accordingly,FIG. 2Idepicts the FinFET device100after several process operations were performed. First, using traditional replacement-gate manufacturing techniques, the sacrificial gate structure116and the sacrificial gate insulation layer110were removed and a replacement gate structure comprised of a high-k (k value of 10 or greater) gate insulation layer132and conductive materials134(one or more metal layers and/or polysilicon) was formed in its place. Thereafter, the replacement gate materials were recessed and a gate cap layer136was formed above the replacement gate structure. Next, insulating material128(e.g., silicon dioxide) was formed above the device100and source/drain contact structures130were formed in openings defined in the insulating material128so as to contact the graphene contacts126and thereby establish electrical connection with the source/drain regions of the device100. In the depicted example, the source/drain contact structures130are line-type structures that span across both of the fins (in the gate width direction of the device). See view X-X. In other cases, the source/drain contact structures130may be individual point-type contacts having a generally cylindrical or rectangular configuration (when viewed from above). The source/drain contact structures130may be made of any desired material, e.g., tungsten.

FIGS. 2J-2Kdepict an embodiment of the device100wherein the additional source/drain epi semiconductor material122is not formed on the fins106. Rather, in this embodiment, the silicon-carbide (SiC) epi semiconductor material124is formed on the bare fin106. Starting at the point of fabrication depicted inFIG. 2E(after formation of the sacrificial gate structure),FIG. 2Jdepicts the device100after the above-described silicon-carbide (SiC) epi semiconductor material124was grown on the sidewalls and upper surface of the fins106, and after the above-described heating process was performed to form the above-described graphene contacts126.FIG. 2Kdepict the FinFET device100after the above-described sacrificial gate structure was removed, after the above-described replacement gate structure was formed and after the above-described source/drain contact structures130were formed on the device100.

FIGS. 2L-2Ndepict an embodiment of the device100wherein the additional source/drain epi semiconductor material122is formed in such a manner so that it merges in the source/drain region of the device100, i.e., the epi growth process is performed for a sufficient duration such that the source/drain epi semiconductor material122forms a more or less continuous region of source/drain epi semiconductor material122in the source/drain regions of the device that is positioned above and around the fins106. That is, starting at the point of fabrication depicted inFIG. 2E(after formation of the sacrificial gate structure),FIG. 2Ldepicts the device100after the above-described source/drain epi semiconductor material122was grown on the sidewalls and upper surface of the fins106, i.e., above and around the fins106, until such time as a substantially continuous region of the source/drain epi semiconductor material122was formed in the source/drain regions of the device100. Thereafter, as shown inFIG. 2M, the above-described silicon-carbide (SiC) epi semiconductor material124was grown on the upper surface of the merged source/drain epi semiconductor material regions122and the above-described heating process was performed to form the above-described graphene contacts126on the upper surface of the merged source/drain epi semiconductor material regions122.FIG. 2Ndepicts the FinFET device100after the above-described sacrificial gate structure was removed, after the above-described replacement gate structure was formed and after the above-described source/drain contact structures130were formed on the device100.

The methods disclosed herein may also be employed in cases wherein the fin structure is comprised of an alternative semiconductor material. Accordingly,FIG. 2Odepicts the device100wherein the overall fin structure is comprised of an alternative semiconductor material106X that is made of a semiconductor material that is different from the semiconductor material of the substrate102. For example, in the case where the substrate102is made of silicon, the alternative semiconductor material106X may be made of a compressively stressed silicon-germanium material for a PMOS device or a tensile stressed silicon-carbide material for an NMOS device. Such alternative materials106X are formed in an effort to increase the current carrying capabilities of the FinFET devices. The alternative semiconductor material106X may be a germanium-containing material SixGe(1-x)(where x ranges from 0.1 to about 0.9) such as Si0.75Ge0.25or the alternative semiconductor material106X may also be made of one or more III-V semiconductor materials (or combinations thereof). The thickness (vertical height) of the alternative semiconductor material106X may vary depending upon the particular application, e.g., about 30-40 nm in one illustrative embodiment. Thus, the alternative semiconductor material106X referenced herein should not be considered to be limited to any particular semiconductor material. The alternative semiconductor material106X may be formed using a variety of techniques. For example, starting at the point of fabrication depicted inFIG. 2C(prior to recessing the layer of insulating material109), the fins106may be recessed so as to define a trench in the insulating material109above the recessed fins. Then, an epi growth process may be performed to form the alternative semiconductor material106X on the recessed fins and in the trench in the insulating layer109. At that point, the device may be processed as described above, e.g., recessing of the layer of insulating material to expose the desired final fin height of the fins, etc. In another illustrative embodiment, the alternative semiconductor material106X may be formed in the substrate102by initially forming a trench in the substrate102, performing an epi deposition process to form the alternative semiconductor material layer106X in the trench and thereafter performing a chemical mechanical planarization (CMP) process. After that process, the fin-formation trenches105may be formed in the substrate102so as to define some fins106that are comprised of only the material of the substrate102and to define some fins that are comprised of the material of the substrate102as well as the alternative semiconductor material106X. Other techniques also exist for forming fins for FinFET devices that are comprised of such an alternative semiconductor material106X. In the embodiment shown inFIG. 2O, additional source/drain epi semiconductor material122was formed in an unmerged condition, the above-described additional silicon-carbide (SiC) epi semiconductor material124was grown on the source/drain epi semiconductor material122, and the above-described heating process was performed to form the above-described graphene contacts126.

FIG. 2Pdepicts the device100wherein the overall fin structure is comprised of an alternative semiconductor material106X and wherein the additional source/drain epi semiconductor material122is not formed on the fins106. Rather, in this embodiment, the silicon-carbide (SiC) epi semiconductor material124is formed on the bare alternative semiconductor material106X. This embodiment is similar to that depicted inFIGS. 2J-2Kexcept that the overall fin structure is comprised of the alternative semiconductor material106X.

FIG. 2Qdepicts the device100wherein the overall fin structure is comprised of an alternative semiconductor material106X that is formed in such a manner so that it merges in the source/drain region of the device100, i.e., the epi growth process is performed for a sufficient duration such that the source/drain epi semiconductor material122forms a more or less continuous region of source/drain epi semiconductor material122in the source/drain regions of the device that is positioned above and around the fins106. This embodiment is similar to that depicted inFIGS. 2L-2Nexcept that the overall fin structure is comprised of the alternative semiconductor material106X.

FIGS. 2R-2Udepict various illustrative examples of using the methods disclosed herein for the above-described graphene contacts126on a CMOS based integrated circuit product101that includes an illustrative PMOS transistor100P and an illustrative NMOS transistor100N that are formed in and above the substrate102.FIGS. 2R-2Udepict only the cross-sectional views section of the transistors100P,100N taken through a source/drain region in the gate width direction of the devices (view X-X). To the extent that the various structures in each of the individual devices100P,100N is made, such reference will be made to PMOS and NMOS terminology along with reference numbers with the added “P” or “N” designation.

Starting at the point of fabrication depicted inFIG. 2E(after formation of the sacrificial gate structure),FIG. 2Rdepicts the CMOS product101after several process operations were performed. First, a simplistically depicted NMOS patterned hard mask layer150, made of a material such as silicon nitride, was formed above the NMOS transistor100N. The NMOS hard mask layer150may be formed by blanket-depositing the NMOS hard mask layer150across the CMOS product101and, thereafter, forming an etch mask layer (not shown), e.g., such as a photoresist mask, that covers the area where the NMOS transistor100N is formed and exposes the area where the PMOS transistor100P is formed. Then an anisotropic etching process was performed to remove the portions of the NMOS hard mask layer150from above the PMOS transistor100P so as to expose the PMOS transistor100P, and particularly the portions of the fins106P in the source/drain regions of the device100P, for further processing. Next, additional source/drain epi semiconductor material122P was formed on portions of the fins106P positioned laterally outside of the spacers121. As noted above, in one embodiment, the source/drain epi semiconductor material122P may be a compressively stress SiGe semiconductor material.

FIG. 2Sdepicts the CMOS product101after several process operations were performed. First, the NMOS patterned hard mask layer150was removed. Then, a simplistically depicted PMOS patterned hard mask layer154, made of a material such as silicon nitride, was formed above the PMOS transistor100P using the techniques described above for forming the NMOS hard mask layer150. The patterned PMOS hard mask layer154exposes the NMOS transistor100N, and particularly the portions of the fins106N in the source/drain regions of the device100N, for further processing. Next, additional source/drain epi semiconductor material122N was formed on portions of the fins106N positioned laterally outside of the spacers121. As noted above, in one embodiment, the source/drain epi semiconductor material122M may be a tensile stressed silicon-carbide (SiC) semiconductor material.

FIG. 2Tdepicts the CMOS product101after several process operations were performed. First, the PMOS patterned hard mask layer154was removed. Then, the above-described additional silicon-carbide (SiC) epi semiconductor material124was grown on the additional source/drain epi semiconductor materials122P and122N for the devices100P,100N, respectively.

FIG. 2Udepicts the CMOS product101after the above-described heating process was performed to form the above-described graphene contacts126on the source/drain regions of both the PMOS transistor100P and the NMOS transistor100N. At this point in fabrication, replacement gate structures may be formed for each of the devices and the above-described source/drain contact structures130may be formed on the CMOS product101.