Memory Bit Cell for In-Memory Computation

A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.

BACKGROUND

Technical Field

Embodiments described herein relate to integrated circuits, and more particularly, to techniques for performing computation operations using memory circuits.

Description of the Related Art

Modern computer systems are being asked to perform increasingly complex tasks, such as language processing, image recognition, and the like. To handle such tasks, different classes of algorithms, such as machine learning algorithms, are being employed. Machine learning algorithms often rely on a set of training data from which a model is generated. The generated model is then used to perform a particular processing task, such as image recognition.

Executing machine learning algorithms can often result in repeatedly performing computation intensive operations, such as multiply and accumulate operations. These types of operation tend to not map well to conventional computer systems. For example, execution of these operations on systems that are based on processors or processor cores configured to execute software or program instructions often result in excessive power dissipation and undesirable performance. To improve the energy efficiency of machine learning algorithms, some computer systems employ in-memory computing techniques, in which a matrix to be operated upon is stored in a memory. The memory is accessed using operand data to activate multiple rows of the memory in parallel to generate a product of the operand and the stored matrix.

SUMMARY OF THE EMBODIMENTS

Various embodiments for performing a compute operation in a memory are disclosed. Broadly speaking, a sign data storage cell is configured to store a sign value associated with a weight value, and selectively couple, based on the sign value, either a compute word line or a complement compute word line to a compute select line. A given compute data storage cell of a plurality of compute data storage cells includes a capacitor and is configured to store a corresponding bit of the weight value, and couple, based on the corresponding bit and a voltage level of the compute select line, a respective amount of charge onto a compute bit line via the capacitor. A control circuit is configured to generate, using an operand value, respective voltage levels on the compute word line and the complement compute word line. An analog-to-digital converter circuit is configured to generate, based on a voltage level of the compute bit line, a plurality of output bits whose value is indicative of a product of the operand value and the weight value. By employing capacitors as a tightly-controlled low-variation phenomenon to control an amount of charge coupled onto to a bit line by a data storage cell during a multiplication operation, the performance of in-memory computation could be improved over implementations that rely on transistors to transfer charge onto the bit line.

DETAILED DESCRIPTION OF EMBODIMENTS

As computer hardware and software continue to evolve, machine learning is increasingly being employed for certain types of computing tasks. As used and defined herein, machine learning is an application of artificial intelligence that provides computer systems the ability to learn and improve from experience without being explicitly programmed. For example, machine learning may be used in such areas as image processing and recognition, self-driving vehicles, natural language processing, and the like. Machine learning may, in various circumstances, employ a model developed from training data. The model is then used to analyze data associated with a particular application.

The algorithms used to implement machine learning do not always lend themselves to execution on conventional computer hardware. Machine learning algorithms can include many multiply-and-accumulate operations, which can result in high power consumption and poor performance on conventional computer hardware, which is not necessarily optimized for high-volume multiply-and-accumulated operations. To provide solutions for such multiply-and-accumulate operations that maintain performance while consuming less power, some computer systems employ in-memory computing techniques.

Rather than retrieving operands from memory and performing, using an arithmetic logic unit, repeated multiplications and additions, in-memory computation involves storing a matrix of numbers (often referred to as “weights”) in a compute-memory circuit and operating on the matrix of numbers using circuits within the compute-memory circuit. The compute-memory circuit may be implemented using static random-access memory (SRAM) storage cells, non-volatile memory storage cells, or any other suitable type of storage cell configured to store values indicative of a logic value.

Compute-memory circuits may employ a variety of techniques for performing a multiply-and-accumulate operation. In general, however, such techniques involve activating (or “reading”) multiple rows within an array based on an operand value. Each activated row generates a product of a weight value stored in that row and a corresponding bit of the operand. The products generated by the activated rows are then added, in an analog fashion, on the bit lines of the compute-memory circuit.

Within an activated row, a given data storage cell will either sink a current or not sink a current from its associated bit line based on a value of the weight bit stored in the given data storage cell. For example, if the stored weight bit is a logical-1, then the given data storage cell may sink a small current from the associated bit line. Other data storage cells from other activated rows may also sink current from the bit line, generating a voltage level on the bit line corresponding to the sum of the individual products. The voltage level of the bit line can then be converted to a digital value using an analog-to-digital converter circuit.

Since the data storage cells in a compute-memory circuit are intended to have identical electrical characteristics, each data storage cell sinking a current from a bit line would sink a current of the same value. During the manufacture of an integrated circuit, devices intended to be identical often vary from instance to instance. Such variation may be the result in slight changes in lithography, differences in implantation of doping atoms into the devices, and the like. The variations can result in the currents sunk by different data storage cells being different, resulting in variation in the voltage level of the bit line for a particular sum. In order to account for such variation on the voltage on a bit line, accuracy and/or resolution of the sum need to be reduced.

The inventors have realized that by reducing the variability with a data storage cell, the variation in the voltage level on a bit line for a given sum could be reduced. Rather than relying on devices within the data storage cell, the inventors have determined that a capacitor, the characteristics of which are more tightly controlled during manufacture than transistors of other transconductance devices, could be used to control an amount of charge coupled onto to a bit line during a multiple operation. With more precise control of the amount of charge added (or subtracted) from the bit line, the variation of the voltage level of the bit line for a particular sum is reduced, improving the accuracy with which the final answer may be obtained.

The embodiments illustrated in the drawings and described below provide techniques for performing in-memory computation using data storage cells that employ capacitors to couple charge on to respective the bit lines instead of device currents. By using low-variation capacitors, variation in the voltage levels of the bit lines resulting from device current variation may be reduced and the accuracy of the in-memory computation may be improved.

A block diagram of a compute-memory circuit is depicted inFIG. 1. As illustrated, compute-memory circuit100includes compute data storage cells101A-101D, sign data storage cell102, compute control circuit103, and analog-to-digital converter circuit109.

Sign data storage cell102is configured to store sign value113. In various embodiments, sign value113is associated with a weight value that includes weight bits111A-111D, and denotes whether the weight value is positive or negative. For example, a sign value of “0” and a weight value of “0010” denotes a weight of “+2”, while a sign value of “1” and a weight value of “0010” denotes a weight of “−2.” Sign data storage cell102is further configured to couple, based on sign value113, either compute word line105or complement compute word line106to compute select line107. For example, if sign value113is “0” then complement compute word line106is coupled to compute select line107. Alternatively, if sign value113is “1” then compute word line105is coupled to compute select line107. As described below, the respective voltage levels on compute word line105and complement compute word line106may be selected, based on operand108, from a predetermined set of voltage levels.

Compute data storage cells101A-101D include capacitors112A-112D, respectively, and are configured to store weight bits111A-111D, respectively. Data storage cells101A-101D are further configured to couple, based on a corresponding one of weight bits111A-111D and a voltage level of compute select line107, a respective amount of charge on compute bit line104via a corresponding one of capacitors112A-112D. For example, if compute data storage cell101A is storing a “1” then capacitor112A will couple an amount of charge onto compute bit line104. In various embodiments, the amount of charge coupled onto compute bit line104may be based on the voltage level of compute select line107.

Since the variation of the capacitor is less than that of devices included in data storage cells101A-101D, the amount of charge coupled to compute bit line104varies less than read currents of data storage cells101A-101D. It is noted that although five weight bits with an associated sign bit are depicted in the embodiment ofFIG. 1, in other embodiments, different number of weight bits may be employed. In such cases, a corresponding number of compute data storage cells would also be employed.

Compute control circuit103is configured to generate, using operand108, respective voltage levels on compute word line105and complement compute word line106. As described below, the amount of charge coupled to compute bit line104may be based on a selected on of the generated voltage levels. In various embodiments, operand108may include any suitable number of bits. As described below, compute control circuit103may include decode circuits configured to decode operand108, in order to select one of multiple voltage levels generated by a voltage generator circuit.

Analog-to-digital converter circuit109is configured to generate, based on a voltage level of compute bit line104, output bits110whose value is indicative of a product of the operand108and a weight value encoded by weight bits111A-111D. As described below in more detail, analog-to-digital converter circuit109may perform a successive approximation or other suitable operation to convert the voltage level of compute bit line104to a particular logic value encoded in output bits110. It is noted that output bits110may include any suitable number of bits that may be based, at least in part, on a desired resolution of the product of operand108and the weight value encoded by weight bits111A-111D. With less variability in the voltage level of compute bit line104for a particular sum value (resulting from the user of capacitors112A-D), analog-to-digital converter circuit109may be able generate a more accurate digital representation of the sum value of compute bit line104.

Turning toFIG. 2, an embodiment of a compute data storage cell is depicted. It is noted that compute data storage cell200may correspond to any of compute data storage cells101A-D as depicted inFIG. 1. As illustrated, compute data storage cell200includes devices201-208and capacitor209.

Device201is coupled between power supply node216and node214, and device203is coupled between node214and ground supply node217. Control terminals of both devices201and203are coupled to node213. In a similar fashion, device202is coupled between power supply node216and node213, and device204is coupled between node213and ground supply node217. Control terminals of devices202and204are coupled to node214.

In various embodiments, devices201and203form an inverter circuit, and devices202and204form another inverter circuit. The two inverter circuits are coupled together in a cross-coupled arrangement that is configured to store data indicated of a particular bit of a weight value. As described below, the particular bit of the weight value may be stored into computer data storage cell200using true bit line211and complement bit line212.

Device205is coupled between complement bit line212and node214, while device206is coupled between true bit line211and node213. Device205is configured to couple, based on the voltage level of word line215, complement bit line212to node214. In a similar fashion, device206is configured to selectively couple, based on the voltage level of word line215, true bit line211to node213. Since devices205and206control access to nodes213and214, the devices are often referred to as “pass devices” or “access devices.”

As mentioned above, true bit line211and complement bit line212can be used to store a bit of a weight value into compute data storage cell200. To store the bit, the value of the bit is differentially encoded in the voltage levels of true bit line211and complement bit line212. When the voltage level of word line215is set to a high logic level, devices205and206activate, coupling complement bit line212to node214, and true bit line211to node213. As the voltage levels of true bit line211and complement bit line212are transferred to nodes213and214, respectively, the regenerative feedback between devices201-204reinforce the change in the voltage levels of nodes213and214. When the voltage level of word line215is set to a logical-0level, devices205and206are deactivated, de-coupling complement bit line212from node214, and true bit line211from node213. Devices201-204maintain the new voltage levels of nodes213and214, thereby storing the bit of the weight value in compute data storage cells200.

True bit line211and complement bit line212, along with devices205and206, may be used to retrieve (or “read”) a value of a bit of a weight value stored in compute data storage cell200. In various embodiments, true bit line211and complement bit line212may be pre-charged to a particular voltage level (e.g., the voltage level of power supply node216). Upon completion of such a pre-charge operation, word line215may transition from a logical-0value to a high logic value, activating devices205and206. One of nodes213or214may be a logical-0value, which will reduce the voltage level of either complement bit line212or true bit line211. The small difference in voltage between true bit line211and complement bit line212may be amplified to determine the value of the bit stored in compute data storage cell200.

Device207is coupled between compute select line107and node218, and is controlled by the voltage level of node213. In various embodiments, device207is configured to couple, based on the voltage level of node213, compute select line107to node218. For example, when the voltage level of node213corresponds to a high logic level, device207is active, compute select line107is coupled to node218.

Device208is coupled between node218and zero control signal210, and is configured to couple zero control signal210to node218. For example, in response to the voltage level on node214corresponding to a high logic level, device208is active, coupling zero control signal210to node218.

In various embodiments, a difference between the respective voltage levels of compute bit line104and zero control signal210determines an amount of charge that is coupled onto compute bit line104for a multiplication result of zero. For example, if the voltage level of zero control signal210is set to the pre-charge level of compute bit line104, then no charge will be added to compute bit line when compute select line107is activated. Storing no charge for a zero multiplication result results in the largest signal (i.e., the largest change in voltage on compute bit line104) for non-zero results. In some cases, however, it may be desirable, at the expense of the signal-to-noise ratio of the circuit, to set zero control signal210to store a particular amount of charge for use in generating the multiplication result of zero.

Depending on a value of the bit stored in compute data storage cell200, charge stored in capacitor209may be transferred to compute bit line104in response to an assertion of compute select line107. For example, if the voltage level on node213corresponds to a high logic level (i.e., the bit value stored in compute data storage cell200is a logical-1), device207is active. With device207active, when the voltage level of compute select line107is increased, the voltage level of node218also increases. The increase in the voltage level on node218couples the charge stored in capacitor209into compute bit line104, resulting in a change in the voltage level of compute bit line104. Since whether or not compute select line107increases in voltage is based on a value of operand108, the resultant voltage change on compute bit line104corresponds to a product of the bit of a weight value stored in compute data storage cell200and operand108. It is noted that when compute data storage cell200is storing a logical-0 value, device207is inactive and device208is active, so the change in voltage of compute bit line104is based on a voltage level of zero control signal210. The change in voltage level, which is some cases may be zero, corresponds to a situation where the product of operand108and the bit stored in compute data storage cell200is zero.

Capacitor209is coupled between node218and compute bit line104, and is configured to couple a particular amount of charge onto compute bit line104based, at least in part on, the zero control signal210, and the respective voltage levels of node213, node214, and compute select line107. The particular amount of charge may correspond to a product of the operand108and the bit stored in compute data storage cell200.

In various embodiments, capacitor209may be an embodiment of a metal capacitor formed using metal layers separated by an oxide layer. The use of capacitor209to couple charge onto compute bit line104allows the amount of charge coupled onto compute bit line to vary naturally with the voltage level of power supply node216. Moreover, capacitor209allows for lower static power consumption and a reduced area compared to using a device to couple charge onto compute bit line104. As noted above, different instances of200may use capacitors of different values. In some cases, instances of data storage cell200used to store the bits of a weight value may use capacitors that are weighted in a binary fashion. For example, a capacitor included in a particular data storage cell may be twice the value of a capacitor included in another data storage cell configured to store a next lower significant bit of the weight value.

Devices203-208may be implemented as n-channel metal-oxide semiconductor field-effect transistors (MOSFETs), and devices201and202may be implemented as p-channel MOSFETs. Although the embodiment illustrated inFIG. 2, depicts devices201-208as single devices, in other embodiments, any of devices201-208may include multiple devices in parallel.

Turning toFIG. 3, an embodiment of a sign data storage cell is depicted. As illustrated, sign data storage cell120includes devices305-307. In various embodiments, devices301and302may be implemented as p-channel MOSFETs, and devices303-307may be implemented as n-channel MOSFETs.

Device301is coupled between power supply node216and node315, and device303is coupled between node315and ground supply node217. Control terminals of both devices201and203are coupled to node316. In a similar fashion, device302is coupled between power supply node216and node316, and device304is coupled between node316and ground supply node217. Control terminals of devices202and204are coupled to node315.

In various embodiments, devices301and303form an inverter circuit, and devices302and304form another inverter circuit. The two inverter circuits are coupled together in a cross-coupled arrangement that is configured to store data indicative of a sign bit associated with a particular weight value. As described below, the sign bit may be stored into sign data storage cell300using true bit line309and complement bit line308.

Device305is coupled between complement bit line308and node315, while device306is coupled between true bit line309and node317. Device305is configured to selectively couple, based on the voltage level of word line215, complement bit line308to node315. In a similar fashion, device306is configured to selectively couple, based on the voltage level of word line215, true bit line309to node316. Since devices305and306control access to nodes315and316, the devices are often referred to as “pass devices” or “access devices.”

As mentioned above, true bit line309and complement bit line308can be used to store sign bit into sign data storage cell300. To store the sign bit, the value of the bit is differentially encoded in the voltage levels of true bit line309and complement bit line308. When the voltage level of word line215is set to a high logic level, devices305and306activate, coupling complement bit line308to node315, and true bit line309to node316. As the voltage levels of true bit line309and complement bit line308are transferred to nodes316and315, respectively, the regenerative feedback between devices301-304reinforce the change in the voltage levels of nodes315and316. When the voltage level of word line215is set to a logical-0, devices305and306are deactivated, de-coupling complement bit line212from node214, and true bit line211from node213. The regenerative feedback of devices301-304maintaining the new voltage levels of nodes315and316, thereby storing the sign bit in sign data storage cell300.

True bit line309and complement bit line308, along with devices305and306, may be used to retrieve (or “read”) a value of the sign bit stored in sign data storage cell300. In various embodiments, true bit line309and complement bit line308may be pre-charged to a particular voltage level (e.g., the voltage level of power supply node216). Upon completion of such a pre-charge operation, word line215may transition from a logical-0 value to a high logic value, activating devices305and306. One of nodes315or316may be a logical-0 value, which will reduce the voltage level of either complement bit line308or true bit line309. The small difference in voltage between true bit line309and complement bit line308may be amplified to determine the value of the sign bit stored in sign data storage cell300.

Device306is coupled between compute word line312and select line107, and device307is coupled between complement compute word line314and select line107. A control terminal of device306is coupled to node316, and a control terminal of device307is coupled to node315. Device307is configured to selectively couple, based on a voltage level of node315, complement compute word line314to select line107. Device306is configured to selectively couple, based on a voltage level of node316, compute word line312to select line107.

During a compute operation, the voltage levels of compute word line312and complement compute word line314are set by compute control circuit103. Based upon a value of the sign bit stored in sign data storage cell300, either compute word line312or complement compute word line314is coupled to select line107. For example, if the value of the sign bit stored in sign data storage cell300is a logical-1, then the voltage level of node316corresponds to a high logic value, and the voltage level of node315corresponds to a logical-0 value. The high logic value on node316activates device306, coupling compute word line312to select line107. The logical-0 value on node315deactivates device307, preventing complement compute word line314from coupling to select line107. If sign data storage cell300is storing a logical-0value, then device306is inactive and device307is active, coupling complement compute word line314to select line107.

Turning toFIG. 4, an embodiment of control circuit103is depicted. As illustrated, control circuit103includes compute word line generator circuit401, compute word line generator circuit402, and voltage divider circuit403.

Compute word line generator circuit401is configured to selectively generate a signal on compute word line312using sample clock404, operand108, hold clock405, and voltage levels406. As described below, compute word line generator circuit401may select, based on operand108, different ones of voltage levels406when sample clock404is asserted. In various embodiments, compute word line generator circuit401is configured to pre-charge compute word line312to a particular voltage level, in response to an assertion of hold clock405.

Compute word line generator circuit402is configured to generate a signal on complement compute word line314. In various embodiments, compute word line generator circuit402functions in a similar fashion to compute word line generator circuit402, however the logic circuits of compute word line generator circuit402are a complement of compute word line generator circuit401, resulting in the signal on complement compute word line314being a logical inverse of the signal on compute word line312.

Voltage divider circuit403is configured to generate voltage levels406. In various embodiments, voltage levels406may include any suitable number of voltage levels. For example, in some embodiments, 15 different voltage levels are included in voltage levels406. As described below, voltage divider circuit403may employ a resistive voltage divider or other suitable circuit that uses a voltage level of a power supply node to generate the different ones of voltage levels406.

Turning toFIG. 5, an embodiment of a compute word line generator circuit500is depicted. As illustrated, compute word line generator circuit500includes select circuits501-503, decoder circuit504, and pre-charge circuit505. In various embodiments, compute word line generator circuit500may correspond to either of compute word line generator circuits401and402as depicted inFIG. 4.

As described below in more detail, pre-charge circuit505is configured to set compute word line507to a particular voltage level using hold clock405. For example, in response to an assertion of hold clock405, pre-charge circuit505may set compute word line507to a particular voltage level for a particular value of sign value506, or set compute word line507to a different voltage level for a different value of sign value506.

Decoder circuit504is configured to generate selection signals508using operand108. In various embodiments, decoder circuit504may include any suitable combination of logic circuits configured to assert a particular one of selection signals508based on a value of operand108. In various embodiments, each possible value of operand108may be mapped to a corresponding one of selection signals508.

Select circuit502is configured to select one of voltage levels406to generate voltage level509. In various embodiments, select circuit502may include multiple pass devices configured to activate in response to an assertion of a corresponding one of selection signals508. In a similar fashion, select circuit503may include multiple pass devices, and is configured to select a different one of voltage levels406using selection signals508to generate voltage level510. Although the topology of select circuits502and503are similar, in various embodiments, the connections of either voltage levels406or selection signals508may be different so that select circuit502selects a different one of voltage levels406that does select circuit503for a particular value of operand108.

Select circuit501is configured to selectively couple, using sample clock404and sign value506, one of voltage level509or voltage level510onto compute word line507. As described below in more detail, in response to an assertion of sample clock404, select circuit501is further configured selectively couple, based on a value of sign value506, one of voltage level509or voltage level510to compute word line507. For example, when sign value506is a low or logical-0 value, select circuit501may be configured to couple voltage level509to compute word line507. Alternatively, when sign value506is a high or logical-1 value, select circuit501may be configured to couple voltage level510to compute word line507.

Device601is coupled to compute word line507, and is configured to selectively couple, based on signal607, pre-charge voltage level606to compute word line507. For example, in response to an assertion of signal607, device601may couple pre-charge voltage level606to compute word line507, thereby pre-charging compute word line507. In various embodiments, device601is an embodiment of an n-channel MOSFET or other suitable transconductance device. It is noted that although device601is depicted inFIG. 6as a single device, in other embodiments, any suitable number of devices may be used to implement device601.

Device602is coupled between compute word line507and ground supply node217, and is configured to couple, based on signal608, compute word line507to ground supply node217. In various embodiments, device602is an embodiment of an n-channel MOSFET or other suitable transconductance device. It is noted that although device602is depicted inFIG. 6as a single device, in other embodiments, any suitable number of devices may be used to implement device602.

AND gate603is configured to generate signal607using hold clock405and sign value506. In various embodiments, AND gate603is configured to generate signal607such that a logic value of signal607is the logical AND of the respective values of hold clock405and sign value506. For example, in response to a determination that respective values of hold clock405and sign value506are both logical-1s, AND gate603will set signal607to a logical-1 value, which enables device601, allowing compute word line507to charge to pre-charge voltage level606.

AND gate604is configured to generate signal608using hold clock405and complement sign value605. In various embodiments, AND gate604is configured to generate signal608such that a logic value of signal608is the logical AND of the respective values of hold clock405and complement sign value506. For example, in response to a determination that respective values of hold clock405and complement sign value506are both logical-1s, AND gate604will set signal608to a logical-1 value, which enables device602, discharging compute word line507to the voltage level of ground supply node217.

AND gates603and604may be implemented as CMOS logic gates configured to perform a logical AND operation of its input signals to generate an output signal. In some cases, AND gates603and604may include multiple logic gates (e.g., a NAND gate and an inverter), or any other suitable combination of devices configured to implement the logical AND function.

Turning toFIG. 7, a block diagram of an embodiment of select circuit501is depicted. As illustrated, select circuit501includes devices701and702, and gates703and704.

Device701is coupled to compute word line507, and is configured to selectively couple, based on signal707, voltage level509to compute word line507. For example, in response to an assertion of signal707, device701may couple voltage level509to compute word line507, thereby setting compute word line507to voltage level509. In various embodiments, device701is an embodiment of an n-channel MOSFET or other suitable transconductance device. It is noted that although device701is depicted inFIG. 7as a single device, in other embodiments, any suitable number of devices may be used to implement device701.

Device702is coupled to compute word line507and is configured to couple, based on signal708, compute word line507to voltage level510. In various embodiments, device702is an embodiment of an n-channel MOSFET or other suitable transconductance device. It is noted that although device702is depicted inFIG. 7as a single device, in other embodiments, any suitable number of devices may be used to implement device702.

AND gate703is configured to generate signal707using sample clock404and sign value506. In various embodiments, AND gate703is configured to generate signal707such that a logic value of signal707is the logical AND of the respective values of sample clock404and sign value506. For example, in response to a determination that respective values of sample clock404and sign value506are both logical-1s, AND gate703will set signal707to a logical-1 value, which enables device701, setting compute word line507to voltage level509.

AND gate704is configured to generate signal708using sample clock404and complement sign value605. In various embodiments, AND gate704is configured to generate signal708such that a logic value of signal708is the logical AND of the respective values of sample clock404and complement sign value605. For example, in response to a determination that respective values of sample clock404and complement sign value605are both logical-1s, AND gate704will set signal708to a logical-1 value, which enables device702, setting compute word line507to voltage level510.

AND gates703and704may be implemented as CMOS logic gates configured to perform a logical AND operation of its input signals to generate an output signal. In some cases, AND gates703and704may include multiple logic gates (e.g., a NAND gate and an inverter), or any other suitable combination of devices configured to implement the logical AND function.

Turning toFIG. 8, an embodiment of a select circuit is depicted. As illustrated, select circuit800includes devices801A-D, and may correspond to either of select circuits502or503as depicted in the embodiment ofFIG. 5. Although only four devices are depicted in the embodiment ofFIG. 4, in other embodiments, and suitable number of devices may be employed.

Device801A is coupled between node806and node803A, and is configured to couple, based on selection signal802A, voltage level804A onto node806to generate selected voltage level805. In a similar fashion, device801B is coupled between node806and node803B, and is configured to couple, based on selection signal802B, voltage level804B onto node806to generate selected voltage level805.

Device801C is coupled between node806and node803C, and is configured to couple, based on selection signal802C, voltage level804C onto node806to generate selected voltage level805. In a similar fashion, device801D is coupled between node806and node803D, and is configured to couple, based on selection signal802D, voltage level804D onto node806to generate selected voltage level805.

Voltage levels804A-D may, in various embodiments, be included in voltage levels406as depicted in the embodiment ofFIG. 4. Selection signals802A-D may, in various embodiments, be included in selection signals508as depicted inFIG. 5. It is noted that, in some cases, selection signals802A-D may be mutually exclusive, i.e., only one of selection signals802A-D may be asserted at a time.

Devices801A-D may be implemented as n-channel MOSFETs or other suitable transconductance devices. Although each of devices801A-D are depicted as a single device, in other embodiments, any of devices801A-D may include any suitable number of devices coupled together in parallel.

Voltage levels406may be generated using a variety of circuit techniques. One such circuit technique is depicted in the embodiment ofFIG. 9. As illustrated, voltage divider circuit403includes device901, and resistors902-904.

Resistors902-904are coupled between device901and a ground supply node. Resistors902-904may be fabricated from metal, polysilicon, or any other suitable material available on a semiconductor manufacturing process. It is noted that although only three resistors are depicted in the embodiment ofFIG. 9, in other embodiments, any suitable number of resistors may be employed.

Device901is coupled between a power supply node and the series combination of resistors902-904, and is controlled by enable signal905. In various embodiments, device901may be an embodiment of a p-channel MOSFET configured to conduct current from the power supply node to the series combination of resistors902-904when enable signal905is at a logical-0 level.

As current flows from the power supply node via device901into the series combination of resistors902-904, a voltage drop is developed across each of resistors902-904. The voltage drop across a given on of resistors902-904corresponds to a particular one of voltage levels406. When enable signal905is at a high logic level, device901is disabled, resulting in a high impedance between the power supply node and the series combination of resistors902-904, thereby preventing any current flow through resistors902-904. With no current flow, each of voltage levels406may drop to a voltage level at or near ground potential.

Amplifier circuit1002may, in various embodiments, be an embodiment of a differential amplifier configured to generate amplifier output signal1004using a voltage level of compute bit line104and reference signal1005. In some embodiments, amplifier circuit1002may be configured to compare the voltage level of compute bit line104to reference signal1005in order to determine a particular logic level for amplifier output signal1004. For example, if the voltage level of compute bit line104is less than reference signal1005, then amplifier circuit1002may be configured to set amplifier output signal1004to a logical-1 value.

Successive approximation register circuit1001is configured to generate output bits110using amplifier output signal1004. In various embodiments, successive approximation register circuit1001may be an embodiment of a sequential logic circuit configured, based on a particular value of amplifier output signal1004, to increase or decrease the value of output bits110according to one of various algorithms. For example, successive approximation register circuit1001may change the value of outputs bits110according to a binary search algorithm. Successive approximation register circuit1001may include any suitable number of bits, and may also employ a clock signal (not shown) in conjunction with amplifier output signal1004to increment and decrement the value of output bits110.

Digital-to-analog converter circuit1003is configured to generate reference signal1005using output bits110. In various embodiments, the digital-to-analog converter circuit1003may be configured to determine a voltage level of reference signal1005based on a value of output bits110. For example, in some cases, the larger the value of the number represented by output bits110, the greater the voltage level of reference signal1005.

When compute-memory circuit100initiates a compute operation, successive approximation register circuit1001may initialize the output bits110to a particular value. Digital-to-analog converter circuit1003may then determine the voltage level of reference signal1005based on the value of output bits110. Amplifier circuit1102may then compare reference signal1005to the voltage level of compute bit line104. Successive approximation register circuit1001may then increase or decrease the value of output bits110using results of the comparison of the voltage level of compute bit line104and reference signal1005. The process may continue, with successive approximation register circuit1001modifying the value of output bits110until reference signal1005is within a threshold value of the voltage level of compute bit line104, at which point the value of output bits110represents the voltage level of compute bit line104, and therefore, the product of operand108and the weight value that includes weight bits103A-103D.

Another embodiment of a compute-memory circuit is depicted inFIG. 11. As illustrated, compute-memory circuit1100includes array circuits1101and1102, word line driver circuits1103, compute word line circuits1104, compute control circuit1105, read/write control circuit1106, analog-to-digital converter circuits1107and1108, and input/output circuits1109and1110.

As described below in more detail, array circuits1101and1102may include multiple compute data storage cells200and sign data storage cells300. Array circuits1101and1102are coupled to word line driver circuits1103and compute word line circuits1104. Additionally, the true and complement bit lines of the compute and sign data storage cells included in array circuits1101and1102are coupled to input/output circuits1109and1110, respectively.

Compute word line circuits1104may correspond to control circuit103as depicted inFIG. 1. In various embodiments, compute word line circuits1104are configured to generate compute word lines (e.g., compute word line105) and complement compute word lines (e.g., complement compute word line106) using operands1113.

Word line driver circuits1103are configured to generate word line signals (e.g., word line215) using signals from read/write control circuit1106. In various embodiments, such word lines are used to store weight information in data storage cells included in array circuits1101and1102. In some cases, word line driver circuits1103are configured to decode address information (not shown) to generate the word line signals.

Analog-to-digital converter circuits1108and1109may, in various embodiments, include multiple ones of analog-to-digital converter circuit109as depicted inFIGS. 1 and 7. In some embodiments, analog-to-digital converter circuits1108and1109may be configured to generate compute output1111and compute output1112, respectively, using data from array circuit1101and1102.

Input/output circuit1109is configured to receive read write data1114, and input/output circuit1110is configured to receive read write data1115, respectively, and temporarily store the received data until it is stored in the compute data storage cells and sign data storage cells included in array circuits1101and1102. In various embodiments, read write data1114and1115may include weights use for in-memory compute operations. Additionally, input/output circuits1109and1110may be configured to output data read from array circuits1101and1102. Such read data may be used to verify that the sign and weight values have been correctly stored in the compute and sign data storage cells of array circuit1101. In various embodiments, input/output circuits1109and1110may include any suitable combination of latch circuits, sense amplifier circuits, write driver circuits, and the like.

Read/write control circuit1106is configured to generate, using read write control1116, timing signals (not shown) used by input/output circuits1109and1110to write data to and read data from array circuits1101and1102. In various embodiments, read/write control circuit1106may include any suitable combination of combinatorial and sequential logic circuits.

Turning toFIG. 12, a block diagram of array circuit1200is depicted. In various embodiments, array circuit1200may correspond to either of array circuits1101and array circuits1102as depicted inFIG. 11. As illustrated, array circuit1200includes weight group1201-1206. Although only five weight groups are depicted in array circuit1200, in other embodiments, any suitable number of weight groups may be employed.

Each of weight groups1201-1205may include multiple data storage cells, such as those described above, configured to store sign and weight. For example, weight group1201includes sign bit1207and weight bits1208A-1208D. In various embodiments, sign bit1207may correspond to sign data storage cell300as depicted inFIG. 3, and weight bits1208A-1208D may correspond to compute data storage cell200as depicted inFIG. 2. It is noted that although only4weight bits are depicted in weight group1201, in other embodiments, any suitable number of weight bits may be employed.

Turning toFIG. 13, a flow diagram depicting an embodiment of a method for operating a compute-memory is illustrated. The method, which begins in block1301, may be applied to various compute-memory circuits, including compute-memory circuit1100as depicted inFIG. 11.

The method includes receiving an operand by a compute-memory circuit that includes a plurality of data storage cells (block1302). In various embodiments, the operand may include any suitable number of bits that may be set of respective logical values (e.g., logical-1). In some cases, the operand may be a signed value, in which case one of the bits included in the operand corresponds to a sign of the operand.

The method further includes decoding, by the compute-memory circuit, the operand to generate a plurality of select signals (block1303). In various embodiments, decoding the operand may include latching the bits included in the operand, and generating complement values of the latched bits.

The method also includes setting, using the plurality of select signals, a voltage level of a compute select line (block1304). In some cases, the method further includes generating, by a voltage divider circuit, a plurality of voltage levels. In various embodiments, setting the voltage level of the compute select line includes selecting a first voltage level of the plurality of voltage levels for a compute word line using a first clock signal and a first sign bit associated with the operand, and selecting a second voltage level of the plurality of voltage levels for a complement compute word line using the first clock signal and the first sign bit value.

Setting the voltage level of the compute select line may further include selectively coupling either the compute word line or the complement compute word line to the compute select lines using a second sign bit associated with the weight value. In various embodiments, the method may also include pre-charging the compute word line and the complement compute word line to respective voltage levels using a second clock signal different that the first clock signal.

The method further includes coupling, by a subset of the plurality of data storage cells, a respective amounts of charge onto a compute bit line using the compute select line, wherein the subset of the plurality of data storage cells is configured to store respective bits of a plurality of weight bits included in a weight value (block1305). In some embodiments, coupling, the respective amounts of charge onto the compute bit line includes coupling, by a first data storage cell of the subset of the plurality of data storage cells, a first amount of charge using a first capacitor coupled to the compute bit line, and coupling, by a second data storage cell of the subset of the plurality of data storage cells, a second amount of charge using a second capacitor coupled to the compute bit line, where a value of the second capacitor is greater than a value of the first capacitor. In various embodiments, the value of the first capacitor is twice the value of the second capacitor.

The method also includes generating, using the voltage level of the compute bit line, a plurality of output bits whose value is indicative of a product of the operand and the weight value (block1306). The method may further include setting an initial voltage level on the compute bit line prior to receiving the operand. The method concludes in block1307.

A block diagram of computer system is illustrated inFIG. 14. In the illustrated embodiment, the computer system1400includes power management circuit1401, processor circuit1402, compute-memory circuit1100, and input/output circuits1404, each of which is coupled to communication bus1405. In various embodiments, computer system1400may be a system-on-a-chip (SoC) and/or be configured for use in a desktop computer, server, or in a mobile computing application such as, e.g., a tablet, laptop computer, or wearable computing device.

Power management circuit1401is configured to provide power to processor circuit1402, compute-memory circuit1100, and input/output circuits1404. In various embodiments, power management circuit1401includes one or more power converter circuits configured to generate regulated voltage levels on power supply nodes internal to computer system1400. In some cases, power management circuit1401may generate respective regulated voltage levels for processor circuit1402, compute-memory circuit1100, and input/output circuit1404.

Processor circuit1402may, in various embodiments, be representative of a general-purpose processor that performs computational operations. For example, processor circuit1402may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA).

As described above, compute-memory circuit1100may be configured to perform in-memory compute functions. In various embodiments, compute-memory circuit1100may be configured to store a matrix of weight values and generate a product of the weight values and an operand value. Compute-memory circuit1100may be configured to send the result to processor circuit1402or input/output circuit1404using communication bus1405. It is noted that although in a single compute-memory circuit is illustrated inFIG. 14, in other embodiments, any suitable number of compute-memory circuits may be employed.

Input/output circuits1404may be configured to coordinate data transfer between computer system1400and one or more peripheral devices. Such peripheral devices may include, without limitation, storage devices (e.g., magnetic or optical media-based storage devices including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral devices. In some embodiments, input/output circuits1404may be configured to implement a version of Universal Serial Bus (USB) protocol or IEEE 1394 (Firewire®) protocol.

Input/output circuits1404may also be configured to coordinate data transfer between computer system1400and one or more devices (e.g., other computing systems or integrated circuits) coupled to computer system1400via a network. In one embodiment, input/output circuits1404may be configured to perform the data processing necessary to implement an Ethernet (IEEE 802.3) networking standard such as Gigabit Ethernet or 10-Gigabit Ethernet, for example, although it is contemplated that any suitable networking standard may be implemented. In some embodiments, input/output circuits1404may be configured to implement multiple discrete network interface ports.

The present disclosure includes references to “embodiments,” which are non-limiting implementations of the disclosed concepts. References to “an embodiment,” “one embodiment,” “a particular embodiment,” “some embodiments,” “various embodiments,” and the like do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including specific embodiments described in detail, as well as modifications or alternatives that fall within the spirit or scope of the disclosure. Not all embodiments will necessarily manifest any or all of the potential advantages described herein.

Unless stated otherwise, the specific embodiments are not intended to limit the scope of claims that are drafted based on this disclosure to the disclosed forms, even where only a single example is described with respect to a particular feature. The disclosed embodiments are thus intended to be illustrative rather than restrictive, absent any statements to the contrary. The application is intended to cover such alternatives, modifications, and equivalents that would be apparent to a person skilled in the art having the benefit of this disclosure.

Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure. The disclosure is thus intended to include any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.

For example, while the appended dependent claims are drafted such that each depends on a single other claim, additional dependencies are also contemplated, including the following: Claim9(could depend from any of claims7-8); claim10-11(could depend from any of claims7-9); etc. Where appropriate, it is also contemplated that claims drafted in one statutory type (e.g., apparatus) suggest corresponding claims of another statutory type (e.g., method).

References to the singular forms such as “a,” “an,” and “the” are intended to mean “one or more” unless the context clearly dictates otherwise. Reference to “an item” in a claim thus does not preclude additional instances of the item.

When the term “or” is used in this disclosure with respect to a list of options, it will generally be understood to be used in the inclusive sense unless the context provides otherwise. Thus, a recitation of “x or y” is equivalent to “x or y, or both,” covering x but not y, y but not x, and both x and y. On the other hand, a phrase such as “either x or y, but not both” makes clear that “or” is being used in the exclusive sense.

Various “labels” may proceed nouns in this disclosure. Unless context provides otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. The labels “first,” “second,” and “third” when applied to a particular feature do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise.

The term “configured to” is not intended to mean “configurable to,” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function. This unprogrammed FPGA may be “configurable to” perform that function, however.

Reciting in the appended claims that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U. S.C. § 112(f) for that claim element. Should Applicant wish to invoke Section 112(f) during prosecution, it will recite claim elements using the “means for” [performing a function] construct.