FB DRAM memory with state memory

A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.

TECHNICAL FIELD

Embodiments of the present invention relate to the data storage, such as in FB DRAM (floating body dynamic random access memory) or ZRAM (zero capacitor RAM) memories.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FB DRAM memories are dynamic memories in which the information may be stored in a body of an SOI (silicon on insulator) transistor. Here, in the so-called body, positive charges also referred to as holes, can be stored, wherein these may lead to a reduction in the threshold voltage of the transistor. If such a memory is read out, the transistor current, which is dependent on the positive charges stored in the body, may be assessed. Memory accesses thus can be done quickly, since the selection transistor concurrently corresponds to the memory element. Different ways of accessing an array of FB DRAM cells are possible. For example, this may be done through different gate voltages, via which it may then be determined whether it is to be written or read in a transistor, or if no action is to be taken on this transistor. However, this may result in the fact that, prior to the selection of a certain address, information on the type of access already is needed in a memory region, since the type of access is directly linked with the selection of the transistor or transistors.

The term FB DRAM may also be replaced by ZRAM in the following. The frequent use of the term FB DRAM is not to be understood in a limiting sense, the term ZRAM can be used synonymously.

Embodiments of the present invention may utilize state memories, which can be coupled as buffers between data lines and an FB DRAM memory region. Independently of the type of access to the memory region, embodiments may thus already transfer the contents of the memory region into the state memories, so that the state memories can be written to or read out in the actual access.

FIG. 1shows an embodiment of a memory chip100with a plurality of FB DRAM cells, wherein only two cells110and112are illustrated exemplarily inFIG. 1. The memory chip100further includes a word line (WL)120, which is coupled to the first FB DRAM cell110and the second FB DRAM cell112. The memory chip100further comprises a first bit line (BL)130, which is coupled to the first FB DRAM cell110.FIG. 1further shows a first state memory circuit135, which is coupled to the first bit line130.

The embodiment of a memory chip100further shows a second bit line140, which is coupled to the second FB DRAM cell112, as well as a second state memory circuit145, which is also coupled to the second bit line (BL)140. The memory chip100further comprises a sense amplifier150, which can be coupled to the first FB DRAM cell110, the second FB DRAM cell112, the first state memory circuit135or the second state memory circuit145, which is indicated inFIG. 1by the two-way solid arrows between the state memories135and145, respectively, and the sense amplifier150.

If the memory chip is accessed, the word line120may at first provide a read signal to the two FB DRAM cells110and112. For example, the sense amplifier may at first be coupled to the bit line130and disconnected from the bit line140. If the sense amplifier150is coupled to the bit line130, it may evaluate the current through the FB DRAM cell110, so that a signal reflecting the stored state of the FB DRAM cell110results at the output of the sense amplifier150. The output of the sense amplifier150may then be coupled to the state memory135, so that it now comprises the state of the FB DRAM cell110. Subsequently, the sense amplifier150may again be disconnected from the bit line130and coupled to the bit line140. The sense amplifier150may now make a corresponding current assessment of the FB DRAM cell112, so that a signal reflecting the stored state of the stored FB DRAM cell112results at the output of the sense amplifier. The sense amplifier150may then be coupled to the state memory circuit145, which then stores the stored state of the FB DRAM cell112. The states stored in the two state memory circuits135and145may now be read out or written to externally, which is indicated by the dashed data line160and the dashed two-way mirrors between the data line160and the state memory circuits135and145.

Up to this point, embodiments of the memory chip may also work without the knowledge whether there is to be a reading or writing access to the memory, and the measures just described may conversely already be begun before the information on the type of the access is present, if there is only the information as to on which cell the access will take place. Now there is the possibility to read out the state memory circuit135or145, or manipulate the contents thereof, as it may be performed in a writing access.

The state memories135and145are coupled to the FB DRAM cells110and112, respectively. If a write signal is applied to the word line120, the FB DRAM cells110and120may take over the states stored in the state memory circuits135and145, respectively.

The memory chip100could include several FB DRAM cells, wherein these may, for example, be subdivided into groups. In embodiments, the state memory circuits could then each be coupled to an FB DRAM cell of a group. In other words, in this case a state memory circuit could be coupled to an FB DRAM cell of a group each, so that the state memory circuits can be reused or switched for FB DRAM cells of different groups.

The plurality of FB DRAM cells could be formed to receive a read signal, a write signal or an idle signal on the word line, for example, the word line120, wherein an FB DRAM cell may further be writable if the write signal is present on the word line, may be readable if the read signal is present on the word line, and may be neither readable nor writable if the idle signal is present on the word line. In realizations, these signals may, for example, be realized by mutually different voltages, as will be further explained in the following.

In embodiments, the state memory circuits may, for example, comprise two inversely coupled inverters, which may be connected together into a latch or also into a flip-flop. Furthermore, the FB DRAM cells may be subdivided into groups, wherein there may be a sense amplifier150for each group, so that different groups of FB DRAM cells can be coupled to different sense amplifiers. In other embodiments, a sense amplifier150could also be switched back and forth between individual groups of FB DRAM cells.

In a simple embodiment of a memory chip100, it could also include only a single path, that is, a single bit line130. Such an embodiment, for example, would be the memory chip100fromFIG. 1with an FB DRAM cell110, a bit line130and a sense amplifier coupled to the bit line130, wherein a state memory circuit135can be connected into the bit line130between the FB DRAM cell110and the sense amplifier150. Such a simple embodiment is highlighted inFIG. 1by a dashed box170.

In embodiments, the FB DRAM cell110may further comprise a word line120and be formed to receive a read signal, a write signal or an idle signal at the word line120, wherein the FB DRAM cell110may further be formed to provide a stored state on the bit line130if the read signal is present on the word line120, store a state of the bit line130if the write signal is present on the word line120, and neither store a state nor provide one on the bit line130if the idle signal is present on the word line120.

States to be read or to be written can be buffered in the state memory circuits135in embodiments. External accesses may thus at first take place to the state memory circuits135. If an access takes place before the type of access is known, the FB DRAM cell110can be coupled to the sense amplifier150in order to perform a current assessment of the coupled FB DRAM cell110. In embodiments, a result of the current assessment may then be stored in the state memory circuit135by coupling the state memory circuit135to the output of the sense amplifier150. Then the state memory circuit135may again be coupled to the FB DRAM cell110, and the result of the current assessment of the FB DRAM cell110, or a manipulated result, for example, in a write access, may be stored back into the FB DRAM cell110.

FIG. 2shows a further embodiment of a memory chip200with a first FB DRAM cell210and a second FB DRAM cell212. The memory chip200further includes a sense amplifier220with an input, which can be coupled to the first FB DRAM cell210and the second FB DRAM cell212, and an output. Furthermore, the memory chip200includes a first state memory230, which can be coupled to the output of the sense amplifier220and the first FB DRAM cell210, as well as a second state memory232, which can be coupled to the output of the sense amplifier220and the second FB DRAM cell212.

Between the individual components,FIG. 2shows a series of switches, which can be used for coupling the components. Furthermore,FIG. 2shows a word line (WL) and two bit lines (BL), which are connected to the FB DRAM cells210and212. If an access to the memory chip200takes place, at first all switches are in the open position, as this is also illustrated inFIG. 2. If an access takes place, at first a read signal can be given onto the word line (WL), and the switch240can be closed. The input of the sense amplifier220then is connected to the first FB DRAM cell210and can make a current assessment. The sense amplifier220may then provide at its output a signal reflecting the state of the FB DRAM cell210, and which may be taken over into the state memory230by closing the switch250. The state memory230in turn is connected via the switch260to a data line, which is illustrated as a dashed line inFIG. 3. Access to the memory chip200may take place via the state memory by closing the switch260. If the state read out from the FB DRAM cell210is in the state memory230, the switches250and240can be opened again. By closing the switch270, the state memory can be coupled to the FB DRAM cell. By applying a write signal to the word line (WL), a state can thus be taken over into the FB DRAM cell210from the state memory230, be it the original state or a manipulated state.

An analog procedure would be possible in the embodiment of the memory chip200illustrated inFIG. 2with respect to the FB DRAM cell212. At first, it is assumed that all switches are open. By closing the switch242, the FB DRAM cell can be connected to the input of the sense amplifier220. The sense amplifier220may perform a current assessment and output same at its output, the output of the sense amplifier220may in turn be connected to the state memory232via the switch252, so that now the state of the FB DRAM cell212can be stored there. The switches242and252may then be opened again. Access to the state memory may be done via the data line indicated in dashed manner and the switch262. By closing the switch272, the state memory232can be coupled to the FB DRAM cell212, and by applying a write signal on the word line (WL), the state, be it the original or a manipulated state, can be taken over into the FB DRAM cell212.

In embodiments, the FB DRAM cells210and212may thus be formed to take over a stored state when coupled to a state memory230and232, respectively, if the FB DRAM cells210and212obtain a write signal.

In embodiments, hence, the state memories230and232may be formed to store a state of the output when coupled to the output of the sense amplifier220.

In further embodiments, the sense amplifier220may be formed to perform a current assessment when coupled to an FB DRAM cell210or212and provide a signal based on the state of the FB DRAM cell210or212at the output.

In further embodiments, the memory chip200may further comprise an interface, which can be coupled to the state memories230or232, and via which the state memories230and232are readable or writable.

FIG. 3shows a block circuit diagram of a further embodiment of a memory chip200.FIG. 3shows a first FB DRAM cell210and a second FB DRAM cell212, which can be connected to an input of the sense amplifier220via a switch280. The output of the sense amplifier220may then selectively be connected to a first state memory230or a second state memory232, wherein this may be done via the two switches290and292inFIG. 3.

For reading out the first FB DRAM cell210, it is coupled to the input of the sense amplifier220via the switch280, it may then perform a current assessment and provide an output signal based on a result of the current assessment at its output. The output of the sense amplifier220may then be connected via the switch290to a first state memory230, which then stores the state of the FB DRAM cell210. The state memory230may then be externally read out or manipulated. Via the switch290, the state memory230can be coupled to the first FB DRAM cell210, whereupon a state from the state memory230can be written into the FB DRAM cell210. Analogous operations apply for the right side ofFIG. 3, where the second FB DRAM cell212can be connected to the input of the sense amplifier220via the switch280. The sense amplifier220may then perform a current assessment of the second FB DRAM cell212and provide a corresponding signal at its output. Via the switch292, the output of the sense amplifier220may then be connected to the second state memory232, in which then the state of the second FB DRAM cell212may the stored. In the second state memory232, the state may then be read or manipulated. By switching over the switch292, the second state memory232can be connected to the second FB DRAM cell212so as to store the state again.

FIG. 4shows an embodiment of an apparatus400for exchanging binary data. The apparatus includes an FB DRAM array410with a plurality of FB DRAM cells410, which may be addressable via a read signal, via a write signal or an idle signal.

The apparatus400includes a reading means420for determining a state of an FB DRAM cell. Furthermore, the apparatus400includes a plurality of state memories430, wherein a state memory may be formed for storing a state of an FB DRAM cell. The apparatus400comprises a controller440, which is formed for receiving an activation signal, an FB DRAM address of a read command or write command. The controller440is formed to control the FB DRAM array410at the FB DRAM address with the read signal upon reception of the activation signal and the FB DRAM address, and otherwise, i.e., at other addresses not corresponding to the FB DRAM address, control same with the idle signal, couple the reading means to the FB DRAM cells410of the FB DRAM array of the FB DRAM address and store the states of the FB DRAM cells410of the FB DRAM address in the state memories430, wherein the controller440is further formed to provide the states from the state memories430when receiving the read command, and, when receiving the write command, to receive new states and store same in the state memories430, couple the state memories430to the FB DRAM cells410of the FB DRAM address, and control the FB DRAM cells410of the FB DRAM address with the write signal.

The apparatus400may comprise state memories430that in turn include, e.g., two inversely coupled inverters. The state memories430may thus, for example, be realized as flip-flop or latch. The apparatus400may further comprise an interface for external communication of the state memories430. Furthermore, in embodiments, the FB DRAM cells of the FB DRAM array410may be formed to receive various voltages as read signal, write signal or idle signal.

FIG. 5shows a flow chart of an embodiment of a method for exchanging data with an FB DRAM array. The method, for example, begins with a step505of receiving an activation signal. The step is followed by a loop, which realizes sequential readout of a group of FB DRAM cells. The loop begins with a step510of connecting the FB DRAM cell to an input of a reading means. Subsequently, in a step515, a current assessment of the FB DRAM cell may be performed by a state of an output signal of the reading means. In the next step520, the state of the output signal of the reading means can be stored in a state memory. Subsequently, the FB DRAM cell can be disconnected from the input of the reading means in a step525. If the group is read out completely, the step530is followed by reading or writing the state memory in the step535. If the group of the FB DRAM cells has not yet been read out completely, step530is again followed by the step510for connecting the next FB DRAM cell of the group to the reading means etc. The step of reading or writing the state memory535may then be followed by connecting the state memory to the FB DRAM cells in step540.

In embodiments, the step of connecting the FB DRAM cells to the input of the reading means may be followed or preceded by a step of providing a read voltage to the FB DRAM cell. In general, in embodiments, the step of sequentially reading out, that is the loop inFIG. 5, may take place periodically, for example, within the scope of a refresh cycle. Then, but also in other embodiments, the step of connecting the state memories540to the FB DRAM cells may be followed or preceded by a step of providing a write voltage to the FB DRAM cell.

There are several ways of operating an array of FB DRAM cells. In the so-called “snap-back” variant, for example, the gate voltage of a transistor, the gate of which is, for example, connected to the word lines (WL), can, for example, take on three states. In embodiments, for example, a voltage of about U1=−1.1 V for reading, about U2=1.5 V for writing and about U3=−1.4 V for the idle, i.e., the inactive state, could be used. FB DRAMs may, for example, be different in this property with respect to other DRAMs, where the information may, for example, be stored in a capacitance connected to a selection transistor. As already mentioned above, this can mean that the type of access should be known prior to the memory access. Furthermore, it is to be noted that, when a word line is brought into a write state, the data of the bit lines is taken over, that is it should be in the desired state, because otherwise wrong data might be stored into the cells.

FIG. 6illustrates an embodiment of an FB DRAM memory cell arrangement. In the upper part ofFIG. 6, an FB DRAM cell structure can be seen, wherein three bit lines610,612and614run horizontally. Along each of the three bit lines610,612and614illustrated, there are four transistors each, the gates of which are each coupled to the four word lines620,622,624and626. Furthermore,FIG. 6shows three reference potential lines630,632and634in the arrangement. In the lower part ofFIG. 6, there is further illustrated a table that associates corresponding voltages on the word lines (WL) and bit lines (BL), respectively, with the four actions of writing a zero (write “0”), writing a 1 (write “1”), reading out (“read”) and idle (“idle”). Embodiments generally are not limited to the designated values, the designated values only represent an example for illustrating the procedure in FB DRAM cells.

Reading out FB DRAM cells may, for example, be based on the evaluation of the cell current, wherein current evaluation circuits may generally be bulky and do not lead to an “on-pitch” layout. Furthermore, by the current evaluation, an unfavorably high power level on a memory chip may result if many FB DRAM cells are read out at the same time, because the corresponding currents add. FB DRAMs may be regarded as volatile memories in an embedded region and also as a smaller cell alternative for stand-alone memories. Embodiments allow for a DRAM-compatible interface for FB DRAM memory chips. For communication, in embodiments, DRAM-specific commands may thus be implemented in an FB DRAM architecture.

Embodiments may, for example, provide for the fact that, upon an activation signal, the word lines are already brought to a voltage level provided for reading out the FB DRAM cells. Here, in embodiments, all cells belonging to a word line may be read. Embodiments allow sequential reading for those cells sharing the same read circuit, for example, a sense amplifier. Embodiments thus permit the temporal distribution of the current on the memory chip, since the individual memory cells are read out sequentially. This may lead to more favorable power levels as compared with other systems. In embodiments, the results of the sequential read out may then be stored into parallel state memories or latches. In embodiments, further reading and writing may now take place from these latches or state memories, wherein this may take place with the same speed as it is usually enabled by other DRAMs. In embodiments, after reading out the FB DRAM cell states, the word line can also be brought into the write state, which may enable a refresh function (refresh operation).

FIG. 7shows a further embodiment of a memory chip700. In the upper part, the memory chip700includes a group710of bit lines712,714and716. The number of bit lines here is only exemplarily illustrated as three, memory chips may in general also include any other numbers of bit lines. Furthermore, in the lower part, a second group720of bit lines722,724and726is illustrated. In the upper part of the memory chip700, there also is a state memory713,715and717for each bit line, wherein the state memories may, for example, also be realized as a latch. In the lower group720, the state memories are designated with723,725and727. For each group,FIG. 7further shows a sense amplifier730and740, respectively. Furthermore, inFIG. 7, four word lines750,752,754and756are illustrated.

FIG. 7illustrates that bit lines, e.g.,712,714and716, which belong to an array segment, can be divided into a group710. The bit lines in one group may share one and the same reading circuit, that is a sense amplifier730. In further embodiments, the read amplifiers730may also be switched between groups of adjacent array segments. This is not illustrated inFIG. 7. Embodiments may, however, also provide for the fact that, for example, the sense amplifier730can be switched to the place of the sense amplifier740via switches, wherein then the sense amplifier740could be omitted. Furthermore,FIG. 7shows that a state memory is associated with each bit line. In embodiments, bit lines from adjacent array segments may optionally share a state memory. This also is not shown in the embodiment ofFIG. 7, but it would be possible for the state memory713to be switched into another segment via a switch, unless the bit line712is used.

FIG. 8shows an excerpt of a realization of an embodiment of a memory chip800.FIG. 8shows a word line810, as well as two bit lines820and822, wherein in the embodiment ofFIG. 832 bit lines are assumed, and the bit line820corresponds to the first bit line and the bit line822to the 32ndone, which is also indicated inFIG. 8by the designations BL0and BL31.FIG. 8further shows two state memories830and832, which can be coupled into the bit lines820and822, respectively, and which are realized in form of latches with inversely coupled inverters.FIG. 8further shows a sense amplifier840, the input of which also is designated with MBL_in, its output being designated with SA_out. Furthermore,FIG. 8shows a data line850, as well as a plurality of switches, which will be explained in greater detail in the following. At first, it is to be assumed that all switches are open.

If an activation signal is received, all 32 bit lines or FB DRAM cells are to be read out sequentially in this embodiment. To this end, at first a read signal is given onto the word line810. By closing the switch860, the bit line820can be connected to the input of the sense amplifier840. At the output of the sense amplifier840, then a signal, which reflects the state of the bit line820and which can be coupled to the state memory830via the switch870, is available. Thus, the state of the bit line820can be stored in the state memory830. Subsequently, the switches860and870can be opened again.

In a next step, the subsequent bit lines can be read out in analog manner. At the example of the bit line820, thus the switch862is closed in order to connect the bit line822to the input of the sense amplifier840. The sense amplifier may then be coupled to the state memory832with the switch872so as to store the state of the bit line822in the state memory832. Subsequently, the two switches862and872can be opened again. In order to be able to read out the states from the state memories830and832now, these can be connected to the corresponding data lines850via the switches880and882, respectively. In the same manner, data may also be written from the data lines850into the state memories830and832, respectively. By opening the switches880and882, respectively, the state memories may then again be disconnected from the data lines850.

By closing the switches890and892, respectively, and applying a write signal to the word line810, the FB DRAM cells may now again be written to, be it for refresh reasons or for storing new data.

Following the protocols of the DRAMs, the functioning of an embodiment may also be described with DRAM commands. For example, the ACT (activation signal) command is received. On the basis of the embodiment ofFIG. 8, all 32 bit lines may then be, e.g., sequentially read with the same read circuit, that is the sense amplifier840, and the corresponding data stored in the hold latches, that is the state memories830to832. In embodiments, this operation could take place, for example, in parallel in all blocks the bit lines of which belong to the same page. The sequence may, for example, consist of several steps. Subsequently, an iteration will be described on the basis of the bit line820, this sequence can be performed for all 32 bit lines in an analogous manner. It is assumed that all switches are open at first and the switch860is closed then. Thus, the bit line820is connected to the sense amplifier840, so that it can assess the current value of the FB DRAM cell.

Subsequently, the switch860is switched off again, and the switch870is switched on. The output of the sense amplifier840may thus be stored in the hold latch, i.e., the state memory830. Now the switch870may be opened again, and the switch890may be closed. Thus, the state memory830now is connected to the bit line820. If the word line810is brought to a write voltage at the end of this read operation, a refresh of the page can be performed in embodiments.

Optionally, in other embodiments, the word line could be brought to the idle state at the end of the read operation. Writing back the data could, for example, be performed during a precharge command. A read command may thus be performed in embodiments similar to other DRAMs. The data lines850, or data bus, can be connected to the latches, i.e., the state memories830, via the switches880, and thus the data can be made available. In embodiments, a write command may now take place by taking over data of the data line850into the corresponding state memories830. In one embodiment, the data may then actually be written into the cells, when the word line810is brought to the write state. Otherwise, the writing back could also take place in the precharge. A memory refresh then, for example, could only take place by an activation signal or an activation signal and a precharge signal. Optionally, in the embodiment, during a precharge command, the switches890could be activated, and the word line810could be brought into the write state.

Embodiments of memory chips thus may replace DRAMs, since they may have the same command structure and thus may be made compatible. Furthermore, embodiments can be operated in a more power-efficient manner due to the state memory used, which may allow for sequential readout of the FB DRAM cells with only one sense amplifier, since the cell currents can be distributed temporally. Furthermore, embodiments may provide a higher access speed, since it may not need to wait for whether data is written or read. In embodiments, the data may already be held in the state memories upon arrival of this command.

In particular, it is pointed out that, depending on the conditions, the inventive scheme may also be implemented in software. The implementation may be on a digital storage medium, in particular a floppy disc, a CD, a DVD or the like, with electronically readable control signals capable of cooperating with a programmable computer system so that the corresponding method is executed. In general, the invention may thus also be implemented in a computer program product with a program code stored on a machine-readable carrier for performing the inventive method, when the computer program product is executed on a computer. In other words, the invention may thus be realized as a computer program with a program code for performing the method, when the computer program product is executed on a computer.