Semiconductor device and manufacturing method thereof

A semiconductor device includes a first chip and a second chip bonded to the first chip. The first chip includes: a substrate; a logic circuit disposed on the substrate; and a plurality of first dummy pads that are disposed above the logic circuit, are disposed on a first bonding surface where the first chip is bonded to the second chip, the plurality of first dummy pads not being electrically connected to the logic circuit. The second chip includes a plurality of second dummy pads disposed on the plurality of first dummy pads and a memory cell array provided above the plurality of second dummy pads. A coverage of the first dummy pads on the first bonding surface is different between a first region and a second region, the first region separated from a first end side of the first chip, the second region disposed between the first end side and the first region.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-030950, filed Feb. 26, 2020, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device and a manufacturing method thereof.

BACKGROUND

When a semiconductor device is manufactured by bonding metal pads of a plurality of wafers, defects such as voids may occur in an interlayer insulating film in which the metal pads are embedded.

DETAILED DESCRIPTION

At least one embodiment provides a semiconductor device capable of reducing defects in an insulating film in which pads are embedded, and a manufacturing method thereof.

In general, according to at least one embodiment, a semiconductor device includes a first chip and a second chip bonded to the first chip. The first chip includes a substrate; a logic circuit disposed on the substrate; and a plurality of first dummy pads that are disposed above the logic circuit, are provided on a first bonding surface where the first chip is bonded to the second chip, with the plurality of first dummy pads not being electrically connected to the logic circuit. The second chip includes a plurality of second dummy pads disposed on the plurality of first dummy pads and a memory cell array disposed above the plurality of second dummy pads. A coverage of the first dummy pads on the first bonding surface is different between a first region and a second region, the first region separated from a first end side of the first chip, the second region disposed between the first end side and the first region.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. InFIGS. 1 to 14, the same components are denoted by the same reference numerals, and a repetitive description thereof will be omitted.

First Embodiment

FIG. 1is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment. The semiconductor device ofFIG. 1is a three-dimensional memory in which an array chip1and a circuit chip2are bonded. The circuit chip2is an example of the first chip, and the array chip1is an example of the second chip.

The array chip1includes a memory cell array11including a plurality of memory cells, an insulating film12on the memory cell array11, and an interlayer insulating film13under the memory cell array11. The insulating film12may be, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film13is, for example, a stacked film including a silicon oxide film or a silicon oxide film and another insulating film.

The circuit chip2is provided under the array chip1. Reference numeral S indicates a bonding surface between the array chip1and the circuit chip2. The bonding surface S is an example of the first bonding surface. The circuit chip2includes an interlayer insulating film14and a substrate15under the interlayer insulating film14. The interlayer insulating film14is, for example, a stacked film including a silicon oxide film or a silicon oxide film and another insulating film. The substrate15is, for example, a semiconductor substrate such as a silicon substrate.

FIG. 1shows an X direction and a Y direction, which are perpendicular to each other and parallel with a surface of the substrate15, and a Z direction that is perpendicular to the surface of the substrate15. In this specification, a +Z direction is taken as an upper direction and a −Z direction is taken as a lower direction. The −Z direction may or may not coincide with a gravity direction.

The array chip1includes a plurality of word lines WL and a source line SL as an electrode layer in the memory cell array11.FIG. 1shows a staircase structure portion21of the memory cell array11. Each word line WL is electrically connected to a word wiring layer23via a contact plug22. Each columnar portion CL penetrating the plurality of word lines WL is electrically connected to a bit line BL via a via plug24, and is electrically connected to the source line SL. The source line SL includes a first layer SL1which is a semiconductor layer and a second layer SL2which is a metal layer.

The circuit chip2includes a plurality of transistors31. Each transistor31includes a gate electrode32provided on the substrate15via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate15. Further, the circuit chip2includes a plurality of contact plugs33each provided on the gate electrode32, the source diffusion layer, or the drain diffusion layer of the transistor31, a wiring layer34provided on the contact plugs33and including a plurality of wirings, and a wiring layer35provided on the wiring layer34and including a plurality of wirings.

The circuit chip2may further include a wiring layer36provided on the wiring layer35and may include a plurality of wirings, a plurality of via plugs37provided on the wiring layer36, and a plurality of metal pads38provided on the via plugs37. The metal pad38is, for example, a Cu (copper) layer or an Al (aluminum) layer. The metal pad38is an example of a first pad (first active pad and first dummy pad). Details of the metal pad38will be described later. The circuit chip2functions as a control circuit (logic circuit) that controls an operation of the array chip1. The control circuit may include transistors31and the like, and is electrically connected to the metal pads38.

The array chip1includes a plurality of metal pads41provided on the metal pads38, and a plurality of via plugs42provided on the metal pads41. Further, the array chip1is provided on the via plugs42, and includes a wiring layer43including a plurality of wirings, and a wiring layer44provided on the wiring layer43and including a plurality of wirings. The metal pad41is, for example, a Cu layer or an Al layer. The metal pad41is an example of a second pad (second active pad and second dummy pad). Details of the metal pad41will be described later.

The array chip1further includes a plurality of via plugs45provided on the wiring layer44, a metal pad46provided on the via plugs45and the insulating film12, and a passivation film47provided on the metal pad46and the insulating film12. The metal pad46is, for example, a Cu layer or an Al layer, and functions as an external connection pad (bonding pad) of the semiconductor device ofFIG. 1. The passivation film47is, for example, an insulating film such as a silicon oxide film, and has an opening P that causes an upper surface of the metal pad46to be exposed. The metal pad46may be connected to a mounting substrate or another device through the opening P by a bonding wire, a solder ball, a metal bump, and the like.

FIG. 2is a cross-sectional view showing a structure of a columnar portion CL according to the first embodiment.

As shown inFIG. 2, the memory cell array11includes a plurality of word lines WL and a plurality of insulating layers51alternately stacked on the interlayer insulating film13(FIG. 1). The word line WL is, for example, a W (tungsten) layer. The insulating layer51is, for example, a silicon oxide film.

The columnar portion CL successively includes a block insulating film52, a charge storage layer53, a tunnel insulating film54, a channel semiconductor layer55, and a core insulating film56. The charge storage layer53is, for example, a silicon nitride film, and is formed on a side surface of the word lines WL and the insulating layers51via the block insulating film52. The charge storage layer53may be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer55is, for example, a polysilicon layer, and is formed on a side surface of the charge storage layer53via the tunnel insulating film54. The block insulating film52, the tunnel insulating film54, and the core insulating film56are, for example, silicon oxide films or metal insulating films.

FIGS. 3 and 4are cross-sectional views showing a manufacturing method of the semiconductor device according to the first embodiment.

FIG. 3shows an array wafer W1including a plurality of array chips1, and a circuit wafer W2including a plurality of circuit chips2. The array wafer W1is also referred to as a “memory wafer”, and the circuit wafer W2is also referred to as a “CMOS wafer”. The circuit wafer W2is an example of a first wafer, and the array wafer W1is an example of a second wafer.

The orientation of the array wafer W1ofFIG. 3is opposite to the orientation of the array chip1ofFIG. 1. In at least one embodiment, the array wafer W1and the circuit wafer W2are bonded together to manufacture the semiconductor device.FIG. 3shows the array wafer W1before the orientation is reversed to bond, andFIG. 1shows the array chip1after the orientation is reversed to bond, and after bonding and dicing.

InFIG. 3, reference numeral S1indicates an upper surface of the array wafer W1, and reference numeral S2indicates an upper surface of the circuit wafer W2. The array wafer W1includes a substrate16provided under the insulating film12. The substrate16is, for example, a semiconductor substrate such as a silicon substrate. The substrate15is an example of a first substrate, and the substrate16is an example of a second substrate.

In at least one embodiment, first, as shown inFIG. 3, the memory cell array11, the insulating film12, the interlayer insulating film13, the staircase structure portion21, the metal pad41, and the like are formed on the substrate16of the array wafer W1, and the interlayer insulating film14, the transistor31, the metal pad38, and the like are formed on the substrate15of the circuit wafer W2. For example, the via plug45, the wiring layer44, the wiring layer43, the via plug42, and the metal pad41are sequentially formed on the substrate16. Further, the contact plug33, the wiring layer34, the wiring layer35, the wiring layer36, the via plug37, and the metal pad38are sequentially formed on the substrate15. Next, as shown inFIG. 4, the array wafer W1and the circuit wafer W2are bonded together by a mechanical pressure. Accordingly, the interlayer insulating film13and the interlayer insulating film14are bonded. Next, the array wafer W1and the circuit wafer W2are annealed at 400° C. Accordingly, the metal pad41and the metal pad38are joined together.

Thereafter, the array wafer W1and the circuit wafer W2are cut into a plurality of chips after the substrate15is thinned by chemical mechanical polishing (CMP) and the substrate16is removed by CMP. Accordingly, the semiconductor device inFIG. 1may be manufactured.FIG. 1shows the circuit chip2including the metal pad38and the array chip1including the metal pad41disposed on the metal pad38. The metal pad46and the passivation film47are formed on the insulating film12, for example, after the substrate15is thinned and the substrate16is removed.

Although the array wafer W1and the circuit wafer W2are bonded together in at least one embodiment, the array wafers W1may be bonded together instead. The contents described above with reference toFIGS. 1 to 4and contents described later with reference toFIGS. 5 to 14are also applicable to bonding of the array wafers W1to each other.

AlthoughFIG. 1shows a boundary surface between the interlayer insulating film13and the interlayer insulating film14, and a boundary surface between the metal pad41and the metal pad38, it is common that these boundary surfaces are not observed after the annealing. However, positions of these boundary surfaces can be estimated by detecting, for example, an inclination of a side surface of the metal pad41or a side surface of the metal pad38, or a positional deviation between the side surface of the metal pad41and the metal pad38.

The semiconductor device of at least one embodiment may be a target of a transaction in a state ofFIG. 1after being cut into the plurality of chips, or a target of a transaction in a state ofFIG. 4before being cut into the plurality of chips.FIG. 1shows the semiconductor device in a chip state, andFIG. 4shows the semiconductor device in a wafer state. In at least one embodiment, a multi-chip-shaped semiconductor device (FIG. 1) is manufactured from one wafer-shaped semiconductor device (FIG. 4).

Hereinafter, the circuit wafer W2of at least one embodiment will be described in detail with reference toFIGS. 5 to 14, and specifically, the arrangement of the metal pads38of at least one embodiment will be described in detail. The following description is also applicable to the array wafer W1of at least one embodiment and the arrangement of the metal pads41of at least one embodiment.

FIG. 5is a plan view schematically showing a structure of the circuit wafer W2according to the first embodiment.

As shown inFIG. 5, the circuit wafer W2of at least one embodiment includes a plurality of chip regions R1arranged in a two-dimensional array and a dicing region R2surrounding the chip regions R1. The dicing region R2has a shape including a plurality of dicing lines extending in the X direction and a plurality of dicing lines extending in the Y direction.FIG. 5further shows a boundary line (boundary surface) E between the chip region R1and the dicing region R2.

The circuit wafer W2of at least one embodiment is bonded to the array wafer W1and then cut into the plurality of chips. At this time, the circuit wafer W2is processed by cutting the dicing region R2with a dicing blade. Each chip obtained by cutting includes one chip region R1of the circuit wafer W2and one similar chip region of the array wafer W1. In this case, the boundary surface E is an end surface (end side) of each chip. The end surface of each chip includes a side surface of the substrate15and a side surface of the interlayer insulating film14. The end side is an example of the first end side.

FIGS. 6A and 6Bare cross-sectional views showing a problem of the circuit wafer W2according to the first embodiment.

FIG. 6Ashows a cross section of the chip region R1and the dicing region R2of the circuit wafer W2. In at least one embodiment, after the metal pad38is embedded in the interlayer insulating film14, a surface of the metal pad38is flattened by CMP. At this time, when a slurry having a large polish rate ratio (Cu/SiO2) between the metal pad38and the interlayer insulating film14is used for CMP, dishing which is a phenomenon that the surface of the metal pad38is dented, and an inclination of the surface of the chip region R1(see,FIG. 6A) may occur.

FIG. 6Balso shows the cross section of the chip region R1and the dicing region R2of the circuit wafer W2. The dishing and the inclination described above can be reduced by using slurry having a small polish rate ratio (Cu/SiO2) between the metal pad38and the interlayer insulating film14for CMP. In this case, however, since the interlayer insulating film14is more easily scraped, a void may be formed in the interlayer insulating film14in a region where a density of the metal pads38is low.FIG. 6Bshows a void V formed in the dicing region R2where the metal pad38is not disposed. It is desirable to reduce the formation of such a void V.

FIG. 7is a plan view showing the structure of the circuit wafer W2according to the first embodiment.FIG. 7shows an XY cross section passing through the metal pad38in the circuit wafer W2, for example, an XY cross section of the bonding surface S between the array wafer W1and the circuit wafer W2.

FIG. 7shows one chip region R1and the dicing region R2surrounding the chip region R1. As shown inFIG. 7, the chip region R1of at least one embodiment includes a plurality of active regions R1aand a plurality of dummy regions R1b, R1c, and R1d.

The active region R1aincludes the plurality of metal pads38called active pads. On the other hand, the dummy regions R1b, R1c, and R1dinclude the plurality of metal pads38called dummy pads. The active pad is a pad used for transmitting signals and electric power for operating the semiconductor device, and the dummy pad is an unused pad for transmitting signals and electric power for operating the semiconductor device. The active pad is electrically connected to a circuit element (for example, the memory cell array11and the transistor31) in the semiconductor device, but the dummy pad is not electrically connected to the circuit element in the semiconductor device. The dummy pad is disposed to, for example, adjust the density of the metal pads38on the bonding surface S.

The dummy regions R1b, R1c, and R1dof at least one embodiment are the dummy region R1bdisposed around the active region R1a, the dummy region R1cdisposed at a central portion in the chip region R1, and the dummy region R1ddisposed at a peripheral portion in the chip region R1. These dummy regions R1b, R1c, and R1dinclude the metal pads38with different densities, as described later.

Next, a coverage (an extent of coverage) of the metal pads38in the XY cross section shown inFIG. 7will be described. For example, the coverage of the metal pads38in the chip region R1is a percentage (%) of a total area (Sa) of the metal pads38in the chip region R1with respect to a total area (Sb) of the chip region R1, and is represented by Sa÷Sb×100. The coverage of the metal pads38is a value corresponding to the density of the metal pads38in each region.

The active region R1aand the dummy regions R1b, R1c, and R1dof at least one embodiment have predetermined coverages. Specifically, the coverage of the metal pads38in the active region R1ais 10 to 40%, for example 25%. The coverage of the metal pads38in the dummy region R1bis 10 to 40%, for example 25%. The coverage of the metal pads38in the dummy region R1cis 10 to 40%, for example, about 20%. The coverage of the metal pads38in the dummy region R1dis 5 to 20%, for example, about 10%.

The dummy region R1dof at least one embodiment has a ring shape surrounding the active region R1aand the dummy regions R1band R1c, and is adjacent to the dicing region R2. On the other hand, the active region R1aand the dummy regions R1band R1cof at least one embodiment are surrounded by the dummy region R1dand separated from the dicing region R2. In other words, the dummy region R1dis adjacent to the boundary line E, and the active region R1aand the dummy regions R1band R1care separated from the boundary line E.

In addition, the coverage of the metal pads38in the dummy region R1dof at least one embodiment is different from the coverages of the metal pads38in the active region R1aand the dummy regions R1band R1c, and more specifically, is lower than the coverages of the metal pads38in the active region R1aand the dummy regions R1band R1c. Accordingly, for example, a depth of the void V forming in the dicing region R2can be reduced (see,FIGS. 6A and 6B). The reason is that by lowering the coverage of the metal pads38in the dummy region R1d, a difference in coverage between the dummy region R1dand the dicing region R2can be reduced, and a change in the density of the metal pads38in a vicinity of the boundary line E can be reduced. The dicing region R2of at least one embodiment includes an alignment mark formed of metal, and does not include the metal pad38. The coverage of the metal pads38in the dicing region R2is 0%. The dummy regions R1band R1care examples of the first region, the dummy region R1dis an example of the second region, and the active region R1ais an example of a third region.

As described above, the coverage of the metal pads38in the dummy region R1dof the at least one is lower than the coverages of the metal pads38in the active region R1aand the dummy regions R1band R1c. Accordingly, the depth of the void V forming in the dicing region R2can be reduced. In order to effectively reduce the depth of the void V, a ratio of the coverage in the dummy region R1cto the coverage in the dummy region R1dis preferably set between 3:2 and 3:1. The ratio is similar to a ratio of the coverage in the dummy region R1bto the coverage in the dummy region R1dand a ratio of the coverage in the active region R1ato the coverage in the dummy region R1d. Further, a ratio of an average coverage in the active region R1aand the dummy regions R1band R1cto the coverage in the dummy region R1dis also preferably set between 3:2 and 3:1.

Further, in at least one embodiment, the coverage in the dummy region R1band the coverage in the dummy region R1bare equal to or less than the coverage in the active region R1a. Specifically, the coverage in the dummy region R1badjacent to the active region R1ais the same as the coverage in the active region R1a, and the coverage in the dummy region R1cseparated from the active region R1ais less than the coverage in the active region R1a. Accordingly, for example, the coverage can be gradually reduced from the active region R1ato the dummy region R1d. The dummy region R1bis an example of a first coverage region, and the dummy region R1cis an example of a second coverage region.

The coverage in each region can be changed, for example, by changing a size of the metal pad38or changing a pitch between the metal pads38. The arrangement of the metal pads38in the active region R1aand the dummy regions R1band R1cof at least one embodiment will be described later.

FIG. 7further shows a shortest distance T between the dummy region R1band the dicing region R2. The shortest distance T is, for example, 5 μm or more. On the other hand, a ring width of the dummy region R1dhaving the ring shape is generally, for example, 100 μm. InFIG. 7, numerous dummy regions R1bare surrounded by the dummy regions R1c, and a part of the dummy regions R1bprotrude from the dummy region R1cand are adjacent to the dummy region R1d. Therefore, the above-described shortest distance T can be shorter than the ring width of the dummy region R1d. From another point of view, the ring width of the dummy region R1dis generally 100 μm, but is shorter than 100 μm in a vicinity of the above part of the dummy regions R1b.

FIG. 8is a plan view showing structures of the active region R1aand the dummy region R1baccording to the first embodiment.

FIG. 8shows the metal pads38in the active region R1aand the metal pads38in the dummy region R1b. InFIG. 8, these metal pads38are arranged in a square or rectangular grid shape, and the coverage in the active region R1aand the coverage in the dummy region R1bare both set to 25%. Reference numeral U indicates a unit region of the above grid. An area of one unit region U is four times an area of one metal pad38, and as a result, the coverage in the active region R1aand the dummy region R1bis 25%.

FIG. 8further relates to the metal pads38in the active region R1aand the dummy region R1b, and shows a size Ax of each metal pad38in the X direction, a size Ay of each metal pad38in the Y direction, a pitch Bx between the metal pads38in the X direction, and a pitch By between the metal pads38in the Y direction. In at least one embodiment, these relationships are set as Ax=Ay and Bx=By.

FIG. 9is a plan view showing a structure of the dummy region R1caccording to the first embodiment.

FIG. 9shows the metal pads38in the dummy region R1c. InFIG. 9, these metal pads38are arranged in a triangular (or parallelogram) grid shape, and the coverage in the dummy region R1cis set to about 20%. The metal pads38in the dummy region R1care arranged at intersections of a plurality of first straight lines parallel to a straight line M1and a plurality of second straight lines parallel to a straight line M2. The first straight line is inclined with respect to the X direction, and the second straight line is inclined with respect to the Y direction.

FIG. 9further relates to the metal pads38in the dummy region R1c, and shows a size Cx of each metal pad38in the X direction, a size Cy of each metal pad38in the Y direction, a pitch Dx between the metal pads38in the X direction, and a pitch Dy between the metal pads38in the Y direction, a shift amount Ex between the metal pads38in the X direction, and a shift amount Ey between the metal pads38in the Y direction. In at least one embodiment, these relationships are set as Cx=Cy, Dy=Dz, and Ex=Ey. Further, in at least one embodiment, the size is set to Ax=Cx, and the pitch is set to Bx≠Dx.

Thus, between the dummy region R1band the dummy region R1c, the sizes of the metal pads38are the same in the X direction and in the Y direction, and the pitches between the metal pads38are different from each other. As a result, the coverages of the metal pads38are different from each other between the dummy region R1band the dummy region R1c. Between the dummy region R1band the dummy region R1c, the sizes of the metal pads38may be different from each other, and the pitches between the metal pads38may be the same, so that the coverages may be different from each other.

In at least one embodiment, the dummy region R1bis provided between the active region R1aand the dummy region R1c. Therefore, the coverage in the chip region R1does not decrease between the active region R1aand the dummy region R1b, but decreases between the dummy region R1band the dummy region R1c. Accordingly, it is possible to reduce the formation of a void at an end portion of the active region R1a. On the other hand, a void may be formed in a vicinity of a boundary between the dummy region R1band the dummy region R1c, and the dummy pads are disposed in the vicinity of the boundary between the dummy region R1band the dummy region R1c, but the active pad is not so disposed. Therefore, it is possible to prevent the void from adversely affecting the active pad and hindering the operation of the semiconductor device. This is because the dummy pad generally does not participate in the operation of the semiconductor device.

Hereinafter, an example of a method of determining the arrangement of the metal pads38in the dummy region R1cof the present embodiment will be described.

In at least one embodiment, during determining of the arrangement of the metal pads38in the dummy region R1c, a value of Cx (=Cy) is fixed and a value of Ex (=Ey) is changed to various values. Accordingly, since the coverage changes, the value of Ex at which a desired coverage is obtained is calculated. At this time, if the coverage is changed, directions in which the straight lines M1, M2extend change. As the coverage increases, that is, as Ex decreases, an angle of the straight line M1with respect to an X axis increases, and an angle of the straight line M2with respect to a Y axis also increases. As a result, an acute angle θ1between the straight line M1and the straight line M2decreases.

The reason why the arrangement of the metal pads38in the dummy region R1cis determined by such a method, according to at least one embodiment, is that it is desirable that the directions in which the straight lines M1, M2extend are different from the X direction and the Y direction. In other words, a direction in which the metal pads38in the dummy region R1care arranged is offset from a direction in which the metal pads38in the active region R1aand the dummy region R1bare arranged, and thus the metal pads38are prevented from being continuously arranged in the same direction in the semiconductor device. As a result, a direction in which the metal pads38are arranged is discontinuous between the dummy region R1band the dummy region R1c. This is similar between the dummy region R1band the dummy region R1c. The reason is that the directions in which the straight lines M1, M2inFIG. 9extend are different from directions in which straight lines N1, N2(described later) inFIG. 10extend. For example, an acute angle θ2(described later) between the straight line N1and the straight line N2is different from the acute angle θ1between the straight line M1and the straight line M2.

Further, the reason why the metal pads38are prevented from being continuously arranged in the same direction in the semiconductor device, according to least one embodiment is as follows.

When the array wafer W1and the circuit wafer W2are bonded together, the bonding of the wafers progresses from a central portion to an end portion of each wafer (bonding progress). Here, a bonding progress speed of the wafer depends on the arrangement of the metal pads38,41.

Generally, the surfaces of the metal pads38,41are recessed with respect to surfaces of the interlayer insulating films14,13during bonding, and the bonding of the wafers progresses faster in a direction without the metal pads38,41(bonding progress speed is higher). This is because not many surfaces of the metal pads38,41exist, and many surfaces of the interlayer insulating films14,13exist in that direction. The metal pad38and the metal pad41are bonded (joined) by expansion of the metal pads38,41in an annealing treatment after bonding.

Therefore, if the metal pads38are continuously arranged in the same direction in the semiconductor device, the bonding progress speed in that direction is smaller than the bonding progress speed in other directions, and the bonding progress speed is uneven between the wafers. When the bonding progress speed is uneven between the wafers, the bonded region goes around a tip portion of the non-bonded region, and as a result, a void is formed between the wafers. Since the void hinders the joining between the metal pads38, when the active region R1ais in a vicinity of the void, a defect may occur in the semiconductor device.

The above is the reason that the metal pads38are prevented from being continuously arranged in the same direction in the semiconductor device according to at least one embodiment. According to the at least one embodiment, by offsetting the direction in which the metal pads38in the dummy region R1care arranged from the direction in which the metal pads38in the active region R1aand the dummy region R1bare arranged, it is possible to prevent the metal pads38from being continuously arranged in the same direction in the semiconductor device.

FIG. 10is a plan view showing a structure of the dummy region R1daccording to the first embodiment.

FIG. 10shows the metal pads38in the dummy region R1d. InFIG. 10, these metal pads38are arranged in a triangular (or parallelogram) grid shape, and the coverage in the dummy region R1dis set to about 10%. The metal pads38in the dummy region R1dare arranged at intersections of the plurality of first straight lines parallel to the straight line N1and the plurality of second straight lines parallel to the straight line N2. The first straight line is inclined with respect to the X direction, and the second straight line is inclined with respect to the Y direction.

FIG. 10further relates to the metal pads38in the dummy region R1d, and shows a size Fx of each metal pad38in the X direction, a size Fy of each metal pad38in the Y direction, a pitch Gx between the metal pads38in the X direction, and a pitch Gy between the metal pads38in the Y direction, a shift amount Hx between the metal pads38in the X direction, and a shift amount Hy between the metal pads38in the Y direction. In at least one embodiment, these relationships are set as Fx=Fy, Gx=Gy, and Hx=Hy. Further, in the present embodiment, the size is set to Cx=Fx, and the pitch is set to Dx≠Gx.

Thus, between the dummy region R1cand the dummy region R1d, the sizes of the metal pads38are the same in the X direction and in the Y direction, and the pitches between the metal pads38are different from each other. As a result, the coverages of the metal pads38are different from each other between the dummy region R1cand the dummy region R1d. Between the dummy region R1cand the dummy region R1d, the sizes of the metal pads38may be different from each other, and the pitches between the metal pads38may be the same, so that the coverages may be different from each other.

During manufacturing of the semiconductor device of the present embodiment, the metal pads38are formed in the interlayer insulating film14so as to realize the above-described coverage (see,FIG. 3). Accordingly, the coverages in the active region R1a, the dummy region R1b, the dummy region R1c, and the dummy region R1dare set to 25%, about 20%, and about 10%, respectively.

As a method of determining the arrangement of the metal pads38in the dummy region R1dof at least one embodiment, for example, the same method as in the case of the dummy region R1ccan be adopted. However, since the dummy region R1cand the dummy region R1dhave different coverages, the direction in which the straight lines M1, M2inFIG. 9extend and the direction in which the straight lines N1, N2inFIG. 10extend are different. According to at least one embodiment, by offsetting a direction in which the metal pads38in the dummy region R1dare arranged from the direction in which the metal pads38in the dummy region R1care arranged, it is possible to prevent the metal pads38from being continuously arranged in the same direction in the semiconductor device.

FIG. 11is a plan view showing a structure of the vicinity of the boundary between the dummy region R1band the dummy region R1caccording to the first embodiment.

As shown inFIG. 11, a layout of the metal pads38changes in the vicinity of the boundary between the dummy region R1band the dummy region R1c. As a result, the coverage of the metal pads38changes between the dummy region R1band the dummy region R1c.

FIG. 12is a plan view showing a structure of a vicinity of a boundary between the dummy region R1cand the dummy region R1daccording to the first embodiment.

The circuit wafer W2of at least one embodiment includes the plurality of metal pads38arranged in a line along a boundary line (boundary surface) L between the dummy region R1cand the dummy region R1d. Accordingly, for example, it is possible to reduce an occurrence of a large space in which the metal pad38is not arranged between the dummy region R1cand the dummy region R1d. By reducing the occurrence of such a space, it is possible to reduce the formation of voids between the dummy region R1cand the dummy region R1d.

FIG. 13is a plan view showing a structure of a vicinity of a boundary between the dummy region R1dand the dicing region R2according to the first embodiment.

As shown inFIG. 13, the dummy region R1dincludes the metal pads38, but the dicing region R2does not include the metal pads38. However, the coverage in the dummy region R1dis set lower than the coverages in the active region R1a, the dummy region R1b, and the dummy region R1c. Therefore, according to at least one embodiment, the depth of the void V occurring in the dicing region R2can be reduced.

FIGS. 14A and 14Bare cross-sectional views showing an operation of the circuit wafer W2according to the first embodiment.

FIG. 14Ashows the void V when the coverage in the dummy region R1dis set to 25%.FIG. 14Bshows the void V when the coverage in the dummy region R1dis set to about 10%. According to at least one embodiment, by setting the coverage in the dummy region R1dto be low, the depth of the void V formed in the dicing region R2can be reduced.

As described above, the coverage of the metal pads38of at least one embodiment is different between the active region R1a, the dummy region R1b, and the dummy region R1c, which are separated from the dicing region R2, and the dummy region R1d, which is adjacent to the dicing region R2. For example, the coverage in the dummy region R1dis lower than the coverages in the active region R1a, the dummy region R1b, and the dummy region R1c. Therefore, according to at least one embodiment, it is possible to reduce the occurrence of the defect such as the large void V in the interlayer insulating film14in which the metal pads38are embedded. It is similar to the metal pad41and the interlayer insulating film13in the array wafer W1.