Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from an electrostatic discharge event at an input/output pin. The protection circuit includes a silicon-controlled rectifier having a well and an anode in the well. The anode is coupled with the input/output pin. The protection circuit further includes a control circuit coupled with the well. The control circuit is configured to supply a first control logic voltage to the well that places the silicon-controlled rectifier in a blocking state, and a second control logic voltage to the well that places the silicon-controlled rectifier in a low impedance state. When placed in its low impedance state, the silicon-controlled rectifier is configured to divert current from the electrostatic discharge event at the input/output pin away from the integrated circuit.

BACKGROUND

The invention generally relates to semiconductor manufacturing and integrated circuits and, more particularly, to circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from electrostatic discharge.

Electrostatic discharge (ESD) events can direct potentially large and damaging ESD currents to the sensitive integrated circuits of a chip. An ESD event involves an electrical discharge from a source, such as the human body or a metallic object, over a short duration and can deliver a large amount of current to the integrated circuit. An ESD protection circuit can be utilized to protect the integrated circuits of the chip from ESD events. During an ESD event, the ESD protection circuit triggers a shunting device, such as a silicon-controlled rectifier, to enter a low-impedance, conductive state. The ESD current is directed through the shunting device to ground and thereby diverted away from the integrated circuit. The ESD protection circuit maintains the shunting device in its conductive state until the ESD current is drained and the ESD voltage is discharged to an acceptable level.

Improved circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as improved methods of protecting an integrated circuit from electrostatic discharge, are needed.

SUMMARY

In an embodiment of the invention, a method is provided for operating a protection circuit to protect an integrated circuit from an electrostatic discharge event at an input/output pin. The method includes, when the protection circuit is powered, supplying a first control logic to a well that includes an anode of a silicon-controlled rectifier such that the silicon-controlled rectifier is placed in a blocking state. The method further includes, when the protection circuit is unpowered, supplying a second control logic to the well that places the silicon-controlled rectifier in a low impedance state.

In an embodiment of the invention, a protection circuit is provided for protecting an integrated circuit from an electrostatic discharge event at an input/output pin. The protection circuit includes a silicon-controlled rectifier having a well and an anode in the well. The anode is coupled with the input/output pin. The protection circuit further includes a control circuit coupled with the well. The control circuit is configured to supply a first control logic to the well that places the silicon-controlled rectifier in a blocking state, and a second control voltage to the well that places the silicon-controlled rectifier in a low impedance state. When placed in its low impedance state, the silicon-controlled rectifier is configured to divert current from the electrostatic discharge event at the input/output pin away from the integrated circuit.

In another embodiment of the invention, a method is provided for forming a protection circuit that protects an integrated circuit from an electrostatic discharge event at an input/output pin. The method includes forming an n-well in a substrate and an anode of a silicon controlled rectifier in the well, forming a control circuit, coupling the anode of the silicon controlled rectifier with the input/output pin, and coupling the well with an output of the control circuit.

DETAILED DESCRIPTION

With reference toFIG. 1and in accordance with an embodiment of the invention, an electrostatic discharge (ESD) protection circuit10for a chip generally includes a control circuit12and a shunting device in the form of an silicon-controlled rectifier14coupled with the control circuit12. The control circuit12is coupled between a positive power supply (VDD) rail16and a negative power supply (VSS) rail18. The VDDrail16is connected with a VDDpower pin17of the chip and the VSSrail18is connected with a VSSpower pin19of the chip. The negative power supply voltage at the VSSrail18may be ground potential. Internal circuits20of the chip, which are protected by the ESD protection circuit10, are also connected with the VDDrail16and VSSrail18.

The silicon-controlled rectifier14and the internal circuits20are coupled with an input/output pin22. When triggered by the control circuit12and clamped, the silicon-controlled rectifier14provides a low impedance path with a current-carrying capacity that is sufficient to dissipate the large current produced by an ESD event.

A diode24is coupled in series with the silicon-controlled rectifier14and the input/output pin22at a location in the ESD protection circuit10between the silicon-controlled rectifier14and the input/output pin22. An anode of the diode24is coupled with the input/output pin22and a cathode of the diode24is coupled with the anode of the silicon-controlled rectifier14. The diode24operates as a low-resistance ballast device to alleviate current surges at the time of power on. In an alternative embodiment, the diode24may be omitted from the construction of the ESD protection circuit10. The diode24may be comprised of abutting regions or layers of n-type and p-type semiconductor materials formed by, for example, masked ion implantations.

The silicon-controlled rectifier14may be represented by a parasitic PNP bipolar transistor26and a parasitic NPN bipolar transistor28that is cross-coupled with the PNP bipolar transistor26. The silicon-controlled rectifier14provides a relatively low on-resistance such that it can conduct high current at low voltages, a relatively low capacitance, and a relatively low leakage to limit power loss when the chip is powered. When the chip is powered, the silicon-controlled rectifier14is placed in a high-impedance state by the control circuit12and presents an elevated blocking voltage preventing inadvertent activation of the ESD protection circuit10.

When the chip transitions from a powered condition to an unpowered condition, the silicon-controlled rectifier14is activated by the control circuit12with little time delay. The silicon-controlled rectifier14is maintained in a state of readiness to enter its low-impedance, conducting state in response to the chip being unpowered. Upon the occurrence of an ESD event, the silicon-controlled rectifier14provides a low-impedance ESD current discharge path from the input/output pin22to the ground potential at the VSSrail18.

The silicon-controlled rectifier14may have a lateral device construction that includes doped semiconductor regions of alternating conductivity type formed in a semiconductor layer. The silicon-controlled rectifier14may include four doped semiconductor regions of alternating conductivity type and four electrodes or terminals, namely an anode30, a cathode32, an n-well contact33, and a p-well contact34, that are distributed among its doped semiconductor regions. In particular, one of the doped semiconductor regions may represent the anode30of the silicon-controlled rectifier14, and another of the doped semiconductor regions of opposite conductivity type may represent the cathode32of the silicon-controlled rectifier14. The PNP bipolar transistor26, which includes the anode30, is located in an n-well36formed in the semiconductor layer. The NPN bipolar transistor28, which includes the cathode32, is located in a p-well38formed in the semiconductor layer.

The n-well36is comprised of a region of the semiconductor layer doped with a dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or other available n-type dopant, in order to impart n-type conductivity to the semiconductor material. The n-well36may be formed by implanting ions comprising the dopant in the presence of a patterned ion-implantation mask that controls dopant introduction into the semiconductor layer during implantation. The implantation conditions (e.g., kinetic energy and dose) for forming the n-well36are selected to provide a desired dopant concentration (e.g., light doping) and may include multiple implantation conditions. After ion implantation is complete, the ion-implantation mask is removed by, for example, oxygen plasma ashing or wet chemical stripping.

The p-well38is comprised of a region of the semiconductor layer doped with a dopant, such as boron (B), aluminum (Al), gallium (Ga), or any other available p-type dopant, in order to impart p-type conductivity to the semiconductor material. The p-well38may be formed by implanting ions comprising the dopant in the presence of a patterned ion-implantation mask that controls dopant introduction into the semiconductor layer during implantation. The implantation conditions (e.g., kinetic energy and dose) for forming the p-well38are selected to provide a desired dopant concentration (e.g., light doping) and may include multiple implantation conditions. The p-well38may be formed by counterdoping a portion of the n-well36, or vice-versa. After ion implantation is complete, the ion-implantation mask is removed by, for example, oxygen plasma ashing or wet chemical stripping.

Doped regions of alternating conductivity type are formed in the n-well36and p-well38to define the anode30, cathode32, n-well contact33, and p-well contact34of the silicon-controlled rectifier14. Two of the doped regions are comprised of semiconductor material of the device region doped to have n-type conductivity. One of these doped regions is located in the n-well36and has the same conductivity type as the n-well36but is more heavily doped. The other of these doped regions is located in the p-well38and has the opposite conductivity type from the p-well38. This doped region operates as the cathode32of the silicon-controlled rectifier14. Two of the doped regions are comprised of semiconductor material of the device region doped to have p-type conductivity. One of these doped regions is located in the p-well38and has the same conductivity type as the p-well38but is more heavily doped. The other of these doped regions is located in the n-well36and has the opposite conductivity type from the n-well36. This doped region operates as the anode30of the silicon-controlled rectifier14. Each set of doped regions may be formed with an ion implantation process using a patterned mask, and the implantation conditions may be selected to provide a desired dopant concentration.

The control circuit12has an output40that is coupled with the n-well contact33to the n-well36. The control circuit12is configured to provide state control of the n-well36of the silicon-controlled rectifier14by supplying a logic 1 at the output40so that the n-well36is either biased at VDDor a logic 0 at the output40so that the n-well36is grounded to VSS. The discrete circuitry comprising the control circuit12may vary to provide the logic at the output40that supplies the state control over the n-well36.

When the chip and ESD protection circuit10are powered, the control circuit12supplies voltage from the VDDrail16to the output40and, therefore, a voltage level equal to logic 1 (high or VDD) from the VDDrail16to the n-well36. The silicon-controlled rectifier14is placed in a high-impedance blocking or “off” condition, which prevents triggering and reduces leakage current while the chip is powered.

The control circuit12is configured to operate such that the silicon-controlled rectifier14is placed into a low-impedance state awaiting the occurrence of an ESD event during unpowered time periods outside of normal circuit operation. When the chip and ESD protection circuit10are unpowered, the control circuit12couples the n-well36with ground at the VSSrail18so that a voltage level equal to logic 0 (low or VSS) from the VSSrail18is supplied to the n-well36. As a result, the silicon-controlled rectifier14is placed in its low-impedance or “on” condition and maintained in its low-impedance condition in anticipation of a positive ESD event at the input/output pin22.

The silicon-controlled rectifier14is thus turned on without time delay when the chip and ESD protection circuit10transition from a powered-on condition to a powered-off condition. When the ESD event occurs while the circuit is unpowered, a positive threshold voltage of approximately 0.5 volts is sufficient to trigger the NPN bipolar transistor28so that the ESD current is diverted by the silicon-controlled rectifier14away from the integrated circuits20and is instead conducted to ground at the VSSrail18.

The lowered positive threshold voltage of 0.5 volts represents an improvement over a diode string triggered silicon-controlled rectifier (DTSCR) that include multiple diodes needed to engineer the trigger voltage. Each diode in the string contributes a positive threshold voltage of 0.5 volts to the total trigger voltage, and each diode in the string introduces leakage current. The latter may limit the use of a DTSCR to low voltage applications of less than 1.5 volts.

In use and with reference toFIG. 1, the control circuit12supplies a voltage level equal to logic 1 (high or VDD) to the n-well36when the chip and control circuit12are initially powered to initiate normal circuit operation so that the silicon-controlled rectifier14is placed in its blocking (i.e., high impedance) condition. The optional diode24prevents mistriggering of the silicon-controlled rectifier14by current surges at the time of power on. The control circuit12persistently couples the n-well36with the VDDrail16during normal circuit operation so that the silicon-controlled rectifier14is maintained in its blocking condition. The reverse bias applied to the junction between the n-well36and anode30effectively isolates the input/output pin22from the silicon-controlled rectifier14. In its quiescent state, the silicon-controlled rectifier14restricts current conduction to any leakage current that may be present.

At the time of power off, the control circuit12connects the n-well36with a voltage level equal to logic 0 (low or VSS) so that the silicon-controlled rectifier14is concurrently placed into its low-impedance condition and maintained in its low-impedance condition in anticipation of a positive ESD event at the input/output pin22. Consequently, when the chip is not powered, the silicon-controlled rectifier14can be activated by a positive ESD event occurring at the input/output pin22. The turn-on voltage of silicon-controlled rectifier14at the time of the ESD event may be less than 0.6 volts. In its low impedance condition, the silicon-controlled rectifier14provides a current path for a duration sufficient to discharge the ESD current, thereby clamping the input/output pin22to the VSSrail18(i.e., to ground). The silicon-controlled rectifier14conducts current as long as the conducted current remains above its holding current. After the ESD event has dissipated and the conducted current drops below the holding current, one or both of the bipolar transistors26,28falls into cutoff mode, which returns the silicon-controlled rectifier14to its condition prior to the ESD event.

With reference toFIG. 2in which like reference numerals refer to like features inFIG. 1and in accordance with an embodiment of the invention, the control circuit12may have a double-stage inverter design with an inverter42having the output40coupled with the n-well36and an inverter44having an output coupled with the input of inverter42. The inverter42includes a p-channel field effect transistor (PFET)46and an n-channel field effect transistor (NFET)48that are coupled in series between the VDDrail16and the VSSrail18. The gates of the field effect transistors forming the inverter44are coupled with the VDDrail16. The inverter44functions to protect the gates of the PFET46and NFET48forming the inverter42. A parasitic capacitance45is defined by the wiring coupling the source and body of the PFET46with the VDDrail16, and due to any external power clamps that may exist between the VDDrail16and the VSSrail18.

When the chip is powered, the input to inverter44is a voltage level (i.e., VDD) equal to logic 1 (i.e., high logic) and the output from inverter44is a voltage level (i.e., VSS) equal to logic 0 (i.e., low logic). The PFET46is placed in its low-impedance condition in response to the application of VSSto its gate and, as a result, inverter42responds by outputting a logic signal with a voltage level (i.e., VDD) equal to logic 1 (i.e., high logic) at its output40. As a result, the n-well36, which is coupled with the output40, is biased at VDD, and the silicon-controlled rectifier14is placed in a blocking state.

When the chip is unpowered, the VDDrail16is logic 0 (i.e., low logic). As a result, the n-well36is coupled with ground at VSSso that the silicon-controlled rectifier14is concurrently placed into its low-impedance condition and maintained in its low-impedance condition in anticipation of a positive ESD event at the input/output pin22. The silicon-controlled rectifier14is able to react to an ESD event at the input/output pin22by entering its low-impedance state with negligible time delay.

The transistors of the inverters42,44may be formed on the chip by complementary metal oxide semiconductor (CMOS) processes in front end of line (FEOL) processing. Each of the field-effect transistors may includes a source in the semiconductor layer, a drain in the semiconductor layer, a gate electrode, and a gate dielectric layer positioned between the gate electrode and a region of the semiconductor layer between the source and drain that serves as a channel. The gate electrode may be comprised of a metal, a silicide, polysilicon, of combinations of these and other conductors formed by physical vapor deposition (PVD), CVD, etc. The gate dielectric layer may be comprised of a dielectric or insulating material such as silicon dioxide, silicon oxynitride, hafnium oxide, or layered combinations of these and other dielectric materials, formed by CVD, atomic layer deposition (ALD), etc. The gate dielectric layer and gate electrode may be formed from a layer stack of their constituent materials by patterning using photolithography and etching processes. The source and drain may comprise semiconductor material of the semiconductor layer that is heavily doped by masked ion implantation with either a p-type dopant or an n-type dopant depending upon the device type. A channel is defined between each source-drain pair.

An interconnect structure of the chip may be configured to communicate signals among the silicon-controlled rectifier14, input/output pin22, and inverters42,44and to provide the power and ground connections with the VDDrail16and the VSSrail18. The interconnect structure, which may be fabricated during middle-of-line (MOL) and back-end-of-line (BEOL) processing by, for example, damascene processes, includes wiring layers comprised of metal wiring embedded in dielectric layers. In particular, the output40of the control circuit12, which includes inverter42in this embodiment, is coupled by metal wiring37with the n-well contact33to the n-well36, the anode30of the silicon-controlled rectifier14is coupled by metal wiring39with the input/output pin22, the cathode32of the silicon-controlled rectifier14is coupled by metal wiring41with the VSSrail18, and the p-well contact34to the p-well38is coupled by metal wiring43with the VSSrail18.

With reference toFIG. 3in which like reference numerals refer to like features inFIG. 2and in accordance with an embodiment of the invention, the control circuit12may have a single-stage inverter design that only includes the inverter42. The gates of the PFET46and NFET48of the inverter42may be coupled with (e.g., hardwired with) the VSSrail18(i.e., ground). The hard wiring, which provides continuous grounding of the field-effect transistor gates, may be provided in the interconnect structure of the chip that is formed by middle-of-line and/or back-end-of-line processing.

With reference toFIG. 4in which like reference numerals refer to like features inFIG. 2and in accordance with an embodiment of the invention, the control circuit12may include the PFET46and a junction field effect transistor (JFET)50coupled in series between the VDDrail16and the VSSrail18. The output40at a node between the PFET46and the JFET50is coupled with the n-well36. In one embodiment, the PFET46is an enhancement-mode p-channel field effect transistor and the JFET50is a p-channel junction field effect transistor. The JFET50functions as the pulldown part of the circuit and, when the circuit is powered off, will set the output40to a voltage level equal to logic 0 (low or VSS) so that the n-well36is grounded to VSS.

The JFET50includes a region of semiconductor material (e.g., silicon) of a given conductivity type defining a channel for carrier flow between a source and a drain located at opposite ends of the channel and each having heavier doping than the channel to produce a comparatively higher conductivity. A voltage applied to a gate, which is doped to have an opposite conductivity type from the channel, is used to control the flow of current from the source to the drain by varying the depth of the depletion region within the channel to provide a low impedance condition. The gate and channel define a diode structure that can be reverse biased. As the depletion region increases in volume with increasing reverse bias voltage during operation of the JFET50, the current flowing in the channel drops and is eventually pinched-off to provide a high impedance condition. The source, drain, channel, and gate of the JFET50may be comprised of abutting regions or layers of n-type and p-type semiconductor materials that are formed in a semiconductor layer by ion implantation or another technique.

In one embodiment, the JFET50may be a p-channel junction field effect transistor and the PFET46may be an enhancement mode p-channel field effect transistor. A source of the JFET50is coupled with the VSSrail18and a drain of the JFET50is coupled with the n-well36. The source of the PFET46is coupled with the VDDrail16, the drain of the PFET46is coupled with the n-well36, and the gate of the PFET46is coupled with the VSSrail18.

The various embodiments of the invention may be implemented in bulk technologies (e.g., 200 mm and 300 mm technologies) in which the operating voltage is greater than or equal to 1.5 volts. However, implementation is also contemplated in other bulk technologies. The ability to provide an initially-on device may widen the safe ESD design window in which ESD protection can be provided as device dimensions shrink and the available range of trigger voltages likewise shrinks. The low turn-on voltage of less than 0.6 volts may be applicable to technologies with tight ESD design windows.

It will be understood that when an element is described as being “connected” or “coupled” to or with another element, it can be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. In contrast, when an element is described as being “directly connected” or “directly coupled” to or with another element, there are no intervening elements present. When an element is described as being “indirectly connected” or “indirectly coupled” to or with another element, there is at least one intervening element present.