Technology mapping for programmable logic devices using replicating logic and parallel computations

The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel computation is performed on the replicated nodes followed by selection of the output. The delay reduction approach in the present invention gives a highly efficient logic implementation when delay is the prime concern and area can be afforded to be expanded. The technique relies on replicating logic and performing parallel computation on delay critical LUT's.

TECHNICAL FIELD

Embodiments of the present invention relate to delays incurred during technology mapping in FPGAs. In particular embodiments of the invention relate to reducing the delay incurred during technology mapping in FPGAs.

BACKGROUND

A FPGA is a programmable logic device with uncommitted logic and routing elements. The implementation of logic consists of mapping the logic into Look Up Tables (LUT's) and LUT's into Programmable Logic Blocks (PLB's). The circuit netlist at the gate level is first packed into k input LUT's as available in the PLB architecture. The circuit behavior is also important to be analyzed in terms of the delay that under the unit delay model is the maximum sum of the delays of LUT's in series, by assigning a delay of unity to each of them. The job of the mapper is to map the given logic into as few LUT's as possible.

Various techniques exist for mapping a given logic into FPGA. The focus in all such mapping techniques is to optimize the delay or area as the user may require. Various delay optimization algorithms exist which try to reduce the critical path length under the unit delay model trading off the area to some extent. As delay is an important consideration on only the critical path, algorithms like Flowmap-r have been developed which focus on the delay reduction only on the critical path, focusing on area optimization on the rest.

The objective of the mapping process is to consume as few LUT's as possible, but that is achievable to some extent.

FIG. 1illustrates the flow diagram of the FPGA development process and role of the technology mapping in it.1.1in the figure indicates the Design Entry as entering the design into the system for hardware realization of the design. Logic Synthesis1.2performs the hardware realization of the design entered depending on the target device. The optimized netlist is then mapped into LUT as shown in the1.3that is followed by Placement and Route function as in block1.4. This block implements the positioning and configuration of the interconnects of the logic blocks. The bit stream is generated as in the Device programming unit block1.5for configuring the target device. 1.6 illustrates the configured target device after the completion of the design cycle.

FIG. 2illustrates the diagram of a prior art method for mapping logic/technology in an FPGA. The circular nodes (a-m) represent a logic for two input LUT's. It is evident from the figure that the path from nodes a and b to k is quite long as compared to the path through c, d and e. As a result the signal generation at k has to wait for the signal from a through i. This makes the path a, n, f, i, j as a critical path leading to a critical fan-in node k. A critical path in a circuit is a chain of circuit elements or the longest path such that the signal takes the maximum time to reach the final output through that given path. In most of the cases, nodes (LUTs) falling in the critical path have one or more fan-ins which are critical (have the maximum delay) while the rest of the input take lesser time so are not that critical. This essentially means that a signal at the output of node cannot be generated till all the input signals arrive, in other words non-critical signals have to wait for signals on the critical path. This is what essentially gives rise to a critical path for the whole circuit.

Therefore, it is realized to be essential to provide a scheme to reduce the delay incurred during the technology mapping in an FPGA. Embodiments of the present invention provide such a scheme.

SUMMARY

Embodiments of the present invention obviate the shortcomings of the prior art and provide a method for delay reduction during technology mapping in an FPGA.

Embodiments of the invention identify the critical path for LUT mapping.

Other embodiments of the invention replicate the logic of the critical fan-in nodes falling in the critical path.

Yet other embodiments of the invention perform parallel computation on the replicated logic nodes so as to reduce the mapping delay.

According to one embodiment of the present invention, an improved system for delay reduction during technology mapping in FPGA includes:Critical Path Identifier (CPI) for locating critical fan-in nodes in the mapping logic, wherein,Logic Replicator (LR) for replicating logic for the critical fan-in nodes,Parallel Computer (PC) for performing parallel computation on the critical fan-in nodes and non critical signals,Output Selector (OS) for selecting the output at the last critical fan-in node after performing parallel computation.

According to embodiment of the present invention, an improved method for delay reduction during technology mapping in FPGA includes:locating critical fan-in nodes in the mapping logic using Critical Path Identifier (CPI), wherein,replicating logic for the critical fan-in nodes using Logic Replicator (LR),performing parallel computation on the critical fan-in nodes and non critical signals using Parallel Computer (PC),selecting the output at the last critical fan-in node after performing parallel computation using Output Selector (OS),

thereby reducing delay in the technology mapping in an FPGA.

According to another embodiment of the present invention, the CPI determines the fan-in nodes that constitute the greatest delay/critical path.

According to another embodiment of the present invention, the LR duplicates the critical fan-in nodes.

According to another embodiment of the present invention, the PC performs look ahead logic computation.

According to another embodiment of the present invention, the output selector is a multiplexer.

The greatest delay path may be a chain of logic elements that require the maximum time for logic execution in the FPGA.

The LR may assign complimentary values to each pair of duplicated nodes.

The PC may locate the input of a critical node and perform parallel computation to reduce the delay of the node.

The critical fan-in nodes may be subjected to parallel computation for logic mapping into Look Up Table's (LUT's).

According to another embodiment of the present invention, a computer program product comprising computer readable program code stored on computer readable storage medium embodied therein for providing a system for delay reduction during technology mapping in FPGA includes:a. Critical Path Identifier (CPI) for locating critical fan-in nodes in the mapping logic, wherein,b. Logic Replicator (LR) for creating replicating logic for the critical fan-in nodes,c. Parallel Computer (PC) for performing parallel computation on the critical fan-in nodes and non critical signals,d. Output Selector (OS) for selecting the output at the last critical fan-in node after performing parallel computation.

DETAILED DESCRIPTION

FIG. 1is a flow diagram of the FPGA development process andFIG. 2illustrates a prior art method for technology mapping as described under the heading ‘Background of the Invention’.

FIG. 3is a flow diagram according to one embodiment of the present invention with reference to the prior art inFIG. 1. Here the node k is the first critical fan-in node, followed by the nodes1& m. Here the nodes k, l & m are replicated for parallel computation to obviate the critical path for minimizing the delay. The critical path in this case is defined with reference toFIG. 2and is constituted by the nodes a, f, h, j, k, l & m.

The nodes k0and k1assume the critical input j as 0 or 1, so that there occurs a reduction in their overall criticality.

Look Ahead Computation is performed parallel to the computation of the path constituted by the nodes a, n, f, i, j, in which the replicated nodes are formed as the images of the critical nodes, thus making them independent of the critical input j, which is being simultaneously computed. The term Look ahead computation is used since we are assuming critical inputs for the nodes that are subjected to computation after the computation on the non-critical nodes.

The Look ahead parallel computation for the critical fan-in nodes and the non-critical signals is depicted by Levels1-5.5in the diagram. The replicating logic for parallel computation is depicted in the Levels3to5followed by the using a multiplexer (Level5.5) to select the final output obtained after the replicated logic. It can be observed from the Figure that there is a significant reduction in the number of Levels of the mapping as compared to the prior art inFIG. 2.

It is observed inFIG. 3of the present invention, that the area increment can be observed to be of the order of 13% and the delay decrement is of the order of 31%. It should be noted that as the logic becomes big, this trade-off between area and delay increases substantially. It is also observed that an increment of 4-8 LUTs if brings a delay decrement of 10-20%, which is substantial.

Increasing the number of LUTs in a design to be mapped, delay in mapping could be reduced substantially so as to overcome the drawback of LUT consumption in speed critical circuits.

The difference in the delay values between critical and non-critical nodes depends on the amount of logic we can replicate. Thus, we can significantly reduce the bottleneck of the critical path, by performing replication followed by parallel computation logic.

An FPGA including a system for reducing delay as described above may be utilized in a variety of different types of electronic systems. For example, multiple FPGAs may be contained in development modules utilized during the design of many types of electronic systems.FIG.4illustrates an example computer system400according to one or more embodiments. The computer system400can include various components to implement technology mapping include for example a critical path identifier component402, a logic replicator component404, a parallel computation component406, and an output selector component408as described herein. In at least some embodiments, the computing system can include or make use of a computer program product410to implement aspect of technology mapping. The computer program product410can include computer readable program code stored in computer readable storage that is readable by the computer system400to implement the various components including the critical path identifier component402, logic replicator component404, parallel computation component406, and output selector component408described herein.