The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

BACKGROUND

Technical Field

The present disclosure is directed to a master-slave flip-flop memory circuit, and in particular, to an arrangement of transistors to improve low voltage nominal hold and variability characteristics.

Description of the Related Art

Memory devices are common components in digital circuits. One type of memory is static random access memory (SRAM). SRAM cells use a latching circuit for each memory cell to preserve the data value over time without the use of a refreshing circuit. An output of a single D type latching circuit can be erratic during switching from the various inputs undergoing transitions. Thus one solution is to cascade two D type latches together. In this configuration, the first D type latch latches the desired value at a first time while the second D type latch continues to output a previously stored value. At a second time, the first D type latch outputs the previously received value to the second D type latch. This allows the inputs to stabilize, possibly resulting in less overall output variability of the memory circuit.

Power consumption of a circuit, including memory circuits, is a function of switching speed. Power equals current multiplied by voltage. As switching speed increases, more current flows through the circuit and power consumption increases. As power consumption increases, the circuit becomes more susceptible to thermal failure from the heat generated as power is dissipated by the circuit. Thermal failure can result in erratic electrical signal behavior, spurious signals appearing in the circuit, or from component failure. To try to prevent thermal failure during operation, circuit designs may decrease the source voltage. An unintended consequence of reduced source voltage is that transistor behavior can become more erratic as the threshold voltage of a transistor approaches the overall source voltage of the circuit.

BRIEF SUMMARY

The present disclosure is directed to a transistor layout that improves low voltage nominal hold and variability in a master-slave flip-flop memory circuit without increasing circuit area or dynamic power consumption.

The present disclosure is directed to a master-slave flip-flop memory circuit with a re-architectured transistor layout that improves low voltage nominal hold and variability characteristics without increasing circuit area or dynamic power requirements. The circuit reduces the number of transistors in the nominal hold critical path by coupling an input of the master latch to a low output of the test switch around a partial pass gate. In addition, a first inverter is coupled to the input of the master latch with second and third inverters being coupled to an output of the first inverter. The second inverter has an output coupled to the input of the first inverter and the third inverter has an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled, such that clock and reset signals are not inverted within the master latch.

DETAILED DESCRIPTION

As used in the specification and appended claims, the use of “correspond,” “corresponds,” and “corresponding” is intended to describe a ratio of or a similarity between referenced objects. The use of “correspond” or one of its forms should not be construed to mean the exact shape or size.

Specific embodiments of transistor layouts are described herein; however, the present disclosure and the reference to certain arrangements, dimensions, and details and ordering of processing steps are exemplary, and should not be limited to those shown. Reference to coupling of components refers to embodiments in which the components are directly coupled together with a connector and to embodiments in which the components are coupled together through another component.

FIG. 1is a high-level block diagram of a master-slave flip-flop100memory circuit, according to one embodiment. The master-slave flip-flop100has five inputs and one output. The inputs include a data signal D0, a test input signal TI, a test enable signal TE, a clock signal C, and a reset signal R. The output is a data output Q0. Each of the inputs and output are binary digital signals, with either a high value or a low value corresponding to a high power signal and a lower power signal provided to the master-slave flip-flop100. The high value can be represented with a “1” and the low value can be represented with a “0”, without those values corresponding to any specific power values. The master-slave flip-flop100receives and stores the data signal D0and outputs the data output Q0. The storage and output of signals is controlled by the clock signal C. Separately, the master-slave flip-flop100can output the test input signal TI over the data output Q0when the test enable signal TE enables the test circuit.

To implement the above functionality, the master-slave flip-flop100implements a type of SRAM in which a test switch102selects an input into the master-slave flip-flop100and a master latch104is cascaded with a slave latch106, the slave latch106receiving an inverted clock signal from an inverter108. The test switch102includes a multiplexor that selects between the data signal D0at a first input A and the test input signal TI and a second input B. The multiplexor is controlled by the test enable signal TE to control which of the two inputs A, B is passed to an output Q of the test switch102. In other embodiments, other types of switches may be used for the test switch102.

The output Q of the test switch102is provided to a data input D1of the master latch104. The master latch104also receives the reset signal R and the clock signal C. The master latch104outputs a data output Q1. In some embodiments, the master latch104is a D type latch that has a truth table as depicted in Table 1 below. As depicted in the truth table, a data output Qnof the D type latch is affected by four parameters, the value at a data input D, the value at the clock signal C, the value at the reset signal R, and the previous data output Qn-1. If the reset signal R is 0, then the data output Qnis 1, regardless of the values on the other inputs. This set of conditions can be referred to as the reset or clearing phase. If the reset signal R is 1 and the clock is 0, then the data output Qnis equal to the value at the data input D, regardless of the previous data output Qn-1. This set of conditions can be referred to as the set or setup phase. If the reset signal R is 1 and the clock signal C is 1, then the data output Qnis equal to the value of the previous data output Qn-1, regardless of the value at the data input D. This set of conditions can be referred to as the hold or store phase. Thus a value at the data input D can be received during the setup phase, stored and output during the hold phase, and reset during reset phase.

The data output Q1is provided to a data input D2of the slave latch106. The slave latch106also receives the reset signal R and an inverted clock signalC. The slave latch106outputs a data output Q2as data output Q0of the memory circuit100. In some embodiments, the slave latch106is a D type latch that has a truth table as depicted in Table 1 above. The master-slave flip-flop100configuration has opposite clock level-triggered latches, which can aid in stabilization of the data output Q. In some embodiments, such as the embodiment shown inFIG. 4B, the slave latch106is opposite clock triggered by an output of the inverter108. In other embodiments, such as the embodiment inFIG. 5, the slave flip-flop106is opposite clock level-triggered without the need of inverter108.

Table 1 is an approximation or idealization of the performance of the D type latch. In real world implementations, there can be variability in the signal over time for any number of reasons. One reason for possible variations in the output of latches generally is that the timing of signals propagating through the circuit of the latch can cause unwanted behaviors. For example, a data input may arrive after a clock signal that was supposed to latch and hold the data value. Other issues may be that devices are running at clock speeds or power levels that introduce non-ideal behaviors from operating devices near their operational limits. As discussed above, design preferences are pushing devices to operate faster and at lower power levels.

A specific issue arises in flip-flops, in that high variations in hold time requirements occur under these conditions. In some previous designs, hold time performance may degrade such that rise or fall hold times become undesirable across a range of operating voltages. With severely degraded hold times, it may become impossible to write a 1 or 0 to the master-slave flip-flop100. In some embodiments, negative hold times are desired.

One way to improve hold time is to remove nMOS devices from a critical hold path, the path the signal travels through the master-slave flip-flop100in holding a value. Compared to traditional designs, some of the disclosed embodiments do not include a second inverter in the clock signal to condition the clock signal for the master latch104and remove the nMOS transistor clock enabled pass-through gate at the input of the master latch104. These embodiments will be discussed in further detail below. These embodiments may improve low voltage variability without increasing the circuit area or dynamic power.

FIG. 2is an intermediate-level block diagram of a master-slave flip-flop200memory circuit. The master-slave flip-flop200includes a test switch201, which selects an input into the master-slave flip-flop200, and a master latch205cascaded with a slave latch215.FIG. 2depicts the various functional components of the master-slave flip-flop200with a level of detail between the block diagrams ofFIG. 1and the transistor diagrams ofFIGS. 4-5.

The test switch201is shown having a multiplexer202that receives the data input D at a first input A and the test input TI at a second input B. The multiplexer202is controlled by the test enable signal TE. In one embodiment, when the test enable signal TE is 0, the multiplexer202couples the data input D to an output of the multiplexer202, and when the test enable signal is 1, the multiplexer202couples the test input TI to an output of the multiplexer202. In another embodiment, the values are reversed. The output of the multiplexer202is input into a first inverter204. The inverted output of the first inverter204is an output Q of the test switch201, which is also an input D1to the master latch205. The first inverter204can represent a distinct physical component from the multiplexer202, or can simply represent different functionality contained within a single physical component. In some embodiments, the order of the components of the test switch201are different than depicted, which may or may not impact the output of the test switch201.

The master latch205receives the output Q from the test switch201at an inverter206. The inverter206inverts the signal and supplies the inverted signal to a switch208. The switch208can be any switch, and, in one embodiment, is an on/off switch that couples and uncouples the inverted output from the inverter206from the remaining components of the master latch205. The switch208is shown in an open circuit state. The open/closed state of switch208is controlled by the clock signal C. In one embodiment, when the clock signal C is 1, the switch208is in an open state, and when the clock signal C is a 0, the switch208is in a closed state. Thus, in this embodiment, the test switch201is coupled to the master latch205when the clock signal C is 0 and uncoupled when the clock signal C is 1. In other embodiments, the values for controlling the switch208can be flipped.

An output of the switch208is coupled to a first input A of a NAND gate210. The truth table for NAND gate210is provided in table 2, below. The NAND gate210has a second input B coupled to the reset signal R. Thus, in one embodiment, when the output of the switch208and the reset signal R are 1, an output Q of the NAND gate210is 0. Any other combination of inputs A, B to the NAND gate210in this embodiment results in an output Q of 1.

The output Q of NAND gate210is also an output Q1of the master latch205, which is input into a feedback loop that includes an inverter214and a switch212. The inverter214receives the output Q of the NAND gate210and outputs an inverted signal to the switch212. The switch212can be any switch, and, in one embodiment, is an on/off switch that couples and uncouples the inverted output from the inverter214from the first input A of the NAND gate210. The switch212is shown in a closed circuit state. The open/closed state of switch212is controlled by the clock signal C. In one embodiment, when the clock signal C is a 1, the switch212is in a closed state, and when the clock signal C is a 0, the switch212is in an open state. Thus, in this embodiment, the feedback loop of the master latch205is a closed loop circuit when the clock signal C is 1 and is an open circuit when the clock signal C is 0. In other embodiments, the values for controlling the switch212can be flipped. In some embodiments, the switch208and the switch212respond to inverted inputs such that the clock signal C either causes the master latch205to be coupled to the test switch201or causes the master latch205to have a closed feedback loop.

The various components of the master latch205can represent distinct physical components from each other, or can simply represent different functionality contained within a single or combinations of multiple physical components. In some embodiments, the order of the components of the master latch205is different than depicted, which may or may not impact the output of the master latch205.

The slave latch215receives the output signal Q from the master latch205at a switch216, which is also an input D2of the master latch205. The switch216can be any switch, and, in one embodiment, is an on/off switch that couples and uncouples the input of the slave latch215from a feedback loop of the slave latch215. The switch216is shown in a closed circuit state. The open/closed state of switch216is controlled by the clock signal C. In one embodiment, when the clock signal C is a 1, the switch216is in a closed state, and when the clock signal C is a 0, the switch216is in an open state. Thus, in this embodiment, the slave latch215is coupled to the master latch205when the clock signal C is 1 and uncoupled when the clock signal C is 0. In other embodiments, the values for controlling the switch216can be flipped. In some embodiments, the switch208and the switch216respond to inverted inputs such that the clock signal C causes the slave latch215to be coupled to the master latch205only when the master latch205is decoupled from the test switch201.

An output of the switch216is coupled to an input of an inverter218. The inverter inverts the signal and provides an output to a first input A of a NAND gate220. The NAND gate220can have a similar truth table as the NAND gate210depicted in Table 2. The NAND gate220has a second input B coupled to the reset signal R. Thus, in one embodiment, when the output of the inverter218and the reset signal R are 1, the output Q of the NAND gate220is 0. Any other combination of inputs A, B to the NAND gate220in this embodiment results in an output Q of 1.

The output Q of NAND gate220is coupled to a switch222. The switch222can be any switch, and, in one embodiment, is an on/off switch that couples and uncouples the output Q of the NAND gate210from the input of the inverter218to form a feedback loop. The open/closed state of switch222is controlled by the clock signal C. In this embodiment, the feedback loop of the slave latch215is a closed loop circuit when the clock signal C is a 0, and is an open circuit when the clock signal C is a 1. In other embodiments, the values for controlling the switch222can be flipped. In some embodiments, the switch216and the switch222respond to inverted inputs such that the clock signal C either causes the slave latch215to be coupled to the master latch205or causes the slave latch215to have a closed feedback loop. Also, in some embodiments, the switch212and the switch222respond to inverted inputs such that the clock signal C causes the slave latch215to have a closed feedback loop when the master latch205has an open feedback loop, or the clock signal C causes the slave latch215to have an open feedback loop when the master latch205has a closed feedback loop.

The output of the switch216is also coupled to an inverter224. The inverted signal output from the inverter224is an output Q2of the slave latch215, which is also an output Q0 of the master-slave flip-flop200. The various components of the slave latch215can represent distinct physical components from each other, or can simply represent different functionality contained within a single physical component or combinations of multiple physical components. In some embodiments, the order of the components of the slave latch215is different than depicted, which may or may not impact the output of the slave latch215.

In some embodiments, the master-slave flip-flop200stores a value in master latch205from the test switch201on a first clock transition and stores a value in the slave latch215from the master latch205on a second clock transition. In some embodiments, the value to store is preserved at the output of each section, and, in other embodiments, the value to store is inverted at the output of some sections, but is preserved at the output of the master-slave flip-flop200. And in yet other embodiments, the value to store is inverted at the output of some sections, including the output of the master-slave flip-flop200.

FIG. 3is a timing diagram for a master-slave flip-flop memory circuit, according to one embodiment. The timing diagram is associated with a D flip-flop type of flip-flop. Some of the disclosed embodiments of transistor layouts improve upon the timing performance of master-slave flip-flops. For example, there can be a reduction in the window of time required to have a steady input to the master-slave flip-flop input to reliably capture the value. Alternatively, the relative start/stop times of the read window can be improved upon.

The timing diagram ofFIG. 3includes a timing plot300that has an x-axis value measured in time. Three distinct values are depicted on the timing plot300, each having its own y-axis. The top subplot represents a value of a data input D to the D flip-flop. The middle subplot represents a value of a clock signal C to the D flip-flop. The bottom subplot represents a value of a data output Q to the D flip-flop. The value of each of these three signals can be 0, 1, or a transitional state between one of those values. Possible transitional states are depicted as the slanted lines.

The timing plot300is divided into five time periods. A first time period302occurs before t−1. Time t−1is measured relative to the transition of the clock signal C. At this point the D flip-flop is not reading the data input D, and the data input D has time to change and propagate to the needed components of the D flip-flop. In other words, the D flip-flop has not latched the data input D yet, and a change in the data input D at the input of the D flip-flop during time period302will not affect the performance of the D flip-flop. Thus, various values for data input D are depicted in the timing plot300at time period302, with each X representing possible transitions in the data input D value, from high to low or low to high, that do not otherwise affect the data output Q of the D flip-flop. Since the time period302is defined as an amount of time before the clock signal C, the clock signal is depicted as a single value of 0. In other embodiments, the clock signal C may be a constant 1, or include at least one transition. Data output Q is shown as a constant value of either 1 or 0, as in the period302the D flip-flop has latched the previous data input D and is outputting that value.

A second time period304of the timing plot300occurs after t−1and before t0. Time t0is measured at the point in which clock signal C rises through the halfway point between 1 and 0. At t0the D flip-flop has been triggered to latch the value at the input of the D flip-flop. If the input data D is not stable during reading, the reliability of the D flip-flop can be sacrificed. Thus, a D flip-flop has a point in time relative to the rising edge of the clock signal C in which the data input D must be held constant to allow for accurate readings. The D flip-flop is latching a reliable steady-state signal of the data input D after t−1. The time period304is defined as an amount of time before the clock signal C transitions to a 1 but after the data input D has to stabilize for a reliable reading. During the time period304, the clock signal C is depicted as a single value of 0 until the end of the time period304when the clock signal C makes the first half of the transition to 1. In other embodiments, the clock signal may be a constant 1, or include at least one transition. Data output Q is shown as a constant value of either 1 or 0, as in the time period304the D flip-flop has latched the previous data input D and is outputting that value. Time t−1is also called setup time tsu, reflecting how this is the time relative to the rising edge of the clock signal C in which the D flip-flop input has to be set up and stable for a reliable reading. In some embodiments setup time tsuis negative, reflecting that the setup time tsuoccurs earlier in time than the rising edge of the clock signal C.

A third time period306of the timing plot300occurs after t0and before t1. Time t1is measured relative to the transition of the clock signal C. Because the input data D must be stable during reading, the data input D must be held constant through a specific point in time relative to the rising edge of the clock signal C to allow for accurate readings. The D flip-flop is latching a reliable steady-state signal of the data input D until t1. The time period306is defined as an amount of time after the clock signal C transitions to a 1 but before the data input D can transition without degrading performance. During the time period306the clock signal C is depicted as a single value of 1 except at the beginning of the time period306when the clock signal C makes the second half of the transition to 1. In other embodiments, the clock signal may be a constant 0, or include at least one transition. Data output Q is shown as a constant value of either 1 or 0, as in the time period306the D flip-flop has latched the previous data input D and is still outputting that value. Time t1is also called hold time th, reflecting how this is the time relative to the rising edge of the clock signal C in which the D flip-flop input has to be held constant and stable for a reliable reading. In some embodiments hold time this positive, reflecting that the hold time thoccurs later in time than the rising edge of the clock signal C. In other embodiments, the hold time thcan be any value, including a negative value, reflecting that the hold time thoccurs earlier in time than the rising edge of the clock signal C.

A fourth time period308of the timing plot300occurs after t1but before t2. Time t2is measured relative to the transition of the clock signal C. At t2, the D flip-flop transitions to the data input D value present during the reading window between t−1and t1. In other words, the D flip-flop has latched the new data input D. In other words, the D flip-flop has latched the data input D, and a change in the data input D at the input of the D flip-flop during time period302will not affect the performance of the D flip-flop. Thus, various values for data input D are depicted in the timing plot300at time period308, with each X representing possible transitions in the data input D value that do not otherwise affect the data output Q of the D flip-flop. Since the time period308is defined as an amount of time after the clock signal C, the clock signal is depicted as a single value of 1 during the time period308. In other embodiments, the clock signal may be a constant 0, or include at least one transition. Data output Q is shown as a constant value of either 1 or 0 until the end of the time period308, when the data output Q makes the first half of a transition to reflect the data input D. Time t2is also called propagation delay tpd, reflecting how this is the time relative to the rising edge of the clock signal C that it takes the D flip-flop to latch and output the data input D, or to propagate the signal through the circuit. The propagation delay tpdcan be any positive value.

A fifth time period310of the timing plot300occurs after t2. After t2the D flip-flop has reached a new steady state condition. At any point after t1the D flip-flop is not reading the data input D, thus various values for data input D are depicted in the timing plot300at time period310as well, with each X representing possible transitions in the data input D value that do not otherwise affect the data output Q of the D flip-flop, and the data input D has time to change and propagate to the needed components of the D flip-flop for the next reading window. In other words, the D flip-flop has finished latching the data input D, and a change in the data input D at the input of the D flip-flop during the time period310will not affect the performance of the D flip-flop. Additionally, after t2the data output Q has also stabilized, except at the beginning of the time period310when the data output Q makes the second half of the transition.

FIG. 4Ais a schematic of a first half of a master-slave flip-flop400, according to one embodiment.FIGS. 4-5include circuit diagrams at the transistor level of detail. The transistors are depicted as generic metal-oxide-semiconductor field-effect-transistors (MOSFETs); however, any specific type of transistor may be used. Additionally, the figures and description differentiate between p type MOSFETs (pMOS) and n type MOSFETs (nMOS); however, in other embodiments, any one of the pMOS transistors may be an nMOS transistor and any one of the nMOS transistors may be a pMOS transistor. The various transistors are enabled by the signals on the respective gates of those transistors, in one embodiment. In other embodiments, a transistor may be enabled by a signal on one or more terminals of the transistor.

The master-slave flip-flop400includes a test switch401. The test switch401has a data input402(D0) coupled to a gate of a pMOS transistor404aand a gate of an nMOS transistor404b. The pMOS transistor404ahas a terminal coupled to a terminal of a pMOS transistor406a, and the nMOS transistor404bhas a terminal coupled to a terminal of an nMOS transistor406b. The other terminals of the transistors404a,404bare coupled to outputs of the test switch401, which are also inputs D1to a master latch413. The other terminals of the transistors406a,406bare coupled to a high voltage line VDD and a low voltage line GND, respectively. The voltage line VDD can be a high signal, or a 1, in some embodiments, and the voltage line GND can be a low signal, or a 0, in some embodiments. The gate of the pMOS transistor406ais coupled to a test enable signal TE, and the gate of the nMOS transistor406bis coupled to an inverted test enable signalTE. Thus, when the data input402is 0 and the test enable signal TE is 0, pMOS transistors406a,404aare conducting, and an output of the test switch401is equal to the voltage on the voltage line VDD. Conversely, when the data input402is 1 and the inverted test enable signalTEis 1, nMOS transistors406b,404bare conducting, and an output of the test switch401is equal to the voltage on the voltage line GND. In other combinations of inputs, the voltage lines are not coupled to the output of the test switch401through transistors404a,404b,406a,406b, isolating the data input402from the output of the test switch401.

The test switch401has a test input TI coupled to a gate of a pMOS transistor410aand a gate of an nMOS transistor410b. The pMOS transistor410ahas a terminal coupled to a terminal of a pMOS transistor408aand the nMOS transistor410bhas a terminal coupled to a terminal of an nMOS transistor408b. The other terminals of the transistors410a,410bare coupled to voltage lines VDD, GND, respectively. The other terminals of the transistors408a,408bare coupled to an output of the test switch401. The gate of the pMOS transistor408ais coupled to the inverted test enable signalTE, and the gate of the nMOS transistor408bis coupled to the test enable signal TE. Thus, when the test input TI is 0 and the inverted test enable signalTEis 0, pMOS transistors410a,408aare conducting, and an output of the test switch401is equal to the voltage on the voltage line VDD. Conversely, when the test input TI is 1 and the test enable signal TE is 1, nMOS transistors410band408bare conducting, and an output of the test switch401is equal to the voltage on the voltage line GND. In other combinations of inputs, the voltage lines are not coupled to the output of the test switch401through transistors408a,408b,410a,410b, isolating the test input TI from the output of the test switch401.

The inverted test enable signalTEis generated by an inverter412. The inverter412receives the test enable signal TE at gates of a pMOS transistor412aand an nMOS transistor412b. A first terminal of the pMOS transistor412ais coupled to the voltage line VDD, and a first terminal of the nMOS transistor412bis coupled to the voltage line GND. A second terminal of the transistors412a,412bare common, and are the output of the inverter412generating the inverted test enable signalTE. When the test enable signal TE is 0, pMOS transistor412acouples the inverter412output to the voltage line VDD, and when the test enable signal TE is 1, nMOS transistor430bcouples the inverter412output to the voltage line GND.

In some embodiments, the test switch401operates such that only one of the data input402and the test input TI control an output of the test switch401. In both cases, the output signal is inverted from the received signal. The outputs of the test switch401are coupled to the inputs D1of the master latch413. The outputs of the test switch401is shown as two separate nodes. In other embodiments, it may be any number of nodes greater than zero.

The master latch413includes a pass gate having a pMOS transistor414aand an nMOS transistor414b. The gates of the transistors414a,414bare coupled to a clock signal C. The pMOS transistor414ahas a terminal coupled to a first node of the input to the master latch413, and has a terminal coupled to a second node of the input to the master latch413. The nMOS transistor414bhas a terminal coupled to the second node of the input to the master latch413. The other terminal of the nMOS transistor414bis coupled to an nMOS transistor416. In some embodiments, a clock signal C of 0 allows the test switch output to be received, and a clock signal C of 1 blocks the output of the test switch at the pass gate of transistors414a,414b.

The common node between transistors414a,414bis also coupled to the gates of an inverter that includes a pMOS transistor418aand an nMOS transistor418b. A first terminal of the pMOS transistor418ais coupled to the voltage line VDD, and a first terminal of the nMOS transistor418bis coupled to the voltage line GND. Second terminals of the transistors418a,418bare the output of the inverter.

The output of the inverter at the terminal of transistor418bis also coupled to a gate of the nMOS transistor416. The nMOS transistor416has a second terminal coupled to the voltage line GND. The nMOS transistor416works with the pass gate of transistors414a,414bto control the coupling of the test switch401to the master latch413.

A pass gate having a pMOS transistor420aand an nMOS transistor420bis coupled to the output of the inverter with transistors418a,418b. The gates of the transistors420a,420bare coupled to a clock signal C. The pMOS transistor420ahas a terminal coupled to a terminal of the pMOS transistor418a, and has a terminal coupled to a terminal of the nMOS transistor418b. The nMOS transistor420bhas a terminal coupled to node between the pMOS transistor420aand nMOS transistor418b. In some embodiments, a clock signal C of 0 allows the output of the inverter with transistors418a,418bto be transmitted, and a clock signal C of 1 to float the output. Thus the pass gate of transistors420a,420bserve as a clock enable of the inverter of transistors418a,418b.

The common node between transistors420a,418bis also coupled to the gates of an inverter that includes a pMOS transistor424aand an nMOS transistor424b. A first terminal of the pMOS transistor424ais coupled to the voltage line VDD. A common node of the transistors424a,424bis the output of the inverter. The node including the common node of the transistors424a,424bis also the output of the master latch413, output Q1(node A for page break).

A pass gate having a pMOS transistor426aand an nMOS transistor426bis coupled to the output of the inverter with transistors424a,424b. The gates of the transistors426a,426bare coupled to a reset signal R. The pMOS transistor426ahas a terminal coupled to the voltage line VDD and has a terminal coupled to a node between transistors424a,424b. The nMOS transistor426bhas a terminal coupled to a terminal of the nMOS transistor424band a terminal coupled to the voltage line GND. In some embodiments, a reset signal R of 1 allows the output of the inverter with transistors424a,424bto be transmitted, and a reset signal R of 0 sets the output to the voltage of the voltage line VDD. Thus the pass gate of transistors426a,426bserve as a reset enable of the inverter of transistors424a,424b.

The common node between transistors424a,424bis also coupled to the gates of an inverter that includes a pMOS transistor422aand an nMOS transistor422b. A first terminal of the pMOS transistor422ais coupled to a node between pMOS transistor418aand pMOS transistor420a. A second terminal of the pMOS transistor422ais coupled to the node between pMOS transistor420aand nMOS transistor418b. A first terminal of the nMOS transistor418bis coupled to the voltage line GND. A second terminal of the nMOS transistor418bis coupled to a terminal of the transistor420b. Thus the pass gate of transistors420a,420bserve as a clock enable of the inverter of transistors422a,422b. Additionally, as depicted, the inverter of transistors422a,422bprovide a feedback loop of the master latch413.

FIG. 4Bis a schematic of a second half of the master-slave flip-flop400, including a slave latch427. The slave latch427includes a pass gate having a pMOS transistor428aand an nMOS transistor428b. The gate of the transistor428bis coupled to the clock signal C, and the gate of the transistor428ais coupled to an inverted clock signalC. The transistors have a common node coupled to an input of the slave latch427, input D2(node A for page break), and have a common node as an output to the remainder of the slave latch427. In some embodiments, a clock signal C of 0 and an inverted clock signalCof 1 uncouples the input D2from the slave latch427, and a clock signal C of 1 and an inverted clock signalCof 0 couples the input D2to the slave latch427.

The inverted clock signalCis generated by an inverter429. The inverter429receives the clock signal C at gates of a pMOS transistor430aand an nMOS transistor430b. A first terminal of the pMOS transistor430ais coupled to the voltage line VDD, and a first terminal of the nMOS transistor430bis coupled to the voltage line GND. A second terminal of the transistors430a,430bare common and are the output of the inverter429generating the inverted clock signalC. When the clock signal C is 0, pMOS transistor430acouples the inverter429output to the voltage line VDD, and when the clock signal C is 1, nMOS transistor430bcouples the inverter429output to the voltage line GND.

The common node between transistors428a,428bis also coupled to the gates of an inverter that includes a pMOS transistor432aand an nMOS transistor432b. A first terminal of the pMOS transistor432ais coupled to the voltage line VDD and a first terminal of the nMOS transistor432bis coupled to the voltage line GND. Second terminals of the transistors432a,432bare the output of the inverter.

The common node between transistors432a,432bis also coupled to the gates of an inverter that includes a pMOS transistor434aand an nMOS transistor434b. As depicted, the inverter of transistors434a,434bprovide a feedback loop of the slave latch427.

A pass gate having a pMOS transistor436aand an nMOS transistor436bis coupled to the inverter with transistors434a,434b. The gates of the transistors436a,436bare coupled to a reset signal R. The pMOS transistor436ahas a terminal coupled to the voltage line VDD, and has a terminal coupled to a node between transistors434a,434b. The nMOS transistor436bhas a terminal coupled to a terminal of the nMOS transistor434b, and a terminal coupled to the voltage line GND. In some embodiments, a reset signal R of 1 allows the output of the inverter with transistors424a,424bto be transmitted, and a reset signal R of 0 sets the output to the voltage of the voltage line VDD. Thus the pass gate of transistors436a,436bserve as a reset enable of the inverter of transistors434a,434b.

A pass gate having a pMOS transistor438aand an nMOS transistor438bis coupled to the output of the inverter with transistors434a,434b. The gates of the transistors438a,438bare coupled to the clock signal C and to the inverted clock signalC, respectively. The pMOS transistor438ahas a terminal coupled to a terminal of the pMOS transistor434a, and the nMOS transistor438bhas a terminal coupled to a terminal of the nMOS transistor434b. The transistors438a,438bshare a common node which is an output of the pass gate. In some embodiments, a clock signal C of 0 and an inverted clock signal C of 1 allows the output of the inverter with transistors434a,434bto be transmitted, and a clock signal C of 1 and an inverted clock signalCof 0 floats the output. Thus the pass gate of transistors438a,438bserve as a clock enable of the inverter of transistors434a,434b.

The common node between transistors428a,428bis also coupled to the gates of an inverter that includes a pMOS transistor440aand an nMOS transistor440b. A first terminal of the pMOS transistor440ais coupled to the voltage line VDD. A first terminal of the nMOS transistor440bis coupled to the voltage line GND. A common node of the transistors440a,440bis the output of the inverter. The common node of the transistors440a,440bis also an output Q2of the slave latch427and the master-slave flip-flop400as data output442(Q0).

FIG. 5is a schematic of a second half of a master-slave flip-flop500, including a slave latch506, according to one embodiment. The slave latch506can replace the slave latch427in the master-slave flip-flop400to generate a new embodiment.

The slave latch506receives an input D2at the gates of an inverter that includes a pMOS transistor510aand an nMOS transistor510b. A first terminal of the pMOS transistor510ais coupled to the voltage line VDD. A second terminal of the transistors510a,510bis the output of the inverter.

The common node between transistors510a,510bis also coupled to the gates of an inverter that includes a pMOS transistor514aand an nMOS transistor514b. A first terminal of the pMOS transistor514ais coupled to the voltage line VDD. A second terminal of the transistors514a,514bis the output of the inverter.

Coupled to the inverter having transistors510a,510bis a pass gate having a pMOS transistor512aand an nMOS transistor512b. The gates of the transistors512a,512bare coupled to a clock signal C. The pMOS transistor512ahas a terminal coupled to the voltage line VDD. The nMOS transistor512bhas a terminal coupled to the voltage line GND and a terminal coupled to a terminal of the nMOS transistor510b. In some embodiments, a clock signal C of 1 allows the signal at node A to be received, and a clock signal C of 0 blocks the output of the inverter having transistors510a,510b. Thus the pass gate of transistors512a,512bserve as a clock enable of the inverter of transistors510a,510b.

The common node between transistors514a,514bis also coupled to the gates of an inverter that includes a pMOS transistor520aand an nMOS transistor520b. A first terminal of the pMOS transistor520ais coupled to a terminal of the pMOS transistor512a, and a second terminal is coupled to the common node between transistors510a,510b. A first terminal of the nMOS transistor520bis coupled to the voltage line GND, and a second terminal is coupled to a terminal of the nMOS transistor510b. The second terminals of the transistors520a,520bare the output of the inverter. Additionally, as depicted, the inverter of transistors520a,520bprovide a first feedback loop of the slave latch506.

Coupled to the inverter having transistors510a,510bis a pass gate having the pMOS transistor512aand an nMOS transistor516. The gate of the transistor516is coupled to a clock signal C. The nMOS transistor516has a terminal coupled to the voltage line GND and a terminal coupled to a terminal of the nMOS transistor514b. In some embodiments, a clock signal C of 1 allows the signal at the common node between transistors510a,510bto be received, and a clock signal C of 0 blocks the output of the inverter having transistors514a,514b. Thus the pass gate of transistors512a,516serve as a clock enable of the inverter of transistors514a,514b.

The common node between transistors514a,514bis also coupled to the gates of an inverter that includes a pMOS transistor522aand an nMOS transistor522b. A first terminal of the pMOS transistor522ais coupled to the voltage line VDD. A first terminal of the nMOS transistor522bis coupled to the voltage line GND. A second terminal of the transistors522a,522bis the output of the inverter.

The common node between transistors522a,522bis also coupled to the gates of an inverter that includes a pMOS transistor524aand an nMOS transistor524b. A first terminal of the pMOS transistor524ais coupled to a common node between the pMOS transistor512aand pMOS transistor520a. A second terminal of the pMOS transistor524ais coupled to the common node between transistors514a,514b. A first terminal of the nMOS transistor524bis coupled to a node between nMOS transistor516and nMOS transistor514b. A second terminal of the transistors524a,524bis the output of the inverter. Additionally, as depicted, the inverter of transistors524a,524bprovide a second feedback loop of the slave latch506.

Coupled to the inverter having transistors524a,524bis a pass gate having a pMOS transistor518aand an nMOS transistor518b. The gates of the transistors518a,518bare coupled to a reset signal R. The pMOS transistor518ahas a terminal coupled to the voltage line VDD and a terminal coupled to the common node between transistors514a,514b. The nMOS transistor518bhas a terminal coupled to the voltage line GND and a terminal coupled to a terminal of the nMOS transistor524b. In some embodiments, a reset signal R of 1 allows the second feedback loop to be a closed circuit, and a reset signal R of 0 blocks the output of the inverter having transistors514a,514band forces the output of the inverter to the voltage of the voltage line VDD. Thus the pass gate of transistors518a,518bserve as a reset enable of the inverter of transistors514a,514b.

The common node between transistors514a,514bis also coupled to the gates of an inverter that includes a pMOS transistor526aand an nMOS transistor526b. A first terminal of the pMOS transistor526ais coupled to the voltage line VDD and a first terminal of the nMOS transistor526bis coupled to the voltage line GND. A second terminal of the transistors526a,526bis the output of the inverter. The node including the common terminal of the transistors526a,526bis also an output Q2of the slave latch506, which is the data output Q0of the master-slave flip-flop500.

Some of the embodiments discussed throughout have been shown to improve nominal hold viability and robustness at low voltages without an increase in circuit area or dynamic power, as compared to previous designs. Specifically, previous designs 1, 2, 3 (leftmost column of Table 3) have been compared to a 4th design representative of an embodiment discussed above. The designs 1, 3, 4 each have an area of 5.67 um2. The design 2 has an area of 5.8968 um2which is 1.04 times the area of the designs 1, 3, 4. The Exemplary simulation data is discussed below.

Table 3 illustrates simulation data for the designs 1, 2, 3, 4. For the test simulation, the voltage differential between voltage lines VDD, GND is 0.81V, and the temperature of the circuit is 40 degrees C. The clock signal has a 250 ps slew and the input data has a 50 ps slew. Values in the table are picoseconds (ps). The table illustrates that design 4 has the best overall nominal hold performance, as hold rise and hold fall are both high negative values. Referring toFIG. 3, this means that the hold time ends well before the clock signal C transitions. Additionally, Table 3 illustrates the best overall hold margin with both hold margins being high values. The hold margins are the amount of time from t−1to t2minus the amount of time between t−1to t1. In more plain terms, for a given total time from holding the data input D to getting a data output Q, the largest portion of that time does not require a hold on the data input D. Lastly, the setup plus hold fall time is improved over previous designs by reducing the value, meaning the window required to hold the data input constant is reduced.

Table 4 illustrates simulation data for the designs 1, 2, 3, 4. For the test simulation, the voltage differential between voltage lines VDD, GND is 0.7V, and the temperature of the circuit is 40 degrees C. The clock signal has a 250 ps slew and the input data has a 50 ps slew. Values in the table are ps. The table illustrates that design 4 has the best overall nominal hold performance, as hold rise and hold fall are both high negative values. Additionally, Table 3 illustrates the best overall hold margin with both hold margins being high values. Lastly, the setup plus hold fall time is improved over previous designs by reducing the value.

Table 5 illustrates simulation data for the designs 1, 2, 3, 4. For the test simulation, the voltage differential between voltage lines VDD, GND is 1.2V, and the temperature of the circuit is 25 degrees C. The clock signal has a 250 ps slew and the input data has a 50 ps slew. Values in the table are ps. The table illustrates that design 4 has the best overall nominal hold performance, as hold rise and hold fall are both the most negative values. Additionally, Table 3 illustrates the best overall hold margin with both hold margins being high values. Lastly, the setup plus hold times are both improved over previous designs by reducing the value.

Table 6 illustrates simulation data for the designs 1, 2, 3, 4. For the test simulation, the voltage differential between voltage lines VDD, GND is varied, as expressed in the table. Values in the table are ps. The table illustrates that design 4 has the best overall nominal hold performance, as hold rise and hold fall are together the most negative values.

In addition to timing data, Applicant has generated power simulation data. Table 7 provides cap power, and Tables 8-10 provide dynamic power, which is cap power plus internal power. Tables 8-10 provide power values for transitioning a data signal, holding a high signal, or holding a low signal through a clock signal, respectively. For the test simulation, the voltage differential between voltage lines VDD, GND is 1.26V and the temperature of the circuit is 130 degrees C. The clock signal has a 250 ps slew and the input data has a 50 ps slew. Values in the table are watts unless otherwise indicated.

Tables 11 and 12 illustrate simulation data for the designs 1, 2, 3, 4 including 3 sigma data. Manufacturing variations in the circuit will cause timing to not be a precise value. The 3 sigma data represents the values to be accurate for 99.7% of timing values. For the test simulation in Table 11, the voltage differential between voltage lines VDD, GND is 0.81V and the temperature of the circuit is 40 degrees C. The simulation was run over 2000 iterations with expected circuit variations. The clock signal has a 1500 ps slew and the input data has a 50 ps slew. Values in the table are ps. The table illustrates that design 4 has the best overall 3 sigma nominal hold performance, as hold rise and hold fall are both high negative values. Additionally, Table 3 illustrates the best overall 3 sigma hold margins with both hold margins being high values.

For the test simulation in Table 12, the voltage differential between voltage lines VDD, GND is 0.70V and the temperature of the circuit is 40 degrees C. The simulation was run over 2000 iterations with expected circuit variations. The clock signal has a 1500 ps slew and the input data has a 50 ps slew. Values in the table are ps. The table illustrates that design 4 has the best overall 3 sigma nominal hold performance, as hold rise and hold fall are both high negative values. Additionally, Table 3 illustrates the best overall 3 sigma hold margins with both hold margins being high values.

The embodiment shown inFIG. 5has a 16% increase in area, but reduces dynamic power by 50% while maintaining the same functionality as compared to design 4.