Command interface systems and methods

Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed.

BACKGROUND

Some electronic devices can operate according to external command signals or internal command signals depending on the operating mode. For example, an electronic device may operate according to internal command signals during a sleep mode, and then switch to operate according to external command signals when not in the sleep mode.

When switching modes of operation, there can be a function failure due to an unexpected command at the boundary of transfer between operations according to external command signals and operations according to internal command signals. This function failure is also called a command hazard.

DETAILED DESCRIPTION

Digital signals are shown in the Figures and will be included in the following description. A “high” digital signal has a high voltage and may also be called high, a high signal, or be referred to as being at a high level. A “low” digital signal has a low voltage and may also be called low, a low signal, or be referred to as being at a low level. In some embodiments, a high digital signal has a higher voltage level than that of the low digital signal.

FIG. 1is a block diagram of a system50including a memory device100and a processor101according to an embodiment of the invention. The memory device100includes a control logic circuit102coupled to receive external command signals from the processor101.

The external command signals include a clock enable signal CKE at a pin106, a clock signal CLK at a pin108, and a clock signal CLK/ at a pin110. The “/” designation indicates that the signal is active low. A pin is a conductive physical device such as a wire or a metallic terminal and is a specific type of port through which an external signal is coupled to an electronic device such as the memory device100. The active low clock signal CLK/ is the clock signal CLK inverted. The clock enable signal CKE is a signal instructing validity of the following clock signal. When the signal CKE is at the high level, the rising edge of the following clock signal CLK is valid. When the signal CKE is at the low level, the rising edge of the following clock signal CLK is invalid. The external command signals also include a chip select signal CS/ at pin112, a write enable signal WE/ at a pin114, a column address strobe signal CAS/ at a pin116, a row address strobe signal RAS/ at a pin118, and a data-mask signal DM/ at a pin120. The external command signals at the pins106-120are decoded in a command decoder121.

In addition, the memory device100has one or more mode registers122that are programmed with information for operating the memory device100. The memory device100also includes an address bus124that receives address signals at pins A0-AX, a data bus126that receives and transmits data at pins DQ0-DQX, and a memory circuit128that contains data stored in the memory device100.

The chip select signal CS/ at the pin112is a signal used to select one device, such as the memory device100, out of several devices connected to the same bus. A low CS/ signal enables the command decoder121in the memory device100, and a high CS/ disables the command decoder121. All commands are masked from the memory device100when the CS/ signal is high, but READ/WRITE bursts already in progress will continue to completion, and a data mask (DQM) operation will retain its DQ mask capability while CS/ is high. Thus, the low CS/ signal enables a device connected to a bus to respond to commands and data on the bus while the high CS/ signal tells the device to ignore the bus. The signal CS/ provides for external bank selection on systems with multiple banks.

Address inputs at the pins A0-AX are captured on a falling edge of the row address strobe signal RAS/ at the pin118, and a row corresponding to the address is opened. The row is held open as long as the row address strobe signal RAS/ is low.

Address inputs are captured on a falling edge of the column address strobe signal CAS/ at the pin116, and a column corresponding to the captured address is selected from the currently open row for a read or write operation.

The write enable signal WE/ at the pin114determines whether a given falling edge of the column address strobe signal CAS/ initiates a read or a write operation. A high write enable signal WE/ directs a read operation, while a low write enable signal WE/ directs a write operation. If the write enable signal WE/ is low, data is captured at input pins on the falling edge of the column address strobe signal CAS/.

The signals WE/, CAS/, RAS/, and CS/ can, in various combinations, represent other commands not described above. For example, a high WE/ signal combined with low CKE, CAS/, RAS/, and CS/ signals represent a self-refresh command (SR) and a sleep mode of operation. The CKE signal may change to high to indicate an end of the SR command (and the sleep mode), and the beginning of an auto-refresh (AR) command. Therefore, high WE/ and CKE signals combined with low CAS/, RAS/, and CS/ signals represent the AR command.

The data-mask signal DM/ at the pin120controls input and output over the data bus126during read and write operations. The data bus126is activated to carry data to or from the memory device100if the data-mask signal DM/ is low, and data on the data bus126is masked from the memory device100if the data-mask signal DM/ is high.

The memory circuit128is coupled to the address bus124to receive information identifying a location for reading data to or writing data from the data bus126. Management of read and write operations is performed by the control logic circuit102upon receiving the external command signals from the processor101. The read and write operations of the memory device100are also controlled using a delay lock loop130having a CLK signal input to adjust timing provided to multiple drivers132. Read and write operations are further controlled with a data strobe signal (DQS) that is generated by a DQS generator134coupled to the drivers132. The DQS signal is placed on a DQS line136. In addition, the drivers132put data received from the memory circuit128through a data buffer138on to the data bus126.

The mode registers122have operating information that is programmed by a controller (not shown) on initialization or boot-up of a system including the memory device100. This information includes a burst length that determines the maximum number of column locations that can be accessed for a given read or write command, and a burst type which is either sequential or interleaved. This information also includes a column address strobe signal CAS/ latency that is the number of clock cycles between the registration of a read command by the memory device100and the availability of the first bit of output data from the memory device100. This information also includes an operating mode that is either a normal operation mode or a normal operation mode with a reset of the delay lock loop130.

The memory device100, as well as the mode registers122and the processor101, can each be realized as a single integrated circuit. The memory device100can be formed on a semiconductor die using a substrate, where the substrate is a material such as silicon, germanium, silicon on sapphire, gallium arsenide, or other semiconductor material. The elements of the memory device100are fabricated using conventional processing, well-known to those of ordinary skill in the art, to form the various circuits within the semiconductor material and for providing electrical connections for coupling to an address bus, a data bus, and control lines for communication with a controller or a processor.

FIG. 2is a block diagram of a memory device200according to an embodiment of the invention. The memory device200may be similar to or identical to the memory device100ofFIG. 1. According to some embodiments, the memory device200is a synchronous dynamic random access memory (SDRAM).

The processing of external command signals and address signals received in buffer circuits in the memory device200will now be described. External address signals are received in a buffer210, external command signals RAS/, CAS/, WE/, and CS/ are received in a buffer216, an external clock signal CK is received in a buffer220, and a clock enable signal CKE is received in a buffer226. A reference voltage VREF is received in a buffer230, and a data mask signal DM/ is received in a buffer234. Data signals DQ are exchanged across a two way buffer238coupled to a data register240. The signal DM/ is coupled through the buffer234to the data register240to control the movement of data. An internal input/output (I/O) bus242exchanges data between the data register240and a number of arrays246of memory cells. Each array246includes a column decoder, a row decoder, and an array of memory cells to store data—including a parity area of memory cells. Data is also exchanged from the internal I/O bus242with an error correcting code (ECC) encoder/decoder circuit250in a control circuit block252.

Control circuits in the control circuit block252control operations of the memory device200during a sleep mode of operation. An ECC controller254and a state machine258are also located in the control circuit block252. A power controller260exchanges control signals with a plurality of internal voltage generators262. A temperature sensor circuit264senses a temperature of the memory device200and provides a signal indicating the temperature to an oscillator block270.

The oscillator block270generates clock signals that are coupled to the power controller260, the ECC controller254and the state machine258. The oscillator block270generates an internal clock signal SDCLK that is coupled to an input of a multiplexer272, a second input of the multiplexer272is coupled to receive the external clock signal CK from the buffer220. The multiplexer272generates an internal clock signal ICK to clock operations in the memory device200. The internal clock signal ICK is derived from the external clock signal CK outside the sleep mode of operation, but is derived from the internal clock signal SDCLK during the sleep mode of operation.

The state machine258issues enable signals OscEn to enable the oscillator block270. The oscillator block270generates an internal clock signal ECCLK that is coupled to the ECC controller254for decoding operations.

The external command signals RAS/, CAS/, WE/, and CS/ are coupled from the buffer216to an input of a multiplexer274. A second input of the multiplexer274is coupled to receive internal command signals generated by the ECC controller254. External address signals are coupled from the buffer210to an input of a multiplexer276, and a second input of the multiplexer276is coupled to receive internal address signals from the ECC controller254.

The state machine258generates several super low power flag signals SLPF, SLPFpre, and SLPFpost on lines280that are coupled to the multiplexers272,274and276to control them during the sleep mode of operation. Super is a term of art and does not reflect a particular voltage level. The signals SLPF, SLPFpre, and SLPFpost are used to control the memory device200during the sleep mode of operation, and a potential timing relationship between the signals SLPF, SLPFpre, and SLPFpost will be described below with respect toFIG. 9. The oscillator block270also generates timing signals that are coupled to the power controller260, the ECC controller254, and the state machine258. A clock enable CKE control circuit282is coupled to receive the clock enable signal CKE from the buffer226, and generates a SR signal to indicate the SR command on a line284in response to the clock enable signal CKE. The SR signal on the line284is coupled to the state machine258that generates the signals SLPF, SLPFpre, and SLPFpost based on the SR signal.

The internal clock signal ICK is coupled from the multiplexer272to a command decoder286and an address register288. The multiplexer272chooses the source of the internal clock signal ICK based on the signals SLPF, SLPFpre, and SLPFpost on the lines280. The multiplexer274couples command signals to the command decoder286, selecting either the external commands from the buffer216or the internal commands from the ECC controller254based on the signals SLPF, SLPFpre, and SLPFpost on the lines280. The multiplexer276couples address signals to the address register288, the address signals being either the external address signals from the buffer210or the internal address signals from the ECC controller254based on the signals SLPF, SLPFpre, and SLPFpost on the lines280.

The command decoder286generates an auto refresh command (AR) signal on the line289depending on the commands that it receives, and the AR signal is coupled to the clock enable CKE control circuit282, a refresh counter290, and a multiplexer292. The signals SLPF, SLPFpre, and SLPFpost on the lines280are also coupled to the refresh counter290, which provides data to the multiplexer292that is in turn coupled to a row address latch294, and a bank control logic circuit296. The multiplexer292is coupled to receive address signals from the address register288which are also supplied to a column address latch and counter298. The row address latch294, the bank control logic circuit296, and a column address latch and counter298are coupled to provide control signals to the arrays246.

FIG. 3is a block diagram of control circuits300in a memory device according to an embodiment of the invention. The control circuits300include a state machine302that controls the memory device during a sleep mode of operation, similar to the state machine258shown inFIG. 2.

Others of the control circuits300are similar to circuits having the same name in the memory device200shown inFIG. 2. For example, a clock enable CKE control circuit304generates a SR entry signal on a line306and a SR exit signal on a line308that are coupled to the state machine302. The SR entry signal and the SR exit signal are also coupled to a logic circuit310as is a power-down signal PD on a line312. The PD signal indicates a power-down mode of operation for the memory device when direct current (DC) power dissipation is reduced by, for example, disabling input buffers. An ECC controller316generates a READY signal on a line318that is coupled to the state machine302, and the state machine302generates an Encode/Decode signal on a line320that is coupled to the ECC controller316. The READY signal is generated by the ECC controller316when a decoding operation is complete. The logic circuit310generates control signals as will be described with reference toFIG. 4below.

A power-off timer circuit326generates a T_READY signal on a line328coupled to the state machine302, and the state machine302generates a TIMER signal on a line330that is coupled to the power-off timer circuit326. The state machine302receives a clock signal MSTCLK on a line340that is generated by an oscillator block342. The clock signal MSTCLK is inverted by an inverter344to generate a clock signal MSTCLK/ on a line346. The clock signal MSTCLK is a basic clock signal that controls all states implemented by the state machine302.

The state machine302generates a super low power signal SLP on a line350that is coupled through a first flip flop352timed by the clock signal MSTCLK to generate a SLPF signal on a line354. The SLP signal on the line350is coupled through a second flip flop360timed by the clock signal MSTCLK/ to generate a SLPFpre signal on a line362. The SLPFpre signal on the line362is coupled through a third flip flop370that is also timed by the clock signal MSTCLK/ to generate a SLPFpost signal on a line372. The signals SLPF, SLPFpre, and SLPFpost are used to control the memory device during the sleep mode of operation, and a timing relation between the signals SLPF, SLPFpre, and SLPFpost will be described below with respect toFIG. 9.

FIG. 4is a block diagram of a logic circuit400in a memory device according to an embodiment of the invention. The logic circuit400is an embodiment of the logic circuit310shown inFIG. 3, and generates a variety of control signals based on the states of signals SLPFpre, SLPF, and SLPFpost.

The signals PD and SR are coupled to inputs of a NOR gate402and an output of the NOR gate402is coupled to an input of an inverter404to generate a control signal EN0/ that is coupled to an input of an inverter406to generate a control signal EN0. The signal SR is also coupled to an input of an inverter408to generate a signal ENCMD that is coupled to inputs of a NAND gate410, a NAND gate412, a NOR gate414, and a NAND gate416. The signal SLPFpre is coupled to an input of an inverter418to generate an inverted signal SLPFpre/ that is coupled to an input of the NAND gate410. The signal SLPFpre is also coupled to an input of a NOR gate420. The signal SLPF is coupled to an input of an inverter422, a second input of the NOR gate414, and an input of a NOR gate424. The inverter422generates an inverted signal SLPF/ that is coupled to a second input of the NAND gate412. An output of the NAND gate412generates a control signal EN2/ that is coupled to an input of an inverter426to generate a control signal EN2. The NAND gate410generates a control signal EN1/ that is coupled to an input of an inverter428to generate a control signal EN1. The NOR gate414generates a control signal EN3/ that is coupled to an input of an inverter430to generate a control signal EN3. The signal SLPFpost is coupled to an input of an inverter432to generate an inverted signal SLPFpost/ that is coupled to a second input of the NOR gate420. The NOR gate420generates a control signal ECMCS/ that is coupled to an input of an inverter434to generate a control signal ECMCS. The inverted signal SLPFpost/ is also coupled to a second input of the NAND gate416, the NAND gate416to generate a control signal EN2CS/ that is coupled to an input of an inverter436to generate a control signal EN2CS that is coupled to a second input of the NOR gate424. The NOR gate424generates a control signal EN3CS/ that is coupled to an input of an inverter440to generate a control signal EN3CS.

The control signals generated by the logic circuit400shown inFIG. 4are used to control the buffers and multiplexers in the memory device200shown inFIG. 2during the sleep mode of operation.

FIG. 5is an electrical schematic diagram of a buffer circuit502and a multiplexer504in a memory device according to an embodiment of the invention. The buffer circuit502and the multiplexer504are embodiments of the buffer circuits and multiplexers of the memory device200shown inFIG. 2.

The buffer circuit502and the multiplexer504include an arrangement of transistors that are the same as an arrangement of transistors in buffer circuits and multiplexers shown inFIGS. 6,7and8. These transistors will be described with respect toFIG. 5; the corresponding transistors shown inFIGS. 6-8will be given the same reference numerals and will not be further described herein for purposes of brevity.

The buffer circuit502includes a p-channel transistor510having a source coupled to a supply voltage Vdd and a drain. A gate of the p-channel transistor510is coupled to receive the signal EN0/ that is also coupled to a gate of an n-channel transistor512, the n-channel transistor512having a drain coupled to an output line514and a source coupled to a ground voltage reference Vss. The p-channel transistor510and the n-channel transistor512enable the buffer circuit502to pass a signal to the multiplexer504. The drain of the p-channel transistor510is coupled to a source of a p-channel transistor520and to a source of a p-channel transistor522that are coupled in parallel, a drain of the p-channel transistor520being coupled to a drain of an n-channel transistor530and a drain of the p-channel transistor522being coupled to a drain of an n-channel transistor532. Sources of the n-channel transistors530and532are coupled to the ground voltage reference Vss. A voltage reference Vref is coupled to a gate of the p-channel transistor520and to a gate of the n-channel transistor532. A gate of the n-channel transistor530is coupled to the drains of the n-channel transistors532and512and the output line514.

An external signal is coupled to a gate of the p-channel transistor522such that the buffer circuit502generates the external signal on the output line514. InFIG. 5, the buffer circuit502receives and then generates the external command signal CS/ on the output line514.

The signal on the output line514is coupled to a gate of a p-channel transistor540and a gate of an n-channel transistor542in the multiplexer504. The p-channel transistor540and the n-channel transistor542operate as an inverter to invert the signal on the output line514at an output on a line546connected to a drain of the p-channel transistor540and a drain of the n-channel transistor542.

Operation of the multiplexer504is controlled by several of the control signals shown inFIG. 4. The control signal EN2CS/ is coupled to a gate of a p-channel transistor550having a source coupled to the supply voltage Vdd and a drain coupled to a source of the p-channel transistor540. The control signal EN2CS is coupled to a gate of an n-channel transistor552having a drain coupled to a source of the n-channel transistor542and a source coupled to the ground voltage reference Vss. The control signals EN2CS/ and EN2CS thereby enable the inverter, including the transistors540and542, to pass the signal on the output line514to the line546in inverted form. The control signals EN2CS/ and EN2CS can also disable the inverter including the transistors540and542such that an internal command signal ECMCS/ can be passed to the line546through a pass gate including a p-channel transistor560and an n-channel transistor562. A source of the p-channel transistor560is coupled to a drain of the n-channel transistor562, and a drain of the p-channel transistor560is coupled to a source of the n-channel transistor562. A gate of the p-channel transistor560is coupled to receive the signal SLPF/ and a gate of the n-channel transistor562is coupled to receive the signal SLPF such that, during the sleep mode of operation, the internal command signal ECMCS/ is coupled through the transistors560and562to the line546. A p-channel transistor570includes a source coupled to the supply voltage Vdd and a drain coupled to the line546and the transistors560and562to enable the transistors560and562to pass the internal command signal ECMCS/ to the line546. The p-channel transistor570has a gate coupled to the control signal EN3CS. The signal on the line546is inverted twice, by first and second inverters580and582, and then passed to a command decoder.

FIG. 6is an electrical schematic diagram of a buffer circuit602and a multiplexer604in a memory device according to an embodiment of the invention. The buffer circuit602and the multiplexer604are embodiments of the buffer circuits and multiplexers of the memory device200shown inFIG. 2.

The buffer circuit602represents several buffer circuits that receive and then generate the external command signals RAS/, CAS/, and WE/ on an output line614. The buffer circuit602is enabled by the control signal EN0/. The inverter including the transistors540and542in the multiplexer604is enabled by the control signals EN2/ and EN2, while the pass gate including the transistors560and562is enabled by the control signal EN3and the signals SLPF/ and SLPF. The multiplexer604passes on the external command signals RAS/, CAS/, and WE/ to the line646when the inverter including the transistors540and542is enabled, and passes corresponding internal command signals ECMRAS/, ECMCAS/, and ECMWE/ to the line646when the pass gate including the transistors560and562is enabled. The signals on the line646are inverted twice, by first and second inverters680and682, and then passed to a command decoder.

FIG. 7is an electrical schematic diagram of a buffer circuit702and a multiplexer704in a memory device according to an embodiment of the invention. The buffer circuit702and the multiplexer704are embodiments of the buffer circuits and multiplexers of the memory device200shown inFIG. 2.

The buffer circuit702represents several buffer circuits that receive and then generate the external address signals A0, A1, A2. . . BA0, BA1, . . . on an output line714. The buffer circuit702is enabled by the control signal EN0/. The inverter including the transistors540and542in the multiplexer704is enabled by the control signals EN2/ and EN2, while the pass gate including the transistors560and562is enabled by the control signal EN3and the signals SLPF/ and SLPF. The multiplexer704passes on the external address signals A0, A1, A2. . . BA0, BA1, . . . to the line746when the inverter including the transistors540and542is enabled, and passes corresponding internal address signals ECA0, ECA1, ECA2. . . ECBA0, ECBA1, . . . to the line746when the pass gate including the transistors560and562is enabled. The signals on the line746are inverted twice, by first and second inverters780and782, and then passed to a command decoder.

FIG. 8is an electrical schematic diagram of a buffer circuit802and a multiplexer804in a memory device according to an embodiment of the invention. The buffer circuit802and the multiplexer804are embodiments of the buffer circuits and multiplexers of the memory device200shown inFIG. 2.

The buffer circuit802receives and then generates the external clock signal CK on an output line814. The buffer circuit802is enabled by the control signal EN0/. The inverter including the transistors540and542in the multiplexer804is enabled by the control signals EN1/ and EN1, while the pass gate including the transistors560and562is enabled by the signals SLPFpre/ and SLPFpre. The gate of the p-channel transistor570is coupled to the supply voltage Vdd. The multiplexer804passes on the external clock signal CK to the line846when the inverter including the transistors540and542is enabled, and passes a corresponding internal clock signal SDCLK to the line846when the pass gate including the transistors560and562is enabled. The signals on the line846are inverted twice by first and second inverters880and882and then are passed to other circuits in the memory device.

The control signals shown and described inFIGS. 5,6,7, and8are generated by the logic circuit400shown inFIG. 4and described above. The corresponding internal command signals and internal address signals are generated by an ECC controller such as the ECC controller254shown inFIG. 2during a sleep mode of operation. The corresponding internal clock signal SDCLK is generated by an oscillator block such as the oscillator block270shown inFIG. 2. The internal command signals are passed to a command decoder such as the command decoder286shown inFIG. 2.

FIG. 9is a timing chart900of a memory device according to an embodiment of the invention. The timing chart900includes the signals SLPFpre, SLPF, and SLPFpost generated by the control circuits300shown inFIG. 3and the state machine258shown inFIG. 2, and control signals generated by the logic circuit400shown in FIG.4,. The timing chart900also shows the clock enable signal CKE and external commands received by the memory device200shown inFIG. 2. In particular, the SR command, the AR command, and the SR signal are shown in the timing chart900. The signals are shown with reference to voltage on a vertical axis902, and with respect to time on a horizontal axis904.

As described above, a high WE/ signal combined with low CKE, CAS/, RAS/, and CS/ signals represent the SR command and the beginning of a sleep mode of operation. The SR signal goes high on a rising edge910following a falling edge of the clock enable signal CKE to begin the sleep mode, and the SR signal goes low on a falling edge912following a rising edge of the clock enable signal CKE to indicate the end of the sleep mode. The rising edge of the clock enable signal CKE indicates the beginning of the AR command.

The signal SLPFpre leads the signal SLPF, while the signal SLPFpost lags the signal SLPF.

The signals in the timing chart900show in particular the activity of the internal chip select signal ECMCS/. With reference toFIG. 5, the control signal EN2CS/ disables the inverter while the signal SLPF enables the pass gate in the multiplexer504to pass the internal chip select signal ECMCS/ to the command decoder during the sleep mode of operation.

At the end of the sleep mode of operation, designated by the falling edge912of the SR signal, the memory device enters a transfer state over a transfer period TRANSFER when operation according to internal commands ends and operation according to external commands begins. The external command AR is received during the transfer period. The internal chip select signal ECMCS/ generated by the ECC controller is high for a short time between its rising edge920and its falling edge922and is coupled to the command decoder to disable the command decoder during the transfer period. In this way, commands will not be decoded and the execution of commands will be suspended while the command decoder is disabled. The possibility of command hazard events are therefore substantially reduced, because unexpected commands will not be decoded while the command decoder is disabled by the high internal chip select signal ECMCS/ during the transfer period.

FIG. 10is a state transition diagram1000of states in a sleep mode of a memory device according to an embodiment of the invention. Commands executing the transitions in the state transition diagram1000are generated by a state machine such as the state machine258shown inFIG. 2.

A decoding state1006occurs during system recovery when transitioning from battery power. In the decoding state1006, syndrome patterns are calculated to detect errors in stored data and, if errors are found, the locations of the errors are detected and the erroneous data is corrected.

The state machine shifts to a transfer state1010responsive to the completion of the decoding state1006. The transfer state1010includes the operations described with respect to the timing chart900of the memory device shown inFIG. 9. The transfer state occurs over a transfer time period bridging operation according to internal commands and operation according to external commands. The state machine shifts to an idle state1016responsive to the completion of the transfer state1010. During the idle state1016, the memory device operates according to external commands and an external clock signal.

The idle state1016ends upon the occurrence of the SR command when CKE is low, and the state machine shifts to an encoding state1020. The ECC controller operates the memory device with internal commands and internal addresses and the ECC encoder/decoder circuit is controlled substantially simultaneously to calculate parity bits during the encoding state1020. Parity bits or states are calculated and written to the arrays in the encoding state1020. The encoding state1020can be interrupted by a high CKE signal in which case the state machine shifts to the transfer state1010.

The state machine shifts to a burst refresh state1040responsive to the completion of the encoding state1020and CKE remains low. Data in the arrays is refreshed during the burst refresh state1040. The state machine shifts back and forth between the burst refresh state1040and a power off state1060during the sleep mode when CKE is low. If CKE transitions to a high signal during either of the burst refresh state1040or the power off state1060, the state machine shifts to the decoding state1006described above.

Embodiments of the invention described herein may be implemented with any electronic device that transfers between operation according to internal commands and operation according to external commands. The semiconductor device may comprise a processor or a memory device, such as an SDRAM memory or Flash memory.

FIG. 11is a block diagram of a system1160according to an embodiment of the invention. The system1160, in some embodiments, may include a processor1164coupled to a display1168and/or a wireless transceiver1172. The display1168may be used to display data, perhaps received by the wireless transceiver1172. The system1160, in some embodiments, may include a memory device such as a dynamic random access memory (DRAM)1174and/or a Flash memory1175. The processor1164is coupled to exchange data with the DRAM1174and the Flash memory1175. The DRAM1174may be a synchronous DRAM (SDRAM).

In some embodiments, the system1160may include a camera including a lens1176and an imaging plane1180to couple to the processor1164. The imaging plane1180may be used to receive light captured by the lens1176.

Many variations are possible. For example, in some embodiments, the system1160may include a cellular telephone receiver1182forming a pinion of the wireless transceiver1172. The cellular telephone receiver1182may also receive data to be processed by the processor1164, and displayed on the display1168. In some embodiments, the system1160may include an audio, video, or multi-media player1184, including a memory device1185and a set of media playback controls1186to couple to the processor1164. The processor1164may also be coupled to exchange data with an audio device1192and/or a modem1194.

Any of the electronic components of the system1160may include circuits configured to transfer between operation according to internal commands and operation according to external commands according to embodiments of the invention described herein. In particular, the processor1164issues external commands to be received and processed by components such as the DRAM1174, the Flash memory1175, and the memory device1185. One or more of the DRAM1174, the Flash memory1175, and the memory device1185include circuits configured to transfer between operation according to internal commands and operation according to external commands according to embodiments of the invention described herein.

Any of the circuits or systems described herein may be referred to as a module. A module may comprise a circuit and/or firmware according to embodiments of the invention.

FIG. 12is a flow diagram of several methods1200according to an embodiment of the invention. In block1210, the methods1200start.

In block1220, internal commands are executed with a command decoder in a dynamic random access memory device during a sleep mode of operation, the internal commands being carried by internal command signals.

In block1230, the sleep mode of operation is ended following a change in external command signals and the execution of internal commands and external commands is suspended during a transfer period when an internal active low chip select signal is high to disable the command decoder.

In block1240, external commands are executed with the command decoder during a second mode of operation following the transfer period, the external commands being carried by the external command signals. In block1250, the methods1200end.

The individual activities of methods1200may not have to be performed in the order shown or in any particular order. Some activities may be repeated, and others may occur only once. Embodiments of the invention may have more or fewer activities than those shown inFIG. 12.

The novel apparatus and systems of various embodiments may include and/or be included in electronic circuitry used in high-speed computers, communication and signal processing circuitry, single or multi-processor modules, single or multiple embedded processors, multi-core processors, data switches, and application-specific modules including multilayer, multi-chip modules. Such apparatus and systems may further be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others. Some embodiments may include a number of methods, as described above.