Radiation hardened 10BASE-T ethernet physical layer (PHY)

Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

FIELD OF THE INVENTION

The present invention relates to Ethernet systems, and more particularly to radiation hardened Ethernet systems in compliance with the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard for Ethernet and suitable for space flight.

BACKGROUND

Communications systems used in spacecraft, such as space stations (e.g., the International Space Station (ISS), space vehicles, small satellites or nanosatellites (e.g., CubeSats), avionics (e.g., SpaceCube), etc., face challenges generally not encountered by earth based communication systems, such as radiation exposure and stringent piece part reliability requirements. Specifically, current 10BASE-T Ethernet interface circuits in compliance with the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard for Ethernet do not meet the radiation hardening requirements for space flight. The currently available commercial off the shelf (COTS) 10BASE-T Ethernet interface circuits are not acceptable for space flight because the COTS 10BASE-T Ethernet interface circuits are susceptible to radiation induced upsets and/or failure. Therefore, a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet is needed.

SUMMARY

The various embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened. In various embodiments, the FPGA may include a physical layer interface module configured to exchange data with a media access controller (MAC). In various embodiments, the transmitter circuit may be configured to receive a transmission signal, such as a transmission signal including a link pulse, from the physical layer interface module, and the transmitter circuit may comprise an amplification stage configured to amplify the transmission signal, and a filter stage connected to the amplification stage and configured to filter the amplified transmission signal. In various embodiments, the receiver circuit may be configured to send a difference indication signal to the physical layer interface module, and the receiver circuit may comprise a resistor network configured to reduce an amplitude of a received signal, and a low voltage differential signal receiver connected to the resistor network and configured to output the difference indication signal to the physical layer interface module in response to receiving the reduced amplitude received signal from the resistor network. In the various embodiments, the transformer may be configured to receive the filtered amplified transmission signal from the filter stage and output the filtered amplified transmission signal to a connector, and receive the received signal from the connector and output the received signal to the resistor network.

DETAILED DESCRIPTION

Currently available commercial off the shelf (COTS) 10BASE-T Ethernet interface circuits are not acceptable for space flight because the COTS 10BASE-T Ethernet interface circuits are susceptible to radiation induced upsets and/or failure and are limited in reliability. The current COTS 10BASE-T Ethernet interface circuits rely on non-radiation hardened chipsets that provide IEEE 802.3 standard for Ethernet physical layer interfaces separate from field programmable gate arrays (FPGAs) and/or processors, including FPGAs and/or processors hosting media access controllers (MACs) and/or user applications. Thus, the current COTS 10BASE-T Ethernet interface circuits do not provide physical layer interfaces for IEEE 802.3 standard for Ethernet on radiation hardened FPGAs.

The various embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. In various embodiments, a custom circuit may be used in conjunction with a front-end FPGA to implement an Ethernet physical layer (PHY) in compliance with the IEEE 802.3 standard for Ethernet. In the various embodiments, the custom circuit may make use of radiation hardened parts. In the various embodiments, the custom circuit may handle the electrical interface between standard differential Ethernet signals and the digital signal levels in the FPGA. The portion of the Ethernet PHY that may be located in the FPGA, such as a physical layer interface module, may handle meeting the protocol requirements of the IEEE 802.3 standard for Ethernet. The portion of the Ethernet PHY that may be located in the FPGA, such as a physical layer interface module, may be responsible for decoding received signals, such as packets, link pulses, etc., and encoding transmitted signals, such as data packets, link pulses, etc. Decoded payload data may be sent to a user interface or application (internal to the FPGA or running on a connected processor) and the user interface or application may send data for transmission back to the portion of the Ethernet PHY that may be located in the FPGA.

The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a FPGA, a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened. In various embodiments, the FPGA may include a physical layer interface module configured to exchange data with a MAC. In various embodiments, the transmitter circuit may be configured to receive a transmission signal from the physical layer interface module, and the transmitter circuit may comprise an amplification stage configured to amplify the transmission signal, and a filter stage connected to the amplification stage and configured to filter the amplified transmission signal. In the various embodiments, the transmission signal from the physical layer interface module may be a link pulse, idle pulse, user data, any other type Ethernet data, or any other type mode supported by the IEEE 802.3 standard for Ethernet. In various embodiments, the receiver circuit may be configured to send a difference indication signal to the physical layer interface module, and the receiver circuit may comprise a resistor network configured to reduce an amplitude of a received signal, and a low voltage differential signal receiver connected to the resistor network and configured to output the difference indication signal to the physical layer interface module in response to receiving the reduced amplitude received signal from the resistor network. In the various embodiments, the received signal and the resulting difference indication signal from the physical layer interface module may be a link pulse, idle pulse, user data, any other type Ethernet data, or any other type mode supported by the IEEE 802.3 standard for Ethernet. In the various embodiments, the transformer may be configured to receive the filtered amplified transmission signal from the filter stage and output the filtered amplified transmission signal to a connector, and receive the received signal from the connector and output the received signal to the resistor network. The various embodiments may provide a provide a 10BASE-T Ethernet interface circuit suitable for space flight that may provide a 10BASE-T link pulse transmit mask and data mask according to the IEEE 802.3 standard for Ethernet, using operational amplifiers with very high slew rate and high bandwidth and which may be radiation hardening to 100 kRads.

FIG. 1is block diagram of an Ethernet communication system100according to an embodiment including a 10BASE-T Ethernet Physical Layer provided by a 10BASE-T Ethernet interface circuit102. The 10BASE-T Ethernet interface circuit102may include a FPGA108including a physical layer interface module110, a transmitter circuit104connected to the FPGA108, such as by one or more wire and/or circuit board line to one or more pin of the FPGA108, a receiver circuit106connected to the FPGA108, such as by one or more wire and/or circuit board line to one or more pin of the FPGA108, and a connector107connected to the transmitter circuit104and receiver circuit106, such as by one or more wire and/or circuit board line. The FPGA108, the transmitter circuit104, the receiver circuit106, and the connector107may be radiation hardened parts, such as parts radiation hardened to withstand 100 kRads of radiation. In one embodiment, the connector107may not be a RJ-45 connector. In other embodiments, the connector107may be any type connector, including a RJ-45 connector. The connector107may enable the 10BASE-T Ethernet interface circuit102to connect to a IEEE 802.3 standard for Ethernet compliant node112in the system100via one or more wires and send and receive signals with the node112according to the IEEE 802.3 standard for Ethernet.

The physical layer interface module110of the FPGA108may exchange data with a MAC114which may exchange data with a user application116. In some embodiments the MAC114and/or user application116may be running on the FPGA108. In other embodiments, the MAC114and/or user application116may be running on a separate processor118connected to the FPGA108, such as by one or more wire and/or circuit board line to one or more pin of the FPGA108. The user application116may send and/or receive data for transmission to the node112via the MAC114and the 10BASE-T Ethernet interface circuit102. The physical layer interface module110of the FPGA108may include both a media-independent interface (MII) and management data input/output interface (MDIO) connection to the MAC114and the physical layer interface module110may be configured to implement physical layer signaling and transmit and receive functions according to the IEEE 802.3 standard for Ethernet. While illustrated as a single FPGA108inFIG. 1, FPGA108may include two or more FPGAs connected together and functions of the physical layer inference module110may be distributed across the more than one FPGA. As examples, the FPGA108may be a Xilinx® XC4VFX60-FF152 FPGA, an Aeroflex® FPGA, RTAX2000-CQ352 FPGA, combinations of one or more Xilinx® XC4VFX60-FF152 FPGAs, one or more Aeroflex® FPGAs, and/or one or more RTAX2000-CQ352 FPGA, or any other type FPGAs. In the various embodiments, internal block memory (e.g., BRAM) cells of the FPGA108, such as internal BRAM cells of an RTAX2000-CQ352 FPGA, may not be used to store programming and/or handle data associated with the physical layer inference module110as the cells may be susceptible to radiation induced upsets.

In operation, data from the MAC114for transmission to the node112may be converted by the physical layer interface module110of the FPGA108to a transmission signal output to the transmitter circuit104. The transmission signal may include a positive and negative component. The positive and negative components of the transmission signal may be digital signals and the transmitter circuit104may convert the digital signals to analog waveforms with voltage levels and shapes conforming to the IEEE 802.3 standard for Ethernet through various operations on the transmission signal, including amplification and filtering. The amplified and filtered transmission signal including positive and negative components with analog waveforms with voltage levels and shapes conforming to the IEEE 802.3 standard for Ethernet may be output to the connector107and sent to the node112as an Ethernet transmit (Tx) differential signal (e.g., Tx+ and Tx−). The node112may also output a signal to the connector107, such as an Ethernet receive (Rx) differential signal (e.g., Rx+ and Rx−). The received signal from the node112may be an analog signal with a positive and negative component with analog waveforms with voltage levels and shapes conforming to the IEEE 902.3 standard for Ethernet. The receiver circuit106may receive the received signal from the connector107and generate a difference indication signal and send the difference indication signal to the physical layer interface module110of the FPGA108. The physical layer interface module110of the FPGA108may convert the difference indication signal to data and provide the data to the MAC114. For example, based on the difference indication signal the physical layer interface module110of the FPGA108may determine whether the received signal that resulted in the generation of the difference indication signal may be a link pulse, idle pulse, user data, any other type Ethernet data, or any other type mode supported by the IEEE 802.3 standard for Ethernet, and in response to determining the type mode of the received signal and resulting difference indication signal physical layer interface module110of the FPGA108may convert the difference indication signal to data and provide the data to the MAC114.

FIG. 2is a block diagram of the 10BASE-T Ethernet interface circuit102showing circuit elements of the transmitter circuit104and receiver circuit106and the connections to the physical layer interface module110. A transmission output (phy_td) from the physical media attachment (PMA) function202of the physical layer interface module110may be split into two separate components, and one of the two components may be inverted such that the inverted component may be the negative component of the transmission signal and the un-inverted component may be the positive component of the transmission signal. The transmission signal from the transmission output (phy_td) may be sent to an amplification stage204of the transmitter circuit104. The amplification stage204may be configured to amplify the transmission signal. For example, the amplification stage204may have a gain of −1.52 or any other gain, and the gain may be selected based on the voltage of the FPGA108. For example, when the FPGA108has a voltage level of 3.3 volts, the gain of the amplification stage204may be −1.52 and gain may be different when the voltage level of the FPGA108is different to compensate for the voltage level of the FPGA108.FIGS. 3A-3Ddiscussed below illustrate example configurations of the amplification stage204. As general examples, the amplification stage204may include two AD844 op amps from Analog Devices and the op amps may be tuned to amplify and filter the differential data sent from the FPGA to meet the signal levels and speeds required by the IEEE 802.3 standard for Ethernet (e.g., 10 Mbps).

The amplification stage204may be connected to the filter stage206of the transmitter circuit104and the amplification stage204may output positive and negative components of the amplified transmission signal to the filter stage206which may filter the transmission signal amplified by the amplification stage204. For example, the filter stage206may be a high pass filter. A high pass filter will return the differential pair signals (TX+, TX−) to a differential voltage of 0V when not transmitting signals, such as data or link pulses.FIG. 4discussed below illustrates an example configuration of the filter stage206. The filter stage206may output positive and negative components of the filtered amplified transmission signal to the transformer208. The transformer208may be single transformer dedicated to the transmitter circuit104or may be a shared transformer208with separate transformer portions shared by the transmitter circuit104and receiver circuit106. The transformer208may be a 1 to 1 (1:1) transformer that may provide electrical isolation to the 10BASE-T Ethernet interface circuit102. The transformer208may output the received positive and negative components of the filtered amplified transmission signal to the connector107.FIGS. 6A and 6Bdiscussed below illustrate example configurations of the transformer208.

The connector107may output the positive and negative components of the received differential signal (e.g., Rx+ and Rx−) to the transformer208and the transformer208may output the received signal to a resistor network212of the receiver circuit106. The resistor network212may reduce the amplitude of the received signal. For example, the resistor network212may reduce the voltage of the received signal to a value in the range of 300 mV to 1V.FIG. 5discussed below illustrates an example configuration of a resistor network212. The resistor network212may be connected to a low voltage differential signal receiver, such as a low voltage differential multi-drop (LVDM)/low voltage differential signal (LVDS) device214, and the resistor network212may output the positive and negative components of the reduced amplitude received signal to the LVDM/LVDS214. The LVDM/LVDS214may compare the positive and negative components of the reduced amplitude received signal and may drive a high signal (e.g., a “1”), when the differential is above a threshold, such as greater than −200 mV, which may cover a range when the absolute value of the differential voltage is less than 200 mV. The output of the LVDM/LVDS214may be a difference indication output to the reception input (phy_rd) at the PMA function202of the physical layer interface module110(e.g., a difference indication signal). In an embodiment, the receive pairs may be crossed at the transformer208such that a negative difference indication signal may be generated and passed to the FPGA108and the FPGA may invert the negative difference indication signal such that the difference indication is positive when received at the reception input (phy_rd) at the PMA function202. This inversion of the difference indication signal may be required when the LVDM/LVDS214defaults to driving a logic ‘1’ to the physical layer interface module110when the received differential signal is 0V.

FIGS. 3A, 3B, 3C, and 3Dare block diagrams of various embodiment amplifier stages204A-204D suitable for use in the transmitter circuit104of the 10BASE-T Ethernet interface circuit102illustrated inFIG. 2.FIG. 3Aillustrates a first configuration of an amplification stage204A including a voltage translator302connected to a first inverting op amp304and a second inverting op amp306. The voltage translator302may translate the voltage level of the transmission signal from 3.3 volts to 5.0 volts, or any other voltage as needed based on the FPGA108voltage and the positive and negative components of the transmission signal may be passed to the first inverting op amp304and second inverting op amp306, respectively. As an example, first inverting op amp304and second inverting op amp306may have −1.0 voltage gains. The positive component of the transmission signal may be translated by the voltage translator302and amplified by the first inverting op amp304and the negative component of the transmission signal may be translated by the voltage translator302and amplified by the second inverting op am306. The inverting op amps304and306may be high speed current feedback operational amplifiers with high slew rates, such as up to 2000 V/μsec and bandwidths of 60 MHz at a gain of −1, such as AD844 monolithic op amps. The amplification stage204A may be configured as a push-pull amplifier using the two op amps304and306and may result in a very low distortion transformer driver with a gain of −1, which may basically become a different input and differential output amplifier.FIG. 3Billustrates a second configuration of an amplification stage204B including just two inverting op amps304and306without voltage translator302. As an example, first inverting op amp304and second inverting op amp306may have −1.52 voltage gains in amplification stage204B. The positive component of the transmission signal may be amplified by the first inverting op amp304and the negative component of the transmission signal may be amplified by the second inverting op am306.FIG. 3Cillustrates a third configuration of an amplification stage204C in which the second inverting op amp306may be replaced with a direct current (DC) voltage source308. The DC voltage source308may output a negative DC voltage while the positive component of the transmission signal may be amplified by the first inverting op amp304. In an alternate embodiment, the first inverting op amp304may be replaced with a non-inverting op amp in amplification stage204C.FIG. 3Dillustrates a fourth configuration of an amplification stage204D including two non-inverting op amps310and312. As an example, first non-inverting op amp310and second non-inverting op amp312may have +1.52 voltage gains in amplification stage204D. The positive component of the transmission signal may be amplified by the first non-inverting op amp310and the negative component of the transmission signal may be amplified by the second non-inverting op am312. In the amplification stage configurations, when non-inverting op amps are selected, the signals for the positive and negative Ethernet transmissions may not need to be crossed across the transformer stage.

FIG. 4is a block diagram of an example filter stage206A suitable for use in the transmitter circuit104of the 10BASE-T Ethernet interface circuit102illustrated inFIG. 2. The filter stage206A may include a resistor402and capacitor408connected in series on the positive transmission signal line of the filter stage206A and resistor406and capacitor408connected in series on the negative transmission signal line of the filter stage206A. A resistor404may be connected across the positive and negative transmission signal lines of the filter stage206A. The resistors402and406may be 56 ohm resistors and the resistor404may be a 1000 ohm resistor. The capacitors408and410may be 4700 pF capacitors.

FIG. 5is a block diagram of an example resistor network212A suitable for use in the receiver circuit106of the 10BASE-T Ethernet interface circuit102illustrated inFIG. 2. The resistor network212A may comprise resistors502and506on the positive and negative received signal lines and resistors504and508connected across the positive and negative received signal lines. The resistor504may terminate the twisted pair wires of the Ethernet connection while the resistors502,506and508may act as a voltage divider to scale down the incoming received signal to a level that may be appropriate for the LVDM/LVDS214. The resistor508may be a 100 ohm resistor, the resistors502and506may be 499 ohm resistors, and the resistor508may be a 1000 ohm resistor.

FIGS. 6A and 6Bare block diagrams of example transformer configurations suitable for use in the 10BASE-T Ethernet interface circuit102illustrated inFIG. 2.FIG. 6Aillustrates transformer208A including a transformer section602that may be associated with the transmitter circuit104and a transformer section604that may be associated with the receiver circuit106. The center tap of the FPGA108side of the transformer section602may be connected to a capacitor608and the center tap of the transformer section602on the connector107side may be connected to a resistor606. The resistor606may be a 75 ohm resistor. The center tap of the FPGA108side of the transformer section604may be connected to a DC bias voltage614and the center tap of the transformer section604on the connector107side may be connected to a resistor610. The DC bias voltage614may operate to center the incoming signal to a value around the differential midpoint of the LVDM/LVDS214. The resistor610may be a 75 ohm resistor. The center tap resistors606,610may be connected in series to a capacitor616connected to ground. While illustrated as connected transformer sections602,604comprising one overall transformer208A, the transformer sections602,604may be independent of one another and operate as separate transformers. In such a configuration, the resistors606,610may each be connected to their own respective capacitor. A resistor612, such as a 1000 ohm resistor, may be connected across the positive and negative lines of the transformer section604connected to the connector107. As illustrated inFIG. 6Athe positive and negative lines of the transformer sections602,604may be swapped across the transformer208A before being connected to the connector107. For example, the positive and negative lines of the transformer sections602,604may be swapped across the transformer208A by cross connecting of the positive and negative lines of the transformer sections602,604through one or more board holes618connecting the positive lines of transformer sections602,604to negative transmit and receive pins of the connector107and connecting the negative lines of the transformer sections602,604through one or more board holes618connecting the negative lines of transformer sections602,604to positive transmit and receive pins of the connector107. The swap across the transformer208A may be necessary when inverting op amps are used in the amplification stage204of the transmitter circuit and/or may ensure that a negative difference indication signal is passed from the LVDM/LVDS214to the FPGA108.

FIG. 6Billustrates a transformer208B similar to the transformer208A illustrated inFIG. 6A, except that the positive and negative lines of the transformer sections602,604may not be swapped across the transformer208B before being connected to the connector107. Additionally, in an alternative embodiment, one of either the positive and negative lines of the transformer section602or604may not be swapped across the transformer208B while the other transformer section602or604may be swapped across the transformer208B. For example, the transmitter circuit104may include non-inverting op amps and the positive and negative lines of the transformer section602may not be swapped across the transformer208B while the receiver circuit106associated transformer section604may be swapped across the transformer208B.

FIG. 7is block diagram of logical elements of a physical layer interface module110of a 10BASE-T Ethernet Physical Layer according to an embodiment. The physical layer interface module110may be a container resident on the FPGA that includes a MAC interface and clock enable generator function702, physical layer signaling (PLS) function704, configuration/status logic function706, and the PMA function202. As an example, the physical layer interface module110and the functions702,704,706, and202may be written in Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). The MAC interface and clock enable generator function702(labeled “scphy” inFIGS. 9 and 11) may implement a IEEE 802.3 standard for Ethernet compliant 10BASE-T physical layer transceiver in programmable logic fabric. The MAC interface and clock enable generator function702may be a FPGA fabric-only PHY transceiver created in programmable logic which may be used in a radiation-tolerant FPGA. The MII interface connection from/to the MAC114may carry user data as specified by the IEEE 802.3 standard for Ethernet for connecting a MAC to a PHY. The MDIO interface connection from/to the MAC114may be a PHY control interface specified by IEEE 802.3 standard for Ethernet. These two interfaces may enable the MAC interface and clock enable generator function702to be paired with any MAC core or chip. The MAC interface and clock enable generator function702may handle data provisioning to and from the MAC114, and may provide clock enable management. The physical layer interface module110may run from an oversampled clock to allow it to handle analog signaling as controlled by the MAC interface and clock enable generator function702.

The configuration/status logic function706may include the configuration and status registers for the physical layer interface module110. The PLS function704implements physical layer signaling (PLS) according to the IEEE 802.3 standard for Ethernet. The PLS function704may be an interface layer between the byte-oriented MII interface and the bit-oriented PMA function202. The PLS function704may provide signal encoding/decoding (Manchester), nybble-to-bit conversion, receiver clock recovery, and Ethernet preamble detection. The PMA function202(labeled scphy_pma inFIGS. 9 and 11) may implement the correct electrical waveform formation to transmit and receive the 10BASE-T signals from the analog interface (i.e., the transmitter circuit104and receiver circuit106). PMA function202may implement the Transmit, Receive, Loopback, Jabber Detection, Link Integrity Test, and Collision Presence functions specified in the IEEE 802.3 standard for Ethernet. The PMA function202interfaces directly to the analog interface electronics (i.e., the transmitter circuit104and receiver circuit106), which are external to the host FPGA. By placing the physical layer interface module110in a radiation-hardened FPGA and pairing it with the external analog design (including the digital buffers and transformer) the physical layer interface module110may provide a radiation-hardened 10BASE-T physical interface. While discussed in terms of a radiation hardened FPGA, the design of the physical layer interface module110may be portable into other FPGAs and into other architectures, such as application specific integrated circuits (ASICs).

FIG. 8is an example 10BASE-T Ethernet Physical Layer according to an embodiment andFIG. 9is a block diagram of modules of the FPGA808of the 10BASE-T Ethernet Physical Layer illustrated inFIG. 8. The 10BASE-T Ethernet Physical Layer illustrated inFIG. 8was tested at the University of New Hampshire and verified to adhere to the IEEE 802.3 standard for Ethernet. The 10BASE-T Ethernet Physical Layer illustrated inFIG. 8is designed to work on the Express Logistics Carrier (ELC) system built by NASA Goddard Space Flight Center for installation on the International Space Station (ISS). The 10BASE-T Ethernet Physical Layer illustrated inFIG. 8may include a FPGA808similar to the FPGA108described above, as well as a transmitter circuit including voltage translator302, inverting op amps304,306, filter stage206A, and transformer208A and a receiver circuit including transformer208A, resistor network212A, and LVDM/LVDS214as described above. The inverting op amps304,306may be high speed current feedback operational amplifiers with high slew rates, such as up to 2000 V/sec and bandwidths of 60 MHz at a gain of −1, such as AD844 monolithic op amps. The amplification stage may be configured as a push-pull amplifier using the two op amps304,306and may result in a very low distortion transformer driver with a gain of −1, which may basically become a different input and differential output amplifier. The transmitter circuit may also incorporate a RLC high pass filter as the filter stage206A with Ethernet 10BASE-T dual transformer208A, and may operate as a DC block with a cutoff frequency of approximately 10 kHz with the differential signals for Tx− and Tx+ routed as 50 ohm pairs. As illustrated inFIG. 9, the FPGA808may include various modules including hrdl_sab_rtax902, hrdl_sab_rtax_top904, enet2hrdl_top906, physical layer interface module110, MAC interface and clock enable generator function702, PMA function202, and hrdl_top912. The difference indication signal PAD_ETHER_RX1may be inverted by the MAC interface and clock enable generator function702. The transmission signal PAD_ETHER_TX1_P may be split and one portion inverted by the hardl_sab_rtax module902to generate a negative transmission signal component PAD_ETHER_TX1_N. The signals may be received and/or sent on various pins, A, B, and C of the FPGA808, such as pins325,287, and288, respectively, of a RTAX2000-CQ352 FPGA.

FIG. 10is another example 10BASE-T Ethernet Physical Layer according to another embodiment andFIG. 11is a block diagram of modules of a FPGA1012of the 10BASE-T Ethernet Physical Layer illustrated inFIG. 10. The 10BASE-T Ethernet Physical Layer illustrated inFIG. 10represents an upgrade to the 10BASE-T Ethernet Physical Layer illustrated inFIG. 8with an enhanced transmission portion configured to support data transmission, such as payload data transmission, and not merely link pulse transmission. The 10BASE-T Ethernet Physical Layer illustrated inFIG. 10is designed to work with the SpaceCube and has operated on the ISS communicating with the ELC. Rather than a single FPGA as illustrated inFIG. 8, the 10BASE-T Ethernet Physical Layer illustrated inFIG. 10may include multiple FPGAs1012,1011,1008in communication with one another. For example, the FPGA1012may be a XC4VFX60-FF1152 FPGA in communication with Aeroflex FPGAs1011,1008. The FPGA1008may be connected to the transmitter circuitry and receiver circuitry on a digital control card1004that may connect to a processor card1002including the FPGA1011and FPGA1012. Connectors1009,1010on the digital control card1004and processor card1002, respectively, may connect the FPGAs1012,1011, and1008together. The connectors1009,1010may be stacking connectors. As illustrated inFIG. 11, the FPGA1012on the processor card1002may include the MAC interface and clock enable generator function702, PMA function202. The difference indication signal scphy_0_phy_rd may be inverted by the FPGA1008and provided to the FPGA1012via connectors1009and1010. The transmission signal schpy_0_phy_data_p may be split and one portion inverted by the FPGA1012to generate a negative transmission signal component schpy_0_phy_data_p. The positive and negative transmission signal portions may be sent to the FPGA1011and on to the FPGA1008via connectors1009and1010. The signals may be received and/or sent on various pins, A, B, and C of the FPGA1012, such as pins R27, M13, and M22, respectively, of a XC4VFX60-FF1152 FPGA.

The preceding description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein. The foregoing method descriptions and the process flow diagrams are provided merely as illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the order presented. As will be appreciated by one of skill in the art the order of steps in the foregoing embodiments may be performed in any order. Words such as “thereafter,” “then,” “next,” etc. are not intended to limit the order of the steps; these words are simply used to guide the reader through the description of the methods. Further, any reference to claim elements in the singular, for example, using the articles “a,” “an” or “the” is not to be construed as limiting the element to the singular.