Receiver circuit

A receiver circuit includes: a local signal generation circuit that generates a local signal; and a test signal generation circuit that generates a test signal having a frequency close to a frequency of the local signal, wherein the test signal generation circuit includes an oscillator that generates the test signal, a mixer that mixes the local signal with an output of the oscillator to generate a low-frequency signal which is a difference signal between the local signal and the output of the oscillator, a phase detector that detects a phase difference between the low-frequency signal output by the mixer and a reference signal, and a filter that extracts a low-frequency component from an output of the phase detector, and controls an oscillation frequency of the oscillator by using an output of the filter.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2015-047365, filed on Mar. 10, 2015, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a receiver circuit.

BACKGROUND

In wireless devices, reception characteristics are measured at any time, self-correction is performed based on the measured reception characteristics, and thus high performance and high stability are achieved with low power consumption. To do this, a test signal generation circuit that generates a test signal is provided in a receiver circuit of a wireless device, and the generated test signal is supplied to the receiver circuit. A receiver circuit having such a test signal generation circuit is referred to as a receiving built-in-self-test (BIST) circuit.

In a receiver circuit, a local signal having a frequency close to that of an incoming signal is supplied to a mixer together with the incoming signal, a baseband process is performed in the mixer, and a transmission signal component is thereby extracted. In order to inspect reception characteristics, a signal simulating an incoming signal has to be generated separately, and be input from the immediate vicinity of an antenna.

Thus, a test signal generation circuit having a configuration similar to that of a local signal generation circuit that generates a local signal is installed, and a test signal is input from the immediate vicinity of the antenna by using a coupler or the like. The test signal is received by the receiver circuit, and is subjected to a baseband process. This enables measurement of reception gain, a phase change, and so forth.

The local signal generation circuit and the test signal generation circuit are each typically constituted by a phase locked loop (PLL) circuit, and control output frequencies by changing their respective division ratios. For example, a frequency of a signal generated by a voltage-controlled oscillator (VCO) is divided, a phase of this frequency-divided signal is compared with a phase of a reference signal, and a comparison result is fed back. Thus, feedback is applied so that a frequency of the frequency-divided signal becomes equal to a frequency of the reference signal. When a feedback loop is stabilized, an output frequency of the VCO is stabilized.

A frequency of a test signal has to be different from a frequency of a local signal. Hence, a signal source for test signal generation is installed separately from a local signal source, and frequency dividers installed in these respective signal sources have to be controlled so that their respective division ratios differ from each other. For this reason, the test signal generation circuit results in increases in power consumption and circuit area. In particular, in a frequency divider circuit provided in the test signal generation circuit, the conversion from an output frequency to a reference frequency has to be carried out, high-speed operation is demanded, and a significantly large division ratio is also demanded. Thus, the frequency divider circuit provided in the test signal generation circuit is large in size, and also consumes a large amount of power.

The following is a reference document.

SUMMARY

According to an aspect of the invention, a receiver circuit includes: a local signal generation circuit that generates a local signal; and a test signal generation circuit that generates a test signal having a frequency close to a frequency of the local signal, wherein the test signal generation circuit includes an oscillator that generates the test signal, a mixer that mixes the local signal with an output of the oscillator to generate a low-frequency signal which is a difference signal between the local signal and the output of the oscillator, a phase detector that detects a phase difference between the low-frequency signal output by the mixer and a reference signal, and a filter that extracts a low-frequency component from an output of the phase detector, and controls an oscillation frequency of the oscillator by using an output of the filter.

DESCRIPTION OF EMBODIMENTS

Before a receiver circuit according to each embodiment is described, a typical receiver circuit of a wireless device will be described.

FIG. 1illustrates a basic configuration of a receiver circuit of a wireless device.

The receiver circuit includes an antenna11, a linear amplifier (LA)12, a phase locked loop (PLL) circuit13, a mixer14, an intermediate frequency (IF) amplifier15, and a baseband signal processing circuit16. The antenna11receives a radio signal transmitted from a radio transmitter. Here, the case where a millimeter-wave signal is used as a radio signal will be described as an example. The linear amplifier12amplifies a high-frequency signal from the antenna11. The PLL circuit13generates a local signal for reception operation. The mixer14mixes the high-frequency signal amplified by the linear amplifier12with the local signal to generate an intermediate frequency (IF) signal. The IF amplifier15amplifies the IF signal.

The baseband signal processing circuit16includes an analog-to-digital (A/D) converter circuit17, and a signal processing unit18. The A/D converter circuit17converts the IF signal into a digital signal to generate a baseband signal data. The signal processing unit18performs a digital process on the baseband signal data to acquire incoming data.

The basic configuration of the receiver circuit illustrated inFIG. 1is widely known, and further description thereof is therefore omitted. It is noted that a receiver circuit according to each embodiment to be described below is a circuit used as the receiver circuit of the wireless device or the like illustrated inFIG. 1.

As illustrated inFIG. 1, a local signal generated by the PLL circuit13is supplied to the mixer14for normal reception operation. In order to inspect reception characteristics, a signal simulating an incoming signal has to be generated separately, and be input from the immediate vicinity of the antenna11. For this reason, typically, a test signal generation circuit equivalent to a PLL circuit that generates a local signal is installed, and a test signal is input from the immediate vicinity of an antenna by using a coupler or the like. The test signal is received by a typical receiver circuit, and is subjected to a baseband process, and reception gain and a phase change may thereby be obtained.

FIG. 2illustrates a typical configuration of a receiver circuit in which a test signal generation circuit is installed and which enables reception characteristics inspection.

The receiver circuit illustrated inFIG. 2differs from the receiver circuit illustrated inFIG. 1in that a test signal generation circuit19is provided and a test signal is input from the immediate vicinity of the antenna11, and the receiver circuit illustrated inFIG. 2and the receiver circuit illustrated inFIG. 1are the same in other respects. The test signal generation circuit19is constituted by a PLL circuit. Hereinafter, as illustrated inFIG. 2, the PLL circuit (also referred to as a local signal generation circuit)13that generates a local signal is represented by PLL-LO, and the test signal generation circuit19is represented by PLL-TEST.

FIG. 3illustrates a circuit configuration of the local signal generation circuit (PLL-LO)13and the test signal generation circuit (PLL-TEST)19.

The PLL-LO13includes a voltage-controlled oscillator (VCO)21A, a frequency divider circuit22A, a phase detector (PD)23A, and a filter24A. The VCO21A oscillates at a frequency based on a control voltage, and outputs a local signal having a frequency fLO. The frequency divider circuit22A divides a frequency of the local signal output by the VCO21A by N1, and generates a frequency-divided signal having a frequency of fd1=fLO/N1. A reference signal source20outputs an original reference signal Ref having a frequency fref. The PD23A compares a phase of the original reference signal Ref from the reference signal source20with a phase of the frequency-divided signal, and outputs a phase difference signal. The filter24A extracts a low-frequency component of the phase difference signal to generate a control voltage Vcntl, and outputs the control voltage Vcntl to the VCO21A. In the PLL-LO13, feedback is applied so that the frequency of the frequency-divided signal becomes equal to the frequency of the original reference signal. When a feedback loop is stabilized, the frequency fLOof the local signal, which is an oscillation frequency of the VCO21A, is represented by the following form: fLO=fd1×N1=fref×N1. In the PLL-LO13, a frequency of a local signal to be output is controlled by changing a division ratio.

The PLL-TEST19includes a VCO21B, a frequency divider circuit22B, a PD23B, and a filter24B, and forms a feedback loop similar to that in the PLL-LO13. A frequency fRXof a test signal to be output is represented by the following form: fRX=fd2×N2=fref×N2. The frequency fLOof the local signal and the frequency fRXof the test signal have to be different from each other although they are close to each other, and thus N1=1530.00 is set, whereas N2=1530.02 is set. In an example illustrated inFIG. 3, because of fref=50 MHz and N1=1530.00, fLO=50 MHz×1530=76.500 GHz is obtained. In contrast to this, because of N2=1530.02, fRX=50 MHz×1530.02=76.501 GHz is obtained.

As described above, since a frequency of a test signal has to be different from a frequency of a local signal, a test signal generation circuit is installed separately from a local signal generation circuit, and frequency divider circuits installed in the respective signal generation circuits have to be controlled so that their respective division ratios differ from each other. The local signal generation circuit is a circuit that is large in size and consumes a large amount of power, and thus installation of two such circuits results in increases in power consumption and circuit area. In particular, in a frequency divider circuit, a significantly large division ratio at which the conversion from an output frequency (for example, 80 GHz) to an original reference frequency (for example, 50 MHz) is carried out is demanded, and high-speed operation is also demanded. Thus, the frequency divider circuit is large in size, and consumes a large amount of power.

A receiver circuit according to each embodiment to be described below is used as a receiver circuit of a wireless device, performs self-correction of reception characteristics with a simple circuit configuration, and achieves high performance and high stability with low power consumption.

FIG. 4is a circuit diagram illustrating configurations of a local signal generation circuit (PLL-LO) and a test signal generation circuit (PLL-TEST) in a receiver circuit according to a first embodiment.

The receiver circuit according to the first embodiment is used as a receiver circuit of a wireless device like that illustrated inFIG. 2. The receiver circuit according to the first embodiment includes a reference signal source20, a local signal generation circuit (PLL-LO)30, and a test signal generation circuit (PLL-TEST)40. The reference signal source20outputs an original reference signal Ref having a frequency fref.

The PLL-LO30includes a VCO31, a frequency divider circuit32, a phase detector (PD)33, and a filter34, changes a division ratio N1of the frequency divider circuit32, and thereby changes a frequency fLOof a local signal to be output. In other words, the PLL-LO30forms a feedback loop similar to that in the PLL-LO13illustrated inFIG. 3.

The PLL-TEST40includes a VCO41, a mixer42, a phase detector (PD)43, a filter44, and a reference frequency divider circuit45. The VCO41oscillates at a frequency based on a control voltage Vcntl, and outputs a test signal having a frequency fRX. The mixer42mixes the local signal output by the VCO31of the PLL-LO30with the test signal to generate a low-frequency signal IFd. A frequency fd2of the low-frequency signal IFd is an absolute value of a difference between the frequency fRXof the test signal and the frequency fLOof the local signal. That is, the frequency fd2is represented by the following form: fd2=|fRX−fLO|. Assuming fRX=76.501 GHz and fLO=76.500 GHz, fd2=1 MHz is obtained.

The reference frequency divider circuit45divides a frequency of a frequency-divided signal output by the frequency divider circuit32of the PLL-LO30so as to result in a frequency close to the frequency fd2of the low-frequency signal IFd further to generate a reference signal Refd. The frequency of the frequency-divided signal output by the frequency divider circuit32here is 50 MHz which is equal to the frequency of the original reference signal, and assuming that a division ratio P of the reference frequency divider circuit45is 50.00, a frequency foffsetof the reference signal Refd is 1 MHz. Hence, the frequency foffsetof the reference signal Refd is a frequency close to the frequency fd2of the low-frequency signal IFd.

The PD43compares a phase of the reference signal Refd with a phase of the low-frequency signal IFd, and generates a phase difference signal, which is a comparison result. The filter44extracts a low-frequency component from the phase difference signal to generate a control voltage Vcntl, and supplies the control voltage Vcntl to the VCO41.

In the PLL-TEST40, the VCO41, the mixer42, the PD43, and the filter44constitute a PLL circuit in which the phase of the low-frequency signal IFd is compared with the phase of the reference signal Refd and a comparison result is fed back. In this PLL circuit, feedback is applied so that the frequency fd2of the low-frequency signal IFd becomes equal to the frequency foffsetof the reference signal Refd. When a feedback loop is stabilized, the frequency fRXof the test signal output by the VCO41becomes equal to a frequency obtained by offsetting the frequency fLOof the local signal by the amount of foffset. That is, the frequency fRXis represented by the following form: fRX=fLO+foffset. In the PLL-TEST40, a frequency of a test signal to be output is controlled by changing a division ratio of the reference frequency divider circuit45.

FIG. 5is a circuit diagram illustrating an example of each of the VCO31of the PLL-LO30and the VCO41of the PLL-TEST40. The voltage-controlled oscillator includes a series circuit including an inductor L1and a transistor TR1, and a series circuit including an inductor L2and a transistor TR2, and two series circuits form a differential pair. Sources of the transistors TR1and TR2are connected to a common ground, and terminals of the inductors L1and L2are connected to a common VCC. Capacitors C1and C2are connected in series between a connection node (a drain of the transistor TR1) of the inductor L1and the transistor TR1and a connection node (a drain of the transistor TR2) of the inductor L2and the transistor TR2, and a control voltage Vcntl is supplied to a connection node of the capacitors C1and C2. Oscillation signals are output from the connection node of the inductor L1and the transistor TR1and the connection node of the inductor L2and the transistor TR2.

The VCO circuit illustrated inFIG. 5is widely known, and further description thereof is therefore omitted. It is noted that the VCO circuit illustrated inFIG. 5is an example, and the VCOs used in each embodiment are not limited to this.

FIG. 6is a block diagram illustrating an example of the frequency divider circuit32of the PLL-LO30.

The frequency divider circuit32is called a pulse-swallow programmable frequency divider, and includes a dual-modulus prescaler51, a pulse counter52, and a swallow counter53. The dual-modulus prescaler51is a circuit that generates and outputs a signal having a frequency of 1/N or 1/(N+1) of a frequency of an input signal. Which of frequencies of 1/N and 1/(N+1) of the input signal frequency a signal to be output has is controlled by an output from the swallow counter53.

The pulse counter52is a programmable counter that counts pulses of an input signal received from the dual-modulus prescaler51, and a count number P is externally set. When the count of the set count number P is reached, the pulse counter52changes an output signal (OUT). When the pulse counter52completes the count of the count number P, the pulse counter52automatically starts the count of a subsequent count number P.

The swallow counter53is a programmable counter that counts pulses of an input signal received from the dual-modulus prescaler51, and a count number S is externally set. When the swallow counter53completes the count of the count number S, the swallow counter53stops count operation, and the output is kept low. The swallow counter53resumes (reloads) count operation in accordance with a change in the output signal of the pulse counter52.

A total division ratio Ntotobtained in the frequency divider circuit32illustrated inFIG. 6is represented by the following form: Ntot=N·P+S. Thus, in the frequency divider circuit32, a desired division ratio is obtained by appropriately setting N, P, and S.

For example, assume that N=16 and N+1=17 are set in the dual-modulus prescaler51, the pulse counter52is a 7-bit programmable counter, and the swallow counter53is a 4-bit programmable counter. Assuming that the count number P set in the pulse counter52is represented by P=96 and the count number S set in the swallow counter53is represented by S=4, the total division ratio Ntot=16·96+4=1540 is obtained. When the frequency frefof the original reference signal Ref is represented by fref=50 MHz, fLO=Ntot·fref=1540×50 MHz=77.000 GHz is obtained.

The frequency divider circuit illustrated inFIG. 6is widely known, and further description thereof is therefore omitted. It is noted that the frequency divider circuit illustrated inFIG. 6is an example, and the frequency divider circuit used in each embodiment is not limited to this.

FIGS. 7A to 7Care circuit diagrams of other circuit components,FIG. 7Ais a circuit diagram of each of the filters34and44,FIG. 7Bis a circuit diagram of each of the phase detectors (PDs)33and43, andFIG. 7Cis a circuit diagram of the mixer42.

The filter illustrated inFIG. 7Ais a third-order loop filter including combinations of resistors and capacitors.FIG. 7Billustrates an exclusive OR (XOR) logic circuit that is generally widely used as a simple PD, a reference signal (or an original reference signal) is input to an input Ref which is one input of the XOR logic circuit, and a low-frequency signal is input to an input FD_OUT which is the other input of the XOR logic circuit.FIG. 7Cillustrates a resistive mixer circuit in which a transistor which does not supply power is used as a nonlinear resistor. When a local signal LO and a test signal RF are respectively supplied to a gate of the transistor and one controlled terminal, a low-frequency signal IF subjected to frequency conversion by the nonlinearity of the resistor is obtained from the other controlled terminal.

The circuits illustrated inFIGS. 7A to 7Care widely known, and further description thereof is therefore omitted. It is noted that the circuits illustrated inFIGS. 7A to 7Care examples, and the filters, the phase detectors (PDs), and the mixer which are used in each embodiment are not limited to these.

FIG. 8illustrates an exemplary circuit of the reference frequency divider circuit45.

The reference frequency divider circuit45illustrated inFIG. 8is a frequency divider circuit constituted by M stages of divide-by-two frequency dividers60-1to60-M which are connected in series. For example, connection of six stages results in a division ratio of 64, and thus a frequency of 50 MHz of an input is divided down to a frequency of 0.78 MHz. A signal to be input to the reference frequency divider circuit45is a signal of 50 MHz, and the reference frequency divider circuit45is a lower-speed circuit than the frequency divider circuit32, and also includes a small number of stages.

The frequency divider circuit illustrated inFIG. 8is widely known, and further description thereof is therefore omitted. It is noted that the frequency divider circuit illustrated inFIG. 8is an example, and the reference frequency divider circuit45used in each embodiment is not limited to this.

As described above, in contrast to the typical circuit illustrated inFIG. 3, the test signal generation circuit (PLL-TEST)40in the receiver circuit according to the first embodiment does not include a high-speed frequency divider circuit, and newly includes the mixer42and the reference frequency divider circuit45. Thus, the high-speed frequency divider circuit22B used in the circuit illustrated inFIG. 3does not have to be included. The mixer42is a circuit whose power consumption is zero if a resistive mixer is used, and the reference frequency divider circuit45is a low-speed frequency divider circuit whose operation speed is such a low speed that the conversion from 50 MHz to 1 MHz is carried out. Thus, power consumption in this case is smaller than that in the case where the high-speed frequency divider circuit is provided.

FIG. 9illustrates constituent ratios of power consumed by each component in the receiver circuit inFIG. 3and the receiver circuit according to the first embodiment inFIG. 4.

In the receiver circuit illustrated inFIG. 3, the total of the power consumption of the VCO21A of the PLL-LO13and the VCO21B of the PLL-TEST19is 47.3 mW. The total of the power consumption of the frequency divider circuit22A of the PLL-LO13and the frequency divider circuit22B of the PLL-TEST19is 234 mW. The total of the power consumption of the PD23A of the PLL-LO13and the PD23B of the PLL-TEST19is 3.8 mW. The total of the power consumption of the reference signal source20is 11.4 mW. Thus, the frequency divider circuits22A and22B make up a sizable proportion of the sum total of power consumption.

In contrast to this, in the receiver circuit according to the first embodiment, the power consumption of the VCOs31and41, the power consumption of the PDs33and43, and the power consumption of the reference signal source20are respectively 47.3 mW, 3.8 mW, and 11.4 mW, which are the same as those in the receiver circuit illustrated inFIG. 3. The power consumption of the frequency divider circuit32is 117 mW, which is equal to half the total of the power consumption of the frequency divider circuits22A and22B illustrated inFIG. 3because no frequency divider circuit is provided in the PLL-TEST40. On the other hand, the power consumptions of the mixer42and the reference frequency divider circuit45which are newly included in the PLL-TEST40according to the first embodiment are respectively 0 mW and 1.5 mW. Hence, the sum total of power consumption in the circuit illustrated inFIG. 3is 296.5 mW, whereas the sum total of power consumption in the circuit according to the first embodiment is 181 mW, and thus the power consumption is significantly reduced.

FIG. 10is a circuit diagram illustrating configurations of a local signal generation circuit (PLL-LO) and a test signal generation circuit (PLL-TEST) in a receiver circuit according to a second embodiment.

The receiver circuit according to the second embodiment is used as a receiver circuit of a wireless device like that illustrated inFIG. 2. The receiver circuit according to the second embodiment has the same configuration as that of the first embodiment except that the reference frequency divider circuit45divides a frequency frefof an original reference signal Ref output by the reference signal source20.

As described above, a frequency-divided signal output by the frequency divider circuit32of the PLL-LO30has a frequency which is equal to the frequency frefof the original reference signal Ref output by the reference signal source20, and, when a feedback loop is stabilized, their phases also match each other. Hence, the original reference signal Ref may be used in place of a frequency-divided signal.

The receiver circuit according to the second embodiment exhibits an effect similar to that in the first embodiment.

FIG. 11is a circuit diagram illustrating configurations of a local signal generation circuit (PLL-LO) and a test signal generation circuit (PLL-TEST) in a receiver circuit according to a third embodiment.

The receiver circuit according to the third embodiment has the same configuration as the receiver circuit according to the first embodiment except that an initialization circuit is provided at an output of the filter44of the test signal generation circuit (PLL-TEST)40.

In the first and second embodiments, a frequency of a test signal is able to be offset with respect to a frequency of a local signal, that is, an absolute value of a frequency difference between the local signal and the test signal has to be foffset. For this reason, the test signal may be stabilized at both a frequency on a high-frequency side and a frequency on a low-frequency side with respect to the frequency of the local signal. In other words, which side an output frequency of the test signal is stabilized on depends on a circuit initial state, and thus there is uncertainty.

In the third embodiment, an output from the filter44, that is, a control voltage for the VCO41is set at a level on one potential side by the initialization circuit, and its state is changed to a stable state, thereby resulting in stabilization in one of low-frequency and high-frequency states.

InFIG. 11, the initialization circuit connects a signal line connecting the output of the filter44to an input of the VCO41to a high-potential power line via a resistor RS and a switch SW. When a predetermined time period has elapsed since the start of operation, the switch SW is put into an open state. Thus, in an initial state, a control voltage is set at a level on a high-potential side, an oscillation frequency of the VCO41is an upper limit frequency, feedback control results in a frequency fRXof a test signal in a stable state represented by fRX=fLO+foffset, and the frequency of the test signal is located on a high-frequency side with respect to a frequency of a local signal.

In an example illustrated inFIG. 11, although the initialization circuit is constituted by the resistor RS and the switch SW, if the resistance of the resistor RS is increased, the switch SW does not have to be provided. Subsequently, a feedback loop moves toward stabilization, and, since the feedback loop moves toward stabilization from the high-frequency side, stability is achieved at a frequency offset to the high-frequency side with respect to the frequency of the local signal.

Additionally, inFIG. 11, if the signal line connecting the output of the filter44to the input of the VCO41is connected to a low-potential power line via the resistor RS and the switch SW, a frequency of a test signal is located on a low-frequency side with respect to a frequency of a local signal.

Furthermore, to enable switching between a high-frequency side and a low-frequency side on which a frequency of a test signal is set with respect to a frequency of a local signal, the signal line is connected to both a high-potential power line and a low-potential power line via two sets of the resistor RS and the switch SW.