An analog to digital converter by using an exponential-logarithmic model includes an exponential circuit which acquires an analog input voltage and generates an analog output voltage that is an exponential function of the input voltage. A positive feedback circuit that succeeds the exponential circuit exhibits a natural logarithmic characteristic. A comparator is connected to the positive feedback circuit to compare an output voltage of the positive feedback circuit with a reference voltage. Via the exponential-logarithmic conversion technique, the time interval or pulse produced by the positive feedback circuit is a linear function of the magnitude of the input voltage. Based on the comparator output, a counter is employed to translate the analog input signal to its digital representation.

CROSS-REFERENCE TO RELATED APPLICATION

This present application claims priority to TAIWAN Patent Application Serial Number 100101021, filed on Jan. 11, 2011, which is herein incorporated by reference.

TECHNICAL FIELD

This invention relates to a new analog-to-digital converter architecture and more particularly to an analog-to-digital converter which employs an exponential-logarithmic model to convert a weak analog signal to a digital signal.

DESCRIPTION OF THE RELATED ART

Digital signal processing systems have been widely used in applications which include iPhones, cell phones, smart phones and other electronic devices. Analog-to-digital converters are essential elements in many digital signal processing systems which incorporate digital signal processors and analog-to-digital converters as analog-to-digital converters are utilized convert analog signals to digital signals which can be further processed by digital signal processors.

Some analog-to-digital conversion techniques are widely used. A dual-slope integrating ADC utilizes an integrator to convert an analog input voltage into a digital value. As the input voltage is applied to the input of the integrator to charge the integrator for a fixed interval of time, the charging time period is measured. Then a reference voltage of opposite polarity is applied to the integrator input to discharge the integrator, and the discharging time period is measured. The timing relationship for a dual-slope integrating ADC is defined by equation 1.

VinVref=TChargeTDischarge(1)
Integrating ADCs are useful in applications that have low input bandwidths and operate at slow speeds.

A successive approximation ADC is also a popular analog-to-digital converter architecture. A successive approximation ADC employs a comparator to compare the input voltage with the output of a digital-to-analog converter and achieves analog-to-digital conversion through binary search. One of the main advantages of SAR converters is low power consumption.

Compared to the present invention, dual-slope integrating ADCs and SAR ADCs necessitate more capacitance to achieve the same resolution, thus increasing chip areas. The present invention provides a new analog-to-digital conversion technique that achieves analog-to-digital conversion and reduction of chip area by using an exponential-logarithmic model.

SUMMARY

To reduce the capacitances required by the prior arts and thus reduce chip areas, the present invention provides a new analog-to-digital converter architecture by using an exponential-logarithmic model to achieve analog-to-digital conversion. The present invention employs an exponential circuit and a logarithmic circuit which is a positive feedback circuit to achieve high-resolution analog-to-digital conversion.

The new analog-to-digital converter comprises an exponential circuit, a positive feedback circuit, a comparator, a logic control unit and a counter. An input voltage is applied to the input of the exponential circuit which produces a voltage that is an exponential function of the input voltage. The positive feedback circuit succeeds the output of the exponential circuit and generates a voltage that is a linear function of the input voltage. The comparator connected to the positive feedback circuit compares the rising output voltage of the positive feedback circuit with a reference voltage and changes its output state when the output voltage of the positive feedback circuit reaches the reference voltage. The counter measures the time interval or pulse produced by the comparator and generates a digital representation that corresponds to the input voltage.

DETAILED DESCRIPTION

The invention is more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying figures; however, those skilled in the art will appreciate that these examples are not intended to limit the scope of the present invention, and various changes and modifications are possible within the sprite and scope of the present invention.

Circumventing the difficulties imposed by the prior arts, the present invention relates to an exponential-logarithmic ADC implemented by an exponential-logarithmic model that converts an analog input voltage into a time-domain interval or pulse and a counter that translates the time interval into a digital output value. The exponential-logarithmic analog-to-digital converter of the present invention necessitates only 6 bits to realize a 1mV-LSB, therefore achieving an excellent resolution of the input signals.

FIG. 1illustrates a conceptual block diagram of the exponential-logarithmic analog-to-digital converter. As shown inFIG. 1, the analog-to-digital converter comprises an exponential circuit101, a logarithmic circuit102, and a counter104. Initially, a sampled and held analog input voltage Vi100is applied to the input of the exponential circuit101. The exponential circuit101produces an analog output voltage Y which is an exponential function of the analog input voltage100. The logarithmic circuit102that succeeds the exponential circuit101acquires the output voltage Y of the exponential circuit101and produces a time interval or pulse that exhibits a logarithmic characteristic. The exponential-logarithmic model comprising the exponential circuit101and the logarithmic circuit102produces a time interval which varies linearly with the input voltage. Time to digital conversion can thus be performed by the counter104to correlate the analog input voltage100with a digital output signal105.

FIG. 2illustrates an example of a functional block diagram of the exponential-logarithmic ADC. As shown inFIG. 2, the exponential-logarithmic ADC of the present invention includes an exponential circuit101, a positive feedback circuit102, a comparator103, a control logic circuit110and a counter104. The positive feedback circuit102is connected to the exponential circuit101and the comparator103, and the control logic circuit110is connected to the comparator103and the counter104. In this case, the positive feedback circuit102is implemented by a latch shown inFIG. 3. Initially, an input voltage is sampled onto a sample and hold circuit. Next, the input voltage Visis applied to the input of the exponential circuit101which then produces to an output voltage that is an exponential function of the input voltage100. Subsequently, one terminal node of the positive feedback circuit102is initialized to a set point voltage, and the other terminal node of the positive feedback circuit102is initialized to the sum of the set point voltage and the output voltage of the exponential circuit. Based on the exponential characteristic of the exponential circuit101and the natural logarithmic characteristic exhibited by the positive feedback circuit102, the integration of the exponential circuit101and the positive feedback circuit102shown inFIG. 2allows the sense time of the positive feedback circuit102to vary linearly with the magnitude of the input voltage Vis. Consequently, time to digital conversion can be performed by the counter104to correlate the analog input signal with a digital output signal.

The positive feedback circuit102will force the voltage at the terminal node that received a greater initial voltage than the other terminal node to rise toward the positive supply voltage. Next, the comparator103compares this ascending voltage with a reference voltage. When the ascending voltage exceeds the reference voltage, the comparator103generates a signal which activates the control logic circuit110to latch the output (D1, D2, D3. . . DN-1) of the counter104. The counter104determines the number of clock cycles necessary for the time interval between the initialization of the positive feedback circuit102and the instant the ascending output voltage of the positive feedback circuit102reaches a reference potential. The number of clock cycles corresponds to the analog input value; therefore, the output of the counter104represents the digital codeword of the input voltage Vis.

FIG. 3illustrates an equivalent circuit of a positive feedback circuit according to the present invention.FIG. 3shows a positive feedback circuit102which comprises two inverting amplifiers102aand102bconnected in a positive-feedback loop as a latch with a capacitor CLconnected to each of the two terminal nodes of the inverting amplifiers102aand102b, respectively. The positive feedback circuit102amplifies the voltage between its two nodes and drives the voltages at the terminal nodes toward positive supply voltage (Vdd) and ground, respectively. The amplifiers in the regenerative circuit102drive capacitive loads and provide gain GM. The changing voltage Vxand Vyacross the capacitor CLcan be expressed as

The difference between the output of the regenerative circuit102can be written as

Under the assumption that CLand GMare constant and independent of voltage and time, integration of GM/GLfrom 0 to t and integration of 1/Vxyfrom Vxy(0) to Vxy(t) are performed.

The integrations yield
Vxy(t)=Vxy(0)et/τρχ(6)
where τrcis defined as CL/GM. The sense time which is time required for the Vrnodes of the regenerative circuit102to achieve a certain potential, is a logarithm function of the voltage difference between the two nodes:

ts=τrc⁢ln⁡[Vxy⁡(t)Vxy⁡(0)](7)
and can be described as
ts=τ0−τrcln [Vx(0)−Vy(0)]  (8)
wherein τ0is constant and defined as τrcln [Vxy(t)]

FIG. 4illustrates an example of a functional block diagram of a positive feedback-based analog to digital converter according to the present invention. As shown inFIG. 4, the exponential-logarithmic analog to digital converter of the present invention comprises an exponential circuit101, a positive feedback circuit102, a comparator103, a control logic circuit110and a digital counting circuit104. Similarly, the positive feedback circuit102is connected to the exponential circuit101and the comparator103, and the control logic circuit110is connected to the comparator103and the digital counting circuit104. For example, the positive feedback circuit102is a sense amplifier with controlled switches18,19,20and21, transistors2,13,14,15,16, and17and two identical capacitors22and23. Transistors12,13,14are PMOS transistors, and transistors15,16,17are NMOS transistors. The gate of PMOS transistor13is connected to gate of NMOS transistor15, and drain of PMOS transistor13is connected to drain of NMOS transistor15to implement an inverter. Similarly, the other inverter is constructed by PMOS transistor13and NMOS transistor15. Source of PMOS transistor12is connected to a reference voltage (Vdd), and gate of PMOS transistor12is connected to a gate voltage (Va). Source of NMOS transistor17is connected to ground, and gate of NMOS transistor17is connected to a gate voltage (Vb). The sense amplifier is used to implement a logarithmic circuit and comprises two inverting amplifiers connected in a positive-feedback loop with a capacitor CLconnected to each of the two terminal nodes of the sense amplifier, respectively, shown inFIG. 3. Capacitance of the capacitor CLcan be adjusted depending on the actual or design requirement. Reset switches20,21and Phi2switches18,19are controlled by non-overlapping clock waveforms, Reset and Phi2, respectively. The exponential circuit101comprises an operational amplifier10, a resistor Rfand an NMOS transistor11operating in the sub-threshold region. Resistor Rfis connected between the negative input terminal (Vin) and output terminal (Vo) of the operational amplifier10. Drain of NMOS transistor11is connected to the negative input terminal of the operational amplifier10. Second input terminal (Vip) and the output terminal (Vo) of the operational amplifier10is connected to switches18and19of the positive feedback circuit102, respectively. The comparator103comprises transistors (30,31,32,33,34,35,36), wherein the transistors (30,31,32) are PMOS transistors, and transistors (34,35,36) are NMOS transistors. It should be noted that the gate of NMOS transistor33is connected to a reference voltage (Vref), and the gate of NMOS transistor34is connected to the output terminal of the sense amplifier102. The gate of PMOS transistor30is connected to drain of PMOS transistor30. The gate of NMOS transistors35and36is connected to a gate voltage (Vc), and source of NMOS transistors35and36is connected to ground. The drain of PMOS transistor32is connected to drain of NMOS transistor36. The drain of PMOS transistor31is connected to the drain of NMOS transistor34.

Initially, both terminal nodes of the sense amplifier102are charged to the set point voltage, via the Reset signal, and equilibrium of the sense amplifier102is maintained. Next, as the reset switches20,21turn off, voltages are applied to the two terminal nodes by turning on the Phi2switches18,19. During the Phi2phase period, the right terminal of the sense amplifier is initialized to a greater voltage Vr(0) than the voltage at the left terminal Vl(0). In this charging phase of the sense amplifier102, the differential voltage between the two terminals of the sense amplifier102is latched. After the Phi2switches open, the difference between the voltages Vr(0) and Vl(0) is amplified by the sense amplifier102. Because Vris higher than Vl, the amplification inherent to the positive feedback of the sense amplifier102causes the voltage at the Vrnode to increase toward the positive supply voltage and the voltage at the Vlnode to decrease toward ground.

The time required for the sense amplifier102to reach a specified voltage separation is dependent on the initial voltage differential, the resistance and capacitance of the sense amplifier102. The sense time can be expressed as
ts(V)=τ0−τrcln [Vr(0)−Vl(0)]  (9)
where τ0is a constant and τrcis defined as CL/GM. As equation (9) indicates, the sense time of the sense amplifier102is a natural logarithmic function of the difference between the initial voltage at the left terminal node and the initial voltage at the right terminal node.FIG. 5shows the simulation result of the time required for the positive feedback circuit to produce a predetermined output voltage versus the initial voltage difference between the two terminals of the positive feedback circuit. A logarithmic equation is fitted to the simulated data, which demonstrate a logarithmic characteristic.

In order for the sense time of the sense amplifier102to vary linearly as the amplitude of the input voltage, an NMOS transistor11operating in the sub-threshold region is configured as the input to an operational amplifier10with the output Voof the operational amplifier10connected to Vrand the non-inverting input Vipof the operational amplifier connected to Vl. This configuration replaces the difference between Vr(0) and Vl(0) in equation (9) with an exponential function. The sub-threshold NMOS transistor11produces a drain-source current that is an exponential function of the gate-source voltage and can be expressed as

I=I0⁢ⅇ(Vgsη⁢⁢VT)(10)
where VT=kT/q is the thermal voltage, η is nonlinear parameter, I0is process parameter associated with transistor area, and Vgsis gate-source voltage, which is the input voltage of the analog-to-digital converter, and I0is the zero-bias current.

During the charging phase of the sense amplifier102, the current supplied by the sub-threshold NMOS transistor11flows through the feedback resistor Rfand is converted to a voltage expressed as IRf. The output voltage of the operating amplifier10can thus be described as Vout=IRf+Vip. Therefore, the right node (Vr) of the sense amplifier102is charged to the output voltage (Vout=IRf+Vip) of the operational amplifier10; the left node (Vl) of the sense amplifier102is charged to the voltage (Vip) at the positive terminal of the operational amplifier10. The initial voltage differential of the positive feedback amplifier can be expressed as

The sense time of the sense amplifier102can thus be obtained by combining equations 10 and 11

Via this exponential-logarithmic conversion technique, the produced time interval is a linear function of the input voltage Vgas shown in equation (12) and as illustrated in the simulation result inFIG. 6where the X axis indicates the input voltage which is applied to the input of the exponential circuit101, and the Y axis indicates the time required for the voltage Vr at the right node of the positive feedback circuit102to rise to a specified voltage.

Subsequently, the reference voltage, Vref, is applied to the negative terminal of the comparator103, and the signal Vrwhich is rising toward the positive rail, is applied to the positive terminal of the comparator103. The output of the comparator103is sent to the control logic circuit110. As the rising signal Vrexceeds Vref, the output of the comparator103changes state to disable the counter104, and the digital codeword corresponding to the analog signal is latched. After the digital codeword is read out, the counter104is reset by using digital circuitry.

FIG. 7shows the simulation results in different process corners and indicates the linear relationships between the time intervals and the input voltages.

Table 1 indicates the 6-bit digital output codes corresponding to the input voltages in the TT process corner. The present invention merely requires 6 bits to resolve an LSB of 1 mV. The present invention can be used for neural recording since neural signals are weak and have low frequencies, and small chip areas can facilitate multi-site neural recording.