Efficient method of data transfer between register files and memories

A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit. A method of swapping data between two storage circuits is also described.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to computer memory systems, and more particularly, to methods and systems for moving data between two memory locations.

2. Description of the Related Art

Computer memory systems are very common and are used in many different configurations. A typical block of memory includes a block of memory cells and input and output circuitry that allows the block of memory cells to communicate with a device or system that is external to the block of memory.

FIG. 1Ashows a typical microprocessor100. The microprocessor100includes a first block of memory110includes a block of memory cells102and a block of input and output (I/O) circuitry104. Each one of the memory cells102includes a storage circuit112(e.g., cross-coupled inverters), one or more keeper circuits114, and pre-charge circuits116. The storage circuit112stores a selected voltage level that corresponds to a logic value of 1 or 0. The keeper circuits114assist the storage circuit112in maintaining the selected voltage level. The pre-charge circuits116pre-charge the bit lines that are used to read and/or write the voltage level stored in the storage circuit112.

Typically, the storage circuit112stores one of two voltage levels. Typically a low voltage level corresponds to a logical “0” value and a high voltage level corresponds to a logical “1” value. The actual voltage of the high voltage level and the low voltage level is a function of the design (i.e., type) of the storage circuit112. By way of example, in a first-type of storage circuit112a voltage lower than 0.3 volts could be considered a low voltage level and therefore a logical 0. Similarly, a voltage higher than 0.6 volts could be considered a high voltage level and therefore a logical 1 in the first-type storage circuit112. Conversely, in a second-type storage circuit112a voltage greater than 0.3 volts could be considered a high voltage level and therefore a logical 1. Similarly, the second-type storage circuit112would require a low voltage level of less than about 0.1 or 0.2 to indicate low voltage level that would correspond to a logical 0.

The block of I/O circuitry104includes a sense amplifier122on the read line and a write amplifier124on a write line. The sense amplifier122detects the voltage level of the logic stored in the storage circuit112and amplifies the detected the voltage level. The sense amplifier122can then communicate the voltage level stored in the storage circuit112to an external device such as a bus130. By way of example, the sense amplifier122can detect a voltage level that corresponds to a logical 1 (e.g., greater than about 0.6 volts) stored in the second-type storage circuit112. The circuits external to the first block of memory110may be designed to recognize voltage level of about 1 volt to represent a logical 1. Therefore, the sense amplifier122amplifies the detected 0.6 volts to about 1 volt so as to accurately transmit the data value stored in the second-type storage circuit112.

Similarly, the write amplifier124detects and amplifies a voltage level on an external device (e.g., bus130) and communicates the amplified voltage level to the storage circuit112. By way of example, a logical voltage of about 0.3 volts is detected on the bus130by the write amplifier124. The write amplifier124must accurately discriminate whether the detected 0.3 volts represents a logical one or a logical zero. The write amplifier124then modifies (e.g., amplify or reduce) the detected 0.3 volt logic value to either a logical 1 voltage level or a logical 0 voltage level that can be accurately stored in the storage circuit112.

The microprocessor100can also include a second block of memory140and a processor core150. The second block of memory140and the processor core150can also be coupled to the bus130. The second block of memory140includes a second storage circuit142. As the processor core150performs logical operations, it is often necessary to swap the data from the first block of memory110to the second block of memory140via the bus130.

FIG. 1Bis a flowchart diagram of the method operations160of performing the data swap operation form the first memory110to the second memory140. In an operation162, the sense amplifier122must detect the data voltage level stored in the storage circuit112. In an operation164, the sense amplifier122amplifies the detected data voltage level. In an operation166, the amplified data voltage level is communicated across the bus130to the second block of memory140. In an operation168, the write amplifier124detects the communicated voltage level on the bus130. In an operation170, the write amplifier124amplifies the detected voltage level. In an operation172, the amplified voltage level is stored in the second storage circuit142.

The method operations160of performing the data swap is a very complex and time consuming process as the data voltage level must be amplified and detected multiple times and communicated a relatively long distance across the bus130. This time consuming process slows down the effective speed of the processor core150. Further, the sense amplifiers122and write amplifiers124are relatively large devices (e.g., typically more than 50 or even 100 times the device sizes of the devices that form the storage circuits112and142) and thereby consume excess space on the semiconductor substrate upon which the microprocessor100is formed.

Typically, the sense amplifier122, the write amplifier124, the keeper circuits114and the pre-charge circuits116have substantially larger physical size than the devices (e.g., transistors, inverters, PMOS, NMOS, etc.) that form the storage circuit112. By way of example, the devices that form the storage circuit112can have a width of about 0.5 or 0.3 micron or even smaller. In comparison the keeper circuits114and the pre-charge circuits116can have a width of about 40–50 micron and the sense amplifier122, the write amplifier124can have a width of about 100 micron or greater. These large device sizes122and124exacerbate the problem by causing the bus130(or other interconnecting circuits and conductive lines) to be larger and longer and the memory blocks110and140further apart and further from the processor core150. These large device sizes122and124further limit the number of memory blocks that can be included on the microprocessor100.

In view of the foregoing, there is a need for a more efficient system and method for moving data between multiple memory blocks.

SUMMARY OF THE INVENTION

Broadly speaking, the present invention fills these needs by providing a more compact memory system and a more efficient method of transferring data between cells in the memory system. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, computer readable media, or a device. Several inventive embodiments of the present invention are described below.

One embodiment provides a memory system that includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit through at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit.

The memory system can be included in a microprocessor. The at least one pass gate can include at least one save pass gate and at least one restore pass gate. The at least one restore pass gate has a device size substantially similar to a device size of each one of a set of devices in the active storage circuit and the at least one base storage circuit and wherein the at least one save pass gate has a device size sufficient to overcome a parasitic read operation.

The memory system can also include a pre-charge circuit coupled to the at least one bit line. The memory system can also include a keeper circuit coupled to the at least one bit line. The memory system can also include a timing and control circuit coupled to the at least one bit line.

The at least one base storage circuit can include multiple base storage circuits and wherein each one of the multiple base storage circuits corresponds to a processing thread in a multi-thread processor.

Another embodiment provides a memory system. The memory system including an active storage circuit, multiple base storage circuits, a first bit line and a second bit line. The active storage circuit having a first active node and a second active node. Each one of the base storage circuits including a corresponding first base node and a corresponding second base node. The first bit line is coupled between the first active node and each one of the first base nodes. The first bit line including a first save pass gate and a first save driver coupled in series to the first node and a first restore pass gate and a first restore driver coupled in series to the first node. The second bit line is coupled between the second active node and each one of the of second base nodes. The second bit line including a second save pass gate and a second save driver coupled in series to the second node and a second restore pass gate and a second restore driver coupled in series to the second node. The first save pass gate, the first save driver, the first restore pass gate, the first restore driver, the second save pass gate, second save driver, the second restore pass gate and the second restore driver have a device size substantially similar to a device size of each one of a multiple of devices in the active storage circuit and the multiple base storage circuits.

Another embodiment provides a method of swapping data between two storage circuits. The method includes activating a first pass gate between a first storage circuit and a first bit line and activating a second pass gate between a second storage circuit and the first bit line. The data stored in the first storage circuit can be driven to the first bit line and the data on the first bit line can be stored in the second storage circuit.

Driving the data stored in the first storage circuit to the first bit line can include amplifying the data stored in the first storage circuit in an amplification circuit having device sizes substantially equal to the devices in the first storage circuit and the second storage circuit. Driving the data stored in the first storage circuit to the first bit line can include amplifying the data stored in the first storage circuit in an amplification circuit having device sizes sufficient to overcome a parasitic read operation.

The first pass gate can be a save pass gate and wherein the save pass gate is activated at least a first time delay before the second pass gate is activated. The first time delay can be equal to about two gate delays. The first time delay can be sufficient to allow a sufficient voltage differential to be developed on the first bit line.

The method can also include applying a keeper circuit to the first bit line. The first storage circuit can be an active storage circuit and the second storage circuit can be a base storage circuit. The base storage circuit includes multiple base storage circuits and wherein each one of the multiple base storage circuits corresponds to a processing thread in a multi-thread processor.

Yet another embodiment provides a method of performing a data swap in a multi-threaded microprocessor. The method includes activating a first active pass gate between a first node of an active storage circuit and a first bit line and activating a second active pass gate between a second node of the active storage circuit and a second bit line. The method also includes activating a first base pass gate between a first node of a base storage circuit and the first bit line and activating a second base pass gate between a second node of a base storage circuit and the second bit line. The data can be stored in the active storage circuit to the first bit line and the second bit line. The data on the first bit line and the second bit line can be stored in the base storage circuit.

The base storage circuit can be one of multiple base storage circuits coupled to the first bit line and the second bit line and wherein each one of the multiple base storage circuits corresponds to one of several processing threads. Activating the first base pass gate and activating the second base pass gate can include receiving a thread select control signal that corresponds to a selected process thread and a corresponding base storage circuit.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Several exemplary embodiments for a more compact memory system and a more efficient method of transferring data between cells in the memory system will now be described. It will be apparent to those skilled in the art that the present invention may be practiced without some or all of the specific details set forth herein.

As described above it is often desirable to transfer data between two memory locations. By way of example, a processor may be processing a first set of data to a first interim result using a portion of active memory (e.g., an active register). The processor may be unable to fully process the first set of data to achieve a final result because the processor needs a second set of data that is not yet available. As a result, the first interim results and possibly even the first set of data may be transferred from the active register to a second storage location. The processor can then transfer other data to the active register and process the other data to determine the second set of data. Then the second set of data, the first interim results and/or the first set of data can be stored in the active register of the memory and processed to determine the final results.

FIG. 2is a block diagram of a multi-thread processor200, in accordance with one embodiment of the present invention. The multi-thread processor200includes a processor core150that is coupled to a bus130. An active register210includes multiple active cells210A–210nthat represent memory locations R0through Rn in the register. Each active cell210A–210nis coupled to the bus130by a respective I/O circuit212A-212n.

The multi-thread processor200includes multiple processing threads: Thread0(T0)220, Thread1(T1)222through Thread n (Tn)224. The multi-thread processor may have four or eight or even more processing threads. Each of the processing threads220,222and224includes a corresponding set of base cells220A–220n,222A–222nand224A–224n. Each active cell210A–210nis also coupled directly to one base cell in each of the processing threads220,222and224. By way of example, active cell210B is coupled directly to base cells220B,222B and224B in each of the processing threads220,222and224.

FIG. 3is a flowchart of the method operations300of the operations of the multi-thread processor200, in accordance with one embodiment of the present invention. The multi-thread processor switches between processing threads to perform the processing. Typically, the multi-thread processor will process a first thread until the first thread stalls due to needing data that is not yet available. The multi-thread processor can also interrupt processing of the first thread such as due to a higher priority processing request by a second thread. By way of example, in an operation305, a first set of data is retrieved from the active register210for processing. The processing can be in a processor (e.g., a multi-thread processor200).

In an operation310, the first set of data is processed until processing is stopped in an operation315. The processing the first set of data may be stopped due to an interrupt or a stall or for some other reason.

In an operation320, the first set of data is stored in the active register210. Storing the first set of data is stored in the active register210can also include saving the first set of data from the active register to a corresponding first set of cells220A–220n, in a corresponding first thread220, in an operation325.

In an operation330, a second set of data is restored from a corresponding second set of cells222A–222n, in a corresponding second thread222, to the active register210. In an operation335, the second set of data is retrieved from the active register210for processing in an operation340. The method operations can then continue to switch between threads as described above in operations315–340.

FIG. 4is a schematic diagram of an active cell210A and corresponding base cells220A,222A and224A, in accordance with one embodiment of the present invention. The base cell224A includes a storage circuit402as is well known in the art. It should be known that the storage circuit402is shown as a cross-coupled inverter structure as an exemplary structure only. The storage circuit402is not limited to the cross-coupled inverter structure shown. The storage circuit402can include any structure capable of storing data that can later be read from the structure. The cross-coupled inverter circuit includes PMOS devices I61and I62and NMOS devices I59and I60with the cross-coupled gates as shown.

The base cell224A also includes a control signal input404that allows a control signal wlbTnto be selectively applied to the bases of the NMOS devices I57and I58. Applying an appropriate control signal wlbTnto the gates of the NMOS devices I57and I58causes the NMOS devices I57and I58to conduct. When the NMOS devices I57and I58are conducting a data value can be stored in or read from the storage circuit402.

The control signal wlbTncan also be applied when a respective thread is selected. By way of example, if the Thread n (Tn) is selected then wlbTncan also be applied to base cell224A. Similarly, if the Thread0(T0) is selected, then a respective control signal wlbT0can also be applied to base cell220A.

The active cell210A includes a storage circuit412. The storage circuit412is shown as a cross-coupled inverter circuit however, as described above in regard to the storage circuit402, the storage circuit412can be any structure capable of storing data that can later be read from the structure. The cross-coupled inverter circuit of the storage circuit412includes PMOS devices M1and M3and NMOS devices M0and M2. The gates of the PMOS devices M1and M3and NMOS devices M0and M2are cross-coupled as shown.

The active cell210A also includes a save control circuit414and a restore control circuit416. The save control circuit414allows the data applied to nodes sb and st to be applied to the bit lines bit and bit_n, respectively. The save control circuit414includes save drivers I53and I54and save pass gates M14and M17. The save control circuit414can optionally include an inverter I27on the save control node420so as to match the polarity of the control signal to the polarity of the gates of the pass gates M14and M17. The driver I53is coupled in series between node st and pass gate M14. Similarly, driver I54is coupled in series between node sb and pass gate M17. The outputs of the pass gates M14and M17are coupled to the bit_n and bit bitlines to the base cells220A,222A and224A.

The restore control circuit416includes restore drivers I0and I1and restore pass gates M29and M30. The restore control circuit416can optionally include an inverter I28on the restore control node422so as to match the polarity of the control signal to the polarity of the gates of the pass gates M29and M30. The driver I0is coupled in series between bitline bit_n and pass gate M29. Similarly, driver I1is coupled in series between bitline bit and pass gate M30. The outputs of the pass gates M29and M30are coupled to the node st and node in the storage circuit412.

The pass gates I57, I58, M14, M17, M29and M30only pass data signals and do not amplify the respective data signals that pass through them. The drivers I0, I1, I53and I54provide minimal amplification to the respective data signals that pass through them to and from the corresponding bitlines bit and bit_n. However, it should be understood that the amplification applied by the drivers I0, I1, I53and I54is very limited due to relative short length of the bitlines bit and bit_n. Further, the amplification applied by the drivers I0, I1, I53and I54can also be limited because the amplification needed is very small amount. By way of example, each of the storage circuits402and412can store a logical 1 value as about 0.6 volts. By way of example, in a restore operation, the drivers I0and I1must only detect a logical high value stored in the storage circuit402(e.g., about 0.6 volts) and then amplify that logical high value sufficient enough to ensure that about 0.6 volts (i.e., a logical 1 value) can be stored in the storage circuit412.

Further, very few devices are attached to the bitlines bit and bit_n and therefore the load on the drivers I0, I1, I53and I54is further reduced. As a result, each of the pass gates I57, I58, M14, M17, M29and M30and the drivers I0, I1, I53and I54can be relatively small devices. By way of example, the pass gates I57, I58, M14, M17, M29and M30and the drivers I0, I1, I53and I54can have device sizes approximately equal to the device size of the devices M0, M1, M2, M3, I59, I60, I61, and I62included in the storage circuits402and412.

The active cell210A can optionally include a pre-charge and pull-up circuit430. The pre-charge and pull-up circuit430includes pull-up devices I47, I48, I49and I52. The pull-up devices I47, I48, I49and I52couple VCC to the bit lines bit_n and bit when the data is not being saved or restored between the storage cell412and any of the other storage circuits in any of the base cells220A–224A. By way of example, when neither of the control signals save_n and rsto_n are applied to the control nodes420and422, the pull-up devices I47, I48, I49and I52are forward biased and VCC is coupled across the pull-up devices I47and I52to bit line bit_n and VCC is coupled across the pull-up devices I48and I49to bit line bit.

The active cell210A can optionally include a keeper circuit440. The keeper circuit430includes cross-coupled devices I50and I51. By way of example, when a logical low voltage is present on bit line bit_n, an inverse logical voltage (i.e., a logical high voltage) should be present on the bit line bit. When the logical low voltage is present on bit line bit_n, the gate to PMOS device I51is also pulled low, causing the PMOS device I51to couple VCC to bit line bit.

It should be understood that the devices I47, I48, I49, I52, I50and I51in the pre-charge and pull-up circuit430and the keeper circuit440can have device sizes approximately equal to the device size of the devices M0, M1, M2, M3, I59, I60, I61, and I62included in the storage circuits402and412. The devices I47, I48, I49, I52, I50and I51can be sized due to the substantially the same reasons set out above for pass gates I57, I58, M14, M17, M29and M30and the drivers I0, I1, I53and I54.

FIG. 5is a schematic diagram of a timing and control circuit450optionally included in the active cell210A, in accordance with one embodiment of the present invention. The timing and control circuit450provides a system for controlling when data is written to or read from the storage circuit412. Reading circuit includes a Nand gate I55. Bit line bit_n and thread select control signal th_sel node460are coupled to two inputs of Nand gate I55. The output node458of the Nand gate I55is the da_n (i.e., inverse data) of the data present on bit line bit_n (i.e., data present on node st of the storage circuit412). Although not shown, it should be understood that the Nand gate I55could similarly be coupled to bit line bit and thereby output the data present on bit line bit (i.e., data present on node sb of the storage circuit412) to output node458.

The timing and control circuit450also includes two write control circuits. The first write control circuit includes inverter I33and pass gates M34and M35. In operation, a write control signal wl0_n in applied to control node452of the inverter I33. The output of the inverter I33is applied to the gates of each of the pass gates M34and M35. When activated, pass gate M34passes the data applied to bl0_n at node456D to node sb of the storage cell412and pass gate M35passes the data applied to bl0at node456A to node st of the storage cell412.

The second write control circuit includes inverter I34and pass gates M37and M36. In operation, a write control signal wl1_n in applied to control node454of the inverter I34. The output of the inverter I34is applied to the gates of each of the pass gates M36and M37. When activated, pass gate M37passes the data applied to bl1_n at node456C to node sb of the storage cell412and pass gate M36passes the data applied to bl1at node456B to node st of the storage cell412.

FIG. 6is a flowchart of the method operations600of a data swap operation between two storage circuits402and412, in accordance with one embodiment of the present invention. In an operation605, the pass gates that couple a first storage circuit402to the bit lines bit_n and bit are activated. By way of example and as shown inFIG. 4, in a restore operation (e.g., transfer data from storage circuit402to storage circuit412) pass gates I57and I58are activated by a wordline control signal wlbTnapplied to node404.

In an operation610, the pass gates that couple a second storage circuit412to the bit lines bit_n and bit are activated. Continuing the above example, a restore control signal rsto_n is applied to input node422of inverter I28. The output of inverter I28activates pass gates M29and M30.

In an operation615, the data voltage level stored in the first storage circuit is amplified and in operation620the amplified data voltage level is applied to the bit lines. Continuing the above example, drivers I0and I1drive the data on the respective nodes stb and sbb of the first storage circuit402to respective bit lines bit_n and bit and to respective nodes st and sb of the second storage circuit412.

In an operation625, the amplified data voltage level output from the bit lines is stored in the second storage circuit. Continuing the above example, the data voltage level on the nodes st and sb are stored in the second storage circuit412.

In an alternative example of a save operation (i.e., transferring data from the second storage circuit412to the first storage circuit402), the pass gates M14and M17are activated by a control signal save_n applied to node420. Pass gates I57and I58are activated by a wordline control signal wlbTnapplied to node404. Drivers I53and I54drive the data on the respective nodes st and sb of the second storage circuit412to respective bit lines bit_n and bit and to respective nodes stb and sbb of the first storage circuit402. The data voltage level on the nodes stb and sbb are stored in the first storage circuit402.

As shown above, data can be transferred between an active cell210A any one or more of multiple base cells220A–224A that are coupled to the same bit line or bit lines. In one embodiment, four or eight or more base cells are coupled to each active cell by one or two transfer bit lines.

As described above, the data transfer drivers I0, I1, I53and I54and pre-charge devices I47, I48, I49and I52and keeper devices I50and I51are very small (e.g., core sized devices) and localized within the active memory cell210A, a lot of die area is saved which reduces the overall physical size of the active cell210A. Further, as the data transfer drivers I0, I1, I53and I54and pre-charge devices I47, I48, I49and I52and keeper devices I50and I51are core-sized devices, then the layout can also be simplified. By way of example, the bit lines bit_n and bit can be very short. As a result, the data can be transferred between the active cell210A and the base cells220A–224A in less time (i.e., faster data transfer speed).

During a save operation (i.e., swap data from active cell210A to base cell224A), since data is transferred thru small inverters I53and I54, there is a parasitic read can occur which can oppose the save operation because the device sizes of the driving inverter and base cell220A–224A are approximately the same. As a result, the430and440are used to make sure that the parasitic save operation does not occur and thereby improve the writability and provide a more robust swap operation.

In a first approach, the control signal save_n can be applied to node420early. By way of example, the control signal save_n can be applied to node420approximately two gate delays before the base cell wordline control signal wlbTnis applied to node404so that a sufficient voltage differential is developed on bitlines bit and bit_n to obviate any parasitic read effect from storage nodes stb and sbb in base cell224A.

In a second approach, a PMOS cross-coupled keeper circuit of PMOS I50and I51can be used so that transfer bitlines are not pulled low due to parasitic read. The PMOS keeper devices I50and I51also help during the save operation.

In a third approach, the drivers I53and I54and the save pass gates M14and M17can be sized up a slightly as compared to the NMOS pass gates I58and I57in base cell224A to improve the drive strength and thereby make the save operation more robust. By way of example, the drivers I53and I54and the pass gates M14and M17can have device sizes about two or about three times larger than the pass gates I58and I57. It should be understood that the drivers I53and I54and the save pass gates M14and M17can be sized according to the length of the bit lines bit_n and bit and the number of base cells220A–224A that are coupled to the bit lines bit_n and bit. By way of example, if the length of the bit lines bit_n and bit is very small then drivers I53and I54and the save pass gates M14and M17can be sized approximately the same size as the pass gates I58and I57and the other devices in the storage circuits402and412.

During a restore operation (i.e., data swap from base cell220A–224A to active cell210A), there is no conflict between the parasitic read and write as storage nodes st and sb in active cell discharge path are blocked during restore since th_sel is not asserted.

As used herein in connection with the description of the invention, the term “about” means +/−10%. By way of example, the phrase “about 250” indicates a range of between 225 and 275. With the above embodiments in mind, it should be understood that the invention may employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. Further, the manipulations performed are often referred to in terms, such as producing, identifying, determining, or comparing.

It will be further appreciated that the instructions represented by the operations in the above figures are not required to be performed in the order illustrated, and that all the processing represented by the operations may not be necessary to practice the invention. Further, the processes described in any of the above figures can also be implemented in software stored in any one of or combinations of the RAM, the ROM, or the hard disk drive.