Semiconductor element

A semiconductor device includes a substrate, a body region adjoining the substrate surface, a source contact region within the body region, a drain contact region adjoining the substrate surface and being separated from the body region, a dual JFET gate region located between the body region and the drain contact region, and a lateral JFET channel region adjoining the surface of the substrate and located between the body and the drain contact regions. A vertical JFET gate region is arranged essentially enclosed by the body region, a vertical JFET channel region being arranged between the enclosed vertical JFET gate and the dual JFET gate regions, a reduced drain resistance region being arranged between the dual JFET gate and the drain contact regions, and a buried pocket located under part of the body region, under the dual JFET gate region and under the vertical JFET channel and reduced drain resistance regions.

The present invention relates to a semiconductor device, especially a semiconductor device for use in RF-LDMOS devices for integration into standard CMOS technologies so as to enable a cost-effective on-chip design of multi-band PAs for single-chip solutions, e.g. WLAN applications.

The strong trend toward integration in hand held communication devices for cost and size advantages has started an intensive research effort on the implementation of high power and high efficiency power amplifiers in modern CMOS technologies. The main workhorse up to date has been using the bipolar device in 0.13 μm BiCMOS technologies. Advanced standard CMOS technologies at the 65 nm/45 nm node, otherwise suitable for single chip solutions e.g. WLAN, lack high voltage (around 10V) devices with good linearity and efficiency required for on-chip power amplifiers in the frequency range 2-5 GHz.

In U.S. Pat. No. 5,146,298 a high voltage LDMOS device is implemented as a low voltage MOS device in series with 2 JFETs with common source and drain. This type of device works well as long as the extended drift region is longer than a couple of pm and with a breakthrough voltage in the region of 30-800V. [R. Y. Su, F. J. Yang, J. L. Tsay, C. C. Cheng, R. S. Liou and H. C. Tuan, “State-of-the-art Device in High Voltage Power IC with Lowest On-State Resistance”, IEEE International Electron Devices Meeting (IEDM), pp. 492-495, 2010.]

InFIG. 1, which isFIG. 1from U.S. Pat. No. 5,146,298, is shown the above mentioned low voltage MOS device in series with 2 JFETs with common source and drain, and where now region11has been divided into regions11A,11B and11C. The region marked11A is part of pocket11, close to the source region13.11B is part of the pocket11under region15, and11C is part of the pocket11close to the drain contact region16. For a BV of around 10V where the distance6between gate and drain is around 0.5 μm the on-resistance and current will be determined mostly by the spreading resistances in region11A and region11C. Further as the current goes from source to drain through layer11, the length of the path is around 2.5 μm (depth of layer15is typically 1 μpm) as compared to along the surface 0.5 μm, region14, the n-top, which will increase the on-resistance.

To overcome this problem a new device is proposed where region11B and region11C are made very highly conductive and region11A is made as a very active vertical JFET with length 0.5 μm (depth in the figure of region15is reduced to 0.5 μm), and similar in length at the horizontal JFET at the surface.

A device fulfilling this is characterised in that a vertical JFET gate region is arranged essentially enclosed by the body region, a vertical JFET channel region being arranged between the vertical JFET gate region essentially enclosed by the body region and a dual JFET gate region, a reduced drain resistance region being arranged between said dual JFET gate region and the drain contact region, and a buried pocket being located under part of said body region, under said dual JFET gate region and under said vertical JFET channel and reduced drain resistance regions.

The present invention relates to a practical implementation of a semiconductor device, in which a substrate22of a first conductivity type is, for example, made of p-type material, doped with 1×1016atoms per cm3. A typical depth of substrate22is 100 μm. A buried pocket23of a second conductivity type, for example n-type material, doped at 5×1013atoms per cm2is arranged in the substrate22. The buried pocket23extends to a depth of, for example, 1 μm below a surface24of the die21. The doping levels and dimensions given here and below are for a device with a breakdown voltage of approximately 10 V.

Partly touching the pocket23is a body region25of the first conductivity type, for example p-type material, doped at 1×1018atoms per cm3. The body region25typically extends to a depth of 0.5 μm below the surface24of the die21. A source contact region26of the second conductivity type, for example n-type material, doped at between 1019and 1020atoms per cm3is located within the body region25. The source contact region26extends, for example, to a depth of 0.2 μm below the surface24of the die21.

A drain contact region27of the second conductivity type, for example n-type material, doped at between 1019and 1020atoms per cm3is arranged adjoined to the surface24but separated from the body region25. The drain contact region27extends, for example, to a depth of 0.2 μm below the surface24of the die21.

A source contact28is placed on the surface24in electrical contact with the body region25and a source contact region portion of the source contact region26. A drain contact29is placed on the surface24in electrical contact with the drain contact region27. An insulating layer30is placed on the surface24of the die21. A gate contact31is placed on the insulating layer30over a channel region portion of the body region25.

Partly in the body region25a vertical JFET gate region32of the first conductivity type is located. Between the body region25and region27is a dual JFET gate region33of the first conductivity type located. The vertical JFET gate region32and the dual JFET gate region33is, for example, p-type material both doped at 1×1013atoms per cm2. The vertical JFET gate region32and the dual JFET gate region33extend downwards from the surface24to a depth of, for example, 0.5 μm. The dual JFET gate region33is connected to ground at the surface24in a plane not shown inFIG. 2.

Between vertical JFET gate region32and the dual JFET gate region33is a vertical JFET channel region34of the second conductivity type located. Between the dual JFET gate region33and the drain contact region27is a reduced drain resistance region35of the second conductivity type located. The vertical JFET channel region34and the reduced drain resistance region35is, for example, n-type material both doped at 1×1017atoms per cm3. The vertical JFET channel region34and reduced drain resistance region35extend downwards from the surface24to a depth of, for example, 0.5 μm.

Above the dual JFET gate region33is a lateral JFET channel region36of the second conductivity type located. The lateral JFET channel region36is, for example, n-type material doped at 6×1012atoms per cm2. The lateral JFET channel region36extends downwards from the surface24to a depth of, for example, 0.2 μm. A distance37between an edge of the body region25and an edge of the drain contact region27is, for example 1 μm. A symmetry line39is used for placing a second half of the transistor in a mirror image to the first half shown inFIG. 2.

Above the dual JFET gate region33and the lateral JFET channel region36is a lateral JFET gate region38of the first conductivity type located. The lateral JFET gate region38is, for example, p-type material doped at 3×1012atoms per cm2. The lateral JFET gate region38extends downwards from the surface24to a depth of, for example, 0.05 μm. The lateral JFET gate region38is electrically connected to ground with a contact at the surface24or in a plane not shown inFIG. 2. The lateral JFET gate region38and the dual JFET gate region33may also be grounded in the plane shown by extending the body region25to make contact with JFET gate regions33and38, in given intervals regularly spaced from each other. The lateral JFET gate region38is optional and if it is removed the lateral JFET channel region36is, for example, doped at 3×1012atoms per cm2.

The device shown inFIG. 2may also function as a bipolar transistor with the source contact region26functioning as an emitter, the body region25functioning as a base and the vertical JFET channel region34, the lateral JFET channel region36, the buried pocket23, the reduced drain resistance region35and drain contact region27functioning as an extended collector.

FIG. 3shows a circuit diagram for a MOS transistor with an extended drain which is a parallel combination of a lateral double-sided JFET or optionally single-sided JFET and a vertical double-sided JFET shown inFIG. 2. The MOS transistor40is controlled by a gate contact42. Current through the MOS transistor42travels from a source contact41through the MOS transistor40, through the extended drain region to the drain contact46. The extended drain region includes a parallel combination of a lateral double-sided JFET43and a vertical double-sided JFET44in series with a resistor45. The gate of the lateral double-sided JFET43is connected to ground47and the gate of the vertical double-sided JFET44is connected to ground48.

The source contact41and the gate contact42of the MOS transistor40corresponds to the source contact region26and the gate contact31inFIG. 2. The channel of the lateral double-sided JFET43corresponds to the lateral JFET channel region36inFIG. 2. The grounded gate47of the lateral double-sided JFET43corresponds to the dual JFET gate region33and the lateral JFET gate region38. The channel of the vertical double-sided JFET44corresponds to the vertical

JFET channel region34inFIG. 2. The grounded gate48of the vertical double-sided JFET44corresponds to the dual JFET gate region33and the vertical JFET gate region32. The resistor45corresponds to the buried pocket23and the reduced drain resistance region35inFIG. 2.

A power device implemented in a 65 nm CMOS technology with gate oxide thickness of 5 nm and channel length around 0.2 μm according to the preferred embodiment will achieve an on-resistance of around 1 ohmmm and maximum drain current above 1 A/mm which is at least 2-3 times better than presently shown and should meet the performance specification for e.g. an integrated WLAN solution in the frequency range of 2-5 GHz. [E.g. A. Mai, H. Rucker, R. Sorge, D. Schmidt and C. Wipf, “Cost-Effective Integration of RF-LDMOS Transistors in 0.13 μm CMOS Technology”, IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF '09), pp. 1-4, 2009.]