IC devices including vertical TFETs are disclosed. An example IC device includes a substrate, a channel region, a first region, and a second region. One of the first and second regions is a source region and another one is a drain region. The first region includes a first semiconductor material. The second region includes a second semiconductor material that may be different from the first semiconductor material. The first region and the second region are doped with opposite types of dopants. The channel region includes a third semiconductor material that may be different from the first or second semiconductor material. The channel region is between the first region and the second region. The first region is between the channel region and the substrate. In some embodiments, the first or second region is formed through layer transfer or epitaxy (e.g., graphoepitaxy, chemical epitaxy, or a combination of both).

TECHNICAL FIELD

This disclosure relates generally to the field of semiconductor devices, and more specifically, to integrated circuit (IC) devices.

BACKGROUND

For the past several decades, the scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more processing capacity, however, is not without issue. The necessity to optimize the performance and energy consumption of devices becomes increasingly significant. Tunneling field-effect transistors (“tunneling FETs,” “tunnel FETs,” or “TFETs”) can be a booster for performance increase and energy consumption decrease.

DETAILED DESCRIPTION

Overview

For purposes of illustrating IC devices with vertical TFETs, proposed herein, it might be useful to first understand phenomena that may come into play in such structures. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

Metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely used in ICs. The superiority of MOSFETs lies in the scalability of these devices. However, the channel length scaling of MOSFETs has resulted in substantial energy dissipation in conventional complementary metal oxide semiconductor (CMOS) technology. As transistor size continues to decrease, the power supply voltage to transistors in ICs also decreases. The decrease in power supply voltage requires the threshold voltage of the transistors to decrease. However, lower threshold voltages can be difficult to obtain in MOSFETs because, as the threshold voltage is reduced, the ratio of ON-current to OFF-current also decreases. The ON-current refers to the current through a MOSFET when a gate voltage applied is above the threshold voltage and could be as high the supply voltage, and the OFF-current refers to current through a MOSFET when no gate voltage is applied or when a gate voltage applied is below the threshold voltage. Also, as MOSFET gate length scaling continues, controlling short channel effects such as drain-induced barrier lowering (DIBL) and sub-threshold swing is imperative for improved performance. In order to continue realizing improved performance with scaling of MOSFETs transistors with reduced energy dissipation are needed.

TFETs have potential to reduce power consumption and energy dissipation. TFETs have different switching mechanism from MOSFETs, making TFET devices promising candidates for low-power electronics. In case of MOSFETs, carriers are injected thermionically over the barrier. However, in case of TFET, carriers are injected from source to channel due to gate field induced band-to-band tunneling (BTBT). In the OFF state, alignment between the conduction band of the channel and the valence band of the source is missing, which avoids carrier tunneling and maintains a very low leakage current. However, in the ON state, when the gate field is present, the channel region’s conduction band is pulled down, which allows it to align with the source region’s valence band. This alignment reduces the tunneling barrier width and height, which allows carrier tunneling from source to channel region. This enables a sharp turn-on when the bands are aligned, and therefore allows TFET devices to operate well below the sub-thermionic limits with sub-threshold swing values below 60mV/decade. Under OFF state condition, TFET has comparatively higher barrier for the minority carriers, which leads to negligible leakage current due to minority carrier injection. Leakage current in TFET devices is well below leakage current in MOSFET devices at shorter channel lengths.

Embodiments of the present disclosure relates to IC devices including vertical TFETs. An example IC device includes a substrate, a pair of a source region and a drain region, and a channel region. The pair includes a first region and a second region. The first region includes a first semiconductor material doped with a first type of dopant. The second region includes a second semiconductor material doped with a second type of dopant. The second type is opposite the first type. The first region, channel region, and second region are stacked vertical on the substrate. The channel region is between the first region and the second region. The first region is between the channel region and the substrate. Each of the first region, channel region, and second region may be a layer of a semiconductor material. In some embodiments, the semiconductor materials of the three regions are different from each other. The IC device also includes a gate. The gate facilitates application of gate bias on at least a portion of the channel region. A longitudinal axis of the gate may be orthogonal to the substrate. The gate comprises a gate insulator and a gate electrode. The gate insulator wraps around at least a portion of the channel region. The gate electrode wraps around at least a portion of the gate insulator.

To form an example IC device including a vertical TFET, a first region is formed on the substrate, a channel region is formed on the first region, and a second region is formed on the channel region. Then a gate insulator is formed to wrap around at least a portion of the channel region. The gate insulator may also wrap at least a portion of the first region, at least a portion of the second region, or both. Also, a gate electrode is formed to wrap around at least a portion of the gate insulator.

In some embodiments, the first, channel, or second region can be formed through layer transfer. The first region is formed on a growth substrate. The first region and growth substrate are bonded with the substrate with the first region contacting the substrate. Then the growth substrate is removed so that the first region is transferred from the growth substrate to the substrate. Similarly, the channel region can be transferred from a growth substrate to the first region and the second region can be transferred from a growth substrate to the channel region. A growth substrate may include the same material as the region that is formed on it so that the region can be formed on the growth substrate through homoepitaxy. An orientation of the region can be aligned with (i.e., in parallel or substantially parallel to) an orientation of the growth substrate. In an embodiment, the three growth substrates have aligned orientations so that the three regions have aligned orientations.

In other embodiments, the first, channel, or second region can be formed through layer transfer. For instance, the second region can be formed through epitaxial growth on the channel region. The second region may have a different semiconductor material from the channel region so that the epitaxial growth is heteroepitaxial growth, which may cause that the orientation of the second region is not aligned with the orientation of the channel region. In some embodiments, a guiding pattern, e.g., a topographical guiding pattern, a chemical guiding pattern, or a combination of both, can be used to guide the crystal growth of the second region along a particular direction, e.g., the orientation of the channel region. That way, the orientation of the second region can be aligned with the orientation of the channel region despite that the second region and the channel region have different materials.

The present disclosure provides TFETs with vertical configurations and methods of forming such TFETs. The TFETs can be used in IC devices to reduce power consumption of the IC devices. Compared with MOSFETS, TFETs also have better potential for improve performance as the scaling of features in IC devices continues.

IC devices as described herein, in particular IC devices with including vertical TFETs as described herein, may be used for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies. Therefore, it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Furthermore, although a certain number of a given element may be illustrated in some of the drawings (e.g., a certain number of TFETS, a certain number of source regions, a certain number of drain regions, a certain number of channel regions, a certain number of gate insulators, a certain number of gate electrodes, etc.), this is simply for ease of illustration, and more, or less, than that number may be included in an IC device with a vertical TFET as described herein. Still further, various views shown in some of the drawings are intended to show relative arrangements of various elements therein. In other embodiments, various IC devices with vertical TFETs as described herein, or portions thereof, may include other elements or components that are not illustrated (e.g., transistor portions, various components that may be in electrical contact with any of the transistors, etc.). Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using e.g., Physical Failure Analysis (PFA) would allow determination of presence of IC devices with vertical TFETs as described herein.

Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. These operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. The terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side” to explain various features of the drawings, but these terms are simply for ease of discussion, and do not imply a desired or required orientation. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For example, some descriptions may refer to a particular source or drain region or contact being either a source region/contact or a drain region/contact. However, unless specified otherwise, which region/contact of a transistor is considered to be a source region/contact and which region/contact is considered to be a drain region/contact is not important because under certain operating conditions, designations of source and drain are often interchangeable. Therefore, descriptions provided herein may use the term of a “S/D” region/contact to indicate that the region/contact can be either a source region/contact, or a drain region/contact.

In another example, if used, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die,” the term “insulating” means “electrically insulating,” the term “conducting” means “electrically conducting,” unless otherwise specified. Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “an electrically conductive material” may include one or more electrically conductive materials.

In another example, if used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide.

In yet another example, a term “interconnect” may be used to describe any element formed of an electrically conductive material for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In general, the “interconnect” may refer to both conductive lines/wires (also sometimes referred to as “lines” or “metal lines” or “trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). In general, a term “conductive line” may be used to describe an electrically conductive element isolated by a dielectric material typically comprising an interlayer low-k dielectric that is provided within the plane of an IC chip. Such conductive lines are typically arranged in several levels, or several layers, of metallization stacks. On the other hand, the term “conductive via” may be used to describe an electrically conductive element that interconnects two or more conductive lines of different levels of a metallization stack. To that end, a via may be provided substantially perpendicularly to the plane of an IC chip or a support structure over which an IC device is provided and may interconnect two conductive lines in adjacent levels or two conductive lines in not adjacent levels. A term “metallization stack” may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC chip.

Furthermore, the term “connected” may be used to describe a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” may be used to describe either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” may be used to describe one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.

The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/- 20% of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/- 5-20% of a target value based on the context of a particular value as described herein or as known in the art. Also, the term “or” refers to an inclusive “or” and not to an exclusive “or.”

Example Vertical TFETs

FIG.1Ais a perspective view of an example IC device100including a vertical TFET105, according to some embodiments of the disclosure.FIG.1Bis a cross-sectional view of the example TFET, according to some embodiments of the disclosure. The IC device100also includes a substrate110. In other embodiments, the IC device100may include fewer, more, or different components.FIGS.1A and1Balso illustrate a reference coordinate system that includes an X-axis, a Y-axis, and a Z-axis, which are orthogonal to each other.

The substrate110may be any suitable structure with which the vertical TFET105can be associated. The substrate110has a surface115and a surface117. The surface115is opposite the surface117. In the embodiment ofFIGS.1A and1B, the vertical TFET105is on the surface115of the substrate110. In other embodiments, the vertical TFET105may be at least partially in the substrate110. For instance, a portion of the vertical TFET105, or the whole vertical TFET105, extends from the surface115to the surface117.

The substrate110may be a support structure, a die, a wafer, or a chip. In some embodiments, the substrate110may be a printed circuit board (PCB) substrate. In other embodiments, the substrate110is a semiconductor substrate, which is composed of semiconductor material systems including, for example, n-type or p-type materials systems. One or more transistors may be built on the substrate110. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of Group III-V, Group II-VI, or Group IV materials. In some embodiments, the substrate may be non-crystalline. Although a few examples of materials from which the substrate110may be formed are described here, any material that may serve as a foundation upon which IC devices implementing vertical TFETs as described herein may be built falls within the spirit and scope of the present disclosure. In various embodiments, the substrate110may include any such substrate material that provides a suitable surface for forming vertical TFETs. The substrate110may, e.g., be the wafer2000ofFIG.11A, discussed below, and may be, or be included in, a die, e.g., the singulated die2002ofFIG.11B, discussed below.

The vertical TFET105includes a first region120, a channel region130, a second region140, a gate insulator150, and a gate electrode160. The vertical TFET105has an orthogonal arrangement with respect to the substrate110. The first region120, channel region130, and second region140are stacked on the substrate110along the Z-axis, which is perpendicular to the surface115. As shown inFIGS.1A and1B, the first region120is over the substrate110, particularly on the surface115. The channel region130is over the first region120. The second region140is over the channel region130. The first region120is between the substrate110and the channel region130. In some embodiments, the first region120, channel region130, or second region140is a layer of a semiconductor material. A thickness of a layer (i.e., a dimension of a layer along the Z-axis) may be in a range from 1 to 50 nm. The first region120, channel region130, or second region140may have the same or different thicknesses.

The channel region130is between the first region120and the second region140. In some embodiments, the channel region130(or a combination f the first region120, channel region130, and second region140) has an elongated structure, such as nanowire, fin, or nanoribbon. As shown inFIG.1A, the channel region130has a longitudinal axis along the Z-axis, which is orthogonal to the substrate110. A dimension of the channel region130along the Z-axis may be greater than the dimensions of the channel region130along the X- and Y-axes. In some embodiments (such as embodiments where the channel region130is a nanowire), the transverse cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis) of the channel region130in a X-Y plane may be circular. In other embodiments, the semiconductor structure may have a transverse cross-section of other shapes, such as rectangular, square, triangle, trapezoid, oval, parallelogram, and so on.

The channel region130includes a channel material. The channel material may be composed of semiconductor material systems including, for example, n-type or p-type materials systems. In some embodiments, the channel material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material may include a compound semiconductor with a first sub-lattice of at least one element from Group III of the periodic table (e.g., AI, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material may include a compound semiconductor with a first sub-lattice of at least one element from Group II of the periodic table (e.g., Zn, Cd, Hg), and a second sub-lattice of at least one element of Group IV of the periodic table (e.g., C, Si, Ge, Sn, Pb). In some embodiments, the channel material is an epitaxial semiconductor material deposited using an epitaxial deposition process. The epitaxial semiconductor material may have a polycrystalline structure with a grain size between about 2 nanometers and 100 nanometers, including all values and ranges therein.

For some example n-type transistor embodiments (i.e., for the embodiments where the MOSFET is a NMOS transistor and the TFET is a n-type TFET), the channel material may advantageously include a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). In some embodiments with highest mobility, the channel material may be an intrinsic III-V material, i.e., a III-V semiconductor material not intentionally doped with any electrically active impurity. In alternate embodiments, a nominal impurity dopant level may be present within the channel material, for example to further fine-tune a threshold voltage Vt, or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel material304may be relatively low, for example below1015dopant atoms per cubic centimeter (cm-3), and advantageously below 1013cm-3. These materials may be amorphous or polycrystalline, e.g., having a crystal grain size between 0.5 nanometers and 100 nanometers.

For some example p-type transistor embodiments (i.e., for the embodiments where the MOSFET is a PMOS transistor and the TFET is a p-type TFET), the channel material may advantageously be a Group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments with highest mobility, the channel material may be intrinsic III-V (or IV for P-type devices) material and not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel material, for example to further set a threshold voltage (Vt), or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion is relatively low, for example below 1015cm-3, and advantageously below 1013cm-3. These materials may be amorphous or polycrystalline, e.g., having a crystal grain size between 0.5 nanometers and 100 nanometers.

In some embodiments, the channel material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, aluminum zinc oxide, or tungsten oxide. In general, if the vertical TFET105is a thin-film transistor, the channel material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, molybdenum disulfide, N- or P-type amorphous or polycrystalline silicon, monocrystalline silicon, germanium, indium arsenide, indium gallium arsenide, indium selenide, indium antimonide, zinc antimonide, antimony selenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, black phosphorus, zinc sulfide, indium sulfide, gallium sulfide, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, a thin-film channel material may be deposited at relatively low temperatures, which allows depositing the channel material within the thermal budgets imposed on back-end fabrication to avoid damaging other components, e.g., front end components such as logic devices.

As noted above, the channel material may include IGZO. IGZO-based devices have several desirable electrical and manufacturing properties. IGZO has high electron mobility compared to other semiconductors, e.g., in the range of 20-50 times than amorphous silicon. Furthermore, amorphous IGZO (a-IGZO) transistors are typically characterized by high band gaps, low-temperature process compatibility, and low fabrication cost relative to other semiconductors.

IGZO can be deposited as a uniform amorphous phase while retaining higher carrier mobility than oxide semiconductors such as zinc oxide. Different formulations of IGZO include different ratios of indium oxide, gallium oxide, and zinc oxide. One particular form of IGZO has the chemical formula InGaO3(ZnO)5. Another example form of IGZO has an indium:gallium:zinc ratio of 1:2:1. In various other examples, IGZO may have a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and/or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). IGZO can also contain tertiary dopants such as aluminum or nitrogen.

The first region120and the second region140constitute a pair of a source region and a drain region. In an embodiment, the first region120is the source region of the vertical TFET105and the second region140is the drain region of the vertical TFET105. In another embodiment, the first region120is the drain region and the second region140is the source region. The first region120and the second region140each includes a doped semiconductor material. A doped semiconductor material is a semiconductor material into which dopants (e.g., impurities) are integrated.

The semiconductor material of the first region120may be different from the semiconductor material of the second region140. In some embodiments, the semiconductor material of the first region120or the second region140is a Group IV material, a compound of Group IV materials, a Group III/V material, a compound of Group III/V materials, a Group II/VI material, a compound of Group II/VI materials, or other semiconductor materials. Example Group II materials include zinc (Zn), cadmium (Cd), and so on. Example Group III materials include aluminum (AI), boron (B), indium (In), gallium (Ga), and so on. Example Group IV materials include silicon (Si), germanium (Ge), carbon (C), etc. Example Group V materials include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and so on. Example Group VI materials include sulfur (S), selenium (Se), tellurium (Te), oxygen (O), and so on. A compound of Group IV materials can be a binary compound, such as SiC, SiGe, and so on. A compound of Group III/V materials can be a binary, tertiary, or quaternary compound, such as GaN, InN, and so on. A compound of Group II/VI materials can be a binary, tertiary, or quaternary compounds, such as CdSe, CdS, CdTe, ZnO, ZnSe, ZnS, ZnTe, CdZnTe, CZT, HgCdTe, HgZnTe, and so on.

In some embodiments, the semiconductor material of the first region120is different from the semiconductor material of the second region140, or the channel material of the channel region130, or both. In other embodiments, the semiconductor material of the first region120or the second region140may be the same as the channel material of the channel region130. In some embodiments, the first region120, second region140, and channel region130each include a crystalline structure and has a crystal orientation. The crystal orientation of the channel region130may be different from the crystal orientation of the first region120, or the second region140, or both. The crystal orientation of the first region120may be different from the crystal orientation of the second region140.

In some embodiments, the S/D regions are highly doped, e.g., with dopant concentrations of about 1.1021dopants per cubic centimeter (cm-3), in order to advantageously form Ohmic contacts with the respective S/D contacts (also sometimes interchangeably referred to as “S/D electrodes”), although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Irrespective of the exact doping levels, the S/D regions of the vertical TFET105may be the regions having dopant concentration higher than in other regions, e.g., higher than a dopant concentration in the channel region130, and, therefore, may be referred to as “highly doped” (HD) regions. The channel region130may include one or more semiconductor materials with doping concentrations significantly smaller than those of the S/D regions. For example, in some embodiments, the channel material of the channel region130may be an intrinsic (e.g., undoped) semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, nominal impurity dopant levels may be present within the channel material, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the channel material of the vertical TFET105are still significantly lower than the dopant level in the S/D regions, for example below 1015cm-3, or below 1013cm-3. Depending on the context, the term “S/D terminal” may refer to a S/D region or a S/D contact or electrode of a transistor.

The channel region130can form a source-channel interface with the source region of the vertical TFET105. In some embodiments, a portion of the source-channel interface is in the source region and another portion of the source-channel interface is in the channel region130. The source-channel interface includes the type of dopants in the source region. The source-channel interface may be formed through migration of the dopants form the source region to the channel region130. There can be a gradual change in the concentration of the dopants in the source-channel interface. For instance, the concentration of the dopants in the source-channel interface decreases along the direction from the source region to the channel region130, i.e., there is less dopants per unit volume as it is father from the source region and closer to the channel region130. Similarly, the channel region130can form a drain-channel interface with the drain region of the vertical TFET105. The drain-channel interface includes the type of dopants in the drain region. A portion of the source-channel interface may be in the drain region and another portion of the source-channel interface may be in the channel region130. The drain-channel interface may be formed through migration of the dopants form the drain region to the channel region130. There can be a gradual change in the concentration of the dopants in the drain-channel interface. For instance, the concentration of the dopants in the drain-channel interface decreases along the direction from the drain region to the channel region130, i.e., there is less dopants per unit volume as it is father from the drain region and closer to the channel region130. In some embodiments, a length of the source-channel interface or drain-channel interface along the Z-axis is no more than 2 nm.

The gate insulator150separates at least a portion of the channel region130from the gate electrode160so that the channel region130is insulated from the gate electrode160. In the embodiment ofFIGS.1A and1B, the gate insulator150wraps around the whole first region120, the whole channel region130, and the whole second region140. The first region120, channel region130, and second region140are enclosed by the gate insulator150. In other embodiments, the gate insulator150may wrap around a portion of the first region120or a portion of the second region140, in addition to the whole channel region130. Alternatively, the gate insulator150may wrap around a portion of the channel region130, as opposed to the whole channel region130. The gate insulator150includes an electrical insulator, such as a dielectric material, hysteretic material, and so on. Example dielectric material includes oxide (e.g., Si based oxides, metal oxides, etc), high-k dielectric, and so on. Example hysteretic material include ferroelectric materials, antiferroelectric materials, etc.

In the embodiment ofFIGS.1A and1B, the gate insulator150has a longitudinal axis along the Z-axis. The longitudinal axis of the gate insulator150is perpendicular to the surface115of the substrate110. A thickness155of the gate insulator150along the X-axis, which is shown inFIG.1B, may be in a range from 0.5 nm to 20 nm. The shape or dimensions of the gate insulator150can be different.

The gate electrode160wraps around a portion of the gate insulator150. In some embodiments, the gate electrode160is provided upon the gate insulator150such that the gate electrode160does not extend beyond the gate insulator150in the direction along the Z-axis. In other words, a part or all of the first region120, channel region130, and the second region140is separated from the gate electrode160by the gate insulator150so that the first region120, channel region130, and the second region140do not have direct contact with the gate electrode160. The gate electrode160includes an electrical conductor, such as a metal, alloy, metal-nitride, conductive oxide, conductive metal compounds, and so on. The gate electrode160has a longitudinal axis along the Z-axis. The longitudinal axis of the gate electrode160is perpendicular to the surface115of the substrate110. In some embodiments, a length of the gate electrode160along the Z-axis is in a range from 1 nm to 50 nm. A thickness165of the gate electrode160along the X-axis, which is shown inFIG.1B, may be in a range from 0.5 nm to 20 nm. The shape or dimensions of the gate electrode160can be different.

The gate electrode160can be coupled to a gate terminal that controls the electrostatic potential of the channel region130. Also, additional terminals can be coupled to the first region120and the second region140. In some embodiments, an opening is formed in the substrate110to facilitate the coupling between a terminal and the first region120. The opening may extend from the surface115to the surface117. An electrical connection (e.g., a via) may be formed in the opening to connect the first region120to the terminal.

The vertical TFET105operates based on BTBT. For BTBT to occur, an electron in the valence band of semiconductor tunnels across the band gap to the conduction band without the assistance of traps. BTBT can be triggered by applying a gate bias onto the channel region130through the gate electrode160. The vertical TFET105can be operated by applying gate bias so that electron accumulation occurs in the channel region130. At sufficient gate bias, BTBT occurs when the conduction band of the channel region130aligns with the valence band of the p-type region (i.e., the region doped with p-type dopants, e.g., the first region120or the second region140). Electrons from the valence band of the p-type region tunnel into the conduction band of the channel region130and current can flow across the TFET. As the gate bias is reduced, the bands become misaligned and current can no longer flow. In some embodiments, the vertical TFET105is an n-type TFET, in which the source region is doped with p-type dopants and the drain region is doped with n-type dopants. In other embodiments, the vertical TFET105is a p-type TFET, in which the source region is doped with n-type dopants and the drain region is doped with p-type dopants.

In some embodiments, the vertical TFET105may be a thin-film transistor (TFT). A TFT is a special kind of a FET made by depositing a thin film of an active semiconductor material, as well as a dielectric layer and conductive (e.g., metallic) contacts, over a supporting layer that may be a non-conductor layer and a non-semiconductor layer. At least a portion of the active semiconductor material forms a channel region/material of the TFT. This is different from conventional, non-TFT, front-end-of line (FEOL) transistors where the semiconductor channel material of a transistor is typically a part of a semiconductor substrate, e.g., a part of a silicon wafer, or is epitaxially grown on a semiconductor substrate. Using TFTs as transistors of memory cells provides several advantages and enables unique architectures that were not possible with conventional, FEOL logic transistors. For example, advantages include substantially lower leakage in TFTs than in logic transistors and lower temperature processing used to fabricate TFTs. In context of the present disclosure, the vertical TFET105being a TFT advantageously allows depositing a thin-film channel material of the vertical TFET105in a non-planar arrangement to realize vertical transistor architecture, as will be described in greater detail below.

FIG.2is a cross-sectional view of another example device200including a vertical TFET205, according to some embodiments of the disclosure. The IC device200also includes a substrate210. In other embodiments, the IC device200may include fewer, more, or different components.

The substrate210may be any suitable structure with which the vertical TFET205can be associated. The substrate210has a surface205and another surface207. The surface215is opposite the surface217. In the embodiment ofFIG.2, the vertical TFET205is on the surface215of the substrate210. In other embodiments, the vertical TFET205may be at least partially in the substrate210. For instance, a portion of the vertical TFET205, or the whole vertical TFET205, extends from the surface215to the surface217. The substrate210may be the same as or similar to the substrate110described above in conjunction withFIGS.1A and1B. The substrate210may, e.g., be the wafer2000ofFIG.21A, discussed below, and may be, or be included in, a die, e.g., the singulated die2002ofFIG.21B, discussed below.

The vertical TFET205includes a first region220, a channel region230, a second region240, a gate insulator250, and a gate electrode260. The vertical TFET205has an orthogonal arrangement with respect to the substrate210. The first region220, channel region230, and second region240are stacked on the substrate210along the Z-axis, which is perpendicular to the surface215. As shown inFIG.2, the first region220is over the substrate210, particularly on the surface215. The channel region230is over the first region220. The second region240is over the channel region230. The first region220is between the substrate210and the channel region230. The channel region230is between the first region220and the second region240.

The first region220and the second region240constitute a pair of a source region and a drain region. In an embodiment, the first region220is the source region of the vertical TFET205and the second region240is the drain region of the vertical TFET205. In another embodiment, the first region220is the drain region and the second region240is the source region. The first region220and the second region240each includes a doped semiconductor material. A doped semiconductor material is a semiconductor material into which dopants (e.g., impurities) are integrated. Dopants can be either p-type dopants or n-type dopants. The first region220and the second region240are doped with opposite types of dopants. For instance, the first region220is doped with an n-type dopant, versus the second region240is doped with a p-type dopant. Alternatively, the first region220is doped with a p-type dopant and the second region240is doped with an n-type dopant.

The channel region230is between the first region220and the second region240. The channel region230includes a semiconductor material. The semiconductor material of the channel region230may be different from the semiconductor materials of the first region220and the second region240. In some embodiments, the semiconductor materials of the first region220, second region240, and channel region are all different from each other. In some embodiments, the channel region230is undoped. In other embodiments, the channel region230is lowly doped, e.g., with either n-type dopants or p-type dopants. The semiconductor material of the first region220, second region240, or channel region230may be one of the semiconductor materials listed above. The dopant of the first region220, second region240, or channel region230may be one of the dopants listed above.

The channel region230can form a source-channel interface with the source region of the vertical TFET205. In some embodiments, a portion of the source-channel interface is in the source region and another portion of the source-channel interface is in the channel region230. The source-channel interface includes the type of dopants in the source region. The source-channel interface may be formed through migration of the dopants form the source region to the channel region230. There can be a gradual change in the concentration of the dopants in the source-channel interface. For instance, the concentration of the dopants in the source-channel interface decreases along the direction from the source region to the channel region230, i.e., there is less dopants per unit volume as it is closer to the channel region230. Similarly, the channel region230can form a drain-channel interface with the drain region of the vertical TFET205. The drain-channel interface includes the type of dopants in the drain region. A portion of the drain-channel interface may be in the drain region and another portion of the drain-channel interface may be in the channel region230. The drain-channel interface may be formed through migration of the dopants form the drain region to the channel region230. There can be a gradual change in the concentration of the dopants in the drain-channel interface. For instance, the concentration of the dopants in the drain-channel interface decreases along the direction from the drain region to the channel region230, i.e., there is less dopants per unit volume as it is closer to the channel region230. In some embodiments, a length of the source-channel interface or drain-channel interface along the Z-axis is no more than 2 nm.

As shown inFIG.2, the second region240encloses a portion of the channel region230. The channel region230and the second region240may include crystal structures of semiconductors. A crystal structure has a crystal orientation. In the embodiment ofFIG.2, the channel region230has a crystal orientation235and the second region240has a crystal orientation245. The crystal orientation245is at an angle247to the crystal orientation235, i.e., the crystal orientation245is different from the crystal orientation235. The angle247depends on the materials of the second region240, the material of the channel region230, or both. In an embodiment, the angle247is approximately 60 degrees. For purpose of illustration, the cross-section of the second region240in the X-Z plane has a shape of a parallelograms with sharp corners. In other embodiments, the cross-section of the second region240can have other shapes, e.g., a curved shape with round corners. In some embodiments, the second region240is formed through an epitaxy process, e.g., heteroepitaxy. More details regarding formation of the second region240is described below in conjunction withFIGS.6A-6C.

The gate insulator250separates at least a portion of the channel region230from the gate electrode260. In the embodiment ofFIG.2, the gate insulator250wraps around the first region220and a portion of the channel region230, but does not wrap around any of the second region240. The gate insulator250includes an electrical insulator, which may be the same as the electrical insulator of the gate insulator150.

The gate electrode260wraps around a portion of the gate insulator250. In some embodiments, the gate electrode260is provided upon the gate insulator250such that the gate electrode260does not extend beyond the gate insulator250in the direction along the Z-axis. In other words, a part or all of the first region220, channel region230, and the second region240is separated from the gate electrode260by the gate insulator250so that the first region220, channel region230, and the second region240do not have direct contact with the gate electrode260. The gate electrode260includes an electrical conductor, such as one of the electrical conductors listed above. The gate electrode260can be coupled to a gate terminal that controls the electrostatic potential of the channel region230.

FIG.3is a cross-sectional view of yet another example IC device300including a vertical TFET305, according to some embodiments of the disclosure. The IC device300also includes a substrate310. In other embodiments, the IC device300may include fewer, more, or different components.

The substrate310may be any suitable structure with which the vertical TFET305can be associated. The substrate310has a surface315and a surface317. The surface305is opposite the surface307. In the embodiment ofFIG.3, the vertical TFET305is on the surface315of the substrate310. In other embodiments, the vertical TFET305may be at least partially in the substrate310. For instance, a portion of the vertical TFET305, or the whole vertical TFET305, extends from the surface315to the surface317. The substrate310may be the same as or similar to the substrate110described above in conjunction withFIGS.1A and1B. The substrate310may, e.g., be the wafer2000ofFIG.21A, discussed below, and may be, or be included in, a die, e.g., the singulated die2002ofFIG.21B, discussed below.

The vertical TFET305includes a first region320, a channel region330, a second region340, a gate insulator350, and a gate electrode360. The vertical TFET305has an orthogonal arrangement with respect to the substrate310. The first region320, channel region330, and second region340are stacked on the substrate310along the Z-axis, which is perpendicular to the surface315. As shown inFIG.3, the first region320is over the substrate310, particularly on the surface315. The channel region330is over the first region320. The second region340is over the channel region330. The first region320is between the substrate310and the channel region330. The channel region330is between the first region320and the second region340.

The first region320and the second region340constitute a pair of a source region and a drain region. In an embodiment, the first region320is the source region of the vertical TFET305and the second region340is the drain region of the vertical TFET305. In another embodiment, the first region320is the drain region and the second region340is the source region. The first region320and the second region340each includes a doped semiconductor material. A doped semiconductor material is a semiconductor material into which dopants (e.g., impurities) are integrated. Dopants can be either p-type dopants or n-type dopants. The first region320and the second region340are doped with opposite types of dopants. For instance, the first region320is doped with an n-type dopant, versus the second region340is doped with a p-type dopant. Alternatively, the first region320is doped with a p-type dopant and the second region340is doped with an n-type dopant.

The channel region330is between the first region320and the second region340. The channel region330includes a semiconductor material. The semiconductor material of the channel region330may be different from the semiconductor materials of the first region320and the second region340. In some embodiments, the semiconductor materials of the first region320, second region340, and channel region are all different from each other. In some embodiments, the channel region330is undoped. In other embodiments, the channel region330is lowly doped, e.g., with either n-type dopants or p-type dopants. The semiconductor material of the first region320, second region340, or channel region may be one of the semiconductor materials listed above. The dopant of the first region320, second region340, or channel region may be one of the dopants listed above.

The channel region330can form a source-channel interface with the source region of the vertical TFET305. In some embodiments, a portion of the source-channel interface is in the source region and another portion of the source-channel interface is in the channel region330. The source-channel interface includes the type of dopants in the source region. The source-channel interface may be formed through migration of the dopants form the source region to the channel region330. There can be a gradual change in the concentration of the dopants in the source-channel interface. For instance, the concentration of the dopants in the source-channel interface decreases along the direction from the source region to the channel region330, i.e., there is less dopants per unit volume as it is closer to the channel region330. Similarly, the channel region330can form a drain-channel interface with the drain region of the vertical TFET305. The drain-channel interface includes the type of dopants in the drain region. A portion of the drain-channel interface may be in the drain region and another portion of the drain-channel interface may be in the channel region330. The drain-channel interface may be formed through migration of the dopants form the drain region to the channel region330. There can be a gradual change in the concentration of the dopants in the drain-channel interface. For instance, the concentration of the dopants in the drain-channel interface decreases along the direction from the drain region to the channel region330, i.e., there is less dopants per unit volume as it is closer to the channel region330. In some embodiments, a length of the source-channel interface or drain-channel interface along the Z-axis is no more than 2 nm.

As shown inFIG.3, a portion of the second region340is wrapped around by the channel region330. The length of the second region340along the X-axis is shorter than the length of the channel region330along the X-axis. In some embodiments, the channel region330and the second region340include different semiconductor materials. The channel region330and the second region340may include crystal structures. The crystal orientations of the channel region330and the second region340may be aligned along the same direction, e.g., the Z-axis. In some embodiments, the second region340is formed through an epitaxy process, e.g., graphoepitaxy. More details regarding formation of the second region340is described below in conjunction withFIGS.7A-7CandFIGS.8C-8E.

The gate insulator350separates at least a portion of the channel region330from the gate electrode360. In the embodiment ofFIG.3, the gate insulator350wraps around the first region320and a portion of the channel region330, but does not wrap around any of the second region340. The gate insulator350includes an electrical insulator, which may be the same as the electrical insulator of the gate insulator150.

The gate electrode360wraps around a portion of the gate insulator350. In some embodiments, the gate electrode360is provided upon the gate insulator350such that the gate electrode360does not extend beyond the gate insulator350in the direction along the Z-axis. In other words, a part or all of the first region320, channel region330, and the second region340is separated from the gate electrode360by the gate insulator350so that the first region320, channel region330, and the second region340do not have direct contact with the gate electrode360. The gate electrode360includes an electrical conductor, such as one of the electrical conductors listed above. The gate electrode360can be coupled to a gate terminal that controls the electrostatic potential of the channel region330.

FIG.4is a cross-sectional view of yet another example IC device400including a vertical TFET405, according to some embodiments of the disclosure. The IC device400also includes a substrate410. In other embodiments, the IC device400may include fewer, more, or different components.

The substrate410may be any suitable structure with which the vertical TFET405can be associated. The substrate410has a surface415and a surface417. The surface415is opposite the surface417. In the embodiment ofFIG.4, the vertical TFET405is on the surface415of the substrate410. In other embodiments, the vertical TFET405may be at least partially in the substrate410. For instance, a portion of the vertical TFET405, or the whole vertical TFET405, extends from the surface415to the surface417. The substrate410may be the same as or similar to the substrate110described above in conjunction withFIGS.1A and1B. The substrate410may, e.g., be the wafer2000ofFIG.21A, discussed below, and may be, or be included in, a die, e.g., the singulated die2002ofFIG.21B, discussed below.

The vertical TFET405includes a first region420, a channel region430, a second region440, a gate insulator450, and a gate electrode460. The vertical TFET405has an orthogonal arrangement with respect to the substrate410. The first region420, channel region430, and second region440are stacked on the substrate410along the Z-axis, which is perpendicular to the surface415. As shown inFIG.4, the first region420is over the substrate410, particularly on the surface415. The channel region430is over the first region420. The second region440is over the channel region430. The first region420is between the substrate410and the channel region430. The channel region430is between the first region420and the second region440.

The first region420and the second region440constitute a pair of a source region and a drain region. In an embodiment, the first region420is the source region of the vertical TFET405and the second region440is the drain region of the vertical TFET405. In another embodiment, the first region420is the drain region and the second region440is the source region. The first region420and the second region440each includes a doped semiconductor material. A doped semiconductor material is a semiconductor material into which dopants (e.g., impurities) are integrated. Dopants can be either p-type dopants or n-type dopants. The first region420and the second region440are doped with opposite types of dopants. For instance, the first region420is doped with an n-type dopant, versus the second region440is doped with a p-type dopant. Alternatively, the first region420is doped with a p-type dopant and the second region440is doped with an n-type dopant.

The channel region430is between the first region420and the second region440. The channel region430includes a semiconductor material. The semiconductor material of the channel region430may be different from the semiconductor materials of the first region420and the second region440. In some embodiments, the semiconductor materials of the first region420, second region440, and channel region are all different from each other. In some embodiments, the channel region430is undoped. In other embodiments, the channel region430is lowly doped, e.g., with either n-type dopants or p-type dopants. The semiconductor material of the first region420, second region440, or channel region may be one of the semiconductor materials listed above. The dopant of the first region420, second region440, or channel region430may be one of the dopants listed above.

The channel region430can form a source-channel interface with the source region of the vertical TFET405. In some embodiments, a portion of the source-channel interface is in the source region and another portion of the source-channel interface is in the channel region430. The source-channel interface includes the type of dopants in the source region. The source-channel interface may be formed through migration of the dopants form the source region to the channel region430. There can be a gradual change in the concentration of the dopants in the source-channel interface. For instance, the concentration of the dopants in the source-channel interface decreases along the direction from the source region to the channel region430, i.e., there is less dopants per unit volume as it is closer to the channel region430. Similarly, the channel region430can form a drain-channel interface with the drain region of the vertical TFET405. The drain-channel interface includes the type of dopants in the drain region. A portion of the drain-channel interface may be in the drain region and another portion of the drain-channel interface may be in the channel region430. The drain-channel interface may be formed through migration of the dopants form the drain region to the channel region430. There can be a gradual change in the concentration of the dopants in the drain-channel interface. For instance, the concentration of the dopants in the drain-channel interface decreases along the direction from the drain region to the channel region430, i.e., there is less dopants per unit volume as it is closer to the channel region430. In some embodiments, a length of the source-channel interface or drain-channel interface along the Z-axis is no more than 2 nm.

As shown inFIG.4, the length of the first region420along the X-axis is longer than the length of the channel region430along the X-axis, which is longer than the length of the second region440along the X-axis. Also, different from the embodiment shown inFIGS.1A and1B, the gate insulator450inFIG.4wraps around the channel region430but does not wrap around the first region420or the second region440. Rather, the gate insulator450is over the first region420. In some embodiments, the channel region430and the second region440can be formed through epitaxy, e.g., graphoepitaxy, chemoepitaxy, or both. More details regarding formation of the channel region430and the second region440are described below in conjunction withFIGS.8A-8E.

The gate insulator450separates at least a portion of the channel region430from the gate electrode460. In the embodiment ofFIG.4, the gate insulator450wraps around the first region420and a portion of the channel region430, but does not wrap around any of the second region440. The gate insulator450includes an electrical insulator, which may be the same as the electrical insulator of the gate insulator150.

The gate electrode460wraps around a portion of the gate insulator450. In some embodiments, the gate electrode460is provided upon the gate insulator450such that the gate electrode460does not extend beyond the gate insulator450in the direction along the Z-axis. In other words, a part or all of the first region420, channel region430, and the second region440is separated from the gate electrode460by the gate insulator450so that the first region420, channel region430, and the second region440do not have direct contact with the gate electrode460. The gate electrode460includes an electrical conductor, such as one of the electrical conductors listed above. The gate electrode460can be coupled to a gate terminal that controls the electrostatic potential of the channel region430.

Example Processes of Forming Vertical TFETs

FIGS.5A-5Qillustrate an example process of forming a vertical TFET500through layer transfer, according to some embodiments of the disclosure. Layer transfer includes transferring a layer (e.g., a layer of a semiconductor material) from a growth substrate (e.g., a substrate on which the layer is deposited) to a target substrate.FIG.5Ashows a growth substrate505. The growth substrate505may be any suitable structure on which a semiconductor layer can be grown. The growth substrate505may be semiconductor substrate that includes a semiconductor material. Alternatively, the growth substrate505may include other materials, such as glass. The growth substrate505may include the same material as the substrate110. In various embodiments, the growth substrate505may include any such substrate material that provides a suitable surface for forming the semiconductor layer.

InFIG.5B, a semiconductor layer520is formed on the growth substrate505, which generates a structure515. The semiconductor layer520includes a semiconductor material. The semiconductor layer520may be an embodiment of the first region120inFIGS.1A and1B. The semiconductor layer520may be formed by depositing the semiconductor material onto the growth substrate505. Various deposition techniques can be used, including, e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. Dopants (e.g., n-type dopant or p-type dopant) can be incorporated into the semiconductor material before, during, or after the formation of the semiconductor layer520. In an embodiment, the dopant is mixed with a precursor of the semiconductor material and the mixture is sprayed onto the growth substrate505to form the semiconductor layer520. In another embodiment, the dopant is incorporated into the semiconductor material after the semiconductor layer520is formed on the growth substrate505. InFIG.5C, the structure515is flipped over so that the semiconductor layer520is on the bottom and the growth substrate505is on the top. The step inFIG.5Cmay be optional.

InFIG.5D, the structure515is bonded to a substrate510with the semiconductor layer520touching the substrate510. The substrate510may be an embodiment of the substrate110inFIGS.1A and1B. In some embodiments, the structure515and the semiconductor layer520are bonded together through a thermal compression process. For instance, the structure515is placed over the semiconductor layer520with the semiconductor layer520contacting the semiconductor layer520to form a structure525. Then the structure525is compressed at a predetermined temperature for a predetermined duration of time to form a bonding between the semiconductor layer520and the substrate510. The temperature and duration of time can be determined based on the semiconductor materials of the semiconductor layers520and530.

In some embodiments, an adhesive layer (not shown inFIG.5D) is used to facilitate the bonding. The adhesive layer may be formed on the substrate510or the semiconductor layer520, e.g., through spin coating. The adhesive layer may be in a flowable state. The heating during the thermal compression can harden the adhesive layer and form a stable bond between the substrate510and the semiconductor layer520. An example of the adhesive layer is a hydrogen silsesquioxane (HSQ) layer.

After the bonding process, the growth substrate505is removed from the structure525. The growth substrate505can be removed through various techniques, such as etching, mechanical thinning, epitaxial lift-off, mechanical spalling, laser lift-off, ion cutting, and so on. As a result, a structure502is formed. As shown inFIG.5E, the structure502includes the substrate510and the semiconductor layer520. Through the steps inFIGS.5B-5E, the semiconductor layer520is “transferred” from the growth substrate505to the substrate510, i.e., the target substrate.

FIGS.5F-5Jshows another layer transfer process.FIG.5Fshows a growth substrate535, which may be the same as or similar to the growth substrate505. InFIG.5G, a semiconductor layer530is formed on the growth substrate535and a structure545is generated. The semiconductor layer530may be formed through a process that is the same as or similar to the process of forming the semiconductor layer520. The semiconductor layer530includes a semiconductor material, which may be the same as or different from the semiconductor material of the semiconductor layer520. The semiconductor layer530may be an embodiment of the channel region130inFIGS.1A and1B. InFIG.5H, the growth substrate565is flipped over so that the semiconductor layer530is on bottom and the growth substrate535is on top. InFIG.5I, the growth substrate565is bonded to the structure502to form a structure555, where the semiconductor layer530contacts the semiconductor layer520. The bonding process may be the same as or similar to the bonding process described above in conjunction withFIG.5D. InFIG.5J, the growth substrate535is removed from the structure555. Through the steps inFIGS.5G-5J, the semiconductor layer530is “transferred” from the growth substrate535to the semiconductor layer520, i.e., the target substrate. As a result, a structure504is formed. The structure504includes the substrate510and the semiconductor layers520and530.

FIGS.5K-5Oshows one more layer transfer process.FIG.5Kshows a growth substrate565, which may be the same as or similar to the growth substrate505. InFIG.5L, a semiconductor layer540is formed on the growth substrate565and a structure575is generated. The semiconductor layer540may be formed through a process that is the same as or similar to the process of forming the semiconductor layer520. The semiconductor layer540includes a semiconductor material, which may be the same as or different from the semiconductor material of the semiconductor layer520or530. The semiconductor layer540may be an embodiment of the second region140inFIGS.1A and1B. InFIG.5M, the structure575is flipped over so that the semiconductor layer540is on bottom and the growth substrate565is on top. InFIG.5N, the structure575is bonded to the structure504in a way such that the semiconductor layer540contact the semiconductor layer530. A structure585is formed. The bonding process may be the same as or similar to the bonding process described above in conjunction withFIG.5D. InFIG.5O, the growth substrate565is removed from the structure585. Through the steps inFIGS.5L-5O, the semiconductor layer530is “transferred” from the growth substrate565to the semiconductor layer530, i.e., the target substrate. As a result, a structure506is formed. The structure506includes the substrate510and the semiconductor layers520,530, and540.

InFIG.5P, an insulator550is formed. The insulator550wraps around the structure506. In the embodiment ofFIG.5P, the insulator550wraps around the whole structure506. In other embodiments, the insulator550wraps around a portion of the structure506, e.g., a portion of or the whole semiconductor layer530. The insulator550may be an embodiment of the gate insulator150inFIGS.1A and1B. In some embodiments, before the insulator550is formed, the structure506is changed and a new structure is formed. For instance, a portion of the semiconductor layer520,530, or540may be removed to change the shape of the structure506. The insulator550is formed to wrap around at least a portion of the new structure.

In some embodiments, the insulator550may be deposited using a conformal deposition process, such as ALD or CVD. Conformal deposition generally refers to deposition of a certain coating on any exposed surface of a given structure. A conformal coating may, therefore, be understood as a coating that is applied to exposed surfaces of a given structure, and not, for example, just to the vertical surfaces. In some embodiments, an annealing process may be carried out on the insulator550to improve the quality of the insulator550.

InFIG.5Q, an electrode560is formed and the vertical TFET500is generated. The electrode560wraps around a portion of the insulator550. In other embodiments, the electrode560may wrap around the whole insulator550. The electrode560is separated from some or all of the semiconductor layers520,530, and540by the insulator550. The electrode560may be an embodiment of the gate electrode160inFIGS.1A and1B.

The semiconductor layers520,530, and530of the vertical TFET500are stacked together through layer transfer processes, in which each semiconductor layer is first formed on a growth substrate and then transferred from the growth substrate to the target substrate. Such layer transfer processes can allow the integration of both lattice-matched and mismatched materials for enabling extended functionality and performance by assembling diverse materials or devices in a more compact space. The formation of a semiconductor layer (e.g., the semiconductor layer520,530, or540) may be an epitaxy process, such as one of the epitaxy processes described below in conjunction withFIGS.6A-6O. The epitaxy process includes an oriented crystal growth of the semiconductor material on the underlying substrate (e.g., the growth substrate505,535, or565). Accordingly, the crystal orientations of the semiconductor layer520,530, or540can be controlled separately by using different growth substrates.

The crystal orientation of the semiconductor layer can be determined by the growth substrate. For instance, the semiconductor layer can be formed through homoepitaxial growth if the semiconductor layer and the growth substrate have the same material. With homoepitaxial growth, the crystal structure of the semiconductor layer can match (e.g., identical or substantially identical to) the crystal structure of the growth substrate and the crystal orientation of the semiconductor layer can be aligned with the crystal orientation of the growth substrate, i.e., the two crystal orientations can be the same or substantially same. In embodiments where the semiconductor layers520,530, and540have the same material, the semiconductor layers520,530, and540can be formed on identical (or substantially identical) growth substrates (or the same growth substrate if not damaged when removed) and the semiconductor layers520,530, and540can have aligned crystal orientations. Even when the semiconductor layers520,530, and540have different materials, their crystal orientations can still be aligned by using different growth substrates. For instance, growth substrates having different materials but the same crystal orientation can be used to form the semiconductor layers520,530, and540. Each of the growth substate has the same material as the corresponding semiconductor layer so that the crystal orientation of the semiconductor layer will be aligned with the crystal orientation of the growth substrate. That way, the semiconductor layers520,530, and540will have aligned crystal orientations.

FIGS.6A-6Cillustrate an example process of forming a vertical TFET600through epitaxy, according to some embodiments of the disclosure. The epitaxy includes crystal growth of a semiconductor material on an underlying layer. The epitaxy may be a liquid phase epitaxy, a molecular beam epitaxy, a CVD epitaxy (e.g., metalorganic CVD epitaxy), etc.

FIG.6Ashows a structure605that includes a substrate610and semiconductor layers620and630. The semiconductor layer620is between the substrate610and semiconductor layer630. In some embodiments, the semiconductor layers620and630are formed through layer transfer, e.g., the layer transfer processes shown inFIGS.5A-5J. In other embodiments, the semiconductor layer620or630may be formed through epitaxy. Each of the semiconductor layers620and630includes a semiconductor material. The semiconductor materials of the semiconductor layers620and630may be the same or different. The semiconductor layer620may be an embodiment of the first region120,220, or320. The semiconductor layer630may be an embodiment of the channel region130,230, or330. The semiconductor layer630functions as the substrate of the epitaxy process.

FIG.6Bshows depositing a semiconductor material on a surface635of the semiconductor layer630. InFIG.6B, a spraying assembly615sprays a fluid625onto the surface635. The fluid625may be a gas, liquid, or supercritical fluid. The fluid625includes one or more precursors of the deposited semiconductor material. A precursor may include the semiconductor material or one or more chemical elements of the semiconductor material. The deposited semiconductor material may be formed through a chemical reaction between multiple precursors, chemical reaction between a precursor and a material on the surface635, chemical reaction between a precursor and a material in the environment (e.g., a deposition chamber), or some combination thereof. The deposited semiconductor material is different from the semiconductor material of the semiconductor layer630, i.e., the epitaxy inFIGS.6A-6Cis heteroepitaxy. The fluid625may also include other materials, such as an n-type or p-type dopant. The dopant in the fluid625is the opposite type from a dopant in the semiconductor layer620.

In some embodiments, the spraying of the fluid625is performed in a chamber. The chamber may provide a controlled environment with a predetermined temperature or pressure. For example, the chamber provides a vacuum environment (e.g., a pressure of 10-8-10-12Torr) to prevent contamination. As another example, the chamber has a temperature and pressures to maintain the phase of the precursor, which may be gas, liquid, or superfluid. In some embodiments, the chamber may include plasma that facilitates the spraying of the fluid625. For example, before the fluid625is sprayed onto the surface635, the surface635can be treated with plasma to make the surface635ready for the deposition, e.g., by removing contaminants from the surface635. As another example, the chamber can provide plasmas after the fluid625is sprayed onto the surface635. The plasma facilitates solidification or crystallization of the deposited semiconductor material on the surface635. In other embodiments, the solidification or crystallization can be done through radiation, heat, or other methods.

InFIG.6C, a semiconductor layer640is formed on the surface635. As the semiconductor material of the semiconductor layer640is different from the semiconductor material of the semiconductor layer630, the semiconductor layer640is formed through heteroepitaxial growth on the surface635. There can be a misalignment between the crystal structures (e.g., lattice mismatch) in the two semiconductor layers630and640, which may result in a tilted growth of the semiconductor layer640. As shown inFIG.6C, the crystal orientation645of the semiconductor layer640is different from the crystal orientation637of the semiconductor layer630.

The semiconductor layers620,630, and640constitute the semiconductor regions of the vertical TFET600, with the semiconductor layers620and640being the source and drain regions and the semiconductor layer630being the channel region. Dopants can be incorporated into the crystal structures of the semiconductor layers620,630, and640, e.g., through ion implantation. Even though not shown inFIGS.6A-6C, the vertical TFET600may also include a gate insulator and a gate electrode, which can be formed through the process described above in conjunction withFIGS.5P and5Q.

FIGS.7A-7Cillustrate an example process of forming a vertical TFET through graphoepitaxy, according to some embodiments of the disclosure. The graphoepitaxy includes crystal growth guided by a topographical guiding pattern in an underlying layer. The graphoepitaxy may be a liquid phase epitaxy, a molecular beam epitaxy, a CVD epitaxy (e.g., metalorganic CVD epitaxy), etc.

FIG.7Ashows a structure705that includes a substrate710and semiconductor layers720and730. The semiconductor layer720is between the substrate710and semiconductor layer730. In some embodiments, the semiconductor layers720and730are formed through layer transfer, e.g., the layer transfer processes shown inFIGS.5A-5J. In other embodiments, the semiconductor layer720or730may be formed through epitaxy. Each of the semiconductor layers720and730includes a semiconductor material. The semiconductor materials of the semiconductor layers720and730may be the same or different. The semiconductor layer720may be an embodiment of the first region120,220, or320. The semiconductor layer730may be an embodiment of the channel region130,230, or330. The semiconductor layer730functions as the substrate of the epitaxy process.

InFIG.7B, an opening735is formed in the semiconductor layer730. The opening735is formed at the surface733of the semiconductor layer730. The surface733is opposite the surface737, which contacts the semiconductor layer720. As shown inFIG.7B, a length of the opening735along the X-axis is shorter than the corresponding length of the semiconductor layer730. The opening735is wrapped around by a portion of the semiconductor material of the semiconductor layer730. The portion of the semiconductor material, which is enclosed in the dashed boxes inFIG.7B, constitutes the wall732of the opening735. The wall732has an orientation along the Z-axis. The bottom734of the opening735is surrounded by the wall732.

The opening735constitutes a topographical guiding pattern for the graphoepitaxy process. The topographical guiding pattern can direct crystal growth of semiconductors. For instance, the crystallization rate of a material along the orientation of the wall732(i.e., the Z-axis) is higher than the crystallization rate of the material in other directions. Accordingly, the opening735can promote growth of epitaxial layers along the Z-axis and inhibit growth of epitaxial layers in other directions.

FIG.7Balso shows that a spraying assembly715sprays a fluid745into the opening735to deposit a semiconductor material on the bottom734of the opening735. The fluid745may be a gas, liquid, or supercritical fluid. The fluid745includes one or more precursor of a semiconductor material. In some embodiments, the semiconductor material is different from the semiconductor material of the semiconductor layer730so that the graphoepitaxy is heteroepitaxy. The fluid745may also include a dopant, such as an n-type dopant or p-type dopant. The dopant in the fluid745is the opposite type from the dopant in the semiconductor layer720. In embodiments where the semiconductor layer730is doped, the dopant in the fluid745may be the same type as the dopant in the semiconductor layer730. The concentration of the dopant in the fluid745is higher than the concentration of the dopant in the semiconductor layer730. In some embodiments, the spraying of the fluid745can be performed in a chamber, such as the chamber described above in conjunction withFIG.6A.

InFIG.7C, a semiconductor layer740is formed. A portion of the semiconductor layer740is formed in the opening735. The rest of the semiconductor layer740is beyond the opening735. The formation of the semiconductor layer740is guided by the opening735so that the semiconductor layer740has a crystal orientation750along the Z-axis.

Despite that the semiconductor layers730and740have different materials, the crystal orientation750of the semiconductor layer740can be aligned with the crystal orientation of the semiconductor layer730(i.e., both crystal orientations are along the Z-axis) given the topographical guiding pattern constituted by the opening735. For instance, the crystal orientation of the semiconductor layer730is along the Z-axis and the opening735is formed based on the crystal orientation of the semiconductor layer730. In other embodiments, the semiconductor layer740can have different crystal orientations, e.g., by using topographical guiding patterns that are different from the opening735shown inFIG.7B.

The semiconductor layers720,730, and740constitute the semiconductor regions of the vertical TFET700, with the semiconductor layers720and740being the source and drain regions and the semiconductor layer730being the channel region. Dopants can be incorporated into the crystal structures of the semiconductor layers720,730, and740, e.g., through ion implantation. Even though not shown inFIGS.7A-6C, the vertical TFET700may also include a gate insulator and a gate electrode, which can be formed through the process described above in conjunction withFIGS.5P and5Q.

Even though not shown inFIGS.7A-7C, the semiconductor layers720and730can also be formed through graphoepitaxy. In an example, a gate insulator (e.g., the gate insulator150) can be formed on a substrate (e.g., the substrate110). The gate insulator can function as a topographical guiding pattern that directs the epitaxial growth of the semiconductor layers720and730along a longitudinal axis (e.g., along the Z-axis) of the gate insulator. The gate insulator can also be used to form a second region that is different from the semiconductor layer740, e.g., the second region140that has the same length along the X-axis as the first region120and the channel region130, through epitaxial growth. In another example, a gate insulator (e.g., the gate insulator450) can be formed on a first region (e.g., the first region420) and direct the epitaxial growth of a channel region (e.g., the channel region430) on the first region.

FIGS.8A-8Eillustrate an example process of forming a vertical TFET800through chemoepitaxy, according to some embodiments of the disclosure. The chemoepitaxy includes crystal growth guided by a chemical guiding pattern on an underlying layer. The graphoepitaxy may be a liquid phase epitaxy, a molecular beam epitaxy, a CVD epitaxy (e.g., metalorganic CVD epitaxy), etc.

FIG.8Ashows a structure805that includes a substrate810and semiconductor layers820. The semiconductor layer820is between the substrate810and semiconductor layer830. In some embodiments, the semiconductor layer820is formed through layer transfer, e.g., the layer transfer processes shown inFIGS.5A-5J. In other embodiments, the semiconductor layer820may be formed through epitaxial growth of a semiconductor material on the substrate810. The semiconductor layer820may be an embodiment of the first region120,220, or320.

The semiconductor layer820also functions as a growth substrate for a new semiconductor layer to be formed. In the embodiment ofFIG.8A, a seed layer825is formed on the semiconductor layer820. The seed layer825can function as a chemical guiding pattern for epitaxial growth on the semiconductor layer820and orient the crystal growth of the new semiconductor layer. For instance, the seed layer825can align a crystal orientation of the new semiconductor layer with a particular direction, e.g., the crystal orientation of the semiconductor layer820. In some embodiments, the seed layer825includes oriented grains of a material. The seed layer825may be formed by depositing a small amount of the material, heating the surface to form isolated oriented grains, and then using these grains as seeds for the deposition of an oriented layer. The seed layer825may have a thickness less than 1 µm.

InFIG.8B, a semiconductor layer830is formed on the semiconductor layer820. The formation of the semiconductor layer820is guided by the seed layer825so that the semiconductor layer820has an orientation837(e.g., a crystal orientation) along the Z-axis. In embodiments where the seed layer825includes oriented grains, the orientation837is aligned with the orientation of the grains in the seed layer825. The orientation of the grains in the seed layer825can be aligned with an orientation of the semiconductor layer820so that the semiconductor layer830can have the same orientation as the semiconductor layer820, even when the semiconductor layer830has a different material from the semiconductor layer820.

InFIG.8C, an opening835is formed in the semiconductor layer830. The opening835may be the same as or similar to the opening735inFIG.7B. The opening835can function as a topographical guiding pattern for the formation of a new layer on the semiconductor layer830. InFIG.8D, a seed layer845is formed in the opening835. The seed layer845is over the bottom surface of the opening835. Similar to the seed layer825, the seed layer845can function as a chemical guiding pattern for epitaxial growth on the semiconductor layer830and orient the crystal growth of the new semiconductor layer. The seed layer845may include grains oriented along a particular direction, e.g., the Z-axis. The opening835and the seed layer845constitute a mixed guiding pattern that include both the topographical guiding pattern and the chemical guiding pattern.

InFIG.8E, a semiconductor layer840is formed. A portion of the semiconductor layer840is formed in the opening835. The rest of the semiconductor layer840is beyond the opening835. The formation of the semiconductor layer840is guided by the mixed guiding pattern. Despite that the semiconductor layers830and840may have different materials, the crystal orientation847of the semiconductor layer840can be aligned with the orientation837of the semiconductor layer830(i.e., both crystal orientations are along the Z-axis) due to the mixed guiding pattern.

The semiconductor layers820,830, and840constitute the semiconductor regions of the vertical TFET800, with the semiconductor layers820and840being the source and drain regions and the semiconductor layer830being the channel region. Dopants can be incorporated into the crystal structures of the semiconductor layers820,830, and840, e.g., through ion implantation. Even though not shown inFIGS.8A-6C, the vertical TFET800may also include a gate insulator and a gate electrode, which can be formed through the process described above in conjunction withFIGS.5P and5Q.

Even though not shown inFIGS.8A-8E, the semiconductor layers820and830can also be formed through epitaxial growth directed by mixed guiding patterns. In an example, a gate insulator (e.g., the gate insulator150) can be formed on the semiconductor layer820. The gate insulator can function as a topographical guiding pattern that further directs the epitaxial growth of the semiconductor layer730. Similarly, the semiconductor layer820can be formed through epitaxial growth directed by mixed guiding patterns based on a gate insulator formed on the substrate810(which can function as a topographical guiding pattern) and a seed layer formed on the substrate810and wrapped around by the gate insulator (which functions as a chemical guiding pattern). The gate insulator can also be used to form a second region that is different from the semiconductor layer840, e.g., the second region140that has the same length along the X-axis as the first region120and the channel region130, through epitaxial growth.

Example Methods of Forming IC Devices

FIG.9is a flowchart showing a method900forming an IC device, in accordance with various embodiments. In some embodiments, the method900includes instructions that are stored in one or more non-transitory computer-readable media and are executable by a processing device, e.g., the processing device2402inFIG.14. Although the method900is described with reference to the flowchart illustrated inFIG.9, many other methods for forming IC devices may alternatively be used. For example, the order of execution of the steps inFIG.9may be changed. As another example, some of the steps may be changed, eliminated, or combined.

The method900includes providing (e.g., forming)910a first region over a substrate with a first semiconductor material and dopants of a first type. The method900also includes providing920a channel region over the first region. The channel region includes a semiconductor material. The semiconductor material may be different from the first semiconductor material. A surface of the channel region contacts a surface of the first region. The surface of the channel region may have the same size as the surface of the first region or may be smaller than the surface of the first region.

In some embodiments, the channel region is formed through layer transfer. For instance, the channel region is formed over a substrate, which generates a combined structure that includes the channel region and the substrate. The combined structure is bonded with the first region with the channel region contacting the first region. Then the substrate is removed. In other embodiments, the channel region is formed through epitaxy. For instance, a precursor of the semiconductor material is sprayed onto a surface of the first region. The channel region is formed from the precursor. The surface of the first region may be treated with a guiding material before the precursor is sprayed. An affinity of the precursor to the guiding material is stronger than the affinity of the precursor to the first semiconductor material.

The method900also includes providing930a second region at least partially over the channel region with a second semiconductor material and dopants of a second type. The second semiconductor material may be different from the first semiconductor material, the semiconductor material, or both. The second type is different from the first type. In an example, the first type is p-type and the second type is n-type. In another example, the first type is n-type and the second type is p-type. The first region and the second region constitute a pair of a source region and a drain region. The second region may be formed by layer transfer, epitaxy, or other methods. In an example, a mixture of a precursor of the second semiconductor material and dopants of the second type is sprayed onto a surface of the channel region to form the second region. In some embodiments, a guiding pattern is formed at a surface of the channel region and the second region is formed over the channel region based on the guiding pattern. The guiding pattern may include an opening that is formed in the channel region at a surface of the channel region. A precursor of the second semiconductor material (or a mixture of the precursor and dopants of the second type) is sprayed into the opening to form the second region. At least a portion of the second region is wrapped around by the channel region. The guiding pattern may further include a guiding pattern in the opening. The precursor or mixture has a stronger affinity to the guiding material than to the semiconductor material.

The method900also includes providing940a gate insulator that wraps around at least a portion of the channel region. The gate insulator may be formed with a dielectric material, such as an oxide material, a hysteretic material (e.g., a ferroelectric or an antiferroelectric material), or other materials. The method900further includes providing950a gate electrode that wraps around at least a portion of the gate insulator. The gate electrode is formed by an electrically conductive material, e.g., metal.

FIG.10is a flowchart showing another method of forming an IC device, in accordance with various embodiments. In some embodiments, the method1000includes instructions that are stored in one or more non-transitory computer-readable media and are executable by a processing device, e.g., the processing device2402inFIG.14. Although the method1000is described with reference to the flowchart illustrated inFIG.10, many other methods for providing forming IC devices may alternatively be used. For example, the order of execution of the steps inFIG.10may be changed. As another example, some of the steps may be changed, eliminated, or combined.

The method1000includes providing1010an opening in an insulator over a substrate. In some embodiments, the opening is formed through etching, e.g., dry etching. The opening may be a trench. The method1000further includes1020providing a first layer in the opening. The first layer includes a first semiconductor material. The method1000further includes doping1030the first layer with dopants of a first type. The first type may be p-type or n-type. In some embodiments, the first layer can be formed by spraying a precursor of the first semiconductor material into the opening. In an embodiment, a mixture of the precursor and dopants of the first type is sprayed into the opening to form the doped first layer. The first layer may be formed through graphoepitaxial growth on the substrate and the opening can function as a topographical guiding pattern for the graphoepitaxial growth.

The method1000further includes providing1040a second layer (i.e., L2) over a first layer, the second layer comprising a second semiconductor material. The second semiconductor material may be different from the first semiconductor material. In some embodiments, the second layer is formed through graphoepitaxial growth on the first layer in the opening and the opening can function as a topographical guiding pattern for the graphoepitaxial growth. The first layer and at least a portion of the second layer is wrapped around by the insulator.

The method1000further includes providing a third layer1050over the second layer. The third layer includes a third semiconductor material, which may be different from the first semiconductor material, the second semiconductor material, or both. In an embodiment, the second layer is formed through graphoepitaxial growth on the second layer in the opening in the insulator and the opening in the insulator can function as a topographical guiding pattern for the graphoepitaxial growth. In another embodiment, another opening is formed in the second layer. The third layer can be formed in the opening in the second layer, e.g., through graphoepitaxial growth. The opening in the second layer can function as a topographical guiding pattern for the graphoepitaxial growth.

The method1000also includes doping1060the third layer with dopants of a second type. The second type is different from (e.g., opposite) the first type. In an embodiment, the first type is n-type and the second type is p-type. In another example, the first type is p-type and the second type is n-type. In some embodiments, at least a portion of the third layer is wrapped around by the insulator. In some embodiments, an electrode is formed. The electrode wraps around at least a portion of the insulator.

Example Wafer and Die

FIGS.11A-11Bare top views of a wafer2000and dies2002that may include one or more vertical TFETs, according to some embodiments of the disclosure. In some embodiments, the dies2002may be included in an IC package. For example, any of the dies2002may serve as any of the dies2256in an IC package2200shown inFIG.12. The wafer2000may be composed of semiconductor material and may include one or more dies2002having IC devices formed on a surface of the wafer2000. Each of the dies2002may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more vertical TFETs as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more vertical TFETs as described herein), the wafer2000may undergo a singulation process in which each of the dies2002is separated from one another to provide discrete “chips” of the semiconductor product. In particular, devices that include one or more vertical TFETs as disclosed herein may take the form of the wafer2000(e.g., not singulated) or the form of the die2002(e.g., singulated). The die2002may include one or more diodes, one or more transistors (e.g., one or more vertical TFETs as described herein) as well as, optionally, supporting circuitry to route electrical signals to the III-N diodes with n-doped wells and capping layers and III-N transistors, as well as any other IC components. In some embodiments, the wafer2000or the die2002may implement an electrostatic discharge (ESD) protection device, an RF FE device, a memory device (e.g., a static random-access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die2002.

Example IC Package

FIG.12is a side, cross-sectional view of an example IC package2200that may include one or more IC devices having vertical TFETs, according to some embodiments of the disclosure. In some embodiments, the IC package2200may be a system-in-package (SiP).

As shown inFIG.12, the IC package2200may include a package substrate2252. The package substrate2252may be formed of a dielectric material (e.g., a ceramic, a glass, a combination of organic and inorganic materials, a buildup film, an epoxy film having filler particles therein, etc., and may have embedded portions having different materials), and may have conductive pathways extending through the dielectric material between the face2272and the face2274, or between different locations on the face2272, and/or between different locations on the face2274.

The package substrate2252may include conductive contacts2263that are coupled to conductive pathways2262through the package substrate2252, allowing circuitry within the dies2256and/or the interposer2257to electrically couple to various ones of the conductive contacts2264(or to other devices included in the package substrate2252, not shown).

The IC package2200may include an interposer2257coupled to the package substrate2252via conductive contacts2261of the interposer2257, first-level interconnects2265, and the conductive contacts2263of the package substrate2252. The first-level interconnects2265illustrated inFIG.12are solder bumps, but any suitable first-level interconnects2265may be used. In some embodiments, no interposer2257may be included in the IC package2200; instead, the dies2256may be coupled directly to the conductive contacts2263at the face2272by first-level interconnects2265.

The IC package2200may include one or more dies2256coupled to the interposer2257via conductive contacts2254of the dies2256, first-level interconnects2258, and conductive contacts2260of the interposer2257. The conductive contacts2260may be coupled to conductive pathways (not shown) through the interposer2257, allowing circuitry within the dies2256to electrically couple to various ones of the conductive contacts2261(or to other devices included in the interposer2257, not shown). The first-level interconnects2258illustrated inFIG.12are solder bumps, but any suitable first-level interconnects2258may be used. As used herein, a “conductive contact” may refer to a portion of electrically conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

In some embodiments, an underfill material2266may be disposed between the package substrate2252and the interposer2257around the first-level interconnects2265, and a mold compound2268may be disposed around the dies2256and the interposer2257and in contact with the package substrate2252. In some embodiments, the underfill material2266may be the same as the mold compound2268. Example materials that may be used for the underfill material2266and the mold compound2268are epoxy mold materials, as suitable. Second-level interconnects2270may be coupled to the conductive contacts2264. The second-level interconnects2270illustrated inFIG.12are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects 22770 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects2270may be used to couple the IC package2200to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference toFIG.13.

The dies2256may take the form of any of the embodiments of the die2002discussed herein and may include any of the embodiments of an IC device having one or more vertical TFETs. In embodiments in which the IC package2200includes multiple dies2256, the IC package2200may be referred to as a multi-chip package. Importantly, even in such embodiments of an MCP implementation of the IC package2200, one or more vertical TFETs may be provided in a single chip, in accordance with any of the embodiments described herein. The dies2256may include circuitry to perform any desired functionality. For example, one or more of the dies2256may be ESD protection dies, including one or more vertical TFETs as described herein, one or more of the dies2256may be logic dies (e.g., silicon-based dies), one or more of the dies2256may be memory dies (e.g., high bandwidth memory), etc. In some embodiments, any of the dies2256may include one or more vertical TFETs, e.g., as discussed above; in some embodiments, at least some of the dies2256may not include any III-N diodes with n-doped wells and capping layers.

The IC package2200illustrated inFIG.12may be a flip chip package, although other package architectures may be used. For example, the IC package2200may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package2200may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies2256are illustrated in the IC package2200ofFIG.12, an IC package2200may include any desired number of the dies2256. An IC package2200may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face2272or the second face2274of the package substrate2252, or on either face of the interposer2257. More generally, an IC package2200may include any other active or passive components known in the art.

Example IC Device

FIG.13is a cross-sectional side view of an IC device assembly2300that may include components having one or more IC devices implementing vertical TFETs, according to some embodiments of the disclosure. The IC device assembly2300includes a number of components disposed on a circuit board2302(which may be, e.g., a motherboard). The IC device assembly2300includes components disposed on a first face2340of the circuit board2302and an opposing second face2342of the circuit board2302; generally, components may be disposed on one or both faces2340and2342. In particular, any suitable ones of the components of the IC device assembly2300may include any of the IC devices implementing one or more vertical TFETs in accordance with any of the embodiments disclosed herein; e.g., any of the IC packages discussed below with reference to the IC device assembly2300may take the form of any of the embodiments of the IC package2200discussed above with reference toFIG.12(e.g., may include one or more vertical TFETs in/on a die2256).

The IC device assembly2300illustrated inFIG.13includes a package-on-interposer structure2336coupled to the first face2340of the circuit board2302by coupling components2316. The coupling components2316may electrically and mechanically couple the package-on-interposer structure2336to the circuit board2302, and may include solder balls (e.g., as shown inFIG.13), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure2336may include an IC package2320coupled to an interposer2304by coupling components2318. The coupling components2318may take any suitable form for the application, such as the forms discussed above with reference to the coupling components2316. The IC package2320may be or include, for example, a die (the die2002ofFIG.11B), an IC device (e.g., the IC device ofFIGS.1-2), or any other suitable component. In particular, the IC package2320may include one or more vertical TFETs as described herein. Although a single IC package2320is shown inFIG.13, multiple IC packages may be coupled to the interposer2304; indeed, additional interposers may be coupled to the interposer2304. The interposer2304may provide an intervening substrate used to bridge the circuit board2302and the IC package2320. Generally, the interposer2304may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer2304may couple the IC package2320(e.g., a die) to a BGA of the coupling components2316for coupling to the circuit board2302. In the embodiment illustrated inFIG.13, the IC package2320and the circuit board2302are attached to opposing sides of the interposer2304; in other embodiments, the IC package2320and the circuit board2302may be attached to a same side of the interposer2304. In some embodiments, three or more components may be interconnected by way of the interposer2304.

The interposer2304may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer2304may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer2304may include metal interconnects2308and vias2310, including but not limited to TSVs2306. The interposer2304may further include embedded devices2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD protection devices, and memory devices. More complex devices such as further RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer2304. In some embodiments, the IC devices implementing one or more vertical TFETs as described herein may also be implemented in/on the interposer2304. The package-on-interposer structure2336may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly2300may include an IC package2324coupled to the first face2340of the circuit board2302by coupling components2322. The coupling components2322may take the form of any of the embodiments discussed above with reference to the coupling components2316, and the IC package2324may take the form of any of the embodiments discussed above with reference to the IC package2320.

The IC device assembly2300illustrated inFIG.13includes a package-on-package structure2334coupled to the second face2342of the circuit board2302by coupling components2328. The package-on-package structure2334may include an IC package2326and an IC package2332coupled together by coupling components2330such that the IC package2326is disposed between the circuit board2302and the IC package2332. The coupling components2328and2330may take the form of any of the embodiments of the coupling components2316discussed above, and the IC packages2326and2332may take the form of any of the embodiments of the IC package2320discussed above. The package-on-package structure2334may be configured in accordance with any of the package-on-package structures known in the art.

Example Computing Device

FIG.14is a block diagram of an example computing device2400that may include one or more components including one or more vertical TFETs in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device2400may include a die (e.g., the die2002(FIG.11B)) having one or more vertical TFETs. Any one or more of the components of the computing device2400may include, or be included in, an IC device2200(FIG.12). Any one or more of the components of the computing device2400may include, or be included in, an IC device assembly2300(FIG.13).

A number of components are illustrated inFIG.14as included in the computing device2400, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device2400may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the computing device2400may not include one or more of the components illustrated inFIG.14, but the computing device2400may include interface circuitry for coupling to the one or more components. For example, the computing device2400may not include a display device2412, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device2412may be coupled. In another set of examples, the computing device2400may not include an audio input device2416or an audio output device2414, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device2416or audio output device2414may be coupled.

In some embodiments, the communication chip2406may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip2406may include multiple communication chips. For instance, a first communication chip2406may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip2406may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip2406may be dedicated to wireless communications, and a second communication chip2406may be dedicated to wired communications.

The computing device2400may include a battery/power circuitry2410. The battery/power circuitry2410may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device2400to an energy source separate from the computing device2400(e.g., AC line power).

The computing device2400may include a display device2412(or corresponding interface circuitry, as discussed above). The display device2412may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device2400may include an audio output device2414(or corresponding interface circuitry, as discussed above). The audio output device2414may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device2400may include an audio input device2416(or corresponding interface circuitry, as discussed above). The audio input device2416may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device2400may include an other output device2418(or corresponding interface circuitry, as discussed above). Examples of the other output device2418may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The computing device2400may include a GPS device2422(or corresponding interface circuitry, as discussed above). The GPS device2422may be in communication with a satellite-based system and may receive a location of the computing device2400, as known in the art.

The computing device2400may include a security interface device2424. The security interface device2424may include any device that provides security features for the computing device2400or for any individual components therein (e.g., for the processing device2402or for the memory2404). Examples of security features may include authorization, access to digital certificates, access to items in keychains, etc. Examples of the security interface device2424may include a software firewall, a hardware firewall, an antivirus, a content filtering device, or an intrusion detection device.

In some embodiments, the computing device2400may include a temperature detection device2426and a temperature regulation device2428.

The temperature detection device2426may include any device capable of determining temperatures of the computing device2400or of any individual components therein (e.g., temperatures of the processing device2402or of the memory2404). In various embodiments, the temperature detection device2426may be configured to determine temperatures of an object (e.g., the computing device2400, components of the computing device2400, devices coupled to the computing device, etc.), temperatures of an environment (e.g., a data center that includes, is controlled by, or otherwise associated with the computing device2400), and so on. The temperature detection device2426may include one or more temperature sensors. Different temperature sensors of the temperature detection device2426may have different locations within and around the computing device2400. A temperature sensor may generate data (e.g., digital data) representing detected temperatures and provide the data to another device, e.g., to the temperature regulation device2428, the processing device2402, the memory2404, etc. In some embodiments, a temperature sensor of the temperature detection device2426may be turned on or off, e.g., by the processing device2402or an external system. The temperature sensor detects temperatures when it is on and does not detect temperatures when it is off. In other embodiments, a temperature sensor of the temperature detection device2426may detect temperatures continuously and automatically or detect temperatures at predefined times or at times triggered by an event associated with the computing device2400or any components therein.

The temperature regulation device2428may include any device configured to change (e.g., decrease) temperatures, e.g., based on one or more target temperatures and/or based on temperature measurements performed by the temperature detection device2426. A target temperature may be a preferred temperature. A target temperature may depend on a setting in which the computing device2400operates. In some embodiments, the target temperature may be 200 Kelvin degrees or lower. In some embodiments, the target temperature may be 20 Kelvin degrees or lower, or 5 Kelvin degrees or lower. Target temperatures for different objects and different environments of, or associated with, the computing device2400can be different. In some embodiments, cooling provided by the temperature regulation device2428may be a multi-stage process with temperatures ranging from room temperature to 4 K or lower.

In some embodiments, the temperature regulation device2428may include one or more cooling devices. Different cooling device may have different locations within and around the computing device2400. A cooling device of the temperature regulation device2428may be associated with one or more temperature sensors of the temperature detection device2426and may be configured to operate based on temperatures detected the temperature sensors. For instance, a cooling device may be configured to determine whether a detected ambient temperature is above the target temperature or whether the detected ambient temperature is higher than the target temperature by a predetermined value or determine whether any other temperature-related condition associated with the temperature of the computing device2400is satisfied. In response to determining that one or more temperature-related condition associated with the temperature of the computing device2400are satisfied (e.g., in response to determining that the detected ambient temperature is above the target temperature), a cooling device may trigger its cooling mechanism and start to decrease the ambient temperature. Otherwise, the cooling device does not trigger any cooling. A cooling device of the temperature regulation device2428may operate with various cooling mechanisms, such as evaporation cooling, radiation cooling, conduction cooling, convection cooling, other cooling mechanisms, or any combination thereof. A cooling device of the temperature regulation device2428may include a cooling agent, such as a water, oil, liquid nitrogen, liquid helium, etc. In some embodiments, the temperature regulation device2428may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator. In some embodiments, the temperature regulation device2428or any portions thereof (e.g., one or more of the individual cooling devices) may be connected to the computing device2400in close proximity (e.g., less than about 1 meter) or may be provided in a separate enclosure where a dedicated heat exchanger (e.g., a compressor, a heating, ventilation, and air conditioning (HVAC) system, liquid helium, liquid nitrogen, etc.) may reside.

By maintaining the target temperatures, the energy consumption of the computing device2400(or components thereof) can be reduced, while the computing efficiency may be improved. For example, when the computing device2400(or components thereof) operates at lower temperatures, energy dissipation (e.g., heat dissipation) may be reduced. Further, energy consumed by semiconductor components (e.g., energy needed for switching transistors of any of the components of the computing device2400) can also be reduced. Various semiconductor materials may have lower resistivity and/or higher mobility at lower temperatures. That way, the electrical current per unit supply voltage may be increased by lowering temperatures. Conversely, for the same current that would be needed, the supply voltage may be lowered by lowering temperatures. As energy corelates to the supply voltage, the energy consumption of the semiconductor components may lower too. In some implementations, the energy savings due to reducing heat dissipation and reducing energy consumed by semiconductor components of the computing device or components thereof may outweigh (sometimes significantly outweigh) the costs associated with energy needed for cooling.

FIG.15is a block diagram of an example processing device2500that may include one or more vertical TFETs in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the processing device2500may include a die (e.g., the die2002(FIG.11B)) having one or more vertical TFETs. Any one or more of the components of the processing device2500may include, or be included in, an IC device2200(FIG.12). Any one or more of the components of the processing device2500may include, or be included in, an IC device assembly2300(FIG.13). Any one or more of the components of the processing device2500may include, or be included in, a computing device2400(FIG.14); for example, the processing device2500may be the processing device2402of the computing device2400.

A number of components are illustrated inFIG.15as included in the processing device2500, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the processing device2500may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SoC die or coupled to a single support structure, e.g., to a single carrier substrate.

Additionally, in various embodiments, the processing device2500may not include one or more of the components illustrated inFIG.15, but the processing device2500may include interface circuitry for coupling to the one or more components. For example, the processing device2500may not include a memory2504, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a memory2504may be coupled.

The processing device2500may include logic circuitry2502(e.g., one or more circuits configured to implement logic/compute functionality). Examples of such circuits include ICs implementing one or more of input/output (I/O) functions, arithmetic operations, pipelining of data, etc.

In some embodiments, the logic circuitry2502may include one or more circuits responsible for read/write operations with respect to the data stored in the memory2504. To that end, the logic circuitry2502may include one or more I/O ICs configured to control access to data stored in the memory2504.

In some embodiments, the logic circuitry2502may include one or more high-performance compute dies, configured to perform various operations with respect to data stored in the memory2504(e.g., arithmetic and logic operations, pipelining of data from one or more memory dies of the memory2504, and possibly also data from external devices/chips). In some embodiments, the logic circuitry2502may be configured to only control I/O access to data but not perform any operations on the data. In some embodiments, the logic circuitry2502may implement ICs configured to implement I/O control of data stored in the memory2504, assemble data from the memory2504for transport (e.g., transport over a central bus) to devices/chips that are either internal or external to the processing device2500, etc. In some embodiments, the logic circuitry2502may not be configured to perform any operations on the data besides I/O and assembling for transport to the memory2504.

The processing device2500may include a memory2504, which may include one or more ICs configure to implement memory circuitry (e.g., ICs implementing one or more of memory devices, memory arrays, control logic configured to control the memory devices and arrays, etc.). In some embodiments, the memory2504may be implemented substantially as described above with reference to the memory2404(FIG.14). In some embodiments, the memory2504may be a designated device configured to provide storage functionality for the components of the processing device2500(i.e., local), while the memory2404may be configured to provide system-level storage functionality for the entire computing device2400(i.e., global). In some embodiments, the memory2504may include memory that shares a die with the logic circuitry2502.

In some embodiments, the memory2504may include a flat memory (also sometimes referred to as a “flat hierarchy memory” or a “linear memory”) and, therefore, may also be referred to as a “basin memory.” As known in the art, a flat memory or a linear memory refers to a memory addressing paradigm in which memory may appear to the program as a single contiguous address space, where a processor can directly and linearly address all of the available memory locations without having to resort to memory segmentation or paging schemes. Thus, the memory implemented in the memory2504may be a memory that is not divided into hierarchical layer or levels in terms of access of its data.

In some embodiments, the memory2504may include a hierarchical memory. In this context, hierarchical memory refers to the concept of computer architecture where computer storage is separated into a hierarchy based on features of memory such as response time, complexity, capacity, performance, and controlling technology. Designing for high performance may require considering the restrictions of the memory hierarchy, i.e., the size and capabilities of each component. With hierarchical memory, each of the various memory components can be viewed as part of a hierarchy of memories (m1, m2, ..., mn) in which each member miis typically smaller and faster than the next highest member mi+1of the hierarchy. To limit waiting by higher levels, a lower level of a hierarchical memory structure may respond by filling a buffer and then signaling for activating the transfer. For example, in some embodiments, the hierarchical memory implemented in the memory2504may be separated into four major storage levels: 1) internal storage (e.g., processor registers and cache), 2) main memory (e.g., the system RAM and controller cards), and 3) on-line mass storage (e.g., secondary storage), and 4) off-line bulk storage (e.g., tertiary, and off-line storage). However, as the number of levels in the memory hierarchy and the performance at each level has increased over time and is likely to continue to increase in the future, this example hierarchical division provides only one non-limiting example of how the memory2504may be arranged.

The processing device2500may include a communication device2506, which may be implemented substantially as described above with reference to the communication chip2406(FIG.14). In some embodiments, the communication device2506may be a designated device configured to provide communication functionality for the components of the processing device2500(i.e., local), while the communication chip2406may be configured to provide system-level communication functionality for the entire computing device2400(i.e., global).

The processing device2500may include interconnects2508, which may include any element or device that includes an electrically conductive material for providing electrical connectivity to one or more components of, or associated with, a processing device2500or/and between various such components. Examples of the interconnects2508include conductive lines/wires (also sometimes referred to as “lines” or “metal lines” or “trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”), metallization stacks, redistribution layers, metal-insulator-metal (MIM) structures, etc.

The processing device2500may include a temperature detection device2510which may be implemented substantially as described above with reference to the temperature detection device2426(FIG.14) but configured to determine temperatures on a more local scale, i.e., of the processing device2500of components thereof. In some embodiments, the temperature detection device2510may be a designated device configured to provide temperature detection functionality for the components of the processing device2500(i.e., local), while the temperature detection device2426may be configured to provide system-level temperature detection functionality for the entire computing device2400(i.e., global).

The processing device2500may include a temperature regulation device2512which may be implemented substantially as described above with reference to the temperature regulation device2428(FIG.14) but configured to regulate temperatures on a more local scale, i.e., of the processing device2500of components thereof. In some embodiments, the temperature regulation device2512may be a designated device configured to provide temperature regulation functionality for the components of the processing device2500(i.e., local), while the temperature regulation device2428may be configured to provide system-level temperature regulation functionality for the entire computing device2400(i.e., global).

The processing device2500may include a battery/power circuitry2514which may be implemented substantially as described above with reference to the battery/power circuitry2410(FIG.14). In some embodiments, the battery/power circuitry2514may be a designated device configured to provide battery/power functionality for the components of the processing device2500(i.e., local), while the battery/power circuitry2410may be configured to provide system-level battery/power functionality for the entire computing device2400(i.e., global).

The processing device2500may include a hardware security device2516which may be implemented substantially as described above with reference to the security interface device2424(FIG.14). In some embodiments, the hardware security device2516may be a physical computing device configured to safeguard and manage digital keys, perform encryption and decryption functions for digital signatures, authentication, and other cryptographic functions. In some embodiments, the hardware security device2516may include one or more secure cryptoprocessors chips.

Select Examples

Example 1 provides an IC device, including: a substrate; a first region, including a first semiconductor material with dopants of a first type; a second region, including a second semiconductor material with dopants of a second type, the second type different from the first type; and a channel region, including a third semiconductor material, where: the channel region is between the first region and the second region, the first region is between the channel region and the substrate, one of the first region and the second region is a source region of a transistor, and another one of the first region and the second region is a drain region of the transistor.

Example 2 provides the IC device according to example 1, further including: a gate wrapping around at least a portion of the channel region, where a longitudinal axis of the gate is orthogonal to the substrate.

Example 3 provides the IC device according to example 2, where the gate includes: a gate insulator wrapping around at least a portion of the channel region; and a gate electrode wrapping around at least a portion of the gate insulator.

Example 4 provides the IC device according to any of the preceding examples, where the dopants of the first type are n-type dopants and the dopants of the second type are p-type dopants.

Example 5 provides the IC device according to any of the preceding examples, where the first semiconductor material is different from the second semiconductor material or the third semiconductor material.

Example 6 provides the IC device according to any of the preceding examples, where the first semiconductor material, the second semiconductor material, and the third semiconductor material are the same.

Example 7 provides the IC device according to any of the preceding examples, where the first region incudes a first crystal structure, the second region includes a second crystal structure, and a crystal orientation of the first crystal structure is unaligned with a crystal of the second crystal structure.

Example 8 provides the IC device according to any of the preceding examples, where the channel region includes a first crystal structure, the second region includes a second crystal structure, and a crystal orientation of the first crystal structure is unaligned with a crystal of the second crystal structure.

Example 9 provides the IC device according to any of the preceding examples, where a portion of the second region is wrapped around by the channel region.

Example 10 provides the IC device according to any of the preceding examples, where a surface of the first region is connected with a surface of the channel region, and an area of the surface of the first region is smaller than an area of the surface of the channel region.

Example 11 provides a method for forming an IC device, the method including: providing a first region over a substrate, the first region including a first semiconductor material with dopants of a first type; providing a channel region over the first region; providing a second region at least partially over the channel region, the second region including a second semiconductor material with dopants of a second type, where the second type is different from the first type; providing a gate insulator that wraps around at least a portion of the channel region; and providing a gate electrode that wraps around at least a portion of the gate insulator.

Example 12 provides the method according to example 11, where providing the channel region over the first region includes: providing the channel region over a substrate to form a combined structure; and bonding the combined structure with the first region; and removing the substrate.

Example 13 provides the method according to example 11 or 12, where providing the channel region over the first region includes: providing a precursor of a semiconductor material of the channel region onto a surface of the first region.

Example 14 provides the method according to any one of examples 11-13, where providing the second region at least partially over the channel region includes: providing a mixture of a precursor of the second semiconductor material and the dopants of the second type onto a surface of the channel region.

Example 15 provides the method according to example 14, where providing the second region at least partially over the channel region further includes: providing a guiding pattern at a surface of the channel region, the guiding pattern including an opening in the channel region, where providing the mixture of the precursor of the second semiconductor material and the dopants of the second type onto the surface of the channel region includes providing the mixture into the opening.

Example 16 provides the method according to example 15, where providing the mixture into the opening includes: providing a guiding material into the opening, where the guiding material includes oriented grains; and providing the mixture onto the guiding material.

Example 17 provides the method according to any one of examples 11-16, where providing the channel region over the first region includes: providing a guiding material onto a surface of the first region, where the guiding material includes oriented grains; and providing the semiconductor material onto the guiding material.

Example 18 provides a method for forming an IC device, including: providing an opening in an insulator over a substrate; providing a first layer in the opening, the first layer including a first semiconductor material; doping the first layer with dopants of a first type; providing a second layer over a first layer, the second layer including a second semiconductor material; providing a third layer over the second layer, the third layer including a third semiconductor material; and doping the third layer with dopants of a second type, where the second type is different from the first type, and where the first layer and at least a portion of the second layer are wrapped around by the insulator.

Example 19 provides the method according to example 18, further including: forming an electrode that wraps around at least a portion of the insulator.

Example 20 provides the method according to example 18, where providing the third layer over the second layer and doping the third layer with the dopants of the second type include spraying a mixture of a precursor of the third semiconductor material and the dopants of the second type onto a surface of the second layer.

Example 21 provides an IC package, including the IC device according to any one of examples 1-10; and a further IC component, coupled to the IC device.

Example 22 provides the IC package according to example 21, where the further IC component includes one of a package substrate, an interposer, or a further IC die.

Example 23 provides the IC package according to example 21 or 22, where the IC device according to any one of examples 1-10 may include, or be a part of, at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.

Example 24 provides an electronic device, including a carrier substrate; and one or more of the IC devices according to any one of examples 1-10 and the IC package according to any one of examples 21-23, coupled to the carrier substrate.

Example 25 provides the electronic device according to example 24, where the carrier substrate is a motherboard.

Example 26 provides the electronic device according to example 24, where the carrier substrate is a PCB.

Example 27 provides the electronic device according to any one of examples 24-26, where the electronic device is a wearable electronic device or handheld electronic device.

Example 28 provides the electronic device according to any one of examples 24-27, where the electronic device further includes one or more communication chips and an antenna.

Example 29 provides the electronic device according to any one of examples 24-28, where the electronic device is an RF transceiver.

Example 30 provides the electronic device according to any one of examples 24-28, where the electronic device is one of a switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, or a downconverter of an RF communications device, e.g., of an RF transceiver.

Example 31 provides the electronic device according to any one of examples 24-30, where the electronic device is a computing device.

Example 32 provides the electronic device according to any one of examples 24-31, where the electronic device is included in a base station of a wireless communication system.

Example 33 provides the electronic device according to any one of examples 24-31, where the electronic device is included in a user equipment device of a wireless communication system.

Example 34 provides the method according to any one of examples 11-20, further including processes for forming the IC device according to any one of examples 1-10.

Example 35 provides the method according to any one of examples 11-20, further including processes for forming the IC package according to any one of the examples 21-23.

Example 36 provides the method according to any one of examples 11-20, further including processes for forming the electronic device according to any one of the examples 24-31.