Semiconductor device adapted to minimize clock skew

A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-271919, filed Sep. 17, 2004, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device which has two or more system modules which operate in synchronization with a clock signal and more specifically to a semiconductor device which is adapted to compensate for skew in the clock signal which drives the system modules.

2. Description of the Related Art

Conventionally, a system on silicon chip (SoC) includes two or more system modules different in computing function. These system modules are interconnected by a system bus for data communications among them. Further, the system modules are each controlled by an interrupt control signal produced by another module.

Suppose, for example, that there are a first system module which processes audio data and a second system module which processes image data. Then, the first and second system modules will be different in computing speed. In general, audio data is smaller in data amount than image data; therefore, it is not required for the audio data processing first system module to have a computing speed higher than that in the image data processing second system module. In addition, in some cases there is no need to process audio data while image data is being processed. That is, although the second system module needs to be placed in the operating state at all times, the first system module may be placed in the standby state. For this reason, the second system module is directly supplied with an external supply voltage VCC, but the first system module is supplied, as required, with an internal voltage VINT lower than the external supply voltage VCC.

The first and second system modules are supplied with an external common clock signal CLK. The first and second system modules each contain a logic circuit section, which includes two or more flip-flop and latch circuits. These circuits are clocked by the clock signal. If the arrival times of the clock signal at the flip-flop and latch circuits are displaced, that is, if there is a skew in the clock signals, data in the flip-flop and latch circuits cannot be transferred correctly. This causes malfunction of the logic circuit section.

In general, the timing of change of data with respect to change of the clock signal is designed with setup and hold time margins added. If skew in the clock signals in the whole system exceeds the setup and hold time margins, malfunction of the logic circuit section is caused. For this reason, buffer circuits or delay elements are inserted in paths over which the clock signal propagates in order to make uniform the arrival times of the clock signal at the flip-flop and latch circuits even if the lines over which the clock signal are propagated differ in length and load capacitance.

As described above, the internal voltage VINT applied to the audio data processing first system module is set lower than the external supply voltage VCC. The internal voltage VINT is produced by a stepdown circuit embedded in a chip. Depending on the operating conditions of the stepdown circuit, the internal voltage VINT may vary. The operating conditions of the stepdown circuit include temperature, process conditions, and the value of current dissipated by the first system module. When the internal voltage VINT is high, the propagation speed of the clock signal in the first system module increases and vice versa.

In general, skew in two or more clock signals which are driven with different supply voltages is greater than that in clock signals driven with the same supply voltage. For this reason, a problem arises in that skew in the clock signal in the whole system will increase according to variations in the internal voltage VINT.

As a related technique, there is a technique which provides two or more zones on an integrated circuit with clock buffers adapted to delay a reference clock signal in time and involves comparing zone clock signals output from the clock buffers in adjacent zones through a phase comparator and controlling the amount of delay introduced by the clock buffer in a particular zone according to a control signal produced by the phase comparator (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2001-274341).

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a first logic circuit which has its supply voltage controlled; a second logic circuit which operates in response to an external clock signal; an adjustment circuit including a detection circuit and a first delay circuit supplied with the external clock signal, the detection circuit detecting a skew between timings of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit and the adjustment circuit adjusting the delay time of the first delay circuit according to the result of the detection by the detection circuit and applying an output signal of the first delay circuit to the first logic circuit as a third clock signal.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a first logic circuit which has its supply voltage controlled and outputs a first clock signal; a second logic circuit which outputs a second clock signal; a first adjustment circuit including a first detection circuit and a first delay circuit supplied with an external clock signal, the first detection circuit detecting a skew between timings of the first clock signal output from the first logic circuit and a reference clock signal and the adjustment circuit adjusting the delay time of the first delay circuit according to the result of the detection by the first detection circuit and applying an output signal of the first delay circuit to the first logic circuit as a third clock signal; and a second adjustment circuit including a second detection circuit and a second delay circuit supplied with the external clock signal, the detection circuit detecting a skew between timings of the second clock signal output from the second logic circuit and the reference clock signal and the second adjustment circuit adjusting the delay time of the second delay circuit according to the result of the detection by the second detection circuit and applying an output signal of the second delay circuit to the second logic circuit as a fourth clock signal.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 and 2illustrate a first embodiment of the present invention. As shown inFIG. 1, a one-chip SoC device, indicated generally at11, has first and second system modules12and13having different computing functions, a system bus14, an I/O circuit15, a power supply circuit16, and a delay adjustment circuit17. The first system module12, which is a logic circuit section adapted to process audio data by way of example, includes logic circuits composed of flip-flop and latch circuits not shown. The second system module13, which is a logic circuit section adapted to process image data by way of example, includes logic circuits composed of flip-flop and latch circuits not shown. The computing speed of the first system module12is set lower than that of the second system module13. The first and second system modules12and13are interconnected by the system bus14over which data communications can be made between the modules. Further, each of the first and second system modules12and13is controlled by an interrupt control signal produced by the other.

The second system module13is directly supplied with an external supply voltage VCC and an external clock signal CLK. The second system module13is operated from the external supply voltage VCC and the external clock signal CLK. The first system module12is supplied with an internal supply voltage VINT from the power supply circuit16and a clock signal CLKA from the delay adjustment circuit17. The power supply circuit16, which is comprised of, for example, a stepdown circuit, lowers the external supply voltage VCC according to a computing speed control signal SP to produce the internal supply voltage VINT.

That is, when it is required to make the computing power of the first system module12relatively high, the power supply circuit16is controlled so that the interval voltage VINT is raised. Specifically, the power supply circuit is controlled so that the internal voltage VINT becomes approximately equal to the supply voltage VCC. When the computing power of the first system module12is allowed to be relatively low, on the other hand, the power supply circuit16is controlled so that the interval voltage VINT falls below the supply voltage VCC. Specifically, the power supply circuit is controlled so that the internal voltage VINT becomes lower than the supply voltage VCC by, for example, at least 200 mV.

The delay adjustment circuit17detects a skew (displacement) between timings of a clock signal CLK1from the first system module12and a clock signal CLK2from the second system module13and adjusts the delay time of the external clock signal CLK accordingly to produce the clock signal CLKA. That is, the delay adjustment circuit17detects the phase or time difference between the clock signals CLK1and CLK2from the first and second system modules12and13and controls the delay time of the external clock signal CLK according to the detected phase or time difference so that skew in the clock signals CLK1and CLK2is minimized.

When the internal voltage VINT output from the power supply circuit16is controlled according to the computing speed control signal SP as described above, the propagation speed of the clock signal in the first system module12varies, causing the time interval between the moment that the clock signal CLKA is applied to the first system module12and the moment that the clock signal CLK1is output to vary. However, when the clock signal CLK1varies, the delay time in the delay adjustment circuit17is adjusted so that the clock signals CLK1and CLK2are always in phase with each other.

FIG. 2shows an example of the delay adjustment circuit17. This delay adjustment circuit17is composed of a phase comparator21and a delay circuit22. The phase comparator21makes a comparison in phase between the clock signals CLK1and CLK2. As the result of comparison, when the clock signal CLK1is advanced in phase with respect to the clock signal CLK2, the phase comparator21outputs a control signal to introduce a long delay time in the delay circuit22. Consequently, the delay circuit22outputs the clock signal CLKA which has been delayed by a long time interval with respect to the external clock signal CLK. Thereby, the phase of the clock signal CLK1is delayed, causing the clock signals CLK1and CLK2to become in phase with each other.

As the result of the comparison by the phase comparator21, on the other hand, when the clock signal CLK1is delayed in phase with respect to the clock signal CLK2, the phase comparator21outputs a control signal to shorten the delay time in the delay circuit22. Consequently, the delay circuit22outputs the clock signal CLKA which has been delayed by a short time interval with respect to the external clock signal CLK. Thereby, the phase of the clock signal CLK1is advanced, so that it becomes in phase with the clock signal CLK2.

According to the first embodiment, the phase comparator21detects the phase difference between the clock signal CLK1output from the first system module12and the clock signal CLK2output from the second system module13and the delay circuit22controls the phase of the external clock signal CLK according to the detected phase difference to output the clock signal CLKA. For this reason, even in the event that the operating conditions and drive voltage of the first system module12have changed, the clock skew in the first and second system modules12and13can be minimized. It therefore becomes possible to improve the setup/hold characteristics for data communications between the first and second system modules12and13.

Moreover, the delay adjustment circuit17optimizes the amount of delay one or two clock cycles later, thus allowing the clock skew to be improved at high speed.

FIG. 3illustrates a second embodiment of the present invention, which is another example of the delay adjustment circuit17in the first embodiment.

The delay adjustment circuit17shown inFIG. 3is composed of delay circuits31and32and a time difference measurement circuit33. The delay circuit31delays the clock signal CLK2output from the second system module13in accordance with a delay time select signal (DTSS) from the time difference measurement circuit33to output a clock signal CLKX. The time difference measurement circuit33measures the time difference between the clock signal CLKX from the delay circuit31and the clock signal CLK1from the first system module12to output the signal DTSS. The delay circuit32delays the external clock signal CLK in accordance with the signal DTSS from the time difference measurement circuit33to output the clock signal CLKA.

FIG. 4illustrates the operating principle of the delay adjustment circuit17shown inFIG. 3. The clock signal CLKA output from the delay circuit32is delayed in time by tA with respect to the external clock signal CLK. The clock signal CLKA is applied to the first system module12and propagates through flip-flop and latch circuits in the first system module, so that it is delayed. The clock signal CLK1output from the first system module12is delayed in time by t1with respect to the clock signal CLKA. Therefore, the time tY by which the clock signal CLK1is delayed with respect to the clock signal CLK is given by
tY=tA+t1

On the other hand, the second system module13is directly supplied with the external clock signal CLK. The external clock signal is delayed in time by t2by the second system module13and then output as the clock signal CLK2. In the second embodiment, the clock signal CLK2is applied to the delay circuit31, then delayed by the same time tA as with the delay circuit32and output as the clock signal CLKX. The time tX by which the clock signal CLKX is delayed with respect to the clock signal CLK is given by
tX=t2+tA

The time difference measurement circuit33measures the time difference between the clock signal CLK1and the clock signal CLKX. The time difference tX−tY measured by the time difference measurement circuit33is given by
tX−tY=(t2+tA)−(tA+t1)=t2−t1
That is, the ideal value, t2−t1, of the delay time in the delay circuit when the clock signals CLK1and CLK2coincide in phase with each other is measured regardless of the value of tA used within one cycle. By using the measured time tA′ as the delay time tA for the external clock signal CLK in the next cycle, the skew in the clock signals CLK1and CLK2can be minimized.

FIG. 5illustrates an exemplary arrangement of the delay circuits31and32. The delay circuit is constructed from a plurality of unit delay elements51connected in parallel between its input and output terminals. Each unit delay element is composed of a NAND circuit Ai, an inverter circuit Bi, and a NAND circuit Ci. In each unit delay element, one input of the NAND circuit Ci is connected to the input terminal through inverter circuits52and53and the other input is connected to receive the delay time select signal DTSS. The output of the NAND circuit Ci is connected to one input of the NAND circuit Ai, and the other input is connected to the output of the inverter circuit Bi+1 of the immediately succeeding unit delay element. The output of the NAND circuit Ai is connected through the inverter circuit Bi to the other input of the NAND circuit Ai−1 in the immediately preceding unit delay element. The output of the inverter circuit B1in the unit delay element adjacent to the output terminal is connected to the output terminal through an inverter circuit54.

In the delay circuits31and32thus configured, the number of unit delay elements51which are connected in parallel is controlled by the delay time select signal DTSS from the time difference measuring circuit33, whereby a delay time is set. When the logic levels of bits of the delay time select signal DTSS which are applied to the NAND circuits C1, C2, Ci−1, Ci, Ci+1 are “LLHLL” as shown inFIG. 5, only the NAND circuit Ci−1 is enabled, i.e., the (i−1)st unit delay element is selected. Thus, the input clock signal passes through the selected unit delay element and then propagates through the NAND circuit and the inverter circuit in each of the preceding unit delay elements in sequence. Thus, the more unit delay elements the clock signal passes through, the longer the delay time becomes, and vice versa.

The unit delay time per stage can be increased by inserting a buffer between the NAND circuit Ai and the inverter circuit Bi. A measure of unit delay time per stage is less than half of the system skew accuracy. That is, in order to set the skew accuracy of the whole system to less than one nanosecond by way of example, the unit delay time should be set to less than 500 picoseconds. The reason is that, since the skew in the clock signals CLK1and CLK2is reduced by adjusting the time difference between the clock signal CLK and the clock signal CLKA through the delay circuit, the skew in the whole system cannot be reduced unless the unit delay time, i.e., the accuracy of the delay circuit, is less than half of the system skew accuracy.

FIG. 6shows an exemplary arrangement of the time difference measurement circuit33. This time difference measurement circuit33has first and second input terminals IN1and IN2and measures the time interval between the moment that a pulse signal at a high level is applied to the first input terminal IN1and the moment that the second input terminal IN2goes to the high level. To this end, the first input terminal IN1is connected through inverter circuits62and63to two or more unit delay elements61. The arrangement of the unit delay element61is the same as that of the unit delay element51shown inFIG. 5except input signals to NAND circuits Fi. That is, each unit delay element61is composed of NAND circuits Fi and Di and an inverter circuit Ei. One input of the NAND circuit Fi is connected to the output terminal of the inverter circuit63, and the output is connected to one input of the NAND circuit Di. The other input of the NAND circuit Di is connected to the output terminal of the inverter circuit of the immediately preceding unit delay element. The output terminal of the NAND circuit Di is connected through the inverter circuit Ei to the input terminal of the AND circuit Di+1 of the immediately succeeding unit delay element.

The potential at the other input terminal of the NAND circuit F1in the first-stage unit delay element is set to the high level (supply voltage VCC). The potential at the other input terminal of each of the other NAND circuits F2, Fi, Fi+1 set to the low level (ground potential VSS). Therefore, when a clock signal at high level is applied to the first input terminal IN1, it is conducted through the inverter circuits62and63to the other input of the NAND circuit F1, causing its output to go low. Subsequently, upon the lapse of a delay time set by the NAND circuit D1and inverter circuit E1, the output of the inverter circuit E1goes low. The pulse signal passes through the NAND circuit D2and the inverter circuit E2in the succeeding unit delay element. Thus, the output of the inverter in each of the unit delay elements goes low in sequence with time.

The output terminal of the inverter circuit Ei in each unit delay element is connected to the input terminal D of a corresponding latch circuit Li. The input terminal GN of each latch circuit Li is connected to the second input terminal IN2through inverter circuits64and65. The output terminal Q of each latch circuit Li is connected to one input of a corresponding NOR circuit Gi, the other input terminal of which is connected through an inverter circuit Hi to the output terminal Q of the succeeding latch circuit Li+1. The latch circuit Li outputs the level at the input terminal D when the input terminal GN goes from low to high level to the output terminal Q and holds it.

In the time difference measurement circuit thus configured, when a clock signal at high level is applied to the second input terminal IN2, the output state of the inverter Ei is latched by the corresponding latch circuit Li. That is, in a state where the pulse signal has passed through the i-th unit delay element, the outputs of the inverter circuits E1through Ei−1 have gone low and the outputs of the succeeding inverter circuits Ei and Ei+1 have gone high. When, in this state, the potential at the second input terminal IN2goes high, the outputs of the latch circuits Li through Li−1 go low and the outputs of the succeeding latch circuits Li and Li+1 go high. Thus, only the i-1th delay time select signal DTSS is made high through the NOR circuit Gi−1 connected to the output Q of the latch circuit Li−1 and the inverter circuit Hi−1.

According to the second embodiment, the time difference measurement circuit33measures the time difference between the clock signal CLK1output from the first system module12and the clock signal CLK2output from the second system module13and the delay circuit32delays the external clock signal CLK according to the detected time difference to output the clock signal CLKA for driving the first system module12. For this reason, even in the event that the operating conditions and drive voltage of the first system module12have changed, the clock skew in the clock signals of the first and second system modules12and13can be minimized. It therefore becomes possible to improve the setup/hold characteristics for data communications between the first and second system modules12and13.

Moreover, the delay adjustment circuit17optimizes the amount of delay one clock cycle later, thus allowing the clock skew to be improved at high speed.

FIG. 7shows a modification of the delay circuit according to the second embodiment. InFIG. 7, corresponding parts to those inFIG. 5are denoted by like reference numerals and only different parts will be described. It is desirable that each unit delay element comprising the delay circuit and each unit delay element comprising the time difference measurement circuit33have the same delay time. However, the output terminal of each unit delay element comprising the time difference measurement circuit33is connected to a latch circuit. The capacitive load of this latch circuit will make the unit delay element in the time difference measurement circuit33different in delay time from the unit delay element in the delay circuit31,32.

As shown inFIG. 7, the output terminal of each unit delay element comprising the delay circuit is connected to a capacitive load equivalent to the latch circuit. That is, the output terminals of the inverter circuits B1to Bi+1 are connected to the input terminals of inverter circuits X1to Xi+1,respectively. The output terminal of each of the inverter circuits X1to Xi+1 is made open.

According to the arrangement shown inFIG. 7, the delay time of each unit delay element in the delay circuit31,32can be made equal to that in the time difference measurement circuit33. For this reason, skew in the clock signals CLK1and CLK2can be further reduced.

As another modification, an inverter circuit, similar to Xi inFIG. 7, may be inserted between the output of each inverter circuit Ei and the input of the corresponding latch circuit Li in the time difference measurement circuit33ofFIG. 6, thereby allowing each unit delay element in the time difference measurement circuit and the delay circuits31and32to have exactly the same capacitive load.

In the second embodiment, the output signals of the respective unit delay elements are held through the use of latch circuits corresponding in number to the delay elements. Further, flip-flop circuits may be combined for an application in which the output signals of the respective unit delay elements are held for two or more cycles and averaged.

The result of the time difference measurement circuit33obtained in one cycle may be used two cycles later, not for the delay time in the next cycle.

The use of such modifications will allow the time difference between the clock signals CLK1and CLK2to be measured more accurately.

FIG. 8shows a third embodiment of the present invention. In the first and second embodiments, the delay adjustment circuit17makes a comparison between the clock signals CLK1and CLK2supplied from the first and second system modules12and13. In the first and second embodiments, only the clock signal from the first system module is controlled. In contrast to the first and second embodiments, in the third embodiment, a reference clock signal is produced inside the chip, the phase or time difference between each of the clock signals CLK1and CLK2and the reference clock signal is detected, and clock signals applied to the first and second modules12and13are controlled accordingly.

That is, inFIG. 8, a reference clock signal generating circuit81is provided in the SoC device11. The reference clock generating circuit81produces a reference clock signal CLKS from the external clock signal CLK. The reference clock signal CLKS is a clock signal in which the time required for clock signals to propagate in two or more system modules is standardized, for example, a clock signal which has the average delay time of clock signals in two or more system modules. First and second delay adjustment circuits17-1and17-2are provided for the first and second system modules12and13, respectively. The first and second delay adjustment circuits17-1and17-2may be configured as shown inFIGS. 9 and 10, which correspond toFIGS. 2 and 3, respectively.

When the first delay adjustment circuit17-1is configured as shown inFIG. 9, the phase comparator21makes a comparison in phase between the clock signal CLK1from the first system module12and the reference clock signal CLKS from the reference clock generator81. The delay circuit22delays the external clock signal CLK according to the result of the comparison by the phase comparator21and produces the clock signal CLKA for driving the first system module12.

With the second delay adjustment circuit17-2configured as shown inFIG. 9, the phase comparator21makes a comparison in phase between the clock signal CLK2from the second system module13and the reference clock signal CLKS. The delay circuit22delays the external clock signal CLK according to the result of comparison by the phase comparator21to produce the clock signal CLKB for driving the second system module13.

With the first delay adjustment circuit17-1configured as shown inFIG. 10, on the other hand, the delay circuit31delays the reference clock signal CLKS under control of the time difference measurement circuit33. The time difference measurement circuit33measures the time difference between the clock signal CLKX from the delay circuit31and the clock signal CLK1from the first system module12. The delay circuit32delays the external clock signal CLK according to the measurement by the time difference measurement circuit33to produce the clock signal CLKA for driving the first system module12.

With the second delay adjustment circuit17-2configured as shown inFIG. 10, the delay circuit31delays the reference clock signal CLKS under control of the time difference measurement circuit33. The time difference measurement circuit33measures the time difference between the clock signal CLKX from the delay circuit31and the clock signal CLK2from the second system module13. The delay circuit32delays the external clock signal CLK according to the measurement by the time difference measurement circuit33to produce the clock signal CLKB for driving the second system module13.

According to the third embodiment, the first delay adjustment circuit17-1measures the phase or time difference between the clock signal CLK1from the first system module12and the reference clock signal CLKS and outputs the clock signal CLKA to drive the first system module accordingly. For this reason, skew in the clock signals CLK1and CLKS can be minimized. The second delay adjustment circuit17-2measures the phase or time difference between the clock signal CLK2from the second system module13and the reference clock signal CLKS and outputs the clock signal CLKB to drive the second system module accordingly. For this reason, skew in the clock signals CLK2and CLKS can be minimized. Thus, since each of the clock signals CLK1and CLK2is minimized in skew with respect to the reference clock signal CLKS, skew in the clock signals CLK1and CLK2can also be minimized. Even in the event of a change in the operating state or drive voltage of the first system module12, therefore, clock skew in the whole system can be maintained minimum and the operating margin of flip-flop and latch circuits contained in the first and second system modules12and13can be secured.

Although, in the third embodiment, skew in clock signals for two system modules is adjusted, this is not restrictive. It is also possible to adjust skew in clock signals for three or more system modules.

Although only the operating voltage of the first system module12is adjusted by the power supply circuit16, two or more modules may have their respective operating voltages adjusted by the power supply circuit. Moreover, the operating voltage produced by the power supply circuit16may vary with the system operating state.

However, since the delay adjustment circuits17-1and17-2optimize the amount of delay one cycle later, it is not desirable that the operating voltage changes abruptly and consequently the propagation time of the clock signal in the system module changes greatly with each clock cycle. For this reason, when the system skew accuracy is, say, one nanosecond, it is recommended that the voltage be changed so that the propagation time of the clock signal will not vary more than 500 picoseconds per cycle. In addition, when the system skew accuracy is 200 picoseconds, it is desirable that a change in the clock signal propagation time per cycle be less than 100 picoseconds.

FIG. 11shows a fourth embodiment of the present invention which is a modification of the third embodiment. In the third embodiment, the reference clock generating circuit81is incorporated into the SoC device11and each of the first and second delay adjustment circuits17-1and17-2adjusts the delay time introduced into the transmission of the external clock signal CLK on the basis of the phase or time difference between the reference clock signal CLKS from the reference clock generating circuit and a corresponding one of the clock signals CLK1and CLK2from the first and second system modules12and13.

Unlike the third embodiment, in the fourth embodiment, the reference clock signal generating circuit is omitted. Each of the first and second delay adjustment circuits17-1and17-2adjusts the delay time introduced into the transmission of the external clock signal CLK on the basis of the phase or time difference between the external clock signal CLK as the reference clock signal and a corresponding one of the clock signals CLK1and CLK2from the first and second system modules12and13.

The fourth embodiment can also provide the same advantages as the third embodiment.