Analog circuit with improved layout for mismatch optimization

Embodiments include a semiconductor device comprising: a substrate; a first transistor formed on the substrate; and a second transistor formed on the substrate, wherein a common region of the semiconductor device forms (i) a drain region of the first transistor, and (ii) a source region of the second transistor, and wherein a gate region of the first transistor is electrically coupled to a gate region of the second transistor.

TECHNICAL FIELD

Embodiments of the present disclosure relate to analog circuits, and in particular to optimizing mismatch between various components of an analog circuit.

BACKGROUND

Two substantially similar semiconductor components (e.g., two transistors) having substantially similar dimensions and configurations can have mismatch (e.g., a small difference in threshold voltages of the two transistors), for example, due to random manufacturing variability. Mismatch between various components in a semiconductor device can deteriorate the performance of the semiconductor device.

FIG. 1Aschematically illustrates a conventional current mirror100comprising transistors Ta, Tb and Tc. In the current mirror100, a source of each of the transistors Ta, Tb and Tc is coupled to a supply voltage Vpdd. The gate of the transistors Ta, Tb and Tc are coupled to each other. Furthermore, the gate of the transistor Ta is coupled to a drain of the transistor Ta. A current Ipref output by the transistor Ta is mirrored as currents Ipouta and Ipoutb, respectively, through transistors Tb and Tc. For the currents Ipouta and Ipoutb to substantially mirror the current Iref, each of the transistors Tb and Tc have to be substantially matched to the transistor Ta.

FIG. 1Bschematically illustrates a top view of the transistors Ta, Tb and Tc ofFIG. 1A; andFIG. 1Cschematically illustrates a cross sectional view of the transistors Ta, Tb and Tc. As illustrated inFIGS. 1B and 1C, the transistor Ta has a gate region14a, a source region16a1and a drain region16a2formed on an N-well12a. Also illustrated inFIG. 1Cis a pocket implant region20a(e.g., comprising N-type pocket implant dopants) formed near the source and drain regions of the transistor Ta. The transistors Tb and Tc have similar components as that of the transistor Ta.

The gate regions14a,14band14cof the transistors Ta, Tb and Tc may have substantially similar dimensions (e.g., to reduce mismatch between the transistors). For example, inFIG. 1B, each of the gate regions14a,14band14cof the transistors Ta, Tb and Tc have a length L and a width W.

Mismatch between the transistors Ta, Tb and Tc may be reduced, for example, by employing a relatively large width and/or large length of each of the transistors Ta, Tb and Tc. However, it may not always be feasible to employ a relatively large width and/or large length for the transistors Ta, Tb and Tc.

In a semiconductor device (e.g., especially in a semiconductor device in which the well or the substrate gets relatively lightly doped or almost undoped), a mismatch between various components is based on, for example, fluctuations of pocket implant dosage. As an example, a standard deviation of mismatch between threshold voltages of the transistors Ta, Tb and Tc is substantially proportional to an inverse of square root of an average number of dopants in the pocket implant regions of the transistors Ta, Tb and Tc. However, as illustrated inFIG. 1C, each of the transistors Ta, Tb and Tc has relatively few pocket implants. For example, dopants in the pocket implant region20aof transistor Ta is relatively low, compared to dimensions of the transistor Ta. Such low amount of dopants in the pocket implant regions may result in an increased mismatch between the transistors Ta, Tb and Tc, thereby deteriorating the performance of the current mirror100.

SUMMARY

In various embodiments, the present disclosure provides a semiconductor device comprising: a substrate; a first transistor formed on the substrate; and a second transistor formed on the substrate, wherein a common region of the semiconductor device forms (i) a drain region of the first transistor, and (ii) a source region of the second transistor, and wherein a gate region of the first transistor is electrically coupled to a gate region of the second transistor. In an embodiment, a pocket implant region is formed on an edge of the common region; and the pocket implant region comprises pocket implant dopants. In an embodiment, a first region forms a source region of the first transistor; and a second region forms a drain region of the second transistor. In an embodiment, the common region is a first common region, and wherein the semiconductor device further comprises: a third transistor formed on the substrate, wherein a second common region of the semiconductor device forms (i) a drain region of the second transistor, and (ii) a source region of the third transistor, and wherein the gate region of the second transistor is electrically coupled to a gate region of the third transistor. In an embodiment, the gate region of the first transistor is electrically coupled to the gate region of the second transistor via a metal layer. In an embodiment, the first transistor and the second transistor are coupled in series. In an embodiment, the gate region of the first transistor has a first dimension and a second dimension; the gate region of the second transistor has a third dimension and a fourth dimension; the first dimension is substantially equal to the third dimension; the second dimension is substantially equal to the fourth dimension; and the first dimension and the third dimension are selected such that a sum of the first dimension and the third dimension is substantially equal to a pre-defined dimension. In an embodiment, the first transistor and the second transistor functionally operate as a single transistor. In an embodiment, each of the first transistor and the second transistor are metal oxide semiconductor field effect transistors (MOSFET).

In various embodiments, the present disclosure provides a method of forming a semiconductor device, the method comprising: forming a substrate; forming a first transistor on the substrate; and forming a second transistor on the substrate, wherein a common region of the semiconductor device forms (i) a drain region of the first transistor, and (ii) a source region of the second transistor, and wherein a gate region of the first transistor is electrically coupled to a gate region of the second transistor. In an embodiment, the method further comprises: forming a pocket implant region on an edge of the common region, wherein the pocket implant region comprises pocket implant dopants. In an embodiment, a first region forms a source region of the first transistor; and a second region forms a drain region of the second transistor. In an embodiment, the common region is a first common region, and wherein the method further comprises: forming a third transistor on the substrate, wherein a second common region of the semiconductor device forms (i) a drain region of the second transistor, and (ii) a source region of the third transistor, and wherein the gate region of the second transistor is electrically coupled to a gate region of the third transistor. In an embodiment, the gate region of the first transistor is electrically coupled to the gate region of the second transistor via a metal layer. In an embodiment, the first transistor and the second transistor are coupled in series. In an embodiment, the gate region of the first transistor has a first dimension and a second dimension; the gate region of the second transistor has a third dimension and a fourth dimension; the first dimension is substantially equal to the third dimension; the second dimension is substantially equal to the fourth dimension; and the method further comprises selecting the first dimension and the third dimension such that a sum of the first dimension and the third dimension is substantially equal to a pre-defined dimension. In an embodiment, the first transistor and the second transistor functionally operate as a single transistor. In an embodiment, each of the first transistor and the second transistor are metal oxide semiconductor field effect transistors (MOSFET).

DETAILED DESCRIPTION

In an embodiment, the transistors Tp1, Tp2and Tp3are connected in series (henceforth also referred to as “a series of transistors”), such that a source of the transistor Tp1is coupled to a voltage source Vdd, a drain of the transistor Tp1is coupled to a source of the transistor Tp2, a drain of the transistor Tp2is coupled to a source of the transistor TP3, and a drain of the transistor Tp3is coupled to a current source Is that supplies a current Iref. A gate of the transistor Tp1is coupled to the gates of each of the transistors Tp2and Tp3. Furthermore, the drain of the transistor Tp3is coupled to the gates of each of the transistors Tp1, Tp2and Tp3.

The transistors Tq1, Tq2and Tq3are also connected in series, such that a source of the transistor Tq1is coupled to the voltage source Vdd, a drain of the transistor Tq1is coupled to a source of the transistor Tq2, a drain of the transistor Tq2is coupled to a source of the transistor Tq3, and a drain of the transistor Tq3outputs a current Iout1. A gate of the transistor Tq1is coupled to the gates of each of the transistors Tq2and Tq3. Furthermore, the gates of the transistors Tq1, Tq2and Tq3are coupled to the gates of the transistors Tp1, Tp2and Tp3, as illustrated inFIG. 2A.

The transistors Tr1, Tr2and Tr3are also connected in series in a manner that is similar to the connection of the transistors Tq1, Tq2and Tq3illustrated inFIG. 2A.

In an embodiment, the current Iref output by the transistor Tp3is mirrored as currents Iout1and Iout2, respectively, by the transistors Tq3and Tr3, as illustrated inFIG. 2A. For example, each of the currents Iout1and the current Iout2is substantially equal to the current Iref.

In an embodiment, the series of transistors Tp1, Tp2and Tp3is functionally equivalent to a single transistor Tp. For example, from a functional point of view, the transistors Tp1, Tp2and Tp3can be replaced by the single transistor Tp.

Similarly, from functional point of view, the transistors Tq1, Tq2and Tq3can be replaced by a corresponding single transistor Tq; and the transistors Tr1, Tr2and Tr3can be replaced by a corresponding single transistor Tr.

FIG. 2Bschematically illustrates a top view of the transistors Tp1, Tp2and Tp3of the current mirror200ofFIG. 2A; andFIG. 2Cschematically illustrates a cross sectional view of the transistors Tp1, Tp2and Tp3of the current mirror200ofFIG. 2A. Although the transistors illustrated inFIGS. 2A-2Care P channel metal oxide semiconductor field effect (PMOS) transistors, the transistors can be of any other appropriate type (e.g., NMOS transistors). AlthoughFIG. 2Aillustrates the current Iref being mirrored as two currents Iout1and Iout2(i.e., the current mirror200including three series of transistors), in another embodiment, the current Iref may be mirrored as any different number of currents (i.e., the current mirror200may comprise any different number of mirrored paths, and any corresponding different number of series of transistors). AlthoughFIGS. 2A-2Cillustrate three corresponding transistors being coupled in a series of transistors (e.g., transistors Tp1, Tp2and Tp3being coupled in series), any different number of transistors (e.g., two, four, etc.) may also be coupled in a corresponding series of transistors.

As illustrated inFIGS. 2B and 2C, the transistors Tp1, Tp2and Tp3are formed on an N type substrate (e.g., N well212p). The transistor Tp1has a corresponding gate region214p1. A region216pa, which is formed on the N-well212pand is doped with P type dopants, forms a source region of the transistor Tp1. A region216pb, which is formed on the N-well212pand is doped with P type dopants, forms a drain region of the transistor Tp1.

The transistor Tp2has a corresponding gate region214p2. Furthermore, the region216pbalso forms a source region for the transistor Tp2. Thus, the region216pbis a common region for both the transistors Tp1and Tp2. A region216pc, which is formed on the N-well212pand is doped with P type dopants, forms a drain region of the transistor Tp2.

The transistor Tp3has a corresponding gate region214p3. Furthermore, the region216pcalso forms a source region for the transistor Tp3. Thus, the region216pcis a common region for both the transistors Tp2and Tp3. A region216pd, which is formed on the N-well212pand is doped with P type dopants, forms a drain region of the transistor Tp3.

In an embodiment and although not illustrated inFIGS. 2B and 2C, the gate regions214p1,214p2and241p3of the transistors Tp1, Tp2and Tp3are coupled to each other. For example, the gate regions214p1,214p2and241p3are coupled via one or more metal layers, conductive traces, and/or the like.

Also illustrated inFIG. 2Care pocket implant regions220pformed near or on the edges of the regions216pa,216pb,216pcand216pd. In an embodiment, the pocket implant regions220pcomprise N-type pocket implants or N type dopants.

In an embodiment, each of the gate regions214p1,214p2and214p3has a width of W1, and the gate regions214p1,214p2and214p3have lengths L1, L2and L3, respectively. In an embodiment, the lengths L1, L2and L3are substantially similar.

Although not illustrated inFIGS. 2B-2C, the series of transistors Tq1, Tq2, Tq3is structurally similar to the series of transistors Tp1, Tp2, Tp3; and the series of transistors Tr1, Tr2, Tr3is structurally similar to the series of transistors Tp1, Tp2, Tp3. For example, the transistors Tq1, Tq2, Tq3have structures that are substantially similar to the structures of the transistors Tp1, Tp2, Tp3, respectively, as illustrated inFIGS. 2B and 2C. Accordingly, the structures of the series of transistors Tp1, Tp2, Tp3, and the series of transistors Tr1, Tr2, Tr3are not illustrated separately in the figures.

As previously discussed, the series of transistors Tp1, Tp2and Tp3is functionally equivalent to a single transistor Tp. For example, from a functional point of view, the transistors Tp1, Tp2and Tp3can be replaced by the single transistor Tp. In an example, a sum of the lengths L1, L2and L3of the transistors Tp1, Tp2and Tp3(i.e., an effective length of a gate of the functionally equivalent transistor Tp) is substantially equal to a predefined length. For example, if the transistors Tp1, Tp2and Tp3of the current mirror200ofFIG. 2Aare to replace the single transistor Ta of the current mirror100ofFIG. 1A, then sum of the lengths L1, L2and L3of the transistors Tp1, Tp2and Tp3, for example, is substantially equal to the length L of the transistor Ta.

Replacing the transistor Ta in the current mirror100ofFIGS. 1A-1Cwith the three transistors Tp1, Tp2and Tp3in the current mirror200ofFIGS. 2A-2Chas several advantages. For example, (i) the gate length of the transistor Ta and (ii) the effective gate length of the transistors Tp1, Tp2and Tp3are substantially similar. However, the transistor Ta has pocket implant regions20aformed near the regions16a1and16a2. In contrast, in the transistors Tp1, Tp2and Tp3, pocket implant regions220pare formed near regions216pa,216pb,216pcand216pd. Thus, a number of dopants in the pocket implant regions220pof the series of transistors Tp1, Tp2, Tp3is relatively higher than a number of dopants in the pocket implant regions20pof the transistor Ta. Thus, although the transistor Ta is functionally similar to the series of transistors Tp1, Tp2, Tp3, the series of transistors Tp1, Tp2, Tp3has a higher number of dopants in the pocket implant regions220pcompared to that in the transistor Ta. Similarly, although the transistor Tb is functionally similar to the series of transistors Tq1, Tq2, Tq3, the series of transistors Tq1, Tq2, Tq3has a higher number of dopants in corresponding pocket implant regions compared to that in the transistor Tb. Similarly, although the transistor Tc is functionally similar to the series of transistors Tr1, Tr2, Tr3, the series of transistors Tr1, Tr2, Tr3has a higher number of dopants in corresponding pocket implant regions compared to that in the transistor Tc.

Increasing a number of dopants in pocket implant regions of two transistors results in a decrease in a standard deviation of a mismatch between threshold voltages of the two transistors. Thus, as the number of dopants in the pocket implant regions of each of the series of transistors Tp1, Tp2, Tp3, the series of transistors Tq1, Tq2, Tq3, and the series of transistors Tr1, Tr2, Tr3are relatively high (e.g., higher than the number of dopants in the pocket implant regions of each of the transistors Ta, Tb, Tc), a standard deviation of mismatch between threshold voltages of the equivalent transistors Tp, Tq and Tr is relatively low, thereby resulting in better matching of the currents Iref, Iout1and Iout2.

For example, assume that the transistor Ta has N number of dopants in the pocket implant regions20a. Accordingly, a standard deviation of mismatch between threshold voltages of the transistors Ta, Tb, Tc is substantially proportional to 1/sqrt(N), where sqrt(N) represents a square root of N. In the series of transistors Tp1, Tp2, Tp3, the number of dopants in the pocket implant regions220pis almost three times N, i.e., 3N (e.g., as the pocket implant regions220pis about thrice the size of the pocket implant regions20a). Accordingly, a standard deviation of mismatch between the threshold voltages of the functionally equivalent transistors Tp, Tq, Tr is substantially proportional to 1/sqrt(3N), where sqrt(3N) represents a square root of 3N. Thus, the standard deviation of mismatch between threshold voltages associated with the series of transistors Tp1, Tp2, Tp3is much lower than that of the transistor Ta.

Thus, replacing a single transistor (e.g., transistor Ta ofFIGS. 1A-1C) with a functional equivalent series of transistors Tp1, Tp2and Tp3results in an improvement in the mismatch, without substantially increasing effective dimensions of the gate region (i.e., as discussed, dimensions of the gate region14aof the transistor Ta is substantially equal to effective dimensions of the gate regions214p1,214p2,214p3of the transistors Tp1, Tp2, Tp3).

In an embodiment, having a series of transistors Tp1, Tp2and Tp3in the current mirror200ofFIGS. 2A-2C(e.g., instead of a single transistor) also ensures, for example, that a line edge roughness (LER) effect along a gate length in the series of transistors direction is averaged out due to multiple stacked transistors, thereby making a critical dimension of the gate region of the transistors a relatively smaller factor in device mismatch.

As previously discussed, in an embodiment, the lengths L1, L2and L3of the gate regions214p1,214p2and214p3are substantially equal (e.g., say equal to a length Lp). In an embodiment, the length Lp is equal or near equal to a minimum length of a gate region, as allowed for a given technology used to fabricate the transistors of the current mirror200. This allows usage of a maximum number of transistors in a series of transistors.

For example, assume that the gate length L of the transistor Ta is 100 units. The transistor Ta can be replaced by a series of transistors, where the series of transistors comprises two, three, four, or more number of transistors (e.g., the series of transistors in the example ofFIGS. 2A-2Ccomprises three transistors tp1, tp2, tp3). A first option would be to replace the transistor Ta with two transistors, each having a gate length of 50 units; a second option would be to replace the transistor Ta with three transistors, each having a gate length of 33.33 units; a third option would be to replace the transistor Ta with four transistors, each having a gate length of 25 units; and so on. Also assume that the technology used for fabricating the transistors allows a minimum gate length of 30 units. As the minimum gate length has to be 30 units, the third option of replacing the transistor Ta with four transistors cannot be implemented. In such a case, the second option is to be chosen, in which the transistor Ta is replaced with three transistors, each having a gate length of 33.33 units. Choosing the second option, instead of the first option, allows a maximum number of transistors (i.e., three) used for replacing the transistor Ta (e.g., instead of using two transistors to replace the transistor Ta), thereby increasing an amount of dopant in the pocket implant regions, and thus decreasing possibilities of mismatch.

In an embodiment, a distance between gates of two adjacent transistors in a series of transistors (e.g., distance between gate regions214p1and214p2inFIGS. 2B and 2C) is made as small as possible, as allowed under the technology used to fabricate the transistors. Having smaller distance between gates of two adjacent transistors in a series of transistors, for example, minimizes parasitic resistances and improves layout of the transistors (e.g., by reducing an area occupied by the series of transistors).

AlthoughFIG. 2Aillustrates using the various series of transistors in a current mirror, the various series of transistors (e.g., the series of transistors Tp1, Tp2, Tp3, the series of transistors Tq1, Tq2, Tq3, and/or series of transistors Tr1, Tr2, Tr3) can be used in any other appropriate circuit as well.

FIG. 3is a flow diagram of a method300for forming a semiconductor device (e.g., the series of transistors Tp1, Tp2, Tp3). At304, a substrate (e.g, the N well212pofFIGS. 2B and 2C) is formed. At308, a first transistor (e.g., the transistor Tp1ofFIGS. 2A-2C) is formed on the substrate. At312, a second transistor (e.g., the transistor Tp2ofFIGS. 2A-2C) is formed on the substrate. In an embodiment, a common region (e.g., the region216pbofFIG. 2C) of the semiconductor device forms (i) a drain region of the first transistor, and (ii) a source region of the second transistor. In an embodiment, a gate region (e.g., the gate region214p1) of the first transistor is electrically coupled to a gate region (e.g., the gate region214p2) of the second transistor.

The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. The phrase “in some embodiments” is used repeatedly. The phrase generally does not refer to the same embodiments; however, it may. The terms “comprising,” “having,” and “including” are synonymous, unless the context dictates otherwise. The phrase “A and/or B” means (A), (B), or (A and B). The phrase “A/B” means (A), (B), or (A and B), similar to the phrase “A and/or B.” The phrase “at least one of A, B and C” means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). The phrase “(A) B” means (B) or (A and B), that is, A is optional.

Although certain embodiments have been illustrated and described herein, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments illustrated and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments in accordance with the present invention be limited only by the claims and the equivalents thereof.