Chip-packaging module for a chip and a method for forming a chip-packaging module

A chip-packaging module for a chip is provided, the chip-packaging module including an isolation material configured to cover a chip on at least one side, the isolation material having a first surface proximate to a first side of a chip, and said isolation material having a second surface facing an opposite direction to the first surface; and at least one layer in connection with the chip first side, the at least one layer further configured to extend from the chip first side to the second surface of the isolation material.

TECHNICAL FIELD

Various embodiments relate generally to a chip-packaging module and a method for forming a chip-packaging module.

BACKGROUND

Stackable packages are currently a focus in the market of chip-packaging for packaging chips used in logic applications, mobile applications and consumer electronics. For such applications and consumer electronics, package-on-package (PoP) stacks are used so that packages can be tested before stacking. For embedded wafer level package technology (eWLP), e.g., embedded wafer level Ball grid array BGA (eWLB) technology, an embedded package-on-package (ePoP) version will be required in future. An ePoP may form the base package of the stack. Solder paste may be applied to a printed circuit board (PCB), and a bottom package, e.g. an embedded wafer level ball grid array, may be placed into the solder paste. Solder paste may be applied to the top of the ePOP. A standard BGA, e.g. a wire bonded or flip-chip BGA, or a wafer level ball grid array may be assembled on top of the ePoP package by placing the top package onto the ePOP. A reflow may then be carried out to attach the packages together. During the reflow the top package may then be connected to the bottom package.

The interconnection from a top package through an ePOP base or bottom package to the main board may be a vertical interconnection carried out in two different methods.

A first method makes use of via bars, using through-silicon via (TSV) technology or using PCB technology.

FIGS. 1A and 1Bshow how via bars may be used for providing a vertical interconnection from a top package to a bottom package. In this method, via bars156, e.g. via bars comprising electrically conductive via connections, e.g. copper via connections from a package top114to bottom112side in a standard PCB board, may be placed into a package102prior to molding. Thus via bars156may already be pre-manufactured to establish a connection from the top114to the bottom112of package102even before a redistribution line is applied and may be pre-tested to guarantee a “known-good-via”. Each chip106may have one or more connection pads108formed at chip first side120here oriented to face the bottom112of package102. The process is typically less flexible due to the pre-determined configuration of via bars156.

Typically one, two or four via bars may be used for all interconnects, and smaller groups of via bars may not be possible. Moreover, via bars may be expensive. Silicon bars with TSVs or PCB bars may also be used, with PCB bars being the cheaper alternative to silicon bars. However, sufficiently high aspect ratio of via bars in this method may also be difficult to achieve as the via bars tend to be thick. The process has further difficulties because it relies on picking and placing the via bars in specific locations which may be difficult to control. The molding process is also difficult because via bar shifting during the molding process is very likely. Additional process steps for fixing the via bars may therefore be needed before the molding process.

After a mold material110is applied, top side114of package102may be ground to expose the interconnects. With reference toFIG. 1B, thin-film passivation layer128, redistribution layer (RDL)130and solder stop layer154may be applied at chip first side120and/or package bottom side112. Further thin-film passivation layer140, further redistribution layer (RDL)142and further solder stop layer144may be applied to package top side114. A solder ball146may be attached to redistribution layer130located on chip first side120and/or package bottom side112. Due to the large dimensions of via bars, the process may result in a large package.

FIGS. 2A and 2Bshow illustrations of the use of via bars, e.g. conductive via bars, wherein the dimensions of exemplary via bars262are shown in μm.FIG. 2Ashows two vias256a,256bcomprising copper, each having a width of approximately maximally 150 μm formed adjacent each other. Each via may further comprise a hole plug material258which may have a width of approximately 125 μm. A Bismaleimide-Triazine epoxy (BT) or FR-4 polymer core area260may be the carrier material for the vias256a,256b.FIG. 2Bshows a top-down view of via bar262having an array of vias256wherein the distance between each via may be approximately 175 to 200 μm.

In a second method, instead of using pre-fabricated via bars, prior to the mold-formation process, a etch process may be carried out to etch either through silicon to create a through silicon via (TSV) using a through-silicon via wet etch, or by laser drilling through the silicon or a mold component of the eWLB to create a through mold via (TMV) outside the chip. In the latter case, an overmolding process, i.e. forming a mold to isolate a chip may be carried out before the via etch and via fill processes. Both interconnect methods, TSV and TMV may be realized within the package area.

FIGS. 3A to 3Dshow the steps involved in TMV via creation such as by laser drilling in mold compounds. A chip306having one or more connection pads308at the first side320of chip306may be surrounded by a mold material310, as shown inFIG. 3A. Via holes338may be drilled using a laser to create straight substantially vertical and parallel via holes338, which may be formed substantially perpendicular to chip package bottom side312and top side314, as shown inFIG. 3B. Via holes338may then be filled with a material356and further passivated, as shown inFIG. 3C. Chip package302may have a package bottom side312and package top side314, as shown inFIG. 3D. Thin-film passivation layer328, redistribution layer (RDL)330and solder stop layer354may be applied at the chip first side320and/or package bottom side312. Further thin-film passivation layer340, further redistribution layer (RDL)342and further solder stop layer344may be applied at package top side314. Solder ball346may be attached to redistribution layer330located on the chip first side320and/or package bottom side312, forming an embedded wafer level ball grid array package.

In the case wherein a TSV via may be created through silicon, it may be isolated, conductively filled and plugged. In comparison to the first method, the interconnection of the second method has higher flexibility. However, via drilling in a highly filled mold content is a difficult process. Filling the vias is very difficult due to the undercut and high filler content of the mold compound. Therefore, large via diameters may be needed due to the filler content in the mold compound. The process is slow and costly, and is not a typical thin-film processes and may not be available as part of standard fabrication technology. Therefore, yield may be low causing even properly functional devices to be scrapped, thus contributing to the cost and even exceeding the cost of scrapping the package slot, e.g. the package via. In comparison, the first method offers a relatively simple process and standard fabrication tools, e.g. equipment and processes are available and may be used. However, the process may be less flexible than the first method and the mold and mold frame may consume more space.

It is an aim to generate a cost effective three-dimensional interconnection from the base ePoP package to a device above the base ePOP package which alleviates the problems of via filling while creating the opportunity for a smaller chip package.

SUMMARY

An embodiment is a chip-packaging module for a chip including an isolation material configured to cover a chip on at least one side, the isolation material having a first surface proximate to a first side of a chip, and said isolation material having a second surface facing an opposite direction to the first surface; and at least one layer in connection with the chip first side, the at least one layer further configured to extend from the chip first side to the second surface of the isolation material.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

Various embodiments provide for the use of standard thin-film technology to connect the bottom side of the package to the top side. This may be realized by a bevel cut in the bottom side of the package after the eWLB reconstitution.

FIGS. 4A to 4Eshow illustrations of a standard overmolding process which may be used according to an embodiment. A carrier402, e.g. a metal, silicon or a polymer may be selected, and an adhesive foil404may be laminated onto the carrier surface shown inFIG. 4B, wherein the adhesive foil404may be a double sided adhesive and may be easily releasable from a surface. A pick-and-place process places preferably FE-tested good dies or chips406including interconnections408onto the surface of the adhesive foil404, shown inFIG. 4C. Overmolding may then be carried out as shown inFIG. 4Dusing an isolation material410such as a standard mold compound to isolate the die406. The adhesive foil404may be removed from the chips, releasing the foil and carrier from the adhered dies, as shown inFIG. 4E.

The overmolding process as described with respect toFIGS. 4A to 4Emay be used to embed a die or chip in a mold compound. In the second method described above, vias formed by laser drilling or etching in the mold compound may be typically carried out after the overmolding processes described with respect toFIGS. 4A to 4E.

FIGS. 5A to 5Ishow illustrations of a method for forming a chip-packaging module according to various embodiments. In this description the term “over” can be taken to mean “directly on” or “indirectly on”.

According to an embodiment, after an overmolding process such as a process described with respect toFIGS. 4A to 4E, a chip or semiconductor die406may be embedded in an isolation material410, as shown according toFIG. 4E. An isolation material410, e.g. a mold compound may, from the overmolding process be configured to cover a chip406on at least one side. Isolation material410may be a mold material, e.g. a material selected from a group well known in the art such as a material selected from a group consisting of: epoxy (e.g. in liquid, granulate, or sheet form), thermoset Material, thermoplastic Material.

According to an embodiment, isolation material410may be configured to surround chip406except on at least part of a first side520of chip406.

According to an embodiment, chip406and isolation material410configured to cover chip406on at least one side, may together form part of an embedded wafer level package502.

According to an embodiment, isolation material410may include first surface512and second surface514facing an opposite direction516to first surface512of isolation material410. First surface512of isolation material410may be configured to face the same direction518as first side520of chip406. First surface512of isolation material410may be configured to be level with first side520of chip406.

According to an embodiment, first surface512and second surface514of isolation material410may be configured as a bottom and top surface of embedded wafer level package502respectively. First side520of chip406may include at least part of a wafer front side.

According to an embodiment, one or more connection pads408may be formed on first side520of chip406e.g. one or more connection pads408may be formed on at least part of a wafer front side.

According to an embodiment, a recess524may be formed at first surface512of isolation material410, e.g. at a bottom side of an embedded wafer level package502. The recess524may be fabricated by a bevel cut at first surface512of isolation material410, as shown inFIG. 5A. More precisely, the recess524may include at least one sidewall522at an oblique angle to first512and/or second514surface of isolation material410, entire sidewall522having direct line of sight to an opening534at first surface512defined by the at least one sidewall522.

In this context, an oblique angle refers to any angle that is not parallel or perpendicular to first surface512or second surface514of the isolation material410.

Direct line of sight to opening534may be defined in that sidewall522faces opening534.

Direct line of sight to opening534may be defined in that the view, e.g. a view of sidewall522in a direction perpendicular to first surface512from opening534may be substantially unblocked.

Direct line of sight to opening534may be defined in that an object, or particles, e.g. Microparticles or nanoparticles directed along an imaginary line perpendicular to first surface512from opening534defined by sidewall522, would be unobstructed in meeting sidewall522, or a layer formed in parallel to sidewall522.

According to an embodiment, the bevel cut that forms recess524may be performed deeper i.e. in direction516into isolation material410, e.g. mold compound, than the thickness of chip406as measured in direction516. More precisely, sidewall522of notch524may extend further in the direction516towards second surface514of isolation material410than chip406.

InFIG. 5B, the step of depositing a layer528a,528bin connection with a chip first side520may then be performed, in accordance with an embodiment. According to an embodiment, layer528a,528bmay include a thin-film layer. In this context, a thin film layer means any layer having a thickness of between 4 μm and 30 μm.

InFIG. 5B, layer528a,528bmay be a thin-film passivation layer528a,528b, which may be deposited by spin coating, spray coating or by lamination. Thin-film passivation layer528a,528bmay include portion528aformed substantially parallel to at least one sidewall522, and portion528bformed substantially parallel to isolation material first surface512. Thin-film passivation layer528a,528bmay be configured such that thin-film passivation layer528a,528bonly shortly extends over the chip edge into recess524. Thin-film passivation layer528a,528bmay be configured such that portion528amay comprise a negligible portion, or almost negligible portion of thin-film passivation layer528a,528b. Thin-film passivation layer528a,528bmay be configured to be formed over at least one sidewall522. Also advantageously, thin-film passivation layer528a,528bmay be contiguous at the interface between first side520and notch524. According to an embodiment, thin-film passivation layer528a,528bmay be formed directly on at least one sidewall522. Thin-film passivation layer may further include portion528bwhich may be formed over isolation material first surface512and directly on chip first side520, except ideally in the regions of connection pads408formed on first side520of chip406. Thin-film passivation layer528a,528bmay be a material including a dielectric layer, e.g. pre-pregs (pre-impregnated composite fibers), polyimide, epoxy, silicone or blends.

Because sidewall522may be produced by a bevel cut on first surface512of isolation material410, sidewall522form an oblique angle to first surface512of isolation material410. In this case, sidewall522faces opening534defined by sidewall522on first surface512of isolation material410. Sidewall522has direct line of sight to opening534defined by sidewall522on first surface512of isolation material410. Therefore, a method, e.g. sputtering may be used to deposit a material, e.g. thin-film passivation layer528a,528b, over sidewall522and on first surface512of isolation material410. Atoms of the sputter material if approaching first surface512of isolation material410in a direction516normal or perpendicular to first surface512of isolation material410would be unobstructed in meeting sidewall522. Therefore, a thin-film layer528a,528bmay be deposited over sidewall522and over first surface512of isolation material410.

InFIG. 5C, a further layer, electrically conductive thin-film layer530a,530bmay be configured to be formed over thin-film passivation layer528a,528b. Electrically conductive thin-film layer530a,530bmay be deposited using thin-film deposition techniques, e.g. sputter and/or plating. According to an embodiment, electrically conductive thin-film layer530a,530bmay be formed directly on thin-film passivation layer528a,528b. Electrically conductive thin-film layer530a,530bmay be configured to be in connection with chip first side520and further configured to extend between first surface512of isolation material410and the second surface514of isolation material410. Electrically conductive thin-film layer530a,530bmay be configured to be in electrical connection with one or more connection pads408.

According to an embodiment, electrically conductive thin-film layer530a,530bmay be deposited in a single step wherein electrically conductive thin-film layer530a,530bmay be deposited over first surface512of the isolation material410and at least one sidewall522. As shown, this layer may extend contiguously from end to end.

According to an embodiment, electrically conductive thin-film layer530a,530bmay be deposited in a single step wherein electrically conductive thin-film layer530a,530bmay be deposited directly on thin-film passivation layer528a,528b, over first surface512of isolation material410and at least one sidewall522.

According to an embodiment, electrically conductive thin-film layer530a,530bmay include portion530aformed substantially parallel to at least one sidewall522, and portion530bformed substantially parallel to first surface512of isolation material410. According to an embodiment, electrically conductive thin-film layer530a,530bmay have portion530bconfigured as a redistribution layer530bwhich may be in electrical connection with one or more connection pads408on a chip first side520wherein the redistribution layer530bmay be formed in parallel to first surface512of isolation material410.

Due to recess524(bevel cut) formed on first surface512of the isolation material410, thin-film passivation layer528a,528bformed over (in this case, directly on) sidewall522and in parallel to sidewall522, and further over (directly on) first surface512of isolation material410faces opening534defined by sidewall522on first surface512of isolation material410. Thin-film passivation layer528a,528bformed over (directly on) sidewall522and in parallel to sidewall522, and further over (directly on) first surface512of isolation material410has direct line of sight to opening534defined by sidewall522on first surface512of isolation material410. Therefore, electrically conductive layer530a,530bmay be deposited on thin-film passivation layer528a,528b. In the case of deposition by sputtering for example, the direction of the atoms of sputtered electrically conductive material approaching first surface512of isolation material410in a direction516normal or perpendicular to first surface512of isolation material410would be unobstructed in meeting thin-film passivation layer528aformed in parallel over (directly on) sidewall522. Therefore, electrically conductive thin-film layer530awould be formed over the sidewall522(or directly on thin-film passivation layer portion528a) and over first surface152of the isolation material410(directly on thin-film passivation layer portion528b).

According to an embodiment, thin-film passivation layer528a,528bmay be configured to isolate electrically conductive thin-film layer530a,530bfrom the chip406except where electrically conductive thin-film layer530a,530bmay be in electrical connection with one or more connection pads408. According to an embodiment, thin-film passivation layer528a,528bmay include a thin-film dielectric layer.

According to an embodiment, redistribution layer portion530bof electrically conductive thin film layer530a,530bmay connect connection pads408to solder balls or to positions wherein solder balls may be later placed. Redistribution layer portion530bfurther extends into recess524(bevel cut) of isolation material410.

InFIG. 5D, filler material532may be deposited. According to an embodiment, filler material532may be used to close the recess524bevel cut topology. Filler material532may be used to fill recess524to create a surface of filler material532in recess opening534level planar with first surface512of isolation material410. Filler material532may be deposited by printing, spin coating, spray coating or molding. According to an embodiment, filler material532may comprise a mold compound material.

InFIG. 5E, solder stop layer554may be applied over first surface512of isolation material410, over filled recess (bevel) opening534, and over portions of thin-film passivation layer528band redistribution layer530b. According to an embodiment, solder stop layer554may be applied over redistribution layer530bof electrically conductive thin-film layer530a,530b, exposing only select portions536of redistribution layer530b. According to an embodiment, solder stop layer554may function as filler material532for filling recess524as describe previously. According to an embodiment, filler material532and solder stop layer554may be formed from the same material.

InFIG. 5F, grinding of second surface514of isolation material410may be carried out, so that a thickness of isolation material410from second surface514may be reduced. Second surface514of isolation material410, which may be a top side of the embedded wafer level package502may be ground down, or thinned, to expose recess524region from second surface514of isolation material410. Therefore, electrically conductive thin-film layer530a,530b(redistribution layer) may be accessible from second surface514(top side) of embedded wafer level package502.

When recess524region is exposed and ground down at second surface514of the isolation material410, recess524region may form channel region538between first surface512and second surface514of isolation material410. According to an embodiment, isolation material410may include at least one channel region538. Channel region538may be formed outside, e.g. adjacent chip406. For example, inFIG. 5F, multiple channel regions538of multiple recesses524may be configured adjacent to chip406. Channel regions538may be configured to carry at least one layer, e.g. thin-film passivation layer528a,528bor electrically conductive thin-film layer530a,530bas previously described, in connection with first side520of chip410, between first512and second514surfaces of isolation material410. Channel region538may include the at least one lateral sidewall522described previously, wherein at least one lateral sidewall522defines a graduated opening534of the at least one channel region538between first512and second surface514of the isolation material410. According to an embodiment, the graduated opening of at least one channel region538has a diameter which increases from second surface514to a first surface512of isolation material410.

According to an embodiment, lateral sidewall522may be configured as part of at least one channel region538having a diameter which increases from second514surface to first surface512of isolation material410. According to an embodiment, thin-film passivation layer528a,528b, electrically conductive thin-film layer530a,530band filler material532may be configured as part of a multilayer connection extending between first512and second surface514of isolation material410.

InFIG. 5H, further redistribution layer542may be deposited to form an electrical connection with electrically conductive thin-film layer530a,530bat minor opening526of channel region538located at second surface514of isolation material410(further thin-film passivation layer540not shown). According to an embodiment, further redistribution layer542may be formed over second surface514of isolation material410.

Further redistribution layer542may be formed in parallel to second surface514of isolation material410. Further solder stop layer544may be deposited over further redistribution layer542, exposing only select portions564of further redistribution layer542. On first surface512of package502, solder ball546may be applied to select portions536of redistribution layer530bnot covered by solder stop layer554on first surface512of isolation material410. Chip-packaging module502may comprise an embedded wafer level package ball grid array. Chip-packaging module502may form part of a package-on-package stack. Therefore, select portions564of further redistribution layer542may be connected, e.g. electrically connected or contacted with a further package stacked on a higher level, e.g. above second surface514of isolation material410. For example, chip-packaging module502may comprise a bottom package while the further package may comprise a top package. Further redistribution layer542and further solder stop layer544may be applied using standard thin-film technology, e.g. sputtering, evaporation, plating. Electrically conductive layer530a,530b, which is also a redistribution layer forms a single connecting layer connecting the first surface512of the embedded wafer level package, and second surface514of the embedded wafer level package. According to an embodiment, the layer, e.g. electrically conductive layer530a,530b, may form an interconnection from an ePOP base or bottom package to a top package. e.g. electrically conductive layer530a,530bmay be in connection with chip first side520of ePOP bottom package502, and further in connection with further redistribution layer542which may be in connection with, e.g. via a solder ball or solder bump or connection pad, a chip first side520of a ePOP top package, flip-chip or wire bond ball grid array or any other package type or passive components (e. g. integrated passive devices (IPDs)).

InFIG. 5I, individual chip module552may be separated from a neighboring chip module by dicing through channel region538, e.g. in recess524/bevel cut, wherein the line of separation548by dicing may lie in a direction normal to first512and second surface514of isolation material410, e.g. bisecting channel region538, or at any other pre-defined position550. Individual chip packages may be checked using optical inspection.

According to an embodiment, channel region538may comprise one or more sidewalls wherein a further sidewall has an axis of symmetry with the sidewall522about an imaginary line perpendicular to first510and second surface512of isolation material410, the imaginary line bisecting channel region538. For example, channel region538may include a plurality of oblique sidewalls, the oblique sidewalls forming a V-shaped recess, or substantially conical shaped recess, comprising the features as previously described.

In this way a wafer packaging module comprising a plurality of chips may comprise a chip406as described with respect toFIGS. 5A to 5I, and a laterally adjacent further chip406acomprising the features of the chip406as previously described. Channel region538may be configured between the chip406and the further chip406a, the channel region having a first sidewall522contiguous the chip, and a further sidewall522acontiguous the further chip406a. According to an embodiment, the further multilayer connection arrangement comprising a thin-film passivation layer formed directly on further sidewall and in parallel to further sidewall; thin-film electrically conductive layer formed directly on thin-film passivation layer, over further sidewall and in parallel to further sidewall and thin-film passivation layer; and filler material532, may be formed over further sidewall522a. This has the advantage that a plurality of multilayer connections may be formed within a single channel region538, therefore saving space within a packaging module comprising a plurality of dies or chips.

According to a further embodiment, recess524previously described with respect toFIGS. 5A to 5I, may be formed at second surface514instead of first surface512, i.e. at the top side of the package instead of the bottom side. In this further embodiment, further redistribution layer542may be deposited in a single step over second surface514of isolation material410and over a sidewall.

The recess formed at second surface514may include at least one sidewall configured at an oblique angle to the second surface514of the isolation material410, bearing the features of the sidewall as previously described, but with respect to the second surface514of the isolation material. Further redistribution layer542which is also an electrically conductive thin-film layer may be configured to be in connection with a chip, e.g. wherein the chip may be part of a further chip-packaging module above the chip-packaging module. Therefore, further redistribution layer542may be configured to be in connection with a chip, e.g. a chip of an above package first side, the further redistribution layer542further configured to extend from the chip first side to the first surface of the isolation material.

The method described with respect toFIGS. 5A to 5Iintroduces a very cost effective means of providing a through-mold connection between a first surface512and second surface514of isolation material410of an embedded wafer level package, i.e. between an embedded wafer level package bottom side and top side. The method produces a very high yield in producing the connection, because the difficult step of having to fill a vertical via may be eliminated and replaced by a connection using thin-film deposition techniques. Therefore, complex methods involving through-mold vias TMV and through-silicon vias TSV may be eliminated. This leads to cost savings in the formation of connections through the mold compound, e.g. costs savings in terms of the amount of material used for the electrical connection, and further cost savings since no additional via features (e.g. via bars) or complex via drill & fills are needed. Furthermore, costs may be reduced with respect to dicing. Chip packages may be traditionally diced to include the entire channel within an individual chip package. With this method, the chip package may be diced through the channel, as each channel carries multiple multilayer connections, therefore saving space and creating a smaller chip package. In addition, low space consumption can be created by the high density channels and very small line spaces of the connections themselves e.g. line space 20/20 produced using thin-film technology using the bevel-cut channels. Furthermore, the via design, e.g. line width and thicknesses may be also easily adaptable to the packaging needs. All process steps are therefore standard semiconductor fabrication steps, wherein the equipment to carry out these methods may be found in standard fabrication laboratories.

The PoP-package structure furthermore creates the possibility to use the complete package top side, e.g. the top side of a bottom package for the routing and landing pads of a top package placed above a bottom package, which is not possible for classical PoP-packages like Flip chip ball grid arrays. Low warpage of eWLB-based packages may be achieved in comparison to standard packages.

Furthermore, unlike traditional methods wherein forming the redistribution layer is a distinctly separate process to forming via filled connectors and/or via bars, (that is, the redistribution layers and through mold connections and/or via bars are not formed during the same processing step, and are not necessarily formed of the same material, or even as an integrated single layer), the current method and devices provide a solution for creating a single integrated thin-film layer which functions as a redistribution layer and as a through-mold thin-film interconnection layer.

The basic functionalities of the features described with respect toFIG. 5will be referred to and are applicable throughout all the various embodiments which will be described in more detail below. Identical features as to those described inFIG. 5are denoted with the same reference signs.

FIG. 6shows illustrations respectively of a chip-packaging module602for a chip according to various embodiments.

According to an embodiment, chip-packaging module602may include isolation material610configured to cover a chip606on at least one side, the isolation material having a first surface612proximate to a first side620of the chip606, and said isolation material610having a second surface614facing an opposite direction616to the first surface612; and at least one layer in connection with the chip first side620, the at least one layer further configured to extend from the chip first side620to the second surface614of the isolation material610.

The direction618which first surface612of isolation material610faces may be defined by the direction in which the arrow618is pointing. The direction616which second surface614of isolation material610faces may be defined by the direction in which arrow616is pointing. According to an embodiment, chip-packaging module602may include the basic functionalities and characteristics of the features of chip-packaging module502formed as a result of the processing method described with respect toFIGS. 5A to 5I.

The basic functionalities of the features described with respect toFIG. 6will be referred to and are applicable throughout all the various embodiments which will be described in more detail below. Identical features as to those described inFIG. 6are denoted with the same reference signs.

FIG. 7shows illustrations respectively of a chip-packaging module702for a chip according to various embodiments.

According to an embodiment, the chip-packaging module702may include a chip-packaging module602as described with respect toFIG. 6, wherein the chip-packaging module may include an embedded wafer-level packaging module.

According to an embodiment, first surface612and second surface614of isolation material610may be configured as a bottom612and top614surface of embedded wafer level packaging module702respectively.

According to an embodiment, isolation material610may be configured to surround chip606except on at least part of first side620of chip606.

According to an embodiment, first surface612of isolation material610may be configured to face the same direction618as first side620of chip606.

According to an embodiment, first surface612of isolation material610may be configured to be level with first side620of chip606.

According to an embodiment, one or more connection pads706may be formed on first side620of chip606.

According to an embodiment, at least one layer may be configured over first surface612of isolation material610.

According to an embodiment, the at least one layer may be configured to be in electrical connection with at least one of one or more connection pads706formed on first side620of chip606.

According to an embodiment, chip-packaging module702may form part of a package-on-package stack.

According to an embodiment, at least one layer may include a thin film layer.

According to an embodiment, at least one layer may include an electrically conductive thin-film layer730.

According to an embodiment, isolation material610may be a mold material.

According to an embodiment, isolation material610may be a material selected from a group consisting of: filled or unfilled epoxy, pre-pregs (pre-impregnated composite fibers), laminate, thermoset or thermoplastic material.

According to an embodiment, isolation material610may include at least one lateral sidewall722configured to carry at least one layer between first612and second614surfaces of isolation material610.

According to an embodiment, at least one lateral sidewall722may be configured at an oblique angle to first612or second surface614of isolation material610.

According to an embodiment, lateral sidewall722may be configured as part of at least one channel region738extending between first612and second614surfaces of isolation material610, wherein the diameter of channel region738increases from second surface614to first surface612of the isolation material.

According to an embodiment, at least one layer in connection with chip first side620is configured as part of a multilayer connection extending between first612and second surface614of isolation material610.

According to an embodiment, at least one layer may be configured to lie in parallel to at least one sidewall722.

According to an embodiment, at least one layer may include a thin-film passivation layer728.

According to an embodiment, the multilayer connection may include a filler material710.

According to an embodiment, thin-film passivation layer728may be configured to be formed over at least one sidewall722of channel region738.

According to an embodiment, electrically conductive thin-film layer730may be configured to be formed over thin-film passivation layer728.

According to an embodiment, chip606may include a semiconductor die.

According to an embodiment, layer may be further configured to be formed in parallel to a first612or second614surface of isolation material610.

According to an embodiment, electrically conductive thin-film layer730may be further configured as a redistribution layer.

According to an embodiment, redistribution layer may be formed in parallel to a first612or second614surface of the isolation material.

According to an embodiment, filler material732may be a mold material.

According to an embodiment, first side620of chip606may include at least part of a wafer front side.

According to an embodiment, at least one layer may form an interconnection from an ePOP base or bottom package to a top package.

FIG. 8shows an illustration of a method for forming a chip-packaging module including:

a step8002of forming at least one sidewall through an isolation material, the isolation material configured to cover a chip on at least one side, the isolation material having a first surface proximate to a chip first side, and said isolation material having a second surface facing an opposite direction to the first surface;

the sidewall configured at an oblique angle to the first surface of the isolation material the sidewall having direct line of sight to an opening at the first surface defined by the at least one sidewall;

a step8004of depositing in a single step at least one layer in connection with a chip first side and over at least one sidewall, the layer extending from the chip first side to the second surface of the isolation material.

The method therefore uses a bevel cut on package bottom side in conjunction with thin-film technology to realize a connection from the bottom side to the top side of an embedded wafer level package (eWLB) and embedded package-on-package applications.

FIG. 9shows a package-on-package (POP) stack900in accordance with one embodiment. The package-on-package stack900may include a first chip-packing module901arranged above a second chip-packaging module902. First chip-packing module901may be connected with second chip-packing module902. According to an embodiment first chip-packing module901and/or second chip-packing module902may be configured as described with respect toFIG. 7.