Flash memory device, method of manufacturing the same, and method of operating the same

Provided are a memory device, a method of manufacturing the same, and a method of operating the same. The memory device may include a channel region having an upper end where both sides of the upper end are curved, the curved portions of both sides allowing charges to be injected thereinto in a program or erase voltage such that the curved portions into which the charges are injected are separate from a portion which determines a threshold voltage, and a gate structure on the channel region.

PRIORITY STATEMENT

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2007-0048311, filed on May 17, 2007, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.

BACKGROUND

Example embodiments relate to a flash memory device, and methods of manufacturing and operating the same. Other example embodiments relate to a flash memory device that may offset undesirable reliability due to degradation of a portion into which electrons or holes are injected, and methods of manufacturing and operating the flash memory device.

2. Description of the Related Art

Non-volatile memory devices are semiconductor memory devices that may preserve stored data even when there is no supply of power. Representative non-volatile memory devices may be flash memory devices. Each of a plurality of memory cells constituting flash memory may include a cell transistor having a gate structure in which a floating gate storing charges, e.g., data, and a control gate controlling the floating gate may be sequentially stacked. Program or erase operations may be performed in the cell transistor using the Fowler-Nordheim (F-N) tunnelling mechanism.

In order to satisfy the demand for expanding the memory capacity of the flash memory device, the size of the memory cells has been reduced. Also, according to the reduction in the size of the memory cells, a height of the floating gate in a vertical direction may be reduced. However, the size of the floating gate may limit the reduction in the size of the flash memory device. In order to deal with this limitation, a charge trap flash (CTF) memory device including a charge trap layer instead of a floating gate has been developed. The CTF memory device may utilize a shifting threshold voltage as charges are trapped in the charge trap layer. The CTF memory device may be smaller than a flash memory device that stores charges in a floating gate.

FIGS. 1A and 1Bare cross-sectional views illustrating the program and erase operations of a conventional CTF memory device. Referring toFIGS. 1A and 1B, a memory cell constituting the conventional CTF memory device may include a tunnel oxide layer1formed on a channel region8of a semiconductor substrate and allowing charges to tunnel therethrough, a charge trap layer3formed on the tunnel oxide layer1and allowing the charges tunneling through the tunnel oxide layer1to be trapped therein, a blocking oxide layer5formed on the charge trap layer3and preventing or reducing the charges passing through the charge trap layer3from moving upward, and a control gate7formed on the blocking oxide layer5. The channel region8may be formed in the semiconductor substrate. In a memory cell array, a device isolating region9may be formed by shallow trench isolation (STI) to define the channel region8and electrically separate the memory cells. The tunnel oxide layer1, the charge trap layer3, the blocking oxide layer5, and the control gate7may be formed on the channel region8and the device isolating region9. The memory cell may be defined by the channel region8.

Referring toFIG. 1A, in a program mode, a higher voltage (for example, 16V to 17V) may be applied to the control gate7and a lower voltage (for example, 0V) may be applied to the channel region8. Thus, electrons may be injected from the channel region8into the charge trap layer3and then trapped in the charge trap layer3. A lower voltage, e.g., a voltage Vbodyof 0V, may be applied to the semiconductor substrate and the channel region8.

Referring toFIG. 1B, in an erase mode, a low voltage (for example, 0V) may be applied to the control gate7, the channel region8may be floated, and a high voltage (for example, a voltage Vbodyof 17 to 18V) may be applied to the semiconductor substrate. Thus, the electrons stored in the charge trap layer3may be released from the charge trap layer3to the channel region8, or removed due to recombination with holes injected into the charge trap layer3from the channel region8.

As illustrated inFIG. 2, a threshold voltage may be determined at a central portion A′ of the channel region8adjacent to the channel region8and the tunnel oxide layer1. However, in the program or erase mode, electrons or holes may be injected into the central portion A′, thereby degrading the tunnel oxide layer1. As illustrated inFIG. 3, degradation of the tunnel oxide layer1may result from traps generated in a portion of the tunnel oxide layer1into which the electrons or holes are injected. Such traps may affect the channel region8located below and shift a programmed threshold voltage. Accordingly, when the portion into which electrons or holes are injected is degraded in the program or erase mode, the threshold voltage may be shifted, thereby degrading the reliability of the CTF memory device.

SUMMARY

Example embodiments provide a charge trap flash (CTF) memory device that has improved reliability by separating a portion into which charges are injected from a portion which determines a threshold voltage, and methods of manufacturing and operating the CTF memory device.

According to example embodiments, a memory device may include a channel region having an upper end where both sides of the upper end are curved, the curved portions of both sides allowing charges to be injected thereinto in a program or erase voltage such that the curved portions into which the charges are injected are separate from a portion which determines a threshold voltage, and a gate structure on the channel region.

The upper end of the channel region may be formed to have a convex curvature on both sides. The upper end of the channel region may be further formed to have a concave curvature in the center. Curvatures of portions having the convex curvature may be greater than a portion having the concave curvature. The gate structure may include a tunnel insulating layer, wherein the tunnel insulating layer has a portion near the concave curvature thicker than portions near the convex curvature. At least some layers constituting the gate structure may be formed to conform to the curved shape of the channel region.

The gate structure may be of a charge trap type including a tunnel insulating layer and a charge trap layer on the channel region to conform to the curved shape of the channel region, a blocking insulating layer on the charge trap layer, and a control gate on the blocking insulating layer.

According to example embodiments, a method of manufacturing a memory device may include preparing a substrate, forming a structure including a protrusion portion formed on a preliminary channel region position on the substrate and having first and second protrusions being spaced apart from each other in an upper end of the protrusion portion, and insulating material regions formed on both sides of the protrusion portion to expose the first and second protrusions, forming a channel region having an upper end, etching both sides of the upper end so that the first and second protrusions have a convex curvature, and forming a gate structure on the channel region.

Forming the structure including the protrusion portion and the insulating material regions may include forming a stepped structure on the substrate including a protrusion portion and insulating material regions which are on both sides of the protrusion portion and extend beyond the protrusion portion; etching a first hard mask layer on portions of the protrusion portion adjacent to the insulating material regions, and exposing only a central portion of the protrusion portion, forming first and second protrusions spaced apart from each other on an upper end of the protrusion portion by etching the exposed central portion of the protrusion portion to a depth; and removing the first hard mask layer, and partially removing the insulating material regions to expose outer surfaces of the first and second protrusions.

Forming the stepped structure may include forming a second hard mask layer on the substrate, forming the protrusion portion by removing portions of the second hard mask layer and the substrate other than the preliminary channel region position to a depth, forming an insulating material region on both sides of the protrusion portion so that the insulating material region extend beyond the protrusion portion to obtain a stepped structure, and exposing the stepped structure by removing the second hard mask layer. Etching the first hard mask layer may include forming a first hard mask layer on the stepped structure; and etching the first hard mask layer only on portions of the protrusion portion other than those adjacent to the insulating material regions.

According to example embodiments, a method of operating a memory device may include injecting charges into a channel region, having an upper end where both sides of the upper end are curved, by applying a program or erase voltage, and accelerating the movement of the injected charges by applying an additional voltage.

The additional voltage may be a direct current (DC) voltage or a direct current plus alternating current (DC plus AC) voltage. The additional voltage may have a magnitude less than that of the program or erase voltage. The additional voltage may have a DC polarity opposite to that of the program or erase voltage.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Example embodiments may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. In the drawings, the thickness of layers, films and regions are exaggerated for clarity. Like numbers refer to like elements throughout the specification.

A flash memory device according to example embodiments may include a floating gate type flash memory device having a floating gate and a charge trap flash (CTF) memory device having a charge trap layer. The CTF memory device will now be explained as the flash memory according to example embodiments.FIG. 4Ais a cross-sectional view of a CTF memory device10according to example embodiments.FIG. 4Bis a cross-sectional view of the CTF memory device10ofFIG. 4Aviewed in another direction. In detail,FIGS. 4A and 4Billustrate one memory cell of the CTF memory device10. When memory cells are arranged to constitute a NAND flash memory device,FIG. 4Ais a cross-sectional view in a word line direction andFIG. 4Bis a cross-sectional view in a bit line direction.

Referring toFIGS. 4A and 4B, the CTF memory device10may include a channel region11aformed in a substrate11and a gate structure20formed on the channel region11a. The substrate11is not shown inFIG. 4A. The substrate11may be a silicon semiconductor substrate, or a substrate obtained by forming a single crystal silicon layer on a silicon-on-insulator (SOI) substrate. The channel region11amay have an upper end whose lateral portions at least are curved, such that the curved lateral portions may be used as regions into which charges are injected in a program or erase mode. As a result, a portion into which charges are injected and a portion which determines a threshold voltage are separated from each other. The upper end of the channel region11amay include lateral portions A having a convex curvature in both sides and may further include a portion B having a concave curvature in the center. The convex curvature may be greater than the concave curvature.

FIG. 5Ais a graph illustrating the density of electrons injected into a portion having a convex curvature.FIG. 5Bis a graph illustrating the density of holes injected into the portion having the convex curvature. Referring toFIG. 5A, most of the electrons may be injected into the portion having the convex curvature. Referring toFIG. 5B, most of the holes may be injected into the portion having the convex curvature. Most of the electrons and holes may be injected into the portion having the convex curvature results from an increased field effect due to the convex curvature.

Accordingly, when the upper end of the channel region11aincludes the portions A having the convex curvature in both sides and the portion B having the concave curvature in the center as shown inFIG. 4A, most of the charges may be injected into the portions A having the convex curvature (referred to as charge injection regions) in both sides and a threshold voltage may be determined by the portion B having the concave curvature (referred to as the threshold voltage determination region) in the center. Accordingly, because the charge injection regions A, where degradation is generated, are separated from the threshold voltage determination region B which determines a threshold voltage, the risk of shifting a threshold voltage due to the degradation of the charge injection regions A, into which electrons or holes are injected, may be reduced, thereby improving the reliability of the CTF memory device10considerably.

The gate structure20of the CTF memory device10may include a tunnel insulating layer21. The curvature of the charge injection regions A may be greater than the curvature of the threshold voltage determination region B. The tunnel insulating layer21may have a portion near to the threshold voltage determination region B having the concave curvature and thicker than portions nearer to the charge injection regions A having the convex curvature in order to prevent or reduce electrons from being directly released from the threshold voltage determination region B in an erase mode. For example, electrons may not be directly released from the threshold voltage determination region B in an erase mode, because the curvature of the threshold voltage determination region B may be smaller than that of the charge injection regions A and the portion of the tunnel insulating layer21near the threshold voltage determination region B may be relatively thick.

The gate structure20may include a plurality of layers. At least some of the layers constituting the gate structure20may conform to the curved shape of the upper end of the channel region11a. For example, the gate structure20of the CTF memory device10may include the tunnel insulating layer21formed on the channel region11a, a charge trap layer23formed on the tunnel insulating layer21, a blocking insulating layer25formed on the charge trap layer23, and a control gate27formed on the blocking insulating layer25. The tunnel insulating layer21and the charge trap layer23may be formed on the channel region11ato conform to the curved shape of the channel region11aas shown inFIG. 4A.

The tunnel insulating layer21may allow charges, for example, electrons or holes, to tunnel therethrough. The charges tunnelling through the tunnel insulating layer21may be trapped in the charge trap layer23. In a program mode, injected electrons may be trapped in the charge trap layer23. In an erase mode, injected holes may be recombined with the electrons trapped in the charge trap layer23. The blocking insulating layer25may prevent or reduce charges passing through the charge trap layer23from moving upward. ReferringFIG. 4B, first and second impurity regions13and14doped with predetermined or given conductive impurities may be formed in the substrate11. Any one of the first and second impurity regions13and14may be used as a drain D and the remaining one may be used as a source S. InFIG. 4B, reference numeral19denotes a spacer.

The tunnel insulating layer21may be formed on the substrate11to contact the first and second impurity regions13and14, and to be positioned on the channel region11a. The tunnel insulating layer21may be a tunnelling oxide layer formed of SiO2, various high-k oxides, or a combination thereof. Alternatively, the tunnel insulating layer21may be a silicon nitride layer formed of Si3N4. The silicon nitride layer may be formed by jet vapor deposition to have an impurity density similar to that of a silicon oxide layer, and have increased interfacial characteristics on silicon. Alternatively, the tunnel insulating layer21may have a double-layer structure including a silicon nitride layer and an oxide layer.

Charges may be trapped in the charge trap layer23and thus data may be stored in the charge trap layer23. The charge trap layer23may include any one of a nitride, a high-k dielectric substance, and nanodots. For example, the charge trap layer23may be formed of a nitride, e.g., Si3N4or a high-k oxide, for example, SiO2, HfO2, ZrO2, Al2O3, HfSiON, HfON, or HfAlO. The charge trap layer23may include a plurality of discontinuously arranged nanodots as a charge trap site. The nanodots may be nanocrystalline. The blocking insulating layer25, which prevents or reduces charges passing through the charge trap layer23from moving toward the control gate27, may be an oxide layer.

The blocking insulating layer25may be formed of SiO2, or a high-k material having a dielectric constant higher than that of the tunnel insulating layer21, for example, Si3N4, Al2O3, HfO2, Ta2O5, or ZrO2. The blocking insulating layer25may have a multi-layer structure. For example, the blocking insulating layer25may have a double or more multi-layer structure including an insulating layer formed of a general insulating material, e.g., SiO2, and a high-k dielectric layer formed of a material having a dielectric constant higher than that of the tunnel insulating layer21. The control gate27may be a metal layer. For example, the control gate27may be formed of aluminum (Al). Alternatively, the control gate27may be formed of a metal, e.g., Ru or TaN, or a silicide, e.g., NiSi, which are typically used for a gate electrode of a semiconductor memory device. The channel region11aformed in the semiconductor substrate11may be defined by device isolating regions15formed by shallow trench isolation (STI) that electrically separates the memory cells.

FIG. 4Aillustrates that the CTF memory device10may include the channel region11adefined by the device isolating regions15, the tunnel insulating layer21and the charge trap layer23formed on the channel region11ato conform to the curved shape of the channel region11a, and the blocking insulating layer25and the control gate27formed across the charge trap layer23and the device isolating regions15. The CTF memory device10may control a hole injection region according to the curvatures of the channel region11a, the tunnel insulating layer21, and the charge trap layer23. As a result, because the charge injection regions A and the threshold voltage determination region B are separated from each other, a shift in a threshold voltage due to degradation of the tunnel insulating layer21may be avoided, thereby preventing or reducing reliability degradation of the CTF memory device10.

FIG. 6is illustrating the program operation of the CTF memory device according to example embodiments. Referring toFIG. 6, during program operation, a relatively high voltage (for example, about 16V-about 17V) may be applied to the control gate27, and the substrate11may be kept in a state of Vbody=0V. Due to a relatively high field effect caused by the curvature, during program operation, most of the electrons may be injected into the charge injection regions A having the convex curvature while electrons may not be injected into the threshold voltage determination region B due to inverse curvature. The electron injection regions A and the threshold voltage determination region B may be spatially separated from each other.

FIG. 7Aillustrates a state where electrons are injected into the charge trap layer23during the program operation and a potential therefrom.FIG. 7Bis illustrating movement of electrons and change of a potential when an additional voltage is applied to the CTF device10and the electrons are injected into the charge trap layer13. Because most of the electrons are injected into the charge injection regions A having the convex curvature formed on both sides of the channel region11a, both side portions of the charge trap layer23may become a higher potential regions and a central portion of the charge trap layer23may become a lower potential region. The lower figure ofFIG. 7Aillustrates the lateral potential profile of the charge trap layer23.

The electrons may be moved to the central portion of the charge trap layer23due to the difference in potential, thereby changing a threshold voltage. According to the program method of example embodiments, after the electrons are injected as described above, an additional bias voltage having a polarity opposite to that of a program voltage may be applied. The additional voltage may accelerate the movement of the injected electrons in the charge trap layer23. The additional voltage may be a body bias direct current (DC) or direct current plus alternating current (AC) voltage less than the program voltage. The additional voltage may have DC polarity opposite to the program voltage.

FIG. 7Billustrates where the control gate27is kept in a state of about 0V, and a body bias voltage of about 8V, for example, Vbody=˜8V, is applied to the substrate11. When the additional voltage is applied in this way, the difference in potential charges between a higher electron density region and a lower electron density region may be further increased as shown in the lower figure ofFIG. 7B, thereby accelerating the movement of the electrons.

Accordingly, the additional voltage increases a driving force with respect to the movement of the electrons, thereby moving the electrons. For example, when a DC plus AC bias voltage is applied, the drift mobility of the electrons may be increased, thereby facilitating the movement of the electrons.

FIG. 8Ais illustrating the erase operation of the CTF memory device10according to example embodiments.FIG. 8Billustrates that holes, which are injected into the charge trap layer23by the erase operation ofFIG. 8A, are moved when an additional voltage is applied to the CTF memory device10. Referring toFIG. 8A, during erase, the control gate27may be kept in a state of about 0V, and a higher voltage (for example, Vbody=about 17V˜about 18V) may be applied to the substrate11.

Because the holes are injected into the charge injection regions A having the convex curvature even during erase, degradation of the tunnel insulating layer21may be limited to the charge injection regions A. Because the curvature of the threshold voltage determination region B is less than the curvature of the charge injection regions A and the portion of the tunnel insulating layer21near the threshold voltage determination region B is thicker than the portions of the tunnel insulating layer21near to the charge injection regions A, the electrons may not be directly released from the threshold voltage determination region B having the concave curvature.

According to the erase operation of example embodiments, after the holes are injected in this way, an additional bias voltage having a polarity opposite to that of an erase voltage may be applied to move the holes in the charge trap layer23to a portion where a threshold voltage is determined and then remove the electrons. The additional voltage may accelerate the movement of the injected holes. The additional voltage in the erase operation may be a DC or DC plus AC voltage less than that of the erase voltage. Also, the DC polarity of the additional voltage may be opposite to that of the erase voltage. Referring toFIG. 8B, when a lower DC or DC plus AC voltage of about 8V is applied as an additional voltage to the control gate27, holes may drift into the charge trap layer23, thereby accelerating the erase operation. For example, when the additional voltage is applied, electrons and holes may be rapidly recombined with each other even during erase.

As described above, the program operation may be performed to be a threshold voltage of a program state by injecting electrons into the CTF memory device10and trapping the injected electrons into the trap sites of the charge trap layer23, and the erase operation may be performed to be a threshold voltage of an erase state by injecting holes into the CTF memory device10and removing the electrons due to recombination between the electrons and the holes.

Accordingly, each memory cell has two states, for example, a program state and an erase state. An erase state may be an on state where current flows to a drain connected to a bit line due to a voltage applied to the control gate27during a read operation, thereby reducing the threshold voltage of the memory cell, and a program state may be an off state where current may not flow to the drain connected to the bit line due to the voltage applied to the control gate27during the read operation by increasing the threshold voltage of the memory cell.

FIG. 9is illustrating the read operation of the CTF memory device10according to example embodiments. Referring toFIG. 9, during read operation, a read voltage of, for example, about 4.5V, may be applied to the control gate27and the substrate11may be kept in a state of Vbody=0V. Because the density of electrons in the portions of the charge trap layer23corresponding to the charge injection regions A is still relatively high, the threshold voltage of the charge injection regions A may be high. Although regions C between the charge injection regions A and the threshold voltage determination region B have an electron density similar to that of the threshold voltage determination region B, because the threshold voltage determination region B is a relatively high gate field region due to the concave curvature, the threshold voltage determination region B may have the lowest threshold voltage.

Because the charge injection regions A, which cause degradation, are separated from the threshold voltage determination region B, a programmed threshold voltage may not shift, thereby improving reliability even during a read operation. In the CTF memory device10according to example embodiments, the electron or hole injection regions may change by adding curvature to the channel region11a, the tunnel insulating layer21, and the charge trap layer23. As a result, because the charge injection regions A and the threshold voltage determination region B are separated from each other, a shift in a threshold voltage may be avoided, thereby preventing or reducing reliability degradation of the CTF memory device10.

In the programming, after the electrons are injected by applying a program bias, when the DC or DC plus AC additional voltage smaller than the program bias is also applied, the electrons may move to the desired positions in the charge trap layer23, thereby separating the charge injection regions A from the threshold voltage determination region B. In the erase operation, because the DC or DC plus AC additional voltage smaller than the erase bias is applied after the erase bias is applied to inject holes, the holes may move to the position where a threshold voltage is determined to erase the electrons.

Accordingly, when the additional voltage is applied after the charges are injected for programming or erasing, charge stabilization and recombination speed may be improved, the possibility of incomplete recombination may be reduced, the possibility of coexistence of opposite charges may be reduced, the stability of the erase state or program state may be ensured, and the possibility of degradation in dispersion of the threshold voltage in the program or erase may be reduced.

In generation operation of a CTF memory device, during programming, a program operation may be performed by applying a program voltage pulse to a memory cell of the CTF memory device and then a program verify operation may be performed by applying a verify voltage to verify whether the memory cell is programmed. Also, in a programming mode based on an incremental step pulse programming (ISPP) method, a program operation applying a program voltage to the memory cell, and then a program verify operation applying a verify voltage, may be repeatedly performed until the threshold voltage of the memory cell reaches a threshold voltage in a program state.

In erasing, an erase operation may be performed by applying an erase voltage pulse to the memory cell of the CTF memory device, and then an erase verify operation may be performed by applying a verify voltage to confirm whether the memory cell is erased. Accordingly, as the operating method of example embodiments, when charges are injected for program or erase and then an additional voltage is applied, the additional voltage may be applied between a voltage for program or erase and a verify voltage. For example, after a program or an erase is performed by applying a program voltage or an erase voltage and then applying an additional voltage, a verifying operation may be performed by applying a verify voltage. The program voltage, the erase voltage, the additional voltage, and the verify voltage may be applied as pulses as shown inFIGS. 10A through 12B.

FIGS. 10A and 10Billustrate embodiments of voltage waveforms when the program operation is performed according to an operating method of example embodiments.FIG. 10Aillustrates voltage waveform when an additional voltage is a DC voltage having a magnitude less than and a polarity opposite to those of a program voltage.FIG. 10Billustrates voltage waveform when an additional voltage is a DC plus AC voltage having a magnitude smaller than and a DC polarity opposite to that of a program voltage.

Referring toFIGS. 10A and 10B, during programming, a program voltage, an additional voltage, and a verify voltage are sequentially applied while forming one package.FIGS. 11A and 11Billustrate voltage waveforms when a program operation based on an ISPP method respectively using the voltage waveforms ofFIGS. 10A and 10Bare performed. As may be seen fromFIGS. 11A and 11B, the operation method according to example embodiments may be applied to the program operation based on the ISPP method. InFIGS. 11A and 11B, Vpgm denotes the magnitude of a basic program voltage during the program operation based on the ISPP method and ΔVpgm denotes the increased amount of the program voltage during the program operation based on the ISPP method.

When the operation method according to example embodiments is applied to the program operation based on the ISPP method, a program voltage pulse having a predetermined or given magnitude may be applied to perform a program operation, an additional voltage pulse may be applied, and then a verify voltage pulse may be applied to confirm whether a threshold voltage reaches a threshold voltage in a program state. When it is confirmed that the threshold voltage has not reached a threshold voltage of the program state, the magnitude of the program voltage pulse may be increased by a predetermined or given level and the above process may be repeated. This process may be repeated several times until the threshold voltage reaches the threshold voltage of the program state.

FIGS. 12A and 12Billustrate embodiments of voltage waveforms when the erase operation is performed according to an operating method of example embodiments.FIG. 12Aillustrates voltage waveform when an additional voltage is a DC voltage having a magnitude less than and a polarity opposite to those of an erase voltage.FIG. 12Billustrates voltage waveform when an additional voltage is a DC plus AC voltage having a magnitude less than and a DC polarity opposite to those of an erase voltage. Referring toFIGS. 12A and 12B, during erase, an erase voltage, an additional voltage, and a verify voltage may be sequentially applied while forming a package.

FIGS. 13A-13Kare cross-sectional views illustrating a method of manufacturing a CTF memory device according to example embodiments.

Referring toFIGS. 13A through 131, a substrate11may be prepared. The substrate11may be a silicon semiconductor substrate, or a substrate obtained by forming a single crystal silicon layer on an SOI substrate. A structure including a protrusion portion33formed on a preliminary channel region position of the substrate11and having an upper end whose first and second protrusions33aand33bare spaced apart from each other, and insulating material regions15′ formed on both sides of the protrusion portion33to expose the first and second protrusions33aand33bmay be formed on the substrate11.

Etching may be performed so that the first and second protrusions33aand33bmay have a convex curvature as shown inFIG. 13J. Accordingly, a channel region11ahaving an upper end whose lateral portions have a convex curvature may be formed. A gate structure20may be formed on the channel region11aas shown inFIGS. 13J and 13K. At least a tunnel insulating layer21and a charge trap layer23may be formed to conform to the curved shape of the channel region11a.

The structure including the protrusion portion33and the insulating material regions15′ may be formed by processes ofFIGS. 13A-13Dsuch that a stepped structure having the protrusion33and the insulating material regions15′ extending beyond the protrusion portion33may be formed on the substrate11. In order to form the stepped structure, referring toFIG. 13A, a hard mask layer31may be formed on the substrate11. Referring toFIG. 13B, portions of the hard mask layer31and the substrate11other than the preliminary channel region position may be removed to a predetermined or given depth to form the protrusion portion33. The hard mask layer31may be a nitride layer, for example, a Si3N4layer. Referring toFIG. 13C, the insulating material regions15′ may be formed on both sides of the protrusion portion33to extend beyond the protrusion portion33. The insulating material regions15′ may extend up to the height of the hard mask layer31. Referring toFIG. 13D, the hard mask layer31may be removed to expose the stepped structure.

The insulating material regions15′ may be formed of an oxide. When memory cells of the CTF memory device10according to example embodiments may be electrically separated from one another by STI, the insulating material regions15′ may correspond to device isolating region15by STI process. A hard mask layer35may be formed on only portions of the protrusion portion33adjacent to the insulating material regions15′ to expose a central portion of the protrusion portion33as shown inFIGS. 13E and 13F. Referring toFIG. 13E, the hard mask layer35may be formed on the entire surface of the stepped structure. Referring toFIG. 13F, etching may be performed so that the hard mask layer35may be left on only the portions of the protrusion portion33adjacent to the insulating material regions15′ and the central portion of the protrusion portion33may be exposed.

Referring toFIG. 13G, the exposed central portion at an upper end of the protrusion portion33may be etched to a predetermined or given depth using the hard mask layer35as a mask to obtain the first and second protrusions33aand33bwhich are spaced apart from each other. Referring toFIG. 13H, the hard mask layer35may be removed. Referring toFIG. 13I, the insulating material regions15′ may be partially removed to expose outer surfaces of the first and second protrusions33aand33b.

Referring toFIG. 13J, etching may be performed so that the first and second protrusions33aand33bmay have a convex curvature and a space between the first and second protrusions33aand33bmay have a concave curvature. A tunnel insulating layer21may be formed on the channel region11ahaving the curved shape. Referring toFIG. 13K, a charge trap layer23, a blocking insulating layer25, and a control gate27may be formed on the tunnel insulating layer21, thereby completing a CTF memory device10according to example embodiments.

Although the method of manufacturing the CTF memory device10has been explained with reference toFIGS. 13A-13K, the method of manufacturing according to example embodiments may not be limited thereto and various modifications may be made within the scope of example embodiments. Although a technology of spatially separating a charge injection region from a threshold voltage determination region is applied to a CTF memory device in the above description, example embodiments may not be limited thereto.

Therefore, the technology of example embodiments may be applied to other memory devices, for example, a floating gate type flash memory device including a floating gate and a control gate as well as to the CTF memory device10. Because the application of this technology to the floating gate type flash memory device is obvious to one of ordinary skill in the art from the above description and well-known fact, a detailed explanation thereof will not be given.

As described above, according to example embodiments, a charge injection region and a threshold voltage determination region may be separate from each other. Accordingly, reliability degradation resulting from a shift in a threshold voltage due to degradation of a tunnel insulating layer (oxide layer) of a region into which electrons or holes are injected during programming or erasing may be overcome.

Furthermore, during the program or erasure operation of the flash memory device according to example embodiments, because an additional voltage is applied after a program or erase voltage is applied to inject charges, charge stabilization and recombination speed may be increased, the possibility of incomplete recombination may be reduced, the possibility of coexistence with opposite charges may be reduced, the stability of an erase or program state may be ensured, and the possibility of degradation due to a shift in a threshold voltage in a program or erase may be reduced.