Trim techniques for voltage reference circuits

An example method of trimming a voltage reference in an integrated circuit (IC) includes at a first temperature, sequencing through a first plurality of trim codes for a reference circuit of the voltage reference configured to generate a proportional-to-temperature current and a corresponding first control voltage, and a complementary-to-temperature current and a corresponding second control voltage. The method further includes measuring a voltage output of the voltage reference for each of the first plurality of trim codes to obtain first voltage output values. The method further includes at a second temperature, sequencing through a second plurality of trim codes for the reference circuit. The method further includes measuring the voltage output of the voltage reference for each of the second plurality of trim codes to obtain second voltage output values. The method further includes selecting a trim code for the reference circuit based on the first voltage output values and the second voltage output values.

TECHNICAL FIELD

Examples of the present disclosure generally relate to electronic circuits and, in particular, to trim techniques for voltage reference circuits.

BACKGROUND

Precision voltage references are important blocks in integrated circuits (ICs), such as System-on-Chip (SoC) ICs. Voltage references are required for various purposes, such as for analog-to-digital converters (ADCs), power management, and the like. Generation of a voltage that is dependent on temperature is also useful in some applications, such as to compensate for temperature effects on circuits. Thus, different circuits in an IC require voltage references having different temperature coefficients (e.g., an ADC uses a temperature-independent voltage reference whereas other circuits, such as switches, require a temperature-dependent voltage reference). Further, circuits for generating voltage references typically use bipolar junction transistors (BJTs). BJTs, however, are parasitic devices in the complementary metal oxide semiconductor (CMOS) process used to fabricate ICs. BJT performance degrades as the CMOS technology scales, which is driven by digital logic. Accordingly, it is desirable to provide trim techniques for correcting mismatch and process variation in voltage reference circuits.

SUMMARY

Trim techniques for voltage reference circuits are described. In an example, a method of trimming a voltage reference in an integrated circuit (IC) includes: at a first temperature, sequencing through a first plurality of trim codes for a reference circuit of the voltage reference configured to generate a proportional-to-temperature current and a corresponding first control voltage, and a complementary-to-temperature current and a corresponding second control voltage; measuring a voltage output of the voltage reference for each of the first plurality of trim codes to obtain first voltage output values; at a second temperature, sequencing through a second plurality of trim codes for the reference circuit; measuring the voltage output of the voltage reference for each of the second plurality of trim codes to obtain second voltage output values; and selecting a trim code for the reference circuit based on the first voltage output values and the second voltage output values.

In another example, an apparatus for trimming a voltage reference in an integrated circuit (IC) includes: a memory; and a processor configured to execute code stored in the memory to: at a first temperature, sequence through a first plurality of trim codes for a reference circuit of the voltage reference configured to generate a proportional-to-temperature current and a corresponding first control voltage, and a complementary-to-temperature current and a corresponding second control voltage; measure a voltage output of the voltage reference for each of the first plurality of trim codes to obtain first voltage output values; at a second temperature, sequence through a second plurality of trim codes for the reference circuit; measure the voltage output of the voltage reference for each of the second plurality of trim codes to obtain second voltage output values; and select a trim code for the reference circuit based on the first voltage output values and the second voltage output values.

DETAILED DESCRIPTION

FIG. 1is a block diagram depicting an integrated circuit (IC)100according to an example. The IC100includes a voltage reference circuit200, a control circuit114, and circuits102. The voltage reference circuit200is coupled between a supply node110, which supplies a voltage VCC, and a ground node112, which supplies a ground voltage (e.g., 0 volts). The voltage VCCmay be provided by a voltage supply (not shown) either within the IC100or external to the IC100. The voltage reference circuit200is coupled to one or more of the circuits102by one or more nodes104, each of which supplies a zero temperature coefficient (Tempco) voltage. The voltage reference circuit200is coupled to one or more of the circuits102by one or more nodes106, each of which supplies a negative Tempco voltage. The voltage reference circuit200is coupled to one or more of the circuits102by one or more nodes108, each of which supplies a positive Tempco voltage. Thus, the voltage reference circuit200generates zero Tempco voltage(s), negative Tempco voltage(s), and positive Tempco voltage(s). The control circuit114supplies control signals to the voltage reference circuit200for trimming voltages and/or currents as described in detail below.

FIG. 2is a block diagram depicting the voltage reference circuit200according to an example. The voltage reference circuit200includes a reference circuit202, a zero Tempco circuit204, a negative Tempco circuit206, and a positive Tempco circuit208. A node210couples one output of the reference circuit202to each of the Tempco circuits204. . .208. A node212couples another output of the reference circuit202to each of the Tempco circuits204. . .208. The nodes210and212supply control voltages to the Tempco circuits204. . .208. The reference circuit202generates a proportional-to-absolute-temperature current (referred to as Iptat) and a complementary-to-absolute-temperature current (referred to as Ictat), as described further below. The control voltages on the nodes210and212control current sources in the Tempco circuits204. . .208to mirror the currents Iptat and Ictat, respectively. The zero Tempco circuit204converts a zero Tempco current Iztat (Iztat=Iptat+Ictat) into one or more zero Tempco voltages at the nodes104. The negative Tempco circuit206converts the current Iztat into one or more negative Tempco voltages at the nodes106. The positive Tempco circuit208converts the current Iztat into one or more positive Tempco voltages at the nodes108.

FIG. 3is a schematic diagram depicting the reference circuit202according to an example. The reference circuit202includes p-channel field effect transistors (FETs)302,304, and306, such as p-type metal oxide semiconductor FETs (MOSFETs). A p-channel FET is a FET that uses holes as the majority carrier to carry its channel current. The reference circuit202further includes an operational amplifier308, an operational amplifier316, a multiplexer320, a resistor310, a resistor ladder318, a bipolar junction transistor (BJT)312, and a BJT314. The BJTs312and314are PNP transistors.

A source of the FET302is coupled to the node110that supplies VCC. A drain of the FET302is coupled to a node324. A gate of the FET302is coupled to the node210that supplies a control voltage VP. A source of the FET304is coupled to the node110. A drain of the FET304is coupled to a node326. A gate of the FET304is coupled to the node210. A source of the FET306is coupled to the node110. A gate of the FET306is coupled to the node212that supplies a control voltage VC. A drain of the FET306is coupled to a node330. The resistor ladder318, having a total resistance R2, is coupled between the node330and the ground node112.

FIG. 4is a schematic diagram depicting a resistor ladder400according to example. The resistor ladder400can be used as the resistor ladder318or any other resistor ladder described herein. The resistor ladder400includes a resistor string408, e.g., resistors4081. . .408K, where K is an integer greater than one. The resistors4081. . .408Kare coupled in series between a node410and a node412. The resistor ladder400further includes a multiplexer402. Inputs of the multiplexer402are respectively coupled to a plurality of taps, e.g., taps4041. . .404J, where J is an integer greater than one. Each tap4041. . .404Jis coupled to a respective node of the resistor string408, where the resistor string408includes one or more resistors between each pair of nodes. The multiplexer402includes a control input414for receiving a signal Ctrl that selects one of the taps404. The signal Ctrl is a digital signal having ceiling[log2(J)] bits. The multiplexer402includes an output coupled to a node406. The resistor ladder400provides an effective resistance R between the node406and the node412(shown in phantom for purposes of illustration), which depends on the code value of the Ctrl signal.

Returning toFIG. 3, a node328is coupled to a selected tap of the resistor ladder318based on the value of a Flat Trim code. This effectively splits the resistor ladder318into a resistance3181between the node330and the node328, and a resistance3182between the node328and the ground node112. The resistance3181has a value R2′, and the resistance3182has a value R2″.

An inverting input of the operational amplifier308is coupled to the node324. A non-inverting input of the operational amplifier308is coupled to the node326. An output of the operational amplifier308is coupled to the node210. An inverting input of the operational amplifier316is coupled to the node324. A non-inverting input of the operational amplifier316is coupled to a node328. An output of the operational amplifier316is coupled to the node212.

The resistor310, having a resistance R1, is coupled between the node326and an emitter of the BJT314. Each of a base and a collector of the BJT314is coupled to the ground node112. Thus, the BJT314is a diode-connected BJT having an anode coupled to the resistor310and a cathode coupled to the ground node112. An emitter of the BJT312is coupled to the node324. Each of a base and a collector of the BJT312is coupled to the ground node112. Thus, the BJT312is a diode-connected BJT having an anode coupled to the node324and a cathode coupled to the ground node112. The BJT314has N times the emitter area as the BJT312, where N is an integer greater than one.

In operation, the operational amplifier308is self-biasing and sets the control voltage VPto turn on the FETs302and304. The operational amplifier308applies negative feedback so that the voltage at the node324equals the voltage at the node326. The voltage at the node324is a voltage VEB1, which is the voltage between the emitter and base of the BJT312. The voltage VEB1is complementary to temperature (i.e., has a negative Tempco). The voltage at the emitter of the BJT314is VEB2, which is the voltage between the emitter and base of the BJT314. The voltage VEB2is complementary to temperature. The voltage across the resistor310, between the node326and the emitter of the BJT314, is ΔVBE=VEB1−VEB2=VBE2−VBE1. The differential voltage ΔVBEcan be mathematically expressed as ΔVBE=n*VT*In(N), where VTis the thermal temperature, n is the ideality factor, N is the ratio of emitter area between the BJT314and the BJT312, and In denotes the natural logarithm function. For purposes of example herein, the ideality factor n is assumed to be one and is omitted from subsequent expressions. The thermal voltage VT=kT/q, where T is the temperature in Kelvin, k is the Boltzmann constant, and q is the electron charge in coulombs. As such, ΔVBEis proportional to temperature (i.e., has a positive Tempco). ΔVBEis also dependent on the ratio of collector current, which is related to the base current by the beta factor (i.e., beta=Ic/Ib, where Ic is the collector current and Ib is the base current). The current Iptat can be mathematically expressed as Iptat=ΔVBE/R1, which is also proportional to temperature. The voltage VPat the node210controls current sources in the Tempco circuits to mirror the current Iptat.

The operational amplifier316applies negative feedback through adjustment of the control voltage VCto equalize the voltage at node328and the voltage at node324(e.g., VEB1). Thus, the current Ictat (going from the node330into the resistor ladder318) can be mathematically expressed as Ictat=VEB1/R2″. Since VEB1is complementary to temperature, then Ictat is also complementary to temperature. The voltage VCat the node212controls current sources in the Tempco circuits to mirror the current Ictat. The current Ictat can be trimmed by varying the Flat Trim code. The flat trim balances the temperature coefficient by adjusting Ictat relative to Iptat so that Ictat+Iptat=Iztat is approximately constant over a range of temperature. Note that while the slope of Iptat with respect to temperature is constant, the slope of Ictat with respect to temperature is non-linear. Thus, Iztat varies from the desired constant value over a range of temperature. This first-order error is corrected, as described further below.

A source of the FET502is coupled to the node110that supplies VCC. A drain of the FET502is coupled to a node530. A gate of the FET502is coupled to the node212that supplies the control voltage VC. A source of the FET504is coupled to the node110that supplies VCC. A drain of the FET504is coupled to a node530. A gate of the FET504is coupled to the node210that supplies the control voltage VP. A source of the FET506is coupled to the node110. A drain of the FET506is coupled to a node532. A gate of the FET506is coupled to the node212that supplies the control voltage VC. A source of the FET508is coupled to the node110that supplies VCC. A drain of the FET508is coupled to the node532. A gate of the FET508is coupled to the node210that supplies the control voltage VP. The FETs502and504form a current source5141that mirrors Ictat and Iptat. The FETs506and508form a current source5142that mirrors Ictat and Iptat.

The resistor ladder512, having a resistance RLOAD1, is coupled between the node530and the ground node112. A node556is coupled to a selected tap of the resistor ladder512based on the value of the Ref1Trim code. Selection of the tap results in a resistance5121coupled between the node530and the node556, and a resistance5122coupled between the node556and the ground node112. The resistance5121has a value RLOAD1′, and the resistance5122has a value RLOAD1″. The curvature correction circuit510is coupled to the node556to supply a current Icor, as described further below.

The resistor ladder554, having a resistance RLOAD2, is coupled between the node532and the ground node112. A node558is coupled to a selected tap of the resistor ladder554based on the value of the Ref2Trim code. Selection of the tap results in a resistance5541coupled between the node532and the node558, and a resistance5542coupled between the node558and the ground node112. The resistance5541has a value RLOAD2′, and the resistance5542has a value RLOAD2″.

In operation, the control voltage VCcontrols the FETs502and506to supply the current Ictat. The control voltage VPcontrols the FETs504and508to supply the current Iptat. The currents Ictat and Iptat feed the node530. The control circuit114sets the Ref1Trim to control values of RLOAD1′ and RLOAD1″. The curvature correction circuit510supplies a current Icor to the resistor ladder512such that, in steady state condition, the sum of the currents Iztat and Icor conducts through the resistance RLOAD1″.

The currents Ictat and Iptat feed the node532. In steady state condition, the current Iztat conducts through the resistor ladder554. The control circuit114controls sets Ref2Trim to control values for RLOAD2′ and RLOAD2″. The voltage output by the LPF538is proportional to Iztat. The operational amplifier540, the resistor544, the resistor546, and the resistor552are configured as a non-inverting amplifier that applies a configured amount of gain to the voltage output by the LPF538. The gain is determined by the resistance values of the resistors544,546, and552. The node542supplies a zero Tempco voltage Vref2. The resistors544,548, and552form a voltage divider that supplies a fraction of Vref2at the node550(e.g., half of the voltage to generate Vref2/2).

The Ref1Trim and Ref2Trim codes set a direct current (DC) level of the corresponding pre-gain voltages at the nodes556and558, respectively. Gain circuits can be used to amplifier or attenuate the pre-gain voltages. Voltage dividers can then provide one or more fractions of the post-gain reference voltage.

In the example, the zero Tempco circuit204includes two current sources514for mirroring Ictat and Iptat to generate three zero Tempco voltages. In other examples, the zero Tempco circuit204can include less or more than two current sources514for generating any number of zero Tempco voltages. In an example, one or both of the gain circuits516can be omitted. Alternatively, another current source514can feed another resistor ladder that supplies a pre-gain output voltage.

FIG. 6is a block diagram depicting a test system600according to an example. The test system600includes automatic test equipment (ATE)602and a wafer604having a plurality of ICs100. The ATE602includes a central processing unit (CPU)608, a memory612, input/output (IO) circuits610, and support circuits606. The CPU608can be any type of general-purpose processor, such as an x86-based processor, ARM®-based processor, or the like. The CPU608can include one or more cores and associated circuitry (e.g., cache memories, memory management units (MMUs), interrupt controllers, etc.). The CPU608is configured to execute program code that perform one or more operations described herein and which can be stored in the memory612. The support circuits606include various devices that cooperate with the CPU608. For example, the support circuits606can include a chipset (e.g., a north bridge, south bridge, platform host controller, etc.), voltage regulators, firmware (e.g., a BIOS), and the like. In some examples, the CPU608can be a System-in-Package (SiP), System-on-Chip (SoC), or the like, which absorbs all or a substantial portion of the functionality of the chipset (e.g., north bridge, south bridge, etc.). The IO circuits610include various circuits configured for communication with the ICs100.

The memory612is a device allowing information, such as executable instructions and data, to be stored and retrieved. The memory612can include, for example, one or more random access memory (RAM) modules, such as double-data rate (DDR) dynamic RAM (DRAM). The ATE602can include various other devices, including local storage devices (e.g., one or more hard disks, flash memory modules, solid state disks, and optical disks) and/or a storage interface that enables the test system600to communicate with one or more network data storage systems.

FIG. 7is a flow diagram depicting a method700of setting trim codes in a voltage reference circuit according to an example. The method700can be performed by the ATE602for setting the Flat Trim in the reference circuit202, and the Ref_x Trim (e.g., Ref1Trim, Ref2Trim, etc.) in the circuit500, for each IC100on the wafer604.

The method700begins at step702, where the wafer604is disposed in a 0 degree Celsius (0 C) environment and the ATE602sequences through trim codes for the Flat Trim and measures Vref1. The ATE602obtains a plurality of Vref1values for a corresponding plurality of trim codes of the Flat Trim. At step704, the ATE602fits the Vref1values obtained at step702to a polynomial curve having one or more coefficients (e.g., three coefficients). The ATE602stores the values of the coefficients in the IC100(e.g., in the control circuit114using, for example, an electronic fuse (e-fuse) or the like type memory element).FIG. 8Ais a graph800depicting flat trim codes versus output voltage at different temperatures according to an example. In the graph800, the horizontal axis represents flat trim code and the vertical axis represents output voltage. A curve802represents the polynomial curve determined at704(where T1=0 C).

At step706, the wafer604is disposed in a 100 degree Celsius (100 C) environment and the ATE602sequences through trim codes for the Flat Trim and measures Vref1. The ATE602obtains a plurality of Vref1values for a corresponding plurality of trim codes of the Flat Trim. At step708, the ATE602fits the Vref1values obtained at step706to a polynomial curve having the same order as that used in step704. In the graph800, a curve804represents the polynomial curve determined at step708.

At step710, the ATE602determines an intersection between the Vref1curve at 0 C and the Vref1curve at 100 C. The ATE602can generate the Vref1curve at 0 C by obtaining the coefficients stored by the control circuit114in the IC100. The ATE602generates the Vref1curve at 100 C in step708. At step712, the ATE602determines a trim setting for the Flat Trim corresponding to the intersection between the Vref1curve at 0 C and the Vref1curve at 100 C. As shown in the graph800, the intersection of the curve802and804results in the determined flat trim code value. At step714, the ATE602sets the Flat Trim to the determined trim code at step712and adjusts the Ref1Trim to set a desired voltage of Vref1(e.g., 1V).FIG. 8Bis a graph801depicting ref trim codes versus output voltage at a particular temperature (T=T2) according to an example. In the graph801, the horizontal axis represents ref trim code and the vertical axis represents output voltage. A curve806represents ref trim code versus output voltage and an output voltage of 1V results in the determined ref trim code value.

FIG. 9is a flow diagram depicting a method900of setting trim codes in a voltage reference circuit according to an example. The method900can be performed by the ATE602for setting the Flat Trim in the reference circuit202, and the Ref_x Trim (e.g., Ref1Trim, Ref2Trim, etc.) in the circuit500, for each IC100on the wafer604.

The method900begins at step902, where the ATE602selects an approximate trim code for the Flat Trim. The approximate trim code for the Flat Trim can be set based on simulations of the voltage reference circuit. At step904, the wafer604is disposed in a 0 C environment and the ATE602selects a trim code for the Ref1Trim that sets Vref1to a desired value (e.g., 1 V). The ATE602can adjust the Ref1Trim and measure Vref1until Vref1obtains the desired value. At step906, the ATE602stores the selected trim code for Ref1Trim in the IC100(e.g., in the control circuit114using, for example, an electronic fuse (e-fuse) or the like type memory element).

At step908, the wafer604is disposed in a 100 C environment and the ATE602selects a trim code for the Ref1Trim that sets Vref1to the desired value (e.g., 1 V). At step910, the ATE602determines the slope of the Ref1Trim code over temperature. For example, the ATE602can compute the difference between the Ref1Trim code values at 0 C and at 100 C.FIG. 10Ais a graph1000depicting measurements of the Ref1Trim Code at two different temperatures according to an example. In the graph1000, the horizontal axis represents temperature and the vertical axis represents Ref1Trim Code value. At temperature T1, code1is obtained. At temperature T2, code2is obtained. If the temperature coefficient was zero, the same code would be obtained at both temperatures. The ATE602determines the slope of curve1002at step910.

At step912, the ATE602obtains a trim code value for the Flat Trim from a lookup table based on the Ref1Trim code slope determined at step910. The lookup table can include a plurality of trim code values for the Flat Trim for a corresponding plurality of Ref1Trim code slope values.FIG. 10Bis a graph1001depicting a lookup of the flat trim code given a slope of Ref1Trim according to an example. In the graph1001, the horizontal axis represents flat trim code and the vertical axis represents the slope of the curve1002shown inFIG. 10A. The temperature coefficient determined in step910from the curve1002is corrected by changing the flat trim code setting based on a curve1004.

FIG. 11is a block diagram depicting a programmable IC1according to an example in which the voltage reference200described herein can be used. The programmable IC1includes programmable logic3, configuration logic25, and configuration memory26. The programmable IC1can be coupled to external circuits, such as nonvolatile memory27, DRAM28, and other circuits29. The programmable logic3includes logic cells30, support circuits31, and programmable interconnect32. The logic cells30include circuits that can be configured to implement general logic functions of a plurality of inputs. The support circuits31include dedicated circuits, such as transceivers, input/output blocks, digital signal processors, memories, and the like. The logic cells and the support circuits31can be interconnected using the programmable interconnect32. Information for programming the logic cells30, for setting parameters of the support circuits31, and for programming the programmable interconnect32is stored in the configuration memory26by the configuration logic25. The configuration logic25can obtain the configuration data from the nonvolatile memory27or any other source (e.g., the DRAM28or from the other circuits29). In some examples, the programmable IC1includes a processing system2. The processing system2can include microprocessor(s), memory, support circuits, IO circuits, and the like.

FIG. 12illustrates a field programmable gate array (FPGA) implementation of the programmable IC1that includes a large number of different programmable tiles including transceivers37, configurable logic blocks (“CLBs”)33, random access memory blocks (“BRAMs”)34, input/output blocks (“IOBs”)36, configuration and clocking logic (“CONFIG/CLOCKS”)42, digital signal processing blocks (“DSPs”)35, specialized input/output blocks (“I/O”)41(e.g., configuration ports and clock ports), and other programmable logic39such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. The FPGA can also include PCIe interfaces40, analog-to-digital converters (ADC)38, and the like.

In some FPGAs, each programmable tile can include at least one programmable interconnect element (“INT”)43having connections to input and output terminals48of a programmable logic element within the same tile, as shown by examples included at the top ofFIG. 12. Each programmable interconnect element43can also include connections to interconnect segments49of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element43can also include connections to interconnect segments50of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments50) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments50) can span one or more logic blocks. The programmable interconnect elements43taken together with the general routing resources implement a programmable interconnect structure (“programmable interconnect”) for the illustrated FPGA.

In an example implementation, a CLB33can include a configurable logic element (“CLE”)44that can be programmed to implement user logic plus a single programmable interconnect element (“INT”)43. A BRAM34can include a BRAM logic element (“BRL”)45in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile35can include a DSP logic element (“DSPL”)46in addition to an appropriate number of programmable interconnect elements. An IOB36can include, for example, two instances of an input/output logic element (“IOL”)47in addition to one instance of the programmable interconnect element43. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element47typically are not confined to the area of the input/output logic element47.

Some FPGAs utilizing the architecture illustrated inFIG. 12include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic.

In an example, a method of trimming a voltage reference in an integrated circuit (IC) includes: selecting an approximate trim code for a reference circuit of the voltage reference configured to generate a proportional-to-temperature current and a corresponding first control voltage, and a complementary-to-temperature current and a corresponding second control voltage; at a first temperature, selecting a first trim code for a temperature coefficient (Tempco) circuit, controlled by the reference circuit to generate the voltage output, to set the voltage output to a desired voltage; at a second temperature, selecting a second trim code for the Tempco circuit to set the voltage output to the desired voltage; and selecting a trim code for the reference circuit based on the first trim code and the second trim code.

In an example, the method described above further includes storing the first trim code in the IC. In an example, the method described above further includes: obtaining the first trim code from the IC; and determining a slope of the trim code of the Tempco circuit over temperature based on the first trim code and the second trim code. In an example, the method described above, wherein the step of selecting the trim code for the reference circuit comprises: obtaining the trim code from a lookup table based on the slope of the trim code of the Tempco circuit. In an example, the method described above wherein the approximate trim code is determined based on a simulation of the voltage reference.

In an example, an apparatus for trimming a voltage reference in an integrated circuit (IC) includes: a memory; and a processor configured to execute code stored in the memory to: select an approximate trim code for a reference circuit of the voltage reference configured to generate a proportional-to-temperature current and a corresponding first control voltage, and a complementary-to-temperature current and a corresponding second control voltage; at a first temperature, select a first trim code for a temperature coefficient (Tempco) circuit, controlled by the reference circuit to generate the voltage output, to set the voltage output to a desired voltage; at a second temperature, select a second trim code for the Tempco circuit to set the voltage output to the desired voltage; and select a trim code for the reference circuit based on the first trim code and the second trim code.

In an example, the apparatus described above wherein the processor is further configured to execute the code to: store the first trim code in the IC. In an example, the apparatus described above wherein the processor is further configured to execute the code to: obtain the first trim code from the IC; determine a slope of the trim code of the Tempco circuit over temperature based on the first trim code and the second trim code. In an example, the apparatus described above wherein the processor selects the trim code for the reference circuit by: obtaining the trim code from a lookup table based on the slope of the trim code of the Tempco circuit. In an example, the apparatus described above wherein the approximate trim code is determined based on a simulation of the voltage reference.