Semiconductor device manufacturing method and semiconductor device

A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of prior Japanese Patent Application No. 2013-240272 filed on Nov. 20, 2013, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments relate to a semiconductor device manufacturing method and a semiconductor.

BACKGROUND

There have recently been proposed nonvolatile semiconductor storages, such as a flash memory including a memory cell with a select transistor and a memory transistor. As memory transistors, a floating gate type memory transistor and a SONOS (Silicon Oxide Nitride Oxide Silicon) type memory transistor are known.

In a SONOS type memory transistor, an insulating film having a structure, in which a lower insulating film, a charge storage film, and an upper insulating film are stacked, is used as a gate insulating film. In the SONOS type memory transistor, data storage or erasure is performed by loading or unloading charges into or from the charge storage film.

SUMMARY

According to an aspect of the embodiments, a semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching using the first resist pattern as a mask; forming a third film on the second film in the first region after removing the first resist pattern; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first film, the second film, and the third film under the first gate electrode by patterning the first film, the second film, and the third film using the first gate electrode as a mask.

DESCRIPTION OF EMBODIMENT

If the interval between adjacent ones of memory cells having a SONOS type memory transistor is short or if a charge storage film with high charge mobility is used in each memory cell, charges are exchanged between adjacent memory cells to decrease data retention. The term “data retention” refers to the time needed for stored data to be lost due to change in charges stored (held) in a charge storage film with time. A semiconductor device manufacturing method and a semiconductor device according to an embodiment will be described below with reference to the drawings. The configurations of the first to fourth embodiments below are illustrative only, and semiconductor device manufacturing methods and semiconductor devices according to embodiments are not limited to the configurations of the first to fourth embodiments.

First Embodiment

A semiconductor device manufacturing method and a semiconductor device according to a first embodiment will be described. The first embodiment will be described in the context of a semiconductor device having a flash memory and a logic circuit.FIG. 1is a plan view illustrating a semiconductor device manufacturing process according to the first embodiment and a partial plan view of a select transistor region1and a memory transistor region2of a semiconductor device. The memory transistor region2is an example of a first region. The select transistor region1is an example of a second region.

The steps illustrated inFIGS. 2A to 2Ewill be described. A semiconductor substrate11is first prepared. The semiconductor substrate11is, for example, a P-type silicon substrate. The semiconductor substrate11includes a memory region where a flash memory cell is to be formed and a logic region. The memory region includes the select transistor region1and the memory transistor region2. The logic region includes a first logic region3and a second logic region4. The first logic region3has a P-type MOS (Metal Oxide Semiconductor) transistor formation region3A and an N-type MOS transistor formation region3B. The second logic region4has a P-type MOS transistor formation region4A and an N-type MOS transistor formation region4B.

Element isolation insulating films12are formed in the semiconductor substrate11by, for example, an STI (Shallow Trench Isolation) method. The element isolation insulating film12is, for example, a silicon oxide film (SiO2film). The element isolation insulating films12in the select transistor region1and the memory transistor region2are formed in the semiconductor substrate11so as to extend parallel to a bit line direction (gate length direction). InFIG. 1, the bit line direction is denoted by X while a word line direction (gate width direction) is denoted by Y. Sacrificial oxide films13are then formed on a surface of the semiconductor substrate11by, for example, a thermal oxidation method. The sacrificial oxide film13is, for example, a silicon oxide film.

The formation of the element isolation insulating films12and the sacrificial oxide films13may be performed by, for example, the method below. A silicon oxide film is formed on the semiconductor substrate11by a thermal oxidation method or a CVD (Chemical Vapor Deposition) method. A silicon nitride film is formed on the silicon oxide film by a CVD method. A resist film is formed on (applied to) the silicon nitride film. A mask pattern of a photomask for element isolation is exposure-transferred to the resist film using an exposure apparatus. A resist pattern is formed above the semiconductor substrate11by developing the resist film. A silicon nitride film pattern is formed by dry-etching the silicon nitride film using the resist pattern as a mask. Trenches are formed in the semiconductor substrate11by performing anisotropic dry etching using the silicon nitride film pattern as a mask. A silicon oxide film is formed in the trenches and on the silicon nitride film pattern by a high-density plasma CVD method. The silicon oxide film in the trenches and on the silicon nitride film pattern is planarized by a CMP (Chemical Mechanical Polishing) method using the silicon nitride film pattern as a polishing stopper, thereby forming the element isolation insulating films12in the semiconductor substrate11. With the formation of the element isolation insulating films12in the semiconductor substrate11, active regions (element formation regions) are delimited in the semiconductor substrate11. The silicon oxide film in each element isolation insulating film is densified by annealing. The silicon nitride film pattern is removed by phosphoric acid boiling, and the silicon oxide films formed on the semiconductor substrate11are exposed. The exposed silicon oxide films are removed with hydrofluoric acid, and the sacrificial oxide films13are then formed on the semiconductor substrate11to a thickness of, e.g., 10 nm by, for example, a thermal oxidation method.

The steps illustrated inFIGS. 3A to 3Ewill be described. Impurities are ion-implanted into the semiconductor substrate11, thereby forming N-type wells14and P-type wells15in the semiconductor substrate11. The N-type wells14are formed in the semiconductor substrate11in the select transistor region1, the memory transistor region2, the P-type MOS transistor formation region3A of the first logic region3, and the P-type MOS transistor formation region4A of the second logic region4. The P-type wells15are formed in the semiconductor substrate11in the N-type MOS transistor formation region3B of the first logic region3and the N-type MOS transistor formation region4B of the second logic region4. An impurity for threshold voltage control is ion-implanted into the semiconductor substrate11. Note that a whole region except an N-type impurity implantation region is covered with a resist pattern at the time of ion implantation of an N-type impurity. The whole region except a P-type impurity implantation region is covered with a resist pattern at the time of ion implantation of a P-type impurity. The separate ion implantation operations for the impurities are also performed on each occasion of ion implantation (to be described below).

The steps illustrated inFIGS. 4A to 4Ewill be described. After the sacrificial oxide films13are removed by wet etching using hydrofluoric acid (HF), tunnel oxide films (lower insulating films)16are formed on the surface of the semiconductor substrate11. The tunnel oxide film16is an example of a first film. The tunnel oxide films16are formed by, for example, a thermal oxidation method, a radical oxidation method, a plasma oxidation method, or a CVD method. The tunnel oxide film16is, for example, a silicon oxide film. The thickness of the tunnel oxide film16is, for example, about not less than 2 nm and not more than 15 nm. A charge storage film17is formed on the element isolation insulating films12and on the tunnel oxide films16by a CVD method. The charge storage film17is an example of a second film. The charge storage film17is, for example, a silicon nitride film (SiN film). The thickness of the charge storage film17is, for example, about not less than 5 nm and not more than 30 nm. A surface oxide film (not illustrated) may be formed on the charge storage film17by, for example, a plasma oxidation method. The formation of the surface oxide film is dispensable and may be omitted.

The steps illustrated inFIGS. 5A to 5Ewill be described. A resist pattern18which covers the memory transistor region2and is open in the select transistor region1, the first logic region3, and the second logic region4is formed above the semiconductor substrate11by, for example, photolithography. The resist pattern18is an example of a second resist pattern. The thickness of the resist pattern18is, for example, about not less than 300 nm and not more than 1000 nm. An anti-reflection film may be formed under or on the resist pattern18.

The steps illustrated inFIGS. 6A to 6Ewill be described. Anisotropic dry etching is performed using the resist pattern18as a mask under an etching condition with a high selection ratio (selectivity), thereby etching the charge storage film17. With this etching, the charge storage films17in the select transistor region1, the first logic region3, and the second logic region4are removed. The anisotropic dry etching under the etching condition with the high selection ratio in each step illustrated inFIG. 6A to 6Eis an example of second etching. If a surface oxide film is formed on each charge storage film17, the surface oxide film and the charge storage film17are removed. The etching condition with the high selection ratio is that the etching rate of a silicon nitride film is higher than that of an oxide film. An etching gas is, for example, (1) CHxFy(x and y are the numbers of atoms), a gaseous mixture of Ar and O2, (2) a gaseous mixture of SF6, Ar, and O2, (3) a gaseous mixture of SF6, He, and O2, (4) a gaseous mixture of NF3and O2, (5) a gaseous mixture of CF4and O2, or (6) a gaseous mixture of CF4, HBr, and O2. Since the tunnel oxide films16function as etching stopper films, the etching stops at the tunnel oxide films16, which inhibits damage to the semiconductor substrate11.

Under the etching condition with the high selection ratio, the etching gas includes O2to improve the selection ratio of a nitride film to an oxide film. In this case, reaction between O2and the resist pattern18etches the resist pattern18, which causes the resist pattern18to retreat. Note that since the thickness of the resist pattern18is sufficiently large, even if the anisotropic dry etching is performed under the etching condition with the high selection ratio, the resist pattern18that covers the memory transistor region2remains. The resist pattern18is then removed by, for example, chemical solution treatment using a sulfuric acid-hydrogen peroxide mixture (SPM) and an ammonia-hydrogen peroxide mixture (APM).

The steps illustrated inFIGS. 7A to 7Ewill be described. A resist pattern19which is open above the element isolation insulating films12in the select transistor region1and the memory transistor region2is formed above the semiconductor substrate11by, for example, photolithography. The resist pattern19is an example of a first resist pattern. An anti-reflection film may be formed under or on the resist pattern19. The element isolation insulating films12in the select transistor region1and the memory transistor region2are formed so as to extend parallel to the bit line direction. Thus, the resist pattern19has openings which extend parallel to the bit line direction. The resist pattern19covers the select transistor region1and the memory transistor region2except the element isolation insulating films12, the first logic region3, and the second logic region4.

The steps illustrated inFIGS. 8A to 8Ewill be described. Anisotropic dry etching is performed using the resist pattern19as a mask under an etching condition with a low selection ratio, thereby etching the charge storage film17. With this etching, the charge storage films17on the element isolation insulating films12in the memory transistor region2are removed. The anisotropic dry etching under the etching condition with the low selection ratio in each step illustrated inFIGS. 8A to 8Eis an example of first etching. If a surface oxide film is formed on each charge storage film17, the surface oxide film and the charge storage film17are removed.

The element isolation insulating films12in the select transistor region1and the memory transistor region2are formed so as to extend parallel to the bit line direction. Thus, the removal of the charge storage films17on the element isolation insulating films12in the memory transistor region2separates the charge storage film17in the memory transistor region2into a plurality of parts in the word line direction. Upper portions of the element isolation insulating films12in the select transistor region1and the memory transistor region2are partially removed.

The etching condition with the low selection ratio is that the etching rate of a silicon nitride film is lower than that of an oxide film. An etching gas is, for example, (1) CF4gas, (2) SF6gas, (3) NF3gas, (4) Cl2gas, (5) a gaseous mixture of CF4, Ar, and O2, (6) a gaseous mixture of SF6, Ar, and O2, (7) a gaseous mixture of NF3, Ar, and O2, and (8) a gaseous mixture of Cl2, Ar, and O2.

The openings of the resist pattern19are located above the element isolation insulating films12. For this reason, although the element isolation insulating films12are shaved after the removal of the charge storage films17, the semiconductor substrate11is not shaved. Thus, damage to the semiconductor substrate11is inhibited at the time of the removal of the charge storage films17on the element isolation insulating films12in the memory transistor region2.

Under the etching condition with the low selection ratio, the etching gas does not include O2or the concentration of O2to be included in the etching gas is set to be low. This inhibits the resist pattern19from retreating due to the etching. In the case of, for example, a gaseous mixture of CF4, Ar, and O2, if the concentration of O2is not more than that of CF4, the resist pattern19is inhibited from retreating due to the etching. The resist pattern19is then removed by, for example, chemical solution treatment using a sulfuric acid-hydrogen peroxide mixture (SPM) and an ammonia-hydrogen peroxide mixture (APM).

The steps illustrated inFIGS. 9A to 9Ewill be described. The tunnel oxide films16in the select transistor region1, the first logic region3, and the second logic region4are removed by performing wet etching using hydrofluoric acid. The wet etching using hydrofluoric acid in each step illustrated inFIGS. 9A to 9Eis an example of third etching. If a surface oxide film is formed on each charge storage film17, the tunnel oxide films16and the surface oxide films in the select transistor region1, the first logic region3, and the second logic region4are removed. Since the etching rate of a silicon nitride film with respect to hydrofluoric acid is low, if the charge storage film17is a silicon nitride film, the charge storage film17is not removed. Since the charge storage film17is formed on each tunnel oxide film16in the memory transistor region2, the tunnel oxide films16in the memory transistor region2are not removed.

The steps illustrated inFIGS. 10A to 10Ewill be described. An oxide film is formed by, for example, a radical oxidation method using H2gas and O2gas at a temperature of about not less than 400° C. and not more than 1100° C. The thickness of the oxide film is, for example, about not less than 5 nm and not more than 15 nm.

This oxide film formation causes gate oxide films (gate insulating films)21to be formed on the surface of the semiconductor substrate11in the select transistor region1and top oxide films (upper insulating films)22to be formed on the charge storage films17in the memory transistor region2. The top oxide film22is an example of a third film. The gate oxide film21is an example of a fourth film. The gate oxide film21and the top oxide film22are, for example, silicon oxide films. The oxide film formation also causes gate oxide films (gate insulating films)23to be formed on the surface of the semiconductor substrate11in the first logic region3and gate oxide films (gate insulating films)24to be formed on the surface of the semiconductor substrate11in the second logic region4. The gate oxide films23and24are, for example, silicon oxide films. The oxide film formation further causes sidewalls of each charge storage film17in the memory transistor region2to be oxidized.

The oxide films may be formed by a plasma oxidation method instead of the radical oxidation method. The radical oxidation method or the plasma oxidation method is used to oxidize the surface of the semiconductor substrate11and the charge storage films17in the same step. The use of the radical oxidation method or the plasma oxidation method makes oxidation of the charge storage films17easier than use of another oxidation method, such as a thermal oxidation method.

The steps illustrated inFIGS. 11A to 11Ewill be described. A resist pattern25which is open in the first logic region3is formed above the semiconductor substrate11by performing, for example, photolithography. An anti-reflection film may be formed under or on the resist pattern25. The gate oxide films23in the first logic region3are removed using the resist pattern25as a mask by wet etching using hydrofluoric acid.

The steps illustrated inFIGS. 12A to 12Ewill be described. The resist pattern25is removed by, for example, chemical solution treatment using a sulfuric acid-hydrogen peroxide mixture (SPM) and an ammonia-hydrogen peroxide mixture (APM). Gate oxide films (gate insulating films)26are formed on the surface of the semiconductor substrate11in the first logic region3by, for example, a thermal oxidation method. The thickness of the gate oxide film26is, for example, about not less than 1 nm and not more than 3 nm. With this thermal oxidation method, the gate oxide films21in the select transistor region1and the gate oxide films24in the second logic region4grow. The thicknesses of the gate oxide film21and the gate oxide film24become about 8 nm.

The steps illustrated inFIGS. 13A to 13Ewill be described. Polysilicon27which covers the select transistor region1, the memory transistor region2, the first logic region3, and the second logic region4is formed by, for example, a CVD method.

The steps illustrated inFIGS. 14A to 14Ewill be described. A resist pattern (not illustrated) is formed on the polysilicon27by, for example, photolithography. Anisotropic dry etching is then performed using the resist pattern formed on the polysilicon27as a mask, thereby patterning the polysilicon27. The patterning of the polysilicon27causes a gate electrode31to be formed on the gate oxide films21in the select transistor region1and a gate electrode32to be formed on the top oxide films22in the memory transistor region2. The gate electrode32is an example of a first gate electrode. The gate electrode31is an example of a second gate electrode. The patterning of the polysilicon27also causes gate electrodes33to be formed on the gate oxide films26in the first logic region3and gate electrodes34to be formed on the gate oxide films24in the second logic region4.

The steps illustrated inFIGS. 15A to 15Ewill be described. Wet etching using hydrofluoric acid is performed using the gate electrodes31to34as masks, thereby patterning the gate oxide films21,24, and26and the top oxide films22. With this patterning, the gate oxide films21,24, and26and the top oxide films22in regions not covered with the gate electrodes31to34are removed. Thus, the gate oxide films21remain under the gate electrode31, and the top oxide films22remain under the gate electrode32. The gate oxide film21formed under the gate electrode31is an example of a second insulating film. The gate oxide films26remain under the gate electrodes33while the gate oxide films24remain under the gate electrodes34.

The steps illustrated inFIGS. 16A to 16Ewill be described. A resist pattern35which is open in the select transistor region1and the memory transistor region2is formed above the semiconductor substrate11by performing, for example, photolithography. Anisotropic dry etching is performed using the gate electrodes31and32and the resist pattern35as masks, thereby patterning the charge storage films17in the memory transistor region2. With the patterning of the charge storage films17, the charge storage films17in regions not covered with the gate electrode32are removed. Wet etching using hydrofluoric acid is performed using the gate electrodes31and32and the resist pattern35as masks, thereby patterning the tunnel oxide films16in the memory transistor region2. The resist pattern35is then removed by, for example, chemical solution treatment using a sulfuric acid-hydrogen peroxide mixture (SPM) and an ammonia-hydrogen peroxide mixture (APM).

With the patterning of the tunnel oxide films16, the tunnel oxide films16in regions not covered with the gate electrode32are removed. The patterning of the tunnel oxide films16and the charge storage films17causes gate insulating films (ONO films), each having the tunnel oxide film16, the charge storage film17, and the top oxide film22, to be formed (delimited) under the gate electrode32in the memory transistor region2. The tunnel oxide films16, the charge storage films17, and the top oxide films22are patterned using the gate electrode32as a mask. For this reason, each gate insulating film having the tunnel oxide film16, the charge storage film17, and the top oxide film22is formed to be self-aligned with the gate electrode32. The gate insulating film having the tunnel oxide film16, the charge storage film17, and the top oxide film22is an example of a first insulating film.

The steps illustrated inFIGS. 17A to 17Ewill be described. Formation of a resist pattern (not illustrated) by, for example, photolithography, ion implantation of impurities, and removal of the resist pattern are appropriately repeated. With the repetition, P-type LDD (Lightly Doped Drain) regions36are formed in the select transistor region1and the memory transistor region2. P-type LDD regions37are formed in the P-type MOS transistor formation region3A while N-type LDD regions38are formed in the N-type MOS transistor formation region3B. P-type LDD regions39are formed in the P-type MOS transistor formation region4A while N-type LDD regions40are formed in the N-type MOS transistor formation region4B.

The steps illustrated inFIGS. 18A to 18Ewill be described. An oxide film is formed across the surface of the semiconductor substrate11by, for example, a CVD method, and etchback is performed, thereby forming sidewalls41on side surfaces of the gate electrodes31to34. Formation of a resist pattern (not illustrated) by, for example, photolithography, ion implantation of impurities, and removal of the resist pattern are then appropriately repeated. With the repetition, P-type source-drain regions42are formed in the select transistor region1and the memory transistor region2. P-type source-drain regions43are formed in the P-type MOS transistor formation region3A while N-type source-drain regions44are formed in the N-type MOS transistor formation region3B. P-type source-drain regions45are formed in the P-type MOS transistor formation region4A while N-type source-drain regions46are formed in the N-type MOS transistor formation region4B. A metal film of, for example, Ni (nickel), Ti (titanium), or Co (cobalt) is then formed on the semiconductor substrate11, and heat treatment is performed. With these operations, silicides47are formed on the gate electrodes31to34, on the P-type source-drain regions42,43, and45, and on the N-type source-drain regions44and46.

A plurality of select transistors51are formed in the select transistor region1while a plurality of memory transistors52are formed in the memory transistor region2. The memory transistor52is an example of a first transistor. The select transistor51is an example of a second transistor. A plurality of P-type MOS transistors53are formed in the P-type MOS transistor formation region3A while a plurality of N-type MOS transistors54are formed in the N-type MOS transistor formation region3B. The P-type MOS transistor53and the N-type MOS transistor54are, for example, MOS transistors which are driven at, for example, 1.2 V. A plurality of P-type MOS transistors55are formed in the P-type MOS transistor formation region4A while a plurality of N-type MOS transistors56are formed in the N-type MOS transistor formation region4B. The P-type MOS transistor55and the N-type MOS transistor56are, for example, MOS transistors which are driven at, for example, 3.3 V. After an interlayer insulating film, contact holes, contact plugs, and a piece of wiring, and the like are formed, desired back-end processing is performed, thereby manufacturing the semiconductor device.

According to the first embodiment, the charge storage film17is separated into a plurality of parts in the word line direction. That is, the charge storage films17of the memory transistors52adjacent in the word line direction are separate, and the charge storage films17of the memory transistors52adjacent in the word line direction are not connected to each other. Additionally, the sidewalls of the charge storage film17of each memory transistor52are oxidized, and the top oxide film22is formed so as to cover the charge storage film17. With this configuration, charges are inhibited from being transferred between the charge storage films17of the memory transistors52adjacent in the word line direction. Thus, charges stored (retained) in the charge storage film17of the memory transistor52are inhibited from changing, which allows inhibition of decrease in data retention. For example, even if the interval between the memory transistors52adjacent in the word line direction is short or if the charge storage film17with high charge mobility is used, charges stored in the charge storage film17are inhibited from changing, which allows inhibition of decrease in data retention.

The structure of the memory transistor52according to the first embodiment will be described. The tunnel oxide films16, the charge storage films17, and the top oxide films22of the memory transistors52adjacent in the word line direction are not connected to each other, respectively. Thus, the gate insulating films (the tunnel oxide films16, the charge storage films17, and the top oxide films22) of the memory transistors52adjacent in the word line direction are separate from each other. The gate electrodes32of the memory transistors52adjacent in the word line direction are connected to each other. The gate electrode32is formed between the memory transistors52adjacent in the word line direction. An upper portion of each element isolation insulating film12in the memory transistor region2is partially removed. For this reason, the gate electrodes32are formed so as to cover side surfaces of the tunnel oxide films16, the charge storage films17, and the top oxide films22in the word line direction.

The structure of the select transistor51according to the first embodiment will be described. The gate oxide films21of the select transistors51adjacent in the word line direction are not connected to each other. The gate electrodes31of the select transistors51adjacent in the word line direction are connected to each other.

In the case of a floating gate type memory transistor, an impurity may not be implanted into a gate electrode of a select transistor at the time of source-drain region formation, and a sufficient amount of impurity may not be implanted into the gate electrode of the select transistor. For this reason, a floating gate type memory transistor may cause the problem of depletion of a gate electrode of a select transistor.

The gate electrode31of each select transistor51and the gate electrode32of each memory transistor52are formed in the same layer. For this reason, when the P-type source-drain regions42are to be formed in the select transistor region1and the memory transistor region2, an impurity can be implanted into the gate electrodes31of the select transistors51and the gate electrodes32of the memory transistors52. Thus, the impurity concentration in the gate electrode31of each select transistor51can be increased, and the gate electrode31of each select transistor51can be inhibited from being depleted. As a result, the threshold voltage of each select transistor51can be decreased, which allows decrease in the operating voltage of each select transistor51.

Modification of First Embodiment

The first embodiment may be modified in the manner below. The steps illustrated inFIGS. 5A to 6Eand the steps illustrated inFIGS. 7A to 8Emay be interchanged. That is, the steps illustrated inFIGS. 7A to 8Emay be performed after the steps illustrated inFIGS. 4A to 4Eare performed, and the steps illustrated inFIGS. 5A to 6Emay then be performed.

Second Embodiment

A semiconductor device manufacturing method and a semiconductor device according to a second embodiment will be described. The second embodiment will be described in the context of a semiconductor device having a flash memory and a logic circuit. As the process leading to steps of forming N-type wells14and P-type wells15in a semiconductor substrate11and ion-implanting an impurity for threshold voltage control into the semiconductor substrate11in the semiconductor device manufacturing method according to the second embodiment, the same steps as those illustrated inFIGS. 1 to 3Ein the first embodiment are performed. Since the steps illustrated inFIGS. 1 to 3Ein the first embodiment have already been described, a description thereof will be omitted.

The steps illustrated inFIGS. 19A to 19Ewill be described. After sacrificial oxide films13are removed by wet etching using hydrofluoric acid (HF), tunnel oxide films (lower insulating films)16are formed on a surface of the semiconductor substrate11. The tunnel oxide films16are formed by, for example, a thermal oxidation method, a radical oxidation method, a plasma oxidation method, or a CVD method. The tunnel oxide film16is, for example, a silicon oxide film. The thickness of the tunnel oxide film16is, for example, about not less than 2 nm and not more than 15 nm. A charge storage film61is formed on element isolation insulating films12and on the tunnel oxide films16by a plasma CVD method. The charge storage film61is an example of a second film. The charge storage film61is, for example, a plasma silicon nitride film (P—SiN film). The thickness of the charge storage film61is, for example, about not less than 5 nm and not more than 30 nm. The plasma CVD method is preferably such that, for example, a gaseous mixture of SiH4, NH3, and N2is used and such that the ratio of SiH4to NH3(SiH4/NH3) is not less than 0.1 and not more than 0.4. Alternatively, the plasma CVD method may use, for example, a gaseous mixture of SiH4and N2or a gaseous mixture of SiH4and NH3. A surface oxide film (not illustrated) may then be formed on the charge storage film61by, for example, a plasma oxidation method. The formation of the surface oxide film is dispensable and may be omitted.

The steps illustrated inFIGS. 20A to 20Ewill be described. A resist pattern62which covers the memory transistor region2and is open in the select transistor region1, a first logic region3, and a second logic region4is formed above the semiconductor substrate11by, for example, photolithography. The resist pattern62is an example of a second resist pattern. An anti-reflection film may be formed under or on the resist pattern62.

The steps illustrated inFIGS. 21A to 21Ewill be described. Wet etching using hydrofluoric acid is performed using the resist pattern62as a mask, thereby etching the charge storage film61. With this etching, the charge storage films61in the select transistor region1, the first logic region3, and the second logic region4are removed. The wet etching using hydrofluoric acid in each step illustrated inFIGS. 21A to 21Eis an example of second etching. Since the etching rate of a plasma silicon nitride film is high in the wet etching using hydrofluoric acid, the charge storage film61can be easily removed by the wet etching using hydrofluoric acid. The resist pattern62is then removed by, for example, chemical solution treatment using a sulfuric acid-hydrogen peroxide mixture (SPM) and an ammonia-hydrogen peroxide mixture (APM).

The steps illustrated inFIGS. 22A to 22Ewill be described. A resist pattern63which is open above the element isolation insulating films12in the select transistor region1and the memory transistor region2is formed above the semiconductor substrate11by, for example, photolithography. The resist pattern63is an example of a first resist pattern. An anti-reflection film may be formed under or on the resist pattern63. The element isolation insulating films12in the select transistor region1and the memory transistor region2are formed so as to extend parallel to a bit line direction. Thus, the resist pattern63has openings which extend parallel to the bit line direction. The resist pattern63covers the select transistor region1and the memory transistor region2except the element isolation insulating films12, the first logic region3, and the second logic region4.

The steps illustrated inFIGS. 23A to 23Ewill be described. Anisotropic dry etching is performed using the resist pattern63as a mask under an etching condition with a low selection ratio, thereby etching the charge storage film61. With this etching, the charge storage films61on the element isolation insulating films12in the memory transistor region2are removed. The anisotropic dry etching under the etching condition with the low selection ratio in each step illustrated inFIGS. 23A to 23Eis an example of first etching. If a surface oxide film is formed on each charge storage film61, the surface oxide film and the charge storage film61are removed. The element isolation insulating films12in the select transistor region1and the memory transistor region2are formed so as to extend parallel to the bit line direction. Thus, the removal of the charge storage films61on the element isolation insulating films12in the memory transistor region2separates the charge storage film61in the memory transistor region2into a plurality of parts in a word line direction. Additionally, upper portions of the element isolation insulating films12in the select transistor region1and the memory transistor region2are partially removed. The etching condition with the low selection ratio and the type of an etching gas are the same as those in the first embodiment.

The openings of the resist pattern63are located above the element isolation insulating films12. For this reason, although the element isolation insulating films12are shaved after the removal of the charge storage films61, the semiconductor substrate11is not shaved. Thus, damage to the semiconductor substrate11is inhibited at the time of the removal of the charge storage films61on the element isolation insulating films12in the memory transistor region2.

Under the etching condition with the low selection ratio, the etching gas does not include O2or the concentration of O2to be included in the etching gas is set to be low. This inhibits the resist pattern63from retreating due to the etching. In the case of, for example, a gaseous mixture of CF4, Ar, and O2, if the concentration of O2is not more than that of CF4, the resist pattern63is inhibited from retreating due to the etching. The resist pattern63is then removed by, for example, chemical solution treatment using a sulfuric acid-hydrogen peroxide mixture (SPM) and an ammonia-hydrogen peroxide mixture (APM).

The steps illustrated inFIGS. 24A to 24Ewill be described. Annealing is performed, for example, under the condition in an atmosphere of nitrogen (N2) at about 750° C. for about 90 seconds. Alternatively, the annealing may be performed under the condition in an atmosphere of nitrogen at about 800° C. for about 30 seconds. A thermal oxidation method, a radical oxidation method, or a plasma oxidation method may be performed instead of the annealing. Heat treatment through the annealing, the thermal oxidation method, the radical oxidation method, or the plasma oxidation method decreases the etching rate of a plasma silicon nitride film with respect to hydrofluoric acid.

FIG. 25is a graph illustrating the etching rate of a plasma silicon nitride film with respect to hydrofluoric acid. The ordinate represents the amount of etching of a plasma silicon nitride film while the abscissa represents the amount of hydrofluoric acid. The amount of hydrofluoric acid is expressed in terms of the amount of etching of a thermal oxide film. A solid line A indicates the etching rate of a plasma silicon nitride film which is formed using a gaseous mixture of SiH4, NH3and N2with the ratio SiH4/NH3set to 0.1 with respect to hydrofluoric acid. A solid line B indicates the etching rate of a plasma silicon nitride film which is formed using a gaseous mixture of SiH4, NH3and N2with the ratio SiH4/NH3set to 0.33 with respect to hydrofluoric acid. A dotted line C indicates the etching rate of a plasma silicon nitride film which is obtained after a plasma silicon nitride film having the film quality indicated by the solid line A is annealed with respect to hydrofluoric acid. A dotted line D indicates the etching rate of a plasma silicon nitride film which is obtained after a plasma silicon nitride film having the film quality indicated by the solid line B is annealed with respect to hydrofluoric acid. The annealing is performed under the condition in an atmosphere of nitrogen at 750° C. for 90 seconds.

As illustrated inFIG. 25, the etching rate of a plasma silicon nitride film with respect to hydrofluoric acid decreases with increase in the ratio SiH4/NH3in a gaseous mixture of SiH4, NH3and N2. Additionally, as illustrated inFIG. 25, the etching rate of a plasma silicon nitride film with respect to hydrofluoric acid is different between before annealing and after annealing. After annealing, the etching rate of a plasma silicon nitride film with respect to hydrofluoric acid is lower. For example, if the ratio SiH4/NH3in a gaseous mixture of SiH4, NH3and N2is 0. 33, annealing greatly decreases the etching rate of a plasma silicon nitride film with respect to hydrofluoric acid.

The steps illustrated inFIGS. 26A to 26Ewill be described. The tunnel oxide films16in the select transistor region1, the first logic region3, and the second logic region4are removed by performing wet etching using hydrofluoric acid. The wet etching using hydrofluoric acid in each step illustrated inFIGS. 26A to 26Eis an example of third etching. If a surface oxide film is formed on each charge storage film61, the tunnel oxide films16and the surface oxide films in the select transistor region1, the first logic region3, and the second logic region4are removed. The heat treatment has been performed in each step illustrated inFIGS. 24A to 24E. Since the charge storage film61has a decreased etching rate with respect to hydrofluoric acid, the charge storage films61in the memory transistor region2are not removed. Additionally, since the charge storage film61is formed on each tunnel oxide film16in the memory transistor region2, the tunnel oxide films16in the memory transistor region2are not removed.

The steps illustrated inFIGS. 27A to 27Ewill be described. An oxide film is formed by, for example, a radical oxidation method using H2gas and O2gas at a temperature of about not less than 400° C. and not more than 1100° C. The thickness of the oxide film is, for example, about not less than 5 nm and not more than 15 nm.

This oxide film formation causes gate oxide films (gate insulating films)21to be formed on the surface of the semiconductor substrate11in the select transistor region1and top oxide films (upper insulating films)22to be formed on the charge storage films61in the memory transistor region2. The gate oxide film21and the top oxide film22are, for example, silicon oxide films. The oxide film formation also causes gate oxide films (gate insulating films)23to be formed on the surface of the semiconductor substrate11in the first logic region3and gate oxide films (gate insulating films)24to be formed on the surface of the semiconductor substrate11in the second logic region4. The gate oxide films23and24are, for example, silicon oxide films. The oxide film formation further causes sidewalls of each charge storage film61in the memory transistor region2to be oxidized.

The oxide films may be formed by a plasma oxidation method instead of the radical oxidation method. The radical oxidation method or the plasma oxidation method is used to oxidize the surface of the semiconductor substrate11and the charge storage films61in the same step. The use of the radical oxidation method or the plasma oxidation method makes oxidation of the charge storage films61easier than use of another oxidation method, such as a thermal oxidation method. After the steps illustrated inFIGS. 27A to 27E, the same steps as those illustrated inFIGS. 11A to 18Ein the first embodiment are performed. Since the steps illustrated inFIGS. 11A to 18Ein the first embodiment have already been described, a description thereof will be omitted. Additionally, since the structure of a select transistor51and the structure of a memory transistor52in the second embodiment are the same as those in the first embodiment, a description thereof will be omitted.

According to the second embodiment, the charge storage film61is separated into a plurality of parts in the word line direction. That is, the charge storage films61of the adjacent memory transistors52are separate, and the charge storage films61of the adjacent memory transistors52are not connected to each other. Additionally, the sidewalls of the charge storage film61of each memory transistor52are oxidized, and the top oxide film22is formed so as to cover the charge storage film61. With this configuration, charges are inhibited from being transferred between the charge storage films61of the adjacent memory transistors52. Thus, charges stored (retained) in the charge storage film61of the memory transistor52are inhibited from changing, which allows inhibition of decrease in data retention. For example, even if the interval between the adjacent memory transistors52is short or if the charge storage film61with high charge mobility is used, charges stored in the charge storage film61are inhibited from changing, which allows inhibition of decrease in data retention.

The second embodiment may be modified in the manner below.

First Modification of Second Embodiment

The steps illustrated inFIGS. 20A to 21Eand the steps illustrated inFIGS. 22A to 23Emay be interchanged. That is, the steps illustrated inFIGS. 22A to 23Emay be performed after the steps illustrated inFIGS. 19A to 19Eare performed, and the steps illustrated inFIGS. 20A to 21Emay then be performed.

Second Modification of Second Embodiment

The steps illustrated inFIGS. 22A to 23Eand the steps illustrated inFIGS. 24A to 24Emay be interchanged. That is, the steps illustrated inFIGS. 24A to 24Emay be performed after the steps illustrated inFIGS. 21A to 21Eis performed, and the steps illustrated inFIGS. 22A to 23Emay then be performed.

Third Embodiment

A semiconductor device manufacturing method and a semiconductor device according to a third embodiment will be described. The third embodiment will be described in the context of a semiconductor device having a flash memory and a logic circuit. As the process leading to steps of forming N-type wells14and P-type wells15in a semiconductor substrate11and ion-implanting an impurity for threshold voltage control into the semiconductor substrate11in the semiconductor device manufacturing method according to the third embodiment, the same steps as those illustrated inFIGS. 1 to 3Ein the first embodiment are performed. Since the steps illustrated inFIGS. 1 to 3Ein the first embodiment have already been described, a description thereof will be omitted.

The steps illustrated inFIGS. 28A to 28Ewill be described. After sacrificial oxide films13are removed by wet etching using hydrofluoric acid (HF), tunnel oxide films (lower insulating films)16are formed on a surface of the semiconductor substrate11. The tunnel oxide films16are formed by, for example, a thermal oxidation method, a radical oxidation method, a plasma oxidation method, or a CVD method. The tunnel oxide film16is, for example, a silicon oxide film. The thickness of the tunnel oxide film16is, for example, about not less than 2 nm and not more than 15 nm. A charge storage film71is formed on element isolation insulating films12and on the tunnel oxide films16by a plasma CVD method. The charge storage film71is an example of a second film. The charge storage film71is, for example, a plasma silicon nitride film (P—SiN film). The thickness of the charge storage film71is, for example, about not less than 5 nm and not more than 30 nm. The plasma CVD method uses, for example, a gaseous mixture of SiH4, NH3, and N2. The plasma CVD method may use, for example, a gaseous mixture of SiH4and N2or a gaseous mixture of SiH4and NH3. Alternatively, a surface oxide film (not illustrated) may then be formed on the charge storage film71by, for example, a plasma oxidation method. The formation of the surface oxide film is dispensable and may be omitted.

The steps illustrated inFIGS. 29A to 29Ewill be described. A resist pattern72which covers the memory transistor region2and is open in the select transistor region1, a first logic region3, and a second logic region4is formed above the semiconductor substrate11by, for example, photolithography. The resist pattern72is an example of a second resist pattern. The thickness of the resist pattern72is, for example, about not less than 300 nm and not more than 1000 nm. An anti-reflection film may be formed under or on the resist pattern72.

The steps illustrated inFIGS. 30A to 30Ewill be described. Anisotropic dry etching is performed using the resist pattern72as a mask under an etching condition with a high selection ratio, thereby etching the charge storage film71. With this etching, the charge storage films71in the select transistor region1, the first logic region3, and the second logic region4are removed. The anisotropic dry etching under the etching condition with the high selection ratio in each step illustrated inFIGS. 30A to 30Eis an example of second etching. If a surface oxide film is formed on each charge storage film71, the surface oxide film and the charge storage film71are removed. The etching condition with the high selection ratio and the type of an etching gas are the same as those in the first embodiment. Since the tunnel oxide films16function as etching stopper films, the etching stops at the tunnel oxide films16, which inhibits damage to the semiconductor substrate11.

Under the etching condition with the high selection ratio, the etching gas includes O2to improve the selection ratio of a nitride film to an oxide film. In this case, reaction between O2and the resist pattern72etches the resist pattern72, which causes the resist pattern72to retreat. Note that since the thickness of the resist pattern72is sufficiently large, even if the anisotropic dry etching is performed under the etching condition with the high selection ratio, the resist pattern72that covers the memory transistor region2remains. The resist pattern72is then removed by, for example, chemical solution treatment using a sulfuric acid-hydrogen peroxide mixture (SPM) and an ammonia-hydrogen peroxide mixture (APM).

The steps illustrated inFIGS. 31A to 31Ewill be described. Sacrificial oxide films73are formed on the tunnel oxide films16and on the charge storage film71by, for example, a radical oxidation method or a plasma oxidation method. The sacrificial oxide film73is an example of a second oxide film. The sacrificial oxide film73is, for example, a silicon oxide film. Heat treatment through the radical oxidation method or the plasma oxidation method repairs damage to the semiconductor substrate11. Damage to the semiconductor substrate11is repaired by oxidizing a damaged part of the semiconductor substrate11by the radical oxidation method or the plasma oxidation method and removing the oxidized part in a subsequent step using hydrofluoric acid. For example, if the semiconductor substrate11has been damaged in the steps illustrated inFIGS. 30A to 30Eor another step, heat treatment is performed through the radical oxidation method or the plasma oxidation method, thereby repairing the damage to the semiconductor substrate11. The heat treatment decreases the etching rate of the charge storage film71with respect to hydrofluoric acid.

The steps illustrated inFIGS. 32A to 32Ewill be described. A resist pattern74which is open above the element isolation insulating films12in the select transistor region1and the memory transistor region2is formed above the semiconductor substrate11by, for example, photolithography. The resist pattern74is an example of a first resist pattern. An anti-reflection film may be formed under or on the resist pattern74. The element isolation insulating films12in the select transistor region1and the memory transistor region2are formed so as to extend parallel to a bit line direction. Thus, the resist pattern74has openings which extend parallel to the bit line direction. The resist pattern74covers the select transistor region1and the memory transistor region2except the element isolation insulating films12, the first logic region3, and the second logic region4.

The steps illustrated inFIGS. 33A to 33Ewill be described. Anisotropic dry etching is performed using the resist pattern74as a mask under an etching condition with a low selection ratio, thereby etching the charge storage film71. With this etching, the sacrificial oxide films73above the element isolation insulating films12in the memory transistor region2and the charge storage films71on the element isolation insulating films12in the memory transistor region2are removed. The anisotropic dry etching under the etching condition with the low selection ratio in each step illustrated inFIGS. 33A to 33Eis an example of first etching. If a surface oxide film is formed on each charge storage film71, the surface oxide film and the charge storage film71are removed.

The element isolation insulating films12in the select transistor region1and the memory transistor region2are formed so as to extend parallel to the bit line direction. Thus, the removal of the charge storage films71and the sacrificial oxide films73on the element isolation insulating films12in the memory transistor region2separates each of the charge storage film71and the sacrificial oxide film73in the memory transistor region2into a plurality of parts in a word line direction. Upper portions of the element isolation insulating films12in the select transistor region1and the memory transistor region2are partially removed. The etching condition with the low selection ratio and the type of an etching gas are the same as those in the first embodiment.

The openings of the resist pattern74are located above the element isolation insulating films12. For this reason, although the element isolation insulating films12are shaved after the removal of the charge storage films71and the sacrificial oxide films73, the semiconductor substrate11is not shaved. Thus, damage to the semiconductor substrate11is inhibited at the time of the removal of the charge storage films71on the element isolation insulating films12in the memory transistor region2.

Under the etching condition with the low selection ratio, the etching gas does not include O2or the concentration of O2to be included in the etching gas is set to be low. This inhibits the resist pattern74from retreating due to the etching. In the case of, for example, a gaseous mixture of CF4, Ar, and O2, if the concentration of O2is not more than that of CF4, the resist pattern74is inhibited from retreating due to the etching. The resist pattern74is then removed by, for example, chemical solution treatment using a sulfuric acid-hydrogen peroxide mixture (SPM) and an ammonia-hydrogen peroxide mixture (APM).

The steps illustrated inFIGS. 34A to 34Ewill be described. By performing wet etching using hydrofluoric acid, the tunnel oxide films16and the sacrificial oxide films73in the select transistor region1, the first logic region3, and the second logic region4are removed, and the sacrificial oxide films73in the memory transistor region2are removed. The wet etching using hydrofluoric acid in each step illustrated inFIGS. 34A to 34Eis an example of third etching. If a surface oxide film is formed on each charge storage film71, the tunnel oxide films16and the sacrificial oxide films73in the select transistor region1, the first logic region3, and the second logic region4and the sacrificial oxide films73and the surface oxide films in the memory transistor region2are removed. The heat treatment has been performed in each step illustrated inFIGS. 31A to 31E. Since the charge storage film71has a decreased etching rate with respect to hydrofluoric acid, the charge storage films71in the memory transistor region2are not removed. Additionally, since the charge storage film71is formed on each tunnel oxide film16in the memory transistor region2, the tunnel oxide films16in the memory transistor region2are not removed.

The steps illustrated inFIGS. 35A to 35Ewill be described. An oxide film is formed by, for example, a radical oxidation method using H2gas and O2gas at a temperature of about not less than 400° C. and not more than 1100° C. The thickness of the oxide film is, for example, about not less than 5 nm and not more than 15 nm.

This oxide film formation causes gate oxide films (gate insulating films)21to be formed on the surface of the semiconductor substrate11in the select transistor region1and top oxide films (upper insulating films)22to be formed on the charge storage films71in the memory transistor region2. The gate oxide film21and the top oxide film22are, for example, silicon oxide films. The oxide film formation also causes gate oxide films (gate insulating films)23to be formed on the surface of the semiconductor substrate11in the first logic region3and gate oxide films (gate insulating films)24to be formed on the surface of the semiconductor substrate11in the second logic region4. The gate oxide films23and24are, for example, silicon oxide films. The oxide film formation further causes sidewalls of each charge storage film71in the memory transistor region2to be oxidized.

The oxide films may be formed by a plasma oxidation method instead of the radical oxidation method. The radical oxidation method or the plasma oxidation method is used to oxidize the surface of the semiconductor substrate11and the charge storage films71in the same step. The use of the radical oxidation method or the plasma oxidation method makes oxidation of the charge storage films71easier than use of another oxidation method, such as a thermal oxidation method. After the steps illustrated inFIGS. 35A to 35E, the same steps as those illustrated inFIGS. 11A to 18Ein the first embodiment are performed. Since the steps illustrated inFIGS. 11A to 18Ein the first embodiment have already been described, a description thereof will be omitted. Additionally, since the structure of a select transistor51and the structure of a memory transistor52in the third embodiment are the same as those in the first embodiment, a description thereof will be omitted.

According to the third embodiment, the charge storage film71is separated into a plurality of parts in the word line direction. That is, the charge storage films71of the adjacent memory transistors52are separate, and the charge storage films71of the adjacent memory transistors52are not connected to each other. Additionally, the sidewalls of the charge storage film71of each memory transistor52are oxidized, and the top oxide film22is formed so as to cover the charge storage film71. With this configuration, charges are inhibited from being transferred between the charge storage films71of the adjacent memory transistors52. Thus, charges stored (retained) in the charge storage film71of the memory transistor52are inhibited from changing, which allows inhibition of decrease in data retention. For example, even if the interval between the adjacent memory transistors52is short or if the charge storage film71with high charge mobility is used, charges stored in the charge storage film71are inhibited from changing, which allows inhibition of decrease in data retention.

The third embodiment may be modified in the manner below. A combination of the first to fourth modifications below may be applied to the semiconductor device manufacturing method and the semiconductor device according to the third embodiment.

First Modification of Third Embodiment

The steps illustrated inFIGS. 29A to 30Eand the steps illustrated inFIGS. 32A to 33Emay be interchanged. That is, the steps illustrated inFIGS. 32A to 33Emay be performed after the steps illustrated inFIGS. 28A to 28Eare performed, and the steps illustrated inFIGS. 29A to 30Emay then be performed.

Second Modification of Third Embodiment

The steps illustrated inFIGS. 31A to 31Eand the steps illustrated inFIGS. 32A to 33Emay be interchanged. That is, the steps illustrated inFIGS. 32A to 33Emay be performed after the steps illustrated inFIGS. 30A to 30Eare performed, and the steps illustrated inFIGS. 31A to 31Emay then be performed.

Third Modification of Third Embodiment

In the steps illustrated inFIGS. 30A to 30E, the charge storage film71may be etched by performing wet etching using hydrofluoric acid instead of anisotropic dry etching under the etching condition with the high selection ratio. That is, in the steps illustrated inFIGS. 30A to 30E, the charge storage films71in the select transistor region1, the first logic region3, and the second logic region4may be removed by performing wet etching using hydrofluoric acid, using the resist pattern72as a mask. Since the etching rate of a plasma silicon nitride film is high in the wet etching using hydrofluoric acid, the charge storage film71can be easily removed by the wet etching using hydrofluoric acid.

Fourth Modification of Third Embodiment

In the steps illustrated inFIGS. 28A to 28E, the charge storage film71may be formed on the element isolation insulating films12and on the tunnel oxide films16by a CVD method. In this case, the charge storage film71is a silicon nitride film. If the charge storage film71is a silicon nitride film, even when the heat treatment is performed by the radical oxidation method or the plasma oxidation method in the steps illustrated inFIGS. 31A to 31E, the etching rate of the charge storage film71with respect to hydrofluoric acid changes little. Note that since the etching rate of a silicon nitride film with respect to hydrofluoric acid is low, the charge storage films71in the memory transistor region2are not removed at the time of the wet etching using hydrofluoric acid in the steps illustrated inFIGS. 34A to 34E.

Fourth Embodiment

A semiconductor device manufacturing method and a semiconductor device according to a fourth embodiment will be described. The fourth embodiment will be described in the context of a semiconductor device having a flash memory and a logic circuit. As the process leading to steps of forming N-type wells14and P-type wells15in a semiconductor substrate11and ion-implanting an impurity for threshold voltage control into the semiconductor substrate11in the semiconductor device manufacturing method according to the fourth embodiment, the same steps as those illustrated inFIGS. 1 to 3Ein the first embodiment are performed. Since the steps illustrated in FIGS.1to3E in the first embodiment have already been described, a description thereof will be omitted.

The steps illustrated inFIGS. 36A to 36Ewill be described. After sacrificial oxide films13are removed by wet etching using hydrofluoric acid (HF), tunnel oxide films (lower insulating films)16are formed on a surface of the semiconductor substrate11. The tunnel oxide films16are formed by, for example, a thermal oxidation method, a radical oxidation method, a plasma oxidation method, or a CVD method. The tunnel oxide film16is, for example, a silicon oxide film. The thickness of the tunnel oxide film16is, for example, about not less than 2 nm and not more than 15 nm. A charge storage film81is formed on element isolation insulating films12and on the tunnel oxide films16by a plasma CVD method. The charge storage film81is an example of a second film. The charge storage film81is, for example, a plasma silicon nitride film (P—SiN film). The thickness of the charge storage film81is, for example, about not less than 5 nm and not more than 30 nm. The plasma CVD method uses, for example, a gaseous mixture of SiH4, NH3, and N2. The plasma CVD method may use, for example, a gaseous mixture of SiH4and N2or a gaseous mixture of SiH4and NH3. Alternatively, a surface oxide film (not illustrated) may then be formed on the charge storage film81by, for example, a plasma oxidation method. The formation of the surface oxide film is dispensable and may be omitted.

The steps illustrated inFIGS. 37A to 37Ewill be described. A resist pattern82which covers the memory transistor region2and is open in the select transistor region1, a first logic region3, and a second logic region4is formed above the semiconductor substrate11by, for example, photolithography. The resist pattern82is an example of a second resist pattern. The thickness of the resist pattern82is, for example, about not less than 300 nm and not more than 1000 nm. An anti-reflection film may be formed under or on the resist pattern82.

The steps illustrated inFIGS. 38A to 38Ewill be described. Anisotropic dry etching is performed using the resist pattern82as a mask under an etching condition with a high selection ratio, thereby etching the charge storage film81. With this etching, the charge storage films81in the select transistor region1, the first logic region3, and the second logic region4are removed. The anisotropic dry etching under the etching condition with the high selection ratio in each step illustrated inFIGS. 38A to 38Eis an example of second etching. If a surface oxide film is formed on each charge storage film81, the surface oxide film and the charge storage film81are removed. The etching condition with the high selection ratio and the type of an etching gas are the same as those in the first embodiment. Since the tunnel oxide films16function as etching stopper films, the etching stops at the tunnel oxide films16, which inhibits damage to the semiconductor substrate11. The resist pattern82is then removed by, for example, chemical solution treatment using a sulfuric acid-hydrogen peroxide mixture (SPM) and an ammonia-hydrogen peroxide mixture (APM).

The steps illustrated inFIGS. 39A to 39Ewill be described. A resist pattern83which is open above the element isolation insulating films12in the select transistor region1and the memory transistor region2is formed above the semiconductor substrate11by, for example, photolithography. The resist pattern83is an example of a first resist pattern. An anti-reflection film may be formed under or on the resist pattern83. The element isolation insulating films12in the select transistor region1and the memory transistor region2are formed so as to extend parallel to a bit line direction. Thus, the resist pattern83has openings which extend parallel to the bit line direction. The resist pattern83covers the select transistor region1and the memory transistor region2except the element isolation insulating films12, the first logic region3, and the second logic region4.

The steps illustrated inFIGS. 40A to 40Ewill be described. Anisotropic dry etching is performed using the resist pattern83as a mask under an etching condition with a low selection ratio, thereby etching the charge storage film81. With this etching, the charge storage films81on the element isolation insulating films12in the memory transistor region2are removed. The anisotropic dry etching under the etching condition with the low selection ratio in each step illustrated inFIGS. 40A to 40Eis an example of first etching. If a surface oxide film is formed on each charge storage film81, the surface oxide film and the charge storage film81are removed.

The element isolation insulating films12in the select transistor region1and the memory transistor region2are formed so as to extend parallel to the bit line direction. Thus, the removal of the charge storage films81on the element isolation insulating films12in the memory transistor region2separates the charge storage film81in the memory transistor region2into a plurality of parts in a word line direction. Upper portions of the element isolation insulating films12in the select transistor region1and the memory transistor region2are partially removed. The etching condition with the low selection ratio and the type of an etching gas are the same as those in the first embodiment.

The openings of the resist pattern83are located above the element isolation insulating films12. For this reason, although the element isolation insulating films12are shaved after the removal of the charge storage film81, the semiconductor substrate11is not shaved. Thus, damage to the semiconductor substrate11is inhibited at the time of the removal of the charge storage films81on the element isolation insulating films12in the memory transistor region2.

Under the etching condition with the low selection ratio, the etching gas does not include O2or the concentration of O2to be included in the etching gas is set to be low. This inhibits the resist pattern83from retreating due to the etching. In the case of, for example, a gaseous mixture of CF4, Ar, and O2, if the concentration of O2is not more than that of CF4, the resist pattern83is inhibited from retreating due to the etching. The resist pattern83is then removed by, for example, chemical solution treatment using a sulfuric acid-hydrogen peroxide mixture (SPM) and an ammonia-hydrogen peroxide mixture (APM).

The steps illustrated inFIGS. 41A to 41Ewill be described. Annealing is performed, for example, under the condition in an atmosphere of nitrogen (N2) at about 750° C. for about 90 seconds. Alternatively, the annealing may be performed under the condition in an atmosphere of nitrogen at about 800° C. for about 30 seconds. A thermal oxidation method, a radical oxidation method, or a plasma oxidation method may be performed instead of the annealing. Heat treatment through the annealing, the thermal oxidation method, the radical oxidation method, or the plasma oxidation method decreases the etching rate of a plasma silicon nitride film with respect to hydrofluoric acid.

The steps illustrated inFIGS. 42A to 42Ewill be described. The tunnel oxide films16in the select transistor region1, the first logic region3, and the second logic region4are removed by performing wet etching using hydrofluoric acid. If a surface oxide film is formed on each charge storage film81, the tunnel oxide films16and the surface oxide films in the select transistor region1, the first logic region3, and the second logic region4are removed. The heat treatment has been performed in each step illustrated inFIGS. 41A to 41E. Since the charge storage film81has a decreased etching rate with respect to hydrofluoric acid, the charge storage films81in the memory transistor region2are not removed. Additionally, since the charge storage film81is formed on each tunnel oxide film16in the memory transistor region2, the tunnel oxide films16in the memory transistor region2are not removed.

The steps illustrated inFIGS. 43A to 43Ewill be described. An oxide film is formed by a radical oxidation method or a plasma oxidation method with the semiconductor substrate11set to a high temperature. The oxide film thus formed at a high temperature is also called an HTO (High Temperature Oxide). As a film formation gas, TEOS (Tetraethyl Orthosilicate) gas may be used. The oxide film may be formed by a CVD method, instead of the radical oxidation method or the plasma oxidation method. This oxide film formation causes gate oxide films (gate insulating films)84to be formed on the surface of the semiconductor substrate11in the select transistor region1. The oxide film formation also causes top oxide films (upper insulating films)85to be formed on the charge storage films81in the memory transistor region2and oxide films to be formed at sidewalls of each charge storage film81in the memory transistor region2. The top oxide film85is an example of a third film. The oxide film formation further causes the oxide films84to be formed on the surface of the semiconductor substrate11in the first logic region3and on the surface of the semiconductor substrate11in the second logic region4. If such oxide films are formed using the CVD method, the oxide films84are also formed on the element isolation insulating films12in the select transistor region1, the memory transistor region2, the first logic region3, and the second logic region4. The oxide film84is an example of a first oxide film.

The steps illustrated inFIGS. 44A to 44Ewill be described. A resist pattern86which covers the memory transistor region2and is open in the select transistor region1, the first logic region3, and the second logic region4is formed above the semiconductor substrate11by, for example, photolithography. An anti-reflection film may be formed under or on the resist pattern86. The oxide films84in the select transistor region1, the first logic region3, and the second logic region4are removed by performing wet etching using hydrofluoric acid, using the resist pattern86as a mask. The resist pattern86is then removed by, for example, chemical solution treatment using a sulfuric acid-hydrogen peroxide mixture (SPM) and an ammonia-hydrogen peroxide mixture (APM).

The steps illustrated inFIGS. 45A to 45Ewill be described. An oxide film is formed by, for example, a radical oxidation method using H2gas and O2gas at a temperature of about not less than 400° C. and not more than 1100° C. The thickness of the oxide film is, for example, about not less than 1 nm and not more than 15 nm.

This oxide film formation causes gate oxide films (gate insulating films)21to be formed on the surface of the semiconductor substrate11in the select transistor region1. The gate oxide film21is, for example, a silicon oxide film. The oxide film formation also causes gate oxide films (gate insulating films)23to be formed on the surface of the semiconductor substrate11in the first logic region3and gate oxide films (gate insulating films)24to be formed on the surface of the semiconductor substrate11in the second logic region4. The gate oxide films23and24are, for example, silicon oxide films. The oxide films may be formed by a plasma oxidation method instead of the radical oxidation method. After the steps illustrated inFIGS. 45A to 45E, the same steps as those illustrated inFIGS. 11A to 18Ein the first embodiment are performed. Since the steps illustrated inFIGS. 11A to 18Ein the first embodiment have already been described, a description thereof will be omitted. Additionally, since the structure of a select transistor51and the structure of a memory transistor52in the fourth embodiment are the same as those in the first embodiment, a description thereof will be omitted.

According to the fourth embodiment, the charge storage film81is separated into a plurality of parts in the word line direction. That is, the charge storage films81of the adjacent memory transistors52are separate, and the charge storage films81of the adjacent memory transistors52are not connected to each other. Additionally, the sidewalls of the charge storage film81of each memory transistor52are oxidized, and the top oxide film85is formed so as to cover the charge storage film81. With this configuration, charges are inhibited from being transferred between the charge storage films81of the adjacent memory transistors52. Thus, charges stored (retained) in the charge storage film81of the memory transistor52are inhibited from changing, which allows inhibition of decrease in data retention. For example, even if the interval between the adjacent memory transistors52is short or if the charge storage film81with high charge mobility is used, charges stored in the charge storage film81are inhibited from changing, which allows inhibition of decrease in data retention.

According to the fourth embodiment, the thickness of the gate oxide film21of the select transistor51and the thickness of the top oxide film85of the memory transistor52can be made independent of each other. That is, according to the fourth embodiment, the thickness of the gate oxide film21of the select transistor51and the thickness of the top oxide film85of the memory transistor52can be controlled to different values.

The fourth embodiment may be modified in the manner below. A combination of the first to fourth modifications below may be applied to the semiconductor device manufacturing method and the semiconductor device according to the fourth embodiment.

First Modification of Fourth Embodiment

The steps illustrated inFIGS. 37A to 38Eand the steps illustrated inFIGS. 39A to 40Emay be interchanged. That is, the steps illustrated inFIGS. 39A to 40Emay be performed after the steps illustrated inFIGS. 36A to 36Eare performed, and the steps illustrated inFIGS. 37A to 38Emay then be performed.

Second Modification of Fourth Embodiment

The steps illustrated inFIGS. 39A to 40Eand the steps illustrated inFIGS. 41A to 41Emay be interchanged. That is, the steps illustrated inFIGS. 41A to 41Emay be performed after the steps illustrated inFIGS. 38A to 38Eare performed, and the steps illustrated inFIGS. 39A to 40Emay then be performed.

Third Modification of Fourth Embodiment

In the steps illustrated inFIGS. 38A to 38E, the charge storage film81may be etched by performing wet etching using hydrofluoric acid instead of anisotropic dry etching under the etching condition with the high selection ratio. That is, in the steps illustrated inFIGS. 38A to 38E, the charge storage films81in the select transistor region1, the first logic region3, and the second logic region4may be removed by performing wet etching using hydrofluoric acid, using the resist pattern82as a mask. Since the etching rate of a plasma silicon nitride film is high in the wet etching using hydrofluoric acid, the charge storage film81can be easily removed by the wet etching using hydrofluoric acid.

Fourth Modification of Fourth Embodiment

In the steps illustrated inFIGS. 36A to 36E, the charge storage film81may be formed on the element isolation insulating films12and on the tunnel oxide films16by a CVD method. In this case, the charge storage film81is a silicon nitride film. If the charge storage film81is a silicon nitride film, even when the heat treatment is performed by the annealing, the thermal oxidation method, the radical oxidation method, or the plasma oxidation method in the steps illustrated inFIGS. 41A to 41E, the etching rate of the charge storage film81with respect to hydrofluoric acid changes little. Note that since the etching rate of a silicon nitride film with respect to hydrofluoric acid is low, the charge storage films81in the memory transistor region2are not removed at the time of the wet etching using hydrofluoric acid in the steps illustrated inFIGS. 42A to 42E.