Method of making an MIM capacitor and MIM capacitor structure formed thereby

A method of forming an MIM capacitor having interdigitated capacitor plates. Metal and dielectric layers are alternately deposited in an opening in a layer of insulator material. After each deposition of the metal layer, the metal layer is removed at an angle from the side to form the capacitor plate. The side from which the metal layer is removed is alternated with every metal layer that is deposited. When all the capacitor plates have been formed, the remaining opening in the layer of insulator material is filled with dielectric material then planarized, followed by the formation of contacts with the capacitor plates. There is also an MIM capacitor structure having interdigitated capacitor plates.

BACKGROUND OF THE INVENTION

The present invention relates to methods of fabricating a metal-insulator-metal (MIM) capacitor, and more particularly, to methods of forming a MIM capacitor having interdigitated capacitor plates.

The fabrication of semiconductor devices would benefit from increasing the capacity density of MIM capacitors because a greater capacity density yields a higher capacitance per unit of chip area. This higher capacitance per unit of chip area would allow MIM capacitors to have a smaller area, which permits greater compacting of semiconductor chips through space savings.

MIM capacitors are capacitors typically built into the back end of the line (BEOL) of a chip, which tend to have very good performance properties compared to front end of the line (FEOL) capacitors. Also, MIM capacitors do not consume space on the silicon, and typically do not consume space in wiring levels. This makes MIM capacitors an attractive option for integrated circuit design. However, they do cost extra processing and extra mask levels.

Conventional MIM capacitors require 1 lithographic level per capacitor plate. Since a capacitor requires a minimum of 2 plates, MIM capacitors will thus require at least 2 plates. Integration schemes to use 3 or more interdigitated capacitor plates can become very complicated and costly.

MIM capacitors have been disclosed generally in Tu et al. U.S. Pat. No. 7,115,935, Tu Patent Application Publication US 2005/0124132 and Chou et al. U.S. Patent Application Publication US 2006/0148192, the disclosures of which are incorporated by reference herein.

Coolbaugh et al. U.S. Patent Application Publication US 2003/0197215, the disclosure of which is incorporated by reference herein, discloses a stacked capacitor arrangement in which the capacitor layers are staggered so that each capacitor layer may be connected to a wiring by a via.

BRIEF SUMMARY OF THE INVENTION

The advantages of the invention have been achieved by providing, according to a first aspect of the invention, a method of making an MIM capacitor, the method comprising the steps of:

forming an opening in an insulator layer on a substrate;

depositing a first metal layer on the insulator layer and in the opening;

removing the first metal layer from the insulator layer and a first wall of the opening;

depositing a dielectric over the insulator and into the opening so as to cover the first metal layer;

depositing a second metal layer;

removing the second metal layer from the dielectric layer and a second wall of the opening, wherein the second wall is different from the first wall;

repeating steps (d), (e) and (f) a predetermined number of times until the desired number of metal layers is formed wherein the removing of the metal layer alternates between the first and second walls;

filling the opening with a dielectric material; and

forming electrical contacts with the metal layers.

According to a second aspect of the invention, there is provided a semiconductor article comprising:

a semiconductor substrate;

an insulator layer on the semiconductor substrate, the insulator having an opening;

an MIM capacitor in the opening comprising a plurality of interdigitated L-shaped capacitor plates separated by a dielectric material.

According to a third aspect of the invention, there is provided an MIM capacitor comprising a plurality of interdigitated L-shaped capacitor plates separated by a dielectric material.

DETAILED DESCRIPTION OF THE INVENTION

Referring to the Figures in more detail, and particularly referring toFIG. 1, there is shown a semiconductor substrate10, a layer of insulator material12and an opening14formed in the insulator material12. The layer of insulator material12can be either shallow trench isolation (STI) dielectric or back end of the line (BEOL) dielectric. If the layer of insulator material12is STI dielectric, the semiconductor substrate10will be semiconductor material. Alternatively, if the layer of insulator material12is BEOL dielectric, the semiconductor substrate10will be semiconductor material plus any so-called front end of the line processing that has occurred in or on the semiconductor material and may also include one or more layers of BEOL wiring.

In the next step of the process as shown inFIG. 2, a metal layer18is blanket deposited over the layer of insulator material12and in the opening14. The metal layer18may be any metallic material that is suitable for capacitors such as copper, aluminum, titanium, tantalum, ruthenium, lead, platinum, tin, silver, gold, tantalum nitride, titanium nitride, tungsten silicide, tungsten nitride, ruthenium oxide, titanium silicide, cobalt silicide, nickel silicide or mixtures thereof. The metal layer18should have a thickness of around 100 nanometers (nm), although a lesser or greater thickness is also explicitly contemplated herein. The metal layer18can be deposited by a conventional method, including but not limited to, atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition, sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, or any combination of those methods.

The metal layer18is then removed from at least one wall of the opening14as shown inFIG. 3. In one preferred embodiment of the present invention, the metal layer18is etched, indicated by arrows20inFIG. 2, at an angle alpha (α)22to selectively remove portions of the metal layer18. One preferred method of etching is sputtering. Sputtering is typically a low-pressure process (a few Torr). For the present invention, the angle of incidence of the sputtering ion is very important. Typical sputtering processes use normal incidence of sputtering ion to target, but this is not required or desired for the present invention. One could use an ion implanter to sputter with the right combination of feedgas and energy, which would allow angles more than 45 degrees from normal. Shown inFIG. 3is the metal layer18after it has been etched to remove portions of the metal layer18. It is noted that the remaining metal layer18will form an L-shaped capacitor plate when the MIM capacitor is completed. The L-shaped capacitor plate, now also indicated by30, is comprised of a horizontal portion32on the bottom of the opening14and a vertical portion34along the wall of the opening14. In a preferred embodiment, a segment of horizontal portion32is removed, indicated by arrow28, as a result of the etching process20.

Referring now toFIG. 4, a thin dielectric layer24is blanket deposited over the layer of insulator material12and L-shaped capacitor plate30. The dielectric layer24has a thickness of around 20 nm. The dielectric layer24may be silicon oxide, silicon nitride, silicon oxynitride, and/or any high dielectric constant (i.e., high K) material. Examples of high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, and any combination of these materials. The dielectric layer24can be deposited by a conventional method such as ALD and/or CVD. Thereafter, another metal layer26is deposited over the dielectric layer24. Metal layer26is of the same approximate thickness and material as metal layer18. The metal layer26is then removed, preferably by etching, indicated by arrows36, at an angle (β)38to selectively remove portions of the metal layer26. One preferred method of etching is sputtering. The etching36of metal layer26is from the opposite direction that metal layer18was etched. That is, comparingFIGS. 2 and 4, it can be seen that metal layer18was etched20at an angle α22from the left while metal layer26is etched36at an angle β38from the right. Angle α22will usually be the same as angle β38. It is desirable to alternate the directions of etching so as to form the capacitor plates necessary to the formation of the MIM capacitor according to the present invention.

The etching angle for angle α22and angle β38depends on the geometry of the trench, particularly the aspect ratio of the trench. The aspect ratio is defined as the ratio between the depth and width of the trench. As an example, an etching angle of about 45 degrees will work for a trench with an aspect ratio of 1, meaning the trench has equal depth and width. For most applications, the preferred etching angle will be in the range of 30-60 degrees, although it should be understood that the etching angle can range as high as 80 degrees or as low as 10 degrees for some applications.

Shown inFIG. 5is the metal layer26after it has been etched to remove portions of the metal layer26. It is noted that the remaining metal layer26will form an L-shaped capacitor plate when the MIM capacitor is completed. The L-shaped capacitor plate, now also indicated by40, is comprised of a horizontal portion42approximately parallel to the bottom of the opening14and a vertical portion44approximately parallel to the wall of the opening14. In a preferred embodiment, a segment of horizontal portion42is removed, indicated by arrow46, as a result of the etching process36.

An optional step then may be performed to remove any exposed dielectric that may have been damaged by the etching of the metal layer26. The exposed dielectric, indicated by arrows48inFIG. 5, may be removed by a wet etch process but a dry process such as reactive ion etching could also be utilized. Referring now toFIG. 5A, the exposed and possibly damaged dielectric has been removed. Note that there is no dielectric on the layer of insulator material12or on the exposed surfaces of the capacitor plates30,40.

In the following sequence of steps, additional metal and dielectric layers will be deposited and selectively removed as has been described already to build up the various layers of the MIM capacitor according to the present invention. In the remainingFIGS. 6 through 9, the exposed dielectric has not been removed although removal of the subsequent layers of exposed dielectric could certainly be removed as taught with reference toFIG. 5A.

The process continues inFIGS. 6 through 9to form additional capacitor plates in opening14. Referring toFIG. 6(and continuing fromFIG. 5), dielectric layer50is deposited over dielectric layer24and capacitor plate40. Another metal layer52is deposited over dielectric layer50and then etched from the left at an angle α (etching not shown for clarity) to result in capacitor plate54. Dielectric layer56is then deposited. The next metal layer58is deposited over dielectric layer56and then etched from the right at an angle β (etching not shown for clarity) to result in capacitor plate60.

As noted previously, the direction of dry etching alternates with each capacitor plate so that capacitor plates54and60are dry etched from different (usually opposite) directions.

Shown inFIG. 6is a partial MIM capacitor structure in which there are four interdigitated plates. Additional capacitor plates can be formed in a like manner if desired.

Referring now toFIG. 7, additional dielectric material62, such as an oxide or nitride for example, has been added into opening14and then planarized by a conventional process such as chemical-mechanical polishing.

Referring now toFIG. 8, the process will be described for forming contacts with the capacitor plates30,40,54,60. A suitable mask material66is deposited and then patterned (for example, by reactive ion etching) to form openings68. The mask material could be a hard mask such as a nitride. The openings could be formed by a layer of photoresist on top of the hard mask, then exposed and developed to form openings which are then driven into the hard mask. Alternatively, the mask material66could be a soft mask such as a photoresist which is exposed and developed to form the openings68. If the layer of insulator material12is the STI dielectric, the forming of the openings68can be integrated with the contact array (CA) process in standard CMOS processing so that no extra mask and process are needed to form the contacts. If the layer of insulator material12is formed in the BEOL dielectric, one extra mask will be needed to form the openings68.

Still referring toFIG. 8, once the openings68have been formed, the dielectric layers24,50are recessed by a conventional process as indicated by arrows70to expose the ends of the capacitor plates30,40,54,60.

One preferred embodiment of the final capacitor structure according to the present invention is shown inFIG. 9. In one preferred processing sequence, the mask material66(shown inFIG. 8) is removed and then the contact material72has been deposited. One preferred method of depositing the contact material72is by blanket depositing the contact material72and then planarizing by a process such as chemical-mechanical polishing.

Another preferred embodiment of the final capacitor structure according to the present invention is shown inFIG. 9A. The capacitor structure shown inFIG. 9Ais essentially identical to the capacitor structure shown inFIG. 9except that in the preferred embodiment ofFIG. 9A, the exposed and possibly damaged dielectric material has been removed, as taught with respect toFIG. 5A, in each of the subsequent processing steps.