METHOD OF MANUFACTURING MULTILAYER ELECTRONIC COMPONENT

A method of manufacturing a multilayer electronic component includes cutting a stack, in which internal electrode patterns and ceramic green sheets are alternately stacked in a stacking direction, to obtain unit chips and attaching a portion of a ceramic green sheet for a side margin portion to the unit chips in a direction, different from the stacking direction. The attaching includes attaching the portion of the ceramic green sheet to the unit chips by compression between a first elastic body on which the ceramic green sheet is disposed and the unit chips. The first elastic body includes a first elastic layer having and a second elastic layer having an elastic modulus different from the first elastic layer, and disposed between the unit chips and the first elastic layer. An elastic modulus of the first elastic body is greater than 50 MPa and less than or equal to 1000 MPa.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit under 35 USC 119(a) of Korean Patent Application Nos. 10-2022-0124826 filed on Sep. 30, 2022 and 10-2022-0173423 filed on Dec. 13, 2022, in the Korean Intellectual Property Office, the entire disclosures of which are incorporated herein by reference for all purposes.

TECHNICAL FIELD

The present disclosure relates to a method of manufacturing a multilayer electronic component.

BACKGROUND

A multilayer ceramic capacitor (MLCC), a multilayer electronic component, is a chip-type capacitor mounted on the printed circuit boards of various types of electronic products such as imaging devices including liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, cell phones, and the like, to allow electricity to be charged therein and discharged therefrom.

In the related art, as a method of increasing the capacitance, while miniaturizing multilayer ceramic capacitors, a process of exposing internal electrodes in a width direction of a body to maximize the area of the internal electrodes in the width direction through a marginless design and separately attaching side margin portions to the exposed surface of the internal electrodes in the width direction of a unit chip in an operation before sintering, after a unit chip is manufactured, is applied.

SUMMARY

Exemplary embodiments provide a method of manufacturing a multilayer electronic component capable of efficiently forming a side margin portion in the multilayer electronic component. For example, the occurrence of defects in the process of attaching the side margin portion to the multilayer electronic component may be effectively prevented.

According to an exemplary embodiment, a method of manufacturing a multilayer electronic component includes: cutting a stack, in which a plurality of internal electrode patterns and a plurality of ceramic green sheets are alternately stacked in a stacking direction, in the stacking direction to obtain a plurality of unit chips; and attaching a portion of a ceramic green sheet for a side margin portion to the plurality of unit chips in a direction, different from the stacking direction. The attaching includes attaching the portion of the ceramic green sheet for a side margin portion to the plurality of unit chips by compression between a first elastic body on which the ceramic green sheet for a side margin portion is disposed and the plurality of unit chips. The first elastic body includes a first elastic layer having a first elastic modulus and a second elastic layer having a second elastic modulus, different from the first elastic modulus, and disposed between the plurality of unit chips and the first elastic layer. An elastic modulus of the first elastic body is greater than 50 MPa and less than or equal to 1000 MPa.

According to another exemplary embodiment, a method of manufacturing a multilayer electronic component includes: cutting a stack, in which a plurality of internal electrode patterns and a plurality of ceramic green sheets are alternately stacked in a stacking direction, in the stacking direction to obtain a plurality of unit chips; and attaching a portion of a ceramic green sheet for a side margin portion to the plurality of unit chips in a direction, different from the stacking direction. The attaching includes attaching the portion of the ceramic green sheet for a side margin portion to the plurality of unit chips by compression between a first elastic body on which the ceramic green sheet for a side margin portion is disposed and the plurality of unit chips. The first elastic body includes a first elastic layer having a first elastic modulus and a second elastic layer having a second elastic modulus, different from the first elastic modulus, and disposed between the plurality of unit chips and the first elastic layer. The attaching further includes rotating the plurality of unit chips disposed on a second elastic body before the ceramic green sheet for a side margin portion is disposed on the first elastic body. The second elastic body includes a third elastic layer having a third elastic modulus and a fourth elastic layer having a fourth elastic modulus, different from the third elastic modulus, and disposed between the plurality of unit chips and the third elastic layer.

According to another exemplary embodiment, a method of manufacturing a multilayer electronic component includes: cutting a stack, in which a plurality of internal electrode patterns and a plurality of ceramic green sheets are alternately stacked in a stacking direction, in the stacking direction to obtain a plurality of unit chips; and attaching a portion of a ceramic green sheet for a side margin portion to the plurality of unit chips in a direction, different from the stacking direction. The attaching includes attaching the portion of the ceramic green sheet for a side margin portion to the plurality of unit chips by compression between a first elastic body on which the ceramic green sheet for a side margin portion is disposed and the plurality of unit chips. The first elastic body includes a first elastic layer having a first elastic modulus and a second elastic layer having a second elastic modulus, different from the first elastic modulus, and disposed between the plurality of unit chips and the first elastic layer. The attaching includes attaching the portion of the ceramic green sheet for a side margin portion to the plurality of unit chips by compression between the first elastic body and a second elastic body, after the plurality of unit chips are disposed between the first elastic body and the second elastic body. The second elastic body includes a third elastic layer having a third elastic modulus and a fourth elastic layer having a fourth elastic modulus, different from the third elastic modulus, and disposed between the plurality of unit chips and the third elastic layer.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments of the present inventive concept will be described in detail with reference to the accompanying drawings. The inventive concept may, however, be exemplified in many different forms and should not be construed as being limited to the specific exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like elements.

To clarify the present disclosure, portions irrespective of description are omitted and like numbers refer to like elements throughout the specification, and in the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Also, in the drawings, like reference numerals refer to like elements although they are illustrated in different drawings. Throughout the specification, unless explicitly described to the contrary, the word “comprise” and variations, such as “comprises” or “comprising,” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

In the drawings, a first direction may be defined as a direction in which a plurality of ceramic green sheets are stacked or a thickness (T) direction, a second direction may be defined as a length (L) direction, and a third direction may be defined as a width (W) direction. The second direction and the third direction may be, perpendicular to the first direction.

Referring to4to8, a method of manufacturing a multilayer electronic component according to an exemplary embodiment in the present disclosure may include cutting a stack200in which a plurality of internal electrode patterns221and222and a plurality of ceramic green sheets201and202are alternately stacked in a stacking direction (e.g., the first direction) to obtain a plurality of unit chips210. A bar300may include a structure in which the stack200is disposed on a support film310.

Referring toFIG.4, the support film310may serve to support the stack200in which conductive patterns221′ and222′ and the plurality of ceramic green sheets201and202are stacked. For example, the support film310may include adhesive materials, such as latex, starch, cellulose, protein, isoprene rubber (IR), nitrile butadiene rubber (NBR), styrene butadiene rubber (SBR), and mixtures thereof. The support film310may be parallel to the ground, but is not limited thereto.

The plurality of ceramic green sheets201and202may be formed of a ceramic paste including ceramic powder, an organic solvent, a dispersing agent, and a binder. The ceramic powder is a raw material for forming a dielectric layer111of the multilayer electronic component100, and a barium titanate-based material, a lead composite perovskite-based material, or a strontium titanate-based material may be used. The barium titanate-based material may include BaTiO3-based ceramic powder, and examples of the ceramic powder may include BaTiO3, and (Ba1-xCax) TiO3(0<x<1), Ba (Ti1-yCay) O3(0<y<1), (Ba1-xCax) (Ti1-yZry) O3(0<x<1, 0<y<1), or Ba (Ti1-yZry) O3(0<y<1), in which calcium (Ca), zirconium (Zr), or the like is partially dissolved. The plurality of ceramic green sheets201and202may be sintered to become the dielectric layer111constituting a body110.

Meanwhile, in an exemplary embodiment, the stack200may further include a ceramic green sheet203for a cover portion forming cover portions112and113. The ceramic green sheet203for a cover portion may be formed of the same material and component as those of the ceramic green sheets201and202, but is not limited thereto, and the upper and lower cover portions112and113of the body110may be formed through a sintering process. For example, the ceramic green sheets203for a cover portion may be formed on one surface and the other surface of the stack in the first direction, and may be formed as a single layer or a plurality of layers.

The internal electrode patterns221and222may be formed on the ceramic green sheets201and202by using an internal electrode paste including a conductive metal. The conductive metal included in the internal electrode patterns221and222is not particularly limited, and materials having excellent electrical conductivity may be used. For example, the conductive metal may include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof. A method of forming the internal electrode patterns221and222on the ceramic green sheets201and202is not particularly limited. For example, a conductive paste for an internal electrode including the conductive metal may be formed on the ceramic green sheets201and202by screen-printing or gravure printing.

The internal electrode patterns221and222may have a stripe shape. Specifically, the internal electrode patterns221and222may be formed to contact both ends of the ceramic green sheets201and202in the third direction at regular intervals in the second direction.

The internal electrode patterns221and222may include a first internal electrode pattern221formed on the ceramic green sheet201and a second internal electrode pattern222formed on the other ceramic green sheet202. At this time, the ceramic green sheet on which the first internal electrode pattern221is formed may be referred to as a first ceramic green sheet201, and the ceramic green sheet on which the second internal electrode pattern222is formed may be referred to as a second ceramic green sheet202.

As shown inFIG.4, the plurality of ceramic green sheets201and202may be alternately stacked such that the first internal electrode patterns221and the second internal electrode patterns222are alternately stacked. Accordingly, when the unit chip210to be described below is formed, the first internal electrode pattern221may be exposed from the third surface3and the second internal electrode pattern222may be exposed from the fourth surface4. The first internal electrode pattern221may become the first internal electrode121after sintering, and the second internal electrode pattern222may become the second internal electrode122after sintering.

Referring toFIGS.5to7, when a direction in which the plurality of ceramic green sheets201and202are stacked with respect to the bar300is referred to as the first direction, the bar300may be cut once or more times in the second direction, perpendicular to the first direction, and may be cut once or more times in the third direction, perpendicular to the first and second directions, to obtain a plurality of unit chips210, and in this case, the internal electrode patterns221and222may be connected to both first and second side surfaces S1and S2of the unit chip210.

As shown inFIG.5, the stack200may be cut along cutting lines C1-C1and C2-C2orthogonal to each other. The cutting lines C1-Cl are cutting lines, parallel to the second direction, and are substantially equally spaced in the third direction, and the cutting lines C2-C2are cutting lines, parallel to the third direction, and are substantially equally spaced in the second direction. The unit chip210having a substantially constant size in the third direction may be formed by the cutting line C1-C1, and the unit chip210having a substantially constant size in the second direction may be formed by the cutting line C2-C2.

In particular, since the cutting line C2-C2cuts the center of the first and second internal electrode patterns221and222in the second direction and a space in which the first and second internal electrode patterns221and222are spaced apart from each other in the second direction, the first internal electrode pattern221of the unit chip210may be exposed from the third surface3and the second internal electrode pattern222of the unit chip210may be exposed from the fourth surface4.

A unit for cutting the stack200is not particularly limited. For example, the stack200may be cut using a blade cutting method, such as a doctor blade or a dicing blade, a guillotine cutting method, or a laser cutting method.

Referring toFIGS.6and7, when the bar300is cut, the stack200may be divided into a plurality of unit chips210. Even after being cut, the plurality of unit chips210may be adhered to the support film310due to adhesiveness of the support film310.

FIGS.6and7show a structure in which a plurality of unit chips210are separated from each other at regular intervals by cutting, but the plurality of unit chips210may be substantially in contact with each other due to viscosity of the plurality of ceramic green sheets201and202and the internal electrode patterns221and222in a state in which adhesive force therebetween weakens.

However, it is not excluded that the plurality of unit chips are spaced apart from each other, and a size of space between the plurality of unit chips may be smaller than a size of space in which adjacent unit chips may rotate without coming into contact with each other.

Referring toFIG.8, the internal electrode patterns221and222of the plurality of unit chips210according to an exemplary embodiment in the present disclosure are cut so that the first and second side surfaces S1and S2of the unit chip210facing each other are all connected. Accordingly, an area in which the internal electrode patterns221and222may be formed may be maximized, thereby improving capacitance per unit volume of the multilayer electronic component100. However, the first and second side surfaces S1and S2from which the internal electrode patterns221and222are exposed are vulnerable to external moisture penetration, and if external electrodes to be described below are formed to extend to the first and second side surfaces S1and S2, there may be a risk of short circuit.

In the attaching operation of an exemplary embodiment in the present disclosure, which will be described below, a first side margin portion may be formed by attaching a ceramic green sheet for a side margin portion to the first side surface S1and/or the second side surface S2and punching the same, thereby resolving the problem of moisture resistance reliability and short-circuiting.

Referring toFIGS.9to12, the method of manufacturing a multilayer electronic component according to an exemplary embodiment in the present disclosure may include an operation of attaching a plurality of first portions47aof ceramic green sheets47for a side margin portion to the plurality of unit chips210in a direction (e.g., the third direction ofFIG.8), different from the stacking direction (e.g., the first direction ofFIG.8) of the stack200.

The plurality of first portions47amay be portion of the ceramic green sheet47for a side margin portion. The attaching operation may include attaching the plurality of first portions47ato the plurality of unit chips210, while cutting the plurality of first portions47aand second portions47bof the ceramic green sheet47for a side margin portion, by compressing a first elastic body50din which the ceramic green sheet47for a side margin portion is disposed and the plurality of unit chips210. It may include attaching the plurality of first portions47ato the plurality of unit chips210while cutting between the portions47aand the second portions47b. This may be expressed as punching.

As the elastic modulus of the first elastic bodies50aand50dis lower, a shape of the first elastic bodies50aand50dmay be more easily deformed by an external force and damage to the plurality of unit chips210in the process of attaching the plurality of first portions47ato the plurality of unit chips210may be effectively suppressed.

As the elastic modulus of the first elastic bodies50aand50dis higher, the shape of the first elastic bodies50aand50dmay be maintained more strongly, and cutting defects in the process of cutting between the plurality of first portions47aand the second portions47bmay be effectively suppressed.

Therefore, when the elastic modulus of the first elastic bodies50aand50dis optimized, damage to the plurality of unit chips210in the process of attaching the plurality of first portions47ato the plurality of unit chips210and cutting defects in the process of cutting between the plurality of first portions47aand the second portions47bmay be effectively suppressed.

The first elastic bodies50aand50dmay include a first elastic layer51having a first elastic modulus and a second elastic layer52having a second elastic modulus, different from the first elastic modulus, and disposed between at least one of a plurality of unit chips210and the first elastic layer51. Accordingly, the elastic modulus of the first elastic bodies50aand50dmay be more advantageously optimized.

The elastic modulus of the first elastic bodies50aand50dmay be measured by directly measuring the elastic modulus of the first elastic bodies50aand50d, and may be substantially the same as an interpolation elastic modulus. The interpolation elastic modulus may be calculated as a value obtained by obtaining the sum (a third value) of a product (a first value) of a volume of the first elastic layer51and the first elastic modulus and a product (a second value of a volume of the second elastic layer52and the second elastic modulus and then dividing the sum (the third value) by the sum (a fourth value) of the volume of the first elastic layer51and the volume of the second elastic layer52. That is, the sum of the first value and the second value is the third value, and the value obtained by dividing the third value by the fourth value may be the elastic modulus of the first elastic bodies50aand50d.

The elastic modulus of the first elastic bodies50aand50dmay be an overall elastic modulus of the first and second elastic layers51and52, and may be greater than 50 Mpa and less than 1000 MPa. Since the elastic modulus of the first elastic bodies50aand50dexceeds 50 MPa, cutting defects in the process of cutting between the plurality of first portions47aand second portions47bmay be effectively suppressed. Since the elastic modulus of the first elastic bodies50aand50dis 1000 MPa or less, damage to the plurality of unit chips210in the process of attaching the plurality of first portions47ato the plurality of unit chips210may be effectively suppressed.

The attaching operation may include attaching the plurality of first portions47ato the plurality of unit chips210by compression between the first elastic bodies50aand50dand the second elastic bodies50band50c, after the plurality of unit chips210are disposed between the first elastic bodies50aand50dand the second elastic bodies50band50c. The second elastic bodies50band50cmay include a third elastic layer53having a third elastic modulus and a fourth elastic modulus having a fourth elastic module, different from the third elastic modulus, and disposed between at least one of the plurality of unit chips210and the third elastic layer53.

Accordingly, since the elastic modulus of the second elastic bodies50band50cmay be more advantageously optimized, damage to the plurality of unit chips210in the process of attaching the plurality of first portions47ato the plurality of unit chips210and cutting defects in the process of cutting between the plurality of first portions47aand the second portions47bmay be suppressed more efficiently. The first elastic modulus and the third elastic modulus may be the same as or different from each other. The second elastic modulus and the fourth elastic modulus may be the same as or different from each other.

For example, each of the first, second, third, and fourth elastic moduli may exceed 50 MPa. Accordingly, cutting defects in the process of cutting between the plurality of first portions47aand the second portions47bmay be stably suppressed.

For example, the second elastic modulus may be higher than the first elastic modulus, a thickness of the first elastic layer51may be greater than a thickness of the second elastic layer52, the fourth elastic modulus may be greater than the third elastic modulus, and a thickness of the third elastic layer53may be greater than a thickness of the fourth elastic layer54. Accordingly, the first elastic layer51and/or the third elastic layer53may efficiently serve as a buffer for the plurality of unit chips210, and the second elastic layer52and/or the fourth elastic layer54may efficiently perform a role of cutting between the plurality of first portions47aand second portions47b.

For example, each of the first, second, third, and fourth elastic layers51,52,53, and54may have a thickness greater than 0 μm and less than or equal to 3 μm. For example, a hardness value of each of the first elastic bodies50aand50dand the second elastic bodies50band50cmay be 100 or less. For example, upper and lower surfaces of each of the first, second, third, and fourth elastic layers51,52,53, and54may be 500 mm*500 mm or less.

For example, since nonwoven fabric may have an elastic modulus lower than that of polyethylene terephthalate (PET), the nonwoven fabric may be included in each of the first and third elastic layers51and53. Each of the second and fourth elastic layers52and54may include PET. Here, the thickness of each of the first and third elastic layers51and53may be greater than 0 μm and less than or equal to 2 μm, and the thickness of each of the second and fourth elastic layers52and54may be greater than 0 μm and less than or equal to 1 μm.

For example, each of the first, second, third, and fourth elastic layers51,52,53, and54may replace or may further include at least one of silicone, polyurethane (PU), natural rubber, and polyolefine (PO), as well as non-woven fabric and PET. For example, silicone may be silicone rubber, and the elastic modulus of the silicone rubber may be 60 MPa or more and 80 MPa or less.

Roughness of a surface of the second elastic layer52facing the ceramic green sheet47for a side margin portion may be greater than roughness of the surfaces of the first and second elastic layers51and52facing each other. Roughness of the surface of the fourth elastic layer54facing at least one of the plurality of unit chips210may be greater than roughness of the surfaces of the third and fourth elastic layers53and54facing each other. Accordingly, in the process of attaching the plurality of first portions47ato the plurality of unit chips210, the ceramic green sheet47for a side margin portion or the plurality of unit chips210may be effectively prevented from slipping sideways. For example, in order to implement a roughness difference between upper and lower surfaces of the second and fourth elastic layers52and54, respectively, a known roughness treatment process may be applied to only one of the upper and lower surfaces of the second and fourth elastic layers52and54.

Referring toFIG.9, the attaching operation may further include rotating the plurality of unit chips210disposed on the second elastic body50bbefore the ceramic green sheet for a side margin portion is disposed on the first elastic body, and the second elastic body50bmay include the third elastic layer53having the third elastic modulus and the fourth elastic layer54disposed between at least one of the plurality of unit chips210and the third elastic layer53and having the fourth elastic modulus, different from the third elastic modulus.

For example, the plurality of unit chips210may be disposed on a support40together with an adhesive sheet38, and a plate41may be disposed above the plurality of unit chips210. Thereafter, the plate41may tumble in a horizontal direction. Since the adhesive sheet38may tumble together with the plate41by a connection portion34, the plurality of unit chips210on the adhesive sheet38may be rotated by 90 degrees all together. At this time, the support35supporting between the support40and the plate41may also tumble.

As the elastic modulus of the first elastic body50aand/or the second elastic body50bis lower, the first elastic body50aand/or the second elastic body50bmay serve to buffer against transfer of stress based on the tumbling of the plate41to the plurality of unit chips210, thereby preventing damage to the plurality of unit chips210. As the elastic modulus of the first elastic body50aand/or the second elastic body50bis higher, rotation defects of the plurality of unit chips210may be prevented.

Since the first elastic body50amay include first and second elastic layers51and52respectively having different first and second elastic moduli, the elastic modulus of the first elastic body50amay be efficiently optimized. Since the second elastic body50bmay include the third and fourth elastic layers53and54respectively having the third and fourth elastic moduli different from each other, the elastic modulus of the second elastic body50bmay be efficiently optimized. By optimizing the elastic moduli of the first elastic body50aand/or the second elastic body50b, rotation of the plurality of unit chips210may be stably performed and damage to the plurality of unit chips210may be efficiently prevented.

Meanwhile, the first elastic body50aofFIG.9and the first elastic body50dofFIGS.10to12may be the same as or different from each other. The second elastic body50bofFIG.9and the second elastic body50cofFIGS.10to12may be the same as or different from each other.

Referring toFIGS.10to12, the attaching operation may include a proximity operation shown inFIG.10, a punching operation shown inFIG.11, and a finishing operation shown inFIG.12, which are sequentially performed.

Referring toFIGS.10to12, the ceramic green sheet47for a side margin portion may be formed of ceramic powder including a barium titanate-based material, a lead composite perovskite-based material, or a strontium titanate-based material, an organic solvent, a dispersing agent, and a binder, like the ceramic green sheets201and202described above. However, the ceramic green sheet47for a side margin portion does not necessarily have the same composition as that of the ceramic green sheets201and202described above, and may have a different composition. Accordingly, the margin portions114and115after sintering may have a dielectric average particle size, density, or hardness different from that of the dielectric layer111.

For example, an ambient temperature in the attaching operation may be adjusted to 50° C. to 150° C. to prevent deformation and/or cracking of the ceramic green sheet47for a side margin portion. This may be expressed as thermocompression bonding. Alternatively, the ambient temperature in the attaching operation may be adjusted to 50° C. or less to prevent drying of the ceramic green sheet47for a side margin portion.

For example, an adhesive (e.g., acrylic, epoxy) may be disposed between the second elastic layer52and the plate41and may be disposed between the fourth elastic layer54and the support40.

For example, the sintering process may be performed on the plurality of unit chips210to which the plurality of first portions47aare attached. The sintering process may be performed at a temperature of 1000 to 1300° C. in a reducing atmosphere, but is not limited thereto. Thereafter, external electrodes131and132may be formed on the third and fourth surfaces3and4of the body110, respectively, to form the multilayer electronic component100.

Meanwhile, the unit chip210on which first and second side margin portions214and215are formed may be sintered to form the body110without an additional process, but is not limited thereto, and a conductive paste including a metal having excellent electrical conductivity may be disposed on each of the third and fourth surfaces3and4and simultaneously sintered together with the body110to form the external electrodes131and132to manufacture the multilayer electronic component100.

The vertical and horizontal axes of the stress-strain curve inFIG.13represent stress and strain, respectively. When stress starts to be applied to the first elastic body and/or the second elastic body, strain may increase linearly within a range of modulus of resilience. In this case, the slope of the curve may correspond to the elastic modulus.

The five curves inFIG.14represent 5 stress-strain curves obtained by measuring a PET sample five times, and the elastic modulus of PET having linear elastic behavior may be measured as an average value of the slopes of the stress-strain curves within the linear range in the five measurements.

The five curves inFIG.15represent the five stress-strain curves obtained by measuring nonwoven fabric sample five times, and the elastic modulus of the nonwoven fabric having a nonlinear elastic behavior may be measured as an average value of initial tangential slopes of the stress-strain curves of the five measurements.

The ten stress-strain curves ofFIGS.14and15were obtained by a TIRA tension measuring instrument, a shape of the sample was a plate shape, and an area of upper and lower surfaces of the plate was 5 mm*5 mm.

The elastic moduli inFIG.16were organized according to the measured values in Table 1 below. Here, 0.8T_70, 0.6T_50 (roughness), 0.4T_70, 0.4T_70 (roughness), and 0.2T_70 may respectively correspond to the first elastic body including the first and second elastic layers and may include a structure in which the material or volume ratio included in the first and second elastic layers is adjusted to be different from each other.

Hereinafter, the multilayer electronic component100that may be manufactured by a manufacturing method according to an exemplary embodiment in the present disclosure will be described with reference toFIGS.1to3. However, the multilayer electronic component100may not be limited to the first to third shapes, and the shape and number of internal electrodes and external electrodes may vary depending on a mounting position or use.

The multilayer electronic component100may include the body110including the dielectric layer111and the first and second internal electrodes121and122alternately disposed with the dielectric layer111interposed therebetween and the external electrodes131and132disposed on the body110.

In the body110, the dielectric layer111and the internal electrodes121and122are alternately stacked.

The body110is not particularly limited to a specific shape, but as shown, the body110may have a hexahedral shape or a shape similar thereto. Due to shrinkage of the ceramic powder included in the body110during sintering, the body110may not have a hexahedral shape with perfect straight lines but a substantially hexahedral shape.

The body110may include first and first surfaces1and2facing each other in the first direction, third and fourth surfaces connected to the first and second surfaces1and2and facing each other in the second direction, and the first and second side surfaces S1and S2connected to the surfaces3and4and facing each other in the third direction.

A plurality of dielectric layers111forming the body110are in a sintered state, and adjacent dielectric layers111may be integrated such that boundaries therebetween may not be readily apparent without using a scanning electron microscope (SEM).

According to an exemplary embodiment in the present disclosure, a material for forming the dielectric layer111is not limited as long as sufficient electrostatic capacity may be obtained. For example, a barium titanate-based material, a lead composite perovskite-based material, or a strontium titanate-based material may be used. The barium titanate-based material may include a BaTiO3-based ceramic powder, and the ceramic powder may include BaTiO3and (Ba1-xCax) TiO3, Ba (Ti1-yCay) O3, (Ba1-xCax) (Ti1-yZry) O3, or Ba (Ti1-yZry)O3obtained by partially dissolving calcium (Ca), zirconium (Zr), and the like in BaTiO3.

In addition, various ceramic additives, organic solvents, binders, dispersing agents, etc. may be added to powder, such as barium titanate (BaTiO3) as a raw material forming the dielectric layer111according to the purpose of the present disclosure.

The body110may include a capacitance forming portion Ac disposed inside the body110and including the first internal electrodes121and the second internal electrodes122alternately disposed with the dielectric layer111therebetween and cover portions112and113respectively formed on upper and lower surfaces of the capacitance forming portion Ac in the first direction.

In addition, the capacitance forming portion may be a portion that contributes to formation of capacitance of the capacitor, and may be formed by repeatedly stacking a plurality of first and second internal electrodes121and122with the dielectric layer111interposed therebetween.

The cover portions112and113may include the upper cover portion112disposed above the capacitance forming portion Ac in the first direction and the lower cover portion113disposed below the capacitance forming portion Ac in the first direction.

The upper cover portion112and the lower cover portion113may be formed by stacking a single dielectric layer or two or more dielectric layers on the upper and lower surfaces of the capacitance forming portion Ac in the thickness direction, respectively, and may basically serve to prevent damage to the internal electrodes due to physical or chemical stress.

The upper cover portion112and the lower cover portion113may not include internal electrodes and may include the same material as that of the dielectric layer111.

That is, the upper cover portion112and the lower cover portion113may include a ceramic material, for example, a barium titanate (BaTiO3)-based ceramic material.

In addition, margin portions114and115may be disposed on side surfaces of the capacitance forming portion Ac.

The margin portions114and115may include a margin portion114disposed on the first side surface S1of the body110and a margin portion115disposed on the second side surface S2of the body110. That is, the margin portions114and115may be disposed on both end surfaces of the body110in the third direction.

As shown inFIG.3, the margin portions114and115may refer to a region between both ends of the first and second internal electrodes121and122and a boundary surface of the body110in a cross-section of the body110taken in a width-thickness (W-T) direction.

The margin portions114and115may basically serve to prevent damage to the internal electrodes due to physical or chemical stress.

According to an exemplary embodiment in the present disclosure, in order to suppress a step difference due to the internal electrodes121and122, after stacking, the internal electrodes may be cut to be exposed to the first and second side surfaces S1and S2of the body, and then a single dielectric layer or two or more dielectric layers may be stacked on both side surfaces of the capacitance forming portion Ac in the third direction to form the margin portions114and115.

A width of the margin portions114and115may not be particularly limited. However, an average width of the margin portions114and115may be 15 μm or less in order to more easily achieve miniaturization and high capacitance of the multilayer electronic component. In addition, according to an exemplary embodiment in the present disclosure, after separating the unit chips from the support film in a direction in which the ceramic green sheets are stacked, an arrangement operation of moving the unit chips in a direction, perpendicular to the direction in which the unit chips are separated, and arranging the unit chips such that the second side surface of the unit chip is in contact with an adhesive tape is included, thereby manufacturing the multilayer electronic component having improved reliability, and thus, excellent reliability may be secured even when the average width of the margin portions114and115is 15 μm or less.

The average width of the margin portions114and115may refer to an average size of the margin portions114and115in the third direction, and may be a value obtained by averaging sizes of the margin portions114and115measured from five equally spaced points on the side surface of the capacitance forming portion Ac in the third direction.

The plurality of internal electrodes121and122may be alternately disposed with the dielectric layer111interposed therebetween.

The plurality of internal electrodes121and122may include first and second internal electrodes121and122. The first and second internal electrodes121and122may be alternately disposed to face each other with the dielectric layer111constituting the body110interposed therebetween, and may be connected to the third and fourth surfaces3and4of the body110, respectively.

Specifically, one end of the first internal electrode121may be connected to the third surface3, and one end of the second internal electrode122may be connected to the fourth surface4.

The first internal electrode121may be spaced apart from the fourth surface4and exposed through the third surface3, and the second internal electrode122may be spaced apart from the third surface3and exposed through the fourth surface4. The first external electrode131may be disposed on the third surface3of the body and connected to the first internal electrode121, and the second external electrode132may be disposed on the fourth surface4of the body and connected to the second internal electrode122.

That is, the first internal electrode121may not be connected to the second external electrode132and may be connected to the first external electrode131, and the second internal electrode122may not be connected to the first external electrode131and may be connected to the second external electrode132. Accordingly, the first internal electrode121may be formed to be spaced apart from the fourth surface4by a predetermined distance, and the second internal electrode122may be formed to be spaced apart from the third surface3by a predetermined distance.

In this case, the first and second internal electrodes121and122may be electrically separated from each other by the dielectric layer111disposed therebetween.

The body110may be formed by alternately stacking the ceramic green sheet201on which the first internal electrode pattern221is printed and the ceramic green sheet202on which the second internal electrode pattern222is printed, and then sintering the same.

Materials forming the internal electrodes121and122are not particularly limited, and materials having excellent electrical conductivity may be used. For example, the internal electrodes121and122may include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

In addition, the internal electrodes121and122may be formed by printing a conductive paste for an internal electrode including at least one of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof on a ceramic green sheet. A screen-printing method or a gravure-printing method may be used as a method of printing the conductive paste for an internal electrode, but the present disclosure is not limited thereto.

The external electrodes131and132may be disposed on the third and fourth surfaces3and4of the body110, respectively, and the first external electrode131may be electrically connected to the first internal electrode121and the second external electrode132may be electrically connected to the second internal electrode122.

In the present exemplary embodiment, a structure in which the multilayer electronic component100includes two external electrodes131and132is described, but the number and shape of the external electrodes131and132may change depending on the shape of the internal electrodes121and122or other purposes.

Meanwhile, the external electrodes131and132may be formed using any material having electrical conductivity, such as metal, and a specific material may be determined in consideration of electrical characteristics, structural stability, and the like, and the external electrodes131and132may further have a multilayer structure.

For example, the external electrodes131and132may include an electrode layer disposed on the surface of the body110to directly contact the internal electrodes121and122and a plating layer formed on the electrode layer.

As a specific example of the electrode layer, the electrode layer may be a sintered electrode including a conductive metal and glass or a resin-based electrode including a conductive metal and resin.

In addition, the electrode layer may have a form in which a sintered electrode and a resin-based electrode are sequentially formed on the body. Also, the electrode layer may be formed by transferring a sheet including a conductive metal onto the body or by transferring a sheet including a conductive metal onto a sintered electrode.

As the conductive metal included in the electrode layer, a material having excellent electrical conductivity may be used but is not particularly limited. For example, the conductive metal may be at least one of nickel (Ni), copper (Cu), and alloys thereof.

The plating layer serves to improve mounting characteristics. The type of the plating layer is not particularly limited, and may be a plating layer including at least one of Ni, Sn, Pd, and alloys thereof, and may be formed of a plurality of layers.

For a specific example of the plating layer, the plating layer may be a Ni plating layer or a Sn plating layer, may be a form in which a Ni plating layer and a Sn plating layer are sequentially formed on the electrode layer, and may be a form in which a Sn plating layer, a Ni plating layer, and a Sn plating layer are sequentially formed on the electrode layer. Further, the plating layer may include a plurality of Ni plating layers and/or a plurality of Sn plating layers.

As set forth above, according to an exemplary embodiment, the side margin portions may be efficiently formed in the multilayer electronic component. For example, the occurrence of defects in the process of attaching the side margin portion to the multilayer electronic component may be efficiently prevented.