Source follower, voltage follower, and semiconductor device

A source follower in which any one of the following three modes is selected by a plurality of switching elements: a first mode in which a first potential is supplied to a gate of a transistor and an input potential is supplied to a first electrode of a capacitor respectively and a second electrode of the capacitor and a source of the transistor are connected, a second mode in which an input potential is supplied to the first electrode and the gate of the transistor and the second electrode floats, and a third mode in which the first electrode and the gate of the transistor are connected and a potential thereof floats and a second potential is supplied to the second electrode, a drain of the transistor is supplied with a third potential, and a potential of the source of the transistor is supplied to a subsequent circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a source follower and a voltage follower, and more particularly to a semiconductor device having a source follower and a voltage follower formed by using a thin film transistor in a driver circuit.

2. Description of the Related Art

In an active matrix semiconductor display device, pixels having display elements are arranged in matrix in a pixel portion and each pixel is supplied with video signals for controlling the drive of the display elements through a plurality of signal lines provided in the pixel portion. These signal lines have load capacitance caused by display elements or other circuit elements in the pixel. Therefore, when the current is not supplied enough, the load capacitance is not charged rapidly and a video signal to be inputted to each pixel are largely delayed or do not rise nor fall sharply. In particular, a larger pixel portion in a display device tends to suffer from the aforementioned problem since load capacitance between the wirings are increased as wiring length is increased in accordance with the increased pixels.

In view of the aforementioned problem, such circuit as a source follower or a voltage follower for transforming an impedance are typically provided on the output side of a signal line driver circuit. The source follower in particular has a rather simple configuration that the drain of a transistor is fixed at a constant potential, the gate is used for input, and the source is connected to a constant current supply and used for output. By using these circuits, an area required for the signal line driver circuit does not have to be expanded much even when signal lines are increased in accordance with the increased resolution, therefore, they are used as a typical impedance transformer for a signal line driver circuit of a semiconductor display device. By providing an impedance transformer on the output side of the signal line driver circuit, current supply to the signal line can be increased and a delay or blunted rise and fall of a video signal can be avoided.

An active matrix semiconductor display device formed by using an inexpensive glass substrate can not easily be miniaturized since a periphery (frame area) of the pixel portion required for mounting occupies more area as the resolution becomes higher. Thus, a method for implementing an IC formed by using a single crystalline silicon wafer is considered to be nearing its mature phase, therefore, a technology for integrating a signal line driver circuit and a scan driver circuit on the same glass substrate as a pixel portion, that is referred to as System On Panel is now focused on.

A thin film transistor, however, has a large variation in characteristics as compared to a single crystalline MOS transistor. A variation in threshold voltage in particular is directly reflected to an output voltage of a source follower and a voltage follower.FIG. 9Ashows a circuit diagram of a typical source follower. In the source follower shown inFIG. 9A, an input potential Vin is supplied to the gate (G) of a transistor901and a potential Vdd (Vdd>Gnd (potential of the ground)) is supplied to the drain (D) from a power supply. The source (S) is connected to a constant current supply902and the potential of the source corresponds to an output potential Vout.

The output potential Vout of the source follower having the aforementioned configuration can be obtained by the following formula shown in [Formula 1]. Note that Vgs corresponds to a voltage (gate voltage) that deducted the potential of the source from the potential of the gate.
Vout=Vin−Vgs[Formula 1]

The potential of this gate voltage Vgs is dependent on the relation between the gate voltage Vgs and a drain current Id. In the case where the transistor901is operated in a saturation region, the drain current Id can be obtained by the following formula shown in [Formula 2]. Note that i is mobility, Cois the gate capacitance per unit area, W/L is the proportion of the channel width W to the channel length L of a channel formation region, and Vth is a threshold voltage.
Id=μCoW/L(Vgs−Vth)2/2   [Formula 2]

In Formula 2, μ, Co, W/L, and Vth are all fixed values determined by each transistor. The drain current Id of the transistor901is approximately determined by the constant current supply902. Therefore, when the threshold voltage Vth is constant, it is found from Formula 2 that a predetermined gate voltage Vgs can be obtained. In other words, the gate voltage Vgs varies when the threshold voltage varies, which ends in the variation in the output potential Vout.

FIG. 9Bshows measured values of the output potential Vout relatively to the input potential Vin of the source follower shown inFIG. 9A. As shown inFIG. 9B, the output potential Vout has a variation according to each source follower. This variation in the output of the source follower provided on the output side of the signal line driver circuit cause a variation in the potential of the video signal of each line, and visibly appear as a luminance variation in stripe shapes.

SUMMARY OF THE INVENTION

In view of the aforementioned problem, the invention provides a source follower or a voltage follower which can avoid the variation in output potential even when the threshold voltages of TFTs vary, and a semiconductor device which can avoid the visible luminance variation in striped shapes due to the variation in output potential of the source follower or the voltage follower.

According to the invention, variation in the output potential due to the variation in gate voltage is corrected by using a capacitor. Specifically, an input potential Vin is supplied to a first electrode of a capacitor in a first period (write period). The source of a transistor is connected to a second electrode of the capacitor. A potential of the drain is fixed and a precharge potential Vpre is supplied to the gate, thus a potential that deducted the gate voltage Vgs from the precharge potential Vpre is supplied to the second electrode. At this time, the capacitor stores a voltage of Vin−Vpre+Vgs.

In a second period (store period), the first electrode of the capacitor and the gate electrode of the transistor are connected and an input potential Vin is supplied to both of them. By floating a potential of the second electrode of the capacitor, the voltage accumulated in the first period is stored. Subsequently, a potential of the first electrode of the capacitor and the gate of the transistor connected to each other floats in a third period (output period). Further, by supplying an offset potential Vo to the second electrode of the capacitor, the potential of the first electrode of the capacitor and the gate of the transistor becomes Vo+Vin−Vpre+Vgs, following the law of conservation of electric charge. Accordingly, a potential of the source of the transistor becomes Vo+Vin−Vpre, which corresponds to the output potential Vout. Thus, the output potential Vout can be determined independently of the potential of Vgs.

According to the aforementioned configuration of the invention, variation in the output potential of the source follower due to the variation in threshold voltage of the transistors can be avoided.

The idea of the invention can be applied to not only a source follower but a voltage follower using an operational amplifier as well. In this case, an input potential Vin is supplied to a first electrode of a capacitor in a first period (write period). An output terminal of the operational amplifier is connected to a second electrode of the capacitor. By supplying a precharge potential Vpre to a non-inverted input terminal, a potential that deducted an offset voltage Vop of the operational amplifier from the precharge potential Vpre is supplied to the second electrode of the capacitor. At this time, a voltage stored in the capacitor is Vin−Vpre+Vop. The offset voltage Vop of the operational amplifier is dependent on the characteristics of the transistors configuring the operational amplifier.

In a second period (store period), the first electrode of the capacitor is connected to the non-inverted input terminal of the operational amplifier and an input potential Vin is supplied to both of them. By floating a potential of the second electrode of the capacitor, the voltage accumulated in the first period is stored. Subsequently, a potential of the first electrode of the capacitor and the non-inverted input terminal of the operational amplifier connected to each other floats in a third period (output period). Further, by supplying an offset potential Vo to the second electrode of the capacitor, the potential of the first electrode of the capacitor and the non-inverted input terminal of the operational amplifier becomes Vo+Vin−Vpre+Vop, following the law of conservation of electric charge. Accordingly, a potential of the output terminal of the operational amplifier becomes Vo+Vin−Vpre, which corresponds to the output potential Vout. Thus, the output potential Vout can be determined independently of the potential of Vop.

According to the aforementioned configuration of the invention, variation in the output potential of the voltage follower due to the variation in threshold voltage of the transistors configuring the operational amplifier can be avoided.

By providing the source follower or the voltage follower on the output side of a signal line driver circuit, a variation in potential of video signals to be inputted to each signal line can be avoided and a visible luminance variation that appears in striped shapes on a semiconductor display device can be avoided.

It should be noted that a semiconductor device of the invention includes a semiconductor display device including a liquid crystal display device, a light emitting device having a light emitting element represented by an organic light emitting element in each pixel, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), an FED (Field Emission Display) and the like, and other semiconductor display devices having a circuit element formed by using a semiconductor film in a driver circuit. A semiconductor device of the invention is not limited to the aforementioned semiconductor display devices and a semiconductor integrated circuit having the source follower or the voltage follower of the invention is included as well.

It is possible to use a transistor other than a thin film transistor in the invention. The transistor used in the invention may be a transistor formed by using a single crystalline silicon, a transistor formed by using SOI, or a thin film transistor formed by using a polycrystalline silicon or an amorphous silicon. It may be a transistor formed by using an organic semiconductor or a transistor formed by using a carbon nanotube. A transistor provided in a pixel of a light emitting device of the invention may comprise a single-gate structure, a double-gate structure, or a multi-gate structure having more than two gate electrodes.

According to the aforementioned configuration of the invention, a variation in output potential of the voltage follower due to the variation in threshold voltages of the transistors configuring an operational amplifier can be avoided. By providing the source follower or the voltage follower on the output side of a signal line driver circuit, a variation in potential of video signals to be inputted to each signal line can be avoided and a visible luminance variation that appears in striped shapes on a semiconductor display device can be avoided.

DETAILED DESCRIPTION THE INVENTION

FIG. 1Ais a circuit diagram which corresponds to one mode of the source follower of the invention. The source follower of the invention is configured with a transistor101, a constant current supply102, a correction unit103for correcting a potential supplied to the gate and the source of the transistor101.

A fixed potential Vdd is supplied to the drain of the transistor101and the source thereof is connected to the constant current supply102. The potential of the source of the transistor101corresponds to an output potential.

The correction unit103is configured with a capacitor109, a plurality of transistors104to108as switching elements for controlling a voltage to be supplied to the capacitor109. InFIG. 1A, specifically, the transistor104controls a supply of an input potential Vin to the first electrode of the capacitor109. The transistor107controls a supply of an offset potential Vo to the second electrode of the capacitor109. The transistor108controls a connection between the second electrode of the capacitor109and the source of the transistor101. The transistor105controls a supply of a precharge potential Vpre to the gate of the transistor101. The transistor106controls a connection between the gate of the transistor101and the first electrode of the capacitor109. The transistor105and the transistor106control a supply of the precharge potential Vpre to the first electrode of the capacitor109.

Hereinafter explained is an operation of the source follower shown inFIG. 1A. The operation of the source follower of the invention can be explained in three periods of a write period, a store period, and an output period. Potentials supplied to the gates of the transistors104to108are denoted as Vg1to Vg5, respectively. A timing chart of the potentials Vg1to Vg5are shown inFIG. 1B.

As seen in the timing chart inFIG. 1B, the transistors104,105, and108are turned ON and the transistors106and107are turned OFF in the write period. A simplified connection between the transistor101, the constant current supply102, and the capacitor109in the source follower inFIG. 1Ain the write period is shown inFIG. 2A. It should be noted that V1denotes a potential of the first electrode, V2denotes a potential of the second electrode of the capacitor109. Vss denotes a fixed potential supplied from the power supply, which is lower than the potentials of Vdd, Vpre, and Vin, or it may be the same potential as a ground.

As shown inFIG. 2A, an input potential Vin is supplied to the first electrode of the capacitor109in the write period. Therefore, the potential V1of the first electrode of the capacitor109becomes V1=Vin. Further, a potential for precharge (precharge potential) is supplied to the gate of the transistor101and the source thereof is connected to the second electrode of the capacitor109. Therefore, the source of the transistor101has a potential that deducted a gate voltage Vgs from the precharge potential Vpre, which makes the potential V2of the second electrode of the capacitor109as V2=Vpre−Vgs. Thus, a voltage Vc to be supplied to the capacitor109right before the termination of the write period is Vc=V1−V2=Vin−Vpre+Vgs.

At the beginning of the write period, the transistor104is preferably turned ON after turning ON the transistors105and108. By operating the transistors at the aforementioned timing, an input potential Vin can be supplied to the first electrode of the capacitor109after the potential of the second electrode of the capacitor109is determined.

In the store period after the write period, the transistors104and106are turned ON and the transistors105,107, and108are turned OFF as shown in the timing chart inFIG. 1B. A simplified connection between the transistor101, the constant current supply102, and the capacitor109in the source follower inFIG. 1Ain the store period is shown inFIG. 2B.

As shown inFIG. 2B, the first electrode of the capacitor109and the gate of the transistor101are connected in the store period. An input potential Vin is supplied to the first electrode of the capacitor109and the gate of the transistor101. Therefore, a potential V1of the first electrode is V1=Vin. The transistor108as a switching element is OFF, therefore, the potential of the second electrode of the capacitor109floats. Therefore, the potential V2of the second electrode remains as V2=Vpre−Vgs as was in the write period. Thus, a voltage Vc to be supplied to the capacitor109right before the termination of the write period is stored unchanged as Vc=V1−V2=Vin−Vpre+Vgs.

It should be noted that the transistor108is preferably turned OFF at a faster timing than the transistor105when transiting from the write period to the store period. By operating the transistors at the aforementioned timing, a voltage supplied to the capacitor109can be stored without fail.

In the output period after the store period, the transistors106and107are turned ON and the transistors104,105, and108are turned OFF as shown in the timing chart inFIG. 1B. A simplified connection between the transistor101, the constant current supply102, and the capacitor109of the source follower inFIG. 1Ain the output period is shown inFIG. 2C.

As shown inFIG. 2C, the first electrode of the capacitor109and the gate of the transistor101are connected in the output period. Unlike in the store period, an input potential Vin is not supplied to the first electrode of the capacitor109and the gate of the transistor101, that is to say, the potential thereof floats. An offset potential Vo is supplied to the second electrode of the capacitor109. Thus, the potential V2of the second electrode of the capacitor109is V2=Vo. The voltage Vc stored in the capacitor109is stored as it is, following the law of conservation of electric charge. Therefore, the potential V1of the first electrode of the capacitor109is V1=V2+Vc=Vo+Vin−Vpre+Vgs.

The gate of the transistor101is connected to the first electrode of the capacitor109and the source of the transistor101has a potential that deducted the gate voltage Vgs from the potential of the gate thereof. Therefore, the potential of the source of the transistor101is V1−Vgs=Vo+Vin−Vpre. This potential of the source of the transistor101corresponds to the output potential Vout of the source follower, which is obtained as Vout=Vo+Vin−Vpre.

Thus, the output potential Vout is determined by the offset potential Vo, the input potential Vin, and the precharge potential Vpre, regardless of the potential of the gate voltage Vgs of the transistor101. Therefore, a variation in the output potential Vout of the source follower due to a variation in threshold voltage of the transistors can be avoided. By providing the source follower on the output side of a signal line driver circuit, a variation in potential of video signals to be inputted to each signal line can be avoided and a visible luminance variation that appears in striped shapes on a semiconductor display device can be avoided.

The offset potential Vo, the input potential Vin, and the precharge potential Vpre are set so that the transistor101operates in a saturation region. It is also important to set the offset potential Vo, the input potential Vin, and the precharge potential Vpre so that the constancy of the constant current supply can be maintained.

Before providing a write period again after the output period, a charge stored in the capacitor109may be reset. By resetting, the charge is to be a constant value at all times regardless of the amount of the charge accumulated in the write period.

The timing chart inFIG. 1Bis based on the assumption that the transistors104to108shown inFIG. 1Aare all n-channel transistors. The transistors104to108may be either n-channel or p-channel transistors. The potential to be supplied to the gate of each transistor is not limited to that shown in the timing chart inFIG. 1B. The timing chart is preferably changed according to the polarity of each transistor so that the transistors operate as shown inFIGS. 2A to 2C.

Note that the constant current supply may use a known configuration. For example, a single transistor or a plurality of transistors connected in series may be used as the constant current supply. In this case, the transistor used as the constant current supply is operated in a saturation region in order to maintain the constancy.

FIG. 3Ais a circuit diagram which corresponds to one mode of the voltage follower of the invention. The voltage follower of the invention is configured with an operational amplifier301and a correction unit302for correcting a potential to be supplied to a non-inverted input terminal (+) and the output terminal of the operational amplifier301. The inverted input terminal (−) of the operational amplifier301is connected to its output terminal. The potential of the output terminal of the operational amplifier301corresponds to an output potential.

The correction unit302is configured with a capacitor303, a plurality of transistors304to308as switching elements for controlling a voltage to be supplied to the capacitor303, as in the case of the source follower. InFIG. 3A, specifically, the transistor304controls a supply of an input potential Vin to the first electrode of the capacitor303. The transistor307controls a supply of an offset potential Vo to the second electrode of the capacitor303. The transistor308controls a connection between the second electrode of the capacitor303and the output terminal of the operational amplifier301. The transistor305controls a supply of a precharge potential Vpre to the non-inverted input terminal of the operational amplifier301. The transistor306controls a connection between the non-inverted input terminal of the operational amplifier301and the first electrode of the capacitor303. The transistors305and306control a supply of the precharge potential Vpre to the first electrode of the capacitor303.

Hereinafter explained is an operation of the voltage follower shown inFIG. 3A. The operation of the voltage follower of the invention can be explained in three periods of a write period, a store period, and an output period as in the case of the source follower described in Embodiment Mode 1. The operations of the switching elements in each period are the same in the case of the source follower described in Embodiment Mode 1. That is to say, the transistors304,305, and308are turned ON and the transistors306and307are turned OFF in the write period. A simplified connection between the operational amplifier301and the capacitor303of the voltage follower inFIG. 3Ain the write period is shown inFIG. 3B. It should be noted that V1denotes a potential of the first electrode and V2denotes a potential of the second electrode of the capacitor303.

As shown inFIG. 3B, an input potential Vin is supplied to the first electrode of the capacitor303in the write period. Therefore, the potential V1of the first electrode is V1=Vin. A potential for precharge (precharge potential) is supplied to the non-inverted input terminal of the operational amplifier301and the output terminal thereof is connected to the second electrode of the capacitor303. Therefore, the output terminal of the operational amplifier301has a potential that deducted an offset voltage Vop of the operational amplifier301from the precharge potential Vpre, and the potential V2of the second electrode of the capacitor303becomes V2=Vpre−Vop. Thus, a voltage Vc to be supplied to the capacitor303right before the termination of the write period is Vc=V1−V2=Vin−Vpre+Vop.

At the beginning of the write period, the transistor304is preferably turned ON after turning ON the transistors305and308. By operating the transistors at the aforementioned timing, an input potential Vin can be supplied to the first electrode of the capacitor303after the potential of the second electrode of the capacitor303is determined.

In the store period after the write period, the transistors304and306are turned ON and the transistors305,307, and308are turned OFF. A simplified connection between the operational amplifier301and the capacitor303of the voltage follower inFIG. 3Ain the store period is shown inFIG. 3C.

As shown inFIG. 3C, the first electrode of the capacitor303and the non-inverted input terminal of the operational amplifier301are connected in the store period. An input potential Vin is supplied to the first electrode of the capacitor303and the non-inverted input terminal of the operational amplifier301. Therefore, the potential V1of the first electrode of the capacitor303is V1=Vin. The transistor308as a switching element is OFF, therefore, the potential of the second electrode of the capacitor303floats. Therefore, the potential V2of the second electrode of the capacitor303remains as V2=Vpre−Vop as was in the write period. Thus, a potential Vc to be supplied to the capacitor303right before the termination of the write period is stored unchanged as Vc=V1−V2=Vin−Vpre+Vop.

It should be noted that the transistor308is preferably turned OFF at a faster timing than the transistor305when transiting from the write period to the store period. By operating the transistors at the aforementioned timing, a voltage supplied to the capacitor303can be stored without fail.

In the output period after the store period, the transistors306and307are turned ON and the transistors304,305, and308are turned OFF. A simplified connection between the operational amplifier301and the capacitor303of the voltage follower inFIG. 3Ain the output period is shown inFIG. 3D.

As shown inFIG. 3D, the first electrode of the capacitor303and the non-inverted input terminal of the operational amplifier301are connected in the output period. Unlike in the store period, an input potential Vin is not supplied to the first electrode of the capacitor303and the non-inverted input terminal of the operational amplifier301, that is to say, the potential thereof floats. An offset potential Vo is supplied to the second electrode of the capacitor303. Thus, the potential V2of the second electrode of the capacitor303is V2=Vo. The voltage Vc stored in the capacitor303is stored as it is, following the law of conservation of electric charge. Therefore, the potential V1of the first electrode of the capacitor303is V1=V2+Vc=Vo+Vin−Vpre+Vop.

The non-inverted input terminal of the operational amplifier301is connected to the first electrode of the capacitor303and the output terminal of the operational amplifier301has a potential that deducted the offset voltage Vop of the operational amplifier301from the potential of the non-inverted input terminal thereof. Therefore, the potential of the output terminal of the operational amplifier301is V1−Vop=Vo+Vin−Vpre. This potential of the output terminal of the operational amplifier301corresponds to the output potential Vout of the voltage follower, which is obtained as Vout=Vo+Vin−Vpre.

Thus, the output potential Vout is determined by the offset potential Vo, the input potential Vin, and the precharge potential Vpre, independently of the potential of the offset voltage Vop of the operational amplifier301. Therefore, a variation in the output potential Vout of the voltage follower due to a variation in threshold voltage of the transistor can be avoided. By providing the voltage follower on the output side of a signal line driver circuit, a variation in potential of video signals to be inputted to each signal line can be avoided and a visible luminance variation that appears in striped shapes on a semiconductor display device can be avoided.

It is important to set the offset potential Vo, the input potential Vin, and the precharge potential Vpre so that the operational amplifier301operates properly.

Before providing a write period again after the output period, a charge stored in the capacitor303may be reset. By resetting, the charge is to be a constant value at all times regardless of the amount of the charge accumulated in the write period.

In this embodiment, a configuration of a semiconductor display device of the invention having the source follower ofFIG. 1in a driver circuit is described.FIG. 4Ais a block diagram of the semiconductor display device of this embodiment. The semiconductor display device shown inFIG. 4Ais configured with a pixel portion401having a plurality of pixels provided with display elements, a scan line driver circuit402for selecting each of the pixels, and a signal line driver circuit for controlling an input of a video signal to the selected pixel.

The signal line driver circuit403inFIG. 4Acomprises a shift register404and a source follower405. It should be noted that the source follower of the invention is used as an impedance transformer of the signal line driver circuit403, however, the voltage follower of the invention can be used instead.

A clock signal (CLK) and a start pulse (SP) are inputted to the shift register404. When the clock signal (CLK) and the start pulse (SP) are inputted, a timing signal is generated in the shift register404and inputted to the source follower405. Specifically, the timing signal is supplied to the transistor104of the source follower inFIG. 1Aas a potential Vg1.

Potentials Vg2to Vg5to be supplied to the other transistors105to108and a video signal are supplied to the source follower405. A potential of the video signal is supplied to the source follower405as an input potential Vin. Therefore, an output potential of the source follower405obtained by the inputted video signal is supplied to subsequent signal lines in synchronization with the timing signal or the potentials Vg2to Vg5. The output potential may have difference from the input potential, however, the output potential includes image data of the video signals to be supplied to the source follower405. Therefore, the output potential to be supplied to the signal lines is a video signal as well.

In the case of the semiconductor display device having the signal line driver circuit shown inFIG. 4A, the output period can be overlapped with a display period of the pixels and the write period and the store period can be provided during the horizontal flyback period or the vertical flyback period. However, the write period and the store period can be provided during the other period than the flyback periods as needed as long as they are not overlapped with a period for inputting the video signal to the pixels connected to the signal lines.

A configuration of the scan line driver circuit402is described now. The scan line driver circuit402is configured with a shift register406and a buffer407. A level shifter may be included as the case might be. A select signal is generated in the scan line driver circuit402when the clock signal CLK and the start pulse SP are inputted to the shift register406. The generated select signal is then buffer amplified in the buffer407and then supplied to a corresponding scan line. Gates of transistors in one row of pixels are connected to the scan line. As the transistors of one row of pixels have to be turned ON simultaneously, the buffer407is required to be capable of flowing a large current.

It should be noted that the other circuits such as a decoder circuit that can select signal lines may be used instead of the shift registers404and406.

The signal line driver circuit for driving the semiconductor display device of the invention is not limited to the configuration described in this embodiment.

In this embodiment, a configuration of the semiconductor display device of the invention having the source follower ofFIG. 1in a driver circuit is described.FIG. 4Bis a block diagram of the semiconductor display device of this embodiment. The semiconductor display device inFIG. 4Bis configured with a pixel portion411having a plurality of pixels provided with display elements, a scan driver circuit412for selecting each of the pixels, and a signal line driver circuit413for controlling an input of a video signal to the selected pixel.

The signal line driver circuit413inFIG. 4Bcomprises a shift register414, an analog latch A415, an analog latch B416, and a source follower417. It should be noted that the source follower of the invention is used as an impedance transformer of the signal line driver circuit413, however, the voltage follower of the invention can be used instead.

A clock signal (CLK) and a start pulse (SP) are inputted to the shift register414. When the clock signal (CLK) and the start pulse (SP) are inputted, a timing signal is generated in the shift register414and inputted to a first stage of the analog latch A415sequentially. When the timing signal is inputted to the analog latch A415, a video signal is inputted to the analog latch A415sequentially in synchronization with the timing signal and stored therein. It should be noted that the video signal is inputted to the analog latch A415sequentially in this embodiment, however, the invention is not limited to this configuration. The analog latch A415constituted by a plurality of stages may be divided into some groups and the video signals may be inputted to each of the groups in parallel, that is referred to as a division (split) drive. Note that the number of division groups in the division driving is referred to as a division number. For example, in the case of dividing the latch into groups by four stages, it is referred to as a division drive in four.

A time required for inputting video signals into all the stages of latches in the analog latch A415is referred to as a line period. In practice, the line period may include a horizontal flyback period in addition to the aforementioned line period.

After one line period is terminated, a latch signal is supplied to the analog latch B416and the video signals stored in the analog latch A415are supplied to the analog latch B416in synchronization with the latch signals and stored therein. Subsequent video signals are inputted in synchronization with timing signals from the shift register414again to the analog latch A415after supplying the video signals to the analog latch B416. In this second line period, the video signals supplied and stored in the analog latch B416are inputted to the source follower417as an input potential Vin.

The potentials Vg1to Vg5supplied to the transistors104to108are supplied to the source follower417. Therefore, an output potential of the source follower417obtained by the inputted video signal is supplied to subsequent signal lines in synchronization with the latch signals or the potentials Vg1to Vg5.

FIG. 5is an example of a specific circuit diagram of the analog latch A415, the analog latch B416, and the source follower417in the signal line driver circuit413. As shown inFIG. 5, the analog latch A415is configured with a capacitor420and a switch421for controlling a potential supply of a video signal to the capacitor420. Switching of the switch421is controlled by a timing signal. The analog latch B416is configured with a capacitor422and a switch423for controlling the potential supply of the video signal stored in the capacitor420to the capacitor422. Switching of the switch423is controlled by a latch signal.

The source follower417has the same configuration as the source follower inFIG. 1A, in which a potential of a video signal stored in the capacitor422is supplied to the source follower417as an input potential Vin. A switching element may be provided between the source follower417and signal lines so that an output potential which is supposed to be supplied in the output period is not supplied to the signal lines in the write period and the store period.

In the case of the semiconductor display device having the signal line driver circuit shown inFIGS. 4B and 5, the output period can be overlapped with a display period of the pixels and the write period and the store period can be provided during the horizontal flyback period or the vertical flyback period. However, the write period and the store period can be provided during the other period than the flyback periods as needed as long as they are not overlapped with a period for inputting the video signal to the pixels connected to the signal lines.

It should be noted that the other circuits such as a decoder circuit that can select signal lines may be used instead of the shift registers414and416.

The signal line driver circuit can be configured by using the capacitor109of the source follower417as a capacitor of the analog latch and omitting one of the two analog latches.FIG. 6is an example in which a capacitor in the source follower is used as a capacitor of an analog latch in a part of the signal line driver circuit inFIG. 5.

FIG. 6is a circuit diagram of an analog latch430and a source follower431provided in a signal line driver circuit. In the analog latch430, when a switch433is turned ON by a timing signal supplied from a shift register, a potential of a video signal is supplied to a capacitor434and stored therein. A potential of a latch signal is then supplied to the source follower431as Vg1, which controls the switching of the transistor104. When the transistor104is turned ON, the potential of the video signal stored in the capacitor434is supplied to the capacitor432in the source follower431and stored therein. By an output potential of the source follower431supplied to the signal lines, video signals are inputted to each of the pixels.

By using the capacitor of the source follower as the capacitor of the analog latch, the number of analog latches can be reduced drastically as compared to the signal line driver circuit inFIG. 5, thus the area occupied by the signal line driver circuit can be suppressed.

The signal line driver circuit for driving the semiconductor display device of the invention is not limited to the configurations shown inFIGS. 4A,4B and5.

FIG. 7is an outline view of a light emitting device which is included in the semiconductor display devices of the invention. The semiconductor display device includes various modes in which the use of the invention is apparent, such as a component substrate which corresponds to one mode in which transistors for controlling the drive of display elements are formed in each of the pixels but display elements are not formed, a panel which corresponds to a mode in which display elements are formed on the component substrate, and a module which corresponds to a mode in which an IC including a controller, a power supply circuit and the like are implemented in the panel. In this embodiment, an example of a specific configuration of a light emitting device as a module is described.

FIG. 7is an outline view of a module implemented with a controller801and a power supply circuit802in a panel800. The panel800comprises a pixel portion803provided with a light emitting element in each of the pixels, a scan driver circuit804for selecting the pixels in the pixel portion803, and a signal line driver circuit805for supplying video signals to the selected pixels. InFIG. 7, the source follower or the voltage follower of the invention is provided on the output side of the signal line driver circuit805.

A printed substrate806comprises a controller801and a power supply circuit802. Each type of signals and power supply voltage outputted from the controller801or the power supply circuit802are supplied to the pixel portion803, the scan driver circuit804, and the signal line driver circuit805in the panel800via an FPC807. The video signals for controlling the drive of the source follower and the voltage follower are supplied to the signal line driver circuit from the controller801. Each type of signals and power supply voltage to be supplied to the printed substrate806are supplied via an interface (I/F) portion808provided with a plurality of input terminals.

In this embodiment, the panel800is implemented with the printed substrate806via the FPC807, however, the invention is not limited to this structure. The controller801and the power supply circuit802may be directly mounted on the panel800by using COG (Chip On Glass) method. The controller801and the power supply circuit802may be integrated in the panel800as well. Further, in the printed substrate806, capacitance formed between the lead wirings and resistance of the wirings themselves and the like may cause a blunted rise of the signals or a noise in the power supply voltage or the signals. In order to solve the aforementioned problems, a variety of elements such as a capacitor, a buffer or the like may be provided on the printed substrate806to avoid the blunted rise of the signals or a noise in the power supply voltage or the signals.

The semiconductor device of the invention can be applied to a variety of electronic devices, such as a video camera, a digital camera, a goggle display (a head mounted display), a navigation system, an audio reproduction device (a car audio, an audio component system and the like), a laptop computer, a game machine, a portable information terminal (a mobile computer, a cellular phone, a portable game machine or an electric book and the like), an image reproduction device provided with a recording medium (more specifically, a device which can reproduce a recording medium such as a DVD (digital versatile disc) and so forth, and includes a display for displaying the reproduced image), or the like. Specific examples of the electronic devices are shown inFIGS. 8A to 8H.

FIG. 8Aillustrates a display device which includes a housing2001, a display portion2002, and a speaker portion2003. The semiconductor device of the invention can be applied to the display portion2002. The display device includes a whole series of display device for displaying information, such as a personal computer, a receiver of TV broadcasting and an advertising display. The semiconductor device of the invention can be applied to the display portion2002and the other signal processing circuit.

FIG. 8Billustrates a digital still camera which includes a body2101, a display portion2102, an image receiving portion2103, an operation key2104, an external connection port2105, a shutter2106and the like. The semiconductor device of the invention can be applied to the display portion2102or the other signal processing circuit.

FIG. 8Cillustrates a laptop computer which includes a body2201, a housing2202, a display portion2203, a keyboard2204, an external connection port2205, a pointing mouse2206and the like. The semiconductor device of the invention can be applied to the display portion2203or the other signal processing circuit.

FIG. 8Dillustrates a mobile computer which includes a body2301, a display portion2302, a switch2303, an operation key2304, an infrared port2305and the like. The semiconductor device of the invention can be applied to the display portion2302or the other signal processing circuit.

FIG. 8Eillustrates a portable image reproduction device provided with a recording medium (specifically a DVD reproduction device), which includes a body2401, a housing2402, a display portion A2403, a display portion B2404, a recoding medium (DVD or the like) reading portion2405, an operation key2406, a speaker portion2407and the like. The display portion A2403mainly displays image data while the display portion B2404mainly displays text data. Note that the image reproduction device provided with a recording medium includes a domestic game machine and the like. The semiconductor device of the invention can be applied to the display portions A2403and B2404or the other signal processing circuit.

FIG. 8Fillustrates a goggle type display (a head mounted display) which includes a body2501, a display portion2502, and an arm portion2503. The semiconductor device of the invention can be applied to the display portion2502or the other signal processing circuit.

FIG. 8Gillustrates a video camera which includes a body2601, a display portion2602, a housing2603, an external connection port2604, a remote control receiving portion2605, an image receiving portion2606, a battery2607, an audio input portion2608, operation keys2609and the like. The semiconductor device of the invention can be applied to the display portion2602or the other signal processing circuits.

FIG. 8Hillustrates a cellular phone which includes a body2701, a housing2702, a display portion2703, an audio input portion2704, an audio output portion2705, an operation key2706, an eternal connection port2707, an antenna2708and the like. Note that the power consumption of the cellular phone can be reduced by displaying a white text on a black background in the display portion2703. The semiconductor device of the invention can be applied to the display portion2703and the other signal processing circuits.

As described above, the applicable range of the invention is so wide that the invention can be applied to electronic devices of various fields.