Semiconductor package

A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2015-0132601, filed on Sep. 18, 2015, in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

Some embodiments of the present inventive concepts relate to a semiconductor package, and, more particularly, to a semiconductor package including a seed layer having a curved portion and located under a bump.

A demand for portable devices has rapidly increased. As a result, it is necessary to downscale and reduce a weight of electronic components mounted in portable devices. In order to manufacture lightweight, downscaled electronic components, there is a tendency to decrease the thickness of a semiconductor package. Also, there is a need to increase the memory capacity of a semiconductor package. In order to embody high-capacity memory in a limited structure of a semiconductor package, small-sized external connection terminals may be required. Thus, there is a tendency to downscale bumps formed in the semiconductor package.

SUMMARY

Example embodiments of the present inventive concepts provide a semiconductor package including a seed layer having a curved portion and located under a bump, so that an undercut may be minimized.

According to an aspect of the present inventive concepts, there is provided a semiconductor package including a semiconductor substrate and an electrode pad on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion. A first pattern is located on the peripheral portion. A passivation layer is on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is on the electrode pad and the passivation layer. The seed layer has a third pattern on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed in the third pattern located under an edge of a lower portion of the bump.

In some embodiments, the bump may include a pillar layer being in contact with the seed layer and a solder layer on the pillar layer.

In some embodiments, a top surface of the pillar layer may be a flat surface, and a bottom surface of the pillar layer may include a curved surface corresponding to the third pattern.

In some embodiments, a distance from a center of the pillar layer to a side surface of the pillar layer may be greater than a distance from a center of the seed layer to a side surface of the seed layer.

In some embodiments, in the electrode pad, the first pattern may be spaced apart from the central portion and surrounds the central portion. A top surface of the first pattern may be at the same level as a top surface of the central portion.

In some embodiments, the first pattern may be a plurality of isolated fine patterns. A width of each of the fine patterns may be substantially equal to a distance between the fine patterns.

In some embodiments, in the electrode pad, the first pattern may be connected to the central portion, and a top surface of the first pattern may be a curved surface.

In some embodiments, the second pattern may have a shape corresponding to the first pattern, and the third pattern may have a shape corresponding to the second pattern.

In some embodiments, in the passivation layer, the opening may be surrounded by the second pattern.

In some embodiments, the passivation layer may be a silicon oxide layer or a silicon nitride layer.

According to another aspect of the present inventive concepts, there is provided a semiconductor package including a semiconductor substrate having an electrode pad exposed by a passivation layer. A redistribution is on the electrode pad and the passivation layer. The redistribution is electrically connected to the electrode pad. The redistribution has a first pattern in a region spaced apart from the electrode pad. An insulating layer is on the redistribution and the passivation layer. The insulating layer has an opening exposing a portion of the redistribution and a second pattern on the first pattern. A seed layer is on the redistribution and the insulating layer. The seed layer has a third pattern on the second pattern. A bump is on the seed layer and electrically connected to the redistribution. An undercut is formed in the third pattern located under an edge of a lower portion of the bump.

In some embodiments, the second pattern may have substantially a same top profile as the third pattern.

In some embodiments, a top surface of the redistribution exposed by the opening may be a flat surface.

In some embodiments, in the insulating layer, the opening may be surrounded by the second pattern.

In some embodiments, the insulating layer may be a silicon oxide layer or a silicon nitride layer.

In some embodiments, a semiconductor package includes a semiconductor substrate, and an electrode pad on the semiconductor substrate and including a central portion and a peripheral portion. A first pattern is located on the peripheral portion. The semiconductor package further includes a passivation layer on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern and surrounding the opening exposing the central portion of the electrode pad. The semiconductor package further includes a seed layer on the electrode pad and the passivation layer and having a third pattern on the second pattern and a bump on the seed layer and electrically connected to the electrode pad. An undercut is formed under the bump and a distance from a center of the bump to a side surface of the bump is greater than a distance from a center of the seed layer to a side surface of the seed layer.

In some embodiments, the first pattern, the second pattern, the third pattern and a bottom surface of the bump have curved surfaces.

In some embodiments, the undercut is formed by removing a portion of the third pattern.

In some embodiments, the bump comprises a pillar layer being in contact with the seed layer and a solder layer on the pillar layer.

In some embodiments, a top surface of the pillar layer is a flat surface, and a bottom surface of the pillar layer is a curved surface corresponding to the third pattern.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments of the present inventive concepts are shown. The present inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein.

As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Like numerals refer to like elements throughout.

FIGS. 1A and 1Bare plan views andFIG. 2is a cross-sectional view illustrating an electrode pad according to some example embodiments of the present inventive concepts. Specifically,FIG. 2is a cross-sectional view taken along a line II-II′ ofFIGS. 1A and 1B.

Referring toFIGS. 1A, 1B, and 2, an electrode pad110may be disposed on a semiconductor substrate100. The electrode pad110may externally expand a function of a circuit included in a semiconductor device. The semiconductor substrate100may be, for example, a semiconductor wafer substrate including, for example, a plurality of semiconductor chips, which are arranged as a matrix type and divided from one another by a scribe line (not shown).

A circuit portion may be formed in the semiconductor substrate100by using a semiconductor manufacturing process. The circuit portion may include, for example, discrete unit devices. That is, a transistor(s), a resistor(s), a capacitor(s), a conductive interconnection(s), and an insulating layer(s) located among the transistor(s), the resistor(s), the capacitor(s), and the conductive interconnection(s) may be formed in the semiconductor substrate100.

Various semiconductor devices, for example, a memory device, for example, dynamic random access memory (DRAM), flash memory, or the like, a logic device, for example, a microprocessor (MP)), an analog device, a digital signal processor (DSP) device, a system-on chip (SOC) device, a combination thereof or the like, may be formed on the semiconductor substrate100.

The electrode pad110may be electrically connected to the circuit portion of the semiconductor device so that the semiconductor device may be electrically connected to an external device. A plurality of electrode pads110via which electric signals are input/output to and from the semiconductor substrate100may be provided on the semiconductor substrate100. The plurality of electrode pads110may include a metal having a low resistivity, for example, aluminum (Al) and copper (Cu).

The electrode pad110may be electrically connected to a metal interconnection located thereunder through a via. The formation of the electrode pad110may include depositing a metal, for example, aluminum (Al), on the semiconductor substrate100to a predetermined thickness and performing a photolithography process and an etching process to obtain a desired shape of the electrode pad110. Since the photolithography process and the etching process are typical processes, detailed descriptions thereof are omitted.

In some embodiments, the electrode pad110having a central portion and a peripheral portion may be formed by using a photolithography process and an etching process. A central pattern110C may be formed in the central portion of the electrode pad110and electrically connected to the via thereunder. The central pattern110C may have the same shape as a typical electrode pad. Although the central pattern110C is illustrated as having a regular tetragonal shape, the central pattern110C is not limited thereto. For example, the central pattern110cmay have a polygonal shape, such as a tetragonal shape, a hexagonal shape, or an octagonal shape, a circular shape, or an elliptical shape. The central pattern110C may have at least a predetermined size in order to resist electrical or mechanical stress.

A first pattern110P may be formed in the peripheral portion of the electrode pad110and surround the central pattern110C. The first pattern110P may include a plurality of fine patterns. While the first pattern110P is illustrated as having a regular tetragonal shape, the first pattern110P is not limited thereto. For example, the first pattern110P may have a polygonal shape, such as a tetragonal shape, a hexagonal shape, or an octagonal shape, a circular shape, or an elliptical shape, according to the shape of the central pattern110C. The first pattern110P may have a predetermined width W1. A distance W2between first patterns110P may be substantially the same as a width W1of the first patterns110P. However, the present inventive concepts are not limited thereto, and the width W1of the first patterns110P and the distance W2between the first patterns110P may vary according to a shape of a third pattern, for example, third pattern130P inFIG. 4, to be formed.

As illustrated inFIG. 1A, the central pattern110C and the first pattern110P may be formed spaced apart from each other. Also, the first patterns110P may be formed spaced apart from one another.

As illustrated inFIG. 1B, the first pattern110P may have a checked shape. In such an embodiment, the first pattern110P may be electrically connected to the central pattern110C and includes a large number of curved patterns formed per unit area, bonding strength may increase so that stress applied to the bump, for example, bump structure145R inFIG. 9, may be reduced. That is, the central pattern110C may contact the first pattern110P.

FIGS. 3 to 9are cross-sectional views of a method of manufacturing a semiconductor package using the semiconductor substrate, for example, semiconductor substrate100inFIG. 1A, having the electrode pad, for example, electrode pad110inFIG. 1A, according to some example embodiments of the present inventive concepts.

Referring toFIG. 3, a passivation layer120may be formed on the electrode pad110and the semiconductor substrate100. The passivation layer120may include an opening120H and a second pattern120P. The opening120H may expose a portion of the central pattern110C of the electrode pad110, and the second pattern120P may be formed on the first pattern110P of the electrode pad110. The passivation layer120may be formed on a portion of the central pattern110C, for example, an edge portion of the central pattern110C, on the first pattern110P, in the openings between the second patterns110P and in the opening between the central pattern110C and the first pattern110P.

The exposed portion of the central pattern110C of the electrode pad110may be exposed by the passivation layer120. The passivation layer120is a final protection layer of the circuit portion of the semiconductor device. The electrode pad110may be electrically connected to the circuit portion of the semiconductor device through the via thereunder, and an exposed portion of the electrode pad110, that is, the exposed portion of the central pattern110C, may be electrically connected to an external device through an external connection terminal.

The opening120H may have the same size as in a typical electrode pad. Since the electrode pad110according to the present example embodiment includes the first pattern110P formed in the peripheral portion thereof, the passivation layer120may have the second pattern120P formed along a top profile of the first pattern110P.

The opening120H in the passivation layer120may be surrounded by the second pattern120P. That is, during a process of foaming the passivation layer120, the passivation layer120may be formed in such an appropriate position that the opening120H may expose the portion of the central pattern110C of the electrode pad110and be surrounded by the second pattern120P.

The passivation layer120may be formed along exposed regions of the substrate100and on the electrode pad110on the semiconductor substrate100except for the exposed portion of the central pattern110C. Thus, the semiconductor substrate100may be insulated in the regions except the electrode pad110through hole12011along the central pattern110C. Also, the passivation layer120may serve to protect a top surface of the semiconductor substrate100from external impurities and physical impact. The passivation layer120may include a plurality of layers.

In general, the passivation layer120may include, for example, one material selected from the group consisting of silicon oxide, silicon nitride, polyimide (PI), benzocyclobutene (BCB), polybenzoxaxole (PBO), bismaleimide triazine (BT), phenolic resin, an epoxy, or the like.

In this example embodiment, since the passivation layer120includes the second pattern120P, the passivation layer120may include, for example, a silicon oxide layer or a silicon nitride layer. A silicon-based insulating layer may have good insulating characteristics and be formed based on a shape of an underlying layer. Accordingly, the passivation layer120may have the second pattern120P having a shape corresponding to a shape of the first pattern110P. A profile of the second pattern120P may be substantially the same as or approximately similar to a profile of the first pattern110P. The shape of the second pattern120P may vary according to materials, process conditions, and subsequent processes.

Referring toFIG. 4, a seed layer130may be formed on the electrode pad110and the passivation layer120. The seed layer130may be formed on the exposed surfaces of the electrode pad110, that is, the central pattern110C exposed by opening12011, and the passivation layer120. The seed layer130may be formed by, for example, using a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process to a thickness of about 100 Å to about 0.5 μm. The seed layer130may include, for example, a metal, such as copper (Cu), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), silver (Ag), or an alloy thereof. The seed layer130may be a single layer or a multilayered structure.

The seed layer130may function as a seed for forming a bump structure, for example, bump structure145inFIG. 6. That is, when the bump structure145is formed by using an electroplating process, the seed layer130may provide a current path so that the bump structure145may be formed on the seed layer130.

The seed layer130may include a third pattern130P formed on the second pattern120P of the passivation layer120. A top surface of the third pattern130P may have substantially the same profile as a top surface of the second pattern120P. Also, the seed layer130may substantially planarly cover the entire opening120H of the passivation layer120. That is, the third pattern130P may not be fonned on a region in contact with the electrode pad110. Thus, the third pattern130P surrounds the opening120H and does not contact the exposed portion of the central pattern110C exposed through opening120H.

Referring toFIG. 5, a photoresist pattern PR may be formed on the seed layer130. The photoresist pattern PR may expose a portion of the seed layer130.

The exposed portion of the seed layer130may include a portion of the seed layer130, which is in contact with the electrode pad110, and the third pattern130P. That is, the substantially planar portion of the seed layer130covering the opening120H of the passivation layer120and the third pattern130P are exposed by the photoresist PR. Since a portion of the seed layer130exposed by the photoresist pattern PR corresponds to a portion in which a bump structure, for example, bump structure145inFIG. 6, will be formed in a subsequent process, when a plurality of electrode pads110are formed, a plurality of portions may be exposed by the photoresist pattern PR which correspond to the respective electrode pads110. A portion exposed by the photoresist pattern PR may be referred to as a ball land.

Referring toFIG. 6, a double structure including a pillar layer140and a solder layer150may be formed on the seed layer130on which the photoresist pattern PR is formed. However, the present inventive concepts are not limited thereto. For example, a single structure including the solder layer150may be formed on the seed layer130on which the photoresist pattern PR is formed. The pillar layer140and the solder layer150may form bump structure145.

The pillar layer140may be formed on an exposed top surface of the seed layer130which is exposed by the photoresist pattern PR. The pillar layer140may be formed by, for example, using an electroplating process. The electroplating process for forming the pillar layer140may be referred to as a first electroplating process.

A thickness of a portion of the pillar layer140formed on a region130C of the seed layer130in contact with the central pattern110C of the electrode pad110may be different from a thickness of a portion of the pillar layer140formed on the third pattern130P of the seed layer130. A bottom surface of the pillar layer140may have a shape corresponding to a top profile of the third pattern130P along the third pattern130P and a shape corresponding to a top profile of the region130C along the region130C. In contrast, a top surface of the pillar layer140may be a flat surface.

To form the pillar layer140, the semiconductor substrate100on which the photoresist pattern PR is formed may be put in a bath, and a first electroplating process may be performed. The pillar layer140may be, for example, a single layer including, for example, a metal selected out of copper (Cu), nickel (Ni), and gold (Au), or an alloy thereof, or a multilayered structure including, for example, at least two metals selected out of copper (Cu), nickel (Ni), and gold (Au).

The pillar layer140may partially fill, that is, not completely, a region exposed by the photoresist pattern PR. That is, the pillar layer140may be formed to a smaller thickness than a thickness of the photoresist pattern PR.

The solder layer150may be formed on the pillar layer140. A top surface of the solder layer150may be coplanar with or protrude over a top surface of the photoresist pattern PR. The solder layer150may be formed by using an electroplating process. To distinguish from the first electroplating process for forming the pillar layer140, the electroplating process for forming the solder layer150may be referred to as a second electroplating process.

In order to form the solder layer150, the semiconductor substrate100on which the pillar layer140is formed may be put into a bath that is different from the bath used in the first electroplating process, and a second electroplating process may be performed. The solder layer150may be, for example, an alloy of tin (Sn) and silver (Ag), and small amounts of, for example, copper (Cu), palladium (Pd), bismuth (Bi), and/or antimony (Sb) may be added to the solder layer150.

Referring toFIG. 7, the photoresist pattern, for example, photoresist pattern PR inFIG. 6, may be removed, and a portion of the seed layer130may be removed. For example, the portion of the seed layer130under the photoresist pattern PR and a portion of the seed layer130under the pillar layer140, that is undercut130U, may be removed.

The photoresist pattern PR may be removed by using a strip process or an ashing process. After the photoresist pattern PR is removed, the exposed seed layer130may be wet etched by using the pillar layer140and the solder layer150as an etch mask. When the seed layer130is wet etched by using an isotropic etching process, the undercut130U may be formed in a lower portion of the pillar layer140.

When a material included in the seed layer130is copper (Cu), the seed layer130may be removed by an ammoniacal etching process. For example, the seed layer may be removed by using alkaline etchants including, for example, Cu(NH3)4Cl2, Cu(NH3)2Cl, NH3, and NH4Cl. Thereafter, chemicals containing CuO, which are obtained as a result of the etching process, may be cleaned by using, for example, NH3 and water (H2O).

The undercut130U may be formed under the bump structure145by etching a side surface of the seed layer130. The undercut130U may extend under the bump structure145to a length of about several μm, for example more than 2 μm. Since the undercut130U is formed by removing a portion of the third pattern130P under the pillar layer140, the undercut130U may have the same shape as the third pattern130P. That is, the undercut130U may have a curved surface unlike a typical undercut.

Due to the undercut130U, a distance from a center of the pillar layer140to a side surface of the pillar layer140may be greater than a distance from a center of the seed layer130to the side surface of the seed layer130. That is, a lower edge of the pillar layer140may include an exposed region, which is out of contact with the seed layer130. That is, a lower edge of the pillar layer140and an upper surface of the third pattern130P may be exposed by the undercut130U.

FIG. 8shows a shape of an undercut130AU according to a conventional example and a shape of an undercut130U according to some example embodiments of the present inventive concepts.

(a) ofFIG. 8shows the shape of the undercut130AU according to a conventional example. In the conventional example, since a pattern having a curved surface is not formed on a seed layer130A, unlike in the example embodiments of the present inventive concepts, the undercut130AU may be formed to a predetermined length LA under a pillar layer140A. When the length LA of the undercut130AU increases, the pillar layer140A may be delaminated from electrode pads so that yield may be reduced in a process of forming a bump structure. Also, when a process time for a wet etching process is reduced to reduce the length LA of the undercut130AU, the seed layer130A may be unetched in a large number of bump structures.

(b) ofFIG. 8shows the shape of the undercut130U according to some embodiments of the present inventive concepts and is an enlarged view of a portion C ofFIG. 7. In some embodiments, a third pattern130P may be formed in a portion of a seed layer130and may have a curved surface. As described above, the undercut130U may be formed during a process of wet etching the seed layer130. Since the wet etching process is an isotropic etching process, an etching process may be performed to the same length for the same process time.

Accordingly, as compared with (a) ofFIG. 8, in the same process conditions as process conditions in which the undercut130AU is formed to a length LA of, for example, about 10 μm, an etch length L1obtained in the present example embodiments may also be about 10 μm. That is, the total path by which an etching process is performed in the conventional example of (a) ofFIG. 8may be the same as the total path by which an etching process is performed in the present example embodiments of the present inventive concepts, as illustrated in (b) ofFIG. 8.

In contrast, in the example embodiments of the present inventive concepts, since the etching is performed along the curved surface of the third pattern130P, the undercut13QU formed under the pillar layer140may substantially have a length L2. That is, a vertical distance between a sidewall of the pillar layer140and a sidewall of the seed layer130may correspond to the length L2. For example, when the curved surface of the third pattern130P has a regular triangular shape, the length L2of the undercut130U may be about 5 μm. Accordingly, it can be seen in (b) ofFIG. 8that the undercut130U according to some embodiments of the present inventive concepts is formed to the length L2corresponding to half of the length LA of the undercut130AU according to the conventional example as illustrated in (a) ofFIG. 8. That is, the length L2of the undercut130U may be less than the total etched length L1.

FIG. 9is a cross-sectional view of a process of forming a semiconductor package10by performing a reflow process on the solder layer, for example, solder layer150inFIG. 7, according to some embodiments of the present inventive concepts.

A reflow process may be performed by using an annealing process on the semiconductor substrate100from which the photoresist pattern, for example, photoresist pattern PR inFIG. 6, and a portion of the seed layer, for example, seed layer130inFIG. 6, are removed. The reflow process may be performed at a temperature of about 220° C. to about 260° C. The solder layer150may melt due to the reflow process to form a reflow solder layer150R. The solder layer150may melt but not collapse so that the reflow solder layer150R may be formed on the pillar layer140due to surface tension. An intermetallic compound may be formed at an interface between the reflow solder layer150R and the pillar layer140. A distance from a center of the reflow solder layer150R to a side surface of the reflow solder layer150R may be greater than a distance from a center of the pillar layer140to a side surface of the pillar layer140.

A bump145R may include the pillar layer140and the reflow solder layer150R. However, the present inventive concepts are not limited thereto. For example, the bump145R may include only the reflow solder layer150R. A type of the bump145R may vary according to a semiconductor package to be manufactured. The bump145R may function as an external connection terminal and be a point of contact, which may be electrically connected to an external apparatus. The semiconductor package10may include a plurality of bumps145R, although only one bump145R is illustrated.

In order to embody a high-capacity memory in a limited structure of a semiconductor package, small-sized external connection terminals may be required. Thus, bumps included in the semiconductor package tend to be continuously downscaled. The downscaling of the bumps has led to ever-increasing malfunctions in products due to undercuts. For example, an excessive undercut may weaken bonding strength between a bump and an electrode pad so that the bump may be delaminated from the electrode pad.

The undercuts should be reduced to prevent occurrence of the malfunctions. According to some embodiments of the present inventive concepts, in the semiconductor package10, an undercut may be formed along a curved surface. Thus, the total length of the path of the etching of the undercut may be the same, but a substantial length of the undercut may be reduced. The semiconductor package10according to the example embodiments of the present inventive concepts may reduce malfunctions caused by undercuts or a non-etch phenomenon.

The semiconductor package10according to the example embodiments may reduce malfunctions in a process of forming a bump and increase yield. Thus, manufacturing costs may be reduced, and manufacturing efficiency may increase. Furthermore, even if a seed layer is not sufficiently etched, a rework process may be enabled a plurality of times by using an undercut having a smaller length than in the conventional example.

FIG. 10is a plan view andFIG. 11is a cross-sectional view of a semiconductor package according to some example embodiments of the present inventive concepts.

Specifically,FIG. 10is a plan view of a semiconductor substrate100having an electrode pad112according to some example embodiments, andFIG. 11is a cross-sectional view of a semiconductor package20formed on the semiconductor substrate100.FIG. 11is a cross-sectional view taken along a line II-II′ ofFIG. 10after a semiconductor package manufacturing process is performed.

Referring toFIGS. 10 and 11, in the present example embodiment, the electrode pad112having a central portion and a peripheral portion may be formed by using a photolithography process and an etching process. A first pattern112P may be formed in the peripheral portion and surround the central portion. The first pattern112P may include a plurality of fine patterns. The first pattern112P may be formed in the peripheral portion of the electrode pad112. The first pattern112P, unlike the first pattern110P does not expose the substrate100. That is, the first pattern112P has a thickness less than a total thickness of the electrode pad112. By etching only a portion of the electrode pad112, the first pattern112P may be electrically connected to the central portion of the electrode pad112. The electrode pad112having the central portion and the peripheral portion having the first pattern112P may be formed by using known photolithography and etching processes and, thus, detailed descriptions thereof are omitted.

The semiconductor package20is the same as the above-described semiconductor package, for example, semiconductor package10inFIG. 9, in that a passivation layer120having a second pattern120P, a seed layer130having a third pattern130P, and a bump145R are formed on the electrode pad112, and thus detailed descriptions thereof are omitted.

FIG. 12is a plan view andFIG. 13is a cross-sectional view of a semiconductor package according to some example embodiments of the present inventive concepts.

Specifically,FIG. 12is a plan view of a semiconductor substrate100including an electrode pad114according to some example embodiments, andFIG. 13is a cross-sectional view of a semiconductor package30formed on the semiconductor substrate100.FIG. 13is a cross-sectional taken along a line ofFIG. 12after a semiconductor package manufacturing process is performed.

Referring toFIGS. 12 and 13, in the present example embodiment, the electrode pad114having a central portion and a peripheral portion may be formed by using a photolithography process and an etching process. An electrode pad under layer113including a different material from the electrode pad114may be formed under the electrode pad114. That is, a process of forming an electrode pad including a double layer may be performed. Each of the electrode pad under layer113and the electrode pad114may include a conductive material. A first pattern114P may be formed in the peripheral portion of the electrode pad114and surround the central portion of the electrode pad114. The first pattern114P may include a plurality of fine patterns. The first pattern114P may be spaced apart from the central portion of the electrode pad114and surround the central portion of the electrode pad114. The first patterns114P may be spaced apparat from each other and spaced apart from the central portion of the electrode pad114and may expose a top surface of the electrode pad under layer113. The electrode pad114, the first pattern114P, and the electrode pad under layer113may be electrically connected to one another. The electrode pad114having the central portion and the peripheral portion may be formed by using known photolithography and etching processes and, thus, detailed descriptions thereof are omitted.

The semiconductor package30is the same as the above-described semiconductor package, for example, semiconductor package10inFIG. 9, in that a passivation layer120having a second pattern120P, a seed layer130having a third pattern130P, and a bump145R are formed on the electrode pad114, and, thus, detailed descriptions thereof are omitted.

FIGS. 14 to 20are cross-sectional views of a method of manufacturing a semiconductor package according to some example embodiments of the present inventive concepts.

Referring toFIG. 14, an electrode pad202may be formed on a semiconductor substrate200, and a passivation layer204exposing a portion of the electrode pad202may be formed. A redistribution210may be formed on the electrode pad202and the passivation layer204. The redistribution210may be electrically connected to the electrode pad202and have a first pattern210P formed in a region separate, that is, spaced apart, from the electrode pad202. Materials included in the semiconductor substrate200, the electrode pad202, and the passivation layer204may be the same as those of the semiconductor package, for example, semiconductor package10inFIG. 9.

The redistribution210may include, for example, a metal. For example, the redistribution210may include copper (Cu), nickel (Ni), gold (Au), chromium (Cr), titanium (Ti), palladium (Pd) or an alloy thereof. The redistribution210may be formed by using an electroplating process. The first pattern210P may be formed in a portion of the redistribution210by using a photolithography process and an etching process.

Referring toFIG. 15, an insulating layer220may be formed on the redistribution210and the passivation layer204. The insulating layer220may include an opening220H and a second pattern220P. The opening220H may expose a portion of the redistribution210. The second pattern220P of the insulating layer220may be formed on the first pattern210P of the redistribution210.

The opening220H may have the same size as a typical ball land. Since the redistribution210according to the present example embodiment includes the first pattern210P, the insulating layer220may have the second pattern220P formed along a top profile of the first pattern210P.

The opening220H in the insulating layer220may be surrounded by the second pattern220P of the insulating layer220. That is, during the process of forming the insulating layer220, the insulating layer220may be formed such that the opening220H may expose the portion of the redistribution210and be surrounded by the second pattern220P.

The insulating layer220may be formed such that the redistribution210is insulated in all regions except for in the opening220H. The insulating layer220may have a multilayered structure.

In the present example embodiment, since the insulating layer220includes the second pattern120P, the insulating layer220may include, for example, a silicon oxide layer or a silicon nitride layer. A silicon-based insulating layer may have good insulating characteristics and be formed based on a shape of an underlying layer. Accordingly, the insulating layer220may have the second pattern220P having a shape corresponding to a shape of the first pattern210P. A profile of the second pattern220P may be substantially the same as or approximately similar to a profile of the first pattern210P. A shape of the second pattern220P may vary according to materials, process conditions, and subsequent processes.

Referring toFIG. 16, the seed layer230may include a third pattern230P formed on the second pattern220P of the insulating layer220. A top surface of the third pattern230P may have substantially the same profile as a top surface of the second pattern220P. Also, the seed layer230may substantially planarly cover the entire opening220H of the insulating layer220. That is, the third pattern230P may not be formed on a region in contact with the redistribution210. Thus, the third pattern230P surrounds the opening220H and does not contact the exposed portion of the redistribution210exposed through opening220H.

Since the seed layer230is formed by using the same material and formation process as the seed layer130of the semiconductor package10ofFIG. 9, detailed descriptions thereof are omitted.

Referring toFIG. 17, a photoresist pattern PR may be formed on the seed layer230. The photoresist pattern PR may expose a portion of the seed layer230.

The exposed portion of the seed layer230may include a portion of the seed layer230, which is in contact with the redistribution210, and the third pattern230P. That is, the substantially planar portion of the seed layer230covering the opening220H of the insulating layer220and the third pattern230P are exposed by the photoresist PR. Since a portion, that is, a ball land, of the seed layer230exposed by the photoresist pattern PR corresponds to a portion in which a bump structure, for example, bump structure245inFIG. 18, will be formed in a subsequent process, when a plurality of redistributions210are formed, a plurality of portions may be exposed by the photoresist pattern PR which correspond to the respective redistributions210.

Referring toFIG. 18, a double structure including a pillar layer240and a solder layer250may be formed on the seed layer230on which the photoresist pattern PR is formed. However, the present inventive concepts are not limited thereto. For example, a single structure including a solder layer250may be formed on the seed layer230on which the photoresist pattern PR is formed. The pillar layer240and the solder layer250may form bump structure245.

A thickness of a portion of the pillar layer240formed on a region of the seed layer230in contact with the redistribution210may be different from a thickness of a portion of the pillar layer240formed on the third pattern230P of the seed layer230. A bottom surface of the pillar layer240may have a shape corresponding to a top profile of the third pattern230P along the third pattern230P and a shape corresponding to a top profile of the seed layer230in opening220H along the opening220H. In contrast, a top surface of the pillar layer240may be a flat surface.

Since the pillar layer240and the solder layer250are formed by using the same materials and formation processes as the pillar layer, for example, pillar layer140inFIG. 7, and the solder layer, for example, solder layer150inFIG. 7, as described above, detailed descriptions thereof are omitted.

Referring toFIG. 19, the photoresist pattern, for example, photoresist pattern PR inFIG. 18, may be removed, and a portion of the seed layer230may be removed. For example, the portion of the seed layer230under the photoresist pattern PR and a portion of the seed layer230under the pillar layer240, that is undercut230U, may be removed.

The photoresist pattern PR may be removed by using, for example, a strip process or an ashing process. After the photoresist pattern PR is removed, the exposed seed layer230may be wet etched by using the pillar layer240and the solder layer250as an etch mask. When the seed layer230is wet etched by using an isotropic etching process, the undercut230U may be formed in a lower portion of the pillar layer240.

The undercut230U may be formed under the bump structure245by etching a side surface of the seed layer230. The undercut230U may extend under the bump structure245to a length of about several μm, for example, more than 2 μm. Since the undercut230U is formed by removing a portion of the third pattern230P under the pillar layer240, the undercut230U may have the same shape as the third pattern230P. That is, the undercut230U may have a curved surface unlike the undercut130AU of (a) ofFIG. 8according to the conventional example.

Since the wet etching process is substantially the same as the wet etching process for manufacturing the semiconductor package, for example, semiconductor package10inFIG. 9, detailed descriptions thereof are omitted.

FIG. 20is a cross-sectional view of a process of forming a semiconductor package40by performing a reflow process on the solder layer, for example, solder layer250inFIG. 19, according to some example embodiments of the present inventive concepts.

By melting the solder layer250due to a reflow process, a reflow solder layer250R may be formed. A bump245R may include the pillar layer240and the reflow solder layer250R, However, the present inventive concepts are not limited thereto. For example, the bump245R may include only the reflow solder layer250R. A type of the bump245R may vary according to a semiconductor package to be manufactured. The bump245R may function as an external connection terminal and be a point of contact, which may be electrically connected to an external apparatus. Although the semiconductor package40may include a plurality of bumps245R, only one bump245R is illustrated inFIG. 20.

In a semiconductor package, for example, a wafer-level package, a redistribution may be formed on an electrode pad so that an external connection terminal may be located on the surface of a semiconductor substrate, and a position of the electrode pad may be different from a position of the external connection terminal by using the redistribution.

During a process of forming a bump on the redistribution, an undercut may occur and bonding strength of the bump may be degraded causing malfunctions. Thus, by forming a pattern capable of minimizing undercuts as in the example embodiments of the present inventive concepts, process malfunctions may be reduced to increase yield. As a result, manufacturing costs may be reduced, and manufacturing efficiency may increase.

FIG. 21is a plan view of a memory module1100including a semiconductor package according to some example embodiments of the present inventive concepts.

Referring toFIG. 21, the memory module1100may include a module substrate1110and a plurality of semiconductor packages1120adhered to the module substrate1110.

The plurality of semiconductor packages1120may include a semiconductor package according to the example embodiments of the present inventive concepts. That is, the plurality of semiconductor packages1120may include at least one of the semiconductor packages10,20,30, and40illustrated in connection withFIGS. 9, 11, 13, and/or20.

A connector1130may be located on one side of the module substrate1110and inserted into a socket of a mainboard. A ceramic decoupling capacitor1140may be located on the module substrate1110. The memory module1100according to the present example embodiments is not limited to the construction shown inFIG. 21but may be manufactured in various forms.

FIG. 22is a block diagram of a system1200including a semiconductor package according to some example embodiments of the present inventive concepts.

Referring toFIG. 22, the system1200may include a controller1210, an I/O device1220, a storage device1230, an interface1240and a bus1250.

The system1200may be, for example, a mobile system or a system configured to transmit or receive information. In some embodiments, the mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or the like.

The controller1210may be configured to control an execution program in the system1200. The controller1210may include, for example, a microprocessor (MP), a digital signal processor (DSP), a microcontroller (MC), or a device similar thereto.

The I/O device1220may be used to input or output data to the system1200. The system1200may be connected to an external apparatus, for example, a personal computer (PC) or a network) by using the I/O device1220and exchange data with the external apparatus. The I/O device1220may be, for example, a keypad, a keyboard, a display, or the like.

The storage device1230may store codes and/or data for operations of the controller1210or store data processed by the controller1210. The storage device1230may include a semiconductor package according to some embodiments of the present inventive concepts. That is, the storage device1230may include at least one of the semiconductor packages10,20,30, and40illustrated in connection withFIGS. 9, 11, 13, and/or20.

The interface1240may be a data transmission path between the system1200and another external apparatus. The controller1210, the I/O device1220, the storage device1230, and the interface1240may communicate with one another via the bus1250.

The system1200may be used for, for example, a mobile phone, a MPEG-1 audio layer 3 (MP3) player, a navigation, a portable multimedia player (PMP), a solid-state disk (SSD), household appliances, or the like.

FIG. 23is a block diagram of a memory card1300including a semiconductor package according to some example embodiments of the present inventive concepts.

Referring toFIG. 23, the memory card1300may include, for example, a storage device1310and a memory controller1320.

The storage device1310may store data. In some embodiments, the storage device1310may have non-volatile characteristics and retain stored data even if a power supply is interrupted. The storage device1310may include a semiconductor package according to the example embodiments of the present inventive concepts. That is, the storage device1310may include at least one of the semiconductor packages10,20,30, and40illustrated in connection withFIGS. 9, 11, 13, and/or20.

The memory controller1320may read data stored in the storage device1310or store data in the storage device1310in response to read/write requests from a host1330.