Architecture for ensuring monotonicity in a digital-to-analog converter

A current-mode, digital-to-analog converter (DAC) configured to convert a digital word input having j bits to an analog signal. The DAC has 2j current sources, an output node, a current divider, a first switch, and a second switch. Each of the 2j current sources is configured to produce a current having a value I0. The current divider has a programmable divide ratio, d, where 1/d is between 0 and 1. The first switch is configured to selectively couple 2j−1 of the 2j current sources to the output node. One of the 2j current sources is not coupled to the output node. The second switch is configured to selectively couple each of the 2j current sources to the current divider. This architecture ensures that the fundamental transform of input code to output current always has a slope that does not change from positive to negative or from negative to positive.

FIELD OF THE INVENTION

This disclosure is directed to circuit design of a digital-to-analog converter (DAC), and, more particularly, to an apparatus and method for ensuring monotonicity in a DAC.

BACKGROUND

A digital-to-analog converter, or DAC, converts a digital input into an analog output signal, such as a current or voltage. The digital input may be, for example, a digital word. There are several conventional architectures used for DACs.

FIG. 1shows the general architecture for a conventional form of a binary-weighted, current-mode, DAC100. Such a DAC includes n binary-weighted current sources101, where n is the number of bits in the DAC100. Each current source101is controlled by a switch102, such as a transmission gate. Hence, in the four-bit example ofFIG. 1, four binary-weighted copies of the least-significant element, represented by the current I0, are added to the output in any combination, under the control of a four-bit digital input word. Thus, the output may vary from 0 to I0×(24−1).

But there is a significant drawback with the architecture100inFIG. 1. That is, any of the weighted sources101can be in error by a particular error factor. Consequently, for certain error factors, the slope of the current-vs-code characteristic could reverse. If the slope changes from positive to negative, or vice versa, then the current-vs-code function is not monotonic. For example, if the 8I0source inFIG. 1is 15% low, then the outputs for codes 7 and 8 will be 7I0and 6.8I0instead of 7I0and 8I0. Since 6.8I0is less than 7I0, then the slope of the function will have decreased whereas the function should have increased to 8I0.

In general, the overall matching requirement for monotonicity is that the error factor must be less than the quotient of the least-significant bit divided by the most-significant bit. Non-monotonicity may cause harmonic distortion in DACs used for analog signals, and it can also defeat other algorithms, such as an algorithm for offset correction. This matching problem limits binary DACs that are like the DAC illustrated inFIG. 1to about eight bits of resolution.

One conventional way of ensuring monotonicity is to utilize a thermometer-coded, current-mode DAC200, such as the four-bit example depicted inFIG. 2. The thermometer-coded, current-mode DAC200includes 2n−1 current sources201, where n is the number of bits in the DAC200. Each current source201is controlled by a switch202, such as a transmission gate. Each current source201provides a current with a value equal to I0, the least-significant bit. Accordingly, and as shown inFIG. 2, a single copy of I0is added to the output for each increase in code. Because none of the copies can be negative, monotonicity is ensured. This solution, however, requires a large amount of overhead, in the form of decoding logic and switching, to control the 2n−1 copies of I0. Thus, like the architecture100ofFIG. 1, DACs with the architecture200ofFIG. 2are also usually limited to 8 bits or less.

A combination of a thermometer-coded architecture with other architectures can be used to relieve the tradeoff between overhead and matching for monotonicity. For example, as shown inFIG. 3, a conventional form of a thermometer-coded, current-mode DAC300may include a divider303for each current source301. Except for the divider for the highest code, each divider303is controlled by two switches302, which may be, for example, transmission gates. The divider for the highest code, code8in the example ofFIG. 3, is controlled by a single switch302or transmission gate.

In the architecture ofFIG. 3, when activated, the leftmost switch in the illustrated pair of switches302for each segment allows the full 2I0current to pass to the output. When activated, the rightmost switch for each segment allows the full 2I0current to pass to the divider. If neither switch is activated in the pair of switches302, essentially none of the 2I0current for that segment passes to the output. Hence, in the four-bit example ofFIG. 3, 2n-1copies of 2I0are controlled by thermometer logic segments. Each copy is followed by a divider303to divide the current by two. Therefore, the output of each segment can be 0, I0, or 2I0by operation of the switches302.

Since the dividers303do not create scaled copies of I0, but only split it into portions, monotonicity is still ensured with this architecture300. Only half of the 2I0unit sources and logic are required as compared to the full thermometer DAC, such as the DAC200ofFIG. 2. Note that the 2I0copy for the highest code, code8in the example ofFIG. 3, is never switched fully to the output in this binary example. Thus, the output of the last segment can be 0 or I0, but not 2I0.

The architecture300ofFIG. 3can be simplified to use a single divider since only one copy of 2I0is treated at a time. Thus, as shown inFIG. 4, a conventional form of a thermometer-coded, current-mode DAC400may include a single divider403that operates on each current source401. Except for the current source for the highest code, each current source401is controlled by two switches402or transmission gates. The current source for the highest code, code8in the example ofFIG. 4, is controlled by a single switch402or transmission gate. The switches operate generally as described above forFIG. 3.

The architectures ofFIGS. 3 and 4, though, suffer from a limited set of possible resolution values, dependent only on the number of bits in the DAC300or the DAC400.

Embodiments of the invention address these and other issues in the prior art.

SUMMARY OF THE DISCLOSURE

Embodiments of the disclosed subject matter provide an apparatus and method for ensuring that the fundamental transform of digital input code to analog output current for a current-mode, digital-to-analog converter (DAC) always has a slope that does not change from positive to negative or from negative to positive. Accordingly, embodiments of the disclosed subject matter ensure monotonicity in the DAC.

Thus, at least some embodiments of a current-mode, digital-to-analog converter (DAC) that is configured to convert a digital word input having j bits to an analog signal may include 2jcurrent sources, an output node, a current divider, a first switch, and a second switch. Each of the 2jcurrent sources is configured to produce a current having a value I0. The current divider has a programmable divide ratio, d, where 1/d is between 0 and 1. The first switch is configured to selectively couple 2j−1 of the 2jcurrent sources to the output node. One of the 2jcurrent sources is not coupled to the output node. The second switch is configured to selectively couple each of the 2j current sources to the current divider.

In another aspect, at least some embodiments of a binary divider circuit having k bits may include a current mirror and a current source. The current mirror has a first transistor and a second transistor. Each transistor has a source, and the source of the first transistor is electrically connected to the source of the second transistor. The first transistor has a programmable gain n, where n is greater than or equal to 1. The second transistor has a programmable gain m, where the sum of n plus m equals 2k, where k is the number of bits in the divider circuit.

In yet another aspect, at least some embodiments of a method of dividing a current with a programmable current mirror having k bits may include coupling a current source, producing a current, I0, to the current mirror. The current mirror has a first transistor and a second transistor. Each transistor has a source, and the source of the first transistor is electrically coupled to the source of the second transistor. The first transistor and the second transistor each has a programmable gain. The method may also include: configuring the programmable gain of the first transistor to a value n, where n is greater than or equal to 1; configuring the programmable gain of the second transistor to a value m, where m=2k−n; and outputting a divided current from the programmable current mirror, the divided current being I0×(m/(n+m)).

In still another aspect, at least some embodiments of a method of dividing a current within a DAC configured to convert a digital word input having j bits to an analog signal may include selectively coupling each of 2jcurrent sources to an input side of a current divider. An output side of the current divider is coupled to an output node of the DAC, and each of the 2jcurrent sources produces a current having a value I0. Also, the current divider has a programmable divide ratio, d, where 1/d is between 0 and 1. The method may further include selectively coupling 2j−1 of the 2jcurrent sources to the output node of the DAC. One of the 2jcurrent sources is not coupled to the output node.

DETAILED DESCRIPTION

As described herein, embodiments of the invention are directed to an architecture for a current-mode, digital-to-analog converter (DAC) that ensures that the fundamental transform of input code to output current always has a slope that does not change from positive to negative or from negative to positive. In other words, if the slope of the transform is positive, the slope will remain greater than or equal to zero as the code increases. Also, if the slope of the transform is negative, the slope will remain less than or equal to zero as the code increases.

Embodiments of the invention may be applied to binary DACs, and examples of this are shown and described, but the invention may also be used with other electronic circuits, including other, non-binary DACs. Additionally, the disclosed architectures may be implemented as one or more integrated circuits.

FIG. 5is a functional diagram showing material portions of an architecture for ensuring monotonicity in a DAC, according to embodiments of the invention. As illustrated inFIG. 5, an architecture500may include 2jthermometer-coded segments504, where j is the number of bits in a digital word input to the DAC for conversion to an analog signal. The architecture500may also include a variable divider503having a programmable divide ratio, 1/d, between 0 and 1. That is, an input to the variable divider503is multiplied by the programmable divide ratio, 1/d, to produce an output of the variable divider503.

Each of the thermometer-coded segments504includes a current source501coupled or connected to ground at a node of the current source501, and each current source501provides a current with a value equal to I0, where I0is the least-significant bit, at another node of the current source501.

Each of the first 2j−1 current sources501is also coupled or connected to a pair of switches502or transmission gates. A first switch of the pair of switches502, such as the leftmost switch in each pair illustrated inFIG. 5, allows current to pass between the respective current source and an output node505of the DAC. A second switch of the pair of switches502allows current to pass between the respective current source and the variable divider503, before passing to the output505of the DAC. As shown inFIG. 5, the 2j-thcurrent source, which is the rightmost current source in the example illustrated inFIG. 5, includes only one switch502or transmission gate, which allows current to pass between the 2j-thcurrent source and the variable divider503. Thus, the 2j-thcurrent source is not connected directly to the output505of the DAC in the configuration illustrated inFIG. 5. As used in this disclosure, “j-th” is intended to mean the ordinal number assigned to an item “j” in a sequence.

Thus, in the architecture ofFIG. 5, when activated the leftmost switch in the pair of switches502for 2j−1 of the segments504allows the I0current to pass to the DAC output505. When activated, the rightmost switch for 2j−1 of the segments504allows the I0current to pass to the divider503, and the output of the divider503passes to the DAC output505. If neither switch502is activated in a segment's pair, essentially none of the I0current for that segment504passes to the DAC output505. For one of the 2jsegments504, when activated the corresponding switch502allows the I0current to pass to the DAC output505through the divider503, and there is no connection directly to the output505of the DAC. In this way, 2j−1 of the segments504may pass either 0, I0, or a portion of I0current to the DAC output505, where the portion depends on the divide ratio of the variable divider503. Likewise, one of the 2jsegments504may pass either 0 or a portion of I0current to the DAC output505.

Thus, the output of the DAC500can vary between 0 and I0((2j−1)+(1/d)max), where (1/d)maxis the maximum divide ratio of the variable divider503. As one example, if the variable divider503is programmed or otherwise set to divide an input current by four, then the divide ratio is 1/4.

Accordingly, a method of dividing current within a DAC500may include selectively connecting each of 2jcurrent sources501to an input side, or node,517of a current divider503, each of the 2jcurrent sources501producing a current having a value I0, and the current divider503having a programmable divide ratio, d, where 1/d is between 0 and 1, an output side518of the current divider503being connected to an output node505of the DAC; and selectively connecting 2j−1 of the 2jcurrent sources501to the output node505of the DAC, in which one of the 2jcurrent sources501is not connected to the output node505. The method may also include iteratively reconfiguring the current divider503to have a programmable divide ratio, dnew, where 1/dnewis between 0 and 1 and dnewdoes not equal d. Once the current divider is reconfigured, the method may include again selectively connecting each of 2jcurrent sources to the input side517of the current divider503; and again selectively connecting 2j−1 of the 2jcurrent sources501to the output node505of the DAC, in which one of the 2jcurrent sources501is not connected to the output node505.

FIG. 6is a functional diagram showing material portions of an architecture600for ensuring monotonicity in a DAC, according to embodiments of the invention. The architecture600ofFIG. 6may be a particular case of the architecture500ofFIG. 5, where the variable divider503ofFIG. 5is binary and has k bits. As noted above, though, the DAC architecture need not be binary in all embodiments.

Thus, as illustrated inFIG. 6, the architecture600may include 2jthermometer-coded segments604, where j is the number of bits in a digital word input to the DAC for conversion to an analog signal. The architecture600may also include a divider603having k bits and a programmable divide ratio. Hence, the DAC600is binary with j+k bits.

Each of the thermometer-coded segments604includes a current source601connected to ground, and each current source601provides a current with a value equal to I0, where I0is the value of the least-significant bit (LSB) multiplied by 2k.

As inFIG. 5, each of the first 2j−1 current sources601ofFIG. 6is also connected to a pair of switches602or transmission gates. A first switch of the pair of switches602, such as the leftmost switch in each pair illustrated inFIG. 6, allows current to pass between the respective current source601and an output605of the DAC. A second switch of the pair of switches602, such as the rightmost switch in each pair illustrated inFIG. 6, allows current to pass between the respective current source601and the programmable divider603, before passing to the output605of the DAC. As shown inFIG. 6, the 2j-thcurrent source, which is the rightmost current source601in the example ofFIG. 6, includes only one switch602or transmission gate, which allows current to pass between the 2j-thcurrent source and the programmable divider603. Thus, the 2j-thcurrent source is not connected directly to the output605of the DAC in the configuration illustrated inFIG. 6.

Thus, in the architecture ofFIG. 6, when activated the leftmost switch in the pair of switches602for 2j−1 of the segments604allows the I0current to pass to the DAC output605. When activated, the rightmost switch for 2j−1 of the segments604allows the I0current to pass to the divider603, and the output of the divider603passes to the DAC output605. If neither switch602is activated in a segment's pair, essentially none of the I0current for that segment604passes to the DAC output605. For one of the 2jsegments604, when activated the corresponding switch602allows the I0current to pass to the DAC output605through the divider603, and there is no connection directly to the output605of the DAC. In this way, 2j−1 of the segments604may pass either 0, I0, or a portion of I0current to the DAC output605, where the portion depends on the divide ratio of the programmable divider603. Likewise, one of the 2jsegments604may pass either 0 or a portion of I0current to the DAC output605.

As noted above, the divider603has k bits and a programmable divide ratio. As shown inFIG. 6, the divide ratio may be m/(n+m), where n is greater than or equal to 1 and m is 2k−n. In other words, the sum n+m is constrained to be equal to 2k. For a binary divider603, n and m are integers. As noted above, though, the DAC need not be binary in all embodiments. Thus, in embodiments where the DAC has a non-binary divider, n and m need not be integers as long as n is greater than or equal to 1 and m is the difference of n subtracted from an arbitrary constant, such as 2k.

Accordingly, a method of dividing current within a DAC600may include selectively connecting each of 2jcurrent sources601to an input side617of a current divider603, each of the 2jcurrent sources601producing a current having a value I0, and the current divider603having a programmable divide ratio m/(n+m), where n is greater than or equal to 1 and m=2k−n, an output side618of the current divider603being connected to an output node605of the DAC; and selectively connecting 2j−1 of the 2jcurrent sources601to the output node605of the DAC, in which one of the 2jcurrent sources601is not connected to the output node605. The method of dividing current within a DAC600may also include reconfiguring the current divider603to have a programmable divide ratio mnew/(nnew+mnew), where nnewis greater than or equal to 1, nnewdoes not equal n, and mnew=2k−nnew. Once the current divider is reconfigured, the method may include again selectively connecting each of 2jcurrent sources601to the input side617of the current divider603; and again selectively connecting 2j−1 of the 2jcurrent sources601to the output node605of the DAC, in which one of the 2jcurrent sources601is not connected to the output node605. The method may further include iteratively reconfiguring the current divider603for a plurality of values of nnewand mnew, and perhaps each value of nnewand mnew, for which mnew+nnew=2k.

Thus, the divided output of each segment604is a fraction of I0from 0 to (2k−1)/2k, and the output605of the DAC600can vary between 0 and LSB(2j+k−1).

FIG. 7is a functional diagram showing material portions of a generalized current divider703, according to embodiments of the invention. The current divider703may be, for example, an implementation of the current divider603ofFIG. 6. As illustrated inFIG. 7, the current divider703may be a binary divider circuit having k bits, although the divider may be non-binary in some embodiments. The current divider703may include a current mirror706and a current source701. The current source701is connected to ground and provides a current with a value of I0.

The current mirror706includes a first transistor707and a second transistor708. As an example, each transistor may be a metal-oxide-semiconductor, field-effect transistor (MOSFET) transistor with a source, a drain, and a gate as illustrated inFIG. 7. Even so, other transistors may be used in some embodiments. The source709of the first transistor707and the source710of the second transistor708are electrically connected together and to the current source701. Thus, neither source is connected directly to ground. The gate711of the first transistor707and the gate712of the second transistor708are connected together and to the drain713of the first transistor707. The first transistor707has a programmable gain n, where n is greater than or equal to 1. The second transistor708has a programmable gain m, where n+m=2k.

Accordingly, the current at the drain714of the second transistor708is (I0×m)/(n+m). To put it another way, the current at the drain714of the second transistor708is a programmable fraction of I0from 0 to (2k−1)/2k. In this way, the current mirror706splits the current I0into portions controlled by the relative size of the first transistor707and the second transistor708.

Accordingly, a method of dividing a current with a programmable current mirror706having k bits may include connecting a current source701, which produces a current, I0, to the current mirror706; configuring a programmable gain of the first transistor707to a value n, where n is greater than or equal to 1; configuring a programmable gain of the second transistor708to a value m, where m=2k−n; and outputting a divided current from the programmable current mirror706, the divided current being I0×(m/(n+m)). The method may also include reconfiguring the programmable gain of the first transistor707to a value nnew, where nnewis greater than or equal to 1 and nnewdoes not equal n; and reconfiguring the programmable gain of the second transistor708to a value mnew, where mnew=2k−nnewand mnewdoes not equal m. Additionally, the method may further include iteratively reconfiguring the programmable gain of the first transistor707and iteratively reconfiguring the programmable gain of the second transistor708, for a plurality of values of nnewand mnew, and perhaps each value of nnewand mnew, for which mnew+nnew=2k.

FIG. 8is a functional diagram showing material portions of an architecture800for ensuring monotonicity in a DAC, according to embodiments of the invention. The architecture800combines a current divider, such as the current divider703ofFIG. 7, with a thermometer-coded, DAC, such as the DAC600ofFIG. 6. As illustrated inFIG. 8, the architecture800may include 2jthermometer-coded segments804, where j is the number of bits in a digital word input to the DAC for conversion to an analog signal. The architecture800may also include a current divider803having k bits and a programmable divide ratio. Hence, the DAC800is binary with j+k bits.

Each of the thermometer-coded segments804includes a current source801connected to ground, and each current source801provides a current with a value equal to I0, where I0is the value of the least-significant bit (LSB) multiplied by 2k.

As inFIG. 6, each of the first 2j−1 current sources801ofFIG. 8is also connected to a pair of switches802or transmission gates. A first switch of the pair of switches802, such as the leftmost switch in each pair illustrated inFIG. 8, allows current to pass between the respective current source801and an output805of the DAC. A second switch of the pair of switches802, such as the rightmost switch in each pair illustrated inFIG. 8, allows current to pass between the respective current source801and the current divider803, before passing to the output805of the DAC. As shown inFIG. 8, the 2j-thcurrent source, which is the rightmost current source801in the example ofFIG. 6, includes only one switch802or transmission gate, which allows current to pass between the 2j-thcurrent source and the current divider803. Thus, the 2j-thcurrent source801is not connected directly to the output805of the DAC in the configuration illustrated inFIG. 8.

Consequently, in the architecture ofFIG. 8, when activated the leftmost switch in the pair of switches802for 2j−1 of the segments804allows the I0current to pass to the DAC output805. When activated, the rightmost switch for 2j−1 of the segments804allows the I0current to pass to the current divider803, and the output of the current divider803passes to the DAC output805. If neither switch802is activated in a segment's pair, essentially none of the I0current for that segment passes to the DAC output805. For one of the 2jsegments804, when activated the corresponding switch802allows the I0current to pass to the DAC output805through the current divider803, and there is no connection directly to the output805of the DAC. In this way, 2j−1 of the segments804may pass either 0, I0, or a portion of I0current to the DAC output805, where the portion depends on the divide ratio of the current divider803. Likewise, one of the 2jsegments804may pass either 0 or a portion of I0current to the DAC output805.

The current divider803may include a current mirror806. As with the current mirror806ofFIG. 7, the current mirror806may include a first transistor807and a second transistor808. Each transistor may be a metal-oxide-semiconductor, field-effect transistor (MOSFET) transistor with a source, a drain, and a gate. The source809of the first transistor807and the source810of the second transistor808are connected together and to the current source801. The gate811of the first transistor807and the gate812of the second transistor808are connected together and to the drain813of the first transistor807. The first transistor807has a programmable gain n, where n is greater than or equal to 1. The second transistor808has a programmable gain m, where n+m=2k. The drain813of the first transistor807may be connected to a power supply, Vdd,815, and the connection may be through a third transistor816as illustrated inFIG. 8. Hence, a first, unused portion of I0is shunted to the power supply815while a second, used portion of I0is added to the DAC output805.

Accordingly, the current at the drain814of the second transistor808is (I0×m)/(n+m). In other words, the current at the drain814of the second transistor808is a programmable fraction of I0from 0 to (2k−1)/2k. In this way, the current mirror806splits the current I0into two portions controlled by the relative gains of the first transistor807and the second transistor808. The DAC is guaranteed to be monotonic because I0is being split, but not scaled and copied, by the architecture800.

Accordingly, a method of dividing a current within a DAC800may include selectively connecting each of 2jcurrent sources801to an input side817of a current divider803, the current divider803including a first transistor807having a programmable gain of n, where n is greater than or equal to 1, and a second transistor808having a programmable gain of m, where m=2k−n, an output side818of the current divider803being connected to an output node805of the DAC, each of the 2jcurrent sources801producing a current having a value I0, the current divider803having a programmable divide ratio, d, where 1/d is between 0 and 1; selectively connecting 2j−1 of the 2jcurrent sources801to the output node805of the DAC, in which one of the 2jcurrent sources801is not connected to the output node805; and outputting a divided current from the current divider803, the divided current being I0×(m/(n+m)). The method of dividing a current within a DAC800may also include reconfiguring the programmable gain of the first transistor807to a value nnew, where nnewis greater than or equal to 1 and nnewdoes not equal n; reconfiguring the programmable gain of the second transistor808to a value mnew, where mnew=2k−nnewand mnewdoes not equal m; and outputting a new divided current from the current divider803, the new divided current being I0×(mnew/(nnew+mnew)). Additionally, the method may further include iteratively reconfiguring the programmable gain of the first transistor807and iteratively reconfiguring the programmable gain of the second transistor808, for a plurality of values of nnewand mnew, and perhaps each value of nnewand mnew, for which mnew+nnew=2k.

The previously described versions of the disclosed subject matter have many advantages that were either described or would be apparent to a person of ordinary skill. Even so, all of these advantages or features are not required in all versions of the disclosed apparatus, systems, or methods.

Additionally, this written description makes reference to particular features. It is to be understood that the disclosure in this specification includes all possible combinations of those particular features. For example, where a particular feature is disclosed in the context of a particular aspect or embodiment, that feature can also be used, to the extent possible, in the context of other aspects and embodiments.

Furthermore, the term “comprises” and its grammatical equivalents are used in this disclosure to mean that other components, features, steps, processes, operations, etc. are optionally present. For example, an article “comprising” or “which comprises” components A, B, and C can contain only components A, B, and C, or it can contain components A, B, and C along with one or more other components.

Also, directions such as “right” and “left” are used for convenience and in reference to the diagrams provided in figures. But the disclosed subject matter may have a number of orientations in actual use or in different implementations. Thus, a feature that is vertical, horizontal, to the right, or to the left in the figures may not have that same orientation or direction in all implementations.

Although specific embodiments of the invention have been illustrated and described for purposes of illustration, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited except as by the appended claims.