Shift register circuit

A shift register circuit includes a plurality of bit register units, coupled in series, for transferring an input signal among the plurality of bit register units to sequentially output the input signal to a plurality of data output terminals according to a control signal and a clock signal, wherein the number of the plurality of data output terminals is greater than that of the plurality of bit register units, and a control unit for generating the control signal to control transference of the input signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a shift register circuit, and more particularly, to a shift register circuit capable of cyclically using flip-flops for saving the number of flip-flops that need to be used.

2. Description of the Prior Art

In digital circuits, a shift register, which generally includes a plurality of series connected flip-flops, is a widely used logic circuit unit, and can perform operations such as data registering, delay or conversion of serial and parallel output for input binary data. For example, when applied in liquid crystal display (LCD) driver circuits, the shift registers are utilized for sequentially providing pulse signals to a plurality of data output terminals according to a clock signal, such that data driving signals or gate driving signals can be outputted line-by-line for driving corresponding pixels.

Please refer toFIG. 1andFIG. 2.FIG. 1andFIG. 2are functional block diagrams of a source driver circuit10and a gate driver circuit20of a conventional LCD, respectively. The source driver circuit10includes a shift register110, a sampling control circuit120and an output buffer130. The gate driver circuit20includes a shift register210and an output buffer230. In the source driver circuit10, the shift register110is utilized for sequentially outputting pulse signals L1˜Ln to the sampling control circuit120for enabling latch circuits inside the sampling control circuit120(not shown inFIG. 1) according to an input pulse signal DIN1and a clock signal CLK, so that video data RGB_Data can be sampled accordingly. Then, the output buffer130can output the data driving signals to data lines D1˜Dn according to sampled voltages of the video data RGB_Data. Similarly, in the gate driver circuit20, the shift register210is utilized for sequentially providing pulse signals to the output buffer230for outputting the gate driving signals to scan lines S1˜Sn according to an input pulse signal DIN2and a clock signal CLK2. Detailed operations of the LCD driver circuits are well known by those skilled in the art, and thus not described herein.

Please refer toFIG. 3.FIG. 3is a schematic diagram of a conventional shift register30. The shift register30can be the shift register110inFIG. 1or the shift register210inFIG. 2, and includes series-coupled flip-flops FF1˜FFn and data output terminals OP1˜OPn. Each of the flip-flops FF1˜FFn further includes an input terminal D, an output terminal Q and a clock input terminal C, and is utilized for shifting a logic level received by the input terminal D to the output terminal Q according to a clock signal CLK received by the clock input terminal C. In general, the output terminal of each flip-flop is coupled to the input terminal of a next stage flip-flop and a corresponding data output terminal. Thus, when an input signal DIN is inputted to the input terminal of the first flip-flop FF1, the shift register circuit30then forward transfers a logic level of the input signal DIN stage-by-stage according to the clock signal CLK to output pulse signals to the data output terminals OP1˜Opn in order. As for the related signal sequence, please refer toFIG. 4.

Please further refer toFIG. 5.FIG. 5is a schematic diagram of another conventional shift register40. In the shift register40, the input terminal of each flip-flop is further coupled to an input switch unit SW. The input switch unit SW includes a first switch SW1and a second switch SW2, and is utilized for controlling the first switch SW1and the second switch SW2to couple the input terminal of each flip-flop to an output terminal of a former stage flip-flop or that of a next stage flip-flop according to a direction control signal UD, so as to enhance flexibility when using the shift register40. For example, the input switch unit SW can short the first switch SW1for coupling the input terminal of each flip-flop to the output terminal of a former stage flip-flop according to a low logic level of the direction control signal UD; and can short the second switch SW2for coupling the input terminal of each flip-flop to the output terminal of a next stage flip-flop according to a high logic level of the direction control signal UD. In this case, when the input terminal of each flip-flop is coupled to the output terminal of a next stage flip-flop, the shift register40can then backward transfer the input signal UIN received by the input terminal of each flip-flop stage-by-stage according to the clock signal CLK, for outputting pulse signals to corresponding data output terminals OP1˜OPn in reverse order. As for the related signal sequence, please refer toFIG. 6.

Therefore, utilizing the input switch unit SW, the shift register40can switch the first switch SW1and the second switch SW2for forward or backward transferring the input signal according to the direction control signal UD, so as to output the pulse signals to the data output terminals OP1˜OPn in order or in reverse order. However, no matter how the input signal is transferred, each data output terminal needs one flip-flop for generating the pulse signal, and thus the number of the flip-flops has to be equal to that of the data output terminals. In some applications such as the gate driver circuits or the source driver circuits of the LCD, the shift register has to be used for transferring signals and sequentially outputting the signals to hundreds of data output terminals in order. In this case, hundreds of flip-flops are needed to realize the shift register. In fact, when the input signal is transferred in the shift register, only one or a few flip-flops are in operation (i.e. generating pulse signals) at the same time, but the remaining flip-flops are on standby. Thus, such shift registers waste circuit area and production cost.

SUMMARY OF THE INVENTION

It is therefore a primary objective of the present invention to provide a shift register circuit.

The present invention discloses a shift register circuit. The shift register circuit includes a plurality of bit register units, coupled in series, for transferring an input signal among the plurality of bit register units to sequentially output the input signal to a plurality of data output terminals according to a control signal and a clock signal. The number of the plurality of data output terminals is greater than that of the plurality of bit register units. The shift register circuit further comprises a control unit coupled to the plurality of bit register units for generating the control signal to control transference of the input signal.

DETAILED DESCRIPTION

Please refer toFIG. 7.FIG. 7is a functional block diagram of a shift register50of the present invention. The shift register50includes bit register units RG1˜RGn, data output terminals OP1˜OPm and a control unit51. The bit register units RG1˜RGn are connected in series through a bus line52, and are utilized for transferring an input signal DIN among the bit register units RG1˜RGn to sequentially output the input signal to the data output terminals OP1˜OPm according to a control signal CTRL and a clock signal CLK carried on the bus line52, among which the number of the data output terminals OP1˜OPm is greater than that of the bit register units RG1˜RGn. The control unit51is utilized for generating the control signal CTRL to the bus line52for controlling the input signal DIN transferring among the bit register unit RG1˜RGn. Preferably, each of the bit register units RG1˜RGn includes a flip-flop FF, an input terminal switch unit IN_SW, and an output terminal switch unit OUT_SW. The flip-flop FF includes an input terminal D, a clock input terminal C and an output terminal Q. The input terminal switch unit IN_SW is coupled to the input terminal of the flip-flop FF, and is utilized for switching the input terminal of the flip-flop FF to couple to the output terminal of another flip-flop according to the control signal CTRL. The output terminal switch unit OUT_SW is coupled to the output terminal of the flip-flop FF, and is utilized for switching the output terminal of the flip-flop FF to couple to one of the data output terminals OP1˜OPm according to the control signal CTRL.

Therefore, in the shift register50of the present invention, the input terminal of the flip-flop can be coupled to the output terminal of a flip-flop in any stage by the input terminal switch unit IN_SW, and the output terminal of the flip-flop can be coupled to any one of the data output terminals OP1˜OPm by the output terminal switch unit OUT_SW. In this case, the shift register50of the present invention can control the input signal repeatedly transferring among the bit register units RG1˜RGn, and can sequentially output pulse signals generated by the flip-flops to the data output terminals OP1˜Opm, so that the number of flip-flops that need to be used in the shift register can be reduced significantly, and further, circuit area and production cost can be saved.

For example, please refer toFIG. 8.FIG. 8is a schematic diagram of a shift register60according to an embodiment of the present invention. The shift register60is a shift register with ten data output terminals designed according to the shift register50, and includes bit register units RG1˜RG6, data output terminals OP1˜OP10and a control unit61. In the shift register60, each of the input terminal switch units IN_SW includes a first switch SW1and a second switch SW2, and is utilized for switching the input terminal of each flip-flop to couple to the output terminal of a former stage flip-flop or that of a next stage flip-flop according to a logic level of the control signal CTRL. Each of the output terminal switch units OUT_SW in the bit register units RG1˜RG4includes a third switch SW3and a fourth switch SW4, and is utilized for switching the output terminal QNof the Nthflip-flop to couple to the Nthdata output terminal OPNor the (11−N)thdata output terminal OP(11-N)according to the logic level of the control signal CTRL. Preferably, when the logic level of the control signal CTRL is low, the input terminal switch unit IN_SW shorts the first switch SW1to couple the input terminal of each flip-flop to the output terminal of a former stage flip-flop, and meanwhile, the output terminal switch unit OUT_SW shorts the third switch SW3to couple the output terminal QNof the Nthflip-flop to the Nthdata output terminal OPN. On the other hand, when the logic level of the control signal CTRL is high, the input terminal switch unit IN_SW then shorts the second switch SW2to couple the input terminal of each flip-flop to the output terminal of a next stage flip-flop, and meanwhile, the output terminal switch unit OUT_SW shorts the fourth switch SW4to couple the output terminal of the Nthflip-flop to the (11−N)thdata output terminal OP(11−N). Besides, the control unit61converts the logic level of the control signal CTRL when a pulse signal output by the last bit register unit of the shift register60(i.e. the bit register unit RG6) or a reset signal RST is received.

Therefore, when an input signal DIN is received, the shift register60can utilize the flip-flops FF1˜FF6for forward transferring the input signal DIN according to the clock signal CLK and the low logic level of the control signal CTRL, and can thus forward output pulse signals to the data output terminals OP1˜OP6in order. When the input signal DIN is transferred to the last bit register unit (i.e. the bit register unit RG6), the control unit61then converts the logic level of the control signal CTRL to be high according to the pulse signal outputted by the flip-flop FF6, and the input signal DIN is transferred back to the input terminal of the flip-flop FF4at the same time. Thus, the shift register60can utilize the flip-flops FF4˜FF1for backward transferring the input signal DIN according to the clock signal CLK and the high logic level of the control signal CTRL, and can output pulse signals to the data output terminals OP7˜OP10in order. Please refer toFIG. 9andFIG. 10, which illustrate signal paths of the input signal DIN forward and backward transferring in the shift register60, respectively. As for the related signal sequence of the shift register60, please refer toFIG. 1.

In other words, by properly switching the switches inside the input terminal switch unit IN_SW and the output terminal switch unit OUT_SW according to the control signal CTRL, the embodiment of the present invention can control the input signal to transfer back and forth among the bit register units RG1˜RG6, and can forward output the pulse signals to the data output terminals OP1˜OP10in order. Therefore, in the present invention, a small amount of flip-flops can be used cyclically to achieve output of pulse signals to a large number of data output terminals, so as to save circuit area significantly. For example, in the embodiment, six flip-flops are used for realizing a shift register with ten data output terminals.

Please note that the above-mentioned embodiment is merely an exemplary illustration of the present invention but not a limitation of the present invention, and those skilled in the art can certainly make appropriate modifications according to practical demands. Please further refer toFIG. 12.FIG. 12is a shift register70according to another embodiment of the present invention. The shift register70is similar to the shift register60, and the allocation of switches inside the input terminal switch unit IN_SW and the output terminal switch unit OUT_SW of each bit register unit is as shown inFIG. 12. Compared with the shift register60, when the logic level of the control signal CTRL is high in the embodiment, the input terminal switch unit IN_SW shorts the first switch SW1to couple the input terminal of each flip-flop to the output terminal of a former stage flip-flop, and meanwhile, the output terminal switch unit OUT_SW shorts the fourth switch SW4to couple the output terminal of the Nthflip-flop to the (11-N)thdata output terminal OP(11−N). On the other hand, when the logic level of the control signal CTRL is low, the input terminal switch unit IN_SW shorts the second switch SW2to couple the input terminal of each flip-flop to the output terminal of a next stage flip-flop, and meanwhile, the output terminal switch unit OUT_SW shorts the third switch SW3to couple the output terminal of the Nthflip-flop to the Nthdata output terminal OPN.

Thus, when an input signal DIN is received, the shift register70can utilize the flip-flops FF1˜FF4for forward transferring the input signal DIN according to the clock signal CLK and the high logic level of the control signal CTRL, and can thus sequentially output pulse signals to the data output terminals OP1˜OP7in reverse order. When the input signal DIN is transferred to the bit register unit RG4, the pulse signal outputted from the output terminal of the flip-flop FF4is then received by the input terminal of the flip-flop FF6, and is outputted to the data output terminal OP6on a next clock cycle. Meanwhile, the control unit71converts the logic level of the control signal CTRL to be low according to the pulse signal outputted by the flip-flop FF6, and transfers the input signal DIN back to the input terminal of the flip-flop FF5at the same time. Then, the shift register70can utilize the flip-flops FF5˜FF1for backward transferring the input signal DIN according to the clock signal CLK and the low logic level of the control signal CTRL, and can sequentially output pulse signals to the data output terminals OP5˜OP1in reverse order. Please refer toFIG. 13andFIG. 14, which illustrate signal paths of the input signal DIN forward and backward transferring in the shift register70, respectively. As for the related signal sequence of the shift register70, please refer toFIG. 15.

Therefore, by properly switching the switches inside the input terminal switch unit IN_SW and the output terminal switch unit OUT_SW, the present invention not only can forward provide the pulse signals to the data output terminals OP1˜OP10in order, but can also output the pulse signals to the data output terminals OP10˜OP1in reverse order, so as to enhance flexibility of use. Certainly, those skilled in the art can appropriately combine the shift register60and the shift register70to provide functions of outputting pulse signals in both directions, which also belongs to the scope of the present invention.

Please refer toFIG. 16.FIG. 16is a schematic diagram of a shift register80according to an embodiment of the present invention. The shift register80is another shift register with ten data output terminals designed according to the shift register50, and includes bit register units RG1˜RG5, data output terminals OP1˜OP10, and a control unit81. The allocation of switches inside the input terminal switch unit IN_SW and the output terminal switch unit OUT_SW of each bit register unit is as shown inFIG. 16, and not narrated herein. Preferably, if the shift register80is about to forward output the pulse signals, the input terminal switch unit IN_SW switches the input terminal of each flip-flop to couple to the output terminal of a former stage flip-flop for forward transferring the input signal DIN, and the output terminal switch unit OUT_SW switches the output terminal QNof the Nthflip-flop to couple to the Nthdata output terminal OPNor the (N+T/2)thdata output terminal OP(N+T/2)according to a low logic level or a high logic level of the control signal CTRL, where T is the number of the data output terminals. Thus, when the input signal DIN is received, the shift register80can utilize the flip-flops FF1˜FF5to forward transfer the input signal DIN according to the clock signal CLK and the low logic level of the control signal CTRL, and can forward output pulse signals to the data output terminals OP1˜OP5in order. Then, the control unit81converts the logic level of the control signal CTRL to be high according to the pulse signal outputted by the flip-flop FF5, and the input signal DIN is retransferred to the input terminal of the flip-flop FF1at the same time. Thus, the shift register80can utilize the flip-flops FF1FF5again to forward transfer the input signal DIN according to the clock signal CLK and the high logic level of the control signal CTRL, and can forward output pulse signals to the data output terminals OP6˜OP10in order. As for the related signal sequences of the shift register80, please refer toFIG. 17.

In like manner, if the shift register80is operated for backward outputting the pulse signals, i.e. in reverse order, when an input signal UIN is received by the bit register unit RG5of the shift register80, the shift register80first utilizes the flip-flops FF5˜FF1for backward transferring the input signal UIN and sequentially outputting the pulse signals to the data output terminals OP10˜OP6in reverse order. Then, the control unit81converts the logic level of the control signal CTRL according to the pulse signal outputted by the flip-flop FF1, and retransfers the input signal UIN to the input terminal of the flip-flop FF5. Thus, the shift register80can utilize the flip-flops FF5˜FF1again for backward transferring the input signal UIN and sequentially outputting to the data output terminals OP5˜OP1correspondingly. Therefore, compared with the shift register60and the shift register70that transfer the input signal back and forth, the shift register80retransfers the input signal from an initial bit register unit again when the input signal is transferred to the last bit register unit, which is also capable of saving the number of the flip-flops.

In addition, in some applications such as driver circuits of the LCD, the shift register circuit sometimes needs to transfer two consecutive input signals. Please refer toFIG. 18.FIG. 18is a schematic diagram of a shift register90according to another embodiment of the present invention. The shift register90is utilized for transferring two consecutive input signals, and includes bit register units RG1˜RG7, data output terminals OP1˜OP10and a control unit91. The allocation of switches inside the input terminal switch unit IN_SW and the output terminal switch unit OUT_SW of each bit register unit is as shown inFIG. 18, and not narrated herein. In this case, seven flip-flops are needed to realize the shift register90, and operation of the shift register90is similar to that of the shift register60. First, the shift register90utilizes the flip-flops FF1˜FF7to forward transfer the input signal DIN, and forward outputs the two consecutive signals to the corresponding data output terminals OP1˜OP7in order. Then, the control unit91converts the logic level of the control signal CTRL to be high according to the pulse signal outputted by the flip-flop FF7, and transfers the pulse signal outputted by the flip-flop FF7to the input terminal of the flip-flop FF3. Thus, the shift register90can then utilize the flip-flops FF3˜FF1to backward transfer the input signal DIN, and forward output to the corresponding data output terminals OP8˜OP10in order. Moreover, when finishing transferring the input signal DIN in the shift register90, the control unit91can convert the logic level of the control signal CTRL again according to a reset signal RST to wait for a next signal transfer operation. As for the related signal sequence of the shift register90, please refer toFIG. 19.

As mentioned above, by utilizing the input terminal switch unit and the output terminal switch unit, the shift register of the present invention can control transfer of the input signal among the bit register units for forward or backward outputting the pulse signals to the data output terminals in order. Therefore, by way of cyclically using the flip-flops, the present invention can significantly save the number of flip-flops that need to used when transferring pulse signals to a large amount of data output terminals, so that circuit area and production cost can be saved as well.