Semiconductor circuits

A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35U.S.C. §119 to Korean Patent Application No. 10-2015-0123748 filed on Sep. 1, 2015 in the Korean Intellectual Property Office, and to Korean Patent Application No. 10-2016-0003181 filed on Jan. 11, 2016 in the Korean Intellectual Property Office, the entire contents of each of which are incorporated herein by reference.

BACKGROUND

Field

Example embodiments relate to semiconductor circuits.

Description of the Related Art

With recent trends toward microfabrication, an increased number of logic circuits are being integrated into a single chip. Accordingly, a unit cell area size of the chip may directly affect the integration level of chips. In addition, the performance of a flip-flop configured to transfer data in a digital system according to clock signals may he directly linked with system performance. Accordingly, implementing relatively high-speed flip-flops may be necessary to implement relatively high-speed systems. However, implementing conventional high-speed flip-flops may increase an area of the flip-flop.

SUMMARY

At least some example embodiments of inventive concepts provide semiconductor circuits having reduced setup time and/or including relatively high performance circuits capable of reducing a data output time.

At least one example embodiment provides a semiconductor circuit comprising: a first circuit configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and a second circuit configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the voltage level of the clock signal is at a first level, the first node and the second node have different logical levels. When the voltage level of the clock signal is at a second level, the first node and the second node have the same logical level. The second level is different from the first level.

According to at least some example embodiments, the second circuit may include: a first pull-up transistor connected to the second node, the first pull-up transistor having a gate configured to receive the inverted value of the voltage level at the first node; and a second pull-up transistor connected to the second node in parallel with the first pull-up transistor, the second pull-up transistor having a gate configured to receive the clock signal.

The second circuit further may include: a first pull-down transistor connected to the second node, the first pull-down transistor having a gate configured to receive the inverted value of the voltage level at the second node; and a second pull-down transistor connected to the second node, the second pull-down transistor having a gate configured to receive the input data.

The second circuit may include: a first gate configured to perform an OR operation between the input data and the inverted value of the voltage level at the second node; and a second gate configured to perform a NAND operation between an output of the first gate, the inverted value of the voltage level at the first node, and the clock signal, the second gate being further configured to output a result of the NAND operation to the second node.

The second circuit may include: a first gate configured to perform an OR operation between an enable signal and the inverted value of the voltage level at the second node; and a second gate configured to perform a NAND operation between an output of the first gate, the inverted value of the voltage level at the first node, and the clock signal, the second gate further configured to output a result of the NAND operation to the second node.

The first circuit may include: a first transistor connected to the first node, the first transistor having a gate configured to receive an inverted value of the voltage level of the clock signal, the first transistor being a pull-up transistor; and a second transistor connected between the first node and a ground voltage, the second transistor having a gate configured to receive the inverted value of the voltage level of the clock signal, and configured to transfer the ground voltage to the first node.

The first circuit may further include: a third transistor connected in parallel with the first transistor, the third transistor having a gate configured to receive the voltage level at the first node, and to output the inverted value of the voltage level at the first node; and a fourth transistor connected to the third transistor in series, the fourth transistor having a gate configured to receive the voltage level at the first node, and to output the inverted value of the voltage level at the first node.

The first circuit may further include: a first inverter configured to invert the voltage level at the first node to output the inverted value of the voltage level at the first node.

The first circuit may include: a first gate configured to perform an OR operation between an inverted value of the input data and the voltage level at the first node; and a second gate configured to perform an AND operation between the output of the first gate and the voltage level of the clock signal, the second gate further configured to output a result of the AND operation to the first node.

The first circuit may further include: a third gate configured to perform a NAND operation between the clock signal and the voltage level at the second node, the third gate further configured to output an inverted value of the voltage level of the clock signal.

The first circuit may include: a first gate configured to perform an OR operation between an inverted value of an enable signal and the voltage level at the first node; and a second gate configured to perform an AND operation between an output of the first gate and the clock signal, the second gate further configured to output a result of the AND operation to the first node.

The semiconductor circuit may further include a latch circuit configured to determine a voltage level of an output terminal based on the voltage level of the clock signal and the voltage level at the second node.

The first level may be a logical low level and the second level may be a logical high level.

At least one other example embodiment provides a semiconductor circuit comprising: a first circuit configured to determine a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; a second circuit configured to determine the voltage level at the second node based on the voltage level of the input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node; and a latch circuit configured to determine a voltage level of an output terminal based on the voltage level of the clock signal and the voltage level at the second node; wherein when the voltage level of the clock signal is at a first level, the first node is at the first voltage level and the second node is at a second voltage level, and the voltage level of the second node is transferred to the output terminal, and the second voltage level is different from the first voltage level.

The latch circuit may be configured to change the voltage level of the output terminal at a positive edge of the voltage level of the clock signal. The first voltage level may be a logical low level.

The second circuit may be further configured to pre-charge the second node when the clock signal is at the first voltage level. The first circuit may be further configured to discharge the first node when the clock signal is at the first voltage level.

When the voltage level of the clock signal transitions from the first voltage level to the second voltage level, the semiconductor circuit may be configured to change a voltage level at one of the first node and the second node while maintaining the voltage level at the other of the first node and the second node.

At least one other example embodiment provides a semiconductor circuit comprising a first circuit and a second circuit. The first circuit includes: a first transistor having a gate configured to receive inverted value of a voltage level of a clock signal, the first transistor configured to pull up a first node; a second transistor connected between the first node and a ground voltage, the second transistor having a gate configured to receive the inverted value of the voltage level of the clock signal, and to transfer the ground voltage to the first node; a third transistor connected in parallel with the first transistor, the third transistor having a gate configured to receive the voltage level at the first node, and to output an inverted value of the voltage level at the first node; and a fourth transistor connected to the third transistor in series, the fourth transistor having a gate configured to receive the voltage level at the first node, and to output the inverted value of the voltage level at the first node. The second circuit includes: a fifth transistor having a gate configured to receive the inverted value of the voltage level at the first node, and the fifth transistor configured to pull up the second node; a sixth transistor connected in parallel with the fifth transistor, the sixth transistor having a gate configured to receive the a clock signal, and the sixth transistor configured to pull up the second node; a seventh transistor having a gate configured to receive the voltage level at the second node, the seventh transistor configured to pull down a third node; and an eighth transistor having a gate configured to receive input data, the eighth transistor configured to pull down the third node.

The third transistor and the fourth transistor may be configured as an inverter, which inverts the voltage level at the first node to output the inverted value of the voltage level at the first node.

The second circuit may further include: a ninth transistor connected to the third node, the ninth transistor having a gate configured to receive the inverted value of the voltage level at the first node, the ninth transistor configured to pull down the third node; and a tenth transistor connected in series with the ninth transistor, the tenth transistor having a gate configured to receive the clock signal, the tenth transistor configured to pull down the third node.

The semiconductor circuit may further include a latch circuit configured to determine a voltage level of an output terminal based on the voltage level of the clock signal and the voltage level of the input data.

At least one other example embodiment provides a semiconductor circuit, comprising: a first circuit configured to output a first output signal based on input data, a clock signal, a second output signal, and an inverted version of the first output signal; and a second circuit configured to output the second output signal based on the input data, an inverted version of the first output signal, the clock signal, and an inverted version of the second output signal; wherein the second circuit is further configured to output the second output signal having a logic level different from a logic level of the first output signal in response to the clock signal having a first logic level, and the second circuit is further configured to output the second output signal having a same logic level as the first output signal in response to the clock signal having a second logic level.

The semiconductor circuit may further include a latch circuit having an input terminal configured to receive the second output signal from the second circuit.

The semiconductor circuit may further include a multiplexer configured to input the input data to the first and second circuits.

The first circuit may include: a NAND gate configured to output a NAND gate output signal based on the clock signal and the second output signal; an OR gate configured to output an OR gate output signal based on the first output signal and an inverted version of the input data; an AND gate configured to generate the first output signal based on the NAND gate output signal and the OR gate output signal; and an inverter configured invert the first output signal to generate the inverted first output signal.

The second circuit may include: an inverter configured to invert the second output signal to generate the inverted version of the second output signal; an OR gate configured to generate an OR gate output signal based on the input data and the inverted version of the second output signal; and a NAND gate configured to generate the second output signal based on the clock signal, the inverted version of the first output signal, and the OR gate output signal.

DETAILED DESCRIPTION

Inventive concepts will become more readily understood by reference to the following detailed description of example embodiments and the accompanying drawings. Inventive concepts may, however, be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will fully convey concept of the inventive concepts to those skilled in the art, and the inventive concepts will only be defined by the appended claims, Like reference numerals refer to like elements throughout the specification.

In the following description, illustrative embodiments may be described with reference to acts and symbolic representations of operations (e.g., in the form of flow charts, flow diagrams, data flow diagrams, structure diagrams, block diagrams, etc.) that may be implemented as program modules or functional processes including routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types. The operations may be implemented using existing hardware in existing electronic systems (e.g., display drivers, System-on-Chip (SoC) devices, SoC systems, electronic devices, such as personal digital assistants (PDAs), smartphones, tablet personal computers (PCs), laptop computers, etc.). Such existing hardware may include one or more Central Processing Units (CPUs), digital signal processors (DSPs), application-specific-integrated-circuits (ASICs), SoCs, field programmable gate arrays (FPGAs'), computers, or the like.

Further, one or more example embodiments (e.g., controller1110) may be (or include) hardware, firmware, hardware executing software, or any combination thereof. Such hardware may include one or more CPUs, SoCs, DSPs, ASICs, FPGAs, computers, or the like, configured as special purpose machines to perform the functions described herein as well as any other well-known functions of these elements. In at least some cases, CPUs, SoCs, DSPs, ASICs and FPGAs may generally be referred to as processing circuits, processors and/or microprocessors.

As disclosed herein, the term “storage medium”, “computer readable storage medium” or “non-transitory computer readable storage medium,” may represent one or more devices for storing data, including read only memory (ROM), random access memory (RAM), magnetic RAM, core memory, magnetic disk storage mediums, optical storage mediums, flash memory devices and/or other tangible machine readable mediums for storing information. The term “computer-readable medium” may include, but is not limited to, portable or fixed storage devices, optical storage devices, and various other mediums capable of storing, containing or carrying instruction(s) and/or data.

A code segment may represent a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters or memory contents, Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

FIG. 1is a block diagram of a semiconductor circuit according to some example embodiments of inventive concepts,FIG. 2is a circuit diagram of the semiconductor circuit shown inFIG. 1, andFIG. 3is a timing diagram for explaining example operation of the semiconductor circuit shown inFIGS. 1 and 2.

Referring toFIGS. 1 and 2, the semiconductor circuit according to some example embodiments of inventive concepts includes a first circuit100, a second circuit200, and a latch circuit300.

The first circuit100may determine a voltage level of a first node NET1based on a voltage level of input data D, a voltage level inverted to the voltage level of the first node NET1, a voltage level of a clock signal CLK, and a voltage level of a second node NET2.

The second circuit200may determine the voltage level of the second node NET2based on the voltage level of input data D, a voltage level inverted to the voltage level of the second node NET2, the voltage level of the clock signal CLK, and a voltage level inverted to the voltage level of the first node NET1.

The latch circuit300may determine a voltage level of an output terminal QN based on the voltage level of the clock signal CLK and the voltage level of the second node NET2.

In this example, some of outputs of the first circuit100may be used as inputs of the second circuit200, and some of outputs of the second circuit200may he used as inputs of the first circuit100. The first circuit100, the second circuit200, and the latch circuit300may function as flip-flops. However, aspects of one or more example embodiments are not limited thereto.

In more detail, the second circuit200may include a first gate G1performing an OR operation between the voltage level of input data D and an inverted value of the voltage level of the second node NET2. The inverted value of the voltage level of the second node NET2may he transferred as an input value of the first gate G1by a second inverter IN2.

In addition, the second circuit200may include a second gate G2performing a NAND operation between a voltage level of an output of the first gate G1, an inverted value of the voltage level of the first node NET1, and the voltage level of the clock signal CLK. The second gate G2transfers an output value of the NAND operation to the second node NET2.

The first circuit100may include a third gate G3performing an OR operation between the voltage level of input data D and the voltage level of the first node NET1. The third gate G3outputs the output value of the OR operation to a fourth gate G4. The first circuit100may include an inverter IN1that inverts the voltage level of the first node NET1, and outputs the inverted value of the voltage level of the first node NET1to the third gate G3as well as the second gate02,

In addition, the first circuit100may include a fourth gate G4performing an AND operation between a voltage level of an output of the third gate G3and an inverted value of the inverted voltage level CKB of the clock signal UK. The fourth gate G4outputs an output value of the AND operation to the first node NET1. The first circuit100may include a fifth gate G5performing a NAND operation between the voltage level of the clock signal CLK and the voltage level of the second node NET2and outputting the inverted value CKB of the voltage level of the clock signal CLK, The inverted value CKB of the voltage level of the clock signal CLK, which is the output value of the fifth gate G5, may be inverted and then provided as an input value of the fourth gate G4.

Example operations of the first circuit100and the second circuit200will now be described in more detail.

The output value of the first circuit100is provided as an input value of the second circuit200, and the output value of the second circuit200is provided as an input value of the first circuit100. Accordingly, the first circuit100and the second circuit200perform operations similar to those of an SR latch circuit. In addition, the first circuit100and the second circuit200function as circuits for controlling the second circuit200and the first circuit100, respectively. The output value of the second circuit200may be transferred to the latch circuit300, and the second circuit200may function as a flip-flop circuit.

The first circuit100and the second circuit200perform different operations according to the voltage level of the clock signal CLK. In more detail, for example, when the clock signal CLK is at a logical low level, the second node NET2is pre-charged to a logical high level. Conversely, the first node NET1is discharged to a logical low level by the fifth gate G5connecting to the clock signal CLK and the second node NET2. In this example, the first node NET1and the second node NET2have different logical levels.

In addition, when the clock signal CLK. is at a logical high level, the first node NET1and the second node NET2may operate to have the same logical level. For example, when the input data D is at a logical low level L, the second node NET2is maintained at a logical high level H and the voltage level of the first node NET1transitions from the logical low level L to the logical high level H. In addition, when the input data D is at a logical high level, the first node NET1is maintained at a logical low level L and the voltage level of the second node NET2transitions from the logical high level H to the logical low level L.

According to at least some example embodiments, the logical high level H may refer to a voltage level greater than or equal to a reference level, and the logical low level L may refer to a voltage level less than the reference level. For example, the logical high level H may refer to a voltage level having a value of about 50% or greater and the logical low level L may refer to a voltage level having a value of less than about 50%. However, aspects of example embodiments are not limited to this example. The reference level may vary in various manners. Based on this finding, logical levels of semiconductor circuits will be described with regard to the logical high level H and the logical low level L.

Referring toFIG. 3, in a semiconductor circuit according to some example embodiments of inventive concepts, when the voltage level of the clock signal CLK rises, an inverted value of the voltage level of input data D may be transferred to the output terminal QN. That is, for example, the voltage level of the output node OUT of the latch circuit300is inverted by an inverter to determine the voltage level of the output terminal QN.

The voltage level of the output terminal QN may be changed at a positive edge of the voltage level of the clock signal CLK. Consequently, when the clock signal CLK transitions to the logical high level H and the second node NET2is at the logical low level L, the voltage level of the output terminal QN may be synchronized with the voltage level of the second node NET2to then be output. However, aspects of example embodiments are not limited to this example.

Example circuit operations in a first section ta1will now be described in more detail with reference toFIGS. 1 to 3. In the first section tal, the input data D is at logical low level L and the clock signal CLK is at logical high level H.

In the second circuit200, since the voltage level of the clock signal CLK is logical high level H, a transistor PE2gated to an inverted value of the voltage level of the clock signal CLK is turned on to pre-charge the second node NET2. In this example, the voltage level of the second node NET2may be logical high level H.

In addition, in the second circuit200, the first gate G1performs an OR operation between the voltage level of input data D (e.g., the logical low level L), and the inverted value of the voltage level of the second node NET2(e.g., the logical low level L), and outputs the resulting logical low level L to the second gate G2.

The second gate G2performs a NAND operation between the voltage level of the clock signal CLK, the output of the first gate G1(e.g., the logical low level L) and the voltage level of the first node NET1(e.g., the logical high level H), and transfers the output value of the NAND operation (e.g., the logical high level H) to the second node NET2.

That is, for example, in a state in which the clock signal CLK is at a logical high level H and the input data D is at logical low level L, the second node NET2is maintained at a state in which the second node NET2is pre-charged to the logical high level H, while the first node NET1transitions from the logical low level L to the logical high level H. Since the second node NET2is at logical high level H, an input node IN of the latch circuit300is pre-charged and the voltage level of the output terminal QN is maintained at the logical high level H.

In a second section ta2, the input data D transitions from the logical low level L to the logical high level and the clock signal CLK transitions from the logical high level H to the logical low level L In the second section ta2, the voltage level of the second node NET2is maintained at the logical high level H, and the first node NET1transitions from the logical high level H to the logical low level L.

In a third section ta3, the voltage level of input data is maintained at the logical high level H, and the clock signal CLK transitions from the logical low level L to the logical high level H. In this example, since the voltage level of the output terminal QN is synchronized with the rising edge of the clock signal CLK to be changed, and the second node NET2transitions to the logical low level L, the output terminal QN may also transition to the logical low level L so that the voltage level of the output terminal QN is maintained at the logical low level L,

Referring again toFIG. 2, a semiconductor circuit according to some example embodiments of inventive concepts will be described in terms of example transistor connections.

Referring toFIG. 2, in the semiconductor circuit according to some example embodiments of inventive concepts, the second circuit200includes a transistor PE1(e.g, a pull-up transistor) gated to the inverted value of the voltage level of the first node NET1and pulling up the second node NET2, and a transistor PE2(e.g., a pull-up transistor) connected in parallel with the transistor PE1, gated to the voltage level of the clock signal CLK and pulling up the second node NET2.

In addition, the second circuit200includes a transistor NE1(e.g., a pull-down transistor) gated to the inverted value of the voltage level of the second node NET2and pulling down a third node, and a transistor NE2(e.g., a pull-down transistor) gated to the voltage level of the input data D and pulling down the third node NET3.

The voltage level of the second node NET2is inverted by the second inverter IN2, and output to the gate of the transistor NE1.

A transistor NE5and a transistor NE6may be connected in series, and the transistor NE5may be connected to the third node NET3. The transistor NE5(e.g., a pull-down transistor) is gated to the inverted value of the voltage level of the first node NET1and pulls down the third node NET3. The transistor NE6is gated to the voltage level of the clock signal CLK and pulls down the third node NET3.

The first circuit100may include a transistor PE3(e.g., a pull-up transistor) gated to the inverted value CKB of the voltage level of the clock signal CLK and pulling up the first node NET1, and a transistor NE3connected to the transistor PE3in series, gated to the inverted value CKB of the voltage level of the clock signal CLK and transferring a ground voltage to the first node NET1.

In addition, the first circuit100may include a transistor PE4and a transistor NE4. The transistor PE4is connected in parallel with the transistor PE3, gated to the voltage level of the first node NET1and outputs the inverted value of the voltage level of the first node NET1. The transistor NE4is connected to the transistor PE4in series, gated to the voltage level of the first node NET1, and outputs the inverted value of the voltage level of the first node NET1.

The transistor PE4and the transistor NE4may function as the first inverter IN1ofFIG. 1.

FIG. 4is a block diagram of another semiconductor circuit according to some example embodiments of inventive concepts. The semiconductor circuit shown in FIG,4is similar to the semiconductor circuit shown inFIG. 1, and thus, repeated descriptions of the same details as those of the example embodiment discussed above will be omitted.

Referring toFIG. 4, the semiconductor circuit according to some example embodiments of inventive concepts includes a first circuit100and a second circuit200.

Unlike in the example embodiment shown inFIG. 1, the semiconductor circuit inFIG. 4does not include a latch circuit. Therefore, the semiconductor circuit may function as an integrated clock gating circuit, rather than as a flip-flop circuit, In the example embodiment shown inFIG. 4, an enable signal E, rather than the input data D, is input to the gates G1and G3, and the output of the semiconductor circuit is signal ECLK.

FIG. 5is a block diagram of another semiconductor circuit according to some example embodiments of inventive concepts. The semiconductor circuit shown inFIG. 5is similar to the semiconductor circuit shown inFIG. 1, and thus, repeated descriptions of the same details as those of the example embodiment discussed above will be omitted.

Referring toFIG. 5, the semiconductor circuit according to some example embodiments of inventive concepts includes a first circuit100, a second circuit200, a latch circuit300, and a multiplexer400.

Compared to the semiconductor circuit shown inFIG. 1, the semiconductor circuit shown inFIG. 5may function as a flip-flop circuit by additionally including the multiplexer400to add a scan test signal.

FIG. 6is a block diagram of yet another semiconductor circuit according to some example embodiments of inventive concepts, andFIG. 7is a circuit diagram of a semiconductor circuit according to some example embodiments of inventive concepts. The semiconductor circuit shown inFIGS. 6 and 7is similar to the semiconductor circuit shown inFIGS. 1 and 2. Thus, for brevity, repeated descriptions of the same details as those of the example embodiment shown inFIGS. 1 and 2will be omitted.

Referring toFIGS. 6 and 7, the semiconductor circuit includes a first circuit110, a second circuit210, and a latch circuit300.

The first circuit110is similar to the first circuit100shown inFIGS. 1 and 2, but further includes a circuit operating as a scan test path. Accordingly, the first circuit110may perform a scan test operation using the added scan test path while reducing and/or minimizing a change in the data path. Transistors additionally installed in the first circuit110are illustrated inFIG. 7.

InFIG. 7, flip-flop circuits with scan test paths added are illustrated at the transistor level. Referring toFIG. 7, the added transistors are connected to a node at which an inverted clock signal CKB is generated, and only nodes to which a scan enable signal SE or an inverted scan enable signal SIN is input are connected in parallel with a node to which the input data D is applied.

FIG. 8is a circuit diagram of another semiconductor circuit according to some example embodiments of inventive concepts. The semiconductor circuit shown inFIG. 8is similar to the semiconductor circuit shown inFIGS. 6 and 7. Thus, repeated descriptions of the same details as those of the example embodiment shown inFIGS. 6 and 7will be omitted.

Referring toFIG. 8, the semiconductor circuit according to some example embodiments of inventive concepts includes a first circuit115, a second circuit210, and a latch circuit300.

As with the first circuit110shown inFIGS. 6 and 7, the first circuit115includes a circuit operating as a scan test path. Accordingly, the first circuit115may perform a scan test operation using the added scan test path while reducing and/or minimizing a change in the data path. In addition to the circuitry common the first circuit110and the first circuit115, the first circuit115may further include transistors116aand116bto which a reset signal R is input to perform a reset operation.

FIG. 9is a circuit diagram of another semiconductor circuit according to some example embodiments of inventive concepts. The semiconductor circuit shown inFIG. 9is similar to the semiconductor circuit shown inFIG. 8. Thus, repeated descriptions of the same details as those of the example embodiment shown inFIG. 8will be omitted.

Referring toFIG. 9, the semiconductor circuit includes a first circuit117, a second circuit210, and a latch circuit300.

As with the first circuit115shown inFIG. 8, the first circuit117includes a circuit operating as a scan test path. Accordingly, the first circuit117may perform a scan test operation using the added scan test path while reducing and/or minimizing a change in the data path. The first circuit117further includes a gate circuit118. The gate circuit118receives a scan enable signal SE and an inverted clock signal CKB as inputs, and performs a NAND operation. The gate circuit118is implemented as a NAND gate circuit modified from the NMOS shown inFIG. 7, at which the node NET1discharging the inverted clock signal CKB and the node NSE are connected in parallel.

FIG. 10is a circuit diagram of yet another semiconductor circuit according to some example embodiments of inventive concepts. For brevity, repeated descriptions of the same details as those of the example embodiments discussed above will be omitted.

Referring toFIG. 10, the semiconductor circuit according to some example embodiments of inventive concepts includes a first circuit119, a second circuit210, and a latch circuit300.

The first circuit119further includes a circuit operating as a scan test path. Accordingly, the first circuit119may perform a scan test operation using the added scan test path while reducing and/or minimizing a change in the data path. In addition, the first circuit119includes a separate inverter outputting an output signal NSE inverted to a scan enable signal SE.

FIG. 11is a block diagram of another semiconductor circuit according to some example embodiments of inventive concepts, andFIG. 12is a circuit diagram of the semiconductor circuit shown inFIG. 11. For brevity, repeated descriptions of the same details as those of the example embodiments discussed above will be omitted.

Referring toFIGS. 11 and 12, the semiconductor circuit according to some example embodiments of inventive concepts includes a first circuit120and a second circuit220.

Referring toFIG. 11, the semiconductor circuit does not include a latch circuit, and thus, may function as an integrated clock gating circuit, rather than as a flip-flop circuit. In addition, the first circuit120further includes a circuit operating as a scan test path. Accordingly, the first circuit120may perform a scan test operation using the added scan test path while reducing and/or minimizing a change in the data path.

InFIG. 12, the circuitry of the integrated clock gating circuit with a scan test path added thereto is illustrated at the transistor level.

FIG. 13is a circuit diagram of another semiconductor circuit according to some example embodiments of inventive concepts. For brevity, repeated descriptions of the same details as those of the example embodiments discussed above will be omitted.

Referring toFIG. 13, the semiconductor circuit includes a first circuit120and a second circuit220. Compared to the semiconductor circuit shown inFIG. 12, the semiconductor circuit includes a merged circuit of two transistors to which a voltage level of a second node NET2is input.

FIG. 14is a block diagram of a system-on-chip (SoC) system including one or more semiconductor circuits according to example embodiments.

Referring toFIG. 14, the SoC system1000includes an application processor1001and a dynamic random access memory (DRAM)1060.

The application processor1001may include a central processing unit (CPU)1010, a multimedia system1020, a multilevel interconnect bus (BUS)1030, a memory system1040, and a peripheral circuit1050.

The CPU1010may perform operations required to drive the SoC system1000. In some example embodiments, the CPU1010may be configured in a multi-core environment including a plurality of cores.

The multimedia system1020may be used in performing a variety of multimedia functions in the SoC system1000. The multimedia system1020may include a 3D engine module, a video codec, a display system, a camera system, a post-processor, etc.

The bus1030may be used in performing data communication among the CPU1010, the multimedia system1020, the memory system1040, and/or the peripheral circuit1050. In some example embodiments, the bus1030may have a multi-layered structure. In more detail, examples of the bus1030may include a multi-layer advanced high-performance bus (AHB), or a multi-laver advanced eXtensible interface (AXI), but aspects of example embodiments are not limited thereto.

The memory system1040may provide environments for high-speed operation by connecting the AP1001to an external memory (e.g., the DRAM1060). In some example embodiments, the memory system1040may include a separate controller (e.g., a DRAM controller) for controlling the external memory (e.g., the DRAM1060).

The peripheral circuit1050may provide environments for more smoothly connecting the SoC system1000to an external device (e.g., a main board). Accordingly, the peripheral circuit1050may include various kinds of interfaces which enable the external device to be compatible with the SoC system1000when connected to the SoC system1000.

The DRAM1060may function as a working memory required to operate the AP1001. In some example embodiments, as shown, the DRAM1060may be outside the AP1001. In more detail, for example, the DRAM1060may be packaged with the AP1001in the form of a package on package (PoP).

At least one component of the SoC system1000may employ one or more semiconductor circuits according to example embodiments.

In addition, the SoC system1000may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or any electronic product that may transmit and/or receive information in a wireless environment.

FIG. 15is a block diagram of an electronic system including one or more semiconductor circuits according to example embodiments.

Referring toFIG. 15, the electronic system1100according to example embodiments may include a controller1110, an input/output device (I/O)1120, a memory device1130, an interface1140, and a bus1150. The controller1110, the I/O1120, the memory device1130, and/or the interface1140may be connected to each other through the bus1150. The bus1150corresponds to a path through which data moves.

The controller1110may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements capable of functions similar to those of these elements.

The I/O1120may include a keypad, a keyboard, a display device, and so on.

The memory device1130may store data and/or commands.

The interface1140may perform functions of transmitting data to a communication network or receiving data from the communication network. The interface1140may be wired or wireless. For example, the interface1140may include an antenna and/or a wired/wireless transceiver, and so on.

Although not shown, the electronic system1100may further include high-speed DRAM and/or SRAM as a working memory for improving the operation of the controller1110.

The electronic system1100may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or any electronic product that may transmit and/or receive information in a wireless environment.

At least one component of the electronic system1100may employ one or more of the semiconductor circuits according to example embodiments.