Computer and data saving method

It is provided a computer comprising a nonvolatile memory for storing data, a control processor for controlling the saving of data into the nonvolatile memory, and a battery for supplying power to the computer in case of a failure of an external power supply, wherein the control processor checks a charge amount stored in the battery, calculates an amount of data which can be saved in the nonvolatile memory by the battery in case of a failure of the external power supply based on the checked charge amount, and saves data excluding the amount of data that can be saved, out of data which should be saved into the nonvolatile memory, into the nonvolatile memory in advance.

CLAIM OF PRIORITY

The present application claims priority from Japanese patent application JP 2011-227244 filed on Oct. 14, 2011, the content of which is hereby incorporated by reference into this application.

BACKGROUND OF THE INVENTION

The present invention relates to a computer and particularly to a technology pertaining to data saving in case of a power outage and data recovery at the time of power recovery.

Conventionally, a server system in a data center, a hospital or the like includes an uninterruptible power supply (UPS) and can continue to operate even in case of a failure such as a power outage. Specifically, the system is continuously operated by starting up a private power generator during a continuous operation using the UPS.

JP 2006-172355 A1 discloses a technology for reducing power consumption of a battery power supply while protecting cache data by a control in conformity with data classification in a cache memory and a battery remaining amount in a case where an external power supply is interrupted due to a failure as a technology to recover from the failure.

SUMMARY OF THE INVENTION

In the conventional system using the USP, there have been problems of high cost of the battery used in the UPS and high installation cost. Further, it has not been possible in some cases to safely stop the system in case where the private power generator is not provided and in case where the supply of power is assumed to stop for a long time.

Considering the above problems, the present invention aims to provide a computer capable of stopping a system less costly and safely.

To solve the above problems, configurations as claimed are, for example, adopted.

The representative one of inventions disclosed in this application is outlined as follows. There is provided a computer comprising a nonvolatile memory for storing data, a control processor for controlling the saving of data into the nonvolatile memory, and a battery for supplying power to the computer in case of a failure of an external power supply. The control processor checks a charge amount stored in the battery, calculates an amount of data which can be saved in the nonvolatile memory by the battery in case of a failure of the external power supply based on the checked charge amount, and saves data excluding the amount of data that can be saved, out of data which should be saved into the nonvolatile memory, into the nonvolatile memory in advance.

According to a typical example disclosed in this application, a system can be stopped less costly and safely.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, an embodiment of the present invention is described with reference to the drawings. It should be noted that the same elements are, in principle, denoted by the same reference signs in all the drawings showing the embodiment and not repeatedly described.

FIG. 1is a diagram showing an example of the configuration of an information processing apparatus (computer)1according to the embodiment of the present invention.

The information processing apparatus1includes a mother board100and a power supply device170in the same chassis10. A CPU (Central Processing Unit)110, a PC (Peripheral Controller)120, a HDD (Hard Disk Drive)130, a DRAM (Dynamic Random Access Memory)140, a control processor150, a nonvolatile memory160and the like are mounted on the mother board100.

The CPU110is an arithmetic processing unit and includes a register and a cache memory which are not shown. The PC120is a control device for performing a communication control with a peripheral device (e.g. HDD130inFIG. 1). The HDD130is a nonvolatile storage device for recording various pieces of information.

The DRAM140is a volatile storage device. The control processor150is an arithmetic processing unit for executing a data saving process and a data recovery process according to the embodiment of the present invention. The nonvolatile memory160is a nonvolatile storage device such as a flash memory.

It should be noted that the HDD130and the nonvolatile memory160are collectively called “nonvolatile storage devices” below. Further, the register and the cache memory of the CPU110and the DRAM140are collectively called “volatile storage devices”.

The power supply device170includes a battery250(seeFIG. 2) to be described later, and supplies power to the mother board100in case where the power from an external power supply180is interrupted, i.e. in case of a power outage. The power supply device170is described in detail later usingFIG. 2. The external power supply180is a power supply outside for feeding power to the mother board100via the power supply device170.

FIG. 2is a diagram showing an example of the configuration of the power supply device170according to the embodiment of the present invention.

The power supply device170includes a power supply control processor200, AC/DC converters210,211and212, switches220and221, an A/D converter230, a capacitor240, the battery250, a DC/DC converter260, diodes270and271, wiring and the like.

The power supply control processor200controls the entire power supply device170. Specifically, the power supply control processor200executes an operation of checking the operation of the AC/DC converter210, on/off switching of the switches220and221, on/off switching of the DC/DC converter260, and a charged state of the capacitor240and the battery250based on an output signal of the A/D converter230.

The AC/DC converters210to212convert alternating current power input from the external power supply180into direct current power. The switches220and221switch on/off a current. For example, in case where the switch220is on, the direct current power output from the AC/DC converter211is input to the capacitor240. That is, the capacitor240is charged. The A/D converter230converts a voltage value indicated by an analog quantity into a voltage value indicated by a digital quantity.

The capacitor240is a small-capacity condenser capable of dealing with momentary power interruption. The battery250is a small-capacity storage battery or a condenser having a larger capacity than the capacitor240.

The DC/DC converter260converts the input direct current power into direct current power having a different voltage. The diodes270and271are electronic devices having a rectifying action (action to allow a current to flow only in a specified direction).

During a normal operation, the alternating current power from the external power supply180is supplied to the power supply device170. The supplied alternating current power is fed to the mother board100via the diode270after being converted into direct current power in the AC/DC converter210. Further, the supplied alternating current power is fed to the capacitor240via the switch220after being converted into direct current power in the AC/DC converter211. Furthermore, the supplied alternating current power is fed to the battery250via the switch221after being converted into direct current power in the AC/DC converter212.

Here, power stored in the capacitor240is fed to the mother board100in case of momentary power interruption (power flicker), i.e. in case where the power from the external power supply180is interrupted for about several microseconds.

On the other hand, in case where the power from the external power supply180is interrupted for a period exceeding several microseconds, the power supply control processor200checks the occurrence of a power outage based on an output value of the A/D converter230(specifically, an output voltage value of the AC/DC converter211input to the A/D converter230). Thereafter, the power supply control processor200notifies the occurrence of the power outage to the control processor150. In addition, the power supply control processor200starts up the DC/DC converter260. Then power charged in the battery250to be fed to the mother board100via the diode271.

Further, the power supply control processor200determines charged states and failure states of the capacitor240and the battery250based on an output value of the A/D converter230(specifically, output voltages of the capacitor240and the battery250, temperature information, information on charge/discharge current and the like input to the A/D converter230). Thereafter, the power supply control processor200notifies the charged states and the failure states of the capacitor240and the battery250to the control processor150.

It should be noted that notification may be made by writing data into a storage area in the control processor150or may be made by writing data into an external storage area readably by the control processor150.

FIG. 3shows an example of a transferable data information table300according to the embodiment of the present invention.

Information indicating a correspondence relationship between a charge amount (remaining charge amount) of the battery250and a data amount transferable to the nonvolatile memory160using the charge amount of the battery250is stored in the transferable data information table300. The transferable data information table300is generated in advance and stored in the nonvolatile memory160(seeFIG. 1).

In an example shown inFIG. 3, the charge amount (unit: watt) of the battery250, the data amount (unit: megabyte) transferable from the DRAM140to the nonvolatile memory160and the data amount (unit: megabyte) transferable from the CPU110(strictly speaking, register and cache memory in the CPU110) to the nonvolatile memory160are related to each other.

It should be noted that the data amount transferable from the CPU110to the nonvolatile memory160may differ depending on the type of the memory, i.e. the register or the cache memory, in the CPU110and a transfer method.

Further, in the transferable data information table300, parameter values of a calculation formula may be stored instead of each specific value shown inFIG. 3. For example, in the example shown inFIG. 3, the data amount transferable from the DRAM140to the nonvolatile memory160is expressed by “5X+500” in case where the charge amount of the battery250is “X”. Similarly, the data amount transferable from the CPU110to the nonvolatile memory160is expressed by “25X+2500”. Thus, parameter values of each of these calculation formulas may be stored. In this case, the control processor150calculates a data amount transferable to the nonvolatile memory160based on the calculation formula using the stored parameter values and the charge amount of the battery250.

FIG. 4is a flow chart showing a data saving operation corresponding to the charge amount of the battery250according to the embodiment of the present invention.

Here is described an operation of the information processing apparatus1to save data into the nonvolatile memory160in advance according to the charge amount (remaining amount) of the battery250during a normal operation (in the non-occurrence of a power outage).

First, in Step S410, the power supply control processor200checks the charge amount of the battery250. The power supply control processor200calculates the charge amount of the battery250by comparing an output value of the A/D converter230(specifically, output voltage of the battery250, temperature information, information on charge/discharge currents and the like input to the A/D converter230) and characteristic data of the battery250. Thereafter, the power supply control processor200notifies information on the calculated charge amount of the battery250to the control processor150. It should be noted that the power supply control processor200regularly checks the charge amount of the battery250.

Subsequently, in Step S420, the control processor150calculates a data amount transferable to (can be saved in) the nonvolatile memory160by the battery250in case of a power outage based on the remaining amount of the battery250calculated in Step S410and the transferable data information table300(seeFIG. 3).

Thereafter, in Step S430, the control processor150calculates a data amount of difference data between backup data and current state data. The backup data is the last data backed up (saved) from the volatile storage device to the nonvolatile storage device. The current state data is data currently stored in the volatile storage device. That is, the difference data may be data updated from the backup data (hereinafter, referred to as “updated data”) and data which should be saved in the nonvolatile storage device.

It should be noted that the control processor150may calculate the data amount of the updated data by checking a dirty bit of a TLB (Translation Look-aside Buffer) in the CPU110.

Here, the TLB is a cache in the CPU110and a conversion table for managing mapping information indicating a correspondence relationship between a virtual address used when the CPU110executes a program and a physical address on the DRAM140by the size, for example page (or block). The TLB is managed by an operating system (OS) installed in the information processing apparatus1and holds a part of the mapping information managed by a page table on the DRAM140.

Further, the TLB manages the dirty bit (dirty flag) indicating whether data in each page has been updated. Thus, in case where the dirty bit corresponding to a predetermined page is dirty (set at1), data in a virtual address (data stored in the cache memory in the CPU110) corresponding to the predetermined page has been updated. On the other hand, data in a physical address (data stored in the DRAM140) corresponding to the predetermined page has not been updated. That is, the data in the physical address and the data in the virtual address corresponding to the predetermined page is the updated data.

It should be noted that, in Step S430, the control processor150may obtain a write target address and the size of data to be written based on a write command to the DRAM140issued by the CPU110and calculate the data amount of the above updated data.

Further, in Step S430, the control processor150adds an entry to an updated data information table500(to be described later usingFIG. 5) and writes the address, data size, priority and update time of the updated data respectively in an update address (backup source address)501, a data size503, a priority506and an update time507. The detail of each attribute is described later usingFIG. 5.

Thereafter, in Step S440, the control processor150compares the data amount of the difference data (updated data) calculated in Step S430and the data amount transferable in case of a power outage calculated in Step S420. In case where the data amount of the difference data is smaller than the data amount transferable in case of a power outage (No in S440), the difference data can be saved also in case of a power outage and needs not be saved in advance. Thus, the process is terminated.

On the other hand, in case where the data amount of the difference data is larger than the data amount transferable in a power outage (Yes in S440), data is saved in the nonvolatile storage device in advance so that the data amount of the difference data becomes smaller than the data amount transferable in case of a power outage (S450). For example, in case where the data amount of the difference data is 3000 MB and the data amount transferable in case of a power outage is 1000 MB, data of 2000 MB out of the difference data of 3000 MB excluding (subtracting) 1000 MB is saved in the nonvolatile storage device in advance. This enables the remaining difference data of 1000 MB to be reliably saved in case of a power outage. Thereafter, the process is terminated.

It should be noted that, in Step S450, the control processor150may save the difference data in a decreasing order of the priority506with reference to the priority506(seeFIG. 5) set for the difference data.

Further, in saving the data in Step S450, the control processor150writes a save destination address in a backup destination address502of the updated data information table500(seeFIG. 5) corresponding to the data. Further, the control processor150writes a save completion flag indicating that saving has been completed in a save flag504or505. That is, in case where the save destination is the HDD130, the save flag505is set as “1”. On the other hand, in case where the save destination is the nonvolatile memory160, the save flag504is set as “1”.

As described above, the control processor150saves the updated data into the nonvolatile memory160in advance according to the charge amount of the battery250during the normal operation of the information processing apparatus1. It should be noted that a reduction in the processing of the CPU110can be prevented by not the CPU110, but the control processor150executing a series of operations.

FIG. 5shows an example of the updated data information table500according to the embodiment of the present invention.

The updated data information table500stores information on the updated data that should be saved in the nonvolatile storage devices. The updated data information table500is stored in the nonvolatile memory160(seeFIG. 1).

In the example shown inFIG. 5, information including the update address501, the backup destination address502, the data size503, the nonvolatile memory save flag504, the HDD save flag505, the priority506and the update time507are stored with relations each other as information on the updated data.

The update address501is a backup source address (initial address indicating the arrangement on the DRAM140or the cache memory of the CPU110) of the updated data. The backup destination address502is an initial address indicating the arrangement on the nonvolatile storage device as the backup destination of the updated data.

The data size503is size of the updated data. That is, data from the initial address indicated by the update address501to an address offset by the size indicated by the data size503is the updated data.

The nonvolatile memory save flag504is a flag indicating whether the save destination of the updated data is the nonvolatile memory160. In case where the updated data is saved in the nonvolatile memory160, in the save flag504is set as “1”. Otherwise, “0” is set.

The HDD save flag505is a flag indicating whether the save destination of updated data is the HDD130. In case where the updated data is saved in the HDD130, the save flag505is set as “1”. Otherwise, the save flag505is set as “0”.

The priority506is information indicating a priority pertaining to data saving of each updated data. Upon saving data, updated data having a high priority506is preferentially saved. The priority506is given according to the type and use frequency of an application program using the updated data. For example, the priority of the updated data is set to be higher for an application program having a higher degree of importance according to a degree of importance of each application program set in advance by a user. Further, the priority of the updated data is set to be higher for an application program having a higher use frequency. This enables the updated data having a high priority to be saved even in case where perfect data saving cannot be performed by any chance.

The update time507is information indicating time of updating the updated data. The update time507is recorded after the processing of Step S403ofFIG. 4and when the updated data is saved. At the time of power recovery, the data configuration before the data saving can be restored by recovering the data in a time order of the update time507.

In the updated data information table500described above, the backup source address of the updated data and the backup destination address in the nonvolatile memory160are respectively recorded in the update address501and the backup destination address502and the nonvolatile memory save flag504is set as “1” in case where the updated data is saved in the nonvolatile memory160. Thereafter, in case where the updated data is saved in the HDD130, the nonvolatile memory save flag504is set as “0” and the HDD save flag505is set as “1”. Further, in case where the updated data stored in the DRAM140is saved in the HDD130, an address on the DRAM140as a save source and an address on the HDD130as a save destination are respectively recorded in the update address501and the backup destination address502and the HDD save flag505is set as “1”.

FIG. 6is an example of a flow chart showing a control logic of the data saving process of the power supply control processor200in case of a power outage according to the embodiment of the present invention.

Here is described the data saving process in case where the power from the external power supply180is stopped to enter a so-called power outage state.

First, in Step S610, the power supply control processor200checks a state of the external power supply180. Specifically, the power supply control processor200monitors the power from the external power supply180based on an output value of the A/D converter230. For example, the power supply control processor200periodically checks the power from the external power supply180.

Subsequently, in Step S620, the power supply control processor200determines whether the power from the external power supply180is stopped, based on the output value of the A/D converter230. In case where the power from the external power supply180is not stopped (No in S620), the process is terminated (S650) since the data saving process in a power outage is not necessary.

On the other hand, in case where the power from the external power supply180is stopped (Yes in S620), the power supply control processor200starts the DC/DC converter260and switches to drive the mother board100based on power fed from the battery250(S630). In Step S630, the mother board100is driven by power from the capacitor240until a switch is made to power feeding by the battery250.

Thereafter, in Step S640, the power supply control processor200notifies the switch to the power feeding by the battery250to the control processor150and the control processor150saves data. Data saving by the control processor150is described later usingFIG. 7. Thereafter, the process is terminated (S650).

By the process described above, the power supply control processor200saves the data in case where the power from the external power supply180is stopped to enter the so-called power outage state.

FIG. 7is an example of a flow chart showing a control logic of the data saving process of the control processor150in case of a power outage according to the embodiment of the present invention. Here, the processing in Step S640ofFIG. 6is described in detail.

First, in Step S710, the control processor150checks the updated data that is not recorded in the nonvolatile storage device out of each updated data registered in the updated data information table500(seeFIG. 5). Specifically, the updated data for which the save flags504and505are both set as “0” in the updated data information table500is checked.

Subsequently, in Steps S720and S730, the control processor150saves a register value of the CPU110and the page table stored in the DRAM140into the nonvolatile memory160respectively.

Thereafter, in Step S740, the control processor150writes data in a page for which the dirty bit is dirty (i.e. dirty data), out of data stored in the cache memory in the CPU110, back to the DRAM140(write-back). Here, the dirty data is data stored in the cache memory in the CPU110and updated that is different from the content of the data stored in the DRAM140by a writing operation executed by the CPU110.

Thereafter, in Step S750, the control processor150saves the updated data stored in the DRAM140into the nonvolatile memory160in a decreasing order of the priority506set for each pieces of updated data. Here, the updated data stored in the DRAM140is difference data between the data stored in the DRAM140after the write-back process in Step S740and the last data backed up in the nonvolatile storage devices from the DRAM140.

Thereafter, in Step S760, the control processor150records the save completion flag indicating the completion of data saving into a specific area of the nonvolatile memory160. It should be noted that, in case of a failure of data saving, information on the failure may be recorded.

By the above process, the control processor150saves the data in case of a power outage.

It should be noted that the processings of Steps S720to S730may be executed after the processings of Steps S740to S750. Further, although the updated data stored in the DRAM140is saved in the nonvolatile memory160after the dirty data stored in the cache memory in the CPU110is written back to the DRAM140by the processings of Steps S740and S750, there is no limitation to this case. For example, both the dirty data stored in the cache memory in the CPU110and the updated data stored in the DRAM140may be saved into the nonvolatile memory160without performing the write-back to the DRAM140.

FIG. 8is an example of a flow chart showing a control logic of the data recovery process at the time of power recovery according to the embodiment of the present invention.

Here is described the data recovery process in case where the power from the external power supply180is recovered, i.e. when a normal state is recovered.

First, in Step S810, the power supply control processor200checks a state of the external power supply180. Specifically, the power supply control processor200monitors the power from the external power supply180based on an output value of the A/D converter230. It should be noted that the power supply control processor200operates with power supplied from the recovered external power supply180and other power supplies. Further, the power supply control processor200periodically checks the power from the external power supply180.

In case where the power from the external power supply180is not recovered (No in S820), the power supply control processor200terminates the process since the data recovery process cannot be executed. Thereafter, the control logic shown inFIG. 8is repeated again after the elapse of a predetermined period of time.

On the other hand, in case where the power from the external power supply180is recovered (Yes in S820), the power supply control processor200notifies the recovery of the power from the external power supply180to the control processor150(S830).

Thereafter, in Step S840, the control processor150determines whether the last stop (shutdown of the information processing apparatus1in case of a power outage) is a normal stop. Specifically, the control processor150determines whether the last stop is a normal stop by reading the save completion flag (see Step S760ofFIG. 7) stored in the nonvolatile memory160.

In case where the last stop is not a normal stop (No in S840), i.e. if the save completion flag is set as “1”, the control processor150recovers the data by transferring the data saved in the nonvolatile memory160to an original position (register or cache memory in the CPU110or DRAM140) (S860). In Step S860, the control processor150transfers the data in a time order of the update time507(seeFIG. 5) with reference to the updated data information table500. This is to ensure consistency for the data with the overlapping update address501.

In case where the last stop is a normal stop (Yes in S840), i.e. if the save completion flag is set as “0”, the control processor150performs a normal boot process by executing a boot program stored in the HDD130(S850). It should be noted that in case where the boot program is stored in the nonvolatile memory160, the control processor150may perform the normal boot process by executing the boot program stored in the nonvolatile memory160.

According to the above process, the information processing apparatus1executes the data recovery process in case where the power from the external power supply180is recovered, i.e. when the so-called normal state is recovered.

As described above, according to the information processing apparatus1of the embodiment of the present invention, it is possible to stop and recovery of a system less costly and safely by using the small-size and small-capacity battery250.