Method and apparatus for logically removing defective pages in non-volatile memory storage device

One embodiment of the present invention capable of decommissioning a defective non-volatile memory (“NVM”) page in a block is disclosed. A process able to logically decommission a defective page is able to detect defective or bad pages while executing a write operation writing information to one or more NVM page in a NVM block. For example, after examining operation status after completion of the write operation, the NVM page is identified as a defective page if the operation status fails to meet a set of predefined conditions under a normal write operation. Upon marking a location of a page status table to indicate the NVM page as defective page, the page status table containing the page defective information associated with the NVM page is stored at a predefined page in the NVM block.

FIELD

The exemplary embodiment(s) of the present invention relates to the field of semiconductor and integrated circuits. More specifically, the exemplary embodiment(s) of the present invention relates to non-volatile memory (“NVM”) storage devices.

BACKGROUND

With increasing popularity of electronic devices, such as computers, smart phones, mobile devices, automobiles, drones, real-time images, wireless devices, server farms, mainframe computers, and the like, the demand for reliable data storage with high-speed is constantly growing. To handle voluminous data between various electronic devices, high-volume non-volatile memory (“NVM”) storage devices are in high demand. A conventional NVM storage device, for example, is flash based storage device typically known as solid-state drive (“SSD”).

The flash memory based SSD, for example, is an electronic NV storage device using arrays of flash memory cells. The flash memory can be fabricated with several different types of integrated circuit (“IC”) technologies such as NOR or NAND logic gates with, for example, floating-gate transistors. Depending on the applications, a typical flash memory based NVM is organized in blocks wherein each block is further divided into pages. The access unit for a typical flash based NVM storage is a page while conventional erasing unit is a block at a given time.

A problem, however, associated with a conventional NVM storage device is that when one or more NVM pages become defective, a large portion or entire NVM storage device may be discarded or replaced.

SUMMARY

A method and apparatus capable of decommissioning a defective non-volatile memory (“NVM”) page in a block is disclosed. A process able to logically decommission a defective page is capable of detecting defective or bad pages while executing a write operation writing information to one or more NVM page in a NVM block. For example, after examining operation status after completion of the write operation, the NVM page is identified as a defective page if the operation status fails to meet a set of predefined conditions under a normal write operation. Upon marking a location of a page status table to indicate the NVM page as defective page, the page status table containing the page defective information associated with the NVM page is stored at a predefined page in the NVM block.

In an alternative exemplary embodiment, the process is capable of detecting defective or bad pages while executing a read operation obtaining data from one or more NVM page in a NVM block. For example, upon receiving a read request from a host to a memory controller, a defective NVM page can be detected during a read operation. After marking the defective page at a page status table, the table which contains defect information associated with the NVM page is stored at a predefined page at the NVM block. In one aspect, the content of page status table is preserved between block erase operations. In addition, the process is capable of automatically adjusting accessing NVM page when the page status table indicates that the original targeted NVM page is defective.

DETAILED DESCRIPTION

Embodiments of the present invention are described herein with context of a method and/or apparatus for decommissioning a defective non-volatile memory (“NVM”) page in NVM block.

The purpose of the following detailed description is to provide an understanding of one or more embodiments of the present invention. Those of ordinary skills in the art will realize that the following detailed description is illustrative only and is not intended to be in any way limiting. Other embodiments will readily suggest themselves to such skilled persons having the benefit of this disclosure and/or description.

In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be understood that in the development of any such actual implementation, numerous implementation-specific decisions may be made in order to achieve the developer's specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be understood that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skills in the art having the benefit of embodiment(s) of this disclosure.

Various embodiments of the present invention illustrated in the drawings may not be drawn to scale. Rather, the dimensions of the various features may be expanded or reduced for clarity. In addition, some of the drawings may be simplified for clarity. Thus, the drawings may not depict all of the components of a given apparatus (e.g., device) or method. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.

In accordance with the embodiment(s) of present invention, the components, process steps, and/or data structures described herein may be implemented using various types of operating systems, computing platforms, computer programs, and/or general purpose machines. In addition, those of ordinary skills in the art will recognize that devices of a less general purpose nature, such as hardware devices, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), or the like, may also be used without departing from the scope and spirit of the inventive concepts disclosed herein. Where a method comprising a series of process steps is implemented by a computer or a machine and those process steps can be stored as a series of instructions readable by the machine, they may be stored on a tangible medium such as a computer memory device (e.g., ROM (Read Only Memory), PROM (Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), FLASH Memory, Jump Drive, and the like), magnetic storage medium (e.g., tape, magnetic disk drive, and the like), optical storage medium (e.g., CD-ROM, DVD-ROM, paper card and paper tape, and the like) and other known types of program memory.

The term “system” or “device” is used generically herein to describe any number of components, elements, sub-systems, devices, packet switch elements, packet switches, access switches, routers, networks, computer and/or communication devices or mechanisms, or combinations of components thereof. The term “computer” includes a processor, memory, and buses capable of executing instruction wherein the computer refers to one or a cluster of computers, personal computers, workstations, mainframes, or combinations of computers thereof.

One embodiment of the present invention discloses a method or apparatus capable of decommissioning a defective non-volatile memory (“NVM”) page in a block. A process able to logically decommission a defective page is able to detect defective or bad pages while executing a write operation writing information to one or more NVM page in a NVM block. For example, after examining operation status after completion of the write operation, the NVM page is identified as a defective page if the operation status fails to meet a set of predefined conditions under a normal write operation. Upon marking a location of a page status table to indicate the NVM page as defective page, the page status table containing the page defective information associated with the NVM page is stored at a predefined page in the NVM block.

In an alternative exemplary embodiment, the process can detect defective or bad pages while executing a read operation obtaining data from one or more NVM page in a NVM block. For example, upon receiving a read request from a host to a memory controller, a defective NVM page can be detected during a read operation. After marking the defective page at a page status table, the table which contains defect information associated with the NVM page is stored at a predefined page at the NVM block. In one aspect, the content of page status table is preserved between block erase operations. In addition, the process is capable of automatically adjusting accessing NVM page when the page status table indicates that the original targeted NVM page is defective.

FIG. 1is a block diagram100illustrating a memory system able to access NVM while detecting and managing defective pages in accordance with one embodiment of the present invention. Diagram100includes input data182, storage device183, output port188, and storage controller102. Storage controller102further includes read module186and/or write module187. Diagram100also includes an erase module184which can be part of storage controller102for erasing or recycling used NVM blocks. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (or devices) were added to or removed from diagram100.

Storage device183, in one example, includes a flash memory based NVM such as SSD. The flash memory cells are organized in multiple arrays for storing information persistently. The flash memory, which generally has a read latency less than100microseconds (“μs”), can be organized in logic units (“LUN”), planes, blocks, and pages. A minimum access unit such as read or write operations, for example, can be set to an NVM page which can be four (4) kilobyte (“Kbyte”), eight (8) Kbyte, or sixteen (16) Kbyte memory capacity depending on the flash memory technologies. A minimum erasing or recycling used NVM pages is generally set to be a NVM block at a time. An NVM block, in one example, can contain 64 to 1024 NVM pages.

In one aspect, other types of NVM, such as phase change memory (“PCM”), magnetic RAM (“MRAM”), STT-MRAM, or ReRAM, can also be used in storage device183. Also, a four (4) Kbyte page or flash memory page (“FMP”) is used for the forgoing discussion. It should be noted that a storage system can contain multiple storage devices such as storage devices183. To simplify the forgoing discussion, the flash memory or flash memory based SSD is herein used as an exemplary NV storage device.

Storage device183, in one embodiment, includes multiple NVMs or flash memory blocks (“FMBs”)190. Each of FMBs190further includes a set of pages or FMPs191-196wherein each page such as page191has a block size of 4096 bytes or 4 Kbyte. In one example, FMBs190can contain from 128 to 512 pages or sectors. A page or block is generally a minimal writable unit or readable unit. Blocks such as FMBs190are able to persistently retain information or data for a long period of time without power supply.

Storage controller or controller102, in one embodiment, includes write-operation bad-page detector (“WBD”)108, read-operation bad-page detector (“RBD”)110, and erase module184. In one aspect, controller102includes a flash translation layer (“FTL”) not shown inFIG. 1for facilitating managing and controlling WBD108, RBD110, and erase module184. The FTL table(s), in one example, is stored in one or more of the NVM pages.

WBD108, in one embodiment, is configured to detect bad page or defective pages during a write operation which can be performed by write module187. Upon completing a write operation, WBD108retrieves write status such as error rate occurred during the write operation and a set of predefined threshold values. If, for example, the error rate is higher than the threshold value, the NVM page should be considered bad page or defective page. In one aspect, a page status table which can be a bit map is used to remember which NVM page is a defective page.

RBD110, in one embodiment, is configured to detect bad page or defective pages during a read operation which can be performed by read module186. Upon completing a read operation, RBD110retrieves read status such as error rate occurred during the read operation and a set of predefined read threshold values. If, for example, the error rate is higher than the threshold value, the NVM page should be considered bad page or defective page. In one aspect, a page status table which can be a bit map is used to remember which NVM page is a defective page. In one embedment, RDB110is also able to identify whether the defective page is due to number of read times since the frequency of reading from the same page can deteriorate overall integrity of the content stored in the page.

Erase module184, in one embodiment, is able to preserve the page status table between erase operations performed to each block. In one aspect, the page status table or bit map indicating defective page(s) within an erase-marked NVM block is first stored in a register or another NVM block before the erase-marked NVM block is erased. After the erase operation, the page status table is restored back in the previously erase-marked NVM block whereby the defective page(s) is continuously decommissioned.

FTL, also known as FTL table, is an address mapping table. FTL includes multiple entries which are used for NVM memory accessing. Each entry of the FTL table, for example, stores a PPA addressing a physical page in the NVM. A function of FTL is to map logical block addresses (“LBAs”) to physical page addresses (“PPAs”) whereby the PPA(s) can be accessed by a write or read command. In one aspect, FTL is capable of automatically adjusting access NVM page when the page status table indicates that the original targeted NVM page is defective. For example, FTL includes a record indicating the replacement pages for defective pages for both read or write operations.

In operation, upon receipt of data input or data packets182, write module or circuit187writes the data from data packets182to a page or pages within a block pointed by LBA or PPA facilitated by FTL. Also, the data stored in storage device183can be refreshed or read by read module186via output port188. In one embodiment, WBD108is used to detect defective page(s) during the write operation. Similarly, RBD110is used to detect or identify defective page(s) during a read operation.

An advantage of employing a mechanism of decommissioning an NVM page within NVM block is that it can enhance overall NVM efficiency as well as NVM reliability.

FIG. 2is a block diagram200illustrating an exemplary layout for NVM device capable of logically removing or decommissioning one or more defective NVM page(s) from a block(s) in accordance with one embodiment of the present invention. Diagram200includes a memory package202which can be a memory chip containing one or more NVM dies or logic units (“LUNs”)204. Memory package202, in one aspect, is a flash based NVM storage that contains, for example, a hierarchy of Package-Silicon Die/LUN-Plane-Block-Flash Memory Page-Wordline configuration(s). It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (or devices) were added to or removed from diagram200.

The NVM device such as a flash memory package202, in one example, contains one (1) to eight (8) flash memory dies or LUNs. Each LUN or die204can be divided into two (2) to four (4) NVM or flash memory planes206. For example, die204may have a dual planes or quad planes. Each NVM or flash memory plane206can further include multiple memory blocks or blocks. In one example, plane206can have a range of 1000 to 8000 blocks. Each block such as block208includes a range of 64 to 512 pages. For instance, block210includes 64 or 512 NVM pages depending on NVM technologies.

A flash memory page such as page1, for example, has a memory capacity from 8 KBytes to 64 KBytes plus extra redundant area for management purposes such as ECC parity bits and/or FTL tables. Each NVM block, for instance, contains from 256 to 512 NVM pages. In an operation, a flash memory block is the minimum unit of erase and a flash memory page is the minimum unit of program (or write) and read.

To avoid discarding an entire block due to a few bad or defective pages, a mechanism of logically decommissioning defective page(s) is used. A function of decommissioning process is to maintain the operation of the NVM block while logically removing bad or defective pages. To identify a defective page within NVM block, a page status table is used to keep track of active pages versus defective pages within each NVM block. It should be noted that 4 Megabytes (“MB”) to 128 MB of storage space can be saved if the page decommissioning is used instead of discarding the entire block.

It should be noted that based on flash memory characteristics, a relatively small number of flash memory pages may be defective or become bad or unusable during a high memory page PE (program erase) cycles. With the implementation of page decommissioning process, a bad or defective NVM page, for instance, can be discovered during program or read operation. For example, a defective or bad page is discovered if that page has higher read errors during normal read work load. Also, a defective or bad page can be determined when error rate is higher than normal during an erase operation.

Upon discovery of a defective page such as page1of block210, a page status table212is used to store the defective information of page1. In one aspect, page status table212resides in a predefined memory page such as page0of each block. For example, block210contains page status table212which indicates status information whether it is defective or active associated to all pages in block210.

An advantage of using page decommissioning is that it logically removes the defective NVM page(s) from an NVM block while the remaining NVM pages within the NVM block are operating normally.

FIG. 3is a block diagram300illustrating a storage device capable of logically decommissioning a defective NVM page in an NVM block in accordance with one embodiment of the present invention. Diagram300illustrates a flash memory block320and page decommission manager318. Block320, in one example, contains512NVM pages302-312wherein the first page such as page302is a designated page for storing page status table316. Page status table316, in one aspect, contains active and defective information associated to all pages302-312of block302. It should be noted that other page or pages can also be used as a designated page to store page status table316.

In one embodiment, manager318can mark a page as a bad page by a bit map or page status table316which is associated with flash memory block320. For example, manager318stores a page status table316which contains bad page information in a bit map in the first flash memory page such as page302. Manger318is coupled to block320via internal bus324to commission and/or decommission certain pages within block320due to defective pages. The defective page, for example, is defected or identified when the flash memory block such as page310of block320is programmed or written. Manager318is also configured to facilitate remembering to restoring content of page status table316between block erase operations performed to block320. For example, the content of page status table316is saved in registers in page decommission manager318while performing an erase operation to page320. The content of page status table316is subsequently restored from the registers of page decommissioning manager318to page302after erasing operation. In one embodiment, if page302is defective, page decommission manager318can elect another page such as page312as the designated page to save the page status table. For example, after recycle operation, manager318writes the previously saved content for page status table316back into first flash memory page such as page302.

FIG. 4is a diagram400illustrating a process of logically decommissioning or removing a NVM page from a block in accordance with one embodiment of the present invention. Diagram400includes input data402, write module406, read module408, and NVM block410. In an alternative embodiment, NVM block410can be substituted with multiple NVM blocks. To simplify the forgoing illustration, one NVM block410which contains multiple pages302-312is used. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (or devices) were added to or removed from diagram400.

Block410, in one example, is a flash based NVM block containing multiple NVM pages302-312in which the first page such as NVM page302is designated for storing page status table416. In one aspect, page status table416can be a bit map. Alternatively, page status table416includes multiple entries wherein each entry includes a validity portion and an address portion. The validity portion indicates whether the page is defective or active while the address portion indicates a page address. For example, NVM pages in block410can be organized in a sequential order wherein page302is the first page in the sequence while page312is the last page in the sequence.

Bit map417, in one embodiment, is a blow-up diagram for page status416showing bit positions452-462. The bit positions in bit map417are configured to correspond to page positions302-312in block410. For example, bit454contains a logic value of one (1) which refers to a defective page is used to indicate the corresponding page304in block410as a defective page as indicated by arrow468. Similarly, bit460in bit map317has a logic value of zero (0) which refers to an active page is used to indicate the corresponding page310as an active page as indicated by arrow466.

During a write operation, write module406obtains input data402from incoming data stream while allowing LBA426associated with data402to travel to bit map417. After verifying validity of physical page in accordance with LBA426, page validity module412issues a validity signal to write module406. If the page is invalid or defective, a new page is subsequently selected such as next page in the sequence. If the page is active or valid, write module406begins to write data402to a selected page418which could correspond to page308of block410. After written or programmed page418, WBD420checks and compares writing status428with retrieved value476to determine whether page418is defective or not. While retrieved value476can be a set of predefined maximum error rate(s) for a normal write operation, status428which includes various parameters such as error rate(s) and time consumed for the last write operation contain the most recent write status. The result of comparison between status428and value476is subsequently forwarded to mark module424. Mark module424subsequently marks the logic value(s) based on the result of comparison. For example, if WBD420detects a defective page, mark module424marks or switches the logic value(s) of a bit corresponding to the defective page such as page308.

For a read operation, read module408obtains LBA426as read address and allows LBA426to reach bit map417. After verifying validity of physical page in accordance with LBA426, page validity module412issues a validity signal to read module408. If the page is invalid or defective, a new page is subsequently selected such as next page in the sequence. If the page is active or valid, read module408begins to read data from a selected page such as page310of block410. After read operation, RBD422checks and compares reading status478with retrieved value470to determine whether read page such as page310is defective or not. While retrieved value470can be a predefined maximum error rate for a normal read operation, status478includes various parameters such as error rate, time consumed for the last read operation, and total number read times performed to the particular page such as page310. For example, an error can occur if the page such as page310has been read too many times. The result of comparison between status478and value470is subsequently forwarded to mark module424. Mark module424marks the logic value(s) based on the result of comparison. For example, if RBD422detects a defective page, mark module424marks or switches the logic value(s) of a bit corresponding to the defective page such as page310.

An advantage of using a process of WBD or RBD420-422is that an NVM block such as block410can operate normally even though there is a portion of pages in the NVM block are defective.

FIG. 5is a block diagram500illustrating a bit map used for a page status table configured to indicate defective pages in accordance with one embodiment of the present invention. Diagram500, in one embodiment, includes an NVM block520, bit map502, and temporary memory504. While NVM block520includes multiple NVM pages302-312, bit map502is stored at the first page in the sequence such as page302. The total number of bits in bit map502is the same or similar to the total number of pages302-312in block520. Each bit of bit map502, in one example, is configured to correspond to a page of block520.

NVM block520, in one example, includes256pages organized in 16 rows by 16 columns. To track the status for each page within NVM block520, a bit map502is also organized in 16 rows by 16 columns within each bit indicates validity of an associated page. In one aspect, the logic state of bit zero (0) indicates an active status and logic state of bit one (1) indicates a defective status. For instance, bit508located at row 1 and column 1 of bit map502is used to indicate the status for page302which is located at row 1 and column 1 in block520. Since bit508contains a logic value of zero (0), page302is active.

Bit512located at row 2 and column 16 of bit map502is used to indicate the status of page308which is located at row 2 and column 16 of block520. Since bit512contains logic value of one (1), page308is defective as indicated by arrow514which should be logically decommissioned. Alternatively, bit516located at row 16 and column 16 of bit map502is used to indicate the status of page312which is located at row 16 and column 16 of block520. Since bit516contains logic value of one (1), page312is defective as indicated by arrow518which should be logically decommissioned.

In one embodiment, temporary memory504can be a set of registers, dynamic random access memory (“DRAM”), or NVM storage space. For example, temporary memory504can be placed in a block other than block520. A function of temporary memory504is to save the content of bit map502or page defective information before performing an erase function to block520for memory erasing, recycling, or reclamation. Once the erase function is completed, the saved content of bit map502in temporary memory504is restored back to bit map502as indicated by arrow506.

In an alternative embodiment, bit map502can be organized in a sequential order when NVM pages in block520are also arranged in a sequential order. In one example, the same bit number position within256bits can be used to reference or locate the same page number position in the block with256pages such as block520.

An advantage of using a bit map having the bit number same as the page number is that the address bits are not necessary in order to locate targeted page(s) within the block because the relative bit position is use to reference the same relative page position.

FIG. 6is a diagram600illustrating a page status table containing validity bits608and address bits604to indicate defective pages in accordance with one embodiment of the present invention. Diagram600is similar to diagram500except that diagram600contains a page status table602using addresses604to point bad or defective pages. Page status table602, in one embodiment, includes multiple entries wherein each entry includes a validity bit608and address bits604. Address bits604, in one example, includes sufficient number of bits to address entire pages within block520. For example, if block520includes256NVM pages302-312, eight (8) bits may be required to address256pages.

For example, page status table602contains ten (10) entries with nine (9) bits per entry. A total of 90 bits is allocated for page status table602. In this example, a maximum number of 10 NVM pages within a block can be decommissioned. An advantage of using page status table602instead of bit map502shown inFIG. 5is that page status table602uses less bits than bit map502if the decommissioned pages are kept 10 or less.

FIG. 7is a block diagram700illustrating a host or memory controller capable of decommissioning defective pages in accordance with one embodiment of the present invention. Computer system or a signal separation system700can include a processing unit701, an interface bus712, and an input/output (“IO”) unit720. Processing unit701includes a processor702, a main memory704, a system bus711, a static memory device706, a bus control unit705, an I/O element730, and a NVM controller785. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram700.

Bus711is used to transmit information between various components and processor702for data processing. Processor702may be any of a wide variety of general-purpose processors, embedded processors, or microprocessors such as ARM® embedded processors, Intel® Core™ Duo, Core™ Quad, Xeon®, Pentium™ microprocessor, Motorola™ 68040, AMD® family processors, or Power PC™ microprocessor.

Main memory704, which may include multiple levels of cache memories, stores frequently used data and instructions. Main memory704may be RAM (random access memory), MRAM (magnetic RAM), or flash memory. Static memory706may be a ROM (read-only memory), which is coupled to bus711, for storing static information and/or instructions. Bus control unit705is coupled to buses711-712and controls which component, such as main memory704or processor702, can use the bus. Bus control unit705manages the communications between bus711and bus712. Mass storage memory or SSD106, which may be a magnetic disk, an optical disk, hard disk drive, floppy disk, CD-ROM, and/or flash memories are used for storing large amounts of data.

I/O unit720, in one embodiment, includes a display721, keyboard722, cursor control device723, and communication device725. Display device721may be a liquid crystal device, cathode ray tube (“CRT”), touch-screen display, or other suitable display device. Display721projects or displays images of a graphical planning board. Keyboard722may be a conventional alphanumeric input device for communicating information between computer system700and computer operator(s). Another type of user input device is cursor control device723, such as a conventional mouse, touch mouse, trackball, or other type of cursor for communicating information between system700and user(s).

Communication device725is coupled to bus711for accessing information from remote computers or servers, such as server104or other computers, through wide-area network102. Communication device725may include a modem or a network interface device, or other similar devices that facilitate communication between computer700and storage network.

NVM controller785, in one aspect, is configured to communicate and manage internal as well as external NVM storage devices. NVM controller785can manage different types NVM memory cells such as flash memory cells and phase change memory cells. For external NVM storage devices, NVM controller785further includes I/O interfaces capable of interfacing with a set of peripheral buses, such as a peripheral component interconnect express (“PCI Express” or “PCIe”) bus, a serial Advanced Technology Attachment (“ATA”) bus, a parallel ATA bus, a small computer system interface (“SCSI”), FireWire, Fibre Channel, a Universal Serial Bus (“USB”), a PCIe Advanced Switching (“PCIe-AS”) bus, Infiniband, or the like.

The exemplary embodiment of the present invention includes various processing steps, which will be described below. The steps of the embodiment may be embodied in machine or computer executable instructions. The instructions can be used to cause a general purpose or special purpose system, which is programmed with the instructions, to perform the steps of the exemplary embodiment of the present invention. Alternatively, the steps of the exemplary embodiment of the present invention may be performed by specific hardware components that contain hard-wired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

FIG. 8is a flowchart800illustrating a process of decommissioning a defective page in connection to a write operation in accordance with one embodiment of the present invention. At block802, a process capable of logically decommissioning an NVM page receives and executes a write operation for writing information to a first or targeted NVM page in an NVM block. In one example, a location of the first or targeted NVM block is identified based on LBA. The data is subsequently written to a flash based NVM page in the first NVM block.

At block804, the operation status associated to the write operation to the first or targeted NVM page is examined once the write operation is completed. The operation status, for example, may include error rate and time consumed for performing the operation. The number of errors reported by error correction code (“ECC”), for instance, can be identified during the write operation.

At block806, the process identifies the first or targeted NVM page as a defective page if the operation status fails to meet a set of predefined conditions for normal write operation. For example, the NVM page may be defective if WBD detects a longer programming time for completing the write operation than a predefined time frame. Alternatively, the NVM page is a defective after determining the number of errors recorded in the operation status is more than a predefined maximum number of error allowed for a normal write operation.

At block808, a location of page status table is marked to indicate that the NVM page is defective. In one aspect, the process is capable of identifying a corresponding bit location to the NVM page in NVM block. A logic value such as logic 1 or 0 is subsequently set in the corresponding bit to indicate the defective page.

At block810, the page status table containing page defective information associated with the NVM page is stored at a predefined page in the NVM block. Upon sending an instruction of data storage from a host to a memory controller for storing data persistently, the write operation with LBA is generated by the memory controller. In one example, the LBA can be translated to a physical page address (“PPA”) which indexes the targeted NVM page in the NVM block using, for instance, FTL. The process, in one embodiment, identifies whether the NVM page is defective based on the defective information in the page status table before the write operation begins. The process is further capable of preserving content or data integrity of the page status table when the NVM block is set to be erased. The page status table, in one example, may be saved in a predefined page in the NVM block or a different NVM block.

FIG. 9is a flowchart900illustrating a process of decommissioning a defective page during a read operation in accordance with one embodiment of the present invention. At block902, a process capable of logically removing an NVM page receives and executes a read operation. To determine where to read from, a location of an NVM page within a block is identified based on the LBA. Once the block and pages are identified, data is read from a flash based NVM page in the NVM block.

At block904, the read operation status of the NVM page is determined after the completion of the read operation. To determine the read operation status, number of errors reported by error correction code (“ECC”) during the read operation is identified. Alternatively, the process is also able to identify total number of read times associated with the NVM page to determine the read operation status associated with the NVM page.

At block906, the NVM page is identified as a defective page if the read operation status fails to meet the predefined minimal conditions for a normal read operation. Upon detecting a longer reading time for completing read operation, the NVM page is identified as a defective page. Alternatively, if the number of errors recorded during the read operation is higher than a predefined maximum number of error rate for a normal read operation, the NVM page is likely to be defective.

At block908, a location of a page status table is marked to indicate that the NVM page is defective. For example, the process is capable of identifying a bit location in the bit map associated with the NVM page in the block.

At block910, the page status table containing page defective information associated with the NVM page is stored at a predefined page in the NVM block. In one aspect, after sending an instruction of read data from a host to a memory controller for retrieving data from a storage device, the read operation with LBA is generated by the memory controller for carrying out the instruction. For example, the LBA is translated to a physical page address (“PPA”) which indexes to the NVM page in the block using, for example, FTL. In one embodiment, the process is able to identify whether the NVM page is defective or not based on the page defective information associated with the NVM page stored in the page status table. In one aspect, the process preserves the content of the page status table when the NVM block is set to be erased. In one example, the page status table is saved in a predefined page of the block.