Circuit for multiplying an analog value by a digital value

A multiplication circuit directly multiplying an analog and a digital data without converting analog/digital or digital/analog converting. An analog input voltage is controlled by a switching signal of a digital voltage so as to generate an analog output or cut-off the outputs. Digital input signals b.sub.0 to b.sub.7 of a plural number of bits is integrated giving weights by means of a capacitive coupling, and a sign bit is added by a capacitive coupling CP with a double weight of the most significant bit ("MSB") of the digital input.

FIELD OF THE INVENTION 
The present invention relates to a multiplication circuit. 
BACKGROUND OF THE INVENTION 
In recent years, there are arguments about a limitation of a digital 
computer because of expotential increase in the amount of money for 
investments for equipment concerning to a minute processing technology. 
Here, an analog computer is calling attention. On the other hand, stored 
conventional digital technology should be used and both workings of a 
digital and an analog processings are necessary, and operational 
processing system including an analog data and a digital data is 
important. 
However, conventionally, such an operational circuit including both an 
analog and a digital data without analog/digital or digital/analog 
converting is not known. 
SUMMARY OF THE INVENTION 
The present invention is invented so as to solve the conventional problems 
and has a purpose to provide a multiplication circuit capable of directly 
multiplying an analog data and a digital data without analog/digital or 
digital/analog converting. 
A multiplication circuit according to the present invention controls an 
analog input voltage by a switching signal of a digital voltage so as to 
generate an analog output or cut-off the output. A digital input signal of 
a plural number of bits with giving weights by means of a capacitive 
coupling, and a sign bit is added by a capacitive coupling with a double 
of the MSB of the digital input.

PREFERRED EMBODIMENT OF THE INVENTION 
Hereinafter, an embodiment of a multiplication circuit according to the 
present invention is described with referring to the attached drawings. 
In FIG. 1, a multiplication circuit M has a plural number of switching 
circuits from SW.sub.1 to SW.sub.8 connected with an analog input voltage 
X and digital input voltages from b.sub.0 to b.sub.7 corresponding to each 
bit of a digital data as a control signal to these switching circuits. 
Outputs of switching circuits are connected with each capacitor in a 
capacitive coupling CP parallelly connecting a plural number of capacitors 
from CC.sub.0 to CC.sub.7, and an output of CP generates an output as 
shown by following formula. 
EQU V.sub.3 ==V.sub.2 (C.sub.3 /C.sub.2)=X (C.sub.3 /C.sub.2) (11) 
This formula is rewritten as follows under a condition of C.sub.2 =C.sub.3. 
EQU Y=X (12) 
As mentioned above, products of an analog input voltage X and a digital 
input voltage (from b.sub.0 to b.sub.7) are directly calculated in a 
multiplication circuit M and it is possible to perform inverted processing 
corresponding to sign bit s at INV.sub.1. 
Outputs of INV.sub.1 and INV.sub.2 are connected with a switching circuit 
SW.sub.9, and SW.sub.9 is switched by a sign bit s of a digital data. The 
switch SW.sub.9 outputs V.sub.2 or V.sub.3 alternatively, as an output 
voltage Y. An inverted output V.sub.2 of Y is output when a sign bit s is 
equal to 1 (high level), and a non-inverted output V.sub.2 is output when 
a sign bit s is equal to 0 (low level). 
FIG. 2 shows the inside of composition of inverter circuits INV.sub.1 and 
INV.sub.2, and FIG. 3 shows an inverter circuit in FIG. 2. 
As FIG. 2 shows, by serially connecting a plural number of inverters from 
I.sub.1 and I.sub.3, an output accuracy becomes higher. Inverters from 
I.sub.1 to I.sub.3 consist of nMOS and pMOS the drains of pMOS is 
connected with a positive voltage, the source of pMOS is connected with 
the drain of nMOS, and the source of nMOS is connected with a negative 
voltage. An input voltage is input to the gates of nMOS and pMOS. An 
output is generated from the junctive of both MOSs. 
FIG. 4 shows the switching circuits from SW.sub.1 to SW.sub.8 in detail. 
The switching circuit is a CMOS switch consisting of a CMOS Tr.sub.1 and a 
dummy transistor Tr.sub.2. An output voltage X is input to a drain of 
Tr.sub.1, and an output is generated at the junctive of Tr.sub.1 and 
Tr.sub.2. A digital input voltage is invertedly connected to the gate of 
pMOS of Tr.sub.1 and the gate of nMOS of Tr.sub.2 and non-invertedly 
connected to the gate of mMOS of Tr.sub.1 and the gate of pMOS of 
Tr.sub.2. As a result, it is possible to realize opening and closing of an 
analog input voltage with little voltage drop at a switch. 
FIG. 5 shows the switching circuit in detail. V.sub.2 and V.sub.3 are 
connected with a pMOS source side in two CMOSs Tr.sub.3 and Tr.sub.4, and 
pMOS drain side is connected with a common capacitance C.sub.4. Sign bit s 
is directly input to a nMOS gate of Tr.sub.3 and pMOS gate of Tr.sub.4, 
and an signal inverted by an inverter I.sub.4 is input to a gate of pMOS 
of Tr.sub.3 and a gate of nMOS of Tr.sub.4. When a sign bit s is equal to 
1, then Tr.sub.3 becomes conductive and an inverted output V.sub.2 is 
impressed to C.sub.4. When a sign bit s is equal to 0, then Tr.sub.4 is 
conductive so that non-inverted output V.sub.3 is impressed to C.sub.4. 
Therefore, it is possible to generate positive and negative output 
corresponding to a sign bit. 
As mentioned above, a multiplication circuit according to the present 
invention controls an analog input voltage by a switching signal of a 
digital voltage so as to generate an analog output or cut-off the outputs. 
A digital input signal of a plural number of bits is integrated giving 
weights by means of a capacitive coupling, and a sign bit is added by a 
capacitive coupling with a double weight of the MSB of the digital input 
so that it is possible to provide a multiplication circuit directly 
multiplying an analog and a digital data without converting analog/digital 
or digital/analog converting.