MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

A manufacturing method for a semiconductor device including a first semiconductor element and a second semiconductor element, includes the steps of forming an insulating layer on a first substrate having a first elastic modulus higher than a second elastic modulus, forming a first semiconductor element having a first bonding surface on the insulating layer, forming a second semiconductor element having a second bonding surface on a second substrate having the second elastic modulus, bonding the first bonding surface and the second bonding surface to each other to form a laminate of the first semiconductor element and the second semiconductor element, and removing the first substrate from the laminate.

TECHNICAL FIELD

The present disclosure relates to manufacturing methods for semiconductor devices.

BACKGROUND ART

For example, Patent Document 1 proposes a manufacturing method for a semiconductor device, including bonding a first substrate having a first elastic modulus onto a second substrate having a second elastic modulus higher than the first elastic modulus, forming a semiconductor element on the first substrate that is thinned, and thereafter separating the first substrate from the second substrate. In Patent Document 1, Si (silicon single crystal) is used for the first substrate and SiC is used for the second substrate, for example, the Si substrate is bonded onto the SiC substrate, the Si substrate is thereafter thinned, and the semiconductor element is formed on the thinned Si substrate.

PRIOR ART DOCUMENTS

Patent Document

DISCLOSURE OF THE INVENTION

Problem to be Solved by the Invention

The present disclosure provides a technique capable of easily manufacturing a laminate of semiconductor elements while reducing distortion.

Means for Solving the Problem

According to one aspect of the present disclosure, there is provided a manufacturing method for a semiconductor device including a first semiconductor element and a second semiconductor element, including the steps of forming an insulating layer on a first substrate having a first elastic modulus higher than a second elastic modulus; forming a first semiconductor element having a first bonding surface on the insulating layer; forming a second semiconductor element having a second bonding surface on a second substrate having the second elastic modulus; bonding the first bonding surface and the second bonding surface to each other to form a laminate of the first semiconductor element and the second semiconductor element; and removing the first substrate from the laminate.

Effects of the Invention

According to one aspect, a laminate of semiconductor elements can easily be manufactured while reducing distortion.

MODE OF CARRYING OUT THE INVENTION

Hereinafter, embodiments for implementing the present disclosure will be described with reference to the drawings. In each of the drawings, the same constituent elements are designated by the same reference numerals, and a repeated description thereof may be omitted.

Manufacturing Method For Semiconductor Device

A semiconductor device according to the present embodiment includes a memory cell array having a plurality of memory cells arranged three dimensionally, and a peripheral circuit including a CMOS (Complementary Metal-Oxide-Semiconductor) circuit that controls the memory cell array. The semiconductor device according to the present embodiment is a 3D NAND flash memory, for example.

As an example of a manufacturing method for a semiconductor device having a memory cell array and a peripheral circuit, there is a method of arranging the memory cell array and the peripheral circuit, side by side, on the same Si (silicon) substrate. On the other hand, a known method of manufacturing a 3D NAND Cell on Peri forms the peripheral circuit on the Si substrate, and laminates the memory cells thereon. Further, a known method of manufacturing a 3D NAND Cell Bond Peri forms the peripheral circuit and the memory cell on two Si substrates, respectively, and bonds a metal pad that is connected to a Cu interconnect layer of the peripheral circuit and a metal pad that is connected to a Cu interconnect layer of the memory cell, to each other. According to this method, it is possible to reduce the size of the semiconductor device and increase the circuit integration rate, by laminating the memory cell array and the peripheral circuit.

The memory cell array has a multilayer film in which silicon oxide films and silicon nitride films are alternately laminated. In recent years, the number of laminated layers of the multilayer film has increased to a three-digit number, for example. For this reason, the multilayer film is distorted into a concave shape, a convex shape, a potato chip shape, or the like due to film stress on the multilayer film, and the memory cell array assumes a distorted shape. If the memory cell array has the distorted shape, a focus margin deviates when exposing and patterning a photoresist during a lithography process, and thus, there is a problem in that a patterning accuracy deteriorates.

In contrast, there is a manufacturing method for a semiconductor device, including bonding a Si substrate onto a SiC substrate, thereafter thinning the Si substrate, forming a semiconductor element on the thinned Si substrate, and thereafter separating the Si substrate from the SiC substrate. According to this method, because a peripheral circuit and a semiconductor element of a memory cell array are laminated on the Si substrate, the Si substrate warps, thereby applying film stress to a multilayer film of the memory cell array. Hence, it is difficult to reduce the distortion of the multilayer film. In addition, the step of thinning the Si substrate increases the number of steps of the manufacturing method for the semiconductor device, thereby causing problems in that a productivity deteriorates, and a manufacturing cost increases.

Hence, in the manufacturing method for the semiconductor device according to the present embodiment, a SiC substrate or the like having a higher elastic modulus than a Si substrate is used, and a memory cell array is formed on the SiC substrate or the like. Warping of the substrate can be reduced by using a substrate harder than the Si substrate, and film stress applied to a multilayer film of the memory cell array can be reduced. As a result, distortion of the multilayer film can be reduced, and the problem of the deteriorating patterning accuracy during the lithography process can be eliminated. Further, after the two kinds of substrates are bonded, the step of thinning one of the substrates is not required, thereby enabling the semiconductor device to be manufactured more easily, the productivity to be improved, and the manufacturing cost to be reduced.

Hereinafter, the manufacturing method for the semiconductor device according to the present embodiment will be described in detail, with reference toFIG.1throughFIG.4.FIG.1throughFIG.4are cross sectional views illustrating the manufacturing method for the semiconductor device according to the embodiment. The manufacturing method according to the present embodiment manufactures a semiconductor device having a laminate of a first semiconductor element6and a second semiconductor element7that are laminated. The first semiconductor element6includes a memory cell array, and the second semiconductor element7includes a peripheral circuit.

First, as illustrated inFIG.1(a), a separation layer D is formed on a surface of a first substrate1. Next, an insulating layer3is formed on a surface of the separation layer D, and the first semiconductor element6is formed on the insulating layer3. The separation layer D may be omitted. In a case where the separation layer D is not provided, the insulating layer3is formed on the surface of the first substrate1, and the first semiconductor element6is formed on the insulating layer3. For the sake of convenience in the following description, the insulating layer3may be described as being included in the first semiconductor element6. The first semiconductor element6has a first bonding surface6aon a side opposite from the surface adjacent to a first separation layer4. In the present embodiment, the separation layer D is provided between the first substrate1and the insulating layer3, and the separation layer D includes the first separation layer4and a second separation layer5. A configuration and functions of the separation layer D will be described later.

As illustrated inFIG.1(b), the second semiconductor element7is formed on a surface of a second substrate2. The second semiconductor element7has a second bonding surface7aon a side opposite from the surface adjacent to the second substrate2. The second substrate2has a second elastic modulus, and is monocrystalline silicon, for example. The first substrate1has a first elastic modulus higher than the second elastic modulus, and is formed of SiC or sapphire or diamond, for example.

The elastic modulus represented by the first elastic modulus and the second elastic modulus can be represented by at least one index selected from a bending strength, a tensile strength, a Young's modulus, and a thermal expansion coefficient. For example, the first substrate1having the first elastic modulus higher than the second elastic modulus is formed of a material having at least one physical property value selected from a higher bending strength, a higher tensile strength, a higher Young's modulus, and a lower thermal expansion coefficient than the second substrate2having the second elastic modulus.

Next, as illustrated inFIG.1(c), the first bonding surface6aand the second bonding surface7aare bonded to each other, using the structures illustrated inFIG.1(a)andFIG.1(b), thereby forming a laminate of the first semiconductor element6and the second semiconductor element7that are laminated. AlthoughFIG.1(c)illustrates the structure including the first substrate1and the first semiconductor element6turned upside down from the state illustrated inFIG.1(a)when bonding the first bonding surface6aand the second bonding surface7ato each other, the structure including the second substrate2and the second semiconductor element7may be turned upside down from the state illustrated inFIG.1(b)when bonding the first bonding surface6aand the second bonding surface7ato each other.

Finally, the first substrate1is removed from the laminate. The first substrate1may be removed from the laminate using any method, as long as method enables the first substrate1to be removed from the laminate. For example, the first substrate1may be removed by cutting. The first substrate1may be polished using a grinding method (Back Side Grinding) or a CMP (Chemical Mechanical Polishing), and the first substrate1may be removed thereafter using a wet etching.

By performing the steps described above, the semiconductor device (3D NAND memory) is completed by the manufacturing method according to the present embodiment. The configuration of the embodiment described above is merely an example, and the present embodiment can be applied to other stacked semiconductor devices.

In the semiconductor device manufactured by the manufacturing method according to the present embodiment, the first semiconductor element6is formed on the first substrate having a higher elastic modulus than the second substrate formed of single crystal silicon. Hence, warping of the first substrate can be reduced, thereby reducing distortion caused by film stress applied to the multilayer film of the memory cell array included in the first semiconductor element6. As a result, it is possible to maintain the patterning accuracy during the lithography process.

As described above, in the manufacturing method for the semiconductor device, the following steps (a) through (e) are performed, so that the semiconductor device can easily be manufactured while reducing the distortion of the first semiconductor element6.

(a) Forming an insulating layer on a first substrate having a first elastic modulus higher than a second elastic modulus.

(b) Forming a first semiconductor element having a first bonding surface on the insulating layer.

(c) Forming a second semiconductor element having a second bonding surface on a second substrate having the second elastic modulus.

(d) Bonding the first bonding surface and the second bonding surface to each other to form a laminate of the first semiconductor element and the second semiconductor element.

(e) Removing the first substrate from the laminate.

Removing First Substrate Using Separation Layer

Next, the step (e) of removing the first substrate1using the separation layer D and the subsequent steps will be described with reference toFIG.2andFIG.3.FIG.2is a cross sectional view illustrating the manufacturing method for the semiconductor device, continued fromFIG.1.FIG.3is a cross sectional view illustrating the manufacturing method for the semiconductor device, continued fromFIG.2.

In the manufacturing method for the semiconductor device according to the present embodiment, the first substrate1is removed using the separation layer D. The separation layer D according to the present embodiment includes the first separation layer4and the second separation layer5. The first separation layer4and the second separation layer5are formed between the first substrate1and the first semiconductor element6.

The first separation layer4is formed adjacent to the first semiconductor element6. As illustrated inFIG.2(a), a light source9outputs laser light having a wavelength suitable for conditions described below, and the first separation layer4absorbs the laser light, thereby generating heat and thermally expanding. For example, the first separation layer4is formed of polysilicon (Poly Si) or polysilicon germanium (Poly SiGe).

The second separation layer5is formed between the first separation layer4and the first substrate1. For example, the second separation layer5is a silicon oxide film (SiO2) or a silicon nitride film (SiN). Because a strong stress is applied to the first separation layer4when removing the first substrate1, the second separation layer5functions as a buffer layer for preventing damage to the first substrate1by the stress.

The second separation layer5may be omitted, but is preferably provided between the first substrate1and the first separation layer4. By removing the first substrate1from the laminate without damage using the second separation layer5, the first substrate1can be reused more easily.

As illustrated inFIG.2(a), the laser light is irradiated from the side of the first substrate1. For this reason, the first substrate1and the second separation layer5are formed of a material that transmits the laser light. The first substrate1is formed of SiC or sapphire or diamond, for example. In addition, the second separation layer5is preferably a silicon oxide film in order to sufficiently transmit the laser light. Thus, the laser light output from the light source9can be transmitted through the first substrate1and the second separation layer5and reach the first separation layer4.

The laser light is transmitted through the first substrate1and the second separation layer5, and is absorbed by the first separation layer4. Thus, a force acts to separate the first semiconductor element6from the first substrate1, due to differences in thermal expansion coefficients (differences in stress) between the first separation layer4and each of the second separation layer5and the first substrate1, and due to an increase in pressure inside the first separation layer4caused by heating. The laser light scans, so that the laser light is irradiated on the entire surface of the first separation layer4. The first substrate1is removed in an order starting from a portion of the first separation layer4irradiated with the laser light.

The example inFIG.2(b)illustrates a state where the first separation layer4is separated into first separation layers4aand4b, due to the differences in thermal expansion coefficients between the first separation layer4and each of the second separation layer5and the first substrate1, and due to the increase in pressure inside the first separation layer4caused by the heating. Thus, the first substrate1is removed from the first semiconductor element6. However, the removal is not limited to the removal described above, and the first separation layer4may remain attached to the first semiconductor element6, and the second separation layer5may instead be removed together with the first substrate1. The first separation layer4and a portion of the second separation layer5may remain attached to the first semiconductor element6, and a remaining portion of the second separation layer5may be removed together with the first substrate1.

The laser light output from the light source9is only required to have a wavelength such that the laser light can be transmitted through the first substrate1. For example, in the case where the first substrate1is formed of sapphire or diamond, for example, light having a wavelength greater than or equal to 200 nm and less than or equal to 1500 nm can be transmitted through the first substrate1. Accordingly, in the case where the first substrate1is formed of sapphire or diamond, the wavelength of the laser light output from the light source9may be greater than or equal to 200 nm and less than or equal to 1500 nm. However, in the case where the first substrate1is formed of sapphire or diamond, the wavelength of the laser light to be irradiated is more preferably greater than or equal to 300 nm and less than or equal to 400 nm.

The first separation layer4and the second separation layer5are formed of materials that can exhibit the respective functions according to the material used for the first substrate1. In the case where the first substrate1is formed of sapphire or diamond and the wavelength of the laser light output from the light source9is less than or equal to 400 nm, the first separation layer4is preferably formed of polysilicon. In this case, the first separation layer4can sufficiently absorb the laser light having the wavelengths less than or equal to 400 nm. The second separation layer5is preferably a silicon oxide film, as described above.

In the case where the first substrate1is formed of SiC, light having a wavelength greater than or equal to 400 nm and less than or equal to 1500 nm can be transmitted through the first substrate1. Accordingly, in the case where the first substrate1is formed of SiC, the wavelength of the laser light output from the light source9can be greater than or equal to 400 nm and less than or equal to 1500 nm. However, in the case where the first substrate1is formed of SiC, the wavelength of the laser light to be irradiated is more preferably greater than or equal to 450 nm and less than or equal to 600 nm. In addition, in the case where the first substrate1is formed of SiC, the first separation layer4is preferably formed of polysilicon germanium. In this case, the first separation layer4can sufficiently absorb the laser light having the wavelength less than or equal to 1500 nm. The second separation layer5is preferably a silicon oxide film, as described above. In the case where the first substrate1is formed of sapphire or diamond or Sic, it is important that the laser light is completely absorbed by the first separation layer4and does not damage a device structure, such as the memory cell array or the like inside the first semiconductor element6. For this reason, the first separation layer4preferably has a thickness greater than or equal to 50 nm so as to completely absorb the laser light.

As illustrated in the example inFIG.2(b), the first separation layer4remains on at least one of the first substrate1and the first semiconductor element6. In the example illustrated inFIG.2(b), the first separation layer4remains on both the first substrate1and the first semiconductor element6, by being divided into the first separation layer4aon the first substrate1and the first separation layer4bon the first semiconductor element6. The second separation layer5may remain only on the first substrate1, or may remain on both the first substrate1and the first semiconductor element6.

FIG.3is a cross sectional view illustrating the manufacturing method for the semiconductor device, continued fromFIG.2. The first separation layer4bremaining on the first semiconductor element6illustrated inFIG.3(a)may be removed by a wet etching or a CMP. In the case where the second separation layer5remains on the first semiconductor element6, the second separation layer5may be removed by a wet etching using a hydrofluoric acid. The first separation layer4bon the first semiconductor element6may remain without being removed, and the removal of the first separation layer4bcan be omitted. Similarly, the second separation layer5on the first semiconductor element6may remain without being removed, and the removal of the second separation layer5can be omitted.

After the first substrate1is removed, the first separation layer4bis removed from the laminate of the first semiconductor element6and the second semiconductor element7on the second substrate2, as illustrated inFIG.3(b). In this state, as illustrated inFIG.3(c), the probing pad8is formed on the surface of the first semiconductor element6. Thus, the manufacturing of the semiconductor device including the laminate of the first semiconductor element6having the probing pad8and the second semiconductor element78is completed. The probing pad8enables an electrical connection with an external element.

Next, reusing of the first substrate1will be described with reference toFIG.4.FIG.4is a cross sectional view illustrating a method for reusing the first substrate1separated from the first semiconductor element6, as illustrated inFIG.2(b). The method for reusing the first substrate1illustrated inFIG.4is one step of the manufacturing method for the semiconductor device according to the present embodiment.

The first substrate1separated from the first semiconductor element6inFIG.2(b)is cleaned. The second separation layer5can be removed without damaging the first substrate1, by removing the second separation layer5by a wet etching using a hydrofluoric acid.

As illustrated inFIG.4(a), in the case where the first separation layer4aremains in addition to the second separation layer5, the first separation layer4ais removed by a wet etching or a CMP. Accordingly, it becomes possible to reuse the first substrate1. In a case where the first substrate1is damaged when removing the second separation layer5or the first separation layer4a, it becomes possible to reuse the first substrate1, by polishing and planarizing the damaged surface of the first substrate1by CMP.

After the first substrate1is cleaned, a new insulating layer3is formed on the first substrate1. Further, the steps (b) through (e) are performed, thereby manufacturing a new semiconductor device. In this case, the first substrate can be reused for manufacturing the semiconductor device.

[Examples of Memory Cell Array and Peripheral Circuit]

An example of the internal configuration of the laminate of the first semiconductor element6and the second semiconductor element7manufactured by the manufacturing method for the semiconductor device according to the present embodiment will be described with reference toFIG.5.FIG.5illustrates the laminate illustrated inFIG.1(c)in an upside down state, with the first semiconductor element6on the lower side and the second semiconductor element7on the upper side.

FIG.5is an enlarged cross sectional view of the structure of a periphery of a columnar part BL of the memory cell array11of the first semiconductor element6, and a part of and a periphery of a CMOS circuit of a peripheral circuit50of the second semiconductor element7. The memory cell array11inFIG.5mainly illustrates a staircase structure21.

As illustrated inFIG.5, the second separation layer5, the first separation layer4, and the insulating layer3are laminated in this order on the first substrate1, and the memory cell array11including a plurality of memory cells is formed on the insulating layer3. A conductive common source line CSL is formed in the insulating layer3, and the columnar part BL of the memory cell array11is connected to the common source line CSL.

The memory cell array11includes a plurality of conductor layers (word lines WL) and a plurality of insulating layers laminated in a Z direction (direction perpendicular to the first bonding surface6a). The plurality of conductor layers are provided as a plurality of word lines WL. The plurality of insulating layers are provided between the plurality of word lines WL that are adjacent in the Z direction, and electrically insulate the plurality of word lines WL from one another. Each word line WL is electrically connected to a word interconnect layer23via a contact plug22. The word line WL is formed of a conductive material, such as tungsten or the like, for example.

The plurality of insulating layers include insulating films, such as silicon oxide films or the like, for example.

A selection gate SG is provided on a laminate of the word lines WL and the insulating layers. The selection gate SG is electrically connected to a selection gate interconnect layer27via a contact plug26. The selection gate SG is also formed of a conductive material, such as tungsten or the like, for example. An interlayer insulating film15is provided on the selection gate SG. Further, an interconnect layer24, a contact plug25, and a metal pad28are formed inside or on the interlayer insulating film15.

An interlayer insulating film16is provided between the metal pads28of an uppermost layer.

The columnar part BL penetrates the word lines WL and the selection gate SG, and is electrically connected to the bit line AL. The columnar part BL includes a memory insulating film, a channel semiconductor layer, and a core insulating film extending in the Z direction. The memory insulating film includes a block insulating film, a charge storage layer, and a tunnel insulating film.

By setting the selection gate SG to a conductive state, the columnar part BL is selectively connected to the bit line AL and receives a voltage from the bit line AL. In the selected columnar part BL, charges are injected/discharged between the channel semiconductor layer and the charge storage layer via the tunnel insulating film. Thus, data can be written or erased. The block insulating film is provided to block the charge of the charge storage layer from leaking to the word line WL. The configuration at an intersection of the word line WL and the memory insulating film corresponds to the memory cell. The memory cell array11having such configurations and functions is formed on the first substrate1.

The first substrate1formed of SiC or the like is used as a support substrate, and the memory cell array11is formed on the first substrate1. That is, the memory cell array11is supported on the first substrate1having a higher elastic modulus than the second substrate2. Thus, the first substrate1is harder than the second substrate2formed of Si or the like, and the first substrate1does not warp, so that the memory cell array11can be supported on the surface of the first substrate1can maintain an approximately flat state by being supported on the surface of the first substrate1.

In this state, the first semiconductor element6is oriented to face a first surface F41of the second substrate2and the second semiconductor element7is oriented to face a second surface F12of the first substrate1, so that as to connect the memory cell array11to the peripheral circuit50. AlthoughFIG.5illustrates a state where the first bonding surface6aof the first semiconductor element6and the second bonding surface7aof the second semiconductor element7are non in contact with each other, the first bonding surface6aof the first semiconductor element6and the second bonding surface7aof the second semiconductor element7are bonded to each other by the bonding performed from this state. Accordingly, the metal pads28on the side of the first semiconductor element6and metal pads37on the side of the second semiconductor element7make contact with one another. The metal pads28and37are formed of a conductive material, such as copper, tungsten, or the like, for example. An interlayer insulating film35is provided between the metal pads37.

The peripheral circuit50includes a CMOS circuit (logic circuit) configuring a controller of the memory cell array11, for example. The second semiconductor element7ofFIG.5is a cross sectional view illustrating the structure of a part of and a periphery of the peripheral circuit50including the CMOS circuit. A plurality of transistors31are provided on the first surface F41of the second substrate2. Each transistor31includes a gate electrode32provided on the first surface F41of the second substrate2via a gate insulating film, and a source diffusion layer and a drain diffusion layer that are not illustrated but provided inside the second substrate2. The plurality of transistors31form the CMOS circuit, and function so as to control the memory cell array11.

Moreover, an interlayer insulating film34is provided on the CMOS circuit, a plurality of plugs33are provided on the source diffusion layer or the drain diffusion layer of the transistor31, and a multilayer interconnect structure36is provided on the plugs33. Further, contact plugs38are provided on the multilayer interconnect structure36, and the metal pads37are connected to the contact plugs38. The peripheral circuit50having such a configuration is formed on the first surface F41of the second substrate2.

The first semiconductor element6having the memory cell array11and the second semiconductor element7having the peripheral circuit50are bonded to each other, by bonding the first bonding surface6aand the second bonding surface7ato each other in the manner described above. As illustrated inFIG.1(c)andFIG.5, the memory cell array11and the peripheral circuit50are laminated in the Z direction between the first substrate1and the second substrate2.

Accordingly, the metal pads28exposed from the first bonding surface6aand the metal pads37exposed from the second bonding surface7amake contact with one another and are electrically connected to one another. Hence, it is possible to control the memory cell array11therewith. The metal pads28and the metal pads37are arranged so as to correspond to one another when the peripheral circuit50and the memory cell array11face each other.

In addition, a contact line DL connected to the common source line CSL penetrates the word lines WL and the selection gate SG, and is connected to a contact line CL. The contact line CL is connected to a contact line EL that is connected to the CMOS circuit, by bonding the first bonding surface6aand the second bonding surface7ato each other. Thus, the multilayer interconnect structure36of the second semiconductor element7is electrically connected to the common source line CSL.

As described above, according to the manufacturing method for the semiconductor device according to the present embodiment, the first semiconductor element6having the memory cell array11is formed on the first substrate1, such as the SiC substrate or the like having the first elastic modulus. In addition, the second semiconductor element7having the peripheral circuit50is formed on the second substrate2, such as the Si substrate or the like having the second elastic modulus.

Then, the first semiconductor element6and the second semiconductor element7are bonded to each other by the bonding, and the memory cell array11and the peripheral circuit50are electrically connected to each other in a state where the first semiconductor element6and the second semiconductor element7are laminated.

The first substrate1having the first elastic modulus is formed of a material having a higher elastic modulus than the second substrate2having the second elastic modulus. For example, the first substrate1is formed of SiC, and the second substrate2is formed of Si. For this reason, the multilayer film included in the memory cell array11on the first substrate1is less likely to be distorted compared to the case where the memory cell array11is formed on the second substrate2. Thus, the memory cell array11is supported by the surface of the first substrate1, and can maintain an approximately flat state. As a result, the laminate of the semiconductor elements can easily be manufactured while reducing the distortion of the memory cell array11.

In addition, it is difficult to form the peripheral circuit50on the SiC substrate because the yield is deteriorated thereby. Hence, in the manufacturing method for the semiconductor device according to the embodiment, the first semiconductor element6having the memory cell array11formed on the first substrate1, and the first semiconductor element6and the second semiconductor element7are laminated using the bonding technique. Hence, in the manufacturing method for the semiconductor device according to the present embodiment, the memory cell array11can be formed on the first substrate1formed of a material having a higher elastic modulus than the second substrate2, and the peripheral circuit50can be formed on the second substrate2. As a result, it is possible to avoid the deterioration of the yield which would otherwise occur if the peripheral circuit50were formed on the first substrate1having a higher elastic modulus than the second substrate2.

Moreover, after the first semiconductor element6and the second semiconductor element7are laminated, the first substrate1is removed from the first semiconductor element6. The removed first substrate1can be cleaned, and a new insulating layer can thereafter be formed on the first substrate1, and for use in manufacturing a new semiconductor device. Thus, the first substrate1can be reused, and the manufacturing cost can be reduced.

The manufacturing method for the semiconductor device according to the embodiment disclosed herein is merely an example in all respects and should not be construed as being limiting. The embodiments may be modified and improved in various forms without departing from the scope and spirit of the appended claims. The matters described in a plurality of embodiments can be combined within a range not contradictory with one another.

This application is based upon and claims priority to Japanese Patent Application No. 2021-167235, filed on Oct. 12, 2021, the entire contents of which are incorporated herein by reference.

DESCRIPTION OF THE REFERENCE NUMERALS

1: First substrate2: Second substrate3: Insulating layer4: First separation layer5: Second separation layer6: First semiconductor element6a: First bonding surface7: Second semiconductor element7a: Second bonding surface11: Memory cell array50: Peripheral circuitD: Separation layer