Circuit design method to control access pointers of different memory

A circuit design method to control access pointers of different memory used to transfer the data buffer of printers. The proposed control signal circuit employs a read control signal circuit and a write control signal circuit to receive and send m+n-bit control signals, respectively, to control the access pointers of a memory with 2m*2n-register to perform buffer transfer in printers. The disclosed method is able to solve the problem that only one memory block is accessible in sequential mode before. In addition, the method is able to use all memory blocks in buffer transfer in sequential mode to increases the efficiency of data buffering when printing.

BACKGROUND OF THE INVENTION

1. Field of Invention

The invention relates to a method of designing the control signal circuits in a memory, particularly to a method of designing a control signal circuit that is used to perform buffer access in a printer, and is able to control the access pointers according to the transfer mode and improve the buffer processing efficiency in sequential mode when printing.

2. Related Art

Since the computing power of computer-based devices is more than that of printing peripherals (e.g., printers), printing peripherals usually employ several data buffering mechanisms to coordinate the unmatched data transfer speed and computing power between them.

Data buffering mechanisms usually consist of two parts: one is the control signal circuit and the other is the memory. Suppose that a memory consists of four memory blocks and each memory block consists of eight registers. These memory registers can be accessed in different transfer modes (parallel mode or sequential mode) and access modes (read mode or write mode) according to the control signal circuit. In data accessing in parallel mode (shown in FIG.1-a) and sequential mode (shown in FIG.1-b), after receiving a control signal, the prior control signal circuit can only control the access pointers by sending a prior read control signal100or a prior write control signal. As shown in FIG.1-a,in parallel mode, four memory blocks can be accessed simultaneously by a read pointer110and a write pointer220. However, as shown in FIG.1-b,in sequential mode, only one memory block can be accessed at a time with the same access pointers (i.e., the read pointer110and the write pointer220). The design of the control signal circuit has the limitation that the other three memory blocks cannot be accessed as long as one memory block is accessed.

As a result, in sequential mode, the prior designs of the control signal circuits waste a large amount of memory space, and degrade the efficiency of data buffering. It is because of their the bad designs that the control signal circuits cannot manipulate the control signals and access pointers well, and hence, waste memory space and are inefficient in data buffering. In addition, the prior designs limit the arrangement of the memory block and are not able to fulfill the requirements of data buffering. As a consequence, improving the design of the control signal circuits to increase the efficiency of data buffering especially in sequential mode is a crucial issue for control signal circuit designers.

SUMMARY OF THE INVENTION

In view of the above problems, the invention proposes a circuit design method to control access pointers of different memory blocks and a method of accessing pointers of different memory blocks in the circuit design. The proposed method is employed in printers under sequential mode to properly manipulate the access pointers of memory by the improved designs of the memory blocks and registers in the memory and the control signal circuits.

The proposed circuit design method can fully use and control all registers in the memory to improve the efficiency of data buffering and the performance of the printers. In addition, the arrangement of the designs of the control signal circuit and memory block increases the flexibility of the design of the memory block and fulfills the future requirements in the data buffering mechanism.

To achieve the above objects, the proposed circuit design method includes the following steps: retrieving the previous addresses of the read and write pointers, and receiving the control signals of the data source, analyzing the control signals, determining the control signal circuit according to the transfer mode and the access mode, setting the access pointers pointing to the corresponding memory addresses of the memory block control circuit and the register control circuit, and performing the data accesses of the printed data.

The details of the proposed method are described as follows.

DETAILED DESCRIPTION OF THE INVENTION

The invention is related to a circuit design method to control access pointers of different memory, which is a control signal circuit design method mainly employed to perform the data buffering of printers in sequential mode.

FIG. 2shows the control flow of the proposed method in sequential mode. First, the circuit retrieves the previous addresses of the read and the write pointers before accessing the memory block (Step800). The circuit reads the control signals from the data source (Step810), which is usually a hardware component with computing power. Take a central processing unit (referred to as CPU) as an example. When receiving a data printing request from an application, the CPU sends a control signal to the control signal circuit using the disclosed method, wherein the content of the control signal consists of the following three parts: transfer mode (parallel or sequential mode), access mode (read or write mode) and the access number. Then, the circuit analyzes the received control signal to extract the transfer mode, access mode and the access number, and determines a control signal circuit set according to the transfer mode (Step830). A control signal circuit set consists of the following two parts. One is the write control signal circuit, which is able to transmit memory block write control signals550and register write control signals560in sequential mode. The other one is the read control signal circuit, which is able to transmit memory block read control signals500and register read control signals510. When the received control signal is in write mode, the data are written by the write control signal circuit. When the received control signal is in read mode, the data are read by the read control signal circuit. The circuit then transforms the access number from decimal to binary, and moves the corresponding access pointer (the read pointer415or the write pointer) of the control signal circuit set350to the corresponding memory address of the memory block control circuit (r—ptr—f or w—ptr—f) and register control circuit (r—ptr—or w—ptr—) (Step850). Finally, the circuit accesses the printed data in the memory (Step860). The above steps are repeated until the printing job is finished.

Although the invention focuses on the circuit design in sequential mode, it also proposes the design of the control signal circuit set350(being able to transmit read control signals400and write control signals450) in parallel mode. The circuit design also consists of a transfer mode control signal (used to transmit transfer mode control signals300) to determine the control signal circuit set350according to the transfer mode.

FIGS.3-aand3-bshow the control flow of the proposed method working in parallel mode and sequential mode, respectively. These figures are used to describe how to perform buffer transfer.

The proposed control signal circuit consists of the following parts: a transfer mode control signal circuit300, a data access circuit in parallel mode (400and450), and a data access circuit in sequential mode (comprising data read control signal circuits400and510, and data write control signal circuit550and560). As shown in FIG.3-a,in parallel mode, the transfer mode control signal circuit activates the data access circuit in parallel mode and performs parallel data accessing. On the other hand, as shown in FIG.3-b,in sequential mode, the transfer mode control signal circuit activates the data access circuit in sequential mode and performs data accessing sequentially.

The cooperation of the proposed designs of the control signal circuit and the memory block is as follows. Suppose that the proposed circuit cooperates with 2mmemory blocks and each block consists of 2nregisters. After extraction, each control signal contains an (m+n)-bit binary number, where the most significant m bits indicate a block and the other n bits indicate a register in the block.

FIGS.4-aand4-bare used to describe the association between the control signal circuit and the memory. After extraction, each control signal contains an (m+n)-bit binary number, where the most significant m bits600indicate a block and the other n bits700indicate a register in the block. Hence, the memory must have 2mmemory blocks, and each block must have 2nregisters (as shown in FIG.4-a). FIG.4-bshows two examples with m+n=5 and (m, n)=(2, 3), and m+n=7 and (m, n)=(3, 4), respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG.1-ashows the control flow of the prior circuit design in parallel mode.

FIG.1-bshows the control flow of the prior circuit design in sequential mode.

FIG. 2shows the control flow of the proposed method.

FIG.3-ashows an execution scenario of the proposed method in parallel mode.

FIG.3-bshows an execution scenario of the proposed method in sequential mode.

FIGS.4-aand4-bshow the association between the proposed control signal circuit and the memory block.