Liquid crystal display with multi-frame inverting function and an apparatus and a method for driving the same

A liquid crystal display (LCD) device, can include a timing controller with a multiframe inversion driving portion for modulating an REV signal that designates a polarity of a data voltage for switching the polarity of liquid crystals on an LCD panel with respect to a common electrode voltage, thereby generating a modulated REV signal; a gate driver generates a gate driving voltage; a data driver for generating a data driving voltage based on the modulated REV signal received from the timing controller; and an LCD panel repeats an inversion drive in a period of p frames based on the gate driving voltage and the data driving voltage, the inversion being shifted down by every line in a period of one frame according to a change in the frame.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a liquid crystal display (LCD) device, and an apparatus and method for driving the same. More specifically, the present invention relates to an LCD having a multiframe inverting function, and an apparatus and method for driving the same.

(b) Description of the Related Art

As personal computers or televisions have recently become more light-weighted and thinner, LCDs are required to have smaller weight and thickness. For this reason, flat panel type display devices such as LCD are used as a substitute for a cathode ray tube (CRT) and put to practical uses in various applications.

LCD is a display device in which electric field is supplied to a liquid crystal material having an anisotropic dielectric constant between two substrates and controlled to regulate the amount of light passing through the substrates, thereby generating a desired image signal.

LCD is a representative of portable flat-panel type display devices, among which TFT (Thin Film Transistor)-LCD using an array of TFTs as a switching element is most widely used.

Typically, LCD includes a plurality of gate lines for transmitting a scanning signal, a plurality of data lines intersecting the gate lines and transmitting image data, and a plurality of pixels each formed at a region surrounded by the gate lines and the data lines and connected to the gate lines and the data lines via switching elements in the matrix form.

In the LCD, image data are supplied to the individual pixels as follows.

First, a gate-on signal, i.e., scanning signal is sequentially supplied to the gate lines to turn on the switching elements connected to the gate lines in sequence and, simultaneously, to provide image signals to be supplied to pixel rows corresponding to the gate lines, i.e., supply a gradation voltage to the respective data lines. The image signals supplied to the data lines are supplied to the individual pixels via the switching elements turned on. The gate-on signal is sequentially supplied to all gate lines for one frame so as to display an image of one frame.

It is necessary to invert the gradation voltage with respect to a common voltage, because of the problematic characteristic of the liquid crystal material that the liquid crystal material is degraded under the electric field continuously supplied in one direction. Namely, when a signal voltage positive in polarity is supplied to a pixel, a negative signal voltage has to be supplied to the next frame.

For this purpose, the TFT-LCD is inverted on a frame-by-frame basis (in the frame inversion method (FIM)), on a line-by-line basis (in the line inversion method (LIM)), on a column-by-column basis (in the column inversion method (CIM)), or on a pixel-by-pixel basis (in the dot inversion method (DIM)).

These inversion methods make use of the fact that the averaged brightness of the individual dots in a given area is constant because the human eyes recognize different dots at the same time. The methods are so effective in general displays as not to make the users feel inconvenient, but flickering occurs when displaying the same patterns as the inversion methods. Flickering refers to a quality-related characteristic of the picture that appears in the presence of a transmittivity difference between the two polarities in periodically switching the charging polarity of liquid crystals between positive (+) and negative (−) polarities. Flickering occurs when the same voltage cannot be supplied to the individual dots due to RC delay that depends on the length of the panel, because the individual dots are distributed in area and a control voltage for each dot is supplied in one direction.

That is, flickering occurs in the horizontal pattern for line inversion, in the vertical pattern for column inversion, and in the dot pattern for dot inversion, because human eyes recognize these patterns in the same way as the pattern in frame inversion.

It is however still problematic in that the horizontal, vertical and dot patterns are all included in the range of the user screen.

In an attempt to overcome this problem, there is suggested the 2×1 dot inversion method as illustrated inFIG. 2, in which positive (+) and negative (−) voltages are viewed in a pattern included in the range of the user screen to reduce flickering. This method eliminates flickering from all user screens because the user scarcely uses the 2×1 dot screen that shows flickering. The 2×1 dot inversion method may drive the LCD module with the flickering a lot less noticed, but creates blurred horizontal lines in the screen due to a difference in the charging rate between the odd and even lines.

For example, when the data voltage wavelength is input in the form of pulses with a four-line period, the head of the waveform is delayed due to resistance and capacitance of the data lines, which leads to a delay of the pixel voltage corresponding to the odd lines.

The pixel voltage corresponding to the even lines is also delayed in the next frame for the same reason except that the voltage is in a low state.

The reasons why the head of the waveform is delayed are also considered as that the gate waveform is recognized differently from even lines to odd lines in correlation with data when the waveform varies due to the RC delay of the gate lines, and that the pixel voltage at the head of the waveform differs from odd lines to even lines in connecting an auxiliary capacitance Cst to the gate of the head to drive the auxiliary capacitance.

For these reasons, horizontal lines are created in displaying a screen with an intermediate gradation brightness, which eventually deteriorates the quality of the image.

SUMMARY OF THE INVENTION

It is a first object of the present invention to solve the problem and to provide an LCD having a multiframe inverting function that reduces flickering and horizontal lines in driving a single bank type LCD.

It is a second object of the present invention to provide an LCD having a multiframe inverting function that reduces flickering and horizontal lines in driving a dual bank type LCD.

It is a third object of the present invention to provide an apparatus for driving an LCD having a multiframe inverting function that reduces flickering and horizontal lines in driving a single bank type LCD.

It is a fourth object of the present invention to provide an apparatus for driving an LCD having a multiframe inverting function that reduces flickering and horizontal lines in driving a dual bank type LCD.

It is a fifth object of the present invention to provide a method for driving an LCD having a multiframe inverting function that reduces flickering and horizontal lines in driving a single bank type LCD.

It is a sixth object of the present invention to provide a method for driving an LCD having a multiframe inverting function that prevent flickering and horizontal lines in driving a dual bank type LCD.

In one aspect of the present invention to achieve the first object, there is provided an LCD having a multiframe inversion function, which performs an inversion drive of every frame to be opposite in polarity to the previous one, the LCD including: a timing controller having a multiframe inversion driving portion for modulating a reversal (REV) signal that designates a polarity of a data voltage for switching the polarity of liquid crystals on an LCD panel with respect to a common electrode voltage, thereby generating a modulated REV signal; a gate driver for generating a gate driving voltage; a data driver for generating a data driving voltage based on the modulated REV signal received from the timing controller; and an LCD panel having a plurality of gate lines for transferring scanning signals, a plurality of data lines intersecting the gate lines for transferring image signals, a plurality of switching elements each formed in an area surrounded by the gate lines and the data lines and connected to the gate lines and the data lines, and a plurality of dot electrodes connected to the switching elements and operable in response to the operations of the switching elements, wherein the inversion drive repeats in a period of p frames based on the gate driving voltage and the data driving voltage (where p is an integer equal to or greater than 4), the inversion being shifted down by every line in a period of one frame according to a change in the frame.

In another aspect of the present invention to achieve the second object, there is provided an LCD having a multiframe inversion function, which performs an inversion drive of every frame to be opposite in polarity to the previous one, the LCD including: a timing controller having a multiframe inversion driving portion for modulating a REV signal that designates a polarity of a data voltage supplied to an LCD panel, individually every odd/even column, and generating a modulated odd REV signal and a modulated even REV signal designating the polarities of odd and even data voltages, respectively; a gate driver for generating a gate driving voltage; a data driver for generating a data driving voltage based on the modulated odd and even REV signals received from the timing controller; and an LCD panel having a plurality of gate lines for transferring scanning signals, a plurality of data lines intersecting the gate lines for transferring image signals, a plurality of switching elements each formed in an area surrounded by the gate and data lines and connected to the gate and data lines, and a plurality of dot electrodes connected to the switching elements and operable in response to the operations of the switching elements, wherein the inversion drive repeats in a period of p frames based on the gate driving voltage and the data driving voltage (where p is an integer equal to or greater than 4), the inversion being shifted down by every line in a period of q frames according to a change in the frame, wherein q is less than p.

In still another aspect of the present invention to achieve the third object, there is provided an apparatus for driving an LCD having a multiframe inversion function, which includes a plurality of pixels arranged in a matrix form having a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a plurality of switching elements each formed in an area surrounded by the gate and data lines and connected to the gate and data lines, the apparatus including: a timing controller having a multiframe inversion driving portion for modulating an REV signal that designates a polarity of a data voltage for switching the polarity of liquid crystals on an LCD panel of the LCD with respect to a common electrode voltage, thereby generating a modulated REV signal; a gate driver for generating a gate driving voltage; and a data driver for generating a data driving voltage based on the modulated REV signal received from the timing controller.

In further another aspect of the present invention to achieve the fourth object, there is provided an apparatus for driving an LCD having a multiframe inversion function, which includes a plurality of pixels arranged in a matrix form having a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a plurality of switching elements each formed in an area surrounded by the gate line and the data lines and connected to the gate line and the data lines, the apparatus including: a timing controller having a multiframe inversion driving portion for modulating a REV signal that designates a polarity of a data voltage supplied to an LCD panel of the LCD, individually every odd/even column, and generating a modulated odd REV signal and a modulated even REV signal designating the polarities of odd and even data voltages, respectively; a gate driver for generating a gate driving voltage; and a data driver for generating a data driving voltage based on the modulated odd and even REV signals received from the timing controller.

In still further another aspect of the present invention to achieve the fifth object, there is provided a method for driving an LCD having a multiframe inversion function, which includes a plurality of pixels arranged in a matrix form having a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a plurality of switching elements each formed in an area surrounded by the gate lines and the data lines and connected to the gate lines and the data lines, the method including the steps of: (a) sequentially applying a scanning signal to the gate lines; (b) modulating an REV signal that designates a polarity of a data voltage for switching the polarity of liquid crystals on an LCD panel of the LCD with respect to a common electrode voltage, thereby generating a modulated REV signal; (c) generating a data driving voltage based on the modulated REV signal; and (d) applying the data driving voltage to the data lines.

In still further another aspect of the present invention to achieve the sixth object, there is provided a method for driving an LCD having a multiframe inversion function, which includes a plurality of pixels arranged in a matrix form having a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a plurality of switching elements each formed in an area surrounded by the gate lines and the data lines and connected to the gate lines and the data lines, the method including the steps of: (a) sequentially applying a scanning signal to the gate lines; (b) modulating a REV signal that designates a polarity of a data voltage supplied to an LCD panel of the LCD, individually every odd/even column, thereby generating a modulated odd REV signal and a modulated even REV signal designating the polarities of odd and even data voltages, respectively; (c) generating a data driving voltage based on the modulated REV signal; and (d) applying the data driving voltage to the data lines.

According to the LCD having a multiframe inversion function and a driving apparatus and method thereof, there can be removed flickering caused by dot inversion and horizontal lines from 2×1 dot inversion in driving the LCD.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3is a diagram of an LCD having a multiframe inverting function in accordance with a first embodiment of the present invention, i.e., a single bank type LCD having a multiframe inverting function.

Referring toFIG. 3, the LCD having a multiframe inverting function in accordance with the first embodiment of the present invention includes a timing controller100, a data driver200, a driving voltage generator300, a gate driver400, and an LCD panel500.

The timing controller100receives, from an external graphic controller (not shown) of the LCD module, RGB data, frame-discriminating vertical sync signals Vsync, line-discriminating horizontal sync signals Hsync, main clock signals MCLK, and signals DE that become HIGH only in data output intervals in order to display data entrance areas, and generates digital signals for driving the data driver200and the gate driver400.

More specifically, the timing controller100outputs to the data driver200an instruction signal STH for applying RGB digital signals R(0:N), G(0:N) and B(0:N) from the graphic controller to the data driver200, an instruction signal LP for converting the digital data to the analog form at the data driver200and applying the analog values to the LCD panel500, and a clock signal HCLK for data shift in the data driver200.

The timing controller100also outputs to the gate driver400an instruction signal STV for applying a gate-on signal from the gate driver400to the gate lines in the LCD panel500, and a gate clock signal (CPV: Clock Pulse for a Vertical clock signal) for sequentially applying the gate-on signal to the individual gate lines.

The timing controller100includes a single bank type multiframe inverting driver (not shown). The timing controller100modulates a REV signal that designates the polarity of a data voltage for switching the polarity of liquid crystals on the LCD panel with respect to a common electrode voltage Vcom, and outputs a modulated REV signal REVM to the data driver200.

The modulated REV signal REVM is a modulated signal upon which an inversion drive is carried out in a period of four frames in the LCD and shifted down every line according to a change in the frame.

The data driver200comprises shift register, data register, latch, level shifter, D/A converter, and output buffer, which are not shown in the figure. The data driver200stores the RGB digital signals R(0:N), G(0:N) and B(0:N) received from the timing controller100and, upon receiving the load instruction signal LP, outputs data voltages D1, D2, D3, . . . , and Dmfor transferring selected voltages corresponding to the individual data to the LCD panel500based on the modulated REV signal REVM received from the timing controller100.

More specifically, the D/A converter of the data driver200applies a “high” data voltage to the LCD panel500via the output buffer when the modulated REV signal REVM received from the timing controller100is “high”, or a “low” data voltage to the LCD panel500via the output buffer when the modulated REV signal REVM is “low”.

The driving voltage generator300outputs to the gate driver400a voltage Vonfor generating a gate-on signal, a voltage Vofffor generating a gate-off signal, and a common electrode voltage Vcombeing a reference of the data voltage difference in the TFT'S.

The gate driver400includes a shift register (not shown), a level shifter (not shown) and a buffer (not shown). The gate driver400receives a gate clock signal CPV and a vertical line start signal STV from the timing controller100, and voltages Von, Voffand Vcomfrom the driving voltage generator300, and outputs gate voltages G1, G2, G3, . . . , and Gnto provide a path for applying the corresponding voltage values to the individual pixels on the LCD panel500.

The LCD panel500includes a plurality of gate lines for transferring gate voltages G1, G2, G3, . . . , and Gnas scanning signals received from the gate driver400, a plurality of data lines intersecting the gate lines and transferring data voltages D1, D2, D3, . . . , and Dnas image signals, a plurality of switching elements, i.e., TFT's each formed in an area surrounded by the gate lines and the data lines and connected to the gate and data lines, and a plurality of dot electrodes connected to the switching elements and operable in response to the operation of the switching elements.

The dot electrodes, each indicating any one of RGB dot electrodes, are continuously arranged in the matrix form, preferably, in a continuous array of R, G and B dots. As the gate voltages G1, G2, G3, . . . , and Gnare supplied from the gate driver400to the corresponding pixels, the dot electrodes drive the corresponding RGB dots provided therein in response to data voltages D1, D2, D3, . . . , and Dnfrom the data driver200. The data voltages D1, D2, D3, . . . , and Dnare each output based on the polarity of the modulated REV signal REVM supplied from the timing controller100.

FIG. 4is a diagram explaining a multiframe inversion driving method in accordance with the first embodiment of the present invention.

Referring toFIG. 4, the inversion drive repeats in a period of four frames in contrast to the conventional inversion drive repeating in a period of two frames, and shifts down every one line as the frame changes.

The inversion in each frame occurs in the same manner as the 2×1 dot inversion so as to eliminate flickering that may take place in the dot pattern.

The head and tail of the data voltage waveform are alternately charged by frame, so that the brightness recognized by the observer's eyes is averaged to a constant value in both even lines and odd lines.

The above-described single bank type multiframe inversion driving method overcomes all problems indicated as the causes of the horizontal lines and provides an average brightness over time to prevent a brightness difference between the lines.

FIG. 5is a diagram of a multiframe inversion driving portion in accordance with the first embodiment of the present invention.

Referring toFIG. 5, the multiframe inversion driving portion in accordance with the first embodiment of the present invention includes an REV generator110, a counter120, and a multiplexer130, and outputs a modulated REV signal REVM based on a vertical sync signal Vsync indicating the period of the screen, and a gate clock signal CPV having the same period as the gate pulse width.

More specifically, the REV generator110generates first to fourth REV signals REV1, REV2, REV3and REV4from the vertical sync signal Vsync indicating the period of the screen, and a gate clock signal CPV having the same period as the gate pulse width.

The multiplexer130, preferably, 4×1 multiplexer selects every REV signal received from the REV generator110by period based on the 2-bit switching signals S1and S2to generate a modulated REV signal REVM. Because each of the REV signals repeats in a period of four frames, the vertical sync signal Vsync is processed at the 2-bit counter120and sent to the 4×1 multiplexer130to generate the modulated REV signal REVM in a desired pattern.

Although it has been described that this embodiment uses a 4×1 multiplexer with four inputs multiplexed based on the two-bit switching signals, and one output, it is obvious that an 8×1 multiplexer can be used if the individual REV signals repeat in a period of eight frames. The switching signals used in this case are, of course, 3-bit signals.

The CPV signal can be generated from the signal processors (not shown) of the data driver and the timing controller100that outputs a control signal requested by the data driver, based on a frame-discriminating vertical sync signal Vsync, a line-discriminating horizontal sync signal Hsync, a data enable signal DE, which is “high” only in a data output interval, and a clock signal.

The vertical sync signal Vsync can be externally supplied from the timing controller100, preferably directly from the graphic controller, or generated based on the data enable signal DE.

FIG. 6is a diagram of the REV generator shown inFIG. 5, andFIG. 7is a waveform diagram of a multiframe inversion driving signal in accordance with the first embodiment of the present invention.

Referring toFIG. 6, the REV generator110according to the first embodiment of the present invention comprises first, second and third D flipflops112,114and116.

Now, a description will be given as to the operation of the REV generator according to the first embodiment of the present invention with reference toFIGS. 6 and 7.

First, the three D flipflops112,114and116are initialized based on the vertical sync signal Vsync, and the CPV signal is used to generate a waveform RVS1as in the dot inversion and a waveform RVS2as in the 2×1 dot inversion.

A first REV signal REV1has the same waveform as a second REV signal RVS2as shown inFIG. 7, and the second REV signal REV2is formed from the first REV signal REV1received via the third D flipflop116. A third REV signal REV3, i.e., an inverted waveform of the first REV signal REV1is output at /Q of the second D flipflop114, while a fourth REV signal REV4, i.e., an inverted waveform of the second REV signal REV2is output at /Q of the third D flipflop116.

As described above, the first embodiment of the present invention performs a multiframe inversion driving process to prevent flickering in the dot pattern as well as horizontal lines that may be created during the 2×1 dot inversion.

FIG. 8is a diagram of an LCD having a multiframe inverting function in accordance with a second embodiment of the present invention, i.e., a double bank type LCD having a multiframe inverting function.

Referring toFIG. 8, the LCD having a multiframe inverting function in accordance with the second embodiment of the present invention includes a timing controller600, a data driver700, a driving voltage generator300, a gate driver400, and an LCD panel800.

The timing controller600receives, from an external graphic controller (not shown) of the LCD module, RGB data, frame-discriminating vertical sync signals Vsync, line-discriminating horizontal sync signals Hsync, main clock signals MCLK, and signals DE that become HIGH only in data output intervals in order to display data entrance areas, and generates digital signals for driving the data driver700and the gate driver400.

More specifically, the timing controller600outputs to the data driver700an instruction signal STH for applying RGB digital signals R(0:N), G(0:N) and B(0:N) from the graphic controller to the data driver700, an instruction signal LP for converting the digital data to the analog form at the data driver700and applying the analog values to the LCD panel800, and a clock signal HCLK for data shift in the data driver700.

The timing controller600also outputs to the gate driver400an instruction signal STV for applying a gate-on signal from the gate driver400to the gate lines in the LCD panel800, and a gate clock signal CPV for sequentially applying the gate-on signal to the individual gate lines.

The timing controller600includes a dual bank type multiframe inverting driver (not shown). The timing controller600modulates, separately for even lines and odd lines, REV signals that designate the polarity of a data voltage for switching the polarity of liquid crystals on the LCD panel with respect to a common electrode voltage Vcom, and outputs modulated even REV signals REVM_E and modulated odd REV signals REVM_O to the data driver700.

The modulated odd REV signal REVM_O and the modulated even REV signals REVM_E are modulated signals upon which an inversion drive is carried out on the LCD for a period of four frames and shifted to the right side every column when switching from the first frame to the second one, every pixel as in the dot inversion method when switching from the second frame to the third one, and every column when switching from the third frame to the fourth one.

The data driver700comprises a first data driver710that outputs odd data voltages D1, D3, D5, . . . , and Dm-1., and a second data driver720that outputs even data voltages D2, D4, D6, . . . , and Dm(where m is an even number). The data driver700stores the RGB digital signals R(0:N), G(0:N) and B(0:N) received from the timing controller600and, upon receiving the load instruction signal LP, outputs odd data voltages D1, D3, D5, . . . , and Dm-1and even data voltages D2, D4, D6, . . . , and Dm(wherein m is an even number) for transferring selected voltages corresponding to the individual data to the LCD panel800based on the modulated odd REV signals REVM_O and the modulated even REV signal REVM_E received from the timing controller600.

The first data driver710and the second data driver720include shift register, data register, latch, level shifter, D/A converter, and output buffer, which are not shown in the figure.

More specifically, the D/A converter of the first data driver710applies a “high” data voltage to the LCD panel800via the output buffer when the modulated odd REV signal REVM_O received from the timing controller600is “high”, or a “low” data voltage to the LCD panel800via the output buffer when the modulated odd REV signal REVM_O is “low”.

The D/A converter of the second data driver720applies a “high” data voltage to the LCD panel800via the output buffer when the modulated even REV signal REVM_E received from the timing controller600is “high”, or a “low” data voltage to the LCD panel800via the output buffer when the modulated even REV signal REVM_E is “low”.

The driving voltage generator300outputs to the gate driver400a voltage Vonfor generating a gate-on signal, a voltage Vofffor generating a gate-off signal, and a common electrode voltage Vcombeing a reference of the data voltage difference in the TFT's.

The gate driver400includes a shift register, a level shifter and a buffer. The gate driver400receives a gate clock signal CPV and a vertical line start signal STV from the timing controller600, and voltages Von, Voffand Vcomfrom the driving voltage generator300, and outputs gate voltages G1, G2, G3, . . . , and Gnto provide a path for applying the corresponding voltage values to the individual pixels on the LCD panel800.

The LCD panel800includes a plurality of gate lines for transferring gate voltages G1, G2, G3, . . . , and Gnas scanning signals received from the gate driver400, a plurality of data lines intersecting the gate lines and transferring odd data voltages D1, D3, D5, . . . , and Dm-1and even data voltages D2, D4, D6, . . . , and Dm(where m is an even number) as image signals, a plurality of switching elements, i.e., TFT's each formed in an area surrounded by the gate lines and the data line and connected to the gate lines and the data lines, and a plurality of dot electrodes connected to the switching elements and operable in response to the operation of the switching elements.

The dot electrodes, each indicating any one of RGB dot electrodes, are continuously arranged in the matrix form, preferably, in a continuous array of R, G and B dots. As the gate voltages G1, G2, G3, . . . , and Gnare supplied from the gate driver400to the corresponding pixels, the dot electrodes drive the corresponding RGB dots provided therein in response to odd data voltages D1, D3, D5, . . . , and Dm-1from the first data driver710of the data driver700and even data voltages D2, D4, D6, . . . , and Dmfrom the second data driver720of the data driver700. The odd data voltages D1, D3, D5, . . . , and Dm-1and the even data voltages D2, D4, D6, . . . , and Dmare output based on the polarities of the modulated odd REV signal REVM_O and the modulated even REV signal REVM_E supplied from the timing controller600, respectively.

FIG. 9is a diagram explaining a multiframe inversion driving method in accordance with the second embodiment of the present invention.

Referring toFIG. 9, the inversion drive repeats in a period of four frames in contrast to the conventional inversion drive repeating in a period of two frames, and shifted down every line according to the change in the frame.

More specifically, the inversion shifts to the right side every column when switching from the first frame to the second one, every pixel as in the dot inversion method when switching from the second frame to the third one, and every column when switching from the third frame to the fourth one.

The inversion in each frame occurs in the same manner as the 2×1 dot inversion so as to eliminate flickering that may take place in the dot pattern.

The head and tail of the data voltage waveform are alternately charged by two frames, so that the brightness recognized by the observer's eyes is averaged to a constant value in both even lines and odd lines.

The above-described dual bank type multiframe inversion driving method overcomes all problems indicated as the causes of the horizontal lines and provides an average brightness over time to prevent a brightness difference between the lines.

FIG. 10is a diagram of a multiframe inversion driving portion in accordance with the second embodiment of the present invention.

Referring toFIG. 10, the multiframe inversion driving portion in accordance with the second embodiment of the present invention includes an REV generator610, a counter620, a first multiplexer630and a second multiplexer640, and outputs modulated odd REV signal REVM_O and modulated even REV signal REVM_E based on a vertical sync signal Vsync indicating the period of the screen, and a gate clock signal CPV having the same period as the gate pulse width.

More specifically, the REV generator610generates first to fourth REV signals REV1, REV2, REV3and REV4from the vertical sync signal Vsync indicating the period of the screen, and a gate clock signal CPV having the same period as the gate pulse width.

The counter620, preferably, 2-bit counter outputs 2-bit switching signals S1and S2to the first and second multiplexers630and640.

The first multiplexer630, preferably, 4×1 multiplexer selects the individual REV signals REV1, REV2, REV3and REV4from the REV generator610by period based on the 2-bit switching signals S1and S2to generate modulated odd REV signals REVM_O.

The second multiplexer640, preferably, 4×1 multiplexer selects the individual REV signals REV1, REV2, REV3and REV4from the REV generator610by period based on the 2-bit switching signals S1and S2to generate modulated even REV signals REVM_E.

Because each of the REV signals repeat in a period of four frames, the vertical sync signal Vsync is processed at the 2-bit counter620and sent to the 4×1 multiplexers630and640to generate the modulated REV signals in a desired pattern.

In the dual bank type system, the odd and even REV signals are output as presented in Table 1.

Although it has been described that this embodiment uses a 4×1 multiplexer with four inputs multiplexed based on the two-bit switching signals, and one output, it is obvious that an 8×1 multiplexer may also be used if the individual REV signals repeat in a period of eight frames. The switching signals used in this case are, of course, 3-bit signals.

The CPV signal can be generated from the signal processors (not shown) of the data driver and the timing controller600that outputs a control signal requested by the data driver, based on a frame-discriminating vertical sync signal Vsync, a line-discriminating horizontal sync signal Hsync, a data enable signal DE, which is “high” only in a data output interval, and a clock signal.

The vertical sync signal Vsync can be externally supplied from the timing controller600, preferably directly from the graphic controller, or generated based on the data enable signal DE.

FIG. 11is a diagram of the REV generator shown inFIG. 10, andFIG. 12is a waveform diagram of a multiframe inversion driving signal in accordance with the second embodiment of the present invention.

Referring toFIG. 11, the REV generator610according to the second embodiment of the present invention comprises first, second and third D flipflops612,614and616.

Now, a description will be given as to the operation of the REV generator according to the second embodiment of the present invention with reference to FIGS.11and12.

First, the three D flipflops612,614and616are initialized based on the vertical sync signal Vsync, and the CPV signal is used to generate a waveform RVS1as in the dot inversion and a waveform RVS2as in the 2×1 dot inversion.

A first REV signal REV1has the same waveform of a second REV signal RVS2as shown inFIG. 12, and the second REV signal REV2is formed from the first REV signal REV1received via the third D flipflop616. A third REV signal REV3, i.e., an inverted waveform of the first REV signal REV1is output at /Q of the second D flipflop614, while a fourth REV signal REV4, i.e., an inverted waveform of the second REV signal REV2is output at /Q of the third D flipflop616.

As described above, the second embodiment of the present invention independently processes odd REV signals REV_O for determining the polarity of the odd data lines and even REV signals REV_E for determining the polarity of the even data lines to more effectively enhance the flicker performance.

As described above, the present invention can remove flickering in driving a single/dual bank type LCD by the dot inversion method.

The present invention can also remove horizontal lines in driving a single/dual bank type LCD by the 2×1 dot inversion method.