Semiconductor device having IGBT and diode

A semiconductor device in which both an IGBT element region and a diode element region exist in the same semiconductor substrate includes a low lifetime region, which is formed in at least a part of a drift layer within the diode element region and shortens the lifetime of holes. A mean value of the lifetime of holes in the drift layer that includes the low lifetime region is shorter within the IGBT element region than within the diode element region.

INCORPORATION BY REFERENCE

The disclosure of Japanese Patent Application No. 2008-123618 filed on May 9, 2008 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a reverse conducting semiconductor device in which both an insulated gate bipolar transistor (IGBT) element region and a diode element region are provided in the same semiconductor substrate.

2. Description of the Related Art

Reverse conducting semiconductor devices exist in which both a region where an insulated gate bipolar transistor (IGBT) is formed (IGBT element region) and a region where an free wheel diode (FWD) is formed (diode element region) exist in the same semiconductor substrate. Because two kinds of elements exist in reverse conducting semiconductor devices, it is difficult to form an optimal structure for both of the elements in the same semiconductor substrate. Japanese Patent Application Publication No. 2005-317751 suggests that the recovery loss when the diode is shifted from a conductive state to a non-conductive state is greater in a reverse conducting semiconductor device than in IGBT and the diode formed in separate substrates. To overcome this problem, a semiconductor device100(seeFIG. 14attached to the present application) described in JP-A-2005-317751 includes a low lifetime layer161. Below, the structure and operation of the semiconductor device100will be described.

The semiconductor device100includes an n−-type layer160that extends across both an IGBT element region J101and a diode element region J102. The n−-type layer160serves as a drift layer in the IGBT element region J101. In addition, the n−-type layer160serves as an n−-type cathode layer (high-resistance layer) in the diode element region J102. In this specification, the drift layer and the high-resistance layer will be generically referred to as drift layer. Hereinafter, the n−-type layer160will be referred to as drift layer160. The low lifetime layer161is formed at the intermediate depth of the n−-type layer160. The low lifetime layer161is formed by bombarding a lifetime killer (such as helium) from the front surface102aof a semiconductor substrate102. The low lifetime layer161extends across the drift layer160in the IGBT element region J101and the drift layer160in the diode element region J102. In the low lifetime layer161, the lifetime of minority carriers (holes) is short.

When a voltage higher than that applied to a back-surface electrode103is applied to a front-surface electrode101of the semiconductor device100, holes flow out from a high-concentration p-type region122that is formed to face the front surface102aof the semiconductor substrate102. The holes are injected into the drift layer160via a low-concentration p-type layer130. Also, electrons flow out from a cathode region170that is formed to face a back surface102bof the diode element region J102, and are injected into the drift layer160. Electric current flows between the anode and the cathode (between the high-concentration p-type region122and the cathode region170), so that the diode element region J102is shifted into a conductive state. When the voltage to the front-surface electrode101falls below the voltage to the back-surface electrode103, holes are no longer injected from the high-concentration p-type region122into the drift layer160. The diode element region J102is thus shifted into a non-conductive state.

As the diode element region J102is shifted from a conductive state to a non-conductive state, a phenomenon occurs in which the holes injected into the drift layer160return to the low-concentration p-type layer130. As a result, recovery current flows in the diode element region J102in a direction opposite from that when conductive. When the recovery current flows, loss occurs, and the diode element region J102generates heat. The semiconductor device100includes the low lifetime layer161. Some of the holes that return to the low-concentration p-type layer130at the time of a recovery operation are lost in the low lifetime region161. The provision of the low lifetime layer161makes it possible to reduce the recovery current in the diode element region J102, thus enabling reduction in recovery loss in the diode element region J102.

When the reverse conducting semiconductor device described in JP-A-2005-317751 is used, it is possible to reduce recovery loss in the diode element region J102. However, in the IGBT element region J101, this is likely to adversely affect the conductivity modulation phenomenon when the low lifetime layer161is in an ON state, thereby increasing the voltage in the IGBT element region J101.

SUMMARY OF THE INVENTION

The present invention provides a reverse conducting semiconductor device in which both an IGBT element region and a diode element region are provided in the same semiconductor substrate, and that reduces the recovery loss in the diode element region without increasing the ON-state voltage in the IGBT element region.

An aspect of the present invention relates to a reverse conducting semiconductor device in which both an IGBT element region and a diode element region are formed on the same semiconductor substrate. This semiconductor device includes: a p-type collector layer, an n-type drift layer, and a p-type body layer that are laminated in order in the IGBT element region; a trench gate electrode that extends through the body layer from a front surface of the body layer to project into the drift layer; an insulating film that surrounds the trench gate electrode; an n-type emitter region that is in contact with the insulating film and is formed in an area facing the front surface of the body layer, in which the emitter region is separated from the drift layer by the body layer; an n-type cathode layer, the drift layer, and a p-type anode layer that are laminated in order in the diode element region; an anode region that is formed in an area that faces a front surface of the anode layer, and contains a p-type impurity at higher concentration than in the anode layer, in which the anode region is separated from the drift layer by the anode layer; and a low lifetime region that is formed in at least a part of the drift layer within the diode element region, and shortens a lifetime of a hole. A mean value of a lifetime of a hole in the drift layer that includes the low lifetime region is shorter within the diode element region than within the IGBT element region.

According to the above-mentioned semiconductor device, the low lifetime region is provided in at least a part of the drift layer within the diode element region. Thus, at the time of a recovery operation in which the diode element region is shifted from a conductive state to a non-conductive state, some of the holes that return to the anode layer are lost in the low lifetime region. This makes it possible to reduce recovery current in the diode element region, thus enabling reduction in recovery loss in the diode element region. Also, in the above-mentioned semiconductor device, the mean value of the lifetime of a hole in the drift layer that includes the low lifetime region is shorter within the IGBT element region than within the diode element region. In the IGBT element region, the holes that exist in the drift layer when the IGBT element region is in the ON state are not easily lost, and conductivity modulation is actively performed. Thus, the ON-state voltage in the IGBT element region does not increase. According to the above-mentioned semiconductor device, recovery loss in the diode element region can be reduced without increasing the ON-state voltage in the IGBT element region.

According to the present invention, recovery loss in the diode element region can be reduced without increasing the ON-state voltage in the IGBT element region.

DETAILED DESCRIPTION OF EMBODIMENTS

The main features of a semiconductor device according to an embodiment of the present invention, which will be described in the following, are listed below. A low lifetime region of the semiconductor device is formed at least within a drift layer near the boundary between an anode layer and the drift layer. After a resist is formed on an area of the front surface of a semiconductor layer that is to become an IGBT element region of the semiconductor device, a non-conductive impurity is implanted from the front surface side. The acceleration voltage at the time when the non-conductive impurity is implanted from the front surface side is set in such a way that the peak of the concentration of the non-conductive impurity to be implanted occurs within the drift layer near the boundary between the anode layer and the drift layer.

FIG. 1is a sectional view of the main portion of a reverse conducting semiconductor device1in which an IGBT element region J1and a diode element region J2coexist in a semiconductor layer2. The semiconductor device1includes the semiconductor layer2made of silicon, a back-surface electrode3formed on a back surface2bof the semiconductor layer2, and a front-surface electrode5formed on a front surface2aof the semiconductor layer2.

The back-surface electrode3extends continuously on the back surface of the IGBT element region J1and on the back surface of the diode element region J2. The semiconductor layer2includes a shallow portion2U and a deep portion2L. The deep portion2L includes a p+-type collector region80and an n+-type cathode region70. The collector region80is formed in an area of the back surface2bof the semiconductor layer2that is coextensive with the IGBT element region J1. The cathode region70is formed in an area of the back surface2bthat is coextensive with the diode element region J2. The back-surface electrode3described above is connected to the collector region80and the cathode region70. Also, the deep portion2L includes an n−-type drift layer60that is formed on top of the collector region80and the cathode region70.

A plurality of trenches T are formed in the shallow portion2U of the semiconductor layer2. Each trench T extends with its longitudinal direction aligned along a depth direction shown inFIG. 1. Also, each trench T extends from the front surface2aof the semiconductor layer2in a depth direction of the semiconductor layer2. A trench gate electrode12is received within the trench T while being surrounded by an insulating film14. The shallow portion2U is partitioned into a plurality of partitioned regions4by pairs of successive trenches T.

The same semiconductor structure is formed in each partitioned region4. The partitioned region4includes a low-concentration p-type layer30, an n+-type trench-adjoining region20, and a high-concentration p-type region22. The low-concentration p-type layer30is formed across successive trenches T. The n+-type trench-adjoining region20is exposed on a part of the front surface2aof the semiconductor layer2. The trench-adjoining region20contacts the trench T. Therefore, the trench-adjoining region20faces the trench gate electrode12via the insulating film14. The high-concentration p-type region22is exposed on the other part of the front surface2aof the semiconductor layer2. The high-concentration p-type region22is placed between successive trench-adjoining regions20. In the partitioned region4, the trench-adjoining region20and the high-concentration p-type region22are separated from the n−-type drift layer60by the low-concentration p-type layer30. In this embodiment, the IGBT element region J1and the diode element region J2are common both share the same n-type drift layer60, so both the drift layers60will be generically referred to as drift layers.

In the IGBT element region J1, the low-concentration p-type layer30serves as a body region. In the IGBT element region J1, the trench-adjoining region20serves as an emitter region. In the IGBT element region J1, the high-concentration p-type region22serves as a body contact region. In the diode element region J2, the low-concentration p-type layer30serves as a low-concentration anode layer. In the diode element region J2, the high-concentration p-type region22serves as an anode region.

Further, the diode element region J2includes a low lifetime region61that is formed in at least a part of the region of the drift layer60. In the semiconductor device1shown inFIG. 1, the low lifetime region61is formed within the drift layer60near the boundary between the drift layer60and the low-concentration p-type layer30. The low lifetime region61is formed in an area shallower than the deepest portion of the trench T. The low lifetime region61extends across successive trenches T.

In comparison to the other region of the drift layer60excluding the low lifetime region, the concentration of carbon C (an example of non-conductive impurities) and oxygen O (an example of non-conductive impurities) is high in the low lifetime region61. Carbon C and oxygen O are coupled in between lattices of silicon that form the semiconductor layer2. In regions with a high content of couplings of carbon C and oxygen O, the lifetime of holes is short. In the semiconductor device1, the lifetime of holes in the low lifetime region61is shorter than the lifetime of holes in the drift layer60within the IGBT element region J1at the same depth as the low lifetime region61. The drift layer60is common to the IGBT element region J1and the diode element region J2, while the low lifetime region61is not formed in the drift layer60in the IGBT element region J1. Therefore, the average lifetime of holes in the drift layer60that includes the low lifetime region61is shorter in the diode element region J2than in the IGBT element region J1.

The front-surface electrode5that is formed on the front surface2aof the semiconductor layer2extends continuously on the front surface of the IGBT element region J1and on the front surface of the diode element region J2. In the IGBT element region J1, the front-surface electrode5is in electrical conduction with the trench-adjoining region (emitter region)20and the high-concentration p-type region (body contact region)22. Also, in the diode element region J2, the front-surface electrode5is in electrical conduction with the trench-adjoining region20and the high-concentration p-type region (anode region)22. An insulating film10is formed between the trench gate electrode12and the front-surface electrode5, and the two electrodes are not connected to each other. The trench gate electrode12is connected to gate wiring (not shown) in a region where the front-surface electrode5is not formed.

With the above configuration, the semiconductor device1that serves as a reverse conducting IGBT is formed. The semiconductor device1serves as a circuit in which a diode that is formed by the diode element region J2is connected in anti-parallel between a pair of main electrodes (between a collector and an emitter) of an IGBT that is formed by the IGBT element region J1.

Referring toFIG. 2, the operation of the semiconductor device1when a higher voltage is applied to the back-surface electrode3than to the front-surface electrode5of the semiconductor device1and when a gate voltage G (gate-ON voltage) that is equal to or higher than a threshold value is applied to the trench gate electrode12will be described. In this case, in both the IGBT element region J1and the diode element region J2, the low-concentration p-type layer30that is on the opposite side of the insulating film14from the trench gate electrode12is inverted to n-type to form n-type channels. InFIG. 2, the n-type channels are illustrated as cross marks. Thus, electrons flowing out from the trench-adjoining region20are injected into the drift layer60via the n-type channels. InFIG. 2, the electrons are illustrated as minus marks. As a result, holes move from the collector region80of the IGBT element region J1toward the drift layer60. InFIG. 2, the holes are illustrated as plus marks. A conductivity modulation phenomenon occurs as the electrons and holes are injected into the drift layer60, and the IGBT element region J1is shifted into an ON state with a low ON-state voltage. As indicated by a thick arrow inFIG. 2, current flows from the back-surface electrode3to the front-surface electrode5.

Referring toFIG. 3, the operation of the semiconductor device1when a higher forward voltage is applied to the front-surface electrode5than to the back-surface electrode3of the semiconductor device1will be described. A gate-ON voltage is not applied to the trench gate electrode12. In this case, in both the diode element region J2and the IGBT element region J1, holes flow out from the high-concentration p-type region22to the drift layer60via the low-concentration p-type layer30. On the other hand, electrons move from the n+-type cathode region70toward the drift layer60. The diode element region J2is thus shifted into a conductive state. As indicated by a thick arrow inFIG. 3, a current flows from the front-surface electrode5to the back-surface electrode3.

Thereafter, when the voltage to the front-surface electrode5is set lower than the voltage to the back-surface electrode3, holes no longer flow out from the high-concentration p-type region22to the drift layer60. Thus, the diode element region J2is shifted into a non-conductive state. As the diode element region J2is shifted from a conductive state to a non-conductive state, the holes injected into the drift layer60try to return to the low-concentration p-type layer30. Due to this phenomenon, in the diode element region J2, a recovery current tries to flow in a direction that is opposite to the direction in the conductive state (direction opposite to that indicated by the thick arrow inFIG. 3). The semiconductor device1according to this embodiment includes the low lifetime region61in the drift layer60within the diode element region J2. Thus, some of the holes that return to the low-concentration p-type layer30are lost in the low lifetime region61at the time of a recovery operation. This reduces the recovery current in the diode element region J2, thus enabling a reduction in recovery loss in the diode element region J2.

In the semiconductor device1according to this embodiment, the low lifetime region61is not formed in the IGBT element region J1. In the IGBT element region J1, the holes present in the drift layer60when the IGBT element region J1is in the ON state are not easily lost, and conductivity modulation is actively performed. The ON-state voltage in the IGBT element region J1is low as in a case in which the low lifetime region61is not formed. According to the semiconductor device1of this embodiment, recovery loss is reduced without increasing the ON-state voltage in the IGBT element region J1.

Next, a method of manufacturing the semiconductor device1will be described with reference toFIGS. 4 to 13. As shown inFIG. 4, first, the n-type semiconductor layer2is prepared. Boron, a p-type impurity, is implanted from the front surface2a(implantation condition: the amount of implantation per unit area is set to about 3×1013cm−2). Thereafter, with heat treatment for 40 minutes at 1,150° C., the implanted boron is activated, and the low-concentration p-type layer30shown inFIG. 4is formed. The n−-type semiconductor layer2, that is located below the low-concentration p-type layer30serves as the drift layer60.

Next, as shown inFIG. 5, an oxide film having a thickness of 300 nm is formed on the front surface2avia chemical vapor deposition (CVD). An opening is formed in an area where the trench T is to be formed to make a mask M1. Etching is applied from the portion of the front surface2a, which is exposed at the opening of the mask M1, to the low-concentration p-type layer30and a part of the drift layer60(about 6 μm from the front surface2a). This forms the plurality of trenches T that extends through the low-concentration p-type layer30from the front surface2aand projects into the drift layer60. Then, the mask M1is removed by wet etching.

Next, as shown inFIG. 6, heat treatment is applied to the semiconductor layer2for 50 minutes at 1,100° C. for thermal oxidation of the inner surface of trench T, thereby forming the insulating film14. Then, the trench T is filled with a conductive material such as polysilicon to form the trench gate electrode12. The insulating film14that is formed on the inner surface of the trench T serves as a gate oxide film.

Next, as shown inFIG. 7, a resist R1of about 4 μm in thickness is formed on an area of the front surface2athat is to become the IGBT element region J1. Carbon C and oxygen O as non-conductive impurities are implanted from the front surface2a. In this regard, the relationship between the depth from the front surface2aof the semiconductor layer2, and the concentration of implanted carbon C and oxygen O is shown inFIG. 8. InFIG. 8, carbon C and oxygen O are implanted from depth d1to depth d3. As shown inFIG. 8, the implantation acceleration voltage is set in such a way that the concentration of carbon C and oxygen O to be implanted reaches a maximum within the drift layer60(at depth d2inFIG. 8) near the boundary between the drift layer60and the low-concentration p-type layer30in the area that is to become the diode element region J2. Also, the implantation acceleration voltage is set in such a way that the depth d3is shallower than the depth of the deepest portion of the trench T. For example, when carbon C is implanted, the acceleration voltage of a high-voltage ion implanter is set to about 3 MeV, and the amount of implantation per unit area is set to about 1.5×1012cm−2. Also, when oxygen O is implanted, the acceleration voltage of the high-voltage ion implanter is set to about 4 MeV, and the amount of implantation per unit area is set to about 3×1012cm−2. After implanting carbon C and oxygen O, the resist R1is removed by ashing and oxidation peeling. To repair damage to the semiconductor layer2after the implantation, heat treatment is performed at the temperature of 400° C. or higher. As shown inFIG. 9, the low lifetime region61, which contains a large number of couplings of carbon C and oxygen O, is formed in an area that is to become the diode element region J2.

It should be noted that when impurities are implanted in the diode element region J2, it is preferable that no impurities be implanted in the IGBT element region J1. However, in reality, trace impurities may be implanted beyond the resist R1(seeFIG. 7) and reach a shallow area from the front surface2aof the IGBT element region J1. This is due to such reasons that in order to implant impurities to a deep position from the front surface2aof the diode element region J2, the acceleration voltage at the time of implantation must be set high, and that it is difficult to form a thick resist R1in thickness of over 4 μm on the front surface2a. However, a shallow area from the front surface2a, the trench-adjoining region20with a high n-type impurity concentration and the high-concentration p-type region22with a high p-type impurity concentration are to be formed in subsequent steps. Thus, as far as carbon C and oxygen O are implanted in a shallow area from the front surface2, in the IGBT element region J1, it is unlikely to adversely affect the conductivity modulation phenomenon that occurs in the drift layer60when the IGBT element region J1is in the ON state. Thus, a situation in which the ON-state voltage in the IGBT element region J1increases is unlikely to occur.

Next, as shown inFIG. 10, a mask M2is formed on the front surface2a. The mask M2has an opening that is formed in an area where the trench-adjoining region20is to be formed. Phosphorus, an n-type impurity, is implanted into the semiconductor layer2from the front surface2a(implantation conditions: the amount of implantation per unit area is set to about 4×1014cm−2, and the acceleration voltage is about 60 kV). Then, heat treatment is applied to form the n+-type trench-adjoining region20. The mask M2is removed from the front surface2aby ashing and oxidation peeling. Next, as shown inFIG. 11, a mask M3is formed on the front surface2a. The mask M3has an opening that is formed in an area where the high-concentration p-type region22is to be formed. Boron is implanted into the semiconductor layer2from the front surface2a(implantation conditions: the amount of implantation per unit area is set to about 4×1015cm−2, and the acceleration voltage is about 50 kV). Then, heat treatment is applied to form the high-concentration p-type region22. The mask M3is removed from the front surface2aby ashing and oxidation peeling. It should be noted that the above-described heat treatment to form the trench-adjoining region20may be performed simultaneously at this time. The trench-adjoining region20and the high-concentration p-type region22are formed on the front surface2aof the low-concentration p-type region30between successive trenches T.

Next, as shown inFIG. 12, the insulating film10is formed by the CVD method in a portion where the trench gate electrode12is exposed on the front surface2a. Barrier metal and aluminum are formed on the front surface2aby sputtering to form the front-surface electrode5. The trench gate electrode12may be connected to gate wiring (not shown) at any position in the extension direction of the drench gate electrode across the drift layer inFIG. 12. Then, the semiconductor layer2is polished from below. Thereafter, a hard mask M4is placed on an area of the back surface2bof the semiconductor layer2where the IGBT element region J1is to be formed, and phosphorus is implanted from the back surface2b(implantation conditions: the amount of implantation per unit area is set to about 1×1015cm−2, and the acceleration voltage is about 50 kV). Thereafter, laser annealing is applied, forming the n+-type cathode region70.

Next, as shown inFIG. 13, a hard mask M5is placed in an area where phosphorus is implanted, and boron is implanted from the back surface2b(implantation conditions: the amount of implantation per unit area is set to about 3×1013cm−2, and the acceleration voltage is about 50 kV). Thereafter, laser annealing is applied to form the p+-type collector region80. It should be noted that the collector region80and the cathode region70may be formed by applying laser annealing simultaneously. Alternatively, heat treatment may be applied within a temperature range that does not greatly affect the shallow portion2U that has already been formed. Then, as shown inFIG. 1, for example, a laminated film of aluminum, titanium, nickel, and gold is formed on the back surface2bby sputtering. Thus, the back-surface electrode3that connects to both the collector region80and the cathode region70is formed.

According to the above manufacturing method, the low lifetime region61may be formed only in the drift layer60of the diode element region J2without forming the low lifetime region in the drift layer60in the IGBT element region J1. In addition, the low lifetime region61is formed in an area that is shallower than the deepest portion of the trench T. Thus, implanted carbon C and oxygen O are unlikely to diffuse beyond the trench T during the manufacturing process. In particular, in the portion of the boundary between the IGBT element region J1and the diode element region J2, carbon C and oxygen O that are implanted into the diode element region J2are unlikely to diffuse into the adjoining IGBT element region J1. This is particularly advantageous for when the IGBT element region J1and the diode element region J2are formed alternately. Also, in the above-described manufacturing method, carbon C and oxygen O are implanted into the semiconductor layer2to form the low lifetime region61. The low lifetime region61may be formed at least within the drift layer60near the boundary between the drift layer60and the low-concentration p-type layer30. Accordingly, carbon C and oxygen O are implanted deeply in the front surface2aof the diode element region J2. Among non-conductive impurities that enable lifetime adjustment, carbon C and oxygen O are relatively light. Therefore, carbon C and oxygen O is easily implanted into a deep area.

While this embodiment is directed to the case in which the trench gate electrode12is also formed in the diode element region J2, the trench gate electrode12in the diode element region J2may be omitted. Likewise, the trench-adjoining region20in the diode element region J2may be omitted. The IGBT element region J1and the diode element region J2may be formed alternately along at least one direction for each partitioned region4that is formed in the shallow portion2U of the semiconductor layer2. In this case, the collector region80and the cathode region70are formed in repetition along at least one direction on the back surface2b. The low lifetime region61may extend to a part of the low-concentration p-type region30beyond the boundary between the drift layer60and the low-concentration p-type region30in the diode element region J2. The entire region of the drift layer60in the diode element regions J2may be the low lifetime region61. In addition, this embodiment is directed to the case in which the low lifetime region61is formed across the successive trenches T in the diode element region J2. However, it suffices that the low lifetime region61be formed in at least a part of the drift layer60in the diode element region J2, and may not be formed across the trenches T. Furthermore, this embodiment is directed to the case in which the low lifetime region61is formed by implanting carbon C and oxygen O which are non-conductive impurities originally contained in the semiconductor layer2. However, the non-conductive impurities that are implanted are not limited to carbon C and oxygen O. For example, the lifetime of holes may also be reduced also by implanting one or more heavy metals, such as gold Au or platinum Pt, or carbon, oxygen, nitrogen, fluorine, argon, silicon, germanium, or the like.

While embodiments of the present invention have been described above in detail, it is to be understood that these embodiments are illustrative only and do not limit the scope of the claims. Also, the technical elements described in this specification or the drawings exhibit technical utility when used alone or in various combinations, and are not limited to the combinations described in the claims as filed. In addition, the technique illustrated in this specification or the drawings can attain multiple objects at the same time, and attainment of one of the objects itself provides technical utility.