Semiconductor device, electronic device, and manufacturing method thereof

To provide a semiconductor device in which resistance of a source region and a drain region of a thin film transistor is reduced and a short channel effect is suppressed, and a manufacturing method thereof. The semiconductor device includes a gate electrode which is formed over a first semiconductor layer with a gate insulating film interposed therebetween; sidewalls which are formed on side surfaces of the gate electrode; and second semiconductor layers which are in contact with and stacked over end portions of the sidewalls and the first semiconductor layer, wherein the second semiconductor layers cover at least a part of the end portions of the sidewalls.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device including the semiconductor device.

2. Description of the Related Art

A thin film transistor (TFT) is a transistor formed using a semiconductor. In recent years, in order to improve performance of a semiconductor device, various technologies have been examined in accordance with increasing in integration degree of thin film transistors and downsizing of semiconductor devices using a thin film transistor.

With downsizing of semiconductor devices, parasitic resistance between a source region and a drain region of a thin film transistor cannot be ignored, and sheet resistance is increased.

When the sheet resistance of the source region and the drain region is increased, a problem arises in that current drive capability is deteriorated in a semiconductor device which is manufactured.

In order to solve the forgoing problem, with respect to a thin film transistor, a technique has been developed in which a high-concentration impurity layer is stacked over a semiconductor layer and only the high-concentration impurity layer is etched not to promote etching of a lower semiconductor layer using difference in etching rate between the two layers in dry etching (Non-Patent Document 1: “Raised source and drain structure of poly-Si TFTs” Electrochemical Society Proceeding).

By using this technique, a thin film transistor in which resistance of a source region and a drain region is lowered can be manufactured using a stacked portion of a semiconductor layer and a high-concentration impurity layer for the source region and the drain region.

SUMMARY OF THE INVENTION

In Non-Patent Document 1, since a polycrystalline semiconductor layer has a large thickness of 100 nm, it is possible to perform etching with the polycrystalline semiconductor layer left using the difference in etching rate between the polycrystalline semiconductor layer and a high-concentration impurity layer.

However, when a channel length (the length of a channel formation region in a direction in which carriers flow) of a thin film transistor is reduced in accordance with downsizing of semiconductor devices, leakage current increases and the subthreshold swing (S value) of the thin film transistor increases (a short channel effect). That is, switching characteristics of the thin film transistor are deteriorated.

In order to suppress a short channel effect the polycrystalline semiconductor layer including the channel formation region of the thin film transistor should be thinly formed to have a thickness of less than or equal to 100 nm, particularly, less than or equal to 40 nm.

When the polycrystalline semiconductor layer has a thickness of less than or equal to 40 nm, it is difficult to perform etching with the polycrystalline semiconductor layer left as in Non-Patent Document 1, and it is extremely difficult to prevent the polycrystalline semiconductor layer from being removed regardless of the magnitude of the difference in etching rate.

In view of the foregoing, an object to be disclosed is to provide a semiconductor device in which sheet resistance of a source region and a drain region is reduced, a short channel effect is suppressed, and a semiconductor layer is prevented from being removed.

A semiconductor device to be disclosed includes: a first semiconductor layer formed over an insulator; a gate insulating film formed over the first semiconductor layer; a gate electrode formed over the gate insulating film; sidewalls formed in contact with side surfaces of the gate electrode; and second semiconductor layers which are in contact with and stacked over the first semiconductor layer and which are formed to be in contact with or cover a part of the sidewalls.

A semiconductor device includes: a first semiconductor layer formed over an insulator; a gate insulating film formed over the first semiconductor layer; a gate electrode formed over the gate insulating film; sidewalls formed in contact with side surfaces of the gate electrode; and second semiconductor layers which are in contact with and stacked over end portions of the sidewalls extended over the first semiconductor layer and the first semiconductor layer and which are formed to be in contact with or cover at least a part of the end portions of the sidewalls.

Here, the end portions of the sidewalls which are extended are a part of the sidewalls, and the second semiconductor layers are considered to cover a part of the sidewalls even when the second semiconductor layers are formed to cover the end portions.

Here, the second semiconductor layers are formed to be in contact with at least a part of the sidewalls, and have a structure in which a top surface of the first semiconductor layer is prevented from being exposed between the sidewalls and the second semiconductor layers.

A semiconductor device is provided with a channel formation region and a source region and a drain region in a first semiconductor layer, and low-concentration impurity (also referred to as a light doped drain: LDD) regions between the channel formation region and the source region or the drain region, and high-concentration impurity regions at portions where the first semiconductor layer and the second semiconductor layers are stacked.

A semiconductor device is provided with an insulating layer covering a top surface of the gate electrode.

A method for manufacturing a semiconductor device to be disclosed includes the steps of: forming a first semiconductor layer over an insulator; forming a gate insulating film and a gate electrode which are stacked over the first semiconductor layer in this order; adding an impurity element imparting one conductivity to the first semiconductor layer using the gate electrode as a mask to form low-concentration impurity regions; forming sidewalls on side surfaces of the gate electrode; forming a semiconductor film covering the gate electrode, the sidewalls, and the first semiconductor layer; etching the semiconductor film using a resist mask to form two second semiconductor layers so that the second semiconductor layers are in contact with and stacked over the first semiconductor layer and are in contact with or cover a part of the sidewalls; and adding an impurity element imparting the one conductivity to the two second semiconductor layers to form high-concentration impurity regions.

A method for manufacturing a semiconductor device includes the steps of: forming a first semiconductor layer over an insulator; forming a gate insulating film and a gate electrode which are stacked over the first semiconductor layer in this order; adding an impurity element imparting one conductivity to the first semiconductor layer using the gate electrode as a mask to form low-concentration impurity regions; forming sidewalls which are in contact with side surfaces of the gate electrode and of which end portions are extended over the first semiconductor layer; forming a semiconductor film covering the gate electrode, the sidewalls, the end portions of the sidewalls, and the first semiconductor Layer; etching the semiconductor film using a resist mask to form two second semiconductor layers so that the second semiconductor layers are in contact with and stacked over the first semiconductor layer and are in contact with or cover at least a part of the end portions; and adding an impurity element imparting the one conductivity to the two second semiconductor layers to form high-concentration impurity regions.

A method for manufacturing a semiconductor device includes the steps of: forming a first semiconductor layer over an insulator; forming a gate insulating film, a gate electrode, and an insulating layer which are formed over the first semiconductor layer in this order; adding an impurity element imparting one conductivity to the first semiconductor layer using the gate electrode as a mask to form low-concentration impurity regions; forming sidewalls on side surfaces of the gate electrode; forming a semiconductor film covering the insulating layer, the sidewalls, and the first semiconductor layer; etching the semiconductor film using a resist mask to form two second semiconductor layers so that the second semiconductor layers are in contact with and stacked over the first semiconductor layer and are in contact with or cover at least a part of the sidewalls; and adding an impurity element imparting the one conductivity to the two second semiconductor layers to form high-concentration impurity regions.

A method for manufacturing a semiconductor device includes the steps of: forming a first semiconductor layer over an insulator; forming a gate insulating film, a gate electrode, and an insulating layer which are stacked over the first semiconductor layer in this order; adding an impurity element imparting one conductivity to the first semiconductor layer using the gate electrode as a mask to form low-concentration impurity regions; forming sidewalls on side surfaces of the gate electrode; forming a semiconductor film covering the insulating layer, the sidewalls, and the first semiconductor layer; forming a negative resist covering the semiconductor film; forming a resist mask by performing light exposure from the rear surface side of the insulator to the negative resist using the gate electrode as a mask; etching the semiconductor film using the resist mask; patterning the etched semiconductor film to form two second semiconductor layers so that the second semiconductor layers are in contact with and stacked over the first semiconductor layer and are in contact with or cover at least a part of the sidewalls; and adding an impurity element imparting the one conductivity to the two second semiconductor layers to form high-concentration impurity regions.

That is, a semiconductor device obtained by a manufacturing method to be disclosed is formed so that a first semiconductor layer and second semiconductor layers are stacked and the thickness of the stacked portion is larger than the thickness of a portion which is in the first semiconductor layer and overlaps with a gate electrode.

Further, the second semiconductor layers are formed covering a part of sidewalls.

By forming a channel formation region in a semiconductor layer which is thinned, a short channel effect can be suppressed, and S value can be reduced. Further, a source region and a drain region are formed in a stacked portion of the semiconductor layer and high-concentration impurity layers to thicken the source region and the drain region; thus, sheet resistance between the source region and the drain region can be reduced.

By employing a structure in which a part of sidewalls formed on side surfaces of the gate electrode and the high-concentration impurity layers overlap with each other, a semiconductor device in which the semiconductor layer is prevented from being removed can be provided.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments will be described with reference to the drawings. However, the present invention can be carried out in many different modes, and it is easily understood by those skilled in the art that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the following description of the embodiments.

The following Embodiments 1 to 7 can be combined as appropriate. Parts with the same reference numerals in the drawings can be formed using the same materials and by the same methods unless otherwise noted.

In Embodiment 1, an example of an element structure of a semiconductor device is described.

FIG. 1is a cross-sectional view of a semiconductor device in Embodiment 1.

The semiconductor device illustrated inFIG. 1includes an insulator101, a first semiconductor layer102, a gate insulating film103, a gate electrode104, sidewalls105, second semiconductor layers106, interlayer insulating films110, and electrodes113and114.

The sidewalls105are formed on side surfaces of the gate electrode104, and the second semiconductor layers106are formed partially covering the sidewalls105.

The first semiconductor layer102includes a channel formation region107, low-concentration impurity regions108, and high-concentration impurity regions109. The thickness of the first semiconductor layer is preferably 10 nm to 40 nm. The first semiconductor layer102may have a structure in which the low-concentration impurity regions108are not provided.

The gate electrode104is formed over the channel formation region107with the gate insulating film103interposed therebetween, the sidewalls105are formed over the low-concentration impurity regions108with the gate insulating film103interposed therebetween, and the second semiconductor layers106are formed over the high-concentration impurity regions109to be directly in contact with each other. The thickness of the second semiconductor layers106is preferably greater than or equal to 50 nm (desirably, greater than or equal to 100 nm).

An impurity element imparting one conductivity is added at high concentration to the second semiconductor layers106and regions in the first semiconductor layer102, and a source region and a drain region are formed using the high-concentration impurity regions109and the second semiconductor layers106.

That is, a thin film transistor in which the source region and the drain region are formed to be thicker than the channel formation region107and the low-concentration impurity regions108is manufactured.

Further, the interlayer insulating films110are formed covering the thin film transistor, and the electrodes113and114are electrically connected to the second semiconductor layers106through contact holes111and112, which are formed in the interlayer insulating films110.

Therefore, in a semiconductor device of this embodiment, since the thickness of the first semiconductor layer102is small, a short channel effect can be suppressed, and since the thicknesses of the source region and the drain region are large, sheet resistance can be reduced.

Furthermore, since the second semiconductor layers106cover the high-concentration impurity regions109and parts of the sidewalls105, in patterning the second semiconductor layers, the first semiconductor layer102can be prevented from being removed by the sidewalls105serving as etching stoppers.

Note that, inFIG. 1, bottom surfaces of the sidewalls105are in contact with the gate insulating film103; however, as inFIG. 4, a structure in which bottom surfaces of sidewalls401are not in contact with a gate insulating film402but in contact with the low-concentration impurity regions108in the first semiconductor layer102may be employed.

Further, as inFIG. 3, a structure in which an insulating layer302is formed covering a top surface of the gate electrode104may be employed.

As inFIG. 3, since the insulating layer302covers the top surface of the gate electrode104, a short circuit between the gate electrode104and the second semiconductor layers106can be prevented.

The low-concentration impurity regions108are not necessarily provided; however, by providing the low-concentration impurity regions108, effects such as suppression of a short channel effect, improvement of switching characteristics due to reduction in off-state current, and suppression of generation of hot carriers can be obtained. Therefore, a structure in which the low-concentration impurity regions108are provided is preferable. Note that, in the case where the low-concentration impurity regions108are not provided, an impurity element may be provided at high concentration to regions corresponding to the low-concentration impurity regions.

In Embodiment 2, an element structure of a semiconductor device, which is different from that in Embodiment 1, is described.

FIG. 2is a cross-sectional view of a semiconductor device in Embodiment 2.

InFIG. 2, parts denoted by the same reference numerals as those inFIG. 1can be formed using the same materials and the same method as those inFIG. 1.

A structure in Embodiment 2 is different from that in Embodiment 1 in that end portions202of a sidewall201are extended to be overlapped with parts of the first semiconductor layer102as illustrated inFIG. 2.

In Embodiment 1 (seeFIG. 1), when the second semiconductor layers106are formed, in the case where a resist cannot be patterned over the sidewalls105because of misalignment of a mask, the first semiconductor layer102is partially exposed. At that time, since the thickness of the first semiconductor layer102is extremely small, a problem arises in that the first semiconductor layer is removed while the second semiconductor layers106are patterned.

Thus, with the element structure inFIG. 2, even when the second semiconductor layers106cannot be formed over the sidewall201because of misalignment of a mask, by providing a margin of the misalignment of the mask which corresponds to a width203of the end portions202of the sidewall201, the first semiconductor layer102can be prevented from being removed.

Further, in the semiconductor device of this embodiment, by providing the end portions202, a distance can be put between the second semiconductor layers106and the gate electrode104; therefore, parasitic capacitance between the gate electrode104and the second semiconductor layers106can be reduced.

In Embodiment 3, a first method for manufacturing a semiconductor device is described with reference toFIGS. 5A to 5D,FIGS. 6A to 6C, andFIGS. 7A and 7B.

The first semiconductor layer102is formed over the insulator101. The insulator may be an insulating substrate or may be a base insulating film having a single-layer structure or a stacked-layer structure, which is provided over a substrate (FIG. 5A).

As the insulating substrate, a glass substrate, a quartz substrate, a resin substrate, or the like can be used.

As the base insulating film, a single-layer film or a stacked-layer film of a silicon oxide film, a silicon nitride film, a silicon nitride oxide film in which nitrogen concentration is higher than oxygen concentration, a silicon oxynitride film in which oxygen concentration is higher than nitrogen concentration, a resin film, or the like can be used. The insulator101is formed with the base insulating film provided over a semiconductor substrate, a glass substrate, a quartz substrate, a resin substrate, or the like.

The first semiconductor layer102is formed by patterning an amorphous semiconductor film, a polycrystalline (microcrystalline is included) semiconductor film, or a single crystal semiconductor film which is formed with silicon, silicon germanium, or the like using a known method such as a CVD method or a sputtering method. Note that the first semiconductor layer102may include an impurity element imparting n-type or p-type conductivity.

Further, a crystalline semiconductor having high crystallinity may be formed by performing crystallization with heat or irradiation with light (laser, infrared rays, or the like).

Furthermore, an SOI layer which is formed by a SIMOX method, a bonding method, or the like may be used.

The thickness of the first semiconductor layer102is preferably 10 nm to 40 nm in order to suppress adverse effects of a short channel effect on electrical characteristics of a completed thin film transistor.

Next, an insulating film501which is to be a gate insulating film and has a single-layer structure or a stacked-layer structure is formed over the first semiconductor layer102, and then a conductive film (not illustrated) which is to be a gate electrode is formed thereover. Then, the conductive film is patterned to form the gate electrode104over the first semiconductor layer102with the insulating film501interposed therebetween (FIG. 5B).

Further an impurity element imparting one conductivity is added to the first semiconductor layer102using the gate electrode104as a mask, and the channel formation region107is formed at a portion in the first semiconductor layer102where is overlapped with the gate electrode104. The impurity element which is added may be either an element imparting p-type conductivity or an element imparting n-type conductivity. In the case where a structure in which an LDD region is not provided in a completed thin film transistor is employed, the impurity element may not be added or the impurity element may be added at high concentration (FIG. 5B).

As the impurity element imparting n-type conductivity, phosphorus, arsenic, or the like can be used. As the impurity element imparting p-type conductivity, boron or the like can be used. The impurity element can be added by ion doping, ion implantation, laser doping, a thermal diffusion method, or the like.

Although an example showing only one element is described for convenience in this embodiment, it is preferable to form a plurality of elements in a plane and employ a CMOS structure in which both an n-type thin film transistor and a p-type thin film transistor are formed.

Note that, in this embodiment the impurity element is added in a state where the insulating film501which is to be a gate insulating film is formed, through the insulating film501; however, the impurity element may be added in a state where the first semiconductor layer102is exposed after the insulating film501is etched using the gate electrode104as a mask to form a gate insulating film. In the case of doping through the insulating film501, since the insulating film501covers the first semiconductor layer102, damage of the first semiconductor layer102due to doping can be reduced.

Subsequently, an insulating film502having a single-layer structure or a stacked-layer structure, which covers the gate electrode104and is to be sidewalls, is formed (FIG. 5C).

As the insulating film502which is to be sidewalls, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film in which nitrogen concentration is higher than oxygen concentration, a silicon oxynitride film in which oxygen concentration is higher than nitrogen concentration, or the like can be used. The thickness of the insulating film502is preferably 100 nm to 1 μm.

When the insulating film502is formed, a step is formed due to the influence of a step of the gate electrode104.

Then, the insulating films502and501are etched to form the sidewalls105which cover side surfaces of the gate electrode104. By employing an etch back method to form the sidewalls105, the number of process steps can be reduced as compared to the case of using a mask (FIG. 5D).

When the sidewalls105are formed, it is preferable to etch the insulating film501which is to be a gate insulating film as well as the insulating film502which is stacked thereover and which is to be sidewalls. At this stage, a surface of the first semiconductor layer102is exposed, and the gate insulating film103is formed. As described above, the gate insulating film may be formed by etching the insulating film501using the gate electrode as a mask in a previous process step.

Then, a semiconductor film601which is to be second semiconductor layers is formed covering the sidewalls105, the first semiconductor layer102, and the insulator101(FIG. 6A).

The thickness of the semiconductor film601should be so large that sheet resistance of portions to be a source region and a drain region can be reduced, and is preferably greater than or equal to 50 nm (desirably, greater than or equal to 100 nm).

As the semiconductor film601, an amorphous semiconductor film, a polycrystalline (microcrystalline is included) semiconductor film, or a single crystal semiconductor film which is formed with silicon, silicon germanium, or the like using a known method such as a CVD method or a sputtering method is used. Note that the semiconductor film601may include an impurity element imparting n-type or p-type conductivity to control a threshold value.

Further, a crystalline semiconductor having high crystallinity may be formed by performing crystallization with heat or irradiation with light (laser, infrared rays, or the like).

Then, the semiconductor film601is etched using a resist mask602so that the semiconductor film601is divided over the sidewalls105, and end portions of the semiconductor film601are etched so that they are stacked over the first semiconductor layer102. Thus, two second semiconductor layers603which are in contact with the first semiconductor layer102are formed. The semiconductor film601should be divided so that the gate electrode104and the second semiconductor layers603are not in contact with each other (FIGS. 6B and 6C).

Here, the two second semiconductor layers603should be formed partially covering the sidewalls105as illustrated inFIG. 6C. Since the sidewalls105are partially covered, the sidewalls105function as etching stoppers in patterning the second semiconductor layers603; therefore, a top surface of the first semiconductor layer102is not exposed between the sidewalls105and the second semiconductor layers603. Thus, the first semiconductor layer102can be prevented from being removed in the patterning.

Then, an impurity element imparting the one conductivity is added to the second semiconductor layers603and a portion where the first semiconductor layer102and the second semiconductor layers603are stacked to form high-concentration impurity regions701and704, and low-concentration impurity regions702are formed between the high-concentration impurity regions and the channel formation region (FIG. 7A).

In this process, the impurity element may be added so that the low-concentration impurity regions remain at lower portions in regions which are in the first semiconductor layer102and overlapped with the second semiconductor layers603(corresponding to regions704shown inFIG. 7A) to form lamination of the low-concentration impurity regions and the high-concentration impurity regions in the first semiconductor layer102. In this case, the low-concentration impurity regions are also formed at lower portions in the regions which are in the first semiconductor layer102and overlapped with the second semiconductor layers603. With functions of these low-concentration impurity regions, leakage current of a transistor can be reduced.

The impurity element which is added here may be either an element imparting p-type conductivity or an element imparting n-type conductivity; however, an element imparting the same conductivity as conductivity of the low-concentration impurity regions702should be added. Further, addition is performed so that an impurity concentration of the high-concentration impurity regions701is higher than that of the low-concentration impurity regions702.

In this embodiment, the impurity element is added after the second semiconductor layers603are formed; however, a process may be employed in which addition is performed at the stage where the semiconductor film601is formed (FIG. 6A) to form the high-concentration impurity regions and then patterning is performed to form the second semiconductor layers603.

As the impurity element imparting n-type conductivity, phosphorus, arsenic, or the like can be used. As the impurity element imparting p-type conductivity, boron or the like can be used. The impurity element can be added by ion doping, ion implantation, laser doping, a thermal diffusion method, or the like.

Then, the impurity element which is added is activated with heat or irradiation with light (with laser, infrared rays, or the like).

The high-concentration impurity regions701and704which are formed function as a source region and a drain region of a thin film transistor.

Subsequently, the interlayer insulating films110which have a single-layer structure or a stacked-layer structure are formed. Then, the electrodes113and114are electrically connected to the high-concentration impurity regions701and704through the contact holes111and112, which are provided in the interlayer insulating films110(FIG. 7B).

A structure may be employed in which regions comprising metal silicide are formed over the high-concentration impurity regions701and the electrodes113and114are electrically connected to the regions comprising metal silicide in order to reduce sheet resistance of the source region and the drain region.

As described above, a semiconductor device is manufactured using the first method.

In Embodiment 4, a second method for manufacturing a semiconductor device is described with reference toFIGS. 8A to 8CandFIGS. 9A and 9B.

As in Embodiment 3, the insulator101, the first semiconductor layer102, the insulating film501which is to be a gate insulating film, and a conductive film801which is to be a gate electrode are formed in this order.

Next, an insulating film802is formed over the conductive film801which is to be a gate electrode (FIG. 8A).

Then, the insulating film501, the conductive film801, and the insulating film802are etched using a mask (not illustrated) to form a gate insulating film803, a gate electrode804, and an insulating layer805covering a top surface of the gate electrode804(FIG. 8B).

In the case where an LDD region is formed, the impurity element is added at low concentration as in Embodiment 3. Addition may be performed at this stage or performed through the insulating film501after only the gate electrode804and the insulating layer805which is on a top surface of the gate electrode804are etched without etching the insulating film501. In the case where the impurity element is added through the insulating film, in forming sidewalls in a later process step, it is desirable that the insulating film501is etched to form a gate insulating film. Note that, in the case where an LDD region is not formed, an impurity element may be added at high concentration.

Next, an insulating film806which is to be sidewalls is formed (FIG. 8C).

Then, sidewalls901which cover side surfaces of the gate electrode804are formed by etching back the insulating film806. At this time, since the insulating layer805serves as an etching stopper in etching back, the top surface of the gate electrode804can be prevented from being exposed and damaged. Therefore, the insulating layer805is preferably formed using a material of which the etching rate with respect to that of the sidewalls is low. In the case where the gate insulating film is formed at this stage, the insulating layer805is preferably formed using a material of which the etching rate with respect to that of the gate insulating film is also low (FIG. 9A).

Next, as in Embodiment 3, a semiconductor film (not illustrated) which covers the sidewalls901, the first semiconductor layer102, and the insulator101and which is to be second semiconductor layers is formed. Then, the semiconductor film is patterned to form two second semiconductor layers902which are in contact with the first semiconductor layer102. The second semiconductor layers902should be formed partially covering the sidewalls901, and since the sidewalls901are partially covered, the top surface of the first semiconductor layer102can be prevented from being exposed between the sidewalls901and the second semiconductor layers902and being removed in patterning the second semiconductor layers902(FIG. 9B).

In this embodiment, since the insulating layer805is formed on the top surface of the gate electrode804, even when the second semiconductor layers902are formed at positions which overlap with the gate electrode804, a short circuit between the second semiconductor layers902and the gate electrode804can be prevented.

Formation of the high-concentration impurity regions and subsequent process steps are similar to those in Embodiment 3 (process steps afterFIG. 7A); therefore, a description thereof is omitted.

In Embodiment 5, a third method for manufacturing a semiconductor device is described with reference toFIGS. 10A to 10CandFIGS. 11A to 11C.

Since process steps to and including formation of the insulating film502for forming sidewalls are similar those in Embodiment 3 (FIG. 5C), in this embodiment, a description of processes from formation of sidewalls is made.

After the insulating film502is formed, a resist mask1001is formed covering the gate electrode104(FIG. 10A).

The insulating film502is etched using the resist mask1001, and a sidewall1002and end portions1003of the sidewall1002which extend over the first semiconductor layer102are formed. The end portions1003have widths1004(FIG. 10B).

As in Embodiment 3, the gate insulating film103may be formed at this stage or at the same time as formation of the gate electrode104.

Then, the resist mask1001is removed, and a semiconductor film1005which covers the sidewall1002, the end portions1003, the first semiconductor layer102, and the insulator101and which is to be second semiconductor layers is formed (FIG. 10C).

The thickness of the semiconductor film1005should be so large that sheet resistance of portions to be a source region and a drain region can be reduced, and the thickness is preferably greater than or equal to 50 nm (desirably, greater than or equal to 100 nm).

Then, the semiconductor film1005is etched using the resist mask1101to expose the sidewall1002and to form two second semiconductor layers1102which cover at least a part of the end portions1003and are in contact with and stacked over the first semiconductor layer102(FIGS. 11A and 11B).

Here, as illustrated inFIG. 11B, the second semiconductor layers1102should be formed covering at least a part of the end portions1003. By forming the second semiconductor layers1102so that the end portions1003are partially covered, the end portions1003serve as etching stoppers, and the top surface of the first semiconductor layer102is not exposed between the end portions1003of the sidewall and the second semiconductor layers1102in patterning the second semiconductor layers1102. Therefore, the first semiconductor layer102can be prevented from being removed in the patterning.

Note that end portions of the second semiconductor layers1102and end portions of the first semiconductor layer102do not have to be aligned with each other.

By providing the end portions1003, even in the case where the second semiconductor layers1102are formed not covering the sidewall1002due to misalignment of the resist mask1101, a margin of the widths1004can be obtained, and redundancy of alignment can be improved.

Further, by providing the end portions1003, a distance can be put between the second semiconductor layers1102and the gate electrode104; therefore, parasitic capacitance between the second semiconductor layers1102and the gate electrode104can be reduced.

Then, by adding an impurity element imparting one conductivity, high-concentration impurity regions1103are formed at portions where the first semiconductor layer102and the second semiconductor layers1102overlap with each other, and low-concentration impurity regions1104are formed. Here, the impurity element is added which imparts the same conductivity as the conductivity of the low-concentration impurity regions1104and has higher concentration than the low-concentration impurity regions1104. In this case, the impurity element is added to the first semiconductor layer102through the end portions1003; thus, portions which are in the first semiconductor layer102and overlap with the end portions1003also serve as the high-concentration impurity regions1103(FIG. 11C).

Further, by thickly forming the end portions1003, the end portions1003serve as masks in the addition of the impurity element; therefore, the low-concentration impurity regions1104can also be formed at portions which are in the first semiconductor layer102and overlap with the end portions1003.

Furthermore, the thickness of the end portions1003or conditions for addition of an impurity element is controlled so that a part of the impurity element passes through the end portions1003; thus, impurity regions whose impurity concentration is higher than that of the low-concentration impurity regions and lower than that of the high-concentration impurity regions can be formed at portions which are in the first semiconductor layer102and between the low-concentration impurity regions1104and the high-concentration impurity regions1103and which overlap with the end portions11003.

Alternatively, the impurity element may be added so that the low-concentration impurity regions remain at portions which are in the first semiconductor layer102and overlap with the semiconductor layers1102, and a staked-layer structure of the low-concentration impurity regions and the high-concentration impurity regions may be formed in the first semiconductor layer102.

Note that, in this embodiment, although the impurity element is added after the second semiconductor layers1102are formed, a process may be employed in which the impurity element is added at the stage where the semiconductor film1005is formed (FIG. 10C) to form the high-concentration impurity regions and then the second semiconductor layers1102are formed.

Next, the impurity element which is added is activated with heat or irradiation with light (with laser, infrared rays, or the like).

Then, the high-concentration impurity regions1103which are formed function as a source region and a drain region of a thin film transistor.

Subsequently, the interlayer insulating films110having a single-layer structure or a stacked-layer structure are formed. The electrodes113and114are electrically connected to the high-concentration impurity regions1103through the contact holes111and112, which are provided in the interlayer insulating films110(FIG. 11C).

A structure may be employed in which regions comprising metal silicide are formed over the high-concentration impurity regions1103and the electrodes113and114are electrically connected to the regions comprising metal silicide in order to reduce resistance of the source region and the drain region.

In Embodiment 6, a fourth method for manufacturing a semiconductor device is described with reference toFIGS. 12A to 12C.

Since process steps to and including formation of the sidewalls901are similar to those in Embodiment 4 (FIG. 9A), a description thereof is omitted.

After the sidewalls901, the insulating layer805, the first semiconductor layer102, and a semiconductor film1201which covers the insulator1101and is to be second semiconductor layers are formed, a negative resist is formed over the semiconductor film1201, and light exposure (backside light exposure) is carried out from the insulator101side to the negative resist. Then, development is carried out to process the negative resist into a desired shape (FIG. 12A).

By carrying out backside light exposure, the gate electrode104can be used as a mask; therefore, it is not necessary to use a new mask, and it is possible to achieve reductions in the number of process steps and cost.

Note that, for carrying out backside light exposure, it is important to use a light-transmitting substrate and irradiate the negative resist with energy required for light exposure.

Then, the semiconductor film1201is etched using resist masks1202which are processed so that the semiconductor film1201is divided over the sidewalls901(FIG. 12B).

Then, end portions of the semiconductor film1201are etched to form two second semiconductor layers1203which are stacked over the first semiconductor layer102(FIG. 12C).

The second semiconductor layers1203are formed using as a mask a resist which is formed by backside light exposure using the gate electrode104as a mask. Therefore, the second semiconductor layers1203can be formed so as to overlap parts of the sidewalls901. As a result, as in Embodiment 3, the first semiconductor layer102can be prevented from being removed.

The following process steps are similar to those in Embodiment 3 (process steps afterFIG. 7A); therefore, a description thereof is omitted

In this embodiment examples of electronic devices manufactured using a semiconductor device which is disclosed are described.

A semiconductor device which is disclosed can be applied to a pixel portion, a driver circuit portion, or the like of a display device provided with an organic light emitting element, an inorganic light emitting element, a liquid crystal element, or the like.

Further, an electronic device provided with a memory medium, such as a digital camera, a car navigation system, a notebook personal computers a game machine, a portable information terminal (e.g., a portable telephone or a portable game machine), or a home game machine, can be manufactured using the semiconductor device which is disclosed.

Furthermore, the semiconductor device which is disclosed can be applied to an integrated circuit of a CPU (a central processing unit) or the like.

For example,FIG. 13Ashows a portable information terminal.FIG. 13Bshows a digital camera.FIG. 13Cshows a portable telephone.FIG. 13Dshows a car navigation system.FIG. 13Eshows a notebook personal computer. The semiconductor device which is disclosed can be applied to an integrated circuit incorporated in main bodies1301,1302,1303,1304, and1305, or display portions1311,1312,1313,1314, and1315of the devices.

In manufacturing a display device, it is preferable to employ the first, second, third, or fourth method and use a glass substrate which is inexpensive and does not have a limit on the size of the substrate.

Furthermore, the semiconductor device which is disclosed can be applied to a device which enables non-contact input and output of data. The device capable of inputting and outputting data without contact is also referred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, or a wireless chip They are generically called non-contact tags (non-contact chips).

For example, the semiconductor device which is disclosed can be applied to non-contact tags1400,1401,1402,1403,1404,1405,1406, and1407inFIGS. 14A to 14H.

This application is based on Japanese Patent Application Serial No. 2008-115008 filed with Japan Patent Office on Apr. 25, 2008, the entire contents of which are hereby incorporated by reference.