Wiring substrate, semiconductor package, and method for manufacturing semiconductor package

A wiring substrate includes a block with substrates laid out in an array. The block includes corners and a plan view center. Each substrate includes a substrate body. Pads are formed on the substrate body. Each pad includes a pad surface. The pads of the substrates include first pads, which are the pads of one of the substrates located in at least one of the corners of the block. The pad surface of each of the first pads includes a first axis extending from the first pad toward the plan view center of the block. The pad surface of each of the first pads has a first length along the corresponding first axis and a second length along a second axis, which is orthogonal to the first axis. The first length is longer than the second length.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2014-024374, filed on Feb. 12, 2014, the entire contents of which are incorporated herein by reference.

FIELD

The present disclosure relates to a wiring substrate, a semiconductor package, and a method for manufacturing a semiconductor package.

BACKGROUND

International Publication No. WO2007/069606 describes a semiconductor package formed by arranging an electronic component between an upper substrate and a lower substrate and surrounding the electronic component with an encapsulation resin. A known method for manufacturing such a semiconductor package will now be described.

For example, as shown inFIG. 17, a large substrate72including a block71with a plurality of (7×4inFIG. 17) lower substrates70is first prepared, and an electronic component such as a semiconductor chip, a passive component, or the like is mounted on each lower substrate70. Then, a large substrate81including a plurality of (7×4inFIG. 17) upper substrates80is prepared, and a solder ball is bonded to a connection pad of each upper substrate80. The solder ball is then bonded to a connection pad of each lower substrate70, and the large substrate81is mounted on the large substrate72so that each upper substrate80is mounted on the corresponding lower substrate70by way of the solder ball. The space between the substrates72and the substrates81is filled with an encapsulation resin. Dicing is performed to cut and singulate the substrates72, the substrates81, and the encapsulation resin. This manufactures semiconductor packages.

SUMMARY

When the large substrate72and the large substrate81are overlapped, the displacement amount increases at the peripheral portion of the substrates72and81. In particular, if the difference in the diagonal size of the block71of the substrate72and the diagonal size of the substrate81increases due to a manufacturing error or the like, the displacement amount increases between the lower substrate70located at a corner of the block71and the corresponding upper substrate80. As a result, the solder ball moves over the edge of an opening in a solder resist layer that exposes the connection pad of the lower substrate70. This leads to insufficient solderability, which may lower the connection reliability of the lower substrate70and the upper substrate80.

One aspect of a wiring substrate according to one aspect of the present disclosure is a wiring substrate including a block with a plurality of substrates laid out in a predetermined array. The block includes a plurality of corners and a plan view center. Each of the plurality of substrates includes a substrate body and a plurality of pads formed on an upper surface of the substrate body. Each of the pads includes a pad surface. The pads of the substrates include first pads, which are the pads of one of the substrates located in at least one of the corners of the block. The pad surface of each of the first pads includes a first axis extending from the first pad toward the plan view center of the block. The pad surface of each of the first pads has a first length along the corresponding first axis and a second length along a second axis, which is orthogonal to the first axis. The first length is longer than the second length.

DESCRIPTION OF THE EMBODIMENTS

In the accompanying drawings, elements are illustrated for simplicity and clarity and have not necessarily been drawn to scale. To facilitate understanding, in the cross-sectional views, some components are shown in screentone and some components are shown without hatching lines.

The structure of a wiring substrate10in one embodiment will now be described with reference toFIGS. 1 to 3.

As shown inFIG. 1A, the wiring substrate10has, for example, a substantially tetragonal shape in a plan view. The wiring substrate10includes a plurality of (e.g., three) blocks11separated from one another. Each block11includes a plurality of substrates12arranged in a predetermined planar array (e.g., 3×3 matrix array). The substrates12undergo a step of mounting electronic components such as semiconductor chips, a step of mounting other substrates that are bonded to a spacer, a step of filling the space between the substrates12and the other substrates with an encapsulation resin, and finally cutting out semiconductor packages. In the step of filling the encapsulation resin, for example, resin encapsulation is performed in a batch molding process for each block11. In the following description, nine substrates12arranged in each block11may be referred to as substrates A1to A9, as shown inFIG. 1A. More specifically, in the following description, the substrate A1refers to the substrate12located at the center of each block11, and the substrates A2to A9refer to the substrates12located along the periphery of each block11.

As shown inFIG. 3, each substrate12includes a substrate body20, an uppermost layer wiring pattern30, a metal layer31, a solder resist layer32, a lowermost layer wiring pattern33, a metal layer34, and a solder resist layer35.

The substrate body20includes a core substrate21, through electrodes22formed in through holes21X of the core substrate21, insulating layers23and24stacked on the core substrate21, and wires25and26and vias27and28formed in the insulating layers23and24. In the substrate body20, the through electrodes22, the wires25and26, and the vias27and28electrically connect the wiring pattern30and the wiring pattern33. The material of the core substrate21may be a glass epoxy resin in which a glass cloth (glass woven fabric) is impregnated with a thermosetting insulative resin, the main component of which is an epoxy resin. The material of the insulating layers23and24may be, for example, an insulative resin such as an epoxy resin, a polyimide resin, or the like. The material of the through electrodes22, the wires25and26, and the vias27and28may be, for example, copper (Cu) or a copper alloy.

The wiring pattern30is arranged on an upper surface of the insulating layer23. In other words, the wiring pattern30is arranged on a mounting side surface (e.g., upper surface) of the substrate body20where a semiconductor chip41(seeFIG. 4) is mounted. The material of the wiring pattern30may be, for example, copper or a copper alloy. The wiring pattern30includes chip pads P1, which are electrically connected to the semiconductor chip41, and connection pads P2, which electrically connect the substrate12to another substrate43(seeFIG. 4) mounted on the substrate12. Although not shown from above, each chip pad P1is arranged in a mounting region R1(seeFIG. 1B) where the semiconductor chip41is to mounted in correspondence with the layout of bumps41a(seeFIG. 4), which are arranged on the semiconductor chip41. For example, the chip pads P1are arranged in a matrix array in a plan view in the mounting region R1. Each chip pad P1is, for example circular in a plan view.

The solder resist layer32is arranged on the upper surface of the insulating layer23to partially cover the wiring pattern30. The material of the solder resist layer32is, for example, an insulative resin such as an epoxy resin or an acrylic resin. The solder resist layer32includes openings32X, which expose portions of the wiring pattern30as the chip pads P1, and openings32Y, which expose portions of the wiring pattern30as the connection pads P2. The metal layer31is formed on the wiring pattern30exposed from the openings32X and32Y, that is, formed on the chip pads P1and the connection pads P2. One example of the metal layer31is a metal layer in which a nickel (Ni) layer and a gold (Au) layer are sequentially stacked from the upper surface of the wiring pattern30. Other examples of the metal layer31is a metal layer in which an Ni layer, a palladium (Pd) layer, and an Au layer are sequentially stacked, a metal layer in which an Ni layer, a Pd layer, and a silver (Ag) layer are sequentially stacked, and a metal layer in which an Ni layer, a Pd layer, an Ag layer, and an Au layer are sequentially stacked from the upper surface of the wiring pattern30. The Ni layer, the Au layer, the Pd layer, and the Ag layer may each be a metal layer (non-electrolytic plated metal layer) formed by undergoing non-electrolytic plating. The Ni layer is a metal layer containing Ni or an Ni alloy, the Au layer is a metal layer containing Au or an Au alloy, the Pd layer is a metal layer containing Pd or a Pd alloy, and the Ag layer is a metal layer containing Ag or an Ag alloy. For example, if the metal layer31is an Ni layer/Au layer, the thickness of the Ni layer may be about 0.05 to 5 μm, and the thickness of the Au layer may be about 0.01 to 1 μm. If a chip pad P1is covered by the metal layer31, the metal layer31functions as the chip pad P1. If a connection pad P2is covered by the metal layer31, the metal layer31functions as the connection pad P2.

FIG. 1Bis a plan view schematically showing the layout of the connection pads P2and the openings32Y in the substrate12(e.g., substrate A2). As shown inFIG. 1B, the connection pads P2and the openings32Y are arranged in a plurality of rows (e.g., two rows) surrounding the periphery of the mounting region R1.

FIG. 2is a plan view schematically showing the connection pads P2and the openings32Y of the substrates A1to A9in each block11. InFIG. 2, the number of the connection pads P2and the openings32Y in each substrate A1to A9is less than actual to facilitate illustration. In the description hereafter, the connection pad P2and the opening32Y have identical plan view shapes in a plan view. Thus, only the plan view shape of the connection pads P2will be described. The plan view shape of the connection pad P2is the shape of a pad surface of the pad P2.

As shown inFIG. 2, the connection pads P2of the substrates A1to A9are formed to have plan view shapes that differ in accordance with where the connection pads P2are located in the block11. The plan view shape of the connection pads P2arranged on the substrate A1in the present example is substantially a true circle. The plan view shape of the connection pads P2of the substrates A2to A9in the present example is a substantially an ellipse. In other words, the connection pads P2of the substrates A2to A9located in the peripheral portion of the block11are formed to be substantially ellipse in a plan view, and the connection pads P2of the substrate A1located in the central portion of the block11are formed to be substantially true circles in a plan view. The plan view shapes of the connection pads P2of the substrates A2to A9will now be described in detail.

Each connection pad P2(first pad) of the substrates A2to A9has the shape of an ellipse and includes a major axis AX1extending from the connection pad P2toward a plan view center B1of the block11(see broken line arrow in substrates A2and A3). Each connection pad P2of the substrates A2to A9has an elliptic plan view shape with a major axis AX1that becomes longer as the corresponding substrate12becomes farther from the plan view center B1in the block11. For example, each connection pad P2that is substantially ellipse in a plan view includes a major axis AX1that becomes longer as the distance increases from the plan view center of the corresponding substrate12to the plan view center B1of the block11. Furthermore, each connection pad P2of the substrates A2to A9has an elliptic plan view shape with a minor axis AX2that becomes shorter as the corresponding substrate12becomes farther from the plan view center B1. In other words, each connection pad P2of the substrates A2to A9has a plan view shape with an ellipticity, which is the ratio of the length (major diameter) of the major axis AX1and the length (minor diameter) of the minor axis AX2, set to be smaller as the corresponding substrate12becomes farther from the plan view center B1in the block11.

Thus, in the present example, each connection pad P2of the substrate A2has a smaller ellipticity than each connection pad P2of the substrate A3, which is closer to the plan view center B1of the block11than the substrate A2. In the present example, the distance from a plan view center B2of the substrate A2to the plan view center B1of the block11, the distance from a plan view center B4of the substrate A4to the plan view center B1, the distance from a plan view center B7of the substrate A7to the plan view center B1, and the distance from a plan view center B9of the substrate A9to the plan view center B1are all the same. Thus, the connection pads P2of the substrates A2, A4, A7, and A9are all set to have the same ellipticity. In the present example, the distance from a plan view center B3of the substrate A3to the plan view center B1of the block11, the distance from a plan view center B5of the substrate AS to the plan view center B1, the distance from a plan view center B6of the substrate A6to the plan view center B1, and the distance from a plan view center B8of the substrate A8to the plan view center B1are all the same. Thus, each connection pad P2of the substrates A3, A5, A6, and A8are all set to have the same ellipticity.

In the present example, the connection pads P2in the same substrate12are all set to have the same ellipticity. In other words, the connection pads P2of the same substrate12are all set to have the same size, that is, the ellipse of each connection pad P2has the same major diameter and the same minor diameter. Thus, connection pads P2of the same size are arranged at different angles in accordance with the positional relationship from the plan view center B1of the block11in each substrate.

Furthermore, the upper surfaces of the connection pads P2of every one of the substrates A1to A9in the block11are all set to have the same area. In other words, each connection pad P2of the substrate A1having the shape of a true circle in a plan view, each connection pad P2of the substrates A2, A4, A7, and A9having the shape of an ellipse in a plan view, and each connection pad P2of the substrates A3, A5, A6, and AS having the shape of an ellipse in a plan view are all set to have the same area.

In the present example, each connection pad P2of a substrate12(e.g., substrate A2) is formed so that its major axis AX1lies along a direction (see broken line arrow) extending from the plan view center of the connection pad P2toward the plan view center B1of the block11. In other words, the connection pads P2of the same substrate12are arranged at different angles in accordance with the positional relationship relative to the plan view center B1of the block11. However, there is no limit to such a structure. For example, the connection pads P2of a substrate12(e.g., substrate A2) may all be formed so that their major axes AX1lie along the same direction (e.g., direction from the plan view center of the substrate12(e.g., plan view center B2of the substrate A2) toward the plan view center B1of the block11). In other words, the connection pads P2may be arranged at the same angle in the same substrate12.

In the present example, the connection pads P2of the same substrate12are all set to have the same major diameter and the same minor diameter. However, there is no limit to such a structure. For example, the connection pads P2of the same substrate12may be set to have different major diameters and different minor diameters in accordance with the positional relationship relative to the plan view center B1of the block11. In other words, instead of setting the major diameter and the minor diameter for each of the substrates A2to A9, a different major diameter and minor diameter may be set for each of the connection pads P2in the substrates A2to A9.

As shown inFIG. 3, the wiring pattern33is arranged on the lower surface of the insulating layer24. In other words, the wiring pattern33is arranged on a surface (e.g., lower surface) of the substrate body20located on the side opposite to the mounting surface. The wiring pattern33includes external connection pads P3. An external connection terminal, such as a solder ball or a lead pin, used when mounting the substrate12on a mounting substrate, such as a motherboard, is arranged on each external connection pad P3. Although not shown in the drawings, the external connection pads P3are arranged in, for example, a matrix array. Each external connection pad P3has, for example, a circular plan view shape.

The solder resist layer35is arranged on the lower surface of the insulating layer24to cover portions of the wiring pattern33. The material of the solder resist layer35may be, for example, an insulative resin such as an epoxy resin or an acrylic resin. The solder resist layer35includes a plurality of openings35X exposing portions of the wiring pattern33as the external connection pads P3. The metal layer34is formed on portions of the wiring pattern33exposed from the openings35X, that is, the external connection pads P3. One example of the metal layer34is a metal layer in which an Ni layer and an Au layer are sequentially stacked from the lower surface of the wiring pattern33. Other examples of the metal layer34include a metal layer in which an Ni layer, a Pd layer, and an Au layer are sequentially stacked, a metal layer in which an Ni layer, a Pd layer, an Ag layer are sequentially stacked, and a metal layer in which an Ni layer, a Pd layer, an Ag layer, an Au layer are sequentially stacked from the lower surface of the wiring pattern33. For example, if the metal layer34is an Ni layer/Au layer, the thickness of the Ni layer may be about 0.05 to 5 μm, and the thickness of the Au layer may be about 0.01 to 1 μm. If an external connection pad P3is covered by the metal layer34, the metal layer34functions as an external connection pad.

An organic solderability preservative (OSP) process may be performed on the wiring pattern33exposed from the openings35X to form an OSP film in place of the metal layer34, and the external connection terminals may be connected to the OSP film. The wiring pattern33(when the metal layer34or the OSP film is formed on the wiring pattern33, the metal layer34or the OSP film) exposed from each opening35X may function as the external connection terminal.

The structure of the semiconductor package40(electronic component incorporated substrate) will now be described with reference toFIGS. 4 and 5. The substrate12of the semiconductor package40is the substrate A2shown inFIG. 1A.

As shown inFIG. 4, the semiconductor package40includes the substrate12(substrate A2), a semiconductor chip41, an underfill resin42, a substrate43, a solder ball44, and an encapsulation resin45.

The semiconductor chip41is flip-chip mounted on the substrate12. In other words, the semiconductor chip41is faced down when bonded to the substrate12by joining the bumps41aarranged on a circuit forming surface (e.g., lower surface) of the semiconductor chip41with the metal layer31formed on the corresponding chip pads P1. The semiconductor chip41is electrically connected to the chip pad P1by the bumps41aand the metal layer31.

A logic chip, such as a central processing unit (CPU) chip or a graphics processing unit (GPU) chip, may be used as the semiconductor chip41. Further, a memory chip such as a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, or a flash memory chip, may also be used as the semiconductor chip41. The size of the semiconductor chip41is, for example, about 3 mm×3 mm to 12 mm×12 mm in a plan view. The thickness of the semiconductor chip41is, for example, about 50 to 100 μm.

The bumps41amay be, for example, gold bumps or solder bumps. The material of a solder bump may be, for example, an alloy containing lead (Pb), an alloy of tin (Sn) and Au, an alloy of Sn and Cu, an alloy of Sn and Ag, or an alloy of Sn, Ag, and Cu. The height of each bump41ais, for example, about 20 to 70 μm.

The semiconductor chip41is mounted on the substrate12. However, there is no limit to such a structure, and other electronic components (e.g., capacitor or inductor) may be mounted on the substrate12.

The gap between the upper surface of the substrate12and the lower surface of the semiconductor chip41is filled with the underfill resin42. An insulative resin such as an epoxy resin may be used as the material of the underfill resin42.

The structure of the substrate43will now be described.

The substrate43includes through electrodes52formed in through holes51X of a core substrate51, an uppermost layer wiring pattern53, a metal layer54, a solder resist layer55, a lowermost layer wiring pattern56, a metal layer57, and a solder resist layer58. The through electrodes52electrically connect the wiring pattern53and the wiring pattern56. An insulative resin such as a glass epoxy resin may be used as the material of the core substrate51.

The wiring pattern53is arranged on an upper surface of the core substrate51. The material of the wiring pattern53may be, for example, copper or a copper alloy. The wiring pattern53includes component connection pads P4electrically connected to an electronic component (e.g., semiconductor chip or passive component) that differs from the semiconductor chip41and the semiconductor package. Each component connection pad P4has, for example, a circular plan view shape.

The solder resist layer55is stacked on the upper surface of the core substrate51to cover portions of the wiring pattern53. The material of the solder resist layer55may be, for example, an insulative resin such as an epoxy resin or an acrylic resin. The solder resist layer55includes openings55X exposing portions of the wiring pattern53as the component connection pads P4. The metal layer54is formed on portions of the wiring pattern53exposed from the openings55X, that is, the component connection pads P4. One example of the metal layer54is a metal layer in which the Ni layer/Au layer are sequentially stacked from the upper surface of the wiring pattern53. Other examples of the metal layer54include a metal layer in which an Ni layer, a Pd layer, an Au layer are sequentially stacked, a metal layer in which an Ni layer, a Pd layer, an Ag layer are sequentially stacked, and a metal layer in which an Ni layer, a Pd layer, an Ag layer, and an Au layer are sequentially stacked from the upper surface of the wiring pattern53. For example, if the metal layer54is an Ni layer/Au layer, the thickness of the Ni layer is about 0.05 to 5 μm, and the thickness of the Au layer is about 0.01 to 1 μm. If the component connection pad P4is covered by the metal layer54, the metal layer54functions as the component connection pad.

The wiring pattern56is arranged on the lower surface of the core substrate51. The wiring pattern56includes connection pads P5electrically connecting the substrate12and the substrate43.

The solder resist layer58is stacked on the lower surface of the core substrate51to cover portions of the wiring pattern56. An insulative resin such as an epoxy resin and an acrylic resin may be used as the material of the solder resist layer58. The solder resist layer58includes openings58X exposing portions of the wiring pattern56as the connection pads P5. The metal layer57is formed on portions of the wiring pattern56exposed from the openings58X, that is, the connection pads P5. One example of the metal layer57includes a metal layer in which an Ni layer and an Au layer are sequentially stacked from the lower surface of the wiring pattern56. Other examples of the metal layer57includes a metal layer in which an Ni layer, a Pd layer, an Au layer are sequentially stacked, a metal layer in which an Ni layer, a Pd layer, an Ag layer are sequentially stacked, and a metal layer in which an Ni layer, a Pd layer, an Ag layer, and an Au layer are sequentially stacked from the lower surface of the wiring pattern56. For example, if the metal layer57is an Ni layer/Au layer, the thickness of the Ni layer is about 0.05 to 5 μm, and the thickness of the Au layer is about 0.01 to 1 μm. If each connection pad P5is covered by the metal layer57, the metal layer57functions as the connection pad.

FIG. 5is a plan view schematically showing the positional relationship of the connection pads P2(openings32Y) and the connection pads P5(openings58X).

As shown inFIG. 5, the connection pad P5is arranged to face each connection pad P2of the substrate12and have a plan view shape that is substantially an ellipse. More specifically, the connection pads P5of the present example are arranged in a plurality of rows (e.g., two rows) surrounding the periphery of the semiconductor chip41in a plan view. Each connection pad P5has, for example, a circular plan view shape. The elliptical plan view shape of each connection pad P2has a major axis AX1lying along a direction extending from the connection pad P2toward an arbitrary point B10. The arbitrary point B10is, for example, a point located at a position corresponding to the plan view center B1of the block11shown inFIG. 2. Further, the arbitrary point B10is a point located on the same plane as the connection pad P2at the outer side of the semiconductor package40. Each connection pad P5is arranged so that the entire lower surface overlaps with a portion of the upper surface of the opposing connection pad P2in a plan view.

For example, in the present example, the plan view center C1of the substrate43is displaced from the plan view center B2of the substrate12(substrate A2) in the direction of the arrow in the drawing. In other words, the substrate43is mounted on the substrate A2with the plan view center C1displaced from the plan view center B2of the substrate A2in a direction extending toward the arbitrary point B10. Thus, the connection pads P5of the substrate43are also displaced from the plan view center of the opposing connection pad P2in the direction extending toward the arbitrary point B10. In this case, the major axis of each connection pad P2lies along displacement direction of the opposing connection pad P5. Thus, even if displacement occurs between the plan view center B2of the substrate A2and the plan view center C1of the substrate43, the entire lower surface of each connection pad P5faces the upper surface of the corresponding connection pad P2.

As shown inFIG. 4, each solder ball44is joined with each connection pad P5(metal layer57). Each solder ball44is also joined with the connection pad P2(metal layer31) of the substrate12. More specifically, the solder ball44is arranged between the substrate12and the substrate43. One end of the solder ball44is joined with the metal layer57, and the other end of the solder ball44is joined with the metal layer31. The solder ball44functions as a connection terminal electrically connecting the connection pad P2and the connection pad P5. The solder ball44also functions as a spacer for holding the distance (spaced distance) between the substrate12and the substrate43at a specified value.

The solder ball44of the present example has a structure in which a spherical copper core ball44A is covered with solder44B. In the solder ball44, the solder44B functions as a joining material. Thus, the solder44B joins the solder ball44with the connection pad P2and the connection pad P5. In the solder ball44, the copper core ball44A functions as a spacer. Thus, the height (diameter) of the copper core ball44A sets the height of the space between the substrate12and the substrate43in addition to the pitch of the solder balls44. The height of the copper core ball44A is set to be, for example, greater than the thickness of the semiconductor chip41. Specifically, the height of the copper core ball44A is set to be greater than the total thickness of the semiconductor chip41and the bump41a. For example, the height of the copper core ball44A may be about 100 to 200 μm. The pitch of the solder ball44may be, for example, about 200 to 400 μm.

The space between the substrate12and the substrate43is filled with the encapsulation resin45. The encapsulation resin45fixes the substrate43to the substrate12, and encapsulates the semiconductor chip41mounted on the substrate12. In other words, the encapsulation resin45functions as an adhesive that adheres the substrate12and the substrate43. The encapsulation resin45also functions as a protective layer for protecting the semiconductor chip41. Further, the encapsulation resin45increases the mechanical strength of the entire semiconductor package40.

The material of the encapsulation resin45may be, for example, an insulative resin such as an epoxy resin or a polyimide resin. The material of the encapsulation resin45may also be a resin material in which a filler, such as silica (SiO2), is mixed with an epoxy resin or a polyimide resin. Instead of silica, that material of the filler may be an inorganic compound such as a titanium oxide, aluminum oxide, aluminum nitride, silicon carbide, calcium titanate, zeolite, and the like, or an organic compound. The encapsulation resin45, for example, may be a mold resin formed through transfer molding, compression molding, injection molding, and the like.

A method for manufacturing the wiring substrate10will now be described.

First, as shown inFIGS. 6A and 6B, the core substrate21is prepared to manufacture the wiring substrate10. The core substrate21is, for example, a flat plate having a tetragonal shape in a plan view. A large substrate, from which a large number of substrates12are obtained, is used as the core substrate21. In detail, the core substrate21includes a plurality of (e.g., three) separate blocks11, as schematically shown inFIG. 6A. Each block11includes a predetermined array (e.g., 3×3 matrix array) of substrate formation regions E1, each of which is where a substrate12is formed. The large core substrate21is cut by a dicing blade or the like along a cutting line F1in a subsequent step after manufacturing the semiconductor package40. InFIGS. 6C to 7B, which will be described below, the structure of only one substrate formation region E1is shown for the sake of brevity.

In the step shown inFIG. 6C, the through holes21X are formed at certain locations of the core substrate21. The wall surfaces of the through holes21X are plated to form the through electrodes22and electrically connect the two surfaces of the core substrate21. Then, for example, a subtractive process is performed to form the wires25and26. Next, the insulating layers23and24are respectively formed on the upper surface and the lower surface of the core substrate21by vacuum laminating, heating, and hardening a resin film. The insulating layers23and24may be formed by applying and heating a paste or liquid of a resin. An opening is then formed in each of the insulating layers23and24. When necessary, desmearing is performed. Then, for example, a semi-additive is performed to form the vias27and28and the wiring patterns30and33.

In the step shown inFIG. 7A, the solder resist layer32including the openings32X for exposing portions of the wiring pattern30as the chip pads P1and the openings32Y for exposing portions of the wiring pattern30as the connection pads P2. The solder resist layer35includes the openings35X exposing portions of the wiring pattern33as the external connection pads P3. In the present step, the openings32Y and the connection pads P2are laid out and shaped as shown in the plan view ofFIG. 1B. Thus, the connection pads P2shaped to be substantially ellipse in a plan view are formed in the substrate formation region E1, which is located in the peripheral portion of the block11.

Then, for example, the metal layer31is formed on the chip pads P1and the connection pads P2by performing a non-electrolytic plating method, and the metal layer34is formed on the external connection pads P3. The above manufacturing steps allow the structure corresponding to the substrate12to be manufactured in each substrate formation region E1, and the wiring substrate10including a large number of substrates12to be manufactured.

A method for manufacturing the semiconductor package40will now be described.

First, in the step shown inFIG. 7B, the bumps41aof the semiconductor chip41are flip-chip bonded to the metal layer31formed on the chip pads P1. In other words, the semiconductor chip41is flip-chip mounted in each substrate formation region E1of the wiring substrate10. Then, the space between the semiconductor chip41and the solder resist layer32is filled with the underfill resin42.

As shown inFIGS. 8 and 9A, a substrate material60for forming the substrate43is prepared. The substrate material60, which is a single sheet of a substrate material used to form a plurality of substrates43, includes a plurality of substrate formation regions E2, which are where the substrates43are formed. In the substrate material60of the present example, the substrate formation regions E2are laid out in a predetermined planar array (e.g., 3×3 matrix) and, for example, in the same array as the substrate formation regions E1(substrates12) of the wiring substrate10.FIG. 8shows when a structure corresponding to the substrate43is formed in each substrate formation region E2, that is, when a large number of connection pads P5and the metal layer57are formed on the lower side of each substrate formation region E2. The substrate material60is cut with a dicing blade or the like into the substrates43in a subsequent step. This singulates structures corresponding to the substrates43. The structure corresponding to the substrate43can be manufactured through a known manufacturing method, which will briefly be described with reference toFIGS. 8 and 9A.FIGS. 9, 11, and 13shown the cross-sectional structure of the substrate material60in only one substrate formation region E2for the sake of brevity.

First, as shown inFIG. 9A, the through holes51X are formed at certain locations in the core substrate51, and the wall surfaces of the through holes51X are plated to form the through electrodes52that electrically connect the two surfaces of the core substrate51. Then, for example, a subtractive process is performed to form the wiring patterns53and56. Next, the solder resist layer55is formed including the openings55X exposing portions of the wiring pattern53as the component connection pads P4, and the solder resist layer58is formed including the openings58X exposing portions of the wiring pattern56as the connection pads P5. In this case, as shown inFIG. 8, the openings58X and the connection pads P5are formed along the periphery of each substrate formation region E2in the same manner as the openings32Y and the connection pads P2. Each opening58X and each connection pad P5has a substantially circular shape in a plan view. Each connection pad P5is, for example, set to have a smaller diameter then the connection pads P2of the substrate A1shaped as a substantially true circle in a plan view. InFIG. 8, the number of connection pads P5in each substrate formation region E2is reduced to show, in plan view, the layout and the shape of the connection pads P5in a simplified manner.

Then, as shown inFIG. 9A, the metal layer54is formed on the component connection pads P4, and the metal layer57is formed on the connection pads P5by performing, for example, non-electrolytic plating method. In the above manufacturing steps, the structure corresponding to the substrate43can be manufactured in each substrate formation region E2of the substrate material60.

In the step shown inFIG. 9B, the solder balls44are mounted on (joined with) the metal layer57. For example, after appropriately applying flux to the metal layer57, the solder balls44are mounted, and a reflow process is performed at a temperature of about 230° C. to 260° C. to fix the solder ball44on the metal layer57. Then, the surface is washed to remove the flux.

As shown inFIG. 10, three (i.e., same number as the number of blocks11arranged in the wiring substrate10) substrate materials60, each including a plurality of substrates43joined with the solder ball44, are manufactured in the manufacturing steps described above.

Then, in the step shown inFIG. 10, three substrate materials60are respectively stacked on the three blocks11of the wiring substrate10. In other words, the 3×3 substrates43arranged on each substrate material60are stacked on the 3×3 substrates12arranged in each block11.

Specifically, the substrate materials60are first arranged on the blocks11so that 3×3 substrates12in each block11are aligned with the 3×3 substrates43in the corresponding substrate material60in the vertical direction. More specifically, as shown inFIG. 11, the upper surface of the solder resist layer32in each substrate12and the lower surface of the solder resist layer58of each substrate43are faced toward each other, and positioned so that the metal layer31(connection pad P2) and the solder ball44(connection pad P5) face each other.

Then, the solder balls44are bonded to the upper surface of the metal layer31serving as pads. For example, after appropriately applying flux to the upper surface of the metal layer31, the substrate material60is arranged on the block11(substrate12) of the wiring substrate10with the solder balls44located in between, as shown inFIG. 12. A gap (space) is formed by the solder balls44between the solder resist layer32of each substrate12and the solder resist layer58of each substrate43. The wiring substrate10and the substrate material60, which are overlapped as described above, are then heated at a temperature of about 230° C. to 260° C. in a reflow furnace. This melts the solder44B of each solder ball44and joins the solder ball44with the metal layer31. Accordingly, the substrate material60is fixed to the wiring substrate10by the solder balls44, which electrically connect the connection pads P2and the connection pads P5. Although the reflow process is performed by pushing the substrate material60against the wiring substrate10in the present step, the interval between the substrate material60and the wiring substrate10is maintained at a predetermined distance since the copper core ball44A of the solder ball44functions as the spacer.

With reference toFIG. 13, the positional relationship of the connection pads P2and P5will now be described for a situation when the difference in the diagonal size of the plan view shape of the block11and the diagonal size of the plan view shape of the substrate material60are large in the steps shown inFIGS. 10 to 12.

First, in the step shown inFIG. 10, the substrate material60is stacked on the block11so that the plan view center C2of the substrate material60coincides with the plan view center B1of the block11. As shown inFIG. 13A, if the diagonal size of the plan view shape of the substrate material60is smaller than the diagonal size of the plan view shape of the block11, displacement occurs in the direction from the corner of the block11toward the plan view center B1of the block11. Thus, the connection pads P5of the substrate material60is arranged on the connection pad P2displaced in the direction from the plan view center of the corresponding connection pad P2toward the plan view center B1of the block11. In this case, the connection pads P2arranged on the substrates A2to A9positioned at the peripheral portion of the block11, where the displacement amount is large, are formed to have a plan view shape that is an ellipse with a major axis AX1lying in the direction extending from the plan view center of the connection pad P2toward the plan view center B1of the block11. Thus, as shown inFIG. 13B, the entire lower surface of the connection pad P5may face a portion of the upper surface of the corresponding connection pad P2even in the substrate A2located at the corner of the block11where the displacement amount is the largest.

As shown inFIG. 13C, if the diagonal size of the plan view shape of the substrate material60is greater than the diagonal size of the plan view shape of the block11, displacement occurs in the direction from the plan view center B1of the block11toward the corner of the block11(corner of the substrate material60). Thus, the connection pads P5are arranged on the connection pads P2displaced in a direction opposite to the direction from the plan view center of the corresponding connection pad P2toward the plan view center B1of the block11. In this case, the plan view shapes of the connection pads P2arranged on the substrates A2to A9are formed to be an ellipse having a major axis AX1lying in the direction extending from the plan view center of the connection pad P2toward the plan view center B1of the block11. Thus, as shown inFIG. 13D, the entire lower surface of each connection pad P5faces a portion of the upper surface of the corresponding connection pad P2even in the substrate A2located at the corner of the block11where the displacement amount is the largest.

Accordingly, in the step shown inFIG. 12, the connection pads P2and P5are aligned to face each other in the vertical direction. Thus, the solder balls44are bonded to the connection pads P5and properly mounted on the opposing connection pad P2. In other words, even if displacement occurs as shown inFIG. 13, the solder balls44stop or reduced movement of the edges of the openings32Y onto the solder resist layer32of the substrate12.

In the step shown inFIG. 14, the space between the wiring substrate10and the substrate material60, that is, the space between the solder resist layer32and the solder resist layer58is filled with the encapsulation resin45. For example, the encapsulation resin45is formed in the space between the wiring substrate10(substrate12) and the substrate material60(substrate43) in each block11(seeFIG. 10) by performing batch molding. The encapsulation resin45firmly fixes the wiring substrate10and the substrate material60and encapsulates the semiconductor chip41. Although not particularly illustrated, the encapsulating step is carried out by placing the structure shown inFIG. 12in a lower mold of a molding device (set of upper mold and lower mold), closing the lower mold with the upper mold, and injecting insulative resin into the corresponding block11through a mold gate (not shown) while heating and pressurizing the resin. In this case, if a thermosetting molding resin is used as the material of the encapsulation resin45, pressure (e.g., about 5 to 10 MPa) is applied to the interior of the molding device to drawn in fluid mold resin. Then, the mold resin is heated (heating temperature is, for example, 180° C.) and hardened to form the encapsulation resin45. Methods such as transfer molding, compression molding, injection molding, and the like may be performed to inject the molding resin.

The above manufacturing steps manufactures the structure corresponding to the semiconductor package40in each substrate formation region E1of the wiring substrate10and each substrate formation region E2of the substrate material60.

The structure shown inFIG. 14is cut with a dicing blade or the like along the cutting line F1of the block11to singulate a large number of semiconductor packages40. The above manufacturing steps batch-manufactures a large number of semiconductor packages40. The number of semiconductor packages40that are batch-manufactured is not particularly limited, and any number of semiconductor packages40can be batch-manufactured within a range the substrate12and the substrate43can prepare.

The present embodiment has the advantages described below.

(1) The plan view shape of each connection pad P2(plan view shape of the opening32Y of the solder resist layer32) is an ellipse having a major axis AX1lying in the direction extending from the connection pad P2toward the plan view center B1of the block11. Thus, even if displacement occurs between the connection pads P2and P5due to the difference in the diagonal size of the block11and the diagonal size of the substrate material60, the connection pads P2and the connection pads P5face each other in the vertical direction. Therefore, even if displacement occurs between the connection pads P2and P5, the solder balls44are properly mounted on the connection pads P2, and movement of the solder balls44onto the edges of the opening32Y of the solder resist layer32is prevented or reduced. Thus, insufficient solderability that may occur when the solder ball44moves onto the solder resist layer32is prevented or reduced. Furthermore, the lowering of the connection reliability caused by insufficient solderability is prevented or reduced.

(2) The solder balls44are properly mounted on the connection pads P2even if displacement occurs between the connection pads P2and P5due to the difference in the diagonal size of the block11and the diagonal size of the substrate material60. This allows for easy narrowing of the pitch of the connection pads P2and P5. In other words, even if the diameter of the solder balls44decreases as the pitch of the connection pads P2and P5narrows, the solder balls44may be properly mounted on the connection pads P2while absorbing the influence of dimensional errors of the block11and the substrate material60.

(3) The plan view shape of each connection pad P2arranged on the substrates A2to A9is formed such that the major axis AX1of the ellipse becomes longer as the block11of the substrate12including the connection pad P2becomes farther from the plan view center B1. Thus, even if the displacement amount between the connection pads P2and P5increases in the substrates A2, A4, A7, and A9located at the corners of the block11, for example, the solder balls44are properly mounted on the connection pads P2since the major axis AX1of each connection pad P2lies long along the direction of displacement.

(4) The plan view shape of each connection pad P2arranged on the substrates A2to A9is formed such that the minor axis AX2of the ellipse becomes shorter as the block11of the substrate12including the connection pad P2becomes farther from the plan view center B1. Thus, even if the major axis AX1becomes longer as the plan view center B1becomes farther, the area of the upper surface of each connection pad P2of the substrate12(e.g., substrate A2, A4, A7, or A9) separated from the plan view center B1remains the same. Therefore, the solder amount in each solder ball44neither increases nor decreases.

(5) The upper surfaces of every one of the connection pads P2in the block11are set to have the same area. Thus, the solder balls44of the block11all have the same solder amount.

Other Embodiments

In the embodiment described above, the connection pads P2of the substrates A2to A9located in the peripheral portion of the block11are formed to be substantially ellipse in a plan view. Instead, for example, only the connection pads P2of the substrates A2, A4, A7, and A9located at the corners of the block11may be formed to be substantially ellipse in a plan view. In this case, the connection pads P2arranged in the remaining substrates A1, A3, A5, A6, and A8are formed to be a substantially true circle in a plan view. For example, all the connection pads P2arranged in the block11may be formed to be substantially ellipse in a plan view.

In the embodiment described above, the predetermined array of the substrates12forming the block11is a matrix array. Instead, for example, the block11may be formed by substrates12laid out in strips. In other words, the array of the substrates12is not particularly limited as long as the wiring substrate includes the block11in which N×M (N is an integer greater than or equal to two, M is an integer greater than or equal to one) substrates12are laid out in a predetermined array.

For example, in the embodiment described above, the plan view center B1of the block11coincides with the plan view center of the substrate A1located at the center of the block11. However, the plan view center B1of the block11may not coincide with the plan view center of the substrate A1arranged at the central part of the block11depending on the array of the substrate12. In the embodiment described above, the number of non-peripheral portion substrate12(A1) that does not form the peripheral portion of the block11is one. However, the number of non-peripheral portion substrates12(A1) may be two or more depending on the array of the substrate12.

For example, as shown inFIG. 15, the block11may include the substrates12in a 7×4 matrix. In this example, only the connection pads P2of the substrates12(corner substrates D1to D4ofFIG. 15) located at the corners of the block11are substantially ellipse in a plan view. In this case, the connection pads P2of the remaining substrates12(non-corner substrates D5to D28ofFIG. 15) are substantially true circle in a plan view. Only the connection pads P2of the substrates12(peripheral portion substrates D1to D18ofFIG. 15) located at the peripheral portion of the block11are substantially ellipse in a plan view. In this case, the connection pads P2arranged on the remaining substrates12(non-peripheral portion substrates D19to D28ofFIG. 15) are substantially true circle in a plan view. All the connection pads P2arranged in the block11may be substantially ellipse in a plan view. In any case, each connection pad P2having a substantially elliptical shape in a plan view has a major axis AX1lying in the direction extending from the connection pad P2toward the plan view center B1of the block11(or direction from the substrate12including the connection pad P2toward the plan view center B1).

In the embodiment, each connection pad P2is formed to be substantially ellipse in a plan view. Instead, for example, each connection pad P5may be formed to be substantially ellipse in a plan view. In this case, for example, the solder balls44are first joined with the connection pads P2, and then the solder balls44are joined with the connection pads P5that are substantially ellipse in a plan view.

The connection pad P2is not limited to the substantially elliptical shape in a plan view as long as it has an elongated shape, and for example, may be changed to an elongated or non-square rectangular shape, or an oval or an elongated circle.

For example, as shown inFIG. 16, if the plan view shape of each connection pad P2is an elongated or non-square rectangular shape, a first axis AX3lies in the direction (see broken line arrow) from the connection pad P2toward the plan view center B1of the block11, and the length (long side) along the first axis AX3is longer than the length (short side) along a second axis AX4, which is orthogonal to the first axis AX3.

Thus, the plan view shape of the connection pad P2can be changed as long as it is a plan view shape in which the first axis AX3lies along the direction from the connection pad P2toward the plan view center B1of the block11and the length along the first axis AX3is formed to be longer than the length along the second axis AX4, which is orthogonal to the first axis AX3. The plan view shape of each connection pad P2may be a shape in which the first axis AX3lies along the direction from the substrate12including the connection pad P2toward the plan view center B1and the length along the first axis AX3is longer than the length along the second axis AX4.

In the embodiment, the upper surfaces of all the connection pads P2arranged in the block11are set to have the same area. However, the upper surfaces of the connection pads P2in the block11may have different areas.

In the embodiment, the length of the major axis AX1(first axis AX3) of the connection pad P2and the length of the minor axis AX2(second axis AX4) are both changed according to the positional relationship relative to the plan view center B1of the block11. Instead, for example, only the length of the major axis AX1(first axis AX3) of the connection pad P2may be changed in accordance with the positional relationship relative to the plan view center B1of the block11. In this case, for example, the length of the major axis AX1(first axis AX3) of each connection pad P2may be increased as the substrate12including the connection pad P2becomes farther from the plan view center B1, and the length of the minor axis AX2(second axis AX4) of the connection pad P2may be fixed.

In the substrate12of the embodiment, the structure of the inner layer from the wiring patterns30and33of the outermost layer is not particularly limited. In other words, the substrate12merely needs to have a structure in which the wiring patterns30and33of the outermost layer are electrically connected to each other through the substrate interior, and hence the structure of the inner layer from the wiring patterns30and33of the outermost layer is not particularly limited. For example, the structure and the material of the core substrate21are not particularly limited. The number of lower layer wirings (e.g., wires25,26) and the insulating layers (e.g., insulating layers23,24) that cover such lower layer wirings formed on the core substrate21is also not particularly limited. Alternatively, the substrate body20may be a coreless substrate without the core substrate21, in place of the build-up substrate with a core including the core substrate21.

In the substrate43of the embodiment, the structure of the inner layer from the wiring patterns53and56of the outermost layer is not particularly limited. In other words, the substrate43merely needs to have a structure in which the wiring patterns53and56of the outermost layer are electrically connected to each other through the substrate interior, and hence the structure of the inner layer from the wiring patterns53and56of the outermost layer is not particularly limited. For example, the structure and the material of the core substrate51are not particularly limited. The lower layer wirings and the insulating layers that cover such lower layer wirings may be formed to a required number of layers on the core substrate51. Alternatively, the substrate43may be a coreless substrate that does not include the core substrate51.

In the embodiment, the copper core ball44A is used as a conductive core ball of the solder ball44. Instead, a conductive core ball made from a metal other than copper, such as gold or nickel, may be used or a resin core ball made from resin may be used, for example, in place of the copper core ball44A. Alternatively, a solder ball in which the conductive core ball or the resin core ball is omitted may be used in place of the solder ball44.

In the semiconductor package40of the embodiment, a plurality of electronic components may be mounted on the substrate12.

The encapsulation resin45in the embodiment may be omitted.

In the embodiment, the semiconductor package40having a structure in which two substrates12and43are stacked upon each other by way of the solder balls44. Instead, for example, a semiconductor package may have a structure in which three or more substrates are stacked upon one another by way of the solder balls44.