Signal line for a display device, etchant, thin film transistor panel, and method for manufacturing the same

A thin film panel includes a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line, including a source electrode, and a drain electrode formed on the gate insulating layer or the semiconductor layer, and a pixel electrode connected to the drain electrode, wherein at least one of the gate line and the data line and drain electrode includes a first conductive layer made of a molybdenum Mo-niobium Nb alloy and a second conductive layer made of a copper Cu-containing metal.

This application claims priority to Korean patent application No. 10-2006-0095979, filed on Sep. 29, 2006, and all the benefits accruing therefrom under 35 U.S.C. §119, the contents of which in its entirety are herein incorporated by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a signal line for a display device, etchant, thin film transistor panel, and a method for manufacturing the same. More particularly, the present invention relates to a signal line for a display device having low line resistance and increased reliability, etchant, thin film transistor panel, and a method for manufacturing the same.

(b) Description of the Related Art

Generally, a flat panel display such as a liquid crystal display (“LCD”), an organic light emitting diode (“OLED”) display, and an electrophoretic display includes a pair of electric-field generating electrodes and an electro-optical active layer disposed therebetween. The LCD includes a liquid crystal layer as the electro-optical active layer, and the OLED display includes an organic light emitting layer as the electro-optical active layer.

One of the pair of field generating electrodes is usually coupled with a switching element to receive electrical signals, and the electro-optical active layer converts the electrical signals into optical signals to display images.

The switching element for the flat panel display includes a thin film transistor (“TFT”) having three terminals, and gate lines transmitting control signals for controlling the TFTs and data lines transmitting data signals to be supplied for the pixel electrodes through the TFTs are also provided in the flat panel display.

The gate lines and the data lines are lengthened when increasing the size of the flat panel display such that the line resistance of the gate and data lines is increased. Accordingly, to solve a signal delay due to the increase of the line resistance, the signal lines are generally made of a material having low resistivity.

However, the material having low resistivity has poor physical and chemical characteristics such as against external impact and durability such that its contact with other materials is easily corroded. As a result, the line resistance of the signal lines is not decreased. Furthermore, remnants and skews are greatly generated in a manufacturing process using the materials such that the reliability for the material of the signal lines is deteriorated.

BRIEF SUMMARY OF THE INVENTION

The present invention provides a thin film transistor (“TFT”) array and a method for manufacturing the same to achieve low line resistance and reliability for the material of the signal lines. The present invention also provides a signal line for a display device having low line resistance and increased reliability, and an etchant for use in the manufacture of a display device having the signal line.

According to exemplary embodiments of the present invention, a signal line includes a first conductive layer made of a molybdenum Mo-niobium Nb alloy, and a second conductive layer made of a copper Cu-containing metal. The first conductive layer may be disposed under the second conductive layer. The signal line may further include a third conductive layer made of a Mo—Nb alloy and disposed on the second conductive layer. The signal line may be a gate line or a data line transmitting a signal to a thin film transistor (“TFT”) of the display device.

According to other exemplary embodiments of the present invention, an etchant includes benzotriazole, citric acid, hydrogen peroxide, hydrofluoric acid, and deionized water. The etchant may include benzotriazole at about 0.1 to 1 wt %, citric acid at about 1 to 5 wt %, hydrogen peroxide at about 10 to 20 wt %, hydrofluoric acid at about 0.01 to 0.5 wt %, and deionized water for a remainder of the etchant.

According to still other exemplary embodiments of the present invention, a TFT array panel includes a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line, including a source electrode, and a drain electrode formed on the gate insulating layer or the semiconductor layer, and a pixel electrode connected to the drain electrode. At least one of the gate line and the data line and drain electrode includes a first conductive layer made of a Mo—Nb alloy and a second conductive layer made of a Cu-containing metal.

The first conductive layer may be disposed under the second conductive layer. The TFT array panel may further include a third conductive layer made of a Mo—Nb alloy and disposed on the second conductive layer.

The TFT array panel may further include ohmic contacts formed between the data line and drain electrode, and the semiconductor layer. The semiconductor layer may include a first portion having a substantially same planar shape as the data line and the drain electrode, and a second portion not covered by the data line and the drain electrode and disposed between the source electrode and the drain electrode.

According to yet other exemplary embodiments of the present invention, a method for forming a TFT array panel includes forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line, including a source electrode, and a drain electrode on the gate insulating layer or the semiconductor layer, and forming a pixel electrode connected to the drain electrode, wherein at least one of the gate line and the data line and drain electrode includes a first conductive layer made of a Mo—Nb alloy and a second conductive layer made of a Cu-containing metal.

The first conductive layer may be disposed under the second conductive layer. At least one of the gate line and the data line and drain electrode may further include a third conductive layer made of a Mo—Nb alloy disposed on the second conductive layer.

The first and second conductive layers may be etched under the same etch condition. The etch condition may be wet etching, and an etchant of the wet etching includes benzotriazole, citric acid, hydrogen peroxide, hydrofluoric acid, and deionized water. The etchant may include benzotriazole at about 0.1 to 1 wt %, citric acid at about 1 to 5 wt %, hydrogen peroxide at about 10 to 20 wt %, hydrofluoric acid at about 0.01 to 0.5 wt % and deionized water for a remainder of the etchant.

According to still other exemplary embodiments of the present invention, a TFT array panel includes a plurality of signal lines defining a plurality of pixel regions, wherein the signal lines include a first conductive layer made of a molybdenum Mo-niobium Nb alloy and a second conductive layer made of a copper Cu-containing metal.

The signal lines may further include a third conductive layer made of a molybdenum Mo-niobium Nb alloy, and the second conductive layer may be sandwiched between the first and second conductive layers.

The signal lines may include a plurality of gate lines and a plurality of data lines intersecting the gate lines.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which preferred and exemplary embodiments of the invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

A thin film transistor (“TFT”) array panel according to an exemplary embodiment of the present invention will now be described in detail with reference toFIGS. 1 to 3.

FIG. 1is a layout view of an exemplary TFT array panel for a liquid crystal display (“LCD”) according to an exemplary embodiment of the present invention, andFIGS. 2 and 3are sectional views of the exemplary TFT array panel shown inFIG. 1, taken along lines II-II and III-III.

A plurality of gate lines121and a plurality of storage electrode lines131are formed on an insulating substrate110made of a material such as, but not limited to, transparent glass or plastic.

The gate lines121transmit gate signals and extend substantially in a transverse direction, a first direction. Each of the gate lines121includes a plurality of gate electrodes124projecting downward towards an adjacent gate line121and an end portion129having a large area for contact with another layer or an external driving circuit. A gate driving circuit (not shown) for generating the gate signals may be mounted on a flexible printed circuit (“FPC”) film (not shown), which may be attached to the substrate110, directly mounted on the substrate110, or integrated with the substrate110. The gate lines121may extend to be connected to a driving circuit that may be integrated with the substrate110.

The storage electrode lines131are supplied with a predetermined voltage, and each of the storage electrode lines131includes a stem extending substantially parallel to the gate lines121and a plurality of pairs of storage electrodes133aand133bbranched from the stems. Each of the storage electrode lines131is disposed between two adjacent gate lines121, and a stem thereof is close to one of the two adjacent gate lines121. Each of the storage electrodes133aand133bhas a fixed end portion connected to the stem and a free end portion disposed opposite thereto. The fixed end portion of the storage electrode133bhas a large area, and the free end portion thereof is bifurcated into a linear branch and a curved branch. However, the storage electrode lines131may have various shapes and arrangements.

The gate lines121and the storage electrode lines131include lower layers124p,129p,131p,133ap, and133bpthat are preferably made of a molybdenum Mo-containing metal such as Mo and a Mo alloy, and upper layers124q,129q,131q,133aq, and133bqwhich are preferably made of a copper Cu-containing metal such as Cu and a Cu alloy. The Mo alloy is preferably a molybdenum-niobium Mo—Nb alloy including Mo and a small quantity of Nb. It is preferable that the thickness of the lower layers124p,129p,131p,133ap, and133bpis in the range of about 50 to 500 angstroms, more particularly 100 to 300 angstroms, and that the thickness of the upper layers124q,129q,131q,133aq, and133bqis in the range of about 1000 to 3000 angstroms, more particularly 1500 to 2500 angstroms.

As shown inFIGS. 2 and 3, the lower layers and the upper layers of the gate electrodes124, the end portions129, the storage electrode lines131, and the storage electrodes133aand133bare respectively denoted by adding “p” and “q” to the reference numbers of the gate electrodes124, the end portions129, the storage electrode lines131, and the storage electrodes133aand133b, respectively. The remainder of the gate lines121, although not shown in cross-section, may also have the lower and upper layers p and q as described above.

The Mo—Nb alloy layers124p,129p,131p,133ap, and133bphave a function of a barrier metal layer that reinforces adhesion between the Cu layers124q,129q,131q,133aq, and133bq, and the substrate110for preventing peeling and lifting, and prevent the Cu material of the upper layers124q,129q,131q,133aq, and133bqfrom oxidizing and diffusing to the substrate100.

Although not shown, Mo—Nb layers may be added as capping layers on the upper layers124q,129q,131q,133aq, and133bqto protect the upper layers124q,129q,131q,133aq, and133bqhaving poor quality for chemical resistance.

The lateral sides of the gate lines121and the storage electrode lines131are inclined relative to a surface of the substrate110, and the inclination angle thereof is in a range of about 30 to about 80 degrees.

A gate insulating layer140preferably made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate lines121, the storage electrode lines131, and on the exposed portions of the substrate110.

A plurality of semiconductor stripes151preferably made of hydrogenated amorphous silicon (“a-Si”) or polysilicon are formed on the gate insulating layer140. The semiconductor stripes151extend substantially in the longitudinal direction, a second direction substantially perpendicular to the first direction, and become wide near the gate lines121and the storage electrode lines131such that the semiconductor stripes151cover large areas of the gate lines121and the storage electrode lines131. Each of the semiconductor stripes151includes a plurality of projections154branched out toward the gate electrodes124such that they overlap the gate electrodes124.

A plurality of ohmic contact stripes and islands161and165are formed on the semiconductor stripes151. The ohmic contact stripes and islands161and165are preferably made of n+ hydrogenated a-Si heavily doped with an N-type impurity such as phosphorous, or they may be made of silicide. Each ohmic contact stripe161includes a plurality of projections163, and the projections163and the ohmic contact islands165are located in pairs on the projections154of the semiconductor stripes151, such that they are spaced apart on the projections154.

The lateral sides of the semiconductor stripes151and the ohmic contacts161and165are inclined relative to the surface of the substrate110, and the inclination angles thereof are preferably in a range of about 30 to about 80 degrees.

A plurality of data lines171and a plurality of drain electrodes175are formed on the ohmic contacts161and165and the gate insulating layer140.

The data lines171transmit data signals and extend substantially in the longitudinal direction, the second direction, to intersect the gate lines121. Each data line171also intersects the storage electrode lines131and runs between adjacent pairs of storage electrodes133aand133b. Each data line171includes a plurality of source electrodes173projecting toward the gate electrodes124and being curved like a crescent, and an end portion179having a large area for contact with another layer or an external driving circuit. A data driving circuit (not shown) for generating the data signals may be mounted on an FPC film (not shown), which may be attached to the substrate110, directly mounted on the substrate110, or integrated with the substrate110. The data lines171may extend to be connected to a driving circuit that may be integrated with the substrate110.

The drain electrodes175are separated from the data lines171and disposed opposite the source electrodes173with respect to the gate electrodes124. Each of the drain electrodes175includes a wide end portion and a narrow end portion. The wide end portion overlaps a storage electrode line131and the narrow end portion is partly enclosed by a respective source electrode173having the crescent or “U” shape.

A gate electrode124, a source electrode173, and a drain electrode175along with a projection154of a semiconductor stripe151form a TFT having a channel formed in the projection154disposed between the source electrode173and the drain electrode175.

The data lines171and the drain electrodes175preferably include three conductive layers, such as a lower layer171p,175p, a middle layer171q,175q, and an upper layer171r,175r. It is preferable that the lower layer171p,175pis made of a Mo-containing metal such as pure Mo, a molybdenum nitride alloy Mo—N, a Mo—Nb alloy, a molybdenum vanadium alloy Mo—V, a molybdenum titanium alloy Mo—Ti, and a molybdenum tungsten alloy Mo—W, that the middle layer171q,175qis made of a low resistivity metal such as a Cu-containing metal such as pure Cu and a Cu alloy for reducing signal delay or voltage drop, and that the upper layer171r,175ris made of a Mo-containing metal such as pure Mo, a Mo—N alloy, a Mo—Nb alloy, a Mo—V alloy, a Mo—Ti alloy, and a Mo—W alloy having good contact characteristics with indium tin oxide (“ITO”) and indium zinc oxide (“IZO”). It is preferable that the upper and the lower layers171p,171r,175p, and175rare made of a Mo—Nb alloy. In an alternative embodiment, the upper layer171r,175ras a capping metal may be omitted.

As shown inFIGS. 2 and 3, the lower layer, the middle layer, and the upper layer of the source electrode173, the drain electrode175, and the end portion179of the data line171are respectively denoted by adding “p”, “q”, and “r” to the reference numbers of the source electrode173, the drain electrode175, and the end portion179of the data line171, respectively.

The lower layers171pand175penhance the adhesiveness between the middle layers171qand175qand the under-layers such as the ohmic contact stripes and islands161and165to prevent the middle layers171qand175qof Cu from peeling and lifting. Furthermore, the lower layers171pand175pprevent the Cu of the middle layers171qand175qfrom diffusing into the lower layers such as the ohmic contacts161and165and the semiconductor stripes151by oxidation.

Also, the upper layers171rand175rprevent the middle layers171qand175qfrom being contaminated, corroded, or oxidized by the etchant in the manufacturing process, and the upper layers171rand175rprevent the Cu of the middle layers171qand175qfrom diffusing into other layers connected thereto.

The data lines171and the drain electrodes175have inclined edge profiles, and the inclination angles thereof are is a range of about 30 to about 80 degrees.

The ohmic contacts161and165are interposed only between the underlying semiconductor stripes151and the overlying conductors171and175thereon, and reduce the contact resistance there between. Although the semiconductor stripes151are narrower than the data lines171at most places, the width of the semiconductor stripes151becomes large near the gate lines121and the storage electrode lines131as described above, to smooth the profile of the surface, thereby preventing disconnection of the data lines171. The semiconductor stripes151may have almost the same planar shapes as the data lines171and the drain electrodes175as well as the underlying ohmic contacts161and165. However, the semiconductor stripes151include some exposed portions, which are not covered with the data lines171and the drain electrodes175, such as portions of the projections154located between the source electrodes173and the drain electrodes175.

A passivation layer180is formed on the data lines171, the drain electrodes175, and the exposed portions of the semiconductor stripes151, as well as on exposed portions of the gate insulating layer140. The passivation layer180is preferably made of an inorganic or organic insulator, and it may have a flat top surface. Examples of the inorganic insulator include silicon nitride and silicon oxide. The organic insulator may have photosensitivity and a dielectric constant of less than about 4.0, such as a-Si:C:O and a-Si:O:F formed by plasma enhanced chemical vapor deposition (“PECVD”). The passivation layer180may include a lower film of an inorganic insulator and an upper film of an organic insulator such that it takes the excellent insulating characteristics of the organic insulator while preventing the exposed portions of the semiconductor stripes151from being damaged by the organic insulator.

The passivation layer180has a plurality of contact holes182and185exposing the end portions179of the data lines171and the drain electrodes175, respectively. The passivation layer180and the gate insulating layer140have a plurality of contact holes181exposing the end portions129of the gate lines121, a plurality of contact holes183aexposing portions of the storage electrode lines131near the fixed end portions of the storage electrodes133a, and a plurality of contact holes183bexposing the linear branches of the free end portions of the storage electrodes133a.

A plurality of pixel electrodes191, a plurality of overpasses83, and a plurality of contact assistants81and82are formed on the passivation layer180. They are preferably made of a transparent conductor such as ITO or IZO, or a reflective conductor such as silver Ag, aluminum Al, chromium Cr, and alloys thereof.

The pixel electrodes191are physically and electrically connected to the drain electrodes175through the contact holes185such that the pixel electrodes191receive data voltages from the drain electrodes175. The pixel electrodes191supplied with the data voltages generate electric fields in cooperation with a common electrode of an opposing color filter panel (not shown) supplied with a common voltage, which determine the orientations of liquid crystal molecules (not shown) of a liquid crystal layer (not shown) disposed between the TFT array panel100and the color filter panel. A pixel electrode191and the common electrode form a capacitor referred to as a “liquid crystal capacitor,” which stores applied voltages after the TFT turns off.

A pixel electrode191overlaps a storage electrode line131including storage electrodes133aand133b. The pixel electrode191and a drain electrode175connected thereto and the storage electrode line131form an additional capacitor referred to as a “storage capacitor,” which enhances the voltage storing capacity of the liquid crystal capacitor.

The overpasses83cross over the gate lines121, and they are connected to the exposed portions of the storage electrode lines131and the exposed linear branches of the free end portions of the storage electrodes133bthrough the contact holes183aand183b, respectively, which are disposed opposite each other with respect to the gate lines121. The storage electrode lines131including the storage electrodes133aand133balong with the overpasses83can be used for repairing defects in the gate lines121, the data lines171, or the TFTs.

The contact assistants81and82are connected to the end portions129of the gate lines121, and the end portions179of the data lines171through the contact holes181and182respectively. The contact assistants81and82protect the end portions129, and179, and enhance the adhesion between the end portions129and179and external devices.

Now, an exemplary method of manufacturing the exemplary TFT array panel shown inFIGS. 1 to 3according to an exemplary embodiment of the present invention will be described with reference toFIGS. 4 to 15.

FIGS. 4,7,10, and13are layout views of the exemplary TFT array panel shown inFIGS. 1,2, and3in intermediate steps of an exemplary manufacturing method thereof according to an exemplary embodiment of the present invention,FIGS. 5 and 6are sectional views of the exemplary TFT array panel shown inFIG. 4taken along lines V-V and VI-VI,FIGS. 8 and 9are sectional views of the exemplary TFT array panel shown inFIG. 7taken along lines VIII-VIII and IX-IX,FIGS. 11 and 12are sectional views of the exemplary TFT array panel shown inFIG. 10taken along lines XI-XI and XII-XII, andFIGS. 14 and 15are sectional views of the exemplary TFT array panel shown inFIG. 13taken along lines XIV-XIV and XV-XV.

As shown inFIGS. 4 to 6, two metal films including a lower film made of Mo—Nb alloy and an upper film made of a Cu-containing metal are sequentially sputtered on an insulating substrate110made of a material such as, but not limited to, transparent glass or plastic, and are sequentially patterned by wet etching with a photoresist pattern to form a plurality of gate lines121including a plurality of gate electrodes124and an end portion129, and a plurality of storage electrodes131having a pair of storage electrodes133aand133b.

It is preferably that the thickness of the lower layer124p,129p,131p,133ap,133bpis in the range of 50 to 500 angstroms, more particularly 100 to 300 angstroms, and that the upper layer124q,129q,131q,133aq,133bqis in the range of 1000 to 3000 angstroms, more particularly 1500 to 2500 angstroms.

Also, the lower layers124p,129p,131p,133ap, and133bpand the upper layers124q,129q,131q,133aq, and133bqmay be patterned by one etch condition using an etchant, and the etchant may include benzotriazole, citric acid, hydrogen peroxide, hydrofluoric acid, and deionized water. It is preferable that the etchant includes benzotriazole at about 0.1 to 1 wt %, citric acid at about 1 to 5 wt %, hydrogen peroxide at about 10 to 20 wt %, hydrofluoric acid at about 0.01 to 0.5 wt %, and deionized water for the remainder, and the etchant may include additives such as surfactants.

As shown inFIGS. 7 to 9, after sequential deposition of a gate insulating layer140, an intrinsic a-Si layer, and an extrinsic a-Si layer, the extrinsic a-Si layer and the intrinsic a-Si layer are photo-etched to form a plurality of extrinsic semiconductor stripes164and a plurality of intrinsic semiconductor stripes151including a plurality of projections154on the gate insulating layer140. The gate insulating layer140is deposited with a thickness of about 2000 Å to about 5000 Å in a temperature range of 250 to 500° C.

As shown inFIGS. 10 to 12, three metal layers including a lower layer made of Mo—Nb alloy, a middle layer made of a Cu-containing metal, and an upper layer made of a Mo—Nb alloy are sequentially sputtered on the gate insulating layer140and on the extrinsic semiconductor stripes164and the intrinsic semiconductor stripes151, and are sequentially patterned by wet etching using one etch condition with a photoresist pattern to form a plurality of data lines171each including a plurality of source electrodes173and an end portion179, and a plurality of drain electrodes175, which includes the three metal layers171p,171q,171r,175p,175q, and175r. It is preferable that an etchant of the etch condition is the same or substantially the same as that for etching the gate lines121and the storage electrode lines131.

Portions of the extrinsic semiconductor stripes164formed from the extrinsic a-Si layer that are not covered with the data lines171and the drain electrodes175are removed by etching to complete a plurality of ohmic contact stripes161including a plurality of projections163and a plurality of ohmic contact islands165, and to expose portions of the projections154of the intrinsic semiconductor stripes151. Oxygen plasma treatment may follow thereafter in order to stabilize the exposed surfaces of the semiconductor stripes151.

As shown inFIGS. 13 to 15, a passivation layer180preferably made of an inorganic insulating material such as silicon nitride or an organic insulating material with photosensitivity or flatness is deposited on the data lines171, the drain electrodes175, and the exposed portions of the semiconductor stripes151, as well as on the exposed portions of the gate insulating layer140.

Thereafter, the passivation layer180and the gate insulating layer140are photo-etched to form a plurality of contact holes181,182, and185exposing the drain electrodes175, and the end portions129and179of the gate lines121and the data lines171, a plurality of contact holes183aexposing portions of the storage electrode lines131near the fixed end portions of the storage electrodes133a, and a plurality of contact holes183bexposing the linear branches of the free end portions of the storage electrodes133a.

Finally, with reference again toFIGS. 1 to 3, a transparent material such as ITO is sputtered and etched to form a plurality of pixel electrodes191, a plurality of contact assistants81and82, and a plurality of overpasses83on the passivation layer180.

A TFT array panel according to another exemplary embodiment of the present invention will be described in detail with reference toFIGS. 16 to 33.

FIG. 16is an exemplary layout view of an exemplary TFT array panel for an exemplary LCD according to another exemplary embodiment of the present invention, andFIGS. 17 and 18are sectional views of the exemplary TFT array panel shown inFIG. 16, taken along lines XVII-XVII and XVIII-XVIII, respectively.

Referring toFIGS. 16 to 18, layered structures of the exemplary TFT panels according to this exemplary embodiment are almost the same as those shown inFIGS. 1 to 3.

A plurality of gate lines121including gate electrodes124and end portions129and a plurality of storage electrode lines131including storage electrodes133aand133bare formed on a substrate110, and a gate insulating layer140, a plurality of semiconductor stripes151including projections154, and a plurality of ohmic contact stripes161including projections163and a plurality of ohmic contact islands165are sequentially formed thereon. A plurality of data lines171including source electrodes173and end portions179, and a plurality of drain electrodes175are formed on the ohmic contacts161and165and on the gate insulating layer140, and a passivation layer180is formed thereon. A plurality of contact holes181,182,183a,183b, and185are provided at the passivation layer180and/or the gate insulating layer140. A plurality of pixel electrodes190, a plurality of contact assistants81and82, and a plurality of overpasses83are formed on the passivation layer180.

Different from the LCD shown inFIGS. 1 to 3, the semiconductor stripes151except for the projections154have almost the same planar shapes as the data lines171and the drain electrodes175as well as the underlying ohmic contacts161and165. However, the semiconductor stripes151include some exposed portions, which are not covered with the data lines171and the drain electrodes175, such as portions located between the source electrodes173and the drain electrodes175.

An exemplary method of manufacturing the exemplary TFT array panel shown inFIGS. 16 to 18according to an exemplary embodiment of the present invention is next described in detail with reference toFIGS. 19 to 33, as well as with reference toFIGS. 16 to 18.

FIGS. 19,28, and31are layout views of an exemplary TFT array panel shown inFIGS. 16,17, and18in intermediate steps of an exemplary manufacturing method thereof according to an exemplary embodiment of the present invention,FIGS. 20 and 21are sectional views of the exemplary TFT array panel shown inFIG. 19taken along lines XX-XX and XXI-XXI,FIGS. 22 to 27are sectional views of the exemplary TFT array panel in intermediate steps of an exemplary manufacturing method thereof according to an exemplary embodiment of the present invention,FIGS. 29 and 30are sectional views of the exemplary TFT array panel shown inFIG. 28taken along lines XXIX-XXIX and XXX-XXX, andFIGS. 32 and 33are sectional views of the exemplary TFT array panel shown inFIG. 31taken along lines XXXII-XXXII and XXXIII-XXXIII.

As shown inFIGS. 19 to 21, two conductive films including a lower conductive film made of a Mo—Nb alloy and an upper conductive film made of made of a Cu-containing metal are sputtered in sequence on an insulating substrate110made of a material such as transparent glass. Next, the upper conductive film and the lower conductive film are wet-etched in sequence using a patterned photoresist film as an etch mask to form a plurality of gate lines121including a plurality of gate electrodes124and a plurality of end portions129, and a plurality of storage electrode lines131including a plurality of storage electrodes133aand133b. Thereafter, the photoresist etch mask is removed.

Referring toFIGS. 22 and 23, a gate insulating layer140, an intrinsic a-Si layer150, and an extrinsic a-Si layer160are sequentially deposited by chemical vapor deposition (“CVD”).

A conductive layer170including a lower conductive layer170pmade of a Mo—Nb alloy, a middle conductive layer170qmade of a Cu-containing metal, and an upper layer170rmade of Mo—Nb alloy is then deposited by sputtering.

Referring toFIGS. 24 and 25, a photoresist film with a thickness of about 1-2 microns is coated on the conductive layer170, and is exposed to light through an exposure mask and developed to form a photoresist film52,54having a position-dependent thickness.

The developed photoresist films52and54are portions of the photoresist film of different thicknesses. As shown inFIGS. 24 and 25, the developed photoresist film defines a plurality of portions, referred to herein as the first, second, and third portions. The first portions are located on wire areas A and the second portions are located on channel areas B, indicated by the features of the photoresist film labeled by reference numerals52and54, respectively. The third portions are located on the remaining areas C, where substantially all the photoresist film is removed, thus exposing underlying portions of the conductive layer170, in particular the upper layer170r. The thickness ratio of the photoresist film at features54and52is adjusted depending upon the process conditions in the subsequent process steps. For example, the thickness of the photoresist film at the second portions (i.e., at feature54) may be equal to or less than half of the thickness of the photoresist film at the first portions (i.e., at feature52).

The position-dependent thickness of the photoresist is obtained by several techniques, for example, by providing translucent areas on the exposure mask as well as transparent areas and light blocking opaque areas. The translucent areas may have a slit pattern or a lattice pattern, or they may be a thin film(s) with intermediate transmittance or intermediate thickness. When using a slit pattern, it is preferable that the width of the slits or the distance between the slits is smaller than the resolution of a light exposer used for the photolithography. Another example is to use a reflowable photoresist. In detail, once a photoresist pattern made of a reflowable material is formed by using a normal exposure mask with only transparent areas and opaque areas, it is subject to a reflow process to flow onto areas without the photoresist, thereby forming thin portions.

Referring toFIGS. 26 and 27, the conductive layer170of the third portions at remaining areas C are removed by wet etching to expose the underlying extrinsic a-Si layer160of the third portions, thus forming data metal pattern171,174,179.

Next, the third portions of the extrinsic a-Si layer160on the remaining areas C and of the intrinsic a-Si layer150that are not covered by a data metal pattern171,174, and179are removed, preferably by dry etching.

Next, the second portions54of the photoresist on the channel areas B are removed by an etch-back process to expose the second portions of the conductors174. The removal of the second portions54of the photoresist is performed either simultaneously with or independent from the removal of the third portions of the extrinsic a-Si layer160and of the intrinsic a-Si layer150. Residue of the second portions54of the photoresist remaining on the channel areas C is removed by ashing. At the same time, some amount of the exposed portions of the photoresist film at the first portion52is removed, thereby decreasing the thickness of the remaining photoresist film.

Referring toFIGS. 28 to 30, the data metal pattern171,174, and179is wet-etched using the first portions52of the photoresist as an etch mask, where each conductor174is now divided into a data line171and a plurality of drain electrodes175, and the portions of the extrinsic semiconductor stripe164between the source electrode173and the drain electrode175is now exposed.

Next, the first portions52of the photoresist are removed.

Then, although not shown inFIG. 28 to 30, the portions of the extrinsic semiconductor stripe164between the source electrode173and the drain electrode175are removed to divide the semiconductor stripe164into an ohmic contact stripe161and a plurality of ohmic contact islands165and to expose the underlying portion of the projections154of the semiconductor stripes151. Alternatively, the removal of the portions of the extrinsic semiconductor stripe164may be formed without or prior to the removal of the first portions52of the photoresist.

Referring toFIGS. 31 to 33, a passivation layer180is formed to cover the projections154that are not covered by the data lines171and the drain electrodes175. Thereafter, selected portions of the passivation layer180and the gate insulating layer140are patterned to form a plurality of contact holes181,182,183a,183b, and185.

Finally, with reference again toFIGS. 16 to 18, a plurality of pixel electrodes190, a plurality of contact assistants81and82, and a plurality of overpasses83are formed on the passivation layer180by sputtering and patterning to form an ITO or IZO layer.

FIG. 34is a graph showing skews of the gate lines and the data lines etched by using the etchant described above according to the exemplary embodiment of the present invention, andFIG. 35is a photograph showing remnants and tails of the gate lines and the data lines etched by using the etchant according to the exemplary embodiment of the present invention.

In these embodiments according to the present invention, the gate lines and the data lines were formed of a double layer of a lower Mo layer/an upper Cu layer (Mo/Cu), a quadruple layer of a first Mo layer/a second Cu layer/a third Cu—N alloy layer/a fourth Cu layer (Mo/Cu/CuN/Mo), which are sequentially layered, or a double layer of a lower Mo—Nb alloy layer/an upper Cu layer (MoNb/Cu), and were etched with various etch conditions to detect the skews, the remnants, and the tails.

Here, the skews represent the errors between photoresist patterns as an etch mask and the gate and data lines that were patterned by using the photoresist patterns as an etch mask.

As shown inFIG. 34, when the gate lines and the data line were formed of double layers of a lower Mo layer/an upper Cu layer (Mo/Cu), and the quadruple layer of a first Mo layer/a second Cu layer/a third Cu—N alloy layer/a fourth Cu layer (Mo/Cu/CuN/Mo), the skews were large in the range of about 1.1 to 2.75 microns. However, when the gate lines and the data lines were formed of a double layer of a lower Mo—Nb alloy layer/an upper Cu layer (MoNb/Cu) according to the exemplary embodiment of the present invention, the skews were remarkably decreased in the range of about 0.95 to 1.47 microns. Also, though the gate and data lines are etched under the same etch conditions, the skews were remarkably decreased.

Furthermore, as shown inFIG. 35, when the gate lines and the data lines were formed of double layers of a lower Mo layer/an upper Cu layer (Mo/Cu), and the quadruple layer of a first Mo layer/a second Cu layer/a third Cu—N alloy layer/a fourth Cu layer (Mo/Cu/CuN/Mo), a lot of the remnants and the tails were generated. However, when the gate lines and the data lines were formed of a double layer of a lower Mo—Nb alloy layer/an upper Cu layer (MoNb/Cu) according to the exemplary embodiment of the present invention, few remnants and tails remained.

As above-described, the signal lines are formed of a double layer including a lower Mo—Nb alloy layer/an upper Cu layer, and accordingly the contact characteristics of the upper layer may be reinforced, and the remnants and the skews may be greatly decreased in manufacturing processes such that the reliability for the material of the signal lines may be improved.

While the above exemplary embodiments have been described with reference to a bottom gate structure, it should be understood that the signal lines formed of a double layer including a lower Mo—Nb alloy layer/an upper Cu layer may also be advantageously formed within a TFT array panel having a top gate structure.