DEVICE HAVING RP CELL REGION INCLUDING L-SHAPE AND RESIDENT REGIONS AND METHOD OF MANUFACTURING SAME

A rectangular parallelepiped (RP) cell region includes: a 3D L-shape region, a dummy region and a resident region each of which includes transistor components, transistors of the resident region being free from comprising a function of the L-shape region; the dummy region and the resident region being in first notch formed by an arm and a stem of the L-shape region; first type transistors of the arm being stacked correspondingly over second type transistors of the first part of the stem; dummy transistor(s) of the dummy region being stacked over second type transistors of the second part of the stem; and first type transistors of the resident region being stacked over second type transistors of the third part of the stem.

BACKGROUND

The semiconductor integrated circuit (IC) industry produces a wide variety of analog and digital devices to address issues in a number of different areas. Developments in semiconductor process technology nodes have progressively reduced component sizes and tightened spacing resulting in progressively increased transistor density. ICs have become smaller.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, are used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus is otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein are likewise interpreted accordingly. In some embodiments, the term standard cell structure refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from a library thereof and are used as components in a layout diagram representing a circuit.

In some embodiments, a device includes a first rectangular parallelepiped (RP) cell region. The RP cell region includes groups of transistor components arranged in stacks according to a complementary field-effect transistor (CFET) architecture, where each group of transistor components represents a transistor. The first RP cell region includes a three-dimensional (3D) L-shape region, a dummy region and a resident region. The dummy region and the resident region are in a first notch of the L-shape region. The active transistors of the L-shape region have corresponding operabilities which comprise a function of the L-shape region that represents a function of the RP cell region. The dummy region includes one or more dummy transistors. The resident region includes one or more active transistors having corresponding operabilities which are free from comprising the function of the L-shape region. According to another approach, the notch of an L-shape region of an RP cell region was filled only with a dummy region. Relative to a first direction (e.g., parallel to the X-axis), the dummy region according to other approach is wider than the dummy region according to present embodiments. The larger dummy region according to the other approach wastes space.

An advantage of present embodiments of an RP cell region (which have an L-shape region whose first notch is filled with a dummy region and a resident region) is less wasted space as compared to the other approach because the dummy region of present embodiments is narrower than the dummy region according to the other approach. As such, a density of present embodiments of a device which includes the RP cell region which has an L-shape region whose first notch is filled with a dummy region and a resident region is greater than a density of a device which includes the RP cell region according to the other approach. An advantage of present embodiments of such a device (which includes the RP cell region which has an L-shape region whose first notch is filled with a dummy region and a resident region) is that inclusion of the resident region facilitates not only abutting but overlapping first and second instances of the RP cell region, where the second instance of the RP cell region is a complementarily oriented relative to the first instance of the RP cell region. In such present embodiments, abutting and overlapping of such RP cell regions (which have an L-shape region whose first notch is filled with a dummy region and a resident region) facilitates greater device densities as compared to the other approach.

In the first RP cell region, the L-shape region includes a stem and an arm. The stem extends in a first direction (e.g., parallel to the X-axis) and includes first, second and third parts. The arm extends from the first part of the stem in a second direction (e.g., parallel to the Z-axis) perpendicular to the first direction (X-axis) to form the first notch. Each of the arm and the resident region correspondingly includes one or more first type ones of the active transistors (first active transistors) (e.g., NFETs). The stem includes second type ones of the active transistors (second active transistors) (e.g., PFETs) configured with a second dopant type (e.g., P-type) different than the first dopant type. According to the CFET architecture, and relative to a third direction (e.g., parallel to the Z-axis): the one or more first type active transistors (e.g., NFETs) of the arm are stacked correspondingly with respect to one or more of the second active transistors (e.g., P-type) of the first part of the stem; the one or more dummy transistors of the dummy region are stacked correspondingly with respect to one or more of the second type active transistors (e.g., PFETs) of the second part of the stem, and the one or more first type active transistors (e.g., NFETs) of the resident region are stacked correspondingly with respect to one or more of the second type active transistors (PFETs) of the third part of the stem. When first and second instances of the RP cell region are not only abutted but overlapped, the one or more first type active transistors (e.g., NFETs) of each resident region are stacked correspondingly with respect to one or more of the second type active transistors (PFETs) of the third part of the corresponding stem.

FIG.1is a three-quarter perspective diagram of a complementary field-effect transistor (CFET) stack102, in accordance with some embodiments.

CFET stack102is includes an upper group of transistor components stacked on a lower group of transistor components. The upper group of transistors components represent a first type of metal-oxide field-effect (MOSFET) transistor which uses a first type of doping, e.g., negative type (N-type) doping, and is referred to as a first-type-channel MOSFET, e.g., a negative-channel MOSFET (NFET) or as an NMOS transistor. The lower group of transistors components represent a second type of MOSFET transistor which uses a second type of doping, e.g., positive type (P-type) doping, and is referred to as a second-type-channel MOSFET, e.g., a positive-channel MOSFET (PFET) or as a PMOS transistor. In some embodiments, the first type of doping is P-type and the second type of doping is N-type. In some embodiments, when CFET stack102is included as one of multiple CFET stacks in a CFET-based device, the upper group of transistors components is described as being included in an upper division of the CFET-based device, and the lower group of transistors is described as being included in the lower division of the CFET-based device.

InFIG.1, first, second and third orthogonal directions are assumed that are, e.g., correspondingly parallel to the X-axis, Z-axis and Y-axis.

The upper group includes an active region ARD1having the first type of dopant that extends parallel to the X-axis. First and second instances of an upper metal-to-source/drain (MD) contact UMD are formed correspondingly around first and second ends of active region ARD1. An upper metal-to-gate (MG) contact UMG is formed around a central region of active region ARD1such that the upper MG contact UMG is between the first and second instances of upper MD contact UMD.

The lower group includes an active region ARD2having the second type of dopant that extends parallel to the X-axis. First and second instances of a lower MD contact LMD are formed correspondingly around first and second ends of active region ARD2. A lower MG contact LMG is formed around a central region of active region ARD2such that the lower MG contact LMG is between the first and second instances of the lower MD contact LMD. In some embodiments, the lower active region has the first type dopant and the upper active region has the second type dopant.

InFIG.1, relative to the Z-axis: the active region ARD1is aligned over the active region ARD2; the first and second instances of the upper MD contact UMD are aligned correspondingly over the first and second instances of the lower MD contact MD; and the upper MG contact UMG is aligned over the lower MG contact UMG. Relative to the Z-axis, each of the upper MG contact UMG, the lower MG contact UMG, the first and second instances of the upper MD contact UMD, and the first and second instances of the lower MD contact MD correspondingly has upper and lower parts.

InFIG.1, an instance of an insulator106is formed between each of the following: the upper MG contact UMG and the lower MG contact UMG; the first instances of the upper MD contact UMD and the lower MD contact LMD; and the second instances of the upper MD contact UMD and the lower MD contact LMD. In some embodiments, the instance of insulator106between the upper MG contact UMG and the lower MG contact UMG is replaced with an MG-to-MG (G2G) contact (211FIG.2). In some embodiments, the instance of insulator106between the first instances of the upper MD contact UMD and the lower MD contact LMD is replaced with an MD-to-MD (D2D) contact (not shown). In some embodiments, the instance of insulator106between the second instances of the upper MD contact UMD and the lower MD contact LMD is replaced with a D2D contact (not shown).

FIG.2is a cross-section of a rectangular parallelepiped (RP) cell region200, in accordance with some embodiments.

InFIG.2, first, second and third orthogonal directions are assumed that are, e.g., correspondingly parallel to the X-axis, Z-axis and Y-axis.

RP cell region200includes groups of transistor components arranged in stacks202(1)-202(5) according to the CFET architecture (CFET stacks), where each group of transistor components represents a transistor. RP cell region also includes an L-shape region228, a dummy region238and a resident region242. Dummy region238and resident region242are in a first notch236of L-shape region228. An L-shape region, e.g., L-shape region228, has a shape resembling a three-dimensional uppercase letter L.

Active transistors are represented by the groups of transistor components in L-shape region228and resident region242. The active transistors represented by the groups of transistor components in L-shape region228have corresponding operabilities which comprise a function of L-shape region228. The function of L-shape region228represents a function of RP cell region200.

InFIG.2, one or more active transistors represented by the one or more groups of transistor components in resident region242have corresponding operabilities which are free from comprising the function of L-shape region228. Rather, the operabilities of the one or more active transistors of resident region242comprise a function of another cell region, e.g., a function of another L-shape region (e.g.,328(2)) of another RP cell region (e.g.,300(2)) where the function of the other L-shape region (e.g.,328(2)) represents the function of the other RP cell region (e.g.,300(2)). One or more groups of transistor components in dummy region238correspondingly represent one or more dummy transistors.

In RP cell region200, L-shape region228includes a stem230and an arm232. Stem230extends parallel to the X-axis and includes a first part234(1), a second part234(2) and a third part234(3). Arm232extends from first part234(1) of stem230along the Z-axis to form first notch236.

Each of arm232and resident region242correspondingly includes one or more first ones of the active transistors having the first type of dopant (first active transistors) (e.g., NFETs). Stem230includes second ones of the active transistors having the second type of dopant (second active transistors) (e.g., PFETs).

RP cell region200includes: an active region204D1having a first type of dopant (e.g., N-type) over an active region204D2having a second type of dopant (e.g., P-type); lower MG contacts212(1)-212(5); upper MG contacts210(1)-210(3) over corresponding lower MG contacts212(1),212(2) and212(5); upper DG contacts214(1)-214(2) over corresponding lower MG contacts212(1)-212(2); upper MD contacts224(1)-224(6) over corresponding lower MD contacts226(1)-226(6); instances of an MG-to-MG (G2G) contact211between upper MG contacts210(1)-210(2) and corresponding lower MG contacts212(1)-212(2); and instances of an insulator206between (A) upper MG contact210(3) and lower MG contact212(5), (B) upper DG contacts214(1)-214(2) and corresponding lower MG contacts212(3)-213(4), and (C) upper MD contacts224(1)-224(6) and corresponding lower MD contacts226(1)-226(6).

InFIG.2, examples of the upper groups include: upper MG contact210(1), upper MD contacts224(1)-224(2) and a corresponding portion of active region204D1which represent a first instance of the first active transistor (e.g., a first NFET) and is included in each of CFET stack202(1) and arm232of L-shape region228; upper MG contact210(2), upper MD contacts224(2)-224(3) and a corresponding portion of active region204D1which represent a second instance of the first active transistor (e.g., a second NFET) and is included in each of CFET stack202(2) and arm232of L-shape region228; upper MG contact210(3), upper MD contacts224(5)-224(6) and a corresponding portion of active region204D1which represent a third instance of the first active transistor (e.g., a third NFET) and is included in each of CFET stack202(5) and resident region242; upper DG contact214(1), upper MD contacts224(3)-224(4) and a corresponding portion of active region204D1which represent a first dummy transistor and is included in each of CFET stack202(3) and dummy region238; and upper DG contact214(2), upper MD contacts224(4)-224(5) and a corresponding portion of active region204D1which represent a second dummy transistor and is included in each of CFET stack202(4) and dummy region238.

InFIG.2, examples of the lower groups include: lower MG contact212(1), lower MD contacts226(1)-226(2) and a corresponding portion of active region204D2which represent a first instance of the second active transistor having the second type of dopant (e.g., a first PFET) and is included in each of CFET stack202(1) and stem230of L-shape region228; lower MG contact212(2), lower MD contacts226(2)-226(3) and a corresponding portion of active region204D2which represent a second instance of the second active transistor (e.g., a second PFET) and is included in each of CFET stack202(2) and stem230of L-shape region228; lower MG contact212(3), lower MD contacts226(3)-226(4) and a corresponding portion of active region204D2which represent a third instance of the second active transistor (e.g., a third PFET) and is included in each of CFET stack202(3) and stem230of L-shape region228; lower MG contact212(4), lower MD contacts226(4)-226(5) and a corresponding portion of active region204D2which represent a fourth instance of the second active transistor (e.g., a fourth PFET) and is included in each of CFET stack202(4) and stem230of L-shape region228; and lower MG contact212(5), lower MD contacts226(5)-226(6) and a corresponding portion of active region204D2which represent a fifth instance of the second active transistor (e.g., a fifth PFET) and is included in each of CFET stack202(5) and stem230of L-shape region228. In some embodiments, lower active region204D2has the first type of dopant and upper active region204D1has the second type of dopant.

RP cell region200further includes: upper isolation dummy gates (IDGs)218(1)-218(2) over corresponding lower IDGs220(1)-220(2); and instances of an insulator206between upper IDGs218(1)-218(2) and corresponding lower IDGs220(1)-220(2). In some embodiments, an upper IDG is aligned over a lower MG contact. In some embodiments, a lower IDG is aligned under an upper MG contact.

In some embodiments, an isolation dummy gate (e.g., each of upper IDGs218(1)-218(2) and lower IDGs220(1)-220(2)) is a dielectric structure that includes one or more dielectric materials and functions as an electrical isolation structure. Accordingly, an isolation dummy gate is not a structure that is electrically conductive and thus does not function, e.g., as an active gate of a transistor. An isolation dummy gate includes one or more dielectric materials and functions as an electrical isolation structure. In some embodiments, an isolation dummy gate is based on a gate structure as a precursor. In some embodiments, a dummy gate structure includes a gate conductor, a gate-insulator layer, (optionally) one or more spacers, or the like. In some embodiments, an isolation dummy gate is formed by first forming an upper MG contact or a lower MG contact, sacrificing/removing (e.g., etching) the upper or lower MG contact to form a trench, (optionally) removing a portion of an active region (e.g., active region204D1or204D2) that was formerly surrounded by the corresponding the upper or lower MG contact to deepen the trench, and then filling the trench with one or more dielectric materials such that the physical dimensions of the resultant electrical isolation structure, i.e., the upper or lower IDG, are similar to the dimensions of the upper or lower MG contact which was sacrificed. In some embodiments, an upper or lower IDG is a dielectric feature that includes one or more dielectric materials (e.g., oxide, nitride, oxynitride, or other suitable materials), and functions as an isolation feature. In some embodiments, an upper or lower IDG is a continuous polysilicon on oxide diffusion (OD) edge structure, and is referred to as an upper or lower CPODE structure.

InFIG.2, relative to the X-axis: upper IDG218(1), lower IDG220(1) and the corresponding instance of insulator206represent a left boundary of RP cell region200; and upper IDG218(2), lower IDG220(2) and the corresponding instance of insulator206represent a right boundary of cell region RP200.

FIGS.3A-3Bcorrespondingly are a side view and three-quarter perspective view of an RP cell region300(1), in accordance with some embodiments.

InFIGS.3A-3C, and inFIGS.3C-3Gas well, first, second and third orthogonal directions are assumed that are, e.g., correspondingly parallel to the X-axis, Z-axis and Y-axis.

InFIGS.3A-3B, RP cell region300(1) includes an L-shape region328(1), a dummy region338(1) and a resident region342(1). L-shape region328(1) includes a stem330and an arm332. Stem extends parallel to the X-axis and includes a first part334(1), a second part334(2) and a third part334(3). Arm332extends from first part334(1) of stem330along the Z-axis to form first notch336.

InFIGS.3A-3B, dummy region338(1) and resident region342(1) are in first notch336. Relative to the X-axis, dummy region338(1) is between arm332and resident region342(1). Arm332is aligned over first part334(1) of stem330. Dummy region33(1) is aligned over second part334(2) of stem330. Resident region342(1) is aligned over third part334(3) of stem330. Dummy region33(1) and second (334(2) and third (334(3) parts of stem330form a second notch344. Resident region342(1) is in second notch344.

FIG.3Cis a three-quarter perspective view of an RP cell region300(2), in accordance with some embodiments.

RP cell region300(2) is complementarily oriented relative to RP cell region300(1). Relative to each of the X-axis and the Y-axis, RP cell region300(2) is rotated 180 degrees relative to RP cell region300(1).

InFIG.3C, RP cell region300(2) includes an L-shape region328(2), a dummy region338(2) and a resident region342(2). L-shape region328(2) includes a stem330and an arm332. Stem extends parallel to the X-axis and includes a first part334(4), a second part334(5) and a third part334(6). Arm332extends from first part334(4) of stem330along the Z-axis to form first notch336(not called out inFIG.3C).

InFIG.3C, dummy region338(2) and resident region342(2) are in first notch336(not called out inFIG.3C). Relative to the X-axis, dummy region338(2) is between arm332and resident region342(2). Arm332is aligned under first part334(2) of stem330. Dummy region33(2) is aligned under second part334(2) of stem330. Resident region342(2) is aligned under third part334(3) of stem330. Dummy region33(2) and second (334(2) and third (334(3) parts of stem330form a second notch344(not called out inFIG.3C). Resident region342(2) is in second notch344.

FIG.3Dis a three-quarter perspective view of RP cell regions300(1) and300(2), in accordance with some embodiments.

InFIG.3D, relative to the X-axis, RP cell region300(2) is abutted to RP cell region300(1). Moreover, a portion of RP cell region300(2) overlaps a portion of RP cell region300(1). The overlapped portion of RP cell region300(1) includes third part334(3) and resident region342(1). The overlapped portion of RP cell region300(2) includes third part342(6) and resident region342(2).

InFIG.3D, in effect: third part334(6) of RP cell region300(2) represents resident region342(1) of RP cell region300(1); and third part342(3) of RP cell region300(1) represents resident region342(2) of RP cell region300(2).

In some embodiments, RP cell region300(1) is described as including a first U-shaped region of active transistors that includes L-shape region328(1) and resident region342(1), and where dummy region338(1) is in a gap of the first U-shaped region. In some embodiments, RP cell region300(2) is described as including a second U-shaped region of active transistors that includes L-shape region328(2) and resident region342(2), and where dummy region338(2) is in a gap of the second U-shaped region. A U-shape region has a shape resembling a three-dimensional uppercase letter U. In some embodiments, an uppercase letter U includes first and second stems extending parallel from corresponding first and second ends of a shared arm (or base), with a gap between the first and second stems. In some embodiments, the shared arm (or base) is arcuate. In some embodiments, the arcuate shared arm (or base) is referred to as a shared arch.

RP cell regions300(1) and300(2) share third part334(3) of RP cell region300(1) and third part334(6) of RP cell region300(2). As third part334(6) of RP cell region300(2) is stacked over third part334(3) of RP cell region300(1), third part334(6) of RP cell region300(2) and third part334(3) of RP cell region300(1) represent a CFET stack which is shared by RP cell regions300(1) and300(2).

According to the other approach, each of third part334(3) of RP cell region300(1) and third part334(6) of RP cell region300(2) would be counterpart dummy regions in counterpart first and second RP cell regions. The counterpart dummy regions according to the other approach are comprised of one or more groups of transistor components that correspondingly represent one or more dummy transistors. The counterpart dummy regions according to the other approach waste space. By contrast, the CFET stack represented by third part334(3) of RP cell region300(1) and third part334(6) of RP cell region300(2) correspondingly represents recovered, i.e., unwasted, regions358(1) and358(2) as compared to the other approach. As such, a density of present embodiments of a device which includes RP cell regions300(1)-300(2) rather than the counterpart first and second RP cell regions according to the other approach has a higher density than a device which includes the counterpart first and second RP cell regions according to the other approach.

FIG.3E-3Gare three-quarter perspective views of corresponding cell regions being abutted to each other, in accordance with some embodiments.

At the left side, each ofFIGS.3E-3Fincludes an RP cell region300(3).FIG.3Gincludes an RP cell region300(6) which is version of RP cell region300(3). Relative to a plane formed by the X-axis and the Z-axis, RP cell region300(6) ofFIG.3Gis mirror symmetric with respect to RP cell region300(3) ofFIGS.3E-3F. Each of RP cell regions300(3) and300(6) includes: an L-shape region328(3) and an internal RP region3561(1). Relative to the Y-axis, internal RP region3561(1) is abutted to L-shape regions328(3).

FIGS.3E-3Fare arranged into rows 1 and 2 that extend parallel to the X-axis. Regarding RP cell region300(3), internal RP region356(1) is in row 1 and L-shape region328(3) is in row 2.

In the middle,FIG.3Efurther includes an RP cell region300(4), the latter including an L-shape region328(4). Relative to each of the X-axis and the Y-axis, RP cell region300(2) is rotated 180 degrees relative to RP cell region300(1).RP cell region300(4) is in row 2. Relative to each of the X-axis and the Y-axis, RP cell region300(4) is rotated 180 degrees relative to RP cell region300(3).

At the right side ofFIG.3E, and relative to row 2, a space-recovering arrangement is shown in which L-shape region328(4) of RP cell region300(4) not only abuts but also partially overlaps L-shape region328(3) of RP cell region300(3).

RegardingFIG.3F, the middle ofFIG.3Ffurther includes an RP cell region300(5), the latter including an L-shape region328(5). Relative to the X-axis, L-shape region328(5) of RP cell region300(5) is rotated 180 degrees relative to L-shape region328(3) of RP cell region300(3). Relative to the Z-axis, RP cell region300(5) is rotated 90 degrees counterclockwise relative to RP cell region300(3).

FIG.3Fis further arranged to include a row 3 that extends parallel to the X-axis. RP cell region300(5) spans rows 2 and 3.

At the right side ofFIG.3F, and relative to row 2, a space-recovering arrangement is shown in which L-shape region328(5) of RP cell region300(5) not only abuts but also partially overlaps L-shape region328(3) of RP cell region300(3).

RegardingFIG.3G, the middle ofFIG.3Gfurther includes an RP cell region300(7), the latter including an L-shape region328(6) and in internal RP region356(2). RP cell region300(7) is complementarily oriented with respect to RP cell region300(6) as follows: relative to each of the X-axis and the Y-axis, an intermediary RP cell region (not shown) is rotated 180 degrees relative to RP cell region300(6); and relative to a plane formed the X-axis and the Y-axis, RP cell region300(7) is mirror symmetric with respect to the intermediary RP cell region (not shown).

FIG.3Fis further organized to include rows 4, 5 and 6 that extend parallel to the X-axis. Regarding RP cell region300(6), L-shape region328(3) is in row 5 and internal RP region356(1) is in row 6. Regarding RP cell region300(7), internal RP region356(2) is in row 4 and L-shape region328(6) is in row 5.

At the right side ofFIG.3G, and relative to row 6, a space-recovering arrangement is shown in which L-shape region328(6) of RP cell region300(7) not only abuts but also partially overlaps L-shape region328(3) of RP cell region300(6).

FIGS.4A-4Hare layout diagrams of corresponding arrangements of active regions, in accordance with some embodiments.

The layout diagrams ofFIGS.4A-4H(and in other layout diagrams disclosed herein) are representative of corresponding semiconductor devices. Structures in the semiconductor device are represented by patterns (also known as shapes) in the layout diagram. For simplicity of discussion, elements in the layout diagram ofFIGS.4A-4H(and also in other layout diagrams disclosed herein) will be referred to as if they are structures rather than patterns per se. For example, pattern404D1(1) inFIG.4Arepresents an active region having a first type of dopant, e.g., an N-type active region. In the following discussion, element404D1(1) is referred to active region404D1(1) rather than as active region pattern404D1(1).

InFIGS.4A-4H, as well as in other layout diagrams disclosed herein, an orthogonal Cartesian coordinate system is assumed in which a first direction is parallel to the X-axis, a second direction is parallel to the Y-axis and a third direction is parallel to the Z-axis. A layout diagram per se is a top view. Shapes in the layout diagram are two-dimensional relative to, e.g., the X-axis and the Y-axis, whereas the device being represented is three-dimensional. Relative to the Z-axis, upper division460is stacked on lower division462.

Each ofFIGS.4A-4Hrepresents a CFET stack that includes: one or more first active regions having a first type of dopant, e.g., an N-type dopant, in upper division460; and one or more second active regions having a second type of dopant, e.g., a P-type dopant, in lower division462. In some embodiments, the one or more lower active regions have the second type of dopant and the one or more upper active regions have the first type of dopant.

Layout diagrams vary in terms of the amount of detail represented. In some circumstances, selected layers of a layout diagram are combined/abstracted into a single layer, e.g., for purposes of simplification. Alternatively, and/or additionally, in some circumstances, not all layers of the corresponding semiconductor device are represented, i.e., selected layers of the layout diagram are omitted, e.g., for simplicity of illustration.FIGS.4A-4H, as well as in other layout diagrams disclosed herein, are examples of layout diagrams in which selected layers have been omitted. RegardingFIGS.4A-4H, show upper active regions, upper MG contacts, lower active regions and lower MG contacts, but omit other layers and structures for simplicity of illustration.

InFIGS.4A-4H, a size of an active region relative to the Y-axis is referred to as a width of the active region. InFIG.4A, upper active region404D1(1) and lower active region404D2(1) have substantially the same width. InFIG.4B, the width of upper active region404D1(2) is smaller than the width of lower active region404D2(1). InFIG.4C, the width of upper active region404D1(1) is larger than the width of lower active region404D2(2).

For a given CFET stack included in one or more of the present embodiments, togetherFIGS.4A-4Bshow the width of an upper active region and the width of the lower active region can be the same or different, i.e., the widths are independent of each other.

InFIGS.4D-4F, some of the active regions have a jog profile, namely upper active region404D1(3) and lower active region404D2(3). By contrast some of the active regions do not have a jog profile, namely active region404D1(1) and404D2(1). In some embodiments, an active region is described as having a jog profile when a size of the active region relative to a first axis (e.g., Y-axis) changes at different locations of the active region relative to a second axis (e.g., the X-axis). In some embodiments, an active region is described as having a jog profile when the width the active region changes at different locations along the X-axis. The jog profiles of upper active region404D1(3) and lower active region404D2(3) have an L-shape with a notch where the width changes. In some embodiments (not shown), a transition area of an active region having a jog profile, i.e., an area between corresponding MG contacts in which the width of the active region changes shape, has a shape substantially resembling a right trapezoid. In some embodiments (not shown), a transition area of an active region having a jog profile has a shape substantially resembling a type of trapezoid other than a right trapezoid.

InFIG.4D, upper active region404D1(1) and lower active region404D2(1) have substantially the same jog profile. InFIG.4E, upper active region404D1(3) has a jog profile whereas lower active region404D2(1). InFIG.4F, upper active region404D1(1) does not have a jog profile whereas lower active region404D2(3) does have a jog profile.

For a given CFET stack included in one or more of the present embodiments, togetherFIGS.4D-4Eshow the jog profile of an upper active region and the jog profile of the lower active region can be the same or different, i.e., the jog profiles are independent of each other.

In each ofFIGS.4G-4H, upper division460and lower division462have different numbers of active regions. InFIG.4G, upper division460of the CFET stack includes two active regions, namely active regions404D1(4) and404D1(5). Lower division462of the CFET stack ofFIG.4Gincludes one active region, namely active region404D2(1). The widths of active regions404D1(4) and404D1(5) are substantially the same and substantially smaller than the width of active region404D2(1). InFIG.4H, upper division460of the CFET stack includes one active region, namely active region404D1(1). Lower division462of the CFET stack ofFIG.4Hincludes two active regions, namely active regions404D2(4) and404D2(5). The widths of active regions404D2(4) and404D2(5) are substantially the same and substantially smaller than the width of active region404D2(1).

For a given CFET stack included in one or more of the present embodiments, togetherFIGS.4G-4Hshow that a total number of upper active regions and at total number of lower active regions can be the same or different, i.e., the total numbers are independent of each other.

In some embodiments, active region404D2(1) ofFIG.4Gis the result of having merged active regions404D2(4) and404D2(5) ofFIG.4H. In some embodiments, active region404D1(1) ofFIG.4His the result of having merged active regions404D1(4) and404D1(5) ofFIG.4G.

FIGS.5A-5Bare layout diagrams correspondingly of a lower division562(1) and an upper division560(2) of a CFET-based device, in accordance with some embodiments.

Together, lower division562(1) and upper division560(1) represent an inverter having a relative driving strength of D4, i.e., an INVD4 inverter. Together, lower division562(1) and upper division560(1) represent an RP cell that includes an L-shape region, a dummy region538(1) and a resident region542(1).

Lower division562(1) includes an arm532(1) of the L-shape region, dummy region538(1) and a resident region542(1).

Upper division560(1) includes a stem530(1) of the L-shape region.

FIGS.5A-5Bassume that lower division562(1) is configured for PMOS technology and upper division560(1) is configured for NMOS technology. In some embodiments, lower division562(1) is configured for NMOS technology and upper division560(1) is configured for PMOS technology.

FIGS.5C-5Dare layout diagrams correspondingly of a lower division562(2) and an upper division560(2) of a CFET-based device, in accordance with some embodiments.

Together, lower division562(2) and upper division560(2) represent an inverter having a relative driving strength of D4, i.e., an INVD4 inverter. Together, lower division562(2) and upper division560(2) represent an RP cell that includes an L-shape region, a dummy region538(2) and a resident region542(2).

Lower division562(2) includes a stem530(2) of the L-shape region.

Upper division560(2) includes an arm532(2) of the L-shape region, dummy region538(2) and a resident region542(2).

FIGS.5C-5Dassume that lower division562(2) is configured for PMOS technology and upper division560(2) is configured for NMOS technology. In some embodiments, lower division562(2) is configured for NMOS technology and upper division560(2) is configured for PMOS technology.

FIGS.6A-6Care partial layout diagrams of cell regions, in accordance with some embodiments.

In the context of populating a layout diagram with standard cells,FIGS.6A-6Cshow corresponding techniques for representing a border of a cell region that facilitate reducing a width of standard cells (relative to the X-axis) for purposes including placement of such standard cell regions into the layout diagram, thereby increasing densities of correspondingly resultant layout diagrams and devices manufactured based on such layout diagrams.

InFIG.6A, relative to the X-axis, cell regions670(1) and670(2) are abutted. A gate structure672(1) is shared by cell regions670(1) and670(2). Shared gate structure672(1) represents a common boundary, i.e., the right and left boundaries correspondingly of cell regions670(1) and670(2). Relative to the X-axis, the use of shared gate structure672(1) by cell regions670(1) and670(2) increases the density of a device which includes cell regions670(1) and670(2) as compared to counterpart abutting cell regions which do not share a gate structure on a common boundary.

InFIG.6B, relative to the X-axis, cell regions670(3) and670(4) are abutted. A common boundary, i.e., the right and left boundaries correspondingly of cell regions670(3) and670(4), passes through areas (shown with phantom (dashed) lines inFIG.6B) where MD contacts otherwise would have been formed. In some embodiments, an area where an MD contact otherwise would have been formed is referred to as a ghost MD.

The ghost MD contacts inFIG.6Bare shared by cell regions670(3) and670(4). The ghost MD contacts represent a common boundary, i.e., the right and left boundaries correspondingly of cell regions670(3) and670(4). Relative to the X-axis, the use of the shared ghost contacts by cell regions670(3) and670(4) increases the density of a device which includes cell regions670(3) and670(4) as compared to counterpart abutting cell regions which do not share ghost MD contacts on a common boundary.

FIG.6Cis similar toFIG.6Bexcept thatFIG.6Bfurther includes a cell region670(5).FIG.6Crepresents a two-input AND gate having a relative driving strength of D1, i.e., an AN2D1 type of AND gate. Among other things, cell region670(5) includes an IDG674in place of an active gate structure. Relative to the X-axis, cell region6705(5) is between cell regions670(3) and670(4).

InFIG.6C, relative to the X-axis, cell regions670(3) and670(5) are abutted. A common boundary, i.e., the right and left boundaries correspondingly of cell regions670(3) and670(5), passes through corresponding ghost MD contacts. Also, relative to the X-axis, cell regions670(5) and670(4) are abutted. A common boundary, i.e., the right and left boundaries correspondingly of cell regions670(5) and670(4), passes through corresponding ghost MD contacts.

FIGS.6D,6F and6Hare layout diagrams of a lower division of corresponding CFET-based devices, in accordance with some embodiments.

FIGS.6E,6G and6Iare layout diagrams of an upper division of corresponding CFET-based devices, in accordance with some embodiments.

FIGS.6D-6Hcorrespond to each other as follows:FIGS.6D &6Ecorrespond;FIGS.6F &6Gcorrespond; andFIGS.6H &6Icorrespond. Each ofFIGS.6D-6His example of using left and/or right boundaries of a corresponding upper division or lower division of a CFET-based standard cell region which intersect corresponding ghost MD contacts (ghost-MD-based boundaries) thereby facilitating placement of such standard cell regions into the layout diagram, and thereby increasing densities of correspondingly resultant layout diagrams and devices manufactured based on such layout diagrams.

The pairings ofFIGS.6D &6E,6F &6G and6H &6Irepresent an inverter having a relative driving strength of D4, i.e., an INVD4 inverter. Each ofFIGS.6D-6Iincludes area reductions, i.e., reductions in area,676(1) and676(2) on corresponding left and right sides resulting from using ghost-MD-based boundaries.

The pairings ofFIGS.6F &6G and6H &6Irepresent corresponding RP cell regions, each of which includes an L-shape region, a dummy region (DR) and a resident region (RR).

FIGS.6F and6Gare corresponding counterparts toFIGS.5A-5B. The lower division ofFIG.6Fincludes an arm632(1) of the L-shape region, a dummy region (DR)638(1) and a resident region (RR)642(1). The upper division ofFIG.6Gincludes a stem630(1) of the L-shape region.

FIGS.6F-6Gassume that lower division is configured for PMOS technology and upper division is configured for NMOS technology. In some embodiments, lower division is configured for NMOS technology and upper division is configured for PMOS technology.

FIGS.6H and6Iare corresponding counterparts toFIGS.5C-5D. The lower division ofFIG.6Hincludes a stem630(2) of the L-shape region. The upper division ofFIG.6Iincludes an arm632(2) of the L-shape region, a dummy region (DR)638(2) and a resident region (RR)642(2).

FIGS.6H-6Iassume that lower division is configured for PMOS technology and upper division is configured for NMOS technology. In some embodiments, lower division is configured for NMOS technology and upper division is configured for PMOS technology.

FIG.7Ais a flowchart700of a method of manufacturing a memory device, in accordance with some embodiments.

The method of flowchart (flow diagram)700is implementable, for example, using EDA system800(FIG.8, discussed below) and an IC manufacturing system900(FIG.9, discussed below), in accordance with some embodiments. Examples of a semiconductor device which can be manufactured according to the method of flowchart700include semiconductor devices based on the layout diagrams disclosed herein, or the like.

InFIG.7, the method of flowchart700includes blocks702-704. At block702, a layout diagram is generated which, among other things, includes one or more of layout diagrams disclosed herein, or the like. Block702is implementable, for example, using EDA system800(FIG.8, discussed below), in accordance with some embodiments.

In some embodiments, at block702, a method of generating a layout diagram includes:inspecting a first version of a layout diagram for RP cell regions according to the other approach, each of which includes an L-shape region and a dummy region but not a resident region; andreplacing one or more of the RP cell regions according to the other approach with RP cell regions each of which include the L-shape region, a resident region and a smaller dummy region. From block702, flow proceeds to block704.

At block704, based on the layout diagram, at least one of (A) one or more photolithographic exposures are made or (b) one or more semiconductor masks are fabricated or (C) one or more components in a layer of a semiconductor device are fabricated. See discussion below of IC manufacturing system900inFIG.9below.

FIG.7Bis a flowchart710of a method of fabricating a semiconductor device, and more particularly a first rectangular parallelepiped (RP) cell region, in accordance with some embodiments.

Flowchart710is an example of block704ofFIG.7A. Flowchart710includes blocks712-740. Examples provided in the context of the discussion of blocks712-740assume first, second and third orthogonal directions that are, e.g., correspondingly parallel to the X-axis, Z-axis and Y-axis. The method of flowchart710is implementable, for example, using IC manufacturing system900(FIG.9, discussed below), in accordance with some embodiments. Examples of a semiconductor device which can be manufactured according to the method of flowchart710include semiconductor devices based on three-quarter perspective drawings, cross-sectional drawings and/or the layout diagrams of RP cell regions disclosed herein, or the like.

At block712, lower groups of transistor components of the RP cell region are formed according to a complementary field-effect transistor (CFET) architecture. Examples of the first RP cell region include RP cell regions200ofFIG.2,300(1) ofFIGS.3A-3B, or the like. An example of the lower group includes the lower group ofFIG.1, or the like. Each of the lower groups represents a corresponding active transistor configured with a first dopant-type, i.e., a corresponding first active transistor. An example of the first dopant type is P-type dopant, or the like. Examples of the first active transistors are PMOS transistors ofFIGS.1-2, or the like.

The lower groups of the RP cell region represent a stem of an L-shape region included in the RP cell region, the stem extending the first direction (e.g., parallel to the X-axis). Examples of the L-shape region include L-shape regions228ofFIG.2,328(1) ofFIGS.3A-3B, or the like. Examples of the stem include stems230ofFIG.2,330ofFIGS.3A-3B, or the like. The stem includes first, second and third parts that correspondingly include one or more of the lower groups. Examples of the first part of the stem include first parts234(1) ofFIG.2,334(1) ofFIGS.3A-3B, or the like. Examples of the second part of the stem include second parts234(2) ofFIG.2,334(2) ofFIGS.3A-3B, or the like. Examples of the third part of the stem include third parts234(3) ofFIG.2,334(3) ofFIGS.3A-3B, or the like.

Block712ofFIG.7Bincludes blocks714-722. At block714, lower parts of lower metal-to-gate (MG) contacts are formed. Examples of the lower MG contacts include lower MG contact LMG ofFIG.1, lower MG contacts212(1)-212(5) ofFIG.2, or the like. An example of the lower part of a lower MG contact is the lower part of lower MG contact LMG ofFIG.1, or the like. From block714, flow proceeds to block716.

At block716, lower parts of lower metal-to-source/drain (MD) contacts are formed. Examples of the lower MD contacts include lower MD contacts LMD ofFIG.1, lower MD contacts226(1)-226(6) ofFIG.2, or the like. An example of the lower part of a lower MD contact is the lower part of lower MD contacts LMD ofFIG.1, or the like. From block716, flow proceeds to block718.

At block718, a first active region is formed, portions thereof being on corresponding portions of the lower parts of the lower MG contacts and the lower parts of the lower MD contacts. Examples of the first active region include active region ARD2ofFIG.1,204D2ofFIG.2, or the like. From block718, flow proceeds to block720.

At block720, upper parts of the lower MG contacts are formed on corresponding portions of the lower parts of the lower MG contacts and corresponding portions of the first active region. An example of the upper part of a lower MG contact is the upper part of the lower MG contact LMG ofFIG.1, or the like. From block720, flow proceeds to block722.

At block722, upper parts of the lower MD contacts are formed on corresponding portions of the lower parts of the lower MD contacts and corresponding portions of the first active region. Examples of the upper part of a lower MG contact include the upper parts of the lower MD contacts LMD ofFIG.1, or the like. From block722, flow exits block714and proceeds to block724.

At block724, MG-to-MG (G2G) contacts are formed on corresponding portions of the upper parts of the lower MG contacts. Examples of the G2G contacts include G2G contacts211ofFIG.2, or the like. In some embodiments, insulators (e.g.,206) are formed instead of one or more of the G2G contacts. From block724, flow proceeds to block726.

At block726, MD-to-MD (D2D) contacts are formed on corresponding portions of the upper parts of the lower MD contacts. No D2D contacts are shown inFIG.2. However, in some embodiments, one or more instances of an insulator (e.g.,206), otherwise formed on the upper parts of the lower MD contacts, are replaced with corresponding instances of D2D contacts. From block726, flow proceeds to block728.

At block728, insulators are formed on corresponding portions of the upper parts of the lower MG contacts and/or on corresponding portions of the upper parts of the lower MD contacts. Examples of the insulators include the instances of insulator206on lower MG contacts212(3)-212(5) ofFIG.2, the instances of insulator206on lower MD contacts226(1)-226(6) ofFIG.2, or the like. In some embodiments, one or more instances of insulator206on corresponding lower MG contacts are replaced with instances of G2G contact211. In some embodiments, one or more instances of insulator206on corresponding lower MD contacts are replaced with instances of a D2D contact (not shown). From block728, flow proceeds to block730.

At block730, relative to the second direction (e.g., parallel to the Z-axis), upper groups of transistor components are formed according to the CFET architecture over corresponding ones of the lower groups of transistor components. An example of the upper group includes the upper group ofFIG.1, or the like.

A first set of the upper groups is over the first part (e.g.,334(1)) of the stem (330) and represents an arm of the L-shape region. Examples of the arm include arms232of L-shape region228ofFIG.2,332of L-shape region328(1) ofFIGS.3A-3B, or the like. The arm extends in the second direction (e.g., parallel to the Z-axis) from the first part (e.g.,334(1)) of the stem (e.g.,330) to form a first notch. An example of the first notch is first notch336ofFIG.336ofFIGS.3A-3B, or the like.

A second set of the upper groups is over the second part (e.g.,334(2)) of the stem (e.g.,330) and represents a dummy region included in the RP cell region (e.g.,302(1)). Examples of the dummy region include dummy regions238ofFIG.2,338(1) ofFIGS.3A-3B, or the like. A third set of the upper groups is over the third part (e.g.,334(3)) of the stem (e.g.,330) and represents a resident region. Examples of the resident region include resident regions242ofFIG.1,342(1) ofFIGS.3A-3B, or the like. The dummy region and the resident region are in the first notch (e.g.,336).

Each upper group of the arm (e.g.,332) and the resident region (e.g.,342(1) represents a corresponding active transistor configured with a second dopant-type, i.e., a second active transistor. An example of the second dopant type is N-type dopant, or the like. Examples of the second active transistors are NMOS transistors ofFIGS.1-2, or the like. Each upper group of the dummy region (e.g.,338(1) represents a corresponding dummy transistor.

The lower groups and upper groups of the L-shape region (e.g.,228,328(1)) have corresponding operabilities which comprise a function of the L-shape region that represents a function of the RP cell region (e.g.,202,302(1)). The upper groups of the resident region (e.g.,342(1) have corresponding operabilities which are free from comprising the function of the L-shape region (e.g.,328(1)).

Block730includes blocks732-740. At block732, lower parts of upper MG contacts are formed over corresponding ones of the upper parts of the lower MG contacts (e.g.,212(1)-212(3)) and on corresponding ones of the G2G contacts (e.g.,211) or the insulator (e.g.,206). Examples of the upper MG contacts include upper MG contact UMG ofFIG.1, upper MG contacts210(1)-210(3) ofFIG.2, or the like. An example of the lower part of a upper MG contact is the lower part of upper MG contact LMG ofFIG.1, or the like. From block730, flow proceeds to block732.

At block734, lower parts of upper MD contacts are formed over corresponding ones of the upper parts of the lower MD contacts (e.g.,226(x)) and on corresponding ones of the insulator (e.g.,206) or the D2D contacts (the latter not being shown). Examples of the upper MD contacts include upper MD contacts UMD ofFIG.1, upper MD contacts224(1)-224(6) ofFIG.2, or the like. An example of the lower part of a upper MD contact is the lower part of upper MD contacts UMD ofFIG.1, or the like. From block734, flow proceeds to block736.

At block736, a second active region is formed, portions thereof being on corresponding portions of the lower parts of the upper MG contacts and the lower parts of the upper MD contacts. Examples of the second active region include active region ARD1ofFIG.1,204D1ofFIG.2, or the like. From block736, flow proceeds to block738.

At block738, upper parts of the upper MG contacts are formed on corresponding portions of the lower parts of the upper MG contacts and corresponding portions of the second active region. An example of the upper part of a upper MG contact is the upper part of the upper MG contact UMG ofFIG.1, or the like. From block738, flow proceeds to block740.

At block740, upper parts of the upper MD contacts are formed on corresponding portions of the lower parts of the upper MD contacts and corresponding portions of the second active region. Examples of the upper part of a upper MG contact include the upper parts of the upper MD contacts UMD ofFIG.1, or the like. From block740, flow exits block730.

In some embodiments, regarding the dummy region (e.g.,338(1)), block730includes the following. Lower parts of upper dummy MG (DG) contacts are formed, e.g., before forming the second active region at block736. Upper parts of the upper DG contacts are formed, e.g., before the upper parts of the upper MD contacts are formed at block740. The lower parts of upper dummy MG (DG) contacts are formed over corresponding ones of the upper parts of the lower MG contacts and on corresponding ones of insulator (e.g.,206), the latter being on upper parts of corresponding lower MG contacts (e.g.,212(3)-212(4). Examples of the upper DG contacts include upper DG contacts214(1)-214(2) ofFIG.2, or the like. The upper parts of the upper DG contacts are formed on corresponding portions of the lower parts of the upper DG contacts (214(1)-214(2)) and corresponding portions of the second active region (e.g.,204D1).

FIG.8is a block diagram of an electronic design automation (EDA) system800in accordance with some embodiments.

In some embodiments, EDA system800includes an automatic placement and routing (APR) system. In some embodiments, EDA system800is a general purpose computing device including a hardware processor802and a non-transitory, computer-readable storage medium804. Storage medium804, amongst other things, is encoded with, i.e., stores, computer program code806, i.e., a set of executable instructions. Execution of instructions806by hardware processor802represents (at least in part) an EDA tool which implements a portion or all of, e.g., the method ofFIG.5(block502), methods of generating layout diagrams such asFIGS.2B-2R, methods of generating layout diagrams corresponding to block diagrams such asFIGS.1A-1H, or the like, in accordance with one or more embodiments (hereinafter, the noted processes and/or methods). Storage medium804, amongst other things, stores layout diagrams811such as the layout diagrams disclosed herein, other the like.

Processor802is electrically coupled to computer-readable storage medium804via a bus808. Processor802is further electrically coupled to an I/O interface810by a bus808. A network interface812is further electrically connected to processor802via bus808. Network interface812is connected to a network814, so that processor802and computer-readable storage medium804are capable of connecting to external elements via network814. Processor802is configured to execute computer program code806encoded in computer-readable storage medium804in order to cause system800to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor802is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, storage medium804stores computer program code806configured to cause system800(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium804further stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium804stores library807of standard cells including such standard cells as disclosed herein. In some embodiments, storage medium804stores one or more layout diagrams811.

EDA system800further includes network interface812coupled to processor802. Network interface812allows system800to communicate with network814, to which one or more other computer systems are connected. Network interface812includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems800.

System800is configured to receive information through I/O interface810. The information received through I/O interface810includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor802. The information is transferred to processor802via bus808. EDA system800is configured to receive information related to a user interface (UI) through I/O interface810. The information is stored in computer-readable medium804as UI842.

FIG.9is a block diagram of an integrated circuit (IC) manufacturing system900, and an IC manufacturing flow associated therewith, in accordance with some embodiments.

Based on the layout diagram generated by block502ofFIG.5, the IC manufacturing system900implements block504ofFIG.5wherein at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of an inchoate semiconductor integrated circuit is fabricated using manufacturing system900.

InFIG.9, IC manufacturing system900includes entities, such as a design house920, a mask house930, and an IC manufacturer/fabricator (“fab”)950, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device960. The entities in system900are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and supplies services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house920, mask house930, and IC fab950is owned by a single larger company. In some embodiments, two or more of design house920, mask house930, and IC fab950coexist in a common facility and use common resources.

Design house (or design team)920generates an IC design layout922. IC design layout922includes various geometrical patterns designed for an IC device960. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device960to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout922includes various IC features, such as an active region, gate terminal, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Source/drain region(s) may refer to a source or a drain, individually or collectively, dependent upon the context. Design house920implements a proper design procedure to form IC design layout922. The design procedure includes one or more of logic design, physical design or place and route. IC design layout922is presented in one or more data files having information of the geometrical patterns. For example, IC design layout922is expressed in a GDSII file format or DFII file format.

Mask house930includes data preparation932and mask fabrication934. Mask house930uses IC design layout922to manufacture one or more masks935to be used for fabricating the various layers of IC device960according to IC design layout922. Mask house930performs mask data preparation932, where IC design layout922is translated into a representative data file (“RDF”). Mask data preparation932supplies the RDF to mask fabrication934. Mask fabrication934includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The design layout is manipulated by mask data preparation932to comply with particular characteristics of the mask writer and/or requirements of IC fab950. InFIG.9, mask data preparation932, mask fabrication934, and mask935are illustrated as separate elements. In some embodiments, mask data preparation932and mask fabrication934are collectively referred to as mask data preparation.

In some embodiments, mask data preparation932includes a mask rule checker (MRC) that checks the IC design layout that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to compensate for limitations during mask fabrication934, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

The above description of mask data preparation932has been simplified for the purposes of clarity. In some embodiments, mask data preparation932includes additional features such as a logic operation (LOP) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to IC design layout922during data preparation932may be executed in a variety of different orders.

After mask data preparation932and during mask fabrication934, a mask935or a group of masks935are fabricated based on the modified IC design layout. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The masks are formed in various technologies. In some embodiments, the mask is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, the mask is formed using a phase shift technology. In the phase shift mask (PSM), various features in the pattern formed on the mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask is an attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication934is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in the semiconductor wafer, in an etching process to form various etching regions in the semiconductor wafer, and/or in other suitable processes.

IC fab950uses mask (or masks)935fabricated by mask house930to fabricate IC device960using fabrication tools952. Thus, IC fab950at least indirectly uses IC design layout922to fabricate IC device960. In some embodiments, a semiconductor wafer953is fabricated by IC fab950using mask (or masks)935to form IC device960. Semiconductor wafer953includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).

In some embodiments, a device includes: a first rectangular parallelepiped (RP) cell region including a three-dimensional (3D) L-shape region, a dummy region and a resident region; the L-shape region including active transistors having corresponding operabilities which comprise a function of the L-shape region that represents a function of the RP cell region; the resident region including one or more active transistors having corresponding operabilities which are free from comprising the function of the L-shape region; the L-shape region including a stem including first, second and third parts, and an arm extending from the first part of the stem to form a first notch, and the dummy region and the resident region being in the first notch; and first type active transistors (first active transistors) of the arm being stacked correspondingly with respect to one or more second type active transistors (second active transistors) of the first part of the stem; one or more dummy transistors of the dummy region being stacked correspondingly with respect to one or more of the second active transistors of the second part of the stem; and one or more first active transistors of the resident region being stacked correspondingly with respect to one or more second active transistors of the third part of the stem.

In some embodiments, the dummy region is between the resident region and the arm.

In some embodiments, the first RP cell region includes a second RP cell region; and the second RP cell region is abutted to each of arm, stem, dummy region and resident region.

In some embodiments, the first RP cell region includes: a first active region extends through each of the arm and the notch; and a second active region extends through the stem; and the first active region and the second active region have substantially a same width.

In some embodiments, the first RP cell region includes: a first active region extends through each of the arm and the notch; and a second active region extends through the stem; and the first active region and the second active region have substantially different widths.

In some embodiments, the first RP cell region includes: a first active region extends through each of the arm and the notch; and a second active region extends through the stem; and the first active region and the second active region have corresponding first and second jog-profiles.

In some embodiments, the first jog-profile of the first active region and the second jog-profile of the second active region are substantially different.

In some embodiments, the first jog-profile of the first active region and the second jog-profile of the second active region are substantially same.

In some embodiments, the first RP cell region includes: one or more first active regions extending through each of the arm and the notch; and one or more second active regions extending through the stem; and a first total number of the one or more first active regions and a second total number of the one or more second active regions are different.

In some embodiments, the first RP cell region includes: one or more first active regions extending through each of the arm and the notch; and one or more second active regions extending through the stem; and a first total number of the one or more first active regions and a second total number of the one or more second active regions are same.

In some embodiments, a device includes: first and second rectangular parallelepiped (RP) cell regions correspondingly including three-dimensional (3D) first and second L-shape regions, first and second dummy regions and first and second resident regions; each of the first and second L-shape regions including active transistors having corresponding operabilities which comprise a function correspondingly of the first and second L-shape regions that represents a function correspondingly of the first and second RP cell regions; each of the first and second resident regions including one or more active transistors having corresponding operabilities which are free from comprising the function of the L-shape region correspondingly of the first and second RP cell regions; each of the first and second L-shape regions including a stem including first, second and third parts, and an arm extending from the first part of the corresponding stem to form a first notch; the first and second dummy regions representing the third parts correspondingly of the second and first RP cell regions; for each of the first and second RP cell regions, the dummy region and the resident region being in the first notch; and first type active transistors (first active transistors) of each arm being stacked correspondingly with respect to one or more second type active transistors (second active transistors) of the first part of the corresponding stem; one or more dummy transistors of each dummy region being stacked correspondingly with respect to one or more of the second active transistors of the second part of the corresponding stem; and first and second RP cell regions being complementarily oriented relative to each other such that one or more first active transistors of each resident region being stacked correspondingly with respect to one or more active transistors of the third part of the corresponding stem.

In some embodiments, the stem extends in a first direction; the arm extends from the first part of the corresponding stem in a second direction perpendicular to the first direction; relative to each of the first direction and a third direction perpendicular to each of the first and second directions, the second RP cell region is rotated 180 degrees relative to the first RP cell region.

In some embodiments, the stem extends in a first direction; the arm extends from the first part of the corresponding stem in a second direction perpendicular to the first direction; relative to each of the second direction, the second RP cell region is rotated 90 degrees relative to the first RP cell region.

In some embodiments, relative to each of the first direction, an intermediary RP cell region is rotated 180 degrees relative to the first RP cell region; and relative to plane formed by the first direction and a third direction perpendicular to each of the first and second directions, the second RP cell region is mirror-symmetric with respect to the intermediary RP cell region.

In some embodiments, the first RP cell region further includes a first RP internal region abutted to the corresponding L-shape region; or the second RP cell region further includes a second RP internal region abutted to the corresponding L-shape region.

In some embodiments, each of the first and second RP cell regions includes: a first active region extends through each of the arm and the notch; and a second active region extends through the stem; and for at least one of the first and second RP cell regions, and relative to a third direction perpendicular to each of the first and second directions, the first active region and the second active region have substantially a same width.

In some embodiments, each of the first and second RP cell regions includes: a first active region extends through each of the arm and the notch; and a second active region extends through the stem; and for at least one of the first and second RP cell regions, and relative to a third direction perpendicular to each of the first and second directions, the first active region and the second active region have substantially different widths.

In some embodiments, each of the first and second RP cell regions includes: a first active region extends through each of the arm and the notch; and a second active region extends through the stem; and for at least one of the first and second RP cell regions, and relative to a third direction perpendicular to each of the first and second directions, the first active region and the second active region have corresponding first and second jog-profiles.

In some embodiments, for at least one of the first and second RP cell regions, and the first jog-profile of the first active region and the second jog-profile of the second active region are substantially same.

In some embodiments, for at least one the first jog-profile of the first active region and the second jog-profile of the second active region are substantially different.

In some embodiments, each of the first and second RP cell regions includes: one or more first active regions extending through each of the arm and the notch; and one or more second active regions extending through the stem; and for at least one of the first RP cell region or the second RP cell region, a first total number of the one or more first active regions and a second total number of the one or more second active regions are same.

In some embodiments, each of the first and second RP cell regions includes: one or more first active regions extending through each of the arm and the notch; and one or more second active regions extending through the stem; and for at least one of the first RP cell region or the second RP cell region, a first total number of the one or more first active regions and a second total number of the one or more second active regions are different.

In some embodiments, a method (forming a semiconductor device) includes forming a first rectangular parallelepiped (RP) cell region including: forming lower groups of transistor components, each of the lower groups representing a corresponding first type of active transistor, the lower groups representing a stem of an L-shape region included in the RP cell region, and the stem including first, second and third parts that correspondingly include one or more of the lower groups; and forming upper groups of transistor components over corresponding ones of the lower groups, a first set of the upper groups being over the first part of the stem and representing an arm of the L-shape region, the arm extending from the first part of the stem to form a first notch, a second set of the upper groups being over the second part of the stem and representing a dummy region included in the RP cell region, a third set of the upper groups being over the third part of the stem and representing a resident region, the dummy region and the resident region being in the first notch; each upper group of the arm and the resident region representing a corresponding second type of active transistor, and each upper group of the dummy region representing a corresponding dummy transistor; the lower groups and upper groups of the L-shape region having corresponding operabilities which comprise a function of the L-shape region that represents a function of the RP cell region; and the upper groups of the resident region having corresponding operabilities which are free from comprising the function of the L-shape region.

In some embodiments, the forming lower groups of transistor components includes: forming lower parts of lower metal-to-gate (MG) contacts; forming lower parts of lower metal-to-source/drain (MD) contacts; forming a first active region, portions thereof being on corresponding portions of the lower parts of the lower MG contacts and the lower parts of the lower MD contacts; forming upper parts of the lower MG contacts on corresponding portions of the lower parts of the lower MG contacts and corresponding portions of the first active region; and forming upper parts of the lower MD contacts on corresponding portions of the lower parts of the lower MD contacts and corresponding portions of the first active region.

In some embodiments, for each of the arm and the resident region, the forming upper groups of transistor components includes: forming lower parts of upper MG contacts over corresponding ones of the upper parts of the lower MG contacts; forming lower parts of upper MD contacts over corresponding ones of the upper parts of the lower MD contacts; forming a second active region over the first active region, portions of the second active region being on corresponding portions of the lower parts of the upper MG contacts and the lower parts of the upper MD contacts; forming upper parts of the upper MG contacts on corresponding portions of the lower parts of the upper MG contacts and corresponding portions of the second active region; and forming upper parts of the upper MD contacts on corresponding portions of the lower parts of the upper MD contacts and corresponding portions of the second active region.

In some embodiments, before the forming upper groups of transistor components, the method further includes: forming insulators on corresponding portions of the upper parts of the lower MG contacts; and the forming lower parts of upper MG contacts forms the lower parts of the upper MG contacts on corresponding ones of the insulators.

In some embodiments, before the forming upper groups of transistor components, the method further includes: forming MG-to-MG (G2G) contacts on corresponding portions of the upper parts of the lower MG contacts; and the forming lower parts of upper MG contacts forms the lower parts of the upper MG contacts on corresponding ones of the G2G contacts.

In some embodiments, before the forming upper groups of transistor components, the method further includes: forming insulators on corresponding portions of the upper parts of the lower MD contacts; and the forming lower parts of upper MD contacts forms the lower parts of the upper MD contacts on corresponding ones of the insulators.

In some embodiments, before the forming upper groups of transistor components, the method further includes: forming MD-to-MD (D2D) contacts on corresponding portions of the upper parts of the lower MD contacts; and the forming lower parts of upper MD contacts forms the lower parts of the upper MD contacts on corresponding ones of the D2D contacts.

In some embodiments, for the dummy region, the forming upper groups of transistor components includes: forming lower parts of upper dummy MG (DG) contacts over corresponding ones of the upper parts of the lower MG contacts; forming lower parts of upper MD contacts over corresponding ones of the upper parts of the lower MD contacts; forming a second active region over the first active region, portions of the second active region being on corresponding portions of the lower parts of upper DG contacts and the lower parts of the upper MD contacts; forming upper parts of the upper DG contacts on corresponding portions of the lower parts of upper DG contacts and corresponding portions of the second active region; and forming upper parts of the upper MD contacts on corresponding portions of the lower parts of the upper MD contacts and corresponding portions of the second active region.

In some embodiments, before the forming upper groups of transistor components, the method further includes: forming insulators on corresponding portions of the upper parts of the lower MG contacts; and the forming lower parts of dummy MG contacts forms the lower parts of dummy MG contacts on corresponding ones of the insulators.