High density spin torque three dimensional (3D) memory arrays addressed with microwave current

One embodiment of the present invention includes a three dimensional memory array having a plurality of memory elements coupled to form the array through a single top lead and a single bottom lead, each memory element including a magnetic free layer in which non-volatile data can be stored, wherein each memory element possesses unique resonant frequencies associated with each digital memory state, thereby enabling frequency addressing during parallel write and read operations, each memory element further including a fixed layer and a spacer formed between the free layer and the fixed layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of high density multi-dimensional nonvolatile memory arrays and particularly to multi-dimensional memory arrays made of frequency-addressable spin transfer torque (STT) memory elements, each including at least one free layer, wherein each memory element has a different resonant frequency, due to the shape and material of the memory element, thereby creating large nonvolatile memory arrays.

2. Description of the Prior Art

High density nonvolatile memory devices, based on flash technology, have become increasingly popular for use in many and diverse applications, computing being one of them. However, such technology is approaching practical limits for higher areal densities due to lithographic constraints. The critical lithographic dimension F is currently around 45 nanometers (nm) for flash technology, and is projected to decrease by around 20% per annum in the near future, although reducing the size of F beyond factor of approximately two will be very difficult. The corresponding bit size is approaching 4F2for single-bit-per-cell flash memory, and 2F2for double-bit-per-cell flash memory. While multiple bits may in principle be stored in a single cell, which increases areal density, this has proved impractical beyond 2 bits/cell because signal-to-noise ratios are reduced due the presence of multiple, closely spaced, levels in one memory cell.

Alternative storage devices, comprising single-bit-per-cell multi-layer arrangements of storage elements, have been demonstrated, for example by Matrix Semiconductor, Inc. of Santa Clara, Calif. To date, such multi-layer storage devices have allowed only write-once or one-time-write operation, and have not allowed multiple write operations to memory. New materials for re-writable memory are a topic of current research and require new inventions to be integrated into multilayer devices with large storage capacities.

One class of solid state memory devices, or nonvolatile memory, is Magnetic Random Access Memory (MRAM). MRAM devices are based on magnetic materials. MRAM devices comprise cells or elements having a magnetically hard layer (the “pinned” or “fixed” layer) and a magnetically soft layer (the “free” layer). Writing to MRAM is performed by passing current through current leads that are formed on either side of each memory element in order to create a local induced magnetic field which sets the direction of the soft layer magnetization. Significant problems have been encountered however in scaling these devices to high densities. In particular, disturbances to neighboring cells or elements can occur during writing, sometimes causing a neighboring cell to be erroneously written.

Spin Transfer Torque (STT) devices are similar to MRAM devices except that the current paths pass through the magnetic layers of each memory element, rather than to the side of each memory element, and the soft layer of the memory element is set via the transfer of spin torque from the spin polarized current passing through that layer. However, this approach requires rather high current densities, which are undesirable due to heat and power consumption concerns. In addition, this approach is difficult to scale to high areal densities using a multilevel architecture approach, as this would require cells with multiple free layers and it would be generally difficult to switch each layer independently with only a spin polarized direct current.

In light of the foregoing, there is a need for a high density three-dimensional nonvolatile memory array, which incorporates multiple layers of memory elements, where each memory element can be switched independently.

SUMMARY OF THE INVENTION

Briefly, in one embodiment of the present invention, a two-dimensional (2-D) nonvolatile memory array is disclosed to include a plurality of nonvolatile memory elements coupled to form the array, through a single top lead and a single bottom lead, each memory element including a fixed layer and a free layer, separated by a spacer, wherein the direction of magnetization of the free layer relative to the fixed layer determines the state of the memory element, and wherein each memory element may be frequency addressed for reading and writing based on a unique resonant frequency.

In another embodiment of the present invention, a three-dimensional (3-D) nonvolatile memory array is disclosed to include a plurality of nonvolatile memory elements, arranged in stacks, each stack having a different shape anisotropy than the other stacks, the plurality of memory elements further arranged in layers with each layer having a free layer material with different magnetocrystalline anisotropy (MCA) than the other layers, such that each memory element is selectable based on a unique free layer resonant frequency.

The foregoing and other objects, features and advantages of the invention will become apparent after reading the following detailed description of the preferred embodiments, which is illustrated in the several figures of the drawing.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In the embodiments of the present invention, shown and/or discussed herein, a memory structure is achieved that is designed with a simple materials set and delivers improved bit packing densities and therefore higher capacities for a given form factor. In one embodiment, a three dimensional (3-D) memory arrangement (structure or array) is presented comprising multiple memory (or storage) elements removing the need for individual write and read lines to be attached to each memory element of the array, accordingly, offering economies in manufacturing and in device size. A “device” as used herein includes one or more memory elements.

A high density nonvolatile memory structure is disclosed having multiple layers of non-volatile memory elements, each layer having been created with a different intrinsic magnetocrystalline anisotropy, the layers of memory elements being patterned into stacks of memory elements, each of the stacks possessing a different aspect ratio and thus a different shape anisotropy allowing for large arrays of memory elements, each with a unique resonant frequency and thus no need for individual wires to each layer or memory element.

By way of background, each memory element, depending on its total anisotropy, for example, determined by MCA and shape anisotropy, among other factors, has a characteristic frequency at which it will oscillate, if disturbed with suitable spin polarized current, and this frequency is referred to as the resonant frequency. Each magnetization state of each memory element has a separate resonant frequency. If an alternating current at the resonant frequency is applied to the memory element, an advantageously lower direct current, perhaps zero, is required in conjunction to write the memory element or to change the direction of its magnetization. Thus, the required critical current is lower than that currently used by prior art nonvolatile memory. In an array of memory elements, if a resonant frequency is applied to the entire array, as in the embodiments of the present invention, only the memory element with a matching resonant frequency would be excited (or selected). The application of current to the entire array would only require two current leads thereby eliminating the need for unique pairs of wires to each memory cell, which as earlier noted is one of the limitations experienced by prior art nonvolatile memory.

Thus, in the embodiments of the present invention, high speed current-induced (“spin-torque”) switching of individual nanomagnetic elements is effectuated and electrical measurements of the associated microwave oscillations are made. The microwave oscillation frequency is a function of the memory element size, shape, anisotropy, damping and the like. Accordingly, the resonant or oscillation frequency (f0) is selected by appropriate materials engineering and lithographic processing. These frequencies are measured following the application of a DC current to the memory element, as will become apparent. Therefore, a combination of microwave field or current at the device resonant frequency and a small DC bias field or current is used. The memory element is read either by measuring resistance with a DC current or by measuring the resonant frequency, such as described in publications entitled “Microwave Oscillations Of A Nanomagnet Driven By A Spin-Polarized Current,” S. I. Kiselev et al., Nature 425 (2003) 380-383, and “Time-Domain Measurements Of Nanomagnet Dynamics Driven By Spin-Transfer Torques,” I. N. Krivorotov et al., Science 307 (2005) 228-231.

Thus, high bit packing density using layered memory elements, each of which possess different microwave oscillation frequencies because each has been designed with a different magnetic anisotropy, is achieved. Moreover, in one embodiment of the present invention, these layers of memory elements are patterned into stacks of memory elements each of which possesses a different aspect ratio and thus a different shape anisotropy allowing for large arrays of memory elements, each with unique resonant frequencies. In this manner, large arrays of memory elements, each with unique resonant frequencies, are fabricated. As an example, in the simplest case, the antiparallel, which may be a logical “0”, state and the parallel, which may be a logical “1”, state each have a different resonant frequency, thus there would be two resonant frequencies for each element.

Referring now toFIG. 1(a), a current-perpendicular-to-plane (CPP) device10is shown to include a top lead12and a bottom lead14used for establishing connection with the device10which further includes a pillar (or nonvolatile memory element)16, in accordance with an embodiment of the present invention. In one embodiment, the memory element16, which is a nonvolatile memory element, is made of a magnetic free layer18that is separated from a magnetic fixed layer20by a non-magnetic spacer22. In one embodiment, the memory element16is a spin transfer torque (STT) memory element. InFIG. 1(a), the free layer18and the fixed layer20have in-plane anisotropy, i.e. parallel to the plane, as shown by the direction of the bold-set arrows.

InFIG. 1(a), examples of material used as the free layer18are 22 Å of CO50Fe50or the bilayer structure 6 Å CO50Fe50/35 Å Ni80Fe20. An example of the materials used to form a fixed layer20which minimizes demagnetizing field effects is made of the following thickness and material composite: 25 Å CO50Fe50/8 Å Ru/25 Å CO50Fe50. An example of material used as the spacer22is of the thickness and material 40 Å Cu.

In another embodiment of the present invention, the free and fixed layers could have perpendicular anisotropy and in yet another embodiment, their anisotropy axes could be at some angle to each other, both of which embodiments are discussed and shown in subsequent figures and discussions below.

InFIG. 1(a), the direction of current, represented by the arrow26, is perpendicular to the film plane. The shape of the device10is generally lithographically defined. Examples of current lithography techniques are photolithography, deep ultra-violet, electron beam, and others. The leads12and14are used for applying current thereto to invoke the storage (programming of or writing to) or read-back of data (or bit of information) stored in the memory element16. In one embodiment, the easy anisotropy axis is perpendicular to the film plane as this leads to a smaller required critical write current. High bit packing density (and thus high device capacity) is achieved through layering memory elements, such as the memory element16, each of which possesses different resonant microwave oscillation frequencies because each layer has been designed with a different total magnetic anisotropy.

The pillar16is interchangeably referred to as a “spin transfer torque (STT) memory element”16capable of storing information in binary format.

FIG. 1(b) shows a graph30, of Resistance (R)34, in Ohms, shown in the vertical direction (y-axis) of the memory element16vs. the magnetic field32(H), in kilo Oersted (Oe) units, shown in the horizontal direction (x-axis), as applied to the memory element16. The graph30shows the relationship between the resistance of the pillar16ofFIG. 1(a) and the relative directions of magnetization of the free layer18and the fixed layer20. Stated differently, the direction of magnetization of the free layer18vs. the fixed layer20is parallel or anti-parallel depending on the history of the applied magnetic field. For example, at36, the direction of the magnetization of the free layer18is parallel to the direction of magnetization of the fixed layer20, whereas, at38, the direction of the magnetization of the free layer18is anti-parallel to the direction of magnetization of the fixed layer20. When increasing the field from large negative fields, the free layer reverses, whereas when decreasing the field from large positive fields, the free layer reverses.

Starting from36, the direction of magnetization of the free layer18is in a parallel direction relative to that of the fixed layer20and then, the direction of magnetization of the free layer16switches to anti-parallel relative to that of the fixed layer20and then upon decreasing the applied field, the direction of magnetization of the free layer18switches back to parallel relative to that of the fixed layer20. Thus, the graph30essentially shows field-induced reversal of the direction of magnetization of the free layer16resulting from the application of a magnetic field (H) and observed by measuring the change in resistance (R) of the device as the direction of magnetization of the free layer18switches from parallel to anti-parallel and visa versa relative to that of the fixed layer20. When the direction of magnetization of the free layer18is anti-parallel, resistance (R) increases relative to when the direction of the free layer18is parallel to that of the fixed layer20.

Stated differently, there are two stable magnetic states, those with the magnetization of the free layer20and the fixed layer18aligned parallel and anti-parallel. In one example, the parallel alignment represents a logical ‘1’ state and the anti-parallel alignment represents a logical ‘0’ state.

FIG. 1(c) shows a graph50, of Resistance (R)54, in Ohms, in the vertical direction (y-axis) vs. current52(IB), in milli Ampere units, in the horizontal direction (x-axis), as applied to the memory element16, of the memory element16. The graph50represents current-induced reversal of the direction of magnetization of the free layer18when current (IB) is applied to the memory element16and the change in magnetization is observed by measuring the change in resistance (R) of the device as the direction of magnetization of the free layer18switches from parallel to anti-parallel and visa versa relative to that of the fixed layer20. In this connection,60and62, inFIG. 1(c) show the resistances associated with the parallel and anti-parallel directions of magnetization of the free layer18relative to the fixed layer20, whereas,56and58, inFIG. 1(c) show the currents required to reverse the direction of magnetization of the free layer18relative to that of the fixed layer20.

An understanding of the memory element16is vital because the rest of this document discloses embodiments and methods of fabrication and use of memory arrays built from the memory element16by, for example, stacking and/or placing side-by-side, in a horizontal plane, a plurality of the memory element16to build a large memory array (or high density memory elements).

FIGS. 2(a)-(c) show alternative embodiments of the memory element16ofFIG. 1(a) with different directions of magnetization in the free layer18and the fixed layer20in each embodiment. InFIG. 2(a), the free layer18and the fixed layer20have perpendicular anisotropy and the direction of magnetization is perpendicular to the plane, which is a preferred direction due to lower current requirements for switching relative to an in-plane anisotropy, such as shown inFIG. 1(a).

Depending on the direction of the bold arrows, i.e. the free layer18has magnetization pointing up (parallel to the y-axis) or pointing down (parallel to the y-axis), a logical or binary ‘1’ or ‘0’ is stored or written to the memory element16. That is, the magnetization of the free layer18determines the state of stored bit. For example, in the case of an out-of-plane anisotropy device, if the direction of magnetization of the free layer18matches that of the fixed layer20, this may indicate a binary state ‘1’, whereas if the direction is opposite to that of the fixed layer20, this may indicate a binary state ‘0’ or vice versa.

InFIG. 2(c), while the direction of magnetization in the fixed layer20is parallel to the plane, the direction of magnetization in the free layer18is perpendicular to the plane. InFIG. 2(b), the direction of magnetization of the fixed layer is at a predetermined angle to normal.

FIG. 3(a) shows a two dimensional (2-D) planar nonvolatile memory array80with a plurality of memory elements16, shown in one horizontal plane and in accordance with an embodiment of the present invention. The memory elements16are each shown to include a spacer13. The 2-D array80ofFIG. 3(a) allows for multiple memory elements comprising free and fixed layer couples to be added to a row with all memory elements connected to the leads12and14. While there are five memory elements16shown inFIG. 3(a), any number of memory elements may be employed. InFIG. 3(a), the array80is a single-bit-per-cell configuration (a cell being the same as a memory element) where one cell can assume one of two states, i.e. ‘0’ and ‘1’. The leads12and14provide a simple lead structure allowing for parallel read and write operations of and to all of the memory devices16to which the leads are connected. Current travels in a direction indicated by the arrow82or the reverse. Each free layer18of a memory element16has two unique resonant frequencies (f0), associated with parallel and antiparallel fixed and free layers, designed by control of total magnetic anisotropy, i.e. using lithography to control shape anisotropy and/or by control of magnetocrystalline anisotropy using materials engineering. Accordingly, each memory element in the array can be written and read individually using frequency-space addressing.

As is apparent inFIG. 3(a) and additional embodiments of the present invention, herein, individual pairs of write and read lines to each element, used in conventional non-volatile memory are eliminated.

FIG. 3(b) shows a multi-bit-per-cell device (or nonvolatile memory array)90with two stacked free layers92and94of a plurality of memory elements96and98, in accordance with another embodiment of the present invention. The embodiment ofFIG. 3(b) shows the in-plane anisotropy case with a plurality of memory elements, having more than one free layer, namely two, as shown in the figure, in the same stack. It should be noted that while the device90is shown to comprise two memory elements, other numbers of memory elements are contemplated.

More specifically regarding the device90, there is shown a top lead109and a bottom lead110and therebetween are shown two memory elements96and98, separated by a spacer108. The memory element96is shown atop of the spacer108and further shown to include a free layer92, which is directly formed on top of the spacer108and onto which a spacer104is formed. On top of the spacer104is formed a fixed (or pinned) layer100. On top of the lead110is formed the memory element98, which includes a fixed layer102, a spacer106and a free layer94. The fixed layer102is shown formed on top of the lead110and on top thereof is shown formed the spacer106and on top of the latter is shown formed the free layer94. Because there are two free layers in the device90and each can take on a different direction of magnetization relative to the fixed layer of its corresponding memory element, four states or a two digit binary number can be stored in the device90. The arrows114and116are shown as being dashed to indicate the two possibilities of the direction of magnetization for each of the free layers92and94.

Stated differently, due to the stacking of the free layers, multiple bits, in particular two bits, are achieved. That is, two free layers will effectuate four binary states (00, 01, 10 and 11) because each free layer has two distinct easy magnetization directions, and these can be independently written and read in frequency space by virtue of each having a unique resonant frequency (f0), designed either by control of shape anisotropy, using lithography as an example, and/or by control of magnetocrystalline anisotropy, such as using materials engineering. To provide a practical example, if the direction of the free layer92matched that shown, inFIG. 3(b), of the fixed layer100, there would be a unique state represented, such as ‘0’ and if the direction does not match, an opposite state might be represented, such as ‘1’. Coupling the foregoing with the unique states represented in a similar manner with reference to the memory element98, there are altogether4states or two bits of information that may be stored within the device90due to the 2-memory element stacking thereof. The four states are noted on the right side ofFIG. 3(b), as states1-4with each state showing the direction of magnetization of each of the two corresponding free layers92and94. As earlier noted, there may be additional states or bits of information stored in the device90in the presence of additional stacked memory elements.

In an alternative embodiment, the layers ofFIG. 3(b) may be formed in different order. For example, the fixed layer102may be formed on top the spacer106, which may be formed on top of free layer94to form memory element98. In a further alternative embodiment, the device90may include only one pinned (or fixed layer), such as the pinned layer100with the free layers92and94present, as described. In this case, the magnetic states of the free layers92and94are determined with reference to the magnetic state of the pinned layer100. Moreover, additional free layers than those shown inFIG. 3(b) may be formed thus creating additional storage capacity. In this case, not every memory element will include a fixer layer.

FIG. 4(a) shows a 3-D nonvolatile memory array120made of nonvolatile memory elements122in accordance with yet another embodiment of the present invention. As will be appreciated, the 3-D structure is created by using varying magnetocrystalline anisotropy (MCA) in one dimension, and varying shape anisotropy in another dimension, with the net result of such varying anisotropies summing so that each memory element exhibits a different or unique total anisotropy and thus a different or unique resonant frequency (f0) for each memory state. In the embodiment ofFIG. 4(a), each plane of memory elements122has the same MCA, determined by the thin magnetic film structure for that layer. For example, inFIG. 4(a), 10 layers with varying MCA are shown in an upwardly direction by the arrow124(the lighter and darker shading of each of the memory elements of the different layers are shown to emphasize the varying MCA of the layers) and 10 stacks of memory elements122of differing shapes are shown horizontally by the arrow126(the different sizes of each of the memory elements of the different stacks are shown to further emphasize the shape anisotropy). Each stack of memory elements122has the same shape anisotropy designed by, for example, lithography. In theFIG. 4(a), there are 10×10 or 100 memory elements122depicted.

The array120includes 100 variations of shape and material of memory elements. That is, due to the presence of 10 layers and 10 stacks of memory elements, there are 100 memory elements, each distinguished by its shape and material and thus each having a unique resonant frequency for each magnetic state. To write a memory element from the array120, in the presence of an alternating signal of unique frequency for that memory element, a lower current density is required than that of prior art for reversing the direction of magnetization.

The size of the array120depends on the number of shapes that can be manufactured, which is, at least in part, dependent on lithographic dimension limitations. Thus, as lithographic dimensions reduce, the number of memory elements in an array can increase because the elements can be formed closer together. Further, a large array of memory elements is fabricated with reasonable manufacturing costs and practical operations.

An exploded view of one of the memory elements122appears on the right-hand side ofFIG. 4(a) wherein the memory element122is shown to include a fixed layer142on top of which is formed a spacer140on top of which is formed a free layer138with its magnetization direction parallel or anti-parallel to that of the fixed layer142. The direction of current144is shown to be down.

To provide a practical example, while all of the memory elements of the stack128have the same shape anisotropy, all of the memory elements of the stack128have different shape anisotropy than the memory elements of the remaining nine stacks, including the stacks130and132. Similarly, while all of the memory elements122of the layer134have the same MCA, the memory elements of the layer134have a different MCA than the memory elements of the remaining nine layers, including the layer136. This results in each of the memory elements122ofFIG. 4(a) having a unique resonant frequency for each magnetic state.

Thus, during a write operation, as will be shortly discussed, an alternating current (AC) corresponding to the resonant frequency of a desired state of a desired memory element, i.e. one to be written thereto, is applied. The alternating write current may be applied to the memory element or array of memory elements in conjunction with a direct current which may serve to lower the total energy required to switch the element to be written. That is, a direct current (DC) waveform may be applied to the memory element or array of memory elements either immediately before, during or immediately after the application of the alternating current which is frequency matched to the element which is to be written.

During a read operation, a DC current is applied which is large enough to excite all of the memory elements but not large enough to switch (magnetically reverse) any of them. Then, in response to the applied DC current, the memory elements each generate a radiofrequency (RF) waveform, which includes frequency information indicating whether the memory element is in a parallel or anti-parallel state.

An alternatively topography as previously discussed may be a different order of formation of layers, such as the free layer138on top of which is formed the spacer140on top of which is formed the fixed layer142. InFIG. 4(a), yet another embodiment includes fewer fixed layers than there are free layers which would simplify processing without compromising functionality. The state of each memory element would be determined with respect to a nearby fixed layer.

In another embodiment, a single fixed layer in a stack of multiple free layers is described.FIG. 4(b) shows the array120ofFIG. 4(a) further developed to have a fixed layer150formed on top of the stacks of memory elements, on top of which is formed a top current lead152and below which is formed a bottom current lead154is formed. Each of the memory elements122is separated from the other by a conducting spacer156. The current is applied to the lead152and follows a path shown by the arrow and lines of158. As previously noted, the order of formation of layers may be different and as an example, a free layer150may be below the stacks of memory elements.

In one embodiment, the fixed layer150(also known as a hard layer or a polarizing layer) is made of permanently magnetized magnetic material, well known to those of ordinary skill in the art, such as the antiparallel composite material 25 Å CO50Fe50/8 Å Ru/25 Å CO50Fe50. It is permanently magnetized such that it always polarizes the electrons coming through the device in one direction.

While it may be possible to operate the array120with a single fixed layer150, as shown inFIG. 4(b), it may be necessary to have more than one fixed layer within each stack of memory elements, or to have one fixed layer for every memory element. The stacks are separated from each other by an electrically insulating material, such as Al2O3, and the memory elements in each stack are separated from each other by a conductive spacer layer, for example made of Cu or Ru.

Care must be taken in choosing materials for the manufacturing of the memory elements of the memory array, and in lithographic patterning of those same elements, to ensure that the resonant frequencies of each of the memory elements are far enough apart so as to eliminate undesirable excitation or selection of incorrect memory elements.

FIG. 5(a) shows the result of a spin transfer torque being exerted on the magnetization (M) of the free layer of a memory element, such as the memory element16of the foregoing figures. InFIG. 5(a), at174, a spin polarized current of magnitude suitable for a read operation of the free layer172of a memory element is applied at170, which causes a torque to be exerted on the magnetization M of the free layer172causing it to precess around the easy axis of magnetization, i.e. the lowest energy state. That is, a signal is produced, as a result of the magnetization (M), represented by the arrow180and the dashed arrows therearound, processing a resonant frequency (f0) related to the total anisotropy of the free layer172.

As shown in the graph176, if the signal power of the free layer172is measured at the resonant frequency (f0)178, a peak182is detected. The direction of magnetization of the free layer172is shown by the arrow180and the magnetization M processes about the axis of the arrow180. The areal current density related to the current used for spin precession must be low enough so as avoid reversing the free layer magnetization and also avoid melting the free layer174through Ohmic heating. In an exemplary embodiment, the upper limit of this current density is 109A/cm2.

FIG. 5(b) shows a memory element176, similar to that ofFIG. 5(a), except that the direction of magnetization is178is opposite to that ofFIG. 5(a), as measured relative to the direction of the magnetization of a nearby fixed layer. For this reason, the peak180of the signal power is at a different resonant frequency (f′0).

FIGS. 6(a) and6(b) show block diagrams of the steps performed in writing to and reading from, respectively, a nonvolatile memory element, such as the memory element16of the foregoing figures, in accordance with methods of the present invention. With reference toFIG. 6(a), a location signal190representing the location to which a value is to be written in memory is provided to a look-up-table (LUT) block192. The output of block192is a frequency corresponding to or matching the resonant frequency of the memory element to which data will be written. Thus, the block192is a table of stored information correlating locations to frequencies and vice versa. The output of the block192is provided to the AC wavetrain block194, which essentially provides an AC signal having the desired resonant frequency or the frequency provided by the block192.

The alternating current (AC) signal (or current), from the block194, is added to a DC signal from the DC current block198, by the Bias T unit196, which provides an input to the array of memory cells200and the AC excites the memory element which is intended to be written thereto. It is the AC signal that determines which memory element is selected or addressed for writing thereto because it carries the frequency resonant to the memory element to be written thereto. When the AC is provided to an entire stack of memory elements through the top or bottom leads, the need for many wires is eliminated by virtue of frequency addressing, described herein, which simplifies device architecture over that of prior art.

The direct current (DC) (or DC signal) of the block198may be used to program the desired memory element. The foregoing DC signal may be applied through the top lead and bottom lead of an array of memory elements. This applies as well to the application of DC during a read operation. Alternatively, a combination of DC and AC is used with the AC being one or more AC pulses added into a DC pulse to form a wave train. Still alternatively, AC pulses with no DC may be employed for read and write operations.

An array made of memory elements of the present invention may be written to in parallel or serially. When writing to an array of memory elements, in parallel, a current wave train is applied to the memory elements comprising a DC component and a selection of AC components, the frequencies of which are matched to the microwave oscillation frequencies of the specific memory states of the specific memory elements which are to be written.

Addressing or selecting a memory element based on the resonant frequency associated therewith and that is unique to each memory element is referred to as frequency addressing.

When writing serially, a DC component and an AC component are applied which match the microwave oscillation frequency of a single memory element which is being written thereto.

InFIG. 6(b), when reading, a DC current is applied to the entire array of memory elements (to the array of memory cells208), at the step204. An amplification or pre-amplification is performed at step209on the signal from the array of memory cells208and prior to the frequency discrimination circuit210, which operates thereon. The applied DC excites all of the memory elements so that the frequency discrimination circuit at step210can then determine which free layers are in which magnetization state and this information is represented by various voltage levels, on the signal212, corresponding to various resonant frequencies, which is provided to the LUT block214and the output of the LUT block214generates memory state information.

Location information includes the address of the memory location where information is desired to be read therefrom. Vnis high/low depending on the whether the corresponding fnis present in the wave train. The LUT of the block214correlates Vnto a anti-parallel/parallel configuration of a specific memory element or cell. The blocks192and214are essentially the same blocks wherein during a write operation, the LUT is provided with location information and provides corresponding frequency information and during a read operation, the LUT is provided with frequency information and provides corresponding location information. The level of the DC is generally lower, during the read operation, relative to the DC of the write operation.

FIG. 7(a) shows the timing diagram of some of the signals generated and used during the write operation ofFIG. 6(a). For example, the DC signal220is the output of the block198ofFIG. 6(a), the AC wave train signal222is the output of the194ofFIG. 6(a) and the Bias T output signal224is the output of the Bias T196ofFIG. 6(a).FIG. 7(b) shows the timing diagram of some of the signals generated and used during the read operation ofFIG. 6(b). For example, the DC signal226is the output of the block204ofFIG. 6(b), the output wave train signal228is the output of the block208ofFIG. 6(b) and the voltage signal230is the output of the circuit210ofFIG. 6(b), which corresponds to resonant frequencies, as earlier noted.

FIG. 8shows the initial states and resulting or final states of the free layers and fixed layers of five memory elements, such as the memory element16, ofFIG. 1(a) of the foregoing figures. The initial states of all of the five memory states, prior to programming or writing thereto are in logical state ‘1’ with magnetization states of directions thereof of the free layers and fixed layers all pointing in the same direction (they are parallel). During the write operation, when the signal224(ofFIG. 7(a)), having the waveform shown inFIG. 8and including frequencies f2and f4corresponding to memory elements2and4, is applied, the states of memory elements2and4are changed to logical state ‘0’ where the free layer magnetization is reversed to a direction opposite to that of the fixed layer of the same memory element (they are anti-parallel). This is due to the waveform224having frequencies matching the resonant frequencies of the memory elements being written thereto.

Prior to writing data to the device, the LUT would need to be initialized with the resonant frequencies of all the memory elements. This could be done, for example, by placing the device in a large magnetic field so as to set the direction of all the layers to be parallel to the field. The field could then be set to zero. A DC would be applied so as to measure the resonant frequencies of all devices in the parallel state. The field would then be slowly increased in the reverse direction while monitoring the ac waveform output. As the field increases, the first free layer will reverse, and one of the frequencies in the wave form will vanish and a new frequency will appear. This then identifies the two frequencies of device at location1, and those are stored in the LUT. The field is the increased further, and each free layer will then reverse in succession, identifying the frequencies of each free layer, and thus populating the entire LUT.

FIG. 9shows the steps discussed relative to a read operation and toFIG. 7(b) pictorially with the free and fixed layers of memory elements1-5shown during a read operation, in accordance with an embodiment of the present invention. InFIG. 9, the signal226(ofFIG. 7(b)) is applied to all of the memory elements1-5thereby exciting all of them. An AC waveform or signal, such as the signal228, is generated from the memory elements, corresponding to the directions of magnetization thereof. That is, the waveform (or wave train) of the signal228includes the frequencies fnwhich are the resonant frequencies of the memory element states. This information is used to generate the voltages, Vn, used by the LUT block214, ofFIG. 6(b), to correlate with an AP/P configuration of a specific cell or memory element. Thus, inFIG. 9, the state ‘1’ of the memory element1is read as being in the P, or parallel, configuration, whereas, the state ‘0’ of memory element2is read as being in the AP, or anti-parallel, configuration of the memory element2and so on.

FIG. 10shows a top view of the exemplary states of a free layer of a memory elements of the present invention, relative to the state of the fixed layer, and can be used in any of the foregoing embodiments. In this embodiment, there are specifically four possible low energy magnetization states for the free layer that are each logical states, representing a 2-digit binary value, arising from magnetization of the free layer having equiaxial magnetocrystalline anisotropy (i.e., having two energetically equivalent easy axes of magnetization, or four-fold magnetic symmetry). The magnetization of the fixed layer, shown at232, by M, needs to be at a finite or predetermined angle relative to the easy axes of the free layer to break the inherent symmetry. Accordingly, each of the four states of magnetization of the free layer, shown at234, has a unique resonant frequency, f0.