Semiconductor devices including a gate structure in a substrate

Semiconductor devices are provided. A semiconductor device includes a substrate, and a source/drain region in the substrate. Moreover, the semiconductor device includes a gate structure in a recess in the substrate. The gate structure includes a liner that includes a first portion and a second portion on the first portion. The second portion is closer, than the first portion, to the source/drain region. The second portion includes a metal alloy. Methods of forming a semiconductor device are also provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2016-0075097, filed on Jun. 16, 2016, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated herein in its entirety by reference.

BACKGROUND

The present disclosure relates to semiconductor devices. An increase in the integration density of semiconductor devices and the downscaling of the semiconductor devices have led to decreasing sizes of gate electrodes of transistors. With reduced gate electrode size, an interconnection resistance of a semiconductor device including the gate electrode may increase, and a distance between the gate electrode and a drain region may be reduced. Thus, a leakage current of a transistor may increase.

SUMMARY

Various embodiments of present inventive concepts may provide a semiconductor device capable of reducing a leakage current of a transistor, and a method of forming/manufacturing the device.

Moreover, various embodiments of present inventive concepts may provide a semiconductor device capable of reducing a resistance of a gate electrode, and a method of forming/manufacturing the device.

A semiconductor device, according to some embodiments of present inventive concepts, may include a semiconductor substrate. The semiconductor device may include a source/drain region in the semiconductor substrate. Moreover, the semiconductor device may include a gate structure in a recess in the semiconductor substrate. The gate structure may include a liner that includes a first portion and a second portion on the first portion. The second portion may be closer, than the first portion, to the source/drain region, and may include a metal alloy.

A semiconductor device, according to some embodiments, may include a substrate. The semiconductor device may include first and second source/drain regions in the substrate. Moreover, the semiconductor device may include a buried gate structure in the substrate. The buried gate structure may include a first work function control portion. The buried gate structure may include a second work function control portion on the first work function control portion. The second work function control portion may be closer, than the first work function control portion, to the first and second source/drain regions. The second work function control portion may include a metal alloy including a greater, relative to the first work function control portion, concentration of implanted and/or diffused metal atoms.

A semiconductor device, according to some embodiments, may include a substrate. The semiconductor device may include a source/drain region in the substrate. The semiconductor device may include a bit line on the source/drain region. Moreover, the semiconductor device may include a buried gate structure in the substrate. The buried gate structure may include a liner including first and second portions. The second portion of the liner may be closer, than the first portion, to the source/drain region. The second portion of the liner may include a first concentration of implanted and/or diffused metal atoms that is greater than a second concentration of the metal atoms in the first portion. Moreover, the buried gate structure may include a gate electrode that is adjacent a sidewall of the second portion of the liner and that includes a lower resistivity than polysilicon.

A method of forming a semiconductor device, according to some embodiments, may include forming a recess in a semiconductor substrate. The method may include forming a first metal layer in the recess. The method may include forming a second metal layer between opposing sidewalls of a lower portion of the first metal layer in the recess. Moreover, the method may include forming a metal alloy in an upper portion of the first metal layer in the recess. More of the metal alloy may be in the upper portion of the first metal layer than in the lower portion of the first metal layer.

A method of forming a semiconductor device, according to some embodiments, may include forming a recess in a semiconductor substrate. The method may include forming a first metal layer in the recess. The method may include forming a second metal layer between opposing sidewalls of a lower portion of the first metal layer in the recess. The method may include forming a metal alloy in an upper portion of the first metal layer in the recess. More of the metal alloy may be in the upper portion of the first metal layer than in the lower portion of the first metal layer. Moreover, the method may include forming a source/drain region in the semiconductor substrate, and forming a bit line structure on the source/drain region.

A method of forming a semiconductor device, according to some embodiments, may include forming a recess in a semiconductor substrate. The method may include forming a first metal layer in the recess. The method may include forming a second metal layer between opposing sidewalls of a lower portion of the first metal layer in the recess. The lower portion of the first metal layer may include a first work function control portion. The method may include forming a second work function control portion by forming a metal alloy in an upper portion of the first metal layer in the recess. More of the metal alloy may be in the second work function control portion than in the first work function control portion. Moreover, the method may include forming a source/drain region in the semiconductor substrate, and forming a bit line structure on the source/drain region.

DETAILED DESCRIPTION

FIG. 1is a schematic plan layout of a semiconductor device100according to some embodiments.

Referring toFIGS. 1 to 3, a substrate102may include an active region106defined by an isolation layer104.

The substrate102may include silicon (Si), for example, crystalline silicon, polycrystalline silicon (poly-Si), or amorphous silicon. In some embodiments, the substrate102may include a semiconductor material, such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the substrate102may include a conductive region, for example, a doped well or a doped structure.

The isolation layer104may have a shallow trench isolation (STI) structure. For example, the isolation layer104may include an insulating material, which fills a device isolation trench (refer to104T inFIG. 18A) formed in the substrate102. The insulating material may include fluoride silicate glass (FSG), undoped silicate glass (USG), boro-phospho-silicate glass (BPSG), phospho-silicate glass (PSG), flowable oxide (FOX), plasma enhanced tetra-ethyl-ortho-silicate (PE-TEOS), or tonen silazene (TOSZ), but present inventive concepts are not limited thereto.

The active region106may have a relatively elongated island shape having a minor axis and a major axis. As shown inFIG. 1, the major axis of the active region106may be arranged in a direction D1parallel to a top surface of the substrate102. In some embodiments, the active region106may have a first conductivity type. The first conductivity type may be a P type or an N type.

The substrate102may further include a trench108, which may extend in a first direction (e.g., X direction inFIG. 1) parallel to the top surface of the substrate102. The trench108may intersect the active region106and be formed to a predetermined depth from the top surface of the substrate102. A portion of the trench108may extend into the isolation layer104, and a portion of the trench108formed in the isolation layer104may have a bottom surface located at a lower level than a portion of the trench108formed in the active region106. The term “recess,” as used herein, may refer to the trench108.

A first source/drain region109A and a second source/drain region109B may be located in an upper portion of the active region106on both sides of the trench108. The first source/drain region109A and the second source/drain region109B may be impurity regions doped with impurities of a second conductivity type that is different from the first conductivity type. The second conductivity type may be an N type or a P type. The first source/drain region109A and/or the second source/drain region109B may, in some embodiments, be a non-elevated source/drain region (e.g., may not be elevated beyond an opening of the trench108). A height/position of the first source/drain region109A and/or the second source/drain region109B, however, may be adjusted/modified. For example, in some embodiments, a lowermost surface of the first source/drain region109A and/or the second source/drain region109B may be higher than an uppermost surface of the gate structure130. Alternatively, the lowermost surface of the first source/drain region109A and/or the second source/drain region109B may be lower than the uppermost surface of the gate structure130.

A gate insulating layer120may be formed on an inner wall of the trench108. The gate insulating layer120may be conformally formed on the inner wall of the trench108to a predetermined thickness. The gate insulating layer120may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material having a higher dielectric constant than that of silicon oxide. The high-k dielectric material may include, for example, a metal oxide or a metal oxynitride, such as hafnium oxide, hafnium oxynitride, or hafnium silicon oxide. However, a material included in the gate insulating layer120is not limited thereto. For example, when the gate insulating layer120includes silicon oxide, the gate insulating layer120may include silicon oxide that is formed on an exposed surface of the substrate102by using a thermal oxidation process. Alternatively, in some embodiments, the gate insulating layer120may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material, which is deposited by using a low-pressure chemical vapor deposition (LPCVD) process, a plasma-enhanced CVD (PECVD) process, an ultra-high vacuum CVD (UHV-CVD) process, or an atomic layer deposition (ALD) process.

A gate structure130and a gate capping layer136may be sequentially disposed on the gate insulating layer120within the trench108. The gate structure130may fill a portion of the trench108to a predetermined height from a bottom portion of the trench108, while the gate capping layer136on the gate structure130may fill the remaining portion of the trench108. The gate structure130may be a buried gate structure in the substrate102.

As shown inFIG. 2, the bottom surface of the portion of the trench108formed in the isolation layer104may be at a lower level than the portion of the trench108formed in the active region106. Thus, a bottom surface130B1of the gate structure130formed in the isolation layer104may be located at a lower level than a bottom surface130B2of the gate structure130formed in the active region106. For example, the gate structure130may have a non-planar, saddle-type structure, but present inventive concepts are not limited thereto.

The gate structure130may include a lower gate electrode132filling the bottom portion of the trench108and an upper gate electrode134on the lower gate electrode132. The gate capping layer136may be formed on the gate structure130and fill the remaining portion of the trench108. Here, terms “lower” and “upper” gate electrodes132and134may be interpreted as a portion of the gate structure130that is spaced a relatively large vertical distance apart from an uppermost surface of the substrate102, and a portion of the gate structure130that is spaced a relatively small vertical distance apart from the uppermost surface of the substrate102, respectively. For example, as shown inFIG. 2, a vertical distance d1between a top surface of the lower gate electrode132and the uppermost surface of the substrate102may be greater than a vertical distance d2between the top surface of the upper gate electrode134and the uppermost surface of the substrate102.

The lower gate electrode132may have a predetermined height from a lowermost surface of the trench108and fill the bottom portion of the trench108. The lower gate electrode132may include a lower work-function control layer142conformally formed on the gate insulating layer120in the bottom portion of the trench108, and a lower filling metal layer144formed on the lower work-function control layer142to fill the bottom portion of the trench108.

In some embodiments, the lower work-function control layer142may include a metal, a metal nitride, or a metal carbide, such as titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), titanium silicon carbonitride (TiSiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum aluminum carbonitride (TaAlCN), or tantalum silicon carbonitride (TaSiCN). The lower work-function control layer142may be a single layer including one of the above-described materials or a stacked structure of at least two materials thereof, but present inventive concepts are not limited thereto. In some embodiments, the lower work-function control layer142may have a thickness of about 10 Angstroms (Å) to about 50 Å. The lower work-function control layer142may be formed by using an ALD process, a metal organic ALD (MOALD) process, or a metal organic chemical vapor deposition (MOCVD) process.

In some embodiments, the lower filling metal layer144may include at least one of tungsten (W), tungsten nitride (WN), TiN, and TaN. However, a material included in the lower filling metal layer144is not limited thereto. The lower filling metal layer144may include a material having good gap-filling characteristics and a relatively low resistivity. A height of the lower filling metal layer144may range from about 50% to about 90% of the total height of the gate structure130. For example, since the height of the lower filling metal layer144ranges from about 50% to about 90% of the total height of the gate structure130, a resistance of the gate structure130may be reduced.

The upper gate electrode134may fill a portion of the trench108at a higher level than the lower gate electrode132. The upper gate electrode134may include an upper work-function control layer146conformally formed on an inner wall of the trench108and an upper filling metal layer148formed on the lower filling metal layer144. A depth, in the trench108, of an uppermost surface of the upper work-function control layer146may be 610 Angstroms or fewer. The lower work-function control layer142and the upper work-function control layer146may be respective portions of a metal liner in the trench108. The upper work-function control layer146may be the smaller one of the portions of the metal liner. For example, the upper work-function control layer146may have a smaller volume and/or cross-sectional area in the trench108than the lower work-function control layer142.

The upper work-function control layer146may include a metal, a metal nitride, or a metal carbide, which may include/contain a work-function controlling metal material. For example, the upper work-function control layer146may include a metal, a metal nitride, or a metal carbide, such as Ti, TiN, TiAlN, TiAlC, TiAlCN, TiSiCN, Ta, TaN, TaAlN, TaAlCN, and TaSiCN. The upper work-function control layer146may be a single layer including one of the above-described materials or a stacked structure of at least two materials thereof, but present inventive concepts are not limited thereto.

In some embodiments, the upper work-function control layer146may have a thickness of about 10 Å to about 50 Å. The upper work-function control layer146may have a first height H1in a direction (Z direction) perpendicular to the top surface of the substrate102, and the first height H1may range from about 2 Å to about 50 Å. However, the first height H1of the upper work-function control layer146is not limited thereto. For example, the first height H1, which may be referred to herein as a “vertical thickness,” in the trench108, of the upper work-function control layer146, may range from 2 Angstroms to 300 Angstroms. In some embodiments, the vertical thickness/first height H1may be between 200 Angstroms and 300 Angstroms.

The work-function controlling metal material may include, for example, at least one of lanthanum (La), strontium (Sr), antimony (Sb), yttrium (Y), aluminum (Al), tantalum (Ta), hafnium (Hf), or iridium (Ir). However, a kind (e.g., a type/element) of the work-function controlling metal material is not limited thereto. The work-function controlling metal material may include a metal material that may uniformly diffuse into the upper work-function control layer146. Also, the work-function controlling metal material may include a metal material capable of reducing an effective work function of the above-described metal, metal nitride, or metal carbide included in the upper work-function control layer146.

In some embodiments, when the active region106is an NMOS active region, the work-function controlling metal material may be/include at least one of lanthanum (La), strontium (Sr), antimony (Sb), or yttrium (Y). Alternatively, when the active region106is a PMOS active region, the work-function controlling metal material may include at least one of aluminum (Al), tantalum (Ta), hafnium (Hf), or iridium (Ir).

In some embodiments, the upper work-function control layer146may include the work-function controlling metal material at a first content. The term “content,” as used herein, may refer to a concentration. The first content (e.g., concentration) may range from about 0.01 atomic percent (at %) to about 10 at %, but is not limited thereto. For example, when the upper work-function control layer146includes a TiN material layer including lanthanum (La), lanthanum atoms may be substantially and uniformly distributed in the TiN material layer. Alternatively, lanthanum atoms may be distributed with a gradient in its concentration profile in the TiN material layer. For example, in the upper work-function control layer146, the first content may vary according to a vertical direction (Z direction) and/or a horizontal direction (Y direction). Also, a work function of the TiN material layer including lanthanum may vary depending on the content (e.g., concentration) of lanthanum included/contained in the TiN material layer. For example, the TiN material layer may have a work function of about 4.5 eV. As the content (e.g., concentration) of lanthanum included/contained in the TiN material layer increases, a work function of the TiN material layer including lanthanum may be reduced. For example, when the content (i.e., the first content/concentration) of lanthanum ranges from about 0.01 at % to about 10 at %, the work function of the portion of the TiN material layer including lanthanum may be about 0.01 eV to about 1 eV less than the work function of the portion of the TiN material layer that is substantially free of lanthanum (e.g., that includes a concentration of less than 0.01 percent lanthanum). As an example, the TiN material layer having the work function of about 4.5 eV may have the work function reduced to about 4.1 eV by using lanthanum oxide in the TiN material layer.

The work-function controlling metal material in the upper work-function control layer146may provide a metal alloy. For example, a combination in the upper work-function control layer146of TiN with La atoms may be referred to as a metal alloy. The words “metal alloy,” as used herein, refer to a combination/mixture of metals and do not require a melting of the metals. The metal alloy is formed by implantation and/or diffusion of metal atoms. More of the metal alloy is in the upper work-function control layer146than in the lower work-function control layer142. For example, a majority of implanted and/or diffused metal atoms (e.g., La atoms) are in the upper work-function control layer146, rather than in the lower work-function control layer142. As an example, a concentration of La atoms in the lower work-function control layer142may be less than 0.01 percent, whereas a concentration of La atoms in the upper work-function control layer146may be greater than or equal to 0.01 percent. In some embodiments, the metal alloy in the upper work-function control layer146may include titanium nitride and lanthanum oxide.

Since the work-function controlling metal material is included in the upper work-function control layer146at the first content (e.g., concentration), a work function of the upper work-function control layer146may be less than a work function of the lower work-function control layer142. For example, the work function of the upper work-function control layer146may be about 0.01 eV to about 1 eV less than the work function of the lower work-function control layer142, but is not limited thereto.

In general, as a size of the gate structure130decreases, a distance between the gate structure130and the first and second source/drain regions109A and109B may also decrease. Thus, a gate-induced drain leakage (GIDL) current may be generated due to a high electric field applied between the gate structure130and the first and second source/drain regions109A and109B. However, since the upper gate electrode134located near the first and second source/drain regions109A and109B includes a material having a relatively small work function, application of a high electric field between the gate structure130and the first and second source/drain regions109A and109B may be reduced/prevented. As a result, the GIDL may be reduced. A work function of the gate structure130and a GIDL will be described in detail later with reference toFIGS. 4A and 4B.

In some embodiments, the upper work-function control layer146may be formed integrally with the lower work-function control layer142. For example, in a process of forming the lower and upper work-function control layers142and146according to some embodiments, after the preliminary work-function control layer (refer to140inFIG. 18B) is formed on the inner wall of the trench108, a work-function controlling metal material may be diffused into an upper portion of the preliminary work-function control layer140only to a predetermined height. Thus, the upper work-function control layer146containing the work-function controlling metal material at the first content (e.g., concentration) may be formed in the upper portion of the preliminary work-function control layer140, while the remaining portion of the preliminary work-function control layer140may remain as the lower work-function control layer142.

Meanwhile, a portion of the gate insulating layer120may be between the upper work-function control layer146and the inner wall of the trench108.

The upper filling metal layer148may be formed on the upper work-function control layer146at a higher level than the lower filling metal layer144. An interface of the upper filling metal layer148and the lower filling metal layer144may include oxide. In some embodiments, methods described herein may include removing the oxide from the interface of the upper filling metal layer148and the lower filling metal layer144.

A top surface of the upper filling metal layer148may be at substantially the same level as (e.g., coplanar with) a top surface of the upper work-function control layer146. A material included in the upper filling metal layer148may have similar properties to those of a material included in the lower filling metal layer144. The upper filling metal layer148may not include the work-function controlling metal material.

In some embodiments, the term “gate electrode,” as used herein, may refer to the lower filling metal layer144and/or the upper filling metal layer148. Moreover, references herein to a liner on sidewalls of a gate electrode may refer to the metal liner that includes the lower and upper work-function control layers142,146being on sidewalls of the lower filling metal layer144and/or the upper filling metal layer148.

A portion of the upper gate electrode134may be located at the same level as the first and second source/drain regions109A and109B. For example, an upper portion of the upper gate electrode134may be located at the same level as portions of (e.g., some of) bottom portions of the first and second source/drain regions109A and109B, but present inventive concepts are not limited thereto.FIG. 2illustrates an example in which the first source/drain region109A has a bottom surface located at the same level as a bottom surface of the second source/drain region109B, but present inventive concepts are not limited thereto. For example, unlike the structure illustrated inFIG. 2, the first and second source/drain regions109A and109B may have different heights such that the bottom surface of any one of the first and second source/drain regions109A and109B is at a lower level than the bottom surface of the other thereof. For example, a portion of the upper gate electrode134may be located at the same level as a portion of the first source/drain region109A, while the upper gate electrode134may not be located at the same level as the second source/drain region109B.

The gate capping layer136on the gate structure130may fill the remaining portion of the trench108. For example, the gate capping layer136may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

A bit line structure150may be formed on the first source/drain region109A. The bit line structure150may extend in a second direction (Y direction inFIG. 1) that is parallel to a top surface of the substrate102and perpendicular to the first direction (X direction inFIG. 1). The bit line structure150may include a bit line contact152, a bit line intermediate layer154, a bit line156, and a bit line capping layer158, which are sequentially stacked on the substrate102. For example, the bit line contact152may include polysilicon, and the bit line intermediate layer154may include a metal silicide (e.g., tungsten silicide) or a metal nitride (e.g., tungsten nitride). The bit line156may include a metal material. The bit line capping layer158may include an insulating material, such as silicon nitride or silicon oxynitride.

Optionally, bit line spacers may be further formed on sidewalls of the bit line structure150. The bit line spacers may have a single structure or multi-layered structure including an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride. Also, the bit line spacers may further include air spaces (e.g., gaps).

A contact structure160may be formed on the second source/drain region109B. The contact structure160may include a lower contact pattern162, a metal silicide layer164, and an upper contact pattern166, which are sequentially stacked on the substrate102, and a barrier layer168surrounding a side surface and a bottom surface of the upper contact pattern166. In some embodiments, the lower contact pattern162may include polysilicon, and the upper contact pattern166may include a metal material. The barrier layer168may include a metal nitride having a particular conductivity type. However, a structure of the contact structure160shown inFIG. 2is only an example, and present inventive concepts are not limited thereto. In some embodiments, a conductive pad may be further formed on the upper contact pattern166and the barrier layer168.

First and second insulating interlayers170and172may be formed on the substrate102and surround a side surface of the bit line structure150and a side surface of the contact structure160. The bit line contact152and the bit line intermediate layer154may penetrate through the first insulating interlayer170, and the bit line156may be disposed on the first insulating interlayer170. The second insulating interlayer172may be formed on the first insulating interlayer172to cover side surfaces of the bit line156and the bit line capping layer158. The contact structure160may be connected to the second source/drain region109B through the first and second insulating interlayers170and172. A support layer174including an opening174H exposing a top surface of the contact structure160may be formed on the second insulating interlayer172.

An information storage unit180(which may be referred to as a “storage structure” or a “storage region”) may be formed on the second insulating interlayer172and may be electrically connected to the contact structure160. For example, the information storage unit180may be a cell capacitor of a dynamic random access memory (DRAM) device, a phase-change memory unit of a phase-change RAM (PRAM) device, a variable resistance memory unit of a resistive RAM (ReRAM) device, or a magnetic tunnel junction structure of a magnetic RAM (MRAM) device. For example, when the information storage unit180is a cell capacitor of a DRAM device, the information storage unit180may include a lower electrode182electrically connected to the contact structure160, a capacitor dielectric layer184located on the lower electrode182, and an upper electrode186located on the capacitor dielectric layer184. Meanwhile, the support layer174may surround a portion of a side surface of the lower electrode182.

Hereinafter, effective work functions of portions of the gate structure130will be described with reference toFIGS. 4A and 4B.

FIG. 4Ais a schematic energy band diagram of the lower work-function control layer142of the lower gate electrode132and the active region106adjacent to the lower work-function control layer142.FIG. 4Bis a schematic energy band diagram of the upper work-function control layer146of the upper gate electrode134and the first and second source/drain regions109A and109B adjacent to the upper work-function control layer146.

Referring toFIG. 4A, the lower work-function control layer142may have a Fermi energy level EF,LGthat is similar to a level of mid-gap energy Emid-gapof the active region106. In other words, the lower work-function control layer142may include a mid-gap conductive material. Here, the mid-gap conductive material may refer to a conductive material having an energy level similar to a mid-gap energy Emid-gapof/between a conduction band Ec or a valence band Ev in an energy band diagram of the active region106. Also, the mid-gap energy Emid-gapmay refer to a middle value of/between the conduction band Ec or the valance band Ev in the energy band diagram of the active region106. For example, the lower work-function control layer142may include a metal, a metal nitride, or a metal carbide, such as Ti, TiN, TiAlN, TiAlC, TiAlCN, TiSiCN, Ta, TaN, TaAlN, TaAlCN, TaSiCN, which may be the mid-gap conductive material.

Referring toFIG. 4B, a Fermi energy level EF,UGof the upper work-function control layer146may be closer to the conduction band Ec of the active region106than the Fermi energy level EF,LGof the lower work-function control layer142, due to the fact that the upper work-function control layer146includes a mid-gap conductive material including/containing a work-function controlling metal material at a predetermined concentration/content. For example, when the work-function controlling metal material includes at least one of lanthanum (La), strontium (Sr), antimony (Sb), or yttrium (Y), the work-function controlling metal material may be diffused and distributed in the upper work-function control layer146. Also, due to the work-function controlling metal material, the upper work-function control layer146may have a Fermi energy level EF,UGcloser to the conduction band Ec of the active region106, compared to the case of the Fermi energy level EF,LGof the lower work-function control layer142.

FIG. 4Billustrates a Fermi energy level EF,Nof the first and second source/drain regions109A and109B when the active region106is an NMOS active region. The first and second source/drain regions109A and109B doped with N-type impurities may have a Fermi energy level EF,Nthat is close to the conduction band Ec of the active region106.

As can be seen fromFIGS. 4A and 4B, the Fermi energy level EF,UGof the upper work-function control layer146may be closer to the Fermi energy level EF,Nof the first and second source/drain regions109A and109B of the active region106, compared to the case of the Fermi energy level EF,LGof the lower work-function control layer142.

For instance, when the active region106is an NMOS active region, the work-function controlling metal material may be a metal material having a Fermi energy level higher than a mid-gap energy Emid-gap. In other words, the work-function controlling metal material may be a metal material having a smaller work function than a mid-gap conductive material. That is, since the work-function controlling metal material is included in the upper work-function control layer146, an effective work function ΦUGof the upper work-function control layer146may be less than an effective work function ΦLGof the lower work-function control layer142.

Since the effective work function ΦUGof the upper work-function control layer146is less than the effective work function ΦLGof the lower work-function control layer142(for example, since a level difference (i.e., ΔE=EF,N−EF,UG) between the Fermi energy level EF,UGof the upper work-function control layer146and the Fermi energy level EF,Nof the first and second source/drain regions109A and109B is smaller than a level difference (i.e., ΔE=EF,N−EF,LG) between the Fermi energy level EF,LGof the lower work-function control layer142and the Fermi energy level EF,Nof the first and second source/drain regions109A and109B), an electric field that may be applied between the first and second source/drain regions109A and109B and the upper work-function control layer146may be lower than an electric field that may be applied between the first and second source/drain regions109A and109B and the lower work-function control layer142. Accordingly, a GIDL induced to the first and second source/drain regions109A and109B due to the upper work-function control layer146may be lower than a GIDL induced to the first and second source/drain regions109A and109B due to the lower work-function control layer142. If, on the other hand, the lower work-function control layer142and the upper work-function control layer146included equal concentrations of a work-function controlling material (e.g., lanthanum oxide), then a GIDL problem could persist in the first and second source/drain regions109A and109B.

If the gate structure130includes a metal material including a mid-gap conductive material over the entire height thereof, a relatively high electric field may be applied between the gate structure130and the first and second source/drain regions109A and109B in a similar manner to the case described with reference toFIG. 4A, so that a considerable amount of GIDL may be generated. However, if the upper work-function control layer146having a relatively small effective work function is formed in an upper portion of the gate structure130, an electric field applied between the gate structure130and the first and second source/drain regions109A and109B may be reduced, so that a GIDL may be markedly reduced. If, on the other hand, the GIDL were not reduced, then a DRAM refresh time could be undesirably delayed. Accordingly, various embodiments of present inventive concepts may both (i) reduce GIDL and (ii) increase a DRAM refresh speed, by providing a metal alloy (e.g., lanthanum and titanium nitride) in an upper portion of a liner.

Referring back toFIGS. 1 to 3, in the semiconductor device100, the gate structure130may have the stack structure of the lower gate electrode132and the upper gate electrode134, and a work-function controlling metal material may be included/contained at a predetermined concentration/content in the upper work-function control layer146of the upper gate electrode134. Thus, an effective work function of the upper gate electrode134may be less than an effective work function of the lower gate electrode132. Also, since the upper gate electrode134formed adjacent to the first and second source/drain regions109A and109B has a relatively small effective work function (or has a smaller effective work function than the lower gate electrode132), a GIDL caused by a high electric field may be reduced.

Furthermore, in a comparative case in which an upper gate electrode includes, for example, an n+-doped poly-Si material so as to reduce a GIDL, since a poly-Si material has a relatively high resistivity and poor gap-filling characteristics, a gate structure including the poly-Si material may have a relatively high resistance. However, in the above-described semiconductor device100, the upper gate electrode134may include the upper work-function control layer146and the upper filling metal layer148, and the upper filling metal layer148may have a lower resistivity and better gap-filling characteristics than poly-Si. Accordingly, the gate structure130may have a low resistance.

In conclusion, the above-described semiconductor device100may include the gate structure130having a low resistance and also, have a reduced GIDL. Accordingly, the semiconductor device100may have good electrical performance.

FIG. 5is a cross-sectional view of a semiconductor device100A according to some embodiments.FIG. 5is an enlarged cross-sectional view corresponding to a line C-C′ ofFIG. 1. InFIG. 5, the same reference numerals are used to denote the same elements as inFIGS. 1 to 4.

Referring toFIG. 5, a top level LV1of an upper work-function control layer146A may be lower than a top level LV2of an upper filling metal layer148. A portion of a gate capping layer136A may extend to a top surface of the upper work-function control layer146A between a gate insulating layer120and the upper filling metal layer148. For example, the gate capping layer136A may include an insulating material having good gap-fill characteristics, and a protrusion136P of the gate capping layer136A may be in contact with the upper work-function control layer146A between the gate insulating layer120and the upper filling metal layer148.

Since the top level LV1of the upper work-function control layer146A is lower than the top level LV2of the upper filling metal layer148, a sufficient distance may be ensured between an edge portion of the upper gate electrode134and the bit line contact (refer to152inFIG. 2), and occurrence of an electrical short may be impeded/prevented during the formation of the bit line structure (refer to150inFIG. 2).

In a process of forming the upper gate electrode134according to some embodiments, after the upper work-function control layer146A and the upper filling metal layer148are formed to fill the inside of the trench108, upper portions of the upper work-function control layer146A and the upper filling metal layer148may be removed by using an etchback process. During the etchback process, portions of the upper work-function control layer146A and the upper filling metal layer148may be removed at different etch rates. In this case, a top level LV1of the upper work-function control layer146A may be lower than a top level LV2of the upper filling metal layer148. However, present inventive concepts are not limited thereto. In some embodiments, after portions of the upper work-function control layer146A and the upper filling metal layer148are removed at similar etch rates during the etchback process such that the top level LV1of the upper work-function control layer146A is the same as the top level LV2of the upper filling metal layer148, an additional etching process for removing an upper portion of the upper work-function control layer146A to a predetermined height may be further performed.

FIG. 6is a cross-sectional view of a semiconductor device100B according to some embodiments.FIG. 6is an enlarged cross-sectional view corresponding to the line C-C′ ofFIG. 1. InFIG. 6, the same reference numerals are used to denote the same elements as inFIGS. 1 to 5.

Referring toFIG. 6, a top level LV1of an upper work-function control layer146B may be lower than a top level LV2of an upper filling metal layer148, and a void136V may be formed between a gate insulating layer120and the upper filling metal layer148.

Although a protrusion136P of a gate capping layer136B may be located between the gate insulating layer120and the upper filling metal layer148, the protrusion136P of the gate capping layer136B may not be in contact with a top surface of the upper work-function control layer146B. However, present inventive concepts are not limited thereto. A portion of the top surface of the upper work-function control layer146B located between the gate insulating layer120and the upper filling metal layer148may, in some embodiments, be in contact with the protrusion136P of the gate capping layer136B, and another portion of the top surface of the upper work-function control layer146B may be exposed by the void136V.

For instance, the gate capping layer136B may include an insulating material having relatively poor gap-fill characteristics. Thus, a space between the gate insulating layer120and the upper filling metal layer148may not be completely filled with the gate capping layer136B, so that the void136V may be formed.

FIG. 7is a cross-sectional view of a semiconductor device100C according to some embodiments.FIG. 7is an enlarged cross-sectional view corresponding to the line C-C′ ofFIG. 1. InFIG. 7, the same reference numerals are used to denote the same elements as inFIGS. 1 to 6.

Referring toFIG. 7, a bottom surface of an upper work-function control layer146C may be inclined at a predetermined inclination angle with respect to a top surface of a substrate102. That is, a level of the bottom surface of the upper work-function control layer146C may decrease away from an inner wall of a trench108in a second direction (Y direction) that is parallel to the top surface of the substrate102and perpendicular to a first direction (X direction).

The upper work-function control layer146C may include a first side surface146C_1and a second side surface146C_2. The first side surface146C_1may be in contact with an upper filling metal layer148and a portion of a lower filling metal layer144, and the second side surface146C_2may be in contact with a gate insulating layer120. The first side surface146C_1may have a first height H1C in a third direction (Z direction) perpendicular to the top surface of the substrate102, while the second side surface146C_2may have a second height H2C in the third direction. The first height H1C may be greater than the second height H2C. Also, a lowermost level LV1C of the upper work-function control layer146C may be lower than a bottom level LV2C of the upper filling metal layer148.

FIG. 7illustrates an example in which the bottom surface of the upper work-function control layer146C has a downwardly protruding profile, but present inventive concepts are not limited thereto. For example, the bottom surface of the upper work-function control layer146C may have a sectional shape including a plurality of stepped portions toward the second side surface146C_2and away from the first side surface146C_1(i.e., in a direction toward the gate insulating layer120).

In a process of forming an upper gate electrode134according to some embodiments, after a preliminary work-function control layer (refer to140inFIG. 19) is conformally formed on the inner wall of the trench108, a lower filling metal layer144may be formed to fill a bottom portion of the trench108. Thereafter, ions of a work-function controlling metal material may be implanted into a portion of the preliminary work-function control layer, which is exposed in the trench108at a higher level than the lower filling metal layer144. For example, when the work-function controlling metal material is implanted and/or diffused into the portion of the preliminary work-function control layer by using an oblique ion implantation process, the work-function controlling metal material may be implanted and/or diffused even to a portion of the preliminary work-function control layer, which is located at a lower level than the top surface of the lower filling metal layer144. Thus, an upper work-function control layer146C having an inclined bottom surface may be formed as shown inFIG. 7. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

In a process of forming the upper gate electrode134according to some embodiments, after a preliminary work-function control layer (refer to140inFIG. 18B) is conformally formed on the inner wall of the trench108, a lower filling metal layer144may be formed to fill the bottom portion of the trench108. A metal-containing liner (refer to149inFIG. 18D) may be formed on a portion of the preliminary work-function control layer, which is exposed within the trench108at a higher level than the lower filling metal layer144. The metal-containing liner may include a work-function controlling metal material. The work-function controlling metal material may be diffused from the metal-containing liner into the preliminary work-function control layer, thereby forming the upper work-function control layer146C. The work-function controlling metal material included in the metal-containing liner may be diffused by a predetermined distance in a horizontal direction and/or a vertical direction. The work-function controlling metal material may diffuse to a level (e.g., the lowermost level LV1C of the upper work-function control layer146C) that is lower than the top surface of the lower filling metal layer144. Thus, the upper work-function control layer146C including the inclined bottom surface may be formed as shown inFIG. 7.

FIG. 8is a cross-sectional view of a semiconductor device100D according to some embodiments.FIG. 8is an enlarged cross-sectional view corresponding to the line C-C′ ofFIG. 1. InFIG. 8, the same reference numerals are used to denote the same elements as inFIGS. 1 to 7.

Referring toFIG. 8, an upper work-function control layer146D may have a first width W1D in a second direction (Y direction), and the first width W1D may be less than a second width W2D of a lower work-function control layer142in the second direction (Y direction). An upper filling metal layer148in contact with the upper work-function control layer146D may include a protrusion148P, which may protrude from an interface between the upper work-function control layer146D and the lower work-function control layer142in a horizontal direction (second direction). As shown inFIG. 8, a bottom surface of the protrusion148P of the upper filling metal layer148may be at substantially the same level as a bottom surface of the upper work-function control layer146D, and the bottom surface of the protrusion148P may be in contact with an edge of a top surface of the lower work-function control layer142.

In a process of forming the upper gate electrode134according to some embodiments, after a preliminary work-function control layer (refer to140inFIG. 18B) is conformally formed on an inner wall of a trench108, a lower filling metal layer144may be formed to fill a bottom portion of the trench108, and a metal-containing liner (refer to149inFIG. 18D) may be formed on a portion of the preliminary work-function control layer, which is exposed within the trench108at a higher level than the lower filling metal layer144. The metal-containing liner may include a work-function controlling metal material. The work-function controlling metal material may be diffused from the metal-containing liner into the preliminary work-function control layer, thereby forming an upper work-function control layer146D. Thereafter, the metal-containing liner may be removed. During the process of removing the metal-containing liner, a portion of a sidewall of the upper work-function control layer146D may be removed together. Thus, as shown inFIG. 8, the first width W1D of the upper work-function control layer146D may be less than the second width W2D of the lower work-function control layer142.

FIG. 9is a cross-sectional view of a semiconductor device100E according to some embodiments.FIG. 9is an enlarged cross-sectional view corresponding to the line C-C′ ofFIG. 1. InFIG. 9, the same reference numerals are used to denote the same elements as inFIGS. 1 to 8.

Referring toFIG. 9, an upper portion of an upper work-function control layer146E may have a first width W1E in a second direction (or Y direction), and a lower portion of the upper work-function control layer146E may have a second width W2E larger than the first width W1E in the second direction (or Y direction). A lower work-function control layer142may have a third width W3E greater than the first width W1E in the second direction (or Y direction). A bottom level LV1E of the upper work-function control layer146E may be lower than a bottom level LV2E of an upper filling metal layer148, and the upper work-function control layer146E may include a protrusion146P, which may protrude in a lateral direction toward a lower filling metal layer144at a lower level than the bottom level LV2E of the upper filling metal layer148. As shown inFIG. 9, the protrusion146P of the upper work-function control layer146E may be in contact with the protrusion148P of the upper filling metal layer148.

In a process of forming the upper gate electrode134according to some embodiments, after a preliminary work-function control layer (refer to140inFIG. 18B) is conformally formed on an inner wall of a trench108, the lower filling metal layer144may be formed to fill a bottom portion of the trench108. A metal-containing liner (refer to149inFIG. 18D) may be formed on a portion of the preliminary work-function control layer, which is exposed within the trench108at a higher level than the lower filling metal layer144. The metal-containing liner may include a work-function controlling metal material. The work-function controlling metal material may be diffused from the metal-containing liner into the preliminary work-function control layer so that the upper work-function control layer146E having the bottom level LV1E that is lower than a top surface of the lower filling metal layer144may be formed. Thereafter, the metal-containing liner may be removed. During the process of removing the metal-containing liner, a portion of a sidewall of the upper work-function control layer146E may be removed together. Thus, as shown inFIG. 9, the upper work-function control layer146E may include the protrusion146P.

FIG. 10is a cross-sectional view of a semiconductor device100F according to some embodiments.FIG. 10is an enlarged cross-sectional view corresponding to the line C-C′ ofFIG. 1. InFIG. 10, the same reference numerals are used to denote the same elements as inFIGS. 1 to 9.

Referring toFIG. 10, a metal-containing liner149may be disposed between an upper work-function control layer146and an upper filling metal layer148and between the upper filling metal layer148and a lower filling metal layer144.

The metal-containing liner149may include a work-function controlling metal material. The metal-containing liner149may include a metal material including lanthanum (La), strontium (Sr), antimony (Sb), yttrium (Y), aluminum (Al), tantalum (Ta), hafnium (Hf), or iridium (Ir). The metal-containing liner149may be formed by using an ALD process, a MOALD process, or an MOCVD process.

The metal-containing liner149may include a first portion149_S formed on the upper work-function control layer146and a second portion149_L formed on the lower filling metal layer144. The first portion149_S of the metal-containing liner149may be formed directly on the upper work-function control layer146and in contact with the upper work-function control layer146. Also, the upper filling metal layer148may not be in contact with a lower filling metal layer144.

In a process of forming an upper gate electrode134according to some embodiments, after a preliminary work-function control layer (refer to140inFIG. 18B) is conformally formed on an inner wall of a trench108, the lower filling metal layer144may be formed to fill a bottom portion of the trench108. Thereafter, a metal-containing liner149may be formed on a portion of the preliminary work-function control layer, which is exposed within the trench108, at a higher level than the lower filling metal layer144. A work-function controlling metal material may diffuse from the metal-containing liner149into the preliminary work-function control layer140. Thus, a bottom surface of the upper work-function control layer146may be formed at substantially the same level as a bottom surface of the metal-containing liner149. Thereafter, the upper filling metal layer148may be formed on the metal-containing liner149and fill the remaining portion of the trench108.

In some embodiments, the upper work-function control layer146may have a first thickness W1F of about 10 Å to about 50 Å, and the metal-containing liner149may have a second thickness W2F of about 2 Å to about 10 Å. For example, the metal-containing liner149may have the second thickness W2F, which is equal to about 5% to 20% of the first thickness W1F of the upper work-function control layer146. If the second thickness W2F of the metal-containing liner149is excessively small, an excessively small content (e.g., concentration/percentage/amount) of the work-function controlling metal material may diffuse into the upper work-function control layer146, and a GIDL may not be greatly reduced. In contrast, when the second thickness W2F of the metal-containing liner149is excessively large, a volume of the upper filling metal layer148may be reduced to increase a resistance of the gate structure130. However, the second thickness W2F of the metal-containing liner149is not limited thereto but may be appropriately selected according to a thickness of the upper work-function control layer146, annealing conditions, which can be optionally performed, and a kind/type/element and resistivity of the work-function controlling metal material.

As shown inFIG. 10, a side surface and a bottom surface of the upper filling metal layer148may be surrounded by the metal-containing liner149, while the metal-containing liner149may not be formed on a side surface of the lower filling metal layer144. Thus, a width W3F of a bottom surface of the upper filling metal layer148may be less than a width W4F of the lower filling metal layer144.

FIG. 11is a cross-sectional view of a semiconductor device100G according to some embodiments.FIG. 11is an enlarged cross-sectional view corresponding the line C-C′ ofFIG. 1. InFIG. 11, the same reference numerals are used to denote the same elements as inFIGS. 1 to 10.

Referring toFIG. 11, a metal-containing liner149G may be located between an upper work-function control layer146and an upper filling metal layer148. The metal-containing liner149G may not be formed between the upper filling metal layer148and the lower filling metal layer144, and the upper filling metal layer148may be in direct contact with the lower filling metal layer144. Top surfaces of the upper work-function control layer146, the metal-containing liner149G, and the upper filling metal layer148may be at substantially the same level (i.e., may be coplanar).

For example, the metal-containing liner149G may have a thickness W2G corresponding to about 5% to about 20% of a thickness W1G of the upper work-function control layer146. The thickness W2G of the metal-containing liner149G may be substantially constant in/along a vertical direction (Z direction). Meanwhile, repeated detailed descriptions of the metal-containing liner149G may be omitted in view of the descriptions of the metal-containing liner149provided with reference toFIG. 10.

FIG. 12is a cross-sectional view of a semiconductor device100H according to some embodiments.FIG. 12is an enlarged cross-sectional view corresponding to the line C-C′ ofFIG. 1. InFIG. 12, the same reference numerals are used to denote the same elements as inFIGS. 1 to 11.

Referring toFIG. 12, a metal-containing liner149H may have a spacer-type sectional shape, and an upper thickness W1H of the metal-containing liner149H may be less than a lower thickness W2H of the metal-containing liner149H.

In a process of forming an upper gate electrode134according to some embodiments, after the metal-containing liner (refer to149inFIG. 10) is formed as described with reference toFIG. 10, an anisotropic etching process may be performed on the metal-containing liner149so that a portion of the metal-containing liner149located on a lower filling metal layer144may be removed, and the metal-containing liner149H may remain on a sidewall of an upper work-function control layer146.

FIG. 13is a cross-sectional view of a semiconductor device100I according to some embodiments.FIG. 13is an enlarged cross-sectional view corresponding to the line C-C′ ofFIG. 1. InFIG. 13, the same reference numerals are used to denote the same elements as inFIGS. 1 to 12.

Referring toFIG. 13, a metal-containing liner149I may be located between an upper work-function control layer146I and an upper filling metal layer148I, and a central portion of an upper gate electrode134may protrude upward. That is, a top level LV1I of an upper work-function control layer146I may be lower than a top level LV2I of an upper filling metal layer148I. A top level LV3I of a metal-containing liner149I may be higher than the top level LV1I of the upper work-function control layer146I and lower than the top level LV2I of the upper filling metal layer148I. Top surfaces of the upper filling metal layer148I, the metal-containing liner149I, and the upper work-function control layer146I may be continuously connected without sharp level differences.

In a process of forming the upper gate electrode134according to some embodiments, after the metal-containing liner149(refer to149inFIG. 10) is formed as described with reference toFIG. 10, an anisotropic etching process may be performed on the metal-containing liner149so that a metal-containing liner149I may remain on a sidewall of the upper work-function control layer146I. Thereafter, an upper filling conductive layer may be formed to fill the remaining portion of the trench108. An upper portion of the upper filling conductive layer may be removed by an etchback process to form an upper filling metal layer148I. During the etchback process, upper portions of the upper work-function control layer146I and the metal-containing liner149I may also be removed. When the etchback process adopts an etching condition where etch rates of the upper work-function control layer146I and the metal-containing liner149I are higher than an etch rate of the upper filling metal layer148I, the top levels LV1I and LV3I of the upper work-function control layer146I and the metal-containing liner149I may be lower than the top level LV2I of the upper filling metal layer148I.

In the semiconductor device100I, since the top level LV1I of the upper work-function control layer146I located relatively near the inner wall of the trench108is lower than the top level LV2I of the upper filling metal layer148I, a sufficient distance between an edge portion of the upper gate electrode134and bit line contact (refer to152inFIG. 2) may be ensured, and occurrence of an electrical short may be reduced/prevented during the formation of the bit line structure (refer to150inFIG. 2). Furthermore, the upper filling metal layer148I having a relatively large volume may be formed in a limited space of the trench108so that the gate structure130may have a low resistance.

FIG. 14is a cross-sectional view of a semiconductor device100J according to some embodiments.FIG. 14is an enlarged cross-sectional view corresponding to the line C-C′ ofFIG. 1. InFIG. 14, the same reference numerals are used to denote the same elements as inFIGS. 1 to 13.

Referring toFIG. 14, a top level LV1J of an upper work-function control layer146J may be lower than a top level LV2J of an upper filling metal layer148, and a top surface of a metal-containing liner149J may be at substantially the same level as a top level LV1J of the upper work-function control layer146J. Also, there may be a sharp difference between a top level of the metal-containing liner149J and the top level LV2J of the upper filling metal layer148, and side surfaces of the upper filling metal layer148may be exposed at a level higher than the top surface of the metal-containing liner149J. A gate capping layer136J may be in contact with the side surfaces of the upper filling metal layer148. However, present inventive concepts are not limited thereto. As shown inFIG. 6, the void (refer to136V inFIG. 6) may be formed in a space between the upper filling metal layer148and the gate insulating layer120at a higher level than the top surface of the metal-containing liner149J.

In a process of forming an upper gate electrode134according to some embodiments, after the metal-containing liner149J is formed and an upper filling conductive layer is formed to fill the remaining portion of the trench108, an upper portion of the upper filling conductive layer may be removed by an etchback process, thereby forming the upper filling metal layer148. During the etchback process, the upper work-function control layer146J and the metal-containing liner149J may be etched at a relatively high etch rate. As a result, the top level LV1J of the upper work-function control layer146J may be lower than the top level LV2J of the upper filling metal layer148.

In a process of forming the upper gate electrode134according to some embodiments, after the upper gate electrode134having a top surface formed at the same level is formed as described with reference toFIG. 11, a wet etching process for removing only the upper work-function control layer146J and the metal-containing liner149J to a predetermined height may be further performed. During the wet etching process, the upper filling metal layer148may be insignificantly/hardly removed, while only the upper work-function control layer146J and the metal-containing liner149J may be removed, thereby forming the upper gate electrode134having a discontinuous top level as shown inFIG. 14.

In the semiconductor device100J, the top level LV1J of the upper work-function control layer146J located near the inner wall of the trench108may be lower than the top level LV2J of the upper filling metal layer148. Thus, a sufficient distance between an edge portion of the upper gate electrode134and the bit line contact (refer to152inFIG. 2) may be ensured, and occurrence of an electrical short may be impeded/prevented during the formation of the bit line structure (refer to150inFIG. 2). Furthermore, the upper filling metal layer148having a relatively large volume may be formed in a limited space of the trench108so that the gate structure130may have a low resistance.

FIG. 15is a cross-sectional view of a semiconductor device100K according to some embodiments.FIG. 15is an enlarged cross-sectional view corresponding to the line C-C′ ofFIG. 1. InFIG. 15, the same reference numerals are used to denote the same elements as inFIGS. 1 to 14.

Referring toFIG. 15, an upper filling metal layer148K of an upper gate electrode134may be formed integrally with a lower filling metal layer144K of a lower gate electrode132.

A metal-containing liner149K may be formed on an inner wall of a trench108, a side surface of the metal-containing liner149K may be in contact with a gate insulating layer120, and a bottom surface of the metal-containing liner149K may be in contact with a top surface of an upper work-function control layer146K.FIG. 15illustrates an example in which a width W2K of the metal-containing liner149K in a second direction (Y direction) is less than a width W1K of an upper work-function control layer146K in the second direction (Y direction). Alternatively, in some embodiments, the width W2K of the metal-containing liner149K may be greater than the width W1K of the upper work-function control layer146K, and the bottom surface of the metal-containing liner149K may be in contact with a portion of a top surface of the upper filling metal layer148K.

The metal-containing liner149K may include a work-function controlling metal material. The metal-containing liner149K may include a metal oxide including lanthanum (La), strontium (Sr), antimony (Sb), yttrium (Y), aluminum (Al), tantalum (Ta), hafnium (Hf), or iridium (Ir). When the metal-containing liner149K includes a metal oxide, the metal-containing liner149K may include an insulating material. Here, a term “metal-containing liner”149K may be interpreted as including a work-function controlling metal material, and it is not intended to exclude examples in which the metal-containing liner149K includes both an insulating material and a metal. However, a material included in the metal-containing liner149K is not limited to the above-described examples. The metal-containing liner149K may include not only a metal oxide but also the above-described metals, a metal oxynitride, or a metal nitride.

In a process of forming a gate structure130according to some embodiments, a preliminary work-function control layer (refer to140P1inFIG. 20A) may be conformally formed on the inner wall of the trench108, and a filling metal layer (refer to140P2inFIG. 20A) may be formed to fill the inside of the trench108. A metal-containing liner (refer to149K inFIG. 20A) may be formed on the filling metal layer and the preliminary work-function control layer. Thus, a work-function controlling metal material included/contained in the metal-containing liner149K may be diffused into the preliminary work-function control layer, thereby forming the upper work-function control layer146K. In this case, the upper work-function control layer146K may have a first height H1K from a top surface of the lower filling metal layer144K. Thereafter, an anisotropic etching process may be performed on the metal-containing liner149K so that the metal-containing liner149K may remain on the inner wall of the trench108.

FIG. 16is a cross-sectional view of a semiconductor device100L according to some embodiments.FIG. 16is an enlarged cross-sectional view corresponding to the line C-C′ ofFIG. 1. InFIG. 16, the same reference numerals are used to denote the same elements as inFIGS. 1 to 15.

Referring toFIG. 16, an upper work-function control layer146L may have a spacer-type sectional shape. An upper portion of the upper work-function control layer146L may have a first width W1L in a second direction (or Y direction), and a lower portion of the upper work-function control layer146L may have a second width W2L larger than the first width W1L in the second direction (or Y direction).

In a process of forming the upper gate electrode134according to some embodiments, after a preliminary work-function control layer (refer to140inFIG. 18B) is conformally formed on an inner wall of a trench108, a first filling metal layer may be formed to fill the trench108. An upper portion of the first filling metal layer may be removed by an etchback process to form a lower filling metal layer144inside the trench108. During the etchback process, a sidewall of a portion of the preliminary work-function control layer, which is positioned at a higher level than the lower filling metal layer144, may also be removed so that the preliminary work-function control layer may have a spacer-type sectional shape. Thereafter, a metal-containing liner (refer to149inFIG. 18D) may be formed on the lower filling metal layer144and a portion of the preliminary work-function control layer, and a work-function controlling metal material may be diffused from the metal-containing liner into the portion of the preliminary work-function control layer to form the upper work-function control layer146L. The metal-containing liner may be removed.

FIG. 17is a flowchart of a method of manufacturing a semiconductor device100according to some embodiments.

FIGS. 18A to 18Hare cross-sectional views of process operations of the method of manufacturing the semiconductor device100, according to some embodiments.

Referring toFIGS. 17 and 18A, in operation10, a device isolation trench104T may be formed in the substrate102, and an isolation layer104may be formed in the device isolation trench104T. The active region106may be defined by the isolation layer104in the substrate102. The active region106may have a relatively elongated island shape having a minor axis and a major axis as shown inFIG. 1. Repeated detailed descriptions of the substrate102may be omitted in view of the descriptions of the substrate102provided with reference toFIGS. 1 to 3. The isolation layer104may be a single layer including one kind/type of insulating layer or a multi-layered structure including at least two kinds/types of insulating layers.

Subsequently, a trench108may be formed on a substrate102including the active region106. The trench108may extend in a first direction (X direction) parallel to a top surface of the substrate102and intersect the active region106. In a process of forming the trench108according to some embodiments, a first mask310including a first opening310H may be formed on the substrate102, and the trench108may be formed by using the first mask310as an etch mask. Trenches108may extend parallel to one another and have line shapes intersecting the active region106. In some embodiments, the substrate102and the isolation layer104may be etched together under an etching condition where an etch depth of the isolation layer104is different from an etch depth of the substrate102, so that a stepped portion may be formed in a bottom surface of the trench108. In some embodiments, to form a stepped portion in the bottom surface of the trench108, the isolation layer104and the substrate102may be etched by using respectively different etching processes so that an etch depth of the isolation layer104may be different from an etch depth of the substrate102.

In some embodiments, before performing processes for forming the trench108in the substrate102, impurity ions may be implanted into the substrate102so that first and second source/drain regions109A and109B may be formed in an upper portion of the active region106. Alternatively, in some embodiments, after the gate structure (refer to130inFIG. 18F) is formed to fill the trench108, the first and second source/drain regions109A and109B may be formed on both sides of the gate structure130.

Referring toFIGS. 17 and 18B, in operation20, a preliminary work-function control layer140may be conformally formed in a bottom portion of the trench108and an inner wall of the trench108.

To begin with, as shown inFIG. 18B, a gate insulating layer120may be formed on the bottom portion and the inner wall of the trench108. In some embodiments, the gate insulating layer120may be formed by using a thermal oxidation process, an ALD process, or a CVD process. For example, the gate insulating layer120may include silicon oxide formed at an exposed surface of the substrate102by the thermal oxidation process. In this case, as shown inFIG. 18B, the gate insulating layer120may be formed on an inner wall of a portion of the trench108located in the active region106, while the gate insulating layer120is not formed on an inner wall of a portion of the trench108located in the isolation layer104. Alternatively, the gate insulating layer120may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material formed by an LPCVD process, a PECVD process, an UHV-CVD process, or an ALD process. In some embodiments, in comparison withFIG. 18B, the gate insulating layer120may be formed on both inner walls of the trench108located in the active region106and the isolation layer104.

A preliminary work-function control layer140may be conformally formed on the bottom portion and the inner wall of the trench108. The preliminary work-function control layer140may be formed on the gate insulating layer120to a uniform thickness. The preliminary work-function control layer140may include a metal, a metal nitride, or a metal carbide, such as Ti, TiN, TiAlN, TiAlC, TiAlCN, TiSiCN, Ta, TaN, TaAlN, TaAlCN, and TaSiCN.

Referring toFIGS. 17 and 18C, in operation30, a lower filling metal layer144may be formed on the preliminary work-function control layer140and fill the bottom portion of the trench108.

A first filling metal layer filling the trench108may be formed on the substrate102on which the preliminary work-function control layer140is formed, and an upper portion of the first filling metal layer may be etched back to a partial height, thereby forming the lower filling metal layer144. The lower filling metal layer144may be formed by using at least one of W, WN, TiN, and TaN.

During the etchback process of the first filling metal layer, the preliminary work-function control layer140may not be removed but remain on the inner wall of the trench108. Thus, a portion of the preliminary work-function control layer140may be exposed on the inner wall of the trench108at a higher level than a top surface of the lower filling metal layer144. Here, the portion of the preliminary work-function control layer140exposed at the higher level than the top surface of the lower filling metal layer144will be referred to as a first portion140_1, while a portion of the preliminary work-function control layer140, which is located at a lower level than the top surface of the lower filling metal layer144and covered with the lower filling metal layer144, will be referred to as a second portion140_2.

FIG. 18Cillustrates an example in which the preliminary work-function control layer140is not removed. In some embodiments, however, an upper portion and/or a side portion of the preliminary work-function control layer140may be removed. For example, during the etchback process of the first filling metal layer, the upper portion and/or the side portion of the preliminary work-function control layer140may be removed so that the first portion140_1of the preliminary work-function control layer140, which is exposed at a higher level than the top surface of the lower filling metal layer144, may have a spacer-type sectional shape. In this case, the semiconductor device100L described with reference toFIG. 16may be formed.

Referring toFIGS. 17 and 18D, in operation40, a work-function controlling metal material may be diffused into the first portion140_1of the preliminary work-function control layer140such that a first work function of a material included in the first portion140_1of the preliminary work-function control layer140, located at a higher level than the top surface of the lower filling metal layer144, is less than a second work function of a material included in the second portion140_2of the preliminary work-function control layer140, located at a lower level than the top surface of the lower filling metal layer144.

A metal-containing liner149may be formed on the inner wall of the trench108so that the work-function controlling metal material may diffuse into the first portion140_1of the preliminary work-function control layer140. The metal-containing liner149may be conformally formed on the first portion140_1of the preliminary work-function control layer140and the top surface of the lower filling metal layer144within the trench108. Alternatively, the metal-containing liner149may be formed in the trench108before forming the preliminary work-function control layer140.

The work-function controlling metal material included in the metal-containing liner149may diffuse into the first portion140_1of the preliminary work-function control layer140which contacts the metal-containing liner149. The work-function controlling metal material may be a material that may uniformly diffuse into a material included in the preliminary work-function control layer140, and thus, the work-function controlling metal material may diffuse into the first portion140_1of the preliminary work-function control layer140from the metal-containing liner149. In the first portion140_1of the preliminary work-function control layer140, the work-function controlling metal material may be substantially and uniformly distributed, or may be distributed with a gradient in its concentration profile according to a vertical direction (Z direction) and/or a horizontal direction (Y direction).

Optionally, an annealing process may be performed on the substrate102on which the metal-containing liner149is formed, so that the work-function controlling metal material included in the metal-containing liner149may further diffuse into the first portion140_1of the preliminary work-function control layer140.

The annealing process may be, for example, a rapid thermal annealing (RTA) process, but is not limited thereto. A temperature, time duration, and atmosphere of the annealing process may be appropriately selected according to kinds/types and thicknesses of the metal-containing liner149and the preliminary work-function control layer140. Furthermore, process conditions of the annealing process may be determined such that the work-function controlling metal material included in the metal-containing liner149sufficiently diffuses into the first portion140_1of the preliminary work-function control layer140without changing properties of a gate insulating layer120or degrading reliability of the gate insulating layer120.

In some embodiments, the process conditions of the annealing process may be selected such that the work-function controlling metal material included in the metal-containing liner149diffuses by a predetermined distance in a horizontal direction and/or a vertical direction into not only the first portion140_1of the preliminary work-function control layer140but also an upper portion of the second portion140_2of the preliminary work-function control layer140. In this case, the semiconductor device100C described with reference toFIG. 7may be formed.

During the removal of the metal-containing liner149, the first portion140_1of the preliminary work-function control layer140may not be removed, but rather may be exposed again on the inner wall of the trench108. Also, the top surface of the lower filling metal layer144, which has been covered with the metal-containing liner149, may be exposed again on the inner wall of the trench108.

During the removal of the metal-containing liner149, a sidewall of the first portion140_1of the preliminary work-function control layer140may also be removed so that a width of the first portion140_1of the preliminary work-function control layer140may be less than a width of the second portion140_2of the preliminary work-function control layer140. In this case, the semiconductor device100D described with reference toFIG. 8may be formed.

FIG. 18Eillustrates an example in which the metal-containing liner149is completely removed, but present inventive concepts are not limited thereto. The metal-containing liner149may not be completely removed but remain. For example, an anisotropic etching process may be performed on the metal-containing liner149so that only a portion of the metal-containing liner149located on the top surface of the lower filling metal layer144may be removed, and a portion of the metal-containing liner149in contact with the sidewall of the first portion140_1of the preliminary work-function control layer140may remain. In this case, the semiconductor devices100G,100H,100I, and100J described with reference toFIGS. 11 to 14may be formed. Also, in some embodiments, the process of removing the metal-containing liner149may be omitted. In this case, not only the portion of the metal-containing liner149in contact with the sidewall of the first portion140_1of the preliminary work-function control layer140but also the portion of the metal-containing liner149on the lower filling metal layer144may remain. Accordingly, the semiconductor device100F described with reference toFIG. 10may be formed.

Referring toFIG. 18F, a second filling metal layer filling the trench108may be formed on the first portion140_1of the preliminary work-function control layer140and the lower filling metal layer144. An upper portion of the second filling metal layer may be etched back to a partial height to form an upper filling metal layer148. The upper filling metal layer148may be formed by using at least one of W, WN, TiN, and TaN.

In the process of etching back the second filling metal layer, an upper portion of the first portion140_1of the preliminary work-function control layer140may also be etched back to a partial height. Thus, a top surface of the first portion140_1of the preliminary work-function control layer140may be formed at the same level as a top surface of the upper filling metal layer148. The first portion140_1of the preliminary work-function control layer140, which is located on the sidewall of the upper filling metal layer148after etching back an upper portion of the preliminary work-function control layer140, may be referred to as an upper work-function control layer146. Also, the second portion140_2of the preliminary work-function control layer140may be referred to as a lower work-function control layer142.

In some embodiments, during the etchback process, the first portion140_1of the preliminary work-function control layer140may be etched at a higher etch rate than the second filling metal layer, and the top surface of the first portion140_1of the preliminary work-function control layer140may be at a lower level than the top surface of the upper filling metal layer148. In this case, the semiconductor devices100A and100B described with reference toFIGS. 5 and 6may be formed.

Thereafter, the remaining portion of the trench108may be filled with an insulating material, and the insulating material may be planarized until the top surface of the substrate102is exposed so that a gate capping layer136may be formed on the inner wall of the trench108. Subsequently, the first mask (refer to310inFIG. 18E) may be removed.

Referring toFIG. 18G, a first insulating interlayer170may be formed on the exposed top surface of the substrate102. An opening may be formed through the first insulating interlayer170to expose the first source/drain region109A, and a bit line contact152and a bit line intermediate layer154may be sequentially formed in the opening. The bit line contact152may be electrically connected to the first source/drain region109A. Then, a bit line156and a bit line capping layer158which extend in a second direction may be formed on the first insulating interlayer170.

A second insulating interlayer172may be formed on the first insulating interlayer170to cover side surfaces of the bit line156and the bit line capping layer158. Thereafter, an opening may be formed in the first and second insulating interlayers170and172to expose a top surface of the second source/drain region109B, and a contact structure160may be formed in the opening. The contact structure may include a lower contact pattern162, a metal silicide layer164, and an upper contact pattern166, which may be electrically connected to the second source/drain region109B, and a barrier layer168surrounding a side surface and a bottom surface of the upper contact pattern166.

Referring toFIG. 18H, a support layer174and a mold layer350may be formed on the second insulating interlayer172and may include an opening350H exposing a top surface of the contact structure160.

A lower electrode182may be formed on the support layer174and the mold layer350and conformally cover an inner wall of the opening350H, and the mold layer350may be removed. Subsequently, a capacitor dielectric layer184and an upper electrode186may be formed on the lower electrode182.

The above-described processes may be performed, thereby completing the manufacture of the semiconductor device100.

FIG. 19is a cross-sectional view of a method of manufacturing a semiconductor device100according to some embodiments.

To begin with, the processes described with reference toFIGS. 17 and 18A to 18Cmay be performed and thus, a gate insulating layer120, a preliminary work-function control layer140, and a lower filling metal layer144may be formed in a trench108of a substrate102.

Referring toFIGS. 17 and 19, in operation40, a work-function controlling metal material may be diffused into a first portion140_1of the preliminary work-function control layer140such that a first work function of a material included in a first portion140_1of the preliminary work-function control layer140, located at a higher level than a top surface of the lower filling metal layer144, is lower than a second work function of a material included in a second portion140_2of the preliminary work-function control layer140, located at a lower level than the top surface of the lower filling metal layer144.

In some embodiments, to diffuse the work-function controlling metal material into the first portion140_1of the preliminary work-function control layer140, an ion implantation process P110may be performed on the substrate102so that ions of the work-function controlling metal material may be implanted into the first portion140_1of the preliminary work-function control layer140.

Ions of the work-function controlling metal material may be implanted into the first portion140_1of the preliminary work-function control layer140, which is exposed in the trench108at a higher level than the top surface of the lower filling metal layer144, while the work-function controlling metal material may be insubstantially/hardly implanted into the second portion140_2of the preliminary work-function control layer140, which is located at a lower level than the top surface of the lower filling metal layer144. Thus, the first portion140_1of the preliminary work-function control layer140into which the ions of the work-function controlling metal material are implanted may include a material having a substantially different composition from a material included in the second portion140_2of the preliminary work-function control layer140. Here, the first portion140_1of the preliminary work-function control layer140into which the ions of the work-function controlling metal material are implanted may be referred to as an upper work-function control layer146, while the second portion140_2of the preliminary work-function control layer140into which the work-function controlling metal material is not implanted may be referred to as a lower work-function control layer142.

In some embodiments, the upper work-function control layer146may include a metal, a metal nitride, or a metal carbide, such as Ti, TiN, TiAlN, TiAlC, TiAlCN, TiSiCN, Ta, TaN, TaAlN, TaAlCN, and TaSiCN, which may contain the work-function controlling metal material at a first concentration/content. The first concentration/content may range from about 0.01 at % to about 10 at %, but is not limited thereto. The lower work-function control layer142may include a metal, a metal nitride, or a metal carbide, such as Ti, TiN, TiAlN, TiAlC, TiAlCN, TiSiCN, Ta, TaN, TaAlN, TaAlCN, and TaSiCN, which may not substantially include the work-function controlling metal material.

In some embodiments, the ion implantation process P110may be an ion implantation process for implanting ions of a metal, such as lanthanum (La), strontium (Sr), antimony (Sb), yttrium (Y), aluminum (Al), tantalum (Ta), hafnium (Hf), or iridium (Ir). For example, the ion implantation process P110may be performed at an ion implantation energy of about 10 keV to about 300 keV, but present inventive concepts are not limited thereto. For example, the ion implantation process P110may be performed at an ion implantation dose of about 1×1017atoms/cm2to about 5×1019atoms/cm2, but present inventive concepts are not limited thereto. Also, the ion implantation process P110may be an oblique ion implantation process using an ion implantation inclination angle of about 0.1° to about 30° with respect to the top surface of the substrate102. An ion implantation energy, dose, and inclination angle of the ion implantation process P110may be appropriately selected according to a thickness of the preliminary work-function control layer140and a type/kind of the work-function controlling metal material implanted into the preliminary work-function control layer140, and a required first concentration/content of the work-function controlling metal material.

In some embodiments, the ion implantation process P110for implanting the work-function controlling metal material into the preliminary work-function control layer140may be an oblique ion implantation process, and an interface between the upper work-function control layer146and the lower work-function control layer142may be inclined at a predetermined angle with respect to the top surface of the substrate102. Also, the work-function controlling metal material may be implanted and/or diffused into as far as an upper portion of the second portion140_2of the preliminary work-function control layer140located at a lower level than the top surface of the lower filling metal layer144. Thus, a lowermost surface of the upper work-function control layer146may be located at a lower level than the top surface of the lower filling metal layer144. In this case, the semiconductor device100C described with reference toFIG. 7may be formed.

Subsequently, an annealing process may be optionally performed on the substrate102.

The annealing process may be, for example, an RTA process, but is not limited thereto. A temperature, time duration, and atmosphere of the annealing process may be appropriately selected according to a type/kind and thickness of the preliminary work-function control layer140, a type/kind of the work-function controlling metal material, and a desired/required first concentration/content of the work-function controlling metal material. In addition, process conditions of the annealing process may be determined such that the work-function controlling metal material implanted into the first portion140_1of the preliminary work-function control layer140due to the ion implantation process P110is sufficiently diffused and distributed throughout the entire volume of the first portion140_1of the preliminary work-function control layer140without changing properties of the gate insulating layer120or degrading reliability of the gate insulating layer120.

In some embodiments, the process conditions of the annealing process may be determined such that the work-function controlling metal material implanted into the first portion140_1of the preliminary work-function control layer140due to the ion implantation process P110is sufficiently diffused into an interface between the first portion140_1of the preliminary work-function control layer140and the gate insulating layer120and piled up around the interface in the first portion140_1of the preliminary work-function control layer140without changing the properties of the gate insulating layer120or degrading the reliability of the gate insulating layer120.

In some embodiments, process conditions of the annealing process may be selected such that the work-function controlling metal material implanted into the first portion140_1of the preliminary work-function control layer140due to the ion implantation process P110may diffuse into as far as an upper portion of the second portion140_2of the preliminary work-function control layer140located at a lower level than the top surface of the lower filling metal layer144. In this case, a bottom surface of the upper work-function control layer146may be located at a lower level than the top surface of the lower filling metal layer144. Thus, the semiconductor devices100C and100E described with reference toFIGS. 7 and 9may be formed.

Subsequently, the processes described with reference toFIGS. 18F to 18Hmay be performed, thereby completing the manufacture of the semiconductor device100.

FIGS. 20A and 20Bare cross-sectional views of a method of manufacturing a semiconductor device100K (illustrated inFIG. 15) according to some embodiments.

To begin with, the processes described with reference toFIGS. 17 and 18A and 18Bmay be performed and thus, a gate insulating layer120and a preliminary work-function control layer140P1may be located in a trench108of a substrate102.

Referring toFIG. 20A, a filling metal layer140P2may be formed on the preliminary work-function control layer140P1to fill the inside of the trench108. Thereafter, upper portion of the filling metal layer140P2and the preliminary work-function control layer140P1may be etched back. Thus, top surfaces of the filling metal layer140P2and the preliminary work-function control layer140P1may be located within the trench108at a lower level than an uppermost surface of the substrate102.FIG. 20Aillustrates an example in which the top surface of the preliminary work-function control layer140P1is at substantially the same level as the top surface of the filling metal layer140P2, but present inventive concepts are not limited thereto. Unlike the structure shown inFIG. 20A, an upper portion of the preliminary work-function control layer140P1may be further removed during the etchback process so that the top surface of the preliminary work-function control layer140P1is at a lower level than the top surface of the filling metal layer140P2.

Thereafter, a metal-containing liner149K may be conformally formed on an inner wall of the trench108. The metal-containing liner149K may be formed to a predetermined thickness on the gate insulating layer120and the top surfaces of the filling metal layer140P2and the preliminary work-function control layer140P1within the trench108.

In some embodiments, the metal-containing liner149K may include a work-function controlling metal material. The metal-containing liner149K may include a metal oxide including lanthanum (La), strontium (Sr), antimony (Sb), yttrium (Y), aluminum (Al), tantalum (Ta), hafnium (Hf), or iridium (Ir). However, a material included in the metal-containing liner149K is not limited to the above-described examples. The metal-containing liner149K may include not only a metal oxide but also/alternatively the above-described metals, a metal oxynitride, or a metal nitride.

Referring toFIG. 20B, the work-function controlling metal material included in the metal-containing liner149K may be diffused into the preliminary work-function control layer140P1. For example, the work-function controlling metal material included in the metal-containing liner149K may be diffused into the preliminary work-function control layer140P1to a first height/span H1K from the top surface of the preliminary work-function control layer140P1.

Here, an upper portion of the preliminary work-function control layer140P1, into which the work-function controlling metal material diffuses and which has the first height H1K from the top surface of the preliminary work-function control layer140P1, may be referred to as an upper work-function control layer146K, while a lower portion of the preliminary work-function control layer140P1located under the upper work-function control layer146K may be referred to as a lower work-function control layer142K. Also, a portion of the filling metal layer140P2located at the same level as the upper work-function control layer146K may be referred to as an upper filling metal layer148K, while a lower portion of the filling metal layer140P2located under the upper filling metal layer148K may be referred to as a lower filling metal layer144K.

Optionally, an annealing process P120may be performed on the substrate102on which the metal-containing liner149K is formed. The annealing process P120may be an RTA process, but is not limited thereto. A temperature, time duration, and atmosphere of the annealing process P120may be appropriately selected according to types/kinds and thicknesses of the metal-containing liner149K and the preliminary work-function control layer140P1and a desired/required first height H1K. In some embodiments, however, metal atoms (e.g., lanthanum atoms) may naturally diffuse from the metal-containing liner149K into the preliminary work-function control layer140P1without using the annealing process P120.

In some embodiments, the upper work-function control layer146K may be integrally formed with the lower work-function control layer142K, and the upper filling metal layer148K may be integrally formed with the lower filling metal layer144K.

In some embodiments, the upper work-function control layer146K may include the work-function controlling metal material at a first concentration/content. The first concentration/content may range from about 0.01 at % to about 10 at %, but is not limited thereto. Also, the first concentration/content of the work-function controlling metal material included in the upper work-function control layer146K may be substantially constant or vary in a vertical direction (Z direction). For example, at least a partial region of the upper work-function control layer146K may have a concentration/content profile in which the first concentration/content of the work-function controlling metal material decreases (is reduced) from the top surface toward the bottom surface of the upper work-function control layer146K in the vertical direction (Z direction).

Thereafter, referring back toFIG. 15, an anisotropic etching process may be performed on the metal-containing liner149K so that a portion of the metal-containing liner149K located on the upper filling metal layer148K may be removed, and the metal-containing liner149K may remain on the upper work-function control layer146K and the gate insulating layer120.

Subsequently, the processes described with reference toFIGS. 18F to 18Hmay be performed, thereby completing the manufacture of the semiconductor device100K.

FIG. 21is a block diagram of a system1000including a semiconductor device according to some embodiments.

Referring toFIG. 21, the system1000may include a controller1010, an input/output (I/O) device1020, a memory device1030, and an interface1040. The system1000may be a mobile system or a system configured to transmit or receive information. In some embodiments, the mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card. The controller1010may be configured to control an execution program in the system1000and may include a microprocessor, a digital signal processor (DSP), a microcontroller, or a similar device thereto. The I/O device1020may be used to input or output data to and from the system1000. The system1000may be connected to an external device (e.g., a personal computer (PC) or a network) by using the I/O device1020and may exchange data with the external device. The I/O device1020may be, for example, a keypad, a keyboard, or a display device.

The memory device1030may store code and/or data for operations of the controller1010or store data processed by the controller1010. The memory device1030may include at least one of the semiconductor devices100,100A,100B,100C,100D,100E,100F,100G,100H,100I,100K, and100L described with reference toFIGS. 1 to 20B, according to some embodiments.

The interface1040may be a data transmission path between the system1000and an external device. The controller1010, the I/O device1020, the memory device1030, and the interface1040may communicate with one another via a bus1050. The system1000may be used for a mobile phone, an MPEG-1 audio layer 3 (MP3) player, a navigation device, a portable multimedia player (PMP), a solid-state disk (SSD), or household appliances.

FIG. 22is a block diagram of a memory card1100including a semiconductor device according to some embodiments.

Referring toFIG. 22, the memory card1100may include a memory device1110and a memory controller1120.

The memory device1110may store data. In some embodiments, the memory device1110may have non-volatile characteristics and retain stored data even if a power supply is interrupted. The memory device1110may include at least one of the semiconductor devices100,100A,100B,100C,100D,100E,100F,100G,100H,100I,100K, and100L described with reference toFIGS. 1 to 20B, according to some embodiments.

The memory controller1120may read data stored in the memory device1110or may store data in the memory device1110in response to read/write requests of a host1130. The memory controller1120may include at least one of the semiconductor devices100,100A,100B,100C,100D,100E,100F,1000,100H,100I,100K, and100L described with reference toFIGS. 1 to 20B, according to some embodiments.