Display device and method for driving same

A drive circuit classifies frame periods as a drive period and a pause period, and applies a selection voltage to scanning lines in turn and applies voltages according to a video signal (a measurement voltage in the case of measurement targets) to data lines in turn during the drive period. During the pause period, the drive circuit applies the selection voltage to one scanning line corresponding to measurement target pixel circuits, and a measurement circuit measures drive currents outputted to the data lines from the measurement target pixel circuits. The drive circuit may set a write period and a measurement period in the pause period. During the write period, the drive circuit may apply the measurement voltage to the data lines. During the measurement period, the measurement circuit may measure drive currents outputted to the data lines from the measurement target pixel circuits.

TECHNICAL FIELD

The present invention relates to a display device, and more particularly to a display device including current-driven type light-emitting elements such as organic EL elements, and a method for driving the display device.

BACKGROUND ART

In recent years, an organic EL (Electro Luminescence) display device has been receiving attention as a thin, lightweight, fast response display device. The organic EL display device includes a plurality of pixel circuits arranged two-dimensionally. Each pixel circuit of the organic EL display device includes an organic EL element and a drive transistor. The drive transistor is provided in series with the organic EL element, and controls an amount of current flowing through the organic EL element (hereinafter, referred to as drive current). The organic EL element emits light at a luminance determined according to the amount of drive current.

In the organic EL display device, variations occur in the characteristics (threshold voltage and mobility) of the drive transistors. If variations occur in the characteristics of the drive transistors, then variations occur in the amounts of drive current and accordingly luminance nonuniformity occurs on a display screen. Hence, in order for the organic EL display device to perform high image quality display by suppressing luminance nonuniformity on the display screen, it is necessary to compensate for variations in the characteristics of the drive transistors.

Various types of organic EL display devices that compensate for variations in the characteristics of the drive transistors are known conventionally. For example, Patent Document 1 describes an organic EL display device that reads out a drive current externally via a power supply line, updates a correction gain and a correction offset based on a measured amount of the drive current, and corrects a video signal using the correction gain and the correction offset. Patent Document 2 describes an organic EL display device that reads out a drive current externally via a data line, updates a threshold voltage of a drive transistor based on a result of comparison between a measured amount of the drive current and a target amount, and corrects a video signal using the threshold voltage.

Apart from this, as a low power consumption display device, there is known a display device that performs pause driving (also called intermittent driving or low-frequency driving). The pause driving is a driving method in which, when the same image is continuously displayed, frame periods are classified as a drive period and a pause period, and a drive circuit operates during the drive period and the operation of the drive circuit is stopped during the pause period. The pause driving can be applied when transistors in a pixel circuit have an excellent off-leakage characteristic (small off-leakage current). A display device that performs the pause driving is described in, for example, Patent Document 3.

PRIOR ART DOCUMENTS

Patent Documents

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

In the following, attention is focused on an organic EL display device that reads out a drive current externally via a data line in order to compensate for variations in the characteristics of a drive transistor. In addition, as a display device according to a comparative example, a display device is considered that writes voltages according to a video signal (hereinafter, referred to as data voltages) to pixel circuits in all rows and measures drive currents outputted from pixel circuits in one row, during one frame period. A pixel circuit whose drive current is to be measured is hereinafter referred to as measurement target pixel circuit.

FIG. 18is a timing chart of the display device according to the comparative example.FIG. 18describes changes in voltages on scanning lines SL1to SLm for a case in which pixel circuits in an i-th row are measurement targets. As shown inFIG. 18, in order to write data voltages to the pixel circuits in first to m-th rows in turn, voltages on the scanning lines SL1to SLm are controlled to a high level in turn for one line period (for a time period Ts1). Note, however, that for the pixel circuits in the i-th row, in order to perform a write of data voltages and a measurement of drive currents, the voltage on the scanning line SLi is controlled to the high level for a time period Ts2(>Ts1). The time period Ts2is, for example, about several times longer than the time period Ts1. As such, in the display device according to the comparative example, a selection period of the scanning line SLi corresponding to the measurement target pixel circuits is longer than the selection periods of other scanning lines. In addition, a scanning line whose selection period is longer than other scanning lines is switched every frame period.

A scanning line drive circuit of a display device is generally configured such that flip-flops are connected in multiple stages, a clock signal is supplied to a clock terminal of the flip-flop in each stage, and a start pulse is supplied to an input terminal of the flip-flop in the first stage. However, a scanning line drive circuit of the display device according to the comparative example needs to control voltages on the scanning lines in the manner shown inFIG. 18. Hence, in the display device according to the comparative example, the configuration of the scanning line drive circuit becomes more complex than that of the general display device.

In addition, since the drive current is a very small current of the order of μA or less, to accurately measure the drive current, long measurement time is required. However, in the display device according to the comparative example, since data voltages are written to the pixel circuits in all rows during one frame period, sufficient time for measurement of drive currents cannot be secured. Due to this, the display device according to the comparative example has a problem that the display device cannot sufficiently compensate for variations in the characteristics of the drive transistors and thus cannot sufficiently suppress luminance nonuniformity on a display screen. In addition, the display device according to the comparative example has another problem that, since the display device performs a write of data voltages and a measurement of drive currents during the same frame period, the display device has high peak power consumption.

An object of the present invention is therefore to provide a low power consumption display device that has a scanning line drive circuit with a simple configuration and that is capable of effectively suppressing luminance nonuniformity, and a method for driving the display device.

Means for Solving the Problems

According to a first aspect of the present invention, there is provided a display device having current-driven type light-emitting elements, the display device including: a plurality of pixel circuits arranged corresponding to intersections of a plurality of scanning lines and a plurality of data lines; a drive circuit configured to write voltages to the pixel circuits by driving the scanning lines and the data lines; a measurement circuit configured to measure drive currents outputted to the data lines from the pixel circuits; and a correction circuit configured to correct a video signal based on the drive currents measured by the measurement circuit, wherein each of the pixel circuits includes: a light-emitting element; a drive transistor provided in series with the light-emitting element and configured to output a drive current of an amount according to a voltage between a control terminal and a light-emitting element side conduction terminal of the drive transistor; and an input/output transistor provided between the light-emitting element side conduction terminal of the drive transistor and a corresponding one of the data lines and having a control terminal connected to a corresponding one of the scanning lines, the drive circuit is configured to classify frame periods as a drive period and a pause period, to apply a selection voltage to the scanning lines in turn and apply voltages to be written to the pixel circuits to the data lines in turn during the drive period, and to apply the selection voltage to one or more scanning lines corresponding to measurement target pixel circuits during the pause period, and the measurement circuit is configured to measure drive currents outputted from the measurement target pixel circuits during the pause period.

According to a second aspect of the present invention, in the first aspect of the present invention, the drive circuit is configured to apply voltages according to a corrected video signal to the data lines during a selection period of a scanning line corresponding to pixel circuits that are not measurement targets, in the drive period, and to apply a measurement voltage to the data lines during a selection period of a scanning line corresponding to the measurement target pixel circuits, in the drive period.

According to a third aspect of the present invention, in the second aspect of the present invention, the drive circuit is configured to classify four frame periods as a first drive period, a first pause period, a second drive period, and a second pause period in this order, to apply a first measurement voltage to the data lines during the selection period of the scanning line corresponding to the measurement target pixel circuits in the first drive period, and to apply a second measurement voltage to the data lines during the selection period of the scanning line corresponding to the measurement target pixel circuits in the second drive period, the measurement circuit is configured to measure drive currents outputted from the measurement target pixel circuits as a first drive current during the first pause period, and to measure drive currents outputted from the measurement target pixel circuits as a second drive current during the second pause period, and the correction circuit is configured to correct a portion of the video signal corresponding to the measurement target pixel circuits, based on the first and second drive currents.

According to a fourth aspect of the present invention, in the first aspect of the present invention, the drive circuit is configured to apply voltages according to a corrected video signal to the data lines during a selection period of each scanning line in the drive period, to set a write period and a measurement period in the pause period, and to apply a measurement voltage to the data lines during the write period, and the measurement circuit is configured to measure drive currents outputted from the measurement target pixel circuits during the measurement period.

According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the drive circuit is configured to set a first write period, a first measurement period, a second write period, and a second pause period in this order in the pause period, to apply a first measurement voltage to the data lines during the first write period, and to apply a second measurement voltage to the data lines during the second write period, the measurement circuit is configured to measure drive currents outputted from the measurement target pixel circuits as a first drive current during the first measurement period, and to measure drive currents outputted from the measurement target pixel circuits as a second drive current during the second measurement period, and the correction circuit is configured to correct a portion of the video signal corresponding to the measurement target pixel circuits, based on the first and second drive currents.

According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the drive circuit is configured to set a third write period after the second measurement period in the pause period, and to apply voltages according to the corrected video signal to the data lines during the third write period.

According to a seventh aspect of the present invention, in the second or fourth aspect of the present invention, the drive circuit is configured to apply the selection voltage to one scanning line corresponding to the measurement target pixel circuits during one pause period.

According to an eighth aspect of the present invention, in the second or fourth aspect of the present invention, the drive circuit is configured to apply the selection voltage to a plurality of scanning lines in turn during one pause period, the plurality of scanning lines being corresponding to the measurement target pixel circuits.

According to a ninth aspect of the present invention, in the first aspect of the present invention, the drive circuit is configured to apply voltages according to a corrected video signal to the data lines during a selection period of each scanning line in the drive period, and during a consecutive pause period consisting of a series of the pause periods, to apply the selection voltage to the scanning lines in turn, set a write period and a measurement period in a selection period of each scanning line, and apply a measurement voltage to the data lines during each write period, and the measurement circuit is configured to measure drive currents outputted from the measurement target pixel circuits during each measurement period.

According to a tenth aspect of the present invention, in the ninth aspect of the present invention, the drive circuit is configured to apply the selection voltage to all of the scanning lines in turn during one consecutive pause period.

According to an eleventh aspect of the present invention, in the tenth aspect of the present invention, the drive circuit is configured to apply a first measurement voltage to the data lines during each write period in a first consecutive pause period, and to apply a second measurement voltage to the data lines during each write period in a second consecutive pause period, the measurement circuit is configured to measure drive currents outputted from the measurement target pixel circuits as a first drive current during each measurement period in the first consecutive pause period, and to measure drive currents outputted from the measurement target pixel circuits as a second drive current during each measurement period in the second consecutive pause period, and the correction circuit is configured to correct a portion of the video signal corresponding to the measurement target pixel circuits, based on the first and second drive currents.

According to a twelfth aspect of the present invention, in one of the third, fifth and eleventh aspects of the present invention, the display device further includes a storage unit configured to store, for each of the pixel circuits, first and second correction data to be used to correct the video signal, wherein the correction circuit is configured to update first correction data for the measurement target pixel circuits based on the first drive current, to update second correction data for the measurement target pixel circuits based on the second drive current, and to correct a portion of the video signal corresponding to the measurement target pixel circuits, based on the first and second correction data.

According to a thirteenth aspect of the present invention, in the first aspect of the present invention, the drive circuit includes a first scanning line drive circuit configured to drive the scanning lines during the drive period; and a second scanning line drive circuit configured to drive the scanning lines during the pause period.

According to a fourteenth aspect of the present invention, in the first aspect of the present invention, the drive circuit and the measurement circuit are configured to share drive/measurement circuits corresponding to the data lines, each of the drive/measurement circuits includes an operational amplifier having an inverting input terminal connected to a corresponding one of the data lines; a switching element provided between the inverting input terminal and an output terminal of the operational amplifier; and a passive element provided between the inverting input terminal and output terminal of the operational amplifier and in parallel to the switching element, and the passive element is either one of a capacitive element and a resistive element.

According to a fifteenth aspect of the present invention, there is provided a method for driving a display device including a plurality of pixel circuits arranged corresponding to intersections of a plurality of scanning lines and a plurality of data lines, each of the pixel circuits including a current-driven type light-emitting element; a drive transistor provided in series with the light-emitting element and configured to output a drive current of an amount according to a voltage between a control terminal and a light-emitting element side conduction terminal of the drive transistor; and an input/output transistor provided between the light-emitting element side conduction terminal of the drive transistor and a corresponding one of the data lines and having a control terminal connected to a corresponding one of the scanning lines, the method including: a driving step of writing voltages to the pixel circuits by driving the scanning lines and the data lines; a measuring step of measuring drive currents outputted to the data lines from the pixel circuits; and a correcting step of correcting a video signal based on the measured drive currents, wherein in the driving step, frame periods are classified as a drive period and a pause period, and during the drive period, a selection voltage is applied to the scanning lines in turn and voltages to be written to the pixel circuits are applied to the data lines in turn, and during the pause period, the selection voltage is applied to one or more scanning lines corresponding to measurement target pixel circuits, and in the measuring step, during the pause period, drive currents outputted from the measurement target pixel circuits are measured.

Effects of the Invention

According to the first or fifteenth aspect of the present invention, frame periods are classified as a drive period and a pause period, and drive currents outputted from measurement target pixel circuits to the data lines are measured during the pause period. A scanning line drive circuit that applies a selection voltage to the plurality of scanning lines in turn during the drive period and applies the selection voltage to one or more scanning lines during the pause period has a simple configuration. In addition, by measuring drive currents during the pause period, sufficient time for measurement of drive currents can be secured and variations in the characteristics of the drive transistors can be effectively compensated for, enabling to effectively suppress luminance nonuniformity on a display screen. In addition, by performing a write of voltages and a measurement of drive currents during different frame periods, peak power consumption can be reduced. Therefore, a low power consumption display device that has a scanning line drive circuit with a simple configuration and that is capable of effectively suppressing luminance nonuniformity, or a method for driving the display device can be provided.

According to the second aspect of the present invention, a measurement voltage is written to the measurement target pixel circuits during the drive period. Therefore, drive currents outputted from the pixel circuits to which the measurement voltage has been written can be measured during the subsequent pause period.

According to the third aspect of the present invention, each of a write of a measurement voltage and a measurement of a drive current is performed twice on the measurement target pixel circuit during four frame periods, and a video signal is corrected based on two measurement results. Therefore, variations in two types of characteristics (e.g., threshold voltage and mobility) of a drive transistor can be compensated for, enabling to effectively suppress luminance nonuniformity on a display screen.

According to the fourth aspect of the present invention, a measurement voltage is written to the measurement target pixel circuits during a write period in the pause period. Therefore, drive currents outputted from the pixel circuits to which the measurement voltage has been written can be measured during the subsequent measurement period.

According to the fifth aspect of the present invention, each of a write of a measurement voltage and a measurement of a drive current is performed twice on a measurement target pixel circuit during one frame period, and a video signal is corrected based on two measurement results. Therefore, variations in two types of characteristics of a drive transistor can be compensated for, enabling to effectively suppress luminance nonuniformity on a display screen.

According to the sixth aspect of the present invention, during a third write period, voltages according to a video signal which is corrected based on measurement results obtained during the first and second measurement periods are written to the measurement target pixel circuits. Therefore, results of compensating for variations in the characteristics of drive transistors can be immediately reflected in a display image.

According to the seventh aspect of the present invention, variations in the characteristics of drive transistors in a plurality of pixel circuits connected to one scanning line can be compensated for during one pause period.

According to the eighth aspect of the present invention, variations in the characteristics of drive transistors in a plurality of pixel circuits connected to a plurality of scanning lines can be compensated for during one pause period.

According to the ninth aspect of the present invention, a measurement voltage is written to the measurement target pixel circuits during each write period in a consecutive pause period. Therefore, drive currents outputted from the pixel circuits to which the measurement voltage has been written can be measured during the subsequent measurement period.

According to the tenth aspect of the present invention, variations in the characteristics of the drive transistors in all of the pixel circuits can be compensated for during one consecutive pause period.

According to the eleventh aspect of the present invention, each of a write of a measurement voltage and a measurement of a drive current is performed twice on all of the pixel circuits during two consecutive pause periods, and a video signal is corrected based on two measurement results. Therefore, variations in two types of characteristics of the drive transistors can be compensated for, enabling to effectively suppress luminance nonuniformity on a display screen.

According to the twelfth aspect of the present invention, two pieces of correction data are stored for each pixel circuit, the two pieces of correction data are updated based on two measurement results, and a video signal is corrected based on the two pieces of correction data. By this, variations in two types of characteristics of a drive transistor can be compensated for, enabling to effectively suppress luminance nonuniformity on a display screen.

According to the thirteenth aspect of the present invention, by dividing a circuit into a circuit that operates during the drive period and a circuit that operates during the pause period, a scanning line drive circuit can be easily formed.

According to the fourteenth aspect of the present invention, each drive/measurement circuit applies a voltage which is provided to a non-inverting input terminal of an operational amplifier, to a data line when a switching element is in an on state, and outputs a voltage according to a drive current which is outputted to the data line, from an output terminal of the operational amplifier when the switching element is in an off state. Therefore, using the drive/current measurement circuits, the drive circuit that writes voltages to the pixel circuits and the measurement circuit that measures drive currents outputted to the data lines from the pixel circuits can be easily formed.

MODES FOR CARRYING OUT THE INVENTION

First Embodiment

FIG. 1is a block diagram showing a configuration of a display device according to a first embodiment of the present invention. A display device10shown inFIG. 1is an organic EL display device including a display unit11, a display control circuit12, a first scanning line drive circuit13, a second scanning line drive circuit14, a data line drive/current measurement circuit15, a power supply voltage selection circuit16, an A/D converter17, a correction calculation circuit18, and a correction data storage unit19. In the following, m and n are integers greater than or equal to 2, i is an integer between 1 and m, inclusive, and j is an integer between 1 and n, inclusive.

The display unit11includes m scanning lines SL1to SLm, n data lines DL1to DLn, m power supply lines PL1to PLm, and (m×n) pixel circuits20. The scanning lines SL1to SLm and the power supply lines PL1to PLm are arranged parallel to each other. The data lines DL1to DLn are arranged parallel to each other so as to be orthogonal to the scanning lines SL1to SLm. The scanning lines SL1to SLm intersect the data lines DL1to DLn at (m×n) points. The (m×n) pixel circuits20are arranged at the intersections of the scanning lines SL1to SLm and the data lines DL1to DLn. A direction in which the scanning lines SL1to SLm extend (a horizontal direction inFIG. 1) is hereinafter referred to as row direction, a direction in which the data lines DL1to DLn extend (a vertical direction inFIG. 1) is hereinafter referred to as column direction, and a pixel circuit20in an i-th row and a j-th column is hereinafter referred to as PX(i,j).

The first scanning line drive circuit13is arranged along one side of the display unit11(the right side inFIG. 1). The second scanning line drive circuit14and the power supply voltage selection circuit16are arranged along an opposite side of the display unit11(the left side inFIG. 1). The data line drive/current measurement circuit15is arranged along one of the remaining sides of the display unit11(the lower side inFIG. 1).

The display control circuit12outputs control signals to control the operation of the display device10. More specifically, the display control circuit12outputs a control signal C1to the first scanning line drive circuit13, outputs a control signal C2to the second scanning line drive circuit14, and outputs a control signal C3to the data line drive/current measurement circuit15. In addition, the display control circuit12outputs a video signal D1(pre-correction video signal) to the correction calculation circuit18.

The first scanning line drive circuit13and the second scanning line drive circuit14drive the scanning lines SL1to SLm. The data line drive/current measurement circuit15selectively performs the operation of driving the data lines DL1to DLn and the operation of measuring drive currents which are outputted to the data lines DL1to DLn from the pixel circuits20. The first scanning line drive circuit13, the second scanning line drive circuit14, and the data line drive/current measurement circuit15function as a drive circuit that writes voltages to the pixel circuits20by driving the scanning lines SL1to SLm and the data lines DL1to DLn. The data line drive/current measurement circuit15also functions as a measurement circuit that measures drive currents which are outputted to the data lines DL1to DLn from the pixel circuits20. The power supply voltage selection circuit16selectively applies a first low-level power supply voltage ELVSS for display and a second low-level power supply voltage ELVSS_moni for current measurement to the power supply lines PL1to PLm. To each pixel circuit20are supplied a high-level power supply voltage ELVDD and a reference voltage Vref from a power supply circuit which is not shown.

The correction data storage unit19stores two types of correction data to be used to correct the video signal D1. More specifically, the correction data storage unit19includes a threshold voltage correction data storage unit47and a mobility correction data storage unit48. The threshold voltage correction data storage unit47stores, for each pixel circuit PX(i,j), threshold voltage correction data Vt(i,j). The mobility correction data storage unit48stores, for each pixel circuit PX(i,j), mobility correction data B(i,j).

The data line drive/current measurement circuit15outputs voltages according to drive currents which are outputted to the data lines DL1to DLn from the pixel circuits20. The A/D converter17converts the voltages outputted from the data line drive/current measurement circuit15into digital values. The digital values indicate the amounts of the drive currents outputted from the pixel circuits20. The correction calculation circuit18updates the correction data stored in the correction data storage unit19, based on the digital values outputted from the A/D converter17. In addition, the correction calculation circuit18corrects the video signal D1by referring to the correction data stored in the correction data storage unit19, and outputs a corrected video signal D2. The data line drive/current measurement circuit15drives the data lines DL1to DLn based on the corrected video signal D2.

FIG. 2is a circuit diagram showing the pixel circuit20and a part of the data line drive/current measurement circuit15.FIG. 2describes a pixel circuit PX(i,j) in an i-th row and a j-th column, and a portion of the data line drive/current measurement circuit15corresponding to a data line DLj. As shown inFIG. 2, the pixel circuit20includes N-channel TFTs (Thin Film Transistors)21to23, a capacitor24, and an organic EL element25. For the TFTs21to23, TFTs with an excellent off-leakage characteristic are used. For the TFTs21to23, for example, TFTs having a semiconductor layer which is formed of indium-gallium-zinc oxide (IGZO) are used.

The high-level power supply voltage ELVDD is applied to a drain terminal of the TFT21. A source terminal of the TFT21is connected to an anode terminal of the organic EL element25, and a cathode terminal of the organic EL element25is connected to a power supply line PLi. One conduction terminal of the TFT22is connected to the data line DLj, and the other conduction terminal of the TFT22is connected to the source terminal of the TFT21. The reference voltage Vref is applied to a drain terminal of the TFT23, and a source terminal of the TFT23is connected to a gate terminal of the TFT21. A gate terminal of the TFT22and a gate terminal of the TFT23are connected to a scanning line SLi. The capacitor24is provided between the gate terminal and source terminal of the TFT21.

The organic EL element25is a current-driven type light-emitting element. The TFT21is provided in series with the organic EL element25, and functions as a drive transistor that outputs a drive current of an amount determined according to a gate-source voltage of the TFT21. The TFT22is provided between the source terminal of the TFT21and the data line DLj, and functions as an input/output transistor having a gate terminal connected to the scanning line SLi. The TFT23is provided between a wiring line having the reference voltage Vref and the gate terminal of the TFT21, and functions as a reference voltage application transistor having a gate terminal connected to the scanning line SLi. The capacitor24functions as a holding capacitor that holds a gate-source voltage of the TFT21.

The data line drive/current measurement circuit15includes a D/A converter31, an operational amplifier32, a capacitor33, and a switch34corresponding to the data line DLj. A data voltage value Vm(i,j,P) which is included in the video signal D2is provided to an input terminal of the D/A converter31. The D/A converter31converts the data voltage value Vm(i,j,P) into an analog data voltage (represented as Vm(i,j,P) in the same manner as the data voltage value). An output terminal of the D/A converter31is connected to a non-inverting input terminal of the operational amplifier32. An inverting input terminal of the operational amplifier32is connected to the data line DLj. The switch34is provided between the inverting input terminal and output terminal of the operational amplifier32. The capacitor33is provided between the inverting input terminal and output terminal of the operational amplifier32and in parallel to the switch34. An input/output control signal DWT which is included in the control signal C3is provided to a control terminal of the switch34. The output terminal of the operational amplifier32is connected to an input terminal of an A/D converter17.

When the input/output control signal DWT is at a high level, the switch34goes to an on state, and the inverting input terminal and output terminal of the operational amplifier32are short-circuited. At this time, the operational amplifier32functions as a buffer amplifier, and the data voltage Vm(i,j,P) provided to the non-inverting input terminal of the operational amplifier32is applied to the data line DLj. When the input/output control signal DWT is at a low level, the switch34goes to an off state, and the inverting input terminal and output terminal of the operational amplifier32are connected to each other through the capacitor33. At this time, the operational amplifier32and the capacitor33function as an integrating circuit, and an output voltage from the operational amplifier32is a voltage according to a drive current outputted to the data line DLj from the pixel circuit20. The A/D converter17converts the output voltage from the operational amplifier32into a digital value. The drive current measured by the data line drive/current measurement circuit15is hereinafter referred to as Im(i,j,P), and the digital value outputted from the A/D converter17is hereinafter referred to as drive current value and represented as Im (i,j,P) in the same manner as the drive current.

The display device10performs pause driving where frame periods are classified as a drive period and a pause period. The display device10writes display data voltages to the pixel circuits20during the drive period and does not write display data voltages to the pixel circuits20during the pause period. In addition, during the pause period, the display device10measures drive currents which are outputted to the data lines DL1to DLn from pixel circuits20in one row, and updates correction data stored in the correction data storage unit19, based on drive current values.

More specifically, in the display device10, a first gradation P1and a second gradation P2(>P1) are predetermined within a range of display gradations. The data line drive/current measurement circuit15generates a first measurement voltage Vm(i,j,P1) to write the first gradation P1to a pixel circuit PX(i,j), and measures a drive current outputted from the pixel circuit PX(i,j) to which the first measurement voltage Vm(i,j,P1) has been written, as a first drive current Im(i,j,P1). The correction calculation circuit18updates threshold voltage correction data Vt(i,j) stored in the threshold voltage correction data storage unit47, based on a drive current value obtained at this time (hereinafter, referred to as first drive current value Im(i,j,P1)). In addition, the data line drive/current measurement circuit15generates a second measurement voltage Vm(i,j,P2) to write the second gradation P2to the pixel circuit PX(i,j), and measures a drive current outputted from the pixel circuit PX(i,j) to which the second measurement voltage Vm(i,j,P2) has been written, as a second drive current Im(i,j,P2). The correction calculation circuit18updates mobility correction data B(i,j) stored in the mobility correction data storage unit48, based on a drive current value obtained at this time (hereinafter, referred to as second drive current value Im(i,j,P2)).

The display device10performs pause driving where a drive period and a pause period are switched alternately every frame period.FIG. 3is a diagram showing the operation of the display device10performed during drive periods and pause periods. As shown inFIG. 3, the drive circuit of the display device10classifies four consecutive frame periods F1to F4as a first drive period F1, a first pause period F2, a second drive period F3, and a second pause period F4, and classifies a frame period subsequent to the second pause period F4as a third drive period F5.

During the first drive period F1, the display device10writes a first measurement voltage Vm(i,j,P1) to a measurement target pixel circuit PX(i,j), and writes display data voltages to other pixel circuits. During the first pause period F2, the display device10measures a first drive current Im(i,j,P1) outputted from the measurement target pixel circuit PX(i,j). During the second drive period F3, the display device10writes a second measurement voltage Vm(i,j,P2) to the measurement target pixel circuit PX(i,j), and writes display data voltages to other pixel circuits. During the second pause period F4, the display device10measures a second drive current Im(i,j,P2) outputted from the measurement target pixel circuit PX(i,j). During the third drive period F5, the display device10writes a first measurement voltage to a next measurement target pixel circuit, and writes display data voltages to other pixel circuits (including the pixel circuit PX(i,j)). Note that the data voltage written to the pixel circuit PX(i,j) during the third drive period F5is a voltage based on the corrected video signal D2which is obtained by updating two types of correction data stored in the correction data storage unit19, based on the first drive current value Im(i,j,P1) and the second drive current value Im(i,j,P2), and referring to the updated correction data.

FIG. 4is a timing chart of a drive period of the display device10. During the drive period, the operation of the second scanning line drive circuit14is stopped. The first scanning line drive circuit13selects the scanning lines SL1to SLm in turn for one line period, and applies a selection voltage (here, a high-level voltage) to the selected scanning line. The data line drive/current measurement circuit15applies n data voltages based on the corrected video signal D2, to the data lines DL1to DLn, respectively. Note, however, that when pixel circuits in an i-th row are measurement targets, the data line drive/current measurement circuit15applies first measurement voltages Vm(i,1,P1) to Vm(i,n,P1) or second measurement voltages Vm(i,1,P2) to Vm (i,n,P2) to the data lines DL1to DLn, respectively, during a selection period of a scanning line SLi. The power supply voltage selection circuit16applies the first low-level power supply voltage ELVSS to the power supply lines PL1to PLm. As such, during the drive period, pixel circuits20in one row are selected in turn for one line period, and data voltages or measurement voltages are written to the pixel circuits20in the selected row. By this, data voltages or measurement voltages can be written to all of the pixel circuits20during one drive period.

FIG. 5is a timing chart of a pause period of the display device10. During the pause period, the operation of the first scanning line drive circuit13is stopped. When pixel circuits in the i-th row are measurement targets, the second scanning line drive circuit14applies the selection voltage to the scanning line SLi over one frame period. The power supply voltage selection circuit16applies the second low-level power supply voltage ELVSS_moni to the power supply line PLi, and applies the first low-level power supply voltage ELVSS to other power supply lines. The data line drive/current measurement circuit15measures drive currents outputted to the data lines DL1to DLn from the measurement target pixel circuits20. By this, n drive currents outputted from n pixel circuits20can be measured during one pause period.

The data line drive/current measurement circuit15measures the first drive current Im(i,j,P1) during the first pause period F2, and measures the second drive current Im(i,j,P2) during the second pause period F4. The measurement target pixel circuits are switched every two pause periods. By this, during2mpause periods, two types of correction data for all of the pixel circuits20which are stored in the correction data storage unit19can be updated.

FIG. 6is a diagram showing voltage write operation of the display device10. Voltage write operation for the pixel circuit PX(i,j) will be described below. The voltage write is performed during the drive period. During the drive period, the first low-level power supply voltage ELVSS is applied to the power supply line PLi. During the selection period of the pixel circuits20in the i-th row, a voltage on the scanning line SLi goes to the high level and voltages on other scanning lines go to the low level (seeFIG. 4). A data voltage Vm(i,j,P) to write a gradation P to the pixel circuit PX(i,j) is applied to the data line DLj. Note, however, that when the pixel circuits20in the i-th row are measurement targets, a first measurement voltage Vm(i,j,P1) or a second measurement voltage Vm(i,j,P2) is applied to the data line DLj. When the voltage on the scanning line SLi is changed to the high level, the TFTs22and23go to the on state. Hence, the voltage on the data line DLj is applied through the TFT22to the source terminal of the TFT21, and the reference voltage Vref is applied through the TFT23to the gate terminal of the TFT21.

At this time, a drive current Id flows between the drain and source of the TFT21, and the organic EL element25emits light at a luminance according to the drive current Id. The amount of the drive current Id and the luminance of the organic EL element25depend on the gate-source voltage Vgs of the TFT21, the high-level power supply voltage ELVDD, and the first low-level power supply voltage ELVSS.

When the voltage on the scanning line SLi is changed to the low level thereafter, the TFTs22and23go to the off state. Still after this, the gate-source voltage Vgs of the TFT21is maintained at the existing level by the action of the capacitor24. Therefore, the organic EL element25continuously emits light at a luminance according to the gate-source voltage Vgs of the TFT21.

FIG. 7is a diagram showing current measurement operation of the display device10. Current measurement operation for the pixel circuit PX(i,j) will be described below. The current measurement is performed during the pause period. When the pixel circuits20in the i-th row are measurement targets, during the pause period, a voltage on the scanning line SLi goes to the high level, and voltages on other scanning lines go to the low level (seeFIG. 5). The second low-level power supply voltage ELVSS_moni is applied to the power supply line PLi, and the first low-level power supply voltage ELVSS is applied to other power supply lines. When the source voltage of the TFT21is Vs and the light emission threshold voltage of the organic EL element25is Vt_oled, the second low-level power supply voltage ELVSS_moni is determined so as to satisfy the following equation (1):
|Vs−ELVSS_moni|<|Vt_oled|  (1)

When the voltage on the scanning line SLi is changed to the high level, the TFTs22and23go to the on state. At this time, a drive current Id flows between the drain and source of the TFT21. The amount of the drive current Id depends on the gate-source voltage Vgs of the TFT21, the high-level power supply voltage ELVDD, and the second low-level power supply voltage ELVSS_moni. Note, however, that since equation (1) holds, the drive current Id does not flow through the organic EL element25, but flows through the data line drive/current measurement circuit15via the TFT22and the data line DLj. The data line drive/current measurement circuit15measures the drive current Id outputted from the pixel circuit PX(i,j), and outputs a result of the measurement as the first drive current Im(i,j,P1) or the second drive current Im(i,j,P2).

When the voltage on the scanning line SLi is changed to the low level thereafter, the TFTs22and23go to the off state. The state of the pixel circuit PX(i,j) does not change until the voltage on the scanning line SLi is changed to the high level next time.

FIG. 8is a block diagram showing details of the correction calculation circuit18. As shown inFIG. 8, the correction calculation circuit18includes a first LUT41, a multiplier42, an adder43, a subtractor44, a second LUT45, and a CPU46. InFIG. 8, a reference character P indicates a gradation included in the video signal D1. The correction calculation circuit18performs the operation of correcting the video signal D1by referring to two types of correction data stored in the correction data storage unit19, and the operation of updating two types of correction data stored in the correction data storage unit19, based on two drive current values outputted from the A/D converter17. The correction calculation circuit18functions as a correction circuit that corrects a video signal based on drive currents measured by a measurement circuit (data line drive/current measurement circuit15). Note that the CPU46may be composed of a calculation circuit.

The first LUT41stores an overdrive voltage Vc(P) for each display gradation P. The first LUT41converts the gradation P included in the video signal D1into an overdrive voltage Vc(P). The multiplier42multiplies the overdrive voltage Vc(P) by mobility correction data B(i,j) which is read out from the mobility correction data storage unit48. The adder43adds an output from the multiplier42to threshold voltage correction data Vt(i,j) which is read out from the threshold voltage correction data storage unit47. The subtractor44subtracts an output from the adder43from the value of the reference voltage Vref. By this, correction calculation shown in the following equation (2) is performed on the gradation P included in the video signal D1:
Vm(i,j,P)=Vref−Vc(P)×B(i,j)−Vt(i,j)  (2)

The correction calculation circuit18outputs the corrected video signal D2including the obtained data voltage value Vm(i,j,P). The data line drive/current measurement circuit15drives the data lines DL1to DLn based on the corrected video signal D2.

The second LUT45stores a first target current value I(P1) for the first gradation P1and a second target current value I(P2) for the second gradation P2. The second LUT45outputs the first target current value I(P1) during the first pause period F2, and outputs the second target current value I(P2) during the second pause period F4.

The CPU46receives the first drive current value Im(i,j,P1) from the A/D converter17during the first pause period F2, and receives the second drive current value Im(i,j,P2) from the A/D converter17during the second pause period F4. When the CPU46receives the first drive current value Im(i,j,P1), the CPU46compares the first drive current value Im(i,j,P1) with the first target current value I(P1), and updates threshold voltage correction data Vt(i,j) stored in the threshold voltage correction data storage unit47, according to a result of the comparison. More specifically, when an amount of update is ΔV and a dead zone width is V_dz, the CPU46adds ΔV to the threshold voltage correction data Vt(i,j) when the following equation (3) holds, subtracts ΔV from the threshold voltage correction data Vt(i,j) when the following equation (4) holds, and does not update the threshold voltage correction data Vt(i,j) when the following equation (5) holds. The first drive current value Im(i,j,P1) approaches the first target current value I(P1) in a stepwise manner, and ultimately converges to the first target current value I(P1).
I(P1)−Im(i,j,P1)>V_dz(3)
I(P1)−Im(i,j,P1)<−V_dz(4)
|I(P1)−Im(i,j,P1)|<=V_dz(5)

In addition, when the CPU46receives the second drive current value Im(i,j,P2), the CPU46compares the second drive current value Im(i,j,P2) with the second target current value I(P2), and updates mobility correction data B(i,j) stored in the mobility correction data storage unit48, according to a result of the comparison. More specifically, when an amount of update is ΔB and a dead zone width is B_dz, the CPU46adds ΔB to the mobility correction data B(i,j) when the following equation (6) holds, subtracts ΔB from the mobility correction data B(i,j) when the following equation (7) holds, and does not update the mobility correction data B(i,j) when the following equation (8) holds. The second drive current value Im(i,j,P2) approaches the second target current value I(P2) in a stepwise manner, and ultimately converges to the second target current value I(P2).
I(P2)−Im(i,j,P2)>B_dz(6)
I(P2)−Im(i,j,P2)<−B_dz(7)
|I(P2)−Im(i,j,P2)|<=B_dz(8)

Note that an initial value of the threshold voltage correction data Vt(i,j) is a predetermined voltage value and an initial value of the mobility correction data B(i,j) is 1.

It is assumed that the threshold voltage of the TFT21is Vt and the gain of the TFT21is β. When the TFT21operates in a saturation region, the amount of drive current Id flowing between the drain and source of the TFT21is represented by the following equation (9) using the gate-source voltage Vgs of the TFT21:
Id=β/2×(Vgs−Vt)2(9)

The reference voltage Vref is applied to the gate terminal of the TFT21, and the data voltage Vm(i,j,P) is applied to the source terminal of the TFT21. Hence, equation (9) can be modified to the following equation (10):
Id=β/2×(Vref−Vm(i,j,P)−Vt)2(10)

When equation (2) is substituted into equation (10), the following equation (11) is derived:
Id=β/2×(Vc(P)×B(i,j)+Vt(i,j)−Vt)2(11)

When the drive current Id is smaller than a target amount, the drive current Id needs to be increased. To do so, the threshold voltage correction data Vt(i,j) or the mobility correction data B(i,j) may be increased. When the drive current Id is larger than the target amount, the drive current Id needs to be reduced. To do so, the threshold voltage correction data Vt(i,j) or the mobility correction data B(i,j) may be reduced.

FIG. 9is a diagram showing a gradation-current characteristic of the display device10.FIG. 9describes a characteristic for γ=2.2 as a target characteristic. The CPU46updates the threshold voltage correction data Vt(i,j) and the mobility correction data B(i,j) by the above-described method. Hence, the first drive current value Im(i,j,P1) and the second drive current value Im(i,j,P2) ultimately match their respective target values. In other words, a drive current when the first gradation P1is written to the pixel circuit PX(i,j) and a drive current when the second gradation P2is written to the pixel circuit PX(i,j) match their respective target amounts. InFIG. 9, two black closed circles match two white open circles, respectively. Hence, a drive current when an arbitrary gradation P is written to the pixel circuit PX(i,j) substantially matches a target amount set for the gradation P. Therefore, according to the display device10, by correcting the threshold voltage and mobility of the TFT21on a per pixel circuit20basis, luminance nonuniformity on a display screen is suppressed, enabling to perform high image quality display.

FIG. 10is a circuit diagram of the first scanning line drive circuit13and the second scanning line drive circuit14. As shown inFIG. 10, the first scanning line drive circuit13includes m flip-flops51connected in multiple stages. Each flip-flop51has a reset terminal R, a clock terminal CK, an input terminal D, and an output terminal Q. A reset signal RST is supplied to the reset terminals R of the m flip-flops51, and a clock signal CKa is supplied to the clock terminals CK of the m flip-flops51. A control signal SDa is supplied to the input terminal D of the flip-flop51in the first stage. The input terminals D of the flip-flops51in the second and subsequent stages are connected to the output terminals Q of the flip-flops51in their preceding stages. The output terminals Q of them flip-flops51are connected to the scanning lines SL1to SLm, respectively.

The second scanning line drive circuit14includes m flip-flops52connected in multiple stages; and m N-channel transistors53. The reset signal RST is supplied to reset terminals R of the m flip-flops52, and a clock signal CKb is supplied to clock terminals CK of the m flip-flops52. A control signal SDb is supplied to an input terminal D of the flip-flop52in the first stage. Input terminals D of the flip-flops52in the second and subsequent stages are connected to output terminals Q of the flip-flops52in their preceding stages. The m transistors53are provided between the output terminals Q of the m flip-flops52and the scanning lines SL1to SLm. A control signal CX included in the control signal C2is supplied to control terminals of the m transistors53.

FIG. 11is a timing chart of the first scanning line drive circuit13. As shown inFIG. 11, the clock signal CKa is a clock signal with a cycle of one line period. The control signal SDa goes to the high level over one line period at the beginning of a frame period. During a line period subsequent to the line period where the control signal SDa is at the high level, an output signal SLa1from the flip-flop51in the first stage goes to the high level. During the next line period, an output signal SLa2from the flip-flop51in the second stage goes to the high level. For the subsequent output signals, likewise, output signals SLa3, SLa4, . . . from the flip-flops51in the third and subsequent stages go to the high level in turn for one line period. The output signals SLa1to SLam are applied to the scanning lines SL1to SLm, respectively.

FIG. 12is a timing chart of the second scanning line drive circuit14. As shown inFIG. 12, the control signal CX goes to the low level during the drive period and goes to the high level during the pause period. The clock signal CKb is a clock signal with a cycle of four frame periods, and goes to the high level for a predetermined period of time at the beginning of the drive period. The control signal SDb goes to the high level over four frame periods before the pixel circuits20in the first row are set as measurement targets. During four frame periods subsequent to the four frame periods where the control signal SDb is at the high level, an output signal FF1_Q from the flip-flop52in the first stage goes to the high level. During the next four frame periods, an output signal FF2_Q from the flip-flop52in the second stage goes to the high level. For the subsequent output signals, likewise, output signals FF3_Q, FF4_Q, . . . from the flip-flops52in the third and subsequent stages go to the high level in turn for four frame periods.

When the control signal CX is at the high level, the m transistors53go to the on state, and the output signals FF1_Q to FFm_Q from the m flip-flops52become output signals SLb1to SLbm from the second scanning line drive circuit14. When the control signal CX is at the low level, the m transistors53go to the off state, and the output signals SLb1to SLbm from the second scanning line drive circuit14go to the low level. As a result, the output signal SLb1goes to the high level when the output signal from the flip-flop52in the first stage and the control signal CX are at the high level. The output signal SLb2goes to the high level four frame periods after high-level periods of the output signal SLb1. For the subsequent output signals, likewise, an output signal SLbi goes to the high level four frame periods after high-level periods of an output signal SLbi−1.

FIG. 13is a circuit diagram of the power supply voltage selection circuit16. As shown inFIG. 13, the power supply voltage selection circuit16includes a P-channel transistor54and an N-channel transistor55corresponding to the power supply line PLi. The first low-level power supply voltage ELVSS is applied to a source terminal of the transistor54, and the second low-level power supply voltage ELVSS_moni is applied to a source terminal of the transistor55. Drain terminals of the transistors54and55are connected to the power supply line PLi. The output signal SLbi from the second scanning line drive circuit14is supplied to gate terminals of the transistors54and55. The output signal SLbi goes to the high level during the pause period and when pixel circuits20in the i-th row are measurement targets, and goes to the low level otherwise.

Since the output signal SLbi goes to the high level during the pause period and when pixel circuits20in the i-th row are measurement targets, the transistor54goes to the off state and the transistor55goes to the on state. At this time, the second low-level power supply voltage ELVSS_moni is applied through the transistor55to the power supply line PLi. At other times, the output signal SLbi goes to the low level and thus the transistor54goes to the on state and the transistor55goes to the off state. At this time, the first low-level power supply voltage ELVSS is applied through the transistor54to the power supply line PLi.

The effects of the display device10according to the present embodiment will be described below. As described above, the display device according to the comparative example (the display device that drives the scanning lines at timing shown inFIG. 18) has problems that the configuration of the scanning line drive circuit becomes complex, luminance nonuniformity on a display screen cannot be sufficiently suppressed, and peak power consumption is high.

On the other hand, the display device10according to the present embodiment classifies frame periods as the drive period and the pause period, and measures drive currents during the pause period. The scanning line drive circuit of the display device10applies the selection voltage to the scanning lines SL1to SLm in turn during the drive period, and applies the selection voltage to one scanning line SLi corresponding to measurement target pixel circuits during the pause period (seeFIGS. 4 and 5). Such a scanning line drive circuit can be easily formed using the first scanning line drive circuit13and the second scanning line drive circuit14(seeFIG. 10). Therefore, according to the display device10, the configuration of the scanning line drive circuit can be simplified compared to the display device according to the comparative example.

In addition, since the display device10performs measurement of drive currents during the pause period, the display device10can secure sufficient time for measurement of drive currents. In the longest case, measurement of drive currents may be performed over one frame period. The longer the drive current measurement time, the more accurately the drive currents can be measured. Thus, the characteristics (threshold voltage and mobility) of the TFTs21can be more effectively compensated for. Accordingly, the display device can effectively compensate for variations in the characteristics of the TFTs21and thus can effectively suppress luminance nonuniformity on a display screen, compared to the display device according to the comparative example.

In addition, the display device10performs a write of voltages and a measurement of drive currents during different frame periods. Therefore, the display device10can reduce peak power consumption compared to the display device according to the comparative example.

As described above, the display device10according to the present embodiment includes the (m×n) pixel circuits20; the drive circuit (the first scanning line drive circuit13, the second scanning line drive circuit14, and the data line drive/current measurement circuit15) that writes voltages to the pixel circuits20; the measurement circuit (the data line drive/current measurement circuit15) that measures drive currents outputted from the pixel circuits20; and the correction circuit (the correction calculation circuit18) that corrects a video signal based on the drive currents measured by the measurement circuit. The drive circuit classifies frame periods as a drive period and a pause period, and applies a selection voltage to the scanning lines SL1to SLm in turn and applies voltages (data voltages, first measurement voltages, or second measurement voltages) to be written to the pixel circuits20to the data lines DL1to DLn in turn during the drive period, and applies the selection voltage to one scanning line SLi corresponding to measurement target pixel circuits20during the pause period. The measurement circuit measures drive currents outputted from the measurement target pixel circuits20, during the pause period. Therefore, the display device10can, as described above, simplify the configuration of the scanning line drive circuit, effectively suppress luminance nonuniformity on a display screen, and reduce peak power consumption.

In addition, the drive circuit applies voltages according to a corrected video signal D2to the data lines DL1to DLn during a selection period of a scanning line corresponding to pixel circuits20which are not measurement targets, in the drive period, and applies first or second measurement voltages to the data lines DL1to DLn during a selection period of the scanning line SLi corresponding to the measurement target pixel circuits20, in the drive period. By thus writing the measurement voltage to the measurement target pixel circuits during the drive period, drive currents outputted from the pixel circuits to which the measurement voltage has been written can be measured during the subsequent pause period.

In addition, the drive circuit classifies four frame periods as a first drive period, a first pause period, a second drive period, and a second pause period in this order, and applies a first measurement voltage to a data line DLj during a selection period of a scanning line SLi corresponding to measurement target pixel circuits20in the first drive period, and applies a second measurement voltage to the data line DLj during a selection period of the scanning line SLi corresponding to the measurement target pixel circuits20in the second drive period. The measurement circuit measures drive currents outputted from the measurement target pixel circuits20as a first drive current during the first pause period, and measures drive currents outputted form the measurement target pixel circuits20as a second drive current during the second pause period. The correction circuit corrects a portion of a video signal D1corresponding to the measurement target pixel circuits20, based on the first and second drive currents. By thus performing each of a write of a measurement voltage and a measurement of a drive current twice on a measurement target pixel circuit during four frame periods, and correcting a video signal based on two measurement results, variations in two types of characteristics (threshold voltage and mobility) of a drive transistor can be compensated for, enabling to effectively suppress luminance nonuniformity on a display screen.

In addition, the drive circuit applies the selection voltage to one scanning line SLi corresponding to measurement target pixel circuits20during one pause period. By this, during one pause period, variations in the characteristics of drive transistors in a plurality of pixel circuits connected to one scanning line can be compensated for.

In addition, the display device10includes a storage unit (the correction data storage unit19) that stores, for each pixel circuit20, pieces of first and second correction data (threshold voltage correction data and mobility correction data) which are used to correct the video signal. The correction circuit corrects first correction data for the measurement target pixel circuits20based on the first drive current, updates second correction data for the measurement target pixel circuits20based on the second drive current, and corrects a portion of a video signal D1corresponding to the measurement target pixel circuits20based on the first and second correction data. By thus storing, for each pixel circuit, two pieces of correction data, updating the two pieces of correction data based on two measurement results, and correcting a video signal based on the two pieces of correction data, variations in two types of characteristics of the drive transistor can be compensated for, enabling to effectively suppress luminance nonuniformity on a display screen.

In addition, the drive circuit includes the first scanning line drive circuit13that drives the scanning lines SL1to SLm during the drive period; and the second scanning line drive circuit14that drives the scanning lines SL1to SLm during the pause period. By thus dividing the circuit into a circuit that operates during the drive period and a circuit that operates during the pause period, the scanning line drive circuit can be easily formed.

In addition, the drive circuit and the measurement circuit share a drive/measurement circuit (the operational amplifier32, the capacitor33, and the switch34) provided corresponding to the data line DLj. By using the drive/measurement circuits, the drive circuit that writes voltages to the pixel circuits and the measurement circuit that measures drive currents outputted to the data lines from the pixel circuits can be easily formed.

Second Embodiment

A display device according to a second embodiment of the present invention has the same configuration as the display device10according to the first embodiment (seeFIG. 1). The display device according to the first embodiment measures a first drive current during a first pause period F2, and measures a second drive current during a second pause period F4. On the other hand, the display device according to the present embodiment measures the first drive current and the second drive current during one pause period. Differences from the first embodiment will be described below.

The display device according to the present embodiment writes display data voltages to all pixel circuits20during a drive period. More specifically, during the drive period, a second scanning line drive circuit14stops its operation. A first scanning line drive circuit13selects scanning lines SL1to SLm in turn for one line period, and applies a selection voltage to the selected scanning line (seeFIG. 4). A data line drive/current measurement circuit15applies n data voltages based on a corrected video signal D2, to data lines DL1to DLn, respectively.

FIG. 14is a timing chart of a pause period of the display device according to the present embodiment. As shown inFIG. 14, a drive circuit of the display device according to the present embodiment sets, in one pause period, a first write period T1, a first measurement period T2, a second write period T3, a second measurement period T4, and a third write period T5in this order. When pixel circuits20in an i-th row are measurement targets, the second scanning line drive circuit14applies the selection voltage to a scanning line SLi during the periods T1to T5. Note that in each of the pixel circuits20in the i-th row, a current Ioled flowing through an organic EL element25is zero during the periods T1to T5.

Voltage write operation and current measurement operation for a pixel circuit PX(i,j) will be described below. During the first to third write periods T1, T3, and T5, an input/output control signal DWT goes to a high level, and the data line drive/current measurement circuit15functions as a data line drive circuit. During the first and second measurement periods T2and T4, the input/output control signal DWT goes to a low level, and the data line drive/current measurement circuit15functions as a current measurement circuit.

During the first write period T1, the data line drive/current measurement circuit15applies a first measurement voltage Vm(i,j,P1) to a data line DLj. The first measurement voltage Vm(i,j,P1) is written to the pixel circuit PX(i,j). During the first measurement period T2, the data line drive/current measurement circuit15measures a first drive current Im(i,j,P1) outputted to the data line DLj from the pixel circuit PX(i,j). A CPU46updates threshold voltage correction data Vt(i,j) stored in a threshold voltage correction data storage unit47, based on a first drive current value Im(i,j,P1) obtained at this time.

During the second write period T3, the data line drive/current measurement circuit15applies a second measurement voltage Vm(i,j,P2) to the data line DLj. The second measurement voltage Vm(i,j,P2) is written to the pixel circuit PX(i,j). During the second measurement period T4, the data line drive/current measurement circuit15measures a second drive current Im(i,j,P2) outputted to the data line DLj from the pixel circuit PX(i,j). The CPU46updates mobility correction data B(i,j) stored in a mobility correction data storage unit48, based on a second drive current value Im(i,j,P2) obtained at this time.

During the third write period T5, the data line drive/current measurement circuit15applies a data voltage Vm(i,j,P) to the data line DLj. The data voltage Vm(i,j,P) is written to the pixel circuit PX(i,j). Note that the data voltage Vm(i,j,P) applied during the third write period T5is a voltage based on the corrected video signal D2which is obtained by updating the two types of correction data stored in a correction data storage unit19, based on the first drive current value Im(i,j,P1) and the second drive current value Im(i,j,P2), and referring to the updated correction data.

As in the first embodiment, the display device according to the present embodiment classifies frame periods as a drive period and a pause period, and measures drive currents during the pause period. Therefore, as in the first embodiment, the display device according to the present embodiment can simplify the configuration of the scanning line drive circuit, effectively suppress luminance nonuniformity on a display screen, and reduce peak power consumption.

In addition, in the display device according to the present embodiment, the drive circuit applies voltages according to the corrected video signal D2to the data lines DL1to DLn during a selection period of each scanning line in the drive period, sets a write period and a measurement period in the pause period, and applies the first or second measurement voltages to the data lines DL1to DLn during the write period. The measurement circuit measures drive currents outputted from measurement target pixel circuits20during the measurement period. By thus writing the measurement voltage to the measurement target pixel circuits during the write period in the pause period, drive currents outputted from the pixel circuits to which the measurement voltage has been written can be measured during the subsequent measurement period.

In addition, the drive circuit sets, in the pause period, a first write period, a first measurement period, a second write period, and a second pause period in this order, applies a first measurement voltage to a data line DLj during the first write period, and applies a second measurement voltage to the data line DLj during the second write period. The measurement circuit measures drive currents outputted from the measurement target pixel circuits20as a first drive current during the first measurement period, and measures drive currents outputted from the measurement target pixel circuits20as a second drive current during the second measurement period. A correction circuit corrects a portion of a video signal D1corresponding to the measurement target pixel circuits20, based on the first and second drive currents. By thus performing each of a write of a measurement voltage and a measurement of a drive current twice on the measurement target pixel circuit during one frame period, and correcting the video signal based on two measurement results, variations in two types of characteristics (threshold voltage and mobility) of the drive transistor can be compensated for, enabling to effectively suppress luminance nonuniformity on a display screen.

In addition, the drive circuit sets a third write period after the second measurement period in the pause period, and applies voltages according to the corrected video signal D2to the data lines DL1to DLn during the third write period. By thus writing, during the third write period, voltages according to the video signal which is corrected based on measurement results obtained during the first and second measurement periods, to the measurement target pixel circuits, results of compensating for variations in the characteristics of a drive transistor can be immediately reflected in a display image.

Third Embodiment

A display device according to a third embodiment of the present invention has the same configuration as the display device10according to the first embodiment (seeFIG. 1). The display device according to the first embodiment alternately switches between a drive period and a pause period. On the other hand, the display device according to the present embodiment treats a series of pause periods as a consecutive pause period, and alternately switches between the drive period and the consecutive pause period. Differences from the first and second embodiments will be described below.

FIG. 15is a diagram showing the operation of the display device according to the present embodiment performed during drive periods and consecutive pause periods. As shown inFIG. 15, a drive circuit of the display device according to the present embodiment classifies a plurality of frame periods as a first drive period F1, a first consecutive pause period FS2, a second drive period F3, a second consecutive pause period FS4, and a third drive period F5in this order. Each of the first and second consecutive pause periods FS2and FS4consists of N pause periods (N is an integer greater than or equal to 2). The display device according to the present embodiment performs the same operation on all pixel circuits20during the periods F1, FS2, F3, FS4, and F5.

During the first drive period F1, the display device according to the present embodiment writes a display data voltage to a pixel circuit PX(i,j). During the first consecutive pause period FS2, the display device according to the present embodiment writes a first measurement voltage Vm(i,j,P1) to the pixel circuit PX(i,j), and measures a first drive current Im(i,j,P1) outputted from the pixel circuit PX(i,j). During the second drive period F3, the display device according to the present embodiment writes a display data voltage to the pixel circuit PX(i,j). During the second consecutive pause period FS4, the display device according to the present embodiment writes a second measurement voltage Vm(i,j,P2) to the pixel circuit PX(i,j), and measures a second drive current Im(i,j,P2) outputted from the pixel circuit PX(i,j). During the third drive period F5, the display device according to the present embodiment writes a display data voltage to the pixel circuit PX(i,j).

As in the second embodiment, the display device according to the present embodiment writes display data voltages to all of the pixel circuits20during the drive period.FIG. 16is a timing chart of the consecutive pause period of the display device according to the present embodiment. As shown inFIG. 16, a drive circuit of the display device according to the present embodiment sets m selection periods in one consecutive pause period, and sets a write period Tw and a measurement period Tm in each selection period. A second scanning line drive circuit14applies a selection voltage to a scanning line SLi during an i-th selection period in the consecutive pause period.

Voltage write operation and current measurement operation for the pixel circuit PX(i,j) will be described below. During the first to third drive periods F1, F3, and F5and each write period Tw in the first and second consecutive pause periods FS2and FS4, an input/output control signal DWT goes to a high level, and a data line drive/current measurement circuit15functions as a data line drive circuit. During each measurement period Tm in the first and second consecutive pause periods FS2and FS4, the input/output control signal DWT goes to a low level, and the data line drive/current measurement circuit15functions as a current measurement circuit.

During a selection period of a scanning line SLi in the first drive period F1, the data line drive/current measurement circuit15applies a display data voltage Vm(i,j,P) to a data line DLj. The data voltage Vm(i,j,P) is written to the pixel circuit PX(i,j).

During a write period Tw in a selection period of the scanning line SLi in the first consecutive pause period FS2, the data line drive/current measurement circuit15applies the first measurement voltage Vm(i,j,P1) to the data line DLj. The first measurement voltage Vm(i,j,P1) is written to the pixel circuit PX(i,j). During a measurement period Tm immediately thereafter, the data line drive/current measurement circuit15measures the first drive current Im(i,j,P1) outputted to the data line DLj from the pixel circuit PX(i,j). A CPU46updates threshold voltage correction data Vt(i,j) stored in a threshold voltage correction data storage unit47, based on the first drive current value Im(i,j,P1) obtained at this time.

During a selection period of the scanning line SLi in the second drive period F3, the data line drive/current measurement circuit15applies a display data voltage Vm(i,j,P) to the data line DLj. The data voltage Vm(i,j,P) is written to the pixel circuit PX(i,j).

During a write period Tw in a selection period of the scanning line SLi in the second consecutive pause period FS4, the data line drive/current measurement circuit15applies the second measurement voltage Vm(i,j,P2) to the data line DLj. The second measurement voltage Vm(i,j,P2) is written to the pixel circuit PX(i,j). During a measurement period Tm immediately thereafter, the data line drive/current measurement circuit15measures the second drive current Im(i,j,P2) outputted to the data line DLj from the pixel circuit PX(i,j). The CPU46updates mobility correction data B(i,j) stored in a mobility correction data storage unit48, based on the second drive current value Im(i,j,P2) obtained at this time.

During a selection period of the scanning line SLi in the third drive period F5, the data line drive/current measurement circuit15applies the display data voltage Vm(i,j,P) to the data line DLj. The data voltage Vm(i,j,P) is written to the pixel circuit PX(i,j). Note that the data voltage Vm(i,j,P) applied during the third drive period F5is a voltage based on the corrected video signal D2which is obtained by updating the two types of correction data stored in a correction data storage unit19, based on the first drive current value Im(i,j,P1) and the second drive current value Im(i,j,P2), and referring to the updated correction data.

As in the first and second embodiments, the display device according to the present embodiment classifies frame periods as a drive period and a pause period, and measures drive currents during the pause period. Therefore, as in the first and second embodiments, the display device according to the present embodiment can simplify the configuration of the scanning line drive circuit, effectively suppress luminance nonuniformity on a display screen, and reduce peak power consumption.

In addition, in the display device according to the present embodiment, the drive circuit applies voltages according to the corrected video signal D2to data lines DL1to DLn during a selection period of each scanning line in the drive period, and during a consecutive pause period, applies a selection voltage to scanning lines SL1to SLm in turn, sets a write period and a measurement period in a selection period of each scanning line, and applies the first or second measurement voltage to the data line DLj during each write period. The measurement circuit measures drive currents outputted from the measurement target pixel circuits20during each measurement period. By thus writing a measurement voltage to the measurement target pixel circuits during each write period in the consecutive pause period, drive currents outputted from the pixel circuits to which the measurement voltage has been written can be measured during the subsequent measurement period.

In addition, the drive circuit applies the selection voltage to all of the scanning lines SL1to SLm in turn during one consecutive pause period. By this, during one consecutive pause period, variations in the characteristics of drive transistors in all pixel circuits can be compensated for.

In addition, the drive circuit applies the first measurement voltage to the data line DLj during each write period in the first consecutive pause period, and applies the second measurement voltage to the data line DLj during each write period in the second consecutive pause period. The measurement circuit measures drive currents outputted from the measurement target pixel circuits20as a first drive current during each measurement period in the first consecutive pause period, and measures drive currents outputted from the measurement target pixel circuits20as a second drive current during each measurement period in the second consecutive pause period. A correction circuit corrects a portion of the video signal D1corresponding to the measurement target pixel circuits, based on the first and second drive currents. By thus performing each of a write of a measurement voltage and a measurement of drive current twice on all pixel circuits during two consecutive pause periods, and correcting the video signal based on two measurement results, variations in two types of characteristics (threshold voltage and mobility) of the drive transistors can be compensated for, enabling to effectively suppress luminance nonuniformity on a display screen.

Note that concerning the display devices according to the embodiments of the present invention, the following variants can be formed. Although the pixel circuit20shown inFIG. 2includes N-channel TFTs21to23, the pixel circuit20may include P-channel TFTs. In the case of forming the pixel circuit20using P-channel TFTs, polarities of voltages provided to the pixel circuit20and polarities of voltages in the pixel circuit20are reversed. In addition, although the data line drive/current measurement circuit15shown inFIG. 2includes the capacitor33between the inverting input terminal and output terminal of the operational amplifier32and in parallel to the switch34, the data line drive/current measurement circuit15may include a resistor35in place of the capacitor33(seeFIG. 17). When the switch34is in an off state, the operational amplifier32and the resistor35function as an integrating circuit. As such, either one of a capacitive element and a resistive element may be provided as a passive element between the inverting input terminal and output terminal of the operational amplifier.

In addition, in the display devices according to the first and second embodiments, during one pause period, the drive circuit may apply, in turn, a selection voltage to a plurality of scanning lines corresponding to measurement target pixel circuits. By this, during one pause period, variations in the characteristics of drive transistors in a plurality of pixel circuits connected to a plurality of scanning lines can be compensated for. In addition, in the display device according to the third embodiment, the drive circuit may apply the selection voltage to some of the scanning lines SL1to SLm in turn during one consecutive pause period.

In addition, the classifications of frame periods shown inFIGS. 3 and 15are examples of a classification method, and the setting of write periods and measurement periods in a pause period which is shown inFIG. 14is an example of a setting method. The drive circuit of the display device according to the first embodiment may classify frame periods as a drive period and a pause period in other manners than that shown inFIG. 3. The drive circuit of the display device according to the second embodiment may set write periods and measurement periods in a pause period in other manners than that shown inFIG. 14. The drive circuit of the display device according to the third embodiment may classify frame periods as a drive period and a consecutive pause period in other manners than that shown inFIG. 15.

INDUSTRIAL APPLICABILITY

Display devices and methods for driving the display devices of the present invention are characterized by having a scanning line drive circuit with a simple configuration, being capable of effectively suppressing luminance nonuniformity, and having low power consumption, and thus can be used, for example, for display devices having current-driven type light-emitting elements such as organic EL elements.

DESCRIPTION OF REFERENCE CHARACTERS

10: DISPLAY DEVICE11: DISPLAY UNIT12: DISPLAY CONTROL CIRCUIT13: FIRST SCANNING LINE DRIVE CIRCUIT14: SECOND SCANNING LINE DRIVE CIRCUIT15: DATA LINE DRIVE/CURRENT MEASUREMENT CIRCUIT16: POWER SUPPLY VOLTAGE SELECTION CIRCUIT17: A/D CONVERTER18: CORRECTION CALCULATION CIRCUIT19: CORRECTION DATA STORAGE UNIT20: PIXEL CIRCUIT21,22, and23: TFT24and33: CAPACITOR25: ORGANIC EL ELEMENT31: D/A CONVERTER32: OPERATIONAL AMPLIFIER34: SWITCH35: RESISTOR47: THRESHOLD VOLTAGE CORRECTION DATA STORAGE UNIT48: MOBILITY CORRECTION DATA STORAGE UNIT