Methods of forming redistribution lines and methods of manufacturing semiconductor devices using the same

A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a top surface, on which has been formed a color filter and a micro-lens, and a bottom surface opposite to the top surface, forming a redistribution line on the bottom surface of the semiconductor substrate, and forming on the bottom surface of the semiconductor substrate a passivation layer covering the redistribution line. After the redistribution line and passivation layer are formed, an oxide layer between the redistribution line and the passivation is formed at a temperature that avoids thermal damage to the color filter and the micro-lens.

PRIORITY STATEMENT

This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2017-0166859 filed on Dec. 6, 2017, in the Korean Intellectual Property Office, the contents of which are hereby incorporated by reference in their entirety.

BACKGROUND

The present inventive concept relates to devices employing semiconductors such as images sensors including photodiodes. In particular, the inventive concept relates to a method of forming redistribution lines in the manufacturing of semiconductor devices.

Redistribution lines of a semiconductor device are conductive lines that distribute various signals throughout the device. The redistribution lines are prone to such problems as oxidation and electrochemical migration of constituent elements that make up the lines, which in turn decreases the reliability of the devices in which they are incorporated.

SUMMARY

According to the present inventive concepts there is provided a method of manufacturing a semiconductor device including providing a base structure including a semiconductor substrate having a top surface and a bottom surface opposite to the top surface, and a color filter and a micro-lens on the top surface of the semiconductor substrate, forming a redistribution line on the bottom surface of the semiconductor substrate, forming a passivation layer covering the redistribution line on the bottom surface of the semiconductor substrate, and spontaneously forming an oxide layer on the redistribution line, and growing the oxide layer between the redistribution line and the passivation layer at a temperature regime specified to avoid thermal damage to the color filter and the micro-lens.

According to the present inventive concept, there is also provided a method of manufacturing a semiconductor device including providing a base structure including semiconductor substrate having an active surface and an inactive surface opposite to the active surface, and a color filter and a micro-lens on the active surface, forming a redistribution metal layer on the inactive surface of the semiconductor substrate, forming on the inactive surface of the semiconductor substrate an organic insulation layer covering the redistribution metal layer; and growing a metal oxide layer to a predetermined thickness between the redistribution metal layer and the organic insulation layer. The metal oxide layer is grown to the predetermined thickness during processing carried out subsequent to the forming of the organic insulation layer within a temperature regime specified to avoid thermal damage to the color filter and the micro-lens.

According to the present inventive concept, there is also provided a method of forming a redistribution line that includes providing a base structure including a semiconductor substrate having an active surface and an inactive surface, and a through electrode that does not reach the inactive surface, recessing the inactive surface of the semiconductor substrate to expose the through electrode, subsequently forming the redistribution line on the inactive surface of the semiconductor substrate, the redistribution line electrically connected to the through electrode, forming an organic passivation layer covering the redistribution line, and growing, at a temperature equal to or less than 250° C., a native metal oxide layer between the redistribution line and the organic passivation layer to a thickness in a range of from 50 nm to 200 nm.

According to the present inventive concept, there is also provided manufacturing a semiconductor device that includes providing a base structure including a semiconductor substrate having top and bottom surfaces facing in opposite directions, a via exposed at the bottom surface, and a color filter and a micro-lens on the top surface of the semiconductor substrate, forming a metallic redistribution line extending along the bottom surface of the semiconductor substrate and onto the via, forming a passivation layer covering the metallic redistribution line, and subsequently completing the manufacturing of the semiconductor device by carrying out processes within a temperature regime whose maximum temperature is less than a temperature rating of each of the color filter and the micro-lens, and in which an oxide layer is grown between the metallic redistribution line and the passivation layer under said temperature regime and has a thickness in a range of from 50 nm to 200 nm when said processes have been completed.

DETAILED DESCRIPTION

Methods of forming a redistribution line and methods of manufacturing semiconductor devices including the same according to inventive concept will be hereinafter described in conjunction with the accompanying drawings.

FIG. 1Aillustrates an example of a semiconductor device manufactured according to the inventive concept.

Referring toFIG. 1A, the semiconductor device10may include a semiconductor substrate100with a top surface100aand a bottom surface100cfacing each other, a plurality of photodiodes720provided in the semiconductor substrate100and separated from each other by device isolation layers710, a metal line structure740provided on the top surface100aof the semiconductor substrate100, a plurality of color filters760provided on the metal line structure740, and a plurality of micro-lenses770corresponding to the color filters760. The top surface100amay be an active surface of the semiconductor substrate100, and the bottom surface100cmay be an inactive surface of the semiconductor substrate100.

The metal line structure740may include a plurality of stacked dielectric layers746, a plurality of vias742electrically connected to a plurality of storage nodes730provided in the semiconductor substrate100, and a plurality of metal lines744. The metal line structure740may be covered with an upper insulation layer750having a single-layered or multi-layered structure.

The semiconductor device10may further include a through electrode200that extends through the semiconductor substrate100to come into electrical connection with the metal line structure740, a redistribution line430provided on the bottom surface100cof the semiconductor substrate100and electrically connected to the through electrode200, and a passivation layer500covering the redistribution line430.

The through electrode200may be coupled to a metal line744of the metal line structure740. The through electrode200may be electrically insulated through a via insulation layer220from the semiconductor substrate100. A barrier layer210may further be included between the though electrode200and the via insulation layer220, preventing a component of constituent element, e.g., copper and referred to hereinafter simply as “constituent” of the through electrode200from diffusing into the semiconductor substrate100.

A first lower insulation layer310and a second lower insulation layer320may be sequentially stacked on the bottom surface100cof the semiconductor substrate100. The first lower insulation layer310and the second lower insulation layer320may be of different insulating materials from each other. For example, the first lower insulation layer310may be a layer of silicon oxide, and the second lower insulation layer320may be a layer silicon nitride.

The redistribution line430may be provided on the second lower insulation layer320and electrically connected to the through electrode200. The redistribution line430may include a metal, such as copper. The redistribution line430and the second lower insulation layer320may be provided therebetween with a barrier layer410coupled to the through electrode200and with a seed layer420on the barrier layer410. Alternatively, only one lower insulation layer, i.e., only a mono-layer of an insulating material, may be interposed between the bottom surface100cof the semiconductor substrate100and the redistribution line430.

In either case, the redistribution line430may have a thickness equal to or less than about 15 μm, and preferably from about 10 μm to about 15 μm. Here, and in the description that follows the term “about” is used to refer to minute differences from the design specifications (the enumerated values) as a result of normal tolerances and variations associated with the manufacturing process. Therefore, the ranges given may include the enumerated values.

The passivation layer500may be provided on the bottom surface100cof the semiconductor substrate100as covering the redistribution line430. The passivation layer500may comprise (be or include) an inorganic insulation layer or an organic insulation layer. For example, the passivation layer500may comprise (be or include) an organic insulation layer, such as polybenzoxazole (PBO). The passivation layer500may have a thickness of about 3 μm to about 5 μm.

The redistribution line430may be covered with an oxide layer440. The oxide layer440may be or include a spontaneous oxide layer (or a native metal oxide layer) that automatically grows when oxygen in the passivation layer500and a constituent (e.g., copper) of the redistribution line430are reacted with each other in a subsequent process after the passivation layer500is formed. A spontaneous oxide layer will refer to any oxide layer that is (first) formed without any process, e.g., a thermal oxidation or anneal process, dedicated to that end. Spontaneous oxides may form on a solid as a result of the solid being exposed to air (at room temperature) or as a result of the solid coming into contact with another solid containing oxygen.

In an example of the inventive concept, the oxide layer440may be grown for several to tens of hours (e.g., less than about 10 hours) at a low temperature regime (e.g., temperatures equal to or less than about 250° C.) that avoids thermal damage to the color filters760and/or the micro-lenses770. In particular, the color filters760and the micro-lenses770have temperature ratings which are the maximum temperatures that these elements can withstand for a long duration without degrading. The temperatures ratings can therefore be a known quantity or specification based on the specific type of material, e.g., the polymer, from which the color filters760and micro-lenses770are made. The oxide layer440may automatically grow at the low temperature and/or for the short process time, and accordingly has a thickness T of about 50 nm to about 200 nm, and preferably about 100 nm.

An outer terminal630may be electrically connected to the redistribution line430. A barrier layer610and a seed layer620may be provided between the outer terminal630and the redistribution line430, and a capping layer640may be provided on the outer terminal630. The outer terminal630may be in the form of a bump shape. Alternatively, the outer terminal630may be a solder ball.

According to some examples of inventive concept, the oxide layer440serves as a barrier that prevents migration of a constituent (e.g., copper) of the redistribution line430. If the thickness T of the oxide layer440were less than about 50 nm, a constituent (e.g., copper) of the redistribution line430easily migrates. If the thickness T of the oxide layer440were greater than about 200 nm, the oxide layer440would tend to crack and such a cracked oxide layer440could not serve effectively as a barrier against the migration of a constituent (e.g., copper) of the redistribution line430. Either of these problems could cause an electrical failure of the redistribution line430or the semiconductor device10.

As discussed above, however, according to the inventive concept, the oxide layer440is grown at a relatively low temperature and/or for a relatively short time, thereby allowing it to achieve a thickness T of about 50 nm to about 200 nm, and preferably about 100 nm. As a result, the oxide layer440may be substantially free of copper or cracks that could otherwise cause an electrical failure of the semiconductor device10.

FIG. 1Billustrates an example of a semiconductor package including the semiconductor device ofFIG. 1A.

Referring toFIG. 1B, the semiconductor device10and an electrical device20may be electrically connected to constitute a semiconductor package1. For example, a solder ball30may be formed between the outer terminal630of the semiconductor device10and an outer terminal23of the electrical device20, and an epoxy molding compound (EMC) may be provided and cured to form a mold layer40. The electrical device20may be or include a memory chip, a logic chip, or a combination thereof. Alternatively, the electrical device20may be or include a printed circuit board (PCB). A reflow process for forming the solder ball30and a cure process for forming the mold layer40may be performed at a temperature ranging from about room temperature (e.g., about 25° C.) to equal to or less than about 250° C.

The semiconductor device10may be provided as part of a wafer level process that includes a sawing process. More specifically, a plurality of chip-level electrical devices20may be provided on a wafer on which a plurality of the semiconductor devices10have been formed, the mold layer40may be formed, and then a sawing process may be performed which separates such a structure into individual ones of the semiconductor packages1. As another example, a wafer on which a plurality of the electrical devices20have been formed may be provided on another wafer on which a plurality of the semiconductor devices10have been formed, the mold layer40is then formed, and then a sawing process may be performed to separate that wafer-on-wafer structure into a plurality of individual semiconductor packages1.

The oxide layer440of the semiconductor device10may be subjected to heat produced in one or more thermal processes, e.g., a reflow process and a cure process, that are required to fabricate the semiconductor package1, thereby continuing to grow. The thermal processes may be performed at a temperature regime of temperatures within a range from about room temperature to equal to or less than about 250° C., and in addition, about several to tens of hours (e.g., less than about 10 hours) may be required from an initial stage of forming the oxide layer440to a final stage of fabricating the semiconductor package1. In this way, the oxide layer440may assume a thickness T of about 50 nm to about 200 nm, or more specifically about 100 nm, as discussed above with reference toFIG. 1A.

FIGS. 2A to 2Millustrate a method of manufacturing a semiconductor device, according to the inventive concept.

Referring toFIG. 2A, a semiconductor substrate100as part of a base structure may be provided to have a first surface100aand a second surface100bfacing in opposite directions. The semiconductor substrate100may be or include a semiconductor wafer (e.g., silicon wafer) including a variety of components constituting an image sensor. For example, the semiconductor substrate100may include a device isolation layer710, photodiodes720, and a plurality of storage nodes730. The base structure may also include a metal line structure740, a plurality of color filters760, and a plurality of micro-lenses770on the substrate100. The color filters760and the micro-lenses770may be formed of a polymer.

The metal line structure740may be formed on the first surface100aof the semiconductor substrate100. The forming of the metal line structure740may include deposition of an insulating material, such as silicon oxide, and deposition and patterning of a metallic material, such as copper, aluminum, or tungsten. A polymer may be deposited and patterned to form the color filters760and the micro-lenses770on the metal line structure740. The other components may be similar to those described above with reference toFIG. 1A.

A through electrode or via200may be formed in a blind opening in the semiconductor substrate100. The through electrode200may thus extend into the semiconductor substrate100but without reaching the second surface100bof the semiconductor substrate100. A barrier layer210and a via insulation layer220may be formed before the through electrode200is formed so as to cover side and bottom surfaces of the through electrode200. The through electrode200may be formed by a plating or deposition process in which a conductive material, such as copper, tungsten, or polysilicon is formed on the barrier layer210. The barrier layer210may be formed by depositing titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or the like on the insulating layer220. The via insulation layer220may be formed by depositing silicon oxide, silicon nitride, or the like in the blind opening in the semiconductor substrate100.

Referring toFIG. 2B, the second surface100bof the semiconductor substrate100may be recessed below the end of the through electrode200. For example, a carrier90may be adhered to the first surface100aof the semiconductor substrate100, and the semiconductor substrate100may be turned upside down. The carrier90may include a semiconductor wafer. An adhesive may be used to adhere the carrier90to the semiconductor substrate100.

The recessing of the second surface100bmay entail grinding, etching, or a combination thereof. The recessing may form a third surface100c, and cause the through electrode200to protrude beyond the third surface100c. In this description, the first surface100amay be referred to as a top surface, and the third surface100cmay be referred to as a bottom surface. Unless otherwise stated, the top surface100amay denote an active surface of the semiconductor substrate100, and the bottom surface100cmay denote an inactive surface of the semiconductor substrate100.

Referring toFIG. 2C, the bottom surface100cof the semiconductor substrate100may be sequentially covered with a first lower insulation layer310covering the through electrode200and a second lower insulation layer320covering the first lower insulation layer310. The first and second lower insulation layers310and320may be of different insulating materials from each other. For example, the first lower insulation layer310may be formed of silicon oxide, and the second lower insulation layer320may be formed of silicon nitride. In other examples, the second lower insulation layer320is not formed.

Referring toFIG. 2D, a planarization process, such as chemical mechanical polishing (CMP) or an etch-back process, may be performed to reveal the through electrode200, following which a mask pattern50or “mask” for short may be formed on the bottom surface100cof the semiconductor substrate100. The first and second lower insulation layers310and320may be planarized. The mask pattern50may have a groove55exposing the through electrode200. The mask pattern50may be formed of an organic material, such as photoresist, or an inorganic material, such as silicon oxide or silicon nitride.

Referring toFIG. 2E, a barrier layer410, a seed layer420, and a sacrificial layer60may be formed on the bottom surface100cof the semiconductor substrate100. The barrier layer410may be formed in the groove55and on the mask pattern50, and the seed layer420may be formed on the barrier layer410. The sacrificial layer60may fill the groove55. The barrier layer410may be formed of titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or the like. The seed layer420may be formed of copper (Cu), ruthenium (Ru), nickel (Ni), tungsten (W), or the like. The sacrificial layer60may be formed of an organic material, such as photoresist, or inorganic material, such as silicon oxide or silicon nitride.

Referring toFIG. 2F, the seed layer420may be partially removed. A wet etching process may be employed to partially remove the seed layer420. The wet etching process may allow the seed layer420to remain in the groove55. The seed layer420may then be confined in the groove55between the bottom of the sacrificial layer60and the barrier layer410. Alternatively, the seed layer420may extend along a side surface of the sacrificial layer60in the groove55from between the bottom of the sacrificial layer60and the barrier layer410.

Referring toFIG. 2G, the sacrificial layer60may be removed from the groove55, and a redistribution line430may be formed in the groove55. As the sacrificial layer60is removed, the seed layer420may be exposed in the groove55. The exposed seed layer420may be used to plate the redistribution line430in the groove55. The redistribution line430may be formed of metal, such as copper (Cu). At this time, an interface between the seed layer420and the redistribution line430may not be visually discernible, i.e., the seed layer420may be incorporated into the redistribution line430. However, for illustrative purposes, the seed layer420will continue to be shown in the figures. The redistribution line430has a thickness equal to or less than about 15 μm, and preferably from about 10 μm to about 15 μm.

Referring toFIG. 2H, the barrier layer410may be partially removed such that a remnant thereof is left in the groove55. A wet etching process may be employed to partially remove the barrier layer410. The barrier layer410may then be confined in the groove55between the seed layer420and the second lower insulation layer320. Alternatively, the barrier layer410may be confined in the groove55while extending along a side surface of the redistribution line430from between the seed layer420and the second lower insulation layer320.

Referring toFIG. 2I, the mask pattern50may be removed, and a passivation layer500may be formed. The passivation layer500may be an inorganic insulation layer, such as silicon oxide or silicon nitride layer, or an organic insulation layer, such as a polyimide (PI) or polybenzoxazole (PBO) layer. For example, polybenzoxazole (PBO) may be provided and cured to form the passivation layer500. The passivation layer500may have a thickness of about 3 μm to about 5 μm.

Referring toFIG. 2J, the passivation layer500may be patterned to form an opening550partially exposing the redistribution line430, and thereafter, a barrier layer610and a seed layer620may be sequentially formed on the passivation layer500. The barrier layer610may be in contact with the redistribution line430in the opening550. The barrier layer610may be formed of titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or the like. The seed layer620may be formed of copper (Cu), ruthenium (Ru), nickel (Ni), tungsten (W), or the like.

Referring toFIG. 2K, a mask pattern70exposing the opening550may be formed on the seed layer620. The mask pattern70may be formed of an organic material, such as photoresist, or an inorganic material, such as silicon oxide or silicon nitride.

Referring toFIG. 2L, an outer terminal630and a capping layer640may be formed in the opening550. The outer terminal630may be formed by a plating process using the seed layer620. The capping layer640may be formed by plating metal on the outer terminal630. The outer terminal630may be formed of nickel, tungsten, aluminum, copper, or the like. The capping layer640may be formed of gold, nickel, silver, or the like.

Referring toFIG. 2M, the mask pattern70may be removed. A removal process may be performed on the barrier layer610and the seed layer620that are exposed as a result of the removal of the mask pattern70. A wet etching process may be employed to remove the barrier layer610and the seed layer620. When the carrier90is removed, the semiconductor device10ofFIG. 1Amay be deemed as completed. As illustrated inFIG. 1B, the semiconductor device10may be electrically connected through the solder ball30to the electrical device20, and encapsulated by the mold layer40, which process may complete the fabricating of the semiconductor package1.

According to some examples of inventive concept, after the forming of the passivation layer500discussed above with reference toFIG. 2J, subsequent processes, for example, a deposition process, a plating process, a reflow process, and a cure process, may provide heat by which an oxide layer440may be formed between the redistribution line430and the passivation layer500. For example, during the subsequent processes, heat required for the subsequent processes (i.e., the thermal regime of the subsequent processes) may cause oxygen in the passivation layer500to react with a constituent (e.g., copper) of the redistribution line430. This reaction may form and grow a native metal oxide layer, or the oxide layer440. Note, therefore, although the oxide layer440is only shown inFIG. 2M(as grown to its full thickness), the oxide layer is formed prior to this stage but any beginning of the oxide layer is omitted in the figures, for example, in any ofFIGS. 2G-2L.

The subsequent processes may be performed at relatively low temperature regime within a range from room temperature (e.g., about 25° C.) to about 250° C., and which temperatures are selected to be below the temperature ratings of heat-vulnerable components such as the color filters760and/or the micro-lenses770formed of a polymer so to thermal damage to these components is avoided. The thickness T of the oxide layer440may depend not only on heat but also on process time. The semiconductor device10or the semiconductor package1is designed so that after the passivation layer500is formed, a process time of only several to tens of hours, and preferably less than about 10 hours, is required to complete its fabrication. Here, the time at which the fabrication is completed may coincide with the termination of the last process in which significant heat is generated, e.g., the last process in which temperature is part of the process recipe.

As discussed above with reference toFIG. 1A, the oxide layer400may serve as a barrier that prevents migration of a constituent (e.g., copper) of the redistribution line430. When the thickness T of the oxide layer440is less than about 50 nm or greater than about 200 nm, the oxide layer440will not act as a sufficient barrier electrochemical migration or tends to crack. According to the inventive concept, the low temperature condition and/or the short process time causes the oxide layer440to form to a thickness T ranging from about 50 nm to about 200 nm, and preferably about 100 nm. An oxide layer440having such a thickness T will not adversely affect electrical characteristics of the semiconductor device10and/or of the semiconductor package1.

Referring back toFIG. 1A, the redistribution line430may be surrounded by the barrier layer410and the oxide layer440. When viewed in cross-section, the barrier layer410may have a linear shape covering a top surface of the redistribution line430, and the oxide layer440may have a bracket shape covering bottom and side surfaces of the redistribution line430. The top surface of the redistribution line430may face the bottom surface100cof the semiconductor substrate100, and the bottom surface of the redistribution line430may be opposite to the top surface of the redistribution line430.

FIGS. 3A to 3Dillustrate another example of a method of manufacturing a semiconductor device, according to the inventive concept.

Referring toFIG. 3A, processes identical or similar to those discussed above with reference toFIGS. 2A to 2Emay be performed to form the barrier layer410and the seed layer420on the bottom surface100cof the semiconductor substrate100. Instead of the sacrificial layer60ofFIG. 2E, a metal layer430ais formed to fill the groove55. The metal layer430amay be formed by plating metal, such as copper.

Referring toFIG. 3B, the metal layer430amay be planarized by a planarization process, such as chemical mechanical polishing (CMP) or an etch-back process. The planarization process may form the redistribution line430in the groove55. The planarization process may continue until the mask pattern50is exposed.

Referring toFIG. 3C, processes identical or similar to those discussed above with reference toFIGS. 2I to 2Mmay be performed to form the passivation layer500covering the redistribution line430on the bottom surface100cof the semiconductor substrate100and to form the outer terminal630coupled to the redistribution line430.

Referring toFIG. 3D, when the carrier90is removed, a semiconductor device10amay be fabricated. Similar to the semiconductor device10ofFIG. 1A, the oxide layer440of the semiconductor device10ahas a thickness T ranging from about 50 nm to about 200 nm, and preferably about 100 nm. When viewed in cross-section, the oxide layer440may have a linear shape covering the bottom surface of the redistribution line430, and the barrier layer410may have a bracket shape covering the top and side surfaces of the redistribution line430.

According to inventive concepts, the oxide layer on the redistribution line can prevent migration of a constituent of the redistribution line, and have a thickness resistant to crack initiation and propagation. Accordingly, the present inventive concept can provide a highly reliable redistribution line and/or a semiconductor device including the redistribution line.

Finally, this detailed description of the inventive concept should not be construed as limited to the examples set forth herein. Rather, the inventive concept may be applied to various combinations, modifications and variations of the examples without departing from the spirit and scope of inventive concept as defined by the appended claims.