Image sensor

An image sensor includes a plurality of pixels, at least one of the pixels comprising: a photodiode configured to generate charges in response to light; and a pixel circuit disposed on the substrate, and including a storage transistor configured to store the charges generated by the photodiode, and a transfer transistor connected between the storage transistor and a floating diffusion node, wherein a potential of a boundary region between the storage transistor and the transfer transistor has a first potential when the transfer transistor is in a turned-off state, and has a second potential, lower than the first potential, when the transfer transistor is in a turned-on state.

CROSS-REFERENCE TO THE RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2019-0025715 filed on Mar. 6, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to an image sensor.

2. Description Of Related Art

An image sensor is a semiconductor-based sensor onto which light is irradiated to produce an electrical signal, which may include a pixel array having a plurality of pixels, a logic circuit for driving the pixel array and generating an image, and the like. The pixels may include a photodiode generating charges in response to light, and a pixel circuit outputting a pixel signal using the charges generated by the photodiode. The charges generated by the photodiode may be stored in a storage element of the pixel circuit. In a case in which the charges stored in the storage element are not smoothly transferred to a subsequent node, the performance of the image sensor may deteriorate.

SUMMARY

Exemplary embodiments of the inventive concept may provide an image sensor having improved performance while significantly reducing an increase in an area of a storage element by increasing transfer efficiency of charges from a storage element of a pixel circuit to a floating diffusion node.

According to an aspect of the embodiments, an image sensor may include a plurality of pixels, at least one of the pixels including: a photodiode configured to generate charges in response to light; and a pixel circuit disposed on the substrate, and including a storage transistor configured to store the charges generated by the photodiode, and a transfer transistor connected between the storage transistor and a floating diffusion node, wherein a potential of a boundary region between the storage transistor and the transfer transistor has a first potential when the transfer transistor is in a turned-off state, and has a second potential, lower than the first potential, when the transfer transistor is in a turned-on state.

According to another aspect of the embodiments, an image sensor may include a plurality of pixels, at least one of the pixels including: a photodiode configured to generate charges in response to light; and a pixel circuit including a storage transistor connected to the photodiode and a transfer transistor connected between the storage transistor and a floating diffusion node, wherein, in the pixel circuit, a potential is gradually decreased between the transfer transistor and the storage transistor in a direction away from the storage transistor when the transfer transistor is turned on.

According to still another aspect of the embodiments, an image sensor may include a plurality of pixels, at least one of the pixels including: a photodiode configured to generate charges in response to light; and a pixel circuit including a plurality of transistors configured to output pixel signals using the charges, wherein an active region of at least one of the transistors includes a first impurity region and a second impurity region having an impurity concentration lower than an impurity concentration of the first impurity region, and wherein the second impurity region and the first impurity region are sequentially disposed according to a transfer direction of the charges.

DETAILED DESCRIPTION

Hereinafter, various embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. These embodiments are all exemplary, and thus, the inventive concept is not limited thereto and may be realized in various other forms. An embodiment provided in the following description is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the inventive concept. For example, even if matters described in a specific example are not described in a different example thereto, the matters may be understood as being related to or combined with the different example, unless otherwise mentioned in descriptions thereof.

It will be understood that when an element is referred to as being “over,” “above,” “on,” “connected to” or “coupled to” another element, it can be directly over, above, on, connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly connected to” or “directly coupled to” another element, there are no intervening elements present. Like numerals refer to like elements throughout.

FIGS. 1A and 1Bare diagrams illustrating an image sensor according to an exemplary embodiment.

Referring first toFIG. 1A, an image sensor1according to an exemplary embodiment may include a first layer2, a second layer3provided below the first layer2, and a third layer4provided below the second layer3. The first layer2, the second layer3, and the third layer4may be stacked in directions perpendicular to each other. In an exemplary embodiment, the first layer2and the second layer3may be stacked on each other at a wafer level, and the third layer4may be attached to a lower portion of the second layer3at a chip level. The first to third layers2to4may be provided as a single semiconductor package.

The first layer2may include a sensing area SA on which a plurality of pixels PXs are provided and a first pad area PA1provided around the sensing area SA. The first pad area PA1may include a plurality of upper pads PADs which may be connected to lower pads provided on a second pad area PA2and a control logic circuit LC of the second layer3through vias or the like.

Each of the pixels PXs may include a photodiode receiving light to generate charges, and a pixel circuit that processes the charges generated by the photodiode. The pixel circuit may include a plurality of transistors for outputting a voltage corresponding to the charges generated by the photodiode.

The second layer3may include a plurality of elements that provide the control logic circuit LC. The elements included in the control logic circuit LC may provide circuits for driving the pixels provided on the first layer2, for example, a row driver, a column driver, and a timing controller. The elements included in the control logic circuit LC may be connected to the pixel circuit through the first and second pad areas PA1and PA2. The control logic circuit LC may obtain a reset voltage and a pixel voltage from the pixels PXs to generate a pixel signal.

In an exemplary embodiment, at least one of the pixels PXs may include a plurality of photodiodes disposed on the same level. The pixel signals generated from the charges of each of the photodiodes may have a phase difference from each other, and the control logic circuit LC may provide an autofocusing function based on the phase difference between the pixel signals generated from the photodiodes included in a single pixel PX.

The third layer4provided below the second layer3may include a memory chip MC, a dummy chip DC, and an encapsulating layer EN encapsulating the memory chip MC and the dummy chip DC. The memory chip MC may be a dynamic random access memory (DRAM) or a static random access memory (SRAM), and the dummy chip may not have a function of actually storing data. The memory chip MC may be electrically connected to at least some of the elements included in the control logic circuit LC of the second layer3through bumps, and may store information necessary to provide the autofocusing function. In an exemplary embodiment, the bumps may be microbumps.

Next, referring toFIG. 1B, an image sensor5according to an exemplary embodiment may include a first layer6and a second layer7. The first layer6may include a sensing area SA on which a plurality of pixels PXs are provided, a control logic circuit LC on which elements for driving the pixels PXs are provided, and a first pad area PA1provided around the control logic circuit LC. The first pad area PA1may include a plurality of upper pads PADs which may be connected to a memory chip MC provided on the second layer7through vias or the like. The second layer7may include a memory chip MC, a dummy chip DC, and an encapsulating layer EN encapsulating the memory chip MC and the dummy chip DC.

FIGS. 2 and 3are block diagrams illustrating an image sensor according to an exemplary embodiment.

Referring first toFIG. 2, an image sensor10may include a controller20, a pixel array30, and the like.

The pixel array30may include a plurality of pixels PXs arranged in the form of an array along a plurality of rows and a plurality of columns. Each of the pixels PX may include a photodiode generating charges in response to optical signals incident from the outside, and a pixel circuit generating an electrical signal corresponding to the charges generated by the photodiode. As an example, the pixel circuit may include a floating diffuser, a storage transistor, a transfer transistor, a reset transistor, a driving transistor, a selection transistor, and the like. The configuration of the pixels PXs may vary depending on exemplary embodiments. As an example, each of the pixels PXs may include an organic photodiode that includes an organic material, unlike a silicon photodiode, or may be implemented as a digital pixel. When the pixel PX is implemented as the digital pixel, each of the pixels PXs may include a comparator, a counter converting an output of the comparator into a digital signal and outputting the digital signal, and the like.

The controller20may include a plurality of circuits for controlling the pixel array30. As an example, the controller20may include a row driver21, a readout circuit22, a column driver23, a control logic circuit24, and the like. The row driver21may drive the pixel array30in units of rows. For example, the row driver21may generate a transfer control signal that controls the transfer transistor of the pixel circuit, a reset control signal that controls the reset transistor, a selection control signal that controls the selection transistor, and the like.

The readout circuit22may include a correlated doubled sampler (CDS), an analog-to-digital converter (ADC), and the like. The correlated double sampler may be connected to the pixels PXs included in a row selected by a row selection signal supplied by the row driver21through column lines, and may perform correlated double sampling to detect the reset voltage and the pixel voltage. The analog-to-digital converter may convert the reset voltage and the pixel voltage detected by the correlated double sampler into digital signals, and may transfer the digital signals to the column driver23.

The column driver23may include a latch or buffer circuit in which the digital signals may be temporarily stored, an amplification circuit, and the like, and process the digital signals received from the readout circuit22. The row driver21, the readout circuit22, and the column driver23may be controlled by the control logic circuit24. The control logic circuit24may include a timing controller for controlling operation timings of the row driver21, the readout circuit22, and the column driver23, an image signal processor for processing image data, and the like.

The control logic circuit24may perform signal processing for data output by the readout circuit22and the column driver23to generate image data. As an example, the image data may include a depth map. In addition, the control logic circuit24may generate the image data using the data output by the readout circuit22and the column driver23.

Next, referring toFIG. 3, an image sensor40according to an exemplary embodiment may include a pixel array70, and a controller for driving the pixel array70. The controller may include a row driver50, a readout circuit60, and the like. The readout circuit60may include a ramp voltage generator61, a sampling circuit62, an analog-to-digital converter63, and the like. Data output by the analog-to-digital converter63may be input to a column driver.

The pixel array70may include a plurality of pixels PX11to PXMNprovided at intersections of a plurality of row lines ROWs and a plurality of column lines COLs. The row driver50may input signals necessary to control the pixels PX11to PXMNthrough the row lines ROWs. As an example, the signals input to the pixels PX11to PXMNthrough the row lines ROWs may include a reset control signal RG, a transfer control signal TG, a selection control signal SEL, and the like. The row driver50may sequentially select each of the row lines ROWs. The row driver50may select one of the row lines ROWs during a predetermined horizontal period.

The sampling circuit62may obtain the reset voltage and the pixel voltage from some pixels connected to the row lines scanned by the row driver50, among the pixels PX11to PXMN. The sampling circuit62may include a plurality of samplers SAs, and the samplers SAs may be correlated double samplers. Each of the samplers SAs may receive a ramp voltage generated by the ramp voltage generator61through a first input terminal, and may also receive the reset voltage and the pixel voltage from the pixels PX11to PXMNthrough a second input terminal.

The image sensor40may operate in a global shutter manner. In the image sensor40operating in the global shutter manner, photodiodes included in the pixels PX11to PXMNmay be reset at once and exposed to light for a predetermined exposure time. Hereinafter, a description will be provided with reference toFIG. 4.

FIG. 4is a diagram provided to describe an operation of an image sensor according to an exemplary embodiment.

FIG. 4is a diagram provided to describe a global shutter operation of the image sensor40. Referring toFIG. 4, the photodiodes of the pixels PX11to PXMNincluded in the pixel array70may be simultaneously reset for a reset time TRST. As an example, the row driver50may reset the photodiodes by turning on a reset transistor included in the pixel circuit of each pixel and connecting the photodiodes of the pixels PX11to PXMNto a predetermined power supply voltage.

Once the photodiodes are reset, the photodiodes included in the pixels PX11to PXMNmay be exposed to light for an exposure time TEXto generate charges. As an example, the exposure time TEXmay be determined by an operating environment, a shutter speed, an aperture value, and the like of the image sensor40.

When the exposure time TEXhas elapsed, the row driver50may scan each of the row lines ROWs. The readout circuit60may execute a readout operation for each of the pixels PX11to PXMNaccording to the order that the row driver50scans the row lines ROWs. The readout circuit60may read the reset voltage and the pixel voltage from each of the pixels PX11to PXMNfor a readout time TRO.

In order for the readout circuit60to read the reset voltage and the pixel voltage for the readout time TRO, the charges generated by the photodiodes for the exposure time TEXmay be stored in a storage area of the pixel circuit. The charges stored in the storage area may be moved to the floating diffusion node of the pixel circuit in response to the turn-on of the transfer transistor. The readout circuit60may read the reset voltage of the pixels PX11to PXMNbefore the transfer transistor is turned on, that is, while the charges are stored in the storage area. The readout circuit60may read the pixel voltage of the pixels PX11to PXMNafter the transfer transistor is turned on by the row driver50and the charges in the storage area are moved to the floating diffusion node.

FIG. 5is a circuit diagram illustrating a pixel included in the image sensor according to an exemplary embodiment.

Referring toFIG. 5, a pixel PX according to an exemplary embodiment may include a pixel circuit PC and a photodiode PD. A signal generated by the pixel circuit PC using the charges generated by the photodiode PD may be output through a column line COL.

The pixel circuit PC may include a transfer transistor TX, a reset transistor RX, a driving transistor DX, a selection transistor SX, a storage transistor STX, an intermediate transfer transistor TXX, an overflow transistor OX, and the like. The overflow transistor OX may be turned on and turned off by an overflow control signal OG, and may be connected between a power supply node providing a power supply voltage VDD and the photodiode PD to prevent saturation of the photodiode PD.

In the image sensor operating in the global shutter manner, the photodiode PD, the charges stored in the storage transistor STX, the floating diffusion node FD, and the like may be reset for the reset time. The photodiode PD is exposed to light for the exposure time after the reset time, and the charges generated by the photodiode PD in response to light may be stored in the storage transistor STX.

As described above, in the image sensor operating in the global shutter manner, the readout operation may be executed in a rolling manner after the exposure time expires. As an example, in the readout operation, the reset voltage and the pixel voltage may be sequentially output. For example, the selection transistor SX is turned on such that the reset voltage may be output through the column line COL. After the reset voltage is output, the transfer transistor TX is turned on such that the charges stored in the storage transistor STX may be transferred to the floating diffusion node.

A voltage of the floating diffusion node FD may vary depending on an amount of charges transferred from the storage transistor STX. The driving transistor DX operating as a source-follower amplifier may output a pixel voltage corresponding to the amount of charges transferred to the floating diffusion node FD. Therefore, as transfer efficiency of the charges moving from the storage transistor STX to the floating diffusion node FD is higher when the transfer transistor TX is turned on, the performance of the image sensor may be improved.

In a general pixel circuit, due to an increase of a potential in a region adjacent to a boundary between the storage transistor STX and the transfer transistor TX when the transfer transistor TX is turned on, a potential hump (or potential barrier) phenomenon that hinders the transfer of charges may occur. In the exemplary embodiment, in a boundary region adjacent to the boundary between the storage transistor STX and the transfer transistor TX, at least one of the storage transistor STX and the transfer transistor TX may have a structure for preventing the potential hump. As an example, the structure may be formed on at least one of an active region of the storage transistor STX and a gate of the transfer transistor TX. Due to the above-mentioned structure, the potential of the boundary region may have a first potential when the transfer transistor TX is in a turned-off state, and may have a second potential, lower than the first potential, when the transfer transistor TX is the turned-on state. Therefore, the performance of the image sensor may be improved by increasing the transfer efficiency of the charges when the transfer transistor TX is in the turned-on state.

FIG. 6is a plan view illustrating pixels included in an image sensor according to an exemplary embodiment.

Referring toFIG. 6, an image sensor100according to an exemplary embodiment may include first to fourth pixels PX1to PX4arranged in the form of an array.FIG. 6illustrates only some of a plurality of pixels included in the image sensor100and the number of the pixels included in the image sensor100may be variously modified according to a plate shape, resolution, and the like of the image sensor. The first to fourth pixels PX1to PX4may have a similar structure to one another, and may be optically separated from one another by a pixel separation film (DTI). For convenience of explanation, a pixel structure will hereinafter be described by exemplifying the first pixel PX1.

Referring to first pixel PX1, the first pixel PX may include an active region103, a photodiode PD, and a plurality of gates which are formed by doping an impurity into a semiconductor substrate101. The gates may be coupled to the active region103to provide a plurality of transistors included in the pixel circuit. As an example, the first pixel PX1may include an intermediate transfer gate TXG, a storage gate STG, a transfer gate TG, a reset gate RG, an overflow gate OG, a driving gate DG, a selection gate SEL, and the like.

As an example, the image sensor100may operate in a global shutter manner. When the image sensor100starts to operate, the photodiodes PDs, and the charges stored in the storage transistors of the first to fourth pixels PX1to PX4, and floating diffusion nodes FDs, may be reset for a reset time. The photodiodes PDs are simultaneously exposed to light for the exposure time after the reset time, and the charges generated by the photodiodes PDs may be stored in the storage transistors STXs.

For a readout time after the exposure time, readout operations for the first to fourth pixels PX1to PX4may be executed in a rolling manner. The reset voltage and the pixel voltage of the first pixel PX1and the second pixel PX2that do not share a column line may be simultaneously output, while the reset voltage and the pixel voltage of the first pixel PX1and the third pixel PX3that shares a column line may not be simultaneously output In the readout operation of the first to fourth pixels PX1to PX4, the transfer transistor may be turned on by a voltage input to the transfer gate TG after the reset voltage is output, and the charges stored in the storage transistor may be transferred to the floating diffusion node FD.

As described above, when the transfer transistor is turned on and the charges are transferred, a problem that hinders the transfer of the charges may occur due to an increase in a potential around a boundary between the storage transistor and the transfer transistor. Referring toFIG. 6, in an exemplary embodiment, the transfer gate TG may include a first gate region110and a second gate region120, and the first gate region110may protrude toward the storage transistor. The first gate region110may be disposed on at least a portion of the active region103of the storage transistor. In an exemplary embodiment, the storage gate STG may provide a space accommodating the first gate region110.

By the first gate region110, the potential at the boundary between the transfer transistor and the storage transistor may not increase when the transfer transistor is turned on. As an example, when the transistors included in the first to fourth pixels PX1to PX4are N-channel metal oxide semiconductor (NMOS) transistors, the transfer transistor may be turned on by applying a high voltage to the transfer gate TG. In this case, the potential is decreased at a boundary region adjacent to the boundary between the storage transistor and the transfer transistor by the high voltage applied to the first gate region110such that the charges may be smoothly transferred to the floating diffusion node FD.

In addition, by making the first gate region110narrower than the second gate region120, the potential may be controlled to be tilted to only the floating diffusion node FD in the boundary region when the transfer transistor is turned on. Therefore, a reverse transfer of the charges from the floating diffusion node FD to the storage transistor may be prevented.

FIGS. 7A and 7Bare cross-sectional views illustrating a cross section taken along a direction I-I′ of the image sensor100illustrated inFIG. 6.

Referring first toFIG. 7A, the first pixel PX1of the image sensor100may include a semiconductor substrate101, a micro lens130, an optical insulating layer140, and a plurality of transistors. The optical insulating layer140may include a color filer, a planarization layer, and the like.

The pixel separation film DT1, the active region103for providing the transistors, and the like may be formed on the semiconductor substrate101. At least a portion of the active region103may be provided as the floating diffusion node FD. Referring toFIG. 7A, the first gate region110of the transfer gate TG may be disposed on the active region103of the storage transistor, together with the storage gate STG. That is, the first gate region110of the transfer gate TG may overlap at least a portion of the active region of the storage transistor.

Next, referring toFIG. 7B, the first pixel PX1may further include a barrier layer105provided below the active region103of the storage transistor. The barrier layer105may be doped with an impurity having conductivity different from that of a main charge carrier of the image sensor100. As an example, when the photodiodes of the image sensor100use electrons generated in response to light as the main charge carrier and the transistors are the NMOS transistors, the barrier layer105may be doped with a p-type impurity. The barrier layer105may prevent the charges stored in the storage transistor from leaking.

FIGS. 8 and 9are diagrams provided to describe an operation of an image sensor according to an exemplary embodiment.

Referring toFIGS. 8 and 9, there is illustrated a change in potential of the storage transistor, the transfer transistor, and floating diffusion node FD according to an on/off operation of the transfer transistor. Referring first toFIG. 8, as the charges are stored in the storage transistor, the potential at a lower portion of the storage gate STG may be relatively low. The transfer gate TG may have the first gate region110and the second gate region120as described with reference toFIGS. 6, 7A, and 7B, and when a turn-off voltage is input to the transfer gate TG, the potential at a lower portion of the transfer gate TG maintains a high state such that the charges may not be transferred to the floating diffusion node FD.

When the turn-on voltage is input to the transfer gate TG to turn on the transfer transistor, the potential at the lower portion of the transfer gate TG is decreased such that the charges stored in the storage transistor may be transferred to the floating diffusion node FD. The potential at a lower portion of the first gate region110may be decreased by the turn-on voltage input to the first gate region110overlapping at least a portion of the active region of the storage transistor. Therefore, as illustrated inFIG. 8, the potential may be gradually decreased at the lower portion of the first gate region110corresponding to the boundary region adjacent to the boundary between the storage transistor and the transfer transistor. The potential may be decreased in a direction away from the storage transistor and being closer to the floating diffusion node FD.

In an exemplary embodiment, the potential of the boundary region corresponding to the lower portion of the first gate region110may have a first potential when the turn-off voltage is input to the transfer gate TG, and may have a second potential, lower than the first potential, when the turn-on voltage is input to the transfer gate TG. When the turn-on voltage is input to the transfer gate TG, the charges stored in the storage transistor may be smoothly transferred to the floating diffusion FD. Therefore, the performance of the image sensor may be improved without increasing an area of the storage transistor.

FIG. 9is a diagram illustrating a change in potential when the first gate region110is not formed, that is, when the transfer gate TG includes only the second gate region120. Referring toFIG. 9, as the first gate region110is omitted, a potential hump section in which the potential increases in the boundary region adjacent to the boundary between the storage transistor and the transfer transistor may appear. Therefore, even though the transfer transistor TG is turned on, the charges stored in the storage transistor may not be transferred to the floating diffusion node FD.

As described with reference toFIG. 8, in an exemplary embodiment, the potential hump section may be removed by forming the first gate region110in the transfer gate TG protruding toward the storage transistor. By the turn-on voltage input to the first gate region110, the potential of a portion of the active region of the storage transistor adjacent to the transfer transistor may be decreased, and the potential hump section may be thus removed.

FIG. 10is a plan view illustrating pixels included in an image sensor according to an exemplary embodiment.

Referring toFIG. 10, an image sensor200according to an exemplary embodiment may include first to fourth pixels PX1to PX4arranged in the form of an array. Similar toFIG. 6,FIG. 10illustrates only some of a plurality of pixels included in the image sensor200and the number of the pixels included in the image sensor200may be variously modified according to a plate shape, resolution, and the like of the image sensor. In describing the first to fourth pixels PX1to PX4, the contents similar to those of the image sensor100ofFIG. 6will be omitted.

The charges generated by the photodiode of each of the first to fourth pixels PX1to PX4of the image sensor200may be stored in the storage transistor, and may be transferred to the floating diffusion node FD in response to the turn-on operation of the transfer transistor. In order that the potential hump section generated between the storage transistor and the transfer transistor do not hinder the transfer of the charges, the active region of the storage transistor may include a first impurity region204having a relatively higher impurity concentration. As illustrated inFIG. 10, the first impurity region204may be adjacent to the transfer transistor.

FIGS. 11A and 11Bare cross-sectional views illustrating a cross section taken along a direction II-II' of the image sensor200illustrated inFIG. 10.

Referring first toFIG. 11A, the first pixel PX1of the image sensor200may include a semiconductor substrate201, a micro lens230, an optical insulating layer240, and the like, and a pixel separation film DTI and an active region203may be formed on the semiconductor substrate201. The active region203providing the storage transistor together with the storage gate STG may include a first impurity region204and a second impurity region204having an impurity concentration lower than that of the first impurity region204. The first impurity region204may be disposed closer to the transfer gate TG than the second impurity region205.

As an example, when the electrons are the main charge carriers and the transistors included in the pixel circuit are the NMOS transistors, the potential hump section may not appear by the first impurity region204having a relatively high impurity concentration. Therefore, when the turn-on voltage is input to the transfer gate TG, the charges stored in the storage transistor may be smoothly transferred to the floating diffusion node FD.

Next, referring toFIG. 11B, the first pixel PX1of the image sensor200may further include a barrier layer207provided below the active region203of the storage transistor. The barrier layer207may be doped with an impurity having conductivity different from that of the main charge carrier of the image sensor100. As an example, when the transistors included in the pixel circuit of the image sensor200are the NMOS transistors, the barrier layer207may be doped with a p-type impurity to prevent the charges stored in the storage transistor from leaking.

FIG. 12is a plan view illustrating a pixel included in an image sensor according to an exemplary embodiment. In addition,FIG. 13is a cross-sectional view illustrating a cross section taken along a direction III-III' of the image sensor illustrated inFIG. 12.

Referring toFIGS. 12 and 13, a pixel PX of an image sensor300may be optically separated from other pixels by a pixel separation film DTI. The pixel PX may include a semiconductor substrate301, a micro lens330, an optical insulating layer340, and the like, and an active region303for providing a plurality of transistors may be formed on the semiconductor substrate301. A plurality of gates STG, TXG, TG, RG, OG, DG, and SEL may be formed of a conductive material together with the active region303to provide a plurality of transistors. The transistors may convert the charges generated by the photodiode PD in response to light into electric signals.

In an exemplary embodiment illustrated inFIGS. 12 and 13, the transfer gate TG may include a first gate region310and a second gate region320. The first gate region310may be a region that extends from the second gate region320and protrudes toward the storage gate STG, and may have a width narrower than that of the second gate region320.

In addition, in an exemplary embodiment illustrated inFIGS. 12 and 13, the active region providing the storage transistor may include the first impurity region304and a second impurity region305defined as the remaining region other than the first impurity region304. The first impurity region304may have an impurity concentration higher than that of the second impurity region305, and may be adjacent to the transfer gate TG. As an example, the first impurity region304may have a shape corresponding to the first gate region310as illustrated inFIG. 12, and may surround the first gate region310in a plane.

The first impurity region304may not overlap the transfer gate TG including the first gate region310. Therefore, as illustrated inFIG. 13, the first impurity region304may be disposed between the second impurity regions305in at least one direction.

FIG. 14is a plan view illustrating a pixel included in an image sensor according to an exemplary embodiment andFIG. 15is a cross-sectional view illustrating a cross section taken along a direction IV-IV′ of the image sensor illustrated inFIG. 14.

Referring toFIGS. 14 and 15, a pixel PX of an image sensor300A may be surrounded by a pixel separation film DTI and may be optically and electrically separated from other pixels. The pixel PX may include the semiconductor substrate301on which the active region303is formed, the micro lens330, the optical insulating layer340, and the like, and a plurality of transistors implementing a pixel circuit may be provided by a plurality of gates STG, TXG, TG, RG, OG, DG, and SEL formed on the semiconductor substrate301.

In an exemplary embodiment illustrated inFIGS. 14 and 15, the transfer gate TG may include the first gate region310and the second gate region320. In addition, an active region303A of the storage transistor may include a first impurity region304A and a second impurity region305A. The first gate region310may be a region protruding toward the storage transistor and the first impurity region304A may have an impurity concentration higher than that of the second impurity region305A.

At least a portion of the first impurity region304A may be disposed below the transfer gate TG. The first impurity region304A may not be surrounded by the second impurity region305A in the active region303A of the storage transistor. In an exemplary embodiment illustrated inFIGS. 14 and 15, the first impurity region304A may be disposed closer to the transfer gate TG than the second impurity region305A.

FIGS. 16 and 17are plan views illustrating pixels included in an image sensor according to an exemplary embodiment.

Referring first toFIG. 16, a pixel PX of an image sensor400may be optically and electrically separated from other pixels by a pixel separation film DTI, and may include an active region403and a photodiode PD formed on an active region403of a semiconductor substrate401and a plurality of gates STG, TXG, TG, RG, OG, DG, and SEL disposed on the semiconductor substrate401. The active region403and the gates STG, TXG, TG, RG, OG, DG, and SEL may process charges in the photodiode PD to implement a pixel circuit generating electrical signals.

In an exemplary embodiment illustrated inFIG. 16, regions404,405, and406having a relatively high impurity concentration may be formed below the storage gate STG, the intermediate transfer gate TXG, and the overflow gate OC, respectively. First, a first impurity region404having a relatively high impurity concentration and a second impurity region, which is the remaining active region403other than the first impurity region404, may be disposed below the storage gate STG.

As an example, the active region below the intermediate transfer gate TXG may have a third impurity region405having a relatively high impurity concentration and adjacent to the storage gate STG, and a fourth impurity region, which is the remaining active region403other than the third impurity region405. In addition, the active region below the overflow gate OG may have a fifth impurity region406having a relatively high impurity concentration and disposed to be away from the photodiode PD, and a sixth impurity region, which is the remaining active region403other than the fifth impurity region406.

The first impurity region403, the third impurity region404, and the fifth impurity region405may be disposed in consideration of a transfer direction of the charges. As an example, the charges generated by the photodiode PD may pass through the intermediate transfer gate TXG, and may be stored in the storage transistor including the storage gate STG. In addition, when the turn-on voltage is input to the transfer gate TG, the charges may be transferred to the floating diffusion node FD. Therefore, according to the transfer direction of the charges, the third impurity region405below the intermediate transfer gate TXG may be adjacent to the storage gate STG, and the first impurity region404below the storage gate STG may be adjacent to the transfer gate TG. The charges generated by the photodiode PD may be smoothly transferred to the floating diffusion node FD by the third impurity region405below the intermediate transfer gate TXG and the first impurity region404below the storage gate STG.

The fifth impurity region406formed below the overflow gate OG may prevent a reverse transfer of the charges. When the turn-on voltage is input to the overflow gate OG, the charges of the photodiode PD may be removed by a power supply voltage. In an exemplary embodiment illustrated inFIG. 16, the fifth impurity region406below the overflow gate OG may significantly reduce the reverse transfer that the charges transfers back to the photodiode PD while the turn-on voltage is input to the overflow gate OG, and quickly remove the charges of the photodiode PD, thereby preventing a saturation of the photodiode PD.

Next, referring toFIG. 17, in a pixel PX of an image sensor400A, the transfer gate TG may include a first gate region410and a second gate region420. The first gate region410may be a region that extends from the second gate region420and protrudes toward the storage gate STG, and may be accommodated in a space provided in the storage gate STG. In an exemplary embodiment illustrated inFIG. 17, the first gate region410may be formed to prevent an occurrence of potential hump between the storage transistor and the transfer transistor.

Referring toFIG. 17, the pixel PX of the image sensor400A may have the third impurity region405and the fifth impurity region406having the relatively high impurity concentration and formed on the active regions of the intermediate transfer transistor and the overflow transistor, respectively. In addition, unlike the exemplary embodiment illustrated inFIG. 16, the first impurity region404may not be formed on the active region of the storage transistor. However, according to exemplary embodiments, as described above with reference toFIGS. 12 and 14, the first impurity region404may also be added to the active region of the storage transistor.

FIG. 18is a diagram illustrating an imaging device including an image sensor according to an exemplary embodiment.

Referring toFIG. 18, an imaging device500according to an exemplary embodiment may include a light source501and a sensor unit502. The light source501may include a light emitting element outputting an optical signal having a specific wavelength band. As an example, the light source501may include vertical cavity surface emitting laser (VCSEL), a light emitting diode (LED), or the like as the light emitting element. The light source501may include a plurality of light emitting elements arranged in the form of an array, and optical elements may be further provided on process paths of optical signals output by the light emitting elements. The optical signals output by the light source501may be optical signals having an infrared wavelength band.

The optical signals output by the light source501may be reflected by an object510, and the sensor unit502may be input with the optical signals reflected by the object510as received optical signals. The sensor unit502may include a pixel array having pixels generating electrical signals in response to the received optical signals, a controller generating an image using the electrical signals generated by the pixel array, and the like. As an example, the image generated by the controller may be a depth map including the object510and distance information of environments around the object510.

In an exemplary embodiment, the sensor unit502may provide a proximity sensing function for sensing the presence of the object510close to the imaging device500, a distance measuring function for calculating a distance between the object510and the imaging device500, and the like, together with a function for generating the depth map. As the sensor unit502accurately detects the received optical signals which are output by the light source501and are reflected by the object510, the above-mentioned functions may be implemented more accurately. Therefore, in order to increase sensitivity of the sensor unit502, an area of the photodiode included in each of the pixels may be increased.

FIG. 19is a block diagram illustrating the imaging device including an image sensor according to an exemplary embodiment.

Referring toFIG. 19, an imaging device600may include a pixel array610, a controller620, a light source driver630, a light source640, and the like.

The pixel array610may include a plurality of pixels PXs arranged in the form of array along a plurality of rows and a plurality of columns. Each of the pixels PX may include a photodiode generating charges in response to optical signals incident from an object650, and a pixel circuit generating an electrical signal corresponding to the charges generated by the photodiode. As an example, the pixel circuit may include a floating diffusion node, an intermediate transfer transistor, a storage transistor, a transfer transistor, a reset transistor, a driving transistor, a selection transistor, and the like. The configuration of the pixels PXs may vary depending on the exemplary embodiments. As an example, each of the pixels PXs may include an organic photodiode that includes an organic material, unlike a silicon photodiode, or may be implemented as a digital pixel. When the pixel PX is implemented as the digital pixel, each of the pixels PXs may include a comparator, a counter converting an output of the comparator into a digital signal and outputs the digital signal, and the like.

The controller620may include a plurality of circuits for controlling the pixel array610. As an example, the controller620may include a row driver621, a readout circuit622, a column driver623, a control logic624, and the like. The row driver621may drive the pixel array610in units of rows. For example, the row driver621may generate a transfer control signal that controls the transfer transistor of the pixel circuit, a reset control signal that controls the reset transistor, a selection control signal that controls the selection transistor, and the like.

The readout circuit622may include a correlated doubled sampler (CDS), an analog-to-digital converter (ADC), and the like. The correlated double sampler may be connected to the pixels PXs included in a row selected by a row selection signal supplied by the row driver621through column lines, and may perform correlated double sampling to detect the reset voltage and the pixel voltage. The analog-to-digital converter may convert the reset voltage and the pixel voltage detected by the correlated double sampler into digital signals, and may transfer the digital signals to the column driver623.

The column driver623may include a latch or buffer circuit in which the digital signals may be temporarily stored, an amplification circuit, and the like, and process the digital signals received from the readout circuit622. The row driver621, the readout circuit622, and the column driver623may be controlled by the control logic624. The control logic624may include a timing controller for controlling operation timings of the row driver621, the readout circuit622, and the column driver623, an image signal processor for processing image data, and the like.

The control logic624may perform signal processing for data output by the readout circuit622and the column driver623to generate image data. As an example, the image data may include a depth map. In addition, the control logic624may calculate a distance between the object650and the imaging device600or recognize the object650close to the imaging device600by using the data output by the readout circuit622and the column driver623according to an operation mode of the imaging device600.

The imaging device600may include the light source640outputting the optical signal to the object650to generate the depth map. The light source640may include one or more light emitting elements, and as an example, a plurality of semiconductor light emitting elements may include semiconductor chips arranged in the form of an array. The light source640may operate by the light source driver630. The light source driver630may be controlled by the controller620.

In an exemplary embodiment, the light source driver630may generate a predetermined pulse signal to drive the light source640. The light source driver630may respond to a control command of the controller620to determine a period, a duty ratio, duration, and the like of the pulse signal. As an example, the controller620may synchronize at least one of the signals input to the pixel array610with the pulse signal input to the light source640. In an exemplary embodiment, the signal synchronized with the pulse signal input to the light source640may be at least one of the signals input to the pixel array610by the row driver621.

FIG. 20is a circuit diagram illustrating pixel circuits of a pixel included in an image sensor according to an exemplary embodiment.

Referring toFIG. 20, in a pixel PX of an image sensor according to an exemplary embodiment, a plurality pixel circuit circuits PCA, PCB, PCC, and PCD may be connected to a single photodiode PD. Although it is illustrated in an exemplary embodiment illustrated inFIG. 20that first to fourth pixel circuits PCA, PCB, PCC, and PCD are connected to the photodiode PD, the number of pixel circuits may be changed according to the exemplary embodiments. The first to fourth pixel circuits PCA, PCB, PCC, and PCD may have substantially the same structure as each other.

The image sensor according to an exemplary embodiment illustrated inFIG. 20may be a time-of-flight (ToF) sensor that detects optical signals discharged from a separate light source and reflected from the object to determine a shape of the object, a distance to the object, and the like. The optical signals discharged from the light source may be reflected from the object to generate a phase difference, and the image sensor may determine the shape of the object, the distance to the object, and the like by using the phase difference. As an example, the image sensor may generate a depth map including the shape of the object, the distance to the object, or the like by using information obtained from the separate pixel PX.

The image sensor applied as the ToF sensor may operate in a global shutter manner. While the photodiode is exposed to light, first to fourth intermediate transfer transistors TXXA, TXXB, TXXC, and TXXD included in the first to fourth pixel circuits PCA, PCB, PCC, and PCD may operate with phases different from one another. As an example, the first intermediate transfer transistor TXXA may be turned on and off with the same phase as the optical signal, and the second intermediate transfer transistor TXXB may be turned on and off with a phase difference of 180 degrees with the optical signal. The third intermediate transfer transistor TXXC may be turned on and off with a phase difference of 90 degrees with the optical signal, and the fourth intermediate transfer transistor TXXD may be turned on and off with a phase difference of 270 degrees with the optical signal.

The image sensor may generate the depth map by using pixel voltages obtained from the charges stored in first to fourth storage transistors STXA, STXB, STXC, and STXD by the phase difference operations as described above. In a readout operation, first data corresponding to the charges stored in the first storage transistor STXA may be output through a first column line COL1, and third data corresponding to the charges in the third storage transistor STXC may be output through a third column line COL3. In addition, second data corresponding to the charges stored in the second storage transistor STXB may be output through a second column line COL2, and fourth data corresponding to the charges in the fourth storage transistor STXD may be output through a fourth column line COLO. Meanwhile, according to the exemplary embodiments, the first pixel circuit PCA and the third pixel circuit PCC may be connected to a single column line, and the second pixel circuit PCB and the fourth pixel circuit PCD may also be connected to a single column line.

FIGS. 21 through 23are plan views illustrating pixels included in an image sensor according to an exemplary embodiment.

As an example, a pixel700illustrated inFIGS. 21 through 23may correspond to the pixel PX described above with reference toFIG. 20. Referring first toFIG. 21, a pixel700may be optically and electrically separated from other pixels PXs by a pixel separation film DTI formed on a semiconductor substrate701. In addition, the pixel700may include a photodiode PD, and first to fourth photo gates PGA, PGB, PGC, and PGD may be disposed on the photodiode PD. An active region703for providing a plurality of transistors may be formed on the semiconductor substrate701.

The first to fourth photo gates PGA, PGB, PGC, and PGD may be provide for connecting the photodiode PD with first to fourth pixel circuits. As an example, the charges generated by the photodiode PD may be stored in a first storage transistor while the turn-on voltage is input to a first intermediate transfer gate TXGA and a first storage gate STGA. While the turn-on voltage is input to the first intermediate transfer gate TXGA and the first storage gate STGA, the turn-off voltage may be input to second to fourth intermediate transfer gates TXGB, TXGC, and TXGD and second to fourth storage gates STGB, STGC, and STGD.

In an exemplary embodiment illustrated inFIG. 21, a first transfer gate TGA may have a protrusion region extending toward the first storage gate STGA. The first storage gate STGA may provide a space for accommodating the protrusion region of the first transfer gate TGA. Second to fourth transfer gates TGB, TGC, and TGD and the second to fourth storage gates STGB, STGC, and STGD may have a shape similar to that of the first transfer gate TGA and the first storage gate STGA, respectively.

Similarly to the exemplary embodiments described above, the protrusion region overlapping at least a portion of the active region703of the first storage transistor may be formed in the first transfer gate TGA to prevent an occurrence of potential hump when the turn-on voltage is input to the first transfer gate TGA. Therefore, when the turn-on voltage is input to the first transfer gate TGA, the charges generated by the photodiode PD and stored in the first storage transistor may be smoothly transferred to the floating diffusion node FD.

Next, structures and operations of pixels700A and700B included in the image sensor according to an exemplary embodiment will be described with reference toFIGS. 22 and 23. For convenience of explanation, the description overlapping that of the pixel700according to an exemplary embodiment illustrated inFIG. 21will be omitted.

Referring first toFIG. 22, first to fourth transfer gates TGA, TGB, TGC, and TGD included in a pixel700A may not include protrusion regions. A first pixel circuit will be described as an example. A first impurity region704having a relatively high impurity concentration may be formed in a portion of an active region of a first storage transistor adjacent to the first transfer gate TGA. By forming the first impurity region704, a potential hump may be prevented at a boundary between the first storage transistor and the first transfer transistor and transfer efficiency of the charges may be improved. The first impurity region704may also be formed on the active regions of the second to fourth storage transistors.

Next, referring first toFIG. 23, first to fourth transfer gates TGA, TGB, TGC, and TGD included in a pixel700B may include protrusion regions. In addition, portions of the active regions of the first to fourth storage transistors may be additionally doped with an impurity to form first impurity regions705. The first impurity regions705may be formed to be adjacent to the protrusion regions of the first to fourth transfer gates TGA, TGB, TGC, and TGD in consideration of a transfer direction of the charges. Therefore, when the turn-on voltage is input to each of the first to fourth transfer gates TGA, TGB, TGC, and TGD, an occurrence of a potential hump may be prevented and transfer efficiency of the charges may be increased.

FIG. 24is a block diagram illustrating an electronic device including an image sensor according to an exemplary embodiment.

A computer device1000according to an exemplary embodiment illustrated inFIG. 24may include a display1010, an image sensor1020, a processor1040, a port1050, and the like. In addition, the computer device1000may further include a wired and wireless communication device, a power supply device, and the like. Among the components illustrated inFIG. 24, the port1050may be a device through which the computer device1000communicates with a video card, a sound card, a memory card, a USB device, or the like. The computer device1000may be a concept including both a general desktop computer or a laptop computer, as well as a smartphone, a tablet PC, and a smart wearable device.

The processor1040may perform specific operations, instructions, tasks, or the like. The processor1040may be a central processing unit (CPU), a microprocessor unit (MCU), a system on chip (SoC), or the like, and may communicate with other devices connected to the port1050as well as the display1010, the sensor unit1020, the memory device1030via a bus1060.

The memory1030may be a storage medium for storing data necessary for the operation of the computer device1000, or multimedia data. The memory1030may include a volatile memory, such as a random access memory (RAM), or a non-volatile memory such as a flash memory. In addition, the memory1030may include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical drive (ODD) as a storage device. The image sensor1020may be employed in the computer device1000in the forms according to various exemplary embodiments described with reference toFIGS. 1 through 23.

As set forth above, according to the exemplary embodiment, at least a portion of the gate of the transfer transistor may protrude toward the gate of the storage transistor, or some regions adjacent to the transfer transistor in the active region of the storage transistor may have a relatively high impurity concentration relative to other regions. Therefore, when the transfer transistor is turned on, the potential between the storage transistor and the transfer transistor may gradually decrease as it is closer to the transfer transistor, and the charge transfer efficiency may be increased to improve the performance of the image sensor.

Various advantages and effects of the inventive concept are not limited to the description above, and may be more readily understood in the description of exemplary embodiments.