Method and system for implementing dynamic ground sharing in an image sensor with pipeline architecture

A method of implementing dynamic ground sharing in an image sensor with pipeline architecture starts with a pixel array capturing image data. Pixel array includes pixels to generate pixel data signals, respectively. A readout circuitry acquires the image data from a row in the pixel array. An analog-to-digital conversion (ADC) circuitry included in the readout circuitry samples the image data from the row to obtain sampled input data. When the ADC circuitry is sampling, a ground sharing switch is closed to couple the pixel array and the ADC circuitry to a common ground. When the ADC circuitry is not sampling, the ground sharing switch is open to separate the pixel array and the ADC circuitry from the common ground. The ADC circuitry converts the sampled image data from analog to digital to obtain an ADC output. Other embodiments are described.

FIELD

An example of the present invention relates generally to image sensors with pipeline architecture. More specifically, examples of the present invention are related to methods and systems for implementing dynamic ground sharing in an image sensor with pipeline architecture.

BACKGROUND

High-speed image sensors have been widely used in many applications in different fields including the automotive field, the machine vision field, and the field of professional video photography. The development of high speed image sensors is further driven by the consumer market's continued demand for high speed slow motion video and normal high-definition (HD) video that have a reduced rolling shutter effect.

In addition to the frame rate and power consumption demands, image sensors are also subjected to performance demands. The quality and accuracy of the pixel readouts cannot be compromised to accommodate the increase in frame rate or power consumption.

In order to increase the frame rate, pipeline architectures have been implemented in high-speed image sensors that allow for multiple workflows to be occurring in a high-speed image sensor. However, electrical interference from the different elements in the high-speed image sensor may degrade the image quality being generated by the image sensor.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown to avoid obscuring the understanding of this description.

Examples in accordance with the teaching of the present invention describe an image sensor with pipeline architecture that implements dynamic ground sharing. In pipeline architecture, two or more workflows may be occurring at the same time in one image sensor. Accordingly, while a first row (e.g., current row) of pixels is reset, transferred, sampled, etc., a second row (e.g., previous row) of pixels are converted by an analog-to-digital conversion (ADC) circuitry. In this example, the first row is subsequent to the second row in a pixel array. In some embodiments, a ground sharing switch is closed to couple pixel array and ADC circuitry to a common ground when ADC is sampling, and is open to separate pixel array and ADC circuitry from the common ground when the ADC circuitry is not sampling. There is an electrical interference from pixel actions to ADC circuitry. This may be caused by pixel array and ADC circuitry sharing the same analog ground (e.g. common ground). However, when ADC circuitry samples, it is preferred to have pixel array and ADC circuitry sharing the same ground, otherwise, additional noise will be generated. Accordingly, the electrical interference from pixel actions to ADC circuitry that is caused by pixel array and ADC circuitry sharing the same common ground is reduced.

FIG. 1is a block diagram illustrating an example imaging system100with pipeline architecture that implements dynamic ground sharing in accordance to one embodiment of the invention. Imaging system100may be a complementary metal-oxide-semiconductor (“CMOS”) image sensor. As shown in the depicted example, imaging system100includes pixel array105coupled to control circuitry120and readout circuitry110, which is coupled to function logic115and logic control108.

The illustrated embodiment of pixel array105is a two-dimensional (“2D”) array of imaging sensors or pixel cells (e.g., pixel cells P1, P2, . . . , Pn) that generate pixel data signals, respectively. In one example, each pixel cell is a CMOS imaging pixel. As illustrated, each pixel cell is arranged into a row (e.g., rows R1to Ry) and a column (e.g., columns C1to Cx) to acquire image data of a person, place or object, etc., which can then be used to render an image of the person, place or object, etc. Pixel array105may includes visible pixels and optical black pixels (OPB). The visible pixels convert the light incident to the pixel to an electrical signal (e.g., a visible signal) and output the visible signal whereas the OPB output a dark signal. In one embodiment, pixel array105captures image data, which may include resetting pixels in pixel array105, pre-charging pixels in pixel array105, and transferring the pixel data signals to readout circuitry110.

In one example, after each pixel has acquired its image data or image charge, the image data is read out by readout circuitry110through readout column bit lines109and then transferred to function logic115. In one embodiment, a logic circuitry108can control readout circuitry110and output image data to function logic115. In various examples, readout circuitry110may include amplification circuitry (not illustrated), analog-to-digital conversion (ADC) circuitry220, or otherwise. Function logic115may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one example, readout circuitry110may read out a row of image data at a time along readout column lines (illustrated) or may read out the image data using a variety of other techniques (not illustrated), such as a serial read out or a full parallel read out of all pixels simultaneously.

In one example, control circuitry120is coupled to pixel array105to control operational characteristics of pixel array105. For example, control circuitry120may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels within pixel array105to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows.

FIG. 2is a block diagram illustrating the details of pixel array105and readout circuitry120of imaging system100inFIG. 1that implements dynamic ground sharing in accordance to one embodiment of the invention. In some embodiments, readout circuitry110implements correlated double-sampling (CDS). As shown inFIG. 2, the readout circuitry110may include scanning circuit210and an ADC circuitry220. Scanning circuitry210may include amplification circuitry, selection circuitry (e.g., multiplexers), etc. to readout a row of image data at a time along readout column bit lines109or may readout the image data using a variety of other techniques, such as a serial readout or a full parallel readout of all pixels simultaneously.

In one embodiment, scanning circuitry210selects and amplifies image data from the row and transmitting the image data from the row to ADC circuitry220. ADC circuitry220may receive the image data from a row in the pixel array from scanning circuitry210or from pixel array105. While not illustrated, in some embodiments, ADC circuitry220may include a plurality of ADC circuits. ADC circuits may be a type of column ADC (e.g., SAR, cyclic, etc.). ADC circuits may be similar for each column of pixel array105. ADC circuitry220may sample image data from a row of pixel array105to obtain a sampled input data. ADC circuitry220may convert the sampled input data from analog to digital to obtain an ADC output.

As shown inFIG. 2, a ground sharing switch201couples or separates pixel array105and ADC circuitry220to a common ground. In one embodiment, ground sharing switch201is closed to couple pixel array105and ADC circuitry220to a common ground when ADC circuitry220is sampling, and is open to separate pixel array105and ADC circuitry220from the common ground when ADC circuitry220is not sampling. For example, while ADC circuitry220is not sampling, ground sharing switch201may be open when pixel array105captures the image data or when ADC circuitry220converts the sampled image data.

The electrical interference from pixel actions by pixel array105to ADC circuitry220may be caused by pixel array105and ADC circuitry220sharing the same common ground. However, when ADC circuitry220samples, it is preferred to have pixel array105and ADC circuitry220sharing the same ground, because, otherwise, additional noise will be generated. Accordingly, the electrical interference from pixel actions to ADC circuitry220that is caused by pixel array105and ADC circuitry220sharing the same common ground is reduced.

In one embodiment, logic circuitry108or control circuitry120may control ground sharing switch201. For instance, logic circuitry108or control circuitry120may generate a switch timing signal that controls the opening and closing of ground sharing switch201.FIG. 3is a timing diagram illustrating an exemplary switch timing signal in accordance to one embodiment of the invention. As shown inFIG. 3, switch timing signal may be set to ‘1’ to signal the closing of ground sharing switch201when ADC circuitry220is sampling, and switch timing signal may be set to ‘0’ to signal the opening of ground sharing switch201when ADC circuitry220is not sampling. In pipeline architecture, two or more workflows may be occurring at the same time in one image sensor100. Accordingly, while a first row (e.g., current row) of pixels is reset, transferred, sampled, etc., a second row (e.g., previous row) of pixels is converted by ADC circuitry220. In this example, the first row is subsequent to the second row in a pixel array. Thus, the switch ground sharing switch201to close in order to couple pixel array105and ADC circuitry220to a common ground when ADC circuitry220is sampling the current row of pixels in pixel array105while ADC circuitry220is converting a previous row of pixels in pixel array105.

Accordingly, the electrical interference from pixel actions to ADC circuitry220that is caused by pixel array105and ADC circuitry220sharing the same analog ground (e.g., common ground) is reduced using the ground sharing switch201. In one embodiment, the common ground is included on a printed circuit board (PCB).

In one embodiment, ADC circuitry220includes a digital-to-analog (DAC) circuitry and a Successive Approximation Register (SAR). DAC circuitry may be a capacitor-implemented DAC or may be implemented using resistors or a hybrid of resistors and capacitors. In this embodiment, the image data from the row on DAC circuitry is sampled against an ADC pedestal stored in SAR to obtain the sampled input data. ADC circuitry220then converts the sampled input data from analog to digital to obtain ADC output value by performing a binary search using DAC circuitry and SAR (not shown). SAR may be is reset before each conversion of sampled input data. The sampled input data is obtained by ADC circuitry220sampling the image data from a given row that is being processed.

In another embodiment, ADC circuitry220includes a comparator and an ADC counter (not shown). In this embodiment, ADC circuitry220converting the sampled input data from analog to digital includes comparator, such as a fully differential op, comparing the sampled input data to a ramp signal to generate a comparator output signal, and ADC counter counting based on the comparator output signal to generate the ADC output. In one embodiment, ramp signal is generated a ramp generator included in readout circuitry110or logic circuitry108. In one embodiment, logic circuitry108includes a phased locked loop (PLL) to generate an ADC clock signal that is transmitted to ramp generator. In this embodiment, ramp generator generates a ramp signal that is synchronized to the ADC clock signal.

SAR in conjunction with DAC circuitry perform a binary search and each bit in data output lines of DAC circuitry is set in succession from the most significant bit (MSB) to least significant bit (LSB). In one embodiment, comparator determines whether a bit in data output lines of DAC circuitry should remain set or be reset. At the end of the conversion, SAR holds a conversion of the sampled input data (e.g., ADC output). In some embodiments, function logic115receives and processes ADC outputs from ADC circuitry220to generate a final ADC output.

Moreover, the following embodiments of the invention may be described as a process, which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a procedure, etc.

FIG. 4is a flowchart illustrating a method400for implementing dynamic ground sharing in an image sensor100with pipeline architecture in accordance to one embodiment of the invention. Method400starts with a pixel array105capturing image data. Pixel array105includes pixels to generate pixel data signals, respectively (Block401). In some embodiments, pixel array105capturing the image data includes resetting the plurality of pixels the row of pixel array105, pre-charging the plurality of pixels in the row of pixel array105, and transferring the pixel data signals from pixel array105to readout circuitry110.

At Block402, a readout circuitry110acquires the image data from a row in pixel array105. In one embodiment, readout circuitry110acquires the image data from the row by selecting and amplifying the image data from the row and transmitting the image data from the row to ADC circuitry220.

At Block403, an ADC circuitry220included in readout circuitry110samples the image data from the row to obtain sampled input data. In one embodiment, a ground sharing switch201is closed to couple pixel array105and ADC circuitry220to a common ground when ADC circuitry220is sampling, and ground sharing switch201is open to separate pixel array105and ADC circuitry220from the common ground when the ADC circuitry220is not sampling. In one embodiment, the common ground is included on a printed circuit board (PCB). In this embodiment, PCB may be included in image sensor100. In one embodiment, at least one of logic circuitry108or control circuitry230controls ground sharing switch201by generating and transmitting a switch timing signal. At Block404, ADC circuitry220converts the sampled image data from analog to digital to obtain an ADC output. In some embodiments, function logic115receives and processes ADC outputs from ADC circuitry220to generate a final ADC output.

In one embodiment, sampling by ADC circuitry220the image data from the row to obtain the sampled input data includes sampling the image data from the row on a DAC circuitry included in the ADC circuitry220against an ADC pedestal stored in a SAR to obtain the sampled input data. In this embodiment, converting by ADC circuitry220the sampled input data from analog to digital to obtain the ADC output value includes performing a binary search using DAC circuitry and SAR.

In another embodiment, converting by ADC circuitry220the sampled input data from analog to digital to obtain the ADC output value includes comparing by a comparator included in ADC circuitry220the sampled input data to a ramp signal to generate a comparator output signal, and counting by an ADC counter based on the comparator output signal to generate an ADC output.