System and method for controlling modulation

A system and method for controlling modulation. The system includes a plurality of modulators and a transmitting unit. The plurality of modulators decodes data from a data signal and also encodes the data into a clock signal. The transmitting unit transmits the encoded clock signal. According to the system and method disclosed herein, the present invention provides optimized coding efficiency while minimizing overall power consumption.

FIELD OF THE INVENTION

The present invention relates to data transmission, and more particularly to a system and method for controlling modulation.

BACKGROUND OF THE INVENTION

High-speed serial data transmission between integrated circuits is a major source of power consumption due to high switching rates and driving currents associated with signal and clock transmission. One conventional solution is to use single-channel serial transmission (SCST), which causes a dynamic power draw. However, SCST suffers from board noise sensitivity. Another conventional solution is to use differential transmission, which is more immune to board noise. However, differential transmission requires twice as many board traces, making it expensive to manufacture. Also, differential transmission draws a significant amount of static current during operation.

Another conventional solution is to use frequency modulation techniques, which are effective at compressing data and providing noise immunity. However, these techniques require additional circuitry and do not address the high-power consumption issues. In fact, frequency modulation techniques consume too much power for most applications.

Accordingly, what is needed is an improved system and method for transmitting data. The system and method should be efficient, simple, cost effective and capable of being easily adapted to existing technology. The present invention addresses such a need.

SUMMARY OF THE INVENTION

A system and method for controlling modulation is disclosed. The system includes a plurality of modulators and a transmitting unit. The plurality of modulators decodes data from a data signal and also encodes the data into a clock signal. The transmitting unit transmits the encoded clock signal. According to the system and method disclosed herein, the present invention provides optimized coding efficiency while minimizing overall power consumption.

DETAILED DESCRIPTION OF THE INVENTION

A system and method in accordance with the present invention for controlling modulation are disclosed. The system includes a modulator that encodes data into a clock signal, where the encoding is based on relative phase positions. This optimizes coding efficiency and minimizes switching, which minimizes power consumption. To more particularly describe the features of the present invention, refer now to the following description in conjunction with the accompanying figures.

Although the present invention disclosed herein is described in the context of phase modulation and chip/board level signal transmission, the present invention may apply to other types of modulation and other levels of signal transmission and still remain within the spirit and scope of the present invention.

FIG. 1is a block diagram of a modulator in accordance with the present invention. In a specific embodiment, the modulator is a 21-bit modulator, which includes phase modulators102,104,106,108,110,112, and114. The phase modulators102-114are 3-bit phase modulators. The modulator also includes 8-bit units120,122,124,126,128,130,132, and136, and feedback glitch filters140and142.

FIG. 2is a flow chart showing a method for controlling phase modulation in accordance with the present invention. Referring to bothFIGS. 1 and 2together, the modulator decodes data from a data signal, in a step202. Next, each of the phase modulators102-114encodes the data into an edge of a reference clock signal, in a step204. Since the phase modulators102-114are 3-bit phase modulators, 3-bit words are encoded. Encoding 3 bits into each edge of the reference clock signal maximizes the amount of data in each transmission signal. While the phase modulators102-114are 3-bit phase modulators, the exact number of bits per modulator will depend on the specific application. Modulators of greater than 3-bits can be used is still remain within the spirit and scope of the present invention.

In this specific embodiment, there are seven 3-bit phase modulators102-114. As a result, a total 21 bits of data are transmitted during each reference clock cycle. The exact number of 3-bit phase modulators will depend on the specific application. Next, the 8-bit units120-136transmit the data encoded reference clock signal, in a step206.

Because data and clock information is combined into one transmission signal, the transmission signal can be transmitted at lower in frequency without compromising performance. Operating at lower frequencies contributes to lower overall power consumption. For example, by using a 3-bit encoding scheme in specific embodiments of the present invention, the signal switching rate can be reduced by 20% with respect to conventional serial transmission schemes. Furthermore, the phase modulators of the present invention consume little power by themselves and can be completely powered down while remaining settings in digital registers.

Furthermore, by minimizing the number of transmitting channels, the number of board traces is lowered. This makes the modulator less susceptible to board noise. In addition, modulator maintains a fixed switching rate, which makes it easier to transmit and recover data.

Next, the feedback filters140and142calibrate a reference clock signal, in a step208. This prevents glitches along the transmission line. The calibrating is accomplished by resetting the reference clock after the data has been transmitted through the modulator. This self-reset feature is done automatically and provides calibration with respect to the specific data set that is transmitted in a particular edge. Automatically resetting the reference clock eliminates phase error accumulation and compensates for process variation. This also ensures that each edge is later decoded correctly.

FIG. 3is a block diagram showing phase modulators302,304,306,308,310,312, and314, which can be used to implement the phase modulators102-114ofFIG. 1, respectively, in accordance with the present invention. Storage registers320,322,324,326, and328store data provided by the phase modulators302-314. The storage registers320-328together store 21 bits of data, which are subsequently transmitted in the reference clock signal.

In operation, generally, the phase modulators302-314decode data from a data signal, which is received via an input unit330. The input unit330reads in the first edge of a data signal and then feeds the first edge into each of the phase modulators302-314. In a specific embodiment, the first edge is a rising edge. Each of the phase modulators302-314enables an edge of the transmission signal to carry a 3-bit digital value. The seven 3-bit modulators output a total of 21 bits of data. The storage registers230-238store the 21 bits.

FIG. 4is a block diagram of a decoder400, which can be used to implement one of the phase modulators302-314ofFIG. 3, in accordance with the present invention. The decoder400is a 3-bit decoder and includes filters402,404,406,408,410,412, and414. In a specific embodiment, the filters402-414are 8-bit finite impulse response (FIR) counter filters. Each of the filters402-414stores an 8-bit value, providing high performance on a granular scale.

In operation, the decoder400decodes data from a data signal. Each filter402-414then reads a phase position from a delay chain. Based on the decoded data and the phase readings, the decoder400outputs a 3-bit digital value that indicates one of eight possible phase positions. The 3-bit digital value represents a 3-bit word, which is subsequently combined with other 3-bit words from other decoders to provide a 21-bit word.

The phase positions are relative to a reference phase provided by the reference clock. The decoder400is asynchronous in that the reference clock is separate and independent from the system clock. Accordingly, the decoder400does not rely on the system clock to decode or to generate the phase reference. This is possible because the modulator is data-locked to a reference clock signal.

According to the system and method disclosed herein, the present invention provides numerous benefits. For example, data-locked dual-edge phase modulation (DEPM) is provided with optimized coding efficiency and minimized power consumption. Embodiments of the present invention also provide a fixed switching rate and high noise rejection, eliminate phase error accumulation, and compensate for process variation.

A system and method for controlling modulation has been disclosed. The system includes a modulator that encodes data into a clock signal. This optimizes coding efficiency and minimizes switching, which minimizes power consumption.

The present invention has been described in accordance with the embodiments shown. One of ordinary skill in the art will readily recognize that there could be variations to the embodiments, and that any variations would be within the spirit and scope of the present invention. For example, the present invention can be implemented using hardware, software, a computer readable medium containing program instructions, or a combination thereof. Software written according to the present invention is to be either stored in some form of computer-readable medium such as memory or CD-ROM, or is to be transmitted over a network, and is to be executed by a processor. Consequently, a computer-readable medium is intended to include a computer readable signal, which may be, for example, transmitted over a network. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.