Techniques for converting floating-point to integer are described. An example of an instruction to perform such a conversion includes fields for an opcode, an identification of location of a packed data source operand, an identification of location of a packed data destination operand, an indication of a location in each packed data element of the packed data destination to store an 8-bit integer (INT8) value, wherein the opcode is to indicate to conversion circuitry is to downconvert data of each packed data element of the packed data source operand to an INT8 value and make available for storage the INT8 value in the identified location of a corresponding packed data element of the packed data destination.

BACKGROUND

Today, machine learning (ML) and artificial intelligence (AI) use different 32-bit and 16-bit floating point formats such as bloat16 (BF16) and IEEE float16 (FP16 or half precision) and IEEE float32 (FP32 or single precision). ML and AI also use an 8-bit integer (INT8) format. For cases in which signed or unsigned INT8 is used for matrix multiplication component of ML or AI, software, after doing a non-linear component using either float32 or float16 usually needs to down convert back to signed or unsigned INT8.

DETAILED DESCRIPTION

The present disclosure relates to methods, apparatus, systems, and non-transitory computer-readable storage media for performing a downconvert to 8-bit integer (INT8) values from larger floating point values.

With current architectures, a downconvert procedure is expensive as it requires several instructions to be performed. First there is a need to saturate, using maximum and minimum instructions, then convert to INT32 and then, pending on the architecture, convert directly to INT8 or first to INT16 and then to signed or unsigned INT8. These operations may also involve several shuffle operations.

There are no previously proposed instructions for performing a conversion from 16-bit half-precision floating-point (FP16)/full-precision floating-point (FP32) to signed or unsigned INT8 including saturation and a variable in-place indication. Such instructions will help to balance compute and speed-up execution.

Detailed herein are examples of instructions, and their support, to convert from FP32, FP16, and/or BF16 to INT8 that may include saturation and/or a variable in-place term. In some examples, this class of instructions is called FP2INT8.

For example, BF16 downconvert instructions convert eight, sixteen, or thirty-two packed Brain-float16 values (“BF16” of “bfloat16”) in a source operand to eight, sixteen, or thirty-two signed or unsigned byte integers. The location of the downconverted 8-bit results within a destination data element is determined by an immediate in some examples. The other bits are zeroed. These FP2INT8 instructions do not generate floating point exceptions and do not consult or update MXCSR in some examples. In some examples, denormal BF16 input operands are treated as zeros (DAZ)

In some examples, execution of a vector converts nearest even BF16 to signed integer byte instruction (e.g., opcode mnemonic VCVTNEBF162IBS) converts BF16 floating point elements into signed byte integer elements. When a conversion is inexact, the rounding mode is RNE. If a converted result cannot be represented in the destination format, then, if the value is too big, the singed integer maximum (e.g., INT_MAX_value (2{circumflex over ( )}(w−1)−1, where w represents the number of bits in the destination format) is returned. When the value is too small, the INT_MIN value (2{circumflex over ( )}(w−1)) is returned. When the result is a not-a-number (NaN), (0) is returned.

In some examples, execution of a vector converts nearest even BF16 to unsigned integer byte instruction (e.g., opcode mnemonic VCVTNEBF162IUBS) converts brain-float16 floating point elements into un-signed byte integer elements. When a conversion is inexact, and the rounding mode is RNE, if a converted result cannot be represented in the destination format, then, if the value is too big, the unsinged integer maximum (UINT_MAX) value (2{circumflex over ( )}w−1, where w represents the number of bits in the destination format) is returned. When the value is too small, the UINT_MIN value (0) is returned. In the case of a NaN result, (0) is returned.

In some examples, execution of a vector converts nearest even using truncation BF16 to signed integer byte instruction (e.g., opcode mnemonic VCVTTNEBF162IBS) converts brain-float16 floating point elements into signed byte integer elements. When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result cannot be represented in the destination format, then, if the value is too big, the INT_MAX value (2{circumflex over ( )}(w−1)-1, where w represents the number of bits in the destination format) is returned. When the value is too small, the INT_MIN value (2{circumflex over ( )}(w−1)) is returned. In the case of a NaN result, (0) is returned.

In some examples, execution of a vector converts nearest even using truncation BF16 to signed integer byte instruction (e.g., opcode mnemonic VCVTTNEBF162IUBS) converts brain-float16 floating point elements into un-signed byte integer elements. When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result cannot be represented in the destination format, then, if the value is too big, the UINT_MAX value (2{circumflex over ( )}w−1, where w represents the number of bits in the destination format) is returned. When the value is too small, the UINT_MIN value (0) is returned. In the case of a NaN result, (0) is returned.

In some examples, FP16 downconvert instructions convert eight, sixteen or thirty-two packed half-precision floating-point values in a source operand to eight, sixteen or thirty-two signed or un-signed byte integers in a destination operand. The location of downconverted 8-bit result within 32-bit elements is determined by an immediate in some examples. The other bits are zeroed.

In some examples, execution of a vector converts FP16 to signed integer byte instruction (e.g., opcode mnemonic VCVTPH2IBS) converts half-precision floating point elements into signed byte integer elements. When a conversion is inexact, a floating-point precision exception is raised and the value returned is rounded according to the rounding control bits in a control register (e.g., MXCSR register) or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked then, if the value is too big, the INT_MAX value (2{circumflex over ( )}(w−1)−1, where w represents the number of bits in the destination format) is returned. When the value is too small, the INT_MIN value (2{circumflex over ( )}(w−1)) is returned. In case of a NaN result, (0) is returned.

In some examples, execution of a vector converts FP16 to unsigned integer byte instruction (e.g., opcode mnemonic VCVTPH2IUBS) converts half-precision floating point elements into un-signed byte integer elements. When a conversion is inexact, floating-point precision exception is raised and the value returned is rounded according to the rounding control bits in a control register (e.g., MXCSR register) or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked then, if the value is too big, the UINT_MAX value (2{circumflex over ( )}w−1, where w represents the number of bits in the destination format) is returned. When the value is too small, the UINT_MIN value (0) is returned. In the case of a NaN result, (0) is returned.

In some examples, execution of a vector converts FP16 to signed integer byte using truncation instruction (e.g., opcode mnemonic VCVTTPH2IBS) converts half-precision floating point elements into signed byte integer elements. When a conversion is inexact, floating-point precision exception is raised and a truncated (round toward zero) result is returned. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked then, if the value is too big, the INT_MAX value (2{circumflex over ( )}(w−1)−1, where w represents the number of bits in the destination format) is returned. When the value is too small, the INT_MIN value (2{circumflex over ( )}(w−1)) is returned. In the case of a NaN result, (0) is returned.

In some examples, execution of a vector converts FP16 to unsigned integer byte using truncation instruction (e.g., opcode mnemonic VCVTTPH2IUBS) converts half-precision floating point elements into un-signed byte integer elements. When a conversion is inexact, floating-point precision exception is raised and a truncated (round toward zero) result is returned. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked then, if the value is too big, the UINT_MAX value (2{circumflex over ( )}w−1, where w represents the number of bits in the destination format) is returned. When the value is too small, the UINT_MIN value (0) is returned. In the case of a NaN result, (0) is returned.

In some examples, FP32 downconvert instructions convert four, eight or sixteen packed single-precision floating-point values in the source operand to four, eight or sixteen signed or unsigned byte integers in the destination operand. The location of downconverted 8-bit result within 32-bit elements is determined by an immediate in some examples. The other bits are zeroed.

In some examples, execution of a vector converts FP32 to signed integer byte instruction (e.g., opcode mnemonic VCVTPS2IBS) converts single-precision floating point elements into signed byte integer elements. When a conversion is inexact, floating-point precision exception is raised and the value returned is rounded according to the rounding control bits in a control register (e.g., MXCSR register) or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked then, if the value is too big, the INT_MAX value (2{circumflex over ( )}(w−1)-1, where w represents the number of bits in the destination format) is returned. When the value is too small, the INT_MIN value (2{circumflex over ( )}(w−1)) is returned. In the case of a NaN result, (0) is returned.

In some examples, execution of a vector converts FP32 to unsigned integer byte instruction (e.g., opcode mnemonic VCVTPS2IUBS) converts single-precision floating point elements into un-signed byte integer elements. When a conversion is inexact, floating-point precision exception is raised and the value returned is rounded according to the rounding control bits in a control register (e.g., MXCSR register) or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked then, if the value is too big, the UINT_MAX value (2{circumflex over ( )}w−1, where w represents the number of bits in the destination format) is returned. When the value is too small, the UINT_MIN value (0) is returned. In the case of a NaN result, (0) is returned.

In some examples, execution of a vector converts FP32 to signed integer byte using truncation instruction (e.g., opcode mnemonic VCVTTPS2IBS) converts single-precision floating point elements into signed byte integer elements. When a conversion is inexact, floating-point precision exception is raised and a truncated (round toward zero) result is returned. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked then, if the value is too big, the INT_MAX value (2{circumflex over ( )}(w−1)−1, where w represents the number of bits in the destination format) is returned. When the value is too small, the INT_MIN value (2{circumflex over ( )}(w−1)) is returned. In the case of a NaN result, (0) is returned.

In some examples, execution of a vector converts FP32 to unsigned integer byte using truncation instruction (e.g., opcode mnemonic VCVTTPS2IUBS) converts single-precision floating point elements into un-signed byte integer elements. When a conversion is inexact, floating-point precision exception is raised and a truncated (round toward zero) result is returned. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked then, if the value is too big, the UINT_MAX value (2{circumflex over ( )}w−1, where w represents the number of bits in the destination format) is returned. When the value is too small, the UINT_MIN value (0) is returned. In the case of a NaN result, (0) is returned.

FIG.1illustrates different number representation formats. In this illustration, the formats are in little endian format, however, in some embodiments, a big endian format is used. The FP32 format101has a sign bit (S), an 8-bit exponent, and a 23-bit fraction (a 24-bit mantissa that uses an implicit bit). The FP16 format103has a sign bit (S), a 5-bit exponent, and a 10-bit fraction. The BF16 format105has a sign bit (S), an 8-bit exponent, and a 7-bit fraction.

In contrast to the IEEE 754-standardized 16-bit (FP16) variant, BF16 does not compromise on range when compared to FP32. FP32 numbers have 8 bits of exponent and 24 bits of mantissa (including the one implicit). BF16 cuts 16 bits from the 24-bit FP32 mantissa to create a 16-bit floating point datatype. In contrast FP16 roughly halves the FP32 mantissa to 10 explicit bits and reduces the exponent to 5 bits to fit the 16-bit datatype envelope.

Although BF16 offers less precision than FP16, it is typically better suited to support deep learning tasks. FP16's range is not enough to accomplish deep learning training out-of-the-box due to its limited range. BF16 does not suffer from this issue and the limited precision may actually help to generalize the learned weights in the neural net training task. In other words, lower precision can be seen as offering a built-in regularization property.

As shown, the IEEE and BF16 formats have a fixed number of bits allocated to the fraction (or mantissa which is the fraction bits+1 bit) and exponent fields. Additionally, in some examples, a fixed exponent bias may be provided for a FP16 or BF16 number. As eight bits allows for a small number of mantissa and exponent bits than FP16 or BF16 it may be advantageous to have some variance in INT8 formats (e.g., ensure high accuracy and convergence when training machine learning models).

A signed 8-bit integer format107has a 7-bit data value and one bit (the most significant for a sign). An unsigned 8-bit integer format108has an 8-bit data value and no bit for a sign.

In machine learning, different parameters, namely weights, gradients and activations, have different precision and range requirements to achieve high training accuracy and/or convergence. This allows for different allocations of the number of exponent and fraction (mantissa bits) or integer type depending on the parameter being represented.

FIG.2illustrates an example execution of an instruction to downconvert a floating point value to INT8. As noted above, this class of instructions may be called FP2INT8 instructions. In this illustration, the FP2INT8 instruction has a packed data source201that includes a plurality of FP packed data elements. Depending on the instruction, the elements are FP32, FP16, or BF16. The size of the packed data source may be one or more of: 64-bit, 128-bit, 256-bit, 512-bit, 1028-bit, etc. In some examples, the packed data source201is a register. In some examples, the packed data source201is a memory location.

The packed data source201is fed into downconvert circuitry213of execution circuitry209to be downconverted. FP32 data is converted using FP32 to INT8 circuitry214, FP16 data is converted using FP16 to INT8 circuitry216, and BF16 data is converted using BF16 to INT8 circuitry215. In some examples, broadcast circuitry211broadcasts data from a least significant data element position (e.g., [0]) to be operated on. In some examples, all of the data element positions are fed to downconvert circuitry213.

In some examples, the execution circuitry209is configured according to control information205to use one or more of the described components instead of other execution circuits219. The control information may be provided by a decoder, scheduler, etc. In some embodiments, this execution of the instruction uses a round to nearest (even) rounding mode. In some embodiments, output denormals are always flushed to zero and input denormals are always treated as zero. In some examples, the execution uses truncation.

A packed data destination231is written to store the resultant INT8 values in corresponding packed data elements as the packed data source201. A location selector204within each packed data element position of the packed data destination231is provided to the writeback circuitry221to determine the location within each data element position of where to store the INT8 value. In some examples, an immediate provides this location. For example, a value of 0 writes to the least significant position (e.g., position[0]), a value of 1 to the next most least significant position (e.g., position [1]), etc.

The packed data destination231may be a register or memory location.

In some embodiments, when the instruction calls for the use of predication or writemasking, a writemask (or predicate) register241dictates how the resultant INT8 values are stored and/or zeroed using the writemask circuitry221.

FIGS.3(A)-(B) illustrate examples of how INT8 values are stored as a result of an execution of a FP2INT8 instruction.

InFIG.3(A)a packed data source301includes four packed data elements. In this illustration, the data elements are all FP32, but of course other data element sizes may be used.

Each data element position (storing a packed data element) the packed data source301has a corresponding data element position in the packed data destination303. As an INT8 value is smaller than FP32 value, each data element position of the packed data destination303could store 4 INT8 values. However, as noted above, the instruction includes or refers to an indication of where to store an INT8 value in the larger packed data elements of the packed data destination303. In this example, the INT8 values are stored in the second most least significant 8-bit location (e.g., position[1]). Other 8-bit positions are zeroed.

InFIG.3(B)a packed data source301includes four packed data elements. In this illustration, the data elements are all FP32, but of course other data element sizes may be used.

Each data element position (storing a packed data element) the packed data source311has a corresponding data element position in the packed data destination313. As an INT8 value is smaller than FP32 value, each data element position of the packed data destination313could store 4 INT8 values. However, as noted above, the instruction includes or refers to an indication of where to store an INT8 value in the larger packed data elements of the packed data destination313. In this example, the INT8 values are to be stored in the third most least significant 8-bit location (e.g., position[2]) of the larger data elements when the writemask315allows for that write and other 8-bit positions are zeroed. Note that in this example, one data element position of the packed data destination313is to not be written and all of the 8-bit positions are zeroed (zero masking is used).

An embodiment of a format for a FP2INT8 instruction is FP2INT8_OPCODE DST{k}, SRC IMM. In some embodiments, FP2INT8_OPCODE is the mnemonic. Several opcode mnemonics have been detailed above. DST and SRC are fields for the destination and source operands identifiers respectively such as packed data registers and/or memory. In some examples, the opcode is provided by at least field1903. In some examples, the immediate is provided by immediate value1909. In some examples, the DST is provided by2044and one or more bits of a prefix1901. In some examples, the SRC is provided by2046and one or more bits of a prefix1901and/or SIB byte information2004. In some examples, one or more of the instruction variants take place under the use of a writemask provided by a prefix such as prefix1901(C).

FIG.4illustrates examples of method performed to process a FP2INT8 instruction. In some examples, emulation or binary translation are utilized. For example, a processor core as shown inFIG.16(B), a pipeline, and/or emulation/translation layer perform aspects of this method.

An instance of a single instruction of a first instruction set architecture is fetched at401. In some examples, the instance of the single instruction at least includes fields for an opcode, an identification of location of a packed data source operand, an identification of location of a packed data destination operand, and an indication of a location in each packed data element of the packed data destination to store an INT8 value, wherein the opcode is to indicate conversion circuitry is to convert data of each packed data element of the packed data source operand to an int8 value and provide the INT8 value for storage in the identified location of a corresponding packed data element of the packed data destination.

In some examples, the packed data elements of the source operand are FP32. In some examples, the packed data elements of the source operand are FP16. In some examples, the packed data elements of the source operand are BF16.

In some examples, the INT8 values are signed. In some examples, the INT8 values are unsigned.

In some examples, the identified location is provided by an immediate. In some examples, the identified location is provided by a register.

In some examples, the instruction further includes a prefix. In some examples, the prefix provides aspects of the identification of location of a packed data source operand and/the identification of location of a packed data destination operand. In some examples, the prefix includes an indication of writemask register to utilize during the write (storage) of INT8 values.

In some examples, when a converted integer value is too large to be represented a maximum value is stored. In some examples, when a converted integer value is too small to be represented a minimum value is stored. In some examples, when a NaN is generated a 0 is stored. In some examples, when a conversion is inexact, the INT8 value is a truncated (round toward zero) value.

In some examples, a rounding mode is indicated by the opcode of the instruction. In some examples, a rounding mode is provided by control bits of a control register.

In some examples, the fetched single instruction of the first instruction set architecture is translated into one or more instructions of a second instruction set architecture at402. This translation is performed by a translation and/or emulation layer of software in some examples. In some examples, this translation is performed by an instruction converter3012as shown inFIG.30. In some examples, the translation is performed by hardware translation circuitry.

The instance of the single instruction, or the one or more translated instructions of the second instruction set architecture, is/are decoded at403. For example, the translated instruction(s) is/are decoded by decoder circuitry such as decode circuitry1640, etc. detailed herein. In some examples, the operations of translation and decoding at402and403are merged.

Data values associated with the source operand of the decoded instruction are retrieved at405. For example, when a source operand is stored in memory, the data from the indicated memory location is retrieved.

At407, the decoded instruction(s) is/are executed by execution circuitry (hardware) such as execution circuitry detailed above, execution circuitry detailed above, execution cluster(s)1660shown inFIG.16(B), execution circuitry ofFIG.8, etc. to perform the operation(s) indicated by the opcode of the single instruction of the first instruction set architecture to convert data of each packed data element of the packed data source operand to an int8 value and store the INT8 value in the identified location of a corresponding packed data element of the packed data destination.

In some examples, the packed data elements of the source operand are FP32. In some examples, the packed data elements of the source operand are FP16. In some examples, the packed data elements of the source operand are BF16.

In some examples, the INT8 values are signed. In some examples, the INT8 values are unsigned.

In some examples, the identified location is provided by an immediate. In some examples, the identified location is provided by a register.

In some examples, the instruction further includes a prefix. In some examples, the prefix provides aspects of the identification of location of a packed data source operand and/the identification of location of a packed data destination operand. In some examples, the prefix includes an indication of writemask register to utilize during the write (storage) of INT8 values.

In some examples, when a converted integer value is too large to be represented a maximum value is stored. In some examples, when a converted integer value is too small to be represented a minimum value is stored. In some examples, when a NaN is generated a 0 is stored. In some examples, when a conversion is inexact, the INT8 value is a truncated (round toward zero) value.

In some examples, a rounding mode is indicated by the opcode of the instruction. In some examples, a rounding mode is provided by control bits of a control register.

Examples of pseudocode representing execution acts to be performed by downconvert execution circuitry and/or writeback circuitry are shown inFIGS.5(A)-(D),6(A)-(D), and7(A)-(D).

In the example pseudocode there is a function for conversion. Detailed below is an example of some of those functions:

SrcFmt - can be one of {bf16, fp16, fp32};//Source formatRM - can be one of {RNE, ToZero}// rounding mode: round to nearest even (RNE) or round to 0define SrcFmt_to_signed_byte_saturate_RM(SrcFmt):TMP := cvt_saturate_SrcFmt_Floating_Point_To_signed_int8_RM(SrcFmt)//Convert source to signed/* Signed saturation arithmetic - With signed saturation arithmetic,out-of-range results are limited to the representable range of signedintegers for the integer size being operated on. For example, if positiveoverflow occurs when operating on signed word integers, the result is“saturated” to 7FH, which is the largest positive integer that can berepresented in 8 bits; if negative overflow occurs, the result is saturatedto 80H. */Return TMPdefine SrcFmt_to_unsigned_byte_saturate_RM(SrcFmt):if (fp32 < 0):TMP := 0else:TMP :=cvt_saturate_SrcFmt_Floating_Point_To_unsigned_int8_RM(SrcFmt)//Convert source to unsigned/* Unsigned saturation arithmetic - With unsigned saturationarithmetic, out-of-range results are limited to the representablerange of unsigned integers for the integer size. So, positiveoverflow when operating on unsigned byte integers results in FFHbeing returned and negative overflow results in 00H beingreturned.*/Return TMP

In some examples, the instruction is committed or retired at409.

FIG.8illustrates examples of computing hardware to process at least FP2INT8 instruction. As illustrated, storage803stores a FP2INT8 instruction801to be executed. Other instructions802may also be stored.

The instruction801is received by decoder circuitry805. For example, the decoder circuitry805receives this instruction from fetch circuitry (not shown). The instruction may be in any suitable format, such as that describe with reference toFIG.19, etc. below.

More detailed examples of at least one instruction format for the instruction will be detailed later. The decoder circuitry805decodes the instruction into one or more operations. In some examples, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry809). The decoder circuitry805also decodes instruction prefixes.

In some examples, register renaming, register allocation, and/or scheduling circuitry807provides functionality for one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some examples), 2) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded instruction for execution by execution circuitry out of an instruction pool (e.g., using a reservation station in some examples).

Registers (register file) and/or memory808store data as operands of the instruction to be operated by execution circuitry809. Example register types include packed data registers, general purpose registers (GPRs), and floating-point registers.

Execution circuitry809executes the decoded instruction. Example detailed execution circuitry includes execution circuitry809shown inFIG.8, and execution cluster(s)1660shown inFIG.16(B), etc.

In some examples, retirement/write back circuitry811architecturally commits the destination register into the registers or memory808and retires the instruction.

Some examples utilize instruction formats described herein. Some examples are implemented in one or more computer architectures, cores, accelerators, etc. Some examples are generated or are IP cores. Some examples utilize emulation and/or translation.

Example Architectures

Detailed below are descriptions of example computer architectures. Other system designs and configurations known in the arts for laptop, desktop, and handheld personal computers (PC)s, personal digital assistants, engineering workstations, servers, disaggregated servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand-held devices, and various other electronic devices, are also suitable. In general, a variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

Example Systems

FIG.9illustrates an example computing system. Multiprocessor system900is an interfaced system and includes a plurality of processors or cores including a first processor970and a second processor980coupled via an interface950such as a point-to-point (P-P) interconnect, a fabric, and/or bus. In some examples, the first processor970and the second processor980are homogeneous. In some examples, first processor970and the second processor980are heterogenous. Though the example system900is shown to have two processors, the system may have three or more processors, or may be a single processor system. In some examples, the computing system is a system on a chip (SoC).

Processors970and980are shown including integrated memory controller (IMC) circuitry972and982, respectively. Processor970also includes interface circuits976and978; similarly, second processor980includes interface circuits986and988. Processors970,980may exchange information via the interface950using interface circuits978,988. IMCs972and982couple the processors970,980to respective memories, namely a memory932and a memory934, which may be portions of main memory locally attached to the respective processors.

Processors970,980may each exchange information with a network interface (NW I/F)990via individual interfaces952,954using interface circuits976,994,986,998. The network interface990(e.g., one or more of an interconnect, bus, and/or fabric, and in some examples is a chipset) may optionally exchange information with a coprocessor938via an interface circuit992. In some examples, the coprocessor938is a special-purpose processor, such as, for example, a high-throughput processor, a network or communication processor, compression engine, graphics processor, general purpose graphics processing unit (GPGPU), neural-network processing unit (NPU), embedded processor, or the like.

Network interface990may be coupled to a first interface916via interface circuit996. In some examples, first interface916may be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Express interconnect or another I/O interconnect. In some examples, first interface916is coupled to a power control unit (PCU)917, which may include circuitry, software, and/or firmware to perform power management operations with regard to the processors970,980and/or co-processor938. PCU917provides control information to a voltage regulator (not shown) to cause the voltage regulator to generate the appropriate regulated voltage. PCU917also provides control information to control the operating voltage generated. In various examples, PCU917may include a variety of power management logic units (circuitry) to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or power management source or system software).

PCU917is illustrated as being present as logic separate from the processor970and/or processor980. In other cases, PCU917may execute on a given one or more of cores (not shown) of processor970or980. In some cases, PCU917may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code, sometimes referred to as P-code. In yet other examples, power management operations to be performed by PCU917may be implemented externally to a processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other examples, power management operations to be performed by PCU917may be implemented within BIOS or other system software.

Various I/O devices914may be coupled to first interface916, along with a bus bridge918which couples first interface916to a second interface920. In some examples, one or more additional processor(s)915, such as coprocessors, high throughput many integrated core (MIC) processors, GPGPUs, accelerators (such as graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays (FPGAs), or any other processor, are coupled to first interface916. In some examples, second interface920may be a low pin count (LPC) interface. Various devices may be coupled to second interface920including, for example, a keyboard and/or mouse922, communication devices927and storage circuitry928. Storage circuitry928may be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device which may include instructions/code and data930and may implement the storage803in some examples. Further, an audio I/O924may be coupled to second interface920. Note that other architectures than the point-to-point architecture described above are possible. For example, instead of the point-to-point architecture, a system such as multiprocessor system900may implement a multi-drop interface or other such architecture.

Example Core Architectures, Processors, and Computer Architectures.

FIG.10illustrates a block diagram of an example processor and/or SoC1000that may have one or more cores and an integrated memory controller. The solid lined boxes illustrate a processor1000with a single core1002(A), system agent unit circuitry1010, and a set of one or more interface controller unit(s) circuitry1016, while the optional addition of the dashed lined boxes illustrates an alternative processor1000with multiple cores1002(A)-(N), a set of one or more integrated memory controller unit(s) circuitry1014in the system agent unit circuitry1010, and special purpose logic1008, as well as a set of one or more interface controller units circuitry1016. Note that the processor1000may be one of the processors970or980, or co-processor938or915ofFIG.9.

A memory hierarchy includes one or more levels of cache unit(s) circuitry1004(A)-(N) within the cores1002(A)-(N), a set of one or more shared cache unit(s) circuitry1006, and external memory (not shown) coupled to the set of integrated memory controller unit(s) circuitry1014. The set of one or more shared cache unit(s) circuitry1006may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, such as a last level cache (LLC), and/or combinations thereof. While in some examples interface network circuitry1012(e.g., a ring interconnect) interfaces the special purpose logic1008(e.g., integrated graphics logic), the set of shared cache unit(s) circuitry1006, and the system agent unit circuitry1010, alternative examples use any number of well-known techniques for interfacing such units. In some examples, coherency is maintained between one or more of the shared cache unit(s) circuitry1006and cores1002(A)-(N). In some examples, interface controller units circuitry1016couple the cores1002to one or more other devices1018such as one or more I/O devices, storage, one or more communication devices (e.g., wireless networking, wired networking, etc.), etc.

In some examples, one or more of the cores1002(A)-(N) are capable of multi-threading. The system agent unit circuitry1010includes those components coordinating and operating cores1002(A)-(N). The system agent unit circuitry1010may include, for example, power control unit (PCU) circuitry and/or display unit circuitry (not shown). The PCU may be or may include logic and components needed for regulating the power state of the cores1002(A)-(N) and/or the special purpose logic1008(e.g., integrated graphics logic). The display unit circuitry is for driving one or more externally connected displays.

The cores1002(A)-(N) may be homogenous in terms of instruction set architecture (ISA). Alternatively, the cores1002(A)-(N) may be heterogeneous in terms of ISA; that is, a subset of the cores1002(A)-(N) may be capable of executing an ISA, while other cores may be capable of executing only a subset of that ISA or another ISA.

FIG.11is a block diagram illustrating a computing system1100configured to implement one or more aspects of the examples described herein. The computing system1100includes a processing subsystem1101having one or more processor(s)1102and a system memory1104communicating via an interconnection path that may include a memory hub1105. The memory hub1105may be a separate component within a chipset component or may be integrated within the one or more processor(s)1102. The memory hub1105couples with an I/O subsystem1111via a communication link1106. The I/O subsystem1111includes an I/O hub1107that can enable the computing system1100to receive input from one or more input device(s)1108. Additionally, the I/O hub1107can enable a display controller, which may be included in the one or more processor(s)1102, to provide outputs to one or more display device(s)1110A. In some examples the one or more display device(s)1110A coupled with the I/O hub1107can include a local, internal, or embedded display device.

The processing subsystem1101, for example, includes one or more parallel processor(s)1112coupled to memory hub1105via a bus or other communication link1113. The communication link1113may be one of any number of standards-based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor specific communications interface or communications fabric. The one or more parallel processor(s)1112may form a computationally focused parallel or vector processing system that can include a large number of processing cores and/or processing clusters, such as a many integrated core (MIC) processor. For example, the one or more parallel processor(s)1112form a graphics processing subsystem that can output pixels to one of the one or more display device(s)1110A coupled via the I/O hub1107. The one or more parallel processor(s)1112can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s)1110B.

Within the I/O subsystem1111, a system storage unit1114can connect to the I/O hub1107to provide a storage mechanism for the computing system1100. An I/O switch1116can be used to provide an interface mechanism to enable connections between the I/O hub1107and other components, such as a network adapter1118and/or wireless network adapter1119that may be integrated into the platform, and various other devices that can be added via one or more add-in device(s)1120. The add-in device(s)1120may also include, for example, one or more external graphics processor devices, graphics cards, and/or compute accelerators. The network adapter1118can be an Ethernet adapter or another wired network adapter. The wireless network adapter1119can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.

The computing system1100can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, which may also be connected to the I/O hub1107. Communication paths interconnecting the various components inFIG.11may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or any other bus or point-to-point communication interfaces and/or protocol(s), such as the NVLink high-speed interconnect, Compute Express Link™ (CXL™) (e.g., CXL.mem), Infinity Fabric (IF), Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Intel QuickPath Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omnipath, HyperTransport, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, and variations thereof, or wired or wireless interconnect protocols known in the art. In some examples, data can be copied or stored to virtualized storage nodes using a protocol such as non-volatile memory express (NVMe) over Fabrics (NVMe-oF) or NVMe.

The one or more parallel processor(s)1112may incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). Alternatively, or additionally, the one or more parallel processor(s)1112can incorporate circuitry optimized for general purpose processing, while preserving the underlying computational architecture, described in greater detail herein. Components of the computing system1100may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processor(s)1112, memory hub1105, processor(s)1102, and I/O hub1107can be integrated into a system on chip (SoC) integrated circuit. Alternatively, the components of the computing system1100can be integrated into a single package to form a system in package (SIP) configuration. In some examples at least a portion of the components of the computing system1100can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

It will be appreciated that the computing system1100shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s)1102, and the number of parallel processor(s)1112, may be modified as desired. For instance, system memory1104can be connected to the processor(s)1102directly rather than through a bridge, while other devices communicate with system memory1104via the memory hub1105and the processor(s)1102. In other alternative topologies, the parallel processor(s)1112are connected to the I/O hub1107or directly to one of the one or more processor(s)1102, rather than to the memory hub1105. In other examples, the I/O hub1107and memory hub1105may be integrated into a single chip. It is also possible that two or more sets of processor(s)1102are attached via multiple sockets, which can couple with two or more instances of the parallel processor(s)1112.

Some of the particular components shown herein are optional and may not be included in all implementations of the computing system1100. For example, any number of add-in cards or peripherals may be supported, or some components may be eliminated. Furthermore, some architectures may use different terminology for components similar to those illustrated inFIG.11. For example, the memory hub1105may be referred to as a Northbridge in some architectures, while the I/O hub1107may be referred to as a Southbridge.

FIG.12Aillustrates a parallel processor1200. The parallel processor1200may be a GPU, GPGPU or the like as described herein. The various components of the parallel processor1200may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGA). The illustrated parallel processor1200may be one or more of the parallel processor(s)1112shown inFIG.11.

The parallel processor1200includes a parallel processing unit1202. The parallel processing unit includes an I/O unit1204that enables communication with other devices, including other instances of the parallel processing unit1202. The I/O unit1204may be directly connected to other devices. For instance, the I/O unit1204connects with other devices via the use of a hub or switch interface, such as memory hub1105. The connections between the memory hub1105and the I/O unit1204form a communication link1113. Within the parallel processing unit1202, the I/O unit1204connects with a host interface1206and a memory crossbar1216, where the host interface1206receives commands directed to performing processing operations and the memory crossbar1216receives commands directed to performing memory operations.

When the host interface1206receives a command buffer via the I/O unit1204, the host interface1206can direct work operations to perform those commands to a front end1208. In some examples the front end1208couples with a scheduler1210, which is configured to distribute commands or other work items to a processing cluster array1212. The scheduler1210ensures that the processing cluster array1212is properly configured and in a valid state before tasks are distributed to the processing clusters of the processing cluster array1212. The scheduler1210may be implemented via firmware logic executing on a microcontroller. The microcontroller implemented scheduler1210is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on the processing cluster array1212. Preferably, the host software can prove workloads for scheduling on the processing cluster array1212via one of multiple graphics processing doorbells. In other examples, polling for new workloads or interrupts can be used to identify or indicate availability of work to perform. The workloads can then be automatically distributed across the processing cluster array1212by the scheduler1210logic within the scheduler microcontroller.

The processing cluster array1212can include up to “N” processing clusters (e.g., cluster1214A, cluster1214B, through cluster1214N). Each cluster1214A-1214N of the processing cluster array1212can execute a large number of concurrent threads. The scheduler1210can allocate work to the clusters1214A-1214N of the processing cluster array1212using various scheduling and/or work distribution algorithms, which may vary depending on the workload arising for each type of program or computation. The scheduling can be handled dynamically by the scheduler1210or can be assisted in part by compiler logic during compilation of program logic configured for execution by the processing cluster array1212. Optionally, different clusters1214A-1214N of the processing cluster array1212can be allocated for processing different types of programs or for performing different types of computations.

The processing cluster array1212can be configured to perform various types of parallel processing operations. For example, the processing cluster array1212is configured to perform general-purpose parallel compute operations. For example, the processing cluster array1212can include logic to execute processing tasks including filtering of video and/or audio data, performing modeling operations, including physics operations, and performing data transformations.

The processing cluster array1212is configured to perform parallel graphics processing operations. In such examples in which the parallel processor1200is configured to perform graphics processing operations, the processing cluster array1212can include additional logic to support the execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. Additionally, the processing cluster array1212can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit1202can transfer data from system memory via the I/O unit1204for processing. During processing the transferred data can be stored to on-chip memory (e.g., parallel processor memory1222) during processing, then written back to system memory.

In examples in which the parallel processing unit1202is used to perform graphics processing, the scheduler1210may be configured to divide the processing workload into approximately equal sized tasks, to better enable distribution of the graphics processing operations to multiple clusters1214A-1214N of the processing cluster array1212. In some of these examples, portions of the processing cluster array1212can be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. Intermediate data produced by one or more of the clusters1214A-1214N may be stored in buffers to allow the intermediate data to be transmitted between clusters1214A-1214N for further processing.

During operation, the processing cluster array1212can receive processing tasks to be executed via the scheduler1210, which receives commands defining processing tasks from front end1208. For graphics processing operations, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). The scheduler1210may be configured to fetch the indices corresponding to the tasks or may receive the indices from the front end1208. The front end1208can be configured to ensure the processing cluster array1212is configured to a valid state before the workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated.

Each of the one or more instances of the parallel processing unit1202can couple with parallel processor memory1222. The parallel processor memory1222can be accessed via the memory crossbar1216, which can receive memory requests from the processing cluster array1212as well as the I/O unit1204. The memory crossbar1216can access the parallel processor memory1222via a memory interface1218. The memory interface1218can include multiple partition units (e.g., partition unit1220A, partition unit1220B, through partition unit1220N) that can each couple to a portion (e.g., memory unit) of parallel processor memory1222. The number of partition units1220A-1220N may be configured to be equal to the number of memory units, such that a first partition unit1220A has a corresponding first memory unit1224A, a second partition unit1220B has a corresponding second memory unit1224B, and an Nth partition unit1220N has a corresponding Nth memory unit1224N. In other examples, the number of partition units1220A-1220N may not be equal to the number of memory devices.

The memory units1224A-1224N can include various types of memory devices, including dynamic random-access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Optionally, the memory units1224A-1224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Persons skilled in the art will appreciate that the specific implementation of the memory units1224A-1224N can vary and can be selected from one of various conventional designs. Render targets, such as frame buffers or texture maps may be stored across the memory units1224A-1224N, allowing partition units1220A-1220N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory1222. In some examples, a local instance of the parallel processor memory1222may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

Optionally, any one of the clusters1214A-1214N of the processing cluster array1212has the ability to process data that will be written to any of the memory units1224A-1224N within parallel processor memory1222. The memory crossbar1216can be configured to transfer the output of each cluster1214A-1214N to any partition unit1220A-1220N or to another cluster1214A-1214N, which can perform additional processing operations on the output. Each cluster1214A-1214N can communicate with the memory interface1218through the memory crossbar1216to read from or write to various external memory devices. In one of the examples with the memory crossbar1216the memory crossbar1216has a connection to the memory interface1218to communicate with the I/O unit1204, as well as a connection to a local instance of the parallel processor memory1222, enabling the processing units within the different processing clusters1214A-1214N to communicate with system memory or other memory that is not local to the parallel processing unit1202. Generally, the memory crossbar1216may, for example, be able to use virtual channels to separate traffic streams between the clusters1214A-1214N and the partition units1220A-1220N.

While a single instance of the parallel processing unit1202is illustrated within the parallel processor1200, any number of instances of the parallel processing unit1202can be included. For example, multiple instances of the parallel processing unit1202can be provided on a single add-in card, or multiple add-in cards can be interconnected. For example, the parallel processor1200can be an add-in device, such as add-in device1120ofFIG.11, which may be a graphics card such as a discrete graphics card that includes one or more GPUs, one or more memory devices, and device-to-device or network or fabric interfaces. The different instances of the parallel processing unit1202can be configured to inter-operate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and/or other configuration differences. Optionally, some instances of the parallel processing unit1202can include higher precision floating point units relative to other instances. Systems incorporating one or more instances of the parallel processing unit1202or the parallel processor1200can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and/or embedded systems. An orchestrator can form composite nodes for workload performance using one or more of: disaggregated processor resources, cache resources, memory resources, storage resources, and networking resources.

In some examples, the parallel processing unit1202can be partitioned into multiple instances. Those multiple instances can be configured to execute workloads associated with different clients in an isolated manner, enabling a pre-determined quality of service to be provided for each client. For example, each cluster1214A-1214N can be compartmentalized and isolated from other clusters, allowing the processing cluster array1212to be divided into multiple compute partitions or instances. In such configuration, workloads that execute on an isolated partition are protected from faults or errors associated with a different workload that executes on a different partition. The partition units1220A-1220N can be configured to enable a dedicated and/or isolated path to memory for the clusters1214A-1214N associated with the respective compute partitions. This datapath isolation enables the compute resources within a partition can communicate with one or more assigned memory units1224A-1224N without being subjected to inference by the activities of other partitions.

FIG.12Bis a block diagram of a partition unit1220. The partition unit1220may be an instance of one of the partition units1220A-1220N ofFIG.12A. As illustrated, the partition unit1220includes an L2 cache1221, a frame buffer interface1225, and a ROP1226(raster operations unit). The L2 cache1221is a read/write cache that is configured to perform load and store operations received from the memory crossbar1216and ROP1226. Read misses and urgent write-back requests are output by L2 cache1221to frame buffer interface1225for processing. Updates can also be sent to the frame buffer via the frame buffer interface1225for processing. In some examples the frame buffer interface1225interfaces with one of the memory units in parallel processor memory, such as the memory units1224A-1224N ofFIG.12A(e.g., within parallel processor memory1222). The partition unit1220may additionally or alternatively also interface with one of the memory units in parallel processor memory via a memory controller (not shown).

In graphics applications, the ROP1226is a processing unit that performs raster operations such as stencil, z test, blending, and the like. The ROP1226then outputs processed graphics data that is stored in graphics memory. In some examples the ROP1226includes or couples with a CODEC1227that includes compression logic to compress depth or color data that is written to memory or the L2 cache1221and decompress depth or color data that is read from memory or the L2 cache1221. The compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. The type of compression that is performed by the CODEC1227can vary based on the statistical characteristics of the data to be compressed. For example, in some examples, delta color compression is performed on depth and color data on a per-tile basis. In some examples the CODEC1227includes compression and decompression logic that can compress and decompress compute data associated with machine learning operations. The CODEC1227can, for example, compress sparse matrix data for sparse machine learning operations. The CODEC1227can also compress sparse matrix data that is encoded in a sparse matrix format (e.g., coordinate list encoding (COO), compressed sparse row (CSR), compress sparse column (CSC), etc.) to generate compressed and encoded sparse matrix data. The compressed and encoded sparse matrix data can be decompressed and/or decoded before being processed by processing elements or the processing elements can be configured to consume compressed, encoded, or compressed and encoded data for processing.

The ROP1226may be included within each processing cluster (e.g., cluster1214A-1214N ofFIG.12A) instead of within the partition unit1220. In such example, read and write requests for pixel data are transmitted over the memory crossbar1216instead of pixel fragment data. The processed graphics data may be displayed on a display device, such as one of the one or more display device(s)1110A-1110B ofFIG.11, routed for further processing by the processor(s)1102, or routed for further processing by one of the processing entities within the parallel processor1200ofFIG.12A.

FIG.12Cis a block diagram of a processing cluster1214within a parallel processing unit. For example, the processing cluster is an instance of one of the processing clusters1214A-1214N ofFIG.12A. The processing cluster1214can be configured to execute many threads in parallel, where the term “thread” refers to an instance of a particular program executing on a particular set of input data. Optionally, single-instruction, multiple-data (SIMD) instruction issue techniques may be used to support parallel execution of a large number of threads without providing multiple independent instruction units. Alternatively, single-instruction, multiple-thread (SIMT) techniques may be used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each one of the processing clusters. Unlike a SIMD execution regime, where all processing engines typically execute identical instructions, SIMT execution allows different threads to more readily follow divergent execution paths through a given thread program. Persons skilled in the art will understand that a SIMD processing regime represents a functional subset of a SIMT processing regime.

Operation of the processing cluster1214can be controlled via a pipeline manager1232that distributes processing tasks to SIMT parallel processors. The pipeline manager1232receives instructions from the scheduler1210ofFIG.12Aand manages execution of those instructions via a graphics multiprocessor1234and/or a texture unit1236. The illustrated graphics multiprocessor1234is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of differing architectures may be included within the processing cluster1214. One or more instances of the graphics multiprocessor1234can be included within a processing cluster1214. The graphics multiprocessor1234can process data and a data crossbar1240can be used to distribute the processed data to one of multiple possible destinations, including other shader units. The pipeline manager1232can facilitate the distribution of processed data by specifying destinations for processed data to be distributed via the data crossbar1240.

Each graphics multiprocessor1234within the processing cluster1214can include an identical set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). The functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. The functional execution logic supports a variety of operations including integer and floating-point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. The same functional-unit hardware could be leveraged to perform different operations and any combination of functional units may be present.

The instructions transmitted to the processing cluster1214constitute a thread. A set of threads executing across the set of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within a graphics multiprocessor1234. A thread group may include fewer threads than the number of processing engines within the graphics multiprocessor1234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during cycles in which that thread group is being processed. A thread group may also include more threads than the number of processing engines within the graphics multiprocessor1234. When the thread group includes more threads than the number of processing engines within the graphics multiprocessor1234, processing can be performed over consecutive clock cycles. Optionally, multiple thread groups can be executed concurrently on the graphics multiprocessor1234.

The graphics multiprocessor1234may include an internal cache memory to perform load and store operations. Optionally, the graphics multiprocessor1234can forego an internal cache and use a cache memory (e.g., level 1 (L1) cache1248) within the processing cluster1214. Each graphics multiprocessor1234also has access to level 2 (L2) caches within the partition units (e.g., partition units1220A-1220N ofFIG.12Athat are shared among all processing clusters1214and may be used to transfer data between threads. The graphics multiprocessor1234may also access off-chip global memory, which can include one or more of local parallel processor memory and/or system memory. Any memory external to the parallel processing unit1202may be used as global memory. Embodiments in which the processing cluster1214includes multiple instances of the graphics multiprocessor1234can share common instructions and data, which may be stored in the L1 cache1248.

Each processing cluster1214may include an MMU1245(memory management unit) that is configured to map virtual addresses into physical addresses. In other examples, one or more instances of the MMU1245may reside within the memory interface1218ofFIG.12A. The MMU1245includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile and optionally a cache line index. The MMU1245may include address translation lookaside buffers (TLB) or caches that may reside within the graphics multiprocessor1234or the L1 cache1248of processing cluster1214. The physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. The cache line index may be used to determine whether a request for a cache line is a hit or miss.

In graphics and computing applications, a processing cluster1214may be configured such that each graphics multiprocessor1234is coupled to a texture unit1236for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering the texture data. Texture data is read from an internal texture L1 cache (not shown) or in some examples from the L1 cache within graphics multiprocessor1234and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor1234outputs processed tasks to the data crossbar1240to provide the processed task to another processing cluster1214for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar1216. A preROP1242(pre-raster operations unit) is configured to receive data from graphics multiprocessor1234, direct data to ROP units, which may be located with partition units as described herein (e.g., partition units1220A-1220N ofFIG.12A). The preROP1242unit can perform optimizations for color blending, organize pixel color data, and perform address translations.

It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units, e.g., graphics multiprocessor1234, texture units1236, preROPs1242, etc., may be included within a processing cluster1214. Further, while only one processing cluster1214is shown, a parallel processing unit as described herein may include any number of instances of the processing cluster1214. Optionally, each processing cluster1214can be configured to operate independently of other processing clusters1214using separate and distinct processing units, L1 caches, L2 caches, etc.

FIG.12Dshows an example of the graphics multiprocessor1234in which the graphics multiprocessor1234couples with the pipeline manager1232of the processing cluster1214. The graphics multiprocessor1234has an execution pipeline including but not limited to an instruction cache1252, an instruction unit1254, an address mapping unit1256, a register file1258, one or more general purpose graphics processing unit (GPGPU) cores1262, and one or more load/store units1266. The GPGPU cores1262and load/store units1266are coupled with cache memory1272and shared memory1270via a memory and cache interconnect1268. The graphics multiprocessor1234may additionally include tensor and/or ray-tracing cores1263that include hardware logic to accelerate matrix and/or ray-tracing operations.

The instruction cache1252may receive a stream of instructions to execute from the pipeline manager1232. The instructions are cached in the instruction cache1252and dispatched for execution by the instruction unit1254. The instruction unit1254can dispatch instructions as thread groups (e.g., warps), with each thread of the thread group assigned to a different execution unit within GPGPU core1262. An instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. The address mapping unit1256can be used to translate addresses in the unified address space into a distinct memory address that can be accessed by the load/store units1266.

The register file1258provides a set of registers for the functional units of the graphics multiprocessor1234. The register file1258provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores1262, load/store units1266) of the graphics multiprocessor1234. The register file1258may be divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file1258. For example, the register file1258may be divided between the different warps being executed by the graphics multiprocessor1234.

The GPGPU cores1262can each include floating point units (FPUs) and/or integer arithmetic logic units (ALUs) that are used to execute instructions of the graphics multiprocessor1234. In some implementations, the GPGPU cores1262can include hardware logic that may otherwise reside within the tensor and/or ray-tracing cores1263. The GPGPU cores1262can be similar in architecture or can differ in architecture. For example and in some examples, a first portion of the GPGPU cores1262include a single precision FPU and an integer ALU while a second portion of the GPGPU cores include a double precision FPU. Optionally, the FPUs can implement the IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. The graphics multiprocessor1234can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. One or more of the GPGPU cores can also include fixed or special function logic.

The GPGPU cores1262may include SIMD logic capable of performing a single instruction on multiple sets of data. Optionally, GPGPU cores1262can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (SPMD) or SIMT architectures. Multiple threads of a program configured for the SIMT execution model can be executed via a single SIMD instruction. For example and in some examples, eight SIMT threads that perform the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

The memory and cache interconnect1268is an interconnect network that connects each of the functional units of the graphics multiprocessor1234to the register file1258and to the shared memory1270. For example, the memory and cache interconnect1268is a crossbar interconnect that allows the load/store unit1266to implement load and store operations between the shared memory1270and the register file1258. The register file1258can operate at the same frequency as the GPGPU cores1262, thus data transfer between the GPGPU cores1262and the register file1258is very low latency. The shared memory1270can be used to enable communication between threads that execute on the functional units within the graphics multiprocessor1234. The cache memory1272can be used as a data cache for example, to cache texture data communicated between the functional units and the texture unit1236. The shared memory1270can also be used as a program managed cached. The shared memory1270and the cache memory1272can couple with the data crossbar1240to enable communication with other components of the processing cluster. Threads executing on the GPGPU cores1262can programmatically store data within the shared memory in addition to the automatically cached data that is stored within the cache memory1272.

FIGS.13A-13Cillustrate additional graphics multiprocessors, according to examples.FIGS.13A-13Billustrate graphics multiprocessors1325,1350, which are related to the graphics multiprocessor1234ofFIG.12Cand may be used in place of one of those. Therefore, the disclosure of any features in combination with the graphics multiprocessor1234herein also discloses a corresponding combination with the graphics multiprocessor(s)1325,1350, but is not limited to such.FIG.13Cillustrates a graphics processing unit (GPU)1380which includes dedicated sets of graphics processing resources arranged into multi-core groups1365A-1365N, which correspond to the graphics multiprocessors1325,1350. The illustrated graphics multiprocessors1325,1350and the multi-core groups1365A-1365N can be streaming multiprocessors (SM) capable of simultaneous execution of a large number of execution threads.

The graphics multiprocessor1325ofFIG.13Aincludes multiple additional instances of execution resource units relative to the graphics multiprocessor1234ofFIG.12D. For example, the graphics multiprocessor1325can include multiple instances of the instruction unit1332A-1332B, register file1334A-1334B, and texture unit(s)1344A-1344B. The graphics multiprocessor1325also includes multiple sets of graphics or compute execution units (e.g., GPGPU core1336A-1336B, tensor core1337A-1337B, ray-tracing core1338A-1338B) and multiple sets of load/store units1340A-1340B. The execution resource units have a common instruction cache1330, texture and/or data cache memory1342, and shared memory1346.

The various components can communicate via an interconnect fabric1327. The interconnect fabric1327may include one or more crossbar switches to enable communication between the various components of the graphics multiprocessor1325. The interconnect fabric1327may be a separate, high-speed network fabric layer upon which each component of the graphics multiprocessor1325is stacked. The components of the graphics multiprocessor1325communicate with remote components via the interconnect fabric1327. For example, the cores1336A-1336B,1337A-1337B, and1338A-1338B can each communicate with shared memory1346via the interconnect fabric1327. The interconnect fabric1327can arbitrate communication within the graphics multiprocessor1325to ensure a fair bandwidth allocation between components.

The graphics multiprocessor1350ofFIG.13Bincludes multiple sets of execution resources1356A-1356D, where each set of execution resource includes multiple instruction units, register files, GPGPU cores, and load store units, as illustrated inFIG.12DandFIG.13A. The execution resources1356A-1356D can work in concert with texture unit(s)1360A-1360D for texture operations, while sharing an instruction cache1354, and shared memory1353. For example, the execution resources1356A-1356D can share an instruction cache1354and shared memory1353, as well as multiple instances of a texture and/or data cache memory1358A-1358B. The various components can communicate via an interconnect fabric1352similar to the interconnect fabric1327ofFIG.13A.

Persons skilled in the art will understand that the architecture described inFIGS.1,12A-12D, and13A-13Bare descriptive and not limiting as to the scope of the present examples. Thus, the techniques described herein may be implemented on any properly configured processing unit, including, without limitation, one or more mobile application processors, one or more desktop or server central processing units (CPUs) including multi-core CPUs, one or more parallel processing units, such as the parallel processing unit1202ofFIG.12A, as well as one or more graphics processors or special purpose processing units, without departure from the scope of the examples described herein.

The parallel processor or GPGPU as described herein may be communicatively coupled to host/processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor/cores over a bus or other interconnect (e.g., a high-speed interconnect such as PCIe, NVLink, or other known protocols, standardized protocols, or proprietary protocols). In other examples, the GPU may be integrated on the same package or chip as the cores and communicatively coupled to the cores over an internal processor bus/interconnect (i.e., internal to the package or chip). Regardless of the manner in which the GPU is connected, the processor cores may allocate work to the GPU in the form of sequences of commands/instructions contained in a work descriptor. The GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions.

FIG.13Cillustrates a graphics processing unit (GPU)1380which includes dedicated sets of graphics processing resources arranged into multi-core groups1365A-1365N. While the details of only a single multi-core group1365A are provided, it will be appreciated that the other multi-core groups1365B-1365N may be equipped with the same or similar sets of graphics processing resources. Details described with respect to the multi-core groups1365A-1365N may also apply to any graphics multiprocessor1234,1325,1350described herein.

As illustrated, a multi-core group1365A may include a set of graphics cores1370, a set of tensor cores1371, and a set of ray tracing cores1372. A scheduler/dispatcher1368schedules and dispatches the graphics threads for execution on the various cores1370,1371,1372. A set of register files1369store operand values used by the cores1370,1371,1372when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and/or floating-point data elements) and tile registers for storing tensor/matrix values. The tile registers may be implemented as combined sets of vector registers.

One or more combined level 1 (L1) caches and shared memory units1373store graphics data such as texture data, vertex data, pixel data, ray data, bounding volume data, etc., locally within each multi-core group1365A. One or more texture units1374can also be used to perform texturing operations, such as texture mapping and sampling. A Level 2 (L2) cache1375shared by all or a subset of the multi-core groups1365A-1365N stores graphics data and/or instructions for multiple concurrent graphics threads. As illustrated, the L2 cache1375may be shared across a plurality of multi-core groups1365A-1365N. One or more memory controllers1367couple the GPU1380to a memory1366which may be a system memory (e.g., DRAM) and/or a dedicated graphics memory (e.g., GDDR6 memory).

Input/output (I/O) circuitry1363couples the GPU1380to one or more I/O devices1362such as digital signal processors (DSPs), network controllers, or user input devices. An on-chip interconnect may be used to couple the I/O devices1362to the GPU1380and memory1366. One or more I/O memory management units (IOMMUs)1364of the I/O circuitry1363couple the I/O devices1362directly to the system memory1366. Optionally, the IOMMU1364manages multiple sets of page tables to map virtual addresses to physical addresses in system memory1366. The I/O devices1362, CPU(s)1361, and GPU(s)1380may then share the same virtual address space.

In one implementation of the IOMMU1364, the IOMMU1364supports virtualization. In this case, it may manage a first set of page tables to map guest/graphics virtual addresses to guest/graphics physical addresses and a second set of page tables to map the guest/graphics physical addresses to system/host physical addresses (e.g., within system memory1366). The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped out on a context switch (e.g., so that the new context is provided with access to the relevant set of page tables). While not illustrated inFIG.13C, each of the cores1370,1371,1372and/or multi-core groups1365A-1365N may include translation lookaside buffers (TLBs) to cache guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

The CPU(s)1361, GPUs1380, and I/O devices1362may be integrated on a single semiconductor chip and/or chip package. The illustrated memory1366may be integrated on the same chip or may be coupled to the memory controllers1367via an off-chip interface. In one implementation, the memory1366comprises GDDR6 memory which shares the same virtual address space as other physical system-level memories, although the underlying principles described herein are not limited to this specific implementation.

The tensor cores1371may include a plurality of execution units specifically designed to perform matrix operations, which are the fundamental compute operation used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and inferencing. The tensor cores1371may perform matrix processing using a variety of operand precisions including single precision floating-point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half-bytes (4 bits). For example, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames, to construct a high-quality final image.

In deep learning implementations, parallel matrix multiplication work may be scheduled for execution on the tensor cores1371. The training of neural networks, in particular, requires a significant number of matrix dot product operations. In order to process an inner-product formulation of an N×N×N matrix multiply, the tensor cores1371may include at least N dot-product processing elements. Before the matrix multiply begins, one entire matrix is loaded into tile registers and at least one column of a second matrix is loaded each cycle for N cycles. Each cycle, there are N dot products that are processed.

Matrix elements may be stored at different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8) and 4-bit half-bytes (e.g., INT4). Different precision modes may be specified for the tensor cores1371to ensure that the most efficient precision is used for different workloads (e.g., such as inferencing workloads which can tolerate quantization to bytes and half-bytes). Supported formats additionally include 64-bit floating point (FP64) and non-IEEE floating point formats such as the bfloat16 format (e.g., Brain floating point), a 16-bit floating point format with one sign bit, eight exponent bits, and eight significand bits, of which seven are explicitly stored. One example includes support for a reduced precision tensor-float (TF32) mode, which performs computations using the range of FP32 (8-bits) and the precision of FP16 (10-bits). Reduced precision TF32 operations can be performed on FP32 inputs and produce FP32 outputs at higher performance relative to FP32 and increased precision relative to FP16. In some examples, one or more 8-bit floating point formats (INT8) are supported.

In some examples the tensor cores1371support a sparse mode of operation for matrices in which the vast majority of values are zero. The tensor cores1371include support for sparse input matrices that are encoded in a sparse matrix representation (e.g., coordinate list encoding (COO), compressed sparse row (CSR), compress sparse column (CSC), etc.). The tensor cores1371also include support for compressed sparse matrix representations in the event that the sparse matrix representation may be further compressed. Compressed, encoded, and/or compressed and encoded matrix data, along with associated compression and/or encoding metadata, can be read by the tensor cores1371and the non-zero values can be extracted. For example, for a given input matrix A, a non-zero value can be loaded from the compressed and/or encoded representation of at least a portion of matrix A. Based on the location in matrix A for the non-zero value, which may be determined from index or coordinate metadata associated with the non-zero value, a corresponding value in input matrix B may be loaded. Depending on the operation to be performed (e.g., multiply), the load of the value from input matrix B may be bypassed if the corresponding value is a zero value. In some examples, the pairings of values for certain operations, such as multiply operations, may be pre-scanned by scheduler logic and only operations between non-zero inputs are scheduled. Depending on the dimensions of matrix A and matrix B and the operation to be performed, output matrix C may be dense or sparse. Where output matrix C is sparse and depending on the configuration of the tensor cores1371, output matrix C may be output in a compressed format, a sparse encoding, or a compressed sparse encoding.

The ray tracing cores1372may accelerate ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, the ray tracing cores1372may include ray traversal/intersection circuitry for performing ray traversal using bounding volume hierarchies (BVHs) and identifying intersections between rays and primitives enclosed within the BVH volumes. The ray tracing cores1372may also include circuitry for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing cores1372perform traversal and intersection operations in concert with the image denoising techniques described herein, at least a portion of which may be executed on the tensor cores1371. For example, the tensor cores1371may implement a deep learning neural network to perform denoising of frames generated by the ray tracing cores1372. However, the CPU(s)1361, graphics cores1370, and/or ray tracing cores1372may also implement all or a portion of the denoising and/or deep learning algorithms.

In addition, as described above, a distributed approach to denoising may be employed in which the GPU1380is in a computing device coupled to other computing devices over a network or high-speed interconnect. In this distributed approach, the interconnected computing devices may share neural network learning/training data to improve the speed with which the overall system learns to perform denoising for different types of image frames and/or different graphics applications.

The ray tracing cores1372may process all BVH traversal and/or ray-primitive intersections, saving the graphics cores1370from being overloaded with thousands of instructions per ray. For example, each ray tracing core1372includes a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and/or a second set of specialized circuitry for performing the ray-triangle intersection tests (e.g., intersecting rays which have been traversed). Thus, for example, the multi-core group1365A can simply launch a ray probe, and the ray tracing cores1372independently perform ray traversal and intersection and return hit data (e.g., a hit, no hit, multiple hits, etc.) to the thread context. The other cores1370,1371are freed to perform other graphics or compute work while the ray tracing cores1372perform the traversal and intersection operations.

Optionally, each ray tracing core1372may include a traversal unit to perform BVH testing operations and/or an intersection unit which performs ray-primitive intersection tests. The intersection unit generates a “hit”, “no hit”, or “multiple hit” response, which it provides to the appropriate thread. During the traversal and intersection operations, the execution resources of the other cores (e.g., graphics cores1370and tensor cores1371) are freed to perform other forms of graphics work.

In some examples described below, a hybrid rasterization/ray tracing approach is used in which work is distributed between the graphics cores1370and ray tracing cores1372.

The ray tracing cores1372(and/or other cores1370,1371) may include hardware support for a ray tracing instruction set such as Microsoft's DirectX Ray Tracing (DXR) which includes a DispatchRays command, as well as ray-generation, closest-hit, any-hit, and miss shaders, which enable the assignment of unique sets of shaders and textures for each object. Another ray tracing platform which may be supported by the ray tracing cores1372, graphics cores1370and tensor cores1371is Vulkan API (e.g., Vulkan version 1.1.85 and later). Note, however, that the underlying principles described herein are not limited to any particular ray tracing ISA.

In general, the various cores1372,1371,1370may support a ray tracing instruction set that includes instructions/functions for one or more of ray generation, closest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit, and exceptions. More specifically, some examples includes ray tracing instructions to perform one or more of the following functions:Ray Generation—Ray generation instructions may be executed for each pixel, sample, or other user-defined work assignment.Closest Hit—A closest hit instruction may be executed to locate the closest intersection point of a ray with primitives within a scene.Any Hit—An any hit instruction identifies multiple intersections between a ray and primitives within a scene, potentially to identify a new closest intersection point.Intersection—An intersection instruction performs a ray-primitive intersection test and outputs a result.Per-primitive Bounding box Construction—This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).Miss—Indicates that a ray misses all geometry within a scene, or specified region of a scene.Visit—Indicates the child volumes a ray will traverse.Exceptions—Includes various types of exception handlers (e.g., invoked for various error conditions).

In some examples the ray tracing cores1372may be adapted to accelerate general-purpose compute operations that can be accelerated using computational techniques that are analogous to ray intersection tests. A compute framework can be provided that enables shader programs to be compiled into low level instructions and/or primitives that perform general-purpose compute operations via the ray tracing cores. Exemplary computational problems that can benefit from compute operations performed on the ray tracing cores1372include computations involving beam, wave, ray, or particle propagation within a coordinate space. Interactions associated with that propagation can be computed relative to a geometry or mesh within the coordinate space. For example, computations associated with electromagnetic signal propagation through an environment can be accelerated via the use of instructions or primitives that are executed via the ray tracing cores. Diffraction and reflection of the signals by objects in the environment can be computed as direct ray-tracing analogies.

Ray tracing cores1372can also be used to perform computations that are not directly analogous to ray tracing. For example, mesh projection, mesh refinement, and volume sampling computations can be accelerated using the ray tracing cores1372. Generic coordinate space calculations, such as nearest neighbor calculations can also be performed. For example, the set of points near a given point can be discovered by defining a bounding box in the coordinate space around the point. BVH and ray probe logic within the ray tracing cores1372can then be used to determine the set of point intersections within the bounding box. The intersections constitute the origin point and the nearest neighbors to that origin point. Computations that are performed using the ray tracing cores1372can be performed in parallel with computations performed on the graphics cores1372and tensor cores1371. A shader compiler can be configured to compile a compute shader or other general-purpose graphics processing program into low level primitives that can be parallelized across the graphics cores1370, tensor cores1371, and ray tracing cores1372.

Building larger and larger silicon dies is challenging for a variety of reasons. As silicon dies become larger, manufacturing yields become smaller and process technology requirements for different components may diverge. On the other hand, in order to have a high-performance system, key components should be interconnected by high speed, high bandwidth, low latency interfaces. These contradicting needs pose a challenge to high performance chip development.

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In some examples, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device. Additionally the chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable the interconnection and communication between the different forms of IP within the GPU. The development of IPs on different process may be mixed. This avoids the complexity of converging multiple IPs, especially on a large SoC with several flavors IPs, to the same process.

Enabling the use of multiple process technologies improves the time to market and provides a cost-effective way to create multiple product SKUs. For customers, this means getting products that are more tailored to their requirements in a cost effective and timely manner. Additionally, the disaggregated IPs are more amenable to being power gated independently, components that are not in use on a given workload can be powered off, reducing overall power consumption.

FIG.14shows a parallel compute system1400, according to some examples. In some examples the parallel compute system1400includes a parallel processor1420, which can be a graphics processor or compute accelerator as described herein. The parallel processor1420includes a global logic unit1401, an interface1402, a thread dispatcher1403, a media unit1404, a set of compute units1405A-1405H, and a cache/memory units1406. The global logic unit1401, in some examples, includes global functionality for the parallel processor1420, including device configuration registers, global schedulers, power management logic, and the like. The interface1402can include a front-end interface for the parallel processor1420. The thread dispatcher1403can receive workloads from the interface1402and dispatch threads for the workload to the compute units1405A-1405H. If the workload includes any media operations, at least a portion of those operations can be performed by the media unit1404. The media unit can also offload some operations to the compute units1405A-1405H. The cache/memory units1406can include cache memory (e.g., L3 cache) and local memory (e.g., HBM, GDDR) for the parallel processor1420.

FIGS.15A-15Billustrate a hybrid logical/physical view of a disaggregated parallel processor, according to examples described herein.FIG.15Aillustrates a disaggregated parallel compute system1500.FIG.15Billustrates a chiplet1530of the disaggregated parallel compute system1500.

As shown inFIG.15A, a disaggregated compute system1500can include a parallel processor1520in which the various components of the parallel processor SOC are distributed across multiple chiplets. Each chiplet can be a distinct IP core that is independently designed and configured to communicate with other chiplets via one or more common interfaces. The chiplets include but are not limited to compute chiplets1505, a media chiplet1504, and memory chiplets1506. Each chiplet can be separately manufactured using different process technologies. For example, compute chiplets1505may be manufactured using the smallest or most advanced process technology available at the time of fabrication, while memory chiplets1506or other chiplets (e.g., I/O, networking, etc.) may be manufactured using a larger or less advanced process technologies.

The various chiplets can be bonded to a base die1510and configured to communicate with each other and logic within the base die1510via an interconnect layer1512. In some examples, the base die1510can include global logic1501, which can include scheduler1511and power management1521logic units, an interface1502, a dispatch unit1503, and an interconnect fabric module1508coupled with or integrated with one or more L3 cache banks1509A-1509N. The interconnect fabric1508can be an inter-chiplet fabric that is integrated into the base die1510. Logic chiplets can use the fabric1508to relay messages between the various chiplets. Additionally, L3 cache banks1509A-1509N in the base die and/or L3 cache banks within the memory chiplets1506can cache data read from and transmitted to DRAM chiplets within the memory chiplets1506and to system memory of a host.

In some examples the global logic1501is a microcontroller that can execute firmware to perform scheduler1511and power management1521functionality for the parallel processor1520. The microcontroller that executes the global logic can be tailored for the target use case of the parallel processor1520. The scheduler1511can perform global scheduling operations for the parallel processor1520. The power management1521functionality can be used to enable or disable individual chiplets within the parallel processor when those chiplets are not in use.

The various chiplets of the parallel processor1520can be designed to perform specific functionality that, in existing designs, would be integrated into a single die. A set of compute chiplets1505can include clusters of compute units (e.g., execution units, streaming multiprocessors, etc.) that include programmable logic to execute compute or graphics shader instructions. A media chiplet1504can include hardware logic to accelerate media encode and decode operations. Memory chiplets1506can include volatile memory (e.g., DRAM) and one or more SRAM cache memory banks (e.g., L3 banks).

As shown inFIG.15B, each chiplet1530can include common components and application specific components. Chiplet logic1536within the chiplet1530can include the specific components of the chiplet, such as an array of streaming multiprocessors, compute units, or execution units described herein. The chiplet logic1536can couple with an optional cache or shared local memory1538or can include a cache or shared local memory within the chiplet logic1536. The chiplet1530can include a fabric interconnect node1542that receives commands via the inter-chiplet fabric. Commands and data received via the fabric interconnect node1542can be stored temporarily within an interconnect buffer1539. Data transmitted to and received from the fabric interconnect node1542can be stored in an interconnect cache1540. Power control1532and clock control1534logic can also be included within the chiplet. The power control1532and clock control1534logic can receive configuration commands via the fabric can configure dynamic voltage and frequency scaling for the chiplet1530. In some examples, each chiplet can have an independent clock domain and power domain and can be clock gated and power gated independently of other chiplets.

At least a portion of the components within the illustrated chiplet1530can also be included within logic embedded within the base die1510ofFIG.15A. For example, logic within the base die that communicates with the fabric can include a version of the fabric interconnect node1542. Base die logic that can be independently clock or power gated can include a version of the power control1532and/or clock control1534logic.

Thus, while various examples described herein use the term SOC to describe a device or system having a processor and associated circuitry (e.g., Input/Output (“I/O”) circuitry, power delivery circuitry, memory circuitry, etc.) integrated monolithically into a single Integrated Circuit (“IC”) die, or chip, the present disclosure is not limited in that respect. For example, in various examples of the present disclosure, a device or system can have one or more processors (e.g., one or more processor cores) and associated circuitry (e.g., Input/Output (“I/O”) circuitry, power delivery circuitry, etc.) arranged in a disaggregated collection of discrete dies, tiles and/or chiplets (e.g., one or more discrete processor core die arranged adjacent to one or more other die such as memory die, I/O die, etc.). In such disaggregated devices and systems the various dies, tiles and/or chiplets can be physically and electrically coupled together by a package structure including, for example, various packaging substrates, interposers, active interposers, photonic interposers, interconnect bridges and the like. The disaggregated collection of discrete dies, tiles, and/or chiplets can also be part of a System-on-Package (“SoP”).”

Example Core Architectures—In-Order and Out-of-Order Core Block Diagram.

InFIG.16(A), a processor pipeline1600includes a fetch stage1602, an optional length decoding stage1604, a decode stage1606, an optional allocation (Alloc) stage1608, an optional renaming stage1610, a schedule (also known as a dispatch or issue) stage1612, an optional register read/memory read stage1614, an execute stage1616, a write back/memory write stage1618, an optional exception handling stage1622, and an optional commit stage1624. One or more operations can be performed in each of these processor pipeline stages. For example, during the fetch stage1602, one or more instructions are fetched from instruction memory, and during the decode stage1606, the one or more fetched instructions may be decoded, addresses (e.g., load store unit (LSU) addresses) using forwarded register ports may be generated, and branch forwarding (e.g., immediate offset or a link register (LR)) may be performed. In some examples, the decode stage1606and the register read/memory read stage1614may be combined into one pipeline stage. In some examples, during the execute stage1616, the decoded instructions may be executed, LSU address/data pipelining to an Advanced Microcontroller Bus (AMB) interface may be performed, multiply and add operations may be performed, arithmetic operations with branch results may be performed, etc.

By way of example, the example register renaming, out-of-order issue/execution architecture core ofFIG.16(B)may implement the pipeline1600as follows: 1) the instruction fetch circuitry1638performs the fetch and length decoding stages1602and1604; 2) the decode circuitry1640performs the decode stage1606; 3) the rename/allocator unit circuitry1652performs the allocation stage1608and renaming stage1610; 4) the scheduler(s) circuitry1656performs the schedule stage1612; 5) the physical register file(s) circuitry1658and the memory unit circuitry1670perform the register read/memory read stage1614; the execution cluster(s)1660perform the execute stage1616; 6) the memory unit circuitry1670and the physical register file(s) circuitry1658perform the write back/memory write stage1618; 7) various circuitry may be involved in the exception handling stage1622; and 8) the retirement unit circuitry1654and the physical register file(s) circuitry1658perform the commit stage1624.

FIG.16(B)shows a processor core1690including front-end unit circuitry1630coupled to execution engine unit circuitry1650, and both are coupled to memory unit circuitry1670. The core1690may be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (e.g., opcode mnemonic VLIW) core, or a hybrid or alternative core type. As yet another option, the core1690may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front-end unit circuitry1630may include branch prediction circuitry1632coupled to instruction cache circuitry1634, which is coupled to an instruction translation lookaside buffer (TLB)1636, which is coupled to instruction fetch circuitry1638, which is coupled to decode circuitry1640. In some examples, the instruction cache circuitry1634is included in the memory unit circuitry1670rather than the front-end circuitry1630. The decode circuitry1640(or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode circuitry1640may further include address generation unit (AGU, not shown) circuitry. In some examples, the AGU generates an LSU address using forwarded register ports, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode circuitry1640may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In some examples, the core1690includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in decode circuitry1640or otherwise within the front-end circuitry1630). In some examples, the decode circuitry1640includes a micro-operation (micro-op) or operation cache (not shown) to hold/cache decoded operations, micro-tags, or micro-operations generated during the decode or other stages of the processor pipeline1600. The decode circuitry1640may be coupled to rename/allocator unit circuitry1652in the execution engine circuitry1650.

The execution engine circuitry1650includes the rename/allocator unit circuitry1652coupled to retirement unit circuitry1654and a set of one or more scheduler(s) circuitry1656. The scheduler(s) circuitry1656represents any number of different schedulers, including reservations stations, central instruction window, etc. In some examples, the scheduler(s) circuitry1656can include arithmetic logic unit (ALU) scheduler/scheduling circuitry, ALU queues, address generation unit (AGU) scheduler/scheduling circuitry, AGU queues, etc. The scheduler(s) circuitry1656is coupled to the physical register file(s) circuitry1658. Each of the physical register file(s) circuitry1658represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In some examples, the physical register file(s) circuitry1658includes vector registers unit circuitry, writemask registers unit circuitry, and scalar register unit circuitry. These register units may provide architectural vector registers, vector mask registers, general-purpose registers, etc. The physical register file(s) circuitry1658is coupled to the retirement unit circuitry1654(also known as a retire queue or a retirement queue) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) (ROB(s)) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit circuitry1654and the physical register file(s) circuitry1658are coupled to the execution cluster(s)1660. The execution cluster(s)1660includes a set of one or more execution unit(s) circuitry1662and a set of one or more memory access circuitry1664. The execution unit(s) circuitry1662may perform various arithmetic, logic, floating-point or other types of operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some examples may include a number of execution units or execution unit circuitry dedicated to specific functions or sets of functions, other examples may include only one execution unit circuitry or multiple execution units/execution unit circuitry that all perform all functions. The scheduler(s) circuitry1656, physical register file(s) circuitry1658, and execution cluster(s)1660are shown as being possibly plural because certain examples create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating-point/packed integer/packed floating-point/vector integer/vector floating-point pipeline, and/or a memory access pipeline that each have their own scheduler circuitry, physical register file(s) circuitry, and/or execution cluster—and in the case of a separate memory access pipeline, certain examples are implemented in which only the execution cluster of this pipeline has the memory access unit(s) circuitry1664). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

In some examples, the execution engine unit circuitry1650may perform load store unit (LSU) address/data pipelining to an Advanced Microcontroller Bus (AMB) interface (not shown), and address phase and writeback, data phase load, store, and branches.

The set of memory access circuitry1664is coupled to the memory unit circuitry1670, which includes data TLB circuitry1672coupled to data cache circuitry1674coupled to level 2 (L2) cache circuitry1676. In some examples, the memory access circuitry1664may include load unit circuitry, store address unit circuitry, and store data unit circuitry, each of which is coupled to the data TLB circuitry1672in the memory unit circuitry1670. The instruction cache circuitry1634is further coupled to the level 2 (L2) cache circuitry1676in the memory unit circuitry1670. In some examples, the instruction cache1634and the data cache1674are combined into a single instruction and data cache (not shown) in L2 cache circuitry1676, level 3 (L3) cache circuitry (not shown), and/or main memory. The L2 cache circuitry1676is coupled to one or more other levels of cache and eventually to a main memory.

The core1690may support one or more instructions sets (e.g., the x86 instruction set architecture (optionally with some extensions that have been added with newer versions); the MIPS instruction set architecture; the ARM instruction set architecture (optionally with optional additional extensions such as NEON)), including the instruction(s) described herein. In some examples, the core1690includes logic to support a packed data instruction set architecture extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.

FIG.17illustrates examples of execution unit(s) circuitry, such as execution unit(s) circuitry1662ofFIG.16(B). As illustrated, execution unit(s) circuitry1662may include one or more ALU circuits1701, optional vector/single instruction multiple data (SIMD) circuits1703, load/store circuits1705, branch/jump circuits1707, and/or Floating-point unit (FPU) circuits1709. ALU circuits1701perform integer arithmetic and/or Boolean operations. Vector/SIMD circuits1703perform vector/SIMD operations on packed data (such as SIMD/vector registers). Load/store circuits1705execute load and store instructions to load data from memory into registers or store from registers to memory. Load/store circuits1705may also generate addresses. Branch/jump circuits1707cause a branch or jump to a memory address depending on the instruction. FPU circuits1709perform floating-point arithmetic. The width of the execution unit(s) circuitry1662varies depending upon the example and can range from 16-bit to 1,024-bit, for example. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

Example Register Architecture.

FIG.18is a block diagram of a register architecture1800according to some examples. As illustrated, the register architecture1800includes vector/SIMD registers1810that vary from 128-bit to 1,024 bits width. In some examples, the vector/SIMD registers1810are physically 512-bits and, depending upon the mapping, only some of the lower bits are used. For example, in some examples, the vector/SIMD registers1810are ZMM registers which are 512 bits: the lower 256 bits are used for YMM registers and the lower 128 bits are used for XMM registers. As such, there is an overlay of registers. In some examples, a vector length field selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length. Scalar operations are operations performed on the lowest order data element position in a ZMM/YMM/XMM register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the example.

In some examples, the register architecture1800includes writemask/predicate registers1815. For example, in some examples, there are 8 writemask/predicate registers (sometimes called k0 through k7) that are each 16-bit, 32-bit, 64-bit, or 128-bit in size. Writemask/predicate registers1815may allow for merging (e.g., allowing any set of elements in the destination to be protected from updates during the execution of any operation) and/or zeroing (e.g., zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given writemask/predicate register1815corresponds to a data element position of the destination. In other examples, the writemask/predicate registers1815are scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits per 64-bit vector element).

The register architecture1800includes a plurality of general-purpose registers1825. These registers may be 16-bit, 32-bit, 64-bit, etc. and can be used for scalar operations. In some examples, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

In some examples, the register architecture1800includes scalar floating-point (FP) register file1845which is used for scalar floating-point operations on 32/64/80-bit floating-point data using the x87 instruction set architecture extension or as MMX registers to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.

One or more flag registers1840(e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, compare, and system operations. For example, the one or more flag registers1840may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, the one or more flag registers1840are called program status and control registers.

Segment registers1820contain segment points for use in accessing memory. In some examples, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.

Model specific registers or machine specific registers (MSRs)1835control and report on processor performance. Most MSRs1835handle system-related functions and are not accessible to an application program. For example, MSRs may provide control for one or more of: performance-monitoring counters, debug extensions, memory type range registers, thermal and power management, instruction-specific support, and/or processor feature/mode support. Machine check registers1860consist of control, status, and error reporting MSRs that are used to detect and report on hardware errors. Control register(s)1855(e.g., CR0-CR4) determine the operating mode of a processor (e.g., processor970,980,938,915, and/or1000) and the characteristics of a currently executing task. In some examples, MSRs1835are a subset of control registers1855.

One or more instruction pointer register(s)1830store an instruction pointer value. Debug registers1850control and allow for the monitoring of a processor or core's debugging operations.

Memory (mem) management registers1865specify the locations of data structures used in protected mode memory management. These registers may include a global descriptor table register (GDTR), interrupt descriptor table register (IDTR), task register, and a local descriptor table register (LDTR) register.

Alternative examples may use wider or narrower registers. Additionally, alternative examples may use more, less, or different register files and registers. The register architecture1800may, for example, be used in register file/memory808, or physical register file(s) circuitry1658.

Instruction Set Architectures.

Example Instruction Formats.

FIG.19illustrates examples of an instruction format. As illustrated, an instruction may include multiple components including, but not limited to, one or more fields for: one or more prefixes1901, an opcode1903, addressing information1905(e.g., register identifiers, memory addressing information, etc.), a displacement value1907, and/or an immediate value1909. Note that some instructions utilize some or all the fields of the format whereas others may only use the field for the opcode1903. In some examples, the order illustrated is the order in which these fields are to be encoded, however, it should be appreciated that in other examples these fields may be encoded in a different order, combined, etc.

The prefix(es) field(s)1901, when used, modifies an instruction. In some examples, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), to provide section overrides (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), to perform bus lock operations, and/or to change operand (e.g., 0x66) and address sizes (e.g., 0x67). Certain instructions require a mandatory prefix (e.g., 0x66, 0xF2, 0xF3, etc.). Certain of these prefixes may be considered “legacy” prefixes. Other prefixes, one or more examples of which are detailed herein, indicate, and/or provide further capability, such as specifying particular registers, etc. The other prefixes typically follow the “legacy” prefixes.

The opcode field1903is used to at least partially define the operation to be performed upon a decoding of the instruction. In some examples, a primary opcode encoded in the opcode field1903is one, two, or three bytes in length. In other examples, a primary opcode can be a different length. An additional 3-bit opcode field is sometimes encoded in another field.

The addressing information field1905is used to address one or more operands of the instruction, such as a location in memory or one or more registers.FIG.20illustrates examples of the addressing information field1905. In this illustration, an optional MOD R/M byte2002and an optional Scale, Index, Base (SIB) byte2004are shown. The MOD R/M byte2002and the SIB byte2004are used to encode up to two operands of an instruction, each of which is a direct register or effective memory address. Note that both of these fields are optional in that not all instructions include one or more of these fields. The MOD R/M byte2002includes a MOD field2042, a register (reg) field2044, and R/M field2046.

The content of the MOD field2042distinguishes between memory access and non-memory access modes. In some examples, when the MOD field2042has a binary value of 11 (11b), a register-direct addressing mode is utilized, and otherwise a register-indirect addressing mode is used.

The register field2044may encode either the destination register operand or a source register operand or may encode an opcode extension and not be used to encode any instruction operand. The content of register field2044, directly or through address generation, specifies the locations of a source or destination operand (either in a register or in memory). In some examples, the register field2044is supplemented with an additional bit from a prefix (e.g., prefix1901) to allow for greater addressing.

The R/M field2046may be used to encode an instruction operand that references a memory address or may be used to encode either the destination register operand or a source register operand. Note the R/M field2046may be combined with the MOD field2042to dictate an addressing mode in some examples.

The SIB byte2004includes a scale field2052, an index field2054, and a base field2056to be used in the generation of an address. The scale field2052indicates a scaling factor. The index field2054specifies an index register to use. In some examples, the index field2054is supplemented with an additional bit from a prefix (e.g., prefix1901) to allow for greater addressing. The base field2056specifies a base register to use. In some examples, the base field2056is supplemented with an additional bit from a prefix (e.g., prefix1901) to allow for greater addressing. In practice, the content of the scale field2052allows for the scaling of the content of the index field2054for memory address generation (e.g., for address generation that uses 2scale*index+base).

Some addressing forms utilize a displacement value to generate a memory address. For example, a memory address may be generated according to 2scale*index+base+displacement, index*scale+displacement, r/m+displacement, instruction pointer (RIP/EIP)+displacement, register+displacement, etc. The displacement may be a 1-byte, 2-byte, 4-byte, etc. value. In some examples, the displacement field1907provides this value. Additionally, in some examples, a displacement factor usage is encoded in the MOD field of the addressing information field1905that indicates a compressed displacement scheme for which a displacement value is calculated and stored in the displacement field1907.

In some examples, the immediate value field1909specifies an immediate value for the instruction. An immediate value may be encoded as a 1-byte value, a 2-byte value, a 4-byte value, etc.

FIG.21illustrates examples of a first prefix1901(A). In some examples, the first prefix1901(A) is an example of a REX prefix. Instructions that use this prefix may specify general purpose registers, 64-bit packed data registers (e.g., single instruction, multiple data (SIMD) registers or vector registers), and/or control registers and debug registers (e.g., CR8-CR15and DR8-DR15).

Instructions using the first prefix1901(A) may specify up to three registers using 3-bit fields depending on the format: 1) using the reg field2044and the R/M field2046of the MOD R/M byte2002; 2) using the MOD R/M byte2002with the SIB byte2004including using the reg field2044and the base field2056and index field2054; or 3) using the register field of an opcode.

In the first prefix1901(A), bit positions of the payload byte7:4are set as 0100. Bit position 3 (W) can be used to determine the operand size but may not solely determine operand width. As such, when W=0, the operand size is determined by a code segment descriptor (CS.D) and when W=1, the operand size is 64-bit.

Note that the addition of another bit allows for 16 (24) registers to be addressed, whereas the MOD R/M reg field2044and MOD R/M R/M field2046alone can each only address8registers.

In the first prefix1901(A), bit position 2 (R) may be an extension of the MOD R/M reg field2044and may be used to modify the MOD R/M reg field2044when that field encodes a general-purpose register, a 64-bit packed data register (e.g., a SSE register), or a control or debug register. R is ignored when MOD R/M byte2002specifies other registers or defines an extended opcode.

Bit position 1 (X) may modify the SIB byte index field2054.

Bit position 0 (B) may modify the base in the MOD R/M R/M field2046or the SIB byte base field2056; or it may modify the opcode register field used for accessing general purpose registers (e.g., general purpose registers1825).

FIGS.22(A)-(D) illustrate examples of how the R, X, and B fields of the first prefix1901(A) are used.FIG.22(A)illustrates R and B from the first prefix1901(A) being used to extend the reg field2044and R/M field2046of the MOD R/M byte2002when the SIB byte2004is not used for memory addressing.FIG.22(B)illustrates R and B from the first prefix1901(A) being used to extend the reg field2044and R/M field2046of the MOD R/M byte2002when the SIB byte2004is not used (register-register addressing).FIG.22(C)illustrates R, X, and B from the first prefix1901(A) being used to extend the reg field2044of the MOD R/M byte2002and the index field2054and base field2056when the SIB byte2004being used for memory addressing.FIG.22(D)illustrates B from the first prefix1901(A) being used to extend the reg field2044of the MOD R/M byte2002when a register is encoded in the opcode1903.

FIGS.23(A)-(B) illustrate examples of a second prefix1901(B). In some examples, the second prefix1901(B) is an example of a VEX prefix. The second prefix1901(B) encoding allows instructions to have more than two operands, and allows SIMD vector registers (e.g., vector/SIMD registers1810) to be longer than 64-bits (e.g., 128-bit and 256-bit). The use of the second prefix1901(B) provides for three-operand (or more) syntax. For example, previous two-operand instructions performed operations such as A=A+B, which overwrites a source operand. The use of the second prefix1901(B) enables operands to perform nondestructive operations such as A=B+C.

In some examples, the second prefix1901(B) comes in two forms—a two-byte form and a three-byte form. The two-byte second prefix1901(B) is used mainly for 128-bit, scalar, and some 256-bit instructions; while the three-byte second prefix1901(B) provides a compact replacement of the first prefix1901(A) and 3-byte opcode instructions.

FIG.23(A)illustrates examples of a two-byte form of the second prefix1901(B). In some examples, a format field2301(byte02303) contains the value C5H. In some examples, byte12305includes an “R” value in bit[7]. This value is the complement of the “R” value of the first prefix1901(A). Bit[2] is used to dictate the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector and a value of 1 is a 256-bit vector). Bits[1:0] provide opcode extensionality equivalent to some legacy prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits[6:3] shown as vvvv may be used to: 1) encode the first source register operand, specified in inverted (1s complement) form and valid for instructions with 2 or more source operands; 2) encode the destination register operand, specified in 1s complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

Instructions that use this prefix may use the MOD R/M R/M field2046to encode the instruction operand that references a memory address or encode either the destination register operand or a source register operand.

Instructions that use this prefix may use the MOD R/M reg field2044to encode either the destination register operand or a source register operand, or to be treated as an opcode extension and not used to encode any instruction operand.

For instruction syntax that support four operands, vvvv, the MOD R/M R/M field2046and the MOD R/M reg field2044encode three of the four operands. Bits[7:4] of the immediate value field1909are then used to encode the third source register operand.

FIG.23(B)illustrates examples of a three-byte form of the second prefix1901(B). In some examples, a format field2311(byte02313) contains the value C4H. Byte12315includes in bits[7:5] “R,” “X,” and “B” which are the complements of the same values of the first prefix1901(A). Bits[4:0] of byte12315(shown as mmmmm) include content to encode, as need, one or more implied leading opcode bytes. For example, 00001 implies a 0FH leading opcode, 00010 implies a 0F38H leading opcode, 00011 implies a 0F3AH leading opcode, etc.

Bit[7] of byte22317is used similar to W of the first prefix1901(A) including helping to determine promotable operand sizes. Bit[2] is used to dictate the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector and a value of 1 is a 256-bit vector). Bits[1:0] provide opcode extensionality equivalent to some legacy prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits[6:3], shown as vvvv, may be used to: 1) encode the first source register operand, specified in inverted (1s complement) form and valid for instructions with 2 or more source operands; 2) encode the destination register operand, specified in 1s complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

Instructions that use this prefix may use the MOD R/M R/M field2046to encode the instruction operand that references a memory address or encode either the destination register operand or a source register operand.

Instructions that use this prefix may use the MOD R/M reg field2044to encode either the destination register operand or a source register operand, or to be treated as an opcode extension and not used to encode any instruction operand.

For instruction syntax that support four operands, vvvv, the MOD R/M R/M field2046, and the MOD R/M reg field2044encode three of the four operands. Bits[7:4] of the immediate value field1909are then used to encode the third source register operand.

FIG.24illustrates examples of a third prefix1901(C). In some examples, the third prefix1901(C) is an example of an EVEX prefix. The third prefix1901(C) is a four-byte prefix.

The third prefix1901(C) can encode 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some examples, instructions that utilize a writemask/opmask (see discussion of registers in a previous figure, such asFIG.18) or predication utilize this prefix. Opmask register allow for conditional processing or selection control. Opmask instructions, whose source/destination operands are opmask registers and treat the content of an opmask register as a single value, are encoded using the second prefix1901(B).

The third prefix1901(C) may encode functionality that is specific to instruction classes (e.g., a packed instruction with “load+op” semantic can support embedded broadcast functionality, a floating-point instruction with rounding semantic can support static rounding functionality, a floating-point instruction with non-rounding arithmetic semantic can support “suppress all exceptions” functionality, etc.).

The first byte of the third prefix1901(C) is a format field2411that has a value, in some examples, of62H. Subsequent bytes are referred to as payload bytes2415-2419and collectively form a 24-bit value of P[23:0] providing specific capability in the form of one or more fields (detailed herein).

In some examples, P[1:0] of payload byte2419are identical to the low two mm bits. P[3:2] are reserved in some examples. Bit P[4] (R′) allows access to the high 16 vector register set when combined with P[7] and the MOD R/M reg field2044. P[6] can also provide access to a high 16 vector register when SIB-type addressing is not needed. P[7:5] consist of R, X, and B which are operand specifier modifier bits for vector register, general purpose register, memory addressing and allow access to the next set of 8 registers beyond the low 8 registers when combined with the MOD R/M register field2044and MOD R/M R/M field2046. P[9:8] provide opcode extensionality equivalent to some legacy prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). P[10] in some examples is a fixed value of 1. P[14:11], shown as vvvv, may be used to: 1) encode the first source register operand, specified in inverted (1s complement) form and valid for instructions with 2 or more source operands; 2) encode the destination register operand, specified in 1s complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

P[15] is similar to W of the first prefix1901(A) and second prefix1911(B) and may serve as an opcode extension bit or operand size promotion.

P[18:16] specify the index of a register in the opmask (writemask) registers (e.g., writemask/predicate registers1815). In some examples, the specific value aaa=000 has a special behavior implying no opmask is used for the particular instruction (this may be implemented in a variety of ways including the use of a opmask hardwired to all ones or hardware that bypasses the masking hardware). When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other some examples, preserving the old value of each element of the destination where the corresponding mask bit has a 0. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in some examples, an element of the destination is set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the opmask field allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While examples are described in which the opmask field's content selects one of a number of opmask registers that contains the opmask to be used (and thus the opmask field's content indirectly identifies that masking to be performed), alternative examples instead or additional allow the mask write field's content to directly specify the masking to be performed.

P[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax which can access an upper 16 vector registers using P[19]. P[20] encodes multiple functionalities, which differs across different classes of instructions and can affect the meaning of the vector length/rounding control specifier field (P[22:21]). P[23] indicates support for merging-writemasking (e.g., when set to 0) or support for zeroing and merging-writemasking (e.g., when set to 1).

Example examples of encoding of registers in instructions using the third prefix1901(C) are detailed in the following tables.

Graphics Execution Units

FIGS.25A-25Billustrate thread execution logic2500including an array of processing elements employed in a graphics processor core according to examples described herein. Elements ofFIGS.25A-25Bhaving the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.FIG.25Ais representative of an execution unit within a general-purpose graphics processor, whileFIG.25Bis representative of an execution unit that may be used within a compute accelerator.

As illustrated inFIG.25A, in some examples thread execution logic2500includes a shader processor2502, a thread dispatcher2504, instruction cache2506, a scalable execution unit array including a plurality of execution units2508A-2508N, a sampler2510, shared local memory2511, a data cache2512, and a data port2514. In some examples the scalable execution unit array can dynamically scale by enabling or disabling one or more execution units (e.g., any of execution units2508A,2508B,2508C,2508D, through2508N-1and2508N) based on the computational requirements of a workload. In some examples the included components are interconnected via an interconnect fabric that links to each of the components. In some examples, thread execution logic2500includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache2506, data port2514, sampler2510, and execution units2508A-2508N. In some examples, each execution unit (e.g.2508A) is a stand-alone programmable general-purpose computational unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various examples, the array of execution units2508A-2508N is scalable to include any number individual execution units.

In some examples, the execution units2508A-2508N are primarily used to execute shader programs. A shader processor2502can process the various shader programs and dispatch execution threads associated with the shader programs via a thread dispatcher2504. In some examples the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution unit in the execution units2508A-2508N. For example, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to the thread execution logic for processing. In some examples, thread dispatcher2504can also process runtime thread spawning requests from the executing shader programs.

In some examples, the execution units2508A-2508N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). Each of the execution units2508A-2508N is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment in the face of higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread-state. Execution is multi-issue per clock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. While waiting for data from memory or one of the shared functions, dependency logic within the execution units2508A-2508N causes a waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources may be devoted to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program, including a different vertex shader. Various examples can apply to use execution by use of Single Instruction Multiple Thread (SIMT) as an alternate to use of SIMD or in addition to use of SIMD. Reference to a SIMD core or operation can apply also to SIMT or apply to SIMD in combination with SIMT.

Each execution unit in execution units2508A-2508N operates on arrays of data elements. The number of data elements is the “execution size,” or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some examples, execution units2508A-2508N support integer and floating-point data types.

In some examples one or more execution units can be combined into a fused execution unit2509A-2509N having thread control logic (2507A-2507N) that is common to the fused EUs. Multiple EUs can be fused into an EU group. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary according to examples. Additionally, various SIMD widths can be performed per-EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit2509A-2509N includes at least two execution units. For example, fused execution unit2509A includes a first EU2508A, second EU2508B, and thread control logic2507A that is common to the first EU2508A and the second EU2508B. The thread control logic2507A controls threads executed on the fused graphics execution unit2509A, allowing each EU within the fused execution units2509A-2509N to execute using a common instruction pointer register.

One or more internal instruction caches (e.g.,2506) are included in the thread execution logic2500to cache thread instructions for the execution units. In some examples, one or more data caches (e.g.,2512) are included to cache thread data during thread execution. Threads executing on the execution logic2500can also store explicitly managed data in the shared local memory2511. In some examples, a sampler2510is included to provide texture sampling for 3D operations and media sampling for media operations. In some examples, sampler2510includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send thread initiation requests to thread execution logic2500via thread spawning and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor2502is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In some examples, a pixel shader or fragment shader calculates the values of the various vertex attributes that are to be interpolated across the rasterized object. In some examples, pixel processor logic within the shader processor2502then executes an application programming interface (API)-supplied pixel or fragment shader program. To execute the shader program, the shader processor2502dispatches threads to an execution unit (e.g.,2508A) via thread dispatcher2504. In some examples, shader processor2502uses texture sampling logic in the sampler2510to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing.

In some examples, the data port2514provides a memory access mechanism for the thread execution logic2500to output processed data to memory for further processing on a graphics processor output pipeline. In some examples, the data port2514includes or couples to one or more cache memories (e.g., data cache2512) to cache data for memory access via the data port.

In some examples, the execution logic2500can also include a ray tracer2505that can provide ray tracing acceleration functionality. The ray tracer2505can support a ray tracing instruction set that includes instructions/functions for ray generation.

FIG.25Billustrates exemplary internal details of an execution unit2508, according to examples. A graphics execution unit2508can include an instruction fetch unit2537, a general register file array (GRF)2524, an architectural register file array (ARF)2526, a thread arbiter2522, a send unit2530, a branch unit2532, a set of SIMD floating point units (FPUs)2534, and in some examples a set of dedicated integer SIMD ALUs2535. The GRF2524and ARF2526includes the set of general register files and architecture register files associated with each simultaneous hardware thread that may be active in the graphics execution unit2508. In some examples, per thread architectural state is maintained in the ARF2526, while data used during thread execution is stored in the GRF2524. The execution state of each thread, including the instruction pointers for each thread, can be held in thread-specific registers in the ARF2526.

In some examples the graphics execution unit2508has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and number of registers per execution unit, where execution unit resources are divided across logic used to execute multiple simultaneous threads. The number of logical threads that may be executed by the graphics execution unit2508is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

In some examples, the graphics execution unit2508can co-issue multiple instructions, which may each be different instructions. The thread arbiter2522of the graphics execution unit thread2508can dispatch the instructions to one of the send unit2530, branch unit2532, or SIMD FPU(s)2534for execution. Each execution thread can access128general-purpose registers within the GRF2524, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. In some examples, each execution unit thread has access to 4 Kbytes within the GRF2524, although examples are not so limited, and greater or fewer register resources may be provided in other examples. In some examples the graphics execution unit2508is partitioned into seven hardware threads that can independently perform computational operations, although the number of threads per execution unit can also vary according to examples. For example, in some examples up to 16 hardware threads are supported. In an example in which seven threads may access 4 Kbytes, the GRF2524can store a total of 28 Kbytes. Where16threads may access 4 Kbytes, the GRF2524can store a total of 64 Kbytes. Flexible addressing modes can permit registers to be addressed together to build effectively wider registers or to represent strided rectangular block data structures.

In some examples, memory operations, sampler operations, and other longer-latency system communications are dispatched via “send” instructions that are executed by the message passing send unit2530. In some examples, branch instructions are dispatched to a dedicated branch unit2532to facilitate SIMD divergence and eventual convergence.

In some examples the graphics execution unit2508includes one or more SIMD floating point units (FPU(s))2534to perform floating-point operations. In some examples, the FPU(s)2534also support integer computation. In some examples the FPU(s)2534can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating-point operations. In some examples, at least one of the FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision 64-bit floating-point. In some examples, a set of 8-bit integer SIMD ALUs2535are also present, and may be specifically optimized to perform operations associated with machine learning computations.

In some examples, arrays of multiple instances of the graphics execution unit2508can be instantiated in a graphics sub-core grouping (e.g., a sub-slice). For scalability, product architects can choose the exact number of execution units per sub-core grouping. In some examples the execution unit2508can execute instructions across a plurality of execution channels. In a further example, each thread executed on the graphics execution unit2508is executed on a different channel.

FIG.26illustrates an additional execution unit2600, according to an example. In some examples, the execution unit2600includes a thread control unit2601, a thread state unit2602, an instruction fetch/prefetch unit2603, and an instruction decode unit2604. The execution unit2600additionally includes a register file2606that stores registers that can be assigned to hardware threads within the execution unit. The execution unit2600additionally includes a send unit2607and a branch unit2608. In some examples, the send unit2607and branch unit2608can operate similarly as the send unit2530and a branch unit2532of the graphics execution unit2508ofFIG.25B.

The execution unit2600also includes a compute unit2610that includes multiple different types of functional units. In some examples the compute unit2610includes an ALU unit2611that includes an array of arithmetic logic units. The ALU unit2611can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating point operations. Integer and floating point operations may be performed simultaneously. The compute unit2610can also include a systolic array2612, and a math unit2613. The systolic array2612includes a W wide and D deep network of data processing units that can be used to perform vector or other data-parallel operations in a systolic manner. In some examples the systolic array2612can be configured to perform matrix operations, such as matrix dot product operations. In some examples the systolic array2612support 16-bit floating point operations, as well as 8-bit and 4-bit integer operations. In some examples the systolic array2612can be configured to accelerate machine learning operations. In such examples, the systolic array2612can be configured with support for the bfloat 16-bit floating point format. In some examples, a math unit2613can be included to perform a specific subset of mathematical operations in an efficient and lower-power manner than then ALU unit2611. The math unit2613can include a variant of math logic that may be found in shared function logic of a graphics processing engine provided by other examples (e.g., math logic422of the shared function logic420ofFIG.4). In some examples the math unit2613can be configured to perform 32-bit and 64-bit floating point operations.

The thread control unit2601includes logic to control the execution of threads within the execution unit. The thread control unit2601can include thread arbitration logic to start, stop, and preempt execution of threads within the execution unit2600. The thread state unit2602can be used to store thread state for threads assigned to execute on the execution unit2600. Storing the thread state within the execution unit2600enables the rapid pre-emption of threads when those threads become blocked or idle. The instruction fetch/prefetch unit2603can fetch instructions from an instruction cache of higher level execution logic (e.g., instruction cache2506as inFIG.25A). The instruction fetch/prefetch unit2603can also issue prefetch requests for instructions to be loaded into the instruction cache based on an analysis of currently executing threads. The instruction decode unit2604can be used to decode instructions to be executed by the compute units. In some examples, the instruction decode unit2604can be used as a secondary decoder to decode complex instructions into constituent micro-operations.

The execution unit2600additionally includes a register file2606that can be used by hardware threads executing on the execution unit2600. Registers in the register file2606can be divided across the logic used to execute multiple simultaneous threads within the compute unit2610of the execution unit2600. The number of logical threads that may be executed by the graphics execution unit2600is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of the register file2606can vary across examples based on the number of supported hardware threads. In some examples, register renaming may be used to dynamically allocate registers to hardware threads.

FIG.27is a block diagram illustrating a graphics processor instruction formats2700according to some examples. In one or more example, the graphics processor execution units support an instruction set having instructions in multiple formats. The solid lined boxes illustrate the components that are generally included in an execution unit instruction, while the dashed lines include components that are optional or that are only included in a sub-set of the instructions. In some examples, instruction format2700described and illustrated are macro-instructions, in that they are instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decode once the instruction is processed.

In some examples, the graphics processor execution units natively support instructions in a 128-bit instruction format2710. A 64-bit compacted instruction format2730is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format2710provides access to all instruction options, while some options and operations are restricted in the 64-bit format2730. The native instructions available in the 64-bit format2730vary by example. In some examples, the instruction is compacted in part using a set of index values in an index field2713. The execution unit hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the 128-bit instruction format2710. Other sizes and formats of instruction can be used.

For each format, instruction opcode2712defines the operation that the execution unit is to perform. The execution units execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the operands. In some examples, instruction control field2714enables control over certain execution options, such as channels selection (e.g., predication) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format2710an exec-size field2716limits the number of data channels that will be executed in parallel. In some examples, exec-size field2716is not available for use in the 64-bit compact instruction format2730.

Some execution unit instructions have up to three operands including two source operands, src02720, src12722, and one destination2718. In some examples, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC22724), where the instruction opcode2712determines the number of source operands. An instruction's last source operand can be an immediate (e.g., hard-coded) value passed with the instruction.

In some examples, the 128-bit instruction format2710includes an access/address mode field2726specifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is directly provided by bits in the instruction.

In some examples instructions are grouped based on opcode2712bit-fields to simplify Opcode decode2740. For an 8-bit opcode, bits4,5, and6allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some examples, a move and logic opcode group2742includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some examples, move and logic group2742shares the five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. A flow control instruction group2744(e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). A miscellaneous instruction group2746includes a mix of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instruction group2748includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group2748performs the arithmetic operations in parallel across data channels. The vector math group2750includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands. The illustrated opcode decode2740, in some examples, can be used to determine which portion of an execution unit will be used to execute a decoded instruction. For example, some instructions may be designated as systolic instructions that will be performed by a systolic array. Other instructions, such as ray-tracing instructions (not shown) can be routed to a ray-tracing core or ray-tracing logic within a slice or partition of execution logic.

Graphics Pipeline

FIG.28is a block diagram of another example of a graphics processor2800. Elements ofFIG.28having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

In some examples, graphics processor2800includes a geometry pipeline2820, a media pipeline2830, a display engine2840, thread execution logic2850, and a render output pipeline2870. In some examples, graphics processor2800is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor2800via a ring interconnect2802. In some examples, ring interconnect2802couples graphics processor2800to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect2802are interpreted by a command streamer2803, which supplies instructions to individual components of the geometry pipeline2820or the media pipeline2830.

In some examples, command streamer2803directs the operation of a vertex fetcher2805that reads vertex data from memory and executes vertex-processing commands provided by command streamer2803. In some examples, vertex fetcher2805provides vertex data to a vertex shader2807, which performs coordinate space transformation and lighting operations to each vertex. In some examples, vertex fetcher2805and vertex shader2807execute vertex-processing instructions by dispatching execution threads to execution units2852A-2852B via a thread dispatcher2831.

In some examples, execution units2852A-2852B are an array of vector processors having an instruction set for performing graphics and media operations. In some examples, execution units2852A-2852B have an attached L1 cache2851that is specific for each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

In some examples, geometry pipeline2820includes tessellation components to perform hardware-accelerated tessellation of 3D objects. In some examples, a programmable hull shader2811configures the tessellation operations. A programmable domain shader2817provides back-end evaluation of tessellation output. A tessellator2813operates at the direction of hull shader2811and contains special purpose logic to generate a set of detailed geometric objects based on a coarse geometric model that is provided as input to geometry pipeline2820. In some examples, if tessellation is not used, tessellation components (e.g., hull shader2811, tessellator2813, and domain shader2817) can be bypassed.

In some examples, complete geometric objects can be processed by a geometry shader2819via one or more threads dispatched to execution units2852A-2852B, or can proceed directly to the clipper2829. In some examples, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. If the tessellation is disabled the geometry shader2819receives input from the vertex shader2807. In some examples, geometry shader2819is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper2829processes vertex data. The clipper2829may be a fixed function clipper or a programmable clipper having clipping and geometry shader functions. In some examples, a rasterizer and depth test component2873in the render output pipeline2870dispatches pixel shaders to convert the geometric objects into per pixel representations. In some examples, pixel shader logic is included in thread execution logic2850. In some examples, an application can bypass the rasterizer and depth test component2873and access un-rasterized vertex data via a stream out unit2823.

The graphics processor2800has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the processor. In some examples, execution units2852A-2852B and associated logic units (e.g., L1 cache2851, sampler2854, texture cache2858, etc.) interconnect via a data port2856to perform memory access and communicate with render output pipeline components of the processor. In some examples, sampler2854, caches2851,2858and execution units2852A-2852B each have separate memory access paths. In some examples the texture cache2858can also be configured as a sampler cache.

In some examples, render output pipeline2870contains a rasterizer and depth test component2873that converts vertex-based objects into an associated pixel-based representation. In some examples, the rasterizer logic includes a windower/masker unit to perform fixed function triangle and line rasterization. An associated render cache2878and depth cache2879are also available in some examples. A pixel operations component2877performs pixel-based operations on the data, though in some instances, pixel operations associated with 2D operations (e.g. bit block image transfers with blending) are performed by the 2D engine2841, or substituted at display time by the display controller2843using overlay display planes. In some examples, a shared L3 cache2875is available to all graphics components, allowing the sharing of data without the use of main system memory.

In some examples, graphics processor media pipeline2830includes a media engine2837and a video front-end2834. In some examples, video front-end2834receives pipeline commands from the command streamer2803. In some examples, media pipeline2830includes a separate command streamer. In some examples, video front-end2834processes media commands before sending the command to the media engine2837. In some examples, media engine2837includes thread spawning functionality to spawn threads for dispatch to thread execution logic2850via thread dispatcher2831.

In some examples, graphics processor2800includes a display engine2840. In some examples, display engine2840is external to processor2800and couples with the graphics processor via the ring interconnect2802, or some other interconnect bus or fabric. In some examples, display engine2840includes a 2D engine2841and a display controller2843. In some examples, display engine2840contains special purpose logic capable of operating independently of the 3D pipeline. In some examples, display controller2843couples with a display device (not shown), which may be a system integrated display device, as in a laptop computer, or an external display device attached via a display device connector.

In some examples, the geometry pipeline2820and media pipeline2830are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some examples, driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some examples, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and/or Vulkan graphics and compute API, all from the Khronos Group. In some examples, support may also be provided for the Direct3D library from the Microsoft Corporation. In some examples, a combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). A future API with a compatible 3D pipeline would also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor.

Graphics Pipeline Programming

FIG.29Ais a block diagram illustrating a graphics processor command format2900according to some examples.FIG.29Bis a block diagram illustrating a graphics processor command sequence2910according to an example. The solid lined boxes inFIG.29Aillustrate the components that are generally included in a graphics command while the dashed lines include components that are optional or that are only included in a sub-set of the graphics commands. The exemplary graphics processor command format2900ofFIG.29Aincludes data fields to identify a client2902, a command operation code (opcode)2904, and data2906for the command. A sub-opcode2905and a command size2908are also included in some commands.

In some examples, client2902specifies the client unit of the graphics device that processes the command data. In some examples, a graphics processor command parser examines the client field of each command to condition the further processing of the command and route the command data to the appropriate client unit. In some examples, the graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the commands. Once the command is received by the client unit, the client unit reads the opcode2904and, if present, sub-opcode2905to determine the operation to perform. The client unit performs the command using information in data field2906. For some commands an explicit command size2908is expected to specify the size of the command. In some examples, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some examples commands are aligned via multiples of a double word. Other command formats can be used.

The flow diagram inFIG.29Billustrates an exemplary graphics processor command sequence2910. In some examples, software or firmware of a data processing system that features an example of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for purposes of example only as examples are not limited to these specific commands or to this command sequence. Moreover, the commands may be issued as batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in at least partially concurrence.

In some examples, the graphics processor command sequence2910may begin with a pipeline flush command2912to cause any active graphics pipeline to complete the currently pending commands for the pipeline. In some examples, the 3D pipeline2922and the media pipeline2924do not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will pause command processing until the active drawing engines complete pending operations and the relevant read caches are invalidated. Optionally, any data in the render cache that is marked ‘dirty’ can be flushed to memory. In some examples, pipeline flush command2912can be used for pipeline synchronization or before placing the graphics processor into a low power state.

In some examples, a pipeline select command2913is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some examples, a pipeline select command2913is required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some examples, a pipeline flush command2912is required immediately before a pipeline switch via the pipeline select command2913.

In some examples, a pipeline control command2914configures a graphics pipeline for operation and is used to program the 3D pipeline2922and the media pipeline2924. In some examples, pipeline control command2914configures the pipeline state for the active pipeline. In some examples, the pipeline control command2914is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.

In some examples, return buffer state commands2916are used to configure a set of return buffers for the respective pipelines to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. In some examples, the graphics processor also uses one or more return buffers to store output data and to perform cross thread communication. In some examples, the return buffer state2916includes selecting the size and number of return buffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on the active pipeline for operations. Based on a pipeline determination2920, the command sequence is tailored to the 3D pipeline2922beginning with the 3D pipeline state2930or the media pipeline2924beginning at the media pipeline state2940.

The commands to configure the 3D pipeline state2930include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are to be configured before 3D primitive commands are processed. The values of these commands are determined at least in part based on the particular 3D API in use. In some examples, 3D pipeline state2930commands are also able to selectively disable or bypass certain pipeline elements if those elements will not be used.

In some examples, 3D pipeline2922is triggered via an execute2934command or event. In some examples, a register write triggers command execution. In some examples execution is triggered via a ‘go’ or ‘kick’ command in the command sequence. In some examples, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel back end operations may also be included for those operations.

In some examples, the graphics processor command sequence2910follows the media pipeline2924path when performing media operations. In general, the specific use and manner of programming for the media pipeline2924depends on the media or compute operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decode. In some examples, the media pipeline can also be bypassed and media decode can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In some examples, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives.

In some examples, media pipeline2924is configured in a similar manner as the 3D pipeline2922. A set of commands to configure the media pipeline state2940are dispatched or placed into a command queue before the media object commands2942. In some examples, commands for the media pipeline state2940include data to configure the media pipeline elements that will be used to process the media objects. This includes data to configure the video decode and video encode logic within the media pipeline, such as encode or decode format. In some examples, commands for the media pipeline state2940also support the use of one or more pointers to “indirect” state elements that contain a batch of state settings.

In some examples, media object commands2942supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers containing video data to be processed. In some examples, all media pipeline states must be valid before issuing a media object command2942. Once the pipeline state is configured and media object commands2942are queued, the media pipeline2924is triggered via an execute command2944or an equivalent execute event (e.g., register write). Output from media pipeline2924may then be post processed by operations provided by the 3D pipeline2922or the media pipeline2924. In some examples, GPGPU operations are configured and executed in a similar manner as media operations.

Program code may be applied to input information to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microprocessor, or any combination thereof.

Accordingly, examples also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such examples may also be referred to as program products.

FIG.30is a block diagram illustrating the use of a software instruction converter to convert binary instructions in a source ISA to binary instructions in a target ISA according to examples. In the illustrated example, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof.FIG.30shows a program in a high-level language3002may be compiled using a first ISA compiler3004to generate first ISA binary code3006that may be natively executed by a processor with at least one first ISA core3016. The processor with at least one first ISA core3016represents any processor that can perform substantially the same functions as an Intel® processor with at least one first ISA core by compatibly executing or otherwise processing (1) a substantial portion of the first ISA or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one first ISA core, in order to achieve substantially the same result as a processor with at least one first ISA core. The first ISA compiler3004represents a compiler that is operable to generate first ISA binary code3006(e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one first ISA core3016. Similarly,FIG.30shows the program in the high-level language3002may be compiled using an alternative ISA compiler3008to generate alternative ISA binary code3010that may be natively executed by a processor without a first ISA core3014. The instruction converter3012is used to convert the first ISA binary code3006into code that may be natively executed by the processor without a first ISA core3014. This converted code is not necessarily to be the same as the alternative ISA binary code3010; however, the converted code will accomplish the general operation and be made up of instructions from the alternative ISA. Thus, the instruction converter3012represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have a first ISA processor or core to execute the first ISA binary code3006.

IP Core Implementations

FIG.31is a block diagram illustrating an IP core development system3100that may be used to manufacture an integrated circuit to perform operations according to some examples. The IP core development system3100may be used to generate modular, re-usable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit). A design facility3130can generate a software simulation3110of an IP core design in a high-level programming language (e.g., C/C++). The software simulation3110can be used to design, test, and verify the behavior of the IP core using a simulation model3112. The simulation model3112may include functional, behavioral, and/or timing simulations. A register transfer level (RTL) design3115can then be created or synthesized from the simulation model3112. The RTL design3115is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals. In addition to an RTL design3115, lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary.

The RTL design3115or equivalent may be further synthesized by the design facility into a hardware model3120, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a 3rdparty fabrication facility3165using non-volatile memory3140(e.g., hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design may be transmitted (e.g., via the Internet) over a wired connection3150or wireless connection3160. The fabrication facility3165may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least some examples described herein.

Moreover, in the various examples described above, unless specifically noted otherwise, disjunctive language such as the phrase “at least one of A, B, or C” or “A, B, and/or C” is intended to be understood to mean either A, B, or C, or any combination thereof (i.e. A and B, A and C, B and C, and A, B and C).

Examples include, but are not limited to:

1. An apparatus such as a processor, SoC, core, accelerator, etc. that at least decoder circuitry to decode an instance of a single instruction, the instance of the single instruction to at least include fields for an opcode, an identification of location of a packed data source operand, an identification of location of a packed data destination operand, and an indication of a location in each packed data element of the packed data destination to store an 8-bit integer (INT8) value, wherein the opcode is to indicate conversion circuitry is to downconvert data of each packed data element of the packed data source operand to an INT8 value and provide the INT8 value for storage in the identified location of a corresponding packed data element of the packed data destination; and execution circuitry to execute the decoded instance of the single instruction according to the opcode.

2. The apparatus of example 1, wherein the packed data source operand is a vector register.

3. The apparatus of example 1, wherein the packed data source operand is a memory location.

4. The apparatus of any of examples 1-3, wherein the INT8 value is signed.

5. The apparatus of any of examples 1-3, wherein the INT8 value is unsigned.

6. The apparatus of any of examples 1-5, wherein the data of each packed data element of the packed data source operand is in a 16-bit floating point (FP16) format.

7. The apparatus of any of examples 1-5, wherein the data of each packed data element of the packed data source operand is in a 32-bit floating point (FP32) format.

8. The apparatus of any of examples 1-5, wherein the data of each packed data element of the packed data source operand is in a 16-bit brain-float floating point (BF16) format.

9. The apparatus of any of examples 1-8, wherein the indication of a location in each packed data element of the packed data destination to store an INT8 value is to be provided by an immediate.

10. The apparatus of any of examples 1-9, wherein when a downconversion is inexact a floating-point precision exception is raised and a truncated INT8 value is generated.

11. The apparatus of any of examples 1-9, wherein when a downconversion is inexact a floating-point precision exception is raised and a rounded INT8 value is generated.

12. A method to convert data elements using that at least comprises an instance of a single instruction to at least include fields for an opcode, an identification of location of a packed data source operand, an identification of location of a packed data destination operand, and an indication of a location in each packed data element of the packed data destination to store an 8-bit integer (INT8) value, wherein the opcode is to indicate conversion circuitry is to downconvert data of each packed data element of the packed data source operand to an INT8 value and provide the INT8 value for storage in the identified location of a corresponding packed data element of the packed data destination; decoding the single instruction; and executing the decoded instruction. In some instances translation, etc. is performed the single instruction and those translated one or more instructions are decoded and executed as detailed above.

13. The method of example 12, wherein the packed data source operand is a vector register.

14. The method of example 12, wherein the packed data source operand is a memory location.

15. The method of any of examples 12-14, wherein the INT8 value is signed.

16. The method of any of examples 12-14, wherein the INT8 value is unsigned.

17. The method of any of examples 12-16, wherein the indication of a location in each packed data element of the packed data destination to store an INT8 value is to be provided by an immediate.

18. A system such as a computer, SoC, hardware device, etc. that at least comprises memory to store an instance of a single instruction; decoder circuitry to decode the instance of a single instruction, the instance of the single instruction to at least include fields for an opcode, an identification of location of a packed data source operand, an identification of location of a packed data destination operand, and an indication of a location in each packed data element of the packed data destination to store an 8-bit integer (INT8) value, wherein the opcode is to indicate conversion circuitry is to downconvert data of each packed data element of the packed data source operand to an INT8 value and provide the INT8 value for storage in the identified location of a corresponding packed data element of the packed data destination; and execution circuitry to execute the decoded instance of the single instruction according to the opcode.

19. The system of example 18, wherein the INT8 value is signed.

20. The system of example 18, wherein the INT8 value is unsigned.