Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

BACKGROUND

Two-dimensional (2D) memory arrays are prevalent in electronic devices and may include, for example, NOR flash memory arrays, NAND flash memory arrays, dynamic random-access memory (DRAM) arrays, and so on. However, 2D memory arrays are reaching scaling limits and are hence reaching limits on memory density. Three-dimensional (3D) memory arrays are a promising candidate for increasing memory density and may include, for example, 3D NAND flash memory arrays, 3D NOR flash memory arrays, and so on.

DETAILED DESCRIPTION

Some three-dimensional (3D) memory devices comprise a plurality of memory cells defining a plurality of memory arrays at different elevations above a substrate. According to some embodiments, a lower source/drain region, a semiconductor channel, and an upper source/drain region are vertically stacked and define a common sidewall. A control gate electrode and a data storage layer extend vertically through the plurality of memory arrays along the common sidewall. The data storage layer is between and borders the semiconductor channel and the control gate electrode. Further, the data storage layer comprises a silicon nitride layer separated from the control gate electrode and the semiconductor channel by silicon oxide.

During program and erase operations, electrons tunnel into or out of silicon nitride layer through silicon oxide, such that a bit of data may be represented by the amount of charge in the silicon nitride layer. A challenge is that program and erase operations are dependent upon high voltages for electron tunneling and hence for program and erase operations. Such high voltages may, for example, include voltages greater than about 10 volts or some other suitable voltage. Another challenge is that tunneling current is low and hence program and erase speeds are slow. Such slow speeds may, for example, be speeds greater than about 10 microseconds or some other suitable amount of time. Yet another challenge is that power consumption is high during program and erase operations due to the high voltages and also due to the slow speeds.

Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device and a method for forming the same. Note that although MFIS stands for metal ferroelectric insulator semiconductor, doped polysilicon and other suitable conductive materials may be used in place of metal. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. Further, the semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. The control gate electrode is separated from the semiconductor channel and the lower and upper source/drain regions by a ferroelectric layer and a gate dielectric layer.

The ferroelectric layer has a polarity representing a bit of data. During a program operation, a program voltage is applied across the ferroelectric layer from the control gate electrode to the semiconductor channel to set the polarity to a programmed state. During an erase operation, an erase voltage is applied across the ferroelectric layer from the control gate electrode to the semiconductor channel to set the polarity to an erased state. By employing the ferroelectric layer for data storage, as opposed to a silicon nitride layer, there is no dependence on carrier tunneling. As such, program and erase voltages may be reduced and program and erase speeds may be increased. For example, program and erase voltages may be reduced to less than about 5 volts and/or program and erase speeds may be reduced to less than about 100 nanoseconds. Other suitable values are, however, amenable. By reducing the program and erase voltages and by increasing the program and erase speeds, power consumption may be reduced.

With reference toFIGS. 1A-1C, various views100A-100C of some embodiments of a MFIS memory cell102is provided.FIG. 1Acorresponds to a cross-sectional view100A along line A inFIG. 1C, whereasFIG. 1Bcorresponds to a cross-sectional view100B along line B inFIG. 1C. Further,FIG. 1Ccorresponds to a top view100C. The MFIS memory cell102may, for example, be or comprise a MFIS field-effect transistor (FET) or some other suitable type of semiconductor device having an MFIS stack.

The gate dielectric layer110and the ferroelectric layer112separate the control gate electrode114from the common sidewall108. The gate dielectric layer110is between the ferroelectric layer112and the common sidewall108, and the ferroelectric layer112is between the control gate electrode114and the gate dielectric layer110. Further, the ferroelectric layer112has a polarity representing a bit of data and is hence used for data storage.

During program and erase operations of the MFIS memory cell102, the lower and upper source/drain regions106l,106uare electrically coupled in parallel and used as a proxy for the semiconductor channel104. A program voltage is applied from the control gate electrode114to the semiconductor channel104(e.g., via the lower and upper source/drain regions106l,106u) to set the polarity to a programmed state. Further, an erase voltage having an opposite polarity as the program voltage is applied from the control gate electrode114to the semiconductor channel104(e.g., via the lower and upper source/drain regions106l,106u) to set the polarity to an erased state. The programmed state may, for example, represent a binary “1”, whereas the erased state may, for example, represent a binary “0”, or vice versa.

The ferroelectric layer112screens an electric field produced by the control gate electrode114differently depending whether the polarity is in the programmed state or the erased state. As such, the MFIS memory cell102has a programmed threshold voltage and an erased threshold voltage respectively while the polarity is in the programmed and erased states. During a read operation of the MFIS memory cell102, the control gate electrode114is biased with a read voltage between the programmed and erased threshold voltages and the resistance of the semiconductor channel104is measured. Depending upon whether the semiconductor channel104conducts, the polarity is either in the programmed or erased state.

By using the ferroelectric layer112for data storage, as opposed to a silicon nitride layer, there is no dependence on carrier tunneling for the program and erase operations. As such, program and erase voltages may be reduced and program and erase speeds may be increased. For example, the program and erase voltages may be reduced to less than about 5 volts and/or program and erase speeds may be reduced to less than about 100 nanoseconds. Other suitable values are, however, amenable. By reducing the program and erase voltages and by increasing the program and erase speeds, power consumption may be reduced.

With continued reference toFIGS. 1A-1C, the semiconductor channel104extends from the lower source/drain region106lto the upper source/drain region106u. The semiconductor channel104may, for example, be doped or undoped and may, for example, be or comprise polysilicon and/or some other suitable semiconductor material(s). The semiconductor channel104may, for example, have a thickness (e.g., in an X direction) of about 10-30 nanometers, about 10-20 nanometers, about 20-30 nanometers, or some other suitable value.

The lower and upper source/drain regions106l,106uare doped and may, for example, be or comprise polysilicon and/or some other suitable semiconductor material(s). In some embodiments, the lower and upper source/drain regions106l,106uare or comprise doped polysilicon with a first doping type, and the semiconductor channel104is or comprises doped polysilicon with a second doping type opposite the first doping type. In some other embodiments, the lower and upper source/drain regions106l,106uare or comprise doped polysilicon, and the semiconductor channel104is or comprises undoped polysilicon.

The gate dielectric layer110, the ferroelectric layer112, and the control gate electrode114are at sides of the lower and upper source/drain regions106l,106u. As such, the gate dielectric layer110, the ferroelectric layer112, and the control gate electrode114are uncovered by the upper source/drain region106u. The control gate electrode114may, for example, be or comprise titanium nitride, doped polysilicon (e.g., N+ or P+), tantalum nitride, tungsten, some other suitable conductive material(s), or any combination of the foregoing.

The gate dielectric layer110may, for example, be or comprise silicon oxide (e.g., SiO2), aluminum oxide (e.g., Al2O3), silicon oxynitride (e.g., SiON), silicon nitride (e.g., Si3N4), lanthanum oxide (e.g., La2O3), strontium titanium oxide (e.g., SrTiO3), undoped hafnium oxide (e.g., HfO2), some other suitable dielectric(s), or any combination of the foregoing. In some embodiments, the gate dielectric layer110is or comprises a high k dielectric material having a dielectric constant greater than about 3.9, about 10, or some other suitable value. In some embodiments, the gate dielectric layer110has a dielectric constant of about 3.9-15, about 3.9-10, about 10-15, or some other suitable value. If the dielectric constant is too low (e.g., less than about 3.9 or some other suitable value), an electric field across the gate dielectric layer110may be high. The high electric field may lead to a high time-dependent dielectric breakdown (TDDB) and may hence reduce reliability of the gate dielectric layer110.

In some embodiments, a thickness Tgdlof the gate dielectric layer110(e.g., in an X direction) is less than about 2.5 nanometers or some other suitable value. In some embodiments, the thickness Tgdlis about 1.5-2.5 nanometers, about 1.5-1.75 nanometers, about 1.75-2.5 nanometers, or some other suitable value. If the thickness Tgdlis too small (e.g., less than about 1 nanometer or some other suitable value), leakage current may be high and hence data retention may be low. If the thickness Tgdlis too large (e.g., greater than about 2.5 nanometers or some other suitable value), the program and erase voltages may be large and the memory window (e.g., a difference between the program and erase threshold voltages) may be small. The former leads to low power efficiency, whereas the latter leads to low reliability.

The ferroelectric layer112is in the orthorhombic phase and may, for example, be or comprise hafnium oxide (e.g., HfO2) doped with: 1) aluminum to less than about 20 atomic percent; 2) silicon to less than about 5 atomic percent; 3) zirconium to less than about 50 atomic percent; 4) lanthanum to less than about 50 atomic percent; 5) strontium to less than about 50 atomic percent; or 6) some other suitable element. Other atomic percentages are, however, amenable. Additionally, or alternatively, the ferroelectric layer112may, for example, be or comprise some other suitable ferroelectric material(s). In some embodiments, a dielectric constant of the ferroelectric layer112is greater than that of the gate dielectric layer110.

In some embodiments, a thickness Tfeof the ferroelectric layer112(e.g., in an X direction) is less than about 15 nanometers or some other suitable value. In some embodiments, the thickness Tgdlis about 5-15 nanometers, about 5-10 nanometers, about 10-15 nanometers, or some other suitable value. If the thickness Tfeis too small (e.g., less than about 5 nanometer or some other suitable value), the polarity may weekly switch between the programmed and erased states during the program and erase operations. As a result, reliability may be low. If the thickness Tfeis too large (e.g., greater than about 15 nanometers or some other suitable value), the program and erase voltages may be large and hence power efficiency may be low.

A dielectric structure116surrounds the MFIS memory cell102. The dielectric structure116separates the lower and upper source/drain regions106l,106ufrom each other and, as seen hereafter, separates the MFIS memory cell102from other MFIS memory cells when the MFIS memory cell102is integrated into a memory array. Note that a portion of the dielectric structure116separating the lower and upper source/drain regions106l,106umay also be known as a source/drain dielectric layer. The dielectric structure116may be or comprise, for example, silicon oxide and/or some other suitable dielectric(s).

With reference toFIGS. 2A-2D, various views200A-200D of some embodiments of a 3D memory array202comprising a plurality of MFIS memory cells102configured as inFIGS. 1A-1Cis provided.FIG. 2Acorresponds to a cross-sectional view200A along line C inFIG. 2D.FIG. 2Bcorresponds to a cross-sectional view200B along line D inFIG. 2D.FIG. 2Ccorresponds to a cross-sectional view200C along line E inFIG. 2D.FIG. 2Dcorresponds to a top view200D along lines C-E respectively inFIGS. 2A-2C. The 3D memory array202may, for example, provide high memory density, as well as high reliability (e.g., high endurance and high retention) for high speed and low power consumption applications.

The MFIS memory cells102are grouped into a first memory array204aand a second memory array204b. The first and second memory arrays204a,204bare vertically stacked over a dielectric substrate206, and the second memory array204boverlies the first memory array204a. The first and second memory arrays204a,204bhave the same layout and each has 9 rows and 8 columns (best seen inFIG. 2D). In alternative embodiments, the first and second memory arrays204a,204bhave more or less rows and/or more or less columns. For readability, the rows and the columns are not labeled. However, it is to be appreciated that the rows extend in an X direction (e.g., laterally in the cross-sectional views200A,200B ofFIGS. 2A and 2B), whereas the columns extend in a Y direction (e.g., laterally in the cross-sectional view200C ofFIG. 2C).

A plurality of control gate electrodes114, a ferroelectric layer112, and a gate dielectric layer110extend through the first and second memory arrays204a,204band partially define the MFIS memory cells102. The control gate electrodes114are shared by MFIS memory cells in the first memory array204aand MFIS memory cells in the second memory array204b. For example, each MFIS memory cell in the first memory array204amay share a control gate electrode with an overlying MFIS memory cell in the second memory array204b. Similarly, the ferroelectric layer112and the gate dielectric layer110are shared by MFIS memory cells in the first memory array204aand MFIS memory cells in the second memory array204b. The ferroelectric layer112may, for example, be shared because polarization of the ferroelectric layer112may be localized to a MFIS memory cell at which the polarization occurred.

The MFIS memory cells102are further grouped into pairs208of neighboring MFIS memory cells (e.g., MFIS pairs208) along corresponding rows. The MFIS memory cells in each of the MFIS pairs208share a corresponding one of the control gate electrodes114. A MFIS memory cell on a right side of a corresponding control gate electrode is as illustrated and described inFIGS. 1A-1C. A MFIS memory cell on a left side of a corresponding control gate electrode is as illustrated and described inFIGS. 1A-1C, except thatFIGS. 1A and 1Cshould be flipped horizontally respectively along the Z axis and the Y axis.FIG. 1Bis the same regardless of whether an MFIS memory cell is on a left or right side of a corresponding control gate electrode.

The MFIS pairs208are arranged so an MFIS pair occurs every two columns along each row and occurs every other row along each column. Further, the MFIS pairs208are staggered along neighboring columns and neighboring rows so a pitch Pyof the MFIS pairs208in a Y direction spans a row and a pitch Pxof the MFIS pairs208in an X direction spans two columns. In some embodiments, the control gate electrodes114have individual widths Wcgin the Y direction that are less than about half the Y-direction pitch Py.

A plurality of semiconductor channels104, a plurality of lower source/drain regions106l, and a plurality of upper source/drain regions106ualso partially define the MFIS memory cells102. Note that “lower” and “upper” are relative to the corresponding MFIS memory cells102of the lower and upper source/drain regions106l,106u. The semiconductor channels104extend correspondingly along the columns and are shared by the MFIS memory cells in the corresponding columns. A semiconductor channel may, for example, be shared by multiple MFIS memory cells because an electric field produced by an MFIS memory cell is localized to the MFIS memory cell. In alternative embodiments, the semiconductor channels104are individual to the MFIS memory cells102and are hence not shared. Similar to the semiconductor channels104, the lower and upper source/drain regions106l,106uextend correspondingly along the columns and are shared by the MFIS memory cells in the corresponding columns. Further, the upper source/drain regions106udefine bit lines BL, and the lower source/drain regions106ldefine source lines SL. In alternative embodiments, the upper source/drain regions106udefine the source lines SL, and the lower source/drain regions106ldefine the bit lines BL.

A plurality of array dielectric layers210and a dielectric structure116surround the first and second memory arrays204a,204b. The array dielectric layers210are individual to the first and second memory arrays204a,204band are each atop the upper source/drain region106uof the individual memory array. The array dielectric layers210are a different material than the dielectric substrate206and may, for example, be or comprise silicon nitride and/or some other suitable dielectric(s). The dielectric structure116is along sidewalls of the MFIS memory cells102to laterally separate the MFIS memory cells102from each other.

WhileFIGS. 2A-2Dillustrate a 3D memory array with two memory-array levels, more memory-array levels are amenable. For example, the second memory array204balong with its corresponding one of the array dielectric layers210may be repeated above the second memory array204b. Further, whileFIGS. 2A-2Dillustrate a 3D memory array with two memory-array levels, a two-dimensional (2D) memory array with a single memory-array level is also amenable. For example, the second memory array204balong with its corresponding one of the array dielectric layers210may be omitted.

With reference toFIG. 3A, a cross-sectional view300A of some alternative embodiments of the 3D memory array202ofFIG. 2Ais provided in which the 3D memory array202is uncovered by the gate dielectric layer110and the ferroelectric layer112. As a result, the gate dielectric layer110comprises a plurality of discrete gate dielectric segments, and the ferroelectric layer112comprises a plurality of discrete ferroelectric segments. The gate dielectric segments and the ferroelectric segments are shared by the first and second memory arrays204a,204band have U-shaped profiles. In alternative embodiments, the gate dielectric segments and/or the ferroelectric segments have other suitable profiles. Further, the gate dielectric segments and the ferroelectric segments alternate with the lower and upper source/drain regions106l,106ualong the rows. As inFIGS. 2A-2D, rows extend in an X direction.

With reference toFIGS. 3B and 3C, cross-sectional views300B,300C of some alternative embodiments of the 3D memory array202ofFIG. 2Aare provided in which the control gate electrodes114and the dielectric structure116bulge at the semiconductor channels104. Further, the gate dielectric layer110and the ferroelectric layer112wrap around sides of the bulges. InFIG. 3B, the semiconductor channels104have rectangular profiles and are set back from sidewalls of the lower and upper source/drain regions106l,106u. InFIG. 3C, the semiconductor channels104respectively have C-shaped and reverse C-shaped profiles. In alternative embodiments, the semiconductor channels104have other suitable profiles.

With reference toFIGS. 3D-3F, cross-sectional views300D-300F of some alternative embodiments of the 3D memory array202ofFIG. 2Aare provided in which the gate dielectric layer110comprises a plurality of discrete gate dielectric segments respectively underlying the upper source/drain regions106u. InFIGS. 3D and 3E, the semiconductor channels104respectively have C-shaped and reverse C-shaped profiles that respectively wrap around sides of the gate dielectric segments. InFIG. 3E, the control gate electrodes114and the dielectric structure116further bulge at the gate dielectric segments and the gate dielectric segments respectively have C-shaped and reverse C-shaped profiles respectively wrapping around sides of the bulges. InFIG. 3F, the semiconductor channels104have rectangular profiles and hence do not wrap around sides of the gate dielectric segments. In alternative embodiments, the semiconductor channels104and/or the gate dielectric segments have other suitable profiles.

With reference toFIG. 3G, a cross-sectional view300G of some alternative embodiments of the 3D memory array202ofFIG. 2Ais provided in which cavities302separate the control gate electrodes114from each other instead of the dielectric structure116. The cavities302include air and/or some other suitable gas(es). Further, the cavities302are sealed by a seal dielectric layer304. The seal dielectric layer304covers the 3D memory array202and the cavities302and may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s).

WhileFIGS. 3A-3Gillustrate cross-sectional views300A-300G of some alternative embodiments ofFIG. 2Ain which constituents are modified, it is to be appreciated that the modifications may also be applied to any ofFIGS. 2B-2D. For example, when applying the modifications ofFIG. 3AtoFIGS. 2B-2D, the gate dielectric layer110and the ferroelectric layer112may be cleared from atop the array dielectric layer210of the second memory array204binFIGS. 2B and 2C.FIG. 2Dmay be remain unchanged. WhileFIG. 2Dis described with regard toFIGS. 2A-2C, any ofFIGS. 3A-3Gmay be taken along line C in embodiments ofFIG. 2Dwhich have been modified as necessary as described above. For example,FIG. 3Gmay be taken along line C in alternative embodiments ofFIG. 2Din which the dielectric structure116has been replaced with the cavities302. As another example,FIGS. 3A-3Cmay be taken along line C in the embodiments ofFIG. 2Dwithout modification ofFIG. 2D.

With reference toFIG. 4A, a cross-sectional view400A of some alternative embodiments of the 3D memory array ofFIG. 2Ais provided in which a plurality of metal lines402define the source lines SL and the bit lines BL instead of the lower and upper source/drain regions106l,106u. The metal lines402extend correspondingly along the columns. Further, the metal lines402are individual to the lower and upper source/drain regions106l,106uand electrically couple directly to the individual source/drain regions. In the case of the upper source/drain regions106u, the upper source/drain regions106uunderlie and directly contact the corresponding metal lines. In the case of the lower source/drain regions106l, the lower source/drain regions106loverlie and directly contact the corresponding metal lines.

The metal lines402have smaller resistances than the lower and upper source/drain regions106l,106uand hence reduce voltage drops along the source lines SL and the bit lines BL. The reduce voltage drops allow larger memory arrays and/or reduced power consumption. The metal lines402comprise corresponding metal layers404and corresponding barrier layers406. The barrier layers406are configured to prevent outward diffusion of material from the metal layers404to overlying structure and/or underlying structure. The metal layers404may, for example, be or comprise tungsten and/or some other suitable metal(s). The barrier layers406may, for example, be or comprise titanium nitride (e.g., TiN), tungsten nitride (e.g., WN), some other suitable barrier material(s), or any combination of the foregoing.

With reference toFIG. 4B, a cross-sectional view400B of some alternative embodiments of 3D memory array ofFIG. 4Ais provided in which dummy semiconductor channels408are on sidewalls of the metal lines402to protect the metal lines402from oxidation. Such oxidation may, for example, occur before and/or during deposition of the gate dielectric layer110and the ferroelectric layer112. Oxidation may increase resistances of the metal lines402, thereby increasing voltage drops along the metal lines402. This may, in turn, increase power consumption and/or limit the size of the 3D memory array202. The dummy semiconductor channels408are respectively as the semiconductor channels104are described. This may, for example, be due to formation by the same process or a similar process.

In some embodiments, the dummy semiconductor channels408have individual widths Wdscthat are the same as or substantially the same as individual widths Wscof the semiconductor channels104. In alternative embodiments, the dummy semiconductor channels408have individual widths Wdscthat are different (e.g., greater or less) than the individual widths Wscof the semiconductor channels104. The different widths may, for example, be due to different etch processes while forming recesses within which the dummy semiconductor channels408and the semiconductor channels104are formed and/or may, for example, be due to different etch rates while forming the recesses. Other suitable reasons are, however, amenable.

With reference toFIG. 4C, a cross-sectional view400C of some alternative embodiments of the 3D memory array ofFIG. 2Ais provided in which a plurality of silicide lines410are used in place of the plurality of metal lines402. Hence, the source lines SL and the bit lines BL are defined by the silicide lines410. The silicide lines410are a metal silicide and may, for example, be or comprise nickel silicide or some other suitable metal silicide.

As discussed with regard toFIG. 4B, oxidation of the metal lines402may occur without dummy semiconductor channels408protecting sidewalls of the metal lines402. Such oxidation may, in turn, negatively impact performance of the 3D memory array202. The silicide lines410may have a comparable resistance to the metal lines402and may hence perform comparable to the metal lines402. Further, the silicide lines410may have a lower reactivity to oxygen than the metal lines402. Therefore, by replacing the metal lines402with the silicide lines410, the challenges associated with oxidation may be mitigated without the dummy semiconductor channels408. The dummy semiconductor channels408may add complexity to formation of the 3D memory array202, such that omitting the dummy semiconductor channels408may reduce costs and/or increase yields.

With reference toFIG. 4D, a cross-sectional view400D of some alternative embodiments of the 3D memory array ofFIG. 4Cis provided in which the lower and upper source/drain regions106l,106uare omitted. Instead, the silicide lines410are used as source/drain regions for the MFIS memory cells102.

WhileFIGS. 4A-4Dillustrate cross-sectional views400A-400D of some alternative embodiments of the 3D memory array ofFIG. 2Ain an X direction, it is to be appreciated that top views of the alternative embodiments may be as illustrated inFIG. 2D. For example,FIG. 2Dmay be taken along line C in any one of theFIGS. 4A-4D. Similarly, it is to be appreciated that cross-sectional views of the alternative embodiments in a Y direction may be as illustrated inFIG. 2C, except that the vertical stacks of layers would be modified to matchFIGS. 4A-4D.

With reference toFIGS. 5A-5C, various views500A-500C of some embodiments of an integrated circuit (IC) comprising a 3D memory array202is provided. The 3D memory array202is as described atFIGS. 2A-2Dand includes additional columns. In alternative embodiments, the 3D memory array202is as described at any ofFIGS. 3A-3G and 4A-4Dand further includes the additional columns.FIG. 5Acorresponds to a cross-sectional view500A along line F inFIG. 5C, andFIG. 5Bcorresponds to a cross-sectional view500B along line G inFIG. 5C. Further,FIG. 5Ccorresponds to lines F and G respectively inFIGS. 5A and 5B.

The 3D memory array202overlies a semiconductor substrate502within an interconnect structure504. The semiconductor substrate502may, for example, be or comprise a bulk substrate of monocrystalline silicon and/or some other suitable type of semiconductor substrate. The interconnect structure504comprises an interconnect dielectric layer506, a plurality of wires508, and a plurality of vias510. The wires508and the vias510are alternatingly stacked in the interconnect dielectric layer506to define conductive paths over and under the 3D memory array202. The interconnect dielectric layer506may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). The wires508and the vias510may, for example, be or comprise metal and/or some other suitable conductive material(s).

The plurality of wires508define top word line wires TWL (shown in phantom inFIG. 5C) overlying the 3D memory array202and extending correspondingly along the rows of the 3D memory array202. Further, the plurality of vias510define top electrode vias TEV extending respectively from the control gate electrodes114respectively to the top word lines TWL. Hence, the top word lines TWL and the top electrode vias TEV electrically couple to and interconnect control gate electrodes in corresponding rows.

Semiconductor devices512are on the semiconductor substrate502, between the semiconductor substrate502and the interconnect structure504. The semiconductor devices512comprise corresponding pairs of source/drain regions514, corresponding gate electrodes516, and corresponding gate dielectric layers518. The gate electrodes516correspond to the pairs of source/drain regions514and are laterally sandwiched between the source/drain regions of the corresponding pairs. The gate dielectric layer518respectively underlie the gate electrodes516to separate the gate electrodes516from the semiconductor substrate502. The semiconductor devices512may, for example, be metal-oxide-semiconductor (MOS) FETs, fin FETs, nanostructure FETs, gate-all-around (GAA) FETs, or some other suitable type of semiconductor device. Further, the semiconductor devices512may, for example, implement read and write circuitry for the 3D memory array202.

A trench isolation structure520extends into the semiconductor substrate502to provide electrical isolation between the semiconductor devices512and other semiconductor devices (not shown) on the semiconductor substrate502. The trench isolation structure520may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). Further, the trench isolation structure520may, for example, be or comprise a shallow trench isolation (STI) structure and/or some other suitable type of trench isolation structure.

With reference toFIG. 6, a schematic view600of some embodiments of a portion of the 3D memory array202ofFIGS. 5A-5Cis provided within box BX ofFIGS. 5A-5C. The box BX spans two rows and eight columns. The rows have corresponding top word lines TWL with subscripts denoting specific row numbers beginning at row m, where m is an integer value. The columns have corresponding bit lines BL and corresponding source lines SL with subscripts denoting specific column numbers beginning at column n, where n is an integer value.

The top word lines TWL extend correspondingly along the rows and electrically couple to the MFIS memory cells102in the corresponding rows via the control gate electrodes114in the corresponding rows. The bit lines BL and the source lines SL extend correspondingly along the columns and electrically couple to the MFIS memory cells102in the corresponding columns via the lower and upper source/drain regions106l,106u(see, e.g.,FIGS. 5A-5C) in the corresponding columns. Collectively, the top word lines TWL, the bit lines BL, and the source lines SL facilitate read and write operations on the MFIS memory cells102.

With reference toFIGS. 7A and 7B, cross-sectional views700A,700B of some alternative embodiments of the IC ofFIGS. 5A-5Cis provided in which word lines electrically couple to the control gate electrodes114respectively at a bottom of the 3D memory array202and a top of the 3D memory array202. The cross-sectional view700A ofFIG. 7Acorresponds to the cross-sectional view500A ofFIG. 5A, and the cross-sectional view700B ofFIG. 7Bcorresponds to the cross-sectional view500B ofFIG. 5B.

Control gate electrodes at even numbered rows electrically couple to bottom word lines BWL at a bottom of the 3D memory array202, and control gate electrodes at odd numbered rows electrically couple to top word lines TWL at a top of the 3D memory array202, or vice versa. Further, the control gate electrodes114have different cross-sectional profiles depending upon whether electrically coupled to top or bottom word lines. Control gate electrodes electrically coupled to the bottom word lines BWL have protrusions that protrude respectively to the bottom word lines BWL and that define bottom electrode vias BEV. Control gate electrodes electrically coupled the top word lines TWL lack upward and downward protrusions and are electrically coupled to the top word lines TWL by separate top electrode vias TEV.

By splitting the word lines between the bottom of the 3D memory array202and the top of the 3D memory array202, a pitch of the word lines in a Y direction (e.g., into and out of the page; see, for example,FIG. 5C) may be reduced. Design constraints regarding the spacing of the word lines may otherwise limit the pitch. By reducing the pitch of the word lines, scaling down of the 3D memory array202may be enhanced.

With reference toFIGS. 8A and 8B, cross-sectional views800A,800B of some alternative embodiments of the IC ofFIGS. 7A and 7Bis provided in which the bottom electrode vias BEV are independent of the control gate electrodes114. The control gate electrodes114have the same or substantially the same profile regardless of whether electrically coupled to top or bottom word lines. Further, the control gate electrodes114extend through a cap dielectric layer802between the 3D memory array202and the bottom electrode vias BEV. Control gate electrodes electrically coupled to the bottom word lines BWL extend through the cap dielectric layer802respectively to the bottom electrode vias BEV. Control gate electrodes electrically coupled to the top word lines TWL extend through the cap dielectric layer802to the interconnect dielectric layer506. The cap dielectric layer802may be or comprise, for example, silicon nitride and/or some other suitable dielectric(s).

The 3D memory array202is uncovered by the gate dielectric layer110and the ferroelectric layer112as inFIG. 3A. As such, the gate dielectric layer110comprises a plurality of discrete gate dielectric segments, and the ferroelectric layer112comprises a plurality of discrete ferroelectric segments. A plurality of spacers804separate the control gate electrodes114from the ferroelectric segments. Further, the dielectric structure116extends through the cap dielectric layer802, the gate dielectric segments, and the ferroelectric segments. The spacers804may be or comprise, for example, silicon nitride and/or some other suitable dielectric(s).

As seen hereafter, the spacers804may be formed by a self-aligned process and used with a top one of the array dielectric layers210as a mask to form openings within which the control gate electrodes114are formed. This may lead to a reduction in the number of photomasks used while forming the 3D memory array202. Because photolithography is expensive, the reduction may lead to a substantial cost savings. Further, as seen hereafter, the spacers804protect the ferroelectric layer112while forming openings within which the control gate electrodes114are formed. This, in turn, reduces the likelihood of damage to the ferroelectric layer112and may hence enhance performance of the MFIS memory cells102. Further yet, by forming the bottom electrode vias BEV independent of the control gate electrodes114, aspect ratios (e.g., ratios of height to width) of the openings within which the control gate electrodes114are formed may be reduced. This, in turn, may reduce the complexity of the etch used to form the openings and may enlarge the process window (e.g., the resiliency).

While the embodiments of the ICs inFIGS. 7A, 7B, 8A, and 8Bwere not accompanied with top views, it is to be appreciated that the top view500C ofFIG. 5Cis representative of these top views with a few modifications. Top electrode vias TEV and top word lines TWL at even numbered rows or odd numbered rows, but not both, instead correspond to bottom electrode vias BEV and bottom word lines BWL and should therefore be shown in phantom. Further, sizes of electrode vias and/or shapes of electrode vias may be different. Accordingly, the cross-sectional views700A,800A ofFIGS. 7A and 8Amay, for example, be taken along line F inFIG. 5C(as modified above), and the cross-sectional views700B,800B ofFIGS. 7B and 8Bmay, for example, be taken along line G inFIG. 5C(as modified above).

With reference toFIGS. 9A and 9BthroughFIGS. 18A and 18B, a series of views of some embodiments of a method for forming an IC comprising a 3D memory array of MFIS memory cells is provided. Figures labeled with a suffix of B illustrate cross-sectional views along line H, I, or J (whichever is present) in like-numbered figures with a suffix of A. Figures with a suffix of A illustrate top views along line H, I, or J (whichever is present) in like-numbered figures with a suffix of B. The method may, for example, be employed to form the IC ofFIGS. 5A-5Cor other suitable ICs.

As illustrated by the top and cross-sectional views900A,900B ofFIGS. 9A and 9B, a semiconductor device512and a trench isolation structure520are formed on a semiconductor substrate502. The semiconductor device512comprises a pair of source/drain regions514, a gate electrode516, and a gate dielectric layer518. The gate electrode516and the gate dielectric layer518are stacked between the source/drain regions514. The trench isolation structure520surrounds the semiconductor device512to electrically isolate the semiconductor device512from other semiconductor devices (not shown).

Also illustrated by the top and cross-sectional views900A,900B ofFIGS. 9A and 9B, an interconnect structure504is partially formed over the semiconductor device512and the semiconductor substrate502. The interconnect structure504comprises a lower interconnect dielectric layer506a, a plurality of lower wires508a, and a plurality of lower vias510a. The lower wires508aand the lower vias510aare alternatingly stacked in the lower interconnect dielectric layer506aand define conductive paths leading from the semiconductor device512and other semiconductor devices (not shown) on the semiconductor substrate502.

As illustrated by the top and cross-sectional views1000A,1000B ofFIGS. 10A and 10B, a first memory film1002aand a second memory film1002bare deposited over the interconnect structure504ofFIGS. 9A and 9B. For ease of illustration, only a top portion of the interconnect structure504corresponding to the lower interconnect dielectric layer506ais shown. A remainder of the interconnect structure504is as shown inFIGS. 9A and 9B. The first and second memory films1002a,1002bcomprise corresponding source/drain layers1004, corresponding source/drain dielectric layers116a, and corresponding array dielectric layers210that are vertically stacked. The source/drain dielectric layers116aare each between two of the source/drain layers1004. The array dielectric layers210are respectively at a top of the first and second memory films1002a,1002band are a different material than portions of the lower interconnect dielectric layer506aextending along a top surface of the lower interconnect dielectric layer506a.

In some embodiments, the source/drain layers1004are or comprise doped polysilicon and/or some other suitable semiconductor material(s). In some embodiments, the source/drain dielectric layers116aare or comprise silicon oxide and/or some other suitable dielectric(s). In some embodiments, the array dielectric layers210are or comprise silicon nitride and/or some other suitable dielectric(s).

While two memory films are deposited stacked over the interconnect structure504, more or less memory films may be deposited in alternative embodiments. For example, the second memory film1002bmay be omitted, such that only a single memory film may be deposited. As another example, the second memory film1002bmay be repeatedly deposited, such that three or more memory films may be deposited. In alternative embodiments, to form a 3D memory array according toFIG. 4A, barrier layers406and metal layers404may be deposited stacked with the source/drain layers1004, the source/drain dielectric layers116a, and the array dielectric layers210. In alternative embodiments, to form a 3D memory array according toFIG. 4C, silicide layers may be deposited stacked with the source/drain layers1004, the source/drain dielectric layers116a, and the array dielectric layers210. In alternative embodiments, to form a 3D memory array according toFIG. 4D, silicide layers may be deposited in place of the source/drain layers1004.

As illustrated by the top and cross-sectional views1100A,1100B ofFIGS. 11A and 11B, the first and second memory films1002a,1002bare patterned to form a plurality of trenches1102. The trenches1102are laterally elongated in parallel in a direction (e.g., a Y direction) transverse to the cross-sectional view1100B ofFIG. 11B. In some embodiments, the direction is the direction that columns of the 3D memory array being formed extend and/or the trenches1102have the same or substantially the same dimensions as each other. Further, the patterning divides the source/drain layers1004into lower source/drain regions106land upper source/drain regions106u. The lower source/drain regions106lare at lower sides of corresponding source/drain dielectric layers, and the upper source/drain regions106uare at upper sides of corresponding source/drain dielectric layers. The patterning may, for example, be performed by a photolithography/etching process and/or some other suitable patterning process. The photolithography/etching process may, for example, use dry etching and/or some other suitable type of etching.

As illustrated by the top and cross-sectional views1200A,1200B ofFIGS. 12A and 12B, the source/drain dielectric layers116aare laterally recessed through the trenches1102. The recessing recesses sidewalls of the source/drain dielectric layers116a, relative to neighboring sidewalls of the lower and upper source/drain regions106l,106u, to form recesses1202with a lateral depth Dr. Note that the recesses1202are shown in phantom inFIG. 12A. In some embodiments, the lateral depth Dris about 10-30 nanometers, about 10-20 nanometers, about 20-30 nanometers, or some other suitable depth. The lateral recessing may, for example, be performed by wet etching and/or some other suitable type of etching.

As illustrated by the top and cross-sectional views1300A,1300B ofFIGS. 13A and 13B, a semiconductor layer1302is formed filling the trenches1102(see, e.g.,FIGS. 12A and 12B) and the recesses1202(see, e.g.,FIGS. 12A and 12B). In some embodiments, the semiconductor layer1302is doped. In alternative embodiments, the semiconductor layer1302is undoped. In some embodiments, the semiconductor layer1302is or comprises polysilicon and/or some other suitable semiconductor material(s).

A process for forming the semiconductor layer1302may, for example, comprise: 1) depositing the semiconductor layer1302; and 2) performing a planarization into the semiconductor layer1302until the array dielectric layer210of the second memory film1002bis reached. Alternatively, other suitable processes may form the semiconductor layer1302. The planarization may, for example, be performed by a chemical mechanical polish (CMP) or some other suitable planarization.

While the semiconductor layer1302is formed fully filling the trenches1102and the recesses1202, the semiconductor layer1302may be formed lining and partially filling the trenches1102and the recesses1202in alternative embodiments. Such alternative embodiments may, for example, arise while forming a 3D memory array according toFIGS. 3C-3E. In some embodiments in which the semiconductor layer1302is formed lining and partially filling the trenches1102and the recesses1202, a gate dielectric layer is formed lining and partially filling the trenches and the recesses1202over the semiconductor layer1302. Such alternative embodiments may, for example, arise while forming a 3D memory array according toFIGS. 3D and 3E.

As illustrated by the top and cross-sectional views1400A,1400B ofFIGS. 14A and 14B, the trenches1102are cleared. However, the recesses1202(see, e.g.,FIGS. 12A and 12B) are not cleared or are minimally cleared. By doing so, a plurality of semiconductor channels104are formed localized to the recesses1202from the semiconductor layer1302. The clearing may, for example, be performed by dry etching and/or some other suitable type of etching. Alternatively, other suitable processes for clearing the trenches1102may, for example, be performed. In some embodiments, the array dielectric layer210of the second memory film1002bis used as a mask during the etching.

As illustrated by the top and cross-sectional views1500A,1500B ofFIGS. 15A and 15B, a gate dielectric layer110, a ferroelectric layer112, and a control electrode layer1502(collectively the trench layers) are formed filling the trenches1102. The gate dielectric layer110is formed lining and partially filling the trenches1102, and the ferroelectric layer112is formed lining and partially filling the trenches1102over the gate dielectric layer110. The control electrode layer1502is formed filling a remainder of the trenches1102over the ferroelectric layer112. In some embodiments, the control electrode layer1502is or comprises titanium nitride, doped polysilicon, tantalum nitride, tungsten, some other suitable conductive material(s), or any combination of the foregoing. In some embodiments, the ferroelectric layer112is or comprises doped hafnium oxide (e.g., doped with aluminum, silicon, zirconium, lanthanum, strontium, or the like) and/or some other suitable ferroelectric material(s). In some embodiments, the gate dielectric layer110is or comprises silicon oxide, aluminum oxide, silicon oxynitride, silicon nitride, lanthanum oxide, strontium titanium oxide, undoped hafnium oxide, or some other suitable dielectric material(s), or any combination of the foregoing. In some embodiments, the gate dielectric layer110is or comprises a high k dielectric layer.

A process for forming the trench layers may, for example, comprise: 1) depositing the gate dielectric layer110; 2) depositing the ferroelectric layer112over the gate dielectric layer110; 3) depositing the control electrode layer1502over the ferroelectric layer112; and 4) performing a planarization into the control electrode layer1502until the ferroelectric layer112is reached. Alternatively, other suitable processes may form the trench layers. For example, the planarization may alternatively be performed until the second memory film1002bis reached. The planarization may, for example, be performed by a CMP or some other suitable planarization.

As illustrated by the top and cross-sectional views1600A,1600B ofFIGS. 16A and 16B, the control electrode layer1502is patterned to form a plurality of gate isolation openings1602dividing the control electrode layer1502into a plurality of control gate electrodes114. The control gate electrodes114are arranged in a plurality of rows and a plurality of columns, such that a control gate electrode occurs every other column along each row and such that a control gate electrode occurs every other row along each column. Further, the control gate electrodes114are staggered along neighboring columns and neighboring rows, such that a pitch Pyof the control gate electrodes114in the Y direction spans a row and a pitch Pxof the control gate electrodes114in the X direction spans two columns. In some embodiments, the control gate electrodes114have individual widths Wcgthat are less than about half the Y-direction pitch Py.

The patterning may, for example, be performed by a photolithography/etching process and/or some other suitable patterning process. The photolithography/etching process may, for example, use the ferroelectric layer112as an etch stop and/or may, for example, use dry etching and/or some other suitable type of etching.

Dividing the control electrode layer1502into the control gate electrodes114completes a first memory array204aand a second memory array204b. The first and second memory arrays204a,204bare vertically stacked and are made up of a plurality of MFIS memory cells102. In some embodiments, the MFIS memory cells102are as described atFIGS. 1A-1Cand/orFIGS. 2A-2D. Each of the MFIS memory cells102has a localized portion of the ferroelectric layer112, which has a polarity representing a bit of data.

During program and erase operations for any one of the MFIS memory cells102, the lower and upper source/drain regions106l,106uof the MFIS memory cell are electrically coupled in parallel and used as a proxy for the semiconductor channel104of the MFIS memory cell. A program voltage is applied from the control gate electrode114of the MFIS memory cell to the semiconductor channel104(e.g., via the lower and upper source/drain regions106l,106u) to set the polarity to a programmed state. Further, an erase voltage having an opposite polarity as the program voltage is applied from the control gate electrode114to the semiconductor channel104(e.g., via the lower and upper source/drain regions106l,106u) to set the polarity to an erased state. The programmed state may, for example, represent a binary “1”, whereas the erased state may, for example, represent a binary “0”, or vice versa.

The ferroelectric layer112screens an electric field produced by the control gate electrode114differently depending whether the polarity is in the programmed state or the erased state. As such, the MFIS memory cell has a programmed threshold voltage and an erased threshold voltage respectively while the polarity is in the programmed and erased states. During a read operation of the MFIS memory cell, the control gate electrode114is biased with a read voltage between the programmed and erased threshold voltages and the resistance of the semiconductor channel104is measured. Depending upon whether the semiconductor channel104conducts, the polarity is either in the programmed or erased state.

By using the ferroelectric layer112for data storage, as opposed to a silicon nitride layer, there is no dependence on carrier tunneling for the program and erase operations. As such, program and erase voltages may be reduced and program and erase speeds may be increased. For example, the program and erase voltages may be reduced to less than about 5 volts and/or program and erase speeds may be reduced to less than about 100 nanoseconds. Other suitable values are, however, amenable. By reducing the program and erase voltages and by increasing the program and erase speeds, power consumption may be reduced.

As illustrated by the top and cross-sectional views1700A,1700B ofFIGS. 17A and 17B, an inter-gate dielectric layer116bis formed filling the gate isolation openings1602(see, e.g.,FIGS. 16A and 16B). The inter-gate dielectric layer116bmay, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). A process for forming the inter-gate dielectric layer116bmay, for example, comprise: 1) depositing an inter-gate dielectric layer116bfilling the gate isolation openings1602; and 2) performing a planarization into the inter-gate dielectric layer116buntil the ferroelectric layer112is exposed. In alternative embodiments, the inter-gate dielectric layer116bis formed by some other suitable process. Further, in alternative embodiments, the planarization stops before the ferroelectric layer112is exposed and top electrode vias hereafter formed are formed in a top portion of the inter-gate dielectric layer116b.

As illustrated by the top and cross-sectional views1800A,1800B ofFIGS. 18A and 18B, the interconnect structure504is completed. An upper interconnect dielectric layer506bis formed over the first and second memory arrays204a,204b, and a plurality of upper wires508band a plurality of upper vias510bare formed stacked in the upper interconnect dielectric layer506b. At least some of the upper wires508bdefine top word lines TWL, and at least some of the upper vias510bdefine top electrode vias TEV. The top word lines TWL extend correspondingly along rows of the control gate electrodes114, and the top electrode vias TEV extend respectively from the top word lines TWL respectively to the control gate electrodes114.

WhileFIGS. 9A and 9BthroughFIGS. 18A and 18Bare described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS. 9A and 9BthroughFIGS. 18A and 18Bare not limited to the method but rather may stand alone separate of the method. WhileFIGS. 9A and 9BthroughFIGS. 18A and 18Bare described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS. 9A and 9BthroughFIGS. 18A and 18Billustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments.

With reference toFIG. 19, a block diagram1900of some embodiments of the method ofFIGS. 9A and 9BthroughFIGS. 18A and 18Bis provided.

At1902, an interconnect structure is partially formed over a semiconductor device and a semiconductor substrate. See, for example,FIGS. 9A and 9B.

At1904, a memory film is deposited over the interconnect structure, wherein the memory film comprises a pair of source/drain layers and a source/drain dielectric layer between the source/drain layers. See, for example,FIGS. 10A and 10B.

At1906, the memory film is patterned to form a plurality of trenches extending laterally in parallel in a first direction. See, for example,FIGS. 11A and 11B.

At1908, sidewalls of the source/drain dielectric layer are laterally recessed in the trenches in a second direction transverse to the first direction to form recesses. See, for example,FIGS. 12A and 12B.

At1910, a semiconductor layer is deposited filling the trenches and the recesses. See, for example,FIGS. 13A and 13B.

At1912, the semiconductor layer is patterned to clear the semiconductor layer from the trenches while the semiconductor layer persists in the recesses. See, for example,FIGS. 14A and 14B.

At1914, a gate dielectric layer and a ferroelectric layer are deposited lining and partially filling the trenches. See, for example,FIGS. 15A and 15B.

At1916, a control electrode layer is deposited filling a remainder of the trenches. See, for example,FIGS. 15A and 15B.

At1918, the control electrode layer is patterned to divide the control electrode layer into a plurality of control gate electrodes in a plurality of rows and a plurality of columns. See, for example,FIGS. 16A and 16B.

At1920, the interconnect structure is completed over the memory film and the control gate electrodes. See, for example,FIGS. 17A and 17BandFIGS. 18A and 18B.

With reference toFIGS. 20A and 20BthroughFIGS. 27A and 27B, a series of views of some embodiments of a method for forming an IC comprising a 3D memory array of MFIS memory cells is provided in which word lines are respectively at a bottom and a top of the 3D memory array. Figures labeled with a suffix of B illustrate cross-sectional views along line K, L, or M (whichever is present) in like-numbered figures with a suffix of A. Figures with a suffix of A illustrate top views along line K, L, or M (whichever is present) in like-numbered figures with a suffix of B. The method may, for example, be employed to form the IC ofFIGS. 8A and 8Bor other suitable ICs.

As illustrated by the top and cross-sectional views2000A,2000B ofFIGS. 20A and 20B, a semiconductor device512and a trench isolation structure520are formed on a semiconductor substrate502as illustrated and described atFIGS. 9A and 9B.

Also illustrated by the top and cross-sectional views2000A,2000B ofFIGS. 20A and 20B, an interconnect structure504is partially formed over the semiconductor device512and the semiconductor substrate502. The interconnect structure504comprises a lower interconnect dielectric layer506a, a cap dielectric layer802, a plurality of lower wires508a, and a plurality of lower vias510a. The lower wires508aand the lower vias510aare alternatingly stacked in the lower interconnect dielectric layer506aand define conductive paths leading from the semiconductor device512and other semiconductor devices (not shown) on the semiconductor substrate502. Further, the lower wires508adefine bottom word lines BWL at a top of the interconnect structure504, and the lower vias510adefine bottom electrode vias BEV respectively overlying the bottom word lines BWL. The cap dielectric layer802covers the lower interconnect dielectric layer506aand the bottom electrode vias BEV.

As illustrated by the top and cross-sectional views2100A,2100B ofFIGS. 21A and 21B, the acts atFIGS. 10A and 10BthroughFIGS. 14A and 14Bare performed on the interconnect structure504ofFIGS. 20A and 20B. For ease of illustration, only a top portion of the interconnect structure504is shown. A remainder of the interconnect structure504is as shown inFIGS. 20A and 20B.

According to the acts atFIGS. 10A and 10BthroughFIGS. 14A and 14B, a first memory film1002aand a second memory film1002bare deposited as illustrated and described atFIGS. 10A and 10B. The first and second memory films1002a,1002bare patterned to form a plurality of trenches1102as illustrated and described atFIGS. 11A and 11B. The source/drain dielectric layers116aare laterally recessed through the trenches1102to form recesses1202(see, e.g.,FIGS. 12A and 12B) as illustrated and described atFIGS. 12A and 12B. A semiconductor layer1302is formed filling the trenches1102and the recesses1202as illustrated and described atFIGS. 13A and 13B. The trenches1102are cleared as illustrated and described atFIGS. 14A and 14B.

As illustrated by the top and cross-sectional views2200A,2200B ofFIGS. 22A and 22B, a gate dielectric layer110, a ferroelectric layer112, and a spacer layer2202are formed lining and partially filling the trenches1102. The ferroelectric layer112is formed lining and partially filling the trenches1102over the gate dielectric layer110, and the spacer layer2202is formed lining and partially filling the trenches1102over the ferroelectric layer112. The spacer layer2202may, for example, be or comprise silicon nitride and/or some other suitable dielectric(s).

As illustrated by the top and cross-sectional views2300A,2300B ofFIGS. 23A and 23B, an etching process is performed into the spacer layer2202, the ferroelectric layer112, the gate dielectric layer110, and the cap dielectric layer802to extend the trenches1102to the bottom electrode vias BEV. Initially, the spacer layer2202is etched back and spacers804are formed from the spacer layer2202along sidewalls of the trenches1102. Thereafter, the spacers804and the array dielectric layer210of the second memory film1002bserve as a mask while etching through the ferroelectric layer112, the gate dielectric layer110, and the cap dielectric layer802. These two steps of the etching process may, for example, be performed by the same etch or by different etches.

In alternative embodiments, instead of forming the spacer layer2202atFIGS. 22A and 22Band subsequently performing the etching process atFIGS. 23A and 23B, a photolithography/etching process may be performed to form openings at bottoms of the trenches1102that extend respectively to the bottom electrode vias BEV. The method may then proceed as described hereafter. These alternative embodiments may, for example, be employed to form the IC ofFIGS. 7A and 7Bor other suitable ICs.

As illustrated by the top and cross-sectional views2400A,2400B ofFIGS. 24A and 24B, a control electrode layer1502is formed filling the trenches1102. A process for forming the control electrode layer1502may, for example, comprise: 1) depositing the control electrode layer1502; and 2) performing a planarization into the control electrode layer1502until the array dielectric layer210of the second memory film1002bis reached. Alternatively, other suitable processes may form the control electrode layer1502. The planarization may, for example, be performed by a CMP or some other suitable planarization.

As illustrated by the views ofFIGS. 25A and 25BandFIGS. 26A and 26B, the acts atFIGS. 16A and 16BandFIGS. 17A and 17Bare performed. At the top and cross-sectional views2500A,2500B ofFIGS. 25A and 25B, the control electrode layer1502is patterned to form a plurality of gate isolation openings1602dividing the control electrode layer1502into a plurality of control gate electrodes114as illustrated and described atFIGS. 16A and 16B. At the top and cross-sectional views2600A,2600B ofFIGS. 26A and 26B, an inter-gate dielectric layer116bis formed filling the gate isolation openings1602(see, e.g.,FIGS. 25A and 25B) as illustrated and described atFIGS. 17A and 17B.

As illustrated by the top and cross-sectional views2700A,2700B ofFIGS. 27A and 27B, the interconnect structure504is completed as described atFIGS. 18A and 18B. However, in contrast withFIGS. 18A and 18B, top word lines TWL and top electrode vias TEV are formed at even numbered rows or odd numbered rows, but not both.

WhileFIGS. 20A and 20BthroughFIGS. 27A and 27Bare described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS. 20A and 20BthroughFIGS. 27A and 27Bare not limited to the method but rather may stand alone separate of the method. WhileFIGS. 20A and 20BthroughFIGS. 27A and 27Bare described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS. 20A and 20BthroughFIGS. 27A and 27Billustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments.

With reference toFIG. 28, a block diagram2800of some embodiments of the method ofFIGS. 20A and 20BthroughFIGS. 27A and 27Bis provided.

At2802, an interconnect structure is partially formed over a semiconductor device and a semiconductor substrate, wherein the interconnect structure comprises bottom word lines and bottom electrode vias respectively overlying the bottom word lines at a top of the interconnect structure. See, for example,FIGS. 20A and 20B.

At2804, a memory film is deposited over the interconnect structure, wherein the memory film comprises a pair of source/drain layers and a source/drain dielectric layer between the source/drain layers. See, for example,FIGS. 21A and 21BandFIGS. 10A and 10B.

At2806, the memory film is patterned to form a plurality of trenches extending laterally in parallel in a first direction. See, for example,FIGS. 21A and 21BandFIGS. 11A and 11B.

At2808, sidewalls of the source/drain dielectric layer are laterally recessed in the trenches in a second direction transverse to the first direction to form recesses. See, for example,FIGS. 21A and 21BandFIGS. 12A and 12B.

At2810, a semiconductor layer is deposited filling the trenches and the recesses. See, for example,FIGS. 21A and 21BandFIGS. 13A and 13B.

At2812, the semiconductor layer is patterned to clear the semiconductor layer from the trenches while the semiconductor layer persists in the recesses. See, for example,FIGS. 21A and 21BandFIGS. 14A and 14B.

At2814, a gate dielectric layer, a ferroelectric layer, and a spacer layer are deposited lining and partially filling the trenches. See, for example,FIGS. 22A and 22B.

At2816, an etch is performed to etch back the spacer layer, the ferroelectric layer, and the gate dielectric layer and to extend the trenches to the bottom electrode vias. See, for example,FIGS. 23A and 23B.

At2818, a control electrode layer is deposited filling the trenches. See, for example,FIGS. 24A and 24B.

At2820, the control electrode layer is patterned to divide the control electrode layer into a plurality of control gate electrodes in a plurality of rows and a plurality of columns. See, for example,FIGS. 25A and 25B.

At2822, the interconnect structure is completed over the memory film and the control gate electrodes. See, for example,FIGS. 26A and 26BandFIGS. 27A and 27B.

In some embodiments, the present disclosure provides a memory device including: a lower source/drain region and an upper source/drain region overlying the lower source/drain region; a semiconductor channel that overlies the lower source/drain region and that underlies the upper source/drain region; a control gate electrode extending along a sidewall of the semiconductor channel and along individual sidewalls of the lower and upper source/drain regions; and a gate dielectric layer and a ferroelectric layer separating the control gate electrode from the semiconductor channel and the lower and upper source/drain regions. In some embodiments, the semiconductor channel is completely and laterally between opposite sidewalls of the upper source/drain region, wherein the opposite sidewalls respectively face and face away from the control gate electrode. In some embodiments, the control gate electrode is fully uncovered by the upper source/drain region. In some embodiments, the sidewall of the semiconductor channel is offset from the individual sidewalls of the lower and upper source/drain regions. In some embodiments, the ferroelectric layer extends along the sidewall of the semiconductor channel from top to bottom and further extends along the individual sidewalls of the lower and upper source/drain regions from top to bottom. In some embodiments, the memory device further includes a second semiconductor channel and a source/drain dielectric layer overlying the lower source/drain region and underlying the upper source/drain region, wherein the source/drain dielectric layer is between the semiconductor channel and the second semiconductor channel. In some embodiments, the memory device further includes a second semiconductor channel bordering the control gate electrode on an opposite side of the control gate electrode as the semiconductor channel, wherein the ferroelectric layer and the gate dielectric layer wrap around a bottom of the control gate electrode and separate the control gate electrode from the second semiconductor channel.

In some embodiments, the present disclosure provides another memory device including: a first semiconductor channel; a second semiconductor channel overlying the first semiconductor channel; and a control gate electrode and a ferroelectric layer bordering the first and second semiconductor channels, wherein the ferroelectric layer separates the control gate electrode from the first and second semiconductor channels. In some embodiments, the memory device further includes a high k gate dielectric layer separating the ferroelectric layer from the first and second semiconductor channels. In some embodiments, the control gate electrode, the ferroelectric layer, and the first semiconductor channel partially define a MFIS FET. In some embodiments, the memory device further includes a second control gate electrode laterally spaced from the control gate electrode and also bordering the first and second semiconductor channels, wherein the ferroelectric layer separates the second control gate electrode from the first and second semiconductor channels. In some embodiments, the memory device further includes a lower source/drain region and an upper source/drain region that are vertically stacked with the second semiconductor channel. In some embodiments, the upper source/drain region completely covers the first and second semiconductor channels. In some embodiments, the control gate electrode bulges individually at the first and second semiconductor channels.

In some embodiments, the present disclosure provides a method for forming a memory device, the method including: depositing a memory film over a substrate, wherein the memory film includes a pair of source/drain layers and a source/drain dielectric layer between the source/drain layers; performing a first etch into the memory film to form a trench through memory film; recessing a sidewall of the source/drain dielectric layer relative to sidewalls of the source/drain layers through the trench to form a recess; depositing a semiconductor layer filling the recess and the trench; performing a second etch into the semiconductor layer to clear the semiconductor layer from the trench; depositing a ferroelectric layer lining the trench and further lining the semiconductor layer at the recess; and depositing an electrode layer filling the trench over the ferroelectric layer. In some embodiments, the method further includes performing a third etch into the electrode layer to form a plurality of control gate electrodes bordering the semiconductor layer at the recess. In some embodiments, the method further includes depositing a high k gate dielectric layer lining the trench between the depositing of the semiconductor layer and the depositing of the ferroelectric layer. In some embodiments, the semiconductor layer is deposited on the sidewall of the source/drain dielectric layer and the sidewalls of the source/drain layers, wherein the semiconductor layer is cleared from the sidewalls of the source/drain layers but not the sidewall of the source/drain dielectric layer by the second etch. In some embodiments, the method further includes depositing a second memory film over the memory film, wherein the second memory film includes a pair of second source/drain layers and a second source/drain dielectric layer between the second source/drain layers, wherein the first etch is also performed into the second memory film, and wherein the recessing recesses a sidewall of the second source/drain dielectric layer relative to sidewalls of the second source/drain layers through the trench to form a second recess simultaneous with the recess. In some embodiments, the recessing recesses a second sidewall of the source/drain dielectric layer relative to second sidewalls of the source/drain layers through the trench to form a second recess, and wherein the second recess is on an opposite side of the trench as the recess.