CMOS analog circuits having a triode-based active load

A continuous time linear equalizer (CTLE) is disclosed. The CTLE may include a first cell configured to buffer and invert an input signal and generate a first intermediate signal, a second cell configured to buffer and invert the input signal and generate a second intermediate signal, and a first frequency section configured to selectively buffer and invert a first range of frequencies of the second intermediate signal. The first frequency section may include a first tunable resistor configured to provide a first resistance and a third cell coupled to the first tunable resistor configured to generate a third intermediate signal based on the first resistance.

TECHNICAL FIELD

Aspects of the present disclosure relate generally to CMOS analog circuits, and more specifically to CMOS analog circuits having a triode-based active load.

BACKGROUND

Many modern circuits receive and/or process analog signals for buffering, filtering, amplification and the like. For example, an analog circuit may buffer an analog signal for sampling by an analog-to-digital converter (ADC). In another example, an equalizing circuit may buffer a high-speed analog communication signal to emphasize frequency content which was attenuated in a communication channel to enable data recovery. Analog signals may have varying bandwidths. Therefore, analog buffers and equalizing circuits capable of handling varying bandwidths are very desirable.

SUMMARY

This Summary is provided to introduce in a simplified form a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Moreover, the systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.

One innovative aspect of the subject matter described in this disclosure can be used to equalize analog signals. In some implementations, an continuous time linear equalizer (CTLE) may include a first cell configured to generate a first intermediate signal by buffering and inverting an input signal, a second cell configured to generate a second intermediate signal by buffering and inverting the input signal, and a first frequency section configured to selectively generate a third intermediate signal based at least in part on the second intermediate signal. The first frequency section may include a first tunable resistor configured to provide a first resistance, and a third cell configured to generate the third intermediate signal by buffering and inverting the second intermediate signal based on the first resistance, wherein the first resistance determines, at least in part, a first range of frequencies buffered by the third cell. The CTLE may also include an output configured to provide an equalized output signal based at least in part on a sum of the first intermediate signal and the third intermediate signal.

Another innovative aspect of the subject matter described in this disclosure can be implemented as a method for operating a continuous time linear equalizer (CTLE) comprising generating a first intermediate signal by buffering and inverting an analog signal, generating a second intermediate signal by buffering and inverting the analog signal, generating a third intermediate signal by buffering and inverting the second intermediate signal based on a first resistance, wherein the first resistance determines, at least in part, a first range of frequencies, and wherein the first resistance is provided by a first tunable resistor, and summing the first intermediate signal with the third intermediate signal to generate an equalized signal.

DETAILED DESCRIPTION

Implementations of the subject matter described in this disclosure may be used to buffer analog signals. In some implementations, an analog signal buffer may include an active load having at least one PMOS transistor coupled to at least one NMOS transistor, where the transistors are configured to operate in a triode region. The PMOS transistors and the NMOS transistors may provide an effective resistance to load the output of the analog signal buffer.

Implementations of the subject matter described in this disclosure also may be used to equalize analog signals. In some implementations, a continuous time linear equalizer (CTLE) may include a tunable resistor having at least one PMOS transistor coupled to at least one NMOS transistor, where the transistors are configured to operate in the triode region. The PMOS transistors and the NMOS transistors may enable the CTLE to emphasize particular frequencies of the analog signals.

Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. Analog signal buffers using the active load may have a smaller footprint compared to analog signal buffers that use a conventional resistor to load the output of the signal buffer. Some aspects of the present disclosure may track process, voltage, and temperature changes that may affect the analog signal buffer. Still further, a CTLE using one or more tunable resistors may be tuned to operate on different analog signals, thereby reducing the number of CTLEs needed to equalize analog signals of varying bandwidths.

In the following description, numerous specific details are set forth such as examples of specific components, circuits, and processes to provide a thorough understanding of the present disclosure. The term “coupled” as used herein means coupled directly to or coupled through one or more intervening components or circuits. Also, in the following description and for purposes of explanation, specific nomenclature and/or details are set forth to provide a thorough understanding of the example implementations. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the example implementations. In other instances, well-known circuits and devices are shown in block diagram form to avoid obscuring the present disclosure. Any of the signals provided over various buses described herein may be time-multiplexed with other signals and provided over one or more common buses. Additionally, the interconnection between circuit elements or software blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be a single signal line, and each of the single signal lines may alternatively be buses, and a single line or bus might represent any one or more of a myriad of physical or logical mechanisms for communication between components. The example implementations are not to be construed as limited to specific examples described herein but rather to include within their scope all implementations defined by the appended claims.

FIG. 1Ashows a simplified block diagram of an analog signal buffer100. The analog signal buffer100may include a transconductance cell110and an active load120. The transconductance cell110may include a plurality of NMOS and/or PMOS transistors configured to receive an input voltage VIN and to generate an output voltage VOUT. The output of the transconductance cell110is coupled to the active load120. The term “load” may refer to any device or circuit that receives output signals from another device or circuit. The active load120may provide a tunable load, with respect to the transconductance cell110, to extend the functional bandwidth of the analog signal buffer100. In some implementations, the active load120may receive an output current IOUT (not shown for simplicity) and provide the output voltage VOUT. As used herein, the term “cell” may refer to one or more circuits or devices that include at least one connection or port. For example, the transconductance cell110may include two ports (VIN and VOUT). Other cells may have one port or three or more ports.

FIG. 1Bshows a simplified block diagram of another implementation of an analog signal buffer150. The analog signal buffer150may include the transconductance cell110and the active load120as described with respect toFIG. 1A. In addition, the analog signal buffer150may include a passive peaking block160.

The passive peaking block160may include inductors161-163. In other implementations, the passive peaking block160may include fewer inductors (for example, only one of the inductors161-163), and/or additional components, such as additional inductors, capacitors and resistors not shown for simplicity. The passive peaking block160may perform different types of peaking such as, but not limited to, shunt peaking, series peaking, and t-coil peaking. The peaking provided by the passive peaking block160may increase the functional bandwidth of the analog signal buffer150beyond the capability of only the active load120.

FIG. 2shows a simplified circuit diagram of an active load200. The active load200may be an implementation of the active load120ofFIG. 1and includes a PMOS transistor201, an NMOS transistor202, and an active feedback structure203. In some implementations, the active load200may include other components and/or devices not shown for simplicity. For example, biasing devices and circuits for the PMOS transistor201and/or the NMOS transistor202may be omitted fromFIG. 2. In some other implementations, each of the transistors201and202may be any technically feasible type of transistor including, but not limited to, bipolar transistors, bipolar junction transistors, and the like.

The PMOS transistor201and the NMOS transistor202may be configured to provide a transconductance gain between nodes N1and N2. In some implementations, the transconductances of the PMOS transistor201and the NMOS transistor202may have a common value gm. In some other implementations, the PMOS transistor201may have a different transconductance than the NMOS transistor202. The source of the PMOS transistor201may be coupled to a power supply voltage, denoted here as VDD. The drain of the PMOS transistor201may be coupled to the drain of the NMOS transistor202, at node N2. The gate of the PMOS transistor201may be coupled to the gate of the NMOS transistor202, at node N1.

The active feedback structure203may include an NMOS transistor204and a PMOS transistor205. In some other implementations, the active feedback structure203may include additional components not shown here for simplicity. For example, biasing devices and circuits may be omitted for clarity. The NMOS transistor204and the PMOS transistor205may each be configured to operate in a triode mode. In some implementations, the gate of the NMOS transistor204may be coupled to VDD and the gate of the PMOS transistor205may be coupled to ground. In the triode mode, each of the NMOS transistor204and the PMOS transistor205may be biased by gate voltages to provide a controllable equivalent resistance between node N1and node N2.

In some implementations, the active load200may receive a signal (shown as Active Load In) from a transconductance cell at node N2. The active load200may approximate an inductive-resistive load250. The inductive-resistive load250may include an inductor251and a resistor252. The resistor252may have a value of 1/(2 gm), where gmis the transconductance associated with each of the PMOS transistor201and the NMOS transistor202. The value of the inductor251may be R/□Twhere R is the equivalent resistance and □Trepresents the transit frequency associated with the NMOS transistor202and/or the PMOS transistor201. In some implementations, the transit frequency is based on bias conditions of the NMOS transistor202and the PMOS transistor201.

FIG. 3shows a simplified circuit diagram of an analog signal buffer300. The analog signal buffer300may be an implementation of the analog signal buffer100ofFIG. 1A or 1Band include a transconductance cell310and an active load320. The transconductance cell310may include a PMOS transistor311and an NMOS transistor312. The active load320may be similar to the active load200and may include the PMOS transistor201, the NMOS transistor202, and the active feedback structure203ofFIG. 2. In some other implementations, each of the PMOS transistors201,205, and311and each of the NMOS transistors202,204, and312may be any technically feasible transistor.

The source of the PMOS transistor311may be coupled to VDD and the drain of the PMOS transistor311may be coupled to the drain of the NMOS transistor312, at node N3. The source of the NMOS transistor312may be coupled to ground. The gates of the PMOS transistor311and the NMOS transistor312may be coupled together, forming an input port at node N4to receive the input signal VIN. The transconductance cell310may provide an output signal VOUT at an output port, node N3.

The active load320may receive the output signal at node N3and extend an operating bandwidth of the transconductance cell310by coupling an equivalent L-R (inductive-resistive load) circuit to the transconductance cell310and loading the output signal VOUT. In some implementations, the active load320may increase an equivalent impedance as frequency increases. As impedance increases, gain of the transconductance cell310may increase and compensate for gain loss at higher frequencies. The active load320may occupy less area and user fewer routing resources compared to conventional inductors and resistors. With the reduced area, other elements associated with the active load320can be positioned closer to the PMOS transistors201and311and the NMOS transistors202and312. Further, since the active load320may include transistors with characteristics (doping, geometry, and the like) similar to those of the PMOS transistor311and the NMOS transistor312, the effects of process, voltage and temperature (PVT) changes to the active load320may track the effects of PVT changes to the PMOS transistor311and the NMOS transistor312. In some implementations, the active load320may be tunable, enabling the bandwidth of the analog signal buffer300to be extended beyond what would be possible with a fixed active load320.

The combination of the transconductance cell310and the active load320may be illustrated with the equivalent circuit350. The equivalent circuit350may include a buffer351and an active load352. The buffer351may include the transconductance cell310(not shown for simplicity). The active load352may include an inductor354and a resistor355. The inductor354may have a value of R/□T. As described with respect toFIG. 2, R is the equivalent resistance provided by the NMOS transistor204and the PMOS transistor205and □Tmay be associated with the NMOS transistor202and the PMOS transistor201. The resistor355may have a value of 1/(2 gm), where gmis the transconductance associated with the PMOS transistor201and the NMOS transistor202.

In some implementations, the analog signal buffer300may be used to buffer differential signals. For example, a first analog signal buffer300may be used for the first half of a differential signal pair and a second analog signal buffer300may be used for the second half of a differential signal pair.

FIG. 4shows a simplified circuit diagram of a transimpedance amplifier400. The transimpedance amplifier400may include a transconductance cell410and a transimpedance cell420. The transconductance cell410is similar to the transconductance cell310and may include the PMOS transistor311and the NMOS transistor312ofFIG. 3. An input signal VIN for the transimpedance amplifier400may be received by the transconductance cell410at an input port, node N5. An output signal of the transconductance cell410is provided to an output port, node N6.

The transimpedance cell420may include a PMOS transistor421, an NMOS transistor422and the active feedback structure203described with respect toFIG. 2. The source of the PMOS transistor421may be coupled to VDD and the drain of the PMOS transistor421may be coupled to the drain of the NMOS transistor422, at node N7. The gate of the PMOS transistor421may be coupled to the gate of the NMOS transistor422, at node N6. The transimpedance cell420may receive the output signal from the transconductance cell410, at node N6.

The active feedback structure203may include the NMOS transistor204and the PMOS transistor205which may be configured to operate in the triode mode. Thus, the active feedback structure203may provide an equivalent feedback resistance from node N7to node N6. The active feedback structure203may have a smaller footprint than a conventional resistor. Further, the active feedback structure203may track how changes in PVT affect the PMOS transistors311and421and the NMOS transistors312and422. Moreover, the active feedback structure203may be tunable, enable varying amounts of resistance in the feedback path. Example implementations of a tunable active feedback structure203are described below with respect toFIGS. 5 and 6.

FIG. 5shows a simplified circuit diagram of another implementation of a transimpedance cell500. The transimpedance cell500may be similar to the transimpedance cell420ofFIG. 4. In some implementations, the transimpedance cell500may be used to implement some or all of the active load320. The transimpedance cell500may include a PMOS transistor501, an NMOS transistor502, and active feedback structures503,504, and505. The PMOS transistor501and the NMOS transistor502may be configured to operate as a transconductance buffer. Thus, the source of the PMOS transistor501may be coupled to VDD, the drain of the PMOS transistor501may be coupled to the drain of the NMOS transistor502, at node N8, and the source of the NMOS transistor502may be coupled to ground. The gate of the PMOS transistor501may be coupled to the gate of the NMOS transistor502, at node N9. In some implementations, the transimpedance cell500may receive an input signal VIN at node N9and provide an output signal VOUT at node N8.

The active feedback structures503-505may be similar to the active feedback structure203ofFIG. 2. Biasing circuits for the active feedback structures503-505are omitted for clarity. In one implementation, the active feedback structure503may be enabled (e.g., biased to operate) thereby allowing the transimpedance cell500to operate similarly to the transimpedance cell420ofFIG. 4. Thus, the active feedback structure503may provide a first equivalent resistance between nodes N8and N9. In another implementation, the active feedback structures504and505may be enabled to provide a second effective resistance between nodes N8and N9. For example, the effective resistance of the active feedback structure504may be added to the effective resistance of the active feedback structure505to provide a greater effective resistance between the nodes N8and N9compared to the active feedback structure503.

In some other implementations, other combinations of the active feedback structures503-505may be used to provide different effective resistances between the nodes N8and N9. For example, the active feedback structures503-505may be enabled simultaneously to provide two parallel resistance paths between the nodes N8and N9. This parallel resistance may have an equivalent resistance that is less than either the effective resistance of the active feedback structure503or the combined effective resistance of the active feedback structures504and505.

In some implementations, each of the active feedback structures503-505may include transistors with similar device characteristics including, but not limited to, channel width, channel length, channel area, threshold voltage, bias voltage, or any other feasible device characteristic. In some other implementations, each of the active feedback structures503-505may have different device characteristics. Implementations with different device characteristics enable the active feedback structures503-505to provide different effective resistances. Although only three active feedback structures503-505are described in this example, in some other implementations, the transimpedance cell500may include any feasible number of active feedback structures.

When the transimpedance cell500is used to implement the active load320by coupling N8(instead of N9) to a transconductance cell output, the effective inductance of the active load cell may be modified by changing the effective resistance between the nodes N8and N9. As described herein, the effective resistance may be changed by enabling different combinations of the active feedback structures503-505and/or using active feedback structures503-505with different device characteristics. When the transimpedance cell500is used to implement the transimpedance cell420, the active feedback structures503-505provide an effective feedback resistance between the nodes N8and N9.

FIG. 6shows a simplified circuit diagram of another implementation of a transimpedance cell600The transimpedance cell600may include a PMOS transistor601, an NMOS transistor602, an active feedback structure603, and a digital-to-analog converter (DAC)604. The source of the PMOS transistor601may be coupled to VDD, the drain of the PMOS transistor601may be coupled to the drain of the NMOS transistor602, at node N10, and the source of the NMOS transistor602may be coupled to ground. The gate of the PMOS transistor601may be coupled to the gate of the NMOS transistor602, at node N11. In some implementations, the transimpedance cell600may receive an input signal VIN at node N11and provide an output signal VOUT at node N10.

The active feedback structure603may be similar to the active feedback structure203ofFIG. 2. Thus, the active feedback structure603may include an NMOS transistor605and a PMOS transistor606configured to operate in the triode mode. The source of the NMOS transistor605may be coupled to the source of the PMOS transistor606, at the node N10. The drain of the NMOS transistor605may be coupled to the drain of the PMOS transistor606, at the node N11.

The gates of the NMOS transistor605and the PMOS transistor606may be coupled to the DAC604. In some implementations, the DAC604may control and/or vary the equivalent resistance provided by the active feedback structure603by varying the voltage supplied to the gates of the NMOS transistor605and the PMOS transistor606. In this manner, the transimpedance cell600may share the flexibility of the transimpedance cell500with fewer active feedback structures, thereby saving area and power.

Similar to as described with respect to the transimpedance cell500, the transimpedance cell600may be used to implement the active load320ofFIG. 3. For example, the transimpedance cell600may be used to implement the active load320by coupling N10to the output of a preceding transconductance cell.

FIG. 7shows an illustrative flowchart depicting an example operation700for operating an analog signal buffer. Although described with respect to the analog signal buffer300ofFIG. 3, the operation700may be used to operate the transimpedance amplifier400ofFIG. 4, or any other feasible analog signal buffer or amplifier. In some implementations, the operation described herein may include additional processes, fewer processes, processes in a different order, processes in parallel, and/or some processes that are different.

The analog signal buffer300receives an analog input signal (710). For example, the analog signal buffer may receive an analog input signal VIN from off chip or from adjacent on-chip circuitry. The analog signal buffer300may generate an output signal based on the input signal (712). For example, the analog signal buffer300may generate an output signal VOUT based on an input signal VIN

The analog signal buffer300processes the output signal with one or more active feedback structures (714). For example, the VOUT signal may be processed by the active load320which includes one or more active feedback structures203. In other implementations, the output signal may be processed by the transimpedance cell420which includes one or more active feedback structures203.

In some implementations, the active feedback structure203may also be used to implement a continuous time linear equalizer (CTLE). A CTLE may be used to recover and/or emphasize frequencies in an analog signal, such as a serial communication signal, that may have been lost or attenuated during transmission through a communication channel. The tunable effective resistance of the active feedback structure203may enable the CTLE to operate over a wider bandwidth than a CTLE implemented with fixed resistances and/or capacitors.

FIG. 8shows a simplified diagram of a CTLE800. The CTLE800may include transconductance cells801-803, a negative gain buffer804, a first variable resistor810, a second variable resistor811, a first capacitor821, a second capacitor822, a passive peaking block860, and an active load820. The CTLE800may generate an output signal VOUT based on an input signal VIN. In some implementations, the input signal VIN may be a serial communication signal such as a gigabit signal or a 112G signal. The active load820may be an implementation of the active load200.

In some implementations, the CTLE800may include an all-frequency section830, a mid-frequency section831, and a high-frequency section832. The all-frequency section830may include the transconductance cell801, the mid-frequency section831may include the first variable resistor810, the first capacitor821, and the transconductance cell802, and the high-frequency section832may include the second variable resistor811, the second capacitor822, and the transconductance cell803. In some implementations, the all-frequency section830, the mid-frequency section831, and the high-frequency section832may include other components or devices not shown here for simplicity.

The transconductance cells801-803and the negative gain buffer804may buffer and invert electrical signals. For example, the transconductance cell801may buffer and invert the input signal VIN and provide a first intermediate signal850to node N12, which may function as a summing node. The negative gain buffer804may also buffer and invert the input signal VIN and provide a second intermediate signal851to the mid-frequency section831and the high-frequency section832.

The CTLE800may “equalize” the input signal VIN by selectively emphasizing and/or attenuating certain frequencies of the input signal VIN. The first variable resistor810, the first capacitor821, and the transconductance cell802may buffer and select mid-frequencies of the input signal VIN providing a third intermediate signal852to be subtracted from the first intermediate signal850at node N12. In some implementations, the first variable resistor810and the first capacitor821may select and/or determine a range of frequencies of the input signal VIN (e.g., the mid-frequencies) that are buffered by the transconductance cell802. The negative gain buffer804in combination with the transconductance cell802may provide an inverted signal (with respect to an output signal from the transconductance cell801) to node N12. As a result, by summing the first intermediate signal850and the third intermediate signal852at node N12, the amplitude of the third intermediate signal852is effectively subtracted from the amplitude of the first intermediate signal850at node N12.

Similarly, the second variable resistor811, the second capacitor822, and the transconductance cell803may buffer and select high-frequencies of the input signal VIN providing a fourth intermediate signal853to be subtracted from the first intermediate signal850at node N12. Thus, the output signal VOUT may be based on the first intermediate signal850minus the third intermediate signal852and the fourth intermediate signal853. In this manner, the mid-frequency section831and the high-frequency section832may determine which frequencies of the input signal VIN are to be attenuated. The frequencies of the input signal VIN that are not attenuated are emphasized.

In some implementations, the resistive value of the second variable resistor811may be much smaller than the resistive value of the first variable resistor810. Such a configuration may provide greater separation between the frequencies selected by the mid-frequency section831and the frequencies selected by the high-frequency section832. For example, the resistive value of the second variable resistor811may be orders of magnitude (e.g., ten times) smaller than the resistive value of the first variable resistor810.

In some implementations, the first capacitor821and the second capacitor822may be variable capacitors (not shown for simplicity). Changing the resistances of the first variable resistor810and the second variable resistor811and/or the capacitances of the first capacitor821and the second capacitor822may cause the mid-frequency section831and the high-frequency section832to buffer and select different frequencies of the input signal VIN. In this manner, the CTLE800may be tuned to equalize different analog signals having different bandwidths. In some implementations, the variable resistors810and811and first capacitor821and second capacitor822may allow the CTLE800to equalize gigabit signals, 112G signals, or any other technically feasible signal.

In some implementations, the active load820may extend the operating bandwidth of the CTLE800by coupling an equivalent L-R circuit to node N12and loading the signal at node N12(similar to as described with respect toFIG. 2). In some implementations, the active load820also may include active feedback structures as described with respect toFIGS. 5 and 6. The passive peaking block860may include inductors, capacitors, resistors and the like to emphasize or “peak” one or more frequencies similar to as discussed with respect to the passive peaking block160ofFIG. 1B. Thus, as described inFIG. 1B, VOUT of the CTLE800may be provided by the passive peaking block860. The passive peaking block860may be optional as denoted with dotted lines inFIG. 8. If the passive peaking block860is omitted, then VOUT may be provided at node N12.

FIG. 9shows a simplified schematic diagram of a CTLE900. The CTLE900may be an implementation of the CTLE800ofFIG. 8. The CTLE900may include transconductance cells901-903, a negative gain buffer904, a first tunable resistor910, a second tunable resistor911, a first capacitor921, a second capacitor922, an active load920, a passive peaking block960, and a DAC940. The CTLE900may generate an output signal VOUT based on an input signal VIN. The passive peaking block960may be an implementation of the passive peaking block860ofFIG. 8. The active load920may be an implementation of the active load200. The transconductance cells901-903and the negative gain buffer904may be implementations of the transconductance cells801-803and negative gain buffer804, respectively.

Similar to the CTLE800, the CTLE900may include an all-frequency section930, a mid-frequency section931, and a high-frequency section932. The all-frequency section930may include the transconductance cell901to buffer and invert the input signal VIN and provide a first intermediate signal950to the node N13. The negative gain buffer904may also buffer and invert the input signal VIN and provide a second intermediate signal951to the mid-frequency section931and the high-frequency section932.

The first tunable resistor910may include an NMOS transistor913and a PMOS transistor914configured to operate in the triode mode and provide a variable effective resistance for the mid-frequency section931. The first tunable resistor910may receive and couple the second intermediate signal951to the transconductance cell902and to the first capacitor921. The variable effective resistance from the first tunable resistor910, the first capacitor921, the transconductance cell902may buffer and select mid-frequency components of the input signal VIN and provide a third intermediate signal952for subtraction from the first intermediate signal950at node N13. In a similar manner, the second tunable resistor911may include an NMOS transistor915and a PMOS transistor916configured to operate in the triode mode and provide a variable effective resistance for the high-frequency section932. The variable effective resistance from the second tunable resistor911, the second capacitor922, the transconductance cell903may buffer and select high frequency components of the input signal VIN and provide a fourth intermediate signal953for subtraction from the first intermediate signal950at node N13. In some implementations, the active load920may extend the operating bandwidth of the CTLE900by providing an equivalent L-R circuit to node N13.

The CTLE900may equalize the input signal VIN by selectively emphasizing and/or attenuating certain frequencies of the input signal VIN. The output signal VOUT may be based on the input signal VIN minus frequencies selected by the mid-frequency section931and the high-frequency section932. The frequencies of the input signal VIN that are not attenuated are emphasized. The passive peaking block960may include inductors, capacitors, resistors and the like to emphasize or “peak” one or more frequencies similar to as discussed with respect to the passive peaking block160ofFIG. 1B. Thus, as described inFIG. 1B, VOUT of the CTLE900may be provided by the passive peaking block960. The passive peaking block960may be optional as denoted with dotted lines inFIG. 9. If the passive peaking block960is omitted, then VOUT may be provided at node N13.

The DAC940may be coupled to the first tunable resistor910and the second tunable resistor911. More particularly, the DAC940may provide a first voltage VA to the gates of the NMOS transistors913and915and may provide a second voltage VB to the gates of the PMOS transistors914and916. In some implementations, the DAC940may vary the voltages VA and VB to change the effective resistance provided by the NMOS transistors913and915and the PMOS transistors914and916. This, in turn, may vary the effective resistance provided by the first tunable resistor910and the second tunable resistor911.

In some implementations, the effective resistance of the second tunable resistor911may be smaller than the effective resistance of the first tunable resistor910. Such configuration may provide greater separation between the frequencies attenuated by the mid-frequency section931and the frequencies attenuated by the high-frequency section932. In one implementation, the device area associated with the second tunable resistor911may be greater than the device area associated with the first tunable resistor910, causing the effective resistance of the second tunable resistor911to be smaller than the effective resistance of the first tunable resistor910.

FIG. 10shows an illustrative flowchart depicting an example operation1000for operating a CTLE. Although described with respect to the CTLE900ofFIG. 9, the operation1000may be used to operate any technically feasible CTLE. In some implementations, the operation described herein may include additional processes, fewer processes, processes in a different order, processes in parallel, and/or some processes that are different.

The CTLE900may begin by receiving an analog signal (1002). In some implementations, the analog signal may be a serial communication signal. The CTLE900may generate a first intermediate signal based on the analog signal (1004). For example, the transconductance cell901may receive the input signal VIN and generate the first intermediate signal950.

The CTLE900may generate a second intermediate signal based on the analog signal (1006). For example, the negative gain buffer904may receive the input signal VIN and generate the second intermediate signal951. The CTLE900may generate a third intermediate signal based on a first range of frequencies of the second intermediate signal (1008). For example, the mid-frequency section931may receive the second intermediate signal951and generate a third intermediate signal952based on a first range of frequencies.

The CTLE900may sum the first and third intermediate signals to generate an output signal (1010). For example, the output signal VOUT at node N13may be based on the third intermediate signal952subtracted from the first intermediate signal950. In some implementations, other intermediate signals may be subtracted from the output signal VOUT. For example, the high-frequency section932may receive the second intermediate signal951and generate a fourth intermediate signal953based on a second range of frequencies. The fourth intermediate signal953may also be subtracted from the output signal VOUT. The output signal of the CTLE900may be loaded by an active load (1012). For example, the output signal VOUT may be received by the active load920.

In the foregoing specification, the example implementations have been described with reference to specific example implementations thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.