A single-inductor, multiple-output, DC-DC converter has regulation circuitry that controls switches to alternately charge at least two capacitors associated with at least two DC output voltages via the single inductor from a DC input port. The regulation circuitry determines whether the DC-DC converter is operating in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). In CCM mode, the regulation circuitry regulates the charging duty cycle for a first output voltage and generates the initial charging duty cycle for regulating each other output voltage by scaling the first output voltage duty cycle. In DCM mode, the regulation circuitry independently regulates the charging duty cycles for each output voltage and stores each duty cycle to be used for the next charging period for the same output voltage. The regulation circuitry detects and handles undershoot and overshoot conditions to accelerate recovery at the output ports.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority under 35 U.S.C. § 119 of China application no. 201910587019.3, filed on 1 Jul. 2019, the contents of which are incorporated by reference herein.

BACKGROUND

The present invention relates to a DC-DC converter and, more particularly, to a single-inductor, multiple-output, DC-DC converter.

Single-inductor, multiple-output, DC-DC converters that generate two or more different DC output voltages from a single DC input voltage using a single inductor are known, for example, in U.S. Pat. Nos. 6,204,651 and 6,977,447.

FIG. 4 of the '447 patent shows a single-inductor, two-output, DC-DC boost converter. The boost converter alternates between phases in which energy is transferred from a battery to the inductor and phases in which energy is transferred from the inductor to one of two capacitors that generate the two DC output voltages. In addition, the boost converter alternates between periods of charging the first capacitor associated with the first DC output voltage and periods of charging the second capacitor associated with the second DC output voltage based on which of the two DC output voltages is relatively more deficient compared to its target voltage level.

FIG. 6 of the '447 patent shows a single-inductor, two-output, DC-DC buck converter. The buck converter alternates between a phase in which the inductor and one of two capacitors that generate the two DC output voltages are charged by a battery and a phase in which the inductor is discharged. In addition, the buck converter alternates between periods of charging the first capacitor associated with the first DC output voltage and periods of charging the second capacitor associated with the second DC output voltage based on which of the two DC output voltages is relatively more deficient compared to its target voltage level.

In both of these single-inductor, two-output, DC-DC converters, one of the two DC output voltages is selected to be the primarily regulated output voltage, such that the duty cycle of the charging signal used to charge and discharge the inductor for the primarily regulated output voltage is independently regulated by the converter's regulation module. The initial duty cycle for the charging signal used to charge and discharge the inductor for the other output voltage is generated by scaling the most-recent duty cycle for the primarily regulated output voltage by a fixed scale factor that is based on the different target voltage levels for the two output voltages. Thus, the regulation of the other output voltage is dependent on the regulation of the primarily regulated output voltage.

While the DC-DC converters of the '447 patent perform well with relatively low levels of output ripple when the converters operate in a continuous conduction mode (CCM), these converters do not perform as well and have relatively high levels of output ripple when the converters operate in a discontinuous conduction mode (DCM). In CCM mode, current continuously flows through the inductor. Under certain circumstances (e.g., light output loading), the inductor current may go from positive to negative and then from negative to positive, but, other than the instant when the inductor current transitions from positive to negative or from negative to positive, current continuously flows through the inductor. In DCM mode, on the other hand, the inductor current will reach zero and stay at zero for different periods of time without ever going negative.

Accordingly, it would be advantageous to reduce the output ripple in a single-inductor, multiple output DC-DC converter.

DETAILED DESCRIPTION

Detailed illustrative embodiments of the present invention are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present invention. Embodiments of the present invention may be embodied in many alternative forms and should not be construed as limited to only the embodiments set forth herein. Further, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention.

As used herein, the singular forms “a”, “an”, and “the”, are intended to include the plural forms as well, unless the context clearly indicates otherwise. It further will be understood that the terms “comprises”, “comprising”, “has”, “having”, “includes”, or “including” specify the presence of stated features, steps, or components, but do not preclude the presence or addition of one or more other features, steps, or components. It also should be noted that, in some alternative implementations, the functions/acts noted might occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved. The term “or” is to be interpreted as inclusive unless indicated otherwise.

As described previously, a two-output, DC-DC converter of the '447 patent has a first, so-called “primarily regulated” output voltage and a second, so-called “other” output voltage. The DC-DC converter regulates the duty cycle of the charging signal used to control the primarily regulated output voltage and generates the initial duty cycle for the charging signal used to control the other output voltage by applying a fixed scale factor to the most-recent duty cycle for the primarily regulated output voltage. When such a DC-DC converter operates in CCM mode, the DC-DC converter transitions between periods of charging the capacitors for the two different output voltages with relatively little output ripple in the output voltages. However, when that same fixed scale factor is used to generate the initial duty cycle for the other output voltage when the DC-DC converter is operating in DCM mode, significant output ripple occurs in one or both output voltages following transitions between the capacitor-charging periods for the two output voltages.

According to certain embodiments of the invention, the control of a single-inductor, multiple-output, DC-DC converter is designed to provide reduced output ripple during both CCM and DCM operations.

In one embodiment, the present invention is a single inductor, multiple-output, DC-DC converter that converts a DC input voltage at an input port into at least first and second output voltages at respective first and second output ports. The DC-DC converter comprises an inductor, at least first and second capacitors respectively connected to the first and second output ports, a plurality of switches that selectively connect the input port to either the first capacitor or the second capacitor via the inductor, and regulation circuitry that controls the switches. The regulation circuitry determines whether the DC-DC converter is operating in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). For the CCM mode, (i) the regulation circuitry regulates the first output voltage and (ii) the regulation circuitry regulates the second output voltage dependent on the regulation of the first output voltage. For the DCM mode, (i) the regulation circuitry regulates the first output voltage independent of the regulation of the second output voltage and (ii) the regulation circuitry regulates the second output voltage independent of the regulation of the first output voltage.

Referring now toFIG. 1, a schematic circuit diagram of a single-inductor, two-output, buck-type, DC-DC converter100according to one embodiment of the present invention is shown. The converter100has a single inductor L and two capacitors C1and C2that are selectively charged and discharged based on four switch-control signals V1CTRL, V2CTRL, PCTRL, and NCTRL respectively applied to the gates of four transistor switches Vout1_SW, Vout2_SW, P_SW, and N_SW to convert a DC input voltage DCDC_IN into two different DC output voltages Vout1and Vout2.

For the following discussion, Vout1is assumed to be the “primarily regulated” output voltage, and Vout2is the “other” output voltage. Those skilled in the art will understand how to operate the DC-DC converter100when Vout2is the primarily regulated output voltage and Vout1is the other output voltage.

The switch-control signals V1CTRL and V2CTRL respectively control the p-type switches Vout1_SW and Vout2_SW to control whether the capacitor C1or the capacitor C2is being charged. In particular, to charge capacitor C1(and thereby control Vout1), V1CTRL is driven low to turn on Vout1_SW, and V2CTRL is driven high to turn off Vout2_SW, thereby allowing energy stored in the inductor L to flow to the capacitor C1. Similarly, to charge capacitor C2(and thereby control Vout2), V1CTRL is driven high to turn off Vout1_SW, and V2CTRL is driven low to turn on Vout2_SW, thereby allowing energy stored in the inductor L to flow to the capacitor C2.

The switch-control signals PCTRL and NCTRL respectively control the p-type charging switch P_SW and the n-type discharging switch N_SW to control whether the inductor L is being charged from DCDC_IN or discharged. In particular, to charge the inductor L from DCDC_IN, PCTRL and NCTRL are both driven low to turn on P_SW and turn off N_SW, thereby allowing energy to flow from DCDC_IN to the inductor L and thereby to the currently selected output voltage Vout1or Vout2. Similarly, to discharge the inductor L, PCTRL and NCTRL are both driven high to turn off P_SW and turn on N_SW, thereby stopping charging the inductor, while still allowing energy in the inductor to flow to the currently selected output Vout1or Vout2.

The rest ofFIG. 1shows the regulation circuitry for the converter100that generates the four switch-control signals V1CTRL, V2CTRL, PCTRL, and NCTRL that control the four switches Vout1_SW, Vout2_SW, P_SW, and N_SW, respectively. As described further below, the regulation circuitry selects the output voltage Vout1or Vout2that is more deficient relative to its desired voltage level to be the currently selected output voltage. As a result, the regulation circuitry alternates between periods of charging the output voltage Vout1and periods of charging the output voltage Vout2.

In addition, the regulation circuitry repeatedly turns on and off the switches P_SW and N_SW in a complementary manner to charge the capacitor C1or C2corresponding to the currently selected output voltage Vout1or Vout2. The resulting current flowing intermittently from the input port DCDC_IN to the inductor L may be characterized as a charging signal for the currently selected output voltage Vout1or Vout2, the charging signal having a duty cycle corresponding to the timing of the turning on and off of the switches P_SW and N_SW, where a higher duty cycle corresponds to more charging of the inductor L from DCDC_IN. The charging signal is high during the charge phase of each charge-discharge cycle for the inductor L in which P_SW is on and N_SW is off, and low during the discharge phase of each charge-discharge cycle for the inductor L in which P_SW is off and N_SW is on.

The regulation circuitry also determines whether the DC-DC converter100is operating in CCM mode or DCM mode and controls the duty cycle of the charging signal differently for the two different modes. In particular, if the regulation circuitry determines that the DC-DC converter100is operating in CCM mode, then the regulation circuitry (i) regulates the duty cycle of the charging signal used to control the primarily regulated output voltage Vout1and (ii) similar to the technique described in the '447 patent, generates the initial duty cycle of the charging signal used to control the other output voltage Vout2by applying a scale factor (based on the relative desired output voltage levels for Vout1and Vout2) to the most-recent duty cycle of the charging signal for the primarily regulated output voltage Vout1.

In CCM mode, when controlling the primarily regulated output voltage Vout1, the regulation circuitry stores, in local memory, information identifying the current duty cycle of the Vout1charging signal. When the charging period switches to the other output voltage Vout2, the regulation circuitry retrieves the most-recent Vout1duty cycle from memory and scales that value to generate the initial duty cycle for the charging signal for the output voltage Vout2. When the charging period switches back to the output voltage Vout1, the regulation circuitry retrieves the most-recent Vout1duty cycle from memory and uses that value as the initial duty cycle for the charging signal for the output voltage Vout1. In this way, the regulation circuitry may be said to independently control the Vout1duty cycle, but dependently control the Vout2duty cycle based on the Vout1duty cycle. Note that the regulation circuitry also stores, in local memory, the current Vout2duty cycle, but only the stored Vout1duty cycle is used during CCM mode (i.e., directly for Vout1and scaled for Vout2).

In an alternative embodiment, instead of retrieving and using the previous Vout1duty cycle as the initial duty cycle for the current Vout1charging period during CCM operation, the regulation circuitry “de-scales” the most-recent Vout2duty cycle to generate the initial duty cycle for the current Vout1charging period. In this embodiment, for CCM mode, the regulation of Vout2would be dependent on the regulation of Vout1, and the regulation of Vout1would be dependent on the regulation of Vout2.

In another alternative embodiment, during CCM operation, the regulation circuitry generates the initial duty cycle for the current Vout1charging period by selecting the maximum of (i) the previous Vout1duty cycle and (ii) a “de-scaled” version of the most-recent Vout2duty cycle. Similarly, the regulation circuitry generates the initial duty cycle for the current Vout2charging period by selecting the maximum of (i) the previous Vout2duty cycle and (ii) a scaled version of the most-recent Vout1duty cycle. In this embodiment, for CCM mode, the regulation of Vout2would be dependent on the regulation of Vout1, and the regulation of Vout1would be dependent on the regulation of Vout2.

If the regulation circuitry determines that the DC-DC converter100is operating in DCM mode, then the regulation circuitry alternates between (i) charging periods of regulating the duty cycle of the charging signal used to control the output voltage Vout1and (ii) charging periods of regulating the duty cycle of the charging signal used to control the output voltage Vout2, where the regulation of each output voltage is independent of the regulation of the other output voltage. In doing so, the regulation circuitry saves both duty cycles in local memory so that, at the beginning of a charging period for one of the output voltages, the regulation circuitry retrieves the stored duty cycle from the previous charging period for that output voltage and uses that value as the initial duty cycle for the current charging period for that output voltage.

Note that, when the operation of the DC-DC converter100switches from CCM mode to DCM mode, the regulation circuitry retrieves and uses the stored Vout1duty cycle from the previous CCM charging period for Vout1as the initial duty cycle for the first DCM charging period for Vout1. Similarly, the regulation circuitry retrieves and uses the stored Vout2duty cycle from the previous CCM charging period for Vout2as the initial duty cycle for the first DCM charging period for Vout2.

In addition, the regulation circuitry detects both voltage overshoot and undershoot conditions. If the regulation circuitry detects an overshoot condition in which the currently selected output voltage is determined to be too high, then the regulation circuitry controls the switches P_SW and N_SW to lower that output voltage. In one possible implementation, in DCM mode, the regulation circuitry decreases the duty cycle of the charging signal to zero by maintaining the switch P_SW off and maintaining the switch N_SW on until the inductor current decreases to zero. The switch N_SW is then turned off, and the switches N_SW and P_SW are both maintained off to enable the capacitor C1or C2corresponding to the currently selected output voltage Vout1or Vout2to be discharged by the loading until the output overshoot condition no longer exists.

If the regulation circuitry detects an undershoot condition in which the currently selected output voltage is determined to be too low, then the regulation circuitry controls the switches P_SW and N_SW to raise that output voltage. In one possible implementation, the regulation circuitry increases the initial duty cycle of the charging signal by a specified amount so that the currently selected output voltage can be charged up more quickly with the higher initial duty cycle when undershoot occurs, so the output can recover from undershoot sooner.

To perform these various regulation functions, the regulation circuitry of the DC-DC converter100includes a resistor network102, a comparator104, a load-select module106, a regulation module108, a pulse-width modulation (PWM) module110, OR gates112and114, an AND gate116, a zero-cross detection (ZCD) module118, a pulse-detection module120, a comparator122, a switch module SW1, a switch-control module124, an overshoot detection module126, and an undershoot detection module128.

The resistor network102has two resistor dividers RD1and RD2, each with four resistors: R11-R14in RD1and R21-R24in RD2, where the output voltage Vout1is applied to the resistor divider RD1and the output voltage Vout2is applied to the resistor divider RD2. The resistance levels of the resistors R11-R14and R21-R24are selected to generate three different pairs of divided-down, sensed, feedback voltages: (1) Vout1_hi and Vout2_hi between R11and R12and between R21and R22, respectively, that are used by the undershoot detection module128as described further below; (2) Vout1_sns and Vout2_sns between R12and R13and between R22and R23, respectively, that are used as described further below; and (3) Vout1_lo and Vout2_lo between R13and R14and between R23and R24, respectively, that are used by the overshoot detection module126as described further below.

The divided-down, sensed, feedback voltages Vout1_sns and Vout2_sns are compared by the comparator104to generate the load-select control signal Load_Select. When Vout1_sns is greater than Vout2_sns, then Load_Select will be high; otherwise, Load_Select will be low. The resistance levels of the resistors R11-R14and R21-R24are selected based on the relative magnitudes of the target voltage levels for Vout1and Vout2such that the sensed feedback voltages Vout1_sns and Vout2_sns will be equal when Vout1and Vout2are both at their target voltage levels. For example, if the target voltage level for Vout1is 9 volts and the target voltage level for Vout2is 5 volts, then, in one possible implementation, the resistor network102is designed to divide Vout1by 9 and Vout2by 5, such that, when Vout1=9V and Vout2=5V, Vout1_sns and Vout2_sns will both equal 1V. As such, the load-select control signal Load_Select will indicate which of the two outputs Vout1and Vout2is more deficient relative to its target voltage level. In particular, when Vout2is more deficient than Vout1, Load_Select will be high, and, when Vout1is more deficient than Vout2, Load_Select will be low.

The load-select control signal Load_Select is applied to the load-select module106, which generates switch-control signals V1CTRL and V2CTRL. When Vout2is more deficient than Vout1and Load_Select is high, then the load-select module106will generate V1CTRL to be high and V2CTRL to be low to enable capacitor C2to be connected to and charged by the inductor L. On the other hand, when Vout1is more deficient than Vout2and Load_Select is low, then the load-select module106will generate V1CTRL to be low and V2CTRL to be high to enable capacitor C1to be connected to and charged by the inductor L.

The regulation module108generates a regulation signal109that controls the duty cycle of the charging signal used to charge the capacitor C1or C2for the currently selected output voltage Vout1or Vout2. The regulation signal109is applied to the PWM module110, which generates PWM pulse streams111aand111bhaving PWM pulses with duty cycles dictated by the regulation signal109. The pulse stream111ais applied to the OR gate112, which generates the switch-control signal PCTRL, while the pulse stream111bis applied to the OR gate114, whose output is applied to the AND gate116, which generates the switch-control signal NCTRL.

The PWM pulse streams111aand111bcontain similar PWM pulses where the pulse transitions are slightly offset from one another in time to avoid both switches P_SW and N_SW being on at the same time. In particular, the rising edges of the PWM pulses in the pulse stream111aslightly lead the rising edges of the PWM pulses in the pulse stream111bto ensure that switch P_SW is turned off before switch N_SW is turned on. Similarly, the falling edges of the PWM pulses in the pulse stream111bslightly lead the falling edges of the PWM pulses in the pulse stream111ato ensure that switch N_SW is turned off before switch P_SW is turned on.

As explained further below, during normal CCM operating conditions when there is no overshoot condition, the overshoot-detection control signal Overshoot_det_sig from the overshoot detection module126is low and the ZCD control signal zcd_b_latch from the ZCD module118is high. In that case, the switch-control signal NCTRL generated by the AND gate116is equal to the pulse stream111b, and the switch-control signal PCTRL generated by the OR gate112is equal to the pulse stream111a. As such, during those normal CCM operating conditions, the n-type switch N_SW is turned off and the p-type switch P_SW is turned on when the pulse streams111aand111bare both low, and N_SW is turned on and P_SW is turned off when the pulse streams111aand111bare both high. Thus, the duty cycle of the PWM pulses in the pulse streams111aand111bdetermine how long, within each charge-discharge cycle, the switch P_SW is on and off, which in turn determines how much the inductor L and the currently selected capacitor C1or C2are charged from the input node DCDC_IN.

Because the switch P_SW is a p-type transistor switch, lower duty cycle for the pulse stream111aimplies more charging of the inductor L and the currently selected capacitor, and vice versa. Thus, a decrease in the duty cycle of the pulse stream111acorresponds to an increase in the duty cycle of the charging signal applied to the inductor L and the capacitor for the currently selected output voltage, and vice versa.

The zero-cross detector (ZCD) module118and the pulse-detection module120determine whether the DC-DC converter100is operating in CCM mode or DCM mode. As described previously, when the current in the inductor L remains positive and never reaches zero, the DC-DC converter100is operating in CCM mode, while, in DCM mode, the inductor current does reach zero during the discharge phase of at least some of the charge-discharge cycles.

During each charging phase of the inductor L, the control signals PCTRL and NCTRL are both low, such that the switch P_SW is on and the switch N_SW is off. In that case, positive current will flow from the input port DCDC_in through P_SW to the node LP through the inductor L to the selected capacitor C1or C2through switch Vout1_SW or Vout2_SW. In that case, the voltage at the node LP will always be positive.

During each discharging phase of the inductor L, the control signals PCTRL and NCTRL are both high, such that the switch P_SW is off and the switch N_SW is on. In that case, the node LP will be connected to ground via N_SW. As long as the current through the inductor L remains positive (i.e., flowing from the node LP to the node LN inFIG. 1), the voltage at the node LP will be negative due to the voltage drop from ground across N_SW to the node LP. If and when the current through the inductor L goes negative (i.e., flowing from the node LN to the node LP inFIG. 1), the voltage at the node LP will be positive due to the voltage drop from the node LP across N_SW to ground.

The ZCD comparator ZCD_CMP compares the voltage at the node LP to the ground voltage GND. The output of the ZCD comparator ZCD_CMP is applied to the clock input port of the D-type, ZCD flip-flop DFF_zcd, whose D input port is pinned to a high signal TIE_HIGH and whose reset input port receives the ZCD reset signal reset_zcd from the inverter118A, which receives the switch-control signal NCTRL. The output signal zcd_latch, which appears at the Q output port of DFF_zcd, is applied as the set signal to the set-reset (SR) latch SR_LATCH and to the pulse-detection module120. The inverted value of the switch-control signal PCTRL from the inverter118B is applied as the latch reset signal reset_latch to SR_LATCH, which generates the output signal zcd_b_latch.

In operation, during each inductor charging phase in which PCTRL and NCTRL are both low, the voltage at the node LP will be positive, the output of the comparator ZCD_CMP will be high, and the reset signals reset_zcd and reset_latch will both be high. As such, the flip-flop DFF_zcd will be reset such that the Q output zcd_latch will be low, and the latch SR_LATCH will also be reset such that the latch output zcd_b_latch will be high.

During each inductor discharging phase in which PCTRL and NCTRL are both high, the reset signals reset_zcd and reset_latch will both be low, thereby releasing the flip-flop DFF_zcd and the latch SR_LATCH from their reset states. In that case, as long as the inductor current L remains positive, the voltage at the node LP will remain negative, the output of the comparator ZCD_CMP will remain low, zcd_latch will remain low, and zcd_b_latch will remain high. If and when the inductor current L goes negative, the voltage at the node LP will go positive, the output of the comparator ZCD_CMP will be driven high, which will trigger the flip-flop DFF_zcd to drive zcd_latch high, which will drive zcd_b_latch low.

Driving zcd_b_latch low will result in NCTRL going low, which will turn off the switch N_SW, thereby preventing the inductor current from being driven further negative. NCTRL going low will also drive reset_zcd high, which will reset the flip-flop DFF_zcd and drive zcd_latch low again. Note that zcd_b_latch will remain low until the latch SR_LATCH is reset (i.e., at the beginning of the next inductor current charging phase when PCTRL is again driven low).

The pulse-detection module120detects zcd_latch being driven high as a pulse and drives the DCM mode-detection control signal DCM_mode_det high, indicating that the DC-DC converter100is currently operating in DCM mode. Note that, in some implementations, after a pulse is detected, the pulse-detection module120is configured to maintain DCM_mode_det high for a specified number (e.g., 16) of regulating cycles to avoid undesirable chattering between DCM and CCM modes.

As shown inFIG. 1, the regulation module108generates the regulation signal109based on a one-bit binary feedback charge signal Feedback_Charge_Sig generated by the comparator122, which compares a sensed feedback voltage Feedback_sns to a reference voltage VREF (e.g., 1V for the previously described example of the resistor network102). If Feedback_sns is less than VREF, then Feedback_charge_sig will be high indicating that the charging duty cycle for the selected output voltage needs to be increased. Otherwise, Feedback_charge_sig will be low indicating that the charging duty cycle for the selected output voltage needs to be decreased.

The sensed feedback voltage Feedback_sns is generated based on the state of the switches SW11and SW12in the switch module SW1as controlled by the switch-control signal SW_CTRL, which is generated by the switch-control module124. When DCM_mode_det is low, indicating that the DC-DC converter100is currently operating in CCM mode, the switch-control module124sets SW_CTRL to a value that turns on (i.e., closes) both switches SW11and SW12in the switch module SW1, which causes the Feedback_sns to be based on the common-mode voltage between Vout1_sns and Vout2_sns. This operating mode is referred to as the “common regulated” mode. When DCM_mode_det is high, indicating that the DC-DC converter100is currently operating in DCM mode, then the switch-control module124sets SW_CTRL to the load-select control signal Load_Select such that only the switch SW11or SW12in the switch module SW1corresponding to the currently selected output voltage Vout1or Vout2is turned on, which causes the Feedback_sns to be based on only the corresponding voltage Vout1_sns or Vout2_sns, respectively. This operating mode is referred to as the “respectively regulated” mode.

Thus, when the DC-DC converter100is operating in CCM mode, the regulation module108is operated in the common regulated mode, and, when the DC-DC converter100is operating in DCM mode, the regulation module108is operated in the respectively regulated mode.

As shown inFIG. 1, the regulation module108has a CCM sub-module108A and a DCM sub-module108B. When the DC-DC converter100is operating in CCM mode (as indicated by DCM_mode_det being low), the CCM sub-module108A generates the initial duty cycle for the other output voltage Vout2by scaling the most-recent duty cycle for the primarily regulated output voltage Vout1by a fixed scale factor that is based on the relative target voltage levels of the two output voltages. However, when the DC-DC converter100is operating in DCM mode (as indicated by DCM_mode_det being high), the DCM sub-module108B alternately and independently regulates both output voltages Vout1and Vout2, where the two duty cycles are stored in local memory such that the initial value for the duty cycle at the beginning of the next charging period for each output voltage is the corresponding stored value of the duty cycle for that output voltage from its previous charging period.

For CCM mode, both duty cycles are stored even though only the duty cycle for the primarily regulated output voltage is subsequently used, where the duty cycle for the other output voltage is generated by scaling the duty cycle for the primarily regulated output voltage by the fixed scaling factor. But note that, when a transition occurs from CCM mode to DCM mode, the stored duty cycles for both output voltages from CCM mode are used as the initial duty cycles for DCM mode.

Referring again to the resistor network102, the low-voltage sensed voltages Vout1_lo and Vout2_lo generated by the resistor network102are respectively applied to the switches SW21and SW22of the switch module SW2of the overshoot detection module126. When the DC-DC converter100is operating in DCM mode such that DCM_mode_det is high, the regulation circuitry operates in the respectively regulated mode, and the switch-control signal SW_CTRL generated by the switch-control module124is equal to the load-select control signal Load_Select. In that case, when Load_Select is high indicating that Vout2is the currently selected output voltage, the switch SW21is open and the switch SW22is closed, such that Vout2_lo is applied as a sensed low feedback voltage FB_LO to the overshoot comparator126A. Similarly, when the DC-DC converter100is operated in DCM mode and Load_Select is low indicating that Vout1is the currently selected output voltage, the switch SW21is closed and the switch SW22is open, such that Vout1_lo is applied as FB_LO to the overshoot comparator126A.

On the other hand, when the DC-DC converter100is operated in CCM mode such that DCM_mode_det is low, the regulation circuitry operates in the common regulated mode, and the switch-control signal SW_CTRL generated by the switch-control module124causes both switches SW21and SW22in the switch module SW2to be closed independent of the value of Load_Select, such that the common-mode voltage between Vout1_lo and Vout2_lo is applied as FB_LO to the overshoot comparator126A.

In any case, the overshoot comparator126A compares the sensed low feedback voltage FB_LO to the reference voltage VREF to generate the overshoot detection signal Overshoot_det_sig. If FB_LO is greater than VREF, then Overshoot_det_sig will be high indicating that an overshoot condition exists. Otherwise, Overshoot_det_sig will be low indicating that an overshoot condition does not exist. An overshoot condition will exist when the currently selected output voltage is significantly above its target voltage level.

The overshoot detection signal Overshoot_det_sig is applied (i) to the OR gate112, which also receives the PWM pulse stream111a, and (ii) to the OR gate114, which also receives the PWM pulse stream111b. The output of the OR gate114is applied to the AND gate116, which also receives the ZCD output signal zcd_b_latch.

Under normal CCM operations in which an overshoot condition does not exist, zcd_b_latch from the ZCD module118is high and Overshoot_det_sig is low. In that case, the switch P_SW will be turned on and off based solely on the PWM pulse stream111a, and the switch N_SW will be turned on and off based solely on the PWM pulse stream111b.

If and when, however, during CCM operations, an overshoot condition is detected by the overshoot comparator126A, Overshoot_det_sig will be driven high. In that case, PCTRL will be driven to remain high, independent of the PWM pulse stream111a, and the switch P_SW will be driven to remain off, thereby stopping the charging of the inductor L from DCDC_IN. In addition, with Overshoot_det_sig and zcd_b_latch both high, NCTRL will be driven to remain high, independent of the PWM pulse stream111b. In that case, the switch N_SW will be driven to remain on, and the inductor L will discharge. As the inductor L discharges, at some point the voltage level of the currently selected output voltage Vout1or Vout2will fall such that the feedback voltage FB_LO will again fall below VREF, such that the overshoot detection signal Overshoot_det_sig will again be low. In that case, PCTRL and NCTRL will again be determined solely by the PWM pulse signals111aand111b, respectively.

If and when the current in the inductor L reaches zero indicating that the DC-DC converter100is now operating in DCM mode, the ZCD module118will drive zcd_b_latch low, which will drive NCTRL low, which will turn off the switch N_SW. Driving NTRL low also causes the ZCD flip-flop DFF_zcd to reset, which, in turn, resets SR_latch, which drives zcd_b_latch high again, such that NCTRL will again be determined solely by the PWM pulse signal111b. This enables the switch N_SW to be turned off if, in response to a detected overshoot condition, the inductor L is discharged to zero current. It also enables the switch N_SW to be turned off if the inductor L is discharged to zero current even when no overshoot condition is detected.

Referring again to the resistor network102, the high-voltage sensed voltages Vout1_hi and Vout2_hi are respectively applied to the switches SW31and SW32of the switch module SW3of the undershoot detection module128. Unlike the overshoot detection module126, the switch module SW3of the undershoot detection module128is always controlled based on Load_Select, independent of whether the DC-DC converter100is operating in CCM mode or DCM mode, to ensure that the undershoot detector128always senses the more-deficient output voltage. As such, when Load_Select is high, the switch SW31is open and the switch SW32is closed, such that Vout2_hi is applied as a sensed high feedback voltage FB_HI to the undershoot comparator128A. Similarly, when Load_Select is low, the switch SW31is closed and the switch SW32is open, such that Vout1_hi is applied as FB_HI to the undershoot comparator128A.

In any case, the undershoot comparator128A compares the sensed high feedback voltage FB_HI to the reference voltage VREF to generate an undershoot detection signal Undershoot_det_sig. If VREF is greater than FB_HI, then Undershoot_det_sig will be high indicating that an undershoot condition exists. Otherwise, Undershoot_det_sig will be low indicating that an undershoot condition does not exist. An undershoot condition will exist when the currently selected output voltage is significantly below its target voltage level.

The regulation module108receives the undershoot detection signal Undershoot_det_sig and, if an undershoot condition exists, at sub-module108C, the regulation module108adjusts the regulation signal109based on a specified feedforward value to decrease the duty cycles of the pulse signals111aand111bin order to increase the duty cycle of the charging signal for the currently selected output voltage and thereby accelerate the recovery from the undershoot condition. In some implementations, the regulation signal109is adjusted by adding the specified feedforward value. In other implementations, the regulation signal109is adjusted by multiplying by the specified feedforward value.

FIG. 2is a flow chart of the operations of the DC-DC converter100ofFIG. 1for charging either Vout1or Vout2, where Vout1is assumed to be the primarily regulated output voltage and Vout2is the other output voltage. In step202, at start-up of the DC-DC converter100, initial values for the duty cycles for the two output voltages Vout1and Vout2are set, for example, to pre-programmed values.

In step204, the comparator104determines whether Vout1or Vout2is to be charged based on which one is more deficient relative to its target voltage level.

In step206, the ZCD module118and the pulse-detection module120determine whether the DC-DC converter100is operating in CCM or DCM mode.

If the DC-DC converter100is operating in CCM mode, then, in step208, the undershoot detection module128determines whether or not an undershoot condition exists. If not, then processing proceeds to step212. If an undershoot condition exists, then, in step210, the regulation module108increases the duty cycle for the currently selected output voltage based on the specified feedforward value.

In step212, the regulation module108determines whether the currently selected output voltage is the primarily regulated, first output voltage Vout1. If Vout1is currently selected, then, in step214, the regulation signal109for Vout1, which is generated by the regulation module108based on the feedback charge signal Feedback_charge_sig and saved in local memory, is applied to the PWM module110without any scaling. If, however, Vout2is currently selected, then, in step216, the regulation module108generates the initial regulation signal109for Vout2by scaling the saved regulation signal for Vout1based on the specified fixed scaling factor. The regulation signal109for Vout2is also saved in local memory.

In either case, in step218, the overshoot detection module126determines whether an overshoot condition exists. If not, then processing returns to step206for the next charge-discharge cycle. If an overshoot condition exists, then, in step220, the OR gate112turns off the switch P_SW, and the AND gate116turns on the switch N_SW to discharge the inductor L until (i) the overshoot condition no longer exists or (ii) the current in the inductor L goes to zero. Processing then returns to step206for the next charge-discharge cycle.

If, in step206, the ZCD module118and the pulse-detection module120determine that the DC-DC converter100is operating in DCM mode, then, in step222, the undershoot detection module128determines whether or not an undershoot condition exists. If not, then processing proceeds to step224. If an undershoot condition exists, then processing proceeds to step230.

In step224(i.e., an undershoot condition does not exist), the regulation module108determines whether the currently selected output voltage is the primarily regulated, first output voltage Vout1. If Vout1is currently selected, then, in step226, the regulation module108retrieves the saved regulation signal from the previous charge-discharge cycle for Vout1and generates the current regulation signal for Vout1based on Feedback_charge_sig. If Vout2is currently selected, then, in step228, the regulation module108retrieves the saved regulation signal from the previous charge-discharge cycle for Vout2and generates the current regulation signal for Vout2based on Feedback_charge_sig. Processing then proceeds to step236.

In step230(i.e., an undershoot condition does exist), the regulation module108determines whether the currently selected output voltage is the primarily regulated, first output voltage Vout1. If Vout1is currently selected, then, in step232, the regulation module108retrieves the saved regulation signal from the previous charge-discharge cycle for Vout1and generates the current regulation signal for Vout1based on Feedback_charge_sig, including adjusting the regulation signal based on the feedforward value. If Vout2is currently selected, then, in step234, the regulation module108retrieves the saved regulation signal from the previous charge-discharge cycle for Vout2and generates the current regulation signal for Vout2based on Feedback_charge_sig, including adjusting the regulation signal based on the feedforward value. Processing then proceeds to step236.

In step236, the overshoot detection module126determines whether an overshoot condition exists. If so, then processing proceeds to step220as described previously. If an over shoot condition does not exist, then, in step238, the ZCD module118and the pulse-detection module120determine whether the DC-DC converter100is still operating in DCM mode. If so, then processing returns to step206for the next charge-discharge cycle. If not, then the DC-DC converter100has just transitioned to CCM mode and processing proceeds to step240.

In step240, the regulation module108generates the initial regulation signal for the currently selected output voltage Vout1or Vout2as the maximum value between (i) the saved regulation signal from the last charge-discharge cycle for Vout1and (ii) the saved regulation signal from the last charge-discharge cycle for Vout2. Processing then proceeds to step208as before. Because the duty cycle in DCM is smaller than the duty cycle in CCM, there can be a big voltage drop at the output ports when transitioning from DCM mode to CCM mode. Selecting the maximum duty cycle in step240helps to handle such transitions with less output ripple.

FIG. 3is a timing diagram of example operations of the DC-DC converter100ofFIG. 1during a transition from CCM mode to DCM mode for either output voltage Vout1or Vout2. With the DC-DC converter100operating in CCM mode starting at time t0with positive inductor current, DCM_mode_det is low, zcd_latch is low, and zcd_latch_b is high. During the inductor charging phase from time t0to time t1, PCTRL and NCTRL are both low, and the inductor current rises.

An inductor discharging phase starts at time t1with PCTRL and NCTRL both going high and the inductor current starting to fall. Note that the time offsets between the rising and falling edges in PCTRL and NCTRL are not represented inFIG. 3.

At time t2, the inductor current reaches zero, which causes zcd_batch to go high, zcd_batch_b to go low, DCM_mode_det to go high, NCTRL to go low, and PCTRL to remain high, in order to prevent the inductor current from going negative. At time t3, zcd_latch goes back low.

With DCM_mode_det remaining high, the inductor charging phase of the first full charging cycle in DCM mode begins at time t4with PCTRL going low, which causes zcd_latch_b to go high and the inductor current to rise. The inductor discharging phase begins at time t5with PCTRL and NCTRL both going high and the inductor current falling. At time t6, the inductor current again reaches zero, which causes zcd_batch to go high, zcd_batch_b to go low, NCTRL to go low, and PCTRL to remain high, in order to prevent the inductor current from going negative. At time t7, zcd_latch goes back low.

A similar inductor charging cycle in DCM mode is shown from time t8to time t12.

FIG. 4is a timing diagram of example operations of the DC-DC converter100ofFIG. 1during the occurrence of an overshoot condition for either output voltage Vout1or Vout2. With the DC-DC converter100operating in CCM mode starting at time t0with positive inductor current, DCM_mode_det is low, zcd_latch is low, and zcd_latch_b is high. During the inductor charging phase from time t0to time t1, PCTRL and NCTRL are both low, and the inductor current rises. An inductor discharging phase starts at time t1with PCTRL and NCTRL both going high and the inductor current starting to fall. Note that the time offsets between the rising and falling edges in PCTRL and NCTRL are represented inFIG. 4. Similar CCM charging cycles occur from time t2to time t4and from time t4to time t6.

During the next inductor charging phase, which starts at time t6, the DC-DC converter100detects an overshoot condition at the currently selected output voltage Vout1or Vout2at time t7. As such, Overshoot_det_sig goes high and PCTRL and NCTRL are also driven high, and the inductor current begins to fall.

At time t8, the inductor current reaches zero, which causes zcd_latch to be high, zcd_latch_b to be low, and DCM_mode_det to be high, which in turn causes PCTRL to remain high and NCTRL to go low to prevent the inductor current from going negative. At time t9, zcd_latch is driven low.

At time t10, the DC-DC converter100determines that the overshoot condition at the currently selected output voltage no longer exists, such that Overshoot_det_sig is driven low, which enables the next inductor charging phase to begin at time t10, with PCTRL going low and NCTRL remaining low, which causes zcd_latch_b to go high. Two DCM charging cycles are shown from time t10to time t12and from time t12to time t14. Note that the DCM duty cycle of the charging signal from time t10to time t14is larger than the CCM duty cycle of the charging signal from time t0to time t6, in order to prevent the inductor current from reaching zero.

FIG. 5is a timing diagram of example operations of the DC-DC converter100ofFIG. 1during the occurrence of an undershoot condition for either output voltage Vout1or Vout2. Two normal CCM charging cycles occur from time t0to time t2and from time t2to time t4.

During the next inductor charging phase, which starts at time t4, the DC-DC converter100detects an undershoot condition at the currently selected output voltage Vout1or Vout2at time t5. As such, Undershoot_det_sig goes high at time t5. As a result, for the next three charging cycles from time t8to time t10, from time t10to time t13, and from time t13to time t15, the duty cycle of the charging signal is increased compared to the duty cycle of the charging signal from time t0to time t8, in order to recover from the undershoot condition. Note that, at time t11, the DC-DC converter100detects that the overshoot condition no longer exists Undershoot_det_sig.

Although the regulation module108reacts to a detected undershoot condition by adjusting the regulation signal109based on the specified feedforward value, in other embodiments, the DC-DC converter may handle undershoot conditions in other ways. For example, the load current can be sensed and, if the load current increases faster than a specified threshold level, the regulation module can increase the duty cycle of the charging signal faster in order to attempt to prevent the undershoot condition from occurring.

Although the DC-DC converter100reacts to a detected overshoot condition by turning off the switch P_SW and intermittently turning on the switch N_SW, in other embodiments, the DC-DC converter may handle overshoot conditions in other ways. For example, the load current can be sensed and, if the load current decreases faster than a specified threshold level, the regulation module can decrease the duty cycle of the charging signal faster in order to attempt to prevent the overshoot condition from occurring. Another option is to switch from DCM mode to CCM mode upon detection of an overshoot condition to allow negative current to flow through the inductor L to discharge the output capacitor for the overshot output voltage.

Although the invention has been described in the context of the DC-DC converter100, which (i) has the undershoot detection module128, (ii) has the overshoot detection module126, (ii) stores duty cycles for subsequent use, and (iii) handles CCM and DCM modes differently, in other embodiments, DC-DC converters may be implemented without one or more of these features.

Although the invention has been described in terms of the switches Vout1_SW, Vout2_SW, and P_SW being p-type switches and the switch N_SW being an n-type switch, those skilled in the art will understand that one or more of the p-type switches may be n-type switches and/or the n-type switch may be a p-type switch with appropriate changes made to the circuitry that controls those switches.

Although the invention has been described in the context of the single-inductor, two-output, buck-type, DC-DC converter100ofFIG. 1, in general, the invention can be implemented in the context of single-inductor, multiple-output, DC-DC converters having two or more outputs and for full-bridge, half-bridge, buck, boost, buck/boost, or any other suitable type of DC-DC converters as well as AC-DC converters having an initial, AC-to-DC conversion stage and a subsequent, single-inductor, multiple-output, DC-DC conversion stage.