Secure integrated-circuit systems

A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

TECHNICAL FIELD

The present disclosure relates generally to structures and methods for secure hardware systems incorporating small monitor integrated circuits.

BACKGROUND

Electronic and photonic systems typically employ many different components supplied from a wide variety of sources in many different countries. Such diverse sources can be difficult to manage and secure to ensure that every component is constructed to specification by a manufacturer of the end system. For example, a hardware system can inadvertently incorporate malicious circuitry. Exhaustively testing every component at every stage of construction and integration can be difficult and prohibitively expensive. By interrupting the technology supply chain in some fashion, inimical actors can compromise the security and performance of electronic or photonic systems, for example by inserting undesirable and malicious circuitry into a system or by covertly redesigning components that are then employed in a compromised system. Such compromised systems can be accessed to retrieve information or to inhibit the performance of the compromised systems.

Monitor circuits for establishing appropriate operation are sometimes used to ensure that a circuit is operating as desired. Such monitor circuits typically provide a monitor signal when the circuit operation is no longer within specification. For example, power systems can include monitor circuits to ensure that the power supplied meets the desired specifications. Circuits for checking bit errors in communication systems are used to detect and correct such errors. However, such systems typically require relatively large monitor circuits that are not readily integrated into a small system.

There is a need, therefore, for systems, structures, devices, and methods that provide secure hardware systems where components of the hardware system are not under the complete control of the hardware system manufacturer.

SUMMARY

The present disclosure provides, inter alia, structures, materials, and methods that provide secure hardware systems, for example where components of the hardware system are not under the complete control of the hardware system manufacturer.

According to some embodiments, a method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit monitors the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit in a secure facility.

According to some embodiments, the first die has an area that is ten, twenty, fifty, one hundred, two hundred and fifty, five hundred, one thousand, five thousand, ten thousand times, one hundred thousand times, one million times, one hundred million times, one billion times, or larger than an area of the second die. According to some embodiments, the second die has a length and a width that are both less than or equal to 200 microns, 100 microns, 50 microns, 25 microns, or 10 microns.

The second die can comprise at least a portion of a fractured or separated tether.

According to some embodiments, connecting the second integrated circuit to the first integrated circuit comprises photolithographically forming wires electrically connecting the second integrated circuit to the first integrated circuit. According to some embodiments, the second die comprises one or more connection posts and the first integrated circuit is connected to the second integrated circuit through the one or more connection posts by the step of micro-transfer printing. According to some embodiments, connecting the second integrated circuit to the first integrated circuit comprises wire bonding the second integrated circuit to the first integrated circuit.

According to some embodiments, the connection is an electrical, optical, or electro-optic connection. According to some embodiments, the package comprises a cavity and the step of packaging the compound die comprises disposing the compound die in the cavity. According to some embodiments, the package comprises package leads and the step of packaging the compound die comprises connecting the package leads to the compound die. According to some embodiments, the step of packaging the compound die comprises wire bonding the first integrated circuit to one or more of the package leads. According to some embodiments, the step of packaging the compound die comprises wire bonding the second integrated circuit to one or more of the package leads.

Some embodiments comprise encapsulating the compound die and the compound die is encapsulated, for example with an organic or inorganic dielectric material, such as a resin, an oxide such as silicon dioxide, or a nitride such as silicon nitride.

Some methods comprise providing a plurality of first dies, providing a plurality of second dies, and micro-transfer printing each second die of the plurality of second dies onto a first die. Some methods comprise micro-transfer printing multiple second dies in a common step. Some methods comprise micro-transfer printing only one second die onto each first die. Some methods comprise micro-transfer printing multiple second dies onto each first die. Some methods comprise providing multiple source wafers each having a plurality of second dies and micro-transfer printing a second die from each second wafer onto a common first die. Some methods comprise connecting each second integrated circuit on a common first die together.

According to some embodiments, a secure integrated-circuit system comprises a first integrated circuit in a first die having a first die size and a second integrated circuit in a second die having a second die size smaller than the first die size. The second integrated circuit is operable to monitor the operation of the first integrated circuit and to provide a monitor signal responsive to the operation of the first integrated circuit. The second die is non-native to the first die and the second die can be micro-transfer printed from a source wafer to the first die. The first die can be provided in a destination wafer or destination substrate. The second integrated circuit is connected to the first integrated circuit, such that the first die and the second die together form a compound die. The compound die is disposed in a package.

According to some embodiments, the second die comprises a fractured or separated tether. Two or more second dies can be disposed on a common first die, the two or more second dies connected together to form a monitor circuit.

According to some embodiments, the first integrated circuit is constructed in an insecure facility. The first integrated circuit can incorporate a malicious circuit. The second integrated circuit can be constructed in a secure facility.

According to some embodiments, the first die has an area that is at least ten, (e.g., at least twenty, at least fifty, at least one hundred, at least two hundred and fifty, at least five hundred, at least one thousand, at least five thousand, at least ten thousand times, at least one hundred thousand times, at least one million times, at least one hundred million times, or at least one billion times larger than an area of the second die (e.g., and no more than one hundred thousand times larger, no more than one million times, no more than one hundred million times, no more than one billion times larger than the area of the second die). The second die can have a length and a width that are both no more than 200 microns (e.g., no more than 100 microns, no more than 50 microns, no more than 25 microns, or no more than 10 microns).

According to some embodiments, the second integrated circuit is connected to the first integrated circuit by one or more of an electrical connection, an optical connection, and an electro-optic connection. According to some embodiments, the second integrated circuit is electrically connected to the first integrated circuit with at least one wire bond, one surface wire, or one connection post.

In some embodiments, the components are computers, servers, or communications devices.

The perspectives shown inFIGS. 3A, 6A, and 7Aare exploded illustrations with exaggerated viewing angles and the two cross section lines A indicated in some of the perspective Figures are actually congruent.

Features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The figures are not necessarily drawn to scale.

DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS

Certain embodiments of the present disclosure are directed toward methods and structures for providing secure hardware systems when at least some component of the hardware system is constructed or provided in an insecure facility and can incorporate malicious circuitry.

The flow diagrams ofFIGS. 1 and 2and the sequential cross sections and perspectives ofFIGS. 3-8illustrate methods and structures of some embodiments. Referring specifically toFIG. 3, a method of making a secure integrated-circuit system according to some embodiments comprise providing a first integrated circuit21in or on a first die20having a first die size in step100. A plurality of first dies20each with first integrated circuits21can be provided in a destination wafer40. First integrated circuit21in or on first die20can be constructed in an insecure facility. In step110, a second integrated circuit23is provided in or on a second die22having a second die size smaller than the first die size. Second integrated circuit23can be a monitor circuit. Second integrated circuit23can be constructed in a secure facility (e.g., when first integrated circuit21is constructed in an insecure facility). First and second integrated circuits21,23can be made in first and second dies20,22, respectively, using photolithographic methods and materials. A plurality of second dies22each with second integrated circuits23can be provided in a source wafer10. In some embodiments, multiple source wafers10are provided each with different second dies22comprising different second integrated circuits23and multiple, different second dies22are disposed on a common first die20. In step120, a package90is provided. Optionally, a stamp30with stamp posts32each with a stamp post area on a distal end of each stamp post32is provided for use in micro-transfer printing, for example micro-transfer printing second dies22onto first dies20or into package90.

In step130, second die22is transfer printed (for example micro-transfer printed using stamp30) onto first die20and second integrated circuit23is connected to first integrated circuit21, to provide a compound die60. Optionally, second integrated circuit23can be connected to first integrated circuit21by the step130of transfer printing second die22onto first die20(as represented inFIG. 1with combined step135) or can be connected after transfer printing second die22onto first die20(as shown in step140ofFIG. 1), for example using photolithographic or wire bonding materials and methods (see, for example,FIGS. 9-11 and 13-15, discussed further below). Compound die60is then packaged, for example with a plastic or ceramic package90(e.g., as shown inFIG. 12, discussed below) as are commonly used in the integrated circuit industry. A package90is a container that contains compound die60and, in some embodiments, provides connections, for example with package leads94, to first and second integrated circuits21,23. As shown inFIG. 2, in some embodiments, second integrated circuit23can be connected to first integrated circuit21after packaging in step141(as shown inFIG. 2), rather than before packaging (as shown inFIG. 1).

In operation, second integrated circuit23monitors the behavior of first integrated circuit21and provides a monitor signal74(see, for example,FIG. 16, discussed further below) responsive to any combination of the behavior, performance, or operation of first integrated circuit21that is undesired. Monitor signal74can be electronic, optical, or can use other communication modalities and energy types. According to some embodiments, first integrated circuit21inadvertently incorporates undesired malicious circuitry when first integrated circuit21is constructed in an insecure facility. A malicious circuit can be an undesired circuit provided in first integrated circuit21that purposely performs functions or operates in a way that is deleterious or disruptive to the desired function of or interferes with a secure integrated-circuit system99(e.g., shown inFIG. 12) incorporating first integrated-circuit21.

The sequential cross sections and perspectives ofFIGS. 4A-9, illustrate in more detail a method of transfer printing (step130) second die22onto first die20, according to some embodiments of the present disclosure. Referring to the explodedFIG. 4Aperspective and corresponding cross sectionFIG. 4Btaken along cross section line A ofFIG. 4A, stamp posts32protrude from stamp30to contact second dies22when stamp30is pressed against second dies22, for example using an opto-mechatronic motion platform and control system. As shown inFIG. 4B, second dies22are entirely disposed over, and can be formed on, sacrificial portions14spatially separated by anchors50in sacrificial layer11of source wafer10. Sacrificial layer11can be a patterned sacrificial layer11or an anisotropically etchable layer of source wafer10. For example, second dies22can be, but are not necessarily, arranged in a rectangular array, for example in a regular two-dimensional array, as shown inFIG. 4A. A dielectric layer54disposed over source wafer10and sacrificial portions14connects each second die22with a tether52to an anchor50. In some embodiments, one or more tethers52connect a second die22to each of one or more anchors50. Tethers52can be laterally connected to anchors50(e.g., as shown) or disposed in other locations, for example beneath second dies22. In some embodiments, first dies20are also provided on a source wafer and transferred to a package90(e.g., before or after (i) second dies22are transferred to first dies20and/or (ii) first integrated circuits21are electrically connected to second integrated circuits23).

Referring toFIG. 5, sacrificial portions14(shown inFIG. 4B) are sacrificed, for example by etching sacrificial portions14to form gaps16, so that second dies22are suspended over gaps16and attached to anchors50of source wafer10by tethers52that maintain the physical position of second dies22with respect to source wafer10after sacrificial portions14are etched. Stamp30is moved into position with respect to source wafer10, for example by an opto-mechatronic motion platform, and second dies22are picked up from source wafer10by adhering second dies22to stamp30, for example by pressing stamp30against second dies22on source wafer10with the motion platform and adhering second dies22to the distal ends of stamp posts32, for example with van der Waals or electrostatic forces.

As shown in theFIG. 6Aperspective andFIG. 6Bcross section taken along cross section line A ofFIG. 6A, stamp30in contact with second dies22suspended over gaps16is then removed from source wafer10by the motion platform, separating or fracturing dielectric layer54tethers52from anchors50to form separated or fractured tethers53, respectively, and picking up second dies22from source wafer10with stamp30, providing picked-up second dies22on stamp posts32of stamp30. Picked-up second dies22can comprise a separated or fractured tether53.

Referring to the perspective ofFIG. 7Aand cross section ofFIG. 7Btaken along cross section line A ofFIG. 7A, stamp30and second dies22on stamp posts32of stamp30with fractured tethers53are moved into position and aligned with respect to destination wafer40.

Referring to the perspective ofFIG. 8Aand cross section ofFIG. 8Btaken along cross section line A ofFIG. 8A, picked-up second dies22on stamp30with fractured tethers53are micro-transfer printed to first dies20on or in destination wafer40with stamp30, and stamp30is removed. As shown inFIGS. 4A-8B, each of multiple stamp posts32of stamp30can pick up a second die22and transfer print it to a first die20of destination wafer40, so that multiple second dies22are transfer printed to corresponding multiple first dies20in each transfer print operation.

After second dies22are transfer printed onto first dies20(step130), second integrated circuits23formed in second dies22are each connected to a first integrated circuit21in first die20. A connection can be an electrical connection, for example with electrical conductors such as wires, an optical connection, for example with a light pipe such as a fiber optic or photonic waveguide, or an opto-electronic connection.

As shown inFIG. 9and in step140ofFIG. 1, each second die22can be connected to a first die20after second die22is transfer printed to first die20, for example with bond wires80connected to contact pads86using wire bonding equipment. In some embodiments, each second die22can be connected to a first die20after second die22is transfer printed to first die20by using photolithographic materials and methods to form surface wires82(e.g., traces) with or with or without contact pads86on the respective surfaces of first and second dies20,22, as shown inFIG. 10. Referring toFIG. 11, in some embodiments, connection posts84(e.g., spikes) connected to second integrated circuit23are formed in or on second dies22. Connection posts84can extend from dies22and can have a sharp point that pierces, penetrates, projects into, or otherwise electrically contacts contact pads86on first dies20to form an electrical connection70(shown inFIG. 13) between second integrated circuit23and first integrated circuit21when second die22is transfer printed onto first die20, for example by micro-transfer printing. In some such embodiments, the connection step140is the same step as the transfer print step130and is illustrated as combined step135inFIG. 1. Connection posts can require less space than, for example, contact pads for wire bonding or surface wires82(shown inFIG. 10), and therefore enable reduced size of second dies22, thereby reducing the cost and visibility of second dies22, as well as reducing the number of manufacturing steps required to combine and connect first and second integrated circuits21,23and construct compound die60.

Referring toFIG. 12, after second dies22are transfer printed onto first dies20forming compound die60, compound die60can be packaged (step150,FIGS. 1 and 2) to construct a secure integrated-circuit system99. Suitable ceramic and plastic integrated circuit packages (e.g., dual in-line packages or small-outline integrated circuit packages), are widely available in the integrated-circuit industry and typically comprise a package cavity92into which an integrated circuit is disposed and electrically connected with bond wires. According to some embodiments, compound die60is disposed in or on, and optionally adhered to, package90, for example in package cavity92, and electrically connected to package leads94, for example with package bond wires96and contact pads86, to provide connections from external devices to first and second integrated circuit21,23. In some embodiments, rather than connecting second integrated circuit23to first integrated circuits21before packaging (e.g., as in steps140,135inFIG. 1), second integrated circuits23are connected to first integrated circuits21after packaging (e.g., as in step141,FIG. 2), for example with bond wires80(not shown between first and second integrated circuits21,23inFIG. 12).

In some embodiments, second integrated circuit23is connected to package90in a variety of different ways (e.g., by connecting contact pads86on second die22to contact pads on package90, respectively). Such connections can directly enable connection to package leads94or connect to first integrated circuit21through an additional connection between package90, package leads94, and first die20. Referring toFIG. 13, connections between multiple second dies22disposed on a common first die20and the common first die20are made with connection posts84(e.g., as shown inFIG. 13) and surface wires82. Connections between first die20and package contact pads86are made with package bond wires96to package contact pads86.FIG. 14illustrates bond wires80directly connecting second dies22. InFIG. 15, (package) bond wires80,96directly connect a second die22to a contact pad86on package90. Referring toFIGS. 13-15, although not shown, in some embodiments, package contact pads86are connected to package leads94(FIG. 12), providing an external connection to compound die60.

In some embodiments, and as illustrated inFIG. 16, first and second integrated circuits21,23are directly connected (e.g., as shown inFIGS. 9-11) with electrical connections70, for example transmitting signals through bond wires80(shown inFIG. 9), surface wires82(shown inFIG. 10), or connection posts84(shown inFIG. 11). First integrated circuit21can be connected to external devices or systems through input/output signals72(as can second integrated circuit23, although not shown inFIG. 16), for example through package bond wires96and package leads94. Second integrated circuit23can output monitor signal74, either directly through package bond wires96and package leads94or indirectly through first die20or first integrated circuit21.

In some embodiments, post processing (e.g., photolithographic processing) of first die20or compound die60is reduced by using transfer printing to construct compound die60. Contact pads86on first die20can be left exposed, for example to enable wire bonding or to enable transfer printing to contact pads86(e.g., as shownFIG. 11). After compound die60is formed and first and second integrated circuits21,23are connected, it may only be necessary to provide an encapsulating layer to complete compound die60. By minimizing post processing, additional processing expenses after first integrated circuit21is completed can be reduced or obviated. By integrating first and second dies20,22into a single compound die60, only a single package90is needed which may further reduce size, manufacturing steps, and cost.

In operation, power is provided to first and second integrated circuit21,23, for example through package leads94. Second integrated circuit23can receive power through first integrated circuit21or directly through package bond wires96and package leads94(e.g., as shown inFIG. 15). Once powered, first integrated circuit21operates and second integrated circuit23observes and monitors the operation of first integrated circuit21. If an anomaly is detected, second integrated circuit23provides a monitor signal74(e.g., as shown inFIG. 16) that indicates anomalous operation. Monitor signal74can be provided on a dedicated and direct connection, e.g., through a direct connection between second integrated circuit23and a package lead94(e.g., as shown inFIG. 15). Monitor signal74can be provided through first integrated circuit21and a dedicated connection (e.g., as shown inFIGS. 13 and 14), or indirectly through one or more connections and package leads94that are used for other signals, as well.

In some embodiments, second die22is much smaller than first die20. Such small dies can be transfer printed onto a surface of a semiconductor wafer or circuit and can be so small that they are difficult to observe, providing additional security to a compound die60. For example, in some embodiments, first die20has an area that is at least ten (e.g., at least twenty, at least fifty, at least one hundred, at least two hundred and fifty, at least five hundred, at least one thousand, at least five thousand, at least ten thousand, at least one hundred thousand, at least one million, at least one hundred million, or at least one billion times) larger than an area of second die22. In some embodiments, second die22has an area that is at least ten (e.g., at least twenty, at least fifty, at least one hundred, at least two hundred and fifty, at least five hundred, at least one thousand, at least five thousand, at least ten thousand, at least one hundred thousand, at least one million, at least one hundred million, or at least one billion times) smaller than an area of first die22. In some embodiments, second die22can have a length and a width that are both less than or equal to 200 microns, 100 microns, 50 microns, 25 microns, or 10 microns. For example, first die20can have a length and width of ten centimeters (with an area of one hundred million square microns) and second die22can have a length and width of 100 microns (with an area of ten thousand square microns) and an area ratio of ten thousand.

As discussed above, some methods comprise providing a plurality of first dies20, for example on a first destination wafer40(step100), providing a plurality of second dies22(step110), for example in a source wafer10, and transfer printing only one second die22of the plurality of second dies22onto each first die20of the plurality of first dies20(step130). Some embodiments comprise transfer printing multiple second dies22from a source wafer10to multiple first dies20in a common step, with one second die22transfer printed to each first die20. In some embodiments and as shown inFIG. 12, compound die60comprises two or more second dies22and second integrated circuits23. Multiple second dies22can be micro-transfer printed to a common first die20, for example from different source wafers10, with multiple repetitions of transfer printing step130. The multiple second integrated circuits23can be connected to provide a larger and more complex monitor circuit. Thus, some embodiments comprise providing multiple source wafers10each having a plurality of second dies22and transfer printing a second die22from each source wafer10onto a common first die20, so that each first die20has two or more second dies22disposed thereon. Each second integrated circuit23on a common first die20can be connected together to form a single monitor circuit.

According to some embodiments, a secure integrated-circuit system99comprises a first integrated circuit21in a first die20having a first die size. The first integrated circuit can be constructed in an insecure facility. A second integrated circuit23in a second die22has a second die size smaller than the first die size. The second integrated circuit can be constructed in a secure facility. The second integrated circuit23is operable to monitor the operation of the first integrated circuit21and provides a monitor signal74responsive to the operation of the first integrated circuit21. The second die22is transfer printed onto the first die20and the second integrated circuit23is connected to the first integrated circuit21to provide a compound die60. The compound die60is disposed in a package90. In some embodiments, the second die22comprises a fractured or separated tether.

In some embodiments, secure integrated-circuit system99comprise two or more second dies22on a common first die20. The two or more second dies22are connected together to form a monitor circuit.

Transfer printing, for example micro-transfer printing, can include transferring second dies22from a source substrate (e.g., source wafer10) to first dies20of a destination substrate (e.g., destination wafer40). Methods of micro-transfer printing can comprise contacting second dies22on source wafer10with a stamp30to remove second dies22from source wafer10, transferring stamp30and contacted second dies22to first dies20of destination wafer40, and contacting second dies22to a surface of first dies20of destination wafer40. Second dies22can be adhered to stamp30or first dies20of destination wafer40by, for example, van der Waals forces, electrostatic forces, magnetic forces, chemical forces, or adhesives. In some embodiments of the present disclosure, second dies22are adhered to stamp30with separation-rate-dependent adhesion, for example kinetic control of viscoelastic stamp materials such as can be found in elastomeric transfer devices such as a PDMS stamp30. Stamps30can comprise stamp posts32having a stamp post area on the distal end of stamp posts32. Stamp posts32can have a length, width, or both length and width, similar or substantially equal to the length, width, or both length and width of second die22. In some embodiments, stamp posts32are smaller than second dies22in one or two orthogonal directions.

In exemplary methods, a viscoelastic elastomer (e.g., PDMS) stamp30(e.g., comprising a plurality of stamp posts32) is designed and fabricated to retrieve and transfer arrays of second dies22from their native source wafer10onto non-native destination wafers40or other non-native destination substrates. Stamp30mounts onto motion-plus-optics machinery (e.g., an opto-mechatronic motion platform) that can precisely control stamp30alignment and kinetics with respect to both source wafers10and destination wafers40. During micro-transfer printing, an opto-mechatronic motion platform brings stamp30into contact with second dies22on source wafer10, with optical alignment performed before contact. Rapid upward movement of the print-head and stamp30fractures second die22tether(s)52forming fractured tethers53, transferring second die(s)22from source wafer10to stamp30or stamp posts32. The populated stamp30then travels to destination wafer40and one or more second dies22are then aligned to destination wafer40and printed on a surface of first die20of destination wafer40.

In some embodiments, a source wafer10has releasable (e.g., micro-transfer-printable) second dies22that can be transferred, for example with a stamp30. For example, a source wafer10can be a semiconductor (e.g., silicon in a crystalline or non-crystalline form or crystalline silicon having a crystal structure of (1 0 0) or (1 1 1)), a compound semiconductor (e.g., comprising GaN or GaAs), or a glass, polymer, sapphire, or quartz wafer. Sacrificial portions14can be formed of a patterned oxide (e.g., silicon dioxide) or nitride (e.g., silicon nitride) layer or can be an anisotropically etchable portion of sacrificial layer11of source wafer10. Typically, but not necessarily, source wafers10are smaller than destination wafers40.

Second dies22can be any transfer printable structure, for example including a wide variety of active or passive (or active and passive) second dies22and can be or include any one or more of integrated devices, integrated circuits (such as CMOS circuits), computers, communication equipment, light-emitting diodes, photodiodes, sensors, electrical or electronic devices, optical devices, opto-electronic devices, magnetic devices, magneto-optic devices, magneto-electronic devices, and piezo-electric device, materials or structures. Second dies22can comprise electronic circuits that operate second die22. Second dies22can be responsive to electrical energy, to optical energy, to electromagnetic energy, or to mechanical energy. For example, in some embodiments, second die22includes a light-emitting diode (LED), for example to provide a monitor signal74.

In some embodiments, second dies22formed or disposed in or on source wafers10can be constructed using one or more of integrated circuit, micro-electro-mechanical, and photolithographic methods. Second dies22can comprise one or more different materials, for example non-crystalline or crystalline semiconductor materials such as silicon or compound semiconductor materials or non-crystalline or crystalline piezo-electric materials.

In some embodiments of the present disclosure, second dies22are native to and formed on sacrificial portions14of source wafers10and can include seed layers for constructing crystalline layers on or in source wafers10. Second dies22, sacrificial portions14, anchors50, and tethers52can be constructed using photolithographic processes, for example. Second dies22can be micro-devices having a length and/or width less than or equal to 200 microns, less than or equal to 100 microns, less than or equal to 50 microns, less than or equal to 25 microns, less than or equal to 15 microns, less than or equal to 10 microns, or less than or equal to five microns, and, optionally, a thickness of less than or equal to 50 microns, less than or equal to 25 microns, less than or equal to 15 microns, less than or equal to 10 microns, less than or equal to five microns, less than or equal to two microns, or less than or equal to one micron. Second dies22can be unpackaged dies (also referred to in the plural as dice, each an unpackaged die) transferred directly from native source wafers10on or in which second dies22are constructed to first dies20of destination wafer40. First dies20can be native to and formed on or in destination wafers40. Thus, second dies22can be non-native to destination wafers40. First dies20can be, but are not necessarily, transfer printable, having similar materials or structures as second dies22(e.g., including fractured or separated tethers after transfer).

Anchors50and tethers52can each be or can each comprise portions of source wafer10that are not sacrificial portions14and can include layers formed on source wafers10, for example dielectric or metal layers and for example layers formed as a part of photolithographic processes used to construct or encapsulate second dies22.

Destination wafer40can be any destination substrate or target substrate, for example having first dies20disposed thereon to which second dies22are transfer printed. For example, destination wafer40can be a semiconductor wafer, flat-panel display substrate, printed circuit board, or similar substrate. Destination wafers40can be, for example substrates comprising glass, polymer, quartz, ceramics, metal, or sapphire. Destination wafers40can be semiconductor substrates (for example silicon) or compound semiconductor substrates and can have multiple layers.

In some embodiments of the present disclosure, a layer of adhesive, such as a layer of resin, polymer, or epoxy, either curable or non-curable, adheres second dies22onto first dies20on destination wafer40and can be disposed, for example by coating or lamination. In some embodiments, the layer of adhesive is disposed in a pattern, for example using inkjet, screening, or photolithographic techniques. In some embodiments, a layer of adhesive is coated, for example with a spray or slot coater, and then patterned, for example using photolithographic techniques.

Patterned electrical conductors (e.g., wires, surface wires82, bond wires80, traces, or electrical contact pads86, such as those found on semiconductor wafers, printed circuit boards, flat-panel display substrates, and in thin-film circuits) can be formed on any combination of second dies22, first dies20, and destination wafer40, and any one can comprise electrical contact pads that electrically connect to second dies22. Such patterned electrical conductors (e.g., wires, surface wires82, bond wires80) and contact pads86can comprise, for example, metal, transparent conductive oxides, or cured conductive inks and can be constructed using photolithographic methods and materials. For example, metals such as aluminum, gold, or silver can be deposited by evaporation and patterned using pattern-wise exposed, cured, and etched photoresists, or constructed using imprinting methods and materials or inkjet printers and materials, for example comprising cured conductive inks deposited on a surface or provided in micro-channels in or on first dies20or destination wafer40.

Micro-transfer printing processes and structures suitable for disposing second dies22onto first dies20of destination wafers40are described inInorganic light-emitting diode displays using micro-transfer printing(Journal of the Society for Information Display, 2017, DOI #10.1002/jsid.610, 1071-0922/17/2510-0610, pages 589-609), U.S. Pat. No. 8,722,458 entitled Optical Systems Fabricated by Printing-Based Assembly, U.S. patent application Ser. No. 15/461,703 entitled Pressure Activated Electrical Interconnection by Micro-Transfer Printing, U.S. Pat. No. 8,889,485 entitled Methods for Surface Attachment of Flipped Active Components, U.S. patent application Ser. No. 14/822,864 entitled Chiplets with Connection Posts, U.S. patent application Ser. No. 14/743,788 entitled Micro-Assembled LED Displays and Lighting Elements, and U.S. Pat. No. 10,153,256, entitled Micro-Transfer Printable Electronic Component, the disclosure of each of which is incorporated herein by reference in its entirety.

For a discussion of micro-transfer printing techniques, see also U.S. Pat. Nos. 7,622,367 and 8,506,867, each of which is hereby incorporated by reference in its entirety. Micro-transfer printing using compound micro-assembly structures and methods can also be used with the present disclosure, for example, as described in U.S. patent application Ser. No. 14/822,868, filed Aug. 10, 2015, entitled Compound Micro-Assembly Strategies and Devices, which is hereby also incorporated by reference in its entirety. In some embodiments, micro-transfer printed structure99is a compound micro-assembled structure (e.g., a macro-system).

According to various embodiments of the present disclosure, source wafer10can be provided with second dies22, patterned sacrificial portions14, tethers52, and anchors50already formed, or they can be constructed as part of a method in accordance with certain embodiments of the present disclosure. Source wafer10and second dies22, micro-transfer printing device (e.g., a stamp30), and first dies20of destination wafer40can be made separately and at different times or in different temporal orders or locations and provided in various process states.

The spatial distribution of any one or more of second dies22and first dies20is a matter of design choice for the end product desired. In some embodiments of the present disclosure, all second dies22in an array on a source wafer10are transferred to a stamp30in a single transfer. In some embodiments, a subset of second dies22in an array on a source wafer10is transferred in a single transfer. By varying the number and arrangement of stamp posts32on transfer stamps30, the distribution of second dies22on stamp posts32of the transfer stamp30can be likewise varied, as can the distribution of second dies22on first dies20of destination wafer40.

Because second dies22, in certain embodiments, can be made using integrated circuit photolithographic techniques having a relatively high resolution and cost and destination wafer40, for example a printed circuit board, can be made using printed circuit board techniques having a relatively low resolution and cost, electrical conductors and contact pads86on destination wafer40may be much larger than electrical contacts or electrodes on second die22(or first dies20), thereby reducing manufacturing costs. For example, in certain embodiments, micro-transfer printable second die22has at least one of a width, length, and height from 0.5 μm to 200 μm (e.g., 0.5 to 2 μm, 2 to 5 μm, 5 to 10 μm, 10 to 20 μm, 20 to 50 μm, or 50 to 100 μm, or 100 to 200 μm).

First dies20and second dies22, in certain embodiments, can be constructed using foundry fabrication processes used in the art. Layers of materials can be used, including materials such as metals, oxides, nitrides and other materials used in the integrated-circuit art. Each first die20or second die22can be or include a complete semiconductor integrated circuit and can include, for example, one or more of a transistor, a diode, a light-emitting diode, and a sensor. Second dies22can have different sizes, for example, 100 square microns or larger, 1000 square microns, larger or 10,000 square microns or larger, 100,000 square microns or larger, or 1 square mm or larger. Second dies22can have variable aspect ratios, for example between 1:1 and 10:1 (e.g., 1:1, 2:1, 5:1, or 10:1). Second dies22can be rectangular or can have other shapes. Likewise, first dies20can be rectangular and have a size greater than a size of second dies22, for example having a size greater than 100,000 square microns, 1,000,000 square microns, 100,000,000 square microns, or 1,000,000,000 square microns.

In some embodiments, transferring or transfer printing occurs by micro-transfer-printing. In some embodiments, micro-transfer printing involves using a transfer device (e.g., an elastomeric stamp30, such as a PDMS stamp30) to transfer a second die22using controlled adhesion. For example, an exemplary transfer device can use kinetic or shear-assisted control of adhesion between a transfer device and a second die22. It is contemplated that, in certain embodiments, where a method is described as including micro-transfer-printing a second die22, other analogous embodiments exist using a different transfer method. In some examples, transferring a second die22(e.g., from a source wafer10or wafer to a first die20of destination wafer40) can be accomplished using any one or more of a variety of known techniques. For example, in certain embodiments, a pick-and-place method can be used. As another example, in certain embodiments, a flip-chip method can be used (e.g., involving an intermediate, handle or carrier substrate). In methods according to certain embodiments, a vacuum tool or other transfer device is used to transfer a second die22.

As is understood by those skilled in the art, the terms “over” and “under” are relative terms and can be interchanged in reference to different orientations of the layers, elements, and substrates included in the present disclosure. Furthermore, a first layer “on” a second layer is a relative orientation of the first layer to the second layer that does not preclude additional layers being disposed therebetween. For example, a first layer on a second layer, in some implementations, means a first layer directly on and in contact with a second layer. In other implementations, a first layer on a second layer includes a first layer and a second layer with another layer therebetween (e.g., and in mutual contact).

Throughout the description, where apparatus and systems are described as having, including, or comprising specific elements, or where processes and methods are described as having, including, or comprising specific steps, it is contemplated that, additionally, there are apparatus and systems of the disclosed technology that consist essentially of, or consist of, the recited elements, and that there are processes and methods according to the disclosed technology that consist essentially of, or consist of, the recited processing steps.

It should be understood that the order of steps or order for performing certain action is immaterial so long as the disclosed technology remains operable. Moreover, two or more steps or actions in some circumstances can be conducted simultaneously.

Having described certain implementations of embodiments, it will now become apparent to one of skill in the art that other implementations incorporating the concepts of the disclosure may be used. Therefore, the disclosure should not be limited to certain implementations, but rather should be limited only by the spirit and scope of the following claims.

PARTS LIST

A cross section line10source wafer11sacrificial layer14sacrificial portions16gap20first die21first integrated circuit22second die23second integrated circuit30stamp32stamp post40destination wafer50anchor52tether53fractured tether54dielectric layer60compound die70electrical connection72input/output signals74monitor signal80bond wires82surface wires84connection posts86contact pad90package92package cavity94package leads96package bond wires99secure integrated-circuit system100provide first die step110provide second die step120provide package step130transfer print second die onto first die step135transfer print and connect second integrated circuit to first integrated circuit step140connect first integrated circuit to second integrated circuit step141connect first integrated circuit to second integrated circuit step150package compound die step