Display device and method of driving the same

A display device and a method of driving the same are provided. The display device includes a scan driver that generates a plurality of scanning signals, a data driver that generates a data voltage, and a plurality of pixels that receive the data voltage according to the scanning signal and that display luminance corresponding to the data voltage. Each pixel receives its own data voltage and a data voltage of other pixels while displaying a black color when its own scanning signal is in a first state, and stops reception of the data voltage and displays luminance corresponding to its own data voltage when its own scanning signal is in a second state.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2008-0034287, filed on Apr. 14, 2008, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display device and a method of driving the same. More particularly, the present invention relates to an organic light emitting device and a method of driving the same.

2. Discussion of the Background

A hole-type flat panel display such as an organic light emitting device displays a fixed picture for a predetermined time period, (e.g., a frame), regardless of whether it is a still or motion picture. As an example, when a continuously moving object is displayed, the object moves from a particular position after being at the position for a certain time period of a frame, and is maintained at a new position of a frame for a certain time period before moving again, i.e., movement of the object is discretely displayed. Because the time period of a frame is a time period in which an afterimage is sustained, even if a picture is displayed in this way, movement of an object is continuously perceived.

However, when a continuously moving object is viewed on a screen, because a viewer's eye moves along with the object's movement, which conflicts with a discrete display of the display device, the viewer may see blur on a screen. For example, assume that the display device displays an object that stays at a position A in a first frame and at a position B in a second frame. In the first frame, the viewer's eye moves along an estimated movement path of the object from position A to position B. However, the object is not actually displayed at an intermediate position between position A and position B.

Therefore, because luminance that is recognized by a person for the first frame is a value, i.e., an average value of luminance of the object and luminance of a background that is obtained by integrating luminance of pixels at a path between position A and position B, an object is perceived to be blurred.

In the hole-type display device, because a degree to which the object is perceived to be blurred is proportional to a time period in which the display device sustains the display of the object, a so-called impulse driving method of displaying an image for only some time period and displaying a black color for the remaining time period within a frame has been suggested. In this method, because the time period in which an image is displayed decreases, luminance decreases, so a method of increasing luminance for a display time period or a method of displaying intermediate luminance using adjacent frames instead of a black color has been suggested. However, this method may increase power consumption and complicate driving.

Because a pixel of the organic light emitting device has an organic light emitting element and a thin film transistor (TFT) that drives the organic light emitting element, when the organic light emitting element and the TFT operate for a long time period, estimated luminance may not be displayed due to a change of the TFT's threshold voltage, and when characteristics of a semiconductor that is included in TFTs are not uniform within the display device, a luminance deviation between pixels may occur.

SUMMARY OF THE INVENTION

The present invention provides a display device and method of driving a display device.

The present invention discloses a display device including a scan driver that generates a plurality of scanning signals, a data driver that generates a data voltage, and a plurality of pixels that receive the data voltage according to the scanning signal and that display luminance corresponding to the data voltage. Each pixel receives its own data voltage and a data voltage of another pixel while displaying a black color when its own scanning signal is in a first state, and stops reception of the data voltage and displays luminance corresponding to its own data voltage when its own scanning signal is in a second state.

The present invention also discloses a display device including a scan driver that generates a plurality of scanning signals and a plurality of compensation signals, a data driver that generates a data voltage, and a plurality of pixels that receive the data voltage according to the scanning signals and that display luminance corresponding to the data voltage. Each pixel may include a light emitting element that emits light with an intensity according to a magnitude of a driving current; a capacitor that is connected between a first contact point and a second contact point; a driving transistor that has an input terminal connected to a first voltage and a control terminal connected to the second contact point, and that outputs the driving current; a first switching unit that connects the data voltage to the first contact point while the scanning signal is in a first state and that connects a second voltage to the first contact point while the scanning signal is in a second state; a second switching unit that switches connection between the second voltage and the second contact point according to the compensation signal; and a third switching unit that connects the second contact point to an output terminal of the driving transistor while the scanning signal is in the first state and that connects the light emitting element to the output terminal of the driving transistor while the scanning signal is in the second state. The data driver may change the data voltage in each one horizontal period, and the scanning signal may sustain the first state for a time period that is longer than one horizontal period.

The present invention also discloses a method of driving a display device, including outputting a data voltage that changes in each horizontal period, applying the data voltage to a pixel while stopping light emission of the pixel by applying a first scanning signal to the pixel for a time period that is longer than the one horizontal period, and allowing the pixel to emit light with luminance corresponding to the data voltage while stopping application of the data voltage to the pixel by applying a second scanning signal to the pixel, the first scanning signal and the second scanning signal having different levels from each other.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

First, an organic light emitting device according to an exemplary embodiment of the present invention will be described with reference toFIG. 1andFIG. 2.

FIG. 1is a block diagram of an organic light emitting device according to an exemplary embodiment of the present invention, andFIG. 2is an equivalent circuit diagram of a pixel in an organic light emitting device according to an exemplary embodiment of the present invention.

Referring toFIG. 1, the organic light emitting device includes a display panel300, a scan driver400, a data driver500, and a signal controller600.

The display panel300includes a plurality of signal lines (G1-Gn, S1-Sn, and D1-Dm), a plurality of voltage lines (not shown), and a plurality of pixels PX that are connected thereto and that are arranged in approximately a matrix form.

The signal lines (G1-Gn, S1-Sn, and D1-Dm) include a plurality of scanning signal lines (G1-Gn) that transmit a scanning signal, a plurality of compensation signal lines (S1-Sn) that transmit a compensation signal, and a plurality of data lines (D1-Dm) that transmit a data signal. The scanning signal lines (G1-Gn) and the compensation signal lines (S1-Sn) extend in approximately a row direction and are substantially parallel to each other, and the data lines (D1-Dm) extend in approximately a column direction and are substantially parallel to each other.

The voltage line includes a driving voltage line (not shown) that transmits a driving voltage.

As shown inFIG. 2, each pixel PX includes an organic light emitting element LD, a driving transistor Qd, a capacitor Cst, and five switching transistors Qs1, Qs2, Qs3, Qs4, and Qs5.

The driving transistor Qd has an output terminal, an input terminal, and a control terminal. The control terminal of the driving transistor Qd is connected to the capacitor Cst at a contact point N2, its input terminal is connected to a driving voltage Vdd, and its output terminal is connected to the switching transistor Qs5.

A first electrode of the capacitor Cst is connected to the driving transistor Qd at the contact point N2, and a second electrode of the capacitor Cst is connected to the switching transistors Qs1and Qs2at a contact point N1.

The switching transistors Qs1-Qs5may be formed in three switching units SU1, SU2, and SU3.

The switching unit SU1, which includes switching transistors Qs1and Qs2, selects one of a data voltage Vdat and a sustain voltage Vsus in response to a scanning signal gi(i=1, 2, . . . , N) and connects the selected voltage to the contact point N1. The switching transistor Qs1is connected between the contact point N1and the data voltage Vdat, and the switching transistor Qs2is connected between the contact point N1and the sustain voltage Vsus.

The switching unit SU2, which includes switching transistor Qs3, switches connection between the sustain voltage Vsus and the contact point N2in response to a compensation signal si. Switching transistor Qs3is connected between the sustain voltage Vsus and the contact point N2.

The switching unit SU3, which includes switching transistors Qs4and Qs5, selects one of the contact point N2and the light emitting element LD in response to the scanning signal giand connects the selected one to the output terminal of the driving transistor Qd. The switching transistor Qs4is connected between the output terminal of the driving transistor Qd and the contact point N2, and the switching transistor Qs5is connected between the output terminal of the driving transistor Qd and the organic light emitting element LD.

The switching transistors Qs1, Qs3, and Qs4are n-channel field effect transistors, and the switching transistors Qs2and Qs5and the driving transistor Qd are p-channel field effect transistors. The field effect transistors may be thin film transistors (TFTs), for example, and they may include polysilicon or amorphous silicon. Channel types of the switching transistors Qs1-Q5and the driving transistor Qd may change, and in this case, a driving signal waveform for driving the transistors may be inverted.

An anode and a cathode of the organic light emitting element LD are connected to the switching transistor Qs5and the common voltage Vss, respectively. The organic light emitting element LD emits light with different intensities according to a magnitude of a current ILDthat is supplied by the driving transistor Qd through the switching transistor Qs5, thereby displaying an image. A magnitude of the current ILDdepends on a magnitude of a voltage between the control terminal and the input terminal of the driving transistor Qd.

Referring again toFIG. 1, the scan driver400is connected to the scanning signal lines (G1-Gn) and the compensation signal lines (S1-Sn) of the display panel300, and it applies a scanning signal and a compensation signal, which both include a combination of a high voltage Von and a low voltage Voff, to the scanning signal lines (G1-Gn) and the compensation signal lines (S1-Sn), respectively.

The high voltage Von may allow the switching transistors Qs1, Qs3, and Qs4to electrically connect and intercept the switching transistors Qs2and Qs5, and the low voltage Voff may intercept the switching transistors Qs1, Qs3, and Qs4and allow the switching transistors Qs2and Qs5to electrically connect. A sustain voltage Vsus is a low voltage, and it may intercept the switching transistors Qs1, Qs3, and Qs4and allow the switching transistors Qs2and Qs5to electrically connect, like the low voltage Voff. The sustain voltage Vsus and the driving voltage Vdd may be applied through a driving voltage line.

The data driver500is connected to the data lines (D1-Dm) of the display panel300, and it applies a data voltage Vdat, which is used to display an image, to the data lines (D1-Dm).

The signal controller600controls an operation of the scan driver400, the data driver500, a light emission driver, etc.

Each driving device400,500, and600may be directly mounted on the display panel300in at least one integrated circuit (IC) chip form, may be mounted on a flexible printed circuit film (not shown) to be attached to the display panel300in a tape carrier package (TCP) form, or may be mounted on a separate printed circuit board (PCB) (not shown). Alternatively, the driving devices400,500, and600, together with the signal lines (G1-Gn, S1-Sn, and D1-Dm) and the transistors (Qs1-Qs5, Qd) may be formed on the display panel300. Further, the driving devices400,500, and600may be integrated in a single chip and in this case, at least one of them or at least one circuit element constituting them may be disposed at the outside of the single chip.

A display operation of the organic light emitting device is described in detail below with reference toFIG. 1,FIG. 2,FIG. 3,FIG. 4,FIG. 5,FIG. 6, andFIG. 7.

FIG. 3shows an example of a driving signal waveform that may be applied to pixels of a row in an organic light emitting device according to an exemplary embodiment of the present invention, andFIG. 4,FIG. 5,FIG. 6, andFIG. 7are equivalent circuit diagrams of a pixel in each period that is shown inFIG. 3.

The signal controller600receives an input image signal Din and an input control signal ICON for controlling the display of the input image signal Din from an external graphics controller (not shown). The input image signal Din contains luminance information of each pixel PX, and the luminance has grays of a given quantity, for example, 1024 (=210), 256 (=28), or 64 (=26). The input control signal ICON includes, for example, a vertical synchronization signal, a horizontal synchronizing signal, a main clock signal, and a data enable signal.

The signal controller600processes the input image signal Din to correspond to an operating condition of the display panel300based on the input image signal Din and the input control signal ICON, and generates a scanning control signal CONT1and a data control signal CONT2. The signal controller600then sends the scanning control signal CONT1to the scanning driver400, and sends the data control signal CONT2and an output image signal Dout to the data driver500.

The scanning control signal CONT1may include a scanning start signal STV for instructing the scanning start of the high voltage Von to the scanning signal lines (G1-Gn) and the compensation signal lines (S1-Sn), at least one clock signal for controlling an output period of the high voltage Von, and an output enable signal OE for limiting a sustain time period of the high voltage Von.

The data control signal CONT2includes a horizontal synchronization start signal for notifying the transmission start of a digital image signal Dout for one row of pixels PX, and a load signal and a data clock signal HCLK for applying a data signal, such as an analog data voltage, to the data lines (D1-Dm).

The scan driver400sequentially changes a voltage of a scanning signal that is applied to the scanning signal lines (G1-Gn) and a compensation signal that is applied to the compensation signal lines (S1-Sn) to a high voltage Von, and changes the high voltage Von to a low voltage Voff according to the scan control signal CONT1from the signal controller600.

According to the data control signal CONT2from the signal controller600, the data driver500receives a digital output image signal Dout for each row of pixels PX, converts the digital output image signal Dout to an analog data voltage Vdat, and then applies the analog data voltage Vdat to the data lines (D1-Dm). The data driver500outputs a data voltage Vdat for pixels PX of one row for one horizontal period 1H, as shown inFIG. 3.

A specific pixel row, for example an i-th row, is described below.

Referring toFIG. 3, the scan driver400changes a voltage of a scanning signal githat is applied to the scanning signal line Gito a high voltage Von according to a scan control signal CONT1from the signal controller600. In this case, a compensation signal sithat is applied to the compensation signal line Siis in a low voltage Voff state, and a data voltage Vdat that is applied to the data lines (D1-Dm) is a data voltage (VDi−1) for pixels of a previous row and a data voltage VDi for a pixel of a current row. However, when a voltage of the scanning signal gichanges from a low voltage Voff to a high voltage Von, a data voltage Vdat that is applied to the data lines (D1-Dm) may be a data voltage for pixels of a previous row.

If the switching transistor Qs5is intercepted, the organic light emitting element LD does not emit light, and a period from this time point until a voltage of the scanning signal gichanges to a low voltage Voff and the switching transistor Qs5is again electrically connected is a non-light emitting period TR.

If the switching transistor Qs3is in an interception state and the switching transistor Qs4is electrically connected, the driving transistor Qd that has been flowing a current to the organic light emitting element LD instead flows a current to the contact point N2because its output terminal is connected to its control terminal. Thereafter, if a voltage of the contact point N2, (i.e., the difference between a voltage of a control terminal of the driving transistor Qd and a voltage of an input terminal thereof), becomes a threshold voltage Vth of the driving transistor Qd, the driving transistor Qd is in an interception state. In this case, because the switching transistor Qs1is in an electrical connection state, after a data voltage (VDi−1) of a previous pixel row is applied to the contact point N1, a data voltage (VDi) of a current pixel row starts to be applied thereto.

In this way, in this period, because most of the data voltage (VDi−1) of a previous pixel row is charged to the capacitor Cst, this period is called a precharging period T1.

Referring toFIG. 3, the scan driver400changes a voltage of a compensation signal sithat is applied to the compensation signal line Sito a high voltage Von, thereby starting a charging period T2.

Accordingly, as shown inFIG. 5, the switching transistor Qs3is electrically connected, the switching transistors Qs1and Qs4sustain an electrical connection state, and the switching transistors Qs2and Qs5sustain an interception state.

In this state, a data voltage VDi of a current pixel row is applied to the contact point N1, a sustain voltage Vsus is applied to the contact point N2, and a voltage difference between two contact points N1and N2is stored in the capacitor Cst. Therefore, the driving transistor Qd is electrically connected to flow a current, but because the switching transistor Qs5is intercepted, the organic light emitting element LD remains off.

Referring toFIG. 3, as a voltage of the compensation signal sichanges to a low voltage Voff, the switching transistor Qs3is in an interception state, thereby starting a compensation period T3. Because the scanning signal gicontinues to sustain a high voltage Von in the compensation period T3, the switching transistors Qs1and Qs4sustain an electrical connection state, and the switching transistor Qs2and Qs5sustain an interception state.

Accordingly, as shown inFIG. 6, the contact point N2is separated from a sustain voltage Vsus. However, because the driving transistor Qd sustains an electrical connection state, charges that have been charged in the capacitor Cst are discharged through the driving transistor Qd. The discharge stops after being sustained until a voltage difference between a control terminal and an input terminal of the driving transistor Qd becomes a threshold voltage Vth of the driving transistor Qd.

Therefore, a voltage VN2of the contact point N2is converged to the following voltage value.
VN2=Vdd+Vth(Equation 1)

In this case, because a voltage VN1of the contact point N1sustains a data voltage VDiof a current pixel row, a voltage that is stored in the capacitor Cst is represented by Equation 2.
VN1−VN2=VDi−(Vdd+Vth)  (Equation 2)

Thereafter, as shown inFIG. 3, the scan driver400changes a voltage of a scanning signal gito a low voltage Voff, thereby intercepting the switching transistors Qs1and Qs4and electrically connecting the switching transistor Qs2and Qs5, thereby starting a light emitting period TE. Because the compensation signal sicontinues to sustain a low voltage Voff state in the light emitting period TE, the switching transistor Qs3also sustains an interception state.

Thus, as shown inFIG. 7, the contact point N1is separated from the data voltage Vdat and connected to the sustain voltage Vsus, and a control terminal of the driving transistor Qd is floated.

Therefore, a voltage VN2of the contact point N2is represented by Equation 3.
VN2=Vdd+Vth−VDi+Vsus(Equation 3)

Due to electrical connection of the switching transistor Qs5, an output terminal of the driving transistor Qd is connected to the light emitting element LD, and the driving transistor Qd flows an output current ILDthat is controlled by a voltage difference Vgs between its control terminal and input terminal.

Here, K is a constant according to characteristics of the driving transistor Qd. Specifically, K=μ·Ci·W/L, where μ is electric field effect mobility, Ci is capacity of a gate insulating layer, W is a channel width of the driving transistor Qd, and L is a channel length of the driving transistor Qd.

According to Equation 4, an output current ILDof the light emitting period TE is determined by only the constant K, a data voltage Vdat (i.e., VDi), and a fixed sustain voltage Vsus. Therefore, the output current ILDis not influenced by a threshold voltage Vth of the driving transistor Qd.

The output current ILDis supplied to the organic light emitting element LD, and the organic light emitting element LD emits light with different intensities according to a magnitude of the output current ILD, thereby displaying an image.

Therefore, even if a deviation exists in a threshold voltage Vth between the driving transistors Qd or a magnitude of a threshold voltage Vth of each driving transistor Qd sequentially changes, a uniform image can be displayed.

By advancing a time point for forming a voltage of the scanning signal giat a high voltage Von by a necessary time period, light emission of the light emitting element LD is prevented for a desired time period, whereby a time period in which the pixel PX is in a black color state can be extended.

A scan driver for forming such a scanning signal and a compensation signal is described in detail below with reference toFIG. 8,FIG. 9,FIG. 10,FIG. 11, andFIG. 12.

FIG. 8is a block diagram showing a configuration of a scan driver according to an exemplary embodiment of the present invention,FIG. 9shows an example of a circuit diagram of a shift register in the scan driver ofFIG. 8,FIG. 10is a signal waveform diagram of an organic light emitting device having the scan driver ofFIG. 9,FIG. 11shows another example of a circuit diagram of a shift register in the scan driver ofFIG. 8, andFIG. 12is a signal waveform diagram of an organic light emitting device having the scan driver ofFIG. 11.

Referring toFIG. 8, a scan driver400according to an exemplary embodiment of the present invention includes a shift register410, a level shifter460, and a buffer470that are sequentially connected.

The shift register410includes a plurality of stages that are sequentially connected, and a scanning start signal STV, a plurality of clock signals (CK1, CKB1, CK2, and CKB2), and an output enable signal OE are input thereto.

Each stage generates and outputs scanning signals (g1-gn) and compensation signals (s1-sn).

The level shifter460adjusts and outputs a voltage value of scanning signals (g1-gn) and compensation signals (s1-sn) that are output from the shift register410, and the buffer470performs a function of sustaining the scanning signals (g1-gn) and the compensation signals (s1-sn) that are output from the level shifter460.

In the shift register420that is shown inFIG. 9, each stage (STi, STi+1) includes a latch422, a waveform cutter424, and an output definer426.

The latch422delays carry output signals (Ci−1, Ci) (a scanning start signal STV in a first stage) of a previous stage and outputs the carry output signals (Ci−1, Ci) as its own carry output signals (Ci, Ci+1). The latch422includes two clocked inverters and one regular inverter. One clocked inverter inverts carry output signals (Ci−1, Ci) of a previous stage and sends inverted the carry output signals (Ci−1, Ci) to a regular inverter according to the first/second clock signal (CK1/CK2), and the regular inverter inverts and outputs an input signal. Another clocked inverter inverts the output of the regular inverter and sends the inverted output to the regular inverter according to first/second inversion clock signals (CKB1/CKB2).

As shown inFIG. 10, a period of the first clock signal CK1and the second clock signal CK2is two times a horizontal period 1H, and a duty ratio thereof is greater than 50%. The first clock signal CK1and the second clock signal CK2have a phase difference of about 180°, and the first/second inversion clock signal (CKB1/CKB2) is an inversion signal of the first/second clock signal (CK1/CK2), respectively. The scanning start signal STV and the carry output signals (Ci−1, Ci, and Ci+1) sustain a high voltage Von state for two horizontal periods 2H, and each of the carry output signals (Ci, Ci+1) is delayed by about one horizontal period 1H from front end carry output signals (Ci−1, Ci).

The waveform cutter424cuts and outputs an output signal of the latch422according to the second/first clock signal CK2/CK1. The waveform cutter424includes a NAND gate and an inverter. Thus, it is identical to an AND gate from a logical view. The NAND gate uses the output of the latch422and the second/first clock signal CK2/CK1as two inputs, and the output thereof is input to the inverter. The output signal of the waveform cutter424becomes scanning signals (g1-gn), and is in a high voltage state for approximately a high voltage period of the second/first clock signal CK2/CK1.

The output definer426cuts and outputs the output signal of the waveform cutter424according to the output enable signal OE. The output definer426also includes a NAND gate and an inverter. Thus, it is identical to an AND gate from a logical view. The NAND gate uses the output of the waveform cutter424and the output enable signal OE as two inputs, and the output thereof is input to the inverter. A period of the output enable signal OE is identical to one horizontal period 1H, and it may have various duty ratios, including about 50% as shown inFIG. 10. The output of the output definer426becomes compensation signals (s1-sn), which become a high voltage two times while the scanning signals (g1-gn) are at a high voltage.

A period in which the scanning signals (g1-gn) are at a high voltage is longer than one horizontal period 1H, and a data voltage (VD0-VDn−1) (VD0is a null data voltage) of a previous pixel row is applied to each pixel PX for a front half period, and data voltages (VD1-VDn) of the corresponding pixel are applied for a rear half period. The compensation signals (s1-sn) become a high voltage one time for a front half period in a period in which the scanning signals (g1-gn) are at a high voltage, and become a high voltage one more time for a rear half period. Thereby, the driving transistor Qd operates according to the data voltages (VD0-VDn−1) of a previous pixel row, but because the organic light emitting element LD does not operate, each pixel PX does not display the data voltages (VD0-VDn−1) of a previous pixel row with luminance.

Consequently, because each pixel PX displays a black color for a time period that is longer than one horizontal period 1H, an impulse effect may be improved.

In the shift register430ofFIG. 11, each stage (STi, STi+1) includes a latch432, a voltage sustainer434, a waveform cutter436, and an output definer438.

The latch432, which includes two clocked inverters and one regular inverter, delays carry output signals (Ci−1, Ci) (a scanning start signal STV in a first stage) of a previous stage and outputs the carry output signals (Ci−1, Ci) as its own carry output signals (Ci, Ci+1), similar to the latch422ofFIG. 9. One clocked inverter inverts carry output signals (Ci−1, Ci) of a previous stage and sends the inverted carry output signals (Ci−1, Ci) to a regular inverter according to the first/second clock signal CK1/CK2, and the regular inverter inverts and outputs an input signal. Another clocked inverter inverts the output of the regular inverter and sends the inverted output to the regular inverter according to the first/second inversion clock signal CKB1/CKB2.

As shown inFIG. 12, a period of the first clock signal CK1and the second clock signal CK2is two times a horizontal period 1H, and a duty ratio thereof is 50% or below. The first clock signal CK1and the second clock signal CK2have a phase difference of about 180°, and the first/second inversion clock signal CKB1/CKB2is an inversion signal of the first/second clock signal CK1/CK2, respectively. The scanning start signal STV and the carry output signals (Ci−1, Ci, and Ci+1) sustain a high voltage Von state for two horizontal periods 2H, and each of the carry output signals (Ci, Ci+1) is delayed by about one horizontal period 1H from front end carry output signals (Ci−1, Ci).

The voltage sustainer434includes two inverters, and an output thereof becomes scanning signals (gi, gi+1). The scanning signals (g1-gn) sustain a high voltage Von state for two horizontal periods 2H, and each scanning signal (g1-gn) is delayed by about one horizontal period 1H from a scanning start signal STV or front end scanning signals (g1-gn−1). The voltage sustainer434may be omitted, and the carry output signals (Ci−1, Ci, and Ci+1) may be directly used as scanning signals (g1-gn).

The waveform cutter436cuts and outputs an output signal of the latch432according to the second/first clock signal CK2/CK1. The waveform cutter436includes a NAND gate and an inverter. Thus, it is identical to an AND gate from a logical view. The NAND gate uses an output of the latch432and the second/first clock signal CK2/CK1as two inputs, and an output thereof is input to the inverter.

The output definer438cuts and outputs an output signal of the waveform cutter436according to an output enable signal OE. The output definer438also includes a NAND gate and an inverter. Thus, it is identical to an AND gate from a logical view. The NAND gate uses an output of the waveform cutter436and an output enable signal OE as two inputs, and the output thereof is input to the inverter. A period of the output enable signal OE is identical to one horizontal period 1H, and it may have various duty ratios, including about 50% as shown inFIG. 12. The output of the output definer438becomes compensation signals (si, si+1), which become a high voltage only one time while the scanning signals (g1-gn) are a high voltage, unlike the case ofFIG. 9andFIG. 10.

A period in which the scanning signals (g1-gn) are at a high voltage is longer than one horizontal period 1H, and data voltages (VD0-VDn−1) (VD0is a null data voltage) of a previous pixel row are applied to each pixel PX for a front half period and data voltages (VD1-VDn) of the corresponding pixel are applied for a rear half period. A voltage of the compensation signals (S1-Sn) becomes a high voltage one time for a rear half period in a period in which the scanning signals (g1-gn) are at a high voltage.

Consequently, because each pixel PX displays a black color for a time period that is longer than one horizontal period 1H, an impulse effect may be improved. Particularly, in the present exemplary embodiment, a time period in which the scanning signals (g1-gn) are at a high voltage can be lengthened by a desired time period by extending a high voltage period of a scanning start signal STV, and thus a black color display time period can be freely adjusted, as compared with the exemplary embodiment that is described inFIG. 9andFIG. 10.

The scan driver and the driving method thereof shown inFIG. 9,FIG. 10,FIG. 11, andFIG. 12can be applied to other pixels besides the pixel PX shown inFIG. 2, and they can be applied to other display devices besides an organic light emitting device. For example, the scan driver and the method of driving the same can be applied when a scanning signal is in a high voltage state, each pixel receives a data voltage while displaying a black color, and when a scanning signal is in a low voltage state, each pixel stops reception of a data voltage and displays luminance corresponding to its own data voltage. InFIG. 2, even in a case where switching transistors Qs2, Qs3, and Qs4, which compensate a threshold voltage of the driving transistor Qd, are omitted, the scan drivers and the methods of driving the same that are shown inFIG. 9,FIG. 10,FIG. 11, andFIG. 12can be applied. In this case, portions426,436, and438that are related to compensation signals may be omitted.

By adjusting a high voltage period length of the scanning signal, impulse driving can be realized.