Methods of forming integrated circuit devices with crack-resistant fuse structures

A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

CLAIM OF PRIORITY

This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2009-0119506 filed on Dec. 4, 2009 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

Some example embodiments relate to integrated circuit devices and methods of forming the same and, more particularly, to integrated circuit devices with fuse structures and methods of forming the same.

2. Description of the Related Art

Generally, an integrated circuit device may be manufactured by processing, electrical die sorting (EDS), assembling and testing. The EDS may include a pre-laser test for testing semiconductor chips, a laser repair in which redundant chips are substituted for bad chips, and a post-laser test in which the substitutes are tested. The laser repair may be performed by cutting fuses connected to the bad chips and substituting the redundant chips for the bad chips. The fuses may include polysilicon and metal, and are often formed using a copper damascene process.

SUMMARY

In some embodiments, methods include forming a fuse base insulating region on a substrate. The fuse base insulating region may include, for example, an insulating interlayer or a compensation region formed in such an insulating interlayer. An etch stop layer is formed on the fuse base insulating region. An insulating interlayer having a lower dielectric constant than the fuse base insulating region is formed on the etch stop layer. A trench is formed extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

In some embodiments, forming a fuse base insulating region includes forming a first insulating interlayer and forming an insulating interlayer includes forming a second insulating interlayer having a lower dielectric constant than the first insulating interlayer. Forming a trench includes forming a trench extending through the second insulating interlayer and the etch stop layer and at least partially into the first insulating interlayer. The first insulating interlayer may have a greater mechanical strength and/or density than the second insulating interlayer.

In further embodiments, forming a fuse base insulating region includes forming a first insulating interlayer and forming a compensation region in the first insulating interlayer. Forming an insulating interlayer layer includes forming a second insulating interlayer having a lower dielectric constant than the compensation region. Forming a trench includes forming a trench extending through the second insulating interlayer and the etch stop layer and at least partially into the compensation region. The compensation region may have a greater mechanical strength and/or density than the second insulating interlayer. The compensation region may have a greater dielectric constant, mechanical strength and/or density than the first insulating interlayer. The compensation region may be formed by, for example, implanting ions into a portion of the first insulating interlayer, exposing a portion of the first insulating interlayer to ultraviolet radiation or by removing a portion of the first insulating interlayer to form a trench and depositing an insulating material in the trench to form the compensation region.

In some embodiments, methods include forming a first insulating interlayer on a substrate, forming a wiring pattern in the first insulating interlayer, forming an etch stop layer on the first insulating interlayer and the wiring pattern and forming a second insulating interlayer having a lower dielectric constant than the first insulating interlayer on the etch stop layer. A hole and a first trench through the second insulating interlayer are formed to expose portions of the etch stop layer overlying the wiring pattern and a laterally adjacent portion of the first insulating interlayer, respectively. A second trench in fluid communication with the hole in the second insulating interlayer is formed. Portions of the etch stop layer exposed by the hole and the first trench are removed to expose the wiring pattern and the laterally adjacent portion of the first insulating interlayer. A contact plug is formed in the second trench and the hole and a fuse is formed in the first trench. Removing the portions of the etch stop layer exposed by the hole and the first trench may include removing an upper portion of the first insulating interlayer and the fuse may extend at least partially into the first insulating interlayer.

In additional embodiments, methods include forming a first insulating interlayer on a substrate, forming a first wiring pattern in the first insulating interlayer and forming a second insulating interlayer having a dielectric constant lower than the first insulating interlayer on the first insulating interlayer. A first trench is formed extending partially into the second insulating interlayer, overlying the first wiring pattern. A hole and a second trench are formed in the second insulating interlayer, the hole passing from the first trench through the second insulating interlayer to expose the first wiring pattern and the second trench laterally adjacent the first trench and passing through the second insulating interlayer and at least partially into the first insulating interlayer. A contact plug and a second wiring pattern are formed in the hole and the first trench, respectively, and a fuse is formed in the second trench.

In further embodiments, methods include forming a first insulating layer on a substrate and forming a compensation region in the first insulating layer, the compensation region having a greater mechanical strength than the first insulating layer. A second insulating layer is formed on the first insulating layer and the compensation region. A trench is formed extending through the second insulating layer and at least partially into the compensation region. A fuse is formed in the trench.

Further embodiments provide integrated circuit devices. The devices include a first insulating interlayer on a substrate, a first wiring pattern in the first insulating interlayer and a second insulating interlayer on the first insulating interlayer and the first wiring pattern. The devices further include a second wiring pattern in the second insulating interlayer overlying and in electrical contact with the first wiring pattern and a fuse extending through the second insulating interlayer and at least partially into the first insulating interlayer. The first insulating interlayer has a greater mechanical strength than the second insulating interlayer.

In additional embodiments, integrated circuit devices include a first insulating interlayer on a substrate, a compensation region in the first insulating interlayer and having a greater mechanical strength than the first insulating interlayer and a second insulating interlayer on the first insulating interlayer and the compensation region. The devices further include a fuse extending through the second insulating interlayer and at least partially into the compensation region.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, some example embodiments will be explained in detail with reference to the accompanying drawings.

FIGS. 1 to 6are cross-sectional views illustrating a method of forming a fuse structure in accordance with some example embodiments.

Referring toFIG. 1, a first etch stop layer110and a first insulating interlayer120may be sequentially formed on a substrate100.

The substrate100may include a semiconductor substrate, e.g., a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, and the like. Various types of circuit elements such as transistors, capacitors or wirings may be formed on the substrate100, and an insulation layer (not shown) may be further formed between the substrate100and the first etch stop layer110.

The first etch stop layer110may be formed using a material having a high etching selectivity with respect to the first insulating interlayer120. For example, the first etch stop layer110may be formed using a silicon nitride such as silicon carbonitride.

The first insulating interlayer120may be formed using a material having a higher mechanical strength or density than that of a second insulating interlayer150that may be illustrated with reference toFIG. 2. For example, the first insulating interlayer120may be formed using silicon oxide, silicon nitride, silicon oxynitride, or silicon carboxide having a high density. In some example embodiments, the first insulating interlayer120may be formed to have a high dielectric constant more than about 3.5. For example, the first insulating interlayer120may be formed using silicon oxide doped with fluorine having a high dielectric constant more than about 3.5.

An opening (not shown) exposing a portion of the first etch stop layer110may be formed through the first insulating interlayer120, and a first wiring130may be formed on the exposed portion of the first etch stop layer110to fill the opening. The opening may be formed by a photolithography process using a photoresist pattern. Particularly, a hard mask layer (not shown) may be formed on the first insulating interlayer120, and the hard mask layer may be patterned to form a hard mask (not shown) using the photoresist pattern as an etching mask. Thus, the hard mask may serve as an etching mask for forming the opening. The first wiring130may be formed using a metal or polysilicon. In some example embodiments, the first wiring130may be formed by a copper damascene process. A barrier layer (not shown) may be further formed between the first insulating interlayer120and the first wiring130. The barrier layer may be formed using a metal nitride.

Referring toFIG. 2, a second etch stop layer140and a second insulating interlayer150may be sequentially formed on the first insulating interlayer120and the first wiring130.

The second etch stop layer140may be formed using a material having a high etching selectivity with respect to the second insulating interlayer150. The second etch stop layer140may be formed using a material substantially the same as or different from that of the first etch stop layer110.

The second insulating interlayer150may be formed using a material having a low dielectric constant, for example, a dielectric constant less than about 3.5. Thus, a parasitic capacitance between wirings in the second insulating interlayer150may be low. For example, the second insulating interlayer150may be formed using silicon oxide doped with carbon or fluorine or porous silicon carboxide. The second insulating interlayer150may include an insulating material having a modulus equal to or less than about 50 GPa.

Referring toFIG. 3, the second insulating interlayer150may be partially removed by a photolithography process using a photoresist pattern to form a hole152and a first trench154through the second insulating interlayer150. Particularly, a hard mask layer (not shown) may be formed on the second insulating interlayer150, and the hard mask layer may be patterned to form a hard mask (not shown) using the photoresist pattern as an etching mask. Thus, the hard mask may serve as an etching mask for forming the hole152and the first trench154. Thus, portions of the second etch stop layer140may be exposed by the hole152and the first trench154.

Referring toFIG. 4, an upper portion of the second insulating interlayer150may be removed by a photolithography process to form a second trench156in fluid communication with the hole152.

Referring toFIG. 5, the exposed portions of the second etch stop layer140may be removed by an etching process to expose portions of the first wiring130and the first insulating interlayer120. In some example embodiments, when the exposed portions of the second etch stop layer140are removed, the exposed portion of the first insulating interlayer120may be also partially removed, so that the exposed portions of the second etch stop layer140may be sufficiently removed. Thus, the first trench154may extend into an upper portion of the first insulating interlayer120. When the exposed portions of the second etch stop layer140are removed, the exposed portion of the first wiring130may be also partially removed.

Referring toFIG. 6, a contact plug165and a second wiring160filling the hole152and the second trench156, respectively, and a fuse179filling the first trench154may be formed. In particular, a conductive layer may be formed on the first wiring130, the first insulating interlayer120and the second insulating interlayer150to fill the hole152and the first and second trenches154and156. An upper portion of the conductive layer may be planarized by a chemical mechanical polishing (CMP) process and/or an etch back process until a top surface of the second insulating interlayer150is exposed to form the contact plug165, the second wiring160and the fuse170. The conductive layer may be formed using a material having a low resistance, e.g., copper, gold, silver, and the like.

A diffusion barrier layer180covering the second wiring160and the fuse170may be formed on the second insulating interlayer150. The diffusion barrier layer180may be formed using silicon nitride. The diffusion barrier layer180may be formed using a material substantially the same as or different from those of the first and second etch stop layers110and140. The diffusion barrier layer180may reduce or prevent a material of the second wiring160and the fuse170from diffusing into a layer thereon.

Insulating interlayers (not shown) covering other wirings (not shown) may be further formed on the diffusion barrier layer180, and an opening (not shown) may be formed through the insulating interlayers to expose a portion of the diffusion barrier layer180on the fuse170. In a laser repair process, a laser may be scanned onto the fuse170through the exposed portion of the diffusion barrier layer180. The incidence of cracks may be reduced or eliminated because a lower portion of the fuse170may be bounded by the first insulating interlayer120having a high mechanical strength or density. This may allow the use of an expanded energy window in the laser repair process. Additionally, because the lower portion of the fuse170is not covered by the second insulating interlayer150but by the first insulating interlayer120, the second insulating interlayer150containing the second wiring160may be formed using a low-k material having a dielectric constant less than about 3.5.

In some embodiments, when the second insulating interlayer150is partially removed, the second etch stop layer140and the first insulating interlayer120may be also partially removed to form the first trench154extending to the upper portion of the first insulating interlayer120and the hole152exposing the first wiring130. In particular, referring toFIG. 7, portions of the second insulating interlayer150and portions of the second etch stop layer140therebeneath may be partially removed by a photolithography process using a photoresist pattern. The upper portion of the first insulating interlayer120may be also removed so that the portion of the second etch stop layer140may be sufficiently removed. Thus, the first trench154extending to the first insulating inter layer120and the hole152exposing the first wiring130may be formed. An upper portion of the first wiring130may be also removed when the hole152is formed.

Referring toFIG. 8, an upper portion of the second insulating interlayer150may be removed by a photolithography process to form the second trench156in fluid communication with the hole152.

FIGS. 9 and 10are cross-sectional views illustrating operations for forming a fuse structure in accordance with some example embodiments. These operations may be substantially the same as or very similar to those illustrated with reference toFIGS. 1 to 8, except that the hole152and the first trench154are formed after forming the second trench156. Thus, like reference numerals refer to like elements, and repetitive explanations are omitted.

Referring toFIG. 9, after performing the operations illustrated with reference toFIGS. 1 and 2, the second trench156may be formed in the second insulating interlayer150by a photolithography process.

Referring toFIG. 10, portions of the second insulating interlayer150may be removed to form the hole152in fluid communication with the second trench156and the first trench154by a photolithography process. Thus, portions of the second etch stop layer140may be exposed. The exposed portions of the second etch stop layer140may be removed, and an upper portion of the first insulating interlayer140may be also removed. Thus, the first trench154may extend into the first insulating interlayer120. The first wiring130may be also partially removed.

FIGS. 11 to 16are cross-sectional views illustrating operations for forming a fuse structure in accordance with some example embodiments. These operations may be substantially the same as or very similar to those illustrated with reference toFIGS. 1 to 8, except that a compensation region may be formed on a first low-k dielectric layer (a first insulating interlayer).

Referring toFIG. 11, a first etch stop layer210and a first low-k dielectric layer220may be sequentially formed on a substrate200. The first etch stop layer210may be formed using silicon nitride. The first low-k dielectric layer220may be formed using a low-k material having a low dielectric constant, for example, a dielectric constant equal to or less than about 3.5. The first low-k dielectric layer220may be formed using a material substantially the same as that of the second insulating interlayer150inFIGS. 1 to 8. For example, the first low-k dielectric layer220may be formed using silicon oxide doped with carbon or fluorine or porous silicon carboxide.

A photoresist pattern230may be formed on the low-k dielectric layer220, and an ion implantation process may be performed on an upper portion of the first low-k dielectric layer220exposed by the photoresist pattern230to form a compensation region240. In some example embodiments, oxygen ions or nitrogen ions may be implanted into the upper portion of the first low-k dielectric layer220. In some embodiments, ultraviolet rays may be scanned onto the exposed portion of the first low-k dielectric layer220to form the compensation region240. In some example embodiments, the ultraviolet rays may be scanned at a temperature of about 300° C. to about 450° C. The compensation region240may have a higher mechanical strength than the first insulation layer220due an ion implantation process and/or by treatment with ultraviolet rays.

Alternatively, referring toFIG. 12, the compensation region240may be formed by inserting an additional layer on the first insulating interlayer220. In particular, an upper portion of the first insulating interlayer220may be removed by a photolithography process to form a recess225. A material having a higher mechanical strength than that of the first insulating interlayer220may be deposited in the recess225to form the compensation region240. In some example embodiments, the compensation region240may be formed using silicon oxide, silicon nitride or silicon oxynitride. In further example embodiments, the compensation region240may be formed using a material having a modulus equal to or greater than about 20 GPa and having a hardness equal to or greater than 4 GPa. In still further example embodiments, the compensation region240may be formed using a material having a dielectric constant greater than about 3.5.

Referring toFIG. 13, the first low-k dielectric layer220may be partially removed by a photolithography process to form an opening (not shown), and a first wiring250may be formed in the opening using a conductive material, such as a metal or polysilicon. A barrier layer (not shown) may be further formed between the first low-k dielectric layer220and the first wiring250using, for example, a metal nitride.

Referring toFIG. 14, a second etch stop layer260and a second low-k dielectric layer270may be sequentially formed on the first wiring250, the compensation region240and the first low-k dielectric layer220. The second etch stop layer260may be formed using, for example, silicon nitride. The second low-k dielectric layer270may be formed using a low-k material having a dielectric constant equal to or less than about 3.5. The second low-k dielectric layer270may be formed using, for example, silicon oxide doped with carbon or fluorine or porous silicon oxide. A hole272and a first trench274may be formed through the second low-k dielectric layer270to expose portions of the second etch stop layer260, and a second trench276in fluid communication with the hole272may be formed at an upper portion of the second low-k dielectric layer270.

Referring toFIG. 15, the exposed portions of the second etch stop layer260may be removed by an etching process to expose portions of the first wiring250and the compensation region240. In some example embodiments, when the exposed portions of the second etch stop layer260are removed, the exposed portion of the compensation region240may be also partially removed, so that the exposed portions of the second etch stop layer260may be sufficiently removed. Thus, the first trench274may extend into an upper portion of the compensation region240. When the exposed portions of the second etch stop layer260are removed, the exposed portion of the first wiring250may be also partially removed.

Referring toFIG. 16, a contact plug285and a second wiring280filling the hole272and the second trench276, respectively, and a fuse290filling the first trench274may be formed. The contact plug285, the second wiring280and the fuse290may be formed using a material having a low resistance, e.g., copper, gold, silver, and the like. A diffusion barrier layer300covering the second wiring280and the fuse290may be formed on the second low-k dielectric layer270.

As similar to the method illustrated with reference toFIGS. 1 to 10, in a laser repair process, a laser may be scanned onto the fuse290, and the incidence of cracks may be reduced or eliminated because a lower portion of the fuse290may be bounded by the compensation region240having a high mechanical strength or density. This may allow for an expanded energy window in the laser repair process. Additionally, because the lower portion of the fuse290is not covered by the second low-k dielectric layer270, the second low-k dielectric layer containing the second wiring280may be formed using a low-k material.

The inventive subject matter is applicable to any of a variety of fuse structures and wirings formed in low-k dielectric layers. In some embodiments, low-k dielectric layers containing wirings and fuse structures may be formed so that a parasitic capacitance may be reduced, and a compensation region covering a lower portion of the fuse structure may be formed near the low-k dielectric layers to reduce or eliminate the formation of cracks.

According to some example embodiments, a lower portion of a fuse may be covered by a layer having a high mechanical strength, which may help reduce or eliminate the formation of cracks in a laser repair process. Thus, an insulating interlayer may be formed between wirings using a low-k material, and parasitic capacitance may be reduced.