Apparatus and method for mapping and demapping signals in a communication system using a low density parity check code

An apparatus and method for mapping and demapping signals in a system using a Low Density Parity Check (LDPC) code are provided. In the method, LDPC codeword bits are written column-wise and read row-wise, substreams are generated by demultiplexing the read bits using a demultiplexing scheme, and bits included in each of the substreams are mapped to symbols on a signal constellation. The demultiplexing scheme is determined corresponding to a modulation scheme used in the signal transmitter, a length of the LDPC codeword, and a number of the substreams.

PRIORITY

This application claims priority under 35 U.S.C. §119(a) to Korean Patent Application Serial No. 10-2011-0029128, which was filed in the Korean Intellectual Property Office on Mar. 30, 2011, Korean Patent Application Serial No. 10-2011-0034481, which was filed in the Korean Intellectual Property Office on Apr. 13, 2011, Korean Patent Application Serial No. 10-2011-0037531, which was filed in the Korean Intellectual Property Office on Apr. 21, 2011, and Korean Patent Application Serial No. 10-2011-0141033, which was filed in the Korean Intellectual Property Office on Dec. 23, 2011, the content of each of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus and method for mapping and demapping signals in a system using a Low Density Parity Check (LDPC) code.

2. Description of the Related Art

In a communication system, link performance may be significantly degraded by noise, fading, and Inter-Symbol Interference (ISI) of a channel. Therefore, a future-generation communication system is actively considering using LDPC codes as error correction codes.

Along with growing demands for high-rate data transmission and hardware development, the future-generation communication system is actively considering using Quadrature Amplitude Modulation (QAM), which is excellent in terms of frequency efficiency. In QAM, different modulation bits included in one QAM symbol have different error probabilities.

The error correction ability of each LDPC codeword bit included in the LDPC codeword vector is determined according to the degree of a variable node corresponding to the LDPC codeword bit.

Consequently, even though the same LDPC code is used, the error probability of a QAM symbol varies depending on modulation bits of the QAM symbol, to which LDPC codeword bits are mapped. Accordingly, a need exists for a technique for mapping LDPC codeword bits to modulation bits of a QAM symbol, which minimizes the error probability of the QAM symbol.

SUMMARY OF THE INVENTION

Accordingly, embodiments of the present invention are designed to address at least the problems and/or disadvantages described above and to provide at least the advantages described below.

An aspect of the present invention is to provide an apparatus and method for mapping and demapping signals in a system using an LDPC code.

Another aspect of the present invention is to provide an apparatus and method for mapping and demapping between LDPC codewords and QAM symbols in a system using an LDPC code.

In accordance with an aspect of the present invention, a signal transmitter is provided for use in a system using an LDPC code. The signal transmitter includes an interleaver writes LDPC codeword bits column-wise and reads the written LDPC codeword bits row-wise, a demultiplexer generates substreams by demultiplexing the read bits using a demultiplexing scheme, and a symbol mapper maps bits included in each of the substreams to symbols on a signal constellation, The demultiplexing scheme is determined corresponding to a modulation scheme used in the signal transmitter, a length of the LDPC codeword, and a number of the substreams.

In accordance with another aspect of the present invention, a signal receiver is provided for use in a system using an LDPC code. The signal receiver includes a multiplexer multiplexes substreams using a multiplexing scheme, a deinterleaver deinterleaves the multiplexed bits, and an LDPC decoder generates LDPC codeword bits by LDPC-decoding the deinterleaved bits. The multiplexing scheme is determined corresponding to a demultiplexing scheme used in a signal transmitter, and the demultiplexing scheme is determined corresponding to a modulation scheme used in the signal transmitter, a length of an LDPC codeword, and a number of the substreams.

In accordance with another aspect of the present invention, a signal mapping method is provided for a signal transmitter in a system using an LDPC code. In the method, LDPC codeword bits are written column-wise and read row-wise, substreams are generated by demultiplexing the read bits using a demultiplexing scheme, and bits included in each of the substreams are mapped to symbols on a signal constellation. The demultiplexing scheme is determined corresponding to a modulation scheme used in the signal transmitter, a length of the LDPC codeword, and a number of the substreams.

In accordance with another aspect of the present invention, a signal demapping method is provided for a signal receiver in a system using an LDPC code. In the method, substreams are multiplexed using a multiplexing scheme, the multiplexed bits are deinterleaved, and LDPC codeword bits are generated by LDPC-decoding the deinterleaved bits. The multiplexing scheme is determined corresponding to a demultiplexing scheme used in a signal transmitter, and the demultiplexing scheme is determined corresponding to a modulation scheme used in the signal transmitter, a length of an LDPC codeword, and a number of the substreams.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

In accordance with an embodiment of the present invention, an apparatus and method are provided for mapping and demapping signals in a system using an LDPC code.

In accordance with another embodiment of the present invention, an apparatus and method are provided for mapping and demapping between LDPC codewords and QAM symbols.

The following description of the present invention is provided for a system using LDPC codes, for example, a broadcasting system such as Digital Video Broadcasting (DVB)-Next Generation Handheld (NGH) or a communication system such as Moving Picture Experts Group (MPEG) Media Transport (MMT), Evolved Packet System (EPS), Long-Term Evolution (LTE), and Institute of Electrical and Electronics Engineers (IEEE) 802.16m.

While the present invention is described in the context of an LDPC code and QAM modulation schemes, it is to be clearly understood that the apparatus and method of the present invention are also applicable to other codes and other modulation schemes.

FIG. 2is a block diagram illustrating a signal transmitter in a system using an LDPC code according to an embodiment of the present invention.

Referring toFIG. 2, the signal transmitter includes an LDPC encoder210, a pre-processor220, an interleaver230, a DEMUX unit240, and a symbol mapper250.

The LDPC encoder210generates a parity vector {ρ0, ρ1, . . . , ρNldpc-Kldpc-1} including Nldpc-Kldpcparity bits and then an LDPC codeword vector of length Nldpcby encoding an information word vector I={i0, i1, . . . , iKldpc-1}. The pre-processor220generates a vector U={μ0, μ1, . . . , μNldpc-1} by pre-processing the LDPC codeword vector Λ received from the LDPC encoder210using a predetermined pre-processing scheme. Alternatively, the pre-processor220may be omitted or its function may be incorporated into the interleaver230. A detailed description of the pre-processing scheme is not provided herein.

The interleaver230writes the vector U received from the pre-processor220column-wise in Nc columns and reads the vector U row-wise, thus outputting a vector V={v0, v1, . . . , vNldpc-1} to the DEMUX UNIT240. The DEMUX UNIT240demultiplexes the vector V into Nsubstreamssubstreams Bi={bi,0, bi,1, . . . , bi,Nldpc/Nsubstreams−1} (i=0, 1, . . . , Nsubstreams−1) each having Nc bits. For the input of the bits of each of the Nsubstreamssubstreams, the symbol mapper250generates a cell word of length η MOD, ┌y0, y1, . . . yμ MOD-1┐ and maps the cell word to signal points on a signal constellation, thereby producing a symbol Z. Herein η MOD is a divisor of Nsubstreams.

FIGS. 3,4, and5illustrate mapping relationships between cell words and signal constellations in 16-QAM, 64-QAM, and 256-QAM, respectively, according to embodiments of the present invention.

FIG. 6illustrates an operation of the interleaver230illustrated inFIG. 2according to an embodiment of the present invention. Specifically, inFIG. 6, it is assumed that the interleaver230has Nc rows×Nldpc/Nc columns.

If Nldpc=16200, the number of rows Nr and the number of columns Nc are given for 16-QAM and 64-QAM as shown in Table 1.

The interleaver230sequentially writes the received vector U column-wise in Nc columns and reads the written vector row-wise. Herein, the first storing position of each column may be shifted by a twisting parameter tc. The twisting parameter tc may have the values shown in Table 2 for 16-QAM and 64-QAM, when Nldpc=16200, for example.

FIG. 7illustrates an operation of a DEMUX unit illustrated inFIG. 2according to an embodiment of the present invention.

Referring toFIG. 7, the operation of the DEMUX UNIT240may be expressed as the relationship between Vi (i=0, 1, . . . , Nldpc−1) and bj (j=0, 1, . . . , Nsubstreams−1), which may be extended in the same rule, if Nldpc, is a multiple of Nsubstreams.

FIG. 8illustrates an operation of the DEMUX UNIT240, when Nldpc=16200 and 16-QAM is used, according to an embodiment of the present invention.

FIG. 9illustrates an operation of the DEMUX UNIT240, when Nldpc=16200 and 64-QAM is used, according to an embodiment of the present invention.

FIG. 10illustrates another operation of the DEMUX UNIT240, when Nldpc=16200 and 16-QAM is used, according to an embodiment of the present invention.

FIG. 11illustrates another operation of the DEMUX UNIT240, when Nldpc=16200 and 16-QAM is used, according to an embodiment of the present invention.

FIG. 12illustrates another operation of the DEMUX UNIT240, when Nldpc=16200 and 64-QAM is used, according to an embodiment of the present invention.

FIG. 13illustrates another operation of the DEMUX UNIT240, when Nldpc=16200 and 64-QAM is used, according to an embodiment of the present invention.

FIG. 14illustrates another operation of the DEMUX UNIT240, when Nldpc=16200 and 64-QAM is used, according to an embodiment of the present invention.

FIG. 15illustrates an operation of the DEMUX UNIT240, when Nldpc=16200 and 256-QAM is used, according to an embodiment of the present invention.

FIG. 16illustrates another operation of the DEMUX UNIT240, when Nldpc=16200 and 256-QAM is used, according to an embodiment of the present invention.

As described above, in accordance with the embodiments of the present invention, the DEMUX unit provides LDPC codeword bits to the symbol mapper according to a predetermined mapping rule. Therefore, when the LDPC codeword bits are mapped to symbols (e.g., symbols on a QAM signal constellation), the symbols have different performances according to different mapping rules.

FIG. 17is a block diagram illustrating a signal receiver in the system using the LDPC code, according to an embodiment of the present invention.

Referring toFIG. 17, the signal receiver includes a bit metric calculator1710, a MUX unit1720, a deinterleaver1730, a post-processor1740, and an LDPC decoder1750.

The MUX UNIT1720generates a bit metric vector estimate of length Nldpc, {circumflex over (V)}={{circumflex over (ν)}0, {circumflex over (ν)}1, . . . , {circumflex over (ν)}Nldpc−1} by multiplexing the bit metric estimates {circumflex over (B)}i, i=0, 1, . . . , Nsubstreams−1 received from the bit metric calculator1710. The deinterleaver1730deinterleaves the bit metric vector estimate {circumflex over (V)} using a deinterleaving scheme corresponding to the interleaving scheme used in the signal transmitter, thereby producing a bit metric vector estimate Û={{circumflex over (μ)}0, {circumflex over (μ)}1, . . . , {circumflex over (μ)}Nldpc−1} of U={μ0, μ1, . . . , μNldpc-1}.

FIG. 18is a block diagram illustrating the DEMUX unit240illustrated inFIG. 2, according to an embodiment of the present invention.

Referring toFIG. 18, the DEMUX unit240includes a DEMUX1811and a selection signal generator1813.

The DEMUX1811generates Nsubstreamssubstreams from the vector V received from the interleaver230using selection signals received from the selection signal generator1813. The selection signal generator1813determines a substream to which each bit of the vector V is to be allocated, and then outputs a selection signal by reading a value stored in a storage, for example, a memory, or generating a signal using a predetermined rule. The selection signal output from the selection signal generator1813is determined according to the type, codeword length, code rate, and modulation scheme of an error correction code used in the system. The selection signal is an important factor that affects the error correction capability of the system.

FIG. 19is a block diagram illustrating the MUX unit1720illustrated inFIG. 17, according to an embodiment of the present invention.

Referring toFIG. 19, the MUX unit1720includes a MUX1911and a selection signal generator1913. The MUX1911outputs an estimate of an interleaved codeword from Nsubstreamssubstreams using selection signals received from the selection signal generator1913. The selection signal generator1913determines a substream from which each bit of an estimated interleaved codeword is obtained. The selection signal generator1913outputs a selection signal by reading a value stored in a memory or generating a signal using a predetermined rule. The MUX unit1720performs multiplexing using a manner corresponding to demultiplexing of the DEMUX unit240as illustrated inFIG. 2.

As is apparent from the description above, various embodiments of the present invention can minimize the error probability of a system using an LDPC code, and thus, improve overall system performance by enabling mapping of LDPC codeword bits to modulation symbols according to a used modulation scheme.