Solar cell

A solar cell including a non-amorphous semiconductor substrate of a first conductive type; at least a first semiconductor layer on the non-amorphous semiconductor substrate, the first semiconductor layer including a portion that is amorphous and a plurality of portions having crystal lumps, so that the plurality of portions having the crystal lumps are distributed in the first semiconductor layer; a first electrode on the semiconductor substrate; and a second electrode on the semiconductor substrate.

BACKGROUND OF THE INVENTION

Field of the Invention

Embodiments of the invention relate to a solar cell.

Discussion of the Related Art

Recently, as existing energy sources such as petroleum and coal are expected to be depleted, interests in alternative energy sources for replacing the existing energy sources are increasing. Among the alternative energy sources, solar cells have been particularly spotlighted because, as cells for generating electric energy from solar energy, the solar cells are able to draw energy from an abundant source and do not cause environmental pollution.

A solar cell generally includes a substrate and an emitter layer, each of which is formed of a semiconductor, and electrodes respectively formed on the substrate and the emitter layer. The semiconductors forming the substrate and the emitter layer have different conductive types, such as a p-type and an n-type. A p-n junction is formed at an interface between the substrate and the emitter layer.

When light is incident on the solar cell, a plurality of electron-hole pairs are generated in the semiconductor. The electron-hole pairs are separated into electrons and holes by a photovoltaic effect. Thus, the separated electrons move to the n-type semiconductor (e.g., the emitter layer) and the separated holes move to the p-type semiconductor (e.g., the substrate), and then the electrons and holes are collected by the electrodes electrically connected to the emitter layer and the substrate, respectively. The electrodes are connected to each other using electric wires to thereby obtain electric power.

The plurality of electrodes electrically connected to the emitter layer and the substrate collect the electrons and the holes moving to the emitter layer and the substrate and allow the electrons and the holes to move to a load connected to the outside.

However, in this case, because the electrode is formed on the emitter layer on a light incident surface of the substrate as well as a non-incident surface of the substrate, an incident area of light decreases. Hence, efficiency of the solar cell is reduced.

Accordingly, a back contact solar cell, in which all of electrodes collecting electrons and holes are positioned on a rear surface of a substrate, has been developed so as to increase an incident area of light.

SUMMARY OF THE INVENTION

In one aspect, there is a solar cell including a semiconductor substrate of a first conductive type, a first semiconductor layer of a second conductive type opposite the first conductive type on the semiconductor substrate, the first semiconductor layer including a crystal lump, a first electrode on the semiconductor substrate, the first electrode being electrically connected to the semiconductor substrate, and a second electrode on the semiconductor substrate, the second electrode being electrically connected to the first semiconductor layer.

The first semiconductor layer may have a crystallinity equal to or less than about 10%.

The solar cell may further include a second semiconductor layer of the first conductive type on the semiconductor substrate. The second semiconductor layer may include a crystal lump. The second semiconductor layer may have a crystallinity equal to or less than about 30%.

The solar cell may further include an intrinsic semiconductor layer on the semiconductor substrate. The intrinsic semiconductor layer may include a crystal lump. The intrinsic semiconductor layer may have a crystallinity equal to or less than about 10%.

The semiconductor substrate and the first semiconductor layer may form a hetero junction.

In another aspect, there is a solar cell comprising a substrate of a first conductive type, an emitter layer of a second conductive type opposite the first conductive type on the substrate, the emitter layer including a crystal lump, a first electrode electrically connected to the emitter layer, and a second electrode on the substrate, the second electrode being electrically connected to the substrate, wherein the substrate and the emitter layer form a hetero junction, wherein the emitter layer has a crystallinity equal to or less than about 10%.

The substrate may be formed of single crystal silicon or polycrystalline silicon, and the emitter layer may be formed of amorphous silicon.

The solar cell may further include a back surface field layer between the substrate and the second electrode. The back surface field layer may include a crystal lump. The back surface field layer may have a crystallinity greater than the crystallinity of the emitter layer. The crystallinity of the back surface field layer may be equal to or less than about 30%.

The solar cell may further include at least one passivation layer on the substrate. The at least one passivation layer may include a crystal lump. The at least one passivation layer may have a crystallinity equal to or less than about 10%. The at least one passivation layer may include a front passivation layer on a front surface of the substrate and a rear passivation layer on a rear surface of the substrate.

The emitter layer and the back surface field layer may be positioned on the rear surface of the substrate. The rear passivation layer may be positioned on the substrate between the emitter layer and the back surface field layer.

The emitter layer may be positioned on the front surface of the substrate, and the back surface field layer may be positioned on the rear surface of the substrate. The rear passivation layer may be positioned between the substrate and the back surface field layer.

The solar cell may further include a transparent conductive layer on the emitter layer and a conductive layer between the back surface field layer and the second electrode.

In another aspect, there is a solar cell Including a non-amorphous semiconductor substrate of a first conductive type; at least a first semiconductor layer on the non-amorphous semiconductor substrate, the first semiconductor layer including at least one portion that is crystalline and another portion that is amorphous; a first electrode on the semiconductor substrate; and a second electrode on the semiconductor substrate.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The invention will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the inventions are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings.

First, referring toFIGS. 1 and 2, an example of solar cell according to an embodiment of the invention will be described.

FIG. 1is a partial perspective view of an example of a solar cell according to an embodiment of the invention.FIG. 2is a cross-sectional view taken along line II-II ofFIG. 1.

As shown inFIGS. 1 and 2, a solar cell1according to an embodiment of the invention includes a substrate110, a front passivation layer191on a front surface of the substrate110on which light is incident, an anti-reflection layer130on the front passivation layer191, a plurality of emitter layers120on a rear surface of the substrate110, opposite the front surface of the substrate110, on which light is not incident, a plurality of back surface field (BSF) layers172that are positioned on the rear surface of the substrate110to be spaced apart from the plurality of emitter layers120, a rear passivation layer192positioned between the plurality of emitter layers120and the plurality of BSF layers172on the rear surface of the substrate110, a plurality of first electrodes141on the plurality of emitter layers120, and a plurality of second electrodes142on the plurality of BSF layers172.

The substrate110is a semiconductor substrate formed of first conductive type silicon, for example, n-type silicon, though not required. Silicon used in the substrate110is crystalline silicon, such as single crystal silicon and polycrystalline silicon. If the substrate110is of an n-type, the substrate110may contain impurities of a group V element, such as phosphor (P), arsenic (As), and antimony (Sb). Alternatively, the substrate110may be of a p-type, and/or be made of other materials than silicon. If the substrate110is of the p-type, the substrate110may contain impurities of a group III element, such as boron (B), gallium (Ga), and Indium (In).

The front surface of the substrate110is textured to form a textured surface corresponding to an uneven surface or having uneven characteristics.

The front passivation layer191on the textured surface of the substrate110converts defects, like a dangling bond, existing around the surface of the substrate110into stable bonds to reduce a recombination and/or a disappearance of carriers (e.g., holes) moving to the substrate110resulting from the defects.

The front passivation layer191is formed of amorphous silicon and is an intrinsic region.

The front passivation layer191includes a plurality of crystal lumps181, each of which is comprised of polycrystals.

Each of the crystal lumps181is polycrystalline silicon obtained by performing an epitaxial growth on the front passivation layer191using crystalline silicon of the substrate110as a seed crystal. Most of the crystal lumps181are formed in a portion of the front passivation layer191adjoining the substrate110.

In embodiments of the invention, the front passivation layer191includes regions or portions that are non-amorphous. Such non-amorphous regions or portions may be distributed in the portion of the front passivation layer191adjoining the substrate110, such that the non-amorphous regions or portions may be referred to as the crystal lumps181. One or more of the crystal lumps181may be present in the front passivation layer191, and the crystal lumps181may form a crystalline sublayer or the crystalline sublayer may contain crystal lumps181. In embodiments of the invention, the crystalline sublayer may be formed by the crystal lumps181being joined together in a continuous layer, but such is not required. In other embodiments, the crystal lumps181may be discontinuously distributed in the portion of the front passivation layer191adjoining the substrate110.

The crystal lumps181collect electrons moving to the front passivation layer191to thereby cause a loss of carriers.

When crystal lumps being polycrystalline silicon are grown on a passivation layer formed of amorphous silicon based on a substrate formed of single crystal silicon, a relationship between carrier lifetime and crystallinity of the passivation layer is described with reference toFIG. 3. In the embodiment, the crystallinity indicates a percentage of a volume of polycrystalline silicon grown using the substrate110as a seed layer based on a total volume of a layer (e.g., the front passivation layer191) formed on the substrate110.

FIG. 3is a graph measuring carrier lifetime depending on crystallinity of a front passivation layer formed of amorphous silicon when crystal lumps are grown on the front passivation layer using a substrate formed of single crystal silicon as a seed layer.

As shown inFIG. 3, as the crystallinity of the front passivation layer191is increased (i.e., as an amount of polycrystalline silicon grown on the front passivation layer191increased), lifetime Teff of carriers (e.g., holes) decreased. In other words, as an amount of grown polycrystalline silicon is increased, an amount of carriers that disappears by the grown polycrystalline silicon is increased.

However, when the crystallinity of the front passivation layer191was equal to or less than about 10%, lifetime Teff of charges (or holes) serving as minority carriers in the substrate110was held at a reference time (for example, was equal to or more than about 1 ms). In other words, the lifetime Teff of the charges greatly increased. In this case, the reference time is determined depending on a magnitude of an open-circuit voltage Voc. When the lifetime of minority carriers is equal to or more than about 1 ms, an open-circuit voltage capable of manufacturing a solar cell with high efficiency is obtained. As a result, when the lifetime of the minority carriers is equal to or more than about 1 ms, a solar cell with high efficiency can be manufactured. Regarding the lifetime Teff of minority carriers being a reference time, such a reference time need not be equal to or more than about 1 ms in embodiments of the invention. The lifetime Teff of minority carriers may be equal to or greater than about 0.1 ms (i.e., 100 μs), and may also be equal to or greater than 0.2 ms (i.e., 200 μs).

It could be understood fromFIG. 3that when the crystallinity of the front passivation layer191formed of amorphous silicon was equal to or greater than about 10%, the carrier lifetime decreased because of an increase in an amount of carriers disappeared by the grown polycrystalline silicon.

Accordingly, in the embodiment, an amount of carriers disappeared by grown polycrystalline silicon decreases by allowing the crystallinity of the front passivation layer191to be equal to or less than about 10%, and thus a reduction in the carrier lifetime is reduced or prevented. As a result, as the crystallinity of the front passivation layer191is close to about 0%, amorphization of the epitaxial grown polycrystalline silicon is accelerated. Hence, an amount of carriers that disappear decreases, and the efficiency of the solar cell1is improved.

Referring again toFIGS. 1 and 2, the anti-reflection layer130on the front passivation layer191is formed of silicon nitride (SiNx) or silicon oxide (SiOx), for example. The anti-reflection layer130reduces a reflectance of light incident on the solar cell1and increases a selectivity of a predetermined wavelength band. Hence, the efficiency of the solar cell1is improved. In the embodiment, the anti-reflection layer130has a single-layered structure. However, the anti-reflection layer130may have a multi-layered structure, such as a double-layered structure, and may be omitted if necessary.

The plurality of emitter layers120on the rear surface of the substrate110are formed of a semiconductor of a second conductive type (e.g., a p-type) opposite the first conductive type of the substrate110, and the semiconductor (e.g., amorphous silicon) of the emitter layers120is different from the substrate110. Thus, the emitter layer120and the substrate110form a hetero junction as well as a p-n junction.

As shown inFIG. 1, the plurality of emitter layers120are positioned substantially parallel to one another to be spaced apart from one another and extend in a predetermined direction.

If the emitter layers120are of a p-type, the emitter layers120may contain impurities of a group III element, such as boron (B), gallium (Ga), and Indium (In). On the contrary, if the emitter layers120are of an n-type, the emitter layers120may contain impurities of a group V element, such as phosphor (P), arsenic (As), and antimony (Sb).

Similar to the front passivation layer191, each of the emitter layers120includes a plurality of crystal lumps182, each of which is comprised of polycrystals.

As described above, each of the crystal lumps182is formed by epitaxial growing polycrystalline silicon on each of the emitter layers120using the substrate110formed of crystalline silicon as a seed layer. Most of the crystal lumps182are formed in a portion of each emitter layer120adjoining the substrate110.

In embodiments of the invention, the emitter layers120, being an amorphous silicon layer, includes regions or portions that are non-amorphous. Such non-amorphous regions or portions may be distributed in the portion of the emitter layers120adjoining the substrate110, such that the non-amorphous regions or portions may be referred to as the crystal lumps182. One or more of the crystal lumps182may be present in the emitter layers120, and the crystal lumps182may form a crystalline sublayer or the crystalline sublayer may contain crystal lumps182. In embodiments of the invention, the crystalline sublayer may be formed by the crystal lumps182being joined together in a continuous layer, but such is not required. In other embodiments, the crystal lumps182may be discontinuously distributed in the portion of the emitter layers120adjoining the substrate110.

When crystal lumps are grown on the emitter layer120formed of amorphous silicon using the substrate110formed of single crystal silicon as a seed layer, a relationship between carrier lifetime and crystallinity of the emitter layer120is described with reference toFIG. 4.

FIG. 4is a graph measuring carrier lifetime depending on crystallinity of an emitter layer formed of amorphous silicon when crystal lumps are grown on the emitter layer using a substrate formed of single crystal silicon as a seed layer.

As shown inFIG. 4, when the emitter layer120had crystallinity equal to or less than about 10%, carrier lifetime Teff was equal to or more than about 0.2 ms corresponding to a reference time. When the crystallinity of the emitter layer120was greater than about 10%, the carrier lifetime Teff was equal to or less than about 0.2 ms.

It could be understood fromFIG. 4that when the crystallinity of the emitter layer120formed of amorphous silicon was equal to or less than about 10%, the carrier lifetime was equal to or more than the reference time capable of manufacturing a hetero junction solar cell with high efficiency.

Accordingly, in the embodiment, each of the emitter layers120has the crystallinity equal to or less than about 10% so as to reduce carrier disappearance resulting from the grown crystal lumps182.

Referring again toFIGS. 1 and 2, the plurality of BSF layers172on the rear surface of the substrate110are separated from the plurality of emitter layers120and extend substantially parallel to one another in the same direction as the emitter layers120. Thus, the plurality of emitter layers120and the plurality of BSF layers172are alternately positioned on the rear surface of the substrate110.

The BSF layers172are formed of amorphous silicon and are a region (e.g., an n+-type region) that is more heavily doped with impurities of the same conductive type as the substrate110than the substrate110.

Holes moving to the rear surface of the substrate110are reduced or prevented from moving to the second electrodes142because of a potential barrier resulting from a difference between impurity doping concentrations of the substrate110and the BSF layer172. Therefore, a recombination and/or a disappearance of the electrons and holes are reduced around the second electrodes142.

Because the BSF layers172on the substrate110formed of crystalline silicon are formed of amorphous silicon, each of the BSF layers172includes a plurality of crystal lumps183, each of which is comprised of polycrystals. As described above, each of the crystal lumps183is formed by epitaxial growing polycrystalline silicon on each of the BSF layers172using the substrate110as a seed layer.

In embodiments of the invention, the BSF layers172, being an amorphous silicon layer, includes regions or portions that are non-amorphous. Such non-amorphous regions or portions may be distributed in the portion of the BSF layers172adjoining the substrate110, such that the non-amorphous regions or portions may be referred to as the crystal lumps183. One or more of the crystal lumps183may be present in the BSF layers172, and the crystal lumps183may form a crystalline sublayer or the crystalline sublayer may contain crystal lumps183. In embodiments of the invention, the crystalline sublayer may be formed by the crystal lumps183being joined together in a continuous layer, but such is not required. In other embodiments, the crystal lumps183may be discontinuously distributed in the portion of the BSF layers172adjoining the substrate110.

When crystal lumps are grown on the BSF layers172formed of amorphous silicon based on the substrate110formed of single crystal silicon, a relationship between carrier lifetime and crystallinity of the BSF layers172is described with reference toFIG. 5.

FIG. 5is a graph measuring carrier lifetime depending on crystallinity of a BSF layer formed of amorphous silicon when crystal lumps are grown on the BSF layer using a substrate formed of single crystal silicon as a seed layer.

As shown inFIG. 5, when the BSF layers172had crystallinity equal to or less than about 30%, carrier lifetime Teff was equal to or more than about 0.1 ms corresponding to a reference time. When the crystallinity of the BSF layers172was greater than about 30%, the carrier lifetime Teff was equal to or less than about 0.1 ms.

Accordingly, in the embodiment, each of the BSF layers172has the crystallinity equal to or less than about 30% so as to reduce carrier disappearance resulting from the grown crystal lumps183.

The BSF layers172of the same conductive type as the substrate110have the crystallinity greater than the crystallinity of the emitter layers120of the conductive type opposite the conductive type of the substrate110. This reason is as follows.

In the embodiment, the BSF layers172of the same conductive type (i.e., the n-type) as the substrate110contain a group V element as a dopant. Because one electron of the group V element is released so that the group V element combines with silicon of the substrate110adjoining the BSF layers172, fixed charges of atoms existing in the surface of the BSF layer172have a positive (+) value. As a result, because the fixed charges of the BSF layers172have the same positive value as holes serving as minority carrier in the substrate110, the movement of holes to the BSF layers172is disturbed because of electrical repellent force.

On the contrary, the emitter layers120of the conductive type opposite the conductive type of the substrate110contain a group III element as a dopant. Because the group III element obtains one electron so that the group III element combines with silicon of the substrate110adjoining the emitter layers120, fixed charges of atoms existing in the surface of the emitter layers120have a negative (−) value. As a result, because the fixed charges of the emitter layers120have the negative (−) value opposite the positive (+) value of the holes, the movement of holes to the emitter layers120is accelerated.

Because of the above-described reason, an amount of the minority carriers disappeared by epitaxial grown polycrystalline silicon when a semiconductor material of the same conductivity type as the substrate110is positioned on the substrate110is less than an amount of the minority carriers disappeared by epitaxial grown polycrystalline silicon when a semiconductor material of a conductivity type opposite the conductivity type of the substrate110is positioned on the substrate110. Accordingly, the crystallinity of the BSF layers172of the same conductivity type as the substrate110may be greater than the crystallinity of the emitter layers120of the conductivity type opposite the conductivity type of the substrate110.

A plurality of electron-hole pairs produced by light incident on the substrate110are separated into electrons and holes by a built-in potential difference resulting from the p-n junction formed by the substrate110and the emitter layers120. Then, the separated electrons move to an n-type semiconductor, and the separated holes move to a p-type semiconductor. Thus, when the substrate110is the n-type semiconductor and the emitter layers120are the p-type semiconductors, the separated holes move to the emitter layers120and the separated electrons move to the BSF layers172whose impurity doping concentration is greater than the impurity doping concentration of the substrate110.

Because each of the emitter layers120forms the p-n junction together with the substrate110, the emitter layers120may be of the n-type if the substrate110is of the p-type unlike the embodiment described above. In this case, the separated electrons move to the emitter layers120and the separated holes move to the BSF layers172.

The rear passivation layer192between the plurality of emitter layers120and the plurality of BSF layers172is formed of a non-conductive material such as amorphous silicon in the same manner as the front passivation layer191. The rear passivation layer192converts defects, like a dangling bond, existing around the surface of the substrate110into stable bonds to reduce a recombination and/or a disappearance of carriers (e.g., electrons) moving to the rear surface of the substrate110resulting from the defects and prevents an electric interference between the first and second electrodes141and142.

The rear passivation layer192includes a plurality of epitaxial grown crystal lumps184that are mostly formed in a portion of the rear passivation layer192adjoining the substrate110, in the same manner as the front passivation layer191. Accordingly, discussion of the crystalline sublayer with regard to the front passivation layer191applies also to the rear passivation layer192.

Because the crystal lumps184have the same carrier lifetime characteristic asFIG. 3in the same manner as the crystal lumps181, the rear passivation layer192has crystallinity equal to or less than about 10%.

The plurality of first electrodes141respectively on the plurality of emitter layers120extend along the emitter layers120and are electrically connected to the emitter layers120. Each of the first electrodes141collects carriers (e.g., holes) moving to the corresponding emitter layer120.

The plurality of second electrodes142respectively on the plurality of BSF layers172extend along the BSF layers172and are electrically connected to the BSF layers172. Each of the second electrodes142collects carriers (e.g., electrons) moving to the corresponding BSF layers172.

The first electrodes141and the second electrodes142may be formed of at least one conductive material selected from the group consisting of nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti), gold (Au), and a combination thereof. Other conductive materials may be used.

In the solar cell1according to the embodiment of the invention having the above-described structure, the plurality of first electrodes141and the plurality of second electrodes142are positioned on the rear surface of the substrate110on which light is not incident, and the substrate110and the plurality of emitter layers120are formed of different conductive types of semiconductors. An operation of the solar cell1is described below.

When light irradiated to the solar cell1sequentially passes through the anti-reflection layer130and the front passivation layer191and then is incident on the substrate110, a plurality of electron-hole pairs are generated in the substrate110by light energy based on the incident light. In this case, because the front surface of the substrate110is a textured surface, a light reflectance in the front surface of the substrate110is reduced. Further, because both a light incident operation and a light reflection operation are performed on the textured surface, a light absorptance increases. Hence, the efficiency of the solar cell1is improved. In addition, because a reflection loss of light incident on the substrate110is reduced by the anti-reflection layer130, an amount of light incident on the substrate110further increases.

The electron-hole pairs are separated by the p-n junction of the substrate110and the emitter layer120. Then, the separated holes move to the p-type emitter layers120, and the separated electrons move to the n-type BSF layers172. The holes and the electrons are collected by the first electrodes141and the second electrodes142. When the first electrodes141are connected to the second electrodes142using electric wires (not shown), current flows therein to thereby enable use of the current for electric power.

In the embodiment, because a loss of carriers resulting from the crystal lumps181to184is reduced by controlling the crystallinity of each of the components191,120,172, and192adjoining the substrate110, the efficiency of the solar cell1is improved. Also, in embodiments of the invention, the crystallinity of the n-type BSF layers172is greater than the crystallinity of the p-type the emitter layers120, when the substrate110is n-type. Accordingly, a crystallinity of a layer having the same conductivity type as a conductivity of the substrate may be greater than a crystallinity of a layer having a different conductivity type from the conductivity of the substrate.

Next, referring toFIGS. 6 to 10, other examples of the solar cell according the embodiment of the present invention will be described.

FIGS. 6 and 10are cross-sectional views of other examples of a solar cell according an embodiment of the present invention, respectively.

In comparing solar cells11to15shown inFIGS. 6 to 10to the solar cell1shown inFIGS. 1 and 2, except a formation position of a rear passivation layer and the crystallinity of the rear passivation layer, a plurality of emitter layers and a plurality of BSF layers, the solar cells11to15have the same structures as the solar cell1. Thereby, as compared withFIGS. 1 and 2, the elements performing the same operations are indicated as the same reference numerals, and the detailed description thereof is omitted. In addition, a partial perspective view of each solar cell11to15is omitted.

In the solar cell11shown inFIG. 6, the rear passivation1921is an intrinsic region made of amorphous silicon and is positioned on the entire rear surface of the substrate110. The plurality of emitter layers120and the plurality of BSF layers172are spaced apart from each other and positioned on the rear passivation layer. The rear passivation layer1921has a thickness not to prevent the movement charges moving to the emitter layers120and the BSF layers172.

As above-described referring toFIGS. 1 and 2, the rear passivation layer1921converts defects existing around the surface of the substrate110into stable bonds to reduce a recombination and/or a disappearance of charges moving to the rear surface of the substrate110resulting from the defects. At this time, since the rear passivation layer1921is positioned on the entire rear surface of the substrate110, an amount of the recombination and/or disappearance of charges is largely reduced and a current leakage phenomenon between the first and second electrodes141and142is prevented or decreased.

The rear passivation layer1921includes a plurality of crystal lumps1811that are epitaxy grown and have crystallinity equal to or less than about 10% like the rear passivation layer192shown inFIGS. 1 and 2.

In the solar cell12shown inFIG. 7, the rear passivation layer1922is positioned between the plurality of emitter layers120and the substrate110, but does not exist between the plurality of BSF layers172and the substrate110and on exposed portions of the substrate110. Similar toFIG. 6, the rear passivation layer1922has a thickness not to prevent the movement of charges moving to the emitter layers120. Thereby, an amount of the recombination and/or disappearance of charges on an interface between the emitter layers120and the substrate110is reduced to increase an amount of charges moving to each emitter layer120.

The rear passivation layer1922and the BSF layers172include a plurality of crystal lumps1812aand1812bwhich grown to polycrystals. At this time, as described referring toFIGS. 1 and 2, crystallinity of the rear passivation layer1922is equal to or less than about 10% and crystallinity of the BSF layers142is equal to or less than about 30%.

In the solar cell13shown inFIG. 8, unlike the solar cell12shown inFIG. 7, the rear passivation layer1923is positioned between the plurality of BSF layers172and the substrate110. The rear passivation layer1923also has a thickness not to prevent the movement of charges moving to the BSF layers170. Thereby, an amount of the recombination and/or disappearance of charges on an interface between the BSF layers172and the substrate110is reduced to increase an amount of charges moving to each BSF layer172.

The rear passivation layer1923and the emitter layers120have crystal lumps1813aand1813bwhich are grown to polycrystals. At this time, as described referring toFIGS. 1 and 2, each of the emitter layers120has crystallinity equal to or less than of about 10%. However, since the BSF layers172are positioned on the rear passivation layer1923and each of the BSF layers172have the crystallinity more than the crystallinity of the front passivation layer191and each emitter layer120described based onFIG. 5, the rear passivation layer1923underlying the BSF layers172has crystallinity equal to or less than about 30%.

In the solar cells14and15shown inFIGS. 9 and 10, respectively, the rear passivation layers1924and1925exist between the substrate110and the plurality of emitter layers120and between the substrate110and the plurality of BSF layers172. The rear passivation layers1924and1925also have thicknesses not to prevent the movement of charges moving to the emitter layers120and the BSF layers170, respectively. Thereby, an amount of the recombination and/or disappearance of charges on interfaces between the emitter layers120and the substrate110and between the BSF layers172and the substrate110is reduced to increase an amount of charges moving to each of the emitter layers120and the BSF layers172.

The rear passivation layers1924and1925ofFIGS. 9 and 10have a plurality of crystal lumps1814,1815aand1815bthat are grown to polycrystals, respectively, but the rear passivation layers1924and1925have different crystallinity from each other.

That is, inFIG. 9, the rear passivation layer1924positioned under the emitter layers120and the rear passivation layer1924positioned under the BSF layers172have the same crystallinity as each other, and, for example, have crystallinity equal to or less than about 10%. In this case, the rear passivation layer1924is formed on the entire rear surface of the substrate110and etched to remove portions of the rear passivation layer1924. The emitter layers120and the BSF layers172are formed on the remaining portions of the rear passivation1924. Since the rear passivation layer1924underlying the emitter layers120and the BSF layers172is formed at the same time, the rear passivation layer1924have the same crystallinity.

However, the solar cell15shown inFIG. 10, the rear passivation layer1925aunderlying the emitter layers120and the rear passivation layer1925bunderlying the BSF layers120have different crystallinity from each other.

For example, the rear passivation layer1925aunderlying the emitter layers120has crystallinity of equal to or less than about 10% and the rear passivation layer1925bunderlying the BSF layers172has crystallinity equal to or less than about 30%. At this time, the rear passivation layer1925aand the rear passivation layer1925aare separately formed, and then the emitter layers120and the BSF layers172are formed on the rear passivation layers1925aand1925b, respectively. Thereby, the rear passivation layer1925ahas the crystallinity of about 10% or less than due to the influence of the emitter layers120positioned thereon and the rear passivation layer1925bhas the crystallinity of about 30% or less than due to the influence of the BSF layers172positioned thereon.

Accordingly, because a loss of carriers resulting from the crystal lumps1811,1812a,1812b,1813a,1814,1815aand1815bis reduced by controlling the crystallinity of each of the rear passivation layers1921-1925, the efficiency of the solar cells11-15is improved.

A solar cell according to another embodiment of the invention is described below with reference toFIGS. 11 and 12.

FIG. 11is a partial perspective view of a solar cell according to another embodiment of the invention.FIG. 12is a cross-sectional view taken along the line XII-XII ofFIG. 11. In the following explanations, structural elements having the same functions and structures as those illustrated inFIGS. 1 and 2are designated by the same reference numerals, and a further description may be briefly made or may be entirely omitted.

As shown inFIGS. 11 and 12, a solar cell1aincludes a substrate110formed of crystalline silicon, a front passivation layer191on a front surface of the substrate110, an emitter layer120aon the front passivation layer191, a transparent conductive layer161on the emitter layer120a, a plurality of first electrodes141aon the transparent conductive layer161, at least one electrode current collector1411that is positioned on the transparent conductive layer161and extend in a direction crossing the front electrodes141a, a rear passivation layer192aon a rear surface of the substrate110, a back surface field (BSF) layer172aon the rear passivation layer192a, a conductive layer162on the BSF layer172a, and a second electrode142aon the conductive layer162.

In the solar cell1ashown inFIGS. 11 and 12, the emitter layer120athat is electrically connected to the substrate110and formed of amorphous silicon is formed substantially entirely on a front surface of the substrate110(i.e., a light incident surface of the solar cell1a) when compared with the solar cell1shown inFIGS. 1 and 2. Further, the emitter layer120ais positioned opposite the second electrode142aon the rear surface of the substrate110with the substrate110interposed between the emitter layer120aand the second electrode142a. Hence, the second electrode142ais formed substantially entirely on the rear surface of the substrate110, and also the BSF layer172abetween the substrate110and the second electrode142ais formed substantially entirely on the rear surface of the substrate110.

In the solar cell1a, because the front surface and the rear surface of the substrate110are textured unlike the solar cell1shown inFIGS. 1 and 2, a separate process for removing a texturing pattern on the rear surface of the substrate110is not necessary.

Further, the rear passivation layer192ais formed substantially entirely on the rear surface of the substrate110, i.e., between the substrate110and the BSF layer172a. Thus, carriers moving to the rear surface of the substrate110pass through the rear passivation layer192ato move to the BSF layer172a. A thickness of the rear passivation layer192amay be less than a thickness of the rear passivation layer192shown inFIGS. 1 and 2, so as to easily move the carriers. For example, the thickness of the rear passivation layer192amay be approximately 1 μm to 10 μm.

As described above, the solar cell1ashown inFIGS. 11 and 12further includes the transparent conductive layer161directly on the emitter layer120aand the conductive layer162between the BSF layer172aand the second electrode142a, unlike the solar cell1shown inFIGS. 1 and 2. Hence, the plurality of first electrodes141aare positioned on a portion of the transparent conductive layer161to be electrically connected to the emitter layer120through the transparent conductive layer161, and the second electrode142ais electrically connected to the substrate110through the conductive layer162.

The transparent conductive layer161is a conductive layer based on an oxide layer and collects carriers (e.g., holes) moving to the emitter layer120ato transfer the carriers to the first electrodes141a. In addition, the transparent conductive layer161may serve as an anti-reflection layer. For the above-described operation, the transparent conductive layer161needs to have a high light transmittance capable of transmitting most of incident light and high electrical conductivity for a good flow of carriers. Thus, the transparent conductive layer161may be formed of material selected from the group consisting of indium tin oxide (ITO), tin-based oxide (e.g., SnO2), AgO, ZnO—Ga2O3 (or Al2O3), fluorine tin oxide (FTO), and a combination thereof. Other materials may be used.

The at least one electrode current collector1411is positioned at the same level as the first electrodes141aand is electrically connected to the first electrodes141a. The at least one electrode current collector1411collects carriers received from the first electrodes141ato output the carriers to an external device. In this embodiment, the conductive layer161, the first electrode141aand the electrode current collector1411form a front electrode portion or a first electrode portion.

The conductive layer162increases an adhesive strength between the BSF layer172aformed of silicon and the second electrode142aformed of a conductive material containing a metal component to increase a carrier transfer rate from the BSF layer172ato the second electrode142a. Further, the conductive layer162again reflects light passing through the substrate110from the substrate110to improve the efficiency of the solar cell1a. The conductive layer162may be formed of a transparent conductive material, such as ITO and ZnO. Other materials may be used. In this embodiment, the conductive layer162and the second electrode142aform a rear electrode portion or a second electrode portion.

The emitter layer120aformed of amorphous silicon and the rear passivation layer192a, each of which adjoins the substrate110formed of crystalline silicon, include epitaxial grown crystal lumps185and186each including polycrystals in the same manner asFIGS. 1 to 5, respectively.

Crystallinity of each of the emitter layer120aand the rear passivation layer192ais equal to or less than about 10% in the same manner as the crystal lumps181and184. Hence, a loss of carriers resulting from the crystal lumps185and186is reduced, and thus the efficiency of the solar cell1ais improved.

The embodiments of the invention may be applied to other types of solar cells as well as the above-described type solar cells. For example, the embodiments of the invention may be applied to a thin film solar cell in which a substrate is formed of a transparent material, such as glass, and a semiconductor material as a thin film is formed on the substrate.

The embodiments of the invention include ones having non-amorphous substrate, a first intrinsic semiconductor on the non-amorphous substrate, a second intrinsic semiconductor on an opposite side of the non-amorphous substrate from the first intrinsic amorphous semiconductor. One or both of the first intrinsic semiconductor and the second intrinsic semiconductor contains a crystal lump, or at least one portion that is crystalline and another portion that is amorphous. The crystallinity of one or both of the first intrinsic semiconductor and the second intrinsic semiconductor may be equal to or less than 30%. An emitter layer or a BSF layer may be formed on one of the first intrinsic semiconductor and the second intrinsic semiconductor or on respective first intrinsic semiconductor and the second intrinsic semiconductor. A crystallinity of the one or both of the first intrinsic semiconductor and the second intrinsic semiconductor varies based on whether how the emitter layer or the BSF layer are formed thereon.

As described above, in the solar cell according the embodiments of the invention, when crystal lumps are grown in amorphous silicon using crystalline silicon as a seed layer, a loss of carriers resulting from the crystal lumps is minimized by controlling crystallinity of amorphous silicon at an optimum value. Accordingly, the efficiency of the solar cell is improved.

In embodiments of the invention, reference to front or back, with respect to electrode, a surface of the substrate, or others is not limiting. For example, such a reference is for convenience of description since front or back is easily understood as examples of first or second of the electrode, the surface of the substrate or others.