Device for synchronous DC-DC conversion and synchronous DC-DC converter

A DC-DC converter transforms a DC input voltage to generate a DC output voltage by complementary switching control of a main switching transistor and a synchronous rectifying transistor. The DC-DC converter includes a soft-start circuit configured to generate a soft-start voltage rising from an initial voltage at start-up of the DC-DC converter; and a control circuit configured to control switching of the main switching transistor and the synchronous rectifying transistor based on the soft-start voltage to perform soft start of the DC-DC converter. The control circuit brings both of the main switching transistor and the synchronous rectifying transistor to an off state while the soft-start voltage is lower than the DC output voltage.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Japanese Patent Application No. 2010-233406 filed on Oct. 18, 2010, the disclosure of which including the specification, the drawings, and the claims is hereby incorporated by reference in its entirety.

BACKGROUND

The present disclosure relates to switching DC-DC converters supplying DC voltages to various electronic devices, and more particularly to start-up characteristics of DC-DC converters including synchronous rectifier circuits.

Switching DC-DC converters are used as power supply circuits of numerous electronic devices due to their high-efficiency power conversion characteristics. In general, DC-DC converters convert a DC input voltage to high frequency AC power by switching operation of a main switching transistor, apply the converted power to an inductor, rectify a voltage induced to the inductor by a rectifying means, smooth the induced voltage with an output capacitor, and output the smoothed voltage as a DC output voltage. The DC output voltage of a switching DC-DC converter increases with an increase in a duty ratio, which is a ratio of on-time to a switching period, of the main switching transistor. The control circuit detects a DC output voltage, and adjusts the duty ratio to stabilize the DC output voltage at a target voltage.

When a diode is used as a rectifying means, forward voltage drop causes power loss. Some synchronous rectifier circuits achieve high efficiency with reduced forward voltage drop of the diode by using a transistor such as a MOSFET as a rectifying means similar to the main switching transistor, and turning on the transistor during an off period of the main switching transistor, or at occurrence of a forward voltage during an off period. Such DC-DC converters have often a function called “soft start” of gradually increasing the duty ratio at start-up or gradually increasing a target value of the DC output voltage from 0 V to a target value in normal operation to reduce rapid rising of the output voltage at the start-up and inrush currents occurring accordingly.

In some synchronous rectifier DC-DC converters, a synchronous rectifying transistor is fixed to an off state at start-up. (See, for example, Japanese Patent Publication No. 2003-70238 and Japanese Patent Publication No. H11-220874.) Japanese Patent Publication No. 2003-70238 teaches reducing an overcurrent caused by discharging a residual voltage at an output via the synchronous rectifying transistor, when a voltage remains at the output at start-up in a charger in which a power supply such as a battery is coupled to an output of a DC-DC converter. Even if an overcurrent does not flow, a voltage remaining at the output at the start-up is advantageous in handling the problem that a DC output voltage drops at least once, since the synchronous rectifying transistor allows a current for discharging an output to flow. Japanese Patent Publication No. H11-220874 teaches that an inductor current flows in one direction toward an output at start-up, thereby reducing output oscillation at the start of the oscillation.

SUMMARY

When a synchronous rectifying transistor is off during the almost entire start-up time from power-on until an output voltage is stabilized, and the output voltage reaches a target value in an, e.g., unloaded state, there is the problem that overshoot occurring in the output voltage is not discharged and an overvoltage condition continues. Furthermore, the main purpose of soft start is to reduce rapid rising of an output voltage and an input inrush current occurring accordingly. When there is a voltage remaining at the output, the time for reaching the target value is clearly shortened. However, another problem is that the output voltage does not reach the target value until the time set by the soft start, regardless of the existence of the voltage remaining at the output.

In order to solve the problem, the present disclosure is advantageous in smoothly starting up a synchronous rectifier DC-DC converter having a soft-start function, regardless of the existence of a voltage remaining at an output.

An example DC-DC converter of the present disclosure transforms a DC input voltage to generate a DC output voltage by complementary switching control of a main switching transistor and a synchronous rectifying transistor. The DC-DC converter includes a soft-start circuit configured to generate a soft-start voltage rising from an initial voltage at start-up of the DC-DC converter; and a control circuit configured to control switching of the main switching transistor and the synchronous rectifying transistor based on the soft-start voltage to perform soft-start of the DC-DC converter. The control circuit brings both of the main switching transistor and the synchronous rectifying transistor to an off state, while the soft-start voltage is lower than the DC output voltage.

As such, the main switching transistor and the synchronous rectifying transistor are both in an off state, while the soft-start voltage is lower than the DC output voltage at the start-up of the DC-DC converter. Thus, when a voltage remains in the DC output voltage, the DC output voltage can be stabilized at the target voltage without discharging the residual voltage. Furthermore, when the DC output voltage reaches the target voltage, the synchronous rectifying transistor is in normal operation. Thus, the DC output voltage can be rapidly converged to the target voltage, even if output overshoot caused by unloaded start-up etc. or output oscillation in accordance with the output overshoot occurs.

Specifically, the control circuit includes an error amplifier configured to amplify an error between the DC output voltage and lower one of the soft-start voltage or a target voltage of the DC output voltage, a PWM circuit configured to generate a drive pulse having a duty ratio corresponding to an output of the error amplifier, a comparator configured to compare the soft-start voltage to the DC output voltage, and a logic circuit configured to perform logic operation of the drive pulse and an output signal of the comparator when an enable signal is active, and to generate a first control signal for controlling the main switching transistor and a second control signal for controlling the synchronous rectifying transistor. The logic circuit brings the first and second control signals to a logic level at which the main switching transistor and the synchronous rectifying transistor are both in an off state, when the output signal of the comparator is at a logic level indicating that the soft-start voltage is lower than the DC output voltage.

Alternatively, specifically, after the soft-start voltage has reached a target voltage of the DC output voltage, the soft-start circuit holds the soft-start voltage at the target voltage. The control circuit includes an error amplifier configured to amplify an error between the soft-start voltage and the DC output voltage, a PWM circuit configured to generate a drive pulse having a duty ratio corresponding to an output of the error amplifier, a comparator configured to compare the soft-start voltage to the DC output voltage, and a logic circuit configured to perform logic operation of the drive pulse and an output signal of the comparator, and to generate a first control signal for controlling the main switching transistor and a second control signal for controlling the synchronous rectifying transistor. The logic circuit brings the first and second control signals to a logic level at which the main switching transistor and the synchronous rectifying transistor are both in an off state, when the output signal of the comparator is at a logic level indicating that the soft-start voltage is lower than the DC output voltage.

Preferably, the control circuit controls switching of the main switching transistor, while holding the synchronous rectifying transistor in the off state, since the soft-start voltage becomes higher than the DC output voltage until the DC output voltage reaches a predetermined voltage lower than the target voltage. This smoothly raises the DC output voltage in a condition where the duty ratio is so small to control on-time of the main switching transistor.

Specifically, the DC-DC converter further includes a second comparator configured to compare the DC output voltage to a predetermined voltage lower than the target voltage. The logic circuit changes a logic level of the first control signal in accordance with the drive pulse, while holding the second control signal at a logic level at which the synchronous rectifying transistor is in an off state, when the output signal of the comparator is at a logic level indicating that the soft-start voltage is higher than the DC output voltage, and when an output signal of the second comparator is at a logic level indicating that the DC output voltage is lower than the predetermined voltage.

Preferably, the soft-start circuit raises the soft-start voltage with a steeper slope than that after the soft-start voltage becomes higher than the DC output voltage, while the soft-start voltage is lower than the DC output voltage. This shortens start-up time of the DC-DC converter without damaging the advantages of the soft-start function such as reduction in inrush currents.

DETAILED DESCRIPTION

First Embodiment

FIG. 1illustrates a circuit configuration of a DC-DC converter according to a first embodiment. A main switching transistor2and a synchronous rectifying transistor3are coupled in series between a DC input voltage V1and a ground. The main switching transistor2may be a p-channel MOSFET, and the synchronous rectifying transistor3may be an n-channel MOSFET. A first end of an inductor4is coupled at a connecting point of the main switching transistor2and the synchronous rectifying transistor3. An output capacitor5is coupled between a second end of the inductor4and a ground.

With this configuration, complementary switching control of the main switching transistor2and the synchronous rectifying transistor3is performed, thereby applying a high frequency pulse voltage with a wave height Vi to the first end of the inductor4. The high frequency pulse voltage is equalized by an LC filter including the inductor4and the output capacitor5and is output as a DC output voltage Vo. Where the duty ratio of the main switching transistor2is δ, Vo=δ×Vi is obtained. A control circuit10acontrols the duty ratio so that Vo stabilizes at a target voltage, and controls the main switching transistor2and the synchronous rectifying transistor3.

In the control circuit10a, Vo is coupled to an inverting input terminal of an error amplifier11a, and a soft-start voltage Vs output from a soft-start circuit20aand Vr1which is a target voltage of Vo are coupled to two non-inverting input terminals of the error amplifier11a. As will be described later, Vs is a voltage which rises from an initial voltage (e.g., a ground level) at start-up of the DC-DC converter. The error amplifier11aamplifies an error between Vo and lower one of Vs and Vr1, and outputs an error signal Ve. A PWM circuit12generates a drive pulse Vd having a duty ratio corresponding to Ve. Specifically, the duty ratio δ of Vd increases with an increase in Ve, and decreases with a decrease in Ve. Vo is coupled to an inverting input terminal of a comparator13. Vs is coupled to a non-inverting input terminal of the comparator13. The comparator13compares Vs to Vo, and outputs a determination signal Vx as a comparison result. Note that the comparator13preferably has an offset voltage to bring Vx to an L level where Vo is higher than Vs by a small value or more. Vo is coupled to a non-inverting input terminal of a comparator14. A predetermined voltage Vr2, which is lower than Vr1, is coupled to an inverting input terminal of the comparator14. The comparator14compares Vo to Vr2, and outputs a determination signal Vy as a comparison result.

When an enable signal EN is active (e.g., at an H level), a logic circuit15performs logic operation of Vd, Vx, and Vy, and generates control signals VH and VL for controlling switching of the main switching transistor2and the synchronous rectifying transistor3, respectively. For example, the main switching transistor2is in an on state when VH is at an L level, and is in an off state when VH is at an H level. The synchronous rectifying transistor3is in an on state when VL is at an H level, and is in an off state when VL is at an L level. Drive circuits16aand16bamplify power of VH and VL, respectively, and outputs a drive signal Vgh for driving the main switching transistor2and a drive signal Vg1for driving the synchronous rectifying transistor3so that the main switching transistor2and the synchronous rectifying transistor3are not in an on state at the same time.

The logic circuit15specifically operates as follows. When Vx is at a logic level (e.g. an L level) indicating that Vs is lower than Vo, the logic circuit15brings VH and VL to a logic level (e.g., VH to an H level, and VL to an L level) at which the main switching transistor2and the synchronous rectifying transistor3are both in an off state. Furthermore, when Vx is at a logic level (e.g. an H level) indicating that Vs is higher than Vo, and Vy is at a logic level (e.g. an L level) indicating that Vo is lower than Vr2, the logic circuit15changes the logic level of VH in accordance with Vd, while maintaining VL at a logic level (e.g. an L level) at which the synchronous rectifying transistor3is in an off state. Such logic operation is implemented variously.FIG. 2illustrates an example configuration of the logic circuit15. A NAND gate151outputs a result of NAND operation of EN, Vx, and Vd as VH. An AND gate152outputs a result of AND operation of inversion of EN, Vx, Vy, and Vd as VL.

Referring back toFIG. 1, the soft-start circuit20aoutputs Vs. When EN becomes an H level, the soft-start circuit20astarts the operation and Vs starts to rise from the ground level.FIG. 3illustrates an example configuration of the soft-start circuit20a. When EN is at an H level, a constant current source21outputs a constant current. A capacitor22is coupled between the constant current source21and a ground.

Vs may rise stepwise.FIG. 4illustrates another example configuration of the soft-start circuit20a. When EN becomes an H level, a counter circuit24starts count operation. The counter circuit24is, for example, a 5-bit counter, and outputs signals a, b, c, d, and e, which control constant current sources21a,21b,21c,21d, and21e, respectively. When the signals a-e are at an H level, the constant current sources21a-21eoutput constant currents, respectively. Note that the current ratio of each of the constant current sources21a-21eis set to power of two. A capacitor22′ is coupled to the constant current sources21a-21ein common. A resistive element25is coupled to the capacitor22′ in parallel.FIG. 5is a timing chart of the soft-start circuit20aofFIG. 4. Each time when a logic output value of a counter circuit24is incremented, the total current of the constant current sources21a-21eincreases by unit current I, and voltage drop of the resistive element25, i.e., soft-start voltage Vs increases by R×I. Note that R is a resistance value of a resistive element.

The capacitor22′ is provided to mitigate a stepwise increase in Vs to smooth a slope of Vs, when the total current of the constant current sources21a-21eincreases, but may be omitted.

Then, operation of the DC-DC converter according to this embodiment at start-up will be described.

Case 1: Where Vo is at a ground level

FIG. 6is a timing chart where Vo is at a ground level. Until time t0, EN is at an L level, and Vo is 0 V. Vs is 0V, since the capacitor22is short-circuited by the switch circuit23. Ve is initialized to a lower limit. Since Vo=0 V, Vx is at an H level, and Vy is at an L level. VH is at an H level, and VL is at an L level. The main switching transistor2and the synchronous rectifying transistor3are both in an off state.

When EN becomes an H level at time t0, the switch circuit23becomes non-conductive, and charge of the capacitor22starts to raise Vs. With the rise of Vs, Ve also rises, and the PWM circuit12outputs Vd. At this time, Vy is at an L level, and VL is thus at an L level. While the synchronous rectifying transistor3remains in an off state, only the main switching transistor2starts switching operation, and Vo follows Vs and rises. The synchronous rectifying transistor3is in an off state for the following reasons. The duty ratio is so small to control Vo which is a low voltage directly after start-up, and thus on-time control of the main switching transistor2is difficult. When the synchronous rectifying transistor3operates, on-time of the synchronous rectifying transistor3is long to discharge the output capacitor5too much so that Vo follows Vs, rises less smoothly, and oscillates. This condition continues until time t1when Vo reaches Vr2. Vr2is set so high to sufficiently control on-time of the main switching transistor2, and to control Vo even when discharge of the output capacitor5by the synchronous rectifying transistor3is deducted.

When Vo reaches Vr2at time t1, Vy becomes an H level, VL becomes a pulse output, and the synchronous rectifying transistor3starts switching operation. Vs continues to rise, and complementary switching control of the main switching transistor2and the synchronous rectifying transistor3is performed in accordance with Ve, thereby allowing Vo to follow Vs and rise.

When Vs and Vo reach Vr1at time t2, a non-inverting input of the error amplifier11ais changed to Vr1. That is, the target value of Vo is changed from Vs to Vr1. However, Vo becomes higher than Vr1due to delay in the error amplifier11aand the PWM circuit12. When, the synchronous rectifying transistor3is fixed to an off state as is conventionally done, Vo remains in an overvoltage condition in an unloaded state or in a light-loaded state close to the unloaded state. By contrast, in this embodiment, the synchronous rectifying transistor3discharges the output capacitor5, thereby rapidly reducing the overshoot voltage to stabilize Vo at Vr1.

Case 2: Where a low voltage remains in Vo.

FIG. 7is a timing chart where a low voltage remains in Vo. Until time t0, EN is at an L level, and a voltage higher than the ground level and lower than Vr2remains in Vo. Vs is 0V, since the capacitor22is short-circuited by the switch circuit23. Ve is initialized to a lower limit. Since Vo>Vs, Vx is at an L level. Since Vo<Vr2, Vy is at an L level. VH is at an H level, and VL is at an L level. The main switching transistor2and the synchronous rectifying transistor3are both in an off state.

When EN becomes an H level at time t0, the switch circuit23becomes non-conductive, and charge of the capacitor22starts to raise Vs. However, a low voltage remains in Vo, and thus, Vx remains at an L level, VH remains at an H level, and VL remains at an L level. That is, the main switching transistor2and the synchronous rectifying transistor3are both in an off state. This condition continues until time t1when Vs becomes higher than Vo.

When Vs becomes higher than Vo at time t1, Vx becomes an H level, and VH becomes a pulse output. On the other hand, since Vo<Vr2, Vy remains at an L level, and VL remains at an L level. Therefore, the synchronous rectifying transistor3remains in an off state, only the main switching transistor2starts switching operation, and Vo follows Vs and rises.

When Vo reaches Vr2at time t2, Vy becomes an H level, VL becomes pulse output, and the synchronous rectifying transistor3also starts switching operation. Vs continues to rise, and complementary switching control of the main switching transistor2and the synchronous rectifying transistor3is performed in accordance with Ve, thereby allowing Vo to follow Vs and rise. The operation after that, i.e., after Vs and Vo reach Vr1at time t3is as described above.

Case 3: Where a high voltage remains in Vo.

FIG. 8is a timing chart where a high voltage remains in Vo. Until time t0, EN is at an L level, and a voltage higher than Vr2remains in Vo. Vs is 0V, since the capacitor22is short-circuited by the switch circuit23. Ve is initialized to a lower limit. Since Vo>Vs, Vx is at an L level. Since Vo>Vr2, Vy is at an H level. VH is at an H level, and VL is at an L level. The main switching transistor2and the synchronous rectifying transistor3are both in an off state.

When EN becomes an H level at time t0, the switch circuit23becomes non-conductive, charge of the capacitor22starts to raise Vs. However, since a high voltage remains in Vo, Vx remains at an L level, VH remains at an H level, and VL remains at an L level. That is, the main switching transistor2and the synchronous rectifying transistor3are both in an off state. This condition continues until time t1when Vs becomes higher than Vo.

When Vs becomes higher than Vo at time t1, Vx becomes an H level, and VH and VL are both pulse outputs. As a result, complementary switching control of the main switching transistor2and the synchronous rectifying transistor3is performed in accordance with Ve, thereby allowing Vo to follow Vs and rise. The operation after that, i.e., after Vs and Vo reach Vr1at time t2is as described above.

As described above, according to this embodiment, when a voltage remains in a DC output voltage at start-up, switching control of a synchronous rectifying transistor is stopped to raise the DC output voltage to a target voltage without discharging a residual voltage. When the DC output voltage reaches the target voltage, the DC output voltage can be rapidly converged to the target voltage, even if output overshoot caused by unloaded start-up etc. or output oscillation in accordance with the output overshoot occurs, since a synchronous rectifying transistor operates.

Second Embodiment

FIG. 9illustrates a circuit configuration of a DC-DC converter according to the second embodiment. The DC-DC converter according to this embodiment includes a soft-start circuit20bhaving a different configuration from that of the first embodiment. The differences from the first embodiment will be described below.

In the first embodiment, even when a high voltage remains in Vo at start-up of the DC-DC converter, the main switching transistor2and the synchronous rectifying transistor3are both in an off state until Vs becomes higher than Vo after rising from 0 V (seeFIG. 8).

Thus, when Vs has a gentle rising slope, start-up time may become longer. Therefore, while Vs is lower than Vo, the soft-start circuit20braises Vs with a steeper slope than that after Vs becomes higher than Vo.

FIG. 10illustrates an example configuration of the soft-start circuit20b. The soft-start circuit20bis similar to the soft-start circuit20aofFIG. 3, but a second constant current source21′ and an inverter circuit26are added. The inverter circuit26outputs logical inversion of Vx. The second constant current source21′ is controlled by an output of the inverter circuit26. Specifically, Vx is at an L level, and the second constant current source21′ supplies a current to the capacitor22.

FIG. 11is a timing chart where a high voltage remains in Vo. While Vx is at an L level, Vs rises with a steeper slope than that after Vx becomes an H level. Thus, as compared to the timing chart ofFIG. 8, the period from the time when EN becomes an H level to the time when Vs becomes higher than Vo is shortened.

As described above, according to this embodiment, when a voltage remains in a DC output voltage, start-up time of the DC-DC converter is shortened while achieving the intended objective of soft start such as reduction in an inrush current at the start-up.

Note that, although it is not shown in the figure, the soft-start circuit20aofFIG. 4also changes Vs as shown inFIG. 11by reducing the output period of the counter circuit24while Vx is at an L level as compared to that while Vx is at an H level.

Third Embodiment

FIG. 12illustrates a configuration of a DC-DC converter according to a third embodiment. The DC-DC converter according to this embodiment includes a control circuit10band a soft-start circuit20cwhich have different configurations from those in the first and second embodiments. The differences from the first and second embodiments will be described below.

The control circuit10bincludes a conventional 2-input error amplifier11bin place of the error amplifier11aof the first and second embodiments. Vo is coupled to an inverting input terminal of the error amplifier11b. Vs is coupled to a non-inverting input terminal of the error amplifier11b. The error amplifier11bamplifies an error between Vs and Vo, and outputs an error signal Ve. Other configurations are similar to those in the first and second embodiments.

Similar to the soft-start circuits20aand20b, the soft-start circuit20craises Vs from a ground level at start-up of the DC-DC converter. In addition, the soft-start circuit20chas the function of holding Vs at Vr1after Vs reaches Vr1.FIG. 13illustrates an example configuration of the soft-start circuit20c. A resistor ladder circuit27is coupled between Vr1and a ground.

FIG. 14is a timing chart of the soft-start circuit20cofFIG. 13. While EN is at an L level, only S1is at an H level, and Vs is 0 V. When EN becomes an H level, S2, S3, . . . , are sequentially output. Furthermore, when Vx is at an L level, a one-shot pulse with a pulse width, which is shorter than that when Vx is at an H level, is output. This raises Vs with a relatively steep slope while Vx is at an L level. When an output signal of the switch control circuit29is changed, the capacitor22′ mitigates a stepwise increase in Vs to smooth the slope of Vs. Vs rises, and eventually, only Sn is held at an H level. As a result, Vs is hold at Vr1. Note that the capacitor22′ may be omitted.

As described above, according to this embodiment, a DC output voltage follows a soft-start voltage and is smoothly and rapidly stabilized at a target voltage, regardless of whether or not a voltage remains in a DC output voltage at start-up of a DC-DC converter, and even in an unloaded or light-loaded condition.

While buck converters have been described as various embodiments of the present disclosure, the present disclosure is not limited thereto. The present disclosure is also applicable to boost converters and buck-boost converters including a synchronous rectifying transistor.