Wideband reconfigurable impedance matching network

Embodiments relate to a transformer-based impedance matching network that may dynamically change its characteristic impedance by engaging different inductor branches on a primary side and optionally, on the secondary side. A primary side transformer circuit includes a primary inductor (311) and secondary inductor (321) configured to provide impedance matching over a first frequency band. One or more additional inductor branches (314A, 314B, are switchably coupled to either or both of the primary and secondary inductors to modify the impedance matching characteristics over additional operating frequencies. One or more LC filter branches (321, 322, 326, 327, 336, 330) can be included at the output of the secondary side to filter harmonic frequencies in each of the operating frequency bands.

BACKGROUND

Embodiments of the present invention relate generally to wireless communications, and more particularly, but not limited to, communication circuits and a transformer based impedance matching network and power amplifier for a transmitter.

Mismatches can occur at interfaces between various equipment e.g. transmitter, cable and antenna and when signal reflection occurs due to impedance mismatch between the signal source and the antenna, reflected standing waves are produced in the transmission line wasting transmission power. Therefore, impedance matching networks are implemented to reduce reflected waves and increase power consumption efficiency as much as possible.

Low power consuming transceivers are important for mobile devices and wireless nodes such as those used for the internet-of-things (IoT). Mobile wireless devices are inherently limited by size in form and by their respective power consumption from available sources. Two of the largest power consumers in mobile transceivers are oscillators and amplifiers in transmit chains. As modern wireless devices incorporate an ever increasing number of frequency bands, preferably by a single chip radio, conventional designs require multiple amplifier chains to cover the wide target frequency range. Multiple chains amplifier chains plus their respective impedance matching networks have conventionally been used, which leads to significant consumption in chip area and power consumption.

Accordingly, there is a constant effort to increase efficiencies in mobile devices, particularly in transmit chain(s), to extend battery life and mobile operation of these devices. Certain embodiments of the present invention enable such efforts via transmitter (TX) architectures and methods for low power radios including transmit chains with a configurable transformer-based impedance matching network.

DETAILED DESCRIPTION

In communications, and other electronic devices, it is generally desirable to match a power/signal source, e.g., a power amplifier (PA), impedance (ZS) with a load, e.g., an antenna, impedance (ZL), to avoid reflection and loss between the source and load. Referring toFIG. 1, an example impedance matching network100, in a potentially conventional radio frequency (RF) application, may use a transformer-based approach for impedance matching between the source and load. Transformers offer a nearly ideal solution for making one impedance look like another. Transformers match only the “real” part of the impedance. If there is a large amount of reactance in the load, a transformer will not eliminate these reactive components. In fact, a transformer may exaggerate the reactive portion of the load impedance. The reactive components then result in power that is reflected. Transformers have difficulties at microwave frequencies, but provide wider bandwidths than L-C matching circuits. Advantages of using transformers for impedance matching including: a relatively wide bandwidth, e.g., exceeding 1000 MHz; excellent amplitude and phase balance; and higher return loss (lower VSWR) at the primary side.

Impedance (Z) is defined as the total opposition of a circuit to the flow of an alternating current (AC) at a given frequency, and is represented as a complex quantity in an impedance vector having a real part, resistance (R), and an imaginary part, reactance (X), expressed using the rectangular coordinate form: Z=R+jX or Z=√R2+X2. Here, reactance X may be one or both of inductive reactance (XL), and/or capacitive reactance (XC), and X=XL−XC, which, respectively, are (ideally) calculated as: XL=ω*L=2π*f*L and/or XC=1/(ω*C)=1/(2π*f*C).

In an LC circuit, when the reactance magnitudes are equal, i.e., XL=XC, at a particular frequency, the circuit “resonates.” A series-connected LC circuit operating at resonant frequency has a net reactance of zero, behaving as a short circuit, whereas a parallel-connected LC circuit at resonant frequency has an infinite net reactance and behaves as open circuit.

In transformer-based matching network100, a simple relationship of transformer turns/windings ratio (N) is proportionate to the turns (NP) of the transformer primary inductor110and the number of turns (NS) of the transformer secondary inductor120, or N=NP:NS. In one example, a simple impedance relationship may then be expressed as ZS/ZP=(NS/NP)*2, or NS/NP=√(ZS/ZP), which at resonant frequency, becomes simply a resistance value and easily designed to match the source and load resistances at the desired operating frequency.

RF and/or other high frequency applications utilizing signals with a wavelength (λ, where λ=c/f) shorter than the length of a conduit the signal passes through, e.g., coaxial cable, strip line, microstrip circuits, waveguides, etc., transmission line impedance matching theory is used because the phase/complex portion of the signal becomes critical in matching impedance and reducing SWR. For example, and refraining from a full tutorial, in transmission line impedance matching, a matching network transmission line may be characterized as a network of resistors, inductors and capacitors having a generalized characteristic impedance Z0=√(R+jωL/G+jωC), where ω is the angular frequency (or 2π*frequency in Hz), and per unit length, R=resistance, G=conductance, L=inductance and C=capacitance. Accordingly, as one can see fromFIG. 1, matching network100requires secondary main inductor (Lsm)120and capacitance128selected to match the real and complex portions of impedance between source load140to effectively impedance match. It is noted that this generalized discussion omits reflectance (Γ) calculations of the transmission line itself.

Additionally, matching network100may include an electrostatic discharge (ESD) component130, such as a spiral inductor, to prevent damage to the matching network from static charge. Transformers may often be used as an ESD protection element130in addition to impedance matching components of the network100, as during an ESD event, the inductor becomes the path through which the ESD current shunts to ground due to the frequency of the ESD being much lower than the operating frequency of the general RF circuit.

Thus in transmission line impedance matching, resonant circuits with primary inductor110and capacitors108of the signal source, are impedance matched/tuned to the frequency band of desired operation (FO), e.g., tuned to the center frequency, in a particular TX chain.

According to various embodiments, in order to increase the bandwidth of a common transformer based matching network like shown inFIG. 1, switches and additional inductors may be included to enable a multiband and more wideband operation through re-configuration. The center frequency of the matching network is primarily determined by the input side in-series capacitance C and the transformers primary side inductance L1. Thus at minimum, only the primary side could include switchable inductor branches to dynamically alter the impedance characteristics.

Referring toFIG. 2and others, in various embodiments of the present invention, the frequency bandwidth of a transformer-based impedance matching network may be variably configured to match transmissions for multiple frequency bands by including at least one additional inductor, switchable either in series or in parallel to a primary main inductor210(Lpm), to tune impedance matching200to the center frequency of an additional operating frequency other than the tuned matching of base configuration with just primary and secondary main inductors210,220(Lpm and Lsm). Utilizing switches210and212, the additional inductor(s) may be energized or de-energized to effect impedance matching by altering the mutual inductance coupling to cause matching network200to match the source and load impedance when operating at the additional operating frequency desired.

In some embodiments, a transformer-based matching network200may include at least one additional primary inductor branch214and switch212to modify the impedance of the network. However, preferably, at least one additional secondary inductor branch224is also included and engaged by a respective switch222to tune matching network200to one or more additional operating frequencies. In some embodiments, where a differential input signal is received from the source such as a power amplifier, the additional primary inductor branch may include two switches212to input the differential signal to additional primary inductor214in a balanced fashion. By contrast, since the output to load240is a single output signal, only one switch214is needed to engage additional secondary inductor224for impedance matching at an additional frequency band. In this embodiment, the additional switchable inductor branches214,224are configured in parallel to the respective primary and secondary inductors210,220.

Referring toFIG. 3, an alternate embodiment of a matching network300is shown. Here, the at least one additional primary inductor branch314may utilize two inductors314A,314B, preferably of the same value, and an NMOS switch S1between these two inductors. This arrangement enables inductors314A and3148to be energized and keep the differential input signals balanced. In one embodiment, a center-tap315of the main inductor is DC biased at a voltage between a supply voltage (VDD) and ground, e.g., VDD/2. A logic control bit may be used to apply the bias voltage to the relevant switch (S1

In some embodiments, matching network300includes at least one switchable secondary inductor branch324configured in parallel with a secondary side main inductor circuit320. Secondary inductor branch324may be switched to dynamically adapt the mutual inductance of the primary and secondary sides of transformer-based impedance matching circuit300and thus change its impedance matching characteristics. In preferred embodiments, secondary inductor branch(es)324are switchable in coordination with primary switchable inductor branch(es)314, although the embodiments are in no way so limited.

In this embodiment, the switchable secondary inductor branch324may include one inductor325and an NMOS switch326to dynamically engage inductor325, altering the mutual inductance of circuit300. Preferably, secondary inductor branch324includes a matching capacitor327in parallel similar to the main secondary coil circuit320, i.e., inductor321and capacitor322. Although shown inFIG. 3on an opposite side, switch326may be disposed between inductor325and a respective ground. According to certain inventive embodiments, at least one inductor filter branch330is arranged in parallel with secondary inductor circuit320and secondary branch(es)324. Filter branch circuit330preferably includes an inductor335in series with a capacitor337to form a harmonic filter at a secondary side output. Each filter branch330is not required to be switchable as are the primary and secondary branches314,324, though preferably, a filter branch configuration is included for each frequency of operation.

FIG. 3also shows the biasing scheme for the switches according to various embodiments, where both NMOS or PMOS FETs could be used. For NMOS type transistors the “on” state, a switch bit at1would set to VDD and turn on the transistor. In an “off” state the gate is pulled to VSS and the drain and source terminals are biased to VDD. For a PMOS the biasing scheme can be applied vice versa.

Referring toFIG. 4, a method400of dynamically adapting a transformer-based impedance matching network may generally include: determining410a frequency band for transmission (FT); if420the frequency band FTis associated with (˜) the base impedance configuration Z0, the matching network is unaltered425and the harmonic filter associated with the transmit frequency band FTis used445. If420, however, the impedance of the matching network is other than a main or base configuration of the transformer-based impedance matching network, the appropriate matching impedance ZM:Nor, the inductance Lm:Nnecessary for transmission, is determined430. This may be done simply by a look up table corresponding to the transmit frequency. Alternatively, it may be calculated. Once the primary Lsm+Lp1. . . LpN and/or secondary configuration Lsm+Ls1. . . LsM is known to match at the transmit frequency FT, the appropriate primary and secondary (if any) inductor branches, are energized435by applying an appropriate voltage to the relevant switches S1, S2. . . SN, and/or S1, S2. . . SM to energize the respective primary or secondary additional inductor branches. In some embodiments, this is done by a control bit.

In some embodiments, at least two or more additional inductor branches are energized435, including an additional primary side inductor branch and an additional secondary side inductor branch, to dynamically modify a mutual inductance of the transformer-based impedance matching network to impedance match at the second transmit frequency band; and notch filtering445harmonics of the second transmit frequency band at an output of the secondary side of the matching network until the transmission frequency FTchanges450.

In certain embodiments, the additional primary side inductor branch(es) are in parallel with a main primary inductor of the primary side, and the main primary inductor and additional primary side inductor branch(es) are coupled at each end, to a respective input of two differential source signal inputs via a series capacitor.

Utilizing features of the foregoing embodiments, a solution is provided that enables a matching network to dynamically increase the transmit frequency ranges which may be desired for wideband and multiband transmitter operation. That is, a configurable matching network is provided which may support two or more bands with very different center frequencies. For example, using the embodiments described herein, GSM frequencies of 850 and 900 MHz can be combined with 1800 and 1900 MHz very effectively on a single amplifier chain. Thus advantages of the inventive embodiments may result in significant reduction of on-chip surface area, and/or reduced power consumption since fewer amplifier chains are used to cover a large span in frequency ranges conventionally matched using a different matching network for each frequency band.

InFIG. 5, the bandwidth of a transformer-based matching network500, includes additional in-parallel inductors to enable a multiband and more wideband operation through a set of reconfigurable switches coupling the additional in-parallel inductors. In this and other embodiments, a center frequency of the matching network is primarily determined by the differential input side in-series capacitance C1and the transformers main primary side inductance Lpm, and the output side capacitance C2and main secondary side inductance Lsm.

With the introduction of at least one additional in-parallel inductor pair and switch branches510on the primary side and optionally, in-parallel inductor and switch branches520on the secondary side, the mutual inductance of a transformer-based matching network may be dynamically modified and multiband operation is achieved.FIG. 5shows an exemplary schematic of transformer-based matching network500having switchable circuit including S1. . . SN to energize additional parallel inductor pair branches510on the primary side. The primary side is connected to differential inputs from the source to the main primary inductor Lpm and additional primary inductors via switches (S1, S2. . . SN). Differential input capacitors C1are coupled in series with the primary side circuit, are chosen to resonate on the fundamental of the lower frequency band to be operated.

1 to M additional secondary parallel inductor branches520may include a single inductor in parallel with a respective capacitor and are coupled at one end to a secondary side main inductor Lsm output and at ground on an opposite end. Depending on the state of the 1 to N switches in primary side and 1 to M switches in secondary side, a number of the 1 to N parallel primary inductor pair branches510and equivalent number of 1 to M parallel secondary inductor branches520are activated, which effectively decreases both the primary inductance and secondary inductance. Thus, the resonance frequency is shifted up and the amount depends on the circuit elements chosen, as well as how many branches are used in various configurations.

Preferably, for the primary side inductor pair branches510, two inductors as a pair are identical to each other. Each of the two inductors have one terminal connected to the Lpm and another terminal connected to the NMOS switch S1-SN. In preferred embodiments, these two inductors have a same value and are symmetric in the physical layout. On the primary side, the signal are in differential mode and have a symmetric impedance from the inductor pair in each branch. For the secondary side inductance branches520are coupled to a single-ended output (with the opposite to ground) and thus symmetric impedance is not a concern. As can be seen inFIG. 6, the parallel inductors can be winding laterally outside in lower part of the matching network strip layout. Matching network may include 1 to K inductor windings Lh1. . . LhK, to form harmonic filters branches530to notch out different harmonics with the respective series capacitors having different values suitably selected for resonating at the different operating frequencies/frequency bands.

As shown, a center tap of the primary side main inductor Lpm provides a DC bias in-between the supply (VDD) and ground, e.g., VDD/2. The channel of switches SWp1-SWpN in all the primary side branches510are all DC biased at VDD/2, via the Lpm, Lp1A-LpNA and Lp1B-LpNB metal windings. If any of the primary side branches510switch control is logic 1, the gate of the NMOS is VDD, the switch is in an “on” state and the branch inductor pair is energized. The energized primary branch520reduces the primary side inductance. If any of the primary side branches switch control is logic 0, the gate of the NMOS is ground, the switch is in an “off” state and the branch inductor pair520is not energized and thus has no effects on the primary side inductance Lpm.

To enable high output power, the secondary side voltage swing may be made larger than primary side voltage swing. For example, the secondary side switches (SWs1, SWs2, . . . , SWsM) have source terminals constantly tied to ground (no swings). If any of the secondary side branch switch controls is logic 0, the corresponding NMOS switches (SWs) gate is 0. The override voltage of the switch is at 0, and is independent of the large voltage swing of the output signal. At this voltage, the secondary branch switch has good isolation, acts as an open circuit, and remains in an “off” state. If any of the secondary side branch520switch controls is logic 1, the gate of the corresponding NMOS switches becomes VDD and the override voltage is VDD, at which the switch has good conductivity, like a short circuit. The branch inductance is electrically in-parallel with the secondary side main inductor and thus reduces secondary side total inductance.

In certain implementations, as best seen in microstrip circuit600ofFIG. 6, the two inductors (Lp1A and Lp1B) in each primary side branch may have windings laterally disposed inside the primary side main inductor (Lpm) to maintain symmetry and the NMOS switch in each branch is located in between the two same value inductors Lp1A-Lp1B thru LpNA-LpNB of each branch (note3are shown). The inductors, Ls1. . . Ls3, in each switchable secondary side parallel branch may preferably be windings laterally disposed outside the secondary main inductor Lsm winding and kept on a lower side. Further, the inductors Lh1. . . Lh3in each secondary side harmonic filter branch are arranged windings laterally outside of the secondary main inductor windings and kept in an upper side of circuit600. Utilizing compact windings of the primary side inductance branches, the secondary side inductance branches, and the harmonic filter inductance branches with the primary side and secondary side main inductors respectively, significantly improves the layout are efficiency for the on-chip matching.

In the layout, each of the branch inductor is winding with the current flow direction opposite with the secondary main inductor to enhance the inductance value to each other. Each of the harmonic inductor is winding with the current flow direction same as the secondary main inductor to have small value to resonance with the capacitance (Ch1, Ch2, . . . , CHK) at much higher frequency for harmonics. Compact windings of the primary side inductance branches, the secondary side inductance branches, and the harmonic filter inductance branches with the primary side and secondary side main inductors significantly improves the layout are efficiency for the on-chip matching.

FIGS. 7.1 and 7.2show another possible embodiment for a reconfigurable wideband matching network700. In this embodiment, additional primary inductors L3and L4are switchably coupled to the main primary inductor L1in a series configuration instead of parallel. Port1and2are the differential mode primary inputs. Port6is the secondary single-ended output put with port7as the secondary ground. The winding L7from port6to port8serves as harmonic notch filter (resonance at harmonic frequency with in-series C1). The metal winding between port1and3corresponds to the L3inFIG. 5, and the metal winding between port2and4corresponds to the L4inFIG. 5. If the control is set to logic high (voltage potential is higher than NMOS threshold voltage), the NMOS (N1and N2) switch gates are biased at high voltage potential. The inverter outputs logic low and the primary side center tap (Port5) is biased as low voltage potential. Port1,2,3and4have same DC bias as port5(coupled through primary side metal windings). They are biased at low DC voltage. The N1and N2are closed (gate—channel cross voltage is positive and higher than threshold voltage). The L3and L4are shunted out from the primary side. The matching network primary side is resonant at high frequency band (resonance by C/2 and L1).

If the control is set to logic low, similarly, the N MOS (N1and N2) gates are biased at low voltage. The port1,2,3and4are biased at high voltage. N1and N2are open. The L3and L4are in-series with L1. The matching network resonant at low frequency band (resonance by C2/2 and L1+L3+L4). The L3and L4can be multiple turn windings and cross-coupled with each other to improve the space efficiency.

Embodiments described herein may be implemented into a system using any suitably configured hardware and/or software.FIG. 8illustrates, for one embodiment, example components of an electronic device800. In embodiments, the electronic device800may be, implement, be incorporated into, or otherwise be a part of a user equipment (UE). In some embodiments, the electronic device800may include application circuitry802, baseband circuitry804, Radio Frequency (RF) circuitry806, front-end module (FEM) circuitry808and one or more antennas810, coupled together at least as shown. Electronic device800may include interconnects (shown by arrows and dark lines) such as PCIe, Advanced eXtensible Interconnect (AXI) or open core protocol (OCP) or the like to exchange information and/or signals between a host, various peripherals or sub-peripherals, referred to as components. And each component using the interconnect, must have an interface805to do so.

The application circuitry802may include one or more application processors or processing units. For example, the application circuitry802may include circuitry such as, but not limited to, one or more single-core or multi-core processors802a. The processor(s)802amay include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.). The processors802amay be coupled with and/or may include computer-readable media802b(also referred to as “CRM802b”, “memory802b”, “storage802b”, or “memory/storage802b”) and may be configured to execute instructions stored in the CRM802bto enable various applications and/or operating systems to run on the system and/or enable features of the inventive embodiments to be enabled.

The baseband circuitry804may include circuitry such as, but not limited to, one or more single-core or multi-core processors to arrange, configure, process, generate, transmit, receive, or otherwise determine time differences of carrier aggregation signals as described in various embodiments herein. The baseband circuitry804may include one or more baseband processors and/or control logic to process baseband signals received from a receive signal path of the RF circuitry806via an interconnect interface805and to generate baseband signals for a transmit signal path of the RF circuitry806. Baseband circuity804may also interface805via an interconnect, with the application circuitry802for generation and processing of the baseband signals and for controlling operations of the RF circuitry806. For example, in some embodiments, the baseband circuitry804may include a third generation (3G) baseband processor804a, a fourth generation (4G) baseband processor804b, a fifth generation (5G)/NR baseband processor804c, and/or other baseband processor(s)804dfor other existing generations, generations in development or to be developed in the future (e.g., 6G, etc.). The baseband processing circuit804(e.g., one or more of baseband processors804a-d) may handle various radio control functions that enable communication with one or more radio networks via the RF circuitry806. The radio control functions may include, but are not limited to, signal modulation/demodulation, encoding/decoding, radio frequency shifting, as well as measuring time difference between carrier aggregation signals as discussed previously. In some embodiments, modulation/demodulation circuitry of the baseband circuitry804may include Fast-Fourier Transform (FFT), precoding, and/or constellation mapping/demapping functionality. In some embodiments, encoding/decoding circuitry of the baseband circuitry804may include convolution, tail-biting convolution, turbo, Viterbi, and/or Low Density Parity Check (LDPC) encoder/decoder functionality. Embodiments of modulation/demodulation and encoder/decoder functionality are not limited to these examples and may include other suitable functionality in other embodiments.

In some embodiments, the baseband circuitry804may include elements of a protocol stack such as, for example, elements of an evolved universal terrestrial radio access network (E-UTRAN) protocol including, for example, physical (PHY), media access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), and/or radio resource control (RRC) elements. A central processing unit (CPU)804eof the baseband circuitry804may be configured to run elements of the protocol stack for signaling of the PHY, MAC, RLC, PDCP and/or RRC layers. In some embodiments, the baseband circuitry may include one or more digital signal processor(s) (DSP)804ffor audio processing. The DSP(s)804fmay include elements for compression/decompression and echo cancellation and may include other suitable processing elements in other embodiments. The baseband circuitry804may further include computer-readable media804g(also referred to as “CRM804g”, “memory804g”, or “storage804g”). The CRM804gmay be used to load and store data and/or instructions for operations performed by the processors of the baseband circuitry804. CRM804gfor one embodiment may include any combination of suitable volatile memory and/or non-volatile memory. The CRM804gmay include any combination of various levels of memory/storage including, but not limited to, read-only memory (ROM) having embedded software instructions (e.g., firmware), random access memory (e.g., dynamic random access memory (DRAM)), cache, buffers, etc.). The CRM804gmay be shared among the various processors or dedicated to particular processors. Components of the baseband circuitry804may be suitably combined in a single chip, a single chipset, or disposed on a same circuit board in some embodiments. In some embodiments, some or all of the constituent components of the baseband circuitry804and the application circuitry802may be implemented together, such as, for example, on a system on a chip (SOC).

In some embodiments, the baseband circuitry804may provide for communication compatible with one or more radio technologies. For example, in some embodiments, the baseband circuitry804may support communication with an E-UTRAN, NR and/or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), a wireless personal area network (WPAN). Embodiments in which the baseband circuitry804is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

RF circuitry806may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium. In various embodiments, the RF circuitry806may include switches, filters, amplifiers, etc., to facilitate the communication with the wireless network. RF circuitry806may include a receive signal path that may include circuitry to down-convert RF signals received from the FEM circuitry808and provide baseband signals to the baseband circuitry104. RF circuitry806may also include a transmit signal path that may include circuitry to up-convert baseband signals provided by the baseband circuitry804and provide RF output signals to the FEM circuitry808for transmission.

In some embodiments, the mixer circuitry806aof the transmit signal path may be configured to up-convert input baseband signals via interconnect and based on the synthesized frequency provided by the synthesizer circuitry806dto generate RF output signals for the FEM circuitry808. The baseband signals may be provided by the baseband circuitry804and may be filtered by filter circuitry806c. The filter circuitry806cmay include a low-pass filter (LPF), although the scope of the embodiments is not limited in this respect.

In some embodiments, the output baseband signals and the input baseband signals may be analog baseband signals which are digitally converted to provide digital data to processors via interface805to through the interconnect, although the scope of the embodiments is not limited in this respect. In some alternate embodiments, the output baseband signals and the input baseband signals may be digital baseband signals. In these alternate embodiments, the RF circuitry806may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry and the baseband circuitry804may include an RF interface805, such as an analog or digital baseband interface, to communicate with the RF circuitry806.

In some embodiments, the synthesizer circuitry806dmay be a fractional-N synthesizer or a fractional N/N+1 synthesizer, although the scope of the embodiments is not limited in this respect, as other types of frequency synthesizers may be suitable. For example, synthesizer circuitry806dmay be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider. The synthesizer circuitry806dmay be configured to synthesize an output frequency for use by the mixer circuitry806aof the RF circuitry806based on a frequency input and a divider control input. In some embodiments, the synthesizer circuitry806dmay be a fractional N/N+1 synthesizer.

In some embodiments, frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a requirement. Divider control input may be provided by either the baseband circuitry804or the application circuitry802depending on the desired output frequency. In some embodiments, a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the application circuitry802.

FEM circuitry808may include a receive signal path that may include circuitry configured to operate on RF signals received from one or more antennas810, amplify the received signals and provide the amplified versions of the received signals to the RF circuitry806for further processing. FEM circuitry808may also include a transmit signal path that may include circuitry configured to amplify signals for transmission provided by the RF circuitry806for transmission by one or more of the one or more antennas810. In some embodiments, the FEM circuitry808may include a TX/RX switch to switch between transmit mode and receive mode operation. The FEM circuitry808may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry may include a low-noise amplifier (LNA) to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry806). The transmit signal path of the FEM circuitry808may include a power amplifier (PA) to amplify input RF signals (e.g., provided by RF circuitry806), and one or more filters to generate RF signals for subsequent transmission (e.g., by one or more of the one or more antennas810).

In some embodiments, the electronic device800may include additional elements such as, for example, a display, a camera, one or more sensors, and/or interface805to interconnect (for example, input/output (I/O) interfaces or buses). In embodiments where the electronic device is implemented to provide networking functions, the electronic device800may include network interface circuitry. The network interface circuitry may be one or more computer hardware components that connect electronic device800to one or more network elements, such as one or more servers within a core network via one or more wired connections. To this end, the network interface circuitry may include one or more dedicated processors and/or field programmable gate arrays (FPGAs) to communicate using one or more network communications protocols such as X2 application protocol (AP), S1 AP, Stream Control Transmission Protocol (SCTP), Ethernet, Point-to-Point (PPP), Fiber Distributed Data Interface (FDDI), and/or any other suitable network communications protocols.

EXAMPLE EMBODIMENTS

According to a First Example embodiment, an apparatus is defined including an impedance matching network to match a differential signal source having a source impedance (ZS), with a load having a load impedance (ZL). The impedance matching network including: a differential input to couple with said differential signal source; a transformer impedance matching circuit coupled with, and in parallel to, the differential input circuit, the transformer impedance matching circuit including a primary main inductor having a first mutual inductance coupling with a secondary main inductor and configured to match said load impedance and said source impedance over a first operating frequency range; an LC harmonic filter circuit coupled with, and in parallel to, the secondary main inductor and having components selected to resonate at a frequency within the first operating frequency range; and at least one additional inductor branch switchably coupled to said primary and secondary main inductors, respectively, said additional inductor branches, when engaged, dynamically adapt the transformer impedance matching circuit to have a second mutual inductance to match the load impedance and the source impedance over a second operating frequency range.

In a Second Example embodiment, the First Example is further defined by at least one additional LC filter branch switchably coupled to, and in parallel with, the LC harmonic filter circuit, the at least one additional LC filter branch selected to resonate at a frequency within the second operating frequency range;

A Third Example further defines the First wherein the at least one additional inductor branch coupled to the differential input circuit and the primary main inductor comprises a single inductor in parallel to the primary main inductor and switchably connected by two field-effect transistor (FET) switches, one FET switch on each side of the single parallel inductor, to engage said single parallel inductor in a balanced fashion via the differential input circuit.

A Fourth Example may expand on the First Example wherein the at least one additional inductor branch coupled to the primary main inductor comprises two same value inductors in parallel with the primary main inductor and switchably connected by a single switch disposed between the two same value inductors and biased from a center tap of the primary main inductor.

In a Fifth Example, any of the First thru Fourth Examples are furthered, wherein switchably connected comprises connected via a metal oxide semiconductor field effect transistor (MOSFET) using N-type or P-type material.

In a Sixth Example, the First through Fourth Examples may include the impedance matching network is formed as a microstrip circuit.

According to a Seventh Example embodiment the Second through Fourth Examples are furthered by the apparatus comprises two additional inductor branches and two additional LC branches, and configured to operate in the first, second and a third operating frequency range.

An Eighth Example furthers the First in that the apparatus comprises an analog front end module including the impedance matching network.

In an Ninth Example, the Seventh Example further comprises a baseband processor coupled to the analog front end module and configured to control the impedance matching networks switching of the additional inductor branches.

A Tenth Example defines an apparatus including a transformer-based impedance matching network comprising: a primary side transformer circuit including a primary inductor configured to provide impedance matching over a first frequency band, and one or more additional primary inductor branches coupled to the primary inductor via one or more switches to dynamically adapt impedance matching for one or more additional frequency bands; a secondary side transformer circuit arranged to be inductively coupled to the primary side transformer circuit and including a secondary inductor configured to impedance matching over the first frequency band, and one or more additional secondary inductor branches coupled to the secondary inductor via one or more switches to dynamically adapt impedance matching for the one or more additional frequency bands; and an LC filter circuit coupled to an output of the secondary side transformer circuit and including an inductor and a capacitor in series and configured to notch-filter harmonic frequencies within the first frequency band, and one or more additional LC circuit branches coupled to the output via one or more switches to dynamically adapt the LC filter circuit to notch-filter different harmonic frequencies over the one or more additional frequency bands.

An Eleventh Example furthers the Tenth wherein the one or more additional primary inductor branches are in parallel to the primary inductor and each comprise two same value inductors and a corresponding switch between, to energize the two same value inductors in a balanced fashion.

In a Twelfth Example, the Tenth Example is further by the one or more additional primary inductor branches are mutually inductive to another and in series with the primary inductor.

According to a Thirteenth Example, the Tenth through Twelfth Examples are furthered in that there are two additional primary inductor branches, two additional secondary inductor branches and two additional LC circuit branches, to dynamically adapt impedance matching to a plurality of different frequency bands.

In a Fourteenth Example, the Thirteenth includes the transformer-based impedance matching network is configured as a microstrip circuit, and wherein the three different frequency bands

A Fifteenth Example furthers the Tenth through Twelfth Examples wherein the switches are metal oxide semiconductor field effect transistors (MOSFETs).

In a Sixteenth Example, the Fifteenth is furthered when the MOSFETs are N-type and biased on by a center tap voltage from the primary inductor.

In an Eighteenth Example, the computer readable tangible medium includes instructions that, when executed by a processor, cause the processor to adapt a transformer-based impedance matching network to match a differential source signal having an impedance ZS to a load having an impedance ZL over a plurality of operating frequencies by performing the steps of: determining a frequency (FT) of the differential source signal; and dynamically switching the matching network between one of a plurality of impedance matching configurations comprising: a base configuration including a main primary inductor inductively coupled to, a proximate and parallel located, main secondary inductor when the frequency FT is within a first operating frequency band; and a second configuration including the base configuration and an additional primary inductor branch, in parallel and coupled to, the main primary inductor when FT is within a second operating frequency band.

In a Nineteenth Example, the Seventeenth Example is further defined wherein the second configuration further comprises an additional secondary inductor branch comprising an inductor and a parallel capacitor, the additional secondary inductor branch coupled to an output of, and in parallel to, the main secondary inductor, and ground.

In a Twentieth Example, the Seventeenth is furthered by the plurality of impedance matching configurations further comprise: a third configuration including the second configuration, a second additional primary inductor branch, in parallel and coupled to, the additional primary inductor branch, and a second additional secondary inductor branch including an inductor and a parallel capacitor, the second additional secondary inductor branch coupled in parallel to the additional secondary inductor branch, the second additional inductor branches switchably engaged when the frequency FT is within a third operating frequency band.

In a Twenty-First Example, the Seventeenth through Nineteenth include, wherein the processor comprises a baseband processor and the matching network comprises at least part of an analog front end (AFE) module of a user equipment (UE).

In a Twenty-Second Example embodiment, the Seventeenth through Nineteenth are furthered by the matching network further including one or more filter branches in parallel with the secondary inductor branch, each comprising an inductor coupled to an output of the main secondary conductor in series with a capacitor coupled to ground, each filter branch selected to notch filter harmonics within one of first second or third operating frequency bands.

According to a Twenty-Third Example, the Seventeenth through Nineteenth are furthered by additional primary inductor branches each comprising two same value inductors symmetrically arranged in series, each one disposed on opposite sides of an NMOS switch.

In a Twenty-Fourth Example a communication device includes a transformer-based impedance matching network adapted to operate over three or more different frequency bands. The communication device comprises: a power amplifier circuit configured to provide a differential transmit signal over said least three different transmit frequency bands; one or more antennas to transmit and/or receive over the at least three different transmit frequency bands; and an impedance matching network coupling the power amplifier circuit to the one or more antennas, the matching network dynamically adaptable to impedance match over the three or more different frequency bands and comprising: a primary side inductor circuit having a main primary inductor and one or more additional primary inductor branches each including a switch to modify impedance of the matching network for a given operating frequency; a secondary side inductor circuit having a main secondary inductor and one or more additional secondary inductor branches each including a switch to modify impedance of the matching network for said given operating frequency; and a plurality of LC harmonic filter branches, one for each operating frequency.

In a Twenty-Fifth Example, the Twenty-Third is furthered by the matching network is implemented as a microstrip circuit.

According to a Twenty-Sixth Example embodiment, the Twenty-Third is furthered by each switch being an NMOS FET and wherein each additional primary inductor branch is parallel to the main primary inductor and comprises two same value inductors symmetrically disposed on opposite side of the switch,

A Twenty-Seven Example embodiment defines means for matching a differential source signal having an impedance ZSto a load having an impedance ZLover a plurality of operating frequencies including means for determining a frequency (FT) of the differential source signal; and means for dynamically switching the matching network between one of a plurality of impedance matching configurations including: a base configuration including a main primary inductor inductively coupled to, a proximate and parallel located, main secondary inductor when the frequency FT is within a first operating frequency band; and a second configuration including the base configuration and an additional primary inductor branch, in parallel and coupled to, the main primary inductor when FT is within a second operating frequency band.

A Twenty-Eighth Example includes a method for adapting a transformer-based impedance matching network to match a source impedance to a load impedance over a plurality of operating frequencies including: determining a frequency (FT) of the differential source signal; and dynamically switching the matching network between one of a plurality of impedance matching configurations comprising: a base configuration including a main primary inductor inductively coupled to, a proximate and parallel located, main secondary inductor when the frequency FTis within a first operating frequency band; and a second configuration including the base configuration and an additional primary inductor branch, in parallel and coupled to, the main primary inductor when FT is within a second operating frequency band.

The present disclosure has been described with reference to the attached drawing figures, with certain example terms and wherein like reference numerals are used to refer to like elements throughout. The illustrated structures, devices and methods are not intended to be drawn to scale, or as any specific circuit or any in any way other than as functional block diagrams to illustrate certain features, advantages and enabling disclosure of the inventive embodiments and their illustration and description is not intended to be limiting in any manner in respect to the appended claims that follow, with the exception of 35 USC 112, sixth paragraph, claims using the literal words “means for,” if present in a claim. As utilized herein, the terms “component,” “system,” “interface,” “logic,” “circuit,” “device,” and the like are intended only to refer to a basic functional entity such as hardware, processor designs, software (e.g., in execution), logic (circuits or programmable), firmware alone or in combination to suit the claimed functionalities. For example, a component, module, circuit, device or processing unit “configured to,” “adapted to” or “arranged to” may mean a microprocessor, a controller, a programmable logic array and/or a circuit coupled thereto or other logic processing device, and a method or process may mean instructions running on a processor, firmware programmed in a controller, an object, an executable, a program, a storage device including instructions to be executed, a computer, a tablet PC and/or a mobile phone with a processing device. By way of illustration, a process, logic, method or module can be any analog circuit, digital processing circuit or combination thereof. One or more circuits or modules can reside within a process, and a module can be localized as a physical circuit, a programmable array, a processor. Furthermore, elements, circuits, components, modules and processes/methods may be hardware or software, combined with a processor, executable from various computer readable storage media having executable instructions and/or data stored thereon. Those of ordinary skill in the art will recognize various ways to implement the logical descriptions of the appended claims and their interpretation should not be limited to any example or enabling description, depiction or layout described above, in the abstract or in the drawing figures.