Protection element and method of manufacture

An electrostatic discharge (“ESD”) protection circuit having dynamically configurable series-connected diodes and a method for manufacturing the ESD protection circuit. A doped region of P-type conductivity and a doped region of N-type conductivity are formed in an SOI layer of P-type conductivity, wherein the doped regions are laterally spaced apart by a portion of the SOI layer. At least one gate structure is formed on the SOI region that is between the N-type and P-type doped regions. During normal operation, a portion of the SOI region that is adjacent to and between the P-type and N-type doped regions is biased so that it becomes a region of N-type conductivity, thereby forming two series-connected diodes. During an ESD event, the bias is changed so that the region between the P-type and N-type doped regions becomes a region of P-type conductivity, thereby forming a single P-N junction diode.

FIELD OF THE INVENTION

The present invention relates, in general, to semiconductor components and, more particularly, to the protection of semiconductor components from transient electrical signals.

BACKGROUND OF THE INVENTION

Semiconductor component manufacturers typically include structures for protecting their devices against failure caused by large transient electrical stimuli. When the stimulus is an electrostatic discharge (“ESD”) event, manufacturers generally incorporate protection structures that account for failure mechanisms attributed to the Human Body Model (“HBM”) and to the Charged Device Model (“CDM”). The Human Body Model simulates electrostatic discharge from a human body to a semiconductor device that is sensitive to the discharge event. Here, charge accumulated on the human body discharges to the semiconductor device. The Charged Device Model simulates the discharge of charge accumulated on the semiconductor device itself during the assembly process. When these charged devices contact metal objects, a discharge event occurs which is short in duration accompanied by peak currents capable of exceeding ten amperes.

To protect against these events, semiconductor component manufacturers incorporate ESD protection structures into their components. They are coupled to input and output (“I/O”) pads of the semiconductor devices to prevent device failure due to positive and negative voltage excursions that may appear on the I/O pads. To provide maximal ESD protection, it is desirable to increase the discharge path for ESD induced current by making the ESD protection structures large. However, large ESD protection structures occupy large areas on the semiconductor substrate, which increases the costs associated with manufacturing the semiconductor component. In addition, making the ESD protection structures large increases the capacitance associated with the input and output pads to which they are coupled. In high frequency applications, increasing the capacitance of the ESD protection structure increases the Resistance-Capacitance (“RC”) time constant of the pin coupled to the bond pad, which makes the devices unacceptably slow.

Accordingly, it would be advantageous to have an ESD protection structure with reduced capacitance during normal operation and a method for lowering the capacitance of the ESD protection structure. It would be of further advantage for the method and ESD protection structure to be cost efficient.

SUMMARY OF THE INVENTION

The present invention satisfies the foregoing need by providing an ESD protection element with a dynamically adjustable number of series-connected diodes. In accordance with one aspect, the ESD protection element comprises a semiconductor-on-insulator substrate of a first conductivity type. A first doped region of the first conductivity type extends from a first portion of the major surface into the semiconductor-on-insulator substrate. A second doped region of a second conductivity type extends from a second portion of the major surface into the semiconductor-on-insulator substrate. The first and second doped regions are laterally spaced apart from each other by a substrate region. A first gate structure is asymmetrically positioned on the substrate region.

In accordance with another aspect, the present invention includes a method for manufacturing an ESD protection device in which a semiconductor-on-insulator substrate having a major surface is provided. The semiconductor-on-insulator substrate comprises a first layer of semiconductor material, a first layer of dielectric material disposed on the first layer of semiconductor material, and a second layer of semiconductor material disposed on the first layer of semiconductor material. The second layer of semiconductor material has a major surface, a first dopant concentration, and a first conductivity type. A first doped region of the first conductivity type and a second dopant concentration is formed in the second layer of semiconductor material. A second doped region of a second conductivity type and a third dopant concentration is formed in the second layer of semiconductor material, wherein the second doped region is laterally spaced apart from the first doped region by a portion of the second layer of semiconductor material. The portion of the second layer of semiconductor material has a first dopant concentration and a first conductivity type. At least one gate structure is formed on the second layer of semiconductor material such that the at least one gate structure is asymmetrically positioned over the portion of the second layer of semiconductor material of the first conductivity type and the first dopant concentration.

In accordance with yet another aspect, the present invention comprises a method for protecting a circuit or a circuit element during an electrostatic discharge event by configuring a semiconductor material to comprise at least two diodes coupled in series during a first operating mode, and configuring the semiconductor material to comprise one diode during a second operating mode.

DETAILED DESCRIPTION

Generally, the present invention provides a means for dynamically forming series-connected diodes, wherein the diodes are suitable for use in protecting circuits from damage caused by transient electrical signals such as, for example, an electrostatic discharge event. In accordance with one aspect, the present invention includes a diode structure formed from a Semiconductor-On-Insulator (“SOI”) substrate. The SOI substrate comprises an SOI layer having one of an initial dopant concentration or an intrinsic dopant concentration coupled to a layer of insulating material. In an embodiment in which the SOI layer is a P-type conductivity material, a region of the SOI layer is doped with an impurity material or dopant of P-type conductivity and another region of the SOI layer is doped with an impurity material of N-type conductivity. The regions of P-type conductivity and N-type conductivity are separated by a portion of the SOI layer having either the initial dopant concentration or the intrinsic dopant concentration. This semiconductor region is referred to as the diode multiplication region. One or more gate structures are asymmetrically positioned over the diode multiplication region. The gate structures are biased to either invert, enhance, or not affect the portions of the diode multiplication region underlying the gate structures. By changing the conductivity type of a portion of the diode multiplication region or leaving it unchanged, one or more additional series-connected diodes are formed in the diode multiplication region. The number of diodes can be selected using Equation 1 (Eqt. 1):
Number of diodes=(n/2)+1  Eqt. 1
where n is the number of gate structures formed over the diode multiplication region.

FIG. 1is a cross-sectional side view of a semiconductor component10comprising a gated lateral diode at an early stage of manufacture in accordance with an embodiment of the present invention. What is shown inFIG. 1is an SOI substrate12comprising a layer of insulating material18sandwiched between two layers of semiconductor material14and22. Preferably, semiconductor material14is monocrystalline silicon of P-type conductivity and a thickness ranging from approximately 500 micrometers to approximately 1,000 micrometers; insulating material18is oxide having a thickness ranging from approximately 1,000 Angstroms (Å) to approximately 2,000 Å; and semiconductor material22is monocrystalline silicon of P-type conductivity having a surface24and a thickness of less than approximately 750 Å so that it becomes fully depleted during an ESD event. Layer22is also referred to as a semiconductor-on-insulator layer or an SOI layer. Techniques for manufacturing SOI substrate12are known to those skilled in the art. It should be understood that the type of material, conductivity types, and thicknesses of semiconductor materials14and22and dielectric material18are not limitations of the present invention. Typically, silicon layer14provides structural support for substrate12whereas silicon layer22serves as an active layer. However, this is not a limitation of the present invention. For example, silicon layers14and22can serve as active layers or silicon layer22can serve as the active layer while silicon layer14provides structural support.

A layer of photoresist is formed on SOI layer22and patterned to form an implant block mask26that covers a portion of SOI layer22and leaves a portion of SOI layer22exposed. An impurity material of P-type conductivity such as, for example, boron, is implanted into the portions of SOI layer22unprotected by implant block mask26, i.e., the exposed portions of SOI layer22, to form a doped region28. By way of example, the P-type impurity material is implanted at a dose ranging from approximately 1×1013ions per square centimeter (ions/cm2) to approximately 5×1014ions/cm2and an implant energy ranging from approximately 15 kilo-electron Volts (keV) to approximately 30 keV. The implant is indicated by arrows29. It should be understood that the portions of SOI substrate12that do not underlie photoresist layer26are unprotected by photoresist layer26.

Referring now toFIG. 2, implant block mask26is removed using techniques known to those skilled in the art. Another layer of photoresist is formed on SOI layer22and patterned to form an implant block mask30that covers doped region28and a portion of SOI layer22adjacent doped region28, but leaves a portion of SOI layer22exposed. An impurity material of N-type conductivity such as, for example, phosphorus, is implanted into the portions of SOI layer22unprotected by implant block mask30, i.e., the exposed portions of SOI layer22, to form a doped region32. By way of example, the N-type impurity material is implanted at a dose ranging from approximately 1×1013ions/cm2to approximately 5×1014ions/cm2and an implant energy ranging from approximately 15 keV to approximately 30 keV. The implant is indicated by arrows33. Implant block mask30is removed.

Doped region32is laterally spaced apart from doped region28by a portion34of substrate region22. In accordance with one embodiment, portion34of substrate region22has the same conductivity type and same dopant concentration as SOI layer22before the formation of doped regions28and32. In accordance with another embodiment, portion34of substrate region22is intrinsic semiconductor material. Because additional diodes will be formed from portion34of substrate region22, it is also referred to as a diode multiplication region.

Referring now toFIG. 3, a layer of dielectric material38having a thickness ranging from approximately 15 Å to approximately 100 Å is formed on doped regions28and32and on diode multiplication region34. A portion of dielectric layer38serves as a gate dielectric material and may be formed using techniques known to those skilled in the art including thermal oxidation, chemical vapor deposition, and the like. A layer of polysilicon40having a thickness ranging from approximately 550 Å to approximately 2,000 Å is formed on dielectric layer38. A layer of photoresist is formed on polysilicon layer40and patterned to form an etch mask42. In accordance with one embodiment etch mask42is over a portion of diode multiplication region34that is adjacent to doped region28. In accordance with another embodiment, etch mask42is over a portion of diode multiplication region34that is adjacent to doped region32. Thus, etch mask42is asymmetrically positioned over diode multiplication region34, i.e., etch mask42is not centered or it is off-center over diode multiplication region34. Etch mask42protects the portions of polysilicon layer40and dielectric layer38over which it is positioned. In other words, the portions of polysilicon layer40and dielectric layer38that do not underlie etch mask42are not protected by etch mask42.

Referring now toFIG. 4, the unprotected portions of polysilicon layer40are etched using an etch chemistry that preferentially etches polysilicon and not the underlying dielectric material. By way of example, polysilicon layer40is etched using an anisotropic Reactive Ion Etch (“RIE”) and an etchant species that preferentially etches polysilicon. After removal of the exposed portions of polysilicon layer40, the etch chemistry is changed to anisotropically etch dielectric layer38. The anisotropic etching of dielectric layer38stops or terminates on doped regions28and32and on diode multiplication region34leaving a portion38A of dielectric layer38and a portion40A of polysilicon layer40. Portions38A and40A cooperate to form a gate structure50having sidewalls52and54. Portion38A serves as a gate dielectric and portion40A serves as a gate conductor. It should be understood that the type of etching is not a limitation of the present invention. For example, a wet etch rather than a dry etch can be used to etch polysilicon layer40and dielectric layer38. After formation of gate structure50, etch mask42is removed.

Still referring toFIG. 4, a layer of dielectric material58is formed on gate structure50, doped regions28and32, and on the exposed portion of diode multiplication region34. Suitable materials for dielectric layer58include oxide, nitride, dielectric materials having a low dielectric constant, and the like. By way of example, dielectric layer58is silicon dioxide deposited using a chemical vapor deposition technique. Preferably, silicon dioxide layer58has a thickness ranging from approximately 600 Å to approximately 1,500 Å.

Referring now toFIG. 5, silicon dioxide layer58is anisotropically etched to form spacers60and62adjacent sidewalls52and54, respectively. A layer of dielectric material64having a thickness ranging from approximately 5 Å to approximately 30 Å is formed on gate structure50, spacers60and62, doped regions28and32, and the exposed portion of diode multiplication region34. Suitable materials for dielectric layer64include silicon dioxide, silicon nitride, or the like. Dielectric layer64is planarized using a planarization technique such as, for example, chemical mechanical planarization, electropolishing, electrochemical polishing, chemical polishing, chemically enhanced planarization, and the like.

Still referring toFIG. 5, a layer of photoresist is formed on dielectric layer64and patterned to form an etch mask66. Etch mask66overlies spacer62and portions of diode multiplication region34and gate conductor40A. The exposed portions of dielectric layer64, i.e., the portions that are not under etch mask66, are unprotected by etch mask66.

Referring now toFIG. 6, the exposed portions of dielectric layer64are anisotropically etched to expose gate conductor40A and doped regions28and32. After anisotropically etching dielectric layer64, a portion64A remains over spacer62, diode multiplication region34, a portion of gate electrode40A, and a portion of doped region32. Portion64A prevents diode multiplication region34from becoming electrically shorted to doped region32during salicide formation which occurs in a subsequent processing step.

Referring now toFIG. 7, an optional wet etch is performed to remove any oxide from gate electrode40A and any oxide disposed on the exposed portions of doped regions28and32. A layer of refractory metal (not shown) is deposited on portion64A and the exposed portions of gate structure50and doped regions28and32. By way of example, the refractory metal layer is cobalt having a thickness ranging from approximately 50 Å to approximately 300 Å. The refractory metal is heated to a temperature ranging from approximately 600° C. to approximately 700° C. The heat treatment causes the cobalt to react with the silicon to form cobalt silicide (CoSi2) in all areas in which the cobalt is in contact with silicon. Thus, a cobalt silicide region80is formed from gate conductor40A, a cobalt silicide region82is formed from doped region28, and a cobalt silicide region84is formed from doped region32. The portions of the cobalt disposed on the non-silicon material, e.g., the cobalt disposed on portion64A, remain unreacted. The unreacted cobalt is removed using processes known to those skilled in the art. It should be understood that the type of silicide is not a limitation of the present invention. For example, other suitable silicides include titanium silicide (TiSi), platinum silicide (PtSi), nickel silicide (NiSi), and the like.

Still referring toFIG. 7, a layer of dielectric material86is formed on portion64A and on silicide regions80,82, and84. By way of example, dielectric material86is oxide having a thickness ranging from approximately 5,000 Å to approximately 15,000 Å. Dielectric material86is planarized using techniques known to those skilled in the art. A layer of photoresist is formed on dielectric layer86and patterned to form an etch mask87. In accordance with one embodiment etch mask87is over silicide regions80,82, and84. Etch mask87protects the portions of dielectric layer86over which it is positioned. In other words, the portions of dielectric layer87that do not underlie etch mask87are not protected by etch mask87. Openings are formed in dielectric layer86to expose portions of silicide regions80,82, and84. Using techniques known to those skilled in the art, electrical conductors or electrodes are formed which contact the exposed portions of silicide regions80,82, and84. Etch mask87is removed.

Referring now toFIG. 8, an electrically conductive material having a thickness ranging from approximately 50 Å to approximately 350 Å is formed on the portions of silicide layers80,82, and84exposed by the openings formed in dielectric layer86and on the remaining portion of dielectric layer86. The electrically conductive material serves as a barrier layer. By way of example, the barrier layer is a bilayer structure comprising a titanium contact layer having a titanium nitride layer formed thereon. Suitable techniques for forming the electrically conductive layer include Chemical Vapor Deposition (“CVD”), Plasma Enhanced Chemical Vapor Deposition (“PECVD”), Atomic Layer Deposition (“ALD”), or the like. Other suitable materials for the electrically conductive material include tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), a tantalum (Ta) and tantalum nitride (TaN) combination, tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), and refractory metal compounds such as refractory metal nitrides, refractory metal carbides, and refractory metal borides. It should be understood that the number of layers for the barrier layer is not a limitation of the present invention.

An electrically conductive material having a thickness ranging from approximately 4,000 Å to approximately 8,000 Å is formed on the barrier layer. By way of example, the electrically conductive material is titanium. Alternatively, the electrically conductive material may be copper, silver, aluminum, or the like. The electrically conductive material is planarized using, for example, a CMP technique having a high selectivity to dielectric layer86. Thus, the planarization stops on dielectric layer86. After planarization, portions88,89, and90of the barrier layer remain and portions91,92, and93of the electrically conductive material remain. Silicide layer82, barrier layer88, and electrically conductive material91cooperate to form an anode contact94. Silicide layer84, barrier layer90, and electrically conductive material93cooperate to form a cathode contact95. Silicide layer80, barrier layer89, and electrically conductive material92cooperate to form a gate electrode96.

FIG. 9is a cross-sectional side view of a dual-gated lateral diode100in accordance with another embodiment of the present invention. Dual-gated lateral diode100includes SOI substrate12having doped regions28and32laterally spaced apart by diode multiplication region34. Dual-gated lateral diode100also includes gate structure50and spacers60and62asymmetrically positioned over diode multiplication region34. In addition, dual-gated lateral diode100includes a second gate structure102comprising a gate dielectric material38B, a gate conductor40B, and a silicide layer120. Gate structure102has sidewalls104and106and spacers108and110adjacent sidewalls104and106, respectively. Like gate structure50, gate structure102is asymmetrically positioned on diode multiplication region34. However, gate structure102is laterally adjacent doped region32. Although gate structures50and102are laterally spaced apart, they are preferably close enough together to prevent salicide formation from a region112that is between gate structures50and102. In addition, the gate structures prevent impurity material from doping diode multiplication region34. Thus, gate structure102prevents doped region32from becoming electrically shorted to diode multiplication region34. Each gate structure is asymmetrically positioned on diode multiplication region34. However, it should be understood that the combination of gate structures50and102are preferably positioned such that the combination is symmetrically oriented over diode multiplication region34. Like gate structure50, gate structure102includes an electrically conductive material124disposed on a barrier layer122. Silicide layer120, barrier layer122, and electrically conductive material124cooperate to form a gate electrode126.

FIG. 10illustrates a cross-sectional side view of dual-gated lateral diode100at an earlier stage of manufacture than that shown inFIG. 9.FIG. 10is included to clarify how gate structure102may be formed. Rather than forming a single etch mask42(shown inFIG. 3), a pair of etch masks42and42A are formed from a photoresist layer. Gate structure102is formed using steps similar to those described with reference toFIGS. 4-8. However, a dielectric layer such as dielectric layer64and a protective structure such as structure64A are not formed because gate102serves as a protective structure.

FIG. 11is a cross-sectional side view of a multi-gated lateral diode150in accordance with another embodiment of the present invention. Multi-gated lateral diode150includes SOI substrate12having doped regions28and32laterally spaced apart by diode multiplication region34. Multi-gated lateral diode150also includes gate structures152,154,156and158positioned over diode multiplication region34. Each gate structure152,154,156, and158is asymmetrically positioned over diode multiplication region34. Like gate structures50and102, gate structures152,154,156, and158each include a gate dielectric material disposed on diode multiplication region34and a gate conductor disposed on the gate dielectric material. More particularly, gate structure152comprises a gate dielectric material38C, and a gate conductor40C, gate structure154comprises a gate dielectric38D and a gate conductor40D, gate structure156comprises a gate dielectric material38E and a gate conductor40E, and gate structure158comprises a gate dielectric material38F and a gate conductor40F. The dielectric material of gate dielectric material38C-38F are portions of dielectric layer38described with reference toFIG. 3and the material of gate conductors40C-40F are portions of polysilicon layer40described with reference toFIG. 3. Spacers184are adjacent gate structure152, spacers186are adjacent gate structure154, spacers188are adjacent gate structure156, and spacers190are adjacent gate structure158. A silicide layer166, a barrier layer167, and an electrically conductive material170cooperate to form a gate contact192to gate structure152; a silicide layer168, a barrier layer169, and an electrically conductive material170cooperate to form a gate contact194to gate structure154; a silicide layer174, a barrier layer176, and an electrically conductive material178cooperate to form a gate contact196to gate structure156; and a silicide layer180, a barrier layer182, and an electrically conductive material184cooperate to form a gate contact198to gate structure158. Like gate structures50and102, each gate structure152,154,156, and158is asymmetrically positioned on diode multiplication region34. Gate structures152,154,156, and158are laterally spaced apart from each other but are close enough to prevent salicide formation on or doping of substrate region34. Although each gate structure is asymmetrically positioned on diode multiplication region34, the combination of gate structures152,154,156, and158are preferably positioned symmetrically over diode multiplication region34, i.e., gate structures152and154are symmetrically positioned with respect to gate structures156and158.

FIG. 12illustrates a cross-sectional side view of multi-gated lateral diode150at an earlier stage of manufacture than that shown inFIG. 11.FIG. 12is included to clarify how gate structures152,154,156, and158may be formed. Rather than forming a single etch mask42(shown inFIG. 3), four etch masks42C,42D,42E, and42F are formed from a photoresist layer. Gate structures152,154,156, and158are formed using steps similar to those described with reference toFIGS. 4-8. However, a dielectric layer such as dielectric layer64and a protective structure such as structure64A are not formed because gate structures152,154,156, and158serve as protective structures.

FIG. 13is a circuit schematic200illustrating a triggering or biasing circuit202for controlling a gated diode such as, for example, dual-gated lateral diode100. More particularly, triggering circuit202has an output terminal204coupled to gate electrode96and an output terminal206coupled to gate electrode126of dual-gated lateral diode100.

In operation, triggering circuit202applies logic voltages to gate electrodes96and126to control the operating mode of dual-gated lateral diode100. In a normal operating mode (i.e., in the absence of a transient electrical signal such as an electrostatic discharge event), triggering circuit202biases dual-gated lateral diode100so that it is configured as two series-connected diodes. In this mode, triggering circuit202applies a logic high voltage to gate electrode96and a logic low voltage to gate electrode126. The logic high voltage applied to gate electrode96fully depletes the portion of diode multiplication region34that is between gate structure50and insulating layer18so that it becomes a region of N-type conductivity.

FIG. 14is a cross-sectional side view of dual-gated lateral diode100which is coupled to triggering circuit202and biased in a normal mode of operation. What is shown inFIG. 14is a cross-sectional side view of dual-gated lateral diode100biased to operate as two series-connected diodes, wherein the depleted or inverted portion of diode multiplication region34is identified by reference character34A and the undepleted portion of diode multiplication region34is identified by reference character34B. Doped region28which is a P-type conductivity region and portion34A of diode multiplication region34which is an N-type conductivity region form a diode208. Portion34B of diode multiplication region34which is a P-type conductivity region and doped region32which is an N-type conductivity region form a diode210. It should be understood thatFIG. 14is provided for the sake of clarity and that it represents dual-gated lateral diode100shown inFIG. 9under biasing conditions that forms series-connected diodes208and210.

When an ESD event occurs, triggering circuit202biases dual-gated lateral diode100so that it is configured as a single diode by applying a logic low voltage to gate electrodes96and126. Under these bias conditions regions28and34continue to be regions of P-type conductivity and region32continues to be a region of N-type conductivity, thereby forming a single P-N junction diode, i.e., portion34A continues to be P-type conductivity. It should be noted that a single P-N junction diode is also formed when triggering circuit202applies a logic high voltage to gate electrodes96and126. Alternatively, a single P-N junction diode is formed when triggering circuit202applies a logic low voltage to gate electrode96and a logic high voltage to gate electrode126. Preferably, triggering circuit202is hardwired to form sub-portion34A from portion34of region22for normal operation and to leave region34unaltered during an ESD event.

FIG. 15is a circuit schematic of an ESD protection circuit202in accordance with another embodiment of the present invention. What is shown inFIG. 15is dual-gated lateral diode100coupled to triggering circuit202. Triggering circuit202comprises three inverters252,254, and256, wherein each inverter comprises an N-channel Insulated Gate Field Effect Transistor (IGFET) coupled to a P-channel IGFET. More particularly, inverter252comprises an N-channel IGFET258having gate, source, and drain terminals and a P-channel IGFET260having gate, source, and drain terminals. The source terminal of N-channel IGFET258is coupled for receiving a source of operating potential VSSand the drain terminal is coupled to gate electrode96of dual-gated lateral diode100to form a node259. The source terminal of P-channel IGFET260is coupled for receiving a source of operating potential VDDand the drain terminal is coupled to the drain terminal of IGFET258and to gate electrode96of dual-gated lateral diode100at node259. The gate terminals of IGFETS258and260are coupled to each other and to gate electrode126of dual-gated lateral diode100to form a node261.

Inverter254comprises an N-channel IGFET262having gate, source, and drain terminals and a P-channel IGFET264having gate, source, and drain terminals. The source terminal of N-channel IGFET262is coupled for receiving source of operating potential VSSand the drain terminal is coupled to the gate electrodes of transistors258and260at node261. The source terminal of P-channel IGFET264is coupled for receiving a source of operating potential VDDand the drain terminal is coupled to the drain terminal of IGFET262and to the gate terminals of transistors258and260at node261. The gate terminals of IGFETS262and264are coupled to each other to form a node265.

Inverter256comprises an N-channel IGFET266having gate, source, and drain terminals and a P-channel IGFET268having gate, source, and drain terminals. The source terminal of N-channel IGFET266is coupled for receiving source of operating potential VSSand the drain terminal is coupled to the gate electrodes of transistors262and264at node265. The source terminal of P-channel IGFET268is coupled for receiving a source of operating potential VDDand the drain terminal is coupled to the drain terminal of IGFET266and to the gate terminals of transistors262and264at node265. The gate terminals of IGFETS266and268are coupled to each other to form a node269.

A Resistance-Capacitance (“RC”) network270comprising a resistor272and a capacitor274is coupled to the gate terminals of IGFETS266and268. More particularly, one terminal of resistor272is coupled for receiving source of operating potential VDDand the other terminal of resistor272is coupled to the gate terminals of IGFETS266and268at node269, and one terminal of capacitor274is coupled to resistor272and to the gate terminals of IGFETS266and268at node269and the other terminal of capacitor274is coupled for receiving source of operating potential VSS. By way of example, capacitor274is a transistor connected in a capacitor configuration. The time constant of RC network272is the product of the resistance value of resistor272and the capacitance value of capacitor274.

During normal operation, capacitor274is charged and the voltage appearing at node269is substantially equal to the voltage supplied by source of operating potential VDD. The voltage appearing at node265is substantially equal to the voltage supplied by source of operating potential VSS, the voltages appearing at node261and gate electrode126are substantially equal to the voltage supplied by source of operating potential VDD, and the voltages appearing at node259and gate electrode96are substantially equal to the voltage supplied by source of operating potential VDD. Accordingly, a logic high voltage appears on gate electrode96and a logic low voltage appears on gate electrode126and dual-gated diode100is configured as two series-connected diodes as shown inFIG. 14.

During an ESD event, capacitor274discharges thereby lowering the voltage appearing at node269so that it is substantially equal to the voltage supplied by source of operating potential VSS. The voltage appearing at node265is substantially equal to the voltage supplied by source of operating potential VDD, the voltages appearing at node261and gate electrode126are substantially equal to the voltage supplied by source of operating potential VSS, and the voltages appearing at node259and gate electrode96are substantially equal to the voltage supplied by source of operating potential VSS. Thus, dual-gated lateral diode100is configured as a single diode. Forming a single diode during and ESD event is advantageous because it has a lower “on” voltage than the series-connected diodes, which ensures that dual-gated lateral diode100turns on quickly during an ESD event to prevent damage to the circuitry on the semiconductor chip.

FIG. 16is a circuit schematic of an ESD protection circuit202in accordance with another embodiment of the present invention. What is shown inFIG. 16is an ESD protection network300comprising two dual-gated lateral diodes100A and100B coupled to insulated gate field effect transistors (“IGFETS”)304and306, to receiver and driver circuitry310of the chip, and to an I/O pad302. Dual-gated lateral diode100A has a cathode, an anode, a gate electrode96A and a gate electrode126A and dual-gated lateral diode100B has a cathode, an anode, a gate electrode96B and a gate electrode126B. It should be noted that each dual-gated lateral diode100A and100B is similar to dual-gated lateral diode100shown inFIG. 9; hence the letters “A” and “B” have been appended to reference characters100,126, and96to distinguish between the diodes and to show their similarity. For example, dual-gated lateral diode100has gate electrodes96and126, whereas dual-gated lateral diode100A has gate electrodes96A and126A and dual-gated lateral diode100B has gate electrodes96B and126B. Each IGFET304and306has a control electrode and a pair of current conducting electrodes.

The anode of dual-gated lateral diode100A is coupled for receiving source of operating potential VSSand the cathode of dual-gated lateral diode100A is coupled to the anode of dual-gated lateral diode100B. The cathode of dual-gated lateral diode100A and the anode of dual-gated lateral diode100B are coupled to an I/O pad302and to receiver and driver circuitry310. The cathode of dual-gated lateral diode100B is coupled for receiving a source of operating potential VDD. Control electrodes96A and96B are coupled for receiving source of operating potential VSS. Control electrodes126A and126B are coupled to a drain electrode of a P-channel IGFET304. A source electrode of P-channel IGFET304is coupled for receiving source of operating potential VDD. The gate electrode of P-channel IGFET304is coupled to a drain electrode of IGFET306. The source electrode of IGFET306is coupled for receiving source of operating potential VSSand a gate electrode of IGFET306is coupled for receiving source of operating potential VDD.

During normal operation, gate electrodes96A and96B are coupled for receiving a logic low voltage, e.g., source of operating potential VSS. Because the gate electrode of N-channel IGFET306is coupled for receiving source of operating potential VDDand the source electrode of N-channel IGFET306is coupled for receiving source of operating potential VSS, N-channel IGFET306is “on” and the voltage appearing at the drain electrode of N-channel IGFET306is substantially equal to a logic low voltage. Hence the voltage appearing at the gate electrode of P-channel IGFET304is substantially equal to a logic low voltage. Because, the source electrode of IGFET304is coupled for receiving source of operating potential VDD, the voltage appearing at gate electrodes126A and126B is at a logic high voltage level. Therefore, dual-gated lateral diodes100A and100B are each configured as two series-connected diodes.

During an ESD event, transistors304and306become non-conducting causing logic low voltages to appear at gate electrodes126A and126B and configuring each dual-gated lateral diode100A and100B as a single diode.

FIG. 17is a schematic diagram illustrating triggering or biasing circuit202for controlling a gated diode such as, for example, multi-gated lateral diode150. More particularly, triggering circuit202has an output terminal204coupled to gate electrode192and an output terminal206coupled to gate electrode198. Gate electrodes194and196of multi-gated lateral diode150are coupled for receiving sources of operating potential VDDand VSS, respectively. In other words, a logic high voltage is applied to gate electrode196and a logic low voltage is applied to gate electrode194.

FIG. 18is a cross-sectional side view of multi-gated lateral diode150which is coupled to triggering circuit202and biased in a normal mode of operation. The operation of multi-gated lateral diode is described with reference toFIGS. 17 and 18.

In operation, the logic low voltage applied to gate electrode196fully depletes or inverts the portion34E of diode multiplication region34that is between gate structure40E and insulating layer18. Thus, portion34E becomes a region of N-type conductivity semiconductor material. Because gate electrode194is biased with a logic low voltage level, portion34D of diode multiplication region34remains a semiconductor region of P-type conductivity.

Triggering circuit202applies logic voltages to gate electrodes192and198for controlling the operating mode of dual-gated lateral diode150. During a normal operating mode, triggering circuit202biases dual-gated lateral diode150so that it is configured as three series-connected diodes. In this mode, triggering circuit202applies a logic high voltage to gate electrode192and a logic low voltage to gate electrode198. The logic high voltage applied to gate electrode192fully depletes or inverts sub-portion34C of diode multiplication region34that is between gate structure192and insulating layer18so that it becomes a region of N-type conductivity. Because a logic low voltage level is applied to gate electrode198, sub-portion34F continues to be a region of P-type conductivity. Doped region28which is a P-type conductivity region and sub-portion34C which is an N-type conductivity region form a diode211. Sub-portion34D which is a P-type conductivity region and sub-portion34E which is an N-type conductivity region form a diode212. Sub-portion40F which is a P-type conductivity region and doped region32which is an N-type conductivity region form a diode214. It should be understood that sub-portions34C and34D are formed from a portion of substrate region22and sub-portions34E and34F are formed from another portion of substrate region22.

When an ESD event occurs, triggering circuit202biases multi-gated lateral diode150so that it is configured as a single diode. Preferably, triggering circuit202applies a logic low voltage to gate electrode192and a logic high voltage to gate electrode198. Under these bias conditions region28and sub-portions34C, and34D are regions of P-type conductivity region and sub-portions34E,34F, and region32are regions of N-type conductivity, thereby forming a single P-N junction diode.

It should be understood other biasing schemes may be used to form the series-connected diodes and the single P-N junction diode. For example, regions34D,34E, and34F may be biased with high voltages and region34C may be biased with a low voltage.

By now it should be appreciated that an ESD protection network having reduced capacitance and leakage current during normal operation and a method for forming series-connected diodes have been provided. One or more asymmetric gate structures are formed on a portion of an SOI layer that is between two doped regions. During normal operation, the gate structures are biased to invert or change the conductivity type of least one region in the SOI layer thereby forming an additional P-N junction region that serves as a diode. During an ESD event, the biasing is changed to switch the at least one region back to its original conductivity type. This reduces the number of diodes and enables the ESD protection network to more quickly provide protection against an ESD event. Thus, the method allows for dynamically changing the number of diodes coupled in series. It is advantageous to operate with one or more series-connected diodes during normal operation because the series-connected diodes increase the turn-on voltage for the diodes ensuring they do not turn on during normal operation. The series-connected diodes also decrease the capacitance and the leakage current of the diode network. When an ESD event occurs, decreasing the number of diodes also decreases the voltage needed to turn on the diode structure. An advantage of decreasing the capacitance of the gated diode ESD protection network is that it allows transmission of higher frequency signals through the I/O pads connected to the gated diode ESD protection network. Another advantage is that the decreased capacitance gives designers the option to make larger ESD protection devices.

Yet another advantage is that the number of diodes can be selected by selecting the number of gate structures and biasing the gate structures to form diodes in the diode multiplication region. In addition, the number of diodes is not a limitation of the present invention. For example, there can be eight diodes, ten diodes, twelve diodes, etc. Preferably, the total number of gate structures is an even number.