Memory device for reducing programming time

A non-volatile memory device includes: first and second planes each comprising a plurality of non-volatile memory cells; first and second buffer corresponding to the first and second planes, respectively; an input/output control unit configured to selectively control input/output paths of data stored in the first and second page buffers; a flash interface connected to the input/output control unit; and a host connected to the flash interface.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean Application No. 10-2009-0130727, filed on Dec. 24, 2009, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as if set forth in full.

BACKGROUND

1. Technical Field

The present invention relates to a non-volatile memory device, and more particularly, to a non-volatile memory device for reducing a programming time.

2. Related Art

A non-volatile semiconductor memory device such as a NAND flash memory device typically includes electrically erasable and programmable memory cells.

NAND flash memory devices have a read time in the tens of μs (microseconds) per kilobyte and a programming time in the hundreds of μs per kilobyte. Furthermore, NAND flash memory devices, by their nature, require an erase operation before a write operation. This erase operation takes up to several milliseconds, lengthening the required time for programming the desired data.

For example, in the event of a write command from an external host, a considerable amount of time is needed to store data into a NAND flash memory cell, as the data must be transmitted from the external host to the flash memory cell, and the cell must also complete the erase and write operations.

SUMMARY

In one embodiment of the present invention, a memory device includes: first and second planes each comprising a plurality of non-volatile memory cells; first and second buffer corresponding to the first and second planes, respectively; an input/output control unit configured to selectively control input/output paths of data stored in the first and second page buffers; a flash interface connected to the input/output control unit; and a host connected to the flash interface.

DETAILED DESCRIPTION

Hereinafter, a semiconductor storage system according to an embodiment of the present invention is described below with reference to the accompanying drawings.

First, referring toFIG. 1, a non-volatile memory device according to an embodiment of the present invention is described.

FIG. 1is a block diagram of a non-volatile memory device according to an embodiment. The example of a non-volatile memory device illustrated here is a NAND flash memory device.

Referring toFIG. 1, the non-volatile memory device includes a memory area100, a flash interface200, and a host300.

The memory area100is connected to the flash interface200through first and second global line groups GIO0<0:31> and GIO1<0:31>. In this embodiment, the first and second global line groups GIO0<0:31> and GIO1<0:31> have a data bandwidth of 32 bits. In this embodiment, the first and second global line groups GIO0<0:31> and GIO1<0:31> are distinct from each other, but they are in effect interconnected. The first and second global line groups are named as such to illustrate that they are each connected to the respective page buffer (120,140), for reference purposes. That is, the first global line group GIO0<0:31> is a signal line group connected to the first page buffer120, and the second global line group GIO1<0:31> is a signal line group connected to the second page buffer140. No additional signals are needed to control the first and second global line groups GIO0<0:31> and GIO1<0:31>. When first and second planes110and130corresponding to an input address including plane information and page information are in operation, the page buffers120and140connected to the first and second planes110and130, respectively, may be also driven.

The flash interface200is connected to the host300through data input/output lines IO. In addition, the flash interface200includes a plurality of pads through which signals are transmitted to and from the first and second global line groups GIO0<0:31> and GIO1<0:31>. For example, there may be eight data input/output lines IO of the flash interface200connected to the host300. The flash interface200sends to and receives from the host300control commands, address signals, and data signals.

Specifically, the memory area100includes a plurality of planes110and130.

The first plane110(PLANE #0) includes a plurality of pages containing a memory cell array.

The first page buffer120temporarily stores data of a page in the first plane110so that read and write operations for the page may be performed. Then, the data of the corresponding page buffer selected by an input address may be input or output by using the first page buffer120. Furthermore, a typical copy back function may be supported by using the first page buffer120.

The copy back function refers to the transfer of data of a particular page to another page within the same plane using page buffers120and140, and without use of the host300, which is outside the memory area100, and thus supports direct copy operations within the flash memory area.

The second plane130(PLANE #1) and the second page buffer140are provided in correspondence to the first plane110and the first page buffer120.

The second plane130includes a plurality of pages containing a memory cell array. The second page buffer140corresponds to the pages of the second plane130.

According to an embodiment of this invention, an input/output control unit150is provided between the first page buffer120and second page buffer140, and controls input/output paths of the data of the first and second page buffers120and140in response to a control signal EN. In other words, the input/output control unit150may copy data between different planes by using the copy back function, without being restricted to the same plane.

In a conventional memory device, when data stored in a certain page within the first plane110is to be transmitted and stored into another page within the second plane130, the source page of the first plane110is read and stored into the first page buffer120. Then, the stored data is read by the host300via the flash interface200, and the host300provides the read data to the second page buffer140through the flash interface200. Afterwards, the data stored in the second page buffer140is stored in a free page of the second plane130.

As such, a lot of time is conventionally required to store data using pages from different pages, and using the flash interface200and host300. Furthermore, there are at least 32 global lines in the memory area100. On the other hand, there are fewer input/output lines (IO lines) connected to the flash interface200and the host300—typically eight. That is, the host300divides 32 read data bits into groups of eight bits in response to a predetermined signal, and transmits to and receives from the flash interface200such data. Therefore, in a conventional memory device, since the bandwidth of the data inputted and outputted from the memory area100is different from that of the data transmitted and received by the host300, the transfer speed of the data is inevitably limited.

However, according to an embodiment of this invention, the input/output control unit150uses the copy back function such that the host is not used, when the data of the source page within the first plane110is stored into a target page of the second plane130.

In the conventional copy back function, a source page can only be copied into a target page within the same page.

However, according to one embodiment of the present invention, when data is to be transferred between pages of different planes, the data may be transferred between the first and second page buffer120and140to store the data, without using the host300. Therefore, the data storage time may be reduced even when the source plane is different from the target plane, because the host300is not used. In addition, the data transmission is performed by using the first and second global line groups GIO0<0:31> and GIO1<0:31> within the memory area100. Therefore, since the whole 32-bit bandwidth is used, the data transmission speed is high.

The input/output control unit150for controlling the data transmission between the different planes110and130will be described below.

FIG. 2is a block diagram of the input/output control unit150ofFIG. 1.

Referring toFIG. 2, the input/output control unit150includes a first switching section152and a second switching section154.

The first switching section152may selectively provide a signal path of the first global line group GIO0<0:31> to the second to global line group GIO1<0:31> and a DQ page DQ<0:31> in response to a control signal EN.

The second switching section154may selectively provide a signal path of the second global group GIO1<0:31> to the first global line group GIO0<0:31> and the DQ pad DQ<0:31> in response to a control signal EN.

The control signal EN may be activated by using a test mode signal. That is, when the copy back function is to be used without being restricted to any particular planes, the control signal EN may be activated. Furthermore, as described above the DQ pad DQ<0:31> may be provided in the flash interface200.

Therefore, in contrast with the conventional technology, the first global line group GIO0<0:31> is not only connected, to the DQ pad DQ<0:31> within the flash interface200, but the signal of the first global line group GIO0<0:31> may be also transmitted to the second page buffer140in response to the control signal EN, according to one embodiment of this invention. Similarly, the signal of the second global line group GIO1<0:31> may be transmitted to the first page buffer120.

Put differently, according to an embodiment of this invention, the signal path through which the data stored in the first page buffer120can be transmitted to the second page buffer140may be provided within the memory area100, without the involvement of the host300.

FIG. 3is a circuit diagram of the first switching section152ofFIG. 2. Since the configuration and operational principle of the second switching section154are similar to those of the first switching section152, a detailed description will be given as to the first switching section152to avoid duplication.

Referring toFIG. 3, the first switching section152includes a plurality of transmission units1521,1522, . . . connected to the respective global lines of the first global line group GIO0<0:31>.

First, the first transmission unit1521connects a signal path of the first global line GIO0<0> of the first global line group GIO0<0:31> to the first global line GIO1<0> of the second global line group GIO1<0:31> or the DQ pad DQ<0> in response to the control signal EN.

Similarly, the second transmission unit1522selectively provides a signal path of the second global line GIO0<1> of the first global line group GIO0<0:31> to the second global line GIO1<1> of the second global line group GIO1<0:31> or the DQ pad DQ<1> in response to the control signal EN.

The first transmission unit1521includes first and second transmission gates TR1and TR2and an inverter INV1.

Similarly, the second transmission unit1522includes third and fourth transmission gates TR3and TR4and an inverter INV2.

Again referring toFIGS. 1 through 3, a case in which the copy back mode is performed without being restricted to particular planes will be described.

An example maybe taken where data of a source page of the first plane110is to be stored in a target page of the second plane130.

At this time, a typical copy back read command is used to read the data of the source page of the first plane110into the first page buffer120. In this case, an address corresponding to the source page of the first plane110is inputted when the copy back read command is given.

Then, the control signal EN is activated in response to a new copy back command (not shown), which is used without being restricted to particular planes. In this case, an address corresponding to the target page of the second plane130is inputted to the new copy back command.

Continuously, the first transmission gate TR1is turned on and the second transmission gate TR2is turned off in response to an activated high-level control signal EN.

Accordingly, the signal path of the first global line GIO0<0> of the first global line group GIO0<0:31> may be connected to the first global line GIO1<0> of the second global line group GIO1<0:31>. As such, the data of the first page buffer120may be transmitted through the second global line group GIO1<0:31> from the first global line group GIO0<0:31> and stored in the second page buffer140, while maintaining the 32-bit bandwidth. Subsequently, the data of the second page buffer140may be transferred and stored into the target page of the second plane130corresponding to the address.

When a normal command is given, the control signal EN is deactivated. In this case, the second transmission gate TR2is turned on and the first transmission gate TR1is turned off in response to the deactivated low-level control signal EN. Therefore, the signal of the first global line GIO0<0> of the first global line group GIO0<0:31> is transferred to the pad DQ<0>.

According to one embodiment of this invention, the actual programming time of data without any plane restriction may include the time tR required for reading source data from the first plane110into the first page buffer120, the time tTR required for transferring the source data using the first and second line groups GIO0<0:31> and GIO1<0:31>, and the program time tPROG required for storing the data from the second page buffer140into the target page of the second plane130.

That is, the time it takes to transfer data in units of 8 bits (1-byte) between the flash interface200and the host300, and again from the host300to the flash interface200may be reduced. Frequent involvement of the host300increases the load of the system and inevitably hampers the data processing speed.

According to the above-described embodiment, the simple switching circuit may be provided and the copy back command may be used to directly control the data transfer between different planes within the memory area. Therefore, since the data storage is performed without being transferred to the host300while maintaining the bandwidth, the data transmission time and the data programming time may be reduced.

Those skilled in the art understand that this invention may be practiced in another embodiment without altering its technical theory or essential characteristics, and therefore that the above embodiments are examples only and not limiting. The scope of this invention is represented by the scope of the claims provided below, rather than by the above detailed descriptions. The patent claims, including all changes and amendments thereto, shall be part of the scope of this invention.