Dual SIMOX hybrid orientation technology (HOT) substrates

This invention provides a separation by implanted oxygen (SIMOX) method for forming planar hybrid orientation semiconductor-on-insulator (SOI) substrates having different crystal orientations, thereby making it possible for devices to be fabricated on crystal orientations providing optimal performance. The method includes the steps of selecting a substrate having a base semiconductor layer having a first crystallographic orientation separated by a thin insulating layer from a top semiconductor layer having a second crystallographic orientation; replacing the top semiconductor layer in selected regions with an epitaxially grown semiconductor having the first crystallographic orientation; then using an ion implantation and annealing method to (i) form a buried insulating region within the epitaxially grown semiconductor material, and (ii) thicken the insulating layer underlying the top semiconductor layer, thereby forming a hybrid orientation substrate in which the two semiconductor materials with different crystallographic orientations have substantially the same thickness and are both disposed on a common buried insulator layer. In a variation of this method, an ion implantation and annealing method is instead used to extend an auxiliary buried insulator layer (initially underlying the base semiconductor layer) upwards (i) into the epitaxially grown semiconductor, and (ii) up to the insulating layer underlying the top semiconductor layer.

RELATED APPLICATIONS

This application is related to co-pending and co-assigned U.S. patent application Ser. No. 10/250,241, filed Jun. 17, 2003 entitled “High-performance CMOS SOI devices on hybrid crystal-oriented substrates,” co-pending and co-assigned U.S. patent application Ser. No. 10/634,446, filed Aug. 5, 2003 entitled “Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes,” and co-pending and co-assigned U.S. patent application Ser. No. 10/725,850, filed Dec. 2, 2003 entitled “Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers.” The entire content of each of the three applications mentioned above is incorporated by reference.

The '241 application describes an epitaxial growth method for making a planar hybrid orientation substrate which comprises one or more regions of a first single-crystal semiconductor disposed on bulk silicon, said first semiconductor having a first orientation; and one or more regions of a second single-crystal semiconductor disposed on a buried oxide (BOX) layer, said second semiconductor having a second orientation different from the first.

The '446 application expands upon the methods of the '241 application, providing additional steps for selectively forming a BOX layer under the one or more regions of second semiconductor by a SIMOX (separation by implanted oxygen) treatment applied through openings in a mask.

The '850 application describes an amorphization/templated recrystallization (ATR) method for making a planar hybrid orientation substrate which includes one or more regions of a first single-crystal semiconductor with a first orientation, and one or more regions of a second single-crystal semiconductor with a second orientation, where both first and second semiconductor regions are disposed on a BOX layer created by a SIMOX treatment applied to both semiconductor regions.

Like the '446 application, the present application expands upon the methods of the '241 application by providing a SIMOX treatment to form a buried insulating layer under the second semiconductor regions. However, the SIMOX treatment in the present application is applied to both the first semiconductor region and the second semiconductor region, leaving both semiconductor regions disposed on buried insulating layers that are at least partially created by SIMOX.

FIELD OF THE INVENTION

The present invention relates to high-performance metal oxide semiconductor field effect transistors (MOSFETs) for digital or analog applications, and more particularly to MOSFETs utilizing carrier mobility enhancement from substrate surface orientation.

BACKGROUND OF THE INVENTION

In present semiconductor technology, complementary metal oxide semiconductor (CMOS) devices, such as nFETs (i.e., n-channel MOSFETs) or pFETs (i.e., p-channel MOSFETs), are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation.

Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4× lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area.

On the other hand, hole mobilities on (110) Si are 2× higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.

As can be deduced from the above, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.

In view of the above, there is a need for providing integrated semiconductor devices that are formed upon a substrate having different crystal orientations that provide optimal performance for a specific device. A need also exists to provide a method to form such an integrated semiconductor device in which both the nFETs and the pFETs are formed on a silicon-on-insulator substrate having different crystallographic orientations in which the semiconducting layers that the devices are built upon are substantially coplanar and have substantially the same thickness.

Prior art approaches to this problem are shown inFIGS. 1-3. Specifically,FIGS. 1A-1Fshow the steps of a prior art epitaxial growth method described in U.S. Ser. No. 10/250,241 for making a planar hybrid orientation substrate comprising one or more regions of a first single-crystal semiconductor disposed on bulk silicon, said first semiconductor having a first orientation; and

one or more regions of a second single-crystal semiconductor disposed on a BOX layer, said second semiconductor having a second orientation different from the first.

FIG. 1Ashows an initial semiconductor-on-insulator (SOI) substrate10comprising a base semiconductor substrate layer20having a first orientation; a dielectric or buried oxide layer30; an SOI layer40having a second orientation different from the first; and an optional surface dielectric masking/passivation layer50. Layers20,30, and40of the initial SOI substrate10are typically formed by bonding two different semiconductor wafers together. The base semiconductor substrate layer20may optionally be substituted with any combination of semiconductor and insulating layers provided that an upper surface portion of the base semiconductor substrate includes a top layer of a single crystal semiconductor.

FIG. 1Bshows the structure ofFIG. 1Aafter one or more openings60are formed in layers50,40, and30to expose a surface of the base semiconductor substrate20. As shown inFIG. 1C, sidewall spacers70may be formed on the exposed sidewalls of the openings60. Next, a semiconductor material80having the same crystallographic orientation as that of the base semiconductor substrate20is epitaxially grown in the opening60on exposed surfaces of layer20and thereafter an optional planarization step can be utilized to form the structure ofFIG. 1D.FIG. 1Eshows the structure ofFIG. 1Dafter additional planarization steps to remove the masking/passivation layer50, andFIG. 1Fshows the structure ofFIG. 1Eafter optional formation of shallow trench isolation regions90.

A drawback of the method described above and illustrated inFIGS. 1A-1Fis that the processing leaves only one of the semiconductor orientations disposed on a BOX.FIGS. 2A-2Fshow the additional masking and SIMOX (separation by implanted oxygen) steps described in U.S. application Ser. No. 10/634,446 that can be applied to the structure ofFIG. 1D,1E, or1F to selectively form a BOX layer in the one or more regions of the epitaxially grown semiconductor80.FIG. 2Ashows the structure ofFIG. 1Dafter formation of a patterned mask100with a mask opening110.FIG. 2Bshows the structure ofFIG. 2Abeing implanted with oxygen ions120to form an oxygen-rich silicon layer130and a damaged single crystal semiconductor region140in the semiconductor layer80exposed by the mask opening110.FIG. 2Cshows the structure ofFIG. 2Bafter a high temperature annealing in an oxygen-containing ambient has converted the oxygen-rich silicon layer130into a buried oxide layer150, and the damaged semiconductor region140into a device-quality semiconductor layer140′. A surface oxide layer170also forms during the high temperature annealing step.FIG. 2Dshows the structure ofFIG. 2Cafter removal of the masking layers50and100, removal of the surface oxide layer170, and partial removal of the sidewall spacers70.FIG. 2Eshows the structure ofFIG. 2Dafter optional formation of shallow trench isolation regions190.

A drawback of the approach described above and illustrated inFIGS. 2A-2Eis that it requires additional masking layers to protect the semiconductor layer40from the SIMOX implant and anneal. Use of such masking layers would typically require the additional steps of mask layer deposition, and lithographic alignment and patterning.

FIGS. 3A-3Doutline an alternative amorphization/templated recrystallization (ATR) method described in U.S. Ser. No. 10/725,850 for making a planar hybrid orientation substrate having one or more regions of a first single-crystal semiconductor with a first orientation, and one or more regions of a second single-crystal semiconductor with a second orientation, where both first and second semiconductor regions are disposed on a BOX layer created by a SIMOX treatment applied to both semiconductor regions.FIG. 3Ashows a bonded substrate200comprising a semiconductor substrate210having a first crystallographic orientation and a semiconductor layer220having a second orientation joined at a bonding interface215. Selected regions of the substrate200are amorphized by a process such as ion implantation to produce the structure ofFIG. 3Bwhich includes an amorphized region230and non-amorphized regions220′. The amorphized region230is then recrystallized with a process such as annealing to form a crystalline semiconductor240having the orientation of the semiconductor substrate210, as shown inFIG. 3C. (Trenches or shallow trench isolation regions, not shown, would typically be formed at the boundaries between the amorphized and non-amorphized regions (230and220′, respectively) of the semiconductor layer220to prevent lateral templating.) A buried oxide region250is then formed under the differently oriented semiconductor regions220′ and240by a SIMOX treatment applied to both semiconductor regions, as shown inFIG. 3D.

While the ATR approach illustrated inFIGS. 3A-3Dis highly attractive, it (i) is less mature than epitaxial regrowth methods, and (ii) can be sensitive to oxides and contamination at the bonding interface215.

In view of the above drawbacks with prior art approaches, there is a need for providing a method that is capable of creating a semiconductor substrate material having semiconductor layers of different crystallographic orientations that are substantially coplanar and of substantially the same thickness, yet are both located atop a buried insulating layer, e.g., a BOX layer.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a method of fabricating integrated semiconductor devices such that different types of CMOS devices are formed upon a specific crystal orientation of a silicon-on-insulator (SOI) substrate that enhances the performance of each device.

Another object of the present invention is to provide a method of fabricating integrated semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of the same SOI substrate.

A further object of the present invention is to provide a method of integrating SOI technology with CMOS technology using simple and easy processing steps.

A still further object of the present invention is to provide a method of forming an integrated semiconductor structure in which both CMOS devices, i.e., pFETs and nFETs, are SOI like.

Yet another object of the present invention is to provide a method of forming a hybrid orientation SOI substrate having differently oriented semiconductor layers that are substantially coplanar and have substantially the same thickness.

These and other objects and advantages are achieved in the present invention by utilizing bonding and epitaxial growth methods to form planar hybrid substrates comprising bonded semiconductor regions of one crystallographic orientation disposed directly on a first buried insulating layer, and epitaxially grown semiconductor regions of a different crystallographic orientation not disposed directly on the first buried insulating layer, and then applying a SIMOX-like treatment (including one or more ion implantation of oxygen or nitrogen steps and one or more annealing steps) to both the bonded and epitaxially grown semiconductor regions to (i) form a second buried insulating region in the epitaxially grown semiconductor material and (ii) thicken the first buried insulating layer underlying the bonded semiconductor layer. After removal of any surface oxides produced by the SIMOX annealing steps and an optional touch-up planarization step, the bonded semiconductor and the epitaxially grown semiconductor are left as SOI regions that are substantially coplanar and have substantially the same thickness.

At least one nFET and at least one pFET may then be formed on either the bonded semiconductor layer or the epitaxially grown semiconductor material depending on which surface orientation is optimal for that device. Both CMOS devices, i.e., the nFET and the pFET, are SOI-like devices since they are both located in a SOI layer disposed on a buried insulator.

In particular, the present invention provides a method of forming an integrated semiconductor structure comprising the steps of:

providing a substrate comprising a base semiconductor substrate layer having a first crystallographic orientation, the base semiconductor substrate layer separated by a first insulating layer from a top semiconductor layer of a second crystallographic orientation, said first crystallographic orientation being different from said second crystallographic orientation;

forming at least one opening in the substrate that exposes a surface of the base semiconductor substrate layer;

filling said at least one opening with an epitaxially grown semiconductor material on said exposed surface of the base semiconductor substrate layer, said epitaxially grown semiconductor material having a crystallographic orientation that is the same as the first crystallographic orientation; and

implanting and annealing to (i) form a second insulating layer in the epitaxially grown semiconductor material, and (ii) thicken said first insulating layer underlying the top semiconductor layer.

Following the implanting and annealing step, an optional planarization and/or surface treatments may be used to provide a structure in which the remaining epitaxially grown semiconductor material having the first crystallographic orientation is substantially coplanar and of substantially the same thickness as that of the remaining top semiconductor layer.

The base semiconductor substrate layer described above may be disposed on any combination of semiconductor and insulating layers, including, for example, an auxiliary buried insulator layer. In this case, the steps of (i) forming a second insulating layer within the epitaxially grown semiconductor material, and (ii) thickening said first insulating layer underlying the top semiconductor layer are more precisely described, respectively, as extending the auxiliary buried insulator layer upwards (i) into the epitaxially grown semiconductor, and (ii) up to the first insulating layer underlying the top semiconductor layer.

The present invention also encompasses a variation of the above method in which the first insulating layer separating the base semiconductor substrate layer and the top semiconductor layer is omitted, leaving the base and top semiconductor layers in direct contact at a semiconductor-to-semiconductor interface. In this version, the ion implantation and annealing process is implemented so as to leave the top of the resulting second insulating layer at, or above, the level of the semiconductor-to-semiconductor interface.

DETAILED DESCRIPTION OF THE INVENTION

The present invention, which provides double SIMOX HOT (hybrid orientation technology) substrates, will now be described in more detail by referring to the drawings that accompany the present application. In the accompanying drawings, like and corresponding elements are referred to by like reference numerals. It is noted that the drawings of the present application are provided for illustrative purposes and are thus not drawn to scale.

FIGS. 4A-4Hshow, in cross section view, possible initial substrates that can be employed in the present invention. The initial substrates ofFIGS. 4A-4Hare all planar, hybrid orientation substrates comprising a base semiconductor substrate layer20having a first orientation, and one or more top semiconductor layers or regions300having a second orientation different from the first orientation. The one or more top semiconductor regions300are typically formed by bonding utilizing the procedures described in the '241 application that was previous incorporated herein by reference. The one or more top semiconductor regions300may be disposed on a first insulating layer330(as shown inFIGS. 4A-4Dand4H) or they may be disposed directly on the base semiconductor substrate layer20(as shown inFIGS. 4F and 4G), to form an interface331. The first insulating layer330may comprise an oxide or nitride, and it typically has a thickness from about 2 to about 200 nm.

The base semiconductor substrate layer20may be disposed on any combination of semiconductor and insulating layers. In the structures ofFIGS. 4A-4Dand4G-4H, the base semiconductor substrate layer20comprises a bulk semiconductor substrate wafer. In the structures ofFIGS. 4E and 4F, the base semiconductor substrate layer20is disposed on an auxiliary buried insulator layer325situated on a substrate335. The auxiliary buried insulator layer325comprises an oxide or nitride and it typically has a thickness from about 50 to about 500 μm. The substrate335includes one of the semiconductor materials mentioned below.

The base semiconductor substrate layer20comprises any type of semiconducting material including, for example, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP as well as other III/V or II/VI compound semiconductors. The base semiconductor substrate layer20may also comprise a combination of these semiconductor materials. The base semiconductor substrate layer20may be strained, unstrained or a combination of strained and unstrained layers can be used. The base semiconductor substrate layer20is also characterized as having a first crystallographic orientation which may be, for example, (110), (111) or (100).

The one or more top semiconductor layers300include one of the above mentioned semiconductor materials. Hence, it is possible in the present invention that the one or more top semiconductor layers300comprise the same semiconductor material as the base semiconductor substrate layer20, or they may comprise a different semiconductor material than the base semiconductor substrate layer20. As indicated above, the one or more top semiconductor layers300have a second crystallographic orientation that is different from the first crystallographic orientation of the base semiconductor substrate layer20.

One or more epitaxially grown semiconductor regions310are disposed directly on the base semiconductor substrate layer20and separated from the one or more top semiconductor layers300by (preferably insulating, i.e., oxide, nitride, oxynitride and combinations, including multilayers, thereof) sidewall spacers320. The epitaxially grown semiconductor regions310are comprised of one of the above mentioned semiconductor materials (which may be the same semiconductor material or a different semiconductor than the base semiconductor substrate layer20) and have the same crystallographic orientation as that of the base semiconductor substrate layer20. The lines that are labeled by reference numeral311inFIGS. 4A-4Hare used to indicate the position of the invisible interface between the base semiconductor substrate layer20and the epitaxially grown semiconductor regions310.

The substrates ofFIGS. 4A-4Gmay also include a residual masking layer350(such as shown inFIG. 4Hfor the case of the structure ofFIG. 4A) if the masking layer350is thin enough not to substantially interfere with the subsequent SIMOX (separation by implanted oxygen) steps. If present, the masking layer350is comprised of an insulating material such as, for example, an oxide or nitride. The thickness of the masking layer350is typically from about 20 to about 50 nm.

The structures ofFIGS. 4A-4Ddiffer in the thickness of the first insulating layer330(note the first insulating layer and the second insulating layer to be subsequently formed can both be referred to as buried insulator regions) and the depth of sidewall spacers320. The structures ofFIGS. 4A and 4Bhave a thin first insulating layer330, typically between 1 and 20 nm in thickness, and more typically between 2 and 10 nm in thickness; the structures ofFIGS. 4C and 4Dhave a thicker first insulating layer330, typically between 20 and 1000 nm in thickness, and more typically between 50 and 200 nm in thickness. The sidewall spacers320extend to the bottom of the first insulating layer330in the structures ofFIGS. 4A and 4C, and past the first insulating layer330into the base semiconductor substrate layer20in the structures ofFIGS. 4B and 4D.

It is again noted that the structures ofFIGS. 4A-4Gand the like may be fabricated by methods and with materials known to the art, for example, by the methods described in connection withFIGS. 1A-1F, and the methods and materials described in previously incorporated U.S. patent application Ser. Nos. 10/250,241 and 10/634,446.

FIGS. 5A-5Eand6A-6D outline how a SIMOX-like treatment (including one or more oxygen or nitrogen ion implantation steps and one or more annealing steps) can be applied to the structures shown inFIGS. 4A-4H. In particular, illustration is provided for the particular cases of the structure shown inFIGS. 4A and 4E(where the first insulating layer330is present and thin).FIGS. 5A-5Eillustrate this for the case of the initial structures without the auxiliary buried insulator325andFIGS. 6A-6Dillustrate this for the case of the initial structures with the auxiliary buried insulator325.

Specifically,FIGS. 5A-5Eoutline how a SIMOX-like treatment cant be applied to both the one or more top semiconductor regions300and the epitaxially grown semiconductor regions310to (i) form a second buried insulating layer within the epitaxially grown semiconductor regions310and (ii) thicken the first buried insulating layer330(or other dielectric layer) underlying the top semiconductor layer300.

FIG. 5Ashows the first step of this process for an initial substrate having the structure ofFIG. 4A. Ions380, such as oxygen or nitrogen, are implanted into the structure ofFIG. 5Ato produce the structure shown inFIG. 5Bwith a buried implant region400below the top surfaces of the one or more top semiconductor layers300and the epitaxially grown semiconductor regions310, now denoted as damaged bonded semiconductor regions300′ and damaged epitaxially grown semiconductor regions310′ respectively. The buried implant region400contains a high concentration of implanted species that is capable of forming a second buried insulating layer410during a subsequent high temperature annealing step. The depth and extent of the implant region400is selected so that the second buried insulating layer410subsequently to be formed from the implant region400will have the desired depth alignment with the first buried insulating layer330, the position of which is indicated by370. The second buried insulating layer410is centered around position370of the first buried insulating layer330in the structure ofFIG. 5C, centered above position370in the structure ofFIG. 5D, and centered below position370in the structure shown inFIG. 5E.

FIGS. 6A-6Doutline how a SIMOX-like treatment can be applied to both the one or more top semiconductor regions300and the epitaxially grown semiconductor regions310to extend the auxiliary buried insulator325upwards (i) into the epitaxially grown semiconductor310, and (ii) up to the first insulating layer330underlying the semiconductor base substrate layer20.FIG. 6Ashows the first step of this process for an initial substrate having the structure ofFIG. 4E. Ions380, such as oxygen or nitrogen, are implanted into the structure ofFIG. 6Ato produce the structure shown, for example, inFIG. 6Bwith the buried implant region400. The buried implant region400is situated below the top surfaces of the one or more top semiconductor regions300and the epitaxially grown semiconductor regions310, now denoted as damaged bonded semiconductor regions300′ and damaged epitaxially grown semiconductor regions310′, respectively, and extends into the auxiliary buried insulator325. In this embodiment, the implant region400contains a high concentration of implanted species which is capable of forming the second buried insulating layer410during a subsequent high temperature annealing step. The depth and extent of the implant region400is selected so that the second buried insulating layer410subsequently to be formed from the implant region400will have the desired depth alignment with the first buried insulating layer330, the position of which is indicated by370. The second buried insulating layer410may extend above position370of the first insulating layer330, as shown inFIG. 6C, but preferably ends at position370, as shown, for example, inFIG. 6D.

WhileFIGS. 5A-5Eand6A-6D illustrate the application of a SIMOX treatment to structures having a thin first buried insulating layer330, it is noted that the present invention also applies to structures in which the first insulating layer330is thicker and to structures without the first insulating layer330. In the case without first insulating layer330, the ion implantation and annealing process is implemented so as to leave the top of the resulting second insulating layer at, or above, the level of the semiconductor-to-semiconductor interface. However, buried insulator formation with SIMOX treatments tends to be easier when the initial structure has at least some buried insulator (330or325) present.

The ion implantation used to create the buried implant layer400may include various well-known ion implantation conditions (see, for example, G. K. Celler and S. Cristoloveanu, J. Appl. Phys. 93 4955 (2003)), including for example, the following high dose and low dose ion implantation conditions:

High Dose Implantation:

The term “high dose” as used herein denotes an O+ion dosage of about 4E 17 cm−2or greater, with an ion dosage from about 4E17 to about 2E18 cm−2being more preferred. In addition to using high dosage, this implant is typically carried out in an ion implantation apparatus at an energy from about 10 to about 1000 keV. An implant energy from about 60 to about 250 keV is more typically used.

This implant, which may also be referred to as a base ion implant, is carried out at a temperature from about 200° to about 800° C. at a beam current density from about 0.05 to about 50 μA cm−2. More preferably, the base ion implant may be carried out at a temperature from about 200° to about 600° C. at a beam current density from about 5 to about 20 μA cm2.

If desired, the base implant step may be followed by a second O+implant that is carried out using a dose from about 1E14 to about 1E16 cm−2, with a dose from about 1E15 to about 4E15 cm−2being more highly preferred. The second implant is carried out at an energy from about 40 keV or greater, with an energy from about 120 to about 450 keV being more preferred.

This second implant is performed at a temperature from about 4K to about 200° C. with a beam current density from about 0.05 to about 10 μA cm−2. More preferably, the second implant may be performed at a temperature from about 25° to about 100° C. with a beam current density from about 0.5 to about 5.0 μA cm−2.

When employed, the second implant forms an amorphous region below the damaged region caused by the base ion implant step. During the subsequent annealing, the amorphous and damaged regions are converted into the second buried insulating region described above.

Low Dose Implantation:

The term “low dose” as used herein for this embodiment of the present invention denotes an ion dose of about 4E17 cm−2or less, with an ion dose from about 1E17 to about 3.9E17 cm−2being more preferred. This low dose implant is performed at an energy from about 40 to about 500 keV, with an implant energy from about 60 to about 250 keV being more highly preferred.

This low dose implant, which may be referred to as a base ion implant, is carried out at a temperature from about 100° to about 800° C. More preferably, the base ion implant may be carried out at a temperature from about 200° to about 650° C. The beam current density used in the low dose implant is from about 0.05 to about 50 μA cm−2.

If desired, the base low dose implant step may be followed by a second O+ implant that is carried out using the conditions mentioned above.

It is again emphasized that the above types of ion implantations are exemplary and by no way limit the scope of the present invention. Instead, the present invention contemplates all conventional ion implant conditions, annealing conditions, and combinations of ion implant and anneal sequences found useful for SIMOX processing in more conventional substrates.

After ion implantation, the structures ofFIGS. 5B and 6B, including the implant regions400, are subjected to a high temperature annealing process that is capable of converting the implant region400into the second buried insulating layer410. As described above, the second buried insulating layer410is preferably created with the desired depth alignment with respect to the first buried insulating layer330. This annealing process also converts damaged semiconductor regions300′ and damaged epitaxially grown semiconductor regions310′ into a device quality semiconductor regions300″ and310″.

Specifically, the annealing step of the present invention is performed at a temperature from about 700° to about 1400° C., with a temperature from about 1100° to about 1300° C. being more highly preferred. Moreover, the annealing step of the present invention is carried out in an oxidizing ambient. The oxidizing ambient used during the annealing step includes at least one oxygen-containing gas such as O2, NO, N2O, ozone, air as well as other like oxygen-containing gases. The oxygen-containing gas may be admixed with each other (such as an admixture of O2and NO), or the gas may be diluted with an inert gas such as He, Ar, N2, Xe, Kr, or Ne.

The annealing step may be carried out for a variable period of time, which typically ranges from about 1 to about 100 hours, with a time period from about 2 to about 24 hours being more highly preferred. The annealing step may be carried out at a single targeted temperature, or with various ramp and soak cycles using various ramp rates and soak times.

Because the annealing is performed in an oxidizing ambient, an upper portion of the semiconductor materials300′ and310′ is expected to oxidize if no barrier layer is present, as shown inFIGS. 7A-7C. Specifically,FIG. 7Ashows a typical implanted structure before annealing, whileFIG. 7Bshows the structure ofFIG. 7Aafter formation of a surface oxide layer430. For the case of Si semiconductors, the surface oxide layer430would have a thickness approximately equal to twice the thickness of the consumed silicon.

Referring now toFIG. 7B, the surface oxide layer430, along with the masking layer350(if present) and at least a portion of the sidewall spacers320are removed selectively with respect to the semiconductor material. This step may be referred to as a planarization process since it provides the planar structure shown in FIG.7C. An example of a wet chemical etch solution that selectively removes oxide as compared to semiconductor material is buffered HF. Because the spacers320are typically located in the isolation region (instead of the active device region), recess or removal of the spacers320is acceptable. Damaged spacers320′ can be replaced or repaired during the formation of trench isolation regions.

FIGS. 8A-8Dillustrate an alternative method of performing the annealing steps needed for the ion implantation and annealing process, one that uses a barrier layer to prevent or reduce semiconductor surface oxidation.FIG. 8Ashows a typical implanted structure before annealing.FIG. 8Bshows the structure ofFIG. 8Aafter deposition of a deposited layer420. The deposited layer420may comprise a single material or a layered stack of materials, but is preferably thermally stable, non-reactive with respect to the underlying semiconductor regions, and easy to selectively remove after the anneal. Preferred materials for layer420include SiO2, SiNx, SiNx/SiO2bilayers with SiNxas the bottom (etch stop) layer, and any of these layers with overlayers of Si thin enough to be completely converted to SiO2during the anneal. Barrier layer thicknesses are preferably in the range from 30 to 300 nm, and more preferably in the range from 50 to 100 nm.

After the high temperature anneal and optional planarization steps, at least one nFET and at least one pFET may then be formed on either bonded semiconductor regions300″ or epitaxially grown semiconductor regions310″, depending on which surface orientation is optimal for that device.FIG. 9shows nFET550and pFET560optimally arranged on the substrate structure ofFIG. 7Cor8D after the sidewall spacers320have been incorporated into shallow trench isolation regions520.

The one or more nFETs550and pFETs560are formed utilizing standard CMOS processing steps that are well-known to those skilled in the art. As described in U.S. patent application Ser. No. 10/634,446, each FET includes a gate dielectric, a gate conductor, an optional hard mask located atop the gate conductor, spacers located on sidewalls of at least the gate conductor, and diffusion regions. The pFETs would typically be formed over a semiconductor material that has a (110) or (111) orientation, whereas the nFETs would typically be formed over a semiconductor surface having a (100) or (111) orientation.

It should be noted that while the second buried insulating layer410is shown as having a uniform thickness, it may have different thicknesses under different semiconductor regions. For example, the second buried insulating layer410may have one thickness in “all-SIMOX” regions (where the SIMOX-created buried insulator is created in the epitaxially grown semiconductor regions310) and another in “part-SIMOX” regions (where the SIMOX-created buried insulator augments originally present first buried insulating layer330). The thickness of the second buried insulating layer410can be affected by a number of factors including (i) the thickness of the original buried insulating layer330, and (ii) the semiconductor orientations in which (or between which) the SIMOX buried insulator, i.e., second buried insulating layer410, is formed (since chemical reactivity, semiconductor/oxide interface stability, and diffusion rates can be highly orientation dependent).

Since it is typically more difficult to create a SIMOX buried oxide layer in 110-oriented Si than in 100-oriented Si, a preferred route to the uniform-thickness buried insulator structures ofFIG. 7Cor8D for the case of Si semiconductors with 110 and 100 orientations would utilize Si with a110orientation as the bonded semiconductor layer300, and Si with a 100 orientation as the substrate20and the epitaxially grown semiconductor layer310. With this approach, the all-SIMOX buried oxide would be formed in 100 Si, and the part-SIMOX buried insulator would be formed at or around a Si(110)/Si(100) interface. The first buried insulating layer330would preferably have a thickness selected to compensate for the expected orientation-related differences in the thicknesses of the SIMOX-created portion of the buried insulator, thereby allowing the second buried insulating layer410to have a substantially uniform thickness.

Alternatively, for cases in which the thickness of a SIMOX-created buried insulator layer is relatively insensitive to semiconductor orientation (e.g., for certain SIMOX conditions and/or types of semiconductor materials), the thickness of the first buried insulating layer330would preferably be thin as possible.