Multi-chip module having a support structure and method of manufacture

A multi-chip module and a method for manufacturing the multi-chip module that mitigates wire breakage. A first semiconductor chip is mounted and wirebonded to a support substrate. A spacer is coupled to the first semiconductor chip. A support material is disposed on the spacer and a second semiconductor chip is positioned on the support material. The second semiconductor chip is pressed into the support material squeezing it into a region adjacent the spacer and between the first and second semiconductor chips. Alternatively, the support material is disposed on the first semiconductor chip and a die attach material is disposed on the spacer. The second semiconductor chip is pressed into the die attach material and the support material, squeezing a portion of the support material over the spacer edges. Wirebonds are formed between the support substrate and the first and second semiconductor chips.

FIELD OF THE INVENTION

The present invention relates, in general, to semiconductor components and, more particularly, to semiconductor components comprising multi-chip modules.

BACKGROUND OF THE INVENTION

The desire for faster, cheaper, and more efficient semiconductor components has motivated semiconductor component manufacturers to shrink the sizes of the devices fabricated in a semiconductor chip and place multiple semiconductor chips in a single package typically referred to as a multi-chip module. The semiconductor chips in a multi-chip module can be placed either in a horizontal orientation, i.e., beside each other, or in a vertical orientation, i.e., vertically stacked on top of each other. In a conventional vertically stacked multi-chip module, a first semiconductor chip is attached to a circuit board by adhesive bonding followed by wirebonding bonding pads located on the semiconductor chip to corresponding bonding pads located on the circuit board. A spacer is formed on or attached to the first semiconductor chip and a second semiconductor chip is attached to the spacer. Then bonding pads located on the second semiconductor chip are coupled to corresponding bonding pads located on the circuit board using, for example, a wirebonding process. The spacer must be smaller than the first semiconductor chip to accommodate the wirebonding process. What's more, the spacer is typically smaller than the second semiconductor chip. A drawback with this type of structure is that the portions of the second semiconductor chip that overhang the spacer are pliable or springy. Thus, when the bonding pads located on the overhanging portion of the second semiconductor chip are wirebonded to the corresponding bonding pads located on the circuit board, the pliability of the overhanging portions of the second semiconductor chip weakens the bonds formed to bonding pads on the second semiconductor chip. This bond weakening causes catastrophic device failure.

Accordingly, it would be advantageous to have a multi-chip module and a method for manufacturing the multi-chip module that does not degrade the integrity of the bonds formed to the bonding pads. It would be of further advantage for the method and structure to be cost efficient and suitable for integration with a variety of multi-chip module processes.

SUMMARY OF THE INVENTION

The present invention satisfies the foregoing need by providing a multi-chip module and a method for manufacturing the multi-chip module. In accordance with one embodiment, the present invention includes providing a support substrate having first and second major surfaces, wherein the support substrate has a chip receiving area and a plurality of bonding pads. A first semiconductor chip is coupled to the chip receiving area, wherein the first semiconductor chip has a plurality of bonding pads. A first bonding pad of the first semiconductor chip is coupled to a first bonding pad of the support substrate. A spacer is coupled to a portion of the first semiconductor chip. A support material is disposed on at least one of the spacer or the first semiconductor chip. A second semiconductor chip is positioned on the support material, wherein the second semiconductor chip has a first major surface and a plurality of bonding pads. A first bonding pad of the second semiconductor chip is coupled to a second bonding pad of the support substrate.

In accordance with another embodiment, the present invention comprises a method for manufacturing a multi-chip module that includes providing a support substrate having a first semiconductor chip mounted to a chip or die receiving area on the support substrate. The support substrate has a plurality of bonding pads and the first semiconductor chip has a plurality of bonding pads. A spacer is coupled to the first semiconductor chip and a support material is disposed on one of the spacer or the first semiconductor chip. A semiconductor chip is coupled to the spacer such that the support material becomes positioned between the first semiconductor chip and the second semiconductor chip thereby providing support for the second semiconductor chip.

In accordance with yet another embodiment, the present invention comprises a multi-chip module having a support substrate that has a chip receiving area and a plurality of bonding pads. A first semiconductor chip having a plurality of bonding pads is mounted to the chip receiving area. A spacer having first and second opposing edges is coupled to the first semiconductor chip. A support material is in contact with the spacer. A second semiconductor chip is coupled to the spacer, wherein a portion of the support material is positioned between the first semiconductor chip and the second semiconductor chip.

DETAILED DESCRIPTION

Generally, the present invention provides a multi-chip module and a method for manufacturing the multi-chip module, wherein the semiconductor chips of the multi-chip module are vertically stacked. In vertically stacking the semiconductor chips of a multi-chip module, a spacer is inserted between the semiconductor chips to allow clearance for the wirebonds. A portion of the semiconductor chip positioned above the spacer overhangs the edges of the spacer. The portions of a semiconductor chip overhanging the spacer are pliable. Although the pliability increases the fragility of semiconductor chips in general, the increased fragility is more pronounced in semiconductor chips having thicknesses of less than about 0.6 millimeters (mm). This pliability allows the semiconductor chip to vibrate during the wirebonding process, which breaks the wires being bonded to bonding pads on the semiconductor chip. In accordance with the present invention, the vibration is mitigated by forming a support material under the portion of the second semiconductor chip that overhangs the spacer. The support material provides additional rigidity to the semiconductor chip, which decreases the vibrations of the overhanging portions of the semiconductor chip and improves the reliability of the wirebond.

FIG. 1is cross-sectional side view of a portion of a multi-chip module10at an intermediate stage of manufacture in accordance with an embodiment of the present invention. What is shown inFIG. 1is a Ball Grid Array (BGA) support structure12having top and bottom surfaces14and16, respectively. BGA support substrate12is formed from a resin such as an epoxy resin, a polyimide resin, a triazine resin, or a phenolic resin. Preferably, the resin material of BGA support substrate12is bismaleimidetriazine (BT) resin. Other suitable materials for support substrate12include epoxy-glass composites, FR-4, ceramics, and the like. It should be understood that substrate12is not limited to being a BGA substrate but may also be a Pin Grid Array (PGA) substrate, a ceramic substrate, a printed circuit board, or the like. Bonding pads18A and18B and bonding pads20A and20B are formed on top surface14. A plurality of bonding pads22are formed on bottom surface16. Bonding pads18A,18B,20A, and20B are electrically connected to bonding pads22B,22C,22A, and22D, respectively, on bottom surface16through electrical interconnects28,30,26, and32that extend through BGA support substrate12. For the sake of clarity, only four interconnects are shown as extending through BGA support substrate12inFIG. 1. However, it should be understood that all or nearly all of the bonding pads on the top surface of a support substrate such as support substrate12are coupled to bonding pads on the bottom surface of the support substrate. It should be further understood that bonding pads18A and18B are two of a plurality of bonding pads18that are formed on top surface14. Similarly, bonding pads20A and20B are two of a plurality of bonding pads20that are formed on top surface14. (The pluralities of bonding pads18and20are further illustrated and discussed with reference to inFIG. 3). Solder balls34are attached to bonding pads22.

Still referring toFIG. 1, a die attach material36is dispensed on a semiconductor chip receiving area38and a semiconductor chip or die40is placed on die attach material36. Semiconductor chip40has a bottom surface42and a top surface44. A plurality of bonding pads46is disposed around the periphery of top surface44. Bottom surface42of a semiconductor chip or die40is placed on die attach material36. Although only bonding pads46A and46B are shown, it should be understood that bonding pads46A and46B are part of plurality of bonding pads46, which plurality is further shown and described with reference toFIG. 3. The combination of substrate12, semiconductor chip40, and die attach material36is placed in a curing oven and die attach material36is cured. By way of example, die attach material36is cured by heating to a temperature ranging from about 100 degrees Celsius (° C.) to about 175° C. for a time ranging from about 5 minutes to about 60 minutes. Suitable die attach materials include silver filled epoxy, silica filled epoxy blend, an epoxy film filled with an organic material, and the like.

After curing die attach material36, a die attach material48is disposed on a central portion of top surface44and a spacer50is placed on die attach material48. Spacer50has top and bottom surfaces52and54, respectively, and edges53and55. Spacer50may be a dielectric material, a semiconductor material such as, for example, silicon, another semiconductor chip, or the like. Although spacer50is shown as having a square shape, its shape is not a limitation of the present invention. For example, spacer50may have a rectangular shape, a round shape, a triangular shape, etc. Die attach material48is cured by heating it to a temperature ranging from about 100° C. to about 175° C. for a time ranging from about 5 minutes to about 60 minutes. Suitable die attach materials include silver filled epoxy, silica filled epoxy blend, an epoxy film filled with an organic material, and the like.

Still referring toFIG. 1, bonding pads46on semiconductor chip40are electrically connected to corresponding bonding pads18on BGA substrate12using, for example, a wirebonding process. What is shown inFIG. 1is bonding pad46A coupled to bonding pad18A by an interconnect wire56A and bonding pad46B coupled to bonding pad18B by an interconnect wire56B. Although only two interconnect wires are shown inFIG. 1, it should be understood that typically plurality of interconnects56comprises more than two interconnect wires. (The plurality of interconnect wires56is further illustrated and discussed with reference to inFIG. 3).

Referring now toFIG. 2, a cross-sectional side view of multi-chip module10further along in manufacture is illustrated. What is shown inFIG. 2is a support material60disposed on surface44of semiconductor chip40and a die attach material62disposed on surface52of spacer50. Preferably, support material60is an epoxy paste that is a thermal conductor and an electrical insulator. Examples of the epoxy paste comprising support material60include an epoxy material filled with polytetrafluoroethylene sold under the trademark Teflon (Teflon is a trademark of E.I. Du Pont De Demours and Company Corp.), a nonconductive paste (e.g., silica) filled with an inorganic material, bismaleimide material filled with polytetrafluoroethylene sold under the trademark Teflon, and the like. Suitable materials for die attach material62include silver filled epoxy, silica filled epoxy blend, an epoxy film filled with an organic material, and the like.

Referring now toFIG. 3, a top view of multi-chip module10is shown, wherein the top view illustrates the same stage of manufacture as that shown inFIG. 2. In other words,FIG. 2is a cross-sectional side view taken along section line2-2ofFIG. 3.FIG. 3further illustrates the plurality of bonding pads18, the plurality of bonding pads20, the plurality of bonding pads46, the plurality of wire interconnects56, as well as the individual bonding pads18A,18B,20A, and20B and the individual interconnects56A and56B shown inFIG. 2. In addition,FIG. 3illustrates support material60and die attach material62. Although support material60is shown as having a double-Y or dogbone shape, this is not a limitation of the present invention. For example, support material60can be formed to have circular shapes, triangular shapes, quadrilateral shapes, pentagonal shapes, as well as other polygonal shapes.

Referring now toFIG. 4, a cross-sectional side view of multi-chip module10further along in manufacture is illustrated. A semiconductor chip64is placed on die attach material62. More particularly, semiconductor chip64has a backside66that is placed on die attach material62and a front side68that has a plurality of bonding pads70formed thereon. Pressure is applied to semiconductor chip64to position it in die attach material62and to squeeze support material60in a lateral direction so that it substantially fills the region between surfaces44and66. In this region, peripheral portions65of semiconductor chip64overhang spacer50. Support material60and die attach material62are cured by being heated to a temperature ranging from about 100° C. to about 175° C. for a time ranging from about 5 minutes to about 60 minutes. Because support material60substantially fills the region between surfaces44and66, the peripheral portions65of semiconductor chip64do not freely overhang edges53and54, but are supported by support material60. Thus, peripheral portions65do not bounce significantly during a subsequent wirebonding step. An advantage of placing support material60between surfaces44and66is that it improves the manufacturability and reliability of wirebonds formed in multi-chip modules.

A plurality of bonding pads70are electrically connected to corresponding bonding pads of plurality of bonding pads20using, for example, a wirebonding process. More particularly, bonding pad70A is electrically connected to bonding pad20A by an interconnect wire74A and bonding pad70B is electrically connected to bonding pad20B by an interconnect wire74B. Interconnect wires74A and74B are two interconnect wires of plurality of interconnect wires74.

Referring now toFIG. 5, a protective covering78is formed over semiconductor chip64, interconnect wires56and74, and BGA substrate12. The protective covering illustrated inFIG. 5is a glob top material. However, it should be understood that the type of protective material is not limited to being a glob top material. For example, protective covering78may be a lid or cap.

FIG. 6illustrates a multi-chip module100in accordance with another embodiment of the present invention. The beginning steps in the manufacture of multi-chip module100are the same as those for the manufacture of multi-chip module10. Thus, the description ofFIG. 6continues from that ofFIG. 1. A support material102is disposed on a central portion of spacer surface52. Preferably, support material102is an epoxy paste that is thermally conductive and electrical non-conductive, i.e. it is an electrical insulator. Suitable epoxy pastes for support material102include epoxy material filled with polytetrafluoroethylene sold under the trademark Teflon, nonconductive paste (e.g., silica) filled with an inorganic material, bismaleimide material filled with polytetrafluoroethylene sold under the trademark Teflon, and the like. Support material102also serves as a die attach material.

Referring now toFIG. 7, a top view of multi-chip module100is shown wherein the top view illustrates the same stage of manufacture as that shown inFIG. 6. In other words,FIG. 6is a cross-sectional side view taken along section line6-6ofFIG. 7. LikeFIG. 3,FIG. 7further illustrates the plurality of bonding pads18, the plurality of bonding pads20, the plurality of bonding pads46, the plurality of wire interconnects56, as well as the individual bonding pads18A,18B,20A, and20B and the individual interconnects56A and56B shown inFIGS. 2 and 6. In addition, FIG.7illustrates support material102. Although support material102is shown as having a double-Y or dogbone shape, this is not a limitation of the present invention. For example, support material102can be formed to have circular shapes, triangular shapes, quadrilateral shapes, pentagonal shapes, and other polygonal shapes.

Referring now toFIG. 8, a cross-sectional side view of multi-chip module100further along in manufacture is illustrated. A semiconductor chip104is placed on support material102. More particularly, semiconductor chip104has a backside106that is placed on support material102and a front side108that has a plurality of bonding pads110formed thereon. Pressure is applied to semiconductor chip104to position it in support material102and to urge support material102over edges53and55of spacer50and into the region between surfaces44and106. A portion of support material102remains on spacer50and a portion of support material102substantially fills the region between surfaces44and106. Because support material102substantially fills the region between surfaces44and106, the peripheral portions112of semiconductor chip104do not overhang freely, but are supported. Thus, peripheral portions112do not significantly bounce during a subsequent wirebonding step. Support material102is cured by being heated to a temperature ranging from about 100° C. to about 175° C. for a time ranging from about 5 minutes to about 60 minutes. An advantage of placing support material102between surfaces44and106is that it improves the manufacturability and reliability of wirebonds formed in multi-level semiconductor packaging structures.

A plurality of bonding pads110are electrically connected to corresponding bonding pads of plurality of bonding pads20using, for example, a wirebonding process. More particularly, bonding pad110A is electrically connected to bonding pad20A by an interconnect wire114A and bonding pad110B is electrically connected to bonding pad20B by an interconnect wire114B. For clarity of description, only two interconnect wires, i.e., interconnect wires114A and114B, of a plurality of interconnect wires are shown inFIG. 8.

Referring now toFIG. 9, a protective covering116is formed over semiconductor chip104, interconnect wires56A,56B,114A, and114B, and BGA support substrate12. Protective covering116illustrated inFIG. 9is a lid secured to BGA support substrate12by a lid attach material118. It should be understood that the type of protective covering is not limited to being a lid. For example, protective covering114may be a glob top material or other suitable protective material.

By now it should be appreciated that a multi-chip module having vertically stacked semiconductor chips and a method for manufacturing the multi-chip module been provided. An advantage of multi-chip modules in accordance with the present invention is that it provides a means for decreasing vibration or bounce of regions of a semiconductor chip during a wirebonding process. This improves the reliability of the wirebonds and decreases catastrophic device failure. Another advantage of the present invention is that it increases the variety in the sizes of the semiconductor chips that can be bonded to a spacer. Because the support material provides additional support for the semiconductor chip, larger chips can be mounted to the spacer. In addition, the method is readily integrable into multi-chip module processing flows in a cost and time efficient manner.

Although certain preferred embodiments and methods have been disclosed herein, it will be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. For example, the support material may be disposed on the spacer and the first semiconductor chip. Alternatively, an adhesive film can be used to couple semiconductor chip64to spacer50rather than using a die attach material such as die attach material48. An advantage of using an adhesive material is that an adhesive material does not have to be cured. It is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of applicable law.