SEMICONDUCTOR PACKAGE AND METHOD OF TESTING THE SAME

A semiconductor package includes a substrate. A first semiconductor chip is on the substrate and includes a first semiconductor substrate and a plurality of first test pads on a top surface of the first semiconductor substrate. A second semiconductor chip is on the first semiconductor chip and includes a second semiconductor substrate and a second test pad on a bottom surface of the second semiconductor substrate. The first semiconductor chip and the second semiconductor chip are bonded to each other. The plurality of first test pads face the second test pad. The second test pad has a circular ring shape when viewed in plan. The plurality of first test pads are arranged along a circumference of the second test pad. Areas that the plurality of first test pads overlap the second test pad have same sizes as each other.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2023-0124051, filed on Sep. 18, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.

1. TECHNICAL FIELD

Embodiments of the present inventive concept relate to a semiconductor package and a method of testing the same.

2. DISCUSSION OF RELATED ART

In the semiconductor industry, integrated circuit packaging technology has been developed to be applied to small-form-factor devices and to provide high package reliability. For instance, package techniques capable of achieving a chip-sized package are actively being developed to provide small-form-factor devices. Additionally, package techniques capable of increasing efficiency in a package process and increasing mechanical and electrical reliability of a package product have attracted considerable attention.

In the semiconductor industry, there has been an increased demand for semiconductor devices and electronic products having a high capacity, thinness, and small size. One package technique that has been suggested is a packaging technique which vertically stacks a plurality of semiconductor chips to achieve a high density chip stacking. This packaging technique has an advantage of integrating semiconductor chips having various functions on a relatively small area as compared to a conventional package consisting of one semiconductor chip.

As a semiconductor process becomes finer and more complicated, it is essential to test defects produced on a semiconductor device. The test of defects on the semiconductor package increases the reliability of the semiconductor package and increases a process yield.

SUMMARY

Some embodiments of the present inventive concept provide a semiconductor package having a sufficient joint.

Some embodiments of the present inventive concept provide a method of testing a semiconductor package that causes no damage to the semiconductor package and has a high accuracy.

According to an embodiment of the present inventive concept, a semiconductor package includes a substrate. A first semiconductor chip is on the substrate and includes a first semiconductor substrate and a plurality of first test pads on a top surface of the first semiconductor substrate. A second semiconductor chip is on the first semiconductor chip and includes a second semiconductor substrate and a second test pad on a bottom surface of the second semiconductor substrate. The first semiconductor chip and the second semiconductor chip are bonded to each other. The plurality of first test pads face the second test pad. The second test pad has a circular ring shape when viewed in plan. The plurality of first test pads are arranged along a circumference of the second test pad. Areas that the plurality of first test pads overlap the second test pad have same sizes as each other.

According to an embodiment of the present inventive concept, a semiconductor package includes a substrate. A first semiconductor chip is on the substrate. A second semiconductor chip is on the first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate. A first circuit layer is on a bottom surface of the first semiconductor substrate. A plurality of first test pads is on a top surface of the first semiconductor substrate. A plurality of external pads is on the bottom surface of the first semiconductor substrate. A plurality of through vias vertically penetrates the first semiconductor substrate to connect the plurality of first test pads to the external pads. The second semiconductor chip includes a second semiconductor substrate. A second circuit layer is on a bottom surface of the second semiconductor substrate. A second test pad is on the bottom surface of the second semiconductor substrate. Each of the plurality of first test pads partially overlaps the second test pad. The plurality of first test pads are arranged at a same interval. The plurality of first test pads and the second test pad are electrically insulated from the first circuit layer and the second circuit layer. Each of the external pads is electrically connected through the through via to one of the plurality of first test pads.

According to an embodiment of the present inventive concept, a method of testing a semiconductor package includes forming a wiring pattern in a first semiconductor substrate and a plurality of first test pads on a top surface of the first semiconductor substrate. The plurality of first test pads are electrically connected to the wiring pattern. Each of the plurality of first test pads has a circular shape when viewed in plan. A second test pattern is formed on a bottom surface of the second semiconductor substrate. The second test pad has a circular ring shape when viewed in plan. The first semiconductor substrate and the second semiconductor substrate are bonded to each other. The plurality of first test pads face the second pad after the bonding to each other. The plurality of first test pads are arranged along a circumference of the second test pad. Each of the plurality of first test pads partially overlaps the second test pad. A plurality of external pads is formed on a bottom surface of the first semiconductor substrate. Each of the external pads are electrically connected through the wiring pattern to one of the plurality of first test pads. Two of the external pads are used to measure an electrical resistance of a test path. The electrical resistance of the test path is compared with a reference resistance.

DETAILED DESCRIPTION OF EMBODIMENTS

The following will now describe a semiconductor package according to the present inventive concept with reference to the accompanying drawings.

FIG.1illustrates a cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concept. For convenience of description, some components may be omitted or components may be merged into a single configuration inFIG.1.FIG.2illustrates an enlarged view showing a portion ofFIG.1.

A semiconductor package according to some embodiments of the present inventive concept may be a stacked package in which vias are used. For example, semiconductor chips of the same type may be stacked on a base substrate, and the semiconductor chips may be electrically connected to each other through vias that penetrate therethrough. The semiconductor chips may be bonded to each other through respective pads that face each other.

Referring toFIGS.1and2, a semiconductor package may include a first semiconductor chip100and a second semiconductor chip200that are stacked on each other.

The first semiconductor chip100may be provided. The first semiconductor chip100may include an integrated circuit therein. For example, in an embodiment the first semiconductor chip100may be a wafer-level die formed of a semiconductor, such as silicon (Si). In an embodiment, the first semiconductor chip100may include a first semiconductor substrate110, a first circuit layer120, first vias130, first upper pads140, a first upper protection layer150, first lower pads160, a first lower protection layer170, and a redistribution layer180.

The first semiconductor substrate110may be provided. The first semiconductor substrate110may include a semiconductor material. For example, in an embodiment the first semiconductor substrate110may be a silicon (Si) monocrystalline substrate.

The first semiconductor substrate110may have a device region DR and an edge region ER that are spaced apart from each other. In an embodiment, when viewed in plan, the device region DR may be positioned on a central portion of the first semiconductor substrate110, and the edge region ER may surround the device region DR. The device region DR may be a region on which semiconductor devices of the first semiconductor chip100is provided on the central portion of the first semiconductor substrate110. The edge region ER may be a test region on which patterns are provided for testing a joint between the semiconductor chips100and200on a zone where the semiconductor devices are not provided on the first semiconductor substrate110. The first semiconductor substrate110may have a top surface and a bottom surface that are opposite to each other. The bottom surface of the first semiconductor substrate110may be a front surface of the first semiconductor substrate110, and the top surface of the first semiconductor substrate110may be a rear surface of the first semiconductor substrate110. In this description, the front surface of the first semiconductor substrate110may be defined to indicate a surface on which semiconductor devices are formed or mounted in the first semiconductor substrate110or on which wiring lines and pads are formed in the first semiconductor substrate110, and the rear surface of the first semiconductor substrate110may be defined to indicate a surface opposite to the front surface. For example, the bottom surface of the first semiconductor substrate110may be an active surface.

The first semiconductor chip100may have the first circuit layer120provided on the bottom surface of the first semiconductor substrate110. The first circuit layer120may include a first semiconductor device122and a first device wiring part124.

On the device region DR of the first semiconductor substrate110, the first semiconductor device122may include transistors TR provided on the bottom surface of the first semiconductor substrate110. For example, the transistors TR may each include a source and a drain that are formed on a lower portion of the first semiconductor substrate110, a gate electrode disposed on the bottom surface of the first semiconductor substrate110, and a gate dielectric layer interposed between the first semiconductor substrate110and the gate electrode.FIG.2depicts that one transistor TR is provided. However, embodiments of the present inventive concept are not necessarily limited thereto. The first semiconductor device122may include a plurality of transistors TR. In an embodiment, the first semiconductor device122may include a logic circuit or a memory circuit. In an embodiment, on the device region DR, the first semiconductor device122may include a device isolation pattern, a logic cell or a plurality of memory cells on the bottom surface of the first semiconductor substrate110. Alternatively, in an embodiment the first semiconductor device122may include a passive device, such as a capacitor. The first semiconductor device122may not be disposed on the edge region ER of the first semiconductor substrate110.

The bottom surface of the first semiconductor substrate110may be covered with a first device interlayer dielectric layer126. On the device region DR, the first device interlayer dielectric layer126may bury the first semiconductor device122. The first device interlayer dielectric layer126may downwardly cover the first semiconductor device122. For example, the first semiconductor device122may not be exposed by the first device interlayer dielectric layer126. In an embodiment, the first device interlayer dielectric layer126may include, for example, at least one selected from silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). Alternatively, the first device interlayer dielectric layer126may have a low-k dielectric material. The first device interlayer dielectric layer126may have a mono-layered structure or a multi-layered structure. In an embodiment in which the first device interlayer dielectric layer126is provided as the multi-layered structure, subsequently described wiring layers may be provided in each dielectric layer, and an etch stop layer may be interposed between the dielectric layers. For example, the etch stop layer may be provided on a bottom surface of each dielectric layer. In an embodiment, the etch stop layer may include, for example, one of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN).

On the device region DR, the first device interlayer dielectric layer126may be provided therein with the first device wiring part124connected to the transistors TR. The first device wiring part124may include signal wiring patterns buried in the first device interlayer dielectric layer126. For example, in an embodiment the signal wiring patterns may include redistribution patterns for horizontal wiring and via patterns for vertical connection. The first device wiring part124may vertically penetrate the first device interlayer dielectric layer126to come into connection with (e.g., electrical connection therewith) one of a source electrode, a drain electrode, and a gate electrode of the transistor TR. Alternatively, the first device wiring part124may be connected to various components of the first semiconductor device122. The first device wiring part124may be positioned between top and bottom surfaces of the first device interlayer dielectric layer126. The first device wiring part124may not be positioned on the edge region ER. In an embodiment, the first device wiring part124may include, for example, copper (Cu) or tungsten (W).

FIG.2depicts that one wiring layer is provided in the first device interlayer dielectric layer126. However, embodiments of the present inventive concept are not necessarily limited thereto. According to some embodiments, a plurality of wiring layers may be provided in the first device interlayer dielectric layer126. The following description will focus on the embodiment ofFIG.2for convenience of explanation.

First and second lower connection patterns127and128may be provided in a lower portion of the first device interlayer dielectric layer126. In an embodiment, the first and second lower connection patterns127and128may have bottom surfaces that are exposed on the bottom surface of the first device interlayer dielectric layer126. In an embodiment, the bottom surfaces of the first and second lower connection patterns127and128may be coplanar with the bottom surface of the first device interlayer dielectric layer126. The first lower connection patterns127may be disposed on the device region DR. One of the first lower connection patterns127may be connected to (e.g., electrically connected thereto) the first device wiring part124. The second lower connection patterns128may be disposed on the edge region ER. The second lower connection patterns128may be electrically insulated from the first semiconductor device122and the first device wiring part124. In an embodiment, the first and second lower connection patterns127and128may include, for example, copper (Cu) or tungsten (W).

The first vias130may be arranged to vertically penetrate the first semiconductor substrate110to come into connection with the first lower connection patterns127. The first vias130may be patterns for vertical wiring. On the device region DR, one of the first vias130may vertically penetrate the first device interlayer dielectric layer126on the device region DR to be coupled to a top surface of one of the first lower connection patterns127. On the edge region ER, another of the first vias130may vertically penetrate the first device interlayer dielectric layer126to be coupled to a top surface of one of the second lower connection patterns128. The first vias130may vertically penetrate the first device interlayer dielectric layer126and the first semiconductor substrate110to be exposed on the top surface of the first semiconductor substrate110. In an embodiment, the first vias130may include, for example, tungsten (W).

The first lower pads160may be disposed on the first device interlayer dielectric layer126. The first lower pads160may be disposed on the bottom surfaces of the first and second lower connection patterns127and128and may directly contact the first and second lower connection patterns127,128. The first lower pads160may be disposed on a bottom surface of the first semiconductor substrate110. The first lower pads160may be coupled to the bottom surfaces of the first and second lower connection patterns127and128of the first device wiring part124. For example, the first and second lower connection patterns127and128may be under pads of the first lower pads160. In an embodiment, the first lower pads160may have plate shapes. According to some embodiments, the first lower pads160may each have a T-shaped cross-section including a via portion and a pad portion on the via portion in which via and pad portions are connected into a single unitary piece. The first lower pads160may include a metallic material. For example, in an embodiment the first lower pads160may include copper (Cu).

The first lower protection layer170may be disposed on (e.g., disposed directly thereon) the first device interlayer dielectric layer126. On the bottom surface of the first device interlayer dielectric layer126, the first lower protection layer170may cover the first and second lower connection patterns127and128. On the bottom surface of the first device interlayer dielectric layer126, the first lower protection layer170may surround the first lower pads160, such as lateral side surfaces of the first lower pads160. The first lower pads160, such as an upper surface of the first lower pads160, may be exposed by the first lower protection layer170. For example, when viewed in plan, the first lower protection layer170may surround, but not directly contact, upper surfaces of the first lower pads160. The first lower protection layer170may have a bottom surface coplanar with those of the first lower pads160. In an embodiment, the first lower protection layer170may include one of silicon nitride (SiN), silicon oxide (SiO), silicon carboxide (SiOC), silicon oxynitride (SiON), and silicon carbonitride (SiCN).

The first lower pads160may be external pads for outwardly mounting the semiconductor package. For example, in an embodiment external terminals102may be provided on the first lower pads160. The external terminals102may be coupled to the first lower pads104. In some embodiments, the external terminals102may include a solder ball or a solder bump, and based on type and arrangement of the external terminals102, the semiconductor package may be provided in the shape of one of a ball grid array (BGA) type, a fine ball-grid array (FBGA) type, and a land grid array (LGA) type.

The redistribution layer180may be disposed on (e.g., disposed directly thereon) the top surface of the first semiconductor substrate110. In an embodiment, the redistribution layer180may include first and second upper connection patterns184and186and a first redistribution dielectric pattern182.

The first redistribution dielectric pattern182may be disposed on (e.g., disposed directly thereon) the top surface of the first semiconductor substrate110. In an embodiment, the first redistribution dielectric pattern182may include one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON).

On the device region DR, the first upper connection patterns184may be disposed in the first redistribution dielectric pattern182. Some of the first upper connection patterns184may be connected to the first vias130. For example, some of the first vias130may vertically penetrate the first semiconductor substrate110to be coupled to (e.g., directly coupled thereto) bottom surfaces of the first upper connection patterns184. The first upper connection patterns184may not be positioned on the edge region ER. In an embodiment, the first upper connection patterns184may include, for example, copper (Cu) or tungsten (W).

On the edge region ER, the second upper connection patterns186may be provided in the first redistribution dielectric pattern182. The second upper connection patterns186may be located at the same level as that of the first upper connection patterns184, and may include the same material as that of the first upper connection patterns184. For example, in an embodiment the first and second upper connection patterns184and186may be patterned by patterning a metal layer. The second upper connection patterns186may be electrically insulated from the first semiconductor device122and the first device wiring part124. In addition, the second upper connection patterns186may be electrically insulated from other devices and wiring lines provided in the semiconductor package. Each of the second upper connection patterns186may be connected through the first via130to one of the second lower connection patterns128. For example, the second upper connection patterns186and the second lower connection patterns128may be electrically floated in the semiconductor package. The second upper connection patterns186may not be disposed on the device region DR of the first semiconductor substrate110. In an embodiment, the second upper connection patterns186may include, for example, copper (Cu) or tungsten (W).

The first and second upper connection patterns184and186may have top surfaces that are exposed on a top surface of the first redistribution dielectric pattern182. For example, the top surfaces of the first and second upper connection patterns184and186may be coplanar with the top surface of the first redistribution dielectric pattern182. In an embodiment, the top surfaces of the first and second upper connection patterns184and186may be substantially flat, and likewise the top surface of the first redistribution dielectric pattern182may be substantially flat.

The first upper pads140may be disposed on (e.g., disposed directly thereon) the redistribution layer180. In an embodiment, the first upper pads140may include upper signal pads TSP and upper test pads TTP disposed on a top surface of the first semiconductor substrate110.

The upper signal pads TSP may be disposed on the device region DR. The upper signal pads TSP may be disposed on (e.g., disposed directly thereon) top surfaces of the first upper connection patterns184. The first upper connection patterns184may be under pads of the upper signal pads TSP. The first upper connection patterns184may electrically connect the first semiconductor device122to the upper signal pads TSP.

The upper test pads TTP may be disposed on the edge region ER. The upper test pads TTP may be disposed on (e.g., disposed directly thereon) top surfaces of the second upper connection patterns186. The second upper connection patterns186may be under pads of the upper test pads TTP. The following will describe in detail a shape and arrangement of the upper test pads TTP together with a lower test pad BTP of the second semiconductor chip200which will be discussed below. The upper test pads TTP may be electrically insulated from the first semiconductor device122and the first device wiring part124. When viewed in cross section, an interval between the upper test pads TTP may be less than that between the upper signal pads TSP. For example, the distance between adjacent upper test pads TTP may be less than the distance between adjacent upper signal pads TSP.

In an embodiment, the first upper pads140may have plate shapes. The first upper pads140may each have a width that decreases as the distance from the first semiconductor substrate110decreases. According to an embodiment, the first upper pads140may each have a T shaped cross-section including a via portion and a pad portion on the via portion. In an embodiment, the via and pad portions are connected into a single unitary piece. The first upper pads140may include a metallic material. For example, in an embodiment the first upper pads140may include copper (Cu).

The first upper protection layer150may be disposed on (e.g., disposed directly thereon) the redistribution layer180. On a top surface of the redistribution layer180, the first upper protection layer150may cover the first and second upper connection patterns184and186. On the top surface of the redistribution layer180, the first upper protection layer150may surround the first upper pads140, such as lateral side surfaces of the first upper pads140. The first upper pads140, such as upper surfaces of the first upper pads140, may be exposed by the first upper protection layer150. For example, when viewed in plan, the first upper protection layer150may surround, but not directly contact, upper surfaces of the first upper pads140. The first upper protection layer150may have a top surface coplanar with top surfaces of the first upper pads140. In an embodiment, the first upper protection layer150may include one of high density plasma (HDP) oxide, undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), silicon nitride (SiN), silicon oxide (SiO), silicon carboxide (SiOC), silicon oxynitride (SiON), and silicon carbonitride (SiCN). The first upper protection layer150may have a mono-layered structure or a multi-layered structure.

The second semiconductor chip200may have a structure substantially similar to that of the first semiconductor chip100. For example, the second semiconductor chip200may include a second semiconductor substrate210, a second circuit layer220, second lower pads260, and a second lower protection layer270. In an embodiment, the second semiconductor chip200may not include a second via, a second upper pad, a second upper protection layer, and a second redistribution layer. However, embodiments of the present inventive concept are not necessarily limited thereto. According to some embodiments, the second semiconductor chip200may include at least one selected from a second via, a second upper protection layer, and a redistribution layer.

The second semiconductor substrate210may be provided. The second semiconductor substrate210may include a semiconductor material.

The second circuit layer220may be provided on (e.g., disposed directly on) a bottom surface of the second semiconductor substrate210. The second circuit layer220may include a second semiconductor device222and a second device wiring part224. In an embodiment, on the device region DR of the second semiconductor substrate210, the second semiconductor device222may include transistors TR provided on the bottom surface of the second semiconductor substrate210. The second semiconductor device222may not be disposed on the edge region ER of the second semiconductor substrate210. The bottom surface of the second semiconductor substrate210may be covered with a second device interlayer dielectric layer226. On the device region DR, the second device interlayer dielectric layer226may bury the second semiconductor device222. On the device region DR, the second device interlayer dielectric layer226may be provided therein with the second device wiring part224connected to the transistors TR.

Third lower connection patterns227may be provided in a lower portion of the second device interlayer dielectric layer226. The third lower connection patterns227may have bottom surfaces that are exposed on a bottom surface of the second device interlayer dielectric layer226. The third lower connection patterns227may be disposed on the device region DR. The third lower connection patterns227may be connected to the second device wiring part224.

The second lower pads260may be disposed on (e.g., disposed directly thereon) the second device interlayer dielectric layer226. In an embodiment, the second lower pads260may include lower signal pads BSP and a lower test pad BTP.

The lower signal pads BSP may be disposed on the device region DR. The lower signal pads BSP may be disposed on (e.g., disposed directly thereon) the bottom surfaces of the third lower connection patterns227. The lower signal pads BSP may be electrically connected to the second semiconductor device222. For example, as shown inFIG.2, on the device region DR, the lower signal pads BSP may be coupled to (e.g., directly coupled thereto) the bottom surfaces of the third lower connection patterns227included in the second device wiring part224. For example, the third lower connection patterns227may be under pads of the lower signal pads BSP. The third lower connection patterns227may electrically connect the second semiconductor device222to the lower signal pads BSP.

The lower test pad BTP may be disposed on the edge region ER. The lower test pad BTP may be located at the same level as that of the lower signal pads BSP. The following will describe in detail a shape and arrangement of the lower test pad BTP together with the upper test pads TTP of the first semiconductor chip100. The lower test pad BTP may be electrically insulated from the second semiconductor device222and the second device wiring part224.

The second lower protection layer270may be disposed on (e.g., disposed directly thereon) the second device interlayer dielectric layer226. On the bottom surface of the second device interlayer dielectric layer226, the second lower protection layer270may cover the third lower connection patterns227. On the bottom surface of the second device interlayer dielectric layer226, the second lower protection layer270may surround the second lower pads260. The second lower pads260, such as upper surfaces of the second lower pads260, may be exposed by the second lower protection layer270. For example, when viewed in plan, the second lower protection layer270may surround, but not directly contact, upper surfaces of the second lower pads260. The second lower protection layer270may have a bottom surface coplanar with those of the second lower pads260. In an embodiment, the second lower protection layer270may include one of silicon nitride (SiN), silicon oxide (SiO), silicon carboxide (SiOC), silicon oxynitride (SiON), and silicon carbonitride (SiCN).

The second semiconductor chip200may be disposed on the first semiconductor chip100. In an embodiment, the first upper pads140of the first semiconductor chip100may be vertically aligned with the second lower pads260of the second semiconductor chip200. The first semiconductor chip100and the second semiconductor chip200may be in direct contact with each other.

On an interface between the first semiconductor chip100and the second semiconductor chip200, the first upper protection layer150of the first semiconductor chip100may be bonded to the second lower protection layer270of the second semiconductor chip200. In an embodiment, the first upper protection layer150and the second lower protection layer270may constitute a hybrid bonding of oxide, nitride, or oxynitride. In this description, the term “hybrid bonding” may denote a bonding in which two components of the same kind are merged at an interface therebetween. For example, the first upper protection layer150and the bonded second lower protection layer270may have a continuous configuration and there may be no visible interface therebetween. For example, the first upper protection layer150and the second lower protection layer270may be formed of the same material, and no interface may be present between the first upper protection layer150and the second lower protection layer270. Thus, the first upper protection layer150and the second lower protection layer270may be provided as one integral component. For example, the first upper protection layer150and the second lower protection layer270may be combined to constitute a single unitary piece. The present inventive concept, however, are not necessarily limited thereto. For example, in an embodiment the first upper protection layer150and the second lower protection layer270may be formed of different materials. In this embodiment, the first upper protection layer150and the second lower protection layer270may not have a continuous, integral configuration and there may be a visible interface therebetween.

The first semiconductor chip100may be connected to the second semiconductor chip200. For example, the first semiconductor chip100and the second semiconductor chip200may be in direct contact with each other. On the interface between the first semiconductor chip100and the second semiconductor chip200, the first upper pads140of the first semiconductor chip100may be bonded to (e.g., directly bonded thereto) the second lower pads260of the second semiconductor chip200. For example, the upper signal pads TSP of the first semiconductor chip100may be bonded to (e.g., directly bonded thereto) the lower signal pads BSP of the second semiconductor chip200, and the upper test pads TTP of the first semiconductor chip100may be bonded to (e.g., directly bonded thereto) the lower test pads BTP of the second semiconductor chip200. In this configuration, the first upper pad140and the second lower pad260may constitute an intermetallic hybrid bonding. For example, the first upper pad140and its bonded second lower pad260may have a continuous configuration and there may be no visible interface therebetween. For example, the first upper pads140and the second lower pads260may be formed of the same material and may have no interface therebetween. Therefore, the first upper pad140and the second lower pad260may be provided as one component. For example, the first upper pad140and the second lower pad260may be combined to constitute a single unitary piece.

As the first semiconductor chip100is bonded to the second semiconductor chip200, on the edge region ER, the upper test pads TTP of the first semiconductor chip100may be electrically connected to the lower test pad BTP of the second semiconductor chip200. In this embodiment, the upper test pads TTP of the first semiconductor chip100and the lower test pad BTP of the second semiconductor chip200may be combined to constitute a test structure TS. A configuration of the test structure TS will be discussed in detail below.

FIG.3illustrates a perspective view showing a test structure.FIGS.4to6illustrate plan views showing a test structure ofFIG.3when viewed from above.

Referring toFIGS.3and4, in an embodiment the lower test pad BTP may have a circular ring shape when viewed in plan.FIG.3depicts that the lower test pad BTP has a uniform width. However, embodiments of the present inventive concept are not necessarily limited thereto. According to some embodiments, the width of the lower test pad BTP may increase with decreasing distance from the upper test pads TTP. The width of the lower test pad BTP may indicate a distance from inner to outer lateral surfaces of the lower test pad BTP.

Each of the upper test pads TTP may have a circular shape when viewed in plan. For example, in an embodiment the upper test pads TTP may each have a cylindrical shape.FIG.3depicts that each of the upper test pads TTP has a uniform width. However, embodiments of the present inventive concept are not necessarily limited thereto. According to some embodiments, the width of each of the upper test pads TTP may increase with decreasing distance from the lower test pad BTP. In this description, the width of the upper test pad TTP may indicate a diameter of the upper test pad TTP. The upper test pads TTP may have their top surfaces whose shapes are the same as each other. For example, the top surfaces of the upper test pads TTP may have the same area size.

The upper test pads TTP may be arranged along a circumference of the lower test pad BTP. For example, the upper test pads TTP may be arranged in a circular shape. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment the upper test pads TTP may be arranged along the inner lateral surface of the lower test pad BTP. In an embodiment, there may be a regular interval between adjacent upper test pads TTP. In an embodiment, an interval between adjacent upper test pads TTP may be less than an interval between adjacent upper signal pads TSP. In an embodiment shown inFIG.4, twelve upper test pads TTP may be provided. However, embodiments of the present disclosure are not necessarily limited thereto. Thus, the upper test pads TTP may be disposed on opposite sides in a first direction X of the lower test pad BTP, opposite sides in a second direction Y of the lower test pad BTP, and opposite sides of each of third, fourth, fifth, and sixth directions D1, D2, D3, and D4of the lower test pad BTP. In this description, the first direction X and the second direction Y may be directions orthogonal to each other, and the third, fourth, fifth, and sixth directions D1, D2, D3, and D4may be directions having an interval angle of about 60 degrees with respect to the first direction X and the second direction Y. A regular interval may be provided between the upper test pads TTP when viewed in cross section taken along the first to sixth directions X, Y, D1, D2, D3, and D4. For example, the same interval may be provided between the upper test pads TTP that stand opposite to each other in the first direction X, between the upper test pads TTP that stand opposite to each other in the second direction Y, between the upper test pads TTP that stand opposite to each other in the third direction D1, between the upper test pads TTP that stand opposite to each other in the fourth direction D2, between the upper test pads TTP that stand opposite to each other in the fifth direction D3, and between the upper test pads TTP that stand opposite to each other in the sixth direction D4.

According to some embodiments, eight upper test pads TTP may be provided along the circumference of the lower test pad BTP. As illustrated inFIG.5, the upper test pads TTP may be disposed on opposite sides in the first direction X of the lower test pad BTP, opposite sides in the second direction Y of the lower test pad BTP, and opposite sides of each of seventh and eighth directions D5and D6of the lower test pad BTP. In this description, the seventh and eighth directions D5and D6may be directions having an interval angle of about 45 degrees with respect to the first direction X and the second direction Y.

According to some embodiments, four upper test pads TTP may be provided along the circumference of the lower test pad BTP. As illustrated inFIG.6, the upper test pads TTP may be disposed on opposite sides in the first direction X of the lower test pad BTP and opposite sides in the second direction Y of the lower test pad BTP.

FIGS.4to6depict that four, eight, or twelve upper test pads TTP are provided along the circumference of the lower test pad BTP. However, embodiments of the present inventive concept are not necessarily limited thereto. For example, in an embodiment, four to sixteen upper test pads TTP may be provided at a regular interval along the circumference of the lower test pad BTP. The following description will focus on the embodiment ofFIG.4.

Each of the upper test pads TTP may partially overlap the lower test pad BTP (e.g., in a vertical direction). In an embodiment, the same overlapping area size may be provided between the lower test pad BTP and each of the upper test pads TTP. Therefore, the same interfacial resistance may be present between the lower test pad BTP and each of the upper test pads TTP. In an embodiment, the overlapping area size between the lower test pad BTP and each of the upper test pads TTP may be in a range of about 10% to about 30% of an area size of each of the upper test pads TTP.

Each of the upper test pads TTP may be connected to the first lower pad160through a wiring pattern in the first semiconductor chip100, or through the second upper connection pattern186, the first via130, and the second lower connection pattern128. In an embodiment, as the upper test pads TTP are bonded to the lower test pad BTP, one of the first lower pads160may be electrically connected to the lower test pad BTP through one of the second lower connection patterns128, one of the first vias130, one of the second upper connection patterns186, and one of the upper test pads TTP, and in addition may be electrically connected to another of the first lower pads160through the lower test pad BTP, another of the upper test pads TTP, another of the second upper connection patterns186, another of the first vias130, and another of the second lower connection patterns128. In an embodiment, the first lower pads160electrically connected to the lower test pad BTP may be pads for inputting signals in a process where the bonding between the first and second semiconductor chips100and200is tested. This will be further discussed below in detail in describing a method of testing a semiconductor package.

In the embodiments that follow, a detailed description of technical features repetitive to those discussed above with reference toFIGS.1to6may be omitted, and a difference thereof will be discussed in detail for economy of description. The same reference numerals may be allocated to the same components as those of the semiconductor package discussed above according to some embodiments of the present inventive concept.

FIGS.7to9illustrate plan views showing a test structure.

FIGS.4to6depict that the lower test pad BTP has a circular ring shape when viewed in plan. However, embodiments of the present inventive concept are not necessarily limited thereto.

As illustrated inFIG.7, the lower test pad BTP may have a circular shape when viewed in plan. For example, in an embodiment the lower test pad BTP may have a cylindrical shape. The upper test pads TTP may be arranged along a circumference of the lower test pad BTP. Each of the upper test pads TTP may partially overlap the lower test pad BTP (e.g., in a vertical direction).

Alternatively, as illustrated inFIG.8, in an embodiment the lower test pad BTP may have a tetragonal ring shape when viewed in plan. In this embodiment, four upper test pads TTP may be provided along the circumference of the tetragonal ring shape of the lower test pad BTP. Each of the upper test pads TTP may be disposed adjacent to one of outer lateral surfaces of the lower test pad BTP. Each of the upper test pads TTP may partially overlap the lower test pad BTP (e.g., in a vertical direction).

Alternatively, as illustrated inFIG.9, in an embodiment the lower test pad BTP may have a octagonal ring shape when viewed in plan. In this embodiment, eight upper test pads TTP may be provided along the circumference of the octagonal ring shape of the lower test pad BTP. Each of the upper test pads TTP may be disposed adjacent to one of outer lateral surfaces of the lower test pad BTP. Each of the upper test pads TTP may partially overlap the lower test pad BTP (e.g., in a vertical direction).

Some examples of the lower test pad BTP are explained with reference toFIGS.7to9. However, embodiments of the present inventive concept are not necessarily limited thereto. According to some embodiments, when viewed in plan, the lower test pad BTP may have a polygonal ring shape that has four or more outer lateral surfaces. In an embodiment, the upper test pads TTP may be provided in the same number as that of the outer lateral surfaces of the lower test pad BTP. Each of the upper test pads TTP may be disposed adjacent to one of the outer lateral surfaces of the lower test pad BTP. Each of the upper test pads TTP may partially overlap the lower test pad BTP. Alternatively, when viewed in plan, the lower test pad BTP may have a circular, polygonal, or any other closed curved shape.

FIG.10illustrates a cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concept.

Referring toFIG.10, a first semiconductor chip100may be provided. The first semiconductor chip100in an embodiment shown inFIG.10may be similar to the first semiconductor chip100discussed with reference to an embodiment shown inFIG.1. In an embodiment, the first semiconductor chip100may be a logic chip. Alternatively, the first semiconductor chip100may be a memory chip or a semiconductor chip (e.g., a buffer chip) devoid of an electronic device, such as a transistor.

The first upper pads140of the first semiconductor chip100may further include upper connection pads TCP. The upper connection pads TCP may be disposed on the edge region ER. The upper connection pads TCP may be disposed to be spaced apart from the upper test pads TTP (e.g., in a vertical direction). The upper connection pads TCP may be electrically connected through the first vias130to the first lower pads160.

A second semiconductor chip200may be provided. The second semiconductor chip200in an embodiment ofFIG.10may be similar to the second semiconductor chip200discussed with reference to an embodiment ofFIG.1. The second semiconductor chip200may have a width (e.g., length in a direction parallel to an upper surface of the first semiconductor chip100) less than a width of the first semiconductor chip100(e.g., length in a direction parallel to an upper surface of the first semiconductor chip100). In an embodiment, the second semiconductor chip200may further include second vias230, the second upper pads240, and a second upper protection layer250.

In an embodiment, the second lower pads260may further include lower connection pads BCP. The lower connection pads BCP may be disposed on the edge region ER. The lower connection pads BCP may be disposed to spaced apart from the lower test pads BTP (e.g., in a vertical direction). On an interface between the first semiconductor chip100and the second semiconductor chip200, each of the lower connection pads BCP may be bonded to (e.g., directly bonded thereto) one of the upper connection pads TCP.

The second vias230may be provided to vertically penetrate the second semiconductor substrate210to come into connection with (e.g., direct connection therewith) a circuit layer of the second semiconductor chip200. The second vias230may be patterns for vertical wiring. Some of the second vias230may be electrically connected to the upper signal pads TSP on the device region DR. Others of the second vias230may be electrically connected to the lower connection pads BCP on the edge region ER.

The second upper pads240may be disposed on the second semiconductor substrate210. In an embodiment, the second upper pads240may include upper signal pads TSP and upper test pads TTP.

The upper signal pads TSP may be disposed on the device region DR. The upper signal pads TSP may be electrically connected through the second vias230to a circuit layer of the second semiconductor chip200.

The upper test pads TTP may be disposed on the edge region ER. The upper test pads TTP may be electrically connected through the second vias230to the lower connection pads BCP. The upper test pads TTP may be electrically insulated from the circuit layer of the second semiconductor chip200.

The second upper protection layer250may be disposed on (e.g., disposed directly thereon) the second semiconductor substrate210. The second upper protection layer250may surround the second upper pads240, such as lateral sides of the second upper pads240. The second upper pads240, such as an upper surface of the second upper pads240may be exposed by the second upper protection layer250. For example, when viewed in plan, the second upper protection layer250may surround, but not contact, an upper surface of the second upper pads240. The second upper protection layer250may have a top surface coplanar (e.g., in the vertical direction) with the top surface of the second upper pads240.

In an embodiment, the semiconductor package may further include a third semiconductor chip300stacked on the second semiconductor chip200. The third semiconductor chip300may have a structure substantially similar to that of the second semiconductor chip200. For example, in an embodiment the third semiconductor chip300may include a third semiconductor substrate310, a third circuit layer, third lower pads360, and a third lower protection layer370. In an embodiment, the third semiconductor chip300may not include a third via, a third upper pad, a third upper protection layer, and a third redistribution layer. However, embodiments of the present inventive concept are not necessarily limited thereto.

In an embodiment, the third circuit layer may include semiconductor devices formed on a bottom surface of the third semiconductor substrate310, a device interlayer dielectric layer that buries the semiconductor devices, and a device wiring part in the device interlayer dielectric layer and connected to the semiconductor devices. The semiconductor devices may be disposed on the device region DR.

In an embodiment, the third lower pads360may be disposed below (e.g., directly below) the third semiconductor substrate310, for example, below the third circuit layer. In an embodiment, the third lower pads360may include lower signal pads BSP and a lower test pad BTP. The lower signal pads BSP may be disposed on the device region DR. The lower signal pads BSP may be electrically connected to the semiconductor devices. The lower test pad BTP may be disposed on the edge region ER. The lower test pad BTP may be located at the same level (e.g., in the vertical direction) as that of the lower signal pads BSP. The lower test pad BTP may be electrically insulated from the semiconductor device.

The third lower protection layer370may be disposed below the third circuit layer. The third lower protection layer370may surround the third lower pads360, such as lateral sides of the third lower pads360. The third lower pads360, such as an upper surface of the third lower pads360, may be exposed by the third lower protection layer370.

The third semiconductor chip300may be disposed on the second semiconductor chip200. In an embodiment, the second upper pads240of the second semiconductor chip200may be vertically aligned with the third lower pads360of the third semiconductor chip300. The second semiconductor chip200and the third semiconductor chip300may be in direct contact with each other.

The second semiconductor chip200may be connected to the third semiconductor chip300. For example, the second and third semiconductor chips200and300may be in direct contact with each other. On an interface between the second semiconductor chip200and the third semiconductor chip300, the second upper pads240of the second semiconductor chip200may be bonded to (e.g., directly bonded thereto) the third lower pads360of the third semiconductor chip300. In an embodiment, the second upper pads240and the third lower pads360may constitute an intermetallic hybrid bonding.

As the second semiconductor chip200is bonded to the third semiconductor chip300, on the edge region ER, the upper test pads TTP of the second semiconductor chip200may be electrically connected to the lower test pad BTP of the third semiconductor chip300. In this embodiment, the upper test pads TTP of the second semiconductor chip200and the lower test pad BTP of the third semiconductor chip300may be combined to constitute a test structure.

The test structure including the upper test pads TTP of the second semiconductor chip200and the lower test pad BTP of the third semiconductor chip300shown in an embodiment ofFIG.10may be substantially the same as the test structure TS including the upper test pads TTP of the first semiconductor chip100and the lower test pad BTP of the second semiconductor chip200discussed with reference to embodiments shown inFIGS.1to9.

In an embodiment, the lower test pad BTP of the third semiconductor chip300may have a circular ring shape when viewed in plan. Each of the upper test pads TTP of the second semiconductor chip200may have a circular shape when viewed in plan. For example, each of the upper test pads TTP may have a cylindrical shape. The upper test pads TTP may be arranged along a circumference of the lower test pad BTP. Each of the upper test pads TTP may partially overlap the lower test pad BTP (e.g., in the vertical direction). In an embodiment, the same overlapping area size may be provided between the lower test pad BTP and each of the upper test pads TTP.

Each of the upper test pads TTP of the second semiconductor chip200may be connected to one of the first lower pads160through the second vias230, the lower connection pads BCP, the upper connection pads TCP, and the first vias130.

One of the first lower pads160may be electrically connected to one of the upper test pads TTP, and the first lower pads160may be electrically connected to other first lower pads160through the lower test pad BTP of the third semiconductor chip300. In an embodiment, the first lower pads160electrically connected to the lower test pad BTP of the third semiconductor chip300may be pads for inputting signals in a process where bonding between the second semiconductor chip200and the third semiconductor chip300is tested.

A molding layer400may be disposed on (e.g., disposed directly thereon) the first semiconductor chip100. In an embodiment, on a top surface of the first semiconductor chip100, the molding layer400may surround the second semiconductor chip200and the third semiconductor chip300. In an embodiment, the third semiconductor chip300may have a top surface exposed by a top surface of the molding layer400. However, embodiments of the present inventive concept are not necessarily limited thereto, and the third semiconductor chip300may be buried in the molding layer400in some embodiments. The molding layer400may include a molding member, such as an epoxy molding compound (EMC).

FIG.10depicts that two semiconductor chips200and300are stacked on the first semiconductor chip100. However, embodiments of the present inventive concept are not necessarily limited thereto. For example, according to some embodiments, three or more semiconductor chips may be stacked on the first semiconductor chip100, and two adjacent ones of the semiconductor chips may be tested for whether their bonding is good by using the upper test pads TTP and the lower test pad BTP that are in direct contact with each other on an interface between the two adjacent semiconductor chips.

FIG.11illustrates a cross-sectional view showing a semiconductor module according to some embodiments of the present inventive concept.

Referring toFIG.11, in an embodiment a semiconductor module may be, for example, a memory module including a module substrate910, a chip stack package930and a graphic processing unit940that are mounted on the module substrate910, and an outer molding layer950that covers the chip stack package930and the graphic processing unit940. The semiconductor module may further include an interposer920provided on the module substrate910.

The module substrate910may be provided. In an embodiment, the module substrate910may include a printed circuit board (PBC) having a signal pattern on a top surface thereof.

The module substrate910may be provided with module terminals912disposed thereunder (e.g., disposed directly thereunder). In an embodiment, the module terminals912may include a solder ball or a solder bump, and based on type and arrangement of the module terminals912, the semiconductor module may be provided in the shape of one of a ball grid array (BGA) type, a fine ball-grid array (FBGA) type, and a land grid array (LGA) type.

The interposer920may be provided on the module substrate910. In an embodiment, the interposer920may include first substrate pads922exposed on a top surface of the interposer920and second substrate pads924exposed on a bottom surface of the interposer920. The interposer920may redistribute the chip stack package930and the graphic processing unit940. In an embodiment, the interposer920may be flip-chip mounted on the module substrate910. For example, the interposer920may be mounted on the module substrate910through substrate terminals926provided on (e.g., disposed directly thereon) the second substrate pads924. In an embodiment, the substrate terminals926may include a solder ball or a solder bump. A first underfill layer928may be provided between the module substrate910and the interposer920(e.g., in the vertical direction).

The chip stack package930may be disposed on the interposer920. The chip stack package930in an embodiment ofFIG.11may have a structure that is the same as or similar to that of the semiconductor package discussed with reference toFIGS.1to10.FIG.11depicts that a plurality of second semiconductor chips200are provided between the first semiconductor chip and the third semiconductor chip300. However, embodiments of the present inventive concept are not necessarily limited thereto. According to some embodiments, one second semiconductor chip200is provided as shown in the embodiment ofFIG.10, or the chip stack package930include only two semiconductor chips such as the first semiconductor chip100and the second semiconductor chip200as shown in the embodiment ofFIG.1.

The chip stack package930may be mounted on the interposer920. For example, the chip stack package930may be coupled through the external terminals102of the first semiconductor chip100to the first substrate pads922of the interposer920. A second underfill layer938may be provided between the chip stack package930and the interposer920(e.g., in the vertical direction). The second underfill layer938may fill a space between the interposer920and the first semiconductor chip100and may surround the external terminals102of the first semiconductor chip100.

In an embodiment, the graphic processing unit940may be disposed on the interposer920. The graphic processing unit940may be disposed to be spaced apart from the chip stack package930(e.g., in a horizontal direction parallel to an upper surface of the module substrate910). In an embodiment, the graphic processing unit940may have a thickness (e.g., length in the vertical direction) greater than thicknesses of the semiconductor chips100,200, and300of the chip stack package930. The graphic processing unit940may include a logic circuit. For example, in an embodiment the graphic processing unit940may be a logic chip. The graphic processing unit940may be provided with bumps942on a bottom surface thereof. For example, the graphic processing unit940may be coupled through the bumps942to the first substrate pads922of the interposer920. A third underfill layer948may be provided between the interposer920and the graphic processing unit940(e.g., in the vertical direction). The third underfill layer948may surround the bumps942while filling a space between the interposer920and the graphic processing unit940.

The outer molding layer950may be provided on the interposer920. The outer molding layer950may cover the top surface of the interposer920. The outer molding layer950may encapsulate the chip stack package930and the graphic processing unit940. In an embodiment, the outer molding layer950may have a top surface located at the same level or at a higher level than that of a top surface of the chip stack package930. The outer molding layer950may include a dielectric material. For example, in an embodiment the outer molding layer950may include an epoxy molding compound (EMC).

FIGS.12A to16Aillustrate cross-sectional views showing a method of fabricating and testing a semiconductor package according to some embodiments of the present inventive concept.FIGS.12B,13B,14B,15B,15C,15D,16B, and16Cillustrate plan views showing a test structure in a method of fabricating and testing a semiconductor package.

Referring toFIGS.12A and12B, a first semiconductor substrate1000may be provided. In an embodiment, the first semiconductor substrate1000may be a wafer formed of a semiconductor, such as silicon (Si). The first semiconductor substrate1000may include device regions DR and a scribe lane region SR positioned between the device regions DR (e.g., in a horizontal direction parallel to an upper surface of the first semiconductor substrate1000). The first semiconductor substrate1000may include first semiconductor chips100. Each of the first semiconductor chips100shown in an embodiment ofFIG.12Amay have a structure that is the same as or similar to that of the first semiconductor chip100discussed with reference toFIGS.1to10. The upper test pads TTP of the first semiconductor chips100may be positioned on the scribe lane region SR. In an embodiment, the upper test pads TTP may each have a circular shape when viewed in plan. The upper test pads TTP may have top surfaces having shapes are the same as each other. The upper test pads TTP may be arranged in a circular shape.

Referring toFIGS.13A and13B, a second semiconductor substrate2000may be provided. In an embodiment, the second semiconductor substrate2000may be a wafer formed of a semiconductor, such as silicon (Si). The second semiconductor substrate2000may include device regions DR that correspond to the device regions DR of the first semiconductor substrate1000, and may also include a scribe lane region SR that corresponds to the scribe lane region SR of the first semiconductor substrate1000. The second semiconductor substrate2000may include second semiconductor chips200. Each of the second semiconductor chips200may have a structure that is the same as or similar to that of the second semiconductor chip200discussed with reference toFIGS.1to10. The lower test pad BTP of each of the second semiconductor chips200may be positioned on the scribe lane region SR. In an embodiment, the lower test pad BTP may have a circular ring shape when viewed in plan.

Referring toFIGS.14A and14B, the second semiconductor substrate2000may be mounted on the first semiconductor substrate1000. The second semiconductor substrate2000may be aligned on the first semiconductor substrate1000to allow the first upper pads140of the first semiconductor substrate1000to reside on the second lower pads260of the second semiconductor substrate2000. The second semiconductor substrate2000may be disposed on the first semiconductor substrate1000to allow the first upper pads140to directly contact the second lower pads260. In an embodiment, an annealing process may then be performed on the first and second semiconductor substrates1000and2000. The annealing process may bond (e.g., directly bond) the first upper pads140to the second lower pads260. For example, in an embodiment the first upper pad140and the second lower pad260may be combined to form a single unitary piece. The first upper pads140and the second lower pads260may be automatically bonded to each other. For example, in an embodiment the first upper pads140and the second lower pads260may be formed of the same material (e.g., copper (Cu)), and may be bonded to each other by an intermetallic hybrid bonding process resulting from surface activation at an interface between the first upper pad140and the second lower pad260that are in direct contact with each other.

The bonding between the first upper pads140and the second lower pads260may bond (e.g., directly bond) the upper test pads TTP of the first semiconductor chip100and the lower test pad BTP of the second semiconductor chip200to each other. Each of the upper test pads TTP may partially overlap the lower test pad BTP. In an embodiment, when the first semiconductor substrate1000and the second semiconductor substrate2000are aligned with each other, an overlapping area size between the lower test pad BTP and each of the upper test pads TTP may be in a range of about 10% to about 30% of an area size of each of the upper test pads TTP. For example, in an embodiment the same overlapping area size may be provided between the lower test pad BTP and each of the upper test pads TTP.

Referring toFIGS.15A and15B, a test process may be performed to test an alignment and bonding between the first semiconductor substrate1000and the second semiconductor substrate2000. For example, an electrical resistance between two of the upper test pads TTP may be measured. In this embodiment, measurement tips TT may directly contact two of the first lower pads160. The two first lower pads160may be the first lower pads160connected to the upper test pads TTP. A path SP of an electrical signal that is input or output through the measurement tips TT may be shown as indicated by an arrow inFIG.15B. For example, the electrical signal path SP may be a transit path that passes through one of the first lower pads160, one of the first vias130, one of the upper test pads TTP, the lower test pad BTP, another of the upper test pads TTP, another of the first vias130, and another of the first lower pads160. As illustrated inFIG.15B, the electrical signal path SP may pass through the upper test pad TTP positioned in a direction opposite to the first direction X, the lower test pad BTP, and the upper test pad TTP positioned in the sixth direction D4. The measurement tips TT may be used to measure an electrical resistance of the electrical signal path SP.

In an embodiment, the measurement tips TT may then directly contact another two of the first lower pads160. As illustrated inFIG.15C, a path SP of an electrical signal that is input or output through the measurement tips TT may pass through the upper test pad TTP positioned in the sixth direction D4, the lower test pad BTP, and the upper test pad TTP positioned in the fifth direction D3.

Alternatively, as illustrated inFIG.15D, a path SP of an electrical signal that is input or output through the measurement tips TT may pass through the upper test pad TTP positioned in a direction opposite to the first direction X, the lower test pad BTP, and the upper test pad TTP positioned in the first direction X.

The measurement of electrical resistances by using the measurement tips TT may not be performed only on adjacent upper test pads TTP. The measurement of electrical resistances by using the measurement tips TT may be performed on two upper test pads TTP that are adjacent to each other or two upper test pads TTP that are not adjacent to each other.

In an embodiment, the measurement of electrical resistances by using the measurement tips TT may be performed at least twice or more. An overlapping area size between the lower test pad BTP and each of the upper test pads TTP (e.g., in a vertical direction) may be in a range of about 10% to about 30% of an area size of each of the upper test pads TTP. In an embodiment, then the first semiconductor substrate1000and the second semiconductor substrate2000are aligned with each other within this range, the same overlapping area size may be provided between the lower test pad BTP and each of the upper test pads TTP. Therefore, the same interfacial resistance may be present between the lower test pad BTP and each of the upper test pads TTP. In such a case, electrical resistances measured by the measurement tips TT may be the same as each other.

The first semiconductor substrate1000and the second semiconductor substrate2000may be misaligned with each other.FIGS.16A to16Cdepict an embodiment of misalignment between the first semiconductor substrate1000and the second semiconductor substrate2000.FIGS.16B and16Cdepict by way of example a misalignment in which the second semiconductor substrate2000is shifted in the first direction X from the first semiconductor substrate1000.

As illustrated inFIG.16B, a path SP of an electrical signal that is input or output through the measurement tips TT may pass through the upper test pad TTP positioned in a direction opposite to the first direction X, the lower test pad BTP, and the upper test pad TTP positioned in the sixth direction D4. As the second semiconductor substrate2000is shifted in the first direction X from the first semiconductor substrate1000, the closer to a direction opposite to the first direction X, the smaller the overlapping area size between the lower test pad BTP and each of the upper test pads TTP. Therefore, an electrical resistance measured by the measurement tips TT may be greater in this case than in a case where the first semiconductor substrate1000and the second semiconductor substrate2000are correctly aligned with each other. For example, when each of overlapping area sizes between the lower test pad BTP and the upper test pads TTP is less than about 10% of an area size of each of the upper test pads TTP, a large electrical resistance may be measured. A reduction in overlapping area size between the lower test pad BTP and each of the upper test pads TTP may cause an increase in measured electrical resistance.

In an embodiment, the electrical resistance between the upper test pads TTP measure by using the measurement tips TT may be compared with a reference resistance. The reference resistance may be an electrical resistance measured between the same upper test pads TTP when the first semiconductor substrate1000and the second semiconductor substrate2000are correctly aligned with each other as discussed with referenceFIG.16B. For example, the reference resistance may be the same as an electrical resistance of a test path measured when an overlapping area size between the lower test pad BTP and each of the upper test pads TTP is in a range of about 10% to about 30% of an area size of each of the upper test pads TTP. When the measured resistance is less than the reference resistance, the second semiconductor substrate2000may be misaligned with the first semiconductor substrate1000. In this case, a direction in which the second semiconductor substrate2000is shifted from the first semiconductor substrate1000may be opposite to a direction in which the measured upper test pads TTP are positioned from a center of the lower test pad BTP.

Alternatively, the reference resistance may be a resistance measured between the upper test pads TTP other than the measured upper test pads TTP. As illustrated inFIG.16C, a path SP of an electrical signal that is input or output through the measurement tips TT may pass through the upper test pad TTP positioned in the first direction X, the lower test pad BTP, and the upper test pad TTP positioned in the third direction D1. As the second semiconductor substrate2000is shifted in the first direction X from the first semiconductor substrate1000, the closer to the first direction X, the larger the overlapping area size between the lower test pad BTP and each of the upper test pads TTP. Therefore, an electrical resistance measured by the measurement tips TT may be less in this case than in a case where the first semiconductor substrate1000and the second semiconductor substrate2000are correctly aligned with each other. For example, when each of overlapping area sizes between the lower test pad BTP and the upper test pads TTP is greater than about 10% of an area size of each of the upper test pads TTP, a small electrical resistance may be measured. An increase in overlapping area size between the lower test pad BTP and each of the upper test pads TTP may cause a reduction in measured electrical resistance.

Referring toFIGS.16A to16c, in an embodiment the measurement of electrical resistances by using the measurement tips TT may be performed at least twice or more. Electrical resistances may be measured between the upper test pads TTP. For example, it may be possible to measure electrical resistances between a plurality of electrical signal paths SP. In this case, the reference resistance may be one of the measured electrical resistances. For example, the measured electrical resistances may be compared with each other. When the measured resistances are different from each other, the second semiconductor substrate2000may be misaligned with the first semiconductor substrate1000. A direction in which the second semiconductor substrate2000is shifted from the first semiconductor substrate1000may be a direction that is directed from the upper test pad TTP having the minimum measured electrical resistance towards the upper test pad TTP having the maximum measured electrical resistance. Alternatively, a direction in which the second semiconductor substrate2000is shifted from the first semiconductor substrate1000may be opposite to a direction in which the upper test pad TTP having the minimum measured electrical resistance is positioned from a center of the lower test pad BTP.

According to some embodiments of the present inventive concept, the test pads TTP and BTP in the first and second semiconductor substrates1000and2000may be used to test an alignment between the first semiconductor substrate1000and the second semiconductor substrate2000. For example, the alignment between the first semiconductor substrate1000and the second semiconductor substrate2000may be tested by using a simplified process in which the external pads (e.g., the first lower pads160) are used to measure an electrical resistance. Therefore, when testing the alignment between the first semiconductor substrate1000and the second semiconductor substrate2000, it may be possible to avoid damage to the first semiconductor substrate1000and the second semiconductor substrate2000. It may thus be possible to provide a method of testing a semiconductor package in which method a semiconductor package is free of damage caused by the test.

In addition, in accordance with the number and arrangement of the upper test pads TTP, it may be possible to measure the degree and direction of misalignment between the first semiconductor substrate1000and the second semiconductor substrate2000. For example, it may be possible to provide a method of testing a semiconductor package that is capable of obtaining detailed information about the alignment between the first semiconductor substrate1000and the second semiconductor substrate2000. Accordingly, the method of testing a semiconductor package may have a high test precision and may achieve good bonding between semiconductor substrates of a semiconductor package fabricated and tested thereby.

Additionally, a small number of the test structure TTP and BTP, for example, one test structure TTP and BTP may be used to test an alignment between the first semiconductor substrate1000on which a plurality of first semiconductor chips100are formed and the second semiconductor substrate2000on which a plurality of second semiconductor chips200are formed, and it may be unnecessary to test all of the alignments between the first semiconductor chips100and the second semiconductor chips200. In conclusion, it may be possible to provide a simplified method of testing a semiconductor package.

Referring back toFIGS.15A to15D, to achieve an easy test of an alignment between the first semiconductor substrate1000and the second semiconductor substrate2000, a size of area (referred to hereinafter as an overlapping area size) where each of the upper test pads TTP overlaps the lower test pad BTP may be in a range of about 10% to about 30% of an area size of each of the upper test pads TTP. In this description, the overlapping area size may be an area size measured when the first semiconductor substrate1000and the second semiconductor substrate2000are correctly aligned with each other. In a case where the overlapping area size is less than about 10% of the area size of each of the upper test pads TTP due to the first semiconductor substrate1000and the second semiconductor substrate2000being misaligned with each other, one or more of the upper test pads TTP may be completely spaced apart from the lower test pad BTP. For example, the one or more of the upper test pads TTP may be electrically insulated from the lower test pad BTP, and no electrical resistance may be measured between the test pads TTP and BTP. In a case where the overlapping area size is greater than about 30% of the area size of each of the upper test pads TTP, even when the overlapping area size is increased, an interfacial resistance between the lower test pad BTP and each of the upper test pads TTP may be constant without being increased. Therefore, even if the first semiconductor substrate1000and the second semiconductor substrate2000are misaligned with each other, the measured electrical resistances may be the same as each other when the overlapping area size between the lower test pad BTP and each of the upper test pads TTP is still greater than about 30% of the area size of each of the upper test pads TTP. Thus, no alignment test may be performed between the first semiconductor substrate1000and the second semiconductor substrate2000.

Referring back toFIG.1, in an embodiment a portion of the scribe lane region SR may be removed through a sawing process that uses a laser to separate semiconductor packages in which the first semiconductor chips100are bonded to the second semiconductor chips200. For example, the laser may be irradiated along an arbitrary cutting line positioned in the scribe lane region SR, and the laser may remove the second semiconductor substrate2000, the second lower protection layer270, the first upper protection layer150, the first semiconductor substrate1000, and the first lower protection layer170that are provided on a portion of the scribe lane region SR. The cutting line may be set on the scribe lane region SR. The cutting line may extend in a direction that runs across between the device regions DR. The cutting line may be positioned at a middle of the scribe lane region SR. For example, distances between the cutting line and the device regions DR may be substantially identical or similar. In this case, the cutting line may be spaced apart from the test structure BTP and TTP. After the sawing process, a remaining region other than the removed portion of the scribe lane region SR may be defined as an edge region ER of a semiconductor package.

FIG.1depicts that the test structure BTP and TTP remains without being removed in the sawing process. However, embodiments of the present inventive concept are not necessarily limited thereto. According to some embodiments, a portion of the scribe lane region SR may be removed through a sawing process that uses a laser to separate semiconductor packages in which the first semiconductor chips100are bonded to the second semiconductor chips200. The cutting line may be positioned at a middle of the scribe lane region SR. In this case, the test structure BTP and TTP may be positioned in a region that is removed through the sawing process. Thus, the test structure BTP and TTP may be removed in the sawing process, and may not remain in a semiconductor package.

Referring again toFIG.1, external terminals102may be provided on (e.g., disposed directly thereon) the first lower pads160.

In a method of testing a semiconductor package according to some embodiments of the present inventive concept, test pads in semiconductor substrates may be used to test an alignment between the semiconductor substrates. For example, the alignment between the semiconductor substrates may be tested by using a simplified process in which external pads are used to measure an electrical resistance. Thus, damage to the semiconductor substrates may be prevented when testing the alignment between the semiconductor substrates. It may thus be possible to provide a method of testing a semiconductor package in which method a semiconductor package is free of damage caused by the test.

In addition, in accordance with the number and arrangement of upper test pads, it may be possible to measure all of the degree and direction of misalignment between the semiconductor substrates. For example, it may be possible to provide a method of testing a semiconductor package which provides detailed information about the alignment or misalignment between the semiconductor substrates. Accordingly, the method of testing a semiconductor package may have high test precision and may achieve good bonding between the semiconductor substrates of a semiconductor package fabricated and tested thereby.

Moreover, a small number of test structure may be used to test the alignment between the semiconductor substrates, and it may be unnecessary to test all of the alignment between semiconductor chips. In conclusion, it may be possible to provide a simplified method of testing a semiconductor package.

Although the present inventive concept have been described in connection with the some embodiments of the present inventive concept illustrated in the accompanying drawings, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and essential feature of the present inventive concept. Therefore, the described embodiments should thus be considered illustrative and not restrictive.