APPARATUS FOR MANUFACTURING DISPLAY DEVICE, METHOD OF MANUFACTURING DISPLAY DEVICE, AND MASK ASSEMBLY

An apparatus for manufacturing a display device includes a chamber, a mask assembly disposed inside the chamber to face a display substrate, and a deposition source unit that is disposed inside the chamber to face the mask assembly, supplies a deposition material, and deposits the deposition material on the display substrate by passing through the mask assembly, wherein the mask assembly includes a first mask layer including a first mask opening, and a second mask layer disposed on the first mask layer and including a second mask opening overlapping the first mask opening, and the second mask layer includes a first inorganic layer, a first organic layer disposed on the first inorganic layer, and a second inorganic layer disposed on the first organic layer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0039074, filed on Mar. 24, 2023, and Korean Patent Application No. 10-2023-0052820, filed on Apr. 21, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference herein.

BACKGROUND

1. Technical Field

One or more embodiments relate to an apparatus and a method, and more particularly, to an apparatus for manufacturing a display device, a method of manufacturing a display device, and a mask assembly.

2. Description of the Related Art

A display device visually displays data. The display device may provide an image by using light-emitting diodes. Recently, display devices have been diversified in usage. Accordingly, various designs of the display devices have been attempted to improve the quality of the display devices.

SUMMARY

One or more embodiments include a mask assembly capable of performing readily thickness adjustment, improving durability, and reducing (or minimizing) a clogging phenomenon of an opening through which a deposition material passes.

According to one or more embodiments, an apparatus for manufacturing a display device may include a chamber, a mask assembly disposed inside the chamber to face a display substrate, and a deposition source unit that is disposed inside the chamber to face the mask assembly and supplies a deposition material, and deposits the deposition material on the display substrate by passing through the mask assembly, wherein the mask assembly may include a first mask layer including a first mask opening, and a second mask layer disposed on the first mask layer and including a second mask opening overlapping the first mask opening, wherein the second mask layer may include a first inorganic layer, a first organic layer disposed on the first inorganic layer, and a second inorganic layer disposed on the first organic layer.

In an embodiment, the second mask opening may include a first inorganic opening disposed in the first inorganic layer, a first organic opening disposed in the first organic layer, and a second inorganic opening disposed in the second inorganic layer.

In an embodiment, a width of the first organic opening may be greater than a width of the second inorganic opening in a cross-sectional view.

In an embodiment, a width of the first inorganic opening and the width of the second inorganic opening may be same as each other in a cross-sectional view.

In an embodiment, a width of the first inorganic opening, a width of the first organic opening, and a width of the second inorganic opening may be same as each other in a cross-sectional view.

In an embodiment, a thickness of the first organic layer may be greater than a thickness of the first inorganic layer and a thickness of the second inorganic layer in a cross-sectional view.

In an embodiment, the first mask layer may include a silicon material.

In an embodiment, the second mask layer may further include a second organic layer disposed on the second inorganic layer, and a third inorganic layer disposed on the second organic layer.

According to one or more embodiments, a method of manufacturing a display device may include disposing a display substrate inside a chamber, disposing a mask assembly inside the chamber, and supplying a deposition material toward the mask assembly from a deposition source unit, wherein the disposing of the mask assembly may include disposing a second mask layer on a first mask layer, forming a first mask opening in the first mask layer, and forming a second mask opening in the second mask layer, wherein the disposing of the second mask layer may include disposing a first inorganic layer on the first mask layer, disposing a first organic layer on the first inorganic layer, and disposing a second inorganic layer on the first organic layer.

In an embodiment, the forming of the second mask opening may include forming a first inorganic opening in the first inorganic layer, forming a first organic opening in the first organic layer, and forming a second inorganic opening in the second inorganic layer.

In an embodiment, the forming of the second inorganic opening may include disposing, on the second inorganic layer, a first photoresist layer in which a first photo-opening is disposed, etching a portion of the second inorganic layer that overlaps the first photo-opening, and removing the first photoresist layer.

In an embodiment, the forming of the first organic opening may include etching a portion of the first organic layer that overlaps the second inorganic opening.

In an embodiment, a width of the first organic opening may be greater than a width of the second inorganic opening in a cross-sectional view.

In an embodiment, the forming of the first inorganic opening may include etching a portion of the first inorganic layer that overlaps the second inorganic opening.

In an embodiment, a width of the first inorganic opening and a width of the second inorganic opening may be same as each other in a cross-sectional view.

According to one or more embodiments, a mask assembly may include a first mask layer including a first mask opening, and a second mask layer disposed on the first mask layer and including a second mask opening overlapping the first mask opening, wherein the second mask layer may include a first inorganic layer, a first organic layer disposed on the first inorganic layer, and a second inorganic layer disposed on the first organic layer.

In an embodiment, the second mask opening may include a first inorganic opening disposed in the first inorganic layer, a first organic opening disposed in the first organic layer, and a second inorganic opening disposed in the second inorganic layer.

In an embodiment, a width of the first organic opening may be greater than a width of the second inorganic opening in a cross-sectional view.

In an embodiment, a thickness of the first organic layer may be greater than a thickness of the first inorganic layer and a thickness of the second inorganic layer in a cross-sectional view.

In an embodiment, the first mask layer may include a silicon material.

Other aspects, features, and advantages other than those described above will now become apparent from the following drawings, claims, and the detailed description of the disclosure.

DETAILED DESCRIPTION

FIG.1is a schematic cross-sectional view of an apparatus for manufacturing a display device according to an embodiment.

An apparatus1for manufacturing a display device may include a chamber CH, a first support portion SP1, a second support portion SP2, a mask assembly MA, a deposition source unit SC, a magnetic force unit MG, a vision unit VS, and a pressure adjusting unit PSC.

The chamber CH may have a space therein, and a display substrate DS and the mask assembly MA may be accommodated in the space. For example, a portion of the chamber CH may be formed to be opened, and a gate valve GB may be installed on the open portion (e.g., entrance, door, or opening and closing parts) of the chamber CH. For example, the open portion of the chamber CH may be opened or closed according to an operation of the gate valve GB.

For example, the display substrate DS may include a substrate100and at least one of an organic layer, an inorganic layer, and a metal layer, which are deposited on the substrate100, as described below, in a process of manufacturing a display device. In another example, the display substrate DS may be a substrate100on which any one of an organic layer, an inorganic layer, and a metal layer has not yet been deposited.

The first support portion SP1may support the display substrate DS. For example, the first support portion SP1may have a plate shape fixed inside the chamber CH. In another example, the first support portion SP1may also have a shuttle shape such that the display substrate DS may be seated on the first support portion SP1and may perform a linear movement in the chamber CH. In another example, the first support portion SP1may also include an electrostatic chuck or an adhesive chuck, which is fixed to the chamber CH or arranged in the chamber CH to be movable in the chamber CH.

The second support portion SP2may support the mask assembly MA. For example, the second support portion SP2may be arranged in the chamber CH. The second support portion SP2may finely adjust the position of the mask assembly MA. For example, the second support portion SP2may include a separate driver or an alignment unit to move the mask assembly MA in a different direction from the moving direction of the second support portion SP2.

In another example, the second support portion SP2may also have a shuttle shape. For example, the second support portion SP2may include the mask assembly MA seated thereon and may transfer the mask assembly MA. For example, the second support portion SP2may move to the outside of the chamber CH and enter the chamber CH from the outside of the chamber CH after the mask assembly MA is seated on the second support portion SP2.

For example, the first support portion SP1may be integral with the second support portion SP2. For example, the first support portion SP1and the second support portion SP2may include a movable shuttle. For example, the first support portion SP1and the second support portion SP2include a structure that fixes the mask assembly MA and the display substrate DS thereon in case that the display substrate DS is seated on the mask assembly MA, and are able to linearly move the display substrate DS and the mask assembly MA.

However, hereinafter, for convenience of description, a case, in which the first support portion SP1and the second support portion SP2are formed to be separated from each other and arranged at different positions in the chamber CH, and the first support portion SP1and the second support portion SP2are arranged inside the chamber CH, is described in detail.

The mask assembly MA may be arranged inside the chamber CH to face the display substrate DS. A deposition material M may be deposited on the display substrate DS through the mask assembly MA.

The deposition source unit SC may be arranged to face the mask assembly MA, and may supply the deposition material M such that the deposition material M may be deposited on the display substrate DS by passing through the mask assembly MA. For example, the deposition source unit SC may evaporate or sublimate the deposition material M by applying heat to the deposition material M. The deposition source unit SC may be arranged to be fixed inside the chamber CH or arranged inside the chamber CH to be able to linearly move in a direction.

The magnetic force unit MG may be arranged inside the chamber CH to face the display substrate DS and/or the mask assembly MA. For example, the magnetic force unit MG may press the mask assembly MA toward the side of the display substrate DS by applying a magnetic force to the mask assembly MA.

The vision unit VS may be arranged in the chamber CH and may capture an image of the positions of the display substrate DS and the mask assembly MA. For example, the vision unit VS may include a camera that captures an image of the display substrate DS and the mask assembly MA. Based on the image captured by the vision unit VS, the positions of the display substrate DS and the mask assembly MA may be determined, and the transformation of the mask assembly MA may be confirmed. For example, based on the image, the position of the display substrate DS may be finely adjusted by the first support portion SP1, and the position of the mask assembly MA may be finely adjusted by the second support portion SP2. However, hereinafter, a case in which the positions of the display substrate DS and the mask assembly MA are aligned with each other by finely adjusting the position of the mask assembly MA by the second support portion SP2is described in detail.

The pressure adjusting unit PSC may be connected to the chamber CH to adjust the inner pressure of the chamber CH. For example, the pressure adjusting unit PSC may adjust the inner pressure of the chamber CH to be equal to or similar to atmospheric pressure. For example, the pressure adjusting unit PSC may adjust the inner pressure of the chamber CH to be same as or similar to a vacuum state.

The pressure adjusting unit PSC may include a connection pipe81connected to the chamber CH and a pump82installed in the connection pipe81. For example, depending on an operation of the pump82, external air may be introduced (or transferred) to the chamber CH through the connection pipe81, or a gas inside the chamber CH may be guided to the outside through the connection pipe81.

Referring to a method of manufacturing a display device by using the apparatus1for manufacturing a display device as described above, the display substrate DS may be prepared.

The pressure adjusting unit PSC may maintain the inside of the chamber CH in a state that is equal to or similar to atmospheric pressure, and the gate valve GB may operate to open the open portion (e.g., entrance, door, or opening and closing same) of the chamber CH.

Thereafter, the display substrate DS may be charged (or transferred) into the chamber CH from the outside. For example, the display substrate DS may be charged (or transferred) into the chamber CH in various ways. For example, the display substrate DS may be charged (or transferred) into the chamber CH from the outside of the chamber CH by a robot arm arranged outside the chamber CH. In another example, in case that the first support portion SP1is formed in a shuttle shape, after the first support portion SP1is carried out from the inside of the chamber CH to the outside of the chamber CH, the display substrate DS may be seated on the first support portion SP1, and the first support portion SP1may be charged (or transferred) into the chamber CH from the outside of the chamber CH, by a separate robot arm or the like arranged outside the chamber CH.

The mask assembly MA may be arranged inside the chamber CH as described above. In another example, the mask assembly MA may also be charged (or transferred) into the chamber CH from the outside of the chamber CH in the same or similar manner to the display substrate DS.

In case that the display substrate DS is charged (or transferred) into the chamber CH, the display substrate DS may be seated on the first support portion SP1. For example, the vision unit VS may capture an image of the positions of the display substrate DS and the mask assembly MA. The positions of the display substrate DS and the mask assembly MA may be determined based on the image captured by the vision unit VS. For example, the apparatus1for manufacturing a display device may include a separate controller to determine the positions of the display substrate DS and the mask assembly MA.

In case that the positions of the display substrate DS and the mask assembly MA are determined, the second support portion SP2may finely adjust the position of the mask assembly MA.

Thereafter, the deposition source unit SC may operate to supply the deposition material M to a side of the mask assembly MA, and the deposition material M passing through the mask assembly MA may be deposited on the display substrate DS. For example, the deposition source unit SC may move parallel to the display substrate DS and the mask assembly MA, or the display substrate DS and the mask assembly MA may move parallel to the deposition source unit SC. For example, the deposition source unit SC may move relatively to the display substrate DS and the mask assembly MA. For example, the pump82may maintain the inner pressure of the chamber CH in a state that is same as or similar to a vacuum state by absorbing and discharging a gas inside the chamber CH to the outside.

As described above, the deposition material M supplied from the deposition source unit SC may be deposited on the display substrate DS by passing through the mask assembly MA, and accordingly, a plurality of layers to be deposited on a display device to be described below, for example, at least one of an organic layer, an inorganic layer, and metal layer, may be formed.

FIG.2is a schematic cross-sectional view of a mask assembly according to an embodiment, andFIG.3is a schematic plan view of a portion of a second mask layer according to an embodiment.FIG.3is a diagram of a region A ofFIG.2as viewed from above (e.g., in a plan view).

Referring toFIGS.2and3, the mask assembly MA may include a first mask layer41and a second mask layer42.

The first mask layer41may support the second mask layer42. A first mask opening OP41may be arranged in the first mask layer41such that the deposition material M (refer toFIG.1) may pass therethrough. An inner peripheral surface may be formed in the first mask layer41by the first mask opening OP41. The first mask opening OP41may be arranged at a central portion of the first mask layer41. A central portion of the second mask layer42may be exposed through the first mask opening OP41of the first mask layer41.FIG.2shows that the inner peripheral surface of the first mask layer41is inclined with respect to the second mask layer42in a cross-sectional view, but this is only an example, and the inner peripheral surface of the first mask layer41may be perpendicular to the second mask layer42.

The first mask layer41may include a silicon material. For example, the first mask layer41may include at least one material of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy).

The second mask layer42may be disposed on the first mask layer41. A second mask opening OP42may be arranged in the second mask layer42such that the deposition material M (refer toFIG.1) may pass therethrough. The second mask opening OP42may overlap the first mask opening OP41. Second mask openings OP42may be provided. For example, as shown inFIG.3, the second mask openings OP42may be arranged in a first direction (e.g., an x-axis direction) and a second direction (e.g., a y-axis direction). The second mask layer42may include a first inorganic layer421, a first organic layer422, and a second inorganic layer423.

The first inorganic layer421may be disposed on the first mask layer41. For example, the first inorganic layer421may include at least one material of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy).

The first organic layer422may be disposed on the first inorganic layer421. The first organic layer422may include at least one material of polyimide (PI), polyester, and acrylic.

In a cross-sectional view, a thickness TH2of the first organic layer422may be greater than a thickness TH1of the first inorganic layer421and a thickness TH3of the second inorganic layer423. For example, a length of the first organic layer422in a third direction (e.g., a z-axis direction) may be greater than the thickness TH1of the first inorganic layer421and the thickness TH3of the second inorganic layer423in the third direction (e.g., the z-axis direction). Due to the arrangement of the first organic layer422, a thickness of the second mask layer42may be readily adjusted, and the durability of the second mask layer42may be improved.

The second inorganic layer423may be disposed on the first organic layer422. The second inorganic layer423and the first inorganic layer421may include the same material. In a cross-sectional view, the thickness TH3of the second inorganic layer423may be substantially equal to the thickness TH1of the first inorganic layer421. For example, the length of the second inorganic layer423in the third direction (e.g., the z-axis direction) may be substantially equal to the length of the first inorganic layer421in the third direction (e.g., the z-axis direction).

The second mask opening OP42may include a first inorganic opening OP421, a first organic opening OP422, and a second inorganic opening OP423. The first inorganic opening OP421may be arranged in the first inorganic layer421, the first organic opening OP422may be arranged in the first organic layer422, and the second inorganic opening OP423may be arranged in the second inorganic layer423.

The first inorganic opening OP421, the first organic opening OP422, and the second inorganic opening OP423may overlap each other. Accordingly, the deposition material M (refer toFIG.1) may sequentially pass through the first inorganic opening OP421, the first organic opening OP422, and the second inorganic opening OP423.

In a cross-sectional view, a width W2of the first organic opening OP422may be greater than a width W1of the first inorganic opening OP421and a width W3of the second inorganic opening OP423. In a plan view, an area of the first organic opening OP422may be greater than an area of the first inorganic opening OP421and an area of the second inorganic opening OP423. For example, in a cross-sectional view, the size of the width W1of the first inorganic opening OP421may be the same as the size of the width W3of the second inorganic opening OP423. In a plan view, the area/size of the first inorganic opening OP421may be substantially equal to the area/size of the second inorganic opening OP423.

In such a structure, a first step portion43may be formed in the first organic layer422and the second inorganic layer423. The first step portion43may include at least a portion of a surface of the first organic layer422and a surface of the second inorganic layer423. The first step portion43may be arranged around the first organic opening OP422and the second inorganic opening OP423. In a cross-sectional view, a shape of the first step portion43may have a ‘¬’ shape.

At least a portion of the deposition material M (refer toFIG.1) supplied from the deposition source unit SC (refer toFIG.1) may be accumulated in the second mask opening OP42without passing through the second mask opening OP42. For example, at least a portion of the deposition material M (refer toFIG.1), which is accumulated in the second mask opening OP42, may be accumulated on the first step portion43. For example, due to the first step portion43, a phenomenon in which the deposition material M (refer toFIG.1) blocks the second mask opening OP42may be reduced. Accordingly, although there is no separate cleaning process of the mask assembly MA, the usage time (or lifespan) of the mask assembly MA may increase.

FIGS.4to11are cross-sectional views for explaining a method of manufacturing a display device according to an embodiment.

Referring toFIGS.4to11, the same reference numerals as those inFIGS.1to3refer to the same members, and redundant descriptions thereof are omitted for descriptive convenience.

Referring toFIGS.4to11, the method of manufacturing a display device may include arranging the mask assembly MA inside the chamber CH (refer toFIG.1). The arranging of the mask assembly MA may include disposing the second mask layer42on the first mask layer41, forming the first mask opening OP41in the first mask layer41, and forming the second mask opening OP42in the second mask layer42.

Referring toFIG.4, the disposing of the second mask layer42on the first mask layer41may include disposing the first inorganic layer421on the first mask layer41, disposing the first organic layer422on the first inorganic layer421, and disposing the second inorganic layer423on the first organic layer422. For example, the first inorganic layer421may be deposited on the first mask layer41, the first organic layer422may be deposited on the first inorganic layer421, and the second inorganic layer423may be deposited on the first organic layer422.

Referring toFIGS.4to6, the forming of the second mask opening OP42may include forming the second inorganic opening OP423in the second inorganic layer423. The second inorganic opening OP423may be formed by a photolithography process.

Referring toFIG.4, the forming of the second inorganic opening OP423may include disposing a first photoresist layer PR1, in which a first photo-opening OPPR1is arranged, on the second inorganic layer423. After the first photoresist layer PR1is disposed on the second inorganic layer423, the first photoresist layer PR1is exposed through a patterned mask, and then the first photo-opening OPPR1may be formed by a process of removing a portion of the first photoresist layer PR1.

Referring toFIG.5, the forming of the second inorganic opening OP423may include etching the second inorganic layer423overlapping the first photo-opening OPPR1. A portion of the second inorganic layer423, which overlaps the first photo-opening OPPR1, may be removed by an etching process. For example, a portion of the second inorganic layer423may be removed by a dry etching process.

Referring toFIG.6, the forming of the second inorganic opening OP423may include removing the first photoresist layer PR1(refer toFIG.5). The first photoresist layer PR1(refer toFIG.5) remaining on the second inorganic layer423may be removed (e.g., entirely removed).

Referring toFIG.7, the forming of the second mask opening OP42may include forming the first organic opening OP422in the first organic layer422. The forming of the first organic opening OP422may include etching the first organic layer422overlapping the second inorganic opening OP423. A portion of the first organic layer422, which overlaps the second inorganic opening OP423, may be removed by an etching process. For example, a portion of the first organic layer422may be removed by a wet etching process. For example, due to an etching solution, a width W2of the first organic opening OP422may be greater than a width W3of the second inorganic opening OP423in a cross-sectional view.

Referring toFIGS.8to10, the forming of the second mask opening OP42may include forming the first inorganic opening OP421in the first inorganic layer421. The first inorganic opening OP421may be formed by a photolithography process.

Referring toFIG.8, the forming of the first inorganic opening OP421may include disposing a second photoresist layer PR2, in which a second photo-opening OPPR2is arranged, on the second inorganic layer423. The second photo-opening OPPR2may overlap the second inorganic opening OP423. In a plan view, the second photo-opening OPPR2may have the same size and shape as that of the second inorganic opening OP423.

Referring toFIG.9, the forming of the first inorganic opening OP421may include etching the first inorganic layer421overlapping the second photo-opening OPPR2. For example, the forming of the first inorganic opening OP421may include etching the first inorganic layer421overlapping the second inorganic opening OP423. A portion of the first inorganic layer421, which overlaps the second inorganic opening OP423, may be removed by an etching process. For example, a portion of the first inorganic layer421may be removed by the dry etching process described above. For example, in a cross-sectional view, the size of the width W1of the first inorganic opening OP421and the size of the width W3of the second inorganic opening OP423may be the same as each other.

Referring toFIG.10, the forming of the first inorganic opening OP421may include removing the second photoresist layer PR2(refer toFIG.9). The second photoresist layer PR2(refer toFIG.9) remaining on the second inorganic layer423may be removed (e.g., entirely removed).

Referring toFIG.11, the first mask opening OP41may be formed by a photolithography process. A portion of the first mask layer41may be removed by an etching process. For example, a portion of the first mask layer41may be removed by the dry etching process or wet etching process described above.

FIG.12is a schematic cross-sectional view of the mask assembly MA according to another embodiment.

InFIG.12, the same reference numerals as those inFIG.2refer to the same members, and redundant description thereof are omitted for descriptive convenience.

Referring toFIG.12, in a cross-sectional view, the sizes of the widths W1, W2, and W3of the first inorganic opening OP421, the first organic opening OP422, and the second inorganic opening OP423may be same as each other. In a plan view, areas of the first inorganic opening OP421, the first organic opening OP422, and the second inorganic opening OP423may be substantially equal to each other.

However, the shape of the second mask opening OP42shown inFIGS.2to12is only an example, and the shape of the second mask opening OP42is not limited thereto. For example, unlike those shown inFIGS.2to12, in a cross-sectional view, the width W2of the first organic opening OP422may be less than the width W1of the first inorganic opening OP421and the width W3of the second inorganic opening OP423, and may also have various shapes.

FIG.13is a schematic cross-sectional view of a mask assembly according to another embodiment.

InFIG.13, the same reference numerals as those inFIG.2refer to the same members, and redundant descriptions thereof are omitted for descriptive convenience.

Referring toFIG.13, the second mask layer42may include the first inorganic layer421, the first organic layer422, the second inorganic layer423, a second organic layer424, and a third inorganic layer425. The second organic layer424may be disposed on the second inorganic layer423, and the third inorganic layer425may be disposed on the second organic layer424. The first inorganic layer421, the second inorganic layer423, and the third inorganic layer425may include the same material. The first organic layer422and the second organic layer424may include the same material.

For example, the second mask opening OP42may include the first inorganic opening OP421, the first organic opening OP422, the second inorganic opening OP423, a second organic opening OP424, and a third inorganic opening OP425. The second organic opening OP424may be arranged in the second organic layer424, and the third inorganic opening OP425may be arranged in the third inorganic layer425.

The first inorganic opening OP421, the first organic opening OP422, the second inorganic opening OP423, the second organic opening OP424, and the third inorganic opening OP425may overlap each other. Accordingly, the deposition material M (refer toFIG.1) may sequentially pass through the first inorganic opening OP421, the first organic opening OP422, the second inorganic opening OP423, the second organic opening OP424, and the third inorganic opening OP425.

In a cross-sectional view, a width W4of the second organic opening OP424may be greater than a width W1of the first inorganic opening OP421, a width W3of the second inorganic opening OP423, and a width W5of the third inorganic opening OP425. In a plan view, an area of the second organic opening OP424may be greater than an area of each of the first inorganic opening OP421, the second inorganic opening OP423, and the third inorganic opening OP425. For example, in a cross-sectional view, the sizes of the widths W1, W3, and W5of the first inorganic opening OP421, the second inorganic opening OP423, and the third inorganic opening OP425may be same as each other. In a plan view, the areas of the first inorganic opening OP421, the second inorganic opening OP423, and the third inorganic opening OP425may be substantially equal to each other.

In such a structure, a second step portion44may be formed in the second organic layer424and the third inorganic layer425. The second step portion44may include at least a portion of a surface of the second organic layer424and a surface of the third inorganic layer425. The second step portion44may be arranged around the second organic opening OP424and the third inorganic opening OP425. In a cross-sectional view, a shape of the second step portion44may have a ‘¬’ shape.

At least a portion of the deposition material M (refer toFIG.1) supplied from the deposition source unit SC (refer toFIG.1) may be accumulated in the second mask opening OP42without passing through the second mask opening OP42. For example, at least a portion of the deposition material M (refer toFIG.1), which is accumulated in the second mask opening OP42, may be accumulated on the first step portion43and the second step portion44. For example, due to the first step portion43and the second step portion44, a phenomenon in which the deposition material M (refer toFIG.1) blocks the second mask opening OP42may be reduced. Accordingly, although there is no separate cleaning process of the mask assembly MA, the usage time (or lifespan) of the mask assembly MA may increase.

FIG.14is a schematic perspective view of a display device according to an embodiment.

Referring toFIG.14, a display device2may include a display area DA and a peripheral area PA surrounding the display area DA. The display device2may provide a certain image by using light emitted from pixels arranged in the display area DA.

The peripheral area PA may surround (e.g., entirely surround) the display area DA. The peripheral area PA may be a kind of non-display area in which pixels are not arranged, and drivers or lines for providing electrical signals or power to the pixels may be arranged therein.

As shown inFIG.14, the display device2may have a rectangular shape in which a horizontal length is greater than a vertical length, but embodiments are not limited thereto. The display device2may have various shapes such as a polygonal shape, a circular shape, or an elliptical shape.

Hereinafter, the display device2according to an embodiment is described as an organic light-emitting display device as an example, but embodiments are not limited thereto. In another example, a display device of another type, such as a quantum dot light-emitting display, may be used.

FIG.15is a schematic cross-sectional view of a display device according to an embodiment.FIG.15is a cross-sectional view of the display device2taken along line A-A′ ofFIG.14.

Referring toFIG.15, the display device2may include a display panel10, an input sensing layer40disposed on the display panel10, and an optical functional layer50. The display panel10, the input sensing layer40, and the optical functional layer50may be covered by a window60. The display device2may be various types of electronic devices, such as a mobile phone, a notebook computer, and a smart watch.

The display panel10may display an image. The display panel10may include pixels arranged in the display area DA. The pixels may include a display element and a pixel circuit connected to the display element. The display element may include an organic light-emitting diode, a quantum dot organic light-emitting diode, or the like.

The input sensing layer40may obtain (or collect) coordinate information according to an external input, for example, a touch event. The input sensing layer40may include a sensing electrode (or touch electrode) and a trace line connected to the sensing electrode. The input sensing layer40may be disposed on the display panel10. The input sensing layer40may sense an external input in a mutual-capacitive method and/or a self-capacitive method.

The input sensing layer40may be formed (e.g., directly formed) on the display panel10or formed separately and then bonded to the display panel10through an adhesive layer such as an optical clear adhesive. For example, the input sensing layer40may be formed continuously after a process of forming the display panel10. For example, the input sensing layer40may be formed as a portion of the display panel10, and an adhesive layer may not be between the input sensing layer40and the display panel10.FIG.15illustrates that the input sensing layer40is between the display panel10and the optical functional layer50, but the input sensing layer40may also be disposed above the optical functional layer50in another example.

The optical functional layer50may include an anti-reflection layer. The anti-reflection layer may reduce the reflectance of light incident from the outside (e.g., external light) toward the display panel10through the window60. In an embodiment, the anti-reflection layer may include a black matrix and color filters. The color filters may be arranged according to the color of light emitted from each of the pixels of the display panel10.

In another example, the anti-reflection layer may include a retarder and a polarizer. The retarder may be a film type or a liquid-crystal coating type, and may include a λ/2 retarder and/or a λ/4 retarder. The polarizer may also be a film type or a liquid-crystal coating type. The film-type polarizer may include a stretch-type synthetic resin film, and the liquid-crystal-coating-type polarizer may include liquid crystals in a certain arrangement. The retarder and the polarizer may further include a protective film. The retarder and the polarizer or the protective film may be defined as a base layer of the anti-reflection layer.

In another example, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer arranged on different layers. First reflected light and second reflected light respectively reflected from the first reflective layer and the second reflective layer may destructively interfere, and thus, the reflectance of external light may be reduced.

In an embodiment, the optical functional layer50may be formed continuously after a process of forming the display panel10and/or the input sensing layer40. For example, the adhesive layer may not be between the optical functional layer50and the input sensing layer40and/or between the input sensing layer40and the display panel10.

For example, a layer including an optical clear adhesive or an optical clear resin may be between the window60and the optical functional layer50.

FIG.16is a schematic plan view of a display panel according to an embodiment. As described above with reference toFIG.15, a display device according to an embodiment may include the display panel10.FIG.16may illustrate a view of a substrate100of the display panel10.

Referring toFIG.16, the display panel10may include the display area DA and the peripheral area PA outside the display area DA. The display area DA may be a portion that displays an image, and pixels P may be arranged in the display area DA. The display area DA have various shapes, for example, a circular shape, an oval shape, a polygonal shape, a shape of a certain figure, or the like. InFIG.16, the display area DA is shown to have a substantially rectangular shape with rounded corners.

Each of the pixels P refers to a sub-pixel, and may include a display element such as an organic light-emitting diode (OLED). The pixel P may emit, for example, red, green, blue, or white light.

The peripheral area PA may be arranged outside the display area DA. Outer circuits for driving the pixels P may be arranged in the peripheral area PA. A first scan driving circuit11, a second scan driving circuit12, an emission control driving circuit13, a terminal14, a driving power supply line15, and a common power supply line16may be arranged in the peripheral area PA.

The first scan driving circuit11may provide a scan signal to the pixel P through a scan line SL. The second scan driving circuit12may be arranged in parallel with the first scan driving circuit11with the display area DA therebetween. Some of the pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit11, and the remaining pixels P may be connected to the second scan driving circuit12. For example, the second scan driving circuit12may be omitted, and all of the pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit11.

The emission control driving circuit13may be arranged on a side of the first scan driving circuit11and provide an emission control signal to the pixel P through an emission control line EL. AlthoughFIG.14illustrates that the emission control driving circuit13is arranged only on a side of the display area DA, the emission control driving circuit13may be arranged on both sides of the display area DA, similar to the first scan driving circuit11and the second scan driving circuit12.

In an embodiment, the peripheral area PA may include a bending area extending toward a side of the display area DA (in a negative y-axis direction). The bending area may be bent toward a rear surface of the display area DA, so that an area (or size) of the non-display area that is visible when viewed from a front surface of the display device may be reduced.

A driving chip20may be arranged in the peripheral area PA. The driving chip20may include an integrated circuit that drives the display panel10. The integrated circuit may be a data driving integrated circuit that generates data signals, but embodiments are not limited thereto.

The terminal14may be arranged in the peripheral area PA. The terminal14may be exposed by not being covered by an insulating layer and may be electrically connected to a printed circuit board30. A terminal34of the printed circuit board30may be electrically connected to the terminal14of the display panel10.

The printed circuit board30may transmit a signal or power of a controller to the display panel10. A control signal generated by the controller may be transmitted to each of the first and second scan driving circuits11and12and the emission control driving circuit13through the printed circuit board30. For example, the controller may transmit a driving voltage ELVDD (refer toFIG.17) to the driving power supply line15and provide a common voltage ELVSS (refer toFIG.17) to the common power supply line16. The driving voltage ELVDD may be transferred to each pixel P through a driving voltage line PL connected to the driving power supply line15, and the common voltage ELVSS may be transferred to an opposite electrode of the pixel P connected to the common power supply line16. The driving power supply line15may have a shape extending in a direction (e.g., x-axis direction) from a lower side of the display area DA. The common power supply line16may have a loop shape with a side open to partially surround the display area DA.

The controller may generate a data signal, and the generated data signal may be transferred to an input line IL through the driving chip20and to the pixel P through a data line DL connected to the input line IL. For reference, “line” may mean “wire”. The above description is similar to the embodiments and modification examples thereof to be described below.

FIG.17is a schematic diagram of an equivalent circuit of a pixel included in a display device according to an embodiment.

Referring toFIG.17, a pixel P may include a pixel circuit PC and an organic light-emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC may include a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red light, green light, or blue light, or may emit red light, green light, blue light, or white light, through the organic light-emitting diode OLED.

The second thin-film transistor T2may be a switching thin-film transistor, which is connected to a scan line SL and the data line DL and transfers, to the first thin-film transistor T1, a data voltage input from the data line DL based on a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the second thin-film transistor T2and the driving voltage line PL and may store a voltage corresponding to a difference between a voltage received from the second thin-film transistor T2and the driving voltage ELVDD supplied to the driving voltage line PL.

The first thin-film transistor T1may be a driving thin-film transistor, which is connected to the driving voltage line PL and the storage capacitor Cst and controls a driving current flowing from the driving voltage line PL through the organic light-emitting diode OLED, in accordance with a voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having a certain brightness according to the driving current. An opposite electrode (e.g., a cathode) of the organic light-emitting diode OLED may receive the common voltage ELVSS.

FIG.17illustrates that the pixel circuit PC includes two thin-film transistors and one storage capacitor, but embodiments are not limited thereto. The number of thin-film transistors and the number of storage capacitors may be variously changed according to the design of the pixel circuit PC. For example, the pixel circuit PC may further include four or more thin-film transistors in addition to the above-mentioned two thin-film transistors.

FIG.18is a schematic cross-sectional view of a display device according to an embodiment.

Referring toFIG.18, the display panel device2may include the substrate100.

The substrate100may include a glass material or a polymer resin. In an embodiment, the substrate100may have a multi-layered structure in which a base layer including a polymer resin and a barrier layer preventing penetration of external materials are cross-stacked.

The barrier layer may include an inorganic material such as silicon nitride (SiNx) and silicon oxide (SiOx).

In the display area DA of the substrate100, a first pixel P1emitting light in a first color, a second pixel P2emitting light in a second color, and a third pixel P3emitting light in a third color. The first color, the second color, and the third color may be any one of red, blue, green, or white.

The first pixel P1may include a first pixel circuit PC1and a first organic light-emitting diode OLED1as a display element electrically connected to the first pixel circuit PC1. The second pixel P2may include a second pixel circuit PC2and a second organic light-emitting diode OLED2electrically connected to the second pixel circuit PC2. The third pixel P3may include a third pixel circuit PC3and a third organic light-emitting diode OLED3electrically connected to the third pixel circuit PC3.

A buffer layer201may be formed on the substrate100to prevent impurities from penetrating into a semiconductor layer Act of a thin-film transistor TFT of the first pixel circuit PC1. The buffer layer201may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxynitride (SiOxNy), and silicon oxide (SiOx), and may include a single layer or a multi-layer that includes the material described above.

The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3may be disposed on the buffer layer201. The first pixel circuit PC1may include the thin-film transistor TFT and the storage capacitor Cst. The thin-film transistor TFT may include the semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. The thin-film transistor TFT shown inFIG.18may correspond to the first thin-film transistor described with reference toFIG.17. The data line DL may be electrically connected to a second thin-film transistor of the first pixel circuit PC1. In an embodiment, a top-gate type in which the gate electrode GE may be disposed above the semiconductor layer Act with a gate insulating layer203between the gate electrode GE and the semiconductor layer Act, but according to another example, the thin-film transistor TFT may be a bottom-gate type. The second pixel circuit PC2and the third pixel circuit PC3may be the same as or similar to the first pixel circuit PC1. Hereinafter, each component of the first pixel circuit PC1is described.

The semiconductor layer Act may include polysilicon. In another example, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, or the like. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a multi-layer or a single layer that includes the material described above.

The gate insulating layer203between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiOx), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or the like. The gate insulating layer203may be a single layer or a multi-layer that includes the above-mentioned material.

The storage capacitor Cst may include a lower electrode CE1and an upper electrode CE2, which overlap each other with a first interlayer insulating layer205between the lower electrode CE1and the upper electrode CE2. The storage capacitor Cst may overlap the thin-film transistor TFT. In this regard,FIG.18illustrates that the gate electrode GE of the thin-film transistor TFT is the lower electrode CE1of the storage capacitor Cst. In another example, the storage capacitor Cst may not overlap the thin-film transistor TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer207. The upper electrode CE2of the storage capacitor Cst may include a conductive material including Mo, Al, Cu, Ti, or the like, and may include a multi-layer or a single layer that includes the above-mentioned material.

The first interlayer insulating layer205and the second interlayer insulating layer207may each include an inorganic insulating material, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiOx), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or the like. The first interlayer insulating layer205and the second interlayer insulating layer207may each be a single layer or a multi-layer that includes the above-mentioned material.

The source electrode SE, the drain electrode DE, and the data line DL may be disposed on the same layer, and may include the same material. For example, the source electrode SE, the drain electrode DE, and the data line DL may be disposed on the second interlayer insulating layer207. The source electrode SE, the drain electrode DE, and the data line DL may each include a material having good conductivity. The source electrode SE and the drain electrode DE may each include a conductive material including Mo, Al, Cu, Ti, or the like, and may include a multi-layer or a single layer that includes the above-mentioned material. In an embodiment, the source electrode SE, the drain electrode DE, and the data line DL may each include a multi-layer of Ti/Al/Ti.

The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3, each of which includes the thin-film transistor TFT and the storage capacitor Cst, may be covered with a first organic insulating layer209. An upper surface of the first organic insulating layer209may be substantially flat.

The first organic light-emitting diode OLED1electrically connected to the first pixel circuit PC1, the second organic light-emitting diode OLED2electrically connected to the second pixel circuit PC2, and the third organic light-emitting diode OLED3electrically connected to the third pixel circuit PC3may be disposed on the first organic insulating layer209.

The first pixel circuit PC1may be electrically connected to a first pixel electrode221rof the first organic light-emitting diode OLED1. For example, as shown inFIG.18, a contact metal layer CM may be between the thin-film transistor TFT and the first pixel electrode221r. The contact metal layer CM may be in contact with the thin-film transistor TFT through a contact hole penetrating the first organic insulating layer209, and the first pixel electrode221rmay be in contact with the contact metal layer CM through a contact hole penetrating a second organic insulating layer211on the contact metal layer CM. The contact metal layer CM may include a conductive material including Mo, Al, Cu, Ti, or the like and may be a multilayer or a single layer including the above-mentioned material. In an embodiment, the contact metal layer CM may include a multi-layer of Ti/Al/Ti.

The first organic insulating layer209and the second organic insulating layer211may each include a general commercial polymer such as poly(methyl methacrylate) (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, and an organic insulating material, such as an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and a mixture thereof. In an embodiment, the first organic insulating layer209and the second organic insulating layer211may each include polyimide (PI).

According to another example, any one of the first organic insulating layer209and the second organic insulating layer211may be omitted. For example, the contact metal layer CM may be omitted.

The first organic light-emitting diode OLED1may include the first pixel electrode221r, a first emission layer222r, and a first opposite electrode223r. The second organic light-emitting diode OLED2may include a second pixel electrode221g, a second emission layer222g, and a second opposite electrode223g. The third organic light-emitting diode OLED3may include a third pixel electrode221b, a third emission layer222b, and a third opposite electrode223b. The second organic light-emitting diode OLED2and the third organic light-emitting diode OLED3may each have a structure similar to or the same as that of the first organic light-emitting diode OLED1.

The first pixel electrode221rmay be disposed on the second organic insulating layer211. The first pixel electrode221rmay include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another example, the first pixel electrode221rmay include a reflective film. For example, the reflective film may include silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another example, the first pixel electrode221rmay further include a film including ITO, IZO, ZnO, or In2O3above/below the reflective film mentioned above.

A pixel defining layer213and a bank layer215may be disposed on the first pixel electrode221r. When viewed from a direction (e.g., z-axis direction) substantially perpendicular to the substrate100, the pixel defining layer213may overlap an edge portion of the first pixel electrode221r. The pixel defining layer213may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxynitride (SiOxNy), or silicon oxide (SiOx).

A first remaining sacrificial layer212R may be between the first pixel electrode221rand the pixel defining layer213. The first remaining sacrificial layer212R may be a portion remaining after a sacrificial layer protecting an upper surface of the first pixel electrode221ris removed. When viewed from a direction (e.g., z-axis direction) substantially perpendicular to the substrate100, the first remaining sacrificial layer212R may be in a region where the pixel defining layer213and the first pixel electrode221roverlap each other. For example, the first remaining sacrificial layer212R may be positioned along the edge portion of the first pixel electrode221rto expose a central portion of the first pixel electrode221r.

The first remaining sacrificial layer212R may be continuously formed with the first pixel electrode221r, and may include a material that is selectively etched without damaging the first pixel electrode221r. For example, the first remaining sacrificial layer212R may include indium gallium zinc oxide (IGZO) and/or indium zinc oxide (IZO).

The first remaining sacrificial layer212R and the pixel defining layer213may overlap the edge portion of the first pixel electrode221rto increase a distance between the first pixel electrode221rand the bank layer215and the first opposite electrode223r, thereby preventing an arc or the like from being generated between the first pixel electrode221rand the first opposite electrode223rand the first opposite electrode223r. In some embodiments, a sacrificial layer may be completely removed so that the first remaining sacrificial layer212R may not exist. For example, a groove formed by removing the sacrificial layer between the first pixel electrode221rand the pixel defining layer213may be empty or filled with the first emission layer222rto be described below.

The bank layer215may be disposed on the pixel defining layer213. The bank layer215may include a conductive material. For example, the bank layer215may include a conductive material including Mo, Al, Cu, Ti, or the like, and may include a multi-layer or a single layer that includes the above-mentioned material. For example, the bank layer215may have a double-layered structure of Al/Ti or a triple-layered structure of Ti/Al/Ti.

The pixel defining layer213and the bank layer215may extend from the display area DA to the peripheral area PA (referFIG.16) of the substrate100, and the bank layer215may be in contact with (e.g., in direct contact with) the common power supply line16(refer toFIG.16) in the peripheral area PA (referFIG.16) through an opening portion of the pixel defining layer213. Accordingly, the bank layer215may function as a connection electrode or an auxiliary line for transferring the common voltage ELVSS to the first opposite electrode223r, the second opposite electrode223g, and the third opposite electrode223bto be described below.

A first conductive layer217may be disposed on the bank layer215. The first conductive layer217may have a tip portion217T protruding outward with respect to a center portion of the first pixel electrode221r. When viewed from a direction (e.g., z-axis direction) perpendicular to an upper surface of the substrate100, the tip portion217T of the first conductive layer217may have a loop shape surrounding (e.g., completely surrounding) the first pixel electrode221r.

A first opening OP1may expose a central portion of an upper surface of the first pixel electrode221rby penetrating the pixel defining layer213, the bank layer215, and the first conductive layer217, and the first emission layer222rto be described below may overlap and contact the first pixel electrode221rthrough the first opening OP1. Accordingly, the first opening OP1may define a first emission area EA1. An outside of the first emission area EA1may be defined as a non-emission area NEA. Further, a second opening OP2may define a second emission area EA2, and a third opening OP3may define a third emission area EA3.

A portion of the first conductive layer217may be spaced apart from the bank layer215in a direction (e.g., z-axis direction) perpendicular to the substrate100to have the tip portion217T protruding outward with respect to the center portion of the first pixel electrode221r. Because the tip portion217T of the first conductive layer217is formed by removing a portion of the sacrificial layer between the first conductive layer217and the bank layer215, the first conductive layer217may have an undercut structure/shape. Accordingly, the tip portion217T of the first conductive layer217may form an eaves structure in which a lower surface thereof is exposed. A protruding length of the tip portion217T of the first conductive layer217may be about 0.5 μm or more. In some embodiments, the protruding length of the tip portion217T of the first conductive layer217may be about 0.3 μm to about 1 μm or about 0.3 m to about 0.7 m.

The first conductive layer217may include a conductive material. For example, the first conductive layer217may include a conductive material including Mo, Al, Cu, Ti, or the like, and may include a multi-layer or a single layer that includes the above-mentioned material. For example, the first conductive layer217may have a double-layered structure of Al/Ti or a triple-layered structure of Ti/Al/Ti.

In an embodiment, a low-reflection layer may be disposed on the first conductive layer217. The low-reflection layer may be a layer having a lower surface reflectance than that of the first conductive layer217. The low-reflection layer may prevent light (e.g., external light) incident toward the display device2from being reflected from a surface of the first conductive layer217to be recognized by a user of the display device2.

In an embodiment, the low-reflection layer may include a low-reflection material. The low-reflection material may include a metal oxide having a high light absorption rate, e.g., a high extinction coefficient (k). For example, the low-reflection layer may include at least one of copper oxide (CuO), calcium oxide (CaO), molybdenum oxide (MoOx), and zinc oxide (ZnO). In some embodiments, the low-reflection layer may include a material obtained by mixing copper oxide (CuO) and calcium oxide (CaO).

A second remaining sacrificial layer214R may be between the first conductive layer217and the bank layer215. The second remaining sacrificial layer214R may be a remaining portion of the sacrificial layer removed to form the tip portion217T of the first conductive layer217. When viewed from a direction (e.g., z-axis direction) substantially perpendicular to the substrate100, the second remaining sacrificial layer214R may be spaced apart from the first pixel electrode221rby a certain distance, and may have a shape surrounding (e.g., completely surrounding) the first pixel electrode221r. Due to the second remaining sacrificial layer214R, the first conductive layer217may have an undercut structure/shape.

The second remaining sacrificial layer214R may determine the protruding length of the tip portion217T of the first conductive layer217. For example, the second remaining sacrificial layer214R may be positioned inside an end portion of the tip portion217T of the first conductive layer217, and the protruding length of the tip portion217T may be a length from a sidewall of the second remaining sacrificial layer214R to the end portion of the tip portion217T.

The second remaining sacrificial layer214R may include a material that is selectively etched without damaging the first pixel electrode221r, the bank layer215, and the first conductive layer217. For example, the second remaining sacrificial layer214R and the first remaining sacrificial layer212R may include the same material. The second remaining sacrificial layer214R may include indium gallium zinc oxide (IGZO) and/or indium zinc oxide (IZO).

The first emission layer222rmay be positioned over the first pixel electrode221rand the first conductive layer217. For example, the first emission layer222rmay be arranged to be in contact with the first pixel electrode221rthrough the first opening OP1. The first pixel electrode221rmay include a polymer organic material or a low-molecular-weight organic material, which emits light of the first color (e.g., red). In another example, the first emission layer222rmay include an inorganic material or quantum dots.

The first emission layer222rmay include a first functional layer and a second functional layer thereabove and/or therebelow. The first functional layer may include a hole transport layer (HTL) and/or a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and/or an electron injection layer (EIL).

FIG.18shows a single-stacked structure including a single emission layer, but in another example, the display device2may also have a tandem structure, that is a multi-stacked structure including a plurality of emission layers. In case that the display device2has a tandem structure, a charge generation layer (CGL) may be arranged between adjacent stacks of the multi-stacked structure.

The first emission layer222rmay be disconnected from a dummy portion222rpby the tip portion217T of the first conductive layer217. For example, the first emission layer222rmay include the same material and/or the same number of sub-layers (e.g., the first functional layer, the second functional layer, or the like) as that of the dummy portion222rp.

The first emission layer222rmay have at least one first hole222rhexposing a portion of an upper surface of the first conductive layer217.

The second emission layer222gmay include a polymer organic material or a low-molecular-weight organic material, which emits light of the second color (e.g., green), and the third emission layer222bmay include a polymer organic material or a low-molecular-weight organic material, which emits light of the third color (e.g., blue).

The first opposite electrode223rmay be disconnected from a dummy portion223rpby the tip portion217T of the first conductive layer217. The first opposite electrode223rand the dummy portion223rpmay include the same material.

The first opposite electrode223rmay include a transparent layer or a semi-transparent layer. The transparent layer or the semi-transparent layer may include Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), alloys thereof, or the like. In another example, the first opposite electrode223rmay further include a layer, such as ITO, IZO, ZnO, or In2O3, above the transparent layer or the semi-transparent layer including the materials described above.

A first inorganic encapsulation layer311may be disposed on the first opposite electrode223r. Because the first inorganic encapsulation layer311has a relatively excellent step coverage, the first inorganic encapsulation layer311may cover at least a portion of an exposed lower surface of the tip portion217T of the first conductive layer217. For example, the first inorganic encapsulation layer311may be continuously formed to cover upper and side surfaces of the first opposite electrode223r, a side surface of the first emission layer222r, side and lower surfaces of the tip portion217T of the first conductive layer217, a side surface of the second remaining sacrificial layer214R, and an upper surface of the bank layer215.

The first inorganic encapsulation layer311may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxynitride (SiOxNy), and silicon oxide (SiOx). The first inorganic encapsulation layer311may be in contact with (e.g., in direct contact with) a metal surface at the side and lower surfaces of the tip portion217T of the first conductive layer217to form an inorganic contact region ICR. Accordingly, the inorganic contact region ICR may form a closed loop surrounding (e.g., completely surrounding) the first organic light-emitting diode OLED1to minimize (or block) a path through which impurities, such as moisture and/or air, penetrate.

As shown inFIG.18, a second inorganic encapsulation layer312may seal the second organic light-emitting diode OLED2, and a third inorganic encapsulation layer313may seal the third organic light-emitting diode OLED3. As the first inorganic encapsulation layer311, the second inorganic encapsulation layer312, and the third inorganic encapsulation layer313form the inorganic contact region ICR in the display area DA, an inorganic contact region of the peripheral area PA (refer toFIG.16) required to reduce the peeling defect due to emission layer may be reduced. For example, as an organic light-emitting diode is sealed in units of pixels, although a path through which impurities, such as moisture and/or air, penetrate occurs at one pixel or at the boundary of the substrate100, a resulting defect may be prevented from being propagated to neighboring pixels.

An organic planarization layer410may be arranged to cover the first inorganic encapsulation layer311, the second inorganic encapsulation layer312, and the third inorganic encapsulation layer313. The organic planarization layer410may cover irregularities caused by the pixel defining layer213, the bank layer215, and the first conductive layer217to provide a flat base surface for components disposed on an upper portion of the organic planarization layer410. The organic planarization layer410may include a polymer-based material. The polymer-based material may include an acrylic resin, an epoxy resin, polyimide, polyethylene, or the like.

In an embodiment, a refractive index of the organic planarization layer410may be greater than a refractive index of each of the first inorganic encapsulation layer311, the second inorganic encapsulation layer312, and the third inorganic encapsulation layer313. For example, the refractive index of the organic planarization layer410may be about 1.6 or more. The refractive index of the organic planarization layer410may be about 1.6 to about 1.9. The organic planarization layer410may further include dispersed particles for high refractive index. For example, metal oxide particles, such as zinc oxide (ZnOx), titanium oxide (TiO2), zirconium oxide (ZrO2), barium titanate (BaTiO3), or the like, may be dispersed in the organic planarization layer410.

A protective layer420may be disposed on the organic planarization layer410. The protective layer420may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxynitride (SiOxNy), and silicon oxide (SiOx). In an embodiment, a refractive index of the protective layer420may be less than the refractive index of the organic planarization layer410.

An anti-reflection layer500including a first color filter510, a second color filter520, a third color filter530, a light-blocking layer540, and an overcoat layer550may be disposed on the protective layer420. The anti-reflection layer500may reduce the reflectance of light (e.g., external light) incident from the outside toward the display device2.

The light-blocking layer540may overlap the bank layer215and the first conductive layer217to at least partially absorb light reflected by the bank layer215and the first conductive layer217in a non-emission area NEA. For example, the non-emission area NEA may be defined as an area that does not overlap the first emission area EA1, the second emission area EA2, and the third emission area EA3. The light-blocking layer540may include black pigment. The light-blocking layer540may be a black matrix. The light-blocking layer540may include a first filter opening540OP1corresponding to the first emission area EA1, a second filter opening540OP2corresponding to the second emission area EA2, and a third filter opening540OP3corresponding to the third emission area EA3.

The first color filter510may be positioned in the first filter opening540OP1to correspond to the first emission layer222rdisposed therebelow. The first color filter510may selectively transmit light emitted by the first emission layer222r. For example, the first color filter510as shown inFIG.18may be a red color filter that selectively transmits red light.

For example, the second color filter520may be positioned in the second filter opening540OP2to correspond to the second emission layer222g. The second color filter520may selectively transmit light emitted by the second emission layer222g. The third color filter530may be positioned in the third filter opening540OP3to correspond to the third emission layer222b. The third color filter530may selectively transmit light emitted by the third emission layer222b. For example, the second color filter520as shown inFIG.18may be a green color filter that selectively transmits green light, and the third color filter530may be a blue color filter that selectively transmits blue light.

The overcoat layer550may be disposed on the first to third color filters510,520, and530. The overcoat layer550may be a transparent layer, which covers irregularities caused by the first to third color filters510,520, and530and the light-blocking layer540and provide a flat upper surface. The overcoat layer550may include a colorless transparent organic material, such as an acrylic resin.

According to embodiments, durability and manufacturing efficiency of an apparatus for manufacturing a display device may be improved.