Method and apparatus to test the power-on-reset trip point of an integrated circuit

Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuit technology. More particularly, the present invention relates to circuits and methods for testing on-chip power-on-reset circuits

2. The Prior Art

In an integrated circuit, a power-on-reset circuit is used to generate a negative or positive pulse to reset the entire chip when power is ramping up so that the on-chip circuitry is in a known reset state. The highest VCCat which the whole chip is still in the reset mode is called the power-on-reset trip point.

The power-on-reset trip point can not be set to too low a value because the on-chip circuitry will not be working properly at values of VCCthat are too low. In other words, the entire chip will not be reset properly to a known reset state. In addition, the power-on-reset trip point can not be set to too high a value because the on-chip circuitry will still be in reset mode at too high a value of VCC.

In order to determine the power-on-reset trip point, the minimum value of VCCat which the chip is still working is characterized during the debugging and qualification stages of the chip development. Due to process variations, including, but not limited to lot-to-lot variations, wafer-to-wafer variations, variations across a wafer, or individual defects, or the sensitivities of the power-on-reset circuit to temperature, layout, or process parameters, the actual power-on-reset trip point may vary from die to die and may be different from the characterized value.

The power-on-reset trip point is not tested, or not 100% tested before shipping. In the prior art, no special power-on-reset trip point test circuit is embedded. The power-on-reset trip point shift, especially shifting to a lower trip point, is causing field application failure.

BRIEF DESCRIPTION OF THE INVENTION

Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A duplicate power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.

A method for testing a power-on-reset circuit in an integrated circuit according to the present invention includes providing a duplicate power-on-reset circuit; selectively coupling a signal related to the output of the duplicate power-on-reset circuit to an I/O pad on the integrated circuit; and sensing the signal at the I/O pad on the integrated circuit.

DETAILED DESCRIPTION OF THE INVENTION

Referring now toFIG. 1, a schematic diagram shows an illustrative power-on-reset test circuit10according to the principles of the present invention. Power-on-reset test circuit10includes a first I/O pad12. A series string of diode-connected n-channel MOS transistors14,16,18,20,22, and24is connected between the first I/O pad12and ground. N-channel MOS transistor24is a weak device, i.e., formed at the minimum device size for the process technology employed.

N-channel MOS transistors14,16,18,20,22, and24together function as a high-voltage detector. If a voltage of, for example, 12 volts, is placed on first I/O pad12if high voltage (for example, 12V) is applied to high voltage detector, the voltage at the drain of n-channel MOS transistor22will be about 4V and the voltage at the drain of n-channel MOS transistor24will be about 2V. If VDDor 0V is applied to first I/O pad12, the voltage at the drain of n-channel MOS transistor22will be about 1V and the voltage at the drain of n-channel MOS transistor24will be about 3V.

A first inverter26includes n-channel MOS transistor28and p-channel MOS transistor30. First inverter26is powered by VDDand has an input coupled to the drain of n-channel MOS transistor24. The n-well containing p-channel MOS transistor30in inverter26is biased at VDD.

A second inverter32includes n-channel MOS transistor34and p-channel MOS transistor36. Second inverter32is powered by the voltage at the drain of n-channel MOS transistor22and has an input coupled to the output of first inverter26. The n-well containing p-channel MOS transistor36in inverter32is biased at the voltage at the drain of n-channel MOS transistor22.

A third inverter38includes n-channel MOS transistor40and p-channel MOS transistor42. Third inverter38is powered by the voltage at the drain of n-channel MOS transistor22and has an input coupled to a second I/O pad44. The n-well containing p-channel MOS transistor42in inverter38is biased at the voltage at the drain of n-channel MOS transistor22.

A duplicate power-on-reset circuit46(POR′) has an output coupled to n-channel MOS transistor48. N-channel MOS transistor48is used as a pass gate to transfer the output of duplicate power-on-reset circuit46. It is preferred to use a duplicate power-on-reset circuit rather than the original power-on-reset circuit in the integrated circuit in order to avoid affecting the performance of the power-on-reset circuit used by the integrated circuit, although the original power-on-reset circuit may be used in accordance with the present invention. The gate of n-channel MOS transistor48is driven by the output of third inverter38.

N-channel MOS transistor50is connected in series with n-channel MOS transistor48. N-channel MOS transistor50is also used as a pass gate for the signal out of the duplicate power-on-reset circuit46. The gate of n-channel MOS transistor50is driven by the output of second inverter32.

After passing through n-channel MOS transistor48and n-channel MOS transistor50, the output of the duplicated power-on-reset circuit46is connected to the gate of n-channel MOS pulldown transistor52. As presently preferred, n-channel MOS pulldown transistor52should be a large enough device to make the switching time acceptably small for the test times that are desired to be achieved as will be appreciated by persons of ordinary skill in the art. The source of n-channel MOS pulldown transistor52is coupled to ground and its drain is coupled to an I/O pad54.

N-channel MOS pulldown transistor56has its drain coupled to the gate of n-channel MOS pulldown transistor52, its source coupled to ground, and its gate is driven by the output of first inverter26. Persons of ordinary skill in the art will appreciate that n-channel MOS pulldown transistor52will be turned off if the output of first inverter26is a logic “1”, since n-channel MOS pulldown transistor56will be turned on, pulling the gate of n-channel MOS pulldown transistor52to ground. Conversely, such skilled persons will appreciate that n-channel MOS pulldown transistor56will be turned off if the output of the first inverter26is a logic “0” and the gate of n-channel MOS pulldown transistor52will therefore be controlled by the signal at the output of duplicate power-on-reset circuit46through pass gate transistors48and50.

FIG. 1also shows the operational power-on-reset circuit58disposed on the integrated circuit. Power-on-reset circuit58is coupled to circuits on the integrated circuit to reset them to known states upon power-up of the integrated circuit as is known in the art. Power-on-reset circuit58and duplicate power-on-reset circuit46are preferably formed using identical components and are disposed near one another or adjacent to one another on the integrated circuit die so that they will have characteristics that are as nearly identical as possible. In this manner, the duplicate power-on-reset circuit46can be used for testing with reasonable assurances that its output will closely track the output of power-on-reset circuit58that is actually used to perform the reset function in the integrated circuit.

The operation of the illustrative circuit shown inFIG. 1has two modes, one in which the integrated circuit is in normal operating mode and the other when the integrated circuit is in the power-on-reset trip point test mode. He normal operating mode of the integrated circuit will be disclosed first.

During the normal operating mode of the integrated circuit, I/O pad12will be at either VDDor 0V, I/O pad44will be at either VDDor 0V, and I/O pad54will be in a high impedance state. The drains of n-channel MOS transistors22and24will be logic “0.” Consequently, the input of inverter26will be at a logic “0,” and its output will be a logic “1.” N-channel MOS pulldown transistor56will be turned on and n-channel MOS pulldown transistor52will thus be turned off. The input to second inverter32will be a logic “1” and its output will be at a logic “0,” partly because its power supply is turned off. The power supply of third inverter38will also be turned off and its output will be at a logic “0.” N-channel MOS transistor50will be turned off. The output of the duplicate power-on-reset circuit46will not be passed to the gate of n-channel MOS transistor52.

The power-on-reset trip point test according to the present invention is done in a sequence as will be disclosed herein. An exemplary test sequence is disclosed herein. The voltages (for example, 2V, 1V, 1.7V, 1.1V) expressed herein are merely for the purposes of illustration. Persons of ordinary skill in the art will appreciate that other potentials may be used depending on the integrated circuit voltage specifications.

First, the circuit is tested while the integrated circuit should still be in the reset mode. It is desired that the chip is in the reset mode at VDD=1.1V assuming that nominal VDDis about 1.7V. Therefore, a VDDvoltage of about 1.1V is used for this test.

To perform the test, I/O pad44is placed at ground potential and the integrated circuit is powered up or down to VDD=1.1V. I/O pad54is connected to a tester. A high voltage (e.g., 12V) is applied to I/O pad12. With 12V at I/O pad12, the drain of n-channel MOS transistor22is at about 3V and the drain of n-channel MOS transistor24is at about 1V. Under these conditions, second and third inverters32and38will be supplied with power, and the input to the first inverter26will be a logic “1,” making its output a logic “0.” N-channel MOS pulldown transistor56will be turned off, allowing the gate of n-channel MOS pulldown transistor52to operate. The output of second inverter32will be a logic “1,” turning on n-channel MOS transistor50.

Because I/O pad44is at ground, the input to third inverter38is at a logic “0” and its output is at a logic “1,” thus turning on n-channel MOS transistor48. Because n-channel MOS transistors48and50are both turned on, the output of duplicate power-on-reset circuit46is presented to the gate of n-channel MOS pulldown transistor52.

Current is forced into I/O pad54from the tester. If I/O pad54is “high” and will sink no current, the integrated circuit is still in the reset mode because n-channel MOS pulldown transistor52is not turned on, assuming that the output of duplicate power-on-reset circuit46is low when there is a reset. This means that the power-on-reset trip point is higher than 1.1V and the integrated circuit passes the first checkpoint of the power-on-reset trip point test. If I/O pad54is “low” and will sink current, this means that n-channel MOS pulldown transistor54is turned on and that the integrated circuit is not in the reset mode. The integrated circuit fails the test because the power-on-reset trip point is lower than 1.1V.

Next, the circuit is tested at a VDDvoltage of 1.7V. At this voltage, the integrated circuit should not still be in the reset mode, since 1.7V is the normal operating value of VDD. The VDDvoltage is raised from 1.1V to 1.7V and the tester again forces current into I/O pad54. If I/O pad54is “low” and will sink current, n-channel MOS pulldown transistor52is turned on and the integrated circuit has exited the reset mode. This means that the power-on-reset trip point is lower than 1.7V and the integrated circuit passes the second checkpoint of the power-on-reset trip point test. If I/O pad54is “high” and will not sink current, n-channel MOS pulldown transistor52is still off, meaning that the integrated circuit is still in the reset mode. The integrated circuit fails the test because the power-on-reset trip point is higher than 1.7V, and that will affect normal operation at VDD=1.7V.

If the integrated circuit passes both checkpoints, it means the power-on-reset trip point is higher than 1.1V and below 1.7V. Persons of ordinary skill in the art will observe that the test can be performed at other intermediate values of VDDto more precisely identify the trip point of the power-on-reset circuit.

Referring now toFIG. 2, a timing diagram illustrates the waveforms at selected circuit nodes to help explain the operation of the present invention. The first trace represents the waveform present at the VDDnode of the integrated circuit. The second trace represents the waveform present at I/O pad12of the integrated circuit, which triggers a test event. The third trace represents the waveform present at I/O pad44of the integrated circuit. The fourth trace represents the waveform present at circuit node “A” of the integrated circuit, which is located at the input to inverter26. The fifth trace represents the waveform present at circuit node “B” of the integrated circuit, which is located at the source of the p-channel MOS transistor36of inverter32. The sixth trace represents the waveform present at circuit node “C” of the integrated circuit, which is located at the gate of the n-channel MOS transistor48. The seventh trace represents the waveform present at circuit node “P” of the integrated circuit, which is located at the output of POR′ circuit46. The eighth trace represents the waveform present at circuit node “D” of the integrated circuit, which is located at the output of inverter26. The ninth trace represents the waveform present at circuit node “E” of the integrated circuit, which is located at the input to inverter32. The tenth trace represents the waveform present at circuit node “F” of the integrated circuit, which is located at the gate of the n-channel MOS transistor52. Finally, the eleventh trace represents the waveform present at I/O pad54of the integrated circuit.FIG. 2provides an illustration of the operation of the circuit ofFIG. 1in the manner previously described.

The solid-line trace at node P represents the case where a low output from the POR circuit indicates a reset state. The dashed lines present in the traces for nodes P, F, and I/O pad54illustrate an embodiment where a high output from the POR circuit indicates a reset state.

The present invention provides several advantages. By employing the present invention, the power-on-reset trip point of every integrated circuit can be tested before shipping with a simple and short “go/no-go” test. In addition, field failure due to shifting of the power-on-reset trip point with time, especially a shift to a lower trip point, can be scanned and prevented. Finally, the short test time means cost savings to the manufacturer.