Layout pattern for improved MOS device matching

This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits. The layout uses dummy Metal oxide field effect transistors, or MOSFETs, to keep the environment the same around each of the MOSFETs in a matched pair. The MOSFETs in a matched pair are in a single row with each MOSFET in the matched pair having dummy MOSFETs adjacent to it on either side. The dummy MOSFETs can be part of the matched pair, can be used in other parts of the circuit, or may not be used. The use of dummy MOSFETs keeps the environment around each MOSFET in the matched pair the same and this improves the matching characteristics.

BACKGROUND OF THE INVENTION 
(1) Field of the Invention 
This invention provides a circuit layout pattern and layout method for 
matching pairs of metal oxide semiconductor field effect transistors used 
in matched pairs in precision analog circuits. 
(2) Description of the Related Art 
Matched pairs of transistors are important in precision analog circuits. 
There are conventional layout methods to design matched pairs in 
integrated circuit elements, such as cross-coupled metal oxide 
semiconductor field effect transistor layouts. These methods use a 
relatively large area of the integrated circuit element and do not handle 
short channel lengths of about 1.0 micrometer or less effectively. 
The layout methods of this invention use a smaller area of the integrated 
circuit element and produce good matching results at channel lengths as 
low as 0.8 micrometers. 
SUMMARY OF THE DISCLOSURE 
Matching the parameters of metal oxide field effect transistors, or 
MOSFETs, is very important when the MOSFETs are used in critical analog 
circuits. FIG. 1 shows a conventional cross-coupled layout of four P 
channel metal oxide semiconductor field effect transistors, or PMOSFETs, 
in an integrated circuit element. The first, second, third, and fourth 
PMOSFETs are laid out in a rectangle as shown in FIG. 1. The first PMOSFET 
has a first channel diffusion area 100, a first gate electrode 103, and a 
first drain electrode 101, and a first source electrode 102. The second 
PMOSFET has a second channel diffusion area 110, a second gate electrode 
113, and a second drain electrode 111, and a second source electrode 112. 
The third PMOSFET has a third channel diffusion area 120, a third gate 
electrode 123, and a third drain electrode 121, and a third source 
electrode 122. The fourth PMOSFET has a fourth channel diffusion area 130, 
a fourth gate electrode 133, and a fourth drain electrode 131, and a 
fourth source electrode 132. The first 100, second 110, third 120, and 
fourth 130 channel diffusion areas are rectangular each rectangle having 
two long sides and two short sides. 
As shown in FIG. 1 the PMOSFETs are in a 2.times.2array with the first 
PMOSFET and second PMOSFET in the first row, the third PMOSFET and fourth 
PMOSFET in the second row, the first PMOSFET and third PMOSFET in the 
first column, and the second PMOSFET and fourth PMOSFET in the second 
column. The long sides of the channel diffusion areas 100, 110, 120, and 
130 lie on four parallel lines. The short sides of the channel diffusion 
areas 100, 110, 120, and 130 lie on four parallel lines which are 
perpendicular to the lines containing the long sides. FIG. 2 shows the 
sources of the four PMOSFETs connected together at a source node 17 for 
test purposes. The drains of the second PMOSFET 11 and third PMOSFET 12 
are connected together at a first common node 15 and the drains of the 
first PMOSFET 10 and fourth PMOSFET 13 are connected together at a second 
common node 16. The first PMOSFET 10 and the fourth PMOSFET 13 form a 
first transistor in the matched pair, and the second PMOSFET 11 and third 
PMOSFET 12 form a second transistor in the matched pair in the 
cross-coupled arrangement. 
FIG. 3 shows the mismatching test results as a function of PMOSFET size, 
for channel widths between about 0.8 micrometers and 20 micrometers and 
channel lengths between about 0.65 micrometers and 4.0 micrometers, for 
cross-coupled PMOSFET arrays as described above and shown in FIGS. 1 and 
2. The curves in FIG. 3 show the mean difference in threshold voltage 36 
in millivolts, the standard deviation of the difference in threshold 
voltage 31, the mean difference of drain current factor 34 in percent, the 
standard deviation of the difference of drain current factor 35, the mean 
difference in drain current 33 in percent, and the standard deviation of 
the difference in drain current 32 all as a function of PMOSFET size. 
Drain current factor, .beta., is defined by the equation 
I.sub.d=.beta.(V.sub.g -V.sub.t).sup..alpha. ; where I.sub.d, is the drain 
current, V.sub.g is the gate voltage, V.sub.t is the threshold voltage, 
and .alpha. is the velocity factor. The PMOSFET sizes are for a channel 
width of about 20 micrometers with channel lengths of 0.65, 0.9, 1.1, 1.6, 
2.0, and 4.0 micrometers; a channel width of 1.6 micrometers; with channel 
lengths of 0.65, 0.9, 1.1, and 1.6 micrometers; a channel width of 1.2 
micrometers with a channel length of 0.9 micrometers; and a channel width 
of 0.8 micrometers with a channel length of 0.9 micrometers. As can be 
seen in FIG. 3 the mismatching increases as the channel width or channel 
length decreases. 
It is a principle objective of this invention to provide a circuit layout 
of metal oxide semiconductor field effect transistors, or MOSFETs, which 
will provide improved matching of matched pairs of transistors used in 
analog circuits and extend to lower channel widths or channel lengths. 
It is another principle objective of this invention to provide a method of 
matching of metal oxide semiconductor field effect transistors, or 
MOSFETs, for use as matched pairs in analog circuits and extend to lower 
channel widths or channel lengths. 
These objectives are accomplished by using a circuit layout of MOSFETs 
which places a number of MOSFETs in a row in an integrated circuit 
element, such as that shown in FIG. 4. In this type of circuit layout 
there is a dummy MOSFET on either side of each MOSFET which is part of a 
matched pair of MOSFETs. The MOSFETs of the matched pair are adjacent to 
each other in the row. FIG. 4 shows a first MOSFET 401, a second MOSFET 
402, a third MOSFET 403, and a fourth MOSFET 404 arranged in a row such 
that a line representing the direction of source to drain current flow of 
each MOSFET is parallel to the line representing the direction of source 
to drain current flow of the other transistors in the row. The dummy 
MOSFET can be a part of the matched pair, can be used for other purposes, 
or need not be used. The presence of the dummy MOSFETs on either side of 
each MOSFET in the matched pair provides significant improvement of the 
matching characteristics of the matched pair. 
As an example refer to FIG. 4. If the second MOSFET 402 and the third 
MOSFET 403 make up the matched pair, the first MOSFET 401 and the third 
MOSFET 403 serve as the dummy MOSFETs for the second MOSFET 402, and the 
second MOSFET 402 and the fourth MOSFET 404 serve as the dummy MOSFETs for 
the third MOSFET 403. The second MOSFET 402 serves as a dummy MOSFET for 
the third MOSFET 403 even though it is part of the matched pair of 
MOSFETs.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring now to FIGS. 4, 5, and 6, there is shown an embodiment of the 
MOSFET circuit layout array of this invention for MOSFET matching. FIG. 4 
shows a first MOSFET 401, a second MOSFET 402, a third MOSFET 403, and a 
fourth MOSFET 404 arranged in an integrated circuit element in a row such 
that a line representing the direction of source to drain current flow of 
each MOSFET is parallel to the line representing the direction of source 
to drain current flow of the other transistors in the row. In this 
embodiment there is a dummy MOSFET on either side of the MOSFET which is 
part of the matched pair. The MOSFETs which make up the matched pair are 
adjacent to each other. The dummy MOSFET can be a part of the matched 
pair, can be used for other purposes, or need not be used. The presence of 
the dummy MOSFETs on either side of each MOSFET in the matched pair 
provides significant improvement of the matching characteristics of the 
matches pair. 
As an example refer to FIG. 4. If the second MOSFET 402 and the third 
MOSFET 403 make up the matched pair, the first MOSFET 401 and the third 
MOSFET 403 serve as the dummy MOSFETs for the second MOSFET 402, and the 
second MOSFET 402 and the fourth MOSFET 404 serve as the dummy MOSFETs for 
the third MOSFET 403. The second MOSFET 402 serves as a dummy MOSFET for 
the third MOSFET 403 even though it is part of the matched pair of 
MOSFETs. 
Refer now to FIG. 5, there is shown a circuit layout array of MOSFETs in an 
integrated circuit element used for evaluating MOSFET matching 
characteristics. There are twelve MOSFETs in the layout of this embodiment 
a first MOSFET 201, a second MOSFET 202, a third MOSFET 203, a fourth 
MOSFET 204, a fifth MOSFET 205, and a sixth MOSFET 206 in a first row of 
the array; and a seventh MOSFET 207, an eighth MOSFET 208, a ninth MOSFET 
209, a tenth MOSFET 210, an eleventh MOSFET 211, and a twelfth MOSFET 212 
in a second row of the array. A single source electrode 216 connects the 
source contacts of all the MOSFETs in the array. A first gate electrode 
215 forms the gate for the first, second, third, fourth, fifth, and sixth 
MOSFETs. A second gate electrode 217 forms the gate for the seventh, 
eighth, ninth, tenth, eleventh, and twelfth MOSFETs. Each MOSFET has an 
identical drain electrode 225 connected to the drain contact. Each MOSFET 
has an identical rectangular channel diffusion area. 
The rectangular diffusion area 20 is shown in FIG. 6. Each rectangular 
diffusion area 20 has a width 22, a top edge 221, a bottom edge 222, an 
inside edge 223, and an outside edge 224. The inside edges 223 and the 
outside edges 224 of the MOSFETs in the first row of the array are all 
parallel to each other as are the inside edges 223 and the outside edges 
224 of the second row of the array. The top edges 221 of the MOSFETs in 
the first row of the array are co-linear, the bottom edges 222 of the 
MOSFETs in the first row of the array are co-linear, the top edges 221 of 
the MOSFETs in the second row of the array are co-linear, and the bottom 
edges 222 of the MOSFETs in the second row of the array are co-linear. The 
top edges 221 of the MOSFETs in the first row of the array, the bottom 
edges 222 of the MOSFETs in the first row of the array, the top edges 221 
of the MOSFETs in the second row of the array, and the bottom edges 222 of 
the MOSFETs in the second row of the array lie on parallel lines. 
The inside edges 223 of the first and seventh MOSFET are co-linear, the 
outside edges 224 of the first and seventh MOSFET are co-linear, the 
inside edges 223 of the second and eighth MOSFET are co-linear, the 
outside edges 224 of the second and eighth MOSFET are co-linear, the 
inside edges 223 of the third and ninth MOSFET are co-linear, the outside 
edges 224 of the third and ninth MOSFET are co-linear, the inside edges 
223 of the fourth and tenth MOSFET are co-linear, the outside edges 224 of 
the fourth and tenth MOSFET are co-linear, the inside edges 223 of the 
fifth and eleventh MOSFET are co-linear, the outside edges 224 of the 
fifth and eleventh MOSFET are co-linear, the inside edges 223 of the sixth 
and twelfth MOSFET are co-linear, and the outside edges 224 of the sixth 
and twelfth MOSFET are co-linear. The top edges 221 and bottom edges 222 
are perpendicular to the inside edges 223 and the outside edges 224. 
FIG. 6 shows a section of the gate electrode 21 crossing the rectangular 
channel diffusion area 20. The width of the channel 22 is determined by 
the width of the rectangular channel diffusion area 20. The length of the 
channel is determined by the width 23 of the gate electrode 21. 
FIG. 7 shows a schematic diagram of the circuit layout of FIG. 5. The first 
201, second 202, third 203, fourth 204, fifth 205, and sixth 206 MOSFETs 
are in the first row and the seventh 207, eighth 208, ninth 209, tenth 
210, eleventh 211, and twelfth 212 MOSFETs are in the second row. The 
sources of all MOSFETs are connected to a source terminal 216, the gates 
of the top row of MOSFETs are connected to a first gate terminal 215, and 
the gates of the MOSFETs in the second row are connected to a second gate 
terminal 217. The drain connections of each MOSFET are connected to 
separate terminals 225. 
In order to be part of a matched pair of MOSFETs a MOSFET must have a dummy 
MOSFET adjacent to the inside edge of its channel diffusion area, a dummy 
MOSFET adjacent to the outside edge of its channel diffusion area, and be 
adjacent to the other MOSFET in the matched pair. Referring again to FIG. 
5, the second and third MOSFETs can form a matched pair as can the eighth 
and ninth MOSFETs but the first and second MOSFETs cannot. The dummy 
MOSFET makes the environment around both MOSFETs of the matched pair 
nearly identical and thereby improves the matching characteristics of the 
pair. 
Refer now to FIG. 8, there is shown the mismatching results of twelve N 
channel MOSFETs with a channel width of 20 micrometers and a channel 
length of 0.8 micrometers made according to the circuit layout of FIGS. 5 
and 7. The curves show the mean difference in threshold voltage in 
millivolts between MOSFETs in the pair 71, the standard deviation of the 
difference in threshold voltage between MOSFETs in the pair 72, the mean 
of the difference in drain current factor between MOSFETs in the pair 73, 
the standard deviation of difference in drain current factor between 
MOSFETs in the pair 74, the mean difference in drain current in percent 
between MOSFETs in the pair 75, and the standard deviation of the 
difference in drain current between MOSFETs in the pair 76 all as a 
function of MOSFET pair. As can be seen from FIG. 8 the mismatching 
results of pairs of MOSFETs which meet the matched pair criteria of a 
dummy MOSFET on either side of each MOSFET in the pair; second and third 
MOSFETs, third and fourth MOSFETs, and fourth and fifth MOSFETs are very 
good. The mismatching results of the pairs of MOSFETs where one of the 
MOSFETs in the pair is not adjacent to a dummy MOSFET; first and second 
MOSFETs, fifth and sixth MOSFETs, first and seventh MOSFETs, and first and 
twelfth MOSFETs have less desirable results. 
Refer now to FIG. 9, there is shown the mismatching results of twelve N 
channel MOSFETs with a channel width of 20 micrometers and a channel 
length of 2.0 micrometers made according to the circuit layout of FIGS. 5 
and 7. The curves show the mean difference in threshold voltage in 
millivolts between MOSFETs in the pair 81, the standard deviation of the 
difference in threshold voltage between MOSFETs in the pair 82, the 
difference in drain current factor between MOSFETs in the pair 83, the 
standard deviation of the difference in drain current factor between 
MOSFETs in the pair 84, the mean difference in drain current in percent 
between MOSFETs in the pair 85, and the standard deviation of the 
difference in drain current between MOSFETs in the pair 876 all as a 
function of MOSFET pair. As can be seen from FIG. 9 the mismatching 
results of pairs of MOSFETs which meet the matched pair criteria of a 
dummy MOSFET on either side of each MOSFET in the pair; second and third 
MOSFETs, third and fourth MOSFETs, and fourth and fifth MOSFETs are very 
good. The mismatching results of the pairs of MOSFETs where one of the 
MOSFETs in the pair is not adjacent to a dummy MOSFET; first and second 
MOSFETs, fifth and sixth MOSFETs, first and seventh MOSFETs, and first and 
twelfth MOSFETs have less desirable results. 
The results shown in FIGS. 8 and 9 show that the matched pairs of this 
invention produce good matching results over a wide range of channel width 
to channel length ratios. The use of dummy MOSFETs make it possible to use 
short channel devices, as low as 0.65 micrometers, in matched pairs. These 
layout methods also use less integrated circuit element area. The results 
shown in FIGS. 8 and 9 also show that the matched pairs of this invention 
produce much better matching results than the conventional methods of 
forming matched pairs. 
Refer now to FIGS. 10 and 11. The circuit layout of FIG. 10 can be used to 
form the analog circuit of FIG. 11. As shown in FIG. 10, the first 301, 
second 302, third 303, fourth 304, fifth 305, and sixth 306 MOSFETs are in 
a single row in the integrated circuit element. A first matched pair is 
formed from the second 302 and third 303 MOSFETs and a second matched pair 
is formed from the fourth 304 and fifth 305 MOSFETs. The first 301 MOSFET 
serves as a dummy MOSFET for the second MOSFET and the sixth 306 MOSFET 
serves as a dummy for the fifth 305 MOSFET. FIG. 11 shows a schematic 
diagram where the matched pairs are used in an analog circuit, the second 
302 and third 303 MOSFETs forming a first matched pair and the fourth 304 
and fifth 305 MOSFETs forming a second matched pair. The interconnection 
310 between the fourth 304 and fifth 305 MOSFETs, the interconnection 311 
between the second 302 and third 303 MOSFETs, the interconnection 312 
between the third 303 and fifth 305 MOSFETs, and the interconnection 313 
between the second 302 and fourth 304 MOSFETs are shown in FIGS. 10 and 
11. 
While the invention has been particularly shown and described with 
reference to the preferred embodiments thereof, it will be understood by 
those skilled in the art that various changes in form and details may be 
made without departing from the spirit and scope of the invention.