ESL TFT substrate structure and manufacturing method thereof

The present invention provides an ESL TFT substrate structure and a manufacturing method thereof. In the ESL TFT substrate structure, an etch stop layer (5) includes a first via (51) and a second via (52) formed therein to correspond to two side portions of an oxide semiconductor layer (4). A drain terminal (6) is set in engagement with the oxide semiconductor layer (4) through the first via (51). A passivation protection layer (7) includes a through hole (72) formed therein to extend to and communicate with the second via (52). An electrode layer (8) is formed on the passivation protection layer (7) and has a side portion that is adjacent to the drain terminal (6) and is set in engagement with the oxide semiconductor layer (4) through the through hole (72) and the second via (52) to form a source terminal (81) and an opposite side portion that is extended in a direction away from the drain terminal (6) to form a pixel electrode (82). The ESL TFT substrate structure has a reduced channel length so as to provide the TFT with excellent electrical conduction performance and also to reduce the size of the TFT thereby increasing an aperture ratio of pixels and reducing difficult of pixel design.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of displaying technology, and in particular to an ESL (Etch Stop Layer) TFT (Thin-Film Transistor) substrate structure and a manufacturing method thereof.

2. The Related Arts

In the field of displaying technology, flat panel displays, such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, are gradually taking the place of cathode ray tube (CRT) displays and are widely used in liquid crystal televisions, mobile phones, personal digital assistants, digital cameras, computer monitors, and notebook computer screens.

A display panel is an important component of LCDs and OLEDs. For display panels of both the LCDs and the OLEDs, they are often composed of a thin-film transistor (TFT) substrate. Taking an LCD display panel as an example, it is generally composed of a TFT substrate, a color filter (CF) substrate, and a liquid crystal layer interposed between the two substrates, of which the principle of operation is that a drive voltage is applied to the TFT substrate and the CF substrate to control molecules of the liquid crystal to rotate in order to refract out light from a backlight module for generating an image.

Currently, the known TFT substrates are generally classified in various types, including coplanar type, etch stop layer (ESL), and back channel etch (BCE).

Referring toFIG. 1, a conventional ESL TFT substrate comprises a base plate10and a gate terminal20, a gate insulation layer30, an oxide semiconductor layer40, an etch stop layer50, a source terminal60, a drain terminal62, a passivation protection layer70, and a pixel electrode80that are sequentially formed on the base plate10.

The ESL TFT substrate shown inFIG. 1comprises an etch stop layer (ESL) to protect a back channel from being damaged. However, due to errors of accuracy of a manufacturing process (such as alignment error of an exposure operation and line width deviation in an etching operation), the source terminal61and the drain terminal62must overlap the etch stop layer50by predetermined lengths L1, L3, this plus a minimum length L2of a gap between the source terminal61and the drain terminal62that is present due to the capability of the state of the art making the actual length of the channel L the sum of L1, L2, and L3, namely L=L1+L2+L3, which is greater than the back channel length of a BCE TFT substrate. The length of the back channel of a BCE TFT is corresponding to the minimum gap length L2between the source terminal and the drain terminal.

The greater channel length L may deteriorate the electrical conduction performance of the TFT and may also enlarge the overall size of the TFT, leading to reduction of an aperture ratio of pixels and increasing the difficult of pixel design.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an ESL TFT substrate structure, which has a reduced channel length so as to, on the one hand, provide the TFT with excellent electrical conduction performance and, on the other hand, reduce the overall size of the TFT to thereby increase an aperture ratio of pixels and reduce difficult of pixel design.

An object of the present invention is also to provide a manufacturing method of an ESL TFT substrate, which reduces a channel length, improves electrical conduction performance of the TFT, and also reduces the overall size of the TFT so as to increase an aperture ratio of pixels and reduce difficult of pixel design.

To achieve the above objects, the present invention provides an ESL TFT substrate structure, which comprises:

a base plate;

a gate terminal formed on the base plate;

a gate insulation layer formed on the gate terminal and the base plate;

an oxide semiconductor layer located above the gate terminal and formed on the gate insulation layer;

an etch stop layer formed on the oxide semiconductor layer, wherein the etch stop layer comprises a first via and a second via formed therein to respectively correspond to two side portions of the oxide semiconductor layer;

a drain terminal formed on the etch stop layer and in engagement with the oxide semiconductor layer through the first via;

a passivation protection layer formed on the drain terminal and the etch stop layer, wherein the passivation protection layer comprises a through ole formed therein to extend to and communicate with the second via; and

an electrode layer formed on the passivation protection layer wherein the electrode layer has one side portion that is adjacent to the drain terminal and is in engagement with the oxide semiconductor layer through the through hole and the second via to form a source terminal; and the electrode layer has an opposite side portion that is extended in a direction away from the drain terminal to form a pixel electrode.

The source terminal and the drain terminal do not overlap in a space above the gate terminal.

The source terminal and the drain terminal overlap in a space above the gate terminal.

The oxide semiconductor layer comprises a material of indium gallium zinc oxide.

The electrode layer comprises a material of indium tin oxide.

The present invention also provides an ESL TFT substrate structure, which comprises:

a base plate;

a gate terminal formed on the base plate;

a gate insulation layer formed on the gate terminal and the base plate;

an oxide semiconductor layer located above the gate terminal and formed on the gate insulation layer;

an etch stop layer formed on the oxide semiconductor layer, wherein the etch stop layer comprises a first via and a second via formed therein to respectively correspond to two side portions of the oxide semiconductor layer;

a drain terminal formed on the etch stop layer and in engagement with the oxide semiconductor layer through the first via;

a passivation protection layer formed on the drain terminal and the etch stop layer, wherein the passivation protection layer comprises a through ole formed therein to extend to and communicate with the second via; and

an electrode layer formed on the passivation protection layer wherein the electrode layer has one side portion that is adjacent to the drain terminal and is in engagement with the oxide semiconductor layer through the through hole and the second via to form a source terminal; and the electrode layer has an opposite side portion that is extended in a direction away from the drain terminal to form a pixel electrode;

wherein the source terminal and the drain terminal do not overlap in a space above the gate terminal;

wherein the oxide semiconductor layer comprises a material of indium gallium zinc oxide; and

wherein the electrode layer comprises a material of indium tin oxide.

The present invention further provides a manufacturing method of a ESL TFT substrate, which comprises the following steps:

(1) providing a base plate, depositing a first metal layer on the base plate, and subjecting the first metal layer to patternization to form a gate terminal;

(2) depositing a gate insulation layer on the gate terminal and the base plate and depositing and patternizing an oxide semiconductor layer on the gate insulation layer;

(3) depositing an etch stop layer on the oxide semiconductor layer, subjecting the etch stop layer to patternization by using a gray tone mask in order to fully etch off a portion of the etch stop layer that is located above one side portion of the oxide semiconductor layer to expose a side zone of the oxide semiconductor layer for forming an extending-through first via and to partially etch off a portion of the etch stop layer that is located above an opposite side portion of the oxide semiconductor layer without exposing an opposite side zone of the oxide semiconductor layer to form a blind-hole like second via,

wherein the first and second vias are spaced by a spacing distance that defines a channel length;

(4) depositing a second metal layer on the etch stop layer and subjecting the second metal layer to patternization to form a drain terminal, wherein the drain terminal is in engagement with the oxide semiconductor layer through the first via;

(5) depositing a passivation protection layer on the drain terminal and the etch stop layer and subjecting the passivation protection layer to patternization to form a through hole that extends to and communicate with the blind-hole like second via and also to complete hole through the blind-hole like second via to form an extending-through second via so as to keep the channel length unchanged; and

(6) depositing and patternizing the electrode layer on the passivation protection layer in such a way that one side of the electrode layer is adjacent to the drain terminal and is set in engagement with the oxide semiconductor layer through the through hole and the second via to form a source terminal and an opposite side of the electrode layer is extended in a direction away from the drain terminal to form a pixel electrode.

Step (3) comprises the following steps:

(31) coating a photoresist layer on the etch stop layer, subjecting the photoresist layer to exposure and development by using the gray tone mask so as to obtain a full exposure area located above and corresponding to one side portion of the oxide semiconductor layer and a partial exposure area located above and corresponding to an opposite side portion of the oxide semiconductor layer;

(32) subjecting the etch stop layer to etching with the photoresist layer as a shielding layer in order to completely etch off a portion of the etch stop layer that is located below the full exposure area so as to form the extending-through first via and to partially etch off a portion of the etch stop layer that is located below the partial exposure area to form the blind-hole like second via; and

In step (32), the etching is achieved with a dry etching operation.

The source terminal and the drain terminal do not overlap in a space above the gate terminal.

The source terminal and the drain terminal overlap in a space above the gate terminal.

The efficacy of the present invention is that the present invention provides an ESL TFT substrate structure, which comprises an electrode layer to serve as both a source terminal and a pixel electrode and which comprises a drain terminal that is located at a different layer from the source terminal so that the channel length of the TFT is reduced, whereby on the one hand, the TFT is provided with excellent electrical conduction performance and, on the other hand, the size of the TFT is reduced so as to increase an aperture ratio of pixels and reduce the difficult of pixel design. The present invention provides a manufacturing method of an ESL TFT substrate, in which a gray tone mask is first used to subject the etch stop layer to patternization in order to form an extending-through first via and a blind-hole like second via, wherein a spacing distance between the first and second vias defines a channel length, and then, a drain terminal is formed, followed by depositing and patternizing a passivation protection layer and completely holing through the blind-hole like the second via with the channel length being kept unchanged, and finally an electrode layer that serves as both a source terminal and a pixel electrode is formed, thereby the channel length is reduced; the electrical conduction performance of the TFT is improved; and the size of TFT is reduced so as to increase aperture ratio and reduce difficult of pixel design.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Firstly, the present invention provides an etch stop layer (ESL) thin-film transistor (TFT) substrate structure.FIG. 2is a schematic view illustrating an ESL TFT substrate structure according to a first embodiment of the present invention. The ESL TFT substrate structure comprises:

a base plate1;

a gate terminal2formed on the base plate1;

a gate insulation layer3formed on the gate terminal2and the base plate1;

an oxide semiconductor layer4located above the gate terminal2and formed on the gate insulation layer2;

an etch stop layer5formed on the oxide semiconductor layer4, wherein the etch stop layer5comprises a first via51and a second via52formed therein to respectively correspond to two side portions of the oxide semiconductor layer4; and the first and second vias51,52are spaced by a spacing distance L4therebetween to define a channel length;

a drain terminal6formed on the etch stop layer (ESL) and in engagement with the oxide semiconductor layer4through the first via51;

a passivation protection layer7formed on the drain terminal6and the etch stop layer5, wherein the passivation protection layer7comprises a through hole72formed therein to extend to and communicate with the second via52; and

an electrode layer8formed on the passivation protection layer7, wherein the electrode layer8has one side portion that is adjacent to the drain terminal6and is in engagement with the oxide semiconductor layer4through the through hole72and the second via52to form a source terminal81; and the electrode layer8has an opposite side portion that is extended in a direction away from the drain terminal6to form a pixel electrode82.

Specifically, the oxide semiconductor layer4comprises a material of indium gallium zinc oxide (IGZO). The electrode layer8comprises a material of indium tin oxide (ITO).

It is worth mentioning here that in the first embodiment illustrated inFIG. 2, the source terminal81and the drain terminal6do not overlap each other in a space above the gate terminal2.

FIG. 3is a schematic view illustrating an ESL TFT substrate structure according to a second embodiment of the present invention. The second embodiment is different from the first embodiment kin that the source terminal81and the drain terminal6overlap each other in a space above the gate terminal2and thus, the requirement for accuracy of a manufacturing process of the electrode layer8is relatively low. The remaining is the same as the first embodiment and repeated description will be not necessary.

The present invention provides an ESL TFT substrate structure, which comprises an electrode layer8to serve as both a source terminal81and a pixel electrode82and which comprises a drain terminal6that is located at a different layer from the source terminal81so that the channel length of the TFT is defined as the spacing distance L4between the first and second vias51,52and is smaller than the channel length of a conventional ESL TFT substrate, whereby on the one hand, the TFT is provided with excellent electrical conduction performance and, on the other hand, the size of the TFT is reduced so as to increase an aperture ratio of pixels and reduce the difficult of pixel design.

Referring toFIG. 4, the present invention also provides a manufacturing method of an ESL TFT substrate, which comprises the following steps:

Step1: as shown inFIG. 5, providing a base plate1, depositing a first metal layer on the base plate1, and subjecting the first metal layer to patternization to form a gate terminal2.

Step2: as shown inFIG. 6, depositing a gate insulation layer3on the gate terminal2and the base plate1and depositing and patternizing an oxide semiconductor layer4on the gate insulation layer3.

Specifically, the oxide semiconductor layer4comprises a material of IGZO.

Step3: as shown inFIGS. 7-9, depositing an etch stop layer5on the oxide semiconductor layer4, subjecting the etch stop layer5to patternization by using a gray tone mask in order to fully etch off a portion of the etch stop layer5that is located above one side portion of the oxide semiconductor layer4to expose a side zone of the oxide semiconductor layer4for forming an extending-through first via51and to partially etch off a portion of the etch stop layer5that is located above an opposite side portion of the oxide semiconductor layer4without exposing an opposite side zone of the oxide semiconductor layer4to form a blind-hole like second via52. The first and second vias51,52are spaced by a spacing distance L4that defines a channel length.

Step31: as shown inFIG. 7, coating a photoresist layer30on the etch stop layer5, subjecting the photoresist layer30to exposure and development by using the gray tone mask so as to obtain a full exposure area301located above and corresponding to one side portion of the oxide semiconductor layer4and a partial exposure area302located above and corresponding to an opposite side portion of the oxide semiconductor layer4.

Step32: as shown inFIG. 8, subjecting the etch stop layer5to etching with the photoresist layer30as a shielding layer in order to completely etch off a portion of the etch stop layer5that is located below the full exposure area301so as to form the extending-through first via51and to partially etch off a portion of the etch stop layer5that is located below the partial exposure area302to form the blind-hole like second via52.

Step4: as shown inFIG. 10, depositing a second metal layer on the etch stop layer5and subjecting the second metal layer to patternization to form a drain terminal6, wherein the drain terminal6is in engagement with the oxide semiconductor layer4through the first via51.

Step5: as shown inFIG. 11, depositing a passivation protection layer7on the drain terminal6and the etch stop layer5and subjecting the passivation protection layer7to patternization to form a through hole72that extends to and communicate with the blind-hole like second via52and also to complete hole through the blind-hole like second via52to form an extending-through second via52so as to keep the channel length unchanged.

Step6: as shown inFIG. 12, depositing and patternizing the electrode layer8on the passivation protection layer7in such a way that one side of the electrode layer8is adjacent to the drain terminal6and is set in engagement with the oxide semiconductor layer4through the through hole72and the second via52to form a source terminal81and an opposite side of the electrode layer8is extended in a direction away from the drain terminal6to form a pixel electrode82.

Specifically, the electrode layer8comprises a material of ITO.

FIG. 12schematically illustrates the source terminal81and the drain terminal6do not overlap each other in a space above the gate terminal2. It is, however, obvious that due to limitations imposed by accuracy of manufacturing operations, the source terminal81and the drain terminal6may overlap each other in a space above the gate terminal2as shown inFIG. 3.

In the above-described manufacturing method of an ESL TFT substrate, a gray tone mask is first used to subject the etch stop layer5to patternization in order to form an extending-through first via51and a blind-hole like second via52, wherein a spacing distance L4between the first and second vias51,52defines a channel length, and then, a drain terminal6is formed, followed by depositing and patternizing a passivation protection layer7and completely holing through the blind-hole like the second via52with the channel length being kept unchanged, and finally an electrode layer that serves as both a source terminal81and a pixel electrode82is formed, thereby the channel length is reduced; the electrical conduction performance of the TFT is improved; and the size of TFT is reduced so as to increase aperture ratio and reduce difficult of pixel design.

In summary, the present invention provides an ESL TFT substrate structure, which comprises an electrode layer to serve as both a source terminal and a pixel electrode and which comprises a drain terminal that is located at a different layer from the source terminal so that the channel length of the TFT is reduced, whereby on the one hand, the TFT is provided with excellent electrical conduction performance and, on the other hand, the size of the TFT is reduced so as to increase an aperture ratio of pixels and reduce the difficult of pixel design. The present invention provides a manufacturing method of an ESL TFT substrate, in which a gray tone mask is first used to subject the etch stop layer to patternization in order to form an extending-through first via and a blind-hole like second via, wherein a spacing distance between the first and second vias defines a channel length, and then, a drain terminal is formed, followed by depositing and patternizing a passivation protection layer and completely holing through the blind-hole like the second via with the channel length being kept unchanged, and finally an electrode layer that serves as both a source terminal and a pixel electrode is formed, thereby the channel length is reduced; the electrical conduction performance of the TFT is improved; and the size of TFT is reduced so as to increase aperture ratio and reduce difficult of pixel design.