Method for performing refresh management in a memory device, associated memory device and controller thereof

A method for performing refresh management in a memory device, the memory device and controller thereof are provided. The method may include: monitoring a temperature of the memory device, wherein the temperature is detected through a temperature sensor; updating a recorded highest temperature and a recorded lowest temperature according to said temperature; checking whether a difference between the recorded highest temperature and the recorded lowest temperature is greater than a predetermined temperature threshold; and when the difference is greater than the predetermined temperature threshold, triggering refresh of the memory device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to access of flash memories, and more particularly, to a method for performing refresh management in a memory device, an associated memory device and a controller thereof.

2. Description of the Prior Art

Developments in memory technology have enabled the wide application of portable memory devices (or non-portable memory devices), such as memory cards conforming to SD/MMC, CF, MS and XD specifications, solid state drive (SSD), and embedded storage devices conforming to the UFS or EMMC specification. Improving access control of memories in these portable memory devices still remains an issue to be solved in the art.

NAND flash memories may comprise single level cell (SLC) and a plurality of level cell (MLC) flash memories. In an SLC flash memory, each transistor used as a memory cell may have either of two electrical charge values: the logic values 0 and 1. In comparison, the storage ability of each transistor used as a memory cell in an MLC flash memory may be fully utilized. The transistors are driven by a voltage higher than that in the SLC flash memory, and different voltage levels are utilized to record information of at least two bits (such as 00, 01, 11, or 10). In theory, the recording density of the MLC flash memory may reach at least twice the recording density of the SLC flash memory, and is therefore preferred by manufacturers of NAND flash memories.

The lower cost and larger capacity of the MLC flash memory means it is more likely to be applied in portable memory devices than an SLC flash memory. The MLC flash memory does have instability issues, however. To ensure that access control of the flash memory in the portable memory device meets required specifications, a controller of the flash memory is configured to apply management mechanisms for properly managing data access.

Memory devices inevitably have certain deficiencies, even for those with the above management mechanism. For example, under a situation where the temperature varies rapidly, the data error rate can increase significantly. Hence, there is a need for a novel method and memory access mechanism of memory devices which can provide an optimal performance without introducing side effects or in a way that is less likely to introduce side effects.

SUMMARY OF THE INVENTION

One of the objectives of the present invention is to provide a method, an associated memory device and controller thereof, and an associated electronic device for performing refresh management, in order to solve the above issue.

Another objective of the present invention is to provide a method, an associated memory device and controller thereof, and an associated electronic device for performing refresh management, in order to reach an optimal performance of the memory device without introducing side effects or in a way that is less likely to introduce side effects.

At least one embodiment of the present invention provides a method for performing refresh management in a memory device. The memory device comprises a non-volatile (NV) memory that comprises a plurality of NV memory elements. The method comprises: monitoring a temperature of the memory device, wherein the temperature is detected via a temperature sensor; updating a recorded highest temperature and a recorded lowest temperature according to the monitored temperature; checking whether a difference value between the recorded highest temperature and the recorded lowest temperature is greater than a predetermined temperature threshold; and when the difference value is greater than the predetermined temperature threshold, triggering a refresh of the memory device.

At least one embodiment of the present invention provides a memory device, which comprises an NV memory and a controller. The NV memory is arranged to store information, wherein the NV memory comprises a plurality of NV memory elements. The controller is coupled to the NV memory, and the controller is arranged to control operations of the memory device, wherein the controller comprises a processing circuit. The processing circuit is arranged to control the controller according to a plurality of host commands from a host device, in order to allow the host device to access the NV memory via the controller, wherein: the controller monitors a temperature of the memory device, wherein the temperature is detected by a temperature sensor; the controller updates a recorded highest temperature and a recorded lowest temperature according to the monitored temperature; the controller checks whether a difference value between the recorded highest temperature and the recorded lowest temperature is greater than a predetermined temperature threshold; and when the difference value is greater than the predetermined temperature threshold, the controller triggers a refresh of the memory device.

At least one embodiment of the present invention provides a controller of a memory device, the memory device comprising the controller and an NV memory. The NV memory comprises a plurality of NV memory elements. The controller comprises a processing circuit that is arranged to control the controller according to a plurality of host commands from a host device, in order to allow the host device to access the NV memory via the controller, wherein: the controller monitors a temperature of the memory device, wherein the temperature is detected via a temperature sensor; the controller updates a recorded highest temperature and a recorded lowest temperature according to the monitored temperature; the controller checks whether a difference value between the recorded highest temperature and the recorded lowest temperature is greater than a predetermined temperature threshold; and when the difference value is greater than the predetermined temperature threshold, the controller triggers a refresh of the memory device.

An advantage provided by the present invention is that operations of the memory device can be properly controlled via performing refresh management, in order to prevent data errors due to rapid variation of temperature. In addition, implementations according to the embodiments of the present invention will not greatly increase additional costs, and therefore problems which exist in related art techniques can be solved without greatly raising the overall cost. Further, the present invention may achieve optimal performance without introducing side effects or in a way that is less likely to introduce side effects.

DETAILED DESCRIPTION

I. Memory System

Refer toFIG. 1, which is a diagram illustrating a memory device100and a host device50according to an embodiment of the present invention. The host device50may comprise: at least one processer (not shown) arranged to control operations of the host device50; and a power supply circuit (not shown) coupled to the processer, and arranged to provide power to the processer and the memory device100, wherein the memory device100may provide storage space for the host device50. Examples of the host device50may comprise (but are not limited to): a multifunctional mobile phone, tablet, wearable device, and personal computer (e.g. a desktop computer or a laptop computer). Examples of the memory device100may comprise (but are not limited to): a portable memory device (e.g. a memory card conforming to the SD/MMC, CF, MS, XD or UFS specification), a solid state drive (SSD) and all kinds of embedded storage devices (e.g. those conforming to the UFS or EMMC specification). According to this embodiment, the memory device100may comprise a controller such as a memory controller110, and may further comprise a non-volatile (NV) memory120, wherein the controller is arranged to access the NV memory120, and the NV memory120is arranged to store information. The NV memory120may comprise a plurality of NV memory elements122-1,122-2, . . . , and122-N, wherein the symbol “N” may represent an integer larger than 1. For example, the NV memory120may be a flash memory, and the NV memory elements122-1,122-2, . . . , and122-N may be a plurality of flash memory chips (i.e. flash chips) or a plurality of flash memory dies (i.e. flash dies), but the present invention is not limited thereto.

As shown inFIG. 1, the memory controller110may comprise a processing circuit such as a microprocessor112, a storage such as a read only memory (ROM)112M, a control logic circuit114, a buffer memory116, a temperature sensor117and a transmission interface circuit118, wherein these components may be coupled to one another via a bus. The buffer memory116is implemented with a random access memory (RAM), e.g. a Static RAM (SRAM), and can be utilized for buffering data, and the temperature sensor117may be arranged to detect temperatures. Further, the ROM112M in this embodiment is arranged to store a program code112C, and the microprocessor112is arranged to execute the program code112C in order to control the access to the NV memory120. Note that the program code112C may also be stored into the buffer memory116or any other type of memory. In addition, the control logic circuit114may comprise an error correction circuit (not shown), in order to protect data and/or perform error corrections. The transmission interface circuit118may conform to a specific communications specification, such as the Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Universal Serial Bus (USB), or Peripheral Component Interconnect Express (PCIE) specifications, and may perform communications according to the specific communications specification.

In this embodiment, the host device50may indirectly access the NV memory120of the memory device100by transmitting a plurality of host commands and corresponding logic addresses to the memory controller110. The memory controller110receives the host commands and the logic addresses, translates the host commands into memory operating commands (which can be called operating commands, for brevity), and utilizes the operating commands to control the NV memory120to read or write/program memory units or data pages of specific physical addresses in the NV memory120, wherein a physical address corresponds to a logic address. For example, the memory controller110may generate or update at least one logic-to-physical address mapping table to manage relationships between logic addresses and physical addresses. Further, the control logic circuit114may comprise a randomizer/de-randomizer (not shown), which is arranged to perform randomizing/de-randomizing operations. When the memory controller110writes data into the NV memory120, the memory controller110may perform a randomizing operation upon the data to make the NV memory120store randomized data. When the memory controller110reads data from the NV memory120, the memory controller110may perform a de-randomizing operation upon the read randomized data in order to obtain the previously written data.

II. Distribution Shift Corresponding to Temperature Variations

FIG. 2illustrates a distribution shifting effect of the memory device100shown inFIG. 1according to an embodiment of the present invention. The horizontal axis inFIG. 2may represent the digital control value Vth_DAC of the threshold voltage Vth, and the vertical axis may represent the cell count CCb0of the memory cells carrying “0” bits in the NV memory120(e.g. the NV memory elements122-1,122-2, . . . and122-N) that are read via the threshold voltage Vth, wherein the digital control value Vth_DAC may also be called the “threshold voltage digital control value”, and the cell count CCb0may also be called the “zero-bit cell count”. Since the memory controller110may be equipped with a randomizing/de-randomizing mechanism (which can be actualized by utilizing the randomizer/de-randomizer to perform randomizing/de-randomizing operations), the data stored in the NV memory120may have been randomized.

Table 1 demonstrates an example of the relationship between the threshold voltage Vth and the digital control value Vth_DAC, wherein the symbols in Table 1 “ . . . ” represent the omissions of some table contents therein, but the present invention is not limited thereto. The digital control value Vth_DAC in this example may be an integer greater than or equal to zero, and each variation step may be 20 millivolts (mV). For example, when Vth_DAC=0, Vth=0 mV; when Vth_DAC=1, Vth=20 mV; etc. In another example, when the digital control value Vth_DAC increases to 255, Vth=5100 mV (which equals to 5.1 volts (V)).

The threshold voltage Vth is affected by temperature in a significant manner. Compared with the distribution of accessing the NV memory120under room temperature (e.g. both writing and reading are performed at 25° C., which is labeled “W 25° C./R 25° C.”), the distribution of accessing the NV memory120under an abnormal temperature (e.g. writing is performed at −40° C. and reading is performed at 85° C., which is labeled “W −40° C./R 85° C.”) is right shifted, which shows that accessing the NV memory120with the same threshold voltage Vth but with an abnormal temperature can easily result in data errors.

FIG. 3illustrates a distribution shifting effect of the memory device100shown inFIG. 1according to another embodiment of the present invention. Compared with the distribution of accessing the NV memory120under room temperature (e.g. both writing and reading are performed at 25° C., which is labeled “W 25° C./R 25° C.”), the distribution of accessing the NV memory120under an abnormal temperature (e.g. writing at 85° C. and reading at −40° C., labeled “W 85° C./R −40° C.”) is left shifted, which further shows that accessing the NV memory120with the same threshold voltage Vth but with an abnormal temperature can easily result in data errors.

III. Data Refresh Management

Regarding the distribution shift, the memory controller110may perform a refresh of the memory device100, and more particularly, may perform a refresh of the whole storage space (e.g. the storage space of the NV memory elements122-1,122-2, . . . and122-N) of the memory device100in order to read data from the NV memory120(e.g. the data in the NV memory elements122-1,122-2, . . . and122-N), and rewrite the data to the NV memory120, wherein the logic addresses of a same set of data usually remain unchanged, while the physical addresses of the set of data are allowed to be changed. Examples of the refresh operation may comprise (but are not limited to): re-charging, re-programming, data-swapping, data-moving, etc.

FIG. 4is a working flow300of a method for performing refresh management in a memory device according to an embodiment of the present invention, wherein the method may be applied to the memory device100, and may be applied to the controller such as the memory controller110.

In Step S10, the memory controller110may perform initialization upon the memory device100. For example, the memory controller110may set both a recorded highest temperature Tmax and a recorded lowest temperature Tmin of the temperature T as a predetermined value T0(i.e. Tmax=T0, and Tmin=T0, wherein the predetermined value T0is used as their respective initial values), wherein the memory controller110may utilize the hardware resource therein (e.g. the buffer memory116or any type of memory) to store the predetermined value T0, the recorded highest temperature Tmax and the recorded lowest temperature Tmin. The symbols “Tmax” and “Tmin” indicate that the recorded highest temperature Tmax and the recorded lowest temperature Tmin may be regarded as a recorded maximum value and a recorded minimum value of the temperature T being monitored (e.g. the recorded maximum temperature and the recorded minimum temperature), respectively.

In Step S21, the memory controller110may control the memory device100to operate under a normal mode. For example, the microprocessor112may control the memory controller110according to the host commands from the host device50, in order to allow the host device50to access the NV memory120via the memory controller110.

In Step S22, the memory controller110may utilize a built-in sensor such as the temperature sensor117to monitor the temperature T of the memory device100. For example, the memory controller110may use the latest temperature detected by the built-in sensor to update the temperature T, wherein the memory controller110may utilize the hardware resource therein (e.g. the buffer memory116or any other type of memory) to store the temperature T.

In Step S31, the memory controller110may check whether the temperature T is greater than the recorded highest temperature Tmax (labeled “T>Tmax?”). When the temperature T is greater than the recorded highest temperature Tmax, Step S41is entered; otherwise, Step S32is entered.

In Step S32, the memory controller110may check whether the temperature T is smaller than the recorded lowest temperature Tmin (labeled “T<Tmin?”). When the temperature T is smaller than the recorded lowest temperature Tmin, Step S42is entered; otherwise, Step S21is entered.

In Step S41, the memory controller110may update the recorded highest temperature Tmax, and more particularly, may update the recorded highest temperature Tmax to the latest value of the temperature T, such as the latest temperature detected by the built-in sensor.

In Step S42, the memory controller110may update the recorded lowest temperature Tmin, and more particularly, may update the recorded lowest temperature Tmin to the latest value of the temperature T, such as the latest temperature detected by the built-in sensor.

In Step S50, the memory controller110may check whether the difference value (Tmax−Tmin) between the recorded highest temperature Tmax and the recorded lowest temperature Tmin is greater than a predetermined temperature threshold Th1(labeled “(Tmax−Tmin)>Th1?”). When the difference value (Tmax−Tmin) is greater than the predetermined temperature threshold Th1, Step S61is entered; otherwise, Step S21is entered.

In Step S61, the memory controller110may reset the recorded highest temperature Tmax and the recorded lowest temperature Tmin. For example, the memory controller110may reset both the recorded highest temperature Tmax and the recorded lowest temperature Tmin as the predetermined value T0(i.e. Tmax=T0, and Tmin=T0).

In Step S62, the memory controller110may trigger the refresh of the whole storage space (e.g. the storage space of NV memory elements122-1,122-2, . . . and122-N) of the memory device100, wherein this trigger operation may represent entering a refresh process (e.g., by initializing the refresh process). For example, the refresh process may comprise the operations of Step S70and Step S80, but the present invention is not limited thereto.

In Step S70, the memory controller110may check whether the temperature T is within a target range, wherein the target range may be a predetermined temperature range, and more particularly, may be a range corresponding to room temperature. For example, the target range may be within 20° C. to 30° C. (e.g. the interval [20, 30] (° C.)). In another example, the predetermined value T0may be within the target range, and more particularly, may be a central value of the target range or a mean value of the two boundary values (e.g. 20° C. and 30° C.) of the target range, such as 25° C. When the temperature T is within the target range, Step S80is entered; otherwise, Step S70is entered once more. According to this embodiment, the memory controller110may wait for the temperature T to be within the target range via performing Step S70once more, wherein the refresh of the memory device100is not started until the temperature T is within the target range, so, in the refresh process, the refresh of the memory device100is performed when the temperature T is within the target range.

In Step S80, the memory controller110may refresh the whole storage space (e.g. the storage space of NV memory elements122-1,122-2, . . . and122-N) of the memory device100.

According to some embodiments, adjustments such as modifying, adding and/or deleting one or more steps are allowed in the flowchart300. For example, the timing of the operation of Step S61may be adjusted to be performed during the refresh process (e.g. the operation of Step S61can be postponed until after the operation of Step S62or until after the operation of Step S70in other embodiments), but the present invention is not limited thereto. In another example, the timing of the operation of Step S61may be adjusted to be performed following the refresh process (e.g. the operation of Step S61can be postponed until after the operation of Step S80).

According to some embodiments, the target range and/or predetermined value T0may be modified. For example, regarding some nations and/or geographical areas with higher temperatures, the target range may be adjusted to be a higher temperature range, such as 35° C. to 45° C. (e.g. the interval [35, 45] (° C.)), and the predetermined value T0may be adjusted to a higher value, such as (° C.). In another example, regarding some nations and/or geographical areas with lower temperatures, the target range may be adjusted to a lower temperature range, such as 5° C. to 15° C. (e.g. the interval [5, 15] (° C.)), and the predetermined value T0may be adjusted to a lower temperature value, such as 10 (° C.). For brevity, similar descriptions for these embodiments are not repeated in detail here.

According to some embodiments, the memory controller110may determine the current value of the temperature T as the predetermined value T0via the built-in sensor, such as the temperature sensor117. In this situation, the operation of Step S61may be performed following the operation of Step S80. For example, the execution of the operation of Step S61may be postponed until after the operation of Step S80. For brevity, similar descriptions for these embodiments are not repeated in detail here.

According to some embodiments, the built-in sensor may be replaced by an external sensor (not shown), such as a temperature sensor. The external sensor may be located external to the memory device100, and more particularly, may be located in the host device50. In another example, the external sensor may be located in the memory device100but external to the memory controller110. For brevity, similar descriptions for these embodiments are not repeated in detail here.