Electronic device having a plurality of CPUs and a method

An electronic device includes a first CPU, a second CPU, an auxiliary storage unit, and a controller. The auxiliary storage unit includes a first starting program for the first CPU and a second starting program for the second CPU. The first CPU loads the first starting program via the controller, and causes the controller to load the second starting program in DMA transfer. The controller, if the controller is caused by the first CPU to transfer part of the first starting program while the controller is loading the second starting program, stops loading the second starting program. When completing the transfer of the part of the first starting program, the controller restarts loading the second starting program.

INCORPORATION BY REFERENCE

This application is based on, and claims priority to corresponding Japanese Patent Application No. 2013-244535, filed in the Japan Patent Office on Nov. 27, 2013, the entire contents of which are incorporated herein by reference.

FIELD

Unless otherwise indicated herein, the description in this field section or the background section is not prior art to the claims in this application and is not admitted to be prior art by inclusion in this section. The present disclosure relates to an electronic device having a plurality of Central Processing Units (CPUs) and a method.

BACKGROUND

A typical electronic device having a plurality of CPUs includes a first CPU, a second CPU, and an auxiliary storage unit that stores a first starting program for the first CPU and a second starting program for the second CPU. The first CPU and second CPU load the first starting program from the auxiliary storage unit in a section unit. Since the electronic device can reduce the time necessary to load the first starting program, the time taken by the first CPU to start according to the first starting program can be reduced. The electronic device prioritizes starting by the first CPU according to the first starting program, so starting by the second CPU according to the second starting program is delayed.

Furthermore, the auxiliary storage device, in the typical electronic device, in which the first starting program and second starting program are stored, may not allow a plurality of accesses at the same time. In this case, while one of the first CPU and second CPU is accessing the auxiliary storage device, the other CPU cannot access the auxiliary storage device, weakening the effect of reducing the time taken by the first CPU. In addition, when the effect of reducing the time taken by the first CPU is weakened, starting by the second CPU according to the second starting program is further delayed.

SUMMARY

The present disclosure related to an electronic device and a method that, even in a case in which the starting program is stored for each of a plurality of CPUs in an auxiliary storage device that does not allow a plurality of accesses at the same time, preferentially reduces the time taken by a particular CPU to start according to its corresponding starting program and also reduces the time taken by another CPU to start according to its corresponding starting program.

An electronic device according to an embodiment of the present disclosure includes a first CPU, a second CPU, an auxiliary storage unit that does not allow a plurality of accesses at the same time, and a controller that controls access to the auxiliary storage unit. The auxiliary storage unit includes a first starting program for the first CPU and a second starting program for the second CPU.

The first CPU loads the first starting program from the auxiliary storage unit via the controller, and causes the controller to load the second starting program from the auxiliary storage unit in direct memory access (DMA) transfer.

The controller, if the controller is caused by the first CPU to transfer part of the first starting program from the auxiliary storage unit while the controller is loading the second starting program from the auxiliary storage unit in the DMA transfer, stops loading of the second starting program, and when completing the transfer of the part of the first starting program, restarts loading of the second starting program.

DETAILED DESCRIPTION

Various embodiments are described below with reference to the figures. It should be understood, however, that numerous variations from the depicted arrangements and functions are possible while remaining in the scope and spirit of the claims. For instance, one or more elements may be added, removed, combined, distributed, substituted, re-positioned, re-ordered, and/or otherwise changed. Further, where this description refers to one or more functions being implemented on and/or by one or more devices, one or more machines, and/or one or more networks, it should be understood that one or more of such entities could carry out one or more of such functions by themselves or in cooperation, and may do so by application of any suitable combination of hardware, firmware, and/or software. For instance, one or more processors may execute one or more sets of programming instructions as at least part of carrying out one or more of the functions described herein.

First, the structure of a multi-function peripheral (MFP) that functions as the electronic device according to an embodiment of the present disclosure will be described.

FIG. 1is a schematic diagram illustrating the block configuration of the MFP10according to an embodiment.

As illustrated inFIG. 1, the MFP10includes: a manipulation unit11, which is an input device, including buttons and the like with which the user enters various types of manipulation inputs; a display unit12, such as, for example, a liquid crystal display (LCD) unit, on which various types of information items are displayed; a scanner13, which is a read device that reads an image from a draft; a printer14, which executes printing on a sheet or another recording medium; a facsimile communication unit15, which performs facsimile communication with an external facsimile device (not illustrated) via a communication line such as a public telephone line; a network communication unit16, which communicates with an external device (not illustrated) via a local area network (LAN), the Internet, or another network; and a control unit20that controls the whole of the MFP10.

FIG. 2is a schematic diagram illustrating the block configuration of the control unit20.

As illustrated inFIG. 2, the control unit20includes: a main central processing unit (CPU)21, which functions as a first CPU; a read-only memory (ROM)22, in which a program for the main CPU21and various types of data are stored; a random-access memory (RAM)23for the main CPU21; a sub-CPU24, which functions as a second CPU; a ROM25, in which a program for the sub-CPU24and various types of data, a RAM26for the sub-CPU24; an NAND device27, which functions as an auxiliary storage unit that does not allow a plurality of accesses at the same time; and an NAND device controller28, which functions as a controller that controls accesses to the NAND device27.

The NAND device27stores a main CPU starting program27aused as a first starting program for the main CPU21, and also stores a sub-CPU starting program27bused as a second starting program for the sub-CPU24.

The NAND device controller28handles direct memory access (DMA) transfer and programmed input/output (PIO) transfer.

Next, the operation of the MFP10at the time of starting of the MFP10will be described.

When caused to start the MFP10, the main CPU21executes the operation illustrated inFIG. 3.

FIG. 3is a flowchart of the operation executed by the main CPU21at the time of starting of the MFP10.

As illustrated inFIG. 3, the main CPU21causes the NAND device controller28to load the sub-CPU starting program27bin DMA transfer from the NAND device27to the RAM26(S101).

Next, the main CPU21loads the main CPU starting program27ain PIO transfer from the NAND device27to the RAM23via the NAND device controller28, and executes loaded portions of the main CPU starting program27ain succession while executing the loading (S102). That is, the main CPU21causes the NAND device controller28to transfer only part of the main CPU starting program27aat a time and executes in succession transferred portions.

When the process in S102is completed, the main CPU21terminates the operation inFIG. 3.

Although, inFIG. 3, the main CPU21executes the process in S102after executing the process in S101, the main CPU21may execute the process in S101in the middle of executing the process in S102.

When caused to start the MFP10, the NAND device controller28executes the operation illustrated inFIG. 4.

FIG. 4is a flowchart of the operation executed by the NAND device controller28at the time of starting of the MFP10.

As illustrated inFIG. 4, the NAND device controller28determines whether the main CPU21has commanded transfer of part of the main CPU starting program27a(S131).

If the NAND device controller28determines in S131that transfer of part of the main CPU starting program27ahas been commanded, the NAND device controller28reads out a portion commanded by the main CPU21, the portion being part of the main CPU starting program27a, from the NAND device27and transfers the read-out portion to the main CPU21(S132).

If the NAND device controller28determines in S131that transfer of part of the main CPU starting program27ahas not been commanded or the process in S132has been completed, the NAND device controller28determines whether the main CPU21has commanded loading of the sub-CPU starting program27bin DMA transfer (S133).

If the NAND device controller28determines in S133that loading of the sub-CPU starting program27bin DMA transfer has not been commanded, the NAND device controller28executes the process in S131.

If the NAND device controller28determines in S133that loading of the sub-CPU starting program27bin DMA transfer has been commanded, the NAND device controller28starts to load the sub-CPU starting program27bin DMA transfer (S134). Specifically, the NAND device controller28starts to read out the sub-CPU starting program27bfrom the NAND device27and loads the read-out sub-CPU starting program27bin the RAM26.

Next, the NAND device controller28determines whether the main CPU21has commanded transfer of part of the main CPU starting program27a(S135).

If the NAND device controller28determines in S135that transfer of part of the main CPU starting program27ahas been commanded, the NAND device controller28halts the loading of the sub-CPU starting program27bin DMA transfer (S136) and reads out a portion commanded by the main CPU21, the portion being part of the main CPU starting program27a, from the NAND device27and transfers the read-out portion to the main CPU21(S137).

When completing the transfer in S137, the NAND device controller28restarts loading of the sub-CPU starting program27bin DMA transfer (S138).

If the NAND device controller28determines in S135that transfer of part of the main CPU starting program27ahas not been commanded or the process in S138has been completed, the NAND device controller28determines whether loading of the sub-CPU starting program27bin DMA transfer has been completed (S139).

If the NAND device controller28determines in S139that loading of the sub-CPU starting program27bin DMA transfer has not been completed, the NAND device controller28executes the process in S135.

If the NAND device controller28determines in S139that loading of the sub-CPU starting program27bin DMA transfer has been completed, the NAND device controller28notifies the main CPU21that loading of the sub-CPU starting program27bin DMA transfer has been completed (S140) and then executes the process in S131.

When the main CPU21is notified by the NAND device controller28that loading of the sub-CPU starting program27bin DMA transfer has been completed, the main CPU21causes the sub-CPU24to execute the sub-CPU starting program27b. Thus, the sub-CPU24executes the sub-CPU starting program27bloaded in the RAM26.

As described above, the MFP10prioritizes that the main CPU21loads the main CPU starting program27afrom the NAND device27via the NAND device controller28(S102). Furthermore, while the main CPU21is not loading the main CPU starting program27afrom the NAND device27via the NAND device controller28, the NAND device controller28loads the sub-CPU starting program27bfrom the NAND device27in DMA transfer (S134and S138).

That is, the MFP10efficiently transfers the sub-CPU starting program27bby using the time during which the NAND device27is not accessed. Therefore, despite the main CPU starting program27aand sub-CPU starting program27bbeing stored in the NAND device27that does not allow a plurality of accesses at the same time, the MFP10can preferentially reduce the time taken by the main CPU21to start according to the main CPU starting program27aand can also reduce the time taken by the sub-CPU24to start according to the sub-CPU starting program27b.

Since the main CPU21loads the main CPU starting program27ain PIO transfer from the NAND device27and executes loaded portions of the main CPU starting program27ain succession while executing the loading, the MFP10can also reduce the time taken by the main CPU21to start according to the main CPU starting program27a.

Although, in this embodiment, the MFP10is structured so that the main CPU21loads the main CPU starting program27ain PIO transfer from the NAND device27, this is not a limitation; if transfer of the main CPU starting program27ais processed by the NAND device controller28so that the transfer has a higher priority than transfer of the sub-CPU starting program27b, the NAND device controller28may be caused to load the main CPU starting program27afrom the NAND device27in the RAM23in DMA transfer.

Although, in this embodiment, the MFP10has the RAM23for the main CPU21and the RAM26for the sub-CPU24, this is not a limitation; the RAM23and RAM26may be physically allocated in different areas in a single RAM.

Although, in this embodiment, the auxiliary storage unit is an NAND device, this is not a limitation; if the auxiliary storage unit does not allow a plurality of accesses at the same time, the auxiliary storage unit may be a non-NAND device.

Although, in this embodiment, the electronic device is an MFP, this is not a limitation; the electronic device may be a copier, a printer, or another image forming apparatus other than MFPs. Alternatively, the electronic device may be a general-purpose personal computer, a home electrical appliance, or another electric device other than image forming apparatuses.