Bonding pad structure

A substrate has a bonding region and a sensing region. A first dielectric layer is formed overlying the substrate and has a dielectric island surrounded by a ring-shaped trench. A first conductive layer is formed in the ring-shaped trench of the first dielectric layer. A passivation layer is formed overlying the first dielectric layer and has an opening, in which the opening corresponds to the bonding region and the sensing region and exposes the dielectric island and a part of the first conductive layer. A second conductive layer covers the opening of the passivation layer and is electrically connected to the first conductive layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to integrated circuits, and more particularly to a bonding pad structure.

2. Description of the Related Art

Bonding pads are interfaces between integrated circuits contained in semiconductor chips and a device package. Modern IC designs with high circuit density require a significantly increased number of pins and bonding pads to reduce bonding pad pitch and size. Large mechanical stresses inherent in bonding operations, however, easily damage smaller bonding pads.

Traditionally, each bonding pad is connected to one or more contact pads on an IC-mounting surface of the device package through wire-bonding, tape automated bonding (TAB) or flip-chip technologies. When an IC chip is probed in an electrical test or the like, a probe pin may damage the soft surface of the bonding pad. The Cu layer beneath the AlCu pad is exposed to air, and may be corroded. The corroded pads caused by this type of pad voids degrade the bondability of wire connection. Currently, a top copper layer of a solid profile is used for connecting an aluminum pad, but has disadvantages of pad voids, narrow bondability window, ball lifting and dielectric crack issues. Accordingly, several modifications of the top copper layer have been developed as listed below. Moreover, in order to overcome this problem, the bonding pad has been divided into a bonding pad region and a sensing pad region, and the probe pin is brought into contact only with the sensing pad region which is allowed to be damaged.

As disclosed in U.S. Pat. No. 6,552,438, one conventional bonding pad comprises a plurality of independent metal plugs formed in an array of via holes of an inter-dielectric layer, in which each metal plug has a bottom portion connected to a lower aluminum layer and a top portion connected to an upper aluminum pad. Moreover, a passivation layer is formed on the aluminum pad to expose a predetermined bonding area for bonding a wire. Another conventional bonding pad comprises a top metal layer filling a lattice trench of an inter-dielectric layer for surrounding dielectric islands. A passivation layer is also formed on the top metal layer to expose a predetermined bonding area for forming an aluminum pad, thus allowing a ball to be bonded on the aluminum pad.

The above-described bonding pads, however, have the following disadvantages. During wafer sorting, wire bonding or probe pin testing, applied forces or large mechanical stresses may crack the inter-dielectric layer adjacent to a probe pin region. Second, the crack may extend into the interior of the inter-dielectric layer surrounding the top metal layer, causing corrosion and layer-open problems. This also causes the aluminum pad to peel from the top metal layer, thus the pad-open problem causes the wire to lose contact with the aluminum pad, decreasing bonding reliability. Additionally, the pitch and size of the bonding pad cannot be further shrinked as the bonding pad is susceptible to damage from the mechanical stress, thus limiting chip size reduction in next generation technologies. Fourth, during wire bonding, a high distribution ratio of the independent metal plugs or the dielectric islands may create a pad finding issue.

As disclosed in U.S. Pat. No. 6,566,752, another conventional bonding pad comprises a top metal ring formed in a trench of an inter-dielectric layer. A passivation layer with a plurality of via holes is formed on the inter-dielectric layer to expose the top metal ring. An aluminum pad is formed on the passivation layer and is electrically connected to the top metal ring through via holes. However, the width of the top metal ring is limited by the via hole design, resulting in a misalignment problem during photolithography, which prohibits bonding pad fabrication within active areas.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a top metal layer design for a bonding pad structure to obtain a metal-free area or a small metal area under a metal pad within a sensing region.

According to the object of the invention, a bonding pad structure comprises a substrate having a bonding region and a sensing region. A first dielectric layer is formed overlying the substrate and has a dielectric island surrounded by a ring-shaped trench. A first conductive layer is formed in the ring-shaped trench of the first dielectric layer. A passivation layer is formed overlying the first dielectric layer and has an opening, in which the opening corresponds to the bonding region and the sensing region and exposes the dielectric island and a part of the first conductive layer. A second conductive layer covers the opening of the passivation layer and is electrically connected to the first conductive layer.

Another object of the present invention is to provide a passivation opening design for a bonding pad structure to protect a top metal layer under a metal pad within a sensing region.

According to the object of the invention, a bonding pad structure comprises a substrate having a bonding region and a sensing region. A first dielectric layer is formed overlying the substrate and has a trench. A first conductive layer is formed in the trench of the first dielectric layer. A passivation layer is formed overlying the first dielectric layer and has an opening corresponding to the bonding region, wherein the passivation layer covers the first conductive layer formed within the sensing region. A second conductive layer covers the opening of the passivation layer and is formed overlying the sensing region. The second conductive layer is electrically connected to the first conductive layer.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a top metal layer design for a bonding pad structure to obtain a metal-free area or a small metal area under a metal pad within a sensing region. The present invention additionally provides a passivation opening design for a bonding pad structure to protect a top metal layer under a metal pad within a sensing region. The present invention effectively prevents corrosion in the top metal layer due to probing, lengthens the bondability window, eliminates cracks in the under-layer dielectrics, and prevents peeling of the metal pad from the under-layer dielectrics. The present invention also improves pad finding capability (pad recognition capability), reduces pad pitch, and allows the bonding pad structures to be located over peripheral circuit areas, active areas, scribe lines or a combination thereof.

FIG. 1is a top view of an individual chip including bonding pad structures of the present invention. A semiconductor wafer comprises substantially isolated chips, and the isolated chip comprises a main area10defined by first scribe lines12extending in a first direction and second scribe lines14extending in a second direction. The individual chip10containing circuitry comprises an active area16and a peripheral area18. A plurality of bonding structures20is allowed on the active area16, the peripheral area18, the first scribe line12, the second scribe line14, or a combination thereof. The bonding pad structures20may be aligned in a single line or staggered to form CUP (circuit under pad) pads.

The bonding pad structures20with a top metal layer design and a passivation opening design for obtaining a metal-free area or a small metal area under a metal pad within a sensing region are described below.

FIRST EMBODIMENT

The present invention provides a bonding pad structure with a top metal layer design for obtaining a metal-free area or a small metal area under a metal pad within a sensing region.

FIG. 2Ais a cross-section of a bonding pad structure according to the first embodiment of the present invention.FIG. 2Bis a top view of the conductive ring shown inFIG. 2A.

A semiconductor substrate22with partially completed integrated circuits has a bonding region I for bonding a ball or a bump and a sensing region II for testing by probe pins or other implement. A first dielectric layer24, an next level dielectric of the substrate22, comprises a ring-shaped trench25which correspondingly defines a dielectric island24a. A first conductive layer26, an uppermost interconnection of the substrate22, fills the ring-shaped trench25to serve as a conductive ring26, thus enclosing the dielectric island24a. A passivation layer30is formed on the first dielectric layer24, and has an opening31corresponding to the bonding region I and the sensing region II, thus exposing the dielectric island24aand a sufficient area of the conductive ring26. A second conductive layer32is patterned on the first dielectric layer24and the passivation layer30within the bonding region I and the sensing region II to serve as a conductive pad32, in which the conductive pad32is directly connected to the conductive ring26without requiring via holes. A bonding element34, such as a ball or a bump, is bonded on the conductive pad32within the bonding region I. Moreover, a barrier layer28is formed on an interface between the conductive pad32and the conductive ring26for increasing adhesion therebetween.

The first dielectric layer24may be plasma oxide, HDP (high density plasma) oxide, dielectric with high resistance to mechanical stress, low-k dielectrics, fluorinated silicate glass (FSG) or silicon-based dielectrics. The conductive ring26may be copper (Cu), aluminum (Al), AlCu alloy, a copper manganese alloy or a copper-containing alloy. The conductive ring26is approximately 1˜50 μm in width and 0.5˜2 μm in depth. Preferably, a measurement ratio R1satisfies the formula: R1=Ar/Asand 0≦R1≦30%, where Aris the area of the conductive ring26formed within the sensing region II, and Asis the area of the sensing region II. The barrier layer28may be Ti, TiN, W, WN, Ta, TaN, or a combination thereof. The conductive pad32may be aluminum (Al), AlCu alloy or an aluminum-containing alloy. The bonding element34may be a gold ball used in wire bonding technology or a metal bump used in a flip chip technology.

In accordance with the top metal layer design, the conductive ring26occupies a small area of the sensing region II to achieve a metal-free area or a small metal area, thus overcoming problems caused by the conventional bonding pads and obtains the following advantages. The metal-free area or the small metal area effectively reduces the possibility of cracks penetrating the first dielectric layer24to the conductive ring26, thus preventing corrosion and layer-open problems. The metal-free or small metal area prevents peeling of the conductive pad32from the conductive ring26or the first dielectric layer24, thus eliminating pad-open problems and ensuring bonding reliability. Additionally, the pitch and size of the bonding pad structure20can be further reduced since the conductive ring26is not susceptible to damage from mechanical stress, thus allowing reduction in chip size for next generation technologies. The pad finding capability of the wire bonding tool is effectively improved as only one smooth dielectric island24ais enclosed by the conductive ring26. Finally, since the conductive ring26is directly connected to the conductive pad32without use of via holes or plugs, limitation in ring width and misalignment problems caused by a via hole design are eliminated, and various modifications of the conductive ring26and the conductive pad32are allowed.

Various modifications of the conductive ring26and the conductive pad32are herein described.

FIRST EXAMPLE

Based on design requirements of the top metal layer, the interconnections underlying the conductive ring26may be modified to have a ring, lattice, island, or solid profile.

FIG. 3Ais a cross-section of another conductive ring underlying the conductive ring26. Elements similar to those inFIG. 2Aare omitted here. A second dielectric layer36underlying the first dielectric layer24is provided. A third conductive layer38is patterned as a ring and embedded in the second dielectric layer36. A conductive plug40also is formed in the second dielectric layer36to electrically connect the conductive ring26to the third conductive layer38.

FIG. 3Bis a cross-section of a conductive lattice underlying the conductive ring26. Elements similar to those inFIG. 3Aare omitted here. The third conductive layer38is modified to form a lattice, in which an array of dielectric islands36ais provided and the dielectric islands36aare spaced apart from each other by the third conductive layer38. Alternately, the third conductive layer38is modified to form an array of independent plugs spaced apart from each other by the second dielectric layer36.

FIG. 3Cis a cross-section illustrating a conductive solid underlying the conductive ring26. Elements similar to those inFIG. 3Aare omitted here. The third conductive layer38is modified to have a solid form.

SECOND EXAMPLE

Based on the design requirements of the top metal layer, the conductive ring26, the conductive pad32, or a combination thereof may be further modified to have various geometric shapes.

FIGS. 4A˜4Fare top views illustrating examples of profile designs for the conductive ring26.FIGS. 5A˜5Fare top views illustrating examples of the profile designs for the conductive pad32.

The conductive ring26is a quadrilateral ring, and the corresponding dielectric island24ais a quadrilateral solid. InFIG. 4A, the conductive ring26is a square ring, and the corresponding dielectric island24ais a square solid. InFIG. 4B, the conductive ring26is a rectangular ring, and the corresponding dielectric island24ais a rectangular solid.

The conductive ring26is a circular ring, and the corresponding dielectric island24ais a circular solid. InFIG. 4C, the conductive ring26is a circular ring, and the corresponding dielectric island24ais a circular solid. InFIG. 4D, the conductive ring26is an elliptical ring; and the corresponding dielectric island24ais an elliptical solid.

The conductive ring26is a polygonal ring, and the corresponding dielectric island24ais a polygonal solid. InFIG. 4E, the conductive ring26is a hexagonal ring, and the corresponding dielectric island24ais a hexagonal solid. InFIG. 4F, the conductive ring26is an octagonal ring, and the corresponding dielectric island24ais an octagonal solid.

The conductive pad32may only be shaped into a geometric solid if the electrical connection between the conductive pad32and the conductive ring26is reliable. InFIG. 5A, the conductive pad32is a square solid. InFIG. 5B, the conductive pad32is a rectangular solid. InFIG. 5C, the conductive pad32is a circular solid. InFIG. 5D, the conductive pad32is an elliptical solid. InFIG. 5E, the conductive pad32is a hexagonal solid. InFIG. 5F, the conductive pad32is an octagonal solid.

THIRD EXAMPLE

Based on a quadrilateral design for the conductive ring26or the conductive pad32, at least one corner cut portion is provided to prevent peeling.

FIG. 6Ais a top view of corner cut portions of the conductive ring26.FIG. 6Bis a top view of corner cut portions of the conductive pad32. Elements similar to those inFIG. 2Bare omitted here.

InFIG. 6A, the conductive ring26comprises four corner cut portions42adjacent to four corners of the quadrilateral ring, respectively. The corner cut portion42prohibits the formation of the first conductive layer26, but allows the formation of the first dielectric layer24. Preferably, the corner cut portion42is a right triangle, where the hypotenuse41is approximately 0.5˜5 μm in length, an included angle θ1between the hypotenuse41and the X axis is approximately 10°˜80°, and a measurement ratio R2satisfies the formula: R2=At1/Ac1and 0<R2<80%, where At1is the area of the corner cut portion42, and Ac1is the corner area of the conductive ring26. The corner area Ac1satisfies the formula: Ac1=W1×W2, where W1is the X-axis width of the conductive ring26, W2is the Y-axis width of the conductive ring26, W1=1 μm˜10 μm, and W2=1 μm˜10 μm.

InFIG. 6B, the conductive pad32comprises four corner cut portions44adjacent to four corners of the quadrilateral solid, respectively. The corner cut portion44prohibits the formation of the second conductive layer32, but allows the formation of the passivation layer30. Preferably, the corner cut portion44is a right triangle, where the hypotenuse43is approximately 0.5˜10 μm in length, and an included angle θ2between the hypotenuse41and the X axis is approximately 10°˜80°.

FOURTH EXAMPLE

In order to clearly discriminate the sensing region II from the bonding region I, a marking notch is provided on the conductive ring26, the conductive pad32, or a combination thereof.

FIG. 7Ais a top view of the conductive ring26with a marking notch.FIG. 7Bis a top view of the conductive pad32with a marking notch. Elements similar to those inFIG. 2Bare omitted here.

InFIG. 7A, the conductive ring comprises two marking notches46, and two dielectric markings24bare correspondingly defined within the two marking notches46, respectively. The two marking notches46are approximately aligned in a line to delineate the sensing region II from the bonding region I. Each of the two marking notches46is composed of a bottom side46I and two lateral sides46II and46III. Preferably, a first-direction length L1from the lateral side46III to the edge of the conductive ring26for defining the bonding region I is approximately 40˜60 μm. Preferably, a first length S1of the dielectric marking24b, parallel to the bottom side46I, is approximately 1˜3 μm. Preferably, a second length S2of the dielectric marking24b, parallel to the lateral side46II, is approximately 0.5˜2 μm.

InFIG. 7B, the conductive pad32comprises two marking notches48, and two passivation markings30bare correspondingly defined within the two marking notches48, respectively. The two marking notches48are approximately aligned in a line to delineate the sensing region II from the bonding region I. Each of the two marking notches48is composed of a bottom side48I and two lateral sides48II and48III. Preferably, a first-direction length L2from the lateral side48III to the edge of the conductive pad32for defining the bonding region I is approximately 40˜60 μm. Preferably, a first length S1of the passivation marking30b, parallel to the bottom side48I, is approximately 1˜3 μm. Preferably, a second length S2of the passivation marking30b, parallel to the lateral side48II, is approximately 0.5˜2 μm.

Additionally, the marking notch design for the conductive ring26and the conductive pad32can be combined with the corner cut designs as described inFIGS. 6A and 6B.

FIG. 8Ais a top view of the conductive ring26with the marking notches46and the corner cut portions42.FIG. 8Bis a top view of the conductive pad32with the marking notches48and the corner cut portions44. Elements similar to those inFIGS. 6˜7are omitted here.

FIFTH EXAMPLE

Based on the design requirements of the top metal layer, a circuit under pad (CUP) scheme can be further provided under an extension portion the conductive ring26. Locating the circuit under the pad shortens some of the conductors and thereby decreases their inductance and resistance and also reduces the parasitic capacitance of the circuit.

FIG. 9Ais a cross-section of a CUP scheme50adjacent to the bonding pad structure20.FIG. 9Bis a top view of the conductive ring26and the CUP scheme50shown inFIG. 9A. Elements similar to those inFIGS. 6˜7are omitted here.

The conductive ring26comprises an extension portion26awhich extends from one peripheral edge of the conductive ring26and away from the bonding region I and the sensing region II. A CUP scheme50is formed adjacent to the extension portion26a. A buffer layer52is formed underneath the first dielectric layer24and has a circuit scheme54patterned therein. A plurality of conductive plugs56is formed in an array of via holes57of the first dielectric layer24. Thus, the extension portion26acan be electrically connected to the circuit scheme54through via holes57. Also, the circuit scheme54can be electrically connected to a lowermost conductive layer58through interconnections. Preferably, the number of via holes57for a signal circuit scheme is smaller than that for a power circuit scheme.

In addition, based on a combination of the conductive ring26and the CUP scheme50, the buffer layer52may be optional, and the conductive layers underlying the conductive ring26may be modified.

FIG. 10Ais a cross-section of one example of forming the CUP scheme50without using the buffer layer52. Elements similar to those inFIG. 9Aare omitted here. The different portion is that the buffer layer52is omitted, thus the circuit scheme54is formed in the first dielectric layer24.

FIG. 10Bis a cross-section of another example of forming the CUP scheme50underneath two conductive rings. Elements similar to those inFIG. 9Aare omitted here. The different portion is that the third conductive layer38is patterned as a ring and embedded in the second dielectric layer36, and is electrically connected to the conductive ring26through the conductive plug40. Also, the third conductive layer38has an extension portion38awhich extends from one peripheral edge of the ring to be electrically connected to the circuit scheme54through via holes57.

SECOND EMBODIMENT

The present invention provides a bonding pad structure with a passivation opening design for protecting a top metal layer within a sensing region.

FIG. 11Ais a cross-section of a bonding pad structure according to the second embodiment of the present invention.FIG. 11Bis a top view of the conductive ring26and the passivation layer30shown inFIG. 11A.

A semiconductor substrate22with partially completed integrated circuits has a bonding region I for bonding a ball or a bump and a sensing region II for testing by probe pins or other implement. A first dielectric layer24, an uppermost dielectric of the substrate22, comprises a ring-shaped trench25which correspondingly defines a dielectric island24a. A first conductive layer26, an uppermost conductive layer of interconnections in the substrate22, fills the ring-shaped trench25to serve as a conductive ring26, thus enclosing the dielectric island24a. A passivation layer30is formed on the first dielectric layer24, and has an opening31corresponding to the bonding region I, thus covering the conductive ring26located within the sensing region II. A second conductive layer32is formed overlying the first dielectric layer24and the passivation layer30within the bonding region I and the sensing region II to serve as a conductive pad32, in which the conductive pad32is directly connected to the conductive ring26without requiring via holes. A bonding element34, such as a ball or a bump, is bonded to the conductive pad32within the bonding region I. Moreover, a barrier layer28is provided on an interface between the conductive pad32and the conductive ring26.

Preferably, the first dielectric layer24may be plasma oxide, HDP (high density plasma) oxide, dielectric with high resistance to mechanical stress, low-k dielectrics, FSG, or silicon-based dielectrics. The conductive ring26may be copper (Cu), aluminum (Al), AlCu alloy, a copper manganese alloy or a copper-containing alloy. The conductive ring26is approximately 1˜50 μm in width and 0.5˜2 μm in depth. The barrier layer28may be Ti, TiN, W, WN, Ta, TaN, or a combination thereof. The conductive pad32may be aluminum (Al), AlCu alloy or an aluminum-containing alloy. The bonding element34may be a gold ball used in wire bonding technology or a metal bump used in a flip chip technology.

Accordingly, the passivation layer30covers the conductive ring26within the sensing region II to prevent damage to the conductive ring26within the sensing region caused by mechanical stress. The passivation layer30adjacent to the demarcation between the bonding region I and the sensing region II can also serve as a marking strip, which has the same function of the marking notches as described inFIGS. 7A and 7B. In addition, other interconnections underlying the conductive ring26may be modified to have a ring, lattice, island, or solid profile as disclosed inFIGS. 3A˜3C.

The passivation opening design for the passivation layer30achieves the following advantages. The passivation layer30covers the conductive ring26within the sensing region II to prohibit dielectric cracks from penetrating into the conductive ring26, thus preventing corrosion and layer-open problems. The passivation layer also prevents peeling of the conductive pad32from the conductive ring26or the first dielectric layer24, thus eliminating a pad-open problem and ensuring bonding reliability. The pitch and size of the bonding pad structure20can be further reduced since the conductive ring26is not susceptible to damage from mechanical stress, thus allowing chip size reduction for next generation technologies. The pad finding capability can be effectively improved during wire bonding as only one dielectric island24ais enclosed by the conductive ring26,. Finally, the conductive ring26is directly connected to the conductive pad32without use of via holes or plugs, thus limitation in ring width and misalignment problems caused by via hole design are eliminated, enabling various modifications of the conductive ring26and the conductive pad32.

Various modifications of the conductive ring26and the conductive pad32are herein described.

FIRST EXAMPLE

Based on the passivation opening design rule, the first conductive layer26may be further modified to have a lattice form or as independent plugs.

FIG. 12Ais a cross-section of the first conductive layer26patterned as a lattice form.FIG. 12Bis a top view of the first conductive layer26shown inFIG. 12A. Elements similar to those inFIGS. 11A and 11Bare omitted here. The first dielectric layer24comprises a plurality of dielectric islands24a. The first conductive layer26fill the trenches of the first dielectric layer24to completely surround the dielectric islands24a, thus achieving a lattice form.

FIG. 13Ais a cross-section of the first conductive layer26patterned as independent plugs.FIG. 13Bis a top view of the first conductive layer26shown inFIG. 13A. Elements similar to those inFIGS. 11A and 11Bare omitted here. The first dielectric layer24comprises a plurality of via holes. The first conductive layer26fills the via holes of the first dielectric layer24to form a plurality of independent plugs26. Additionally, the independent plugs26can be electrically connected to each other through a third conductive layer38underlying the plugs26.

Other interconnections underlying the first conductive layer26may also be modified to have a ring, lattice, island, or solid profile as disclosed inFIGS. 3A˜3C.

SECOND EXAMPLE

Based on the passivation opening design rule, the first conductive layer26may be further modified to have a solid form.

FIG. 14Ais a cross-section of the first conductive layer26patterned as a solid form.FIG. 14Bis a top view of the first conductive layer26shown inFIG. 14A. Elements similar to those inFIGS. 11A and 11Bare omitted here. The first conductive layer26fills a large-size trench of the first dielectric layer24to become a solid form. In addition, other interconnections underlying the first conductive layer26may be modified to have ring, lattice, island, or solid profiles as disclosed inFIGS. 3A˜3C.

THIRD EXAMPLE

Based on the passivation opening design rule, the first conductive layer26, the conductive pad32or a combination thereof may be further modified to have various profiles including quadrilateral, circular and polygonal profiles as described inFIGS. 4A˜4FandFIGS. 5A˜5F. Features similar to those inFIGS. 4˜5are omitted here.

FOURTH EXAMPLE

Based on the passivation opening design rule, the first conductive layer26, the conductive pad32or a combination thereof may be further modified with at least one corner cut portion as described inFIGS. 6A and 6B. Features similar to those inFIGS. 6A and 6Bare omitted here.

FIFTH EXAMPLE

Based on the passivation opening design rule, the first conductive layer26, the conductive pad32or a combination thereof may be further modified with a marking notch as described inFIGS. 7A and 7BandFIGS. 8A and 8B. Features similar to those inFIGS. 7˜8are omitted here.

SIXTH EXAMPLE

Based on the passivation opening design rule, a circuit under pad (CUP) scheme50can be provided under an extension portion26athe first conductive layer26as described inFIGS. 9˜10. Features similar to those inFIGS. 9˜10are omitted here.