Dynamic back-up storage system with rapid restore and method of operation thereof

A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.

TECHNICAL FIELD

The present invention relates generally to a dynamic back-up storage system, and more particularly to a system for dynamic back-up of memory data with rapid restore support.

BACKGROUND ART

Contemporary high performance computing main memory systems are generally composed of one or more memory devices, such as dual in-line memory modules (DIMMs), which are connected to one or more memory controllers and/or processors. The DIMMs may be connected via one or more memory interface elements such as buffers, hubs, bus-to-bus converters, etc. The memory devices are generally located in a memory subsystem and are often connected via a pluggable interconnection system by one or more connectors to a system board, such as a PC motherboard.

Overall computer system performance is affected by each of the key elements of the computer structure, including the performance/structure of the processor, any memory caches, the input/output (I/O) subsystem, the efficiency of the memory control functions, the performance of the main memory devices, any associated memory interface elements, and the type and structure of the memory interconnect interface.

Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved and/or innovative solutions to maximizing overall system performance and density by improving the memory system design. High-availability systems present further challenges as related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems in regard to mean-time-between-failure (MTBF), in addition to offering additional functions, increased performance, increased storage, lower operating costs, etc.

Some vital computer applications rely on data integrity and go to extreme lengths to protect the data from unexpected faults, such as power failures. Most storage systems make some provision for storing pending data in the event of a power failure, but most are on a best effort basis and rely on transient energy sources to preserve as much data as possible before the energy runs out. In disk drives for instance, the spinning media becomes a source of energy utilized to store any residual unwritten data.

Data that may not have been transferred from system memory to a peripheral storage system may be at a greater risk. In applications that rely on data integrity other accommodations must be made at the system level. A standard approach to preserving system operation is a battery back-up structure, but this approach consumes significant space and may only be a short term solution. Beyond the duration of the battery back-up system, the critical data would be lost.

Other frequent customer requirements further exacerbate the memory system design challenges, and include such items as ease of upgrade and reduced system environmental impact (such as space, power and cooling). In addition, customers are requiring the ability to access an increasing number of higher density memory devices (e.g. DDR2 and DDR3 DRAMs) at faster and faster access speeds.

Thus, a need still remains for a dynamic back-up storage system with rapid restore, that can positively protect vital system data for as long as necessary. In view of the increasing reliance on computer data structures, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.

DISCLOSURE OF THE INVENTION

The present invention provides a method for operating a dynamic back-up storage system including: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.

The present invention provides a dynamic back-up storage system including: a high speed memory with a first rank memory device and subsequent ranks of memory devices; a non-volatile memory for saving data from the high speed memory; and a control logic unit for controlling access of the high speed memory by a central processing unit includes the first rank memory device accessed before the subsequent ranks of memory devices are restored from the non-volatile memory.

BEST MODE FOR CARRYING OUT THE INVENTION

Where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with similar reference numerals. For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the Earth, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane, as shown in the figures. The term “on” means that there is direct contact between elements.

The term “processing” as used herein includes assembling data structures, transferring data structures to peripheral storage devices, manipulating data structures, and reading data structures from external sources. Data structures are defined to be files, input data, system generated data, such as calculated data, and program data.

Referring now toFIG. 1, therein is shown a functional block diagram of a dynamic back-up storage system100with rapid restore, in an embodiment of the present invention. The functional block diagram of the dynamic back-up storage system100depicts a carrier102, such as a printed circuit board, having a first rank memory device104and subsequent ranks of memory devices106. The first rank memory device104and the subsequent ranks of memory devices106may be high speed memory107, such as random access memory (RAM), that lose data when power is removed.

A first multiplexer108may be coupled to the first rank memory device104. The first multiplexer108may provide address and data lines to the first rank memory device104. It is to be understood that the data lines may be bi-directional and the address lines are unidirectional from the first multiplexer108. The first multiplexer108may have a control line110for managing the output of the first multiplexer108and selecting between a host interface112and a back-up interface114.

It is understood that the host interface112and the back-up interface114both have a substantially identical number of address and data lines. The host interface112may be sourced from a memory control interface116, which may include an interface connector (not shown). The back-up interface114may be sourced from a control logic unit118, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

A second multiplexer120may be coupled to the subsequent ranks of memory devices106. The subsequent ranks of memory devices106may include additional memory devices of equal or different size as compared to the first rank memory device104. The subsequent ranks of memory devices106may include any number of additional memory devices. By way of example, the subsequent ranks of memory devices106is shown to include three of the additional memory devices, but any number of the additional memory devices may be coupled to the second multiplexer120. This is an example only and the subsequent ranks of memory devices106may include a different number of the additional memory devices.

A back-up control line122may be sourced from the control logic unit118. The back-up control line122may manage the output of the second multiplexer120for selecting between the host interface112and the back-up interface114.

A non-volatile memory124may include a number of flash memory chips having a sufficient capacity to store all of the data from the first rank memory device104and the subsequent ranks of memory devices106. The non-volatile memory124may be coupled to the control logic unit118through an NV memory bus126. The NV memory bus126may include data lines as well as address and control lines.

An interface status bus128may couple the memory control interface116to the control logic unit118. The interface status bus128may convey availability of the first rank memory device104and the subsequent ranks of memory devices106. The interface status bus128may also provide early warning for system shut down or other error conditions that may activate a memory back-up process.

It will be understood by those having ordinary skill in the art that the above described hardware may detect system fault conditions in order to initiate a total memory back-up process. During the total memory back-up process the contents of the first rank memory device104and the subsequent ranks of memory devices106are stored in the non-volatile memory124.

It has been discovered that during system power-on, the first rank memory device104may be restored from the non-volatile memory124and presented to the system central processing unit (CPU), not shown, in substantially less time than it takes to restore all of the system memory. By presenting the first rank memory device104to the CPU the system may start normal operation while the subsequent ranks of memory devices106are restored.

Referring now toFIG. 2, therein is shown a functional block diagram of a computer system200with critical data needs. The functional block diagram of the computer system200depicts a central processing unit (CPU)202coupled to a power source204. It is understood that while the power source204is shown coupled to the CPU202it is also the main source of power for all of the devices shown as part of the computer system200.

The CPU202may be coupled to a memory control chip (MC)206which controls a memory bus208comprising data and control lines that manage the transfer of data between the dynamic back-up storage system100, such as a specialized memory DIMM as shown in this example. It is understood that the dynamic back-up storage system100may take a different form rather than a memory DIMM without changing its function. It is further understood that the memory control chip206may be integrated with the CPU202into a single device, which still supports the transfer of data.

A basic input/output system (BIOS) memory210may be coupled to the memory bus208for initialization of the input/output structure of the CPU202. The CPU202may also be coupled to an input/output controller (I/O C)212that manages the peripheral devices that may be used by the CPU202.

The peripheral devices used by the CPU202may include a disk interface controller214, a universal serial bus (USB) interface controller216, and a graphics interface controller218. Other peripheral devices may include a network interface controller (not shown), but it is not required to explain the function of the dynamic back-up storage system100.

A disk system220may be coupled to the disk interface controller214. The disk system220may be comprised of a single disk drive220or multiple disk drives220configured either individually or as a random array of independent disks (RAID).

The USB interface controller216may be coupled to human interface devices222, such as a keyboard, a mouse or joystick, an audio system or a combination of these and other such devices. The human interface devices222may be used to select options to determine what programs are executed by the CPU202or to access file systems that may be saved within the disk system220.

A display224may be coupled to the graphics interface controller218. The display224may allow an operator (not shown) to execute selected programs, display data, or monitor progress of operations.

During normal operations the operator may select and activate a program from a list displayed on the display224. The selected program requires the CPU202to locate the selected program on the disk system220and transfer it to the dynamic back-up storage system100for execution. The CPU would initiate the transfer by initializing the I/O C212and the MC206to move the data that makes-up the selected program. Once the selected program is loaded in the first rank memory device104, ofFIG. 1, the subsequent ranks of memory devices106, ofFIG. 1, or a combination thereof it may be executed by the CPU202.

If an unexpected interruption of the power source204occurs the dynamic back-up storage system100may take the entire content of the first rank memory device104and the subsequent ranks of memory devices106and save it in the non-volatile memory124, ofFIG. 1, in order to protect the data and the state of execution of the selected program.

When the power source204is once again on and stable the dynamic back-up storage system100will restore the data to the first rank memory device104and the subsequent ranks of memory devices106then allow the CPU202to resume execution of the selected program from the same operation that was interrupted by the power source204removing the power.

It has been discovered that a portion of the high speed memory107, such as the first rank memory device104, may be made available to the CPU202before all of the memory has been restored. This early availability may shorten the recovery time for the data critical operations performed by the CPU202. Examples of data critical operations might be plotting real-time traffic patterns for air traffic control, or processing magnetic real-time imaging (MRI) data during an arthroscopic operation. The time saved by restoring the active data for use by the CPU202may prevent an accident that may endanger lives.

Referring now toFIG. 3, therein is shown an operational flowchart of a restore process300of the dynamic back-up storage system100as performed by the present invention. The operational flowchart of the restore process300depicts an initialize restore block302, which clears all of the restore flags (not shown) and prepares to copy the stored data back into the first rank memory device104, ofFIG. 1, and the subsequent ranks of memory devices106, ofFIG. 1, for use by the CPU202, ofFIG. 2. During this process the first rank memory device104and the subsequent ranks of memory devices106are not available to the CPU202. The CPU202may access the BIOS memory210in order to initialize the attached peripherals.

The flow proceeds to a select first rank block304. The first rank memory device104is a segment of the entire capacity of the high speed memory107that may be restored independently. By way of an example, if the entire accessible memory may have a capacity of 4 GB and the first rank memory device104may represent a 1 GB segment of the memory. Also by selecting the first rank memory device104, any of the subsequent ranks of memory devices106are blocked from both the CPU202and the internal logic (not shown) within the control logic unit118, ofFIG. 1.

The flow proceeds to an initialize transfer block306in order to load the memory segment pointers within the control logic unit118in order to properly load the first rank memory device104and the subsequent ranks of memory devices106with the saved data. In some conditions the first rank memory device104and the subsequent ranks of memory devices106may remain clear and in an initialized state.

A transfer data block308may transfer some amount of data between the non-volatile memory124, ofFIG. 1and the first rank memory device104or the subsequent ranks of memory devices106. If the first rank memory device104and the subsequent ranks of memory devices106are to remain initialized, the transfer length may be initialized to zero length, status done set, and all ranks done set. In this condition no data will be transferred and the entire memory may be enabled for use by the CPU202, ofFIG. 2.

A done check310is performed as a check of the current rank of memory being filled. If the done check310finds that more data must be transferred, the not done branch is taken to an increment addresses block312. The address within the control logic unit118will be incremented in order to address the next line of data within the currently addressed rank of memory. The flow then returns to the entry for the transfer data block308.

If the done check310does indicate that the current rank is completely restored, the flow moves to a first rank done check314. If the first rank done flag is not set in the control logic unit118, the flow proceeds to a set first rank done block316, which activates a first rank done flag within the control logic unit118and increments the rank address. The flow then proceeds to an enable to CPU block318. In this block the first rank memory device104is enabled to the CPU202for program execution. The subsequent ranks of memory devices106are enabled to communicate with the control logic unit118in order to continue the memory restore process. When the first rank done flag is first set within the control logic unit118, the memory controls switch to activate the subsequent ranks of memory devices106for access by the control logic unit118only.

If the first rank done check314finds that the first rank memory device104had been restored on a previous iteration, an increment rank pointers block322may indicate which of the subsequent ranks of memory devices106was just restored. An all ranks done check320will determine whether the restore is complete. If the restore of the subsequent ranks of memory devices106is not complete the flow will re-enter the transfer data block308. This loop will continue until all of the memory has been restored with the data that was saved in the non-volatile memory124.

When the all ranks done320detects that indeed all of the ranks have been restored, the flow proceeds to an enable all ranks to CPU block324. In this block the control logic unit118switches control of all of the memory ranks to the CPU202. From this event onward the CPU202may have access to all of the restored data that was available before the power source204, ofFIG. 2, removed the power.

It has been discovered that a time delay between power on and the data available time for the first rank memory device104may be reduced to 25-40% of the delay that a prior art back-up memory device can provide. As the maximum addressable memory increases these delays may become on the order of minutes for the prior art solutions. During the power on initialization of the CPU, most if not all of the memory accesses will occur in the first rank memory device. By allowing that access to occur in an earlier timeframe, the rest of the memory may be restored while the CPU202prepares for full memory operation. This decrease in operational delay may have a significant impact on real-time applications as previously mentioned.

Referring now toFIG. 4, therein is shown a functional block diagram of a control logic unit400in an embodiment of the present invention. The functional block diagram of the control logic unit400depicts an access/operational control block402, which may contain the logic required to shorten the restore time delay as experienced by the CPU202, ofFIG. 2. The access/operational control block402may include control logic and state machines that manage the operation of the back-up and restore of the data in the first rank memory device104, ofFIG. 1, and the subsequent ranks of memory devices106, ofFIG. 1.

An operational interface404may be coupled to the access/operational control block402. The operational interface404may include status and control lines (not shown) for signaling the availability of the first rank memory device104and the subsequent ranks of memory devices106to the CPU202as well as operating the first multiplexer108, ofFIG. 1, and the second multiplexer120, ofFIG. 1.

A power management block406may detect the interruption of power and supply a residual power source (not shown) in order to save the data from the first rank memory device104and the subsequent ranks of memory devices106. The access/operational control block402may receive the notification of the interruption of power and proceed to save the data from the first rank memory device104and the subsequent ranks of memory devices106in the non-volatile memory124, ofFIG. 1.

The access/operational control block402may rely on an address management block408to manage the source addresses for the first rank memory device104and the subsequent ranks of memory devices106as well as the non-volatile memory124throughout the back-up process. A data transfer state machine410controls the data movement between the first rank memory device104and the subsequent ranks of memory devices106including managing the first multiplexer108and the second multiplexer120.

A dynamic random access memory controller412may control the interface timing for the first rank memory device104and the subsequent ranks of memory devices106as well as any required refresh timing. A non-volatile storage controller414may manage the interface timing requirements for the non-volatile memory124.

The above description of the control logic unit400is an example only and other patricians are possible. The primary function of the control logic unit400is to provide a data back-up and restore controller that provides a fast release for providing access to the first rank memory device before the entire memory has been restored.

Referring now toFIG. 5, therein is shown a flow chart of a method500of operation of dynamic back-up storage system in an embodiment of the present invention. The method500includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices in a block502; providing a non-volatile memory for saving data from the high speed memory in a block504; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device in a block506.

The resulting method, process, apparatus, device, product, and/or system is straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.