Switched capacitor circuit utilizing delayed control signal and inverting control signal for performing switching operation and related control method

A switched capacitor circuit includes an inverter, a first capacitor, and a first switch unit. The inverter is arranged to receive a control signal to generate an inverting control signal corresponding to the control signal. The first capacitor is coupled between a first output port and a first node. The first switch unit is arranged to receive a first input signal and a second input signal, and selectively couple the second input signal to the first node according to the first input signal. The first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The disclosed embodiments of the present invention relate to a switched capacitor circuit, and more particularly, to a switched capacitor circuit utilizing a delayed control signal and an inverting control signal for performing switching operations and related control method thereof.

2. Description of the Prior Art

In a modern communication system, a local oscillation (LO) signal is generated mainly by a voltage-controlled oscillator (VCO). Regarding a VCO including an inductor-capacitor tank (LC tank) circuit, the VCO can provide an accurate LO signal to improve the sensitivity of radio frequency (RF) transceivers due to its high quality factor and signal purity.

In general, an on-chip inductor occupies a large area. Therefore, an oscillation frequency of a VCO is varied by adjusting capacitance values in most cases, where a switched capacitor array is used to generate discrete switch capacitance values according to switch voltages. However, a junction capacitance effect may occur in a switched capacitor circuit of the switched capacitor array. Besides, when coupled to voltages of output ports, transistors in the switched capacitor circuit may turn on accidentally, thus degrading the performance of the VCO.

Thus, there is a need for an innovative circuit design, which can improve the switching quality of the switched capacitor circuit with no increase or negligible increase in the layout area, to solve the abovementioned problems.

SUMMARY OF THE INVENTION

It is one objective of the present invention to provide a switched capacitor circuit, which utilizes a delayed control signal and an inverting control signal for performing switching operations, and related control method thereof to solve the abovementioned problems.

According to an embodiment of the present invention, an exemplary switched capacitor circuit is disclosed. The exemplary switched capacitor circuit includes an inverter, a first capacitor and a first switch unit. The inverter is arranged to receive a control signal to generate an inverting control signal corresponding to the control signal. The first capacitor is coupled between a first output port and a first node. The first switch unit is arranged to receive a first input signal and a second input signal, and selectively couple the second input signal to the first node according to the first input signal. The first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal.

According to another embodiment of the present invention, another exemplary switched capacitor circuit is disclosed. The exemplary switched capacitor circuit includes an inverter, a capacitor and a switch unit. The inverter is arranged to generate an inverting control signal according to a control signal. The capacitor is coupled between an output port and a node. The switch unit has a drain coupled to the node, a source for receiving the inverting control signal, and a gate controlled by the control signal.

According to an embodiment of the present invention, an exemplary method for controlling a switched capacitor circuit is disclosed. The switched capacitor circuit comprises a capacitor. The capacitor is coupled between an output port and a node. The exemplary method comprises: receiving a control signal; generating an inverting control signal corresponding to the control signal according to the control signal; and selectively coupling a second input signal to the node according to a first input signal, wherein the first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal.

The proposed switched capacitor circuit, which utilizes a delayed control signal and an inverting control signal for performing switching operations, can have a high quality factor of the differential switched capacitor circuit, avoid the junction capacitance effect in the VCO application, and prevent the switch unit from accidentally turning on. Moreover, there is almost no increase in the layout area when the proposed switched capacitor circuit is employed. Besides, there is no complicated circuit configuration required.

DETAILED DESCRIPTION

Advantages of switched capacitor circuits disclosed in the present invention are described with reference to an application of using the LC tank circuit in the VCO. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. In other words, the switched capacitor circuits disclosed in the present invention are applicable to, but not limited to, VCOs, resonant tank circuits or other frequency-adjustable switched capacitor array circuits.

Please refer toFIG. 1, which is a diagram illustrating an exemplary switched capacitor circuit according to a first embodiment of the present invention. The switched capacitor circuit100includes an inverter110, a first capacitor C1and a first switch unit120. The inverter110is arranged to receive a control signal CS to generate an inverting control signal ICS corresponding to the control signal CS. The first capacitor C1is coupled between a first output port V_OUT1and a first node N1. The first switch unit120is arranged to receive a first input signal S_IN1and a second input signal S_IN2, and selectively couple the second input signal S_IN2to the first node N1according to the first input signal S_IN1, wherein the first input signal S_IN1is determined by one of the control signal CS and the inverting control signal ICS, and the second input signal S_IN2is determined by the other of the control signal CS and the inverting control signal ICS.

By way of example, the first switch unit120in this embodiment may be a transistor M1whose gate, source and drain are coupled to the first input signal S_IN1, the second input signal S_IN2and the first node N1, respectively. Please note that, in this embodiment, the first switch unit120directly receives the control signal CS as the first input signal S_IN1, and directly receives the inverting control signal ICS as the second input signal S_IN2. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. In an alternative design, the switch unit120may directly receive the inverting control signal ICS as the first input signal S_IN1, and directly receive the control signal CS as the second input signal S_IN2. To put it another way, the inverter110may be coupled to the gate of the transistor M1. In another alternative design, the control signal CS may be properly processed (e.g., amplified or attenuated) before fed into the first switch unit120to serve as the first input signal S_IN1, and the inverting control signal ICS may be properly processed (e.g., amplified or attenuated) before fed into the first switch unit120to serve as the second input signal S_IN2. In this embodiment, in a case where the first input signal S_IN1(i.e., the control signal CS) is at a first level (e.g., a high voltage level), the second input signal S_IN2(i.e., the inverting control signal ICS) coupled to the source of the transistor M1is at a low voltage level. Therefore, the transistor M1may be turned on, resulting in a current flowing from the first node N1to the transistor M1(i.e., the first switch unit120). In a case where the first input signal S_IN1(i.e., the control signal CS) is at a second level (e.g., a low voltage level), the second input signal S_IN2(i.e., the inverting control signal ICS) coupled to the source of the transistor M1is at a high voltage level. Therefore, even if the transistor M1is turned off, leakage current is still allowed to flow from the transistor M1(i.e., the first switch unit120) to the first node N1to increase a voltage of the first node N1, which may reduce/alleviate the junction capacitance effect.

Please refer toFIG. 2, which is a diagram illustrating an exemplary switched capacitor circuit according to a second embodiment of the present invention. The switched capacitor circuit200uses the design concept of a differential circuit and the design concept of the switched capacitor circuit100shown inFIG. 1. The switched capacitor circuit200includes the inverter110, first capacitor C1and first switch unit120shown inFIG. 1, and further includes a second capacitor C2, a second switch unit230, and a third switch unit240. The second capacitor C2is coupled between a second output port V_OUT2and a second node N2. The second switch unit230is coupled between the first node N1and the second node N2, and arranged to selectively couple the first node N1to the second node N2according to the first input signal S_IN1. The third switch unit240, coupled to the second node N2, is arranged to receive the first input signal S_IN1and the second input signal S_IN2and selectively couple the second input signal S_IN2to the second node N2according to the first input signal S_IN1. It should be noted that the first input signal S_IN1is determined by one of the control signal CS and the inverting control signal ICS, and the second input signal S_IN2is determined by the other of the control signal CS and the inverting control signal ICS.

By way of example, the first switch unit120, the second switch unit230and the third switch unit240in this embodiment are a first transistor M1, a second transistor M2and a third transistor M3, respectively. Gates of the first, the second and the third transistors M1-M3are all coupled to the first input signal S_IN1, drains of the first and the second transistors M1and M2are both coupled to the first node N1, sources of the first and the third transistors M1and M3are both coupled to the second input signal S_IN2, and a source of the second transistor M2and a drain of the third transistor M3are both coupled to the second node N2. In a case where the first input signal S_IN1(i.e., the control signal CS) is at a first level (e.g., a high voltage level), the second input signal S_IN2(i.e., the inverting control signal ICS), coupled to the sources of the first transistor M1and the third transistor M3, is at a low voltage level. Therefore, the first, the second and the third transistors M1-M3may be turned on. In addition, the first capacitor C1and the second capacitor C2may be regarded as ideal grounded capacitors. In a case where the first input signal S_IN1(i.e., the control signal CS) is at a second level (e.g., a low voltage level), the second input signal S_IN2(i.e., the inverting control signal ICS), coupled to the sources of the first transistor M1and the third transistor M3, is at a high voltage level. Therefore, even if the first, the second and the third transistors M1-M3are turned off, leakage current is still allowed to flow from the first transistor M1to the first node N1to increase a voltage of the first node N1, and flow from the third transistor M3to the second node N2to increase a voltage of the second node N2, which may not only prevent the second transistor M2from turning on but also reduce/alleviate the junction capacitance effect.

It should be noted that the voltage increase at the second node N2due to the leakage current may be small (e.g., hundreds of milivolts). Thus, when the voltage of the second node N2is coupled to a higher voltage through the second output port V_OUT2, the voltage of the second node N2may still be lower than the gate voltage of the second transistor M2, which may cause the second transistor M2to turn on accidentally. Please refer toFIG. 3, which is a timing diagram of the switched capacitor circuit200shown inFIG. 2. As shown inFIG. 3, the control signal CS is at a high voltage level before a time point T1. In addition, the first, the second and the third transistors M1-M3are all turned on, and the voltages of the first node N1and the second node N2may be regarded as the grounded voltages (i.e., zero voltages). At the time point T1, the control signal CS is switched from the high voltage level to a low voltage level, which implies that the second transistor M2should be cut off ideally. In a case where the voltages of the first and the second nodes N1and N2are coupled to higher voltages through the first and the second output ports V_OUT1and V_OUT2, respectively, the voltage of the second node N2is lower than the gate voltage (i.e., the zero voltage) of the second transistor M2, which causes the second transistor M2to turn on accidentally. Thus, the oscillation frequency accuracy and the signal purity of the VCO may be affected.

Please refer toFIG. 4andFIG. 5together.FIG. 4is a diagram illustrating an exemplary switched capacitor circuit according to a third embodiment of the present invention, andFIG. 5is a timing diagram of the switched capacitor circuit shown inFIG. 4. The architecture of the switched capacitor circuit400is based on that of the switched capacitor circuit200shown inFIG. 2, and the major difference therebetween is that the switched capacitor circuit400further includes a delay unit D, wherein the delay unit D is coupled to the first switch unit120, the second switch unit230and the third switch unit240, and configured to delay the first input signal S_IN1to generate the delayed first input signal S_IN1. In addition, the second switch unit230selectively couples the first node N1to the second node N2according to the delayed first input signal S_IN1, and the third switch unit240selectively couples the second input signal S_IN2to the second node N2according to the delayed first input signal S_IN1. A delay time by which the first input signal S_IN is delayed, or a delay time caused by the delay unit D, may be determined according to an impedance of the first capacitor C1and an impedance of the first switch unit120, or determined according to an impedance of the second capacitor C2and an impedance of the third switch unit240.

As shown inFIG. 5, the control signal CS is at a high voltage level before a time point T1. In addition, the first, the second and the third transistors M1-M3are all turned on, and the voltages of the first node N1and the second node N2may be regarded as the grounded voltages (i.e., zero voltages). During a period between the time point T1and a time point T2(i.e., during a delay period TD), although the control signal CS has been switched to a low voltage level, the signal received at the gate of the second transistor M2is still at the high voltage level. In the meantime, the gates of the first transistor M1and the third transistor M3are both coupled to the inverting control signals ICS having the high voltage level. During the delay period TD, the voltages of the first node N1and the second node N2may be charged to a predetermined voltage (e.g., the aforementioned high voltage level). As mentioned above, the delay period TD may be determined according to the impedance of the first capacitor C1and the impedance of the first switch unit120, or determined according to the impedance of the second capacitor C2and the impedance of the third switch unit240. Therefore, the delay time caused by the delay unit D, as well as the predetermined voltage, may depend on the actual design considerations/requirements. In addition, the delay unit D is configured to prevent oscillation voltages of the first node N1and the second node N2from being lower than zero. After the time point T2, because the voltages of the first node N1and the second node N2have been charged to the predetermined voltage, and the gate of the second transistor M2has received the delayed first input signal S_IN1(having the low voltage level), the accidental turn-on of the second transistor M2may be avoided. In brief, during the delay period TD, the voltages of the first node N1and the second node N2may be boosted to sufficiently high voltages to prevent the second transistor M2from accidentally turning on, which improves the oscillation frequency accuracy and the signal purity.

Please note that the aforementioned corresponding relationship between the first and the second input signals and the control signal and the inverting control signal is for illustrative purposes only, and is not meant to be a limitation of the present invention. In an alternative design, the first switch unit120may directly receive the inverting control signal ICS as the first input signal S_IN1, and directly receive the control signal CS as the second input signal S_IN2. In other words, the inverter110is coupled to the gate of the first transistor M1, and the delay unit D is coupled to the sources of the first transistor M1and the third transistor M3. In another alternative design, the delay unit D and the inverter110may be replaced or combined with each other.

Furthermore, the switched capacitor circuit100having a single-ended output shown inFIG. 1may use the design concept of the delay unit shown inFIG. 4to improve the performance of the VCO. Please refer toFIG. 6, which is a diagram illustrating an exemplary switched capacitor circuit according to a fourth embodiment of the present invention. The architecture of the switched capacitor circuit600is based on that of the switched capacitor circuit100shown inFIG. 1, and the major difference therebetween is that the switched capacitor circuit600further includes a delay unit D, wherein the delay unit D is coupled to the first switch unit120, and configured to delay the first input signal S_IN1to generate the delayed first input signal S_IN1. In addition, the first switch unit120selectively couples the second input signal S_IN2to the first node N1according to the delayed first input signal S_IN1, wherein a delay time by which the first input signal S_IN is delayed may be determined according to an impedance of the first capacitor C1and an impedance of the first switch unit120. As a person skilled in the art can readily understand the operation of the switched capacitor circuit600after reading above paragraphs, further description is omitted for brevity.

As can be known from above descriptions, it should be appreciated that the proposed switched capacitor circuit may be applicable to, but not limited to, VCOs, resonant tank circuits or other frequency-adjustable switched capacitor array circuits. Therefore, employing the proposed switched capacitor circuit may avoid the junction capacitance effect in the VCO application, improve the qualify factor of the VCO, and prevent the switch unit from accidentally turning on. Moreover, there is almost no increase in the layout area when the proposed switched capacitor circuit is employed. Besides, there is no complicated circuit configuration required.