Semiconductor package and method of fabricating the same

According to example embodiments, a semiconductor package includes: a lower molding element; a lower semiconductor chip in the lower molding element and having lower chip pads on an upper surface and at an areas close to first and second sides of the lower molding element; conductive pillars surrounding the lower semiconductor chip and passing through the lower molding element; an upper semiconductor chip on the upper surface of the lower molding element and lower semiconductor chip, the upper semiconductor chip having upper chip pads on a top surface and at areas close to third and the fourth sides of the upper semiconductor chip, and a connecting structure on the lower molding element and the upper semiconductor chip and electrically connecting each of the lower chip pads and upper chip pads to a corresponding conductive pillar. The upper semiconductor chip is substantially orthogonal to the lower semiconductor chip.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0101153 filed on Sep. 12, 2012, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Example embodiments of inventive concepts relate to a semiconductor package including a semiconductor chip having chip pads disposed on an upper surface thereof close to two opposite sides, and a method of fabricating the same.

2. Description of Related Art

A semiconductor package may include at least one semiconductor chip. Various studies for achieving high integration and improving reliability have been conducted on semiconductor packages.

SUMMARY

Example embodiments of inventive concepts relate to a semiconductor package including a semiconductor chip having chip pads disposed on an upper surface thereof close to two opposite sides, and/or a method of fabricating the same.

Example embodiments of inventive concepts relate to a semiconductor package that limits (and/or prevents) damage to an electrical connection between chip pads of a semiconductor chip from an external environment, and/or a method of fabricating the same.

Features and/or advantages of example embodiments of inventive concepts are not limited to the foregoing; other features and/or advantages may become apparent to those of ordinary skill in the art based on the following descriptions.

In accordance with example embodiments of inventive concepts, a semiconductor package includes: a lower molding element including a first side, a second side opposite the first side, a third side substantially perpendicular to the first side, and a fourth side opposite the third side; a lower semiconductor chip in the lower molding element, the lower semiconductor chip including lower chip pads on an upper surface of the lower semiconductor chip and at areas close to the first side and the second side of the lower molding element; conductive pillars surrounding the lower semiconductor chip and passing through the lower molding element; an upper semiconductor chip on the upper surface of the lower molding element and the lower semiconductor chip, the upper semiconductor chip including upper chip pads on a top surface of the supper semiconductor chip and at areas close to the third side and the fourth side of the lower molding element, and a connecting structure on the lower molding element and the upper semiconductor chip, the connecting structure electrically connecting each of the lower chip pads and upper chip pads to a corresponding one of conductive pillars. A level of the upper surface of the lower semiconductor chip is equal to a level of an upper surface of the lower molding element. The upper semiconductor chip is substantially orthogonal to the lower semiconductor chip.

In example embodiments, the connecting structure may include a first upper insulating layer in direct contact with the upper surface of the lower molding element, the upper surface of the lower semiconductor chip, and side and upper surfaces of the upper semiconductor chip. The connecting structure may further include a first redistribution pattern on the first upper insulating layer, and a second upper insulating layer on the first redistribution pattern. The first redistribution pattern may include first contact plugs in direct contact with upper surfaces of the conductive pillars, second contact plugs in direct contact with upper surfaces of the lower chip pads, and third contact plugs in direct contact with upper surfaces of the upper chip pads.

In example embodiments, sides of the second upper insulating layer may be farther away from the upper semiconductor chip than outermost sides of the first redistribution pattern.

In example embodiments, the sides of the second upper insulating layer may be vertically aligned with sides of the first upper insulating layer.

In example embodiments, the connecting structure may further include a second redistribution pattern on the second upper insulating layer, and a third insulating layer on the second redistribution pattern. The second redistribution pattern may include fourth contact plugs in direct contact with an upper surface of the first redistribution pattern.

In example embodiments, sides of the third upper insulating pattern may be farther away from the semiconductor chip than outermost sides of the second redistribution pattern, and vertically aligned with the sides of the second upper insulating layer.

In example embodiments, some of the lower chip pads may be electrically connected to corresponding upper chip pads, and the second redistribution pattern may be configured to supply a same signal to the some of the lower chip pads and the corresponding upper chip pads.

In example embodiments, the semiconductor package may further include external terminals, and each of the external terminals may be in direct contact with a lower surface of one of the conductive pillars.

In example embodiments, a vertical height of the upper semiconductor chip may be smaller than a vertical height of the lower semiconductor chip.

In example embodiments, the vertical height of the lower semiconductor chip may be the same as a vertical height of the lower molding element.

In example embodiments, the semiconductor package may further include an adhesive layer between the lower semiconductor chip and the upper semiconductor chip. The adhesive layer may be in direct contact with the upper surface of the lower semiconductor chip and a lower surface of the upper semiconductor chip.

In example embodiments, the adhesive layer may extend between the upper semiconductor chip and the lower molding element.

In accordance with example embodiments of inventive concepts, a semiconductor package includes: a lower semiconductor chip including: lower chip pads disposed on an upper surface thereof, the lower chip pads being close to two opposite sides of the lower semiconductor chip; a lower molding element surrounding sides of the lower semiconductor chip; conductive pillars penetrating the lower molding element along edges of the lower molding element; external terminals in direct contact one-to-one with lower surfaces of the conductive pillars; an upper semiconductor chip on the upper surface of the lower semiconductor chip, the upper semiconductor chip including upper chip pads on an upper surface thereof, the upper semiconductor chip not covering the lower chip pads; a connecting structure on the lower molding element and the upper semiconductor chip, the connecting structure including sides that are vertically aligned with sides of the lower molding element, the connecting structure electrically connecting each of the lower chip pads and the upper chip pads to corresponding ones of the external terminals through corresponding ones of the conductive pillars; and an upper molding element on an upper surface of the connecting structure, the upper molding element including sides that are vertically aligned with sides of the connecting structure.

In example embodiments, a coefficient of the thermal expansion of the lower molding element may be smaller than a coefficient of the thermal expansion of the upper molding element.

In example embodiments, the lower molding element may be harder than the upper molding element.

In accordance with example embodiments of inventive concepts, a semiconductor package includes: a lower semiconductor chip including a plurality of lower chip pads on two opposite ends of an upper surface, and a plurality of sides; a lower molding element surrounding the plurality of sides of the lower semiconductor chip and exposing the upper surface of the lower semiconductor chip; an upper semiconductor chip orthogonally crossing over the upper surface of the semiconductor chip between the plurality of lower chip pads on opposite ends, the upper semiconductor chip including a plurality of upper chip pads on two portions of the upper semiconductor chip, the two portions of the upper semiconductor chip extending over the lower molding element from two sides of the plurality of sides of the lower semiconductor chip; a plurality of conductive pillars that are spaced apart from the lower semiconductor chip and extend through the lower molding element; and a connecting structure that electrically connects upper surfaces of the plurality of lower chip pads and upper surfaces of the plurality of upper chip pads to upper surfaces of the plurality of conductive pillars.

In example embodiments, a plurality of external terminals may be electrically connected one-to-one to bottom surfaces of the plurality of conductive pillars.

In example embodiments, the connecting structure may include a first insulating layer on the molding layer, the two opposite ends of the lower semiconductor chip, and the upper semiconductor chip. The first insulating layer may define first upper via holes that expose the upper surfaces of the plurality of conductive pillars, second upper via holes that expose the upper surfaces of the plurality of lower chip pads, and third upper via holes that expose the upper surfaces of the plurality of upper chip pads. The connecting structure may include a first redistribution pattern on the first insulating layer.

In example embodiments, the connecting structure may further include a second insulating layer on the first redistribution pattern. Sides of the second insulating layer may be farther away from the upper semiconductor chip than outermost sides of the first redistribution pattern.

In example embodiments, an upper molding element may be on the upper semiconductor chip and the lower molding element. A coefficient of the thermal expansion of the lower molding element may be smaller than a coefficient of the thermal expansion of the upper molding element. A hardness of the lower molding element may be harder than a hardness of the upper molding element.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Example embodiments of inventive concepts will now be described more fully with reference to the accompanying drawings in which some example embodiments of inventive concepts are shown. Example embodiments of inventive concepts, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments of inventive concepts are provided so that this disclosure is thorough and complete and fully conveys the scope of example embodiments of inventive concepts to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

The terminology used herein to describe particular embodiments only and is not intended to be limiting of example embodiments of inventive concepts. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including,” if used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as is customary in the art to which example embodiments of inventive concepts belong. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

FIG. 1is a separated perspective view showing a semiconductor package in accordance with example embodiments of inventive concepts.FIG. 2Ais a cross-sectional view taken along line I-I′ inFIG. 1.FIG. 2Bis a cross-sectional view taken along line II-II′ inFIG. 1.FIG. 2Cis a cross-sectional view taken along line III-III′ inFIG. 1.

Referring toFIG. 1andFIGS. 2A to 2C, a semiconductor package in accordance with example embodiments of inventive concepts may include a lower semiconductor chip110, an upper semiconductor chip130, conductive pillars320, a lower molding element410, a connecting structure500, and an upper molding element610.

The semiconductor package may further include external terminals720disposed on lower surfaces of the conductive pillars320. Each of the external terminals720may be in direct contact with the lower surface of a corresponding conductive pillar320. The external terminals720may include a solder ball, a solder bump, a grid array, or a conductive tab.

The lower semiconductor chip110may include a memory device. For example, the lower semiconductor chip110may include a dynamic random access memory (DRAM) device; a flash memory device, or a variable resistance memory device, but example embodiments of inventive concepts are not limited thereto.

The lower semiconductor chip110may be disposed under the upper semiconductor chip130. The lower semiconductor chip110may be orthogonal to the upper semiconductor chip130. The lower semiconductor chip110may be disposed in the lower molding element410. The lower semiconductor chip110may be disposed in the middle of the lower molding element410. The level of an upper surface of the lower semiconductor chip110may be the same as that of an upper surface of the lower molding element410.

The vertical height of the lower semiconductor chip110may be the same as a vertical height of the lower molding element410. The lower semiconductor chip110may pass through the lower molding element410.

The lower semiconductor chip110may include lower chip pads112aand112b. The lower chip pads112aand112bmay be disposed on the upper surface of the lower semiconductor chip110. The lower chip pads112aand112bmay be disposed on the upper surface of the lower semiconductor chip110exposed by the upper semiconductor chip130. The lower chip pads112aand112bmay be arranged so they are not vertically overlapped by the upper semiconductor chip130.

The lower chip pads112aand112bmay include first lower chip pads112aand second lower chip pads112b. The second lower chip pads112band the first lower chip pads112amay be symmetrical. The first lower chip pads112aand the second lower chip pads112bmay be disposed at areas close to two opposite sides on the upper surface of the lower semiconductor chip110. For example, the first lower chip pads112amay be disposed close to a first side S1of the lower molding element410. The second lower chip pads112bmay be disposed close to a second side S2of the lower molding element410. The second side S2of the lower molding element410may be opposite the first side S1of the lower molding element410. A data signal, an address/control signal, and a power voltage signal may be supplied to the lower chip pads112aand112b. A different signal may be supplied to each of the lower chip pads112aand112b. For example, the power voltage signal may be supplied to one of the first lower chip pads112a. A first data signal may be supplied to another one of the first lower chip pads112a. A second data signal may be supplied to one of the second lower chip pads112b. The address/control signal may be supplied to another one of the second lower chip pads112b.

The lower chip pads112aand112bmay include a conductive material. For example, the lower chip pads112aand112bmay include a metal such as Au, Ag, Cu, Ni, or Al, but example embodiments of inventive concepts are not limited thereto.

The upper semiconductor chip130may include a memory device. For example, the upper semiconductor chip130may include a DRAM device, a flash memory device, or a variable resistance memory device, but example embodiments of inventive concepts are not limited thereto. The upper semiconductor chip130may be the same kind of chip as the lower semiconductor chip110.

In a semiconductor package in accordance with example embodiments of inventive concepts, both of the lower semiconductor chip110and the upper semiconductor chip130may include memory devices. However, example embodiments of inventive concepts are not limited thereto. For example, the lower semiconductor chip110or the upper semiconductor chip130may include a logic device. For example, the lower semiconductor chip110may include a logic device such as a microprocessor (MP).

The upper semiconductor chip130may be disposed on the upper surface of the lower semiconductor chip110. The upper semiconductor chip130may be orthogonally stacked on the upper surface of the lower semiconductor chip110. Some area of the upper semiconductor chip130may be arranged to not vertically overlap the lower semiconductor chip110. The area of the upper semiconductor chip130that may be arranged to not vertically overlap the lower semiconductor chip110may vertically overlap the lower molding element410.

The horizontal area of the upper semiconductor chip130may be the same as that of the lower semiconductor chip110. For example, the horizontal length and width of the upper semiconductor chip130may be the same as the horizontal length and width of the lower semiconductor chip110. The vertical height of the upper semiconductor chip130may be smaller than that of the lower semiconductor chip110. The vertical height of the upper semiconductor chip130may be smaller than that of the lower molding element410.

The upper semiconductor chip130may include upper chip pads132aand132b. The upper chip pads132aand132bmay be disposed on an upper surface of the upper semiconductor chip130. The upper chip pads132aand132bmay not vertically overlap the lower semiconductor chip110. The upper chip pads132aand132bmay be disposed at some areas on the upper surface of the upper semiconductor chip130which do not vertically overlap the lower semiconductor chip110. The upper chip pads132aand132bmay vertically overlap the lower molding element410.

The upper chip pads132aand132bmay include first upper chip pads132aand second upper chip pads132b. The second upper chip pads132band the first upper chip pads132amay be symmetrical. The first upper chip pads132aand the second upper chip pads132bmay be disposed at the areas close to two opposite sides on the upper surface of the upper semiconductor chip130. For example, the first upper chip pads132amay be disposed close to a third side S3of the lower molding element410. The second upper chip pads132bmay be disposed close to a fourth side S4of the lower molding element410. The fourth side S4of the lower molding element410may be opposite the third side S3of the lower molding element410.

A data signal, an address/control signal, and a power voltage signal may be supplied to the upper chip pads132aand132b. A different signal may be supplied to each of the upper chip pads132aand132b. For example, the power voltage signal may be supplied to one of the first upper chip pads132a. A third data signal may be supplied to another one of the first upper chip pads132a. A fourth data signal may be supplied to one of the second upper chip pads132b. The address/control signal may be supplied to another one of the second upper chip pads132b.

The upper chip pads132aand132bmay include a conductive material. For example, the upper chip pads132aand132bmay include a metal such as Au, Ag, Cu, Ni, or Al, but example embodiments of inventive concepts are not limited thereto. The upper chip pads132aand132bmay include the same material as the lower chip pads112aand112b.

In accordance with the embodiment of inventive concepts, the semiconductor package may further include an adhesive layer210disposed between the lower semiconductor chip110and the upper semiconductor chip130. The adhesive layer210may be in direct contact with the upper surface of the lower semiconductor chip110and a lower surface of the upper semiconductor chip130. The upper semiconductor chip130may be attached to the upper surface of the lower semiconductor chip110by the adhesive layer210.

The adhesive layer210may cover the entire lower surface of the upper semiconductor chip130. For example, sides of the adhesive layer210may be vertically aligned with sides of the upper semiconductor chip130. The adhesive layer210may have the same shape as the lower surface of the upper semiconductor chip130. The adhesive layer210may extend between the lower molding element410and the upper semiconductor chip130. The adhesive layer210may be orthogonal to the lower semiconductor chip110.

The adhesive layer210may include an epoxy resin. For example, the adhesive layer210may include a die attach film (DAF).

The conductive pillars320may pass through the lower molding element410. The conductive pillars320may surround the lower semiconductor chip110. The conductive pillars320may be disposed at the outside of the lower semiconductor chip110and upper semiconductor chip130. For example, the conductive pillars320may be disposed along edges of the lower molding element410.

The level of lower surfaces of the conductive pillars320may be the same as that of a lower surface of the lower molding element410. The vertical height of the conductive pillars320may be the same as that of the lower molding element410. The level of upper surfaces of the conductive pillars320may be the same as that of the upper surface of the lower semiconductor chip110.

Sides of the conductive pillars320may be perpendicular to the upper surfaces of the conductive pillars320. The sides of the conductive pillars320may be parallel to sides of the lower semiconductor chip110. The sides of the conductive pillars320may be parallel to each other. The horizontal width at the lower surfaces of the conductive pillars320may be the same as the horizontal width at the upper surfaces of the conductive pillars320. For example, the conductive pillars320may have a cylindrical shape.

The conductive pillars320may include a conductive material. For example, the conductive pillars320may include a metal such as Au, Ag, Cu, Ni, or Al, but example embodiments of inventive concepts are not limited thereto.

The lower molding element410may include the first side S1, the second side S2, the third side S3, and the fourth side S4. The second side S2may be opposite the first side S1. The third side S3and the fourth side S4may be disposed between the first side S1and the second side S2. The third side S3may be perpendicular to the first side S1. The fourth side S4may be opposite the third side S3. The fourth side S4may be perpendicular to the second side S2.

The lower molding element410may cover the sides of the lower semiconductor chip110. The lower molding element410may cover the sides of the conductive pillars320. The lower molding element410may fill a space between the lower semiconductor chip110and the conductive pillars320. The lower molding element410may surround the sides of the lower semiconductor chip110and the sides of the conductive pillars320.

The level of the upper surface of the lower molding element410may be the same as that of the upper surface of the lower semiconductor chip110. The upper surface of the lower molding element410may be in direct contact with a lower surface of the adhesive layer210under the upper semiconductor chip130. The lower molding element410may be vertically overlapped by the upper chip pads132aand132b.

The lower molding element410may include a thermosetting material. For example, the lower molding element410may include an epoxy molding compound (EMC).

In accordance with the embodiment of inventive concepts, the semiconductor package may further include a lower insulating layer710disposed on the lower surface of the lower molding element410. The lower insulating layer710may reduce (and/or prevent) unintended electrical connection between the lower semiconductor chip110and the external terminals720. Each of the conductive pillars320may be electrically connected to a corresponding external terminal720by the lower insulating layer710. The lower insulating layer710may include a solder resist.

The lower insulating layer710may include lower via holes710h. The lower via holes710hmay expose the lower surfaces of the conductive pillars320. The horizontal width of the lower via holes710hmay be greater than that of the lower surfaces of the conductive pillars320. Each of the external terminals720may be in direct contact with a lower surface of a corresponding conductive pillar320through the lower via holes710h.

The connecting structure500may electrically connect each of the lower chip pads112aand112band upper chip pads132aand132bto a corresponding conductive pillar320. The lower semiconductor chip110and the upper semiconductor chip130may be rerouted by connecting structure500. Each of the lower chip pads112aand112band upper chip pads132aand132bmay be electrically connected to a corresponding external terminal720by the connecting structure500and conductive pillars320.

The connecting structure500may be disposed on the lower molding element410and the upper semiconductor chip130. The connecting structure500may cover the upper surfaces of the lower chip pads112aand112b, the upper surfaces of the upper chip pads132aand132b, and the upper surfaces of the conductive pillars320. The connecting structure500may include a first upper insulating layer510, a first redistribution pattern522, a second upper insulating layer530, a second redistribution pattern542, and a third upper insulating layer550.

The first upper insulating layer510may be in direct contact with the upper surface of the lower semiconductor chip110which is not vertically overlapped by the upper semiconductor chip130and the upper surface of the lower molding element410. The first upper insulating layer510may be in direct contact with the side and upper surfaces of the upper semiconductor chip130. Sides of the first upper insulating layer510may be vertically aligned with the sides of the lower molding element410.

The first upper insulating layer510may include first upper via holes510a, second upper via holes510b, and third upper via holes510c. The first upper via holes510amay be disposed on the upper surface of the lower molding element410. The first upper via holes510amay expose the upper surface of the conductive pillars320. The second upper via holes510bmay be disposed on the upper surface of the lower semiconductor chip110. The second upper via holes510bmay expose the upper surfaces of the lower chip pads112aand112b. The third upper via holes510cmay be disposed on the upper surface of the upper semiconductor chip130. The third upper via holes510cmay expose the upper surfaces of the upper chip pads132aand132b.

The horizontal width of the first upper via holes510amay be smaller than that of the upper surfaces of the conductive pillars320. The horizontal width of the second upper via holes510bmay be greater than that of the lower chip pads112aand112b. The horizontal width of the third upper via holes510cmay be greater than that of the upper chip pads132aand132b. The horizontal width of the second upper via holes510bmay be the same as that of the first upper via holes510a. The horizontal width of the third upper via holes510cmay be the same as that of the second upper via holes510b.

The first redistribution pattern522may reroute the lower chip pads112aand112band the upper chip pads132aand132b. The first redistribution pattern522may electrically connect at least one of the lower chip pads112aand112band upper chip pads132aand132bto a corresponding conductive pillar320. For example, some of the lower chip pads112aand112band some of the upper chip pads132aand132bmay be electrically connected to corresponding conductive pillars320by the first redistribution pattern522.

The first redistribution pattern522may be disposed on the first upper insulating layer510. The outermost sides of the first redistribution pattern522may be disposed more inside than the sides of the first upper insulating layer510. The first redistribution pattern522may include first contact plugs522a, second contact plugs522b, third contact plugs522c, and a first interconnection portion522r.

The first contact plugs522amay be disposed in the first upper via holes510aof the first upper insulating layer510. The first contact plugs522amay be in direct contact with the upper surfaces of the conductive pillars320.

The second contact plugs522bmay be disposed in the second upper via holes510bof the first upper insulating layer510. The second contact plugs522bmay be in direct contact with the upper surfaces of the lower chip pads112aand112b.

The third contact plugs522cmay be disposed in the third upper via holes510cof the first upper insulating layer510. The third contact plugs522cmay be in direct contact with the upper surfaces of the upper chip pads132aand132b.

The first interconnection portion522rmay reroute the lower chip pads112aand112bthrough the second contact plugs522b. The first interconnection portion522rmay reroute the upper chip pads132aand132bthrough the third contact plugs522c. The first interconnection portion522rmay selectively connect the first contact plugs522a, the second contact plugs522b, and the third contact plugs522c.

The first interconnection portion522rmay be disposed on the upper surface of the first upper insulating layer510. The first interconnection portion522rmay be in direct contact with upper surfaces of the first contact plugs522a, second contact plugs522b, and third contact plugs522c. The first interconnection portion522rmay include the same material as the first contact plugs522a, second contact plugs522b, and third contact plugs522c.

The second upper insulating layer530may be disposed on the first redistribution pattern522. The second upper insulating layer530may cover the side and upper surfaces of the first redistribution pattern522. Sides of the second upper insulating layer530may be disposed outer than the outermost sides of the first redistribution pattern522. The sides of the second upper insulating layer may be vertically aligned with the sides of the first upper insulating layer510.

The second upper insulating layer530may include fourth upper via holes530h. The fourth upper via holes530hmay be disposed on the upper surface of the first redistribution pattern522. The fourth upper via holes530hmay expose an upper surface of the first interconnection portion522rof the first redistribution pattern522.

The second redistribution pattern542may electrically connect the lower chip pads112aand112band the upper chip pads132aand132bwhich are not electrically connected to corresponding conductive pillars320by the first redistribution pattern522, to the corresponding conductive pillars320. The second redistribution pattern542may electrically connect some of the lower chip pads112aand112bto the upper chip pads132aand132bto which the same signal as the signal supplied to corresponding lower chip pads112aand112bis supplied. Some of the first redistribution pattern522may be connected by the second redistribution pattern542. For example, one of the lower chip pads112aand112bto which a power voltage signal is supplied, may be electrically connected to one of the upper chip pads132aand132bto which the power voltage signal is supplied, by the second redistribution pattern542.

The second redistribution pattern542may be disposed on the second upper insulating layer530. The outermost sides of the second redistribution pattern542may be disposed more inside than the sides of the second upper insulating layer530. The second redistribution pattern542may include fourth contact plugs542pand a second interconnection portion542r.

The fourth contact plugs542pmay be disposed in the fourth upper via holes530hof the second upper insulating layer530. The fourth contact plugs542pmay be in direct contact with the upper surface of the first interconnection portion522rof the first redistribution pattern522.

Some of the first redistribution pattern522may be connected by the second interconnection portion542rthrough the fourth contact plugs542p. The second interconnection portion542rmay be disposed on an upper surface of the second upper insulating layer530. The second interconnection portion542rmay be in direct contact with upper surfaces of the fourth contact plugs542p. The second interconnection portion542rmay include the same material as the fourth contact plugs542p.

The third upper insulating layer550may be disposed on the second redistribution pattern542. The third upper insulating layer550may cover side and upper surfaces of the second redistribution pattern542. Sides of the third upper insulating layer550may be disposed outer than the outermost sides of the second redistribution pattern542. The sides of the third upper insulating layer550may be vertically aligned with the sides of the second upper insulating layer530.

Sides of the connecting structure500may consist of the sides of the first upper insulating layer510, the sides of the second upper insulating layer530, and the sides of the third upper insulating layer550. The sides of the connecting structure500may be vertically aligned with the sides of the lower molding element410.

Although the connecting structure500may include the first redistribution pattern522and the second redistribution pattern542, example embodiments of inventive concepts are not limited thereto. However, the connecting structure500may include one or both of the redistribution patterns522and542. For example, in a semiconductor package in accordance with example embodiments of inventive concepts, the connecting structure500may include only the first upper insulating layer510, the first redistribution pattern522, and the second upper insulating layer530. In this case, the first redistribution pattern522may electrically connect all of the lower chip pads112aand112band upper chip pads132aand132bto corresponding conductive pillars320.

In a semiconductor package in accordance with example embodiments of inventive concepts, the lower chip pads112aand112band the upper chip pads132aand132bmay be rerouted by the connecting structure500. That is, in a semiconductor package in accordance with example embodiments of inventive concepts, the lower semiconductor chip110and the upper semiconductor chip130may be simultaneously rerouted by the connecting structure500.

In addition, in a semiconductor package in accordance with example embodiments of inventive concepts, the lower chip pads112aand112band the upper chip pads132aand132bmay be electrically connected to corresponding external terminals720by the conductive pillars320and the connecting structure500. That is, in a semiconductor package in accordance with example embodiments of inventive concepts, the lower semiconductor chip110and the upper semiconductor chip130may be electrically connected to the external terminals720, without any circuit board. Accordingly, in a semiconductor package in accordance with example embodiments of inventive concepts, the overall vertical height may decrease. Accordingly, a semiconductor package in accordance with example embodiments of inventive concepts may achieve high integration and/or small size.

In addition, in a semiconductor package in accordance with example embodiments of inventive concepts, the lower semiconductor chip110and the upper semiconductor chip130may be electrically connected to the external terminals720without a wire. That is, in a semiconductor package in accordance with example embodiments of inventive concepts, damage to the electrical connection between the lower semiconductor chip110and upper semiconductor chip130and the external terminals720by a subsequent process, may be reduced (and/or prevented). Accordingly, a semiconductor package in accordance with example embodiments of inventive concepts may improve reliability.

The upper molding element610may be disposed on the connecting structure500. The upper molding element610may be in direct contact with an upper surface of the connecting structure500. Sides of the upper molding element610may be vertically aligned with the sides of the connecting structure500. The sides of the upper molding element610may be vertically aligned with the sides of the lower molding element410.

The upper molding element610may include a thermosetting material. For example, the upper molding element610may include an epoxy molding compound (EMC). The upper molding element610may include the same material as the lower molding element410.

Here, in a semiconductor package in accordance with example embodiments of inventive concepts, the upper semiconductor chip130and the connecting structure500may be supported by the lower molding element410. Accordingly, in a semiconductor package in accordance with example embodiments of inventive concepts, the lower molding element410may be harder than the upper molding element610.

In addition, in a semiconductor package in accordance with example embodiments of inventive concepts, if the lower molding element410is deformed, the whole structure may become unstable. Accordingly, in a semiconductor package in accordance with example embodiments of inventive concepts, the thermal expansion rate of the lower molding element410may be smaller than that of the upper molding element610.

FIGS. 3A to 3Care cross-sectional views showing a semiconductor package in accordance with example embodiments of inventive concepts.

Referring toFIGS. 3A to 3C, the semiconductor package in accordance with example embodiments of inventive concepts may include a lower semiconductor chip110, an upper semiconductor chip130disposed on the lower semiconductor chip110, a lower molding element410covering sides of the lower semiconductor chip110, conductive pillars320passing through the lower molding element410, a connecting structure500disposed on the lower molding element410and upper semiconductor chip130, an upper molding element610disposed on the connecting structure500, and external terminals720disposed on lower surfaces of the conductive pillars320. The lower semiconductor chip110may include lower chip pads112aand112bexposed by the upper semiconductor chip130. The upper semiconductor chip130may include upper chip pads132aand132bwhich do not vertically overlap the lower semiconductor chip110. The upper semiconductor chip130may be orthogonal to the lower semiconductor chip110.

The semiconductor package in accordance with example embodiments of inventive concepts may further include an adhesive layer210disposed between the lower semiconductor chip110and the upper semiconductor chip130, and a lower insulating layer710disposed on a lower surface of the lower molding element410. The lower insulating layer710may include lower via holes710hdisposed on the lower surfaces of the conductive pillars320.

The connecting structure500may include a first upper insulating layer510, a first redistribution pattern522disposed on the first upper insulating layer510, a second upper insulating layer530disposed on the first redistribution pattern522, a second redistribution pattern542disposed on the second upper insulating layer530, and a third upper insulating layer550adisposed on the second redistribution pattern542.

The first upper insulating layer510may include first upper via holes510adisposed on an upper surface of the lower molding element410, second upper via holes510bdisposed on an upper surface of the lower semiconductor chip110, and third upper via holes510cdisposed on an upper surface of the upper semiconductor chip130.

The first redistribution pattern522may include first contact plugs522ain direct contact with the conductive pillars320, second contact plugs522bin direct contact with the lower chip pads112aand112b, third contact plugs522cin direct contact with the upper chip pads132aand132b, and a first interconnection portion522r. The second upper insulating layer530may include fourth upper via holes530hdisposed on an upper surface of the first interconnection portion522r. The second redistribution pattern542may include fourth contact plugs542pin direct contact with the first interconnection portion522rand a second interconnection portion542r.

The level of the upper surface of the lower semiconductor chip110may be the same as that of the upper surface of the lower molding element410. The vertical height of the lower semiconductor chip110may be smaller than that of the lower molding element410. The lower molding element410may cover side and lower surfaces of the lower semiconductor chip110. The vertical height of the lower semiconductor chip110may be the same as that of the upper semiconductor chip130.

FIGS. 4A to 4Care cross-sectional views showing a semiconductor package in accordance with example embodiments of inventive concepts.

Referring toFIGS. 4A to 4C, the semiconductor package in accordance with example embodiments of inventive concepts may include a lower semiconductor chip110having lower chip pads112aand112bdisposed at areas of an upper surface thereof close to two opposite sides, a lower molding element410covering sides of the lower semiconductor chip110, an upper semiconductor chip130which has upper chip pads132aand132bdisposed at areas of an upper surface thereof close to two opposite sides and is orthogonally attached to the upper surface of the lower semiconductor chip110by an adhesive layer210, a connecting structure500disposed on the upper semiconductor chip130and redistribution the lower chip pads112aand112band the upper chip pads132aand132b, conductive pillars320passing through the lower molding element410and electrically connecting the connecting structure500to external terminals720, and an upper molding element610disposed on the connecting structure500. The semiconductor package in accordance with example embodiments of inventive concepts may further include a lower insulating layer710disposed on a lower surface of the lower molding element410.

The connecting structure500may include first and second redistribution patterns522and542which connect each of the lower chip pads112aand112band upper chip pads132aand132bto a corresponding conductive pillar320, and first to third upper insulating layers510,530, and550surrounding the first redistribution pattern522and the second redistribution pattern542.

The level of the upper surface of the lower semiconductor chip110may be the same as that of an upper surface of the lower molding element410. The vertical height of the lower semiconductor chip110may be the same as that of the upper semiconductor chip130. The level of a lower surface of the lower semiconductor chip110may be the same as that of the lower surface of the lower molding element410. The vertical height of the lower molding element410may be the same as that of the upper semiconductor chip130. The vertical height of the conductive pillars320may be the same as that of the upper semiconductor chip130.

FIGS. 5A to 5Care cross-sectional views showing a semiconductor package in accordance with example embodiments of inventive concepts.

Referring toFIGS. 5A to 5C, the semiconductor package in accordance with example embodiments of inventive concepts may include a lower molding element410, a lower semiconductor chip110passing through a central area of the lower molding element410, conductive pillars320passing through an edge area of the lower molding element410, an upper semiconductor chip130orthogonally stacked on the lower semiconductor chip110, a connecting structure500covering the lower molding element410and the upper semiconductor chip130, and an upper molding element610disposed on the connecting structure500. The semiconductor package in accordance with the embodiment of inventive concepts may further include a lower insulating layer710disposed on a lower surface of the lower molding element410, and external terminals720.

The connecting structure500may include a first upper insulating layer510covering side and upper surfaces of the upper semiconductor chip130and an upper surface of the lower molding element410, lower chip pads112aand112b, upper chip pads132aand132b, and a first redistribution pattern522in direct contact with the conductive pillars320, a second upper insulating layer520covering the first redistribution pattern522, a second redistribution pattern542in direct contact with the first redistribution pattern522, and a third upper insulating layer550covering the second redistribution pattern542.

The horizontal width at lower surfaces of the conductive pillars320may be greater than that at upper surfaces of the conductive pillars320. The horizontal width of the conductive pillars320may become small from the lower surface of the lower molding element410toward the upper surface of the lower molding element410. Sides of the conductive pillars320may be tilted toward the center of the conductive pillars320. For example, the conductive pillars320may be a circular truncated cone shape. The vertical cross-section of the conductive pillars320may be a trapezoidal shape.

FIGS. 6A to 6Care cross-sectional views showing a semiconductor package in accordance with example embodiments of inventive concepts.

Referring toFIGS. 6A to 6C, the semiconductor package in accordance with example embodiments of inventive concepts may include a lower package P1, an upper package P2disposed on an upper surface of the lower package P1, and package connecting elements740electrically connecting the upper package P2to the lower package P1.

The lower package P1may include a lower semiconductor chip110, an upper semiconductor chip130, conductive pillars320, a lower molding element410, a connecting structure500, and an upper molding element610. The connecting structure500may include a first upper insulating layer510, a first redistribution pattern522, a second upper insulating layer530, a second redistribution pattern542, and a third upper insulating layer550.

The third upper insulating layer550of the connecting structure500may include first package via holes550hdisposed on an upper surface of the lower molding element410. The upper molding element610may include second package via holes610hdisposed on the upper surface of the lower molding element410. The first package via holes550hand the second package via holes610hmay be disposed on upper surfaces of the conductive pillars320.

Sidewalls of the first package via holes550hmay continue to sidewalls of the second package via holes610h. For example, the shape of the first package via holes550hon an upper surface of the third upper insulating layer550may be the same as that of the second package via holes610hon a lower surface of the upper molding element610. The horizontal width of the first package via holes550hon the upper surface of the third upper insulating layer550may be the same as that of the second package via holes610hon the lower surface of the upper molding element610.

The upper package P2may include a lower semiconductor chip150, an upper semiconductor chip170, conductive pillars360, a lower molding element430, a connecting structure800, and an upper molding element630. The connecting structure800may include a fourth upper insulating layer810, a third redistribution pattern822, a fifth upper insulating layer830, a fourth redistribution pattern842, and a sixth upper insulating layer850. The upper package P2may be the same kind of package as the lower package P1. For example, the connecting structure800of the upper package P2may be the same as the connecting structure500of the lower package P1.

The package connecting elements740may be disposed on a lower surface of the lower molding element430of the upper package P2. The package connecting elements740may be in direct contact with lower surfaces of the conductive pillars360of the upper package P2. The package connecting elements740may be disposed in the first package via holes550hand the second package via holes610h. The package connecting elements740may be in direct contact with an upper surface of the second redistribution pattern542of the lower package P1. The conductive pillars360of the upper package P2may be electrically connected to the connecting structure500of the lower package P1by the package connecting elements740. The connecting structure800of the upper package P2may be electrically connected to the conductive pillars320of the lower package P1by the package connecting elements740.

For example, the package connecting elements740may include a solder ball, a solder bump, a grid array, or a conductive tap. The package connecting elements740may include the same material as external terminals720.

The semiconductor package in accordance with example embodiments of inventive concepts may further include the external terminals (720) disposed on lower surfaces of the conductive pillars320of the lower package P1. Lower chip pads152aand152band upper chip pads172aand172bof the upper package P2may be electrically connected to corresponding external terminals720through the conductive pillars320of the lower package P1, the package connecting elements740, the conductive pillars360of the upper package P2, and the connecting structure800of the upper package P2, respectively.

FIGS. 7A to 28A,7B to28B, and7C to28C are cross-sectional views sequentially describing a method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts.

A method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts will be described with reference toFIGS. 1,2A to2C,7A to28A,7B to28B, and7C to28C. First, referring toFIGS. 7A to 7C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of providing a first carrier901.

The process of providing the first carrier901may include a process of forming a first carrier adhesive layer250on an upper surface of the first carrier901.

Referring toFIGS. 8A to 8C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of arranging conductive structure300on the upper surface of the first carrier901.

The process of arranging the conductive structure300on the upper surface of the first carrier901may include a process of aligning the conductive structure300on an upper surface of the first carrier adhesive layer250, and a process of attaching the conductive structure300to the upper surface of the first carrier adhesive layer250. The conductive structure300may include conductive pillars320and a pillar interconnection portion340.

The process of aligning the conductive structure300on the upper surface of the first carrier adhesive layer250may include a process of aligning the conductive structure300on the upper surface of the first carrier adhesive layer250so that lower surfaces of the conductive pillars320of the conductive structure300face the upper surface of the first carrier adhesive layer250.

The process of attaching the conductive structure300to the upper surface of the first carrier adhesive layer250may include a process of attaching the lower surfaces of the conductive pillars320of the conductive structures300to the upper surface of the first carrier adhesive layer250.

Referring toFIGS. 9A to 9C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of arranging the lower semiconductor chip110between the conductive pillars320of the conductive structure300. The lower semiconductor chip110may be stay apart from the pillar interconnection portion340of the conductive structure300.

The process of arranging the lower semiconductor chip110may include a process of providing the lower semiconductor chip110, a process of aligning the lower semiconductor chip110on the upper surface of the first carrier adhesive layer250, and a process of attaching the lower semiconductor chip110to the upper surface of the first carrier adhesive layer250. The lower semiconductor chip110may include lower chip pads112aand112b. The lower chip pads112aand112bmay be disposed on areas of an active surface110A close to two opposite sides.

The process of aligning the lower semiconductor chip110on the upper surface of the first carrier adhesive layer250may include a process of aligning the lower semiconductor chip110on the upper surface of the first carrier adhesive layer250so that the active surface110A of the lower semiconductor chip110faces the upper surface of the first carrier adhesive layer250, and a process of aligning the lower semiconductor chip110between the conductive pillars320of the conductive structure300so that the lower semiconductor chip110stays apart from the pillar interconnection portion340of the conductive structure300.

The process of attaching the lower semiconductor chip110to the upper surface of the first carrier adhesive layer250may include a process of attaching the active surface110A of the lower semiconductor chip110to the upper surface of the first carrier adhesive layer250.

The vertical height of the lower semiconductor chip110may be greater than that of the conductive structures300. For example, the lower semiconductor chip110may be a unit semiconductor chip on which a backside grinding process or a backside etch back process has not been performed.

Referring toFIGS. 10A to 10C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a lower molding element410on the upper surface of the first carrier901.

The process of forming the lower molding element410on the upper surface of the first carrier901may include a process of surrounding the conductive structures300and the lower semiconductor chip110with the lower molding element410. The process of surrounding the conductive structures300and the lower semiconductor chip110with the lower molding element410may include a process of covering side and upper surfaces of the conductive structures300with the lower molding element410. The process of surrounding the conductive structures300and the lower semiconductor chip110with the lower molding element410may include a process of covering side and upper surfaces of the lower semiconductor chip110with the lower molding element410. The vertical height of the lower molding element410may be greater than that of the lower semiconductor chip110.

Referring toFIGS. 11A to 11C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of rotating the lower molding element410so that the active surface110A of the lower semiconductor chip110becomes an upper surface of the lower semiconductor chip110.

The process of rotating the lower molding element410may include a process of rotating the lower semiconductor chip110, the lower molding element410, and the conductive structures300up and down, and a process of removing the first carrier901and the first carrier adhesive layer250. Accordingly the active surface110A of the lower semiconductor chip110may be exposed out of the lower molding element410. In addition, upper surfaces of the conductive pillars320of the conductive structures300may be exposed out of the lower molding element410.

Referring toFIGS. 12A to 12C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of orthogonally stacking the upper semiconductor chip130on the upper surface of the lower semiconductor chip110.

The process of orthogonally stacking the upper semiconductor chip130on the upper surface of the lower semiconductor chip110may include a process of providing the upper semiconductor chip130, a process of attaching the adhesive layer210to a lower surface of the upper semiconductor chip130, a process of aligning the upper semiconductor chip130to be orthogonal to the lower semiconductor chip110on the upper surface of the lower semiconductor chip110, and a process of attaching the upper semiconductor chip130to the upper surface of the lower semiconductor chip110using the adhesive layer210. Accordingly, the lower chip pads112aand112bof the lower semiconductor chip110may not be vertically overlapped by the upper semiconductor chip130.

The upper semiconductor chip130may include upper chip pads132aand132b. The upper chip pads132aand132bmay be disposed on an upper surface of the upper semiconductor chip130. The upper chip pads132aand132bmay be disposed on areas of the upper surface close to two opposite sides. The upper chip pads132aand132bmay not vertically overlap the lower semiconductor chip110.

The vertical height of the upper semiconductor chip130may be smaller than that of the lower semiconductor chip110. For example, the upper semiconductor chip130may be a unit semiconductor chip on which the backside grinding process has been performed.

Referring toFIGS. 13A to 13C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a first upper insulating layer510on the lower molding element410and the upper semiconductor chip130.

The process of forming the first upper insulating layer510on the lower molding element410and the upper semiconductor chip130may include a process of covering upper surfaces of the lower molding element410and lower semiconductor chip110which are not overlapped by the upper semiconductor chip130, with the first upper insulating layer510. The process of forming the first upper insulating layer510on the lower molding element410and the upper semiconductor chip130may include a process of covering side and upper surfaces of the upper semiconductor chip130with the first upper insulating layer510.

Referring toFIGS. 14A to 14C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming first upper via holes510a, second upper via holes510b, and third upper via holes510cin the first upper insulating layer510.

The process of forming the first upper via holes510a, the second upper via holes510b, and the third upper via holes510cin the first upper insulating layer510may include a process of forming the first upper via holes510ain the first upper insulating layer510disposed on the upper surfaces of the conductive pillars320, a process of forming the second upper via holes510bin the first upper insulating layer510disposed on upper surfaces of the lower chip pads112aand112b, and a process of forming the third upper via holes510cin the first upper insulating layer510disposed on upper surfaces of the upper chip pads132aand132b. The process of forming the first upper via holes510a, the second upper via holes510b, and the third upper via holes510cmay be simultaneously performed.

Referring toFIGS. 15A to 15C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a first redistribution layer520on the first upper insulating layer510.

The process of forming the first redistribution layer520on the first upper insulating layer510may include a process of filling the first upper via holes510a, the second upper via holes510b, and the third upper via holes510cwith the first redistribution layer520. The first redistribution layer520may be in direct contact with the upper surfaces of the conductive pillars320through the first upper via holes510a. The first redistribution layer520may be in direct contact with the upper surfaces of the lower chip pads112aand112bthrough the second upper via holes510b. The first redistribution layer520may be in direct contact with the upper surfaces of the upper chip pads132aand132bthrough the third upper via holes510c.

Referring toFIGS. 16A to 16C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a first redistribution pattern522on the first upper insulating layer510.

The process of forming the first redistribution pattern522on the first upper insulating layer510may include a process of patterning the first redistribution layer520. The first redistribution pattern522may include first contact plugs522adisposed in the first upper via holes510a, second contact plugs522bdisposed in the second upper via holes510b, third contact plugs522cdisposed in third upper via holes510c, and a first interconnection portion522rdisposed on an upper surface of the first upper insulating layer510. The first interconnection portion522rmay selectively connect the first contact plugs522a, the second contact plugs522b, and the third contact plugs522c.

Referring toFIGS. 17A to 17C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a second upper insulating layer530on the first redistribution pattern522.

The process of forming the second upper insulating layer530on the first redistribution pattern522may include a process of covering side and upper surfaces of the first redistribution pattern522with the second upper insulating layer530.

Referring toFIGS. 18A to 18C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming fourth upper via holes530hin the second upper insulating layer530.

The process of forming the fourth upper via holes530hin the second upper insulating layer530may include a process of forming the fourth upper via holes530hin the second upper insulating layer530disposed on an upper surface of the first interconnection portion522r.

Referring toFIGS. 19A to 19C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a second redistribution layer540on the second upper insulating layer530.

The process of forming the second redistribution layer540on the second upper insulating layer530may include a process of filling the fourth upper via holes530hwith the second redistribution layer540. The second redistribution layer540may be in direct contact with the upper surface of the first interconnection portion522rof the first redistribution pattern522through the fourth upper via holes530h.

Referring toFIGS. 20A to 20C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a second redistribution pattern542on the second upper insulating layer530.

The process of forming the second redistribution pattern542on the second upper insulating layer530may include a process of patterning the second redistribution layer540. The second redistribution pattern542may include fourth contact plugs542pdisposed in the fourth upper via holes530hand a second interconnection portion542rdisposed on an upper surface of the second upper insulating layer530. The second interconnection portion542rmay selectively connect the fourth contact plugs542p.

Referring toFIGS. 21A to 21C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a third upper insulating layer550on the second redistribution pattern542.

The process of forming the third upper insulating layer550on the second redistribution pattern542may include a process of covering side and upper surfaces of the second redistribution pattern542with the third upper insulating layer550. The first upper insulating layer510, the first redistribution pattern522, the second upper insulating layer530, the second redistribution pattern542, and the third upper insulating layer550may configure a connecting structure500.

Referring toFIGS. 22A to 22C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming an upper molding element610on the third upper insulating layer550of the connecting structure500.

Referring toFIGS. 23A to 23C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of arranging a second carrier902on an upper surface of the upper molding element610.

The process of arranging the second carrier902on the upper surface of the upper molding element610may include a process of providing the second carrier902, a process of forming a second carrier adhesive layer270on a lower surface of the second carrier902, and a process of attaching the second carrier902to the upper surface of the upper molding element610using the second carrier adhesive layer270.

Referring toFIGS. 24A to 24C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of removing the pillar connection part340of the conductive structure300.

The process of removing the pillar connection part340of the conductive structure300may include a process of making the vertical height of the lower molding element410the same as that of the lower semiconductor chip110. The process of removing the pillar connection part340of the conductive structure300may include a process of making the vertical height of the conductive pillars320the same as that of the lower semiconductor chip110. The process of removing the pillar connection part340of the conductive structure300may include a process of grinding or etching back lower surfaces of the lower semiconductor chip110and the lower molding element410.

Referring toFIGS. 25A to 25C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a lower insulating layer710on the lower surfaces of the conductive pillars320, the lower molding element410, and the lower semiconductor chip110.

The process of forming the lower insulating layer710on the lower surfaces of the lower molding element410may include a process of covering the lower surfaces of the conductive pillars320, the lower molding element410, and the lower semiconductor chip110with the lower insulating layer710.

Referring toFIGS. 26A to 26C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming lower via holes710hin the lower insulating layer710.

The process of forming the lower via holes710hin the lower insulating layer710may include a process of forming the lower via holes710hin the lower insulating layer710disposed on the lower surfaces of the conductive pillars320. The horizontal width of the lower via holes710hmay be greater than that of the lower surfaces of the conductive pillars320.

Referring toFIGS. 27A to 27C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming external terminals720on the lower surfaces of the conductive pillars320.

The process of forming the external terminals720on the lower surfaces of the conductive pillars320may include a process of forming external terminals720in the lower via holes710hof the lower insulating layer710.

Referring toFIGS. 28A to 28C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of removing the second carrier902and the second carrier adhesive layer270.

Referring toFIGS. 1, and2A to2C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a unit package.

The process of forming the unit package may include a process of cutting the lower molding element410, the connecting structure500, and the upper molding element610. The process of cutting the lower molding element410, the connecting structure500, and the upper molding element610may include a sawing process.

FIGS. 5A to 5C,29A to35A,29B to35B, and29C to35C are cross-sectional views sequentially describing a method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts.

The method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts will be described with reference toFIGS. 5A to 5C,29A to35A,29B to35B, and29C to35C. First, referring toFIGS. 29A to 29C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of arranging a lower semiconductor chip110on an upper surface of a first carrier adhesive layer250of a first carrier901and a process of forming a lower molding element410covering side and upper surfaces of the lower semiconductor chip110on the upper surface of the first carrier adhesive layer250.

The process of arranging the lower semiconductor chip110on the upper surface of the first carrier adhesive layer250may include a process of providing the lower semiconductor chip110having lower chip pads112aand112b, a process of aligning the lower semiconductor chip110on the upper surface of the first carrier adhesive layer250so that an active surface110A in which the lower chip pads112aand112bare disposed faces the first carrier adhesive layer250, and a process of attaching the active surface110A of the lower semiconductor chip110to the upper surface of the first carrier adhesive layer250.

Referring toFIG. 30A to 30C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of orthogonally stacking an upper semiconductor chip130on the active surface110A of the lower semiconductor chip110, and a process of forming a connecting structure500on the lower molding element410and the upper semiconductor chip130.

The process of orthogonally stacking the upper semiconductor chip130on the active surface110A of the lower semiconductor chip110may include a process of rotating the lower semiconductor chip110and the lower molding element410up and down, removing the first carrier901and the first carrier adhesive layer250, a process of providing the upper semiconductor chip130having upper chip pads132aand132bon an upper surface thereof, forming an adhesive layer210on a lower surface of the upper semiconductor chip130, a process of aligning the upper semiconductor chip130so that the adhesive layer210faces the active surface110A of the lower semiconductor chip110, a process of aligning the upper semiconductor chip130to be orthogonal to the lower semiconductor chip110, and a process of attaching the upper semiconductor chip130to the active surface110A of the lower semiconductor chip110using the adhesive layer210.

The process of forming the connecting structure500may include a process of forming a first upper insulating layer510on the lower molding element410and the upper semiconductor chip130, a process of forming a first redistribution pattern522on the first upper insulating layer510, a process of forming a second upper insulating layer530on the first redistribution pattern522, a process of forming a second redistribution pattern542on the second upper insulating layer530, and a process of forming a third upper insulating layer550on the second redistribution pattern542.

The process of forming the first upper insulating layer510on the lower molding element410and the upper semiconductor chip130may include a process of forming the first upper insulating layer510having first upper via holes510a, second upper via holes510b, and third upper via holes510c. The first upper via holes510amay be disposed on an upper surface of the lower molding element410which is not overlapped by the upper semiconductor chip130. The first upper via holes510amay be disposed on upper surfaces of conductive pillars320formed in a subsequent process. The second upper via holes510bmay be disposed on upper surfaces of the lower chip pads112aand112b. The third upper via holes510cmay be disposed on upper surfaces of the upper chip pads132aand132b.

The process of forming the first redistribution pattern522on the first upper insulating layer510may include a process of forming the first redistribution pattern522having first contact plugs522a, second contact plugs522b, and third contact plugs522c. The first contact plugs522amay be disposed in the first upper via holes510a. The second contact plugs522bmay be disposed in the second upper via holes510b. The third contact plugs522cmay be disposed in the third upper via holes510c.

Referring toFIGS. 31A to 31C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming an upper molding element610on the connecting structure500, a process of forming a second carrier adhesive layer270and a second carrier902on the upper molding element610, and a process of etching lower surfaces of the lower molding element410and lower semiconductor chip110.

The process of etching the lower surfaces of the lower molding element410and the lower semiconductor chip110may include a process of grinding or etching back the lower surfaces of the lower molding element410and the lower semiconductor chip110. The process of etching the lower surfaces of the lower molding element410and the lower semiconductor chip110may include a process of making the vertical height of the lower molding element410the same as that of the lower semiconductor chip110.

Referring toFIGS. 32A to 32C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming pillar via holes410hin the lower molding element410.

The process of forming the pillar via holes410hin the lower molding element410may include a process of exposing lower surfaces of the first contact plugs522a. The horizontal width of the upper surface of the lower molding element410of the pillar via holes410hmay be greater than that of the first upper via holes510a.

The process of exposing the lower surface of the first contact plugs522amay include a process of etching the lower molding element410disposed under the first contact plugs522a. The process of etching the lower molding element410disposed under the first contact plugs522amay include a laser drilling process. The horizontal width of the lower surface of the lower molding element410of the pillar via holes410hmay be greater than that of the upper surface of the lower molding element410of the pillar via holes410h.

Referring toFIGS. 33A to 33C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a conductive layer380on the lower surfaces of the lower molding element410and the lower semiconductor chip110.

The process of forming the conductive layer380on the lower surface of the lower molding element410and the lower surface of the lower semiconductor chip110may include a process of filling the pillar via holes410hwith the conductive layer380. The conductive layer380may be in direct contact with the lower surface of the first contact plugs522athrough the pillar via holes410h.

Referring toFIGS. 34A to 34C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming conductive pillars320in the pillar via holes410h.

The process of forming the conductive pillars320in the pillar via holes410hmay include a process of removing the conductive layer380disposed on the lower surface of the lower molding element410and the lower surface of the lower semiconductor chip110. The process of removing the conductive layer380disposed on the lower surface of the lower molding element410and the lower surface of the lower semiconductor chip110may include a process of planarizing a lower surface of the conductive layer380until the lower surface of the lower molding element410and the lower surface of the lower semiconductor chip110are exposed. The process of planarizing the lower surface of the conductive layer380may include a Chemical Mechanical Polishing (CMP) process.

Referring toFIGS. 35A to 35C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a lower insulating layer710on lower surfaces of the conductive pillars320, the lower molding element410, and the lower semiconductor chip110, a process of forming lower via holes710hexposing the lower surfaces of the conductive pillars320in the lower insulating layer710, and a process of forming external terminals720in direct contact with the lower surfaces of the conductive pillars320in the lower via holes710h.

Referring toFIGS. 5A to 5C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming a unit package by removing the second carrier902and the second carrier adhesive layer270, and by a sawing process.

FIGS. 6A to 6C,36A to36C, and37A to37C are cross-sectional views sequentially describing a method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts.

The method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts will be described with reference toFIGS. 6A to 6C,36A to36C, and37A to37C. First, referring toFIGS. 36A to 36C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of forming first package via holes550hand second package via holes610hin a lower package P1.

The process of forming the first package via holes550hand the second package via holes610hin the lower package P1may include a process of providing the lower package P1having a lower semiconductor chip110, an upper semiconductor chip130, conductive pillars320, a lower molding element410, a connecting structure500, an upper molding element610, and external terminals720, a process of forming the second package via holes610hin the upper molding element610of the lower package P1, and a process of forming the first package via holes550hin a third upper insulating layer550of the connecting structure500. The first package via holes550hand the second package via holes610hmay be disposed on upper surfaces of the conductive pillars320. The first package via holes550hand the second package via holes610hmay expose an upper surface of a second redistribution pattern542of the connecting structure500.

The process of forming the second package via holes610hin the upper molding element610may include a process of etching the upper molding element610disposed on the upper surfaces of the conductive pillars320. The process of forming the first package via holes550hon the third upper insulating layer550may include a process of etching the third upper insulating layer550disposed on the upper surfaces of the conductive pillars320

The process of etching the upper molding element610disposed on the upper surface of the conductive pillars320, and the process of etching the third upper insulating layer550disposed on the upper surfaces of the conductive pillars320may be performed in succession. The process of etching the upper molding element610disposed on the upper surfaces of the conductive pillars320, and the process of etching the third upper insulating layer550disposed on the upper surfaces of the conductive pillars320may include a laser-drilling process. Sidewalls of the first package via holes550hmay continue to sidewalls of the second package via holes610h.

Referring toFIGS. 37A to 37C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of aligning the upper package P2on an upper surface of the lower package P1.

The process of aligning the upper package P2on the upper surface of the lower package P1may include a process of providing the upper package P2having a lower semiconductor chip150, an upper semiconductor chip170, conductive pillars360, a lower molding element430, a connecting structure800, an upper molding element630, and package connecting elements740, and a process of aligning the upper package P2so that the package connecting elements740of the upper package P2are disposed on upper surfaces of the second package via holes610hof the lower package P1.

The process of providing the upper package P2may include a process of forming the package connecting elements740on lower surfaces of the conductive pillars360before forming the unit package.

Referring toFIGS. 6A to 6C, the method of fabricating a semiconductor package in accordance with example embodiments of inventive concepts may include a process of electrically connecting the package connecting elements740to the second redistribution pattern542of the connecting structure500of the lower package P1through the first package via holes550hand second package via holes610hof the lower package P1.

The process of electrical connecting the package connecting elements740to the second redistribution pattern542of the connecting structure500of the lower package P1may include a process of filling the first package via holes550hand second package via holes610hof the lower package P1with the package connecting elements740.

The process of filling the first package via holes550hand second package via holes610hof the lower package P1with the package connecting elements740may include a process of adjusting a space between the lower package P1and the upper package P2so that some of the package connecting elements740are inserted in the second package via holes610h, and a process of reflowing the package connecting elements740.

FIG. 38is a configuration diagram showing a memory module including a semiconductor package in accordance with example embodiments of inventive concepts.

Referring toFIG. 38, the memory module1100in accordance with example embodiments of inventive concepts may include a module substrate1100, semiconductor packages1120, and module contact terminals1130. The semiconductor packages1120may be the semiconductor packages in accordance with example embodiments of inventive concepts. Accordingly, the memory module1100may achieve high integration and small size. The module substrate1110may be a system board. The semiconductor packages1120may be arranged parallel to the module substrate1110. The semiconductor packages1120may be arranged in both sides of the module substrate1110. The module contact terminals1130may be formed in parallel in an edge of the module substrate1110. The module contact terminals1130may be electrically connected to the semiconductor packages1120.

FIG. 39is a configuration diagram showing a semiconductor module including a semiconductor package in accordance with example embodiments of inventive concepts.

Referring toFIG. 39, the semiconductor module2000may include a module substrate2100, memories2200, microprocessors2300, and input/output terminals2400. The memories2200and the microprocessors2300may be mounted on the module substrate2100. The memories2200may include semiconductor packages in accordance with example embodiments of inventive concepts. Accordingly, the semiconductor module2000may achieve high integration and small size. The semiconductor module2000may include a memory card or a card package.

FIG. 40is a configuration diagram showing a mobile system including a semiconductor package in accordance with example embodiments of inventive concepts.

Referring toFIG. 40, the mobile system3000may include a display unit3100, a body3200, and an external apparatus3300. The body3200may be a system board or a mother board including a printed circuit board (PCB). The body3200may include a microprocessor unit3210, a power supply3220, a function unit3230, and a display controller unit3240. The microprocessor unit3210, the power supply3220, the function unit3230, and the display controller unit3240may be mounted or installed on the body3200. The microprocessor unit3210may receive a voltage from the power supply3220to control the function unit3230and the display controller unit3240. The power supply3220may receive a constant voltage from an external power source (not shown), etc., divide the voltage into various levels, and supply those voltages to the microprocessor unit3210, the function unit3230, and the display controller unit3240. The function unit3230may perform various functions of the mobile systems3000. For example, the function unit3230may have several components which can perform functions of a mobile phone such as dialing, video output to the display unit3100through communication with an external apparatus3300, and sound output to a speaker, and if a camera is installed, the function unit3230may function as an image processor. The microprocessor unit3210and the function unit3230may include a semiconductor package in accordance with example embodiments of inventive concepts, in order to process various signals. Accordingly, the mobile system3000may achieve high integration and small size. The display unit3100may be located on a surface of the body3200. The display unit3100may be connected to the body3200. The display unit3100may display an image processed by the display controller unit3240of the body3200. The mobile system3000may be connected to a memory card, etc. in order to expand capacity. In this case, the function unit3230may include a memory card controller. The function unit3230may exchange signals with the external apparatus3300through a wired or wireless communication unit2400. In addition, the mobile system30002000may include a universal serial bus (USB) in order to expand functionality. In this case, the function unit3230may function as an interface controller.

FIG. 41is a configuration diagram showing a mobile apparatus including a semiconductor package in accordance with example embodiments of inventive concepts.

Referring toFIG. 41, the mobile apparatus4000may be a mobile wireless phone, or a tablet PC. The mobile apparatus4000may include a semiconductor package in accordance with example embodiments of inventive concepts. Accordingly, the mobile apparatus4000may achieve high integration and small size.

FIG. 42is a configuration diagram showing an electronic system including a semiconductor package in accordance with example embodiments of inventive concepts.

Referring toFIG. 42, the electronic system5000may include a semiconductor package in accordance with example embodiments of inventive concepts. The electronic system5000may be used to fabricate a mobile apparatus or a computer. For example, the electronic system5000may include a memory system5100, a microprocessor5200, a random access memory (RAM)5300, and a user interface5400performing data communication using a bus5500. The microprocessor5200may program and control the electronic system5000. The RAM5300may be used as an operation memory of the microprocessor5200. For example, the microprocessor5200or the RAM5300may include a semiconductor package in accordance with example embodiments of inventive concepts. Accordingly, the electronic system5000may achieve high integration and small size. The microprocessor5200, the RAM5300, and/or other components can be assembled in a single package. The user interface5400may be used to input data to, or output data from the electronic system5000. The memory system5100may store codes for operating the microprocessor5200, data processed by the microprocessor5200, or external input data. The memory system5100may include a controller and a memory.