System, device and method for comprehensive input/output interface between process or machine transducers and controlling device or system

Comprehensive universal configurable interface for electrical, electronic, and electromechanical control, sensing, and actuation. Circuit, apparatus, method, and signal set for interfacing an electrical or electronic component or a mechanical component generating or effecting an electrical or electronic signal to a control system or device. Comprehensive universal input/output interface system, circuit, and method for interfacing such components and control systems that send or receive analog or digital voltage and/or current inputs over a large range of voltages and/or current without hardware or software switches. Interface and method includes and needs only two terminals for the connection of sensor or actuator. Provides plurality of operation mode circuits to accomplish the following functions: digital input, digital output, analog input, analog output, and others. Supports either voltage or current input and output, and voltage and current capabilities over a broad dynamic range. Single physical package for user configuration into a broad set of applications.

FIELD OF THE INVENTION

This invention pertains generally to systems, circuits, methods, and signals for interfacing an electrical or electronic component or a mechanical component or process generating or effecting an electrical or electronic signal to a control system or device; and more particularly to a single comprehensive universal input/output interface system, circuit, method, and signal set for interfacing such components and control systems that send or receive analog or digital voltage and/or current inputs and/or outputs over large voltage ranges of voltages and/or currents.

BACKGROUND

In automated processes or machines the controlling device monitors various sensors within the controlled process, evaluates the differences between the actual process state and the control algorithm requirements, and then activates appropriate process actuators. Conventionally, every automated system requires an individual electronic interface between a controller and each of the sensors and actuators of the process or machine being controlled. The sensing and actuating tasks are complex.

The sensor and actuator portion of the interface and interfacing task is complex and extensive at least in part because of the wide variety of voltages and currents such sensors and actuators encounter and therefore encode, interface with, and/or respond to. This problem became apparent at least since the 1969 development of the first general-purpose control device, the programmable logic controller (PLC). Conventionally, manufacturer's solution to the problem has been a series of compromises that do not favor the system designer or user.

There are four basic signal types for purpose of convenient description and analysis, they are: (1) analog inputs, (2) analog outputs, (3) digital inputs, and (4) digital outputs. The number of possible signal types is further compounded to include such characteristics as whether the signal is an ac (alternating current) signal or a dc (direct current) signal, whether it expresses logic levels (typically within the range of ±15 volts) or power line levels, whether the signal is fast or slow, and many ranges for analog sensors and actuators. Realistically there is a need to handle or interface over fifty different signal types for existing sensing, actuating, and control applications.

More usually, a manufacturer address the problem by limiting their standard products, for example, they may produce and market a subset of the ten to twenty interface blocks representing the most common signal types. This makes it necessary for the user requiring an interface circuit to use external signal conditioners to fill in voids for the less common signal types for which individualized blocks are not readily available commercially. Typically these plug-in signal conditioning blocks handle from one to sixteen I/O points of a single signal type.

This approach is not only expensive for the manufacturers to produce, document, market, stock, inventory and sell even the ten to twenty or so common different interface block types, but the designers who use them must select the appropriate type, and the controlled system user must maintain an inventory of essential spares so that spares are available for each type. The requirement to spare and service each type increases costs at the user end as well but not having an available spare of the correct type may mean shutting down a machine or process until a spare or repair is available, perhaps idling an assembly line and sending workers home at considerable cost.

The requirements for so many different signal interface block types also increase the risk that the wrong type will be used or will be miswired. This creates risk for personal and property damage.

There is also a need for a comprehensive interface component or circuit that provides for multiple analog voltage inputs that are switch or software/firmware programmable to support a range of analog voltage inputs extending from the micro-volt levels of thermocouple devices to high-voltage power ranges such as 220 VAC or higher.

Thus, there is a need for a universal or comprehensive interface that can handle more than one signal type or condition, or, where one cannot be designed or cost-effectively sold, for a fewer number of such comprehensive interface blocks that can handle classes or a plurality of signal types. There is also a need to provide such interfaces that reduce the risk of harm caused by miswiring. There is also a need for an interface that permits simultaneous sensing inputs and outputs.

There is also a need for a comprehensive interface component or circuit that provides combined inputs and outputs supporting these features rather than providing input and output in separate or piecemeal manner.

Thus, it is desirable to provide a comprehensive means to overcome the multiple deficiencies in order to simplify the design, manufacturing, and/or control of automated processes and machines.

SUMMARY

Comprehensive universal configurable interface for electrical, electronic, and electromechanical control, sensing, and actuation. Circuit, apparatus, and method for interfacing an electrical or electronic component or a mechanical component generating or effecting an electrical or electronic signal to a control system or device. Comprehensive universal input/output interface system, circuit, and method for interfacing such components and control systems that send or receive analog or digital voltage and/or current inputs over a large range of voltages and/or current without hardware or software switches.

One embodiment provides an electrical input and output (I/O) interface including a first port for coupling the interface to a first external device, a second port for coupling the interface with a second device, an operating circuit communicating with a first signal set at the first port and communicating a second signal set at the second port and performing an operation on one of the first signal set and the second signal set as an input and generating the other one of the first signal set and the second signal set as an output, and an operation selector selecting the operation performed by the operating circuit from among a plurality of operations.

In another aspect, the invention provides a method of interfacing a process or machine controller with a sensor monitoring a condition within the process or machine or an actuator acting to modify the process or machine with a controller receiving inputs from the sensor or sending commands to the actuator, where the method includes: coupling the sensor or actuator with first and second electrical terminals of an interface having a plurality of operation mode circuits providing different signal type input and output functions including a digital input function, a digital output function, an analog input function, and an analog output function; and controlling activation and deactivation of different ones of the operation mode circuits to provide a selected ones of the signal type input and output functions.

Embodiments of the invention provide a comprehensive universal electrical input and output interface and interface method between a controller (or other device) and the sensors and actuators or other transducers of a machine or process, used in monitoring, or monitoring and controlling the machine or process. In one embodiment, the inventive interface and method includes and needs only two terminals for the connection of sensor or actuator. It also includes a plurality of operation mode circuits to accomplish the following functions: digital input, digital output, analog input, analog output, and in some embodiments a combination of these functions. The inventive interface also supports either voltage or current input and output, and voltage and current capabilities over a broad range, such as from millivolts to hundreds of volts. These features may be provided in a single physical package for user configuration into a broad set of applications.

DETAILED DESCRIPTION OF SELECTED EMBODIMENTS

Various embodiments and features of the inventive system, apparatus, circuit, method, and signal set are now described relative to the figures.

With reference to the embodiment of the invention inFIG. 1, sensors70, such as sensors installed in industrial processes or machines, provide external controllers14, frequently computers, with the information (typically via analog or digital electrical signals) upon which to base control decisions that are subsequently implemented by actuators72. Embodiments of the inventive input/output Engine (I/O Engine)15provides a universal electronic interface between a wide variety of sensors70and actuators72and sensor first and second pins, nodes, or connections74,75; and first and second actuator pins, nodes or connections76,77. Each of the sensors and actuators requiring only two terminals T1101and T2102of the I/O Engine interface.

Typically, the two terminals T1101and T2102of the I/O Engine interface see the serial combination of either or both sensor70in series with a voltage or current source71, or actuator72in series with a voltage or current source73. These are somewhat idealized models but suffice for describing the structure and operation of the inventive structure and method.

Controller14may typically use a conventional SPI (Serial Peripheral Interface) with a single connection each for receiving STAT106(status) information, sending CMD105(command) data and sending CLK (clock)109, though other different signal sets or signaling schemes may be used. Note that signal CLK109is required only for the analog operations that use the Point-Controller12, and is optional or not needed for other operations. Furthermore, in all but the simplest processes electrical isolation block11should be provided between the Controller14and the I/O Engine15, though this is a safety and implementation derived requirement rather than a requirement of the invention of any embodiment of the invention. Isolation may conveniently be provided for the STAT106, CMD105, and CLK109signals using optical or magnetic components to provide the desired degree of isolation when utilized. Configuration data supplied by the Controller14selects which of the seven different modes of operation shown inFIG. 1meet the requirements of the multitude of different characteristics of most sensors and actuators. Point controller12and point controller table values for selecting an operating mode are described in greater detail elsewhere in this specification relative toFIG. 9andFIG. 10.

It is noted that inFIG. 1, data lines are conveniently illustrated as solid lines and control lines are illustrated as dashed or broken lines.

Although the modes are explained individually in the sections to follow, it is to be noted that in the inventive structures, circuits, and methods described herein, input modes for a given signal type can be used concurrently with their output modes. This makes it possible to read the actual output signal rather than the usual conventional method (and limitation) of reading the state of the output command register. The inventive structure and method thereby providing for reading the actual value not merely the commanded value.

Point-controller12which typically includes a microprocessor and analog input and output functions is required only for analog type input and output signals and may be eliminated or not used for other signal types. Furthermore, if only dc input and output signals are used, the bridge circuit10can be eliminated.

It will be appreciated that the embodiment of the I/O Engine15presented inFIG. 1illustrates a comprehensive universal input/output interface that explicitly supports seven modes of operation. It will also be appreciated by those workers having ordinary skill in the art in light of the description provided herein that embodiments of the invention having only one mode, any combination of two or more modes, or all modes may be provided in any single device or interface block or package. For example, an I/O Engine15having only a Mode 1 (Input Digital ON/OFF) capability, only a Mode 2 (Output Digital ON/OFF) capability, only a Mode 3 (Output Digital ON/OFF Analog Amps) capability, only a Mode 4 (Input Analog milliamps) capability, only a Mode 5 (Output Analog milliamps) capability, only a Mode 6 (Input Analog Volts) capability, or only a Mode 7 (Output Analog Volts) capability, are contemplated by the invention although such embodiments would not provide the comprehensiveness of embodiments having additional operating mode capabilities. But, for example, an embodiment of the invention might for example provide for any one or more of Mode 1, Mode 2, and Mode 3 operation; or alternatively Mode 1, Mode 3, Mode 6, and Mode 7 operation. Elimination or deactivation of a particular circuit or set of circuits from a commercial device may permit manufacture and sale of such commercial device at a lower price where the set of operating modes needed by a customer is restricted. It will also be appreciated that while the embodiment of the I/O Engine illustrated inFIG. 1shows separate functional blocks for each of the seven modes, that other embodiments of the invention may provide either for separate and distinct sets of circuits to provide the operating mode capability, or for shared sets of circuits and components where such sharing is technically feasible and of operational, cost, commercial, or other advantage.

Having now described various embodiments of the overall I/O engine and their interfaces to external sensors, actuators, and controllers, attention is now directed to a somewhat more detailed description of the sensor70and actuator72connections and to bridge circuit10which is utilized for some signal types in embodiments of the invention. In general, a bridge circuit such as bridge10is utilized in order that a single unidirectional circuit path is available to either monitor sensors or to control actuators. (Recall that in embodiments of the invention or applications where only dc input and output signals are used, the bridge circuit10can be eliminated.) While workers having ordinary skill in the art will appreciate that there are many bridge circuits as well as other non-bridge circuits known in the art that will provide the desired operation, the four diode bridge circuit10ofFIG. 2serves to illustrate the desired operation.

In this embodiment, diodes D1201, D2202, D3203and D4204ofFIG. 2make up a conventional full-wave bridge10that when excited by either an ac or dc voltage applied to its first and second input leads or terminals107and108will produce an output voltage signal output at output lead or terminal110that is positive with respect to a reference (such as ground reference) output lead103. As in the general case, bridge10is utilized to provide a single unidirectional circuit path to either monitor sensors70or to control actuators72.

Applications that sense a condition of sensor70are conveniently described as input applications and applications that control an actuator are conveniently described as output applications.

With input applications, a sensor70, that can be as simple as a mechanical switch or as complex as a variable impedance, in series with a power source71produces a voltage or current that is applied to terminals T1101and T2102. Resistor130is representative of the one or several current paths within operating modes and their corresponding circuits or logic16between signal110and reference or ground103causing a current133through the resistor (current path)130. A current of the same magnitude132flows from terminal T1101via lead107to the Bridge10and also from the Bridge10through lead108to terminal T2102. The direction of current132depends on the polarity of the signal applied from Sensor70and its power (voltage or current) source71.

With output applications, an actuator72, that can be as simple as a relay or as complex as a voltage or current actuated device (such as for example a proportional valve) in series with a power (voltage or current) source73energizes a voltage or current path that is applied to terminals T1101and T2102. Variable resistor131is representative of the one or several current control paths within operating modes and their corresponding circuits or logic16between signal110and reference or round103causing a current133, the magnitude of which is controlled by the equivalent resistance131. A current of the same magnitude132flows from terminal T1101via lead107to the Bridge10and also from the Bridge10through lead108to terminal T2102. The direction of current132depends on the polarity of the signal applied from actuator72and its power source73.

A first mode of operation (Mode 1) is now described relative to the embodiment of the invention illustrated inFIG. 3. The first mode of operation, or Mode 1, involves digital inputs or inputs having a first or ON state or a second or OFF state. These generally correspond to “0” and logic values and a corresponding signal that may be encoded in a variety of ways. For example, in terms of a low and high (or high and low) voltage level, a pulse or signal duration such as a pulse length modulation scheme, or other signaling schemes that are known in the art.

With further reference toFIG. 3, operation of bridge10generates an output signal110relative to a reference or ground signal103, or where each line is considered differently, two output signals103and110. Bridge circuit10may for example be the four-diode bridge circuit illustrated and described inFIG. 2, or any other circuit that performs analogous or equivalent signal processing or conditioning. This or these bridge output signals103and110serve as inputs to Level Detector20and Milliamp Common40.

Receiving and reacting to bridge output signals103and110, Milliamp Common40produces an output LV signal111that increases in magnitude as the current133through a low current detection circuit falls below its preset constant current value. In one embodiment, typically, the current133is on the order of about 1 mA or less, though larger currents may occur in other embodiments. Point-Controller12includes a digital-to-analog converter (DAC) that outputs a milliamp control signal (mACTRL)429(SeeFIG. 6) set in a tri-state mode that allows internal circuits to provide a low level constant current. This low level constant current may be used for the preset constant current value.

Low magnitude current detection advantageously makes it possible to evaluate the ON or OFF state of logic level signals (for example, logic level signals in about the ±3 to 15 volt range) and reduce the effects of voltage generated noise on the lines connected to terminals T1101and T2102, as such lines may be maintained in a substantially current noise free state and it is difficult to induce current noise in such lines. Within Level Detector20, low-voltage (LV) signal111is compared with a predetermined reference and produces a low-voltage state output signal (LV ON/OFF)112indicating the ON or OFF state of the low current path.

At a top-level, level detector block or circuit20receives signals from the input (and optionally through bridge10when required) and compares the received signal with one or more reference voltages to determine the voltage and/or current characteristics of the input signals, particularly whether the input falls within a high-voltage range or a low-voltage range. In some embodiments, the low voltage range may be a voltage magnitude between about 0 volts and 15 volts such as may be encountered for electronic circuit logic level signals, and a high-voltage may be a voltage for example greater than 24 volts, or greater than 100 volts.

In one embodiment, resistive voltage divider circuits or other circuits are used within the Level Detectors block20to both generate reference voltages and to attenuate the input signal in step-wise manner so that comparisons may be made using two-input comparators between reference voltages and attenuated signal voltages.

In one embodiment, three comparators are used for these voltage comparisons. A first comparator216generates a low-voltage on/off (Lv On/Off) signal112by comparing input LV signal111received from the current detector42section of milliamp control40with a first reference voltage221. Second comparator217generates a high-voltage/low-voltage select signal (Hv/Lv Select)113by comparing an attenuated version of input signal110with a second reference voltage222. The output of second comparator217provides output signal high-voltage/low-voltage select (HV/LV Select)113to Current-Voltage Selector21. Third comparator218generates a high-voltage on/off signal (Hv On/Off)114by comparing the same attenuated input signal with a third reference voltage223. The output of the third comparator218provides a high-voltage on/off output signal (HV ON/OFF)114to Ripple filter22and then on to Current-Voltage Selector21.

For ac signals, the attenuated input as presented to third comparator218after being rectified by bridge10, will vary from 0 volts to a peak voltage Vp volts and back to 0 volts. This causes the high-voltage on/off signal (Hv On/Off)114output to drop out for a portion of each ac signal cycle which dropout is removed by ripple filter22.

Current Voltage-Current Selector21controls which ON/OFF signal, either low-voltage on/off (Lv On/Off) signal112or filtered high-voltage on/off signal (Hv On/Off) signal242(filtered high-voltage on/off signal (Hv On/Off)114) is to provide the output STAT106. Low-voltage on/off (Lv On/Off) signal112is presented at STAT when Hv/Lv Select113has not detected the presence of a high voltage. Filtered high-voltage on/off signal (Hv On/Off) signal242is provided at STAT106when Hv/Lv Select113has detected a high voltage input, this information is latched in current-voltage selector21and used to direct subsequent Hv ON/OFF data to STAT106. Characteristics and operation of level detectors20, current voltage selector21, and ripple filter22are described in greater detail relative to the embodiment inFIG. 11and elsewhere in this specification.

A second mode of operation (Mode 2) is now described relative to the embodiment of the invention illustrated inFIG. 4. This second mode of operation, or Mode 2, involves digital outputs or outputs having a first or ON state or a second or OFF state.

In this embodiment, Load Control block or circuit33provides a controllable means including circuit elements in one embodiment for controlling the completion of the current path connecting Terminals T1101and T2102as directed by a current control (ICTRL) signal330communicated from surge control block32to load control block33. The Load Control33output signal, Load Current122, is an electrical signal whose magnitude is proportional (or at least substantially proportional) to the current passing through Load Control33and terminals T1101and T2102.

If Circuit Breaker circuit31determines, after a time delay, that the magnitude of Load Current122is greater than a predetermined acceptable limit, its output circuit-breaker OK signal (CBOK)307provides a circuit-breaker “tripped” or not OK state, and its complementary OK state.

CMD Control block or circuit30provides a surge control Enable signal306to Surge Control32when called for by command signal (CMD)105so long as Circuit Breaker31output signal CBOK307permits.

When enabled by Enable signal306, Surge Control circuit32provides a time dependent changing level output current control signal (I CTRL)330to Load Control circuit33. It can be shown that, the current passing through Load Control circuit33and terminals T1101and T2102is directly proportional to the magnitude of the current control signal (I CTRL)330, thus providing the structure, method, and means for limiting the maximum load current, as well as provide the structure, method, and means for “time shaping” load current33during both turn-on and turn-off of loads in response to command (CMD) signal105. Such “shaping” can desirable minimize current induced turn-on and turn-off EMI (electromagnetic interference) and RFI (radio frequency interference) with their related noise transients, and can also substantially reduce otherwise destructive mechanical and thermal shock to various actuators such as valves, motors and incandescent lamp loads. These structural, circuit, and method features therefore provide capabilities and advantages that are not available in conventional circuits, systems, or methods.

It is to be noted that the Mode 1 Digital Input functions can operate simultaneously with Mode 2 Digital Output.

A third mode of operation (Mode 3) is now described relative to the embodiment of the invention illustrated inFIG. 5. This third mode of operation, or Mode 3, involves digital output with load current input. Architecturally and from a circuit component standpoint, the Mode 4 configuration adds a point controller12to the structure already described relative to the embodiment inFIG. 4. Of course, the structure illustrated inFIG. 5that includes the point controller may be used for Mode 2 operation by temporarily disabling the point controller or by ignoring its outputs.

Point controller12may for example be a microprocessor Type controller, such as the model ADμC812 made by Analog Devices of Massachusetts, USA. Functionally, point controller12is used in this embodiment to select which circuitry is active for a given mode and encode and decode analog values and other data to and from serial bit streams for communication with controller14.

In Mode 3 operation, Point Controller12upon the receipt of a unique external command via a digital bit stream on command signal (CMD)105, causes CMD Control block or circuit30, via the Ana Select signal120to ignore any subsequently received direct signals via command signal (CMD)105. The unique external command signal may be any signal recognized as being for this purpose. In this manner, only Point Controller12controls, via Local ON/OFF signal115, the CMD Control block30output enable signal (Enable)306. Other than these changes, other digital ON/OFF functions operate the same as already described relative to Mode 2 operation and the embodiment inFIG. 4, and is not repeated here. The external Controller14(SeeFIG. 1) coupled to the I/O Engine15through optional isolation11, may retrieve the load current information from Point Controller12through a digital bit stream on status signal (STAT)106.

Fourth and fifth modes of operation (Mode 4 and Mode 5) are now described relative to the embodiment of the invention illustrated inFIG. 6. This fourth mode of operation (Mode 4) involves determination of analog signal level proportional to current flow in the range of a few milliamps, and conversion of this signal level into a form suitable for transmission to the controller14, and the fifth mode of operation (Mode 5) involves use of analog values conveyed from the controller14to control the output current, in the range of a few milliamps to one of a plurality of current flow rates proportional to the analog value.

For Mode 4, when an external current signal, of either polarity, is applied to terminals T1101and T2102of rectification or bridge circuit10, bridge circuit output signal110will be positive with respect to ground103owing to the rectification provided by the bridge circuit. On basic electronic circuit principles, current flow between terminals T1101and T2102must pass through circuitry connecting signal110and ground103. In modes 4 and 5, Milliamp Common40provides this path.

Milliamp Common40uses a digital-to-analog converter (DAC) output milliamp control signal (mACTRL)429provided by point-controller12, to control the current flow from terminal T1101through bridge10to terminal T2102. Point-controller12, output milliamp control (mACTRL)429is at maximum for Mode 4 in order to cause FET424to its lowest resistance state, typically less than 100 ohms, so that the current between terminals T1100and T2is not affected. Milliamp Common40generates a voltage signal (mA)430, which is proportional to this current flow, which is an input to an analog-to-digital converter (ADC) within point-controller12, and is digitized to provide a serial bit stream output over status signal (STAT)106to controller14.

In Mode 5, Point Controller12, in response to a serial bit stream command from controller14, generates a voltage signal mACTRL429, having a plurality of levels proportional to the desired current flow. Circuitry within Milliamp Common40uses mACtrl429to control the current flow between terminals T1101and T2102. During operation in Mode 5, the current between T1and T2may also be monitored as described for Mode 4.

A sixth mode of operation (Mode 6) is now described relative to the embodiment of the invention illustrated inFIG. 7. This sixth mode of operation involves analog voltage inputs.

Voltage signals, ac or dc, applied to terminal T1101, complete a circuit path through Attenuators51, and Ground Select54to Terminal T2102. Attenuators51scales the applied input signal107from T1101based on the magnitude and type (ac or dc) of input signal107. On or more attenuator control signals603(SeeFIG. 14for an embodiment providing four attenuator control signals604,605,606, and607), allows point-controller12, to configure various scaling factors for scaling the input signal to a value or value range that is suitable for input to an analog-to-digital converter (ADC). In this embodiment, the ADC input range is 0-2.5 volts. The scaled version proportional to the voltage between T1101and T2102is applied via signal613and614to an ADC within point controller12where its value is digitized and available as a serialized output over STAT106, to for example, external controller14.

Voltage Limiter52, optionally but desirably provided, prevents component damage the I/O Engine in the event input signal107is greater than the range configured by point-controller12.

Circuitry of Ground Select54, an important element of the invention, via Ground Control lines103,608, and609, under the control of Point Controller12, selects the appropriate ground return based on signal range and type.

Ground select circuitry54selects the appropriate ground return based on signal range and type under control of point-controller12, this feature provides significant advantages over conventional circuits and methods. Selection of an appropriate ground path is made via one or more ground control signals from point-controller12to ground select54. A particular embodiment of the ground select circuit54, one particularly advantageous aspect of the invention, is described in greater detail relative to the embodiment ofFIG. 14.

A seventh mode of operation (Mode 6) is now described relative to the embodiment of the invention illustrated inFIG. 8. This seventh mode of operation involves control of analog voltage outputs.

With reference toFIG. 8, a digital-to-analog converter (DAC) that is part of Point-Controller12provides a voltage control signal (V CTRL) signal706to Voltage Output drive circuit700that provides analog output voltage via input/output interface lead107directly to terminal T1101and via ground select54and input/output interface lead108to terminal T2102.

Concurrent with the Mode 7 operation, but not shown inFIG. 8to avoid obscuring structures utilized for Mode 7 operation, Mode 6 operation may optionally but advantageously occur for the analog voltage input so that voltage is monitored and compensation may be provided to correct for errors that can occur in Voltage Output Drive700.

Voltage Output Drive Supply circuit701provides the voltage level and current sufficient to meet analog output signal needs. Voltage Limiter52detects erroneously applied external voltages to terminals T1101and T2102and acts to disconnect, via Ground Select54, any damaging current flow that might occur.

For each of the output modes corresponding input modes can be used simultaneously, specifically Mode 1 with Mode 2, Mode 4 with Mode 5 and Mode 6 with Mode 7. Within appropriate signal ranges different modes can be dynamically invoked sequentially.

Attention is now directed to description of some further embodiments of the invention, and in particular to some specific circuit implementations of the afore described point-controller12and of the Mode 1-Mode 7 configurations of the inventive comprehensive interface and input/output engine.

With reference to the diagrammatic illustration of an exemplary point-controller12inFIG. 9and the Mode Control Table inFIG. 10, it is noted that point controller12provides structure, control, and other means for a single device to operate in any of the seven modes encompassing digital input and output and analog input and outputs. It allows selection of any one of these seven modes, on an individual point basis, at the discretion of the external controller14. By on a “point basis” we mean that the type of signal used to interface individual sensors or actuators need not be the same for blocks of two or more sensors or actuators within the same system.

Point controller12has a plurality of digital outputs and inputs which provide for data flow to and from various components, including the selection of which components are active in a given mode. The point controller also provides a plurality of Digital-to-Analog Converters (DACs) and Analog-to-Digital Converters (ADCs) used by the various analog modes. It also includes circuits, lines, control, and other means of communicating with an external controller14.

For a device which is to operate only in Mode 1 and/or Mode 2 involving digital input and/or digital output, point-controller12is not required, but as it may be deconfigured from active operation in the circuit, it may be provided in a single comprehensive interface package and ignored when not required for the intended operation.

A particular embodiment of a point-controller comprising an Analog Devices microcontroller Part No. ADμC81260and Analog Devices analog-to-digital converter Part No. AD771561is now described relative to an exemplary embodiment inFIG. 9. Products made by other manufacturers having comparable features may alternatively be used and it will be understood by those workers having ordinary skill in the art that there are many alternative and equivalent commercial devices as well as custom devices and circuits that may be employed. The exemplary ADμC812 includes a microprocessor with digital I/O lines, a SPI interface, two 12 bit DACs and an eight channel 12 bit ADC.

The AD771561used during Mode 6 and Mode 7 operation, is a 16 bit ADC with SPI interface and a Programmable Gain Amplifier (PGA). The PGA is particularly useful in reading any of several analog signal ranges.

In this particular embodiment, communications between the ADμC81260and the external controller14is via a SPI interface utilizing command signal (CMD)105, status signal (STAT)106and clock signal (CLK)109. This communications allows the external controller14to send commands that select which of the seven modes to configure, writes values for outputs, and reads values of inputs and outputs.

The ADμC81260contains a program that allows it to control its various I/O lines, DACs and ADCs as well as communicate with controller14and react to commands from the controller14. The details of such a program are known in the art and not described in further detail here. Other microcontrollers than the ADμC812 may alternatively be used and provide similar or analogous features so that neither the invention nor any particular embodiment of the invention are limited to use of this particular microcontroller.

The point controller12uses a plurality of digital and analog signals that are summarized inFIG. 10and described below.

Two ADC channels of the ADμC81260measure signals (mA)430, of Modes 4 and 5, and load current (LdCur)122of Mode 3. The ADC in AD771561is used to measure the scaled voltage613of Modes 6 and 7. Control of AD7715 by ADμC81260is via SPI bus leads ADC CLK126, AD DI127and AD DO128.

One DAC of ADμC81260provides the milliamp control (mACTRL) signal429of Modes 4 and 5. A second DAC provides voltage control signal (VCTRL)706for Mode 7 operation.

Digital I/O output lines603,604,605,606,607, and608of ADμC81260are used to select circuitry used for various signal ranges of Modes 6 and 7. For other modes these signals are generally low to disable such circuitry.

The Ana Sel signal115, another digital output line of ADμC81260when high, connects CMD105and STAT106directly to the circuitry used in modes 1 and 2. When AnaSel115is low, CMD105and STAT106are preempted for the exclusive use of ADμC81260for its own use in communicating with Controller14.

In Mode 3, AnaSel115is low and Local ON/OFF is used to control the ON/OFF state of the external load. In Modes 4, 5, 6 and 7, where AnaSel115is also low, Local ON/OFF is low to turn off the current path used during digital output.

With reference toFIG. 11, attention is now directed to a further embodiment of a Mode 1 configured level-detector block or circuit, a top-level description of which structure and operation was provided relative toFIG. 3. This includes circuitry for the level detector20, the current-voltage selector21and the ripple filter22. The milliamp control40circuitry is shown separately inFIG. 13.

A network of four resistors212,213,214,215connected in series between Vcc104and ground103provide first, second, and third reference voltages221,222,223for use in comparisons with input signal voltages by the first, second, and third comparators216,217,218.

The ratio of resistors210,211forming a voltage divider between first and second level detectors circuit20input signal110and ground103are chosen to limit the attenuated input signal voltage220between resistors210,211to a value which will not damage the comparators with the highest level detector circuit input signal110voltage. The sum of resistances210,211is chosen to be large enough to limit the current flow and power dissipation, as well as keeping the leakage current low enough to allow turning outputs off.

First comparator216generates a low-voltage on/off (Lv On/Off) signal112by comparing LV signal111with it's own first reference voltage221. LV signal111is received from the current detector42section of milliamp control40that is shown separately inFIG. 13. As the potential of signal110becomes smaller, op amp output111increases in an attempt to maintain current433constant. The magnitude of signal111is used in the determination of the ON or OFF state of input signal110.

Second comparator217generates a high-voltage/low-voltage select signal (Hv/Lv Select)113by comparing the attenuated signal220with it's own second reference voltage222. The reference voltage222of the second comparator217is based on the dividing level between typical ac input control signals (usually above 24 Vac) and lower levels logic signals (generally 15 Vdc and lower), of course any other dividing level may be selected to suit the particular application. So for example, a dividing level of for example 15 volts, 20 volts, 24 volts, or other appropriate voltage level may conveniently be selected. The output of the second comparator217provides output signal high-voltage/low-voltage select (FV/LV Select)113to CurrentVoltage Selector21.

Third comparator218generates a high-voltage on/off signal (Hv On/Off)114by comparing the same attenuated signal220with its own third reference voltage223that is nominally half of second reference voltage222. The output of the third comparator218provides output signal 1V ON/OFF114to Ripple filter22and then on to Current-Voltage Selector21.

Current Voltage-Current Selector21controls which ON/OFF signal112or242(filtered114) is to provide output STAT106.

For ac signals, the attenuated input voltage signal220as input to comparator218after being rectified by bridge10, will vary from 0 volts to a peak voltage Vp volts and back to 0 volts. This causes the high-voltage on/off signal (Hv On/Off)114output by third comparator218to drop out for a portion of each ac signal cycle. Ripple filter22has a resistor240and capacitor241that removes this dropout from signal242presented to the current-voltage selector circuit21.

The current-voltage selector circuit21latches the high voltage state of the high-voltage/low-voltage select signal (Hv/Lv Select)113with a bistable flip-flop composed in one embodiment of NAND gates230,231, though other logic may alternatively be used. The NAND gate output signals232,233are used to enable one and only one of the next pair of three-input NAND gates234,235, which in turn determine whether the low-voltage on/off (Lv On/Off)112or high-voltage on/off (Hv On/Off)114signal condition is reflected in the status (Stat)106output signal of the maControl block or circuit40.

Each NAND gate234,235has a third input AnaSelect115, generated by the point controller12. This allows the point controller12to disable both gates for other modes. When so disabled, Stat106is pulled high through resistor237to Vcc104, allowing control of Stat106by the point controller. If a point controller is not present, AnaSelect115is pulled high through resistor236to Vcc104, thus allowing either NAND gate234or235to be enabled.

This embodiment shows two thresholds for on/off determination, additional thresholds could be utilized by adding more comparators to the level detector20and additional gates to the current-voltage selector21as will be apparent to those skilled in the art.

A further embodiment and implementation of the digital output circuitry for Mode 2 and Mode 3 operation is now described with reference toFIG. 12. Also included is the generation of the Signal Load Current122used in Mode 3 operation. The optional output status signal (STAT)106is the same as previously described for Mode 1, and not repeated here.

Current practice in electronics typically utilizes either triacs or Field Effect Transistors (FETs) to control power level loads. Triacs mimic the characteristics of their mechanical counterpart, switches, they are either fully on or fully off; however, unlike conventional mechanical switches, can only control ac loads. After triacs are triggered or turned on, a minimum holding current is required to maintain them in an on state. This characteristic leads to two limitations in conventional practice that require correction for satisfactory operation in the present context.

First, triacs turn off for a short period of time during each zero crossing of the ac voltage signal because the current becomes less than the triac minimum holding value. This turn-off and subsequent turn-on at the ac line rate, gives rise to the generation of troublesome electromagnetic interference (EMI) that may require the use of filtering to remove or control the interference within acceptable limits. Second, driving devices loads (such as for example, solenoid controlled or activated valves in a controlled process or machine) whose current requirements are less than the triac's holding requirement necessitate the adding of power-wasting resistors in parallel with the load. In order to minimize the triac controlled turn-on surge current and minimize EMI, special “zero” crossing circuitry is used that enables turn-on only when the ac supply-voltage passes through zero.

Triac turn-off, with inductive (L) loads, produces inductive “kick”, that is, L di/dt voltages, high voltages that can be sufficient to cause triacs to lose control. The addition of so-called “snubbing” resistive-capacitive (RC) networks is required to protect the switching device and to reduce the effects of EMI generated by the triac turn-off. Triac turn-off can generally only occur as its current approaches zero, which is not necessarily when the voltage approaches zero. Therefore, a triac turn-off time delay of up to one-half cycle from the zero voltage crossing of the ac power source will occur.

Power level loads may alternatively be controlled using power FETs. A power FET, a unipolar device, when used with the invention's Field Terminal Circuit214, can control both ac and dc loads. FETs may be thought of as a voltage controlled resistor whose resistance is controlled by the FET gate-to-source voltage. Conventionally, the FET gate current is controlled with an ON/OFF signal and operation depends upon the inherent and so called constant-current characteristic of individual FETs to control surge current. It is known; however, that this so called constant-current FET characteristic typically varies from FET to FET and with operating temperature.

FETs controlled by ON/OFF switching signals are exposed to similar electrical problems as those arising when triacs are used, such as surge currents (or inrush), that can be very high at turn-on for inductive loads, as a consequence of their low dc resistance, and for incandescent lamp loads with their low cold temperature resistance.

A FET, which behaves as a variable resistor, may also be partially turned on to control the maximum current to values which are intermediate between the full ON and full OFF values. By controlling the current to slowly turn on and off the external load, undesired problems and conditions observed with conventional circuits and methods, previously described, are reduced.

In the embodiment ofFIG. 12, FET333is a power FET with a very low RDSon(the minimum value of the drain-to-source resistance). FET333is able to carry high voltage currents, such as currents in the multi-ampere range.

Sense resistor339, used to monitor or sense the load current, desirably has the lowest value practical in order to minimize its power dissipation when carrying large currents.

Operational Amplifier (Op Amp)332, with its first and second biasing resistors331,334, are configured as a voltage follower loop controlling FET333. This loop follows the voltage drop across Sense Resistor339which is proportional to the load current, and allows FET333to control the maximum current to a value proportional to current control (I CTRL) signal330. This maximum current is, independent (or at least substantially independent) of operating temperature and characteristics of the FET.

Load control circuit33also includes Op Amp336which amplifies the voltage drop across load resistor to provide the Signal Load Current122at its output, which is in turn input to the circuit breaker circuit31. In Mode 3 operation, the Load Current122is also input to the point-controller12.

Circuit Breaker31monitors Load Current122as provided by Load Control circuit33. This signal122is delayed by the Resistor315and Capacitor316to provide input signal314to Comparator313. Comparator input signal314is compared to a voltage reference value317generated from the voltage divider consisting of first and second resistors318,319between supply voltage Vcc104and Ground103. When the current level, as reflected by comparator input signal314, exceeds the reference voltage317, the comparator output signal312of Comparator313sets the flip-flop309(composed of first and second NOR Gates310,311) to its tripped state. This in turn causes CMD Control circuit30via circuit breaker OK (CBOK) signal307to override the commanded ON state, ultimately causing the external load to be turned OFF.

Flip-Flop309(NOR gates310,311) will stay in this tripped state until Signal308from CMD Control30reflects a command OFF state. Output circuit breaker OK (CBOK) signal307will then reflect a non-tripped state allowing normal operation to resume.

The surge control circuit enable (Enable) signal306from CMD Control circuit30is either ON or OFF (asserted or deasserted). For a variety of reasons previously described and/or known in the art, suddenly turning ON or OFF the external load is undesirable. This is true for command changes of state as well as circuit breaker trips.

Surge Control32, via the combination of capacitor322and resistors320,321, reshape the square wave of the Enable signal306into a current control (I CTRL) signal330. This reshaped current control signal330has a slower rise and fall time owing to the signal conditioning in surge control32. This signal, when applied by Load Control33allows full control of the rate of current change in the external load. A simple R-C network is shown, but more complex or different configurations can be implemented, using either alternative passive element topologies and/or using digital and/or analog outputs of point-controller12.

In CMD Control30, the combination of NAND Gates302,303together with Inverter301and NOR Gate304allow a select signal to determine which of two signals CMD105from Controller14or Local ON/OFF121from Point Controller12, control NOR Gate304, NOR gate output signal308, and ultimately affect or determine the ON/OFF state of the external load via Signal110. It also includes NOR Gate305which allows Circuit Breaker31Output307to Override308, thus allowing a tripped circuit breaker to turn OFF the signal at306, and ultimately the external load, even though it would otherwise be ON. Signal308, when in the output OFF state, also resets the Circuit Breaker31, so that normal operation may resume.

With reference toFIG. 13, the central element of mA Control block or circuit is operational amplifier (op amp)423configured as a voltage follower with FET424and resistors427and428completing its negative feedback. By closed loop voltage follower action, operational amplifier output111, applied to the gate of FET424, causes voltage level426to be equal to operational amplifier input422with the result that a current433is equal to the voltage422divided by the sum of resistors427and428.

It is to be noted that the magnitude of current433is constant and is independent of the applied signal voltage110so long as operational amplifier input422is equal to or larger than voltage422. It is this characteristic that makes it possible to operate over a wide range of input signals110without the necessity of having to dissipate the power loss of voltage divider type of input circuits. Furthermore, because it is current rather than voltage that is being detected the effects of voltage induced electrical noise on input lines is significantly reduced.

As the potential of signal110becomes smaller, op amp423output signal111increases in an attempt to maintain current433constant. The magnitude of signal111is used in the determination of the ON or OFF state of input signal110.

A flip-flop made up of NOR gates411and412driving the gate of FET410form the Current Limiter41. On power-up, capacitor413and resistor414cause signal431to be high causing the output of NOR gate412to be low and in turn causing the resistance of FET410to be many megohms. Should signal110become so large that current433exceeds specified limits, voltage415will cause the flip-flop to change state with the result that the resistance of FET410approaches 100 ohms forcing signal422to near ground with the result that operational amplifier423output111will cause the resistance of FET424to its many megohm state that reduces and holds current433to a safe value.

Signal mA430, a voltage signal across resistors427and428, is proportional to the current433and is utilized in Modes 4 and 5. Signal mACTRL429, an output of point controller14, is utilized in Modes 4 and 5 and can over ride the magnitude of signal422established by the voltage divider action of resistors420and421, that is used in Mode 1.

With reference toFIG. 14, Point Controller12, via eight control lines601through608, control all of the operations of Mode 6, the Analog Voltage In operating mode. (Other controllers may use a different number or different control lines, but it will be understood that the same or analogous operation may be achieved.) Control lines607and608in concert with Voltage Limiter output609enable AND gates640and645respectively, causing FETs642and647to their less than 100 ohm resistance states so that Terminal T2102, Ground103and lead613between Attenuators51and Ground Control54are at the same electrical potential.

Point controller12control lines603,604and605respectively via AND gates620,625and630respectively cause FETs622,627or632to be in their low less than 100 ohms resistance states. Attenuation of input signals, for inputs greater than full scale range of an ADC (analog-to-digital converter) that is part of Point controller12, requires Control signal606, via AND gate635, to place FET637in its low resistance state and connect resistor638effectively to terminal T2. Resistor638is part of a voltage divider made up of diode624and resistor623for ac voltages or resistor628for dc voltages. The resulting divided voltage615via resistor660and613that appears across resistor638and FET613are applied respectively as Voltage+614and Voltage−613to an ADC (analog to digital converter) that is part of Point Controller12. For low voltage inputs Attenuator51FET632is placed in its low resistance state and FET637is placed its multi-megohm state thus connecting thus allowing the input via resistor660to be applied directly to the ADC.

Transient protector662with resistor660protects the ADC from damaging high voltages If either of the input signals615or613exceed a limit determined by reference resistor network652and656, the outputs663of Comparator653or657of Voltage Limiter52goes low setting the flip-flop made up of NAND gates658and659such that signal601via gate650will bring all FETs to their high resistance state and protect all circuits from damage.

The states of four Point controller12control lines603through606when enabled by Voltage Limiter output609determine the attenuation factor to be applied to analog input signals applied between terminals T1101and T2102. For high voltage ac input signals, control line603places FET622in its less than 100 ohm resistance state.

With reference toFIG. 15, attention is now directed to an embodiment of the invention operating in Mode 7 for an analog voltage output situation. In the Voltage Output Drive circuit700, operational amplifier703is configured as a voltage follower, by means of first and second resistors707and709, causing operational amplifier output signal704to be directly related (by an amplification or multiplier factor) to op amp703non-inverting terminal input signal (V CTRL)706. This multiplier relationship, a function of the ratio of the value of first resistor707to second resistor709, and the output (both voltage and current) of Voltage Output Drive Supply701are determined by the full-scale output requirements of Mode 7, voltage output. Optional diode705, desirably provided between operational amplifier703output704and terminal T1101via lead107, prevents circuit damage should a reverse voltage be applied to terminal T1101.

Ground Control circuit54, whose AND gate645enabled by Voltage Limiter52output signal603and Point Controller12output signal609, causes FET647to exhibit a resistance less than 100 ohms thus having the practical effect of bringing internal ground103to the same (or substantially the same) electrical potential as terminal T1101. The function of optional Voltage Limiter circuit52and its output signal603, is to protect circuitry from the potential effects of damaging high voltage applied by mistake between terminals terminal T1101and terminal T2102.

With reference toFIG. 16is a diagrammatic illustration showing the flow of bidirectional Data-Out and Data-In signals over a single conductor or line according to one embodiment of the invention.

Signal line1201from controller14tri-state I/O Port1110through the MonoLine Serial Interface1200to I/O Engine15. The embodiment of the single or monoline serial interfaceFIG. 16includes circuit, software/firmware, logic, or other means for the controller14to sequence a single I/O line port1110through the following states: (i) a low impedance output high, an active state, for transmitting data; (ii) a low impedance output low, an active state, for transmitting data, where the output low state can be held for a variable length of time dependent upon the output data a “1” or “0” for digital data or a plurality of values for analog data; (iii) return to output high to generate an edge which may be used as a SPI clock by the I/O Engine15; (iv) high impedance input, a passive state for receiving data, which state will be maintained until the transmission of the next bit of output data. Sample the input data, interpreting its level as a digital “1” or “0”.

The means for providing this sequence of states may, for example, be via a software driver using a standard tri-state I/O port, or by specific hardware which transfers data to and from registers containing one or a plurality of bits.

The single or monoline serial interface also includes a data direction multiplexer1300, with a means to respond to the active and passive states, as seen at1315from signal1201allowing time alternate bi-directional transfer of information on a time-shared basis.

The active output1201seen at1315is latched such that data-out+clock1311is maintained at the last observed active output state, during the passive input state.

For Data-In STAT106to be returned to Controller14via1201, the Data Direction Multiplexer must transform this signal to meet two requirements: First, it must be presented to1201with an impedance such that the I/O Engine15appears passive to active master output, but active to passive master input. Second, the data-in information must be presented to1201in such a way that it does not change the value latched for data-out+clock1311.

The Data Direction Multiplexer1300achieves this by providing logic ahead of the latch such that the latch changes state only within two narrow signal ranges, one near Vcc104and the other near Ground103. Signal levels between these two ranges, which represent valid high or low values to other logic, or valid analog levels, are in a dead band as seen by the latch and do not affect it. By modifying the values of data-in STAT106, when different from latched data, to fall within this dead band, they can be presented to1201such that they are correctly seen by the Controller14, but do not change the latch.

The data-out extractor1500extracts the data information from the data-out & clock1311and passes it to the I/O Engine15. Data out as CMD105and clock as CLK109. SPI hardware of the I/O Engine is configured to clock data-in and out on the clock trailing edge. When so configured, the data-in signal need only be in its correct state for a short period of time before and after the trailing clock edge.

Optionally, isolation circuitry11, is placed between the data direction multiplexer1300and the Data-Out Extractor1500. It electrically isolates Data-Out+clock1311, Data-In1503, VCC104, and Ground103. By so doing the I/O Engine15is completely isolated form the controller14.

From the foregoing it will be appreciated that embodiments of the invention provide a comprehensive universal electrical input and output interface and interface method between a controller and the sensors and actuators or other transducers of a machine or process, used in monitoring, or monitoring and controlling the machine or process. In one embodiment, the interface includes only two terminals for the connection of sensor or actuator. It also includes a plurality of operation mode circuits to accomplish the following functions: Digital Input, Digital Output, Analog Input, Analog Output, and in some embodiments a combination of these functions. The inventive interface also supports either voltage or current input and output, and voltage and current capabilities over a broad range, such as from millivolts to hundreds of volts. Embodiments of the invention also provide means for controlling activation circuits for a given function and deactivate of other the others within a given function so that interfacing of a plurality of signal types is supported. In other aspects, the invention further includes means for an external controller to activate circuits for a given signal type and deactivate others.

In another aspect, the invention provides an interface that can monitor and return the actual state of output signals as opposed only their commanded status. This is advantageous as it provides a ready means for dynamically detecting while a process is under control that certain actuators are not operating as expected. It also provide a means for reducing installation and debugging time by detecting certain wiring or program errors, such as actual inputs being driven as outputs.

In another aspect, the invention provides interface that can limit damage to said interface as well as sensor or actuator as a result of miswiring or misconnection of the input terminals to other circuits or devices.

In still another aspect, the invention provides an interface with the means, by detecting input current rather than conventional input voltages, for detecting the state of a sensor that reduces the effects of induced electrical noise on lines connecting sensors to the universal interface.

In another aspect, the invention provides an interface with the means for measuring power, both real and imaginary, by dynamically switching between voltage and current measurements.

In still another aspect, the invention provides circuit, system, method, and means for controlling (not just limiting) load current, by providing constant current control, for power level actuators the manifestation of which: (a) can minimize the on-off mechanical shock to electromechanical solenoid valves; (b) can reduce electromagnetic (EMI) and RFA (radio frequency interference) caused by energizing, or de-energizing, inductive loads such as relays and solenoid valves thus reducing the need for circuits to suppress such effects; (c) can increase the speed of operation of inductive devices by driving them with a constant current; (d) can prevent the inherent low-resistance initial current loads of incandescent lamps from tripping circuit breakers; (e) can substantially increase the life of incandescent lamps by eliminating the initial thermal shock resulting from high initial turn on currents; (f) can reduce the destructive effects, both human and mechanical, of the so-called inductive “kicks” (actually −L di/dt) that occur when deenergizing inductive loads; and (g) minimizes the typical half-cycle time delay in energizing and de-energizing ac loads that occur with traditional triac control circuits.

In another aspect, the invention provides a single assembly or device, and as a result of a single assembly being able to monitor and control a wide variety of sensors and actuators, (that is a veritable one size fits all), to materially reduce the engineering time and cost required to design, purchase, assemble and debug the components of a system.

In another aspect, the inventive interface is provided in any of several industry standard physical and electrical connection configurations for retrofit replacement of conventional interface components.