SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device according to the present embodiment includes a substrate, a first semiconductor chip, a second semiconductor chip, a bonding layer, and a member. The substrate has a first surface. The first semiconductor chip is provided on the first surface. The second semiconductor chip is provided above the first semiconductor chip, has a second surface facing the first surface and the first semiconductor chip, and coats the first semiconductor chip as viewed from a direction substantially perpendicular to the first surface. The bonding layer is provided between the second surface and both the first surface and the first semiconductor chip. The member is provided on at least part of an outer periphery of the bonding layer as viewed from the direction substantially perpendicular to the first surface.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2022-093908, filed on Jun. 9, 2022, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof.

BACKGROUND

In a package structure of a semiconductor device, there is occasionally a case where a memory chip is arranged so as to cover a controller chip on the substrate with a thick DAF (Die Attach Film).

DETAILED DESCRIPTION

Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments. In the embodiments, “an upper direction” or “a lower direction” refers to a relative direction when a direction perpendicular to a surface of a wiring substrate on which semiconductor chips are provided is assumed as “an upper direction”. Therefore, the term “upper direction” or “lower direction” occasionally differs from an upper direction or a lower direction based on a gravitational acceleration direction. It should be noted that the drawings are schematic or conceptual, and the relationship between the thickness and the width in each element and the ratio among the dimensions of elements do not necessarily match the actual ones. Even if two or more drawings show the same portion, the dimensions and the ratio of the portion may differ in each drawing. In the present specification and the drawings, elements identical to those described in the foregoing drawings are denoted by like reference characters and detailed explanations thereof are omitted as appropriate.

A semiconductor device according to the present embodiment includes: a substrate; a first semiconductor chip; a second semiconductor chip; a bonding layer; and a member. The substrate has a first surface. The first semiconductor chip is provided on the first surface. The second semiconductor chip is provided above the first semiconductor chip, has a second surface facing the first surface and the first semiconductor chip, and coats the first semiconductor chip as viewed from a direction substantially perpendicular to the first surface. The bonding layer is provided between the second surface and both the first surface and the first semiconductor chip. The member is provided on at least part of an outer periphery of the bonding layer as viewed from the direction substantially perpendicular to the first surface.

First Embodiment

FIG.1is a cross sectional view showing an example of a configuration of a semiconductor device1according to a first embodiment. The semiconductor device1includes a wiring substrate semiconductor chips20and30to33, bonding layers40to43, a member50, a bonding layer60, bonding wires90, and a sealing resin91. An example of the semiconductor device1is a package of NAND flash memories.

The wiring substrate10may be a printed circuit board or an interposer including wiring layers (not shown) and insulating layers (not shown). For the wiring layers, there is used, for example, a low-resistance metal such as copper, nickel, or an alloy of these. For the insulating layers, there is used, for example, an insulative material such as a glass epoxy resin. The wiring substrate10may have a multilayer wiring structure configured by stacking a plurality of wiring layers and a plurality of insulating layers. Like an interposer, for example, the wiring substrate10may have through electrodes (not shown) penetrating its front surface and back surface.

On a surface F10aas a front surface (upper surface) of the wiring substrate10, there are provided pads10p1and10p2connected to the wiring layers. The surface F10ais an example of a first surface.

Metal bumps13are provided on a back surface (lower surface) of the wiring substrate10. The metal bumps13are provided for electrically connecting not-shown other components to the wiring substrate10.

The semiconductor chip20is provided on the front surface (surface F10a) side of the wiring substrate10. The semiconductor chip20is bonded to the wiring substrate10via a bonding layer21. An example of the semiconductor chip20is a controller chip which controls a memory chip. On a surface (front surface), of the semiconductor chip20, that is on the opposite side to a surface thereof facing the wiring substrate10, not-shown semiconductor elements are provided. For example, the semiconductor elements may be CMOS (Complementary Metal Oxide Semiconductor) circuits constituting the controller. Bonding wires22electrically connect the pads10p2provided on the front surface of the wiring substrate10to pads (not shown) provided on the front surface of the semiconductor chip20.

The semiconductor chip30is bonded to an upper portion above the semiconductor chip20via the bonding layer40. An example of the semiconductor chip30is a memory chip including a NAND flash memory. The semiconductor chip30has semiconductor elements (not shown) on its front surface. For example, the semiconductor elements may be a memory cell array and its peripheral circuit (CMOS circuit). The memory cell array may be a three-dimensional memory cell array having a plurality of memory cells three-dimensionally arranged. Moreover, the semiconductor chip31is bonded onto the semiconductor chip30via the bonding layer41. The semiconductor chip32is bonded onto the semiconductor chip31via the bonding layer42. The semiconductor chip33is bonded onto the semiconductor chip32via the bonding layer43. As with the semiconductor chip30, an example of each of the semiconductor chips31to33is a memory chip including a NAND flash memory. The semiconductor chips30to33may be the same memory chips. In the figure, the semiconductor chips30to33as four memory chips, along with the semiconductor chip20as a controller chip, are stacked. Nevertheless, the number of stacked semiconductor chips may be three or less, or five or more.

More in detail, the semiconductor chip30has a surface F30a, a surface F30bthat is on the opposite side of the surface F30a, and the bonding layer40on the surface F30a. The surface F30ais a surface that faces both the surface F10aof the wiring substrate10and the semiconductor chip20. The surface F30ais an example of a second surface. The surface F30bis an example of a third surface.

Moreover, the bonding layer40is thicker than the bonding layers41to43. The bonding layer40is provided such that the semiconductor chip20and the bonding wires22are embedded therein (so as to coat the semiconductor chip20and the bonding wires22). Namely, the bonding layer40is provided between the surface F30aof the semiconductor chip30and both the surface F10aof the wiring substrate and the semiconductor chip20. Moreover, lateral surfaces of the bonding layer40are approximately parallel to lateral surfaces of the semiconductor chip30existing between the surface F30aand the surface F30b. Moreover, a width of the bonding layer40is approximately equal to a width of the semiconductor chip30. Notably, each width means a width in the direction substantially parallel to the surface F10a. This is because a wafer on which a bonding layer is pasted is divided into separate pieces by dicing as described later with reference toFIG.3AtoFIG.3E.

The member50is provided on the outer periphery of the bonding layer40. The member50is bonded to the wiring substrate10via the bonding layer60. Notably, details of arrangement of the member50is described later with reference toFIG.2. Moreover, in the example shown inFIG.1, a height of an upper surface of the member50is approximately equal to a height of the surface F30aof the semiconductor chip30.

Each bonding wire90is connected to any pads of the wiring substrate10and the semiconductor chips30to33. For connection with the bonding wires90, the semiconductor chips30to33are stacked with displacements for the pads.

More in detail, the bonding wires90afford electrical connection between the pads10p1provided on the front surface of the wiring substrate10and pads (not shown) provided on the front surfaces of the semiconductor chips30to33.

Furthermore, the sealing resin (resin layer)91seals the semiconductor chips20and30to33, the bonding layers40to43and the member50, the bonding wires90, and the like. Thereby, the semiconductor device1is configured as one semiconductor package of the plurality of semiconductor chips20and30to33on the wiring substrate10.

FIG.2is a plan view showing an example of positional relationship of the wiring substrate10, the semiconductor chip20, the bonding layer and the member50inFIG.1.FIG.2is a view as a plane parallel to the surface F30ashown inFIG.1(see the A-A line inFIG.1) which is viewed from an upper portion above the view plane ofFIG.1.

An outer edge of the bonding layer40(outer edge of the semiconductor chip30) as viewed from a direction substantially perpendicular to the surface F10ais outward of an outer edge of the semiconductor chip20. Namely, the semiconductor chip30is provided so as to coat (cover) the semiconductor chip20as viewed from the direction substantially perpendicular to the surface F10a.

The member50is provided on the outer periphery of the bonding layer40as viewed from the direction substantially perpendicular to the surface F10a. More in detail, the member50is provided so as to cover the outer periphery of the bonding layer40along the outer periphery of the bonding layer40. Namely, the member50is provided between the bonding layer40and the sealing resin91.

Moreover, the member50is composed of a material having higher strength than the sealing resin91. Examples of the strength include a tensile strength, a bending strength, and a hardness. The tensile strength of the member50is higher than 10 kgf/mm2, for example. This can restrain a crack from arising.

An example of the bonding layer40is a thermosetting adhesive agent. An example of a main component of the bonding layer40is an acrylic resin. An example of a thermal expansion coefficient of the bonding layer40is about 70 ppm/° C. at ambient temperature, and about 120 ppm/° C. at 260° C. Notably, a structure material of the bonding layer40is not limited to the above.

An example of the sealing resin91is a thermosetting resin. An example of a main component of the sealing resin91is an epoxy resin. An example of a thermal expansion coefficient of the sealing resin91is about 9 ppm/° C. at ambient temperature, and about 36 ppm/° C. at 260° C. An example of a bending strength of the sealing resin91is about 170 MPa at 30° C., and about 19 MPa at 260° C. Notably, a structure material of the sealing resin91is not limited to the above.

The member50is composed, for example, of silicon (Si). Notably, a structure material of the member50is not limited to silicon. For example, it only has to be a material having higher strength than the sealing resin91. Moreover, the member50is still preferably composed of a material that can be processed into any shape. The member50may be composed of a resin, for example.

Next, a manufacturing method of a semiconductor device is described.

FIG.3AtoFIG.3Eshow steps of dividing a wafer W on which the bonding layer40is pasted into separate semiconductor chips30.FIG.4AtoFIG.4Fshow steps of providing the semiconductor chips20and30and the member50on the wiring substrate10.

FIG.3AtoFIG.3Eare views showing an example of a manufacturing method of the semiconductor device1according to the first embodiment.

As shown inFIG.3A, a silicon wafer W (hereafter called wafer) on which a plurality of semiconductor parts are formed is prepared. The wafer W includes a third surface including the semiconductor parts and a fourth surface separate from the third surface in the Z-axis direction. Next, a surface protecting tape110is bonded onto the third surface of the wafer W.

Next, as shown inFIG.3B, the wafer W is reversed. Then, the fourth surface of the wafer W is ground using a grinding stone120, which is then retracted. This step is what is called a BSG (Back Side Grinding) step.

Next, as shown inFIG.3C, the wafer W is reversed. Then, the fourth surface of the wafer W is bonded to a bonding resin pasted on a dicing ring130. An example of the bonding resin is a DAF (Die Attach Film)140a.

Next, as shown inFIG.3D, the surface protecting tape110is peeled off from the third surface of the wafer W.

Next, as shown inFIG.3E, the wafer W is diced using a blade150. Dicing lines160are formed on the wafer W. Each dicing line160is formed along the X-axis direction and the Y-axis direction. The wafer W is separated into the plurality of semiconductor chips30.

Notably, the DAF140aas a second bonding layer is divided together with the wafer W into separate pieces to be bonding layers40each as a first bonding layer.

FIG.4AtoFIG.4Fare views showing an example of a manufacturing method of the semiconductor device1according to the first embodiment. The left side in each ofFIG.4AtoFIG.4Fshows a top view. The right side in each ofFIG.4AtoFIG.4Fshows a lateral view.

As shown inFIG.4A, the semiconductor chip20is provided (mounted) on the surface F10aof the wiring substrate10via the bonding layer21. The bonding layer21is pasted on the semiconductor chip20in advance. Thereafter, the bonding wires22are formed. Notably, the bonding layer21, the bonding wires22, the pads10p2, and the like are omitted.

Next, as shown inFIG.4B, the semiconductor chip30obtained by the division into separate pieces in the steps ofFIG.3AtoFIG.3Eis provided on the surface F10aof the wiring substrate10via the bonding layer40. More in detail, the semiconductor chip30is provided such that the semiconductor chip20and the bonding wires22are embedded in the bonding layer40provided on the surface F30a(such that the bonding layer40coats the semiconductor chip20and the bonding wires22).

Notably, as mentioned above, the lateral surfaces of the bonding layer40are approximately parallel to the lateral surfaces of the semiconductor chip30existing between the surface F30aand the surface F30b. Moreover, the width of the bonding layer40is approximately equal to the width of the semiconductor chip30.

Next, as shown inFIG.4C, a member51is provided on the surface F10aof the wiring substrate10via the bonding layer60. The bonding layer60is pasted on the member51in advance. For example, the member51is provided along one side (short side) of the semiconductor chip30. The member51is a part of the member50.

Next, as shown inFIG.4D, a member52is provided on the surface F10aof the wiring substrate10via the bonding layer60. The bonding layer60is pasted on the member52in advance. For example, the member52is provided along one side (long side) of the semiconductor chip30. The member52is a part of the member50.

Next, as shown inFIG.4E, a member53is provided on the surface F10aof the wiring substrate10via the bonding layer60. The bonding layer60is pasted on the member53in advance. For example, the member53is provided along one side (short side) of the semiconductor chip30. The member53is a part of the member50.

Next, as shown inFIG.4F, a member54is provided on the surface F10aof the wiring substrate10via the bonding layer60. The bonding layer60is pasted on the member54in advance. For example, the member54is provided along one side (long side) of the semiconductor chip30. The member54is a part of the member50.

As shown inFIG.4F, the members51to54are provided along all of the sides of the semiconductor chip30(the outer periphery of the bonding layer40). The members51to54correspond to the member50shown inFIG.2. Notably, the order for providing the member51to54is not limited to that in the example shown inFIG.4CtoFIG.4F.

As above, according to the first embodiment, the member50is provided on the outer periphery of the bonding layer40as viewed from the direction substantially perpendicular to the surface F10a. Since the member50is composed of the material having higher strength than the sealing resin91, a crack can be restrained from arising due to tensile concentration, and the influence of a crack can be reduced.

Comparative Example

FIG.5is a cross sectional view showing an example of a configuration of a semiconductor device1aaccording to a comparative example. The comparative example is different from the first embodiment in that the member50and the bonding layer60are not provided.

There is occasionally a case where a crack C arises in the example shown inFIG.5. A region between the bonding layer40and the sealing resin91can become an origin of the crack C arising due to stress concentration caused by temperature change. In the example shown inFIG.5, the crack C possibly arises with a boundary portion among the semiconductor chip30, the bonding layer40, and the sealing resin91being as the origin.

When the crack C advances to the wiring substrate10, this results in a possibility of affecting wiring in the wiring substrate10, which can cause electrical failures such as disconnection defects.

In contrast, with the first embodiment, by providing the member contact between the bonding layer40and the sealing resin91can be restrained. The member50higher in strength than the sealing resin91is provided on the periphery of the bonding layer40, that is, between the bonding layer40and the sealing resin91, and thereby, a crack can be restrained from arising.

Notably, in the example shown inFIG.4F, the members51to54are provided with almost no gaps therebetween. Nevertheless, the member50does not have to be provided on part of the outer periphery of the bonding layer40. Accordingly, the member50may be provided on at least part of the outer periphery of the bonding layer40as viewed from the direction substantially perpendicular to the surface F10a.

For example, there is a possibility that the influence of stress due to temperature change (expansion) varies due to the material, the structure, the shape, or the like of the bonding layer40. As a result, this occasionally results in a case where a tendency of a crack arising varies depending on the position of contact between the bonding layer40and the sealing resin91. In such a case, the member50only has to be arranged at the positions where a crack tends to arise, and the member does not have to be arranged at the other places. For example, when it is known in advance that a defect such as a crack tends to arise at the portions of the short sides of the semiconductor chip30inFIG.4BtoFIG.4F, the members51and53arranged along the short sides only have to be provided, and the members52and54do not have to be provided.

FIG.6is a plan view showing an example of positional relationship between the wiring substrate10, the semiconductor chip30, and the member50according to a modification.

The wiring substrate10occasionally has a region A1inside which wiring is provided, and a region A2inside which wiring is not provided. InFIG.6, the region A2is the region, on the wiring substrate10, other than the region A1. Even when a crack advances into the region A2, disconnection defects do not arise. Accordingly, the member50does not have to be provided on an outer periphery, of the bonding layer40, that is on the region A2side (on a side, of the semiconductor chip30, that is on the region A2side) as viewed from the direction substantially perpendicular to the surface F10a. This can accordingly reduce material costs of the member50. In the example shown inFIG.6, the region A2is on a side where the left short side of the semiconductor chip20exists. Accordingly, the member50is not provided on the side where the left short side of the semiconductor chip20exists.

Second Embodiment

FIG.7is a cross sectional view showing an example of a configuration of a semiconductor device1according to a second embodiment. As compared with the first embodiment, the second embodiment has a different height of the upper surface of the member50.

The height of the upper surface of the member50is larger than the height of the surface F30aof the semiconductor chip30. More in detail, the height of the upper surface of the member50is a height of the surface F30bof the semiconductor chip30. The member50functions as a spacer that supports the semiconductor chip31provided on the semiconductor chip30. Thereby, the semiconductor chip31can be supported when the bonding wires90are formed onto the semiconductor chip31. As a result, the influence of load and stress exerted during wire bonding can be reduced, and a crack can be restrained from arising.

The other configurations of the semiconductor device1according to the second embodiment are similar to the corresponding configurations of the semiconductor device1according to the first embodiment, and their detailed description is omitted. The semiconductor device1according to the second embodiment can attain the similar effects to those in the first embodiment.

Third Embodiment

FIG.8is a cross sectional view showing an example of a configuration of a semiconductor device1according to a third embodiment. As compared with the first embodiment, the third embodiment has a different height of the upper surface of the member50.

The height of the upper surface of the member50is lower than the surface F30aof the semiconductor chip30. In this case, the volume of the member50can be reduced, and material costs can be reduced.

Even when the crack C shown inFIG.5arises, by the member50covering the surface F10aof the wiring substrate10, the crack C can be caused not to reach the wiring substrate10. Namely, the member50according to the third embodiment functions as a wiring protection member for the wiring substrate10. Thereby, the influence of the crack C can be reduced.

For example, the member50is provided from the outer periphery of the bonding layer40to the pads10p1. In order to protect the wiring, the member50is preferably provided over a wider range in parallel directions to the surface F10a. Nevertheless, in order not to be in contact with the bonding wires90, the member50is preferably provided behind the pads10p1from the directions, among those, where the pads10p1exist (the right-left directions in the view plane ofFIG.8).

The other configurations of the semiconductor device1according to the third embodiment are similar to the corresponding configurations of the semiconductor device1according to the first embodiment, and their detailed description is omitted. The semiconductor device1according to the third embodiment can attain the similar effect to those in the first embodiment.