Amplifiers

This application relates to an amplifier selectively operable in first or second modes. The first mode is a BTL mode with first and second output drivers (103p, 103n) both active to generate respective driving signals that vary with an input signal. The second mode is an SE mode, where the first output driver (103p) is active to generate a driving signal at and the output of the second driver (103n) is held constant. A controller (201) selectively controls the mode based on an indication of output signal amplitude. In the first mode, a ratio of magnitude of the two driving signals varies with the indication of output signal amplitude, i.e. the magnitudes of the two driving signals may vary so as to be not equal.

TECHNICAL FIELD

The field of representative embodiments of this disclosure relates to methods, apparatus and/or implementations concerning or relating to amplifiers, in particular amplifiers for driving loads such as transducers.

BACKGROUND

Many electronic devices include amplifier circuits for generating driving signals for driving a transducer, for instance for driving audio signals into an audio output transducer such as a loudspeaker.

In some applications, the amplifier circuit may be configured to drive the transducer in a bridge-tied-load (BTL) configuration. In a BTL configuration, both sides of the load are driven with respective driving signals that are complementary to one another so as to apply the relevant driving voltage across the load.

FIG. 1illustrates one example of an amplifier circuit100for driving a transducer101, in this example a speaker, in a BTL configuration.FIG. 1illustrates the amplifier circuit has an amplifier stage102that, in this example, comprises respective positive and negative drivers103pand103nfor driving respective positive and negative output terminals104pand104n, coupled to opposite sides of the transducer101, with complementary driving signals Vp and Vn, based on an input signal Sin, so as to apply an output signal Vout across the load101.

In the example ofFIG. 1, the amplifier stage102receives differential inputs, Sinp and Sinn, and amplifies these differential inputs to provide the differential driving signals Vp and Vn. In some implementations, the amplifier circuit100may receive an input signal Sin and derive the differential signals, Sinp and Sinn, therefrom, for instance as illustrated inFIG. 1by using the input signal Sin as the positive signal component and providing an inverter105to invert the input signal Sin to provide the negative signal component Sinn. It will be understood, however, that other arrangements are possible or amplifier circuit100may receive a differential input.

Each of the positive and negative drivers103pand103nmay be an amplifier which receives supply voltages VH and VL, which could, for instance, be a supply voltage and ground, or positive and negative supply voltages. In some applications the drivers103pand103nmay be implemented as class-D amplifiers, which, as will be understood by one skilled in the art, may switch between the two supply voltages with a duty cycle based on the respective input Sinp or Sinn.

The BTL arrangement of the amplifier circuit100thus drives both side of the load, e.g. transducer101, with driving voltages that vary with the input signal Sin. This can provide advantages in terms maximum power output compared to the alternative single-ended configuration, in which a variable driving voltage is applied to one side of the load transducer only, and the other side of the transducer is tied to a reference voltage, which for audio transducers and the like, is a midpoint voltage.

In a BTL configuration one side of the load may be driven to near VH (less appropriate headroom) whilst the other side of the load may be to near VL. Thus, the maximum magnitude of the output voltage could be close to the magnitude of the supply voltage, i.e. VH−VL. In a single-ended configuration one side of the load is held at a midpoint voltage, and thus the maximum magnitude of the output voltage is equal to half the magnitude of the supply voltage (less headroom).

In at least some applications it may be desirable for the amplifier circuitry to be operable to drive transducers with relatively high power driving voltages, and thus a BTL configuration may be implemented.

In at least some applications, however, power efficiency is also desirable, especially for portable and/or battery powered devices, where power consumption is an important consideration for operating life.

SUMMARY

Embodiments of the present disclosure relate to improved amplifier arrangements and methods of amplification. Embodiments may, in particular, relate to an amplifier arrangement operable in a BTL configuration but which may offer power efficiency advantages.

According to an aspect of the disclosure there is provided an amplifier circuit for generating an output signal between first and second output nodes based on a received input signal, the amplifier circuit comprising:

first and second output drivers; and

a controller for selectively controlling the amplifier circuit in a first mode or a second mode based on an indication of output signal amplitude; wherein:

in the first mode the first and second output drivers are both active to generate respective first and second driving signals that each vary with the input signal at the first and second output nodes respectively; and

in the second mode the first output driver is active to generate a first driving signal at the first output node that varies with the input signal and the second output node is held at a constant voltage;

and wherein in the first mode a ratio of magnitude of the second driving signal compared to magnitude of the first driving signal varies with the indication of output signal amplitude.

In some examples the controller is configured such that, when operating in the first mode, the ratio of magnitude of the second driving signal compared to magnitude of the first driving signal varies within a range from zero to one and increases with increasing indication of output signal amplitude. The controller may be configured to, in the first mode, minimise the ratio of magnitude of the second driving signal compared to the magnitude of the first driving signal.

In some example the first output driver is located in a first signal path and the second output driver is located in a second signal path and the controller may be configured to control the ratio of magnitude of the second driving signal compared to magnitude of the first driving signal by controlling gains applied in the first and second signal paths.

In some examples the indication of output signal amplitude comprises a gain setting indicating a gain to be applied by the amplifier circuit.

Additionally or alternatively, in some examples the indication of output signal amplitude comprises an indication of amplitude of the input signal. In which case, the controller may comprise an envelope detector configured to receive a version of the input signal and determine the amplitude of the input signal. The amplifier circuit may comprise at least one element having a propagation delay located in a signal path upstream of at least one of the first and second output drivers and the envelope detector may receive the version of the input signal from upstream of the delay element.

In some examples the controller may be further configured to selectively control a bias applied to at least the first output driver based on the indication of the amplitude of the output signal. The controller may be configured such that a lower bias current is applied to the first output driver in the second mode than in the first mode. The controller may be configured such that a bias current applied to the first output driver in the first mode increases with increasing output signal amplitude.

In some examples the amplifier circuit may comprise a voltage regulator which is activate in the second mode to regulate the voltage at the second output node. The voltage regulator may comprise at least one of: a DC-DC converter and a charge pump.

In some examples the controller may be configured to disable the second output driver when operating in the second mode.

In some examples the first and second output drivers each comprise a respective class-D amplifier.

The amplifier circuit may, in use, further comprise a load transducer coupled between the first and second output nodes. In some examples, the load transducer may comprise a loudspeaker.

Aspects also relate to an electronic device comprising the amplifier circuit of any of the embodiments described herein.

In a further aspect there is provided an amplifier circuit for generating an output signal between first and second output nodes based on a received input signal, the amplifier circuit comprising:

first and second output drivers;

the amplifier circuit being operable in a first mode in which the first and second output drivers are both active to generate respective first and second driving signals that each vary with the input signal at the first and second output nodes respectively; and wherein, in the first mode, a ratio of magnitude of the second driving signal compared to magnitude of the first driving signal varies with an indication of output signal amplitude.

In a further aspect there is provided an amplifier circuit comprising:

a first signal path comprising a first amplifier;

a second signal path comprising a second amplifier; and

a controller for selectively operating the circuit in:

a first mode, in which both the first amplifier and second amplifier are active to drive first and second output nodes with respective first and second driving signals that each vary with the input signal; and

a second mode in which the first amplifier is active to drive the first output node with the first driving signal that varies with the input signal and the second output node is held at a constant voltage;

wherein the controller operates in the first mode when an indication of output signal amplitude is within a first range and where the controller controls a gain of the second path to reduce with reducing indication of output signal amplitude over said first range whilst maintain or increasing a gain of the first path.

In a further aspect there is provided an amplifier circuit comprising:

a first signal path comprising a first amplifier;

a second signal path comprising a second amplifier; and

a controller for selectively operating the circuit in:

a first mode, in which both the first amplifier and second amplifier are active to drive first and second output nodes with respective first and second driving signals that each vary with the input signal; and

a second mode in which the first amplifier is active to drive the first output node with the first driving signal that varies with the input signal and the second output node is held at a constant voltage; and

wherein in the first mode a gain of the first signal path is controlled to be constant at a first value and a gain of the second signal path is selectively variable within a range of gain values up to said first value based on a gain control signal; and

in the second mode the gain of the first signal path is selectively variable within a range of gain values up to said first value based on gain control signal.

Unless expressly indicated to the contrary, any of the various features of the various implementations discussed herein may be implemented together with any one or more of the other described features in any and all suitable combinations.

DETAILED DESCRIPTION

The description below sets forth example embodiments according to this disclosure. Further example embodiments and implementations will be apparent to those having ordinary skill in the art. Further, those having ordinary skill in the art will recognize that various equivalent techniques may be applied in lieu of, or in conjunction with, the embodiments discussed below, and all such equivalents should be deemed as being encompassed by the present disclosure.

As discussed above with reference toFIG. 1, a bridge-tied-load (BTL) configuration may be used in some applications to drive a load, such as a transducer. In a BTL configuration both side of the load transducer are driven with driving signal. Thus with two drivers103pand103nreceiving supply voltages VH and VL, one side of the transducer can be driven to near VH whilst the other side of the transducer is driven to near VL (less amplifier headroom), thus applying almost the full voltage magnitude |VH−VL| across the load transducer as the output signal Vout. For a single-ended driving configuration one side of the transducer is held at a midpoint voltage Vmid, equal to (VH−VL)/2, and thus the maximum voltage of the output signal that can be applied is near half the full voltage magnitude of the difference between the supply voltages (again less headroom). The BTL configuration can thus be advantageous for driving a load with a higher power driving signal than a single-ended configuration for a given voltage supply.

However, whilst a BTL configuration can be advantageous to provide an output driving signal with an amplitude that is a significant proportion of the supply voltage, at lower output signal levels a BTL configuration may be relatively inefficient in terms of power efficiency. In general, as will be understood by one skilled in the art, the efficiency of a linear amplifier may be characterised as being proportional to Vsig/Vdd, where Vsig is amplitude of the output of the amplifier and Vdd is the magnitude of the supply voltage (i.e. VH−VL). In general, therefore, any amplifier where the output amplitude is significantly lower than the supply voltage is operating inefficiently, but for the BTL configuration as each output driver103pand103ngenerates a driving signal Vp or Vp with half the amplitude of the overall driving signal.

Also, a BTL amplifier circuit may also be implemented with class-D amplifiers for the drivers103pand103n. Class-D amplifiers operate to switch between the supply voltages with a duty-cycle controlled based on the input signal. Switching losses mean that class-D amplifiers are relatively inefficient at low power signal levels.

Embodiments of the present disclosure relate to amplifier circuitry and methods of operation thereof, where the amplifier circuitry comprises an output stage that is operable in a BTL configuration to drive a load, but which is also operable in a single-ended mode of operation and which is configured to dynamically transition between the modes of operation in use. The mode of operation may be controlled based on an indication of the output signal amplitude.

If the indication of output signal amplitude indicates that the required output signal amplitude is relatively low, and within the output range of just one of the drivers, then the amplifier circuit may operate in the single-ended mode. In this mode, one of the drivers of the output stage provides a driving signal which provides the full voltage excursion for the required output signal, with respect to a defined quiescent voltage level, typically a midpoint voltage Vmid. The other driver may then be disabled and the voltage at the relevant output may be held at the midpoint voltage. Disabling one of the drivers and using the other to provide the full voltage excursion thus increases the efficiency of the amplifier circuit and, where the drivers are class-D amplifiers, avoid the switching losses associated with one of the drivers.

If, however, the indication of output signal amplitude indicates that the required output signal could exceed the output range of just one of the drivers, then the amplifier circuit can operate in a BTL configuration and apply time-varying driving signals based on the input signal to both sides of the load.

FIG. 2illustrates an example of an amplifier circuit200according to an embodiment, in which similar components to those discussed with reference toFIG. 1are identified using the same reference numerals.

The amplifier circuit200ofFIG. 2comprises an amplifier stage202. The amplifier stage202has output terminals104pand104nfor connecting, in use, to both side of a load101, which may, for example, be an audio output transducer such as a loudspeaker. The amplifier stage202comprises drivers103pand103noperable to generate respective driving signals Vp and Vn at the respective output nodes104pand104n. The drivers103pand103nmay each comprise a class-D amplifier or driver.

The amplifier circuit200according to an embodiment also comprises a controller201for controlling a mode of operation of the circuit, e.g. of the amplifier stage202. The controller201may be operable to selectively control the circuit200in a first mode, which may be referred to as a BTL (bridge-tied-load) mode. In the first mode both the drivers103pand103nmay be operable to generate respective driving signals based on the input signal Sin. Thus, in first or BTL mode of operation, the voltages Vp and Vn at both output nodes104pand104nmay vary with the input signal Sin. The voltage Vp and Vn may vary inversely from one another with respect to the midpoint voltage, but as will be described below, may vary asymmetrically or unequally.

The controller201is also operable to selectively control the circuit in a second mode, which may be referred to a SE (single-ended) mode. In the second mode, a driving signal based on the input signal Sin is generated at one of the output nodes only, and the other output node is held substantially constant, generally at a voltage which corresponds to the quiescent level of the driving signal, e.g. a midpoint voltage Vmid.

In the example ofFIG. 2, the driver103nmay be deactivated or disabled in the second (SE) mode of operation and the voltage at output node104nheld at the midpoint voltage Vmid, e.g. by activating a voltage regulator203as will be discussed in more detail below. In this mode, the voltage Vp at output node104pmay thus vary with the input signal Vin, but the voltage Vn at the output node104nmay be held substantially constant.

The controller201may generate one or more control signals Scn for controlling whether or not the driver103nis enabled and whether the voltage regulator202is active or not. The control signal(s) Scn may also control one or more parameters of the negative signal path of the amplifier stage102when active in the BTL mode, in particular a gain applied in the negative signal path. The controller may also generate at least one control signal Scp control one or more parameters of the positive signal path, in particular a gain applied in the positive signal path. In some embodiments the controller201may also control a level of bias applied to at least the driver103p.

The controller201is configured to selectively control the mode of operation, i.e. BTL or SE mode, based on an indication of the amplitude of the output signal Vout. The controller201may be configured to operate in the SE mode if the indication of the amplitude of the output signal Vout indicates that the required voltage excursion for the output signal Vout may be generated using just the driver103p.

For instance, consider that each of the drivers103pand103nare operable to generate a driving signal Vp or Vn in an output range of 0V to +1.0V. It will of course be understood that this output range is chosen merely as an illustrative example. In the BTL mode of operation the output signal Vout may vary between +1.0V (with Vp=+1.0V, Vn=0V) and −1.0V (Vp=0V, Vn=+1.0V). The quiescent signal level, Vout=0V, in this example corresponds to Vp=Vn=Vmid=0.5V.

In the SE mode the voltage Vn would be held at Vmid=0.5V. In this mode the output signal Vout may vary between +0.5V (with Vp=+1.0V) and −0.5V (with Vp=0V).

Thus, if the indication of the output signal amplitude indicates that, for this example, the amplitude of the output signal will be below 0.5V, the controller may be configured to control the circuit in the SE mode of operation, with the voltage Vn at the output node104nheld substantially constant, e.g. by regulator203. This may allow driver103nto be disabled or suspended.

If, however, the indication of the output signal amplitude indicates that the output signal amplitude is, or may be, above 0.5V, then the circuit may operate in the BTL mode of operation and the driver103nmay be enabled so that the voltage Vn at the output node104nalso varies with the input signal Sin to provide the required output signal Vout.

In some examples the indication of the output signal amplitude may be an indication of an overall gain to be applied by the amplifier circuit between the input signal Sin and the output signal Sout, e.g. a system or user controlled volume setting VOL or the like.

The volume setting may define the maximum voltage excursion, i.e. maximum amplitude, of the output signal Vout for a full-scale input signal. For example, consider that amplifier circuit200has a controllable volume in the range 0 to 1 that defines the ratio between the input signal (normalised within the available input signal range) and the output signal (normalised within the available output signal range). If the volume setting were set to 1, then a full-scale input signal could lead to a full-scale output signal, which would require BTL operation. However, at a volume setting below 0.5, even a full-scale input signal may use less than half of the available output range. Such a volume setting could thus be used to control the mode of operation and, as illustrated inFIG. 2, the controller may receive a volume signal VOL indicating the volume setting. Note in this case the volume setting is effectively used as an indication of the what the output signal amplitude could be, for a full-scale input signal.

In some examples, however, the indication of the amplitude of output signal may be an indication of the amplitude of the input signal. In some examples the controller may determine such an indication of amplitude from the input signal. The output signal Vout is generated based on the input signal Sin and thus the level of the input signal, together with the overall gain of the amplifier circuit, defines the level of the output signal.

The controller201may thus be configured to receive a version of the input signal Sin and may determine an amplitude or envelope value for the input signal.

FIG. 3illustrates an example of an amplifier circuit300according to an embodiment which shows that the controller201receives a version of the input signal Sin. In this example the controller201comprises an envelope detector301which generates an indication of the envelope or amplitude of the input signal Sin.

In some examples the envelope detector301may comprise a peak detector that determines the peak absolute magnitude values of the input signal as it varies, within some defined time frame. The indication of the peak absolute magnitude could be used directly as an indication of the signal amplitude or envelope, but in some implementations the envelope detector301may comprise an envelope tracker configured to track the envelope or amplitude value of the input signal. The envelope tracker may have a fast attack time constant, so as to respond rapidly to any increases in signal amplitude, but may have a slower decay time constant so as to avoid rapid variations in envelope level.

It will be understood that envelope trackers and the like are used to determine input signal amplitude in other applications, for instance for control of supply voltages in class G amplifiers, or for gain control for dynamic range extension for ADCs and DACs. Any of the signal monitoring techniques or apparatus used for such other applications could be employed in embodiments of the present disclosure to monitor the input signal and the amplitude thereof.

The indication of the amplitude of the input signal Sin may be supplied to a processor302of the controller201which is configured to determine the mode of operation of amplifier circuit based on the amplitude level. For example, if the amplitude of the input signal is below a threshold, which means that the output signal is within the output range of driver103p, then the processor302may operate the circuit in the SE mode, with the driver103ndisabled and the regulator203activated to maintain the voltage Vn at the output node at the midpoint voltage. If, however, the amplitude of the input signal increases above such a threshold, then the processor302may operate the circuit in the BTL mode and activate the driver103nand deactivate the voltage regulator203.

In some embodiments, if any variable gain is applied downstream of where the input signal Sin is monitored, for instance some user or system controlled volume VOL, the processor302may take such gain or volume into account in determining the mode of operation.

To allow the controller201time to determine the amplitude level of the input signal and the required operating mode and have sufficient time to active the driver103n, when switching from the SE to BTL mode of operation, or activate the regulator203, when switching from BTL to SE mode, the controller201may be implemented as part of a look-ahead arrangement. The controller201may thus be configured to monitor the input signal Sin before some element in the downstream signal path with a signal path propagation delay or latency, so that the controller201has time to react to any change in signal amplitude before that change in signal amplitude has propagated to the drivers103pand103n.FIG. 3illustrates that the amplifier stage202comprises at least one DAC (digital-to-analogue converter) and, in the example ofFIG. 3, there are respective DACs303pand303nin each of the positive and negative signals paths of the amplifier stage202so as to provide respective analogue input signals for the drivers103pand103n. There will be some processing delay or latency associated with the DACs303pand303n, e.g. due to interpolation, sample-rate conversion etc. By monitoring the input signal prior to the DACs303pand303n, the controller201may exploit some inherent delays in the main signal path to provide at least part of a look ahead, as well as allowing the controller201to monitor the input signal Sin in the digital domain. A DAC is just one example of an element with a signal path propagation latency however, and there may be additional and/or alternative delay elements in the signal path, which could include at least one dedicated delay element304that is present only to provide a suitable propagation delay.

In order to change the mode of operation, the controller201can enable or disable the driver103nwhilst also deactivating or activating the regulator203. For a class-D amplifier the driver may be disabled by stopping switching of the output stage of the class-D amplifier. In some examples various parts of the class-D amplifier may be powered down when the driver103nis disabled, although some parts of the class-D amplifier may be kept powered so as to allow the amplifier to be enabled more quickly when required.

In addition, the controller201may control the conversion gains of the positive and/or negative signal paths of the amplifier stage202. Advantageously the controller may be operable so that, when operating in the BTL mode, different gains may be applied in the positive and negative signal paths of the amplifier stage depending on the indication of output signal amplitude. In other words, when operating in the BTL mode the magnitude of the positive and negative driving signals may be different from one another depending on the indication of signal amplitude. This is different to conventional BTL operation, where the positive and negative driving signals would be equal and opposite from one another. Varying the gains applied in the positive and negative signal paths of the amplifier stage202, and hence the relative magnitudes of the voltages Vp and Vn, and hence their relative contribution to the output signal Vout, can be advantageous in transitioning between the modes of operation.

Consider the amplifier circuit300is operating in the BTL mode and the input signal Sin has a certain signal level, say S1. In the BTL mode, the voltage Vp depends on the input signal Sin, so the driving voltage Vp is equal to Gp*S1, where Gp is the gain of the positive signal path. Equally, in the BTL mode, the voltage Vn depends on the input signal Sin, so the driving voltage Vn is equal to −Gn*S1, where Gn is the gain of the negative signal path. The output signal Vout is equal to Vp−Vn=(Gp+Gn)*S1.

Conventionally, in BTL operation the positive and negative driving voltages are equal and opposite, i.e. Vp=Vn, and thus the positive and negative signal paths have the same gain as one another, i.e. Gp=Gn.

In the SE mode, however, the voltage Vn at the output node104nis held constant at Vmid. Thus, the gain Gn of the negative path is effectively zero. In this mode the driver103pmust generate the driving signal Vp to provide all the required voltage excursion of the output signal Vout, rather than just half the voltage excursion as in conventional BTL operation. If the controller were to swap between an SE mode of operation, where the driving signal Vp provides all the required voltage excursion, to a conventional BTL mode where the driving signals Vp and Vn are equal and opposite, this would require a step change in gain in both the positive and negative signal paths on a change of mode, which may result in unwanted artefacts or the like.

In embodiments of the present disclosure, the controller201may control the amplifier stage202in the BTL mode so that the contribution to the output signal from the positive and negative signals paths are unequal, for at least some indications of output signal amplitude. In particular, the controller201may be operable, in the BTL mode, to reduce the relative contribution to the output signal of the voltage Vn at the output node104n(i.e. the voltage that will be held constant in the SE mode) for lower amplitudes of the output signal. In essence, as the indication of the amplitude of the output signal decreases, the relative contribution to the output signal from the voltage Vn, compared to the voltage Vp, may be reduced. This means that the voltage excursion of Vn around Vmid will be reduced (possibly with a consequent increase in the voltage excursion of Vp to maintain a desired output signal Vout) as the indication of the output signal amplitude decreases. If the indication of output amplitude then decreases to a level where the amplifier circuit can operate in SE mode, there will thus already be little contribution to the output signal Vout from the voltage Vn and most of the output signal will be due to Vp.

The amplifier circuit may thus operate in the SE mode for a first range of output signal amplitudes and operate in the BTL mode for a second, higher, range of signal amplitudes. The controller201may control the contribution from the positive and negative signals path so that the contribution from one of the signal paths approaches zero as the indication of output signal amplitude approaches the bottom of the second range. This can aid in transitioning between modes.

The controller201may thus be configured to, when operating in the BTL mode, control the circuit such that a ratio of magnitude of the negative driving signal compared to magnitude of the positive driving signal varies with the indication of output signal amplitude. That is, the ratio |Vn−Vmid|/|Vp−Vmid| varies with the indication of signal amplitude.

FIG. 4illustrates one example of how the contributions from the positive and negative signals paths may be controlled, e.g. based on a volume setting, to achieve a desired overall effective gain. The top plot ofFIG. 4illustrates how the gains Gp and Gn of the positive and negative signal paths may be controlled based on the volume setting, and the lower plot shows the effective gain of the amplifier circuit.FIG. 4illustrates normalised values, i.e. the gains Gp and Gn are normalised in a range of 0 to 1, where a gain of 1 corresponds to a full-scale input signal leading to a full-scale driving signal from the relevant driver103por103n. The effective gain of the amplifier circuit, which is equal to Gp+Gn, is thus illustrated in the range of 0 to 2. The indication of amplitude is also normalised in the range of 0 to 1, where 1 corresponds to the maximum.

If the volume setting is at the maximum value of 1, then a full-scale input signal could lead to a full-scale output signal. In this case, therefore, the gains Gp and Gn are both at maximum. In this operating state the circuit is operating in a conventional BTL mode and the variation of voltages Vp and Vn from the midpoint voltage will be opposite and equal, i.e. the ratio |Vn−Vmid|/|Vp−Vmid| would be equal to 1.

However, if the volume setting is reduced, the gain Gn is reduced, whilst, as far as possible, keeping the gain Gp at maximum. Thus, as the volume setting decreases, in the range of 1 to 0.5, the gain Gn is reduced accordingly. The contribution to output signal Vout from the voltage Vn thus also reduces. The ratio of |Vn−Vmid|/|Vp−Vmid| thus drops to be lower than 1.

At a volume setting of 0.5, the gain Gn is reduced to zero. At this point the output variation due to a full-scale input signal can be provided by driver103palone. The circuit can thus switch to the SE mode of operation of disable the driver103n. It will be noted that at this point the driver103pis already providing the whole voltage variation for the output signal Vout and thus no change in gain for the positive signal path is needed.

If the volume setting were to be reduced further, the gain Gp could be reduced to provide the required volume control.

FIG. 5illustrates alternatively how the gains of the positive and negative signals paths may be varied based on the indication of the required output signal amplitude and may vary with the required signal amplitude so as to maintain a constant effective gain across the range of signal amplitudes. In this case the amplitude can be seen the input signal amplitude (assuming any volume controlled gain has already been applied).

If the input signal amplitude is less than 0.5, the required output signal can be generated by the positive driver103palone and the circuit may operate in the SE mode. The gain Gn of the negative signal path is thus 0. For the normalised range of input signal amplitudes from 0 to 0.5, the gain of the positive signal path may be fixed at a level that means that an input signal amplitude of 0.5 corresponds to a full-scale output from the driver103p. For the purposes of illustration the gain Gp inFIG. 5is thus represented as being 2.0 in this range.

If the input signal amplitude is greater than 0.5, the driver103pcannot generate the corresponding output signal on its own, and thus the amplifier circuit switches to BTL mode. The gain Gp of the positive signal path is reduced, to avoid clipping, but rather than simply set the gains Gp to be equal, the gain Gp is reduce only to the extent necessary to avoid clipping and the gain Gn is increased by a corresponding amount so that the overall gain is constant. If the signal amplitude increases further, the gain Gp is reduced further, with a consequent increase to the gain Gn, until for a signal amplitude of 1.0, the gains Gp and Gn are equal and the circuit is operating in a conventional BTL mode.

This means that, in the BTL mode, as the signal amplitude decreases, the relative contribution to the output signal from the voltage Vn becomes less and less, compared to Vp, until the point is reached where the negative signal path contributes nothing and the circuit can enter the SE mode.

Thus, for example, consider the example described above where the output range of each driver103pand103nis from 0V to 1V. If the output signal were required to have an amplitude of 0.6V, e.g. to vary between +0.6V and −0.6V, then conventionally in BTL operation, the drivers103pand103nwould produce inverse driving signals, each with an amplitude of 0.3V. In embodiments of the present disclosure however, to generate an output signal magnitude of 0.6V, the driver103pmay be driven to provide an output signal with a magnitude of 0.5V, i.e. a full-scale output, whilst the driver103ngenerates a driving signal that varies inversely with a magnitude of 0.1V.

Operating in this way thus allows for switching between modes relatively easily, as if the signal amplitude changes only relatively gradually, the changes in gain required when swapping between BTL and SE modes of operation may be relatively low.

There are various ways that the controller201may control the gains of the positive and negative signal paths. In some examples the controller may control the conversation gain of the drivers103pand103n. Additionally, or alternatively at least some gain control may be applied by one or more gain elements305pand305nin the respective signal paths. The gain elements may, conveniently, be located in a digital part of the relevant signal paths.

In the SE mode, the driver103nmay be disabled and the whole variation in the output signal Vout is driven by driver103p. This improves the efficiency of the amplifier circuit and avoids any power consumption associated with driver103n, for instance switching losses associated with a class-D amplifier.

In addition, in the SE mode, as the whole variation in the output signal Vout is driven by driver103p, the whole load resistance RL is seen by the driver103p. This is in contrast to BTL mode, where both drivers103pand103nare providing driving signals that vary with the input signal, and each driver only sees a proportion of the load resistance.

A higher effective load resistance for driver103pmay be beneficial, as various performance requirements may be relaxed for higher load impedances.

Operating in SE mode for lower output signal amplitudes may therefore be advantageous as it may ease some design considerations for the driver103p. Additionally, or alternatively, the operating parameters of the driver103pmay be varied in use.

In particular, in some embodiments a bias supplied to the driver103pmay be varied in use, for instance the magnitude of a bias current. When operating in the SE mode, in which the driver103pexperiences the full load resistance, a lower bias current may be supplied to achieve a desired performance than when operating in the BTL mode.

Referring back toFIG. 3the controller201may thus also be configured to control a bias source306so as control a bias applied to at least the driver103p. In particular a lower bias current may be used in the SE mode, which provide additional power savings.

When operating in the BTL mode an increase bias may be required to achieve a desired performance. However, as discussed above the relatively contributions to the output signal Vout from the positive and negative signal paths may be unequal, unless operating at the highest output amplitudes.

In at least some applications it may be expected that relatively high amplitude output signals may be required only relatively infrequently, and thus it may be expected that for a majority of the time in normal use the required output signal may have a relatively low amplitude. Embodiments of the present disclosure thus effectively optimise the amplifier circuit for generating such lower amplitude outputs signals whilst still allowing operation to provide relatively high amplitude output signals when required.

As discussed above, in the SE mode, the voltage at the output node or terminal104pis held at the defined midpoint voltage Vmid by regulator203.

In some implementations the midpoint voltage could be ground. For instance, if the supply voltages VH and VL are positive and negative voltages of the same magnitude, the midpoint voltage will be ground. In such a case the voltage regulator203may simply be a switch for selectively coupling the output node104nto ground, or some other type of ground clamp circuitry that could be activated and deactivated as required.

In some instances, however, the midpoint voltage Vmid may be a voltage level other than ground. For example, the supply voltage VH and VL could be voltages Vdd and ground respectively. In such a case the midpoint voltage may be Vdd/2 and the voltage regulator must maintain the defined voltage. The voltage regulator should advantageously be relatively power efficient.

In some examples the voltage regulator203may comprise a DC-DC converter such a charge pump or the like.FIG. 6illustrates one example where the supply voltages are Vdd and ground. In this example the voltage regulator comprises a charge pump which receives the supply voltage Vdd and which is operable to generate an output voltage of Vdd/2. There are various types of such step-down charge pump as will be understood by one skilled in the art which can efficiently generate the midpoint voltage when required. The charge pump may be activated and deactivated by a control signal Scn from the controller201. In some embodiments the switching frequency of the charge pump may also be variable in use, and may be reduced when the indication of the output signal amplitude decreases, so as to save power.

Embodiments of the disclosure thus relate to amplifier circuitry which is selectively operable in a BTL mode to drive both sides of a load with voltages that vary in accordance with an input signal, or a SE mode of operation in which only one side of the load is driven with a varying driving voltage and the other side of the load is held at a substantially constant voltage. The amplifier circuitry may operate in the SE mode when possible and swap to the BTL mode when required to generate higher amplitude output signal. When operating in the BTL mode the driving voltages on either side of the load may, for at least some amplitudes of output signal, be asymmetric or unequal. In particular the circuit may be operable so that, when operating in the BTL mode, the relative contribution to the output signal from the driving voltage on one side of the load is reduced at lower signal amplitudes, which may be advantageous for swapping between modes.

The discussion above has described that it is the voltage at the negative output node104nwhich is held constant in the SE mode and it is the contribution at the positive output node104pwhich is maximised in the BTL mode. It will of course be understood that the opposite could be implemented. It will also be understood that the terms positive and negative are used simply as labels to distinguish the differential signal components and should not be taken to imply anything about the level or polarity of any voltages produced.

The description has also focused on driving audio output transducers. This may include transducers such as loudspeakers for generating audible sounds, but may also include ultrasonic or other similar transducers and/or haptic transducers. Embodiments also relate to amplifier circuits for driving other types of transducers.

Embodiments may be advantageously implemented as part of audio processing circuitry, e.g. for audio amplifiers for providing audio driving signals to audio output transducers such as loudspeakers, which may be transducers of a host device and/or transducers of an accessory apparatus which may be removably connected to the host device in use.

Embodiments may be arranged as part of an audio and/or signal processing circuit, for instance an audio circuit such as a codec which may be provided in a host device. A circuit according to an embodiment of the present invention may be implemented as an integrated circuit.

Embodiments may be incorporated in a host electronic device, which may for example be a portable device and/or a device operable with battery power. The host device could a device with one or more loudspeaker provided as part of the host device and/or a connector for making a wired connection with a loudspeaker of a removable accessory apparatus that may be removably connected to the host device in use. The host device may include a wireless communication module for receiving input data. The host device could be a communication device such as a mobile telephone or smartphone or similar, a computing device such as notebook, laptop or tablet computing device, a wearable device such as a smartwatch. The host device could alternatively be an accessory device for use with any such communication, computing or wearable device. For instance the host device could be a headset or earbud or similar