Printed wiring board and method for manufacturing printed wiring board

A printed wiring board includes a first insulation layer, an electronic component built into the first insulation layer, a second insulation layer having a via conductor and formed on a first surface of the first insulation layer, and a conductive film formed on the first insulation layer on the opposite side with respect to the first surface of the first insulation layer such that the conductive film is positioned to face a back surface of the electronic component. The first insulation layer has a coefficient of thermal expansion which is set higher than a coefficient of thermal expansion of the second insulation layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2013-157558, filed Jul. 30, 2013, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a printed wiring board with a built-in electronic component and to a method for manufacturing such a printed wiring board.

2. Description of Background Art

JP 2012-191204A describes a method for embedding an electronic component in an insulation layer without using a core substrate so as to obtain a thinner wiring board. JP 2012-191204A describes a method for manufacturing a semiconductor device which includes mounting an electronic component on a support board, embedding in an insulation layer the electronic component on the support board, and removing the support board. The entire contents of this publication are incorporated herein by reference.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a printed wiring board includes a first insulation layer, an electronic component built into the first insulation layer, a second insulation layer having a via conductor and formed on a first surface of the first insulation layer, and a conductive film formed on the first insulation layer on the opposite side with respect to the first surface of the first insulation layer such that the conductive film is positioned to face a back surface of the electronic component. The first insulation layer has a coefficient of thermal expansion which is set higher than a coefficient of thermal expansion of the second insulation layer.

According to another aspect of the present invention, a method for manufacturing a printed wiring board includes forming copper layer portions on a support board having a copper foil, forming a conductive film and an external connection pad on the copper layer portions formed on the copper foil, respectively, mounting a semiconductor component on the conductive film such that a back side of the semiconductor component is adhered to the conductive film via an adhesive agent, forming a first insulation layer on the support board such that the semiconductor component is embedded in the first insulation layer, forming a first via conductor in the first insulation layer such that the first via conductor connects to an electrode of the semiconductor component, forming a second insulation layer having a second via conductor on the first insulation layer, separating the support board from the first insulation layer such that a laminated structure comprising the first insulation layer, the semiconductor component built in the first insulation layer and the second insulation layer formed on the first insulation layer is removed from the support board, and removing the copper foil and the copper layer portions such that the conductive film and the external connection pad are exposed.

DETAILED DESCRIPTION OF THE EMBODIMENTS

First Embodiment

A printed wiring board according to a first embodiment of the present invention is described below with reference toFIGS. 1 and 2.

FIG. 1is a cross-sectional view of printed wiring board10according to the first embodiment.FIG. 2shows a usage example of the printed wiring board of the first embodiment. InFIG. 2, solder bump76is formed on pad (71FP) of the printed wiring board shown inFIG. 1.

As shown inFIG. 1, printed wiring board10has the following: outermost first resin insulation layer30, which accommodates IC chip90with a redistribution wiring layer and which has main surface (F) and secondary surface (S) opposite the main surface; pad (51SP) on the secondary-surface side of first resin insulation layer30; first conductive layer34on main surface (F) of the first resin insulation layer; second resin insulation layer (50A) on the main surface of first resin insulation layer30; second conductive layer (58A) on second resin insulation layer (50A); third resin insulation layer (50B) on second resin insulation layer (50A) and on second conductive layer (58A); third conductive layer (58B) on third resin insulation layer (50B); outermost fourth resin insulation layer (50C) on third resin insulation layer (50B) and on third conductive layer (58B); and outermost fourth conductive layer (58C) on outermost fourth resin insulation layer (50C). On the back surface of IC chip90, conductive film (22D) is formed with adhesive agent24disposed in between. Instead of an adhesive agent, die-attach paste or die-attach film made of silver paste or the like, or a conductive adhesive agent may be used. Pad (51SP) is formed in a position recessed from the secondary surface of first resin insulation layer30. Pad (51SP) and first conductive layer34are connected by via conductor36penetrating through the first resin insulation layer. Electrode92of the IC chip and first conductive layer34are connected by connection via conductor (36A). First conductive layer34and second conductive layer (58A) are connected by via conductor (60A) penetrating through the second resin insulation layer. Second conductive layer (58A) and third conductive layer (58B) are connected by via conductor (60B) penetrating through third resin insulation layer (50B). Third conductive layer (58B) and fourth conductive layer (58C) are connected by via conductor (60C) penetrating through fourth resin insulation layer (50C). Solder-resist layer70is formed on fourth resin insulation layer (50C). In solder-resist layer70, opening71to expose pad (71FP) is formed, nickel film72and gold film74are formed on pad (71FP), and solder bump76is formed on gold film74(seeFIG. 2).

In a printed wiring board of the first embodiment, first resin insulation layer30is formed to have thickness (t1) at 50 μm; second resin insulation layer (50A) to have thickness (t2) at 30 μm; third resin insulation layer (50B) to have thickness (t3) at 30 μm; fourth resin insulation layer (50C) to have thickness (t4) at 30 μm; and solder-resist layer70to have thickness (t5) at 20 μm. Among the above, the thickness of the first resin insulation layer to embed an IC chip is formed to be greatest, and the thickness is preferred to be 50˜250 μm. Second resin insulation layer (50A), third resin insulation layer (50B) and fourth resin insulation layer (50C) are made with the same composition, and their CTE (coefficient of thermal expansion) is approximately 10˜20 ppm. First resin insulation layer30is made with the same resin composition as that of second resin insulation layer (50A), third resin insulation layer (50B) and fourth resin insulation layer (50C) except that its CTE is adjusted by the amount of inorganic filler so as to have a CTE of approximately 30˜40 ppm, which is approximately 1.5˜3 times the CTE of the second, third and fourth resin insulation layers. The CTE of the solder-resist layer is adjusted to be in the mid-range between the CTE of the first resin insulation layer and the CTE of the second, third and fourth resin insulation layers. The first, second and third resin insulation layers are made of resin containing inorganic particles of a hydroxide or the like. Examples of resin are epoxy resin, BT (bismaleimide triazine) resin and the like. Inorganic particles of a hydroxide are, for example, metal hydroxides such as aluminum hydroxide, magnesium hydroxide, calcium hydroxide, barium hydroxide and the like. The first, second, third and fourth resin insulation layers do not contain a core material. However, it is an option for the second, third and fourth resin insulation layers to contain a core material (reinforcing material). Examples of a reinforcing material are glass cloth, aramid fiber, fiberglass and the like. The glass is preferred to be T-glass.

In a printed wiring board of the first embodiment, first resin insulation layer30with embedded IC chip90has a higher CTE than second resin insulation layer (50A), third resin insulation layer (50B) and fourth resin insulation layer (50C) formed on the first resin insulation layer. Since the CTE of the first resin insulation layer30is higher, warping occurs in a direction that lowers the peripheral sides of the first resin insulation layer when it is under high temperature, offsetting the warping in a direction that raises the peripheral sides of the second, third and fourth resin insulation layers having a smaller CTE with respect to the CTE of the first resin insulation layer30. On the other hand, warping occurs in a direction that raises the peripheral sides of the first resin insulation layer when it is under normal temperature, offsetting the warping in a direction that lowers the peripheral sides of the second, third and fourth resin insulation layers having a large CTE. Thus, warping in the printed wiring board is reduced. Accordingly, reliability is enhanced when an IC chip and first printed wiring board are mounted on the printed wiring board.

In a printed wiring board of the first embodiment, since conductive film (22D) is provided on the back surface of IC chip90, which is on the secondary-surface side of first resin insulation layer30, the difference decreases between the area of conductors on the secondary-surface side of the first insulation layer, where a smaller amount of conductors is formed, and the area of conductors on the second, third and fourth insulation layers. Accordingly, warping caused by the difference in the areas of conductors is reduced, thus enhancing the reliability of mounting an electronic component or a second printed wiring board on the printed wiring board.

FIG. 8is a plan view of conductive film (22D) for mounting IC chip90. The area of conductive film (22D) is preferred to be greater than the area of the back surface of IC chip90. By increasing the area of conductive film (22D), the difference decreases between the area of conductors on the secondary-surface side of the first insulation layer, where a smaller amount of conductors is formed, and the area of conductors on the second, third and fourth insulation layers.

FIG. 9is a graph showing change in warping in proportion to the thickness of the electronic component and the thickness of conductive film (22D). The upper side of the graph shows the degree of warping at normal temperature (25° C.) and the lower side of the graph shows the degree of warping at high temperature (260° C.), when the thickness of the electronic component is set at 150 μm (black triangle), at 125 μm (black rectangle), and at 100 μm (black diamond) respectively. By providing a 15-μm thick conductive film, the degree of warping is reduced compared with a situation where no conductive film (22D) is provided (thickness of 0 μm). Moreover, by providing a 30-μm thick conductive film, the degree of warping is further reduced. Here, the electronic component is preferred to have an approximate thickness of 30˜200 μm, and the thickness of conductive film (22D) is preferred to be 5˜40 μm.

Adhesive agent24is preferred to have a thickness of 3˜25 μm. Adhesive agent24is preferred to be a non-conductive adhesive agent when the electronic component accommodated in a printed wiring board is a memory or the like that generates less heat, whereas a die-attach film with high heat transmission or a conductive agent is preferable when the electronic component is a power MOSFET or the like for a power supply that generates more heat. Conductive film (22D) can be used as a heat sink. When a non-conductive adhesive agent is used, conductive film (22D) is preferred to be used as a ground layer to stabilize the power source.

In the first embodiment, since pad (51SP) is provided in recess (51S) of the first resin insulation layer, it is not necessary to form a solder-resist layer to prevent short circuiting when solder bumps are formed thereon. Thus, there is no need to form a solder-resist layer with a low CTE on the exposed-surface side of the first resin insulation layer. Accordingly, no solder-resist layer will inhibit the first resin insulation layer from functioning to reduce the degree of warping.

The following is a method for manufacturing a printed wiring board according to the first embodiment described with reference toFIG. 3˜7.

Double-sided copper-clad laminate (20A) formed by laminating copper foils23on resin substrate20, along with copper foil21with a thickness of 3˜20 μm, is prepared (FIG. 3(A)). Copper foil21is bonded to copper foil23of the copper-clad laminate by an adhesive agent or by ultrasonic bonding. The copper-clad laminate and the copper foil are bonded at a predetermined width along their peripheries.

Plating resist (not shown) having openings is formed on copper foil21, and electrolytic plating is performed to form copper layer29, gold layer28, nickel layer26and copper layer22in that order in the openings. Then, the plating resist is removed (FIG. 3(B)).

In the IC chip mounting region, IC chip90is positioned on copper layer22with adhesive agent24disposed in between in such a way that the back surface of the IC chip faces double-sided copper-clad laminate (20A) (FIG. 3(C)).

Resin film for forming interlayer resin insulation layers is laminated on copper foil21to form first resin insulation layer30(FIG. 3(D)).

Using a laser, opening31reaching copper layer22and opening (31A) reaching electrode92of the IC chip are formed in first resin insulation layer30(FIG. 3(E)).

Electroless plating is performed to form electroless copper-plated film38on the surface of first resin insulation layer30and in openings (31,31A) (FIG. 4(A)).

Plating resist35with a predetermined pattern is formed on electroless copper-plated film38(FIG. 4(B)).

Electrolytic plating is performed to form electrolytic plated film33in portions where no plating resist35is formed (FIG. 4(C)). At that time, opening31is filled with electrolytic plated film to form via conductor36, and opening (31A) is filled with electrolytic plated film to form connection via conductor (36A).

The plating resist is removed, and electroless copper-plated film38is removed from portions where no electrolytic plated film is formed so as to form first conductive layer34made up of electroless plated film38and electrolytic plated film33(FIG. 5(A)).

Second resin insulation layer (50A) and second conductive layer (58A) are formed on first resin insulation layer30by the same procedures described above with reference toFIG. 3(D)˜FIG. 5(A). First conductive layer34and second conductive layer (58A) are connected by via conductor (60A) (FIG. 5(B)).

Third resin insulation layer (50B) and third conductive layer (58B) are formed on second resin insulation layer (50A) by the same procedures described above with reference toFIG. 3(D)˜FIG. 5(A). Second conductive layer (58A) and third conductive layer (58B) are connected by via conductor (60B).

Fourth resin insulation layer (50C) and fourth conductive layer (58C) are formed on third resin insulation layer (50B) by the same procedures described above with reference toFIG. 3(D)˜FIG. 5(A). Third conductive layer (58B) and fourth conductive layer (58C) are connected by via conductor (60C) (FIG. 6(A)).

Solder-resist layer70having opening71is formed on fourth resin insulation layer (50C). Electroless plating is performed to form Ni film72and Au film74in opening71(FIG. 6(B)). Laminated substrate1000is completed. Instead of Ni/Au film, metal film such as Ni/Pd/Au film or Sn film may also be formed.

The laminated substrate is cut at (k-k) inside the bonded portion of copper foil21and double-sided copper-clad laminate (20A), and double-sided copper-clad laminate (20A) is removed (FIG. 7(A)).

Copper foil21and copper layer29are removed from laminated substrate1000by selective etching. “SF-5420” made by Mec Co., Ltd. may be used as the etching solution. Gold layer28is exposed and the gold layer forms pad (51SP), and copper layer22, nickel layer26and gold layer28under the IC chip form conductive film (22D) (FIG. 7(B),FIG. 1). In the first resin insulation layer, first recess (51SS) for forming conductive film and second recess (51S) for forming a pad are formed when copper layer29is removed. Conductive film (22D) is formed in first recess (51SS) and pad (51SP) is formed in second recess (51S).

In a printed wiring board according to the first embodiment, pad (51SP) is recessed from secondary surface (S) of first resin insulation layer30. Thus, short circuiting of solder bumps on adjacent pads is unlikely to occur.

First Modified Example of First Embodiment

In the first embodiment, a gold layer was formed on the nickel layer. In a first modified example of the first embodiment, a gold layer is omitted, and copper layer29, nickel layer26and copper layer22are formed, and after etching copper layer29, nickel layer26is removed by selective etching to expose copper layer22. Then, as shown inFIG. 10, OSP27(organic film such as heat-resistant water-soluble preflux) is formed on copper layer22(pad (51P) and conductive film (22D)). It is easier to form OSP than to form metal film by plating.

Second Modified Example of First Embodiment

FIG. 11is a cross-sectional view of a printed wiring board according to a second modified example of the first embodiment.

In the first embodiment, conductive film (22D) was formed in first recess (51SS) so that the surface of conductive film (22D) is recessed from the secondary surface of first resin insulation layer30. By contrast, in the second modified example of the first embodiment, the surface of conductive film (22D) is made flush with the secondary surface of first resin insulation layer30.

FIG. 14shows a method for manufacturing a printed wiring board according to the second modified example of the first embodiment. After double-sided copper-clad laminate (20A) has been removed as shown inFIG. 7(A), copper foil21is removed by etching (FIG. 14(A)). Etching resist102is formed on conductive film (22D) (FIG. 14(B)), copper layer29in the pad-forming portion is removed, and pad (51SP) made of gold layer28is formed in second recess (51S). In the second modified example of the first embodiment, by increasing the thickness of conductive film (22D), the amount of conductive layer between layers is adjusted. In the second modified example, it is another option to omit the gold layer, and to form conductive film (22D) with a copper-nickel-copper layer, and to perform surface treatment on the exposed copper layer.

Third Modified Example of First Embodiment

FIG. 12is a cross-sectional view of a printed wiring board according to a third modified example of the first embodiment. In the third modified example of the first embodiment, the surface of conductive film (22D) protrudes from the secondary-surface side of first resin insulation layer30.

FIG. 15shows a method for manufacturing a printed wiring board according to the third modified example of the first embodiment. After double-sided copper-clad laminate (20A) has been removed as shown inFIG. 7(A), etching resist102is formed on the portion of conductive film (22D) on copper foil21(FIG. 15(A)). Then, copper foil21where no etching resist is formed and copper layer29on a pad-forming portion are removed by etching so as to form pad (51SP) made of gold layer28in second recess (51S) (FIG. 15(B)). In the third modified example, the gold layer may be omitted; instead, it is an option to form conductive film (22D) with a copper-nickel-copper layer, and to perform surface treatment on the exposed copper layer.

Fourth Modified Example of First Embodiment

FIG. 13is a cross-sectional view of a printed wiring board according to a fourth modified example of the first embodiment.

In the first embodiment, via conductor36penetrating through first resin insulation layer30is formed by filling plating. By contrast, in the fourth modified example of the first embodiment, resin37is filled in via conductor (36B) penetrating through first resin insulation layer30. In the fourth modified example of the first embodiment, only via conductor (36B) that penetrates through thick first resin insulation layer30is filled with resin so that its rigidity is balanced with connection via conductor (36A) in the same layer and with via conductors (60A,60B,60C) in other layers. Accordingly, the degree of warping is reduced.

Second Embodiment

FIG. 16is a cross-sectional view of a printed wiring board according to a second embodiment.FIG. 17shows a usage example of a printed wiring board of the second embodiment. InFIG. 17, printed wiring board10is mounted on motherboard96through solder bump (76F) and pad (96P) of the printed wiring board shown inFIG. 1, and memory chip94is mounted on pad (51SP) of printed wiring board10through solder bump (76S) and pad (94P).

As shown inFIG. 16, printed wiring board10has the following: first resin insulation layer30which accommodates IC chip90with a redistribution wiring layer and which has main surface (F) and secondary surface (S) opposite the main surface; first conductive layer34on main surface (F) of the first resin insulation layer; second resin insulation layer (50A) on the main surface of first resin insulation layer30; second conductive layer (58A) on second resin insulation layer (50A); third resin insulation layer (50B) on second resin insulation layer (50A) and on second conductive layer (58A); third conductive layer (58B) on third resin insulation layer (50B); outermost fourth resin insulation layer (50C) on third resin insulation layer (50B) and on third conductive layer (58B); and outermost fourth conductive layer (58C) on outermost fourth resin insulation layer (50C). On the back surface of IC chip90, conductive film (22D) is formed with adhesive agent24disposed in between.

On the secondary-surface side of first resin insulation layer30, the printed wiring board has fifth conductive layer (58D), fifth resin insulation layer (50D) on the secondary surface of first resin insulation layer30, sixth conductive layer (58E) on fifth resin insulation layer (50D), and sixth resin insulation layer (50E) on fifth resin insulation layer (50D) and on sixth conductive layer (58E). Recess (51S) to expose pad (51SP) is formed in sixth resin insulation layer (50E). Pad (51SP) and sixth conductive layer (58E) are connected by via conductor (60E) penetrating through the sixth resin insulation layer. Sixth conductive layer (58E) and fifth conductive layer (58D) are connected by via conductor (60D) penetrating through the fifth resin insulation layer. Fifth conductive layer (58D) and first conductive layer34are connected by via conductor36penetrating through the first resin insulation layer. Electrode92of the IC chip and first conductive layer34are connected by connection via conductor (36A). First conductive layer34and second conductive layer (58A) are connected by via conductor (60A) penetrating through the second resin insulation layer. Second conductive layer (58A) and third conductive layer (58B) are connected by via conductor (60B) penetrating through third resin insulation layer (50B). Third conductive layer (58B) and fourth conductive layer (58C) are connected by via conductor (60C) penetrating through fourth resin insulation layer (50C). Solder-resist layer70is formed on fourth resin insulation layer (50C). Opening71to expose pad (71FP) is formed in solder-resist layer70. Nickel film72and gold film74are formed on pad (71FP), and solder bump (76F) is formed on gold film74(seeFIG. 17).

In the second embodiment, second resin insulation layer (50A), third resin insulation layer (50B) and fourth resin insulation layer (50C) are made with the same composition, and their CTE (coefficient of thermal expansion) is approximately 10˜20 ppm. First resin insulation layer30is made with the same resin composition as that of second resin insulation layer (50A), third resin insulation layer (50B), fourth resin insulation layer (50C), fifth resin insulation layer (50D) and sixth resin insulation layer (50E), except that its CTE is adjusted by the amount of inorganic filler so as to have a CTE of approximately 30˜40 ppm, which is approximately 1.5˜3 times the CTE of the second, third and fourth resin insulation layers. The CTE of the solder-resist layer and the CTE of fifth resin insulation layer (50D) and sixth resin insulation layer (50E) are adjusted to be in the mid-range between the CTE of the first resin insulation layer and the CTE of the second, third and fourth resin insulation layers.

In a printed wiring board of the second embodiment, first resin insulation layer30with embedded IC chip90has a higher CTE than second resin insulation layer (50A), third resin insulation layer (50B) and fourth resin insulation layer (50C) formed on the first resin insulation layer. Since the CTE of the first resin insulation layer is higher, warping occurs in a direction that lowers the peripheral sides of the first resin insulation layer when it is under high temperature, offsetting the warping in a direction that raises the peripheral sides of the second, third and fourth resin insulation layers having a smaller CTE with respect to the CTE of the first resin insulation layer30. On the other hand, warping occurs in a direction that raises the peripheral sides of the first resin insulation layer when it is under normal temperature, offsetting the warping in a direction that lowers the peripheral sides of the second, third and fourth resin insulation layers having a large CTE. Thus, warping in the printed wiring board is reduced. Accordingly, reliability is enhanced when an IC chip and first printed wiring board are mounted on the printed wiring board.

A printed wiring board according to the second embodiment has a buildup layer on the back-surface side of the IC chip. Thus, when an electronic component with numerous connection terminals such as a memory is mounted, flexibility in pad-positioning design is high on the memory side. In addition, a memory of a generic design can be used as is.

FIGS. 18 and 19show steps in manufacturing a printed wiring board according to the second embodiment.

Double-sided copper-clad laminate (20A) with copper foil23laminated on resin substrate20, along with copper foil21with a thickness of 3˜20 μm, is prepared (FIG. 18(A)). Copper foil21is bonded on copper foil23of the copper-clad laminate by an adhesive agent or by ultrasonic bonding so that the copper-clad laminate and the copper foil are bonded at a predetermined width along their peripheries.

Plating resist (not shown) with openings is formed on copper foil21, and electrolytic plating is performed to form copper layer29, gold layer28, nickel layer26and copper layer22in that order in the opening. Then, the plating resist is removed (FIG. 18(B)).

Sixth resin insulation layer (50E) and sixth conductive layer (58E) are formed on copper foil21by the same procedures described above with reference toFIG. 3(D)˜FIG. 5(A)in the first embodiment. Copper layer22and sixth conductive layer (58E) are connected by via conductor (60E) (FIG. 18(C)).

Fifth resin insulation layer (50D), fifth conductive layer (58D) and conductive film (22D) are formed on sixth resin insulation layer (50E) by the same procedures described above with reference toFIG. 3(D)˜FIG. 5(A). Sixth conductive layer (58E) and fifth conductive layer (58D) are connected by via conductor (60A) (FIG. 18(D)).

In the IC chip mounting region, IC chip90is mounted on conductive film (22D) with adhesive agent24disposed in between in such a way that the back surface of the IC chip faces the conductive film (FIG. 19(A)).

By the same procedures described above with reference toFIG. 3(D)˜FIG. 5(A), first resin insulation layer30, first conductive layer34, via conductor36and connection via conductor (36A) are formed. Second resin insulation layer (50A) and second conductive layer (58A) are formed on first resin insulation layer30. First conductive layer34and second conductive layer (58A) are connected by via conductor (60A). Third resin insulation layer (50B) and third conductive layer (58B) are formed on second resin insulation layer (50A). Second conductive layer (58A) and third conductive layer (58B) are connected by via conductor (60B). Fourth resin insulation layer (50C) and fourth conductive layer (58C) are formed on third resin insulation layer (50B). Third conductive layer (58B) and fourth conductive layer (58C) are connected by via conductor (60C). Solder-resist layer70with opening71is formed on fourth resin insulation layer (50C). Electroless plating is performed to form Ni film72and Au film74in opening71(FIG. 19(B)). Laminated substrate1000is completed. Since the subsequent steps are the same as in the first embodiment, their descriptions are omitted here.

When an electronic component is embedded in a resin insulation layer, warping is likely to occur in the resin insulation layer at the peripheries of the highly rigid electronic component made of silicon, causing a printed wiring board at normal temperature to warp in a shape with lowered peripheries and at high temperature to warp in a shape with raised peripheries. Accordingly, connection reliability is thought to decrease when another electronic component or a second printed wiring board is mounted on the printed wiring board.

A printed wiring board according to an embodiment of the present invention has an electronic component built-in and exhibits a smaller degree of warping.

A printed wiring board according to an embodiment of the present invention is characterized by having the following: a first insulation layer having a main surface and a secondary surface opposite the main surface; an electronic component built into the first insulation layer; a second insulation layer having a via conductor and positioned on the main surface of the first insulation layer; a third insulation layer having a via conductor and positioned on the second insulation layer; and a conductive film provided on the back surface of the electronic component, which is on the secondary-surface side of the first insulation layer. In such a printed wiring board, the coefficient of thermal expansion of the first insulation layer is set to be higher than that of the second insulation layer.

In a printed wiring board according to an embodiment of the present invention, the CTE of a first insulation layer with an embedded electronic component is higher than that of a second insulation layer formed on the first insulation layer. Since the first insulation layer has a higher CTE, warping at high temperature occurs in a direction that lowers the peripheral sides of the first insulation layer, thus offsetting the warping in a direction that raises the peripheral sides of the second insulation layer. At normal temperature, warping occurs in a direction that raises the peripheral sides of the first insulation layer, thus offsetting the warping in a direction that lowers the peripheral sides of the second insulation layer. Accordingly, the degree of warping in the printed wiring board is made smaller. Moreover, since conductive film is provided on the back surface of the electronic component, which is on the secondary-surface side of the first insulation layer, the difference decreases between the area of conductors on the secondary-surface side of the first insulation layer, where a smaller amount of conductors is formed, and the area of conductors on the second and third insulation layers. Thus, warping caused by the difference in the areas of the conductors is reduced. Accordingly, reliability is enhanced when an electronic component or a second printed wiring board is mounted on the printed wiring board.

In each of the embodiments above, a printed wiring board with a built-in electronic component was described as an example. However, it is an option for each printed wiring board to accommodate multiple electronic components. In addition, instead of active components such as an IC chip, it is another option to accommodate passive components such as a chip capacitor.