A bottom-emitting multijunction VCSEL array includes a first reflector region, a multijunction active region, and a second reflector region. In one aspect, the multijunction VCSEL array is attached to a submount by flip-chip bonding. In another aspect, the multijunction VCSEL array further includes a contact layer formed between the first reflector region and the substrate. The multijunction VCSEL array is attached to a submount by flip-chip bonding.

FIELD OF INVENTION

This invention generally relates to Vertical Cavity Surface Emitting Laser (VCSEL) arrays and specifically to bottom-emitting multijunction VCSEL arrays.

BACKGROUND OF THE INVENTION

Compared to edge-emitting semiconductor lasers with a horizontal Fabry-Perot resonator and cleaved facets acting as mirrors, VCSELs have a vertical cavity and emit a circular beam normal to the surface. VCSELs have many advantages over edge-emitting semiconductor lasers such as compact size, small beam spot, low beam divergence, narrow spectral width, low sensitivity to temperature, fast rise time, and ease of fabricating two-dimensional (2-D) VCSEL array, etc.

In recent years, VCSEL arrays become a prominent player in three-dimensional (3D) sensing applications. For instance, many smartphones are equipped with a VCSEL-array-based 3D sensor using the Time-of-Flight (ToF) method or the structured light method for facial recognition. In addition, VCSEL-array-based systems, such as light detection and ranging (LIDAR) systems, have entered the emerging autonomous vehicle landscape. LIDAR systems may help recognize running vehicles and walking or standing pedestrians on a road effectively and quickly, and thus may prevent fatal accidents and mitigate one of the most challenging issues a driverless car faces.

LIDAR is based on ToF measurement principles. It illuminates a scene with a laser beam. The beam is scattered by objects of the scene. It then detects the bounce-back of the beam. The distance is calculated by the time it takes for the beam to travel to the objects and back from them. In VCSEL-based LIDAR applications, the detection range is often determined by the output power and thus high-power VCSELs are desirable for LIDAR applications.

Multijunction VCSEL represents one approach to increase the output power of VCSEL. In a multijunction VCSEL structure, the gain volume is increased. For example, two or more than two multi-quantum-well (MQW) active regions may be configured in series to form a multijunction active region. As the coherent light is generated in each MQW active region, the output power may be multiplied. In addition, the slope efficiency is improved. However, while the output power is increased, so is the heat generated in the multijunction active region, which may make overheating issues more severe in a multijunction VCSEL than those in a VCSEL with a single MQW active region. Overheating may cause problems such as reduced power output, higher thresholds, and wavelength change of the VCSEL output.

Thus, efficient heat dissipation is important for a multijunction VCSEL, and especially for a multijunction VCSEL array. When a top-emitting multijunction VCSEL is mounted, the top p+ contact layer faces upward and the substrate is bonded to a submount, i.e., the heat sink. As the heat is generated in the multijunction active region, the heat has to go through the substrate to reach the heat sink. The substrate, however, has to be thick enough, e.g., 100-600 micrometers, to provide a stable support for a VCSEL array. As such, heat dissipation of a top-emitting multijunction VCSEL is inherently affected by the substrate.

Therefore, there exists a need to improve heat dissipation of a multijunction VCSEL array.

SUMMARY OF THE INVENTION

The present invention discloses methods and apparatus for bottom-emitting multijunction VCSEL array devices. In one aspect, a bottom-emitting multijunction VCSEL array device includes a submount and a VCSEL array chip attached to the submount. The VCSEL array chip includes a substrate and VCSEL structures formed in a first chip region above the substrate. Each VCSEL structure includes a first reflector region formed above the substrate, a multijunction active region including MQW active regions formed above the first reflector region, a second reflector region formed above the multijunction active region, and a pad metal layer formed above the second reflector region. The pad metal layer faces the submount and is between the substrate and the submount after the VCSEL array chip is attached to the submount.

In another aspect, a method for fabricating a bottom-emitting multijunction VCSEL array device includes forming VCSEL structures in a first chip region above a substrate of a VCSEL array chip and attaching the VCSEL array chip on a submount. Forming the VCSEL structures includes growing a first reflector region above the substrate, growing a multijunction active region above the first reflector region, growing a second reflector region above the multijunction active region, and forming a pad metal layer above the second reflector region. The pad metal layer faces the submount and is between the substrate and the submount after the VCSEL array chip is attached on the submount.

In another aspect, a bottom-emitting multijunction VCSEL array device includes a submount and a VCSEL array chip attached to the submount. The VCSEL array chip includes a substrate and VCSEL structures formed in a first chip region above the substrate. Each VCSEL structure includes a contact layer formed above the substrate, a first reflector region formed above the contact layer, a multijunction active region formed above the first reflector region, a second reflector region formed above the multijunction active region, and a pad metal layer formed above the second reflector layer and electrically connected to the contact layer. The pad metal layer faces the submount and is between the substrate and the submount after the VCSEL array chip is attached to the submount.

DETAILED DESCRIPTION

Detailed description of the present invention is provided below along with figures and embodiments, which further clarifies the objectives, technical solutions, and advantages of the present invention. It is noted that schematic embodiments discussed herein are merely for illustrating the invention. The present invention is not limited to the embodiments disclosed.

FIG.1shows a multijunction VCSEL100in a cross-sectional view. VCSEL100may be one of the VCSEL emitters of a VCSEL array. The VCSEL emitters may be separated by isolation structures. The VCSEL array may include thousands or tens of thousands of VCSEL emitters or VCSELs. In other figures and descriptions below, only a few VCSELs are used for explaining principles and methods of a VCSEL array. VCSEL100represents a top-emitting VCSEL structure or a top-emitting VCSEL emitter which emits a laser beam through the top surface when charged with an electrical current. As used herein, a VCSEL, VCSEL structure, and VCSEL emitter have the same meaning and may be used interchangeably.

As shown inFIG.1, VCSEL100exemplarily includes a multijunction active region101, a top reflector region102, and a bottom reflector region103, each of which include layers grown epitaxially above a substrate104. Multijunction active region101contains multi quantum well (MQW) active regions, oxide layers, and at least one tunnel junction structure. For example, multijunction active region101may include MQW active regions105,106, and107, oxide layers108,109, and110, and tunnel junction structures111and112. Oxide layers108,109, and110are configured to form three oxide apertures, such as an oxide aperture113formed by oxide layer108. In some embodiments, a multijunction VCSEL may have fewer MQW active regions, fewer oxide layers, and fewer tunnel junction structures. For example, a VCSEL may have a structure similar to that of VCSEL100, e.g., having MQW active regions105and106, oxide layers108and109, and tunnel junction structure111, but may not have tunnel layer112, oxide layer110, and MQW active region107. That is, a multijunction VCSEL may have two MQW active regions, two oxide layers, and one tunnel junction structure. In some other embodiments, a multijunction VCSEL may have more MQW regions, more oxide layers, and more tunnel junction structures than VCSEL100. For example, a multijunction VCSEL may have N MQW active regions, N oxide layers, and N-1 tunnel junction structures, where N is an integer larger than 3, e.g., N may be 4 or 5.

Top reflector region102may contain a p-type Distributed Bragg Reflector (DBR). Bottom reflector region103may contain an n-type DBR. Substrate104may include, for example, a conductive n-type gallium arsenide (GaAs) substrate. The quantum well layers, tunnel junction structures, and DBRs may be grown above substrate104in an epitaxial process. Reflector regions102and103are electrically conductive. A metal layer114may be deposited on the top surface of reflector region102, followed by deposition of a dielectric layer (not shown). On the bottom surface of substrate104, a metal layer115may be deposited. Metal layers114and115serve as the anode and cathode contacts, respectively. VCSEL100may be separated from other VCSELs (not shown) by isolation region116. Isolation region116may be a trench filled with a dielectric material.

During VCSEL operation, the majority of heat comes from the active region. For a multijunction VCSEL with multiple active regions, the heat generated in the VCSEL may be approximately proportional to the number of active regions. That is, when the number of active regions is increased in a VCSEL structure for achieving higher output power, the heat generated is also increased and overheating issues may become worse. Hence, thermal management of multijunction VCSEL is an important factor for reliability, opto-electric performances, and intensity uniformity.

As shown inFIG.1, multijunction active region101is closer to the top surface of reflector region102than the bottom surface of substrate104(or metal layer115). As aforementioned, the substrate thickness is around 100-600 micrometers. Then, the distance between active region101and the bottom surface of substrate104may be ten times or more than ten times of that between active region101and the top surface of reflector region102. For a top-emitting VCSEL, the substrate is bonded to a submount. For a bottom-emitting VCSEL, a pad metal layer on the top reflector region is bonded to a submount in a flip-chip process. Therefore, the active region of a bottom-emitting VCSEL is much closer to the submount than that of a top-emitting VCSEL. The closer the active region to a submount, i.e., the heat sink, the more efficient the heat dissipation becomes. Hence, heat dissipation of a bottom-emitting VCSEL is inherently better than that of a top-emitting VCSEL. Therefore, compared to a top-emitting VCSEL, a bottom-emitting VCSEL has improved heat dissipation. That is, a bottom-emitting multijunction VCSEL is advantageous over a top-emitting multijunction VCSEL in terms of heat management. In addition, a bottom-emitting VCSEL chip is often bonded to a submount without using bonding wires. Hence, it supports operations of short-pulse mode, e.g., nanosecond-pulse mode.

FIGS.2A,2B, and2Ceach schematically illustrate a bottom-emitting multijunction VCSEL array200according to embodiments of the present invention.FIGS.2A and2Care cross-sectional views of array200or a chip containing array200, whileFIG.2Bis a top view.FIG.2Cshows a cross-sectional view along a line AA’ ofFIG.2B. As shown inFIG.2A, array200may include a multijunction active region201, a top reflector region202, and a bottom reflector region203. Regions201,202, and203each include multiple layers that are grown epitaxially above a substrate204. Top and bottom reflector regions202and203may include a conductive p-type DBR and a conductive n-type DBR structure, respectively. In some embodiments, substrate204may include an n-type substrate, such as an n-type GaAs substrate or indium phosphide (InP) substrate. In some embodiments, substrate204may include an undoped substrate, such as an undoped GaAs substrate or InP substrate. Multijunction active region201may include MQW active regions (not shown), oxide layers (not shown), and at least one tunnel junction structure (not shown). For example, multijunction active region201may include N MQW active regions, N oxide layers, and N-1 tunnel junction structures, where N is an integer larger than 1, e.g., N may be 3, 4 or 5.

Because substrate204may have a thickness of 100-600 micrometers, the distance between active region201, i.e., the main heat source, and the bottom surface of substrate204may be ten times or more of that between active region201and the top surface of region202. Hence, the path of heat dissipation of a top-emitting VCSEL, where substrate204is attached to a submount, may be, e.g., ten times longer than that of a bottom-emitting VCSEL, where the top side of array200is attached to a submount. As such, a bottom-emitting VCSEL structure may dissipate heat more efficiently than a top-emitting VCSEL structure, and a bottom-emitting multijunction VCSEL array may overcome overheating issues more efficiently than a top-emitting multijunction VCSEL array.

Regions203,201, and202are formed sequentially in an epitaxial growth process. For example, region203may be grown epitaxially above substrate204, region201may be grown epitaxially above region203, and region202may be grown epitaxially above region201. After regions201-203are formed in the epitaxial growth process, a metal deposition process may be performed to form a metal layer209on parts of region202. Metal layer209electrically contacts the p+ layer of the DBR structure and thus is electrically connected to top reflector region202. Then, a dielectric layer208(including2081) with a material, such as silicon nitride or silicon oxide, may be deposited.

Thereafter, a selective etch process, such as a selective dry etch or dry and wet etch processes, may be performed to form an isolation trench205that separates the VCSELs of array200. In some embodiments, trench205may form, for example, connected rings in a horizontal plane, such as that shown inFIG.2B. Each ring may surround a VCSEL structure or a dummy VCSEL structure. “Dummy VCSEL structure”, as used herein, may indicate a structure that is similar to some parts of a VCSEL structure, but is not made to be a VCSEL structure and does not function as a VCSEL. In some embodiments, trench205may extend vertically through top reflector region202, multijunction active region201, and partially through bottom reflector region203, as shown inFIG.2C. Then, portions of the n-type DBR structure of bottom reflector region203are exposed. The selective etch process also exposes sides of aluminum (Al)-rich or relatively high Al-content layers that are arranged adjacent to each MQW active region of multijunction active region201.

Then, a wet oxidation process may be performed to oxidize the Al-rich layers and form multiple oxide layers. One of the oxide layers, such as an oxide layer206, is illustrated schematically inFIG.2C. Oxide layer206is arranged to form an oxide aperture207for each VCSEL emitter. A laser output beam of each VCSEL emitter is aligned with oxide aperture207. As shown inFIG.2C, top reflector region202, oxide aperture207, multijunction active region201, and bottom reflector203form an optical cavity or laser cavity. Oxide aperture207not only serves to form the laser cavity, but also to direct electrical currents through the central region of the cavity.

FIGS.2D and2Eschematically illustrate VCSEL array200in cross-sectional views after certain fabrication processes according to embodiments of the present invention. After the oxidation process, a dielectric layer may be deposited on the sidewall and bottom surface of trench205. The dielectric layer may include, for example, a silicon oxide layer or a silicon nitride layer. Then, a selective dry etch may be performed to etch out a portion of the dielectric layer at the bottom of trench205, which exposes parts of region203. Subsequently, a metal layer210may be deposited on the exposed parts of region203at the bottom of trench205. Metal layer210electrically contacts bottom reflector region203and also extends to cover parts of layer208that are on top of dummy VCSEL structures 1 and 2, as shown inFIG.2D. Next, trenches205may be filled with a dielectric material, such as polyimide, silicon oxide, or silicon nitride, and layer2081may be etched away to expose metal layers209, as shown inFIG.2D. As metal layers209and210are exposed on top of VCSELs 1 and 2 and dummy structures 1 and 2, a metal deposition process may be performed to form pad metal layers211and212. Pad metal layer211, as the anode contact of array200, may be deposited on metal layer209, and pad metal layer212, as the cathode contact of array200, may be deposited on metal layer210, as shown inFIG.2E.

FIGS.2F and2Gschematically illustrate VCSEL array200in cross-sectional views after assembly processes according to embodiments of the present invention. As VCSEL array200is configured bottom emitting, the VCSEL chip is attached to a submount213by, e.g., a flip-chip bonding method, as shown inFIG.2F. In the assembly, the bottom surface of substrate204faces upward and faces a direction away from submount213. Pad metal layers211and212face submount213downwardly and are disposed between substrate204and submount213. An electrically conductive adhesive material214is used to electrically contact pad metal layer211, and an electrically conductive adhesive material215is used to electrically contact pad metal layer212. Materials214and215bond VCSEL array200on submount213, and electrically connect pad metal layer211(the anode) and pad metal layer212(the cathode) to plated metal layers (not shown) arranged on submount213. As such, bonding wires are not needed for electrical connection between VCSEL array200and submount213. Submount213may be configured as a heat sink made of materials with high thermal conductivity. Compared with a top-emitting VCSEL array where a substrate is between the active region and the submount, a bottom-emitting VCSEL is flip-chip bonded and thus the active region becomes much closer to the submount, i.e., the heat sink. Hence, heat generated by multijunction active region201may be dissipated more efficiently with a flip-chip assembly.

As shown inFIG.2G, the bottom surface of substrate204is at the top of the assembly, and thus the bottom surface may be selectively etched to form an array of micro-lens216by a dry etch or dry and wet etch processes. Micro-lens215is configured to collimate an output laser beam coming out from VCSEL 1 or 2. Then, VCSEL array200may produce an array of collimated beams that are desirable in some 3D sensing applications.

FIGS.3A,3B, and3Ceach schematically illustrate a bottom-emitting multijunction VCSEL array300according to embodiments of the present invention.FIGS.3A and3Care cross-sectional views of array300or a chip containing array300, whileFIG.3Bis a top view.FIG.3Cshows a cross-sectional view along a line BB’ ofFIG.3B. As shown inFIG.3A, array300may include a multijunction active region301, a top reflector region302, a bottom reflector region303, and a conductive n+ contact layer304. Lines representing epitaxial layers of regions302and303are not shown inFIGS.3A,3C, and following figures for simplicity. Regions301-303and layer304are grown above a substrate305, such as a GaAs substrate or InP substrate that may be undoped or lightly doped with n-type dopants. Top and bottom reflector regions302and303may include a conductive p-type DBR and a conductive n-type DBR structure, respectively. Layer304is configured as a contact layer for the cathode electrode of a VCSEL emitter. Multijunction active region301may include MQW active regions (not shown), oxide layers (not shown), and at least one tunnel junction structure (not shown). For example, multijunction active region301may include N MQW active regions, N oxide layers, and N-1 tunnel junction structures, where N is an integer larger than 1, e.g., N may be 3, 4 or 5.

Layer304and regions303,301, and302are formed sequentially in an epitaxial process. For example, layer304may be grown epitaxially above substrate305, region303may be grown epitaxially above layer304, region301may be grown epitaxially above region303, and region302may be grown epitaxially above region301. After regions301-303are deposited in the epitaxial growth, a deposition process may be performed to deposit a metal layer310on a top surface of region302. Metal layer310electrically contacts the p+ layer of the DBR structure and thus is electrically connected to top reflector region302. Then, a dielectric layer309(including3091) with material such as silicon nitride or silicon oxide may be deposited.

Thereafter, a first selective etch process, such as a selective dry etch or dry and wet etch processes, may be performed to form an isolation trench307. The first selective etch process exposes sides of Al-rich or relatively high Al-content layers that are arranged adjacent to each MQW active region of multijunction active region301. Then, a wet oxidation process may be performed to oxidize the Al-rich layers and form multiple oxide layers. One of the oxide layers, such as an oxide layer308, is illustrated schematically inFIG.3C. Oxide layer308is arranged to form an oxide aperture for each VCSEL emitter. A laser output beam of each VCSEL emitter is aligned with the oxide aperture. After the wet oxidation process, a second selective etch process, such as a selective dry etch or dry and wet etch processes, may be performed to form an isolation trench306.

Trench306may be arranged in a region 1 above substrate305that is beside a region 2 where a group of VCSEL emitters, such as VCSEL emitters 1, 2, and 3, are configured. VCSELs emitters 1, 2, and 3 are illustrated with signs “1”, “2”, and “3” inFIG.3C, respectively. As such, trench306is outside region 2, i.e., the region of the VCSELs, and not configured for the purpose of separating the VCSELs.

In some embodiments, trench306may have a rectangular shape in a horizontal plane, such as that shown inFIG.3B. In some other embodiments, trench306may have another regular or an irregular shape in the horizontal plane. In some embodiments, trench306may adjoin trench307in a horizontal plane, such as that shown inFIG.3B. In some other embodiments, trench306may be separated from trench307in the horizontal plane. Trench306may extend vertically through top reflector region302, multijunction active region301, and bottom reflector region303, and reach and expose n+ contact layer304.

Trench307is formed to separate VCSEL emitters 1, 2, and 3. For example, parts of trench307may be arranged between VCSEL emitters 1 and 2 and between emitters 2 and 3, respectively. Trench307may have a connected-ring shape and each ring surrounds a VCSEL emitter in the horizontal plane. Trench307may extend vertically through top reflector region302, multijunction active region301, and through or partially through bottom reflector region303.

In some other embodiments, trenches306and307may be formed simultaneously in one selective etch process, e.g., the first selective etch process. Hence, the process to form the trenches may be simplified. In such a scenario, both trenches306and307may extend vertically through top reflector region302, multijunction active region301, and bottom reflector region303, and reach and expose n+ contact layer304.

FIGS.3D and3Eschematically illustrate VCSEL array300in cross-sectional views after some fabrication processes according to embodiments of the present invention. After the wet oxidation process, a dielectric layer may be deposited on the sidewalls and bottom surfaces of trenches306and307. The dielectric layer may include, for example, a silicon oxide layer or a silicon nitride layer. Then, a selective dry etch may be performed to etch out a portion of the dielectric layer at the bottom of trench306, which exposes a part of layer304. Subsequently, a metal layer311may be deposited on the exposed part of layer304at the bottom of trench306. Metal layer311electrically contacts n+ contact layer304and is made as the contact metal for the cathode.

Next, a dielectric material may be deposited and trench307may be filled with the dielectric material, such as polyimide, silicon oxide, or silicon nitride. The dielectric material may be used to make the sidewall of trench306thicker. In some other embodiments, trench307may be filled with a conductive material, e.g., a metal. After trench307is filled, layer3091may be etched out to expose metal layer310. As metal layers310and311are exposed on top of VCSELs 1-3 and at the bottom of trench306, a metal deposition process may be performed to form pad metal layers312and313. Pad metal layer312, as the anode contact of array300, covers metal layer310, and pad metal layer313, as the cathode contact of array300, covers metal layer311. Pad metal layer313also extends to cover a part of isolation layer309that is adjacent to trench306in region 1, as shown inFIG.3E. In some embodiments, pad metal layers312and313may include a thin layer of gold with a thickness between two to five micrometers.

After pad metal layers312and313are formed, another dielectric layer314, such as a silicon oxide layer, aluminum oxide layer, or silicon nitride layer, may be deposited to cover the pad metal layers and other areas that are exposed. Then, a selective etch, such as a selective dry etch, may be performed to etch away some portions of layer314to expose parts of pad metal layers312and313. For example, two portions of layer314may be removed to form openings315and one portion of layer314may be removed to form an opening316, as shown inFIG.3E.

FIGS.3F and3Gschematically illustrate VCSEL array300in cross-sectional views after some assembly processes according to embodiments of the present invention.FIG.3Fschematically shows that the bottom-emitting VCSEL array chip is attached to a submount317by, for example, flip-chip bonding. In the assembly, the bottom surface of substrate305faces upward and faces a direction away from submount317. Pad metal layers312and313face submount317downwardly and are arranged between substrate305and submount317. An electrically conductive adhesive material318is used to electrically contact pad metal layer312(the anode), and an electrically conductive adhesive material319is used to electrically contact pad metal layer313(the cathode). Materials318and319bond VCSEL array300on metal layers320and321, respectively. Metal layers320and321, deposited on submount317, may be electrically connected to the p-bus line and n-bus line, respectively. As such, bonding wires are not needed for electrical connection between VCSEL array300and submount317. Similar to submount213used to mount VCSEL array200, submount317may be configured as a heat sink and may be made of materials with high thermal conductivity. Hence similarly, heat dissipation of bottom-emitting multijunction VCSEL array300may be improved with the flip-chip assembly.

As shown inFIG.3G, the bottom surface of substrate305may be selectively etched to form an array of micro-lens322by a dry etch or dry and wet etch processes. Micro-lens320is configured to collimate an output laser beam coming out from the laser cavity of a VCSEL emitter. As such, VCSEL array300may generate an array collimated beams that are desirable in some 3D sensing applications.

FIGS.4A,4B, and4Ceach schematically illustrate a bottom-emitting multijunction VCSEL array400according to embodiments of the present invention.FIGS.4A and4Care cross-sectional views of array400or a chip containing array400, whileFIG.4Bis a top view.FIG.4Cshows a cross-sectional view along a line CC’ ofFIG.4B. As shown inFIG.4A, array400may include a multijunction active region401, a top reflector region402, a bottom reflector region403, and a conductive n+ contact layer404. Lines representing epitaxial layers of regions402and403are not shown inFIGS.4A,4C, and following figures for simplicity. Similar to regions301-303and layer304of array300, regions401-403and layer404are grown epitaxially above a substrate405, such as a GaAs substrate or InP substrate. The substrate may be undoped or doped with n-type dopants. Top and bottom reflector regions402and403may include a conductive p-type DBR and a conductive n-type DBR structure, respectively. Layer404is configured as a contact layer for the cathode electrode of a VCSEL emitter. Multijunction active region401may include MQW active regions (not shown), oxide layers (not shown), and at least one tunnel junction structure (not shown). For example, multijunction active region401may include N MQW active regions, N oxide layers, and N-1 tunnel junction structures, where N is an integer larger than 1, e.g., N may be 3, 4 or 5.

After regions401-403are deposited epitaxially, a deposition process may be performed to deposit a metal layer412on a top surface of region402. Metal layer412electrically contacts the p+ layer of the p-type DBR structure and is electrically connected to top reflector region402. Next, a dielectric layer409(including4091) with material, such as silicon nitride or silicon oxide, may be deposited.

Thereafter, a selective etch process, such as a selective dry etch or dry and wet etch processes, may be performed to form a trench406. Trench406may be used to separate VCSEL emitters, such as VCSEL emitters 1, 2, and 3. VCSELs emitters 1, 2, and 3 are illustrated with signs “1”, “2”, and “3” inFIG.4C, respectively. In some embodiments, the cross-section of trenches406may include, for example, a connected ring shape in a horizontal plane, as shown inFIG.4B. Each ring may surround a VCSEL emitter. In some other embodiments, trench406may include individual rings that are separated from each other and each surround a VCSEL structure. In some other embodiments, trench406may include one or more shapes other than a ring shape that are separated from each other and surround VCSELs 1-3 respectively. Trench406may extend vertically through top reflector region402, multijunction active region401, and bottom reflector region403, and reach and expose n+ contact layer404.

Trench406exposes sides of Al-rich or relatively high Al-content layers that are arranged adjacent to each MQW active region of multijunction active region401. Then, a wet oxidation process may be performed to oxidize the Al-rich layers and form multiple oxide layers. One of the oxide layers, such as an oxide layer407, is illustrated schematically inFIG.4C. Oxide layer407is arranged to form an oxide aperture408for each VCSEL emitter. A laser output beam of each VCSEL emitter is aligned with oxide aperture408.

FIGS.4D,4E, and4Fschematically illustrate VCSEL array400in cross-sectional views after some fabrication processes according to embodiments of the present invention. After the wet oxidation process, a process is performed to deposit a dielectric layer on the sidewall and bottom surface of trench406. Then, a portion of the dielectric layer on the bottom surface of trench406may be etched out to expose conductive layer404. After layer404is exposed at the bottom of trench406, a contact metal layer410may be deposited on the exposed part of layer404, as shown inFIG.4E. Then, a pad metal layer411may be deposited on metal layer410. Pad metal layer411also may fill trench406and is used as the anode contact of array400, as shown inFIG.4E.

Thereafter, a selective etch, such as a selective dry etch, may be performed to etch out layer4091that covers metal layers412of VCSELs 1, 2, and 3. Then, layers412are exposed, as shown inFIG.4E. Next, pad metal layers413may be deposited on metal layers412as the anode contact of array400, as shown inFIG.4F.

FIG.4Gschematically illustrates VCSEL array400in a top view after pad metal layers411and413are deposited according to embodiments of the present invention. The cross-sectional view ofFIG.4Fis along a line DD’ ofFIG.4G. As shown inFIGS.4F and4G, pad metal layer411surrounds VCSELs 1, 2, and 3 horizontally and extends vertically through top reflector region402, multijunction active region401, and bottom reflector region403, adjoins contact metal layers410, and electrically connects with n+ contact layer404. As described above, in some embodiments, pad metal layer411may have another shape or separate trench portions surrounding VCSELs 1, 2, and 3 in a horizontal plane.

FIG.4Hschematically illustrates a VCSEL array400in a cross-sectional view after some assembly processes according to embodiments of the present invention. As shown inFIG.4H, the chip of bottom-emitting VCSEL array400is bonded on a submount414by flip-chip bonding. As such, the bottom surface of substrate405faces upward and faces a direction away from submount414. Pad metal layers411and413face submount414downwardly and are configured between substrate405and submount414. An electrically conductive adhesive material415is used to electrically contact pad metal layer411(the cathode), and an electrically conductive adhesive material416is used to electrically contact pad metal layer413(the anode). Materials415and416bond VCSEL array400on metal layers417and418on submount414, respectively. Then, pad metal layers411and413are electrically connected with metal layers417and418, respectively. Metal layers417and418, formed on submount414, may be electrically connected to contact pads419and420, respectively. In some embodiments, metal layers417and418may have multiple layers for electrical connection as shown inFIG.4H. Thus, bonding wires are not needed for electrical connection between VCSEL array400and submount414. Similar to submount213used to mount VCSEL array200and submount317used to mount VCSEL array300, submount414may be configured as a heat sink and may be made of materials with high thermal conductivity. Hence similarly, heat dissipation of bottom-emitting multijunction VCSEL array400may be improved with the flip-chip assembly.

In some embodiments, for the above-described examples, an epitaxial growth, such as the epitaxial growth of multijunction active region201or301, top reflector region202or302, bottom reflector region203or303, or n+ contact layer304, may be performed by metalorganic chemical vapor deposition (MOCVD). In some embodiments, an isolation layer, e.g., silicon oxide layer or silicon nitride layer, and/or a metal layer may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, an isolation layer, e.g., silicon oxide layer or silicon nitride layer, and/or a metal layer may be deposited by a combination of at least two of CVD, PVD, and ALD.