System and method for observing threshold voltage variations

A system and method for observing threshold voltage variations are provided. A ring oscillator circuit comprises a plurality of inverters arranged in a sequential loop, a plurality of test circuits having devices under test, each coupled between a respective one of the inverters and a power supply. Each test circuit has a bypass field effect transistor (FET) having a first channel coupled between the power supply and a respective one of the inverters responsive to an individual enable signal, and a FET device under test having a second channel arranged in parallel to the first channel. A method is described for determining the threshold voltage of the device under test by disabling, for one of the inverters in the ring oscillator, the first FET device such that the device under test is coupled between the power supply and the respective inverter and affects the operating frequency of the ring oscillator.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices, and more particularly to a system and method for observing threshold voltage variations.

BACKGROUND

Semiconductors are used in integrated circuits for a wide range of applications, including personal computers, music and/or video devices, multimedia devices, digital assistants, communications devices, and so forth. In general, integrated circuits manufactured using modern semiconductor fabrication processes may be extremely consistent, with individual integrated circuits from a single wafer being substantially identical to one another in terms of performance.

However, process variations may occur. Process variations may include field effect transistor channel widths and lengths, gate oxide thicknesses, doped material concentrations, and so forth. A fairly common side-effect due to variations in the fabrication process used to create integrated circuits may be local changes in threshold voltage (ΔVTH) of transistors in the integrated circuits. A change in threshold voltage may alter leakage current, which may impact dynamic random access memory (DRAM) charge retention times, transistor operating speeds, logic gate switching speeds, and so forth.

FIG. 1ais a diagram of a prior art ring oscillator100as typically used to characterize process variations in an integrated circuit. Ring oscillator100comprises an odd number of inverters105-109arranged serially in a loop. When an integrated circuit containing ring oscillator100is powered on, ring oscillator100will also be energized and will automatically produce a clock signal at a frequency that is a function of inverters105-109. The frequency of the clock signal may be measured to determine global process variations. For example, if the frequency of the clock signal is greater than an expected frequency, then the threshold voltage of at least one of the inverters may have decreased below an expected value. Similarly, if the frequency of the clock signal is lower than the expected frequency, then the threshold voltage of at least one of the inverters may have increased beyond the expected value.

FIG. 1bis a diagram of a prior art single stage of a prior art ring oscillator150. Rather than having only inverters arranged serially in a loop, each stage of ring oscillator150comprises an inverter155and also a pass gate160. Each stage also includes an effective load165modeled as a capacitor. Effective load165may be representative of a subsequent stage coupled to pass gate160. Pass gate160may be used to make or break the loop. Pass gate160may be implemented using a field effect transistor (FET), such as an NFET or a PFET. Preferably, each stage of ring oscillator150includes a pass gate formed from the same type of FET. The use of a particular type of FET may allow for a characterization of process variations for that particular type of FET. For example, if NFETs are used to implement pass gate160, then it may be possible to determine global process variations for NFETs. Similarly, if PFETs are used, then it may be possible to determine global process variations for PFETs. By adding the pass gate transistors to the ring and observing the frequency of the ring oscillator, an average value for transistor threshold voltage variations in the particular integrated circuit device may be obtained. By implementing multiple oscillators, some having PFETs and some having NFETs, the average value for a variation in the threshold voltage for P and N FET devices may be obtained.

FIG. 2is a diagram of an integrated circuit200. Integrated circuit200includes integrated circuitry205that implements the functionality of integrated circuit200. Integrated circuit200also includes several ring oscillators such as, for example, the ring oscillator210arranged along a top side of integrated circuit200, ring oscillators215-216arranged along left and right edges of integrated circuit200, ring oscillator220arranged on a lower right hand corner of integrated circuit200, ring oscillator225formed in an interior of integrated circuit200, and so forth. A ring oscillator may also be formed along more than one edge of integrated circuit200. On a semiconductor wafer, many integrated circuits are fabricated at the same time, prior to being separated and packaged as integrated circuits. Ring oscillators may be provided as test structures at certain places on the wafer, or in the scribe line areas, and tested using wafer probes to determine whether the threshold voltages for devices in different areas of the semiconductor wafer fall within acceptable ranges, for example. Using the ring oscillators may allow for a measurement of process variations throughout integrated circuit200. In general, it is desirable to have multiple ring oscillators or alternatively to have a large ring oscillator distributed over different portions of integrated circuit200, so that the elements of the ring oscillators may encounter process variations like the circuitry in integrated circuit200.FIG. 2may illustrate an exaggerated use of ring oscillators in an integrated circuit.

The approaches of the prior art to characterizing the transistor threshold voltage variations have several disadvantages. The measurements of ring oscillator frequency may not correlate highly to the threshold voltage variations, making the measurements less reliable than desired. In the prior art, the measurements are often indicative of only an average threshold variation in the particular oscillator. Local variations within the ring oscillator may not be detectable. A continuing need thus exists for methods and circuitry to provide highly correlated measurements of threshold voltage variations, and to provide the ability to measure local variations in transistor threshold voltages on an integrated circuit or semiconductor wafer in a cost effective manner.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by embodiments of a system and a method for characterizing process variations.

In accordance with an embodiment, a method for measuring threshold voltage variations is provided, comprising providing a ring oscillator comprising a plurality of inverter circuits coupled in series, each inverter supplied with a virtual positive supply voltage and a virtual ground supply voltage; providing an NFET device under test corresponding to each of the inverters coupled between a positive voltage supply and the respective virtual voltage supply responsive to an individual enable signal; and characterizing the threshold voltage variations of the NFET devices of a process by observing the frequency of the ring oscillator when no devices under test are enabled, and further observing the frequency of the ring oscillator when one of the NFET devices is enabled.

Further method embodiments and alternative circuit and system embodiments are provided to advantageously enable the observation of device threshold variations in an integrated circuit or wafer by virtue of making simple frequency measurements while enabling individual devices under test within the ring oscillator and the threshold voltages of the devices under test correlating to the observed oscillator frequencies.

In accordance with another embodiment, a circuit is provided comprising a plurality of inverters arranged in a sequential loop; and a plurality of test circuits, with each test circuit coupled between a device power supply and a respective power supply node to a respective one of the inverters, each test circuit comprising a first field effect transistor (FET) having a first channel coupled between the reference power supply and receiving an enable signal on a gate terminal of the first FET, and a second FET having a second channel coupled in parallel to the first channel and having a gate terminal coupled to the power supply; wherein when the first FET is disabled by the enable signal, the voltage at the power supply node to the inverter is changed due to the threshold voltage of the second FET.

In accordance with another embodiment, an integrated circuit is provided, comprising integrated circuitry disposed on a substrate, the integrated circuitry configured to perform defined operations; and at least one ring oscillator disposed on the substrate, the ring oscillator configured to produce a clock signal at a frequency dependent on a configuration of elements in the ring oscillator, the ring oscillator comprising a plurality of inverters serially arranged in a loop, each receiving a virtual positive voltage supply and a virtual ground voltage supply; a plurality of header test circuits corresponding to one of the plurality of inverters, each comprising a bypass transistor receiving an enable signal on a gate terminal and having a channel coupled between a positive voltage supply and the respective virtual voltage supply and each further comprising a header transistor under test having a channel coupled between the positive voltage and the respective virtual voltage supply. A plurality of footer test circuits are also provided, each corresponding to one of the plurality of inverters, each also comprising a bypass transistor receiving an enable signal on a gate terminal and having a channel coupled between a ground voltage supply and the respective virtual ground voltage supply, and each further comprising a footer transistor under test having a channel coupled between the ground voltage supply and the respective virtual ground voltage supply; wherein the frequency of oscillation of the ring oscillator may be affected by one of a header transistor under test and a footer transistor under test, responsive to the respective bypass transistor being disabled by the corresponding one of the enable signals.

An advantage of an embodiment is that localized process variations may be quantified, permitting a greater degree of accuracy in locating process variations than in the prior art. High correlation between the observed frequency of the oscillator and the threshold voltages for both the P and N type devices under test enable reliable characterizations with simple measurements.

A further advantage of an embodiment is that localized and global process variations for both NFET and PFET transistors may be determined using a single ring oscillator. This may simplify implementation as well as reduce integrated circuit real estate used in process variation determination.

Yet another advantage of an embodiment is that the ring oscillator produces a digital output, enabling easy measurement and processing.

DETAILED DESCRIPTION

The embodiments will be described in a specific context, namely an integrated circuit for use in an electronic device, wherein there is a desire to measure fabrication process variations.

In a related co-owned pending application entitled “System and Method for Characterizing Process Variations”, filed as a provisional U.S. Patent Application on Jan. 14, 2009, Ser. No. 61/144,672, which application is hereby incorporated by reference herein in its entirety, circuitry and methods for providing an improved ring oscillator arrangement for observing local threshold voltage in MOS devices are presented. The embodiments of the present invention extend the concepts in the above referenced application, and provide alternative embodiments and improvements over the embodiments of the prior application.

FIG. 3ais a diagram of a single stage300of a ring oscillator embodiment of the prior application. Stage300includes an inverter305and a transmission gate310coupled to an input of inverter305. Transmission gate310includes an NFET315and a PFET320with their channels arranged in a parallel, and their drain terminals coupled together and their source terminals coupled together. A gate terminal of NFET315may be coupled to an “N GATE CONTROL” control signal and a gate terminal of PFET320may be coupled to a “P GATE CONTROL” control signal.

According to an embodiment provided in the prior application, the “N GATE CONTROL” and “P GATE CONTROL” control signals may be independent signals, enabling NFET315and PFET320to be turned on or off independently. When either NFET315or PFET320or both are turned on (N GATE CONTROL=1 for NFET315and P GATE CONTROL=0 for PFET320), a signal at input of inverter305may propagate to inverter305, while when both NFET315and PFET320are turned off, the signal at input of inverter305may not propagate to inverter305.

FIG. 3bis a diagram of a ring oscillator350formed from an odd number of stages300. A ring oscillator is provided comprising an odd number of stages arranged serially in a loop. As shown inFIG. 3b, ring oscillator350includes five stages355-359. Each stage355-359may have as input independent “N GATE CONTROL” and “P GATE CONTROL” control signals, for example, stage355may have as input “N GATE CONTROL (NC1)” and “P GATE CONTROL (PC1)” control signals. As discussed previously, the use of independent control signals may allow for the individual control of transistors in each pass gate in ring oscillator350.

Ring oscillator350further includes an enable input that may be used to turn ring oscillator350on or off. As shown inFIG. 3b, the enable function may be implemented as an AND gate335and an ENABLE control signal. AND gate335may have the ENABLE control signal as a first input and, depending on location of AND gate335, an output of one of the transmission gates or an inverter in the loop as a second input.

Although shown inFIG. 3bas being a part of stage359, AND gate335may also be placed in between adjacent inverter stages. Although ring oscillator350is shown with a transmission gate in each stage, alternative embodiments may have fewer transmission gates than inverter stages. The smaller number of transmission gates may simplify the characterizing of process variations while providing some degree of localized characterizing of process variations. Furthermore, the smaller number of transmission gates may help to reduce the size and complexity of the ring oscillators. However, the use of additional transistor gates will add more local observability and improve the information obtained.

FIG. 4ais a diagram illustrating ring oscillator350in a threshold voltage monitoring operation. As shown inFIG. 4a, all of the “N GATE CONTROL” control signals are set to one (1) and all of the “P GATE CONTROL” control signals, with the exception of the “P GATE CONTROL” control signal for stage356being set to one (1), are set to zero (0). This configuration results in both the NFET and the PFET in each transmission gates (except for the transmission gate in stage356) being turned on and effectively disappearing from the operation of ring oscillator350.

The transmission gate in stage356may have its NFET505turned “on” and its PFET506turned “off”. With PFET506turned off, NFET505remains in the circuit for ring oscillator350.FIG. 4bis a diagram illustrating an equivalent circuit for ring oscillator350as configured inFIG. 4a. Since NFET505remains in the ring oscillator350, it may have an impact on the frequency of ring oscillator350. That is, NFET505is now configured as a “device under test” (DUT) and the frequency measurement taken in this configuration will provide a measurement of the threshold voltage variation of the NFET505. The remaining NFET and PFET devices are effectively not in the measurement. Thus, a local threshold voltage variation measurement may be provided by this embodiment from the prior application. Measuring the ring oscillator frequency with, and without, the NFET505in the circuit provides an observation corresponding to the threshold voltage. By comparing the threshold voltage of different DUTs in different parts of the oscillator one at a time, threshold voltage variation measurements may be obtained by observing simple frequency measurements.

FIG. 5depicts in a circuit diagram one exemplary embodiment of an improved ring oscillator stage510of the present invention. InFIG. 5, the inverter stage517receives as an input from the previous stage a signal INV_in and drives an output INV_out to the next stage. A “header” circuit comprises a bypass gate implemented as a PMOS transistor513, and receiving an input enable signal NMOS_test_en, NMOS transistor515, which is available as an NMOS device under test (DUTn), and the header circuit outputs a virtual supply voltage to the inverter stage517, labeled VVDD. The supply voltage V DD remains constant.

Similarly, a “footer” circuit is provided that includes a PMOS “DUT”523, a bypass gate521which receives an enable signal PMOS_test_en as an input, and which supplies a virtual ground supply labeled VVSS to inverter519. PMOS device under test (DUTp)523is coupled between the VVSS node and the ground or lower power supply VSS.

By turning on the PMOS transistor513, the voltage VVDD can rise almost all the way to the VDD supply (the positive “rail”) as is known in the art, because the PMOS transistor513will continue to conduct so long as the gate input signal NMOS_test_en is lower than VDD by an amount greater than a threshold voltage. The resistance Rdson of the PMOS gate513is small so that the voltage difference between VDD and VVDD is likewise minimized. Similarly, by using the NMOS transistor521to couple the virtual supply VVSS node to the VSS voltage, the VVSS voltage can fall almost all the way to VSS, as the NMOS transistor521will continue to conduct so long as the gate input voltage is at least a threshold voltage above VSS, as provided by inverter519. Thus, when the test circuits DUTn and DUTp are bypassed, they are essentially out of the circuit. Further, by making the bypass gate transistors larger than the DUT transistors, additional current is available to the load, effectively the header and footer circuits are “out of the circuit” when the test_en input signals are in an “inactive” state, as VVDD approaches VDD for all of the stages and VVSS approaches VSS for all of the stages in the oscillator. The sizes of the transistors513and521, may be controlled to ensure that the virtual voltages approach the VDD and VSS voltages when the test devices515and523are out of the circuit.

Note that although the embodiment ofFIG. 5depicts a ring oscillator stage embodiment whereby, in a single stage, both NMOS and PMOS threshold voltage variations may be observed by individually placing the respective device under test (DUTn515or DUTp523, depending on the configuration) in the circuit, alternative embodiments of the present invention include forming an inverter stage embodiment with only a “header” portion to test the NMOS voltage threshold variation, and elsewhere forming an inverter stage embodiment with only a “footer” portion to test the PMOS voltage threshold variation. Ring oscillators having only NMOS DUT devices or PMOS DUT devices could then be formed and used for separate measurements of the P and N MOS voltage threshold variations. These alternative embodiments, although less efficient in terms of silicon area, are also envisioned as additional embodiments of the present invention and fall within the scope of the appended claims.

FIG. 6is a diagram illustrating a13stage ring oscillator using the embodiments of the invention. InFIG. 6, the test control signals are shown as a PMOS_test_en and an NMOS_test_en group of signals, one bit of the respective signal group is directed to each inverter stage. Thus, by putting a “0” on all of the test enable signals, none of the DUTn or DUTp devices is in the circuit and the ring oscillator will operate at its natural frequency.

However, in a testing scenario, by placing a “0” in one of the test enable signals, for either a DUTn or a DUTp in one of the stages, the embodiment can test one of the P or N DUTs by putting them into the circuit. Further, each stage of the oscillator may be individually selected, and P and N devices may be individually tested to monitor local threshold voltage variations in the MOS devices.

FIG. 7adepicts in a circuit diagram the implementation of a five stage ring oscillator500using the embodiment inverter stage circuit510ofFIG. 5for each of the five stages555-559, and labeled1-5. Each of the header circuits will receive a respective bit from the group of NMOS_test_en signals, and each of the footer circuits will receive a respective bit from the group of PMOS_test_en signals. The stages,555,556,557,558and559are coupled in a ring or loop, with the output of one stage forming the input of the next, and an ENABLE signal will enable the ring oscillator to run, or not by the action of an AND gate511.

FIG. 7bdepicts the ring oscillator500in an example test operation. In this example, all of the NMOS_test_en control signals are set to zero and all of the PMOS_test_en control signals are also set to zero, with the exception of the NMOS_test_en control signal for stage557being set to one (1). This configuration results in the NMOS FET565being in the circuit as the DUT, and this DUTn device will be “in the circuit” forming the ring oscillator. The remaining stages are all configured to bypass the test devices DUTn and DUTp in each stage.

Note that the DUTp in the footer portion of stage557is still bypassed and is not in the oscillator circuit. The frequency of the oscillator may now be affected by the device DUTn therefore, the frequency measurement provides a measurement correlating to the threshold voltage of NMOS FET565. Each DUTn and DUTp device may be placed individually in the circuit by varying the PMOS_test_en and NMOS_test_en signals. In each test configuration, for the respective one of the stages, the DUTn or DUTp is placed in the circuit and the frequency of the ring oscillator observed then provides a measurement correlating to the threshold voltage of that particular device. By comparing the threshold voltages against an expected threshold or against other measurements, threshold voltage variation can be determined. Local variations can be determined for any particular stage. Process characterization for a device, group of devices, or for a wafer may be quickly performed by simple frequency measurements.

FIG. 7cis a diagram illustrating the equivalent circuit of the ring oscillator500as configured inFIG. 7b. NMOS FET565is shown in the circuit for the stage ‘3’ inverter, the remaining stages have the test devices bypassed and so these DUTs are not in the circuit. The voltage VVDD at the supply input to inverter3is now lowered by the threshold voltage Vthn of the NMOS FET565, that is VVDD is approximately VDD-Vthn. Also, the presence of the device565affects the input voltage of the next stage4, as the output of the stage3inverter is also lowered by the threshold voltage Vtn. The frequency of operation of the oscillator is therefore affected. Measuring the frequency of the oscillator provides a correlating measurement of the Vtn threshold voltage of NMOS FET565. Note that unlike the prior art ring oscillators, this frequency measurement corresponds to the threshold voltage contribution of a single DUT and is not an “average”, so that local device threshold variations may be observed from simple frequency measurements. Faster and slower devices may appear in different portions of a device or wafer and this information is important in determining the causes of process variation, for example.

Pulse575represents a pulse provided as an output of stage3to stage4. Pulse575may be reduced, due to the fact DUT565, an NMOS FET, is in the circuit, by an amount substantially equal to the threshold voltage of NFET565(VTHN). If the VTHN is large, then pulse575may be significantly lower at its peak than VDD (the normal level), while if VTHN is small, then pulse575may be about equal to VDD. Therefore, if pulse575is small, then the output of inverter stage4may be slowed due to the small voltage potential (and correspondingly small current) of the input pulse575, thereby further impacting the frequency of ring oscillator500. The frequency of ring oscillator500may then be measured and used to determine threshold voltage variations present in NFET565(if any).

The above discussion focuses on turning on and off various bypass gates in the “header” circuits between VDD and the VDD supply VVDD to inverters in the ring oscillator. These configurations are used in order to obtain measurements corresponding to localized process variations for NFETs. In a similar technique, various bypass gates in the footer circuits may be turned on and off to obtain localized process variation measurements for the DUTp PFETs for the inverter stages of the oscillator. Therefore, the discussion of the characterization of localized process variations for NFETs should not be construed as being limiting to either the scope or the spirit of the embodiments. The embodiments easily allow for measuring the local threshold voltage variations in the PFETs as well, again by using simple oscillator frequency measurements.

In order to further illustrate the effect of adding a DUT to the ring oscillator on operation of the oscillator,FIG. 8is a circuit diagram illustrating a two stage portion of a ring oscillator700. Stage601and stage603of ring oscillator700are shown. Each stage601and603includes an inverter517and a header circuit comprised of a bypass PMOS gate513receiving a control input from the NMOS_test_en signals, an NMOS test device515, the header circuits providing a virtual supply voltage VVDD to the inverters517for each stage. Each stage601and603also includes a footer circuit comprised of an NMOS bypass gate521receiving a control signal and a PMOS device under test523. For discussion purposes, NMOS transistor565, in stage601is referred to as DUTn.

As shown inFIG. 8, DUTn565is “in the circuit” of the ring oscillator700because the PMOS transistor513is turned off by the ‘1’ signal on its gate, meaning the respective signal from NMOS_test_en at stage601is active. The remaining bypass gates of stage601and stage603are all turned on, so the remaining devices under test are not in the circuit. The virtual supply voltage coupled to inverter517in stage601is therefore reduced by the threshold voltage Vthn of the test device, DUTn565. Again, the pulse at the input of the stage603is shown with a magnitude reduced by the threshold voltage of DUTn device565.

The frequency of the oscillator is therefore affected both by the reduced VDD supply to the inverter of stage601, which will affect the switching speed of the inverter517in stage601, and the reduction in magnitude of the output pulse, which is input to stage603.

FIG. 9depicts a representative embodiment inverter stage implemented in a current semiconductor process, for example a 65 nanometer CMOS process, or smaller. The length and width ratios of the bypass transistor devices are shown, with Lp for the PMOS bypass gate513being 0.04 um, and Wp being 1.23 um, while for the NMOS bypass gate of the footer circuit, the length Ln was 0.04 um while the width Wn was 0.93 um. The inverters517each comprise, as is known to those skilled in the art, a PMOS pull up and an NMOS pull down transistor, in this illustrative example implementation, the sizes of those devices was Lp=0.2 um, Wp=1.23 um. Ln=0.2 um Wn=0.93 um.

FIGS. 10aand10bdepict results obtained in a Monte Carlo simulation using the ring oscillator stage ofFIG. 9to form a13stage oscillator. In the simulation, local stage variations for device process parameters were introduced. A thousand point simulation was conducted using the process conditions corner TT.

InFIG. 10a, the NMOS results are shown. The vertical axis is the ring frequency, in Mhz, observed. The horizontal axis is the threshold voltage for the NMOS DUT transistors in volts. As the threshold voltage increases, the frequency decreases, and the reader should note the inverse linear relationship between oscillator frequency and Vthn. Similarly,FIG. 10bshows the threshold voltage and oscillator frequency data obtained for the PMOS DUT transistors in these simulations.

InFIG. 11, a method embodiment for obtaining the threshold voltage variations for, as an example, the NMOS devices in a circuit comprising the ring oscillator embodiments of the invention, is depicted as a flow diagram.

In step1105, the method begins by configuring each stage in the ring oscillator, which can be any odd number of stages such as5,7,9,13,27, etc. as examples, to bypass the test devices. In this configuration, the oscillator frequency is not impacted by any of the test devices.

In step1107, a baseline or nominal frequency for the oscillator is obtained.

In step1109, a first stage is selected for taking test measurements.

In step1111, a loop of steps begins. The selected stage is configured using the NMOS_test_en signal for that stage to put the device under test DUTn for that stage in the oscillator circuit. Since the bypass gate for the NMOS devices under test is a PMOS transistor, this means setting the NMOS_test_en control signal for that stage to a ‘1’ while maintaining all other NMOS_test_en signals as a ‘0’. Similarly the PMOS_test_en signals would be set to a ‘0’ for every stage in the oscillator.

In step1113, the frequency is measured with the test device of the selected stage in the circuit.

In step1115, the threshold voltage is computed and stored. Alternatively, the frequency obtained may be stored for later statistical analysis.

In step1117, the control signal NMOS_test_en for the selected stage is returned to ‘0’.

In step1119, a conditional step is shown. If additional inverter stages that have not been tested exist, the Y branch is taken, and the process continues to step1121. If there are no more inverter stages to test, the N branch is taken and the method ends.

In step1121, a new inverter stage is selected and the method returns to step1111, where it continues.

The example method embodiment ofFIG. 11is shown using the NMOS devices under test to illustrate the method. The method then is performed using the PMOS_test_en signals to select and measure the ring oscillator frequency with each of the PMOS devices under test in the circuit. For simplicity and to avoid unnecessary duplication, this process is not explicitly shown but the use of the term PMOS_test_en wherever the term “NMOS_test_en” appears, and the use of the term DUTp wherever the term “DUTn” appears inFIG. 11provides the steps for the PMOS device threshold voltage measurements.

FIG. 12aprovides, in a table, the results obtained for the frequency of the13stage oscillator example simulated using the stage embodiment shown inFIG. 9.FIG. 12aprovides the results when no DUTs are in the circuit, with an average frequency obtained as 330.23 Mhz. The standard deviation STD was 1.16. The ratio of the standard deviation STD over the average is therefore 0.35%.FIG. 12bdepicts the simulation results obtained when, for one of the stages, one NMOS DUT is placed in the circuit, with local threshold variations. The correlation coefficient observed between the NMOS threshold voltage variation and the frequency was −0.950. This is a very good correlation which indicates that the oscillator frequency is a very useful measurement of threshold variation for the NMOS devices. The oscillator operation frequency is notably lowered by the presence of the DUTn transistor. Note that the average oscillator frequency is now 172.43 Mhz, while the standard deviation was 15.54 (very much higher than before, due to the presence of the DUTn devices and the local threshold voltage variations).

Similarly,FIG. 12cdepicts the simulation results obtained when one of the PMOS DUTs was introduced into the circuit, and the simulation included local threshold voltage variation in the DUTp devices. The correlation coefficient was observed as −0.946; again very high and very similar to the NMOS DUT case ofFIG. 12b. This correlation is particularly significant as the prior approaches, including the transfer gates used in the related application, did not achieve correlation this high for the PMOS devices. Thus, the embodiments of the present invention provide a simple measurement (frequency of a ring oscillator) that is highly correlated to the threshold voltage variations of the PMOS and NMOS devices under test, and which provides the ability to make local observations of threshold voltage variations. The average frequency was higher than for the NMOS DUTs but still substantially less than for the ring oscillator without DUTs in the circuit, and the frequency STD was 17.89, with the STD/average 10.57%. So from the ring oscillator without any DUTs in the circuit, the STD/Average ratio increased from less than 1% to over 9%.