SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first doped nitride semiconductor layer, and a second doped nitride semiconductor layer. The first nitride semiconductor layer is formed on the substrate. The second nitride semiconductor layer is formed on the first nitride semiconductor layer and has a band gap greater than a band gap of the first nitride semiconductor layer. The first doped nitride semiconductor layer is formed on the second nitride semiconductor layer. The second doped nitride semiconductor layer is formed on the second nitride semiconductor layer. A dopant of the first doped nitride semiconductor layer is different from a dopant of the second doped nitride semiconductor layer.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including different types of doped nitride semiconductor layers and a manufacturing method thereof.

2. Description of the Related Art

Components that include direct bandgap semiconductors, for example, semiconductor components including group III-V materials or group III-V compounds (Category: III-V compounds), can operate or work under a variety of conditions or in a variety of environments (e.g., at different voltages and frequencies) due to their characteristics.

The semiconductor components may include a heterojunction bipolar transistor (HBT), a heterojunction field effect transistor (HFET), a high-electron-mobility transistor (HEMT), a modulation-doped FET (MODFET) and the like.

SUMMARY

In some embodiments of the present disclosure, a semiconductor device is provided. The semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first doped nitride semiconductor layer, and a second doped nitride semiconductor layer. The first nitride semiconductor layer is formed on the substrate. The second nitride semiconductor layer is formed on the first nitride semiconductor layer and has a band gap greater than a band gap of the first nitride semiconductor layer. The first doped nitride semiconductor layer is formed on the second nitride semiconductor layer. The second doped nitride semiconductor layer is formed on the second nitride semiconductor layer. A dopant of the first doped nitride semiconductor layer is different from a dopant of the second doped nitride semiconductor layer.

In some embodiments of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first operating device and a second operating device. The first operating device includes a first doped nitride semiconductor layer and a first conductive structure. The first doped nitride semiconductor layer is formed on a second nitride semiconductor layer. The second nitride semiconductor layer is on the first nitride semiconductor layer and the second nitride semiconductor layer has a band gap greater than a band gap of the first nitride semiconductor layer. The first conductive structure is formed on the first doped nitride semiconductor layer. The second operating device is separated from the first operating device and includes a second doped nitride semiconductor layer and a second conductive structure. The second doped nitride semiconductor layer is formed on the second nitride semiconductor layer. The second conductive structure is formed on the second doped nitride semiconductor layer. The first doped nitride semiconductor layer and the second doped nitride semiconductor layer have substantially identical thickness.

In some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes forming a substrate; forming a first nitride semiconductor layer on the substrate; forming a second nitride semiconductor layer on the first nitride semiconductor layer, the second nitride semiconductor layer having a band gap greater than a band gap of the first nitride semiconductor layer; forming a first doped nitride semiconductor layer on the second nitride semiconductor layer; forming a dielectric layer on the second nitride semiconductor layer; and performing an ion implantation on a first region of the first doped nitride semiconductor layer to form a second doped nitride semiconductor layer.

The enhancement-mode semiconductor device and the depletion-mode semiconductor device can be provided or integrated for one semiconductor device by utilizing, for example, the photo mask or the ion implantation. The manufacturing process can be simple without requiring multiple photo masks. In some embodiments, the doped nitride semiconductor layer of the semiconductor device can be transformed into N-type doping from P-type doping by applying ion implantation. Accordingly, the damage to the nitride semiconductor layer can be decreased due to the applied ion implantation. The thickness of the nitride semiconductor layer can be controlled accurately. The uniformity and reliability such as the threshold voltage of the semiconductor device can thus be improved.

DETAILED DESCRIPTION

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

A direct band gap material, such as a group III-V compound, may include but is not limited to, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), Indium gallium arsenide (InGaAs), Indium aluminum arsenide (InAlAs), and the like.

FIG.1is a cross-sectional view of a semiconductor device10according to some embodiments of the present disclosure.

The semiconductor device10may include an operating device10aand an operating device10b. The operating device10acan be arranged adjacent to the operating device10b. In some embodiments, the operating device10acan include an enhancement-mode semiconductor device. In some embodiments, the operating device10bcan include a depletion-mode semiconductor device. Both the enhancement-mode semiconductor device and the depletion-mode semiconductor device can be provided or integrated for the semiconductor device10.

As shown inFIG.1, the semiconductor device10may include a substrate101, a nitride semiconductor layer102, a nitride semiconductor layer103, a doped nitride semiconductor layer104, a doped nitride semiconductor layer105, a passivation layer120, and a plurality of conductive structures106,107,110,111,112and113.

The substrate101may include, for example, but is not limited to, silicon (Si), doped silicon (doped Si), silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or another semiconductor material. In some embodiments, the substrate101may include an intrinsic semiconductor material. In some embodiments, the substrate101may include a P-type semiconductor material. In some embodiments, the substrate101may include a silicon layer doped with boron (B). In some embodiments, the substrate101may include a silicon layer doped with gallium (Ga). In some embodiments, the substrate101may include an n-type semiconductor material. In some embodiments, the substrate101may include a silicon layer doped with arsenic (As). In some embodiments, the substrate101may include a silicon layer doped with phosphorus (P).

The nitride semiconductor layer102may be disposed on the substrate101. The nitride semiconductor layer102may include group III-V materials. The nitride semiconductor layer102may be a nitride semiconductor layer. The nitride semiconductor layer102may include, for example, but is not limited to, group III nitride. The nitride semiconductor layer102may include, for example, but is not limited to, GaN. The nitride semiconductor layer102may include, for example, but is not limited to, AlN. The nitride semiconductor layer102may include, for example, but is not limited to, InN. The nitride semiconductor layer102may include, for example, but is not limited to, compound InxAlyGa1-x-yN, where x+y≤1. The nitride semiconductor layer102may include, for example, but is not limited to, compound AlyGa(1-y)N, where y≤1.

The nitride semiconductor layer103may be disposed on the nitride semiconductor layer102. The nitride semiconductor layer103may include group III-V materials. The nitride semiconductor layer103may be a nitride semiconductor layer. The nitride semiconductor layer103may include, for example, but is not limited to, group III nitride. The nitride semiconductor layer103may include, for example, but is not limited to, compound AlyGa(1-y)N, where y≤1. The nitride semiconductor layer103may include, for example, but is not limited to, GaN. The nitride semiconductor layer103may include, for example, but is not limited to, AlN. The nitride semiconductor layer103may include, for example, but is not limited to, InN. The nitride semiconductor layer103may include, for example, but is not limited to, compound InxAlyGa1-x-yN, where x+y≤1.

A heterojunction may be formed between the nitride semiconductor layer103and the nitride semiconductor layer102. The nitride semiconductor layer103may have a band gap greater than a band gap of the nitride semiconductor layer102. For example, the nitride semiconductor layer103may include AlGaN that may have a band gap of about 4 eV, and the nitride semiconductor layer102may include GaN that may have a band gap of about 3.4 eV.

In the semiconductor device10, the nitride semiconductor layer102may be used as a channel layer. In the semiconductor device10, the nitride semiconductor layer102may be used as a channel layer disposed on a buffer layer (not shown). In the semiconductor device10, the nitride semiconductor layer103may be used as a barrier layer. In the semiconductor device10, the nitride semiconductor layer103may be used as a barrier layer disposed on the nitride semiconductor layer102.

In the semiconductor device10, because the band gap of the nitride semiconductor layer102is less than the band gap of the nitride semiconductor layer103, two dimensional electron gas (2DEG) may be formed in the nitride semiconductor layer102. In the semiconductor device10, because the band gap of the nitride semiconductor layer102is less than the band gap of the nitride semiconductor layer103, 2DEG may be formed in the nitride semiconductor layer102, and the 2DEG is close to the interface of the nitride semiconductor layer103and the nitride semiconductor layer102. In the semiconductor device10, because the band gap of the nitride semiconductor layer103is greater than the band gap of the nitride semiconductor layer102, 2DEG may be formed in the nitride semiconductor layer102. In the semiconductor device10, because the band gap of the nitride semiconductor layer103is greater than the band gap of the nitride semiconductor layer102, 2DEG may be formed in the nitride semiconductor layer102, and the 2DEG is close to the interface of the nitride semiconductor layer103and the nitride semiconductor layer102.

The doped nitride semiconductor layer104may be disposed over the nitride semiconductor layer103. The doped nitride semiconductor layer104may be in direct contact with the nitride semiconductor layer103. The doped nitride semiconductor layer104may cover a portion of the nitride semiconductor layer103. The doped nitride semiconductor layer104may include N-type doped material. The doped nitride semiconductor layer104may include a group 4A element. The doped nitride semiconductor layer104may include, for example, carbon, silicon, or germanium, but is not limited thereto. The doped nitride semiconductor layer104may include, for example, hydrogen, but is not limited thereto. The doped nitride semiconductor layer104may have length L1and height H1.

The doped nitride semiconductor layer105may be disposed over the nitride semiconductor layer103. The doped nitride semiconductor layer105may be in direct contact with the nitride semiconductor layer103. The doped nitride semiconductor layer105may cover a portion of the nitride semiconductor layer103. The doped nitride semiconductor layer105may include P-type doped material. The doped nitride semiconductor layer105may have length L2and height H2.

The length L2may be substantially identical to the length L1. The length L2may be different from the length L1. The length L2may be smaller than the length L1. The length L2may be greater than the length L1. The height H2may be substantially identical to the height H1. The height H2may be different from the height H1. The height H2may be smaller than the height H1. The height H2may be greater than the height H1.

The conductive structure106may be disposed on the doped nitride semiconductor layer104. The conductive structure106may be in direct contact with the doped nitride semiconductor layer104. The conductive structure106may be surrounded by a passivation layer120. The conductive structure106may be separated from the conductive structure112. The conductive structure106may be separated from the conductive structure113. The conductive structure106may include a metal. The conductive structure106may include, for example, but is not limited to, gold (Au), platinum (Pt), titanium (Ti), palladium (Pd), nickel (Ni), or tungsten (W). The conductive structure106may include a metal compound. The conductive structure106may include, for example, but is not limited to, TiN.

In the semiconductor device10, the conductive structure106may be used as a gate electrode. In the semiconductor device10, the conductive structure106may be configured to control the 2DEG in the nitride semiconductor layer102. In the semiconductor device10, a voltage may be applied to the conductive structure18to control the 2DEG in the nitride semiconductor layer102. In the semiconductor device10, a voltage may be applied to the conductive structure106to control the 2DEG in the nitride semiconductor layer102and below the conductive structure106. In the semiconductor device10, a voltage may be applied to the conductive structure106to control the connection or disconnection between the conductive structure112and the conductive structure113.

The conductive structure107may be disposed on the doped nitride semiconductor layer105. The conductive structure107may be in direct contact with the doped nitride semiconductor layer105. The conductive structure107may be surrounded by a passivation layer120. The conductive structure107may be separated from the conductive structure110. The conductive structure107may be separated from the conductive structure111. The conductive structure107may include a metal. The conductive structure107may include, for example, but is not limited to, gold (Au), platinum (Pt), titanium (Ti), palladium (Pd), nickel (Ni), or tungsten (W). The conductive structure107may include a metal compound. The conductive structure107may include, for example, but is not limited to, TiN.

In the semiconductor device10, the conductive structure107may be used as a gate electrode. In the semiconductor device10, the conductive structure107may be configured to control the 2DEG in the nitride semiconductor layer102. In the semiconductor device10, a voltage may be applied to the conductive structure18to control the 2DEG in the nitride semiconductor layer102. In the semiconductor device10, a voltage may be applied to the conductive structure107to control the 2DEG in the nitride semiconductor layer102and below the conductive structure107. In the semiconductor device10, a voltage may be applied to the conductive structure107to control the connection or disconnection between the conductive structure110and the conductive structure111.

The conductive structures110,111,112and113may be disposed over the nitride semiconductor layer103. The conductive structures110,111,112and113may be in direct contact with the nitride semiconductor layer103. The conductive structure107can be formed between the conductive structures110and111. The conductive structure106can be formed between the conductive structures112and113.

Each of the conductive structures110,111,112and113may include a conductive material. Each of the conductive structures110,111,112and113may include a metal. Each of the conductive structures110,111,112and113may include, for example, but is not limited to, Al. Each of the conductive structures110,111,112and113may include, for example, but is not limited to, Ti. Each of the conductive structures110,111,112and113may include a metal compound. Each of the conductive structures110,111,112and113may include, for example, but is not limited to, AlN. Each of the conductive structures110,111,112and113may include, for example, but is not limited to, TiN.

In the semiconductor device10, each of the conductive structures110,111,112and113may be used as, for example, but is not limited to, a source electrode. In the semiconductor device10, each of the conductive structures110,111,112and113may be used as, for example, but is not limited to, a drain electrode.

FIG.2A,FIG.2B,FIG.2C,FIG.2D,FIG.2E,FIG.2FandFIG.2Gillustrate several operations for manufacturing a semiconductor device20according to some embodiments of the disclosure. The semiconductor device20may correspond to or can be similar to the semiconductor device10ofFIG.1.

As shown inFIG.2A, the semiconductor device20can include a substrate201, a nitride semiconductor layer202, a nitride semiconductor layer203and a doped nitride semiconductor layer204. The nitride semiconductor layer202may be formed on the substrate201. The nitride semiconductor layer202may be formed through CVD and/or another suitable deposition step. The nitride semiconductor layer203may be formed on the nitride semiconductor layer202. The nitride semiconductor layer203may be formed through CVD and/or another suitable deposition step. The doped nitride semiconductor layer204may be formed on the nitride semiconductor layer203. The doped nitride semiconductor layer204may include an epitaxial layer. The doped nitride semiconductor layer204may be formed through CVD and/or another suitable deposition step.

The nitride semiconductor layer203may be formed after forming the nitride semiconductor layer202. A heterojunction may be formed when the nitride semiconductor layer203is disposed on the nitride semiconductor layer202. A band gap of the nitride semiconductor layer203may be greater than a band gap of the nitride semiconductor layer202. Due to the polarization phenomenon of the formed heterojunction between the nitride semiconductor layer203and the nitride semiconductor layer202, 2DEG may be formed in the nitride semiconductor layer202. Due to the polarization phenomenon of the formed heterojunction between the nitride semiconductor layer203and the nitride semiconductor layer202, 2DEG may be formed in the nitride semiconductor layer202and close to an interface between the nitride semiconductor layer202and the nitride semiconductor layer203.

Referring toFIG.2B, the dielectric layer205may be formed on the doped nitride semiconductor layer204. The dielectric layer205may be formed through CVD and/or another suitable deposition step. The dielectric layer205can be used as a block layer for implanting ions into the doped nitride semiconductor layer204and protecting the nitride semiconductor layer203from damage. The dielectric layer205may include, for example, but is not limited to, an oxide material. The dielectric layer205may include, for example, but is not limited to, a nitride material.

Referring toFIG.2C, a photo mask206can be applied or attached over the dielectric layer205. The photo mask206may be used to perform a manufacturing operation, for example, ion implantation. The photo mask206may be used to perform a manufacturing operation, for example, diffusion. The photo mask206may be used to create the doped nitride semiconductor layer2041whose dopant is different from the dopant of other regions of the doped nitride semiconductor layer204. The photo mask206may be used to generate the doped nitride semiconductor layer2041whose dopant is different from the dopant of the doped nitride semiconductor layers2042and2043.

In some embodiments, the doped nitride semiconductor layer2041may include N-type doped material. In some embodiments, the doped nitride semiconductor layer2042may include P-type doped material. The doped nitride semiconductor layer2041may include a group 4A element. The doped nitride semiconductor layer2041may include, for example, carbon, silicon, or germanium, but is not limited thereto. The doped nitride semiconductor layer2041may include, for example, hydrogen, but is not limited thereto.

In some embodiments, the characteristics of the semiconductor device20, such as the threshold voltage, the parasitic capacitor, the parasitic inductor and the intrinsic delay, can be adjusted by the manufacturing operation of ion implantation. The characteristics of the semiconductor device20can be controlled by, for example, adjusting the type of the implanted ions. The characteristics of the semiconductor device20can be controlled by, for example, adjusting the injection energy of the implanted ions. The characteristics of the semiconductor device20can be controlled by, for example, adjusting the dosage or concentration of the implanted ions. The characteristics of the semiconductor device20can be controlled by, for example, adjusting the injection angel of the implanted ions. The characteristics of the semiconductor device20can be controlled by, for example, adjusting the injection area of the implanted ions.

The doped nitride semiconductor layer2041can be transformed into N-type doping from P-type doping by applying ion implantation. The damage to the nitride semiconductor layer203can be decreased due to the applied ion implantation. The thickness of the nitride semiconductor layer203can be accurately controlled. The uniformity and reliability such as the threshold voltage of the semiconductor device20can be improved.

Referring toFIG.2D, the dielectric layer205shown inFIG.2Ccan be removed. In addition, the photo mask206may be detached or removed. The conductive layer207can be formed on the doped nitride semiconductor layer204. The conductive layer207can be in direct contact with the doped nitride semiconductor layer204. The conductive layer207may be formed through CVD and/or another suitable deposition step. The doped nitride semiconductor layer204may include several doped nitride semiconductor layers2041,2042and2043. The conductive layer207can be in direct contact with the doped nitride semiconductor layer2041. The conductive layer207can be in direct contact with the doped nitride semiconductor layer2042.

Referring toFIG.2E, a manufacturing operation, for example, dry etching, may be performed to form the conductive structures2071and2072. A manufacturing operation, for example, wet etching, may be performed to form the conductive structures2071and2072. A manufacturing operation, for example, dry etching, may be performed to remove the doped nitride semiconductor layer2043and leave the doped nitride semiconductor layers2041and2042. A manufacturing operation, for example, wet etching, may be performed to remove the doped nitride semiconductor layer2043and leave the doped nitride semiconductor layers2041and2042. As shown inFIG.2E, the doped nitride semiconductor layer2041can be formed between the nitride semiconductor layer203and the conductive structure2071. The doped nitride semiconductor layer2042can be formed between the nitride semiconductor layer203and the conductive structure2072.

Referring toFIG.2F, the conductive structures210,211,212and213can be formed on the nitride semiconductor layer203. The conductive structures210,211,212and213may be formed through CVD and/or another suitable deposition step. In some embodiments, the conductive structures210and211may be formed spaced apart from the conductive structure2072. The conductive structures210and211may be formed on opposite sides of the conductive structure2072. The conductive structure2072can include a gate electrode, the conductive structure210can include a drain electrode or a source electrode, and the conductive structure211can include a source electrode or a drain electrode. In some embodiments, the conductive structures212and213may be formed spaced apart from the conductive structure2071. The conductive structures212and213may be formed on opposite sides of the conductive structure2071. The conductive structure2071can include a gate electrode, the conductive structure212can include a drain electrode or a source electrode, and the conductive structure213can include a source electrode or a drain electrode.

Referring toFIG.2G, the passivation layer220can be formed over the nitride semiconductor layer203. The passivation layer220may be formed through CVD and/or another suitable deposition step. The passivation layer220may be formed on the conductive structures210,211,212,213,2071and2072. The doped nitride semiconductor layers2041and2042, and the conductive structures210,211,212,213,2071and2072can be surrounded by the passivation layer220. The passivation layer220may include silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, and a combination thereof. The dopant of the doped nitride semiconductor layer2041may be different from the dopant of the doped nitride semiconductor layer2042. The doped nitride semiconductor layer2041may be an N-type GaN layer and the doped nitride semiconductor layer2042may be a P-type GaN layer.

Based on the foregoing, the enhancement-mode semiconductor device and the depletion-mode semiconductor device can be provided or integrated within the semiconductor device20by utilizing one photo mask206. The manufacturing process can be simple without requiring multiple photo masks. Moreover, the damage to the doped nitride semiconductor layer204can be reduced by applying the photo mask206and performing the ion implantation.

FIG.3Ais an enlarged view30aof the structure in the box20aas shown inFIG.2FandFIG.2Gaccording to some embodiments of the present disclosure. The conductive structure3071may correspond to or can be similar to the conductive structure2071ofFIG.2FandFIG.2G. The doped nitride semiconductor layer3041may correspond to or can be similar to the doped nitride semiconductor layer2041ofFIG.2FandFIG.2G. The nitride semiconductor layer303may correspond to or can be similar to the nitride semiconductor layer203ofFIG.2FandFIG.2G.

The conductive structure3071may be formed on the doped nitride semiconductor layer3041. The conductive structure3071may be in direct contact with the doped nitride semiconductor layer3041. The doped nitride semiconductor layer3041may be formed on the nitride semiconductor layer303. The doped nitride semiconductor layer3041may be in direct contact with the nitride semiconductor layer303. In some embodiment, the conductive structure3071can have a length L32. The doped nitride semiconductor layer3041can have a length L31. The nitride semiconductor layer303may extend along a direction parallel with the lengths L31and L32. The length L32can be substantially identical to the length L31. The doped nitride semiconductor layer3041can include N-type doped material and P-type doped material. In the doped nitride semiconductor layer3041, the concentration of the N-type doped material may be greater than the concentration of the P-type doped material. In the doped nitride semiconductor layer3041, the concentration of the P-type doped material may be greater than the concentration of the N-type doped material.

FIG.3Bis another enlarged view30bof the structure in the box20aas shown inFIG.2FandFIG.2Gaccording to some embodiments of the present disclosure. As shown inFIG.3B, the conductive structure3072can have a length L34. The doped nitride semiconductor layer3042can have a length L33. The nitride semiconductor layer303may extend along a direction parallel with the lengths L33and L34. The length L34can be different from the length L33. The length L34can be smaller than the length L33. The doped nitride semiconductor layer3042can include N-type doped material and P-type doped material. In the doped nitride semiconductor layer3042, the concentration of the N-type doped material may be greater than the concentration of the P-type doped material. In the doped nitride semiconductor layer3042, the concentration of the P-type doped material may be greater than the concentration of the N-type doped material.

FIG.3Cis another enlarged view30cof the structure in the box20aas shown inFIG.2FandFIG.2Gaccording to some embodiments of the present disclosure. The conductive structure3073can have a length L36. The doped nitride semiconductor layer3043can have a length L35. The nitride semiconductor layer303may extend along a direction parallel with the lengths L35and L36. The length L36can be different from the length L35. The length L36can be greater than the length L35. The doped nitride semiconductor layer3043can include N-type doped material and P-type doped material. In the doped nitride semiconductor layer3043, the concentration of the N-type doped material may be greater than the concentration of the P-type doped material. In the doped nitride semiconductor layer3043, the concentration of the P-type doped material may be greater than the concentration of the N-type doped material.

As shown inFIG.3C, the doped nitride semiconductor layer3043may be surrounded by the doped nitride semiconductor layers3044and3045. The doped nitride semiconductor layer3043can include N-type doped material. The doped nitride semiconductor layers3044and3045can include P-type doped material. The nitride semiconductor layer3044can be in direct contact with the lateral surface3043aof the nitride semiconductor layer3043. The lateral surface3043acan be a rugged or irregular surface due to the manufacturing operation, such as ion implantation, performed for the nitride semiconductor layer3043. The nitride semiconductor layer3045can be in direct contact with the lateral surface3043bof the nitride semiconductor layer3043. The lateral surface3043bcan be a rugged or irregular surface due to the manufacturing operation, such as ion implantation, performed for the nitride semiconductor layer3043.

FIG.4illustrates some operations to manufacture a semiconductor device according to some embodiments of the present disclosure. While disclosed operations are illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some operations may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

In operation400, a substrate can be formed. In operation402, a first nitride semiconductor layer can be formed on the substrate. In operation404, a second nitride semiconductor layer can be formed on the first nitride semiconductor layer. It should be noted that the second nitride semiconductor layer may have a band gap greater than a band gap of the first nitride semiconductor layer.

In operation406, a first doped nitride semiconductor layer can be formed on the second nitride semiconductor layer. In operation408, a dielectric layer can be formed on the second nitride semiconductor layer. In operation410, ion implantation can be performed on a first region of the first doped nitride semiconductor layer to form a second doped nitride semiconductor layer.

In operation412, a conductive layer can be formed on the first doped nitride semiconductor layer and the second doped nitride semiconductor layer. In operation414, a second portion of the first doped nitride semiconductor layer can be removed which surrounds the first portion of the first doped nitride semiconductor layer. In operation416, at least one conductive structure can be deposited on the first doped nitride semiconductor layer and the second doped nitride semiconductor layer.

As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conduction with an event or circumstance, the terms can refer to instances in which the event of circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise. The term “substantially coplanar” can refer to two surfaces within micrometers (μm) of lying along a same plane, such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of lying along the same plane. When referring to numerical values or characteristics as “substantially” the same, the term can refer to the values lying within ±10%, ±5%, ±1%, or ±0.5% of an average of the values.

Several embodiments of the disclosure and features of details are briefly described above. The embodiments described in the disclosure may be easily used as a basis for designing or modifying other processes and structures for realizing the same or similar objectives and/or obtaining the same or similar advantages introduced in the embodiments of the disclosure. Such equivalent constructions do not depart from the spirit and scope of the disclosure, and various variations, replacements, and modifications can be made without departing from the spirit and scope of the disclosure.