High voltage MOS structure and its manufacturing method

A semiconductor structure includes a HV NMOS structure. The HV NMOS structure includes a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The source region and the drain region are separated from each other. The channel region is disposed between the source region and the drain region. The channel region has a channel direction from the source region toward the drain region. The gate dielectric is disposed on the channel region and on portions of the source region and the drain region. The gate electrode is disposed on the gate dielectric. The gate electrode includes a first portion of n-type doping and two second portions of p-type doping. The two second portions are disposed at two sides of the first portion. The two second portions have an extending direction perpendicular to the channel direction.

TECHNICAL FIELD

This disclosure relates to a semiconductor structure and a method for manufacturing the same. More particularly, this disclosure relates to a semiconductor structure comprising a high-voltage (HV) NMOS structure and a method for manufacturing the same.

BACKGROUND

The metal-oxide-semiconductor (MOS) devices have been widely used in integrated circuits for their small sizes, low cost of production, ease of integration, etc. The MOS devices can be made either p-type or n-type semiconductors, and complementary pairs thereof can be used to make switching circuits with very low power consumption. Typically, in a semiconductor structure, MOS devices are disposed in both the high voltage areas and the low voltage areas, and known as high-voltage (HV) MOS devices and low-voltage (LV) MOS devices, respectively. For the operation under various conditions such as different levels of voltages, the MOS devices and the related elements may have different modified structures.

SUMMARY

This disclosure is directed to a semiconductor structure comprising a high-voltage (HV) NMOS structure and a method for manufacturing the same.

According to some embodiments, a semiconductor structure comprises a HV NMOS structure. The HV NMOS structure comprises a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The source region and the drain region are separated from each other. The channel region is disposed between the source region and the drain region. The channel region has a channel direction from the source region toward the drain region. The gate dielectric is disposed on the channel region and on portions of the source region and the drain region. The gate electrode is disposed on the gate dielectric. The gate electrode comprises a first portion of n-type doping and two second portions of p-type doping. The two second portions are disposed at two sides of the first portion. The two second portions have an extending direction perpendicular to the channel direction.

According to some embodiments, a method for manufacturing a semiconductor structure comprises forming a HV NMOS structure. The formation of the HV NMOS structure comprises the following steps. First, a source region and a drain region are formed in a substrate. The source region and the drain region are separated from each other and define a channel region therebetween. The channel region has a channel direction from the source region toward the drain region. Then, a gate dielectric is formed on the channel region and on portions of the source region source region and the drain region. A gate electrode is formed on the gate dielectric. The formation of the gate electrode comprises the following steps. First, an intrinsic polysilicon layer is formed on the gate dielectric. The intrinsic polysilicon layer has a first portion and two second portions at two sides of the first portion. The two second portions have an extending direction perpendicular to the channel direction. Then, the first portion of the intrinsic polysilicon layer is implanted with a n-type dopant. The two second portions of the intrinsic polysilicon layer are implanted with a p-type dopant.

DETAILED DESCRIPTION

Various embodiments will be described more fully hereinafter with reference to accompanying drawings. For clarity, the components in the figures may not be drawn to scale. It is contemplated that elements and features of one embodiment may be beneficially incorporated in another embodiment without further recitation.

Referring toFIGS. 1A-1C, an exemplary semiconductor structure according to embodiments is shown, whereinFIG. 1Aillustrates a top view,FIG. 1Billustrates a cross-sectional view along the line B-B′ inFIG. 1A, andFIG. 1Cillustrates a cross-sectional view along the line C-C′ inFIG. 1A. This semiconductor structure comprises a HV NMOS structure100. The HV NMOS structure100comprises a source region110, a drain region120, a channel region106, a gate dielectric130, and a gate electrode140. The source region110and the drain region120are separated from each other. The channel region106is disposed between the source region110and the drain region120. The channel region106has a channel direction D from the source region110toward the drain region120. The gate dielectric130is disposed on the channel region106and on portions of the source region110and the drain region120. The gate electrode140is disposed on the gate dielectric130. The gate electrode140comprises a first portion142of n-type doping and two second portions144and146of p-type doping. The two second portions144and146are disposed at two sides of the first portion142. As shown inFIG. 1A, the two second portions144and146have an extending direction perpendicular to the channel direction D.

More specifically, according to some embodiments, the HV NMOS structure100may comprise a substrate102, a first n-type doped region112, a second n-type doped region122, an isolation structure104, a first n-type heavily doped region114, and a second n-type heavily doped region124. The substrate may be a p-type substrate. The first n-type doped region112and the second n-type doped region122are disposed in the substrate102and separated from each other. The first n-type doped region112is disposed in the source region110, and the second n-type doped region122is disposed in the drain region120. The isolation structure104is disposed in the substrate102. The isolation structure104, such as a shallow trench isolation (STI) structure, has a first through opening and a second through opening in the first n-type doped region112and the second n-type doped region122, respectively. The first n-type heavily doped region114and the second n-type heavily doped region124are disposed in the first through opening and the second through opening, respectively. As such, the first n-type heavily doped region114is disposed in the source region110, and the second n-type heavily doped region124is disposed in the drain region120.

The gate dielectric130has a central portion having a first thickness t1and an edge portion having a second thickness t2smaller the first thickness t1. More specifically, except for the edge portion on the isolation structure104, the gate dielectric130is so thick that it is partially formed into the substrate102due to the manufacturing process. Such thick gate dielectric is suitable for a HV NMOS structure, which is operated under a high voltage that may be equal to or higher than 20 V, such as 32 V.

The gate electrode140, as described above, comprises a first portion142of n-type doping and two second portions144and146of p-type doping at two sides of the first portion142. As shown inFIG. 1B, the two second portions144and146of the gate electrode140may be disposed above the source region110and the drain region120. In some embodiments, the portions116and126of the source region110and the drain region120, on which the gate dielectric130is disposed, are completely under the two second portions144and146of the gate electrode140.

Referring toFIGS. 2A-2C, another exemplary semiconductor structure according to embodiments is shown, whereinFIG. 2Aillustrates a top view,FIG. 2Billustrates a cross-sectional view along the line B-B′ inFIG. 2A, andFIG. 2Cillustrates a cross-sectional view along the line C-C′ inFIG. 2A. This exemplary semiconductor structure comprises a HV NMOS structure200. The HV NMOS structure200differs from the HV NMOS structure100in the configuration of the gate electrode. The gate electrode240of the HV NMOS structure200comprises a first portion242of n-type doping and two second portions244and246of p-type doping disposed at two sides of the first portion242. The two second portions244and246have an extending direction perpendicular to the channel direction D. The gate electrode240further comprises two other second portions248and250of p-type doping at two other sides of the first portion142. The two other second portions248and250have an extending direction parallel to the channel direction D.

Now referring toFIG. 3A, a comparative semiconductor structure is shown. The comparative semiconductor structure comprises a HV NMOS structure300. The gate electrode340of the HV NMOS structure300does not comprise any second portion of p-type doping as described above. In other words, the gate electrode340is completely of n-type doping.

The transconductance (Gm)-gate-source voltage (Vgs) curves of the HV NMOS structure300with various base-source voltages (Vbs) are shown inFIG. 3B. As shown inFIG. 3B, two kinks may be observed in a Gm-Vgs curve, as indicated by arrows A1and A2. The kink indicated by the arrow A1may originate from a lower threshold voltage at regions R1(FIG. 3A). It is lower than the desired threshold voltage of the HV NMOS structure, which may be properly presented by the main portion of the gate structure on the channel region. Such lower threshold voltage may be caused by the thinner thickness of the gate dielectric at the regions R1and a segregation of the p-type dopant, such as boron, at the edge of the isolation structure, and may lead to an turn-on at edge portions of the HV NMOS structure earlier than the turn-on of the main portion of the HV NMOS structure. The kink indicated by the arrow A2may originate from a larger threshold voltage at regions R2(FIG. 3A). Such larger threshold voltage may be caused by a parasitic phenomenon at regions R2between the n-type doped gate electrode340and the n-type doped regions of the source and drain regions, and may lead to one more turn-on of the HV NMOS structure.

The embodiments described above can solve the problems, and particular can soothe the kink indicated by the arrow A2. Referring back toFIGS. 1A-1C, in the HV NMOS structure100, two second portions144and146of p-type doping are disposed at two sides of the first portion142of n-type doping. The second portions144and146extending perpendicular to the channel direction D are substantially disposed on the first and second n-type doped regions112and122of the source and drain regions110and120. As such, the threshold voltage at the corresponding regions increases by about 1.4V due to the arrangement of the p-type doped second portions144and146, compared to the cases in which n-type doped gate electrode are used in the corresponding regions as shown inFIG. 3A. The increase of the threshold voltage suppresses the parasitic phenomenon, and thereby soothes the kink indicated by the arrow A2.

In addition, according to some embodiments, the kink indicated by the arrow A1may also be soothed. Referring back toFIGS. 2A-2C, in the HV NMOS structure200, two other second portions248and250of p-type doping are disposed at two other sides of the first portion242of n-type doping. The second portions248and250extending parallel to the channel direction D are substantially disposed along the edges between the channel region106and the isolation structure104. Such arrangement increases the threshold voltage at edge portions of the HV NMOS structure, and thereby soothes the kink indicated by the arrow A1.

Now Referring toFIGS. 4A-4F, an exemplary method for manufacturing a semiconductor structure according to embodiments is shown. The method comprises forming a HV NMOS structure, which is illustrated as the HV NMOS structure100for example. The formation of the HV NMOS structure comprises the following steps. It is contemplated that one or more steps may be added or removed, and/or the sequence of the steps may be changed, while they are possible.

As shown inFIG. 4A, a source region110and a drain region120are formed in a substrate102. The source region110and the drain region120are separated from each other and define a channel region106therebetween. The channel region106has a channel direction D from the source region110toward the drain region120. More specifically, according to some embodiments, a first n-type doped region112and a second n-type doped region122are formed in the substrate102, which may be a p-type substrate. The first n-type doped region112and the second n-type doped region122are separated from each other. The first n-type doped region112is formed in the source region110, and the second n-type doped region122is formed in drain region120. An isolation structure104, such as a shallow trench isolation (STI) structure, is formed in the substrate102. The isolation structure104has a first through opening404and a second through opening406in the first n-type doped region112and the second n-type doped region122, respectively.

As shown inFIG. 4B, a gate dielectric130is formed on the channel region106and on a portion116of the source region110and a portion126of the drain region120. The gate dielectric130may be formed of oxide or the like. The gate dielectric130has a central portion having a first thickness t1and an edge portion having a second thickness t2smaller the first thickness t1.

Then, a gate electrode140is formed on the gate dielectric130. First, as shown inFIG. 4C, an intrinsic polysilicon layer408is formed on the gate dielectric130. In the case illustrated inFIGS. 4A-4F, the intrinsic polysilicon layer408has a first portion410and two second portions412at two sides of the first portion410. The two second portions412have an extending direction perpendicular to the channel direction D. The two second portions412of the intrinsic polysilicon layer408may be located above the source region source region110and the drain region120. In some embodiments, the portions116and126of the source region110and the drain region120, on which the gate dielectric130is disposed, are completely under the two second portions412of the intrinsic polysilicon layer408. In a case in which the semiconductor structure as shown inFIGS. 2A-2Cis formed, the intrinsic polysilicon layer408further comprises two other second portions412of p-type doping at two other sides of the first portion410, and the two other second portions412have an extending direction parallel to the channel direction D.

As shown inFIG. 4D, the first portion410of the intrinsic polysilicon layer408is implanted with a n-type dopant, as indicated by arrows414, so as to form said first portion142. A photoresist416may be provided on the structure, and expose the desired areas to be implanted. The n-type dopant may be selected from the group consisting of phosphorous and arsenic, and a doping concentration of the n-type dopant may be in a magnitude of 10−15cm−3. In some embodiments, as shown inFIG. 4D, the first n-type doped region112exposed by the first through opening404and the second n-type doped region122exposed by the second through opening406are also exposed by the photoresist416. The first n-type doped region112and the second n-type doped region122exposed by the first through opening404and the second through opening406are implanted with the n-type dopant, so as to form a first n-type heavily doped region114in the source region110and a second n-type heavily doped region124in the drain region120.

As shown inFIG. 4E, in the case illustrated inFIGS. 4A-4F, the two second portions412of the intrinsic polysilicon layer408are implanted with a p-type dopant, as indicated by arrows418, so as to form said second portions144and146. A photoresist420may be provided on the structure, and expose the desired areas to be implanted. The p-type dopant may be boron, and a doping concentration of the p-type dopant may be in a magnitude of 10−15cm−3. In a case in which the semiconductor structure as shown inFIGS. 2A-2Cis formed, the two other second portions412as described above are also implanted with the p-type dopant at this step.

In some embodiments, the implantation steps as shown inFIG. 4DandFIG. 4Emay be exchanged. Both implantation steps are typically carried out in the manufacturing process of a semiconductor structure, particularly a semiconductor device comprises both p-type and n-type doped areas, such as a semiconductor device comprises CMOS structures. As such, the second portions144and146of the gate electrode140can be formed by simply modifying the arrangement of photoresists416and420without any additional processing step. It can be appreciated that the first portion142, the second portions144and146, the first n-type heavily doped region114, and the second n-type heavily doped region124may have doping concentrations in the same or a similar order of magnitude, and their doping concentrations are higher than the doping concentration of the first n-type doped region112and the second n-type doped region122.

Thereafter, as shown inFIG. 4F, the photoresist420is removed, and a semiconductor structure comprising the HV NMOS structure100can be formed. It can be appreciated that further processing steps that are typically carried out in the manufacturing process of a semiconductor structure may also be conducted.

Based on the above, a semiconductor structure without being affected by the parasitic phenomenon can be provided through simple modifications of the photoresists used in implantation processes. The parasitic phenomenon is soothed by the arrangement of the p-type doped portions of the gate electrode that are at two sides of the n-type doped portion and extend perpendicular to the channel direction.