Method of manufacturing a semiconductor device

A heat treatment for diffusing impurity ions implanted into a silicon layer is performed at a heat treatment temperature which is less than an aggregation temperature of the silicon layer. A thermal aggregation of the silicon layer can be inhibited, thereby reducing a silicon deficiency of the silicon layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of manufacturing a semiconductor device which is formed in silicon layer located on an insulating layer, or on a silicon-on insulator (SOI) substrate.

The present application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2001-160597, filed May 29, 2001, which is herein incorporated by reference in its entirely for all purposes.

2. Description of the Related Art

A field effect transistors are now typically formed on the SOI substrate (which is called an SOI-FET) instead of the more conventional bulk semiconductor substrate. The SOI-FET is formed in the thin silicon layer (the SOI layer) which is formed on the insulating layer of the SOI substrate. Since a junction capacitance is reduced by such a structure, the SOI-FET can operate at a high-speed. Particularly, a fully depleted SOI-FET formed in the SOI layer is known as a low-power device which has a small parasitic capacitance and a sub-threshold swing which is smaller than that of the conventional bulk semiconductor substrate. The fully depleted transistor has a depletion layer that expand to the bottom surfaces of a source region and a drain region, when a voltage is supplied to a gate electrode thereof. Since an expansion of the depleted layer of the fully depleted SOI-FET is defined by a thickness of the. SOI layer, a short channel effect can be inhibited. Thus, the thickness of the SOI layer is reduced to achieve the fully depleted operation of the SOI-FET.

Such a fully depleted SOI-FET having the source and drain regions in the SOI layer is constructed with an island shaped full isolation structure by performing an element isolation process, for example a local oxidation of silicon process (a LOCOS process). A region between the source and drain regions is called a body region. The body region is basically depleted when the fully depleted SOI-FET is operating.

Since a thickness of a channel depleted layer is determined in accordance with the thickness of the SOI layer, it is necessary reduce the thickness of the thinner SOI layer. When an extremely thin SOI layer (e.g. 10 nm) is formed, defects may arise due to a heat treatment process which is performed at a temperature of 900° C. or more. The heat treatment may cause a void to be opened in the SOI layer due to a thermal aggregation (also called a thermal agglomeration), and an upper surface of the insulating layer under the SOI layer might be exposed. Such a void generated by the thermal aggregation is disclosed in the magazine article of the lecture presentation of the 47thApplied Physics Association, pp. 884, 30p-YK-9, “Initial Stage of Thermal Agglomeration of an Ultrathin SOI”, published in March, 2000. If a subsequent dry etching process forming a contact hole were performed on an SOI substrate having such a void, the void might extend through the insulating layer and be formed in the conductive substrate under the insulating layer. If such a void were formed at the edge of the SOI-FET, the drive current of the SOI-FET might be reduced, since a parasitic resistance of the source and drain regions would be increased so as to increase a resistance between the source and drain regions.

Further more, if a contact plug consisting of a metal material is formed in the contact hole, and a wiring layer connecting the contact plug is formed over the SOI substrate, since the contact plug is also formed in the void, the source and drain regions and the silicon substrate might be electrically shorted.

FIGS.6(a) through6(c) and7(a) through7(c) are cross-sectional views showing a conventional method of manufacturing a semiconductor device. An SOI substrate101includes a silicon substrate101a, an embedded oxide layer101band a thin silicon layer101c(an SOI layer101c). As shown in FIG.6(a), field oxide regions102and highly doped impurity regions108aand108bare formed in the SOI layer101c, and gate electrodes105aand105band side walls107aand107bare formed over the SOI substrate101. The highly doped impurity layers108aand108bare formed by an implantation of impurity ions.

Then, a heat treatment is performed to activate the ion-implanted impurities at a high temperature. At this time, as shown in FIG.6(b), the highly doped impurity layers108aand108bgradually aggregates since the temperature of the heat treatment is equal to or more than an aggregation temperature of the SOI layer101cconsisting of silicon. As such, when the SOI layer is ultra-thin, upper surfaces R of the embedded oxide layer101bbecome partly exposed.

Next, as shown in FIG.6(c), refractory metal silicide layers109aand109bare formed by a conventional silicide process.

Next, as shown in FIG.7(a), an interlayer insulating layer110is formed over the SOI substrate101.

Next, as shown in FIG.7(b), contact holes111aand111bare formed by an anisotropic etching, for example, a dry etching such as a reactive ion etching (RIE). At this time, since the embedded oxide layer101bis partly exposed, a void113is formed extending through the embedded oxide layer101band reaching an upper surface of the silicon substrate101a. As a result, since a parasitic resistance of the highly doped impurity layers108aand108bincreases so as to increase a resistance between the highly doped impurity layers108aand108b, and the drive current of the SOI-FET is reduced.

Next, as shown in FIG.7(c), a contact plug112aconsisting of a metal material is formed in the contact holes111aand111b, and a wiring layer112bconnecting the contact plug112ais formed over the SOI substrate101. At this time, since the contact plug112ais also formed in the void113, the highly doped impurity layer108aand the silicon substrate101aare electrically shorted.

The conventional SOI-MOSFET is disclosed in an article of Proceeding 1995 IEEE International SOI Conference, Oct. 1995, pp.116-117, “Characteristics of Submicrometer LOCOS Isolation”, published on October, 1995.

SUMMARY OF THE INVENTION

In a method of manufacturing a semiconductor device according to the present invention, a substrate is provided which includes an insulating layer having an upper surface and a silicon layer extending over the upper surface of the insulating layer, a field insulating region is formed in the silicon layer, an impurity region is formed which is surrounded by the field insulating region, a gate electrode is formed over the silicon layer, and the silicon layer is heat treated at a heat treatment temperature that is less than an aggregation temperature of the silicon layer.

According to the present invention, a thermal aggregation of a silicon layer can be inhibited. Therefore, a silicon deficiency of the silicon layer caused by the thermal aggregation of the silicon layer can be inhibited.

The above and further novel features of the invention will more fully apparent from the following detailed description, appended claims and accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings. The drawings used for this description typically illustrate major characteristic parts in order that the present invention will be easily understood.

FIGS.1(a) and1(b) are cross-sectional views showing a method of manufacturing a semiconductor device according to a first preferred embodiment of the present invention. An SOI substrate101includes a silicon substrate101a, an embedded oxide layer101band a thin silicon layer101c(an SOI layer101c). As shown in FIG.1(a), a field oxide region102and a highly doped impurity region108are formed in the SOI layer101c, and a gate electrode105and a side wall107are formed over the SOI substrate101. The highly doped impurity region108is formed by an implantation of impurity ions. Then, a heat treatment is performed to activate the ion-implanted impurities. At this time, it is necessary to understand a start temperature (an aggregation temperature) of the thermal aggregation of the SOI layer108, so as to inhibit the thermal aggregation of the SOI layer108.

FIG. 2is an explanatory diagram showing an experimental result of a heat treatment according to the first preferred embodiment of the present invention. In this experiment, the heat treatment is performed for 5 minutes in a hydrogen atmosphere under 266 Pa pressure.FIG. 2shows a relationship between a temperature (° C.) of the heat treatment (in a vertical axis) and a thickness (nm) of the SOI layer108(in a horizontal axis). In particular, an evaluation was made as to whether an aggregation of the SOI layer108was generated at each of the various heat treatment temperatures and thicknesses of the SOI layer. InFIG. 2, white triangles indicate that the SOI layer108had aggregated, and white circles indicates that the SOI layer108had not aggregated.

When the aggregation temperature and the thickness of SOI layer108are T and t, respectively, the aggregation temperature T can be represented as a function of the thickness t. Specifically, the relationship between the aggregation temperature T and the thickness t of the SOI layer108can be indicated as the following equation (1).
T =(10t+530) °C.  (1)

For example, when the thickness t of the SOI layer108is 30 nm, the aggregation temperature T of the SOI layer108ais 830° C. Also, when the thickness t of the SOI layer108is 10 nm, the aggregation temperature T of the SOI layer108is 630° C.

In the first preferred embodiment, the heat treatment is performed at a temperature which is less than the aggregation temperature of the SOI layer108a. Therefore, as shown in FIG.1(b), the ion-implanted impurities into the SOI layer108are activated without the aggregation of the SOI layer108, due to the heat treatment which is performed at the temperature of less than the aggregation temperature of the SOI layer108. Specifically, an upper surface of the embedded oxide layer101bis not exposed as shown in FIG.6(b) in the prior art.

According to the first preferred embodiment of the present invention, since the heat treatment is performed at a temperature which is less than the aggregation temperature of the SOI layer108, the aggregation of the SOI layer108can be inhibited. Therefore, the method of the first preferred embodiment can inhibit a silicon deficiency of the SOI layer108.

FIGS.3(a) through3(e) and4(a) through4(c) are cross-sectional views showing the method of manufacturing a semiconductor device according to a second preferred embodiment of the present invention. In this embodiment, a method for manufacturing a fully depleted SOI-FET will be described. An SOI substrate11includes a silicon substrate11a, an embedded oxide layer11band a thin silicon layer11c(an SOI layer11c). As shown in FIG.3(a), field oxide regions12and circuit regions13aand13bare formed over the SOI substrate11using a LOCOS process. An N type impurity ion (e.g., Boron) is implanted into the circuit region13a, and a P type impurity ion (e.g., Phosphorus) is implanted into the circuit region13b. Then, a heat treatment is performed to activate the impurity ions (Boron and Phosphorus).

Next, as shown in FIG.3(b), an oxide layer14is formed over the SOI substrate11using an electric furnace, and a poly-silicon layer16is formed on the oxide layer14using a CVD apparatus.

Next, as shown in FIG.3(c), gate electrodes15aand15bare formed using a photolithography process and an anisotropic etching of the poly-silicon layer16using a dry etching process (e.g., RIE: reactive ion etching).

Next, as shown in FIG.3(d), side walls17aand17bconsisting of an insulating material (e.g., silicon oxide (SiO2) or silicon nitride (SiN4)) are formed using the CVD process and the anisotropic etching. Then, an As ion is implanted into a source-drain region of the circuit region13a, after a resist layer40is formed over the circuit region13bhaving the gate electrode15b. As a result, a highly doped impurity layer18ais obtained. Then, the resist layer40is removed.

Next, as shown in FIG.3(e), a BF2ion is implanted into a source-drain region of the circuit region13b, after a resist layer41is formed over the circuit region13bhaving the gate electrode15b. As a result, a highly doped impurity layer18bis obtained. Then, the resist layer41is removed.

As a general observation, a thin chemical oxide layer may be formed on the SOI layer when a cleaning process of the SOI substrate is performed before the heat treatment process. However, since such a thin chemical oxide layer is deoxidized at a temperature of more than 800° C. due to a silicon (Si), and then sublimes as a silicon oxide (SiO2), a clean upper surface of the SOI layer is exposed. Such a deoxidization of the thin chemical oxide layer is disclosed in the magazine article of the JAPANESE JOURNAL OF APPLIED PHYSICS, VOL. 29, NO. 6, JUNE, 1990, pp. 1004-1008, “Thermal Desorption from Si (111) Surfaces with Native Oxide Formed During Chemical Treatments”.

Therefore, in the second preferred embodiment, as shown in FIG.4(a), a protection layer30(e.g., silicon oxide (SiO2) or silicon nitride (SiN4)) is formed over the SOI substrate11. At this time, a thickness of the protection layer30is equal to or more than 1 nm. Then, a heat treatment is performed to activate the ion-implanted impurities at a temperature of 1000° C. in a nitride atmosphere using a rapid thermal anneal (RTA). At this time, since upper surfaces of the highly doped impurity layers18aand18bwhich are the SOI layer are covered and protected by the protection layer30, the highly doped impurity layers18aand18bwhich are the SOI layer do not aggregate. Therefore, an upper surface of the embedded oxide layer11blocating at the circuit regions13aand13bdoes not exposes.

Next, as shown in FIG.4(b), refractory metal silicide layers19aand19bare formed in the highly doped impurity layers18aand18b, respectively, by a silicide process after the protection layer30is removed.

Next, as shown in FIG.4(c), an interlayer insulating layer20is formed over the SOI substrate11by a CVD process. Then, contact holes21aand21bare formed in the interlayer insulating layer20, by an anisotropic etching of the interlayer insulating layer20using a dry etching process (e.g., RIE: reactive ion etching). Then, a contact plug22aconsisting of a refractory metal material (e.g., tungsten (W)) is formed in the contact holes21aand21b, and a wiring layer22bconnecting the contact plug is formed over the SOI substrate11.

According to the second preferred embodiment of the present invention, since the protection layer30is formed over upper surfaces of the highly doped impurity layers18aand18bwhich are the SOI layer, before the heat treatment which activates the ion-implanted impurities is preformed, the aggregation of the SOI layer108can be inhibited. Therefore, the method of the first preferred embodiment can inhibit a silicon deficiency of the SOI layer108. Further, since the heat treatment can be performed at a high temperature, a crystal deficiency remaining to the highly doped impurity layers18aand18bcan be effectively recovered. Therefore, the second preferred embodiment can form the SOI-FET having small parasitic leakage.

While the second preferred embodiment of the present invention presents an example in which the protection layer is formed before the heat treatment is performed, the invention is not limited to this, and may instead be formed in the early heat treatment stages before a temperature of the heat treatment reaches the aggregation temperature of the SOI layer. Further, a thermal oxide layer which has a thickness which is equal to or more than 1 nm may be formed over the upper surface of the SOI layer as a protection layer, by introducing a particle of oxide gas in the early heat treatment stage. As a result, since the protection layer is formed during the heat treatment process, a total manufacturing time can be shortened.

FIGS.5(a) through5(e) are cross-sectional views showing a method of manufacturing a semiconductor device according to a third preferred embodiment of the present invention. The third preferred embodiment will be described as an example of a method of manufacturing of a semiconductor device such that an the SOI-FET and a single-electron memory (the quantum effect device) are simultaneously formed over an SOI substrate.

An SOI substrate51includes a silicon substrate51a, an embedded oxide region51band a thin silicon layer51c(an SOI layer11c). As shown in FIG.5(a), field oxide regions52and circuit regions53aand53bare formed over the SOI substrate51using a LOCOS process. At this time, the SOI-FET is formed in the circuit region53a, and the single-electron memory is formed in the circuit region53b. Then, after a resist pattern is formed on the circuit region53b, an N type impurity ion (e.g., Boron) is implanted into the circuit region53a, or a P type impurity ion (e.g., Phosphorus) is implanted into the circuit region53a, depending on the conductive type of the SOI-FET. Then, a heat treatment is performed to activate the impurity ion (Boron or Phosphorus).

Next, as shown in FIG.5(b), similar to the second preferred embodiment, an oxide region54, a gate electrode55and a side wall57are formed in the circuit region53a. The oxide region54is formed using an electric furnace. The gate electrode55which may be a poly-silicon, for example, is formed using a CVD process and an anisotropic etching (e.g., RIE: reactive ion etching). The side wall57consisting of an insulating material (e.g., silicon oxide (SiO2) or silicon nitride (SiN4)) is formed using the CVD process and the anisotropic etching. Then, as shown in FIG.5(b), impurity ion is implanted into the source-drain region (the circuit region53a) to form a highly doped impurity layer58, using the resist layer60as a mask.

Next, an insulating layer which may be a silicon oxide (SiO2) or a silicon nitride (SiN4), for example, is formed over of the SOI substrate51which includes both circuit regions53aand53b, after the resist layer60is removed. A thickness of the insulating layer is more than 1 nm. Then, as shown in FIG.5(c), a protection layer70is formed in the circuit region53a, and a plurality of insulating patterns71are formed in the circuit region53b, due to a patterning of the insulating layer by an etching.

Next, a heat treatment is performed to activate the ion-implanted impurities at a temperature of more than 800° C. in a nitride atmosphere using a rapid thermal anneal (RTA). As a result, as shown in FIG.5(d), a plurality of quantum dots72which have a silicon island structure are formed in the circuit region53b, due to a thermal aggregation of the SOI layer51bof the circuit region53b. However, since the SOI layer51bof the circuit region53ais protected from the high temperature of the heat treatment by the protection layer70, the SOI layer51bof the circuit region53adoes not aggregate.

Next, as shown in FIG.5(e), a refractory metal silicide layer59is formed in the highly doped impurity layer58by a silicide process after the protect layer70and the plurality of insulating patterns71are removed. The subsequent processes of the manufacturing method of the third preferred embodiment are the same of the second preferred embodiment.

According to the third preferred embodiment of the present invention, since the heat treatment is performed after the circuit region53aof the semiconductor substrate51is covered by the protection layer70and the plurality of insulating patterns71are formed in the circuit region53b, the thermal aggregation of the SOI layer51cof the circuit region53acan be inhibited, and that of the circuit region53bcan be selectively aggregated. As a result, the plurality of the quantum dots72which have a silicon island structure can be formed in the circuit region53busing the thermal aggregation of the SOI layer51c. Therefore, the third preferred embodiment can integrate the SOI-FET and the single-electron memory (the quantum effect device) in the one semiconductor chip.

While the third preferred embodiment of the present invention presents an example in which the SOI-FET and the single-electron memory (the quantum effect device) are formed, simultaneously, the invention is not limited to this example, and the SOI-FET may be formed after the single-electron memory (the quantum effect device) is formed. Since an aggregation temperature of the silicon layer depends on accordance with a thickness of the silicon layer, it is necessary to control the aggregation temperature for each of various thicknesses of the silicon layer. However, in the third preferred embodiment, since the thermal aggregation of the silicon layer is used selectively, it is easy to control such a manufacturing process even where a plurality of circuit regions easy have different thicknesses. Furthermore, the third preferred embodiment can simplify a temperature setting of the manufacturing process even when plural devices require different process settings (e.g., the SOI-FET and the quantum effect device).

Further, the third preferred embodiment may be set such that a thickness of the silicon layer of the circuit region53bis thinner than that of the circuit region53a. Therefore, since the aggregation temperature of the silicon layer of the circuit region53bis the lower, a throughput of the manufacturing process can improve.

Further, a monocrystal silicon layer may be formed in the circuit region53aas a silicon layer, and an amorphous silicon layer or a poly-silicon layer may be formed in the circuit region53bas a silicon layer.

Further, while the third preferred embodiment of the present invention presents an example in which the quantum effect device which includes the quantum dots and quantum thin lines is formed in the silicon layer (the SOI layer), the present invention is not limited to this example and the quantum effect device may be formed in a semiconductor layer (e.g., an amorphous germanium layer and a polycrystalline germanium layer) or in a metal layer (e.g., an aluminum layer and a copper layer). The semiconductor layer and the metal layer are aggregated in condition at a temperature which is lower than the thermal aggregation temperature of the silicon layer (the SOI layer). Therefore, since the aggregation temperature at which the quantum effect device is formed is lower, the temperature setting of the manufacturing process step can be simplified.

Further, while the third preferred embodiment of the present invention presents an example in which the heat treatment is performed at a temperature of more than 800° C. in a nitride atmosphere, the present invention is not limited to this example and the heat treatment may be performed at a temperature of more than the thermal aggregation temperature of the silicon layer within a noble gas (e.g., an argon gas) atmosphere as a non-oxidizing atmosphere. As a result, a silicon nitride layer (a deposition layer) which is generated by reacting with the silicon layer (the SOI layer), due to such heat treatment at the high temperature within the nitride atmosphere, is not formed.

Further, the heat treatment may be performed at more than the thermal aggregation temperature of the silicon layer (the SOI layer) in a reducing gas atmosphere (e.g., a hydrogen gas) as a non-oxidizing atmosphere.

Further, the quantum thin line as one of the quantum effect devices may be formed so as to micro fabricate the silicon layer (the SOI layer) in a line pattern. Furthermore, a resonant tunneling device may be formed as one of the quantum effect devices.

Further, while the first thorough third embodiments of the present invention present an example which is used to form the fully depleted SOI-FET, the present invention is not limited to this example, and may be used to form various device structures, for example a double gate type device, and a thin film FET which is formed over an insulating substrate.

As described above, the method of manufacturing the semiconductor device according to the present invention can inhibit the thermal aggregation of the silicon layer (the SOI layer), since the heat treatment is performed at a temperature which is less than the aggregation temperature of the silicon layer (the SOI layer). Furthermore, since the upper surface of the silicon layer (the SOI layer) is covered with the protection layer when the heat treatment is preformed, the aggregation of the silicon layer (the SOI layer) can be inhibited. Therefore, the method of the present invention can inhibit the silicon deficiency of the silicon layer (the SOI layer).

The present invention has been described with reference to illustrative embodiments, however, this invention must not be considered to be confined only to the embodiments illustrated. Various modifications and changes of these illustrative embodiments and the other embodiments of the present invention will become apparent to those skilled in the art with reference to the description of the present invention. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.