Semiconductor memory device with in memory logic operations

According to one embodiment, a semiconductor memory device includes a nonvolatile memory, a read circuit array, a multiply-accumulate operator array, a first bus, an operation controller circuit, and a second bus. The read circuit array reads the data from the nonvolatile memory. The multiply-accumulate operator array receives the data read from the read circuit array. The first bus is connected between the read circuit array and the multiply-accumulate operator array and having a first bit width. The operation controller circuit is electrically connected to the multiply-accumulate operator array. The second bus is connected to the operation controller circuit and having a second bit width smaller than the first bit width.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of and priority to Japanese Patent Application No. 2017-180319, filed Sep. 20, 2017, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor memory device which includes a nonvolatile memory.

BACKGROUND

Deep learning is applied in various fields such as image processing and speech recognition, and expectations for hardware capable of performing an operation process on a large amount of data processed by the deep learning are increased. In such a device for performing the operation process on a large amount of data, data can be read from a memory cell array, and the read data can be supplied to an operation circuit to perform the operation process.

DETAILED DESCRIPTION

An exemplary embodiment provides a semiconductor memory device which is able to realize high speed and low power consumption of an operation process in an operation circuit.

In general, according to some embodiments, a semiconductor memory device includes a nonvolatile memory which stores data in a nonvolatile manner, a read circuit which reads the data from the nonvolatile memory, an operation circuit which receives the read data from the read circuit and carry out at least one operation, a first bus which is connected between the read circuit and the operation circuit and having a first bit width, a controller circuit which is electrically connected to the operation circuit, and a second bus which is connected to the controller and having a second bit width smaller than the first bit width.

Hereinafter, embodiments will be described with reference to the drawings. In the following explanation, the components having the same function and configuration are given the same reference signs. In addition, devices and methods to specify technical ideas of the present disclosure will be exemplified for the embodiments described below, and materials, shapes, structures, and arrangements of the components may be defined in various forms including the following description.

Each functional block may be realized through one or more computer hardware and/or computer software components, or a combination thereof. Each functional block is not necessary to be distinctive as the examples of the present disclosure. For example, some of functions described as being executed by an exemplary functional block may be executed by a functional block different from the exemplary functional block. Further, the exemplary functional block may be subdivided into detailed functional blocks.

A semiconductor memory device of a first embodiment will be described.

First, a configuration of a semiconductor memory device according to the first embodiment will be described.FIG. 1is a circuit diagram illustrating the configuration of the semiconductor memory device of the first embodiment.

As illustrated in the drawing, a semiconductor memory device100includes a nonvolatile memory10, a read circuit array20, a multiply-accumulate operator array30, an input buffer40, an output buffer50, an operation controller60, a parallel conversion circuit70, and a memory controller80. In some embodiments, the operation controller60and the memory controller80are connected to an external host device200(for example, various types of computers).

The nonvolatile memory10includes, for example, a NAND flash memory. The NAND flash memory stores data in a memory cell in a nonvolatile manner. In the NAND flash memory, reading and programming are performed on a page basis, which means the memory cells in a page are simultaneously programmed and read. The size of page is typically several thousands of bits. A memory cell array of the NAND flash memory will be described below in detail.

In some embodiments, the read circuit array20includes sense amplifiers which are arranged in an array shape. The sense amplifiers may read the data stored in the memory cell of the nonvolatile memory10by a page or by bits smaller in number than bits of the page. Hereinafter, the data read by the read circuit array20are denoted as read data.

In some embodiments, a bus BU1having a first bit width (for example, bits of the page) is connected between the read circuit array20and the multiply-accumulate operator array30. The multiply-accumulate operator array30includes multiply-accumulate operators which are arranged in an array shape. The multiply-accumulate operator may perform a multiply-accumulate operation between the read data read from the nonvolatile memory10by the read circuit array20and an input data supplied from the input buffer40, and output an operation result (hereinafter, referred to as operation data).

In some embodiments, the input buffer40temporarily stores the input data received from the operation controller60. Further, the output buffer50may temporarily store the operation data received from the multiply-accumulate operator array30.

In some embodiments, the operation controller60and the host device200are connected by a bus BU2which has a second bit width smaller (or narrower) than the first bit width of the bus BU1. In other words, the bus width (the second bit width) of the bus BU2may be smaller than the bus width (the first bit width) of the bus BU1. The operation controller60may receive a command supplied from the host device200, and control the multiply-accumulate operator array30according to the received command. The operation controller60may supply the input data received from the host device200to the multiply-accumulate operator array30through the input buffer40. The operation controller60may further receive the operation data output from the multiply-accumulate operator array30through the output buffer50. Then, the operation controller60may output the operation data to the host device200using the bus BU2. The operation controller60may be configured as a circuit.

In some embodiments, similar to the multiply-accumulate operator array30, the parallel conversion circuit70is connected with the read circuit array20by the bus BU1which has the first bit width. The parallel conversion circuit70and the memory controller80may be connected by a bus BU3which has a third bit width. The parallel conversion circuit70may convert the read data transmitted through the bus BU1having the first bit width from the read circuit array20into data of the third bit width (for example, 8 bits) smaller than the first bit width (for example, 16 bits, 32 bits, or 64 bits). The third bit width may be the same as or different from the second bit width. Hereinafter, the data converted by the parallel conversion circuit70are denoted by conversion data. The parallel conversion circuit70may output the conversion data to the memory controller80using the bus BU3.

In some embodiments, the memory controller80and the host device200are connected by a bus BU4which has a fourth bit width smaller (or narrower) than the first bit width of the bus BU1. In other words, the bus width (the fourth bit width) of the bus BU4may be smaller than the bus width (the first bit width) of the bus BU1. The fourth bit width may be the same as or different from the third bit width. The memory controller80may receive a command supplied from the host device200, and control the nonvolatile memory10, the read circuit array20, and the parallel conversion circuit70according to the command. The memory controller80may further include an ECC circuit. The ECC circuit may perform an error checking and correcting process (ECC) on the data. In other words, the ECC circuit may generate parity on the basis of write data when the data are programmed, generate a syndrome from the parity to detect an error and correct the error when reading the data. The memory controller80may perform the ECC process on the conversion data received from the parallel conversion circuit70, and output the corrected data to the host device200using the bus BU4. The memory controller80may be configured as a circuit.

In some embodiments, in the semiconductor memory device100, the nonvolatile memory10, the read circuit array20, the multiply-accumulate operator array30, the input buffer40, the output buffer50, the operation controller60, and the parallel conversion circuit70are disposed on the same semiconductor chip (e.g., silicon substrate) or in the same package. In some embodiments, the memory controller80is disposed on the same semiconductor chip (e.g., silicon substrate) or in the same package. Further, the circuits may be arbitrarily disposed on the same semiconductor chip or in the same package.

Next, the detailed configurations of the nonvolatile memory10, the read circuit array20, the multiply-accumulate operator array30, and the operation controller60will be described.FIG. 2is a diagram illustrating a circuit connection between the nonvolatile memory, the read circuit array, the multiply-accumulate operator array, and the operation controller illustrated inFIG. 1.

In some embodiments, in the nonvolatile memory10, weighted data (hereinafter, referred to as parameter) is stored. The parameter may be used in the operation process in the multiply-accumulate operator array30. For example, referring toFIG. 2, the nonvolatile memory10includes memory regions R1, R2, . . . , and Rn, where “n” is a natural number of 1 or more. In the memory regions R1, R2, . . . , and Rn, parameters D1, D2, . . . , and Dn may be stored respectively.

In some embodiments, in the memory cells in the memory regions R1, R2, . . . , and Rn, bit lines BL1, BL2, . . . , and BLn are connected, respectively. The bit lines BL1to BLn whose number correspond to bits of a page for example, may transmit signals of the memory regions R1to Rn in reading.

In some embodiments, the read circuit array20includes sense amplifiers S1, S2, . . . , and Sn which correspond to the bit lines BL1, BL2, . . . , and BLn, respectively. The bit lines BL1, BL2, . . . , and BLn may be connected to the sense amplifiers S1, S2, . . . , and Sn, respectively. The sense amplifiers S1to Sn may read the read data from the signals transmitted through the bit lines BL1to BLn. Further, the bit line may be configured to transmit one bit of data, or may be configured to transmit 8 bits, 16 bits, 32 bits, or 64 bits.

In some embodiments, the number of data lines DL1to DLn of the bus BU1is set to be equal to the number of bit lines BL1to BLn. In some embodiments, the configuration may also be formed in which the number (the first bit width) of data lines DL1to DLn may be set to the number smaller than that of the bit lines, and larger than the number of bits of the second bit width of the bus BU2.

In some embodiments, the multiply-accumulate operation circuit array30is connected to the input buffer40and the output buffer50. Input data DI stored in the input buffer40may be supplied to the multiply-accumulate operator array30. Operation data DO output from the multiply-accumulate operator array30may be stored in the output buffer50.

In some embodiments, the operation controller60and the host device200are connected by the bus BU2which has the second bit width. Referring toFIG. 2, the bus BU2includes external input/output lines EL1, EL2, . . . , and EL8, for example. In other words, the operation controller60may be connected to the host device200through the external input/output lines EL1, EL2, . . . , and EL8. The external input/output lines EL1to EL8may transmit input/output data between the operation controller60and the host device200. The second bit width (or bus width) of the bus BU2is, for example, 8 bits, which is smaller than the first bit width of the bus BU1.

Next, the detailed configuration of the multiply-accumulate operator Pn in the multiply-accumulate operator array30will be described.FIG. 3is a diagram illustrating a configuration of the multiply-accumulate operator Pn.

In some embodiments, the multiply-accumulate operator Pn includes registers31,32, and35, a multiplier33, and an adder34. The operation of the multiply-accumulate operator is as follows. The register31may store the parameter Dn supplied from the sense amplifier Sn in the read circuit array20. The register32may store the input data DI supplied from the input buffer40. The multiplier33may receive the parameter Dn and the input data DI, and multiply the parameter Dn and the input data DI. The adder34may add multiplied data DP and data DO fed back from the register35, and output the added data to the register35. The register35may store the added data, and output the added data as the data DO to the output buffer50.

Next, a memory cell array of the NAND flash memory will be described as an example of the nonvolatile memory10. The NAND flash memory includes a plurality of blocks BLK (seeFIG. 4) in the memory cell array.FIG. 4is a circuit diagram of the block in the memory cell array which is provided in the NAND flash memory.

In some embodiments, as illustrated inFIG. 4, the block BLK includes four string units SU0, SU1, SU2, and SU3, for example. Further, each string unit may include a plurality of NAND strings NS. Further, the number of string units SU in one block BLK and the number of NAND strings NS in one string unit SU are arbitrary. Hereinafter, “SU” denotes each of the plurality of string units SU0to SU3.

In some embodiments, each of the NAND string NS includes, for example, eight memory cell transistors MT0, MT1, . . . , and MT7and select transistors ST1and ST2. Further, a dummy transistor (not shown) may be provided between the memory cell transistor MT0and the select transistor ST2and between the memory cell transistor MT7and the select transistor ST1. Hereinafter, “MT” denotes each of the memory cell transistors MT0to MT7, and “ST” denotes each of the select transistors ST1and ST2.

In some embodiments, the memory cell transistor MT is provided with a layered gate which includes a control gate and a charge storage layer, and stores data in a nonvolatile manner. Further, the memory cell transistor MT may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type in which an insulating film is used as the charge storage layer, or may be an FG (Floating Gate) type in which a conductive film is used as the charge storage layer. Further, the number of memory cell transistors MT may be other numbers such as 16, 32, 64, or 128, in addition to “8” as shown inFIG. 4. Furthermore, the number of select transistors (e.g., ST1and ST2) is arbitrary.

In some embodiments, the sources or drains of the memory cell transistors MT0to MT7are connected in series between the select transistors ST1and ST2. As shown inFIG. 4, the drain of the memory cell transistor MT7at the one end of the series connection is connected to the source of the select transistor ST1, and the source of the memory cell transistor MT0on the other end is connected to the drain of the select transistor ST2.

In some embodiments, the gates of the select transistors ST1of the string units SU0to SU3are connected to select gate lines SGD0, SGD1, SGD2, and SGD3respectively. Hereinafter, “SGD” denotes each of the select gate lines SGD0to SGD3. The gates of the select transistors ST1in the same string unit SU may be connected to the same select gate line SGD in common. For example, the gates of the select transistors ST1in the string unit SU0are connected to the select gate line SGD0in common.

In some embodiments, the gates of the select transistors ST2of the string units SU0to SU3are connected to the select gate line SGS. The gates of the select transistors ST2in the same string unit SU may be connected to the same select gate line in common. For example, the gates of the select transistors ST2in the string unit SU0may be connected to the select gate line SGS in common.

In some embodiments, the control gates of the memory cell transistors MT0to MT7in the same block BLK are respectively connected to word lines WL0to WL7in common. In other words, while the word lines WL0to WL7are connected between the plurality of string units SU in the same block BLK in common, the select gate lines SGD and SGS are independent at every string unit SU even in the same block.

In some embodiments, in the NAND strings NS disposed in the memory cell array in a matrix configuration, the drains of the select transistors ST1of the NAND strings NS of the same row are connected to any one of the bit lines BL0, BL1, . . . , and BL (n−1) in common. Further, “n” is a natural number of 1 or more. InFIG. 4, the starting bit line is denoted as BL0. Hereinafter, in a case where the bit line BL is denoted, it means each of the bit lines BL0to BL(n−1). In other words, the bit line BL is connected to the NAND strings NS in the plurality of string units SU in common.

In some embodiments, the sources of the select transistors ST2of the NAND strings NS in the string units SU0to SU3are connected to a source line SL in common.

Reading and programming of data are collectively performed on the plurality of memory cell transistors MT commonly connected to any word line WL in any string unit SU of any block BLK. A unit of the reading and programming processing is called “page”.

In some embodiments, a data erase range may be set to other forms in addition to one block BLK. For example, the plurality of blocks may be collectively erased, or some regions in one block BLK may be collectively erased.

Next, the operation of the semiconductor memory device of the first embodiment will be described. In some embodiments, referring toFIG. 2, the nonvolatile memory10includes the memory regions R1, R2, . . . , and Rn, and weighted data (or parameters) D0to Dn is stored in the memory regions R1, R2, . . . , and Rn, respectively.

In some embodiments, the sense amplifiers S1to Sn in the read circuit array20read the parameters from the memory regions R1to Rn, respectively.

In some embodiments, the multiply-accumulate operators P1to Pn in the multiply-accumulate operator array30receive the parameters D1to Dn read by the sense amplifiers S1to Sn through the data lines DL1to DLn, respectively. In other words, the parameters D1to Dn are transmitted from the sense amplifiers S1to Sn to the multiply-accumulate operators P1to Pn using the bus BU1(the data lines DL1to DLn) having a first bit width. The first bit width may correspond to the number of bits of the page. Alternatively, the first bit width may be smaller than the page, and correspond to the number of bits larger than the second bit width of the bus BU2. In some embodiments, the multiply-accumulate operators P1to Pn each receive the input data DI from the input buffer40. The multiply-accumulate operators P1to Pn may perform a multiply-accumulate operation with the parameters D1to Dn and the input data DI, and output the operation data DO.

In this way, the multiply-accumulate operators P1to Pn can receive the parameters D1to Dn obtained by one reading operation of the read circuit array20, and can perform the multiply-accumulate operation using the parameters D1to Dn. Therefore, it is possible to improve a processing speed of the multiply-accumulate operation in the multiply-accumulate operator array30.

In some embodiments, the output buffer50stores the operation data DO output from the multiply-accumulate operator array30, and outputs the operation data DO to the operation controller60.

In some embodiments, the operation controller60outputs the received operation data DO to the host device200through the external input/output lines EL1to EL8. In other words, the operation data DO is transmitted from the operation controller60to the host device200using the bus BU2(the external input/output lines EL1to EL8) of the second bit width. The second bit width may be 8 bits, for example.

In some embodiments, the read circuit array20and the multiply-accumulate operator array30are directly connected, and the memory region Rn and the multiply-accumulate operator Pn are associated with each other. For example, a data distribution circuit is provided, and the data distribution circuit distributes the parameter Dn supplied from the sense amplifier Sn in the read circuit array20to the multiply-accumulate operator Pn corresponding to the parameter Dn. With reference toFIG. 5, this example will be described.

FIG. 5is a circuit diagram illustrating a configuration of a semiconductor memory device showing a modification of the first described embodiment. As illustrated in the drawing, a semiconductor memory device110includes a data distribution circuit90between the read circuit array20and the multiply-accumulate operator array30.

In some embodiments, the read circuit array20and the data distribution circuit90are connected by the bus BU1having a first bit width similarly to the multiply-accumulate operator array30inFIG. 1. The data distribution circuit and the multiply-accumulate operator array30may be connected by a bus BU5of the first bit width similarly. The data distribution circuit90may distribute the parameter Dn supplied from the sense amplifier Sn in the read circuit array20to the multiply-accumulate operator Pn corresponding to the parameter Dn. In some embodiments, the data distribution circuit90includes a buffer configured to temporarily store the the parameters supplied from the sense amplifiers.

In some embodiments, the parameter Dn is distributed to the multiply-accumulate operator Pn corresponding to the parameter Dn by the data distribution circuit90. Therefore, there is no need to store the parameter Dn associated to the memory region Rn in advance. The remaining configuration is similar to those of the above-described first embodiment.

Effect of First Embodiment

According to the embodiments illustrated inFIG. 1toFIG. 5(as the first embodiment), it is possible to provide the semiconductor memory device which is able to realize high speed and low power consumption in operation.

In the first embodiment, the read data read from the nonvolatile memory10by the read circuit array20is supplied to the multiply-accumulate operator array30without any change. There is no need to adjust a bit width of the read data, for example, before the read data is supplied to the multiply-accumulate operator array30. Therefore, it is possible to improve a processing speed of the multiply-accumulate operation in the multiply-accumulate operator array30, and the power consumption can be reduced.

In addition, in the embodiment illustrated inFIG. 5, the data (parameter Dn) corresponding to the multiply-accumulate operator Pn can be distributed by the data distribution circuit90, so that there is no need to store the data associated to the memory region Rn in the nonvolatile memory in advance, and the flexibility of the nonvolatile memory is improved.

With reference toFIG. 6andFIG. 7, the second embodiment will be described as to an example in which the nonvolatile memory10and the multiply-accumulate operator array30are disposed on different semiconductor chips, and are connected by a TSV (Through Silicon Via). The following description of the second embodiment highlights the differences from the first embodiment.

FIG. 6is a circuit diagram illustrating a configuration of a semiconductor memory device of the second embodiment. In some embodiments, a package300includes semiconductor chips310and320. The terminals of the semiconductor chip310and the semiconductor chip320may be connected by a TSV (Through Silicon Via)330.

In some embodiments, in the semiconductor chip310, the nonvolatile memory10and the read circuit array20are disposed. In the semiconductor chip320, the multiply-accumulate operator array30, the input buffer40, the output buffer50, and the operation controller60may be disposed. The read circuit array20in the semiconductor chip310and the multiply-accumulate operator array30in the semiconductor chip320may be electrically connected by the TSV330.

The structure of the package300will be described usingFIG. 7, which depicts a cross-sectional view of the structure of the package300. In some embodiments, the package300is made as a package by stacking the semiconductor chip320and the semiconductor chip310on a package substrate340. As a method of stacking the semiconductor chips320and310, a TSV method may be used.

In the following, the structure of the package300will be described in detail. In some embodiments, on an upper surface of the package substrate340, the semiconductor chip320is disposed, and the semiconductor chip310is further disposed on the semiconductor chip320.

In some embodiments, in the semiconductor chip320, at least one TSV321is provided from an upper surface of the semiconductor chip320to a bottom surface of the semiconductor chip320. In some embodiments, in the semiconductor chip310, at least one TSV330is provided from an upper surface of the semiconductor chip310to a bottom surface of the semiconductor chip310. The TSVs321and330may be vias which are electrically conductive from the upper surface to the bottom surface of each semiconductor chip. A bump331may be provided between the TSVs321and330. The TSVs321and330and the bump331may be electrically connected between the semiconductor chips320and310.

In some embodiments, an electrode322is provided on the bottom surface of the semiconductor chip320. A bump323may be provided between the electrode322and the package substrate340. For example, the semiconductor chip320is electrically connected to the package substrate340through the TSV321, the electrode322, and the bump323. In addition, the semiconductor chip310may be electrically connected to the package substrate340through the TSV330, the bump331, the TSV321, the electrode322, and the bump323.

In some embodiments, a bump342is provided on the bottom surface of the package substrate340. In a case where the package300is a BGA (ball grid array) package, the bump342may be a soldering ball. The package substrate340may be electrically connected to the outside (for example, the host device200) through the bump342.

In some embodiments, the package300is configured as an integrated circuit dedicated to the operation process. For example, when the parallel conversion circuit70and the memory controller80are added (seeFIG. 1), it is possible to form a general purpose nonvolatile memory.

The remaining configuration and operation of the second embodiment are similar to those of the first embodiment.

Effect of Second Embodiment

In the second embodiment, the nonvolatile memory10and the multiply-accumulate operator array30are disposed on different semiconductor chips, and connected by the TSV. With such a configuration, even in a case where the nonvolatile memory10and the multiply-accumulate operator array30are not possible to be disposed on the same semiconductor chip, the read circuit array20and the multiply-accumulate operator array30can be connected by the TSV330, so that it is possible to realize a high-speed operation process and to reduce power consumption. The other effects are similar to those of the above-described first embodiment.