FERROELECTRIC MEMORY DEVICE

A ferroelectric memory device according to an embodiment includes a substrate, an interfacial insulation layer and a ferroelectric insulation layer that are sequentially disposed on an inner wall of a trench formed in the substrate. In addition, the ferroelectric memory device includes a gate electrode layer disposed on the ferroelectric insulation layer. A portion of the ferroelectric insulation layer disposed on the interfacial insulation layer common to a bottom surface of the trench and a portion of the ferroelectric insulation layer disposed on the interfacial insulation layer common to a sidewall surface of the trench have crystal growth planes in directions perpendicular to the bottom surface and the sidewall surface of the trench, respectively.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C 119(a) to Korean Patent Application No. 10-2017-0069798, filed on Jun. 5, 2017, which is herein incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments of the present disclosure generally relate to a semiconductor device, and more particularly, relate to a ferroelectric memory device.

2. Related Art

Generally, a ferroelectric material refers to a material having spontaneous electrical polarization in a state in which no external electric field is applied. More specifically, the ferroelectric material can maintain one of two stable remanent polarization states. Such property may be utilized to store information “0” or “1” in a nonvolatile manner.

SUMMARY

There is disclosed a ferroelectric memory device according to an aspect of the present disclosure. The ferroelectric memory device includes a substrate, an interfacial insulation layer and a ferroelectric insulation layer that are sequentially disposed on an inner wall of a trench formed in the substrate. In addition, the ferroelectric memory device includes a gate electrode layer disposed on the ferroelectric insulation layer. A portion of the ferroelectric insulation layer disposed on the interfacial insulation layer common to a bottom surface of the trench and a portion of the ferroelectric insulation layer disposed on the interfacial insulation layer common to a sidewall surface of the trench have crystal growth planes in directions perpendicular to the bottom surface and the sidewall surface, respectively.

There is disclosed a ferroelectric memory device according to another aspect of the present disclosure. The ferroelectric memory device includes a substrate including a trench having a bottom surface and a sidewall surface, wherein the bottom surface and the sidewall surface of the trench have a crystal plane of the same family, a ferroelectric insulation layer having the same crystal growth plane on the bottom surface and the sidewall surface of the trench, and a gate electrode layer disposed on the ferroelectric insulation layer. A portion of the ferroelectric insulation layer disposed on the bottom surface of the trench has a remanent polarization orientation aligned in a direction perpendicular to the bottom surface of the trench and a portion of the ferroelectric insulation layer disposed on the sidewall surface of the trench has a remanent polarization orientation aligned in a direction perpendicular to the sidewall surface.

DETAILED DESCRIPTION

Various embodiments will now be described hereinafter with reference to the accompanying drawings. In the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. The drawings are described with respect to an observer's viewpoint. If an element is referred to be located on another element, it may be understood that the element is directly located on the other element, or an additional element may be interposed between the element and the other element. The same reference numerals refer to the same elements throughout the specification.

In addition, expression of a singular form of a word should be understood to include the plural forms of the word unless clearly used otherwise in the context. It will be understood that the terms “comprise” or “have” are intended to specify the presence of a feature, a number, a step, an operation, an element, a part, or combinations thereof, but not used to preclude the presence or possibility of addition one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Further, in performing a method or a manufacturing method, each process constituting the method can take place differently from the stipulated order unless a specific sequence is described explicitly in the context. In other words, each process may be performed in the same manner as stated order, may be performed substantially at the same time, or may be performed in a reverse order.

FIG. 1is a cross-sectional view schematically illustrating a ferroelectric memory device1according to an embodiment of the present disclosure.FIG. 2is an enlarged view of a portion of the ferroelectric memory device1ofFIG. 1. The ferroelectric memory device1according to this embodiment may be a transistor-type memory device having a gate structure buried in a trench.

Referring toFIGS. 1 and 2, the ferroelectric memory device1may include a substrate101, a ferroelectric insulation layer120, and a gate electrode layer130. The ferroelectric insulation layer120may be disposed along an inner wall surface of a trench10formed in the substrate101. In addition, the ferroelectric memory device1may further include an interfacial insulation layer110disposed between the inner wall surface of the trench10and the ferroelectric insulation layer120. Further, the ferroelectric memory device1may include a source region140and a drain region150disposed in the substrate101at both ends or on opposite sides of the trench10. In an embodiment, the source and drain regions140and150may be formed by injecting a dopant into the substrate101.

The substrate101may, for example, be a silicon (Si) substrate or a germanium (Ge) substrate. As another example, the substrate101may be a compound substrate such as a gallium arsenide (GaAs) substrate. The substrate101may, for example, be doped with a p-type dopant.

In an embodiment, the substrate101may be a single crystalline silicon substrate. At this time, a surface101aof the single crystalline silicon substrate may be included in the set of planes {100} in a family of planes in a cubic crystal system. As an example, the surface101sof the single crystalline silicon substrate may have a plane index of (100) of a cubic crystal system. In the present disclosure, a plane index of a crystalline structure is based on the Miller indices.

Referring toFIGS. 1 and 2, the trench10may be formed in the substrate101. The trench10may be formed to extend from the surface101sto an inner region of the substrate101. The trench10may have a bottom surface101aand sidewall surfaces101band101c(hereinafter, for convenience of explanation, collectively referred to as “both sidewall surfaces”, as shown in the drawings). The bottom surface101amay be substantially perpendicular to both sidewall surfaces101band101c. In an embodiment, when the surface101sof the substrate101has a plane index of (100) of the cubic crystal system, the bottom surface101aof the trench10may also have a plane index of (100) of the cubic crystal system, and both sidewall surfaces101band101cmay be parallel to each other and have a plane index of (010) or (001) of the cubic crystal system. Accordingly, the bottom surface101aand both sidewall surfaces101band101cof the trench10may be included in the set of planes {100} in a family of a cubic crystal system.

Referring toFIGS. 1 and 2, the interfacial insulation layer110may be disposed along the inner wall surfaces101a,101band101cof the trench10. The interfacial insulation layer110may include metal oxide. The metal oxide may, for example, have paraelectric or antiferroelectric properties. The interfacial insulation layer110may include, for example, zirconium oxide, hafnium oxide, or a combination thereof.

In an embodiment, the interfacial insulation layer110may have the same crystal system as the inner wall surfaces101a,101b, and101cof the trench10. In an embodiment, when the substrate101includes single crystalline silicon and the interfacial insulation layer110includes zirconium oxide, the interfacial insulation layer110may be a crystalline layer having a crystal structure of the cubic crystal system. When the bottom surface101aof the trench10has a plane index of (100), a portion of the interfacial insulation layer110disposed on the bottom surface101aof the trench10may have a plane index of (100). As an example, when both sidewall surfaces101band101cof the trench10have a plane index of (010), portions of the interfacial insulation layer110disposed on sidewall surfaces101band101cmay also have a plane index of (010).

As described above, the interfacial insulation layer110may have a plane index of a {100} family of a cubic crystal system on the inner wall surfaces101a,101band101cof the trench10. However, in an edge boundary region where the bottom surface101aof the trench10meets the sidewall surfaces101band101c, the interfacial insulation layer110may have various crystal planes different from the {100} family. The above-described crystalline interfacial insulation layer110may, for example, have a thickness that is equal to 1.5 nm or less, but greater than 0.

In an embodiment, the interfacial insulation layer110can function as a buffer layer between the substrate101and the ferroelectric insulation layer120. The interfacial insulation layer110can reduce any difference in lattice constants between the substrate101and the ferroelectric insulation layer120. In an embodiment, the interfacial insulation layer110may further include a dopant for changing the lattice constant thereof. As an example, when the interfacial insulation layer110includes zirconium oxide, the dopant may include scandium (Sc), yttrium (Y), lanthanum (La), gadolinium (Gd), actinium (Ac), or a combination of two or more thereof. In an embodiment, a silicon substrate having a plane index of {100} family of the cubic crystal system is used as the substrate101, and hafnium oxide having a plane index of (100) of an orthorhombic crystal system is disposed as the ferroelectric insulation layer120, then the interfacial insulation layer110may be an yttrium (Y)-doped zirconium oxide layer having a plane index of {100} family of the cubic crystal system. As an example, the yttrium (Y) may be doped to the zirconium oxide at a concentration of about nine (9) mole percent (mol %) to about twenty (20) mol %. Thus, the difference in lattice constant at the interface between the interfacial insulation layer110and the ferroelectric insulation layer120can be reduced.

In addition, the interfacial insulation layer110can function to suppress or reduce the transfer of electric charges conducted through a channel105in the substrate101from moving into the ferroelectric insulation layer120during a read operation of the ferroelectric memory device1. The interfacial insulation layer110may also function to suppress or reduce the diffusion of materials between the substrate101and the ferroelectric insulation layer120.

The ferroelectric insulation layer120may be disposed on the interfacial insulation layer110. The ferroelectric insulation layer120may include a ferroelectric material having a remanent polarization. In operations, the remanent polarization can induce electrons in the channel region105in the substrate101located under or adjacent to the ferroelectric insulation layer120. During a read operation of the ferroelectric memory device1, the electrical resistance of the channel region105may vary depending on the amount of the electrons induced by the remanent polarization of the ferroelectric insulation layer120.

The ferroelectric insulation layer120may include crystalline metal oxide. The ferroelectric insulation layer120may include, for example, hafnium oxide, zirconium oxide, or a combination thereof. In an embodiment, the ferroelectric insulation layer120may include at least one dopant. The dopant may, for example, include carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), lanthanum (La), or a combination of two or more thereof.

Meanwhile, since the interfacial insulation layer110is formed in a crystalline state on the inner wall surfaces101a,101band101cof the trench10, the ferroelectric insulation layer120may be formed in a crystalline state on the interfacial insulation layer110.

In an embodiment, the interfacial insulation layer110may be a crystalline yttrium (Y)-doped zirconium oxide layer. In the paper of “Epitaxial Y-stabilized ZrO2films on silicon: Dynamic growth process and interface structure” by S. J. Wang et al., published in Applied Physics Letters Vol. 80, 2541 (2002), a method of epitaxially forming an yttrium (Y)-doped zirconium oxide film on a (100) plane of a silicon wafer by pulsed laser deposition is disclosed. The yttrium (Y)-doped zirconium oxide layer formed in a thickness of 1.5 nm has a crystal structure of a cubic crystal system with a plane index of (100) on a (100) plane of the silicon wafer. A configuration of the yttrium (Y)-doped zirconium film disclosed in the above paper can be utilized as the interfacial insulation layer110according to an embodiment of the present disclosure. In an embodiment of the present disclosure, the yttrium (Y)-doped zirconium oxide layer may have a thickness that is equal to 1.5 nm or less, but greater than 0.

When an yttrium (Y)-doped zirconium oxide layer is implemented as the interfacial insulation layer110, a crystalline hafnium oxide layer may be used as the ferroelectric insulation layer120. In this embodiment, the crystalline hafnium oxide layer can be relatively easily formed on the crystalline yttrium (Y)-doped zirconium oxide layer through strain crystallization from the lattice mismatch between the layers.

In a comparative example, when an amorphous silicon oxide layer (SiO2) is used in the interfacial insulation layer, when a hafnium oxide layer is deposited on the silicon oxide layer in a thickness of less than four (4) nm, the hafnium oxide layer preferentially forms in an amorphous state. Therefore, in order to secure a crystalline hafnium oxide layer having the thickness of less than 4 nm, the hafnium oxide layer needs to be deposited on the silicon oxide layer in a thickness of at least four (4) nm or greater, and then the thickness of the hafnium oxide layer is reduced to the desired thickness by etching the deposited hafnium oxide layer.

In contrast, in embodiments disclosed herein, a crystalline hafnium oxide layer having a thickness of about one (1) nm to about four (4) nm can be formed merely depositing hafnium oxide on the crystalline yttrium (Y)-doped zirconium oxide layer using known methods, without the need to etch back a thicker hafnium oxide layer.

In an embodiment, a portion of the ferroelectric insulation layer120disposed on the interfacial insulation layer110common to the bottom surface101aof the trench10may have a crystal growth plane in a direction substantially perpendicular to the bottom surface101a. That is, this portion of the ferroelectric insulation layer120may have grains grown in the direction substantially perpendicular to the bottom surface101a. In addition, portions of the ferroelectric insulation layer120disposed on the interfacial insulation layer110common to the sidewall surfaces101band101cof the trench10may have a crystal growth plane in a direction substantially perpendicular to the sidewall surfaces101band101c. That is, portions of the ferroelectric insulation layer120may have grains grown in the direction substantially perpendicular to the sidewall surfaces101band101c.

In an embodiment, the portion of the ferroelectric insulation layer120disposed on the interfacial insulation layer110common to the bottom surface101aof the trench10, and portions of the ferroelectric insulation layer120disposed on the interfacial insulation layer110common to the sidewall surfaces101band101cof the trench10may have crystal growth planes included in the same plane index of a crystal system. As an example, when the bottom surface101aand the sidewall surfaces101band101cof the trench10include single crystalline silicon having a plane index of {100} family of a cubic crystal system, and the interfacial insulation layer110disposed on the bottom surface101aand the sidewall surfaces101band101cof the trench10includes zirconium oxide having a plane index of {100} family of the cubic crystal system, then the ferroelectric insulation layer120disposed on the interfacial insulation layer110may include hafnium oxide having a plane index of (100) of an orthorhombic crystal system.

Referring toFIGS. 1 and 2, the gate electrode layer130may be disposed on the ferroelectric insulation layer120. The gate electrode layer130may be formed to fill the remainder of trench10. The orientation of remanent polarization of the ferroelectric insulation layer120can thus be changed by applying a voltage to the ferroelectric insulation layer120through the gate electrode layer130.

The gate electrode layer130may include a conductive material. The gate electrode layer130may include, for example, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, alloys of any of the above, or a combination of two or more of the above. The gate electrode layer130may be composed of a single layer or a plurality of layers in the trench10.

The source region140and the drain region150may be disposed in regions of the substrate101at both ends or on opposite sides of the trench10. The source and drain regions140and150may be formed by doping the regions of the substrate101with a dopant of the opposite type to the substrate101. As an example, the source and drain regions140and150may be doped with an n-type dopant.

FIGS. 3A and 3Bare views illustrating polarization orientation of ferroelectric insulation layer120in ferroelectric memory device1according to the embodiment of the present disclosure.FIG. 3Ais a view illustrating the interfacial insulation layer110and the ferroelectric insulation layer120sequentially disposed on the bottom surface101aof the trench10of the ferroelectric memory device1described above and with reference toFIGS. 1 and 2.FIG. 3Bis a view illustrating the interfacial insulation layer110and the ferroelectric insulation layer120sequentially disposed on the sidewall surfaces101band101cof the ferroelectric memory device1.

Referring toFIG. 3A, the bottom surface101aof the trench10may correspond to the (100) plane of the cubic crystal system of the single crystalline silicon substrate101. The interfacial insulation layer110disposed on the bottom surface101amay have a plane index of (100) of the cubic crystal system. The ferroelectric insulation layer120, disposed on the interfacial insulation layer110having the plane index of (100), may have a plane index of (100) of the orthorhombic crystal system. As a result, after the write operation of the ferroelectric memory device1, the ferroelectric insulation layer120may have remanent polarizations Pup and Pdn arranged in a direction perpendicular to the surface101aof the single crystalline silicon substrate101, that is, the bottom surface101aof the trench10.

Referring toFIG. 3B, as an example, each of the sidewall surfaces101band101cof the trench10may correspond to the (010) plane of the cubic crystal system of the single crystalline silicon substrate101. The interfacial insulation layer110disposed on the sidewall surfaces101band101cmay have a plane index of (010) of the cubic crystal system. The ferroelectric insulation layer120, disposed on the interfacial insulation layer110having a plane index of (010), may have a plane index of (100) of the orthorhombic crystal system. As a result, after the write operation of the ferroelectric memory device1, the ferroelectric insulation layer120may have remanent polarizations Pup and Pdn arranged in a direction perpendicular to the surfaces101band101c—of the single crystalline silicon substrate101, that is, the sidewall surfaces101band101cof the trench10.

As described above, the ferroelectric memory device1according to an embodiment of the present disclosure may be a transistor-type memory device having a buried gate electrode130, in which the channel region105is formed along the trench10in the substrate101. At this time, the crystal growth plane of the ferroelectric insulation layer120can be controlled in a direction substantially perpendicular to the inner wall surfaces101a,101band101cof the trench10. As a result, in the write operation of the ferroelectric memory device1, the remanent polarization orientation in the ferroelectric insulation layer120can be aligned in the direction perpendicular to the inner wall surfaces101a,101band101c, respectively. As an example, a portion of the ferroelectric insulation layer120disposed on the interfacial insulation layer110common to the bottom surface101aof the trench10may have a remanent polarization orientation aligned in a vertical direction (z-direction) with respect to the bottom surface101a, and portions of the ferroelectric insulation layer120disposed on the interfacial insulation layer110common to the sidewall surfaces101band101cof the trench10may have a remanent polarization orientation aligned in a vertical direction (x direction) with respect to the sidewall surfaces101band101c. Accordingly, in the write operation of the ferroelectric memory device1in which the channel region105is formed in substrate101along the inner wall surfaces101a,101band101cof the trench10, the degree of alignment of the polarization orientation in the ferroelectric insulation layer120can be improved. The remanent polarization value of the ferroelectric insulation layer120after the write operation can be increased when the degree of alignment improves.

FIGS. 4A to 4Care views schematically illustrating a ferroelectric memory device2according to an embodiment of the present disclosure. More specifically,FIG. 4Ais a perspective view of the ferroelectric memory device2,FIG. 4Bis a cross-sectional view of the ferroelectric memory device2taken along line I-I′ ofFIG. 4A, andFIG. 4Cis a cross-sectional view of the ferroelectric memory device2taken along line II-II′ ofFIG. 4A. The ferroelectric memory device2illustrated inFIGS. 4A to 4Cmay be a three-dimensional transistor device having a saddle fin structure.

Referring toFIGS. 4A to 4C, a fin structure2010protrudes or extends upward from a substrate201in the z direction. As an example, the substrate201may have substantially the same configuration as the substrate101described above and with reference toFIG. 1. In an embodiment, the substrate201may be a doped single crystalline silicon substrate. In an embodiment, the fin structure2010may be formed of the same material as the substrate201. The fin structure2010may be arranged along an x direction.

Referring toFIGS. 4A and 4C, an insulation layer205may be disposed surrounding the fin structure2010on the substrate201. At this time, a top surface of the fin structure2010and an upper surface of the insulation layer205may be positioned on the same plane.

Referring toFIGS. 4A and 4B, an interfacial insulation layer210may be disposed along inner walls201a,201band201cof a first trench20aformed in the saddle fin structure2010. A ferroelectric gate insulation layer220may be disposed on the interfacial insulation layer210.

Referring toFIG. 4B, the inner walls201a,201band201cof the first trench20amay be composed of a bottom surface201aand sidewall surfaces201band201c. In an embodiment, the bottom surface201aof the first trench20amay have a plane index of (100) of a cubic crystal system, and the sidewall surfaces201band201cparallel to each other and have a plane index of (010) or (001). Accordingly, the bottom surface201aand sidewall surfaces201band201cof the first trench20amay each have a plane included in the set of planes {100} in a family of the cubic crystal system.

The interfacial insulation layer210may disposed along the inner walls201a,201band201cof the first trench20a. A configuration of the interfacial insulation layer210may be substantially the same as a configuration of the interfacial insulation layer110disposed along the inner walls101a,101band101cof the trench10described above and with reference toFIGS. 1 and 2. The interfacial insulation layer210may have a plane index of a {100} family of the cubic crystal system on the inner walls201a,201band201cof the first trench20a. However, in some embodiments, in an edge boundary region where the bottom surface201aof the first trench20ameets the sidewall surfaces201band201c, the interfacial insulation layer210may have various other crystal planes having different plane index from the {100} family. The above-described crystalline interfacial insulation layer210may have a thickness that is equal to 1.5 nm or less, but greater than 0, for example.

The ferroelectric gate insulation layer220may be disposed on the interfacial insulation layer210. A configuration of the ferroelectric gate insulation layer220may be substantially the same as a configuration of the ferroelectric insulation layer120disposed on the inner wall surfaces101a,101band101cof the trench10described above and with referenceFIGS. 1 and 2.

In other words, a portion of the ferroelectric gate insulation layer220disposed on the interfacial insulation layer210common to the bottom surface201aof the first trench20amay have a crystal growth plane in a direction substantially perpendicular to the bottom surface201aof the first trench20a. That is, the portion of the ferroelectric gate insulation layer220may have grains grown substantially in the z-direction. In addition, portions of the ferroelectric gate insulation layer220disposed on the interfacial insulation layer210common to the sidewall surfaces201band201cof the first trench20amay have a crystal growth plane in a direction substantially perpendicular to the sidewall surfaces201band201c. That is, the portion of the ferroelectric gate insulation layer220may have grains grown substantially in the x-direction.

In an embodiment, the portion of the ferroelectric gate insulation layer220disposed on the interfacial insulation layer210common to the bottom surface201aof the first trench20aand portions of the ferroelectric gate insulation layer220disposed on the interfacial insulation layer210common to the sidewall surfaces201band201cof the first trench20amay have crystal growth planes included in the same plane index of a crystal system.

As an example, when the bottom surface201aand the sidewall surfaces201band101cof the first trench20ainclude single crystal silicon having a plane index of {100} family of a cubic crystal system, and the interfacial insulation layer210disposed on the bottom surface201aand the sidewall surfaces201band201cincludes zirconium oxide having a plane index of {100} family of the cubic crystal system, the ferroelectric insulation layer220disposed on the interfacial insulation layer210may include a plane index of (100) of an orthorhombic crystal system. However, in some embodiments, in an edge boundary region where the bottom surface201aof the first trench20ameets the sidewall surfaces201band201c, the portion of the ferroelectric insulation layer220may have various crystal planes having plane indices different from those of the above-described (100) plane of an orthorhombic system.

Referring toFIG. 4C, the interfacial insulation layer210and the ferroelectric gate insulation layer220may be disposed on at least a portion of the top surface201dand both side surfaces201eand201fof the fin structure2010. In an embodiment, the top surface201dmay have a plane index of (100) of a cubic crystal system. The side surfaces201eand201fmay have a plane index of (010) or (001) of a cubic crystal system. The interfacial insulation layer210may have a plane index of {100} family of a cubic crystal system on the top surface201dand both side surfaces201eand201f. However, in some embodiments, a portion of the interfacial insulation layer210in the edge boundary regions where the top surface201dmeets the side surfaces201eand201fmay have various crystal planes having plane indices different from those of the above-described plane (100) of a cubic crystal system.

In an embodiment, the ferroelectric gate insulation layer220may have a plane index of (100) of an orthorhombic crystal system on the interfacial insulation layer210. At this time, a portion of the ferroelectric gate insulation layer220disposed on the interfacial insulation layer210common to the top surface201dof the fin structure2010may have a crystal growth plane in a direction substantially perpendicular to the top surface201d. Portions of the ferroelectric insulation layer220disposed on the interfacial insulation layer210common to the side surfaces201eand201fof the fin structure2010may have a crystal growth plane in a direction substantially perpendicular to the side surfaces201eand201f. However, in some embodiments, in edge boundary regions where the top surface201dmeets the side surfaces201eand201f, the portion of the ferroelectric insulation layer220may have various crystal planes having plane indices different from those of the above-described (100) plane of an orthorhombic crystal system.

Referring toFIGS. 4A to 4C, a gate electrode layer235and an upper conductive layer245may be sequentially disposed on the ferroelectric gate insulation layer220. The gate electrode layer235and the upper conductive layer245may be arranged along a y-direction. The gate electrode layer235and the upper conductive layer245may constitute a word line.

A configuration of the gate electrode layer235may be substantially the same as a configuration of the gate electrode layer130of the embodiment described above and with reference toFIGS. 1 and 2. The upper conductive layer245may, for example, be formed of a metal material. The upper conductive layer245may have a lower electrical resistance than the gate electrode layer235. The upper conductive layer245may include, for example, copper (Cu), aluminum (Al), tungsten (W) or the like.

A source region250and a drain region260may be disposed in regions of the substrate201at both ends or on opposite sides of the gate electrode layer235. The source and drain regions250and260may be formed by doping the regions of the substrate201with a doping type opposite to a doping type of the substrate201. As an example, the source and drain regions250and260may be doped with an n-type dopant.

As described above, the ferroelectric memory device2of this embodiment may have the interfacial insulation layer210and the ferroelectric gate insulation layer220disposed on the inner wall surfaces201a,201band201cof the first trench20aand on the wall surfaces201d,201eand201fof a transistor having a saddle fin structure.

At this time, by controlling the crystal growth plane of the ferroelectric gate insulation layer220in the substantially vertical direction with respect to the inner wall surfaces201a(z direction),201band201c(x direction) of the first trench20aand the wall surfaces201d(z direction),201eand201f(y direction) of the fin structure2010, the remanent polarization orientation in the ferroelectric gate insulation layer220can be aligned perpendicular with respect to the inner wall surfaces201a,201band201cand wall surfaces201d,201eand201fin the write operation of the ferroelectric memory device2. As a result, in the write operation of the ferroelectric memory device2, the degree of alignment of the polarization orientation in the ferroelectric gate insulation layer220can be improved. When the degree of alignment of the polarization orientation is improved, the remanent polarization value of the ferroelectric gate insulation layer220can be increased after the write operation.

FIGS. 5 to 9are views schematically illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present disclosure.

Referring toFIG. 5, a substrate101may be prepared. As an example, the substrate101may include a semiconductor material. In an embodiment, the substrate101may be a p-type doped silicon substrate. A surface101sof the substrate101may have a plane index of (100) of a cubic crystal system.

A trench10may be formed in the substrate101. The trench10may be formed from the surface101sof the substrate101to an inner region. In an embodiment, the trench10may be formed by selectively patterning the substrate101using an anisotropic etching method. The trench10may have a bottom surface101aand sidewall surfaces101band101c. The bottom surface101aand the sidewall surfaces101band101cmay be substantially perpendicular to each other. In an embodiment, the patterning may proceed so that the bottom surface101aof the trench10may have a plane index of (100) of a cubic crystal system, and the sidewall surfaces101band101cparallel to each other may have a plane index of (010) or (001) of a cubic crystal system.

Referring toFIG. 6, an interfacial insulation layer110may be formed along the inner wall surfaces101a,101band101cof the trench10and the surface101sof the substrate101. The interfacial insulation layer110may include crystalline metal oxide. As an example, the interfacial insulation layer110may include zirconium oxide, hafnium oxide, or a combination thereof. The interfacial insulation layer110may function as a buffer layer between the inner wall surfaces101a,101band101cand a ferroelectric insulation layer120to be formed later.

In an embodiment, the interfacial insulation layer110may include a dopant to adjust a lattice constant of the interfacial insulation layer110. The dopant may include, for example, scandium (Sc), yttrium (Y), lanthanum (La), gadolinium (Gd), actinium (Ac) or a combination of two or more thereof.

The interfacial insulation layer110may, for example, be formed by applying a chemical vapor deposition method, an atomic layer deposition method or the like. The dopant may be injected as a source gas during the deposition of the interfacial insulation layer110, or may be injected by ion implantation or the like after deposition of the interfacial insulation layer110.

The interfacial insulation layer110may be formed in a crystalline state. The interfacial insulation layer110may have, for example, a thickness that is equal to 1.5 nm or less, but greater than 0. In an embodiment, when a silicon substrate having a plane index of {100} family of a cubic crystal system is used as the substrate101and a hafnium oxide layer having a plane index of (100) of an orthorhombic crystal system is utilized as the ferroelectric insulation layer120, the interfacial insulation layer110may be formed with an yttrium (Y)-doped zirconium oxide layer having a plane index of {100} family of a cubic crystal system. As an example, the yttrium (Y) may be doped to the zirconium oxide layer at a concentration of nine (9) mol % to twenty (20) mol %. In an embodiment, the yttrium (Y)-doped zirconium oxide layer having the plane index of {100} family may be obtained by a sufficiently low deposition rate when the interfacial insulation layer110is formed on the silicon substrate using the chemical vapor deposition method or the atomic layer deposition.

In an embodiment, when the bottom surface101aof the trench10has a plane index of (100), a portion of the interfacial insulation layer110disposed on the bottom surface101amay have a plane index of (100). In addition, when the sidewall surfaces101band101cof the trench10have a plane index of (010), portions of the interfacial insulation layer110disposed on the sidewall surfaces101band101cmay have a plane index of (010).

Referring toFIG. 7, the ferroelectric insulation layer120may be formed on the interfacial insulation layer110. The ferroelectric insulation layer120may include a ferroelectric material having a remanent polarization. The ferroelectric insulation layer120may include, for example, hafnium oxide, zirconium oxide, or a combination thereof. In an embodiment, the ferroelectric insulation layer120may include at least one dopant. The dopant may include, for example, carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), lanthanum (La) or a combination of two or more thereof.

In an embodiment, the ferroelectric insulation layer120may, for example, be formed by applying a chemical vapor deposition method, an atomic layer deposition method or the like. The ferroelectric insulation layer120may, for example, be formed in a thickness of about one (1) nm to about four (4) nm.

In an embodiment, a portion of the ferroelectric insulation layer120disposed on the interfacial insulation layer110common to, the bottom surface101aof the trench10may be formed to have a crystal growth plane in a direction substantially perpendicular to the bottom surface101a. Portions of the ferroelectric insulation layer120disposed on the interfacial insulation layer110common to the sidewall surfaces101band101cof the trench10may be formed to have a crystal growth plane in a direction substantially perpendicular to the sidewall surfaces101band101c.

In an embodiment, when a silicon (Si) substrate having a plane index of {100} family of a cubic crystal system is used as the substrate101and an yttrium (Y)-doped zirconium oxide layer having a plane index of {100} family of a cubic crystal system is utilized as the interfacial insulation layer110, the ferroelectric insulation layer120may be formed with a hafnium oxide layer having a plane index of (100) of an orthorhombic crystal system. In an embodiment, the hafnium oxide layer having a plane index of (100) of an orthorhombic crystal system may be obtained by a sufficiently low deposition rate when the ferroelectric insulation layer120is formed on the interfacial insulation layer110using the chemical vapor deposition method or the atomic layer deposition.

Referring toFIG. 8, a gate electrode layer130may be formed on the ferroelectric insulation layer120in the trench10. At this time, the gate electrode layer130may be formed to fill the remainder of the trench10. The gate electrode layer130may be deposited on the ferroelectric insulation layer120outside the trench10.

The gate electrode layer130may include, for example, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, or a combination of two or more thereof. The gate electrode layer130may, for example, be formed using a chemical vapor deposition method, an atomic layer deposition method, or a sputtering method.

Referring toFIG. 9, the gate electrode layer130, the ferroelectric insulation layer120, the interfacial insulation layer110disposed outside the trench10may be removed by performing a planarization process or a selective etching process. The removal process may be performed until the surface of the substrate101outside the trench10is exposed.

Next, a source region140and a drain region150may be formed in substrate101regions at both ends or on opposite sides of the trench10. The source and drain regions140and150may be formed by selectively injecting an n-type dopant into the substrate101. The dopant may be injected, for example, using an ion implantation method.

By progressing through the above-described processes, a ferroelectric memory device according to an embodiment of the present disclosure can be manufactured. The ferroelectric memory device to be manufactured may be substantially the same as the ferroelectric memory device1described above and with reference toFIGS. 1 and 2.

FIGS. 10 to 14are cross-sectional views schematically illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present disclosure.FIGS. 13B and 13Care cross-sectional views taken along line A-A′ and line B-B′, respectively, of the perspective view ofFIG. 13A.

Referring toFIG. 10, a substrate201may be prepared. As an example, the substrate201may include a semiconductor material. In an embodiment, the substrate201may be a p-type doped silicon substrate.

Next, the substrate201may be selectively etched by an anisotropic etching to form a fin structure2010that protrudes or extends from an upper portion of the substrate201. After anisotropic etching, the substrate201may have a first surface201s1and a second surface201s2. The fin structure2010may have a top surface201tand both side surfaces201uand201v. In an embodiment, the first and second surfaces201s1and201s2and the top surface201tmay have a plane index of (100) of a cubic crystal system and the side surfaces201uand201v, which are parallel to each other, may have a plane index of (001) of the cubic crystal system.

Referring toFIG. 11, an insulation layer205surrounding the fin structure2010on the substrate201may be formed. At this time, the insulation layer205may be planarized such that the upper surface of the fin structure2010and the upper surface of the insulation layer205are positioned on the same plane. The insulation layer205may be formed by applying a chemical vapor deposition method, a coating method or the like. The insulation layer205may be planarized, for example, by applying a chemical mechanical polishing process or an etch-back process.

Referring toFIG. 12, the fin structure2010and the insulation layer205may be etched to form a trench20. In a specific embodiment, the fin structure2010may be selectively etched to form a first trench20a. Also, the insulation layer205may be selectively etched to form second trenches20b. At this time, the etching depth for the insulation layer205may be greater than the etching depth of the fin structure2010. As a result, a fin recess region2010a, which is a region protruding upward from the substrate201in the trench20, may be formed.

In the recess region2010a, the fin structure2010may have a bottom surface201aand both sidewall surfaces201band201c. In addition, the fin structure2010may have an upper surface201dand both sidewall surfaces201eand201fformed by the second trenches20b. As illustrated, the bottom surface201aof the first trench20aand the upper surface201dof the fin structure2010are the same plane.

In an embodiment, the bottom surface201aof the first trench20aand the upper surface201dof the fin structure2010may have a plane index of (100) of a cubic crystal system. The sidewall surfaces201band201cof the first trench20amay have a plane index of (010) of the cubic crystal system. The side surfaces201eand201fof the fin structure2010may have a plane index of (001) of the cubic crystal system.

Referring toFIGS. 13A and 13B, an interfacial insulation layer210may be formed on the fin recess region2010aalong the inner wall surfaces201a,201band201cof the first trench20a. As illustrated inFIGS. 13A and 13C, the interfacial insulation layer210may be formed on the upper surface201dand side surfaces201eand201fnear the fin recess region2010a. In an embodiment, the interfacial insulation layer210may be formed in a crystalline state using a chemical vapor deposition method or an atomic layer deposition method, for example. The interfacial insulation layer210may be formed in a sufficiently low deposition rate to obtain a crystal structure. The interfacial insulation layer210may be formed to have a thickness that is equal to 1.5 nm or less, but greater than 0, for example. As an example, the interfacial insulation layer210may include zirconium oxide, hafnium oxide, or a combination thereof. The interfacial insulation layer210may include a dopant to adjust a lattice constant of the interfacial insulation layer210. The dopant may include, for example, scandium (Sc), yttrium (Y), lanthanum (La), gadolinium (Gd), actinium (Ac) or a combination of two or more thereof.

The interfacial insulation layer210may have substantially the same plane index as the inner wall surfaces201a,201band201cof the first trench20a, and the upper surface201dand side surfaces201eand201fof the fin recess region2010a. In an embodiment, the interfacial insulation layer210may have a plane index of {100} family of a cubic crystal system.

Referring toFIGS. 13A and 13C, a ferroelectric insulation layer220may be formed on the interfacial insulation layer210. The ferroelectric insulation layer220may be formed in a crystalline state using a chemical vapor deposition method or an atomic layer deposition method, for example. In an embodiment, ferroelectric insulation layer220may be formed in a sufficiently low deposition rate to obtain a crystal structure. The ferroelectric insulation layer220may be formed to have a thickness about one (1) nm to about four (4) nm, for example.

The ferroelectric insulation layer220may be formed to have a crystal growth plane in a direction perpendicular to the inner wall surfaces201a,201band201cof the first trench20aunder the ferroelectric insulation layer220and to the upper surface201dand side surfaces201eand201fof the fin recess region2010a. In an embodiment, the ferroelectric insulation layer220may have a plane index of (100) of an orthorhombic system.

The ferroelectric insulation layer220may include, for example, hafnium oxide, zirconium oxide, or a combination thereof. In an embodiment, the ferroelectric insulation layer220may include at least one dopant. The dopant may include, for example, carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), lanthanum (La) or a combination of two or more thereof.

Referring toFIG. 14, a gate electrode layer230and an upper conductive layer240may be sequentially formed on the ferroelectric insulation layer220. The gate electrode layer230may include, for example, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, alloys of any of the above, or a combination of two or more of the above. The gate electrode layer230may be formed using a chemical vapor deposition method, an atomic layer deposition method or a sputtering method, for example. The upper conductive layer240may be formed of a metal material, for example. In an embodiment, the upper conductive layer240may have a lower electrical resistance than the gate electrode layer230. The upper conductive layer240may include, for example, copper (Cu), aluminum (Al), tungsten (W) or the like. The upper conductive layer240may, for example, be formed using a chemical vapor deposition method, an atomic layer deposition method or a sputtering method.

Referring toFIG. 15, the gate electrode layer230and the upper conductive layer240may be selectively etched to form a gate electrode layer235and an upper conductive layer245. Next, the fin structure2010positioned at both ends or opposite sides of the gate electrode layer235may be doped to form a source region250and a drain region260. The source and drain regions250and260may be formed by selectively injecting an n-type dopant into the fin structure2010. The dopant injecting may be performed using an ion implantation method, for example.

By proceeding through the above-described processes, a ferroelectric memory device according to an embodiment of the present disclosure can be manufactured. The ferroelectric memory device to be manufactured may be substantially the same as the ferroelectric memory device2described above and with reference toFIGS. 4A to 4C.

The embodiments of the inventive concept have been disclosed above for illustrative purposes. Those of ordinary skill in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concept as disclosed in the accompanying claims.