Display apparatus, display system and method of driving apparatus

A display apparatus, comprising: signal lines and scanning lines arranged vertically and horizontally; a plurality of display pixel parts connected to the signal lines and scanning lines; and a display control part which applies image data to the plurality of display pixel parts, wherein the display pixel part includes: a plurality of sub-display pixels which performs display in accordance with analog pixel data or digital pixel data applied to the corresponding signal line; and a plurality of one bit memories which store the digital pixel data applied to the corresponding signal line, wherein the display control part changes the order of the analog pixel data applied to the signal lines and the order of the digital pixel data applied to the signal lines to each other.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-362175 filed on Nov. 28, 2001 and No. 2002-57701 filed on Mar. 4, 2002, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display on which a drive circuit and a pixel part are integrally formed on a common insulating substrate. Especially, the present invention relates to the liquid crystal display in which a plurality of one bit memories are provided to store image data for each pixel.

2. Related Background Art

A display apparatus in which a memory is provided for each pixel to store image data has been proposed. For example, a display apparatus for holding the pixel voltage by a capacitor in the memory has been disclosed in Japanese Laid Open H9-258168. A display apparatus which holds data (voltage) for designating whether or not to turn on the pixel to the capacitor in the pixel, thereby continuing still image without driving the signal lines for a prescribed period is disclosed in Japanese Laid Open 2001-306038.

If the pixel data is stored in the memory, when the screen is not rewritten, it is possible to perform display by reading out data stored in the memory. Because of this, it is unnecessary to operate a latch circuit, a D/A converter, an analog buffer and so on in the signal drive circuit, thereby reducing power consumption.

However, if the memory is provided for each pixel, when moving image is displayed, contents of the memory has to be often updated, thereby increasing power consumption. Because the memory is formed below an opposite electrode and a pixel electrode, the capacitor in the memory causes a capacitance coupling between the opposite electrode and the pixel electrode. Therefore, a voltage at both ends of the capacitor is subjected to the influence of voltage fluctuation of the opposite electrode and the pixel electrode.

FIG. 28is a diagram schematically showing positioning relationships between the opposite electrode COM and the pixel electrode Pix, and between the electrodes at both ends of the capacitor C composing of the memory. As shown inFIG. 28, when the potential of the opposite electrode fluctuates, the potential of the pixel electrode also fluctuates by the influence, and accordingly, the potential at the upper side electrode of the capacitor composing the memory also fluctuates.

When the potential at the upper electrode of the capacitor fluctuates, the logic held to the capacitor changes, thereby causing the change of color. That is, undesired problem such as irregular color may occur.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a display apparatus capable of reducing power consumption.

In order to achieve the foregoing object, a display apparatus, comprising:

signal lines and scanning lines arranged vertically and horizontally;

a plurality of display pixel parts connected to said signal lines and scanning lines; and

a display control part which applies image data to said plurality of display pixel parts,

wherein said display pixel part includes:

a plurality of sub-display pixels which performs display in accordance with analog pixel data or digital pixel data applied to the corresponding signal line; and

a plurality of one bit memories which store the digital pixel data applied to the corresponding signal line,

wherein said display control part changes the order of the analog pixel data applied to the signal lines and the order of the digital pixel data applied to the signal lines to each other.

Further, a display apparatus according to the resent invention which comprises an array substrate having signal lines and scanning lines arranged vertically and horizontally, and a plurality of display pixel parts connected to the signal lines and scanning lines,

wherein said display pixel part includes:

a plurality of sub-display pixels which perform display based on analog pixel data or digital pixel data applied to the corresponding signal line; and

a one bit memory which stores the digital pixel data applied to the corresponding signal line,

wherein said one bit memory includes:

a capacitor which charges electric charge in accordance with the digital pixel data; and

a control transistor which switches whether or not to charge the electric charge to said capacitor,

wherein said capacitor includes:

a first electrode connected to said control transistor; and

a second electrode arranged opposite to said first electrode and connected to a ground line or a power supply line, said second electrode being formed above said first electrode and below pixel electrodes of said plurality of display pixel parts.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a display apparatus according to the present invention will be more specifically described with reference to drawings.

FIG. 1is a block diagram showing schematic configuration of a liquid crystal display according to a first embodiment of a display apparatus of the present invention. The liquid crystal display ofFIG. 1has a pixel array part1on which signal lines and scanning lines are arranged vertically and horizontally and a plurality of pixels are formed, a signal line drive circuit2for driving signal lines, a scanning drive circuit3for driving scanning lines, a display controller IC4, a power supply IC5, and so on. The liquid crystal display ofFIG. 1displays pixel data applied from a host computer6.

A liquid crystal display part7consisted of the pixel array part1, the signal line drive circuit2and the scanning line drive circuit3is formed of, for example, poly-silicon TFTs formed on an insulating substrate. The display controller IC4and the power supply IC5are implemented on a common insulating substrate by COG (Chip On Glass). The circuits embedded in the display controller IC4may be formed of the poly-silicon TFT on the insulating substrate.

The signal line drive circuit2has a data sampling circuit11for sampling the pixel data applied from the display controller IC4via a video bus L1, a latch circuit12for latching data sampled by the data sampling circuit11, a D/A converter (D/A)13for converting the latched data into an analog voltage, an amplifier14for amplifying the output of the D/A13, a selector15for distributing the output of the amplifier14to the signal lines, a timing control circuit16for controlling timing of each part in the signal line drive circuit2, and a memory controller17for controlling data writing for the pixel array part1.

The scanning line driving circuit3has a Y-decoder21and four gate drivers22. In the pixel array part1, for example, the number of total pixels is 320(×3)×480, the display area is divided into four above and below, and each block has 320(×3)×120 pixels. The scanning lines of each block are driven by the corresponding gate driver22.

The display controller IC4has an input part31, a lookup table (LUT)32, a memory control part33, a timing generator34, an address generator35, a frame memory36, a buffer37, a data output part38and a control signal output part39.

The power supply IC5embeds a DC/DC converter, an opposite electrode drive circuit and so on. The power supply IC5is supplied with the driving voltage VDD of 3V and the ground voltage VSS from an external power supply not shown.

FIG. 2is a circuit diagram showing schematic configuration of one display pixel in the pixel array part1. As shown inFIG. 2, one display pixel includes a pixel TFT41connected to the signal line, six sub-display pixel parts42, six one-bit memories (DRAM)43, a refresh circuit44for refreshing these DRAMs43, and a polarity inversion circuit45connected between the sub-display pixel parts42and the refresh circuit44.

Area ratio of the respective sub-display pixel parts42is 32:16:8:4:2:1. Thus, the gradation display of 26=64 is realized by providing six sub-display pixel parts42each having the different area.

A liquid crystal layer is sealed between the sub-display pixel part42and the opposite electrode to form a liquid crystal capacitor C1. Because the liquid crystal as material of the liquid crystal layer requires no high-speed response, a normal TN liquid crystal may be used as the material. Each of the sub-display pixel parts42has an auxiliary capacitor C2and a transferring TFT46.

Each of the DRAMs43has a read/write control transistor47and a capacitor C3. The refresh circuit44has two inverters IV1connected in series, and a feedback TFT48connected between an input terminal of an inverter IV1at initial stage and an output terminal of an inverter IV2at subsequent stage. The output terminal of the inverter IV1at initial stage and the input terminal of the inverter IV2at subsequent stage are connected to a polarity inversion circuit45. The refresh circuit44refreshes data stored in the DRAM43by using the power supply voltage Vdd (5V) and the ground voltage Vss (0V).

The polarity inversion circuit45has selecting transistors49and50for selecting either of the outputs of the inverters IV1and IV2in the refresh circuit44. These selecting transistors49and50are controlled to ON/OFF based on the polarity control signals SPOLA and SPOLB from the memory controller17of FIG.1.

The liquid crystal display of the present embodiment can realize display of 26=64 gradations by area gradation method. It is possible to switch the display based on analog pixel data and the display based on digital pixel data. More specifically, the liquid crystal display of the present embodiment performs display based on the analog pixel data during moving image display period, and performs display based on digital pixel data during still image display period.

Hereinafter, the writing based on the analog pixel data is called analog writing, and the writing based on the digital pixel data is called digital writing.

The display controller IC4determines whether to perform the analog writing or the digital writing. The digital controller IC4monitors the writing from a host computer6to the frame memory36. If the contents of the frame memory36do not change for a prescribed period, it is determined to be the still image display, and the digital writing is performed for the next one frame. After then, data output from the display controller IC4is stopped. When the contents of the frame memory36changes, data output from the display controller IC4is again begun from subsequent frame to perform the analog writing.

When the still image is displayed, the display is updated based on data stored in the DRAM43of each pixel. Because of this, it is unnecessary to drive a peripheral circuit such as the signal line drive circuit2and so on, thereby reducing power consumption.

In the conventional liquid crystal display, even if the image data D/A13is not inputted to the display controller IC4, the display controller IC4has always outputted the pixel data for one frame. On the other hand, according to the present embodiment, because each pixel embeds the memory, the output of all the image data from the display controller IC4is stopped, and even if the operation of the signal line drive circuit2is stopped, it is possible to continue the display.

The liquid crystal display according to the present embodiment can perform the analog writing with regard to only a portion of the display screen, and can perform the digital writing with regard to the other area. Alternatively, it is possible to continue the display by only the polarity inversion operation of the pixel electrode based on data stored in the DRAM43in each pixel. Accordingly, it is possible to partially rewrite the display screen. Therefore, it is unnecessary to drive the signal line drive circuit and so on in vain, thereby further reducing power consumption.

In the present embodiment, the operation of the signal line drive circuit2is different from the analog writing and the digital writing.FIG. 3is a diagram showing a detailed connection relationship of the latch circuit12and the D/A (DAC)13. The circuit ofFIG. 3is practically provided 160 pieces.

During the analog writing period, the digital pixel data of 6 bits applied to one signal line is latched by six latch circuits12, respectively. The D/A13converts 6 bits the data latched by the six latch circuits12into the analog pixel voltages. The multiplexer51arranged at subsequent stage of the D/A13supplies the analog pixel voltage outputted from the D/A13to the amplifier14. The amplifier14performs current amplification of the analog pixel voltage from the D/A13, and supplies the analog pixel voltage to the corresponding signal line. The selector is realized by known analog switches.

On the other hand, during the digital writing period, certain bits among six types of the digital pixel data supplied to six signal lines, for example, initially most significant bit, are latched by six latch circuits12, respectively. The multiplexer51supplies six types of data latched by six latch circuits12to the amplifier14by selecting for every one type. The selector15supplies the output of the amplifier14to the corresponding signal line. This operation is repeated in order. By performing such an operation, it is unnecessary to provide the additional latch circuit.

Next, the operation of the liquid crystal display ofFIG. 1will be described hereinafter.FIGS. 4A and 4Bare timing chart during the analog writing, andFIG. 5is a diagram explaining the operation of the liquid crystal display during the analog writing display period.

FIG. 4Ashows the operational timing of ¼frame period expressed by a hatched line of FIG.5. As shown inFIG. 4A, the writing is performed in order by each horizontal line.FIG. 4Bshows detailed writing timing of the second horizontal line (2H).

During the analog writing period, as shown inFIG. 4B, the writing is performed in order of (1) odd pixel data for one horizontal line of red color (time T1-T2), (2) odd pixel data for one horizontal line of blue color (time T3-T4), (3) even pixel data for one horizontal line of green color (time T5-T6), (4) odd pixel data for one horizontal line of green color (time T7-T8), (5) even pixel data for one horizontal line of red color (time T9-T10), and (6) even pixel data for one horizontal line of blue color (time T11-T12).

When the writing of (1)-(6) is finished, the same processings are repeated with regard to the next horizontal line.

When the analog writing is performed, two selecting transistors49and50in the polarity inversion circuit45ofFIG. 2are set to be OFF. Accordingly, data is not written to the DRAM43. When the analog writing is performed, the signals S0-S5ofFIG. 2are always set to be high level, and all the transferring TFTs46are set to be ON. At this state, when the analog pixel data of (1)-(6) are applied in order, the electric charge in accordance with the analog pixel voltage is charged to all the liquid crystal capacitor C1and the auxiliary capacitor C2, thereby realizing 64 gradations for each color.

As shown inFIG. 3, the liquid crystal display of the present embodiment has the D/A13and the amplifier14for every six signal lines. Accordingly, during the analog writing period, the selector15at subsequent stage of the amplifier14switches the selection in order of (1)-(6) of FIG.6. The timing of the signals XSW1-XSW6for switching the selection of the selector15is shown in FIG.4B.

Thus, by providing the selector15to subsequent stage of the amplifier14, it is possible to share the amplifier14and the D/A13by a plurality of signal lines, thereby reducing the circuit volume and power consumption. Although the example in which the signal lines driven at the same time are divided into six groups by the colors of RGB and even/odd has been described, the present invention is not been limited to the above-mentioned example. The signal lines may be divided into twelve groups of 12×N+1, 12×N+2, . . . , 12×N+12 (N=0, 1, . . . ). That is, various modifications are possible.

Next, the digital writing will be described.FIGS. 7A and 7Bare timing charts during the digital writing period, andFIG. 8is a diagram explaining the liquid crystal display during the digital writing period.

FIG. 7Ashows the timing of ¼frame period, and the writing timing of one horizontal line is shown in FIG.7B.

During the digital writing period, as shown inFIG. 7B, the writing is performed in order of (1) the most significant bit D5of all the pixel data for one horizontal line (time T1-T2), (2) a bit D4of all the pixel data for one horizontal line (time T3-T4), (3) bit D3of all the pixel data for one horizontal line (time T5-T6), (4) bit D2of all the pixel data for one horizontal line (time T7-T8), (5) bit D1of all the pixel data for one horizontal line (time T9-T10), and (6) bit D0of all the pixel data for one horizontal line (time T11-T12).

In the above-mentioned (1)-(6), as shown inFIG. 9, the writing is performed in order of the odd pixels of red color, the odd pixels of green color, the odd pixels of blue color, the even pixels of red color, the even pixels of green color and the even pixels of blue color.

During the digital writing period, as shown inFIG. 7B, because the signal S0is always set to be high level, the transferring TFT46is always set to be ON state. At this state, the signals S5-S1are set to be ON in order.

First, the signal S5is set to be ON. Therefore, the transferring TFT46to which the signals S0and S5are inputted and the read/write control transistor47in the DRAM43to which the signals S0and S5are inputted turns on. At this time, the most significant bit data D5of the red odd pixel data is applied to the signal lines, the data is stored into the corresponding DRAM43, and the corresponding electric charge is stored into the liquid crystal capacitor C1of the corresponding sub-display pixel.

Subsequently, the signal S5is maintained to be ON, and the most significant bit data D5of the green color odd pixel data is applied to the adjacent signal line. Therefore, the data is stored into the DRAM43corresponding to the signal line, and the corresponding electric charge is charged to the liquid crystal capacitor C1of the corresponding sub-display pixel.

Similarly, at the state that the signal S5is maintained to be ON, the most significant bit data D5of each data of blue color odd pixels, red color even pixels, green color even pixels and blue odd pixels are applied to the corresponding signal line in order.

Next, instead of the signal S5, the signal S4is set to be ON. Therefore, the transferring TFT46to which the signals S0and S4are inputted, and the read/write control transistor47in the DRAM43to which the signals S0and S4are inputted, turn on. At this time, the bit data D4of the red color odd pixel data is applied to the signal line. The data is stored into the corresponding DRAM43, and the corresponding electric charge is charged to the corresponding liquid crystal capacitor C1.

Subsequently, the signal S4is maintained to be ON, and the bit data D4of each data of green color odd pixels, blue color odd pixels, red color even pixels, green color even pixels and blue color even pixels is applied to the corresponding signal line in order.

Next, similarly, the signals S3-S1are set to be ON in order, and the bit data D3-D1of the pixel data is written in order.

Next, only the signal S0is set to be ON, and the least significant bit data D0is written to the DRAM43to which the signal S0is inputted, and the corresponding electric charge is charged to the liquid crystal capacitor C1.

As described above, the present embodiment changes the writing order of the pixel data in the cases of the analog writing and the digital writing. The reason is why if the digital writing is performed at the same writing sequence as that of the analog writing, the transferring TFT has to be often turned on/off, thereby increasing power consumption. On the other hand, if the digital writing is performed by the above-mentioned method, all colors are written in sequence with regard to a certain bit of the digital pixel data, and during writing the certain bit, it is unnecessary to allow the transferring TFT to turn ON or OFF. Because of this, it is possible to decrease the number of times that the transferring TFT is turned on/off, thereby reducing power consumption.

FIG. 10is a diagram summarizing the data writing order at the analog writing and the digital writing. InFIG. 10, data written at the same timing is shown in horizontal direction, and data written at the different timing is shown in vertical direction. For example, R1, 5 expresses fifth bit of the first signal line of red color.

Next, the holding display of data stored in the DRAM43, that is, the still image display will be described hereinafter.FIG. 11is a timing chart during the still image display period, andFIG. 12is a diagram explaining operation of the liquid crystal display during the still image display period.

During the still image display period, as shown inFIG. 12, a portion of the signal line drive circuit2, more specifically, the data sampling circuit11, the latch circuit12, the D/A13, the amplifier14and the selector15do not operate. During the still image display period, as shown inFIG. 11, the signals S5-S0becomes high for each constant period in order, respectively. When the signals S5-S0are high level, the refresh circuit44operates to perform refresh operation.

The operation of the liquid crystal display during the still image display period will be more specifically described with reference to FIG.2. At the state in which the signal S5is set to be high level, data of the DRAM43corresponding to the signal line is led to the refresh circuit44. When the signal Gr becomes high, two inverters IV1and IV2are connected on loop shape to refresh the DRAM43. Either of two transistors49and50composing the polarity inversion circuit45turns on, and the electric charge in accordance with data stored in the DRAM43or the inversion data is charged to the liquid crystal capacitor C1corresponding to the signal S5.

Next, at state that the signal S4is set to high level, data of the DRAM43is led to the refresh circuit44. When the signal Gr becomes high level, the inverters IV1and IV2are connected on the loop to refresh the DRAM43. Either of two transistors composing the polarity inversion circuit45turns on, and the electric charge in accordance with data stored in the DRAM or the inversion data is charged to the liquid crystal capacitor C1corresponding to the signal S4.

By repeating the same operation with regard to the signals S3, S2, S1and S0in order, the polarity inversion of all the liquid crystal capacitors is finished.

The still image display is performed for each pixel block obtained by dividing the display screen into four backwards and forwards. More specifically, as shown inFIG. 11, the still image display of 1-120 lines is performed at time T1-T2, the still image display of 121-240 lines is performed at time T3-T4, the still image display of 241-360 lines is performed at time T5-T6, and the still image display of 361-480 lines is performed at time T7-T8in order.

After then, at next frame, the common voltage is inverted, and then the same processings are performed.

Thus, during the still image display period, because data stored in the DRAM43is read out to perform display processings. It is unnecessary to operate the data sampling circuit11, the latch circuit12, the D/A13, the amplifier14and the selector15in vain, thereby reducing power consumption.

Next, an example of performing the analog writing with regard to only a partial area of the display screen will be described.FIG. 13is a timing chart in this case, andFIG. 14is a diagram explaining operation of the liquid crystal display in the case of performing the analog writing with regard to only the partial area.FIG. 13shows an example of performing the analog writing with regard to only the 241-320 lines as shown in a hatched part of FIG.14and performing the polarity inversion operation by reading out the contents of the DRAM43with regard to the other area.

In this case, the analog writing is performed in sync with the timing that the scanning line drive circuit3drives the gates of the pixel TFTs41of 241-320 lines at time T1-T2of FIG.13. In the other period, similarly to the still image display, data stored in the DRAM43is read out in units of 120 lines in order to rewrite the data read out by the DRAM43to the liquid crystal capacitor C1.

Thus, according to the present embodiment, it is possible to alternatively perform the analog writing and the digital writing, to perform the analog writing with regard to only a portion of the display screen and to perform the digital writing with regard to the other area of the display screen. Because of this, it is unnecessary to operate the D/A13and so no in the signal line drive circuit2in vain, thereby reducing power consumption.

The present embodiment performs a so-called common inversion drive. When DC voltage continues to be applied to liquid material, particles (molecules) gradually breakdown. As a result, it is known to cause display defect such as contrast irregularity or image sticking. As this countermeasure, it is necessary to invert polarity of a voltage applied to the liquid crystal layer at a prescribed cycle, and V line inversion drive and common inversion drive are well used.

The V line inversion drive fixes the common electrode to 5V, and alternatively applies to the signal lines the positive polarity voltage of 5.5-9.5V and the negative polarity voltage of 4.5-0.5V. The V line inversion drive is a drive method of alternatively changing the positive polarity and the negative polarity for each signal line.

The common inverting drive drives the common electrode to 0V or 5V at a prescribed cycle, and a voltage applied to the signal line is set to be 0.5-4.5V. In the liquid crystal display for portable telephones and the display for portable information terminals such as a PDA, common inverting driving is favorable because required voltage range for signal line is smaller. The common inversion drive is an example, if the voltage range applied to the signal lines is small, the other drive method may be adopted. The reason is why the reduction of power consumption of the signal line drive circuit is effective in order to extend charging cycle of the battery.

A second embodiment has a feature in which the voltage at both ends of the capacitor composing the DRAM43is not affected on fluctuation of the voltage of the pixel electrode and the common voltage.

FIG. 15is a block diagram showing schematic configuration of a display apparatus according to the present invention. InFIG. 15, the same reference numbers are attached to configurations common to those of FIG.1. Hereinafter, different points will be mainly described.

The liquid crystal display ofFIG. 15has a common voltage output circuit61for performing waveform shaping of the common voltage in addition to configuration of FIG.1. The common voltage output circuit61is embedded in an IC separate from the liquid crystal part6and the display controller IC4.

FIG. 16is a circuit diagram showing a detailed configuration of the common voltage output circuit61. As shown inFIG. 16, the common voltage output circuit61has an operational amplifier62which outputs a signal designating common potential supplied from the display controller IC4and common electrode driving waveform in accordance with a reference voltage Ref for adjusting a rising speed of a common electrode drive waveform applied to the common electrode and an output circuit63. The operational amplifier62has a transistor pair64, a current mirror circuit65and a constant current circuit66.

The constant current circuit66variably adjusts the current based on the bias signal applied from the display controller IC4. More specifically, in the case of performing the analog writing of the entire screen, the current flowing through the constant current circuit66is increased. Therefore, the common voltage waveform becomes sharp. In the case of performing holding display based on the contents of the DRAM43, the current flowing through the constant current circuit66is decreased. Therefore, the common voltage waveform is rounded.

As the other method for rounding the common voltage waveform, without using the operational amplifier62, as shown inFIG. 30, it is possible to insert a resistor at subsequent stage of the output circuit63. In the case of small type liquid crystal display for the portable telephone having about 2 inch of diagonal length, if the frame frequency, which is a cycle for performing data writing for one frame, is 60 Hz, it is desirable to set a product between the resistor and the common capacitor of the liquid crystal cell to be some msec.

FIG. 17is a diagram showing cross section structure of the liquid crystal display according to a second embodiment. The waveforms described to right side ofFIG. 17illustratively show a potential of the common electrode on the opposite substrate, a potential of the pixel electrode on the array substrate, upper electrode of the DRAM on the array substrate and the potential waveform of the lower electrode of the DRAM, in order from upper side, respectively. The potential of the common electrode alternatively becomes 0V or 5V at a prescribed cycle. The potential of the pixel electrode fluctuates at the same amplitude as that of the common electrode in accordance with the potential fluctuation of the common electrode, because the pixel electrode causes capacitance coupling with the common electrode. There is no likelihood in which the upper electrode of the DRAM fluctuates at the same amplitude as the potential of the pixel electrode in accordance the potential fluctuation of the pixel electrode, because the upper electrode of the DRAM is the power supply line or the ground line for supplying the power supply to the circuit in the pixel. In a moment in which the potential of the pixel electrode fluctuates, the potential of the upper electrode changes a little bit, and then soon returns to the original potential, because the electric charge is resupplied from the external power supply to the upper electrode. The lower electrode of the DRAM becomes high level or low level in accordance with the stored data. Although the voltage of the lower electrode fluctuates in accordance with that of the upper electrode, when the upper electrode returns to a prescribed potential, the potential of the lower electrode returns to a prescribed logic level. The liquid crystal display ofFIG. 17has a plurality of sub-display pixel electrodes each having different area ratio for each pixel and the DRAMs43, and performs area gradation display.

The DRAM43is composed of the read/write control transistor47and the capacitor C3, similarly to FIG.2. One electrode71composing the DRAM43is formed of the same material as poly-silicon being the material of the active layer of the read/write control transistor47. On the upper face of the electrode71, the other electrode73is formed via the insulation layer72made of oxide silicon. The other electrode73is set to ground level.

Thus, the reason why the other electrode73set to the ground level is arranged to near side of the opposite electrode74and the pixel electrode75is because the electrode set to be ground level is not affected on the potential fluctuation of the opposite electrode74and the pixel electrode75.

The read/write control transistor47is formed on the insulation substrate by using the active layer71made of poly-silicon. The gate insulating film72made of oxide silicon is formed on the upper face of the active layer71, and the gate electrode74made of MoW alloyed metal is formed on the gate insulating film72. Source and drain electrodes70and76are formed back and forth of the gate electrode74via an interlayer insulation film made of oxide silicon. An interlayer insulation film77made of acrylic resin and so on is formed on the source and drain electrodes70and76, and the pixel electrode75made of Al is formed on the interlayer insulation film77.

The opposite substrate79arranged opposite to the array substrate78with such a structure has a color filter81of red, blue and green formed on the grass substrate80and an opposite electrode82which is made of a transparent electrode such as ITO and formed on the color filter81.

The common voltage applied to the opposite electrode82periodically becomes 0V or 5V in order to perform polarity inversion drive. When the common voltage drastically changes from 0V to 5V, or from 5V to 0V, due to the change of voltage, there is a likelihood in which the voltage of the upper electrode (ground electrode) of the capacitor of the DRAM43fluctuates. The reason is why when the voltage fluctuation is too much large, the analog switch83of the DRAM43causes leak.

Because of this, in the present embodiment, the common voltage output circuit61ofFIG. 15rounds the voltage waveform of the common voltage as shown in FIG.18. Therefore, the voltage fluctuation of the upper electrode of the capacitor is restrained, and the voltage fluctuation at both ends of the capacitor is restrained. The round amount of the waveform depends on screen size of the display apparatus, the number of pixels, liquid crystal material, the electric charge supplying ability of the power supply supplying the voltage to the upper electrode and so on. Roughly, the peak value of the potential fluctuation of the upper electrode during common inversion period should be roughly designed to be equal to or less than noise margin of the inverter IV1and IV2of the refresh circuit44. Under the condition, even if the voltage at both ends of the capacitor fluctuates, the refresh circuit44can refresh the voltage stored in the DRAM43without misunderstanding the logic level.

Thus, in the second embodiment, because the ground electrode of the capacitor of the DRAM43is arranged to near side of the opposite electrode74, and the voltage waveform of the common voltage supplied to the opposite electrode74is rounded, the voltage at both ends of the capacitor is not affected on the voltage fluctuation of the opposite electrode74and the pixel electrode, thereby improving the display quality.

A third embodiment shares one sub-pixel by a plurality of bits of digital pixel data.

FIG. 19is a circuit diagram showing circuit configuration of one pixel in the signal line drive circuit according to a third embodiment of a display apparatus of the present invention.FIG. 19shows that the number of bits of the digital pixel data is six and each pixel has three sub-display pixels of area ratio 16:4:1. Practically, the circuit ofFIG. 19is provided one by one for each color of RGB, and one pixel is composed of these three circuits. InFIG. 19, an uncharacteristic portion of the signal line drive circuit is omitted.

The liquid crystal display apparatus ofFIG. 19has the DRAM43having six capacitors Cd0, Cd1, Cd2, Cd3, Cd4and Cd5provided in accordance with each bit of the digital pixel data, a refresh circuit44for holding the digital pixel data stored in the DRAM43in order for every one bit, an accumulating capacitor82consisted of three capacitors provided in accordance with each of three sub-display pixels for storing data held by the refresh circuit44, a first switching part83for switching whether or not to transmit the digital pixel data stored in the DRAM43to the refresh circuit44, a second switching part84for switching whether or not to transmit data held by the refresh circuit44to the accumulating capacitor82, a polarity switching circuit85, and a data import control circuit86for controlling whether or not to take in data on the signal line S.

The accumulating capacitor82stores the digital pixel data of 6 bits stored in the DRAM43in twice at each different timing for each different period, and three sub-display pixels perform display in accordance with data stored in the corresponding accumulating capacitor82.

The refresh circuit44has two inverters IV1and IV2connected in series, and a transistor switch48connected between the output terminal of the inverter IV2at subsequent stage and the input terminal of the inverter IV1at forward stage.

FIG. 20is a layout diagram for one bit according the third embodiment of the display apparatus of the present invention. InFIG. 20, the pixel electrodes G1, G2and G3are displayed with heavy-line frame. As shown inFIG. 20, the pixel electrodes G1, G2and G3with area ratio of 16:4:1 are provided for each color of RGB. Each of the pixel electrodes G1, G2and G3is connected to the accumulating capacitor82.

FIG. 21is a display timing chart according to the third embodiment of the display apparatus of the present invention. As shown inFIG. 21, at time t0-t1, the digital pixel data for one frame is stored in the DRAM43.

After then, at time t1-t5, the positive polarity data based on the digital pixel data stored in the DRAM43is divided into odd bits and even bits and is stored in the accumulating capacitor82in order. After then, at time t5-t9, the negative polarity data based on data stored in the DRAM43is divided into the odd bits and the even bits and stored in the accumulating capacitor82.

Subsequently, as long as data displayed to the screen is not changed, the processings at time t1-t9are repeated.

Hereinafter, the processings of time t1-t9will be described in detail. First, at time t1-t2, among the digital pixel data for one frame stored in the DRAM43, the positive polarity data corresponding to data of odd bits D5, D3and D1is stored in the accumulating capacitor82.

Subsequently, at time t2-t3, data stored in the accumulating capacitor82is held. The display in accordance with odd bits D5, D3and D1is performed during this period. The period of time t2-t3is, for example, 8 msec.

Subsequently, at time t3-t4, among the digital pixel data for one frame stored in the DRAM43, the positive polarity data corresponding to data of the even bits D4, D2and D0is stored in the accumulating capacitor82. After then, at time t4-t5, data stored in the accumulating capacitor82is held. The display in accordance with the even bits D4, D2and D0is performed during this period. The period of time t3-t4is, for example, 4 msec.

Subsequently, at time t5-t7, the negative polarity data corresponding to the odd bits D5, D3and D1of the digital pixel data is stored in the accumulating capacitor82to display it. At time t7-t9, the negative polarity data corresponding to the even data D4, D2and D0of the digital pixel data is stored in the accumulating capacitor82to display it.

Thus, according to the present embodiment, the digital pixel data of 6 bits for one frame is separated into the odd bits and the even bits. The display is performed for 8 msec based on the values of the odd bits in the first half. The display is performed for 4 msec based on the value of the even bits in the second half. Because the area ratio of three pixel electrodes in one pixel is 16:4:1, (area×time) in the first half are 16×8, 4×8 and 1×8, respectively, and (area×time) in the second half are 16×4, 4×4 and 1×4, respectively. The ratio of these total six sets is 32:8:2:16:4:1. Therefore, 26=64 gradation display is realized.

FIG. 22is a detailed timing chart showing the writing processing of the digital pixel data to the DRAM43, which is performed at time t0-t1of FIG.21. At time t11-t24ofFIG. 22, the digital pixel data for one horizontal line is written into the DRAM43, and at time t25-t38, the digital pixel data for next one horizontal line is written into the DRAM43.

Hereinafter, the processings at time t11-t24are more specifically described. At time t12-t17, the control signal SEL1becomes high level, and the odd bits D1, D3and D5of the digital pixel data are stored in the capacitors Cd1, Cd3, Cd5, respectively. More specifically, at time t12-t13, the transistors Q6and Q7in the first switching part83turn on, and the digital pixel data of fifth bit applied to the signal line is written into the capacitor Cd5. After then, at time t14-t15, the transistors Q8and Q9in the first switching part83turn on, and the digital pixel data of third bit applied to the signal line is written to the capacitor Cd3. After then, at time t16-t17, the transistors Q10and Q11in the first switching part83turn on, and the digital pixel data of first bit applied to the signal line is written into the capacitor Cd1.

After then, at time t18-t23, the control signal SEL2becomes high, and the digital pixel data D0, D2and D4of the odd bits are stored in the capacitors Cd0, Cd2and Cd4, respectively. More specifically, at time t18-t19, the transistors Q6and Q7in the first switching part83turn on, and the digital pixel data of fourth bit applied to the signal line is written into the capacitor Cd4. After then, at time t20-t21, the transistors Q8and Q9in the first switching part83turn on, and the digital pixel data of second bit applied to the signal line is written into the capacitor Cd2. After then, at time t22-t23, the transistors Q10and Q11in the first switching part83turn on, and the digital pixel data of 0th bit applied to the signal line is written into the capacitor Cd0.

At time t25-t38, the same processings are performed with regard to the next horizontal line.

FIG. 23is a timing chart showing detailed writing operation to the accumulating capacitor82, and shows an example in which the odd bits D5, D3and D1of the digital pixel data are written into the accumulating capacitor82. In time t41ofFIG. 23, when the signal SEL1is high level, and the signals LOAD1and LOAD2become high level, data stored in the capacitor Cd5is transmitted to the refresh circuit44.

Subsequently, at time t42, the signal REF becomes high, two inverters IV1and IV2in the refresh circuit44are connected in ring shape, and the refresh circuit44performs holding operation.

Subsequently, at time t43, the signal POLA becomes high, and the output of the inverter IV2in the refresh circuit44is written to the capacitor Cs3in the accumulating capacitor82at time t43-t44.

After then, at time t46, the signal LOAD1becomes high level and the signal LOAD2becomes low level. The data stored in the capacitor Cd3in the DRAM43is stored in the capacitor Cs2in the accumulating capacitor82at time t48-t49.

After then, at time t51, the signal LOAD1becomes low level, and the signal LOAD2becomes high level. Data stored in the capacitor Cd1in the DRAM43is stored in the capacitor Cs1in the accumulating capacitor82at time t53-t54.

After the above-mentioned operation is finished, and the prescribed period, for example, 8 msec lapses, data corresponding to the even bits D4, D2and D0of the digital pixel data is written into the accumulating capacitor82.

FIG. 24is a timing chart showing a detailed writing processings to the accumulating capacitor82for one frame. As shown inFIG. 24, the same processings as those ofFIG. 23are performed for every prescribed period (8 msec or 4 msec) in four times. More specifically, the positive polarity data corresponding to the odd bits D5, D3and D1of the digital pixel data is stored in the accumulating capacitor82at time t61-t62, and after 8 msec, the positive polarity data corresponding to the even bits D4, D2and D0of the digital pixel data is stored in the accumulating capacitor82at time t63-t64. After 4 msec, the negative polarity data corresponding to the odd bits D5, D3and D1of the digital pixel data is stored in the accumulating capacitor82at time t65-t66. After 8 msec, the negative polarity data corresponding to the even bits D4, D2and D0of the digital pixel data is stored in the accumulating capacitor82at time t67-t68.

Thus, according to the third embodiment, the digital pixel data is divided into odd bits and even bits, and is stored in the common accumulating capacitor82by staggering timing. Because of this, it is possible to decrease the number of the capacitors in the accumulating capacitor82in half of the number of the capacitors in the DRAM43. Accordingly, it is possible to reduce the number of the capacitors and the number of the analog switches in the second switching part84.

Furthermore, the first switching part83for switching data transmission from the DRAM43to the refresh circuit44and the second switching part84for switching data transmission from the refresh circuit44to the accumulating capacitor82are switched by common control signals LOAD1and LOAD2, thereby reducing the number of wirings. By such an advantageous effect, according to the present embodiment, it is possible to increase the number of bits of area gradation per one pixel without increasing the area so much, and to realize high gradation display.

In the above-mentioned third embodiment, an example of performing the display based on the digital pixel data has been described. However, by using the circuit ofFIG. 19, it is possible to perform display based on the analog gradation voltage. The timing chart at this case is shown in FIG.25.

In the case ofFIG. 25, the analog gradation voltage applied to the signal line is directly written into the accumulating capacitor82. That is, the DRAM43and the first switching part83are not used.

The display for one horizontal line is performed during time t71-t78of FIG.25. The display for the next horizontal line is performed during time t79-t80.

Hereinafter, the display operation of time t71-t78will be more specifically described. First, at time t72-t73, the signals LOAD1and LOAD2become high level, and data in accordance with the analog gradation voltage applied from the signal line is charged to the capacitor Cs3in the accumulating capacitor82.

Next, at time t74-t75, the signal LOAD1becomes high level, and the signal LOAD2becomes low level. Data in accordance with the analog gradation voltage supplied from the signal line is charged to the capacitor Cs2in the accumulating capacitor82.

Next, at time t76-t77, the signal LOAD1becomes low level, and the signal LOAD2becomes high level. Data in accordance with the analog gradation voltage supplied from the signal line is charged to the capacitor Cs1in the accumulating capacitor82.

Thus, when performing the analog writing, the writing to three capacitors Cs1, Cs2and Cs3is performed based on the same analog gradation voltage. Because the analog writing does use neither the DRAM43nor the first switching part83, the operation is simpler than that of the above-mentioned digital writing. Accordingly, the analog writing is suitable to the case in which it is necessary to switch the screen at high speed such as moving image display.

In the present embodiment, the example in which the number of time division is two, the number of division of the pixel portion is three, and by this combination, the gradation display of 6 bits is performed, has been described. The number of time division and the number of division of the pixel portion are not limited to the above-mentioned one. For example, the other example in which the number of time division is three, and the number of division of the pixel portion is two, is also possible. In this case, the ratio of time division is set to be 16:4:1, and the ratio of the division of the pixel portion is set to be 2:1. Summarily, if the product of (area×time) becomes 2n (n=0, 1, . . . 5), the same gradation display is possible.

In the present embodiment, although the period of two time division has been set to be 8 msec and 4 msec, the time length is not limited to 8 msec and 4 msec. For example, the time length may be 6 msec and 3 msec. Although it is effective to set the time as long as possible in order to reduce power consumption, the effective voltage to the liquid crystal may become lower, thereby occurring flicker and deteriorating visibility. Accordingly, it is desirable to set time as long as possible at range in which the flicker does not occur.

In the present embodiment, when the potential of the common electrode is inverted at a prescribed cycle, the potential of the pixel electrode fluctuates due to coupling, and whether or not the logic level of the DRAM provided below the pixel electrode can be held normally has been described in detail. Even in the driving method of holding the potential of the common electrode to a constant potential, it is effective to normally hold the logic level of the DRAM when the pixel potential fluctuates by the potential inversion and so on during the period in which the DRAM is in high impedance state (state in which the electric charge is not supplied).

In the above-mentioned embodiment, an example in which the present invention is applicable to the liquid crystal display has been described. However, the present invention is also applicable to an EL (electro luminescence) display apparatus.

FIG. 26is a circuit diagram showing circuit configuration for one pixel in the signal line drive circuit according to a four embodiment of a display apparatus of the present invention. The display apparatus ofFIG. 26is an EL display apparatus, and shows an example in which three sub-display EL light-emitting parts with area ratio 16:4:1 are provided for each color of RGB.

The EL display apparatus ofFIG. 26has a the DRAM43having the same configuration as that ofFIG. 19, the refresh circuit44, the accumulating capacitor82, a first switching part83, a second switching part84and a data import control circuit86.

In the EL display apparatus, because it is unnecessary to perform the polarity inverting drive, the polarity inversion circuit is omitted.

A gate terminal of a light control TFT87is connected to each of the accumulating capacitor82, an EL display element88is connected to the drain terminal of the TFT87, and a power supply line DVDD is connected to the source terminal.

When the light control TFT87is in ON, if the power supply line DVDD becomes a high level voltage, the EL display element88turns on a light. Even if the power supply line DVDD is in high level voltage, when the light control TFT87is in off state, the EL display element88does not turn on a light.

FIG. 27is a diagram showing drive timing of the EL display apparatus of FIG.26. As evidenced by comparingFIG. 27withFIG. 21, because the present embodiment does not perform the polarity inverting drive, the timing control ofFIG. 27is easier than that of FIG.21.

First, at time t0-t1, the digital pixel data for one frame is stored in the DRAM43. After then, at time t1-t5, the digital pixel data stored in the DRAM43is divided into odd bits and even bits, and is stored in the accumulating capacitor82in order. After then, the processings of time t1-t5are repeated.

The period (time t2-t3=8 msec) for driving the EL display element88based on the odd bits of the digital pixel data is twofold of the period (time t4-t5=4 msec) for driving the EL display element88based on the even bits. Because of this, the values of (area×time) of time t2-t3become 16×8, 4×8 and 1×8, respectively, and the values of (area×time) of time t4-t5become 16×4, 4×4 and 1×4, respectively. The ratio of these six sets becomes 32:8:2:16:4:1. Therefore, 26=64 gradation display is realized.

Thus, even when the present invention is applied to the EL display apparatus, 2ngradation display is realized by the accumulating capacitors82and the EL display elements88having the half of the number n of bits of the digital pixel data, thereby simplifying the configuration of the pixels.

In the present embodiment, although the period in which the power supply line DVDD is in H level has been set to be 8 msec and 4 msec, the time length is not limited to 8 msec and 4 msec. In the sight of the refresh of the DRAM, it is assumed to become low power consumption as the time length is long.

On the other hand, from the viewpoint of the DRAM refresh, when time is too much long, the time interval at which one DRAM is refreshed becomes too much long, the voltage level of the DRAM deteriorates too much until the level which is not adjusted by the refresh circuit. Therefore, there is a likelihood in which correct light control becomes impossible. The deterioration of the voltage level of the DRAM becomes lower as the leak current of the switch is small. The length of the lighting period should be optimized from these viewpoints.

In the present embodiment, although the refresh circuit composed of two inverters connected in loop shape has been used, the configuration of the refresh circuit is not limited to the above-mentioned one. The refresh circuit should able to adjust the logic level of the DRAM43, and supply the sufficient on/off voltage to the light control TFT87. For example, the adjustment of the logic level of the DRAM43may be performed by 0 or 5 volt, and the supply of the light control voltage to the accumulating capacitor may be performed by −2 volt or 8 volt. In this configuration, the level shifter of arbitrary configuration may be inserted between the refresh circuit44of FIG.26and the switching circuit84.

Even in the present embodiment, the number of time division and the number of the division of the lighting part are not limited.

In the present embodiment, although it is assumed that the product of (area×time) becomes 2n(n=0, 1, . . . 5), according to the characteristics of the actual EL element, the adjustment to be a little bit of different value from 2nis also effective. The area, the time and the DVDD voltage level may be adjusted in accordance with colors by degrees.

The above-mentioned display apparatus according to the first to fourth embodiments can stop the signal line drive circuit after writing data for one screen into the memory of each pixel in order to display the still image, thereby saving power consumption to a large degree. The reason is why the display control operation in the pixel is sufficiently small, as compared with the operation of the signal line drive circuit.