Innovative Structure for the Register Group

A processing circuit comprises a plurality of modules connected in series to form a module pipeline. Each module comprises one or more registers having corresponding addresses within an address range for the module. A register request, including a target register address, is passed from one module to succeeding modules down the module pipeline until the register request is received at the module containing the targeted register. Data is written into or read out from the targeted register.

DETAILED DESCRIPTION

FIG. 1shows a processing circuit5according to one exemplary embodiment. The processing circuit5may comprise, for example, an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA). Processing circuit5includes a bus converter10and a plurality of modules20A-G. As will be described in more detail below, each module20includes one or more registers24(FIG. 2) for storing configuration data, status information, or other data used by the module20. The bus converter10and modules20are connected in series by segments32of an internal register bus30. Each segment of the internal register bus30connects one module20to a preceding module20, a succeeding module20, and/or the bus converter10to form a module pipeline. Each module20also connects to a data bus40to receive data to be processed and to output processed data. Two data buses40are shown in the exemplary embodiment. Those skilled in the art will appreciate, however, that the number of data buses is not material to the invention.

Bus converter10provides an external interface to the internal register bus30to enable external applications to access the registers within the modules20. The bus converter10receives register requests from external applications over an interface bus (not shown) and converts register requests from an external interface protocol used on the interface bus to an internal register bus protocol used on the internal register bus30. The bus converter10forwards the converted register request to the first module20A in the module pipeline. As will be described in greater detail below, the register request is sequentially passed from one module20to the succeeding module20until it arrives at the module20containing the targeted register. Upon receiving the register request, the receiving module20decodes the target register address and compares the decoded address to its assigned register address range to determine whether the target register belongs to the receiving module20. If the target register address falls within the register address range of the receiving module20, the module20latches the register data into or reads the register data from the matching register, i.e., the register having a register address matching the target register address. If the target register address falls outside the register address range of the receiving module20, the receiving module20passes the register request to the succeeding module20.

FIG. 2illustrates the main functional components of an exemplary module20. Module20comprises a register group22, a controller26, and a data processing unit28. Register group22comprises a decoder23and one or more registers24. Registers24store configuration information, status information, or other information used by the module20. The decoder23decodes the target register addresses associated with register requests received by the module20as hereinafter described. The controller26controls the operation of the module20and provides the data processing unit28access to the registers24in the register group22. The data processing unit28performs the processing functions assigned to the module20. Data processing unit28may perform different functions or operate in different modes depending on the configuration data stored in the registers24. That is, by writing configuration data into the registers24, the function or mode of the data processing unit28can be controlled.

Each register24within the register group22has a corresponding register address within a predetermined register address range for the host module20. It will be appreciated that the register address range of a module20comprises one or more addresses assigned to the registers24within the module20, and that the register address range may be contiguous or discontiguous. The register group22has a first interface21A connected by one internal bus segment32to a preceding module20or bus converter10, and second interface21B connected by another internal bus segment32to a succeeding module20. The second interface21B is not used by the last module20in the module pipeline, e.g., module20G. The first and second interfaces are shown inFIG. 4and described in more detail below.

To access a register24, an external application sends a register request to the bus converter10. The bus converter10converts the register request into the internal register bus protocol and forwards the converted register request to the first module20A. The register request includes a target register address that specifies a targeted register. The register request may comprise a write request or a read request. When a register request is received by a module20over the first interface21A, the decoder23decodes the target register address associated with the register request and compares the target register address with the address range and/or the individual addresses of its registers24to determine whether the targeted register belongs to the module20. If the targeted register does not belong to the module21decoder23outputs the register request over the second interface to the succeeding module20in the pipeline. If the targeted register belongs to the module20, decoder23either latches the write data into the targeted register (write request), or reads the register data from the targeted register (read request).

FIG. 3shows an exemplary process100implemented by a processing module20. Processing module20receives a register request including a target register address on a first interface (block110) connected to a preceding module20or the bus converter10by a first segment of an internal register bus, and compares the target register address to a register address range for the receiving module20(block120). If the target register address falls within the register address range of the processing module20, the decoder23accesses the matching register24to write data into or read data from the matching register (block130). If the target register address falls outside the register address range, the decoder23outputs the register request to the succeeding module20connected to the processing module20over the second interface (block140).

FIG. 4illustrates exemplary interfaces contained in the internal bus segments connecting Module K to a preceding module, Module K−1, and a succeeding module, Module K+1. Table 1 identifies the various lines of the internal register bus segments32, where the symbol “?” represents either “i” or “o”, and where “i” indicates an input signal for module K and “o” indicates an output signal for module K.

TABLE 1Internal Register Bus InterfaceLabelDefinitionReg_req_?Register requestReg_wt1_rd0_?Write or read flagReg_address_?[*]Request address bus indicating the target registeraddressReg_wdata_?[*]Write data line carrying write data when theReg_wt1_rd0_? indicates a write flagReg_rd_rdy_?Read out data from the target register whenReg_wt1_rd0_? indicates a read flagReg_rdata_?[*}Valid flag of read-out data from the target registerwhen Reg_wt1_rd0_? indicates a read flag
The internal register bus interface comprises six interfaces. The first four interfaces listed in Table 1 provide the register request described herein to the receiving module20, e.g., the write/read interface identifies whether the register request is a read request or a write request and the Reg_address interface carries the target register address. The remaining interfaces facilitate the read data passed up the pipeline as disclosed herein.

FIG. 5discloses another exemplary method200executed by a module20, Module K. Module K monitors an interface with a preceding module20, Module K−1, or the bus converter10to determine when a register request is received (block210), where the register request is sequentially passed through the modules20. When Module K receives a register request, a decoder23in Module K decodes the target address of the request (block220). If the decoded address is not in the address range of Module K (block230), Module K passes the register request along with any associated data to the succeeding module20, Module K+1 to pass the register request and the associated data down the module pipeline (block240). If, however, the decoded address is in the address range of Module K (block230), decoder23determines the request type (block250). If the register request is a write request, decoder23latches data associated with the register request into the matching register, i.e., the register in Module K having a register address matching the target register address (block260). If the register request is a read request, decoder23reads data from the matching register and sends the read data to the preceding module20, Module K−1 to pass the read data up the module pipeline (block270). In this case, each module20receives the read data from a succeeding module20and outputs the received read data to a preceding module20to pass the read data up the module pipeline.

The processing circuit5, module20, and corresponding methods100and200disclosed herein have several benefits over conventional implementations, e.g., better timing performance, flexible update, and reduced power consumption. In particular, because each module20only decodes its own register address and the internal register bus is segmented, the timing issues of the conventional solutions are avoided. Further, a new module20may be added by connecting it into any stage of the register pipeline without requiring any modifications to the logic functions already implemented by the processing circuit. Similarly, an old module20may be removed from the processing circuit by disconnecting it from the register pipeline. Also, because most of the circuit power is consumed when the internal registers are toggled, and because using the pipeline structure disclosed herein reduces the register toggle rate because the pipeline structure terminates the register request when it arrives at the module20containing the target register, the pipeline structure disclosed herein reduces the circuit power consumption.