Semiconductor integrated circuit device and fabrication method thereof

The invention discloses a semiconductor integrated circuit device characterized in that an inverse transistor element portion and a normal transistor element portion are formed in a common semiconductor layer and are separated from each other by an oxide layer penetrating said semiconductor layer in the direction of its thickness. In particular, in order to attain improved characteristics for the respective devices, the semiconductor layer of the inverse transistor element portion is thinner than the semiconductor layer of the normal transistor element portion.

BACKGROUND OF THE INVENTION 
This invention relates to a semiconductor integrated circuit device 
(hereinafter simply referred to as an "IC") including an I.sup.2 L 
(Integrated Injection Logic) element portion having an inverse transistor 
and a bipolar circuit element portion having a normal transistor. Further, 
this invention also relates to a method of fabricating the IC. 
The term "inverse transistor" herein denotes a transistor having a 
structure in which a semiconductor body such as a semiconductor substrate 
or a semiconductor layer (epitaxial layer) is used as its emitter region, 
a first semiconductor region formed in the semiconductor body is used as 
the base region and a second semiconductor region formed in the first 
semiconductor region is used as the collector region. On the other hand, 
the term "normal transistor" herein denotes a transistor having a 
structure in which the above-mentioned second semiconductor region is used 
as the emitter region, the above-mentioned first semiconductor region is 
used as the base region and the above-mentioned semiconductor body is used 
as the collector region. 
When an I.sup.2 L element and a linear or digital circuit element are to be 
separately disposed on a common epitaxial layer, a drawback develops with 
regard to the respective element characteristics. Specifically, the 
current amplification factor .beta..sub.i of the inverse transistor of the 
I.sup.2 L element increases with a decreasing thickness of the epitaxial 
layer. However, the collector-to-emitter or collector-to-base withstand 
voltage in the linear circuit element having a normal vertical transistor 
structure increases with an increasing thickness of the epitaxial layer. 
Therefore, in order to have both elements present together on a common 
epitaxial layer, it becomes necessary to sacrifice either the current 
amplification factor or the withstand voltage insofar as the thickness of 
the epitaxial layer is uniform. 
SUMMARY OF THE INVENTION 
It is therefore an object of the present invention to provide an IC of a 
composite element type in which both kinds of transistors are disposed on 
a single semiconductor substrate without lowering either the current 
amplification factor of the inverse transistor or the withstand voltage of 
the normal transistor. 
It is another object of the present invention to provide a method of 
fabricating the above-mentioned IC with a high level of reproducibility. 
In accordance with the IC of the present invention, the inverse transistor 
element portion and the normal transistor element portion are disposed on 
a common semiconductor layer and are separated from each other by an oxide 
layer penetrating the semiconductor layer in the direction of its 
thickness. Further, in conjunction with this, the semiconductor layer of 
the inverse transistor element portion is thinner than the semiconductor 
layer of the normal transistor element portion.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Hereinafter, an embodiment in which the present invention is applied to a 
composite layer type IC including an I.sup.2 L circuit element portion 
having an inverse transistor and a linear transistor circuit element 
portion having a normal transistor will be described with reference to the 
drawings. 
The IC of this embodiment will be explained according to its production 
steps. First, as depicted in FIG. 1A, and N.sup.- type epitaxial layer 3 
is grown to a thickness of 1.8 to 2.0 .mu.m on a P type Si substrate 1 
over an N.sup.+ type buried layer 2. The surface of this epitaxial layer 3 
is thermally oxidized to grow a thin protective SiO.sub.2 film 4. Then, a 
Si.sub.3 N.sub.4 is grown on the SiO.sub.2 film 4 by vapor growth and 
shaped in predetermined patterns 5a and 5b by ordinary photoprocessing. In 
this case, the Si.sub.3 N.sub.4 film 5a covers a portion where a bipolar 
transistor will be formed while the Si.sub.3 N.sub.4 film 5b covers a 
portion where the I.sup.2 L element will be formed. 
Next, as shown in FIG. 1B, the SiO.sub.2 film 4 and the epitaxial layer 3 
below these Si.sub.3 N.sub.4 films 5a, 5b are selectively etched to a 
depth of 0.6 to 1.2 .mu.m using the films 5a, 5b as the mask, forming a 
recess 6 for LOCOS oxidation (local oxidation). 
Subsequently, Si in the recess 6 is thermally oxidized using the Si.sub.3 
N.sub.4 films 5a, 5b as the mask as shown in FIG. 1C so as to form a 
relatively thick SiO.sub.2 layer 7 which extends into the epitaxial layer 
3 in the direction of its thickness. This SiO.sub.2 layer 7 encompassing 
each element region (i.e. the inverse transistor and the normal 
transistor) and separates them from one another. The growth condition for 
the oxidizing of the SiO.sub.2 layer 7 is, for example a temperature of 
1,000.degree. C. for a period of 5 hours in wet O.sub.2. 
Next, as shown in FIG. 1D, a photoresist 8 is deposited by ordinary 
techniques so as to cover a region in which the normal transistor of the 
bipolar transistor circuit element portion is to be formed. The the 
Si.sub.3 N.sub.4 film 5b on the I.sup.2 L side that is not covered with 
the photoresist 8 is selectively removed by exposure to CF.sub.4 plasma, 
exposing the original SiO.sub.2 film 4 at that portion. 
Next, as shown in FIG. 1E, the surface is successively thermally oxidized 
to extend the SiO.sub.2 layer 7 until it penetrates epitaxial layer 3, 
thereby growing a thick SiO.sub.2 layer 9 separating the epitaxial layer 3 
into the element regions 3a and 3b. This process is referred to as "LOCOS 
oxidation", and the SiO.sub.2 layer 9 thus obtained functions as an 
isolating film. Simultaneously with this LOCOS oxidation, the region 3b is 
oxidized so that the thin SiO.sub.2 film 4 grows into a relatively thick 
thermal oxidation SiO.sub.2 film 10 as shown in the drawing. This 
oxidation condition may be performed at a temperature of 1,000.degree. C. 
for a period of three hours in wet O.sub.2. By this treatment, the 
thickness of the SiO.sub.2 film 10 becomes 0.5 to 0.7 .mu.m. Consequently, 
the difference between the thickness of the surface SiO.sub.2 film 4 of 
the region 3a of the bipolar transistor circuit element portion and the 
thickness of the surface SiO.sub.2 film 10 of the inverse transistor 
region 3b of the I.sup.2 L circuit element portion becomes approximately 
0.3 .mu.m, for example, at this time. This difference is considerable 
since the original epitaxial layer 3 is extremely thin, i.e., 1.8 to 2.0 
.mu.m. 
Next, as shown in FIG. 1F, after the Si.sub.3 N.sub.4 film 5a is removed by 
plasma etching as described above, windows are bored in the SiO.sub.2 
surface films 4 and 10 by an ordinary photoprocess, and a P type impurity 
such as boron vapor is diffused through the thus-formed openings or 
reduced thickness portions. This forms a P type semiconductor region 11 to 
serve as the base in the region 3a, and P.sup.+ semiconductor regions 12 
and 13 to serve as the injector and base, respectively, in the inverse 
transistor in the region 3b. 
As shown in FIG. 1G, the surface of each SiO.sub.2 film 4 and 10 is further 
selectively etched using an ordinary photoprocess, and an N type impurity 
such as phosphorous is diffused in the gaseous phase from each opening or 
reduced thickness portion thus formed. In this manner, in region 3a an 
N.sup.+ ohmic contact region 14 is formed for taking out a collector 
electrode, and an N.sup.+ semiconductor region 15 is formed to serve as 
the emitter. In region 3b an N.sup.+ ohmic contact region 16 is formed to 
take out the emitter electrode of the inverse transistor, and an N.sup.+ 
semiconductor region 17 is formed as a multicollector. The SiO.sub.2 films 
4 and 10 on the surface are left, as passivation films, but the surfaces 
of these films 4 and 10 are preferably treated with phosphorous to 
stabilize them. Though not shown in the drawing, an opening is formed in 
the surface of each SiO.sub.2 film by an ordinary photoprocess, and 
electrodes are then fitted into these openings (by patterning after vacuum 
evaporation of Al on the entire surface, for example). Also an Al wiring 
as an upper wiring layer would be disposed with a necessary inter-layer 
insulating film, thereby completing the IC. These elements have been 
omitted from the drawings for clarity inasmuch as their formation is well 
known in the art. 
In accordance with the thus formed composite type IC in which the I.sup.2 L 
circuit element portion and the linear (bipolar) circuit element portion 
are both present, the thickness of the epitaxial layer 3b of the I.sup.2 L 
circuit element portion is considerably smaller than that of the epitaxial 
layer 3a of the linear circuit element portion due to the difference 
between the thicknesses of SiO.sub.2 films 10 and 4. For this reason, the 
current amplification ratio .beta..sub.1 of the inverse transistor in the 
I.sup.2 L circuit element portion can be made large while retaining the 
withstand voltage of the normal vertical transistor in the linear circuit 
element portion at a high level. Hence, both requirements for a high 
amplification factor and for a high withstand voltage can be satisfied in 
the same chip. Further, an IC with these excellent in these 
characteristics can be easily fabricated by carrying out LOCOS oxidation 
over two stages as described above. Moreover, in this case, if the 
oxidizing conditions (especially the oxidation time) in the step shown in 
FIG. 1D are suitably set, the difference between the thicknesses of 
epitaxial layers 3a and 3b can be controlled arbitrarily and with a high 
level of reproducibility. Accordingly, the structure and method in 
accordance with this embodiment are extremely effective when the epitaxial 
layer for forming each element is extremely thin. 
In particular, because the impurity concentration distribution in the 
direction of depth of the I.sup.2 L inverse transistor changes sharply 
between the semiconductor regions, the current amplification factor can 
also be improved in this respect. This advantage results from the fact 
that the thickness of the epitaxial layer 3b is reduced in this embodiment 
by growing the thick SiO.sub.2 film on the surface as described above, 
and, therefore, high concentration post-diffusion of the N type impurity 
inside the same layer does not occur. If the phosphorous inside the 
N.sup.+ buried layer 2 is post-diffused up into the epitaxial layer 3b in 
order to reduce the effective thickness of the epitaxial layer 3b, the 
change in the impurity concentration along the direction of thickness is 
only gradually graded towards the base side (13) due to the 
post-diffusion, and hence the current amplification ratio .beta..sub.i 
lowers. 
In accordance with the present invention, since the thickness of the 
semiconductor layer of the I.sup.2 L circuit element portion is made 
earlier than that of the normal bipolar circuit element portion already 
described, high current amplification ratio of the former and high 
withstand voltage of the latter can be simultaneously accomplished on the 
same chip. Moreover, these requirements can be easily satisfied with a 
high level of reproducibility or controllability by suitably selecting the 
oxidizing conditions when performing the surface oxidation. This is 
especially effective when the epitaxial layer is thin. 
Also, in accordance with the present invention, excellent isolation between 
the circuit elements is ensured by the insulating film so that the 
tendency to form a parasitic transistor is greatly reduced. The 
integration density can also be improved in comparison with PN junction 
isolation. 
Though the present invention is explained with reference to the 
above-mentioned embodiment, various modifications can be made on the basis 
of the technical concept of the present invention. For example, in the 
step shown in FIG. 1D, the Si.sub.3 N.sub.4 film 5b may be removed by 
etching with hot phosphoric acid in liquid phase. In such a case, it is 
preferred that an SiO.sub.2 film be disposed by a chemical vapor growth 
process between the photoresist 8 and the Si.sub.3 N.sub.4 film 5a. In the 
same figure, the Si.sub.3 N.sub.4 film 5a may also be removed and an 
oxidation-resistant mask may be applied to that portion. And, of course, 
the semiconductor type of each of the above-mentioned semiconductor 
regions may be suitably changed if desired. 
As another embodiment of the present invention, the following method is 
proposed. Namely, after the step shown in FIG. 1E is completed, the 
SiO.sub.2 films 4 and 10 formed on the surface of the regions 3a and 3b 
are removed by etching, as shown in FIG. 2A. Then, as shown in FIG. 2B, 
and insulating films 20a and 20b of a desired thickness are formed on the 
exposed surface of the regions 3a and 3b. Thereafter, the steps shown in 
FIGS. 1F through IA are carried out for formation of the regions of the 
respective transistors. 
Most preferably, the insulating films 20a and 20b are SiO.sub.2 films 
formed by oxidizing the surface of the regions 3a and 3b. However, if 
desired, they may be oxide films formed a CVD (chemical vapor deposition) 
process. In any event, in accordance with this method, the insulating 
films 20a and 20b are formed on the surface of the regions 3a and 3b are 
equal to each other so that simultaneous etching of these insulating films 
20a and 20b can readily be accomplished. 
In the step shown in FIG. 1D in each of the above-mentioned embodiments, 
the photoresist 8 may be left as such and an N type impurity such as 
phosphorus may be introduced into the epitaxial layer 3b through the thin 
SiO.sub.2 film 4 so as to reach the N.sup.+ type buried layer 2. 
Introduction of the N type impurity into the epitaxial layer 3b makes it 
possible to increase the speed of the I.sup.2 L circuit element. In this 
regard, it should be noted that since no mask is necessary for introducing 
the N type impurity, increasing the speed of the I.sup.2 L circuit element 
can easily be accomplished.