NITRIDE SEMICONDUCTOR DEVICE

The present disclosure provides a nitride semiconductor device. The nitride semiconductor device includes an electron travelling layer, an electron supply layer, a gate layer, a gate electrode, a source electrode, a drain electrode and a passivation layer. The gate layer includes a gate layer side surface located at an end portion of a side of the source electrode along a first direction, which is a direction in which the gate layer, the source electrode and the drain electrode are arranged. The passivation layer includes a passivation first side surface facing the source electrode along the first direction. The nitride semiconductor device further includes a source insulator film that covers the gate layer side surface and the passivation first side surface. The source insulator film insulates the gate layer from the source electrode.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-022511, filed on Feb. 16, 2023, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a nitride semiconductor device.

BACKGROUND

Currently, high electron mobility transistors (HEMTs) using Group III nitride semiconductors such as gallium nitride (GaN) (hereinafter sometimes simply referred to as “nitride semiconductors”) are being commercialized. HEMT uses two-dimensional electron gas (2DEG) formed near the semiconductor heterojunction interface as a conductive path (channel). Power devices using HEMTs are known to be capable of low on-resistance and high-speed/high-frequency operation compared to typical silicon (Si) power devices.

For example, the nitride semiconductor device described in Patent Document 1 includes an electron travelling layer composed of a gallium nitride (GaN) layer and an electron supply layer composed of an aluminum gallium nitride (AlGaN) layer. 2DEG is formed in the electron travelling layer near the heterojunction interface between the electron travelling layer and the electron supply layer. In addition, in the nitride semiconductor device of Patent Document 1, a gate layer (for example, a p-type GaN layer) containing acceptor-type impurities is provided at a position directly below the gate electrode on the electron travelling layer. In this structure, in the area directly below the gate layer, the gate layer will increase the band energy of the conduction band near the heterojunction interface between the electron travelling layer and the electron supply layer, so that the channel directly below the gate layer will disappear, thus achieving normal disconnection.

PRIOR TECHNICAL LITERATURE

Patent Documents

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the nitride semiconductor device disclosed herein will be illustrated with reference to the accompanying drawings.

In addition, in order to make the description simple and clear, the components shown in the drawings are not necessarily drawn on a fixed scale. Further, in order to facilitate understanding, hatching may be omitted in cross-sectional views. The drawings are merely used to illustrate the embodiments disclosed herein and should not be construed as limiting the invention disclosed herein.

The following detailed description includes devices, systems and methods that embody the exemplary embodiments disclosed herein. The detailed description is intended to be illustrative only, and is not intended to limit the embodiments disclosed herein or the application and use of such embodiments.

[Schematic Structure of Nitride Semiconductor Device]

FIG.1is a schematic top view of an exemplary nitride semiconductor device10according to an embodiment.FIG.2is a schematic cross-sectional view of the nitride semiconductor device10, taken along line2-2inFIG.1. In one example, the nitride semiconductor device10may be a HEMT using GaN. Hereinafter, the cross-sectional structure of the nitride semiconductor device10will be described first with reference toFIG.2, and then the planar structure of the nitride semiconductor device10will be described with reference toFIG.1.

As shown inFIG.2, the nitride semiconductor device10includes a semiconductor substrate12, a buffer layer14formed on the semiconductor substrate12, an electron travelling layer16formed on the buffer layer14, and an electron supply layer18formed on the electron travelling layer16.

The semiconductor substrate12may be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate12may be a Si substrate. The thickness of the semiconductor substrate12may be, for example, 200 μm or more and 1500 μm or less. The Z-axis direction of the mutually orthogonal XYZ axes shown inFIGS.1and2is the thickness direction of the semiconductor substrate12. In addition, the term “top view” used in this specification means that the nitride semiconductor device10is viewed from above along the Z-axis direction unless otherwise specified.

The buffer layer14may be located between the semiconductor substrate12and the electron travelling layer16. In one example, the buffer layer14may be made of any material that can easily epitaxially grow the electron travelling layer16. The buffer layer14may include one or more nitride semiconductor layers.

In one example, the buffer layer14may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a gate-type AlGaN layer with different aluminum (Al) combinations. For example, the buffer layer14may be composed of a single AlN layer, a single AlGaN layer, a layer with an AlGaN/GaN superlattice structure, a layer with an AlN/AlGaN superlattice structure, or a layer with an AlN/GaN superlattice structure. In addition, in order to suppress the leakage current in the buffer layer14, impurities may be introduced into a portion of the buffer layer14to make the buffer layer14semi-insulating. In this case, the impurity may be carbon (C) or iron (Fe), for example, and the concentration of the impurity may be set to 4×1016cm−3or more, for example.

The electron travelling layer16is composed of a nitride semiconductor. The electron travelling layer16is, for example, a GaN layer. The thickness of the electron travelling layer16is, for example, 0.5 μm or more and 2 μm or less. In addition, in order to suppress the leakage current in the electron travelling layer16, impurities may be introduced into a portion of the electron travelling layer16to make the region other than the surface layer region of the electron travelling layer16semi-insulating. In this case, the impurity is C, for example, and the peak concentration of the impurity in the electron travelling layer16is, for example, 1×1019cm−3or more.

The electron supply layer18is composed of a nitride semiconductor having a larger band gap than the electron travelling layer16. The electron supply layer18is an AlGaN layer, for example. In this case, the more the Al component, the larger the band gap. Therefore, the electron supply layer18which is an AlGaN layer has a larger band gap than the electron travelling layer16which is a GaN layer. In one example, the electron supply layer18is composed of AlxGa1−xN, where x is 0.1<x<0.4, and more preferably 0.2<x<0.3. The thickness of the electron supply layer18is, for example, 5 nm or more and 20 nm or less.

The electron travelling layer16and the electron supply layer18are composed of nitride semiconductors having different lattice constants from each other. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron travelling layer16and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer18form a lattice-mismatched heterojunction. The energy level of the conduction band of the electron travelling layer16near the heterojunction interface will become lower than the Fermi level due to the spontaneous polarization of the electron travelling layer16and the electron supply layer18and the piezoelectric polarization induced by the stress on the electron supply layer18near the heterojunction interface. Therefore, in the electron travelling layer16at a position close to the heterojunction interface between the electron travelling layer16and the electron supply layer18(for example, within a range of about a few nanometers from the interface), there will be diffusion of two-dimensional electron gas (2DEG)20.

The nitride semiconductor device10further includes a gate layer22formed on the electron supply layer18, a gate electrode24formed on the gate layer22, and a passivation layer26. The passivation layer26is formed above the electron supply layer18, the gate layer22, and the gate electrode24, and includes a first opening26A and a second opening26B. In addition, the nitride semiconductor device10further includes a source electrode28connected to the electron supply layer18via the first opening26A, and a drain electrode30connected to the electron supply layer18via the second opening26B.

The gate layer22is located between the first opening26A and the second opening26B of the passivation layer26and is separated from the first opening26A and the second opening26B respectively. The gate layer22is located closer to the first opening26A than the second opening26B. The detailed structure of the gate layer22will be described below.

The gate layer22is composed of a nitride semiconductor that has a smaller band gap than the electron supply layer18and contains acceptor-type impurities. The gate layer22may be made of any material having a smaller band gap than the electron supply layer18which is an AlGaN layer, for example. In one example, the gate layer22is a GaN layer doped with acceptor-type impurities (p-type GaN layer). The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), and C. The maximum concentration of the acceptor-type impurities in the gate layer22is, for example, 1×1018cm−3or more and 1×1020cm−3or less.

By including the acceptor-type impurity in the gate layer22as described above, the energy levels of the electron travelling layer16and the electron supply layer18are raised. Therefore, in the region directly below the gate layer22, the energy level of the conduction band of the electron travelling layer16near the heterojunction interface between the electron travelling layer16and the electron supply layer18becomes approximately the same as the Fermi level, or larger than the Fermi level. Therefore, when voltage is not applied to the gate electrode24(zero bias), 2DEG20is not formed in the region directly below the gate layer22in the electron travelling layer16. 2DEG20will be formed in the region other than the region directly below the gate layer22in the electron travelling layer16.

In this way, due to the presence of the gate layer22doped with the acceptor-type impurities, the 2DEG20in the region directly below the gate layer22is destroyed. As a result, the normally-off operation of the transistor is achieved. If an appropriate turn-on voltage is applied to the gate electrode24, a channel composed of 2DEG20will be formed in the region directly below the gate electrode24in the electron travelling layer16, so that the source-drain conduction occurs.

The gate electrode24is composed of one or more metal layers. In one example, the gate electrode24is a titanium nitride (TiN) layer. Alternatively, the gate electrode24may be composed of a first metal layer and a second metal layer laminated on the first metal layer, the first metal layer is made of a material containing Ti, and the second metal layer is made of a material containing TiN. The gate electrode24may form a Schottky junction with the gate layer22. The gate electrode24may be formed in a smaller area than the gate layer22in a top view. The thickness of the gate electrode24is, for example, 50 nm or more and 200 nm or less.

The passivation layer26is formed on the electron supply layer18. It can also be said that the passivation layer26covers the electron supply layer18. The passivation layer26may be made of, for example, a material including any one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), AlN, and aluminum oxynitride (AlON).

The thickness of the passivation layer26is greater than the thickness of the electron supply layer18. The thickness of the passivation layer26is, for example, 300 nm or more and 1,000 nm or less. In addition, the thickness of the passivation layer26can be changed arbitrarily. The detailed structure of the passivation layer26will be described below.

The source electrode28and the drain electrode30are arranged on the upper surface of the electron supply layer18with the gate layer22interposed therebetween. The source electrode28and the drain electrode30may be composed of one or more metal layers. For example, the source electrode28and the drain electrode30may be composed of a combination of two or more metal layers selected from the group consisting of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, an AlCu layer, and the like. At least a portion of the source electrode28is filled in the first opening26A, and is in ohmic contact with the 2DEG20directly below the electron supply layer18via the first opening26A. Similarly, at least a portion of the drain electrode30is filled in the second opening26B, and is in ohmic contact with the 2DEG20directly below the electron supply layer18via the second opening26B.

In one example, the source electrode28may include a source contact portion28A filled in the first opening26A, and a source field plate portion28B formed on the passivation layer26. The source field plate portion28B is continuous with the source contact portion28A and is integrally formed with the source contact portion28A. The source field plate portion28B includes an end portion28C located between the second opening26B and the gate layer22in a top view. The source field plate portion28B is separated from the drain electrode30. The source field plate portion28B functions as follows: when a drain voltage is applied to the drain electrode30in a zero-bias state in which a gate voltage is not applied to the gate electrode24, the electric field concentration near an end of the gate electrode24and near an end of the gate layer22is relaxed.

[Detailed Structure of Gate Layer]

The gate layer22may have a stepped structure. Hereinafter, the details of the gate layer22having the stepped structure will be described with reference toFIG.3.FIG.3is an enlarged cross-sectional view of the periphery of the source electrode28and the gate electrode24in the nitride semiconductor device10ofFIG.2. Furthermore, 2DEG20is omitted fromFIG.3.

The gate layer22includes a ridge portion42and extension portions43extending in opposite directions from both sides of the ridge portion42. The ridge portion42and the extension portion43form a stepped structure of the gate layer22.

The ridge portion42corresponds to a relatively thick portion of the gate layer22. The gate electrode24contacts the ridge portion42. The ridge portion42may have a rectangular shape or a trapezoidal shape in a cross-section along the XZ plane ofFIG.3. The ridge portion42may have a thickness of, for example, 100 nm or more and 200 nm or less. The thickness T1of the ridge portion42refers to the distance from the upper surface to the lower surface of the ridge portion42(from the upper surface22A of the gate layer22on which the gate electrode24is formed to the lower surface22B of the gate layer22in contact with the electron supply layer18). The thickness T1of the ridge portion42(the gate layer22) can be determined taking into consideration of various parameters such as the gate withstand voltage.

The extension portion43includes a source-side extension portion44and a drain-side extension portion46. The source-side extension portion44extends from the ridge portion42toward the first opening26A of the passivation layer26. The drain-side extension portion46extends from the ridge portion42toward the second opening26B of the passivation layer26(referring toFIG.2). The source-side extension portion44and the drain-side extension portion46may have the same length, or may have different lengths.

The source-side extension portion44may have a thickness T2of 5 nm or more and 30 nm or less, for example. The source-side extension portion44may have a first direction length L1of, for example, 100 nm or more in the direction from the ridge portion42toward the first opening26A. The first direction length L1of the source-side extension portion44is, for example, 200 nm or more and 300 nm or less. The drain-side extension portion46may have a thickness T3of 5 nm or more and 30 nm or less, for example. The drain-side extension portion46may have a first direction length L2of, for example, 200 nm or more and 600 nm or less in the direction from the ridge portion42toward the second opening26B. The thickness T2of the source-side extension portion44and the thickness T3of the drain-side extension portion46are equal to each other. Here, if the difference between the thickness T2of the source-side extension portion44and the thickness T3of the drain-side extension portion46is, for example, within 10% of the thickness of the source-side extension portion44, then it can be said that the thickness T2of the source-side extension portion44and the thickness T3of the drain-side extension portion46are equal to each other.

The gate layer22has an upper surface22A and a lower surface22B. The lower surface22B is the surface of the gate layer22facing the upper surface18A of the electron supply layer18, and the upper surface22A is the surface of the gate layer22located on the opposite side to the lower surface22B. The upper surface22A of the gate layer22having the stepped structure represents the upper surface of the ridge portion42. The lower surface22B of the gate layer22having the stepped structure represents a surface including the lower surface of the ridge portion42, the lower surface of the source-side extension portion44, and the lower surface of the drain-side extension portion46.

In addition, the cross-sectional shape of the gate layer22is not limited to a shape having a stepped structure. For example, the gate layer22may have a rectangular, trapezoidal or ridge-shaped cross-section on the XZ plane inFIG.1.

As shown inFIG.2, an example of the passivation layer26includes at least a first passivation layer51formed above the electron supply layer18and a second passivation layer52formed above the first passivation layer51. In addition, the field plate electrode53is embedded between the first passivation layer51and the second passivation layer52of the passivation layer26.

An example of the first passivation layer51is formed on the gate electrode24, a region of the gate layer22located closer to the drain electrode30than the gate electrode24, and a region of the electron supply layer18located between the gate layer22and the drain electrode30. In other words, the first passivation layer51is in contact with and covers the upper surfaces of the gate electrode24, the region of the gate layer22, and the region of the electron supply layer18.

As shown inFIG.3, the first passivation layer51has a first side surface51A located at an end on the source electrode28side in the X direction, that is, the direction in which the source electrode28, the gate electrode24and the drain electrode30are arranged (hereinafter referred to as the first direction). The first side surface51A of the first passivation layer51is located above the electrode side surface24A that is located at an end of the gate electrode24on the source electrode28side. The first side surface51A and the electrode side surface24A are on the same plane and form a continuous side surface. In addition, as shown inFIG.2, the first passivation layer51has a second side surface51B located at an end on the drain electrode30side in the first direction.

In addition, the first passivation layer51only needs to be formed at least partially on a region of the electron supply layer18closer to the drain electrode than the gate layer22. In addition, when the field plate electrode53is provided, the first passivation layer51has a portion located between the field plate electrode53and the gate layer22and between the field plate electrode53and the gate electrode24.

The first passivation layer51has a thickness of, for example, 50 nm or more and 200 nm or less. The thickness of the first passivation layer51may be, for example, the thickness of the portion formed on the electron supply layer18or the thickness of the portion formed on the gate electrode24or the gate layer22.

As shown inFIG.2, an example of the second passivation layer52includes: a source side portion52A formed on a portion of the gate layer22closer to the source electrode28than the gate electrode24; and a drain side portion52B formed on the first passivation layer51. A field plate electrode53is formed between the first passivation layer51and the drain side portion52B of the second passivation layer52. Details of the field plate electrode53will be described below.

As shown inFIG.3, the source side portion52A of the second passivation layer52has a first side surface52C located at an end on the source electrode28side in the first direction. The first side surface52C of the second passivation layer52is located above the gate layer side surface22C, which is located at the end of the gate layer22on the source electrode28side. In the example shown inFIG.3, the gate layer side surface22C is the front end surface of the source-side extension portion44. The first side surface52C of the second passivation layer52and the gate layer side surface22C are on the same plane, and form a continuous side surface. In addition, the source side portion52A of the second passivation layer52is in contact with the electrode side surface24A of the gate electrode24and the first side surface51A of the first passivation layer51.

As shown inFIG.2, the drain-side portion52B of the second passivation layer52has a second side surface52D located at an end on the drain electrode30side in the first direction. The second side surface52D of the second passivation layer52is located above the second side surface51B of the first passivation layer51. The second side surface52D of the second passivation layer52and the second side surface51B of the first passivation layer51are on the same plane and form a continuous side surface.

Herein, the passivation layer26has a passivation first side surface26C facing the source electrode28in the first direction, and a passivation second side surface26D facing the drain electrode30. The passivation first side surface26C is formed from the first side surface52C of the second passivation layer52. The passivation second side surface26D is formed from the second side surface51B of the first passivation layer51and the second side surface52D of the second passivation layer52.

In addition, it can also be said that the second passivation layer52is a portion of the passivation layer26other than the first passivation layer51. The formation range of the second passivation layer52can be changed according to the formation range of the first passivation layer51.

The second passivation layer52is formed thicker than the first passivation layer51, for example. The thickness of the second passivation layer52is, for example, the thickness T3of the portion forming the first side surface52C in the source side portion52A. The thickness T3of the second passivation layer52is, for example, 500 nm or more and 1,500 nm or less. In addition, the thickness T3of the second passivation layer52can also be said to be the thickness on the first side surface52C of the second passivation layer52.

Each of the first passivation layer51and the second passivation layer52may be made of the material comprising any one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), AlN, and aluminum oxynitride (AlON), for example. The first passivation layer51and the second passivation layer52may be made of the same material. In one example, the first passivation layer51and the second passivation layer52are both silicon nitride (SiN) layers.

In addition, the first passivation layer51and the second passivation layer52may be made of different materials. In one example, the first passivation layer51is a silicon nitride (SiN) layer, and the second passivation layer52is a silicon dioxide (SiO2) layer. By setting the first passivation layer51covering the electron supply layer18as a silicon nitride (SiN) layer, the surface of the electron supply layer18is protected, thereby enabling the effect of reducing trap energy level. In addition, by setting the second passivation layer52that forms the passivation first side surface26C facing the source electrode28as a silicon dioxide (SiO2) layer, even if the source electrode28is sintered, it is also possible to more stably insulate the gate electrode24from the source electrode28.

Next, the field plate electrode53will be described. As shown inFIG.2, the field plate electrode53is separated from the drain electrode30. The field plate electrode53functions as follows: when a drain voltage is applied to the drain electrode30in a zero-bias state in which a gate voltage is not applied to the gate electrode24, the electric field concentration near the end of the gate layer22is relaxed. In addition, the source field plate portion28B of the source electrode28relaxes the electric field concentration when a relatively large voltage is applied, and the field plate electrode53relaxes the electric field concentration when a relatively small voltage is applied.

At least a portion of the field plate electrode53is formed between the gate layer22on the first passivation layer51and the drain electrode30. The field plate electrode53is electrically connected to the source electrode28, but this is not shown inFIG.2. Details of the connection structure between the field plate electrode53and the source electrode28will be described below.

The field plate electrode53includes a first end portion53A that is an end portion in the first direction, and a second end portion53B located on the opposite side of the first end portion53A. The first end portion53A is an end portion of the field plate electrode53close to the source electrode28. The second end53B is an end of the field plate electrode53close to the drain electrode30.

The second end portion53B of the field plate electrode53is located on the first passivation layer51between the gate layer22and the drain electrode30. The second end portion53B is located, for example, between the gate layer22and the drain electrode30and close to the gate layer22.

As shown inFIG.3, an example of the first end portion53A of the field plate electrode53is located above the gate electrode24. In this case, the field plate electrode53has a portion that overlaps the gate electrode24with the first passivation layer51therebetween. As the area of the portion of the field plate electrode53overlapping the gate electrode24increases, the parasitic capacitance between the gate and the source increases. By increasing the parasitic capacitance between the gate and the source, self-starting is suppressed, and the operation of the nitride semiconductor device10becomes stable. Furthermore, in this case, the field plate electrode53covers the end of the gate layer22on the side close to the drain electrode30(the tip of the drain-side extension portion46) with the first passivation layer51therebetween. As a result, the electric field concentration at the end of the gate layer22close to the drain electrode30can be alleviated.

In addition, the position of the first end portion53A of the field plate electrode53can be changed as appropriate. For example, it may be located above a region of the gate layer22closer to the drain electrode30than the gate electrode24(for example, above the drain-side extension portion46), or may be located on the first passivation layer51between the gate layer22and the drain electrode30.

Herein, the positional relationship between the field plate electrode53and the source field plate portion28B of the source electrode28will be described. As shown inFIG.2, the source field plate portion28B is formed above the second passivation layer52. The end portion28C of the source field plate portion28B is located closer to the drain electrode30than the second end portion53B of the source field plate electrode53in the first direction.

The source electrode28and the drain electrode30may be composed of a combination of two or more metal layers selected from the group consisting of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, an AlCu layer, and the like. The field plate electrode53may be composed of one or more metal layers. For example, the field plate electrode53is composed of a TiN layer or a combination of a Ti layer and a TiN layer. In addition, an example of the field plate electrode53may be made of the same material as one or both of the source electrode28and the drain electrode30.

[Peripheral Structure of Source Electrode and Gate Electrode]

As shown inFIG.3, the nitride semiconductor device10includes a source insulator film61that insulates the source electrode28and the gate layer22. The source insulator film61is formed between the source electrode28and the gate layer22and covers the gate layer side surface22C of the gate layer22. In addition, the source insulator film61is formed between the source electrode28and the passivation layer26and covers the passivation first side surface26C of the passivation layer26.

The source insulator film61is formed by self-alignment with respect to the side surface (sidewall) formed by the passivation first side surface26C of the passivation layer26and the gate layer side surface22C of the gate layer22of. In this way, the source insulator film61can be formed thin. The first direction length L3of the source insulator film61is shorter than the first direction length L1of the source side extension portion44of the gate layer22. The first direction length L3of the source insulator film61is less than 100 nm, for example.

The source insulator film61may be made of the material comprising, for example, any one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), AlN, and aluminum oxynitride (AlON). In one example, the source insulator film61is a silicon dioxide (SiO2) film. In addition, the source insulator film61may be made of the same material as the first passivation layer51, or may be made of a different material from the first passivation layer51. In addition, the source insulator film61may be made of the same material as the second passivation layer52, or may be made of a different material from the second passivation layer52. An example of the source insulator film61is composed of a material having higher insulation properties than the portion forming the passivation first side surface26C, which is the second passivation layer52.

[Peripheral Structure of Drain Electrode]

As shown inFIG.2, the nitride semiconductor device10further includes a drain insulator film62. The drain insulator film62covers the passivation second side surface26D of the passivation layer26and is insulated from the passivation second side surface26D. The drain insulator film62is formed with respect to the passivation second side surface26D of the passivation layer26, i.e. the side surface (sidewall) formed by the second side surface51B of the first passivation layer51and the second side surface52D of the second passivation layer52, through self-alignment. As a result, the drain insulator film62can be formed thin. The first direction length L4of the drain insulator film62is less than 100 nm, for example. The first direction length L4of the drain insulator film62may be the same as or different from the first direction length L1of the source insulator film61.

The drain insulator film62may be made of, for example, the material comprising any one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), AlN, and aluminum oxynitride (AlON). In one example, the drain insulator film62is a silicon dioxide (SiO2) film. In addition, the drain insulator film62may be made of the same material as the first passivation layer51, or may be made of a different material from the first passivation layer51. In addition, the drain insulator film62may be made of the same material as the second passivation layer52, or may be made of a different material from the second passivation layer52.

The drain insulator film62is, for example, interposed between the sites where a large electric field concentration occurs, i.e. between the end of the drain electrode30in the first direction and the passivation layer26, thereby suppressing electrons from the drain electrode30from injection into the passivation layer26. In this case, long-term stability of the electrical characteristics (for example, withstand voltage between the drain and source) of the nitride semiconductor device10can be achieved.

[Planar Structure of Nitride Semiconductor Device]

Next, the planar structure of the nitride semiconductor device10will be described with reference toFIG.1. InFIG.1, the passivation layer26and the source electrode28are omitted, and the first opening26A and the second opening26B are drawn with dotted lines.

The nitride semiconductor device10includes, for example, a working region that contributes to transistor operation and a non-working region (not shown) that does not contribute to transistor operation. In one example, working regions and non-working regions are alternately arranged along the Y direction.

In the working region of the nitride semiconductor device10, the source electrode28(referring toFIG.2), the gate electrode24, and the drain electrode30are arranged adjacent to each other in the X direction on the electron supply layer18(referring toFIG.2). The combination of the source electrode28, the gate electrode24, and the drain electrode30adjacent in the X direction constitutes one HEMT cell10HC. In the example ofFIG.1, two HEMT units10HC are arranged along the X direction in the working region. In addition, more HEMT units10HC can actually be configured in each working region.

As shown inFIG.1, the field plate electrode53is formed in a ring shape surrounding the drain electrode30in a top view. The field plate electrode53has body portions53C located between the source electrode28and the drain electrode30in a top view; and connection portions53D located closer to one side and the other side of the Y direction than the drain electrode30, connecting two adjacent body portions53C to each other.

A bonding via54is formed in the second passivation layer52(not shown) located on the connection portion53D of the field plate electrode53. The bonding via54penetrates the second passivation layer52(not shown) and is connected to the source electrode28(the source field plate portion28B). As a result, the field plate electrode53is electrically connected to the source electrode28through the bonding via54.

[Method for Manufacturing Nitride Semiconductor Device]

An exemplary method for manufacturing the nitride semiconductor device10will be described with reference toFIGS.4to26. In addition, inFIGS.4to26, the same components as those inFIG.1are denoted by the same reference numerals. In addition, inFIGS.4to26, the semiconductor substrate12and the buffer layer14as shown inFIG.2are omitted for simple illustration.

The method for manufacturing the nitride semiconductor device10includes the following steps: forming an electron travelling layer16; and forming an electron supply layer18on the electron travelling layer16. The method for manufacturing the nitride semiconductor device10further includes the following steps: forming a gate layer22on the electron supply layer18; forming a gate electrode24on the gate layer22; and forming a passivation layer26on the electron supply layer18, the gate layer22, and the gate electrode24. An example of the step of forming the passivation layer26includes: forming a first passivation layer51on the electron supply layer18, the gate layer22, and the gate electrode24; forming a field plate electrode53on the first passivation layer51; and forming a second passivation layer52on the first passivation layer51with the field plate electrode53interposed therebetween.

As shown inFIG.4, the buffer layer14(not shown), the electron travelling layer16, the electron supply layer18and a first nitride semiconductor layer71are sequentially formed on the semiconductor substrate12(not shown). The semiconductor substrate12is, for example, a Si substrate. The buffer layer14, the electron travelling layer16, the electron supply layer18and the first nitride semiconductor layer71are formed, for example, by epitaxial growth using a Metal Organic Chemical Vapor Deposition (MOCVD) method.

The buffer layer14(referring toFIG.1) may be a multilayer buffer layer, for example, but the relevant illustration is omitted. The multilayer buffer layer may include an AlN layer (the first buffer layer) formed on the semiconductor substrate12and a gate-type AlGaN layer (the second buffer layer) formed on the AlN layer. In one example, the gate-type AlGaN layer is formed by sequentially laminating three AlGaN layers with Al components of 75%, 50%, and 25% respectively, starting from the side close to the AlN layer.

The electron travelling layer16is, for example, a GaN layer, and the electron supply layer18is, for example, an AlGaN layer. Therefore, the electron supply layer18is composed of a nitride semiconductor having a larger band gap than the electron travelling layer16. The first nitride semiconductor layer71is a layer for forming the gate layer22and is, for example, a GaN layer containing Mg as an acceptor type impurity. The first nitride semiconductor layer71is formed by doping GaN with Mg while GaN is grown on the electron supply layer18.

Next, a first electrode layer72is formed on the first nitride semiconductor layer71, and a first protective layer73is formed on the first electrode layer72. The first electrode layer72is a layer used to form the gate electrode24, and is, for example, a TiN layer. The first electrode layer72is formed by a sputtering method, for example. The first protective layer73is, for example, a SiN layer. The first protective layer73is formed, for example, by a plasma-enhanced chemical vapor deposition (PECVD) method.

Next, as shown inFIG.5, the first electrode layer72and the first protective layer73are selectively removed so as to expose a portion of the upper surface of the first nitride semiconductor layer71, and then the second protective layer74covering the first electrode layer72, the first protective layer73and the first nitride semiconductor layer71is formed. The first electrode layer72and the first protective layer73are selectively removed, for example, by performing photolithography and etching using a mask. The second protective layer74is, for example, a SiN layer. The second protective layer74is formed by the PECVD method, for example.

Next, as shown inFIG.6, the second protective layer74is etched back by, for example, the full-surface anisotropic dry etching until the upper surface of the first electrode layer72is exposed. As a result, the remaining portion of the second protective layer74is formed as a mask74A covering the side surface of the first electrode layer72, the side surface of the first protective layer73and a portion of the upper surface of the first nitride semiconductor layer71.

Next, as shown inFIG.7, etching is performed using the first protective layer73and the mask74A, thereby selectively removing the first nitride semiconductor layer71. Therefore, the drain portion71A is formed to be locally thinner than the first nitride semiconductor layer71. The drain portion71A is a portion for forming the drain-side extension portion46.

Next, as shown inFIG.8, a third protective layer75is formed to cover the first protective layer73, the mask74A, and the drain portion71A of the first nitride semiconductor layer71. The third protective layer75is, for example, a SiN layer. The third protective layer75is formed by the PECVD method, for example.

Next, as shown inFIG.9, the third protective layer75is etched back by, for example, the full-surface anisotropic dry etching until the upper surface of the drain portion71A of the first nitride semiconductor layer71is exposed. As a result, the remaining portion of the third protective layer75is formed into the mask75A covering the side surface of the mask74A, the side surface of the first nitride semiconductor layer71and a portion of the upper surface of the drain portion71A.

Next, as shown inFIG.10, the drain portion71A of the first nitride semiconductor layer71is selectively removed by etching using the first protective layer73, the mask74A, and the mask75A. Therefore, the remaining portion of the drain portion71A is formed as the drain-side extension portion46.

Next, as shown inFIG.11, after peeling off the first protective layer73, the mask74A and the mask75A, a first insulator layer76covering the first electrode layer72, the first nitride semiconductor layer71and the electron supply layer18is formed. The first insulator layer76is a layer for forming the first passivation layer51. The first insulator layer76is, for example, a SiN layer. The first insulator layer76is formed by, for example, the Low Pressure Chemical Vapor Deposition (LPCVD) method.

Next, as shown inFIG.12, a second electrode layer77is formed on the first insulator layer76. The second electrode layer77is a layer used to form the field plate electrode53, and is, for example, a TiN layer. The second electrode layer77is formed by the PECVD method, for example.

Next, as shown inFIG.13, the second electrode layer77is selectively removed. As a result, the remaining portion of the second electrode layer77is formed into the field plate electrode53. The second electrode layer77is selectively removed by, for example, performing photolithography and etching using a mask.

Next, as shown inFIG.14, a second insulator layer78covering the first insulator layer76and the field plate electrode53is formed. The second insulator layer78is a layer for forming the second passivation layer52. The second insulator layer78is, for example, a SiO2layer. The second insulator layer78is formed by, for example, the PECVD method.

Next, as shown inFIG.15, the first electrode layer72, the first insulator layer76and the second insulator layer78are selectively removed so as to expose a portion of the upper surface of the first nitride semiconductor layer71. The first electrode layer72, the first insulator layer76, and the second insulator layer78are selectively removed by, for example, performing photolithography and etching using a mask. As a result, the remaining portion of the first electrode layer72is formed into the gate electrode24.

Next, as shown inFIG.16, a third insulator layer79covering the first nitride semiconductor layer71, the first electrode layer72, the first insulator layer76and the second insulator layer78is formed. The third insulator layer79is, for example, a SiN layer. The third insulator layer79is formed by the PECVD method, for example.

Next, as shown inFIG.17, the third insulator layer79is etched back by, for example, full-surface anisotropic dry etching until the upper surface of the first nitride semiconductor layer71is exposed. As a result, the remaining portions of the third insulator layer79form the second passivation component parts79A and79B. The second passivation component part79A covers the side surface of the gate electrode24, the side surface of the second insulator layer78located above the side surface of the gate electrode24, and a portion of the upper surface of the first nitride semiconductor layer71. The second passivation component part79B covers a portion of the upper surface and a portion of the side surface of the second insulator layer78.

Next, as shown inFIG.18, the first nitride semiconductor layer71is selectively removed by etching using the first protective layer73and the second passivation component part79B. As a result, the source portion71B is formed that is locally thinner than the first nitride semiconductor layer71. The source portion71B is a portion for forming the source-side extension portion44.

Next, as shown inFIG.19, a fourth insulator layer80covering the source-side extension portion44of the first nitride semiconductor layer71, the second insulator layer78, and the second passivation component portions79A and79B is formed. The fourth insulator layer80is, for example, a SiO2layer. The fourth insulator layer80is formed by, for example, the PECVD method.

Next, as shown inFIG.20, the fourth insulator layer80is etched back by, for example, full-surface anisotropic dry etching until the upper surface of the source-side extension portion44of the first nitride semiconductor layer71is exposed. In addition, the remaining portion of the fourth insulator layer80is used to form the second passivation component portions80A and80B. The second passivation component portion80A covers the side surface of the second passivation component portion79A and a portion of the upper surface and side surface of the first nitride semiconductor layer71. The side surface of the second passivation component portion80A is the passivation first side surface26C. The second passivation component portion80B covers a portion of the side surface of the second passivation component portion79A and a portion of the upper surface of the second insulator layer78.

Next, as shown inFIG.21, the source portion71B of the first nitride semiconductor layer71is selectively removed by etching using the second insulator layer78and the second passivation component portions79A,79B,80A, and80B. Therefore, the remaining portion of the source portion71B is formed as the source-side extension portion44. The remaining portion of the first nitride semiconductor layer71is used to form the gate layer22having the source-side extension portion44and the drain-side extension portion46. In addition, the first opening26A of the passivation layer26is thus formed in such a manner that the gate layer side surface22C located at the end of the gate layer22is exposed.

Next, as shown inFIG.22, the first insulator layer76and the second insulator layer78are selectively removed so as to expose a portion of the upper surface of the electron supply layer18. The first insulator layer76and the second insulator layer78are selectively removed by photolithography and etching using a mask, for example. Thus, the passivation layer26and the second opening26B of the passivation layer26are formed.

Specifically, the first passivation layer51is formed using the remaining portion of the first insulator layer76. In addition, the second passivation layer52is formed from the remaining portion78A of the second insulator layer78and the second passivation component portions79A,79B,80A, and80B. The side surface of the first passivation layer51where the second opening26B is formed and the side surface of the second passivation layer52(the side surface of the remaining portion78A of the second insulator layer78) serve as the passivation second side surface26D.

The method for manufacturing the nitride semiconductor device10further includes the step of forming the source insulator film61and the drain insulator film62on the passivation first side surface26C of the passivation layer26. This step includes forming an insulator layer (the fifth insulator layer81described below) covering the upper surface and the passivation first side surface26C of the passivation layer26, the side surface of the gate layer22on the source electrode28side (the side surface of the source-side extension portion44), and the upper surface of the electron supply layer18; and removing a portion of the insulator layer covering the upper surface of the electron supply layer18.

As shown inFIG.23, a fifth insulator layer81is formed to cover the upper surface and side surface of the passivation layer26, the side surface of the source-side extension portion44of the gate layer22, and the upper surface of the electron supply layer18exposed from the first opening26A and the second opening26B. The fifth insulator layer81is, for example, a SiO2layer. The fifth insulator layer81is formed by the PECVD method, for example.

Next, as shown inFIG.24, the fifth insulator layer81is etched back by, for example, full-surface anisotropic dry etching until the upper surface of the electron supply layer18is exposed. That is, the portions of the fifth insulator layer81formed on the upper surface of the passivation layer26and the upper surface of the electron supply layer18are removed. As a result, the source insulator film61covering the passivation first side surface26C of the passivation layer26is formed, and the drain insulator film62covering the passivation second side surface26D is formed. In this way, the source insulator film61and the drain insulator film62can be formed by self-alignment.

The method for manufacturing the nitride semiconductor device10includes the step of forming the source electrode28and the drain electrode30so as to be in contact with the electron supply layer18.

As shown inFIG.25, the third electrode layer82is formed on the passivation layer26, the source insulator film61and the drain insulator film62. The third electrode layer82is a layer used to form the source electrode28and the drain electrode30, and is, for example, a Ti layer. The third electrode layer82is formed by the PECVD method, for example.

The third electrode layer82is formed on the entire upper surface of the passivation layer26. The third electrode layer82fills the first opening26A of the passivation layer26and is in contact with the upper surface of the electron supply layer18and the source insulator film61within the first opening26A. The third electrode layer82fills the second opening26B of the passivation layer26and is in contact with the upper surface of the electron supply layer18and the drain insulator film62within the second opening26B. In addition, when the third electrode layer82is formed, the bonding via54electrically connecting the field plate electrode53and the third electrode layer82is formed in the passivation layer26.

Next, as shown inFIG.26, the third electrode layer82is selectively removed. As a result, the remaining portion of the third electrode layer82is formed into the source electrode28and the drain electrode30. The third electrode layer82is selectively removed by, for example, performing photolithography and etching using a mask. Through the above steps, the nitride semiconductor device10as shown inFIG.1is manufactured.

Next, the function of the nitride semiconductor device10according to the embodiment will be described.

As shown inFIG.3, the source insulator film61of the nitride semiconductor device10is formed on the passivation first side26C of the passivation layer26and the gate layer side surface22C (the front end surface of the source-side extension portion44) of the gate layer22. The source insulator film61is formed in manner of contacting the source electrode28and the gate layer side surface22C.

By disposing the source insulator film61between the gate layer22and the source electrode28, the gate layer22and the source electrode28are effectively separated, such that the gate layer22is insulated from the source electrode28. As a result, the leakage path electrically connecting the gate electrode24, the gate layer22, and the source electrode28is blocked, thereby suppressing the generation of gate leakage current and improving the gate withstand voltage.

In addition, since the source insulator film61is the only component located between the gate layer22and the source electrode28in the first direction, the source electrode28can be disposed at a position closer to the gate layer side surface22C of the gate layer22. Therefore, the distance between the source electrode28and the drain electrode30can be shortened, thereby achieving the reduction of on-resistance.

Effects

The nitride semiconductor device10according to the embodiments can obtain the following effects.

The nitride semiconductor device10includes: the electron travelling layer16; the electron supply layer18formed on the electron travelling layer16; the gate layer22formed on the electron supply layer; and the gate electrode24formed on the gate layer22; the source electrode28and the drain electrode30in contact with the upper surface of the electron supply layer18; and the passivation layer26formed above the electron supply layer18, the gate layer22and the gate electrode24. The gate layer22includes the gate layer side surface22C, which is located at the end on the source electrode28side in the direction in which the gate layer22, the source electrode28and the drain electrode30are arranged, i.e. the first direction. The passivation layer26includes the passivation first side surface26C facing the source electrode28in the first direction. The nitride semiconductor device10further includes the source insulator film61that covers the gate layer side surface22C and the passivation first side surface26C and insulates the gate layer22from the source electrode28.

According to this configuration, the leakage path electrically connecting the gate electrode24, the gate layer22and the source electrode28is blocked by the source insulator film61. By blocking the leakage path, the generation of the gate leakage current flowing from the gate electrode24to the source electrode28is suppressed so as to improve the gate withstand voltage. In addition, since the source electrode28can be disposed closer to the gate layer side surface22C of the gate layer22, the distance between the source electrode28and the drain electrode30can be shortened, thereby achieving the reduction of the on-resistance. Therefore, not only the gate withstand voltage can be improved, but also the on-resistance can be reduced.

In addition, according to this configuration, the degree of freedom in selecting the material of the passivation layer26is improved. For example, a material that can more stably insulate the gate electrode24and the source electrode28even if the source electrode28is sintered is selected as the material constituting the source insulator film61. In this case, the material of the passivation layer26can be selected without considering the insulation between the gate electrode24and the source electrode28after the sintering process. Further, in one example, the source insulator film61is made of a material with higher insulating properties than the portion of the passivation layer26forming the passivation first side surface26C.

The passivation first side surface26C is located above the gate layer side surface22C. According to this configuration, the passivation first side surface26C and the gate layer side surface22C form one continuous side surface, that is, a side wall. Therefore, the source insulator film61can be easily formed by self-alignment with respect to the side wall. In this case, it is easy to shorten the first direction length L3of the source insulator film61. Therefore, the effect of significantly reducing the on-resistance will be obtained.

The passivation layer26includes a first passivation layer51formed on at least a region of the electron supply layer18closer to the drain electrode30than the gate layer22, and a second passivation layer52formed on the first passivation layer51.

According to this structure, other structures such as the field plate electrode53can be easily arranged between the first passivation layer51and the second passivation layer52. In addition, by making the materials constituting the first passivation layer51and the second passivation layer52different, the properties of the region formed by the first passivation layer51and the region formed by the second passivation layer52in the passivation layer26can be made different.

The second passivation layer52has a source side portion52A formed on a region of the gate layer22closer to the source electrode than the gate electrode24. The passivation first side surface26C is the side surface of the end portion of the source-side portion52A of the second passivation layer52located on the source electrode28side.

According to this configuration, by adjusting the thickness of the source side portion52A of the second passivation layer52, it is easy to form the side wall formed by the passivation first side surface26C and the gate layer side surface22C higher. When the source insulator film61is formed by self-alignment, since the side walls are formed higher, the source insulator film61can be formed with good accuracy with respect to the first direction length L3. Therefore, the effect of being able to reduce the on-resistance more significantly is obtained.

The source side portion52A of the second passivation layer52is thicker than the first passivation layer51. According to this configuration, the above-mentioned effect (1-4) will be obtained more significantly.

The gate electrode24includes an electrode side surface24A located at the end on the source electrode28side in the first direction. The first passivation layer51includes a first side surface51A located at the end on the source electrode28side in the first direction. The first side surface51A of the first passivation layer51is located on the electrode side surface24A of the gate electrode24. The source side portion52A of the second passivation layer52is in contact with the electrode side surface24A of the gate electrode24and the first side surface51A of the first passivation layer51.

The end portion of the junction portion between the gate electrode24and the gate layer22on the source electrode28side is a portion where large electric field concentration is likely to occur. According to the above configuration, the end portion of the junction portion on the source electrode28side where large electric field concentration is likely to occur is covered with the second passivation layer52. Therefore, by forming the second passivation layer52with a material suitable for alleviating electric field concentration, there is no need to consider alleviation of the electric field concentration at said portion when selecting the material constituting the first passivation layer51. Therefore, the degree of freedom in selecting the material of the first passivation layer51increases. Furthermore, in one example, the second passivation layer52is made of a material that has a higher property of suppressing electric field concentration and relaxation than the material constituting the first passivation layer51.

The first passivation layer51is a SiN layer, and the second passivation layer52is a SiO2layer. According to this configuration, by setting the first passivation layer51as a SiN layer, the surface protecting the electron supply layer18is obtained, thereby achieving the effect of reducing the trap energy level. By setting the second passivation layer52as a SiO2layer, it is easy to ensure the insulation between the gate electrode24and the source electrode28after the source electrode28is sintered.

The field plate electrode53is also included. The field plate electrode53is formed between the first passivation layer51and the second passivation layer52and electrically connected to the source electrode28. At least a portion of the field plate electrode53is formed between the gate layer22and the drain electrode30in the first direction.

According to this configuration, when a high voltage is applied to the drain electrode30, the field plate electrode53extends the depletion layer toward the 2DEG20directly below it, thereby achieving the effect of alleviating the electric field concentration in the drain-source region. As a result, the insulation damage to the electron supply layer18and the passivation layer26caused by local electric field concentration can be suppressed, and the drain-source withstand voltage can be improved.

The source electrode28includes a source field plate portion28B formed on the second passivation layer52. The end portion28C of the source field plate portion28B on the drain electrode30side is located closer to the drain electrode30than the field plate electrode53. According to this configuration, when a high voltage is applied to the drain electrode30, the source field plate portion28B extends the depletion layer toward the 2DEG20directly below it, thereby achieving the effect of alleviating the electric field concentration in the drain-source region. As a result, the insulation damage to of the electron supply layer18and the passivation layer26caused by local electric field concentration can be suppressed, and the drain-source withstand voltage can be improved.

The gate layer22includes a ridge portion42that is in contact with the electron supply layer18; and a source-side extension portion44that is in contact with the electron supply layer18and extends from the ridge portion42toward the source electrode28side in the first direction, and is thinner than the ridge portion42. The gate layer side surface22C of the gate layer22is the front end surface of the source-side extension portion44. In addition, the gate layer22includes a drain-side extension portion46that is in contact with the electron supply layer18and extends from the ridge portion42toward the drain electrode30side in the first direction, and is thinner than the ridge portion.

According to these configurations, the source-side extension portion44and the drain-side extension portion46allow the electric force lines concentrated at the lower end of the ridge portion42to escape to the respective extension portions44and46when the gate is forward biased, thereby making the potential within the gate layer22in the first direction become uniform. As a result, the electric field intensity acting on the end portion of the gate electrode24can be reduced, thereby suppressing the generation of gate leakage current when a high gate voltage is applied and improving the gate withstand voltage.

The first direction length L3of the source insulator film61is shorter than the first direction length L1of the source-side extension portion44. In addition, the first direction length of the source insulator film is less than 100 nm. According to these configurations, by making the first direction length L3of the source insulator film61shorter, the effect of significant reduction of on-resistance can be obtained.

The passivation layer26includes the passivation second side surface26D facing the drain electrode30in the first direction. The nitride semiconductor device10further includes a drain insulator film that covers the passivation second side surface26D and insulates the passivation second side surface26D from the drain electrode30.

According to this configuration, by interposition at where a relatively large electric field concentration occurs, i.e. between the end portion of the drain electrode30in the first direction and the passivation layer26, the injection of electrons from the drain electrode30into the passivation layer26can be suppressed. As a result, the long-term stability of the electrical characteristics (for example, drain-source withstand voltage) of the nitride semiconductor device10can be achieved.

Modified Examples

The above-described embodiments can be modified as follows, for example. The above-described embodiments and the following modifications can be combined with each other as long as no technical contradiction occurs. In addition, in the following modified examples, the same reference numerals as those in the above-described embodiments are assigned to the parts that are common to the above-described embodiments, and the relevant description is omitted.The shape of the gate layer22may also be changed. For example, one of the source-side extension portion44and the drain-side extension portion46may be omitted from the gate layer22. In addition, the gate layer22may have a shape in which the source-side extension portion44and the drain-side extension portion46are omitted. For example, the gate layer22may be formed only of the ridge portion42.In the above embodiments, the field plate electrode53may also be omitted. In this case, the passivation layer26may be composed of one layer.In the above embodiments, the source electrode28may omit the source field plate portion28B.In the above embodiments, the number of HEMTs formed in the working region is not particularly limited.

The expression “on” used in the disclosure includes both meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, the expression “component A is formed on component B” is intended to express that in one embodiment, component A may be directly disposed on component B and in contact with component B, while in another embodiment, component A may be arranged above component B without contacting component B. That is, the expression “on” does not exclude the structure in which other component is formed between component A and component B.

The Z direction used in the disclosure is not necessarily the vertically straight direction, nor does it need to be exactly the same as the vertically straight direction. Therefore, the various structures disclosed herein are not limited to the case where “upper” and “lower” in the Z direction described in this specification are “upper” and “lower” in the vertically straight direction. For example, the X direction may be a vertically straight direction, or the Y direction may be a vertically straight direction.

The words “first”, “second”, “third” and the like in the disclosure are only used to distinguish the objects, and are not intended to rank the objects.

A method for manufacturing a nitride semiconductor device (10), comprising the following steps:forming an electron travelling layer (16) made of a nitride semiconductor;forming an electron supply layer (18) on the electron travelling layer (16) and made of a nitride semiconductor having a band gap larger than a band gap of the electron travelling layer (16);forming a gate layer (22) on the electron supply layer (18) and made of a nitride semiconductor including acceptor-type impurities;forming a gate electrode (24) on the gate layer (22);forming a passivation layer (26) covering the electron supply layer (18), the gate layer (22), and the gate electrode (24) and having a first opening (24A) and a second opening (24B);forming a source electrode (28) contacting the electron supply layer (18) through the first opening (24A);forming a drain electrode (30) contacting the electron supply layer (18) through the second opening (24B); andforming a source insulator film (61) insulating the gate layer (22) from the source electrode (28); whereinthe passivation layer (26) is formed in such a manner that the gate layer side surface (22C) of the gate layer (22) located at the end portion on the first opening (24A) side is exposed from the first opening (24A),before forming the source electrode (28) and after forming the insulator layer (81) covering the upper surface and side surface of the passivation layer (26), the gate layer side surface (22C) of the gate layer (22), and the upper surface of the electron supply layer (18) exposed from the first opening (24A), the source insulator film (61) is formed by removing the portions of the insulator layer (81) formed on the upper surface of the passivation layer (26) and the upper surface of the electron supply layer (18).