Hybrid hysteretic control system

A system comprises a first comparator, a second comparator, a pulse-width modulation (PWM) controller, and a ramp generator. The first comparator has a positive input coupled to a first ramp output of the ramp generator and a negative input configured to receive an input voltage. The second comparator has a positive input configured to receive the input voltage and a negative input coupled to a second ramp output of the ramp generator. The PWM controller is coupled to outputs and control signal inputs of the first and second comparators and has a control output. In some implementations, the ramp generator generates a high-side falling ramp for the first comparator and a low-side rising ramp for the second comparator. In some implementations, the ramp generator includes a first ramp generator for the high-side falling ramp and a second ramp for the low-side rising ramp.

BACKGROUND

Hybrid hysteretic control (HHC) systems are used to improve the transient response of power supply units by simplifying the compensation into a first order system. Two-sided HHC provides faster transient response times than one-sided HHC, but is implemented with an external comparator and ramp generator, increasing the area occupied by the HHC system on the integrated circuit including the HHC system and the power converter. In addition, unavoidable differences between the two feedback signal chains can introduce imbalance and asymmetry in the resulting pulse width modulation control signals.

SUMMARY

A system comprises a first comparator, a second comparator, a pulse-width modulation (PWM) controller, and a ramp generator. The first comparator has a positive input coupled to a first ramp output of the ramp generator and a negative input configured to receive an input voltage. The second comparator has a positive input configured to receive the input voltage and a negative input coupled to a second ramp output of the ramp generator. The PWM controller is coupled to outputs and control signal inputs of the first and second comparators and has a control output.

In some implementations, the ramp generator generates a first ramp for the first comparator and a second ramp for the second comparator. The first ramp can be a high-side falling ramp, and the second ramp can be a low-side rising ramp. In some implementations, the ramp generator includes a first ramp generator for the high-side falling ramp and a second ramp for the low-side rising ramp. The first and second ramps are offset by half a period T.

In some implementations, a voltage sensing circuit provides the input voltage. The input voltage is a first input voltage in some implementations, and the control output of the PWM comprises a first control output and a second control output. The system also includes a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, an inductor, and a transformer. The first transistor has a first control terminal coupled to the first control output and first and second current terminals. The second transistor has a second control terminal coupled to the second control output and third and fourth current terminals. The third current terminal is coupled to the second current terminal, and the first and fourth current terminals receive a second input voltage.

The capacitor has a first capacitor terminal coupled to the fourth current terminal and a second capacitor terminal. The voltage sensing circuit measures the first input voltage across the capacitor. The inductor has a first inductor terminal coupled to the second and third current terminals and a second inductor terminal. The transformer has a first input coupled to the second inductor terminal and a second input coupled to the second capacitor terminal. The transformer also has three transformer outputs.

The third transistor has a third control terminal configured to receive a biasing voltage, a fifth current terminal coupled to the first transformer output, and a sixth current terminal. The fourth transistor has a fourth control terminal configured to receive the biasing voltage, a seventh current terminal coupled to the second transformer output, and an eighth current terminal coupled to the sixth current terminal. In some implementations, the transformer is a center-tap transformer.

The same reference number is used in the drawings for the same or similar (either by function and/or structure) features.

DETAILED DESCRIPTION

The described digital two-sided hybrid hysteretic control (HHC) systems include two comparators, two ramp generators, and a pulse-width modulation (PWM) controller. Each comparator has a positive input, a negative input, a control input, and an output. In the first comparator, the positive input receives a high-side falling ramp from a ramp generator, and the negative input receives a voltage across a resonant capacitor in a power converter. The control input receives a first feedback signal from the PWM controller. In the second comparator, the positive input receives the voltage across the resonant capacitor, and the negative input receives a low-side rising ramp from the other ramp generator. The control input receives a second feedback signal from the PWM controller, which generates first and second control signals for the power converter based on the outputs of the first and second comparators. The digital two-sided HHC systems are integrated into a single semiconductor die and use both rising and falling ramps, instead of a falling ramp only.

FIG.1Ashows a block diagram of an example LLC converter100and corresponding one-sided hybrid hysteretic control (HHC) system150. The LLC converter100includes transistors MA, MB, MC, and MD; resonant capacitor C115, inductor L120, transformer130, voltage sensing circuit125, and the one-sided HHC system150. The voltage sensing circuit125is configured to measure the voltage across the resonant capacitor C115. In some implementations, the transformer130is a center-tap transformer. The one-sided HHC system150includes a comparator160, a pulse-width modulation (PWM) controller170, an analog-to-digital converter (ADC)174, an adder180, and a ramp generator185.

The transistors MA, MB, MC, and MD may be metal oxide semiconductor field-effect transistors (MOSFETs). Accordingly, MA-MD are n-type MOSFETs (NMOS) in an example. In other examples, one or more of MA-MD are p-type MOSFETs (PMOS) or bipolar junction transistors (BJTs). A BJT includes a base corresponding to the gate terminal of a MOSFET, and a collector and an emitter corresponding to the drain and source terminals of a MOSFET. The base of a BJT and the gate terminal of a MOSFET are also called control inputs. The collector and emitter of a BJT and the drain and source terminals of a MOSFET are also called current terminals.

The source terminal of MA and the drain terminal of MB are coupled together, and the input voltage Vin105is applied across the drain terminal of MA and the source terminal of MB. The gate terminal of MA is configured to receive the first control signal CTLA110A, and the gate terminal of MB is configured to receive the second control signal CTLB110B. The inductor L120has a first terminal coupled to the source terminal of MA and the drain terminal of MB and a second terminal coupled to the transformer130. The resonant capacitor C115has a first terminal coupled to the source terminal of MB and a second terminal coupled to the transformer130. The voltage sensing circuit125is coupled to the second terminal of the resonant capacitor C115and measures the voltage VCR155across the resonant capacitor C115.

The transformer130includes a primary winding134and a secondary winding138. The second terminal of the inductor L120is coupled to a first terminal of the primary winding134, and the second terminal of the resonant capacitor C115is coupled to a second terminal of the primary winding134. A first terminal of the secondary winding138is coupled to the drain terminal of MD, and a second terminal of the secondary winding138is coupled to the drain terminal of MC. The source terminals of MC and MD are coupled together, and the gate terminals of MC and MD are configured to receive a biasing voltage Vbias140. The output voltage Vout145is taken across the center tap of transformer130and the source terminals of MC and MD.

In the one-sided HHC system150, the comparator160has a first input configured to receive the voltage VCR155across the resonant capacitor C115from the voltage sensing circuit125, and a second input coupled to an output of the ramp generator185to receive the ramp190. The comparator160is also configured to receive a feedback signal FDBK168from the PWM controller170, which resets a digital-to-analog converter (DAC) of the comparator160to support HHC. The output164of comparator160is provided to the PWM controller170, which outputs the control signals CTLA110A and CTLB110B for transistors MA and MB, respectively, as well as the feedback signal FDBK168for the comparator160. The ADC174receives the output voltage Vout145, and adder180subtracts the output of the ADC174from a reference signal Vref178, which represents the target output voltage. A voltage controller183receives the difference between the target output voltage represented by Vref178and the digitized output voltage from ADC174, and generates a control signal for the ramp generator185. The ramp generator185receives the control signal from the voltage controller183and generates the ramp signal190. In some implementations, the control signal from the voltage controller183indicates the initial value of the ramp signal190.

FIG.1Bshows waveforms of signals generated in the one-sided HHC system150shown inFIG.1A. At time t0, the control signal CTLA110A transitions from logic low to logic high, and the control signal CTLB110B transitions from logic high to logic low. The VCR155intersects with the ramp signal190at time t1, triggering the control signal CTLB110B to transition from logic low to logic high. CTLB110B is logic high and CTLA110A is logic low from time t1to time t2, at which CTLB110B transitions to logic low and CTLA110A transitions to logic high. The length of time between time t0and t1while CTLA110A is logic high is measured, and the time t2is chosen such that the length of time between t1and t2while CTLB110B is logic low is kept equal to the length of time between t0and t1. At time t3, the VCR155intersects with the ramp190, and the control signal CTLB110B transitions from logic low to logic high. The time between t1and t3is a period T195. However, one-sided HHC can have slower transient response times than two-sided HHC, shown inFIG.2A.

FIG.2Ashows a block diagram of an example analog two-sided HHC system250that may be used in place of one-sided HHC system150in the LLC converter100shown inFIG.1A. For ease of explanation, the analog two-sided HHC system250is described herein with respect to the LLC converter shown inFIG.1A, and includes an inverter210, two comparators260A-B, a pulse-width modulation (PWM) controller270, an ADC274, an adder280, and a ramp generator285. The comparator260A has a positive input that receives a first ramp290A from the ramp generator285and a negative input that receives the voltage VCR155across the resonant capacitor C115. The comparator260A also receives a feedback signal FDBK268A from the PWM controller270and generates an output signal TRIPA264A, which is provided to the PWM controller270.

The inverter210receives the voltage VCR155and outputs the inverse,VCR255to a negative input of comparator260B. The positive input of comparator260B receives a second ramp290B from the ramp generator285. The comparator260B also receives a feedback signal FDBK268B from the PWM controller270and generates an output signal TRIPB264B, which is provided to the PWM controller270. The PWM controller270generates the feedback signals FDBK268A and268B for comparator260A and260B, respectively, to reset the DACs in comparators260A and260B. The PWM controller270outputs the control signals CTLA110A and CTLB110B for transistors MA and MB, respectively, in the LLC converter100shown inFIG.1A.

The ADC274receives the output voltage Vout145, and adder280subtracts the output of the ADC274from a reference signal Vref278, which represents the target output voltage. A voltage controller283receives the difference between the target output voltage represented by Vref278and the digitized output voltage from ADC274and generates a control signal for ramp generator285. The ramp generator285receives the control signal from the voltage controller283and generates the ramps290A and290B for the comparators260A and260B, respectively. In some implementations, the control signal from the voltage controller283indicates the initial values for ramps290A and290B.FIG.2Bshows waveforms of signals generated in the two-sided HHC system250shown inFIG.2A, including the ramp290A relative to VCR155, the ramp290B relative toVCR255, and the control signals CTLA110A and CTLB110B.

Ramp290B is offset from ramp290A by half a period T295of the ramp290B, and at time t1,VCR255intersects with ramp290B, causing CTLB110B to transition from logic high to logic low and CTLA110A to transition from logic low to logic high. At time t2, VCR155intersects with ramp290A, causing CTLA110A to transition from logic high to logic low and CTLB110B to transition from logic low to logic high. At t3,VCR255intersects with ramp290B, causing CTLB110B to transition from logic high to logic low and CTLA110A to transition from logic low to logic high.

At time t4, VCR155intersects with ramp290A, causing CTLA110A to transition from logic high to logic low and CTLB110B to transition from logic low to logic high. The analog two-sided HHC system250offers faster transient response times than one-sided HHC system150but utilizes an analog inverter210to generate the second feedback signalVCR255, which can introduce error or delays into the resulting output signal TRIPB264B from comparator260B. In addition, the ramp generator285is external to the integrated circuit including the comparators260A and260B and PWM controller270, occupying additional area.

FIG.3Ashows a block diagram of an example digital two-sided HHC system350that may be used in place of one-sided HHC system150in the LLC converter100shown inFIG.1A. For ease of explanation, the digital two-sided HHC system350is described herein with respect to the LLC converter100shown inFIG.1A, and includes two comparators360A-B, a PWM controller370, an ADC374, an adder380, a voltage controller383, and a ramp generator385. The comparator360A has a positive input that receives a high-side falling ramp RAMP_H390A from the ramp generator385and a negative input that receives the voltage VCR155across the resonant capacitor C115. The comparator360A also receives a feedback signal FDBK368A from the PWM controller370and generates an output signal TRIP_H364A, which is provided to the PWM controller370.

The comparator360B has a positive input that receives the voltage VCR155across the resonant capacitor C115and a negative input that receives a low-side rising ramp RAMP_L390B from the ramp generator385. The comparator360B also receives a feedback signal FDBK368B from the PWM controller370and generates an output signal TRIP_L364B, which is provided to the PWM controller370. The PWM controller370generates the feedback signals FDBK368A and368B for comparator360A and360B, respectively. The PWM controller370outputs the control signals CTLA110A and CTLB110B for transistors MA and MB, respectively, in the LLC converter100shown inFIG.1A.

The ADC374receives the output voltage Vout145, and adder380subtracts the output of the ADC374from a reference voltage Vref378, which represents the target output voltage. A voltage controller383receives the difference between the target output voltage represented by Vref378and the digitized output voltage from ADC374, and generates a control signal for the ramp generator385. The ramp generator385receives control signal from the voltage controller383and generates the high-side falling ramp RAMP_H390A and the low-side rising ramp RAMP_L390B for the comparators360A and360B, respectively. In some implementations, the control signal from the voltage controller383indicates the initial values of the ramp signals RAMP_H390A and RAMP_L390B. The ramp generator385uses preset slopes for each of RAMP_H390A and RAMP_L390B, and the feedback signals FDBK368A and368B reset the comparator DACs in comparator360A and360B to cut off the ramps RAMP_H390A and RAMP_L390B.

FIG.3Bshows waveforms of signals generated in the digital two-sided HHC system350shown inFIG.3A, including the high-side ramp RAMP_H390A and the low-side ramp RAMP_L390B relative to VCR155, and the control signals CTLA110A and CTLB110B. The low-side ramp RAMP_L390B is offset from the high-side ramp RAMP_H390A by half a period T395of the ramps390A and390B, and at time t1, VCR155intersects with low-side ramp RAMP_L390B, causing CTLB110B to transition from logic high to logic low and CTLA110A to transition from logic low to logic high. At time t2, VCR155intersects with high-side ramp RAMP_H390A, causing CTLA110A to transition from logic high to logic low, and CTLB110B to transition from logic low to logic high. At time t3, VCR155intersects with low-side ramp RAMP_L390B, causing CTLB110B to transition from logic high to logic low and CTLA110A to transition from logic low to logic high. At time t4, VCR155intersects with high-side ramp RAMP_H390A, causing CTLA110A to transition from logic high to logic low, and CTLB110B to transition from logic low to logic high.

The digital two-sided HHC system350offers the faster transient response times of a two-sided HHC system relative to one-sided HHC systems and also offers reduced PWM asymmetry compared to the analog two-sided HHC system250shown inFIG.2Aby triggering transitions in CTLA110A and CTLB110B based on both the high side and the low side of VCR155. In addition, the ramp generator385is included in the integrated circuit with the comparators360A-B, PWM controller370, and the remaining components of digital two-sided HHC system350.

The digital two-sided HHC system350shown inFIG.3Acan be used to support advanced topologies such as peak boost converters, peak buck converters, valley boost converters, valley buck converters, and the like. To illustrate,FIG.4Ashows a block diagram of an example peak current-mode control (PCMC) DC-DC converter400that can be controlled by the digital two-sided HHC system shown inFIG.3A. The PCMC DC-DC converter400includes transistors MA and MB, capacitors C415and C430, and inductor L420. The transistors MA and MB are NMOS in this example. In other examples, one or more of MA and MB are PMOS or BJTs.

The capacitor C415has a first terminal coupled to a first terminal of the inductor L420, and a second terminal. The input voltage Vin405is applied to the first and second terminals of the capacitor C415and the first terminal of the inductor L420. The second terminal of the inductor L420is coupled to the drain terminal of MA and the source terminal of MB. A current iL425flows through the inductor L420. The source terminal of MA is coupled to the second terminal of the capacitor C415, and the gate terminal of MA is configured to receive the first control signal CTLA410A. The drain terminal of MB is coupled to a first terminal of the capacitor C430, and the gate terminal of MB is configured to receive the second control signal CTLB410B. The capacitor C430has a second terminal coupled to the source terminal of MA and the second terminal of the capacitor C415. The output voltage Vout445is taken across the capacitor C430.

The digital two-sided HHC system350shown inFIG.3Acan be used to provide the control signals CTLA410A and CTLB410B.FIG.4Bshows waveforms of the current iL425through the inductor L420shown in the PCMC DC-DC converter400shown inFIG.4Aand the high side falling ramp RAMP_H490A and the low side rising ramp RAMP_L490B generated in the digital two-sided HHC system used to generate the control signals CTLA410A and CTLB410B.

At time t1, the current iL425intersects with the high side falling ramp RAMP_H490A, and the control system generates the control signals CTLA410A and CTLB410B such that iL425decreases. At time t2, iL425increases again, and at time t3, iL425intersects the high side falling ramp RAMP_H490A, and the control system generates the control signals CTLA410A and CTLB410B such that iL425decreases. At time t4, the current iL425intersects with the low side rising ramp RAMP_L490B, and the control system generates the control signals CTLA410A and CTLB410B such that the current iL425increases. At time t5, the current iL425decreases again, and at time t6, iL425intersects with the low side rising ramp RAMP_L490B, and the control system generates the control signals CTLA410A and CTLB410B such that the current iL425increases.

FIG.4Cshows a graph of the average current lo450over duty cycle D for the PCMC DC-DC converter400shown inFIG.4A. During a first time period Tcharge455, the capacitors C415and430are charged, and at the duty cycle Do465, the average current lo450changes directions and the capacitors C415and430begin to discharge for a time period Tdischarge460. The duty cycle Do465may be represented as:

While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-type metal-oxide-silicon field effect transistor (“MOSFET”) may be used in place of an n-type MOSFET with little or no changes to the circuit. Furthermore, other types of transistors may be used (such as bipolar junction transistors (BJTs)).

Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means+/−10 percent of the stated value. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.