Standard cell having compensation capacitance

A standard cell includes a capacity element which is made up of a first well diffusion layer into which a first conductive impurity is diffused in a region from a surface of a substrate to a predetermined depth, an insulation film which is provided on the first well diffusion layer, and a first dummy pattern which is provided on the insulation film.

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2008-103572 filed on Apr. 11, 2008 and Japanese Patent Application No. 2009-4492 filed on Jan. 13, 2009, the content of which is incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a standard cell and a semiconductor device.

2. Description of Related Art

An example of a standard cell used for semiconductor devices will be described.FIG. 1is a plan perspective view to show a configuration example of a related standard cell. The standard cell shown inFIG. 1is an inverter circuit, some wirings of which are omitted from the figure.

As shown inFIG. 1, the standard cell has a rectangular outer shape. The standard cell shown inFIG. 1includes the following two regions. One is a Pch-Tr element region where a P channel Metal Oxide Semiconductor (MOS) transistor element (hereafter indicated by a Pch-Tr element) is formed. The other is an Nch-Tr element region where an N channel MOS transistor element (hereafter, indicated by an Nch-Tr element) is formed.

There are two Pch-Tr elements21and22provided in a region of N-well diffusion layer10to be turned into a Pch-Tr element region. There are also two Nch-Tr elements31and32provided in the Nch-Tr element region.

FIG. 2Ais a plan view of an active pattern of the standard cell shown inFIG. 1;FIG. 2Bis a plan view of a gate pattern of the standard cell shown inFIG. 1; andFIG. 2Cis a plan view of a wiring pattern of the standard cell shown inFIG. 1.

It is noted that inFIGS. 2A and 2C, the active pattern and the wiring are drawn by combining rectangular patterns as in the layout design, as a result of which, dividing lines are drawn in a pattern. Since the drawing on a mask used in the lithography process is performed without providing these dividing lines, the diving lines will not appear in the semiconductor device to be formed.

Active pattern41shown inFIG. 2Aprovides a generation region for source electrodes, drain electrodes, and channels of Pch-Tr elements21and22. Active pattern42is provided along each side of the two long-sides and one of the short-sides of a rectangle, and in the inner edge thereof. Active pattern42provides an opening for applying a predetermined electric potential to N-well diffusion layer10.

Active pattern43provides a generation region for source electrodes, drain electrodes, and channels of Nch-Tr elements31and32. Active pattern44is provided along each side of the two long-sides and one of the short-sides of a rectangle, and in the inner edge thereof. Active pattern44provides an opening for applying an electric potential that is lower than that to N-well diffusion layer10, to a P-well diffusion layer.

As shown inFIG. 2B, there are two kinds of dummy patterns provided in the gate pattern, besides gate electrodes of transistor elements. The first kind is a dummy pattern for the purpose of uniformly forming a pattern of gate electrodes at the time of gate-etching. Dummy patterns25a,25b,27a, and27bcorrespond to the pattern of this kind. By making the pattern of the gate electrode uniform, the gate length is made uniform, thereby suppressing variation in transistor characteristics.

As shown inFIG. 2B, each of dummy patterns25aand25bhas an equal length to that of respective gate electrodes211and221, and dummy patterns25aand25bare provided in parallel beside gate electrodes211and221respectively. Each of dummy patterns27aand27bhas an equal length to that of respective gate electrodes311and321, and dummy patterns27aand27bare provided in parallel beside gate electrodes311and321respectively. These dummy patterns25a,25b,27a, and27bare kept at a floating potential or fixed to a predetermined electric potential by being connected to the wiring. In this case, the electric potential of dummy patterns25a,25b,27a, and27bare kept at a floating state.

The second kind is a dummy pattern for the purpose of improving the planarization of an inter-layer insulation film to be formed on a gate pattern. Dummy patterns26and28correspond to the pattern of this kind. When an inter-layer insulation film formed on a gate pattern is planarized by CMP (Chemical and Mechanical Polishing) processing, a data rate, which is the proportion of the area occupied by the pattern in the gate-electrode forming layer, is preferably uniform in anywhere of the gate-electrode forming layer. Accordingly, it is necessary to increase the data rate of portions having a lower pattern density compared with the vicinity of a gate-electrode forming region, where the pattern density per unit area is relatively large. Specifically, the sizes of dummy patterns26and28are determined such that the pattern densities are within a predetermined range and dummy patterns26and28are provided as shown inFIGS. 1 and 2B.

Dummy patterns26,28are kept at a floating potential or are fixed to a predetermined electric potential by being connected with the wiring. In this case, the electric potential of dummy pattern26,28is fixed to a predetermined electric potential.

As shown inFIG. 2C, the wiring pattern includes wirings51,52, and53. Although wiring51appears to be made up of a plurality of patterns, it is in reality made up of one pattern as described above. The same is also true with wiring53.

Wiring51is connected with each of drain electrodes212and222and source electrode215of the Pch-Tr element, and active pattern42via well contact61as shown inFIGS. 1,2A and2C. Well contact61is a plug provided so as to pass through an inter-layer insulation film (not shown) and a gate oxide film (not shown) which are formed between the active pattern and the wiring pattern. Due to well contact61, N-well diffusion layer10and drain electrodes212and222will have the same electric potential.

Wiring53is connected with each of source electrodes312and322and drain electrode315of the Nch-Tr element, and active pattern43via sub-contact63as shown inFIGS. 1,2A and2C. Sub-contact63is provided so as to pass through an inter-layer insulation film (not shown) and a gate oxide film (not shown) which are formed between the active pattern and the wiring pattern. Due to sub-contact63, the P-well diffusion layer (not shown) and source electrode312and322will have the same electric potential.

It is noted that when the substrate on which the standard cell shown inFIG. 1is formed is a P-type substrate, the P-well diffusion layer (not shown) and the substrate will have the same electric potential. Therefore, the contact plug which connects a P-well diffusion layer with a wiring pattern is referred to as sub-contact63.

Contact62is a plug provided so as to pass through an inter-layer insulation film (not shown) formed between dummy pattern26and wiring51as shown inFIGS. 1,2B, and2C. Dummy pattern26will have the same electric potential as that of N-well diffusion layer10. Moreover, contact64is a plug provided so as to pass through an inter-layer insulation film (not shown) formed between dummy pattern28and wiring53. Dummy pattern28will have the same electric potential as that of the P-well diffusion layer (not shown).

As shown inFIGS. 1,2A, and2C, wiring52connects source electrode215of the Pch-Tr element with drain electrode315of the Nch-Tr element via well contact61and sub-contact63.

Well contact61, contacts62and64, and sub-contact63are formed in the same process. The material for well contact61, contacts62and64, and sub-contact63is metal such as tungsten and copper, or a conductive material such as polysilicon doped with a conductive impurity.

Next, a standard cell including a resistance element will be described.

A DRAM (Dynamic Random Access Memory) is provided with a reference circuit for generating various reference voltages by resistive potential division. A reference circuit often utilizes resistance elements which are formed by diffusing a conductive impurity into a site from the surface to a predetermined depth of a substrate or well.

The configuration of a standard cell including a resistance element formed of a diffusion layer will be described. In this case, it is supposed that a MOS transistor is formed on the substrate as well.

FIG. 3Ais a plan perspective view to show a configuration example of a standard cell including a resistance element; andFIG. 3Bshows an equivalent circuit of the standard cell shown inFIG. 3A.FIG. 4is a sectional view taken along line AB shown inFIG. 3A.

As shown inFIG. 4, a P-well diffusion layer is provided in each element-forming region of a resistance element and a MOS transistor, from the surface of P-type conductive substrate (simply referred to as “P-substrate”)700to a predetermined depth, and gate oxide film710is provided as an insulation film on the surface of P-substrate700.

As shown inFIGS. 3A and 4, resistance element500is formed of a diffusion layer of an N-type conductive impurity and is formed in a region from the surface of P-well diffusion layer600to a predetermined depth. N-well diffusion layer602is formed in the surrounding of P-well diffusion layer600, and the side face of P-well diffusion layer600is covered with N-well diffusion layer602.FIG. 3Ashows outer edge622aand inner edge622bof the pattern of N-well diffusion layer602. Further, as shown inFIG. 4, deep N-well diffusion layer604is formed underneath P-well diffusion layer600, and the bottom face of P-well diffusion layer600is covered with deep N-well diffusion layer604.

Trench oxide film551is formed in the area that surrounds resistance element500, and the side face of resistance element500is covered with trench oxide film551. Dummy pattern502is provided above trench oxide film551in such a way as to surround the forming region of resistance element500along the planer pattern of trench oxide film551. This dummy pattern502corresponds to the second of the two kinds of dummy patterns described above and is for the purpose of planarization by CMP processing. Dummy pattern502and the gate electrode (not shown) of the MOS transistor are in the same layer.

The reason why dummy pattern502is provided in the area that surrounds resistance element500is for the purpose of preventing the insulation film formed above the gate electrode from being ground faster than other sites thereby from being removed from the surface when it is ground by CMP processing. Dummy pattern504described later also has the same role as that of dummy pattern502. The material of dummy patterns502and504is the same as that of the gate electrode (not shown), and in this case, they are made of a polysilicon layer into which a conductive impurity is diffused. Further, hereafter, the polysilicon layer into which a conductive impurity is diffused is simply referred to as a “polysilicon layer”.

Sub-contact diffusion layer512into which a P-type conductive impurity is diffused is formed outside trench oxide film551. Since sub-contact diffusion layer512has a higher concentration of conductive impurities than that in P-well diffusion layer600, it is indicated by “P+” inFIG. 4. The reason why sub-contact diffusion layer512has a higher concentration of conductive impurities is to decrease the contact resistance between the plug provided in the overlying layer and P-well diffusion layer600. A diffusion layer for making contact with P-well diffusion layer600, which has the same kind of conductive impurities as that of P-substrate700, is referred to as a sub-contact diffusion layer.

On sub-contact diffusion layer512, there is formed gate oxide film710which has a smaller film thickness than that of the trench oxide film formed next to each side of sub-contact diffusion layer512. Because providing an opening through gate oxide film710will enable making contact with P-well diffusion layer600via sub-contact diffusion layer512, the forming site of sub-contact diffusion layer512corresponds to the opening pattern of the present invention.

Trench oxide film553is formed in the area that surrounds sub-contact diffusion layer512, and the side face of sub-contact diffusion layer512is covered with trench oxide film553. Dummy pattern504is provided above trench oxide film553along the planar pattern of trench oxide film553. Since the bottom face of trench oxide film553is at halfway point with respect to the depth of N-well diffusion layer602, the side face of P-well diffusion layer600is covered with trench oxide film553and N-well diffusion layer602.

Well-contact diffusion layer514into which an N-type conductive impurity is diffused is formed in the area that surrounds trench oxide film553. Since well-contact diffusion layer514has a higher concentration of the conductive impurity than that of N-well diffusion layer602, it is indicated by “N+” inFIG. 4. The reason why well-contact diffusion layer514has a higher concentration of the conductive impurities is to decrease contact resistance between the plug provided in the overlying layer and N-well diffusion layer602. A diffusion layer for making contact with N-well diffusion layer602is referred to as a well-contact diffusion layer.

On well-contact diffusion layer514, there is formed gate oxide film710, which has a smaller film thickness than that of the trench oxide film formed next to each side of well-contact diffusion layer514. Because providing an opening through gate oxide film710will enable making contact with N-well diffusion layer602via well-contact diffusion layer514, the forming site of well-contact diffusion layer514corresponds to the opening pattern of the present invention.

Compared to resistance element500and well-contact diffusion layer514concerning the concentration of N-type conductive impurities, the concentration of N-type conductive impurities of resistance element500is lower than that of well-contact diffusion layer514. Therefore, resistance element500is indicated by “N−” and well-contact diffusion layer514is indicated by “N+” inFIG. 4.

As shown inFIG. 3A, one of the two ends of resistance element500of a rectangular pattern is connected with tungsten wiring533via a contact, and the other end is connected with tungsten wiring537via a contact. Further, tungsten wiring537is connected with sub-contact diffusion layer512via sub-contact522. Each of tungsten wiring531and tungsten wiring535is connected with well-contact diffusion layer514via well contact524. Sub-contact522is a plug for connecting the wiring with sub-contact diffusion layer512, and well contact524is a plug for connecting the wiring with well-contact diffusion layer514.

The planar pattern of tungsten wiring533is rectangular. The planar pattern of tungsten wiring537has a shape in which a rectangular pattern and the planar pattern of sub-contact diffusion layer512are superposed with each other. However, in order to arrange that tungsten wiring533and tungsten wiring537in the same layer do not come into contact with each other, a part of the wiring pattern corresponding to the planar pattern of sub-contact diffusion layer512is removed as shown inFIG. 3A.

Tungsten wiring531and tungsten wiring535, as shown inFIG. 3A, have a shape in which a portion which intersects with each of tungsten wiring537and tungsten wiring533is removed from the wiring pattern corresponding to the planar pattern of well-contact diffusion layer514.

As shown inFIG. 4, insulation film712and insulation film714are stacked one after another on gate oxide film710. Dummy pattern502and dummy pattern504are provided within insulation film712and on gate oxide film710. Sub-contact522passes through gate oxide film710and insulation film712to reach sub-contact diffusion layer512. Well contact524passes through gate oxide film710and insulation film712to reach well-contact diffusion layer514. Tungsten wirings531,533,535, and537, which are in the same layer, are provided within insulation film714and on insulation film712.

In order to make resistance element500insusceptible to noises from the substrate, deep N-well diffusion layer604is interposed between P-well diffusion layer600, in which resistance element500is formed, and a P-well diffusion layer (not shown), in which another element (such as a transistor element in the vicinity) is formed, to separate respective P-well diffusion layers of resistance element500and another element. In this way, resistance element500is disposed on P-well diffusion layer600dedicated for its own element.

For the above described purpose, deep N-well diffusion layer604needs to be kept at a high-voltage potential so as to be reversely biased in the P-N direction with respect to P-well diffusion layer600without fail. N-well diffusion layer602is provided in order to supply a high-voltage potential to deep N-well diffusion layer604, and well-contact diffusion layer514is provided to supply a high-voltage potential to N-well diffusion layer602. A high-voltage is, for example, a power supply voltage (VDD). Hereafter, description will be made of the cases in which a VDD potential is applied.FIGS. 3A and 3Bshow wirings to which a VDD potential is applied. A VDD potential is applied to each of tungsten wirings531,533, and535.

As so far described with reference toFIGS. 3A and 4, resistance element500is disposed in the center of the forming region of resistance element500; sub-contact diffusion layer512for supplying an electric potential to P-well diffusion layer600is disposed around resistance element500; and well-contact diffusion layer514for supplying an electric potential to N-well diffusion layer602and deep N-well diffusion layer604is disposed around sub-contact diffusion layer512. Further, dummy pattern502is disposed between resistance element500and sub-contact diffusion layer512; and dummy pattern504is disposed between sub-contact diffusion layer512and well-contact diffusion layer514.

If a pattern made up of a polysilicon layer, such as dummy patterns502and504, is not disposed in the area that surrounds resistance element500at all, the forming region of resistance element500will have an extremely low data rate of polysilicon layer compared with the region where a pattern of polysilicon layer is disposed. This will adversely affect the planarization by CMP processing. In order to avoid occurrence of the problem, dummy patterns502and504are disposed in the area that surrounds resistance element500so that the data rate of polysilicon layer in the forming region of resistance element500becomes closer to that in the forming region of a MOS transistor. Dummy patterns502and504are kept at a floating or VDD potential.

In recent years, as the degree of integration of semiconductor devices has increased, memory LSIs have larger storage capacity and system LSIs have more functions implemented, as a result of which the size of semiconductor devices has become larger. Moreover, improvements in signal processing speed have resulted in semiconductor devices having increased speeds. For semiconductor devices whose sizes steadily increase and which have higher speeds, the noise of power supply lines has become a problem. As a countermeasure, Japanese Patent Laid-Open No. 2006-253393 (hereinafter referred to as “Patent Document 1”) discloses an example of the method of suppressing the fluctuation of power supply voltage by providing a compensation capacity between power supplies having different electric potentials.

As a result of advances integration scale and processing speed, semiconductor devices utilize not only power supply voltages supplied from the outside, but also various internal power supply voltages which are produced by decreasing or increasing the power supply voltage supplied from the outside by means of an internal circuit. For that reason, a compensation capacity becomes necessary for each of those internal power supplies besides power supply voltages supplied from the outside. Although the compensation capacity is preferably provided in the free space of the chip, the necessary quantity of the compensation capacity may become very large, and the amount of free space in the chip may not be enough to provide the compensation capacity.

The above described reference circuit will be described by way of example. Since the reference circuit is made up of analog circuits, it is characteristically susceptible to noise. Taking into consideration the following two points: that the power supply voltage supplied to the reference circuit will be the original voltage to create a reference voltage in a chip; and that the reference circuit is susceptible to noise, it is particularly important that the reference circuit be disposed with a compensation capacity to control the power supply noise, and thus it becomes necessary to secure layout space for that.

Securing space for disposing compensation capacity in a chip will result in an increase in chip size. When compensation capacity is provided in the free space of a chip within a permissible range without increasing the chip size, countermeasure against the noise of the power supply lines may be insufficient and thus the noise may adversely affect circuit characteristics.

A decision must be made whether to give a higher priority to compensation capacity and to provide the necessary quantity of compensation capacity in a chip by increasing the chip size, or to give a higher priority to chip size and to provide a quantity of compensation capacity which can be disposed in the free space of the chip, but taking the risk that there will be an occurrence of noise from the power supply; however, solving one problem will result in a manifestation of the other problem.

Patent Document 1 discloses a technology of providing a compensation capacity in a circuit cell as a countermeasure against the problem that sufficient layout space for compensation capacity cannot be obtained. However, in the technology disclosed in the foregoing patent, it is considered to select the most important configuration from among a gate dummy pattern for compensation capacity, a well contact, and a sub-contact, depending on the purpose of the circuit cell, and the configuration selected is disposed in the circuit cell. Therefore, the object is not to dispose a gate dummy pattern for compensation capacity, a well contact, and a sub-contact all in a single cell.

SUMMARY

In one embodiment, there is provided a standard cell that includes a capacity element which is made up of a first well diffusion layer into which a first conductive impurity is diffused in a region from a surface of a substrate to a predetermined depth, an insulation film provided on the first well diffusion layer, and a first dummy pattern provided on the insulation film.

In one embodiment, there is provided a semiconductor device that includes a plurality of the above described standard cells, wherein a plurality of the standard cells are disposed such that first capacity elements of adjacent standard cells are overlapped.

In the present invention, with a dummy pattern as an electrode; a first well diffusion layer as another electrode; and an insulation film therebetween as a dielectric, a capacitor is configured in which a dielectric is interposed between the two electrodes. The capacitor which utilizes a dummy pattern provided in the standard cell enables obtaining compensation capacity for controlling noise.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

First Embodiment

The configuration of a standard cell of the semiconductor device of the present embodiment will be described. The standard cell of the present embodiment is configured to include a MOS transistor.

FIG. 5is a plan perspective view to show a configuration example of the standard cell of the present embodiment. The standard cell shown inFIG. 5is an inverter circuit, in which some of the wirings are omitted from the figure.

FIG. 6Ais a plan view to show the pattern of gates of the standard cell shown inFIG. 5, andFIG. 6Bis a plan view to show the pattern of wirings of the standard cell shown inFIG. 5. Since the active patterns are the same as inFIG. 2A, description thereof will be omitted. Configurations similar to those shown inFIG. 1are given the same symbols and detailed description thereof will be omitted.

It is noted that dummy patterns ofFIG. 6Aare drawn by combining rectangular patterns as in the case of a layout design. Therefore, dividing lines are drawn in a pattern. Since drawing on a mask used in the lithography process is performed without providing these dividing lines, they will not appear in the semiconductor device to be formed. This is also true with the wiring pattern shown inFIG. 6B.

As shown inFIG. 5, the standard cell of the present embodiment has a rectangular outer shape. In the standard cell of the present embodiment, compensation capacity element71is provided around Pch-Tr elements21and22, and compensation capacity element73is provided around Nch-Tr elements31and32. Hereafter, the configuration of compensation capacity elements71and73will be described in detail.

In a Pch-Tr element region, as shown inFIG. 6A, dummy pattern126is configured to include dummy patterns25a,25b, and26shown inFIG. 2B. The portion of dummy pattern126corresponding to dummy patterns25aand25bis provided in parallel with the gate electrode of Pch-Tr elements21and22. The portion corresponding to dummy pattern26is provided between the active pattern on the side of short-side and Pch-Tr elements21and22.

Further, in the present embodiment, a part of dummy pattern126is provided on active pattern42shown inFIG. 2A, and this portion becomes part of the configuration of compensation capacity element71. Dummy pattern126is connected with wiring57shown inFIG. 6Bvia contact66shown inFIG. 5.

In an Nch-Tr element region, as shown inFIG. 6A, dummy pattern128is configured to include dummy patterns27a,27b, and28shown inFIG. 2B. The portion of dummy pattern128corresponding to dummy patterns27aand27bis provided in parallel with the gate electrode of Nch-Tr elements31and32. The portion corresponding to dummy pattern28is provided between the active pattern on the side of short-side and Nch-Tr elements31and32.

Further, in the present embodiment, a part of dummy pattern128is provided on active pattern44shown inFIG. 2Aand this portion becomes part of the configuration of compensation capacity element73. Dummy pattern128is connected with wiring55shown inFIG. 6Bvia contact68shown inFIG. 5.

Contacts66and68are formed concurrently with well contact61and sub-contact63. In the present embodiment, gate electrodes211,221,311, and321and dummy patterns126and128are formed of polysilicon doped with a conductive impurity.

Wiring55shown inFIG. 6Bis longer than the pattern of wiring51shown inFIG. 2Cby the length of the portion where the right end portion in the figure forms contact68. In contrast, wiring57shown inFIG. 6Bis longer than the pattern of wiring53shown inFIG. 2Cby the length of the portion where the left end portion in the figure forms contact66.

FIG. 7is a sectional view taken along line A-B shown inFIG. 5; andFIG. 8is a sectional view taken along line C-D shown inFIG. 5.FIG. 7shows a section of compensation capacity element71in a Pch-Tr element region.FIG. 8shows a section of compensation capacity element73in an Nch-Tr element region.

As shown inFIG. 7, N-well diffusion layer10is provided from the surface of substrate100to a predetermined depth, and trench oxide film81is provided in the outer periphery of active patterns in N-well diffusion layer10. Gate oxide film83is formed on N-well diffusion layer10and dummy pattern126is provided on a part of the surface of gate oxide film83. Inter-layer insulation film85covering the side face and upper face of dummy pattern126is formed on gate oxide film83, and wiring55is provided on inter-layer insulation film85. Wiring55has its side face and upper face covered with insulation film87.

Well-contact diffusion layer91is formed in N-well diffusion layer10under the site of gate oxide film83which is not covered with dummy pattern126. Well-contact diffusion layer91has a higher concentration of N-type conductive impurities than that of N-well diffusion layer10. Well-contact diffusion layer91is connected with wiring55via well contact61which is provided so as to pass through inter-layer insulation film85and gate oxide film83.

As shown inFIG. 7, dummy pattern126and well contact61are alternately provided on the active pattern in the longitudinal direction of the standard cell. It is noted that well-contact diffusion layer91is concurrently formed in the source/drain electrode forming process of Nch-Tr elements31and32.

As shown inFIG. 8, P-well diffusion layer82is provided from the surface of substrate100to a predetermined depth, and trench oxide film81is provided in the outer periphery of active patterns in P-well diffusion layer82. Gate oxide film83is formed on P-well diffusion layer82and dummy pattern128is provided on a part of the surface of gate oxide film83. Inter-layer insulation film85covering the side face and upper face of dummy pattern128is formed on gate oxide film83, and wiring57is provided on inter-layer insulation film85. Wiring57has its side face and upper face covered with insulation film87.

Sub-contact diffusion layer93is formed in P-well diffusion layer82under the site of gate oxide film83which is not covered with dummy pattern128. Sub-contact diffusion layer93has a higher concentration of P-type conductive impurities than that of P-well diffusion layer82. Sub-contact diffusion layer93is connected with wiring57via sub-contact63which is provided so as to pass through inter-layer insulation film85and gate oxide film83.

Making the impurity concentration in well-contact diffusion layer91and sub-contact diffusion layer93higher than that in the well-diffusion layer will reduce the contact resistance with the well diffusion layer thereby facilitating the supply of voltage from the wiring.

As shown inFIG. 8, dummy pattern128and sub-contact63are alternately provided on the active pattern in the longitudinal direction of the standard cell. It is noted that sub-contact diffusion layer93is concurrently formed in the source/drain electrode forming process of Pch-Tr elements21and22.

Compensation capacity element71is configured to include dummy pattern126, gate oxide film83, and N-well diffusion layer10. A capacity element made up of these three configurations is formed in the region of active pattern42shown inFIG. 2A. As so far described usingFIG. 5, dummy pattern126is connected with wiring57via contact66. Further, as described usingFIG. 8, wiring57is connected with P-well diffusion layer82via sub-contact63, as a result of which, dummy pattern126has the same electric potential as P-well diffusion layer82.

Compensation capacity element73is configured to include dummy pattern128, gate oxide film83, and P-well diffusion layer82. A capacity element made up of these three configurations is formed in the region of active pattern44shown inFIG. 2A. As so far described usingFIG. 5, dummy pattern128is connected with wiring55via contact68. Further, as described usingFIG. 7, wiring55is connected with N-well diffusion layer10via well contact61, as a result of which, dummy pattern128has the same electric potential as N-well diffusion layer10.

It is noted that while the standard cell of the present embodiment has characteristic features in its pattern layout and in the structure formed associated therewith, it can be fabricated by using a usual manufacturing technology of semiconductor devices; therefore, detailed description on the manufacturing method of the standard cell of the present embodiment will be omitted.

Next, the actions by the standard cell having the above described configuration will be described.

A predetermined electric potential is applied to N-well diffusion layer10of the standard cell shown inFIG. 5via wiring55, and an electric potential lower than the foregoing electric potential is applied to P-well diffusion layer82via wiring57. Hereafter, the higher one of the two types of electric potentials is referred to as a “high potential” and the lower one as a “low potential”.

In compensation capacity element71, dummy pattern126will be the electrode to which a low potential is applied; N-well diffusion layer10will be the electrode to which a high potential is applied; and gate oxide film83functions as a dielectric. This will result in a configuration in which a plurality of parallel plate capacity elements, each of which is made up of two electrodes interposing a dielectric, are connected in parallel. The capacity, owing to compensation capacity element71, provides a compensation capacity between the high and low potential power supplies for suppressing fluctuation of the power supply voltage.

In compensation capacity element73, dummy pattern128will be the electrode to which a high potential is applied; P-well diffusion layer82will be the electrode to which a low potential is applied; and gate oxide film83functions as a dielectric. This will result in a configuration in which a plurality of parallel plate capacity elements, each of which is made up of two electrodes interposing a dielectric, are connected in parallel. The capacity, owing to compensation capacity element73, provides a compensation capacity between the high and low potential power supplies for suppressing fluctuation of the power supply voltage. Hereafter, a site where the parallel plate capacity element is formed is referred to as a capacity element forming site.

As so far described, in the present embodiment, by proving a capacity element in an active pattern utilizing a gate oxide film and a gate dummy pattern disposed in a standard cell, compensation capacity for controlling power supply noise is formed in the standard cell without an increase in the cell size. Providing a contact for supplying voltage to the well diffusion layer in an active pattern will enable disposing all those configurations within the standard cell and make them exhibit respective functions without sacrificing the contact and the gate dummy pattern.

Since it is possible to dispose all of contacts for supplying voltage to the well diffusion layer and to dispose gate dummy patterns to make up part of the configuration of the capacity element for controlling power supply noise, it is providing a compensation capacity for controlling noise in a quantity that is required for various power supplies without resulting in an increase in chip size is made possible.

Further, since the gate dummy pattern includes a dummy pattern for the purpose of reducing variation of the gate length when forming gate electrodes and for the purpose of planarization of inter-layer insulation films when applying CMP processing thereto, these objects can also be realized.

Application examples of the standard cell of the present embodiment will be described. In this example, multiple kinds of standard cells including the standard cell of the present embodiment are disposed side by side along the X-direction and Y-direction.

FIG. 9is a plan perspective view to show a configuration example of a circuit in which multiple kinds of standard cells are placed side by side. The lateral direction ofFIG. 9is referred to as X-direction and the longitudinal direction as Y-direction. Two kinds of standard cells including the standard cell shown inFIG. 5are utilized. The standard cell shown inFIG. 5corresponds to standard cells2ato2dshown inFIG. 9, and the other kind of cell corresponds to standard cells4aand4b.

In the site indicated by arrow401ofFIG. 9, adjacent portions between respective capacity element forming sites of standard cell2aand standard cell2care overlapped. In a similar manner to this, the capacity element forming sites in the adjacent portions of standard cells4a,2band standard cells2d,4bare overlapped. Accordingly, parts of N-well diffusion layer10aand N-well diffusion layer10bare overlapped as well. As a result of such disposition, the circuit area in the X-direction will be reduced by the amount of overlap indicated by arrow401.

In the site indicated by arrow403ofFIG. 9, capacity element forming sites in adjacent portions of standard cell2cand standard cell2dare overlapped. In a similar manner to this, the capacity element forming sites in respective adjacent portions of standard cell2dand standard cell4b, standard cell2aand standard cell4a, and standard cells4aand standard cell2bare overlapped. As a result of such disposition, the circuit area will be reduced in the Y-direction as well.

When disposing a plurality of standard cells side by side, by overlapping the capacity element forming sites of adjacent standard cells so as to allow the adjacent standard cells to share the use of the capacity element, reducing the area occupied by the circuit is made possible.

Next, various dimensions in a standard cell will be described for the case in which standard cells are placed side by side along the X-direction and Y-direction as shown inFIG. 9.FIG. 10is a plan perspective view to explain various dimensions in a standard cell where the standard cell shown inFIG. 5is used. Moreover, the coordinate axes ofFIG. 10correspond to those ofFIG. 9.

InFIG. 9, adjacent standard cells are disposed in such a way that the capacity element forming sites thereof are overlapped. In this case, it is desirable that length E of the standard cell in the longitudinal direction, length G of Pch-Tr element region in the longitudinal direction, and length H of Nch-Tr element region in the longitudinal direction are standardized for all kinds of standard cells that are to be disposed. Length F of the standard cell in Y-direction is adapted to be an integral multiple of a predetermined basic length. The basic length is, for example, 1.2 μm.

Further, in order to arrange that adjacent standard cells can share the use of a capacity element forming site, it is necessary make a configuration such that the well contacts or sub-contacts and the dummy patterns in the overlapping portions between adjacent standard cells correspond to one another adjacent standard cell. Describing this on the inner edge of the upper side of the cell inFIG. 10, the pitch of capacity electrode part126awhich is part of the capacity element of dummy pattern126is fixed, and the pitch of well contact61is fixed as well. Then, those pitches are set to have the same value J. This value of J corresponds to have above described predetermined basic length.

In this case, although description has been made of the inner edge of the cell on the side of Pch-Tr element region, the same is true with the respective pitches of capacity electrode part128aand sub-contact63in the inner edge of the cell on the side of Nch-Tr element region.

The pitch of well contacts61, which are disposed along the X-direction in respective left and right inner edges of the cell inFIG. 10, is fixed, and the pitch of sub-contact63is fixed as well. The pitches for capacity electrode parts126band128b, which are disposed along the X-direction, are also fixed respectively. Further, the distance between well contact61aand contact68is made equal to the distance between sub-contact63aand contact66.

In the present example, even when well contacts, sub-contacts, and gate dummy patterns are disposed in a standard cell, it is possible to form a capacity between power supplies having different voltages without increasing the size of the standard cell.

Though the number of standard cells mounted on a single chip varies depending on the scale of the chip and the design specifications of the mask layout, now, we consider cases of hundreds to thousands cells. Although the capacity which can be formed in a single chip is small, when hundreds to thousands of standard cells are mounted, the total capacity will become large making it possible to dispose a compensation capacity for controlling power supply noise within a chip in a sufficient quantity required for various power supplies without resulting in an increase in chip size.

In Patent Document 1, in view of the purpose of circuitry of the standard cell, it is considered to select the most important configuration from among a compensation capacity, a contact including a well contact and a sub-contact, and a gate dummy pattern, and the configuration selected is disposed in a circuit cell. In the present embodiment, it is possible to provide a compensation capacity, a well contact, a sub-contact, and a gate dummy pattern all within a standard cell. Therefore, it is possible to avoid such a case in which providing one of the patterns of those configurations prevents providing the other patterns, and thus to improve the reliability of products.

Second Embodiment

The present embodiment is another configuration example based on the standard cell which has been described in the first embodiment. It is noted that in this embodiment, description will be made concerning different points of the standard cell shown inFIG. 5, and description on similar configurations will be omitted. Further, configurations similar to those of the first embodiment are given the same.

The pattern of compensation capacity element will not be limited to the case of the standard cell shown inFIG. 5. The pattern of a compensation capacity element can have any geometry provided that a parallel plane capacity element having a gate oxide film as a dielectric can be configured by superposing an active pattern and a dummy pattern of gate electrode disposed in a standard cell, via a gate oxide film. Several examples will be described below.

FIG. 11is a plan perspective view to show a configuration example of the standard cell in the present embodiment. The standard cell shown inFIG. 11is configured such that the numbers of well contacts and sub-contacts connected to the active pattern in the inner edge of the cell are decreased compared with the standard cell shown inFIG. 5, thereby increasing the overlapping area between the dummy pattern and the well diffusion layer.

In the configuration example shown inFIG. 11, the number of well contacts61to be connected to active pattern42is decreased by 6 to 4 from 10 in the case shown inFIG. 5. Then dummy pattern261is enlarged over the free space where the contacts have been removed. Similarly to this, the number of sub-contacts63connected to active pattern44is decreased to 4 from 10 in the case ofFIG. 5, and dummy pattern281is enlarged over the free space where the contacts have been removed. In this way, by enlarging the area of the opposing surface between the well diffusion layer and the dummy pattern in which a portion of surface area of the well diffusion layer corresponds to the corresponding surface area of the dummy pattern, the capacity value of the compensation capacity becomes larger than in the case shown inFIG. 5.

However, when the pattern as shown inFIG. 11is used, the data rate of the gate pattern may become too large, and there is risk of degrading the planarization by CMP processing. In order to avoid this problem, the standard cell shown inFIG. 11may be configured as follows.

FIG. 12is a plan perspective view to show another configuration example of the standard cell shown inFIG. 11. By providing slit361in dummy pattern261shown inFIG. 11to form dummy pattern263as shown inFIG. 12, the data rate of the gate pattern will be decreased. Similarly for the side of Nch-Tr element region, by providing dummy pattern283formed with slit381, the data rate of the gate pattern will be decreased. Further, by adjusting the areas of slits361and381, it is possible to adjust the data rate of the gate pattern.

Although the data rate of gate pattern suitable for CMP varies depending on the diffusion process, when the entire chip is divided into squares of about 20 μm, a range of 25% to 95% in each square is desirable.

Next, another standard cell which is configured to have a compensation capacity value larger than that of the standard cell shown inFIG. 5will be described.

FIG. 13is a plan perspective view to show another configuration example of the standard cell of the present embodiment. The standard cell shown inFIG. 13is configured such that the gate width of the Pch-Tr element is smaller than that of the standard cell shown inFIG. 5and is equal to that of the Nch-Tr element. Decreasing the gate width will increase the area of dummy pattern26shown inFIG. 2B.

Further, the active pattern in the Pch-Tr element region is enlarged from arrow412to arrow411to be designated as active pattern46. InFIG. 13, dummy pattern26shown inFIG. 2Bis overlapped with active pattern46via gate oxide film83so that the area of the opposing surface between N-well diffusion layer10and dummy pattern265in which a portion of surface area of N-well diffusion layer10corresponds to the corresponding surface area of dummy pattern265, is enlarged to be larger than in the standard cell shown inFIG. 5. Similarly, the active pattern in the Nch-Tr element region is expanded from arrow414to arrow413to be designated as active pattern48. The area of the opposing surface between the P-well diffusion layer and dummy pattern285in which a portion of surface area of the P-well diffusion layer corresponds to the corresponding surface area of dummy pattern285, is enlarged to be larger than in the standard cell shown inFIG. 5.

In this way, the compensation capacity of the standard cell becomes larger than in the case shown inFIG. 5. It is noted that although inFIG. 13, the gate width of the Pch-Tr element is made smaller than in the case shown inFIG. 5, the gate width may be the same as in the case shown inFIG. 5.

When expanding the area of active pattern as shown inFIG. 13, a contact may be provided in a part of the enlarged area rather than assigning all of the enlarged area to the compensation capacity element. Hereafter, examples of such a case will be described.

FIG. 14is a plan perspective view to show another configuration example of the standard cell shown inFIG. 13.

From dummy pattern265shown inFIG. 13, a part of the region near the Pch-Tr element is removed to form dummy pattern267as shown inFIG. 14. Then, well contacts61aand61bare provided in the site from where the part of dummy pattern has been removed. Similarly, from dummy pattern285shown inFIG. 13, a part of the region near the Nch-Tr element is removed to form dummy pattern287as shown inFIG. 14. Then, well contacts63aand63bare provided in the site from where the part of dummy pattern has been removed.

In this way, by increasing the number of contacts for supplying electric potential to N-well diffusion layer10and the P-well diffusion layer, the electric potential of N-well diffusion layer10and the P-well diffusion layer is more stabilized thereby improving anti-latchup characteristic.

It is noted that although, in the above described first and second embodiments, Nch-Tr elements and Pch-Tr elements are provided in each standard cell, one of them may be provided in each standard cell. Although description has been made that the standard cell is configured to include a Pch-Tr element region and an Nch-Tr element region, it may be a cell that includes at least either one of the element regions.

Further, although a gate oxide film is used for the dielectric of the compensation capacity element, other types of insulation films may be used. Moreover, description has been made of the case in which the standard cell is an inverter circuit (INV), the standard cell may be other logic circuits such as an NAND and NOR.

Third Embodiment

The configuration of a standard cell of the semiconductor device of the present embodiment will be described. The standard cell of the present embodiment is configured to include a resistance element. Configurations similar to those shown inFIGS. 3 and 4are given like symbols, and detailed description thereof will be omitted. In the present embodiment, the case in which the resistance element is an N-type diffusion layer will be described.

FIG. 15Ais a plan perspective view to show a configuration example of the standard cell of the present embodiment; andFIG. 15Bshows an equivalent circuit of the standard cell shown inFIG. 15A.FIG. 16Ais a sectional view taken along line C-D shown inFIG. 15A.

The standard cell of the present invention is provided with dummy pattern506which is formed by adding a plurality of enlarged parts505in the outer periphery of dummy pattern504shown inFIG. 3A. Dummy pattern506is formed for example in the same layer as the gate electrode of a transistor element not shown, and corresponds to a dummy pattern for planarization at the time of CMP processing. Enlarged part505of dummy pattern506is formed above N-well diffusion layer602via gate oxide film710as shown inFIG. 16A. With enlarged part505of dummy pattern506and N-well diffusion layer602being electrodes, and with gate oxide film710being an insulation film, it is realized that a configuration in which the insulation film is interposed by two electrodes is formed.

With a VDD potential applied to well-contact diffusion layer514and N-well diffusion layer602and with a low voltage potential which is lower than a VDD potential (hereafter, the low voltage potential is a ground potential VSS) applied to dummy pattern506, a parallel plate capacitor having gate oxide film710as a dielectric is constituted of enlarged part505of dummy pattern506, N-well diffusion layer602, and gate oxide film710. The capacity of the parallel plate capacitor provides a compensation capacity between VDD and VSS power supplies for the purpose of suppressing variation of power supply voltage. That is, the parallel plate capacitor provides a compensation capacity element for controlling power supply noise.

First aluminum wiring540is provided on insulation film714shown inFIG. 4. The reason why the wiring is referred to as first aluminum wiring540is that it has two characteristics: that the wiring is in the first layer of the wirings provided above insulation film714, and that the conductive material thereof is aluminum. Although, the conductive material is aluminum in this case, other metals such as copper and tungsten may be used. The supply of a VSS potential to dummy pattern506is performed, as shown inFIG. 15A, via first aluminum wiring540, contact526, tungsten wiring539, and contact528. Hereafter, the connection relationship of these configurations will be described with reference to a sectional structure diagram.

FIG. 16Bshows a sectional structure at the site of first aluminum wiring540. As shown inFIG. 16B, contact526made up of a conductive plug is provided in insulation film712, and tungsten wiring539and contact528are provided in insulation film714. Dummy pattern506is connected with tungsten wiring539via contact526. First aluminum wiring540is connected with tungsten wiring539via contact528. Tungsten wiring539serves as a pad for relaying the electrical connection between dummy pattern506and first aluminum wiring540.

According to the configuration described above, compensation capacity element750is provided between tungsten wirings531and535to which a VDD potential is supplied, and to first aluminum wiring540to which a VSS potential is supplied, as shown in the equivalent circuit ofFIG. 15B.

It is noted that inFIG. 15A, a boundary line for distinguishing dummy pattern504from enlarged part505is drawn on dummy pattern506in order to explain the enlarged pattern, but the boundary line is not provided on the pattern which is actually fabricated. Further, the outer edge of enlarged part505corresponds to deep N-well diffusion layer604, but that is not necessarily so.

Further, the reason why the outer periphery of dummy pattern504is not uniformly enlarged, and instead a site where there is no dummy pattern above well-contact diffusion layer514, is to provide well contact524for connecting tungsten wiring535with well-contact diffusion layer514as shown inFIG. 16A. This will cause well contact524and dummy pattern506to be electrically isolated so that the insulating property of the two electrodes of the compensation capacity is maintained.

In the standard cell of the present embodiment, a part of the dummy pattern, which is disposed between sub-contact diffusion layer512and well-contact diffusion layer514, out of the dummy pattern disposed in the region of the cell including a resistance element, is enlarged toward the outside and is overlapped on well-contact diffusion layer514via gate oxide film710. This configuration forms a parallel plate capacitor in which well-contact diffusion layer514to which a VDD potential is supplied and dummy pattern506to which a VSS potential is supplied serve as the electrode respectively, and gate oxide film710serves as a dielectric, and the capacity of this capacitor provides a compensation capacity between VDD-VSS power supplies for the purpose of suppressing the fluctuation of power supply voltage.

Further, to provide a VSS potential to dummy pattern506, it is necessary to provide wiring for the VSS potential somewhere in the region of the standard cell, but generally a resistance element is susceptible to noise. Because of this, it is necessary to cut off noises to the resistance element from the signal wiring which is provided in an upper layer of the standard cell, such as a second aluminum wiring and a third aluminum wiring. To cut off the noise, the resistance element is covered with a shield by the first aluminum wiring fixed to a VSS potential, or the disposition of a signal line above the resistance element is avoided in many cases. Taking into consideration such a wiring layout, it is easy to provide a connection configuration for connecting the first aluminum wiring fixed to a VSS potential with dummy pattern506, and the provision of such connection configuration will not be a demerit to the chip.

As described in the section of related art, in a DRAM, resistance elements are used in large numbers in a reference circuit for generating various reference voltages by resistive potential division. Since a reference circuit is made up of analog circuits, it is characteristically susceptible to noise and therefore it is especially important to dispose a compensation capacity for controlling power supply noise for a power supply used in a reference circuit. Further, concerning the location at which compensation capacity will be disposed, it is more effective in achieving noise reduction to dispose it in the vicinity of circuit elements rather than in free space that is distant from the circuit elements such as a resistance element.

The present embodiment makes it possible to utilize the well-contact diffusion layer disposed in the region of resistance element, and the dummy pattern for CMP processing to form compensation capacity for controlling power supply noise without resulting in an increase in the size of the standard cell including the resistance element.

Although there is a limit for the capacitive value of a capacity element which can be formed without changing the entire size of the standard cell, generally, in a DRAM, resistance elements based on a diffusion layer are disposed side by side in a certain number (equals about 50) and also configurations in which a certain number of them are disposed side by side are present in several locations within a chip. Therefore, the value that represents the total quantity of capacity throughout the chip becomes a large one thereby enabling the achievement of a satisfactory effect by way of the compensation capacity. Further, it is possible to dispose the compensation capacity element in the vicinity of the circuit element thereby demonstrating that a greater effect can be obtained in implementing counter measures against noise.

The present example is configured such that a plurality of the standard cells shown inFIG. 15Aare disposed side by side. Although it is possible to use the standard cell including a resistance element described in the third embodiment by singly disposing it as shown inFIG. 15A, it is often the case that a plurality of resistance elements are used by being placed side by side in a circuit of DRAM.

FIG. 17Ais a plan perspective view to show a configuration example in a case in which a plurality of the standard cells shown inFIG. 15Aare disposed side by side. With reference to two axes shown inFIG. 17A, four (2 rows×2 columns) standard cells1001ato1001dare disposed side by side. Resistance elements500a,500b,500c, and500dare series connected in order. When disposing standard cells1001ato1001dside by side, they are disposed such that sites of adjacent well-contact diffusion layers are overlapped. This will be described with reference to the drawings.

Standard cell1001aand standard cell1001bshare the use of a compensation capacity element which is shown by arrow P ofFIG. 17Aand is made up of a well-contact diffusion layer, a gate oxide film, and a dummy pattern. Standard cell1001cand standard cell1001dshare the use of a compensation capacity element which is shown by arrow Q ofFIG. 17Aand is made up of a well-contact diffusion layer, a gate oxide film, and a dummy pattern. Standard cell1001aand standard cell1001dshare the use of a compensation capacity element which is shown by arrow R ofFIG. 17Aand is made up of a well-contact diffusion layer, a gate oxide film, and a dummy pattern. Standard cell1001band standard cell1001cshare the use of a compensation capacity element which is shown by arrow S ofFIG. 17Aand is made up of a well-contact diffusion layer, a gate oxide film, and a dummy pattern.

Respective dummy patterns506of standard cells1001ato1001dare electrically connected. A dummy pattern group, in which four dummy patterns506are connected into a unity, is connected with first aluminum wiring541via a contact, tungsten wiring, and a contact. In the example shown inFIG. 17A, the dummy pattern group is connected with first aluminum wiring541via contact526, tungsten wiring539, and contact528which are provided in each of standard cell1001cand standard cell1001d. As shown inFIG. 17B, the compensation capacity elements of respective standard cells are connected with first aluminum wiring541.

As shown inFIG. 17A, in order to allow a plurality of standard cells1001ato1001dto be disposed, the overlapping portions between adjacent standard cells are configured to have the same geometry even when the standard cells are disposed in a mirrored manner with respect to each of the X-axis and Y-axis in the area that surrounds a standard cell.

FIG. 18is a plan view to show the layout of the standard cell of the present example. As shown inFIG. 18, the sizes of length G of standard cell1001in the X-axis direction (short-side length) and length H in the Y-axis direction (long-side length) are specified to be values divisible by two. The value of length G divided by 2 is indicated as “I”, and the value of length H divided by 2 as “J”.

Further, in order to enable the respective forming of a contact for supplying a predetermined electric potential to the well-contact diffusion layer and a compensation capacity element even when respective parts of adjacent standard cells are overlapped by being disposed in a mirrored manner, dummy pattern506, which is superposed above a well-contact diffusion layer via a gate oxide film, is configured to have symmetric left and right geometries (two geometries of length I shown inFIG. 18) with the centerline halving length G in the X-axis direction as the axis of symmetry. For the same reason, dummy pattern506is configured to have symmetric upper and lower geometries (two geometries of length J shown inFIG. 18) with the centerline halving length H in Y-axis direction of the standard cell as the axis of symmetry.

In the present example, a plurality of the standard cells described in the third embodiment are provided in such a way that well-contact diffusion layers and dummy patterns disposed in the region of a standard cell are overlapped between adjacent standard cells. Thereafter, providing the dummy pattern with a low voltage potential (for example, VSS) opposite to the well-contact diffusion layer will result in the formation of a compensation capacity for controlling noise between VDD-VSS power supplies. Thus, without increasing the size of the standard cell shown inFIG. 3Aand also without sacrificing respective functions of the well-contact diffusion layer and the dummy pattern provided in the standard cell, the well-contact diffusion layer and the dummy pattern can be utilized to form compensation capacity for controlling power supply noise.

Fourth Embodiment

The standard cell of the present embodiment is configured such that the capacity of the compensation capacity is increased compared with the standard cell described in the third embodiment. It is noted that in the drawing to explain the present embodiment, configurations similar to those of the standard cell described in the third embodiment are given the same symbols and detailed description thereof will be omitted.

In addition to the standard cell described in the third embodiment, the dummy pattern may be of any geometry provided that a parallel plate capacitor having a gate oxide film as a dielectric can be formed by superposing a well-contact diffusion layer and a dummy pattern via a gate oxide film.

FIG. 19is a plan perspective view to show a configuration example of the standard cell of the present embodiment. As shown inFIG. 19, tungsten wiring532which is smaller in wiring length compared with tungsten wiring531shown inFIG. 15Ais disposed in place of tungsten wiring531. Further, the number of well contacts524for connecting tungsten wiring532with well-contact diffusion layer514is decreased from 9 to 4. By reducing the length of tungsten wiring and decreasing the number of well contacts, the overlapping area between well-contact diffusion layer514and dummy pattern507is increased accordingly.

Further, tungsten wiring534which is smaller in wiring length compared with tungsten wiring535shown inFIG. 15Ais disposed in place of tungsten wiring535. The number of well contacts524for connecting tungsten wiring534with well-contact diffusion layer514is decreased from 9 to 4. By reducing the length of tungsten wiring and decreasing the number of well contacts, the overlapping area between well-contact diffusion layer514and dummy pattern507is increased accordingly. In this way, the compensation capacity has been increased.

FIG. 20is a plan perspective view to show another configuration example of the standard cell of the present embodiment. InFIG. 20, the compensation capacity is further increased compared with the configuration shown inFIG. 19.

As shown inFIG. 20, tungsten wiring536corresponding to the short-side length of the standard cell is disposed in place of tungsten wiring532shown inFIG. 19. The number of well contacts524for connecting tungsten wiring536with well-contact diffusion layer514is decreased to 2 from 4 in the case ofFIG. 19so that well contacts524are only provided in two corners of the standard cell. By reducing the length of tungsten wiring and decreasing the number of well contacts, the overlapping area between well-contact diffusion layer514and dummy pattern508is further increased accordingly.

Further, as shown inFIG. 20, tungsten wiring538corresponding to the short-side length of the standard cell is disposed in place of tungsten wiring534shown inFIG. 19. The number of well contacts524for connecting tungsten wiring538with well-contact diffusion layer514is decreased from 4 to 2 in the case ofFIG. 19so that well contacts524are only provided in two corners of the standard cell. By reducing the length of tungsten wiring and decreasing the number of well contacts, the overlapping area between well-contact diffusion layer514and dummy pattern508is further increased accordingly.

According to the present embodiment, it is possible to increase the compensation capacity for controlling power supply noise, thereby improving immunity against noise.

Fifth Embodiment

Although, in the third and fourth embodiments, description has been made of the case in which the resistance element included in the standard cell is an N-type conductive diffusion layer, the present embodiment corresponds to the case in which the resistance element is a P-type conductive diffusion layer.

The configuration of the standard cell of the present embodiment will be described.FIG. 21Ais a plan perspective view to show a configuration example of the standard cell of the present embodiment;FIG. 21Bshows an equivalent circuit of the standard cell shown inFIG. 21A.FIG. 22is a sectional view taken along a line C-D shown inFIG. 21A. It is noted that configurations similar to those shown inFIGS. 3A,4, and15A are given the same symbols and detailed description thereof will be omitted.

An N-well diffusion layer (not shown) is provided in each element-forming region of a resistance element and a MOS transistor, from the surface of N-type conductive substrate (hereafter simply referred to as an “N-substrate”)900to a predetermined depth, and gate oxide film710is provided as an insulation film on the surface of N-substrate900.

As shown inFIG. 21A, resistance element800is formed of a diffusion layer of a P-type conductive impurity and is formed in a region from the surface of an N-well diffusion layer (not shown) to a predetermined depth. P-well diffusion layer902is formed in the area that surrounds the N-well diffusion layer, and the side face of the N-well diffusion layer is covered with P-well diffusion layer902.FIG. 21Ashows outer edge922aand inner edge922bof the pattern of P-well diffusion layer902. Further, deep P-well diffusion layer904is formed underneath the N-well diffusion layer, and the bottom face of the N-well diffusion layer is covered with deep P-well diffusion layer904. Further, as shown inFIG. 22, deep P-well diffusion layer904is in contact with the bottom face of P-well diffusion layer902.

Trench oxide film551shown inFIG. 4is formed in the area that surrounds resistance element800, and the side face of resistance element800is covered with trench oxide film551. Dummy pattern502is provided on trench oxide film551in such a way to surround the forming region of resistance element800along the planer pattern of trench oxide film551.

Sub-contact diffusion layer812into which an N-type conductive impurity is diffused is formed outside trench oxide film551shown inFIG. 4. Sub-contact diffusion layer812has a higher concentration of the conductive impurity than that of the N-well diffusion layer (not shown). The reason why sub-contact diffusion layer812has a higher concentration of the conductive impurity is to decrease the contact resistance between sub-contact822provided in the overlying layer and the N-well diffusion layer provided in the underlying layer. Trench oxide film553shown inFIG. 4is formed in the area that surrounds sub-contact diffusion layer812, and the side face of sub-contact diffusion layer812is covered with trench oxide film553.

Well-contact diffusion layer814into which a P-type conductive impurity is diffused is formed in the area that surrounds trench oxide film553. Since well-contact diffusion layer814has a higher concentration of the conductive impurity than that of P-well diffusion layer902, it is designated as “P+” inFIG. 22. The reason why well-contact diffusion layer814has a higher concentration of the conductive impurity is to decrease the contact resistance between well contact824provided in the overlying layer and P-well diffusion layer902provided in the underlying layer.

The standard cell of the present embodiment is, as shown inFIG. 21A, provided with dummy pattern506which is formed by adding a plurality of enlarged parts in the outer periphery of dummy pattern504shown inFIG. 3A. The enlarged part of dummy pattern506is formed above P-well diffusion layer902via gate oxide film710as shown inFIG. 21A. It is assumed that the enlarged part of dummy pattern506and P-well diffusion layer902are the electrodes and gate oxide film710is the insulation film, a configuration in which an insulation film is interposed by two electrodes, is realized as shown inFIG. 22.

When a VSS potential is applied to well-contact diffusion layer814and P-well diffusion layer902, and when a VDD potential is applied to dummy pattern506, a parallel plate capacitor that as gate oxide film710as a dielectric will be made up of dummy pattern506, P-well diffusion layer902, and gate oxide film710. The capacity of the parallel plate capacitor provides a compensation capacity between VDD and VSS power supplies for the purpose of suppressing the variation of power supply voltage. That is, the parallel plate capacitor provides a compensation capacity element for controlling power supply noise.

According to the above described configuration, compensation capacity element850is provided between tungsten wirings531,535to which a VSS potential is supplied and first aluminum wiring540to which a VDD potential is supplied as shown in the equivalent circuit ofFIG. 21B.

It is noted that although, inFIG. 21A, a boundary line is drawn on dummy pattern506to make the enlarged part more recognizable, the boundary line will not be provided on the pattern that is to be actually fabricated. Further, although the outer edge of the enlarged part corresponds to deep P-well diffusion layer904, that is not necessarily so.

Further, the reason why the outer periphery of dummy pattern504shown inFIG. 15Ais not uniformly enlarged, and instead a site free of dummy pattern is provided above well-contact diffusion layer814, is to provide well contact824for connecting tungsten wiring535with well-contact diffusion layer814as shown inFIG. 22. This will cause well contact824and dummy pattern506to be electrically isolated so that the insulating performance between the two electrodes of the compensation capacity element is maintained.

The standard cell of the present embodiment will achieve a similar effect to that of the third embodiment even if the resistance element is a P-type conductive diffusion layer. It is noted that each of Example 2 and the fourth embodiment may be applied to the standard cell described in the present embodiment.

According to the present invention, preventing the increase of chip size and improving immunity against power supply noise are made possible.