Driving circuit suppressing peak value of charging current from power supply to capacitive load

A buffer circuit, which supplies current to a capacitive load, has a first circuit for reducing the power supply charging current to the capacitive load during switching intervals. The first circuit includes a charge storage device precharged between inverter switching intervals to produce at least a portion of the load charging current during the switching intervals. A second circuit includes a switching element connected between the power supply and the capacitive load to electrically connect the power supply through the second circuit to the load at a selected time in the switching interval to supplement the charging current produced by the charge storage device.

BACKGROUND OF THE INVENTION 
The present invention relates to an inverter or switching circuit making 
use of complementary insulated gate field effect transistors (hereinafter 
abbreviated as CMOSFET's). More particularly, it relates to an inverter 
circuit with a capacitive load connected to the output terminal thereof in 
which a heavy transient current flows from a power supply under a 
transient condition where an input signal is changed to invert the 
inverter output. 
Since an inverter circuit using CMOSFET's (hereinafter abbreviated as CMOS 
inverter) consumes little power in the steady state condition, its use in 
large-scale integrated circuits (thereinafter abbreviated as IC) is 
desirable. Under the transient condition, however, a considerably large 
power supply current (hereinafter abbreviated as I.sub.DD) flows through 
the CMOS inverter due to a charging current flowing to a capacitive 
component of the load. Accordingly, the peak value of I.sub.DD in the CMOS 
inverter is large during the transient period. Therefore, it is necessary 
to take measures, such as lowering the impedance of power supply wirings 
to the CMOS inverter to reduce this transient current. But such a measure 
would deteriorate a valuable feature of the CMOS circuit; namely, that it 
can use fine wirings because of the low steady state power consumption. 
This problem becomes more remarkable in a memory IC where a large number 
of address inverters operate simultaneously. For instance, in a 64K-bit 
memory, an address input is 16-bits, which means that at least 16 address 
inverters operate simultaneously in response to 16 address input signals 
applied in parallel. In that case, I.sub.DD is multiplied by a factor of 
16, causing an extremely large peak current to flow from the power supply 
of this memory IC. Consequently, a noise is generated in the power supply 
lines, causing many faults in the operation of the memory IC. 
It has been proposed to reduce the peak current by prolonging the CMOS 
inverter switching time to thereby gradually charge the load capacitance. 
However, this method has a drawback that speed-up of the whole IC is 
prevented because of the prolonged response time of the inverter. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide an inverter circuit, in 
which the peak value of the load capacitance charging current component of 
the power supply current can be largely reduced while maintaining 
high-speed operation. 
According to one feature of the present invention, there is provided an 
inverter circuit responsive to an input signal for outputting an inverted 
signal of the input signal, with a first auxiliary circuit connected to 
the inverter circuit. The first auxiliary circuit includes an auxiliary 
capacitor which is charged at a time other than the transient time when 
the output transfers from the low level to the high level (e.g. when the 
input signal is "1" (or "0") level), and is discharged during the 
transient period when the input signal is changed from the low level to 
the high level. Since the discharge current from the auxiliary capacitor 
is added to the power supply current from the power supply for charging 
the capacitive load in the transient period, the peak power supply current 
during the transient period can be greatly reduced. The power supply 
current for charging the auxiliary capacitor flows at a time other than 
the transient period and contributes to the reduced peak current. 
According to another feature of the invention, a second auxiliary circuit 
is added to the inverter circuit in parallel with the first auxiliary 
circuit to feed a part of the output current of the inverter circuit at 
least after the discharging current from the auxiliary capacitor starts to 
flow and favorably after the mentioned discharging current ends during the 
transient period. 
The inverter circuit may comprise a first P-channel type field effect 
transistor (hereinafter abbreviated as Pch-FET) and a first N-channel type 
field effect transistor (hereinafter abbreviated as Nch-FET) connected in 
series between the two power supply terminals, the gates of these FET's 
being commonly connected to an input terminal, and the common junction 
point therebetween being used as an output terminal. The first auxiliary 
circuit may include second, third and fourth Pch-FET's (or Nch-FET's) 
connected in series between one of the power supply terminals and the 
output terminal of the inverter circuit with their respective gates 
connected to the other power supply terminal, the output terminal of the 
inverter circuit and the input terminal of the inverter circuit, 
respectively. An auxiliary capacitor is inserted between the common 
junction point between the second and third FET's and the other power 
supply terminal. The second auxiliary circuit may include a fifth Pch-FET 
(or Nch-FET) inserted between the one of the power supply terminals and 
the output terminal of the inverter circuit and a delay circuit coupled 
between the input terminal of the inverter circuit and the gate of the 
fifth FET. The second auxiliary circuit may further include a sixth 
Pch-FET (or Nch-FET) inserted between the drain of the fifth FET and the 
output terminal of the inverter circuit and having its gate connected to 
the input terminal of the inverter circuit. With the first and second 
auxiliary circuits, the inverter circuit according to this invention can 
reduce the peak value of the capacitive load charging current component of 
the power supply current as compared to the prior art inverter circuit, 
while maintaining a high-speed operation.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
Referring to FIG. 1, a prior art inverter circuit comprises an Nch-FET 
Q.sub.1 and a Pch-FET Q.sub.2 with their drains connected in common to 
form an output terminal 3. The source of the FET Q.sub.1 is connected to a 
V.sub.SS power supply terminal (in the illustrated example, to the ground 
terminal) and the source of the FET Q.sub.2 is connected to a V.sub.DD 
power supply terminal 4 (in the illustrated example, V.sub.DD represents a 
positive voltage). The gates of both FET's are connected in common and 
form an input terminal 2. It is to be noted that a load capacitor C.sub.L 
is present between the output terminal 3 and the ground terminal. 
Referring also to FIG. 2, when the input signal .phi..sub.IN is at "1" 
level (in the illustrated example, a high voltage V.sub.DD level) at a 
time t.sub.o, the Nch-FET Q.sub.1 is ON, and hence the output signal 
.phi..sub.OUT maintains "0" level (V.sub.SS level). Since the Pch-FET 
Q.sub.2 is OFF at this time, the power supply current I.sub.DD does not 
flow. Subsequently, the input signal .phi..sub.IN begins to transfer from 
the "1" level to the "0" level (in the illustrated example the low voltage 
V.sub.SS is the 0 volt level), and when the voltage of the input signal 
has lowered to V.sub.DD -.vertline.V.sub.TP .vertline. (V.sub.TP : a 
threshold voltage of the Pch-FET Q.sub.2) at a time t.sub.1, the Pch-FET 
Q.sub.2 is turned ON and a power supply current I.sub.DD begins to flow. 
As a result, the voltage of the output signal .phi..sub.OUT begins to 
rise, determined by the capability ratio between the Nch-FET Q.sub.1 and 
the Pch-FET Q.sub.2. As the voltage of the output signal .phi..sub.OUT 
rises, the load capacitor C.sub.L is driven, and a charging current 
I.sub.DDL flows from the V.sub.DD power supply terminal through the 
Pch-FET Q.sub.2 into the load capacitor C.sub.L. Therefore, the power 
supply current I.sub.DD which is the sum of the charging current I.sub.DDL 
and a current I.sub.DDO flowing through the FET Q.sub.1 to the ground 
becomes large. Then, the input signal .phi..sub.IN approaches the "0" 
level, and when the voltage reaches V.sub.TN (a threshold voltage of the 
Nch-FET Q.sub.1), the Nch-FET Q.sub.1 is turned OFF, and the power supply 
current component flowing through the Nch-FET Q.sub.1 (I.sub.DDO) stops. 
When the input signal .phi..sub.IN reaches "0" level at a time t.sub.2, 
the output signal .phi..sub.OUT also reaches "1" level, so that the 
I.sub.DDL also stops flowing. Thus the charging current component 
I.sub.DDL has a nearly symmetric waveform with a large peak value. The 
peak value of the charging current I.sub.DDL become larger as the load 
capacitor C.sub.L is increased. As described previously, an important 
problem to be solved is how best to reduce the peak value of this 
I.sub.DDL. 
With reference to FIG. 3, the circuit of a preferred embodiment of the 
present invention comprises a basic inverter circuit 11 which includes a 
first Pch-FET Q.sub.12 and a first Nch-FET Q.sub.11 connected in series at 
an output terminal 17. The source of the Nch-FET Q.sub.11 is connected to 
V.sub.SS terminal (the ground terminal in this example) and the source of 
the Pch-FET Q.sub.12 is connected to a V.sub.DD power supply terminal 16. 
The gates of the Nch-FET Q.sub.11 and the Pch-FET Q.sub.12 are both 
connected to an input terminal 15. A first auxiliary circuit 12 is added 
to the inverter circuit 11, which in turn includes second, third and 
fourth Pch-FET's Q.sub.14, Q.sub.15 and Q.sub.16 connected in series 
between the V.sub.DD power supply terminal 16 and the output terminal 17. 
The respective gates of Q.sub.14, Q.sub.15 and Q.sub.16 are connected to 
the input terminal 15, the output terminal 17, and the ground terminal, 
respectively. The first auxiliary circuit further includes an auxiliary 
capacitor C.sub.A inserted between the common junction point N2 of the 
Pch-FET's Q.sub.15 and Q.sub.16 and the ground terminal. A second 
auxiliary circuit 13 is also added, which includes a fifth Pch-FET 
Q.sub.13 inserted between the V.sub.DD power supply terminal 16 and the 
output terminal 17 and a delay circuit 14 inserted between the input 
terminal 15 and the gate of Q.sub.13. The delay circuit 14 is used to 
delay the input signal .phi..sub.IN by a predetermined period. Since 
precision is not required, the delay circuit 14 can be easily constructed 
using known techniques. 
Now description will be made of the operation of this circuit when the 
input signal .phi..sub.IN transfers from "1" level (V.sub.DD) to the "0" 
level (ground), with reference to FIG. 4. Since the basic inverter circuit 
11 has the same construction as the circuit in the prior art shown in FIG. 
1, its operation is basically the same as that of the prior art circuit. 
At first, when the input signal .phi..sub.IN is at the "1" level (V.sub.DD) 
at a time between t.sub.o and t.sub.11, the Pch-FET's Q.sub.15 and 
Q.sub.16 of the first auxiliary circuit 12 are ON and the Pch-FET Q.sub.14 
is OFF. Hence the auxiliary capacitor C.sub.A is charged via the Pch-FET 
Q.sub.16 by V.sub.DD and stores electric charge therein. Accordingly, the 
charging current I.sub.DDA for this capacitor C.sub.A flows from the 
V.sub.DD power supply terminal 16 as a component of the power supply 
current I.sub.DD, during the period of time t.sub.o to t.sub.11. At this 
moment, the Nch-FET Q.sub.11 is ON and the Pch-FET's Q.sub.12 and Q.sub.13 
are OFF. Therefore, the output voltage .phi..sub.OUT at the output 
terminal 17 is at the "0" level, and the power supply current I.sub.DDO 
through the Nch-FET Q.sub.11 and the charging current I.sub.DDL for the 
load capacitor C.sub.L are both zero. 
Within the period of t.sub.0 to t.sub.11, the input signal .phi..sub.IN 
starts to fall. When the voltage of the input signal .phi..sub.IN is 
lowered to V.sub.DD -.vertline.V.sub.TP .vertline. at the time t.sub.11, 
the Pch-FET Q.sub.12 and the Pch-FET Q.sub.14 are turned ON, and hence a 
current I.sub.DDO through the Pch-FET Q.sub.12 and the Nch-FET Q.sub.11 
and a charging current I.sub.DDL1 through the Pch-FET Q.sub.12 and load 
capacitor C.sub.L for charging the load capacitor C.sub.L begin to flow. 
Furthermore, the electric charge previously stored in the auxiliary 
capacitor C.sub.A begins to discharge as a part of the charging current 
for the load capacitor C.sub.L through the Pch-FET Q.sub.14 (this 
component being represented by I.sub.DDL2). Since this discharge current 
I.sub.DDL2 is based on the discharge of electric charge that has been 
preliminarily stored in the auxiliary element C.sub.A, an increment of the 
power supply current I.sub.DD that is necessary for I.sub. DDL2 after the 
time t.sub.11 is very small. If the conductance of the Pch-FET Q.sub.16 is 
chosen less than about 1/10 of that of the Pch-FET Q.sub.12, then the 
I.sub.DD component passing through the Pch-FET Q.sub.16 is very small, and 
therefore it can be neglected. Moreover, if the auxiliary capacitor 
C.sub.A is chosen nearly the same size as the load capacitor C.sub.L, then 
about one-half of the charging current I.sub.DDL can be obtained from 
I.sub.DDL2. 
Subsequently, the voltage of the input signal .phi..sub.IN is further 
lowered after t.sub.11 and accordingly the voltage of the output signal 
.phi..sub.OUT rises, and when the output voltage value reaches about 
V.sub.DD /2 at a time t.sub.12, the input signal .phi.'.sub.IN delayed by 
the delay circuit 14 in the second auxiliary circuit is applied to the 
Pch-FET Q.sub.13, so that the Pch-FET Q.sub.13 is turned ON and sends out 
an output current to the output terminal 17 which forms another part of 
the charging current for the load capacitor C.sub.L (this component being 
called I.sub.DDL3). As a result the power supply current I.sub.DD now 
includes the I.sub.DDL3 component. On the other hand, the potential at the 
node N.sub.2 which serves as one terminal of the auxiliary capacitor 
C.sub.A becomes nearly the same level as the .phi..sub.OUT when the 
voltage of the output signal .phi..sub.out exceeds V.sub.DD /2, and hence 
the Pch-FET Q.sub.15 is turned OFF, so that the charging current 
I.sub.DDL2 from the auxiliary capacitor C.sub.A is eliminated. Therefore, 
at this time the charging current for the load capacitor C.sub.L is 
comprised of two components; that is, the I.sub.DDL1 passing through the 
Pch-FET Q.sub.12 and the I.sub.DDL3 passing through the Pch-FET Q.sub.13. 
This I.sub.DDL3 component compensates for the loss of the above-described 
I.sub.DDL2 component to promote charging of the load capacitor C.sub.L and 
serves to quickly raise the voltage of the output signal .phi..sub.OUT. 
Therefore, it is favorable to select the conductance of the Pch-FET 
Q.sub.13 larger than that of the Pch-FET Q.sub.12. 
Next, when the input signal .phi..sub.IN approaches the "0" level and its 
voltage becomes equal to or lower than V.sub.TN, then the Nch-FET Q.sub.11 
is turned OFF, and hence the I.sub.DDO component passing through the 
Nch-FET stops. Then, the input signal .phi..sub.IN reaches the "0" level 
and the output signal .phi..sub.OUT reaches the "1" level at a time 
t.sub.13, and as a result, the I.sub.DDL1 component passing through the 
Pch-FET Q.sub.12 as well as the I.sub.DDL3 component passing through the 
Pch-FET Q.sub.13 are also eliminated. 
As will be apparent from the above description, in the circuit of the 
illustrated embodiment, the charging current I.sub.DDL for the load 
capacitor C.sub.L is formed in such a manner that until the voltage of the 
output signal .phi..sub.OUT becomes nearly equal to V.sub.DD /2, the 
charging current is comprised of the I.sub.DDL1 passing through the 
Pch-FET Q.sub.12 and the discharging current I.sub.DDL2 of the auxiliary 
capacitor C.sub.A which has been preliminarily charged, and after the 
output signal .phi..sub.OUT nearly exceeds V.sub.DD /2, the I.sub.DDL2 is 
eliminated and instead the I.sub.DD3 passing through the Pch-FET Q.sub.13 
is newly added. Consequently, the load capacitor charging current 
component I.sub.DDL of the power supply current of the circuit would flow 
over the entire region of operation, and its peak value during the period 
t.sub.11 to t.sub.13 becomes very small as shown in FIG. 4. The extent of 
this reduction of the peak value depends upon the design of the first and 
second auxiliary circuits such as the magnitude of the auxiliary capacitor 
C.sub.A and the conductance of the Pch-FET Q.sub.13. However, it is quite 
easy to reduce the peak value of the charging current to 1/2 or less of 
the peak value in the prior art inverter circuit. 
Furthermore, since those auxiliary charging currents can be subjected to 
appropriate adjustment by varying the delay characteristics of the delay 
circuit 14 in the second auxiliary circuit 13 so as to meet the response 
time of the circuit, there is no need to prolong a response time of the 
inverter circuit 11, and the response time may be rather shortened by 
selecting appropriate timing. 
Now description will be made of the case where the input signal transfers 
from the "0" level to the "1" level, with reference to FIG. 5 which shows 
waveforms of the input signal .phi..sub.IN, the output signal 
.phi..sub.OUT and the power supply current I.sub.DD for this case. 
At first, during the period t.sub.0 to t.sub.20, when the input signal 
.phi..sub.IN is at the "0" level (ground), the Pch-FET's Q.sub.12, 
Q.sub.13, Q.sub.14 and Q.sub.16 are ON and the Nch-FET Q.sub.11 and the 
Pch-FET Q.sub.15 are OFF. Accordingly, the auxiliary capacitor C.sub.A is 
charged, and a power supply charging current I.sub.DDA flows. 
Next, the input signal .phi..sub.IN starts to rise at a time t.sub.20. When 
it rises up to V.sub.TN at a time t.sub.21, the Nch-FET Q.sub.11 is turned 
ON and the discharging current of the load capacitor C.sub.L begins to 
flow through the Nch-FET Q.sub.11. Furthermore the power supply current 
I.sub.DDO flows through the Pch-FET Q.sub.12 and the Nch-FET Q.sub.11, and 
the power supply current I.sub.DDO ' flows through the Pch-FET Q.sub.13 
and the Nch-FET Q.sub.11. At this moment, since the Pch-FET Q.sub.15 is 
kept OFF, only the I.sub.DDA flows through the first auxiliary circuit. 
Subsequently, when the input signal .phi..sub.IN reaches V.sub.DD 
-.vertline.V.sub.TP .vertline., at a time t.sub.23, the Pch-FET Q.sub.13 
is turned OFF and the I.sub.DDO stops flowing, but since the voltage of 
the delayed signal .phi..sub.IN for the input signal .phi..sub.IN which is 
a driving voltage for the Pch-FET Q.sub.13 does not rise as shown in FIG. 
5, the Pch-FET Q.sub.13 is still kept ON, and so the I.sub.DDO ' continues 
to flow. Thereafter when the .phi.'.sub.IN becomes V.sub.DD -V.sub.TP at a 
time t.sub.24, the Pch-FET Q.sub.13 is turned OFF and the I.sub.DDO ' 
stops flowing. The input signal .phi..sub.IN reaches the "1" level, and 
the output signal .phi..sub.OUT reaches the "0" level. 
In other words, in the transient period when the input signal .phi..sub.IN 
transfers from the "0" level to the "1" level, the I.sub.DDO ' passing 
through the Pch-FET Q.sub.13 is added to the power supply current 
I.sub.DDO which flows together with the discharge current of the load 
capacitor C.sub.L in the circuit known in the prior art, and therefore, 
the overall power supply current I'.sub.DD takes the form shown in FIG. 5. 
As described, the circuit of the illustrated embodiment of FIG. 3 has a 
problem that although the peak value of the load capacitor charging 
current component I.sub.DDL of the power supply current I.sub.DD can be 
greatly reduced when the input signal .phi..sub.IN transfers from the "1" 
level to the "0" level, the power supply current I.sub.DDO ' caused by the 
second auxiliary circuit is added to the power supply current when the 
input signal .phi..sub.IN transfers from the "0" level to the "1" level. 
The circuit of another preferred embodiment of the present invention shown 
in FIG. 6 solves the above-mentioned problem. The only difference from the 
circuit shown in FIG. 3 and described previously resides in that the 
second auxiliary circuit 13' includes another Pch-FET Q.sub.17 inserted 
between the drain of the Pch-FET Q.sub.13 and the output terminal 17 and 
having its gate connected to the input terminal 15. In this circuit of the 
modified embodiment, the Pch-FET Q.sub.17 is turned OFF in response to the 
input signal .phi..sub.IN and the I.sub.DDO ' also ceases to flow at the 
same time when I.sub.DDO ceases to flow through Q.sub.12. Therefore, the 
I.sub.DD in this modified embodiment becomes small as indicated by 
I".sub.DD in FIG. 5. 
It is to be noted that in the above-described embodiments, the conductivity 
type of the respective FET's can be changed if necessary. For instance, in 
place of the Pch-FET an Nch-FET can be used for the FET Q.sub.14, and an 
inverted input signal .phi..sub.IN would then be applied to the gate of 
this FET. The Pch-FET's and Nch-FET's may be replaced by Nch-FET's and 
Pch-FET's, respectively, with the terminals of the power supply voltage 
being reversely connected.