Solder bump structure with enhanced high temperature aging reliability and method for manufacturing same

Implementations described herein generally relate to chip packaging, and in particular, to solder bump structures for a semiconductor device and methods of fabricating the same. In one implementation, a solder bump assembly is provided. The solder bump assembly comprises a conductive bond pad formed on a substrate. A conductive pillar is formed on the conductive bond pad. A plating layer is formed on the conductive pillar, wherein the plating layer comprises copper and nickel. A solder bump is formed on the plating layer in electrical communication with the plating layer. The plating layer may be a bi-layer structure comprising a nickel layer formed on the conductive pillar and a copper layer formed on the nickel layer in electrical communication with the solder bump. The plating layer may be a copper-nickel alloy.

TECHNICAL FIELD

Implementations described herein generally relate to chip packaging, and in particular, to solder bump structures for a semiconductor device and methods of fabricating the same.

BACKGROUND ART

An increasing demand for electronic equipment that is smaller, lighter, and more compact has resulted in a concomitant demand for semiconductor packages that have smaller outlines and mounting areas or “footprints.” One response to this demand has been the development of the “flip-chip” method of attachment and connection of semiconductor chips or “dice” to substrates (e.g., PCBs or lead-frames). Flip-chip mounting involves the formation of bumped contacts (e.g., solder balls) on the active surface of the die, then inverting or “flipping” the die upside down and reflowing the bumped contacts (i.e., heating the bumped contacts to the melting point) to form solder joints fusing the bumped contacts to the corresponding pads on the substrate.

In flip-chip mounting and connection methods, thermo-mechanical reliability is becoming an increasing concern of the electronics industry. Notably, the reliability of the solder joints is one of the most critical issues for successful application of such mounting and connection methods. However, solder joints formed using known methods may be prone to cracks at high-stress points due to thermal stress cycling.

Therefore, there is a need for improved solder joints and methods of forming improved solder joints for an integrated circuit.

SUMMARY

Implementations described herein generally relate to chip packaging, and in particular, to solder joints for a semiconductor device and methods of fabricating the same. In one implementation, a solder bump assembly is provided. The solder bump assembly comprises a conductive bond pad formed on a substrate, a conductive pillar formed on the conductive pad, and a plating layer formed on the conductive pillar. The plating layer comprises copper and nickel. A solder bump is formed on the plating layer and is in electrical communication with the plating layer.

In another implementation, an integrated circuit device is provided. The integrated circuit device comprises a substrate, an integrated circuit formed on the substrate, a plurality of conductive bond pads formed in the integrated circuit, and a plurality of solder bump assemblies. Each conductive bond pad of the conductive bond pads is enabled to form an electrical coupling with a portion of the integrated circuit. Each solder bump assembly of the plurality of solder bump assemblies is enabled to form an electrical coupling between a conductive bond pad and circuitry outside the integrated circuit device. Each solder bump assembly comprises a conductive pillar formed on the conductive bond pad, a plating layer formed on the conductive pillar, wherein the plating layer comprises copper and nickel, and a solder bump formed on the plating layer and in electrical communication with the plating layer.

In yet another implementation, a method for fabricating a solder bump assembly is provided. The method comprises forming a first conductive pillar on a first conductive bond pad deposited on a substrate, forming a first plating layer comprising copper and nickel on the first conductive pillar, and forming a first lead-free solder bump on the first plating layer, wherein the first lead-free solder bump includes tin and silver.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments. However, in some embodiments non-identical elements having the same functions can be substituted.

DETAILED DESCRIPTION

Implementations described herein generally relate to chip packaging, and in particular, to solder bump structures for a semiconductor device and methods of fabricating the same. High Temperature Storage (HTS) tests are typically performed to determine the effect on devices of long-term storage at elevated temperatures without any electrical stresses applied. For stacked silicon interconnect (SSIT) production, solder micro-bump joints often suffer from HTS aging reliability issues. Both the limited tin volume in the solder micro-bump joint and volume shrinkage due to the fast formation of tin intermetallic compounds (IMC) (e.g., nickel-tin and copper-tin) during HTS testing lead to volumetric voiding and/or cracking defects within the solder micro-bump joints. In some implementations described herein, a nickel barrier layer for suppression of the IMC reaction and a surface copper layer are provided to minimize the undesirable void formation that leads to voiding or cracking defects within the solder micro-bump joint. This reduction in voiding or cracking defects increases the durability and reliability of the package. Although the implementations described herein are discussed in terms of solder micro-bump structures, it should be understood that the implementations described herein are also applicable to solder bump structures of other sizes, for example, C4 solder bump structures.

FIG. 1is a partial schematic side view of a conventional solder micro-bump connection100formed using implementations known in the art. The solder micro-bump connection100electrically couples a first substrate assembly102awith a second substrate assembly102b. The solder micro-bump connection100comprises a first solder micro-bump assembly110acoupled with a second solder micro-bump assembly110b. It should be noted thatFIG. 1shows the first solder micro-bump assembly110acoupled with a second solder micro-bump assembly110bafter exposure to a solder reflow process to couple the micro-bump assemblies110a,110btogether, thus forming the solder micro-bump connection100.

Each substrate assembly102a,102bmay independently comprise a semiconductor chip or die (e.g., a die configured for flip-chip bonding). Each substrate assembly102a,102bcomprises a layer of metal that is deposited using known techniques to define a conductive bond pad112a,112b. Each conductive bond pad112a,112bmay be in electrical communication with one or more circuit traces (108a,108b) or a plated through-hole, called a “via” (not shown), as is well known in the art.

A passivation layer114a,114bis formed over each substrate102a,102band a portion of each conductive bond pad112a,112b. Each passivation layer114a,114bmay be a silicon nitride layer. The silicon nitride layer may be deposited on the substrate102a,102busing a chemical vapor deposition (CVD) process. An aperture116a,116bis formed in each passivation layer114a,114bto expose at least a portion of each conductive bond pad112a,112b.

A copper pillar120a,120bis formed within each aperture116a,116b. Each copper pillar120a,120bis electrically and mechanically connected to the exposed portion of each conductive bond pad112a,112b. As depicted inFIG. 1, each copper pillar120a,120bextends above a top surface of each passivation layer114a,114b. In some implementations, an adhesion/barrier layer121a,121bis formed over each passivation layer114a,114band within each aperture116a,116bprior to deposition of the conductive pillar120a,120b. In some implementations, a conductive seed layer122a,122bis formed over the adhesion/barrier layer121a,121bprior to deposition of the copper pillar120a,120band the copper pillar120a,120bis formed on the conductive seed layer122a,122b.

A nickel layer124a,124bis formed on each copper pillar120a,120b. Solder micro-bumps (not shown) composed of a lead-free solder including tin and silver (Sn—Ag) are formed on each nickel layer124a,124brespectively. As discussed above,FIG. 1depicts the solder micro-bumps after performance of a solder reflow process and as a result, the solder micro-bump of the first solder micro-bump assembly110aand the second solder micro-bump assembly110bare melted together and depicted as a unitary solder micro-bump structure130.

During performance of the HTS test, the solder from the solder micro-bump structure130migrates onto the copper pillar120a,120bto form tin intermetallic layers134a-d(e.g., nickel-tin (Ni—Sn) and copper-tin (Cu—Sn)). These tin intermetallic layers134a-dare typically nickel rich and thus porous. This porosity allows for the migration of tin from the unitary solder micro-bump structure130to the copper pillar120a,120b. This migration of tin from the unitary solder micro-bump structure130to the copper pillar120a,120bdepletes the amount of solder in the unitary solder micro-bump structure130leading to volumetric voiding and/or cracking defects140.

FIG. 2is a schematic diagram depicting an exemplary die stack200incorporating a solder micro-bump connection202formed according to implementations described herein. The die stack200comprises a first IC die204aand a second IC die204belectrically coupled together by one implementation of the solder micro-bump connection200described herein. Each IC die204a,204bmay be independently selected from programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, processors or other IC logic structures.

FIG. 2also includes an exploded schematic side view of the solder micro-bump connection202. The solder micro-bump connection202comprises a first solder micro-bump assembly210acoupled with a second solder micro-bump assembly210b(collectively210). It should be noted thatFIG. 1shows the first solder micro-bump assembly210acoupled with a second solder micro-bump assembly210bafter exposure to a solder reflow process to couple the micro-bump assemblies210a,210btogether, thus forming the micro-bump connection202.

Each IC die204a,204bmay independently comprise a sheet of insulative material, such as flexible polyimide film or tape, fiberglass, ceramic, silicon, silicon oxide, silicon nitride and like type integrated circuit packaging materials known in the art. Alternatively, each IC die204a,204bmay independently comprise a semiconductor chip or die (e.g., a die configured for flip-chip bonding). Each IC die204a,204bcomprises a layer of metal (e.g., copper, aluminum, gold, silver, nickel, tin, platinum, or a multilayer combination of the aforementioned metals that has been laminated and/or plated on a surface of the IC die204a,204b) that is deposited using known techniques, for example, photolithography, to define a conductive bond pad212a,212b(collectively212). Each conductive bond pad212a,212bmay be in electrical communication with one or more circuit traces (208a,208b) or a plated through-hole, called a “via” (not shown).

A passivation layer214a,214b(collectively214) is formed over each IC die204a,204band a portion of the conductive bond pad212a,212b. Each passivation layer214a,214bmay be a silicon nitride layer. The silicon nitride layer may be deposited using a chemical vapor deposition (CVD) process. An aperture216a,216bis formed in each passivation layer214a,214bto expose at least a portion of each conductive bond pad212a,212b.

A conductive pillar220a,220bis formed within each aperture216a,216bthat is electrically and mechanically connected to the exposed portion of each conductive bond pad212a,212b. Exemplary conductive materials for each conductive pillar220a,220binclude copper, nickel, or other solder materials. Exemplary processes for deposition of the conductive pillar include plating processes such as electrochemical plating (ECP) processes. As depicted inFIG. 2B, the conductive pillar220a,220bextends above a top surface of the passivation layer214a,214b. The conductive pillar220a,220bmay have a thickness from about 5 micrometers to about 20 micrometers, for example, from about 10 micrometers to about 15 micrometers.

In some implementations, an adhesion/barrier layer221a,221bis formed over each passivation layer214a,214band within each aperture216a,216bprior to deposition of each conductive pillar220a,220b. Exemplary adhesion/barrier layer materials include titanium, titanium tungsten (TiW), nickel (Ni), nickel vanadium (NiV), and/or chromium (Cr). Exemplary processes for deposition of the adhesion/barrier layer221a,221binclude electrochemical plating (ECP) processes, electroless plating processes and physical vapor deposition (PVD) processes.

In some implementations, a conductive seed layer222a,222bis formed over each adhesion/barrier layer221a,221bprior to deposition of the conductive pillar220a,220b, and the conductive pillar220a,220bis formed on the conductive seed layer222a,222b. Exemplary conductive seed layer materials include copper and titanium. Exemplary processes for deposition of the conductive seed layer materials include ECP processes, electroless plating processes and PVD processes.

A plating layer is formed on each conductive pillar220a,220b. The plating layer may comprise copper and nickel. In some implementations, the plating layer is a bi-layer structure (seeFIG. 2) comprising a nickel layer224a,224band a copper layer226a,226bformed on the nickel layer224a,224b. In some implementations, the plating layer comprises a copper-nickel alloy (seeFIG. 4).

A nickel layer224a,224bis formed on each conductive pillar220a,220b. Exemplary processes for deposition of the nickel layer include ECP processes and electroless plating processes. The nickel layers224a,224bmay have a thickness from about 1 micrometer to about 10 micrometers, for example from about 3 micrometers to about 5 micrometers.

A copper layer226a,226bis formed on each nickel layer224a,224b. Exemplary processes for deposition of the copper layer226a,226binclude ECP processes. The copper layer226a,226bmay have a thickness from about 1 micrometer to about 10 micrometers, for example, from about 3 micrometers to about 5 micrometers.

Solder micro-bumps (not shown) composed of a lead-free solder including tin and silver (Sn—Ag) are formed on each copper layer226a,226brespectively. Exemplary processes for deposition of the solder micro-bumps included ECP processes. As discussed above,FIG. 2depicts the solder micro-bumps after performance of a solder reflow process and as a result, the solder micro-bump of the first solder micro-bump assembly210aand the second solder micro-bump assembly210bare melted together and depicted as a unitary solder micro-bump structure230.

FIG. 3is a schematic diagram depicting an exemplary implementation of an integrated chip package300incorporating the solder micro-bump connection202ofFIG. 2B. The integrated chip package300includes a plurality of IC dies204a-cconnected by a through silicon via (TSV) interposer304to a package substrate306. The interposer304includes circuitry for electrically connecting the dies204a-cto circuitry of the package substrate306. The circuitry of the interposer304may optionally include transistors.

An interposer underfill material (not shown) may be disposed between the TSV interposer304and the package substrate306to increase the structural integrity of the package substrate to interposer interface. When present, the interposer underfill material typically covers package bumps332, also known as “C4 bumps,” which provide the electrical connection between the circuitry of the interposer304and the circuitry of the package substrate306. In some implementations, the package bumps332may be similar to or the same as solder micro-bump connections202or solder micro-bump connection400, later described with reference toFIG. 4. Although, only six package bumps are illustrated inFIG. 3to minimize drawing clutter, the number of package bumps may be increased or decreased to meet design needs. The package substrate306may be mounted and connected to a printed circuit board (PCB), utilizing solder balls, wire bonding or other suitable technique. The PCB is not shown inFIG. 3.

The IC dies204b,204care mounted to one or more surfaces of the interposer304. The IC dies204b,204cmay be programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, processors or other IC logic structures. In the implementation depicted inFIG. 3, the IC dies204b,204care mounted to a top surface320of the interposer304by micro-bumps330. In some implementations, the micro-bumps330may be similar to or the same as solder micro-bump connections202or solder micro-bump connection400. Although, only five micro bumps, coupling IC die204band IC die204cto the interposer304, are shown to minimize drawing clutter, the number of package bumps may be increased or decreased to meet design needs. The micro-bumps330electrically connect the circuitry of the IC dies204b,204cto circuitry of the interposer304. The circuitry of the interposer304connects the micro-bumps330to selective package bumps332, and hence, selective circuitry of the IC dies204a-cto the package substrate306, to enable communication of the IC dies204a-cwith the PCB after the integrated chip package300is mounted.

The IC dies204a-cmay be disposed on the interposer304in any suitable arrangement. For example, the IC dies204a-cmay be disposed on a top surface320of the interposer304in a 3-D array. Optionally, one or more IC dies204a-cmay be stacked on a bottom surface322of the interposer304.

FIG. 4is a partial schematic side view of a solder micro-bump connection400formed according to implementations described herein. The solder micro-bump connection400may be used in place of solder micro-bump connection202depicted inFIG. 2. The solder micro-bump connection400comprises a first solder micro-bump assembly410acoupled with a second solder micro-bump assembly410b(collectively410). It should be noted thatFIG. 4shows the first solder micro-bump assembly410acoupled with a second solder micro-bump assembly410bafter exposure to a solder reflow process to couple the micro-bump assemblies410a,410btogether, thus forming the micro-bump connection400.

The solder micro-bump connection400is similar to the solder micro-bump connection200except that the plating layers (e.g., nickel layers224a,224band the copper layers226a,226b) of solder micro-bump connection200have been replaced by copper-nickel alloy layers424a,424b(collectively424). Exemplary processes for deposition of the copper-nickel alloy layers424a,424binclude electrochemical plating (ECP) processes and electroless plating processes. The copper-nickel alloy layers424a,424bmay have a thickness from about 0.5 μm to about 5 μm. Not to be bound by theory but it is believed that inclusion of the copper-nickel alloy layer suppresses the IMC reaction thus reducing the depletion of solder and minimizing the undesirable void formation that leads to voiding or cracking defects within the solder micro-bump joint.

FIGS. 5A-5Iare schematic cross-sectional views illustrating a method for solder micro-bump connection formed according to implementations described herein.FIG. 6is a flow diagram illustrating one implementation of a method600for fabricating the solder micro-bump connection ofFIGS. 5A-5I.

At block610, a first passivation layer214is formed on a substrate as shown inFIG. 5A. The substrate204may comprise a sheet of insulative material, such as flexible polyimide film or tape, fiberglass, ceramic, silicon, and like type integrated circuit packaging materials known in the art. Alternatively, the substrate204may comprise a semiconductor chip or die (e.g., a die configured for flip-chip bonding). The substrate204comprises a layer of metal (e.g., copper, aluminum, gold, silver, nickel, tin, platinum, or a multilayer combination of the aforementioned metals that has been laminated and/or plated on a surface of the substrate204) that is patterned using known techniques, for example, photolithography, to define a conductive bond pad212. The conductive bond pad212may be in electrical communication with one or more circuit traces (not shown) or a plated through-hole, called a “via” (not shown).

A passivation layer214is formed over the substrate204and a portion of the conductive bond pad212. Each passivation layer214may be a silicon nitride layer. The silicon nitride layer may be deposited using a chemical vapor deposition (CVD) process. An aperture216is formed in each passivation layer214to expose at least a portion of each conductive bond pad212as shown inFIG. 5A.

Optionally, at block615, a conductive seed layer222is formed over the adhesion/barrier layer221if present as shown inFIG. 5B.

At block620, a patterned mask510defining an aperture512is formed over the conductive seed layer222if present as shown inFIG. 5C. The aperture512exposes a portion of the conductive seed layer222. The patterned mask510may comprise a photoresist material such as an acrylic or a polyimide plastic or, alternatively, an epoxy resin that is silk screened or spin-coated on the substrate204. The photoresist material may be patterned using known photolithography techniques to define the aperture512.

At block625, a conductive pillar220is formed in the aperture512as shown inFIG. 5D. At block630, a plating layer comprising copper and nickel is formed on the conductive pillar220as shown inFIG. 5E. In some implementations, the plating layer includes multiple layers. As shown inFIG. 5E, the plating layer is a bi-layer structure comprising a nickel layer224formed on the conductive pillar220and a copper layer226is formed on the nickel layer224.

At block635, a micro-bump230is formed on the plating layer. As shown inFIG. 5E, the micro-bump230is formed on the nickel layer224.

At block640, the patterned mask510is removed to expose a portion of the conductive seed layer222as shown inFIG. 5F. The patterned mask510may be removed using known photoresist removal techniques.

At block645, the exposed portions of the conductive seed layer222are removed to expose portions of the adhesion layer221as shown inFIG. 5G. The exposed portions of the conductive seed layer222may be removed using known etching techniques, for example, wet etching techniques.

At block650, the exposed portions of the adhesion layer221are removed as shown inFIG. 5H. The exposed portions of the adhesion layer221may be removed using known etching techniques, for example, wet etching techniques.

At block655the micro-bump230is exposed to a solder reflow process as shown inFIG. 5I. At block660, the substrate204is mounted to a second substrate (not shown) utilizing the micro-bump230. The micro-bump230may be solder reflowed to an area of a second substrate to form a mechanical and electrical connection between the substrate204and the second substrate (not shown). In some implementations, the micro-bump230may be solder reflowed to a bond pad of the second substrate. In some implementations, the micro-bump230may be solder reflowed to a corresponding micro-bump of the second substrate. In some implementations, the micro-bump230may be solder reflowed to a corresponding conductive pillar of the second substrate. After mounting, underfill material may be wicked between the substrate204and the second substrate. After curing, the die underfill material provides structural rigidity between the substrate204and the second substrate.

Improved solder joints and methods of forming improved solder joints for integrated circuits have been provided. In some implementations, the improved solder joints described herein have been exposed to HTS testing for over 2,000 hours without experiencing the cracking defects present in conventionally known solder joints after HTS testing between 500 and 700 hours.