Apparatus for producing single crystals

A process and apparatus for producing silicon single crystals with excellent dielectric strength of gate oxide films by adjusting the temperature gradient of the pulled-up silicon single crystal without loss of its rate of pulling. The process of producing silicon single crystals by pulling up the single crystal from a melt of material of the single crystal imposes a certain average temperature gradient on the grown single crystal while it is still at high temperature. The apparatus is provided with a heating element outside a crucible and pulling shaft with which a single crystal is pulled up from the melt of the material in the crucible. The ratio of length h of the heating element to the inside diameter .phi. of the crucible is adjusted so as to be between 0.2 and 0.8 whereby the temperature gradient can be maintained below 2.5.degree. C./mm.

FIELD OF THE INVENTION 
The present invention relates to a process and an apparatus for producing 
single crystals, specifically silicon single crystals which have excellent 
dielectric strength of gate oxide films. 
DESCRIPTION OF THE PRIOR ART 
Among a number of methods, Czochralski process has been widely applied to 
production of silicon single crystals because it is a feasible industrial 
method for producing single crystals. 
FIG. 7 is a schematic cross section to show how Czochralski process is 
realized, in which (1) indicates a crucible. A heating element (2) is 
installed outside the crucible (1), the crucible contains the melt (4) of 
the material of the single crystal which is the original material for 
forming the single crystal melted by the heating element. The lower end of 
the seed crystal held with a pulling shaft or a pulling wire is lowered to 
contact the surface of the melt, then the pulled crystal (3) grows and 
becomes solidified out of the melt at the lower end of the crystal. 
Recently as the degree of integration of MOS devices increases, 
requirements for various characteristics have been imposed on silicon 
wafers, which are fabricated from the pulled single crystals. The 
requirement of high reliability for the gate oxide films is strict, 
because the intensity of the electric field applied to the films as stress 
is enhanced under a constant single source voltage, while thinning of the 
gate oxide films advances with decreasing dimensions of the integrated 
circuits for DRAM. 
Dielectric strength of gate oxide films is one of the material 
characteristics which has decisive importance upon the reliability of the 
product. Therefore, development of the single crystals and their 
production technology is urgently needed. 
Two methods have been proposed for the process of producing single crystals 
which have excellent dielectric strength of gate oxide films. 
First, a process for producing silicon single crystals was developed using 
Czochralski technique with a limit of 0.8 mm/min or less for growing the 
single crystal in order to improve dielectric strength of gate oxide films 
of the crystal (See Laid-open (Kokai) No. 2-267195). As a result, in 
accordance with this method, when the dielectric strength of gate oxide 
films is evaluated in terms of the voltage ramping method, which will be 
explained later, the ratio of the number of acceptable MOB diodes is 
beyond 60%; if the average strength of the electric field imposed on the 
oxide films formed on the silicon wafer is above 8.0 MV/cm, no dielectric 
breakdown of insulation of the oxide films occurs. 
However, the rate of crystal growth is equivalent to the rate of pulling up 
of the silicon single crystal and is directly connected to the rate of 
producing the silicon crystal. The rate of pulling up silicon single 
crystals in industrial production is generally greater than 1.0 mm/min, 
and reducing the rate of pulling up, as is indicated in the method 
mentioned above, means a sharp lowering of productivity of silicon single 
crystals. Also it is a matter of concern in the generation of oxidation 
induced stacking faults in the silicon single crystal which have a low 
rate of pulling up below 0.8 mm/min. 
Secondly, there is a report about the effects of the thermal history in the 
process of pulling up single crystals in accordance with Czochralski 
process upon dielectric strength of oxide films (See 30P-ZD-17, The Japan 
Society of Applied Physics Extended Abstracts, The 39th Autumn Meeting, 
1992). 
According to this report, the dielectric strength of gate oxide films of a 
silicon wafer is largely dependent on the rate of crystal growth. It is 
not dominated, however, by the rate of crystal growth solely, but is 
consequently dependent upon the varying thermal history during the crystal 
growth. It has been reported also that the nuclei of imperfections in 
crystals, which reduce dielectric strength of gate oxide films, are formed 
during the crystal growth by pulling, the nuclei contracting in the high 
temperature range (above 1250.degree. C.) and grown in the low temperature 
range (below 1100.degree. C.). Here, the term, thermal history, refers to 
the heat patterns to which the single crystal is exposed during the 
cooling stage from the temperature of solidification while the single 
crystal is pulled up. It is said that the dielectric strength of the 
silicon wafer can be improved by adjusting the thermal history of the 
silicon single crystal during its growth by crystal pulling. 
It is true that the nuclei imperfections may be contracted, extinguished, 
or diminished by slow cooling the crystal at high temperature. In the 
above mentioned report, adjustment of the cooling rate is attained by 
interrupting pulling up of the single crystal to stop its growth and to 
hold it as is for 30 minutes, and then the pulling is resumed so that the 
growth of the single crystal can continue. This way of adjusting the 
thermal history is a feasible measure for an experimental analysis, but 
cannot be used for industrial production of silicon single crystals. The 
problem with the known process of producing single crystals which have 
excellent dielectric strength of gate oxide films has been that it was not 
applicable to industrial production of silicon single crystals. 
SUMMARY OF THE INVENTION 
The objects of this invention are the process and the apparatus which 
enable production of silicon single crystals with excellent dielectric 
strength of gate oxide films by adjusting the temperature gradient in the 
silicon single crystal to improve the thermal history to which the silicon 
single crystal is exposed, without an extreme reduction of the rate of 
pulling up. 
This invention provides a method for producing silicon single crystals and 
an apparatus for producing silicon single crystals. 
According to the method of the invention, a single crystal is grown by 
pulling up the crystal from a melt of original material for the crystal 
contained in a crucible and heated to form the melt by a heating element 
installed outside the crucible. The method is characterized by giving a 
prescribed average temperature gradient to the grown single crystal while 
it is still at a high temperature range in order to obtain a silicon 
single crystal which has excellent dielectric strength of gate oxide 
films. 
The apparatus according to the invention for producing silicon single 
crystals with excellent dielectric strength of gate oxide films includes a 
heating element outside a crucible and a pulling mechanism to pull up the 
single crystal from a melt of material for the crystal contained in the 
crucible, in which a ratio of a length of the heating element (h) to an 
inside diameter of the crucible (.phi.) is characterized by being between 
0.2 and 0.8.

DETAILED DESCRIPTION OF THE INVENTION 
This inventor investigated in detail the method of adjusting the thermal 
history of the silicon single crystal during the crystal growth by pulling 
up the crystal in order to accomplish the process of producing silicon 
single crystal which has excellent dielectric strength of gate oxide 
films. 
A rate of pulling of silicon single crystal larger than a certain rate is 
required in order to produce the silicon single crystal on an industrial 
scale. The thermal history to cool slowly at a high temperature range 
under certain conditions of pulling so that defect nuclei shrink and 
disappear can be realized by adjusting the temperature gradient at a high 
temperature range (above 1250.degree. C.) when the crystal is cooled down 
from the temperature of solidification. The temperature gradient is 
related to the cooling rate and shows the temperature difference 
(.degree.C.) per a unit length (1 mm) of the single crystal, and is 
represented by the average temperature gradient in .degree.C./mm for a 
specific temperature range between the beginning and the end of cooling. 
FIG. 2 schematically shows the pulled crystal rod (3) relative to the melt 
(4) and to the solid liquid interface. x.sub.o in FIG. 2 is the interface 
on an X--X central axis is the rod which shows where the crystal begins to 
solidify. x.sub.1 and x.sub.2 are locations in the crystal rod on the X--X 
axis, and the distances from tee interface x.sub.1 &lt;x.sub.2. 
FIG. 3 shows the results of simulation of the temperature distribution 
along the X--X axis in the pulled crystal rod (3) with different 
temperature gradients 1 to 3 for a constant rate of pulling. The 
temperature gradient immediately below the solidification temperature 
(1410.degree. C.) is relatively large and tends to decrease with the 
progress of pulling. The temperature gradient varies with the temperature 
of the pulled crystal rod or with the distance from the interface, and it 
is convenient to use the average temperature gradient (.degree.C./mm) in 
analysis of the thermal history. The average temperature gradients 
.degree.C./mm here have been set to be 1&lt;2&lt;3. 
It can be seen from FIG. 3 that the thermal history of cooling in the high 
temperature range can be realized by adjusting the temperature gradient. 
At location x.sub.1, the temperature at gradient 1 is higher than 
1250.degree. C. and the temperature at gradient 3 is already as low as 
about 1100.degree. C. 
Consequently, a thermal history of slow cooling at a high temperature range 
is realized with the temperature gradient 1 compared with the temperature 
gradient 3. By adjusting the temperature gradient appropriately the nuclei 
of imperfections in crystals disappear which adversely effects the 
dielectric strength of gate oxide films. 
With the apparatus for pulling crystals which is constituted of the 
crucible (1) and the heating element (2) as shown in FIG. 1, selecting the 
inside diameter of the crucible and the dimensions of the heating element 
allows adjustment of the average temperature gradient and variation of the 
thermal history. 
The knowledge has been derived based on extensive investigation but at this 
time a theoretical basis has not been established. If, however, the 
position of installing the heating element (the relative position to the 
surface of the melt in the crucible) is properly selected and a short 
length h of the heating element relative to the crucible diameter .phi. is 
chosen, the temperature in the melt (4) about the solidification 
temperature of the crystal can be raised and the average temperature 
gradient in the solidified crystal can be lowered, and the temperature of 
the pulled crystal (3) can be maintained at high temperature above 
1250.degree. C. for a long period of time. Presumably, the reason is that, 
if the length h of the heating element is shorter relative to the crucible 
diameter .phi., the radiation flux to the melt (4) from the heating 
element (2) increases. 
FIG. 1 illustrates a vertical cross section of a preferable embodiment of 
the apparatus in accordance with this invention. It is preferable to have 
the upper edge S of the heating element within the range between +100 mm 
to -100 mm relative to the surface of the melt (4). The height of the 
upper edge S of the heating element is represented by positive values for 
the position above the surface of the melt and negative values for that 
below the surface of the melt. The upper limit +100 mm of the upper edge S 
of the heating element has been determined to prevent too large of a 
temperature variation of the melt caused by a convection of the melt, and 
the lower limit -100 mm has been determined to prevent solidification in 
the upper edge of the crucible. 
If the heating element (2) with a determined length relative to the 
crucible diameter .phi. is placed near the surface of the melt which is 
the location of solidification, the temperature of the melt (4) near the 
location of solidification of the crystal is raised, and the average 
temperature gradient in the pulled crystal (3) in the high temperature 
range can be reduced. 
FIG. 4 shows the thermal histories of the pulled single crystals when the 
ratio of the length h of the heating element to the crucible diameter 
.phi., h/.phi. is varied with a constant level of the upper edges of the 
crucible and with a constant input of the electric power. The thermal 
history is measured with the thermocouple vertically inserted into the 
pulled crystal. 
The distance from the interface between the solid and the liquid in FIG. 4 
represents the lapse of time after solidification of the single crystal. 
Since the rate of pulling the crystal is kept constant, a longer length 
from the interface between the solid and the liquid represents a longer 
time after the solidification of the single crystal. As h/.phi. is 
reduced, the average temperature gradient of the pulled crystal at a high 
temperature range is reduced. Consequently, the pulled crystal is 
maintained at a high temperature range for a long period of time. For 
h/.phi.=0.8 the average temperature gradient between the solidification 
temperature and 1250.degree. C. is 2.5.degree. C./min. 
FIG. 5 shows the acceptance rate of the dielectric strength of oxide films 
of silicon wafers evaluated by a voltage ramping method. With h/.phi. 
below 0.8, a favorable result of the acceptance ratio above 70% has been 
obtained. 
It can be seen from FIG. 4 and FIG. 5 that favorable states are realized as 
to dielectric strength of gate oxide films for smaller h/.phi.; however, 
its lower limit is set at h/.phi.=0.2 in this invention. The test results 
by this inventor indicates that smaller h/.phi. tends to create a 
non-uniform temperature distribution in the melt, and the lower limit is 
selected in consideration of the pulling rate of the crystal. If a certain 
degree of fluctuation in the temperature of the melt occurs, a stable 
crystal growth can be achieved by slowing down the pulling rate as to the 
growth of the single crystal. However, maintaining the rate of pulling 
above 0.8 mm/min is required in order to industrially produce silicon 
single crystals with the quality which are free from the problems of 
oxidation induced stacking faults. Thus, the lower limit of h/.phi. has 
been set at 0.2 as the required limit for the stable growth of the single 
crystal with the pulling rate above 0.8 m/min. 
EXAMPLES 
An embodiment of the process of growing single crystals in accordance with 
this invention is shown in FIG. 1. The notation used to label the drawing 
in FIG. 1 is the same in previous drawings. 
FIG. 1 shows a schematic cross section of the apparatus to carry out the 
process of this invention. A crucible (1) consists of a double-layered 
structure, of which the inside is a quartz crucible (1a), and the outside 
is a graphite crucible (1b). This crucible is placed upon a crucible shaft 
(6). The crucible shaft is equipped with the function to lift the crucible 
as well as to rotate it. 
A chamber (8) is a cylindrical vacuum vessel with a pulling shaft (7) of 
the single crystal located along its center line, and the crucible is 
placed at the center of the chamber. A heating element (2) which consists 
of resistance elements is located outside and surrounds the crucible. In 
addition, the heating element is surrounded by a heat insulating cylinder 
(5). The heating element is equipped with a lifting device, although it is 
not shown in the drawing. The relationship between the level of the melt 
surface in the crucible and the vertical position of the heating element 
can be adjusted in terms of the relative vertical position between the 
crucible and the heating element. 
The pulling shaft (7) which can be lifted and lowered is installed above 
the crucible through the pulling chamber (9) connected to the upper part 
of the chamber (8), and the pulled crystal (3) is connected to the lower 
end of the pulling shaft. 
The pulled crystal is rotated and pulled up as the pulling shaft is rotated 
and pulled; a single crystal grows at its lower end where it contacts the 
surface of the melt (4). 
The pulled single crystal was a P type silicon single crystal of 6 inch 
diameter with &lt;100&gt; crystallographic orientation. The crucible used was 
406 mm (16 inch) in diameter and 365 mm (14 inch) in height. The heating 
element used for this was 150 mm long, with h/.phi.=0.37. Other variables 
are h/.phi. from 0.20 to 1.50, as shown in Table 1. 
As a pretreatment for crystal growing solid crystalline material in blocks, 
chips, and granular forms of crystalline silicon were charged in the 
crucible in preparation for crystal growing. The quantity of the material 
weighed 65 kg so that a 6 inch single crystal of an appropriate length 
could be pulled up. 
After the solid material for crystal growing was melted in the crucible, 
the chamber was filled with argon (Ar) to maintain an atmospheric pressure 
of 10 Torr in the chamber. Then the heating element was raised to a 
position where the upper end S of the heating element was between -150 mm 
and +150 mm; namely the heating element was adjustable to be situated near 
the melt surface, and the single crystal was pulled up. Table 1 shows the 
conditions of processing in accordance with this invention and other 
examples for comparison. 
The silicon single crystals were processed through industrial steps 
commonly required such as slicing and polishing. MOB diodes were mounted 
on the surface in order to evaluate the dielectric strength of gate oxide 
films of the wafer. In mounting a MOB diode, a silicon wafer was coated 
with oxide films, and then gate metallization was carried out. Coating the 
wafer with oxide films was carried out by heating the wafer in an oxidized 
atmosphere. The film used was a 25 nm thick dry oxide film. The gate was 
formed with phosphorus (P)-doped polycrystalline silicon, the area of 
which was 8 mm.sup.2. 
A voltage ramping method, which is an electric method to evaluate an oxide 
film, was used for evaluation of the oxide films of this silicon wafer. 
FIG. 6 schematically shows the measurement by the voltage ramping method. 
Increments of electric voltage were applied on the silicon wafer (11) 
mounted with a MOS diode, and the voltage was raised by increments of one 
volt by adjusting the direct current source (12), The leakage current is 
monitored with a current-meter (13). Dielectric strength of gate oxide 
films is evaluated by taking 100 to 150 measurement points within a 
silicon wafer surface, observing the dielectric breakdown at each point, 
and determining the acceptability of the silicon wafer. If a leaking 
current of 12.5 .mu.A/cm.sup.2 is measured in the dielectric strength, it 
is determined that a breakdown has occurred. If a measurement point has 
broken down at an average electric field less than 8 Mv/cm, that point is 
rejected and the ratio of acceptable points covering all the wafer surface 
represents the acceptance ratio. Generally speaking, the dielectric 
strength of gate oxide films depends on the acceptance ratio of the 
silicon wafers. 
Results of measurements are shown in TABLE 1. 
TABLE 1 
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the comparative 
Crystal Ratio, Height of 
Rate, 
pulling heater length 
upper edge 
accept. 
Rod rate to crucible dia. 
of heater 
DSO+ 
No. mm/min h/.phi. mm % 
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Example in accordane with this invention 
A 0.8 0.20 0 85 
B 0.9 0.37 0 80 
C 0.9 0.37 +100 85 
D 0.9 0.37 +150** 70 
E 1.0 0.50 0 80 
F 1.0 0.50 -100 80 
G 1.0 0.50 -150** 60 
H 1.0 0.80 0 70 
I 1.0 0.80 -100 70 
J 1.0 0.80 -150** 55 
Other example 
K 1.0 1.00 0 50 
L 1.0 1.00 -100 45 
M 1.0 1.50 0 40 
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**indicates that the upper edge is out of the preferable range. 
DSO+ stands for dielectric strength of gate oxide films 
It can be seen from TABLE 1 that the acceptance ratio for examples for 
comparison is low; however, the acceptance ratio of single crystals in 
accordance with this invention is remarkably high. 
There had been no occurrence of problems with quality such as oxidation 
induced stacking fault in any of the single crystals. 
As has been explained so far, production of silicon single crystals which 
have excellent dielectric strength of gate oxide films can be carried out. 
The forthcoming demand for better reliability of the gate oxide films 
accompanied with higher integration of MOS devices can be coped with the 
process and using the device in accordance with this invention without 
loss of productivity of single crystals.