Mechanism to provide test access to third-party macro circuits embedded in an ASIC (application-specific integrated circuit)

Novel structures and testing methods for the FPGAs (Field-Programmable Gate Arrays) embedded in an ASIC (Application-Specific Integrated Circuit). Basically, a shift/interface system is coupled between the FPGAs and the ASIC. During normal operation, the shift/interface system electrically couples the FPGAs to the ASIC. During the testing of the FPGAs, the shift/interface system scans in FPGA test data in series, then feeds the FPGA test data to the FPGAs, then receives FPGA response data from the FPGAs, and then scans out the FPGA response data in series. During the testing of the ASIC, the shift/interface system scans in ASIC test data in series, then feeds the ASIC test data to the ASIC, then receives ASIC response data from the ASIC, and then scans out the ASIC response data in series.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to FPGAs (Field-Programmable Gate Arrays), and more particularly, to testing of FPGAs embedded in an ASIC (Application-Specific Integrated Circuit).

2. Related Art

An FPGA (Field-Programmable Gate Array) and an ASIC (Application-Specific Integrated Circuit) can be combined to form a hybrid IC (integrated circuit) so that the hybrid IC can have the advantages of both the FPGA (design flexibility) and the ASIC (low power, high performance, and low test pin count).

Testing a standalone FPGA typically consists of exhaustively testing the logic blocks and interconnect resources of the FPGA through a series of structural tests. These structural tests configure the standalone FPGA in different ways and require access to all input/output (I/O) pins of the standalone FPGA. Similarly, testing the FPGA in the hybrid IC consists of essentially the same structural tests. The problem is how to access all I/O pins of the FPGA in the hybrid IC given the low test pin count of the hybrid IC.

Therefore, there is a need for a novel structure and testing method for a low test pin count, hybrid IC comprising an ASIC and multiple FPGAs.

SUMMARY OF THE INVENTION

The present invention provides a digital system, comprising (a) N macro circuits, N being a positive integer; (b) an application-specific integrated circuit (ASIC); and (c) a shift/interface system being coupled to the N macro circuits and the ASIC, wherein, in response to the N macro circuits and the ASIC being in normal operation, the shift/interface system electrically couples each macro circuit of the N macro circuits to the ASIC, wherein, in response to the N macro circuits being tested, the shift/interface system is further configured to scan-in macro circuit test data in series, then to feed the macro circuit test data to the N macro circuits, then to receive macro circuit response data from the N macro circuits, and then to scan-out the macro circuit response data in series, and wherein, in response to the ASIC being tested, the shift/interface system is further configured to scan-in ASIC test data in series, then to feed the ASIC test data to the ASIC, then to receive ASIC response data from the ASIC, and then to scan-out the ASIC response data in series.

The present invention also provides a system testing and operating method, comprising the steps of (a) providing a digital system including (i) N macro circuits, (ii) an application-specific integrated circuit (ASIC), and (iii) a shift/interface system being coupled to the N macro circuits and the ASIC; (b) in response to the N macro circuits and the ASIC being in normal operation, using the shift/interface system to electrically couple each macro circuit of the N macro circuits to the ASIC; (c) in response to the N macro circuits being tested, (i) scanning-in macro circuit test data in series into the shift/interface system, (ii) feeding the macro circuit test data from the shift/interface system to the N macro circuits, (iii) using the shift/interface system to receive macro circuit response data from the N macro circuits, and (iv) scanning-out the macro circuit response data in series from the shift/interface system; and (d) in response to the ASIC being tested, (i) scanning-in ASIC test data in series into the shift/interface system, (ii) feeding the ASIC test data from the shift/interface system to the ASIC, (iii) using the shift/interface system to receive ASIC response data from the ASIC, and (iv) scanning-out the ASIC response data in series from the shift/interface system.

The present invention also provides a system testing method, comprising the steps of (a) providing a digital system including (i) a macro circuit, (ii) an application-specific integrated circuit (ASIC), and (iii) a shift/interface system being coupled to the macro circuit and the ASIC, and (iv) a multiple-input signature register (MISR) including K MISR stages, K being a positive integer, the K MISR stages being coupled together, being coupled to K output pins of the macro circuit, and being coupled to K shift/interface circuits of the shift/interface system, wherein the K shift/interface circuits are coupled together; (b) scanning-in macro circuit test data in series into the shift/interface system; (c) transmitting the macro circuit test data from the shift/interface system to the macro circuit in parallel; (d) using the macro circuit to process the macro circuit test data into macro circuit response data and to present the macro circuit response data at the K output pins of the macro circuit; (e) transmitting the macro circuit response data from the K output pins of the macro circuit to the K MISR stages; (f) using the MISR to process the macro circuit response data into a macro circuit response signature and send the macro circuit response signature to the K shift/interface circuits; and (g) scanning the macro circuit response signature out of the K shift/interface circuits in series.

The present invention provides a novel structure and testing method for a low test pin count, hybrid IC comprising an ASIC and multiple FPGAs.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1Aillustrates a testing system100comprising an IC (integrated circuit)110and a tester120, in accordance with embodiments of the present invention. In one embodiment, illustratively, the IC110can comprise FPGAs (Field-Programmable Gate Arrays)130aand130b, MISRs (Multiple-Input Signature Registers)140aand140b, a shift/interface system150, and an ASIC (Application-Specific Integrated Circuit)160. In general, the IC110can comprise M FPGAs similar to the FPGAs130aand130b, and M MISRs similar to the MISRs140aand140b(M is positive integer).

The FPGA130ais coupled to the shift/interface system150via connections133aand to the MISR140avia connections135a. The MISR140ais coupled to the shift/interface system150via connections145a. Similarly, the FPGA130bis coupled to the shift/interface system150via connections133band to the MISR140bvia connections135b. The MISR140bis coupled to the shift/interface system150via connections145b. The shift/interface system150is coupled to the ASIC160via connections155and to the tester120via connections157. The ASIC160is coupled to the tester120via connections165.

In one embodiment, during the normal operation of the IC110(i.e., the ASIC160and the FPGAs130aand130bare in normal operation), the shift/interface system150can be configured to (a) electrically couple the FPGAs130ato the ASIC160via the connections133aand155and (b) electrically couple the FPGAs130bto the ASIC160via the connections133band155. In other words, during the normal operation of the IC110, the shift/interface system150is transparent to the FPGAs130aand130band the ASIC160.

In one embodiment, a structural test180(FIG. 1B) of the FPGAs130aand130bcan be carried out as follows. With reference toFIGS. 1A and 1B, illustratively, in step182, the tester120can place the FPGAs130aand130bin a safe (i.e., shut-off) state by sending a stability signal to both the FPGAs130aand130b. As a result, random signals on the inputs (not shown) of the FPGAs130aand130bwould not place the FPGAs130aand130binto an unknown or unstable state. In one embodiment, the tester120can send the stability signal to both the FPGAs130aand130bthrough the connections157, the shift/interface system150, and then the connections133aand133b, respectively.

Next, in step184, with the FPGAs130aand130bbeing placed in the safe state, in one embodiment, the tester120can make a first data shift of a first bitstream comprising first FPGA test data and second FPGA test data into the shift/interface system150via connection157. The first data shift is carried out such that, at the end of the first data shift, the first FPGA test data is applied to the input pins of the FPGA130avia the connections133a, and the second FPGA test data is applied to the input pins of the FPGA130bvia the connections133b.

Next, in step186, in one embodiment, the tester120can send an operation signal to the FPGAs130aand130bso as to place the FPGAs130aand130bin an operation state. In one embodiment, the tester120can send the operation signal to the FPGAs130aand130bby deactivating the stability signal.

Next, in step188, in one embodiment, the tester120can send configuration signals to the FPGAs130aand130bso as to configure the FPGAs130aand130bto operate on the first and second FPGA test data, respectively. In one embodiment, the tester120can send the configuration signals to the FPGAs130aand130bthrough the connections157, the shift/interface system150, and then the connections133aand133b, respectively.

Next, in step190, in one embodiment, the FPGA130acan send a first reset signal to the MISR140avia the connections135aso as to reset the MISR140a. In one embodiment, the FPGA130bcan send a second reset signal to the MISR140bvia the connections135bso as to reset the MISR140b.

Next, in step192, in one embodiment, the FPGAs130aand130band the MISRs140aand140bare clocked N times (N can be selected based on the design of the FPGAs130aand130b). In one embodiment, the FPGAs130aand130band the MISRs140aand140bcan be clocked by the same clock signal.

In one embodiment, for each of the N clocks, the FPGA130agenerates a different FPGA response to both the MISR140a(via connections135a) and the shift/interface system150(via connections133a). At the shift/interface system150, the current FPGA response overrides and replaces the previous FPGA response. But, at the MISR140a, the current FPGA response is combined with all previous FPGA responses from the FPGA130asuch that after the N clocks, the MISR140acombines all the N FPGA responses from the FPGA130ainto a first response signature. In one embodiment, after the N clocks, the FPGA130acan also send its configuration status from its configuration status outputs to the shift/interface system150via connections133a.

Similarly, for each of the N clocks, the FPGA130bgenerates a different FPGA response to both the MISR140b(via connections135b) and the shift/interface system150(via connections133b). At the shift/interface system150, the current FPGA response overrides and replaces the previous FPGA response. But, at the MISR140b, the current FPGA response is combined with all previous responses such that after the N clocks, the MISR140bcombines all the N responses from the FPGA130binto a second response signature. In one embodiment, after the N clocks, the FPGA130bcan also send its configuration status from its configuration status outputs to the shift/interface system150via connections133b.

Next, in step194, in one embodiment, the tester120can send the stability signal to both the FPGAs130aand130bto place the FPGAs130aand130bin the safe state.

Next, in step196, in one embodiment, the shift/interface system150can make a second data shift of a second bitstream comprising the first and second response signatures and the configuration status of the FPGA130aand130bout of the shift/interface system150to the tester120via connections157.

Next, in one embodiment, one or more structural test of the FPGAs130aand130bsimilar to the structural test180described supra can be performed.

FIGS. 2A-2E, respectively, illustrate five shift/interface circuits151a,151b,151c,151d, and151erepresentative of five different types of shift/interface circuits of the shift/interface system150ofFIG. 1A(hereafter also referred to as types151a,151b,151c,151d, and151e), in accordance with embodiments of the present invention. Hereafter, a shift/interface circuit of any of the five types above can be referred to as the shift/interface circuit151.

In one embodiment, the shift/interface system150ofFIG. 1Acan comprise one chain of multiple shift/interface circuits151each of which can be of any one of the five types151a,151b,151c,151d, and151e(FIGS. 2A,2B,2C,2D, and2E, respectively). For example, one shift/interface circuit151in the chain can be of type151a(FIG. 2A), while the next shift/interface circuit151in the chain can be of type151c(FIG. 2C).

In one embodiment, the chain can have none, one, or more shift/interface circuits151of each type of the five types151a,151b,151c,151d, and151e(FIGS. 2A,2B,2C,2D, and2E, respectively).

In one embodiment, the shift/interface circuits151of a same type are arranged electrically next to each other in the chain. For example, all shift/interface circuits151of type151a(FIG. 2A) of the chain can be placed electrically next to each other in the chain (two shift/interface circuits151are electrically next to each other in the chain if an output of one of the two shift/interface circuits151is electrically and directly coupled to an input of the other).

In one embodiment, each shift/interface circuits151in the chain, regardless of type, comprises a shift/store unit210and a multiplexer (i.e., MUX)220(FIGS. 2A-2E). In one embodiment, the shift/store unit210can function as a one-bit shift register. That is, in a store mode, the shift/store unit210can store a bit applied to its DI input and place the bit on its SO output. In a shift mode, for each shift, the shift/store unit210can shift its stored bit at its SO output to the next shift/store unit and receive a bit through its SI input from the immediately preceding shift/store unit.

In one embodiment, the SI input of the shift/store unit210of each shift/interface circuit151in the chain is electrically and directly coupled to the SO output of the shift/store unit210of the previous shift/interface circuit151in the chain. Exception is for the first shift/interface circuit151in the chain whose SI input (i.e., the SI input of its shift/store unit210) is electrically coupled to the tester120via connections157. Exception is also for the last shift/interface circuit151in the chain whose SO output (i.e., the SO output of its shift/store unit210) is also electrically coupled to the tester120via connections157.

The following discussion will show how each type of the five types151a,151b,151c,151d, and151e(FIGS. 2A,2B,2C,2D, and2E, respectively) helps in the structural test180(FIG. 1B).

FIG. 2Aillustrates the shift/interface circuit151a(i.e., a shift/interface circuit151of type151a) that can be used in the shift/interface system150ofFIG. 1A, in accordance with embodiments of the present invention. With reference toFIGS. 1A and 2A, for type151a, in one embodiment, the MUX220can have its first and second inputs electrically coupled to an output of the ASIC160(via connection155a, a part of connections155ofFIG. 1A) and the SO output of the shift/store unit210, respectively. The MUX220can have its output electrically coupled to an input of the FPGA130a(via connection136a, a part of connections133aofFIG. 1A) and to the DI input of the shift/store unit210. The MUX220can have its control input receiving a Test-FPGA signal from the tester120via connection157a, a part of connections157ofFIG. 1A. In short, the output of the ASIC160is coupled to the input of the FPGA130avia the shift/interface circuit151of type151a.

In one embodiment, assume that the FPGA130ahas P functional data inputs that need to be directly coupled one-to-one to P functional data outputs of the ASIC160during the normal operation of the IC110ofFIG. 1A(P is a positive integer). As a result, P shift/interface circuits151of type151acan be used in the chain to couple the P functional data outputs of the ASIC160to the P functional data inputs of the FPGA130a.

During the normal operation of the IC110, with reference toFIGS. 1A and 2A, the tester120can pull the Test-FPGA signal low (i.e.,0) to cause the P MUXes220of the P shift/interface circuits151of type151ato electrically couple the P functional data outputs of the ASIC160to the P functional data inputs of the FPGA130a. In other words, during the normal operation of the IC110, the shift/interface system150is transparent to the FPGA130aand the ASIC160as far as the functional data is concerned.

During the structural test180(FIG. 1B) of the FPGA130a, in step184, in one embodiment, after the first data shift, the P shift/store units210of the P shift/interface circuits151of type151aof the chain should contain the first FPGA test data. Then, with the Test-FPGA signal pulled high by the tester120, the P MUXes220of the P shift/interface circuits151of type151aapply the first FPGA test data (at the P SO outputs of the P shift/store units210) to the P functional data inputs of the FPGA130a.

During the testing of the ASIC160, the tester120can pull the Test-FPGA signal low (i.e., 0) to electrically couple the P outputs of the ASIC160to the P DI inputs of the P shift/interface circuits151of type151a. As a result, signals on the P outputs of the ASIC160can be stored in the P shift/interface circuits151of type151aand can be later shifted out to the tester120for analysis.

In one embodiment, multiple shift/interface circuits151of type151acan also be used to couple functional data outputs of the ASIC160to functional data inputs of the FPGA130bin a manner similar to that for the FPGA130a. In one embodiment, the testing of the FPGAs130aand130bcan be carried out simultaneously in a similar manner.

FIG. 2Billustrates the shift/interface circuit151b(i.e., a shift/interface circuit151of type151b) that can be used in the shift/interface system150ofFIG. 1A, in accordance with embodiments of the present invention. With reference toFIGS. 1A and 2B, for type151b, in one embodiment, the MUX220can have its first and second inputs electrically coupled to an output of the ASIC160(via connection155b, a part of connections155ofFIG. 1A) and an output of the tester120, respectively. The MUX220can have its output electrically coupled to the input DI of the shift/store unit210and an input of the FPGA130avia connection136b, a part of connections133aofFIG. 1A. The MUX220can have its control input receiving the Test-FPGA signal from the tester120. In short, the output of the ASIC160is coupled to the input of the FPGA130avia the shift/interface circuit151of type151b.

In one embodiment, assume that the FPGA130ahas Q configuration inputs that need to be directly coupled one-to-one to Q configuration outputs of the ASIC160during the normal operation of the IC110ofFIG. 1A(Q is a positive integer). As a result, Q shift/interface circuits151of type151bcan be used in the chain to couple the Q configuration outputs of the ASIC160to the Q configuration inputs of the FPGA130a.

During the normal operation of the IC110, with reference toFIGS. 1A and 2B, the tester120can pull the Test-FPGA signal low (i.e.,0) to cause the Q MUXes220of the Q shift/interface circuits151of type151bto electrically couple the Q configuration outputs of the ASIC160to the Q configuration inputs of the FPGA130a. In other words, during the normal operation of the IC110, the shift/interface system150is transparent to the FPGA130aand the ASIC160as far as the configuration data is concerned.

During the structural test180(FIG. 1B) of the FPGA130a, in step188, in one embodiment, with the Test-FPGA signal being high, the Q MUXes220of the Q shift/interface circuits151of type151bcan apply the Q configuration signal bits from the tester120to the Q configuration inputs of the FPGA130a. During the structural test180(FIG. 1B), the tester120can change the configuration signal bits sent to the FPGA130a.

During the testing of the ASIC160, the tester120can pull the Test-FPGA signal low (i.e.,0) to electrically couple the Q outputs of the ASIC160to the Q DI inputs of the Q shift/interface circuits151of type151b. As a result, signals on the Q outputs of the ASIC160can be stored in the Q shift/interface circuits151of type151band can be later shifted out to the tester120for analysis.

In one embodiment, multiple shift/interface circuits151of type151bcan also be used to couple configuration outputs of the ASIC160to configuration inputs of the FPGA130bin a manner similar to that for the FPGA130a. In one embodiment, the testing of the FPGAs130aand130bcan be carried out simultaneously in a similar manner.

FIG. 2Cillustrates the shift/interface circuit151c(i.e., a shift/interface circuit151of type151c) that can be used in the shift/interface system150ofFIG. 1A, in accordance with embodiments of the present invention. With reference toFIGS. 1A and 2C, for type151c, in one embodiment, the MUX220can have its first and second inputs electrically coupled to an output of the FPGA130a(via connection136c, a part of connections133aofFIG. 1A) and the SO output of the shift/store unit210, respectively. The MUX220can have its output electrically coupled to an input of the ASIC160(via connection155c, a part of connections155ofFIG. 1A) and to the DI input of the shift/store unit210. In one embodiment, the MUX220can have its output further electrically coupled directly to the tester120via a connection (not shown). As a result, the tester120can continuously monitor the output of the FPGA130aas long as the MUX220selects the output of the FPGA130a. The MUX220can have its control input receiving a Test-ASIC signal from the tester120via connection157c, a part of connections157ofFIG. 1A. In short, the output of the FPGA130ais coupled to the input of the ASIC160via the shift/interface circuit151of type151c.

In one embodiment, assume that the FPGA130ahas R configuration status outputs that need to be directly coupled one-to-one to R configuration status inputs of the ASIC160during the normal operation of the IC110ofFIG. 1A(R is a positive integer). Assume further that the FPGA130ahas S functional data outputs that need to be electrically coupled one-to-one to S functional data inputs of the ASIC160during the normal operation of the IC110ofFIG. 1A(S is a positive integer). As a result, R shift/interface circuits151of type151ccan be used in the chain to couple the R configuration status outputs of the FPGA130ato the R configuration status inputs of the ASIC160. Also, S shift/interface circuits151of type151ccan be used in the chain to couple the S functional data outputs of the FPGA130ato the S functional data inputs of the ASIC160.

During the normal operation of the IC110, with reference toFIGS. 1A and 2C, the tester120can pull the Test-ASIC signal low (i.e.,0) to cause the R+S MUXes220of the R+S shift/interface circuits151of type151cto electrically couple the R configuration status outputs and S functional data outputs of the FPGA130ato the R configuration status inputs and S functional data inputs of the ASIC160, respectively. In other words, during the normal operation of the IC110, the shift/interface system150is transparent to the FPGA130aand the ASIC160as far as the FPGA configuration status data and the FPGA functional output data are concerned.

During the structural test180(FIG. 1B) of the FPGA130a, in step192, in one embodiment, the tester120can pull the Test-ASIC signal low (i.e.,0) to cause the R+S MUXes220of the R+S shift/interface circuits151of type151cto electrically couple the R configuration status outputs and S functional data outputs of the FPGA130ato the R+S DI inputs of the R+S shift/store units210of the R+S shift/interface circuits151of type151c. As a result, configuration status data from the FPGA130acan be transmitted to and stored in the R shift/interface circuits151of type151cof the chain and can be later shifted out to the tester120for analysis (as part of the second bitstream). Similarly, the FPGA responses at the S functional data outputs of the FPGA130acan be transmitted to the S shift/interface circuits151of type151cof the chain, and the last FPGA response of the FPGA130acan be later shifted out to the tester120for analysis (as part of the second bitstream).

During the testing of the ASIC160, the tester120can pull the Test-ASIC signal high (i.e.,1) to electrically couple the R+S inputs of the ASIC160to the R+S SO outputs of the R+S shift/interface circuits151of type151c. As a result, ASIC test data can be shifted into the shift/interface system150from the tester120(in one embodiment, as part of the first bitstream) and then applied to the R+S inputs of the ASIC160via the R+S MUXes220of the R+S shift/interface circuits151of type151c.

In one embodiment, multiple shift/interface circuits151of type151ccan also be used to couple configuration status outputs and functional data outputs of the FPGA130b(FIG. 1A) to configuration status inputs and functional data inputs of the ASIC160, respectively, in a manner similar to that for the FPGA130a. In one embodiment, the testing of the FPGAs130aand130bcan be carried out simultaneously in a similar manner.

FIG. 2Dillustrates the shift/interface circuit151d(i.e., a shift/interface circuit151of type151d) that can be used in the shift/interface system150ofFIG. 1Aand a MISR stage142that can be used in the MISR140aofFIG. 1A, in accordance with embodiments of the present invention.

In one embodiment, S MISR stages (not shown) like the MISR stage142(or in short, the S MISR stages142) can be coupled together in daisy chain to form the MISR140aofFIG. 1A. In one embodiment, the S MISR stages142can be coupled one-to-one to the S functional data outputs (described above) of the FPGA130aand also coupled one-to-one to S shift/interface circuits151of type151d.

In one embodiment, the shift/interface circuit151dhas a structure similar to the shift/interface circuit151c(FIG. 2C), except that in the shift/interface circuit151d, the first input of the MUX220is coupled to an output of the associated MISR stage142(via connection137) and the output of the MUX220is not coupled to the ASIC160.

During the structural test180(FIG. 1B) of the FPGA130a, in step192, in one embodiment, FPGA responses on the S functional data outputs of the FPGA130acan be transmitted via connection136dto the S associated MISR stages142to be processed into the first FPGA response signature. More specifically, when a current FPGA response at the S functional data outputs of the FPGA130ais transmitted to the S associated MISR stages142, the S MISR stages142combine the current FPGA response with the previous FPGA response signature to form a current FPGA response signature. At the end, the first FPGA response signature is created at the S outputs of the S MISR stages142. With the Test-ASIC signal pulled low (i.e.,0) by the tester120, the S MUXes220of the S shift/interface circuits151of type151dapply the first FPGA response signature from the S MISR stages142to the S DI inputs of the S shift/interface circuits151of type151d. In step196(FIG. 1B), the first FPGA response signature is shifted out to the tester120for analysis (as part of the second bitstream).

In one embodiment, T more MISR stages142(T being a positive integer) can be added to the end of the chain of the S MISR stages142so as to reduce the chance of response signature alias. As a result, T more shift/interface circuits151of type151dcorresponding to the T additional MISR stages142can be added to the chain. The first FPGA response signature therefore has S+T bits instead of S bits.

In one embodiment, multiple shift/interface circuits151of type151dand multiple MISR stages142can also be coupled to functional data outputs of the FPGA130bin a manner similar to that for the FPGA130a. In one embodiment, the testing of the FPGAs130aand130bcan be carried out simultaneously in a similar manner with respect to FPGA response signature formation.

FIG. 2Eillustrates the shift/interface circuit151e(i.e., a shift/interface circuit151of type151e) that can be used in the shift/interface system150ofFIG. 1A, in accordance with embodiments of the present invention. With reference toFIGS. 1A and 2E, for type151e, in one embodiment, the MUX220can have its first and second inputs electrically coupled to an output of the ASIC160and an output of the tester120(via connection157e2, apart of the connections157ofFIG. 1A), respectively. The output of the ASIC160is also electrically coupled to the DI input of the shift/store unit220. The MUX220can have its output electrically coupled to an input of the FPGA130avia connection136e. The MUX220can have its control input receiving a Test-Enable signal from the tester120via connection157e1, a part of connections157ofFIG. 1A. In one embodiment, the input of the FPGA130acan be a stability input of the FPGA130afor receiving the stability signal from the tester120.

During the normal operation of the IC110, with reference toFIGS. 1A and 2E, the tester120can pull the Test-Enable signal low (i.e., 0) to cause the MUX220of the shift/interface circuit151eto electrically couple the output of the ASIC160to the stability input of the FPGA130a.

During the structural test180(FIG. 1B) of the FPGA130a, in steps182and194in one embodiment, the tester120can pull the Test-Enable signal high and also assert the stability signal on the connection157e2. As a result, the asserted stability signal is transmitted to the stability input of the FPGA130avia the MUX220of the shift/interface circuit151e. Therefore, the FPGA130ais placed in the stable state. In one embodiment, in step186of the structural test180(FIG. 1B), the tester120can pull the Test-Enable signal high and also deactivate the stability signal on the connection157e2. As a result, the FPGA130ais placed in the operation state.

During the testing of the ASIC160, the shift/store unit220can store the bit from the output of the ASIC160. Later, the stored bit can be shifted out to the tester120for analysis.

In one embodiment, another shift/interface circuit151of type151ecan also be used for a stability input of the FPGA130bin a manner similar to that for the FPGA130a. In one embodiment, the testing of the FPGAs130aand130bcan be carried out simultaneously in a similar manner.

FIG. 3illustrates one embodiment of the shift/store unit210that can be used in the shift/interface circuits151a,151b,151c,151d, and151eofFIGS. 2A-2E, respectively, in accordance with embodiments of the present invention. In one embodiment, the shift/store unit210can comprise latches310and320. The latch310can have four inputs I, A, C, and D and one output L1, whereas the latch320has two inputs B and E and one output L2.

The inputs SI and DI of the shift/store unit210can be electrically coupled to inputs I and D of the latch310, respectively. The output L1of the latch310is electrically coupled to input E of the latch320. The output L2of the latch320is electrically coupled to the output SO of the shift/store unit210. The inputs A, B, and C can be control inputs which can be electrically coupled to the tester120via connections157(FIG. 1A).

In one embodiment, for the latch310, if A=1 (i.e., logic high) and C=0 (i.e., logic low), then the output L1is electrically coupled to input I (i.e., L1=I). If A=0 and C=1, then L1=D. If A=C=0, then L1remains at its current state. The case A=C=1 is not allowed. In one embodiment, for the latch320, if B=1, then L2=E. If B=0, L2is electrically decoupled from E.

In the embodiments described above, all the shift/interface circuits151(FIGS. 2A-2E) of the shift/interface system150(FIG. 1A) are coupled together in a single chain. Alternatively, the shift/interface circuits151can be coupled together in multiple chains each of which can start from and end at the tester120. In one embodiment, latches in the ASIC160(FIG. 1A) can also be included in the chain(s) of the shift/interface circuits151.

In the embodiments described above, with reference toFIG. 1A, the FPGAs130aand130bare shown separate from the ASIC160. Alternatively, the FPGAs130aand130bcan be embedded in the ASIC160.

In the embodiments described above, with reference toFIG. 1A, the FPGAs130aand130bare used for illustration. In general, the present invention is applicable to any macro circuits (not just FPGAs). A macro circuit is itself an integrated circuit (IC). A macro circuit can be integrated in another integrated circuit.