MIXER CIRCUIT, SEMICONDUCTOR DEVICE, RECEIVING CIRCUIT, RECEIVING DEVICE, AND COMMUNICATION DEVICE

According to an embodiment, a mixer circuit includes first transistors each having a charge storage layer, a second transistor, a group of first nodes, and an output node. The first transistors as a pair receive a differential signal having a first frequency. The second transistor receives a signal having a second frequency. The group of first nodes makes the charge storage layer of at least any one of the first transistors store charge during non-operation period during which the differential signal having the first frequency and the signal having the second frequency are not mixed and reduces loss of the charge during operation period during which those signals are mixed, to adjust a threshold voltage of at least any one of the first transistors from outside. The output node outputs a signal resulting from mixing the differential signal having the first frequency and the signal having the second frequency.

DETAILED DESCRIPTION

According to an embodiment, a mixer circuit includes a plurality of first transistors, a second transistor, a group of first nodes, and an output node. The plurality of first transistors is used in a pair and receives a differential signal having a first frequency. The first transistors each have a charge storage layer. The second transistor receives a signal having a second frequency. The group of first nodes makes the charge storage layer of at least any one of the first transistors store charge during non-operation period during which the differential signal having the first frequency and the signal having the second frequency are not mixed and reduces loss of the charge during operation period during which the differential signal having the first frequency and the signal having the second frequency are mixed, so as to adjust a threshold voltage of at least any one of the first transistors from outside. The output node outputs a signal resulting from mixing the differential signal having the first frequency and the signal having the second frequency.

First, the circumstances that lead to a mixer circuit according to the embodiment being conceived will be described below with reference to the accompanying drawings.

FIG. 1is a diagram illustrating an exemplary configuration of a single balanced mixer1using a pair of nMOS transistors. As illustrated inFIG. 1, the single balanced mixer1includes differential input nodes10-1and10-2, an input node12, output nodes14-1and14-2, nMOS transistors20-1,20-2and22, and load resistors24-1and24-2.

The single balanced mixer1is used for frequency conversion of RF (radio frequency) signals in a receiving circuit (seeFIG. 10) of a wireless communication device, for example. For example, when the single balanced mixer1to which power supply voltage (Vdd) is applied is used in a direct conversion receiving circuit, a local signal LO (local oscillator) having a frequency f1 is differentially input to the differential input nodes10-1and10-2from a local oscillator. The differential signals of the local signal LO are respectively input to gate terminals of the nMOS transistors20-1and20-2.

An RF signal having a frequency f2 that is equal to or very close to the frequency f1 is input to the input node12. The RF signal is input to a gate terminal of the nMOS transistor22. Note that the load resistors24-1and24-2lower the power supply voltage across the nMOS transistors20-1and20-2, respectively.

The single balanced mixer1then mixes the differential signals of the local signal LO and the RF signal, and outputs differential signals having frequencies f2±f1 (if f2>f1; frequencies f1±f2 if f2<f1) from the output nodes14-1and14-2. In the direct conversion method, signals having a frequency f2−f1, for example is used as a baseband signal.

If the nMOS transistors20-1and20-2and the load resistors24-1and24-2that are used in a pair have the same characteristics, it is possible to suppress even-order distortion including second-order distortion. It is, however, extremely difficult to make the characteristics of the nMOS transistors20-1and20-2and the load resistors24-1and24-2the same without variation in normal processes. Thus, the variation in characteristics existing in the nMOS transistors20-1and20-2and the load resistors24-1and24-2inevitably causes second-order distortion of an interfering wave in proximity in the baseband bandwidth, which deteriorates the SN ratio.

In general, when the random variation in threshold voltage Vth of a transistor is represented by σVth, a gate length is represented by L and a gate width is represented by W, σVth is proportional to −½ power of LW. Thus, the variation in Vth of the transistor is larger as the transistor is miniaturized. Accordingly, with the related art, it is difficult to make the variation smaller, and to improve the high-frequency characteristics by making L smaller and lower power consumption by making W smaller at the same time.

It is therefore attempted to reduce deterioration in the characteristics caused by the variation in transistors used in a pair regardless of the size of the transistors by means of a mixer circuit according to the embodiment.

Embodiment

An example of the mixer circuit according to the embodiment will be described below with reference to the accompanying drawings.FIG. 2is a diagram illustrating an exemplary configuration of a mixer circuit2according to the embodiment. For example, the mixer circuit2is a single balanced mixer having a configuration including transistors26-1and26-2instead of the nMOS transistors20-1and20-2illustrated inFIG. 1. Components of the mixer circuit2that are substantially the same as those of the single balanced mixer1illustrated inFIG. 1will be designated by the same reference numerals. When certain one of a plurality of components such as the transistors26-1and26-2is referred to without specifying which of the components, the component may be simply referred to as a “transistor26” or the like.

First, the transistor26will be described.FIG. 3is a diagram illustrating an exemplary configuration of the transistor26. The transistor26is a charge storage SONOS (silicon-oxide-nitride-oxide-semiconductor) transistor, for example. As illustrated inFIG. 3, the transistor26has a structure in which a source61and a drain62are formed on an Si (p-well) substrate60and a gate63, a block layer64, a charge storage layer65, and a tunnel film66are stacked between the source61and the drain62.

The tunnel film66is a silicon dioxide (SiO2) film. The charge storage layer65is an insulating silicon nitride (SiN) film. The block layer64is, for example, a multi-layered film of silicon dioxide films or a silicon dioxide film and a silicon nitride film. Thus, the SONOS transistor (SONOS) stores charge in a trap in the nitride film (charge storage layer) that is an insulating film between silicon dioxide films and has a function of holding memory. The threshold voltage Vth of the SONOS changes with the amount of charge stored by the charge storage layer, and the value of the threshold voltage Vth is maintained when the amount of charge is maintained. The transistor26may be an MONOS (metal-oxide-nitride-oxide-semiconductor) or a transistor used for floating gate (FG) flash memory or the like.

An FG transistor employs a floating gate (Poly-Si) that is a conductor instead of an insulating charge storage layer (SiN). Since the floating gate is a conductor, the potential thereof is constant in the plane direction, and if a defect leading to charge leakage is caused in the tunnel film, the charge will be lost through the floating gate regardless of the position of the defect. In contrast, in a transistor such as an SONGS having an insulating charge storage layer, charge leakage is not caused unless the position of the defect in the tunnel film and the position of the trap in the charge storage layer match each other, and such transistors are therefore better in retention characteristics than the floating gate transistors.

Examples of the method for storing charge in an SONGS includes a method using FN tunnel injection and a method using a hot carrier generated by impact ionization (collision ionization) at the drain62of a channel67(N channel, for example) as illustrated inFIG. 3. In order to cause FN tunnel injection, a high voltage of about 10 V is typically required, and a booster circuit for boosting the power supply voltage is required. In contrast, the method using a hot carrier is advantageous is that writing (charge storage) is possible at the power supply voltage and a booster circuit is not required.

FIGS. 4A and 4Bare diagrams illustrating an outline of potential of the transistor26during writing (charge storage) and during circuit operation. As illustrated inFIG. 4A, voltage is applied to the gate of the transistor26, current flows between the drain and the source, and charge is thus stored. Note that the drain and the source of the transistor26are reversed during circuit operation and during writing. In other words, the drain and the source of the transistor26are replaced with each other. Furthermore, the drain voltage Vds of the transistor26is set to the power supply voltage, for example, during writing while the drain voltage Vds is set to be lower than the power supply voltage during circuit operation so as to prevent unintended writing to the charge storage layer.

Alternatively, as illustrated inFIG. 4B, the transistor26may be modified to have a configuration in which an nMOS transistor36sharing the gate terminal with the transistor26is connected to the high potential side during circuit operation. In this manner, in the transistor26, a node at the high potential side during writing may become the low potential side during circuit operation and unintended writing to the charge storage layer may be prevented by voltage drop caused by the nMOS transistor36arranged at the high potential side during circuit operation.

The mixer circuit2(FIG. 2) is provided with transistors28-1and28-2respectively connected in series with the load resistors24-1and24-2. The transistor28is an SONOS transistor having the same structure as the transistor26described above, for example. The transistors28-1and28-2are provided to resolve the variation in resistances of the load resistors24-1and24-2arranged as a pair. For example, since the threshold voltage Vth of the transistor28varies with the amount of change stored by the charge storage layer65, the on-resistance thereof varies. It is thus possible to resolve the influence of the variation of the load resistors24-1and24-2by adjusting the on-resistance of at least either one of the transistors28-1and28-2.

Furthermore, the mixer circuit2is provided with pMOS transistors31-1,31-2,33-1,33-2,35-1,35-2,37-1, and37-2. The mixer circuit2is also provided with nMOS transistors32-1,32-2,34-1, and34-2.

The mixer circuit2also includes nodes40,41-1to49-1, and41-2to49-2that can be connected to external circuits, and nodes51-1to55-1, and51-2to55-2that are internal nodes. For example, potentials of the nodes40,41-1to49-1, and41-2to49-2can be arbitrarily changed in a range from the power supply voltage to ground by external control. Furthermore, the nodes40,41-1to49-1, and41-2to49-2are set to different potentials between during writing and during circuit operation.

The pMOS transistor31has a gate terminal to which the node45is connected, and a drain terminal, when the power supply voltage, etc., is applied to the node41, connected to the gate terminal of the transistor26at the node54.

The pMOS transistor33has a gate terminal to which the node46is connected, and a drain terminal, when the power supply voltage, etc., is applied to the node42, connected to the output node14at the node55.

The pMOS transistor35has a gate terminal to which the node47is connected, and a drain terminal, when the power supply voltage, etc., is applied to the node43, connected to the gate terminal of the transistor28.

The pMOS transistor37has a gate terminal to which the node44is connected, and a drain terminal, when the power supply voltage, etc., is applied to the node40, connected to the drain terminal of the nMOS transistor22at the node51.

The nMOS transistor32has a gate terminal to which the node49is connected, and a drain terminal connected to the node52between the transistor26and the transistor28. Note that the potentials of the node55and the node52are equal.

The nMOS transistor34has a gate terminal to which the node48is connected, and a drain terminal connected to the node53between the low potential side of the load resistor24and the transistor28.

Next, an example of operation for writing (charge storage, threshold voltage adjustment) to the transistor26will be described.FIG. 5is a diagram illustrating the direction of current during writing to the transistor26. Note that the mixer circuit2illustrated inFIG. 5is the same as the mixer circuit2illustrated inFIG. 2, and only one (left side inFIG. 5) of the differential input and the differential output is designated by reference numerals for simplification.

When the power supply voltage (3.3 V, for example) is applied to the node40and the node44is set to 0 V, the pMOS transistor37is turned on and the potential of the node51becomes approximately equal to the power supply voltage level. Furthermore, when the power supply voltage is applied to the node49, the nMOS transistor32is turned on and the potential of the node52becomes approximately equal to the ground level.

When the power supply voltage is applied to the node41and the node45is set to 0 V in this state, the pMOS transistor31is turned on and voltage approximately equal to the power supply voltage is applied to the gate terminal of the transistor26. The direction of current at this point is indicated by a thick arrow.

When the transistor26operates in this manner, a hot carrier is generated by impact ionization at the drain (on the side of the node51) of the transistor26, electrons are trapped in the charge storage layer65(FIG. 3) and the threshold voltage Vth changes. At this point, the voltage applied to the gate terminal of the transistor26may be at any level equal to or lower than the power supply voltage and may be changed as appropriate so as to efficiently cause impact ionization.

After changing the threshold voltage Vth of the transistor26, the operator makes the mixer circuit2operate to measure second-order distortion. The operator then adjusts the threshold voltage Vth of the transistor26until the second-order distortion during circuit operation of the mixer circuit2is reduced to a desired value. In other words, the deterioration in the characteristics due to variation of the transistors26-1and26-2can be reduced by adjusting the threshold voltage Vth of at least either one of the transistors26-1and26-2. Note that the adjustment of the threshold voltage Vth is not limited to that by actually measuring the second-order distortion but may be performed by other methods such as by measuring the threshold voltage Vth directly.

As described above, the threshold voltage Vth changes with the amount of charge stored by the charge storage layer65, and the value of the threshold voltage Vth is maintained when the amount of charge is maintained. Accordingly, when the mixer circuit2operates after the threshold voltage Vth is adjusted, potentials that do not allow writing to the charge storage layer65of the transistor26are set at the nodes51,52and54. For example, in relation to the transistor26, a node that is a source is set to 0 V, a node that is a drain is set to 0.1 V, and a node that is a gate is set to 0.8 V.

Next, an example of operation for writing (charge storage, threshold voltage adjustment) to the transistor28will be described.FIG. 6is a diagram illustrating the direction of current during writing to the transistor28. Note that the mixer circuit2illustrated inFIG. 6is the same as the mixer circuit2illustrated inFIG. 2, and only one (left side inFIG. 6) of the differential input and the differential output is designated by reference numerals for simplification.

When the power supply voltage (3.3 V, for example) is applied to the node42and the node46is set to 0 V, the pMOS transistor33is turned on and the potential of the nodes55and52becomes approximately equal to the power supply voltage level. Furthermore, when the power supply voltage is applied to the node48, the nMOS transistor34is turned on and the potential of the node53becomes approximately equal to the ground level.

When the power supply voltage is applied to the node43and the node47is set to 0 V in this state, the pMOS transistor35is turned on and voltage approximately equal to the power supply voltage is applied to the gate terminal of the transistor28. The direction of current at this point is indicated by a thick arrow.

When the transistor28operates in this manner, a hot carrier is generated by impact ionization at the drain (on the side of the node52) of the transistor28, electrons are trapped in the charge storage layer65(FIG. 3) and the threshold voltage Vth (that is, on-resistance) changes. At this point, the voltage applied to the gate terminal of the transistor28may be at any level equal to or lower than the power supply voltage and may be changed as appropriate so as to efficiently cause impact ionization.

After changing the threshold voltage Vth of the transistor28, the operator makes the mixer circuit2operate to measure second-order distortion. The operator then adjusts the threshold voltage Vth of the transistor28until the second-order distortion during circuit operation of the mixer circuit2is reduced to a desired value. In other words, the deterioration in the characteristics due to variation of the load resistors24-1and24-2can be reduced by adjusting the threshold voltage Vth of at least either one of the transistors28-1and28-2. Note that the adjustment of the threshold voltage Vth is not limited to that by actually measuring the second-order distortion but may be performed by other methods such as by measuring the threshold voltage Vth directly.

As described above, the on-resistance (threshold voltage Vth) changes with the amount of charge stored by the charge storage layer65, and the value of the threshold voltage Vth is maintained when the amount of charge is maintained. Accordingly, when the mixer circuit2operates after the on-resistance is adjusted, potentials that do not allow writing to the charge storage layer65of the transistor28are set at the nodes43,47,52and53. For example, in relation to the transistor28, a node that is a source is set to 0 V, a node that is a drain is set to 0.1 V, and a node that is a gate is set to 0.8 V.

Although the mixer circuit2is described taking the single balanced mixer as an example, the mixer circuit2is not limited thereto and may be a double balanced mixer or the like. For example, when the mixer circuit2is modified to a double balanced mixer, the input nodes12are provided to constitute a differential pair. Accordingly, two nMOS transistors22constituting a differential pair may also be replaced by SONOSs so that the threshold voltage Vth thereof can be adjusted.

Next, characteristics of the SONOS will be described in detail. The SONOS has a configuration in which a tunnel film SiO2(5 nm), a charge storage layer SiN (5 nm), a block layer (SiO2; 2 nm+SiN; 2 nm+SiO2; 2 nm), and a Poly-Si gate electrode are stacked.

FIG. 7is a graph illustrating an example of operation of the SONOS (N channel) after the amount of charge stored by a charge storage layer is changed. The amount of charge stored by the charge storage layer is adjusted using the length of time (voltage application time) during which writing is performed on the SONOS. The gate voltage and the drain voltage applied to the SONOS during writing is 3.3 V. In the SONOS, the amount of charge stored in the charge storage layer increases as the voltage application time is longer. In the example illustrated inFIG. 7, the voltage application time is changed from 0 sec. (initial value) to 0.0365 sec. In this case, the gate length L and the gate width W of the SONOS are 130 nm and120respectively. Furthermore, in the example illustrated inFIG. 7, the drain voltage Vd of the SONOS is set to 50 mV. In the graph illustrated inFIG. 7, the horizontal axis represents the gate voltage Vg (V) and the vertical axis represents the drain current Id (A) in logarithmic expression so as to express the threshold voltage Vth as a boundary between a weak inversion region and a strong inversion region.

As illustrated inFIG. 7, as the amount of charge stored in the charge storage layer increases, the boundary (threshold voltage Vth) between a weak inversion region in which the drain current exponentially (linearly inFIG. 7) increases with respect to the gate voltage and a strong inversion region in which high drain current flows becomes higher.

FIG. 8is a graph illustrating the relationship between a change (ΔVth) in threshold voltage Vth and voltage application time (pulse width) in the result illustrated inFIG. 7. For example, in a case of a transistor in which the gate length is 130 nm or shorter, the change (ΔVth) in the threshold voltage Vth to be adjusted is typically about 30 mV. InFIG. 8, the pulse width corresponding to 30 mV is 2e-4 sec. Thus, if the threshold voltage Vth is to be corrected by 30 mV, the gate voltage and the drain voltage of 3.3 V are applied to the SONGS for 2e-4 sec.

Furthermore, the SONGS may be configured to adjust the amount of charge stored in the charge storage layer by repeating writing and erasing.FIG. 9is a diagram illustrating an exemplary configuration of an SONGS capable of isolating potentials for each SONGS. As illustrated inFIG. 9, the SONGS may be formed in a triple well structure. Specifically, the SONGS illustrated inFIG. 3may be formed in a deep n-well71formed in a p-type Si substrate70. The SONGS is individually isolated by STI (shallow trench isolation)72on the outside of the source61and the drain62, and a well contact73provided in the substrate60and a well contact74provided in the deep n-well71are isolated by STI72.

Since substrate potentials can be isolated from one another among a plurality of substrates (p-wells)60of a plurality of SONOSs structured as illustrated inFIG. 9, it is possible to apply positive bias to the substrate60via the well contact73and the well contact74in each of the SONOSs.

For example, if change (electrons) stored in the charge storage layer of an SONGS after performing writing to the SONGS, positive bias is selectively applied to the substrate60on which the SONGS is formed and 0 V is applied to the gate terminal of the SONGS. In other words, it is possible to draw out only electrons stored by the selected SONGS into the substrate60. In this manner, it is possible to select and perform erasing operation on each of a plurality of SONOSs structured as illustrated inFIG. 9. Furthermore, it is also possible to erase an intended amount of electrons by controlling the time during which the voltage is applied. Accordingly, it is possible to set the threshold voltage Vth of the SONGS illustrated inFIG. 9to a desired level with higher accuracy by repeating writing and erasure. Furthermore, erasure may be performed by injecting a hot hole generated by an band to band tunneling in a region where the gate and the drain overlap with each other into the charge storage layer by applying 0 V, for example to the gate and 3.3 V, for example to the drain of the SONGS.

Next, a receiving circuit of a communication device in which the mixer circuit2is used to reduce deterioration in the characteristics will be described.FIG. 10is a block diagram illustrating an outline of a receiving circuit8of a direct conversion communication device in which the mixer circuit2is used. As illustrated inFIG. 10, the receiving circuit8includes an antenna80, a switch81, a low-noise amplifier (LNA)82, a phase locked loop (PLL)83, the mixer circuit2, a baseband filter85, a baseband amplifier86, and an AD converter87.

The antenna80receives a radio wave containing a signal superimposed on a carrier wave. The switch81switches a receiving circuit to/from a transmitting circuit that is not illustrated. The LNA82amplifies a signal (RF signal) received by the antenna80and outputs the amplified signal to the mixer circuit2. The PLL83includes a voltage controlled oscillator (VCO)84, phase-locks a signal (local signal LO) having a frequency equal to that of the carrier wave, and outputs the resulting signal to the mixer circuit2.

The mixer circuit2mixes the local signal LO output from the PLL83and the RF signal output from the LNA82, and outputs the resulting signal to the baseband filter85. Although not illustrated inFIG. 10, the mixer circuit2receives the local signal LO as differential signals by the differential input nodes10-1and10-2, receives the RF signal output from the LNA82by the input node12, and outputs the differential signals resulting from the mixture from the output nodes14-1and14-2.

The baseband filter85receives signals from the mixer circuit2and allows a baseband signal to pass therethrough. The process for generating a baseband signal from the differential signals output from the mixer circuit2may be performed at any block. The baseband amplifier86amplifies the baseband signal. The AD converter87converts the baseband signal to a digital signal and outputs the digital signal to a baseband processing circuit that is not illustrated.

According to the mixer circuit according to the embodiment, since the threshold voltage of a transistor can be adjusted from outside, deterioration in the characteristics due to variation of transistors constituting a pair can be reduced.