IMAGE SENSOR

An image sensor includes a first substrate having a photoelectric conversion element. A first gate electrode is on a first side of the first substrate. A floating diffusion region is in the first substrate. A first wiring structure is on the first side and includes a first wiring layer and a first bonding pad. A second substrate has a third side that includes second and third gate electrodes. An impurity region is in the second substrate. A second wiring structure is on the third side and includes a second wiring layer and a second bonding pad directly contacting the first bonding pad. A fourth gate electrode is on a fourth side of the second substrate. A third wiring structure is on the fourth side and includes a third wiring layer. The floating diffusion region is connected to the impurity region through the first wiring structure and the second wiring structure.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0164770, filed on Nov. 30, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.

1. TECHNICAL FIELD

The present disclosure relates to an image sensor.

2. DISCUSSION OF RELATED ART

An image sensor is a semiconductor device that converts optical information into an electric signal. Image sensors may include a charged coupled device (CCD) image sensor and a complementary metal-oxide semiconductor (CMOS) image sensor.

The image sensor may be arranged in the form of a package. The package may be protect the image sensor and allow light to enter a photo-receiving surface or a sensing area of the image sensor.

SUMMARY

Aspects of the present disclosure provide an image sensor having increased product reliability.

According to an embodiment of the present disclosure, an image sensor includes a first substrate that includes a first side and a second side opposite to each other in a first direction. A photoelectric conversion element is in the first substrate. A first gate electrode is on the first side of the first substrate and positioned adjacent to the photoelectric conversion element. A floating diffusion region is in the first substrate on one side of the first gate electrode. A first wiring structure is on the first side of the first substrate. The first wiring structure includes a first wiring layer and a first bonding pad on the first wiring layer. A second substrate includes a third side opposite to the first side and a fourth side opposite to the third side. Second and third gate electrodes are spaced apart from each other on the third side of the second substrate. An impurity region is in the second substrate on one side of the second gate electrode. A second wiring structure is on the third side of the second substrate. The second wiring structure includes a second wiring layer and a second bonding pad on the second wiring layer. A fourth gate electrode is on the fourth side of the second substrate. A third wiring structure is on the fourth side of the second substrate. The third wiring structure includes a third wiring layer. The second bonding pad directly contacts the first bonding pad. The floating diffusion region is connected to the impurity region through the first wiring structure and the second wiring structure.

According to an embodiment of the present disclosure, an image sensor comprising a first semiconductor chip and a second semiconductor chip having a plurality of pixel groups positioned therein. The first and second semiconductor chips are stacked in a first direction. The first semiconductor chip includes a first substrate that includes a first side and a second side opposite to each other in the first direction. A first pixel is on the first side of the first substrate. The first pixel includes a first photoelectric conversion element in the first substrate and a first-1 transistor. A second pixel is on the first side of the first substrate. The second pixel includes a second photoelectric conversion element in the first substrate and a first-2 transistor. A third pixel is on the first side of the first substrate. The third pixel includes a third photoelectric conversion element in the first substrate and a first-3 transistor. A fourth pixel is on the first side of the first substrate. The fourth pixel includes a fourth photoelectric conversion element in the first substrate and a first-4 transistor. A floating diffusion region is connected to the first-1 to first-4 transistors in the first substrate. The floating diffusion region is disposed between the first to fourth pixels. A first wiring structure is on the first side of the first substrate. The first wiring structure includes a first wiring layer. The second semiconductor chip includes a second substrate including a third side opposite to the first side, and a fourth side opposite to the third side. A second wiring structure is on the third side of the second substrate. The second wiring structure includes a second wiring layer. Second and third transistors are on the third side of the second substrate. The second and third transistors are spaced apart from each other. A fourth transistor is on the fourth side of the second substrate. A third wiring structure is on the fourth side of the second substrate. The third wiring structure includes a third wiring layer. Each plurality of pixel groups includes the first to fourth pixels, the floating diffusion region, and the second to fourth transistors.

According to an embodiment of the present disclosure, an image sensor includes a first substrate that includes a first side and a second side opposite to each other in a first direction. A color filter is on the second side of the first substrate. A microlens is on the color filter. A photoelectric conversion element is inside the first substrate. A first gate electrode is on the first side of the first substrate. The first gate electrode is positioned adjacent to the photoelectric conversion element. A floating diffusion region is in the first substrate on one side of the first gate electrode. A first wiring structure is on the first side of the first substrate. The first wiring structure includes a first wiring layer and a first bonding pad on the first wiring layer. A second substrate includes a third side opposite to the first side and a fourth side opposite to the third side. Second and third gate electrodes are on the third side of the second substrate. The second and third gate electrodes are spaced apart from each other. An impurity region is inside the second substrate on one side of the second gate electrode. A second wiring structure is on the third side of the second substrate. The second wiring structure includes a second wiring layer and a second bonding pad on the second wiring layer. The second bonding pad directly contacts the first bonding pad. A fourth gate electrode is on the fourth side of the second substrate. A third wiring structure is on the fourth side of the second substrate. The third wiring structure includes a third wiring layer, a contact penetrating the second substrate and connected to the second wiring layer and the third wiring layer, and a third bonding pad on the third wiring layer. A third substrate includes a fifth side opposite to the fourth side. A fifth gate electrode is on the fifth side of the third substrate. A fourth wiring structure is on the fifth side of the third substrate. The fourth wiring structure includes a fourth wiring layer and a fourth bonding pad on the fourth wiring layer. The first bonding pad directly contacts the second bonding pad. The third bonding pad directly contacts the fourth bonding pad. The floating diffusion region is connected to the impurity region and the third gate electrode through the first wiring structure and the second wiring structure.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG.1is a block diagram of an image sensing device according to some embodiments.

Referring toFIG.1, an image sensing device1according to some embodiments may include an image sensor10and an image signal processor20.

In an embodiment, the image sensor10may generate an image signal IMS, by sensing an image to be sensed using light. In some embodiments, the generated image signal IMS may be, for example, a digital signal. However, embodiments of the present disclosure are not necessarily limited thereto.

The image signal IMS may be provided to the image signal processor20and processed by the image signal processor20. In an embodiment, the image signal processor20receives the image signal IMS that is output from a buffer17of the image sensor10, and may process or treat the received image signal IMS to easily display the image signal

In some embodiments, the image signal processor20may perform digital binning on the image signal IMS that is output from the image sensor10. The image signal IMS that is output from the image sensor10may be a raw image signal from the pixel array PA without analog binning or may be the image signal IMS on which the analog binning has already been performed.

In some embodiments, the image sensor10and the image signal processor20may be positioned separately from each other as shown. For example, the image sensor10may be mounted on a first chip and the image signal processor20may be mounted on a second chip. In this embodiment, the image sensor10and the image signal processor20may communicate with each other through a predetermined interface. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment the image sensor10and the image signal processor20may be implemented as a single package, for example, a MCP (multi-chip package).

In an embodiment, the image sensor10may include a pixel array PA, a control register block11, a timing generator12, a row driver14, a readout circuit16, a ramp signal generator13, and a buffer17.

The control register block11may generally control the operation of the image sensor10. For example, the control register block11may directly transmit an operating signal to the timing generator12, the ramp signal generator13, and the buffer17.

The timing generator12may generate a signal that serves as a reference for the operating timing of various components of the image sensor10. An operating timing reference signal generated by the timing generator12may be sent to the ramp signal generator13, the row driver14, the readout circuit16, and the like.

The ramp signal generator13may generate and transmit the ramp signal that is used in the readout circuit16. For example, in an embodiment the readout circuit16may include a correlated double sampler (CDS), a comparator, or the like. The ramp signal generator13may generate and transmit the ramp signal that is used in the correlated double sampler, the comparator, or the like.

The row driver14may selectively activate the rows of the pixel array PA.

The pixel array PA may sense an external image. In an embodiment, the pixel array PA may include a plurality of pixels that are arranged two-dimensionally (e.g., in the form of a matrix).

In an embodiment, the readout circuit16may sample the pixel signal provided from the pixel array PA, compare the pixel signal with the ramp signal, and then convert an analog image signal (e.g., data) into a digital image signal (e.g., data) on the basis of the comparison results

The buffer17may include, for example, a latch. The buffer17may temporarily store the image signal IMS to be provided to the outside, and may transmit the image signal IMS to an external memory or an external device.

FIG.2is a circuit diagram for explaining the pixel of the image sensor according to some embodiments.

Referring toFIGS.1and2, the pixel array PA according to some embodiments may include a plurality of pixel groups PG.

In an embodiment, the pixel group PG includes first to fourth photoelectric conversion elements PD1, PD2, PD3, and PD4, first to fourth transfer transistors TX1, TX2, TX3, and TX4, a floating diffusion region FD, a dual conversion gain transistor DCX, a reset transistor RX, a source follower transistor SX, and a selection transistor AX. The first to fourth photoelectric conversion elements PD1, PD2, PD3and PD4may share the floating diffusion region FD, the dual conversion gain transistor DCX, the reset transistor RX, the source follower transistor SX, and the selection transistor AX.

Each of the first to fourth photoelectric conversion elements PD1, PD2, PD3, and PD4may generate electric charges in proportion to the amount of light incident from the outside.

The first to fourth transfer transistors TX1, TX2, TX3and TX4may include the first to fourth transfer gate electrodes TG1, TG2, TG3and TG4, respectively. Sources of the first to fourth transfer transistors TX1, TX2, TX3, and TX4may be connected to the first to fourth photoelectric conversion elements PD1, PD2, PD3, and PD4, respectively, and drains of each of the first to fourth transfer transistors TX1, TX2, TX3, and TX4may be connected to the floating diffusion region FD. For example, the first to fourth transfer transistors TX1, TX2, TX3, and TX4may share the floating diffusion region FD as a drain. Electric charges generated by the respective first to fourth photoelectric conversion elements PD1, PD2, PD3and PD4are transmitted to the floating diffusion region FD by the respective first to fourth transfer transistors TX1, TX2, TX3and TX4, and may be accumulated in the floating diffusion region FD. The floating diffusion region FD is a region for switching the electric charges to voltage, and has a parasitic capacitance, and the electric charges may be accumulatively stored.

The source follower transistor SX including the source follower gate electrode SF amplifies the change in electric potential of the floating diffusion region FD that has received the electric charges from the first to fourth photoelectric conversion elements PD1, PD2, PD3, and PD4, and outputs it to an output line VOUT. The source follower gate electrode SF may be connected to the floating diffusion region FD. In an embodiment, the drain of the source follower transistor SX may be connected to the power supply voltage VDD, and the source of the source follower transistor SX may be connected to the drain of the selection transistor AX. When the source follower transistor SX is turned on, the power supply voltage VDD supplied to the drain of the source follower transistor SX may be sent to the drain of the selection transistor AX.

The selection transistor AX including the selection gate electrode SEL may select a pixel to be read in units of a row. When the selection transistor AX is turned on, the power supply voltage VDD connected to the drain of the selection transistor AX may be sent to the output line VOUT.

The dual conversion gain transistor DCX may adjust a conversion gain. In an embodiment, the drain of the dual conversion gain transistor DCX may be connected to the source of the reset transistor RX, and the source of the dual conversion gain transistor DCX may be connected to the floating diffusion region FD. In an embodiment, the dual conversion gain transistor DCX including the dual conversion gain gate electrode DCG may be, for example, turned on in a high illumination mode, and turned off in a low illumination mode.

The reset transistor RX including the reset gate electrode RG may periodically reset the floating diffusion region FD. When the reset transistor RX and the dual conversion gain transistor DCX are turned on, the power supply voltage VDD supplied to the drain of the reset transistor RX may be sent to the floating diffusion region FD.

FIG.3is a perspective view of an image sensor according to some embodiments.

Referring toFIGS.1to3, an image sensor10according to some embodiments may include a first semiconductor chip100, a second semiconductor chip200, and a third semiconductor chip300that are stacked in order (e.g., consecutively stacked in a third direction Z). The first semiconductor chip100may be disposed above the second semiconductor chip200, and the second semiconductor chip200may be disposed above the third semiconductor chip300. The first semiconductor chip100may be called an upper board, the second semiconductor chip200may be called a middle board, and the third semiconductor chip300may be called a lower board. Hereinafter, the upper surface, the lower surface, the upper side, and the lower side may be based on the third direction Z.

The first semiconductor chip100and the second semiconductor chip200may include a pixel array PA. The pixel array PA may include a first pixel array30and a second pixel array40. For example, the first semiconductor chip100may include the first pixel array30, and the second semiconductor chip200may include the second pixel array40. In an embodiment, the first pixel array30may include first to fourth pixels PX1, PX2, PX3, and PX4and a floating diffusion region FD. The second pixel array40may include a dual conversion gain transistor DCX, a reset transistor RX, a source follower transistor SX, and a selection transistor AX.

In an embodiment, the third semiconductor chip300may include a logic region50in which logic elements are disposed. The logic elements included in the logic region50are electrically connected to the pixel array PA, and may provide signals to the pixels or process signals output from the pixels. In an embodiment, the logic region50may include, for example, a control register block11, a timing generator12, a ramp signal generator13, a row driver14, a readout circuit16, and the like.

FIG.4is a layout diagram of an image sensor according to some embodiments.

Referring toFIG.4, the image sensor according to some embodiments may include a sensor array region SAR, a connecting region CR, and a pad region PR.

The sensor array region SAR may include a region corresponding to the pixel array PA ofFIG.1. The sensor array region SAR may include a pixel array PA and a light shielding region OB. The active pixels that receive light to generate an active signal may be arranged in the pixel array PA. The optical black pixels that block light and generate optical black signals may be arranged in the light shielding region OB. The light shielding region OB may be formed, for example, along the periphery of the pixel array PA. For example, in an embodiment, the light shielding region OB may completely surround the pixel array PA (e.g., in the X and Y directions). However, embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, dummy pixels may be formed in the pixel array PA adjacent to the light shielding region OB.

The connecting region CR may be formed around the sensor array region SAR. For example, the connecting region CR may be formed on one side of the sensor array region SAR. For example, in an embodiment shown inFIG.4the connecting region CR is formed on the right side of the sensor region SAR (e.g., in the X direction). However, embodiments of the present disclosure are not necessarily limited thereto. Wirings may be formed in the connecting region CR, and may be configured to transmit and receive electrical signals of the sensor array region SAR.

The pad region PR may be formed around the sensor array region SAR. For example, the pad region PR may be formed to be adjacent to at least one edge of the image sensor according to some embodiments. The pad region PR may be connected to an external device or the like, and may be configured to transmit and receive electrical signals between the image sensor and the external device.

Although the connecting region CR is shown as being interposed between the sensor array region SAR and the pad region PR, this is merely an example. The positioning of the sensor array region SAR, the connecting region CR and the pad region PR may vary in some embodiments.

FIGS.5to7are enlarged views of the region R ofFIG.4.FIG.8is a cross-sectional view taken along a line A-A′ ofFIGS.5to7.FIG.5is an enlarged view of the region R on the first substrate110of the first semiconductor chip100,FIG.6is an enlarged view of the region R on the third side210aof the second substrate210of the second semiconductor chip200, andFIG.7is an enlarged view of the region R on the fourth side210bof the second substrate210of the second semiconductor chip200.

Referring toFIGS.2and5to8, the pixel array PA of the image sensor according to some embodiments may include a plurality of pixel groups PG. In an embodiment, the plurality of pixel groups PG may include the first to fourth pixels PX1, PX2, PX3, and PX4, the floating diffusion region FD, the dual conversion gain transistor DCX, the reset transistor RX, the source follower transistor SX, and the selection transistor AX. Each of the first to fourth pixels PX1, PX2, PX3and PX4may include respective first to fourth photoelectric conversion elements PD1, PD2, PD3and PD4and respective first to fourth transfer transistors TX1, TX2, TX3and TX4.

The image sensor according to some embodiments may include a first substrate110, a floating diffusion region FD, a pixel isolation pattern120, first to fourth photoelectric conversion elements PD1, PD2, PD3, and PD4, and first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4, a first insulating layer140, a grid pattern150, a first protective layer155, a second insulating layer160, a color filter170, a microlens180, a second protective layer185, a dual conversion gain gate electrode DCG, a source follower gate electrode SF, a reset gate electrode RG, a selection gate electrode SEL, a second substrate210, a third substrate310, and first to fourth wiring structures IS1, IS2, IS3and IS4.

The first substrate110may include a first side110aand a second side110bthat are opposite to each other (e.g., in the Z direction). The first side110amay be called a front side of the first substrate110, and the second side110bmay be called a back side of the first substrate110. In an embodiment, the first and second directions X and Y may intersect each other, and may be parallel to the first side110aof the first substrate110. The third direction Z may intersect the first and second directions X and Y, and may be perpendicular to the first side110aof the first substrate110.

In some embodiments, the second side110bof the first substrate110may be a photo receiving surface on which light is incident. For example, an image sensor according to some embodiments may be a back illuminated (BSI) image sensor.

The first substrate110may be a semiconductor substrate. For example, in an embodiment the first substrate110may be bulk silicon or SOI (silicon-on-insulator). In some embodiments, the first substrate110may be a silicon substrate or may include other substances, for example, silicon germanium, indium antimonide, lead tellurium compounds, indium arsenic, indium phosphide, gallium arsenide or gallium antimonide. However, embodiments of the present disclosure are not necessarily limited thereto. Alternatively, the first substrate110may have an epitaxial layer formed on a base substrate.

A pixel array of an image sensor according to some embodiments may include a plurality of pixel groups PG arranged two-dimensionally (e.g., in the form of matrix) in a plane including the first direction X and the second direction Y.

In an embodiment, the pixel group PG may include first to fourth pixels PX1, PX2, PX3, and PX4that are adjacent to each other. For example, a first pixel PX1may be adjacent to a third pixel PX3in the second direction Y, a second pixel PX2may be adjacent to the first pixel PX1in the first direction X and may be adjacent to the fourth pixel PX4in the second direction Y, and the fourth pixel PX4may be adjacent to the third pixel PX3in the first direction X. The first to fourth pixels PX1, PX2, PX3, and PX4may be arranged in two rows and two columns.

The first to fourth pixels PX1, PX2, PX3, and PX4may be formed on the first substrate110. The first to fourth photoelectric conversion elements PD1, PD2, PD3and PD4may be disposed in the first substrate110of the first to fourth pixels PX1, PX2, PX3and PX4, respectively. For example, the first substrate110may include p-type impurities (e.g., boron (B)), and the first to fourth photoelectric conversion elements PD1, PD2, PD3, and PD4may be formed by ion-implantation of n-type impurities (e.g., phosphorus (P) or arsenic (As)) into the p-type first substrate110. Hereinafter, an embodiment in which the first substrate110includes p-type impurities will be described for convenience of explanation.

In the image sensor according to some embodiments, each of the first to fourth pixels PX1, PX2, PX3, and PX4may include a first active region ACT1and a first ground region GND1.

A first element isolation layer112may be disposed in the first substrate110. For example, the first element isolation layer112may be formed by burying an insulating material in a shallow trench formed by patterning the first substrate110. The first element isolation layer112may extend from the first side110aof the first substrate110towards the second side110b, and a upper surface of the first element isolation layer112may be positioned in the first substrate110. The first element isolation layer112may surround each of the first active region ACT1and the first ground region GND1. Accordingly, the first element isolation layer112may define a first active region ACT1and a first ground region GND1.

In an embodiment, the first ground region GND1is formed by ion-implantation of P-type impurities of high-concentration into the first substrate110.

The floating diffusion region FD may be positioned between the first to fourth pixels PX1, PX2, PX3and PX4. The first to fourth pixels PX1, PX2, PX3and PX4may surround the floating diffusion region FD. The floating diffusion region FD may be disposed inside the first substrate110. The floating diffusion region FD may be positioned inside the first active region ACT1. The floating diffusion region FD may be positioned inside the first side110aof the first substrate110. In an embodiment, the floating diffusion region FD may be formed by ion-implantation of n-type impurities into the first substrate110.

The pixel isolation pattern120may separate the first to fourth pixels PX1, PX2, PX3, and PX4. The pixel isolation pattern120may surround at least a portion of the first to fourth pixels PX1, PX2, PX3, and PX4and a portion of the floating diffusion region FD from a planar viewpoint.

For example, the pixel isolation pattern120may be formed by burying an insulating material in a deep trench formed by patterning the first substrate110. The pixel isolation pattern120may pass through the first substrate110except for a region that overlaps the floating diffusion region FD in the third direction Z. The pixel isolation pattern120may be spaced apart from the floating diffusion region FD in the third direction Z. The pixel isolation pattern120may overlap the floating diffusion region FD in the third direction Z. For example, the pixel isolation pattern120may extend from the second side110btoward the first side110aand may terminate away from the first side110aand spaced apart from the floating diffusion region FD (e.g., in the third direction Z).

The pixel isolation pattern120may include a filling pattern124and a spacer layer122. In an embodiment, the filling pattern124may include, but is not necessarily limited to, a conductive material, for example, polysilicon (poly Si). The spacer layer122may extend along the side surfaces of the filling pattern124. In an embodiment, the spacer layer122may include an insulating material, for example, but is not necessarily limited to, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. The spacer layer122may be interposed between the filling pattern124and the first substrate110to electrically separate the filling pattern124and the first substrate110from each other.

The first to fourth transfer transistors TX1, TX2, TX3, and TX4may be positioned on the first side110aof the first substrate110. The first to fourth transfer gate electrodes TG1, TG2, TG3and TG4may be positioned on the first side110aof the first substrate110. The first to fourth transfer gate electrodes TG1, TG2, TG3and TG4may be positioned on the first active region ACT1of the first to fourth pixels PX1, PX2, PX3and PX4, respectively. The first to fourth transfer gate electrodes TG1, TG2, TG3and TG4may be adjacent to (e.g., in the third direction Z) the first to fourth photoelectric conversion elements PD1, PD2, PD3and PD4, respectively.

The floating diffusion region FD may be positioned in the first active region ACT1between the first to fourth transfer gate electrodes TG1, TG2, TG3and TG4. For example, the floating diffusion region FD may be positioned in the first substrate110on one side of each of the first to fourth transfer gate electrodes TG1, TG2, TG3and TG4.

The floating diffusion region FD may overlap the second substrate210in the third direction Z. The first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4may, for example, overlap the second substrate210in the third direction Z.

In some embodiments, the first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4may be vertical transfer gates. For example, at least a portion of each of the first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4may be positioned inside the first substrate110. For example, a trench extending from the first side110aof the first substrate110may be formed in the first substrate110. At least a portion of the first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4may be formed to fill the trench. Therefore, the lower surfaces of the first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4may be formed below the first side110aof the first substrate110and the upper surfaces of the first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4may be disposed inside the first substrate110.

In some embodiments, the widths of the first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4may decrease as they go away from the first side110aof the first substrate110. This may be due to the characteristics of the etching process for forming the trench.

The first wiring structure IS1may be disposed on the first substrate110. The first wiring structure IS1may be disposed on the first side110aof the first substrate110. The first wiring structure IS1may cover the first side110aof the first substrate110. The first semiconductor chip100may include a first substrate110and a first wiring structure IS1.

The first wiring structure IS1may include a first inter-wiring insulating layer195, a first wiring layer and a first bonding pad BP1in the first inter-wiring insulating layer195. The first wiring layer may include a plurality of first contacts191and192, a plurality of first wirings193, and a plurality of first vias194. The number and placement of the first wiring layers, the placement of the first bonding pad BP1, and the like are merely examples, and embodiments of the present disclosure are not necessarily limited thereto.

A first contact191may connect the first to fourth transfer gate electrodes TG1, TG2, TG3and TG4and the first wiring193to each other. The first contact192may connect the floating diffusion region FD and the first wiring193to each other. The first via194may connect the first wiring193and the first bonding pad BP1to each other.

One surface, such as a lower surface, of the first bonding pad BP1may be exposed by the first inter-wiring insulating layer195. A lower surface of the first bonding pad BP1may be positioned on substantially the same plane (e.g., in the third direction Z) as the lower surface of the first inter-wiring insulating layer195.

The second substrate210may include a fourth side210band a third side210athat are opposite to each other (e.g, in the third direction Z). The third side210aof the second substrate210may be a side that faces the first semiconductor chip100. The third side210aof the second substrate210may be opposite to the first side110aof the first substrate110(e.g., in the third direction Z).

In an embodiment, the second substrate210may be bulk silicon or silicon on insulator (SOI). The second substrate210may be a silicon substrate or may include other substances, for example, silicon germanium, indium antimonide, lead tellurium compounds, indium arsenic, indium phosphide, gallium arsenide or gallium antimonide. However, embodiments of the present disclosure are not necessarily limited thereto. Alternatively, the second substrate210may have an epitaxial layer formed on a base substrate.

The second substrate210may include a plurality of regions P. In an embodiment, one region P may correspond to one pixel group PG. The dual conversion gain transistor DCX, the source follower transistor SX, the reset transistor RX, and the selection transistor AX included in one pixel group PG may be positioned in one region P.

A portion of the region P may overlap the first to fourth pixels PX1, PX2, PX3, and PX4in the third direction Z. In an embodiment, the center of the region P may not be positioned on the same line in the third direction Z as the centers of the first to fourth pixels PX1, PX2, PX3, and PX4. For example, the region P may be biased in the first direction X relative to the first to fourth pixels PX1, PX2, PX3, and PX4. The region P may protrude from the first to fourth pixels PX1, PX2, PX3, and PX4in the first direction X.

For example, the sum of the width of the region P in the first direction X and the distance between the regions P adjacent in the first direction X may be substantially equal to the sum of the width of the first pixel PX1in the first direction X, the width of the second pixel PX2in the first direction X, and the distance between the first pixel PX1and the second pixel PX2.

The region P may be defined by a first portion235aof a third-1 inter-wiring insulating layer235, which will be described below. The first portion235aof the third-1 inter-wiring insulating layer235may surround the region P from a planar viewpoint. For example, the first portion235aof the third-1 inter-wiring insulating layer235may surround the region P in the X and Y directions. The first portion235aof the third-1 inter-wiring insulating layer235may fill a through-hole210hpenetrating through the second substrate210. The through-hole210hmay extend from the fourth side210bof the second substrate210to the third side210a.

The region P may include second active regions ACT21and ACT22, third active regions ACT31and ACT32, a second ground region GND2, and a third ground region GND3.

A second element isolation layer212and a third element isolation layer214may be further positioned inside the second substrate210. The second element isolation layer212and the third element isolation layer214may be formed, for example, by burying an insulating material in a shallow trench formed by patterning the second substrate210.

The second element isolation layer212may extend from the third side210aof the second substrate210towards the fourth side210b, and the bottom surface of the second element isolation layer212may be positioned in the second substrate210. The second element isolation layer212may surround each of the second active regions ACT21and ACT22and the second ground region GND2. Accordingly, the second element isolation layer212may define the second active regions ACT21and ACT22and the second ground region GND2. The second active regions ACT21and ACT22and the second ground region GND2may be spaced apart from each other.

The third element isolation layer214may extend from the fourth side210bof the second substrate210towards the third side210a, and the upper surface of the third element isolation layer214may be positioned in the second substrate210. The third element isolation layer214may surround each of the third active regions ACT31and ACT32. Accordingly, the third element isolation layer214may define the third active regions ACT31and ACT32and the third ground region GND3. The third active regions ACT31and ACT32and the third ground region GND3may be spaced apart from each other.

In an embodiment, the second ground region GND2and the third ground region GND3may be formed by ion-implantation of high-concentration P-type impurities into the second substrate210.

In an embodiment, the dual conversion gain transistor DCX and the source follower transistor SX may be positioned on the third side210aof the second substrate210. The entire dual conversion gain transistor DCX and the entire source follower transistor SX may overlap the second substrate210in the third direction Z. The dual conversion gain gate electrode DCG and the source follower gate electrode SF may be positioned on the third side210aof the second substrate210. The dual conversion gain gate electrode DCG may be positioned on the second active region ACT22above the third side210aof the second substrate210, and the source follower gate electrode SF may be positioned on the second active region ACT22above the third side210aof the second substrate210.

An impurity region213may be disposed in the second substrate210. The impurity regions213may be positioned inside the third side210aof the second substrate210. The impurity region213may be formed by implanting impurities into the second substrate210. The impurity region213may be positioned on one side of the dual conversion gain gate electrode DCG. The impurity region213may function as a source of the dual conversion gain transistor DCX.

The second wiring structure IS2may be positioned on the second substrate210. The second wiring structure IS2may be positioned on the third side210aof the second substrate210. The second wiring structure IS2may cover the third side210aof the second substrate210.

The second wiring structure IS2may include a second inter-wiring insulating layer225, a second wiring layer and a second bonding pad BP2in the second inter-wiring insulating layer225. The second wiring layer may include a plurality of second contacts221a,221b,221cand222, a plurality of second wirings223, and a plurality of second vias224. The number of layers and placement of the second wiring layer, the placement of the second bonding pads BP2, and the like shown in an embodiment ofFIG.8are merely examples, and embodiments of the present disclosure are not necessarily limited thereto.

A second contact221amay connect the dual conversion gain gate electrode DCG and the second wiring223to each other. A second contact221bmay connect the source follower gate electrode SF and the second wiring223to each other. A second contact221cmay connect the impurity region and the second wiring223in the active region (for example, the second active region ACT22) on one side of the dual conversion gain gate electrode DCG. The impurity region connected to the second contact221cmay serve as a drain of the dual conversion gain transistor DCX. The second contact222may connect the impurity region213and the second wiring223. The second via224may connect the second wiring223and the second bonding pad BP2.

One surface, such as an upper surface, of the second bonding pad BP2may be exposed by the second inter-wiring insulating layer225. The upper surface of the second bonding pad BP2may be positioned on substantially the same plane as the upper surface of the second inter-wiring insulating layer225. The second bonding pad BP2may be in direct contact with the first bonding pad BP1exposed by the first inter-wiring insulating layer195. The second inter-wiring insulating layer225may be in directly contact with the first inter-wiring insulating layer195. The second bonding pad BP2may be bonded to the first bonding pad BP1. Therefore, the second semiconductor chip200may be bonded to the first semiconductor chip100.

The impurity region213and the source follower gate electrode SF may be electrically connected to the floating diffusion region FD through the first wiring structure IS1and the second wiring structure IS2. For example, the floating diffusion region FD may be electrically connected to the first contact191, the first wiring193, the first via194and the first bonding pad BP1. The impurity region213may be electrically connected to the second contact222, the second wiring223, the second via224, and the second bonding pad BP2. The source follower gate electrode SF may be electrically connected to the second contact222b, the second wiring223, the second via224and the second bonding pad BP2. The second bonding pad BP2may be connected to the first bonding pad BP1, and the impurity region213and the source follower gate electrode SF may be electrically connected to the floating diffusion region FD accordingly.

The reset transistor RX and the selection transistor AX may be positioned on the fourth side210bof the second substrate210. The entire reset transistor RX and the entire selection transistor AX may overlap the second substrate210in the third direction Z. The reset gate electrode RG and the selection gate electrode SEL may be positioned on the fourth side210bof the second substrate210. In an embodiment, the reset gate electrode RG may be positioned on the third active region ACT31, and the selection gate electrode SEL may be positioned on the third active region ACT32.

A third wiring structure IS3may be disposed on the second substrate210. For example, the third wiring structure IS3may be disposed on the fourth side210bof the second substrate210. The second wiring structure IS2may cover the fourth side210bof the second substrate210. In an embodiment, the second semiconductor chip200may include a second substrate210, a second wiring structure IS2, and a third wiring structure IS3.

The third wiring structure IS3may include third inter-wiring insulating layers235and236, and a third wiring layer and a third bonding pad BP3in the third inter-wiring insulating layers235and236. The third inter-wiring insulating layers235and236may include a third-1 inter-wiring insulating layer235and a third-2 inter-wiring insulating layer236. The third wiring layer may include a plurality of third contacts230,231a,231b, and231cin the third-1 inter-wiring insulating layer235, and a plurality of third wirings233, a plurality of third vias234and a third bonding pad BP3in the third-2 inter-wiring insulating layer236. The number of layers and placement of the third wiring layer, the placement of the third bonding pad BP3, and the like shown in an embodiment ofFIG.8are merely examples, and embodiments of the present disclosure are not necessarily limited thereto.

The third-1 inter-wiring insulating layer235may include a first portion235aand a second portion235b. The first portion235amay fill the through-hole210hof the second substrate210, and the second portion235bmay be disposed on the fourth side210bof the second substrate210and the first portion235a. The second portion235bmay cover the fourth side210bof the second substrate210. The third-2 inter-wiring insulating layer236may be disposed on the third-1 inter-wiring insulating layer235. For example, the third-2 inter-wiring insulating layer236may be disposed directly on a lower surface of the third-1 inter-wiring insulating layer235.

The third contact230may be positioned inside the through-hole210h. The third contact230may partially penetrate the third-1 inter-wiring insulating layer235and the second inter-wiring insulating layer225to connect the third wiring233and the second wiring223to each other. The third contact231amay connect the reset gate electrode RG and the third wiring233to each other. The third contact231bmay connect the selection gate electrode SEL and the third wiring233to each other. The third contact231cmay connect the impurity region and the third wiring233in the active region (e.g., the third active region ACT31) on one side of the reset gate electrode RG. The impurity region connected to the third contact231cmay serve as the source of the reset transistor RX. The source of the reset transistor RX may be connected to the drain of the dual conversion gain transistor DCX through the third contact231c, the third wiring233, the third contact230, the second wiring223and the second contact221c. The third via234may connect the third wiring233and the third bonding pad BP3.

One surface, such as a lower surface, of the third bonding pad BP3may be exposed by the third-2 inter-wiring insulating layer236. The lower surface of the third bonding pad BP3may be positioned on substantially the same plane as the lower surface of the third-2 inter-wiring insulating layer236.

The third substrate310may include a fifth side310athat faces the second semiconductor chip200. The fifth side310aof the third substrate310may be opposite to the fourth side210bof the second substrate210(e.g., in the third direction Z).

An impurity region that serves as a drain of the dual conversion gain transistor DCX may be positioned on one side of the dual conversion gain gate electrode DCG in the second substrate210, and an impurity region that serves as the source of the reset transistor RX may be positioned on one side of the reset gate electrode RG in the second substrate210. The impurity region positioned on one side of the dual conversion gain gate electrode DCG may be connected to the impurity region positioned on one side of the reset gate electrode RG through the second wiring structure IS2and the third wiring structure IS3. An impurity region that serves as the source of the source follower transistor SX may be positioned on one side of the source follower gate electrode SF in the second substrate210, and an impurity region that serves as the drain of the selection transistor SEL may be positioned on one side of the selection gate electrode SEL in the second substrate210. The impurity region positioned on one side of the source follower transistor SX may be connected to the impurity region positioned on one side of the selection gate electrode SEL through the second wiring structure IS2and the third wiring structure IS3.

In an embodiment, the third substrate310may be bulk silicon or silicon on insulator (SOI). For example, the third substrate310may be a silicon substrate or may include other substances, for example, silicon germanium, indium antimonide, lead tellurium compounds, indium arsenic, indium phosphide, gallium arsenide or gallium antimonide. However, embodiments of the present disclosure are not necessarily limited thereto. Alternatively, the second substrate210may have an epitaxial layer formed on a base substrate

A transistor including the gate electrode312may be positioned on the fifth side310aof the third substrate310. In an embodiment, the transistor including the gate electrode312may include, for example, electronic elements that constitute the control register block11, the timing generator12, the ramp signal generator13, the row driver14, the readout circuit16, and the like ofFIG.1.

A fourth wiring structure IS4may be disposed on the third substrate310. The fourth wiring structure IS4may be disposed on the fifth side310aof the third substrate310. The fourth wiring structure IS4may cover the fifth side510aof the third substrate310. In an embodiment, the third semiconductor chip300may include a third substrate310and a fourth wiring structure IS4.

The fourth wiring structure IS4may include a fourth inter-wiring insulating layer325, and a fourth wiring layer and a fourth bonding pad BP4in the fourth inter-wiring insulating layer325. The fourth wiring layer may include a plurality of fourth contacts321, a plurality of fourth wirings323and a plurality of fourth vias324. The number of layers and placement of the fourth wiring layer, the positioning of the fourth bonding pads BP4, and the like shown in an embodiment ofFIG.8are merely examples, and embodiments of the present disclosure are not necessarily limited thereto.

A fourth contact321may connect the gate electrode312and the fourth wiring323to each other. The fourth via324may connect the fourth wiring323and the fourth bonding pad BP4to each other.

One surface, such as an upper surface, of the fourth bonding pad BP4may be exposed by the fourth inter-wiring insulating layer325. The upper surface of the fourth bonding pad BP4may be positioned on substantially the same plane as the upper surface of the fourth inter-wiring insulating layer325. The fourth bonding pad BP4may be in direct contact with the third bonding pad BP3. The fourth inter-wiring insulating layer325may be in direct contact with the third-2 inter-wiring insulating layer236. The fourth bonding pad BP4may be bonded to the third bonding pad BP3. Therefore, the third semiconductor chip300may be bonded to the second semiconductor chip200.

In an embodiment, the first inter-wiring insulating layer195, the second inter-wiring insulating layer225, the third-1 inter-wiring insulating layer235, the third-2 inter-wiring insulating layer236, and the fourth inter-wiring insulating layer325may each include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant (low-k) material having a dielectric constant lower than that of silicon oxide. However, embodiments of the present disclosure are not necessarily limited thereto.

In an embodiment, a plurality of first contacts191and192, a plurality of first wirings193, a plurality of first vias194, a first bonding pad BP1, a plurality of second contacts221a,221b,221c, and220, a plurality of second wirings223, a plurality of second vias226, a plurality of second bonding pads BP2, a plurality of third contacts231and232, a plurality of third wirings233, a plurality of third vias234, a third bonding pad BP3, a plurality of fourth contacts321, a plurality of fourth wirings323, a plurality of fourth vias324, and a fourth bonding pads BP4may each include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. However, embodiments of the present disclosure are not necessarily limited thereto. For example, the first bonding pad BP1and the second bonding pad BP2, and the third bonding pad BP3and the fourth bonding pad BP4may each include the same material.

A gate dielectric layer132may be disposed between the first substrate110and the first to fourth transfer gate electrodes TG1, TG2, TG3and TG4. The gate dielectric layer132may be disposed between the second substrate210and the dual conversion gain gate electrode DCG, and between the second substrate210and the source follower gate electrode SF. The gate dielectric layer132may be disposed between the second substrate210and the reset gate electrode RG, and between the second substrate210and the selection gate electrode SEL. The gate dielectric layer132may be disposed between the third substrate310and the gate electrode312.

In an embodiment, the gate dielectric layer132may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant (low-k) material having a dielectric constant lower than that of silicon oxide. However, embodiments of the present disclosure are not necessarily limited thereto.

A gate spacer134may be positioned on each side surface of the first to fourth transfer gate electrodes TG1, TG2, TG3and TG4, the dual conversion gain gate electrode DCG, the source follower gate electrode SF, the reset gate electrode RG, and the selection gate electrode SEL.

The first insulating layer140may be disposed on the second side110bof the first substrate110. The first insulating layer140may extend along the second side110bof the first substrate110. In some embodiments, at least a portion of the first insulating layer140may be in direct contact with the pixel isolation pattern120.

The first insulating layer140may include an insulating material. For example, in an embodiment the first insulating layer140may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and combinations thereof. However, embodiments of the present disclosure are not necessarily limited thereto.

The color filter170may be disposed on the first insulating layer140. The color filter170may be arranged to correspond to each of the first to fourth pixels PX1, PX2, PX3, and PX4. For example, the plurality of color filters170may be arranged two-dimensionally (e.g., in the form of a matrix) in a plane that includes the first direction X and the second direction Y.

For example, in an embodiment the color filter170may be arranged in a Bayer pattern that includes a red color filter, a green color filter, and a blue color filter. As another example, the color filter170may include a yellow filter, a magenta filter, and a cyan filter, and may further include a white filter. However, embodiments of the present disclosure are not necessarily limited thereto and the arrangement of the color filter170may further vary.

A grid pattern150may be positioned between the color filters170. The grid pattern150may be positioned on the first insulating layer140. The grid pattern150may be formed in a grid pattern from a planar viewpoint and may be interposed between the color filters170.

In an embodiment, the grid pattern150may include a conductive pattern151and a low refractive index pattern153. The conductive pattern151and the low refractive index pattern153may be, for example, sequentially stacked on the first insulating layer140.

The conductive pattern151may include a conductive material. For example, in an embodiment the conductive pattern151may include at least one of titanium (Ti), titanium nitride (TIN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof. The low refractive index pattern153may include a low refractive index material having a lower refractive index than silicon (Si). For example, the low refractive index pattern153may include at least one compound selected from silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof.

A first protective layer155may be disposed on the first insulating layer140and the grid pattern150. For example, the first protective layer155may conformally extend along profiles of the upper surface of the first insulating layer140and the side and upper surfaces of the grid pattern150. In an embodiment, the first protective layer155may include, for example, aluminum oxide.

A second insulating layer160may be disposed on the color filter170. The second insulating layer160may cover the color filter170. The second insulating layer160may include an insulating material. For example, in an embodiment the second insulating layer160may include silicon oxide.

A microlens180may be disposed on the second insulating layer160. In an embodiment, the microlens180may be arranged to correspond to each of the first to fourth pixels PX1, PX2, PX3, and PX4. For example, the plurality of microlenses180may be arranged two-dimensionally (e.g., in the form of a matrix) in a plane including the first direction X and the second direction Y.

A second protective layer185may be disposed on the microlenses180. The second protective layer185may extend along the surface of the microlens180. The second protective layer185may include, for example, an inorganic oxide layer. For example, in an embodiment the second protective layer185may include at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and combinations thereof. However, embodiments of the present disclosure are not necessarily limited thereto. The second protective layer185may include, for example, low temperature oxide (LTO).

In the image sensor according to some embodiments, the dual conversion gain transistor DCX, the source follower transistor SX, the reset transistor RX, and the selection transistor AX may be disposed on the fourth side210band the third side210aof the second substrate210. For example, the dual conversion gain transistor DCX, the source follower transistor SX, the reset transistor RX, and the selection transistor AX may be formed, using both sides of the second substrate210without an additional substrate. In addition, since both sides of the second substrate210are used, an area in which the transistors DCX, SX, RX, and AX are formed may increase as compared to an embodiment in which the transistors DCX. SX, RX, and AX are formed on one side of the second substrate210. Also, since both sides of the second substrate210are used, the size of the image sensor may decrease as compared to an embodiment in which the transistors DCX, SX, RX, and AX are formed on one side of the second substrate210.

In the image sensor according to some embodiments, since the pixel groups PG share the floating diffusion region FD, the area of the floating diffusion region FD may increase.

In the image sensor according to some embodiments, the first to third semiconductor chips100,200, and300may be bonded by the first to fourth bonding pads BP1, BP2, BP3, and BP4. Therefore, for example, compared to an embodiment in which the first to third semiconductor chips100,200, and300are bonded by the use of a deep contact extending from the first substrate110to the second substrate210, the degree of freedom in design in which the transistors and the like are positioned on the second substrate210may increase.

Further, for example, in an embodiment in which the floating diffusion region FD of the first substrate110, and the dual conversion gain transistor DCX and the source follower transistor SX of the second substrate210are connected using the deep contact extending from the first substrate110to the second substrate210, the parasitic capacitance may increase due to the length of the dip contact, and the conversion gain may decrease accordingly. However, in the image sensor according to some embodiments of the present disclosure, the dual conversion gain transistor DCX and the source follower transistor SX are positioned on the third side210aof the second substrate210and connected by the first and second wiring structures IS1and IS2. Therefore, the parasitic capacitance may decrease, and the conversion gain may increase accordingly.

FIG.9is an enlarged view of the region R ofFIG.4.FIG.10is a cross-sectional view taken along a line A-A′ ofFIG.9. For convenience of explanation, the explanation will focus on points that are different from those explained usingFIGS.1to8and a repeated description of similar or identical elements may be omitted for economy of description.

Referring toFIGS.9and10, in the image sensor according to some embodiments, the first to fourth pixels PX1, PX2, PX3and PX4in the pixel group PG may include first to fourth floating diffusion regions FD1, FD2, FD3, and FD4, respectively.

The first to fourth floating diffusion regions FD1, FD2, FD3and FD4may be connected to the impurity region213of the second substrate210through the first wiring structure IS1. The first contact192may connect the first floating diffusion region FD1and the first wiring193, and the first contact192may connect the second floating diffusion region FD2and the first wiring193

FIG.11is a circuit diagram for explaining pixel of an image sensor according to some embodiments.

Referring toFIG.11, a pixel group PG of an image sensor according to some embodiments may include first to fourth photoelectric conversion elements PD1, PD2, PD3, PD4, a floating diffusion region FD, a reset transistor RX, a source follower transistor SX, and a selection transistor AX. The first to fourth photoelectric conversion elements PD1, PD2, PD3, PD4may share the floating diffusion region FD, the reset transistor RX, the source follower transistor SX and the selection transistor AX.

A source of the reset transistor RX may be connected to the floating diffusion region FD.

FIGS.12and13are enlarged views of the region R ofFIG.4.FIG.12is an enlarged view of the region R on the third side210aof the second substrate210of the second semiconductor chip200, andFIG.13is an enlarged view of the region R on the fourth side210bof the second substrate210of the second semiconductor chip200.FIG.14is a cross-sectional view taken along a line A-A′ ofFIGS.5,12and13.

Referring toFIGS.11to14, the source follower transistor SX, the reset transistor RX, and the selection transistor AX included in one pixel group PG may be positioned in one region P. In an embodiment, the region P may include second active regions ACT21and ACT22, a third active region ACT32, a second ground region GND2, and a third ground region GND3.

The reset transistor RX and the source follower transistor SX may be disposed on the third side210aof the second substrate210. The entire reset transistor RX and the entire source follower transistor SX may overlap the second substrate210in the third direction Z. The reset gate electrode RG and the source follower gate electrode SF may be disposed on the third side210aof the second substrate210. In an embodiment, the reset gate electrode RG may be disposed on the second active region ACT22on the third side210aof the second substrate210, and the source follower gate electrode SF may be disposed on the second active region ACT22on the third side210aof the second substrate210.

The selection transistor AX may be disposed on the fourth side210bof the second substrate210. The entire selection transistor AX may overlap the second substrate210in the third direction Z. The selection gate electrode SEL may be disposed on the fourth side210bof the second substrate210. The selection gate electrode SEL may be disposed on the third active region ACT32.

The impurity region213may be positioned on one side of the reset gate electrode RG. The impurity region213may serve as the source of the reset transistor RX.

FIG.15is an enlarged view of the region R ofFIG.4.

Referring toFIG.15, four pixels PX1, PX2, PX3, and PX4adjacent to each other in the image sensor according to some embodiments may share the first ground region GND1. The first ground region GND1may be positioned between four different pixel groups PG, and the four pixels PX1, PX2, PX3, and PX4adjacent to the first ground region GND1in each of the four pixel groups PG may share the first ground region GND1. In an embodiment, the first to fourth pixels PX1, PX2, PX3, and PX4that share the first ground region GND1may be included in different pixel groups PG. For example, the plurality of pixel groups PG may include a first pixel group, a second pixel group adjacent to the first pixel group in the first direction X, a third pixel group adjacent to the first pixel group in the second direction Y, and a fourth pixel group adjacent to the third pixel group in the first direction X and adjacent to the second pixel group in the second direction Y. The first ground region GND1may be positioned between the first to fourth pixel groups. The fourth pixel PX4of the first pixel group, the third pixel PX3of the second pixel group, the second pixel PX2of the third pixel group, and the first pixel PX1of the fourth pixel group may share the first ground region GND1.

FIGS.16to19are intermediate stage diagrams for explaining a method for manufacturing an image sensor according to some embodiments. The first and second pixels PX1and PX2will be described as an example.

Referring toFIG.16, the pixel isolation pattern120may be formed in the first substrate110. The first and second pixels PX1and PX2may be separated by the pixel isolation pattern120. A plurality of active regions (e.g., the first active region ACT1and the first ground region GND1) separated by the first element isolation layer112may be formed in the first substrate110. The floating diffusion region FD may be formed in the first substrate110. First and second photoelectric conversion elements PD1and PD2may be formed in the first substrate110.

In an embodiment, the first transfer transistor TX1including the first transfer gate electrode TG1and the second transfer transistor TX2including the second transfer gate electrode TG2may be formed on the first side110aof the first substrate110. The first wiring structure IS1may be formed on (e.g., formed directly below) the first side110aof the first substrate110. The first wiring structure IS1may include a first inter-wiring insulating layer195, and a plurality of first contacts191and192, a plurality of first wirings193, a plurality of first vias194, and a first bonding pad BP1inside the first inter-wiring insulating layer195. For example, in an embodiment the width of the plurality of first contacts191and192and the width of the plurality of first vias194may become smaller as they approach the first side110aof the first substrate110.

In an embodiment, the first insulating layer140, the grid pattern150, the first protective layer155, the second insulating layer160, the microlens180and the second protective layer185may be formed on the second side110bof the first substrate110.

The second substrate210that includes a sixth side210cand a third side210aopposite to each other (e.g., in the third direction Z) may be provided. A plurality of active regions (e.g., the second active regions ACT21and ACT22and the second ground region GND2) separated by the second element isolation layer212may be formed in the fourth side210bof the second substrate210. In an embodiment, the dual conversion gain transistor DCX including the dual conversion gain gate electrode DCG and the source follower transistor SX including the source follower gate electrode SF may be formed on the third side210aof the second substrate210.

The second wiring structure IS2may be formed on the third side210aof the second substrate210. The second wiring structure IS2may include the second inter-wiring insulating layer225, and the plurality of second contacts221a,221b,221c, and222, the plurality of second wirings223, the plurality of second vias224and the second bonding pad BP2inside the second inter-wiring insulating layer225. For example, in an embodiment the widths of the plurality of second contacts221a,221b,221c, and222and the widths of the plurality of second vias224may decrease as they approach the third side210aof the second substrate210.

Subsequently, the first bonding pad BP1and the second bonding pad BP2may come into direct contact with each other. The first bonding pad BP1and the second bonding pad BP2may be bonded. Therefore, the second wiring structure IS2and the first wiring structure IS1may be bonded.

Referring toFIG.17, the sixth side210cof the second substrate210may be ground. Accordingly, the second substrate210may include the fourth side210band the third side210athat are opposite to each other (e.g., in the third direction Z).

Subsequently, a plurality of active regions (e.g., the third active regions ACT31and ACT32and the third ground region GND3) separated by the third element isolation layer214may be formed in the fourth side210bof the second substrate210. The reset transistor RX including the reset gate electrode RG and the selection transistor AX including the selection gate electrode SEL may be formed on the fourth side210bof the second substrate210. A through-hole210hmay be formed in the second substrate210. The region P of the second substrate210may be defined by the through-hole210h.

Referring toFIG.18, a third-1 inter-wiring insulating layer235may be formed on the fourth side210bof the second substrate210. The first portion235aof the third-1 inter-wiring insulating layer235may fill the through-hole210h, and the second portion235bof the third-1 inter-wiring insulating layer235may cover the fourth side210bof the second substrate210. The region P of the second substrate210may be defined by the first portion235aof the third-1 inter-wiring insulating layer235.

Subsequently, a plurality of third contacts230,231a,231b, and231cmay be formed. The third contact230may partially penetrate the third-1 inter-wiring insulating layer235and the second inter-wiring insulating layer225in the through-hole210h, and may be connected to the second wiring223. The third contact231amay penetrate the third-1 inter-wiring insulating layer235and be connected to the reset gate electrode RG, and the third contact231bmay penetrate the third-1 inter-wiring insulating layer235and be connected to the selection gate electrode SEL. The third contact231cmay penetrate the third-1 inter-wiring insulating layer235and be connected to the impurity region in the active region (for example, the third active region ACT31) on one side of the reset gate electrode RG. In an embodiment, the impurity region connected to the third contact231cmay serve as the source of the reset transistor RX.

Referring toFIG.19, the third-2 inter-wiring insulating layer236, the plurality of third wirings233, the plurality of third vias234, and the third bonding pad BP3may be formed on the third-1 inter-wiring insulating layer235. Therefore, the third wiring structure IS3may be formed.

Although embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments, and may be manufactured in various forms. Those skilled in the art will appreciate that the present disclosure may be embodied in other specific forms without changing the technical spirit or essential features of the present disclosure. Accordingly, the above-described embodiments are to be considered in all respects as illustrative and not restrictive.