Semiconductor device and manufacturing method thereof

A semiconductor device includes a wiring board; a first semiconductor chip including a first surface, a second surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump; a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer parallel to the second surface of the first semiconductor chip; and a second semiconductor chip including a third surface, a fourth surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer. The upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-116296, filed on Jul. 6, 2020, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device and a manufacturing method thereof.

BACKGROUND

A package structure of a semiconductor device can include a number of memory chips are stacked above a controller chip that is flip-chip connected to a substrate. For example, a spacer chip can be provided around the controller chip and the memory chips are supported by the controller chip and the spacer chip.

However, the spacer chip may increase the assembly cost and the number of processes. Furthermore, matching heights between the controller chip and the spacer chip is challenging. If a step is generated, wettability of the memory chip in the lowermost stage deteriorates, which can deteriorate, the mold-filling property of a tunnel portion.

DETAILED DESCRIPTION

Embodiments provide a semiconductor device capable of more appropriately supporting a semiconductor chip without using a spacer chip, and a manufacturing method thereof.

In general, according to one embodiment, there is provided a semiconductor device. The semiconductor device includes a wiring board; a first semiconductor chip including a first surface, a second surface opposite to the first surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump; a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer substantially parallel to the second surface of the first semiconductor chip; and a second semiconductor chip including a third surface, a fourth surface opposite to the third surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer. The upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top.

Hereinafter, embodiments according to the present disclosure will be described with reference to the drawings. These embodiments do not limit the present disclosure. In the following embodiments, a vertical direction of a wiring board indicates a relative direction when a surface on which a semiconductor chip is mounted is facing up, and may be different from the vertical direction according to gravitational acceleration. The drawings are schematic or conceptual, and a ratio of each part is not always the same as the actual one. In the specification and the drawings, the same elements as those described above with respect to the existing drawings are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.

First Embodiment

FIG.1is a cross-sectional view illustrating a configuration example of a semiconductor device1according to the first embodiment. The semiconductor device1includes a wiring board10, semiconductor chips20,30to33, adhesive layers40to43, a metal material70, a resin layer80, a bonding wire90, and a sealing resin91. The semiconductor device1is, for example, a package of a NAND flash memory.

The wiring board10may be a printed circuit board or an interposer including a wiring layer11and an insulating layer15. For the wiring layer11, a low resistance metal such as copper, nickel or an alloy thereof is used. For the insulating layer15, an insulating material such as a glass epoxy resin is used. In the figure, the wiring layer11is provided on a front surface and a rear surface of the insulating layer15. However, the wiring board10may have a multi-layered wiring structure in which a plurality of wiring layers11and a plurality of insulating layers15are stacked. The wiring board10may have a through-electrode12penetrating the front surface and the rear surface thereof, for example, like an interposer.

On the front surface of the wiring board10, a solder resist layer14provided on the wiring layer11is provided. The solder resist layer14is an insulating layer for protecting the wiring layer11from the metal material70and preventing short-circuit defects. The solder resist layer14is provided with an opening OP, and a part of the wiring layer11and the insulating layer15are exposed from the opening OP.

The solder resist layer14provided on the wiring layer11is also provided on the rear surface of the wiring board10. A metal bump13is provided on the wiring layer11exposed from the solder resist layer14. The metal bump13electrically connects another component (not illustrated) to the wiring board10.

A semiconductor chip20is provided on the front surface side of the wiring board10. The semiconductor chip20is, for example, a controller chip that controls a memory chip. A semiconductor element (not illustrated) is provided on a surface of the semiconductor chip20facing the wiring board10. The semiconductor element may be, for example, a complementary metal oxide semiconductor (CMOS) circuit that configures a controller. An electrode pillar21electrically connected to the semiconductor element is provided on the rear surface of the semiconductor chip20. For the electrode pillar21, a low resistance metal material such as copper, nickel or an alloy thereof is used.

The electrode pillar21as a connection bump is inserted into the opening OP of the wiring board10. The metal material70is provided around the electrode pillar21. The electrode pillar21is electrically connected to the exposed wiring layer11at the opening OP through the metal material70. As the metal material70, for example, a low resistance metal material such as solder, silver, or copper is used. The metal material70, for example, covers a part of the wiring layer11of the wiring board10in the opening OP, and also covers a part of side surfaces of the electrode pillar21of the semiconductor chip20. With this configuration, the metal material70electrically connects the electrode pillar21of the semiconductor chip20and the wiring layer11of the wiring board10.

More specifically, the semiconductor chip20includes a surface20a, a surface20bopposite to the surface20a, and the electrode pillar21on the surface20a. The semiconductor chip20is connected to the wiring board10through the electrode pillar21on the surface20aside.

A resin layer (underfill)80is provided around the semiconductor chip20and between the semiconductor chip20and the wiring board10. The resin layer80is formed by curing, for example, a cured non-conductive paste (NCP), and covers and protects the periphery of the semiconductor chip20.

More specifically, the resin layer80covers the electrode pillar21between the semiconductor chip20and the wiring board10. The resin layer80is provided around the semiconductor chip20so that an upper surface S thereof is substantially parallel to the surface20bof the semiconductor chip20. As illustrated inFIG.1, the resin layer80has a substantially trapezoidal cross-sectional shape. That is, a gradient is provided at an outer peripheral end of the resin layer80. Accordingly, an area of the lower part of the resin layer80is larger than an area of the upper surface S. An upper direction of the resin layer80is an upper direction on the paper surface ofFIG.1. The lower direction of the resin layer80is the lower direction in the paper surface ofFIG.1.

The semiconductor chip30is adhered onto the semiconductor chip20through the adhesive layer40. The semiconductor chip30is, for example, a memory chip including a NAND flash memory. The semiconductor chip30includes a semiconductor element (not illustrated) on the front surface thereof. The semiconductor element may be, for example, a memory cell array and a peripheral circuit (CMOS circuit) thereof. The memory cell array may be a three-dimensional memory cell array in which a plurality of memory cells are three-dimensionally arranged. The semiconductor chip31is adhered onto the semiconductor chip30through the adhesive layer41. The semiconductor chip32is adhered onto the semiconductor chip31through the adhesive layer42. The semiconductor chip33is adhered onto the semiconductor chip32through the adhesive layer43. The semiconductor chips31to33are memory chips including a NAND flash memory, similar to the semiconductor chip30, for example. The semiconductor chips30to33may be the same memory chip. In the figure, in addition to the semiconductor chip20as the controller chip, the semiconductor chips30to33as the four memory chips are stacked. However, the number of stacked semiconductor chips may be 3 or less or 5 or more.

More specifically, the semiconductor chip30includes a surface30a, a surface30bopposite the surface30a, and the adhesive layer40on the surface30a. The semiconductor chip30is adhered to the surface20bof the semiconductor chip20and the upper surface S of the resin layer80through the adhesive layer40on the surface30aside.

The resin layer80supports the semiconductor chip30. Accordingly, a spacer is not provided between the semiconductor chip30and the wiring board10. The resin layer80is provided not only around the semiconductor chip20but also in a wide area. In the example illustrated inFIG.1, the outer peripheral end of the resin layer80is located between the outside of the semiconductor chip30and the wiring layer11(pad10p). With this configuration, when the bonding wire90is connected to a pad (see pad30pillustrated inFIG.2) of the semiconductor chip30, the semiconductor chip30can be appropriately supported. Accordingly, since the resin layer80supports the semiconductor chip30, a spacer for supporting the semiconductor chip30becomes unnecessary. In the example illustrated inFIG.1, the lower part of the semiconductor chip30is entirely filled with the resin layer80. However, a part of semiconductor chip30filled with the resin layer80is not limited thereto, and a width of the resin layer80may be narrow as long as the width of the resin layer80is within a range in which the semiconductor chip30can be supported. In this case, the sealing resin91is filled between the semiconductor chip30and the wiring board10in addition to the resin layer80.

The bonding wire90is connected to the wiring board10and any pad of the semiconductor chips30to33. In order to connect with the bonding wire90, the semiconductor chips30to33are stacked so as to be shifted by an amount of pad. Since the semiconductor chip20is flip-chip connected by the electrode pillar21, the semiconductor chip20is not wire-bonded. However, the semiconductor chip20may also be wire-bonded in addition to connection by the electrode pillar21.

Furthermore, the sealing resin91seals the semiconductor chips20,30to33, a spacer chip50, the resin layer80, the bonding wire90, and the like. With this configuration, the semiconductor device1includes a plurality of semiconductor chips20,30to33as one semiconductor package on the wiring board10.

FIG.2is a plan view illustrating an example positional relationship between the wiring board10, the semiconductor chips20and30, and the resin layer80ofFIG.1.FIG.2is a diagram seen from above the second surface of the semiconductor chip30. The cross-sectional view seen from line A-A inFIG.2corresponds toFIG.1.

20oindicates an outer edge of the semiconductor chip20.30oindicates an outer edge of the semiconductor chip30.10pindicates a pad provided on the wiring board10.30pindicates a pad provided on the surface30bof the semiconductor chip30.30s1indicates a side on which the pad30pis provided among sides of the semiconductor chip30. The side30s1is the long side of the semiconductor chip30in the example illustrated inFIG.2.30s2indicates a side of the semiconductor chip30on which the pad30pis not provided among the sides of the semiconductor chip30. The side30s1is the short side of the semiconductor chip30in the example illustrated inFIG.2.

L1indicates a distance between the side30s1and the pad10p. L2indicates the distance between the side30s2and the outer edge of the upper surface S.

The upper surface S of the resin layer80is wider than the outer edge20oof the semiconductor chip20. With this configuration, the resin layer80can appropriately surround and protect the semiconductor chip20.

The upper surface S of the resin layer80projects outside at least a part of the outer edge30oof the semiconductor chip30when viewed from above the surface30bof the semiconductor chip30. That is, the resin layer80is provided not only around the semiconductor chip20but also in a wide area. Furthermore, a part of the resin layer80is provided exceeding the outer edge30o.

The upper surface S of the resin layer80projects outside the outer edge30oon the pad30pside provided on the surface30bof the semiconductor chip30when viewed from above the surface30bof the semiconductor chip30. In the example illustrated inFIG.2, the pad30pis arranged along the side30s1of the semiconductor chip30. That is, the upper surface S of the resin layer80projects outside the side30s1.

The upper surface S of the resin layer80may be inside the outer edge30oother than the outer edge30oon the pad30pside. In the example illustrated inFIG.2, the lower part and the upper surface S of the resin layer80are inside the side30s2without projecting beyond the side30s2. That is, depending on the direction, the resin layer80may be housed inside the outer edge30o. This is because the package size and the width of the resin layer80are restricted depending on the product or the like due to the package size standard.

The resin layer80can connect the bonding wire90to the pad30pprovided on the surface30bof the semiconductor chip30supported by the upper surface S of the resin layer80, and is provided in a range up to the front of the pad10pprovided on the wiring board10and connected to the bonding wire90. In the example illustrated inFIG.2, the lower part of the resin layer80projecting to the outside of the outer edge30o(side30s1) is located so as not to exceed L1. Accordingly, the resin layer80is not in contact with the pad10p. This is because if the resin layer80is in contact with the pad10p, it becomes difficult to connect the bonding wire90to the pad10p. In the example illustrated inFIG.2, even if the upper surface S of the resin layer80is inside the side30s2, since L2is short, most of the semiconductor chip S1is supported by the upper surface S. Accordingly, the resin layer80can support the semiconductor chip30during wire bonding. If L2becomes long, there is a possibility that the semiconductor chip30is deformed during wire bonding and the bonding wire90cannot be connected. For example, when the pad30pis about 50 μm angle, L2is preferably about 200 μm or less. Accordingly, by the positional relationship described above, the resin layer80can support the semiconductor chip30during the wire bonding and is disposed so as not to be in contact with the pad10p. An upper limit distance of L2may change depending on, for example, the arrangement of the pad30p. For example, when the pad30pis provided only near the central portion of the side30s1, the upper limit distance of L2becomes long. Accordingly, the resin layer80in this case can support the semiconductor chip30even if L2is long.

In the example illustrated inFIG.2, the pad10pfor connecting to the semiconductor chips32and33is provided below the paper surface ofFIG.2. The upper surface S of the resin layer80projects outside the outer edge30oeven below the paper surface ofFIG.2.

Next, a manufacturing method of the semiconductor device1according to this embodiment will be described.

FIGS.3to12are diagrams illustrating an example of the manufacturing method of the semiconductor device1according to the first embodiment.

First, a semiconductor element is formed on a semiconductor wafer W.FIG.3is a perspective view of the semiconductor wafer W on which the semiconductor element is formed. The semiconductor element is formed on the semiconductor wafer W, and a polyimide PI covers the semiconductor element. The semiconductor wafer W includes a plurality of semiconductor chips20(or30to33) that are singulated in a dicing process described later.

Next, as illustrated inFIG.4, a protective tape TP1is attached onto the polyimide PI. Next, as illustrated inFIG.5, the rear surface of the semiconductor wafer W is polished with a grinder G with the protective tape TP1facing down.

After the protective tape TP1is peeled off, the rear surface of the semiconductor wafer W is attached to a flexible resin tape TP2stretched in a wafer ring WR as illustrated inFIG.6. Next, as illustrated inFIG.7, a laser oscillator LG is used to emit a laser beam along a dicing line on the front surface or the rear surface of the semiconductor wafer W. With this configuration, a groove is formed in the dicing line.

Next, as illustrated inFIG.8, the semiconductor wafer W is cut along the groove of the dicing line by a dicing blade DB. With this configuration, the semiconductor wafer W is singulated into the semiconductor chips20(or30to33). The singulated semiconductor chips20(or30to33) are picked up from the resin tape TP2for mounting on the wiring board10.

On the other hand, in the wiring board10, the insulating layer15, the wiring layer11, the through-electrode12, and the solder resist layer14are formed. Next, the opening OP is formed in the solder resist layer14by using a mask material formed on the solder resist layer14. In this case, the opening OP is formed so as to expose the wiring layer11and the insulating layer15around the wiring layer11.

Next, as illustrated inFIG.9, a material80aof the resin layer80is applied onto the wiring board10. As described with reference toFIG.2, a sufficient amount of material80ais applied so that the resin layer80can support the semiconductor chip20.

Next, as illustrated inFIG.10, the semiconductor chip20formed in the process illustrated inFIG.8is picked up, and the surface20aof the semiconductor chip20is made to face the wiring board10by a mount tool MT. The mount tool MT includes suction holes (not illustrated) and sucks the semiconductor chip20through a film F in which the suction holes are similarly formed. The film F prevents the material80afrom crawling up and being in contact with the mount tool MT during pressing of the material80aby the mount tool MT. This is because if the material80aenters the suction hole of the mount tool MT, the mount tool MT cannot be used as the mount tool MT. That is, the film F protects the mount tool MT. The size of the surface of the mount tool MT facing the surface20bis preferably sufficiently larger than the size of the semiconductor chip20.

Next, as illustrated inFIG.11, the semiconductor chip20and the material80aare pressed by the mount tool MT. By pressing, the material80aspreads in the lateral direction in the paper surface ofFIG.11. Accordingly, the material80acan be filled up to the end of the mount tool MT. Since the surface of the mount tool MT facing the surface20bis substantially flat, the upper surface S is also substantially flat. For example, flip-chip connection is performed by thermocompression bonding. With this configuration, the semiconductor chip20is connected to the wiring board10.

Next, although not illustrated, curing processing and plasma processing of the resin layer80are performed. By plasma processing, an adhesion property between the surface20bof the semiconductor chip20and the adhesive layer40is improved. The resin layer80shrinks due to curing. Accordingly, the upper surface S and the surface20bmay not always be exactly parallel to each other. However, the difference between the upper surface S and the surface20bis sufficiently small, and the adverse effect on the semiconductor chip20is prevented by the adhesive layer40.

That is, the electrode pillar21is connected to the wiring board10in the resin layer80by making the surface20aof the semiconductor chip20face the wiring board10and the resin layer80is cured so that the upper surface S of the resin layer80is substantially parallel to the surface20bof the semiconductor chip20. The upper surface S of the resin layer80is substantially parallel to the surface20bof the semiconductor chip20at a boundary portion B between the outer peripheral end of the semiconductor chip20and the resin layer80. This is because the material80ais pressed by the mount tool MT having a substantially flat lower surface and is filled so as to be in contact with the film F at the outer peripheral end of the semiconductor chip20.

Next, as illustrated inFIG.12, the semiconductor chip30formed in the process illustrated inFIG.8is picked up, and the semiconductor chip30is adhered to the semiconductor chip20and the resin layer80. That is, the surface30aof the semiconductor chip30is adhered to the surface20bof the semiconductor chip20and the upper surface S of the resin layer80through the adhesive layer40.

After that, adhesion of the semiconductor chips31to33, connection of the bonding wire90, and sealing of the semiconductor chips20,30to33with the sealing resin91are performed.

As described above, according to the first embodiment, the resin layer80is provided around the semiconductor chip20so that the upper surface S is substantially parallel to the surface20bof the semiconductor chip20. The upper surface S of the resin layer80projects outside at least a part of the outer edge30oof the semiconductor chip30when viewed from above the surface30bof the semiconductor chip30. For example, the resin layer80having the upper surface S having an area comparable to that of the semiconductor chip20is provided. With this configuration, the resin layer80appropriately supports the semiconductor chip20. Accordingly, the semiconductor chip30can be supported more appropriately without using the spacer chip. Since the spacer tip is not used, for example, an increase in the number of processes can be prevented.

A structure in which the memory chip covers the controller chip with a thick die attach film (DAF) without using a spacer chip is known. However, in this structure, the memory chip may be distorted in a dome shape when the controller chip is buried in the DAF. The center of the memory chip needs to be matched with the center of the controller chip. If the memory chip is shifted with respect to the controller chip, burying of the controller chip may be difficult and support of the memory chip may become difficult. As a result, the memory chip may be easily inclined. Accordingly, the memory chip may not be appropriately supported.

In contrast, in the first embodiment, the semiconductor chip20does not need to be buried, and the semiconductor chip30only needs to be adhered to the semiconductor chip20and the resin layer80. Accordingly, the degree of difficulty mounting the semiconductor chip30is low. The semiconductor chip30does not necessarily need to be arranged directly above the semiconductor chip20. Accordingly, the degree of freedom in a mounting position of the semiconductor chip30can be improved. Moreover, since the DAF (adhesive layer40) can be made thin, the material cost can be reduced.

Second Embodiment

FIGS.13A and13Bare diagrams illustrating the semiconductor device1according to the second embodiment. The second embodiment is different from the first embodiment in that an offset (shift) exists at the position of the semiconductor chip30.FIGS.13A and13Bare plan views illustrating an example of the positional relationship between the semiconductor chip30and the resin layer80, respectively. The upper surface S is omitted. The resin layer80illustrated inFIGS.13A and13Bprojects outside the entire outer edge30oof the semiconductor chip30.

In the example illustrated inFIG.13A, the center position of the semiconductor chip30substantially coincides with the center position of the semiconductor chip20and the center position of the resin layer80. On the other hand, the semiconductor chip30illustrated inFIG.13Bis shifted in the lower direction in the paper surface from the semiconductor chip30illustrated inFIG.13A. Accordingly, the center position of the semiconductor chip30is shifted from the center position of the semiconductor chip20and the center position of the resin layer80. That is, the semiconductor chip30is shifted with respect to the semiconductor chip20or the resin layer80when viewed from above the surface30bof the semiconductor chip30. More specifically, the semiconductor chip30is shifted with respect to the semiconductor chip20or the resin layer80so that the pad30pprovided on the semiconductor chip30is separated from the pad10pprovided on the wiring board10and electrically connected to the pad30p. With this configuration, for example, the distance between the pad10pand the pad30pcan be increased. By increasing the distance between the pads10pand30p, the wire bonding property can be improved.

In this way, the mounting position of the semiconductor chip30can be changed within the range in which the resin layer80can support the semiconductor chip30. Accordingly, the degree of freedom in package design can be improved.

In the structure in which the memory chip covers the controller chip with the thick DAF described above, the mounting position of the memory chip is determined by the position of the controller chip. Accordingly, the positional relationship between the pads10pand30pis also difficult to change.

In contrast, in the second embodiment, the arrangement of the semiconductor chips30can be shifted to change the distance between the pads10pand30p. In the package design, the degree of freedom in designing the position of the pad10pcan be improved.

Since other configurations of the semiconductor device1according to the second embodiment are the same as the corresponding configurations of the semiconductor device1according to the first embodiment, detailed description thereof will be omitted. The semiconductor device1according to the second embodiment can obtain the same effect as that of the first embodiment.

Third Embodiment

FIGS.14A and14Bare diagrams illustrating the semiconductor device1according to the third embodiment. The third embodiment is different from the first embodiment in that an adjusted amount of the material80aof the resin layer80is applied onto the wiring board10.FIG.14Ais a diagram illustrating an example of the material80aof the resin layer80when the applying amount is small. InFIG.14A, the upper stage illustrates a cross-sectional view, and the lower stage illustrates a plan view.FIG.14Bis a diagram illustrating an example of the material80aof the resin layer80when the applying amount is large. InFIG.14B, the upper stage illustrates a cross-sectional view, and the lower stage illustrates a plan view.

The plan views ofFIGS.14A and14Billustrate the applying process of the material80ainFIG.9. In the examples illustrated inFIGS.14A and14B, the material80ais applied in an X shape in the vicinity of the opening OP.

In the process illustrated inFIG.9, an amount of the material of the resin layer80adjusted so that the upper surface S of the resin layer80has a predetermined area is applied onto the wiring board10. In the example illustrated inFIG.14A, since the applying amount of the material80ais small, the area of the cured resin layer80becomes small. On the other hand, in the example illustrated inFIG.14B, since the applying amount of the material80ais large, the area of the cured resin layer80becomes large. The resin layer80needs to be pressed with the mount tool MT having a size in accordance with a predetermined area.

In this way, by adjusting the applying amount of the material80a, the area (volume) of the resin layer80and the area of the upper surface S of the resin layer can be adjusted.

Since the other configurations of the semiconductor device1according to the third embodiment are the same as the corresponding configurations of the semiconductor device1according to the first embodiment, detailed description thereof will be omitted. The semiconductor device1according to the third embodiment can obtain the same effect as that of the first embodiment. The semiconductor device1according to the third embodiment may be combined with the second embodiment.

Fourth Embodiment

FIGS.15A to15Dare diagrams illustrating the semiconductor device1according to the fourth embodiment. The fourth embodiment is different from the first embodiment in that the size and position of the resin layer80relative to the semiconductor chips20and30change depending on the applying position of the material80aof the resin layer80.FIG.15Ais a plan view illustrating an example of the applying position of the material80aof the resin layer80.FIG.15Bis a plan view illustrating the positional relationship between the semiconductor chip30and the resin layer80at the applying position ofFIG.15A.

In the process illustrated inFIG.9, the material of the resin layer80is applied onto the wiring board10so as to form the resin layer80at a predetermined position on the wiring board10or to form the resin layer80in a predetermined shape. In the example illustrated inFIG.15A, the material80aof the resin layer80is applied in a cross shape in the vicinity of the opening OP. The material80ais applied long in the lateral direction of the paper surface. With this configuration, as illustrated inFIG.15B, the resin layer80long in the lateral direction in the paper surface is formed.

FIG.15Cis a plan view illustrating an example of the applying position of the material80aof the resin layer80.FIG.15Dis a plan view illustrating the positional relationship between the semiconductor chip30and the resin layer80at the applying position ofFIG.15C.

In the example illustrated inFIG.15C, the material80aof the resin layer80is applied in an X shape in the vicinity of the opening OP. The material80aof the resin layer80is applied in a round shape at two points in the left direction in the paper surface and the lower direction in the paper surface away from the opening OP. With this configuration, as illustrated inFIG.15D, a long resin layer80is formed in the lower left direction in the paper surface while covering the semiconductor chip20.

In this way, the position and shape of the resin layer80can be adjusted by adjusting the applying position and coating shape of the material80a.

Since the other configurations of the semiconductor device1according to the fourth embodiment are the same as the corresponding configurations of the semiconductor device1according to the first embodiment, detailed description thereof will be omitted. The semiconductor device1according to the fourth embodiment can obtain the same effect as that of the first embodiment. The semiconductor device1according to the fourth embodiment may be combined with the second embodiment and the third embodiment.

Fifth Embodiment

FIGS.16A to16Dare diagrams illustrating the semiconductor device1according to the fifth embodiment. In the fifth embodiment, the positional relationship between the semiconductor chip30and the resin layer80is different from that in the first embodiment.FIGS.16A to16Dare plan views illustrating an example of the positional relationship between the semiconductor chip30and the resin layer80, respectively. Adjustment methods of the size and shape of the resin layer80may be the same as those of the third embodiment and the fourth embodiment, respectively.

In the example illustrated inFIG.16A, the resin layer80projects beyond the short side of the semiconductor chip30, but does not project beyond the long side of the semiconductor chip30. In the example illustrated inFIG.16B, the resin layer80projects beyond the short side of the semiconductor chip30and the long side on the upper side of the paper surface, but does not project beyond the long side of the semiconductor chip30on the lower side of the paper surface. In the example illustrated inFIG.16C, the resin layer80projects beyond the long side of the semiconductor chip30. The outer peripheral end of the resin layer80substantially coincides with the short side of the semiconductor chip30when viewed from above the semiconductor chip30. In the example illustrated inFIG.16D, the resin layer80projects beyond the long side on the lower side of the paper surface and the short side on the right side of the paper surface of the semiconductor chip30, but does not project beyond the long side on the upper side of the paper surface and the short side on the left side of the paper surface of the semiconductor chip30.

More specifically, the resin layer80is shifted with respect to the semiconductor chip20or the semiconductor chip30when viewed from above the surface30bof the semiconductor chip30. In the examples illustrated inFIGS.16B and16D, for example, the center position of the resin layer80is shifted from the center position of the semiconductor chip20and the center position of the semiconductor chip30.

In this way, only a specific side of the resin layer80may be larger or smaller than the semiconductor chip30. That is, the position and shape of the resin layer80can be changed within the range in which the resin layer80can support the semiconductor chip30. Accordingly, the degree of freedom in package design can be improved.

Since the other configurations of the semiconductor device1according to the fifth embodiment are the same as the corresponding configurations of the semiconductor device1according to the first embodiment, detailed description thereof will be omitted. The semiconductor device1according to the fifth embodiment can obtain the same effect as that of the first embodiment. The semiconductor device1according to the fifth embodiment may be combined with the second to fourth embodiments.