System and method of testing a semiconductor device and method of fabricating the semiconductor device

A semiconductor device test system may include a body providing an internal space, in which a test device is loaded, and a cover coupled to the body to cover the internal space. The cover may include a first cover including first openings two-dimensionally arranged and a second cover including second openings two-dimensionally arranged. An arrangement of the first openings may be different from an arrangement of the second openings.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2018-0087209, filed on Jul. 26, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

1. TECHNICAL FIELD

The present inventive concept relates to a system and a method of testing a semiconductor device, and in particular, to a system and a method of testing electromagnetic interference (EMI) effecting a semiconductor device.

2. DESCRIPTION OF RELATED ART

A semiconductor fabrication process is complex and necessitates inspection. Therefore, it is necessary to test a semiconductor device for defects in order to manage the quality of the manufactured semiconductor device. Examining the semiconductor device for defects allows for defect detection and therefore increased reliability of the semiconductor device yielded in a process of fabricating the semiconductor device. Reliability of the semiconductor device may also be increased by testing and evaluating electromagnetic interference characteristics of the semiconductor device.

SUMMARY

The inventive concept provides for a system and a method of testing a semiconductor device in order to increase reliability.

According to an exemplary embodiment of the present inventive concept, a semiconductor device test system may include a body forming an internal space, in which a test device is loaded. A cover is coupled to the body to cover the internal space. The cover may further include a first cover including an array of first openings and a second cover including an array of second openings. An array of the first openings is different from an array of the second openings.

According to an exemplary embodiment of the present inventive concept, a method of testing a semiconductor device is provided. The method is performed using a semiconductor device test system including a body in which a test device is loaded. A first cover is coupled to the body and has first openings arranged in a first array. A second cover is coupled to the body and has second openings arranged in a second array different from the first array. The method includes loading the test device into the body and performing a first test process on the test device using the first cover. The method also includes performing a second test process on the test device using the second cover. The data obtained through the first and second test processes is overlapped to obtain test data on the test device.

According to exemplary embodiments of the present inventive concept, a method of fabricating a semiconductor device may include performing a packaging process on a semiconductor device. A test process may be performed on the semiconductor device after the packaging process. The performing of the test process may include loading the semiconductor device into a test socket. A first test process may be performed on the semiconductor device in which a test probe is inserted into first openings formed in a first cover covering the test socket. A second test process is performed on the semiconductor device in which a test probe is inserted into second openings which are formed in a second cover covering the test socket. The second openings are offset from the first openings when viewed from a plan view. Next, performing a step for overlapping data obtained through the first and second test processes.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the present inventive concept will now be described more fully with reference to the accompanying drawings.

FIG. 1is an exploded perspective view schematically illustrating a semiconductor device test system100according to an exemplary embodiment of the present inventive concept. In the drawings of the present specification, for convenience in illustration and description, sizes of some of illustrated elements may be different from sizes of their actual shapes. The semiconductor device test system100may be, for example, a test socket structure. The semiconductor device test system100may include a body110, pogo-pins120, a test board130, and a cover140.

The body110may be mounted on the test board130. The body110may be configured to provide an internal space112in which a test device TD is loaded. For example, the body110may have a hollow structure, but the inventive concept is not limited thereto. The body110may include a plastic material. According to an exemplary embodiment of the present inventive concept depicted inFIG. 1, a planar surface area of the test board130viewed from a plan view may be different from a planar surface area of the body110. For example, side edges of the body110may have a uniform distance from adjacent side edges of the test board130.

As shown inFIG. 1, the internal space112may be provided to correspond to the test device TD or to have the same size and shape as the test device TD, but the inventive concept is not limited thereto. According to the exemplary embodiment shown inFIG. 1, the internal space112may be a cavity formed in a side of the body110opposite to the side contacting the test board130, but the inventive concept is not limited thereto.

The pogo-pins120may be provided in the internal space112. According to an exemplary embodiment of the present inventive concept, the pogo-pins120may be disposed on a different plane than a plane of a surface of the body110. For example, the pogo pins120may be recessed from a surface of the body110in the interior of the body110. The pogo-pins120may be configured to contact respective external connection members12of the test device TD and may electrically connect the test device TD to the test board130. The test board130may include, for example, a test-purposed printed circuit board (PCB). The test device TD may be a semiconductor device. The test device TD may include a single chip10. The test device TD may further include the external connection members12provided under the single chip10. The external connection members12may be solder balls and/or solder bumps. The test device TD may include a memory chip, but the inventive concept is not limited thereto. For example, the test device TD may be a dynamic random access memory (DRAM) chip, a semiconductor package, or an electronic device (e.g., a cellular phone). In the present specification, the terms “test device” and “semiconductor device” may be used interchangeably to refer to element TD.

The cover140may be combined with the body110. The cover140may be coupled with the body110to seal the internal space112. The cover140may include a first cover142and a second cover144which may have a substantially similar width and length, but are not limited thereto.

The first cover142may include a plurality of first openings143. The first openings143may be provided to penetrate the first cover142. The first openings143may be two-dimensionally arranged in the first cover142. For example, the first openings143may be formed as rows extending in a first direction and columns extending in a second direction intersecting the first direction. Each of the first openings143may be configured to allow a test probe P, which will be described in further detail with reference toFIG. 6A, to be inserted therein. A size of each of the first openings143may be larger than or equal to a size of the test probe P. According to an exemplary embodiment of the present inventive concept, the size of the test probe P may correspond to a diameter and/or sectional area of the first openings143. The first cover142may include a plastic material. For example, the plastic material selected may be a plastic that does not exert or interact with electromagnetic forces. The second cover144may include second openings145. The second openings145may be provided to penetrate the second cover144. The second openings145may be two-dimensionally arranged in the second cover144. For example, the second openings145may be formed in rows and columns. The arrangement of the second openings145may be different from the arrangement of the first openings143. Each of the second openings145may be configured to allow the test probe P to be inserted therein. A size of each of the second openings145may be larger than or equal to the size of the test probe P. The second cover144may include a plastic material. For example, the plastic material selected may include a plastic that does not exert or interact with electromagnetic forces.

In the present specification, the arrangement of the openings may represent how the openings are arranged on a plane. For example, the arrangement of the openings may be dependent on the number and/or sizes of the openings, a distance between centers of the openings, or a density of the openings.

In addition, the semiconductor device test system100may further include a controller. The controller may be configured to control the body110, the pogo-pins120, the test board130, and the cover140. In addition, the controller may control the test probe P during a test process to be described in detail below. The controller may include a display part which is used to display a test result. Furthermore, an additional fixing part may be provided on a bottom surface of the cover140to fix the test device TD.

FIG. 2Ais a plan view illustrating a first cover142aaccording to an exemplary embodiment of the present inventive concept.FIG. 2Billustrates a second cover144aaccording to an exemplary embodiment of the present inventive concept. For comparison in area between the first or second cover142aor144aand the test device TD, a region TDR, whose area corresponds to the size of the test device TD, is illustrated inFIGS. 2A and 2B.FIG. 2Cillustrates the first cover142aofFIG. 2Aand the second cover144aofFIG. 2Boverlapping one another.FIG. 2Cillustrates the overlap between the first cover142aofFIG. 2Aand the second cover144aofFIG. 2B. First openings143aare depicted by solid lines, and second openings145aare depicted by dotted lines. The first cover142aand the second cover144awill be described in more detail with reference toFIGS. 2A to 2C.

Referring toFIG. 2A, the first cover142amay include the first openings143a. The first openings143amay be two-dimensionally arranged in the first cover142a. For example, the first openings143amay be arranged into rows extending in a first direction and columns extending in a second direction intersecting the first direction. The first openings143amay be arranged, for example, in the form of 3×3 matrix. When viewed in a plan view, a first region R1ais defined by a line connecting centers C1of outermost ones of the first openings143a. For example, a first region R1amay be delimited by a line connecting centers C1of the first openings143athat comprise the perimeter of the arrangement of first openings143a. According to an exemplary embodiment of the present inventive concept, the first region R1amay be overlapped with the test device region TDR. For example, when viewed from a plan view, the test device region TDR may have a greater planar area than the first region R1a, and thus might be only partially overlapped by the first region R1a, but the inventive concept is not limited thereto. Referring toFIG. 2B, the second cover144amay include the second openings145a. The second openings145amay be two-dimensionally arranged in the second cover144a. For example, the second openings145amay be arranged into rows extending in a first direction and columns extending in a second direction intersecting the first direction. The arrangement of the second openings145amay be different from the arrangement of the first openings143a. The number of the second openings145amay be different from the number of the first openings143a. For example, the number of the second openings145amay be greater than the number of the first openings143a. The second openings145amay be arranged in the form of 4×4 matrix.

When viewed from a plan view, the test device region TDR may be overlapped with a second region R2a, which is delimited by a line connecting centers C2of the outermost ones of the second openings145a. For example, a second region R2amay be delimited by a line connecting centers C2of the second openings145athat comprise the perimeter of the arrangement of second openings145a. In other words, a portion of the second region R2amay be overlapped with the test device region TDR. For example, the second region R2amay have a larger planar area in a plan view relative to the test device region TDR. When viewed from a plan view, the first region R1amay be overlapped with the second region R2a. In other words, when viewed from a plan view, a portion of the second region R2amay be overlapped with the first region R1a. For example, the first region R1amay have a smaller planar area than the second region R2awhen observed from a plan view.

Referring toFIG. 2C, a size of the first opening143amay be substantially the same as a size of the second opening145a. In other words, a radius r1of the first openings143amay be substantially the same as a radius r2of the second openings145a. Distances D1and D2represent distances between centers of two adjacent arbitrary openings of the first openings143ato a second opening145aadjacent thereto. Distances D1and D2may be substantially equal to each other. According to the exemplary embodiment illustrated inFIG. 2C, the first openings143aand the second openings145amay be staggered with respect to one another.

According to an exemplary embodiment of the present inventive concept, characteristics of the test device TD may be tested by inserting a test probe into each of the first openings143aand the second openings145aof the first cover142aand the second cover144a, respectively. The test probe may be inserted into the first and second openings143aand145ato contact a surface of the test device TD. The test probe may be used to test the characteristics of the test device TD at positions corresponding to the first and second openings143aand145a. Since the first openings143aand the second openings145aare offset from one another when viewed from a plan view, it is possible to reduce an average distance between regions to be tested by the test probe. Accordingly, it is possible to increase reliability and precision in the test process. In addition, it is possible to perform a test process on the test device TD without an additional soldering process, and thus, it is possible to prevent the test device TD from incurring thermal damage.

FIG. 3Aillustrates a first cover142baccording to an exemplary embodiment of the present inventive concept.FIG. 3Billustrates a second cover144baccording to an exemplary embodiment of the present inventive concept. A region TDR, whose area corresponds to the size of the test device TD, is illustrated inFIGS. 3A and 3Bto show the comparative areas of the first cover142band the second cover144bin relation to the test device TD.FIG. 3Cillustrates the first cover142bofFIG. 3Aand the second cover144bofFIG. 3Boverlapped with each other.FIG. 3Cis a plan view illustrating the overlap between the first cover142bofFIG. 3Aand the second cover144bofFIG. 3B. First openings143bare depicted by solid lines, and second openings145bare depicted by dotted lines. The first cover142band the second cover144bwill be described in more detail with reference toFIGS. 3A to 3C.

Referring toFIG. 3A, the first cover142bmay include the first openings143b. The first openings143bmay be two-dimensionally arranged in the first cover142b. The first openings143bmay be arranged in the form of 3×3 matrix. When viewed from a plan view, a first region R1bdelimited by a line connecting the centers C1of the outermost ones of the first openings143bmay be overlapped with the test device region TDR. In other words, when viewed from a plan view, a portion of the test device region TDR may be overlapped with the first region R1b.

Referring toFIG. 3B, the second cover144bmay include the second openings145b. The second openings145bmay be two-dimensionally arranged in the second cover144b. The arrangement of the second openings145bmay be different from the arrangement of the first openings143b. The number of the second openings145bmay be different from the number of the first openings143b. The number of the second openings145bmay be greater than the number of the first openings143b. The second openings145bmay be arranged in the form of 4×4 matrix.

When viewed from a plan view, the test device region TDR may be overlapped with a second region R2b. The second region R2bis delimited by a line connecting the centers C2of the outermost ones of the second openings145b. In other words, when viewed from a plan view, a portion of the second region R2bmay be overlapped with the test device region TDR. When viewed from a plan view, the first region R1bmay be overlapped with the second region R2b. For example, when viewed from a plan view, a portion of the second region R2bmay be overlapped with the first region R1b.

Referring toFIG. 3C, a size of the first opening143bmay be different from that of the second opening145b. For example, the size of the first opening143bmay be greater than the size of the second opening145b, therefore a radius r1of the first opening143bmay be different from a radius r2of the second opening145b. Distances D1and D2represent distances between centers of two adjacent arbitrary openings of the first openings143bto the second opening145badjacent thereto. Distances D1and D2may be substantially equal to each other. According to an exemplary embodiment of the present inventive concept, the first openings143band the second openings145bmay be staggered with respect to one another. However, the inventive concept is not limited thereto. For example, some of the first openings143band the second openings145bmay partially overlap one another, while others do not.

According to an exemplary embodiment of the present inventive concept, the first cover142band the second cover144bare used to test characteristics of the test device TD. Test probes of different types may be inserted into respective ones of the first openings143band ones of the second openings145b. For example, since the first openings143band the second openings145bhave different sizes, test probes of different types may be inserted into the first openings143band the second openings145bwhen the characteristics of the test device TD are tested. A type of test probe to be inserted into each of the openings may be selected based upon the purpose and effect of the test process to be performed. In addition, since the first openings143band the second openings145bhave different sizes offset from each other, it is possible to reduce an average distance between regions to be tested by the test probes. However, the present inventive concept is not limited thereto. According to an exemplary embodiment, some of the first and second openings143band145bmay partially overlap one another. Accordingly, it is possible to increase reliability and precision in the testing process.

FIG. 4Aillustrates a first cover142caccording to an exemplary embodiment of the present inventive concept.FIG. 4Billustrates a second cover144caccording to an exemplary embodiment of the present inventive concept. For comparison of the relative areas of the first and second cover142cor144cin relation to the test device TD, a region TDR is illustrated inFIGS. 4A and 4Bwith an area that corresponds to the size of the test device TD.FIG. 4Cillustrates the first cover142cofFIG. 4Aand the second cover144cofFIG. 4B, which overlap each other. InFIG. 4Cillustrating the overlap between the first cover142cofFIG. 4Aand the second cover144cofFIG. 4B, first openings143care depicted by solid lines, and second openings145care depicted by dotted lines. The first cover142cand the second cover144cwill be described in more detail with reference toFIGS. 4A to 4C.

Referring toFIG. 4A, the first cover142cmay include the first openings143c. The first openings143cmay be two-dimensionally arranged in the first cover142c. According to an exemplary embodiment of the present inventive concept, the first openings143cmay be arranged into rows extending in a first direction and columns extending in a second direction intersecting the first direction. For example, the first openings143cmay be arranged in the form of 3×3 matrix. When viewed from a plan view, a first region R1cis delimited by a line connecting the centers C1of outermost first openings143c, and may be overlapped with the semiconductor device region TDR. In other words, when viewed from a plan view, a portion of the semiconductor device region TDR may be overlapped with the first region R1c.

Referring toFIG. 4B, the second cover144cincludes the second openings145c. The second openings145cmay be two-dimensionally arranged in the second cover144c. The arrangement of the second openings145cmay be different from the arrangement of the first openings143c. The number of the second openings145cmay be different from the number of the first openings143c. The number of the second openings145cmay be greater than the number of the first openings143c.

The second cover144cmay further include third openings146. The arrangement of the third openings146may be different from the arrangement of the first openings143cand the arrangement of the second openings145c. As an example, a region of the second cover144cin which the third openings146are formed may be overlapped with a center region of the test device region TDR, and a region of the second cover144cin which the second openings145care formed may be overlapped with an edge region of the test device region TDR.

When viewed from a plan view, the test device region TDR may be overlapped with a second region R2c, which is delimited by a line connecting the centers C2of outermost second openings145c. In other words, when viewed from a plan view, a portion of the second region R2cmay be overlapped with the semiconductor device region TDR. When viewed from a plan view, a third region R3c, which is delimited by a line connecting centers C3of the outermost ones of the third openings146, may be overlapped with the test device region TDR. In other words, when viewed from a plan view, a portion of the test device region TDR may be overlapped with the third region R3c. Although not shown, when viewed from a plan view, the first region R1cmay be overlapped with the second region R2c. In other words, when viewed from a plan view, a portion of the second region R2cmay be overlapped with the first region R1c.

Referring toFIG. 4C, a radius r1of the first opening143cmay be different from a radius r2of the second opening145c. The size of the first openings143cmay be greater than the size of the second openings145c. Distances D1and D2represent distances from centers of two adjacent arbitrary openings of the first openings143cto the second opening145cadjacent thereto, and may be substantially equal to one another. A radius r3of the third opening146may be substantially equal to the radius r1of the first opening143c. According to an exemplary embodiment of the present inventive concept, the radius r3of the third opening146may be different from the radius r2of the second opening145c. For example, the size of the third opening146may be greater than the size of the second opening145c. Distances D3and D4represent distances from centers of two adjacent arbitrary openings of the first openings143cto the third opening146adjacent thereto. Distances D3and D4may be substantially equal to one another.

According to an exemplary embodiment of the present inventive concept, in the case where the first cover142cand the second cover144care used to test characteristics of the test device TD, different types of test probes may be used to test the characteristics of the test device TD. The different types of test probes may be inserted into each of the first openings143c, the second openings145c, and the third openings146. In other words, since the first openings143c, the second openings145c, and the third openings146may have different sizes, test probes of different types may be inserted into the first openings143c, the second openings145c, and the third openings146, respectively. A type of a test probe to be inserted into each of the openings may be selected based upon the purpose and effect of the test process to be performed. For example, the test probe utilized may be an E-field/H-field test probe equipped to take measurements in the x, y, and/or z planes. In addition, a density of the test probes inserted into the various openings may vary depending on a position on the test device TD. As an example, a density of test regions may be higher in the edge region of the test device TD than in the center region of the test device TD when it is necessary to more precisely perform the test process on the edge region of the test device TD rather than on the center region of the test device TD. Accordingly, it is possible to increase reliability and precision in the test process.

FIG. 5is a flow chart illustrating a process of fabricating a semiconductor device using the semiconductor device test system100ofFIG. 1.

A packaging process may be performed on a semiconductor device (S10). The semiconductor device may include a memory chip. As an example, the packaging process may include supplying an epoxy molding compound to encapsulate a memory chip, and forming a mold layer to protect the memory chip.

After the packaging process, a step to perform a test process on the semiconductor device (S20) may be performed. The test process may include a process of testing the quality and/or characteristics of the semiconductor device. As an example, the test process may include a process of testing electromagnetic interference characteristics of the semiconductor device. The test process of the semiconductor device may include a step to load a test device (S22), performing a first test process using a first cover (S24), performing a second test process using a second cover (S26), and overlapping test data obtained through the first and second test processes (S28).

FIGS. 6A to 6Dare diagrams illustrating a process of testing the semiconductor device TD using the first and second covers142aand144aofFIGS. 2A to 2C, respectively.

Referring toFIGS. 5 and 6A, the step to load the test device TD (S22) may include loading the test device TD into the internal space112of the body110of the semiconductor device test system. A handler may be provided to transport the semiconductor device TD. As an example, the semiconductor device TD may be fastened to the handler for transport by the handler.

A test probe P for the test process may be prepared. The test probe P may include a test probe tip PT, which is provided as a lower portion thereof. The test probe tip PT may directly contact the semiconductor device TD during a test process.

Referring toFIGS. 5, 6B, and 6C, the first test process may be performed on the semiconductor device TI) (S24) using the first cover142a. After loading the semiconductor device TD, the first cover142amay be coupled to the body110to cover the semiconductor device TD. The test probe P may be inserted into one of the first openings143aof the first cover142a. The test probe P may be inserted into the first opening143asuch that the test probe tip PT is in contact with a surface of the semiconductor device TD. According to an exemplary embodiment of the present inventive concept, a gap attributed to the internal space112may exist between an upper surface of the semiconductor device TD and the first cover142asuch that a lateral surface of the test probe P may be exposed in the gap while the test probe tip PT is in contact with the semiconductor device TD. The test probe P may test EMI characteristics of the semiconductor device TD at a region in contact with the test probe P. If the test process at one of the first openings143ais finished, the test probe P may be used to further perform the test process at remaining first openings143a.

Referring toFIGS. 5 and 6D, the second test process may be performed on the semiconductor device TD using the second cover144a(S26). According to an exemplary embodiment of the present inventive concept, the second cover144a(instead of the first cover142a) may be coupled to the body110to cover the semiconductor device TD situated in the internal space112. The test probe P may be inserted into one of the second openings145aof the second cover144a. The test probe P may contact the surface of the semiconductor device TD through the second openings145a. The test probe P may test EMI characteristics of the semiconductor device TD at a region in contact with the test probe P. When the test process at one of the second openings145ais finished, the test probe P may be used to perform the test process at remaining second openings145a.

The first test process and the second test processes may be similar to each other, and may be performed on the semiconductor device TD using the same test probe P.

Thereafter, test data obtained through the first and second test processes may be overlapped (S28). The test data obtained through the first test process and the second test processes may be overlapped. In other words, the test data obtained through the first and second processes may be combined to obtain a test result on the entire region of the semiconductor device TD. For example, the test result may be used to produce an intensity graph of the entire semiconductor device TD.

FIGS. 7A to 7Care diagrams illustrating a process of testing the semiconductor device TD using the first and second covers142band144bofFIGS. 3A to 3C.

Referring toFIGS. 5 and 7A, the test device TD may be loaded into the internal space112of the body110of the semiconductor device test system (S22). Test probes P1and P2may be prepared for the test process. The first test probe P1and the second test probe P2may be separate test probes that are different from each other. The test probes P1and P2may further include test probe tips PT1and PT2, respectively, each of which is provided as a lower portion of respective test probes P1and P2. Test probe tips PT1and PT2may be in direct contact with the semiconductor device TD during a test process.

Referring toFIGS. 5 and 7B, a test process may be performed on the semiconductor device TD using the first cover (S24). After loading the semiconductor device TD into the internal space112, the first cover142bmay be coupled to the body110to cover the semiconductor device TD. The first test probe P1may be inserted into one of the first openings143bof the first cover142b. The first test probe P1may contact the surface of the semiconductor device TD through the first opening143b. The first test probe P1may test EMI characteristics of the semiconductor device TD at a region in contact with the first test probe P1. When the test process at one of the first openings143bis finished, the first test probe P1may be used to perform the test process at remaining first openings143b.

Referring toFIGS. 5 and 7C, a second test process may be performed on the semiconductor device TD using the second cover144b(S26). According to an exemplary embodiment of the present inventive concept, the second cover144b(instead of the first cover142b) may be coupled to the body110to cover the semiconductor device TD situated in the internal space112. The second test probe P2may be inserted into one of the second openings145bof the second cover144b. The second test probe P2may contact the surface of the semiconductor device TI) through the second openings145b. The second test probe P2may test EMI characteristics of the semiconductor device TD at a region in contact with the second test probe P2. If the test process at one of the second openings145bis finished, the second test probe P2may be used to perform the test process at remaining second openings145b.

The first test process and the second test process may be performed on the semiconductor device TD using the test probes P1and P2, which may also be different from each other. As an example, the first test probe P1may be used to perform the test process on only a specific bandwidth, unlike the second test probe P2. According to exemplary embodiments of the present inventive concept, the first test probe P1may have a higher sensitivity compared with the second test probe P2.

Test data obtained through the first and second test processes may then be overlapped (S28). The test data obtained through the first test process and the second test process may be overlapped to obtain a test result, or test data, on the entire region of the semiconductor device TD. For example, the test result may be used to produce an intensity graph of the entire semiconductor device TD.

FIG. 8is a diagram schematically illustrating a semiconductor device test system200according to an exemplary embodiment of the present inventive concept. The semiconductor device test system200may include a body210, an internal space212, pogo-pins, a test board230, and a cover240. The cover240may include a first cover242and a second cover244. The first cover242may have first openings243. The second cover244may have second openings245. The body210, the internal space212, the test board230, and the cover240ofFIG. 8may be substantially the same as or similar to the body110, the internal space112, the test board130, and the cover140of the semiconductor device test system100described with reference toFIG. 1. A detailed description thereof will therefore be omitted. The test device TD, to which the semiconductor device test system200ofFIG. 8is used, may be an electronic device including a chip10. As an example, the test device TD may be a portable phone in which a case is opened and the chip10is exposed.

In an exemplary embodiment of the present inventive concept, the covers140and240have been described to include two covers (e.g., the first and second covers). However, according other exemplary embodiments of the present inventive concept, the covers140and240may include three or more covers. In addition, as described above, the cover140or240may be configured to have openings, whose arrangement may be changed depending on a particular test process. Furthermore, the arrangement of the openings243and245may be variously changed in consideration of characteristics of the corresponding test device TD. In an exemplary embodiment illustrated inFIG. 8, the cover240may have an irregular hexagonal shape. For example, the shape of the cover240may comprise two parallel sides spaced apart by a first width and offset from one another; a perpendicular side extending from the parallel side as a second width shorter than the first width, in which diagonal lines connect the perpendicular sides with the opposite parallel side from which they extend.

According to an exemplary embodiment of the present inventive concept, it may be possible to provide a system and a method of testing a semiconductor device to increase reliability and precision.

While exemplary embodiments of the present inventive concept has been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the accompanying claims.