Pixel output parasitic capacitance reduction and predictive settling assist

Disclosed herein are electronic devices and image sensors containing pixel arrays, layouts of electrical signal lines for such pixel arrays, and methods of pixel read out operations, including row read operations, for such pixel arrays. Layouts are disclosed that have reduced sets of shielding or ground lines. In some layouts, shielding ground lines are used only between pairs of adjacent pixel output signal lines (OSLs). Also disclosed is a method of using one OSL within a pair of adjacent pixel OSLs to provide settling assist of the pixel output signal on the other OSL of the adjacent pair of OSLs.

FIELD

The present disclosure generally relates to image or other sensors that include an array of light-gathering pixels, such as may be found in cameras of smart phones, robotic equipment, or cameras of security monitors, among others. This disclosure also generally relates to electrical connections of such pixel arrays and signaling methods over such electrical connections.

BACKGROUND

Electronic devices may include light-gathering sensors, such as image sensors in a camera, that in turn may include one or more arrays of pixels. Examples of such electronic devices include cell phones, tablet computers, personal digital assistants, security camera devices, and remotely operated equipment, among others.

Such arrays of pixels (or just “pixel arrays”) may include columns of pixels connected to output signal lines (OSLs). The pixel arrays may have ground lines interspersed with the OSLs for shielding and/or substrate connection purposes.

SUMMARY

Disclosed herein are electronic devices, image sensors, their various component systems and subsystems, and methods of their operation. The electronic devices, image sensors, or their various component systems and subsystems, may contain a light-sensing pixel array.

More specifically, described herein, in some embodiments, is a method of performing a row read operation of a pixel array of an image sensor that includes a set of electrical signal lines associated with a pair of pixel columns of the pixel array. The associated electrical signal lines associated with the pair of pixel columns may be positioned with or between the pair of pixel columns. The electrical signal lines include a first and a second pair of adjacent output signal lines (OSLs), a ground line interposed between the first pixel column and the first pair of adjacent OSLs, a ground line interposed between the first pair of adjacent OSLs and the second pair of adjacent OSLs, and a ground line interposed between the second pair of adjacent OSLs and the second pixel column. The row read operation includes applying an initial voltage to a first OSL of the first pair of adjacent OSLs and subsequently configuring a voltage of the first OSL of the first pair of adjacent OSLs to float. While the voltage of the first OSL of the first pair of adjacent OSLs floats, a signal transfer pulse is applied to a first pixel of the first pixel column. A pixel output signal of the first pixel of the first pixel column is received on a second OSL of the first pair of adjacent OSLs. A low voltage signal is applied to the first OSL of the first pair of adjacent OSLs during a pull-down time interval containing a falling edge of the signal transfer pulse.

Also described herein, and in some embodiments, is an electronic device that includes a pixel array and an electronic control system operably linked with the pixel array. The pixel array includes a first pixel column and a second pixel column adjacent to the first pixel column, and a set of electrical signal lines positioned with or between the first and second pixel columns. The electrical signal lines include: a first pair of adjacent output signal lines (OSLs), a second pair of adjacent OSLs positioned with or between the first pair of adjacent OSLs and the second pixel column, a first ground line positioned with or between the first pixel column and the first pair of adjacent OSLs, a second ground line interposed between the first pair of adjacent OSLs and the second pair of adjacent OSLs, and a third ground line positioned with or between the second pair of adjacent OSLs and the second pixel column. The electronic control system is operable to apply a row read operation to the pixel array. The row read operation includes applying an initial voltage value to a first OSL of the first pair of adjacent OSLs; applying a signal transfer pulse to a pixel in the first pixel column; receiving on a second OSL of the first pair of adjacent OSLs a pixel output signal of the pixel in the first pixel column; and applying a low voltage pulse to the first OSL of the first pair of adjacent OSLs during a pull-down time interval containing the falling edge of the signal transfer pulse.

Also described herein, and in some embodiments, is an image sensor including a pixel array and an electronic control system. The pixel array includes a first column of pixels, a second column of pixels adjacent to the first column of pixels, and a set of electrical signal lines positioned with or between the first column of pixels and the second column of pixels and extending parallel to the first column of pixels. The electrical signal lines include: four pairs of adjacent output signal lines (OSLs); a first ground line positioned with or between the first column of pixels and a first pair of adjacent OSLs; a second ground line interposed between the first pair of adjacent OSLs and a second pair of adjacent OSLs; a third ground line interposed between the second pair of OSLs and a third pair of adjacent OSLs; a fourth ground line interposed between the third pair of OSLs and a fourth pair of adjacent OSLs; and a fifth ground line positioned with or between the fourth pair of adjacent OSLs and the second column of pixels. The electronic control system is linked with the electrical signal lines of the pixel array and configured to selectively float or bias a first OSL in a pair of adjacent OSLs while receiving a pixel output signal on a second OSL in the pair of adjacent OSLs.

DETAILED DESCRIPTION

The embodiments described herein are directed to electronic devices, including but not limited to image sensors, that contain one or more arrays of light gathering picture elements (or just ‘pixels’ of ‘pixel arrays’). In such pixel arrays, each pixel may contain one or more light sensitive semiconductor elements, such as photodiodes or avalanche diodes, that receive light and convert it to an electric charge from which an electrical signal may be generated. Pixel arrays are often, but not necessarily, configured as a rectangular array of M columns and N rows, for integers M and N, which may be large (e.g., on the order of millions of pixels). Herein, two columns of pixels of a pixel array are said to be ‘adjacent’ if there are no other intervening pixels, though there may be various intervening electrical connection lines.

The electronic devices may also contain various electronic components (such as oscillators and timing elements, row or column select transistors or circuits, comparators, buffers and amplifiers, analog-to-digital and digital-to-analog converters, various processors, etc.) that may form one or more electronic control or logic (sub)systems that may control operations related to the reception of the light by the pixels, or to the transmission or processing of the electrical signals arising from light-generated charges in the pixels. Electrical signals produced by, or received from, a pixel, such as signals related to light-generated charges during an image exposure, are termed herein “pixel output signals.”

Pixel arrays and associated electronic control systems of an image sensor may be implemented on a single semiconductor wafer or ‘chip.’ Alternatively, each may be implemented on separate chips that are then joined by a ‘flip chip’ process, with electrical connections between the chips implemented by conductive paths or vias extending to the connecting interface surfaces of the two chips. An example of the latter case is used in ‘backside illuminated’ fabrication techniques for pixel arrays, in which the semiconductor structures of the pixels for the pixel array are first formed on a substrate, followed by fabrication (such as epitaxial deposition) of connection lines and/or associated electronic components above the pixel array. The pixel array is removed from the substrate and joined, on the chip side opposite to the pixel array, to the electronic control chip so that the pixel array faces a direction of incoming light.

Such pixel arrays may include multiple electrical connections, such as voltage supply lines, timing input lines, and internal component connection lines, among others. Also, the pixel arrays may contain output signal lines (OSLs) by which the electrical pixel output signals of the pixels of the pixel array are transmitted to other components of the electronic device for processing. The pixel arrays also contain ground lines, which may be held at low or zero voltage. The ground lines can provide the low or zero voltage electrical connection for the various electronic components. Also, the ground lines can provide electrical shielding to reduce interference between voltages of the electronic components and to reduce interference or noise between output signal lines.

In some pixel arrays, certain of the ground lines and OSLs (and possibly other signal lines) may be positioned parallel to the pixel columns, and positioned either below or atop a pixel column, or in a pixel-free region between adjacent columns of pixels. There may be a dielectric or other shielding layer positioned between a pixel column and any such ground line or OSL positioned below or atop the pixel column. Herein, a set of OSLs or ground lines positioned either below or atop a column of two adjacent columns of pixels, or in a pixel-free region between the two adjacent columns of pixels, and parallel to the two adjacent columns of pixels, are said to be “positioned with or between” the two adjacent pixel columns. Herein, a ground line, OSL, or pair of OSLs, is said to be “interposed between” any two of the ground lines, OSLs, or pixel columns if those two are disposed on opposite sides of that ground line, OSL, or pair of OSLs, whether that ground line, OSL, or pair of OSLs is below, atop or to the side of a pixel column. Such a structure may allow, after an image capture exposure, for pixel output signals of pixels across one or more rows to be received simultaneously onto the OSLs positioned with or between the columns of pixels. Herein, such a procedure will be termed a “row read operation.”

The ground lines, when placed in proximity to an OSL, may introduce a stray capacitance between the two lines. Such a capacitance between the two lines may reduce the transmission speed of the output signal. Also, such as in the case of a pulsed pixel output signal, the capacitance may slow a return to low voltage on the OSL at the conclusion of the pulsed output signal.

Various embodiments described herein relate to using a reduced number of ground lines in a set of electrical signal lines positioned with or between adjacent columns of a pixel array. Such a reduction may result in a decrease of the stray capacitances on the pixel array. Also, such a reduction of ground lines may allow for greater separation between the totality of OSLs and ground lines, which may also decrease the stray capacitances. The reduction of the number of ground lines may also decrease the complexity of fabrication of the pixel arrays.

In some embodiments, ground lines may be omitted between two OSLs to form an adjacent pair of OSLs. In such embodiments, during a row read operation not all OSLs may be used to carry pixel output signals. Within such a pair of adjacent OSLs, a first OSL may receive (or “carry”) a pixel output signal, while the second OSL of the adjacent pair, unused for carrying a pixel output signal, may instead be used to reduce the associated settling time (such as of a voltage) of the first OSL at the conclusion of the pixel output signal. In one embodiment, the second OSL is initially placed at either a floating or high voltage level prior to the initiation of transmission of the pixel output signal onto the first OSL. At or near the conclusion of the transmission of the pixel output signal onto the first OSL, a low voltage pulse is applied to the second OSL. After application of the low voltage pulse, the second OSL may be allowed to have a floating voltage, or may be kept at a low voltage.

Directional terminology, such as “top”, “bottom”, “upper”, “lower”, “front”, “back”, “over”, “under”, “above”, “below”, “left”, “right”, etc. is used with reference to the orientation of some of the components in some of the figures described herein. Because components in various embodiments can be positioned in a number of different orientations, directional terminology is used for purposes of illustration and is not always limiting. Directional terminology is intended to be construed broadly, and therefore should not be interpreted to preclude components being oriented in different ways. Also, as used herein, the phrase “at least one of” preceding a series of items, with the term “and” or “or” to separate any of the items, modifies the list as a whole, rather than each member of the list. The phrase “at least one of” does not require selection of at least one of each item listed; rather, the phrase allows a meaning that includes at a minimum one of any of the items, and/or one of any combination of the items, and/or one of each of the items. By way of example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” each refer to only A, only B, or only C; any combination of A, B, and C; and/or one or more of each of A, B, and C. Similarly, it may be appreciated that an order of elements presented for a conjunctive or disjunctive list provided herein should not be construed as limiting the disclosure to only that order provided.

FIGS.1A and1Bshow an example of a device100that may include an illumination projector. The device's dimensions and form factor, including the ratio of the length of its long sides to the length of its short sides, suggest that the device100is a mobile phone (e.g., a smartphone). However, the device's dimensions and form factor are arbitrarily chosen, and the device100could alternatively be any portable electronic device including, for example a mobile phone, tablet computer, portable computer, portable music player, wearable device (e.g., an electronic watch, health monitoring device, or fitness tracking device), augmented reality (AR) device, virtual reality (VR) device, mixed reality (MR) device, gaming device, portable terminal, digital single-lens reflex (DSLR) camera, video camera, vehicle navigation system, robot navigation system, or other portable or mobile device. The device100could also be a device that is semi-permanently located (or installed) at a single location.FIG.1Ashows a front isometric view of the device100, andFIG.1Bshows a back isometric view of the device100. The device100may include a housing102that at least partially surrounds a display104. The housing102may include or support a front cover106that defines a front surface of the device100, and/or a back cover108that defines a back surface of the device100(with the back surface opposite the front surface). More generically, the device100may include one or more “covers.” The front cover106may be positioned over the display104, and may provide a window through which the display104may be viewed. In some embodiments, the display104may be attached to (or abut) the housing102and/or the front cover106. In alternative embodiments of the device100, the display104may not be included and/or the housing102may have an alternative configuration.

The display104may include one or more light-emitting elements, and in some cases may be a light-emitting diode (LED) display, an organic LED (OLED) display, a liquid crystal display (LCD), an electroluminescent (EL) display, or another type of display. In some embodiments, the display104may include, or be associated with, one or more touch and/or force sensors that are configured to detect a touch and/or a force applied to a surface of the front cover106.

The various components of the housing102may be formed from the same or different materials. For example, a sidewall118of the housing102may be formed using one or more metals (e.g., stainless steel), polymers (e.g., plastics), ceramics, or composites (e.g., carbon fiber). In some cases, the sidewall118may be a multi-segment sidewall including a set of antennas. The antennas may form structural components of the sidewall118. The antennas may be structurally coupled (to one another or to other components) and electrically isolated (from each other or from other components) by one or more non-conductive segments of the sidewall118. The front cover106may be formed, for example, using one or more of glass, a crystal (e.g., sapphire), or a transparent polymer (e.g., plastic) that enables a user to view the display104through the front cover106. In some cases, a portion of the front cover106(e.g., a perimeter portion of the front cover106) may be coated with an opaque ink to obscure components included within the housing102. The back cover108may be formed using the same material(s) that are used to form the sidewall118or the front cover106. In some cases, the back cover108may be part of a monolithic element that also forms the sidewall118(or in cases where the sidewall118is a multi-segment sidewall, those portions of the sidewall118that are conductive or non-conductive). In still other embodiments, all of the exterior components of the housing102may be formed from a transparent material, and components within the device100may or may not be obscured by an opaque ink or opaque structure within the housing102.

The front cover106may be mounted to the sidewall118to cover an opening defined by the sidewall118(i.e., an opening into an interior volume, in which various electronic components of the device100, including the display104, may be positioned). The front cover106may be mounted to the sidewall118using fasteners, adhesives, seals, gaskets, or other components.

A display stack or device stack (hereafter referred to as a “stack”) including the display104may be attached (or abutted) to an interior surface of the front cover106and extend into the interior volume of the device100. In some cases, the stack may include a touch sensor (e.g., a grid of capacitive, resistive, strain-based, ultrasonic, or other type of touch sensing elements), or other layers of optical, mechanical, electrical, or other types of components. In some cases, the touch sensor (or part of a touch sensor system) may be configured to detect a touch applied to an outer surface of the front cover106(e.g., to a display surface of the device100).

In some cases, a force sensor (or part of a force sensor system) may be positioned within the interior volume above, below, and/or to the side of the display104(and in some cases within the device stack). The force sensor (or force sensor system) may be triggered in response to the touch sensor detecting one or more touches on the front cover106(or a location or locations of one or more touches on the front cover106), and may determine an amount of force associated with each touch, or an amount of force associated with a collection of touches as a whole. In some embodiments, the force sensor (or force sensor system) may be used to determine a location of a touch, or a location of a touch in combination with an amount of force of the touch. In these latter embodiments, the device100may not include a separate touch sensor.

As shown primarily inFIG.1A, the device100may include various other components. For example, the front of the device100may include one or more front-facing cameras110, speakers112, microphones, or other components114(e.g., audio, imaging, and/or sensing components) that are configured to transmit or receive signals to/from the device100. In some cases, a front-facing camera110, alone or in combination with other sensors, may be configured to operate as a bio-authentication or facial recognition sensor. The device100may also include various input devices, including a mechanical or virtual button116, which may be accessible from the front surface (or display surface) of the device100. In some embodiments, a virtual button116may be displayed on the display104and, in some cases, a fingerprint sensor may be positioned under the button116and configured to image a fingerprint through the display104. In some embodiments, the fingerprint sensor or another form of imaging device may span a greater portion, or all, of the display area.

The device100may also include buttons or other input devices positioned along the sidewall118and/or on a back surface of the device100. For example, a volume button or multipurpose button120may be positioned along the sidewall118, and in some cases may extend through an aperture in the sidewall118. In other embodiments, the button120may take the form of a designated and possibly raised portion of the sidewall118, but the button120may not extend through an aperture in the sidewall118. The sidewall118may include one or more ports122that allow air, but not liquids, to flow into and out of the device100. In some embodiments, one or more sensors may be positioned in or near the port(s)122. For example, an ambient pressure sensor, ambient temperature sensor, internal/external differential pressure sensor, gas sensor, particulate matter concentration sensor, or air quality sensor may be positioned in or near a port122.

In some embodiments, the back surface of the device100may include a rear-facing camera124that includes one or more image sensors (seeFIG.1B). A flash or light source126may also be positioned on the back of the device100(e.g., near the rear-facing camera). In some cases, the back surface of the device100may include multiple rear-facing cameras.

FIG.2Aillustrates a configuration200of example electrical components of a pixel202. The pixel202may be part of a pixel array as described herein, which in turn may be part of an image sensor in the device100, or in another electronic device. The configuration200is exemplary; in the pixel arrays of the embodiments disclosed below, the pixels of those pixel arrays may by implemented with alternative configurations of internal electrical components.

The pixel202is connected to a voltage supply201that connects to the drain of a reset (RST) transistor M1210. The pixel202includes a photodiode D1204that connects to the source of a transmit (TX) transistor M2206. The drain of the transmit transistor206is connected to a floating diffusion (FD) node208. The FD node208is connected to the source of the RST transistor210and to the gate of the output transistor M3212. The drain of the output transistor212connects to the voltage supply201, and its source connects to the drain of a row select (RS) transistor M4214. The source of the RS transistor214connects to an output signal line (OSL)218. A current source I1216may buffer the output signal from the pixel202on the OSL218. The current source216may be separate from the pixel as shown, or implemented in the pixel itself.

FIG.2Bshows a configuration220of a section of a pixel array that may be part of an image sensor. The pixel array may have N rows (the horizontal direction inFIG.2B) and M columns (the vertical direction inFIG.2B), for M and N positive integers. In the shown section of the pixel array, the left column of pixels222contains the pixels222a,222b,222c, and222d. In the shown section of the pixel array, the right column of pixels224contains the pixels224a,224b,224c, and224d. Some or all of the pixels222a-dand224a-dmay have the configuration of the pixel202ofFIG.2A, or an alternative configuration.

As shown in the configuration220, there is a set of electrical signal lines226a,226b,227a,227b,227c,227d,227e,228a, and228bpositioned with or between the left column of pixels222and right column of pixels224, and extending parallel to the direction of the left and right columns of pixels222and224. For clarity ofFIG.2Band simplicity of presentation, the electrical signal lines226a,226b,227a,227b,227c,227d,227e,228a, and228bare shown positioned between the left and right column of pixels222and224. However, as stated previously, at least some of these electrical signal lines may be positioned atop or below either of the columns of pixels222and224. The pixel array may include other electrical signal or connection lines that are not shown, such as, but not limited to, horizontally positioned row select connection lines. Herein, two electrical signal lines of any types are said to be adjacent if there are no other electrical signal lines or pixels between them.

The set of electrical signal lines includes the output signal line (OSL)226aconnected to receive pixel output signals from the pixels222band of the left column of pixels222, and the OSL226bconnected to receive pixel output signals from the pixels222aand222cof the left column of pixels222. Similarly, the set of electrical signal lines includes the OSL228aconnected to receive the pixel output signals of the pixels224band224dof the right column of pixels224, and OSL228bconnected to receive the pixel output signals of the pixels224aand224cof the right column of pixels224. In the configuration220, the set of electrical signal lines also includes the ground lines227a,227b,227c,227dand227ethat alternate with the OSLs226a-band228a-b. The ground lines227a-emay be at a low voltage. The OSLs226a-b, the OSLs228a-b, and the ground lines227a-emay connect to output/read circuitry (not shown), which may be part of an electrical control system (or subsystems) of an electronic device, such as electronic device100.224dof the right column of pixels224. In the configuration220, the set of electrical signal lines also includes the ground lines227a,227b,227c,227dand227ethat alternate with the OSLs226a-band228a-b. The ground lines227a-emay be at a low voltage. The OSLs226a-b, the OSLs228a-b, and the ground lines227a-emay connect to output/read circuitry (not shown), which may be part of an electrical control system (or subsystems) of an electronic device, such as electronic device100.

FIG.2Cshows a timing diagram230of signals that may be applied to, or received from, the pixel202ofFIG.2Aduring a pixel read operation, such as may occur in a row read operation. The ground lines227a-emay be at a low voltage during the pixel read operation. After an exposure time in which the photodiode D1204has acquired light-generated charge, the pixel read operation of the pixel202may begin with a row select (RS) signal233applied to enable the RS transistor214, as shown on the first timing graph232. After the start of the RS signal233, a reset (RST) pulse signal235is applied to the RST transistor210to reset the FD node208, as shown on the RST timing graph234. The RST pulse signal235can reset the FD node voltage to provide a clean reference for a first analog-to-digital conversion (ADC). The reset voltage239aof the FD node208is then transmitted through an RS transistor (such as RS transistor214ofFIG.2A) onto the OSL218. A first ADC may be performed by output/read circuitry exterior to the pixel202; for example, in electronic control or logic systems of the electronic device. The first ADC may be performed in the time interval from the time T1242to the time T2244aas shown on the time axis231.

After the first ADC, a transfer (TX) pulse237is applied to the transmit transistor206starting at time T2244ato transfer charge acquired by the photodiode204during the exposure to the FD node208, as shown on the third timing graph236. As shown in the fourth timing diagram238, the voltage239bbegins to fall at the FD node208during the application of the TX pulse237, which has a falling edge at time T3244b. The fifth timing graph240shows the voltage on the OSL218during the pixel read operation. After a time T4246, the voltage239cat the FD node208and the pixel output signal241on OSL218have both settled to a point at which a second ADC may be performed. The amount of light-generated charges may then be estimated based on the first and second ADCs.

In the configuration220of the pixel array shown inFIG.2B, a parallel row read operation using the signals analogous to those described in relation toFIG.2Cmay be performed concurrently that uses all four OSLs226a,226b,228aand228b. For example, a first row select signal, such as the RS signal233, may be applied concurrently to both the pixels222aand224a, and concurrently with a second row select signal, such as RS signal233, applied to both the pixels222band224b. The outputs of pixels222band224bare received onto the respective OSLs226aand228a.

FIG.3illustrates a configuration of a part of a pixel array300that includes electrical signal lines, including the output signal lines (OSLs), from left to right:306d,306c,306b, and306aconnected to respective pixels of the left column of pixels302, and OSLs308d,308c,308b, and308aconnected to respective pixels of the right pixel column304. Also, there are ground lines314a,314b,314c,314d,314e,314f,314g,314h, and314i. The ground lines314a-iare interlaced with the OSLs306a-dand308a-dso that each of the OSLs306a-dand308a-dhas a ground line adjacent to its left and right.FIG.3shows a part of two columns of pixels302and304of the pixel array300: the left column of pixels302containing pixels302a,302b,302c, and302d; and the right column of pixels304containing pixels304a,304b,304c, and304d. One skilled in the art will understand that pixel arrays may contain more columns of pixels, and that such columns may contain more than the illustrated number of pixels. For clarity of illustration, the OSLs306a-d,308a-dand ground lines314a-iare shown positioned in a pixel-free region of the pixel array between the two adjacent pixel columns302and304. However, one skilled in the art will recognize that one or more of the OSLs306a-d,308a-dand/or ground lines314a-imay be positioned atop or below either of one or both the pixel columns302and304, such as for efficiency of layout of the elements or components of the pixel array. For the configuration of the pixel array300, and subsequent configurations of the embodiments described below, the term “associated electrical signal lines” will be used to refer to OSLs positioned with or between two columns of pixels of a pixel array, and to ground lines that provide shielding to such OSLs.

The pixel array300may be a component in an image sensor configured to receive color information or images. The left column of pixels302of the pixel array300is configured with pixels302a-dthat alternate between those implemented to receive, or respond primarily to, red light (pixels302aand302c) and those configured to receive, or respond primarily to, green light (pixels302band302d). Such color reception may be implemented by color filters or lenses proximate to the light receiving surfaces of the respective pixels. The right column of pixels304is configured with pixels304a-dthat alternate between those pixels configured to receive, or respond primarily to, green light (pixels304aand304c) and those configured to receive, or respond primarily to, blue light (pixels304band304d). In other pixel arrays, a different color pattern may be used for the pixels of a pixel array.

In the shown configuration of the pixel array300, pixel302acontains multiple internal subpixel elements R0, R1, R2, R3, R4, R5, R6, and R7, one or more of which may be configured, such as with a color filter or lens, to detect or respond primarily to red light. The internal subpixel elements R0, R1, R2, R3, R4, R5, R6, and R7may contain one or more light gathering components and associated transistors, such as described in relation toFIG.2A, or may have another structure. The subpixel elements R0, R1, R2, R3, R4, R5, R6, and R7of pixel302amay each be used separately as individual pixels in a light gathering operation (e.g., during a bright light image capture event), or may operate together as a single pixel, such as by having their respective light-generated charges combined (e.g., during a dim light image capture event). The pixel302ais connected through the connection line310ato the OSL306a. Similarly, the pixel302bmay have multiple internal subpixel elements G0, G1, G2, G3, G4, G5, G6and G7with structures and functions analogous to those of R0, R1, R2, R3, R4, R5, R6, and R7. The pixel302bconnects to OSL306bthrough the connection line310b. The pixels302cand302dmay also have internal subpixel elements with analogous structures and functions, but which are not shown for simplicity of discussion. The pixels302cand302drespectively connect to through connection lines310cand310dto OSL306b. Similarly, in the right pixel column304, the pixel304a, implemented to receive or respond primarily to green light, and pixel304b, implemented to receive or respond primarily to blue light, may also have subpixel elements as just described, as also may pixels304cand304d, though such subpixel elements are not shown for pixels304cand304d. The pixel304aconnects through connection line312ato OSL308a, and pixels304b-drespectively connect through connection lines312b-dto OSL308b.

One type of row read operation is indicated inFIG.3, in which at least two parallel rows of pixels of the pixel array300have their pixels' output signals received (or just “pixels read”) concurrently. As illustrated, the row of pixel array300containing pixels302aand304ahas those pixels' output signals (S) read onto respective OSLs306aand308a. Concurrently, the row of pixel array300containing pixels302cand304chas those pixels' output signals (S) read onto respective OSLs306band308b. During such a concurrent row read operation, the OSLs,306d,306c,308dand308c, may not be in use and may be configured or biased to have a floating voltage (F). A floating voltage may, in one example, be accomplished by setting any electrical component to which the OSL is connected to have a high input and/or output impedance, though the OSL may still be connected to a voltage source through the high impedance. In a subsequent row read operation, the OSLs,306d,306c,308dand308c, may be used to receive pixel output signals of pixels in other rows of the pixel array300. In such a subsequent row read operation, the OSLs306a,306b,308b, and308amay be put at a floating voltage.

During the concurrent row read operation, the ground lines314c,314d, and314emay provide shielding, for example, to prevent interference between the pixel output signals on OSLs306band306a. A mutual capacitance between an output signal line and an adjacent ground line increases as the spacing between the two decreases. Such stray capacitances may inhibit the associated settling time of a voltage on an OSL at the end of a pixel read operation. As described herein, the signals of the OSLs306a-d, the OSLs308a-d, and the ground lines314a-imay connect to output/read circuitry (not shown).

FIG.4shows an embodiment of a section of a pixel array400containing two pixel columns222and224and the connection diagram for their associated electrical signal lines (output signal lines and ground lines)406a-b,408a-band407a-c, such as may be used in an image sensor or other electronic device. The embodiment of the pixel array400shown inFIG.4uses a reduced set of associated electrical signal lines compared to the pixel array with the configuration220shown inFIG.2B. The pixel array400may have reduced stray capacitance between the associated electrical signal lines406a-b,408a-band407a-c, by having fewer ground lines than are present in the configuration220ofFIG.2B.

The section of the pixel array shown inFIG.4shows a left column of pixels222with pixels222a,222b,222c, and222d, and a right column of pixels224with pixels224a,224b,224c, and224d, which may be as described in relation toFIG.2B. In the embodiment of the pixel array400ofFIG.4, the associated electrical signal lines include two pairs of adjacent output signal lines (OSLs): the adjacent OSLs406aand406bforming the first pair, and the adjacent OSLs408aand408bforming the second pair. In the embodiment ofFIG.4, there is no ground line interposed between adjacent OSLs406aand406b. Similarly, there is no ground line interposed between adjacent OSLs408aand408b. There is a first ground line407ainterposed between the column of pixels222a-dand the OSL406bof the first pair of OSLs. The first ground line407amay provide shielding between voltages within any of the pixels222a-dand a pixel output signal (such as a voltage) carried on either OSL406aor406b. Similarly, there is a second ground line407cinterposed between the column of pixels224a-dand the OSL408a. Further, there is a third ground line407binterposed between the first pair of OSLs406a-band the second pair of OSLs408a-b, as shown interposed between OSLs406aand408b. In the embodiment shown inFIG.4, the electrical signal lines406a-b,408a-b, and407a-cextend parallel to the two adjacent columns of pixels.

The pixels of the left and right pixel columns222and224may be configured to be responsive to specific colors, such as the pixels described in relation toFIG.3, or may be responsive to a wider range of light frequencies, such as all or most visible light frequencies. In the former case, color filters or lenses may be used to provide a color filter array pattern. The latter case may, for example, be used in pixel arrays designed to capture black and white images, or other cases of electronic devices having pixel arrays in which only the total light intensity received at a pixel is desired.

The pixel array400having the reduced configuration diagram may be part of an electronic device, such as an image sensor or image capture device. In addition to including the pixel array400, such electronic devices may include electronic control systems or subsystems that control operations of the pixel array, and receive and process the pixel output signals. Examples of such control processing operations include, but are not limited to, applying various input signals to the pixels of the pixel array, applying signals on certain of the OSLs406a-band408a-b, and performing ADC operations on the pixel output signal, as described in relation toFIGS.6and7. The electronic control system may be part of a single unit that includes the pixel array400, or it may be a separate component system or subsystem within the electronic device.

One operation that may be performed or controlled by an electronic control system is a row read operation on the pixel array400, in which the row of the pixel array400containing pixels222aand224aare concurrently selected and have their pixel output signals received onto the respective OSLs406aand408a. The lack of a ground line interposed between the OSLs406aand406ballows for the OSL406b, which does not receive a pixel output signal (or “unused”) during the row read operation, to be set at an initial voltage, or be configured (or “biased”) to have a floating voltage, (or just “float”). Configuring the voltage on the OSL406bto float may be accomplished by removing any voltage sources (such as other pixels connected to the OSL406b) connected to the OSL406bother than one voltage source with high input impedance or output impedance. This may be accomplished by configuring such voltage sources to have high input or output impedance. Similarly, the OSL408bmay be unused in the row read operation and also set at an initial voltage, or allowed to have a floating voltage. At the conclusion of a transmission of the pixel output signal onto the OSL406a, a low voltage pulse may be applied to the OSL406b. Because there is no shielding ground line interposed between OSLs406aand406b, the low voltage on OSL406bmay reduce the time of settling or leveling off of the voltage on the OSL406a. The detailed signaling for such a row read operation is presented in more detail below with respect toFIGS.6and7.

FIG.5Ashows a first embodiment of a configuration510of a section of a pixel array with associated electrical signal lines shown positioned with or between two adjacent pixel columns502and504. For comparison purposes, the configuration of the associated electrical signal lines of the pixel array300as described in relation toFIG.3is included inFIG.5Aabove the configuration510. The embodiment of a pixel array with the configuration510has four pairs of adjacent output signal lines (OSLs) for which there is no intervening ground line: (from left to right) a first pair of OSLs512dand512c, a second pair of OSLs512band512a, a third pair of OSLs514dand514c, and a fourth pair of OSLs514band514a. As previously described, one or more of the OSLs of the four pairs of adjacent OSLs512a-b,512c-d,514a-b, and514c-d, or of the ground lines511a-e, may be positioned atop or below either of the two adjacent pixel columns502and504, but that for clarity of presentation all are shown positioned in a pixel-free region between the two adjacent pixel columns502and504. The pixel columns502and504may have the same configuration of pixels as described in relation toFIG.3. In some embodiments, the pixel columns502and504may be part of a pixel array with the Bayer color filter array pattern described in relation toFIG.3. Alternatively, the pixel columns502and504may be part of a pixel array with an alternative color filter array pattern, or may be part of a pixel array without a color filter array pattern. Connection lines from the pixels of the pixel columns502and504to the four pairs of OSLs512a-b,512c-d,514c-d, and514a-bare not shown for clarity of explanation. The connection lines from the pixels of the pixel column502to respective OSLs of the OSLs512a-d, and the connection lines from the pixels of the pixel column504to respective OSLs of the OSLs514a-dmay be the same as for the configuration of the connection lines of the pixels302a-dand304a-dto the respective OSLs of the OSLs306a-d, and308a-d, or may have an alternative connection configuration.

In the configuration510, the four pairs of OSLs512c-d,512a-b,514c-d, and514a-b, and the ground lines511a,511b,511c,511d, and511eare positioned with or between, and in parallel with the direction of, the two pixel columns502and504. The ground line511amay provide shielding between the pixel column502and the first pair of OSLs512d-c, the ground line511bmay provide shielding between the first pair of OSLs512d-cand the second pair of OSLs512b-a, the ground line511cmay provide shielding between the second pair of OSLs512b-aand the third pair of OSLs514c-d, the ground line511dmay provide shielding between the third pair of OSLs514c-dand the fourth pair of OSLs514a-b, and the ground line511emay provide shielding between the fourth pair of OSLs514a-band the pixel column504.

In the configuration510, there is a first distance d1separating the OSLs within each of the four pair of OSLs512a-b,512c-d,514d-c, and514b-a. A different distance d2separates each of the ground lines511b-dfrom each of the two OSLs to which it is adjacent. In some embodiments the distance d1is greater than the distance d2.

In the configuration510, within each of the four pairs of OSLs512c-d,512a-b,514c-d, and514a-b, during at least a time interval during a row read operation, one of the OSLs therein may be reserved to have a floating voltage (F), as described in relation toFIGS.6and7. As shown in the configuration510, OSLs512c,512a,514c, and514amay be set at a floating voltage (F), for at least a part of the row read operation. The remaining OSL within each of the four pairs of OSLs512a-b,512c-d,514c-d, and514a-b, then may be used to carry a pixel output signal (S) during the row read operation. As indicated in the configuration510, during a row read operation, the two pairs of OSLs512a-band512c-dare used to receive pixel output signals (S) from pixels of the pixel column502or have a floating voltage (F), and the two pairs of OSLs514a-band514c-d, are used to receive pixel output signals (S) from pixels of the pixel column504or have a floating voltage (F). Further, in a subsequent row read operation, the OSL within a pair of adjacent OSLs that is set at the floating voltage during the first row read operation may be switched to carry a pixel output signal in the subsequent row read operation.

FIG.5Bshows a second embodiment of a configuration520of a section of a pixel array having associated electrical signal lines positioned with or between the two adjacent pixel columns502and504of a pixel array. For comparison purposes, the configuration of the electrical signal lines of the pixel array300as described in relation toFIG.3is included inFIG.5Babove the configuration520. There are four pairs of adjacent OSLs, shown from left to right: a first pair with OSLs522dand522c, a second pair with OSLs522band522a, a third pair with OSLs524dand524c, and a fourth pair with OSLs524band524a, and the ground lines521a,521b,521c,521d, and521epositioned in parallel with the direction of the two pixel columns502and504. Similar to the configuration510ofFIG.5A, the ground line521bmay provide shielding between the first pair of OSLs522c-dand the second pair of OSLs522a-b, the ground line521cmay provide shielding between the second pair of OSLs522a-band the third pair of OSLs524c-d, and the ground line521dmay provide shielding between the third pair of OSLs524c-dand the fourth pair of OSLs524a-b. The ground line521amay provide shielding between the pixel column502and the first pair of OSLs522c-d, and the ground line521emay provide shielding between the fourth pair of OSLs524a-band the second pixel column504.

The configuration520differs from the configuration510at least in that there is common distance d3523separating any two adjacent electrical signal lines (the OSLs522a-b,522c-d,524a-b,524c-d, and the ground lines521a-521e).

The signaling pattern(s) during a row read operation described for the configuration510may be used with the configuration520.

FIG.6shows a timing diagram600of control, input, and output signals of an embodiment that may be applied to, or arise from, a pixel of a pixel array, during an embodiment of a row read operation. The embodiment shown differs from the timing signals ofFIG.2C: in this embodiment and related variations, a first output signal line (OSL1) of a pair of adjacent output signal lines is used to receive an output signal from the pixel while a second output signal line (OSL2) of the pair of adjacent output signal lines is initially unused and may initially be configured to have a floating voltage but may subsequently receive a pull-down pulse. The particular control, timing, and output signals may relate to the pixel202described with respect toFIG.2A, or to a pixel having an alternative structure. Timing events shown on the time axis601apply to the horizontal axis of each of the signal axes602,604,606,608,610, and612described below. For simplicity of description, the vertical axis of each of the signal axes602,604,606,608,610, and612described will be presumed to be a voltage axis, but one skilled in the art will recognize that the one or more of the signals' values may have other units, for example, current values.

The exemplary row-select (RS) signal603shown on the row-select signal axes602initiates the row read operation by switching to a high voltage level (or just switching ‘high’). For the pixel202ofFIG.2A, the row-select signal603is applied to the gate of the output transistor212. The actual high voltage level may depend on the particular semiconductor technology used for the pixel array. Further, in alternative embodiments, an alternative row-select signal may initiate a row read operation by switching to a negative voltage level from a low voltage level, or to a low voltage level from a high voltage level. The row-select signal603remains high for the duration of the row read operation. The row-select signal603may be applied to multiple pixels in the same row of the pixel array for a concurrent row read operation of output signals from multiple pixels in the same row of the pixel array. Further, the row-select signal603may be applied to pixels in multiple rows currently in cases in which the pixel array has sufficiently many OSLs positioned with or between columns, such as described in relation toFIGS.3,5A, and5B.

After initiation of the row read operation, a reset signal605(RST) is applied to the pixel, as shown on the reset axis signal604. The reset signal605may serve to clear residual charges from a previous light exposure, such as in the FD node208of the pixel202. The exemplary reset signal605is a level voltage pulse signal, though this is not required.

After the end of the reset signal605, at a time T1620, a first analog-to-digital conversion (ADC) may be performed on the pixel's first output signal line's (OSL1) signal613a, shown on the OSL1signal axis612. The first ADC may be performed by components of an electronic control system that may be either on the same semiconductor chip as the pixel array, or on a separate (e.g., logic circuitry) chip to which the pixel array is connected.

After the conclusion of the first ADC, at time T2622, a signal transfer pulse607TX, shown on the transmit signal axis606, is applied to the pixel to allow movement of charge from the pixel's photodiode to a storage location in the pixel, such as the FD node208of pixel202.

As a result, the pixel's resulting FD node voltages609a,609b, and609c, shown on the FD node voltage axis608, varies over time. After the reset signal605, and before the time T2622when the signal transfer pulse607begins, a first FD node voltage609ais at a first voltage level, which may be related to a supply voltage of the pixel. After initiation of the charge transfer at the rising edge of the signal transfer pulse607at time T2622, the second FD node voltage609bfalls for the duration of the signal transfer pulse607. At the conclusion of the signal transfer pulse607, the third FD node voltage609cfalls to a low voltage level.

As a result of the signal transfer pulse607, the pixel's output may be received as a first output signal line's OSL1voltage signals613a,613b, and613c, as shown on the OSL1signal axis612. After completion of the reset signal605at time T1620, but before the start time T2622of the signal transfer pulse607, the OSL1voltage signal613amay have a voltage related to the reset first FD node voltage609a. After the time T2622, the OSL1voltage613bfollows the decrease of the second FD node voltage609b. After the end time T3624of the signal transfer pulse607, the OSL1voltage613csettles to a low voltage level. Though shown settling to the time axis, one skilled in the art will recognize that a settling voltage level need not be a zero voltage; it may be related to the charge transferred to the FD node (such as FD node208of pixel202).

In the embodiment of a row read operation with the signaling operations of the timing diagram600, the second output signal line (OSL2) may be used to decrease the settling time of OSL1voltage613c. As shown on the OSL2signal axis610, a first OSL2voltage611amay be a floating voltage level, in which OSL2is not connected to a supply voltage, a ground voltage, or another voltage source. The OSL2may, prior to the start of the row select signal603, have been connected to a high voltage source and then disconnected (e.g., by a transistor being switched to a high impedance state) from the high voltage source.

During a pull-down time interval containing the end time T3624of the signal transfer pulse607, the OSL2may be connected to a low voltage source to cause the OSL2voltage signal611bto have a low voltage. After the end of the pull-down time interval, the OSL2voltage signal611cmay be allowed to have a floating voltage, or may be kept connected to the low voltage source. The pull-down time interval may be only a small percentage of the duration of the signal transfer pulse607and may begin prior to the falling edge at the time T3624and conclude at subsequent time T3624. Alternatively, the pull-down time interval may begin with the falling edge of the signal transfer pulse607at time T3624.

Once the OSL1voltage613chas settled, a second ADC may be performed on the OSL1voltage613c. The difference in values of the first and second ADCs may be used to estimate an amount of light-generated charges received at the photodiode of the pixel, such as pixel202, during an image capture operation by an image sensor or electronic device containing the pixel array.

FIG.7shows a timing diagram700of some of the control, input, and output signals that may be applied to, or arise from, the pixel of the pixel array, during the embodiment of a row read operation described in relation toFIG.6, as well as another control signal VRAMPshown on the VRAMPaxis706. The time axis701of the first output signal line (OSL1) axis708applies to the transmit signal axis702, the second output signal lines (OSL2) axis704, and the VRAMPaxis706.

The transmit (TX) signal703on the transmit signal axis702may be as described for the signal transfer pulse607. The signal transfer pulse703may be a voltage pulse signal with a rising edge from a low voltage level to a high voltage level at the time T2, and returning to a low voltage level at time T3.

The second output signal line (OSL2) voltage signal705, shown on the OSL2axis704, is as described in relation toFIG.6. The OSL2voltage signal705may have a floating voltage until a pull-down time interval containing, or proximate to, the falling edge of the signal transfer pulse703. During the pull-down time interval, a low voltage level is applied to the OSL2. After the pull-down time interval, the OSL2voltage signal705may be either a floating voltage or may continue to have an applied low voltage.

The OSL1voltage signal709may have a first, approximately constant, value from the start of the row read operation up to the time T2at the start of the signal transfer pulse703. Thereafter, the OSL1voltage signal709falls due to charge transfer from the pixel's photodiode to the pixel's storage location, such as the FD node208of the pixel202. At the end of the signal transfer pulse703at time T3, the OSL1voltage signal709settles to a second value by the time T4.

The VRAMPsignal707shown on the VRAMPaxis706may be one signal input to an analog-to-digital converter, which has the OSL1voltage signal709as another input. For example, both the VRAMPsignal707and the OSL1voltage signal709may be inputs to a comparator that is a component of a ramp-compare analog-to-digital converter. At time T1a, the VRAMPsignal707rises from value L1to value L value L2, expected to be above a high voltage on the OSL1. At time T1b, the first ADC starts with the VRAMPsignal707beginning a linear decrease to the level L3at the time T2, at which time the first ADC is completed and the VRAMPsignal707returns to a high level in preparation for the second ADC. At time T2the signal transfer pulse703may occur. Though shown concurrently with the end of the first ADC, the rising edge of the signal transfer pulse703may begin after the end of the first ADC at time T2. At time T4, the VRAMPsignal707again decreases linearly to start the second ADC.

FIG.8shows an example block diagram of an electronic device800, which in some cases may be the electronic device described with reference toFIGS.1A and1B, or another type of electronic device including one or more of the image sensors having one or more pixel arrays as described herein. The electronic device800may include an electronic display802(e.g., a light-emitting display), a processor804, a power source806, a memory808or storage device, a sensor system810, an input/output (I/O) mechanism812(e.g., an input/output device, input/output port, or haptic input/output interface), and/or an illumination projector814. The processor804may control some or all of the operations of the electronic device800. The processor804may communicate, either directly or indirectly, with some or all of the other components of the electronic device800. For example, a system bus, other bus(es), or other communication mechanism816can provide communication between the electronic display802, the processor804, the power source806, the memory808, the sensor system810, the I/O mechanism812, and the illumination projector814.

The processor804may be implemented as any electronic device capable of processing, receiving, or transmitting data or instructions, whether such data or instructions is in the form of software or firmware or otherwise encoded. For example, the processor804may include a microprocessor, a central processing unit (CPU), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a controller, or a combination of such devices. As described herein, the term “processor” is meant to encompass a single processor or processing unit, multiple processors, multiple processing units, or other suitably configured computing element or elements. In some cases, the processor804may provide part or all of the processing system or processor described herein.

It should be noted that the components of the electronic device800can be controlled by multiple processors. For example, select components of the electronic device800(e.g., the sensor system810) may be controlled by a first processor and other components of the electronic device800(e.g., the electronic display802) may be controlled by a second processor, where the first and second processors may or may not be in communication with each other.

The power source806can be implemented with any device capable of providing energy to the electronic device800. For example, the power source806may include one or more batteries or rechargeable batteries. Additionally or alternatively, the power source806may include a power connector or power cord that connects the electronic device800to another power source, such as a wall outlet.

The memory808may store electronic data that can be used by the electronic device800. For example, the memory808may store electrical data or content such as, for example, audio and video files, documents and applications, device settings and user preferences, timing signals, control signals, instructions, and/or data structures or databases. The memory808may include any type of memory. By way of example only, the memory808may include random access memory, read-only memory, Flash memory, removable memory, other types of storage elements, or combinations of such memory types.

The electronic device800may also include one or more sensor systems810positioned almost anywhere on the electronic device800. The sensor system(s)810may be configured to sense one or more types of parameters, such as but not limited to, vibration; light; touch; force; heat; movement; relative motion; biometric data (e.g., biological parameters) of a user; air quality; proximity; position; connectedness; surface quality; and so on. By way of example, the sensor system(s)810may include a heat sensor, a position sensor, a light or optical sensor, a self-mixing interferometry (SMI) sensor, an image sensor (e.g., one or more of the image sensors or cameras described herein), an accelerometer, a pressure transducer, a gyroscope, a magnetometer, a health monitoring sensor, an air quality sensor, and so on. Additionally, the one or more sensor systems810may utilize any suitable sensing technology, including, but not limited to, interferometric, magnetic, capacitive, ultrasonic, resistive, optical, acoustic, piezoelectric, or thermal technologies.

In particular, the sensor system(s)810of the electronic device800may include one or more cameras or other types of image sensors that include pixel arrays as described herein, and which may be operated or controlled, such as by the processor804, by the methods described herein in relationFIGS.6and7.

The I/O mechanism812may transmit or receive data from a user or another electronic device. The I/O mechanism812may include the electronic display802, a touch sensing input surface, a crown, one or more buttons (e.g., a graphical user interface “home” button), one or more microphones or speakers, one or more ports such as a microphone port, and/or a keyboard. Additionally or alternatively, the I/O mechanism812may transmit electronic signals via a communications interface, such as a wireless, wired, and/or optical communications interface. Examples of wireless and wired communications interfaces include, but are not limited to, cellular and Wi-Fi communications interfaces.

The illumination projector814may be configured as described with reference toFIGS.1A and1Band elsewhere herein, and in some cases may be integrated or used in conjunction with one or more of the sensor system(s)810. For example, the illumination projector814may illuminate an object or scene, and light that reflects or scatters from the object or scene may be sensed by a light or optical sensor, an SMI sensor, or an image sensor (e.g., one or more of the image sensors or cameras described herein). In some embodiments, an illumination projector814may be part of a sensor system810.