Nonvolatile semiconductor memory with virtual ground array

A nonvolatile semiconductor memory of virtual ground array in which a common connection of the sources and a common connection of the drains of nonvolatile memory cells arranged in rows and columns in a memory cell array are used as bit lines, the nonvolatile memory cells including: a reference cell from which a characteristic used as a reference in a differential readout determination operation is obtained; and a neighbor cell at one side of the reference cell, the neighbor cell sharing one of the source and the drain of the reference cell and being connected to a word line which is connected to the reference cell, wherein the nonvolatile semiconductor memory includes a neighbor cell programming circuit to set the neighbor cell to a programmed state when the word line is activated to set the reference cell to a conduction state, the neighbor cell being kept in a non-conduction state during the programmed state.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory with virtual ground array (VGA) system developed for the aim of reducing chip area in which, for example, a common connection of the sources and a common connection of the drains of memory cells are used as bit lines, and the source or the drain is shared by adjacent memory cells to reduce the number of drain contacts or source contacts and to greatly reduce the chip area. Specifically, the present invention relates to a semiconductor memory or the like in which stabilized reading is realized in such a manner that when a characteristic used as a reference in a differential readout determination operation is obtained from a memory cell (reference cell) of a memory cell array, variation in the characteristic is suppressed.

2. Description of the Prior Art

Since the VGA structure can adopt a memory array structure having extremely good area efficiency, the VGA structure is used as a way to realize a large capacity memory (for example, seeFIG. 1of the specification of United States Laid-Open Patent Publication No. 2005/0088878). Here, in order to reduce leakage of cell current into a neighbor cell (hereinafter referred to as neighbor effect) in sense operation caused by a common connection of the drains and a common connection of the sources, a technique is adopted which involves applying a voltage to the source of the neighbor cell in a source side sense operation (FIG. 5Bin the specification of United States Laid-Open Patent Publication No. 2005/0088878). Also in a drain side sense operation, a technique is also adopted in which a voltage being the same as the drain voltage of the relevant cell is applied to the drain of the neighbor cell (seeFIG. 2of Japanese Laid-Open Patent Publication No. 2003-22684).

The above-mentioned VGA structure can be adopted not only to a main area which stores data, but also to a memory cell (reference cell) from which the characteristic used as a reference in the differential readout determination operation is obtained.

However, it is found that when the conventional VGA structure is used to form such a reference cell as mentioned above, a leakage current via a cell neighboring the reference cell varies in processes, which makes it difficult to realize stable reading.

FIG. 24shows an algorism for reprogramming and readout operations of a conventional nonvolatile semiconductor memory. When a characteristic used as a reference is obtained from a memory cell (reference cell), programming of the reference cell is first performed in Step1such that the reference cell conducts a predetermined reference current. Then, in the reprogramming operation in actual use of the nonvolatile semiconductor memory, an erase operation in Step2, a programming operation in Step3, and a readout operation in Step4are performed on a main area.

FIG. 23is a block diagram illustrating the conventional nonvolatile semiconductor memory.

With reference toFIG. 23, the programming of the reference cell in Step1will be first explained. A row decoder3selects a word line RWL1to select a reference cell RC12in a memory cell region1in which memories are arranged in an array. In this state, a column decoder4drives column selection lines CSp1and CSp0to have a logical value of 1, which allows application of voltages V1=Vd and V2=VSS generated in a programming bias circuit9respectively to main bit liens RMBL3and RMBL2via column selection transistors Cp1and Cp0. At the same time, selection line driving circuits2-2and2-1drive block selection lines SEL6and SEL2to have a logical value of 1, which allows application of the Vd and the VSS respectively to subbit lines DBL3and DBL2via block selection transistors SL12and SL02. Then, the Vd and the VSS are respectively applied to the source and the drain of the reference cell RC12, and electrons are injected in a charge accumulation region at a subbit line DBL3side by a hot electron injection method, so that the reference cell is programmed.

Next, the readout operation performed in Step2, Step3, and Step4using the reference cell will be explained. Likewise, the row decoder3selects the word line RWL1to select the reference cell RC12. In this state, the column decoder4drives column selection lines CSr1and CSr0to have a logical value of 1, which allows application of a voltage V3=Vb generated in a read bias circuit7to the main bit line RMBL2via a column selection transistor Cr1, and connection of the main bit line RMBL3to a reference side input of a sense amplifier6via a column selection transistor Cr0. At the same time, a column selection line CSn is driven to have a logical value of 1, which allows injection of a current Iadd from a neighbor effect suppression circuit8into a bit line RMBL0via a column selection transistor Cn. At the same time, the selection line driving circuits2-1and2-2drive the block selection lines SEL2, SEL6, and SEL1to have a logical value of 1, which allows application of the Vb to the subbit line DBL2via the block selection transistor SL02, connection of the subbit line DBL3to the sense amplifier6via the block selection transistor SL12, and injection of the current Iadd from the neighbor effect suppression circuit8into a subbit line DBL4via a block selection transistor SL01. In this case, the current Iadd is set to have the same value as that of a leakage current Ines via a neighbor cell RC13connected to the word line RWL1which is connected to the reference cell RC12, so that the leakage current via the neighbor cell RC13does not occur, and thus a cell current Iref of the reference cell RC12is faithfully input into the sense amplifier6. That is, the above-mentioned function of the neighbor effect suppression circuit8reduces the neighbor effect, which is particular to the VGA structure. Then, as shown inFIG. 25, based on a result from an integration of currents input from a main side and from a reference side, a difference potential between both nodes is differentially determined and the readout operation is performed.

Since in the conventional structure, characteristics of cells, including the neighbor cell RC13but excepting the reference cell RC12, vary in processes, it is not in all cases possible to completely counterbalance variation in leakage current Ines by the current Iadd. Therefore, reference side input current input to the sense amplifier6varies, and a reference side input voltage SA_IN_Ref of the sense amplifier6varies in the range of SA_IN_Ref− to SA_IN_Ref+ as shown in the graph inFIG. 25, which disables a stable readout operation.

Explanations have been given with reference to a system in which a cell current is taken at a source side (source sense system). However, in a system in which a cell current is taken at a drain side (drain sense system), a neighbor cell RC11has similar influence.

SUMMARY OF THE INVENTION

The present invention relates to a semiconductor memory with VGA structure, and an object of the present invention is to realize stabilized reading in such a manner that especially when a characteristic used as a reference in a differential readout determination operation is obtained from a memory cell (reference cell) arranged in part of a memory cell array, variation in the characteristic is suppressed.

To achieve the object, the present invention includes a mechanism for programming a memory cell which neighbors a reference cell. Overviews of representative examples of the invention disclosed in this specification are briefly explained as follows.

A first example includes a selection means for applying a programming potential to the source of a neighbor cell provided at a common source side and a selection means for applying a ground potential to the drain of the neighbor cell. According to the first example, it is possible to reduce variation in neighbor effect in a source side sense system.

A second example includes a selection means for applying a ground potential to the drain of a neighbor cell provided at a common drain side and a selection means for applying a programming potential to the source of the neighbor cell. According to the second example, it is possible to reduce variation in neighbor effect in a drain side sense system.

A third example includes a selection means for applying a programming potential to the source of neighbor cells provided at a common source side and at a common drain side and a selection means for applying a ground potential to the drain of the neighbor cells provided at the common source side and at the common drain side. According to the third example, the circuit scale increases, but it is possible to reduce variation in neighbor effect in a source side sense system, and to improve access time by increasing the drain side charge up speed in a readout operation.

A fourth example includes a selection means for applying a programming potential to the drain of a neighbor cell provided at a common source side and a selection means for applying a ground potential to the source of the neighbor cell. According to the fourth example, it is possible to realize more reduction in variation in neighbor current in a source side sense system.

A fifth example includes a selection means for coupling a sense amplifier to the source of a neighbor cell provided at a common source side and a selection means for applying a readout potential to the drain of the neighbor cell, and involves the operation of verifying the programming threshold value of the neighbor cell. According to the fifth example, the circuit scale increases and the algorism is complex, but it is possible to improve degradation in threshold value (reliability) of the neighbor cell in a source sense system.

A sixth example includes a selection means for coupling a sense amplifier to the drain of a neighbor cell provided at a common drain side and a selection means for applying a ground potential to the source of the neighbor cell, and involves the operation of verifying the programming threshold value of the neighbor cell. According to the sixth example, the circuit scale increases and the algorism is complex, but it is possible to improve degradation in threshold value (reliability) of the neighbor cell in a drain sense system.

A seventh example includes in addition to the means of the fifth example, a mode detection circuit and a gate voltage selection circuit, wherein the programming threshold value of a neighbor cell is set higher only to a neighbor cell which neighbors a reference cell used to verify the programming of a main cell. According to the seventh example, it is possible to optimally improve neighbor effect in verifying the programming.

A eighth example includes in addition to the means of fifth example, a power supply activation detection circuit and a sequencer circuit, wherein a neighbor cell whose threshold value degrades is automatically reprogrammed at the time of power supply activation. According to the eighth example, it is possible to reprogram the neighbor cell after the nonvolatile semiconductor device is put on the market and to facilitate reliability design.

A ninth example includes in addition to the means of the fifth example, an external terminal and a sequencer circuit, wherein a neighbor cell whose threshold value degrades is reprogrammed under external control. According to the ninth example, it is possible to realize the function of the eighth example with a simpler circuit structure although the function is required to be controlled.

A tenth example includes in addition to the means of the fifth example, a decoding means for individually selecting every word line in a memory cell array and for applying a gate voltage in programming to program all neighbor cells connected to a bit line at a common source side. According to the tenth example, it is possible to reduce neighbor effect caused by over erase currents of all the neighbor cells connected to the subbit line at the common source side in the source sense system.

An eleventh example includes in addition to the means of the sixth example, a decoding means for individually selecting every word line in a memory cell array and applying a gate voltage in programming thereto to program all neighbor cells connected to a bit line at a common drain side. According to the eleventh example, it is possible to reduce neighbor effect caused by over erase currents of all the neighbor cells connected to the subbit line at the common drain side in the drain sense system.

A twelfth example includes in addition to the means of the fifth example, a selection means for outputting a current flowing through a common source to the outside. According to the twelfth example, it is possible to facilitate the characteristic evaluation of a neighbor effect current in a source sense system.

A thirteenth example includes in addition to the means of the sixth example, a selection means for outputting a current flowing into a common drain to the outside. According to the thirteenth example, it is possible to facilitate the characteristic evaluation of a neighbor effect current in a drain sense system.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First, the outline of a nonvolatile semiconductor memory of the present invention will be described. A well-known structure of a memory cell provided in the nonvolatile semiconductor memory is such that the memory cell includes a floating gate between a substrate and a control gate. The memory cell holds binary information depending on whether or not electrons are accumulated in the floating gate. If electrons are accumulated in the floating gate, the threshold value of a gate voltage applied to the control gate increases. Therefore, even with the application of a predetermined gate voltage, a current does not practically flow through the memory cell. This state is defined as such that “0” is stored. Contrary to this, if electrons are not accumulated in the floating gate, the threshold value of the gate voltage decreases. Therefore, if a predetermined gate voltage is applied to the control gate, a current flows through the memory cell. This state is defined as such that “1” is stored. In this case, a state where electrons are not accumulated is referred to as an erased state “1”, and a state where electrons are accumulated is referred to as a written state “0”. Moreover, the present invention is applicable not only to a memory cell including a floating gate, but also to a memory cell including a MONOS structure in which electrons are accumulated in a trap in a nitride film to hold memories, the nitride film being an insulation film provided between oxide films.

The overview of a nonvolatile semiconductor memory of Embodiment 1 of the present invention will be described below with reference to the drawings. According to the nonvolatile semiconductor memory of Embodiment 1, it is possible to reduce variation in neighbor effect in a source side sense system.

FIG. 2shows an exemplary algorism for reprogramming and readout operations of Embodiment 1 of the present invention. Programming of a reference cell is first performed in Step1such that the reference cell conducts a predetermined reference current. Subsequently, programming of a neighbor cell of the reference cell is performed in Step5. Then, in a reprogramming operation in actual use of the nonvolatile semiconductor memory, an erase operation in Step2, a programming operation in Step3, and a readout operation in Step4are performed on a main area.

Note that, Step1, Step2, and Step3may involve a verify action for level adjustment.

It is shown a case where Step5is performed immediately after Step1. However, Step5may be performed whenever before Step2.

FIG. 1is a block diagram illustrating the nonvolatile semiconductor memory of Embodiment 1 of the present invention.

Since the programming of the reference cell in Step1and the readout operation in Step2, Step3, and Step4using the reference cell are the same as those described in the conventional example, descriptions thereof with reference toFIG. 1are omitted, but the programming of the neighbor reference cell performed in Step5will be described with reference toFIG. 1. A row decoder3selects a word line RWL1to select a neighbor reference cell RC13arranged in an array in a memory cell region1. In this state, a column decoder4drives column selection lines CSp1and CSp2to have a logical value of 1, which allows application of voltages V1=Vd and V2=VSS generated in a programming bias circuit9respectively to main bit lines RMBL3and RMBL0via column selection transistors Cp1and Cp2. At the same time, selection line drive circuits2-2and2-1drive block selection lines SEL6and SEL1to have a logical value of 1, which allows application of the Vd and the VSS respectively to subbit lines DBL3and DBL4via block selection transistors SL12and SL01. Then, the Vd and the VSS are respectively applied to the source and the drain of the neighbor reference cell RC13, and electrons are injected in a charge accumulation region at a subbit line DBL3side by a hot electron injection method, so that the neighbor reference cell is programmed.

As described above, in the structure of Embodiment 1 of the present invention, the neighbor cell RC13is programmed, which makes it possible to reduce a leakage current Ines in the readout operation performed in Step2, Step3, and Step4using the reference cell. Therefore, after the leakage current Ines is counterblanaced by a current Iadd from a neighbor effect suppression circuit8, variation in reference side input current to a sense amplifier6is reduced, and variation in reference side input voltage SA_IN_Ref to the sense amplifier6is also reduced as shown in the graph inFIG. 3. In this way, it is possible to realize a stable readout operation.

Note that, since programming of the neighbor reference cell RC13can reduce the leakage current as explained above, it is not necessary to provide the neighbor effect suppression circuit8. If the neighbor effect suppression circuit8is not provided, it is possible to reduce power consumption.

The overview of a nonvolatile semiconductor memory of Embodiment 2 of the present invention will be described below with reference to the drawings. According to the nonvolatile semiconductor memory of Embodiment 2, it is possible to reduce variation in neighbor effect in a drain side sense system.

FIG. 2shows an exemplary algorism for reprogramming and readout operations of Embodiment 2 of the present invention. Programming of a reference cell is first performed in Step1such that the reference cell conducts a predetermined reference current. Subsequently, programming of a neighbor cell of the reference cell is performed in Step5. Then, in a reprogramming operation in actual use of the nonvolatile semiconductor memory, an erase operation in Step2, a programming operation in Step3, and a readout operation in Step4are performed on a main area.

Note that, Step1, Step2, and Step3may involve a verify action for level adjustment.

It is shown a case where Step5is performed immediately after Step1. However, Step5may be performed whenever before Step2.

FIG. 4is a block diagram illustrating the nonvolatile semiconductor memory of Embodiment 2 of the present invention.

Since the programming of the reference cell in Step1is the same as that in the conventional example, a description thereof with reference toFIG. 4is omitted.

First, the programming of the neighbor reference cell performed in Step5will be described. A row decoder3selects a word line RWL1to select a neighbor reference cell RC11arranged in an array in a memory cell region1. In this state, a column, decoder4drives column selection lines CSp3and CSp0to have a logical value of 1, which allows application of voltages V1=Vd and V2=VSS generated in a programming bias circuit9respectively to main bit lines RMBL1and RMBL2via column selection transistors Cp3and Cp0. At the same time, selection line drive circuits2-2and2-1drive block selection lines SEL4and SEL2to have a logical value of 1, which allows application of the Vd and the VSS respectively to subbit lines DBL1and DBL2via block selection transistors SL10and SL02. Then, the Vd and the VSS are respectively applied to the source and the drain of the neighbor reference cell RC11, and electrons are injected in a charge accumulation region at a subbit line DBL1side by a hot electron injection method, so that the neighbor reference cell is programmed.

Next, the readout operation in Step2, Step3, and Step4using the reference cell will be explained. Likewise, the row decoder3selects the word line RWL1to select a reference cell RC12. In this state, the column decoder4drives column selection lines CSr1and CSr0to have a logical value of 1, which allows connection of the main bit line RMBL2to a sense amplifier6at a reference side via a column selection transistor Cr1, and application of a voltage V4=VSS generated in a readout bias circuit7to a main bit line RMBL3via a column selection transistor Cr0. At the same time, the selection line drive circuits2-1and2-2drive the block selection lines SEL2and SEL6to have a logical value of 1, which allows application of the VSS to a subbit line DBL3via a block selection transistor SL12, and connection of the subbit line DBL2to the sense amplifier6via the block selection transistor SL02. In this case, since the neighbor cell RC11has been programmed in Step5, a leakage current Ined via the neighbor cell RC11is reduced, the neighbor cell RC11being connected to the word line RWL1which is connected to the reference cell RC12. Therefore, process variation in neighbor current is suppressed as shown in the graph inFIG. 5, and a cell current Iref of the reference cell RC12is faithfully detected by the sense amplifier6.

As described above, in the structure of Embodiment 2 of the present invention, a neighbor cell in the drain side sense system is programmed, which reduces variation in reference side input current I_SA_Ref to the sense amplifier6. Therefore, it possible to realize a stable readout operation.

The overview of a nonvolatile semiconductor memory of Embodiment 3 of the present invention will be described below with reference to the drawings. According to the nonvolatile semiconductor memory of Embodiment 3, it is possible to reduce variation in neighbor effect in a source side sense system and to improve access time by increasing the drain side charge-up speed.

FIG. 2shows an exemplary algorism for reprogramming and readout operations of Embodiment 3 of the present invention. Programming of a reference cell is first performed in Step1such that the reference cell conducts a predetermined reference current. Subsequently, programming of a neighbor cell of the reference cell is performed in Step5. Then, in a reprogramming operation in actual use of the nonvolatile semiconductor memory, an erase operation in Step2, a programming operation in Step3, and a readout operation in Step4are performed on a main area.

Note that, Step1, Step2, and Step3may involve a verify action for level adjustment.

It is shown a case where Step5is performed immediately after Step1. However, Step5may be performed whenever before Step2.

FIG. 6is a block diagram illustrating the nonvolatile semiconductor memory of Embodiment 3 of the present invention.

Since the programming of the reference cell in Step1and the readout operation in Step2, Step3, and Step4using the reference cell are the same as those described in the conventional example, descriptions thereof with reference toFIG. 6are omitted.

Since in Embodiment 3, both a neighbor cell RC11and a neighbor cell RC13are programmed, a circuit structure of Embodiment 3 includes column selection transistors Cp2and Cp3for which selection signals CSp2and CSp3are output from a column decoder4-2. Programming the neighbor cells RC11and RC13using these circuits in neighbor reference cell programming operation in Step5reduces a drain side leakage current Ined and a source side leakage current Ines of a reference cell RC12. Reducing the drain side leakage current Ined makes it possible to shorten set-up time of a drain voltage Vd applied from a readout bias circuit7. Moreover, reducing the source side leakage current Ines makes it possible to reduce variation in reference side input current to a sense amplifier6.

As described above, the structure of Embodiment 3 of the present invention includes an additional column selection mechanism for programming both of the neighbor cells. In this structure, it is possible to improve access time by increasing the drain side charge-up speed as well as to reduce variation in neighbor effect in the source side sense system.

Note that, such a structure as mentioned above may be applied to the drain side sense system as shown inFIG. 4.

The overview of a nonvolatile semiconductor memory of Embodiment 4 of the present invention will be described below with reference to the drawings. According to the nonvolatile semiconductor memory of Embodiment 4, it is possible to reduce variation in neighbor effect in a source side sense system especially in a memory cell employing MONOS structure in which electrons are accumulated in a trap in a nitride film to hold memories, a nitride film being an insulation film provided between oxide films.

FIG. 2shows an exemplary algorism for reprogramming and readout operations of Embodiment 4 of the present invention. Programming of a reference cell is first performed in Step1such that the reference cell conducts a predetermined reference current. Subsequently, programming of a neighbor cell of the reference cell is performed in Step5. Then, in a reprogramming operation in actual use of the nonvolatile semiconductor memory, an erase operation in Step2, a programming operation in Step3, and a readout operation in Step4are performed on a main area.

Note that, Step1, Step2, and Step3may involve a verify action for level adjustment.

It is shown a case where Step5is performed immediately after Step1. However, Step5may be performed whenever before Step2.

FIG. 7is a block diagram illustrating the nonvolatile semiconductor memory of Embodiment 4 of the present invention.

Since the programming of the reference cell in Step1and the readout operation in Step2, Step3, and Step4using the reference cell are the same as those described in the conventional example, descriptions thereof with reference toFIG. 7are omitted.

The programming of the neighbor reference cell performed in Step5will be described. A row decoder3selects a word line RWL1to select a neighbor reference cell RC13arranged in an array in a memory cell region1. In this state, a column decoder4drives column selection lines CSp2and CSp3to have a logical value of 1, which allows application of voltages V1=Vd and V2=VSS generated in a programming bias circuit9respectively to main bit lines RMBL0and RMBL3via column selection transistors Cp2and Cp3. At the same time, selection line drive circuits2-2and2-1drive block selection lines SEL1and SEL6to have a logical value of 1, which allows application of the Vd and the VSS respectively to subbit lines DBL4and DBL3via block selection transistors SL01and SL12. Then, the VSS and the Vd are respectively applied to the source and the drain of the neighbor reference cell RC13, and electrons are injected in a charge accumulation region at a subbit line DBL4side by a hot electron injection method, so that the neighbor reference cell is programmed.

A memory cell employing MONOS structure includes two charge accumulation regions at a subbit line DBL3side and a subbit line DBL4side, and in terms of reduction in neighbor effect, it is preferable that charges are accumulated at the subbit line DBL4side. Therefore, as described above, Embodiment 4 of the present invention includes an additional column selection transistor compared to Embodiment 1. However, in Embodiment 4, it is possible to realize more reduction in variation in reference side input voltage SA_IN_Ref to a sense amplifier6as shown in the graph inFIG. 3and to realize a more stable readout operation.

The overview of a nonvolatile semiconductor memory of Embodiment 5 of the present invention will be described below with reference to the drawings. The nonvolatile semiconductor memory of Embodiment 5 includes a circuit for verifying the programming threshold value of a neighbor cell and involves a verification action, with which it is possible to improve degradation in threshold value (reliability) of the neighbor cell in a source sense system.

FIG. 9shows an exemplary algorism for reprogramming and readout operations of Embodiment 5 of the present invention. Programming of a reference cell is first performed in Step1such that the reference cell conducts a predetermined reference current. Subsequently, programming of a neighbor cell of the reference cell is performed in Step5, and the programming of Step5is verified in Step6and determined in Step7. Then, in the reprogramming operation in actual use of the nonvolatile semiconductor memory, an erase operation in Step2, a programming operation in Step3, and a readout operation in Step4are performed on a main area.

Note that, Step1, Step2, and Step3may involve a verify action for level adjustment.

It is shown a case where Steps5through7are performed immediately after Step1. However, Steps5through7may be performed whenever before Step2.

FIG. 8is a block diagram illustrating the nonvolatile semiconductor memory of Embodiment 5 of the present invention.

Since the programming of the reference cell in Step1, the readout operation in Step2, Step3, and Step4using the reference cell, and the programming of the neighbor cell in Step5are the same as those described in Embodiment 1, descriptions thereof with reference toFIG. 8are omitted.

First, verification of the programming of the neighbor reference cell in Step6will be explained. A row decoder3selects a word line RWL1to select a neighbor cell RC13. In this state, a column decoder4drives column selection lines CSr2and CSr0to have a logical value of 1, which allows application of a voltage V3=Vb generated in a readout bias circuit7to a main bit line RMBL0via a column selection transistor Cr2and connection of a main bit line RMBL3to a reference side input of a sense amplifier6via a column selection transistor Cr0. At the same time, a column selection line CSn1is driven to have a logical value of 1, which allows injection of a current from a neighbor effect suppression circuit8to a main bit line RMBL2via a column selection transistor Cn1. At the same time, selection line drive circuits2-1and2-2drive block selection lines SEL2, SEL6, and SEL1to have a logical value of 1, which allows application of the Vb to a subbit line DBL4via a block selection transistor SL01, connection of a subbit line DBL3to the sense amplifier6via a block selection transistor SL12, and injection of the current from the neighbor effect suppression circuit8to a subbit line DBL2via a block selection transistor SL02. In this way, the sense amplifier6differentially determines a difference potential between both nodes according to current input values at a main side and a reference side to determine the programming threshold value of the neighbor cell.

Next, if it is determined in Step7that the verification of Step6shows a success of the programming, the process proceeds to Step2, but if it is determined in Step,7that the verification of Step6shows a failure of the programming, Step5is performed again.

As described above, in Embodiment 5 of the present invention, the programming of the neighbor cell in the source sense system is verified and determined to prevent overprogramming of the neighbor cell, which makes it possible to improve the degradation in threshold value (reliability) of the neighbor cell in the source sense system.

The overview of a nonvolatile semiconductor memory of Embodiment 6 of the present invention will be described below with reference to the drawings. The nonvolatile semiconductor memory of Embodiment 6 includes a circuit for verifying the programming threshold value of a neighbor cell and involves a verification action, with which it is possible to improve degradation in threshold value (reliability) of the neighbor cell in a drain sense system.

FIG. 9shows an exemplary algorism for reprogramming and readout operations of Embodiment 6 of the present invention. Programming of a reference cell is first performed in Step1such that the reference cell conducts a predetermined reference current. Subsequently, programming of a neighbor cell of the reference cell is performed in Step5, and the programming of Step5is verified in Step6and determined in Step7. Then, in the reprogramming operation in actual use of the nonvolatile semiconductor memory, an erase operation in Step2, a programming operation in Step3, and a readout operation in Step4are performed on a main area.

Note that, Step1, Step2, and Step3may involve a verify action for level adjustment.

It is shown a case where Steps5through7are performed immediately after Step1. However, Steps5through7may be performed whenever before Step2.

FIG. 10is a block diagram illustrating the nonvolatile semiconductor memory of Embodiment 6 of the present invention.

Since the programming of the reference cell in Step1, the readout operation in Step2, Step3, and Step4using the reference cell, and the programming of the neighbor cell in Step5are the same as those described in Embodiment 2, descriptions thereof with reference toFIG. 10are omitted.

First, verification of the programming of the neighbor reference cell in Step6will be explained. A row decoder3selects a word line RWL1to select a neighbor cell RC11. In this state, a column decoder4drives column selection lines CSr1and CSr4to have a logical value of 1, which allows connection of a main bit line RMBL2to a reference side input of a sense amplifier6via a column selection transistor Cr1and application of a voltage V4=VSS generated in a readout bias circuit7to a main bit line RMBL1via a column selection transistor Cr4. At the same time, a column selection line CSn1is driven to have a logical value of 1, which allows injection of a current from a neighbor effect suppression circuit8to a main bit line RMBL3via a column selection transistor Cn1. At the same time, selection line drive circuits2-1and2-2drive block selection lines SEL2, SEL4, and SEL6to have a logical value of 1, which allows connection of a subbit line DBL2to the sense amplifier6via a block selection transistor SL02, application of the VSS to a subbit line DBL1via a block selection transistor SL10, and injection of the current from the neighbor effect suppression circuit8to a subbit line DBL3via a block selection transistor SL12. In this way, the sense amplifier6differentially determines a difference potential between both nodes according to current values at the main side and at the reference side to determine the programming threshold value of the neighbor cell.

Next, if it is determined in Step7that the verification in Step6shows a success of the programming, the process proceeds to Step2, but if it is determined in Step7that the verification in Step6shows a failure of the programming, Step5is performed again.

As described above, in Embodiment 6 of the present invention, the programming of the neighbor cell in the drain sense system is verified and determined to prevent overprogramming of the neighbor cell, which makes it possible to improve the degradation in threshold value (reliability) of the neighbor cell in the drain sense system.

The overview of nonvolatile semiconductor memory of Embodiment 7 of the present invention will be described below with reference to the drawings. The nonvolatile semiconductor memory of Embodiment 7 includes a mode detection circuit and a gate voltage selection circuit, which enables setting of the programming threshold values of neighbor cells to different values according to types of reference cells which the neighbor cells neighbor, and thus optimization of reliability and neighbor effect is possible.

Here, setting methods of a readout-operation use reference cell and a programming-verification use reference cell will be explained.

FIG. 12shows an exemplary algorism for reprogramming and readout operations of Embodiment 7 of the present invention. The readout-operation use reference cell RC12and the programming-verification use reference cell RC22are first programmed in Step1such that these reference cells conduct a predetermined reference current. Subsequently, programming of a neighbor cell of the readout-operation use reference cell is performed in Step5-1, and the programming of Step5-1is verified in Step6-1and determined in Step7-1. Subsequently, programming of a neighbor cell of the programming-verification use reference cell is performed in Step5-2, and the programming of Step5-2is verified in Step6-2and determined in Step7-2. Then, in the reprogramming operation in actual use of the nonvolatile semiconductor memory, an erase operation in Step2, a programming operation in Step3, and a readout operation in Step4are performed on a main area.

Note that, Step1, Step2, and Step3may involve a verify action for level adjustment.

It is shown a case where Steps5-1through7-2are performed immediately after Step1. However, Steps5-1through7-2may be performed whenever before Step2, and Steps5-1through7-1and Steps5-2through7-2are interchangeable.

FIG. 11is a block diagram illustrating the nonvolatile semiconductor memory of Embodiment 7 of the present invention.

Since the programming of the reference cell in Step1, and the readout operation in Step2, Step3, and Step4using the reference cell are the same as those described in Embodiment 1, descriptions thereof with reference toFIG. 11are omitted.

Moreover, Steps5-1through7-1and Steps5-2through7-2are respectively the same as those described in Embodiment 5. However, in a circuit structure of Embodiment 7, a control signal CONT input to a predecoder11differs depending on whether a neighbor cell of the readout-operation use reference cell is to be accessed, or a neighbor cell of the programming-verification use reference cell is to be accessed. The predecoder sets an output signal MOD to a logical value of 0 in the former case and to a logical value of 1 in the latter case. Receiving such signal, a power supply circuit10and a row decoder3respond as shown in Table 1 below, where a power supply of the row decoder is indicated by VWL which corresponds to a potential of the word line RWL having a logical value of 1.

As to a word line voltage in verifying the programming, in order to determine (identify) a post-programming threshold value, the word line voltage in verifying the programming in Step6-2is set to a higher value than that in Step6-1so as to set a lower threshold value for a readout use neighbor reference cell RC13which requires longer operating time and to set a higher threshold value for a programming-verification use neighbor reference cell RC23. As a result, neighbor effect is suppressed, which makes it possible to improve accuracy of the post-programming threshold value of a main cell in Step3.

As described above, in Embodiment 7 of the present invention, it is possible to set the programming threshold values of neighbor cells to different values according to types of reference cells which the neighbor cells neighbor, and thus optimization of reliability and neighbor effect is possible.

The overview of a nonvolatile semiconductor memory of Embodiment 8 of the present invention will be described below with reference to the drawings. According to the nonvolatile semiconductor memory of Embodiment 8, after the nonvolatile semiconductor memory is put on the market, if the threshold value of a neighbor cell degrades, it is possible to automatically reprogram the neighbor cell.

FIG. 14shows an exemplary algorism for a reprogramming operation of Embodiment 8 of the present invention, andFIG. 13is a block diagram illustrating the nonvolatile semiconductor memory of Embodiment 8.

First, a power supply VDD is activated in Step8to output a voltage detection signal STRWBAK. Next, in Step9, through monitoring whether or not the voltage detection signal STRWBAK is switched to have a logical value of 1, the completion of activation of the power supply is detected. The voltage detection signal STRWBAK is input to a state machine13to generate signals for controlling each block at an appropriate timing.

Next, programming of a cell neighboring a reference cell is performed in Step5, and the programming of Step5is verified in Step6and determined in Step7. Then, the reprogramming operation is performed in actual use of the nonvolatile semiconductor memory.

Since Step5, Step6, and Step7are the same as those described in Embodiment 5, the detailed descriptions thereof are omitted.

In order to verify the programming of the neighbor cell of the reference cell in Step6after the nonvolatile semiconductor memory is put on the market, a circuit structure of Embodiment 8 includes a reprogramming use reference current generation circuit. In the reprogramming use reference current generation circuit, an initial state memory cell (which is constant in a neutral state) is used as a constant current source. In verification of the programming of the neighbor cell in Step6, a reprogramming use reference cell control circuit14outputs a word line BWL to activate a memory cell BC0. Next, selection signals SELB1, SELB2, CSB1, and CSB2are switched to have a logical value of 1, which allows input of a cell current output via the memory cell BC0from a readout bias circuit7to a main side input of a sense amplifier6, the cell current input to the sense amplifier6being used as a reference current in Step6.

As described above, Embodiment 8 of the present invention includes the power source activation detection circuit12and the sequencer circuit to automatically reprogram a neighbor cell having a decreased threshold value at the time of power supply activation. Therefore, it possible to automatically reprogram the neighbor cell after the nonvolatile semiconductor memory is put on the market and to facilitate reliability design.

Note that, descriptions of the reprogramming use reference current generation circuit have been given with reference to a case where a memory cell is used therein. However, it is possible to generate a reference current using a general transistor or passive component (for example, resistor or capacitor).

The overview of a nonvolatile semiconductor memory of Embodiment 9 of the present invention will be described below with reference to the drawings. According to the nonvolatile semiconductor memory of Embodiment 9, it is possible to facilitate a mechanism for reprogramming a neighbor cell when the threshold value thereof degrades.

FIG. 16shows an exemplary algorism for a reprogramming operation of Embodiment 9 of the present invention, andFIG. 15is a block diagram of the nonvolatile semiconductor memory of Embodiment 9.

First, in Step10, a reprogramming signal STRWBAK is set from the outside to have a logical value of 1. Next, the reprogramming signal STRWBAK is input to a state machine13which generates signals for controlling each block at an appropriate timing.

Next, programming of a neighbor cell of a reference cell is performed in Step5, and the programming of Step5is verified in Step6and determined in Step7. Then, the reprogramming operation is performed in actual use of the nonvolatile semiconductor memory.

Since Step5, Step6, and Step7are the same as those described in Embodiment 8, the detailed descriptions thereof are omitted.

As described above, in Embodiment 9 of the present invention, a neighbor cell having a decreased threshold value is reprogrammed under external control. Although this structure requires the external control compared to that of Embodiment 8, this structure can be realized more simply without the power source activation detection circuit.

The overview of a nonvolatile semiconductor memory of Embodiment 10 of the present invention will be described below with reference to the drawings. According to the nonvolatile semiconductor memory of Embodiment 10, in a source sense system, all neighbor cells connected to a bit line at a common source side are programmed to reduce the neighbor effect caused by over erase currents of all the neighbor cells connected to a subbit line at the common source side.

FIG. 18shows an exemplary algorism for reprogramming and readout operations of Embodiment 10 of the present invention. A readout-operation use reference cell RC12is first programmed in Step1such that the readout-operation use reference cell RC12conducts a predetermined reference current. Subsequently, programming of a neighbor cell is performed in Step5-1, and the programming of Step5-1is verified in Step6-1and determined in Step7-1. Then, as shown in the block diagram ofFIG. 17illustrating the nonvolatile semiconductor memory of Embodiment 10, row decoders3-2and3-3sequentially activate word lines RWL0, RWL2, and RWL3such that programming of all neighbor cells connected to a bit line at a common source side is performed in Step5-2, and the programming of Step5-2is verified in Step6-2and determined in Step7-2subsequently. Then, in the reprogramming operation in actual use of the nonvolatile semiconductor memory, an erase operation in Step2, a programming operation in Step3, and a readout operation in Step4are performed on a main area.

Note that, Step1, Step2, and Step3may involve a verify action for level adjustment.

It is shown a case where Steps5-1through7-2are performed immediately after Step1. However, Steps5-1through7-2may be performed whenever before Step2, and Steps5-1through7-1and Steps5-2through7-2are interchangeable.

InFIG. 17, the programming of the reference cell in Step1, the readout operation in Step2, Step3, and Step4using the reference cell, and the Steps5-1thorough7-1and the Steps5-2through7-2are the same as those described in Embodiment 5. However, in a circuit structure of Embodiment 10, all the neighbor cells connected to the bit line at the common source side are to be accessed and programmed to reduce an over erase leak cell current which flows out via the common source line. Therefore, it is possible to reduce variation in reference side input current to a sense amplifier6.

According to the above-mentioned structure, in Embodiment 10 of the present invention, it is possible to reduce the neighbor effect caused by the over erase currents of all the neighbor cells connected to the subbit line at the common source side in the source sense system.

The overview of a nonvolatile semiconductor memory of Embodiment 11 of the present invention will be described below with reference to the drawings. According to the nonvolatile semiconductor memory of Embodiment 11, in a drain sense system, all neighbor cells connected to a bit line at a common drain side are programmed to reduce the neighbor effect caused by over erase currents of all the neighbor cells connected to a subbit line at the common drain side.

FIG. 20shows an exemplary algorism for reprogramming and readout operations of Embodiment 11 of the present invention. A readout-operation use reference cell RC12is first programmed in Step1such that the readout-operation use reference cell RC12conducts a predetermined reference current. Subsequently, programming of a neighbor cell is. performed in Step5-1, and the programming of Step5-1is verified in Step6-1and determined in Step7-1. Then, as shown in the block diagram ofFIG. 19illustrating the nonvolatile semiconductor memory of Embodiment 11, row decoders3-2and3-3sequentially activate word lines RWL0, RWL2, and RWL3such that programming of all neighbor cells connected to a bit line at a common drain side is performed in Step5-2, and the programming of Step5-2is verified in Step6-2and determined in Step7-2subsequently. Then, in the reprogramming operation in actual use of the nonvolatile semiconductor memory, an erase operation in Step2, a programming operation in Step3, and a readout operation in Step4are performed on a main area.

Note that, Step1, Step2, and Step3may involve a verify action for level adjustment.

It is shown a case where Steps5-1through7-2are performed immediately after Step1. However, Steps5-1through7-2may be performed whenever before Step2, and Steps5-1through7-1and Steps5-2through7-2are interchangeable.

InFIG. 20, the programming of the reference cell in Step1, the readout operation in Step2, Step3, and Step4using the reference cell, and the Steps5-1thorough7-1and the Steps5-2through7-2are the same as those described in Embodiment 6. However, in a circuit structure of Embodiment 11, all the neighbor cells connected to the bit line at the common drain side are to be accessed and programmed to reduce an over erase leak cell current which flows out via a common drain line. Therefore, it is possible to reduce variation in reference side current of a sense amplifier6.

According to the above-mentioned structure, in Embodiment 11 of the present invention, it is possible to reduce the neighbor effect caused by the over erase currents of all the neighbor cells connected to the subbit line at the common drain side in the drain sense system.

The overview of a nonvolatile semiconductor memory of Embodiment 12 of the present invention will be described below with reference to the drawings. The nonvolatile semiconductor memory of Embodiment 12 includes a selection means for outputting a current flowing through a common source to the outside to facilitate characteristic evaluation of the neighbor effect current in a source sense system.

FIG. 21is a block diagram illustrating the nonvolatile semiconductor memory of Embodiment 12 of the present invention, and the operation of measuring a neighbor cell current will be explained.

A row decoder3selects a word line RWL1to select a neighbor cell RC13. In this state, a column decoder4drives column selection lines CSr2and CSr0to have a logical value of 1, which allows application of a voltage V3=Vb generated in a readout bias circuit7to a main bit line RMBL0via a column selection transistor Cr2and connection of a main bit line RMBL3to an input terminal of a transfer gate Ci0via a column selection transistor Cr0. At the same time, selection line drive circuit2-1and2-2drive block selection lines SEL6and SEL1to have a logical value of 1, which allows connection of a subbit line DBL3to the input terminal of the transfer gate Ci0via a block selection transistor SL12and application of the Vb to a subbit line DBL4via a block selection transistor SL01. In this way, a control signal SCi0from a transfer gate control circuit16is set to have a logical value of 1, so that a neighbor current Inref is output to an output terminal17.

According to the above-mentioned structure, in Embodiment 12 of the present invention, external measurement of the neighbor current in the source sense, system is possible, which makes it possible to facilitate the characteristic evaluation of the cell.

The overview of a nonvolatile semiconductor memory of Embodiment 13 of the present invention will be described below with reference to the drawings. The nonvolatile semiconductor memory of Embodiment 13 includes a selection means for outputting a current flowing into a common drain to the outside to facilitate characteristic evaluation of the neighbor effect current in a drain sense system.

FIG. 22is a block diagram illustrating the nonvolatile semiconductor memory of Embodiment 13 of the present invention, and the operation of measuring a reference cell current will be explained.

A row decoder3selects a word line RWL1to select a neighbor cell RC11. In this state, a column decoder4drives column selection lines CSr1and CSr4to have a logical value of 1, which allows connection of a main bit line RMBL2to an input terminal of a transfer gate Ci0via a column selection transistor Cr1and application of a voltage V4=VSS generated in a readout bias circuit7to a main bit line RMBL1via a column selection transistor Cr4. At the same time, selection line drive circuit2-1and2-2drive block selection lines SEL2and SEL4to have a logical value of 1, which allows connection of a subbit line DBL2to the input terminal of the transfer gate Ci0via a block selection transistor SL02and application of the VSS to a subbit line DBL1via a block selection transistor SL10. In this way, a control signal SCi0from a transfer gate control circuit16is set to have a logical value of 1, so that a neighbor current Ined is output to an output terminal17.

According to the above-mentioned structure, in Embodiment 13 of the present invention, external measurement of the neighbor current in the drain sense system is possible, which makes it possible to facilitate the characteristic evaluation of the cell.

Effects obtained from the representative examples of the invention disclosed in the present application will be explained as follows.

In a source sense system and in a drain sense system, a mechanism for programming a memory cell neighboring a reference cell is provided, which enables reduction in neighbor current. As a result, it is possible to improve a margin in readout operation and to achieve stabilization.

A means for verifying the threshold value of a neighbor cell is provided, which makes it possible to improve degradation in threshold value (reliability) of the neighbor cell and to achieve optimization according to types of reference cells.

A mechanism for reprogramming the neighbor cell through internal detection or external control and a means for generating a reference current used in the reprogramming are provided to enable the reprogramming after the nonvolatile semiconductor memory is put on the market. Therefore, it possible to ease the specification required for the neighbor cell and to facilitate reliability design.

Further, a word line decoding means for programming all neighbor cells connected to the source or the drain of a reference cell is provided to reduce the neighbor effect caused by over erase currents. Therefore, it is possible to improve a margin in the readout operation and to achieve stabilization.

Furthermore, a circuit mechanism for externally monitoring a cell current of the neighbor cell is provided, which makes it possible to facilitate the characteristic evaluation and analysis of the cell current of the neighbor cell.

A nonvolatile semiconductor memory of the present invention has effects that data can be accurately determined while increase in area of a circuit is suppressed, and is applicable as, for example, a nonvolatile semiconductor memory having a memory cell region in which memory cells and a reference cell are arranged in rows and columns.