Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation

A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.

BACKGROUND OF THE INVENTION

Recent miniaturization of the wirings in ULSIs disadvantageously contributes to a reduction in reliability of the wirings. In particular, due to a development in multilamination of wirings, there is increasingly used a so-called stacked structure in which upper and lower plugs made of a high-melting-point metal such as W (tungsten), TiN or the like and its compound, are respectively disposed, as opposite to each other, on and under a wiring. In such a stacked structure, that portion of the wiring held by and between the plugs is dis-advantageously weak in reliability.

To enhance the wiring reliability, a first method of prior art is for example arranged to prevent the stress migration that stress from a protective layer disconnects wirings. More specifically, a wiring layer large in grain size is formed in a region in which a major portion of the electric current flows, and a wiring layer small in grain size is formed at a position to which stress is relatively readily applied, such as a surrounding of the wiring (in particular, lateral wall or upper end portion) (See Japanese Patent Laid-Open Publication No. 5-275426).

According to a second method of prior art, there is proposed a stacked structure in which the width of each wiring is smaller than the width of the lower-layer-side connection hole and in which the bottom of the upper-layer-side connection hole extends into the lower-layer-side connection hole such that the wiring is reinforced as if entirely surrounded (See Japanese Patent Laid-Open Publication No. 8-167609).

According to the first method of prior art, however, the wiring is formed by forming a wiring layer small in grain size at a lateral wall of a wiring layer large in grain size. This excessively increases the width of the wiring and is therefore not suitable for miniaturization.

According to the second method of prior art, the width of each of the upper- and lower-layer-side connection holes is inevitably larger than the width of the wiring. This is neither suitable for miniaturization. Further, no consideration has been taken for stress from a high-melting point metal or its compound which surrounds the wiring.

SUMMARY OF THE INVENTION

In a multilayer wiring structure of a semiconductor device having a stacked structure, the present invention is proposed with the object of restraining a wiring from being lowered in reliability, particularly, due to stress applied to that portion of the wiring held by and between upper- and lower-layer-side plugs.

Further, the present invention provides a semiconductor device which is to be used for reliability evaluation and which has a test pattern capable of detecting, with high sensitivity, a connection failure in a stacked structure.

More specifically, a multilayer wiring structure of a semiconductor device according to the present invention comprises: a substrate; two or more wiring layers formed on the substrate; an upper plug for electrically connecting a wiring formed at one of the wiring layers to the upper wiring; and a lower plug opposite to the upper plug with the wiring interposed, for electrically connecting the wiring to the lower wiring layer or to the substrate, wherein when viewed in the direction of vertical line of the substrate surface, the distance between center of contact surface between the upper plug and the wiring, and center of contact surface between the lower plug and the wiring is about ⅔ or more of the diameter of each of the upper and lower plugs.

Further, a multilayer wiring structure of a semiconductor device according to the present invention comprises; a substrate; two or more wiring layers formed on the substrate; an upper plug for electrically connecting a wiring formed at one of the wiring layers to the upper wiring layer; and a lower plug opposite to the upper plug with the wiring interposed, for electrically connecting the wiring to the lower wiring layer or to the substrate, wherein the upper plug is inserted from the top surface of the one wiring layer to a depth of about ⅓ or more of the thickness thereof, the one wiring layer has a part projecting into lower side and being in contact with said lower plug, and the height of the projecting part from the undersurface of the one wiring layer is about ⅓ or less of the diameter of each of the lower plugs.

Further, a multilayer wiring structure of a semiconductor device according to the present invention comprises: a substrate; two or more wiring layers formed on the substrate; an upper plug for electrically connecting a wiring formed at one of the wiring layers to the upper wiring layer; and a lower plug opposite to the upper plug with the wiring interposed, for electrically connecting the wiring to the lower wiring layer or to the substrate, wherein the wiring has no grain boundary in the region between the opposite upper and lower plugs.

Further, a multilayer wiring structure of a semiconductor device according to the present invention comprises; a substrate; two or more wiring layers formed on the substrate; an upper plug for electrically connecting a wiring formed at one of the wiring layers to the upper wiring layer; and a lower plug opposite to the upper plug with the wiring interposed, for electrically connecting the wiring to the lower wiring layer or to the substrate, wherein the difference in thermal expansion coefficient between the material of the wiring and the material of at least one of the upper and lower plugs is so small that no void may be generated in the region of the wiring between the opposite upper and lower plugs.

A multilayer wiring structure of a semiconductor device according to the present invention comprises; a substrate; two or more wiring layers formed on the substrate; an upper plug for electrically connecting a wiring formed at one of the wiring layers to the upper wiring layer; and a lower plug opposite to the upper plug with the wiring interposed, for electrically connecting the wiring to the lower wiring layer or to the substrate, wherein the one wiring layer has a layer of a high-melting-point metal or an alloy of high-melting-point metal on the top surface thereof, and the wiring is in contact with the upper plug through the layer of a high-melting-point metal or an alloy of high-melting-point metal.

Further, a multilayer wiring structure of a semiconductor device according to the present invention comprises; a substrate; two or more wiring layers formed on the substrate; an upper plug for electrically connecting a wiring formed at one of the wiring layers to the upper wiring layer; and a lower plug opposite to the upper plug with the wiring interposed, for electrically connecting the wiring to the lower wiring layer or to the substrate, wherein the one wiring layer has a layer of a high-melting-point metal on the undersurface thereof, and said layer of a high-melting-point metal has a thickness of not greater than 10 nm or not less than 80 nm.

Further, a method of producing a multilayer wiring structure of a semiconductor device according to the present invention comprises; a step of forming a first opening in a first insulating layer formed on a substrate and forming a lower plug in the first opening; a step of forming a wiring on the first insulating layer and the lower plug; and a step of forming a second insulating layer on the wiring, and forming, in the second insulating layer and the wiring, a second opening opposite to the first opening and with a depth of about ⅓ or more of the thickness of the wiring, and forming an upper plug in the second opening; at the lower plug forming step, a CMP or etching-back method being used such that the distance between top surface of the lower plug and top surface of the first insulating layer, is about ⅓ or less of the diameter of each of the upper and lower plugs.

Further, a method of producing a multilayer wiring structure of a semiconductor device according to the present invention comprises: a step of forming a first opening in a first insulating layer formed on a substrate and forming a lower plug in the first opening; a step of forming, on the first insulating layer and the lower plug, a wiring having a layer of aluminium or aluminium-alloy; and a step of forming a second insulating layer on the wiring, and forming, in the second insulating layer, a second opening opposite to the first opening, and forming an upper plug in the second opening; at the wiring forming step, the aluminium or aluminium-alloy layer of the wiring being formed, by sputtering, at a substrate temperature of about 200° C. or more such that the region of the wiring between the opposite upper and lower plugs, has no grain boundary.

Further, a method of producing a multilayer wiring structure of a semiconductor device according to the present invention comprises; a step of forming a first opening in a first insulating layer formed on a substrate; a step of forming a lower plug in the first opening and forming a wiring on the first insulating layer; and a step of forming a second insulating layer on the wiring, and forming, in the second insulating layer, a second opening opposite to the first opening, and forming an upper plug in the second opening; at the lower plug and wiring forming step, a CVD method or a CVD and sputtering method being used such that aluminium or an aluminium alloy is deposited in the first opening and on the first insulating layer, thus forming the lower plug and the wiring.

Further, a semiconductor device according to the present invention comprises: a substrate; and three or more wiring layers formed on the substrate; a test pattern for reliability evaluation formed at the wiring layers; the test pattern comprising: an electrically isolated wiring formed at other wiring layer than the highest and lowest layers; an upper plug in contact with top surface of the wiring for electrically connecting the wiring to the upper wiring layer; and a lower plug in contact with the undersurface of the wiring for, electrically connecting the wiring to the lower wiring layer, wherein the upper and lower plugs are opposite to each other with the wiring interposed, and when viewed in the direction of vertical line of the substrate, contact surface between the wiring and the upper plug overlaps with, at least partially, contact surface between the wiring and the lower plug.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1illustrates the structure of a sample to be used for electrically detecting the effect of the stacked structure of a multilayer wiring structure of a semiconductor device.

FIG. 1(a) is a section view of this sample. Shown inFIG. 1(a) are a semiconductor substrate1, a first insulating layer2, contact embedded metals (lower plugs)3made of W (tungsten) formed on a Ti/TiN two-lamination film, a first wiring4formed of a Cu-containing Al alloy formed above a Ti/TiN two-lamination film and above which a TiN film is formed, a second insulating layer5, through-hole embedded metals (upper plugs)6each having a metal composition similar to contact embedded metal3, second wirings7each having a metal composition similar to first wiring4, a silicon nitride layer8serving as a protective layer, and a polyimide layer9as an LSI chip coat.

FIG. 1(b) is a perspective view of first wiring4, and the contact embedded metal3and the through-hole embedded metal6respectively connected to the underside and top of the first wiring4. The first wiring4has a wiring length of 31 mm and has 1,000 contact holes and 1,000 through-holes. Wiring widths of first wiring4are in the range from 0.4 to 1.0 μm and are respectively equal to the diameters of the corresponding contact holes and through-holes.

InFIG. 1(b), the characteristics of voltage and current are measured between pad portions4A,4B disposed at both ends of each first wiring4. The measurement of characteristics of voltage and current refers to the measurement of resistance value of first wiring4provided at the underside and top thereof with contact embedded metal3and through-hole embedded metal6, respectively. For semiconductor substrate1electrically connected to contact embedded metals3is made of Si and is higher in resistance value than first wiring4made of metal. And second wirings7electrically connected to through-hole embedded metal6are electrically independently arranged in its wiring layer.

FIG. 2illustrates the result of measurement on the characteristics of voltage and current between pad portions4A,4B, i.e., the resistance variations of first wirings4, of samples shown inFIG. 1before and after storage at around 250° C.FIG. 2(a) is a graph illustrating the relationship between storage period at about 250° C., and rate of wiring failure. InFIG. 2(a), ordinate axis represents rate of failure (%) while abscissa axis represents storage period (hrs). Here, rate of failure is obtained on the basis that wiring of which resistance variation exceeded 20%, is judged as failure.FIG. 2(b) is a graph illustrating the relationship between wiring width and resistance variation of samples after stored at about 250° C. for 1,000 hours. InFIG. 2(b), ordinate axis represents resistance variation (%) while abscissa axis represents wiring width (μm).

FIG. 3is a graph illustrating the relationship, in the samples shown inFIG. 1, between storing temperature and accumulated failure attainment period during which accumulated failure rate reached 0.1%. Likewise inFIG. 2, wiring of which resistance variation exceeded 20% is judged as failure. InFIG. 3, ordinate axis represents accumulated failure attainment period (hrs) while abscissa axis represents 1000/storing temperature (1/K).FIG. 3shows that the accumulated failure attainment period is minimized in the vicinity of 250° C. It is understood that such a phenomenon occurs from an Al alloy migration failure due to stress, which is a kind of a so-called stress migration failure.

FIG. 4is a view illustrating the relationship between wiring structure and rate of acceptable product.FIG. 4shows the rate of acceptable product for three types of wiring structures, i.e., wiring structure A having an upper plug and a lower plug opposite to each other, wiring structure B having only a lower plug, and wiring structure C having only an upper plug, after storage at 200° C. for 1,000 hours. Here, rate of acceptable product is obtained on the basis that wiring of which resistance variation exceeded 20% is judged as failure. It is understood fromFIG. 4that the problem to be solved by the present invention is characteristic in the wiring structure having an upper plug and a lower plug opposite to each other.

FIG. 5is a section view illustrating the result of observation by transmission electron microscope of a wiring structure having an upper plug and a lower plug opposite to each other, and of which resistance variation exceeded 20% after stored at 200° C. for 1000 hours.FIG. 5also shows the result of measurement on microstructure of Al alloy of first wiring4, using X-ray diffraction.

As shown inFIG. 5, a void40was observed in the portion of first wiring4between contact-hole embedded metal3serving as an upper plug and through-hole embedded metal6serving as a lower plug. The surface orientation of Al alloy of wiring portions41,42between first insulating layer2and second insulating layer5, was (111), while the surface orientation of Al alloy of wiring portions43,44between contact embedded metals3and through-hole embedded metals6, was (311) or (022). A grain boundary45exists in a region between contact hole embedded metal3and through-hole embedded metal6. Thus, the size of grains in wiring portions43,44is smaller than in wiring portions41,42.

FIG. 6is a view illustrating the result of simulation, using a finite-element method, of internal stress generated in a right-half region X of the region between contact hole embedded metal3and through-hole embedded metal6in the wiring structure inFIG. 5when the temperature was changed from 400° C. to 25° C.

The stress applied to first wiring4at its flat portions was 200˜300 MPa. On the contrary, the stress applied to the portion of first wiring4into which through-hole embedded metal6enters was much higher. More specifically, the stress was 457 MPa when the top of contact embedded metal3is lower the top of first insulating layer2(FIG. 6(a)), and the stress was 449 MPa when the top of contact embedded metal3is located at the same level of the top of first insulating layer2(FIG. 6(b)).

From these tests and simulation, the following factors would be considered to contribute to stress migration failure in multilayer wiring structure of a semiconductor device. When multilayer wiring structure is stored at high temperature, stress migration occurs, in the wiring portion between the opposite upper and lower plugs, particularly in which the upper plug enters into the wiring and strong stress is applied, because grain size is small and surface orientation is weak in stress such as (311) or (022) in the wiring portion.

The following description will discuss embodiments of the present invention with reference to the attached drawings.

A first embodiment of the present invention is arranged such that, in a wiring structure having an upper plug and a lower plug opposite to each other, the overlap rate between upper and lower plugs when viewed in the direction of vertical line of the substrate surface, is reduced to the extent that no voids are generated.

FIG. 7is a view illustrating the relationship, in wiring structure having an upper plug and a lower plug opposite to each other, between rate of acceptable product and overlap rate between the upper and lower plugs. In this embodiment, each of upper and lower plugs is 0.6 μm in diameter, and overlap rates are 0.6 μm, 0.3 μm, 0.2 μm (distances between center of contact surface between upper plug and wiring, and center of contact surface between lower plug and wiring are 0 μm, 0.3 μm, 0.4 μm). The rate of acceptable product is obtained on the basis that wiring of which resistance variation exceeded 20%, is judged as failure after storage at 200° C. for 1,000 hours.

As shown inFIG. 7, acceptable product is 100% when overlap rate is 0.2 μm. This shows that stress migration failure will not occur when overlap rate is not greater than 0.2 μm. Accordingly, by setting the distance between center of contact surface between upper plug and wiring, and center of contact surface between lower plug and wiring, to 0.4 μm or more, i.e., to ⅔ or more of the diameter of each of the upper and lower plugs, a good multilayer wiring structure in which a stress migration failure hardly occurs can be formed.

FIG. 8(a) is a section view of a multilayer wiring structure of a semiconductor device according to a second embodiment of the present invention.

The multilayer wiring structure of a semiconductor device as shown inFIG. 8(a) is produced in the following manner. First, a contact opening as first opening is formed in a first insulating layer2on a semiconductor substrate by dry-etching, a Ti/TiN two-lamination film is formed by sputtering or the like, and W is then embedded in the contact opening by a CVD method. Then, W and the Ti/TiN two-lamination film were subjected to etching-back, and a contact embedded metal3is formed a lower plug in the contact opening. Then, a Ti/TiN two-lamination film is formed, and a Cu-containing Al alloy is formed on this two-lamination film, and a TiN film is formed on the Al alloy, thus forming a first wiring4. A second insulating layer5is formed on the first wiring4. In a through-hole opening as second opening in the second insulating layer5, a through-hole embedded metal6having a composition similar to contact embedded metal3, is formed in a manner similar to forming the contact embedded metal3, the through-hole embedded metal6serving as an upper plug. To lower the contact resistance between first wiring4and through-hole embedded metal6, through-hole embedded metal6is inserted into first wiring4to a depth of about ⅓ or more of the thickness of first wiring4from the top thereof.

A plurality of samples each of which had the multilayer wiring structure as shown inFIG. 8(a), and which were different in recess d1by changing the amount of over-etching at etching-back of W and Ti/TiN two-lamination film were produced. The recesses d1is the height of projecting part4H that projects into lower side and is in contact with contact embedded metal3, from the under surface of first wiring4.FIG. 8(b) is a graph illustrating rate of failure for these samples after storage at 250° C. for 168 hours. Rate of failure is obtained on the basis that samples of which resistance variation exceeded 20%, is judged as failure. InFIG. 8(b), ordinate axis represents rate of failure (%) while abscissa axis represents recess d1(μm). Each of upper and lower plugs is 0.6 μm in diameter.

As apparent fromFIG. 8(b), when recess d1is not greater than 0.2 μm, rate of failure is 0% and stress migration failure has not occurred. Observation by a scanning electron microscope of samples in section after measurement of rate of failure shows the following. In each sample of which the recess d1is larger than 0.2 μm, a grain boundary is almost always present in the region of first wiring4above contact embedded metal3. On the other hand, in each sample of which the recess d1is not greater than 0.2 μm, a grain boundary is hardly present in the region of first wiring4above contact embedded metal3and the grain size in this region is substantially equal to in other region.

From the foregoing, the recess d1of 0.2 μm would be the border line of whether or not a stress migration failure occurs. Accordingly, when recess d1is brought to 0.2 μm or less, i.e., to about ⅓ or less of the diameter of each of upper and lower plugs, a good multilayer wiring structure in which a stress migration failure hardly occurs can be formed.

In the foregoing, the description has been made of the case where an etching-back method using dry-etching is employed for forming contact embedded metal3and through-hole embedded metal6. However, when the etching-back method is used, a residue readily remains, often resulting in over-etching. Thus, the recess d1tends to be increased. On the other hand, when forming the contact embedded metal3and the through-hole embedded metal6with the use of a CMP (Chemical Mechanical Polishing) method, the recess d1can be controlled in size with high precision. Therefore, there can securely be formed a multilayer wiring structure of a semiconductor device according to the second embodiment.

FIG. 9(a) toFIG. 9(f) are section views of the multilayer wiring structure of a semiconductor device at the respective steps of a production method according to a third embodiment of the present invention. As shown inFIG. 9(a), a contact opening2ais formed in a first insulating layer2on a semiconductor substrate1. As shown inFIG. 9(b), a W layer3bis then formed on a Ti/TiN two-lamination layer3a.Then, as shown inFIG. 9(c), the Ti/TiN two-lamination layer3aand the W layer3bon the first insulating layer2, are etched such that the Ti/TiN two-lamination layer3aand the W layer3bremain only in the contact opening2a,thus forming a contact embedded metal3. Formed on the contact embedded metal3is a Ti/TiN two-lamination layer4a,on which formed is a Cu-containing Al alloy4b,on which a TiN layer4cis formed. Thus, a first wiring4is formed.

The Al alloy4bis formed by sputtering at a deposition temperature of not less than 200° C. By depositing Al alloy4bat temperature of not less than 200° C., the crystal of Al alloy4bgrows during deposition. Accordingly, Al alloy4bis formed to fill the recess around contact opening2a.Thus, the portion of Al alloy4bon contact opening2abecomes thicker than other portion of Al alloy4b.

As shown inFIG. 9(d), a second insulating layer5is formed on the first wiring4. A through-hole opening5ais formed in the second insulating layer5. Then, a W layer6bis formed on a Ti/TiN two-lamination layer6a.The through-hole opening5aenters into the first wiring4. However, provision is made such that the depth of that portion of the through-hole opening5aentering into the first wiring4, is equal to or smaller than the difference in level between the top of the contact embedded metal3and the top of that portion of the first insulating layer2around the contact opening2a.By forming the through-hole opening5ain this manner, the depth of that portion of the first wiring4on the contact embedded metal3is equal to or greater than the depth of the other portion of the first wiring4.

As shown inFIG. 9(e), the Ti/TiN two-lamination layer6aand the W layer6bon the second insulating layer5are etched such that the Ti/TiN two-lamination layer6aand the W layer6bremain only in the through-hole opening5a,thus forming a through-hole embedded metal6. Formed on the through-hole embedded metal6is a Ti/TiN two-lamination layer7a,on which formed is a Cu-containing Al alloy7b,on which a TiN layer7cis then formed. Thus, a second wiring7is formed. As shown inFIG. 9(f), a silicon nitride layer8is then formed as a protective layer by a plasma CVD method.

In the multilayer wiring structure of a semiconductor device thus produced, that portion of the Al alloy4bof the first wiring4on the contact embedded metal3has a thickness equal to or greater than that of other portion of the Al alloy4b.Likewise in the second embodiment, a grain boundary hardly existed in that portion of the first wiring4on the contact embedded metal3, i.e., that portion of the Al alloy4bheld by and between the upper- and lower-layer-side plugs opposite to each other. Further, the sizes of the crystal grains in this portion were substantially equal to those in other portion. Thus, likewise in the second embodiment, the structure according to the third embodiment exhibited no increase in wiring resistance due to stress migration failure after the structure had been stored at high temperature.

FIGS. 10(a) and10(b) are views illustrating the relationship between deposition temperature at sputtering and the depth of the portion of first wiring4between upper and lower plugs opposite to each other.FIG. 10(a) shows the sectional structure of a sample used in the test. A contact opening having a diameter of 0.6 μm was formed in first insulating layer2having a thickness of 0.7 μm on semiconductor substrate1, and in this contact opening, contact embedded metal3is formed of W on the Ti/TiN two-lamination film. The distance between the underside of first wiring4and the top of contact embedded metal3is 0.2 μm. Formed on contact embedded metal3were a Ti film having a thickness of 50 nm, a Cu-containing Al alloy having a thickness of 600 nm and a TiN film having a thickness of 30 nm. For the test, the samples were produced at a variety of Al alloy deposition temperatures, and the depth d2of concave portion of first wiring4on contact embedded metal3, was measured through an SEM observation in section.

FIG. 10(b) shows the experiment result. To make the thickness of portion of Al alloy of first wiring4on contact opening, equal to or greater than that of other portion of Al alloy, it is required that depth d2is not greater than 0.2 μm. FromFIG. 10(b), depth d2is not greater than 0.2 μm when Al alloy deposition temperature is not less than 200° C. Then, the Al alloy deposition temperature would preferably be not less than 200° C.

FIG. 11(a) toFIG. 11(e) are section views of the multilayer wiring structure of a semiconductor device at the respective steps of a production method according to a fourth embodiment of the present invention. As shown inFIG. 11(a), a contact opening2aas first opening was formed in a first insulating layer2on a semiconductor substrate1. As shown inFIG. 11(b), a Ti film4dwas formed on the first insulating layer2. Using a CVD method at deposition temperature of 260° C. with dimethyl aluminium hydride used as material gas, an aluminium film in a thickness of 100 nm was deposited on the Ti film4d.Then, a Cu-containing Al alloy was deposited in a thickness of 500 nm at deposition temperature of 400° C. by sputtering, thus forming a CVD aluminium-Al alloy layer4e. Then, a TiN film4fwas formed. The Ti film4d,the CVD aluminium-Al alloy layer4eand the TiN film4fwere processed in the form of a first wiring4. Since the aluminium film was formed using a CVD method, contact opening2awas filled with aluminium. Accordingly, the portion of first wiring4on contact opening2awas sufficiently thicker than the other portion of first wiring4.

As shown inFIG. 11(c), a second insulating layer5was formed on the first wiring4, and a through-hole opening5aas second opening was formed in second insulating layer5. As shown inFIG. 11(d), a CVD aluminium-Al alloy layer7ewas formed on a Ti film7d,and a TiN film7fwas then formed on CVD aluminium-Al alloy layer7e.Ti film7d,the CVD aluminium-Al alloy layer7eand TiN film7fwere processed in the form of a second wiring7. As shown inFIG. 11(e), a silicon nitride layer8was formed as a protective layer by a plasma CVD method.

In such a multilayer wiring structure of a semiconductor device, both a first wiring4and a contact embedded metal3& a through-hole embedded metal6are made of an Al alloy. More specifically, a wiring4and the upper and lower plugs opposite to each other with this wiring interposed, are made of the same material. In such a structure, the stress applied to the portion between upper and lower plugs is remarkably smaller than that in a structure in which upper and lower plugs are made of metal (e.g., W) different from the material of wiring. Accordingly, the structure according to the fourth embodiment exhibited no increase in wiring resistance due to stress migration failure after storage at high temperature.

According to the fourth embodiment, contact opening2aand through-hole opening5awere filled with an Al alloy by CVD and sputtering. However, such filling can be made using CVD only. Alternatively, an Al alloy may be formed by sputtering and then heated or pressurized, causing the Al alloy to flow and fill contact opening2aand through-hole opening5a.

Further, even though upper and lower plugs are different in material from wiring, stress migration failure very seldom occurs as far as the difference in thermal expansion coefficient between the materials of wiring and either of upper and lower plugs is small to the extent that no voids are generated during storage at high temperature.

FIG. 12is a partial enlarged view of a multilayer wiring structure of a semiconductor device according to a fifth embodiment of the present invention, illustrating the portion of a first wiring4between a contact embedded metal3and a through-hole embedded metal6. In the multilayer wiring structure inFIG. 12, the first wiring4comprises a Ti film4a,a Cu-containing Al alloy4band a TiN film4cas high-melting-point metal or high-melting-pint metal alloy which are formed in lamination. First wiring4is in contact with through-hole embedded metal6serving as an upper plug through TiN film4c.

The multilayer wiring structure inFIG. 12is basically produced through steps similar to the third embodiment. However, when forming a through-hole opening5ain second insulating layer5by dry-etching or the like, TiN layer4cof first wiring4is not removed but remains.

According to the multilayer wiring structure of the fifth embodiment, first wiring4is in contact with through-hole embedded metal6through TiN film4c.This TiN film4clessens the stress from the through-hole embedded metal6. This restrains the generation of voids, thus preventing the resistance increase due to stress migration.

There were produced samples shown inFIG. 1(a) with Ti film as high-melting-point metal film, instead of the lowest Ti/TiN two-lamination film of first wiring4, and rate of failure was measured for the samples per thickness of Ti film in the range of 0 to 120 nm.FIG. 13is a graph illustrating, as the results of measurement, the relationship between the rate of failure and the thickness of Ti film. The rate of failure was obtained on the basis that sample of which resistance variation exceeded 20% was judged as failure after storage at 250° C. for 168 hours.

As understood fromFIG. 13, rate of failure is maximized when the thickness of Ti film4ais 50 nm, and rate of failure is equal to zero when the thickness of Ti film4ais 0 nm and not less than 100 nm. The following would be considered as the reason of the relationship between thickness of Ti film and rate of failure as shown inFIG. 13. The stress applied to first wiring4is lessened by Ti film, and this stress lessening effect is increased with an increase in film thickness. On the other hand, when Ti film4ais present, Si in the aluminium alloy is sucked by Ti film4a,causing vacancy to be readily generated in aluminium alloy. It is therefore considered that the results as shown inFIG. 13were obtained based on the balance between stress lessening effect and the susceptibility to vacancy generation in the aluminium alloy.

Accordingly, by excluding the range from 10 nm to 80 nm as the thickness of Ti film4a,i.e., by setting the thickness of Ti film4ato 10 nm or less, or to 80 nm or more, good multilayer wiring structures in which stress migration failure hardly occurs can be formed.

In each of the first to sixth embodiments, the description has been made of the two-layer wiring structure, but the present invention can also be achieved in a multilayer wiring structure having three or more layers.

FIG. 14is a section view of a semiconductor device according to a seventh embodiment of the present invention. Shown inFIG. 14are a silicon substrate51, a silicon oxide layer52, a plurality of first-layer aluminium alloy wirings53each having a width of 2 μm and a length of 10 μm serving as lower-layer wirings, a silicon oxide layer54formed on the first-layer aluminium alloy wirings53, W plugs55serving as lower plugs each having a diameter of 0.5 μm for electrically connecting the first-layer aluminium alloy wirings53to a plurality of second-layer aluminium alloy wirings56serving as 2 μm-square wirings, a silicon oxide layer57formed on the second-layer aluminium alloy wirings56, W plugs58serving as upper plugs each having a diameter of 0.5 μm for electrically connecting the second-layer aluminium alloy wirings56to a plurality of third-layer aluminium alloy wirings59serving as upper-layer wirings each having a width of 2 μm and a length of 10 μm, and a silicon oxide layer60formed on the third-layer aluminium alloy wirings59. A void61is generated and grows in a second-layer aluminium alloy wiring56.

As shown inFIG. 14, in the semiconductor device according to the seventh embodiment of the present invention, the first-layer aluminium alloy wirings53, the second-layer aluminium alloy wirings56and the third-layer aluminium alloy wirings59mutually insulated by the silicon oxide layers54,57, are electrically connected in series through the W plugs55,58. A test pattern71for measuring a via resistance for reliability evaluation, is formed by these serially connected first-layer aluminium alloy wirings53, second-layer aluminium alloy wirings56and third-layer aluminium alloy wirings59, and the W plugs55,58.

The resistance value of the test pattern71is a sum of the resistance values of the aluminium alloy wirings53,56,59and the resistance values of the W plugs55,58. When it is now suppose that the sheet resistance of each of the aluminium alloy wirings53,56,59is equal to 100 mΩ/□, that the resistance value of each of the W plugs55,58is equal to 1 Ω, and that the number of each of the W plugs55,58is 1,000, the resistance value of the test pattern71in a normal mode is equal to 2,500 Ω.

According to the seventh embodiment, the second-layer aluminium alloy wirings56receive stress from the upper and lower W plugs55,58since the test pattern71has a stacked via structure. When the void61grows in the second-layer aluminium alloy wiring56due to a stress migration phenomenon, the test pattern71is accordingly increased in resistance value. Therefore, by measuring the resistance value of the test pattern71, it is possible to detect a disconnection of the second-layer aluminium alloy wiring56in the vicinity of plugs.

FIG. 14shows the case in which the void61is generated in the top of a second-layer aluminium alloy wiring56. In the arrangement of test pattern71of the seventh embodiment, however, the disconnection can be detected even though such a void is generated in the bottom of a second-layer aluminium alloy wiring56.

FIG. 15is a graph illustrating the dependency of stress migration failure upon the wiring area in the semiconductor device according to the seventh embodiment inFIG. 14. Semiconductor devices each having the structure inFIG. 14, were stored at 250° C. for 1,000 hours and the increase rates of the resistance values of their test patterns71were measured. The rate of failure was obtained on the basis that semiconductor devices of which increase rate was not less than 20%, were judged as failure. As a parameter, the area of each second-layer aluminium alloy wiring56was changed in the range from 1 μm2to 100 μm2. InFIG. 15, ordinate axis represents rate of failure (%) after storage for 1,000 hours while abscissa axis represents the area (μm2) of each second-layer aluminium alloy wiring56, i.e., each wiring in contact at its top and underside with plugs. Each wiring thickness was 0.6 μm.

As shown inFIG. 15, semiconductor devices became defective when the area of each second-layer aluminium alloy wiring56in contact at its top and underside with plugs, was not less than 20 μm2. A void generated in a wiring grows when crystal vacancies have been collected. When the wiring volume is small, no void is increased in size of not less than 0.5 μm which will result in a failure, even though all crystal vacancies in a wiring are collected. As understood fromFIG. 15, when the area of a 0.6 μm-thick wiring is not less than 20 μm2, i.e., when the wiring volume is not less than 12 μm3, it is possible to detect, with high sensitivity, an increase in resistance of the wiring due to a void generated and growing in a wiring portion held by and between upper and lower plugs.

FIG. 16is a section view of a semiconductor device according to an eighth embodiment of the present invention. InFIG. 16, like parts are designated by like reference numerals used inFIG. 14. InFIG. 16, second-layer aluminium alloy wirings56A as wirings and third-layer aluminium alloy wirings59A as upper-layer wirings are respectively different in sizes from the second- and third-layer aluminium alloy wirings56,59inFIG. 1.

As shown inFIG. 16, the semiconductor device of the eighth embodiment is arranged such that a plurality of first-layer aluminium alloy wirings53and a plurality of second-layer aluminium alloy wirings56A are insulated by a silicon oxide layer54, and are electrically connected in series to each other through W plugs55, and that a test pattern72for measuring a via resistance for reliability evaluation, is formed by these serially connected first-layer aluminium alloy wirings53and second-layer aluminium alloy wirings56A, the W plugs55, the W plugs58connected to the tops of the second-layer aluminium alloy wirings56A, and the third-layer aluminium alloy wirings59A. Even though in contact with the second-layer aluminium alloy wirings56A, the W plugs58serve as false plugs in which no electric current flows when a voltage is applied to the test pattern72. The W plugs58terminate at the electrically isolated third-layer aluminium alloy wirings59A.

The resistance value of the test pattern72is a sum of the resistance values of the first- and second-layer aluminium alloy wirings53,56A and the resistance values of the W plugs55. When it is now supposed that the sheet resistance of each of the aluminium alloy wirings53,56A, is equal to 100 mΩ/□, that the resistance value of each of the W plugs55is equal to 1 Ω, and that the number of the W plugs55is 1,000, the resistance value of the test pattern72in a normal mode is equal to 1,500 Ω.

According to the eighth embodiment, the second-layer aluminium alloy wirings56A have, on the tops thereof, the electrically isolated W plugs58and the third-layer aluminium alloy wirings59A, and the test pattern72employs a stacked via structure. Thus, the second-layer aluminium alloy wirings56A receive stress from the upper and lower W plugs55,58. When a void61grows in a second-layer aluminium alloy wiring56A due to a stress migration phenomenon, the test pattern72is accordingly increased in resistance value. Therefore, by measuring the resistance value of the test pattern72, it is possible to detect a disconnection of an aluminium alloy wiring56A in the vicinity of plugs. According to the eighth embodiment, the number of the W plugs in the test pattern72is reduced to a half as compared with the seventh embodiment. This reduces the resistance value in the test pattern72in a normal mode, thus further enhancing the detection sensitivity.

FIG. 17is a section view of a semiconductor device according to a ninth embodiment of the present invention. InFIG. 17, like parts are designated by like reference numerals used inFIG. 14. InFIG. 17, first-layer aluminium alloy wirings53B as lower-layer wirings, second-layer aluminium alloy wirings56B as wirings and third-layer aluminium alloy wirings59B as upper-layer wirings are respectively different in sizes from the first-, second- and third-layer aluminium alloy wirings53,56,59inFIG. 14.

As shown inFIG. 17, the semiconductor device of the ninth embodiment is arranged such that a plurality of second-layer aluminium alloy wirings56B and a plurality of third-layer aluminium alloy wirings59B are insulated from each other by a silicon oxide layer57, and are electrically connected in series to each other through W plugs58, and that a test pattern73for measuring a via resistance for reliability evaluation, is formed by these serially connected second-layer aluminium alloy wirings56B and third-layer aluminium alloy wirings59B, the W plugs58, the W plugs55connected to the undersides of the second-layer aluminium alloy wirings56B, and the first-layer aluminium alloy wirings53B. Even though in contact with the second-layer aluminium alloy wirings56B, the W plugs55serve as false plugs in which no electric current flows when a voltage is applied to the test pattern73. The W plugs55terminate at the electrically isolated first-layer aluminium alloy wirings53B.

The resistance value of the test pattern73is a sum of the resistance values of the second- and third-layer aluminium alloy wirings56B,59B and the resistance values of the W plugs58. When it is now supposed that the sheet resistance of each of the aluminium alloy wirings56B,59B, is equal to 100 mΩ/□, that the resistance value of each of the W plugs58is equal to 1 Ω, and that the number of the W plugs58is 1,000, the resistance value of the test pattern73in a normal mode is equal to 1,500 Ω.

According to the ninth embodiment, the second-layer aluminium alloy wirings56B have, at the undersides thereof, the electrically isolated W plugs55and the first-layer aluminium alloy wirings53B, and the test pattern73employs a stacked via structure. Thus, the second-layer aluminium alloy wirings56B receive stress from the upper and lower W plugs55,58. When a void61grows in a second-layer aluminium alloy wiring56B due to a stress migration phenomenon, the test pattern73is accordingly increased in resistance value. Therefore, by measuring the resistance value of the test pattern73, it is possible to detect a disconnection of the aluminium alloy wiring56B in the vicinity of plugs. According to the ninth embodiment, the number of serially connected W plugs in the test pattern73is reduced to a half as compared with the seventh embodiment. This reduces the resistance value of the test pattern73in a normal mode, thus further enhancing the detection sensitivity.

FIG. 18is a section view of a semiconductor device according to a tenth embodiment of the present invention. InFIG. 18, like parts are designated by like reference numerals used in each ofFIGS. 14,16,17. A second-layer aluminium alloy wiring62as a wiring has a width of 0.6 μm and a length of 6 mm. Even though in contact with the second-layer aluminium alloy wiring62, W plugs55serve as false plugs which terminate at electrically isolated first-layer aluminium alloy wirings53B. Even though in contact with the second-layer aluminium alloy wiring62, W plugs58serve as false plugs which terminate at electrically isolated third-layer aluminium alloy wirings59A. Pairs of false plugs65are formed by the W plugs55,58opposite to each other with respect to the second-layer aluminium alloy wiring62.

As shown inFIG. 18, the semiconductor device of the tenth embodiment is arranged such that the second-layer aluminium alloy wiring62is in contact with the pairs of false plugs65and that a test pattern74for measuring a via resistance for reliability evaluation, is formed by the second-layer aluminium alloy wiring62, the pairs of false plugs65, and the first- and third-layer aluminium alloy wirings53B,59A at which the W plugs55,58forming the pairs of false plugs65respectively terminate.

When it is now supposed that the sheet resistance of the aluminium alloy wiring62, is equal to 100 mΩ/□, the resistance value of the test pattern74in a normal mode is equal to

According to the tenth embodiment, the test pattern74has a stacked via structure. Thus, the second-layer aluminium alloy wiring62receives stress from the upper and lower W plugs55,58. When a void61grows in the second-layer aluminium alloy wiring62due to a stress migration phenomenon, the test pattern74is accordingly increased in resistance value. Therefore, by measuring the resistance value of the test pattern74, it is possible to detect a disconnection of the aluminium alloy wiring62in the vicinity of plugs. According to the tenth embodiment, the test pattern74does not have serially connected W plugs. This reduces the resistance value of the test pattern74, thus increasing the sensitivity of detection of an increase in resistance due to a disconnection phenomenon.

FIG. 19is a graph illustrating the dependency of stress migration failure upon the distance between adjacent pairs of false plugs in semiconductor devices according to the embodiment shown inFIG. 18. Likewise in the seventh embodiment, the semiconductor devices each having the arrangement inFIG. 18were stored at 250° C. for 1,000 hours and the rates of increase in resistance value of the test patterns74were measured. Then, the rate of failure was obtained on the basis that semiconductor devices of which increase rate were not less than 20%, were judged as failure. As a parameter, the distance L between adjacent pairs of false plugs65was changed from 1 μm to 100 μm. InFIG. 19, ordinate axis represents rate of failure (%) after storage for 1,000 hours while abscissa axis represents the distance L (μm) between adjacent pairs of false plugs65. Each wiring has a thickness of 0.6 μm.

As shown inFIG. 19, when the distance L between adjacent pairs of false plugs65was not less than 10 μm, a failure occurred in semiconductor devices. A void generated in a wiring grows when crystal defects in the wiring are collected. When the wiring volume is small, no void is increased in size of not less than 0.5 μm which will result in a failure, even though all crystal defects in the wiring are collected. As understood fromFIG. 19, when the distance L between adjacent pairs of false plugs65is not less than 10 μm, it is possible to detect, with high sensitivity, an increase in resistance of a wiring due to the void generated and growing in its portion held by and between a pair of false plugs65.

Modification of Embodiment 10

FIG. 20is a plan view of a modification of the semiconductor device according to the tenth embodiment of the present invention, illustrating that portion of a second-layer aluminium alloy wiring which is in contact with a pair of false plugs. InFIG. 20, a second-layer aluminium alloy wiring62A is in contact at its top and underside with a pair of false plugs65, respectively. In the second-layer aluminium alloy wiring62A, its portion in contact with the pair of false plugs65has a length of 1 μm and a wiring width of 0.4 μm, and other portion has a wiring width of 0.6 μm. The second-layer aluminium alloy wiring62A has a length of 6 mm. Each of the pair of false plugs65has a diameter of 0.5 μm.

When it is now supposed that the sheet resistance of the aluminium alloy wiring62A, is equal to 100 mΩ/□ and that the number of the pairs of false plugs65is 1,000 pairs, the resistance value of the test pattern74is equal to 1,008 Ω. According to this modification, the test pattern74has a stacked via structure. Thus, the second-layer aluminium alloy wiring62A receives stress from the upper and lower W plugs55,58. When a void grows in the second-layer aluminium alloy wiring62A due to a stress migration phenomenon, the test pattern74is accordingly increased in resistance value. Therefore, by measuring the resistance value of the test pattern74, it is possible to detect a disconnection of the aluminium alloy wiring62A in the vicinity of plugs.

In the structure of this modification, the wiring width of those top and underside portions of the second-layer aluminium alloy wiring62A which are in contact with a pair of false plugs65, is smaller than the plug diameter. This securely increases the resistance value of a wiring when the wiring is disconnected due to stress. This enhances the sensitivity of detection of an increase in resistance due to a disconnection phenomenon.

In each of the seventh to tenth embodiments, the description has been made of a semiconductor device having three wiring layers. However, the present invention may be arranged such that a semiconductor device has four or more wiring layers. When four or more wiring layers are disposed, the wiring layer between upper and lower plugs opposite to each other, may be disposed at other wiring layer than the highest and lowest wiring layers.