High aspect ratio MEMS devices and methods for forming the same

An HF vapor etch etches high aspect ratio openings to form MEMS devices and other tightly-packed semiconductor devices with 0.2 um air gaps between structures. The HF vapor etch etches oxide plugs and gaps with void portions and oxide liner portions and further etches oxide layers that are buried beneath silicon and other structures and is ideally suited to release cantilevers and other MEMS devices. The HF vapor etches at room temperature and atmospheric pressure in one embodiment. A process sequence is provided that forms MEMS devices including cantilevers and lateral, in-plane electrodes that are stationary and vibration resistant.

FIELD OF THE DISCLOSURE

The disclosure relates, most generally, to semiconductor manufacturing methods and structures and, more particularly, to forming MEMS (Micro Electro Mechanical System) devices with stationary lateral electrodes using an HF vapor etching process.

BACKGROUND

MEMS (Micro Electro Mechanical System) technologies have become quite prevalent in the semiconductor manufacturing industry. MEMS devices, very small mechanical devices driven by electricity, find utility in many applications. MEMS devices often utilize cantilever-type structures that are free to bend and whose movement is detected by electrodes.

There is a drive to form the cantilevers and other MEMS structures to smaller dimensions as is the case for all semiconductor structures. It is desirable to form the cantilevers or other MEMS devices in close proximity to one another and in close proximity to their respective electrodes. In order to achieve this, it is desirable to form openings with high aspect ratios that are not achievable due to the limitations of commercial etchers. In order to form MEMS devices, it is also necessary to “release” the structures such as by etching an underlying oxide layer beneath the cantilever. There are various challenges associated with having an oxide etchant species access and etch the underlying oxide. Current technologies must utilize release holes that extend through the cantilevers or other moveable mechanical structures to provide access to the underlying oxide. These holes adversely impact the mechanical properties of the MEMS device.

It would be desirable to form MEMS and other devices using processes that can etch high aspect ratio openings and underlying oxide materials.

DETAILED DESCRIPTION

The disclosure provides for an HF (hydrofluoric acid) vapor etch of oxide materials in the formation of various semiconductor devices such as MEMS devices. The HF vapor etch etches oxide materials that line or fill openings having high aspect ratios. Openings with aspect ratios on the order of about 250:1 can be produced by etching oxide from such openings using the HF vapor etch. The HF vapor etch is used, in one embodiment, to form suspended cantilever structures or other moveable structures used as MEMS devices. The HF vapor etch is also used to form other MEMS devices including various beam-type structures such as clamped beam structures or other suspended mechanical features. In addition to etching oxide materials that are disposed in vertical openings formed at the end or sides of a cantilever structure, the HF vapor etch also extends beneath the cantilever structure and etches oxide materials disposed beneath the cantilever structure to release the cantilever structure.

The HF vapor etching is used in various applications to create openings with high aspect ratios by etching oxides. In some embodiments, the HF vapor etching is used to create MEMS devices which utilize upper and lower electrodes in one embodiment and one or more fixed lateral electrodes in another embodiment. In other embodiments, the HF vapor etching is used in other applications. The HF vapor etching finds utility in any application in which openings with high aspect ratios must be etched. The HF vapor etching operation etches subjacent oxide materials that are buried beneath other structures and not accessible from above, i.e., not directly exposed to the etching species.

The disclosure also provides for forming fixed lateral electrodes such as are used in applications in which moveable mechanical structures bend within a plane, i.e. laterally. The fixed lateral electrodes lie in the same plane as the bendable mechanical structures that bend side to side. The fixed lateral electrodes therefore do not vibrate when the moveable mechanical structure bends, since they are stationary.

The following sequence of processing operations illustrates embodiments in which the HF vapor etching operation is used but it should be understood that these represent one of many embodiments in which the HF vapor etching operation is used.

FIG. 1Ais a cross-sectional view showing substrate2with oxide layer4formed on substrate surface8, and etch stop layer6formed over oxide layer4. Substrate2is formed of silicon on one embodiment. In other embodiments, substrate2is formed of GaAs, glass, or other suitable semiconductor manufacturing substrate materials. Etch stop layer6is a SiN film in one embodiment and in other embodiments, etch stop layer6is AlN, SiC, low stress SiN, or other materials that are resistant to HF etching and therefore can serve as suitable etch stop layers. Patterned polysilicon10is formed over etch stop layer6and is used for signal routing in some embodiments. Patterned polysilicon10is used as lower electrodes for MEMS devices in various embodiments.

FIG. 1Aalso shows Si wafer14having thickness16. Release oxide layer18is formed on surface20and includes oxide release trenches22. Release oxide layer18includes a thickness ranging from about 200 Å to about 10 um in various embodiments. Oxide release trenches22extend to surface20and are advantageously positioned to accelerate the removal of subjacent oxide materials including release oxide layer18, during the subsequent HF vapor etching operation. Oxide release trenches22have various dimensions in various embodiments and the number of oxide release trenches22and the proximity of oxide release trenches22to one another varies in various embodiments. SI wafer14is formed of crystalline silicon or other silicon materials in various embodiments.

In other embodiments, release oxide layer18is not formed on silicon wafer14but instead, is formed over the structure formed on substrate2. According to this embodiment, the release oxide layer is formed over patterned polysilicon10and etch stop layer6using various formation methods. A CMP (chemical mechanical polishing) or other polishing operation is used to planarize the structure and tailor the release oxide layer to a desired thickness, in some embodiments.

FIG. 1Bshows a structure formed when silicon wafer14is fusion bonded to substrate2. Various suitable pressures are used to fusion bond the individual substrates together. After the bonding operation, a polishing operation is used in some embodiments to diminish thickness16to a desired thickness. Thickness16ranges from about 5 μm-100 μm after polishing in various embodiments but other thicknesses are used in other embodiments. MEMS devices will be formed from silicon wafer14in many embodiments and therefore thickness16is chosen to produce the desired dimensions for the MEMS structures such as cantilever structures. After polishing, oxide mask24is formed over opposed surface26. Oxide mask24is formed to various suitable thicknesses which may be determined by device application or based on other processing considerations.

One or more etching operations are then used to sequentially etch unmasked portions of oxide mask24and silicon wafer14, to form the structure shown inFIG. 1C. InFIG. 1C, silicon islands32are formed. Silicon islands32have various widths and are spaced from one another by openings30. Each opening30is bounded by silicon sidewalls34. Various suitable photoresist patterning and etching operations are available and are used in various embodiments to produce the structure shown inFIG. 1C. Silicon islands32are spaced apart by various distances and at least some of silicon islands32will be used as MEMS devices in various embodiments.

FIG. 1Dshows the structure ofFIG. 1Cafter a thin oxide deposition operation has been carried out. Thin oxide38is formed on silicon sidewalls34. In one embodiment, thermal oxidation is used. In another embodiment, LPTEOS (low pressure TEOS) deposition is used. TEOS, tetraethyl orthosilicate, is a gaseous compound commonly used in CVD, chemical vapor deposition, of oxides. LPTEOS is therefore a low pressure CVD oxide deposition operation using tetraethyl orthosilicate. Other methods for forming thin oxide38are used in other embodiments. Thin oxide38has a thickness ranging from 0.02 μm to 2 μm in one embodiment but various other thicknesses are used in other embodiments. Thin oxide38formed on silicon sidewalls34occupies portions of openings30and produce smaller gaps, i.e. smaller void areas between adjacent silicon islands32.

FIG. 1Eshows the structure ofFIG. 1Dafter a patterning operation and oxide etching operation are carried out to remove thin oxide38from some silicon sidewalls34. According to some embodiments in which the gaps between silicon islands32inFIG. 1Dhave greater than about a 20:1 aspect ratio, spray coating of photoresist is used. After the photoresist is introduced by spray coating, it is then patterned. An etching operation such as BOE is then used to produce the structure shown inFIG. 1Ewhich includes silicon islands32and trenches40. Some silicon sidewalls34of silicon islands32are exposed and other silicon sidewalls34include unremoved thin oxide38thereon. In other words, some trenches40include thin oxide38on one or both of their lateral sidewalls, and others do not.

FIG. 1Fshows the structure ofFIG. 1Eafter plugs44have been formed. Plugs44fill trenches40ofFIG. 1E. LPCVD, low pressure chemical vapor deposition, or other suitable deposition techniques are used to form plugs44, in various embodiments. The deposition is followed by CMP or other suitable polishing operations to form the structure shown inFIG. 1F. In some embodiments, plugs44are formed of polysilicon and in other embodiments, plugs44are formed of silicon germanium or other suitable conductive or semiconductive materials. It will be seen that some plugs44will be utilized as fixed electrodes in conjunction with the MEMS devices. Some plugs44are formed directly adjacent silicon islands32, and other plugs44are separated from silicon islands32by thin oxide38which has a thickness ranging from 0.02 μm to 2 μm in some embodiments. When thin oxide38is removed, as will be described below, air gaps on the order of 0.02 μm to 2 μm may be formed and openings with aspect ratios of as great as 250:1 may be produced.

FIG. 1Gshows patterned bonding material48formed over the structure shown inFIG. 1F. Patterned bonding material48is advantageous in eutectic bonding. Patterned bonding material48is formed of germanium, Ge, in one embodiment. Patterned bonding material48is formed of other suitable materials such as aluminum, aluminum copper, gold and other suitable conductive materials suitable for eutectic bonding, in other embodiments.

FIG. 1Hshows the structure ofFIG. 1Gafter patterning and etching operations have been sequentially carried out. A patterning operation is carried out to expose portions to be etched. This is followed by an etching operation that removes the exposed (unmasked) silicon sections of the structure ofFIG. 1G. Various suitable silicon etching techniques including RIE (reactive ion etching) and DRIE (deep reactive ion etching) are used in various embodiments to remove some plugs44.

FIG. 1Hshows the structure formed after the silicon etching operation has been carried out.FIG. 1Hshows remaining plugs44and silicon islands32. At some locations, silicon islands32are in direct lateral contact with plugs44. At other locations, silicon islands32are spaced from plugs44. Some silicon islands32are also spaced from one another by gaps. According to the embodiment in which plugs44are polysilicon, the silicon structures including silicon islands32and silicon islands32in combination with plugs44, are separated by gaps50A,50B. Some gaps such as gaps50A are filled with oxide material, i.e. “oxide plugs”. Other gaps such as gaps50B have void areas bounded by oxide materials. The gaps50A,50B represent the space between adjacent silicon structures and may be solid oxide or may include oxide liners with a void therebetween. Gaps50A and50B have various dimensions. Gap width52and thickness16of silicon islands32determine the aspect ratio of a particular gap. The HF vapor etching process of the disclosure has been demonstrated to be effective in etching aspect ratios as great as 250:1. The HF vapor etching process of the disclosure also extends beneath silicon islands32and etches subjacent oxide release layer18to release MEMS structures. Oxide release trenches22expedite the subjacent etching. No holes extend through silicon islands32.

The structure shown inFIG. 1His exposed to a vapor HF environment. In one embodiment, the temperature for the HF vapor etch is room temperature. More particularly, in some exemplary embodiments, the HF vapor is not heated and the etching operation may take place at a temperature within the range of about 60° F. to about 80° F. In another embodiment, the temperature is raised 10-15 degrees with respect to room temperature. Various heating methods are used. In other embodiments, other temperatures are used. Ambient atmospheric pressure is used in some embodiments and an decreased pressure is used in other embodiments. Various concentrations of vaporized HF are used in various embodiments. In some embodiments, the HF vapor is diluted with methanol or other suitable materials.

The HF vapor etching operation is carried out and removes exposed oxide materials to produce the structure shown inFIG. 1I. It can be seen that oxide has been removed from gaps50A and50B ofFIG. 1Hto produce void gaps60. Portions56represent silicon islands32(see previous FIGS.) and silicon islands32in conjunction with plugs44. According to the embodiment in which plugs44are silicon, portions56are silicon. According to this and other embodiments, portions56are spaced from one another by void gaps60. Oxide such as release oxide layer18is also removed from subjacent areas62releasing silicon islands32to serve as MEMS cantilever structures. The HF vapor effectively etches the oxide materials from the gaps to produce void gaps60which may have an aspect ratio of as great as 250:1. Thickness16may range from about 25 μm-75 μm and the width of some void gaps60may be as narrow as 0.2 μm in some embodiments. In other embodiments, other dimensions are used. The HF vapor etch also reaches the otherwise buried oxide layers such as release oxide layer18. (SeeFIG. 1H) Etch stop layer6as described above, stops the etch from penetrating further.

FIGS. 2A-2Frepresent another embodiment representing another sequence of processing operations used instead of the operations shown and described inFIGS. 1C-1F.

FIG. 2Aillustrates a structure such as may be formed by carrying out an etching operation on the structure shown inFIG. 1B.FIG. 2Ais comparable toFIG. 1Cexcept the structure shown inFIG. 2Aincludes each of the silicon islands32having about the same width as one another. Silicon islands32are spaced from one another by openings30. Each opening30is bounded by silicon sidewalls34. Various suitable photoresist patterning and etching operations are available and are used in various embodiments to produce the structure shown inFIG. 2Afrom the structure shown inFIG. 1B. The structure inFIG. 2Aincludes substrate2, oxide layer4, etch stop layer6, release oxide layer18, and oxide mask24. Silicon islands32include thickness16.

FIG. 2Bshows the structure ofFIG. 2Aafter a thin oxide deposition operation has been carried out. Thin oxide38is formed on silicon sidewalls34. Thin oxide38is formed by thermal oxidation in one embodiment. Thin oxide38is formed using LPTEOS deposition methods in another embodiment. Other methods for forming thin oxide38are used in other embodiments. Thin oxide38has a thickness ranging from about 0.02 μm to 2 μm in one embodiment but various other thicknesses are used in other embodiments. Thin oxide38formed on silicon sidewalls34occupies portions of previous openings30to produce smaller void areas lined with thin oxide38, in the gaps between silicon islands32. Voids66are present in the gaps between silicon islands32.

FIG. 2Cshows the structure ofFIG. 2Bafter plugs68are formed within voids66that were present inFIG. 2B. In one embodiment, plugs68are formed of polysilicon. In another embodiment, plugs68are formed of SiGe or other suitable conductive materials. Plugs68are formed by a deposition process such as LPCVD, followed by a polishing operation that planarizes the structure, in one embodiment. In other embodiments, different deposition methods are used. Chemical mechanical polishing is the polishing operation in some exemplary embodiments but other polishing methods are used in other exemplary embodiments. The polishing operation produces substantially planar upper surface70.

A photoresist operation is carried out on the structure shown inFIG. 2Cto produce the structure ofFIG. 2D. Conventional or other photoresist coating methods are used in various embodiments. Although spray coating of photoresist is not required due to planar upper surface70, spray coating can be used in some embodiments.FIG. 2Dshows the structure ofFIG. 2Cafter masking operation and oxide etching operation have been carried out to form a photoresist mask, then etch through oxide mask24. A silicon etching operation is used to etch uncovered portions of silicon islands32. Various oxide and silicon etching operations are used in various exemplary embodiments. The etching operations produce openings74.

FIG. 2Eshows the structure ofFIG. 2Dafter an oxide etching operation has been carried out upon the structure shown inFIG. 2Dwith the photoresist mask (not shown) still intact over the structure shown inFIG. 2D. The etching operation is BOE, buffered oxide etching, in one embodiment. Wet or dry etching operations are used in various embodiments. The etching operation removes exposed oxide portions such as thin oxide layer38from silicon sidewalls34and also exposed portions of release oxide layer18.

FIG. 2Fshows the structure ofFIG. 2Eafter openings74are filled with a further plug material. Further plug material78fills openings74ofFIG. 2E. LPCVD, low pressure chemical vapor deposition, or other suitable deposition techniques can be used. The deposition is followed by CMP or other suitable polishing operations to form the structure shown inFIG. 2F. In some embodiments, further plug material78is formed of polysilicon and in other embodiments, further plug material78is formed of silicon germanium or other suitable conductive or semiconductive materials. Fixed electrode80is formed of further plug material78and plugs68. Fixed electrode80is coupled to patterned polysilicon10which provides electrical connection, in some embodiments. Fixed electrode80is a lateral electrode that can sense the movement of a MEMS structure formed from silicon island32that is immediately adjacent the right hand side of fixed electrode80, after an etching operation is used to release silicon islands32so that released silicon island32that is immediately adjacent the right hand side of fixed electrode80, may serve as a mechanical feature that bends left-to-right.

FIG. 2Fis comparable to the structure shown inFIG. 1Fand can undergo subsequent processing operations such as described in conjunction withFIGS. 1G-1I, including the HF vapor etch.

The structure ofFIG. 1Ishows portions56that include some silicon islands32and other portions56that include silicon islands32in conjunction with additional structures as described above. Some portions56include silicon island portions32from silicon wafer14and plug materials44. According to the embodiment in which plug materials44are polysilicon, portions56are also silicon structures. According to this embodiment,FIG. 1Ishows a number of discrete silicon structures spaced apart by void gaps60. In some embodiments, silicon islands32are used as MEMS structures. It should be understood that each MEMS structure32is anchored to substrate2although the anchor is not shown in the cross section ofFIG. 1I.

FIG. 3shows a portion of the structure ofFIG. 1I, in greater detail. In one embodiment, silicon island32identified within dashed box84moves left-to-right in conjunction with fixed electrode86formed of plug44and which is in the same plane as the MEMS structure, i.e. silicon island32in dashed box84. In another embodiment, silicon island32within dashed box84is a cantilever MEMS structure that moves up and down and works in conjunction with lower electrode88formed of patterned polysilicon10. According to this embodiment upper electrodes may also be formed over the MEMS structure. In other embodiments, the various structures shown inFIG. 1IandFIG. 3are used as various MEMS structures including cantilevers that bend left-to-right, or up-and-down, or other mechanical structures such as other suspended beam-type structures, in various embodiments.

After the structure inFIG. 1Iis formed, subsequent processing operations are carried out. The subsequent processing operations may include the formation of additional electrodes that may be formed over the MEMS structures, additional wiring features and other associated processes and features. The structure inFIG. 1Ican then be packaged using various packaging techniques. In some embodiments, the packaging techniques include additional packaging wafers that may be bonded to the structure inFIG. 1Iand utilized along with through-silicon vias (“TSV's”). Other packaging techniques are used in other embodiments.

According to one aspect, a method for forming a semiconductor device is provided. The method comprises: providing a substrate with structures thereover, the structures spaced apart by gaps including gaps filled with oxide and gaps including voids and lined with oxides and at least some of the structures having a release oxide. liner formed thereunder; and, etching in an HF vapor that removes the oxides in the gaps and the release oxide liner.

In another aspect, a method for forming MEMS (micro electro mechanical system) devices is provided. The method comprises: providing a substrate with discrete silicon-based portions disposed thereover, the discrete silicon-based portions spaced apart by oxide plugs and openings lined with oxide liners; etching the oxide plugs and the oxide liners in an HF vapor thereby producing gaps between the discrete silicon-based portions, the gaps defined by opposed sides of the discrete silicon-based portions, wherein at least some of the discrete silicon-based portions are further processed to serve as MEMS devices.