HOST BANDWIDTH OPTIMIZED DATA STREAM MEMORY WRITES

A system and related method, including memory and processing circuitry, which is to write data of a data stream. The memory includes a first memory portion of a first density and a second memory portion of a second density. The processing circuitry receives a write request. The processing circuitry is then to select to write the data to the first memory portion based on a characteristic of the data stream, wherein both the first memory portion and the second memory portion are available to be written to, and the processing circuitry then causes the data to be written to the first memory portion. The processing circuitry may select to write the data to the first memory portion based on a size of the data stream and/or based on a bandwidth of writing data of the data stream to the memory.

TECHNICAL FIELD

The present disclosure is directed to systems and methods for writing data of a data stream to a memory by host bandwidth optimized data stream memory writes based on characteristics of the data stream.

SUMMARY

In accordance with the present disclosure, systems and methods are provided for writing data of a data stream to a memory by host bandwidth optimized data stream memory writes based on characteristics of the data stream. The system and methods disclosed herein enable the preservation of valuable low-density memory (e.g., single-level cell (SLC) memory), which is used for data that should be accessed quickly. When the system receives write requests from an outside source (e.g., a host device), the system is to allocate system memory to store the data associated with the write requests. The system and methods disclosed herein use host bandwidth optimized data stream memory writes to reduce the likelihood of a large, slow data stream to occupy the valuable low-density memory. This improves the overall access latency and efficiency of the processing circuitry of a storage device (e.g., a solid-state drive device).

In some embodiments, the system (e.g., a storage device) is provided with a memory and processing circuitry that are communicatively coupled to each other. In some embodiments the system can be distributed between a storage device and another device separate from the storage device (e.g., a host device, such as a storage controller device), such as where the host device provides processing circuitry to implement at least some of the functionality described herein. In some embodiments, the processing circuitry receives write requests and signals from the host device. In some embodiments, the processing circuitry selects to write data associated with the write request to the first memory portion based on a characteristic of the data stream when each portion of the memory is available to be written to. The signal received by the processing circuitry may include data such as the characteristic of the data stream which is used by the processing circuitry in the selection to write the data associated with the write request to the first memory portion. The processing circuitry then writes the data associated with the write request to the first memory portion.

DETAILED DESCRIPTION

In accordance with the present disclosure, systems and method are provided for writing data of a data stream to a memory by host bandwidth optimized data stream memory writes based on characteristics of the data stream on a storage device (e.g., a solid-state drive (SSD) device). Conventionally, an SSD device may receive write requests and perform a write based on a low-density memory write first process, which prioritizes writing to a low-density memory regardless of the data stream of write requests. Low-density memory is useful for its quick access time. However low-density memory tends to be a small portion of mass storage memory, compared to high-density memory, which stores more data per memory cell. For example, an SSD device may have a memory that includes a first memory portion of single-level cells (SLCs) and a second memory portion of multi-level cells (MLCs). In some embodiments, the multi-level cells may include any one of dual-level cell (DLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, or any other suitable memory that has a memory density greater than 5 bits per memory cell. If the processing circuitry of the SSD device prioritizes writes to low-density memory portions, the processing circuitry allocates memory in the first memory portion and writes data associated with the write requests to the allocated memory. In such an example, when the write requests are of a large, slow data stream, the processing circuitry still writes the data associated with the write requests to the SLCs of the first memory portion. However, if another data stream, which is small and faster than the previous data stream, is sent by a host device, the SLCs of the first memory portion may still be occupied, forcing the processing circuitry to write the small and faster data stream into the MLCs of the second memory portion, which causes unnecessary data access inefficiencies.

In order to improve the access efficiency of the SSD device, the processing circuitry may process received write requests based on a characteristic of the data stream associated with the write requests. In some embodiments, the write requests are sent by an outside source, such as a host device. In some embodiments, the characteristic of the data stream may be included in a signal sent by the host device. The characteristic of the data stream may include a size of the data stream or a bandwidth of writing data of the data stream to the memory. For example, when a data stream is large in size or is a low-bandwidth data stream, the processing circuitry writes the data associated with the write requests to the high-density MLCs of the second memory portion within the SSD device. Conversely, when the processing circuitry receives a data stream with a small volume of write requests or a high-bandwidth data stream, the processing circuitry then writes the data associated with the write requests to the low-density SLCs of the first memory portion within the SSD device.

In some embodiments, the processing circuitry may initially store the data associated with the write requests in a buffer or other suitable temporary memory in the SSD device. In some embodiments, the first memory portion may be used to buffer the write requests until the processing circuitry determines which portion of memory to store the data associated with the write requests of the whole data stream based on the characteristic of the data stream. For example, the processing circuitry may initially write data associated to write requests of a data stream to a first memory portion of SLCs, but once the processing circuitry determines that the data stream includes a large number of write requests (e.g., a large data stream size) or a low-bandwidth data stream, the processing circuitry may write the initially written data as well as any data from outstanding write requests to the second memory portion. This process of using host bandwidth optimized data stream memory writes based on characteristics of the data stream may be performed to write to a certain portion of memory until that portion of memory is exhausted.

In some embodiments, the memory of the system disclosed herein may contain at least two of the following memory densities: single-level cells (SLCs), dual-level cells (DLCs), triple-level cells (TLCs), quad-level cells (QLCs) and penta-level cells (PLCs). In some embodiments, the system may include more than two portions of memory, wherein each respective portion of memory has a different respective memory density. In some embodiments, the portions of memory may be distributed among at least two SSD devices.

For purposes of brevity and clarity, the features of the disclosure described herein are in the context of an SSD having processing circuitry and memory. However, the principles of the present disclosure may be applied to any other suitable context in which host bandwidth optimized data stream memory writes based on characteristics of the data stream is used. A storage device may include processing circuitry and memory and the processing circuitry and memory are communicatively coupled by a network bus or interface. In some embodiments, the processing circuitry receives data, which may be driven on a network bus or interface from a source outside of the storage device or may be transmitted from within the storage device (e.g., from memory).

In particular, the present disclosure provides systems and methods that use at least two portions of memory, each memory of a respective memory density and respective access time. The systems and methods leverage the at least two portions of memory by writing data associated to write requests to the portion of memory that closely matches the most efficient access times based on the size of the data stream and/or the bandwidth of writing data of the data stream to the memory. This improves the overall throughout of the system, by closely matching the access bandwidth from the system (e.g., an SSD device) to the host bandwidth of the data stream write requests received by the system.

For example, a user of the SSD device could download a large executable or movie file from the Internet or a portable storage device. Such a file tends to be slow, cumbersome streams that are large and sequential in nature and would consume valuable SLC or other low-density memory space. Host bandwidth optimized writes may solve this problem by having an outside source (e.g., a host) driver detect slow streams with large writes span and send a signal to hint to the processing circuitry of the SSD device to transfer the write requests to the QLC or other high-density memory space.

In some embodiments, a processor of the processing circuitry may be a highly parallelized processor capable of handling high bandwidths of incoming data quickly (e.g., by starting simultaneous processing of write requests before completion of previous write requests).

In some embodiments the system and methods of the present disclosure may refer to a storage device system (e.g., an SSD storage system), which includes a storage device such as a solid-state drive device, which is communicatively coupled to the processing circuitry by a network bus or interface.

An SSD is a data storage device that uses integrated circuit assemblies as memory to store data persistently. SSDs have no moving mechanical components, and this feature distinguishes SSDs from traditional electromechanical magnetic disks, such as, hard disk drives (HDDs) or floppy disks, which contain spinning disks and movable read/write heads. Compared to electromechanical disks, SSDs are typically more resistant to physical shock, run silently, have lower access time, and less latency.

Many types of SSDs use NAND-based flash memory which retain data without power and include a type of non-volatile storage technology. Quality of Service (QOS) of an SSD may be related to the predictability of low latency and consistency of high input/output operations per second (IOPS) while servicing read/write input/output (I/O) workloads. This means that the latency or the I/O command completion time needs to be within a specified range without having unexpected outliers. Throughput or I/O rate may also need to be tightly regulated without causing sudden drops in performance level.

The subject matter of this disclosure may be better understood by reference toFIGS.1-5.

FIG.1shows an illustrative diagram of a system100of a storage device102with a processing circuitry104and memory106, in accordance with some embodiments of the present disclosure. In some embodiments, storage device102may be a solid-state storage device (e.g., a solid-state drive device). In some embodiments, processing circuitry104may include a processor or any suitable processing unit. In some embodiments, memory106may be non-volatile memory. It will be understood that the embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, the storage device102may include a hard disk drive (HDD) device in addition to or in place of an SSD. In some embodiments, system100includes a host108, which communicates with the storage device102.

In some embodiments, the processing circuitry104is configured to receive write requests110and/or signals112, where the write request110includes data and a memory address where to write the data of the write request110. In some embodiments, the signals112are indicative of a characteristic of the data stream, such as the volume of data associated with the data stream write requests110or the host bandwidth of sequential write requests. In some embodiments, write requests110and signals112are transmitted on a network bus or interface to the processing circuitry104. In some embodiments, write requests110is transmitted from an external source (e.g., host108). In some embodiments, the processing circuitry104receives data (e.g., write requests110and signals112) from both internal and external sources of the storage device102. There may also be a temporary memory (e.g., a cache or queue) disposed within the processing circuitry104, the temporary memory configured to store any outstanding data that is to be processed by the processing circuitry104.

Additionally, storage device102includes memory106. In some embodiments, memory106includes any one or more of a non-volatile memory, such as Phase Change Memory (PCM), a PCM and switch (PCMS), a Ferroelectric Random Access Memory (FeRAM), or a Ferroelectric Transistor Random Access Memory (FeTRAM), a Memristor, a Spin-Transfer Torque Random Access Memory (STT-RAM), and a Magnetoresistive Random Access Memory (MRAM), any other suitable memory, or any combination thereof. In some embodiments, memory106includes a first memory portion and a second memory portion, each portion of their own respective memory density (e.g., a first memory density and a second memory density). The first memory portion of memory106may be implemented as a cache for the second memory portion. In some implementations, the first memory density is less than the second memory density. For example, the first memory portion includes a single-level cell (SLC) memory, and the second memory portion includes a multi-level cell (MLC) memory, such as a dual-level cell (DLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, or any other suitable memory that has a memory density greater than 5 bits per memory cell. In some embodiments, processing circuitry104is communicatively coupled to memory106, in order to store and access data corresponding to write requests110. In some embodiments, a data bus interface is used to transport write requests110or data associated with the write requests110. The data bus between the memory106and processing circuitry104provides a network bus for accessing or writing of data to memory106(e.g., any one portion of memory106). In some embodiments, the processor or processing unit of processing circuitry104may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. The processor, also referred to herein as processing circuitry104, may include any suitable software, hardware, or both for controlling the memory106and the processing circuitry104. In some embodiments, the storage device102may further include a multi-core processor. Memory106may also include hardware elements for non-transitory storage of instructions, commands, or requests.

The processing circuitry104is configured to perform host bandwidth optimized data stream memory writes based on characteristics of the data stream, where the characteristics of the data stream may include the size of the data stream and bandwidth of writing data of the data stream to the memory. In addition, the processing circuitry104may receive signals112from host108. The signals112are indicative of the characteristics of the data stream which may be used to determine whether to perform host bandwidth optimized data stream memory writes. Once the processing circuitry104receives the signal112, the processing circuitry sets a flag bit, which when set, indicates that the processing circuitry104is using host bandwidth optimized data stream memory writes on write requests110received. The host bandwidth optimized data stream memory writes will ensure that the processing circuitry104stores data in portions of memory106which have a larger memory density than other portions of memory106. The host bandwidth optimized data stream memory writes, completed by the processing circuitry104, improves write performance of the storage device102and reserves valuable portions of memory106, which have lower memory densities, which are not necessary for large, slow sequential streams of data. Even when all portions of memory106are available, the processing circuitry104causes the data to be written to a portion of greater memory density in order to preserve the valuable portion of memory106for smaller, quick streams of data.

Storage devices (for example, SSD devices) may include one or more packages of memory dies (e.g., memory106), where each die includes storage cells. In some embodiments, the storage cells are organized into pages, and pages are organized into blocks. Each storage cell can store one or more bits of information. In some embodiments, the portions of memory wherein each respective portion of memory has a respective density of memory may be distributed among the one or more packages of memory dies.

It will be understood that, while system100depicts an embodiment in which a storage device102is configured to have capabilities for writing data of a data stream to a memory by host bandwidth optimized data stream memory writes based on characteristics of the data stream in accordance with the present disclosure, any other suitable device may be implemented in a similar manner.

For purposes of clarity and brevity, and not by way of limitation, the present disclosure is provided in the context of writing data of a data stream to a memory by host bandwidth optimized data stream memory writes based on characteristics of the data stream, which provides the features and functionalities disclosed herein. The process of writing data of a data stream to a memory by host bandwidth optimized data stream memory writes based on characteristics of the data stream may be configured by any suitable software, hardware, or both for implementing such features and functionalities. Writing data of a data stream to a memory by host bandwidth optimized data stream memory writes based on characteristics of the data stream may be at least partially implemented in, for example, storage device102(e.g., as part of processing circuitry104, or any other suitable device). For example, for a solid-state storage device (e.g., storage device102), host bandwidth optimized data stream memory writes based on characteristics of the data stream may be implemented in processing circuitry104.

FIG.2shows an illustrative diagram of memory system200, including memory106shown inFIG.1, with the memory106including a first memory portion202and a second memory portion204, in accordance with some embodiments of the present disclosure.

The first memory portion202is of a first memory density and performs reads/writes at a first access time and the second memory portion204is of a second memory density and performs reads/writes at a second access time. In some embodiments of memory106, there may be more than two memory portions. For example, in another embodiments of memory system200, memory106also includes a third memory portion (not shown) of a third memory density and a third access time to perform read and writes. In some embodiments, memory106may contain at least two of the following memory densities: single-level cells (SLCs), dual-level cells (DLCs), triple-level cells (TLCs), quad-level cells (QLCs), penta-level cells (PLCs), and any other suitable memory that has a memory density greater than 5 bits per memory cell. In some embodiments, memory106include more than two portions of memory, wherein each respective portion of memory has a different respective memory density. In some embodiments, the portions of memory may be distributed among at least two SSD devices.

The first memory portion202of memory106may be implemented as a cache for the second memory portion. In some implementations, the first memory density is less than the second memory density. For example, the first memory portion202includes a single-level cell (SLC) memory and the second memory portion204includes a multi-level cell (MLC) memory, such as a dual-level cell (DLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, or any other suitable memory that has a memory density greater than 5 bits per memory cell. In some embodiments, each memory portion (e.g., first memory portion202and second memory portion204) is communicatively coupled with each other memory portion in memory106, in order to store and access data corresponding to write requests110or move data corresponding to a respective write request between each memory portion (e.g., from the first memory portion202to the second memory portion204, or from the second memory portion204to the first memory portion202). In some embodiments, data206may include data corresponding to a respective write request110, as well as control data to enable the memory to store the data corresponding to the respective write request to the selected memory portion. In some embodiments, data206has been sent form the processing circuitry104. In some embodiments, a data bus memory interface is used to transport data associated with the write requests110. The data bus memory interface between the first memory portion202and the second memory portion204provides a memory network bus for accessing or writing of data between each memory portion (e.g., the first memory portion202and the second memory portion204).

In some embodiments, memory106includes any one or more of a non-volatile memory, such as Phase Change Memory (PCM), a PCM and switch (PCMS), a Ferroelectric Random Access Memory (FeRAM), or a Ferroelectric Transistor Random Access Memory (FeTRAM), a Memristor, a Spin-Transfer Torque Random Access Memory (STT-RAM), and a Magnetoresistive Random Access Memory (MRAM), any other suitable memory, or any combination thereof. In some embodiments, memory106may include a separate write request cache or other suitable volatile memory to temporarily store write requests before they are processed by the processing circuitry104. In some embodiments, memory106may also include hardware elements for non-transitory storage of instructions, commands, or requests.

FIGS.3A and3Bshow illustrative diagrams of a system at two instances (e.g., a first instance300and a second instance301) performing host bandwidth optimized data stream memory writes, in accordance with some embodiments of the present disclosure. In some embodiments, storage device102may be a solid-state storage device (e.g., a solid-state drive device).

In some embodiments, the system includes a host108, which communicates with the storage device102. The host108may include buffer310, which stores the data stream of write requests (i.e., first write request302, second write request304, third write request306, and fourth write request308) that are to be driven to the storage device102. Buffer310may be implemented as a stack, queue, or any other suitable temporary storage memory. In some implementations, host108drives a signal (e.g., first signal303or second signal305) to the storage device102, where the signal may include data such as the characteristic of the data stream. This signal data may be used by the processing circuitry104in the selection to write the data associated with a respective write request to either of the first memory portion202or the second memory portion204.

In some embodiments, memory106may be non-volatile memory. The first memory portion202of memory106may be implemented as a cache for the second memory portion. In some implementations, the first memory density is less than the second memory density. For example, the first memory portion202includes a single-level cell (SLC) memory and the second memory portion204includes a multi-level cell (MLC) memory, such as a dual-level cell (DLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, or any other suitable memory that has a memory density greater than 5 bits per memory cell.

FIG.3Ashows the system at a first instance300, where host108drives the first write request302to the storage device102. The first write request302is received by processing circuitry104. In some implementations, host108drives a first signal303, which includes data corresponding to the first write request302. The first write request302is one write request of a data stream of write requests, including the second write request304, the third write request306, a fourth write request308. At the first instance300, processing circuitry104processes the first write request302with or without the data included in first signal303.

FIG.3Bshows the system at a second instance301, where processing circuitry104selects to write the data associated with first write request312to the first memory portion202based on characteristics of the data stream of write requests, including characteristics of the first write request302. Processing circuitry104then causes the data associated with first write request312to be written to the first memory portion. Concurrently, at second instance301, host108may drive the second write request304to the storage device102to be received by processing circuitry104. In some implementations, the buffer310is used as a first-in-first-out queue, wherein the head of the buffer is dequeued and is driven to the storage device102. In some implementations, the second write request304may be accompanied by a second signal305. In some embodiments, the data associated with second write request (not shown) is written to the first memory portion202, and the data associated with each subsequent write request of the data stream of write requests (e.g., third write request306, fourth write request308, etc.) is to be written to the first memory portion202while memory space remains available in the first memory portion202.

In some embodiments, processing circuitry104may cause the data associated with the write requests (including data312) to be written to the second memory portion204based on the characteristics of the data stream of write requests (e.g., first write request302, second write request304, third write request306, and fourth write request308), including the data of the first signal303and the second signal305. In such embodiments, the data stream of the write requests may be a large, slow data stream, one in which the processing circuitry determines is to be stored in the more densely-packed second memory portion204.

FIG.4shows a flowchart400of illustrative steps for performing host bandwidth optimized data stream memory writes based on characteristics of the data stream, in accordance with some embodiments of the present disclosure. In some embodiments, the referenced storage device, processing circuitry, memory, first memory portion, second memory portion, host, write request, and signal may be implemented as storage device102, processing circuitry104, and memory106, first memory portion202, second memory portion204, host108, write request110, and signal112, respectively. In some embodiments, the process400can be modified by, for example, having steps rearranged, changed, added, and/or removed.

At step402, the processing circuitry receives a write request to write data to memory, wherein the memory106includes a first memory portion of a first density and a second memory portion of a second memory density. In some embodiments, the write request is received, by the processing circuitry, from a network bus or interface. In some embodiments, the received write request is one of at least two write requests of a data stream. For example, the processing circuitry receives a write request sent from an outside source, such as a host. In some embodiments, the memory may include a third memory portion of a third memory density. In some embodiments, the storage device receives more than one write request. At least one of the received write request may be stored in the memory or a temporary memory, such as a cache or queue, or any form of volatile memory. In some embodiments, the processing circuitry may include a multi-core processor which can perform host bandwidth optimized writes. Once the processing circuitry receives a write request the processing circuitry selects to write the data to the first memory portion based on a characteristic of the data stream, wherein both the first memory portion and the second memory portion are available to be written to, at step404.

At step404, the processing circuitry selects to write the data to the first memory portion based on a characteristic of the data stream, when both the first memory portion and the second memory portion are available to be written to. In some embodiments, if one of the portions of memory is not available to be written to, the processing circuitry is configured to write data associated with the write requests to the available memory portion. In some embodiments the processing circuitry may process received write requests based on a characteristic of the data stream. In some embodiments, the write requests are sent by an outside source, such as a host device (e.g., host108). In some embodiments, the characteristic of the data stream may be included in a separate signal sent by the host device. The characteristic of the data stream may include a size of the data stream or a bandwidth of writing data of the data stream to the memory. For example, when a data stream is large in size or is a low-bandwidth data stream, the processing circuitry writes the data associated with the write requests to the high-density MLCs of the second memory portion within the SSD device. Conversely, when the processing circuitry receives a data stream with a small volume of write requests or a high-bandwidth data stream, the processing circuitry then writes the data associated with the write requests to the low-density SLCs of the first memory portion within the SSD device. Once the processing circuitry selects to write the data to the first memory portion based on a characteristic of the data stream, when both the first memory portion and the second memory portion are still available to be written to, the processing circuitry then causes the data to be written to the first memory portion, at step406.

At step406, processing circuitry causes the data to be written to the first memory portion. The processing circuitry is configured to process the write request and write the data associated with the write request to memory. In some embodiments, the processing circuitry writes the data associated with the write request to the first available memory address in the selected memory portion, such as the first memory portion. In some embodiments, the first memory portion may not have any unused memory space. However, some of the used memory space of the first memory portion may store dirty data, which may not be relevant or needed any longer. Dirty data stored at a respective memory address of the first memory portion may be overwritten in order to clear the old or invalid data, and open memory space to store the data associated with the write request, which is new and more likely to be used. In other embodiments, the processing circuitry may determine to overwrite data of memory addresses in a memory portion selected to be written to based on a first-in-first-out process, a least recently used process, optimal page replacement process, random replacement, or a combination thereof. In some embodiments, the processing circuitry may select to write the data to the second memory portion based on the characteristics of the data stream, when both the first memory portion and the second memory portion are available to be written to. In such an embodiment, in a comparable manner of causing the data to be written to the first memory portion, the processing circuitry causes the data to be written to the second memory portion.

In some embodiments, the processing circuitry104may process a first few write requests of a data stream, which are directed to store the associated data of each of each respective write request of the first few write requests to a first memory portion. However, in such embodiments, after processing the first few write requests of the data stream, processing circuitry may then receive a subsequent write request of the data stream and based on the characteristic of at least the subsequent write request, processing circuitry selects to write the data associated to the subsequent write request in the second memory portion. The processing circuitry may make such a selection based on a characteristic of each of the first few write requests as well as the subsequent write request. In such an embodiment, the data associated with the first few write requests are to be moved or transferred from the first memory portion to the second memory portion. In addition, each additional write request received from the data stream is to be processed by the processing circuitry104and the data of each additional write request stored in the second memory portion of the memory.

FIG.5shows a flowchart of illustrative steps of a subprocess500for selecting to write the data to the first memory portion based on a characteristic of the data stream, wherein both the first memory portion and the second memory portion are available to be written to (e.g., as seen inFIG.4, at404), in accordance with some embodiments of the present disclosure. In some embodiments, the referenced storage device, processing circuitry, memory, first memory portion, second memory portion, host, write request, and signal may be implemented as storage device102, processing circuitry104, and memory106, first memory portion202, second memory portion204, host108, write request110, and signal112, respectively. In some embodiments, the process500can be modified by, for example, having steps rearranged, changed, added, and/or removed. Processing circuitry104may perform subprocess500by selecting to write the data to the first memory portion based on a size of the data stream, at502, or by selecting to write the data to the first memory portion based on a bandwidth of writing data of the data stream to the memory, at504. At502and at504, processing circuitry104selects the to write the data when each of the first memory portion and the second memory portion are available to be written to.

At step502, the processing circuitry selects to write the data to the first memory portion based on a size of the data stream. The size of the data stream may be determined by the number of write requests within the data stream and the data size of the write requests. In some embodiments, the size of the data stream may be defined by the amount of memory space required to store the data stream. In some embodiments, processing circuitry104selects to write the data of a small data stream to a first memory portion, where the first memory portion includes a lesser-dense memory (e.g., SLC) than the second memory portion that includes MLC memory. Conversely, processing circuitry selects to write the data of a large data stream to a second memory portion, so to preserve the first memory portion for data streams that may require quick access reads once stored in memory106.

At step504, the processing circuitry selects to write the data to the first memory portion based on a bandwidth of writing data of the data stream to the memory. The bandwidth of writing data of the data stream to the memory may be determined by the rate of which write requests of the data stream are written to the memory and the data size of the write requests. In some embodiments, the bandwidth of writing data of the data stream to the memory may be constrained by the physical interconnections that are configured to couple the storage device to the host. In some embodiments, processing circuitry104selects to write the data of a high-bandwidth data stream to a first memory portion, where the first memory portion includes a lesser-dense memory (e.g., SLC) than the second memory portion that includes MLC memory. Conversely, processing circuitry selects to write the data of a low-bandwidth data stream to a second memory portion, so to preserve the first memory portion for data streams that may require quick access reads once stored in memory106.

A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments. Further, although process steps, method steps, algorithms or the like may be described in a sequential order, such processes, methods, and algorithms may be configured to work in alternate orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order practical. Further, some steps may be performed simultaneously.

The foregoing description of various embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to be limited to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.