Nonvolatile ferroelectric memory device having a multi-bit control function

A nonvolatile ferroelectric memory device having a multi control function can determine a plurality of cell data in a reference timing strobe interval by setting a plurality of sensing voltage levels when cell data are sensed in a sensing critical voltage. In a read mode, a plurality of read data applied from a cell array block are stored in a timing data register array unit through a common data bus unit. In a write mode, a plurality of read data stored in the timing data register array unit or input data applied from a timing data buffer unit are stored in a cell array block through the common data bus unit. Here, since a plurality of sensing voltage levels are set in cell data, a plurality of sensed data bits can be stored in one cell.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a nonvolatile ferroelectric memory device having a multi-bit control function, and more specifically, to a technology for storing and sensing multi-bit data in a ferroelectric memory cell.

2. Description of the Prior Art

Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.

The FRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.

The technical contents on the above FRAM are disclosed in the Korean Patent Application No. 2002-85533 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FRAM are not described herein.

In the conventional nonvolatile ferroelectric memory, a sensing reference voltage is set to have a proper level when cell data are sensed.

However, as a chip operation voltage of the FeRAM becomes lower, the level of the reference voltage to sense a cell also becomes lower. When the sensing voltage level of the cell data is low, a voltage margin between the sensing voltage and the reference voltage is reduced. As a result, it is difficult to determine data. Also, a sensing margin is reduced by a voltage level change of the reference voltage. Therefore, it is difficult to obtain a rapid operation speed of the FeRAM chip having a1T1C (1transistor,1capacitor).

As a semiconductor memory device becomes smaller, the size of cell also becomes smaller. As a result, a technology for storing a plurality of multi-bit data in a cell is required to improve the efficiency of the cell size.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to detect a plurality of data levels and stored a plurality of data bits in a cell with a sensing critical voltage in a different reference timing strobe interval.

It is another object of the present invention to sense a plurality of data levels with a plurality of sensing critical voltages in a timing strobe interval, thereby storing a plurality of data bits in a cell.

It is still another object of the present invention to embody a chip having an improved data access time by storing a plurality of read/written data through a register.

It is still another object of the present invention to secure the margin of a sensing voltage and improve the operation speed in the embodiment of a chip having a low voltage or a rapid access time by amplifying a self-sensing voltage of cell data in a reference timing interval and judging a plurality of voltage levels of data on a basis of a time axis.

In an embodiment, a nonvolatile ferroelectric memory device having a multi-bit control function comprises a plurality of cell array blocks, a timing data register array unit and a common data bus unit. The plurality of cell array blocks outputs a plurality of different cell data sensing voltages induced in a main bitline in a reference timing strobe interval. Here, each of the plurality of cell array blocks comprises a nonvolatile ferroelectric memory. The timing data register array unit compares the plurality of cell data sensing voltages with a plurality of preset sensing critical voltages to output comparison results corresponding to a plurality of bit data, and converts a plurality of inputted bit data or the plurality of cell data sensing voltage into analog reference level signals. The common data bus unit, connected in common to the plurality of cell array blocks, controls data exchange between the plurality of cell array blocks and the timing data register array unit.

In another embodiment, a nonvolatile ferroelectric memory device having a multi-bit control function comprises a plurality of cell array blocks, a timing data register array unit and a common data bus unit. The plurality of cell array blocks output a plurality of difference cell data sensing voltages induced to a main bitline in a reference timing strobe interval. Here, each of the plurality of cell array blocks comprises a nonvolatile ferroelectric memory. The timing data register array unit outputs a plurality of bit data corresponding to a plurality of sensing data levels detected when the plurality of cell data sensing voltages reach a preset sensing critical voltage, and converts a plurality of inputted bit data or the plurality of sensing data levels into analog reference level signals. The common data bus unit, connected in common to the plurality of cell array blocks, controls data exchange between the plurality of cell array blocks and the timing data register array unit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a diagram of a nonvolatile ferroelectric memory device having a multi-bit control function according to a first embodiment of the present invention.

In an embodiment, the nonvolatile ferroelectric memory device comprises a timing data buffer unit100, a data buffer bus unit200, a timing data register array unit300, a plurality of cell array blocks400and a common data bus unit500.

The cell array block400comprises a plurality of cell arrays for storing data. The cell array block400comprises a bitline cell array having a multi-bitline structure comprising sub bitlines and a main bitline. The multi-bitline structure cell array converts a sensing voltage of the sub bitline into current, and induces a main bitline sensing voltage. Here, the plurality of cell array blocks400share the common data bus unit500.

The timing data buffer unit100is connected to the timing data register array unit300through the data buffer bus unit200. The timing data register array unit300determines data “high” and “low” based on when a voltage level of data passes a sensing critical voltage in sensing data of the common data bus unit500.

In a read mode, data read from the cell array block400are stored in the timing data register array unit300through the common data bus unit500. The read data stored in the timing data register array unit300are outputted into the timing data buffer unit100through the data buffer bus unit200.

In a write mode, input data inputted through the timing data buffer unit100are stored in the timing data register array unit300through the data buffer bus unit200. The input data or read data stored in the timing data register array unit300are written in the cell array block400through the common data bus unit500.

FIG. 2is a diagram of a nonvolatile ferroelectric memory device having a multi-bit control function according to a second embodiment of the present invention.

In an embodiment ofFIG. 2, a plurality of cell array blocks400are arranged above the common data bus unit500, and a plurality of cell array blocks402are arranged under the common data bus unit500. The common data bus unit500is shared by the plurality of cell array blocks400and402. The rest structure is the same as that ofFIG. 1.

FIG. 3is a diagram of the cell array block400ofFIGS. 1 and 2.

The cell array block400comprises a MBL (main bitline) pull-up controller410, a main bitline sensing load unit420, a plurality of sub cell arrays430and a column selecting switch unit440.

Here, a main bitline of the plurality of sub cell arrays430is connected to the common data bus unit500through the column selecting switch unit440.

FIG. 4is a circuit diagram of the main bitline pull-up controller410and the main bitline sensing load unit420ofFIG. 3.

The MBL pull-up controller410comprises a PMOS transistor P1for pulling up a voltage of a main bitline MBL in a precharge mode. The PMOS transistor P1has a source connected to a power voltage VCC terminal, a drain connected to the main bitline MBL, and a gate to receive a main bitline pull-up control signal MBLPUC.

The main bitline sensing load unit420comprises a PMOS transistor P2for controlling sensing load of the main bitline MBL. The PMOS transistor P2has a source connected to a power voltage VCC terminal, a drain connected to the main bitline MBL and a gate to receive a main bitline control signal MBLC.

FIG. 5is a circuit diagram of the column selecting switch unit440ofFIG. 3.

The column selecting switch unit440comprises an NMOS transistor N1and a PMOS transistor P3. Here, the NMOS transistor N1, connected between the main bitline MbL and the common data bus unit500, has a gate to receive a column selecting signal CSN. The PMOS transistor P3, connected between the main bitline MBL and the common data bus unit500, has a gate to receive a column selecting signal CSP.

FIG. 6is a circuit diagram of the sub cell array430ofFIG. 3.

Each main bitline MBL of the sub cell array430is selectively connected to one of a plurality of sub bitlines SBL. That is, when a sub bitline selecting signal SBSW1is activated, an NMOS transistor N6is turned on, thereby activating one sub bitline SBL. One sub bitline SBL is connected to a plurality of cells C.

When a sub bitline pull-down signal SBPD is activated to turn on an NMOS transistor N4, the sub bitline SBL is pulled down to a ground level. A sub bitline pull-up signal SBPU is to control power supplied to the sub bitline SBL. That is, in a low voltage, the sub cell array420generates a voltage higher than a power voltage VCC and supplies the voltage to the sub bitline SBL.

An NMOS transistor N5controls connection between a sub bitline pull-up signal SBPU terminal and the sub bitline SBL in response to a sub bitline selecting signal SBSW2.

An NMOS transistor N3, connected between an NMOS transistor N2and the main bitline MBL, has a gate connected to the sub bitline SBL. The NMOS transistor N2, connected between the ground voltage terminal and the NMOS transistor N3, has a gate to receive a main bitline pull-down signal MBPD, thereby regulating a sensing voltage of the main bitline MBL.

FIG. 7is a diagram of the timing data register array300unit ofFIGS. 1 and 2.

The timing data register array unit300comprises a bus pull-up unit301, a sense amplifier unit302and a data register310. Here, the data register310comprises a lock switching unit311, a data latch unit312, a data input regulator313and a data output regulator314.

In a precharge mode, the bus pull-up unit301pulls up the common data bus unit500to a high level in response to a data bus pull-up control signal DBPUC. The sense amplifier302senses read data applied from the common data bus unit500in response to a sensing control signal SEN1and a sensing pull-up control signal SPU.

The lock switching unit311outputs data applied from the sense amplifier unit302into the data latch unit312in response to a lock signal LOCKN. The data latch unit312stores read data applied from the lock switching unit311and input data applied from the data input regulator313in response to a sensing control signal SEN2.

In the write mode, the data input regulator313outputs a coding signal DEC—ENC<n> applied from a decoder into the data latch unit312in response to a write control signal WSN. The data output regulator314outputs data applied from the data latch unit312as data register signals DREG<n> into a D/A converter or the data buffer bus unit200in response to a control signal WHSN and a read control signal RSN.

In the read mode, the timing data register array unit300senses cell data applied from the common data bus unit500through the sense amplifier unit302, and stores the sensed data in the data latch unit312through the lock switching unit311. Data stored in the data latch unit312are outputted into the data buffer bus unit200through the data output regulator314. Data stored in the data output regulator314are feedback outputted as data register signals DREG<n> into a D/A converter350, and used to restore destroyed data.

In the write mode, data applied from the data buffer bus unit200are stored in the data latch unit312through the data input regulator313. Data stored in the data latch unit312are outputted into the common data bus unit500through the data output regulator314.

FIG. 8is a circuit diagram of the bus pull-up unit301and the sense amplifier302ofFIG. 7.

The bus pull-up unit301comprises a PMOS transistor P4for pulling up the common data bus unit500to a power voltage VCC level in a precharge mode. The PMOS transistor P4, connected between the power voltage VCC terminal and the common data bus unit500, has a gate to receive a data bus pull-up control signal DBPUC.

The sense amplifier unit302comprises PMOS transistors P5, P6, NMOS transistors N7, N8and an inverter IV1. The PMOS transistor P5, connected between the power voltage VCC terminal and a node SL, has a gate connected to the common data bus unit500.

The PMOS transistor P6, connected between the power voltage VCC terminal and the node SL, has a gate to receive a sensing pull-up control signal SPU. In the precharge mode, when the sensing pull-up control signal SPU is disabled, the PMOS transistor P6pulls up the node SL to the power voltage VCC level. In an active mode, the sensing pull-up control signal SPU is inactivated, and the sensing control signal SEN1is activated, thereby activating the PMOS transistor P5and the NMOS transistor N7.

The NMOS transistor N7, connected between the node SL and the NMOS transistor N8, has a gate connected to the common data bus unit500. The NMOS transistor N8, connected between the NMOS transistor N7and the ground voltage terminal, has a gate to receive the sensing control signal SEN1. Here, the sensing control signal SEN1determines activation of the PMOS transistor P5and the NMOS transistor N7to sense data levels of the common data bus unit500.

The inverter IV1inverts a signal of the node SL, and outputs the inverted signal into the node /SL. Here, in the active interval, the sensing pull-up control signal SPU and the sensing control signal SEN1are enabled to a high level.

FIG. 9is a circuit diagram of the data register310ofFIG. 7.

The lock switching unit311comprises transmission gates T1and T2. The transmission gate T1switched in response to lock signals LOCKN/LOCKP outputs an output signal from the node SL into a node CN1of the data latch unit312. The transmission gate T2switched in response to the lock signals LOCKN/LOCKP outputs an output signal from a node /SL into a node CN2of the data latch unit312.

The voltage change rate of the main bitline MBL is different depending on the voltage level of the sub bitline SBL, and a data voltage level of the common data bus unit500reaches a sensing critical value at a different time. When voltage levels of data high and low transmitted into the common data bus unit500reach sensing critical values, the data register310generates the lock signals LOCKN/LOCKP.

The data latch unit312comprises PMOS transistors P7and P8cross-coupled, NMOS transistors N9and N10cross-coupled, and an NMOS transistor N11. When the sensing control signal SEN2is activated, the NMOS transistor N11is turned on to activate a latch circuit, thereby latching data applied from the lock switching unit311or the data input regulator313.

The data input regulator313comprises transmission gates T3˜T5, an inverter IV2and an NMOS transistor N12. The transmission gate T5outputs a coding signal DEC—ENC<n> into the inverter IV2in response to write control signals WSN and WSP. When the write control signal WSP is enabled, the NMOS transistor N12is turned on to pull down an input terminal of the inverter IV2. The transmission gate T3outputs an output signal from the transmission gate T5into the node CN1in response to the write control signals WSN and WSP. The transmission gate T4outputs an output signal from the inverter IV2into the node CN2in response to the write control signals WSN and WSP.

The data output regulator314comprises transmission gates T6and T7, an NMOS transistor N13and an inverter IV3. The transmission gate T6outputs an output signal from the node CN2into a node ND1in response to control signals WHSN and WHSP. IF the controls signal WHSN is activated, an output signal from the data latch unit312is outputted into the node ND1.

When the control signal WHSP is activated, the NMOS transistor N13pulls down the node ND1to a low level. The transmission gate T7outputs an output signal from the node ND1inverted by the inverter IV3as a decoding signal DEC—ENC<n> into the encoder340in response to the read control signals RSN and RSP. Here, in restore of data, an output signal from the inverter IV3is outputted as a data register signal DREG<n> into a D/A converter.

FIG. 10is a timing diagram illustrating the operation of the sense amplifier302ofFIG. 7.

In an interval TO, a wordline WL and a plateline PL are inactivated, the main bitline MBL and the common data bus unit500are precharged to a high level. Here, the sub bitline SBL is precharged to a low level, and the node SL is precharged to a high level by the sensing pull-up control signal SPU. The sensing control signal SEN1is kept disabled.

In an interval T1, if cell data are read, a sensing voltage level of the sub bitline SBL is determined depending on a value of the sensed data. Voltages of the main bitline MBL and the common data bus unit500precharged to a high level depending on a sensing voltage of the sub bitline SBL are pulled down. Here, the amount of current flowing in the NMOS transistor N3is differentiated depending on the sensing voltage of the sub bitline SBL. As a result, the change rage of the sensing voltage of the main bitline MBL and the common data bus unit500are differentiated.

When the sensing voltage of the sub bitline SBL is “high”, the sensing voltage of the common data bus unit500is rapidly reduced to the sensing critical voltage in an interval T2. However, when the sensing voltage of the sub bitline SBL is “low”, the sensing voltage of the common data bus unit500is slowly reduced than data “high” to the sensing critical voltage in an interval T3.

Data of the nodes SL and /SL of the sense amplifier unit302are divided into data “high” and “low” in the interval T2. If the data of the nodes SL and /SL are detected for the interval T2as a timing detecting strobe interval, available data of the common data bus unit500can be obtained. In the interval T2, the sensing voltage of the common data bus unit500is higher or lower than the sensing critical voltage depending on values of the cell data. As a result, the PMOS transistor P5or the NMOS transistor N7of the sense amplification unit302are selectively turned on, the values of the nodes SL and /SL are divided into data “high” and “low”.

When the sensing control signal SEN1is at a high level, the data of the nodes SL and /SL detected by the sense amplifier unit302are stored in the data latch unit312by the lock signals LOCKN/LOCKP. Thereafter, data stored in the data latch unit312are outputted as decoding signals DEC—ENC<n> or data register signals DREG<n> through the data output regulator314.

FIG. 11is a timing diagram illustrating the write operation of the data register array unit300ofFIG. 1when a selected column operates.

In the active mode, the write enable signal WEB is activated, and the column selecting decoding signal Yi<n> is activated. As the write control signal WSN becomes at a high level, and the control signal WHSN becomes at a low level.

In a data sensing interval, after the sensing control signal SEN1is activated, the sensing control signal SEN2is activated, and the sensed data are latched in the data latch unit312. Here, the latched sensing data are not transmitted into the common data bus unit because the control signal WHSN is inactivated.

If the sensing control signal SEN1is inactivated, the lock signal LOCKN is also inactivated to prevent the sensed data from being transmitted into the data latch unit312.

If data to be written in the data buffer bus unit200are applied, the corresponding data are latched in the data latch unit314through the data input regulator313. If the control signal WHSN is activated, the latched data are outputted as data register signals DREG<n>. Here, the read control signal RSN is maintained at a low level.

FIG. 12is a timing diagram illustrating the write operation of the data register array unit300ofFIG. 1when an unselected column operates.

When a column is not selected, a restore operation is performed even though an external command is a write command. When the write enable signal WEB is activated, the write control signal WSN is maintained at a low level and the control signal WHSN is maintained at a high level. As a result, write data of the data buffer bus unit200are not transmitted into the data latch unit312.

Then, the sensed data are stored in the data latch unit312and outputted into the common data bus unit500, and the unselected column data operate into a restore mode.

FIGS. 13 and 14are diagrams illustrating a 2 bit recording level according to an embodiment of the present invention.

4(22) level data is required to store 2 bits in a memory cell. That is, data levels of 00, 01, 10 and 11 are required. Thus, in order to store data of four levels in a cell, a voltage level is divided into VW1(VPP), VW2, VW3and VW4(VSS), and stored.

Hereinafter, the write operation of 2 bit data is described.

If a VW1(VPP) voltage is applied to a cell while the plate line PL is at the ground voltage VSS level, hidden data “1” is written in all cells.

Next, when a pumping voltage VPP is applied to the plateline PL, a voltage VW2is applied to the sub bitline SBL and the main bitlines MBL to store a data level 10. As a result, a voltage VW1–VW2is applied to the plateline PL and the sub bitline SBL. That is, the charge initially stored in the cell is reduced to that corresponding to the voltage VW1–VW2. Thus, a data level 11 transits to the data level 10.

Thereafter, data levels 01 and 00 are stored in the cell by applying different voltages VW3and VW4to the sub bitline SBL and the main bitline MBL.

FIG. 15is a diagram of the timing data register array unit300ofFIGS. 1 and 2.

The sense amplifier array unit303comprises a plurality of sense amplifiers302described inFIG. 8. The sense amplifier array unit303sets a plurality of sensing critical voltages by regulating the sensing size of the PMOS transistor P5and the NMOS transistor N7in order to sense read data applied through the common data bus unit500as a plurality of data levels.

The sense amplifier unit302is set to have different sensing critical voltages. That is, the lowest sensing critical voltage is set in the sense amplifier (0)302, the second lowest sensing critical voltage is set in the sense amplifier (1)302, and the highest sensing critical voltage is set in the sense amplifier (2)302.

Data 11 and 10 can be determined in the sense amplifier (0)302, data 10 and 01 in the sense amplifier (1)302, and data 01 and 00 in the sense amplifier (2)302.

The data register array unit320comprising a plurality of data registers310described inFIG. 7latches a plurality of sensing data levels applied from the sense amplifier array unit303in response to lock signals LOCKN0˜LOCKN2. The data register array unit320outputs data register signals DREF<0:2> into the D/A converter350in response to the control signal WHSN and the read control signal RSN to restore read data. The data register array unit320stores coding signals DEC—ENC<0:2> applied through the decoder330, and outputs the coding signals DEC—ENC<0:2> stored in the encoder340.

The timing data register array unit300comprises three sense amplifiers302to process 2 bit data. The timing data register array unit300compares four data sensing levels with three sensing critical voltages, and stores the comparison results in the three data registers310.

The decoder330decodes input data applied from the timing data buffer unit100through the data buffer bus unit200, and outputs the coding signals DEC—ENC<0:2> into the data register array units320. The encoder340encodes the coding signals DEC—ENC<0:2> applied from the data register array unit320, and outputs the encodes signals into the timing data buffer unit100through the data buffer bus unit200.

The D/A converter350converts a plurality of data register signals DREG<0:2> applied from the data register array unit340into analog signals, and outputs the converted signals into the common data bus unit500.

FIG. 16is a timing diagram illustrating the operation of the timing data register array unit300ofFIG. 15.

In an interval T1, lock signals LOCKN<n> are enabled, and a plurality of cell sensing data 00,01,10 and 11 are applied to the sub bitline SBL. A plurality of data sensing levels in the sub bitline SBL are separated into a plurality of main bitline MBL signals. The plurality of sensing levels applied to the main bitline MBL are compared with a plurality of sensing critical voltages preset in the sense amplifier302.

In an interval T2, if the sensing control signal SEN1is enabled, the sense amplifier302is activated, and a plurality of cell sensing data 11,10,01 and 00 having a plurality of voltage levels are outputted through the node SL and /SL.

If the sensing control signal SEN2is enabled, the data latch unit312is activated, and read data having a plurality of sensing levels are continuously stored in the data latch unit312. As a result, for the reference timing strobe interval, a plurality of cell sensing data 00,01,10 and 11 which reach a plurality of sensing critical voltages have different voltage values in the main bitline MBL.

In the interval T2, while the sensing control signal SEN2is enabled, a plurality of data sensed in the sense amplifier302are stored in the three data registers310. If the lock LOCKN<n< transits to a low level, the lock switching unit311is disconnected, and read data are no longer inputted into the data latch unit312. When the clock signal LOCKN is disabled and the reference timing strobe is applied, the previously stored data in the data latch unit312can be continuously maintained.

Thereafter, in an interval T3, if the sensing control signal SEN1and the lock signal LOCKN transit to a low level, the sense amplifier unit302and the lock switching unit311are inactivated. As a result, the node SL is enabled to a high level regardless of voltage levels of a plurality of cell data.

FIG. 17shows another example of the timing data register array unit300ofFIGS. 1 and 2.

When compared withFIG. 15, one sense amplifier302is used in the timing data register array unit300ofFIG. 17. As a result, the sensing critical voltage of the sense amplifier302is set to have one value.

The timing data register array unit300requires data processing of 4 levels to process 2 bit data. Four data sensing levels are compared in one sensing critical voltage with difference timing references, and the comparison results are stored in the three data registers310. In one sensing critical voltage, a plurality of cell sensing data levels are detected by regulating timing of the lock signal LOCKN controlled by the difference reference timing.

FIG. 18is a timing diagram illustrating the operation of the timing data register array unit300ofFIG. 17.

For reference timing strobe intervals T2˜T4, the sensing control signal SEN1is maintained at a high level, thereby activating the sense amplifier302. In the interval T2, the sensing control signal SEN2<0> becomes at a high level and the lock signal LOCKN0becomes at a low level. As a result, data 11 and 10 are determined and stored in the data register (0)310.

In the interval T3, the sensing control signal SEN2<1> becomes at a high level, and the lock signal LOCKN1becomes at a low level. As a result, data 10 and 01 are determined, and stored in the data register (1)310. In the interval T4, the sensing control signal SEN2<2> becomes at a high level, and the lock signal LOCKN2becomes at a low level. As a result, data 01 and 00 are determined, and stored in the data register (2)310.

FIG. 19is a diagram of the D/A converter350ofFIGS. 15 and 17.

The D/A converter350comprises a reference level generator351and a common data bus driving unit355.

The reference level generator351outputs a reference level signal DAC—REF in response to a plurality of data register signals DREG<0:2> applied from the data register array unit320, a plateline control signal DAC—PL and an equalizing signal DAC—EQ. The reference level generator351generates 4 cell recording voltage levels using three data register signals DREG<0:2> to process 2 bit data.

The reference level generator351outputs the reference level signal DAC—REF having a data level “3” when the data register signals DREG<0:2> are all “1”. The reference level generator351outputs the reference level signal DAC—REF having a data level “2” when the data register signal DREF<0> is “0” and the other data register signals DREF<1> and DREF<2> are “1”.

The reference level generator351outputs the reference level signal DAC—REF having a data level “1” when the data register signal DREF<2> is “1” and the data register signals DREF<0> and DREF<l> are “0”. The reference level generator351outputs the reference level signal DAC—REF having a data level “0” when the data register signals DREF<0:2> are all “0”.

The common data bus driving unit385drives the reference level signal DAC—REF and outputs the driven signal DAC—REF into the common data bus unit600.

FIG. 20is a circuit diagram of the reference level generator351ofFIG. 19.

The reference level generator351comprises a switching unit352, a capacitor regulator353and a precharge controller354.

The switching unit352comprises a plurality of inverters IV4˜IV6, and a plurality of transmission switches T8˜T10. The capacitor regulator353comprises a plurality of nonvolatile ferroelectric capacitors FC1˜FC3. The precharge controller354comprises an NMOS transistor N14. The NMOS transistor N14, connected between a reference level signal DAC—REF output terminal and a ground voltage VSS terminal, has a gate to receive an equalizing signal DAC—EQ.

The inverters IV4˜IV6in the switching unit352invert a plurality of data register signals DREG<0:2> applied from the data register array unit320. The transmission gates T8˜T10selectively outputs a plateline control signal DAC—PL in response to the plurality of data register signals DREG<0:2>.

The nonvolatile ferroelectric capacitors FC1˜FC3controls a data voltage level of the reference level signal DAC—REF by selectively regulating the size of the capacitor outputted in response to output signals from the transmission gates T8˜T10, respectively.

During the precharge interval, the equalizing signal DAC—EQ becomes at a high level, and the NMOS transistor N14is turned on to precharge the reference level signal DAC—REF to a low level.

FIG. 21is a circuit diagram of the common data bus driving unit355ofFIG. 19.

The common data bus driving unit355comprises a buffer356and a driving unit355. The buffer356amplifies a current driving capacity of the reference level signal DAC—REF. Here, the voltage of the reference level signal DAC—REF is the same as that of the common data bus unit500.

The driving unit357comprises an inverter IV7and a transmission gate T11. The driving unit357selectively outputs an output signal from the buffer356into the common data bus unit500in response to the driving enable signal DAC—EN enabled only in the write mode.

FIG. 22is a timing diagram of the D/A converter350ofFIGS. 15 and 17.

In an interval t0, the plateline control signal DAC—PL transits to a low level, and is maintained at a high level after an interval t1. As a result, noise charge is removed of the capacitor regulator353. In addition, the equalizing signal DAC—EQ becomes at a high level, thereby initializing the capacitor regulator353to a low level.

When the interval t1starts, the equalizing signal DAC—EQ transits to a low level. The driving enable signal DAC—EN is enabled during the write mode of the interval t1in order to write data in the cell array block400through the common data bus unit500. The voltage level of the reference level signal DAC—REF is determined in response to the plurality of data register signals DREG<0:2>.

In other words, when the plurality of data register signals DREG<0:2> are all at a high level, the voltage level of the plateline control signal DAC—PL is applied to the three nonvolatile ferroelectric capacitors FC1˜FC3of the capacitor regulator353. As a result, the reference level signal DAC—REF is outputted with the highest voltage level.

On the other hand, when the plurality of data register signals DREG<0:2> are all at a low level, the voltage level of the plateline control signal DAC—PL is not applied to the nonvolatile ferroelectric capacitors FC1˜FC3of the capacitor regulator353. As a result, the reference level signal DAC—REF is outputted with the lowest voltage level.

In the initial operation, since the common data bus unit500is precharged to a high level, the reference level signal DAC—REF is written in the write mode.

FIG. 23is a timing diagram illustrating the write operation of a nonvolatile ferroelectric memory device having a multi-bit control function.

When an interval t1starts, if the chip selective signal CSB and the write enable signal /WE are disabled to a low level, the write operation becomes active. Here, the sub bitline pull-down signal SBPD and the main bitline control signal MBLC are disabled to a low level. The main bitline pull-up control signal MBLPUC is enabled to a high level.

Thereafter, when an interval t2starts, if the wordline WL and the plateline PL are enabled to a pumping voltage VPP, the voltage level of the sub bitline SBL rises. Then, the column selecting signal CSN is enabled to connect the common data bus unit500to the main bitline MBL.

Next, when an interval t3, a data sensing interval, starts, the sense amplifier enable signal SEN is enabled to apply cell data to the main bitline MBL.

When an interval t4starts, the plateline PL is disabled to a low level, and the sub bitline selecting signal SBSW2is enabled to a high level. Here, the sub bitline pull-down signal SBPD is enabled to a high level, and the sub bitline SBL and the main bitline pull-down signal MBPD are disabled to a low level.

In an interval t5, hidden data “1” is written. When the interval t5starts, the voltage of the wordline WL rises, and the sub bitline selecting signal SBSW2is enabled to the pumping voltage VPP level in response to the sub bitline pull-up signal SBPU. As a result, the voltage level of the sub bitline SBL rises to the pumping voltage VPP level.

In an interval t6, multi-level data can be written in response to the write enable signal /WE. When the interval t6starts, the plateline PL is enabled again. Then, the sub bitline selecting signal SWSB1rises to the pumping voltage VPP level, and the sub bitline selecting signal SBSW2is disabled. Here, the main bitline control signal MBLC is enabled to a high level.

Therefore, while the sub bitline selecting signal SWSB1is at the pumping voltage VPP level, a plurality of data can be written in the memory cell depending on multi-voltages VW1˜VW4levels applied to the sub bitline SBL and the main bitline MBL.

When an interval t7starts, the wordline WL, the plateline PL, the sub bitline selecting signal SBSW1and the sub bitline pull-up signal SBPU are disabled. Then, the sub bitline pull-down signal SBPD is enabled, and the sense amplifier enable signal SEN is disabled. The main bitline pull-up control signal MBLPUC is disabled, and the main bitline MBL is precharged to the power voltage VCC level. Here, the column selecting signal CSN is disabled to disconnect the common data bus unit500to the main bitline MBL.

FIG. 24is a timing diagram illustrating the read operation of a nonvolatile ferroelectric memory device having a multi-bit control function.

In the read mode, the write enable signal /WE is maintained at the power voltage VCC level. In the interval t2and t3, data are sensed. In the interval t5, hidden data “1” is written, and a data output available interval is maintained after the interval t5.

The cell array block400does not write input data externally inputted through the timing data buffer unit100in the cell. Instead, the cell array block400restores read data stored in the timing data register array unit300in the cell.

Thereafter, in the interval t6, a plurality of multiple level data are restored. That is, while the sub bitline selecting signal SBSW1is at a high level, multiple levels of the voltages VW1˜VW4are applied to the sub bitline SBL and the main bitline MBL by a feedback decoder loop. As a result, the multiple levels are restored in the memory cell.

During the interval t6, a plurality of data levels stored in the cell array block400are sensed, and outputted through the common data bus unit500.

As described above, in a nonvolatile ferroelectric memory device according to an embodiment of the present invention, a plurality of data levels are detected by differentiating timing of a reference timing strobe interval using a sensing critical voltage, and a plurality of data bits are stored in a cell, thereby improving the sensing margin. Also, a plurality of data levels are detected in a timing strobe interval using a plurality of sensing critical voltages, and a plurality of data bits are stored in a cell, thereby improving the sensing margin. Since a plurality of read/written data are stored through a register, a chip having an improved access time can be obtained. In addition, a self-sensing voltage of cell data is amplified in a reference timing interval and a plurality of data voltage levels are determined on a basis of a time axis, thereby securing the margin of the sensing voltage and improving the operation speed.