High performance I2C transmitter and bus supply independent receiver, supporting large supply voltage variations

One or more embodiments are directed to inter-integrated circuit (I2C) transmitters, receivers, and devices that utilize a stable reference voltage for driving a pre-driver of the transmitter and for driving a first input stage of the receiver. One embodiment is directed to a device A device that includes an inter-integrated circuit (I2C) transmitter and an I2C receiver. The I2C transmitter includes a driver coupled to an I2C data line, and a pre-driver coupled to a variable first supply voltage, a second supply voltage, and a reference voltage. The pre-driver is configured to output a control signal to a control terminal of the driver. The I2C receiver includes a first stage coupled to the I2C data line, the variable first supply voltage, the second supply voltage, and the reference voltage.

BACKGROUND

Technical Field

The present disclosure is generally related to inter-integrated circuit (I2C) transmitter and receiver circuits, and more particularly, to I2C transmitters and receivers that receive a stable reference voltage for driving a last stage of the transmitter and a first stage of the receiver.

Description of the Related Art

Input/Output buffers (I/Os) form an integral part of any chip. These I/Os are circuits that help the chip communicate with the external environment, e.g., to transmit and receive data from other chips or devices. The external environment can be unpredictable at times, and further, the operation conditions of the I/Os themselves can experience many changes, which adds a further degree of complexity.

In battery operated circuits, which typically operate for large ranges of supply voltages, the drive capability of an NMOS transistor varies quadratically with the supply voltage. In such scenarios, it is very difficult to meet stringent specifications such as inter-integrated circuit (I2C) specifications for Tr, Tf, loopdelay, and the like.

Original implementations of I2C supported data signaling rates of up to 100 kilobits per second (100 kbps) in standard-mode operation, with more recent standards supporting speeds of 400 kbps in a fast-mode operation, and 1 megabit per second (Mbps) in a fast-mode plus (Fast+ mode) operation.

BRIEF SUMMARY

The present disclosure provides various embodiments of I2C I/O transmitters and receivers that receive a stable reference voltage in place of a variable supply voltage in at least one of the stages of the transmitter or receiver. The transmitter has a stable reference voltage (e.g. Vref) coupled to a last stage in the transmitter (e.g., a last stage of the pre-driver in a transmitter), in contrast to the conventional approach, in which a variable supply voltage (VDDE) is used as the supply voltage for all stages of the transmitter. Because Vref is stable, the transmitter drive spread is decreased, and the transmitter's operating speed is increased.

The same concept is applied to the receiver. Namely, a stable reference voltage (Vref) is used to drive the first stage of the receiver (e.g., an inverting Schmitt trigger or an inverter), instead of using VDDE. Vref is always lower than a bus supply voltage VBUS provided to the I2C data line, which prevents any short circuit current from being consumed in the receiver.

In one embodiment, the present disclosure provides an inter-integrated circuit (I2C) transmitter that includes an input terminal, an output terminal, a driver coupled to an I2C data line via the output terminal, and a pre-driver. The pre-driver is coupled to a variable first supply voltage, a second supply voltage, and a reference voltage. The pre-driver outputs a control signal to a control terminal of the driver based on an input signal at the input terminal, and the control signal has a voltage level of one of the second supply voltage and the reference voltage.

In another embodiment, the present disclosure provides an inter-integrated circuit (I2C) receiver that includes an input terminal, an output terminal, and a first stage. The first stage is coupled to an I2C data line via the input terminal, and the first stage coupled to a variable first supply voltage, a second supply voltage, and a reference voltage. The reference voltage has a voltage level that is less than a lowest voltage level of a variable bus supply voltage supplied to the I2C data line.

In another embodiment, the present disclosure provides a device that includes an inter-integrated circuit (I2C) transmitter and an I2C receiver. The I2C transmitter includes a driver coupled to an I2C data line, and a pre-driver coupled to a variable first supply voltage, a second supply voltage, and a reference voltage. The pre-driver is configured to output a control signal to a control terminal of the driver. The I2C receiver includes a first stage coupled to the I2C data line, the variable first supply voltage, the second supply voltage, and the reference voltage.

In yet another embodiment, the present disclosure provides a method that includes: supplying a variable first supply voltage, a second supply voltage, and a stable reference voltage to a pre-driver of an inter-integrated circuit (I2C) transmitter; controlling, by the pre-driver, a driver of the I2C transmitter with a control signal having a voltage level of one of the second supply voltage and the stable reference voltage; and supplying the variable first supply voltage, the second supply voltage, and the stable reference voltage to a first input stage of an I2C receiver.

DETAILED DESCRIPTION

The present disclosure provides inter-integrated circuit (I2C) transmitters, receivers, devices, and methods that utilize a stable reference voltage in addition to a variable first supply voltage and a second voltage, such as a ground voltage. These I2C transmitters and receivers may be part of a processor or other central processing unit in handheld or other electronic devices. These I2C transmitters and receivers assist in communication between various electronic components within an electronic device. These I2C transmitters and receivers will reduce power consumption and extend battery life of battery operated circuits in these electronic devices.

In certain applications, such as in battery operated circuits which operate in large ranges of supply voltages, a drive capability of an NMOS driver16in an I2C transmitter10or receiver50varies quadratically in relation to the supply voltage. For example, a drive current can vary from about 10 mA to about 72 mA when a supply voltage VDDE ranges between about 1.62V and 3.78V. This variation in the drive current extends outside of I2C specifications, and then limits the speed of the I2C transmitter. For example, with such a wide range of drive current, the I2C transmitter is incapable of operating at 1 Mbps speed.FIG. 1is a schematic diagram illustrating an I2C transmitter10that includes the NMOS driver16that is coupled between the unregulated supply voltage VDDE and ground GND, the drive signal ND is provided at either the supply voltage VDDE or the ground GND voltage levels. The I2C transmitter10includes a multiplexer and level shifter12and a pre-driver14, which are each coupled to VDDE. The transmitter10includes an input terminal A that receives a core signal from other components within the chip that includes the I2C transmitter10. The core signal is any internal chip level signal that is to be communicated to the outside environment, i.e., to the I2C data line20via an input/output terminal10.

The core signal provided at the input terminal A may include multiple signals. For example, the core signal may include the chip level data signal that is to be communicated to the I2C data line20, and may further include control signals, such as an enable signal or the like, for control of the circuitry in the transmitter10. The multiplexer and level shifter12receive the signals from the input terminal A, and select and level shift the signals to provide a control signal15to the pre-driver14that is used to generate a drive signal for driving the driver16to output data to the I2C data line20.

The pre-driver14receives the control signal and outputs a drive signal ND based on the control signal to control the driver16. The pre-driver14may include a plurality of elements, such as logic stages, and a final stage or an output stage is coupled to an unregulated supply voltage VDDE. The pre-driver14may include a logic element such as a buffer or an inverter that outputs the drive signal ND to control the driver16.

FIG. 2is a schematic diagram illustrating an I2C receiver50that experiences similar problems as the I2C transmitter10ofFIG. 1, due to variations in the supply voltage VDDE.

The I2C receiver50includes an input terminal10coupled to the I2C data line20. A first stage52of the I2C receiver50, which may be, for example, a Schimitt trigger or an inverter, is coupled to the input terminal10. Additional circuitry, such as an I2C filter54and a level shifter56is coupled between the first stage52and an output terminal ZI.

In the I2C communication protocol, the bus supply VBUS can be uncorrelated to the IO supply, i.e., VDDE. This can lead to heavy current consumption in the first stage52of the I2C receiver50, particularly, when the uncorrelated bus supply VBUS is at a voltage level that is substantially lower than the IO supply voltage VDDE. For example, in the case where the supply voltage VDDE ranges between about 1.62V and 3.78V and the bus supply voltage VBUS is 1.62V, a high short circuit current is present in the first stage52when the supply voltage VDDE is at 3.78V. This results in high current consumption in the I2C receiver50, which reduces the battery life.

One approach to alleviating the problems of the I2C transmitter10ofFIG. 1and the I2C receiver50ofFIG. 2is to downgrade the mode of communication, e.g., from the Fast+ mode (1 Mbps) to the Fast mode (400 kbps) to meet the specifications of the transmitter10. However, this reduction in speed reduces the efficiency of communication, which is undesirable. Another approach is to provide a set of bits to the IO that indicate various regions of voltage ranges of the IO supply. However, in such a case, the IO needs to be designed to meet specifications in a variety of different bands of supply voltages, which complicates the design process and requires additional circuitry and components. This approach results in an increased circuit area, as different parts of circuits may need to be multiplexed to work at a particular voltage band. Yet another approach may be to restrict the VBUS supply voltage to a narrow band of potential, and then to provide this info to the IO via selection bits. However, this approach requires additional IO pads on the chip in order to carry this information to the chip.

In accordance with various embodiments of the present disclosure, one or more of the drawbacks described above with respect to the I2C transmitter10ofFIG. 1and the I2C receiver50ofFIG. 2are reduced or eliminated by providing a stable reference voltage VREF to drive a pre-driver114of the transmitter and a first stage152of the receiver150. The I2C transmitter and receiver can achieve operating speeds that improve operation of the processor or chip within which the I2C transmitter is positioned. For example, the I2C transmitter10can operate in the Fast+ mode, in which a communication speed of 1 Mbps is achieved.

By utilizing a stable reference voltage in the transmitter10, the transmitter drive spread is decreased, and this reduced spread allows the transmitter10to meet the tighter specifications (e.g., Loopdelay) of the Fast+ mode. Accordingly, the I2C transmitter is capable of operating in a Fast+ mode of communication at all times.

Similarly, in the I2C receiver, the stable reference voltage is used to drive the first stage of the receiver. The stable reference voltage will be lower than a variable voltage of the I2C data line, as such a short circuit current is prevented in the first stage of the receiver, thereby decreasing power consumption and extending battery life.

The I2C transmitter and the I2C receiver may be on the same chip, with one of the transmitter or receiver being enabled at a time, i.e., via bidirectional communication. One or both of the I2C transmitter and the I2C receiver may be coupled to the stable reference voltage. The transmitter and receiver communicate with other chips on a same printed circuit board or within a same electronic device, such as a smart phone, a laptop, a notebook, a multimedia device, a digital audio player, a camera, a game console, a wearable computing device, an appliance, or the like.

FIG. 3illustrates an I2C transmitter110having a pre-driver114coupled to a stable supply voltage Vref, in accordance with one or more embodiments of the present disclosure. The transmitter110may be similar to the transmitter10shown inFIG. 1, with the differences as will be explained below. The transmitter110includes an input terminal A that receives a core signal that is to be communicated to the I2C data line20via an input/output terminal10.

The core signal provided at the input terminal A may include multiple signals. For example, the core signal may include the chip level data signal that is to be communicated to the I2C data line20, and may further include control signals, such as an enable signal or the like, for control of the circuitry in the transmitter110. The multiplexer and level shifter112receives the signals and select and process the signals, e.g., by level shifting the received data signal, and provide the signals to the pre-driver114. The multiplexer and level shifter112may be coupled to a first supply voltage VDDE and to a second supply voltage GND. The first supply voltage VDDE may be a variable supply voltage. For example, the supply voltage VDDE may vary from about 1.62V to about 3.78V, however the range of the voltages provided by the supply voltage VDDE are not limited thereto. For example, the supply voltage VDDE may be output within any range of voltages for operation of various battery operated circuits. The second supply voltage GND may be, for example, a low voltage or a ground voltage.

The pre-driver114receives a control signal and outputs a drive signal ND based on the control signal115from the MUX and level shifter112. The pre-driver controls a driver116, such as an NMOS driver with a control signal ND. The control signal ND is coupled to a gate of the NMOS transistor in the NMOS driver. Further details of the pre-driver114are shown inFIG. 4.

The driver116is connected as an open-drain driver that is provided as an NMOS transistor having a gate terminal coupled to the output of the pre-driver114and conduction terminals coupled between the input/output terminal10and the second supply voltage GND. Open-drain refers to a type of output which can either pull the I2C data line20down to a low voltage (e.g., GND), or “release” the I2C data line20so it may be pulled up to a bus voltage VBUS by a pull-up resistor R.

Accordingly, the input/output terminal10is coupled to the second supply voltage GND when a high voltage (e.g., logic 1) is applied to the gate of the driver116, thereby pulling down the voltage on the I2C data line20to the second supply voltage GND level. When a low voltage (e.g., logic 0) is applied to the gate of the driver116, the NMOS transistor is off, and the I2C data line20is released by the driver116thereby allowing the pull-up resistor R to raise the voltage on the I2C data line20to a high level.

As shown inFIG. 4, the pre-driver114may include a plurality of elements, such as a plurality of transistors that are connected as one or more logic stages. The pre-driver114is coupled to the first supply voltage VDDE, which is a variable supply voltage and to the second supply voltage GND. That is, one or more of the elements in the pre-driver114are coupled between the variable first supply voltage VDDE and the second supply voltage GND. However, a last stage117or an output stage of the pre-driver114is coupled to a stable supply voltage Vref instead of the variable first supply voltage VDDE.

In particular, the pre-driver114may include a first pair of transistors121,122that are coupled between the variable first supply voltage VDDE and the second supply voltage GND. Each of the transistors121,122of the first pair of transistors have a respective gate terminal coupled to an input IN, to which the control signal115is supplied. A second pair of transistors123,124are similarly coupled between the variable first supply voltage VDDE and the second supply voltage GND. Each of the transistors123,124of the second pair of transistors have a respective gate terminal coupled to an output of the first pair of transistors121,122.

The pre-driver114may include a logic element such as a buffer or an inverter as the last stage117that outputs the drive signal ND to control the driver116. The last stage117of the pre-driver114may include a third pair of transistors125,126, which are coupled between the stable supply voltage Vref and the second supply voltage GND. Since the last stage117of the pre-driver114is coupled between the stable supply voltage Vref and the second supply voltage GND, the drive signal ND is provided at either the stable supply voltage Vref or the second supply voltage, e.g., ground GND voltage levels. Thus, in contrast to the pre-driver14of the I2C transmitter10shown inFIG. 1, which outputs the drive signal ND with a voltage that swings between the variable first supply voltage VDDE and the second supply voltage GND, the pre-driver114outputs the drive signal ND with a voltage that swings between the stable supply voltage Vref and the second supply voltage GND. Because the stable supply voltage Vref is a constant voltage, there is no variation in the voltage level provided by the stable supply voltage Vref, and thus the drive signal ND has one of two possible values: the voltage level of the second supply voltage GND (e.g., 0V), or the voltage provided by the stable supply voltage Vref.

As shown inFIG. 3, by providing a stable supply voltage Vref to the last stage117of the pre-driver114, the drive spread of the driver116is not dependent on a variable supply voltage (e.g., the variable first supply voltage VDDE, as inFIG. 1). Indeed, the spread of the drive current Idc in the I2C transmitter110is within a range of about 10 mA to about 22 mA in the I2C transmitter110ofFIG. 3, which is significantly reduced with respect to the I2C transmitter10ofFIG. 1, which varies from about 10 mA to about 72 mA when the supply voltage VDDE ranges between about 1.62V and 3.78V.

While it is possible to supply the stable supply voltage Vref to all of the stages of the pre-driver114, the stable supply voltage may only be provided at last stage117of pre-driver114, since that is the stage that outputs the drive signal ND at a level between 0 and Vref. Accordingly, in one or more embodiments the stable supply voltage Vref may be provided to all of the stages of the pre-driver114, while in other embodiments the stable supply voltage Vref is supplied only to the last stage117of the pre-driver114.

FIG. 5illustrates an I2C receiver150having a first stage152coupled to a stable supply voltage Vref, in accordance with one or more embodiments of the present disclosure.

The I2C receiver150may be similar to the receiver50shown inFIG. 2, with the differences as will be explained below. The receiver150includes an input terminal10that is coupled to the I2C data line20and receives a data signal communicated from the I2C data line20.

The first stage152of the I2C receiver150is coupled to the input terminal10. The first stage152may include a plurality of elements, such as a plurality of transistors that are connected as one or more logic stages. For example, the first stage152of the receiver150may be, for example, an inverter or an inverting Schmitt trigger (as shown). The I2C receiver150may further include additional circuitry, such as an I2C filter154and a level shifter156coupled between the first stage152and an output terminal ZI.

Various circuitry included in the I2C receiver150, such as the I2C filter154and the level shifter156, may be coupled between the variable first supply voltage VDDE and the second supply voltage GND. However, the first stage152of the I2C receiver150is coupled to the stable supply voltage Vref instead of, or in addition to, the variable first supply voltage VDDE. The first stage152of the I2C receiver150may also be coupled to the variable first supply voltage VDDE, for example, to drive one or more transistors that are between an input element of the first stage152and an output element of the first stage152. For example, the first stage152may be an inverting Schmitt trigger that includes an input transistor and one or more additional transistors. In such a case, the input transistor is coupled to the stable supply voltage Vref, while the additional transistors may be coupled to the variable first supply voltage VDDE.

The stable supply voltage Vref may be selected such that it is always at a voltage level that is lower than the bus supply voltage VBUS. The bus supply voltage VBUS may be a variable voltage. For example, the bus supply voltage VBUS may be from about 1.62V to about 3.6V in one or more embodiments. In such a case, the stable supply voltage Vref may be selected to be a steady voltage that is less than 1.62V, such that the stable supply voltage Vref is less than the bus supply voltage VBUS regardless of the variations of the bus supply voltage VBUS.

As discussed above with respect to the I2C receiver50shown inFIG. 2, a high short circuit current may be present in the first stage52when the supply voltage VDDE is higher than the uncorrelated bus supply voltage VBUS. However, in the I2C receiver150shown inFIG. 5, the first stage152is coupled between the stable supply voltage Vref and the second supply voltage GND. Since the stable supply voltage Vref may be selected to always be lower than the bus supply voltage VBUS, the short circuit current may be prevented in the first stage152regardless of the values of the variable first supply voltage VDDE and the bus supply voltage VBUS. Thus, in contrast to the I2C receiver50ofFIG. 2, the first stage152of the I2C receiver150ofFIG. 5does not consume current even when the bus supply voltage VBUS is at its lowest value (e.g., 1.62V), since the stable reference voltage Vref is equal to or less than the bus supply voltage VBUS.

FIG. 6is a circuit diagram illustrating a reference voltage generator200, in accordance with one or more embodiments of the present disclosure. The reference voltage generator200may be, for example, a low-dropout (LDO) regulator that generates the reference voltage Vref.

As shown inFIG. 6, the reference voltage generator200includes a differential amplifier202, a transistor204, and first and second resistors206,208. The differential amplifier202receives a steady reference voltage, such as a bandgap reference voltage, at a non-inverting terminal. The differential amplifier202has an inverting terminal coupled to a node between the first resistor206and the second resistor208. An output of the differential amplifier202is coupled to the gate of the transistor204, which has conduction terminals coupled between the variable first supply voltage VDDE and an output node that is coupled to the first resistor206.

The inverting terminal of the differential amplifier202monitors the output voltage Vref through a voltage divider formed by the first and second resistors206,208. If the output voltage Vref rises or falls relative to the steady reference voltage, then the output of the differential amplifier202changes to drive the transistor204to maintain a constant output voltage Vref.

The reference voltage generator200may be designed to output the stable supply voltage Vref at a voltage level that is less than the lowest value of the bus supply voltage VBUS. For example, if the bus supply voltage VBUS varies from about 1.62V to about 3.6V, in one or more embodiments, then the reference voltage generator200may be designed to output the stable supply voltage Vref at a value of about 1.35V.

FIG. 7is a schematic diagram illustrating an integrated circuit (IC)300having an I2C transmitter and an I2C receiver coupled to a regulated supply voltage, in accordance with one or more embodiments of the present disclosure.

The IC300includes the I2C transmitter110ofFIG. 3and the I2C receiver150ofFIG. 5, each of which is coupled to the I2C data line20via respective input/output terminals10. The IC300may further include a reference voltage generator200, for example as shown inFIG. 6. The reference voltage generator200may be included in the IC300, as shown inFIG. 7. That is, the reference voltage generator200may be formed on a same semiconductor die or on a same chip as the IC300. The reference voltage generator200generates the stable reference voltage Vref, which is supplied to the I2C receiver150and to the I2C transmitter110.

FIG. 8is a schematic diagram illustrating a device400that includes a plurality of integrated circuits communicatively coupled to one another by the I2C data line20.

The plurality of integrated circuits IC1to ICn may be connected to an I2C bus or I2C data line20, which facilitates communication between the ICs. The device400may be any battery powered electronic device, including, for example, a smart phone, a laptop, a notebook, a multimedia device, a digital audio player, a camera, a game console, a wearable computing device, an appliance, or the like. The ICs may be any integrated circuits included in such devices, including, for example, integrated circuits for display drivers, LED controllers, bus controllers, memory, data converters, temperature sensors, image sensors, and the like.

One or more of the integrated circuits IC1to ICn may include a reference voltage generator200, for example, as shown in the integrated circuit300ofFIG. 7. In one or more embodiments, each of the integrated circuits IC1to ICn may include a reference voltage generator200for supplying a stable reference voltage Vref to the I2C transmitter110and the I2C receiver150within each respective integrated circuit. Alternatively, the device400may include a separate reference voltage generator200which supplies the stable reference voltage Vref to each of the integrated circuits IC1to ICn.

As shown and described herein, the stable reference voltage Vref may be supplied to only a last stage of a pre-driver and to a first stage of the receiver, while other circuitry in the I2C transmitter and the I2C receiver is supplied with the variable first supply voltage VDDE. This is because providing a stable reference voltage to all of the circuitry within the I2C transmitter and receiver would require a reference voltage generator that is heavily loaded. In such a case, the loading on the reference voltage generator would need to be accounted for in the design of the circuit, which would result in a more expensive design and a larger circuit

The I2C transmitters and I2C receivers described herein provide several advantages over prior designs. For example, the I2C transmitter described herein is capable of operation in the I2C Fast+ mode at all times. Further, there is no short circuit current consumption in the first stage of the I2C receiver. Additionally, a single I2C receiver can work with multiple boards, having different supplies, without the need of one or more additional supply selection pins at the chip level. That is, supply selection pins that are used in conventional circuits to inform the receiver of the level of the bus supply voltage VBUS and/or the level of VDDE are not needed, since the receiver input stage is regulated by the stable reference voltage Vref. Moreover, there is no need to regulate the whole VDDE supply, which might be feeding many blocks, since the reference voltage generation can be internal to the IO (i.e., the I2C transmitter or receiver). An inexpensive global reference generator could be used to generate the stable reference voltage Vref in one or more embodiments, with Vref being supplied to a relative low number of branches. In another embodiment, the reference voltage generator may be a low-dropout (LDO) regulator that generates the reference voltage Vref and that supplies it to a plurality of IOs, e.g., to share the reference voltage Vref to many such instances of IO in an IO-ring. This provides the advantage that one does not need to design a global reference generator for the whole VDDE, which might be very costly as VDDE is feeding many circuits.