Balun with structural enhancements

A balun including a pair of metal coil structures and an intervening dielectric layer having a thickness that is selected in response an operating frequency of the balun. The thickness of the dielectric layer may be used to tune the balun and enhance its self-inductance at its operating frequency. In addition, a balun with a pair of metal coil structures formed with an asymmetry that is selected to minimize an amplitude error in its output signal. A balun according the present teachings may also include an asymmetry in the positioning of its output terminals. The positioning of the output terminals of a balun may be adjusted to minimize phase errors at its output signal.

BACKGROUND

A balun may be employed in a variety of electronic circuits to transform a single-ended input signal into a balanced output signal. A single-ended input signal may be defined as an electrical signal that is carried on two signal lines with one of the signal lines tied to ground. A balanced output signal may be defined as an electrical signal that is carried on three signal lines with one of the signal lines tied to ground and the remaining two signal lines carrying electrical signals of equal amplitude but opposite phase.

A balun may be implemented by forming a pair of metal coil structures in relatively close proximity to one another. For example, a balun may include a primary metal coil structure formed adjacent to a secondary coil structure with an intervening dielectric that separates the primary and secondary metal coil structures. A single-ended input signal applied to the primary metal coil structure may be used to induce an image electrical signal in the secondary metal coil structure and provide a balance output signal from the secondary metal coil structure.

It may be desirable to form a balun so that the self-inductance of its metal coil structures is maximized. For example, a balun having metal coil structures with a relatively low amount of self-inductance may place an undesirable load on an electronic circuit. In addition, metal coil structures formed on an integrated circuit die may suffer from a relatively low amount of self-inductance as a consequence of the relatively limited space in which to form a balun.

In addition, the metal coil structures in prior baluns may cause amplitude and phase errors in its output signal. For example, the asymmetry in the input signal to a balun, i.e. one input terminal connected to ground and the other to an input signal, may cause undesirable differences in the amplitudes and phases of in the output signals on its two output terminals.

SUMMARY OF THE INVENTION

A balun is disclosed that includes a pair of metal coil structures and an intervening dielectric layer having a thickness that is selected in response an operating frequency of the balun. The thickness of the dielectric layer may be used to tune the balun and enhance its self-inductance at its operating frequency.

In addition, a balun is disclosed with a pair of metal coil structures formed with an asymmetry that is selected to minimize an amplitude error in its output signal. A balun according the present teachings may also include an asymmetry in the positioning of its output terminals. The positioning of the output terminals of a balun may be adjusted to minimize phase errors at its output signal.

Other features and advantages of the present invention will be apparent from the detailed description that follows.

DETAILED DESCRIPTION

FIG. 1is a cross-sectional view of a balun10according to the present teachings. The balun10includes pair of metal coil structures12and16that are separated by a dielectric layer14. The metal coil structures12and16and the intervening dielectric layer14are in one embodiment formed on a dielectric layer18over a substrate20, e.g. an integrated circuit die.

The physical arrangement of the coil structures12and16and the intervening dielectric layer14causes a parasitic capacitance of Cx in the balun10. The value of Cx is a function of the physical characteristics of the metal coil structures12and16and a thickness d of the dielectric layer14. The present techniques include adjusting the thickness d of the dielectric layer14to tune the balun10to an operating frequency of interest for the balun10.

FIG. 2shows a method for designing the balun10according to the present techniques. At step30, a physical layout for the metal coil structures12and16is determined. Determining the physical layout of the metal coil structures12and16may include determining the number of turns in each metal coil structure12and16and determining the size of the turns.

Step30may be performed in response to a variety of application-specific criteria for the balun10using known design techniques. The application-specific criteria for the balun10may include its overall physical dimensions and its lowest operating frequency of interest. For example, if the balun10is to be contained on an integrated circuit die then its overall physical dimensions may restrict the number and size of the turns in the metal coil structures12and16.

At step32, the thickness d of the dielectric layer14is adjusted to tune the balun10. The thickness d of the dielectric layer14may adjusted to adjust the value of the parasitic capacitance Cx in the balun10to a desired value. For example, the thickness d of the dielectric layer14may be increased to decrease the value of the parasitic capacitance Cx in the balun10. Conversely, the thickness d of the dielectric layer14may be decreased to increase the value of the parasitic capacitance Cx in the balun10.

The value of the parasitic capacitance Cx may be used to tune a resonant frequency of the balun10to a lowest frequency of interest for the balun10. The tuning of the resonant frequency of the balun10to a lowest frequency of interest may be used to minimize the loss of the balun10at the frequency of interest. Known simulation techniques may be used to determine the resonant frequency of the balun10in response to different values of the parasitic capacitance Cx yielded by changes to the thickness d of the dielectric layer14.

FIG. 3shows a top view of a physical layout for the balun10that is selected to minimize amplitude and phase errors in its output signal. The metal coil structure12is shown over the metal coil structure16. The metal coil structure12includes a half-structure40and a half-structure42. Similarly, the metal coil structure16includes a half-structure50and a half-structure52.

The half-structures50and52include a pair of pads60and62, respectively, that provide an input port for the balun10. The pad62may be connected to a ground plane of an integrated circuit that holds the balun10and the pad60may be connected to a bond wire that carries an input signal to the balun10.

The half-structures40and42include a pair of pads74and76, respectively, and a pair of output lines70and72, respectively, that provide an output port for the balun10. The pads74and76may be connected to a ground plane on an integrated circuit that holds the balun10and the lines70and72may be connected to an external circuit that receives a balanced output signal from the balun10.

The balun10is formed with an asymmetry in the half-structures40and42and50and52so as to correct for amplitude errors in its output signal. The half-structures40and50are larger than the half-structures42and52by an amount that is selected to minimize amplitude errors in the output signal at the output lines70and72. The half-structures40and50have an x dimension of d4and a y-dimension of d3and the half-structures42and52have an x dimension of d2and a y-dimension of d1. In one embodiment, d2=d4and d1>d3and the amount by which d1is greater than d3is selected to minimize amplitude errors in the output signal at the output lines70and72. The value of d1−d3may be determined by experimentation or by simulation of the balun10in a system under design.

The balun10is formed with an asymmetry in the positions of the output lines70and72in the y-direction so as to correct for phase errors in its output signal. In one embodiment, the output lines70and72are offset in the positive y-direction by a distance d5from a midpoint located a distance d6from each extreme y edge of the balun10. The position of the output lines70and72contrasts with prior art baluns that typically position output lines equidistant from the edges. The distance d5is selected to minimize phase errors in an output signal at the of a balun lines70-72. The value of d5may be determined by experimentation or by simulation of the balun10in a system under design.

In one embodiment, the substrate20is an integrated circuit substrate, e.g. gallium arsenide, and the metal coil structures12and16are formed using photolithography. The balun10has an operating frequency of 2110-2170 MHz. The metal coil structures12and16are formed of gold and the dielectric layer14is BCB. The dimensions d6=350 microns and d2=600 microns. A resonant frequency of 2000 MHz for the balun10in this embodiment is achieved with the thickness d=1 micron for the dielectric layer14.

A 2.5 dimension field solver may be used to determine the electrical characteristics of the metal coil structures12and16as well as the electrical performance of the balun10in response to changes in the structures of the balun10as described above. For example, a trial and error method may be employed to adjust the thickness d of the dielectric layer14while the 2.5 dimension field solver is used to evaluate the electrical characteristics of the balun10for each trial thickness d until a suitable value for d is found. Similarly, a trial and error method may be employed to adjust the asymmetry of the metal coil structures12and16and/or the asymmetry in positioning the output lines70and72while the 2.5 dimension field solver is used to evaluate the electrical characteristics of each trial until a suitable design is found.

The foregoing detailed description of the present invention is provided for the purposes of illustration and is not intended to be exhaustive or to limit the invention to the precise embodiment disclosed. Accordingly, the scope of the present invention is defined by the appended claims.