Electrically programmable device with embedded EEPROM and method for making thereof

An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region.

CROSS-REFERENCES TO RELATED APPLICATIONS

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BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a programmable device with embedded electrically-erasable programmable read-only memory (EEPROM) and method for making thereof. Merely by way of example, the invention has been applied to one-time programmable (OTP) device with embedded EEPROM. But it would be recognized that the invention has a much broader range of applicability.

Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.

Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Moreover, the output of the fabrication facility also depends on the complexity of the fabrication process. For example, additional masking steps and/or additional ion implantation steps may significantly reduce the throughput and increase the cost.

Fabrication of custom integrated circuits using chip foundry services has evolved over the years. Fabless chip companies often design the custom integrated circuits. Such custom integrated circuits require a set of custom masks commonly called “reticles” to be manufactured. A chip foundry company called Semiconductor International Manufacturing Company (SMIC) of Shanghai, China is an example of a chip company that performs foundry services. Although fabless chip companies and foundry services have increased through the years, many limitations still exist. For example, it is difficult to efficiently make erasable programmable read-only memory (EPROM) with embedded EEPROM. These and other limitations are described throughout the present specification and more particularly below.

From the above, it is seen that an improved semiconductor device and method for making thereof is desired.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a programmable device with embedded electrically-erasable programmable read-only memory (EEPROM) and method for making thereof. Merely by way of example, the invention has been applied to one-time programmable (OTP) device with embedded EEPROM. But it would be recognized that the invention has a much broader range of applicability.

In a specific embodiment, the invention provides a method for making a semiconductor device. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region. Moreover, the method includes forming a first gate in the first device region and a second gate and a third gate in the second device region, and depositing a first dielectric layer on the first gate, the second gate, the third gate, and the first gate oxide layer. Also, the method includes etching a first part and a second part of the first dielectric layer and a first part of the first gate oxide layer in the first device region. The first part of the first dielectric layer is on the first gate, and the second part of the first dielectric layer is on the first part of the first gate oxide layer. Additionally, the method includes growing an inter-gate oxide layer and a second gate oxide layer in the first device region. The inter-gate oxide layer is on the first gate, and the second gate oxide layer is on the substrate. Moreover, the method includes forming a fourth gate on at least the second oxide layer, the inter-gate oxide layer, and the first dielectric layer in the first device region, forming a fifth gate on the first dielectric layer in the second device region, and implanting a second plurality of ions to form a plurality of source regions and a plurality of drain regions. The etching a first part and a second part of the first dielectric layer and a first part of the first gate oxide layer in the first device region is free from removing any part of the first dielectric layer in the second device region.

According to another embodiment, a method for making a semiconductor device includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region. Moreover, the method includes forming a first gate in the first device region and a second gate and a third gate in the second device region, and depositing a first dielectric layer on the first gate, the second gate, the third gate, and the first gate oxide layer. Also, the method includes etching a first part and a second part of the first dielectric layer and a first part of the first gate oxide layer in the first device region. The first part of the first dielectric layer is on the first gate, and the second part of the first dielectric layer is on the first part of the first gate oxide layer. Additionally, the method includes growing an inter-gate oxide layer and a second gate oxide layer in the first device region, the inter-gate oxide layer being on the first gate, the second gate oxide layer being on the substrate, and forming a fourth gate on at least the second oxide layer, the inter-gate oxide layer, and the first dielectric layer in the first device region. Moreover, the method includes forming a fifth gate on the first dielectric layer in the second device region, and implanting a second plurality of ions to form a plurality of source regions and a plurality of drain regions. The inter-gate oxide layer is associated with a thickness ranging from 150 Å to 250 Å, and the forming a fourth gate includes using the first dielectric layer as an etch stopping layer.

According to yet another embodiment, a semiconductor device with embedded EEPROM devices includes a one-time programmable device on a silicon wafer and an electrically erasable programmable device on the silicon wafer. The one-time programmable device includes a first gate oxide layer and a second gate oxide layer. The second gate oxide layer is thinner than the first gate oxide layer. Additionally, the one-time programmable device includes a first gate on the first gate oxide layer, a first dielectric layer on the first gate, an inter-gate oxide layer on the first gate, and a second gate on the first dielectric layer, the inter-gate oxide layer, and the second gate oxide layer. The inter-gate oxide is adapted to shape the first gate for programming the one-time programmable device. Moreover, the electrically erasable programmable device has a tunnel oxide for programming and erasing in the electrically erasable programmable device.

Many benefits are achieved by way of the present invention over conventional techniques. For example, the present technique provides a process for making programmable devices which is fully compatible with a process for making EEPROM devices. In some embodiments, the method provides an easy to use process that relies upon conventional technology. Additionally, the method often does not require any substantial modifications to conventional equipment and processes. Depending upon the embodiment, one or more of these benefits may be achieved. These and other benefits will be described in more throughout the present specification and more particularly below.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a programmable device with embedded electrically-erasable programmable read-only memory (EEPROM) and method for making thereof. Merely by way of example, the invention has been applied to one-time programmable (OTP) device with embedded EEPROM. But it would be recognized that the invention has a much broader range of applicability.

FIG. 1is a simplified method for forming a programmable device according to an embodiment of the present invention. The method100includes at least the following processes:1. Process110for ion implantation and gate oxide formation;2. Process115for photolithography and ion implantation for threshold adjustment;3. Process120for forming tunneling oxide;4. Process125for gate and oxide-nitride-oxide formation;5. Process130for oxide-nitride-oxide photolithography and threshold adjustment;6. Process135for oxide-nitride-oxide etching;7. Process140for gate and inter-gate oxide formation;8. Process145for polysilicon deposition;9. Process150for control gate photolithography;10. Process155for control gate etching;11. Process160for gate photolithography;12. Process165for gate etching;13. Process170for light doped drain region and lightly doped source region formation;14. Process175for spacer formation;15. Process180for drain and source formation.

The above sequence of processes provides a method according to an embodiment of the present invention. Other alternatives can also be provided where processes are added, one or more processes are removed, or one or more processes are provided in a different sequence without departing from the scope of the claims herein. Future details of the present invention can be found throughout the present specification and more particularly below.

In a specific embodiment, the present method includes provide a semiconductor substrate. The semiconductor substrate is a single crystal silicon wafer in a specific embodiment. Other semiconductor substrates such as silicon on insulator (commonly called SOI), silicon germanium (SiGe) may also be used, depending on the application. Of course there can be other variations, modifications, and alternatives.

FIGS. 2-17are simplified cross-sectional diagrams illustrating a method for forming a one-time programmable (OTP) device with embedded EEPROM according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. In each ofFIGS. 2-17, two regions of the device area are shown simultaneously, i.e., the e-OTP device region and the e-EEPROM device region. A method for simultaneously forming a OTP device and an EEPROM device is discussed below.

At the process110, an ion implantation is performed and gate oxide is formed.FIG. 2illustrates a simplified process110for ion implantation and gate oxide formation overlying the semiconductor substrate according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 2, gate oxide layers210and212can be formed by an oxide growth process. Gate oxide layer210is formed in the OTP region, and gate oxide layer212is formed in the EEPROM region. For example, the gate oxide layers210and212can provide a high breakdown voltage. As another example, the gate oxide layers210and212have a thickness ranging from 200 Å to 300 Å. As yet another example, the gate oxide layers210and212overly on a substrate such as a single silicon wafer. In a specific embodiment, an ion implantation process is performed to form diffusion regions220,222, and224. For example, the ion implantation can use implant species such as arsenic in certain embodiments. The implant energy may range from 25 keV to 80 keV, and the implant dose may range from 1E14 to 3E15 per cm2. As another example, the diffusion region220is used for electron tunneling during operation of a programmable device, and the diffusion regions222and224are used for electron tunneling during operation of the EEPROM.

At the process115, photolithography and ion implantation are performed for adjusting threshold voltage.FIG. 3is a simplified process115for photolithography and ion implantation according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 3, a photoresist layer230is formed by a photolithography process, and masks the diffusion regions222and224. With the photoresist layer230, an ion implantation process is performed to form the diffusion regions240and242, which is used to adjust threshold voltages for the programmable device and the EEPROM respectively. For example, the ion implantation process can use B ions or BF ions for a N-channel device. The boron implant energy may range from about 5 keV to about 25 keV, which is equivalent to a BF2implant energy of about 20 keV to about 100 keV. The implant dose may range from about 5E12 per cm2to about 1E13 per cm2.

At the process120, tunneling oxide is formed.FIG. 4is a simplified process120for tunneling oxide formation according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 4, photoresist layers250,252, and254are formed by a photolithography process. A wet etching process is performed to remove a portion of the gate oxide layer212that is not covered by the photoresist. Subsequently, a tunneling oxide layer260is grown to a thickness, which for example ranges from 50 Å to 150 Å.

At the process125, gates and oxide-nitride-oxide layers are formed.FIG. 5is a simplified process125for gate and oxide-nitride-oxide formation according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 5, gates270,272, and a floating gate274are formed by a polysilicon deposition and etching process. For example, the thickness of these gates ranges from about 70 nm to about 300 nm. A part of the floating gate274is located on the tunneling oxide layer260. Additionally, a conformal oxide-nitride-oxide (ONO) layers280and282are formed on the gates270,272and274, and on the gate oxide layers210and212. In one embodiment, each oxide-nitride-oxide layer includes a first oxide layer, a nitride layer, and a second oxide layer. For example, the first oxide layer, the nitride layer, and the second oxide layer each have a thickness ranging from 30 Å to 150 Å.

At the process130, oxide-nitride-oxide photolithography and threshold adjustment is performed.FIG. 6is a simplified process130for oxide-nitride-oxide photolithography and threshold adjustment according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 6, photoresist layers290and292are formed by a photolithography process. In one embodiment, the photoresist layer290covers only part of the oxide-nitride-oxide layer280, but in contrast the photoresist layer292covers the entire oxide-nitride-oxide layer282. An ion implantation process is performed to form a diffusion region300under the gate oxide layer210and not covered by either the photoresist layer290or the floating gate270. For example, for a N channel device, the ion implantation process can use boron ion species such as B ions, BF2ions, or In ions. The implant energy may range from about 5 keV to about 100 keV, and the implant dose may range from about 1E12 per cm2to about 2E14 per cm2.

At the process135, oxide-nitride-oxide and gate oxide is etched.FIG. 7is a simplified process135for etching oxide-nitride-oxide and gate oxide according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 7, a substantially anisotropic etch is performed in the vertical direction in the OTP device region and removes parts of the oxide-nitride-oxide layer280and part of the gate oxide layer210that are exposed to the vertical etch.

As shown, a first part and a second part of the oxide-nitride-oxide layer280is removed, leaving a vertical sidewall of the oxide-nitride-oxide layer280on a side of gate270. Removing the first part of the oxide-nitride-oxide layer280exposes a top portion of the gate region270near the sidewall280. Removing the second part of the oxide-nitride-oxide layer280exposed an underlying portion of gate oxide layer210, which is also removed in the etch process.

InFIG. 7, the oxide-nitride-oxide layer282and the gate oxide layer212in the EEPROM device region are protected by the photoresist layer292and thus remain intact. For example, the anisotropic etch uses a dry etching process.

At the process140, gate and inter-gate oxide is formed.FIG. 8is a simplified process140for growing gate and inter-gate oxide according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 8, gate oxide layer310and inter-gate oxide layer320are grown in areas where the oxide-nitride-oxide layer280and the gate oxide layer210are removed respectively in the OTP device region at the process130. The oxide-nitride-oxide layers280and282, respectively prevent selectively regions from oxidation. For example, the gate oxide layer310has a thickness ranging from 50 Å to 150 Å, and the inter-gate oxide layer320has a thickness ranging from 150 Å to 250 Å. As another embodiment, the inter-gate oxide layer320has a thickness substantially equal to 210 Å. In one embodiment, the gate oxide layer310is thinner than the gate oxide layer210, and has a breakdown voltage lower than that of the gate oxide layer210.

In a specific embodiment, the formation of the inter-gate oxide layer320can cause a sharp corner to be formed at a corner of the gate270. This sharp corner can be used advantageously to lower the voltage required to program the OTP device.

At the process145, polysilicon is deposited.FIG. 9is a simplified process145for polysilicon deposition according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 9, polysilicon layers330and332are formed by a deposition process. The polysilicon layers330and332each have a thickness ranging from about 70 nm to about 300 nm.

At the process150, the control gate photolithography is performed.FIG. 10is a simplified process150for control gate photolithography according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 10, a photolithography process is performed to form photoresist layers340and342as parts of the structures410,420,510and520. The structure410corresponds to a structure400as shown inFIG. 9, and the structure420corresponds to another structure that is the same as the structure400but next to the structure400. The structure510corresponds to a structure500as shown inFIG. 9, and the structure520corresponds to another structure that is the same as the structure400but next to the structure500.

At the process155, an etching is performed to form control gates.FIG. 11is a simplified process155for control gate etching according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 11, an etching process is performed to remove parts of the polysilicon layers330and332that are not protected by the photoresist layer340or342or the oxide-nitride-oxide layer280or282. The oxide-nitride-oxide layers280and282serve as etch stops.

At the process160, gate photolithography is performed.FIG. 12is a simplified process160for gate photolithography according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 12, resist layers610,612, and614are formed by a photolithography process. At least portions of the polysilicon layer330and the gate oxide layer320are not covered by any resist layer.

At the process165, etching is performed to form gate structures.FIG. 13is a simplified process165for gate photolithography according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 13, an etching process is performed to remove parts of the polysilicon layer330and the gate oxide layer310that are not protected by the photoresist layer610,612or614, and form gates620and622.

At the process170, photolithography and ion implantation are performed to form lightly doped drain region and lightly doped source region.FIG. 14is a simplified process170for photolithography and ion implantation according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 14, resist layers630and632are formed by a photolithography process. At least portions of the gate oxide layer212are not covered by the photoresist layer630or632, the oxide-nitride-oxide layer282, or the gate272. Through these portions of the gate oxide layer212, an ion implantation process is performed to form lightly doped drains642. In one embodiment, the implantation uses phosphorus ions as implant species. The implant energy may range from about 50 keV to about 100 keV, and the implant dose may range from about 5E13 per cm2to about 4E14 per cm2.

At the process175, spacers are formed.FIG. 15is a simplified process175for spacer formation according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 15, spacers650and660are formed for gates270,272,274,620,622, and332. For example, the spacers each have a thickness ranging from about 50 nm to about 150 nm. In another example, the spacers can be made of a silicon oxide, silicon nitride, or a silicon oxide on silicon nitride on silicon oxide (commonly called an ONO) composite stack.

At the process180, an ion implantation is performed to form heavily doped sources and drains.FIG. 16shows a simplified process180for ion implantation according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG. 16. The ion implantation process is performed to form heavily doped drains and sources670and672. In one embodiment, the implantation uses arsenic ions as implant species. The implant energy may range from about 5 keV to about 70 keV, and the implant dose may range from about 1E15 per cm2to about 6E15 per cm2.

As discussed above and further emphasized here,FIGS. 1-16are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the method includes forming one or more interlayer dielectric (ILD) layers and performing other back-end-of-line processes after the process180.

FIG. 17is a simplified system for electrically programmable devices with embedded EEPROM devices according to an embodiment of the present invention. The device1700includes the following components:1. Electrically programmable devices1710and1712;2. EEPROM devices1720and1722.

The above electronic devices provide components for the system1700according to an embodiment of the present invention. Other alternatives can also be provided where certain electrically programmable devices and/or EEPROM devices are added, one or more of devices1710,1712,1720, and1722are removed, or one or more devices are arranged with different connections without departing from the scope of the claims herein. In one embodiment, the system1700is fabricated with the method100. In another embodiment, the devices1710and1712and the devices1720and1722are on the same silicon wafer.

As shown inFIG. 17, the devices1710and1712include a gate oxide layer1210. For example, the gate oxide layer1210has a high breakdown voltage. As another example, the gate oxide layer1210has a thickness ranging from 200 Å to 300 Å. Additionally, the devices1710and1712include a diffusion region1220. For example, the diffusion region1220has a dopant concentration ranging from about 1E18 per cm3to about 1E20 per cm3, and a depth ranging from about 0.2 um about 0.5 um. As another example, the diffusion region1220is used for electron tunneling during operation of the programmable devices. Moreover, the devices1710and1712include a diffusion region1240, which is used to adjust threshold voltages of the programmable devices. For example, the diffusion region1240has a dopant concentration ranging from about 1E16 per cm3to about 1E18 per cm3, and a depth ranging from about 0.3 um to about 0.6 um.

As shown inFIG. 17, the devices1710and1712includes gates1270. For example, the gates1270are made of polysilicon. As another example, the thickness for these gates ranges from 70 nm to 300 nm. Additionally, the devices1710and1712include an oxide-nitride-oxide layer1280on at least the gates1270. In one embodiment, each oxide-nitride-oxide layer1280includes a first oxide layer, a nitride layer, and a second oxide layer. For example, the first oxide layer, the nitride layer, and the second oxide layer each have a thickness ranging from 50 Å to 150 Å. Moreover, the devices1710and1712include a diffusion region1300under at least part of the gate oxide layer1210. For example, the diffusion region1300has a dopant concentration ranging from 1E16 per cm3to 1E18 per cm3, and a depth ranging from about 0.2 um to about 0.7 um. Also, the devices1710and1712include oxide layers1310and1320. For example, the gate oxide layer1310has a thickness ranging from 50 Å to 150 Å, and the inter-gate oxide layer1320has a thickness ranging from 150 Å to 250 Å. In one embodiment, the gate oxide layer1310is thinner than the gate oxide layer1210, and has a breakdown voltage lower than that of the gate oxide layer1210.

As shown inFIG. 17, the devices1710and1712include gates1620and1622. For example, these gates each can have a thickness ranging from 70 nm to 300 nm. Moreover, the devices1710and1712include spacers1650for gates1270,1620and1622. For example, the spacers each have a thickness ranging from 50 nm to 150 nm. In another example, the spacers can be made of silicon oxide or silicon nitride or a silicon oxide on silicon nitride on silicon oxide (commonly known as ONO) composite stack. Also, the devices1710and1712include heavily doped drains and/or sources1670. For example, the heavily doped drains and/or sources1670each can have a dopant concentration ranging from about 1E15 per cm3to about 6E15 per cm3, and a depth ranging from about 0.1 um to about 0.4 um. In one embodiment, the devices1710and1712also include other back end of line (BEOL) layers such as inter-layer dielectric (ILD) layer1670and metal layer1672, among others.

As shown inFIG. 17, the devices1720and1722include a gate oxide layer1220. For example, the gate oxide layer1220has a high breakdown voltage. As another example, the gate oxide layer1220has a thickness ranging from 200 Å to 300 Å. Additionally, the devices1720and1722include diffusion regions1222and1224. For example, the diffusion regions1222and1224each have a dopant concentration ranging from about 1E18 per cm3to about 1E18 per cm3, and a depth ranging from about 0.2 um to about 0.8 um. As another example, the diffusion regions1222and1224are used for electron tunneling during operation of the EEPROM devices. Moreover, the devices1720and1722include a diffusion region1242, which is used to adjust threshold voltages for the EEPROM devices. For example, the diffusion region1242has a dopant concentration ranging from about 5E15 per cm3to about 2E16 per cm3, and a depth ranging from 0.3 um to 0.8 um. Also, the devices1720and1722include a tunneling oxide layer1260. For example, the tunneling oxide layer1260has a thickness ranging from 50 Å to 150 Å.

As shown inFIG. 17, the devices1720and1722each include gates1272and1274. For example, the gates1272and1274are made of polysilicon. As another example, the thickness for these gates ranges from 70 nm to 300 nm. In yet another example, a part of the floating gate1274is located on the tunneling oxide layer260. Additionally, the devices1720and1722include an oxide-nitride-oxide stack1282on at least the gates1272and1274. In one embodiment, each oxide-nitride-oxide stack1282includes a first oxide layer, a nitride layer, and a second oxide layer. For example, the first oxide layer, the nitride layer, and the second oxide layer can each have a thickness ranging from 50 Å to 150 Å.

As shown inFIG. 17, the devices1720and1722include control gates1332. Additionally, the devices1720and1722include lightly doped drain regions1642. For example, the lightly doped drain regions each can have a dopant concentration ranging from about 1E18 per cm3to about to about 1E18 per cm3, and a thickness ranging from about 0.2 um to about 0.6 um. Moreover, the devices1720and1722include spacers1660for gates1272,1274, and1332. For example, the spacers each have a thickness ranging from 50 nm to 150 nm. In another example, the spacers can be made of silicon oxide or silicon nitride or an ONO (silicon oxide on silicon nitride on silicon oxide) stack. Also, the devices1720and1722include heavily doped drains and/or sources1672. For example, the heavily doped drains and/or sources1672each can have a dopant concentration ranging from about 1E15 per cm3to about 6E15 per cm3, and a depth ranging from 0.1 um to 0.4 um. In one embodiment, the devices1720and1722also include convention back end of line (BEOL) layers such as an inter-layer dielectric layer1680and metal layer1682.

As discussed above and further emphasized here,FIG. 17is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the devices1710and1712are used as one-time programmable (OTP) devices, whereas devices1720and1722are EEPROM devices. In an embodiment, one-time programmable (OTP) device1710includes a first gate oxide layer1210and a second gate oxide layer1310, the second gate oxide layer1310being thinner than the first gate oxide layer1210. It also has a first gate1270on the first gate oxide layer1210and a first dielectric layer1280on the first gate. OPT device1710also has an inter-gate oxide layer1320on the first gate1270. Additionally, a second gate1620overlying the first dielectric layer1280, the inter-gate oxide layer1320, and the second gate oxide layer1310. In a specific embodiment, the inter-gate oxide layer1320is adapted to shape a corner region of the second gate1620for programming the OTP device. In an embodiment, EEPROM devices1720and1722each includes a tunnel oxide region for program and erase of the EEPROM devices.

In one embodiment, these OTP devices cannot be erased by ultra-violet radiation, but can be erased by X-rays. As another example, the devices1710and1712include a quartz window in the package and used as erasable programmable read only memory (EPROM) devices. In one embodiment, the EPROM devices can be erased by ultra-violet radiation.

FIG. 18is a simplified top view for electrically programmable devices with embedded EEPROM devices according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown,FIG. 18is a cross sectional view along AA′ inFIG. 17.