Semiconductor device including anti-fuse element and method of manufacturing the device

In a semiconductor device including an anti-fuse element, a first electrode layer is formed on a semiconductor substrate. A first insulating layer is formed only on the first electrode layer for insulating the first electrode layer. An anti-fuse insulating film is coated on at least one side wall portion of each of the first electrode layer and the first insulating layer. A second electrode layer is formed on the anti-fuse insulating film, and the first and second electrode layers and the anti-fuse insulating film constitute the anti-fuse element.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates to an improvement of an anti-fuse element, and more 
particularly, to a semiconductor device of low capacitance including an 
anti-fuse element and suitable for high integration. 
2. Description of the Related Art 
An anti-fuse element is a switch element which can be irreversibly shifted 
from an electrically non-conductive state to a conductive state by an 
electrical method or other physical methods. The anti-fuse element is 
mainly used in an EPROM (Electrically Programmable Memory) or an FPGA 
(Field Programmable Gate Array). 
In general, an anti-fuse element is formed between two wire layers, and 
then programmed by selectively applying high voltage therebetween such 
that it is shifted from a non-conductive state to a conductive state, 
thereby electrically connecting the wire layers to each other. 
In light of this, the anti-fuse element, which is employed in a large 
capacity EPROM or FPGA operable at high speed, must have a sufficiently 
low resistance after the programming, a sufficiently small capacitance 
before the programming, and a sufficiently small size. 
Referring to FIGS. 1-4, a semiconductor device including a conventional 
anti-fuse element will be explained. FIG. 1 shows a first example of the 
anti-fuse element. As is shown in FIG. 1, the anti-fuse element comprises 
a highly doped diffusion layer 103 formed on a semiconductor substrate 
101, an anti-fuse insulating film 104 formed on the diffusion layer 103, 
and an electrode layer 105 formed on the film 104 (see U.S. Pat. No. 
4,823,181). 
The above structure has the following drawbacks: 
First, it inevitably has a high resistance (typically about 500 .OMEGA., 
and occasionally about several K .OMEGA.) after the programming due to the 
parasitic resistance of the diffusion layer 103. This makes it difficult 
to apply the anti-fuse element to the FPGA which must operate at high 
speed. 
Second, it is extremely difficult to make the size of the anti-fuse element 
smaller than a predetermined value since the size of the element region is 
determined by a LOCOS oxide film 102. This is disadvantageous in 
integration of elements. 
FIG. 2 shows a second example of the conventional anti-fuse element. As is 
shown in FIG. 2, the element comprises a first electrode layer 107 formed 
on the semiconductor substrate 101 with an insulating film 106 interposed 
therebetween, the anti-fuse insulating film 104 formed on the first 
electrode layer 107, and a second electrode layer 110 formed on the 
anti-fuse insulating film 104. The first and second electrode layers are 
metal layers (see '92 IEDM Technical Digest, pp. 611-614). It is known 
that this structure enables the electrode layers to have significantly low 
resistance even after programming. However, since an interlayer insulating 
film 108 formed on the first electrode layer 107 is thick, it is necessary 
to form a contact hole 109 in the interlayer insulating film 108. This 
being so, the size of the anti-fuse element is limited by the width of the 
hole, and cannot be set equal to or less than a minimum value determined 
in a lithography process. 
Moreover, masking is necessary to form the contact hole 109 in the 
insulating film 108, which requires the lithography process. 
FIG. 3 shows a third example of the anti-fuse element. As is shown in FIG. 
3, the anti-fuse element comprises a side wall portion of the electrode 
layer 107, that portion of the anti-fuse insulating film 104 which is 
formed on the side wall portion of the layer 107, and that portion of the 
second electrode layer 110 which is opposed to the side wall portion of 
the layer 107 via the anti-fuse insulating film 104 (see U.S. Pat. No. 
5,171,715). Since the anti-fuse element is formed parallel to the surface 
of the semiconductor substrate 101, it can have a small area. Since, 
however, the first electrode layer 107 and the interlayer insulating film 
108 on the layer 107 are formed thick, a contact hole 109 must be formed 
in that portion of the film 108 which is placed on the layer 107, and also 
in the layer 107. Therefore, as in the case of the second example, 
patterning is necessary to form the hole 109. For the patterning, it is 
necessary to make the first and second electrode layers 107 and 110 have 
sufficient widths in consideration of the occurrence of misalignment in 
masking. As a result, it is difficult to considerably increase the degree 
of integration of elements. 
The third example of the anti-fuse element will be explained in more detail 
with reference to its plan view of FIG. 4. The first and second electrode 
layers 107 and 110 are formed in a matrix, and the anti-fuse element is 
formed at an edge portion (indicated by the thick line) of each contact 
hole 109. This clarifies that the size of the anti-fuse element is 
determined in a lithography process, and hence that it is difficult to 
produce a highly integrated FPGA capable of high-speed operation. 
In light of the above, there has been a demand for improving the 
semiconductor device with the conventional anti-fuse element and the 
method for manufacturing the device. 
SUMMARY OF THE INVENTION 
It is an object of the invention to provide a semiconductor device 
including an anti-fuse element, in which the anti-fuse element does not 
surround each contact hole in electrode layers, but is present on at least 
one side wall portion of an electrode layer, thereby reducing the width of 
each electrode layer and making the semiconductor device suitable for high 
integration. 
It is another object of the invention to provide a method for manufacturing 
a semiconductor device including an anti-fuse element, which is suitable 
to high integration, by forming first and second electrode layer lines in 
a matrix with the use of an RIE method such that the value of distance 
between each adjacent pair of the electrode layers is smaller than the 
value of the width of a contact hole formed in the conventional 
lithography process. 
According to a first aspect of the invention, there is provided a 
semiconductor device including an anti-fuse element, comprising: 
a semiconductor substrate; 
a first electrode layer formed on the semiconductor substrate; 
a first insulating layer formed only on the first electrode layer for 
insulating the first electrode layer; 
an anti-fuse insulating film covering at least one side wall portion of 
each of the first electrode layer and the first insulating layer; and 
a second electrode layer formed on the anti-fuse insulating film, the first 
and second electrode layers and the anti-fuse insulating film constituting 
the anti-fuse element. 
According to a second aspect of the invention, there is provided a 
semiconductor device including anti-fuse elements, comprising: 
a semiconductor substrate; 
a first electrode layer group including a plurality of first electrode 
layers arranged in columns on the semiconductor substrate; 
a first insulating layer formed only on each of the first electrode layers 
for insulating the first electrode layers; 
an anti-fuse insulating film covering the entire surface of a resultant 
structure including upper portions of the first insulating layers, side 
wall portions of the first electrode layers and the first insulating 
layers; and 
a second electrode layer group including a plurality of second electrode 
layers arranged in rows on the anti-fuse insulating film, the second 
electrode layer group and the first electrode layer group being arranged 
in a matrix, the first and second electrode layers and the anti-fuse 
insulating film constituting the anti-fuse elements. 
According to a third aspect of the invention, there is provided a 
semiconductor device including anti-fuse elements, comprising: 
a semiconductor substrate; 
a first electrode layer group including a plurality of first electrode 
layers arranged in columns on the semiconductor substrate; 
a first insulating layer formed only on each of the first electrode layers 
for insulating the first electrode layers; 
an anti-fuse insulating film covering the entire surface of a resultant 
structure including upper portions of the first insulating layers, side 
wall portions of the first electrode layers and the first insulating 
layers; 
a second electrode layer group including a plurality of second electrode 
layers arranged in rows on the anti-fuse insulating film, the second 
electrode layers constituting a pair of anti-fuse elements at opposed side 
wall portions of each adjacent pair of the first electrode layers, each of 
the anti-fuse elements including a corresponding one of the first 
electrode layers, the anti-fuse insulating film and a corresponding one of 
the second electrode layers, the first electrode layer group and the 
second electrode layer group being arranged in a matrix; 
a second insulating layer formed on the anti-fuse insulating film for 
insulating the second electrode layer group; and 
a third electrode layer group including a plurality of third electrode 
layers arranged in rows on the second insulating layer and the second 
electrode layers. 
According to a fourth aspect of the invention, there is provided a method 
for manufacturing a semiconductor device including an anti-fuse element, 
comprising the steps of: 
forming a first metal layer on a semiconductor substrate with an oxide film 
interposed therebetween; 
forming a first insulating film on the first metal layer; 
selectively etching the first metal layer and the first insulating film, 
thereby forming a first electrode layer; 
coating at least one side wall portion of the first electrode layer with an 
anti-fuse insulating film; and 
forming a second electrode layer on the anti-fuse insulating film, the 
first and second electrode layers and the anti-fuse insulating film 
constituting the anti-fuse element. 
According to a fifth aspect of the invention, there is provided a method 
for manufacturing a semiconductor device including anti-fuse elements, 
comprising the steps of: 
forming on a semiconductor substrate a first electrode layer group 
including a plurality of first electrode layers arranged in columns; 
forming a first insulating layer only on each of the first electrode layers 
for insulating the first electrode layers; 
coating an anti-fuse insulating film on the entire surface of a resultant 
structure including upper portions of the first insulating layers, side 
wall portions the first electrode layers and the first insulating layers; 
and 
forming on the anti-fuse insulating film a second electrode layer group 
including a plurality of second electrode layers arranged in rows, such 
that the second electrode layer group and the first electrode layer group 
are arranged in a matrix, and the first and second electrode layers and 
the anti-fuse insulating film constitute the anti-fuse elements. 
According to a sixth aspect of the invention, there is provided a method 
for manufacturing a semiconductor device including anti-fuse elements, 
comprising the steps of: 
forming on a semiconductor substrate a first electrode layer group 
including a plurality of first electrode layers arranged in columns; 
forming a first insulating layer only on each of the first electrode layers 
for insulating the first electrode layers; 
coating an anti-fuse insulating film on the entire surface of a resultant 
structure including upper portions of the first insulating layers, side 
wall portions of the first electrode layers and the first insulating 
layers; 
forming on the anti-fuse insulating film a second electrode layer group 
including a plurality of second electrode layers arranged in rows, the 
second electrode layers including a pair of anti-fuse elements at opposed 
side wall portions of each adjacent pair of the first electrode layers, 
each of the anti-fuse elements including a corresponding one of the first 
electrode layers, the anti-fuse insulating film and a corresponding one of 
the second electrode layers, the first electrode layer group and the 
second electrode layer group being arranged in a matrix; 
forming a second insulating layer on the anti-fuse insulating film for 
insulating the second electrode layer group; and 
forming on the second insulating layer and the second electrode layers a 
third electrode layer group including a plurality of third electrode 
layers arranged in rows. 
Since in the above-described semiconductor device including the anti-fuse 
element, the anti-fuse element is constituted by the first and second 
electrode layers and the anti-fuse insulating film at a side wall portion 
of the first electrode layer, the electrode layer itself can have a narrow 
width, and hence the semiconductor device which includes the anti-fuse 
element can be made suitable to high integration. 
Further, since in the method for manufacturing the semiconductor including 
the anti-fuse element, a lithography process can be omitted, and 
patterning of a contact hole is not necessary, the degree of integration 
can be significantly increased. Thus, a low-capacity semiconductor device 
suitable to high integration can be manufactured. 
In addition, since in the method for manufacturing the semiconductor 
including the anti-fuse element, the anti-fuse element can be formed 
without a fine treatment such as the forming of a hole in the first 
electrode layer, the distance between the electrode layers can easily be 
set in a self-alignment manner.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The embodiments of the invention will be explained with reference to the 
accompanying drawings. 
As is shown in FIG. 5, after forming an oxide film 12 on a silicon 
substrate 11, a first metal layer 21 made of an Al alloy (Al/Si/Cu) and 
having a thickness of about 1000.ANG. is formed on the oxide film 12 by 
sputtering. 
Then, a first insulating film 22, such as a silicon oxide film, having a 
thickness of about 3000.ANG. is deposited by the plasma CVD method, or the 
like. 
Subsequently, as is shown in FIG. 6, the first metal layer 21 and the first 
insulating film 22 are selectively etched by the RIE method, thereby 
forming a first electrode layer 20. 
Further, as is shown in FIG. 7, an anti-fuse insulating film 13 formed of, 
e.g., a silicon nitride film and having a thickness of about 200.ANG. is 
deposited on the entire surface of the resultant structure by the plasma 
CVD method. Thereafter, an Al alloy (Al/Si/Cu) layer of about 6000.ANG. is 
deposited on the anti-fuse insulating film 13 by sputtering, and then 
patterned to form a second electrode layer 30. 
As is shown in the plan view of FIG. 8, the first and second electrode 
layers 20 and 30 are formed in a matrix. Anti-fuse elements 40 (indicated 
by the thick lines) comprise the first and second electrode layers 20 and 
30 and the anti-fuse insulating film 13, and are formed on opposite side 
wall portions of the first electrode layer 20 in a self-alignment manner. 
A second embodiment of the anti-fuse element will be explained with 
reference to FIGS. 9-11. In this case, however, only portions different 
from those of the first embodiment will be explained. 
As is shown in FIG. 9, the first and second electrode layers 20 and 30 are 
formed in a matrix in the second embodiment, too. However, the second 
electrode layer 30 comprises a second metal layer 31 and a third metal 
layer 32 connected to the second metal layer 31 in a contact hole 15. Each 
anti-fuse element 40 is formed on one of the side wall portions of each 
first electrode layer 20, i.e., on opposite side wall portions of each 
adjacent pair of the first electrode layers 20. 
A method for manufacturing the semiconductor device with the anti-fuse 
element shown in FIG. 9 will be explained with reference to FIGS. 10-12. 
Referring first to FIG. 10, a first electrode layer 20 and an anti-fuse 
insulating film 13 are formed on a silicon substrate 11, as in the first 
embodiment. Thereafter, a TiN layer with a thickness of 2000.ANG. is 
deposited on the insulating film 13 by sputtering, and then patterned such 
that it remains on upper portions of the insulating film 13 and the 
portions thereof covering the opposite side wall portions of each adjacent 
pair of the first electrode layers 20, thereby forming second metal layers 
31. 
Subsequently, as is shown in FIG. 11, an interlayer insulating film 14 is 
formed on the entire surface of the resultant structure, and contact holes 
15 are formed in those portions of the interlayer insulating film 14 which 
are located on the second metal layers 31. Thereafter, a third metal layer 
32 of an Al alloy (Al/Si/Cu) is formed. The third metal layer 32 is 
connected to the second metal layer 31 in the contact hole 15. These metal 
layers constitute the second electrode layer 30. 
Since, in the second embodiment, the anti-fuse element 40 is formed on only 
one side wall portion of the first electrode layer 20, its capacitance can 
be reduced to 1/2 of that in the first embodiment. Accordingly, the 
anti-fuse element 40 can have higher performance. 
In the first and second embodiments, the capacitance of the anti-fuse 
element can be reduced by making the first metal layer 21 as thin as 
possible. 
As described above, in the first and second embodiments, the anti-fuse 
elements 40 are formed on side wall portions of the first electrode layer 
20, which means that no contact hole is formed in the first electrode 
layer 20. As a result, the size of the anti-fuse element 40 is not limited 
to the minimum value required to form the contact hole by lithography. 
Therefore, the anti-fuse elements 40 can be highly integrated, and can be 
of a small capacitance. 
The material of first and second electrode layers is not limited to an Al 
alloy or TiN. Each of these layers may be formed of a single layer or a 
lamination layer which is made of a metal of a high fusing point (such as 
a doped polysilicon, Ti, W or Mo), or of their compounds or a silicide. 
Moreover, the first and second electrode layers are not necessarily made 
of the same material. In addition, the anti-fuse insulating film is not 
limited to a silicon nitride film, but may be formed of a lamination film 
or the like, as long as it is dielectric. 
Additional advantages and modifications will readily occur to those skilled 
in the art. Therefore, the present invention in its broader aspects is not 
limited to the specific details, representative devices, and illustrated 
examples shown and described herein. Accordingly, various modifications 
may be made without departing from the spirit or scope of the general 
inventive concept as defined by the appended claims and their equivalents.