Memory device including predecoder and operating method thereof

A memory device and operating method of the memory device are provided. The memory device comprises a memory cell storing data based on a first voltage, a row decoder selecting a wordline of the memory cell based on the first voltage, and a wordline predecoder configured to generate a “predec” signal, which is for generating a wordline voltage to be provided to the row decoder. The wordline predecoder is driven by the first voltage and a second voltage, which is different from the first voltage, receives a row address signal, associated with selecting the wordline, and an internal clock signal associated with adjusting operating timings of elements included in the memory device. The wordline predecoder performs a NAND operation on the row address signal and the internal clock signal, and provides the “predec” signal generated based on a result of the NAND operation to the row decoder.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No. 10-2021-0074133, filed on Jun. 8, 2021, and all the benefits accruing therefrom under 35 U.S.C. § 119, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Inventive concepts relate to a semiconductor device, and particularly, to a memory device equipped with a dual power line.

Semiconductor devices such as application processors may be configured as system-on-chips (SoCs) including a plurality of functional blocks (IP) (e.g. blocks of standard cells), and the SoCs may include static random access memories (SRAMs), which are typically used as cache and/or buffer memories. There is a trend to lower the driving voltage for a mobile device for the efficiency of power, but there is a limit in lowering the voltage provided to memory cells to ensure a sufficient margin for an SRAM included in the mobile device. However, the voltage provided to peripheral circuits can be lowered below the voltage provided to the memory cells. This type of SRAM power supply method may be referred to as a dual power supply scheme. However, as the difference between the voltage provided to the memory cells and the voltage provided to the peripheral circuits increases, a timing skew may occur. Thus, the need/desire of techniques for securing an operating margin for memory cells and/or reducing power consumption arises.

SUMMARY

Example embodiments of Inventive concepts provide a memory device equipped with a dual voltage line that consumes less power and/or has an operating margin secured.

Example embodiments of Inventive concepts also provide an operating method of a memory device equipped with a dual voltage line that consumes less power and/or has an operating margin secured.

However, example embodiments of Inventive concepts are not restricted to those set forth herein. The above and other example embodiments of Inventive concepts will become more apparent to one of ordinary skill in the art to which Inventive concepts pertains by referencing the detailed description of Inventive concepts given below.

According to some aspects of inventive concepts, there is provided a memory device comprising a memory cell configured to store data based on a first voltage, a row decoder configured to select a wordline of the memory cell based on the first voltage, and a wordline predecoder configured to generate a “predec” signal associated with generating a wordline voltage to be provided to the row decoder. The wordline predecoder is configured to be driven by the first voltage and by a second voltage which is different from the first voltage, configured to receive a row address signal associated with selecting the wordline, and to receive an internal clock signal associated with adjusting operating timings of elements included in the memory device, configured to perform a NAND operation on the row address signal and the internal clock signal, and configured to provide the “predec” signal generated based on a result of the NAND operation to the row decoder.

According to some aspects of inventive concepts, there is provided a memory device comprising a static random-access memory (SRAM) cell connected to a wordline and a bitline, a wordline driver configured to provide a wordline voltage having a first voltage to the wordline, a bitline precharge circuit configured to provide a bitline voltage having a second voltage, which is lower than the first voltage, to the bitline, and a wordline predecoder configured to generate a “predec” signal, which is associated with enabling the wordline voltage. The wordline predecoder includes a pull-up transistor, which is configured to pull up the “predec” signal based on a first control signal having the first voltage, and a first pull-down transistor, which is configured to pull down the “predec” signal based on a second control signal having the second voltage.

According to some aspects of inventive concepts, there is provided an operating method of a memory device comprising allowing an internal clock signal to transition from a first level to a second level, in response to the internal clock signal transitioning to the second level, allowing a bitline precharge voltage to rise from the first level to the second level at a first time, and in response to the internal clock signal transitioning to the second level, allowing a wordline voltage to rise from the first level to a third level, which is greater than the second level, at a second time, which is later than the first time.

Other features and example embodiments may be apparent from the following detailed description, the drawings, and the claims.

DETAILED DESCRIPTION OF SOME EXAMPLE EMBODIMENTS

Some example embodiments of inventive concepts will hereinafter be described with reference to the accompanying drawings.

FIG.1is a block diagram of a memory device equipped with a dual voltage line, according to some embodiments of inventive concepts.

Referring toFIG.1, a memory device1may include a memory circuit100, a peripheral circuit200, a wordline predecoder300, and a controller400. A dual voltage including a first voltage VDDH and a second voltage VDDL, which is lower than/less than (less in absolute value than) the first voltage VDDH and a third voltage (e.g., a ground voltage), may be provided to the memory device1. The first voltage VDDH may be provided to the memory circuit100, and the first or second voltage VDDH or VDDL may be selectively provided to the peripheral circuit200and the precoder circuit300, for example depending on the operation mode of the memory device1.

In a case where the memory device1is set to a high-speed operation mode, the controller400may select the first voltage VDDH from among the first and second voltages VDDH and VDDL based on an operation mode control signal CTRL_m, and may provide the first voltage VDDH to the peripheral circuit200and the wordline predecoder300. Alternatively, in a case where the memory device1is set to a low-speed operation mode (or a low-power operation mode), the controller400may select the second voltage VDDL from between the first and second voltages VDDH and VDDL based on the operation mode control signal CTRL_m, and may provide the second voltage VDDL to the peripheral circuit200and the wordline predecoder300.

The operating speed of the memory device1, which is provided with a double voltage line, can be increased by applying a relatively high voltage (e.g., the first voltage VDDH), and the power consumption of the memory device1can be reduced by applying a relatively low voltage (e.g., the second voltage VDDL). For example, the voltage applied to the memory device1may be selectively controlled depending on the purpose of use of the memory device1.

However, in a case where the memory device1is set to the lower-power operation mode (e.g. the low-speed operation mode), a timing skew may be generated due to the difference between the first voltage VDDH, applied to the memory circuit100, and the second voltage VDDL, applied to the peripheral circuit200. In this case, an additional circuit for compensating for the timing skew may be needed, resulting in an increase in performance overhead.

FIG.2is a block diagram of the memory device1.

Referring toFIG.2, the memory circuit100may include a row decoder110, a wordline driver (“WL DRIVER”)120, and a memory cell array130. The row decoder110may receive a row address signal ROW_ADDR and a “predec” signal PREDEC, e.g. from the outside. The row decoder110may apply a wordline voltage WL to a wordline driver for selecting a wordline based on the “predec” signal PREDEC. The structure of the row decoder110will be described later. The wordline driver120may be connected to the memory cell array130through a plurality of wordlines (e.g. rows). Under the control of the row decoder110, the wordline driver120may select one of a plurality of wordlines (not illustrated) included in the memory cell array130based on the row address ROW_ADDR. Also, the wordline driver120may apply the wordline voltage WL to the selected wordline. Here, the wordline voltage WL may include a read wordline voltage and a write wordline voltage that may or may not be the same as each other. The read wordline voltage and/or the write wordline voltage may be greater than a threshold voltage of transistors included in cells131that are included in the memory cell array130. The memory cell array130may be connected to the wordline driver120through the wordlines and may be connected to a column multiplexer236through a plurality of bitlines. The memory cell array130may include a memory cell131, which is connected to the wordlines and the bitlines. The memory cells131may be (or may include) a static random access memory (SRAM) cell including, for example, two (cross-coupled) inverters, but inventive concepts are not limited thereto. The SRAM cell may be or may include a six-transistor (6T) cell; however, example embodiments are not limited thereto, and the SRAM cell may be or may include other configurations such as but not limited to a 4T cell, or an 8T cell.FIG.2illustrates the memory cell array130as including only one memory cell131, but inventive concepts are not limited thereto. For example, the memory cell array130may include more than one memory cell131, and may be arranged in an array, e.g. a rectangular (or square) array of rows and columns.

The peripheral circuit200may include an address latch (“ADDR LATCH”)210, an internal clock signal generator (“ICK GENERATOR”)220, a data read/write circuit230, and a bitline precharge circuit240. The address latch210may receive an address signal ADDR generated by a control circuit (not illustrated) and may provide a row address signal ROW_ADDR to the wordline predecoder300and to the row decoder110. Examples of the row address signal ROW_ADDR may include a high (large) row address signal and a low (small) row address signal. The wordline predecoder310may receive the low row address signal, may convert the low row address signal into a “predec” signal PREDEC, and may output the “predec” signal PREDEC to the row decoder110. The row decoder110may receive the high row address signal and the “predec” signal PREDEC and may generate the wordline voltage WL, which is for selecting one of the wordlines, based on the high row address signal and on the “predec” signal PREDEC. The internal clock signal generator220may receive a clock signal from the control circuit and may generate an internal clock signal ICK. The internal clock signal generator220may provide the internal clock signal ICK to each of or some of the elements and/or the circuits of the memory device1to adjust the operation timings of the elements and/or the circuits of the memory device1.

The data read/write circuit230may write data Din, which is provided by an external circuit, block, and/or device, to the memory cell131, connected to a wordline and at least one bitline pair selected by the control circuit. Alternatively or additionally, the data/write circuit230may read data Dout from the memory cell131and may provide the data Dout to the external circuit, block, or device. For example, the data read/write circuit340may include a write enable latch231, which receives a write enable signal WEN, a write enable circuit232, which provides the write enable signal WE from the write enable latch231to a column decoder233and a write driver235, and the column decoder233, which controls the column multiplexer236based on the write enable signal WEL. Also, the data read/write circuit340may include a data latch234, which receives the data Din from the external circuit, block, or device, the write driver235, which writes the data Din to the memory cell array130, the column multiplexer236, which selects at least one bitline pair, a sense amplifier237, which senses the data Dout stored in the memory cell131, and a data driver238, which provides the data Dout sensed by the sense amplifier237to the external circuit, block, or device. A bitline precharge circuit240may precharge the bitline pair selected by the control circuit.

The memory cell array130may include other cells, for example redundancy cells (not illustrated). There may be a redundancy check circuit (not illustrated) connected to either or both of the row decoder110and the column decoder233. The redundancy check circuit may determine and/or reroute the row address ROW_ADDR and/or the column address COL_ADDR based on a check of redundancy.

The wordline predecoder300may include a wordline predecoder (“WL PREDECODER”)310, a first level shifter320, and a second level shifter330. The wordline predecoder310may receive the row address signal ROW_ADDR from the address latch210, may receive the internal clock signal ICK from the internal clock signal generator220, and may generate the “predec” signal PREDEC based on the row address signal ROW_ADDR and on the internal clock signal ICK. The first level shifter320may receive the row address signal ROW_ADDR from the address latch210, may shift the level of the row address signal ROW_ADDR, and may provide the level-shifted row address signal ROW_ADDR to the wordline predecoder310. The second level shifter330may receive the internal clock signal ICK from the internal clock signal generator220, may shift the level of the internal clock signal ICK, and may provide the level-shifted internal clock signal ICK to the wordline predecoder310. The wordline predecoder310may be connected to/directly connected to the address latch210and the internal clock signal generator220and may thus receive the row address signal ROW_ADDR and the internal clock signal ICK. For example, the wordline predecoder310may receive the level-shifted row address signal ROW_ADDR and the level-shifted internal clock signal ICK from the first and second level shifters320and330. For example, the wordline predecoder310may receive a row address signal ROW_ADDR having the first or second voltage VDDH or VDDL and an internal clock signal ICK having the first or second voltage VDDH or VDDL. The wordline predecoder310will be described later in further detail.

The structure of the memory cell131and data read/write operations will hereinafter be described.

FIG.3is a circuit diagram of the memory cell131ofFIG.2.FIG.4illustrates the operation of the memory cell131ofFIG.3.FIGS.5and6are circuit diagrams for explaining the operation of the memory cell131ofFIG.3.

Referring toFIGS.3,5, and6, the memory cell131may include a first inverter, which consists of or includes a first P-type metal-oxide-semiconductor (PMOS) transistor MP1, e.g. a first pullup transistor and a first N-type metal-oxide-semiconductor (NMOS) transistor MN1, e.g. a first pulldown transistor. The memory cell may include a second inverter, which consists of or includes a second PMOS transistor MP2(a second pullup transistor) and a second NMOS transistor MN2(a second pulldown transistor). The memory cell may further include third and fourth NMOS transistors MN3and MN4, e.g. first and second passgate transistors, which receive a wordline voltage as a gate voltage and function as switches. The memory cell131may use the first voltage VDDH as a cell voltage. For example, the first voltage VDDH is provided to the common source of the first and second PMOS transistors MP1and MP2. Thus, the memory cell131may be supplied with the first voltage VDDH, which is higher than (greater than) the second voltage VDDL, regardless of the operation mode of the memory device1. The first and second inverters may form a latch circuit, and the latch circuit may receive the first voltage VDDH and may maintain data with the first voltage VDDH.FIG.3illustrates the third and fourth NMOS transistors MN3and MN4as being turned on by a wordline voltage V_WL having a first level (e.g., a high level) which may be greater than a threshold voltage of third and fourth NMOS transistors MN3and MN4, but inventive concepts are not limited thereto. For example, the first and fourth NMOS transistors may be configured to be turned on by a wordline voltage having a third level (e.g., a low level), which may be greater than a threshold voltage of the third and fourth NMOS transistors MN3and MN4.

The operation of the memory cell131will hereinafter be described with reference toFIGS.4through6.FIG.4shows example data stored in the memory cell131, for explaining the operation of the memory cell131. Referring toFIG.4, a data value of logic “0” may be stored in the memory cell131when the voltage at a first node SN1of the memory cell131has a low level and the voltage at a second node SN2of the memory cell131has a high level. A data value of logic “1” may be stored in the memory cell131when the voltage at the first node SN1has a high level and the voltage at the second node SN2has a low level. However, inventive concepts are not limited to this. Alternatively, the data value of “0” may be stored in the memory cell131when the voltage at the first node SN1has a high level and the voltage at the second node SN2has a low level.

Referring toFIGS.5and6, a latch circuit consisting of or including a pair of inverters may store data. During a read operation for the memory cell131, information indicating whether the memory cell131stores a data value of “0” or “1” is transmitted to an output terminal. For example, first and second bitlines BL and BLS (e.g. bitline true and bitline complimentary) are precharged to a predetermined or variable determined voltage. The value of a wordline signal of the memory cell131becomes “1” so that the first and second nodes SN1and SN2of the memory cell131are connected to the first and second bitlines BL and BLS, respectively. Then, the voltages of the first and second bitlines BL and BLS change in accordance with the data stored in the memory cell131. Then, a voltage difference ΔV between the first and second bitlines B11and BLS is sensed and amplified by the sense amplifier237, and the result of the sensing is transmitted to the data driver238. In this manner, the read operation for the memory cell131is performed.

Once the read operation for the memory cell131begins, the value of the wordline signal of the memory cell131becomes “1”. For example, in a case where the value of the wordline signal of the memory cell131becomes “1” and the read operation for the memory cell131is being performed, a cell current from the first bitline BL flows into the memory cell131so that the voltage of the first bitline BL decreases and the voltage of the second bitline BLS increases. For example, there may be a splitting of rails between the first bitline BL and the second bitline BLS. As a result, the voltage difference ΔV arises between the first and second bitlines BL and BLS and is transmitted to the sense amplifier237. Then, the sense amplifier237performs a sensing operation. The sensing operation of the sense amplifier237is performed by the voltage difference ΔV, and the sense amplifier237senses which of the voltages of the first and second bitlines BL and BLS has decreased, and transmits a digital data value of “0” or “1” to the data driver237based on the result of the sensing. However, inventive concepts are not limited to this.

The structure of the row decoder110will hereinafter be described with reference toFIG.7.

FIG.7is a circuit diagram of the row decoder ofFIG.2.

Referring toFIG.7, the row decoder110includes a first NAND gate NAND1, which receives the row address signal ROW_ADDR as an input signal, a second NOR gate NOR1, which receives the output of the first NAND gate NAND1as and a retention signal RET as input signals, a first transmission gate TM1, which receives the “predec” signal PREDEC as an input signal and outputs a decoding signal, and a first inverter INV1, which is connected to a final output terminal. The row address signal ROW_ADDR input to the first NAND gate NAND1of the row decoder110may be a high (or large) row address signal. The retention signal RET may reduce power consumption by blocking the power of the peripheral circuit200in accordance with the operation of the memory cell131.FIG.7illustrates only one row decoder110, but the number of row decoders110is not particularly limited. For example, as many row decoders as there are wordlines may be provided.

FIG.8is a block diagram for explaining the wordline predecoder310, to which a dual voltage is provided.

Referring toFIG.8, each of the row address signal ROW_ADDR and the internal clock signal ICK may be provided to the wordline predecoder310as a dual voltage consisting of or including the first and second voltages VDDH and VDDL. A row address signal ROW_ADDR having the second voltage VDDL may be provided from the address latch210to the wordline predecoder310, and a row address signal ROW_ADDR level-shifted from the second voltage VDDL to the first voltage VDDH by the first level shifter320may be provided to the wordline predecoder310. Similarly, an internal clock signal ICK having the second voltage VDDL may be provided from the internal clock signal generator220to the wordline predecoder310, and an internal clock signal ICK level-shifted from the second voltage VDDL to the first voltage VDDH by the second level shifter330may be provided to the wordline predecoder310.

The operation of the wordline predecoder310, to which a dual voltage is provided, will hereinafter be described.

FIG.9is a circuit diagram for explaining the operation of the wordline predecoder310when the memory device1is set to a high-speed operation mode.

Referring toFIG.9, the wordline predecoder310may include a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6. The first voltage VDDH may be provided to the sources of the third and fourth PMOS transistors MP3and MP4. The drains of the third and fourth PMOS transistors MP3and MP4may be electrically connected (e.g. directly connected) to each other. The third and fourth PMOS transistors MP3and MP4may receive a row address signal ROW_ADDR having the first voltage VDDH and an internal clock signal ICK having the first voltage VDDH as respective gate voltages. For example, the third and fourth PMOS transistors MP3and MP4may form an OR logic circuit that performs an OR operation. The OR logic circuit may output the “predec” signal PREDEC as the first voltage VDDH based on the result of the OR operation.

The drain of the fifth NMOS transistor MN5may be connected to the source of the sixth NMOS transistor MN6, and a third voltage VSS may be connected to the drain of the sixth NMOS transistor MN6. The fifth NMOS transistor MN5may receive the row address signal ROW_ADDR having the first voltage VDDH as a gate voltage, and the sixth NMOS transistor MN6may receive the internal clock signal ICK having the first voltage VDDH as a gate voltage. For example, the fifth and sixth NMOS transistors MN5and MN6may form an AND logic circuit that performs an AND operation. The AND logic circuit may ground the “predec” signal PREDEC to a low value, e.g. as low as the third voltage VSS based on the result of the AND operation.

Referring toFIG.9, in a case where the memory device1is operating in a high-speed operation mode, the row address signal ROW_ADDR having the first voltage VDDH and the internal clock signal ICK having the first voltage VDDH are provided to the gates of the third and fourth PMOS transistors MP3and MP4, respectively and the gates of the fifth and sixth NMOS transistors MN5and MN6, respectively. Also, the row address signal ROW_ADDR having the first voltage VDDH and the internal clock signal ICK having the first voltage VDDH are provided to the respective gates of the fifth and sixth NMOS transistors MN5and MN6. In this case, as signals having a relatively high voltage (e.g., the first voltage VDDH) are provided to both the gates of the third and fourth PMOS transistors MP3and MP4and the gates of the fifth and sixth NMOS transistors MN5and MN6, the amount of time taken to connect (e.g. turn on) and disconnect (e.g. turn off) the source and drain of each of the third and fourth PMOS transistors MP3and MP4and the source and drain of each of the fifth and sixth NMOS transistors MN5and MN6may be reduced. Thus, the operating speed of the memory device1can be improved.

For example, the internal clock signal ICK provided to the gate of the fourth PMOS transistor MP4may be generated from the second level shifter330, while the row address ROW_ADDR provided to the gate of the third PMOS transistor MP3may be generated from the first level shifter320. Furthermore, the internal clock signal ICK provided to the gate of the sixth NMOS transistor MN6may be generated from the first level shifter320, while the row address ROW_ADDR provided to the gate of the fifth NMOS transistor MN5may be generated from the second level shifter330.

FIG.10is a timing diagram for explaining the operation of the memory device according to the embodiment ofFIG.9.

FIG.10illustrates the operation of the memory device1, which is equipped with a dual voltage line, when a uniform predetermined voltage VDD is applied to the memory device1. The voltage VDD may be one of a variety of voltages including the first and second voltages VDDH and VDDL.

Referring toFIG.10, the internal clock signal ICK is output from the internal clock signal generator220at a time t1.

Thereafter, in response to the internal clock signal ICK being applied to the bitline precharge circuit240, a bitline precharge voltage PCH rises to as high as the voltage VDD at a time t2.

In response to the internal clock signal ICK being applied to the wordline predecoder310, the “predec” signal PREDEC is generated in the wordline predecoder310and is applied to the row decoder110, the row decoder110selects one of the wordlines of the memory cell array130in response to the “predec” signal PREDEC. The wordline driver120applies the wordline voltage WL to the selected wordline so that the wordline voltage rises to as high as the voltage VDD at a time t3. As the wordline voltage WL needs to/is to pass through the wordline predecoder310and the row decoder110to be applied, the time t3when the wordline voltage WL rises may come later than the time t2when the bitline precharge voltage PCH rises.

Thereafter, the wordline voltage WL decreases back at a time t4, and the bitline precharge voltage PCH also decreases at a time t5. The pulse width of the wordline driving voltage WL may be (t4−t3), and the pulse width of the bitline precharge voltage PCH may be (t5−t2). As illustrated inFIG.10, the pulse width of the wordline voltage WL may be smaller than the pulse width of the bitline precharge voltage PCH. The sense amplifier237may sense the voltage difference ΔV between the first and second bitlines BL and BLS, between the time t4and the time t5.

If a single uniform voltage (e.g., the voltage VDD), rather than a dual voltage, is applied to the memory device1, the bitline precharge voltage PCH rises and falls ahead of the wordline voltage WL, as illustrated inFIG.10. Thus, a timing skew does not occur.

FIG.11is a circuit diagram for explaining the operation of the wordline predecoder310when the memory device1is set to the low-power operation mode.

Referring toFIG.11, the wordline predecoder310may include the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6. The first voltage VDDH may be provided to the sources of the third and fourth PMOS transistors MP3and MP4. The drains of the third and fourth PMOS transistors MP3and MP4may be electrically connected to/directly connected to each other. The third and fourth PMOS transistors MP3and MP4may receive the row address signal ROW_ADDR having the first voltage VDDH and the internal clock signal ICK having the first voltage VDDH as their gate voltages. For example, the third and fourth PMOS transistors MP3and MP4may form an OR logic circuit that performs an OR operation. The OR logic circuit may output the “predec” signal PREDEC as the first voltage VDDH based on the result of the OR operation.

Alternatively, the drain of the fifth NMOS transistor MN5may be connected to the source of the sixth NMOS transistor MN6, and the third voltage VSS may be connected to the drain of the sixth NMOS transistor MN6. The fifth NMOS transistor MN5may receive the row address signal ROW_ADDR having the second voltage VDDL as a gate voltage, and the sixth NMOS transistor MN6may receive the internal clock signal ICK having the second voltage VDDL as a gate voltage. For example, the fifth and sixth NMOS transistors MN5and MN6may form an AND logic circuit that performs an AND operation. The AND logic circuit may ground the “predec” signal PREDEC to as low as the third voltage VSS based on the result of the AND operation.

Referring toFIG.11, in a case where the memory device1is in the low-power operation mode, the row address signal ROW_ADDR having the first voltage VDDH and the internal clock signal ICK having the first voltage VDDH are provided to the gates of the third and fourth PMOS transistors MP3and MP4and the gates of the fifth and sixth NMOS transistors MN5and MN6. However, the row address signal ROW_ADDR having the second voltage VDDL and the internal clock signal ICK having the second voltage VDDL are provided to the gates of the fifth and sixth NMOS transistors MN5and MN6In this case, as signals having a relatively high voltage (i.e., the first voltage VDDH) are provided to the gates of the third and fourth PMOS transistors MP3and MP4, the amount of time that it takes to connect (or turn on) and disconnect (or turn off) the source and drain of each of the third and fourth PMOS transistors MP3and MP4can be reduced. On the contrary, as signals having a relatively low voltage (i.e., the second voltage VDDL) are provided to the gates of the fifth and sixth NMOS transistors MN5and MN6, the amount of time that it takes to connect (or turn on) and disconnect (or turn off) the source and drain of each of the third and fourth PMOS transistors MP3and MP4increases relatively. Thus, the operating speed of the memory device1may become slower in the low-speed operation mode than in the high-speed operation mode. However, as the second voltage VDDL, which is relatively low, is provided to the peripheral circuit200, the power consumption of the memory device1can be reduced.

For example, the internal clock signal ICK provided to the gate of the fourth PMOS transistor MP4may be generated from second level shifter330, while the row address ROW_ADDR provided to the gate of the third PMOS transistor MP3may be generated from the first level shifter320. Furthermore, the internal clock signal ICK provided to the gate of the sixth NMOS transistor MN6may be generated from the internal clock signal generator220, while the row address ROW_ADDR provided to the gate of the fifth NMOS transistor MN5may be generated from the address latch210.

FIG.12is a timing diagram for explaining the operation of the memory device according to some example embodiments described with reference toFIG.11.

The operation of the memory device1in a case where the memory device1is set to the low-power operation mode will hereinafter be described with reference toFIG.12.

Referring toFIG.12, the internal clock signal ICK is output from the internal clock signal generator220at a time t1.

Thereafter, in response to the internal clock signal ICK having the second voltage VDDL being applied to the bitline precharge circuit240, the bitline precharge voltage PCH rises to as high as the second voltage VDDL at a time t2. The second voltage VDDL may be lower than the voltage VDD ofFIG.10. As already mentioned above, in a case where the voltage applied to the gate of a transistor becomes low, the turning on or off of the transistor may become slow. Thus, the time t2may come later than its counterpart ofFIG.10.

In response to the internal clock signal ICK being applied to the wordline predecoder310, the “predec” signal PREDEC is generated in the wordline predecoder310and is applied to the row decoder110, the row decoder110selects one of the wordlines of the memory cell array130in response to the “predec” signal PREDEC, and the wordline driver120applies the wordline voltage WL to the selected wordline so that the wordline voltage rises to as high as the first voltage VDDH at a time t3. As already mentioned above, even when the memory device1is set to the low-power operation mode, the memory circuit100may operate at the first voltage VDDH, which is a relatively high voltage, to secure an operating margin. Thus, the transistors included in the memory circuit100may be turned on or off later than transistors operating at the second voltage VDDL. However, as the fifth and sixth NMOS transistors MN5and MN6of the wordline predecoder310, which determine when to generate the “predec” signal PREDEC, operate at the second voltage VDDL, the “predec” signal PREDEC may be generated relatively late. Thus, the time t3when the wordline voltage WL rises may still come later than the time t2when the bitline precharge voltage PCH rises.

Thereafter, the wordline voltage WL decreases back at a time t4, and the bitline precharge voltage PCH also decreases at a time t5. The pulse width of the wordline driving voltage WL may be (t4−t3), and the pulse width of the bitline precharge voltage PCH may be (t5−t2). As illustrated inFIG.12, the pulse width of the wordline voltage WL may be smaller than the pulse width of the bitline precharge voltage PCH. The sense amplifier237may sense and amplify the voltage difference ΔV between the first and second bitlines BL and BLS, between the time t4and the time t5.

Even if a dual voltage (i.e., the first and second voltages VDDH and VDDL) is applied to the memory device1, the bitline precharge voltage PCH rises ahead of the wordline voltage WL and falls later than the wordline voltage WL, as illustrated inFIG.12. Thus, a timing skew does not occur.

FIG.13is a timing diagram for explaining the operation of a memory device not including the wordline predecoder310.

Referring toFIG.13, in a memory device equipped with a double voltage line that does not include the wordline predecoder310, an internal clock signal ICK is output from an internal clock signal generator220at a time t1.

Thereafter, a row decoder110selects one of a plurality of wordlines of a memory cell array130in response to the internal clock signal ICK, and a wordline driver120applies a wordline voltage WL to the selected wordline so that the wordline voltage WL rises to as high as a first voltage VDDH at a time t2.

In response to the internal clock signal ICK being applied to a bitline precharge circuit240, a bitline precharge voltage PCH rises to as high as a second voltage VDDL at a time t3.

For example, in a case where the wordline predecoder310is not provided, the row decoder110and the wordline driver120, which operate at the first voltage VDDH, are faster than the bitline precharge circuit240, the time t2when the wordline voltage WL rises may be earlier than the time t3when the bitline precharge voltage PCH rises. In this case, a period of time when the wordline voltage WL rises to the first voltage VDDH but the bitline precharge voltage PCH is yet to rise up to the second voltage VDDL, e.g., a timing skew, may occur.

Thereafter, the wordline voltage WL decreases back at a time t4, and the bitline precharge voltage PCH also decreases at a time t5. The pulse width of the wordline driving voltage WL may be (t4−t2), and the pulse width of the bitline precharge voltage PCH may be (t5−t3). As illustrated inFIG.13, the pulse width of the wordline voltage WL may be smaller than the pulse width of the bitline precharge voltage PCH. As the wordline voltage WL rises ahead of the bitline precharge voltage PCH, a timing skew may occur, and data cannot be read from, or written to, memory cells131during the timing skew. Thus, the effective operating window of the memory device1can be reduced.

A sufficient margin for the memory device1for a data read/write operation can be secured, and the operating reliability of the memory device1can be improved, as compared to a memory device not including the wordline predecoder310.

The operation of a wordline predecoder of a memory device according to some embodiments of inventive concepts, to which a dual voltage is provided, will hereinafter be described.

FIG.14is a circuit diagram for explaining the operation of a wordline predecoder of a memory device according to some embodiments of inventive concepts in a case where the memory device is set to a low-power operation mode.

Referring toFIG.14, a wordline predecoder310of a memory device1may include a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6. A first voltage VDDH may be provided to the sources of the third and fourth PMOS transistors MP3and MP4. The drains of the third and fourth PMOS transistors MP3and MP4may be electrically connected to each other. The third and fourth PMOS transistors MP3and MP4may receive a row address signal ROW_ADDR having the first voltage VDDH and an internal clock signal ICK having the first voltage VDDH as their gate voltages. That is, the third and fourth PMOS transistors MP3and MP4may form an OR circuit. The OR logic circuit may output the “predec” signal PREDEC as the first voltage VDDH based on the result of the OR operation.

However, the drain of the fifth NMOS transistor MN5may be connected to the source of the sixth NMOS transistor MN6, and a third voltage VSS may be connected to the drain of the sixth NMOS transistor MN6. The fifth NMOS transistor MN5may receive the row address signal ROW_ADDR having the first voltage VDDH as a gate voltage, and the sixth NMOS transistor MN6may receive an internal clock signal ICK having a second voltage VDDL as a gate voltage. For example, the fifth and sixth NMOS transistors MN5and MN6may form an AND logic circuit that performs an AND operation. The AND logic circuit may ground the “predec” signal PREDEC to as low as the third voltage VSS based on the result of the AND operation.

Referring toFIG.14, in a case where the memory device1is in the low-power operation mode, the row address signal ROW_ADDR having the first voltage VDDH and the internal clock signal ICK having the first voltage VDDH are provided to the gates of the third and fourth PMOS transistors MP3and MP4and the gate of the fifth NMOS transistor MN5. On the contrary, the internal clock signal ICK having the second voltage VDDL is provided to the gate of the sixth NMOS transistor MN6. In this case, as signals having a relatively high voltage (i.e., the first voltage VDDH) are provided to the gates of the third and fourth PMOS transistors MP3and MP4and the gate of the fifth NMOS transistor MN5, the amount of time that it takes to connect (e.g., turn on) and disconnect (e.g., turn off) the source and drain of each of the third and fourth PMOS transistors MP3and MP4and the fifth NMOS transistor MN5can be reduced. However, as a signal having a relatively low voltage (e.g., the second voltage VDDL) is provided to the gate of the sixth NMOS transistor MN6, the amount of time that it takes to connect (or turn on) and disconnect (or turn off) the source and drain of the sixth NMOS transistor MN6increases relatively. Thus, the operating speed of the memory device1may become slower in the low-speed operation mode than in the high-speed operation mode. However, as the second voltage VDDL, which is relatively low, is provided to a peripheral circuit200, the power consumption of the memory device1can be reduced.

For example, the internal clock signal ICK provided to the gate of the fourth PMOS transistor MP4may be generated from second level shifter330, while the row address ROW_ADDR provided to the gate of the third PMOS transistor MP3may be generated from the first level shifter320. Furthermore, the internal clock signal ICK provided to the gate of the sixth NMOS transistor MN6may be generated from the first level shifter320, while the row address ROW_ADDR provided to the gate of the fifth NMOS transistor MN5may be generated from the internal clock signal generator220.

FIG.15is a timing diagram for explaining the operation of the memory device according to some example embodiments described with reference toFIG.14.

Referring toFIG.15, an internal clock signal ICK is output from an internal clock signal generator220at a time t1.

Thereafter, a row decoder110selects one of a plurality of wordlines of a memory cell array130in response to the internal clock signal ICK, and a wordline driver120applies a wordline voltage WL to the selected wordline so that the wordline voltage WL rises to as high as the first voltage VDDH at a time t2.

In response to the internal clock signal ICK being applied to a bitline precharge circuit240, a bitline precharge voltage PCH rises to as high as the second voltage VDDL at a time t3.

For example, in the memory device1including the wordline predecoder310ofFIG.14, the row decoder110and the wordline driver120, which operate at the first voltage VDDH, are faster than the bitline precharge circuit240, the time t2when the wordline voltage WL rises may be earlier than the time t3when the bitline precharge voltage PCH rises. In this case, a period of time when the wordline voltage WL rises to the first voltage VDDH but the bitline precharge voltage PCH is yet to rise to the second voltage VDDL, i.e., a timing skew, occurs. However, the memory device1including the wordline predecoder310ofFIG.14can reduce a timing skew, as compared the memory device according to some example embodiments described with reference toFIG.13that does not include the wordline predecoder310.

Thereafter, the wordline voltage WL decreases back at a time t4, and the bitline precharge voltage PCH also decreases at a time t5. The pulse width of the wordline driving voltage WL may be (t4−t2), and the pulse width of the bitline precharge voltage PCH may be (t5−t3). As illustrated inFIG.15, the pulse width of the wordline voltage WL may be smaller than the pulse width of the bitline precharge voltage PCH.

The memory device1according to some example embodiments described with reference toFIG.14can reduce a timing skew as compared to the memory device according to the embodiment ofFIG.13, and the effective operating window of the memory device1according to some example embodiments described with reference toFIG.14can be widened. Thus, a sufficient margin for a data read/write operation can be or more likely to be secured, and the operating reliability of the memory device1according to some example embodiments described with reference toFIG.14can be improved.

The operation of a wordline predecoder of a memory device according to some embodiments of inventive concepts will hereinafter be described.

FIG.16is a circuit diagram for the operation of a wordline predecoder of a memory device according to some embodiments of inventive concepts in a case where the memory device is set to a low-power operation mode.

Referring toFIG.16, a wordline predecoder310may include a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6. A first voltage VDDH may be provided to the sources of the third and fourth PMOS transistors MP3and MP4. The drains of the third and fourth PMOS transistors MP3and MP4may be electrically connected to each other. The third and fourth PMOS transistors MP3and MP4may receive a row address signal ROW_ADDR having the first voltage VDDH and an internal clock signal ICK having the first voltage VDDH as their gate voltages. For example, the third and fourth PMOS transistors MP3and MP4may form an OR logic circuit that performs an OR operation. The OR logic circuit may output a “predec” signal PREDEC as the first voltage VDDH based on the result of the OR operation.

However, the drain of the fifth NMOS transistor MN5may be connected to the source of the sixth NMOS transistor MN6, and a third voltage VSS may be connected to the drain of the sixth NMOS transistor MN6. The fifth NMOS transistor MN5may receive a row address signal ROW_ADDR having a second voltage VDDL as a gate voltage, and the sixth NMOS transistor MN6may receive the internal clock signal ICK having the first voltage VDDH as a gate voltage. For example, the fifth and sixth NMOS transistors MN5and MN6may form an AND logic circuit that performs an AND operation. The AND logic circuit may ground the “predec” signal PREDEC to as low as the third voltage VSS based on the result of the AND operation.

Referring toFIG.16, in a case where a memory device1is in the low-power operation mode, the row address signal ROW_ADDR having the first voltage VDDH and the internal clock signal ICK having the first voltage VDDH are provided to the gates of the third and fourth PMOS transistors MP3and MP4and the gate of the sixth NMOS transistor MN6. However, the internal clock signal ICK having the second voltage VDDL is provided to the gate of the fifth NMOS transistor MN5. In this case, as signals having a relatively high voltage (i.e., the first voltage VDDH) are provided to the gates of the third and fourth PMOS transistors MP3and MP4and the gate of the sixth NMOS transistor MN6, the amount of time that it takes to connect (or turn on) and disconnect (or turn off) the source and drain of each of the third and fourth PMOS transistors MP3and MP4and the sixth NMOS transistor MN6can be reduced. On the contrary, as a signal having a relatively low voltage (i.e., the second voltage VDDL) is provided to the gate of the fifth NMOS transistor MN5, the amount of time that it takes to connect (or turn on) and disconnect (or turn off) the source and drain of the fifth NMOS transistor MN5increases relatively. Thus, the operating speed of the memory device1may become slower in the low-speed operation mode than in the high-speed operation mode. However, as the second voltage VDDL, which is relatively low, is provided to a peripheral circuit200, the power consumption of the memory device1can be reduced.

For example, the internal clock signal ICK provided to the gate of the fourth PMOS transistor MP4may be generated from second level shifter330, while the row address ROW_ADDR provided to the gate of the third PMOS transistor MP3may be generated from the first level shifter320. Furthermore, the row address signal ROW_ADDR provided to the gate of the fifth NMOS transistor MN5may be generated from the address latch210, while the internal clock signal ICK provided to the gate of the sixth NMOS transistor MN6may be generated from the second level shifter330.

The operation of the memory device according to some example embodiments described with reference toFIG.16may be similar to the operation of the memory device according to some example embodiments described with reference toFIG.15. For example, as a signal having the second voltage VDDL is applied to only one of the fifth and sixth NMOS transistors MN5and MN6, the effect of delaying the rise of the wordline voltage VDDH can be slightly reduced, but due to the presence of only one level shifter, some example embodiments described with reference toFIG.16may be beneficial in terms of integration density.

A memory device according to some example embodiments of inventive concepts will hereinafter be described.

FIG.17is a block diagram of a memory device according to some embodiments of inventive concepts.FIG.18is a block diagram for explaining a wordline predecoder ofFIG.17.FIG.19is a circuit diagram for explaining the wordline predecoder ofFIG.17in a case where the memory device ofFIG.17is set to a low-power operation mode.

Referring toFIG.17, a memory device2may include a memory circuit100, a peripheral circuit200, and a predecoder circuit500. The predecoder circuit500may include a wordline predecoder (“WL PREDECODER”)510and a level shifter520. The wordline predecoder510may receive a row address signal ROW_ADDR from an address latch210, may receive an internal clock signal ICK from an internal clock signal generator220, and may generate a “predec” signal PREDEC based on the row address signal ROW_ADDR and the internal clock signal ICK. The level shifter520may receive the internal clock signal ICK from the internal clock signal generator220, may level-shift the internal clock signal ICK, and may provide the level-shifted internal clock signal ICK to the wordline predecoder510. The wordline predecoder510may be directly connected to the internal clock signal generator220to receive the internal clock signal ICK, or may receive the level-shifted internal clock signal ICK from the level shifter520. The wordline predecoder510may be directly connected to the address latch210to receive the row address signal ROW_ADDR. For example, the wordline predecoder510may receive an internal clock signal ICK having a first voltage VDDH or an internal clock signal ICK having a second voltage VDDL and may also receive a row address signal ROW_ADDR having the first voltage VDDH.

Referring toFIG.18, the row address signal ROW_ADDR may be provided to the wordline predecoder510as the first voltage VDDH, and the internal clock signal ICK may be provided to the wordline predecoder510as a dual voltage consisting of or including the first and second voltages VDDH and VDDL. The row address signal ROW_ADDR having the first voltage VDDH may be provided from the address latch210to the wordline predecoder510. On the contrary, the internal clock signal ICK having the second voltage VDDL may be provided from the internal clock signal generator220to the wordline predecoder510, and an internal clock signal ICK level-shifted from the second voltage VDDL to the first voltage VDDH by the level shifter520may be provided to the wordline predecoder510.

Referring toFIG.19, the wordline predecoder510may include a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8. The first voltage VDDH may be provided to the sources of the fifth and sixth PMOS transistors MP5and MP6. The drains of the fifth and sixth PMOS transistors MP5and MP6may be electrically connected to each other. The fifth and sixth PMOS transistors MP5and MP6may receive the row address signal ROW_ADDR having the first voltage VDDH and the internal clock signal ICK having the first voltage VDDH as their gate voltages. For example, the fifth and sixth PMOS transistors MP5and MP6may form an OR logic circuit that performs an OR operation. The OR logic circuit may output a “predec” signal PREDEC as the first voltage VDDH based on the result of the OR operation.

On the contrary, the drain of the seventh NMOS transistor MN7may be connected to the source of the eighth NMOS transistor MN8, and a third voltage VSS may be connected to the drain of the eighth NMOS transistor MN8. The seventh NMOS transistor MN7may receive the row address signal ROW_ADDR having the second voltage VDDL as a gate voltage, and the eighth NMOS transistor MN8may receive the internal clock signal ICK having the second voltage VDDL as a gate voltage. That is, the seventh and eighth NMOS transistors MN7and MN8may form an AND logic circuit that performs an AND operation. The AND logic circuit may ground the “predec” signal PREDEC to as low as the third voltage VSS based on the result of the AND operation.

Referring toFIG.19, in a case where the memory device2is in the low-power operation mode, the row address signal ROW_ADDR having the first voltage VDDH and the internal clock signal ICK having the first voltage VDDH are provided to the gates of the fifth and sixth PMOS transistor MP5and MP6and the gate of the seventh NMOS transistor MN7. On the contrary, the internal clock signal ICK having the second voltage VDDL is provided to the gate of the eighth NMOS transistor MN8. In this case, as signals having a relatively high voltage (i.e., the first voltage VDDH) are provided to the gates of the fifth and sixth PMOS transistors MP5and MP6and the gate of the seventh NMOS transistor MN7, the amount of time that it takes to connect (or turn on) and disconnect (or turn off) the source and drain of each of the fifth and sixth PMOS transistors MP5and MP6and the seventh NMOS transistor MN7can be reduced. On the contrary, as a signal having a relatively low voltage (i.e., the second voltage VDDL) is provided to the gate of the eighth NMOS transistor MN8, the amount of time that it takes to connect (or turn on) and disconnect (or turn off) the source and drain of the eighth NMOS transistor MN8increases relatively. Thus, the operating speed of the memory device2may become slower in the low-speed operation mode than in a high-speed operation mode. However, as the second voltage VDDL, which is relatively low, is provided to a peripheral circuit200, the power consumption of the memory device2can be reduced.

The operation of the memory device2may be similar to the operation of the memory device according to some example embodiments described with reference toFIG.15. That is, as a signal having the second voltage VDDL is applied to only one of the seventh and eighth NMOS transistors MN7and MN8, the effect of delaying the rise of the wordline voltage VDDH can be slightly reduced, but due to the presence of only one level shifter, some example embodiments described with reference toFIG.17may be beneficial in terms of integration density.

A memory device according to some embodiments of inventive concepts will hereinafter be described.

FIG.20is a block diagram of a memory device according to some embodiments of inventive concepts.FIG.21is a block diagram for explaining a wordline predecoder ofFIG.20.FIG.22is a circuit diagram for explaining the wordline predecoder ofFIG.20in a case where the memory device ofFIG.20is set to a low-power operation mode.

Referring toFIG.20, a memory device3may include a memory circuit100, a peripheral circuit200, and a predecoder circuit600. The predecoder circuit600may include a wordline predecoder (“WL PREDECODER”)610and a level shifter620. The wordline predecoder610may receive a row address signal ROW_ADDR from an address latch210, may receive an internal clock signal ICK from an internal clock signal generator220, and may generate a “predec” signal PREDEC based on the row address signal ROW_ADDR and the internal clock signal ICK. The level shifter620may receive the row address signal ROW_ADDR from the address latch210, may level-shift the row address signal ROW_ADDR, and may provide the level-shifted row address signal ROW_ADDR to the wordline predecoder610. The wordline predecoder610may be directly connected to the address latch210to receive the row address signal ROW_ADDR or may receive the level-shifted row address signal ROW_ADDR. The wordline predecoder610may be directly connected to the internal clock signal generator220to receive the internal clock signal ICK. That is, the wordline predecoder610may receive a row address signal ROW_ADDR having a first voltage VDDH or a row address signal ROW_ADDR having a second voltage VDDL and may also receive an internal clock signal ICK having the first voltage VDDH.

Referring toFIG.21, the row address signal ROW_ADDR may be provided to the wordline predecoder610as a dual voltage consisting of or including the first and second voltages VDDH and VDDL, and the internal clock signal ICK may be provided to the wordline predecoder610as the first voltage VDDH. The row address signal ROW_ADDR having the first voltage VDDH may be provided from the address latch210to the wordline predecoder610, and a row address signal ROW_ADDR level-shifted from the second voltage VDDL to the first voltage VDDH by the level shifter620may be provided to the wordline decoder610. On the contrary, the internal clock signal ICK having the first voltage VDDH may be provided from the internal clock signal generator220to the wordline predecoder610.

Referring toFIG.22, the wordline predecoder610may include a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth NMOS transistor MN9, and a tenth NMOS transistor MN10. The first voltage VDDH may be provided to the sources of the seventh and eighth PMOS transistors MP7and MP8. The drains of the seventh and eighth PMOS transistors MP7and MP8may be electrically connected to each other. The seventh and eighth PMOS transistors MP7and MP8may receive the row address signal ROW_ADDR having the first voltage VDDH and the internal clock signal ICK having the first voltage VDDH as their gate voltages. That is, the seventh and eighth PMOS transistors MP7and MP8may form an OR logic circuit that performs an OR operation. The OR logic circuit may output a “predec” signal PREDEC as the first voltage VDDH based on the result of the OR operation.

On the contrary, the drain of the ninth NMOS transistor MN9may be connected to the source of the tenth NMOS transistor MN10, and a third voltage VSS may be connected to the drain of the tenth NMOS transistor MN10. The ninth NMOS transistor MN9may receive the row address signal ROW_ADDR having the second voltage VDDL as a gate voltage, and the tenth NMOS transistor MN10may receive the internal clock signal ICK having the second voltage VDDL as a gate voltage. That is, the ninth and tenth NMOS transistors MN9and MN10may form an AND logic circuit that performs an AND operation. The AND logic circuit may ground the “predec” signal PREDEC to as low as the third voltage VSS based on the result of the AND operation.

Referring toFIG.22, in a case where the memory device3is in the low-power operation mode, the row address signal ROW_ADDR having the first voltage VDDH and the internal clock signal ICK having the first voltage VDDH are provided to the gates of the seventh and eighth PMOS transistor MP7and MP8and the gate of the tenth NMOS transistor MN10. On the contrary, the internal clock signal ICK having the second voltage VDDL is provided to the gate of the ninth NMOS transistor MN9. In this case, as signals having a relatively high voltage (i.e., the first voltage VDDH) are provided to the gates of the seventh and eighth PMOS transistors MP7and MP8and the gate of the tenth NMOS transistor MN10, the amount of time that it takes to connect (or turn on) and disconnect (or turn off) the source and drain of each of the seventh and eighth PMOS transistors MP7and MP8and the tenth NMOS transistor MN10can be reduced. On the contrary, as a signal having a relatively low voltage (i.e., the second voltage VDDL) is provided to the gate of the ninth NMOS transistor MN9, the amount of time that it takes to connect (or turn on) and disconnect (or turn off) the source and drain of the ninth NMOS transistor MN9increases relatively. Thus, the operating speed of the memory device3may become slower in the low-speed operation mode than in a high-speed operation mode. However, as the second voltage VDDL, which is relatively low, is provided to a peripheral circuit200, the power consumption of the memory device3can be reduced.

The operation of the memory device3may be similar to the operation of the memory device according to example embodiments described with reference toFIG.15. For example as a signal having the second voltage VDDL is applied to only one of the ninth and tenth NMOS transistors MN9and MN10, the effect of delaying the rise of the wordline voltage VDDH can be slightly reduced, but due to the presence of only one level shifter, example embodiments described with reference toFIG.20may be beneficial in terms of integration density.

FIG.23is a block diagram of a mobile terminal, to which embodiments of inventive concepts are applicable.

Referring toFIG.23, a mobile terminal1000includes an image processing unit1100, a radio transmission/reception unit1200, an audio processing unit1300, an image file generation unit1400, a nonvolatile memory device (“NVM”)1500, a user interface1600, and a controller1700.

The image processing unit1100includes a lens1110, an image sensor1120, an image processor1130, and a display unit1140. The radio transmission/reception unit1200includes an antenna1210, a transceiver1220, and a modem1230. The audio processing unit1300includes an audio processor1310, a microphone1320, and a speaker1330.

The mobile terminal1000may include various semiconductor devices. An application processor that performs the functions of the controller1700is required to exhibit high performance while consuming less power. Accordingly, the controller1700may be provided as a multicore through a miniaturization process. The controller1700may include an SRAM1750, which is equipped with a wordline predecoder according to some example embodiments of inventive concepts. Even though the SRAM1750is driven in a dual-voltage manner, a timing skew can be reduced, and/or a sufficient operating margin may be or be made more likely to be secured in connection with the input/output of data to/from memory cells.

A system-on-chip (SoC) according to some embodiments of inventive concepts may be formed using various types of packages. For example, the SoC may be include and/or be formed using at least one of package-on-package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual in-line package (PDIP), a die-in waffle pack, a die-in wafer form, a chip-on-board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat pack (MQFP), a thin quad flat pack (TQFP), a small outline integrated circuit (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a thin quad flat pack (TQFP), a system-in-package (SIP), a multi-chip package (MCP), a wafer-level fabricated package (WFP), or a wafer-level processed stack package (WSP).

Some example embodiments of inventive concepts have been described above with reference to the accompanying drawings, but inventive concepts are not limited thereto and may be implemented in various different forms. It will be understood that Invent inventive concepts can be implemented in other specific forms without changing the technical spirit or gist of inventive concepts. Furthermore example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include features described with reference to one or more figures, and may also include features described with reference to one or more other figures. Therefore, it should be understood that example embodiments set forth herein are illustrative in all respects and not limiting.