Apparatus of detecting capacitance

An apparatus of detecting capacitance detects a capacitance change of a capacitive sensor. The apparatus includes a pulse modulator configured to output a charging signal including at least one pulse. A switch is configured to charge the capacitive sensor according to the charging signal and output a discharging signal from the capacitive sensor. A discharging compensator is configured to output a discharging delay signal by compensating a voltage level of the discharging signal during a falling period of the discharging signal. A detector is configured to output a detection signal by detecting a region where the discharging delay signal has a voltage threshold. A controller is configured to detect the capacitance change by measuring a discharging time of the capacitive sensor according to the detection signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority to Korean Patent Application No. 10-2013-0153469 filed in the Korean Intellectual Property Office on Dec. 10, 2013, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to an apparatus of detecting capacitance. More particularly, the present disclosure relates to an apparatus of detecting capacitance that charges/discharges a capacitive sensor by a set number of times and prevents a malfunction according to a noise.

BACKGROUND

A capacitive sensor senses a capacitance change that occurs when a body or a particular object approaches. A traditional method for detecting the capacitance change induces charge into the capacitive sensor by using a large capacity capacitor and measures a time when a charging voltage of the capacitor becomes a reference voltage. The method as stated above needs be charged and discharged a number of times because an amount of induced charge into the capacitive sensor is small, and the capacitive sensor is affected by surrounding environment or noise.

Another traditional method for detecting a capacitance change induces charge into a capacitive sensor by a set number of times and measures a voltage change according to discharging time of induced charge. The method as stated above measure a discharging voltage of specific point of time, so that the discharging voltage is affected by surrounding environment or noise. As a result, the traditional methods have a possibility to misdetection of the capacitance change of the capacitive sensor.

SUMMARY

The present disclosure provides an apparatus of detecting capacitance having advantages of charging/discharging a capacitive sensor by a set number of times and preventing a malfunction according to a noise.

According to an exemplary embodiment of the present disclosure, an apparatus of detecting capacitance may include a pulse modulator configured to output a charging signal including at least one pulse. A switch is configured to charge a capacitive sensor according to the charging signal and output a discharging signal from the capacitive sensor. A discharging compensator is configured to output a discharging delay signal by compensating a voltage level of the discharging signal during a falling period of the discharging signal. A detector is configured to output a detection signal by detecting a region where the discharging delay signal has a voltage threshold. A controller is configured to detect the capacitance change by measuring a discharging time of the capacitive sensor according to the detection signal.

The pulse modulator may receive an input signal including at least one pulse from the controller and may output the charging signal by modulating a pulse width of the input signal.

The pulse modulator may include an inverter configured to output an inverting input signal by inverting the input signal. A delayer is configured to output an input delay signal by delaying the inverting input signal for a set period of time. A first negated and (NAND) gate is configured to output an output signal by executing a NAND operation of the input signal and the input delay signal. A second NAND gate is configured to output the charging signal by executing a NAND operation of the output signal and a high level signal.

The delayer may include a resistance having both ends, one end of the resistance connected to output end of the inverter. A capacitor includes one end connected to the other end of the resistance and the other end connected to a ground terminal.

The discharging compensator may receive a compensation signal including a pulse which has constant size from the controller, and may increase a voltage level of the discharging signal by using the compensation signal.

The discharging compensator may include a discharging delayer configured to output a compensation delay signal by delaying the compensation signal for a set period of time. An adder is configured to output the discharging delay signal by adding the discharging signal and the compensation delay signal.

The discharging delayer may include a resistance having both ends, the compensation signal being transmitted to one end of the resistance. A capacitor includes one end connected to the other end of the resistance and the other end connected to the ground terminal.

The detector may include a NAND gate configured to receive an input signal which has a pulse width corresponding to the voltage threshold and output the detection signal by executing the NAND operation of the input signal and the discharging delay signal.

The apparatus may further include a signal processor configured to output a voltage signal corresponding to a duty ratio of the detection signal. The signal processor may include a charge amplifier.

The controller may charge the capacitive sensor by a set number of times and may detect the capacitance change by using an average value of the discharging time about the set number of times.

An apparatus of detecting capacitance according to an exemplary embodiment of the present disclosure may decrease charging and discharging number of times since the capacitive sensor is charged and discharged by a predetermined number of times.

In addition, the apparatus of detecting capacitance according to an exemplary embodiment of the present disclosure may acquire strength against a noise by detecting a discharging signal of a voltage threshold after delaying a discharging time by increasing voltage level of the discharging signal from the capacitive sensor.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a circuit diagram of an apparatus of detecting capacitance according to an exemplary embodiment of the present disclosure. Referring toFIG. 1, an apparatus of detecting capacitance1according to an exemplary embodiment of the present disclosure include a pulse modulator10, a switch20, a discharging compensator30, a detector40, a signal processor50, and a controller60.

The pulse modulator10receives a first input signal INP1including at least one pulse from the controller60and output a charging signal CP by to modulating a pulse width the first input signal INP1. For example, a pulse width of the first input signal INP1may be approximately 200 μs, and a pulse width of the charging signal CP may be approximately 20 ns. In this regard, a charging time may be shortened if a capacitive sensor2is charged by the charging signal CP with a pulse shape.

The pulse modulator10includes an inverter INV, a delayer12, a first negated and (NAND) gate NAND1, and a second NAND gate NAND2. The inverter INV outputs an inverting input signal /INP1by inverting the first input signal INP1.

The delayer12outputs a first input delay signal INP1_D by delaying the inverting input signal /INP1for a set period of time. At this point, the delayer12controls a delaying time of the inverting input signal /INP1depending on a RC time constant. To this end, the delayer12includes a first resistance R1and a first capacitor C1. The first resistance R1includes one end connected to output end of the inverter INV and the other end connected to one end of the first capacitor C1. The other end of the first capacitor C1is connected to a ground terminal.

The first NAND gate NAND1outputs an output signal OUT by executing a NAND operation of the first input signal INP1and the first input delay signal INP1_D. The second NAND gate NAND2outputs the charging signal CP by executing NAND operation of the output signal OUT and a high level signal H.

The switch20controls charging and discharging of the capacitive sensor2depending on the charging signal CP. To this end, the switch20includes a switch SW. The switch SW connects a common terminal (com) connected to the capacitive sensor2to a discharging terminal (a) during a low level region of the charging signal CP. The switch SW connects a common terminal (com) to a charging terminal (b) during a high level region of the charging signal CR That is, if the common terminal (com) is connected to the discharging terminal (a), a discharging channel of the capacitive sensor2is formed, on the contrary, if the common terminal (com) is connected to the charging terminal (b), a charging channel of the capacitive sensor2is formed.

If the charging channel of the capacitive sensor2is formed, the capacitive sensor2is charged as a reference voltage level by receiving the charging signal CP from the pulse modulator10. On the contrary, if the discharging channel of the capacitive sensor2is formed, the capacitive sensor2is discharged and outputs a discharging signal DS. At this point, a discharging time of the discharging signal DS changes in accordance with changing a discharging amount when a body or a particular object approaches to the capacitive sensor2.

The discharging compensator30delays the discharging time of the discharging signal DS by compensating a voltage level of the discharging signal DS during a falling region of the discharging signal DS. In more detail, the discharging compensator30receives a compensation signal RES from the controller60and outputs a compensation delay signal DDS by increasing the voltage level of the discharging signal DS on the basis of the compensation signal RES. At this point, the compensation signal RES includes a pulse which has a constant size. The discharging compensator30includes a discharging delayer32and an adder34. The discharging delayer32receives the compensation signal RES from the controller60and outputs a compensation delay signal RES_D by delaying the compensation signal RES depending on a RC time constant.

The discharging delayer32includes a second resistance R2and a second capacitor C2. The second resistance R2includes one end receives the compensation signal RES and the other end connected to the second capacitor C2. The other end of the second capacitor C2is connected to ground terminal. In addition, the adder34outputs the compensation delay signal DDS by adding the discharging signal DS and the compensation delay signal RES_D.

The detector40receives a second input signal INP2and outputs a detection signal DETS by detecting a region where the compensation delay signal DDS has a voltage threshold depending on the second input signal INP2. For example, the detector40may detect a region where the compensation delay signal DDS has a range of 2.5-5 V. In this regard, the second input signal INP2has a pulse width corresponding to a maximum time that the compensation delay signal DDS may change as the voltage threshold. The detector40includes a third NAND gate NAND3. The third NAND gate NAND3outputs a detection signal DETS by executing NAND operation of the second input signal INP2and the discharging delay signal DDS.

The signal processor50outputs a voltage signal VDETS by converting an electric signal corresponding to a duty ratio of the detection signal DETS. To this end, the signal processor50includes a charge amplifier CAMP that converts an input charge amount to a voltage and amplifies a voltage level. The charge amplifier CAMP may adjust a sensitivity of an output signal about an input signal and prevent the voltage signal VDETS from being influencing by a noise.

The controller60generates a first input signal INP1, a second input signal INP2, and a compensation signal RES. The controller60transmits the first input signal INP1to the pulse modulator10, transmits the second input signal INP2to the detector40, and transmits the compensation signal RES to the discharging delayer32. In addition, the controller60detects a capacitance change of the capacitive sensor2by determining the voltage signal VDETS. The controller60may include an analog-digital converter (not shown) which converts the voltage signal VDETS to a digital format. For example, the controller60may measure a discharging time of the capacitive sensor2that the discharging delay signal DDS has the voltage threshold according to a voltage level of the voltage signal VDETS. The controller60may detect the capacitance change by comparing the measured discharging time with a set discharging standard time.

The discharging standard time means that the discharging delay signal DDS has the voltage threshold when the body or the particular object does not approach to the capacitive sensor2. That is, the controller60may determine that the body or the particular object approaches to the capacitive sensor2when the measured discharging time is longer than the discharging standard time. In addition, the controller60may charge the capacitive sensor2by a predetermined number of times and may measure the discharging time of the capacitive sensor2every number of times. The controller60may detect the capacitance change of the capacitive sensor2based on an average of the discharging time.

The apparatus of detecting capacitance1according to an exemplary embodiment of the present disclosure may be applied to a module for opening and closing a trunk of a vehicle when a driver approaches to the trunk of the vehicle. The controller60may transmit a data whether a body or a particular object approaches or not to a controller for opening and closing the trunk of the vehicle (not shown).

FIG. 2is a flowchart showing a method of detecting capacitance according to an exemplary embodiment of the present disclosure. Referring toFIG. 2, the pulse modulator10outputs a charging signal CP by modulating a pulse width the first input signal INP1. If the pulse modulator10outputs the charging signal CP, the charging channel of the capacitive sensor2is formed during the high level region of the charging signal CP, and the capacitive sensor2is charged through the charging channel at step S1.

After that, the discharging channel of the capacitive sensor2is formed during the low level region of the charging signal CP, and the capacitive sensor2is discharged through the discharging channel at step S2. At this time, a waveform of the discharging signal DS output from the capacitive sensor2changes when the body or the particular object approaches to the capacitive sensor2.

The discharging compensator30outputs the compensation delay signal DDS by compensating a voltage level of the discharging signal DS during a falling region of the discharging signal DS at step S3. After that, the detector40outputs the detection signal DETS by detecting a region where the compensation delay signal DDS has a voltage threshold depending on the second input signal INP2.

The signal processor50outputs the voltage signal VDETS depending on a duty ratio of the detection signal DETS, and the controller60measures the discharging time that the discharging delay signal DDS has the voltage threshold at step S4.

After that, the controller60determines whether to measure the discharging time by a set number of times at step S5. If the discharging time is not measured by the set number of times, the controller60returns a process to the step S1and performs the process again.

On the other hand, if the discharging time is measured by the set number of times, the controller60detects the capacitance change of the capacitive sensor2by using an average of the discharging time measured by the set number of times.

FIG. 3is a operation timing chart of an apparatus of detecting capacitance according to an exemplary embodiment of the present disclosure. Referring toFIG. 3, the controller60generates the first input signal INP1and outputs first input signal INP1at a point of time P1. The inverter INV outputs the inverting input signal /INP1by inverting the first input signal INP1, the delayer12outputs the first input delay signal INP1_D by delaying the inverting input signal /INP1. Then, the first NAND gate NAND1outputs the output signal OUT by executing a NAND operation of the first input signal INP1and the first input delay signal INP1_D. In addition, the second NAND gate NAND2outputs the charging signal CP by executing a NAND operation of the output signal OUT and a high level signal H.

At this time, the switch SW connects the common terminal (com) to the charging terminal (b) during a high level region of the charging signal CP. If the common terminal (com) and the charging terminal (b) are connected, the capacitive sensor2is charged as a predetermined voltage level depending on the charging signal CP. After that, the charging signal CP drops from the high level region to the low level region, and the switch SW connects the common terminal (com) to the discharging terminal (a) at a point of time P2. As a result, the capacitive sensor2is discharged, so the discharging signal DS is output.

The controller60generates the compensation signal RES and outputs the compensation signal RES at a point of time P3. The discharging delayer32outputs the compensation delay signal RES_D by delaying the compensation signal RES. If the compensation delay signal RES_D is output, the adder34outputs the compensation delay signal DDS by adding the discharging signal DS and the compensation delay signal RES_D. Then, the controller60generates the second input signal INP2and outputs the second input signal INP2at a point of time P4. If the second input signal INP2is output, the third NAND gate NAND3outputs the detection signal DETS by executing NAND operation of the second input signal INP2and the discharging delay signal DDS.

The signal processor50outputs the voltage signal VDETS depending on a duty ratio of the detection signal DETS, and the controller60measures the discharging time of the capacitive sensor2by using the voltage signal VDETS. After that, the operation as described above is repeated by a predetermined number of times, for example four times. The controller60detects capacitance change of the capacitive sensor2by using an average of the discharging time of the capacitive sensor2measured by four times.