Switch fabric packet flow reordering

An ingress fabric endpoint coupled to a switch fabric within a network device reorders packet flows based on congestion status. In one example, the ingress fabric endpoint receives packet flows for switching across the switch fabric. The ingress fabric endpoint assigns each packet for each packet flow to a fast path or a slow path for packet switching. The ingress fabric endpoint processes, to generate a stream of cells for switching across the switch fabric, packets from the fast path and the slow path to maintain a first-in-first-out ordering of the packets within each packet flow. The ingress fabric endpoint switches a packet of a first packet flow after switching a packet of a second packet flow despite receiving the packet of the first packet flow before the packet of the second packet flow.

TECHNICAL FIELD

The disclosure relates to computer networks and, more particularly, to communicating packets within computer networks.

BACKGROUND

A computer network is a collection of interconnected computing devices that can exchange data and share resources. In a packet-based network, such as an Ethernet network, the computing devices communicate data by dividing the data into variable-length blocks called packets, which are individually routed across the network from a source device to a destination device. The destination device extracts the data from the packets and assembles the data into its original form.

Certain devices, referred to as routers, maintain routing information representative of a topology of the network. The routers exchange routing information so as to maintain an accurate representation of available routes through the network. A “route” can generally be defined as a path between two locations on the network. Upon receiving an incoming data packet, a router examines information within the packet, often referred to as a “key,” to select an appropriate next hop to which to forward the packet in accordance with the routing information.

A variety of types of routers exist within the Internet. Network Service Providers (NSPs), for example, maintain “edge routers” to provide Internet access and other services to the customers. Examples of services that the NSP may provide include Voice over IP (VoIP), access for Asynchronous Transfer Mode (ATM) or frame relay communications, Internet protocol (IP) data services, and multimedia services, such as video streaming. The edge routers of the NSPs often communicate network traffic to high-speed “core routers,” which may be generally viewed as forming the backbone of the Internet. These core routers often include substantially more processing resources than the edge routers and are designed to handle high volumes of network traffic.

In some examples, a core router or another router or switching device may employ a distributed, multi-stage switch fabric architecture, in which network packets traverse multiple stages of the switch fabric located in distributed forwarding components of the router to travel from an ingress point of the switch fabric to an egress point of the switch fabric. As one example, a switch fabric may be implemented as a single multi-stage Clos switch fabric, which relays packets across the stages of the switch fabric. A typical multi-stage Clos switch fabric has a plurality of switches interconnected to form a plurality of stages. In a typical arrangement, the switch fabric includes an ingress (or “first”) stage, one or more intermediate stages, and an egress (or “final”) stage, with each stage having one or more switches (e.g., crossbar switches—often referred to more simply as “crossbars”). Moreover, the switch fabric may be implemented such that the switches are arranged as multiple parallel fabric planes that each provide independent forwarding from ingress ports to egress ports through the multiple stages, one or more of which may be treated as a spare fabric plane. In other words, each of the parallel fabric planes may viewed as an independent portion of the multi-stage Clos switch fabric, where each plane provides switching redundancy.

A switch fabric switches packets among multiple fabric endpoints. Typically, each fabric endpoint is able to use the switch fabric to reach and send packets to any other fabric endpoint connected to the switch fabric. In some examples, fabric endpoints exchange data units known as “cells,” with each cell having a sequence number that defines a position of the cell in a sequence of cells. The sequence of cells from an ingress fabric endpoint to an egress fabric endpoint is known as a cell stream.

SUMMARY

In general, techniques are described for reordering, to produce a cell stream, packets from packets flows based on a congestion status of each packet flow to allow packets of uncongested packet flows to bypass packets of congested packet flows in the cell stream. An ingress fabric endpoint receives a plurality of packet flows and processes the packet flows to generate a stream of discrete data units known as “cells,” for switching across the switch fabric to an egress fabric endpoint. The ingress fabric endpoint stamps each cell with a sequence number that defines a position of the cell in a sequence of cells that forms a cell stream to a particular egress fabric endpoint. The packets within a particular packet flow should be processed by the ingress fabric endpoint and switched to the egress fabric endpoint according to a first-in-first-out (FIFO) ordering of the packets to ensure integrity of the packet flow. The techniques described herein permit a non-FIFO ordering for packets from different packet flows.

For example, an ingress fabric endpoint coupled to a switch fabric within a network device may use a congestion status of a packet flow to assign packets of the packet flow to a fast path for packet switching or a slow path for packet switching to allow packets of uncongested packet flows to bypass packets of congested packet flows. The ingress fabric endpoint receives packet flows for switching across the switch fabric to an egress fabric endpoint. The ingress fabric endpoint assigns packets for each packet flow of the received packet flows to one of a fast path for packet switching or a slow path for packet switching based at least on a congestion status of the packet flow. In some examples, the fast path uses an internal memory of the network device to buffer packets for internal switching, while the slow path uses an external memory of the network device for internal switching.

The ingress fabric endpoint processes packets from the fast path and the slow path to generate a stream of cells for switching across the switch fabric to the egress fabric endpoint while maintaining a FIFO ordering of the packets within each packet flow but not a FIFO ordering of packets of different packet flows. In this way, the ingress fabric endpoint preserves the correct ordering of packets within each packet flow but allows packets of uncongested packet flows, assigned to the fast path, to bypass packets of congested packet flows, assigned to the slow path, to prevent the congested packet flows from impacting the throughput of uncongested packet flows.

The packet reordering techniques described herein may provide one or more specific technical improvements to the computer-related field of network traffic forwarding. For example, because a fabric endpoint can reorder packets of a packet flow with respect packets of other packet flows, the techniques may improve the throughput of the network device by allowing packets of uncongested packet flows to bypass packets of congested packet flows, which would otherwise block packets of uncongested packet flows under a strict FIFO ordering. Further, the techniques of the disclosure may allow a fabric endpoint to efficiently use both low-latency, internal memory and expandable, higher-latency external memory so as to improve the scalability of the fabric endpoint by increasing the number of simultaneous packet flows that the fabric endpoint may process, without the fabric endpoint becoming bottlenecked by higher latencies imposed by the use of external memories. Accordingly, the techniques of the disclosure may lead to improved packet flow throughput, more efficient usage of memory of the network device, and better resource utilization overall.

In some examples, a method is described comprising: receiving, by an ingress fabric endpoint of a plurality of fabric endpoints coupled to a switch fabric within a network device to exchange cells, a plurality of packet flows for switching across the switch fabric to an egress fabric endpoint of the plurality of fabric endpoints for the packet flows; assigning, by the ingress fabric endpoint, each packet for each packet flow of the plurality of packet flows to one of a fast path for packet switching or a slow path for packet switching; and processing, by the ingress fabric endpoint to generate a stream of cells for switching across the switch fabric to the egress fabric endpoint, packets from the fast path and the slow path to maintain a first-in-first-out ordering of the packets within each packet flow of the plurality of packet flows and to switch a packet of a first packet flow of the packet flows after switching a packet of a second packet flow of the packet flows despite the packet of the first packet flow being received by the ingress fabric endpoint before the packet of the second packet flow.

In some examples, a network device is described comprising: a plurality of fabric endpoints coupled to a switch fabric within the network device to exchange cells, an ingress fabric endpoint of the plurality of fabric endpoints configured to: receive a plurality of packet flows for switching across the switch fabric to an egress fabric endpoint of the plurality of fabric endpoints for the packet flows; assign each packet for each packet flow of the plurality of packet flows to one of a fast path for packet switching or a slow path for packet switching; and process, to generate a stream of cells for switching across the switch fabric to the egress fabric endpoint; packets from the fast path and the slow path to maintain a first-in-first-out ordering of the packets within each packet flow of the plurality of packet flows and to switch a packet of a first packet flow of the packet flows after switching a packet of a second packet flow of the packet flows despite the packet of the first packet flow being received by the ingress fabric endpoint before the packet of the second packet flow.

In some examples, a non-transitory, computer-readable medium is described comprising instructions that, when executed, are configured to cause one or more processors of a network device to execute an ingress fabric endpoint of a plurality of fabric endpoints coupled to a switch fabric within the network device to exchange cells, the ingress fabric endpoint configured to: receive a plurality of packet flows for switching across the switch fabric to an egress fabric endpoint of the plurality of fabric endpoints for the packet flows; assign each packet for each packet flow of the plurality of packet flows to one of a fast path for packet switching or a slow path for packet switching; and process, to generate a stream of cells for switching across the switch fabric to the egress fabric endpoint, packets from the fast path and the slow path to maintain a first-in-first-out ordering of the packets within each packet flow of the plurality of packet flows and to switch a packet of a first packet flow of the packet flows after switching a packet of a second packet flow of the packet flows despite the packet of the first packet flow being received by the ingress fabric endpoint before the packet of the second packet flow.

Like reference characters denote elements throughout the figures and text.

DETAILED DESCRIPTION

FIG. 1is a block diagram illustrating an example network environment in which a service provider network includes a network device configured to perform fabric reordering in accordance with techniques described in this disclosure. For purposes of example, the principles of the invention are described with respect to a simplified network environment2ofFIG. 1in which network device4communicates with edge routers5A and5B (“edge routers5”) to provide customer networks8A-8C (“customer networks8”) with access to service provider network6. Network device4may represent a router that exchanges routing information with edge routers5in order to maintain an accurate representation of the topology of network environment2. Network device4may consist of a plurality of cooperative routing components operating as a single node within service provider network6. Network device4may alternatively represent an L2 and/or L3 switch, or any other device that includes an internal switching fabric for internally switching packets among fabric endpoints of the device.

Although not illustrated, service provider network6may be coupled to one or more networks administered by other providers and may thus form part of a large-scale public network infrastructure, e.g., the Internet. Consequently, customer networks8may be viewed as edge networks of the Internet. Service provider network6may provide computing devices within customer networks8with access to the Internet and may allow the computing devices within customer networks8to communicate with each other. In another example, service provider network6may provide network services within the core of the Internet. In either case, service provider network6may include a variety of network devices (not shown) other than network device4and edge routers5, such as additional routers, switches, servers, or other devices.

In the illustrated example, edge router5A is coupled to customer network8A via access link9A, and edge router5B is coupled to customer networks8B and8C via access links9B and9C, respectively. Customer networks8may be networks for geographically separated sites of an enterprise. Customer networks8may include one or more computing devices (not shown), such as personal computers, laptop computers, handheld computers, workstations, servers, switches, printers, customer data centers or other devices. The configuration of network environment2illustrated inFIG. 1is merely an example. Service provider network6may be coupled to any number of customer networks8. Nonetheless, for ease of description, only customer networks8A-8C are illustrated inFIG. 1. Many different types of networks besides service provider network may employ an instance of network device4, including customer/enterprise networks, transport networks, aggregation or access networks, and so forth.

Network device4may include multiple chassis (not shown inFIG. 1) that are physically coupled and configured to operate as a single router. In such examples and to edge routers5of network environment2, network device4appears as a single routing device. For example, although network device4may include a plurality of chassis, from the perspective of peer routers5, network device4has one or more unified host network addresses and maintains single peer routing sessions for each routing protocol maintaining peer routing sessions with each of the edge routers5. Additional details regarding an example of a multi-chassis router having a multi-stage switch fabric are found in Pradeep S. Sindhu, U.S. Patent Publ. No. 2008/0044181 A1, entitled “Multi-chassis router with multiplexed optical interconnects” and published Feb. 21, 2008, which is incorporated by reference in its entirety.

As described in further detail below, network device4forwards packets, i.e., network traffic, on a data plane of network device4using an internal multi-stage switch fabric12that interconnects fabric endpoints within the network device, the fabric endpoints themselves connected to network interface cards (e.g., port interface cards) of the network device. In other words, fabric endpoints in communication with the network interfaces switch packets to one another via the switch fabric12. In the example ofFIG. 1, the multi-stage switch fabric12switches data units from ingress fabric endpoints in communication with ingress ports of the network interface cards to the egress fabric endpoints in communication with egress ports of the network interface cards to perform high-speed packet forwarding among the forwarding units of the network device4. Multi-stage switch fabric12may represent a 3-stage Clos network, a 5-stage Clos network, or an n-stage Clos network for any value of n. Fabric endpoints can be an ingress fabric endpoint for a given packet and an egress fabric endpoint for another given packet.

In general, fabric endpoints divide packets received at an ingress port into one or more fixed-length cells for switching. However, in some instances packets may be divided into variable-length data units for switching or switched intact as respective data units. A “data cell” or “cell” refers to a smallest block of data that is passed through the multi-stage switch fabric12. The cell includes a header portion and a data portion. “Cell data” refers to data contained within a data portion of a cell. The header portion includes at least a source identifier indicating the ingress fabric endpoint of the cell and a sequence number. As used throughout this description unless specifically indicated otherwise, “cell” may refer to any unit of data switched by a multi-stage switch fabric.

The multi-stage switch fabric12offers multiple possible switch paths between each ingress fabric endpoint and an egress fabric endpoint to facilitate non-blocking switching. As a result of the differing latencies that individual cells may experience across the multiple paths that are available from an ingress fabric endpoint to an egress fabric endpoint, cells received at the egress fabric endpoint may arrive out of order relative to the sequence in which the cells were dispatched by the ingress fabric endpoint. The egress fabric endpoint therefore reorders the cells prior to processing in order to process the cells in the correct ordering. As noted above and to facilitate reordering, each cell includes a sequence number field. A fabric endpoint may receive a different stream of cells (“cell stream”) from each fabric endpoint of network device, including at least in some cases from the fabric endpoint itself.

In accordance with techniques described herein, network device4reorders, to produce a cell stream, packets from packets flows based on a congestion status of each packet flow to allow packets of uncongested packet flows to bypass packets of congested packet flows in the cell stream. As explained in further detail below, an ingress fabric endpoint (not depicted inFIG. 1) of network device4receives a plurality of packet flows and processes the packet flows to generate a stream of discrete data units known as “cells,” for switching across the switch fabric to an egress fabric endpoint of network device4(not depicted inFIG. 1). The ingress fabric endpoint stamps each cell with a sequence number that defines a position of the cell in a sequence of cells that forms a cell stream to a particular egress fabric endpoint. The packets within a particular packet flow should be processed by the ingress fabric endpoint and switched to the egress fabric endpoint according to a FIFO ordering of the packets to ensure integrity of the packet flow. The techniques described herein permit a non-FIFO ordering for packets from different packet flows.

For example, an ingress fabric endpoint coupled to a switch fabric within network device4may use a congestion status of a packet flow to assign packets of the packet flow to a fast path for packet switching or a slow path for packet switching to allow packets of uncongested packet flows to bypass packets of congested packet flows. The ingress fabric endpoint receives packet flows for switching across the switch fabric to an egress fabric endpoint of network device4. The ingress fabric endpoint assigns packets for each packet flow of the received packet flows to one of a fast path for packet switching or a slow path for packet switching based at least on a congestion status of the packet flow. In some examples, the fast path uses an internal memory of network device4to buffer packets for internal switching, while the slow path uses an external memory of network device4for internal switching.

The ingress fabric endpoint processes packets from the fast path and the slow path to generate a stream of cells for switching across the switch fabric to the egress fabric endpoint while maintaining a FIFO ordering of the packets within each packet flow but not a FIFO ordering of packets of different packet flows. In this way, the ingress fabric endpoint preserves the correct ordering of packets within each packet flow but allows packets of uncongested packet flows, assigned to the fast path, to bypass packets of congested packet flows, assigned to the slow path, to prevent the congested packet flows from impacting the throughput of uncongested packet flows.

The packet reordering techniques described herein may provide one or more specific technical improvements to the computer-related field of network traffic forwarding. For example, because a fabric endpoint can reorder packets of a packet flow with respect to packets of other packet flows, the techniques may improve the throughput of network device4by allowing packets of uncongested packet flows to bypass packets of congested packet flows, which would otherwise block packets of uncongested packet flows under a strict FIFO ordering. Further, the techniques of the disclosure may allow a fabric endpoint to efficiently, use both low-latency, internal memory and expandable, higher-latency external memory so as to improve the scalability of the fabric endpoint by increasing the number of simultaneous packet flows that the fabric endpoint may process, without the fabric endpoint becoming bottlenecked by higher latencies imposed by the use of external memories. Accordingly, the techniques of the disclosure may lead to faster traffic flow throughput, more efficient usage of memory of the network device, and better resource utilization overall.

FIG. 2is a block diagram illustrating an example of a switching system according to techniques described herein. Multi-stage switch fabric18(“fabric18”) of switching system16may represent an example instance of multi-stage switch fabric12of the network device4ofFIG. 1. Fabric endpoints20A,20B (collectively, “fabric endpoints20”) of switching system16and separately coupled to each of fabric planes22A-22K of multi-stage switch fabric18operate as sources and/or destinations of data units (e.g., cells) switched by fabric18. In the illustrated example, ingress fabric endpoint20A sends, ingresses, originates, or otherwise sources packets26for switching via multi-stage switch fabric18to egress fabric endpoint20B that receives, egresses, consumes, or otherwise sinks packets26. AlthoughFIG. 2illustrates only two fabric endpoints, switching system16may include many hundreds of fabric endpoints, or more. In some examples, switching system16includes 96 fabric endpoints in communication with multi-stage switch fabric18. In such examples, any given fabric endpoint20may receive cells for cell streams sourced by 96 different fabric endpoints20.

Although each of fabric endpoints20typically operates as both an ingress and an egress for cells, any of fabric endpoints20may be either an ingress or an egress for cells in various instances. In some examples, fabric endpoints20may each represent a packet forwarding engine or other forwarding unit such that fabric endpoints20collectively implement a distributed forwarding plane for a packet switching device (e.g., network device4). In some examples, fabric endpoints20may represent fabric interfaces for servers or other hosts (e.g., virtual machines) that exchange packets for a distributed application via fabric18. Fabric endpoints20may include respective switch fabric interfaces or “switch interfaces” (SIs—not shown) to provide queuing for cells being switched via fabric18, among other operations.

In this example, multi-stage switch fabric18includes a plurality of operationally independent, parallel switch fabric planes22A-22K (illustrated as “fabric planes22A-22K”) and referred to herein collectively as “fabric planes22”). The number of fabric planes22may be any number, dependent upon the respective capacities of the fabric planes22and the fabric bandwidth needed. Fabric planes22may include 4, 5, or 18 planes, for instance. In some examples, fabric plane22K operates as a backup or spare fabric plane to the remaining fabric planes22. Each of fabric planes22includes similar components for implementing an independent Clos or other multi-stage switch network (e.g., a Benes network) to provide independent switching bandwidth to fabric endpoints20, said components and functionality being described hereinafter primarily with respect to fabric plane22A. Fabric planes22are operationally independent in that a failure of one of fabric planes22does not affect the switching ability of the remaining, operational fabric planes. Each of fabric planes22may provide non-blocking connectivity. Additional details regarding an example of a multi-stage switch fabric having a plurality of switch planes are found in Pradeep S. Sindhu, U.S. Pat. No. 7,102,999, entitled “Switching Device” and filed Nov. 24, 1999, which is incorporated by reference in its entirety.

Each of fabric planes22includes an input port coupled to fabric endpoint20A and an output port coupled to fabric endpoint20B. Although only one ingress fabric endpoint20A and one egress fabric endpoint20B is illustrated for simplicity, each fabric plane22typically includes multiple input ports and output ports coupled to respective fabric endpoints. When a fabric endpoint20A obtains a packet, the fabric endpoint20A performs a lookup operation to determine fabric endpoint20B (in this example) is an egress for the packet. Obtaining a packet may refer to receiving a packet from the network or host, or originating a packet, for instance. Fabric endpoint20A optionally divides the packet into cells and forwards the packet/cells across multi-stage fabric18to fabric endpoint20B. Fabric endpoint20A selects different fabric planes22to switch the cells to distribute the bandwidth load across the fabric planes22.

Fabric endpoints20A,20B may employ a request/grant protocol to transmit a data cell across fabric18. In such cases, ingress fabric endpoint20A transmits a request across fabric18to the egress fabric endpoint20B. Fabric endpoint20A transmits each such request across a different one of fabric planes22in a round-robin or other balancing order to fairly distribute the transport load. In response to receiving the request, fabric endpoint20B transmits a grant to the fabric endpoint20A across the same fabric plane22on which fabric endpoint20B received the corresponding request. In response to receiving the grant, fabric endpoint20A transmits the data cell to the fabric endpoint20B across the same fabric plane22on which fabric endpoint20A issued the corresponding request.

As noted above, each of fabric planes22may include similar components to perform similar multi-stage switch functionality. Fabric plane22A, as an example, includes a plurality of fabric chips24coupled by fabric chip-to-chip links (CCLs—not shown) to implement a multi-stage switch fabric for the fabric plane224. Fabric chips24A may be distributed among various switching devices, chassis, etc., of the switching system16. Each of fabric chips24A may include an application-specific integrated circuit (ASIC) and may be referred to as a “fabric ASIC.” Each fabric chip may perform the switching functionality for one or more stage switches and may represent, e.g., a crossbar switch.

In some examples, fabric endpoints20A-20B include respective fabric reorder modules to reorder cells received from other fabric endpoints20. For instance, fabric endpoint20B operating as an egress fabric endpoint receives, from ingress fabric endpoint20A, cells in a disordered sequence according to the sequence numbers of the cells and according to the times as which cells were sent by ingress fabric endpoint20A, which incrementally increases the sequence number with each cell sent for the cell stream to a particular egress fabric endpoint (here, fabric endpoint20B). Fabric endpoint20B may perform cell reordering on different subsequences of a cell stream, to detect missing or skipped cells, and to detect and facilitate robust recovery from other error conditions. Additional information on cell reordering may be found in U.S. Pat. No. 9,866,427 to Yadav, et al., entitled “MULTI-STAGE SWITCH FABRIC FAULT DETECTION AND HANDLING,” filed on Feb. 16, 2015 and issued on Jan. 9, 2018, the entire content of which is incorporated herein by reference.

In accordance with the techniques of the disclosure, fabric endpoints20A-20B include respective sequence modules30A-30B (collectively, “sequence modules30”) use a congestion status of a packet flow to assign packets of the packet flow to a fast path for packet switching or a slow path for packet switching to allow packets of uncongested packet flows to bypass packets of congested packet flows. Ingress fabric endpoint20A receives packet flows for switching across switch fabric18to egress fabric endpoint20B. Sequence module30A of ingress fabric endpoint20A assigns packets for each packet flow of the received packet flows to one of a fast path for packet switching or a slow path for packet switching based at least on a congestion status of the packet flow. In some examples, the fast path uses an internal memory of network device4to buffer packets for internal switching, while the slow path uses an external memory of network device4for internal switching.

Sequence module30A processes packets from the fast path and the slow path to generate a stream of cells for switching across switch fabric18to egress fabric endpoint20B while maintaining a FIFO ordering of the packets within each packet flow but not a FIFO ordering of packets of different packet flows. In this way, ingress fabric endpoint20A preserves the correct ordering of packets within each packet flow but allows packets of uncongested packet flows, assigned to the fast path, to bypass packets of congested packet flows, assigned to the slow path, to prevent the congested packet flows from impacting the throughput of uncongested packet flows.

The packet reordering techniques described herein may provide one or more specific technical improvements to the computer-related field of network traffic forwarding. For example, because a fabric endpoint can reorder packets of a packet flow with respect to packets of other packet flows, the techniques may improve the throughput of the network device by allowing packets of uncongested packet flows to bypass packets of congested packet flows, which would otherwise block packets of uncongested packet flows under a strict FIFO ordering. Further, the techniques of the disclosure may allow a fabric endpoint to efficiently use both low-latency, internal memory and expandable, higher-latency external memory so as to improve the scalability of the fabric endpoint by increasing the number of simultaneous packet flows that the fabric endpoint may process, without the fabric endpoint becoming bottlenecked by higher latencies imposed by the use of external memories. Further, ingress fabric endpoint20A may use high-speed internal memory to buffer uncongested packet flows so as to ensure that the uncongested packet flows are processed and forwarded to switch fabric18as quickly as possible. In contrast, ingress fabric endpoint20A may use slower-speed external memory to buffer congested packet flows which are not yet ready for processing and forwarding to switch fabric18.

FIG. 3is a block diagram illustrating a logical representation of a three-stage switching network150(or “switch fabric150”) that operates in accordance with techniques described herein. Three-stage network150may logically represent switch fabric12of FIG.1, switch fabric18ofFIG. 2, or another switch fabric in which components or devices are interconnected to provide a multi-stage switch fabric. The three stages of the example network150ofFIG. 3include: stage1151consisting of crossbar switches156A-156R (collectively “switches156”), stage2152consisting of crossbar switches158A-158M (collectively “switches158”), and stage3consisting of crossbar switches160A-160R (collectively “switches160”). Switches156receive data packets via inputs154N-154N (collectively “inputs154”), there are a total of N×R inputs154in this example. Switches160send the data packets via output ports162A-162N (collectively “outputs162”); there are a total of N×R outputs162in this example.

As shown inFIG. 3, stage1151and stage3153each include R crossbar switches, while stage2152includes M crossbar switches. Three-stage network in coupled to N inputs and N outputs, thus completing the characterization of the Clos network. The integer values for M and N define blocking characteristics of three-stage switching network150. For example, stage2152may include more crossbar switches than stage1151and stage3153(i.e., M>R) to reduce or eliminate the possibility that an open one of inputs154could be blocked from an open one of outputs162.

Each of switches156,158,160may be implemented by a fabric chip. In some cases, corresponding stage1switches156and stage3switches160(e.g., switch156A and switch160A) may be implemented by a same fabric chip. As described with respect to multi-chassis router150ofFIG. 3, stage1151and stage3153may be located in a plurality of LCCs, while stage2152is located in an SCC.

To establish a path through network150from one of inputs154to the intended output162, the one of switches156associated with the receiving input154determines an available stage2152switch158that allows a connection path to the stage3153switch160including the intended output162. For example, assume a packet received by switch156A is to be relayed to one of outputs162A on switch160A. Switch156A selects any of switches158with an open connection to both switch156A and switch160A. Assume switch156A selects switch158B. Once switch158B receives the data packet, switch158B determines an available path to switch160A and forwards the data packet to switch160A. For example, switch158B may have more than one open path to switch160A. An ingress fabric endpoint may use different open paths from one of inputs154to the intended output162to switch consecutive cells (by sequence number), each open path having a different latency. As a result, fabric cells for the cell sequence from the ingress fabric endpoint may arrive out of order at the egress fabric endpoint.

While generally described as a three-stage switch network such as network150, in other examples fabric planes described herein may contain different another type of switch architecture. For example, the second stage in a three-stage network may be replaced with another three-stage network, thereby forming a five-stage network.

FIG. 4is a flow diagram conceptual diagram illustrating different memory latencies for uncongested packet flows and congested packet flows received by an ingress fabric endpoint, in accordance with techniques described herein. A packet flow may be received as a set of data pointers, along with an Egress/Destination ID (fabric endpoint number) and a VOQ ID (virtual output queue/flow in the Destination fabric endpoint). Ingress fabric endpoint20A may send packet flows as cell streams across switch fabric18to multiple egress fabric endpoints20. As described herein, a packet flow here may represent network traffic destined to a virtual output queue (VOQ) of, e.g., egress fabric endpoint20B.

Packet data corresponding to packet flows to be transmitted from ingress fabric endpoint20A to egress fabric endpoint20B may be read from internal memory (e.g., on-chip SRAM) or from external memory (e.g., DRAM) and converted to cell streams for switching across switch fabric18. The internal or external memory may act as a buffer of ingress fabric endpoint20A for packet information such that ingress fabric endpoint20A fetches packet data from the internal or external memory prior to generating cell streams from the packet data for switching across switch fabric18to egress fabric endpoint20B. Ingress fabric endpoint20A may use an internal memory to store packet data for uncongested flows, while ingress fabric endpoint20A may use external memory to store packet data for congested flows. As described herein, a “congested packet flow” refers to a packet flow that has one or more delayed packets. Typically, a packet flow becomes congested when a queue somewhere along a network path for the packet flow is at capacity, which causes delays in the switching of packets for the packet flow from the network device or, more specifically, from ingress fabric endpoint20A to the egress fabric endpoint20for the packet flow.

Ingress fabric endpoint20A may track a congestion status for each packet flow. In some examples, ingress fabric endpoint20A track the congestion status of each packet flow by maintaining a queue length for packets of each received packet flow. Ingress fabric endpoint20A compares the queue length for a packet flow to a threshold to determine whether the packet flow is congested or uncongested. For example, upon determining that the queue length for the packet flow is less than the threshold, ingress fabric endpoint20A determines that the flow is uncongested. As another example, upon determining that the queue length for the packet flow is greater than the threshold, ingress fabric endpoint20A determines that the flow is congested. In some examples, the threshold is configurable by a user. Generally, ingress fabric endpoint20A stores data for all packet flows in an internal memory. Upon determining that a packet flow has become congested, ingress fabric endpoint20A switches data for the packet flow to an external memory, while data for other packet flows that are uncongested are continued to be stored in the internal memory.

Packet data switched by ingress fabric endpoint20A to egress fabric endpoint20B should honor particular ordering requirements. Specifically, ingress fabric endpoint20A should maintain an order of pages within a packet flow. However, ingress fabric endpoint20A may reorder an order of pages between different packet flows. To assist in reordering or buffering the flow data for transmission to egress fabric endpoint20B, sequence module30A processes packets of packet flows into a cell stream and assigns a sequence number to each cell of the cell stream prior to switching the cell stream across switch fabric18to egress fabric endpoint20B. Egress fabric endpoint20B uses the sequence number to reorder received cells to ensure that the order of the cell stream, and thus the order of packets within each packet flow represented in the cell stream, remains intact. The number of VOQs may be large, and therefore maintaining the sequence number per-VOQ (per-flow) may be prohibitively expensive to implement in hardware. Thus, as described herein, sequence module30A assigns sequence numbers per-fabric endpoint20(e.g., a set of VOQs) and maintains order per-fabric endpoint20.

In some examples, ingress fabric endpoint20A stores data for a single packet flow (managed using a VOQ for an egress fabric endpoint20) in either internal or external memory. Typically, the read latency of the external memory404is much higher, perhaps by multiple microseconds, than a read latency of the internal memory402. Thus, to process traffic flows in an efficient manner, ingress fabric endpoint20A may store data for uncongested traffic flows in the internal memory, while storing data for congested traffic flows in the external memory. In some examples, ingress fabric endpoint20A stores a sequence of data packets (e.g., for a single packet flow or for multiple packet flows) in a combination of internal and external memory. For example, ingress fabric endpoint20A stores a sequence of data packets for a single packet flow in both internal and external memory because a packet flow has transitioned from a congested to an uncongested state. Thus, different pages of a packet flow may have different latencies for reading data from a memory of ingress fabric endpoint20A, for some pages of the packet flow are buffered in internal memory, while other pages of the packet flow are buffered in external memory. As used herein, “pages” refers to memory pages to which packets are stored and is used herein to refer to the stored packets, and vice-versa. As depicted in the example ofFIG. 4, an ingress fabric endpoint receives a pointer for packet P0, which belongs to a first packet flow which is or has been congested. The ingress fabric endpoint, using the pointer for P0, reads the packet P0from an external memory for the ingress fabric endpoint. Shortly thereafter, the first packet flow becomes uncongested and packets for the first packet flow are stored to internal memory. The ingress fabric endpoint receives a pointer for packet P1, which also belongs to the first packet flow. The ingress fabric endpoint, using the pointer for P1, reads the packet P1from an internal memory of the ingress fabric endpoint due to the uncongested status of the first traffic flow. If all data in the first packet flow shares a single ordering sequence, because the sequence of the first packet flow includes some number of congested pages that are externally buffered (e.g., packet P0) and some number uncongested pages that are internally buffered (e.g., packet P1), packet P1may race ahead of packet P0. In other words, absent techniques described herein, due to latency differences between the internal and external memory for a conventional ingress fabric endpoint, the conventional ingress fabric endpoint would perform sequence number stamping406on packet P1prior to performing sequence number stamping406on earlier-in-time packet P0such that the ingress fabric endpoint would violate the ordering requirements for the first packet flow.

To honor the ordering sequence requirements, a conventional reorder engine of an egress fabric endpoint buffers and delays flow data for an uncongested page of a packet flow which may arrive multiple microseconds before a congested page of the packet flow is received due to the large read latency differences between the internal and external memories of the conventional ingress fabric endpoint. This may decrease overall performance and throughout of a conventional network device because the conventional network device must delay a first, uncongested packet flow due to the presence of a second, congested packet flow that may be unrelated to the first packet flow.

Alternatively, a conventional ingress fabric endpoint may delay an uncongested packet flow such that all packet flows are initially converted into cell streams in order. For example, a conventional ingress fabric endpoint may add an extra buffering cost to uncongested packet flows to preserve the cell stream order. However, this extra buffering cost causes undesirable jitter in uncongested flows. Further, to maintain performance, a conventional ingress fabric endpoint may be required to impose a delay on packet flow data stored on the internal memory that is as long as a latency of the external memory, which may dramatically reduce the speed at which a conventional ingress fabric endpoint may process and forward uncongested packet flows.

FIG. 5is a block diagram illustrating, in detail, an example of one of sequence modules30ofFIG. 2in accordance with the techniques of the disclosure. The example sequence module30ofFIG. 5may be an example of sequence module30A of ingress fabric endpoint20A or sequence module30B of ingress fabric endpoint20B ofFIG. 2.

The techniques of the disclosure recognize that if a sequentially first page of a first flow is to be read from external memory507and a sequentially second page of the first flow is to be read from internal memory, then the second page in the internal memory will be available first, even though the second page arrived later. This occurs due to considerable latency difference in read times between the internal and external memories. However, to ensure that the pages within the first flow maintain order, sequence module30should not read the second page from the internal memory until after reading the first page from the external memory. Furthermore, sequence module30may continue to forward pages for other, uncongested flows for the same fabric endpoint20to prevent blocking of other packet flows that do not need to maintain order with respect to the first flow. For example, if these other packet flows are stored in internal memory, then the other packet flows may progress in front of (and irrespective) of the first flow which has pages queued in external memory.

In accordance with the techniques of the disclosure, sequence module30segregates packet flows which have at least a one page in external memory from flows which have pages only in internal memory. For example, sequence module30implements two data paths for processing packet flows, referred to herein as a “fast path” and a “slow path.” As is described in more detail below, sequence module30assigns packets of uncongested packet flows to the fast path and packets of congested packet flows to the slow path so as to allow packets of the uncongested packet flows to be processed and switched across switch fabric18before congested packet flows assigned to the slow path.

As described herein, packet flows that have pages only in internal memory are referred to as “fast flows.” Typically, uncongested packet flows are stored only in internal memory, and therefore are typically fast flows. Packet flows that have pages stored in external memory are referred to as “slow external flows.” Typically, congested flows are stored only in external memory, and therefore are typically slow flows. Further, packet flows which have pages in external memory that have not yet been processed, but for which subsequent pages are stored in internal memory are referred to as “slow internal flows.” This scenario arises for packet flows that were originally congested, and therefore sequence module30originally assigned packets for the congested packet flows to the slow path in external memory. However, subsequently the packet flows became uncongested, such that sequence module30assigns subsequent packets for the packet flows to the fast path in internal memory. Without the techniques of the disclosure, as described above with respect toFIG. 4, the uncongested pages for the slow internal flows that are stored in internal memory may race ahead of the congested pages for the slow internal flows that are stored in external memory, breaking the sequence order for the flows.

In accordance with the techniques of the disclosure, upon reading pages from external memory for congested packet flows, sequence module30includes merge point520(also referred to as “multiplexer520” or MUX520) for merging flows that traverse the fast path and slow path prior to sequence number assignment524. Merge point520occurs before fetching data from internal memory to allows for multiple processing threads to fetch data from internal memory, thereby further improving performance of sequence module30. Because the sequence numbers have already been stamped, mis-ordering by the use of the multiple threads may be prevented. Thus, sequence module30may subsequently reorder sequence of packets between different packet flows by delaying sequence number stamping of packets for congested packet flows until after sequence module30reads pages for congested packets from the external memory.

Further, using the techniques described herein, sequence module30may avoid misordering, prior to merge point520, of packets within a single packet flow which has a sequence of packets assigned to both the fast path and the slow path. For example, sequence module30receives, from packet source502, a plurality of packets for a plurality of packet flows. For each packet of each packet flow of the plurality of packet flows, sequence module30determines, at the start of transmission processing, whether to assign the packet to the fast path for packet switching or the slow path for packet switching. For example, if a packet is indicated as externally buffered, sequence module30assigns the packet to the slow path and increments counter509for the packet flow. When the packet data for the packet assigned to the slow path is available, the packet buffered in external memory is read (506) from external memory507. Prior to merging at merge point520, sequence module30maintains a strict FIFO order504of packets within each of the fast path and the slow path using fast push ready FIFO512and slow push ready FIFO514, respectively. That is, sequence module30pushes fast path-assigned and slow path-assigned packets to a respective fast path queue (FIFO512) and a slow path queue (FIFO514).

In most cases, sequence module30buffers packets assigned to the fast path in internal memory, while sequence module30buffers packets assigned to the slow path in external memory. However, if a packet flow transitions to uncongested and an internally-buffered packet for the packet flow follows closely after an externally-buffered packet for the same packet flow, the internally-buffered packet may race ahead to merge point520, violating ordering requirements. Accordingly, in some examples, sequence module30assigns an internally-buffered packet to the slow path to maintain the proper order. To prevent subsequently-received packets of a first flow that are assigned to the fast path from racing ahead of previously-received packets of the same first flow that have been assigned to the slow path, sequence module30implements context decision logic508to maintain a per-flow counter509of the number of outstanding packets assigned to the slow path. Per-flow counter509allows sequence module30to keep track of the number of packets or pages assigned to and remaining in the slow path for a packet flow. For example, sequence module30increments counter509for a packet flow upon assigning a packet of the packet flow to the slow path, and decrements counter509upon outputting a packet of the packet flow from the slow path to merge point520. Further, upon receiving an internal page for a packet flow for which counter509is non-zero, sequence module30may assign the internal page to the slow path to maintain the order of the flow. Sequence module30may maintain a separate counter509for each packet flow. In some cases, the counter may be a count of the number of packets in a slow path queue for the slow path.

If the packet is indicated as internally buffered and counter509is zero, then sequence module30assigns the packet to the fast path via selector operation510. In effect, sequence module30may send the packet for forwarding to merge point520in a FIFO order for the fast path. Sequence module30performs sequence number assignment524to stamp the packet with a next sequence number for the corresponding cell stream. In some examples, sequence module30refers to sequence number table526for the next sequence number for assignment to the packet. Further, sequence module30reads the packet, and generates and switches cell data for the packet to egress fabric endpoint20B.

If the packet is internally buffered but counter509is non-zero, sequence module30assigns the packet to the internal slow path516to prevent the packet from racing ahead of prior-sequenced packets for the same flow that have not yet been processed from the slow path. This forces the packet to be delayed internally until all preceding external-fetched data has been read from external memory (518) for that packet flow, so as to ensure that all packets for that packet flow are output to merge point520in correct order.

As will be described in more detail below, sequence module30may include merging stage528that includes fast push ready FIFO512, slow push ready FIFO514, merge point520, and round robin scheduler522. Packets assigned to the fast path for packet switching may be queued in FIFO512according to a first-in, first, out scheme for outputting to merge point520, Similarly, packets assigned to the slow path for packet switching may be queued in FIFO514according to a first-in, first, out scheme for outputting to merge point520. Merge point520merges packets from fast push FIFO512and slow push FIFO514for sequence number assignment514and switching across switch fabric518. In some examples, merge point520uses a round robin scheduler, such as a deficit-weighted round-robin (DWRR) scheduler, to ensure that packets from the fast path and slow path are processed and output from ingress fabric endpoint20A evenly.

The following example may illustrate the operation of sequence module30. In this example sequence module30receives 2 flows. Flow A is uncongested and has packets only in internal memory, whereas flow B originally was uncongested and so had packets in internal memory, at some point in time became congested and so had subsequent packets shifted to external memory, and finally became uncongested and so subsequent packets were shifted back to internal memory. The sequence of packets, with packet P0being first to arrive and packet P4being last to arrive, are as follows:

Sequence module30checks per-flow counter509for packet P0. Because packet P0belongs to flow A, which has packets only in internal memory, the per-flow counter of flow A is 0. Thus, sequence module30pushes packet P0to the fast data path.

Packet P1belongs to flow B and is an external packet. Thus, sequence module30increments per-flow counter509for flow B and pushes packet P1to the slow data path.

Packet P2belongs to flow A, which has packets only in internal memory. After checking per-flow counter509for packet P2, sequence module30pushes packet P2to the fast data path.

Packet P3belongs to flow B. Sequence module30checks per-flow counter509for packet P3. Because flow B already has an external packet in the slow data path, per-flow counter509is non-zero. Accordingly, sequence module30pushes packet P3to the slow data path to maintain the per-flow order of packets within flow B.

Packet P4belongs to flow A. After checking per-flow counter509for packet P4, sequence module30pushes packet P4to the fast data path. Thus, it may be recognized that packets of flow A, which is uncongested, may be received subsequent to packets of flow B, which is congested, but the packets of flow A may be output for processing and switching by sequence module30prior to processing and switching of the packets of flow B. Further, flow A, which has packets only in internal memory, is not affected (e.g., blocked or delayed) by flow B, which has packets in external memory.

FIG. 6is a block diagram illustrating an example conceptual diagram for merging congested and uncongested traffic flows in accordance with the techniques of the disclosure. In some examples, the merging of congested and uncongested traffic flows is performed by merge point520of sequence module30ofFIG. 5. In the example ofFIG. 5, sequence module30receives 3 flows: flow 0, flow 1, and flow 2. Flows 1 and 2 are uncongested, while flow 0 is congested. Sequence module30assigns, based on the congestion status of each flow, packets of flow 0 to the slow path and packets of flows 1 and 2 to the fast path. Sequence module30may buffer the packets of flow 0 in external memory until the data for the packets of flow 0 becomes available. Merge point520may merge packets for flows 0, 1, and 2 according to an availability of each of the packets. For example, because packets of flows 1 and 2 are assigned to the fast path, the packets of flows 1 and 2 are available for immediate processing. Merge point merges packets of each of flows 1 and 2 according to a round-robin scheduler (e.g., outputting a packet from flow 2, then a packet of flow 1, and so on). Once sequence module30outputs the packets of uncongested flows 1 and 2 for processing, sequence module30may output the packets of congested flow 2 as the data for the packets becomes available. Thus, by assigning flows 0, 1, and 2 to one of the fast path and slow path based on a congestion status of each flow, sequence module30enables packets of uncongested flows 1 and 2 to bypass the packets of congested flow 0 such that the congested nature of flow 0 does not impact uncongested flows 1 and 2.

FIG. 7is a block diagram illustrating example merging stage528ofFIG. 5for merging fast and slow paths of sequence module30A in accordance with the techniques of the disclosure. Fast push FIFO512, slow push ready FIFO514, round robin scheduler522, and merge point520may operate in a substantially similar fashion to the like components ofFIG. 5.

Fast Push Ready FIFO512queues internal packets, e.g., Fast Internal packets. Slow Push Ready FIFO514queues both internal and external packets, e.g., External and Slow Internal packets. Once pages on the slow path are ready for output, then packets for the fast path queued in fast path FIFO512and packets for the slow path queued in slow path FIFO514may be merged into a single stream using round robin scheduler522and multiplexor706and multiplexor720of merge point720. In some examples, round robin scheduler522implements deficit round robin (DRR). To maintain fairness, scheduler522maintains credits for a fast internal page bucket, a slow internal page bucket, an internal page bucket, and an external page bucket.

In one example, scheduler522includes 2 DRRs—DRR702and DRR704. DRR module702applies deficit round robin to merge data packets traversing the fast internal path with data packets traversing the slow internal path. DRR704merges data packets on the internal path (e.g., data packets for the merged fast internal and slow internal paths) with data packets on the external path.

For example, if Slow Push Ready FIFO514has an external packet at the head, merging stage528runs DRR704between internal packets and external packets. If merging stage528selects an external packet for dequeueing, DRR704charges credits to the external page bucket. If merging stage528selects an internal packet for dequeueing, then DRR704charges credits to both the internal page bucket and the fast internal page bucket. If Slow Push Ready FIFO514has an internal packet at the head, merging stage528runs DRR702between a slow internal packet and a fast internal packet. If merging stage528selects a slow internal packet for dequeueing, DRR702charges credits to the slow internal page bucket and the internal page bucket. If merging stage528selects a fast internal packet for dequeueing, DRR702charges credits to the fast internal page bucket and the internal page bucket. Once scheduler522selects a page, scheduler522pops the page from the selected FIFO512,514and sends the packet for sequence number stamping and egress.

FIG. 8is a flowchart illustrating an example operation in accordance with the techniques of the disclosure. For convenience,FIG. 8is discussed with respect to HG2.

Ingress fabric endpoint20A receives a plurality of packet flows for switching across switch fabric18to egress fabric endpoint20B (802). The plurality of packet flows include packet flows that are congested and packet flows that are uncongested. A “congested packet flow” is a packet flow that has one or more delayed packets. Typically, a packet flow becomes congested when a queue somewhere along a network path for the packet flow is at capacity, which causes delays in the switching of packets for the packet flow from ingress fabric endpoint20A across switch fabric18. In the example ofFIG. 8, ingress fabric endpoint20A receives a first packet of a first packet flow that is congested. After receiving the first packet of the first packet flow, ingress fabric endpoint20A receives a second packet of a second packet flow that was previously congested but has become uncongested. After receiving the second packet of the second packet flow, ingress fabric endpoint20A receives a third packet of a third packet flow that is uncongested.

Sequence module30A of ingress fabric endpoint20A assigns each packet for each packet flow of the plurality of packet flows to a fast path for packet switching or a slow path for packet switching. To assign each packet for each packet flow to the fast path or the slow path, sequence module30A determines whether the packet flow is congested (804). For example, in response to determining that the first packet flow is congested (“YES” block of804), sequence module30A assigns a first packet of the first packet flow to the slow path (806). For each packet of the first packet flow assigned to the slow path, sequence module30A increments a flow counter for the first packet flow (808). The flow counter for the first packet flow indicates a number of packets of the first packet flow currently assigned to the slow path.

As another example, in response to determining that the second packet flow is uncongested (“NO” block of804), sequence module30A determines whether a flow counter for the second packet flow indicates a non-zero number of packets of the second packet flow are currently assigned to the slow path (810). In response to determining that the flow counter for the second packet flow indicates a non-zero number of packets of the second packet flow are currently assigned to the slow path (“YES” block of810), sequence module30A assigns a second packet of the second packet flow to the slow path (806) and increments the flow counter for the second packet flow (808).

As another example, in response to determining that the third packet flow is uncongested (“NO” block of804) and in response to determining that a flow counter for the third packet flow indicates that no packets of the third packet flow are currently assigned to the slow path (“NO” block of810), sequence module30A assigns a third packet of the third packet flow to the fast path (812).

Sequence module30A processes packets from the fast path and the slow path to generate a stream of cells for switching across switch fabric18to egress fabric endpoint20B. For example, sequence module30A merges packets from the fast path and the slow path (814). For each packet, sequence module30A determines whether the packet was assigned to the slow path (816). In response to determining that a packet (e.g., the first packet of the first flow) was assigned to the slow path (“YES” block of816), sequence module30A decrements the flow counter for the first packet flow (818). After decrementing the counter, or alternatively, in response to determining that a packet was not assigned to the slow path (“NO” block of816), sequence module30A generates, from the merged packets, a stream of cells for switching across switch fabric18to egress fabric endpoint20A (820). Thus, sequence module30A maintains a FIFO ordering of the packets within each packet flow of the plurality of packet flows. Further, sequence module30A may switch a packet of a first packet flow (e.g., a congested packet flow) after switching a packet of another packet flow (e.g., an uncongested packet flow such as the third packet flow) despite the packet of the first packet flow being received by ingress fabric endpoint20A before the packet of the third packet flow.