Driving transistor control circuit

A control circuit controls a driving transistor connected in series with an electrical load between a power supply voltage and a ground. The control circuit includes a pull-up resistor connected at one end to a power supply voltage side of the driving transistor, a current detection resistor for detecting an electric current flowing from the driving transistor to the ground, a current mirror circuit including a starting transistor connected between the pull-up transistor and the current detection resistor. The current mirror circuit supplies a mirror current of the electric current. The control circuit further includes a current source circuit for supplying a driving current to a control terminal of the driving transistor in accordance with the mirror current to turn ON the driving transistor in response to an external control signal.

CROSS REFERENCE TO RELATED APPLICATION

This application is based on and incorporates herein by reference Japanese Patent Application No. 2008-187094 filed on Jul. 18, 2008, No. 2008-187095 filed on Jul. 18, 2008, and No. 2009-25982 filed on Feb. 6, 2009.

FIELD OF THE INVENTION

The present invention relates to a control circuit for controlling ON and OFF of a driving transistor connected in series with an external electrical load between a power supply voltage and a ground.

BACKGROUND OF THE INVENTION

In a device for diving an electrical load by supplying a direct current to the electrical load through a driving transistor (i.e., output driver), switching noise occurs due to a change in the current flowing through the electrical load. As one simple approach to reduce such switching noise, a resistance value of a resistor connected to the gate of the driving transistor is increased so that a gas signal waveform can be slowed due to a RC time constant of the resistance value and a gate capacitance. However, when a gate signal level exceeds a threshold voltage Vt of a FET, an energizing current increases sharply. Therefore, this approach may be insufficient to reduce harmonic noise.

As another approach to reduce such switching noise, a gate signal is caused to have a trapezoidal waveform. This approach can reduce a low-order harmonic wave but cannot reduce a high-order harmonic wave caused by corner portions of the trapezoidal waveform. US 2006/0267665 corresponding to JP-A-2007-13916 discloses a structure for causing a gate signal to have a near-sinusoidal waveform, thereby reducing such switching noise.

However, since the structure disclosed in US 2006/0267665 needs many current sources and comparators, the structure is increased in size and complexity.

JP-A-H9-8639 discloses a structure for preventing a shoot-through current from flowing between a power supply voltage and a ground in a signal output section of a CMOS. In the structure, multiple FETs are connected on each of a PMOS side and a NMOS side to remove a timing lag when each FET is switched to an OFF state and to create a timing lag when each FET is switched to an ON state. This structure may prevent the shoot-through current. However, since an electric current greatly changes when the gate voltage of each FET changes near a threshold voltage Vt of the FET, a noise reduction effect may be small. Further, the structure disclosed in JP-A-H9-8639 is increased in size and complexity.

JP-A-H11-136108 discloses a structure for reducing a switching noise. In the structure, multiple P-channel MOSFETs for signal output are connected in parallel, and the gate of each FET is individually provided with a level shift circuit. Further, ON-timings of the FETs are changed by using multiple delay circuits so as to reduce the switching noise. However, the structure disclosed in JP-A-H11-136108 is increased in size and complexity compared to the structure disclosed in JP-A-H9-8639.

SUMMARY OF THE INVENTION

In view of the above, it is an object of the present invention to provide a driving transistor control circuit having a simple structure for effectively reducing switching noise associated with a switching operation of a driving transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

A first embodiment of the present invention is described below with reference toFIGS. 1-3. A series circuit of an external electrical load1, an N-channel MOSFET2acting as a driving transistor, and a current detection resistor3for current detection is connected between a power supply voltage +B and a ground. Examples of the electrical load1can include a DC motor, a lamp, and an inductor. A series circuit of a pull-up resistor4and a NPN transistor5acting as a starting transistor is connected between the drain and the source of the MOSFET2. For example, the current detection resistor3has a resistance value of about a few tens of ohms (Ω), and the pull-up resistor4has a resistance value of about a few hundred kilohms (kΩ).

The NPN transistor5and a NPN transistor6form a first current mirror circuit7acting as a current control current mirror circuit. The bases of the NPN transistors5,6are connected to the collector of the NPN transistor5. The emitter of the NPN transistor6is connected to the ground, and the collector of the NPN transistor6is connected to the power supply voltage +B via a resistor8and a P-channel MOSFET9. The MOSFET9, a P-channel MOSFET10, and a P-channel MOSFET11form a second current mirror circuit12. The gates of the MOSFETs9-11are connected to the drain of the MOSFET9.

The drain of the MOSFET10is connected to the ground via a resistor13and a NPN transistor14. The NPN transistor14and a NPN transistor15form a third current mirror circuit16. The bases of the NPN transistors14,15are connected to the collector of the NPN transistor14. The collector of the NPN transistor15acting as a mirror side transistor is connected to the gate of the MOSFET2. The gate of the MOSFET2serves as a control terminal.

The drain of the MOSFET11is connected to the ground via a resistor17and a NPN transistor18. The NPN transistor18and a NPN transistor19form a fourth current mirror circuit20. The bases of the NPN transistors18,19are connected to the collector of the NPN transistor18. The collector of the NPN transistor19is connected to the power supply voltage +B via a P-channel MOSFET21. The MOSFET21and a P-channel MOSFET22form a fifth current mirror circuit23. The gates of the MOSFETs21,22are connected to the drain of the MOSFET21. The drain of the MOSFET22is connected to the gate of the MOSFET2.

An N-channel MOSFET24is connected in parallel to the NPN transistor14, and an N-channel MOSFET25is connected in parallel to the NPN transistor18. A control signal for controlling ON and OFF of the MOSFET2is supplied to the gate of the MOSFET25via a NOT gate26. The control signal passing through the NOT gate26is supplied to the gate of the MOSFET24via a NOT gate27. The above described circuit components except the electrical load1and the MOSFET2construct a driving transistor control circuit28. Further, a portion of the driving transistor control circuit28excluding the first current mirror circuit7constructs a driving current source circuit29.

Advantages of the first embodiment are described below with further reference toFIGS. 2 and 3. An electric current always flows from the pull-up resistor4to the current detection resistor3via the NPN transistor5regardless of whether the MOSFET2is ON or OFF. Accordingly, the first current mirror circuit7is always ON so that the second current mirror circuit12can be always ON.

The control signal for the MOSFET2is supplied from an external circuit. When the control signal for the MOSFET2is at a low level, the MOSFET24is turned OFF, and the MOSFET25is turned ON. Accordingly, the fifth current mirror circuit23is turned OFF. As a result, the gate potential of the MOSFET2becomes a low level so that the MOSFET2can be turned OFF. In the present embodiment, the pull-up resistor4has a high resistance value, and the current detection resistor3has a low resistance value. Therefore, the emitter potential of the NPN transistor5is kept close to the ground potential so that a small amount of current limited by the pull-up resistor4can flow through the NPN transistor5.

Then, when the control signal for the MOSFET2changes from the low level to the high level, the MOSFET24is turned ON, and the MOSFET25is turned OFF. Accordingly, the fifth current mirror circuit23is turned ON. As a result, the gate potential of the MOSFET2becomes the high level so that the MOSFET2can be turned ON. This turn-ON process of the MOSFET2is described below with reference toFIG. 2by dividing gate voltage rise of the MOSFET2in three stages, i.e., early stage V1, middle stage V2, and last stage V3

(Early Stage of Gate Voltage Rise)

Since an electric current supplied to the gate of the MOSFET2from the fifth current mirror circuit23is a mirror current of a collector current of the NPN transistor5of the first current mirror circuit7, the electric current eventually depends on the energization state of the first current mirror circuit7. At the early stage of the gate voltage rise, since a base-emitter voltage Vbe5of the NPN transistor5becomes substantially equal to a base-emitter voltage Vbe6of the NPN transistor6, the fifth current mirror circuit23supplies a small amount of current limited by the pull-up resistor4having the high resistance value. Therefore, as shown inFIG. 2, a waveform of the gate voltage is gentle at the early stage V1.

(Middle Stage of Gate Voltage Rise)

When the MOSFET2is turned ON according to the rise in the gate voltage, an electric current IR supplied via the MOSFET2to the current detection resistor3increases. Accordingly, a voltage drop across the current detection resistor3increases. In this case, the base-emitter voltages Vbe5, Vbe6of the NPN transistors5,6have the following relationship: Vbe6=Vbe5+RxIR, where R represents the resistance value of the current detection resistor3. That is, a mirror ratio of the first current mirror circuit7increases equivalently with a change in a ratio between the base-emitter voltages Vbe5, Vbe6. And, the electric current supplied from the fifth current mirror circuit23increases sharply so that the gate voltage of the MOSFET2can increase sharply. Therefore, as shown inFIG. 2, the waveform of the gate voltage is sharp at the middle stage V2.

(Last Stage of Gate Voltage Rise)

Then, when the MOSFET2is substantially fully turned ON, a voltage drop across the pull-up resistor4becomes very small so that an electric current passing through the NPN transistor5can decrease. Therefore, as shown inFIG. 2, the waveform of the gate voltage becomes gentle at the last stage V3.

By the way, when the control signal for the MOSFET2changes to the low level from this state so that the MOSFET2can be turned OFF, the above turn-ON process is reversely followed.FIG. 3is a diagram illustrating a result of a simulation conducted to measure a waveform of an output voltage (i.e., drain-ground voltage) of the MOSFET2. As indicated by circles inFIG. 3, the waveform of the output voltage has rounded corners where the output voltage starts and finish rising. Accordingly, the waveform of the output voltage is gentle as a whole.

As described above, according to the first embodiment, the NPN transistor5is connected between the current detection resistor3and the pull-up resistor4, and the first current mirror circuit7supplies a mirror current of an electric current passing through the current detection resistor3and the pull-up resistor4. When the MOSFET2is turned ON in accordance with the control signal, the driving current source circuit29supplies a driving current to the gate of the MOSFET2in accordance with the mirror current supplied from the first current mirror circuit7. In such an approach, when the voltage applied to the gate of the MOSFET2starts rising during the turn-ON process of the MOSFET2, the change in the gate voltage is reduced. Further, when the voltage applied to the gate of the MOSFET2finishes rising during the turn-ON process of the MOSFET2due to the fact that the MOSFET2is almost fully turned ON, the change in the gate voltage is reduced. Therefore, when the MOSFET2is switched between On and OFF states, the change in the output voltage of the MOSFET2is reduced. Thus, in particular, switching noise caused by high-order harmonic wave can be reduced.

When the third and fourth current mirror circuits16,20are turned OFF and ON, respectively, to turn ON the MOSFET2, the mirror current supplied from the first current mirror circuit7is successively mirrored by the second, fourth and fifth current mirror circuits12,20,23. Thus, the fifth current mirror circuit23supplies the driving current to the gate of the MOSFET2so that the MOSFET2can be turned ON. In contrast, when the third and fourth current mirror circuits16,20are turned ON and OFF, respectively, to turn OFF the MOSFET2, the supply of the driving current to the gate of the MOSFET2from the fifth current mirror circuit23is stopped. Thus, the third current mirror circuit16causes the gate of the MOSFET2to be set to the potential that can turn OFF the MOSFET2.

Second Embodiment

A driving transistor control circuit31according to a second embodiment of the present invention is described below with reference toFIG. 4. A difference between the first and second embodiments is as follows. The driving transistor control circuit31includes N-channel MOSFETs5M,6M,14M,15M,18M, and19M instead of the NPN transistors5,6,14,15,18, and19of the driving transistor control circuit28. The MOSFETs5M,6M form a first current mirror circuit7M instead of the first current mirror circuit7. The MOSFETs14M,15M form a third current mirror circuit16M instead of the third current mirror circuit16. The MOSFETs18M,19M form a fourth current mirror circuit20M instead of the fourth current mirror circuit20.

The driving transistor control circuit28of the first embodiment is constructed with both a MOSFET and a bipolar transistor and suitably designed based on a difference in operating speed between a MOSFET and a bipolar transistor. In contrast, the driving transistor control circuit31of the second embodiment is constructed with only a MOSFET. That is, kinds of transistors used to form a driving transistor control circuit are not limited. The driving transistor control circuit31can have the same advantages as the driving transistor control circuit28.

Third Embodiment

A driving transistor control circuit32according to a third embodiment of the present invention is described below with reference toFIG. 5. A difference between the first and third embodiments is as follows. As compared to the driving transistor control circuit28, the driving transistor control circuit32further includes an N-channel MOSFET33acting as a current detection transistor. The source of the MOSFET2is directly connected to the ground. The drain and gate of the MOSFET33are connected to the drain and gate of the MOSFET2, respectively. The source of the MOSFET33is connected to the ground via a current detection resistor34.

In such an approach, an electric current flowing through the MOSFET33can be smaller than an electric current flowing through the MOSFET2. Therefore, even when the electric current flowing through the MOSFET2is relatively large, an electric current flowing through the current detection resistor34becomes small. Therefore, the electric current can be easily detected.

Fourth Embodiment

A driving transistor control circuit32H according to a fourth embodiment of the present invention is described below with reference toFIG. 6. A difference between the third and fourth embodiments is as follows. The driving transistor control circuit32H is achieved by modifying the driving transistor control circuit32in a high side drive configuration. That is, the electrical load1is connected between the source of the MOSFET2and the ground. The emitters of the transistors5,6and a lower potential side of the current detection resistor34are connected to the ground via the electrical load1. The sources of the MOSFETs21,22of the fifth current mirror circuit23that supplies the driving current to the gate of the MOSFET2is connected to a power supply voltage +BB that is greater than the power supply voltage +B. The power supply voltage +BB can be produced by boosting the power supply voltage +B.

As describe above, according to the fourth embodiment, the present invention can be applied to a high side drive configuration.

Fifth Embodiment

A fifth embodiment of the present invention is described below with reference toFIG. 7. In the fifth embodiment, the driving transistor control circuits32,32H of the third and fifth embodiments are connected in a totem pole configuration. A junction between the source of a MOSFET2H of a driving transistor control circuit32H and the drain of a MOSFET2L of a driving transistor control circuit32L is connected to the electrical load1.

The MOSFETs2H,2L are supplied with control signals that cause the MOSFETs2H,2L to be exclusively turned ON. When the MOSFET2H is turned ON, a source current is supplied to the electrical load1. In contrast, when the MOSFET2L is turned ON, a sink current is drawn from the electrical load1. As described above, according to the fifth embodiment, two driving transistor control circuits32L,32H are connected in a totem pole configuration. In such an approach, the electrical load1can be driven by switching the source current and the sink current.

Sixth Embodiment

A driving transistor control circuit35according to a sixth embodiment of the present invention is described below with reference toFIG. 8. A difference between the first and sixth embodiments is as follows. As compared to the driving transistor control circuit28, the driving transistor control circuit35further includes a PNP transistor36acting as a current interrupting switch and a resistor37. The PNP transistor36is connected between the pull-up resistor4and the NPN transistor5. Specifically, the emitter of the PNP transistor36is connected to the pull-up resistor4, and the collector of the PNP transistor36is connected to the collector of the NPN transistor5. The base of the PNP transistor36is connected to the power supply voltage +B via the resistor37. A control signal STB of high active is applied to the base of the PNP transistor36.

Advantages of the sixth embodiment are described below. For example, when there is a need to activate an output stage of the driving transistor control circuit35as in the first embodiment, the control signal STB is set to a low level so that the PNP transistor36can be turned ON. Thus, an electric current is supplied via the pull-up resistor4to the NPN transistors5,6of the first current mirror circuit7. In contrast, when there is no need to activate the output stage of the driving transistor control circuit35, the control signal STB is set to a high level so that the PNP transistor36can be turned OFF. Thus, the supply of the electric current via the pull-up resistor4to the first current mirror circuit7is interrupted. For example, when the MOSFET2is kept ON or OFF for a long time period, the control signal STB can be set to a high level. For another example, the control signal STB can be set to a high level during a time period excluding rising and falling periods of turn-ON and turn-OFF of the MOSFET2.

As described above, according to the sixth embodiment, a leak current flowing via the pull-up resistor4is reduced so that a consumption current can be reduced. Further, the PNP transistor36acts as a current interrupting switch. Therefore, the electric current flowing via the pull-up resistor4can be controlled by controlling ON and OFF of the PNP transistor36.

The embodiments described above can be modified in various ways. For example, the driving transistor control circuit can be constructed with only a bipolar transistor. In the fifth embodiment, another one set of the driving transistor control circuits32H,32L can be used to form a H-bridge circuit for switching an energization direction of the electrical load1. In the sixth embodiment, the current interrupting switch can be constructed with a transistor other than a PNP transistor. For example, the current interrupting switch can be constructed with a P-channel MOSFET, a NPN transistor, or an N-channel MOSFET. The current interrupting switch of the sixth embodiment can be applied to the second to fifth embodiments.

Seventh Embodiment

A seventh embodiment of the present invention is described below with reference toFIG. 9. A series circuit of the electrical load1and an N-channel MOSFET102acting as a primary driving transistor is connected between the power supply voltage +B and the ground. The MOSFET102is a power MOSFET and large in size (e.g., gate width and gate length). For example, the MOSFET102can be formed as a LDMOS (laterally diffused MOS). An N-channel MOSFET103acting as a secondary driving transistor is connected in parallel with the MOSFET102. The MOSFET103is smaller in size than the MOSFET102and larger in ON-resistance than the MOSFET102.

The gate (i.e., control terminal) of the MOSFET103is connected to the power supply voltage +B via a resistor104acting as a first resistor and a P-channel MOSFET105acting as a control transistor. Further, the gate of the MOSFET103is connected to the gate of the MOSFET102via a resistor106acting as a second resistor. The gate of the MOSFET102is also connected to the ground via a resistor107acting as a third resistor and an N-channel MOSFET108acting as a second control transistor.

A control signal IN for controlling ON and OFF of the MOSFET102is supplied to the gate of the MOSFET108from an external circuit. Further, the control signal IN is applied via a NOT gate109to the gate of an N-channel MOSFET110acting as a third control transistor. The source of the MOSFET110is connected to the ground. The drain of the MOSFET110is connected via a resistor111to the gate of the MOSFET105. The gate of the MOSFET105is connected via a resistor112to each of the power supply voltage +B and the source of the MOSFET102.

The above described circuit components except the electrical load1and the MOSFET102construct a driving transistor control circuit113. Further, a portion of the driving transistor control circuit113excluding the MOSFET103constructs an energization control circuit114.

Advantages of the seventh embodiment are described below.

(Turn-ON Operation of MOSFET102)

When the control signal IN is at a low level, the control signal commands the MOSFET102to be turned ON. In this case, the MOSFET108is turned OFF, and the MOSFET110is turned ON. As a result, the gate potential of the MOSFET105is reduced below the power supply voltage +B so that the MOSFET105can be turned ON. Accordingly, the power supply voltage +B is applied via the resistor104to the gate of the MOSFET103. Then, the gate potential of the MOSFET103gradually increases in accordance with a time constant of a resistance value R1of the pull-up resistor4and a gate capacitance of the MOSFET103. As a result, the MOSFET103is turned ON. In this way, a small amount of current flows through the MOSFET103having a high ON-resistance.

Since the power supply voltage +B is applied via the resistor106to the gate of the MOSFET102, turn-ON of the MOSFET102is lessened by the time constant of a resistance value R2of the resistor106and the gate capacitance of the MOSFET102. Therefore, the MOSFET102is turned ON later than the MOSFET103so that the amount of an energization current flowing through the electrical load1can be increased. In this turn-ON operation of the MOSFET102, the amount of change in the energization current flowing through the electrical load1becomes small, as compared to when only the MOSFET102is turned ON.

(Turn-OFF Operation of MOSFET102)

When the control signal is at a high level, the control signal commands the MOSFET102to be turned OFF. In this case, the MOSFET108is turned ON, and the MOSFET110is turned OFF. Then, the gate of the MOSFET103is connected via the resistor107to the ground, so that the gate potential of the MOSFET103gradually decreases in accordance with a time constant of a resistance value R3of the resistor107and the gate capacitance of the MOSFET102. Therefore, the MOSFET102is turned OFF earlier than the MOSFET103.

Since the ground potential is applied via the resistor106to the gate of the MOSFET103, the gate potential of the MOSFET103decreases at a time constant of the resistance value R2of the resistor106and the gate capacitance of the MOSFET103in addition to the resistance value R3and the gate capacitance of the MOSFET108. Thus, a turn-ON of the MOSFET103is lessened. Accordingly, the MOSFET103is turned OFF later than the MOSFET102so that the electrical load1can be de-energized. The resistance values of the resistors104,106,107,111are selected by taking into consideration the time constant according to the gate capacitances of the MOSFETs102,103,105.

As described above, according to the seventh embodiment, the MOSFET103connected in parallel to the MOSFET102is smaller in size than the MOSFET102and larger in ON-resistance than the MOSFET102. When the MOSFET102is commanded to be turned ON, the energization control circuit114turns ON the MOSFET103before turning ON the MOSFET102. That is, when the MOSFET102is commanded to be turned ON, the MOSFET103is turned ON earlier than the MOSFET102. In such an approach, the MOSFET102is turned ON, after a small amount of electric current flows through the electrical load1. Therefore, as compared to when the switching is performed by only the MOSFET102, the degree of change in electric current is lessened. In contrast, when the MOSFET102is commanded to be turned OFF, the energization control circuit114turns OFF the MOSFET103after turning OFF the MOSFET102. In such an approach, an increase in the degree of change in electric current can be prevented, although the MOSFETs102,103are connected in parallel with each other. Accordingly, switching noise can be reduced.

Upon receipt of the control signal IN that commands the MOSFET102to be turned ON, the energization control circuit114turns ON the MOSFET105so as to turn ON the MOSFET103. In this case, the energization control circuit114lessens the turn-ON of the MOSFET103by the time constant of the resistance value R1of the resistor104and the gate capacitance of the MOSFET103. Further, since the power supply voltage +B is applied to the gate of the MOSFET102via the resistor106, the turn-ON of the MOSFET103is lessened by the time constant of the resistance value R2of the resistor106and the gate capacitance of the MOSFET102. Thus, the MOSFET102is turned ON later than the MOSFET103.

In contrast, upon receipt of the control signal IN that commands the MOSFET102to be turned OFF, the energization control circuit114turns ON the MOSFET108so as to turn OFF the MOSFET102. In this case, since the ground potential is applied to the gate of the MOSFET103via the resistors106,107, the MOSFET103is turned OFF later than the MOSFET102by the time constant of the resistance value R2of the resistor106and the gate capacitance of the MOSFET108.

Further, ON and OFF of the MOSFET108and the MOSFET110are exclusively controlled in accordance with the control signal IN for the MOSFET102. In such an approach, when the control signal IN commands the MOSFET to be turned ON, the gate of the MOSFET105is supplied with the potential that turns ON the MOSFET105. In this way, the MOSFET105is controlled in conjunction with the MOSFET108. Thus, the energization control circuit114can be easily implemented.

Eighth Embodiment

An eighth embodiment of the present invention is described below with reference toFIG. 10. A difference between the seventh and eighth embodiments is as follows. In the eighth embodiment, four driving transistor control circuits113, each of which is configured as described in the seventh embodiment, are connected to form a H-bridge circuit that can control an energization direction of the electrical load1by using four MOSFETs102.FIG. 10illustrates only two driving transistor control circuit13H,13L for controlling ON and OFF of MOSFETs102H,102L. The source of the MOSFET102H and the drain of the MOSFET102L are commonly connected to one side of the electrical load1.

In the seventh embodiment, the driving transistor control circuit113employs a low side drive configuration in which the MOSFET2is connected to a ground side of the electrical load1. As shown inFIG. 10, the driving transistor control circuit113can be applied to a high side drive configuration. It is noted that the source of the MOSFET105of the driving transistor control circuit113H is connected to the power supply voltage +BB that is greater than the power supply voltage +B, and that the source of the MOSFET105of the driving transistor control circuit113L is connected to a power supply voltage +BBB that is independent of the power supply voltage +B.

The driving transistor control circuits113H,113L are supplied from an external circuit with control signals INH, INL for controlling ON and OFF of the MOSFETs102H,102L, respectively. According to the eighth embodiment, the energization direction of the electrical load1can be switched by turning ON the MOSFETs102H,102L in an exclusive manner, and switching noise due to the switching of the energization direction can be reduced.

The seventh and eighth embodiments described above can be modified in various ways. For example, the MOSFETs102,103can be a P-channel MOSFET. The MOSFETs102,103can be a MOSFET other than LDMOS. The MOSFETs102,103can be a voltage-controlled transistor other than a MOSFET. For example, the MOSFETs102,103can be an insulated gate bipolar transistor (IGBT).

As to each control transistor, the channel type can be replaced between N-channel and P-channel. The control transistor can be a bipolar transistor.

In the eighth embodiment, only the driving transistor control circuits113H,113H can be connected to the electrical load1without forming a H-bridge circuit. In this case, when the MOSFET102H is turned ON, a source current is supplied to the electrical load1. In contrast, when the MOSFET102L is turned ON, a sink current is drawn from the electrical load1.