Integrated isolator incorporating trench capacitor

A circuit module including an integrated circuit (IC) and a method for forming an IC are disclosed. An embodiment of the circuit module includes a trench having a conductive trench liner formed in a semiconductor substrate, and further includes semiconductor device circuitry formed in the substrate, where a conductor within a metallization layer of the semiconductor device circuitry electrically connects to the conductive trench liner. The embodiment also includes an insulating structure arranged over the conductive trench liner, where the insulating structure extends to an upper contact formed within an upper metallization layer of the semiconductor device circuitry. An isolation capacitor operable between the upper contact and the conductive trench liner has one or more electrical properties dependent on both a depth of the trench and a number of metallization layers below the upper metal layer in the semiconductor device circuitry.

BACKGROUND

This disclosure relates to integrated circuit design and fabrication, and in particular to formation of an integrated isolator.

Signal transmission between circuits without direct current flow between them is important to various applications. Isolators for this purpose can be based on multiple technologies, including conversion to and from optical signals, inductive coupling via transformers, and capacitive coupling. For isolation within or between integrated circuits, integration of an isolator into an integrated circuit reduces the number of components needed.

Integrated isolators using inductors or capacitors have been formed using integrated circuit (IC) metallization layers to implement inductor coils or capacitor plates. Like other dimensions of IC features, thicknesses of metallization layers and of the intermetal dielectric layers between them are subject to limitations imposed by design rules of the IC fabrication process used.

DETAILED DESCRIPTION

An integrated isolator design disclosed herein employs a trench capacitor integrated on a semiconductor substrate with semiconductor device circuitry. In an embodiment, an isolation capacitor is formed with a bottom capacitor plate in the trench and a top plate formed within a metallization layer of the semiconductor device circuitry. The disclosed design is believed to provide greater configurability and lower fabrication cost than previous designs in which integrated isolation structures are formed solely within metallization layers of an integrated circuit.

FIG.1is a schematic diagram illustrating the basic concept of a capacitive isolator. System100includes a first circuit102isolated from a second circuit104by isolator106. Isolator106includes two capacitors108that prevent direct current flow between circuits102and104, while allowing signals to be passed between the circuits. In an embodiment, circuit102is a transmitter circuit and circuit104a receiver circuit (or vice versa). Capacitive isolators may be implemented in circuits of other configurations in other embodiments.

FIGS.2-7illustrate successive configurations of a semiconductor substrate during an embodiment of a method for forming an integrated circuit including an integrated isolator.FIG.2is a partial cross-sectional view of a semiconductor substrate200, of which a circuitry region202and an isolator region204are denoted by corresponding brackets. In the embodiment ofFIG.2, a field effect transistor (FET) structure including a gate region210, sidewall spacers212and source/drain regions208is formed within circuitry region202of substrate200. Isolation regions206are formed on either side of the FET structure, and interlevel dielectric214is deposited over substrate200and the devices formed therein. Interlevel dielectric214may sometimes be referred to as a premetal dielectric. In other embodiments, semiconductor devices of other types than the FET ofFIG.2are formed within circuitry region202. These devices may include, for example, other types of FET such as FinFET or laterally-diffused metal-oxide-semiconductor (LDMOS), or other transistor types such as bipolar transistors or heterojunction bipolar transistors.

The FET structure shown inFIG.2is merely one simplified example of semiconductor devices formed in circuitry region202of substrate200in embodiments of the methods disclosed herein. In an embodiment, devices formed in region202form a part of circuitry operable to implement a receiver or transmitter. Alternatively, devices formed in region202may form a part of circuitry operable to implement some other circuit function for which access to an isolator is desirable.

In an embodiment, devices formed in region202are formed using an established IC fabrication process. For example, substrate200is a silicon substrate in one embodiment. In a further embodiment, substrate200is a silicon layer of a semiconductor-on-insulator (SOI) substrate (See for exampleFIG.11where substrate200is layer of an SOI substrate). In other embodiments, substrate200is another type of semiconductor, such as a compound semiconductor and/or a semiconductor alloy. Example of compound semiconductors include, but are not limited to, GaAs, GaP, GaN, and InP. Semiconductor alloys include, but are not limited to, SiGe alloys, AlGaAsP alloys, AlGaN alloys and InGaP alloys. Isolation regions206are formed by shallow trench isolation (STI) in one embodiment, or may be formed by other methods such as localized oxidation of silicon (LOCOS) in other embodiments. Multiple process steps and variations thereof for semiconductor device formation will be understood by one of ordinary skill in the art of semiconductor fabrication in view of this disclosure, including but not limited to well implantation and annealing, gate patterning, dielectric spacer formation, source and drain implant and anneal, silicide formation, and interlevel dielectric deposition and chemical-mechanical polishing (CMP). In an embodiment, isolation regions206, spacers212and interlevel dielectric214are each formed from SiO2layers deposited or grown using one of various deposition or growth process known to one of ordinary skill in the art. In other embodiments, one or more of regions206, spacers212or layer214are formed from a different dielectric material such as silicon nitride. Devices within region200are formed using a complementary metal-oxide-semiconductor (CMOS) process in some embodiments.

The stage of processing depicted inFIG.2is sometimes referred to as completion of the “front end of the line” (FEOL), or fabrication of an integrated circuit up to, but not including, interconnect metal deposition. Embodiments of the integrated isolator fabrication processes disclosed herein allow FEOL processing to remain unchanged, aside from reservation of an isolator region of the substrate, such as region204, in which other circuitry is not formed. In the embodiment ofFIG.2, devices formed in region202are sealed and protected by dielectric214prior to trench etching for isolator formation.

FIG.3is a partial cross-sectional view of substrate200after formation of a trench300in isolator region204. In an embodiment, formation of trench300includes deposition of a silicon nitride layer by plasma-enhanced chemical vapor deposition (PECVD) for use as a hard mask, and patterning of the silicon nitride layer by photolithography and etching. In a further embodiment, the silicon nitride layer is approximately 0.1 Trench300is formed in such an embodiment by etching into substrate200using the patterned silicon nitride layer as a mask. In an embodiment, interlevel dielectric214is etched together with etching of an overlying silicon nitride hard mask. Etching of trench300is performed using an anisotropic etch process as understood by one of ordinary skill in the art. In an embodiment, a hard mask layer used to form trench300is subsequently removed. Trench300has a floor302and sidewalls304.

FIG.4is a partial cross-sectional view of substrate200after a conductive layer402is deposited over the floor and sidewalls of trench300. In the embodiment ofFIG.4, conductive layer402is formed during the process steps that form contact404through dielectric214to the FET structure in substrate200. These steps are the contact layer portion of an established IC fabrication process used to fabricate circuitry in circuitry region202. In an embodiment, the process includes deposition of nitride or oxide cap layer400over dielectric214and the exposed floor and sidewalls of trench300. In addition to serving as an etch stop layer for subsequent contact metal deposition, layer400provides electrical isolation between conductive layer402in trench300and substrate200. An opening is made through dielectric214so that deposition of conductive layer402produces contact404. In an embodiment, deposition of conductive layer402comprises deposition of a contact barrier layer such as titanium, titanium nitride, tantalum nitride or a combination of these, followed by deposition of tungsten.

Fabrication of the structure shown inFIG.4further includes depositing a trench fill dielectric406to substantially fill trench300. To the extent that an upper surface of dielectric406is below a top of trench300as defined by the top of conductive layer402, the trench is nonetheless filled sufficiently that a subsequent dielectric layer deposition over dielectric406can fill in the rest of the trench and result in a continuous dielectric structure extending upward. In an embodiment, trench fill dielectric406is a material having high dielectric strength, such as silicon dioxide, silicon nitride, or a spin-on glass (SOG). In a further embodiment, trench fill dielectric is formed with SOG.

FIG.5is a partial cross-sectional view of substrate200after portions of conductive layer402and trench fill dielectric406outside of the trench have been removed. In an embodiment, portions of conductive layer402external to trench300and contact404are removed using a tungsten CMP process employed in an established contact formation process for IC fabrication in region202of substrate200. In a further embodiment, the tungsten CMP process is modified to first remove portions of trench fill dielectric406covering the portions of conductive layer402external to trench300, or an additional step to remove these portions of dielectric406is added. Removal of the portions of conductive layer402external to the trench results in formation of a conductive trench liner500within trench300.

FIG.6is a partial cross-sectional view of substrate200after formation of a metallization layer600over the interlevel dielectric. In an embodiment, the metallization layer is formed using metallization layer steps of an established IC fabrication process used in region202of substrate200. As an example, such metallization layer steps can include metal layer deposition, metal masking and photolithography, metal etching to form interconnects or other conductors, photoresist stripping, and cleaning of the patterned conductors within metallization layer600. In the embodiment ofFIG.6, the mask used for patterning of metallization layer600defines an interconnect606that electrically contacts trench liner500at the top of the sidewalls304of trench300. Metallization layer600further includes other conductors, such as interconnect604, which electrically connects to contact404, and interconnect602. In an embodiment, interconnects within metallization layer600are formed from copper.

FIG.7is a partial cross-sectional view of substrate200after deposition of an intermetal dielectric700and formation of an uppermost metallization layer704. In the embodiment ofFIG.7, a via702is formed through intermetal dielectric700, forming a connection between an interconnect708in uppermost metallization layer704and interconnect604in metallization layer604. A passivation layer716is formed over uppermost metallization layer704. In an embodiment, intermetal dielectric700, via702, uppermost interconnect layer704and passivation layer716are formed using standard process modules of an established IC fabrication process employed for fabricating semiconductor circuitry718in region202of substrate200. In a further embodiment, the standard process modules are part of a standard CMOS flow. Semiconductor circuitry718includes the semiconductor devices formed in region202as well as the overlying contacts and interconnects for accessing the devices. The steps illustrated byFIGS.4-7are often referred to as “back end of the line” (BEOL) processing, in which contacts and interconnects of an IC are formed. The trench formation in the embodiment ofFIGS.2-7occurs between the FEOL and BEOL stages. In other embodiments, trench formation could be done before the FEOL device formation.

In the embodiment ofFIG.7, the mask used for patterning of uppermost metallization layer704defines an upper contact710overlying a central portion of trench300. Uppermost metallization layer704further includes guard ring structures712and714for blocking surface leakage currents. In an embodiment, ring712is a termination ring and ring714is a floating ring. In other embodiments, more or fewer guard ring structures are used. Other interconnects within uppermost metallization layer704include interconnect708, which is electrically connected to interconnect604by via702, and interconnect706. In an embodiment, via702and interconnects within uppermost metallization layer704are formed from copper. In a further embodiment, intermetal dielectric700is a silicon dioxide layer and passivation layer716includes a silicon nitride or silicon oxynitride layer. Trench fill dielectric406and intermetal dielectric700combine to form a dielectric structure extending from trench liner500to upper contact710. This creates an isolation capacitor operable between liner500and upper contact710. Trench liner500forms a bottom plate of the capacitor, and is connected to circuitry718via interconnect606(the specific connection between interconnect606and a device within circuitry718is not shown inFIG.7). Upper contact710forms a top plate of the capacitor, and can be connected to an additional circuit external to substrate200.FIG.11is similar toFIG.7where substrate200is located over an insulating layer1102of an SOI substrate.

An example of connection of a top contact of an integrated capacitive isolator to an additional circuit is shown inFIG.8.FIG.8is a simplified top view of a circuit module including a first integrated circuit802and second integrated circuit804mounted onto a chip carrier800. Integrated circuit802is formed in and on a semiconductor substrate similar to substrate200ofFIGS.2-7, and includes a circuitry region806and isolator region807, similar to regions202and204, respectively, ofFIGS.2-7. Semiconductor device circuitry is formed in region806of IC802but not shown in the simplified view ofFIG.8. In an embodiment, IC802includes semiconductor device circuitry operable to implement a receiver circuit.

A pair of capacitive isolators is formed in isolator region807of IC802. Each isolator includes an upper contact808, similar to upper contact710inFIG.7. Each isolator also includes a lower plate contact810, similar to interconnect606ofFIGS.6-7. Lower plate contact810is shown with a dashed-line border to indicate that it is below the surface of IC802, at a metallization layer similar to layer600inFIGS.6-7. Guard rings such as rings712and714ofFIG.7are not shown in the embodiment ofFIG.8but may be present in other embodiments. Each of upper contacts808is connected via a respective wire bond812to a respective contact pad814on second IC804. Contact pads814of IC804are electrically connected to semiconductor circuitry of IC804, which circuitry is not shown inFIG.8. In an embodiment, IC804includes semiconductor device circuitry operable to implement a transmitter circuit. In an embodiment in which IC802implements a receiver circuit and IC804implements a transmitter circuit, the pair of capacitors in region807of IC802functions as a communications channel isolator. However, such isolators may be used in other types of circuits as well.

Various lateral dimensions for the capacitive isolators of IC802are designated inFIG.8, including an upper contact diameter D, a lower plate contact width p, a lateral spacing d between edges of upper contact808and lower plate contact810, and a lateral spacing x between outer edges of the two lower plate contacts. These dimensions can be used to define dimensions of isolator region807. In an embodiment in which a spacing of x/2 is maintained between outer edges of lower plate contact p and edges of region807, a height H of region807can be defined as H=D+2d+2p+x, and a width W of region807can be defined as W=2D+4p+4d+2x.

With reference to the dimensions designated inFIG.8, an example of some estimated dimensions and properties of an integrated isolation capacitor as disclosed herein is provided in Table 1 below. For the embodiment of Table 1, the capacitor dielectric is assumed to be SiO2, with a dielectric constant of 3.9 and a dielectric strength of 107V/cm. The contact width p, spacing x and spacing d are each assumed to be 10 μm for the embodiment of Table 1. A dielectric layer thickness between capacitor plates of 6.5 μm is assumed. Using

A=area of capacitor plate overlap in square meters (which for this geometry is the upper plate area) and

d=distance between plates in meters,

and a vacuum permittivity of 8.854 pF/m gives the estimated dimensions in Table 1 for capacitors with 100 femtoFarad, 150 femtoFarad, and 200 femtoFarad capacitance values. It is noted that Table 1 reflects a simplified calculation and starting assumptions for rough estimation purposes rather than an optimized layout. Actual layout dimensions should account for multiple additional factors, such as prevention of breakdown in a lateral direction.

Turning now to consideration of vertical dimensions for capacitive isolators disclosed herein,FIG.9is a simplified cross-sectional view of a portion of a semiconductor substrate900having a conductive trench liner912and trench fill dielectric914, showing seven metallization layers formed over the substrate. The structure ofFIG.9is intended to illustrate vertical dimensions available using a given fabrication process, rather than to depict a specific IC configuration. In an embodiment,FIG.9illustrates the backend dimensions for a 0.13 μm process; other processes would have different dimensions than those inFIG.9. A dashed line indicating the substrate surface prior to trench formation is used in defining a trench depth DTas the depth of the trench into the semiconductor substrate (as opposed to the depth extending through interlevel dielectric902). In the embodiment ofFIG.9, interlevel dielectric902is 0.7 thick. Metallization layers labeled M1 through M7 are separated by intermetal dielectric layers908which are 0.45 μm thick. As is typical for integrated circuits having multiple metallization layers, metallization layer thicknesses inFIG.9are smaller for lower metallization layers (layers closer to the substrate) than for higher ones. In the embodiment ofFIG.9, 0.25 μm thick metallization layer904is used for the M1 and M2 metallization layers, while 0.35 μm thick metallization layer906is used for the M3 through M7 metallization layers.

Dielectric thicknesses available for isolation capacitors using an IC fabrication process corresponding to the structure ofFIG.9can be determined by considering the vertical dimensions available and the capacitor structures used. In the case of a prior design in which capacitor plates are formed within respective metallization layers, the largest dielectric thickness available using the structure ofFIG.9would be the dielectric thickness between M1 and M7, or 4.35 μm. One problem with such a structure is that some isolator applications require several kilovolts of isolation and may therefore require capacitor dielectric thicknesses of 5 μm or more. Another problem is that additional metallization layers add significant costs to a fabrication process, so that using a process with more metallization layers than are needed for the non-isolator circuitry can be quite expensive.

The isolator employing a trench capacitor disclosed herein reduces the number of metal layers needed to obtain a given capacitor dielectric thickness, since a portion of the capacitor dielectric is formed within the trench. For example, the 6.5 μm dielectric thickness assumed in the calculation of Table 1 could be obtained using only two metallization layers of the structure ofFIG.9. A dielectric thickness between the bottom of trench liner912and an upper contact formed in the M2 layer would be 6.5 μm if trench depth DTis 5.1 μm. Because formation of such a deep trench can cause its own processing problems, it may be more desirable in some embodiments to use a greater number of metallization layers so that a shallower trench can be used. Continuing with the example of a 6.5 μm dielectric thickness using the process ofFIG.9, forming the upper contact in the M3 layer would allow for a trench depth DTof 4.4 μm, and forming the upper contact in the M4 layer would allow for a depth of 3.6 μm. Whatever number of metallization layers is used, metallization layers below the uppermost metallization layer are patterned such that no interconnects from these intervening metallization layers overlie the trench.

The integrated isolator structure disclosed herein has a capacitor dielectric formed from a combination of trench depth and metallization layer spacing. As such, electrical properties of the isolation capacitor, such as capacitance or breakdown voltage, depend on both the depth of the trench and the number of metallization layers in the IC. The structure disclosed herein allows greater dielectric thicknesses to be achieved with fewer metallization layers needed in the IC as compared to previous solutions. The number of metallization layers used can be increased in order to reduce the trench depth required to obtain a desired dielectric thickness, or the trench depth can be increased to reduce the number of metallization layers required. In an embodiment, a discrete set of available trench depths is included in the design rules of an IC fabrication process. In such an embodiment, circuit designers can choose among the available trench depths and choose a desired number of metallization layers when designing an integrated isolator.FIG.10is a graph of isolator dielectric thickness as a function of trench depth for a process producing the vertical dimensions shown inFIG.9. The four traces inFIG.10are for isolation capacitors formed using 3, 4, 5 and 6 metallization layers, respectively. If the available trench depths in a process corresponding toFIG.10were 1 μm, 1.5 μm and 2 μm, a set of dielectric thicknesses in a range from 3.1 μm to 6.5 μm would be achievable, depending on how many metallization layers were used. Graphs similar toFIG.10can be produced for fabrication processes other than that ofFIG.9, with dielectric thickness corresponding to the vertical dimensions achievable by those processes.

Multiple alternatives and variations to the semiconductor processes described herein will be apparent to one of ordinary skill in the art of integrated circuit design and manufacturing in view of this disclosure. Aspects of IC fabrication processes described herein, such as dimensions, specific materials and circuit technologies, are merely examples. The vertical dimensions shown inFIG.9, for example, are suitable for the back end of an 0.13 μm process. Other processes have different vertical dimensions. Although a circular geometry is shown inFIG.8for lower plate contact810and upper contact808, the isolation capacitor disclosed herein could have a noncircular shape in other embodiments, such as rectangular, square, oval, or any other shape. Wire bond connections described herein could be made with some other electrical coupling technology, such as solder bumps in a tape-automated bonding or flip-chip packaging arrangement.

An embodiment disclosed herein of a circuit module including an integrated circuit includes a first trench formed in a semiconductor substrate, a first conductive trench liner covering a floor and sidewalls of the first trench, semiconductor device circuitry formed in the semiconductor substrate, and an insulating structure arranged over the first conductive trench liner and filling the first trench. A first conductor within a metallization layer of the semiconductor device circuitry electrically connects to the first conductive trench liner, the insulating structure extends to a first upper contact formed within an upper metallization layer of the semiconductor device circuitry and overlying a central portion of the first trench, and a first isolation capacitor operable between the first upper contact and the first conductive trench liner has one or more electrical properties dependent on both a depth of the first trench and a number of metallization layers below the upper metallization layer in the semiconductor device circuitry.

In a further embodiment of the circuit module, the semiconductor substrate is an upper layer of a semiconductor on insulator substrate. Another embodiment of the circuit module also includes an insulating layer between the first conductive trench liner and the floor and sidewalls of the first trench. In still another embodiment of the circuit module, the upper metallization layer is connected by one or more vias to the metallization layer. In an alternative embodiment, the circuit module further includes one or more additional metallization layers of the semiconductor device circuitry between the metallization layer and the upper metallization layer. In another embodiment the circuit module further comprises an electrical coupling of the first upper contact to a contact of a separate integrated circuit. In still another embodiment, the upper metallization layer includes an uppermost metallization layer of the semiconductor device circuitry.

In another embodiment of the circuit module, the semiconductor device circuitry is operable to implement a receiver or transmitter circuit. In a further embodiment, the circuit module further includes a second trench formed in the semiconductor substrate and a second conductive trench liner covering a floor and sidewalls of the second trench. A second conductor within the metallization layer of the semiconductor device circuitry electrically connects to the second conductive trench liner, the insulating structure is further arranged over the second conductive trench liner and filling the second trench, the insulating structure further extends to a second upper contact formed within the upper metallization layer of the semiconductor device circuitry and overlying a central portion of the second trench, and a second isolation capacitor operable between the second upper contact and the second conductive trench liner has one or more electrical properties dependent on both a depth of the second trench and the number of metallization layers below the upper metallization layer in the semiconductor device circuitry.

An embodiment of a method disclosed herein includes forming one or more semiconductor devices in a circuitry region of a semiconductor substrate, depositing an interlevel dielectric over the semiconductor substrate containing the one or more semiconductor devices, and forming, in an isolator region of the semiconductor substrate, a first trench into the semiconductor substrate. The embodiment further includes forming a first conductive trench liner covering a floor and sidewalls of the first trench, depositing a trench fill dielectric over the first conductive trench liner and substantially filling the first trench, and forming a metallization layer over the first interlevel dielectric. A first conductor within the metallization layer electrically connects to the first conductive trench liner, and the metallization layer includes an interconnect for the one or more semiconductor devices. The embodiment further includes depositing a first intermetal dielectric over the substrate containing the first trench and the metallization layer and forming an upper metallization layer above the first intermetal dielectric layer, where the upper metallization layer comprises a first upper contact overlying a central portion of the first trench.

In a further embodiment of the method, forming the upper metallization layer above the first intermetal dielectric layer includes forming one or more additional metallization layers, covered by one or more respective additional intermetal dielectric layers, between the first intermetal dielectric layer and the upper metallization layer.

In another embodiment of the method, forming the one or more semiconductor devices includes forming components of circuitry operable as a receiver or transmitter circuit. A further embodiment also includes forming, in the isolator region of the semiconductor substrate, a second trench into the semiconductor substrate, forming a second conductive trench liner covering a floor and sidewalls of the second trench, and depositing the trench fill dielectric over the second conductive trench liner and substantially filling the second trench. A second conductor within the metallization layer electrically connects to the second conductive trench liner, depositing the first intermetal dielectric layer includes depositing the first intermetal dielectric layer over the substrate containing the first trench, second trench and metallization layer, and the upper metallization layer further includes a second upper contact overlying a central portion of the second trench.

An embodiment disclosed herein of a circuit module including an integrated circuit includes a first trench formed in a first semiconductor substrate, a first conductive trench liner covering a floor and sidewalls of the first trench, first semiconductor device circuitry formed in the first semiconductor substrate and an insulating structure arranged over the first conductive trench liner and filling the first trench. A first conductor within a metallization layer of the first semiconductor device circuitry electrically connects to the first conductive trench liner, and the insulating structure extends to a first upper contact formed within an upper metallization layer of the first semiconductor device circuitry and overlying a central portion of the first trench. The embodiment further includes a second integrated circuit comprising second semiconductor device circuitry formed in a second semiconductor substrate and an electrical coupling between the first upper contact and a first contact pad of the second integrated circuit. In a further embodiment, the electrical coupling includes a wire bond connection.

In a further embodiment of the circuit module, one of the first semiconductor circuitry and second semiconductor circuitry is operable to implement a receiver circuit, and the other of the first semiconductor circuitry and second semiconductor circuitry is operable to implement a transmitter circuit. A still further embodiment of the circuit module further includes a second trench formed in the first semiconductor substrate, a second conductive trench liner covering a floor and sidewalls of the second trench, and an electrical coupling between the second upper contact and a second contact pad of the second integrated circuit. The insulating structure is further arranged over the second conductive trench liner and filling the second trench, and the insulating structure further extends to a second upper contact formed within the upper metallization layer of the first semiconductor device circuitry and overlying a portion of the second trench.

In another embodiment of the circuit module, one or both of the first semiconductor substrate or second semiconductor substrate is an upper layer of a semiconductor on insulator substrate. In still another embodiment, the upper metallization layer of the first semiconductor device circuitry is connected by one or more vias to the metallization layer. An alternative embodiment further includes one or more additional metallization layers of the first semiconductor device circuitry between the metallization layer and the upper metallization layer.