Insulated gate semiconductor device with improved short-circuit tolerance

In an insulated gate semiconductor device, a loss is suppressed and a short-circuit tolerance as well as a latch-up tolerance are improved. A saturation current I.sub.CE (sat) and a short-circuit tolerance tw are reduced without much influencing a collector-emitter saturation voltage V.sub.CE (sat) by setting a sheet resistance of an n-type emitter region 4 at a large value. When the sheet resistance is in the range between 40.OMEGA./.quadrature. and 150.OMEGA./.quadrature., 10 .mu.sec or more of the short-circuit tolerance, which is practically sufficient, is ensured while the collector-emitter saturation voltage V.sub.CE (sat) is suppressed to practically small 2.4 V or less. Both the collector-emitter saturation voltage V.sub.CE (sat) and the saturation current I.sub.CE (sat) are restrained small, thereby realizing an enhanced short-circuit tolerance.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to an insulated gate semiconductor device 
such as an insulated gate bipolar transistor (hereinafter referred to as 
an IGBT) and a method of fabricating the same. More particularly, the 
invention relates to an improvement in short-circuit tolerance. 
2. Description of the Background Art 
&lt;1. Structure of Conventional Device&gt; 
FIG. 40 is a plan view of a conventional N-channel IGBT 100. The IGBT 100 
comprises a multiplicity of IGBT elements (hereinafter referred to as IGBT 
unit cells) 110 connected in parallel, only one of which is illustrated. 
An emitter electrode 7 and an oxide film 8 to be described later with 
reference to FIG. 41 are not illustrated in FIG. 40. The configurations of 
various mask patterns to be used in the process steps for fabricating the 
IGBT 100 are also shown in FIG. 40. FIGS. 41 and 42 are cross-sectional 
views of one of the IGBT unit cells 110 taken along the lines A--A and 
B--B of FIG. 40, respectively. A circuit diagram of an equivalent circuit 
of the IGBT unit cell 110 is also illustrated in FIG. 41. 
Referring to FIGS. 41 and 42, the IGBT unit cell 110 includes a p-type 
collector layer 1 which is a p-type semiconductor substrate and an n-type 
epitaxial layer 2. The layers 1 and 2 form a semiconductor body 120. A 
p-type base region 3 is formed in a partial region in the top major 
surface of the n-type epitaxial layer 2 of the semiconductor body 120 by 
selective diffusion of p-type impurities. In a partial region in the top 
major surface of the semiconductor body 120 are also formed n-type emitter 
regions 4 by selective diffusion of n-type impurities. A gate insulating 
film 5 is formed to cover the top surface of the p-type base region 3 
between the top surface of the n-type epitaxial layer 2 and the top major 
surface of the n-type emitter regions 4. The gate insulating films 5 for 
adjacent IGBT unit cells 110 are integrally formed on the top surface of 
the n-type epitaxial layer 2. A gate electrode 6 made of, for example, 
polycrystalline silicon (hereinafter referred to as polysilicon) is formed 
on the gate insulating film 5. The emitter electrode 7 made of, for 
example, aluminum is formed such that it is electrically connected to both 
the p-type base region 3 and the n-type emitter regions 4. The gate 
electrode 6 and the emitter electrode 7 are insulated from each other by 
an oxide film 8 serving as an inter-layer insulating film, and are 
electrically connected in common in and between all of the IGBT unit cells 
110. A high-concentration p-type semiconductor region 31 is formed in the 
p-type base region 3 through diffusion of p-type impurities at high 
concentration in a pattern which surrounds the n-type emitter regions 4. A 
collector electrode 9 made of metal is formed on the bottom major surface 
of the p-type collector layer 1 integrally for all of the IGBT unit cells 
110. 
As shown in FIG. 40, the IGBT cell 110 has regions in which the n-type 
emitter regions 4 are relatively wide as viewed from the top and regions 
in which they are relatively narrow. The region around the line A--A is 
one of the former regions while the region around the line B--B is one of 
the latter regions. The dotted lines of FIG. 40 represent a mask pattern 
51 to be used for formation of the gate electrode 6, a mask pattern 52 to 
be used for formation of the high-concentration p-type semiconductor 
region 31, and a mask pattern 53 to be used for formation of the n-type 
emitter regions 4 in a process of fabricating the IGBT 100. 
&lt;2. Operation of Conventional Device&gt; 
Referring to FIG. 41, the IGBT unit cell 110 includes an insulated gate 
field effect transistor MOS, which may be a metal-oxide-semiconductor 
transistor and is hereinafter referred to as an MOSFET, a pnp bipolar 
transistor Tr1, an npn bipolar transistor Tr2, and a resistance Rb. These 
elements are equivalently connected to each other as shown in the 
equivalent circuit diagram FIG. 41. 
When a gate voltage V.sub.GE is applied across the gate and emitter 
electrodes 6 and 7 with a collector voltage V.sub.CE applied across the 
collector and emitter electrodes 9 and 7, the p-type semiconductor in the 
top surface of the p-type base region 3 between the n-type emitter regions 
4 and n-type epitaxial layer 2 is inverted into an n-type semiconductor to 
form n-type channels. Then conduction is permitted between the n-type 
epitaxial layer 2 serving as a drain of the MOSFET and the n-type emitter 
regions 4 serving as a source thereof, and an electronic current flows 
from the n-type emitter regions 4 through the n-type channels into the 
n-type epitaxial layer 2. The electronic current serves as a base current 
for the transistor Tr1. In response to the electronic current, holes are 
introduced from the p-type collector layer 1 into the n-type epitaxial 
layer 2. Some of the introduced holes are recombined with the carrier 
electrons in the n-type epitaxial layer 2, and the other holes flow 
through the p-type base region 3 into the emitter electrode 7 to provide a 
hole current. As a result, the IGBT 100 conducts or turns on, that is, 
conduction is permitted across the collector and emitter electrodes 9 and 
7. 
The IGBT 100, a voltage-controlled transistor having insulated gates (MOS 
gates) like the MOSFET, is advantageous in that a drive circuit of the 
IGBT 100 is constructed more simply than that of bipolar transistors and 
in that a collector-emitter saturation voltage (ON-voltage) lower than 
that of the MOSFET is achieved. The latter advantage is provided because 
the holes introduced from the p-type collector layer 1 into the n-type 
epitaxial layer 2 cause a conductivity modulation so that the resistance 
of the n-type epitaxial layer 2 effectively becomes low. 
When the gate voltage V.sub.GE is a zero voltage or is zero-biased or when 
it is a negative voltage or is negatively biased, the MOSFET enters a 
cut-off state so that the electronic current slops flowing. As a result, 
the IGBT 100 is cut off. However, accumulated holes remain in the n-type 
epitaxial layer 2 during the transition period in which the transition 
from ON to OFF starts. A certain period of time (turn-off time) is 
required for the holes accumulated in the course of the transition to 
disappear. During the turn-off period, the hole current continues flowing 
while decaying. The accumulated holes are useful for achieving a low 
saturation voltage when the IGBT 100 is on but are a factor prolonging the 
turn-off time when the IGBT 100 turns off. Hence the amount of holes to be 
introduced in the ON-state or the lifetime thereof should be optimized. 
The IGBT unit cell 110 includes a parasitic thyristor formed by the n-type 
emitter regions 4, the p-type base region 3, the n-type epitaxial layer 2 
and the p-type collector layer 1. The parasitic effect which is turn-on of 
the parasitic thyristor associated with the operation of the IGBT 100 
sometimes prevents the original function of the IGBT 100. It is therefore 
necessary to suppress the parasitic effect. One of the effective 
approaches for suppression of the parasitic effect is to decrease the 
lateral resistance Rb of a part of the p-type base region 3 which lies 
just under the n-type emitter regions 4. For decrease in the resistance 
Rb, there has been proposed an arrangement shown in FIGS. 41 and 42 in 
which the high-concentration p-type semiconductor region 31 is provided 
just under the n-type emitter regions 4, which is disclosed in Japanese 
Patent Application Laid-Open No. 60-196974 (1985), for example. As 
illustrated in FIGS. 41 and 42, the high-concentration p-type 
semiconductor region 31 is formed on the inside of the n-type emitter 
regions 4 for the purpose of exerting no influence on a gate threshold 
voltage. That is, the high-concentration p-type semiconductor region 31 is 
formed such that the region 31 itself is not included in the n-type 
channels to be formed in the p-type base region 3 when the gate voltage 
V.sub.GE is applied. 
&lt;3. Disadvantage of Conventional Device&gt; 
The IGBT 100 is often used for an inverter device and the like. It is hence 
necessary that the IGBT 100 is not broken down when the inverter device is 
short-circuited or when the IGBT 100 turns on with a short-circuit voltage 
applied thereto. The resistance to short-circuit of the IGBT 100 
(short-circuit tolerance) decreases in proportion to the product of the 
voltage and the current when the IGBT 100 is short-circuited and a 
short-circuit time. The IGBT 100 having a small chip area, in particular, 
has a low short-circuit tolerance. 
The voltage at the time of short-circuit and the short-circuit time are 
determined by the conditions under which the IGBT 100 is used, e.g., the 
operating conditions of the inverter. Since the IGBT 100, when 
short-circuited, is saturated, the current at the time of the 
short-circuit is just a saturation current I.sub.CE (sat) of the IGBT 100. 
The establishment of a low saturation current I.sub.CE (sat) is effective 
for improving the short-circuit tolerance. The saturation current I.sub.CE 
(sat) is determined by: 
##EQU1## 
where: 
.alpha.pnp is a current transfer ratio of the pnp transistor; 
C.sub.ox is a gate capacitance; 
.mu.n is a surface mobility; 
W is a channel width; 
L is a channel length; 
V.sub.GE is the gate voltage; and 
V.sub.GE (th) is the gate threshold voltage. 
For reduction in losses where the IGBT 100 is applied as a switching 
clement to the inverter and the like, a small collector-emitter saturation 
voltage V.sub.CE (sat) is required. One of the effective schemes to 
decrease a collector-emitter saturation voltage V.sub.CE (sat) is to 
improve the electrical characteristics of a portion corresponding to the 
MOSFET (the portion MOS of FIG. 41) in the IGBT unit cell 110 to reduce a 
drop voltage when the MOS is conducting. For example, a shallow diffusion 
is carried out in a diffusing step for forming the p-type base region 3 to 
shorten the channel length L of the MOS. Otherwise, the IGBT unit cell 110 
is reduced in size and increased in density by reducing the width of the 
p-type base region 3 (the whole lateral width of the p-type base region 3 
of FIGS. 41, 42), to thereby relatively increase the total of the channel 
widths W for the whole IGBT 100. 
However, either shortening the channel length L or increasing the channel 
width W for reduction in collector-emitter saturation voltage V.sub.CE 
(sat) is accompanied by increase in saturation current I.sub.CE (sat) as 
will be understood from Formula (1). Then the parasitic thyristor causes 
latch-up to break down the IGBT 100, or otherwise the product of the 
voltage and current at the time of short-circuit grows large, so that the 
short-circuit tolerance falls off. The conventional IGBT 100 is, 
therefore, disadvantageous in that low losses when used as a switching 
clement cannot coexist with high short-circuit tolerance. 
SUMMARY OF THE INVENTION 
According to the present invention, an insulated gate semiconductor device 
comprises: (a) a semiconductor body comprising: (a-1) a first 
semiconductor region of a first conductivity type exposed at a top major 
surface of the semiconductor body; (a-2) a second semiconductor region of 
a second conductivity type selectively formed in a top surface portion of 
the first semiconductor region and selectively exposed at the top major 
surface of the semiconductor body; (a-3) a third semiconductor region of 
the first conductivity type selectively formed in a top surface portion of 
the second semiconductor region and exposed at the top major surface of 
the semiconductor body on the inside of a peripheral edge portion of the 
exposed surface of the second semiconductor region, wherein the third 
semiconductor region defines a pattern on the top major surface of the 
semiconductor body, the pattern including a pair of strip areas arranged 
in parallel across a central area; (a-4) a fourth semiconductor region of 
the second conductivity type having an impurity concentration higher than 
an impurity concentration of the second semiconductor region and 
selectively formed in a top surface portion of the semiconductor body so 
as to surround the third semiconductor region, the fourth semiconductor 
region comprising: a first portion exposed at the top major surface of the 
semiconductor body in the central area; and a second portion exposed at 
the top major surface of the semiconductor body in an external area 
selectively defined on the outside of the pair of strip areas; (b) an 
insulating layer selectively formed on the top major surface of the 
semiconductor body and having an opening on a predetermined region 
covering part of the pair of strip areas and at least part of the central 
area; (c) a control electrode layer buried in the insulating layer and 
opposed to the exposed surfaces of the second semiconductor region and the 
second portion of the fourth semiconductor region between the pair of 
strip areas of the third semiconductor region and the exposed surface of 
the first semiconductor region; (d) a first main electrode layer formed in 
the opening and electrically connected to a portion of the top major 
surface of the semiconductor body exposed in the opening; and (e) a second 
main electrode layer formed on a bottom major surface of the semiconductor 
body and electrically connected to the semiconductor body. 
In the insulated gate semiconductor device of the present invention, the 
first and third semiconductor regions of the first conductivity type are 
exposed at the top major surface of the semiconductor body. In some 
portions, the second semiconductor region of the second conductivity type 
is exposed throughout the section between the exposed surfaces of the 
first and third semiconductor regions. In the other portions, the fourth 
semiconductor region of the second conductivity type having the high 
impurity concentration is partially exposed in the section. The control 
electrode layer is opposed to the section. When a voltage is applied to 
the control electrode layer, an inverted layer is formed in the section so 
that conduction is permitted between the first and third semiconductor 
regions. Since the second semiconductor region has the relatively low 
impurity concentration of the second conductivity type and the fourth 
semiconductor region has the relatively high impurity concentration, a 
gate threshold voltage V.sub.GE (th) to be applied to the control 
electrode layer for the formation of the inverted layer is relatively low 
in the former portions and relatively high in the latter portions in the 
section. 
The insulated gate semiconductor device includes the portions having a 
relatively low gate threshold voltage V.sub.GE (th) and a relatively high 
gate threshold voltage V.sub.GE (th) which are connected in parallel in 
the section in which the inverted layer is to be formed. The gate 
threshold voltage of the device mainly depends on the portion having the 
low gate threshold voltage V.sub.GE (th) and is not largely varied by the 
provision of the portion having the high gate threshold voltage V.sub.GE 
(th). An collector-emitter saturation voltage V.sub.CE (sat) is not 
largely affected by the provision of the portion having the high gate 
threshold voltage V.sub.GE (th). On the other hand, a saturation current 
I.sub.CE strongly depends on the percentage of the portion having the high 
gate threshold voltage V.sub.GE (th) and is decreased as the percentage 
increases. Increase in saturation current I.sub.CE (sat) generated by size 
reduction and density increase of the semiconductor device is prevented by 
the provision of the portion having the high gate threshold voltage 
V.sub.GE (th). By optimizing the distribution of the portions having the 
high and low gate threshold voltage V.sub.GE (th) for the small and dense 
semiconductor devices which provide a low collector-emitter saturation 
voltage V.sub.CE (sat) and low losses, the saturation current I.sub.CE 
(sat) is reduced to achieve a semiconductor device having a high 
short-circuit tolerance. 
Preferably, the first main electrode contacts exposed portions of the third 
and fourth semiconductor regions in the opening, the exposed portions of 
the third semiconductor region contacting the first main electrode have an 
area A1, the exposed portions of the fourth semiconductor region 
contacting the first main electrode have an area A2, and a ratio 
A1/(A1+A2) is less than 50%. 
The ratio of the third and fourth semiconductor regions electrically 
connected to the first main electrode layer is optimized, so that a small 
saturation current I.sub.CE (sat) and, accordingly, a high short-circuit 
tolerance are provided. 
The ratio A1/(A1+A2) may be 5% to 25%. 
In this insulated gate semiconductor device, the emitter bypass ratio, 
which is a ratio of the area size of the pair of the exposed strip areas, 
i.e., the third semiconductor region, at the opening to the area size of 
the opening to which the first main electrode layer is connected in the 
top major surface of the semiconductor body, is 5% to 25%. The less the 
emitter bypass ratio is, the higher the effective resistance of the third 
semiconductor region becomes, thereby improving the short-circuit 
tolerance. Since the emitter bypass ratio is not more than 25% including a 
predetermined extra amount of tolerance, 10 .mu.sec or more of the 
short-circuit tolerance, which is practically sufficient, is ensured. 
Since the emitter bypass ratio is not less than 5%, the collector-emitter 
saturation voltage V.sub.CE (sat) has a practically small value. 
Preferably, the external area comprises a plurality of unit external areas 
periodically aligned at a predetermined period (H+L) in an elongated 
direction of the pair of strip areas, and a percentage of the length (H) 
of each unit external area in the elongated direction of the pair of strip 
areas to the period (H+L) is not less than 20%. 
The percentage of the part of the pair of strip areas bordering on the 
external area, that is, the percentage of the inverted layer having the 
relatively high gate threshold voltage V.sub.GE (th) is optimized, so that 
the small saturation current I.sub.CE (sat) and, accordingly, the high 
short-circuit tolerance are provided. 
Preferably, the sheet resistance of the third semiconductor region is equal 
to or larger than a critical sheet resistance which is determined by a 
predetermined short-circuit tolerance. 
In this insulated gate semiconductor device, the sheet resistance of the 
third semiconductor region is equal to or larger than the critical sheet 
resistance which is determined by the predetermined short-circuit 
tolerance. With an increase in the sheet resistance of the third 
semiconductor region, an effective resistance value increases and the 
short-circuit tolerance improves. Since the sheet resistance of the third 
semiconductor region is set at or larger than the critical sheet 
resistance, a desired short-circuit tolerance is secured. 
Preferably, the sheet resistance is in the range between 
40.OMEGA./.quadrature. and 150.OMEGA./.quadrature.. 
In this insulated gate semiconductor device, the sheet resistance of the 
third semiconductor region is in the range between 40.OMEGA./.quadrature. 
and 150.OMEGA./.quadrature.. Hence, 10 .mu.sec or more short-circuit 
tolerance, which is a tolerance practically competent, is ensured while a 
practically competent amount of the collector-emitter saturation voltage 
V.sub.CE (sat) is obtained. 
Preferably, the sheet resistance of the control electrode layer is not more 
than 250 .OMEGA./.quadrature.. 
In this insulated gate semiconductor device, the sheet resistance of the 
control electrode layer is not more than 250.OMEGA./.quadrature.. As the 
sheet resistance of the control electrode layer decreases, the switching 
operation of the device becomes fast, thereby reducing a loss at the 
device switching operation. Since the sheet resistance is not more than 
250.OMEGA./.quadrature., a low switching loss which is practically 
desirable is obtained. 
The present invention is also directed to a method of fabricating an 
insulated gate semiconductor device. 
According to the present invention, the method of fabricating an insulated 
gate semiconductor device comprises the steps of: (a) providing a 
semiconductor body including a first semiconductor region of a first 
conductivity type exposed at a top major surface of the semiconductor 
body; (b) forming an oxide film on the top major surface of the 
semiconductor body; (c) forming a control electrode layer having a first 
opening of a substantially strip configuration on the oxide film; (d) 
obtaining a second semiconductor region of the second conductivity type 
under the first opening, wherein the second semiconductor region 
selectively extending to part of the semiconductor body underlying the 
control electrode layer; (e) selectively providing a mask pattern on the 
oxide film and the control electrode layer, the mask pattern being 
provided with a second opening partially overlapped with the first 
opening; (f) obtaining in the semiconductor body under the second opening 
a third semiconductor region of the second conductivity type having a 
impurity concentration higher than the impurity concentration of the 
second semiconductor region, wherein third semiconductor region 
selectively extends to part of the semiconductor body underlying the 
control electrode layer; (g) selectively removing a portion of the oxide 
film lying under the first opening to obtain a pair of strip windows 
arranged substantially in parallel and an oxide region remaining on a 
central area defined between the pair of strip windows; (h) selectively 
introducing a first impurity of the first conductivity type into the top 
major surface of the semiconductor body using the oxide region and the 
oxide film lying under the control electrode layer as a mask to obtain a 
fourth semiconductor region of the first conductivity type in the third 
semiconductor region, the fourth semiconductor region selectively exposed 
to the top major surface to define a pair of strip areas on the top major 
surface; (i) removing the oxide region; (j) forming an insulating layer 
having a third opening on a predetermined region of the top major surface 
of the semiconductor body covering part of the pair of strip areas and at 
least part of the central area, the insulating layer covering side and top 
surfaces of the control electrode layer; (k) providing in the third 
opening a first main electrode layer electrically connected to the top 
major surface of the semiconductor body; and (l) forming on a bottom major 
surface of the semiconductor body a second main electrode layer 
electrically connected to the bottom major surface of the semiconductor 
body. 
The method of the present invention affords the fabrication of the 
insulated gate semiconductor device having the foregoing advantages. 
Accordingly, an object of the present invention is to provide an insulated 
gate semiconductor device having a high short-circuit tolerance and an 
improved latch-up tolerance with low losses. 
A further object of the present invention is to provide an insulated gate 
semiconductor device in which a switching-induced loss is suppressed low. 
Another object of the invention is to provide a method of suitably 
fabricating the semiconductor device. 
These and other objects, features, aspects and advantages of the present 
invention will become more apparent from the following detailed 
description of the present invention when taken in conjunction with the 
accompanying drawings.