DEEP VIA WITH INTERNAL VOID FOR STRESS MITIGATION

A deep-via structure includes at least one via-interfacing layer. The deep-via structure also includes a via. The via is embedded within the at least one via-interfacing layer. The via includes a conductive material. The deep-via structure also includes a stress-relief void that is formed within the conductive material of the via.

BACKGROUND

The present invention relates to microcircuitry connection, and more specifically, to deep vias.

Some circuitry chips (e.g., microprocessor chips, memory chips) include vias to electrically connect layers of those chips. Vias typically take the form of a trench that is etched and then filled with a conductive material. An electrical signal from the circuitry in one layer may travel through the via to the circuitry in a second layer.

Typical vias may be approximately 10 nm wide and span several layers of a chip. Some designs also include significantly larger vias. These significantly larger vias may, depending on the use case, sometimes be referred to as “deep vias” or, in some specific use cases, “through-silicon vias” or “through-chip vias.” Deep vias may be 10,000 nm (10 microns) or even 15,000 nm (15 microns) wide and span 100,000 nm (100 microns) of a chip. These larger vias may sometimes be used to connect a chip to another system component (e.g., to a ball-grid array) or to connect different areas of the same chip.

SUMMARY

Some embodiments of the present disclosure can be illustrated as a deep-via structure. The deep-via structure comprises a via-interfacing layer. The deep-via structure also comprises a via that is embedded within the via-interfacing layer. The via comprises a conductive material. The deep-via structure also comprises a stress-relief void that is formed within the via.

Some embodiments of the present disclosure can also be illustrated as a microprocessor chip. The microprocessor chip comprises a first deep via structure and a second deep via structure. The first deep-via structure comprises a first via-interfacing layer and a first via that is embedded within the first via-interfacing layer. The first via comprises a conductive material. The first deep-via structure comprises a first stress-relief void that is formed within the first via. The second deep-via structure comprises a second via-interfacing layer. The second deep-via structure comprises a second via that is embedded within the second via-interfacing layer. The second via comprises a conductive material. The second deep-via structure also comprises a second stress-relief void that is formed within the second via.

DETAILED DESCRIPTION

In microcircuitry, vias typically take the form of trenches filled with conductive material that primarily extends from and perpendicular to a layer in a chip. The dimension in which these vias primarily extend is often referred to as a “vertical” dimension with respect to the plane of the circuitry layer. Some vias, for example, are used to enable signals to travel between two circuitry layers in a microprocessor or between a bit line and a word line in a memory chip. These vias may sometimes be referred to as standard via interconnects. Standard via interconnects are typically used in middle-of-the-line layers and back-end-of-the-line layers. Standard via interconnects are often relatively similar in size to the node size in the design in which they are installed. A standard via interconnect may be 10 nm to 50 nm wide, for example, and 20 nm to 100 nm deep.

Some vias, however, are designed to be significantly larger than a standard via interconnect. These vias are often referred to herein as “deep vias.” These deep vias often span a vertical distance through a large amount of a dielectric material (e.g., silicon). Like standard via interconnects, these deep vias may often be used to connect two circuitry layers, but rather than connecting adjacent or near-adjacent layers, these deep vias may be used to connect layers at two sections of a chip that are 100,000 nm (100 microns) apart. Some deep vias may also be used to connect a circuitry layer to an interconnect layer, such as a series of solder balls in a ball-grid array. Rather than approximately 10 nm wide, these deep vias may be 10,000 nm (10 microns) wide or wider.

Like a standard via interconnect, deep vias are typically filled with conductive material such as copper, tungsten, cobalt, and ruthenium. This results in an extremely large amount of conductive material as compared to the size of the typical wires, transistors, and standard via interconnects that may be found in the circuitry layers near these deep vias. This relatively large mass of conductive material in a typical deep via can, in certain circumstances, cause high levels of mechanical stress to the nearby structures in a chip.

For example, the conductive material within a deep via can heat and cool during use of the device into which the deep via is installed. As the conductive material heats and cools, it expands and contracts. Because of the relatively large mass of the conductive material, this expansion and contraction can result in a similarly relatively large application of force upon the relatively small structures towards which and away from which the conductive material is expanding and contracting. Put another way, a thermal expansion may result in a small percentage increase in the width of a deep via that is normally 15,000 nm (15 microns) wide. However, a small percentage increase in a 15,000 nm wide deep via may have disproportionately large effects on a nearby structure that is only 10 nm wide. These effects may include a mechanical force being applied to the structure and components around the structure shifting position.

As a result, structures near deep vias may be particularly sensitive to the operating temperature of the device (e.g., memory chip) or the operating temperature of the deep via itself. This may cause device instability, including circuits performing inconsistently or becoming non-functional when the temperature at a deep via reaches (or cools to) a certain level. In some instances, this instability may be eliminated when the temperature at the deep via returns to normal levels. However, in some instances the mechanical stress caused by the deep via expansion may result in permanent damage to nearby structures.

One method of addressing the stress caused by thermal expansion and contraction is to design a keep-out zone around deep vias. These keep-out zones may reserve a relatively large amount of space surrounding a deep via for stress absorption. Designs with these keep-out zones typically do not allow smaller structures to be placed in the keep-out zone.

However, in order to increase their chances of efficacy, these keep-out zones are typically also relatively large. For example, a keep-out zone of a deep via with a 15,000 nm (15 microns) diameter may surround the deep via with 5,000 nm (5 microns) of reserved space. This would result in a circular area with a 25,000 nm (25 microns) diameter in which devices cannot be formed. In a design in which the node size may be 10 nm, an area of 25,000 nm in which devices cannot be formed would represent a significant amount of space.

To address some of the above problems, some embodiments of the present disclosure include a deep via with a stress-absorbing void embedded within the conductive material. This void may be located within the horizontal center of the conductive material, and may be filled, for example, with air, another gas, a vacuum or a near vacuum.

Some embodiments of the present disclosure may form a via with a stress-absorbing void with two sections. A first, wider section may contain the stress-absorbing void. A second, narrower section may be sealed during formation, encapsulating the void within the first section. For example, filling a deep via trench with the described first and second section with a conformal application of a conductive material from the second-narrower section of the trench may cause the narrower section of the trench to seal before the wider section of the trench is filled with conductive material. This incomplete filling of the wider section may result in a stress-absorbing void to remain within the wider section.

The conductive material within a deep via that contains a stress-absorbing void may still expand and contract when heated and cooled. However, the conductive material may be capable of expanding into the void within the via rather than outward toward the surrounding structures. This inward expansion may reduce the extent to which the conductive material expands into and exerts force on smaller, surrounding structures of the device. This, in turn, may reduce the necessary size of keep-out zones near deep vias, or eliminate the need for keep-out zones entirely.

FIG.1, for example, discloses a deep-via structure100with stress-relief void102within deep via108and bi-layer dielectric104. Deep-via structure100is formed upon substrate106, which may contain, for example, chip circuitry (e.g., front-end-of-the-line devices), inter-layer contacts (e.g., middle-of-the-line contacts), or inter-chip connections (e.g., back-end-of-the-line dielectic and wiring, connection to a land-grid array). Deep-via structure100may be, for example an interposer. Deep via108may, for example, be integrated into a microprocessor chip and connect to one or more layers of the microprocessor chip. For example, deep via108may be formed as a “via-first” through-silicon via, and may thus be integrated into a substrate of the microprocessor chip and connect to a front-end-of-the-line (“FEOL”) layer of the chip. Deep via108may also be formed as a “via-middle” through-silicon via, and may thus pass through a substrate of the microprocessor chip, and potentially the FEOL layer of the microprocessor chip, and connect to a metal layer in a back-end-of-the-line (“BEOL”) layer of the chip (i.e., at or near the connection between the FEOL layer and the BEOL layer). Deep via108may also be formed as a “via-last” through-silicon via, and may thus span the depth of a substrate, FEOL layer, and BEOL layer of the microprocessor chip and connect to the back side of the BEOL layer of the chip (i.e., at or near the end of the BEOL layer that is opposite to the connection between the FEOL layer and the BEOL layer).

In some embodiments, deep via108may act as an interposer between two microprocessor chips. For example, deep via108may connect a first microprocessor chip to a second microprocessor chip. This may include for example, one end of deep via108connecting to the FEOL layer of the first microprocessor chip. Deep via108may then pass through a substrate and connect to the BEOL layer of a second microprocessor chip.

Deep-via structure100contains deep via108, which is filled with stress-relief void102and conductive material110. Conductive material110may include, for example, copper or tungsten. Stress-relief void102, on the other hand, is characterized as a space within conductive material110. For example, stress-relief void102could take the form of an air space trapped within the tungsten of conductive material110. The precise composition of stress-relief void may depend on the environment in which conductive material110was applied within deep via108. If conductive material was applied in a vacuum, stress-relief void102could be a vacuum. In theory, stress-relief void could also be a non-air gas or a liquid. The formation of a stress-relief void is detailed, for example, inFIGS.3G-3L.

Deep via108is illustrated as containing a first section112, second section114, major dimension116, and minor dimension118. “Major dimension,” as used herein, refers to the larger dimension of a structural element, whereas “minor dimension,” as used herein, refers to the smaller dimension of a structural element. In this example, deep via108is illustrated as taller than it is wide, and thus the height of deep via108is referred to as major dimension116. Thus, the width of deep via108is, as illustrated, considered to be perpendicular to major dimension116.

As illustrated, therefore, deep via108has two widths that are perpendicular to major dimension116. First section112has a first width that is perpendicular to major dimension116, and second section114has a second width that is perpendicular to major dimension116. The width of first section112is greater than the width of second section114.

Bi-layer dielectric104contains a first dielectric120and second dielectric122that is formed upon first dielectric120. Because they both at least partially surround and touch conductive material110in deep via108, both first dielectric120and second dielectric122may be referred to herein as via-interfacing layers. First dielectric120is formed upon substrate106, and may take the form of a dielectric with a low relative dielectric constant, such as silicon dioxide. Second dielectric122may be a dielectric that exhibits etch selectivity to first dielectric120(i.e., that is resistant to an etchant that can be used to selectively etch first dielectric120). This selective etching is discussed with respect toFIGS.3A-3L and4A-4L. If first dielectric120is silicon dioxide, for example, second dielectric122may be silicon nitride.

As illustrated, conductive material110interfaces with first dielectric120within first section112and interfaces with second dielectric122within second section114. As illustrated, stress-relief void102is embedded within conductive material110within first section112. However, in some embodiments, stress-relief void102may span into second section114.

Deep-via structure100has been described above as containing a bi-layer dielectric (i.e., first dielectric120and second dielectric122). In such embodiments, deep-via structure100may be, for example, an interposer. However, in some embodiments deep-via structure may take the form of a through-silicon via. In such embodiments, the overall structure of deep-via structure100that is illustrated inFIG.1may remain essentially the same, but the nature of specific components may differ. For example, in some embodiments the first via interfacing layer (i.e., first dielectric120) may actually take the form of a silicon layer. For this reason, first dielectric120or the alternative silicon layer could both generically be referred to as a via-interfacing layer, because they at least partially surround the conductive material110that forms most of deep via108.

In a through-silicon via, substrate106may take the form of a connection layer into which devices that the through-silicon via connects are embedded. In these embodiments, second dielectric122may remain a dielectric and may still be used to selectively etch the width of the silicon layer in first section112. However, in these embodiments, second dielectric122may be the only dielectric in deep-via structure100.

Of note, deep-via structure100can be described as having a thickness that is parallel to the major dimension116of deep via108. In other words, the thickness of deep-via structure100could be described as the distance between the top of substrate106and the top of second dielectric122or the top of conductive material110. In other words, major dimension116of deep via108, as illustrated, spans the thickness of deep-via structure110.

Also of note, the illustration ofFIG.1, as well as the illustrations presented inFIGS.2-4L, are intended to serve as abstract depictions for the purpose of understanding. For this reason, the relative sizes and shapes of the components of deep-via structure100, for example, are not intended to be precise representations of the real-life sizes and shapes of deep-via structure100when physically reduced to practice.

For example, whileFIG.1illustrates second dielectric122as approximately half as thick as first dielectric120, in practice second dielectric122may actually be significantly thinner than first dielectric120. In some embodiments, the thickness of second dielectric122may account for 10% of the total thickness of via310. In theory, second dielectric122may also actually be removed from deep-via structure100before device operation.

Similarly, the size and shape of stress-relief void102may vary based on the proportions of the remaining components of deep-via structure100as well as conditions under which conductive material110is applied within deep via108. For example, if first section112of deep via108is relatively thick (i.e., long in a dimension parallel to major dimension116) as compared to the width of deep via108at first section112and second section114, stress-relief void will also be relatively thick (i.e., long in a dimension parallel to major dimension116). As the width of deep via108at first section112increases as compared to the width of deep via108at second section114, the width of stress-relief void102is likely to increase. However, as the widths of deep via108at first section112and deep via108at second section114increase with respect to the overall thickness of deep via108, the thickness of stress-relief void102is likely to decrease. In some embodiments, the resistance of deep via108may be negatively impacted if the volume of stress-relief void102is too large or if stress-relief void102is too wide as compared to the width of deep via108. Thus, in some embodiments it may be beneficial to limit the volume and width of stress-relief void102. In some embodiments, therefore, the total volume of stress relief void102may be less than 10% of the total volume of deep via108.

FIG.2discloses a deep-via structure200with a stress-relief void202and a spacer element204. Similar to deep-via structure100, deep-via structure200is formed upon a substrate (substrate206) and contains deep via208that is filled with conductive material210and stress-relief void202. Deep via208also has two sections: first section212and a narrower second section214.

Deep-via structure200also includes dielectric220, which, as illustrated, spans the entire thickness of deep-via structure200. Within deep via208, conductive material210interfaces with dielectric220within first section212and interfaces with spacer element204within second section214. In other words, spacer element204takes the form of as a spacer between conductive material210and dielectric220within second section214. Similar to dielectric122, spacer element204may be a dielectric that is resistant to an etchant that can be used to selectively etch dielectric220. In some embodiments, spacer element204may slow be a non-dielectric material, such as a conductive material. This may reduce the overall resistance of deep via208. The formation of a spacer element, such as spacer element204, within a deep-via structure is illustrated inFIGS.4D-4F.

Similar toFIG.1, the precise composition, size, and shape of stress-relief void202may vary based on the relative sizes and shapes of sections212and214of deep via208.

Similar to deep-via structure100, deep-via structure200may also take the form of a through-silicon via. In these embodiments, dielectric220may take the form of a silicon layer, while spacer element204may still be a conductive material or a dielectric and may still be used to selectively etch the silicon in via208at section212.

FIGS.3A-3Lprovide example stages of forming a deep via with a stress-relief void in a bi-layer dielectric. While these stages do provide an example process of forming a deep via such as deep via108within deep-via structure100, these stages are not intended to be presented as the only possible or the most optimal stages of forming such a deep via or stress-relief void.

FIG.3Adiscloses a first stage of forming a deep via with a stress-relief void in a bi-layer dielectric. At this stage, only substrate302is present. Substrate302may contain, for example, chip circuitry (e.g., front-end-of-the-line devices), inter-layer contacts (e.g., middle-of-the-line contacts), or inter-chip connections (e.g., back-end-of-the-line dielectic and wiring, connection to a land-grid array).

FIG.3Bdiscloses a second stage of forming a deep via with a stress-relief void in a bi-layer dielectric. At this stage, a first dielectric304has been formed upon substrate302. First dielectric304may be designed to span the majority of the thickness of the eventual deep via, and may thus be formed as a relatively thick layer. First dielectric304may be SiO2or another low-k dielectric.

FIG.3Cdiscloses a third stage of forming a deep via with a stress-relief void with a stress-relief void in a bi-layer dielectric. At this stage, a second dielectric306is formed upon first dielectric304. Second dielectric306may be chosen from a variety of dielectrics with etching sensitivities that differ from the etching sensitivities of first dielectric304. For example, if first dielectric304is composed of SiO2, second dielectric may be composed of SiN.

FIG.3Ddiscloses a fourth stage of forming a deep via with a stress-relief void in a bi-layer dielectric. At this stage, via mask308is patterned onto second dielectric306. Via mask308may be selected based on its resistance to a directional etching that may be used to etch a via into first dielectric304and second dielectric306. For example, if first dielectric304is composed of SiO2and second dielectric is composed of SiN, via mask308may be composed of a metal nitride such as titanium nitride or tantalum nitride.

FIG.3Ediscloses a fifth stage of forming a deep via with a stress-relief void in a bi-layer dielectric. At this stage, deep via310has been etched into first dielectric304and second dielectric306. Deep via310may be etched, for example, using anisotropic etching such as reactive ion etching.FIG.3Fdiscloses a sixth stage of forming a deep via with a stress-relief void in a bi-layer dielectric. At this stage, via mask308is no longer needed and has been removed.

FIG.3Gdiscloses a seventh stage of forming a deep via with a stress-relief void in a bi-layer dielectric. At this stage, first dielectric304has been isotropically etched with an etchant to which second dielectric306is not sensitive. This results in two sections of deep via310: first section312and second section314. Because first section312occupies the portion of deep via310that is surfaced by first dielectric304, it has been etched and is wider than second section314as a result.

FIG.3Hdiscloses an eighth stage of forming a deep via with a stress-relief void in a bi-layer dielectric. At this stage, conductive material316has been partially applied into via310through conformal deposition. Conductive material316may be, for example, copper or tungsten. As can be seen, due to the different thicknesses of via310at first section312and second section314, the deposition pattern of conductive material316differs slightly between the two sections.

FIG.3Idiscloses a ninth stage of forming a deep via with a stress-relief void in a bi-layer dielectric. At this stage, conductive material316has been more completely applied into via310through continued conformal deposition. Again, due to the different thicknesses of via310at first section312and second section314, conductive material316has almost sealed via310in second section314while a larger void remains within first section312.

FIG.3Jdiscloses a tenth stage of forming a deep via with a stress-relief void in a bi-layer dielectric. At this stage, the conformal deposition of conductive material316has sealed second section314of via310before first section312of via310was filled. This has resulted in stress-relief void318. Stress-relief void318may be useful, for example, in absorbing mechanical stress that results from thermal expansion and contraction of conductive material316in via310during operation.

Of note, the conformal deposition of conductive material316within via310has also caused deposition of conductive material on top of second dielectric306. This excess conductive material can be etched in a planarization process after sealing second section314.

FIG.3Killustrates the result of a planarization step in which the excess conductive material316has been etched to the top of section314and second dielectric306. This is effectively the state illustrated by deep via structure100inFIG.1. This may be performed, for example, by performing chemical mechanical polishing (CMP) on conductive material316using a chemical slurry that does not readily corrode second dielectric306. This would effectively utilize second dielectric306as an etch stop.

Of further note, there may also be benefit to reduce the depth of deep-via structure300by removing conductive material316within second section314and removing second dielectric306. Thus, some embodiments may perform a planarization step in which deep via structure300is polished with a CMP chemical that strongly corrodes second dielectric306and conductive material316, but does not corrode first dielectric304.

FIG.3Lillustrates the result of such a planarization step. In some embodiments, the stages illustrated inFIGS.3K and3Lmay be part of a single planarization process. In other embodiments, the stage illustrated inFIG.3Kmay result from a first planarization process (for example, with a first CMP chemical) and the stage illustrated inFIG.3Lmay result from a second planarization process (for example, with a second CMP chemical).

Etching away deep via structure300to the top of first dielectric305, as illustrated inFIG.3L, may be considered an optional step inFIGS.3A-3L. In some use cases the reduction of depth of the deep via structure may be worth the added process complexity. In other use cases, however, the reduction of the depth may not result in significant enough benefits to make the more substantial etching worth performing. In these use cases, deep-via structure300may be finalized as illustrated inFIG.3K.

FIGS.4A-4Jprovide example stages of forming a deep via with a stress-relief void and a spacer dielectric. While these stages do provide an example process of forming a deep via such as deep via208within deep-via structure200, these stages are not intended to be presented as the only possible or the most optimal stages of forming such a deep via or stress-relief void.

FIG.4Adiscloses a first stage of forming a deep via with a stress-relief void and a spacer dielectric. At this stage, only substrate402is present.FIG.4Bdiscloses a second stage of forming a deep via with a stress-relief void and a spacer dielectric. At this stage, a first dielectric404has been formed upon substrate402. First dielectric404may be designed to span the entire thickness of the eventual deep via, and may thus be formed as a thick layer.

FIG.4Cdiscloses a third stage of forming a deep via with a stress-relief void and a spacer dielectric. At this stage, via mask406onto first dielectric404. Via mask406may be selected based on its resistance to a directional etching that may be used to etch a via into first dielectric404.

FIG.4Ddiscloses a fourth stage of forming a deep via with a stress-relief void and a spacer dielectric. At this stage, a first directional-etch process has been performed upon first dielectric404, resulting in the beginning of deep via408. In some embodiments, this etching may have been performed to a precise, pre-determined depth that is designed to correspond to the pre-determined depth of a narrow section of a via (similar to second sections114and214).

FIG.4Ediscloses a fifth stage of forming a deep via with a stress-relief void and a spacer dielectric. At this stage, a dielectric spacer410has been applied to the inner walls of the beginning of deep via408. In some embodiments, dielectric spacer410may have been applied through conformal deposition (e.g., atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition). In some embodiments, dielectric spacer410may have been etched to the shape shown inFIG.4Eusing directional anisotropic etch (e.g., reactive ion etching).

FIG.4Fdiscloses a sixth stage of forming a deep via with a stress-relief void and a spacer dielectric. At this stage, a second directional-etch process has been performed upon first dielectric404, resulting in the entire trench of deep via408being formed. Of note, spacer dielectric410and via mask406are not illustrated as being etched by this second directional-etch process because, in typical embodiments, they would both exhibit etch selectivity to first dielectric404. In practice, the top surfaces of both via mask406and spacer dielectric via mask406may be slightly eroded from this etch process. However, in typical embodiments, via mask406and spacer dielectric410may have been deposited thick enough past the top of first dielectric404that they are able to sustain that slight erosion. This partial erosion would, in most embodiments, become irrelevant when deep-via structure400is planarized during the removal of via mask406(and the corresponding top portion of spacer dielectric410).

FIG.4Gdiscloses a seventh stage of forming a deep via with a stress-relief void and a spacer dielectric. At this stage, via mask406and the corresponding top portion of dielectric spacer410have been removed. Further, first dielectric404has been isotropically etched with an etchant to which dielectric spacer410is not sensitive. This results in two sections of deep via408: first section412and second section414. Because first section412occupies the portion of deep via408that is surfaced by first dielectric404, it has been etched and is wider than second section414as a result.

FIG.4Hdiscloses an eighth stage of forming a deep via with a stress-relief void and a spacer dielectric. At this stage, conductive material416has been partially applied into via408through conformal deposition. As can be seen, due to the different thicknesses of via408at first section412and second section414, the deposition pattern of conductive material416differs slightly between the two sections.

FIG.4Idiscloses a ninth stage of forming a deep via with a stress-relief void and a spacer dielectric. At this stage, conductive material416has been more completely applied into via408through continued conformal deposition. Again, due to the different thicknesses of via408at first section412and second section414, conductive material416has almost sealed via408in second section414while a larger void remains within first section412.

FIG.4Jdiscloses a tenth stage of forming a deep via with a stress-relief void and a spacer dielectric. At this stage, the conformal deposition of conductive material416has sealed second section414of via408before first section412of via408was filled. This has resulted in stress-relief void418. Stress-relief void418may be useful, for example, in absorbing mechanical stress that results from thermal expansion and contraction of conductive material416in via408during operation.

Of note, the conformal deposition of conductive material416within via408has also caused deposition of conductive material on top of first dielectric404and spacer dielectric410. This excess conductive material can be etched in a planarization process after sealing second section414.

FIG.4Killustrates the result of a planarization step in which the excess conductive material416has been polished using CMP to the top of second section414, and first dielectric404, and spacer dielectric410. This is effectively the state illustrated by deep via structure200inFIG.2. This may be performed, for example, by polishing conductive material416using an chemical that does not readily corrode first dielectric404, spacer dielectric410, or both. This would effectively utilize one or both of first dielectric404and spacer dielectric410as an etch stop.

Of further note, there may also be benefit to reduce the depth of deep-via structure400by removing second section414of the deep via and the corresponding portions of first dielectric404and spacer dielectric410. Thus, some embodiments may perform a planarization step in which deep via structure400is etched with an chemical that corrodes all of conductive material416, first dielectric404, and spacer dielectric410.

FIG.4Lillustrates the result of such a planarization step. Unlike the planarization step that was performed to create the result illustrated inFIG.4K, it may not be feasible to use an etch stop to signal the completion of the desired etching of this planarization step. This is because all three components of deep via structure400above substrate402are being etched. However, it may be particularly important to avoid unwanted polishing into first section412, because polishing section412may open stress-relief void418, which may then be filled in later bonding or deposition steps. For this reason, this planarization step may be closely timed, rather than monitored for indications of hitting an etch-stop layer.

In some embodiments, the stages illustrated inFIGS.4K and4Lmay be part of a single planarization process. In other embodiments, the stage illustrated inFIG.4Kmay result from a first planarization process (for example, with a first chemical that does not readily corrode first dielectric404and spacer dielectric410) and the stage illustrated inFIG.4Lmay result from a second planarization process (for example, with a second chemical that does readily corrode first dielectric404and spacer dielectric410). While performing these two planarization steps separately may add process complication, it may also beneficially enable more accurate control of the second planarization step. Specifically, the first planarization step may cause deep-via structure400to have a very flat top surface with a known starting point (e.g., the top of first dielectric404). Beginning the second, timed planarization step from this known, precise starting point may therefore cause the timed control of the second planarization step to have more accurate and predictable results.

Similar to the result discussed inFIG.3L, polishing away deep via structure400to the top of first section412, as illustrated inFIG.4L, may be considered an optional step inFIGS.4A-4L. In some use cases the reduction of depth of the deep via structure may be worth the added process complexity. In other use cases, however, the reduction of the depth may not result in significant enough benefits to make the more substantial etching worth performing. In these use cases, deep-via structure400may be finalized as illustrated inFIG.4K.

FIG.5discloses a process500of forming a deep via with a stress-relief void. Process500is presented as a general process for the sake of understanding, and is intended to apply to various methods of forming a deep via with a stress-relief void in practice. For example, process500could be performed in a way that resulted in deep-via structure100, deep-via structure200, stages 2-10 ofFIGS.3B-3J, or stages 3-10 ofFIGS.4B-4J.

Process500begins in block502in which a first dielectric is applied to a substrate. This substrate may contain, for example, chip circuitry (e.g., front-end-of-the-line devices), inter-layer contacts (e.g., middle-of-the-line contacts), or inter-chip connections (e.g., back-end-of-the-line dielectic and wiring, connection to a land-grid array). Of note, in embodiments in which a deep-via structure is being provided for a through-silicon via, this step may be replaced with applying a silicon layer to the substrate.

Process500continues in block504in which a second dielectric is applied to the structure. In some embodiments, this second dielectric could be formed upon the first dielectric, forming a bi-layer dielectric. This may resemble the stage illustrated inFIG.3C. In some embodiments, this second dielectric could be applied through conformal deposition as a spacer element in a preliminary via. In these embodiments, block504may follow a masking and preliminary directional etching process to form this preliminary via, and may resemble the stage illustrated inFIG.4E.

Process500also includes forming a via mask in block506. In some embodiments, this via mask could be applied on top of a bi-layer dielectric formed in block504, in which case block506would follow block504and may resemble the stage illustrated inFIG.3D. In some embodiments, this via mask could be applied on top of the first dielectric that was applied in block502, in which case block506may be performed prior to block504. This may resemble the stage illustrated inFIG.4C.

Process500continues in block508in which a via trench is formed through a directional etching process (e.g., nisotropic etching). In some embodiments, block508may form a complete via through a bi-layer dielectric. This may resemble the stage illustrated inFIG.3E. In some embodiments, block508may be a second stage of etching and may complete a via from a previously formed preliminary via. This may resemble the stage illustrated inFIG.4F.

Process500continues in block510in which the via trench is broadened into the first dielectric. This may be performed through an isotropic etching process that introduces an etchant to which the first dielectric is sensitive but the second dielectric is not sensitive. This may result in a first section of the via trench (i.e., the section that is surrounded by the first dielectric) that is wider than a second section of the via trench (i.e., the section that is surrounded by the second dielectric). This may resemble the stages illustrated inFIGS.3G and4G.

Process500continues in block512in which the via trench is filled with a conductive material using a conformal deposition process. Due to the broadening of the first via section in block510, this may result in a stress-relief void within the conductive material within the first via section. In some embodiments, this stress-relief void may also partially extend into the second via section.