Memory management storage to a host device

Systems and methods of memory management storage to a host device are disclosed. A method is performed in a data storage device with a non-volatile memory and a controller operative to manage the non-volatile memory and to generate management data for managing the non-volatile memory. The method includes performing, at a given time, originating at the controller data management transfer to a host device or originating at the controller data management retrieval from the host device.

FIELD OF THE DISCLOSURE

The present disclosure generally relates to storing and retrieving memory management data of a non-volatile memory device.

BACKGROUND

Managed flash storage devices, such as embedded or removable cards, often include flash memories and a controller. The controller may include a microprocessor that executes flash management software. The flash management software may maintain a database of several tables, such as a logical to physical address translation table.

Such tables may be kept in a volatile memory of the storage device. Although larger management tables may enable increased performance, the management tables may be limited in size by the volatile memory of the controller. For example, a capacity of a random access memory (RAM) embedded in the controller may be limited by manufacturing costs. In addition, volatile memory does not retain information upon power down. As a result, after power down, the tables may be rebuilt using a process that takes time and resources when the storage device is powered up.

SUMMARY

A data storage device is disclosed that includes a controller and a non-volatile memory. The data storage device stores data, such as for a user, an operating system (OS) of a host device, or applications. Memory management data, such as management tables, may be stored or generated on the fly by the controller for management of the non-volatile memory. For example, the data storage device may be a flash memory card with a controller that generates management data to manage a flash memory array.

The data storage device may initiate a data transfer operation to store or retrieve management data to/from the host device memory in order to virtually increase the controller's internal storage space and enhance the device's performance. The data storage device may also use the host memory for storage so that the data can be retrieved after power up where data stored in the internal controller RAM is lost. Using the host memory as storage for management data that is retrieved after power up may enhance the power-up start up time for the device.

DETAILED DESCRIPTION

A storage device is disclosed that is capable of using a memory of a host device to virtually extend an internal controller RAM. The storage device is capable of writing data into a host RAM. The storage device is also capable of reading this data later in time from the host RAM. The data read/written to the host memory is used during controller operation, virtually increasing the controller RAM capacity. The writing and reading to host RAM may be initiated by the storage device sending dedicated commands that instruct the host to store and retrieve data. The writing and reading to host RAM may be performed at the device driver level transparently to the host operating system or applications.

The storage device may maintain a policy of backing up data residing in its internal RAM to the host. The host may turn off power of the storage device to save energy. In most scenarios where the storage device power is turned on and off, the host maintains power for the host RAM because the host RAM is used for code execution. After turning on the power of the storage device, the storage device rebuilds its tables by using the information stored in host RAM much faster then it would take rebuilding the tables without using the stored information.

Read and write latencies of a NAND flash may be on the order of tens of microseconds, and although read and write latencies of the host RAM may be on the order of tens of nanoseconds, a speed of data transfer from the host RAM may be limited by the time it takes to transfer the data to the controller. Improvements in high-speed interface technologies enable increasingly faster data transfer and bandwidth, and in some cases storage of the tables to the host RAM and retrieval from the host RAM may be performed faster than if the tables were stored and retrieved from the NAND flash within the storage device.

In addition, NAND flash may have a limited endurance arising from accumulated wear effects that may result from write and erase operations to the NAND flash. In some implementations, management data transferred to the host RAM may also be stored to the non-volatile memory so that the management data is recoverable in case the host RAM powers down. In other implementations, however, the tables may be stored to the host RAM without also being stored to the NAND flash. As a result, the NAND flash will have a reduced number of write and erase cycles as compared to implementations where the tables are stored to the NAND flash. Because the size of the management data may be small compared to the overall size of the NAND flash, the resulting improvement to the flash endurance, while beneficial, may be relatively small.

According to a particular embodiment, reading data from and writing data to the host RAM may implement a technique called bus mastering or “first-party direct memory access” (FPDMA). “First-party DMA” is different from “third-party DMA” where a system DMA controller (the third party) is actually doing a data transfer (the first two parties are, for example, the host processor and a peripheral). In contrast, “first-party DMA” refers to a system where the peripheral actually takes control of the system bus to perform the transfer by initiating the transactions. FPDMA is implemented by hardware, making it fast and efficient.

The host processor may be coupled to a mass storage device via a mass storage (MS) interface. Examples of mass storage interfaces are secure digital (SD) interfaces, such as SD3.0, ultra high speed (UHS) interfaces, such as UHS-II, multimedia card (MMC) interfaces, serial advanced technology attachment (SATA) interfaces and others. Use of high speed interfaces (e.g. UHS-II) may enable management data transfer rates between the host and the controller that approach or exceed read/write speeds to the NAND flash.

The host processor may include (but is not limited to) a central processing unit (CPU), a host memory controller, a mass storage controller, and a DMA controller, all coupled via a system bus (or equivalent). A host DMA controller may be used for moving data between the MS interface and the host memory, freeing the CPU to perform other tasks.

The storage device may include a controller and NAND flash memories. The controller can include a processor that runs flash management firmware, a RAM, and optionally a DMA controller. The DMA controller may capable of moving data between the internal RAM of the controller and the host interface. The DMA controller may also be capable of moving data between the flash memory and the controller RAM or the host interface.

Referring toFIG. 1, a representative system includes a storage device110coupled to a host device120via a device interface132, such as a mass storage interface (MS I/F). The host device120includes a host processor108that is coupled to a host memory130, such as a DRAM, via a host memory interface134. The host memory130may be within the host device120and is coupled to the host processor108via the host memory interface134to transmit data to and to receive data from the host processor108.

The storage device110includes a controller114and a non-volatile memory112, such as a NAND flash array. The controller114is coupled to the non-volatile memory112via a non-volatile memory interface116, such as a flash interface. The storage device110may be a removable flash storage device, such as a universal serial bus (USB) flash drive (UFD) or a memory card, such as a Secure Digital SD® card, a microSD® card, a miniSD™ card (trademarks of SD-3C LLC, Wilmington, Del.), a MultiMediaCard™ (MMC™) card (trademark of JEDEC Solid State Technology Association, Arlington, Va.), or a CompactFlash® (CF) card (trademark of SanDisk Corporation, Milpitas, Calif.). Alternatively, the storage device110may be embedded memory in the host device120, such as eMMC® (trademark of JEDEC Solid State Technology Association, Arlington, Va.) and eSD, as illustrative examples.

The controller114includes a system bus141, a volatile memory144(e.g. RAM), and a central processing unit (CPU)146. The controller114includes logic142, such as the illustrated host interface. The host interface optionally includes a direct memory access (DMA) controller (not shown) that may be configured to perform first-party DMA (FPDMA) operations. The CPU146is coupled to the logic142and to the volatile memory144via the system bus141.

The host processor108includes a host memory controller124and a host processing unit122(e.g. a CPU). The host processing unit122is coupled to the host memory130via the host memory controller124to enable the host processing unit122to access the host memory130via the system bus121, the host memory controller124, and the host memory interface134.

The host processor108may optionally include a host direct memory access (DMA) controller126, which is coupled to the system bus121. The host processor108further includes a device interface controller128, such as a mass storage controller, coupled to the system bus121. The device interface controller128is coupled to the storage device110via the device interface132.

The controller114is configured to manage the non-volatile memory112and to generate management data150for managing the non-volatile memory112, such as flash management data, that is accessible at the controller memory144during management of the non-volatile memory112. For example, the management data150may include a logical address to physical address mapping table that is generated and updated by the controller114to manage the non-volatile memory112. When the data storage device110is operatively coupled to the host device120, the controller114may be operative to determine a need to transfer the management data150generated by the controller114or a need to retrieve the management data150from the host device120. Based on the determined need, the controller114may be operative to initiate transfer of the management data150from the data storage device110to the host device120or to initiate retrieval from the host device120of the management data150.

For example, the controller114may be configured to originate a data management transfer to transfer the management data150to the host device120on determining the need to use a host device memory (e.g. the host memory130) as a virtual extension of the volatile memory144. To illustrate, the management data150for the non-volatile memory112may be transferred from the controller memory144to the host device120in response to the management data150requiring more memory space than is available at the controller memory144. The management data150may alternatively, or in addition, be transferred to the host device120in response to the controller114detecting an event while the controller114is operatively coupled to the host device120. Thus, the management data150may be transferred by the storage device110to the host device120and stored within the host memory130.

The data management transfer to the host device120is originated at the controller114to store the management data150at the host memory130. The host device120does not request the management data150and may be unable to use the management data150. For example, the controller114may be configured to encrypt the management data150and to transfer the encrypted management data to the host device120without providing a key to the host device120for decrypting the encrypted management data. Instead, the key that enables decryption of the encrypted management data may be stored at the data storage device110and used by the controller114to recover the management data150after the encrypted management data has been retrieved from the host device120. The storage device110initiates transfer of the management data150without receiving a request for the management data from the host device120.

In addition to using the host memory130as a virtual extension of the volatile memory144, the controller114may be configured to originate a data management transfer to transfer the management data150to the host device120on determining the need to use a host device memory (e.g. the host memory130) to hold the management data150when the data storage device110is to be powered down. For example, the controller114may initiate transfer of the management data150to the host device120in response to detecting an event that may include receiving an indication that the storage device110is to be powered down.

Alternatively, the management data150may be retrieved from the host device120by the controller114. In this case, a data retrieval operation may be initiated by the storage device110in response to the controller114determining a need to retrieve the management data150from the host device120. The controller114may be configured to originate data management retrieval from the host device120on determining the need to access the management data150when the data storage device110receives power (after transferring the management data150to the host device120and being powered down). To illustrate, the controller114may initiate retrieval of the management data150in response to detecting an event that includes the data storage device110receiving power after the data storage device110has transferred the management data150to the host device120and entered a power-down state.

The storage device110may initiate an instruction for the host device120to transfer the management data150to the host memory130or may initiate an instruction for the host device120to send the management data150back from the host device120to the data storage device110, as described inFIG. 2. The host processor108may facilitate the data transfer or retrieval via signaling on the system bus121. In an optional implementation where the host device120includes the host DMA controller126, the processing unit122may respond to the instruction by instructing the host DMA controller126to facilitate the data transfer or retrieval. In an implementation where the logic142includes a DMA controller, the DMA controller may be configured to enable the controller114to selectively initiate the data transfer or the data retrieval. For example, the DMA controller may be configured to instruct the host DMA controller126to transfer the management data150from the controller memory144to the host memory130or to retrieve the management data150from the host memory130to the controller114.

In an implementation where the data storage device110is a removable memory card, the memory card may be selectively inserted into a socket of the host device120to be removably connected to the host device120. When the data storage device110is embedded memory in the host device120, the data storage device110may be permanently affixed within or connected to the host device120. For example, the host device120may comprise a personal computer, a portable computer, or a mobile communication device (e.g. cellular phone, smart phone) that incorporates an embedded memory that includes the data storage device110.

By initiating transfers of the management data150to the host memory130and retrievals of the management data150from the host memory130, the storage device110makes use of available resources in a way that may benefit both the storage device110and the overall system. The storage device110is able to have a small form factor (e.g. a microSD form factor). Maintaining the management data150, such as flash management tables, on host RAM may boost performance.

Referring toFIG. 2, a particular embodiment that illustrates further details of operation of a system including the host device120and the storage device110is illustrated. The management data150may be transferred and retrieved between the storage device110and the host device120via a data transfer and retrieval path252. For example, during a transfer of the management data150from the controller memory144to the host memory130, the illustrated data transfer path252includes the controller system bus141, the logic142, the device interface132, the device interface controller128, the host system bus121, the host memory controller124, and the host memory interface134. During a retrieval of the management data150from the host memory130to the controller memory144, the data retrieval path252may include the host memory interface134, the host memory controller124, the host system bus121, the device interface controller128, the device interface132, the logic142, and the controller system bus141.

In the illustrated embodiment where the logic142includes the DMA controller, the management data150may be sent or received by the DMA hardware configured by the controller114. For example, the controller114may initiate an instruction260and in some instances may provide one or more transfer or retrieval parameters262, while in other instances the controller114may send the instruction260without providing any transfer or retrieval parameters.

Data management transfer originated at the controller114may include sending to the host device120a transfer instruction, and data management retrieval originated at the controller114may include sending to the host device120a retrieval instruction. The transfer instruction may include one or more transfer parameters. For example, the transfer parameters may include one or more of: a start address; a data transfer size; a maximal controller buffer size; a DMA transfer priority; a unique identifier (ID); a time stamp; and a signature. Although in some instances the transfer instruction may include one or more transfer parameters, in other instances the transfer instruction may include none.

The retrieval instruction may include one or more retrieval parameters, such as one or more of: a start address; a data retrieval size; a maximal controller buffer size; a DMA priority; a unique ID; a time stamp; and a signature. The start address may be a relative address and the maximal controller buffer size may be included so that the host sends one buffer size at a time and does not exceed the designated maximal controller buffer size. The DMA transfer priority may indicate whether to queue the command after a previous command or to execute before one or more other commands. Although in some instances the retrieval instruction may include one or more retrieval parameters, in other instances the retrieval instruction may include none.

In implementations where the parameters262are sent to the host device120, the instruction260and the parameters262may be communicated from the controller114to the host device120separately or as a single instruction260that includes the parameters262. For example, the logic142may determine a data length of the management data150resident in the controller memory144and provide such information to the host device120via the parameters262.

To illustrate, the controller114may negotiate with the host device120about the size of storage space the controller114may get. Different hosts may be capable of providing different RAM sizes for the use of the storage device110. The controller114may send data to the host storage specific location relative to the storage space starting address. For example, if the host device120reserves on the host memory130an area starting at address 123000, this address may be translated to 0 from the point of view of the controller114.

The controller114may implement a paging mechanism that implements virtual memory. For example, the controller114may implement a paging mechanism that is similar to a virtual memory mechanism implemented by an operating system where some RAM areas are stored on a hard disk and where a request to access a RAM area that is stored on the hard disk causes the operating system to fetch the appropriate page from the hard disk. As applied to the system ofFIG. 2, the controller114may implement a paging mechanism where some memory areas are stored to the host memory130. In response to a request to access one of these memory areas (e.g. from flash management firmware executed by the CPU146), the controller114initiates a data transfer from the host memory130.

In an embodiment where the host device120does not include the host DMA controller126, the host processing unit122may facilitate the data transfer between the storage device interface and the host memory130by reading the data from the interface and writing it back to the memory130(or vice versa). In another embodiment where the host device120includes the host DMA controller126, the host processing unit122receives the instruction260and the parameters262and may facilitate the data transfer or retrieval itself or may instruct the host DMA controller126to facilitate the data transfer or retrieval. In each of these embodiments, the specific mechanism by which data is transferred or retrieved within the host device120may be transparent to the data storage device110. In either case, the data storage device110initiates the data transfer or retrieval operation by sending the instruction260to the host device120and receives or sends the requested management data150via the device interface132. The transfer of the management data150from the controller114to the host device120may be initiated based on determining a need to transfer the management data150to use a host device memory as a virtual extension of the volatile memory144when a size of the management data150exceeds an available capacity of the volatile memory144. Alternatively, the transfer of the management data150may be initiated based on determining a need to transfer the management data150in response to one or more other events. For example, transfer of the management data150may be initiated at the data storage device110in response to receipt of an indication that the data storage device110is to be powered down. To illustrate, the host device120may send a command or a signal to the data storage device110indicating that the host device120is going to power down the data storage device110and there are no data transfer operations expected before the power down. In the event that the data storage device110is to be powered down, in order to save the management data150prior to the powered down condition, the logic142may initiate the data transfer operation so that the management data150is stored at the host memory130prior to the storage device110signaling to the host device120that the storage device110is ready to be powered down.

Thus, operation of the data storage device110may include the controller114performing, at a given time, originating at the controller114data management transfer to the host device120or originating at the controller114data management retrieval from the host device120. The data management transfer to the host device120may be originated by determining a need to transfer the management data150generated by the controller, and, based on the determined need, initiating transfer of the management data150from the data storage device110to the host device120. As one example, the controller114may originate the data management transfer to the host device120on determining the need to use a host device memory as a virtual extension of the volatile memory144. As another example, the controller may originate the data management transfer to the host device120on determining the need to use a host device memory to hold the management data150when the data storage device110is to be powered down.

The transfer of the management data150from the data storage device110to the host device120may be initiated by sending a transfer instruction to the host device120. In some instances, the transfer instruction may include one or more transfer parameters (e.g. the instruction260and the parameters262). The transfer instruction may instruct the host device120to facilitate transferring the management data150and the transfer parameters (if provided) may indicate the management data150to be transferred.

In an example implementation where the data storage device110has initiated the data transfer operation by sending the instruction260to the host device120, the host DMA controller126may facilitate the data transfer operation by generating signals including one or more requests for read access to the management data150and one or more requests for write access to a destination of the management data150. The management data150may be transferred from the data storage device110to the host device120by indicating to the host device120that the controller114requests an action of the host device120(e.g. by raising a flag in a status register) In response to the request from the storage device110, the storage device110may receive a query from the host device120and in reply the storage device110may request the host device120to store a specified amount of the management data150to the host memory130at a specified relative address. The host device120may then receive the data from the storage device's interface and store the data to the appropriate location in the host memory130.

The data management retrieval from the host device120may be originated by the controller114by determining a need to retrieve the management data150from the host device120. Based on the determined need, the controller114may initiate retrieval from the host device120of the management data150, and the management data150may be received from the host device120. The controller114may originate the data management retrieval from the host device120on determining the need to access the management data150when the data storage device110receives power. The data management retrieval may be initiated by sending a retrieval instruction to the host device120. The retrieval instruction may include one or more retrieval parameters (e.g. the instruction260and the parameters262). The retrieval instruction may instruct the host device120to perform a data retrieval of the management data150from the host memory130, and the retrieval parameters (if provided) may indicate the management data150to be sent back to the data storage device110.

Referring toFIG. 3, further details of the flash management data150stored within the volatile memory144(e.g. RAM) of the controller114within the storage device110is illustrated. As illustrated, the management data150may include flash management data including one or more logical to physical mapping tables372, one or more other management tables376, other mapping data374, other flash management data, or any combination thereof. The controller114is configured to manage the non-volatile memory112using the management data150. For example, the controller114can update the logical to physical mapping tables372as part of a wear-leveling operation of the non-volatile memory112. Thus, the storage device110illustrated inFIG. 3maintains the management data150within the controller memory144(e.g. a volatile memory) for use by the controller114to manage and control operation of the non-volatile memory112.

In the illustrated embodiment ofFIG. 3, the controller114includes a host interface controller342to enable the controller114to communicate data to a host device. For example, the host interface controller342may control retrieval of the management data150from the controller memory144, such that the retrieved flash management data150may be communicated from the storage device110to a host device.

Although the management data150is depicted inFIG. 3as being contained within the controller memory144, all or part of the management data150may have a size that exceeds an available capacity of the controller memory144. For example, the controller114may generate flash management data that is too large to be maintained at the controller memory144(e.g., a non-used capacity of the controller memory144may be smaller than a data size of the management data150). The controller114may initiate a data transfer operation to transfer all or part of the flash management data to the host device120. The controller114may therefore use the host memory130as a virtual extension of the controller's RAM.

Referring toFIG. 4, a particular illustrative embodiment of a method of transferring management data is shown and generally designated400. As previously described, in some embodiments a flash management data transfer operation is initiated by instructing the host to send or receive the management data, and the specific transfer mechanism used within the host (e.g. CPU or DMA) is transparent to the storage device. The method400illustrates an alternative embodiment where the data transfer is facilitated by the host DMA.

A controller at a data storage device determines a start address and size of content to be backed up, at402. The method further includes the controller configuring a first-party direct memory access to perform a storage to host memory (e.g. DRAM) operation, at404. For example, the controller may be the controller114and the first-party direct memory access may be configured by a DMA controller included in the logic142shown inFIGS. 1-2. The first-party DMA notifies a host having a DMA controller of the data transfer operation and provides data parameters, at406. For example, the logic142may include the DMA controller that sends the instruction260including or otherwise identifying the parameters262.

The first-party DMA reads data from the controller RAM and sends the read data through a mass storage interface to the host processor, at408. For example, the logic142may include a DMA controller that reads the management data150from the controller memory144and sends the management data150to the host device120. The host DMA controller facilitates transfer of the data from the mass storage controller to the host memory controller and performs a write operation to the host memory, at410. For example, the host DMA controller126may facilitate transfer of the management data150from the device interface132to the host memory controller124and performs a write operation using the host memory controller124to write the management data150to the host memory130. The data transfer operation may therefore transfer the management data from the data storage device to a host memory, such as for virtual extension of the controller memory or maintaining the management data during a power-down event.

Referring toFIG. 5, an example of a method of transferring flash management data from a host memory to a data storage device is depicted and generally designated500. As previously described, in some embodiments a flash management data transfer operation is initiated by instructing the host to send or receive the management data, and the specific transfer mechanism used within the host (e.g. CPU or DMA) is transparent to the storage device. The method500illustrates an alternative embodiment where the data transfer is facilitated by the host DMA.

The method500includes a storage controller configuring a first-party direct memory access controller to perform a host memory (e.g. DRAM) to storage operation, at502. For example, the controller114of the data storage device110may instruct the logic142to initiate a data transfer operation to transfer the flash management data150to the controller114. The first-party DMA notifies the host and provides data parameters, at504. For example, the logic142may include a DMA controller that sends an instruction, such as the instruction260, and the parameters262to the host device120. The host DMA controller may be configured to issue a read command to the host memory through the host memory controller and to transfer the data to a mass storage interface, at506. For example, the host DMA controller126may issue the read command to the host memory130through the host memory controller124and transfer the management data150to the device interface132.

The first-party DMA transfers the data from the mass storage controller to the mass storage interface and writes the data into the internal RAM, at508. For example, the logic142may include a DMA controller that transfers the management data150from the device interface132and writes the management data150into the controller memory144. The data transfer operation may therefore transfer the management data from a host memory to a data storage device, such as to retrieve the management data after a power-up event.

The controller114may be configured to keep information that will enable the data storage device110to recover from power down without getting information from the host device120(e.g. the host device120may be powered down and lose the data stored in the host memory130). The controller114may keep a signature of every block of data the controller114sends to be stored at the host memory130and may be configured to verify the integrity of that data upon receiving the data from the host device120to verify that the data has not be destroyed or manipulated

The controller114may keep track of its state and mange a state counter in its non-volatile memory112. The state counter can be attached to any data sent to the host device120and may be used for power recovery. At power up, the controller114may compare the stored state to the state number of the data received from the host device120and to verify that both states match prior to using this data. By comparing the state counter values, the controller114may verify that the data stored in the host memory130represents the latest device state before power down.

Although various components depicted herein are illustrated as block components and described in general terms, such components may include one or more microprocessors, state machines, or other circuits configured to enable the data storage device110ofFIGS. 1-3to perform the particular functions attributed to such components, or any combination thereof. For example, the controller114ofFIGS. 1-3may represent physical components, such as hardware controllers, state machines, logic circuits, or other structures to enable the data storage device110ofFIGS. 1-3to transfer management data to the host device120and retrieve the management data from the host device120.

For example, the logic142(e.g. configured to instruct the host to send or receive flash management data) may be implemented using a microprocessor or microcontroller programmed to determine a starting address and/or a data transfer size of the management data, and to initiate a data transfer operation with the host device120. Although the logic142can include a hardware-implemented DMA controller (i.e. dedicated circuitry), the logic142may also or alternatively include executable instructions that are executed by a processor and the instructions are stored at the memory112. Alternatively, or in addition, executable instructions that are executed by a processor (such as the CPU146or a processor that may be included in the logic142) may be stored at a separate memory location that is not part of the memory112, such as at the RAM144or at a read-only memory (ROM) (not shown).

In a particular embodiment, the data storage device110may be a portable device configured to be selectively coupled to one or more external devices. However, in other embodiments, the data storage device110may be attached or embedded within one or more host devices, such as within a housing of a portable communication device. For example, the data storage device110may be within a packaged apparatus such as a wireless telephone, personal digital assistant (PDA), gaming device or console, portable navigation device, or other device that uses internal non-volatile memory. In a particular embodiment, the data storage device includes a non-volatile memory, such as a flash memory (e.g., NAND, NOR, Multi-Level Cell (MLC), Divided bit-line NOR (DINOR), AND, high capacitive coupling ratio (HiCR), asymmetrical contactless transistor (ACT), or other flash managed devices).

The illustrations of the embodiments described herein are intended to provide a general understanding of the various embodiments. Other embodiments may be utilized and derived from the disclosure, such that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments. Accordingly, the disclosure and the figures are to be regarded as illustrative rather than restrictive.