Capacitor and method for fabricating the same

A capacitor is disclosed, including: a semiconductor substrate including opposite upper and lower surfaces; one first trench disposed in the semiconductor substrate and formed downward from the upper surface; one second trench disposed in the substrate and corresponding to the first trench, and formed upward from the lower surface; a first conductive layer disposed above the substrate and in the first trench; a first insulating layer disposed between the substrate and the first conductive layer; a second conductive layer disposed on the substrate and in the first trench, the second conductive layer being electrically connected to the substrate; a second insulating layer disposed between the second conductive layer and the first conductive layer; a third conductive layer disposed below the substrate and in the second trench; and a third insulating layer disposed between the third conductive layer and the substrate, which is electrically connected to the first conductive layer.

TECHNICAL FIELD

The present application relates to the field of capacitors, and more particularly, to a capacitor and a method for fabricating the same.

BACKGROUND

A capacitor can play a role of bypassing, filtering, decoupling, or the like in a circuit, which is an indispensable part of ensuring a normal operation of the circuit. A silicon capacitor is a capacitor manufactured on a silicon wafer using semiconductor processing techniques. Compared with a traditional planar silicon capacitor, a 3 Dimensions (3D) silicon capacitor increases a surface area by processing a 3D structure such as a deep hole and a trench on a substrate, and a capacitance density thereof can reach more than 20 times that of a plate silicon capacitor. At present stage, based on a concept of multi-layer nesting in the manufacture of a dynamic random access memory (DRAM), a 3D silicon capacitor is fabricated by alternately depositing a conductor and an insulator material on a surface of a 3D structure to form a plurality of vertically stacked capacitor structures, then connecting all the capacitors in parallel by different connection manners on the front side of a silicon substrate to finally form a capacitor with a large capacitance value. However, the 3D silicon capacitor fabricated by the above method needs to undergo multiple photolithography steps (including exposure, development, and etching) on the front side of a wafer, which requires not only higher pattern alignment precision, but also results in problems such as low reliability and short circuit of a capacitor since a material film to be fabricated first is easily destroyed due to exposure to a corrosive gas and solution in a subsequent photolithography process.

SUMMARY

The present application provides a capacitor and a method for fabricating the same. A photolithography step is performed separately on both sides of a semiconductor substrate (silicon wafer) by processing both front and back sides, thereby reducing alignment difficulty of multiple photolithography, and meanwhile, a capacitance density could be further increased by fabricating a capacitor structure on the back side of the semiconductor substrate.

In a first aspect, provided is a capacitor, the capacitor including:

a semiconductor substrate (101) including an upper surface and a lower surface opposite to the upper surface;

at least one first trench (108) disposed in the semiconductor substrate (101) and formed downward from the upper surface;

at least one second trench (109) disposed in the semiconductor substrate (101) and corresponding to the first trench (108), and formed upward from the lower surface;

a first conductive layer (103) disposed above the semiconductor substrate (101) and in the first trench (108);

a first insulating layer (102) disposed between the semiconductor substrate (101) and the first conductive layer (103) to isolate the first conductive layer (103) from the semiconductor substrate (101);

a second conductive layer (105) disposed on the semiconductor substrate (101) and in the first trench (108), the second conductive layer (105) being electrically connected to the semiconductor substrate (101);

a second insulating layer (104) disposed between the second conductive layer (105) and the first conductive layer (103) to isolate the second conductive layer (105) from the first conductive layer (103);

a third conductive layer (107) disposed below the semiconductor substrate (101) and in the second trench (109); and

a third insulating layer (106) disposed between the third conductive layer (107) and the semiconductor substrate (101) to isolate the third conductive layer (109) from the semiconductor substrate (101), the third conductive layer (107) being electrically connected to the first conductive layer (103).

Therefore, a capacitor provided by an embodiment of the present application is a wafer-level 3D silicon capacitor with characteristics of less size and high capacity. A photolithography step is performed separately on both sides of a semiconductor substrate (silicon wafer) by processing both front and back sides, thereby reducing alignment difficulty of multiple photolithography, and meanwhile, a capacitance density could be further increased by fabricating a capacitor structure on the back side of the semiconductor substrate.

The capacitor described in the embodiment of the present application possesses excellent performance and stability, and has a high capacitance density. At the same time, the capacitor described in the embodiment of the present application can play a role of bypassing, filtering, decoupling, or the like in a circuit.

Optionally, the semiconductor substrate is preferably an n-type or p-type heavily doped low-resistivity silicon wafer. A high-resistivity wafer may also be adopted, but after the first trench is fabricated, the upper surface (front side) of the semiconductor substrate and a surface of the first trench are required to be doped to form a heavily doped low-resistivity conductive layer.

In some possible implementation manners, at least one third trench (110) is disposed in the semiconductor substrate (101), the third trench (110) is formed upward from the lower surface of the semiconductor substrate (101), a depth of the third trench (110) is less than a thickness of the semiconductor substrate (101), and the third insulating layer (106) and the third conductive layer (107) are sequentially disposed in the at least one third trench (110).

In some possible implementation manners, any cross section of the third trench (110) parallel to the surfaces of the semiconductor substrate (101) in the semiconductor substrate (101) is the same as that of the second trench (109).

In some possible implementation manners, the second conductive layer (105) forms a downward recess between two adjacent first trenches (108) to block the second insulating layer (104) and be electrically connected to the semiconductor substrate (101); or the second conductive layer (105) is evenly disposed between two adjacent first trenches (108), and is isolated from the semiconductor substrate (101) by the second insulating layer (104).

In some possible implementation manners, a width of any cross section of the first trench (108) parallel to the surfaces of the semiconductor substrate (101) in the semiconductor substrate (101) is greater than that of the second trench (109).

In some possible implementation manners, the first trench (108) is aligned with the second trench (109).

In some possible implementation manners, a depth of the first trench (108) is greater than that of the second trench (109).

In some possible implementation manners, a depth of the first trench (108) is equal to a thickness of the semiconductor substrate (101), and a depth of the second trench (109) is equal to zero.

In some possible implementation manners, a projected area of the first insulating layer (102) on the semiconductor substrate (101) is the same as that of the first conductive layer (103), the projected area of the first insulating layer (102) on the semiconductor substrate (101) is less than that of the second insulating layer (104), and the projected area of the second insulating layer (104) on the semiconductor substrate (101) is less than that of the second conductive layer (105).

In some possible implementation manners, a projected area of the third insulating layer (106) on the semiconductor substrate (101) is greater than that of the third conductive layer (107).

In some possible implementation manners, at least one of the first insulating layer (102), the second insulating layer (104) and the third insulating layer (106) includes at least one of:

a silicon oxide layer, a silicon nitride layer, a metal oxide layer, and a metal nitride layer.

Optionally, at least one of the first insulating layer (102), the second insulating layer (104), and the third insulating layer (106) includes at least one of: a silicon dioxide layer, an aluminum oxide layer, a zirconium oxide layer, a hafnium oxide layer, a lead zirconate titanate (PbZrxTi1-xO3, PZT) layer, and a calcium copper titanate (CaCu3Ti4O12, CCTO) layer.

For example, at least one of the first insulating layer (102), the second insulating layer (104), and the third insulating layer (106) may be a stack of a material having a high dielectric constant, such as silicon dioxide/aluminum oxide/silicon dioxide (SiO2/Al2O3/SiO2).

It should be understood that at least one of the first insulating layer (102), the second insulating layer (104), and the third insulating layer (106) may be formed by bonding of a material having a high dielectric constant (relative permittivity or dielectric constant).

Therefore, the first insulating layer, the second insulating layer, and the third insulating layer described in the embodiment of the present application may be formed by bonding a material having a high dielectric constant, thereby making the capacitor described in the embodiment of the present application have a larger capacitance density.

In some possible implementation manners, at least one of the first conductive layer (103), the second conductive layer (105) and the third conductive layer (107) includes at least one of: a heavily doped polysilicon layer, a carbon-based material layer, a metal layer, and a titanium nitride layer.

In some possible implementation manners, the second conductive layer (105) is one electrode of the capacitor, and the third conductive layer (107) is the other electrode of the capacitor.

In a second aspect, provided is a method for fabricating a capacitor, including:

etching a semiconductor substrate to form at least one first trench in the semiconductor substrate, where the first trench is formed downward from an upper surface of the semiconductor substrate, and a depth of the first trench is less than a thickness of the semiconductor substrate;

depositing a first insulating layer on the upper surface of the semiconductor substrate and an inner surface of the at least one first trench;

depositing a first conductive layer on an upper surface and an inner surface of the first insulating layer;

performing photolithography processing on the first insulating layer and the first conductive layer to expose the upper surface of the semiconductor substrate;

depositing a second insulating layer on an upper surface and an inner surface of the first conductive layer, and the upper surface of the semiconductor substrate;

performing photolithography processing on the second insulating layer to expose the upper surface of the semiconductor substrate, where the second insulating layer covers the first insulating layer and the first conductive layer;

depositing a second conductive layer on an upper surface and an inner surface of the second insulating layer, and the upper surface of the semiconductor substrate;

etching the semiconductor substrate to form at least one second trench in one-to-one correspondence with the at least one first trench in the semiconductor substrate, where the second trench penetrates upward through the first insulating layer from a lower surface of the semiconductor substrate to expose the first conductive layer, or the second trench extends upward from a lower surface of the semiconductor substrate to the first insulating layer;

depositing a third insulating layer on the lower surface of the semiconductor substrate and an inner surface of the at least one second trench;

if the second trench penetrates through the first insulating layer, removing the third insulating layer deposited on the bottom of the at least one second trench to expose the first conductive layer, or

if the second trench extends to the first insulating layer, removing the third insulating layer deposited on the bottom of the at least one second trench, and removing the first insulating layer deposited on the bottom of the at least one first trench to expose the first conductive layer; and depositing a third conductive layer on a lower surface and an inner surface of the third insulating layer.

Therefore, in the embodiment of the present application, by properly designing a pattern, a first prepared material film is covered and protected in a subsequent photolithography process, thereby reducing etching difficulty and improving process reliability.

In some possible implementation manners, before etching the semiconductor substrate, the method further includes:

performing thinning processing on the lower surface of the semiconductor substrate.

In some possible implementation manners, the method further includes:

etching the semiconductor substrate to form at least one third trench in the semiconductor substrate, where the third trench is upward from the lower surface of the semiconductor substrate, and a depth of the third trench is less than the thickness of the semiconductor substrate; anddepositing the third insulating layer on an inner surface of the at least one third trench, and depositing the third conductive layer on the inner surface of the third insulating layer.

In some possible implementation manners, any cross section of the third trench parallel to the surfaces of the semiconductor substrate in the semiconductor substrate is the same as that of the second trench.

In some possible implementation manners, the method further includes:

performing photolithography processing on the third conductive layer to expose the lower surface of the semiconductor substrate.

In some possible implementation manners, on the upper surface of the semiconductor substrate, the second conductive layer between two adjacent first trenches is electrically connected to the semiconductor substrate.

In some possible implementation manners, a width of any cross section of the first trench parallel to the surfaces of the semiconductor substrate in the semiconductor substrate is greater than that of the second trench.

In some possible implementation manners, the first trench is aligned with the second trench.

In some possible implementation manners, the depth of the first trench is greater than that of the second trench.

In some possible implementation manners, the etching the semiconductor substrate includes:

etching the semiconductor substrate by deep reactive ion etching (DRIE).

In a third aspect, provided is a method for fabricating a capacitor, including:

etching a semiconductor substrate to form at least one first trench in the semiconductor substrate, where the first trench is downward from an upper surface of the semiconductor substrate, and a depth of the first trench is less than or equal to a thickness of the semiconductor substrate;

depositing a first insulating layer on the upper surface of the semiconductor substrate and an inner surface of the at least one first trench;

depositing a first conductive layer on an upper surface and an inner surface of the first insulating layer;

performing photolithography processing on the first insulating layer and the first conductive layer to expose the upper surface of the semiconductor substrate;

depositing a second insulating layer on an upper surface and an inner surface of the first conductive layer, and the upper surface of the semiconductor substrate;

performing photolithography processing on the second insulating layer to expose the upper surface of the semiconductor substrate, where the second insulating layer covers the first insulating layer and the first conductive layer;

depositing a second conductive layer on an upper surface and an inner surface of the second insulating layer, and the upper surface of the semiconductor substrate;

depositing a third insulating layer on a lower surface of the semiconductor substrate;

removing the third insulating layer under the at least one first trench to expose the first conductive layer; and

depositing a third conductive layer on a lower surface and an inner surface of the third insulating layer.

Therefore, in the embodiment of the present application, by properly designing a pattern, a first prepared material film is covered and protected in a subsequent photolithography process, thereby reducing etching difficulty and improving process reliability.

In some possible implementation manners, when the depth of the first trench is less than the thickness of the semiconductor substrate, the method further includes:

performing thinning processing on the lower surface of the semiconductor substrate before depositing the third insulating layer on the lower surface of the semiconductor substrate.

In some possible implementation manners, the method further includes:

performing photolithography processing on the third conductive layer to expose the lower surface of the semiconductor substrate.

In some possible implementation manners, on the upper surface of the semiconductor substrate, the second conductive layer between two adjacent first trenches is electrically connected to the semiconductor substrate.

In some possible implementation manners, the etching the semiconductor substrate includes:

etching the semiconductor substrate by DRIE.

Therefore, according to a capacitor and a method for fabricating the same in an embodiment of the present application, a semiconductor substrate is provided with at least one first trench and at least one second trench in one-to-one correspondence with the at least one first trench; a first conductive layer and a second conductive layer are disposed on the semiconductor substrate and in the at least one first trench; a first insulating layer is disposed between the first conductive layer and the semiconductor substrate; a second insulating layer is disposed between the first conductive layer and the second conductive layer, and the second conductive layer is electrically connected to the semiconductor substrate; a third conductive layer is disposed below the semiconductor substrate and in the at least one second trench; and a third insulating layer is disposed between the third conductive layer and the semiconductor substrate, and the third conductive layer is electrically connected to the first conductive layer. Therefore, a photolithography step is performed separately on both sides of a semiconductor substrate by processing both front and back sides, thereby reducing alignment difficulty of multiple photolithography, and further, a capacitance density could be further increased by fabricating a capacitor structure on the back side of the semiconductor substrate.

DESCRIPTION OF EMBODIMENTS

Technical solutions in embodiments of the present application will be described hereinafter with reference to accompanying drawings.

It should be understood that a capacitor of an embodiment of the present application can play a role of bypassing, filtering, decoupling, or the like in a circuit.

The capacitor described in the embodiment of the present application may be a 3D silicon capacitor which is a novel capacitor based on semiconductor wafer processing techniques. Compared with a traditional MLCC (multi-layer ceramic capacitor), the 3D silicon capacitor has advantages of small size, high precision, strong stability, and long lifetime. In a basic processing flow, a 3D structure with a high aspect ratio such as a deep hole, a trench, a pillar shape, a wall shape, or the like is required to be first processed on a wafer or substrate, and then an insulating film and a low-resistivity conductive material are deposited on a surface of the 3D structure to fabricate a lower electrode, an dielectric layer and an upper electrode of the capacitor, sequentially.

At present stage, based on a concept of multi-layer nesting in the manufacture of a DRAM, the 3D silicon capacitor is fabricated by alternately depositing a conductor and an insulator material on a surface of a 3D structure to form a plurality of vertically stacked capacitor structures, then connecting all the capacitors in parallel by different connection manners on the front side of a silicon substrate to finally form a capacitor with a large capacitance value. However, the 3D silicon capacitor fabricated by the above method needs to undergo multiple photolithography steps (including exposure, development, and etching) on the front side of a wafer, which requires not only higher pattern alignment precision, but also results in problems such as low reliability and short circuit of a capacitor since a material film to be fabricated first is easily destroyed due to exposure to a corrosive gas and solution in a subsequent photolithography process. In this context, the present application proposes a novel double-sided and multi-layer 3D capacitor structure and a method for fabricating the same in order to avoid the above disadvantages.

Specifically, a stacked capacitor structure including a conductive substrate, an insulating layer, a conductive layer, an insulating layer and a conductive layer is fabricated in a deep hole or a trench in a front side of a wafer. The intermediate conductive layer is then led out by digging the hole (or the trench) on a back side of the wafer.

Hereinafter, a capacitor according to an embodiment of the present application will be introduced in detail with reference toFIGS. 1 to 4. It should be understood that capacitors inFIGS. 1 to 4are merely examples, and the number of first trenches, second trenches, and third trenches included in the capacitors is not limited to that included in the capacitors as shown inFIGS. 1 to 4, and may be determined according to actual needs. Meanwhile, in embodiments ofFIGS. 1 to 4, description is made by an example where an extending direction of a trench is a direction perpendicular to a semiconductor substrate (wafer). In the embodiments of the present application, the extending direction of the trench may also be some other directions, for example, any direction satisfying that an angle with respect to the direction perpendicular to the semiconductor substrate (wafer) is less than a preset value.

It should be noted that in embodiments shown below, for structures shown in different embodiments, like structures are denoted by like reference numerals for ease of understanding, and detailed description of the same structures is omitted for brevity.

FIG. 1is a possible structural diagram of a capacitor100according to an embodiment of the present application. As shown inFIG. 1, the capacitor100includes a semiconductor substrate101, a first insulating layer102, a first conductive layer103, a second insulating layer104, a second conductive layer105, a third insulating layer106, and a third conductive layer107.

Specifically, the semiconductor substrate101includes an upper surface and a lower surface opposite to the upper surface.

The semiconductor substrate101is provided with at least one first trench108and at least one second trench109in one-to-one correspondence with the at least one first trench, a bottom of the first trench108is in communication with a bottom of the second trench109, the first trench108extends (is formed) downward from the upper surface of the semiconductor substrate101, and the second trench109extends (is formed) upward from the lower surface of the semiconductor substrate101.

The first conductive layer103is disposed above the semiconductor substrate101and in the first trench108; the first insulating layer102is disposed between the semiconductor substrate101and the first conductive layer103, and the first insulating layer102isolates the first conductive layer103from the semiconductor substrate101; the second conductive layer105is disposed on the semiconductor substrate101and in the first trench108, and the second conductive layer105is electrically connected to the semiconductor substrate101; the second insulating layer104is disposed between the second conductive layer105and the first conductive layer103to isolate the second conductive layer105from the first conductive layer103; the third conductive layer107is disposed below the semiconductor substrate101and in the second trench109; and the third insulating layer106is disposed between the third conductive layer107and the semiconductor substrate101to isolate the third conductive layer109from the semiconductor substrate101, and the third conductive layer107is electrically connected to the first conductive layer103.

It should be noted that, in the embodiment of the present application, sizes of cross sections of the first trench108and the second trench109are not limited. For example, the trench may be a hole with a small difference between length and width of a cross section, or a trench with a large difference between length and width. Here, the cross section may be understood as a section parallel to the surfaces of the semiconductor substrate, andFIG. 1shows a section along a longitudinal direction of the semiconductor substrate.

It should be understood that the insulating layer in the embodiment of the present application may also be referred to as a dielectric layer.

It should be noted that the second conductive layer105may serve as one electrode of the capacitor100, and the third conductive layer107may serve as the other electrode of the capacitor100.

In a specific implementation, in the capacitor100, for example, only one first trench108and one second trench109are provided, and the semiconductor substrate101, the first insulating layer102and the first conductive layer103may constitute a capacitor A (capacitance C1). The first conductive layer103, the second insulating layer104, and the second conductive layer105may constitute a capacitor B (capacitance C2). The third conductive layer107, the third insulating layer106and the semiconductor substrate101may constitute a capacitor C (capacitance C3). The capacitor A, the capacitor B and the capacitor C are connected in parallel, and therefore, capacitance C of the capacitor100may be equivalent capacitance of the capacitor A, the capacitor B, and the capacitor C in parallel, that is, C=C1+C2+C3. The second conductive layer105and the third conductive layer107serve as common electrodes of the three parallel capacitors, respectively.

In a specific implementation, extending directions of the first trench108and the second trench109may be the same or different, as long as the third conductive layer107is ensured to be electrically connected to the first conductive layer103. Similarly, extending directions of different first trenches108may be the same or different, and extending directions of different second trenches109may be the same or different.

Preferably, the first trench108is aligned with the second trench109. That is, the extending directions of the first trench108and the second trench109are the same. In other words, a central axis of the first trench108coincides with that of the second trench109(FIG. 1shows just the case of coincidence of central axes).

Optionally, the semiconductor substrate101is preferably an n-type or p-type heavily doped low-resistivity silicon wafer. A high-resistivity wafer may also be adopted, but after the first trench is fabricated, the upper surface (front side) of the semiconductor substrate101and a surface of the first trench108are required to be doped to form a heavily doped low-resistivity conductive layer.

Optionally, in the embodiment of the present application, a width of any cross section of the first trench108in the semiconductor substrate101is greater than that of the second trench109. That is, in any cross section of the semiconductor substrate101, the width of the first trench108is greater than the width of the second trench109, for example, as shown inFIG. 1, a width of a cross section A of the first trench108is greater than a width of a cross section B of the second trench109. The width here is a size of an opening of a trench, which may refer to the maximum width of the trench.

In the embodiment of the present application, shapes of cross sections of a plurality of first trenches108disposed in the semiconductor substrate101may be the same or different, and similarly, shapes of cross sections of a plurality of second trenches109disposed in the semiconductor substrate101may be the same or different.

Optionally, in the embodiment of the present application, a depth of the first trench108is greater than that of the second trench109. For example, as shown inFIG. 1, in the semiconductor substrate101, a depth H1of the first trench108is greater than a depth H2of the second trench109.

It should be noted that depth and width of the first trench108may be flexibly set according to actual needs. Similarly, a depth of the second trench109may also be flexibly set according to actual needs.

Optionally, in the embodiment of the present application, at least one of the first insulating layer102, the second insulating layer104, and the third insulating layer106includes at least one of: a silicon dioxide layer, an aluminum oxide layer, a zirconium oxide layer, a hafnium oxide layer, a lead zirconate titanate (PbZrxT1-xO3, PZT) layer, and a calcium copper titanate (CaCu3Ti4O12, CCTO) layer. A specific insulating material and a layer thickness may be adjusted according to a capacitance value, a frequency characteristic, a loss and other requirements of a capacitor. Of course, at least one of the first insulating layer102, the second insulating layer104, and the third insulating layer106may further include some other material layers having high dielectric constant characteristics, which are not limited in the embodiment of the present application.

For example, the first insulating layer102may be a stack of a material having a high dielectric constant, such as silicon dioxide/aluminum oxide/silicon dioxide (SiO2/Al2O3/SiO2).

It should be noted that the first insulating layer102, the second insulating layer104, and the third insulating layer106may be formed by bonding of one or more materials having a high dielectric constant (relative permittivity or dielectric constant).

Therefore, the first insulating layer, the second insulating layer, and the third insulating layer described in the embodiment of the present application may be formed by bonding a material of a high dielectric constant, thereby making the capacitor described in the embodiment of the present application have a larger capacitance density.

Optionally, in the embodiment of the present application, at least one of the first conductive layer103, the second conductive layer105, and the third conductive layer107includes at least one of: a heavily doped polysilicon layer, a carbon-based material layer, a metal layer and a titanium nitride layer.

It should be noted that materials of the first conductive layer103, the second conductive layer105, and the third conductive layer107may be heavily doped polysilicon, a carbon-based material, or various metals such as aluminum, tungsten and copper, and may also be a low resistivity compound such as titanium nitride or a combination of the above several conductive materials.

Optionally, in the embodiment of the present application, a projected area of the first insulating layer102on the semiconductor substrate101is the same as that of the first conductive layer103, the projected area of the first insulating layer102on the semiconductor substrate101is less than that of the second insulating layer104, and the projected area of the second insulating layer104on the semiconductor substrate101is less than that of the second conductive layer105.

In other words, the second insulating layer104covers the first insulating layer102and the first conductive layer103, thereby achieving the purpose of electrically isolating the first conductive layer103from the second conductive layer105. The second conductive layer105covers the second insulating layer104, thereby achieving electrical connection between the second conductive layer105and the semiconductor substrate101.

Optionally, in the embodiment of the present application, a projected area of the third insulating layer106on the semiconductor substrate101is greater than that of the third conductive layer107.

Optionally, as an embodiment, as shown inFIG. 2, in the capacitor100described in the embodiment of the present application, at least one third trench110is disposed in the semiconductor substrate101.

Specifically, the third trench110is upward from the lower surface of the semiconductor substrate101, a depth of the third trench110is less than a thickness of the semiconductor substrate101, and the third conductive layer107is also disposed in the at least one third trench110, that is, the third conductive layer107is deposited or implanted into the second trench109and the third trench110. The third insulating layer106is disposed between the third conductive layer107and the semiconductor substrate101, that is, the third insulating layer is also formed in the third trench110to isolate the semiconductor substrate from the three conductive layer.

Preferably, any cross section of the third trench110parallel to the surfaces of the semiconductor substrate101in the semiconductor substrate101has the same shape as a cross section of the second trench109.

Preferably, a depth of the third trench110is equal to that of the second trench109.

In other words, the third trench110and the second trench109may be substantially identical trenches formed in the semiconductor substrate, both are provided with the third insulating layer and the third conductive layer therein, and only differ in that a connection with the second conductive layer is not generated at the location of the third trench.

It should be noted thatFIG. 2is only described by an example where the third trench110has the same cross section in the semiconductor substrate101as the second trench109, and the third trench110has a depth equal to the second trench, but does not limit the specific implementation of the third trench110in this embodiment.

It should be noted that a size of the cross section of the third trench110is not limited in the embodiment. For example, the third trench110may be a hole with a small difference between length and width of the cross section (which may be referred to as a deep hole), or a trench with a large difference between length and width.

A pattern of the cross section of the third trench110in the semiconductor substrate101may refer to related description of the first trench108and the second trench109, and details are not described herein again.

In a specific implementation, an extending direction of the third trench110may be the same with or different from the extending directions of the first trench108and the second trench109, as long as the third trench110is ensured not to be in communication with the first trench108and the second trench109. For example, one of the trenches may be perpendicular to the surfaces of the semiconductor substrate and other trenches may have an oblique angle with respect to the trench. Similarly, extending directions of different third trenches110may be the same or different.

It should be noted that, in a specific implementation, as shown inFIG. 2, in the capacitor100, two first trenches108, two second trenches109, and three third trenches110are disposed. The semiconductor substrate101, the first insulating layer102and the first conductive layer103may constitute a capacitor D (capacitance C4), the first conductive layer103, the second insulating layer104and the second conductive layer105may constitute a capacitor E (capacitance C5), and the third conductive layer107, the third insulating layer106and the semiconductor substrate101may constitute a capacitor F (capacitance C6). The capacitor D, the capacitor E and the capacitor F are connected in parallel, and capacitance C of the capacitor100may be equivalent capacitance of the capacitor D, the capacitor E and the capacitor F in parallel, that is, C=C4+C5+C6. Compared to the capacitor shown inFIG. 1, the number of capacitors included in the capacitor100remains unchanged, but due to an increased opposing area of two electrode plates of each of the capacitors (capacitor D, capacitor E and capacitor F), C4, C5 and C6 are all increased, and at this time, the equivalent capacitance C is increased as well. In other words, the total capacitance value of the capacitor100is increased.

Therefore, in the embodiment, the total capacitance value could be further increased by providing a third trench in a semiconductor substrate to increase the opposing area between the semiconductor substrate101and the third conductive layer107.

Optionally, as an embodiment, as shown inFIG. 3, in the capacitor100of the embodiment of the present application, on the upper surface of the semiconductor substrate101, the second conductive layer105forms a downward recess between two adjacent first trenches108to block the second insulating layer104and be electrically connected to the semiconductor substrate101.

In a specific implementation, as shown inFIG. 3, in the capacitor100, two first trenches108and two second trenches109are disposed. For example, the two first trenches108may be a first trench M and a first trench N (corresponding to a first trench108on the left side and a first trench108on the right side inFIG. 3, respectively), and the two second trenches109may be a second trench X and a second trench Y (corresponding to a second trench109on the left side and a second trench109on the right side inFIG. 3, respectively). For the first trench M and the second trench X corresponding thereto, the semiconductor substrate101, the first insulating layer102and the first conductive layer103may constitute a capacitor O (capacitance C7), the first conductive layer103, the second insulating layer104and the second conductive layer105may constitute a capacitor P (capacitance C8), and the third conductive layer107, the third insulating layer106, and the semiconductor substrate101may constitute a capacitor Q (capacitance C9). For the first trench N and the second trench Y corresponding thereto, the semiconductor substrate101, the first insulating layer102and the first conductive layer103may constitute a capacitor R (capacitance C10), the first conductive layer103, the second insulating layer104and the second conductive layer105may constitute a capacitor S (capacitance C11), and the third conductive layer107, the third insulating layer106, and the semiconductor substrate101may also constitute a capacitor Q (capacitance C9). The capacitor O, the capacitor P, the capacitor Q, the capacitor R and the capacitor S are connected in parallel, and capacitance C of the capacitor100may be equivalent capacitance of the capacitor O, the capacitor P, the capacitor Q, the capacitor R and the capacitor S in parallel, that is, C=C7+C8+C9+C10+C11.

It should be noted that, a contact point between a second conductive layer and a semiconductor substrate is added between two adjacent first trenches, which is beneficial to reduce equivalent series resistance (Equivalent Series Resistance, ESR) of a capacitor and optimizing capacitor performance.

Optionally, as an embodiment, as shown inFIG. 4, in the capacitor100of the embodiment of the present application, a depth of the first trench108is substantially equal to a thickness of the semiconductor substrate101, and a depth of the second trench109is substantially equal to zero.

Specifically, as shown inFIG. 4, at this time, the semiconductor substrate101is only required to be provided with the first trench108, and there is no need to provide the second trench109, but before forming the third conductive layer, an opening is required to be formed at a position of the third insulating layer corresponding to the first trench such that the third conductive layer is electrically connected to the first conductive layer. The opening formed here has a basic function similar to the second trench.

It should be noted that, in the embodiment, at least one third trench110may be disposed.

Therefore, in the embodiment, only a first trench needs to be etched, which simplifies a fabrication process of a capacitor.

Hereinafter, a method for fabricating a capacitor according to an embodiment of the present application will be introduced in detail with reference toFIGS. 5 to 9. It should be understood thatFIGS. 5 to 9are schematic flow charts of a method for fabricating a capacitor according to an embodiment of the present application, but these steps or operations are merely examples, and other operations or variations of various operations inFIGS. 5 to 9may also be performed in the embodiment of the present application.

FIG. 5illustrates a schematic flow chart of a method200for fabricating a capacitor according to an embodiment of the present application. As shown inFIG. 5, the method200for fabricating the capacitor includes the following steps.

Step201, a semiconductor substrate101is etched to form at least one first trench108in the semiconductor substrate101, where the first trench108is downward from an upper surface of the semiconductor substrate101, and a depth of the first trench108is less than a thickness of the semiconductor substrate101.

Optionally, the semiconductor substrate may be etched according to deep reactive ion etching to form the at least one first trench in the semiconductor substrate.

Specifically, first, a layer of photoresist201is spin-coated on an upper surface (front side) of a semiconductor substrate101as shown inFIG. 6a, and after exposure and development, an etched pattern window not covered with the photoresist is formed, as shown inFIG. 6b. Next, at least one first trench structure108is fabricated in the semiconductor substrate101by deep reactive ion etching. The first trench108extends downward from the upper surface of the semiconductor substrate101, and a depth of the first trench108is less than a thickness of the semiconductor substrate101, as shown inFIG. 6c.

It should be understood that after etching the at least one first trench108, the photoresist201is removed.

Step202, a first insulating layer102is deposited on the upper surface of the semiconductor substrate101and an inner surface of the at least one first trench108.

Specifically, an insulating material is deposited in the at least one first trench to form a first insulating layer102, as shown inFIG. 6d.

For example, silicon dioxide is deposited (grown) as the first insulating layer on the upper surface of the semiconductor substrate and the inner surface of the at least one first trench by means of thermal oxidation. For another example, a silicon nitride or a silicon oxide, such as silicon dioxide converted by undoped silicon glass (USG) or tetraethyl orthosilicate (TEOS), is grown by means of physical vapor deposition (PVD) or chemical vapor deposition (CVD), and used as the first insulating layer. For another example, various types of polymers, such as polyimide, parylene, benzocyclobutene (BCB), or the like, are sprayed or spin-coated and used as the first insulating layer; or the first insulating layer may also be spin on glass (SOG), that is, amorphous phase silicon oxide obtained by spin-coating or spraying a silicide-containing solution on a silicon wafer, then performing heating to remove a solvent, and conducting curing. In view of processing effect and cost, silicon dioxide may be selectively grown as the first insulating layer by means of thermal oxidation.

It should be noted that a material of the first insulating layer102includes a silicon oxide, a silicon nitride, a metal oxide, a metal nitride, or the like, such as silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, zinc oxide, titanium dioxide, lead zirconate titanate, or the like. The first insulating layer may be single-layered, or two or multi-layered. A specific material and a layer thickness may be adjusted according to a capacitance value, a frequency characteristic, a loss and other requirements of a capacitor.

Step203, a first conductive layer103is deposited on an upper surface and an inner surface of the first insulating layer102.

Specifically, in a structure shown inFIG. 6d, a conductive material is deposited on an upper surface and an inner surface of the first insulating layer102to form a first conductive layer103, as shown inFIG. 6e.

It should be noted that, the method of depositing the first conductive layer103includes ALD, PVD, metal-organic chemical vapor deposition, evaporation, electroplating, or the like. A conductive material of the first conductive layer may be heavily doped polysilicon, a carbon-based material, or various metals such as aluminum, tungsten and copper, and may also be a low resistivity compound such as titanium nitride, or a combination of the above several conductive materials. The first conductive layer includes at least one of: a heavily doped polysilicon layer, a carbon-based material layer, a metal layer, and a titanium nitride layer.

Step204, photolithography processing is performed on the first insulating layer102and the first conductive layer103to expose the upper surface of the semiconductor substrate101.

Specifically, first, an upper surface of a structure shown inFIG. 6eis covered with a photosensitive dry film202, and after exposure and development, a dry film protection layer covering the first insulating layer102, the first conductive layer103and their edges is formed, as shown inFIG. 6fNext, the first insulating layer102and the first conductive layer103not covered with the photosensitive dry film202are removed by dry etching. Finally, the photosensitive dry film202is removed to obtain a pattern of a first insulating layer102and a first conductive layer103as shown inFIG. 6g. In this step, the pattern of the first insulating layer102and the first conductive layer103required remains, and excess portions of the first insulating layer102and the first conductive layer103are removed to expose the upper surface of the semiconductor substrate101. It should be understood that the pattern shape of the first insulating layer102and the first conductive layer103remained may be designed according to capacitor specification requirements, and description will not be elaborated here.

Step205, a second insulating layer104is deposited on an upper surface and an inner surface of the first conductive layer103, and the upper surface of the semiconductor substrate101.

Specifically, in a structure shown inFIG. 6g, an insulating material is deposited on an upper surface and an inner surface of the first conductive layer103, and the upper surface of the semiconductor substrate101to form a second insulating layer104, as shown inFIG. 6h.

It should be noted that, the second insulating layer104may refer to the related description of the first insulating layer102. For brevity, details are not described herein again.

Step206, photolithography processing is performed on the second insulating layer104to expose the upper surface of the semiconductor substrate101, where the second insulating layer104covers the first insulating layer102and the first conductive layer103.

Specifically, first, an upper surface of a structure shown inFIG. 6his covered with a photosensitive dry film202, and after exposure and development, a dry film protection layer covering the second insulating layer104is formed, as shown inFIG. 6i. Next, the second insulating layer104not covered with the photosensitive dry film is removed by dry etching. Finally, the photosensitive dry film202is removed to obtain a pattern of the second insulating layer104as shown inFIG. 6j. Similarly, the second insulating layer104in this step remains in a predetermined pattern region, and an excess portion of the second insulating layer104is removed to expose the semiconductor substrate101corresponding to the portion. The second insulating layer104completely covers the first conductive layer103.

Step207, a second conductive layer105is deposited on an upper surface and an inner surface of the second insulating layer104, and the upper surface of the semiconductor substrate101.

Specifically, in a structure shown inFIG. 6j, a conductive material is deposited on an upper surface and an inner surface of the second insulating layer104, and the upper surface of the semiconductor substrate101to form a second conductive layer105, as shown inFIG. 6k.

It should be noted that the second conductive layer105may refer to the related description of the first conductive layer103. For brevity, details are not described herein again.

Step208, the semiconductor substrate101is etched to form at least one second trench109in one-to-one correspondence with the at least one first trench108in the semiconductor substrate101, where the second trench109penetrates upward through the first insulating layer102from a lower surface of the semiconductor substrate101to expose the first conductive layer103, or the second trench109extends upward from a lower surface of the semiconductor substrate101to the first insulating layer102.

Optionally, the semiconductor substrate101may be etched according to deep reactive ion etching to form the at least one second trench109in the semiconductor substrate101.

It should be understood that an upper surface of each material layer in steps202-208refers to a surface of the material layer substantially parallel to the upper surface of the semiconductor substrate, and an inner surface of each material layer refers to an upper surface of the material layer in the trench. The upper surface and the inner surface may be regarded as a whole.

Specifically, first, a layer of photoresist201is spin-coated on a lower surface (back side) of a structure as shown inFIG. 6k, and after exposure and development, an etched pattern window not covered with the photoresist201is formed, as shown inFIG. 6l. Next, at least one second trench structure109is fabricated in the semiconductor substrate101by deep reactive ion etching. Optionally, in Manner I, the second trench109penetrates upward through the first insulating layer102from a lower surface of the semiconductor substrate101to expose the first conductive layer103, as shown inFIG. 6m. In Manner II, the second trench109extends upward from a lower surface of the semiconductor substrate101to the first insulating layer102, that is, only to the surface of the first insulating layer102, as shown inFIG. 6n.

It should be understood that after etching the at least one second trench109, the photoresist201is removed.

Step209, a third insulating layer106is deposited on the lower surface of the semiconductor substrate101and an inner surface of the at least one second trench109.

Specifically, if the second trench109is formed in Manner I in step208, in a structure shown inFIG. 6m, an insulating material is deposited on the lower surface of the semiconductor substrate101and an inner surface of the at least one second trench109to form a third insulating layer106, as shown inFIG. 6o.

If the second trench109is formed in Manner II in step208, in a structure shown inFIG. 6n, an insulating material is deposited on the lower surface of the semiconductor substrate101and an inner surface of the at least one second trench109to form a third insulating layer106, as shown inFIG. 6p.

It should be noted that the third insulating layer106may refer to the related description of the first insulating layer102. For brevity, details are not described herein again.

Step210, if the second trench109penetrates through the first insulating layer102(Manner I in step208), the third insulating layer106deposited on the bottom of the at least one second trench109is removed to expose the first conductive layer103, or,

if the second trench109extends to the first insulating layer102(Manner II in step208), the third insulating layer106deposited on the bottom of the at least one second trench109is removed, and the first insulating layer102deposited on the bottom of the at least one first trench108is removed to expose the first conductive layer103.

Specifically, if the second trench109is formed in Manner I in step208, first, a lower surface of a structure shown inFIG. 6ois covered with a layer of photosensitive dry film202, and after exposure and development, a dry film protection layer covering a lower surface of the third insulating layer106is formed, as shown inFIG. 6q. Next, the third insulating layer106deposited on the bottom of the at least one second trench109is removed by dry etching to expose the first conductive layer103, as shown inFIG. 6r.

If the second trench109is formed in Manner II in step208, first, a lower surface of a structure shown inFIG. 6pis covered with a layer of photosensitive dry film202, and after exposure and development, a dry film protection layer covering a lower surface of the third insulating layer106is formed, as shown inFIG. 6s. Next, the third insulating layer106deposited on the bottom of the at least one second trench109and the first insulating layer102deposited on the bottom of the at least one first trench108are removed by dry etching to expose the first conductive layer103, as shown inFIG. 6t.

Step211, a third conductive layer107is deposited on a lower surface and an inner surface of the third insulating layer106.

Specifically, if the second trench109is formed in Manner I in step208, in a structure shown inFIG. 6r, a third conductive layer107is deposited on a lower surface and an inner surface of the third insulating layer106, as shown inFIG. 6u.

If the second trench109is formed in Manner II in step208, in a structure shown inFIG. 6t, a third conductive layer107is deposited on a lower surface and an inner surface of the third insulating layer106, as shown inFIG. 6v.

It should be noted that the third conductive layer107may refer to the related description of the first conductive layer103. For brevity, details are not described herein again.

Optionally, before etching the semiconductor substrate101in step208, the method200further includes: performing thinning processing on the lower surface of the semiconductor substrate101.

Specifically, the lower surface of the semiconductor substrate101is first thinned to a suitable thickness by means of back grinding and polishing, and then etched to form the at least one second trench109.

It should be noted that when the thickness of the semiconductor substrate101does not satisfy a requirement of a capacitor, thinning processing is performed on the lower surface of the semiconductor substrate101. That is, when the sum of the depth of the first trench108and the depth of the second trench109is less than the thickness of the semiconductor substrate101, thinning processing is required to be performed on the lower surface of the semiconductor substrate101so as to achieve communication between the bottom of the first trench108and the bottom of the second trench109.

performing photolithography processing on the third conductive layer107to expose the lower surface of the semiconductor substrate101.

That is, after step211, photolithography processing is further required to be performed on the third conductive layer107to expose the lower surface of the semiconductor substrate101.

Specifically, first, a layer of photoresist201is spin-coated on a lower surface of a structure as shown inFIG. 6uorFIG. 6v, and after exposure and development, a photoresist pattern covering the third conductive layer107is formed. Next, a metal not covered with the photoresist201is removed with a copper etching solution and a titanium etching solution. Finally, the photoresist201is removed to obtain a capacitor as shown inFIG. 6worFIG. 6x.

It should be understood thatFIG. 6(FIGS. 6a-6x) is exemplified by etching one first trench108and one second trench109, and other numbers of first trenches108and second trenches109may also be etched, which is not limited by the embodiment of the present application.

In this step, a third conductive layer in a pattern region remains according to a pre-designed electrode pattern, and the third conductive layer in the rest region is removed to expose a surface of a semiconductor substrate, and the remained third conductive layer thus forms an electrode of the predetermined pattern, and serves as one electrode of a capacitor.

etching the semiconductor substrate101to form at least one third trench110in the semiconductor substrate101, where the third trench110extends upward from the lower surface of the semiconductor substrate101, and a depth of the third trench110is less than the thickness of the semiconductor substrate101; and

depositing the third insulating layer106on an inner surface of the at least one third trench110, and depositing the third conductive layer107on the inner surface of the third insulating layer106.

Specifically, first, a layer of photoresist201is spin-coated on the lower surface (back side) of the semiconductor substrate101, and after exposure and development, an etched pattern window not covered with the photoresist201is formed. Next, at least one third trench110is fabricated in the semiconductor substrate101by deep reactive ion etching.

Optionally, a capacitor including a third trench110as shown inFIG. 7may be fabricated, and a capacitor including a third trench110as shown inFIG. 8may also be fabricated.

It should be understood thatFIG. 7andFIG. 8are exemplified by etching one first trench, one second trench and two third trenches, and other numbers of first trenches, second trenches and third trenches may also be etched, which is not limited by the embodiment of the present application. The third trench and the second trench may be formed in the same process, that is, the two trenches and filling materials such as an insulating layer and a conductive layer in the trenches may be formed synchronously.

FIG. 9illustrates a schematic flow chart of a method300for fabricating a capacitor according to an embodiment of the present application. As shown inFIG. 9, the method300for fabricating the capacitor includes:

step301, etching a semiconductor substrate to form at least one first trench in the semiconductor substrate, where the first trench is downward from an upper surface of the semiconductor substrate, and a depth of the first trench is less than or equal to a thickness of the semiconductor substrate;

step302, depositing a first insulating layer on the upper surface of the semiconductor substrate and an inner surface of the at least one first trench;

step303, depositing a first conductive layer on an upper surface and an inner surface of the first insulating layer;

step304, performing photolithography processing on the first insulating layer and the first conductive layer to expose the upper surface of the semiconductor substrate;

step305, depositing a second insulating layer on an upper surface and an inner surface of the first conductive layer, and the upper surface of the semiconductor substrate;

step306, performing photolithography processing on the second insulating layer to expose the upper surface of the semiconductor substrate, where the second insulating layer covers the first insulating layer and the first conductive layer;

step307, depositing a second conductive layer on an upper surface and an inner surface of the second insulating layer, and the upper surface of the semiconductor substrate;

step308, depositing a third insulating layer on a lower surface of the semiconductor substrate;

step309, removing the third insulating layer under the at least one first trench to expose the first conductive layer; and

step310, depositing a third conductive layer on a lower surface and an inner surface of the third insulating layer.

Optionally, when the depth of the first trench is less than the thickness of the semiconductor substrate, the method300further includes:

performing thinning processing on the lower surface of the semiconductor substrate before depositing the third insulating layer on the lower surface of the semiconductor substrate (step308).

Specifically, the lower surface of the semiconductor substrate is first thinned to a suitable thickness by means of back grinding and polishing, and then the third insulating layer is deposited on the lower surface of the semiconductor substrate.

performing photolithography processing on the third conductive layer to expose the lower surface of the semiconductor substrate.

Specifically, compared with the method200, the method300mainly differs in that a second trench is not formed on the lower surface of the semiconductor substrate, or the second trench has a depth of zero; and a third insulating layer is formed directly on a semiconductor substrate, and further a window or a hole is opened on the third insulating layer to form a third conductive layer (i.e., an electrode of a capacitor) electrically connected to a first conductive layer. Based on the method300, a capacitor as shown inFIG. 4may be fabricated.

It should be understood that steps in the method300for fabricating a capacitor may refer to the corresponding steps in the method200for fabricating a capacitor. For brevity, details are not described herein again.

Therefore, in the embodiment of the present application, by properly designing a pattern, a first prepared material film is covered and protected in a subsequent photolithography process, thereby reducing etching difficulty and improving process reliability.

A method for fabricating a capacitor according to the present application is further described below in conjunction with a specific embodiment. For ease of understanding, a capacitor as shown inFIG. 1is fabricated in this embodiment. Of course, capacitors shown inFIG. 2,FIG. 3,FIG. 4,FIG. 6,FIG. 7, andFIG. 8may also be fabricated by using the method for fabricating the capacitor in the embodiment, except that design of a trench, coverage area of an insulating layer and a conductive layer as well as other parts are slightly different. For the sake of brevity, details are not described herein again.

Step 1: A boron-doped silicon wafer with resistivity of 0.001-0.005 Ω·cm, a crystal orientation of (100), and a thickness of 750 μm is selected as a semiconductor substrate. A layer of photoresist is spin-coated on an upper surface (front side) of the semiconductor substrate, and after exposure and development, a circular hole of a photoresist is formed on the upper surface of the semiconductor substrate, and a diameter of the circular hole is 10 μm. A first trench having a depth of 120 μm is then processed by using a DRIE process. Finally, the photoresist is removed.

Step 2: By means of an ALD process, 20 nm thick hafnium oxide (HfO2) is deposited on the upper surface of the semiconductor substrate and a surface of the first trench as a first insulating layer.

Step 3: By means of an ALD process, a 25 nm thick titanium nitride (TiN) is deposited on a surface of the first insulating layer (hafnium oxide layer) as a first conductive layer.

Step 4: The upper surface of the semiconductor substrate is covered with a photosensitive dry film, and after exposure and development, a dry film protection layer covering the first trench and its edges is formed. Next, hafnium oxide and titanium nitride not covered with the dry film are removed by dry etching. Finally, the dry film is removed to obtain a pattern of the first insulating layer and the first conductive layer.

It should be noted that the photosensitive dry film occupies a partial region of the upper surface of the semiconductor substrate, and after the hafnium oxide and the titanium nitride not covered with the dry film are removed by dry etching, the upper surface of the semiconductor substrate is exposed.

Step 5: By means of an ALD process, 20 nm thick hafnium oxide (HfO2) is deposited on the upper surface of the semiconductor substrate and a surface of the first conductive layer as a second insulating layer.

Step 6: An upper surface of the second insulating layer is covered with a photosensitive dry film, and after exposure and development, a dry film protection layer covering the second insulating layer and its edges is formed. Next, hafnium oxide not covered with the dry film is removed by dry etching. Finally, the dry film is removed to obtain a pattern of the second insulating layer.

It should be noted that, the photosensitive dry film occupies a partial region of the second insulating layer, and after the hafnium oxide not covered with the dry film is removed by dry etching, the upper surface of the semiconductor substrate is exposed.

Step 7: A second conductive layer is deposited on the upper surface of the semiconductor substrate and the surface of the second insulating layer. A layer of titanium and a thinner layer of copper are first deposited as a barrier layer and a seed layer for electroplating by means of PVD, and then a thicker layer of copper is deposited by electroplating to obtain the second conductive layer.

Step 8: A thickness of the lower surface (back side) of the semiconductor substrate is thinned to 150 μm by means of back grinding and polishing.

Step 9: A layer of photoresist is spin-coated on the lower surface (back side) of the polished semiconductor substrate, and after exposure and development, a circular hole of a photoresist is formed on the lower surface of the semiconductor substrate, and a diameter of the circular hole is 5 μm. A second trench aligned with the first trench is then processed by using a DRIE process. Finally, the photoresist is removed. It should be noted that, a depth of the second trench penetrates through the first insulating layer on the bottom of the first trench to expose the first conductive layer.

Step 10: A 200 nm TEOS is deposited on the lower surface of the semiconductor substrate and a surface of the second trench as a third insulating layer by means of a plasma enhanced chemical vapor deposition (PECVD) process.

Step 11: The lower surface of the semiconductor substrate is covered with a layer of photosensitive dry film, and after exposure and development, an opening is formed at the position of the second trench. The TEOS on the bottom of the second trench is then removed by dry etching to expose the first conductive layer.

Step 12: A third conductive layer is deposited on the lower surface of the semiconductor substrate, the bottom of the second trench, and a surface of the third insulating layer. A layer of titanium and a thinner layer of copper are first deposited as a barrier layer and a seed layer for electroplating by means of PVD, and then a thicker layer of copper is deposited by electroplating to obtain the third conductive layer.

Step 13: A layer of photoresist is spin-coated on a surface of the third conductive layer, and after exposure and development, a photoresist pattern is formed. A metal not covered with the photoresist is removed with a copper etching solution and a titanium etching solution.

It should be noted that, the photoresist occupies a partial region of the third conductive layer, and after the metal not covered with the photoresist is removed by the copper etching solution and the titanium etching solution, a lower surface of the third insulating layer is exposed.

A person skilled in the art can understand that preferred embodiments of the present application are described in detail above with reference to the accompanying drawings. However, the present application is not limited to specific details in the foregoing embodiments. Within the technical concept of the present application, the technical solution of the present application may carry out a variety of simple variants, all of which are within the scope of protection of the present application.

In addition, it should be noted that each of specific technical features described in the above specific embodiments may be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, various possible combination manners will not be described separately in the present application.

In addition, any combination of various different embodiments of the present application may also be made as long as it does not contradict the idea of the present application, and should also be regarded as the content of the application.