Multi-layer integrated RF/IF circuit board

A multi-layered integrated RF/IF circuit board is provided. The board is fabricated beginning with a center layer of material. In a first preferred embodiment, the center layer is a rigid core material. In a second preferred embodiment, the center layer is a pliable non-conductive material. For every layer added to the upper surface of the stack-up structure of the board, a corresponding layer of the same material is added to the lower surface of the stack-up structure. Thus, during the lamination process, both the upper and lower surfaces are primarily soft, pliable non-conductive material. These non-conductive layers absorb any stresses introduced during the lamination process. Thus, when cooled, the board has large area flatness. Standard manufacturing processes can be used for each individual step in the fabrication of the board. Therefore, a multi-layered integrated RF/IF circuit board in accordance with the present invention can be fabricated inexpensively.

CROSS-REFERENCE TO RELATED APPLICATIONS

FIELD OF THE INVENTION

The present invention relates to radio circuit boards, and more particularly to radio circuit boards that transmit and receive high frequency signals over a wireless link.

BACKGROUND OF THE INVENTION

The demand for high speed data connections is growing every day. The cost and delay associated with installing electrical and optical cables to carry high speed data are often greater than the market can bear. As an alternative, wireless broadband access (WBA) services have been developed which allow for transmission of high speed data over the wireless channel. WBA service is typically offered in a relatively high frequency band (such as 18 to 40 GHz) so that the operational bandwidth can be very broad such as about (50 MHz) allowing data rates of 200 megabits per second (MBPS) and higher. Many countries have specifically allocated spectrum for the WBA services. However, the allocated spectrum is not consistent and varies from country to country.

One key element of any WBA system is the radio card which transmits and receives the high frequency signals over the wireless link. Designing a new radio card for each possible frequency band is expensive and time consuming.

As the WBA service market grows, more pre-packaged parts are available to radio designers. For example, Hittite Microwave Corporation™ makes a line of packaged GaAs parts for use in the 20 to 40 GHz range. One part made by Hittite™ is the HMC264LM3 GaAs MMIC Sub-Harmonic SMT Mixer 20–30 GHZ™. The part comes in a leadless chip carrier package. The specification sheet for the part recommends mounting the device on Rogers RO4003™ material using 0.5 oz. copper.

Rogers RO4003™ material is made by Rogers Corporation™. The material is a glass reinforced hydrocarbon thermoset laminate.FIG. 1illustrates a Rogers™ multi-layered printed circuit board (PCB). The stack up100of the Rogers™ PCB includes a core material I with a plurality of conductive and non-conductive layers at its upper and lower surfaces. At the upper surface of the core1, the stack up100includes a first inner conductive layer2A, a first inner non-conductive layer3A, and a first Rogers™ core5A with a first outer conductive layer4A and a first outer-most conductive layer6A. At the lower surface of the core1, the stack up100includes a second inner conductive layer2B, a second inner non-conductive layer3B, and a second Rogers™ core5B with a second outer conductive layer4B and a second outer-most conductive layer6B. As shown inFIG. 1, the stack up100further includes vias7A,7B,8A,8B, and an opening9.

Several difficulties arise with the Rogers™ multi-layer PCB. A typical radio includes both a very high radio frequency (RF) portion and a lower intermediate frequency (IF) portion. However, a composite PCB made from a RO4000 series or other ceramic or Teflon laminate does not provide a good substrate for the lower frequency operation. Lower frequency designs work better with thicker dielectric materials, i.e., larger metal features provides better tolerance at IF, while the high frequency materials are typically very thin. An assembly incorporating a daughter board to carry the RF or IF signaling can be used to boost signal performance, but this solution is more expensive and difficult to manufacture than a single board design.

In addition, the Rogers™ multi-layered PCB requires a custom manufacturing process.FIG. 2is a flowchart illustrating the manufacturing process for the Rogers™ multi-layer PCB. First, the core1is provided with the first inner conductive layer2A at a first surface and the second inner conductive layer2B at a second surface opposite to the first surface, via step201. Next, the first inner non-conductive layer3A is applied to the first inner conductive layer2A, via step202, and a second inner non-conductive layer3B is applied to the second inner conductive layer2B, via step203. Then, a first Rogers™ core5A, with a first outer conductive layer4A on one side and a first outer-most conductive layer6A on the other side, is applied to the first inner non-conductive layer3A, via step204. A second Rogers™ core5B, with a second outer conductive layer4B on one side and a second outer-most conductive layer6B on the other side, is applied to the second inner non-conductive layer3B, via step205. All of the above layers are then simultaneously laminated, via step206. However, this manufacturing process is expensive since specialized, custom processing steps are required.

Conventional radio cards that integrate RF and IF have several other disadvantages. For example, the high frequency materials used in the radio cards are expensive. A PCB which uses these materials is much more expensive to design, prototype, iterate and produce. Even if these high frequency materials are used with standard PCB materials, compatibility and responsibility issues limit their viability. The high frequency materials are typically manufactured by a company different from the one that manufactures the standard PCB materials. If the high frequency material delaminates from the lower frequency materials produced by the other company, no single company is responsible for the failure. This increases both the financial and technical risks associated with the use of a composite PCB.

Also, ceramic laminates are rigid. During the PCB fabrication process, the rigid high frequency material is laminated to a standard rigid FR4 core material using both heat and pressure. A special glue or prepreg material is placed between the high frequency material and the FR4 core. The assembly is pressed between two heated plates. The glue melts and deforms to provide a mechanical connection to the assembly. Because both the high frequency material and the stand FR4 core are rigid, stress builds up between the plates and both surfaces of the PCB at various locations during the lamination process. As the PCB is cooled and removed from the press, the PCB seeks to relieve these stresses by deforming. Because the location of the stresses varies based on the design features impressed on the PCB, the PCB may become concave, convex, wavey or twisted. Predicting the effects of the stress is extremely difficult. Relieving the stress can require redesign of the RF and IF layout of the PCB, or require adjustment in the machinery. Thus, use of rigid ceramic laminates may result in a PCB which is not flat and which causes a variety of negative effects to the fully assembled board.

Another problem with conventional radio cards concerns the mounting of a microstrip filter to the PCB. At high frequency bands, it is convenient to use a microstrip to create certain circuit elements such as transmission lines, couplers and filters. As the frequency band at which the system operates varies, the filtering requirements imposed on the radio card also vary. Thus, in a reusable, versatile PCB design, the microstrip filters cannot be printed directly on the PCB, and the tolerance on a low cost PCB is not good. Instead, the filters can be designed on a surface mount substrate or leadless surface mount substrate. One common substrate is alumina. A surface mount printed filter is soldered to the PCB to provide both signaling and a ground plane to the filter. However, when the conventional PCB is not flat, the surface mount printed filter may not properly attach or it may detach from the PCB when the populated PCB is installed in its housing.

Accordingly, there exists a need for an improved multi-layered integrated RF/IF circuit board. The improved board should provide good RF and IF performance on a single board. Its manufacturing process should be inexpensive, requiring little or no custom processing. The present invention addresses such a need.

SUMMARY OF THE INVENTION

An improved multi-layered integrated RF/IF circuit board has been disclosed. The board is fabricated beginning with a center layer of material. In a first preferred embodiment, the center layer is a rigid core material. In a second preferred embodiment, the center layer is a pliable non-conductive material. For every layer added to the upper surface of the stack-up structure of the board, a corresponding layer of the same material is added to the lower surface of the stack-up structure. Thus, during the lamination process, both the upper and lower surfaces are primarily soft, pliable non-conductive material. These non-conductive layers absorb any stresses introduced during the lamination process. Thus, when cooled, the board has large area flatness. Standard manufacturing processes can be used for each individual step in the fabrication of the board. Therefore, a multi-layered integrated RF/IF circuit board in accordance with the present invention can be fabricated inexpensively.

DETAILED DESCRIPTION

According to the present invention, a versatile radio card design which can be used in a variety of different bands is provided. The radio card is a single versatile printed circuit board (PCB) which can be populated with different components in order to provide operation in one of two or more frequency bands. The PCB in accordance with the present invention is made from standard board materials of the same family of materials. Thus, standard manufacturing processes for the individual steps may be used. The PCB in accordance with the present invention provides good functionality at high frequency (RF) as well as at intermediate frequencies (IF) and with digital signals.

To more particularly describe the features of the present invention, please refer toFIGS. 3 through 15in conjunction with the discussion below.

FIG. 3illustrates a vertical cross-sectional view of a first preferred embodiment of a stack up structure for a multi-layered integrated RF/IF circuit board in accordance with the present invention. The stack up300comprises a core material10with a plurality of conductive and non-conductive layers at its upper and lower surfaces. In this embodiment, the non-conductive layers are prepreg layers but can be other types of glue material. The final stack up300comprises a first, outer-most conductive layer22A, forming Layer1of the stack up300. Components for signal output are mounted on top of the conductive layer22A. Under the first conductive layer22A and coupled to the upper surface of the core10, the final stack up300also comprises a first, outer prepreg layer20A, a first outer conductive layer16A (Layer2), a first inner prepreg layer14A, and a first inner conductive layer12A (Layer3). The first outer conductive layer16A provide the RF ground, while the first inner conductive layer12A provide the IF ground.

Coupled to the lower surface of the core10, the final stack up300also comprises a second inner conductive layer12B (Layer4), a second inner prepreg layer14B, a second outer conductive layer16B (Layer5), a second outer prepreg layer20B, and a second outer-most conductive layer22B (Layer6). The second outer-most conductive layer22B is the ground or routing layer for the stack up300. A waveguide backshort and heat sink (not shown) can be mounted beneath the second outer-most conductive layer22B. Traces are etched onto the conductive layers16A,12A,12B, and16B.

The stack up300further comprises a plurality of vias, including buried vias18A–18B, micro-vias24A–24B, and through vias26A–26B. In order to connect one conductive layer to another, a conductive path through the stack must be constructed. These vertical paths are called vias. A via which traverses the entire stack allowing the interconnection of any layer of the board to any other layer or to multiple layers is called a through via. A via which traverses one or more internal layers but does not traverse either outer layer is called a buried via. A micro-via is a small via (typically with a diameter of 0.002 inches–0.015-inches) that connects an outer layer of a PCB to the nearest inner layer or even deeper if thin substrates are used.

The stack up300further comprises a routed opening28for the waveguide which traverses from the bottom of the stack up300to approximately half-way into the prepreg layer14A.

Note that the stack up300includes only one piece of rigid material, i.e., the core10. Additional layers of conductive material are added using prepreg material. The stack up300is thus symmetrical about a center core10.

FIG. 4is a flowchart illustrating a first preferred embodiment of a method for fabricating a multi-layered integrated RF/IF circuit board in accordance with the present invention. First, a core10is provided with a first inner conductive layer12A at a first surface of the core10and a second inner conductive layer12B at a second surface of the core10opposite to the first surface, via step401. Next, a first inner non-conductive layer14A is applied to the first inner conductive layer12A, via step402, and a second inner non-conductive layer14B is applied to the second inner conductive layer12B, via step403. Next, a first outer conductive layer16A is applied to the first inner non-conductive layer14A, via step404, and a second outer conductive layer16B is applied to the second inner non-conductive layer14B, via step405. The conductive layers12A–12B and16A–16B, the non-conductive layers14A–14B, and the rigid core10are then simultaneously laminated, via step406. The lamination process is performed under high pressure at a high temperature. While under pressure, the stack is heated uniformly and cooled. The heat and pressure melt the resin in the prepreg materials which saturates the fiberglass, providing mechanical coupling of the stack into a single board.

Note that for every layer added to the top of the stack up300, a corresponding layer of the same material is added to the bottom of the stack up300. In addition, during the lamination process, both the upper and lower surfaces are primarily soft, pliable prepreg, the non-conductive material for this embodiment. The prepreg layers14A–14B absorb any stresses introduced during the lamination process by the flow of the melted resin. Thus, once cooled, the stack assembly has large area flatness.

After the first lamination process, via step406, a first outer non-conductive layer20A is applied to the first outer conductive layer16A, via step407, and a second outer non-conductive layer20B is applied to the second outer conductive layer16B, via step408. A first outer-most conductive layer22A is then applied to the first outer non-conductive layer20A, via step409, and a second outer-most conductive layer22B is applied to the second outer non-conductive layer20B, via step410. All of the above layers are then simultaneously laminated in a second lamination process, via step411. As with the first lamination process, the second lamination process is performed under high pressure at a high temperature, where the stack is heated uniformly and cooled. The heat and pressure melt the resin in the prepreg materials which saturates the fiberglass, providing mechanical coupling of the stack into a single board. The first and second outer non-conductive layers20A–20B absorb any stresses introduced during the lamination process by the flow of the melted resin. Thus, once cooled, a board with large area flatness can be realized.

FIG. 5is a flowchart illustrating in more detail the first preferred embodiment of the method for fabricating a multi-layered integrated RF/IF circuit board in accordance with the present invention.FIGS. 6A–6Iillustrate the steps of this method. Referring toFIG. 5andFIGS. 6A–6I, first, a comparatively homogenous material is selected for the core10, via step501and illustrated inFIG. 6A. For example, the core10may be 21 mil, GETEK™ core material made from three layers of 7628 material and sold by GE Electromaterials™ in a prefabricated form. In the prefabricated form, the core10is pre-metalized with the first and second inner conductive layers12A and12B. Traces are then etched on the first inner conductive layer12A and the second inner conductive layers12B, via step502.

The first and second inner prepreg layers14A and14B are applied, respectively, to the etched first and second inner conductive layers12A and12B, via step503and illustrated inFIG. 6B. For example, the first and second inner prepreg layers14A and14B may be made of the 14 mil, GETEK™ prepreg material such as two layers of 7628 GETEK™ material. Next, the first and second outer conductive layers16A and16B are applied, respectively, to the first and second inner prepreg layers14A and14B, via step504and illustrated inFIG. 6C. For example, the conductive layers16A and16B may be thin copper foil selected from a variety of commercially available products. Then, the stack up assembly is laminated, via step505.

As noted above, in steps503and504, the same materials which are applied to the upper surface of the core10are also applied on the lower surface of the core10. Thus, in step505, when the partially completed stack is submitted to the first lamination process, the stack up assembly is symmetrical. In addition, because both the upper and lower surfaces are soft, pliable prepreg, any stresses introduced during the lamination process can be absorbed during the lamination process by the flow of the melted resin. Thus, when the cooled board is removed from the press, the board remains flat. At the completion of step505, the core layer10, the etched conductive layers12A and12B, the prepreg layers14A and14B, and the conductive layers16A and16B are assembled into a mechanically stable expanded core.

After lamination, buried vias18A and18B are drilled through the assembly, typically using a mechanical drill, via step506and illustrated inFIG. 6D. The traces in the conductive layers16A and16B are then etched, via step507. Also in step507, the buried via18A and18B are plated to provide a vertical electrical connection through the PCB.

In step508and illustrated inFIG. 6E, the first and second outer prepreg layers20A and20B are applied to the upper and lower surface of the stack up assembly respectively. For example, the prepreg layers20A and20B may be made of the 7 mil, 7628 GETEK™ prepreg material. In step509and illustrated inFIG. 6F, the first and second outer-most conductive layers22A and22B are applied to the assembly.

The stack up assembly is then laminated again, via step510. As noted above, in steps508and509, the same materials which are applied to the upper surface of the expanded core are also applied on the lower surface of the expanded core. Thus, in step510, when the stack up assembly is submitted to the second lamination process, the stack up assembly is symmetrical. In addition, because both the upper and lower surfaces are primarily soft prepreg, any stresses introduced during the lamination process can be absorbed by the flow of the melted resin. The prepreg material is also relatively inexpensive, which helps to lower the cost of manufacturing as the material is applied to both sides of the core. At the completion of step510, when the cooled board is removed from the press, the board remains flat.

Next, micro-vias24A and24B are drilled (typically by laser) on the upper and lower outer-most layers, via step511and illustrated inFIG. 6G. The through vias26A and26B are drilled through the stack up assembly, via step512and illustrated inFIG. 6H. In step513, the micro and through vias are plated, and the conductive layers22A and22B are etched. Because the RF performance of the micro-vias on the bottom layer of the board, such as micro-via24B, is unimportant if no signals are carried thereby, these micro-vias could be mechanically drilled rather than laser drilled. A routed opening28is drilled into the stack up assembly to support a waveguide transition, via step514and illustrated inFIG. 6I.

Although the first preferred embodiment is described with the sequence of steps above, one of ordinary skill in the art will understand that these steps can be reordered without departing from the spirit and scope of the present invention. In addition, more two sets of prepreg layers can be added consistent with the invention, as well as just one set of prepreg layers.

One advantage of the stack up300is that its manufacturing process is relatively inexpensive. In contrast to conventional stack ups which incorporate special frequency substrates, the stack up300in accordance with the present invention can be constructed using industry standard processes in the individual steps. Not only are the materials from which it is built standard and, thus, less expensive, but the process is also less expensive and simpler. The board can be bid out to a large variety of overseas or domestic board houses, thus further allowing for cost reductions. In addition, the use of materials from with the same family of materials assist in assuring compatibility of materials and flatness of the board.

In the first preferred embodiment of the stack up300, the outer non-conductive layer20A is 7 mil prepreg. The thin nature of this material makes it particularly advantageous for high frequency (RF) strip line design (such as, for example, at 18 to 40 GHz). The bulk of the components are installed upon the upper most surface of the conductive layer22A. To provide good performance at IF, the first outer conductive layer16A under the IF section of the board can be etched away. Thus, the first outer prepreg layer20A and adjacent prepreg layer14A directly contact one another under the IF section. Since the prepreg layers20A and14A are of the same material, they form a single substrate. Thus, under the IF circuitry, a thicker dielectric layer is produced. For example, according to the exemplary dimensions given above, the combined substrate is 21 mils thick. This thicker dielectric layer under the IF section of the board provides good performance at IF.

The first preferred embodiment of the stack up300can also be used to provide an effective heat sink for a component installed thereon.FIG. 7illustrates a top view of a stack up providing a heat sink for an RF component in accordance with the present invention. The part outline100shows the outline of an RF part. For illustrative purposes, we assume that the RF part is a commercial, prepackaged part. A series of micro-vias24A.1–24A.N provides both an RF ground and a heat flow path. The buried vias18A–18N are located in close proximity to the micro-vias24A–24N and provide a heat path through the majority of the board depth. The buried vias18A–18N carry the heat from the second conductive layer16A, the ground layer under the RF section, to the sixth conductive layer22B.

The micro-vias24B.1–24B.N transfer the heat from the sixth conductive layer22B to an external heat sink (not shown) coupled to the sixth conductive layer22B on the board. The micro-vias24B.1–24B.N are located in proximity to the buried vias18A–18N to more effectively transfer heat. The micro-vias24B.1–24B.N may be scattered under the part outline100. Also shown inFIG. 7are a series of conductive pads108for the leads of the RF part. It is also possible to locate one of the buried vias18A–18N directly beneath one of the micro-vias24A.1–24A.N, with the buried vias filled. Likewise, it is possible to locate one of the buried vias18A–18N directly above one of the micro-vias24B.1–24B.N.

The RF characteristics of the micro-vias, such as24A, which connect the first conductive layer22A and the second conductive layer16A are important, especially if they are used to carry ground currents or RF signaling. The RF performance of a micro-via is best when the micro-vias has uniform shape, meaning that the sloping walls of the micro-via are fairly smooth and uniformly sloped.

Conventional wisdom is to use prepreg material with as much resin and as little fiberglass as possible to achieve micro-vias with a uniform shape. Contrary to this teaching, with the present invention, a prepreg material that has less resin produces a via with a more uniform shape. Thus, in a board with less resin, the percentage of fiberglass in the removed material is more uniform over the surface of the board leading to the formation of more uniform vias. Thus, as noted above, the prepreg material used in the first preferred embodiment uses 7628 GETEK™ prepreg material which has a relatively low resin content. The use of a low resin content material also increases the board flatness on a microscopic level.

In order to bring an RF signal onto the board as well as transition an RF signal off the board, some means of connecting the board to an external signal carrying mechanism must be devised. One typical external signal carrying mechanism is the waveguide. A waveguide is an electromagnetic feed line used in microwave communications. A waveguide consists of a rectangular or cylindrical metal tube or pipe. The electromagnetic field of the carried signal propagates lengthwise down the waveguide. A waveguide provides low loss and high efficiency connection as long as the interior of the waveguide is kept clean and dry.

In the first preferred embodiment, to facilitate the signal transition via a waveguide, the stack up300is routed from the second outer-most conductive layer22B through to part-way into the first inner prepreg layer14A.FIGS. 8 and 9illustrate a vertical and a horizontal cross-sectional views, respectively, of the routed opening28in the stack up structure in accordance with the present invention. Buried vias (18A,18B, . . . ) are drilled as described above such that they form the walls of the routed opening28. InFIG. 9, these buried vias (18A,18B, . . . ) reside within the area marked with a dotted rectangle starting in Layer2of the stack up300. By drilling the buried vias (18A,18B, . . . ) in this way, a virtual waveguide is created within the route opening28. A metal patch901is mounted on top of the conductive layer22A over the opening28. A microstrip902traverses on top of the buried vias (18A,18B, . . . ) to the metal patch901. In this manner, signals received by the board are sent from the microstrip through the metal patch901to the waveguide28. Similarly, signals transmitted by the board are sent from the waveguide28to the metal patch901and to the microstrip902. Transitioning signals on and off the board in this manner requires no tuning on the board. The routed opening28is also a transition which is less lossy than conventional boards.

Although the first preferred embodiment describes the stack up with buried vias as the walls of the waveguide, a stack up can be designed such that the buried vias are not necessary.FIG. 10illustrates a horizontal cross-sectional view of a second preferred embodiment of a stack up for a multi-layered integrated RF/IF circuit board in accordance with the present invention. In the second embodiment, the through vias1011are drilled very close to the microstrip902. With this configuration of through vias1011, signals can be carried between the routed opening1012and the microstrip902via the metal patch901without the need for buried vias.

Without the need for buried vias, a second preferred embodiment of the stack up structure which is even less expensive to manufacture than the first preferred embodiment of the stack up structure300is possible.FIG. 11illustrates a vertical cross-sectional view of a second preferred embodiment of a stack up structure for a multi-layered integrated RF/IF circuit board in accordance with the present invention. The second preferred embodiment of the stack up1100comprises a pliable non-conductive center material1001with a plurality of conductive and non-conductive layers at its upper and lower surfaces. In this embodiment, the non-conductive layers are prepreg layers. The final stack up1100comprises a first, outer most conductive layer1008, forming layer1of the stack up1100. Components for signal output are mounted on top of the conductive layer1008. Coupled to the upper surface of the central prepreg layer1001, the final stack up1100also comprises a first outer prepreg layer1006, a first outer conductive layer1003A, a first core1002, and a first inner conductive layer1003B. Coupled to the lower surface of the center prepreg layer1001, the stack up1100also comprises a second inner conductive layer1005A, a second core1004, a second outer conductive layer1005B, a second outer prepreg layer1007, and a second outer-most conductive layer1009. A waveguide backshort and heat sink (not shown) can be mounted beneath the sixth conductive layer1009. Traces are etched onto the conductive layers1003A,1003B,1005A, and1005B.

The stack up1100further comprises a plurality of vias, including micro-vias1010A–1010B and through vias1011. The stack up1100further comprises a routed opening1012for the waveguide which traverses from the bottom of the stack up1100to approximately half-way into the first core1002.

Note that the stack up1100has no buried vias, as they are not necessary to provide walls to the routed opening1012. The stack up1100is also symmetrical about a center layer1001. Electrically, the second preferred embodiment of the stack up1100is substantially identical to the first preferred embodiment of the stack up300. In the stack up1100, the first outer conductive layer1003A provides the RF ground, while the first inner conductive layer1003B provide the IF ground. The second outer-most conductive layer1009is the ground or routing layer for the stack up1100. However, because the stack up1100does not have buried vias, its manufacturing process is less expensive than for the stack up300.

FIG. 12is a flowchart illustrating a second preferred embodiment of a method for fabricating a multi-layered integrated RF/IF circuit board in accordance with the present invention. The process begins with the center prepreg layer1001, via step1201. Then, a first core1002is provided with a first outer conductive layer1003A at a first surface of the first core1002and a first inner conductive layer1003B at a second surface of the first core1002opposite to the first surface, via step1202. A second core1004with a second inner conductive layer1005A at a first surface of the second core1004and a second outer conductive layer1005B at a second surface of the second core1004opposite to the first surface is also provided, via step1203. Then, the first inner conductive layer1003B, with the core1002and the first outer conductive layer1003A, is applied to a first surface of the center prepreg layer1001, via step1204. The second inner conductive layer1005A, with the second core1004and the second outer conductive layer1005B, is applied to a second surface of the center prepreg layer1001, via step1205. Next, the first outer prepreg layer1008is applied to the first outer conductive layer1003A, and the second outer prepreg layer1007is applied to the second outer conductive layer1005B, via step1206. Next, the first outer-most conductive layer1008is applied to the first outer prepreg layer1006, and a second outer-most conductive layer1009is applied to the second outer prepreg layer1007, via step1207. The prepreg, core, and conductive layers are then laminated, via step1208. Thus, with the second preferred embodiment, the stack up1100is fabricated with a single lamination step. Because both the upper and lower surfaces are primarily soft prepreg, any stresses introduced during the lamination process can be absorbed by the flow of the melted resin. At the completion of step1208, when the cooled board is removed from the press, the board remains flat.

FIG. 13is a flowchart illustrating in more detail the second preferred embodiment of a method for fabricating a multi-layered integrated RF/IF circuit board in accordance with the present invention.FIGS. 14A through 14Eillustrate the steps of this method. Referring toFIG. 13andFIGS. 14A through 14E, the process begins with the center prepreg layer1001, via step1301and illustrated inFIG. 14A. Then, a first core1002with the first outer conductive layer1003A and the first inner conductive layer1003B are provided, via step1302and illustrated inFIG. 14B. The second core1004with the second inner conductive layer1005A and a second outer conductive layer1005B are also provided, via step1303. Traces are then etched on the first and second inner and outer conductive layers1003A,1003B,10054A,1005B, via step1304.

The first core1002with the first inner and outer conductive layers1003A–1003B are then applied to the first side of the center prepreg layer1001, via step1305and illustrated inFIG. 14C. The second core1004with the second inner and outer conductive layers1005A–1005B are also applied to the second side of the center prepreg layer1001, via step1306. Next, the first outer prepreg layer1008is applied to the first outer conductive layer1003A, and a second outer prepreg layer1007is applied to the second outer conductive layer1005B, via step1307and illustrated inFIG. 14D. Then the first outer-most conductive layer1008is applied to the first outer prepreg layer1006, and a second outer-most conductive layer1009is applied to the second outer prepreg layer1007, via step1308and illustrated inFIG. 14D.

The conductive layers, prepreg layers, and cores, are then laminated together, via step1309. The micro-vias1010A–1010B are then lasered into the stack up1100, via step1310, the through vias1011are drilled, via step1311and illustrated inFIG. 14E. Traces are etched on the first and second outer-most conductive layers1008-1009with the micro-vias1010A–1010B and the through vias1011, via step1312. An opening1012is then routed for the waveguide, via step1313and illustrated inFIG. 14E.

As with the first preferred embodiment of the stack up300, the first outer conductive layer1003A is etched under the IF section of the board. Thus, the first outer non-conductive layer and the first core touch to form a single dielectric layer. In this manner, a thicker dielectric under the IF section of the board is provided, which provides good performance at IF.

In the second preferred embodiment of the stack up1100, the heat flow paths are provided by the through vias1011. The through vias1011are interleaved with pads for solder balls (not shown) of the components mounted on the first outer-most conductive layer1008.

Once the stack up300or1100is formed, components (not shown) are coupled to the outer surface of the first outer-most conductive layer22A or1008, respectively. One of these components is a filter. In the preferred embodiments, the filter is an alumina filter. In placing the filter upon the conductive layer22A or1008, accurate alignment to the input and output signal transitions of the board is important. This is because a housing is later clamped to the board around the filter with tight tolerances since the housing creates a very specific electrical cavity. If the filter is not aligned accurately, the housing would hit the filter and destroy it during assembly. To facilitate the accurate placement of the filter, the present invention utilizes a specific solder pad and resist pattern.

FIG. 15illustrates a preferred embodiment of the solder pad and solder resist pattern for mounting a filter onto a circuit board in accordance with the present invention. Here, the filter must align to the signal input/output transitions1503A–1503B. Micro-vias1504A–1504B are placed under these transitions to bring the ground up into the filter. The solder resist1501and solder pads1502are strategically placed on the board, such that when the filter is aligned and attached onto the board, the filter does not misalign to the transitions1503A–1503B and also remains flat. In this manner, a filter can be mounted onto the board without being destroyed by the housing during assembly.

An improved multi-layered integrated RF/IF circuit board has been disclosed. The board is fabricated beginning with a center layer of material. In a first preferred embodiment, the center layer is a rigid core material. In a second preferred embodiment, the center layer is a pliable non-conductive material. For every layer added to the upper surface of the stack-up structure of the board, a corresponding layer of the same material is added to the lower surface of the stack-up structure. Thus, during the lamination process, both the upper and lower surfaces are primarily soft, pliable non-conductive material. These non-conductive layers absorb any stresses introduced during the lamination process. Thus, when cooled, the board has large area flatness. Standard manufacturing processes can be used for each individual step in the fabrication of the board. Therefore, a multi-layered integrated RF/IF circuit board in accordance with the present invention can be fabricated inexpensively.