METHOD AND APPARATUS FOR MANAGING WAVEFORM DATA AND DELAYS IN A WAVEFORM GENERATOR

A signal decode circuit is coupled to a buffer for each signal channel. A memory includes a shared area configured to store waveform data sets, each waveform data set including a sequence of coded waveform values specifying waveform step states. The shared area further stores delay data sets, each delay data set including a digital delay value for each signal channel defining a delay profile. A signal pointer addresses the shared area to read one waveform data set from the memory with the sequence of coded waveform values being selectively loaded into one or more of the buffers. A delay pointer addresses the shared area to read one delay data set from the memory with the digital delay values used to control delayed actuation of the signal decode circuits to decode the sequence of coded waveform values from the buffers and generate waveform signals in accordance with the delay profile.

TECHNICAL FIELD

Embodiments herein relate to a waveform generator. In particular, the waveform generator is well-suited for use in generating selected waveform signals that are applied with selected delays to transducers in an ultrasound imaging system.

BACKGROUND

Reference is made toFIG.1which shows a block diagram for a transmitter of an ultrasound imaging system10. A plurality of transducer elements12generate acoustic signals14a, . . . ,14nin response to corresponding waveform signals16a, . . . ,16n. The waveform signals16a, . . . ,16nmay all be identical to each other, or all may be different from each other, or some plural number of waveform signals may be the same and others different. The waveform signals16a, . . . ,16nare generated by a waveform generator18and supplied to high voltage analog pulse driver (D) circuits20coupled to transducer elements12that perform signal level shifting operations on the received waveform signal16. Each pair of an analog pulse driver circuit20and transducer12forms a signal channel25for a waveform signal. The waveform generator18includes a waveform memory circuit and a beamforming circuit. The waveform memory circuit stores coded waveform data defining the shapes of various waveform signals. The beamforming circuit reads the coded waveform data from the memory, decodes the data to determine waveform state information and generates the corresponding waveform signal16. The beamforming circuit further receives a delay control signal22generated by a delay control circuit24. The delay control signal22specifies a relative delay to be applied by the beamforming circuit in supplying each of the waveform signals16a, . . . ,16nto the corresponding waveform signal channels25a, . . . ,25n. The analog pulse driver circuits20of the waveform signal channels25amplify the waveform signals16for application to the transducer elements12to generate the acoustic signals14. Responsive to the delay control signal22, the beamforming circuit produces different delayed internal triggers for each of the waveform signal channels25a, . . . ,25nthat are used to start read operations to retrieve the coded waveform data from the memory and perform decoding with a relative signal transmission delay between the waveform signal channels. The delay control signal22is generated by the delay control circuit24in response to a direction signal26that specifies an angle Θ for an imaging direction for the wavefront28of the acoustic signals14.

Each waveform signal16is a pulsed voltage signal defined by a sequence of waveform steps, wherein each step is defined (at least in part) by a signal state (or value such as a voltage level). In one case, the waveform step states may be binary (i.e., there are two states: high and low, for example). In another case, the waveform step states may be ternary (i.e., there are three states: high, intermediate and low, for example). More generally speaking, the waveform step states may be m-ary (i.e., there are m distinct states or levels).FIG.2illustrates an example of an N step (where N=8) ternary waveform signal16. The three states possible at each waveform step inFIG.2include a positive (high) voltage state (HV+), an intermediate clamp state (CLP) and a negative (high) voltage state (HV−).

Reference is now made toFIG.3which shows a block diagram for the waveform generator18. The waveform generator18includes a first memory100including a plurality of delay channel memory areas102a-102n. Each of the delay channel memory areas102a, . . . ,102ncorresponds to one of the waveform signal channels25a, . . . ,25nand stores a digital delay value specifying for that waveform signal channel a signal delay to be applied for the generation of a corresponding one of the waveform signals16a, . . . ,16n. Collectively, the digital delay values stored in the delay channel memory areas102a-102nmay be referred to as a delay data set which describes a delay profile for the generation of the waveform signals16a, . . . ,16n. The digital delay values making up the delay data set are loaded in the first memory100by the delay control circuit24using the delay control signal22. A counter circuit104is actuated in response to a transmission start signal106to begin counting and output an incrementing (for example) counter value108. A comparison circuit110compares each digital delay value stored in the delay channel memory areas102a-102nto the incrementing counter value108. When there is a match between the incrementing counter value108and one of the digital delay values of the delay data set, the comparison circuit110asserts (for example, pulses logic high) a start transmission signal112a-112nfor the corresponding waveform signal channel25a, . . . ,25n.

The waveform generator18further includes a second memory120including a plurality of waveform signal data channel memory areas122a-122n. Each of the waveform signal data channel memory areas122a, . . . ,122ncorresponds to one of the waveform signal channels25a, . . . ,25nand stores a sequence of coded waveform values specifying the waveform step states of the waveform signal16to be generated for that waveform signal channel (with the timing delay specified by the digital delay value stored in the corresponding delay channel memory area102). Collectively, the coded waveform values stored in each of the waveform signal data channel memory areas122a-122nmay be referred to as a waveform data set which will result in the generation of the pulsed voltage signal levels for the desired waveform signal16. A decoder and signal driver circuit124for each of the waveform signal channels25a, . . . ,25ngenerates the waveform signal16by decoding the coded waveform values of the waveform data set retrieved from one of the waveform signal data channel memory areas122a, . . . ,122nto identify signal states and the pulsed voltage signal levels for the waveform signal16are generated in accordance with the identified signal states.

Reference is now additional made toFIG.4which shows an example of a waveform signal data channel memory area122. Each data location134in a sequence of consecutive addressable data locations for each waveform signal data channel memory area122includes a data field storing data bits (referred to herein as a coded waveform value) defining the m-ary signal state of a waveform step in a given waveform data set for a waveform signal16. The decoder and signal driver circuits124a, . . . ,124nrespond to the pulsing of the start transmission signals112a-112nby controlling an address pointer signal126to sequentially point to the addressable data locations134in the waveform signal data channel memory areas122a-122n, respectively, that are storing the waveform data set for the desired waveform signal. The coded waveform values stored at the addressed data locations are sequentially read from the waveform signal data channel memory area122and output as a code sequence signal128. Each coded waveform value in the code sequence signal128is decoded by a decoding function of the decoder and signal driver circuit124to determine an analog signal level for the corresponding waveform step. A signal generating function of the decoder and signal driver circuit124then generates the waveform signal16to include the determined signal level for each waveform step. The generated waveform signal16is supplied to the high voltage analog pulse driver circuit20(see,FIG.1) to be level shifted in connection with driving the associated transducer12.

The memory data locations134shown inFIG.4illustrate N (where N=8) sequentially addressable data locations storing the coded waveform values for the waveform data set of the example waveform signal shown inFIG.2. It will be understood that the memory area122may include many more than N data locations134. Because the waveform signal is of a ternary type, only two bits are needed for the coded waveform values to code the three possible signal states for each step (where, for example, the coded waveform value <10> codes the positive (high) voltage state (HV+), the coded waveform value <11> codes the intermediate clamp state (CLP), and the coded waveform value <01> codes the negative (high) voltage state (HV−)). So, in the context of the example waveform signal16shown inFIG.2, the first data location134in the sequence stores coded waveform value <11> for the intermediate clamp state of signal step1, the second data location134in the sequence stores coded waveform value <10> for the positive (high) voltage state of signal step2, the third data location134in the sequence stores coded waveform value <01> for the negative (high) voltage state of signal step3, . . . , and the eighth data location134in the sequence stores coded waveform value <11> for the intermediate clamp state of signal step8.

In the implementation shown inFIG.3, the first memory100, counter104, comparison circuit110and decoder and signal driver circuits124a, . . . ,124ngenerally correspond to the beamformer circuit of the waveform generator18inFIG.1and the second memory120corresponds to the waveform memory circuit of the waveform generator18inFIG.1.

It will be noted that the implementation of the waveform generator18as shown inFIG.3utilizes dedicated memory resources for each waveform channel25. In other words, each waveform channel25is associated with a dedicated delay channel memory102and a dedicated waveform signal data channel memory area122. The memory resources with this implementation are not managed efficiently.

SUMMARY

In an embodiment, a waveform generator comprises: a plurality of signal channels; a memory including: a shared area configured to store a plurality of waveform data sets, each waveform data set comprising a sequence of coded waveform values specifying waveform step states; and an active area including a buffer for each signal channel, each buffer configured to store a selected waveform data set of the plurality of waveform data sets; and a signal decode circuit coupled to the buffer for each signal channel. The memory further comprises: a signal pointer configured to address said shared area of the memory to read one waveform data set from the memory; and a mask vector circuit configured to selectively load said one waveform data set as the selected waveform data set into one or more of the buffers in the active area of the memory in accordance with a mask signal. The signal decode circuit is configured to decode the coded waveform values of the selected waveform data set in the buffer and generate a waveform signal on the signal channel having the waveform step states.

In an embodiment, a waveform generator comprises: a plurality of signal channels; and a memory including: a shared area configured to: store a plurality of delay data sets, each delay data set comprising a digital delay value for each signal channel; and a plurality of waveform data sets, each waveform data set comprising a sequence of coded waveform values specifying waveform step states; and an active area including a buffer for each signal channel, each buffer configured to store a selected waveform data set. A signal decode circuit is coupled to the buffer for each signal channel, wherein said signal decode circuit is configured to decode the coded waveform values of the waveform data set in the buffer and generate a waveform signal on the signal channel having the waveform step states. A delay control circuit is configured to control the signal decode circuits to generate the waveform signals with a delay profile specified by the digital delay values of a selected delay data set. The memory further comprises: a delay pointer configured to address said shared area of the memory to read the selected delay data set from the memory; and a signal pointer configured to address said shared area of the memory to read the selected waveform data set from the memory.

In an embodiment, a waveform generator comprises: a plurality of signal channels; and a memory including: a delay area including a plurality of rows, wherein each row is configured to store a delay data set with a digital delay value for each signal channel; a shared area configured to store a plurality of waveform data sets, each waveform data set comprising a sequence of coded waveform values specifying waveform step states; and an active area including a buffer for each signal channel, each buffer configured to store a selected waveform data set. A signal decode circuit is coupled to the buffer for each signal channel, wherein said signal decode circuit is configured to decode the coded waveform values of the waveform data set in the buffer and generate a waveform signal on the signal channel having the waveform step states. A delay control circuit is configured to control the signal decode circuits to generate the waveform signals with a delay profile specified by the digital delay values of a selected delay data set. The memory further comprises: a delay pointer configured to address a selected row of said delay area of the memory to read the selected delay data set from the memory; and a signal pointer configured to address said shared area of the memory to read the selected waveform data set from the memory.

The waveform generator may be used in a system where each waveform signal is applied to a transducer.

DETAILED DESCRIPTION OF THE DRAWINGS

Reference is made toFIG.5Awhich shows a block diagram for a transmitter of an ultrasound imaging system200. A plurality of transducer elements212generate acoustic signals in response to corresponding waveform signals216a, . . . ,216n. The waveform signals216a, . . . ,216nmay all be identical to each other, or all may be different from each other, or some plural number of waveform signals may be the same and others different. The waveform signals216a, . . . ,216nare generated by a waveform generator and supplied to the high voltage analog pulse driver (D) circuits220coupled to transducer elements212that perform signal level shifting operations on the received waveform signal216. Each pair of an analog pulse driver circuit220and transducer212forms a signal channel225for a waveform signal216.

The waveform generator includes a memory circuit202and a beamforming circuit204. The memory circuit202includes a shared waveform area230which stores waveform data sets (WDS), wherein each waveform data set comprises a sequence of coded waveform values specifying the waveform step states, representing the shapes of various waveform signals216. The memory circuit202further includes a shared delay set area232which stores delay data sets (DDS), wherein each delay data set includes digital delay values specifying the signal delays to be applied at the waveform signal channels225a, . . . ,225n, representing various delay profiles for the generation of the waveform signals216a, . . . ,216n. The memory circuit202still further includes an active area234which stores the waveform data sets for the waveform signal channels225a, . . . ,225nrepresenting the shapes of the waveform signals16a, . . . ,16nthat have been selected to be generated in order to produce a desired acoustic signal output.

The memory circuit202may be implemented as any suitable memory circuit such as a random access memory (RAM) and can be arranged in a plurality of memory column (or memory block) areas238a, . . . ,238ncorresponding to the plurality of channels225a, . . . ,225n. Each memory column area238includes N memory rows (for example, N=256). The first X rows (i.e., rows 0 to X−1) in each column area238are a part of the active area234, the next Y rows (i.e., rows X to X+Y−1) are a part of the shared waveform area230, and the next Z rows (i.e., rows X+Y to N−1) are a part of the delay set area232.

A delay pointer240is used to selectively point to a row of memory locations in the delay set area232to read one of the stored delay data sets (DDS) from the memory202which provides the digital delay values for a desired delay profile to be applied in the generation of the waveform signals216a, . . . ,216nfor the corresponding waveform signal channels225a, . . . ,225n. For example, the value of the delay pointer may specify a certain row across the column areas238a, . . . ,238nin the delay set area232where a corresponding set of n digital delay values data set are stored. The digital delay values of the selected row are read from the memory and used to specify the delays for each channel of a given transmission.

Reading from the row identified by the address loaded in the delay pointer240, the digital delay values of the read delay data set242are then loaded in the delay registers244of the beamforming circuit204. The delay registers244store the digital delay values and the beamforming circuit204includes a comparison circuit110that operates to compare an incrementing counter value (generated by a counter circuit104) to each of the register stored delay values for the purpose of triggering waveform signal216generation (see,FIG.3, signals112a-112n).FIG.5Aspecifically illustrates, by example, the pointing of the delay pointer240to one row of memory locations246across the column areas238storing the digital delay values for a certain delay data set DDS to produce the read digital delay set242for storage in the delay registers244.

It will be noted that consecutive rows of memory locations in the delay set area232can be loaded with consecutive sets of digital delay values. A processing automation can be implemented where the delay pointer240is auto-incremented by one at the end of each transmission to select the next set of digital delay values for the next transmission.

A signal pointer250of the memory circuit202is used to selectively point to a sequence of memory locations in the shared waveform area230to read one of the stored waveform data sets (WDS) from the memory which provides the sequence of coded waveform values specifying shape of a desired one of the waveform signals216to be generated. For example, the value of the signal pointer may specify a starting location at a certain row in a certain one of column areas238a, . . . ,238nfor a sequence of memory locations the shared waveform area230where the sequence of coded waveform values for a selected waveform data set is stored.

Reading from the starting location identified by the address loaded in the signal pointer250, the sequence of coded waveform values for the selected waveform data set252are then processed through a mask vector circuit254and selectively loaded into one of more of the buffer memory areas256a, . . . ,256n(within column areas238a, . . . ,238n, respectively) of the active area234. The mask vector circuit254receives a destination mask signal that specifically identifies which one or ones of the buffer memory areas256are to be loaded with the read waveform data set252. The destination mask signal may, for example, comprise an n-bit digital signal wherein a logic high value at a given bit location in the signal specifies that the read waveform data set252is to be stored in the buffer memory area256corresponding to that bit location. It is important to note that the waveform data set for the desired waveform signal shape can be stored in any of the column areas238a, . . . ,238nof the shared waveform area230. In other words, due to the shared nature of the shared waveform area230, the waveform data set stored in a given one of the column areas238is not linked to the corresponding signal channel, and may indeed be used by the beamforming circuit in connection with generating the waveform signal for any signal channel (subject to selection made by the vector mask circuit). As an example, the sequence of memory locations in the shared waveform area230may comprise p memory locations, wherein the sequence of p memory locations stores the coded waveform values for the waveform data set defining one or more waveform steps of the desired waveform signal216. A decoder and signal driver circuit124for each waveform signal channel225applies an address pointer signal126to sequentially point to addressable data locations in the buffer memory area256that store the waveform data set for the desired waveform signal. The coded waveform values stored at the addressed data locations are sequentially read from the buffer memory area256and output as a code sequence signal128. Each coded waveform value in the code sequence signal128is decoded by a decoding function of the decoder and signal driver circuit124to determine an analog signal level for the corresponding waveform step. A signal generating function of the decoder and signal driver circuit124then generates the waveform signal216to include the determined analog signal level for each waveform step. The generated waveform signal216is supplied to the high voltage analog pulse driver circuit220to be level shifted in connection with driving the associated transducer212.

FIG.5Aspecifically illustrates, by example, the pointing of the signal pointer250to a sequence of memory locations260in column area238estoring coded waveform values for the waveform data set WDS of a desired waveform signal. In this example, the n-bit destination mask signal has a value of <10010 . . . 01>. The logic “1” data bits in the destination mask signal indicate that read waveform data set252is to be selectively stored by the mask vector circuit254in the buffer memory areas256a,256dand256n(of corresponding column areas238a,238d, and238n). The logic “0” data bits in the n-bit destination mask signal indicate that the read waveform data set252is blocked by the mask vector circuit254from being loaded in the buffer memory areas of the corresponding column areas. The coded waveform values of this waveform data set WDS are then processed by the decoder and signal driver circuits124to generate the waveform signals216a,216dand216nfor channels225a,225d, and225n.FIG.5Afurther illustrates, by example, the pointing of the signal pointer250to a sequence of memory locations261in column area238nstoring coded waveform values for another waveform data set WDS' of a desired waveform signal. In this example, the n-bit destination mask signal has a value of <01101 . . . 10>. The logic “1” data bits in the destination mask signal indicate that read waveform data set252is to be selectively stored by the mask vector circuit254in the buffer memory areas256b,256c,256eand256m(of corresponding column areas238b,238c,238eand238m). The logic “0” data bits in the n-bit destination mask signal indicate that the read waveform data set252is blocked by the mask vector circuit254from being loaded in the buffer memory areas of the corresponding column areas. The coded waveform values of this another waveform data set WDS' are then processed by the decoder and signal driver circuits124to generate the waveform signals216b,216c216eand216mfor channels225b,225c,225eand225m.

From the foregoing, it will be noted that the process for reading a waveform data set from the shared waveform area230using the signal pointer250can be repeated as many times as necessary to selectively load through the mask vector circuit254a sequence of coded waveform values in each of the buffer memory areas256a, . . . ,256n.

A control circuit270generates a load command signal272that is applied to the memory202. Responsive to this load command signal272, the memory202is configured to use the delay pointer240to retrieve the desired one delay profiles stored in the delay set area232for loading in the delay registers244of the beamforming circuit204. Further responsive to this load command signal272, the memory202is configured to use the signal pointer250to retrieve the coded waveform data for the waveform data sets WDS of one or more desired waveform signals for loading in the buffer memory areas256a, . . . ,256n. The control circuit270further generates a counter start command signal274that is applied to the counter circuit104in the beamformer circuit204. Responsive to this counter start command signal274, incrementing of the counter104is initiated. When the comparison circuit110determines that the incrementing count value matches any of the digital delay values stored in the delay registers244, the start transmission signal112is pulsed and the corresponding decoder and signal driver circuit124retrieves the coded waveform data for the waveform data set WDS from buffer memory area256to generate the waveform signal216. The control circuit270still further generates the destination mask signal to control the mask vector254operation for selectively loading coded waveform data in the buffer memory areas256a, . . . ,256n.

It will be noted that in the embodiment ofFIG.5A, the memory resources of memory circuit202are separated into three general types: a) a shared waveform area230where waveform data sets are stored; b) a delay set area232where delay data sets are stored; and c) an active memory area234that provides an output buffer256dedicated to each channel225in order to support independent waveform signal generation with a configured timing delay. There are fixed boundaries between the three types, and the user can configure the memory circuit202, and in particular the size of each of the shared memory area230, the delay set area232, and the active memory area234as necessary in order to store the desired number of waveform data sets and delay data sets. Separation between the shared memory area230, delay set area232, and the active memory area234is logical (or functional) only, not necessarily physical. So, it will be understood that the boundaries between the areas230,232,234are flexible. The actual addresses occupied by each type of data are simply defined by the user. The only limitation that is imposed is given by the actual physical memory size.

Operation of the memory for loading the desired waveform data set(s) and desired delay data set is efficient. Turning first to the loading of the desired delay data set, the delay pointer240is used to point to a row location in the delay set area232across the column areas238that stores the digital delay data (of the desired delay profile defined by the delay data set) for each of the signal channel225. The read digital delay data values at that row are loaded in the delay registers244and are ready to be used to manage individual signal delays in connection with generating the waveform signals216a, . . . ,216n. Turning next to the loading of the desired waveform data set(s), the signal pointer250is used to point to a starting location anywhere in the shared memory area (more specifically within the shared waveform area230) to select a memory row within a column area238that stores the coded waveform data for a first waveform step (of the desired waveform signal defined by the waveform data set). From this memory location, the sequentially following locations store the coded waveform data for the remaining waveform steps in the waveform data set. The last memory location in the sequence stores an end (or stop) code indicating that the end of the waveform data set has been reached. The coded waveform data for the read waveform data set is then selectively loaded in the buffer memory areas256a, . . . ,256ndependent on asserted bits of the destination mask signal. The process is repeated as necessary to load a waveform data set in each buffer256.

Reference is made toFIG.5Bwhich shows a block diagram for another embodiment of a transmitter of an ultrasound imaging system200. A plurality of transducer elements212generate acoustic signals in response to corresponding waveform signals216a, . . . ,216n. The waveform signals216a, . . . ,216nmay all be identical to each other, or all may be different from each other, or some plural number of waveform signals may be the same and others different. The waveform signals216a, . . . ,216nare generated by a waveform generator and supplied to the high voltage analog pulse driver (D) circuits220coupled to transducer elements212that perform signal level shifting operations on the received waveform signal216. Each pair of an analog pulse driver circuit220and transducer212forms a signal channel225for a waveform signal216.

The waveform generator includes a memory circuit202and a beamforming circuit204. The memory circuit202includes a shared delay set and waveform area230′ that stores waveform data sets (WDS), wherein each waveform data set comprises a sequence of coded waveform values specifying the waveform step states, representing the shapes of various waveform signals216. The shared delay set and waveform area230′ of the memory circuit202further stores delay data sets (DDS), wherein each delay data set includes digital delay values specifying the signal delays to be applied at the waveform signal channels225a, . . . ,225n, representing various delay profiles for the generation of the waveform signals216a, . . . ,216n. The memory circuit202still further includes an active area234which stores the waveform data sets for the waveform signal channels225a, . . . ,225nrepresenting the shapes of the waveform signals16a, . . . ,16nthat have been selected to be generated in order to produce a desired acoustic signal output.

The memory circuit202may be implemented as any suitable memory circuit such as a random access memory (RAM) and can be arranged in a plurality of memory column (or memory block) areas238a, . . . ,238ncorresponding to the plurality of channels225a, . . . ,225n. Each memory column area238includes N memory rows (for example, N=256). The first X rows (i.e., rows 0 to X−1) in each column area238are a part of the active area234, the next Y rows (i.e., rows X to N−1) are a part of the shared delay set and waveform area230′.

A delay pointer240of the memory circuit202is used to selectively point to a sequence of memory locations in the shared delay set and waveform area230′ to read one of the stored delay data sets (DDS) from the memory202which provides the digital delay values for a desired delay profile to be applied in the generation of the waveform signals216a, . . . ,216nfor the corresponding waveform signal channels225a, . . . ,225n. For example, the value of the delay pointer may specify a starting location at a certain row in a certain one of column areas238a, . . . ,238nfor a sequence of memory locations in the shared delay set and waveform area230′ where the digital delay values of a selected delay data set are stored.

Reading from the starting location identified by the address loaded in the delay pointer240, the digital delay values of the read delay data set242are then loaded in the delay registers244of the beamforming circuit204. It is important to note that the delay data set for the desired one of delay profiles can be stored in any of the column areas238a, . . . ,238nof the shared delay set and waveform area230′. In other words, due to the shared nature of the shared delay set and waveform area230′, the delay data set stored in a given one of the column areas238is not linked to the corresponding signal channel225. As an example, the sequence of memory locations in the shared delay set and waveform area230′ for a given delay data set may comprise n memory locations, wherein each of the n memory locations stores a digital delay value specifying a timing delay for starting generation of the corresponding one of the n waveform signals216. The delay registers244store the digital delay values and the beamforming circuit204includes a comparison circuit110that operates to compare an incrementing counter value (generated by a counter circuit104) to each of the register stored delay values for the purpose of triggering waveform signal216generation (see,FIG.3, signals112a-112n).FIG.5Bspecifically illustrates, by example, the pointing of the delay pointer240to a sequence of memory locations246in column area238dstoring the digital delay values for a certain delay data set DDS to produce the read digital delay set242for storage in the delay registers244.

A signal pointer250of the memory circuit202is used to selectively point to a sequence of memory locations in the shared delay set and waveform area230′ to read one of the stored waveform data sets (WDS) from the memory which provides the sequence of coded waveform values specifying shape of a desired one of the waveform signals216to be generated. For example, the value of the signal pointer may specify a starting location at a certain row in a certain one of column areas238a, . . . ,238nfor a sequence of memory locations the shared delay set and waveform area230′ where the sequence of coded waveform values for a selected waveform data set is stored.

Reading from the starting location identified by the address loaded in the signal pointer250, the sequence of coded waveform values for the selected waveform data set252are then processed through a mask vector circuit254and selectively loaded into one of more of the buffer memory areas256a, . . . ,256n(within column areas238a, . . . ,238n, respectively) of the active area234. The mask vector circuit254receives a destination mask signal that specifically identifies which one or ones of the buffer memory areas256are to be loaded with the read waveform data set252. The destination mask signal may, for example, comprise an n-bit digital signal wherein a logic high value at a given bit location in the signal specifies that the read waveform data set252is to be stored in the buffer memory area256corresponding to that bit location. It is important to note that the waveform data set for the desired waveform signal shape can be stored in any of the column areas238a, . . . ,238nof the shared delay set and waveform area230′. In other words, due to the shared nature of the shared delay set and waveform area230′, the waveform data set stored in a given one of the column areas238is not linked to the corresponding signal channel, and may indeed be used by the beamforming circuit in connection with generating the waveform signal for any signal channel (subject to selection made by the vector mask circuit). As an example, the sequence of memory locations in the shared delay set and waveform area230′ may comprise p memory locations, wherein the sequence of p memory locations stores the coded waveform values for the waveform data set defining one or more waveform steps of the desired waveform signal216. A decoder and signal driver circuit124for each waveform signal channel225applies an address pointer signal126to sequentially point to addressable data locations in the buffer memory area256that store the waveform data set for the desired waveform signal. The coded waveform values stored at the addressed data locations are sequentially read from the buffer memory area256and output as a code sequence signal128. Each coded waveform value in the code sequence signal128is decoded by a decoding function of the decoder and signal driver circuit124to determine an analog signal level for the corresponding waveform step. A signal generating function of the decoder and signal driver circuit124then generates the waveform signal216to include the determined analog signal level for each waveform step. The generated waveform signal216is supplied to the high voltage analog pulse driver circuit220to be level shifted in connection with driving the associated transducer212.

FIG.5Bspecifically illustrates, by example, the pointing of the signal pointer250to a sequence of memory locations260in column area238estoring coded waveform values for the waveform data set WDS of a desired waveform signal. In this example, the destination mask signal has a value of <10010 . . . 01>. In this example, the n-bit destination mask signal has a value of <10010 . . . 01>. The logic “1” data bits in the destination mask signal indicate that read waveform data set252is to be selectively stored by the mask vector circuit254in the buffer memory areas256a,256dand256n(of corresponding column areas238a,238d, and238n). The logic “0” data bits in the n-bit destination mask signal indicate that the read waveform data set252is blocked by the mask vector circuit254from being loaded in the buffer memory areas of the corresponding column areas. The coded waveform values of this waveform data set WDS are then processed by the decoder and signal driver circuits124to generate the waveform signals216a,216dand216nfor channels225a,225d, and225n.FIG.5Afurther illustrates, by example, the pointing of the signal pointer250to a sequence of memory locations261in column area238nstoring coded waveform values for another waveform data set WDS' of a desired waveform signal. In this example, the n-bit destination mask signal has a value of <01101 . . . 10>. The logic “1” data bits in the destination mask signal indicate that read waveform data set252is to be selectively stored by the mask vector circuit254in the buffer memory areas256b,256c,256eand256m(of corresponding column areas238b,238c,238eand238m). The logic “0” data bits in the n-bit destination mask signal indicate that the read waveform data set252is blocked by the mask vector circuit254from being loaded in the buffer memory areas of the corresponding column areas. The coded waveform values of this another waveform data set WDS' are then processed by the decoder and signal driver circuits124to generate the waveform signals216b,216c216eand216mfor channels225b,225c,225eand225m.

From the foregoing, it will be noted that the process for reading a waveform data set from the shared delay set and waveform area230′ using the signal pointer250can be repeated as many times as necessary to selectively load through the mask vector circuit254a sequence of coded waveform values in each of the buffer memory areas256a, . . . ,256n.

A control circuit270generates a load command signal272that is applied to the memory202. Responsive to this load command signal272, the memory202is configured to use the delay pointer240to retrieve the desired one delay profiles stored in the shared delay set and waveform area230′ for loading in the delay registers244of the beamforming circuit204. Further responsive to this load command signal272, the memory202is configured to use the signal pointer250to retrieve the coded waveform data for the waveform data sets WDS of one or more desired waveform signals for loading in the buffer memory areas256a, . . . ,256n. The control circuit270further generates a counter start command signal274that is applied to the counter circuit104in the beamformer circuit204. Responsive to this counter start command signal274, incrementing of the counter104is initiated. When the comparison circuit110determines that the incrementing count value matches any of the digital delay values stored in the delay registers244, the start transmission signal112is pulsed and the corresponding decoder and signal driver circuit124retrieves the coded waveform data for the waveform data set WDS from buffer memory area256to generate the waveform signal216. The control circuit270still further generates the destination mask signal to control the mask vector254operation for selectively loading coded waveform data in the buffer memory areas256a, . . . ,256n.

It will be noted that in the embodiment ofFIG.5B, the memory resources of memory circuit202are separated into two general types: a) a shared memory and delay set area230′ where waveform data sets and delay data sets are stored; and b) an active memory area234that provides an output buffer256dedicated to each channel225in order to support independent waveform signal generation with a configured timing delay. There is no need to specify a fixed boundary between the two types. Rather, the user can configure the memory circuit202, and in particular the size of each of the shared memory and delay set area230′ and the active memory area234as necessary in order to store the desired number of waveform data sets and delay data sets. Separation between the shared memory and delay set area230′ and the active memory area234is logical (or functional) only, not necessarily physical. So, it will be understood that the boundaries between the areas230′,234are flexible. The actual addresses occupied by each type of data are simply defined by the user. The only limitation that is imposed is given by the actual physical memory size.

Operation of the memory for loading the desired waveform data set(s) and desired delay data set is efficient. Turning first to the loading of the desired delay data set, the delay pointer240is used to point to a starting location anywhere in the shared memory and delay set area230′ to select a memory row within a column area238that stores the digital delay data (of the desired delay profile defined by the delay data set) for the first signal channel225. From this memory location, the next n−1 sequential locations store the digital delay data for the remaining signal channels225. The read digital delay data values are loaded in the delay registers244and are ready to be used to manage individual signal delays in connection with generating the waveform signals216a, . . . ,216n. Turning next to the loading of the desired waveform data set(s), the signal pointer250is used to point to a starting location anywhere in the shared memory and delay set area230′ to select a memory row within a column area238that stores the coded waveform data for a first waveform step (of the desired waveform signal defined by the waveform data set). From this memory location, the sequentially following locations store the coded waveform data for the remaining waveform steps in the waveform data set. The last memory location in the sequence stores an end (or stop) code indicating that the end of the waveform data set has been reached. The coded waveform data for the read waveform data set is then selectively loaded in the buffer memory areas256a, . . . ,256ndependent on asserted bits of the destination mask signal. The process is repeated as necessary to load a waveform data set in each buffer256.

Reference is now made toFIG.6A. Like references inFIGS.5A and6Arefer to same components and functionality whose description will not be repeated. The implementation ofFIG.6Adiffers from the implementation ofFIG.5Ain the support of an auto-loading functionality for either or both the delay pointer240and the signal pointer250.

Turning first to auto-loading for the delay pointer240, a delay data set (DDS) stored in the memory202provides the digital delay values for a desired delay profile to be applied in the generation of the waveform signals216a, . . . ,216nfor the corresponding waveform signal channels225a, . . . ,225nalong with an end value specifying a next delay pointer address for accessing the next delay data set. This is shown by the following:

Here, the entries for Delay a through Delay n in the delay data set specify the digital delay values for a delay profile to be applied to the corresponding waveform signals216a, . . . ,216nof a given acoustic signal transmission. The last entry in the delay data set includes an end tag (End) along with an address value (Addr). This address value Addr specifies a starting location at a certain row in a certain one of column areas238a, . . . ,238nfor a sequence of memory locations in the shared delay set area232where the digital delay values of a next delay data set are stored.

The delay pointer240is loaded with the address pointing to the starting location of the selected delay data set. Reading from the starting location, the digital delay values Delay a, . . . , Delay n of the read delay data set242are then loaded in delay registers244a, . . . ,244n, respectively, of the beamforming circuit204. Then the last entry in the delay data set including the end tag (End) is read. In response to reading the end tag, the address value (Addr) is extracted and loaded into a next delay pointer (Next DP) register. Following transmission of the acoustic signal using the waveform signals216a, . . . ,216ndelayed in accordance with the delay profile specified by the selected delay data set, the address value (Addr) in the Next DP register is then automatically loaded into the delay pointer240, with this address value pointing to the starting location of the next selected delay data set. Reading from that starting location, the digital delay values of another read delay data set242are then loaded in delay registers244a, . . . ,244n. Transmission of the acoustic signal using the waveform signals216a, . . . ,216ndelayed in accordance with the delay profile specified by the next selected delay data set is then made. It will be noted that this automatic delay profile loading functionality provides an added level of efficiency to signal generation in that there is no need for the user to specifically enter a new delay pointer value just before each signal transmission. Instead, by selecting a delay data set that includes the end tag with a preloaded address value (Addr), there will be an automatic loading of the next delay data set dependent on the previous delay data set.

Turning next to auto-loading for the signal pointer250, a waveform data set (WDS) stored in the memory202provides the sequence of coded waveform values specifying the shape of a desired one of the waveform signals216to be generated along with an end value specifying a next signal pointer address for accessing the next waveform data set. This is shown by the following:

Here, the code entries (HV+, HV−, CLP) specify signal states (levels) for a sequence of waveform steps of the waveform signal shown inFIG.2. The last entry in the waveform data set includes an end tag (End) along with an address value (Addr). This address value Addr specifies a starting location at a certain row in a certain one of column areas238a, . . . ,238nfor a sequence of memory locations in the shared waveform area230where the sequence of coded waveform values of a next waveform data set are stored.

The signal pointer250is loaded with the address pointing to the starting location of the selected waveform data set. Reading from the starting location, the coded waveform values Code CLP, Code HV+, . . . , Code CLP of the read waveform data set252are then selectively loaded in the buffer memory areas256a, . . . ,256n. It will be noted that this loading operation can be, as described above, made subject to the logic state of the bits of the mask vector signal. Then the last entry in the waveform data set including the end tag (End) is read. In response to reading the end tag, the address value (Addr) is extracted and loaded into a next signal pointer (Next SP) register. Following transmission of the acoustic signal using waveform signals216a, . . . ,216nwhose shapes are specified by the waveform data set(s), the address value (Addr) is then automatically loaded into the signal pointer250, with this address value pointing to the starting location of the next selected waveform data set. Reading from that starting location, the coded waveform values of another waveform data set252are then selectively loaded in the buffer memory areas256a, . . . ,256n. Again, this load can be made subject to the to the logic state of the bits of the mask vector signal. Transmission of the acoustic signal using the waveform signals216a, . . . ,216nhaving shapes are specified by the next waveform data set(s) is then made. It will be noted that this automatic waveform data set loading functionality provides an added level of efficiency to signal generation in that there is no need for the user to specifically enter a new signal pointer value just before each signal transmission. Instead, by selecting a waveform data set that includes the end tag with a preloaded address value (Addr), there will be an automatic loading of the next waveform data set dependent on the previous waveform data set.

Reference is now made toFIG.6B. Like references inFIGS.5B and6Brefer to same components and functionality whose description will not be repeated. The implementation ofFIG.6Bdiffers from the implementation ofFIG.5Bin the support of an auto-loading functionality for either or both the delay pointer240and the signal pointer250. This functionality operates in a manner like that described above in connection withFIGS.5A and6Aexcept that memory access is made to the memory area230′ as opposed to the memory areas230and232.

FIGS.7A-7Fillustrate a flow of processing steps for an example implementation of the auto-loading functionality for the delay pointer240. In this example, a simplification is shown using only three channels225, and three delay registers244a,244b, and244c. It will, however, be understood that no correlation between the number n of delayed data sets DDSn and the number of channels25is imposed. The shared delay set area232stores three delay data sets DDS1, DDS2, and DDS3. Each delay data set includes three digital delay values specifying the signal delays to be applied at the waveform signal channels225representing various delay profiles for the generation of the waveform signals216. Each delay data set DDS further includes a last entry with an end tag (End). The end tag End of the delay data set DDS1further includes an address Addr for the delay data set DDS3, and the end tag End of the delay data set DDS2further includes an address Addr for the delay data set DDS1.

As a starting condition,FIG.7Ashows that the delay pointer240is loaded with the address in the shared delay set area232of the delay data set DDS2. Responsive thereto,FIG.7Bshows that the delay values Delay4, Delay5, and Delay6of the delay data set DDS2are read from the shared delay set area232and loaded into the delay registers244a,244b, and244c, respectively. Also, the end tag End of the delay data set DDS2is read, and the Addr for the delay data set DDS1is loaded in the Next DP register. A transmission of the waveform signals216is then made with the delay profile specified by the delay values Delay4, Delay5, and Delay6. For the following waveform signal216transmission, the Addr for the delay data set DDS1is automatically transferred inFIG.7Cfrom the Next DP register to the delay pointer240. Responsive thereto,FIG.7Dshows that the delay values Delay1, Delay2, and Delay3of the delay data set DDS1are read from the shared delay set area232and loaded into the delay registers244a,244b, and244c, respectively. Also, the end tag End of the delay data set DDS1is read, and the Addr for the delay data set DDS3is loaded in the Next DP register. A transmission of the waveform signals216is then made with the delay profile specified by the delay values Delay1, Delay2, and Delay3. Following waveform signal216transmission, the Addr for the delay data set DDS3is automatically transferred inFIG.7Efrom the Next DP register to the delay pointer240. Responsive thereto,FIG.7Fshows that the delay values Delay7, Delay8, and Delay9of the delay data set DDS3are read from the shared delay set area232and loaded into the delay registers244a,244b, and244c, respectively. A transmission of the waveform signals216is then made with the delay profile specified by the delay values Delay7, Delay8, and Delay9.

FIGS.8A-8Fillustrate a flow of processing steps for an example implementation of the auto-loading functionality for the signal pointer. In this example, a simplification is shown using only three channels225, and three buffer memory areas256a,256b, and256c. The shared waveform set area230stores three waveform data sets WDS1, WDS2, and WDS3. Each waveform data set includes a sequence of coded waveform values specifying the shape of a waveform signals216(these code sequences are illustrated pictorially to show the waveform shape). Each waveform data set WDS further includes a last entry with an end tag (End). The end tag End of the waveform data set WDS1further includes an address Addr for the waveform data set WDS3, and the end tag End of the waveform data set WDS2further includes an address Addr for the waveform data set WDS1.

As a starting condition,FIG.8Ashows the signal pointer250is loaded with the address in the shared waveform set area230of the waveform data set WDS2. Responsive thereto,FIG.8Bshows that the sequence of coded waveform values specifying the shape the waveform signal of the waveform data set WDS2are read from the shared waveform set area230and loaded into the buffer memory areas256a,256b, and256c. As previously discussed, this loading operation can be made subject to the mask vector signal. Also, the end tag End of the waveform data set WDS2is read, and the Addr for the waveform data set WDS1is loaded in the Next SP register. A transmission of the waveform signals216having the shape specified by the waveform data set WDS2is then made. It will be noted that the timing of transmission of these waveform signals may be made in accordance with the delay profile specified by the stored delay values in the delay registers244a,244b, and244c, respectively (see,FIG.7B). For the following waveform signal216transmission, the Addr for the waveform data set WDS1is automatically transferred inFIG.8Cfrom the Next SP register to the signal pointer250. Responsive thereto,FIG.8Dshows that the sequence of coded waveform values specifying the shape the waveform signal of the waveform data set WDS1are read from the shared waveform set area230and loaded into the buffer memory areas256a,256b, and256c. Again, this loading operation can be made subject to the mask vector signal. Also, the end tag End of the waveform data set WDS1is read, and the Addr for the waveform data set WDS3is loaded in the Next SP register. A transmission of the waveform signals216having the shape specified by the waveform data set WDS1is then made. It will be noted that the timing of transmission of these waveform signals may be made in accordance with the delay profile specified by the stored delay values in the delay registers244a,244b, and244c, respectively (see,FIG.7D). Following waveform signal216transmission, the Addr for the waveform data set WDS3is automatically transferred inFIG.8Efrom the Next SP register to the signal pointer250. Responsive thereto,FIG.8Fshows that the sequence of coded waveform values specifying the shape the waveform signal of the waveform data set WDS3are read from the shared waveform set area230and loaded into the buffer memory areas256a,256b, and256c. Again, this loading operation can be made subject to the mask vector signal. A transmission of the waveform signals216having the shape specified by the waveform data set WDS3is then made. It will be noted that the timing of transmission of these waveform signals may be made in accordance with the delay profile specified by the stored delay values in the delay registers244a,244b, and244c, respectively (see,FIG.7F).