Identifying faulty programmable interconnect resources of field programmable gate arrays

A method of identifying faulty programmable interconnect resources of a field programmable gate array (FPGA) may be carried out during manufacturing testing and/or during normal on-line operation. The FPGA resources are configured into a working area and a self-testing area. The working area maintains normal operation of the FPGA throughout on-line testing. Within the self-testing area, programmable interconnect resources of the FPGA are grouped and comparatively tested for faults. Upon the detection of one or more faults within a group of programmable interconnect resources, the group of resources is subdivided for further comparative testing in order to minimize a region of the group of resources including the fault for each fault. Once the region of the group of resources which includes the fault is minimized, the wires within the minimized region are comparatively tested in order to determine which wire includes the faulty resource or resources. Once the wire which includes the faulty resource is determined, a variety of testing configurations may be utilized to identify the faulty resource within the wire.

TECHNICAL FIELD

The present invention relates generally to the field of integrated circuit devices and, more particularly, to a method of identifying faulty programmable interconnect resources of field programmable gate arrays.

BACKGROUND OF THE INVENTION

A field programmable gate array (FPGA) is a type of integrated circuit consisting of an array of programmable logic blocks interconnected by a programmable interconnect network and programmable input/output cells. Programming of the logic blocks, the interconnect resources which make up the network, and the input/output cells is selectively completed to make the necessary interconnections that establish one configuration thereof to provide the desired system operation/function for a particular application.

The present inventors have recently developed off-line methods of built-in self-testing the array of programmable logic blocks and the programmable interconnect resources in FPGAs at the device, board and system levels. These methods are set out in detail in U.S. Pat. Nos. 5,991,907, 6,003,150, 6,108,806, and 6,202,182. The full disclosures in these patents are incorporated herein by reference.

In addition to these off-line testing methods, the present inventors have also recently developed methods of testing and fault tolerant operation of the programmable logic blocks and methods of testing the programmable interconnect resources during normal on-line operation of the FPGAs. These testing and operating methods are set out in detail in U.S. Pat. Nos. 6,256,758, 6,550,030, 6,631,487, 6,474,761, and 6,530,049. The full disclosures in these patents are also incorporated herein by reference.

On-line testing and fault tolerant operation of FPGAs is most important in high-reliability and high-availability applications, such as, long-life space missions, telecommunication network routers, or remote equipment in which adaptive computing systems often rely on reconfigurable hardware to adapt system operation to environment changes. In such applications, the FPGA hardware must work continuously and simply cannot be taken off-line for testing, maintenance, or repair.

When faults are detected in the programmable interconnect resources of the FPGA hardware of these systems, the faulty resources must be quickly identified in order to facilitate efficient reconfiguration of the remaining FPGA resources to avoid the faulty resources, or to reuse the faulty resources for fault-tolerant operation of the FPGA. Accordingly, a need is identified for an efficient and adaptive method of identifying faulty programmable interconnect resources which may be performed concurrently with normal system operation or during manufacturing testing.

SUMMARY OF THE INVENTION

In accordance with the present invention, a method of identifying faulty programmable interconnect resources of a field programmable gate array (FPGA) may be carried out during normal on-line operation and/or during manufacturing testing. The FPGA resources are configured into a working area and a self-testing area. The working area maintains normal operation of the FPGA throughout on-line testing. During manufacturing testing, the working area may be replaced with additional self-testing areas or the self-testing area extended to include the entire FPGA. Within the self-testing area, the programmable interconnect resources are tested for faults and faulty interconnect resources identified. It is initially presumed that all of the resources of the FPGA are fault-free as determined through manufacturing testing.

To test the programmable interconnect resources, test patterns are generated and applied to programmable interconnect resources selected for testing. Outputs of a first group of selected programmable interconnect resources, or wires under test, are preferably compared to outputs of a second group of wires under test. Based on a comparison of the outputs of the groups of wires under test, fault status data is generated.

The first and second groups of wires under test may be further compared to at least a third group of wires under test. Based on a comparison of the outputs of the first group of wires under test with the third group, for example, the presence of the at least one faulty resource within either the first or second group of wires under test may be determined. Whether or not the fault is identified within the first group of wires under test through comparison to the third group of wires under test, the second group of wires under test may also be compared to the third, or a different group of wires under test, to determine whether multiple faults are present, i.e., to insure that the second group of wires under test are fault-free.

Once a group of wires under test containing a faulty programmable interconnect resource is identified, the FPGA resources within the self-testing area of the FPGA under test may be reconfigured into subsequent groups of wires under test for further testing in order to minimize a region of the group of wires under test which includes the faulty interconnect resource. Specifically, the group of wires under test which includes the faulty interconnect resource may be subdivided and its interconnect resources grouped with additional known fault-free resources to form the subsequent groups of wires under test. The subsequent groups of wires under test may be further comparatively tested in the manner described above. These steps of testing and reconfiguring may be repeated until the region of the group of wires under test which includes the faulty interconnect resource is minimized.

Depending upon which interconnect resources are being tested, an alternate method of testing the programmable interconnect resources with the faulty group of wires under test (or a combination of the two methods) may be utilized to minimize the region of the group of wires under test which includes the faulty resource. Specifically, the FPGA resources within the self-testing area may be configured such that comparisons of the output patterns of regions of the groups of wires under test may be made at several locations along the groups of wires under test and fault status data for each region may be produced. In this manner, the region of the group of wires under test containing the faulty interconnect resource may be minimized without subdividing the group of wires under test as described above.

Once a region of the groups of wires is identified as including the faulty resource in the alternate method, the direction of propagation of the test patterns along the groups of wires under test may be reversed allowing the identified region of the group of wires to be further reduced, or a determination made that multiple interconnect resources may be faulty. If there are multiple faulty resources, the group of wires under test may then be subdivided and tested as described above in order to separate the multiple faulty resources for further testing. Once separated, the FPGA resources within the self-testing area may be reconfigured into subsequent groups of wires under test for further testing in order to isolate regions of the groups of wires under test which include the faulty interconnect resources in the manner described above.

Once the region from the group of wires under test containing a faulty programmable interconnect resource is minimized, the FPGA resources within the self-testing area of the FPGA under test may be reconfigured into subsequent groups of wires under test for further testing in order to identify which wire within the minimized region of the group of wires under test includes the faulty interconnect resource. Specifically, the wires of the region of the group of wires under test which includes the faulty interconnect resource may be subdivided and grouped with additional known fault-free resources to form the subsequent groups of wires under test. The subsequent groups of wires under test are further comparatively tested in the manner described above. These steps of testing and reconfiguring may be repeated until the wire within the minimized region of the group of wires under test includes the faulty interconnect resource is identified.

In accordance with the broad teachings of the present invention, the steps of minimizing a region of the group of wires under test and identifying which wire in the group of wires under test includes the faulty interconnect resource may be conducted in any order. For example, once a group of wires under test containing a faulty programmable interconnect resource is identified, the FPGA resources within the self-testing area of the FPGA under test may be reconfigured into subsequent groups of wires under test for further testing in order to identify which wire in the group of wires under test includes the faulty interconnect resource in the manner described above. Once the wire of the group of wires under test is identified, a region of the identified wire which includes the faulty interconnect resource may be minimized in the manner described above.

Once the region of the group of wires under test which includes the faulty interconnect resource is minimized and the wire within the group of wires identified, the FPGA resources within the self-testing area are again reconfigured to test the interconnect resources, i.e., the wire segments and/or configurable interconnect points, within the minimized region of the identified wire in order to identify the faulty interconnect resource or combination of resources. Specifically, portions of the faulty region of the identified wire are re-routed using known fault-free wires and/or configurable interconnect points to avoid suspect faulty wire segments or configurable interconnect points and further tested. These steps of re-routing and testing may be repeated until the faulty wire and/or configurable interconnect point is identified.

In accordance with another aspect of the present invention, the self-testing area of the FPGA under test may be reconfigured so that a portion of the working area becomes a subsequent self-testing area, and at least a portion of the initial self-testing area becomes a portion of the working area once testing of the resources in the self-testing area of the FPGA under test is completed and any faulty interconnect resource identified. In other words, the self-testing area may rove around the FPGA under test repeating the steps of testing, reconfiguring, and identifying faulty interconnect resources within the self-testing areas while normal operation of the FPGA under test continues within the working areas uninterrupted by the activities conducted within the roving self-testing area.

An apparatus for identifying faulty programmable interconnect resources of an FPGA under test during normal on-line operation includes a test and reconfiguration controller in communication with the FPGA under test for: (a) configuring the field programmable gate array into a self-testing area and a working area, the working area maintaining normal operation of the field programmable gate array; (b) initiating testing of groups of programmable interconnect resources located within the self-testing area for faults; (c) reconfiguring groups of resources determined to include a faulty resource for further testing in order to minimize a region of the group of resources which includes the faulty resource; (d) repeating the steps of testing and reconfiguring until the region of the group of resources which include the faulty resource is minimized; (e) reconfiguring the resources located within the minimized faulty region of the group of resources for further testing in order to identify the faulty resource by re-routing portions of the minimized faulty region to avoid suspect resources; and (f) repeating the steps of reconfiguring and further testing until the faulty resource is identified. The testing apparatus further includes a storage device or medium in communication with the test and reconfiguration controller for storing a plurality of test configurations, and usage and fault status data for each FPGA resource.

Reference will now be made in detail to the present preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

A typical field programmable gate array (FPGA) generally consists of a plurality of resources including an array of programmable logic blocks (PLBs) interconnected by a programmable interconnect network, and programmable input/output cells or boundary scan ports (most FPGAs feature a boundary-scan mechanism). Such structures are, for example, featured in Agere Systems' ORCA Series FPGAs, in the Xilinx VIRTEX Series FPGAs, and in the Altera FLEX 8000 logic devices. In accordance with a preferred embodiment of the present inventive method, programmable interconnect resources which make up the interconnect network of an FPGA under test10are tested for faults and faulty interconnect resources identified in an efficient and adaptive manner during normal on-line operation of the FPGA under test10.

As shown in schematic block diagram inFIG. 1, the present method of identifying faulty programmable interconnect resources is preferably controlled by a test and reconfiguration controller12. Most preferably, an external test and reconfiguration controller12is utilized because present commercially available FPGAs do not provide internal access to their configuration memory. Accordingly, a configuration decompiler tool of a type known in the art is utilized to determine the intended function or mode of operation of the FPGA resources. Alternatively, this information may be extracted from the design stage and made available to the controller12. It should be appreciated by those skilled in the art that any controller, e.g., internal or external to an FPGA, could be utilized with an FPGA that allows for internal access to its configuration memory and that a single test and reconfiguration controller is capable of controlling several FPGAs. For purposes of illustration of the present preferred embodiment of the invention, however, a one-to-one controller to FPGA ratio is utilized.

The preferred controller12may be implemented on a microprocessor in communication with a storage medium or memory14for storing the various FPGA operational and test configurations, as well as, fault status data for the FPGA resources, or a standard piece of test equipment. In operation, the controller12accesses the FPGA under test10using its boundary-scan interface in a known manner such that access is transparent to normal function of the FPGA10. Specifically, the controller12uses the boundary-scan interface to configure the FPGA resources for testing, to initiate testing of the FPGA resources, and to scan out the test results. As shown inFIG. 2, the FPGA under test10is initially configured by the controller12into a self-testing area16and a working area18. In accordance with an important aspect of the present invention, normal operation of the FPGA under test10is maintained within the working area18while the programmable interconnect resources are tested and faulty resources identified in the self-testing area16. During manufacturing testing, the working area may be replaced with additional self-testing areas or the self-testing area extended to include the entire FPGA.

Testing of the FPGA10is generally accomplished by configuring its resources within the self-testing area16to function as a test pattern generator (TPG)20and an output response analyzer (ORA)22, and as groups of interconnect resources or wires under test (WUTs)24as shown inFIG. 3. During testing, an exhaustive set of equivalent test patterns generated using the TPG20is applied to and propagated along the groups of WUTs24. Most preferably, the TPG20utilized to generate the exhaustive set of test patterns is configured as an n-bit counter. The groups of WUTs24may include wire segments26, configurable or configuration interconnect points (CIPs) (including cross point CIPs28for connecting wire segments located in disjoint planes and break-point CIPs29for connecting wire segments in the same plane), and programmable logic blocks (PLBs)30. Preferably the groups of WUTs24initially extend along the length of the self-testing area16.

Outputs of the groups of WUTs24are compared by the ORA22to determine whether a fault exists within either of the groups of WUTs24. A match/mismatch result of the comparison performed by the ORA22is communicated as a pass/fail result or fault status data through the boundary-scan interface of the FPGA under test to the controller12. The fault status data is stored in memory14and utilized by the controller12in reconfiguring the FPGA resources for further testing.

In order to minimize the number of reconfigurations required during testing and therefore the total testing time, the FPGA resources within the self-testing area16are preferably configured to include several testing regions19(Region1, Region2, . . . . Regionn) as shown inFIG. 4. Necessarily each tester19includes at least a TPG20, an ORA22, and two groups of WUTs24. Comparative testing of the interconnect resources within each tester19is conducted concurrently. The present preferred comparison-based on-line method of testing the programmable interconnect resources briefly described above including the fault model utilized and configuration of the self-testing area is described in detail for programmable interconnect resources in the above-referenced U.S. Pat. No. 6,574,761 and in C. StroudET AL., Built-In Self-Test of FPGA Interconnect, PROC. INTN'LTESTCONF., at 404–411, 1998 incorporated herein by reference. As indicated above, the present preferred method may target permanent faults that exist in a newly manufactured FPGA device or which appear during the lifetime of the FPGA under test.

In order to avoid potential problems caused by equivalent faults in the groups of WUTs being compared in each tester, the test patterns propagated along a first group of WUTs32are preferably compared to test patterns propagated along two different groups of WUTs. As shown inFIG. 5, for example, the test patterns propagated along a first group of WUTs32are compared to the test patterns propagated along a second group of WUTs33in the same tester34, and subsequently to test patterns propagated along a third group of WUTs35from a different tester37. In addition, the test patterns propagated along the second group of WUTs33are similarly compared to test patterns propagated along a third group of WUTs from a different tester, such as the third group of WUTs35from the tester37. Advantageously, these secondary comparisons substantially eliminate the potential problem of equivalent faults within the groups of WUTs and, in accordance with an important aspect of the present invention, provide an indication as to which of the first or second group of WUTs32or33within the tester34, or both, contain the faulty interconnect resource or resources.

When the fault status data indicates the detection of a fault in one of the testing regions19in the self-testing area16, roving of the self-testing area16is temporarily interrupted. In other words, the controller12stops or parks the self-testing area16over the testing region19suspected of containing the faulty interconnect resource. In this manner, the faulty interconnect resource may be identified while normal operation of the FPGA under test10continues in the working area18.

Once a group of WUTs32is identified as including a faulty programmable interconnect resource, the resources of the FPGA under test10within the self-testing area16are reconfigured for further testing in order to minimize a region of the group of WUTs32which includes the faulty interconnect resource. Preferably, the group of WUTs32containing the faulty resource is reconfigured into subsequent groups of WUTs32aand32bas shown inFIG. 6for further comparative testing. The subsequent groups of WUTs32a,32bare further tested in order to minimize a region of the group of WUTs32which includes the faulty interconnect resource. Specifically, the suspect group of WUTs32is subdivided and its interconnect resources grouped with additional know fault-free resources to form the two subsequent groups of WUTs32a,32b. The programmable interconnect resources in each subsequent group of WUTs32a,32bare independently comparatively tested in new testing regions35,36in the manner described above. Dependent upon the subsequent fault status data, the interconnect resources within one or both of the subsequent groups of WUTs32a,32bmay be further reconfigured or subdivided, and tested until the region (or regions in the case of multiple faults) of the group of WUTs32which includes the faulty programmable interconnect resource is minimized. In other words, the steps of testing and reconfiguring may be repeated until the region of the group of WUTs32which includes the faulty interconnect resource cannot be further subdivided.

Depending upon which interconnect resources are being tested, an alternate method of testing the programmable interconnect resources within the faulty group of wires under test (or a combination of the two methods) may be utilized to minimize the region of the group of wires under test which includes the faulty resource. As shown inFIG. 7, the FPGA resources within the self-testing area16may be configured such that comparisons of the output patterns of regions of the groups of wires under test37,38may be made by ORAs22at several locations along the groups of wires under test and fault status data for each region may be produced. In this manner, the region of the group of wires under test containing the faulty interconnect resource may be minimized without subdividing the group of wires under test as described above.

Once a region of the groups of wires is identified as including the faulty resource in the alternate method, the direction of propagation of the test patterns along the groups of wires under test37,38may be reversed allowing the identified region of the group of wires to be further reduced, or a determination made that multiple interconnect resources may be faulty. If there are multiple faulty resources, the group of wires under test37,38may then be subdivided and tested as described above in order to separate the multiple faulty resources for further testing. Once separated, the FPGA resources within the self-testing area16may be reconfigured into subsequent groups of wires under test for further testing in order to minimize regions of the groups of wires under test which include the faulty interconnect resources in the manner described above.

Once it becomes impractical to further subdivide the region of the group of WUTs32which includes the faulty interconnect resource, the resources of the FPGA under test10are again reconfigured in order to identify a wire32a1,32a2, . . .32anof the minimized region of the group of WUTs32a, for example, which includes the faulty interconnect resource. Specifically as shown inFIG. 8, the wires32a1,32a2, . . .32anof the suspect group of WUTs32aare grouped with additional known fault-free resources to form two subsequent groups of WUTs which are comparatively tested in new testing regions35a,35b, . . .35nin the manner described above. Dependent upon the subsequent fault status data, the wires32a1,32a2, . . .32anmay be further reconfigured and tested until the wire of the minimized region of the group of WUTs32awhich includes the faulty programmable interconnect resource is identified. In other words, the steps of testing and reconfiguring may be repeated until the wire (e.g.,32a1) of the minimized region of the group of WUTs32awhich includes the faulty interconnect resource is identified.

In accordance with the broad teachings of the present invention, the steps of minimizing a region of the group of wires under test and identifying which wire in the group of wires under test includes the faulty interconnect resource may be performed in any order. For example, once a group of wires under test containing a faulty programmable interconnect resource is identified, the FPGA resources within the self-testing area of the FPGA under test may be reconfigured into subsequent groups of wires under test for further testing in order to identify which wire in the group of wires under test includes the faulty interconnect resource in the manner described above. Once the wire of the group of wires under test is identified, a region of the identified wire which includes the faulty interconnect resource may be minimized in the manner described above.

Once the region of the WUTs is minimized and the wire identified, a variety of testing configurations may be adaptively utilized to identify the faulty interconnect resource within the faulty region of the wire. In order to more precisely identify which interconnect resource, i.e., which wire segment or configuration interconnect point (CIP), within the faulty region is faulty, further reconfiguration and comparative testing is required.

In accordance with the preferred embodiment of the present invention, the faulty region of the identified wire is compared to a second group of interconnect resources containing only known fault-free resources in the manner described above. As shown inFIG. 9, for example, the resources in the faulty region38may include wire segments42,44, and46and CIPs41,43,45, and47. The second group of interconnect resources39may include a single known fault-free wire40or a group or interconnect resources. In order to identify which interconnect resource within the faulty region38is faulty, additional known fault-free resources are combined with the resources in the faulty region38in order to circumvent one suspect resource at a time.

As shown inFIG. 10, for example, the additional fault-free resources49,50,51,52, and53may be utilized to re-route the resources within the faulty region38to avoid a selected suspect resource (e.g.,46) one at a time during testing. In other words, the additional fault-free resources49,50,51,52, and53are utilized to re-route the resources within the faulty region38such that the suspected faulty resource, i.e., wire segment46is removed from the faulty region38during the comparative testing. The steps of re-routing and testing are repeated until each interconnect resource in the faulty region38is removed from the faulty region38during testing.

Although a preferred method for identifying faulty interconnect resources is broadly set out above, it must be appreciated that the steps utilized to identify a faulty interconnect resource within a faulty region depend both on the type of fault, e.g., an open, a short, etc., and the type of interconnect resources included in the faulty region. The following example is provided to better illustrate this point and the present invention.

Before providing the noted example, however, it must first be understood that the definition of a wire segment varies dependent upon the type of fault associated therewith. A wire segment for an open fault is defined as a wire bounded by any two CIPs (including cross-point and breakpoint CIPs) with no other CIPs in between. A wire segment for a short fault, on the other hand, is defined as a wire(s) bounded by breakpoint CIPs.

Referring toFIG. 11, for example, wire segments are represented by numerals55,56, and57when the fault is an open fault. Wire segment55is bound by a breakpoint CIP58and a cross-point CIP59, wire segment56is bound by cross-point CIPs59and60, and wire segment57is bound by cross-point CIP60and breakpoint CIP61. The reason for this definition is that an open in any of these wire segments55,56, or57can be uniquely identified using the above-described re-routing steps. For example, assume that the bold solid line (or signal net) routed through cross-point CIP59, wire segment56, and cross-point CIP60represents a group of WUTs62in an FPGA under test. This group of WUTs may be used to test wire segment56for an open fault even though wire segments55,57,63, and64are connected to the same signal net62through cross-point CIPs59and60respectively. These wire segments55,57,63, and64connect the group of WUTs62to other wire segments in the interconnect network due to the function of the cross-point CIPs59and60which does not break continuity along horizontal and vertical wires like breakpoint CIPs. Similarly, wire segments55and57may be tested for an open fault by reconfiguring the interconnect resources and more specifically creating new groups of WUTs which include wire segments65,55, and64and63,57and66, respectively.

Further reconfigurations and testing may be utilized to identify the faulty interconnect resource, i.e., whether the open fault is in a wire segment or an adjacent CIP, in some scenarios depending upon where the open fault actually resides. If the open fault is in wire segment56which is positioned between two cross-point CIPs59and60, for example (shown inFIG. 11), further reconfiguration(s) and testing may identify that the CIPs are in working order and that the open fault resides in the wire segment56. If the open fault resides in one of the CIPs59or60as a stuck-open fault, then a determination of whether the open fault resides in the wire segment56or an adjacent CIP59or60cannot be made. Nevertheless, an open wire segment56and an adjacent stuck-open cross-point CIP59or60are equivalent faults making such a determination unnecessary. Similarly, if the fault status data indicates that the open fault is in wire segment55which is positioned between a breakpoint CIP58and a cross-point CIP59then a determination of whether the open fault resides in the wire segment55or adjacent breakpoint CIP58cannot be made. Again, however, an open wire segment55and an adjacent stuck open breakpoint CIP58are equivalent faults making such a determination unnecessary.

As indicated above, a wire segment for a short fault is defined to include a group of wire segments bounded by breakpoint CIPs. As shown inFIG. 11, the wire segment for a short fault includes wires55,56, and57. This is because a short fault, such as short67, between wires55and68affect wire segments55,56, and57which must therefore be treated as a single faulty segment. This is due in part to the fact that further reconfigurations and testing are generally ineffective to identify the faulty interconnect resource, i.e., whether the short is in a wire or a CIP. For example, when the fault status data indicates a short between two wires connected by a CIP, a determination as to whether a short fault between the wires exists or whether the CIP is stuck-closed cannot be made. Shorted wires which are not connected by a CIP, such as wires55and68inFIG. 11however, can be further diagnosed by seeing that each wire is fully functional while the other segment it is shorted to is unused. When both segments are being tested then the failure is visible and testing can determine that the fault is a short between these segments.

Upon the completion of testing of at least the interconnect resources of the FPGA within the initial self-testing area16and identifying the faulty interconnect resource(s), the FPGA under test10is reconfigured such that the functions of the PLBs forming a portion of the working area18are copied to the PLBs forming the initial self-testing area16and the programmable interconnect resources appropriately re-routed. Once completed, the copied portion of the working area becomes a subsequent self-testing area. Preferably, the initial self-testing area16is reconfigured as an adjacent portion of the working area, i.e., the programmed function of an adjacent portion of the working area is relocated or more specifically, copied to the initial self-testing area16, and the adjacent portion of the working area is reconfigured as the subsequent self-testing area. The present preferred method of roving the self-testing area16and reconfiguring the FPGA under test10is described in detail in the above-referenced U.S. application Ser. No. 09/405,958 and in M. ABRAMOVICI ET AL., Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications, PROC. INTN'LTESTCONF., pp. 973–982, 1999 incorporated herein by reference.

In accordance with the present inventive method, the programmable interconnect resources of subsequent self-testing areas are similarly tested and faulty resources identified, if required, as described above for the initial self-testing area16until each portion of the FPGA under test10is reconfigured as a subsequent self-testing area and at least its interconnect resources tested. In other words, the self-testing area may continuously rove around the FPGA under test10repeating the steps of configuring, testing, and identifying so long as the FPGA under test10is in operation. Advantageously, normal operation of the FPGA under test10continues uninterrupted by the testing conducted within the self-testing areas.

In summary, the method of identifying faulty programmable routing resources in field programmable gate arrays may be carried out during normal on-line operation of an FPGA under test and/or during manufacturing testing by configuring FPGA resources into a working area and a self-testing area. The working area maintains normal operation of the FPGA throughout testing. During manufacturing testing, the working area may be replaced with additional self-testing areas or the self-testing area extended to include the entire FPGA. Within the initial and subsequent self-testing areas, however, the FPGA interconnect resources are reconfigured as testing regions which include groups of wires under test. The groups of wires under test are comparatively tested to determine whether a fault exists within either of the groups of wires under test. The FPGA resources within the group of wires under test identified to include a faulty interconnect resource are reconfigured, or subdivided, into subsequent groups of wires under test for further testing in order to minimize a region of the group of wires under test which includes the faulty resource and to identify a wire within the minimized region which includes the faulty resource. The FPGA resources within the self-testing area are again reconfigured to test the interconnect resources, i.e., the wire segments and/or configurable interconnect points, within the minimized region of the identified wire in order to identify the faulty interconnect resource(s). Specifically, portions of the faulty region of the identified wire are re-routed using known fault-free wires, wire segments, and/or configurable interconnect points to avoid suspect faulty wire segments or configurable interconnect points and further tested. These steps of re-routing and testing are repeated until the faulty wire segment, configurable interconnect point, and/or combination thereof is identified. Advantageously, the working area is substantially unaffected by testing, and testing time constraints are reduced since normal operation continues in the working area.