SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

An electronic device comprises a substrate and a semiconductor component coupled to the substrate. The substrate may include a dielectric layer, a seed layer, a conductive pattern, and an external interconnect first structure coupled to the conductive pattern. The dielectric layer may include photo-definable dielectric material. The conductive pattern and the external interconnect first structure may include one or more electroplated conductive layers formed using the same seed layer of the substrate.

BACKGROUND

Present semiconductor packages and methods of forming semiconductor packages are inadequate, for example resulting in excess cost, decreased reliability, or package sizes that are too large. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such approaches with the present disclosure as set forth in the remainder of the present application with reference to the drawings.

SUMMARY

Various aspects of this disclosure relate to an electronic device having a photo-definable and/or low loss tangent dielectric layer and a seed layer from which multiple conductive structures (e.g., conductive pattern(s), conductive stud(s), etc.) are formed. Various aspects of this disclosure further relate to a system for manufacturing such electronic devices per a manufacturing method that forms the electronic devices from panels comprising multiple subpanels having multiple semiconductor components. The manufacturing method may include performing various operations on multiple subpanels and their respective semiconductor components while mounted to a carrier panel, and perform additional operations on a subpanel after it has been removed from the carrier panel. As such, aspects of the manufacturing method may be performed at a panel level and other aspects of the manufacturing method may be performed at a subsequent subpanel level.

DETAILED DESCRIPTION OF VARIOUS ASPECTS OF THE DISCLOSURE

The following discussion presents various aspects of the present disclosure by providing examples thereof. Such examples are non-limiting, and thus the scope of various aspects of the present disclosure should not necessarily be limited by any particular characteristics of the provided examples. In the following discussion, the phrases “for example,” “e.g.,” and “exemplary” are non-limiting and are generally synonymous with “by way of example and not limitation,” “for example and not limitation,” and the like.

The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “includes,” “comprising,” “including,” “has,” “have,” “having,” and the like when used in this specification, specify the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure. Similarly, various spatial terms, such as “upper,” “lower,” “lateral,” “side,” “top,” “bottom,” and the like, may be used in distinguishing one element from another element in a relative manner. It should be understood, however, that components may be oriented in different manners, for example a semiconductor component or package may be turned sideways so that its “top” surface is facing horizontally and its “lateral” or “side” surface is facing vertically, without departing from the teachings of the present disclosure.

Various aspects of the present disclosure are directed to semiconductor components and fabricating or manufacturing methods thereof, which may decrease the cost, increase the reliability, and/or increase the manufacturability of such semiconductor components.

FIG.1depicts an example electronic device100. As shown, the electronic device100may have a device top side100a, a device bottom side100bopposite the device top side100a, and a device lateral side100cbetween the device top side100aand the device bottom side100b. Further, the electronic device100may include a substrate110, a semiconductor component120, a component encapsulant130, and external interconnect second structures140that protrude from and/or are positioned along the device bottom side100b.

The substrate110may include a substrate top side110a, a substrate bottom side110bopposite the substrate top side110a, and a substrate lateral side110cbetween the substrate top side110aand the substrate bottom side110b. In general, the substrate110may provide a signal distribution structure that defines electrical paths between the substrate top side110aand the substrate bottom side110b.

To this end, the substrate110may include a first dielectric layer112, a seed layer113, a conductive pattern114, a substrate encapsulant116, and external interconnect first structures118. The first dielectric layer112may have a first dielectric layer top side112a, a first dielectric layer bottom side112bopposite the first dielectric layer top side112a, and a first dielectric layer lateral side112cbetween the first dielectric layer top side112aand the first dielectric layer bottom side112b. The first dielectric layer112may further include first dielectric layer apertures112dthat pass through the first dielectric layer112between the first dielectric layer top side112aand the first dielectric layer bottom side112b.

The seed layer113of the substrate110may cover the first dielectric layer bottom side112b. Moreover, the seed layer113may extend into the first dielectric layer apertures112d. In various implementations, the seed layer113conforms to or lines inner walls of the first dielectric layer apertures112d. Further, in various implementations, the seed layer113may extend through the first dielectric layer apertures112dto define upper portions that contact interconnection structures122of the semiconductor component120. Such upper portions of the seed layer113may be coplanar with the first dielectric layer top side112aas shown. In various implementations, the upper portions may protrude above the first dielectric layer top side112aor remain recessed below the first dielectric layer top side112a.

The seed layer113may comprise any of a variety of materials. For example, the seed layer113may comprise copper. Also for example, the seed layer113may comprise one or more layers of any of a variety of metals such as silver, gold, aluminum, tungsten, titanium, nickel, molybdenum, etc. The seed layer113may be formed utilizing any of a variety of techniques such as sputtering, physical vapor deposition (PVD) processes, chemical vapor deposition (CVD) processes, electroless plating, electrolytic plating, etc.

The conductive pattern or layer114of the substrate110may comprise conductive traces that cover a bottom side of the seed layer113. Moreover, the conductive pattern114may extend into the first dielectric layer apertures112dand fill the seed layer lined inner walls of the first dielectric layer apertures112d. The conductive pattern114may comprise any of a variety of materials such as copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc.

Similar to the seed layer113, the conductive pattern114may be formed utilizing any of a variety of techniques such as sputtering, physical vapor deposition (PVD) processes, chemical vapor deposition (CVD) processes, electroless plating, electrolytic plating, etc. However, in various implementations, the conductive pattern114may be grown or plated on the seed layer113via an electrolytic plating process, in which electrical current passes through the seed layer113.

The substrate encapsulant116may surround and contact the first dielectric layer bottom side112b, the first dielectric layer lateral side112c, a lateral side of the seed layer113, a bottom side of the conductive pattern114, a lateral side of the conductive pattern114, and lateral sides of the external interconnect first structures118. As shown, the substrate encapsulant116may also surround and contact lateral sides of each external interconnect second structure140. However, in various implementations, the external interconnect first structures118may protrude below the substrate encapsulant116. In various other implementations, bottom sides of the external interconnect first structures118may be coplanar with the substrate bottom side116b. In such implementations, the substrate encapsulant116may not surround or contact lateral sides of the external interconnect second structures140.

As shown, the substrate encapsulant116may have a substrate encapsulant top side116a, a substrate encapsulant bottom side116b, and a substrate encapsulant lateral side116c. In various implementations, the substrate encapsulant top side116aand the first dielectric layer top side112aare coplanar and may generally define the substrate top side110a. Further, the substrate encapsulant bottom side116band the substrate encapsulant lateral side116cmay generally define the substrate bottom side110band the substrate lateral side110c, respectively. Thus, as shown, a width of the substrate encapsulant116between opposite lateral sides116cmay be greater than a width of the first dielectric layer112between its corresponding lateral sides112c.

The substrate encapsulant116may comprise any of a variety of characteristics. For example, the substrate encapsulant116may comprise any of a variety of encapsulating or molding materials such as resin, polymer, polymer composite material, polymer with filler, epoxy resin, epoxy resin with filler, epoxy acrylate with filler, silicone resin, combinations thereof, equivalents thereof, etc. The substrate encapsulant116may be formed in any of a variety of manners such as compression molding, transfer molding, liquid encapsulant molding, vacuum laminating, paste printing, film assisted molding, film pressing, spin coating, spraying, etc.

The external interconnect first structures118may be coupled to the conductive pattern114. In particular, a top side of each external interconnect first structures118may be coupled to a bottom side of the conductive pattern114. Moreover, a bottom side of each external interconnect first structures118may be exposed at the substrate encapsulant bottom side116b. In various embodiments, the bottom side of the external interconnect first structures118may protrude below the substrate encapsulant bottom side116bor may be coplanar with the substrate encapsulant bottom side116b. However, as shown, the external interconnect first structures118may be recessed in the substrate encapsulant bottom side116bin various implementations.

Each external interconnect first structure118may comprise any of a variety of materials such as copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc. In various implementations, each external interconnect first structure118may comprise one or more electroplated conductive layers formed with the aid of the electroplating seed layer113. Such electroplated conductive layers may form a variety of structures. For example, the external interconnect first structures118may be implemented as conductive pillars, conductive studs, conductive pins, conductive vias, under bump metal, etc. Thus, in various implementations, the seed layer113may be used by electrolytic plating processes to not only form layer(s) of the conductive pattern114but also layer(s) of each external interconnect first structure118. Further, in various implementations, the external interconnect first structures118may comprise various non-electroplated conductive structures such as conductive pillars, conductive studs, conductive pins, conductive vias, under bump metal, conductive bumps, solder balls, solid core solder balls, and/or other conductive structures suitable for electrically coupling the semiconductor component120to external devices.

The semiconductor component120may have a component top side120a, a component bottom side120bopposite the component top side120a, and a component lateral side120cbetween the component top side120aand the component bottom side120b. The semiconductor component120may further include interconnection structures122such as contacts, dies pads, terminals, bumps, pillars, balls, etc. along the component bottom side120b. In various implementations, the interconnection structures122may protrude from the component bottom side120bsuch that bottom sides of the interconnections structures122are below the component bottom side120b. However, in other implementations, the bottom sides of the interconnections structures122may be coplanar with the component bottom side120bas shown inFIG.1or may be recessed such that the bottom sides of the interconnections structures122are above the component bottom side120b.

In various implementations, the semiconductor components120may include one or more electrical components such as semiconductor dies with integrated circuits, packaged semiconductor dies, active components, passive components, etc. As such, the interconnection structures122may be coupled to such electrical components and provide electrical connections to such electrical components that permit external devices to interact (e.g., send and/or receive signals) with electrical components via the interconnection structure122.

As shown, the interconnection structure122of the semiconductor component120may be electrically and physically coupled to the substrate top side110a. In particular, the interconnection structures122may be electrically coupled to the conductive pattern114via the seed layer113, and to the external interconnect first structure118via the conductive pattern114. As shown, external interconnect second structures140may be coupled to the external interconnect first structures118. As such, the substrate110may electrically couple one or more of the external interconnect second structures140to the semiconductor component120.

The external interconnect second structures140may comprise and/or be referred to as solder balls, solder coated metal core balls (e.g., solder coated copper core balls), pillars, bumps, and/or copper pillars with solder caps, and/or copper bumps with solder caps. The external interconnect second structures140may comprise tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn—Pb, Sn37-Pb, Sn95-Pb, Sn—Pb—Ag, Sn—Cu, Sn—Ag, Sn—Au, Sn—Bi, Sn—Ag—Cu and/or Sn—Ag—Cu—Bi. In some examples, the external interconnect second structures140may be provided through a reflow process after forming a solder-containing conductive material on the bottom side of the external interconnect first structures118by a ball drop process. The external interconnect second structures140may couple the semiconductor component120to an external device. In particular, the external interconnect second structures140may permit external components to send and/or receive signals with the semiconductor component120via the substrate110.

As shown, a width of the first dielectric layer112between its lateral sides112cmay be greater than a width of the semiconductor component120between its corresponding later sides120c. As such, one or more conductive traces of the conductive pattern114and/or one or more of the external interconnect first structures118may extend laterally outside the footprint of the semiconductor component120. As such, the substrate110may provide a signal distribution structure with a fan-out configuration. Namely, the external interconnect second structures140of the electronic device100have a greater footprint than the interconnection structures122of the semiconductor component120.

The component encapsulant130may have a component encapsulant top side130a, a component encapsulant bottom side130b, and a component encapsulant lateral side130c. As shown, the component encapsulant130may surround and contact the semiconductor component120and the substrate top side110a. In particular, the component encapsulant130may surround and contact the component top side120aand the component lateral side120c. However, in various implementations, the component encapsulant may further underfill the semiconductor component120and contact the component bottom side120band/or the interconnection structure122. Moreover, in some implementations, the component top side120amay be exposed at the electronic device top side100a. In such implementations, the components top side120aand component encapsulant top side130amay be coplanar and may generally define the electronic device top side100a.

The component encapsulant130may comprise any of a variety of characteristics. For example, the component encapsulant130may comprise any of a variety of encapsulating or molding materials such as resin, polymer, polymer composite material, polymer with filler, epoxy resin, epoxy resin with filler, epoxy acrylate with filler, silicone resin, combinations thereof, equivalents thereof, etc. The component encapsulant130may be formed in any of a variety of manners such as compression molding, transfer molding, liquid encapsulant molding, vacuum laminating, paste printing, film assisted molding, film pressing, spin coating, spraying, etc.

FIG.2shows a flow diagram of an example method200used by a manufacturing system to make the electronic device100. A manufacturing system may vary the order of operations depicted inFIG.2without departing from the scope of this disclosure. Moreover, a manufacturing system may eliminate one or more of the depicted operations and/or add one or more operations without departing from the scope of this disclosure.

A manufacturing system may initiate the method200in response to any of a variety of causes or conditions, non-limiting examples of which are provided herein. For example, the manufacturing system may automatically initiate the method200in response to one or more signals received from one or more upstream or downstream manufacturing stations, in response to a signal from a central manufacturing line controller, upon arrival of components or manufacturing materials utilized during performance of the method200, etc. Also, for example, the manufacturing system may initiate the method200in response to an operator command invoked by a user that requests a manufacturing station or other component of the manufacturing system to initiate the method200.

At210, the manufacturing system may receive a carrier panel, which may also be referred to herein as a panel or frame. The carrier panel may, for example, comprise a carrier panel to which a plurality of subpanels are to be mounted to form a hybrid panel.

The carrier panel may comprise a plurality of characteristics. For example, a carrier panel may have any of a variety of shapes. The carrier panel may, for example, be rectangular. The carrier panel may also, for example, be square, n-polygonal where n is an integer greater than 2, elliptical, circular, etc. The carrier top surface or bottom surface may be entirely planar, or the carrier top or bottom surface may have recesses or apertures (e.g., for the accommodation of subpanels).

The carrier panel may, for example, comprise any of a variety of materials. For example, the carrier panel may comprise metal (e.g., stainless steel, etc.). Also for example, the carrier panel may comprise glass (e.g., transparent glass, etc.). Additionally for example, the carrier panel may comprise ceramic. Further for example, the carrier panel may comprise semiconductor material (e.g., silicon, gallium arsenide, etc.). In an example implementation, the carrier panel may be formed of a material having a coefficient of thermal expansion (CTE) that is the same as or substantially the same as (e.g., within 5%, within 10%, within 25%, etc.) the CTE of subpanels that are to be mounted to the carrier panel (e.g., at240). In another example implementation, the carrier panel may be formed of a material having a CTE that is within 50% of the CTE of the subpanels that are to be mounted to the carrier panel.

The carrier panel may provide structural support throughout processing of the subpanels mounted or coupled thereto or processing of the carrier panel. For example, the carrier panel may be formed to withstand temperatures experienced during such processing. In various implementations, during the forming of various signal redistribution structures, the manufacturing system may subject the carrier panel to temperatures reaching or exceeding 230 degrees Celsius for two or three or more hours. As such, the carrier panel may be design to withstand such temperatures without compromising its basic function of providing support and stability during manufacturing. Also, the carrier panel may be designed to withstand chemical exposures experienced during such processing. In various implementations, during the forming of various signal redistribution structures or other processes, the manufacturing system may subject the carrier panel to various chemicals such as propylene glycol methyl ether acetate (PGMEA), tetramethylammonium hydroxide (TMAH), cyclopentanone, sulfuric acid, hydrofluoric acid (0.5%), etc. The carrier panel may therefore be designed to withstand such chemicals without compromising its basic function of providing support and stability during manufacturing.

The manufacturing system at215may prepare the received carrier panel for subsequent processing. For example, the manufacturing system may prepare the received carrier panel for the mounting of subpanels thereto, for manufacturing processes to which the carrier panel may be exposed, etc. To this end, the manufacturing system at215may clean the received carrier panel. The manufacturing system may further inspect the received carrier panel to verify that the carrier panel meets manufacturing tolerances such as size, flatness, planarity, thickness, coefficient of thermal expansion (CTE) requirements, aperture requirements, transparency requirements, etc. Additionally, the manufacturing system at215may comprise verifying that the carrier panel has not been damaged during shipping or during previous manufacturing operations such as when carrier panels are reused.

The manufacturing system at220may receive subpanels for mounting to the carrier panel. The term subpanel, as utilized herein, may refer to any of a variety of types of subpanels. For example, a subpanel may have any of a variety of shapes such as circular, rectangular, rectangular strip, square, n-polygonal with n being an integer greater than 2, elliptical, etc. A subpanel may comprise any of variety of forms. For example, a subpanel may comprise a semiconductor wafer such as a wafer of integrated circuits output from a wafer fab process; an interposer wafer with or without active or passive components integrated therein; a reconstituted wafer comprising a plurality of semiconductor components and/or a plurality of semiconductor dies that have been previously singulated that are now coupled to each other with a joining material such as an molding material, epoxy resign, encapsulant, etc. Additionally, a subpanel may comprise an interposer or a substrate such as a cored substrate or a coreless substrate. Such an interposer or substrate be bare or may comprise electronic components such as semiconductor components, active components, passive components, etc. attached thereto.

The manufacturing system at220may receive a semiconductor wafer from a wafer fabrication facility, from an upstream process, etc. The wafer may be circular having a diameter of 2″, 4″, 8″, 12″, 300 mm, etc. The wafer may comprise any of a variety of semiconductor materials such as Silicon (Si), Gallium Arsenide (GaAs), InP, etc. The wafer may comprise microelectromechanical machine system (MEMS) components.

In some example implementations, the manufacturing system at220may comprise receiving subpanels in the form of reconstituted subpanels. Such reconstituted subpanels may comprise circular wafers, rectangular subpanels, square subpanels, etc. Such a reconstituted subpanel may comprise any of a variety of dimensions. For example, the reconstituted subpanel may have a circular diameter or side length of 2″, 4″, 8″, 12″, 300 mm, etc. Moreover, the reconstituted subpanel may comprise any of a variety of thicknesses. For example, a subpanel may be less than 100 μm thick in order to provide a relatively thin and flexible subpanel or may be greater than 300 μm to provide a relatively thick and inflexible subpanel.

The manufacturing system at225may mount subpanels received at220to the carrier panel received at210and prepared at215. The manufacturing system at225may mount the subpanels to the carrier panel in any of a variety of manners, various non-limiting examples of which are provided herein. In various example implementation, the manufacturing system at225may mechanically clamp the subpanels to the carrier panel. For example, such mechanically clamping may comprise utilizing clips, magnets such as permanent magnets, etc. The manufacturing system at225may vacuum clamp the subpanels to the carrier panel.

For example, as shown atFIG.7A, the manufacturing system at225may form a panel700by mounting a first subpanel714aand a second subpanel714bto a carrier panel710. The first subpanel714aand the second subpanel714bmay be mounted to the carrier panel710via an adhesive material712. The first subpanel714amay comprise semiconductor components120(e.g., a semiconductor die, a packaged semiconductor die, etc.) and component encapsulant130. Similarly, the second subpanel714bmay comprise semiconductor components120surrounded by component encapsulant130.

As further shown, each semiconductor component120may include interconnection structures122such as contacts, dies pads, terminals, bumps, pillars, balls, etc. that are exposed at its front side. In some implementations, the interconnection structures122may protrude from the front side. In such implementations, the component encapsulant130may also extend over the front side of the semiconductor component120and/or may contact lateral sides of such protruding interconnection structures122.

At230, the manufacturing system may provide a patterned first dielectric layer112over the subpanels and carrier panel. For example, as shown inFIG.7B, the manufacturing system may provide and pattern a first dielectric layer112over a top side of the panel700. In particular, providing of the first dielectric layer112may include covering the front side of the semiconductor components120and a front side of the component encapsulant130for both subpanels714a,714band any exposed portions712eof the adhesive material712. Moreover, patterning of the first dielectric layer112may include forming apertures112dand singulation apertures112ethat pass between a first side112aand a second side112bof the first dielectric layer112. The apertures112d,112emay expose underlying structures such as front sides of the semiconductor components120and/or interconnection structures122of the semiconductor components120.

The manufacturing system at235may form a seed layer over the patterned first dielectric layer112. For example, as shown inFIG.7C, the manufacturing system may form an electroplating seed layer113over the panel700. In particular, the manufacturing system may form the electroplating seed layer113by depositing or otherwise forming the seed layer113on the patterned first dielectric layer112such that the seed layer113covers the top sides of the subpanels714a,714b, the lateral sides of the subpanels714a,714b, the top side of the carrier panel710between adjacent subpanels714a,714b, etc. The seed layer113may comprise any of a variety of materials. For example, the seed layer113may comprise copper. Also for example, the seed layer113may comprise one or more layers of any of a variety of metals such as silver, gold, aluminum, tungsten, titanium, nickel, molybdenum, etc. The seed layer113may be formed utilizing any of a variety of techniques such as sputtering, physical vapor deposition (PVD) processes, chemical vapor deposition (CVD) processes, electroless plating, electrolytic plating, etc. As addressed further below, the manufacturing system may use the seed layer113during one or more subsequent electroplating processes.

At240, the manufacturing system may provide a patterned second dielectric layer720over the seed layer113. For example, as shown inFIG.7D, the manufacturing system may provide the patterned second dielectric layer720over a top side of the seed layer113. In particular, providing of the second dielectric layer720may include covering the top side of the seed layer113including portions of the seed layer113over the interconnection structures122of the semiconductor components and portions of the seed layer113over portions712eof the adhesive material712. Moreover, patterning of second dielectric layer720may include forming apertures720dthat pass through the second dielectric layer720. The apertures720dmay expose underlying structures such as portions of the seed layer113over the interconnection structures122of the semiconductor components120and may define conductive traces or paths of a subsequently formed conductive pattern.

The manufacturing system at245may form a conductive pattern114comprising conductive traces defined by the patterned second dielectric layer720. As shown inFIG.7E, the manufacturing system may form a conductive pattern114over the seed layer113. The manufacturing system may electroplate the conductive pattern114on portions of the seed layer113exposed by apertures720dthrough the patterned second dielectric layer720. To this end, the manufacturing system may apply an electric current to the seed layer113and electroplate the conductive pattern114on the seed layer113. In some implementations, the manufacturing system may planarize the top sides of the conductive pattern114and the patterned second dielectric layer720before proceeding to250. In various implementations, the conductive pattern114is formed to be thicker than a typical redistribution layer thickness (RDL). For example, the conductive pattern114in various implementations can have a target thickness of 20-30 μm, whereas a typical RDL thickness is in the range of 2-10 μm. The thicker target thickness of the conductive pattern114may provide improved electrical characteristics and/or thermal dissipation, especially with regard to high frequency signals.

At250, the manufacturing system may provide a patterned third dielectric layer730over the conductive pattern114. As shown inFIG.7F, the manufacturing system may form a patterned third dielectric layer730over the conductive pattern114and exposed portions of the patterned second dielectric layer720. Providing of the third dielectric layer730may include covering the top side of the conductive pattern114and the top side of the patterned second dielectric layer720. Moreover, patterning of third dielectric layer730may include forming apertures730dthat pass through the third dielectric layer730. The apertures730dmay expose underlying structures such as portions of the conductive pattern114and may define sidewalls of a subsequently formed external interconnect first structures.

The manufacturing system at255may form external interconnect first structures118on exposed portions of the conductive pattern114. As shown inFIG.7G, the manufacturing system may form external interconnect first structures118on the conductive pattern114. In particular, the manufacturing system may form the external interconnect first structures118such that each external interconnect first structure118extends through an aperture730dof the patterned third dielectric layer730and contacts an exposed portion of the conductive pattern114. In some implementations, the manufacturing system may apply an electric current to the seed layer113in order to form one or more electroplated layers of the external interconnect first structures118. In this manner, the manufacturing system may reuse the seed layer113to form not only layer(s) of the conductive pattern114but also layer(s) of the external interconnect first structures118. In various implementations, the external interconnect first structures118may comprise any of a variety of materials such as copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc., but the scope of the present disclosure is not necessarily limited thereto. Moreover, in various implementations, the external interconnect first structures118may have a target thickness of 20-30 μm. In contrast, under bump metal (UBM) typically has a thickness of 5-10 μm. The greater thickness provided by the external interconnect first structure118may aid in physically separating the semiconductor component120from a printed circuit board (PCB) or other component to which the electronic device100is coupled via the external interconnect second structures140. As such, the external interconnect first structures117may provide a superior decoupling of the semiconductor component120from an external PCB in comparison to a UBM of typical thickness.

Per the method200, the manufacturing system may form a substrate110having only a single conductive pattern114. However, in other implementations, alternating layers of patterned dielectric layers and conductive patterns may be repeated so as to form a substrate having multiple layers of conductive patterns and their associated conductive traces. Moreover, the manufacturing system may form such additional conductive patterns by applying an electric current to seed layer113and electroplating such conductive patterns. Thus, the same seed layer113may be reused to form multiple layers of conductive patterns and/or external interconnect first structures.

Further, the manufacturing system per the method200provides three patterned dielectric layers112,720,730. The manufacturing system may provide the three patterned dielectric layers112,720,730via example processes described below. In at least one implementation, the first dielectric layer112is provided by a photo-definable dry film or photo-definable ABF build-up film and the dielectric layers720,730are provided by laminated photoresist. However, each dielectric layer112,720,730may be independently provided by any of the below processes. Thus, each dielectric layer112,720,730may be provided by a different one of the following processes, each dielectric layer112,720,730may be provided by a same one of the following processes, etc.

In some implementations, one or more of the dielectric layers112,720,730may be provided per a conventional photolithography processes. Such a photolithography process may provide a dielectric layer over lower layers of the substrate, form a patterned photoresist layer over the dielectric layer using a mask and radiation, transfer the pattern of the photoresist layer to the dielectric layer via etching or another process, and remove the patterned photoresist layer. The one or more of the dielectric layers112,720,730may comprise one or more layers of any of a variety of dielectric materials. For example, the dielectric layers112,720,730may include inorganic dielectric materials (e.g., Si3N4, SiO2, SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) or organic dielectric material (e.g., a polymer, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), a molding material, a phenolic resin, an epoxy, silicone, acrylate polymer, combinations thereof, equivalents thereof, etc.). In such implementation, the dielectric layers112,720,730may be provided using any one or more of a variety of processes (e.g., spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporating, etc.).

In various embodiments, one or more of dielectric layers112,720,730may be provided by a dry film or ABF film (hereafter “dry film”) of dielectric material. In particular, dry films are laminated rather than spin-coated and may provide a dielectric layer (e.g., dielectric layer112,720, or730) with a thickness having a target range of 20-30 μm. Conversely, liquid films formed, via one of the many above-noted processes (e.g., spin-coating), generally provide a dielectric layer (e.g., dielectric layer122,720, or730) having thickness in the range of 3-10 μm. Thus, the dry films may provide a dielectric layer that is 2 to 10 times thicker than that provided by the above-note processes.

In various implementations, the dry film is photo-definable and thus may be patterned via photolithography processes such as stepper photolithography processes and mask-less laser-direct imaging (LDI) processes. LDI processes generally provide a lower exposure dose than stepper processes. For example, in various implementations, the exposure dose for LDI dry films is in the range of 50-100mJ/cm2, whereas the exposure dose for stepper dry films is in the range of about 250-1000mJ/cm2.

Moreover, in certain implementations, the dry film comprises a low loss tangent dielectric material. Examples of such photo-definable and/or low loss tangent dielectric materials include photo imageable dielectric films (e.g., PVI-3 HR-200) from Taiyo Ink Mfg. Co., Ltd. Moreover, for purposes of the present disclosure, dielectric materials having a low loss tangent of 0.015 or less are considered low loss tangent dielectric materials. In various embodiments, the dielectric materials of the dry film have a loss tangent less than 0.015, less than 0.010, between 0.003 and 0.015, or between 0.003 and 0.010. Such a low tangent dielectric may improve signal integrity for high frequency applications.

The dry film may be laminated over exposed lower layers of the substrate110, a mask or reticle may be placed over the dry film, and radiation (e.g., ultra-violet light) may pass through openings in the mask or directly from a laser source. In some implementations, exposure of the dry film to the radiation hardens such exposed portions of the dry film. In other implementations, exposure of the dry film to the radiation breaks down or softens such exposed portions of the dry film. Regardless of whether the exposed portions or non-exposed portions are the softer portions of the dry film, the softened or non-hardened parts of the dry film may be removed via solvents and a pattern may be transferred to the dry film layer to form one or more of the patterned dielectric layers112,720,730. Thus, in various implementations, one or more of the dielectric layers112,720,730may be patterned without the aid of a separate photoresist layer between the mask and the dielectric layer112,720,730as is typical in conventional photolithography processes. As such, the manufacturing system of the present disclosure may eliminate steps of a conventional patterning process (e.g., patterning a photoresist layer and its subsequent removal) for forming one or more of the dielectric layers112,720,730.

As noted above, one or more of the dielectric layers112,720,730may be implemented using photo-definable dry film. However, in some implementations, one or more of the dielectric layers112,720,730may be formed using a dry film that is not photo-definable. In such implementations, the manufacturing process may laminate the dry film over lower layers of the substrate and then pattern the dry film using laser ablation, in which a laser is used to directly pattern or cut through the dry film.

Finally, one or more of the dielectric layers720,730may be implemented using a photoresist as the patterned dielectric layer itself. To this end, the manufacturing system may spin coat a photoresist layer over lower layers of the substrate and pattern the photoresist layer using a mask and exposing the photoresist to radiation through openings in the mask. In such implementations, the patterned photoresist layers itself is used as one or more of the patterned dielectric layers720,730without transferring the pattern of the photoresist layer to the dielectric layer via etching or another process, and subsequently removing the patterned photoresist layer.

Returning to the flow ofFIG.2, the manufacturing system at260may remove the patterned dielectric layers720,730and the exposed portions of the seed layer113. For example, as shown inFIG.7H, the manufacturing system may remove the dielectric layers720,730and the portions of the seed layer113exposed after removal of the dielectric layer720,730. To this end, the manufacturing system may strip the dielectric layers720,730from the subpanels714a,714bexposing portions of the seed layer113. As shown, the removal of the dielectric layer720may expose the singulation apertures112dand portions of the seed layer113in such singulation apertures112d. The manufacturing system may then etch away the exposed portions of the seed layer113including seed layer portions in the singulation apertures112d. As further shown, portions of the seed layer113between the patterned first dielectric layer112and the conductive pattern114may be retained.

The manufacturing system at265may transfer each subpanel to a respective carrier such that the manufacturing system may perform further operations at a subpanel level. First, the manufacturing system may remove each subpanel714a,714bfrom the carrier panel710. The manufacturing system may perform such removal in any of a variety of manners, various non-limiting examples of which are provided herein. For example, the manufacturing system may remove the subpanels714a,714bby a heating and pulling process in which the manufacturing system applies heat and pulls subpanels714a,714bfrom the carrier panel710and/or adhesive material712; by an illuminating and pulling process in which the manufacturing system illuminates the adhesive712through the carrier panel710to reduce its adhesive properties and pulls subpanels714a,714bfrom the carrier410and adhesive material412; and/or by applying a shear force, etc.

The manufacturing system may then attach each subpanel714a,714bto a respective carrier. For example,FIG.8Adepicts subpanel714aattached to carrier subpanel810via an adhesive material812. The carrier subpanel810and adhesive material812may share characteristics with any of the carriers and adhesive materials or the forming thereof discussed herein.

At270, the manufacturing system may provide semiconductor components of the subpanel with external interconnect second structures. For example, as shown inFIG.8A, the manufacturing system may provide each external interconnect first structure118with a corresponding external interconnect second structure140. To this end, the manufacturing system may attach or form solder balls, solder coated metal core balls (e.g., solder coated copper core balls), pillars, bumps, and/or copper pillars with solder caps, and/or copper bumps with solder caps on the external interconnect first structures118. In some implementations, the manufacturing system may provide the external interconnect second structures140through a reflow process after forming a solder-containing conductive material on the bottom side of each external interconnect first structures118by a ball drop process.

The manufacturing system at275may form a substrate encapsulant116. For example, as shown inFIG.8B, the manufacturing system may form the substrate encapsulant116over the conductive pattern114such that it surrounds and contacts the front sides and lateral sides of the conductive pattern114and the first dielectric layer112. As further shown, the substrate encapsulant116fills the singulation apertures112eand contacts a front side of the component encapsulant130. The substrate encapsulant116may comprise any of a variety of characteristics. For example, the substrate encapsulant116may comprise any of a variety of encapsulating or molding materials such as resin, polymer, polymer composite material, polymer with filler, epoxy resin, epoxy resin with filler, epoxy acrylate with filler, silicone resin, combinations thereof, equivalents thereof, etc. The manufacturing system may form substrate encapsulant116in any of a variety of manners such as compression molding, transfer molding, liquid encapsulant molding, vacuum laminating, paste printing, film assisted molding, film pressing, spin coating, spraying, etc. In various implementations, the manufacturing system may form the substrate encapsulant116using a film assisted molding that encapsulates lateral sides or portions thereof of the external interconnect second structures140.

At280, the manufacturing system may singulate the subpanels into electronic devices. As shown inFIG.8C, the manufacturing system may physically saw through the substrate encapsulant116and the component encapsulant130in order to singulate an electronic device100of the subpanel714afrom other electronic device(s)100of the subpanel714a. Such sawing or singulation may pass through singulation apertures112eof the first dielectric layer112. As such, the first dielectric layer112may be spared from some of the physical forces associated with the singulation process. Furthermore, the first dielectric layer lateral sides112cmay remain encapsulated in the substrate encapsulant116, thus further protecting the first dielectric layer112.

Per the above, the external interconnect second structures140are provided on the external interconnect first structures118inFIG.8Abefore encapsulating with component encapsulant130inFIG.8B. However, in some implementations, the substrate110and semiconductor components120may be encapsulated with the component encapsulant130prior to providing the external interconnect second structures140. In such implementations, a portion of a top side of the component encapsulant130may be removed through etching, grinding, etc. to expose top surfaces of the external interconnect first structures118. After exposing the external interconnect first structures118, the external interconnect second structures140may be provided on the exposed surfaces of the external interconnect first structures118.

As explained above, the manufacturing system at220may receive subpanels comprising reconstituted wafers. In various implementations, instead of receiving such subpanels at220, the manufacturing system may form subpanels of reconstituted wafers. To this end,FIGS.3A-3Edepict a face-down, a front-side-down, or active-side-down example method which the manufacturing system may use to form subpanels of reconstituted wafers. Similarly,FIGS.4A-4Fdepict a face-up, a front-side-up, or a active-side-up example method which the manufacturing system may use to form subpanels of reconstituted wafers.

As shown atFIG.3A, the manufacturing system may receive an example carrier310per the example method. The example carrier310may comprise any of a variety of characteristics. For example, the example carrier310may be circular, rectangular, shaped like the reconstituted subpanel to be formed thereon etc. Further, the example carrier310may be formed from a variety of materials such as glass, semiconductor material (e.g., silicon, etc.), metal (e.g., stainless steel, etc.), ceramic, etc.

As shown atFIG.3B, the manufacturing system may prepare the carrier310. Such preparing may be performed in any of a variety of manners, various non-limiting examples of which are provided herein. For example, the manufacturing system may clean the received carrier310, prepare the carrier310for the application of various materials thereon, etc. In particular, the manufacturing system may form an adhesive material312(e.g., a layer of adhesive material) on a top side of the carrier310. The adhesive material312may comprise any of a variety of characteristics, non-limiting examples of which are discussed herein. The adhesive material312may, for example, comprise a thermal-releasable adhesive, a light-releasable adhesive (e.g., UV-releasable, etc.), a die-attach film, etc. The manufacturing system may form the adhesive material312in any of a variety of manners, for example, printing; spraying; applying or laminating a preformed adhesive tape or film; spin-coating; vapor-depositing; etc. In general, the adhesive material312or the forming thereof may share characteristics with any of the adhesive materials or the forming thereof discussed herein.

The manufacturing system atFIG.3Cmay include mounting semiconductor dies, electrical circuits, MEMS circuits, etc. to the carrier310. Such mounting may be performed in any of a variety of manners, various non-limiting examples of which are provided herein. In particular, the manufacturing system may apply or adhere a plurality of semiconductor dies or semiconductor components314a,314b,314c, and314dto the carrier310via the adhesive material312. The example semiconductor dies314a-314dare shown mounted in a face-down configuration with the front sides of the semiconductor dies314a-314dor interconnection structures at the front sides of the semiconductor dies314a-314dfacing the adhesive material312and the carrier310. In some examples, the front sides of the semiconductor dies314a-314dmay comprise or be referred to as active sides or interconnect sides of the semiconductor dies314a-314d. In various implementations, a pick-and-place machine of the manufacturing system may place or press the example semiconductor dies314a-314donto the adhesive material312. In some implementations, interconnection structures315such as terminals, bond pads, pillars, posts, bumps, balls, etc. may protrude from front sides of the semiconductor dies314a-314dsuch that a gap is defined between the front sides of the semiconductor dies314a-314dand the adhesive material312. In some examples, interconnection structures315may be substantially coplanar with the front sides of the semiconductor dies314a-314d, or the front sides of semiconductor dies314a-314dmay contact the adhesive material312. In some examples, the interconnection structures315may be recessed into the front sides of the semiconductor dies314a-314dand may, but need not, contact the adhesive material312.

AtFIG.3D, the manufacturing system may encapsulate the mounted semiconductor dies314a-314d. Such encapsulating may be performed in any of a variety of manners, various non-limiting examples of which are provided herein. In particular, the manufacturing system may form an encapsulating material316around the semiconductor dies314a-314d. As shown, the encapsulating material316may surround and contact all sides of the dies314a-314d(e.g., top side, bottom side, and lateral sides), but the scope of this disclosure is not limited to such coverage. For example, the front sides of the semiconductor dies314a-314dmay be partially or entirely exposed from the encapsulating material316. In an example implementation, a front side of the encapsulating material316and respective front sides of the semiconductor dies314a-314dmay be coplanar or substantially coplanar (e.g., within a 5% height deviation from a reference plane at the bottom of the reconstituted subpanel, within a 10% height deviation from a reference plane at the bottom of the reconstituted subpanel, etc.). Further, a portion of the encapsulating material316may be below the semiconductor dies314a-314dsuch that the encapsulating material316laterally contacts and/or surrounds interconnection structures315of the semiconductor dies314a-314d. However, not all implementations necessarily include such a configuration. For example, the bottom sides of the semiconductor dies314a-314dmay be free of the encapsulating material316.

The encapsulant or encapsulating material316may comprise any of a variety of characteristics. For example, the encapsulating material316may comprise any of a variety of encapsulating or molding materials such as resin, polymer, polymer composite material, polymer with filler, epoxy resin, epoxy resin with filler, epoxy acrylate with filler, silicone resin, combinations thereof, equivalents thereof, etc. The manufacturing system may form the encapsulating material316in any of a variety of manners such as compression molding, transfer molding, liquid encapsulant molding, vacuum laminating, paste printing, film assisted molding, film pressing, spin coating, spraying, etc.

The manufacturing system atFIG.3Emay remove the carrier310and the adhesive material312. The manufacturing system may perform such removal in any of a variety of manners, various non-limiting examples of which are provided herein. As shown, the carrier310and/or adhesive material312may be temporary structures which the manufacturing system may remove by performing a grinding and/or etching process; by a heating and pulling process in which heat is applied and the carrier310and/or adhesive material312are pulled from the encapsulating material316and the semiconductor dies314a-314d; by an illuminating and pulling process in which the manufacturing system illuminates the adhesive material312through the carrier310to reduce its adhesive properties and pulls the carrier310and adhesive material312from the encapsulating material316and the semiconductor dies314a-314d; and/or by the manufacturing system applying a shear force, etc. As shown inFIG.3E, after the removal of the carrier310and adhesive material312, interconnection structures315such as terminals, bond pads, pillars, posts, bumps, balls, etc. at the bottom sides of the semiconductor dies314a-314dmay be exposed at a bottom surface of the encapsulating material316.

Referring now toFIGS.4A-4F, the example method for forming a subpanel comprising reconstituted wafer is explained. Per such method, the manufacturing system atFIG.4Amay receive an example carrier410. The manufacturing system may perform such receiving in any of a variety of manners, various non-limiting examples of which are provided herein. The example carrier410may comprise any of a variety of characteristics. For example, the example carrier410may be circular, rectangular, shaped like the reconstituted subpanel to be formed thereon, etc. The example carrier410may comprises a variety of materials such as glass, semiconductor material (e.g., silicon, etc.), metal (e.g., stainless steel, etc.), ceramic, etc.

AtFIG.4B, the manufacturing system may prepare the carrier410. The manufacturing system may perform such preparing in any of a variety of manners, various non-limiting examples of which are provided herein. For example, the manufacturing system may clean the received carrier410, prepare the carrier410for the application of various materials thereon, etc. In particular, as shown atFIG.4B, the manufacturing system may apply an adhesive material412(e.g., a layer of adhesive material) on a top side of the carrier410. The adhesive material412may comprise any of a variety of characteristics, non-limiting examples of which are discussed herein. The adhesive material412may, for example, comprise a thermal-releasable adhesive, a light-releasable adhesive (e.g., UV-releasable, etc.), a die-attach film, etc. The manufacturing system may form the adhesive material412in any of a variety of manners, for example, printing; spraying; applying or laminating a preformed adhesive tape or film; spin-coating; vapor-depositing; etc. The adhesive material412or the forming thereof may share characteristics with any of the adhesive materials or the forming thereof discussed herein.

The manufacturing system atFIG.4Cmay comprise mounting semiconductor dies, semiconductor components, electrical circuits, MEMS circuits, etc. to the carrier410. The manufacturing system may perform such mounting in any of a variety of manners, various non-limiting examples of which are provided herein. As shown atFIG.4C, the manufacturing system may apply or adhere a plurality of semiconductor dies or semiconductor components314a,314b,314c, and314dto the carrier410via the adhesive material412. In particular, the example semiconductor dies314a-314dmay be mounted in a face-up configuration with the front sides of the semiconductor dies314a-314dor interconnection structures formed on the semiconductor dies314a-314dfacing upward or away from the adhesive material412. A pick-and-place machine of the manufacturing system may place or press the example semiconductor dies314a-314donto the adhesive material412. In some examples, interconnection structures215such as terminals, bond pads, pillars, posts, bumps, balls, etc. may protrude from the front sides of the semiconductor dies314a-314d. In some examples, interconnection structures215may be substantially coplanar with the front sides of the semiconductor dies314a-314d. In some examples, the interconnection structures415may be recessed into the front sides of the semiconductor dies314a-314d.

The manufacturing system atFIG.4Dmay encapsulate the mounted semiconductor dies or semiconductor components314a-314d. The manufacturing system may perform such encapsulating in any of a variety of manners, various non-limiting examples of which are provided herein. As shown, the manufacturing system may form an encapsulating material416around the semiconductor dies314a-314d. In particular, the encapsulating material416may surround and/or contact lateral and front sides of the semiconductor dies314a-314d, but the scope of this disclosure is not necessarily limited to such coverage. For example, the front sides of the semiconductor dies314a-314dmay be entirely exposed from the encapsulating material416. In example implementations, a portion of the encapsulating material416may be above the semiconductor dies314a-314dand may laterally contact and/or surround interconnection structures415of the semiconductor dies314a-314d. However, not all implementations necessarily include such a configuration. In example implementations, the encapsulating material416, respective front sides of the semiconductor dies314a-314d, and/or interconnection structures415thereon may be coplanar or substantially coplanar (e.g., within a 5% height deviation from a reference plane at the bottom of the reconstituted subpanel, within a 10% height deviation from a reference plane at the bottom of the reconstituted subpanel, etc.).

The encapsulating material416may comprise any of a variety of characteristics. For example, the encapsulating material416may comprise any of a variety of encapsulating or molding materials such as resin, polymer, polymer composite material, polymer with filler, epoxy resin, epoxy resin with filler, epoxy acrylate with filler, silicone resin, combinations thereof, equivalents thereof, etc. The manufacturing system may form the encapsulating material416in any of a variety of manners such as compression molding, transfer molding, liquid encapsulant molding, vacuum laminating, paste printing, film assisted molding, film pressing, spin coating, spraying, etc.

As shown atFIG.4E, in various implementations, the manufacturing system may cover the front sides of the semiconductor dies314a-314dand/or interconnection structures415with the encapsulating material416. For such implementations, the manufacturing system may thin or planarize the encapsulating material416and/or interconnection structures415via grinding, etching, etc. to thin and expose the front sides of the semiconductor dies314a-314dor the top sides of interconnection structures415. In an example implementation, a top side of the encapsulating material416and respective front sides of the semiconductor dies314a-314dor interconnection structures415may be coplanar or substantially coplanar (e.g., within a 5% height deviation from a reference plane at the bottom of the reconstituted panel, within a 10% height deviation from a reference plane at the bottom of the reconstituted panel, etc.).

Note that the method ofFIGS.3A-3Emay further include a thinning or planarization process similar toFIG.4E. Such thinning or planarizing may thin or planarize the encapsulating material316atFIG.3Dand/or the front sides of the semiconductor dies314a-314datFIG.3E.

The manufacturing system atFIG.4Fmay remove the carrier410and/or the adhesive material412. The manufacturing system may perform such removal in any of a variety of manners, various non-limiting examples of which are provided herein. As shown, the carrier410and/or adhesive material412may be temporary structures which the manufacturing system may remove by performing a grinding and/or etching process; by a heating and pulling process in which the manufacturing system applies heat and pulls the carrier410and/or adhesive material412from the encapsulating material416and the semiconductor dies314a-314d; by an illuminating and pulling process in which the manufacturing system illuminates the adhesive material412through the carrier410to reduce its adhesive properties and pulls the carrier410and adhesive material412from the encapsulating material416and the semiconductor dies314a-314d; and/or by applying a shear force, etc.

As shown inFIG.4F, after the removal of the carrier410and adhesive material412, the back sides of the semiconductor dies314a-314dmay be exposed at a bottom surface of the encapsulating material416. In an example implementation, a bottom side of the encapsulating material416and respective back sides of the semiconductor dies314a-314dmay be coplanar or substantially coplanar (e.g., within a 5% height deviation from a reference plane at a top surface of the encapsulating material, within a 10% height deviation from a reference plane at a top surface of the encapsulating material, etc.).

As explained above with regard toFIG.2, the manufacturing system at225may mount subpanels to a carrier panel to form a panel upon which further operations are performed.FIGS.5A-5Fdepict various examples of subpanel, panel, and hybrid panel configurations, which the manufacturing system may utilize and/or form at225. Referring toFIG.5A, a perspective view of a panel510is provided. The panel510may include four circular subpanels515such as wafer subpanels, reconstituted wafer subpanels, etc. mounted to a square carrier panel512. Referring toFIG.5B, a perspective view of another example panel520is shown. The panel520may include sixteen circular subpanels525such as wafer subpanels, reconstituted wafer subpanels, etc. mounted to a square carrier panel522. A perspective view of another example panel530is shown inFIG.5C. The panel530may include eight circular subpanels535such as wafer subpanels, reconstituted wafer subpanels, etc. mounted to a rectangular and non-square panel532.

As discussed herein, the panels and their mounted subpanels may be square, rectangular, n-polygonal with n being an integer greater than two, etc. For example, a perspective view of such an example panel540is shown inFIG.5D. The panel540may include four square subpanels545mounted to a square carrier panel542. A perspective view of another example panel550is shown inFIG.5E. The panel550may include two rectangular (e.g., non-square, or strip) subpanels555mounted to a square carrier panel552. Referring toFIG.5F, a perspective view of another example panel560is shown. The panel560may include eight rectangular (or square) subpanels565mounted to a rectangular (e.g., non-square) carrier panel562.

As shown in the various panel examples510,520,530,540,550, and560, the subpanels may be arranged in a matrix (or row/column) configuration on the carrier panel. Such matrix configurations may include a same number of subpanels in the rows and columns, or may include a different number of subpanels in the rows and columns. In various implementations, panels may arrange subpanels in a non-matrix configuration. As such, the scope of this disclosure covers both matrix and non-matrix configurations. For example, subpanels may be arranged in a circular configuration, n-polygonal configuration with n being any integer greater than two, staggered configuration, etc.

Also, as shown in the various panel examples510,520,530,540,550, and560, the subpanels mounted to a particular carrier panel may all be identical or may be a same shape or size. The scope of this disclosure is not necessarily limited thereto. For example, subpanels of different shapes or sizes may be mounted to a same carrier panel. Also for example, subpanels of different types of dies (e.g., with the same or different size subpanel dimensions) may be mounted to a same carrier panel. Also, subpanels with different sizes or numbers of respective dies may be mounted to a same carrier panel.

Additionally, as shown in the various panel examples510,520,530,540,550, and560, the subpanels may be arranged on a carrier panel, such that the carrier panel extends laterally outward from the subpanels. For example, an outer perimeter region on the top side of the carrier panel may laterally surround the subpanels. Such an outer perimeter region on the top side of the carrier panel may be free of adhesive material. Such a configuration may be beneficial for a variety of reasons such as carrier panel handling, carrier panel securing, carrier panel alignment, inspection, processing uniformity, etc.

Again, as explained above with regard toFIG.2, the manufacturing system at225may mount subpanels to a carrier panel to form a panel upon which further operations are performed.FIGS.6A and6Bdepict aspects of such panel formation. As shown, an example carrier panel610may be provided. As discussed herein, the carrier panel610may comprise any of a variety of materials. For example, the carrier panel610may comprise metal (e.g., stainless steel, etc.), glass, ceramic, etc. In an example implementation, the carrier panel610may comprise glass through which light (e.g., UV radiation) may efficiently pass to a light-releasable adhesive thereon such as glass or other material having a high transmittance at the relevant wavelengths, above 80%, above 90%, etc. In another example implementation, the carrier panel610or any carrier panel discussed herein may comprise a metal or other conductive material through which thermal energy may efficiently pass to a thermal-releasable adhesive thereon.

Note that the example carrier panel610or any example carrier panel discussed herein may be formed of a material that has a same or substantially the same (e.g., within 5%, within 10%, etc.) coefficient of thermal expansion (CTE) as the subpanels to be mounted to the carrier panel610. Also for example, the example carrier panel610or any example carrier panel discussed herein may be formed of a material that has a CTE within 25% or 50% of the CTEs of the subpanels to be mounted to the carrier panel610.

PerFIGS.6A and6B, the manufacturing system at225may form an adhesive material or adhesive layer612on the carrier panel610. As discussed herein, the adhesive material612may comprise any of a variety of characteristics. For example, the adhesive material612may comprise a light-releasable adhesive, a thermal-releasable adhesive, a die-attach adhesive, a curable bonding agent, etc. As discussed herein, although the adhesive material612is shown covering an entire top side of the carrier panel610, such coverage is not required. For example, a perimeter region on the top side of the carrier panel610, or at one or more lateral or horizontal ends of the top side of the carrier panel610, may remain free of the adhesive material612. Such adhesive free regions may be beneficial for handling, securing, aligning, etc. the carrier panel610and/or subpanels.

The manufacturing system may form the adhesive material612in any of a variety of manners such as rolling on, printing, spraying one or multiple coats, applying or laminating a preformed adhesive tape or film, spin-coating, dipping, etc. In an example implementation, the adhesive material612is applied via a preformed adhesive sheet such as a tape or film that may be rolled on the top side of the carrier panel610.

PerFIGS.6A and6B, the manufacturing system may form the adhesive material612on the carrier panel610prior to placing the subpanels614a,614b,614c, and614don the carrier panel610. Alternatively, the manufacturing system may individually form adhesive material612on the back sides of the subpanels614a-614dinstead of, or in addition to, forming adhesive material612on the carrier panel610.

In the example shown inFIGS.6A and6B, after the adhesive material612is formed on the carrier panel610, the manufacturing system may place or press the subpanels614a-614don the adhesive material612, thus adhering the subpanels614a-614dto the carrier panel610. In various implementations, the manufacturing system may use vacuum lamination, clamping, or other force providing process to mount the subpanels614a-614dto the adhesive material612and carrier panel610.

As shown, the manufacturing system may mount the subpanels614a-614dface-up such that front or active sides of the subpanel semiconductor dies are facing upward and/or interconnection structures of the subpanel semiconductor dies are facing upward. In general, the manufacturing system may position a side (e.g., a front side, an active side, a back side, inactive side, or other side) of the subpanel on which further processing is to be performed, face upward from the carrier panel610.

In this example, the top side of the carrier panel610is entirely planar. However, the entire top side of the carrier panel610may not be planar in other implementations. For example, the carrier panel610may comprise apertures in or over which the subpanels614a-614dare placed. Such apertures may extend entirely or only partially through the carrier panel610. In some implementations, the carrier panel610may comprise cavities such as registration indentations, etc. in or over which the subpanels614a-614dare placed. Such cavities may extend entirely or only partially through the carrier panel610.

The discussion herein included numerous illustrative figures that showed various methods of manufacturing an electronic device, various apparatuses for performing such methods, and various electronic devices or portions thereof resulting from performing such methods. For illustrative clarity, such figures did not show all aspects of each of the example methods, apparatuses, or electronic devices. Any of the example methods, apparatuses, or electronic devices presented herein may share any or all characteristics with any or all of the other example methods, apparatuses, or electronic devices presented herein.

While the foregoing has been described with reference to certain aspects and examples, various changes may be made and equivalents may be substituted without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from its scope. Therefore, it is intended that the disclosure not be limited to the particular example(s) disclosed, but that the disclosure will include all examples falling within the scope of the appended claims.