Techniques for an inductor at a first level interface

Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

TECHNICAL FIELD

This document pertains generally, but not by way of limitation, to inductors, and more particularly, to an inductor formed at a first level interface of an integrated circuit.

BACKGROUND

Electronic circuit evolution continues to provide ever increasing functionality and speed from ever smaller systems. Such miniaturization pressures circuit designers to use less components, in smaller sizes, yet deliver the same or improved performance. Inductors have also been relegated to the same design constraints. However, in certain terms, better inductor characteristics typically require increase size in at least one dimension.

DETAILED DESCRIPTION

The present inventors have recognized alternative techniques that can provide an inductor with increased z-axis form factor yet not increase the form factor of stacked integrated circuits connected at a first level interface. As used herein, a first level interface is an electrical and mechanical connection between a first semiconductor die and a second semiconductor chip, such as an interposer, a second die or a substrate of a package. It is anticipated that future integrated circuits may require significant power delivery improvements without increasing in size, especially in vertical height which may be referred to as a z-axis dimension or z-height. Magnetic inductor arrays can provide some improvement, but also require an external device that, in most cases, add to or will not satisfy future z-height requirements. Enabling magnetic materials on a coreless substrate may satisfy both future z-height requirements and performance, however, processes used to embed the magnetic components interact with wet chemistry processes such as, but not limited to, desmear, eless Cu, flash etch, soft etch, or surface finish. Magnetic materials can be exposed to the chemistry baths during processing and can result in premature corrosion, as well as, leaching of the magnetic materials into the baths. Such leaching can corrupt the bath resulting in shorter bath life and diminished chemistry performance, thus, adding additional costs to processing.

FIGS. 1A-1Cillustrate generally a perspective view of die package100including an inductor101formed at a first level interface according to various examples of the present subject matter. The die package100can include a first die111, a second die112, and interconnects102of the first level interface for electrically and mechanically connecting the first die111with the second die112. Each of the first die111and the second die112can include traces103embedded within, or located on a surface, of a semiconductor substrate of the respective die111,112. Each trace103can form a portion of an inductor coil. Upon connection of the first die111with the second die112, the respective traces103can from one or more coil loops of the inductor101. In certain examples, the inductor101does not include a magnetic core. In other examples, a magnetic material107can be applied to an external side of the substrate of either the first die111, the second die112, or a combination of the first die111and the second die112to provide a magnetic core inductor.FIG. 1Aillustrates general a perspective view of an example inductor101formed at a first level interface.FIG. 1Billustrate generally the example ofFIG. 1Awith dashed lines to show hidden features of the assembled first and second die111,112.FIG. 1Cillustrates generally the examples ofFIGS. 1A and 1Bwith the solder balls interconnects104drawn as lines.FIG. 1Cmore clearly illustrates the multiple coils formed when the first die111and the second die112are electrically connected.

Each of the first die111and the second die112include traces103that form the inductor101when the dies111,112are electrically connected together. The example ofFIGS. 1A-1Cshow the traces103on or at a surface of each respective die111,112that faces away from the center of the inductor103. Conductive through-silicon-vias (TSVs), or conductive vias105extending through the particular substrate material of each die111,112, can couple a trace103to a respective interconnect104or to an interconnect pad106used to electrically couple the first and second dies111,112together. In other examples, the traces103of each die can optionally be at or near the opposite surface of the respective die111,112, for example, the surface of the die facing the center of the inductor101and including the termination for the corresponding interconnect104. In certain examples, such as that shown inFIGS. 1A and 1B, the interconnects104between the first die111and the second die112can include solder balls. It is understood that other interconnects besides solder balls or bumps can be used without departing from the present subject matter, including, but not limited to, connection pins, microballs (μballs), alloy paste, Cn/Sn bumps, or other suitable interconnect structure for a first level interface.

FIG. 2Aillustrates generally top or bottom view of a first die211configured to form an inductor at a first level interface. The first die211can include a substrate220, and one or more traces203configured to form a portion of each coil of the inductor. In some examples, the traces203can be form on a surface of the first die211. In some examples, the traces203can be integrated with the semiconductor substrate220of the first die211. In certain examples, the first die211can optionally include vias205, extending through the substrate220, to connect a trace embedded within the substrate220, or on a first surface of the substrate220, with a termination on a second surface of the substrate220. In certain examples, two or more external terminations of the first die211can connect with external terminations of a second die212. In certain examples, the first die211can optionally include one or more terminations or one or more traces that couple the inductor to circuitry of the first die211.

FIG. 2Billustrates generally top or bottom view of a second die212configured to form an inductor at a first level interface when electrically and mechanically coupled with the first die211ofFIG. 2A. The second die212can include a substrate221, and one or more traces203configured to form a portion of each coil of the inductor. In some examples, the traces203can be located on a surface of the second die212. In some examples, the traces203can be integrated with the semiconductor substrate221of the second die212. In certain examples, the second die212can include vias205to connect a trace embedded within the substrate221, or on a first surface of the substrate221, with a termination on a second surface of the substrate221. In certain examples, two or more external terminations of the second die212can connect with external terminations of the first die211to form one or more coils of the inductor. In certain examples, the second die212can optionally include one or more terminations215or one or more traces that couple the inductor to circuitry of the second die.

In certain examples, the surface of one of the dies that faces the inside of the inductor coils can include a magnetic material such that the inductor includes a magnetic core. The magnetic material can be assembled to the surface the die after most, if not all, of the chemical processing of the die has been completed. As such, the magnetic material is not exposed to processing materials that can accelerate corrosion, and chemical baths used to process the die are not exposed to contamination from the magnetic material.

FIG. 3illustrates generally a flowchart of an example method300for manufacturing an inductor at a first level interface that does not increase the z-height of the stacked integrated circuit dies. At301, a first portion of an inductor coil can be fabricated at or on a first die. In certain examples, the first portion can include a conductive trace deposited on, grown on, or embedded within the substrate of the first die. In some examples, the first portion can include conductive vias to extend the trace to an external or internal termination of the first die.

At303, a second portion of the inductor coil can be fabricated at or on a second die. In certain examples, the second portion can include a conductive trace deposited on, grown on, or embedded within the substrate of the second die. In some examples, the second portion can include conductive vias to extend the trace to an external or internal termination of the second die.

At305, the first die can be electrically and mechanically coupled with the second die and can include electrically and mechanically coupling the first portion of the inductor coil with the second portion of the inductor coil to provide an inductor having at least one conductive coil or turn. In certain examples, connecting the first portion of inductor coil can be electrically connected with the second portion of the inductor coil using die-to-die interconnects such as solder balls or pins. In such cases, the die-to-die interconnects can become part of the inductor and can form a portion of an inductor coil.

In some examples, a core material of the inductor can be fabricated on at least one of the first die or the second die such that the core material traverses through a coil of the inductor formed by the first portion, the second portion and the die-to-die interconnects. In some examples, the core material can include a magnetic material, such as, but not limited to, a ferrous material, organic magnetic materials, inorganic magnetic materials, composite magnetic materials, or combination thereof. In certain examples, the core material can be applied using sputtering, spin coating, lamination, paste printing, or combinations thereof.

FIGS. 4A-4Cillustrates generally an alternative configuration and method for an inductor401at a first level interface.FIG. 4Aillustrates a first semiconductor die411, a semiconductor interposer413, and a semiconductor substrate or second semiconductor die412. The first die411and the second die412can be fabricated to include traces403for the inductor401using conventional semiconductor fabrication techniques. Each individual trace403can form a portion of a coil of the inductor401.FIG. 4Billustrates generally the assembled first die411and interposer413. Prior to assembly, a magnetic material407can be applied to a surface of the first die411, one or more surfaces of the interposer413, or to a surface of the interposer413and a surface of the first die411. The first die411and the interposer413can be assembled by, for example, thermal compression bonding (TCB), de-flux, and epoxy fill. Optionally, additional die408can be assembled to the interposer413on the same side as the first die411. In some examples, the inductor401can be completed upon assembly of the first die411and the interposer413when the interposer413includes trace routings to complete the coils of the inductor401.

FIG. 4Cillustrates generally a package assembly400including the assembled first die411and interposer413, and the second die412. In certain examples, traces or conductive vias405at the back side of the interposer can be connected to the second die412using interconnects404such as solder balls to complete the inductor401. In such an example, the interposer413includes traces and vias405to form vertical portions of inductor coils, and the first and second dies411,412include traces403to form horizon portions of the inductor coils. In some examples, magnetic material407can be applied to a surface of the second die412. In general, the magnetic material407can be applied to any or all of the first die411, second die412or interposer413such that upon assembly, the magnetic material407is enveloped within the coils of the inductor401as in the examples ofFIGS. 1A-IC and2A-2B. In certain examples, the magnetic material407can be applied by, but not limited to, chemical vapor deposition or sputtering. Such processes can allow use of insulating magnetic materials with higher permeability (1400-2400) including, but not limited to, FeXN, where Fe is iron, N is nitrogen and X can be Titanium (Ti), Aluminum (Al), Hafnium (Hf), Cobalt-Halfnium (CoHf), Chromium-Halfnium (CrHf).

FIG. 5illustrates a block diagram of an example machine500upon which any one or more of the techniques (e.g., methodologies) discussed herein may perform. In alternative embodiments, the machine500may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine500may operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine500may act as a peer machine in peer-to-peer (or other distributed) network environment. As used herein, peer-to-peer refers to a data link directly between two devices (e.g., it is not a hub- and spoke topology). Accordingly, peer-to-peer networking is networking to a set of machines using peer-to-peer data links. The machine500may be a single-board computer, an integrated circuit package, a system-on-a-chip (SOC), a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, or other machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.

Machine (e.g., computer system)500may include a hardware processor502(e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory504and a static memory506, some or all of which may communicate with each other via an interlink (e.g., bus)508. The machine500may further include a display unit510, an alphanumeric input device512(e.g., a keyboard), and a user interface (UI) navigation device514(e.g., a mouse). In an example, the display unit510, input device512and UI navigation device514may be a touch screen display. The machine500may additionally include a storage device (e.g., drive unit)516, a signal generation device518(e.g., a speaker), a network interface device520, and one or more sensors521, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine500may include an output controller528, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.). In certain examples, any one or more of the display unit510, storage device516, network interface device or combination thereof can include a multiple device PCIe card.

The storage device516may include a machine readable medium522on which is stored one or more sets of data structures or instructions524(e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions524may also reside, completely or at least partially, within the main memory504, within static memory506, or within the hardware processor502during execution thereof by the machine500. In an example, one or any combination of the hardware processor502, the main memory504, the static memory506, or the storage device516may constitute machine readable media.

FIG. 6illustrates a system level diagram, depicting an example of an electronic device (e.g., system) including a PCIe card as described in the present disclosure.FIG. 6is included to show an example of a higher level device application that can use serial interfaces, such as those discussed above, exchange data between the illustrated components. In one embodiment, system600includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system600is a system on a chip (SOC) system.

In one embodiment, processor610has one or more processor cores612and612N, where612N represents the Nth processor core inside processor610where N is a positive integer. In one embodiment, system600includes multiple processors including610and605, where processor605has logic similar or identical to the logic of processor610. In some embodiments, processing core612includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor610has a cache memory616to cache instructions and/or data for system600. Cache memory616may be organized into a hierarchal structure including one or more levels of cache memory.

In some embodiments, processor610includes a memory controller614, which is operable to perform functions that enable the processor610to access and communicate with memory630that includes a volatile memory632and/or a non-volatile memory634. In some embodiments, processor610is coupled with memory630and chipset620. Processor610may also be coupled to a wireless antenna678to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, an interface for wireless antenna678operates in accordance with, but is not limited to, the IEEE 602.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

In some embodiments, volatile memory632includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory634includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

Memory630stores information and instructions to be executed by processor610. In one embodiment, memory630may also store temporary variables or other intermediate information while processor610is executing instructions. In the illustrated embodiment, chipset620connects with processor610via Point-to-Point (PtP or P-P) interfaces617and622. Chipset620enables processor610to connect to other elements in system600. In some embodiments of the example system, interfaces617and622operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In some embodiments, chipset620is operable to communicate with processor610,605N, display device640, and other devices, including a bus bridge672, a smart TV676, I/O devices674, nonvolatile memory660, a storage medium (such as one or more mass storage devices)662, a keyboard/mouse664, a network interface666, and various forms of consumer electronics677(such as a PDA, smart phone, tablet etc.), etc. In one embodiment, chipset620couples with these devices through an interface624. Chipset620may also be coupled to a wireless antenna678to communicate with any device configured to transmit and/or receive wireless signals.

Chipset620connects to display device640via interface626. Display640may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the example system, processor610and chipset620are merged into a single SOC. In addition, chipset620connects to one or more buses650and655that interconnect various system elements, such as I/O devices674, nonvolatile memory660, storage medium662, a keyboard/mouse664, and network interface666. Buses650and655may be interconnected together via a bus bridge672.

While the modules shown inFIG. 6are depicted as separate blocks within the system600, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory616is depicted as a separate block within processor610, cache memory616(or selected aspects of616) can be incorporated into processor core612.

ADDITIONAL NOTES

In a first example, Example 1, an apparatus can include a first die having first plurality of external terminations, a second die having a second plurality of external terminations, a plurality of connectors coupling the first plurality of external terminations to the second plurality of external terminations, and an inductor winding comprising the plurality of connectors.

In Example 2, an integrated circuit package optionally includes the second die of Example 1.

In Example 3, the plurality of connectors of any one or more of Examples 1-2 optionally includes solder balls.

In Example 4, the apparatus of any one or more of Examples 1-3 optionally includes a magnetic material disposed within the inductor winding and disposed between the first die and the second die.

In Example 5, the plurality of connectors of any one or more of Examples 1-4 optionally is arranged in two groups and the magnetic material is disposed between the two groups of connectors.

In Example 6, the magnetic material of any one or more of Examples 1-5 optionally is mechanically coupled to a surface of the first die, the surface directly adjacent the second die.

In Example 7, the magnetic material of any one or more of Examples 1-6 optionally is mechanically coupled to a surface of the second die, the surface directly adjacent the first die.

In Example 8, an inductor can include a winding, and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, a plurality of connectors configured to connect the first die with the second die, and each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

In Example 9, an integrated circuit package optionally includes the second die of any one or more of Examples 1-8 optionally.

In Example 10, the plurality of connectors of any one or more of Examples 1-9 optionally includes solder balls.

In Example 11, the core of any one or more of Examples 1-10 optionally includes a magnetic material within the winding and located between the first die and the second die.

In Example 12, the plurality of connectors of any one or more of Examples 1-11 optionally is arranged in two groups and the magnetic material is disposed between the two groups of connectors.

In Example 13, the magnetic material of any one or more of Examples 1-12 optionally is mechanically coupled to a surface of the first die, the surface directly adjacent the second die.

In Example 14, the magnetic material of any one or more of Examples 1-13 optionally is mechanically coupled to a surface of the second die, the surface directly adjacent the first die.

In Example 15, a method can include fabricating a first portion of an inductor coil at a substrate of a first die, fabrication a second portion of the inductor coil at a substrate of a second die, and electrically and mechanically coupling the first die and the first portion of the inductor coil with the second die and the second portion of the inductor coil.

In Example 16, the fabricating the first portion of the inductor coil of any one or more of Examples 1-15 optionally includes coupling a trace of the substrate forming a first portion of a first winding coil to first and second external terminations of the second die, the trace configured to form a first portion of a first complete winding of the inductor coil.

In Example 17, the method of any one or more of Examples 1-16 optionally includes depositing a magnetic material to the substrate of the first die between the first and second external terminations of the first die.

In Example 18, the fabricating the second portion of the inductor coil of any one or more of Examples 1-17 optionally includes coupling a trace of the second die to first and second external terminations of the second die.

In Example 19, the method of any one or more of Examples 1-18 optionally includes depositing a magnetic material to a surface of the second die between the first and second external terminations of the second die.

In Example 20, the electrically and mechanically coupling the first die and first portion of inductor coil with the second die and second portion of inductor coil of any one or more of Examples 1-19 optionally includes mechanically and electrically coupling a trace of the first portion of the inductor coil with a trace of the second portion of the inductor coil using a solder ball connector.