Method of semiconductor integrated circuit fabrication

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs.

BACKGROUND

This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing. For these advances to be realized, similar developments in IC processing and manufacturing are needed. When a semiconductor device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) is scaled down through various technology nodes, interconnects of conductive lines and associated dielectric materials that facilitate wiring between the transistors and other devices play a more important role in IC performance improvement. Although existing methods of fabricating IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, challenges rise to develop a more robust metal line formation for interconnection structures. It is desired to have improvements in this area

DETAILED DESCRIPTION

FIG. 1is a flowchart of one embodiment of a method100of fabricating one or more semiconductor devices according to aspects of the present disclosure. The method100is discussed in detail below, with reference to a semiconductor device200shown inFIGS. 2 to 6for the sake of example.

Referring toFIGS. 1 and 2, the method100begins at step102by providing a substrate210. The substrate210includes silicon. Alternatively or additionally, the substrate210may include other elementary semiconductor such as germanium. The substrate210may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate210may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate210includes an epitaxial layer. For example, the substrate210may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the substrate210may include a semiconductor-on-insulator (SOI) structure. For example, the substrate210may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable technique, such as wafer bonding and grinding.

The substrate210may also include various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions include n-well, p-well, light doped region (LDD), heavily doped source and drain (S/D), and various channel doping profiles configured to form various integrated circuit (IC) devices, such as a complimentary metal-oxide-semiconductor field-effect transistor (CMOSFET), imaging sensor, and/or light emitting diode (LED). The substrate210may further include other functional features such as a resistor or a capacitor formed in and on the substrate.

The substrate210may also include various isolation features. The isolation features separate various device regions in the substrate210. The isolation features include different structures formed by using different processing technologies. For example, the isolation features may include shallow trench isolation (STI) features. The formation of a STI may include etching a trench in the substrate210and filling in the trench with insulator materials such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trench may have a multi-layer structure such as a thermal oxide liner layer with silicon nitride filling the trench. A chemical mechanical polishing (CMP) may be performed to polish back excessive insulator materials and planarize the top surface of the isolation features.

The substrate210may also include gate stacks formed by dielectric layers and electrode layers. The dielectric layers may include an interfacial layer (IL) and a high-k (HK) dielectric layer deposited by suitable techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, or other suitable techniques. The electrode layers may include a single layer or multi layers, such as metal layer, liner layer, wetting layer, and adhesion layer, formed by ALD, PVD, CVD, or other suitable process.

The substrate210may also include a plurality of inter-level dielectric (ILD) layers and conductive features integrated to form an interconnect structure configured to couple the various p-type and n-type doped regions and the other functional features (such as gate electrodes), resulting a functional integrated circuit. In one example, the substrate210may include a portion of the interconnect structure and the interconnect structure includes a multi-layer interconnect (MLI) structure and an ILD layer integrated with a MLI structure, providing an electrical routing to couple various devices in the substrate210to the input/output power and signals. The interconnect structure includes various metal lines, contacts and via features (or via plugs). The metal lines provide horizontal electrical routing. The contacts provide vertical connection between silicon substrate and metal lines while via features provide vertical connection between metal lines in different metal layers.

The substrate210includes a device component214. In one embodiment, the device component214includes conductive features. The conductive feature214may include a portion of the interconnect structure. For example, the conductive features214include contacts, metal vias, or metal lines. The conductive features214may be formed by a procedure including lithography, etching and deposition. In another embodiment, the conductive features214include electrodes, capacitors, resistors or a portion of a resistor. Alternatively, the conductive features214may include doped regions (such as sources or drains), or gate electrodes. In another example, the conductive features214are silicide features disposed on respective sources, drains or gate electrodes. The silicide feature may be formed by a self-aligned silicide (salicide) technique.

Referring toFIGS. 1 and 3, the method100proceeds to step104by forming a patterned adhesion layer310with a first thickness (t1) above the substrate210. The patterned adhesion layer310may include cobalt (Co), ruthenium (Ru), manganese (Mn), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), or other suitable material. The patterned adhesion layer310may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or other suitable processes. The patterned adhesion layer310may be patterned by lithography and etching processes. The patterned adhesion layer310includes a first area312that it is aligned to at least a portion of the respective device component214and a second area314where the device component214is absent. For example, in the first area312, the patterned adhesion layer310fully covers the respective device component214and extends to the substrate210. For another example, in the first area312, the patterned adhesion layer310is formed aligning with the respective device component214without extending to the substrate210. The second area314is located with a distance (d) from the first area312.

Referring toFIGS. 1 and 4, the method100proceeds to step106by depositing a metal layer410with a second thickness (t2) over substrate210, and above the patterned adhesion layer310. The metal layer410includes metals, as well as metal alloys, with high surface energy, such as copper (Cu), tin (Sn), silver (Ag), gold (Au), palladium (Pd), platinum (Pt), rhenium (Re), iridium (Ir), ruthenium (Ru), osmium (Os), copper manganese (CuMn), copper aluminum (CuAl), copper titanium, (CuTi), copper vanadium (CuV), copper chromium (CuCr), copper silicon (CuSi), copper niobium (CuNb), or other suitable metals. The metal410may be deposited by PVD, CVD, ALD, electrochemical plating (ECP), or other suitable processes.

Referring toFIGS. 1 and 5, the method100proceeds to step108by applying an elevated temperature thermal process to agglomerate the metal layer410and form self-forming metal features (SFMF)420on the patterned adhesion layer310, with a width w and a height h. During the thermal process, voids start to be formed in the metal layer410in an area where the patterned adhesion layer310is absent, followed by the growth of these voids as fractals. Finally the metal layer410is fully agglomerated to form the SFMFs420on top of the patterned adhesion layer310. As seen from a top view, a shape of the SFMF420is substantially the same as a shape of the respective patterned adhesion layer310. A top portion of a SFMF420is observed to have an irregular agglomerated surface. In the present embodiment, the width w of the SFMF420is defined by the patterned adhesion layer310and the height h is formed as a result of a combination of a thickness of the metal layer410and the width w. A shape of the top portion of the irregular agglomerated surface of the SFMF420may be substantially different corresponding to a different ratio of w to h. For example, it is observed that the higher of the ration (w/h), the more flat in a center and more round in edges of the top portion of the agglomerated surface.

In the present embodiment, a set of predetermined targets of the first thickness (t1) of the patterned adhesion layer310, the distance (d) between the first and second areas,312and314, of the patterned adhesion layer310, the second thickness (t2) of the metal layer410and the temperature of the thermal process is configured to achieve forming the SFMF420over the patterned adhesion layer310. The metal layer410is fully segregated in the area where the patterned adhesion layer310is absent. As an example, the first thickness (t1) of the Co patterned adhesion layer310is in a range from 5 Å to 15 Å and the second thickness (t2) of the Cu layer410is in a range from 10 Å to 500 Å. The temperature of the thermal process is in a range from 200° C. to 700° C. As another example, the Co patterned adhesion layer is deposited with a thickness in a range from 5 Å to 20 Å, and the Cu layer is deposited on the Co patterned adhesion layer with a thickness in a range from 50 Å to 200 Å. The thermal process is applied to the Cu layer with a temperature in a range from 350° C. to 500° C. In one embodiment, the second area314of the patterned adhesion layer310is designed for forming a dummy SFMF in a low metal feature density area.

In one embodiment, the SFMF420formed in the first area312is configured to provide vertical connection between device components in the substrate and metal lines of different metal layers, while the SFMF420formed in the second area314to provide a horizontal electrical routing in a same metal layer.

Referring toFIGS. 1 and 6, the method100proceeds to step110by depositing a dielectric layer510between SFMFs420to isolate each SFMF420from each other. The dielectric layer510includes dielectric materials, such as silicon oxide, silicon nitride, a dielectric material having a dielectric constant (k) lower than thermal silicon oxide (therefore referred to as low-k dielectric material layer), or other suitable dielectric material layer. In various examples, the low k dielectric material may include fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other materials as examples. In another example, the low k dielectric material may include an extreme low k (XLK) dielectric material. A process of forming the dielectric layer510may utilize spin-on coating or CVD.

In one embodiment, a barrier layer430is deposited on the SFMF420prior to depositing the dielectric layer510. The barrier layer430may include tantalum (Ta), titanium (Ti), manganese (Mn), cobalt (Co), ruthenium (ru), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), manganese oxide (MnO), aluminium nitride, aluminium oxide, or other suitable materials. The barrier layer430may be deposited by PVD, CVD, ALD, or other suitable processes.

Additionally, a CMP process is performed to remove excessive dielectric layer510. In one embodiment, the CMP removes a portion of top portion of the SFMF420and planarize the top surface of the dielectric layer510with the top surface of the SFMF420.

Additional steps can be provided before, during, and after the method100, and some of the steps described can be replaced, eliminated, or moved around for additional embodiments of the method100. As an example, steps104to110are repeated to form new metal/dielectric interconnections.

Based on the above, the present disclosure offers methods for fabricating IC device. The method employs forming a metal line by agglomerating high surface energy metal and patterning the metal line by using adhesion differentiation with a patterned adhesion layer during the agglomeration. The method provides a metal line formation by deposition and thermal process. The method demonstrates a robust metal line formation for small dimension.

The present disclosure provides many different embodiments of fabricating a semiconductor IC that provide one or more improvements over other existing approaches. In one embodiment, a method for fabricating a semiconductor integrated circuit (IC) includes providing a providing a substrate, forming a patterned adhesion layer over the substrate, depositing a metal layer on the patterned adhesion layer, applying a thermal process to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) over the patterned adhesion layer. A top portion of the SFMF has an irregular agglomerated surface. The method also includes and depositing a dielectric layer between SFMFs.

In another embodiment, a method for fabricating a semiconductor IC includes providing a substrate having conductive features, forming a patterned adhesion layer over the substrate. The patterned adhesion layer has a first area which aligns to, at least, a portion of the respective conductive feature. The method also includes depositing a metal layer on the patterned adhesion layer, applying a thermal process to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) over the patterned adhesion layer. A top portion of the SFMF has an irregular agglomerated surface. The method also includes depositing a dielectric layer between SFMFs.

In yet another embodiment, a semiconductor device includes a substrate having a device component, a patterned adhesion layer over the substrate. The patterned adhesion layer has a first area where the patterned adhesion layer aligns to at least a portion of the device component and a second area where the device component is absent. The semiconductor device also includes a self-forming-metal-feature (SFMF) formed by metal agglomeration on the patterned adhesion layer, in both of first and second areas, with an irregular agglomerated surface. A top portion of the SFMF has an irregular agglomerated surface. As seen from a top view, the SFMF has a shape that is substantial similar to a shape of the corresponding portion of the patterned adhesion layer. The SFMF is formed with a pattern which is substantial same as the patterned adhesion layer over the substrate. The semiconductor device also includes a dielectric layer between the SFMFs.