Testing device and testing method

A testing device includes a transmitter circuit, a receiver circuit, and a loopback circuit. The transmitter circuit is configured to receive a plurality of first test signals. The receiver circuit is configured to receive input data from a plurality of pads in a normal mode. The loopback circuit is coupled to the plurality of pads and input terminals of a sampler circuit, and the loopback circuit is configured to transmit the plurality of first test signals from the transmitter circuit to the input terminals of the sampler circuit, in order to generate test data for subsequent analysis.

BACKGROUND

Technical Field

The present disclosure relates to a testing device. More particularly, the present disclosure relates to a testing device and a testing method for loopback test.

Description of Related Art

Integrated circuits may be connected with each other via high-speed serial interfaces. In practical applications, high-speed serial interfaces typically include an input/output (I/O) circuit. A test signal may be applied to transmitter pads of an I/O circuit and may be looped back to receiver pads of the I/O circuit, in order to identify defects in the I/O circuit. In current approaches, in order to perform such test, an additional multiplexer is required to be coupled to the receiver. As a result, the performance of the receiver is degraded due to impacts from extra capacitance and resistance of the additional multiplexer.

SUMMARY

Some aspects of the present disclosure are to provide a testing device that includes a transmitter circuit, a receiver circuit, and a loopback circuit. The transmitter circuit is configured to receive a plurality of first test signals. The receiver circuit is configured to receive input data from a plurality of pads in a normal mode. The loopback circuit is coupled to the plurality of pads and input terminals of a sampler circuit, and the loopback circuit is configured to transmit the plurality of first test signals from the transmitter circuit to the input terminals of the sampler circuit, in order to generate test data for subsequent analysis.

Some aspects of the present disclosure are to provide to a testing method that includes the following operations: receiving, by a transmitter circuit, a plurality of first test signals; and transmitting, by a loopback circuit, the plurality of first test signals from the transmitter circuit to input terminals of a sampler circuit, in order to generate test data for subsequent analysis, in which the loopback circuit is coupled to a plurality of pads corresponding to a receiver circuit and the input terminals of the sampler circuit.

As described above, the testing device and the testing method provided in some embodiments of the present disclosure are able to be applied for loopback high-speed data transmission.

DETAILED DESCRIPTION

The following embodiments are disclosed with accompanying diagrams for detailed description. For illustration clarity, many details of practice are explained in the following descriptions. However, it should be understood that these details of practice do not intend to limit the present disclosure. That is, these details of practice are not necessary in parts of embodiments of the present embodiments. Furthermore, for simplifying the drawings, some of the conventional structures and elements are shown with schematic illustrations.

In this document, the term “coupled” may also be termed as “electrically coupled,” and the term “connected” may be termed as “electrically connected.” “Coupled” and “connected” may mean “directly coupled” and “directly connected” respectively, or “indirectly coupled” and “indirectly connected” respectively. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

In this document, the term “circuitry” may indicate a system formed with one or more circuits. The term “circuit” may indicate an object, which is formed with one or more transistors and/or one or more active/passive elements based on a specific arrangement, for processing signals.

Reference is made toFIG. 1.FIG. 1is a schematic diagram of a testing device100according to some embodiments of the present disclosure. In some embodiments, the testing device100may be a design for test (DFT) circuitry that is formed in a single chip. In some embodiments, the testing device100is for high-speed data input/output (I/O) tests.

The testing device100includes a transmitter circuit110, a loopback circuit120, a pattern generator circuit130, a receiver circuit140, and a sampler circuit150. The transmitter circuit110is configured to output data DOUT via pads TX1and TX2. The receiver circuit140is configured to receive data DIN via pads RX1and RX2. In some embodiments, the pads TX1and TX2may be output pads of a die where the testing device100is formed on, and the pads RX1and RX2may be input pads of the die.

The pattern generator circuit130is configured to generate test signals ST1and ST2, and transmit the same to the transmitter circuit110. In some embodiments, the test signals ST1and ST2may be signals that have specific patterns for testing I/O circuitry.

The loopback circuit120is coupled between the transmitter circuit110and the receiver circuit140. In some embodiments, the loopback circuit120is enabled in response to an enable signal EN. The loopback circuit120is enabled to provide a connection between the transmitter circuit110and the receiver circuit140, in order to loop signal(s) from the transmitter circuit110back to the receiver circuit140.

For example, when the loopback circuit120is enabled, the receiver circuit140operates in a testing mode and receives test signals ST3and ST4, such that a test on the transmitter circuit110and the receiver circuit140is started. Alternatively, when the loopback circuit120is not enabled, the receiver circuit140operates in a normal mode and receives the data DIN. In some embodiments, logic values of the test signals ST3and ST4are the same as the test signals ST1and ST2respectively. In some embodiments, the loopback circuit120outputs the test signals ST3and ST4in response to the test signals ST1and ST2correspondingly.

In some embodiments, as discussed below, the loopback circuit120is coupled to termination resistors of the receiver circuit140and input terminals of the sampler circuit150. In some embodiments, the loopback circuit120is configured to cooperate with these termination resistors, in order to transmit the test signals ST3and ST4to the sampler circuit150. As a result, the testing device100is able to be applied for high-speed test. An example of the loopback circuit120is provided with reference toFIG. 2for further clarification.

The sampler circuit150is coupled to the loopback circuit120and the receiver circuit140to receive the test signal ST3and ST4. The sampler circuit150is configured to sample the test signal ST3and ST4, in order to output test data DT for subsequent analysis. In some embodiments, the sampler circuit150may be implemented with a comparator circuit.

Reference is made toFIG. 2.FIG. 2is a circuit diagram of part of the testing device100inFIG. 1according to some embodiments of the present disclosure. For ease of understanding, like elements inFIGS. 1-2are designated with the same reference number.

The transmitter circuit110includes transistors T1and T2and a current source circuit I1. The transistors T1and T2may be biased by the current source circuit I1, in order to operate as an input pair of a pre-driver. In the normal mode, the test signals ST1and ST2are de-asserted, and signals VT1and VT2are asserted. Under this condition, the transistors T1and T2receive the signals VT1and VT2, and operate in response to the signals VT1and VT2, respectively, to amplify the signals VT1and VT2, in order to output the data DOUT via the pads TXTand TX2. In the testing mode, the test signals ST1and ST2are asserted and the signals VT1and VT2are de-asserted. Under this condition, input terminals of the transistors T1and T2are configured to receive the test signals ST1and ST2from the pattern generator circuit130, and the transistors T1and T2operate in response to the signals ST1and ST2, respectively.

In some embodiments, asserting the signals VT1and VT2while de-asserting the test signals ST1and ST2, and asserting the test signals ST1and ST2while de-asserting the signals VT1and VT2, are performed by at least one multiplexer circuit. For example, the signals ST1and VT1are selected by a multiplexer, and the signals ST2and VT2are selected by another multiplexer.

In some embodiments, the receiver circuit140includes termination resistors TR1and TR2. The termination resistor TR1is coupled to the pad RX1and an input terminal151of the sampler circuit150. The termination resistor TR2is coupled to the pad RX2and an input terminal152of the sampler circuit150. In some embodiments, the termination resistors TR1and TR2are configured to prevent signals received by the pads RX1and RX2from being reflected. In some embodiments, each of the termination resistors TR1and TR2may be implemented with a variable resistor. In some embodiments, each of the termination resistors TR1and TR2may be 50 ohm, but the present disclosure is not limited thereto.

The implementations and the values of the termination resistors TR1and TR2are given for illustrative purposes only. Various implementations and the values of the termination resistors TR1and TR2are within the contemplated scope of the present disclosure.

The loopback circuit120is coupled to control terminals of transistors T1and T2(e.g., input terminals of the transmitter circuit110), the termination resistors TR1and TR2, and the input terminals151and152of the sampler circuit150. In some embodiments, the loopback circuit120includes a control circuit121and a driver circuit122. The control circuit121is enabled by the enable signal EN, in order to output control signals O1and O2in response to the test signal ST1and ST2. The driver circuit122generates the test signal ST3and ST4in response to the control signals O1and O2.

For example, the control circuit121includes inverters A1and A2. An input terminal of the inverter A1is coupled to the control terminal of the transistor T1, in order to receive the test signal ST1. The inverter A1is enabled by the enable signal EN, and thus outputs the control signal O1in response to the test signal ST1. An input terminal of the inverter A2is coupled to the control terminal of the transistor T2, in order to receive the test signal ST2. The inverter A2is enabled by the enable signal EN, and thus outputs the control signal O2in response to the test signal ST2.

The driver circuit122is coupled to the termination resistors TR1and TR2and the input terminals151and152of the sampler circuit150. The driver circuit122includes transistors T3and T4, and a current source circuit I2. A first terminal of the transistor T3is coupled to the input terminal151of the sampler circuit150, a second terminal of the transistor T3is coupled to the current source circuit I2, and a control terminal of the transistor T3is configured to receive the control signal O2. In response to the control signal O2, the transistor T3is turned on or off to adjust a level of the input terminal151, in order to generate the test signal ST3. For example, if the test signal ST2has a logic value of 0, the control signal O2has a logic value of 1. In response to this control signal O2, the transistor T3is turned on to pull down the level of the input terminal151to the ground voltage GND via the current source circuit I2. Under this condition, the test signal ST3having the logic value of 0 is generated and transmitted to the input terminal151. Alternatively, if the test signal ST2has the logic value of 1, the control signal O2has the logic value of 0. In response to this control signal O2, the transistor T3is turned off, and thus the level of the input terminal151is pulled up to a voltage VDD via the termination resistor TR1(e.g., current signal Su1). Under this condition, the test signal ST3having the logic value of 1 is generated and transmitted to the input terminal151.

A first terminal of the transistor T4is coupled to the input terminal152of the sampler circuit150, a second terminal of the transistor T4is coupled to a first terminal of the current source circuit I2, and a control terminal of the transistor T4is configured to receive the control signal O1.

In response to the control signal O1, the transistor T4is turned on or off to adjust a level of the input terminal152, in order to generate the test signal ST4. For example, if the test signal ST1has a logic value of 0, the control signal O1has a logic value of 1. In response to this control signal O1, the transistor T4is turned on to pull down the level of the input terminal152to the ground voltage GND via the current source circuit I2. Under this condition, the test signal ST4having the logic value of 0 is generated and transmitted to the input terminal152. Alternatively, if the test signal ST1has the logic value of 1, the control signal O1has the logic value of 0. In response to this control signal O1, the transistor T4is turned off, and thus the level of the input terminal152is pulled up to a voltage VDD via the termination resistor TR2(e.g., current signal Su2). Under this condition, the test signal ST4having the logic value of 1 is generated and transmitted to the input terminal152.

In this example, the sampler circuit150is implemented with a comparator circuit that compares the test signal ST3with the test signal ST4, in order to generate the test data DT. In some embodiments, by comparing the test signal ST3with the test signal ST4, a test pattern carried between the test signal ST3and the test signal ST4is able to be sampled.

In some related approaches, an additional multiplexer is employed and is arranged between a receiver and a loopback circuit, in order to couple an input signal path of the receiver to a transmitter. However, the additional multiplexer introduces parasitic capacitance and/or resistance to the receiver. As a result, the performance of the receiver is degraded, and thus the receiver is not suitable for high-speed data transmission.

In some embodiments, the loopback circuit120is directly coupled the pads RX1and RX2and the termination resistors TR1and TR2. In practical applications, the pads RX1and RX2may include an electrostatic discharge (ESD) protection device (not shown) to avoid ESD damage. Under this condition, capacitances and/or resistances on nodes (e.g., input terminals151and152) that are coupled to the pads RX1and RX2are substantially dominated by the ESD protection device. Accordingly, capacitances and/or resistances introduced from the loopback circuit120to these nodes can be negligible. As a result, the performance of the receiver circuit140is not significantly impacted by the loopback circuit120.

In some other approaches, a transmitter and a receiver may be operated in different power domains, and thus an additional level shifter is required in a loopback test. Compared to these approaches, in some embodiments, as discussed above, the test signal ST3and ST4are generated in response to the current signal (e.g., Su1, Su2, and/or current of the current source circuit I2). Accordingly, no additional level shifter is needed in the loopback test. In other words, the loopback circuit120is able to run the loopback test in high-speed data transmission without the level shifter.

Reference is made toFIG. 3.FIG. 3is a circuit diagram of the inverter A1inFIG. 2according to some embodiments of the present disclosure. For ease of understanding, like elements inFIGS. 2-3are designated with the same reference number.

The inverter A1includes transistors M1, M2, and M3. The transistors M2and M3are configured to operate as a normal inverter circuit. The transistor M1is coupled to the transistors M2and M3in series, and is turned on according to the enable signal EN. The transistor M1provides a power gating mechanism to the transistors M2and M3. For example, when the transistor M1is turned on, the transistors M2and M3are powered (e.g., enabled) to generate the control signal O1. Alternatively, when the transistor M1is turned off, the transistors M2and M3are shut off. Circuit architecture of the inverter A2may be the same as that of the inverter A1, and thus the repetitious descriptions are not given.

The embodiments of each figure are given for illustrative purposes, and the present disclosure is not limited to circuit configurations, transistor types (e.g., N type or P type) and/or transistor (e.g., field transistor, bipolar junction transistors) shown in each embodiment. Various circuit configurations that are able to achieve the same operations are within the contemplated scope of the present disclosure.

Reference is made toFIG. 4.FIG. 4is a flow chart of a testing method400of some embodiments of the present disclosure.

In operation S410, the transmitter circuit110receives the test signals ST1and ST2.

In operation S420, the loopback circuit120transmits the test signals ST1and ST2from the transmitter circuit110to the input terminals151and152of the sampler circuit150, in order to generate test data DT for subsequent analysis.

The above operations can be understood with reference to embodiments inFIGS. 1-3, and thus the repetitious descriptions are not given. The above description of the testing method400includes exemplary operations, but the operations of the testing method400are not necessarily performed in the order described above. The order of the operations of the testing method400can be changed, or the operations can be executed simultaneously or partially simultaneously as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure.

As described above, the testing device and the testing method provided in some embodiments of the present disclosure are able to be applied for loopback high-speed data transmission.

Various functional components or blocks have been described herein. As will be appreciated by persons skilled in the art, in some embodiments, the functional blocks will preferably be implemented through circuits (either dedicated circuits, or general purpose circuits, which operate under the control of one or more processors and coded instructions), which will typically comprise transistors or other circuit elements that are configured in such a way as to control the operation of the circuitry in accordance with the functions and operations described herein. As will be further appreciated, the specific structure or interconnections of the circuit elements will typically be determined by a compiler, such as a register transfer language (RTL) compiler. RTL compilers operate upon scripts that closely resemble assembly language code, to compile the script into a form that is used for the layout or fabrication of the ultimate circuitry. Indeed, RTL is well known for its role and use in the facilitation of the design process of electronic and digital systems.