Power management SRAM write bit line drive circuit

A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, where the downlevel is a second supply voltage lower than the first supply voltage.

TECHNICAL FIELD

The present disclosure relates to a static random-access memory (SRAM). In particular, this disclosure relates to reduced voltage write bit line for an SRAM.

BACKGROUND

SRAMs may be structured so that two or more SRAM cells are connected in parallel to one or more write bit lines. The write bit line(s) are coupled to a data input through a write driver logic. Prior to a write operation, the write driver logic may drive one of the write bit lines high, in conjunction with driving another of the write bit lines low, in response to a logic value applied to the data input. A particular SRAM cell is selected for writing by activating the cell's write word line. Once an SRAM cell's write word line is activated, the data value represented by the logic state(s) of the write bit line(s) may be written into the SRAM cell. The write word line is deactivated following the write operation. The state of the write bit line(s) may be changed prior to the next write operation.

FIG. 1is a schematic representation of a portion of a prior art SRAM circuit100having a column of SRAM cells110, a write driver logic156, a data input (DATA)150, a write bit line (WBL)160, and a write bit line complement (WBLC)158. Each cell110includes a pair of cross-coupled inverters,130,132, a write word line (WWL)108, a read word line (RWL)106, and a read data line (RD)103. Each cell110also includes NFET pass transistors1N1and1N2, read transistors1N3and1N8, and the nodes data true (TRU)104and data complement (CMP)102.

SRAM cells110are coupled to the write driver logic156through the WBL160, and the WBLC158. The transistors depicted inFIGS. 1,2and4will be recognized by one with ordinary skill in the art to be arranged to implement functions including pass gates, pull-up and pull-down devices.

The write driver logic156is comprised of inverter162coupled to DATA150and WBLC158, and inverter164coupled to WBLC158and WBL160. Inverters162and164are connected so as to invert and buffer (respectively) the logic value of DATA150, while driving WBLC158and WBL160, respectively with complimentary logic values. While the write bit line in this prior art example comprises two complimentary write bit lines WBL160and WBLC158, other types of SRAMs are contemplated which may employ only a single write bit line.

WBL160and WBLC158are connected to all SRAM cells110in a particular SRAM cell column, and distribute the logic value present on DATA150to all SRAM cells110within that column. Transistors1N1and1N2and WWL108are used to control the write operation to SRAM cell110. Each SRAM cell110of an SRAM column has its own WWL108, RWL106, and RD103, but only one of each is shown for simplicity of the text and figures.

One of ordinary skill in the art will recognize that “0” and “1” refer to logical “zero” and “one” values, respectively.

A write operation employs the write driver logic156. As an illustration, to write a 1 to the cell110, a 1 data value is applied to the DATA150input. The write driver logic156inverts and buffers the 1 value using inverters162and164, driving a 1 on WBL160and a 0 on WBLC158. WWL108is subsequently used to turn on pass transistors1N1and1N2, applying the 1 present on the WBL160and the 0 present on the WBLC158to the cross-coupled inverters130and132within SRAM cell110. The 1 data value applied to DATA150is then written into the SRAM cell110. After the data write operation, the WWL108is disabled, shutting off pass transistors1N1and1N2. The logic value on the DATA150may then change in preparation for a further write operation

A read operation employs the transistors1N3and1N8and the RWL106to enable reading, and RD103as an output capable of indicating the data read from SRAM cell110. Each SRAM cell110includes transistors1N3and1N8, an RWL106and an RD103, although these are only shown in one cell110(FIG. 1) for simplicity of figures and descriptions.

SUMMARY

One embodiment is directed to a static random access memory (SRAM). The SRAM may include two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC). In addition, the SRAM may also include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is also adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel. The downlevel is a voltage lower than the uplevel voltage, and low enough to be interpreted as a downlevel by the SRAM cell.

Another embodiment is directed to a static random access memory (SRAM). The SRAM may include two or more SRAM memory cells connected with a write bit line (WBL) and a write driver logic coupled to the WBL. The write driver logic is adapted to drive the WBL to a voltage uplevel below a first supply voltage in response to a first logical value on a data input, and to shut off the drive to the WBL when the WBL reaches the uplevel. The write driver logic is further adapted to drive the WBL to a downlevel, in response to a second logical value on the data input. The downlevel is a voltage lower than the uplevel voltage, and low enough to be interpreted as a downlevel by the SRAM cell.

A further embodiment is directed to a design structure for producing an SRAM. Aspects of the various embodiments may allow power consumption in an SRAM to be reduced.

In the drawings and the Detailed Description, like numbers generally refer to like components, parts, steps, and processes.

DETAILED DESCRIPTION

According to embodiments of the invention, an SRAM write bit line (WBL) may be driven by a write driver logic to a voltage uplevel below a first supply voltage. An SRAM column may contain a write driver logic and one or more SRAM cells, each cell storing a 1 or a 0. The SRAM cells may be coupled to the write driver logic through the WBL. During an SRAM write operation, the write driver logic may receive a data value from a data input. The write driver logic may drive the data value on a write bit line (WBL). The WBL may be connected to an SRAM cell. Connections between the WBL and the SRAM cell may be enabled by a write word line (WWL) causing the data value present on the WBL to be written into the SRAM cell. The WWL may be subsequently disabled, and the WBL may be driven to another data value for a next write operation.

The term “write bit line” is a generic term that may be used to indicate a single signal connected to two or more SRAM cells that conveys a logic value (0 or 1) to be written into an SRAM cell. “Write bit line” may also be used to indicate a pair of signals comprising, for example, a true (WBL) and a complement (WBLC) used in a similar manner. The terms “true” and “complement” are used only to distinguish two similar but inversely operable lines.

It will be appreciated by one skilled in the art of SRAM design that when the term “write bit line” indicates a pair of signals, that the signal pair will always be logical compliments of each other (one signal is a 1 while the other is a 0) during a write, within the timing tolerances of the logic used to generate them. It will also be understood that the logic used to drive each of the WBL and WBLC signals may be identical in structure and function, and may differ only in which phase of the data input signal is applied to the logic input.

For simplicity of the text, only the process of writing a 1 into an SRAM cell will be described, however, writing a 0 into an SRAM cell is a similar operation, using complimentary polarities of signals, and logic functions, understood by those skilled in the art. The write data true (WDT) and write data complement (WDC) logic functions (FIG. 4354,352) for example are identical in both structure and function, the only difference between them being the polarity of the logic signal presented to their inputs.

Exemplary embodiments shown inFIGS. 1,2,3and4depict the write bit line as a complimentary signal pair WBL and WBLC. This depiction does not limit the invention in any way. A single signal embodiment of the write bit line, or other means of conveying data to be written to an SRAM cell is contemplated.

Power reduction and management are becoming increasingly important as circuit technology advances. The write bit lines of SRAMs are often long, heavily loaded nets, having a rail to rail voltage swing between GND and Vdd. Fully drawing write bit lines to Vdd in SRAM circuits consumes unneeded energy and resources, while providing no performance benefit to SRAMs.

A reduction in write bit line voltage swing and SRAM switching power may result from drawing the write bit line to an uplevel below Vdd. Decreasing SRAM circuit power consumption may enable chips with lower overall power consumption.

A write driver logic with a feedback path to turn it off at a voltage below a first supply voltage but high enough to write data into an SRAM cell may be used in conjunction with a keeper circuit employing an NFET between the supply voltage Vdd and the write bit line. A reduction in write bit line voltage swing may result, causing a reduction of required write operation power. Reduction of write operation power may provide opportunities for SRAM and overall chip power management.

As may be seen from the following equation, the reduction of overall WBL voltage swing may reduce the energy consumed to charge and discharge the write bit lines:
P=A×C×V2×F
Where:
P=chip dynamic power consumption (W)
A=activity factor (coefficient with values between 0 and 1 indicating signal activity level)
C=capacitance of nodes being charged and discharged (F)
V=signal voltage swing (V)
F=switching frequency (Hz)

Reducing the voltage difference between the WBL uplevel voltage and the WBL downlevel voltage reduces V in the equation, which may in turn exponentially reduce power used in a write operation.

The device electrical characteristics of the NFETs employed in keeper circuits allow the write bit lines to be held at a voltage level of one NFET threshold voltage (Vt) below Vdd, according to embodiments of the invention. The write driver logic may also provide rapid charging of the write bit line (WBL), which may cause an SRAM performance increase.

When the source of an NFET pass transistor connected to the write bit line rises above (Vdd-Vt), where Vt is the NFET threshold voltage, the NFET is cut off, not allowing any more current to flow through it. Now referring toFIG. 1, when a write bit line (WBL)160is driven to apply a voltage uplevel to an inverter pair130,132in an SRAM cell110, if the voltage on WBL160is higher than the voltage on TRU104, then the source of NFET1N2is the side connected to TRU104. Once TRU104rises above the voltage of (Vdd-Vt), current no longer flows through NFET1N2to charge up TRU104. Thus, any power consumed in drawing WBL160(or similarly, WBLC158) to a voltage above (Vdd-Vt) is wasted, as charging of TRU104ceases at that voltage level.

FIG. 2is a schematic representation of a portion of an SRAM circuit200having a column of SRAM cells210, a write driver logic256, a data input (DATA)250, a write bit line (WBL)260, and a write bit line complement (WBLC)258. Referring toFIG. 1, the SRAM cells210, WBL260, and WBLC258are identical to the SRAM cells110, WBL160, and WBLC158(respectively) previously described.

Again referring toFIG. 1, one difference between write driver logic156and write driver logic256(FIG. 2) is use of NFET transistors2N6and2N4coupled between Vdd and WBL260, WBLC258, respectively, to draw the WBL260and WBLC258to an uplevel below Vdd. As an example, if a 1 is applied to the data input (DATA)250, inverters262and264buffer the signal, driving a 1 on the gate of NFET2N6, turning it on. NFET2N6then couples WBL260to VDD, subsequently charging WBL260, drawing its voltage towards Vdd. As the WBL260voltage approaches Vdd-Vt, the charging of WBL260diminishes rapidly, and the voltage “rolls off”, as shown in WBL voltage514(FIG. 5) of SRAM circuit200. Similarly, the TRU voltage512(FIG. 5) of SRAM circuit200also rolls off.

The SRAM circuit200(FIG. 2) may result in reduced power consumption (as previously described), relative to the prior art SRAM circuit100(FIG. 1) due to the reduced voltage swing of write bit lines. However, it may also yield reduced performance, due to the lower slew rate of the write bit lines (FIG. 5), which may not be desirable. Reduced SRAM power consumption accompanied by a performance reduction may not be a desirable combination.

FIG. 3is a diagrammatic representation of a portion of an SRAM circuit300having a write driver logic356and keeper circuits318and320coupled to an SRAM column301, according to embodiments of the invention.

The SRAM circuit300may contain an SRAM column301coupled to the write driver logic356and keeper circuits318and320. The column may have a plurality of SRAM cells310, each coupled to the write driver logic356and keeper circuits318and320through a write bit line (WBL)360and a write bit line complement (WBLC)358.

The write driver logic356may be comprised of a write data true (WDT)354logic, a write data complement (WDC)352logic and an inverter336. A data input (DATA)350may be coupled to the input of the inverter336and the input of the write data true (WDT)354logic. The output of the inverter336may be coupled to the input of the write data complement (WDC)352logic. The output of WDT354may drive the WBL360and the output of the WDC352may drive the WBLC358. The WDT354and the WDC352logics may be identical in structure and function.

In embodiments of the invention, driving the WBL360to an uplevel may be carried out through the write driver logic356, which may use a switch, such as a P-channel field effect transistor (PFET) operated by a data input (DATA)350signal. Embodiments of the invention may also hold or “keep” the WBL voltage level once it has been driven to an uplevel. Holding the WBL voltage level may be accomplished by using an NFET keeper circuit which is activated through feedback circuitry. So long as there is no drive path enabled for the WBL360, the WBL360may not be driven to an uplevel. Once a signal on the DATA input350enables a drive path for the WBL360, the WBL360may be driven to an uplevel by the write driver logic356. The write driver logic356may have a gate operated by a DATA350signal.

In embodiments of the invention the WBL360voltage may be at a downlevel from a previous write operation. Prior to a write operation, a data value (0 or 1) is presented to DATA350. The write driver logic356may either drive WBL360to an uplevel or a downlevel, in response to the data value on DATA350. For example, if the signal on DATA350is a 1, then write driver logic356may drive WBL360to an uplevel less than Vdd, and if the signal on DATA350is a 0, then write driver logic356may drive WBL360to a downlevel below the uplevel. Once the data presented on DATA350is represented on WBL360, it is then written into one of the SRAM cells310.

Various embodiments may contain sections of circuitry within the write driver logic356that may drive individual write bit lines to an uplevel or a downlevel, such as write data true (WDT)354and write data complement (WDC)352. Embodiments may also include keeper circuits (318and320) that may hold write bit lines at a WBL uplevel510(FIG. 5). Both write data and keeper circuits may provide coupling between Vdd and write bit lines.

One of the purposes of the write data logic is to rapidly pull up the write bit lines (358,360) to a 1 state (uplevel) to prepare it for a write operation. A write data circuit connects the WBL360to Vdd in response to a 1 level on the DATA350input. After the WBL360has been pulled to an uplevel, the WDT354is disabled, shutting off the driving connection between Vdd and WBL360.

The SRAM circuit300(FIG. 3) may result in reduced power consumption (as previously described) with no performance loss relative to the prior art SRAM circuit100(FIG. 1). SRAM circuit300may also result in increased performance over the SRAM circuit200(FIG. 2), which may be desirable. The voltage waveform WBL voltage508is an exemplary illustration of a charging curve of the WBL360as it is driven to an uplevel by WDT354.

The purpose of the keeper circuit such as318or320is to counteract any charge leakage that would cause the WBL360or WBLC358voltage to decrease from its uplevel over time. If the voltage of the WBL360is allowed to decrease due to leakage, it may incorrectly represent a 0 value, causing a data write error in the SRAM. The keeper circuit couples the WBL360to Vdd when the WBL360voltage is sensed at a 1 voltage level. The keeper circuit maintains a relatively weak connection between the WBL360and Vdd, which may generally be overcome without difficulty by the write driver logic356when the write driver logic356is driving a 0 on the WBL360. When the WBL360is discharged or pulled to a 0 level, the keeper circuit disables its connection between Vdd and WBL360.

The NFET transistor used in the keeper circuits318,320provides a voltage drop between Vdd and the WBL360. The connection scheme and electrical properties of the NFET transistors ensure a voltage drop between NFET source and drain terminals, causing the WBL uplevel voltage510(inFIG. 5) to be one NFET threshold voltage (Vt)504(FIG. 5) below Vdd502(FIG. 5).

Other embodiments of the elements ofFIG. 3are contemplated.

FIG. 4is a schematic representation of a portion of an SRAM circuit300having a column401coupled to a write driver logic356and keeper circuits318and320, according to embodiments of the invention.

The column401may have a plurality of SRAM cells310, each coupled to the write driver logic356and keeper circuits318and320through a write bit line (WBL)460and a write bit line complement (WBLC)458. The write driver logic356is comprised of a write data true (WDT)354logic, a write data complement (WDC)352logic and an inverter336.

The SRAM cells310, including all devices, inputs and outputs are identical to SRAM cells110previously described in reference toFIG. 1.

The interconnection of WDT354logic, WDC352logic and inverter336is identical to the interconnection previously described for WDT354, WDC352and inverter336(FIG. 3). For simplicity of the text, only the WDT354will be described, as the WDC352is identical to it in both structure and functionality.

One purpose of the write data true (WDT) circuit354is to provide a means to drive the WBL460to a WBL uplevel510(FIG. 5) (logic 1 value) corresponding to a voltage below a supply voltage Vdd (502) (FIG. 5), but suitable to drive the “1” into the SRAM cell310. Another purpose of the write data true (WDT) circuit354is to provide a means to drive the WBL460to a downlevel (logic 0 value) corresponding to a WBL downlevel518(FIG. 5).

The write data true (WDT) circuit354includes NFET4N7with a source connected to GND, a drain connected to WBL460, and a gate connected to the output of inverter444. The input of inverter444is connected to the data input (DATA)350. Inverter444and NFET4N7are used together to control driving the WBL460to a downlevel.

The write data true (WDT) circuit354also includes PFET4P2with a source connected to Vdd, a drain connected to WBL460, and a gate connected to the output of NAND gate438. One input of NAND gate438is connected to the data input (DATA)350, and the other input is connected to the output of inverter424. The input of inverter424is connected to WBL460. Inverter424, NAND gate438and PFET4P2are used to control driving the WBL460to an uplevel.

As an illustration of an operation of driving WBL460to an uplevel, it is assumed that the data value on input DATA350is initially a 0 and that the WBL460is a 0, ready to be driven to an uplevel. The initial states of both DATA350and WBL460cause the PFET4P2gate, the NFET4N7gate and node428to all be 1.

The operation to drive WBL to an uplevel begins with the DATA350signal changing from a 0 to a 1, causing inverter444to drive a 0 on the gate of NFET4N7. The 0 on the gate of NFET4N7causes it to shut off, terminating the connection between WBL460and GND. The NAND gate438responds to the 1 inputs from DATA350and node428, and drives a 0 on the gate of PFET4P2, turning it on. When on, PFET4P2connects Vdd to WBL460, rapidly increasing the WBL voltage508(inFIG. 5) from the WBL downlevel518(inFIG. 5).

As the voltage level of the WBL460rises from the WBL downlevel518(inFIG. 5), and crosses the switching threshold of inverter424, inverter424drives a 0 on node428. The 0 on node428causes the NAND gate438to drive a 1 on the gate of PFET4P2, shutting it off. Once PFET4P2is shut off, the connection of Vdd to WBL460connection is terminated, causing the driving of WBL460to cease.

The described feedback path creates a self-timed circuit that only enables the WBL460to be driven high as long as necessary to raise the WBL voltage508(FIG. 5) to a WBL uplevel (Vdd-Vt)510(FIG. 5). A designer may specify and tune the inverter424switching threshold to turn off PFET4P2just as WBL460reaches the WBL uplevel (Vdd-Vt)510(FIG. 5). Inverter424switching threshold adjustments may be made to accommodate various loads and slew rates of WBL460, as well as the combined delay of inverter424and NAND gate438. For example, a width/length ratio of a PFET pullup in inverter424that is large relative to a width/length ratio of an NFET in inverter424would make an inverter switching threshold higher than Vdd/2.

WBL voltage508(inFIG. 5) depicts an exemplary WBL charging waveform with a rapid slew rate, and limited voltage swing, both of which may be desirable.

As an illustration of an operation of driving WBL460to a downlevel, it is assumed that the data value on input DATA350is initially a 1, and that the WBL460is a 1, ready to be driven to an downlevel. The initial states of both DATA350and WBL460cause the PFET4P2gate to be a 1, and the NFET4N7gate and node428to be 0.

The operation to drive WBL to a downlevel begins with the DATA350signal changing from a 1 to a 0, causing inverter444to drive a 1 on the gate of NFET4N7. The 1 on the gate of NFET4N7causes it to turn on, creating a connection between WBL460and GND. When on, NFET4N7rapidly decreases the WBL460voltage until WBL460reaches WBL downlevel518. The NAND gate438continues to drive a 1 on the gate of PFET4P2, keeping it turned off.

The purpose of the keeper circuits318and320is to counteract any charge leakage that would cause the WBL460or WBLC458voltage to decrease from its uplevel over time. For simplicity of the text, only the keeper circuit320will be described, as the keeper circuit318is identical to it in both structure and functionality.

The keeper circuit connects the WBL460to Vdd when the WBL voltage is sensed at a 1 voltage level. Inverters416and414provide a copy of the 1 level sensed on WBL460to the gate of NFET4N5, turning it on. The keeper circuit maintains a relatively weak connection between the WBL460and Vdd, which may generally be overcome without difficulty by the write data true (WDT) logic354. When the WBL460is driven to a downlevel, the keeper circuit disables its connection between Vdd and WBL460. The NFET transistors used in the keeper circuit paths provide a voltage drop between Vdd and the WBL460. The connection scheme and electrical properties of the NFET transistors ensure a voltage drop between NFET source and drain terminals, causing the WBL uplevel510(FIG. 5) to be one NFET threshold voltage (Vt)504(FIG. 5) below Vdd502(FIG. 5).

A designer may specify the switching threshold of inverter416to be less than the inverter424switching threshold, approximating one half of Vdd. Providing the inverter416with a lower switching threshold than the inverter424ensures that the keeper circuit may become and stay activated despite minor variations in the WBL uplevel voltage510(FIG. 5). The switching threshold of inverter416may also be tuned to provide suitable noise margins between the WBL uplevel voltage510(inFIG. 5) and WBL downlevel voltage518(FIG. 5).

A designer may also specify the NFET4N5width and length to enable the write data true (WDT)354logic to overcome NFET4N5without difficulty.

One of ordinary skill in the art will appreciate that the embodiments depicted inFIGS. 3 and 4may produce shorter WBL rise times, and less roll off than the embodiment depicted inFIGS. 2 and 5, which may be desirable. The performance difference may arise from an NFET in the WBL drive path of write driver logic256(FIG. 2) having a gate to source voltage approaching an NFET threshold voltage during the latter part of the WBL260drive operation, limiting the current the NFET may source to the WBL to charge it.

FIG. 5is a waveform diagram depicting exemplary WBL460and TRU404(inFIG. 4) voltage levels during a write operation of an SRAM cell according to embodiments of the invention.FIG. 5also depicts an exemplary WBL voltage508swing between the WBL downlevel518and the WBL uplevel510.FIG. 5also illustrates an exemplary TRU voltage506swing between the GND516and the Vdd502.

Waveform TRU512illustrates a charging curve of node TRU204(FIG. 2), and WBL514illustrates a charging curve of node WBL260of (FIG. 2).

In this example, WBL downlevel voltage518may be identical to the ground (GND)516. Other embodiments may employ WBL downlevel voltages518that differ from ground (GND)516.

Prior to a write operation, the WBL360(inFIG. 3) may be drawn to the WBL uplevel510. The WBL uplevel voltage (Vdd-Vt)510may be one NFET threshold (Vt)504below Vdd502.

In an exemplary embodiment of the invention, the NFET threshold (Vt)504may be approximately ten percent of the supply voltage Vdd502. In another exemplary embodiment of the invention, the Vt504may be approximately twenty percent of the supply voltage Vdd502. A generally accepted range of Vt504values lies between approximately ten and thirty percent of supply voltage Vdd502, but this range does not limit possible (Vt)504values in any way. NFET threshold voltages may vary according to several factors, including but not limited to various design parameters and semiconductor process variations. One skilled in the art of SRAM design may understand how various design parameters may be determined to effect a change in NFET threshold voltages (Vt)504.

FIG. 6illustrates multiple design structures600including an input design structure620that is preferably processed by a design process. Design structure620may be a logical simulation design structure generated and processed by design process610to produce a logically equivalent functional representation of a hardware device. Design structure620may alternatively include data or program instructions that, when processed by design process610, generate a functional representation of the physical structure of a hardware device. Whether representing functional or structural design features, design structure620may be generated using electronic computer-aided design, such as that implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure620may be accessed and processed by one or more hardware or software modules within design process610to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown inFIGS. 3 and 4. As such, design structure620may include files or other data structures including human or machine-readable source code, compiled structures, and computer-executable code structures that, when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language design entities or other data structures conforming to or compatible with lower-level HDL design languages such as Verilog and VHDL, or higher level design languages such as C or C++.

Design structure690may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g., information stored in a GDSII, GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure690may comprise information such as symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown inFIGS. 3 and 4. Design structure690may then proceed to a state695where, for example, design structure690proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.

Although the present invention has been described in terms of specific embodiments, it is anticipated that alterations and modifications thereof may become apparent to those skilled in the art. Therefore, it is intended that the following claims be interpreted as covering all such alterations and modifications as fall within the true spirit and scope of the invention.