Semiconductor device structure and method for forming the same

A method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes forming a first mask layer covering the gate stack, forming a contact alongside the gate stack and the first mask layer, recessing the contact, etching the first mask layer, and forming a second mask layer covering the contact and a portion of the first mask layer.

BACKGROUND

As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin vertical “fin” (or fin structure) extending from a substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over the fin. The advantages of a FinFET may include reducing the short channel effect and providing a higher current flow.

DETAILED DESCRIPTION

Further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.

Fin structures described below may be patterned by any suitable method. For example, the fins may be patterned using one or more lithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine lithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

Embodiments of forming a semiconductor device structure are provided. The method for forming the semiconductor device structure may include forming a first mask layer covering the gate stack, etching the first mask layer, and forming a second mask layer covering the source/drain contact and a portion of the first mask layer. The second mask layer may protect the first mask layer during the subsequent etching process for forming a gate via. As a result, the via-to-gate overlay window and the time-dependent dielectric breakdown (TDDB) window of the semiconductor device may be improved, which enhances the reliability of the semiconductor device.

FIG. 1is a perspective view of a semiconductor device structure100, in accordance with some embodiments of the disclosure. A semiconductor device structure100is provided, as shown inFIG. 1, in accordance with some embodiments. The semiconductor device structure100is a FinFET device structure, in accordance with some embodiments. The formation of the semiconductor device structure100includes providing a substrate102, and forming fin structures104and an isolation structure103on the substrate102, in accordance with some embodiments. The isolation structure103surrounds the fin structures104, in accordance with some embodiments.

In some embodiments, the substrate102is a semiconductor substrate such as a silicon substrate. In some embodiments, the substrate102includes an elementary semiconductor such as germanium; a compound semiconductor such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Furthermore, the substrate102may optionally include an epitaxial layer (epi-layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and/or have other suitable enhancement features.

The fin structures104are arranged in the Y direction and extend in the X direction, in accordance with some embodiments. In some embodiments, the formation of the fin structures104includes recessing the substrate102to form trenches. In some embodiments, the fin structures104are formed protruding from between the trenches.

Afterward, the trenches are filled with an insulating material for the isolation structure103, in accordance with some embodiments. The insulating material is also formed over the upper surfaces of the fin structures104, in accordance with some embodiments. In some embodiments, the insulating material includes silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, and/or a combination thereof. In some embodiments, the insulating material is formed using chemical vapor deposition (CVD) such as low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), or high density plasma CVD (HDP-CVD), high aspect ratio process (HARP), flowable CVD (FCVD)); atomic layer deposition (ALD); another suitable method, and/or a combination thereof.

The insulating material over the upper surfaces of the fin structures104is removed to expose the upper surfaces of the fin structures104, for example, using chemical mechanical polishing (CMP), in accordance with some embodiments. Afterward, the insulating material is recessed to expose an upper portion of the sidewalls of the fin structures104and forms the isolation structure103surrounding lower portions of the fin structures104, in accordance with some embodiments.

In some embodiments, the semiconductor device structure100is formed using a gate-late process. For example, dummy gate structures including dummy gate dielectric layers and dummy gate electrode layers (not shown) may be formed across the fin structures104in the place where gate stacks are to be formed.

The formation of the semiconductor device structure100further includes forming gate spacer layers118along opposite sides of the dummy gate structures, in accordance with some embodiments. In some embodiments, the gate spacer layer118is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), and/or a combination thereof.

The formation of the semiconductor device structure100further includes forming source/drain features106on the fin structures104, in accordance with some embodiments. The source/drain features106are formed on the opposite sides of the dummy gate structures, in accordance with some embodiments. In some embodiments, the source/drain features106on the adjacent fin structures104merge to form a continuous source/drain feature106, as shown inFIG. 1. In some embodiments, the source/drain features106on the adjacent fin structures do not merge together and remain separate source/drain features.

The formation of the source/drain features106includes recessing the fin structures104to form source/drain recesses on opposite sides of the dummy gate structures, in accordance with some embodiments. The recesses may have bottom surfaces that are located at a level substantially the same as or lower than the upper surface of the isolation structure103. Afterward, the source/drain features106are grown in the source/drain recesses using an epitaxial growth process, in accordance with some embodiments.

In some embodiments, the source/drain features106are made of any suitable material for an n-type semiconductor device and a p-type semiconductor device, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof. In some embodiments, the source/drain features106are in-situ doped during the epitaxial growth process. For example, the source/drain features106may be the epitaxially grown SiGe doped with boron (B). For example, the source/drain features106may be the epitaxially grown Si doped with carbon to form silicon:carbon (Si:C) source/drain features, phosphorous to form silicon:phosphor (Si:P) source/drain features, or both carbon and phosphorous to form silicon carbon phosphor (SiCP) source/drain features.

The formation of the semiconductor device structure100further includes forming a lower interlayer dielectric (ILD) layer108over the substrate102, in accordance with some embodiments. The lower ILD layer108covers the isolation structure103, the fin structures104, and the source/drain features106, in accordance with some embodiments. In some embodiments, the upper surface of the lower ILD layer108is substantially coplanar with the upper surfaces of the dummy gate structures.

In some embodiments, the lower ILD layer108is made of a dielectric material, such as un-doped silicate glass (USG), or doped silicon oxide such as borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and/or another suitable dielectric material. In some embodiments, the ILD layer is formed using CVD (such as HDP-CVD, PECVD, or HARP), ALD, another suitable method, and/or a combination thereof. In some embodiments, after the dielectric material for lower ILD layer108is formed, the dielectric material over the dummy gate structures are removed using such as CMP, until the upper surfaces of the dummy gate structures are exposed.

The dummy gate structures are replaced with gate stacks110, in accordance with some embodiments. The replacement process may include removing the dummy gate structures using one or more etching process to form trenches, and forming the gate stacks110in the trenches. The gate stacks110extend across the fin structures104, in accordance with some embodiments. The gate stacks110are arranged in the X direction and extend in the Y direction, in accordance with some embodiments.

In some embodiments, each gate stack110includes an interfacial layer (not shown inFIG. 1but inFIG. 2A-1), a gate dielectric layer114formed on the interfacial layer, and a gate electrode layer116formed on the gate dielectric layer114. In some embodiments, the interfacial layer is made of silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed on the exposed surface of the fin structures104by chemical oxidation, thermal oxidation, ALD, CVD, and/or another suitable method.

In some embodiments, the gate electrode layer116includes a conductive material, such as doped semiconductor, a metal, metal alloy, or metal silicide. In some embodiments, the gate electrode layer116includes a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal fill layer, and/or another suitable layer. The gate electrode layer116may be made of doped polysilicon, doped poly-germanium, Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, another suitable conductive material, or multilayers thereof. The gate electrode layer116may be formed by ALD, PVD, CVD, e-beam evaporation, or another suitable process. Further, the gate stack110may be formed separately for N-FET and P-FET transistors which may use different gate electrode materials and/or different work function materials.

A semiconductor device structure200is provided, as shown inFIGS. 2A-1 and 2A-2, in accordance with some embodiments. The semiconductor device structure200is similar to the semiconductor device structure100ofFIG. 1.FIG. 2A-1also shows an interfacial layer112of the gate stack110formed on the fin structure104, in accordance with some embodiments.

The gate spacer layers118and the gate stacks110are recessed to form trenches120, as shown inFIGS. 2B-1 and 2B-2, in accordance with some embodiments. The recessing process may include one or more etching processes, such as dry etching and/or wet etching. The recessed gate spacer layers118and the recessed gate stacks110are denoted as gate spacer layers119and gate stacks111, respectively, in accordance with some embodiments. The gate spacer layer119has an inner sidewall facing the gate stack111and an outer sidewall facing away from the gate stack111, in accordance with some embodiments. In some embodiments, the inner sidewall or the gate spacer layer119has a curved upper portion that is connected to the outer sidewall of the gate spacer layer119.

The top of the gate spacer layer119is higher than the upper surface of the gate stack111, in accordance with some embodiments. As such, the trench120has an upper portion above the top of the gate spacer layer119and a lower portion between the gate spacer layer119, and the upper portion is wider than the lower portion, in accordance with some embodiments.

The trenches120are filled with first mask layers122, as shown inFIGS. 2C-1 and 2C-2, in accordance with some embodiments. Each first mask layer122is formed directly above and covers a single gate stack111and two neighboring gate spacer layers119, in accordance with some embodiments. In some embodiments, the upper surface of the first mask layer122is substantially coplanar with the upper surface of the lower ILD layer108. The first mask layer122has an upper portion above the top of the gate spacer layer119and a lower portion between the gate spacer layer119, and the upper portion is wider than the lower portion, in accordance with some embodiments. In some embodiments, the first mask layer122has outermost sidewalls (or edges) that are substantially aligned with the opposite outer sidewalls of two gate spacer layers119facing away from the gate stack111.

In some embodiments, the first mask layers122are made of an insulating material such as a dielectric material (e.g., SiC, LaO, AlO, AlON, ZrO, HfO, SiN, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, or SiO); or undoped silicon (Si). In some embodiments, the formation of the first mask layers122includes depositing an insulating material for the first mask layers122in the trenches120and over the upper surface of the lower ILD layer108. In some embodiments, the deposition process may be CVD (such as HDP-CVD, PECVD, or HARP), ALD, another suitable method, and/or a combination thereof. In some embodiments, afterward, the insulating material over the upper surface of the lower ILD layer108is removed using such as CMP or etching-back process until the upper surface of the lower ILD layer108is exposed.

Portions of the lower ILD layer108formed directly above the source/drain features106are removed to form contact openings124, as shown inFIGS. 2D-1 and 2D-2, in accordance with some embodiments. It is noted that the source/drain features106are located behind the cross-section view ofFIG. 2D-1and depicted by dashed lines. The contact openings124expose the upper surfaces of the source/drain features106, in accordance with some embodiments. The contact openings124also expose portions of the outermost sidewalls of the first mask layers122, in accordance with some embodiments. The contact openings124also expose portions of the outer sidewalls of the gate spacer layers119facing away from the gate stacks111, in accordance with some embodiments. The contact openings124has a dimension may be less than the dimension of source/drain features106, as measured in the Y direction.

The removal process may include forming a patterned mask layer (such as photoresist layer and/or hard mask layer, not shown) on the lower ILD layer108and the first mask layer122. The patterned mask layer may have patterns (e.g., openings) corresponding to the contact openings124. The portions of the lower ILD layer108exposed from the openings of the patterned mask layer may be etched away. The etch processes may include a reactive ion etch (RIE), neutral beam etch (NBE), inductive coupled plasma (ICP) etch, the like, or a combination thereof. The etch processes may be anisotropic. Afterward, the patterned mask layer may be removed.

Contact liners126are conformally formed along the sidewalls of the contact openings124, as shown inFIGS. 2E-1 and 2E-2, in accordance with some embodiments. That is, the contact liners126are conformally formed along the respective exposed sidewalls of the first mask layers122, the gate spacer layers119, and the lower ILD layer108, in accordance with some embodiments. The contact openings124are partially filled by the contact liners126, in accordance with some embodiments.

In some embodiments, the contact liners126are made of an insulating material such as a dielectric material (e.g., SiC, LaO, AlO, AlON, ZrO, HfO, SiN, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, or SiO); or undoped silicon (Si). In some embodiments, the formation of the contact liners126includes conformally depositing an insulating material for the contact liners126along the sidewalls and the bottom surface of the contact openings124, the upper surface of the lower ILD layer108, and the upper surface of the first mask layer122. The deposition process may be CVD (such as HDP-CVD, PECVD, or HARP), ALD, another suitable method, and/or a combination thereof. Afterward, the insulating material along the bottom surface of the contact openings124, the upper surface of the lower ILD layer108, and the upper surface of the first mask layer122are removed using etching process such as an anisotropic etching. The etching process may be performed without a patterned mask layer.

Source/drain contacts128are formed in the remaining portions of the contact openings124and land on the source/drain features106, as shown inFIGS. 2E-1 and 2E-2, in accordance with some embodiments. The source/drain contacts128are surrounded by the contact liners126, in accordance with some embodiments. The source/drain contacts128are formed alongside the gate stacks111, the gate spacer layers119, the first mask layers122, and the lower ILD layer108, in accordance with some embodiments. The source/drain contact128has an upper surface substantially coplanar with the upper surface of the contact liner126, the upper surface of the lower ILD layer108, and the upper surface of the first mask layer122, in accordance with some embodiments.

In some embodiments, the source/drain contacts128are made of one or more conductive materials, for example, cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), cupper (Cu), aluminum (Al), ruthenium (Ru), molybdenum (Mo), TiN, TaN, and/or a combination thereof. Each source/drain contact128may include a silicide layer, such as WSi, NiSi, TiSi or CoSi, formed on the exposed upper surface of the source/drain feature106.

In some embodiments, the formation of the source/drain contacts128includes depositing a conductive material for source/drain contacts128in the contact openings124and over the upper surface of the lower ILD layer108and the upper surfaces of the first mask layers122. In some embodiments, the conductive material is deposited using CVD, PVD, e-beam evaporation, ALD, electroplating (ECP), electroless deposition (ELD), another suitable method, or a combination thereof. In some embodiments, a planarization process such as CMP is performed on the conductive material until the upper surface of the lower ILD layer108and the upper surfaces of the first mask layer122are exposed.

The source/drain contacts128may have a multi-layer structure including, for example, liner layers, seed layers, adhesion layers, barrier layers, and the like. In some embodiments, the conductive material for the source/drain contacts128is formed using a selective deposition technique such as cyclic CVD process or ELD process, and therefore it is not necessary to form glue layer in the contact opening124before depositing the conductive material. In some embodiments, if the conductive material for the source/drain contacts128does not easily diffuse into the dielectric material (such as the ILD layer108and the first mask layers122), the barrier layer may be omitted.

The source/drain contacts128are recessed to form recesses130, as shown inFIGS. 2F-1 and 2F-2, in accordance with some embodiments. The recessing process may include an etching process, such as dry etching or wet etching. The recessed source/drain contacts128are denoted as source/drain contacts129, in accordance with some embodiments. The recesses130expose upper portions of the inner sidewalls of the contact liners126facing the source/drain contacts129, in accordance with some embodiments. In some embodiments, the exposed upper surface of the source/drain contact129(i.e., the bottom surface of the recess130) is located at a higher level than the top (or the upper surface) of the gate spacer layer119, in accordance with some embodiments.

An etching process is performed on the semiconductor device structure200to laterally enlarge the recesses130, in accordance with some embodiments. The enlarged recesses130are denoted as recesses131, as shown inFIGS. 2G-1 and 2G-2, in accordance with some embodiments. The etching process is an isotropic etching process, in accordance with some embodiments. For example, the etching process may be a wet etching or a dry chemical etching without the need for a lithography step. That is, in some embodiments, no patterned masking element formed above the lower ILD layer108and the first mask layers122is used in the etching process. The contact liners126and the first mask layer122are laterally etched from the recesses130during the etching process, in accordance with some embodiments. The recesses131pass through upper portions of the contact liners126, in accordance with some embodiments. The recesses131extend into the first mask layers122from the outermost sidewalls of the first mask layers122facing the source/drain contacts129, in accordance with some embodiments. The recessed contact liners126are denoted as contact liners127, in accordance with some embodiments. In some embodiments, the source/drain contacts129are substantially not further recessed during the etching process.

In some embodiments, before the etching process for enlarging the recesses130, a patterned mask layer having openings corresponding to the recesses131is formed over the semiconductor structure200. The etching process may be performed using the patterned mask layer.

FIG. 2G-3is a portion of the cross-sectional view ofFIG. 2G-1, in accordance with some embodiments. The recess131has an upper portion131U and a lower portion131L, as shown inFIG. 2G-3, in accordance with some embodiments. The upper portion131U is located above the contact liners127, and the lower portion131L is located between the contact liners127, in accordance with some embodiments. The upper portion131U is wider than the source/drain contact129and has an upwardly increasing width, in accordance with some embodiments. The lower portion131L and the source/drain contact129are substantially equal in width, in accordance with some embodiments. Laterally recessing the upper portions of the contact liner126and the first mask layer122creates a concave surface on the first mask layer122and a protruding portion136of the first mask layer122directly below the concave surface of the first mask layer122, in accordance with some embodiments.

Furthermore, the upper portion131U of the recess131has a sidewall132(i.e., the concave surface of the first mask layer) with a convex profile, as shown inFIG. 2G-3, in accordance with some embodiments. The sidewall132extends from an edge134of the recess131to the lower portion131L, in accordance with some embodiments. In some embodiments, the convex profile of the sidewall132is nonlinear (e.g., curved). As a result, the recess131has a bowl shape, in accordance with some embodiments.

Furthermore, the recess131passes by above the outer sidewall119S1of the gate spacer layer119(facing away from the gate stack111), as shown inFIG. 2G-3, in accordance with some embodiments. That is, the edge134of the recess131is located within the area of the gate spacer layer119when viewed from the top view ofFIG. 2G-2, in accordance with some embodiments.

The trenches131are filled with second mask layers138, as shown inFIGS. 2H-1 and 2H-2, in accordance with some embodiments. Each second mask layer138is formed directly above and covers a single source/drain contact129and two neighboring contact liners127, in accordance with some embodiments. The second mask layer138also partially covers the first mask layer122, in accordance with some embodiments. The second mask layer138interfaces the first mask layer122at the concave surface of the first mask layer122, in accordance with some embodiments. The second mask layer138interfaces the source/drain contact129and the contact liner127, in accordance with some embodiments. The upper surface of the second mask layer138is substantially coplanar with the upper surface of the first mask layer122and the lower ILD layer108, in accordance with some embodiments.

FIG. 2H-3is a portion of the cross-sectional view ofFIG. 2H-1, in accordance with some embodiments. The second mask layer138has an upper portion138U and a lower portion138L, as shown inFIG. 2H-3, in accordance with some embodiments. The upper portion138U is located above the contact liners127, and the lower portion138L is located between the contact liners127, in accordance with some embodiments. The upper portion138U is wider than the source/drain contact129and has an upwardly increasing width, in accordance with some embodiments. The lower portion138L and the source/drain contact129are substantially equal in width, in accordance with some embodiments.

Furthermore, the upper portion138U of the second mask layer138has a protruding portion144, as shown inFIG. 2G-3, in accordance with some embodiments. The protruding portion144of the second mask layer138is located directly above and covers the protruding portion136of the first mask layer122, in accordance with some embodiments. The protruding portion144of the second mask layer138has a surface144S with a convex profile, in accordance with some embodiments. The convex surface144S of the second mask layer138is mated with the concave surface of the first mask layer, in accordance with some embodiments. The surface144S extends from an edge146of the second mask layer138to the lower portion138L, in accordance with some embodiments. In some embodiments, the convex profile of the surface144S is nonlinear (e.g., curved). As a result, the second mask layer138has a bowl shape, in accordance with some embodiments.

Furthermore, the protruding portion144of the second mask layer138passes by above the outer sidewall119S1of the gate spacer layers119(facing away from the gate stack111), as shown inFIG. 2G-3, in accordance with some embodiments. That is, the edge146of the second mask layer138is located within the area of the gate spacer layer119when viewed from the top view ofFIG. 2H-2, in accordance with some embodiments.

Furthermore, the lower portion138L of the second mask layer138extends downwardly between the contact liners127, in accordance with some embodiments. In some embodiments, the bottom surface138B of the second mask layer138is located at a level equal to or higher than the top of the gate spacer layer119. In some embodiments, the higher the level of the bottom surface138B of the second mask layer138(i.e., the higher the level of the upper surface of the source/drain contact129) the shorter the source/drain via formed subsequently, thereby reducing the resistance of the subsequently formed source/drain via.

In some embodiments, the protruding portion144of the second mask layer138is used to protect the protruding portion136of the first mask layer122during the following etching process. In some embodiments, the second mask layers138are made of a different insulating material than the first mask layer122, in particular, an insulating material having a different etching selectivity than the first mask layer122. In some embodiments, the second mask layer138are made of an insulating material such as a dielectric material (e.g., SiC, LaO, AlO, AlON, ZrO, HfO, SiN, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, or SiO); or undoped silicon (Si). In some embodiments, the formation of the second mask layer138includes depositing an insulating material for the second mask layer138in the trenches131and over the upper surface of the lower ILD layer108and the upper surfaces of the first mask layers122. In some embodiments, the deposition process may be CVD (such as HDP-CVD, PECVD, or HARP), ALD, another suitable method, and/or a combination thereof. In some embodiments, afterward, the insulating material over the upper surface of the lower ILD layer108is removed using such as CMP or etching-back process until the upper surface of the lower ILD layer108is exposed.

An etching stop layer148is formed over the upper surface of the lower ILD layer108, the upper surfaces of the first mask layers122, and the upper surfaces of the second mask layers138, as shown inFIGS. 2I-1, 2I-2, and 2I-3, in accordance with some embodiments. In some embodiments, the etching stop layer148is made of an insulating material such as a dielectric material (e.g., SiC, LaO, AlO, AlON, ZrO, HfO, SiN, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, or SiO); or undoped silicon (Si). In some embodiments, the etching stop layer148is formed using CVD (such as LPCVD, PECVD, HDP-CVD, HARP, and FCVD), ALD, another suitable method, or a combination thereof.

Gate via152is formed through the upper ILD layer150, the etching stop layer148, and the first mask layer122and lands on the gate stack111, as shown inFIGS. 2I-1 and 2I-3, in accordance with some embodiments. Source/drain vias154are formed through the upper ILD layer150, the etching stop layer148, and the second mask layer138sand land on the source/drain contacts129, as shown inFIGS. 2I-2 and 2I-3, in accordance with some embodiments. After the gate via152and the source/drain via154are formed, a semiconductor device is produced.

In some embodiments, the formation of the gate via152includes patterning the upper ILD layer150, the etching stop layer148, and the first mask layer122to form a via hole exposing the gate stack111. In some embodiments, the formation of the source/drain via154includes patterning the upper ILD layer150, the etching stop layer148, and the second mask layer138to form a via hole exposing the source/drain contact129. In some embodiments, the steps of forming the via holes the gate via152and the source/drain via154includes forming a patterned mask layer (not shown) on the upper ILD layer150, and etching the upper ILD layer150, the etching stop layer148, the first mask layer122and the second mask layer138uncovered by the patterned mask layer.

For example, a photoresist may be formed on the upper ILD layer150, such as by using spin-on coating, and patterned with a pattern corresponding to the via holes by exposing the photoresist to light using an appropriate photomask. Exposed or unexposed portions of the photo resist may be removed depending on whether a positive or negative resist is used. The pattern of the photoresist may then be transferred to the upper ILD layer150, the etching stop layer148, the first mask layer122and the second mask layer138, such as by using one or more suitable etch processes. The photoresist may be removed in an ashing or wet strip process, for example.

For example, a hard mask layer may be formed on the upper ILD layer150. The hard mask layer may include, or be formed of, a nitrogen-free anti-reflection layer (NFARL), carbon-doped silicon dioxide (e.g., SiO2:C), titanium nitride (TiN), titanium oxide (TiO), boron nitride (BN), a multilayer thereof, or another suitable material. The hard mask layer may be patterned using photolithography and etching processes described above to have a pattern corresponding to the via holes. The hard mask layer may transfer the pattern to the upper ILD layer150, the etching stop layer148, the first mask layer122and the second mask layer138to form the via holes which may be by using one or more suitable etch processes.

The etch processes may include a reactive ion etch (RIE), neutral beam etch (NBE), inductive coupled plasma (ICP) etch, the like, or a combination thereof. The etch processes may be anisotropic. Furthermore, the etching processes for forming the via hole of the gate via152and the via hole of the source/drain via154are performed separately, e.g., using different etchants, in accordance with some embodiments.

In some embodiments, one or more conductive materials for the gate via152and the source/drain via154fill the via holes and/or is formed over the upper surface of the upper ILD layer150. In some embodiments, the one or more conductive materials are deposited using CVD, PVD, e-beam evaporation, ALD, ECP, ELD, another suitable method, or a combination thereof. In some embodiments, a planarization process such as CMP is performed on the one or more conductive materials until the upper surface of the upper ILD layer150is exposed.

The gate via152and the source/drain via154each may have a multi-layer structure including, for example, liner layers, seed layers, adhesion layers, barrier layers, and the like. In some embodiments, the conductive material for the gate via152and the source/drain via154is formed using a selective deposition technique such as cyclic CVD process or ELD process, and therefore it is not necessary to form glue layer in the via holes before depositing the conductive material. In some embodiments, if the conductive material for the gate via152and the source/drain via154does not easily diffuse into the dielectric material (such as the upper ILD layer150, the etching stop layer148, the first mask layers122, and the second mask layer138), the barrier layer may be omitted.

As the scale of the semiconductor devices continues to shrink, one of the design challenges of the semiconductor devices is to improve via-to-gate overlay window. The spacing S1is the distance between the gate via152and the source/drain contact129, as measured in the X direction, as shown inFIG. 2I-1, in accordance with some embodiments. If the gate via152is too close to the source/drain contact129(i.e., the spacing S1is too small), the time-dependent dielectric breakdown (TDDB) of the semiconductor device may become worse.

The protruding portion144of the second mask layer138covers the protruding portion136of the first mask layer122, and the second mask layer138is made of a material having a lower etching rate than the first mask layer122during the etching process for forming the gate via hole. As a result, the protruding portion144of the second mask layer138may protect the protruding portion136of the first mask layer122during the etching process for forming the gate via hole. After forming the via hole for the gate via152, the protruding portion136of the first mask layer122remains between the gate via152and the source/drain contact129, which may prevent the gate via152from being too close to the source/drain contact129(i.e., maintaining the greater spacing S1). Therefore, the via-to-gate overlay window and the TDDB window of the semiconductor device may be improved, which may enhance the reliability of the semiconductor device.

FIG. 2Jis a cross-sectional view of a portion of the semiconductor device to illustrate the dimensions of some features of the semiconductor device. It is noted that the cross-sectional ofFIG. 2Jcuts through the source/drain feature106and the fin structure104. In some embodiments, the upper portion138U of the second mask layer138has a dimension D1from the upper surface of the second mask layer138to the upper surface (or the lowest point of the upper surface) of the contact liner127, as measured in the Z direction. In some embodiments, the dimension D1is in the range from about 0.5 nm to about 40 nm.

In some embodiments, the lower portion138L of the second mask layer138extends between the contact liners127by a dimension D2, as measured in the Z direction. In some embodiments, the dimension D2is less than about 50 nm.

In some embodiments, the lower portion138L of the second mask layer138has a dimension D3along the upper surface of the source/drain contact138, as measured in the X direction. In some embodiments, the dimension D3is in the range from about 3 nm to about 50 nm.

In some embodiments, the protruding portion144of the second mask layer138extends from an extending plane of an inner sidewall of the source/drain contact129facing the source/drain contact129to the edge146of the second mask layer138by a dimension D4, as measured in the X direction. In some embodiments, the dimension D4is in the range from about 0.5 nm to about 50 nm. The ratio of the dimension D4to the dimension D3is in a range from about 0.3 to about 9. If the ratio of the dimension D4to the dimension D3is too high, the landing area of the gate via152to gate stack111may be reduced. If the ratio of the dimension D4to the dimension D3is too low, the via-to-gate overlay window may be reduced because the second mask layer138may not sufficiently protect the first mask layer122.

In some embodiments, the upper portion of the first mask layer122has a dimension D5above the top of the gate spacer layer119, as measured in the Z direction. In some embodiments, the dimension D5is in the range from about 1 nm to about 40 nm.

In some embodiments, the protruding portion136of the first mask layer122has a dimension D6along an outer sidewall of the contact liner127facing away from the source/drain contact129, as measured in the Z direction. In some embodiments, the dimension D6is less than about 50 nm.

In some embodiments, the first mask layer122has a dimension D7from the edge146of the second mask layer138to the gate spacer layer119, as measured in the Z direction. In some embodiments, the dimension D7is less than 60 nm.

In some embodiments, the lower portion of the first mask layer122has a dimension D9along the upper surface of the gate stack111, as measured in the X direction. In some embodiments, the dimension D9is in the range from about 3 nm to about 50 nm.

In some embodiments, the first mask layer122has a dimension D10directly above the gate spacer layer119, as measured in the X direction. In some embodiments, the dimension D10is in the range from about 1 nm to about 40 nm.

In some embodiments, the gate spacer layer119has a dimension D8from the top of the gate spacer layer119to the edge of the inner sidewall119S2of the gate spacer layer119, as measured in the Z direction. In some embodiments, the dimension D8is less than about 10 nm.

In some embodiments, the contact liner127has a dimension D11, as measured in the X direction. In some embodiments, the dimension D11is less than about 30 nm.

FIG. 3is a portion of a cross-sectional view of a semiconductor device300which is a modification of the semiconductor device200ofFIG. 2I-1in accordance with some embodiments. The semiconductor device300is similar to the semiconductor device200ofFIG. 2I-1except the gate via, in accordance with some embodiments.

The semiconductor device300includes a gate via152A that is offset from the gate stack111and toward the source/drain contact129, in accordance with some embodiments. The gate via152A lands on a portion of the gate stack111and covers a portion of the second mask layer138, in accordance with some embodiments.

In some embodiments, during forming the gate via152A, a pattern (e.g., opening) of the patterned mask for forming the gate via152A corresponds to a portion of the gate stack111and a portion of the source/drain contact129. During the etching process for forming the via hole of the gate via152, the via hole passes through the upper ILD layer150, the etching stop layer148, and the first mask layer122to expose a portion of the gate stack111, in accordance with some embodiments. Because the etching rate of the second mask layer138is lower than the etching rate of the first mask layer122during the etching process, the via hole of the gate via152exposes and stops at the upper surface of the second mask layer138, in accordance with some embodiments. As such, the via hole of the gate via152does not pass through the second mask layer138and does not extend to the source/drain contact129.

The protruding portion144of the second mask layer138covers and protects the protruding portion136of the first mask layer122, thereby preventing the protruding portion136from being entirely removed by the etching process. After the etching process, the first mask layer122has a remaining portion136R between the gate via152A and the contact liner127. The remaining portion136R may prevent the gate via152from being too close to the source/drain contact129, and therefore the via-to-gate overlay window and the TDDB window of the semiconductor device may be improved, which may enhance the reliability of the semiconductor device. In some embodiments, the remaining portion136R has a dimension D12as measured in the X direction. In some embodiments, the dimension D12is less than about 20 nm.

Furthermore, the remaining portion136R of the first mask layer122may provide additional benefits. Because the remaining portion136R between the gate via152A and the contact liner127maintains the spacing S2between the gate via152A and the source/drain contact129, the source/drain contact129may be formed to have a greater thickness. That is, the dimension D2of the low portion138L of the second mask layer138may be reduced, or alternatively, the second mask layer138does not have a low portion138L. As a result, the source/drain via154(shown inFIG. 2I-2) landing on the source/drain contact129may be shorter, thereby reducing the resistance of the source/drain via154.

FIG. 4Ais a portion of a cross-sectional view of a semiconductor device400A which is a modification of the semiconductor device200ofFIG. 2I-1, in accordance with some embodiments. The semiconductor device400A is similar to the semiconductor device200ofFIG. 2I-1except for the second mask layer138, in accordance with some embodiments. The lower portion138L of the second mask layer138extends downwardly to a level that is below the top (or the upper surface) of the gate spacer layer119, as shown inFIG. 4A-1, in accordance with some embodiments. That is, the bottom surface138B of the second mask layer138is located at a level below the upper surface of the gate spacer layer119, in accordance with some embodiments.

FIG. 4Bis a portion of a cross-sectional view of a semiconductor device400B which is a modification of the semiconductor device400A ofFIG. 4A, in accordance with some embodiments. The semiconductor device400B is similar to the semiconductor device400A ofFIG. 4Aexcept that the gate via152A is offset toward the source/drain contact129, as shown inFIG. 4B, in accordance with some embodiments. The gate via152A lands on a portion of the gate stack111and covers a portion of the second mask layer138, in accordance with some embodiments. Because the second mask layer138may protect the first mask layer122during the etching process for forming the gate via hole, the via-to-gate overlay window and the TDDB window of the semiconductor device may be improved, which may enhance the reliability of the semiconductor device.

FIG. 4Cis a portion of a cross-sectional view of a semiconductor device400C which is a modification of the semiconductor device200ofFIG. 2I-1, in accordance with some embodiments. The semiconductor device400C is similar to the semiconductor device200ofFIG. 2I-1except the second mask layer138, in accordance with some embodiments. The second mask layer138has no lower portion extending between the contact liners127, as shown inFIG. 4C, in accordance with some embodiments. The bottom surface138B of the second mask layer138is located at substantially the same level as the upper surface of the contact liner127. As a result, the source/drain via154(as shown inFIG. 2I-2) landing on the source/drain contact129may be shorter, thereby reducing the resistance of the source/drain via154.

FIG. 4Dis a portion of a cross-sectional view of a semiconductor device400D which is a modification of the semiconductor device400C ofFIG. 4C, in accordance with some embodiments. The semiconductor device400D is similar to the semiconductor device400C ofFIG. 4Cexcept that the gate via152A is offset toward the source/drain contact129, as shown inFIG. 4Din accordance with some embodiments. The gate via152A lands on a portion of the gate stack111and covers a portion of the second mask layer138, in accordance with some embodiments. Because the second mask layer138may protect the first mask layer122during the etching process for forming the gate via hole, the via-to-gate overlay window and the TDDB window of the semiconductor device may be improved, which may enhance the reliability of the semiconductor device.

FIGS. 5A, 5B, and 5Care portions of a cross-sectional view of semiconductor devices500A,500B and500C which are modifications of the semiconductor device200ofFIG. 2I-1, in accordance with some embodiments.

The semiconductor device500A is similar to the semiconductor device200ofFIG. 2I-1except that the second mask layer138has a T-shape rather than a bowl shape, as shown inFIG. 5A, in accordance with some embodiments. The protruding portion144has two substantially flat surfaces144S1and144S2constituting a convex profile, in accordance with some embodiments. The surface144S1is substantially perpendicular to the surface144S2, in accordance with some embodiments.

The semiconductor device500B is similar to the semiconductor device200ofFIG. 2I-1except for the gate spacer layer119, as shown inFIG. 5B, in accordance with some embodiments. In some embodiments, the gate spacer layer119has a substantially flat outer sidewall119S1, a substantially flat inner sidewall119S2, and a substantially flat upper surface119S3connecting the outer sidewall119S1and the inner sidewall119S2.

The semiconductor device500C is similar to the semiconductor device500B ofFIG. 5Bexcept that the second mask layer138has a T-shape, as shown inFIG. 5C, in accordance with some embodiments. The protruding portion144has two substantially flat surfaces144S1and144S2constituting a convex profile, in accordance with some embodiments. The surface144S1is substantially perpendicular to the surface144S2, in accordance with some embodiments.

As described above, the method for forming a semiconductor device structure includes forming a gate stack111over a substrate102, forming a first mask layer122covering the gate stack111, forming a contact129alongside the gate stack111and the first mask layer122, recessing the contact129, etching the first mask layer122, and forming a second mask layer138covering the contact129and a portion of the first mask layer122. Because the second mask layer138may protect the first mask layer122during the subsequent etching process, the via-to-gate overlay window and the TDDB window of the semiconductor device may be improved, which may enhance the reliability of the semiconductor device.

Embodiments of a method for forming a semiconductor device structure are provided. The method for forming the semiconductor device structure may include forming a first mask layer covering the gate stack, forming a contact alongside the gate stack and the first mask layer, recessing the contact, etching the first mask layer, and forming a second mask layer covering the contact and a portion of the first mask layer. The second mask layer may protect the first mask layer during the subsequent etching process. As a result, the via-to-gate overlay window and the TDDB window of the semiconductor device may be improved, which may enhance the reliability of the semiconductor device.

In some embodiments, a method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes forming a gate stack over a substrate, forming a first mask layer covering the gate stack, forming a contact alongside the gate stack and the first mask layer, recessing the contact, and forming a second mask layer covering the contact and a portion of the first mask layer.

In some embodiments, a method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes forming gate stacks and a source/drain feature over a substrate. The gate stacks are located on opposite sides of the source/drain feature. The method for forming the semiconductor device structure also includes forming first mask layers over the gate stacks, forming a contact over the source/drain feature, recessing the contact to form a recess between the first mask layers, etching the first mask layers from the recess thereby forming an enlarged recess, and forming a second mask layer in the enlarged recess.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate, a source/drain feature alongside the gate stack, a first mask layer over the gate stack, a contact over the source/drain feature, and a second mask layer over the contact and alongside the first mask layer. The second mask layer has an upper portion partially covering the first mask layer. The semiconductor device structure also includes a via through the first mask layer and landing on the gate stack.