Semiconductor device and fabrication method

A semiconductor device, in which a semiconductor element is mounted on one side of a circuit board that is made up from an insulating layer and a wiring layer, includes metal posts provided on the side of the circuit board on which the semiconductor element is mounted; and a sealing layer provided on the side of the circuit board on which the semiconductor element is mounted such that the semiconductor element is covered and such that only portions of the metal posts are exposed.

This application is based upon and claims the benefit of priority from Japanese patent application No. 2007-105852, filed on Apr. 13, 2007, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device for realizing a package for stacked package SiP that is thinner and less prone to warp, and to a method of fabricating such a semiconductor device.

2. Description of the Related Art

SiP (System in Package) is receiving attention as a technology for achieving smaller electronic apparatuses having higher functionality. Within SiP, stacked-package SiP (PoP, Package on Package) provides an easy solution to the problem of ensuring that products are defect-free. In addition, stacked-package SiP allows a high degree of freedom in combining chips. As a result, orders for stacked-package SiP are increasing, particularly for portable telephones.

However, stacked-package SiP have the problem of higher assembly height than stacked-semiconductor element SiP in which a plurality of semiconductor elements are stacked in one package. Stacked-package SiP further have the problems of greater package warp and swelling due to the thinning of the interposer substrate and partial molding in which only sites for mounting semiconductor elements are molded.

FIG. 1is a sectional view showing a typical configuration of a lower package in stacked-package SiP. This package uses built-up circuit board11having core layer12as an interposer substrate. In this package, moreover, semiconductor element10, which is a chip, is connected by wire bonding to built-up circuit board11by bonding wires26. This package has a partially molded structure in which only the mounting site of semiconductor element10is sealed by sealing layer14.

Various techniques have been proposed as countermeasures for the height of attachment and package warp.

For example, JP-A-2003-133521 describes a technique for lowering the profile of the assembly. More specifically, JP-A-2003-133521 describes a technique in which a package is fabricated by, rather than mounting a chip on a substrate, providing an opening in the substrate, mounting a chip face-up on a support tape on the bottom of the opening, connecting the chip by wire bonding, implementing partial molding of the chip site, and finally, mounting balls.

Alternatively, JP-A-2005-45251 discloses a technique for fabricating a package by mounting a chip on a substrate, mounting solder balls as external electrodes, molding the entire surface, and then grinding a portion of the solder balls and chip reverse surface.

As a countermeasure for warp of the package, JP-A-2007-42762 discloses a technique of varying the heights of electrodes that are formed on a lower package and that are the connectors with an upper package in order to ensure connection reliability when warp occurs.

Although both lower profile of the assembly height and reduced warp of the package are sought in stacked-package SiP, these two objects are difficult to achieve simultaneously in stacked-package SiP.

In the technique disclosed in JP-A-2003-133521, the thickness of a package is reduced by providing openings in the substrate and mounting semiconductor elements in these openings. However, such a package adopts a partially molded construction only for semiconductor elements, and as a result, warp is difficult to suppress at the ends of the package that are not sealed by molding.

In the technique disclosed in JP-A-2005-45251, a construction in which the entire surface is sealed by molding is realized by mounting a semiconductor element and solder balls on a substrate and then molding the entire surface. However, the reverse surface of the semiconductor element is exposed by grinding, and although the thickness of the package can be reduced, warp in the region of the semiconductor element is difficult to suppress.

In the technique disclosed in JP-A-2007-42762, the problem of connection defects resulting from warp when stacking an upper and lower package is solved by adjusting the height of electrodes on the lower package. However, when reducing the thickness of a substrate to achieve assembly height of a lower profile, warp of the package is difficult to absorb by merely adjusting the height of electrodes. Lower profile of the assembly height and reduced warp are therefore difficult to achieve simultaneously.

SUMMARY OF THE INVENTION

An exemplary object of the present invention is to provide a semiconductor device that can simultaneously achieve a lower profile of assembly height and reduced warp and a method of fabricating such a semiconductor device.

A semiconductor device according to an exemplary aspect of the invention is a semiconductor device, in which a semiconductor element is mounted on one side of a circuit board that is made up from an insulating layer and a wiring layer, and which includes metal posts provided on the side of the circuit board on which the semiconductor element is mounted; and a sealing layer provided on the side of the circuit board on which the semiconductor element is mounted such that the semiconductor element is covered and such that only portions of the metal posts are exposed.

A method according to an exemplary aspect of the invention is a method of fabricating a semiconductor device which includes forming a circuit board composed of an insulating layer and a wiring layer on a metal body; forming a mask on a surface of the metal body that is opposite a surface of the metal body that contacts the circuit board; forming metal posts by removing a portion of the metal body using the mask; mounting a semiconductor element on the circuit board on which the metal posts have been formed; embedding the semiconductor element and the metal posts in a sealing layer; and exposing surfaces of the metal posts that are opposite surfaces that contact the circuit board by removing a portion of the sealing layer.

The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate an example of the present invention.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

The exemplary embodiments of the present invention are next described specifically with reference to the accompanying figures.

Semiconductor Device

FIG. 2is a sectional view showing an example of the construction of the semiconductor device according to the first exemplary embodiment of the present invention and a partial enlarged view of this semiconductor device.

Semiconductor device40shown inFIG. 2includes circuit board17. In circuit board17, lower-layer wiring18is electrically connected to upper layer wiring20by way of vias19. A plurality of metal posts24, semiconductor element10, and sealing layer14are provided on the lower-layer wiring18side of circuit board17. Semiconductor element10is covered by sealing layer14. Sealing layer14is also provided between the plurality of metal posts24. The surfaces of metal posts24, which are opposite the surfaces that contact circuit board17(only portions of metal posts24), are exposed. Sealing layer14is formed from an organic material that includes reinforcement material27.

According to the purposes of lower cost and ease of processing, copper is particularly suited as metal posts24. In the first exemplary embodiment, copper is used as metal posts24.

Regarding the shape of metal posts24, of the surfaces of metal posts24in the first exemplary embodiment, the area of the surfaces that contact circuit board17is greater than the area of the opposite surfaces, and the degree of contact between metal posts24and circuit board17is therefore high. As a result, sealing layer14can be easily processed even when sealing layer14is deposited in liquid or film form on metal posts24.

In the first exemplary embodiment, the shape of metal posts24is not limited to the shape shown inFIG. 2. In addition, at least one of a plurality of metal posts24is connected to lower-layer wiring18.

Semiconductor element10is electrically connected by way of solder balls15to circuit board17(more specifically, to lower-layer wiring18). This connection is realized as a flip-chip connection. The space between semiconductor element10and circuit board17is filled with underfill resin16.

Solder balls15are balls composed of a solder material. Solder balls15are attached on circuit board17by means of a plating method, ball transfer method, and printing method. Solder balls15are composed of lead-tin eutectic solder or lead-free solder.

Underfill resin16is made up from a material obtained by adding silica filler to an epoxy material. Underfill resin16decreases the difference between the thermal expansion coefficients of semiconductor element10and solder ball15, and underfill resin16therefore prevents damage to solder balls15. If solder balls15have sufficient rigidity to enable maintenance of high reliability, underfill resin16is unnecessary.

Regarding the bonding of circuit board17and semiconductor element10, a conductive paste or copper bumps may be used in place of solder balls15. In the first exemplary embodiment, solder balls15are used.

The method of connecting semiconductor element10and circuit board17is not limited to the method described above.

For example, semiconductor element10may be adhered to circuit board17by adhesive25as shown inFIG. 3, or, of the surfaces of semiconductor element10, the surface opposite the surface adhered to circuit board17may be connected to circuit board17(more specifically, lower-layer wiring18) by bonding wires26.

An organic material or silver paste may be used as adhesive25. Bonding wires26are composed of a material chiefly composed of gold and electrically connect the electrodes of both semiconductor element10and circuit board17.

Circuit board17is made up from, for example, at least one wiring layer and insulating layer, as shown inFIG. 2.

InFIG. 2, insulating layer21is of one layer while the wiring layers are the two layers: upper-layer wiring20and lower-layer wiring18, but the insulating layer and the wiring layers are not limited to this form, and the insulating layer and the wiring layers may be of a configuration made up from a required number of layers.

Insulating layer21of circuit board17is formed of, for example, an organic material that is photosensitive or non-photosensitive. A material such as epoxy resin, epoxy-acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), or polynorbornane resin may be used as the organic material. Alternatively, a material obtained by impregnating a woven fabric or a non-woven fabric formed from glass cloth or aramid fibers with epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole) or polynorbornane resin may be used as the organic material. In the first exemplary embodiment, a glass cloth impregnated with epoxy resin is used as the organic material.

At least one metal selected from the group composed of copper, silver, gold, nickel, aluminum, and palladium or an alloy that takes these metals as a chief component is used as lower-layer wiring18, upper-layer wiring20, and vias19that are included in circuit board17.

According to the standpoints of electrical resistance and cost, lower-layer wiring18, upper-layer wiring20, and vias19are preferably formed from copper.

In the first exemplary embodiment, lower-layer wiring18, upper-layer wiring,20, and vias19are formed from copper. A solder resist may be formed on insulating layer21such that a portion of upper-layer wiring20is exposed and the remaining portion of upper-layer wiring20is covered.

A portion of lower-layer wiring18in circuit board17having a surface on which metal posts24are provided may be level with insulating layer21or may be depressed with respect to insulating layer21.

When the surfaces are even, electrode pads (not shown) that are made up from lower-layer wiring18can be applied to narrow pitches in the wire bonding connection between circuit board17and semiconductor element10. In addition, the elimination of interference between the bonding wire tool and insulating layer21improves yield when making connections.

When the portion of lower-layer wiring18is depressed (seeFIG. 3), insulating layer21functions as a resist in the flip-chip connection of semiconductor element10. As a result, solder balls can be formed in only the depressed portions, thereby eliminating the need to separately provide a resist pattern for forming solder balls.

In addition, a capacitor may be provided in a desired position of circuit board17in order to serve as a noise filter of the circuit.

A metal oxide material such as titanium oxide, tantalum oxide, aluminum oxide (Al2O3), silicon dioxide (SiO2), zirconium oxide (ZrO2), hafnium oxide (HfO2), or niobium pentoxide (Nb2O5) is preferably used as the dielectric material that makes up the capacitor. Alternatively, a perovskite material such as BST (barium strontium titanate) (BaxSr1-xTiO3), PZT (lead zirconate titanate) (PbZrxTi1-xO3), or PLZT (Pb1-yLayZrxTi1-xO3), or a Bi-series layered compound such as SrBi2Ta2O9may be used as the dielectric material. Here, the values “x” and “y” satisfy the relations 0≦x≦1 and 0<y<1. In addition, an organic material in which an inorganic or magnetic material is mixed may also be used as the dielectric material that makes up the capacitor.

Any of glass, aramid, liquid crystal polymer, and PTFE (polytetrafluoroethylene) is used as sealing layer14. Alternatively, a material may be used as sealing layer14that is obtained by impregnating or laminating reinforcement material27composed of a plurality from among glass, aramid, liquid crystal polymer, and PTFE in an epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), or polynorbornane resin.

A low-cost process can be realized when reinforcement material27is glass. High water-vapor permeability can be achieved when reinforcement material27is aramid. Tensile strength and elastic modulus are improved when reinforcement material27is liquid crystal polymer. Heat resistance, shock resistance, and high insulation are improved when reinforcement material27is PTFE.

Reinforcement material27inFIG. 2is a woven fabric. Reinforcement material27inFIG. 5is a film. In either case, reinforcement material27does not contact metal posts24, but reinforcement material27may contact metal posts24without causing problems.

The inclusion of reinforcement material27in sealing layer14enables an increase in the rigidity of sealing layer14. When reinforcement material27is woven fabric, not only is the rigidity of sealing layer14increased, but surface variation of reinforcement material27can also be reduced and the ease of laser processing can be improved. When reinforcement material27is a non-woven fabric, not only is the rigidity of sealing layer14increased, but the water-vapor permeability of sealing layer14can also be increased. When reinforcement material27is a film, not only can the rigidity of sealing layer14be increased, but a thinner sealing layer14can also be achieved.

In the first exemplary embodiment, a glass woven fabric impregnated with epoxy resin is used as sealing layer14.

Sealing layer14is preferably formed of a material that improves the rigidity of semiconductor device40by a material having a high modulus of elasticity. Alternatively, sealing layer14is preferably formed of a material that results in a small difference in thermal expansion between sealing layer14and circuit board17to avoid deterioration of the union of sealing layer14and insulating layer21.

In addition, because sealing layer14can raise the rigidity of semiconductor device40, circuit board17can be made thinner, whereby a semiconductor device can be realized with a low profile and little warp.

According to the first exemplary embodiment, semiconductor element10and metal posts24are secured by sealing layer14that includes reinforcement material27. As a result, sealing layer14can increase the rigidity of semiconductor device40and realize reduced warp of semiconductor device40. Further, because sealing layer14can increase the rigidity of semiconductor device40, circuit board17can be made thinner. Using a thin substrate as circuit board17can realize semiconductor device40that has little warp, and moreover, that is thin.

FIG. 6is a sectional view showing an example of the construction of the semiconductor device according to the second exemplary embodiment of the present invention.

The semiconductor device according to the second exemplary embodiment includes circuit board17in which lower-layer wiring18is electrically connected to upper-layer wiring20by way of via19. A plurality of metal posts24, semiconductor element10, and sealing layer14are provided on the lower-layer wiring18side of circuit board17. Semiconductor element10is covered by sealing layer14. Sealing layer14is also provided between the plurality of metal posts24. Of the surfaces of metal posts24, the surfaces opposite the surfaces that contact circuit board17are exposed. Sealing layer14is formed of an organic material that includes reinforcement material27. Embedding material29is provided between reinforcement material27and semiconductor element10or metal posts24(around the peripheries of metal posts24).

FIG. 6is an enlarged view of the portion of metal posts24and reinforcement material27and embedding material29of the semiconductor device according to the second exemplary embodiment.

The following explanation regards the differences with respect to the semiconductor device according to the first exemplary embodiment. Parts that are not specifically described are the same as in the description of the semiconductor device according to the first exemplary embodiment.

Embedding material29is formed of an organic material that is photosensitive or non-photosensitive. The organic material is a material such as epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), and polynorbornane resin. Embedding material29does not include reinforcement material27.

In addition, embedding material29preferably has a lower modulus of elasticity than sealing layer14to function as a stress-relief layer.

In addition, the use of embedding material29can secure the outer periphery of metal posts24or semiconductor element10, and the other areas can be secured by sealing layer14. Adopting different resins for each area enables the selection of the optimum organic material for warp in each of the areas.

According to the second exemplary embodiment, semiconductor element10and metal posts24are indirectly secured by sealing layer14that includes reinforcement material27. As a result, the rigidity of semiconductor device40can be increased by sealing layer14, and lower warp of semiconductor device40can be realized.

In addition, circuit board17can be made thinner because sealing layer14can increase the rigidity of semiconductor device40. The use of a thin substrate as circuit board17enables the realization of a thin semiconductor device40with low warp.

The use of embedding material29provided between reinforcement material27and semiconductor element10or metal posts24with a less elastic resin than sealing layer14allows these components to function as a stress-relief layer, whereby the reliability of the semiconductor device as a separate entity and the reliability at the time of secondary packaging are improved.

The use of embedding material29allows the outer periphery of metal posts24or semiconductor element10to be secured by embedding material29and allows the other areas to be secured by sealing layer14. Adopting different resins for each of the areas enables selection of the ideal organic material for countering warp, whereby a further suppression of warp of the semiconductor device can be achieved.

FIG. 7is a sectional view showing an example of the construction of the semiconductor device according to the third exemplary embodiment of the present invention.

Semiconductor device40shown inFIG. 7includes circuit board17in which lower-layer wiring18is electrically connected to upper-layer wiring20by way of via19. A plurality of metal posts24, semiconductor element10, and sealing layer14are provided on the lower-layer wiring18side of circuit board17. Sealing layer14is provided between the plurality of metal posts24. Of the surfaces of metal posts24, the surfaces opposite the surfaces that contact circuit board17are exposed. Sealing layer14is formed of an organic material that includes reinforcement material27. Semiconductor element10is embedded in semiconductor element sealing layer30. Sealing layer14and semiconductor element sealing layer30function as sealing layers.

The following explanation regards the portions of semiconductor device40that differ from the first exemplary embodiment. Parts that are not specifically described are the same as described in the first exemplary embodiment.

Semiconductor element sealing layer30is formed of an organic material that is photosensitive or non-photosensitive. The organic material is, for example, epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), or polynorbornane resin. Semiconductor element sealing layer30is formed of a different material than sealing layer14. A reinforcement material (not shown) may be provided on the surface opposite the connection surface with circuit board17or on the outer periphery of semiconductor element10.

In addition, as shown in each ofFIGS. 8 and 9, semiconductor element sealing layer30may project above, or be depressed below sealing layer14.

When semiconductor element sealing layer30protrudes, semiconductor element10can be made thicker. Increasing the thickness of the resin of semiconductor element sealing layer30on semiconductor element10enables a reduction of warp on semiconductor element10.

Alternatively, when semiconductor element sealing layer30is depressed, semiconductor element10can be made thinner and the assembly height when connected with other semiconductor devices can be reduced.

According to the third exemplary embodiment, semiconductor element10and metal posts24are secured by sealing layer14that includes reinforcement material27. The rigidity of semiconductor device40can therefore be increased by sealing layer14, and lower warp of semiconductor device40can be achieved. In addition, sealing layer14increases the rigidity of semiconductor device40, whereby circuit board17can be made thinner. Using a thin substrate as circuit board17enables the realization of semiconductor device40that is both thin and has reduced warp.

Still further, using sealing layer14to seal metal posts24and using semiconductor element sealing layer30to seal semiconductor element10allows the selection of the optimum organic material for reducing warp in the respective areas, whereby a greater suppression of warp of the semiconductor device can be achieved.

In addition, the heights of semiconductor element sealing layer30and sealing layer14can be freely adjusted. When semiconductor element sealing layer30protrudes more than sealing layer14, semiconductor element10can be made thicker, and the rigidity of semiconductor element10can be improved. Increasing the resin thickness of semiconductor element sealing layer30on semiconductor element10can further reduce warp on semiconductor element10.

Alternatively, when semiconductor element sealing layer30is depressed, the solder balls of the semiconductor device that is connected on the upper side can be made a smaller diameter, whereby the assembly height can be further reduced.

FIG. 11is a sectional view showing the construction of the semiconductor device according to the fourth exemplary embodiment of the present invention.

In the semiconductor device shown inFIG. 11, a plurality of metal posts24, semiconductor element10, and sealing layer14are provided on the lower-layer wiring18side of circuit board17. Semiconductor element10is covered by sealing layer14. Sealing layer14is further provided between the plurality of metal posts24. Of the surfaces of metal posts24, the surfaces opposite the surfaces that contact circuit board17are exposed. The semiconductor device shown inFIG. 11has a configuration that includes two semiconductor devices that are stacked with these exposed surfaces connected to the other semiconductor device by way of an interposed connection material.

At least one of metal posts24is connected to lower-layer wiring18and functions as an external terminal part. The function as an external terminal should include at least the function of electrical connection to an external element.

InFIG. 11, the semiconductor device shown inFIG. 2is used as the lower semiconductor device, but any of the first to third exemplary embodiments may be used for this semiconductor device.

InFIG. 11, one semiconductor element10is mounted on each of the semiconductor devices, but a plurality of elements may be mounted.

Still further, two semiconductor devices are stacked inFIG. 11, but three or more semiconductor devices may be stacked.

Alternatively, a high heat-discharge semiconductor device may also be formed by not stacking semiconductor devices but rather, mounting heat sink32on metal posts24as shown inFIG. 12.

Heat sink32is made up from copper, nickel, aluminum, gold, silver, palladium, platinum, iron, stainless steel, zinc, magnesium, titanium, 42-alloy, chromium, vanadium, rhodium, molybdenum, or cobalt, or from a material of a plurality of these elements. According to the standpoints of cost and ease of processing, copper is particularly suitable as heat sink32. In the fourth exemplary embodiment, copper is used as heat sink32.

Heat sink32may further be formed with fins as shown inFIG. 12, or may be formed without fins. For connecting heat sink32and semiconductor device40, an adhesive layer (not shown) may be formed over the entire surface of semiconductor device40, or an adhesive layer (not shown) may be formed at points other than the exposed surfaces of metal posts24.

According to the fourth exemplary embodiment, semiconductor element10and metal posts24are secured by sealing layer14that includes reinforcement material27. As a result, the rigidity of semiconductor device40can be increased by sealing layer14and semiconductor device40with lower warp can be realized. Further, the rigidity of semiconductor device40can be increased by sealing layer14, whereby circuit board17can be made thinner.

Using a thin substrate as circuit board17enables the realization of semiconductor device40that is both thin and subject to less warp.

The stacked configuration of the semiconductor device has such advantages as allowing stacking of the semiconductor device in a plurality of levels, increasing the degree of freedom in the assembly of semiconductor elements, and increasing the flexibility of, for example, processing changes in memory capacity.

In addition, a high heat-discharge semiconductor device can be realized by mounting a heat sink.

Method of Fabricating the Semiconductor Device

FIGS. 13A to 13Lare sectional views showing the steps of a method of fabricating a semiconductor device according to the first exemplary embodiment of the present invention in order. This method is for fabricating a semiconductor device according to the first embodiment such as shown inFIG. 2.

First, as shown inFIG. 13A, metal body33is subjected to the processes of wet cleaning, dry cleaning, leveling, and roughening as necessary.

Metal body33is ultimately caused to function as metal posts24. Consequently, at least one metal selected from the group of copper, aluminum, nickel, stainless steel, iron, magnesium, and zinc, or an alloy that takes these metals as principal components is used as metal body33. The selection of copper as metal body33is particularly desirable according to the standpoints of electrical resistance and cost. Copper is used in the present embodiment.

A subtractive method is a method of obtaining a desired pattern by forming a resist of a desired pattern on a copper foil provided on the substrate, and, after etching unnecessary copper foil, stripping off the resist.

A semi-additive method is a method of obtaining a desired wiring pattern by forming a power-supply layer by an electroless plating method, a sputtering method, or a CVD (chemical vapor deposition) method, then forming a resist in which openings are provided in a desired pattern, depositing metal by an electroplating method in the resist openings, and then, after removing the resist, etching the power-supply layer.

A full-additive method is a method of obtaining a desired wiring pattern by adsorbing an electroless plating catalyst on a substrate, then forming a pattern by a resist, activating the catalyst with this resist left unchanged as an insulating film, and then depositing metal in the openings of the insulating film by an electroless plating method.

At least one metal selected from the group composed of, for example, copper, silver, gold, nickel, aluminum, and palladium, or an alloy that takes these metals as chief components is used as lower-layer wiring18. Lower-layer wiring18is preferably formed from copper according to the standpoints of electrical resistance and cost. In the present embodiment, copper is used.

Insulating layer21is formed of, for example, an organic material that is photosensitive or non-photosensitive. A material such as epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), or polynorbornane resin is used as the organic material. Alternatively, a woven fabric or non-woven fabric formed of glass cloth or aramid fibers that is impregnated with, for example, epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), or polynorbornane resin may be used as the organic material. In the present embodiment, a glass cloth impregnated with epoxy resin is used.

When insulating layer21is formed of a photosensitive material, via-holes34are formed by photolithography. When insulating layer21is a non-photosensitive material, or when insulating layer21is a photosensitive material but formed of a material having low pattern resolution, via-holes34are formed by a laser processing method, a dry etching method, or a blast method. In the present embodiment, a laser processing method is used.

Next, as shown inFIG. 13E, vias19are formed by filling the insides of via-holes34with at least one metal of the group composed of, for example, copper, silver, gold, nickel, aluminum, and palladium, or an alloy that takes these metals as chief components.

In the present embodiment, copper is used. The filling method is implemented by electroplating, electroless plating, printing, or a molten metal suction method.

Alternatively, a method may be employed in which conductor posts are formed in advance at the positions of vias19, following which insulating layer21is formed and the surface of insulating layer21then ground by polishing/grinding to expose the conductor posts and thus form vias19. Alternatively, vias19may be formed in the same step as upper-layer wiring20described hereinbelow.

Upper-layer wiring20is further formed on vias19by a method such as a subtractive method, a semi-additive method, or a full-additive method.

At least one metal selected from the group composed of, for example, copper, silver, gold, nickel, aluminum, and palladium, or an alloy that takes these metals as chief components is used as upper-layer wiring20. Upper-layer wiring20is preferably formed from copper, particularly according to the standpoints of electrical resistance and cost. In the present embodiment, a semi-additive method is used, and copper is employed for upper-layer wiring20.

Next, as shown inFIG. 13F, a pattern of solder resist22is formed on upper-layer wiring20.

Solder resist22is formed for producing the flame resistance and surface circuit protection of circuit board17. This material may be composed of an organic material such as an epoxy, acryl, urethane, or polyimide; and an inorganic or organic filler material may be used as an additive according to necessity. In addition, it is not necessary that solder resist22be provided on the circuit board.

Although an example was shown inFIG. 13Bin which circuit board17is formed starting from the formation of a wiring layer, circuit board17may also be formed starting from an insulating layer.

InFIG. 13, an example is shown in which circuit board17is composed of two conductive layers and one insulating layer, circuit board17may also be formed by repeating the above-described steps a number of times corresponding to the desired number of layers.

Next, as shown inFIG. 13G, metal post mask35, which is formed using at least one organic material or at least one metal material that differs from that of metal body33, is formed to a thickness of from 0.01 μm to 100 μm at desired positions at which metal posts24are to be provided on, of the surfaces of metal body33, the surface opposite the surface that contacts circuit board17.

If mask35is formed of an organic material, and if the organic material is in liquid form, mask35is laminated by means of a spin coating method, die coating method, curtain coating method, or printing method. If the organic material is a dry film, mask35is laminated by, for example, a lamination method.

After laminating the organic material, the organic material is cured by a process such as drying, following which the organic material is formed at desired positions at which metal posts24are to be provided by, for example, photo-processing if the organic material is photosensitive or by, for example, a laser processing method if the organic material is non-photosensitive.

When mask35is formed from a metal material, a plating resist is laminated on, of the surfaces of metal body33, the surface opposite the surface that contacts circuit board17.

If the plating resist is in liquid form, the plating resist is laminated by means of a spin coating method, a die coating method, a curtain coating method, or a printing method; and if the plating resist is a dry film, the plating resist is laminated by a lamination method.

After laminating the plating resist, the plating resist is cured by, for example, a drying process, following which openings in the plating resist are provided at desired positions at which metal posts24are to be provided by means of photo-processing if the plating resist is photosensitive or by means of a laser processing method if the plating resist is non-photosensitive.

A metal material that differs from that of metal body33is then deposited in the openings of the plating resist by means of a electroplating method or an electroless plating method, following which the plating resist is removed, whereby the metal material is formed at desired positions at which metal posts24are to be provided.

In the present embodiment, a metal material (nickel) is applied in mask35, a photosensitive liquid plating resist (trade name PMER P-LA900 manufactured by Tokyo Ohka Kogyo, Ltd.) is used for the plating resist, the plating resist is applied to metal body33by a spin coating method, openings are provided in the plating resist by photolithography, nickel is electroplated in the openings of the plating resist by an electroplating method, and the thickness was set to 10 μm.

Next, as shown inFIG. 13H, metal body33is subjected to an etching process using an etchant from the upper surface of mask35.

A dip method or a spray method is used as the etching method. In the present embodiment, a spray etching method was employed that uses an alkaline copper etchant having ammonia as a chief ingredient (trade name E-Process, manufactured by Meltex, Inc.).

Next, as shown inFIG. 13I, semiconductor element10is flip-chip connected to circuit board17by way of solder balls15on, of the surfaces of circuit board17, the surface opposite the surface on which metal posts24are formed.

Underfill resin16is then used to fill the space between semiconductor element10and circuit board17on which solder balls15are formed.

Underfill resin16is used with the object of reducing the difference in thermal expansion coefficients of semiconductor element10and solder balls15and preventing damage to solder balls15.

If solder balls15have sufficient strength to maintain the desired reliability, filling the space with underfill resin16is not necessary.

Solder balls15are micro-balls composed of a solder material and are formed by a plating method, ball transfer, and a printing method. The material of solder balls15can be selected as appropriate from lead-tin eutectic solder and lead-free solder materials.

Underfill resin16is formed from an epoxy material. Underfill resin16is applied after semiconductor element10is connected by means of solder balls15.

In addition, the connection between semiconductor element10and circuit board17may be implemented by bumps of a metal such as copper and not by micro-balls composed of a solder material.

Although the form of connecting semiconductor element10described inFIG. 13Iuses flip-chip connection, connection by means of wire bonding, or connection in which wires of the wiring board are directly connected to connection terminal parts of semiconductor element10without using bumps or wire bonding may also be used.

Any of glass, aramid, liquid crystal polymer, or PTFE is used as sealing layer14. Alternatively, a material in which reinforcement material27composed of a plurality of glass, aramid, liquid crystal polymer, and PTFE is impregnated in or laminated with epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), or polynorbornane resin may also be used as sealing layer14.

Sealing layer14is laminated by means of a method such as vacuum pressurization and vacuum lamination on metal posts24and semiconductor element10that is mounted.

When reinforcement material27is glass, a low-cost process can be realized. When reinforcement material27is aramid, high water-vapor permeability can be achieved. When reinforcement material27is a liquid crystal polymer, tensile strength and the modulus of elasticity are improved. When reinforcement material27is PTFE, heat resistance, shock resistance, and high insulation are improved.

Explanation next regards the method of laminating sealing layer14.

As shown inFIG. 14, semiconductor element area opening36and metal post area openings37are provided in advance on sealing layer14. Methods such as a laser, drilling, dry etching, and wet etching may be used as the method of forming the openings. In the present embodiment, a laser is used.

Next, as shown inFIG. 15, each of the substrates are stacked such that semiconductor element10and metal posts24on circuit board17are inserted into the semiconductor element area opening36and metal post area openings37on sealing layer14. In addition, sealing layer41that lacks openings and reinforcement material is stacked on sealing layer14. Sealing layer41that lacks openings and reinforcement material may also be stacked only on semiconductor element10.

Next, reinforcement material27can effectively be provided around semiconductor element10and metal posts24by the batch curing these stacked resin components.

Next, as shown inFIG. 13K, the surfaces of metal posts24opposite the surfaces that contact circuit board17are exposed from the surface of sealing layer14by grinding or polishing and these surfaces are made substantially level with the surface of sealing layer14.

Next, as shown inFIG. 13L, solder balls15are mounted on the surface of circuit board17that is opposite metal posts24.

According to the present embodiment, the semiconductor device of the first embodiment can be efficiently formed.

Semiconductor element10and metal posts24are secured by sealing layer14that includes reinforcement material27, whereby the rigidity of semiconductor device40can be increased by sealing layer14, and reduced warp of semiconductor device40is achieved.

In addition, sealing layer14can increase the rigidity of semiconductor device40. As a result, circuit board17can be made thinner. Using a thin substrate as circuit board17enables the realization of semiconductor device40that has little warp and moreover, that is thin.

FIG. 16Ashows semiconductor element10and metal posts24that are provided on circuit board17, andFIG. 16Bis an upper plan view of this construction.

FIG. 16Cis a sectional view for explaining the state when superposing and stacking sealing layer14that includes reinforcement material27in which are provided semiconductor element area opening36and metal post area opening37and sealing layer41that lacks openings and reinforcement material and that is arranged over sealing layer14on circuit board17shown inFIG. 16A, andFIG. 16Dis an upper plan view of this configuration.

FIG. 16Eis a sectional view following stacking, andFIG. 16Fis an upper plan view of this configuration.

FIG. 17is a sectional view showing a portion of the method of fabricating the semiconductor device according to the second exemplary embodiment of the present invention. The fabrication method of the present embodiment is for fabricating the semiconductor device of the second embodiment such as shown inFIG. 6.

The following explanation regards portions that differ from the first exemplary embodiment of the method of fabricating a semiconductor device. Parts that are not specifically described are the same as in the explanation of the first exemplary embodiment of the method of fabricating a semiconductor device.

Explanation first regards the method of stacking sealing layer14.

As shown inFIG. 17, semiconductor element area opening36and metal post area openings37are provided in sealing layer14in advance. The openings are formed using, for example, a laser, drill, dry etching, and wet etching. In the present embodiment, a laser is used.

Next, as shown inFIG. 17, each of the substrates are stacked such that semiconductor element10and metal posts24on circuit board17are inserted into semiconductor element area opening36and metal post area openings37on sealing layer14. In addition, embedding material29that differs from sealing layer14and that lacks openings and reinforcement material is stacked on sealing layer14.

Next, reinforcement material27can be effectively provided around semiconductor element10and metal posts24by the batch curing of these stacked resin parts, and embedding material29that differs from sealing layer14can be formed between semiconductor element10and metal posts24, and reinforcement material27.

According to the present embodiment, the semiconductor device of the second exemplary embodiment can be efficiently formed.

In addition, semiconductor element10and metal posts24are secured by sealing layer14that includes reinforcement material27. As a result, the rigidity of semiconductor device40can be increased by sealing layer14, and lower warp of semiconductor device40can be achieved. Still further, the increased rigidity of semiconductor device40enables the use of a thin substrate as circuit board17. The use of a thin substrate enables the realization of a semiconductor device having less warp, and moreover, that is thin.

Still further, by making embedding material29provided between reinforcement material27and semiconductor element10or metal posts24a less elastic resin than sealing layer14, these components function as a stress-relief layer, whereby the reliability of a semiconductor device as a single entity and the reliability in secondary packaging are improved.

In addition, by using embedding material29, the outer peripheries of semiconductor element10and metal posts24can be secured by embedding material29, and the remaining areas can be secured by sealing layer14. By making each area a different resin, the optimum organic material for preventing warp can be selected in each area to enable a further suppression of warp of the semiconductor device.

FIG. 18is a sectional view showing a portion of the method of fabricating the semiconductor device according to the third exemplary embodiment of the present invention. The fabrication method of this embodiment is for fabricating the semiconductor device according to the third exemplary embodiment such as shown inFIG. 7.

The following explanation regards the parts that differ from the first exemplary embodiment of the fabrication method of a semiconductor device. Parts that are not specifically described are the same as in the explanation of the first exemplary embodiment of the fabrication method of a semiconductor device.

As shown inFIG. 18A, semiconductor element10and metal posts24are provided on circuit board17.

Next, as shown inFIG. 18B, semiconductor element sealing layer30is laminated only in the area of semiconductor element10.

The material of semiconductor element sealing layer30is, for example, epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), or polynorbornane resin. Semiconductor element sealing layer30is provided using, for example, a transfer molding method, a compressed formation molding method, a printing method, a vacuum pressurization method, or vacuum lamination.

Next, as shown inFIG. 18C, sealing layer14is laminated only in the areas of metal posts24.

Metal post area openings37are provided in advance in sealing layer14. The openings are formed using, for example, a laser, drill, dry etching, or wet etching. In the present embodiment, a laser is used.

Each substrate is next stacked such that metal posts24on circuit board17are inserted in metal post area openings37on sealing layer14. In addition, sealing layer41that lacks openings and reinforcement material may either be stacked or not stacked.

Alternatively, sealing layer41that lacks openings and reinforcement material may be stacked in the area of semiconductor element10as shown inFIGS. 19A-19D. In addition, embedding material29may also be stacked.

The embedding of semiconductor element sealing layer30and metal posts24may also be in the reverse order.

According to the present embodiment, the semiconductor device of the third exemplary embodiment is efficiently formed.

In addition, semiconductor element10and metal posts24are secured by sealing layer14that includes reinforcement material27. As a result, the rigidity of semiconductor device40can be increased by sealing layer14and reduced warp of semiconductor device40can be achieved. In addition, the increase in the rigidity of semiconductor device40realized by sealing layer14allows the use of a thinner substrate as circuit board17, whereby a semiconductor device having reduced warp and of thinner form can be achieved.

In addition, sealing metal posts24by sealing layer14and sealing semiconductor element10by semiconductor element sealing layer30allows selection of the optimum organic material for preventing warp in each of the areas, whereby a further suppression of warp of the semiconductor device can be achieved.

In addition, the height of semiconductor element sealing layer30and sealing layer14can be freely adjusted. When semiconductor element sealing layer30projects above sealing layer14, semiconductor element10can be made thicker. Increasing the thickness of the resin of semiconductor element sealing layer30on semiconductor element10enables a reduction of warp on semiconductor element10. On the other hand, when semiconductor element sealing layer30is depressed below sealing layer14, semiconductor element10can be made thin and the assembly height when connected with another semiconductor device can be made lower.

FIG. 20is a sectional view showing a portion of the method of fabricating the semiconductor device according to the fourth exemplary embodiment of the present invention. The fabrication method of this embodiment is for fabricating the semiconductor device according to the fourth exemplary embodiment such as shown inFIG. 11.

The following explanation regards the parts that differ from the first exemplary embodiment of the fabrication method of a semiconductor device. Parts that are not specifically descried are the same as in the explanation of the first exemplary embodiment of the fabrication method of a semiconductor device.

In the fabrication method of a semiconductor device of the present embodiment, the semiconductor device according to the first to third exemplary embodiments is connected to another semiconductor device by way of metal posts24as shown inFIGS. 20A-20B.

Any of the semiconductor devices of the first to third exemplary embodiments may be used as the semiconductor device shown inFIG. 20. Solder balls15are provided on the upper semiconductor device at points that correspond to the exposed surfaces of metal posts24of the lower semiconductor device.

The upper semiconductor device is first stacked on the upper layer of the lower semiconductor device using mounting equipment. Alternatively, the lower semiconductor device may be packaged on a board and the upper semiconductor device then mounted.

Metal posts24of the lower semiconductor device function as external terminals. The function as external terminals should include at least the function of electrically connecting to an external element. At least one of metal posts24is connected to lower-layer wiring18.

Next, while maintaining this state, the assembly is introduced into a reflow furnace to apply a temperature of at least the melting point of solder balls15, whereby solder balls15are connected to metal posts24. A method may also be employed in which, instead of reflow, solder balls15are melted by the mounting equipment.

According to the present embodiment, the semiconductor device of the fourth exemplary embodiment is efficiently formed.

In addition, semiconductor element10and metal posts24are secured by sealing layer14that includes reinforcement material27. The rigidity of semiconductor device40can therefore be increased by sealing layer14and semiconductor device40having reduced warp is achieved. In addition, the increase in rigidity of semiconductor device40realized by sealing layer14enables the use of a thin substrate as circuit board17. The use of a thin substrate enables the realization of a semiconductor device that has reduced warp, and moreover, a thin form.

The present embodiment has various advantages such as enabling stacking of multiple layers of semiconductor devices, increasing the degree of freedom of combination of semiconductor elements, and raising the flexibility of processing for changes in memory capacity. In addition, a high heat-discharge semiconductor device can be realized by mounting a heat sink.

Each of the exemplary embodiments exhibits the following effects:

Sealant covers not only the site of mounting semiconductor element10but also the entire surface of circuit board17on which semiconductor element10is mounted. In this case, not only can the rigidity of the semiconductor device be maintained, but lower warp can also be realized.

In addition, when sealing layer14includes reinforcement material27, the overall rigidity of the semiconductor device is further improved, the unit reliability of a package is improved, and because the difference in thermal expansion of the package substrate (circuit board)17and semiconductor element10is decreased, the package reliability is also improved.

Further, because the rigidity of the semiconductor device is increased, high connection reliability with upper packages can be achieved when packages are stacked above the semiconductor device.

In addition, metal posts24provided in the semiconductor device can function not only as connection terminals, but also as a heat discharge path, whereby a high-heat discharge semiconductor device can be realized.

Still further, the increased rigidity of the semiconductor device brought about by sealing layer14allows a corresponding thinning of circuit board17. The use of a thin substrate as circuit board17allows the realization of a semiconductor device that both has low warp and is thin in form.

The method of fabricating the above-described semiconductor device uses a metal body, which is the support base of the thin substrate, as connection terminals. As a result, the need to newly form electrodes is eliminated, whereby lower cost can be achieved for a semiconductor device than for the stacked package SiP construction of the related art.

In addition, sealing layer14that includes reinforcement material27can be provided effectively at the peripheries of semiconductor element10and metal posts24.

In order to improve the handling ability of circuit board on which metal posts24are formed, part of the metal body that is the support base is left. The rigidity of circuit board17on which metal posts24are formed can therefore be maintained.

The sealing layer is preferably an organic material that includes reinforcement material.

The reinforcement material is preferably composed of any of glass, aramid, liquid crystal polymer, and PTFE, or composed of a plurality of these materials.

The reinforcement material is preferably a woven fabric.

The reinforcement material is preferably a non-woven fabric.

The reinforcement material is preferably a film.

The reinforcement material and the metal posts preferably do not contact.

The reinforcement material and metal posts preferably contact.

An embedding material is preferably provided at the periphery of the metal posts.

The sealing layer preferably includes a semiconductor element sealing layer that covers the semiconductor element.

Regarding the shape of the metal posts, the area of the surfaces of the metal posts that contact the circuit board is preferably greater than the area of the opposite surfaces of the metal posts.

A portion of the wiring layer of the circuit board of the surface on which the metal posts are provided is preferably lower than the insulating layer.

The connection between the semiconductor element and circuit board is preferably either flip-chip connection or wire bonding connection.

The connection between the semiconductor element and circuit board is preferably connection in which circuit board wiring is directly connected to connection terminal parts of the semiconductor element.

There is preferably a plurality of metal posts, any of the metal posts being preferably connected to a wiring layer and used as the connection parts with another semiconductor device.

The metal posts are preferably connected to a heat sink.

The embedding a semiconductor element and metal posts preferably includes: forming a semiconductor element area opening and metal post area openings in a sealing layer; stacking the sealing layer in which openings have been formed on a circuit board on which the semiconductor element and metal posts have been provided; and stacking a second sealing layer that lacks openings and reinforcement material on the sealing layer.

The embedding a semiconductor element and metal posts preferably includes: forming a semiconductor element area opening and metal post area openings in a sealing layer; stacking the sealing layer in which openings have been formed on a circuit board on which the semiconductor element and metal posts have been provided; and stacking an embedding material on the sealing layer.

The embedding a semiconductor element and metal posts preferably includes: embedding the semiconductor element in a semiconductor element sealing layer; and embedding the metal posts in a sealing layer.

The embedding the semiconductor element and metal posts preferably includes: embedding the metal posts in a sealing layer; and embedding the semiconductor element in a semiconductor element sealing layer.

Stacking a semiconductor device with the metal posts of the semiconductor device as electrical connection parts is preferably included.

An exemplary advantage according to the invention is the capability of providing both a semiconductor device that can simultaneously realize an assembly height having a lower profile and reduced package warp and a method of fabricating such a semiconductor device.