Vertical decoders

Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may include a doped material that may extend between a first conductive line and an access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells. The access line may be coupled with two decoders, in some cases.

BACKGROUND

The following relates generally to operating a memory array and more specifically to vertical decoders.

Memory devices are widely used to store information in various electronic devices such as computers, cameras, digital displays, and the like. Information is stored by programing different states of a memory device. For example, binary devices have two states, often denoted by a logic “1” or a logic “0.” In other systems, more than two states may be stored. To access the stored information, a component of the electronic device may read, or sense, the stored state in the memory device. To store information, a component of the electronic device may write, or program, the state in the memory device.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices may be volatile or non-volatile. Non-volatile memory cells may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory cells may lose their stored state over time unless they are periodically refreshed by an external power source.

Improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Improved solutions for saving space in the memory array, increasing the memory cell density, or decreasing overall power usage of the memory array may be desired.

DETAILED DESCRIPTION

Some memory devices may include one or more decoders coupled with the memory array. In some cases, the one or more decoders may each include doped materials formed in a specific orientation to reduce the array size of the die used by the one or more decoders. For example, the one or more decoders may include doped materials that extend in a direction that is non-parallel (e.g., perpendicular) a surface of a substrate. The doped material may extend from the conductive line of the one or more decoders to an access line associated with the memory array. In accordance with teachings herein, the one or more decoders may be coupled with the substrate and a side of the memory array and configured to apply a voltage to the access line of the memory array.

To save space and resources, the one or more decoders that each include vertical doped materials may be implemented as part of or in the self-selecting memory array. In some examples, the decoders may be examples of row decoders implemented to bias one or more word-lines or examples of column decoders implemented to bias one or more a bit-lines or both. For example, the memory device may include a first row decoder, a second row decoder, a first column decoder, a second column decoder, or a combination thereof. The decoders may be positioned above the memory array, below the memory array, or both. In such cases, the size of the memory array may be reduced based on the placement and/or orientation of the one or more decoders. In addition, the size (e.g., the resistance) of the one or more word-lines and one or bit-lines may also be reduced based on the placement of the one or more decoders. These and other techniques and advantages described herein may thus improve the size and density of the memory array. In some cases, the memory array may be an example of a self-selecting memory array. In some cases, a self-selecting memory array may be fabricated in a three-dimensional fashion and may include vertical memory cells.

Features of the disclosure introduced above are further described below in the context of a memory array. Specific examples are then described for operating the memory array related to vertical decoders in some examples. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and flowcharts that relate to techniques for vertical decoders.

FIG. 1illustrates an example of a memory device100as disclosed herein. Memory device100may also be referred to as an electronic memory apparatus.FIG. 1is an illustrative representation of various components and features of the memory device100. As such, it should be appreciated that the components and features of the memory device100shown to illustrate functional interrelationships, not their actual physical positions within the memory device100. In the illustrative example ofFIG. 1, the memory device100includes a three-dimensional (3D) memory array102. The 3D memory array102includes memory cells105that may be programmable to store different states. In some examples, each memory cell105may be programmable to store two states, denoted as a logic 0 and a logic 1. In some examples, a memory cell105may be configured to store more than two logic states. A memory cell105may, in some examples, include a self-selecting memory cell. Although some elements included inFIG. 1are labeled with a numeric indicator, other corresponding elements are not labeled, though they are the same or would be understood to be similar, in an effort to increase visibility and clarity of the depicted features.

The 3D memory array102may include two or more two-dimensional (2D) memory arrays103formed on top of one another. This may increase a quantity of memory cells that may be placed or created on a single die or substrate as compared with 2D arrays, which in turn may reduce production costs, or increase the performance of the memory device, or both. The memory array102may include two levels of memory cells105and may thus be considered a 3D memory array; however, the quantity of levels is not limited to two. Each level may be aligned or positioned so that memory cells105may be aligned (exactly, overlapping, or approximately) with one another across each level, forming a memory cell stack145. In some cases, the memory cell stack145may include multiple self-selecting memory cells laid on top of another while sharing an access line for both as explained below. In some cases, the self-selecting memory cells may be multi-level self-selecting memory cells configured to store more than one bit of data using multi-level storage techniques.

In some examples, each row of memory cells105is connected to an access line110, and each column of memory cells105is connected to a bit line115. Access lines110and bit lines115may be substantially perpendicular to one another and may create an array of memory cells. As shown inFIG. 1, the two memory cells105in a memory cell stack145may share a common conductive line such as a bit line115. That is, a bit line115may be in electronic communication with the bottom electrode of the upper memory cell105and the top electrode of the lower memory cell105. Other configurations may be possible, for example, a third layer may share an access line110with a lower layer. In general, one memory cell105may be located at the intersection of two conductive lines such as an access line110and a bit line115. This intersection may be referred to as a memory cell's address. A target memory cell105may be a memory cell105located at the intersection of an energized access line110and bit line115; that is, access line110and bit line115may be energized to read or write a memory cell105at their intersection. Other memory cells105that are in electronic communication with (e.g., connected to) the same access line110or bit line115may be referred to as untargeted memory cells105.

As discussed above, electrodes may be coupled to a memory cell105and an access line110or a bit line115. The term electrode may refer to an electrical conductor, and in some cases, may be employed as an electrical contact to a memory cell105. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of memory device100. In some examples, a memory cell105may include a chalcogenide material positioned between a first electrode and a second electrode. One side of the first electrode may be coupled to an access line110and the other side of the first electrode to the chalcogenide material. In addition, one side of the second electrode may be coupled to a bit line115and the other side of the second electrode to the chalcogenide material. The first electrode and the second electrode may be the same material (e.g., carbon) or different.

Operations such as reading and writing may be performed on memory cells105by activating or selecting access line110and bit line115. In some examples, access lines110may also be known as word lines110, and bit lines115may also be known digit lines115. References to access lines, word lines, and bit lines, or their analogues, are interchangeable without loss of understanding or operation. Activating or selecting a word line110or a bit line115may include applying a voltage to the respective line. Word lines110and bit lines115may be made of conductive materials such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductively-doped semiconductors, or other conductive materials, alloys, compounds, or the like.

Accessing memory cells105may be controlled through a row decoder120and a column decoder130. For example, a row decoder120may receive a row address from the memory controller140and activate the appropriate word line110based on the received row address. Similarly, a column decoder130may receive a column address from the memory controller140and activate the appropriate bit line115. For example, memory array102may include multiple word lines110, labeled WL_1through WL_M, and multiple digit lines115, labeled DL_1through DL N, where M and N depend on the array size. Thus, by activating a word line110and a bit line115, e.g., WL_2and DL_3, the memory cell105at their intersection may be accessed. As discussed below in more detail, accessing memory cells105may be controlled through a row decoder120and a column decoder130that may include one or more doped materials that extend in a direction away from a surface of a substrate coupled to the memory array102. In some cases, memory device100may include a set of row decoders120and a set of column decoders130.

Upon accessing, a memory cell105may be read, or sensed, by sense component125to determine the stored state of the memory cell105. For example, a voltage may be applied to a memory cell105(using the corresponding word line110and bit line115) and the presence of a resulting current may depend on the applied voltage and the threshold voltage of the memory cell105. In some cases, more than one voltage may be applied. Additionally, if an applied voltage does not result in current flow, other voltages may be applied until a current is detected by sense component125. By assessing the voltage that resulted in current flow, the stored logic state of the memory cell105may be determined. In some cases, the voltage may be ramped up in magnitude until a current flow is detected. In other cases, predetermined voltages may be applied sequentially until a current is detected. Likewise, a current may be applied to a memory cell105and the magnitude of the voltage to create the current may depend on the electrical resistance or the threshold voltage of the memory cell105.

In some examples, a memory cell may be programmed by providing an electric pulse to the cell, which may include a memory storage element. The pulse may be provided via a first access line (e.g., word line110) or a second access line (e.g., bit line115), or a combination thereof. In some cases, upon providing the pulse, ions may migrate within the memory storage element, depending on the polarity of the memory cell105. Thus, a concentration of ions relative to the first side or the second side of the memory storage element may be based at least in part on a polarity of a voltage between the first access line and the second access line. In some cases, asymmetrically shaped memory storage elements may cause ions to be more crowded at portions of an element having more area. Certain portions of the memory storage element may have a higher resistivity and thus may give rise to a higher threshold voltage than other portions of the memory storage element. This description of ion migration represents an example of a mechanism of the self-selecting memory cell for achieving the results described herein. This example of a mechanism should not be considered limiting. This disclosure also includes other examples of mechanisms of the self-selecting memory cell for achieving the results described herein.

Sense component125may include various transistors or amplifiers to detect and amplify a difference in the signals, which may be referred to as latching. The detected logic state of memory cell105may then be output through column decoder130as output135. In some cases, sense component125may be part of a column decoder130or row decoder120. Or, sense component125may be connected to or in electronic communication with column decoder130or row decoder120. An ordinary person skilled in the art would appreciate that sense component may be associated either with column decoder or row decoder without losing its functional purposes.

A memory cell105may be set or written by similarly activating the relevant word line110and bit line115and at least one logic value may be stored in the memory cell105. Column decoder130or row decoder120may accept data, for example input/output135, to be written to the memory cells105. In the case of a self-selecting memory cell including a chalcogenide material, a memory cell105may be written to store a logic state in the memory cell105by applying, by the decoder (e.g., row decoder120or column decoder130), the first access voltage to the access line (e.g., word line110or bit line115) coupled with the memory cell105as part of the access operation based on identifying the decoder.

The memory controller140may control the operation (e.g., read, write, re-write, refresh, discharge) of memory cells105through the various components, for example, row decoder120, column decoder130, and sense component125. In some cases, one or more of the row decoder120, column decoder130, and sense component125may be co-located with the memory controller140. Memory controller140may generate row and column address signals to activate the desired word line110and bit line115. Memory controller140may also generate and control various voltages or currents used during the operation of memory device100.

The memory controller140may be configured to receive an access command comprising an instruction to perform the access operation on the memory cell105. In some cases, the memory controller140may be configured to identify a first row decoder (e.g., row decoder120) of the set of row decoders configured to apply a first access voltage to the access line (e.g., word line110) coupled with the memory cell105as part of the access operation based on receiving the access command. The memory controller140may be configured to issue a command for the first row decoder to apply the first access voltage to the access line coupled with the memory cell105as part of the access operation of the memory cell based on identifying the first row decoder.

In some examples, the memory controller140may be configured to identify a second row decoder (e.g., row decoder120) of the set of row decoders. For example, the second row decode may be configured to apply a second access voltage to the access line (e.g., word line110) coupled with the memory cell105as part of the access operation based on receiving the access command. The memory controller140may be configured to issue a command for the second row decoder to apply the second access voltage to the access line coupled with the memory cell105as part of the access operation based on identifying the second row decoder.

The memory controller140may delay an application of the first access voltage to the access line based on identifying the second row decoder to apply the second access voltage. In such cases, applying the second access voltage to the access line occurs at the same time as applying the first access voltage to the access line. In some examples, the memory controller140may select the memory cell105based on applying the first access voltage.

FIG. 2illustrates an example of a top-down view of a decoder200as disclosed herein. Decoder200may be an example of a row decoder120or column decoder130described with reference toFIG. 1. Decoder200may include doped material210that extends in a direction away from a surface of the substrate (not shown). Decoder200may be an example of a last level decoder of a memory array.

Decoder200may include at least first conductive line205. In some cases, decoder200may include a plurality of first conductive lines205. First conductive line205may be configured to carry a voltage that is applied to the access line of the array of memory cells (not shown). For example, each first conductive line205may receive a signal from an access line within decoder200. First conductive line205may extend in a second direction.

In some cases, decoder200may include doped materials210that may extend between first conductive line205and the access line (not shown). For example, doped material210may extend in a direction (e.g., first direction) away from the surface of the substrate. In some cases, the direction may be perpendicular or orthogonal to a plane defined by a surface of the substrate.

For example, the second direction may be perpendicular to the first direction in which the first conductive line205extends. Doped material210may be configured to selectively couple first conductive line205of decoder200with the access line. In some cases, doped material210may comprise a semiconductor material such as polysilicon. In some cases, polysilicon may be deposited at a lower temperature than other materials, thereby increasing the compatibility between the polysilicon material of decoder200and the memory array.

Decoder200may also include contacts215. Contact215may extend between doped material210and other conductive lines of the decoder200or access lines of the array of memory cells. In some cases, doped material210may selectively couple first conductive line205of decoder200with contact215. Contact215may also extend between conductive material220and a conductive line (not shown).

In some examples, decoder200may include at least one conductive material220. Conductive material220may be coupled with doped material210. In some cases, conductive material220may be configured to carry a second voltage (e.g., different voltage than the voltage applied to the access line) for causing doped material210to selectively couple first conductive line205with the access line the memory array (e.g., array of memory cells). In that case, one or more conductive materials220may receive a signal from an access line associated with the memory array. In some cases, the access line may be an example of a word line. Each conductive material220may contact to an access line of the memory array.

In some cases, decoder200may include one or more transistors. For example, doped material210and conductive material220may comprise a transistor. The transistor may selectively couple first conductive line205with the access line of the memory array. In that case, conductive material220may be an example of a gate of the transistor and doped material210may be an example of a source of the transistor, a drain of the transistor, or both. In some cases, conductive material220may contact an oxide of doped material210.

The transistor may be an example of a nMOS type transistor or a pMOS type transistor. In some cases, polysilicon transistors as decoders may allow for large degree of freedom as compared to polysilicon transistors as selectors in the back-end of the memory array. For example, polysilicon transistors in the front-end of the memory array may allow the use of a higher thermal budget for dopant activation, thereby reducing the device engineering complexity. In some cases, a gate oxide may be positioned between the conductive material220and the doped material210.

In some examples, if decoder200includes doped material210that extends in a direction away from a surface of the substrate, the size and dimensions of decoder200may be optimized. For example, distance225between two conductive materials220may decrease when a vertical decoder is implemented. In some cases, width230of conductive material220may also decrease when a vertical decoder is implemented. In some examples, the combined distance235of distance225and width230may decrease when a vertical decoder is implemented.

In some cases, distance240between two first conductive lines205may increase when a vertical decoder is implemented. In some cases, width245of first conductive line205may decrease when a vertical decoder is implemented. The combined distance250of distance240and width245may decrease when a vertical decoder is implemented. As described below in further detail, decoder200may be viewed via perspective line255.

FIG. 3illustrates an example of a cross-sectional view of a portion of a memory array300that supports vertical decoders as disclosed herein. The portion of the memory array300may include a decoder302that may include doped materials310-a,310-b,310-c, and/or310-dthat extend in a direction away from a surface335of the substrate325. Decoder302may be an example of decoder200as described with reference toFIG. 2. Doped materials310-a,310-b,310-c, and310-dmay be examples of doped material210described with reference toFIG. 2.

The portion of the memory array300may include substrate325. In some examples, decoder302may be coupled with substrate325. Substrate325may be above or below decoder302. In some cases, decoder302may be configured to apply a voltage to an access line of an array of memory cells (e.g., a word line or digit line) as part of an access operation. In some cases, one or more decoders may be configured to apply a voltage to a same access line of the array of memory cells. Decoder302may also include first conductive line305, which may be an example of first conductive line205as described in reference toFIG. 2. In some cases, first conductive line305may be directly coupled with doped material310-a.

In some cases, decoder302may include doped materials310-athrough310-d. Doped materials310-athrough310-dmay be a polysilicon material. In some examples, doped materials310-athrough310-dmay extend between first conductive line305and the access line of the array of memory cells (e.g., word line or digit line) in a direction away from a surface335of substrate325. For example, doped materials310-athrough310-dmay extend orthogonally from a plane defined by the surface335of substrate325.

In some examples, doped material310may be include a first doped region340and a second doped region345. For example, the first doped region340may be a first distance away from the surface335of substrate325, and the second doped region345may be a second distance away from the surface335of substrate325. In that case, the first distance and the second distance away from the surface335of substrate325may be different. In some cases, the first doped region340and the second doped region345may include similarly doped materials. In other examples, the first doped region340and the second doped region345may include different doped materials. For example, the first doped region340may include polysilicon and the second doped region345may include a different semiconductor material.

Decoder302may include one or more contacts315including contacts315-aand315-b, which may be examples of contact215described in reference toFIG. 2. Contact315-amay extend between doped material310-aand the access line of the array of memory cells. In such cases, contact315-amay be directly coupled with doped material310-a. In some cases, doped material310-amay selectively couple first conductive line305of decoder302with contact315-a.

Decoder302may also include conductive material320that may be coupled with doped material310-aand310-b, and which may be an example of conductive material220as described in reference toFIG. 2. Conductive material320may be configured to carry a voltage for causing doped material310-ato selectively couple first conductive line305with the access line or the contact315-a. In some cases, conductive material320may be directly coupled with a surface of doped material310-a. For example, conductive material320may be coupled with a surface of doped material310-a. Conductive material320may contact an oxide of doped material310-a. In some examples, conductive material320may extend in a direction parallel to the surface of substrate325. Doped material310-amay extend in a direction perpendicular to a surface of the conductive material320.

In some cases, decoder302may include conductive line330. Conductive line330may be coupled to contact315-b. For example, contact315-bmay extend between conductive line330and conductive material320. Conductive line330may carry a voltage for causing doped material310-ato couple first conductive line305of decoder302with the access line. In some cases, contact315-bmay carry the voltage from conductive line330to conductive material320as part of the access operation. Conductive line330may extend in a direction parallel to the surface of substrate325. In that case, doped material310-amay extend in a direction perpendicular to a surface of the conductive line330. In some cases, the first conductive line305may be an example of a global word line or global digit line of the decoder302and the conductive line330may be an example of a local word line or a local digit line of the decoder302.

As described herein, the memory device may include one or more decoders302. The size of the memory array may be increased based on the placement/or orientation of the one or more decoders302. In such cases, the decoders302may be positioned above the memory array, below the memory array, or both (e.g., each decoder302opposite of each other), thereby reducing the size of the memory array. In addition, the size of the first conductive line305may be reduced based on the placement of the one or more decoders302. For example, one or more decoders302may be coupled with a same first conductive line305of the memory array, thereby reducing the resistance of the first conductive line305.

FIG. 4illustrates an example of a memory array400that supports vertical decoders as disclosed herein. Memory array400may include decoders402-a,402-b,402-c,402-d, substrate425, an array of memory cells435, first set of access lines432-a, and second set of access lines432-b. Decoders402-a,402-b,402-c,402-dand substrate425may be examples of decoder and substrate, as described in reference toFIGS. 3 and 4. Memory array400may include the array of memory cells435coupled with substrate425. In some cases, set of access lines432-amay comprise word lines or digit lines. In some examples, the set of access lines432-bmay comprise bit lines or digit lines or word lines. In other examples, memory array400may be an example a cross-point architecture, a pillar architecture, or a planar architecture. Memory array400may be an example of an electrical schematic representation.

Decoders402-aand402-bmay each be an example of a vertical row decoder as described herein. Decoder402-amay be an example of a first row decoder coupled with substrate425and a first side of the array of memory cells435. In some cases, decoder402-amay include conductive lines405-a(e.g., first conductive line), doped materials410-a, contacts415-a, and conductive material420-a, which may be examples of conductive lines, doped materials, contact, and conductive materials, as described in reference toFIGS. 2 and 3. In some examples, decoder402-amay be positioned above the array of memory cells435.

Decoder402-amay apply a first voltage to an access line430-aof set of access lines432-aas part of an access operation. Conductive line405-amay carry the first voltage for the access operation. In some cases, conductive line405-amay be coupled to the access line430-aof the set of access lines432-abased on applying the first voltage. For example, the contact415-amay carry a signal from another conductive line to cause the conductive line405-ato be coupled with the access line430-a. The contact415-amay couple the doped material410-awith the access line430-a.

In some cases, access line430-amay be selected based on activating the conductive line405-aand the conductive material420-a. The first voltage may also be applied to a memory cell of the array of memory cells435based on coupling conductive line405-ato the access line430-a. In some cases, a logic state stored in the memory cell of the array of memory cells435may be outputted based on applying the first voltage. In that case, the access operation may be a read operation. In some examples, a logic state may be stored in the memory cell of the array of memory cells435based on applying the first voltage. In that case, the access operation may be a write operation.

Doped material410-amay extend between conductive line405-aand one of the set of access lines432-a(or contacts415-a) in a direction that is non-parallel (e.g., perpendicular) to the surface of substrate425. That is, doped material410-amay extend in a direction that is non-parallel (e.g., perpendicular) to a surface of conductive material420-a. In some cases, conductive line405-aand access line430-amay be selectively coupled via doped material410-a.

Decoder402-bmay be an example of a second row decoder coupled with substrate425and a second side of the array of memory cells435. For example, the array of memory cells435may be positioned between decoder402-aand decoder402-b. In some cases, decoder402-bmay include conductive lines405-b(e.g., second conductive line), doped materials410-b, contacts415-b, and conductive material420-b, which may be examples of conductive lines, doped materials, contact, and conductive materials, as described in reference toFIGS. 2 and 3. In some examples, decoder402-bmay be positioned below the array of memory cells435.

Decoder402-bmay apply a second voltage to the access line430-aof set of access lines432-aas part of an access operation. Conductive line405-bmay carry the second voltage for the access operation. In some cases, conductive line405-bmay be coupled to the access line430-aof the set of access lines432-abased on applying the second voltage. For example, the contact415-bmay carry a signal from another conductive line to cause the conductive line405-bto be coupled with the access line430-a. The contact415-bmay couple the doped material410-bwith the access line430-a. In some cases, access line430-amay be selected based on activating the conductive line405-band the conductive material420-b. The second voltage may also be applied to a memory cell of the array of memory cells435based on coupling conductive line405-bto the access line430-a.

In some cases, a logic state stored in the memory cell of the array of memory cells435may be outputted based on applying the first voltage and the second voltage. In such cases, the access operation may be a read operation. In some examples, a logic state may be stored in the memory cell of the array of memory cells435based on applying the first voltage and the second voltage. In that case, the access operation may be a write operation. In some cases, the voltage applied to the access line430-amay be split between the first voltage and the second voltage. For example, the first voltage applied by the decoder402-amay include a portion of the voltage applied to the access line430-a, and the second voltage applied by decoder402-bmay include the other portion of the voltage applied to the access line430-a.

In some examples, decoder402-amay apply the first voltage at the same time as decoder402-bmay apply the second voltage. For example, decoder402-aand decoder402-bmay operate in parallel. In other examples, decoder402-amay apply the first voltage at a different time as decoder402-bmay apply the second voltage. For example, the application of the first voltage may be delayed in order to apply the first voltage and the second voltage at the same time.

Doped material410-bmay extend between conductive line405-band one of the set of access lines432-a(or contacts415-b) in a direction that is non-parallel (e.g., perpendicular) to the surface of substrate425. That is, doped material410-bmay extend in a direction that is non-parallel (e.g., perpendicular) to a surface of conductive material420-b. In some cases, conductive line405-band access line430-amay be selectively coupled via doped material410-b.

As described herein, memory array400may include decoder402-aand decoder402-b. The size of the memory array400may be reduced based on the placement/or orientation of decoder402-aand decoder402-b. In addition, the size of access line430-amay be reduced based on the placement/or orientation of decoder402-aand decoder402-band/or the reduction in the amount of voltage carried over the access line. For example, if two decoders are used to bias an access line to a particular voltage, the amount voltage/current applied by each decoder may be less than the amount of voltage applied by a single decoder. In some cases, the worst case access resistance (e.g., parasitic resistance) of access line430-amay be reduced of a fourth of the total resistance of the array of memory cells435.

In some cases, memory array400may include decoder402-cwhich may be a first column decoder. For example, decoder402-cmay be coupled with substrate425and a third side of the array of memory cells435. In some cases, decoder402-cmay include conductive lines405-c, doped materials410-c, contacts415-c, and conductive material420-c. In some examples, decoder402-cmay be positioned above the array of memory cells435or below the array of memory cells435(not shown).

In some cases, fabrication techniques to form memory array400may include a different masking step to form each of the different lengths of contacts415-c(e.g., the distance between doped material410-cand access line430-b). In some examples, the contacting scheme may be an example of a staggered configuration. For example, the length of contact415-cmay increase as the distance between contact415-cand the array of memory cells435increases. In such cases, the top access line430-bmay extend further than the bottom access line430-b. The contacting scheme may be implemented via additional conductive layers (not shown). In some examples, a single masking step after deposition may be implemented to obtain the contacting scheme (e.g., staggered configuration).

In some examples, decoder402-cmay apply a third voltage to the access line430-bof the set of access lines432-bas part of the access operation. Conductive line405-cmay carry the third voltage for selecting a memory cell of the array of memory cells435as part of the access operation. The contact415-cmay couple the doped material410-cwith the access line430-b. In some cases, the access line430-bmay be selected based on activating the conductive line405-cand the conductive material420-c. In some cases, the contact415-cmay carry a signal from another conductive line to cause conductive line405-cto be coupled with the access line430-b.

A memory cell included in the array of memory cells435may be selected based on the intersection of activated access lines430-aand430-b. For example, the intersection of the first voltage and second voltages and the third voltage may select the memory cell. In that case, the signal applied to the memory cell of the array of memory cells435may have a positive or negative polarity.

In some cases, doped material410-cmay extend between conductive line405-cand one of the set of access lines432-b(or contacts415-c) in a direction that is non-parallel (e.g., perpendicular) to the surface of substrate425. Conductive line405-cand access line430-bmay be coupled via doped material410-c.

In some cases, memory array400may include decoder402-dwhich may be a second column decoder. For example, decoder402-dmay be coupled with substrate425and a fourth side of the array of memory cells435. For example, the array of memory cells435may be positioned between decoder402-cand decoder402-d. In some cases, decoder402-dmay include conductive lines405-d, doped materials410-d, contacts415-d, and conductive material420-d. In some examples, decoder402-dmay be positioned above the array of memory cells435(not shown) or below the array of memory cells435.

In some cases, fabrication techniques to form memory array400may include a different masking step to form each of the different lengths of contacts415-d(e.g., the distance between doped material410-dand access line430-b). In some examples, the contacting scheme may be an example of a staggered configuration. For example, the length of contact415-dmay increase as the distance between contact415-dand the array of memory cells435increases. In such cases, the top access line430-bmay extend further than the bottom access line430-b. The contacting scheme may be implemented via additional conductive layers (not shown). In some examples, a single masking step after deposition may be implemented to obtain the contacting scheme (e.g., staggered configuration).

In some examples, decoder402-dmay apply a fourth voltage to the access line430-bof the set of access lines432-bas part of the access operation. Conductive line405-bmay carry the fourth voltage for selecting a memory cell of the array of memory cells435as part of the access operation. The contact415-dmay couple the doped material410-dwith the access line430-b. In some cases, the access line430-bmay be selected based on activating the conductive line405-dand the conductive material420-d. In some cases, the contact415-dmay carry a signal from another conductive line to cause conductive line405-dto be coupled with the access line430-b.

A memory cell included in the array of memory cells435may be selected based on the intersection of activated access lines430-aand430-b. For example, the intersection of the first voltage and second voltages and the fourth voltage may select the memory cell. In that case, the signal applied to the memory cell of the array of memory cells435may have a positive or negative polarity. In some cases, the voltage applied to the access line430-bmay be split between the third voltage and the fourth voltage. For example, the third voltage applied by the decoder402-cmay include a portion of the voltage applied to the access line430-b, and the fourth voltage applied by decoder402-dmay include the other portion of the voltage applied to the access line430-b. In some examples, decoder402-cmay apply the third voltage at the same time as decoder402-dmay apply the fourth voltage. For example, decoder402-cand decoder402-dmay operate in parallel.

In other examples, decoder402-cmay apply the third voltage at a different time as decoder402-dmay apply the fourth voltage. For example, the application of the third voltage may be delayed in order to apply the third voltage and the fourth voltage at the same time.

In some cases, doped material410-dmay extend between conductive line405-dand one of the set of access lines432-b(or contacts415-d) in a direction that is non-parallel (e.g., perpendicular) to the surface of substrate425. Conductive line405-dand access line430-bmay be coupled via doped material410-d.

As described herein, memory array400may include decoder402-cand decoder402-d. The size of the memory array400may be reduced based on the placement/or orientation of decoder402-cand decoder402-d. In addition, the size of access line430-bmay be reduced based on the placement/or orientation of decoder402-cand decoder402-dand/or the reduction in the amount of voltage carried over the access line. For example, if two decoders are used to bias an access line to a particular voltage, the amount voltage applied by each decoder may be less than the amount of voltage applied by a single decoder. In some cases, the resistance (e.g., parasitic resistance) of access line430-bmay be reduced to a fourth of the total resistance of the array of memory cells435.

FIG. 5illustrates an example of a memory array500that supports vertical decoders as disclosed herein. Memory array500may include decoders502-a,502-b, and502-c, substrate525, an array of memory cells535, first set of access lines532-a, and second set of access lines532-b. Decoders502-a,502-b, and502-cand substrate525may be examples of decoder and substrate, as described in reference toFIGS. 2-5. Memory array500may include the array of memory cells535coupled with substrate525. In some cases, set of access lines532-amay comprise word lines or digit lines. In some examples, the set of access lines532-bmay comprise bit lines or digit lines or word lines. In other examples, memory array500may be an example a cross-point architecture, a pillar architecture, or a planar architecture. Memory array500may be an example of an electrical schematic representation and may be an example of memory array400, as described in reference toFIG. 4.

Decoder502-amay be an example of a first row decoder coupled with substrate525and a first side of the array of memory cells535. For example, decoder502-amay be an example of and perform the methods of decoder402-a, as described in refence toFIG. 4. In some cases, decoder502-amay include conductive lines505-a(e.g., first conductive line), doped materials510-a, contacts515-a, and conductive material520-a, which may be examples of conductive lines, doped materials, contact, and conductive materials, as described in reference toFIGS. 2-4. In some examples, decoder502-amay be positioned above the array of memory cells535.

In some cases, memory array500may include decoder502-b. Decoder502-bmay be an example of a second row decoder coupled with substrate525and a second side of the array of memory cells535. For example, the array of memory cells535may be positioned between decoder502-aand decoder502-b. Decoder502-bmay be an example of and perform the methods of decoder402-b, as described in refence toFIG. 4. In some cases, decoder502-bmay include conductive lines505-b(e.g., second conductive line), doped materials510-b, contacts515-b, and conductive material520-b, which may be examples of conductive lines, doped materials, contact, and conductive materials, as described in reference toFIGS. 2-4. In some examples, decoder502-bmay be positioned below the array of memory cells535.

In some cases, memory array500may include decoder502-cwhich may be a first column decoder. For example, decoder502-cmay be coupled with substrate525and a third side of the array of memory cells535. Decoder502-cmay be an example of and perform the methods of decoder402-c, as described in refence toFIG. 4. In some cases, decoder502-cmay include conductive lines505-c, doped materials510-c, contacts515-c, and conductive material520-c, which may be examples of conductive lines, doped materials, contact, and conductive materials, as described in reference toFIGS. 2-4. In some examples, decoder502-cmay be positioned above the array of memory cells535or below the array of memory cells535(not shown).

As described herein, memory array500may include decoder502-aand decoder502-b. The size of the memory array500may be reduced based on the placement/or orientation of decoder502-aand decoder502-b. In addition, the size of access line530-amay be reduced based on the placement/or orientation of decoder502-aand decoder502-b. For example, the worst case access resistance (e.g., parasitic resistance) of access line530-amay be reduced of a fourth of the total resistance of the array of memory cells535. In some examples, the size of access line530-bmay remain unchanged based on the placement/or orientation of decoder502-c. In such cases, a size of the access line530-amay be smaller than a size of the access line530-b. In some cases, the resistance of access line530-bmay be equal to the total resistance of the array of memory cells535.

FIG. 6illustrates an example of a memory array600that supports vertical decoders as disclosed herein. Memory array600may include decoders602-a,602-b, and602-c, substrate625, an array of memory cells635, first set of access lines632-a, and second set of access lines632-b. Decoders602-a,602-b, and602-cand substrate625may be examples of decoder and substrate, as described in reference toFIGS. 2-5. Memory array600may include the array of memory cells635coupled with substrate625. In some cases, set of access lines632-amay comprise word lines or digit lines. In some examples, the set of access lines632-bmay comprise bit lines or digit lines or word lines. In other examples, memory array600may be an example a cross-point architecture, a pillar architecture, or a planar architecture. Memory array600may be an example of an electrical schematic representation and may be an example of memory array400and500, as described in reference toFIGS. 4 and 5.

Decoder602-amay be an example of a first column decoder coupled with substrate625and a first side of the array of memory cells635. For example, decoder602-amay be an example of and perform the methods of decoder402-cand502-c, as described in refence toFIGS. 4 and 5. In some cases, decoder602-amay include conductive lines605-a(e.g., first conductive line), doped materials610-a, contacts615-a, and conductive material620-a, which may be examples of conductive lines, doped materials, contact, and conductive materials, as described in reference toFIGS. 2-5. In some examples, decoder602-amay be positioned above the array of memory cells635. Decoder602-amay be configured to access the array of memory cells635coupled with access line630-b(e.g., first access line).

In some cases, memory array600may include decoder602-b. Decoder602-bmay be an example of a second column decoder coupled with substrate625and a second side of the array of memory cells635. For example, the array of memory cells635may be positioned between decoder602-aand decoder602-b. Decoder602-bmay be an example of and perform the methods of decoder402-d, as described in refence toFIG. 4. In some cases, decoder602-bmay include conductive lines605-b(e.g., second conductive line), doped materials610-b, contacts615-b, and conductive material620-b, which may be examples of conductive lines, doped materials, contact, and conductive materials, as described in reference toFIGS. 2-5. In some examples, decoder602-bmay be positioned below the array of memory cells635. Decoder602-bmay be configured to access the array of memory cells635coupled with access line630-b(e.g., first access line).

Decoder602-aand decoder602-bmay access the same array of memory cells635at a same time. In some cases, decoder602-aand decoder602-bmay access the array of memory cells635in a differential access operation. For example, the memory cells of the array of memory cells635closer to decoder602-athan decoder602-bmay receive more energy from decoder602-athan energy from decoder602-b. In other examples, the memory cells of the array of memory cells635closer to decoder602-bthan decoder602-amay receive more energy from decoder602-bthan energy from decoder602-a.

In some cases, memory array600may include decoder602-cwhich may be a first row decoder. For example, decoder602-cmay be coupled with substrate625and a third side of the array of memory cells635. Decoder602-cmay be an example of and perform the methods of decoder402-aand502-a, as described in refence toFIGS. 4 and 5. In some cases, decoder602-cmay include conductive lines605-c, doped materials610-c, contacts615-c, and conductive material620-c, which may be examples of conductive lines, doped materials, contact, and conductive materials, as described in reference toFIGS. 2-5. In some examples, decoder602-cmay be positioned above the array of memory cells635or below the array of memory cells635(not shown). In some examples, decoder602-cmay be configured to access the array of memory cells635coupled with access line630-a(e.g., second access line).

As described herein, memory array600may include decoder602-aand decoder602-b. The size of the memory array600may be reduced based on the placement/or orientation of decoder602-aand decoder602-b. In addition, the size of access line630-bmay be reduced based on the placement/or orientation of decoder602-aand decoder602-b. For example, the worst case access resistance (e.g., parasitic resistance) of access line630-bmay be reduced of a fourth of the total resistance of the array of memory cells635. In some examples, the size of access line630-amay remain unchanged based on the placement/or orientation of decoder602-c.

In such cases, a size of the access line630-bmay be smaller than a size of the access line630-a. In some cases, the resistance of access line630-amay be equal to the total resistance of the array of memory cells635. In some examples, memory array600may include a decrease in performance and cost when compared memory array500and600. In such cases, the size (e.g., footprint) of memory array600may be the same as the size (e.g., footprint) of memory array400, but memory array600may include half of the gain on access line630-adue to the presence of a single row decoder (e.g., decoder602-c).

FIG. 7illustrates an example of a memory array700that supports vertical decoders as disclosed herein. Memory array700may include decoders702-a,702-b, and702-c, substrate725, an array of memory cells735, first set of access lines732-a, and second set of access lines732-b. Decoders702-a,702-b, and702-cand substrate725may be examples of decoder and substrate, as described in reference toFIGS. 3-6. Memory array700may include the array of memory cells735coupled with substrate725. In some cases, set of access lines732-amay comprise word lines or digit lines. In some examples, the set of access lines732-bmay comprise bit lines or digit lines or word lines. In other examples, memory array700may be an example a cross-point architecture, a pillar architecture, or a planar architecture. Memory array700may be an example of an electrical schematic representation and may be an example of memory array400,500, and600, as described in reference toFIGS. 4-6.

Decoder702-amay be an example of a first column decoder coupled with substrate725and a first side of the array of memory cells735. For example, decoder702-amay be an example of and perform the methods of decoder402-c,502-c, and602-aas described in refence toFIGS. 4-6. In some cases, decoder702-amay include conductive lines705-a(e.g., first conductive line), doped materials710-a, contacts715-a, and conductive material720-a, which may be examples of conductive lines, doped materials, contact, and conductive materials, as described in reference toFIGS. 2-6. In some examples, decoder702-amay be positioned above the array of memory cells735. Decoder702-amay be configured to access the array of memory cells735coupled with access line730-b(e.g., first access line).

In some cases, memory array700may include decoder702-b. Decoder702-bmay be an example of a second column decoder coupled with substrate725and a second side of the array of memory cells735. For example, the array of memory cells735may be positioned between decoder702-aand decoder702-b. Decoder702-bmay be an example of and perform the methods of decoder402-dand602-b, as described in refence toFIGS. 4 and 6. In some cases, decoder702-bmay include conductive lines705-b(e.g., second conductive line), doped materials710-b, contacts715-b, and conductive material720-b, which may be examples of conductive lines, doped materials, contact, and conductive materials, as described in reference toFIGS. 2-6. In some examples, decoder702-bmay be positioned below the array of memory cells735. Decoder702-bmay be configured to access the array of memory cells735coupled with access line730-b(e.g., first access line).

Decoder702-aand decoder702-bmay access the same array of memory cells735at a same time. In some cases, decoder702-aand decoder702-bmay access the array of memory cells735in a differential access operation. For example, the memory cells of the array of memory cells735closer to decoder702-athan decoder702-bmay receive more energy from decoder702-athan energy from decoder702-b. In other examples, the memory cells of the array of memory cells735closer to decoder702-bthan decoder702-amay receive more energy from decoder702-bthan energy from decoder702-a.

In some cases, memory array700may include decoder702-cwhich may be a first row decoder. For example, decoder702-cmay be coupled with substrate725and a third side of the array of memory cells735. Decoder702-cmay be an example of and perform the methods of decoder402-band502-b, as described in refence toFIGS. 4 and 5. In some cases, decoder702-cmay include conductive lines705-c, doped materials710-c, contacts715-c, and conductive material720-c, which may be examples of conductive lines, doped materials, contact, and conductive materials, as described in reference toFIGS. 2-6. In some examples, decoder702-cmay be positioned above the array of memory cells735(not shown) or below the array of memory cells735. In some examples, decoder702-cmay be configured to access the array of memory cells735coupled with access line730-a(e.g., second access line).

As described herein, memory array700may include decoder702-aand decoder702-b. The size of the memory array700may be reduced based on the placement/or orientation of decoder702-aand decoder702-b. In addition, the size of access line730-bmay be reduced based on the placement/or orientation of decoder702-aand decoder702-b. For example, the worst case access resistance (e.g., parasitic resistance) of access line730-bmay be reduced of a fourth of the total resistance of the array of memory cells735. In some examples, the size of access line730-amay remain unchanged based on the placement/or orientation of decoder702-c.

In such cases, a size of the access line730-bmay be smaller than a size of the access line730-a. In some cases, the resistance of access line730-amay be equal to the total resistance of the array of memory cells735. In some examples, memory array700may include a decrease in performance and cost when compared memory array500and600. In such cases, the size (e.g., footprint) of memory array700may be the same as the size (e.g., footprint) of memory array400, but memory array700may include half of the gain on access line730-adue to the presence of a single row decoder (e.g., decoder702-c).

FIG. 8Aillustrates an example of a memory device configuration800-athat supports vertical decoders as disclosed herein. Memory device configuration800-amay include decoder805-a, array of memory cells810-a, and substrate815-a, which may be examples of a decoder, array of memory cells, and substrate, as described in reference toFIGS. 2-7. In some cases, array of memory cells810-amay be positioned between substrate815-aand decoder805-a.

FIG. 8Billustrates an example of a memory device configuration800-bthat supports vertical decoders as disclosed herein. Memory device configuration800-bmay include decoder805-b, array of memory cells810-b, and substrate815-b, which may be examples of a decoder, array of memory cells, and substrate, as described in reference toFIGS. 2-7. In some cases, decoder805-bmay be positioned between array of memory cells810-band substrate815-b.

FIG. 9shows a block diagram900of a device905that supports vertical decoders as disclosed herein. In some examples, the device905may be an example of a memory array. The device905may be an example of portions of a memory controller (e.g., memory controller140as described with reference toFIG. 1). The device905may include command component910, decoder identifier915, voltage component920, and selection component925. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

Command component910may receive an access command comprising an instruction to perform an access operation on a memory cell. In some examples, command component910may issue a command for the first row decoder to apply the first access voltage to the access line coupled with the memory cell as part of the access operation of the memory cell based at least in part on identifying the first row decoder. In some examples, command component910may issue a command for the second row decoder to apply the second access voltage to the access line coupled with the memory cell as part of the access operation of the memory cell based at least in part on identifying the second row decoder.

Decoder identifier915may identify a first row decoder of a set of row decoders configured to apply a first access voltage to an access line coupled with the memory cell as part of the access operation based at least in part on receiving the access command. In some examples, decoder identifier915may identify a second row decoder of the set of row decoders configured to apply a second access voltage to the access line coupled with the memory cell as part of the access operation based at least in part on receiving the access command.

Voltage component920may apply, by the first row decoder, the first access voltage to the access line coupled with the memory cell as part of the access operation of the memory cell based at least in part on identifying the first row decoder. In some examples, voltage component920may apply, by the second row decoder, the second access voltage to the access line coupled with the memory cell as part of the access operation of the memory cell based at least in part on identifying the second row decoder. In some cases, applying the second access voltage to the access line may occur concurrently with applying the first access voltage to the access line. In some examples, voltage component920may delay an application of the first access voltage to the access line based at least in part on identifying the second row decoder for applying the second access voltage.

Selection component925may select the memory cell during the access operation based at least in part on applying the first access voltage to the access line.

FIG. 10shows a flowchart illustrating a method1000that supports vertical decoders as disclosed herein. The operations of method1000may be implemented by a memory controller or its components as described herein. For example, the operations of method1000may be performed by a device905as described with reference toFIG. 9or a memory controller140as described with reference toFIG. 1. In some examples, a memory controller may execute a set of instructions to control the functional elements of the memory array to perform the functions described below. Additionally or alternatively, a memory controller may perform portions of the functions described below using special-purpose hardware.

At1005, the memory controller may receive an access command comprising an instruction to perform an access operation on a memory cell. The operations of1005may be performed according to the methods described herein. In some examples, portions of the operations of1005may be performed by a command component as described with reference toFIG. 9.

At1010, the memory controller may identify a first row decoder of a set of row decoders configured to apply a first access voltage to an access line coupled with the memory cell as part of the access operation based at least in part on receiving the access command. The operations of1010may be performed according to the methods described herein. In some examples, portions of the operations of1010may be performed by a decoder identifier as described with reference toFIG. 9.

At1015, the memory controller may apply, by the first row decoder, the first access voltage to the access line coupled with the memory cell as part of the access operation of the memory cell based at least in part on identifying the first row decoder. The operations of1015may be performed according to the methods described herein. In some examples, portions of the operations of1015may be performed by a voltage component as described with reference toFIG. 9.

FIG. 11shows a flowchart illustrating a method1100that vertical decoders as disclosed herein. The operations of method1100may be implemented by a memory controller or its components as described herein. For example, the operations of method1100may be performed by a device905as described with reference toFIG. 9or a memory controller140as described with reference toFIG. 1. In some examples, a memory controller may execute a set of instructions to control the functional elements of the memory array to perform the functions described below. Additionally or alternatively, a memory controller may perform portions of the functions described below using special-purpose hardware.

At1105, the memory controller may receive an access command comprising an instruction to perform an access operation on a memory cell. The operations of1105may be performed according to the methods described herein. In some examples, portions of the operations of1105may be performed by a command component as described with reference toFIG. 9.

At1110, the memory controller may identify a first row decoder of a set of row decoders configured to apply a first access voltage to an access line coupled with the memory cell as part of the access operation based at least in part on receiving the access command. The operations of1110may be performed according to the methods described herein. In some examples, portions of the operations of1110may be performed by a decoder identifier as described with reference toFIG. 9.

At1115, the memory controller may apply, by the first row decoder, the first access voltage to the access line coupled with the memory cell as part of the access operation of the memory cell based at least in part on identifying the first row decoder. The operations of1115may be performed according to the methods described herein. In some examples, portions of the operations of1115may be performed by a voltage component as described with reference toFIG. 9.

At1120, the memory controller may identify a second row decoder of the set of row decoders configured to apply a second access voltage to the access line coupled with the memory cell as part of the access operation based at least in part on receiving the access command. The operations of1120may be performed according to the methods described herein. In some examples, portions of the operations of1120may be performed by a decoder identifier as described with reference toFIG. 9.

At1125, the memory controller may apply, by the second row decoder, the second access voltage to the access line coupled with the memory cell as part of the access operation of the memory cell based at least in part on identifying the second row decoder. The operations of1125may be performed according to the methods described herein. In some examples, portions of the operations of1125may be performed by a voltage component as described with reference toFIG. 9.

In some examples, an apparatus as described herein may perform a method or methods, such as the method1100. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving an access command comprising an instruction to perform an access operation on a memory cell. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for identifying a first row decoder of a set of row decoders configured to apply a first access voltage to an access line coupled with the memory cell as part of the access operation based at least in part on receiving the access command. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for applying, by the first row decoder, the first access voltage to the access line coupled with the memory cell as part of the access operation of the memory cell based at least in part on identifying the first row decoder.

Some examples of the method1100and the apparatus described herein may further include operations, features, means, or instructions for identifying a second row decoder of the set of row decoders configured to apply a second access voltage to the access line coupled with the memory cell as part of the access operation based at least in part on receiving the access command. Some examples of the method1100and the apparatus described herein may further include operations, features, means, or instructions for applying, by the second row decoder, the second access voltage to the access line coupled with the memory cell as part of the access operation of the memory cell based at least in part on identifying the second row decoder. In some cases, applying the second access voltage to the access line may occur concurrently with applying the first access voltage to the access line.

Some examples of the method1100and the apparatus described herein may further include operations, features, means, or instructions for delaying an application of the first access voltage to the access line based at least in part on identifying the second row decoder for applying the second access voltage. Some examples of the method1100and the apparatus described herein may further include operations, features, means, or instructions for selecting the memory cell during the access operation based at least in part on applying the first access voltage to the access line. Some examples of the method1100and the apparatus described herein may further include operations, features, means, or instructions for issuing a command for the first row decoder to apply the first access voltage to the access line coupled with the memory cell as part of the access operation of the memory cell based at least in part on identifying the first row decoder. Some examples of the method1100and the apparatus described herein may further include operations, features, means, or instructions for issuing a command for the second row decoder to apply the second access voltage to the access line coupled with the memory cell as part of the access operation of the memory cell based at least in part on identifying the second row decoder.

As used herein, the term “substantially” means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) need not be absolute but is close enough to achieve the advantages of the characteristic.