A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.

FIELD

This invention relates to integrated circuits and, more particularly, to integrated circuit voltage-level converters.

BACKGROUND

In traditional complementary metal-oxide semiconductor (CMOS) very large scale integration (VLSI) circuit designs, CMOS integrated circuits are powered by one voltage level. Although traditional CMOS integrated circuits powered by one voltage level continue to be developed and manufactured, the demand for longer battery life in many electronic devices, such as ultra low-power microprocessors used in portable computers and digital signal processors used in personal digital assistants and cellular telephones, is creating a demand for CMOS VLSI circuit designs that consume less power than traditional designs.

One approach to reducing power in a CMOS circuit design is to power the CMOS circuits with two voltage levels. The first or higher voltage level powers critical circuit paths and critical functional units. A critical circuit path is a circuit path that is designed to transmit signals as fast as possible along the path. A critical functional unit is a functional unit, such as an arithmetic and logic unit, that is designed perform a logical operation as fast as possible. A CMOS circuit path powered at a higher voltage level transmits a signal more rapidly than the same CMOS path powered at a lower voltage level, and a CMOS functional unit powered by higher voltage level generally processes signals more rapidly than the same functional unit powered at a lower voltage level. The second or lower voltage level powers non-critical paths and non-critical functional units. The result of applying this design approach to CMOS circuits is that the non-critical CMOS circuit paths, which are powered at the lower voltage level, and the non-critical CMOS functional units, which are also powered at the lower voltage level, consume less power than they would consume if powered at a higher voltage level. Thus, a complete CMOS circuit can be designed to consume less power when powered at two voltage levels than when powered at one voltage level.

One problem with powering a CMOS circuit with two voltage levels, such as a lower voltage level and a higher voltage level, is that signals generated by circuits powered at the lower voltage level are usually incompatible with circuits powered at the higher voltage level. To make signals generated by circuits powered at the lower voltage level compatible with circuits powered at the higher voltage level, a voltage level converter is inserted between the circuits powered at the lower voltage level and the circuits powered at the higher voltage level.

FIG. 1is a schematic diagram of a prior art voltage level converter100. The prior art voltage level converter100includes n-type insulated-gate field-effect transistors (FETs)102-103, an inverter104, cross-coupled p-type insulated-gate FETs106-107, and an output buffer109. The p-type insulated-gate FET106is coupled to the n-type insulated-gate FET102at node111, the p-type insulated-gate FET107is coupled to the n-type insulated-gate FET103at node113, the gate of the p-type insulated-gate FET106is coupled to the node113, the gate of the p-type insulated-gate FET107is coupled to the node111, and the input node115is coupled to the n-type insulated-gate FET103through the inverter104.

FIG. 2Ais a sketch of a logic signal illustrating a transition from a high logic level, VCCL, to a low logic level, VLOW. The logic signal shown inFIG. 2Ais one example of INPUT SIGNAL117shown inFIG. 1.FIG. 2Bis a sketch of the logic signal at the node113that results from applying the input logic signal shown inFIG. 2Ato the prior art voltage-level converter100shown inFIG. 1.FIG. 2Cis a sketch of the BUFFERED OUTPUT SIGNAL127that results from applying the input logic signal shown inFIG. 2Ato the prior art voltage level converter100.

Referring again toFIG. 1, for INPUT SIGNAL117at a high logic level (assuming a high logic level corresponds a positive voltage level) as shown inFIG. 2Aat201, the n-type insulated-gate FET102is turned on, the p-type insulated-gate FET106is turned off, the n-type insulated-gate FET103is turned off, and the p-type insulated-gate FET107is turned on. Thus, substantially zero current flows between the power supply node119and the ground node121, substantially zero current flows between the power supply node123and the ground node125, and substantially zero power is consumed by the voltage level converter100.

FIG. 2Dis a sketch of a logic signal illustrating a transition from a low logic level, VLOW, to a high logic level, VCCL. For the INPUT SIGNAL117at a low logic level (assuming a low logic level corresponds to a zero voltage level) as shown at203inFIG. 2D, the n-type insulated-gate FET102is turned off, the p-type insulated-gate FET106is turned on, the n-type insulated-gate FET103is turned on, and the p-type insulated-gate FET107is turned off. Thus, substantially zero current flows between the power supply node119and the ground node121, substantially zero current flows between the power supply node123and the ground node125, and substantially zero power is consumed by the voltage level converter100. Therefore, for a static input logic signal at input node115substantially zero power is consumed by the prior art voltage-level converter100.

However, during the transition of a signal at the input node115power is consumed by the prior art voltage-level converter100. For example, during the transition of the INPUT SIGNAL117from a high logic-level to a low logic-level, as shown at205inFIG. 2A, the p-type insulated-gate FET103turns on before the n-type insulated-gate FET107turns off, so current flows between the power supply node123and the ground node125. Similarly, during the transition of INPUT SIGNAL117from a low logic-level to a high logic-level, as shown at207inFIG. 2D, the n-type insulated-gate FET102turns on before the p-type insulated-gate FET106turns off, so current flows between the power supply node119and the ground node121. Therefore, power is consumed by voltage converter circuit100during transitions of the INPUT SIGNAL117.

Unfortunately, including a voltage-level inverter, such as voltage-level converter100, in a two voltage-level CMOS VLSI circuit design increases the power consumed by the circuit when compared to the power consumed in a traditional CMOS one supply voltage circuit design.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which are shown, by way of illustration, specific embodiments of the invention which may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

To simplify the description of the operation of the embodiments of the voltage-level converters described herein the input and output signals for each of the voltage-level converters are described only once below.

Each of the example embodiments of the voltage-level converters disclosed in the block diagrams and schematics shown inFIGS. 3A-3B,4A-4D,5A-5D, and6A-6C receive and convert an INPUT SIGNAL comprised of a first pair of signal levels to an OUTPUT SIGNAL or a BUFFERED OUTPUT SIGNAL comprised of a second pair of signal levels. The signals illustrated inFIGS. 2A and 2Drepresent typical INPUT SIGNALS comprising the first pair of signal levels, VCCLand VLOW. The signals illustrated inFIGS. 2B and 2Crepresent typical OUTPUT SIGNALS and BUFFERED OUTPUT SIGNALS comprising the second pair of signal levels, VCCHand VLOW.

The VCCHsignal level is greater than the VCCLsignal level.

FIG. 3Ais a block diagram of one embodiment of a voltage-level converter300including a static voltage-level converter302coupled to a split-level output circuit304according to the teachings of the present invention.

The static voltage-level converter302includes an input node306, a first output node308, and a second output node309. The split-level output circuit304includes a first split-level input node311, a second split-level input node312, and a split-level output node314. The first split-level input node311is coupled to the first output node308of the static voltage-level converter302, and the second split-level input node312is coupled to the second output node309of the static voltage-level converter302. A split-level output circuit includes at least two input nodes for receiving input signals.

The static voltage-level converter302comprises a circuit that consumes substantially zero power for static or unchanging inputs. Thus, for an INPUT SIGNAL having a logical zero voltage level or a logical one voltage level, the static voltage-level converter302consumes substantially zero power. The voltage-level converter300is not limited to use in connection with a particular static voltage-level converter302. Any static voltage-level converter that consumes substantially zero power for static or unchanging inputs is suitable for use in connection with the voltage-level converter300.

The split-level output circuit304provides improved current drive capability when compared with the current drive capability provided at output nodes308and309of the static voltage-level converter302or with a single-ended inverter. The improved current drive capability permits the voltage-level converter300to drive more logic gates or larger capacitive loads without substantially increasing the rise time (the time for a signal to change from 10% to 90% of its final value) or the fall time (the time for a signal to change from 90% to 10% of its initial value) of the BUFFERED OUTPUT SIGNAL.

FIG. 3Bis a schematic diagram of one embodiment of the voltage-level converter300shown inFIG. 3Aaccording to the teachings of the present invention. The voltage-level converter300includes the static voltage-level converter302and the split-level output circuit304.

The static voltage-level converter302includes the input node306, the first output node308, the second output node309, a first pair of transistors320connected in series, a second pair of transistors322connected in series, and an inverter324. The first pair of transistors320includes a first transistor326and a second transistor328. The first transistor326is coupled to the input node306. The second pair of transistors322includes a first transistor330and a second transistor332. The second transistor332of the second pair of transistors322is cross-coupled with the second transistor328of the first pair of transistors320. Two transistors are cross-coupled by coupling a control port of a first transistor to a controlled port of a second transistor and by coupling a control port of a second transistor to a controlled port of the first transistor. As can be seen inFIG. 3B, the gate of transistor328(the control port of transistor328) is coupled to the drain/source of transistor332(the controlled port of transistor332) and the gate of transistor332(the control port of transistor332) is coupled to the drain/source of transistor328(the controlled port of transistor332). The inverter324is coupled to the input node306, to the first transistor326of the first pair of transistors320, to the first transistor330of the second pair of transistors322, and to the second output node309. The second transistor332of the second pair of transistors322is coupled to the first output node308.

In one embodiment, transistors328and332are down-sized to reduce contention. Reducing contention increases the performance of the voltage level converter300.

The split-level output circuit304includes the first split-level input node311, the second split-level input node312, the split-level output node314, a first insulated-gate field-effect transistor (FET)334coupled to the first split-level input node311, and a second insulated-gate FET336coupled to the second split-level input node312. The first insulated-gate FET334is connected in series with the second insulated-gate FET336and a common node338is formed at the drain/source connection between the drain/source of the first insulated-gate FET334and the drain/source of the second insulated-gate FET336. The common node338is coupled to the split-level output node314.

The static voltage-level converter300, in one embodiment, is powered by a first voltage level, VCCH, and a second voltage level, VCCL, referenced to a third voltage level VLOW, with the first voltage level being greater than the second voltage. The first pair of transistors320and the second pair of transistors322are connected to the first voltage level and the third voltage level, and the inverter324is connected to the second voltage level and the third voltage level (not shown). The split level output circuit304is connected between the first voltage level and the third voltage level. This power design permits the INPUT SIGNAL having signal levels of VCCLand VLOWto be converted to the BUFFERED OUTPUT SIGNAL having signal levels of VCCHand VLOW.

In operation, the split-level output circuit304receives complementary inputs at the first split-level node311and the second split-level node312from the voltage-level converter302. The first insulated-gate field-effect transistor (FET)334and the second insulated-gate FET336are each preferably operating in the saturation region. For the first insulated-gate FET334operating in the saturation region and the second insulated-gate FET336operating in the saturation region, the split-level output circuit304can source and sink equal amounts of current and can pull the output node314to a first voltage level or a second voltage. Thus, the split-level output circuit304can drive the same loads as a single level output circuit.

FIG. 4Ais a block diagram of an alternative embodiment of a voltage-level converter400according to the teachings of the present invention. The voltage-level converter400includes a static voltage level converter402, a first transistor404, and a second transistor406. The static voltage level converter402includes an input node408, a first pull-up node410, a second pull-up node412, an inverter output node414, and an output node416. The first transistor404is coupled to the input node408and the first pull-up node410. The second transistor406is coupled to the inverter output node414and to the second pull-up node412.

The static voltage level converter402preferably comprises a circuit that consumes substantially zero power for static or unchanging inputs. Thus, for an input signal418having a logical zero voltage level or a logical one voltage level, the static voltage-level converter402consumes substantially zero power. The voltage-level converter400is not limited to use in connection with a particular static voltage-level converter402. Any static voltage-level converter that consumes substantially zero power for static or unchanging inputs is suitable for use in connection with the voltage-level converter400.

The first transistor404and the second transistor406are not limited to being fabricated in a particular technology. Any transistor capable of functioning as a switch in connection with the static voltage level converter402is suitable for use as the first transistor404and the second transistor406. In one embodiment, the first transistor404and the second transistor406are insulated-gate field-effect transistors (FETs). In an alternative embodiment, the first transistor404and the second transistor406are p-type insulated-gate FETs.

The first transistor404and the second transistor406function as switches that substantially eliminate current flow between a high voltage source (shown as VCCHinFIG. 4A) and a low voltage source (shown inFIG. 4A, not shown inFIG. 4B) during transitions of the INPUT SIGNAL at the input node408.

FIG. 4Bis a schematic diagram of one embodiment of the voltage-level converter400shown inFIG. 4Aaccording to the teachings of the present invention. The voltage-level converter400includes the static voltage level converter402, the first transistor404, and the second transistor406.

The static voltage level converter402includes the input node408, the first pull-up node410, the second pull-up node412, the inverter output node414, the output node416, a first pair of transistors420connected in series, a second pair of transistors422connected in series, and an inverter424. The first pair of transistors420includes a first transistor426and a second transistor428. The first transistor426is coupled to the input node408. The second pair of transistors422includes a first transistor430and a second transistor432. The second transistor432of the second pair of transistors422is cross-coupled with the second transistor428of the first pair of transistors420. Two transistors are cross-coupled by coupling a control port of a first transistor to a controlled port of a second transistor and by coupling a control port of a second transistor to a controlled port of the first transistor. As can be seen inFIG. 4B, the gate of the transistor428(the control port of the transistor428) is coupled to the drain/source of transistor432(the controlled port of transistor432) and the gate of the transistor432(the control port of transistor432) is coupled to the drain/source of transistor428(the controlled port of transistor428). The inverter424is coupled to the input node408, to the first transistor430of the second pair of transistors422, and to the output node416.

The first transistor404is coupled to the input node408and the first pull-up node410. The second transistor406is coupled to the inverter output node414and to the second pull-up node412.

The first transistor404provides a switch in the current path between node436and node438that improves the performance of the static voltage-level converter402during a low-to-high transition of the INPUT SIGNAL at input node408. During a low-to-high transition of the INPUT SIGNAL at the input node408, the first transistor404and the transistor426switch at about the same time but before the transistor428switches. Switching the first transistor404and the transistor426at about the same time substantially eliminates current flow between the node436and the node438, substantially eliminates voltage contention at the node440, and substantially eliminates power consumption in the current path between the node436and the node438.

The second transistor406provides a switch in the current path between the node442and the node444that improves the performance of the static voltage-level converter402during a high-to-low transition of the INPUT SIGNAL at input node408. During a high-to-low transition of the INPUT SIGNAL at the input node408, the second transistor406and the transistor430switch at about the same time but before the transistor432switches. Switching the second transistor406and the transistor432at about the same time substantially eliminates current flow between node442and node444, substantially eliminates voltage contention at node446, and substantially eliminates power consumption in the current path between node442and node444.

FIG. 4Cis a schematic diagram of the voltage-level converter400shown inFIG. 4Acoupled to an inverter440according to the teachings of the present invention. Coupling the voltage-level converter400to the inverter440improves the drive capability of the voltage-level converter400. In one embodiment, the inverter440is a single-input inverter.

FIG. 4Dis a schematic diagram of the voltage level converter400shown inFIG. 4Acoupled to a split-level output buffer441according to the teachings of the present invention. The split-level output buffer441is a multiple-input inverter. The split-level buffer441includes an n-type insulated-gate field-effect transistor (FET)452coupled to an output node444, a first p-type insulated-gate FET446coupled to the inverter output node448, and a second p-type insulated-gate FET450coupled to the static level converter402. The n-type insulated gate FET452, the first p-type insulated-gate FET446, and the second p-type insulated-gate FET450are connected in series.

All circuits in the voltage-level converter400, for the embodiments shown inFIGS. 4B-4D, are powered by the voltage level VCCHand the voltage level VLOWexcept for the inverter424, which is powered by the voltage level VCCL, which has a voltage value less than VCCH. This power design permits the INPUT SIGNAL having signal levels of VCCLand VLOWto be converted to the BUFFERED OUTPUT SIGNAL having signal levels of VCCHand VLOW.

FIG. 5Ais a block diagram of an alternative embodiment of a voltage-level converter500according to the teachings of the present invention. The voltage-level converter500includes a static voltage-level converter502, a first transistor504, and a second transistor506. The static voltage-level converter502includes an input node508and an output node510. The first transistor504is coupled to the input node508and the static voltage-level converter502. The second transistor506is coupled to the static voltage-level converter502.

The first transistor504and the second transistor507are preferably insulated-gate field-effect transistors (FETs), however the first transistor504and the second transistor507are not limited to insulated-gate FETs. The first transistor504and the second transistor507can be fabricated using any fabrication technology that is capable of producing transistors compatible with the static voltage-level converter502.

FIG. 5Bis a block diagram of one embodiment of the voltage-level converter500shown inFIG. 5Acoupled to an inverter508. The voltage-level converter is not limited to being coupled to a particular type of inverter. In one embodiment, as shown inFIG. 5C, the voltage-level converter500is coupled to a single-input converter512. In an alternative embodiment, as shown inFIG. 5D, the voltage-level converter500is coupled to a multiple-input inverter514.

FIG. 6Ais a schematic diagram of one embodiment of a voltage-level converter600according to the teachings of the present invention. The voltage-level converter600includes a static voltage-level converter602, a first transistor604, and a second transistor606. The static voltage-level converter602includes an input node608, a first pair of serially connected transistors610and611, a second pair of serially connected transistors612and613, and an inverter614. The input node608is connected to the transistor611. The inverter614couples the transistor611to the transistor613. The first transistor604is located between the transistor610and the transistor611and is coupled to the input node608. The second transistor606is located between the transistor612and the transistor613and is and coupled to the inverter614. The output node616is coupled to the transistor613.

The static voltage-level converter602is not limited to being fabricated using a particular technology. In one embodiment, the transistors610-611,612-613, and the inverter614are insulated-gate field effect transistors fabricated using a complementary metal-oxide semiconductor process.

The first transistor604and the second transistor606are also not limited to being fabricated using a particular technology. The first transistor604and the second transistor606can be fabricated using any fabrication technology, such as a complementary metal-oxide semiconductor (CMOS) process, that produces transistors that are compatible with the fabrication technology used to fabricate the static voltage-level converter602. In one embodiment, the first transistor604and the second transistor606are insulated-gate field-effect transistors fabricated using a CMOS process. In an alternative embodiment, the first transistor604and the second transistor606are p-type insulated-gate field-effect transistors fabricated using a CMOS process.

FIG. 6Bis a schematic diagram of the voltage-level converter600shown inFIG. 6Acoupled to a single-input buffer618according to the teachings of the present invention. The single-input buffer618is not limited to being fabricated using a particular technology. In one embodiment, the single-input buffer618comprises a pair of serially connected insulated-gate field-effect transistors fabricated using a complementary metal-oxide semiconductor (CMOS) process.

FIG. 6Cis a schematic diagram of the voltage-level converter600shown inFIG. 6Acoupled to a multiple-input buffer620according to the teachings of the present invention. In one embodiment, the multiple-input buffer620is a multiple-input inverter coupled to at least three outputs of the static voltage-level converter602. The multiple-input buffer620includes an n-type insulated-gate field-effect transistor (FET)621, a first p-type insulated-gate FET622, and a second p-type insulated-gate FET624. The n-type insulated-gate FET621, the first p-type insulated-gate FET622, and the second p-type insulated-gate FET624are connected in series, and the n-type insulated-gate FET621is coupled to the inverter614, the first p-type insulated-gate FET622is coupled to the node632, and the second p-type insulated-gate FET is coupled to the inverter614.

In each of the voltage-level converters600shown inFIGS. 6A-6C, the first transistor604provides a switch in the current path between node628and node630that improves the performance of the static voltage-level converter600during a low-to-high transition of the INPUT SIGNAL at the input node608. During a low-to-high transition of the INPUT SIGNAL at the input node608, the first transistor604and the transistor611switch at about the same time but before the transistor610switches. Switching the first transistor604and the transistor611at about the same time substantially eliminates current flow between the node628and the node630, substantially eliminates voltage contention at the node632, and substantially eliminates power consumption in the current path between the node628and the node630.

In each of the voltage-level converters600shown inFIGS. 6A-6C, the second transistor606provides a switch in the current path between node634and node636that improves the performance of the static voltage-level converter600during a high-to-low transition of the INPUT SIGNAL at input node608. During a high-to-low transition of the INPUT SIGNAL at the input node608, the second transistor606and the transistor613switch at about the same time but before the transistor612switches. Switching the second transistor606and the transistor612at about the same time substantially eliminates current flow between the node634and the node636, substantially eliminates voltage contention at the node638, and substantially eliminates power consumption in the current path between the node634and the node636.

Each of the voltage-level converters shown inFIGS. 3A-3B,FIGS. 4A-4D,FIGS. 5A-5D, andFIGS. 6A-6Cconsume less power than the current best methods for voltage-level conversion, can be used as a drop-in replacement for commonly used voltage-level converters, and avoids signal contention on internal nodes.

FIG. 7Ais a block diagram of some embodiments of a logic unit700including one or more first logic units702, one or more second logic units704, and a voltage-level converter706. The voltage-level converter706is coupled to at least one of the one or more first logic units702and at least one of the one or more second logic units704and couples signals generated by the one or more first logic units702to the one or more second logic units704.

The one or more first logic units702, in one embodiment, include logic units in a non-critical path or functional unit (see the Background for a definition of “non-critical path” and “non-critical functional unit”) coupled to a first node708powered at a first voltage level. Exemplary logic units in a non-critical path or functional unit include memory and storage circuits. The one or more second logic units704include logic circuits in a critical path or functional unit (see the Background for a definition of “critical path” and “critical functional unit”) coupled to a second node710powered at a second voltage level that is greater than the first voltage level. Exemplary critical path logic units include clock generation and distribution circuits. Exemplary critical functional units include arithmetic and logic circuits. In operation, the voltage-level converter706converts logic signals produced by the one or more first logic units702, such as storage or memory circuits, to logic signals compatible with the one or more second logic units704, such as clock distribution circuits.

The one or more first logic units702and the one or more second logic units704are preferably fabricated using a complementary metal-oxide semiconductor (CMOS) process. However, the one or more first logic units702and the one or more second logic units704are not limited to being fabricated using a CMOS process. Any process or technology used in the fabrication of logic circuits is suitable for use in connection with the present invention.

The logic unit700is not limited to use in connection with a particular voltage-level converter706. Some embodiments of the voltage-level converter706suitable for use in connection with the logic unit700include the voltage level converters shown inFIGS. 3A-3B,FIGS. 4A-4D,FIGS. 5A-5D, andFIGS. 6A-6C.

FIG. 7Bis a block diagram of one embodiment of the logic unit700shown inFIG. 7Aembedded in a communication unit712according to the teachings of the present invention. Exemplary communication units suitable for use in connection with the logic unit700include cell phones and cell phone base stations. However, the logic unit700is not limited to being embedded in a communication unit, and that the logic unit700can be embedded in any logic system that requires voltage level conversion. Exemplary logic systems in which the logic unit700can be embedded include microprocessors, digital signal processors, personal digital assistants, and application specific integrated circuits.

Although specific embodiments have been described and illustrated herein, it will be appreciated by those skilled in the art, having the benefit of the present disclosure, that any arrangement which is intended to achieve the same purpose may be substituted for a specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.