Semiconductor device and electric apparatus having a semiconductor layer divided into a plurality of square subregions

The present invention provides a semiconductor device and an electric apparatus each of which can realize both high-speed switching operation and energy loss reduction and excels in resistance to current concentration based on a counter electromotive voltage generated by, for example, an inductance load of the electric apparatus. A semiconductor device (100) of the present invention includes: a semiconductor layer (3) made of a first conductivity type wide band-gap semiconductor; a transistor cell (101T) in which a vertical field effect transistor (102) is formed, the vertical field effect transistor (102) causing a charge carrier to move in a thickness direction of the semiconductor layer (3); and a diode cell (101S) in which a Schottky diode (103) is formed, the Schottky diode (103) being formed such that a Schottky electrode (9) forms a Schottky junction with the semiconductor layer (3), wherein the semiconductor layer 3 is divided into a plurality of square subregions (101T and 101S) based on virtual border lines (30) in plan view, and includes the subregion (101T) as the transistor cell and the subregion (101S) as the diode cell.

RELATED APPLICATIONS

This application is the U.S. National Phase under 35 U.S.C. §371 of International Application No. PCT/JP2006/313575, filed on Jul. 7, 2006, which in turn claims the benefit of Japanese Application No. 2005-200517, filed on Jul. 8, 2005, the disclosures of which Applications are incorporated by reference herein.

TECHNICAL FIELD

The present invention relates to a semiconductor device and an electric apparatus, and particularly to an improvement technology of a power semiconductor device used for inverter control of various electric apparatuses.

BACKGROUND ART

In light of an energy loss reduction, a wide band-gap semiconductor (such as silicon carbide (SiC)) are attracting attention as a semiconducting material which goes beyond the limit of an existing Si power field effect transistor (hereinafter referred to as “Si-MISFET”).

Since a SiC semiconductor has a wide band gap, a drift region of a power field effect transistor (hereinafter referred to as “SiC-MISFET”) made of the SiC semiconductor has an excellent high withstand voltage performance. This realizes the reduction in thickness of the drift region which plays an important role to improve a conduction loss caused due to the decrease in an on-resistance (Ron) per unit area of a semiconductor device while securing a certain withstand voltage.

To be specific, since the wide band-gap semiconductor is used, the on-resistance of the SiC-MISFET is much lower than the on-resistance of the Si-MISFET, and is expected to be lower than the on-resistance of a Si-IGBT whose resistance value is 1 or more digits smaller than the on-resistance of the Si-MISFET. Therefore, compared to these existing switching elements, heat generated when the SiC-MISFET is ON can be suppressed, and the conduction loss of the SiC-MISFET can be kept low.

Moreover, since the SiC-MISFET is a unipolar device, its switching performance is advantageous in the increase in speed, compared to a bipolar device (for example, IGBT).

However, even in the case of the SiC-MISFET, by a parasitic diode comprised of a PN junction of a P-type region and an n-type region in a semiconductor device, a reverse recovery time delay may occur in the case of switching from an ON state of the parasitic diode to an OFF state of the SiC-MISFET when a reverse bias is applied.

For example, when a positive voltage that is a counter electromotive voltage generated by an inductance load when the switching element is turned off is applied to a source electrode, positive holes as minority carriers are implanted in the n-type region via the parasitic diode, and this causes the reverse recovery time delay of the operation of the parasitic diode.

In the past, the present inventors developed a semiconductor device in which a Schottky diode and a MISFET are incorporated as one chip, both a semiconductor region of the Schottky diode and a drift region of the MISFET being made of an SiC material (see Patent Document 1).

In the semiconductor device described in Patent Document 1 (hereinafter referred to as “conventional semiconductor device”), a metal electrode which forms a Schottky junction with an n-type epitaxial layer is provided on the surface of the n-type epitaxial layer existing between p-type wells of adjacent MISFETs. In this conventional semiconductor device, even assuming that the positive voltage is applied to the source electrode, and the positive holes as the minority carriers are implanted in the n-type region, the Schottky diode can quickly absorb the minority carriers (positive holes) as soon as a negative voltage is applied to the source electrode, and the reverse recovery time by the parasitic diode can be shortened.

Moreover, in this conventional semiconductor device, a forward rising voltage (about 1 V) of the Schottky diode is lower than a forward rising voltage (3 V) of the parasitic diode (PN junction). Therefore, when the positive voltage is applied to the source electrode, a forward current preferentially flows to the Schottky diode (the Schottky electrode has the same voltage as the source electrode). As a result, the implanting of the minority carriers via the parasitic diode is effectively avoided.

Furthermore, in this conventional semiconductor device, since the Schottky diode and the MISFET can be integrated in one chip, the reduction in space of the semiconductor device can be realized.

DISCLOSURE OF THE INVENTION

Problems to be Solved by the Invention

In the case of using the above conventional semiconductor device as the switching element composing a specific inverter power source circuit (for example, an inverter power source circuit for a three-phase motor of an air-conditioner compressor, etc.), there are the following problems for the practical application of such switching element.

The installation area of the metal electrode (Schottky electrode) of the Schottky junction does not cause harmful effects for the increase in speed of switching of the semiconductor device. However, considering that the forward voltage is applied to the parasitic diode in the MISFET and the Schottky diode, and the current is applied to these diodes, the installation area of the metal electrode is an important matter which should be considered in light of securing of an appropriate conduction ability.

In fact, the technology described in Patent Document 1 was applied to the inverter power source circuit for the three-phase motor. Discovered here was a possibility that the switching element breaks down due to the current which concentrates on the schottky electrode because of the counter electromotive voltage, as a trigger, generated based on the inductance load when the switching element is turned off.

Moreover, the schottky electrodes shown in FIG. 2 of Patent Document 1 are arranged in an orthogonal lattice manner in plan view so as to surround a field effect transistor region and be connected to a micro wiring. On this account, during fabrication of the semiconductor devices, the micro wiring tends to break, and this may become a factor for deteriorating fabrication yield of the semiconductor devices.

The present invention was made in view of these circumstances, and an object of the present invention is to provide a semiconductor device and an electric apparatus each of which can realize both high-speed switching operation and energy loss reduction and excels in resistance to current concentration based on the counter electromotive voltage generated by, for example, the inductance load of the electric apparatus.

Means for Solving the Problems

To solve the above problems, a semiconductor device according to the present invention comprises: a semiconductor layer made of a first conductivity type wide band-gap semiconductor; a transistor cell in which a vertical field effect transistor is formed, the vertical field effect transistor causing a charge carrier to move in a thickness direction of the semiconductor layer; and a diode cell in which a schottky diode is formed, the schottky diode being formed such that a schottky electrode forms a schottky junction with the semiconductor layer, wherein the semiconductor layer is divided into a plurality of square subregions based on virtual border lines in plan view and includes the subregion as the transistor cell and the subregion as the diode cell.

Note that the plurality of the subregions may be arranged in a matrix manner in two directions orthogonal to each other.

In accordance with the semiconductor device thus constructed, since the field effect transistor (switching element) made of the wide band-gap semiconductor and the schottky diode (built-in diode) using the wide band-gap semiconductor are used, it is possible to realize the increase in speed compared to the existing bipolar device (IGBT).

Moreover, the on-resistance of the field effect transistor made of the wide band-gap semiconductor is sufficiently smaller than that of the existing switching element (such as Si-MISFET or IGBT). Therefore, heat generated when the field effect transistor is ON can be suppressed, and the conduction loss can be kept low.

Furthermore, the schottky electrode can widely occupy substantially the entire area of the transistor cell. Therefore, for example, it is possible to take appropriate measures against the breakdown of the switching element due to the current which concentrates on the electrode of the schottky diode because of the counter electromotive voltage, as a trigger, generated based on the inductance load of the three-phase motor when the switching element is turned off.

The field effect transistor may include: a second conductivity type well provided on a surface of the semiconductor layer; a first conductivity type region provided inside the well; a drift region as the semiconductor layer other than the well and the region; a first source/drain electrode provided so as to contact the region and the well; a gate electrode provided on the well with an insulating layer disposed between the gate electrode and the well; and a second source/drain electrode connected to a back surface of the drift region in an ohmic manner.

The term “source/drain electrode” means that it can function as a source electrode of a transistor or a drain electrode of a transistor.

The diode cells may be provided so as to be surrounded by the transistor cells.

With this, the diode cell can be suitably provided on the surface of the drift region such that the area ratio of the surface area of all the diode cells to the surface area of all the subregions is kept within an appropriate range.

Specifically, a ratio of an area of all the transistor cells in plan view to an area of all the subregions in plan view may be more than 0.5 and not more than 0.99. In other words, a ratio of an area of all the diode cells in plan view to an area of all the subregions in plan view may be more than 0.01 and not more than 0.5.

Even when the area ratio of the surface area of all the diode cells to the surface area of all the subregions is set to 0.01 (1%) or 0.5 (50%), it is possible to reduce the loss compared to the semiconductor device adopting the conventional PN junction diode. Meanwhile, when the area ratio is 0.01 or less, the value of the current flowing in the schottky diode is likely to exceed its allowable current value. When the area ratio is more than 0.5, the tendency of the increase in the on-resistance is confirmed due to the decrease in the share of the area of the field effect transistor.

Moreover, in light of securing a space for vertically applying the drift current along a side wall surface of the second conductivity type well, a surface area of the well included in each of the transistor cells in plan view may be smaller than a surface area of the schottky electrode included in each of the diode cells in plan view.

The present invention is applicable to a semiconductor device having an inverter power source circuit of an AC driving device, and for example, to an apparatus in which the semiconductor device is incorporated as an arm module.

In accordance with the electric apparatus thus constructed, the conduction loss of the semiconductor device corresponds to a value obtained by multiplying the current by the voltage (current×voltage). Therefore, since the forward voltage of the schottky diode can be kept lower than the forward voltage of the conventional PN junction diode, the loss of the semiconductor device is improved compared to the existing semiconductor device adopting the PN junction diode.

Furthermore, the switching speed of the semiconductor device from the ON state to the OFF state increases. Therefore, the switching loss can be decreased.

A voltage applied to a built-in parasitic diode of the field effect transistor and the schottky diode based on a counter electromotive voltage generated by an inductance load in the AC driving device may be higher than a forward rising voltage of the schottky diode and lower than a forward rising voltage of the built-in parasitic diode.

One example of the AC driving device is an AC motor driven by the inverter power source circuit. The AC motor drives, for example, an air-conditioner compressor.

The above object, other objects, features, and advantages of the present invention will be made clear by the following detailed explanation of preferred embodiments with reference to the attached drawings.

Effects of the Invention

The present invention can provide a semiconductor device and an electric apparatus each of which can realize both high-speed switching operation and energy loss reduction and excels in resistance to current concentration based on the counter electromotive voltage generated by, for example, the inductance load of the electric apparatus.

EXPLANATION OF REFERENCE NUMBERS

21high voltage feed terminal

30ahorizontal border line

30bvertical border line

100H upper arm module

100L lower arm module

105inverter motor drive system

106three-phase inverter power source circuit

G gate terminal

S source terminal

D drain terminal

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a preferred embodiment of the present invention will be explained with reference to the drawings.

FIG. 1is a plan view showing one example of a construction of a semiconductor device according to an embodiment of the present invention.FIG. 2is a sectional view of the semiconductor device as taken along line A-A ofFIG. 1. In the following explanation, “n” and “p” denote a conductivity type, and in such type of layer or region, electrons or positive holes are carriers. In addition, “+” denotes high impurity concentration, and “−” denotes low impurity concentration.

As shown inFIGS. 1 and 2, in a semiconductor device100in plan view, a SiC layer3(semiconductor layer) is constructed such that a plurality of quadrangular (square, herein) subregions101T and101S are arranged evenly (equal area) in a matrix manner in two directions intersecting (orthogonal to) each other by a plurality of border lines30comprised of virtual horizontal border lines30aand virtual vertical border lines30b.

Among the subregions101T and101S arranged by the border lines30, there are a subregion corresponding to a transistor cell101T in which a vertical field effect transistor102(seeFIG. 2; hereinafter referred to as “SiC-MISFET102”.) which causes the electrons to move in a thickness direction of the SiC layer3is formed, and a subregion corresponding to a diode cell101S in which a schottky electrode9which forms a schottky junction with the SiC layer3(drift region3a) is formed.

For ease of explanation of the claims and description, the border lines30shown by two-dot chain lines inFIG. 1are virtual lines extending in a vertical direction or a horizontal direction so as to be located equidistant from the centers of adjacent subregions101T and from the centers of adjacent subregions101T and101S. The border lines30do not exist in a product obtained by embodying the present technology. Depending on the shape of the SiC-MISFET102or the schottky diode103, the border lines30shown are changed suitably.

Even when the subregions101T and101S are arranged by the virtual lines, the SiC-MISFET102or the schottky electrode9is formed in each of the subregions101T and101S. Therefore, as is easily understood from explanations regardingFIG. 1andFIG. 4described below, determining the centers of the gate electrode8and the schottky electrode9depending on their shapes determines the virtual border lines30. As a result, the subregions101T and101S can be specified.

As shown inFIG. 4, various arrangement patterns can be assumed as actual arrangements of the SiC-MISFET102and the schottky diode103. Therefore, examples for specifying the virtual border lines30, corresponding to respective arrangement patterns inFIG. 4, are explained with reference toFIG. 4.

For the purpose of simplification ofFIG. 4and the following explanation, the SiC-MISFET102is abbreviated as an element “T”, and the schottky diode103is abbreviated as an element “S”. In addition, for the sake of convenience of explanation, a direction in which the horizontal border line30aextends is referred to as an “X direction”, and an arrangement of respective elements (the number of which may be one) lined up in the X direction is referred to as a row direction arrangement. Moreover, a direction in which the vertical border line30bextends is referred to as a “Y direction”, and an arrangement of respective elements (the number of which may be one) lined up in the Y direction is referred to as a column direction arrangement.

FIG. 4(a) shows square elements T and S arranged in a matrix manner of 3 rows and 3 columns. Such arrangement pattern of the elements T and S is the same kind as that of the SiC-MISFET102and the schottky diode103shown inFIGS. 1 and 2.

FIG. 4(a) shows an example in which the square element S exists only in a center portion defined by the second row and the second column, however such example of the shape and the arrangement is just set appropriately for the purpose of explaining a specific example of the border lines30. For example, the specific shape of the elements T and S does not have to be square, and may be circular, triangular, or polygonal (pentagonal or more) as long as its center is determined properly.

When the elements T and S whose shapes are significantly different from each other (for example, the element T is square, and the element S is triangular) are mixedly arranged in the semiconductor device, an area ratio, described below, regarding the total number of the subregions101T and the total number of the subregions101S, may need to be modified based on a suitable correction coefficient.

Since the elements T and S existing in respective portions of 3 rows and 3 columns are square, a center Pij (i=1 to 3, j=1 to 3) of each element is uniquely determined as an intersection point of diagonal lines of the square as shown inFIG. 4(a).

The horizontal border line30ashown inFIG. 4(a) is a virtual line extending in the X direction so as to be located equidistant from centers P11and P21of a pair of elements T adjacent to each other in a column direction, centers P12and P22of the elements T and S adjacent to each other in the column direction, and centers P13and P23of a pair of elements T adjacent to each other in the column direction.

The vertical border line30bshown inFIG. 4(a) is a virtual line extending in the Y direction so as to be located equidistant from the centers P11and P12of a pair of elements T adjacent to each other in a row direction, the centers P21and P22of the elements T and S adjacent to each other in the row direction, and centers P31and P32of a pair of elements T adjacent to each other in the row direction.

The virtual border lines30other than the horizontal border line30aand the vertical border line30bshown inFIG. 4(a) can be easily specified with reference to the above explanation andFIG. 4(a), so that detailed explanations of these border lines30are omitted here.

FIG. 4(b) shows the square elements T and S arranged in a staggered manner (zigzag alignment). To be specific, each of the elements T and S constituting the second row shifts in the X direction by half a pitch of each of the elements T constituting the first row or the third row relative to each of the elements T constituting the first row or the third row. As shown inFIG. 4(b), the arrangement pattern of the elements T and S has 6 columns. As a result, the element T or S is not arranged in some of respective portions of 3 rows and 6 columns (for example, no element is provided in a portion defined by the second row and the third column).

FIG. 4(b) shows an example in which the square element S exists only in a portion defined by the second row and the fourth column, however such example of the shape and the arrangement is just set appropriately for the purpose of explaining a specific example of the border lines30. For example, the specific shape of the elements T and S does not have to be square, and may be circular, triangular, or polygonal (pentagonal or more) as long as its center is determined properly.

When the elements T and S whose shapes are significantly different from each other (for example, the element T is square, and the element S is triangular) are mixedly arranged in the semiconductor device, the area ratio, described below, regarding the total number of the subregions101T and the total number of the subregions101S, may need to be modified based on a suitable correction coefficient.

Since the elements T and S existing in proper places of respective portions of 3 rows and 6 columns are square, a center Pij (i=1 to 3, j=1 to 6, except for P12, P14, P16, P21, P23, P25, P32, P34and P36) of each element is uniquely determined as an intersection point of diagonal lines of the square.

The horizontal border line30a(shown by a thin chain double-dashed line inFIG. 4(b)) shown inFIG. 4(b) is a virtual line extending in the X direction so as to pass through a midpoint (The midpoint is shown by a black dot inFIG. 4(b). The same is true in the following explanation.) on a zigzag line200(dotted line) extending between the center P11of the element T defined by the first row and the first column and the center P22of the element T defined by the second row and the second column which elements are adjacent to each other in a row-column direction (oblique direction), a midpoint on the zigzag line200extending between the center P22of the element defined by the second row and the second column and the center P13of the element T defined by the first row and the third column which elements are adjacent to each other in the row-column direction, a midpoint on the zigzag line200extending between the center P13of the element T defined by the first row and the third column and the center P24of the element S defined by the second row and the fourth column which elements are adjacent to each other in the row-column direction, a midpoint on the zigzag line200extending between the center P24of the element S defined by the second row and the fourth column and the center P15of the element T defined by the first row and the fifth column which elements are adjacent to each other in the row-column direction, and a midpoint on the zigzag line200extending between the center P15of the element T defined by the first row and the fifth column and the center P26of the element T defined by the second row and the sixth column which elements are adjacent to each other in the row-column direction.

The vertical border line30b(shown by a thick chain double-dashed line inFIG. 4(b)) shown inFIG. 4(b) is a virtual line comprised of three Y portions30Y extending in the Y direction and two X portions30X connecting ends of the Y portions and extending in the X direction, so as to be located equidistant from the centers P11and P13of a pair of elements T adjacent to each other in the row direction, the centers P22and P24of the elements T and S adjacent to each other in the row direction, and the centers P31and P33of a pair of elements T adjacent to each other in the row direction.

The virtual border lines30other than the horizontal border line30aand the vertical border line30bshown inFIG. 4(b) can be easily specified with reference to the above explanation andFIG. 4(b), so that detailed explanations of these border lines30are omitted here.

FIG. 4(c) shows four rectangular elements T and S lined up in the X direction. To be specific, the elements T and S seamlessly extend in the Y direction and are arranged in a striped manner.

FIG. 4(c) shows an example in which the rectangular element S exists only in a portion defined by the third column, however such example of the shape and the arrangement is just set appropriately for the purpose of explaining a specific example of the border lines30. For example, the specific shape of the elements T and S does not have to be rectangular, and may be elliptical or triangular as long as its center is determined properly.

When the elements T and S whose shapes are significantly different from each other (for example, the element T is rectangular, and the element S is triangular) are mixedly arranged in the semiconductor device, the area ratio, described below, regarding the total number of the subregions101T and the total number of the subregions101S, may need to be modified based on a suitable correction coefficient.

Since the elements T and S are rectangular, a center Pij (i=1, j=1 to 4) of each element is uniquely determined as an intersection point of diagonal lines of the rectangle.

The vertical border line30bshown inFIG. 4(c) is a virtual line extending in the Y direction so as to be located equidistant from the centers P11and P12of a pair of elements T adjacent to each other in the row direction.

InFIG. 4(c), there are no elements T and S adjacent to each other in the column direction. Therefore, selected as the horizontal border lines are such a pair of virtual lines that a distance between one of the virtual lines and the center (P11, P12, P13and P14) of each of a plurality of (four, herein) elements T adjacently lined up in the row direction is equal to a distance between the other one of the virtual lines and the center (P11, P12, P13and P14) of each of the elements T. As an example of such virtual lines, a pair of horizontal border lines30aare shown, one of which passes through one side surfaces of the elements T and S and the other passes through the other side surfaces of the elements T and S.

The border lines30other than the horizontal border lines30aand the vertical border line30bshown inFIG. 4(c) can be easily specified with reference to the above explanation andFIG. 4(c), so that detailed explanations of these border lines30are omitted here.

FIG. 4(d) shows the square elements T arranged in a matrix manner and the rectangular element S. The arrangement pattern of the elements T and S shown inFIG. 4(d) is the same as the arrangement pattern of the elements T and S shown inFIG. 4(a) except that the element S inFIG. 4(d) occupies two subregions and extends in the Y direction so as to intersect the horizontal border line30a.

Therefore, explanations of the border lines30other than the horizontal border line30aintersecting the element S are omitted here.

The horizontal border line30a, shown inFIG. 4(d), intersecting the element S is a virtual line extending in the X direction so as to be located equidistant from the centers P21and P31of a pair of elements T adjacent to each other in the column direction and the centers P23and P33of a pair of elements T adjacent to each other in the column direction. To be specific, the horizontal border line30ais defined based on a pair of elements T existing on both sides of the element S in the X direction.

In many cases, the arrangement pattern and shape of the product manufactured by embodying the elements T and S are not manufactured according to its blueprint due to various disturbances. For example, due to mask displacement which occurs in the process of manufacturing the elements T and S, it may be difficult to specify the above-described border line which is located equidistant from the centers of the elements T and S.

In this case, the border line does not have to be located severely equidistant from the centers of the elements T and S in view of, for example, the manufacturing displacement of the elements T and S.

To be specific, the above-described examples for specifying the border lines are based on the assumption that the elements T and S are ideally manufactured according to its blueprint. The specifying of the border lines is suitably modified for each product embodying the elements T and S according to the product.

Thus, the subregions101T and101S are arranged by the virtual horizontal border lines30aand the virtual vertical border lines30bso that the square subregions101T and101S arranged in two directions intersecting each other are the same in area as each other. As a result, the area ratio, described below, can be appropriately obtained by using the total number of the subregions101T and the total number of the subregions101S.

The diode cells101S acting as the schottky diodes103are suitably distributed so that each diode cell101S is surrounded by the transistor cells101T acting as the SiC-MISFETs102. Thus, the number of the diode cells101S is properly adjusted relative to the number of the transistor cells101T.

More specifically, in the semiconductor device100, where the total number of the diode cells101S (subregions101S) acting as the schottky diodes103is A, and the total number of the transistor cells101T (subregions101T) acting as the SiC-MISFETs102is B, an area ratio (A/(A+B)) obtained by dividing the total number A of the diode cells101S acting as the schottky diodes103by the total number (A+B) of the subregions101S and101T is set in a numerical range of more than “0.01” to not more than “0.5” in view of the conduction loss of the semiconductor device100described below.

In brief, the area ratio (A/(A+B)) corresponds to a ratio of the area of all the diode cells101S (subregions101S) in plan view to the area of all the subregions101S and101T in plan view.

For the same purpose as above, an area ratio (B/(A+B)) obtained by dividing the total number B of the transistor cells101T acting as the SiC-MISFETs102by the total number (A+B) of the subregions101T and101S is set in a range of more than “0.5” to not more than “0.99”.

In brief, the area ratio (B/(A+B)) corresponds to a ratio of the area of all the transistor cells101T (subregions101T) in plan view to the area of all the subregions101S and101T in plan view.

As shown inFIG. 1of the partially enlarged view andFIG. 2, in the transistor cell101T, the SiC-MISFET102of the flat (planar) type includes: an n+-type semiconductor substrate2made of a SiC semiconductor; an n−-type SiC layer3which is formed on the surface of the semiconductor substrate2by the epitaxial growth method so as to have a predetermined thickness (10 μm for example); a p-type well4which is provided immediately below the surface of the SiC layer3and is square in plan view (seeFIG. 1of the enlarged view), and into which acceptors, such as aluminum ions, are implanted; an n+-type source region5which is provided in a region of the p-type well4and is square and annular in plan view (seeFIG. 1of the enlarged view), and into which donors, such as nitrogen ions, are implanted; a drift region3awhich is a portion of the SiC layer3other than the source region5and the p-type well4; a channel region4cwhich is a portion of the p-type well4, the portion being located around an outer periphery of the source region5, and is square and annular in plan view (seeFIG. 1of the enlarged view); a gate insulating film7which is deposited so as to cover the channel region4c, step over the outer periphery of the source region5, extend toward the inner side of the source region5and covers a part of the source region5, and is made of a SiO2material; a gate electrode8which is formed on the entire surface of the gate insulating film7so as to face the channel region4c, and is made of aluminum (Al); a source electrode6which covers a center portion of the p-type well4(portion located in a center opening of the source region5), steps over the inner periphery of the source region5, extends toward the inner side of the source region5and squarely and annularly covers a part of the source region5, and is square in plan view (seeFIG. 1of the enlarged view); and a drain electrode10which is formed on the entire back surface of the semiconductor substrate2so as to be connected to the back surface of the drain region3ain an ohmic manner.

Used as a material of the drain electrode10and the source electrode6is, for example, nickel (Ni).

As is easily understood fromFIGS. 1 and 2, a large number of the SiC-MISFETs102share the drift region3aand the drain electrode10, are integrated in one chip and are arranged in parallel.

As shown by dotted line arrows201inFIG. 2, electrons moving from the n+-type source region5toward the drain electrode10moves in a lateral direction (horizontal direction) in the vicinity of the p-type well4. Therefore, to secure a space for such movement of the electrons, the surface area of the p-type well4is set to be smaller than the surface area of the transistor cell101T (subregion101T).

Moreover, the gate insulating film7and the gate electrode8are formed on the entire surface of the SiC layer3except for contact holes H1and H2. Meanwhile, the contact hole H1is formed on the gate insulating film7so as to be located in the transistor cell101T, and the source electrode6is formed in the contact hole H1.

The source electrode6and the semiconductor (SiC layer3) are connected to each other in an ohmic manner by the source region5and the p-type well4, and the drain electrode10and the semiconductor (SiC layer3) are connected to each other in an ohmic manner by the semiconductor substrate2.

The SiC layer3(band gap of SiC: 3.02 eV) is made of a wide band-gap semiconductor whose band gap is wider than that of a silicon semiconductor (band gap: 1.11 eV) and that of a GaAs semiconductor (band gap: 1.43 eV).

The wide band-gap semiconductor is a semiconductor whose energy band gap (that is a material parameter which defines a property of a semiconductor) is wider than that of the silicon semiconductor and that of the GaAs semiconductor. In the present description, the term “wide band-gap semiconductor” is a generic name for semiconducting materials having the band gap of, for example, 2 eV or more.

In addition to SiC, examples of a wide band-gap semiconducting material are group III nitride, such as GaN (band gap: 3.39 eV) and AlN (band gap: 6.30 eV), and diamond.

As shown inFIG. 2, the schottky diode103is constructed such that the contact hole H2is formed on the gate insulating film7so as to be located in the diode cell101S, and the schottky electrode9(anode) which is rectangular (square, herein) in plan view ofFIG. 1and made of Ni is formed in the contact hole H2so as to cover the entire surface of the SiC layer3(drift region3a) of the diode cell101S. In view of avoidance of electric field concentration, corners of the rectangular schottky electrode9may be rounded.

Since the current flowing from the schottky electrode9toward the drain electrode10flows in a longitudinal direction (vertical direction) throughout the entire area of the diode cell101S, the surface area of the schottky electrode9is set to be substantially equal to the surface area of the diode cell101S (subregion101S), so that an adequately large amount of current can flow.

The drain electrode10is provided on the back surface of the semiconductor substrate2which faces the diode cell101S so as to step over a boundary between the transistor cell101T and the diode cell101S. Via the drain electrode10, a voltage is applied to the semiconductor (SiC layer3) that is a cathode of the schottky diode103.

Electric connection between the source electrodes6and electric connection between the source electrode6and the schottky electrode9are realized via a first wiring11(for example, a wiring constructed by a suitable interlayer insulating layer (not shown) and a suitable contact hole (not shown)). These source electrodes6and schottky electrodes9are connected to a ground potential (negative voltage) side of a power source via a source terminal S provided at an appropriate position of a semiconductor package (not shown).

That is, the schottky electrode9is electrically connected to the source electrode6via the first wiring11.

Via a gate wiring12(for example, a wiring constructed by the above interlayer insulating layer and a suitable contact hole (not shown)) and a gate terminal G provided at an appropriate position of the semiconductor package, a predetermined control signal voltage is applied between the source electrode6and the gate electrode8formed in an orthogonal lattice manner on substantially the entire surface of the SiC layer3except for the regions of the contact holes H1and H2in plan view (seeFIG. 2).

The drain electrode10is connected to a switching voltage (positive voltage) side of the power source via a drain terminal D provided at an appropriate position of the semiconductor package.

In the SiC-MISFET102of the semiconductor device100, a voltage that is positive with respect to the source electrode6is applied to the gate electrode8, so that the electrons are attracted by the channel region4c, and the channel region4cbecomes the n-type. As a result, a channel is formed. Thus, the SiC-MISFET102is turned ON. The electrons moving from the source region5via the channel region4cand the SiC layer3toward the drain electrode10mainly moves along routes shown by the dotted line arrows201ofFIG. 2. As a result, a drift current flows in the SiC layer3in the longitudinal direction.

Moreover, when the forward voltage based on the counter electromotive voltage generated by the inductance load of the three-phase motor for example is applied to the parasitic diode (diode based on the PN junction between the p-type well4and the n−-type SiC layer3) existing in the SiC-MISFET102and to the schottky diode103(between the source terminal S and the drain terminal D), the implanting of the minority carriers (positive holes) into the SiC layer3can be avoided appropriately by preferentially applying the forward current to the schottky diode103, since the forward rising voltage (about 1 V) of the schottky diode103is lower than the forward rising voltage (3 V) of the parasitic diode (PN junction).

For the same reason as above, when a momentary overvoltage, such as a surge voltage, is applied to the semiconductor device100, the overvoltage can be reduced by preferentially applying a leakage current, generated by the overvoltage, to the schottky diode103. As a result, dielectric breakdown of the SiC-MISFET102can be prevented.

Furthermore, regarding a surge current, since the schottky electrode9and a PN junction diode are connected in parallel, the schottky diode103allows a certain current, corresponding to a region where a forward voltage Vfis low, to flow at high speed, and the PN junction diode allows a large current, corresponding to a region where the forward voltage Vfis high, to flow. As a result, breakdown of the schottky diode103by current concentration can also be prevented.

That is, the semiconductor device100of the present embodiment is an element whose resistance to the surge voltage and the surge current are high.

Even if the minority carriers are implanted into the p-type well4and the source region5when the PN junction diode is ON, the minority carriers are absorbed by the schottky electrode9immediately after the reverse bias is applied, and the PN junction diode can be set to an OFF state immediately. On this account, the semiconductor device100of the present embodiment can suppress the occurrence of so-called latch-up (that is, an OFF operation is not carried out quickly) which is a concern in a conventional FET having only a PN junction diode.

As examples of the construction of the SiC-MISFET, there are a planar type in which a p layer and an n layer are planarly formed on a semiconductor layer, and a trench type in which a thin, deep groove is formed and a gate electrode and a gate insulating film are embedded therein. The SiC-MISFET102of the present embodiment has a planar construction in consideration of various reasons, described below, such as a relation with the schottky diode103.

As a publication describing a construction in which a trench type MISFET and a schottky diode are integrally formed, there is, for example, Published Japanese Translation of PCT Application 2005-501408 (hereinafter referred to as “prior example”).

In this prior example, a schottky junction portion of a semiconductor and a metal is formed on a bottom surface of a trench (dug groove or hole) to construct a schottky diode. A trench portion is originally a portion composing a gap of a transistor unit element portion, and is different from a transistor unit element (a plurality of square subregions101S and101T arranged based on the virtual border lines of the present embodiment).

Meanwhile, the schottky diodes103of the present embodiment occupy substantially the entire subregions101S that are a part of a plurality of square subregions101S and101T arranged based on the virtual border lines, which is totally different from the above construction in which the schottky electrode is embedded in (the trench portion of) the gap in the prior example.

Furthermore, the semiconductor device100of the planar construction of the present embodiment has such a structural flexibility that whether the SiC-MISFET102is provided or the schottky diode103is provided in a plurality of square subregions101S and101T arranged based on the virtual border lines can be selected arbitrarily. Therefore, the semiconductor device100of the planar construction of the present embodiment is advantageous over the semiconductor device adopting the trench construction as in the prior example. That is, with such structural flexibility, it is possible to embody the design concept (the area ratio between the SiC-MISFET102and the schottky diode103can be set arbitrarily) of the present embodiment.

Moreover, in the prior example, it is necessary to form the gate electrode on a trench wall surface with the gate insulating film disposed between the gate electrode and the trench wall surface, secure insulation by an interlayer insulating film, and further form the schottky electrode thereon. In the case of forming the above-described insulating film, electrode film and insulating film on the trench wall surface, it is difficult to form the schottky electrode, having a large area, on the bottom surface portion of the trench covered by the above-described multiple layers, and only a part of the bottom surface of the trench functions as the schottky diode. Therefore, the area for forming the diode is limited to be small, which is problematic. Meanwhile, in the semiconductor device100of the planar construction of the present embodiment, it is possible to appropriately solve such problem regarding the limitation of the area.

Moreover, in the case of forming the schottky electrode on the bottom surface of the trench in the prior example, the schottky electrode is located near the drain electrode on the back surface. Therefore, an electric field concentration occurs at the schottky electrode, so that the withstand voltage of the schottky electrode is a concern. However, in the semiconductor device100of the planar construction of the present embodiment, the schottky electrode9is formed on the surface of the SiC layer9, whereas the p-type well4in the adjacent SiC-MISFET102is formed deep. Therefore, the electric field concentration does not occur at the schottky electrode9, and the withstand voltage is secured appropriately.

As described above, the semiconductor device100of the present embodiment adopting the planar construction is advantageous over the semiconductor device having the trench construction described in the prior example in that the area ratio between the SiC-MISFET102and the schottky diode103can be set arbitrarily, the withstand voltage can be secured appropriately, and the process of manufacturing the semiconductor device100can be simplified.

Moreover, in view of the resistance to high current and resistance to high voltage (described later) of the diode, the schottky diode103of the present embodiment uses the schottky electrode9, made of Ni, as the anode, and the wide band-gap semiconductor (the SiC layer3herein as one example) as the cathode.

Assuming that the schottky diode is constructed using Ni as the anode and silicon as the cathode, it is difficult to supply high current to the schottky diode. That is, if the high current is applied to such schottky diode, a silicide layer tends to be formed at an interface between the silicon and Ni. As a result, these may be connected to each other in an ohmic manner, and may not function as a diode.

This case may stand against such a principle of the present embodiment for solving the problems that the dielectric breakdown of the SiC-MISFET can be prevented by preferentially applying the leakage current, generated by the overvoltage, to the schottky electrode.

Meanwhile, assuming that the schottky diode is constructed using Ni as the anode and the wide band-gap semiconductor (the SiC layer3as one example) as the cathode, the silicide layer is not substantially formed by a normally-performed conduction operation, which is preferable in view of the resistance to high current and resistance to high voltage of the diode.

That is, in the present embodiment, the structural difference regarding the cathode of the schottky diode103(difference regarding whether the cathode is silicon or SiC) is not just a design matter determined by a person with ordinary skill in the art, but a matter which directly leads to the above principle for solving the problems.

Furthermore, in the case of providing the diode on a peripheral portion, to which a high voltage is applied, of the semiconductor device100, the schottky diode adopting Ni as the anode and SiC as the cathode excels in the withstand voltage compared to the schottky diode adopting Ni as the anode and silicon as the cathode.

Although the PN junction diode excels in both the resistance to high current and the resistance to high voltage, the loss of the semiconductor device by the increase of the forward voltage Vfincreases in the case of the PN junction diode adopting Ni as the anode and SiC as the cathode.

Next, a method for manufacturing the semiconductor device100according to the present embodiment will be explained with reference toFIG. 2.

Drawings showing components in the process of respective manufacturing steps are omitted. Therefore, when explaining the present manufacturing method, the reference numerals of the finished product shown inFIG. 2are used for convenience as the reference numbers of respective components in the process of manufacturing steps.

First, prepared is the semiconductor substrate2having an offcut surface which is inclined in a [11-20] direction at 8 degrees from an n+-type 4H-SiC(0001)Si surface in which nitrogen is doped so that the nitrogen concentration is 3×1018cm−3.

Next, after the semiconductor substrate2is cleaned, the SiC layer3as a nitrogen-doped n−-type epitaxial layer whose nitrogen concentration is adjusted to 1.3×1016cm−3is formed on the offcut surface by CVD so as to have a thickness of 10 μm.

Then, a mask (not shown) having openings is disposed on the surface of the SiC layer3such that the openings are located at appropriate positions of the surface of the SiC layer3, multistage ion energy in a range of 30 to 700 keV directed toward the surface of the SiC layer3is suitably selected, and aluminum ion is implanted via the openings in a dose amount of 2×1014cm−2. This ion implantation forms the p-type wells4, each having a depth of about 0.8 μm, on the surface of the SiC layer3in an island manner.

After that, using another mask (not shown) having openings being disposed on the surface of the p-type well4such that the openings are located at appropriate positions of the surface of the p-type well4, nitrogen ion whose energy is 30 to 180 keV is implanted in the p-type wells4in a dose amount of 1.4×1015cm−2so as to form the n+-type source regions5.

The semiconductor substrate2is subjected to an Ar atmosphere, kept at a temperature of 1,700 degrees C. and subjected to a heat treatment for about an hour, so that the above ion implanted regions are activated.

Next, the semiconductor substrate2is kept at a temperature of 1,100 degrees C. in an oxidation treatment furnace so as to be subjected to wet oxidation for three hours. This oxidation treatment forms a silicon oxide film (This film acts as a gate insulating film7eventually.), having a thickness of 40 nm, on the entire surface of the SiC layer3.

The contact holes H1and H2are patterned on the silicon oxide film using photolithography and etching.

Then, the source electrode6made of Ni is provided on the surface of the SiC layer3inside the contact hole H1, and the drain electrode10made of Ni is provided on the back surface of the semiconductor substrate2. After depositing these Ni layers, a suitable heat treatment is carried out. Thus, the electrode6and the semiconductor (SiC layer3) are connected to each other in an ohmic manner via the source region5and the p-type well4, and the electrode10and the semiconductor (SiC layer3) are connected to each other in an ohmic manner via the semiconductor substrate2.

Moreover, the gate electrode8made of Al and the gate wiring12are selectively patterned on the surface of the silicon oxide film.

Furthermore, the schottky electrode9made of Ni is selectively patterned on the surface of the SiC layer3exposing at the bottom of the contact hole H2.

Thus, the semiconductor device100(withstand voltage of 600V, rated current of 20 A in a square of 3 mm×3 mm) is obtained.

The following will describe an example in which the semiconductor device100according to the present embodiment is applied to an inverter power source circuit that is a power electronics control device of an electric apparatus.

FIG. 3is a view showing one example of a construction of an inverter motor drive system in which the semiconductor device according to the present embodiment is applied to a drive of a three-phase motor of an air-conditioner compressor.

As shown inFIG. 3, an inverter motor drive system105includes a three-phase inverter power source circuit106and a three-phase (AC) motor107(AC driving device).

The three-phase inverter power source circuit106includes six upper and lower arm modules100H and100L (semiconductor devices) each constructed such that a circuit made by connecting the SiC-MISFET102and the schottky diode103in antiparallel is integrated in one chip.

More specifically, the three-phase inverter power source circuit106is constructed by connecting three pairs108of arm modules (hereinafter referred to as “phase switching circuit108”) in parallel, each pair being constructed by connecting, in series, the source terminal S (seeFIG. 2) of the upper arm module100H and the drain terminal D (seeFIG. 2) of the lower arm module100L.

Moreover, in each phase switching circuit108, the drain terminal D of the upper arm module100H is connected to a high voltage feed terminal21, and the source terminal S of the lower arm module100L is connected to a ground terminal22.

Moreover, respective connection portions (midpoints)110where the source terminal S of the upper arm module100H and the drain terminal D of the lower arm module100L are connected are respectively connected to three input terminals20of the three-phase motor107.

Gate terminals G (seeFIG. 2) of the upper and lower arm modules100H and100L are connected to a control circuit (not shown) including a suitable inverter microcomputer.

In the inverter motor drive system105, by adjusting ON and OFF timings of the upper arm module100H and the lower arm module100L provided in each phase switching circuit108, it is possible to modulate the voltage of the connection portion110corresponding to the midpoint of each phase switching circuit108.

In short, the voltage of the connection portion110is a ground potential when the lower arm module100L is ON and the upper arm module100H is OFF, and is a predetermined high voltage when the lower arm module100L is OFF and the upper arm module100H is ON.

Thus, in accordance with the switching frequency of ON or OFF of the upper and lower arm modules100H and100L, it is possible to change the power source frequency of the three-phase motor107to which power is supplied by the three-phase inverter power source circuit106via the connection portion110, and also possible to change the rotating speed of the three-phase motor107freely, continuously and efficiently.

Since the inverter motor drive system105uses the SiC-MISFETs102(switching elements) and the schottky diodes103(built-in diodes), it can realize the increase in speed compared to the existing bipolar device (IGBT).

Therefore, the switching of the upper and lower arm modules100H and100L from ON to OFF is carried out in a short period of time, this removes the limitation of the upper limit of the frequency of the three-phase inverter power source circuit106, and the switching loss of the three-phase inverter power source circuit106is improved.

As one example of specific data, a high frequency (100 kHz, or higher) switching operation was confirmed in the upper and lower arm modules100H and100L (withstand voltage of 600 V, rated current of 20 A in a square of 3 mm×3 mm,), and the switching loss in this case was 5% or less.

Moreover, the on-resistance of a region where the SiC-MISFET102is formed is sufficiently small compared to the existing switching element (such as Si-MISFET or IGBT). Therefore, the heat generated when the SiC-MISFET102in the inverter motor drive system105is ON can be suppressed, and the conduction loss can also be kept low.

Furthermore, in the schottky diode103built in each of the upper and lower arm modules100H and100L, the schottky electrode9can widely occupy substantially the entire diode cell101S. Therefore, it is possible to take appropriate measures against the breakdown of the switching element due to the current which concentrates on the schottky electrode9because of the counter electromotive voltage, as a trigger, generated based on the inductance load of the three-phase motor107when the switching element is turned off.

Next, the following will explain examples of operations of the upper and lower arm modules100H and100L. In these examples, the loss of the inverter motor drive system105is considered using, as a parameter, the area ratio (A/(A+B)) of the area (A; the total number of the diode cells101S) of the diode cells101S in plan view to the area (A+B) of all the subregions101T and101S in plan view.
[Area Ratio (A/(A+B))=0.01 (1%)]

The on-resistance per unit area of a region where the schottky diode103in each of the upper and lower arm modules100H and100L (withstand voltage of 600 V, rated current of 20 A in a square of 3 mm×3 mm) is formed is about 1 mΩcm2.

Moreover, the SiC layer3located immediately below the p-type well4of the SiC-MISFET102does not sufficiently function as a conduction region as shown by the dotted line arrows201inFIG. 2, whereas the SiC layer3located immediately below the schottky electrode9of the schottky diode103functions as the conduction region throughout its entire region. Therefore, the averaged on-resistance per unit area of the region where the SiC-MISFET102is formed is about 1 digit larger (10 mΩcm2) than that of the schottky diode103.

A contact resistance between the schottky electrode9and the SiC layer3is about 2 digits smaller than the on-resistance of the region where the schottky diode103is formed, and this resistance is negligible.

The current applied to the SiC-MISFET102and the schottky diode103is estimated from the above-described on-resistance of the region where the SiC-MISFET102is formed and on-resistance of the region where the schottky diode103is formed. When the area ratio (A/(A+B)) is set to 0.01 (the surface area of the diode cells101S: the surface area of the subregions101T and101S≈1:100), the current of about 20 A/cm2(current density of the entire element) can be applied to the schottky diode103if the forward voltage Vfof the schottky diode103including the forward rising voltage (about 1 V) generated by a schottky barrier is about 3 V (the increase in the forward voltage Vfby a current which flows through a resistor is 2 V).

The above-described voltage value (3 V) corresponds to the lowest forward voltage (that is, the voltage due to a voltage dropped by a junction barrier of the PN junction) when the forward current is applied to the parasitic diode of the PN junction built in the SiC-MISFET102. Therefore, the current is preferentially applied to the schottky diode103if the forward voltage Vfis kept to 3 V or less when the forward current is applied to the schottky diode103.

At this time, the conduction loss of the upper and lower arm modules100H and100L corresponds to a value obtained by multiplying the current by the voltage (current×voltage). Since the forward voltage Vfof the schottky diode103can be kept lower than the forward voltage Vfof the conventional PN junction diode, the loss of the upper and lower arm modules100H and100L adopting the schottky diodes103is expected to be improved compared to the existing arm module adopting the PN junction diode.

More specifically, when the area ratio (A/(A+B)) of the surface area (A) of all the diode cells101S in the upper and lower arm modules100H and100L to the surface area (A+B) of all the subregions101T and101S in the upper and lower arm modules100H and100L is set to 0.01(1%), the switching loss decreases due to the increase in an OFF speed, about 2% of the decrease in the loss is confirmed compared to the existing arm module adopting the PN junction diode, and the improvement effect of the loss of the inverter motor drive system105is achieved even if the ratio of the schottky diodes103is low (1%).

At this time, the averaged on-resistance per unit area of the region where the SiC-MISFET102is formed is 10 mΩcm2. Therefore, the current density when the SiC-MISFET102is ON (hereinafter referred to as “ON current density”) is estimated at 200 A/cm2when the increase in the forward voltage Vfis 2 V. Note that the current when the SiC-MISFET102is ON (hereinafter referred to as “ON current”) flows in a direction opposite the direction of the current flowing in the schottky diode103.

That is, when the current whose current density is about 1/10 of the ON current density of the SiC-MISFET102is applied to the schottky diode103in a direction opposite the direction of the ON current, it is preferable that the area ratio (A/(A+B)) be set to 0.01 (1%).

During an experiment of a continuous operation of the upper and lower arm modules100H and100L, the operations of the upper and lower arm modules100H and100L were not stable due to the heat generation of the upper and lower arm modules100H and100L in some cases. This is estimated to be caused since the current flowing in the schottky diode103has exceeded the above-described allowable current (20 A/cm2).

Therefore, it is desirable that the above-described ratio be set to a value of more than 0.01 in consideration of the current capacity limit of the region where the schottky diode103of the upper and lower arm modules100H and100L is formed.
[Area Ratio (A/(A+B))=0.1 (10%)]

When the area ratio (A/(A+B)) of the surface area (A) of all the diode cells101S in the upper and lower arm modules100H and100L to the surface area (A+B) of all the subregions101T and101S in the upper and lower arm modules100H and100L is set to 0.1 (10%), the allowable value of the current flowing in the schottky diode103is about 200 A/cm2(current density of the entire element). Thus, a malfunction caused by the shortage of the current allowable amount of the schottky diode103is solved. In this case, about 5% of the decrease in the loss is confirmed compared to the existing arm module adopting the PN junction diode, and the sufficient improvement effect of the loss of the inverter motor drive system105is achieved.

At this time, the averaged on-resistance per unit area of the region where the SiC-MISFET102is formed is 10 mΩcm2. Therefore, the ON current density of the SiC-MISFET102is estimated at 200 A/cm2when the increase in the forward voltage Vfis 2 V. Note that the ON current of the SiC-MISFET102flows in a direction opposite the direction of the current flowing in the schottky diode103.

That is, when the current whose current density is equal to the ON current density of the SiC-MISFET102is applied to the schottky diode103in a direction opposite the direction of the ON current, it is preferable that the area ratio (A/(A+B)) be set to 0.1 (10%).
[Area Ratio (A/(A+B))=0.5 (50%)]

As described above, the averaged on-resistance per unit area of the region where the SiC-MISFET102is formed is about 10 mΩcm2. In the future, however, the on-resistance of the region where the SiC-MISFET102is formed can be decreased by, for example, the reduction in the channel resistance of the SiC-MISFET. As a result, the averaged on-resistance becomes close to the on-resistance (1 mΩcm2) of the region where the schottky diode103is formed.

Although the on-resistance of the region where the SiC-MISFET102is formed does not become smaller than the on-resistance of the region where the schottky diode103is formed, these on-resistances may become substantially equal to each other. In this case, when the ON current densities of the ON currents respectively flowing in the SiC-MISFET102and the schottky diode103are equal to each other (note that the directions of these currents are opposite to each other), it is preferable that the area ratio (A/(A+B)) be set to 0.5 (50%).

When the area ratio (A/(A+B)) of the surface area (A) of all the diode cells101S in the upper and lower arm modules100H and100L to the surface area (A+B) of all the subregions101T and101S in the upper and lower arm modules100H and100L is set to 0.5 (50%), about 1% of the decrease in the loss is confirmed compared to the existing arm module adopting the PN junction diode, and the improvement effect of the loss of the inverter motor drive system105is achieved even if the ratio of the schottky diodes103is high (50%).

When the area ratio (A/(A+B)) is set to more than 0.5, the increase in the on-resistance is confirmed due to the decrease in the share of the area of the region where the SiC-MISFET is formed. Therefore, the increase in the loss of the upper and lower arm modules100H and100L becomes a concern.

Furthermore, since stable operations are expected when the current flowing in the schottky electrode9is from 200 to 600 A/cm2(current density of the entire element), a desirable range of the area ratio (A/(A+B)) is 0.1 to 0.3.

As described above, in a case where the ON current densities of the ON currents respectively flowing in the SiC-MISFET102and the schottky diode103are equal to each other (note that the directions of these currents are opposite to each other), the area ratio (A/(A+B)) may be set to 0.1 when the on-resistance of the region where the schottky diode103is formed is 1/10 of the on-resistance of the region where the SiC-MISFET102is formed, and the area ratio (A/(A+B)) may be set to 0.3 when the on-resistance of the region where the schottky diode103is formed is ⅓ of the on-resistance of the region where the SiC-MISFET102is formed.

In the above embodiment, the SiC-MISFET is explained using the N channel type MISFET as an example. However, the semiconductor device100(arm module) according to the present embodiment can be constructed by using a P channel type MISFET in which the source electrode and the drain electrode are reversed.

Moreover, in the above embodiment, an example in which the gate electrode is made of aluminum is explained. However, instead of aluminum, the gate electrode may be made of polysilicon. Even when the gate electrode is made of polysilicon, the same operational effects as above can be obtained.

Moreover, in the present embodiment, an example in which nickel (Ni) is used as materials of the schottky electrode9, the source electrode6and the drain electrode10. However, the materials of the electrodes6,9and10are not limited to this, and may be a metal, such as titanium (Ti), aluminum (Al) or molybdenum (Mo).

From the foregoing explanation, many modification and other embodiments of the present invention are obvious to one skilled in the art. Therefore, the foregoing explanation should be interpreted only as an example, and is provided for the purpose of teaching the best mode for carrying out the present invention to one skilled in the art. The structures and/or functional details may be substantially modified within the spirit of the present invention.

INDUSTRIAL APPLICABILITY

A semiconductor device according to the present invention can realize both high-speed switching operation and energy loss reduction and excels in resistance to current concentration based on a counter electromotive voltage generated by, for example, an inductance load of an electric apparatus, and is applicable to a high-speed inverter power source circuit of, for example, electric apparatus.