Data storage apparatus utilizing sequential map entry for responding to read request and operating method thereof

A data storage apparatus includes a nonvolatile memory device including block groups, a random access memory including a sequential map table that stores a sequential map entry for consecutive sequential write logical addresses, among write addresses received from a host apparatus, greater than or equal to a predetermined threshold number, and a processor configured to determine whether or not first sequential write logical addresses are present among logical addresses corresponding to physical addresses for a first region of a first block group when a write operation for the first region of the first block group in response to a write request received from the host apparatus is completed, generate a first sequential map entry for the first sequential write logical addresses when the first sequential write logical addresses are present, and store the first sequential map entry in the sequential map table.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2018-0005728, filed on Jan. 16, 2018, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments of the present invention generally relate to a semiconductor apparatus. Particularly, the embodiments relate to a data storage apparatus and an operating method thereof.

2. Related Art

The computing environment paradigm has recently changed to ubiquitous computing, which enables computer systems to be used anytime and anywhere. As a result, use of portable electronic apparatuses such as mobile phones, digital cameras, and laptop computers has been increasing rapidly. Generally, portable electronic apparatuses use data storage apparatuses that employ memory devices. Data storage apparatuses may be used to store data used in the portable electronic apparatuses.

Since they have no mechanical driving units, data storage apparatuses using memory devices have advantages such as good stability and endurance, high information access rate, and low power consumption. Such data storage apparatuses may include a universal serial bus (USB) memory device, a memory card having various interfaces, a universal flash storage (UFS) device, a solid state drive (SSD), and the like.

SUMMARY

Embodiments are provided to a data storage apparatus with improved read performance and an operating method thereof.

In an embodiment of the present disclosure, a data storage apparatus may include: a nonvolatile memory device including a plurality of block groups; a random access memory including a sequential map table that stores a sequential map entry for consecutive sequential write logical addresses, among write addresses received from a host apparatus, greater than or equal to a predetermined threshold number; and a processor configured to determine whether or not first sequential write logical addresses are present among logical addresses corresponding to physical addresses for a first region of a first block group when a write operation for the first region of the first block group in response to a write request received from the host apparatus is completed, generate a first sequential map entry for the first sequential write logical addresses when the first sequential write logical addresses are present, and store the first sequential map entry in the sequential map table.

In an embodiment of the present disclosure, an operating method of a data storage apparatus, the method may include: determining whether or not consecutive first sequential logical addresses that are greater than or equal to a predetermined threshold number are present based on physical to logical (P2L) entries stored in an address buffer when map updating operation is performed; and generating a first sequential map entry including a start logical address for the first sequential logical addresses, a logical address length, and a start physical address corresponding to the start logical address when the first sequential logical addresses are present.

In an embodiment of the present disclosure, a memory system may include: a memory device; and a controller configured to generate, during a write operation, a sequential map entry having a start logical address, length of consecutive logical addresses from the start logical address and a start physical address corresponding to the start logical address; and control the memory device to perform a read operation by providing a read-requested physical address. The controller obtains the read-requested physical address based on the start logical address, a read-requested logical address, and the start physical address.

According to embodiments, a sequential map entry for preset threshold number or more consecutive sequential logical addresses may be separately generated and stored in the random access memory and the sequential logical addresses may be converted to corresponding physical addresses using the sequential map entry in response to a random read request from a host apparatus. Accordingly, the unnecessary map read operation is reduced and thus random read performance may be improved.

As logical to physical (L2P) entries for a sequential write may be simplified and then stored as one sequential map entry only including a start logical address, a logical address length, and a start physical address, a space for map data storage may be reduced and a map coverage may be improved.

DETAILED DESCRIPTION

Various embodiments of the present invention are described below in more detail with reference to the accompanying drawings. We note, however, that the present invention may be embodied in different forms and variations, and should not be construed as being limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the present invention to those skilled in the art to which this invention pertains. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. It is noted that reference to “an embodiment” does not necessarily mean only one embodiment, and different references to “an embodiment” are not necessarily to the same embodiment(s).

The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments.

As used herein, singular forms may include the plural forms as well and vice versa, unless the context clearly indicates otherwise.

The present invention is described herein with reference to cross-section and/or plan illustrations of idealized embodiments of the present invention. However, embodiments of the present invention should not be construed as limiting the inventive concept. Although a few embodiments of the present invention will be shown and described, it will be appreciated by those of ordinary skill in the art that changes may be made in these embodiments without departing from the principles and spirit of the present invention.

FIG. 1is a block diagram illustrating a configuration example of a data storage apparatus10according to an embodiment. The data storage apparatus10according to an embodiment may store data to be accessed by a host apparatus (not shown) such as, for example, a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game player, a television (TV), or an in-vehicle infotainment system, and the like. The data storage apparatus10may refer to a memory system.

The data storage apparatus10may be manufactured as any one among various types of storage apparatuses according to a host interface which refers to a transfer protocol with a host apparatus (not shown). For example, the data storage apparatus10may be configured of any one of various types of storage apparatuses, such as a solid state drive (SSD), a multimedia card in the form of an MMC, an eMMC, an RS-MMC, and a micro-MMC, a secure digital card in the form of an SD, a mini-SD, and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnection (PCI) card type storage device, a PCI-express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, a memory stick, and the like.

The data storage apparatus10may be manufactured as any one among various types of packages. For example, the data storage apparatus10may be manufactured as any one of various types of packages, such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-level fabricated package (WFP), and a wafer-level stack package (WSP).

Referring toFIG. 1, the data storage apparatus10may include a nonvolatile memory device100and a controller200.

The nonvolatile memory device100may be operated as a storage medium of the data storage apparatus10. Non-limiting examples of the nonvolatile memory device100may include any one of various types of nonvolatile memory devices, such as a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a magnetic random access memory (MRAM) using a tunneling magneto-resistive (TMR) layer, a phase-change random access memory (PRAM) using a chalcogenide alloy, and a resistive random access memory (RERAM) using a transition metal compound, according to a memory cell constituting the nonvolatile memory device.

The nonvolatile memory device100may include a memory cell array including a plurality of memory cells (not shown) arranged in regions in which a plurality of word lines (not shown) and a plurality of bit lines (not shown) cross each other. The memory cell array may include a plurality of memory blocks and each of the plurality of memory blocks may include a plurality of pages.

For example, each of the memory cells in the memory cell array may be at least one among a single level cell (SLC) in which a single bit data (for example, 1-bit data) is stored, a multilevel cell (MLC) in which 2-bit data is stored, a triple level cell (TLC) in which 3-bit data is stored, and a quad level cell QLC in which 4-bit data is stored. The memory cell array may include at least one or more cells among the SLC, the MLC, the TLC, and the QLC. For example, the memory cell array may include memory cells having a two-dimensional (2D) horizontal structure or memory cells having a 3D vertical structure.

FIG. 2Ais a diagram illustrating a configuration example of a nonvolatile memory device ofFIG. 1andFIG. 2Bis a diagram illustrating a configuration example of a super block ofFIG. 2A. Although the example of a first super block SB1is illustrated inFIG. 2A, the other super blocks, for example, second to k-th super blocks SB2to SBk may have the same configuration as the configuration of the first super block SB1. AlthoughFIG. 2Ashows, as an example, that the nonvolatile memory device100includes four dies D1to D4, the number of dies included in the nonvolatile memory device100is not limited thereto. AlthoughFIG. 2Bshows, as an example, that the four pages P1to P4are included in one block B and four sectors S are included in each of the pages P1to P4, the number of pages included in each block and the number of sectors included in each page are not limited thereto.

Referring toFIG. 2A, the nonvolatile memory device100may include first to fourth dies D1to D4. Each of the first to fourth dies D1to D4may include a plurality of memory blocks B1to Bk. Although not shown inFIG. 2A, each of the dies D1to D4may include a plurality of planes including a plurality of memory blocks.

Referring toFIG. 2A, the same memory blocks in the dies D1to D4may be grouped into one memory block group. The one memory block group in which the same memory blocks in the dies D1to D4are grouped may refer to a super block. The first memory blocks B1in the dies D1to D4may be grouped into and used as the first super block SB1. The nonvolatile memory device100may include k super blocks, for example, first to k-th super blocks SB1to SBk. The controller200may operate the four memory blocks included in each of the super blocks SB1to SBk in parallel.

For example, the controller200may control the nonvolatile memory device100to simultaneously perform the read/write operation on four first memory blocks B1included in the first super block SB1. Referring toFIG. 2B, each of the four first memory blocks B1included in the first super block SB1may include four pages P1to P4and each of the pages P1to P4may include four sectors S. Accordingly, the first super block SB1may include total64sectors S1to S64.

Write data received from a host apparatus may be sequentially stored in the first super block SB1in an arrow direction indicated by a dotted line inFIG. 2B. For example, the write data may be sequentially stored from a first sector S1to a 64-th sector in a write operation for the first super block SB1. When the write data are stored from the first sector to the 64-th sector, map updating operation on the first super block SB1may be performed. The map updating operation may refer to an operation of mapping a physical block address (PBA: hereinafter, referred to as physical address) to each of logical block addresses (LBAs: hereinafter, referred to as logical addresses) which are received from a host apparatus. The physical address PBA may include an index of the super block SB in which the write data are stored and an index of the sector.

An address map table AMT (shown inFIG. 3) may be stored in the nonvolatile memory device100. The address map table AMT may store mapping information between the logical address LBA received from a host apparatus and the physical address PBA corresponding to the logical address LBA.

FIG. 3is a diagram illustrating a configuration example of the address map table AMT according to an embodiment. Referring toFIG. 3, the address map table AMT may include a plurality of map segments MS0to MSn. Each of the map segments MS0to MSn may include a plurality of logical addresses LBA0to LBAm and a plurality of physical addresses PBAO to PBAm corresponding to the plurality of logical addresses LBA0to LBAm. When the mapping information between one logical address LBA and one physical address PBA refers to a logical to physical (L2P) entry, each of the map segments MS0to MSn may include m L2P entries.

When an address buffer AB (shown inFIG. 4) in which P2L entries are stored has no empty space, the address map table AMT may be updated, but the updating timing is not limited thereto. The updating of the mapping information stored in the address map table AMT may refer to map updating operation. The address map table AMT may be updated in map segment units.

The controller200may include a host interface210, a processor220, a memory interface230, a random access memory (RAM)240, and a sequential map search engine250.

The host interface210may perform interfacing between a host apparatus (not shown) and the data storage device10. By way of example and not limitation, the host interface210may communicate with the host apparatus through any one among standard transfer protocols such as a USB protocol, a UFS protocol, an MMC protocol, a parallel advanced technology attachment (PATA) protocol, a serial advanced technology attachment (SATA) protocol, a small computer system interface (SCSI) protocol, a serial attached SCSI (SAS) protocol, a PCI protocol, and a PCI-E protocol.

The processor220may be a micro control unit (MCU) and a central processing unit (CPU). The processor220may process a request received from a host apparatus. To process the request received from the host apparatus, the processor220may drive a code-type instruction or algorithm (for example, software) loaded into the RAM240and control internal function blocks and the nonvolatile memory device100.

The memory interface230may control the nonvolatile memory device100according to control of the processor220. The memory interface230may refer to a memory controller. The memory interface230may provide control signals to the nonvolatile memory device100. The control signals may include a command, an address, and the like for controlling the nonvolatile memory device100. The memory interface230may provide data to the nonvolatile memory device100or receive data from the nonvolatile memory device100. The memory interface230may be coupled to the nonvolatile memory device100through a channel CH including one or more signal lines.

The RAM240may be a random access memory such as a dynamic RAM (DRAM) or a static RAM (SRAM). The RAM240may store software driven through the processor220. The RAM240may store data (for example, meta data) required for the driving of the software. For example, the RAM240may be operated as a working memory of the processor220.

The RAM240may temporarily store data to be transmitted from a host apparatus to the nonvolatile memory device100or data to be transmitted from the nonvolatile memory device100to the host apparatus. For example, the RAM240may be operated as a data buffer memory or a data cache memory.

FIG. 4is a diagram illustrating a configuration example of the RAM240according to an embodiment.

Referring toFIG. 4, the RAM240may include the address buffer AB, a map update buffer MUB, a map cache buffer MCB, a sequential map table SMT, and the like.

The address buffer AB may store the mapping information, for example, a logical address LBA received from a host apparatus and a physical address PBA of the nonvolatile memory100in which write data is stored. The address mapping information stored in the address buffer AB may be the P2L entry. The address map table AMT of the nonvolatile memory device100may be updated based on the P2L entry stored in the address buffer AB.

The address buffer AB, the map update buffer NUB, the map cache buffer MCB, and the sequential map table SMT will be described in more detail below.

FIG. 5Ais a conceptual diagram illustrating the address buffer AB ofFIG. 4.

Referring toFIG. 5A, the address buffer AB may include regions each of which corresponds to the sectors S1to S64included in an arbitrary super block SB. The arbitrary super block SB may correspond to a super block which is currently used for example, a super block on which a write operation is currently performed. When the logical addresses LBAs are received from a host apparatus, each of the logical addresses LBAs may be matched with and stored in one sector S among the sectors S1to S64. The one logical address LBA mapped with the one sector S may refer to the P2L entry. The physical address PBA may include an index of the using super block SB and an index of each of the sectors S1to S64.

The map update buffer MUB may temporarily store L2P entries of at least one or more map segments as an update target among the plurality of map segments MS0to MSn stored in the address map table AMT of the nonvolatile memory device100. The physical addresses PBAs for the L2P entries temporarily stored in the map update buffer MUB may be changed based on the P2L entries stored in the address buffer AB. As the L2P entries in which the physical addresses PBAs are changed may be written in the address map table AMT of the nonvolatile memory device100, the updating of the address map table AMT, for example, a map updating operation may be completed.

The map cache buffer MCB may cache map data corresponding to a logical address which is recently read-requested from a host apparatus or a logical address which is frequently read-requested from the host apparatus. The map data cached in the map cache buffer MCB may be the L2P entries.

The sequential map table SMT may store the sequential map entries for consecutive logical addresses LBAs greater than or equal to a predetermined threshold number, based on the P2L entries stored in the address buffer AB. The sequential map entries may be generated and stored in the sequential map table SMT when the map updating operation is performed.

FIG. 5Bis a conceptual diagram illustrating the sequential map table SMT ofFIG. 4.

Referring toFIG. 5B, the sequential map table SMT may include one or more sequential map entry indexes SME Index, and one or more sequential map entries SME. The sequential map table SMT may have regions in which i sequential map entries1to i are stored. Each of the sequential map entries SME may be configured to include a start logical address Start LBA, a logical address length LBA length, and a start physical address Start PBA.

For example, when the write operation for the arbitrary super block SB is completed, the map updating operation may be performed. The processor220may determine whether or not consecutive logical addresses LBAs (i.e., sequential logical address) that are greater than or equal to the predetermined threshold number are present by scanning the P2L entries stored in the address buffer AB. When the sequential logical addresses are present, the processor220may generate a sequential map entry SME which includes values indicating a start logical address Start LBA of the sequential logical addresses, a logical address length LBA length, and a start physical address Start PBA corresponding to the start logical address of the sequential logical addresses and store the generated sequential map entry SME in the sequential map table SMT.

FIG. 6Ais a diagram illustrating an example when P2L entries are stored in the address buffer AB in a sequential write and a random write according to an embodiment.FIG. 6Bis a diagram illustrating an example of generating and storing a sequential map entry SME of the sequential write ofFIG. 6Ainto the sequential map table SMT. For clarity, it is assumed that a write operation is performed on a 10-th super block SB10. Further, it is assumed that the predetermined threshold number of logical addresses for determining whether to or not correspond to the sequential logical addresses in this particular embodiment is 30. However, it is to be noted that the present disclosure is not limited thereto. That is, the write operation may be performed on any super block, and the predetermined threshold number may be any suitable number depending on design.

Referring toFIG. 6A, as write data for a first write command WCMD1received from a host apparatus are stored in first to 48-th sectors S1to S48of the 10-th super block SB10, write logical addresses LBA1to LBA48corresponding to the first write command WCMD1may be mapped with the corresponding sectors S1to S48and information indicating that mapping relationship may be stored in the address buffer AB. Next, as write data for a second write command WCMD2received from the host apparatus are stored in 49-th to 56-th sectors S49to S56of the 10-th super block SB10, write logical addresses LBA1401to LBA1408corresponding to the second write command WCMD2may be mapped with the corresponding sectors S49to S56and information indicating that mapping relationship may be stored in the address buffer AB. Lastly, as write data for a third write command WCMD3received from the host apparatus are stored in 57-th to 64-th sectors S57to S64of the 10-th super block SB10, write logical addresses LBA1501to LBA1508corresponding to the third write command WCMD3may be mapped with the corresponding sectors S57to S64and information indicating that mapping relationship may be stored in the address buffer AB.

As the use of the 10-th super block is completed, the map updating operation may be performed. As described above, the map updating operation may be performed by storing the map segments MS, which include the write logical addresses LBA1to LBA48, LBA1401to LBA1408, and LBA1501to LBA1508in the address map table AMT stored in the nonvolatile memory device100, in the map update buffer MUB, changing the physical addresses PBAs corresponding to the write logical addresses LBA1to LBA48, LBA14O1to LBA1408, and LBA1501to LBA1508to the super block index (for example, 10) and the sector indexes (for example, 1 to 64), and restoring the map segments MS including the write logical addresses LBA1to LBA48, LBA1401to LBA1408, and LBA1501to LBA1508, in which the physical addresses PBAs are changed, in the nonvolatile memory device100.

While the map updating operation is performed, the processor220may determine whether or not consecutive sequential logical addresses that are greater than or equal to the predetermined threshold number (for example, 30) are present based on the P2L entries stored in the address buffer AB. As illustrated inFIG. 6A, since the sequential logical addresses, for example, the first to 48-th logical addresses LBA1to LBA48, is greater than the predetermined threshold number for this embodiment (for example, 30), the processor220may determine that the first to 48-th logical addresses LBA1to LBA48correspond to the sequential logical addresses, generate the sequential map entry SME for the corresponding logical addresses LBA1to LBA48, and store the sequential map entry SME in the sequential map table SMT.

As illustrated inFIG. 6B, the sequential map table SMT may include values representing ‘LBA1’ as the start logical address Start LBA of the sequential map entry SME for the first to 48-th logical addresses LBA1to LBA48, ‘48’ as the logical address length LBA length, and ‘10’ as the super block index and ‘1’ as the sector index for the start physical address Start PBA.

FIG. 7Ais a diagram illustrating an example of generating and updating a sequential map entry SME when a plurality of map updating operations are performed with respect to a sequential write performed in one super block according to an embodiment. For clarity, it is assumed that a sequential write operation is performed on the whole 10-th super block SB illustrated inFIG. 7A.

A size of the address buffer AB in the RAM240may be smaller than that of the super block SB.FIG. 7Aillustrates an example when the size of the super block SB is four times larger than that of the address buffer AB. When the address buffer AB is completely filled with the P2L entries, the map updating operation may be performed. Accordingly, the map updating operation may be performed four times until the write operation for the 10-th super block SB10can be completed.

For example, when the 10-th super block SB10includes first to4j-th sectors S1to S4jand the address buffer AB includes first to j-th mapping regions, the map updating operation may be performed whenever the write operations for first to j-th sectors S1to Sj, j+1-th to2j-th sectors Sj+1 to S2j,2j+1-th to3j-th sectors S2j+1 to S3j, and3j+1-th to 4-th sectors S3j+1 to S4jof the 10-th super block SB10are completed.

When the write operation for the first to j-th sectors S1to Sj of the 10-th super block SB10is completed, the map updating operation may be performed and the processor220may generate a sequential map entry SME1for the sequential logical addresses LBA1to LBAj. The generated sequential map entry SME1may include values indicating ‘LBA1’ as the start logical address, as the logical address length LBA length, and ‘10’ as the super block index and ‘1’ as the sector index for the start physical address Start PBA.

When the write operation for the j+1-th to2j-th sectors Sj+1 to S2jof the 10-th super block SB10is completed, the map updating operation may be performed and the processor220may determine whether or not a sequential map entry SME having an end logical address LBAj consecutive to the start logical address LBAj+1 of the sequential logical addresses LBAj+1 to LBA2jis present in the sequential map table SMT. Since the sequential map entry SME1having the end logical address LBAj is stored in the sequential map table SMT, the processor220may update the logical address length LBA length to ‘2j’ in the corresponding sequential map entry SME1.

Similarly, whenever the write operations for the2j+1-th to3j-th sectors S2j+1 to S3jand3j+1-th to4j-th sectors S3j+1 to S4jof the 10-th super block SB10are completed, the processor220may sequentially update the logical address lengths LBA length to ‘3j’ and ‘4j’ in the sequential map entry SME1stored in the sequential map table SMT.

FIG. 7Bis a diagram illustrating an example of generating a sequential map entry SME when a sequential write completed with respect to one super block is continuously performed on another super block according to an embodiment.

When the sequential write completed with respect to the 10-th super block SB10as illustrated inFIG. 7Ais continuously performed from the first to the j-th sectors S1to Sj of the 11-th super block SB11, the index of the super block is changed and the processor220may generate a new sequential map entry SME2for the sequential logical addresses LBA4j+1 to LBA5j. The newly generated sequential map entry SME2may include values indicating ‘LBA4j+1’ as the start logical address, ‘j’ as the logical address length LBA length, and the super block index ‘11’ and the sector index ‘1’ as the start physical address Start PBA.

When a read request is received from a host apparatus, the sequential map search engine250may search for a sequential map entry SME including a read-requested logical address among the sequential map entries SME stored in the sequential map table SMT through control of the processor220. When the sequential map entry SME including the read-request logical address is present in the sequential map table SMT, the sequential map search engine250may provide the index value of the sequential map entry index SME Index indicating the corresponding sequential map entry SME to the processor220. When the sequential map entry SME including the read-requested logical address is not present in the sequential map table SMT, the sequential map search engine250may provide a signal indicating that the sequential map entry SME including the read-requested logical address is not present to the processor220.

The processor220may detect the corresponding sequential map entry SME in the sequential map table SMT based on the value of the sequential map entry index SME Index provided from the sequential map search engine250and calculate an offset between the start logical address Start LBA of the corresponding sequential map entry SME and the read-requested logical address. The processor220may control the nonvolatile memory device100to read data stored in a corresponding position of a calculated physical address by adding the calculated offset to the sector index of the physical address (super block index/sector index) of the sequential map entry SME and providing the calculated physical address to the nonvolatile memory device100.

When the signal indicating that the sequential map entry SME including the read-requested logical address is not present is provided from the sequential map search engine250, the processor220may determine whether or not the L2P entry corresponding to the read-requested logical address is present in the map cache buffer MCB of the RAM240. When the L2P entry corresponding to the read-requested logical address is present in the map cache buffer MCB, the processor220may convert the read-requested logical address to the physical address based on the L2P entry and provide the converted physical address to the nonvolatile memory device100.

When the L2P corresponding to the read-requested logical address is not present in the map cache buffer MCB, the processor220may read the map segment MS including the L2P entry corresponding to the read-requested logical address from the address map table AMT of the nonvolatile memory device100, cache the read map segment MS in the map cache buffer MCB, search for the corresponding L2P entry in the map cache buffer MCB, and convert the read-requested logical address to the physical address based on the searched L2P entry.

FIG. 8Ais a diagram illustrating an example of a sequential map table SMT that three sequential map entries are stored according to an embodiment andFIG. 8Bis a diagram illustrating an operation when a random read-requested logical address is included in a sequential map entry SME according to an embodiment.

As illustrated inFIGS. 8A and 8B, when a random read request and a logical address LBA30are received from a host apparatus, the processor220may search for the sequential map entry SME including the read-requested logical address LBA30in the sequential map table SMT using the sequential map search engine250. When the sequential map entry SME1including the logical address LBA30is searched, the processor220may calculate an offset ‘29’ between the start logical address LBA1of the searched sequential map entry SME1and the read-requested logical address LBA30. The processor220may convert the logical address LBA30to the physical address10as the index of the super block SB and30as the index of the sector by adding the offset ‘29’ to the sector index ‘1’ of the index ‘10’ of the super block SB indicated by the start physical address Start PBA of the searched sequential map entry SME1.

FIG. 9is a flowchart illustrating an operation method of the data storage apparatus10according to an embodiment. Specifically,FIG. 9is the flowchart illustrating a method of generating a sequential map entry SME in the operating method of the data storage apparatus10according to an embodiment. The operating method of the data storage apparatus10according to an embodiment will be described with reference toFIG. 9withFIGS. 1 to 8B.

In step S910, the processor220may determine whether or not performing map updating operation is necessary. For example, when the address buffer AB of the RAM240is completely filled with the P2L entries, the processor220may determine that the map updating operation is necessarily performed. When it is determined that the map updating operation is necessary (that is, “Yes” at step S910), the processor may proceed to step S920.

In step S920, the processor220may perform map updating operation by loading map segments MS to be updated from the address map table AMT of the nonvolatile memory device100to the map update buffer MUB of the RAM240based on the P2L entries of the address buffer AB, changing physical addresses included in the loaded map segments MS based on the P2L entries of the address buffer AB, and storing the updated map segments MS in the address map table AMT of the nonvolatile memory device100.

In step S930, the processor220may determine whether or not sequential logical addresses are present based on the P2L entries stored in the address buffer AB. The sequential logical addresses mean consecutive logical addresses that are greater than or equal to the predetermined threshold number. When the sequential logical addresses are not present, the processor may proceed to step S910. When the sequential logical addresses are present, the processor may proceed to step S940.

In step S940, the processor220may determine whether or not a sequential map entry SME has an end logical address consecutive to the start logical address of the sequential logical addresses with reference to the sequential map table SMT of the RAM240. When the sequential map entry SME has the end logical address consecutive to the start logical address of the sequential logical addresses (that is, “Yes” at step S940), the processor may proceed to step S950.

In step S950, the processor220may determine whether or not the super block index for the sequential logical addresses is the same as the super block index of the sequential map entry SME. When the super block index for the sequential logical addresses is the same as the super block index of the sequential map entry SME (that is, “Yes” at step S950), the processor may proceed to step S960.

In step S960, the processor220may update a logical address length LBA length of the sequential map entry SME to a value to which the length of the sequential logical addresses is added.

When the sequential map entry SME does not have the end logical address consecutive to the start logical address of the sequential logical addresses (that is, “No” in step S940) or when the super block index for the sequential logical addresses is not the same as the super block index of the sequential map entry SME (that is, “No” at step S950), the processor may proceed to step S970.

In step S970, the processor220may newly generate the sequential map entry SME for the corresponding sequential logical addresses and store the newly generated sequential map entry SME in the sequential map table SMT. Then, the processor may proceed back to step S910.

FIG. 10is a flowchart illustrating an operation method of the data storage apparatus10according to an embodiment. Specifically,FIG. 10is the flowchart illustrating an address conversion method according to a random read request in the operating method of the data storage apparatus10, according to an embodiment. The operating method of the data storage apparatus10inFIG. 10will be described with referencesFIGS. 1 to 8B.

In step S1010, the processor220may determine whether or not a read request is received from a host apparatus. When the read request is received from the host apparatus, the processor220may proceed to step S1020.

In step S1020, the processor220may determine whether or not a sequential map entry SME including a read-requested logical address is present in the sequential map table SMT using the sequential map search engine250. When the sequential map entry SME including the read-requested logical address is present (that is, “Yes” at step S1020), the processor may proceed to step S1030.

In step S1030, the processor220may calculate an offset between a start logical address of the sequential map entry SME and the read-requested logical address.

In step S1040, the processor220may convert the read-requested logical address to a physical address by adding the calculated offset to the start physical address of the sequential map entry SME. For example, the offset may be added to the sector index included in the start physical address. Next, the processor may proceed to step S1080.

When the sequential map entry SME including the read-requested logical address is not present in step S1020(that is, “No” at step S1020), the processor may proceed to step S1050.

In step S1050, the processor220may determine whether or not a L2P entry corresponding to the read-requested logical address is present in the map cache buffer MCB of the RAM240. When the L2P entry corresponding to the read-requested logical address is present in the map cache buffer MCB (that is, “Yes” at step S1050), the processor may proceed to step S1060.

In step S1060, the processor220may convert the read-requested logical address to the physical address based on the L2P entry cached in the map cache buffer MCB. Next, the processor may proceed to step S1080.

When the L2P entry corresponding to the read-requested logical address is not present in the map cache buffer MCB in step S1050(that is, “No” at step S1050), the processor may proceed to step S1070.

In step S1070, the processor220may read a map segment MS including the L2P entry corresponding to the read-requested logical address from the address map table AMT of the nonvolatile memory device100, cache the read map segment MS in the map cache buffer MCB, and convert the read-requested logical address to the physical address based on the L2P entry cached in the map cache buffer MCB. Next, the processor may proceed to step S1080.

In step S1080, the processor220may provide the converted physical address and the read command to the nonvolatile memory device100and control the nonvolatile memory device100to read data from a position corresponding to the converted physical address.

FIG. 11is a diagram illustrating an example of a data processing system including a solid state drive (SSD) according to an embodiment. Referring toFIG. 11, a data processing system2000may include a host apparatus2100and a SSD2200.

The SSD2200may include a controller2210, a buffer memory device2220, non-volatile memory devices2231to223n, a power supply2240, a signal connector2250, and a power connector2260.

The controller2210may control an overall operation of the SSD2220.

The buffer memory device2220may temporarily store data to be stored in the nonvolatile memory devices2231to223n. The buffer memory device2220may temporarily store data read from the nonvolatile memory devices2231to223n. The data temporarily stored in the buffer memory device2220may be transmitted to the host apparatus2100or the nonvolatile memory devices2231to223naccording to control of the controller2210.

The nonvolatile memory devices2231to223nmay be used as a storage medium of the SSD2200. The nonvolatile memory devices2231to223nmay be coupled to the controller2210through a plurality of channels CH1to CHn. The nonvolatile memory devices coupled to the one channel may be coupled to the same signal bus and the same data bus.

The power supply2240may provide power PWR input through the power connector2260to the inside of the SSD2200. The power supply2240may include an auxiliary power supply2241. The auxiliary power supply2241may supply the power so that the SSD2200is normally terminated even when sudden power-off occurs. The auxiliary power supply2241may include large capacity capacitors capable of charging the power PWR.

The controller2210may exchange a signal SGL with the host apparatus2100through the signal connector2250. The signal SGL may include a command, an address, data, and the like. The signal connector2250may be configured of various types of connectors according to an interfacing method between the host apparatus2100and the SSD2200.

FIG. 12is a diagram illustrating an example of the controller2210ofFIG. 11. Referring toFIG. 12, the controller2210may include a host interface2211, a controller2212, a random access memory (RAM)2213, an error correction code (ECC) unit2214, and a memory interface2215.

The host interface2211may perform interfacing between the host apparatus2100and the SSD2200according to a protocol of the host apparatus2100. For example, the host interface2211may communicate with the host apparatus2100through any one among a secure digital protocol, a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, an embedded MMC (eMMC) protocol, a personal computer memory card international association (PCMCIA) protocol, a parallel advanced technology attachment (PATH) protocol, a serial advanced technology attachment (SATA) protocol, a small computer system interface (SCSI) protocol, a serial attached SCSI (SAS) protocol, a peripheral component interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, and a universal flash storage (UFS) protocol. The host interface2211may perform a disc emulation function that the host apparatus2100recognizes the SSD2200as a general-purpose data storage apparatus, for example, a hard disc drive HDD.

The controller2212may analyze and process the signal SGL input from the host apparatus2100. The controller2212may control operations of internal functional blocks according to firmware and/or software for driving the SDD2200. The RAM2213may be operated as a working memory for driving the firmware or software.

The ECC unit2214may generate parity data for the data to be transferred to the nonvolatile memory devices2231to223n. The generated parity data may be stored in the nonvolatile memory devices2231to223ntogether with the data. The ECC unit2214may detect errors for data read from the nonvolatile memory devices2231to223nbased on the parity data. When detected errors are within a correctable range, the ECC unit2214may correct the detected errors.

The memory interface2215may provide a control signal such as a command and an address to the nonvolatile memory devices2231to223naccording to control of the controller2212. The memory interface2215may exchange data with the nonvolatile memory devices2231to223naccording to control of the controller2212. For example, the memory interface2215may provide data stored in the buffer memory device2220to the nonvolatile memory devices2231to223nor provide data read from the nonvolatile memory devices2231to223nto the buffer memory device2220.

FIG. 13is a diagram illustrating an example of a data processing system including a data storage apparatus according to an embodiment. Referring toFIG. 13, a data processing system3000may include a host apparatus3100and a data storage apparatus3200.

The host apparatus3100may be configured in a board form such as a printed circuit board (PCB). Although not shown inFIG. 13, the host apparatus3100may include internal functional blocks configured to perform functions of the host apparatus3100.

The host apparatus3100may include a connection terminal3110such as a socket, a slot, or a connector. The data storage apparatus3200may be mounted on the connection terminal3110.

The data storage apparatus3200may be configured in a board form such as a PCB. The data storage apparatus3200may refer to a memory module or a memory card. The data storage apparatus3200may include a controller3210, a buffer memory device3220, nonvolatile memory devices3231to3232, a power management integrated circuit (PMIC)3240, and a connection terminal3250.

The controller3210may control an overall operation of the data storage apparatus3200. The controller3210may be configured to have the same configuration as the controller2210illustrated inFIG. 12.

The buffer memory device3220may temporarily store data to be stored in the nonvolatile memory devices3231and3232. The buffer memory device3220may temporarily store data read from the nonvolatile memory devices3231and3232. The data temporarily stored in the buffer memory device3220may be transmitted to the host apparatus3100or the nonvolatile memory devices3231and3232according to control of the controller3210.

The nonvolatile memory devices3231and3232may be used as a storage medium of the data storage apparatus3200.

The PMIC3240may provide power input through the connection terminal3250to the inside of the data storage apparatus3200. The PMIC3240may manage the power of the data storage apparatus3200according to control of the controller3210.

The connection terminal3250may be coupled to the connection terminal3110of the host apparatus3100. A signal such as a command, an address, and data and power may be transmitted between the host apparatus3100and the data storage apparatus3200through the connection terminal3250. The connection terminal3250may be configured in various forms according to an interfacing method between the host apparatus3100and the data storage apparatus3200. The connection terminal3250may be arranged in any one side of the data storage apparatus3200.

FIG. 14is a diagram illustrating an example of a data processing system including a data storage apparatus according to an embodiment. Referring toFIG. 14, a data processing system4000may include a host apparatus4100and a data storage apparatus4200.

The host apparatus4100may be configured in a board form such as a PCB. Although not shown inFIG. 14, the host apparatus4100may include internal functional blocks configured to perform functions of the host apparatus4100.

The data storage apparatus4200may be configured in a surface mounting packaging form. The data storage apparatus4200may be mounted on the host apparatus4100through a solder ball4250. The data storage apparatus4200may include a controller4210, a buffer memory device4220, and a nonvolatile memory device4230.

The controller4210may control an overall operation of the data storage apparatus4200. The controller4210may be configured to have the same configuration as the controller2210illustrated inFIG. 12.

The buffer memory device4220may temporarily store data to be stored in the nonvolatile memory device4230. The buffer memory device4220may temporarily store data read from the nonvolatile memory device4230. The data temporarily stored in the buffer memory device4220may be transmitted to the host apparatus4100or the nonvolatile memory device4230through control of the controller4210.

The nonvolatile memory device4230may be used as a storage medium of the data storage apparatus4200.

FIG. 15is a diagram illustrating an example of a network system5000including a data storage apparatus according to an embodiment. Referring toFIG. 15, the network system5000may include a server system5300and a plurality of client systems5410to5430which are coupled through a network5500.

The server system5300may serve data in response to requests of the plurality of client systems5410to5430. For example, the server system5300may store data provided from the plurality of client systems5410to5430. In another example, the server system5300may provide data to the plurality of client systems5410to5430.

The server system5300may include a host apparatus5100and a data storage apparatus5200. The data storage apparatus5200may be configured of the data storage apparatus10ofFIG. 1, the data storage apparatus2200ofFIG. 11, the data storage apparatus3200ofFIG. 13, or the data storage apparatus4200ofFIG. 14.

FIG. 16is a block diagram illustrating an example of a nonvolatile memory device included in a data storage apparatus according to an embodiment. Referring toFIG. 16, a nonvolatile memory device100may include a memory cell array110, a row decoder120, a column decoder140, a data read/write block130, a voltage generator150, and a control logic160.

The memory cell array110may include memory cells MC arranged in regions in which word lines WL1to WLm and bit lines BL1to BLn cross to each other.

The row decoder120may be coupled to the memory cell array110through the word lines WL1to WLm. The row decoder120may operate through control of the control logic160. The row decoder120may decode an address provided from an external apparatus (not shown). The row decoder120may select and drive the word lines WL1to WLm based on a decoding result. For example, the row decoder120may provide a word line voltage provided from the voltage generator150to the word lines WL1to WLm.

The data read/write block130may be coupled to the memory cell array110through the bit lines BL1to BLn. The data read/write block130may include read/write circuits RW1to RWn corresponding to the bit lines BL1to BLn. The data read/write block130may operate according to control of the control logic160. The data read/write block130may operate as a write driver or a sense amplifier according to an operation mode. For example, the data read/write block130may operate as the write driver configured to store data provided from an external apparatus in the memory cell array110in a write operation. In another example, the data read/write block130may operate as the sense amplifier configured to read data from the memory cell array110in a read operation.

The column decoder140may operate though control of the control logic160. The column decoder140may decode an address provided from an external apparatus (not shown). The column decoder140may couple the read/write circuits RW1to RWn of the data read/write block130corresponding to the bit lines BL1to BLn and data input/output (I/O) lines (or data I/O buffers) based on a decoding result.

The voltage generator150may generate voltages used for an internal operation of the nonvolatile memory device100. The voltages generated through the voltage generator150may be applied to the memory cells of the memory cell array110. For example, a program voltage generated in a program operation may be applied to word lines of memory cells in which the program operation is to be performed. In another example, an erase voltage generated in an erase operation may be applied to well regions of memory cells in which the erase operation is to be performed. In another example, a read voltage generated in a read operation may be applied to word lines of memory cells in which the read operation is to be performed.

The control logic160may control an overall operation of the nonvolatile memory device100based on a control signal provided from an external apparatus. For example, the control logic160may control an operation of the nonvolatile memory device100such as a read operation, a write operation, an erase operation of the nonvolatile memory device100.

The above embodiments of the present disclosure are illustrative and not limitative. Various alternatives and equivalents are possible. The examples of the embodiments are not limited by the embodiments described herein. Nor is the present disclosure limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.