Resistive memory device and method for manufacturing with protrusion of electrode

A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

BACKGROUND

A resistive memory device is a type of non-volatile memory device, and each memory cell thereof can be switched between a low resistance state and a high resistance state to store data. A conventional resistive memory device can be manufactured using a complementary metal oxide semiconductor (CMOS) logic process, but is fabricated in the front-end-of-line (FEOL).

DETAILED DESCRIPTION

FIG.1is a schematic top view of a memory cell100of a resistive memory device in accordance with some embodiments.FIG.2is a schematic sectional view of the memory cell100taken along line A-A′ ofFIG.1in accordance with some embodiments. The memory cell100includes a bottom electrode11, a top electrode12and a resistance changing element13. The top electrode12is disposed above and spaced apart from the bottom electrode11, and has a downward protrusion121that is aligned with the bottom electrode11. The resistance changing element13covers side and bottom surfaces of the downward protrusion121. The resistance changing element13provides a storage node between the top electrode12and the bottom electrode11, so the memory cell100can store one bit of data.

In some embodiments, the downward protrusion121may taper from top to bottom. In some embodiments, a top cross section of the downward protrusion121may be a rectangle that has a predetermined aspect ratio falling within a range of from about 1:10 to about 10:1. If the predetermined aspect ratio is outside this range, the top cross section of the downward protrusion121would have a very large area, which is adverse to miniaturization of the memory cell100. In some embodiments, each side length of a bottom cross section of the downward protrusion121may be smaller than a corresponding side length of the top cross section of the downward protrusion121by a predetermined scaling factor that falls within a range of from about 5% to about 50% (i.e., each side length of the bottom cross section of the downward protrusion121may be about 95% to 50% of the corresponding side length of the top cross section of the downward protrusion121). If the predetermined scaling factor is smaller than 5%, it would be very difficult to manufacture the memory cell100. If the predetermined scaling factor is greater than 50%, the bottom cross section of the downward protrusion121would have a very small area, and the memory cell100would be unable to operate properly.

In some embodiments, a distance between the downward protrusion121and the bottom electrode11may fall within a range of from about 1 nm to about 15 nm. If the distance is smaller than 1 nm, the resistance changing element13would be very thin, and the memory cell100would have a poor resistance changing effect. If the distance is greater than 15 nm, the resistance changing element13would be very thick, and it would be necessary to write data to and read data from the memory cell100at high voltages.

In some embodiments, the resistance changing element13may be made of a material containing metal atoms and oxygen atoms (for example but not limited to metal oxide, metal oxycarbide, metal oxynitride, metal oxycarbonitride, or combinations thereof). In some embodiments, an atomic percent of the oxygen atoms in the resistance changing element13may fall within a range of from about 10% to about 90%. If the atomic percent of the oxygen atoms is smaller than 10%, the resistance changing element13would not have a high resistance state, and the memory cell100would not have a resistance changing effect. It would be difficult to make the atomic percent of the oxygen atoms greater than 90% if the resistance changing element13is generated by chemical reaction.

FIG.3is a flow chart illustrating a method600for manufacturing a memory cell of a resistive memory device in accordance with some embodiments.FIGS.4to13are schematic sectional views of semiconductor structures700during various stages of the method600. The method600and the semiconductor devices700are collectively described below. However, additional steps can be provided before, after or during the method600, and some of the steps described herein may be replaced by other steps or be eliminated. Similarly, further additional features may be present in the semiconductor devices700, and/or features present may be replaced or eliminated in additional embodiments.

Referring toFIGS.3and4, the method600begins at block601, where a first dielectric layer701is formed on a substrate900. In some embodiments, the first dielectric layer701may be formed on the substrate900using, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, other suitable deposition techniques, or combinations thereof. In some embodiments, the substrate900may be a silicon substrate that is formed with a plurality of transistors used to write data to and read data from a resistive memory device. In some embodiments, the first dielectric layer701may be made of silicon oxide, silicon carbide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), other suitable dielectric materials, or combinations thereof. In alternative embodiments, the first dielectric layer701may be made of polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzooxazole (PBO), other suitable polymer-based dielectric materials, or combinations thereof. Other suitable materials for the first dielectric layer701are within the contemplated scope of the present disclosure.

Referring toFIGS.3,4,5,6and7, the method600then proceeds to block602, where a bottom electrode703′ is formed in the first dielectric layer701. Block602may be implemented as described below. Firstly, as shown inFIGS.4and5, a photolithography process, which includes, for example, but not limited to, coating the first dielectric layer701with a photoresist702, soft-baking, exposing the photoresist702through a photomask (not shown), post-exposure baking, developing the photoresist702, and hard-baking, may be used to form a patterned photoresist702′. Secondly, as shown inFIG.5, the first dielectric layer701may be etched through the patterned photoresist702′ using, for example, dry etching, wet etching, other suitable etching techniques, or combinations thereof, so as to form a recess721. The patterned photoresist702′ may be removed after the etching process. Thirdly, as shown inFIG.6, a conductive material703may be deposited on the first dielectric layer701using, for example, physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroless plating, electroplating, other suitable deposition techniques, or combinations thereof, so as to fill the recess721. Fourthly, as shown inFIGS.6and7, an excess portion of the conductive material703on the first dielectric layer701may be removed using, for example, chemical mechanical polishing (CMP), or other suitable planarization techniques. The remaining portion of the conductive material703is referred to as the bottom electrode703′ that would serve as the bottom electrode11of the memory cell100shown inFIG.1. In some embodiments, the bottom electrode703′ may be made of copper, aluminum, tungsten, tantalum, titanium, compounds thereof, other suitable conductive materials, or combinations thereof. Other suitable materials for the bottom electrode703′ are within the contemplated scope of the present disclosure.

Referring toFIGS.3and8, the method600then proceeds to block603, where a first etch stop layer704, a second dielectric layer705, a second etch stop layer706and a third dielectric layer707are sequentially formed on the first dielectric layer701and the bottom electrode703′. In some embodiments, the first etch stop layer704, the second dielectric layer705, the second etch stop layer706and the third dielectric layer707may be sequentially formed on the first dielectric layer701and the bottom electrode703′ using, for example, physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroless plating, electroplating, other suitable deposition techniques, or combinations thereof. In some embodiments, each of the first etch stop layer704and the second etch stop layer706may be made of metal nitride, metal oxide, metal carbide, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or combinations thereof. Other suitable materials for the first etch stop layer704and the second etch stop layer706are within the contemplated scope of the present disclosure. The first etch stop layer704and the second etch stop layer706may be made of the same or different materials. In some embodiments, the second dielectric layer705may be made of a dielectric material containing oxygen atoms (for example but not limited to silicon oxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, undoped silicate glass, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, fluorine-doped silicate glass, or combinations thereof). Other suitable materials for the second dielectric layer705are within the contemplated scope of the present disclosure. In some embodiments, the third dielectric layer707may be made of silicon oxide, silicon carbide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, undoped silicate glass, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, fluorine-doped silicate glass, other suitable dielectric materials, or combinations thereof. In alternative embodiments, the third dielectric layer707may be made of polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene, polybenzooxazole, other suitable polymer-based dielectric materials, or combinations thereof. Other suitable materials for the third dielectric layer707are within the contemplated scope of the present disclosure. The first dielectric layer701, the second dielectric layer705and the third dielectric layer707may be made of the same or different materials.

Referring toFIGS.3,8and9, the method600then proceeds to block604, where the third dielectric707, the second etch stop layer706and the second dielectric layer705are recessed to form a first trench722in the second dielectric layer705. The first trench722is aligned with the bottom electrode703′, has a top boundary coplanar with a top surface of the second dielectric layer705, and does not expose the first etch stop layer704. That is, the first trench722has a depth smaller than a thickness of the second dielectric layer705. Block604may be implemented as described below. Firstly, as shown inFIGS.8and9, a photolithography process, which includes, for example, but not limited to, coating the third dielectric layer707with a photoresist708, soft-baking, exposing the photoresist708through a photomask (not shown), post-exposure baking, developing the photoresist708, and hard-baking, may be used to form a patterned photoresist708′. Secondly, as shown inFIG.9, the third dielectric layer707, the second etch stop layer706and the second dielectric layer705may be etched through the patterned photoresist708′ using, for example, dry etching, wet etching, other suitable etching techniques, or a combination thereof, so as to form the first trench722in the second dielectric layer705. The patterned photoresist708′ may be removed after block604. In some embodiments, the first trench722may taper from top to bottom. In some embodiments, a top cross section of the first trench722may be a rectangle that has a predetermined aspect ratio falling within a range of from about 1:10 to about 10:1. In some embodiments, each side length of a bottom cross section of the first trench722may be about 50% to 95% of a corresponding side length of the top cross section of the first trench722.

Referring toFIGS.3,10and11, the method600then proceeds to block605, where the third dielectric layer707and the second etch stop layer706are recessed to form a second trench723therein. The second trench723exposes the second dielectric layer705, has a bottom boundary coplanar with the top surface of the second dielectric layer705, and is in spatial communication with the first trench722. Block605may be implemented as described below. Firstly, as shown inFIGS.10and11, a photolithography process, which includes, for example, but not limited to, coating the second dielectric layer705, the second etch stop layer706and the third dielectric layer707with a photoresist709, soft-baking, exposing the photoresist709through a photomask (not shown), post-exposure baking, developing the photoresist709, and hard-baking, may be used to form a patterned photoresist709′. Secondly, the third dielectric layer707and the second etch stop layer706are etched through the patterned photoresist709′ using, for example, dry etching, wet etching, other suitable etching techniques, or a combination thereof, so as to form the second trench723in the third dielectric layer707and the second etch stop layer706. A portion of the photoresist709may remain in the first trench722after the etching process. The patterned photoresist709′ and the portion of the photoresist709remaining in the first trench722may be removed after block605.

Referring toFIGS.3and12, the method600then proceeds to block606, where a barrier layer is conformally formed on a top surface of the third dielectric layer707, inner surfaces of the second trench723and inner surfaces of the first trench722. In some embodiments, as shown inFIG.12, the barrier layer would chemically react with the second dielectric layer705and the third dielectric layer707to form a resistance changing layer710. In alternative embodiments, the barrier layer would chemically react with only the second dielectric layer705to form the resistance changing layer710. In some embodiments, the barrier layer may be conformally formed on the top surface of the third dielectric layer707, the inner surfaces of the second trench723and the inner surfaces of the first trench722using, for example, physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroless plating, electroplating, other suitable deposition techniques, or combinations thereof. In some embodiments, the barrier layer may be made of a conductive material containing metal atoms. The conductive material may be, for example but not limited to, tungsten, tantalum, titanium, nickel, cobalt, hafnium, ruthenium, zirconium, zinc, iron, tin, aluminum, copper, silver, molybdenum, chromium, compounds thereof (for example but not limited to nitride thereof), or combinations thereof. Other suitable materials for the barrier layer are within the contemplated scope of the present disclosure. In some embodiments, the resistance changing layer710may include a material containing metal atoms and oxygen atoms (for example but not limited to metal oxide, metal oxycarbide, metal oxynitride, metal oxycarbonitride, or combinations thereof). In some embodiments, an atomic percent of the oxygen atoms in the resistance changing layer710may fall within a range of from about 10% to about 90%. In some embodiments, a sum of a thickness of the resistance changing layer710and a thickness of the first etch stop layer704may fall within a range of from about 1 nm to about 15 nm.

Referring toFIGS.3,12and13, the method600then proceeds to block607, where a top electrode711′ is formed on the resistance changing layer710and fills the first trench722and the second trench723. Block607may be implemented by (i) depositing a conductive material711on the resistance changing layer710, and (ii) removing excess portions of the conductive material711and the resistance changing layer710to expose the third dielectric layer707. The remaining portion of the conductive material711is referred to as the top electrode711′ that would serve as the top electrode12of the memory cell100shown inFIG.1. The deposition of the conductive material711for forming the top electrode711′ may be implemented using, for example, physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroless plating, electroplating, other suitable deposition techniques, or combinations thereof. The removal of the excess portions of the conductive material711and the resistance changing layer710may be implemented using, for example, chemical mechanical planarization, or other suitable planarization techniques. The top electrode711′ includes a first portion712that fills the first trench722, and a second portion713that fills the second trench723and that covers the first portion712. The first portion712would serve as the downward protrusion121of the top electrode12of the memory cell100shown inFIG.1. A portion of the resistance changing layer710that covers side and bottom surfaces of the first portion712would serve as the resistive changing element13of the memory cell100shown inFIG.1. In some embodiments, the top electrode711′ may be made of copper, aluminum, tungsten, tantalum, titanium, compounds thereof, other suitable conductive materials, or combinations thereof. Other suitable materials for the top electrode711′ are within the contemplated scope of the present disclosure. The bottom electrode703′ and the top electrode711′ may be made of the same or different materials.

In some embodiments, the method600may be fully compatible with a complementary metal oxide semiconductor (CMOS) logic process for fabricating planar field effect transistors (planar FETs) or fin field effect transistors (FinFETs), without extra process steps. The CMOS logic process is, for example, but not limited to, a 16 nanometer (N16) generation CMOS logic process, a 7 nanometer (N7) generation CMOS logic process, a 5 nanometer (N5) generation CMOS logic process, or other generation CMOS logic processes. In some embodiments, the bottom electrode703′ may be formed using an nthmetal layer of the CMOS logic process, the first portion712of the top electrode711′ may be formed using an nthvia layer of the CMOS logic process, and the second portion713of the top electrode711′ may be formed using an (n+1)thmetal layer of the CMOS logic process, where n is a positive integer, so the semiconductor device700is fabricated in the back-end-of-line (BEOL), and multiple semiconductor devices700can be stacked to form a three-dimensional resistive memory device for use in high density applications. In some embodiments, an area of a top cross section of the first trench722for accommodating the first portion712of the top electrode711′ may be smaller than an area of a top cross section of a trench for accommodating a contact via of the CMOS logic process, so that the first trench722for accommodating the first portion712of the top electrode711′ and the trench for accommodating the contact via of the CMOS logic process can be simultaneously formed, and the first trench722for accommodating the first portion712of the top electrode711′ has a depth smaller than a depth of the trench for accommodating the contact via of the CMOS logic process, and does not expose the first etch stop layer704.

FIG.14is a schematic top view of a memory cell100′ of a resistive memory device in accordance with some embodiments. The memory cell100′ is formed by connecting multiple memory cells100shown inFIG.1in parallel, and includes a bottom electrode11, a top electrode12and multiple resistance changing elements13. The top electrode12is disposed above and spaced apart from the bottom electrode11, and has multiple downward protrusions121that are aligned with the bottom electrode11. Each of the resistance changing elements13covers side and bottom surfaces of a respective one of the downward protrusions121. Each of the resistance changing elements13provides a storage node between the top electrode12and the bottom electrode11, and the storage nodes respectively provided by the resistance changing elements13are connected in parallel, so the memory cell100′ can store one bit of data, and fabrication of the memory cell100′ can have a relatively high yield.

FIG.15is a schematic top view of a memory cell100″ of a resistive memory device in accordance with some embodiments.FIG.16is a schematic sectional view of the memory cell100″ taken along line B-B′ ofFIG.15in accordance with some embodiments. The memory cell100″ includes two bottom electrodes11, a top electrode12and a resistance changing element13. The bottom electrodes11are coplanar, and are spaced apart from each other. The top electrode12is disposed above and spaced apart from the bottom electrodes11, and has a downward protrusion121that is aligned with a region between the bottom electrodes11. The resistance changing element13covers side and bottom surfaces of the downward protrusion121. The resistance changing element13provides two storage nodes, each of which is between the top electrode12and a respective one of the bottom electrodes11, so the memory cell100″ can store two bits of data.

In some embodiments, the downward protrusion121may taper from top to bottom. In some embodiments, a top cross section of the downward protrusion121may be a rectangle that has a predetermined aspect ratio falling within a range of from about 1:10 to about 10:1. If the predetermined aspect ratio is outside this range, the top cross section of the downward protrusion121would have a very large area, which is adverse to miniaturization of the memory cell100″. In some embodiments, each side length of a bottom cross section of the downward protrusion121may be smaller than a corresponding side length of the top cross section of the downward protrusion121by a predetermined scaling factor that falls within a range of from about 5% to about 50% each side length of the bottom cross section of the downward protrusion121may be about 95% to 50% of the corresponding side length of the top cross section of the downward protrusion121). If the predetermined scaling factor is smaller than 5%, it would be very difficult to manufacture the memory cell100″. If the predetermined scaling factor is greater than 50%, the bottom cross section of the downward protrusion121would have a very small area, and the memory cell100″ would be unable to operate properly.

In some embodiments, a projection of a top cross section of the downward protrusion121on a plane on which the bottom electrodes11are located may be non-overlapping with the bottom electrodes11. In some embodiments, a distance between the projection and each of the bottom electrodes11may fall within a range sufficient to make the memory cell100″ have a good resistance changing effect and to make it possible to write data to and read data from the memory cell100″ at low or medium voltages. In some embodiments, the distance may be greater than about 10 nm, and may, for example but not limited to, fall within a range of from about 12 nm to about 16 nm.

In some embodiments, the resistance changing element13may be made of a material containing metal atoms and oxygen atoms (for example but not limited to metal oxide, metal oxycarbide, metal oxynitride, metal oxycarbonitride, or combinations thereof). In some embodiments, an atomic percent of the oxygen atoms in the resistance changing element13may fall within a range of from about 10% to about 90%. If the atomic percent is smaller than 10%, the resistance changing element13would not have a high resistance state, and the memory cell100″ would not have a resistance changing effect. It would be difficult to make the atomic percent greater than 90% if the resistance changing element13is generated by chemical reaction.

Referring toFIGS.3and17to20, the memory cell100″ shown inFIG.15may be manufactured by a method which is similar to the method600, and which differs from the method600in that: (a) in block602, two bottom electrodes703′ are formed in the first dielectric layer701as shown inFIG.17, and would respectively serve as the bottom electrodes11of the memory cell100″; (b) in block604, the first trench722is aligned with a region between the bottom electrodes703′, is formed in the second dielectric layer705and the first etch stop layer704, and exposes the first dielectric layer701as shown inFIG.18; and (c) in block606, the barrier layer723would further chemically react with the first dielectric layer701to form the resistance changing layer710as shown inFIG.19. The semiconductor structure700after block607is depicted inFIG.20.

In some embodiments, other than the second dielectric layer705, the first dielectric layer701may also be made of a dielectric material containing oxygen atoms (for example, but not limited to, silicon oxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, undoped silicate glass, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, fluorine-doped silicate glass, or combinations thereof). In some embodiments, a projection of a top cross section of the first trench722on the first dielectric layer701may be non-overlapping with the bottom electrodes703′.

In some embodiments, the area of the top cross section of the first trench722for accommodating the first portion712of the top electrode711′ may be equal to the area of the top cross section of the trench for accommodating the contact via of the CMOS logic process, so that the first trench722for accommodating the first portion712of the top electrode711′ and the trench for accommodating the contact via of the CMOS logic process can be simultaneously formed, and the first trench722for accommodating the first portion712of the top electrode711′ has a depth substantially equal to a depth of the trench for accommodating the contact via of the CMOS logic process, and exposes the first dielectric layer701.

FIG.21is a schematic top view of a memory cell100″′ of a resistive memory device in accordance with some embodiments. The memory cell100″′ is formed by connecting multiple memory cells100shown inFIG.1in parallel, and includes two bottom electrodes11, a top electrode12and multiple resistance changing elements13. The top electrode12is disposed above and spaced apart from the bottom electrodes11, and has multiple downward protrusions121that are aligned with a region between the bottom electrodes11. Each of the resistance changing elements13covers side and bottom surfaces of a respective one of the downward protrusions121. Each of the resistance changing elements13provides two storage nodes, each of which is between the top electrode12and the respective one of the bottom electrodes11, the storage nodes respectively provided by the resistance changing elements13between the top electrode12and one of the bottom electrodes11are connected in parallel, and the storage nodes respectively provided by the resistance changing elements13between the top electrode12and the other one of the bottom electrodes11are connected in parallel, so the memory cell100″′ can store two bits of data, and fabrication of the memory cell100″′ can have a relatively high yield.

In accordance with some embodiments of the present disclosure, a resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

In accordance with some embodiments of the present disclosure, the downward protrusion tapers from top to bottom.

In accordance with some embodiments of the present disclosure, a top cross section of the downward protrusion is a rectangle.

In accordance with some embodiments of the present disclosure, the top electrode has a plurality of the downward protrusions, the resistive memory device includes a plurality of the resistance changing elements, and each of the resistance changing elements covers the side and bottom surfaces of a respective one of the downward protrusions.

In accordance with some embodiments of the present disclosure, the resistance changing element provides a storage node between the top electrode and the bottom electrode.

In accordance with some embodiments of the present disclosure, a resistive memory device includes two bottom electrodes, a top electrode and a resistance changing element. The bottom electrodes are coplanar with and spaced apart from each other. The top electrode is disposed above and spaced apart from the bottom electrodes, and has a downward protrusion aligned with a region between the bottom electrodes. The resistance changing element covers side and bottom surfaces of the downward protrusion.

In accordance with some embodiments of the present disclosure, a projection of a top cross section of the downward protrusion on a plane on which the bottom electrodes are located does not overlap the bottom electrodes.

In accordance with some embodiments of the present disclosure, the downward protrusion tapers from top to bottom.

In accordance with some embodiments of the present disclosure, a top cross section of the downward protrusion is a rectangle.

In accordance with some embodiments of the present disclosure, the top electrode has a plurality of the downward protrusions, the resistive memory device includes a plurality of the resistance changing elements, and each of the resistance changing elements covers the side and bottom surfaces of a respective one of the downward protrusions.

In accordance with some embodiments of the present disclosure, the resistance changing element provides two storage nodes, each of which is between the top electrode and a respective one of the bottom electrodes.

In accordance with some embodiments of the present disclosure, a method for manufacturing a resistive memory device includes: forming at least one bottom electrode in a first dielectric layer; forming a second dielectric layer and a third dielectric layer on the first dielectric layer and the at least one bottom electrode; recessing the third dielectric layer and the second dielectric layer to form a first trench in the second dielectric layer; recessing the third dielectric layer to form a second trench in the third dielectric layer, the second trench being in spatial communication with the first trench; forming a barrier layer on inner surfaces of the second trench and inner surfaces of the first trench, the barrier layer chemically reacting with at least the second dielectric layer to form a resistance changing layer; and forming a top electrode on the resistance changing layer, the top electrode filling the first trench and the second trench.

In accordance with some embodiments of the present disclosure, a bottom electrode is formed in the first dielectric layer, and the first trench is aligned with the bottom electrode, has a top boundary coplanar with a top surface of the second dielectric layer, and has a depth smaller than a thickness of the second dielectric layer.

In accordance with some embodiments of the present disclosure, the second dielectric layer is made of a dielectric material containing oxygen atoms, and the barrier layer is made of a conductive material containing metal atoms.

In accordance with some embodiments of the present disclosure, two bottom electrodes are formed in the first dielectric layer, the first trench is aligned with a region between the bottom electrodes, and exposes the first dielectric layer, and the barrier layer further chemically reacts with the first dielectric layer to form the resistance changing layer.

In accordance with some embodiments of the present disclosure, each of the first dielectric layer and the second dielectric layer is made of a dielectric material containing oxygen atoms, and the barrier layer is made of a conductive material containing metal atoms.

In accordance with some embodiments of the present disclosure, a projection of a top cross section of the first trench on the first dielectric layer does not overlap the bottom electrodes.

In accordance with some embodiments of the present disclosure, the first trench tapers from top to bottom.

In accordance with some embodiments of the present disclosure, a top cross section of the first trench is a rectangle.

In accordance with some embodiments of the present disclosure, the resistance changing layer includes a material containing metal atoms and oxygen atoms, and an atomic percent of the oxygen atoms in the resistance changing layer falls within a range of from 10% to 90%.