FinFETs with strained channels and reduced on state resistance

The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

FIELD OF THE INVENTION

The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistance and methods of manufacture.

BACKGROUND

With semiconductor scaling, parasitic external resistance can pose significant challenges to achieving device performance. To increase performance, a channel strain can be placed on the device; however, it has been found that significant strain, e.g., approximately 50% of cSiGe strain, can be lost through cavity etching processes needed for source and drain formation. Some of the strain loss can be recovered, but such recovery is not a simple process.

For example, strain loss can be partially recovered by using embedded source and drain epitaxial processes. Alternatively, strain loss can be prevented using cladding techniques. However, cladding might not provide enough dopant source for lowering Ron. More specifically, with cladding processes, there is not enough SiGe:B volume to provide a junction overlap.

SUMMARY

In an aspect of the disclosure a structure comprises: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

In an aspect of the disclosure a structure comprises: a first plurality of fin structures comprising: a fin region composed of a first material in a dielectric material; doped source and drain regions above the dielectric material; and a diffusion blocking layer between the fin region and the doped source and drain regions; and a second plurality of fin structures devoid of the blocking layer.

In an aspect of the disclosure a method comprises: forming a plurality of fins; forming a diffusion blocking layer on exposed surfaces of the plurality of fins; growing an epitaxial layer on the diffusion blocking layer; doping the epitaxial layer with a dopant; and forming source and drain regions from the doped epitaxial layer.

DETAILED DESCRIPTION

The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistance and methods of manufacture. In embodiments, the finFET structures include a blocking layer, e.g., SiC layer, which prevents diffusion of source and drain dopants into the lower portions of the finFET structures. Advantageously, by providing such blocking layer, the structures and methods described herein preserve strain post source and drain (S/D) formation, while also allowing for increased doping for Rext reduction.

More specifically, the finFET structures described herein include an SiC diffusion blocking layer formed as a part of the fin structure. The SiC diffusion blocking layer will prevent dopants used for the source and drain regions from diffusing into the fin structures, mitigating strain loss that would otherwise occur due to S/D recess reactive ion etching (RIE) processes. In addition, the diffusion blocking layer and methods described herein reduce on state resistance due to an increased boron source for the junction; whereas, typical cladded S/D epitaxial processes cannot provide sufficient boron (or other dopants). The processes described herein are also simple to implement with minimal disruption to process flow, while providing multiple alternatives to simplify integration options.

FIG. 1shows a structure and respective fabrication processes in accordance with aspects of the present disclosure. More specifically,FIG. 1illustrates a finFET structure100comprising a PFET region105and an NFET region110, separated by a shallow trench isolation structure (STI)115, e.g., oxide material, formed in a substrate120. In embodiments, the substrate120can be any appropriate semiconductor material, e.g., bulk Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors.

The STI115can be formed prior to or after the formation of fin structures122. For example, the STI115can be formed by conventional lithography, etching and deposition processes known to those of skill in the art. In these processes, a resist formed over the substrate120is exposed to energy (light) to form a pattern (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to form one or more trenches in the substrate120through the openings of the resist. The resist can then be removed by a conventional oxygen ashing process or other known stripants. Following the resist removal, the oxide material can be deposited by any conventional deposition processes, e.g., chemical vapor deposition (CVD) processes. Any residual material on the surface of the substrate120can be removed by conventional chemical mechanical polishing (CMP) processes. In embodiments, the STI115can also be formed post fin structure formation.

Still referring toFIG. 1, the fin structures122are formed from the substrate material by using conventional patterning processes. For example, in embodiments, the fin structures122can be formed by conventional sidewall image techniques (SIT). In an example of a SIT technique, a mandrel material, e.g., SiO2, is deposited on the substrate using conventional CVD processes. A resist is formed on the mandrel material, and exposed to light to form a pattern (openings). A reactive ion etching is performed through the openings to remove portions of the mandrel material in order to form the mandrels. In embodiments, the mandrels can have different widths and/or spacing depending on the desired dimensions. Spacers are formed on the sidewalls of the mandrels which are preferably material that is different than the mandrels, and which are formed using conventional deposition processes known to those of skill in the art. The spacers can have a width which matches the dimensions of the narrow fin structures122, for example. The mandrels are removed or stripped using a conventional etching process, selective to the mandrel material. An etching is then performed within the spacing of the spacers to form the sub-lithographic features. The sidewall spacers can then be stripped.

An oxide material124e.g., a dielectric material, is deposited on the fin structures over the PFET region105and NFET region110, respectively. Following the deposition process, the oxide material124can be partially recessed using conventional selective etchant processes, e.g., RIE process, to reveal upper portions of the fin structures122on both the PFET region105and NFET region110. Alternatively, the oxide material124and STI115can both be formed post fin structure formation.

In any scenario, though, portions of the fin structures122on the PFET region105can be removed, followed by formation of, e.g., exposed fin structures135on the PFET region105. The remaining portions of the fin structures122on the PFET region105will form an underlying fin region within the dielectric material124. During this fin removal process, the fin structures122on the NFET region110will remain protected by, e.g., a hardmask, while a selective etching process will remove upper portions of the fin structures on the PFET region105, above the dielectric material124. It should be understood by those of skill in the art that the exposed fin structures135can be formed on the NFET region110; instead of the PFET region105. In addition, the exposed fin structures135can be formed in different directions and, as such, the present disclosure should not be limited to only the presently described structure.

Referring still toFIG. 1, in embodiments, the exposed fin structures135can be formed as part of a post fin reveal and dummy gate formation or by a replacement growth process, e.g., growing of diffusion blocking material130followed by an upper material region125. For example, in embodiments, the exposed fin structures135include forming a diffusion blocking material130on the surfaces of the recessed fin structures122on the PFET region105, followed by epitaxial growth of upper region material125, e.g., SiGe or other semiconductor material. It should be recognized that the fin structures122within the dielectric material124, below the diffusion blocking material130, is generally an underlying fin region. In embodiments, the diffusion blocking material130is composed of, e.g., silicon carbide (SiC), which, as should be understood by those of skill in the art, will prevent diffusion of dopants into the lower portion of the fin structures135(e.g., portions of the fin structures below the blocking material130), which is performed in subsequent source/drain formation processes.

In embodiments, the diffusion blocking material130can be grown by an epitaxial growth process to a thickness of about 1 nm to about 5 nm; although other dimensions are also contemplated herein. The upper region material125of the exposed fin structures135, e.g., SiGe, can be grown on the diffusion blocking material130on the PFET region105of the structure. The upper region material125can be grown to a height of about 35 nm to about 50 nm to form the exposed fin structures135; although other dimensions are also contemplated herein.

FIG. 2Ashows the structure ofFIG. 1with a doping layer applied on the exposed fin structures135, amongst other features, and respective fabrication processes in accordance with aspects of the present disclosure. More specifically, inFIG. 2A, a hardmask140is deposited on the fin structures122on the NFET region110of the structure. A doping material145is formed on the exposed fin structures135of the PFET region105. That is, in embodiments, the doping material145is formed on the upper or exposed portions, e.g., above the blocking layer130, of the fin structures135of the PFET region105. In embodiments, the doping material145can be a Borosilicate glass (BSG), and more specifically, can be composed of boron doped SiO2. As an example, the thickness of the doping material145can be in a range of about 3 nm to about 5 nm; although other dimensions are also contemplated herein. In embodiments, the hardmask140will prevent the doping layer145from forming on the fin structures122on the NFET region110.

Still referring toFIG. 2A, the deposition of the doping material145can occur by various deposition processes, e.g., chemical vapor deposition (CVD), sub-atmospheric CVD (SACVD), or atomic layer deposition (ALD). Regardless of the deposition process, the doping material145can be driven into the exposed portions, e.g., SiGe region125, of the fin structures135on the PFET region105, above the diffusion blocking material130. For example, the dopants can be driven into the exposed fin structure135by an annealing process, e.g., at a temperature in a range of about 300-1100° C., for a duration in a range of about 5-30 minutes. This annealing process can be followed by removal of an oxide layer using a conventional cleaning process. The diffusion blocking layer130will prevent diffusion of the dopants into the lower portion of the fin structures135on the PFET region105.

Alternatively, as shown inFIG. 2B, doping of the exposed fin structures135can occur by an ion plasma doping process. In this process, the hardmask140is deposited on the fin structures122on the NFET region110. Following the deposition of the hardmask140, the exposed fin structures135and, more specifically, the exposed regions/portions125, e.g., SiGe regions, of the fin structures122on the PFET region105will undergo an ion plasma doping process. In embodiments, the energy level utilized in the ion plasma doping process is dependent upon the required doping levels. As an example, though, the energy levels can be in a range of about 5e14-5e15with a concentration in a range of about 5e20-1e21Again, the blocking layer130will prevent diffusion of the dopants into the lower portion of the fin structures135on the PFET region105. In embodiments, the doping process can also occur post spacer deposition, e.g., SiN, SiOCN spacer deposition.

InFIG. 3, a spacer material150is deposited on the exposed fin structures135and fin structures122across both the PFET region105and NFET region110. The spacer material150can be composed of any suitable insulator material, e.g., SiN/SiOCN. In embodiments, the spacer material150can be deposited using a CVD process, as an example. Following the deposition of the spacer material150, a hardmask155can be provided on the fin structures122on the NFET region110to protect the spacer material150during subsequent etching processes. Alternatively, the driving of the dopants into the exposed fin structures135, e.g., SiGe regions125, can occur post deposition of the spacer material150.

In embodiments, the spacer material150on the PFET region105is pulled down by using a conventional anisotropic etching process. Depending on the epitaxial layer that will be grown in later steps, the spacer material150can be etched down to certain heights, e.g., to about 5 nm to about 15 nm; although other dimensions are also contemplated herein. As noted above, the doping of the exposed portions of the fin structures135(to form source and drain regions) can occur post deposition of spacer material150. Under this alternative approach, the dopant is driven into the spacer material150, allowing for a lower-k potential.

InFIG. 4, the doped exposed fin structures135on the PFET region105are merged together by an epitaxial growth process to form raised doped source and drain regions160, i.e., SiGe:B doped merged portions160. In embodiments, the doped source regions and the doped drain regions160can each be merged by the growth process, with the spacer material150preventing the epitaxial material from growing on sides of the exposed fin structures135. In embodiments, the doped source and drain regions160can also be separate structures (e.g., unmerged) depending on the growth process, e.g., growth time, and fin pitch of the exposed fin structures135. Following the growth process, gates structures can be formed over the fin structures, e.g., doped source and drain regions160, using conventional deposition and patterning process, as should be known to those of skill in the art. Again, a hardmask155can be provided on the fin structures122on the NFET region110.

FIG. 5shows an alternative structure beginning from eitherFIG. 2AorFIG. 2B. In this structure100′, a SiGe:C cladding layer165is formed on the exposed fin structures135, post doping processes, on the NFET region110of the structure. In embodiments, the SiGe:C cladding layer165can have a thickness of about 2 nm to about 3 nm. The spacer material150is deposited on the SiGe:C cladding layer165and subsequently pulled down by using a conventional anisotropic etching process as described herein. As should be understood by those of skill in the art, the SiGe:C cladding layer165will prevent boron diffusion from outgassing from the doped fin structures135and into the spacer material150. Again, a hardmask155can be provided on the fin structures122on the NFET region110.

InFIG. 6, the exposed fin structures135on the PFET region105are merged together by an epitaxial growth process to form doped source and drain regions160, i.e., SiGe:B doped merged portions of the fin structures160. In embodiments, the doped source and drain regions160can be merged together by the growth process, with the spacer material150preventing the epitaxial material from growing on sides of the fin structures135. In embodiments, the doped source and drain regions160can be separate (e.g., unmerged) depending on the growth process, e.g., growth time, and fin pitch of the doped fin structures135. Again, a hardmask155can be provided on the fin structures122on the NFET region110.

In embodiments, as shown inFIG. 7, blocking material170is formed on the PFET region105to protect the doped source and drain regions160, e.g., fin structures135. A conventional source and drain etching is performed between the fin structures122, using a selective etch chemistry to the oxide material124, e.g., dielectric material. In this process, sidewalls of the fin structures122are exposed. Source and drain material is formed in the cavity to form source and drain regions175. In embodiments, the source and drain material can be doped semiconductor material, grown from the sidewalls of the exposed fin structures122. In this way, an embedded source region and drain region can be formed on the NFET region110of the device. Following the source and drain region formation for both the NFET region110and the PFET region105, gates structures can be formed over the fin structures, e.g., doped source and drain regions160and source and drain region175, using conventional deposition and patterning process, as should be known to those of skill in the art.