Methods of fabricating three-dimensional nonvolatile memory devices using expansions

Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. application claims priority under 35 U.S.C. §119 to Korean Patent Application 10-2009-0023626, filed on Mar. 19, 2009, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.

BACKGROUND

The present disclosure herein relates to three-dimensional nonvolatile memory devices and methods of fabricating the same.

Microelectronic devices are widely used in many consumer, commercial and other applications. As the integration density of microelectronic devices continues to increase, three-dimensional microelectronic devices may be fabricated, wherein active devices, such as transistors, are stacked on a microelectronic substrate, such as an integrated circuit substrate.

In particular, memory devices are widely used for general storage and transfer of data in computers and other digital products. In some memory devices, a string of memory cells are connected in series. Moreover, in order to increase the integration density of memory devices, three-dimensional or vertical memory devices have been developed, wherein a string of serially connected memory cells is formed by the memory cells vertically being stacked on a face of a substrate, wherein a first memory cell in the string of serially connected memory cells is adjacent the face of the substrate and a last memory cell in the string of serially connected memory cells is remote from the face of the substrate. As used herein, and as conventionally used, the “vertical” direction is generally orthogonal to the face of the substrate, whereas the “horizontal” direction is generally parallel to (extending along) the face of the substrate. By vertically stacking the memory cells to form the string, increased integration density may be provided. These vertically stacked structures may also be referred to as “three-dimensional” memory devices.

SUMMARY

The present disclosure relates to three-dimensional nonvolatile memory devices that can have excellent reliability and methods of fabricating the same by simple processes.

Embodiments of the inventive concept provide methods of fabricating three-dimensional nonvolatile memory devices. These methods include: forming openings penetrating interlayer insulating layers and conductive layers stacked alternately on a substrate; forming expansions having a diameter wider than that of the openings penetrating the interlayer insulating layers by selectively recessing sidewalls of the conductive layers exposed by the openings; forming first insulating layers on surfaces of the conductive layers exposed by the expansions; forming floating gates disposed in the expansions interposing the first insulating layers; forming second insulating layers on surfaces of the floating gates adjacent to the openings; and forming semiconductor pillars filling the openings.

In some embodiments, the forming of the expansions may include: isotropically etching the conductive layers so as to selectively etch the conductive layers more than the substrate and the interlayer insulating layers, and the forming of the floating gates may include: forming buried conductive layers filling the openings and the expansions; and anisotropically etching the buried conductive layers to expose an upper surface of the substrate.

In other embodiments, the forming of the first insulating layers and the second insulating layers may include performing an oxidation process or deposition process.

In still other embodiments, the methods may further include: forming sequentially stacked lower interlayer insulating layers and lower conductive layers including lower openings provided with sidewalls to be connected successively to the openings on the substrate, before forming the openings.

In yet other embodiments, the methods may further include: isolating the interlayer insulating layers and the conductive layers from each other between the semiconductor pillars; and forming silicide layers on surfaces of the isolated conductive layers.

According to other embodiments, three-dimensional nonvolatile memory devices may be fabricated by forming openings penetrating interlayer insulating layers and conductive layers stacked alternately on a substrate. Then, the sidewalls of the conductive layers that are exposed by the openings are recessed relative to the sidewalls of the interlayer insulating layers that are exposed by the openings, to thereby define expansions between portions of adjacent insulating layers that are exposed by the recessing of the sidewalls of the conductive layers. In some embodiments, the expansions are ring-shaped expansions surrounding the openings. Floating gates are then form in the expansions. Semiconductor pillars are then formed in the openings to extend on the floating gates and on the sidewalls of the interlayer insulating layers.

In some embodiments, between the recessing of the sidewalls and the forming of the floating gates, an insulating layer is formed on the sidewalls of the conductive layers. Moreover, between the forming of the floating gates and the forming of the semiconductor pillars, an insulating layer may be formed on the floating gates, adjacent the openings. Two separate insulating layers may also be formed in some embodiments.

In yet other embodiments, the sidewalls are recessed by selectively etching the sidewalls of the conductive layers that are exposed by the openings relative to the sidewalls of the interlayer insulating layers that are exposed by the openings. Moreover, in some embodiments, the floating gates may be formed in the expansions by forming a conductive layer in the openings and in the expansions, and removing the conductive layer from the openings while allowing the conductive layer to remain in the expansions.

In still other embodiments, prior to forming the openings, lower insulating layers and lower conductive layers are sequentially stacked upon one another on the substrate. Lower openings are formed penetrating the lower insulating layers and the lower conductive layers. Moreover, when the openings are formed in the interlayer insulating layers and conductive layers, they are aligned to the lower openings.

In yet other embodiments, a silicide layer is also formed on sidewalls of the floating gates opposite the semiconductor pillars. In some embodiments, prior to forming the silicide layer, a conductive layer may be formed on the sidewalls of the floating gates opposite the semiconductor pillars.

Embodiments of the inventive concept also provide three-dimensional nonvolatile memory devices, including: semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate; floating gates electrically isolated by the interlayer insulating layers and locally interposed between the semiconductor pillars and the conductive layers; first insulating layers interposed between the floating gates and adjacent sidewalls of the conductive layers; and second insulating layers interposed between the floating gates and the semiconductor pillars.

In some embodiments, the floating gates may be interposed between the interlayer insulating layers adjacent to each other, and the first insulating layers may be disposed between the floating gates and the interlayer insulating layers by extending from the floating gates and the sidewalls of the conductive layers.

In other embodiments, the second insulating layers may surround the semiconductor pillars by vertically extending to sidewalls of the interlayer insulating layers from sidewalls of the floating gates.

In still other embodiments, the conductive layers may include selection line conductive layers, the second insulating layers may be interposed between the selection line conductive layers and the semiconductor pillars, and the selection line conductive layers may come in directly contact with the second insulating layers.

In yet other embodiments, each of the conductive layers may have a multi-layered structure disposed in parallel between adjacent interlayer insulating layers.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “having,” “having,” “includes,” “including” and/or variations thereof, when used in this specification, specify the presence of stated features, regions, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, steps, operations, elements, components, and/or groups thereof.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, materials, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, material, region, layer or section from another element, material, region, layer or section. Thus, a first element, material, region, layer or section discussed below could be termed a second element, material, region, layer or section without departing from the teachings of the present invention.

Relative terms, such as “lower”, “back”, and “upper” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the structure in the Figure is turned over, elements described as being on the “backside” of substrate would then be oriented on “upper” surface of the substrate. The exemplary term “upper”, can therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure. Similarly, if the structure in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below. However, as used herein, and as conventionally used, the “vertical” direction is generally orthogonal to the face of the substrate regardless of its orientation, whereas the “horizontal” direction is generally parallel to (extending along) the face of the substrate.

FIG. 1is a circuit diagram illustrating three-dimensional nonvolatile memory devices according to various embodiments of the inventive concept.

Referring toFIG. 1, a nonvolatile memory device according to some embodiments of the inventive concept includes a cell array having a plurality of strings STRs. The cell array includes a plurality of bit lines BL1to BL4, word lines WL1to WL3, upper selection lines USL1to USL3, a lower selection line LSL, and a common source line CSL. In addition, the nonvolatile memory device includes a plurality of strings STRs between the bit lines BL1to BL4and the common source line CSL.

Each of the strings STRs includes upper and lower selection transistors UST and LST and a plurality of memory cell transistors MC connected between the upper and lower selection transistors UST and LST in series. A drain of the upper selection transistor UST is connected to the bit lines BL1and BL4, and a source of the lower selection transistor LST is connected to the common source line CSL. The common source line CSL is a line to which the sources of the lower selection transistors LSTs are connected in common.

Further, the upper selection transistors USTs are connected to the upper selection lines USL1and USL3, and each of the lower selection transistors LSTs is connected to the lower selection line LSL. In addition, each of memory cells MCs is connected to word lines WL1to WL3.

Since the above-mentioned cell array is arranged in the three-dimensional structure, the strings STRs have a structure in which the memory cells MCs are connected to each other in series in a Z-axis direction perpendicular to X-Y plane in parallel to the upper surface of a substrate. Accordingly, channels of the selection transistors UST and LST and channels of the memory cell transistors MCs may be formed in a direction perpendicular to X-Y plane.

In the three-dimensional nonvolatile memory device, m memory cells may be formed in each X-Y plane, and X-Y plane having the m memory cells may be stacked with n layers (where, m and n are natural numbers).

Nonvolatile memory devices according to various embodiments of the inventive concept will be described below with reference toFIGS. 2 through 9.

A nonvolatile memory device according to first embodiments of the inventive concept will be described.

Referring toFIGS. 2 and 3, interlayer insulating layers110(seeFIG. 2) and conductive layers LSL WL, and USL may alternately be stacked on a substrate100, repeatedly. The substrate100may be a semiconductor substrate including an impurity region105(for example, well region) used as a common source line CSL (seeFIG. 1). Out of the conductive layers LSL, WL, and USL, the uppermost layer may be used as an upper selection line USL, the lowermost layer may be used as a lower selection line LSL, and remaining conductive layers may be used as word lines WLs. The conductive layers may be made of a conductive poly silicon and/or metal material.

The lower selection line LSL may be formed in a plate shape or a line shape separated from each other. The upper selection line USL may be formed in a line shape separated from each other. The word lines are located between the upper selection line USL and the lower selection line LSL. The word lines may be a plate shape. Since the word lines are formed in the plate shape on each layer, the same voltage may be applied to the word lines of the memory cells formed on the same layer.

In addition, the word lines WLs formed at an upper part may have a relatively small area compared to the word lines WLs formed at a lower part. That is, the stacked structure of the interlayer insulating layers110(seeFIG. 2) and the conductive layers LSL, WL, and USL may have a staircase-shaped edge.

A plurality of semiconductor pillars PLs may be disposed on the substrate100. The plurality of semiconductor pillars PLs penetrates the stacked interlayer insulating layers110and conductive layers LSL, WL, and USL. The semiconductor pillars PLs may be electrically connected to the impurity region105included in the substrate100. The semiconductor pillars PLs are spaced from one another and may be arranged in the form of a planar matrix. The semiconductor pillars PLs are formed of a semiconductor material. Moreover, the semiconductor pillars PLs may correspond to each string of the nonvolatile memory device. Channels of the selection transistors and memory cell transistors of each string may be electrically connected to each other through the semiconductor pillars PLs. The semiconductor pillars PLs may be a cylindrical shape but are not limited thereto. The semiconductor pillars PLs may have the same conductivity as a whole. At least, surfaces of the semiconductor pillars PLs may have the same conductivity. Channels of the nonvolatile memory devices according to the embodiments of the inventive concept may be formed in the semiconductor pillars PLs.

Floating gates FGs may be interposed between sides of the semiconductor pillars PLs and the word lines WLs. Furthermore, the floating gates FGs may be interposed between the interlayer insulating layers110(seeFIG. 2) adjacent to each other. That is, the floating gates FGs may be spaced from each other by the interlayer insulating layers110(seeFIG. 2). For instance, the floating gates FGs may surround the semiconductor pillars PLs in the form of a doughnut or ring between the interlayer insulating layers110(seeFIG. 2). At this time, a gate insulating layer143may selectively be interposed between the side of the semiconductor pillar PL and the floating gates FGs. Except for a surface coming in contact with the gate insulating layer143, the remaining surface of the floating gate FG may be surrounded by an inter-gate dielectric layer IGD. That is, the inter-gate dielectric layer IGD may be interposed between the floating gate FG and the word line WL and between the floating gate FG and the interlayer insulating layer110(seeFIG. 2).

The gate insulating layer143may be interposed between the semiconductor pillar PL and a selection line pattern SLP. The selection line pattern SLP may be surrounded by a middle gate dielectric layer MGD, similar to the floating gate FG is surrounded by the inter-gate dielectric layer IGD. The selection line pattern SLP may be made of the same material as the floating gate FG.

Accordingly, the gate insulating layers143surround the semiconductor pillars PLs, but may be spaced from the floating gates FGs.

Bit lines BLs may be formed on upper surfaces of the semiconductor pillars PLs to electrically connect with the semiconductor pillars PLs. The bit lines BLs may be disposed to intersect with the upper selection lines USLs. At this time, each of the semiconductor pillars PLs may be disposed at places where the bit lines BLs and the upper selection lines USLs are intersected with each other.

A perpendicular interval between the floating gates FGs may be adjusted depending on a thickness of the interlayer insulating layer. In addition, the thickness of the interlayer insulating layer may be determined not by a patterning process but by a thin film forming process. Therefore, the thickness of the interlayer insulating layer may be thinner than a limit of a patterning resolution. As a result, according to these embodiments of the inventive concept, the nonvolatile memory device including the floating gates may be operated using a fringe field. As described above, all of the semiconductor pillars according to this embodiment of the inventive concept may have the same impurity type. Furthermore, the impurity type of the semiconductor pillars according to this embodiment of the inventive concept may be a conductivity type opposite to the impurity type pf the floating gates.

A nonvolatile memory device according to a second embodiments of the inventive concept will be described below with reference toFIGS. 4 and 5. Hereinafter, with respect to the nonvolatile memory device according to the first embodiment of the inventive concept, same or similar components will be omitted or briefly described, and different components (e.g., gate insulating layer and inter-gate dielectric layer) will be described.

Referring toFIGS. 4 and 5, the gate insulating layer143may be interposed between the side of the semiconductor pillar PL and the floating gates FGs and interposed between the side of the semiconductor pillar PL and the interlayer insulating layer110(seeFIG. 4). That is, the gate insulating layer143may extend along the side of the semiconductor pillar PL to surround the entire side of the semiconductor pillar PL.

Except for a surface coming in contact with the gate insulating layer143, the remaining surface of the floating gate FG may be surrounded by the inter-gate dielectric layer IGD. The inter-gate dielectric layer IGD may be configured to have a plurality of layers IGD1, IGD21, and IGD22. According to other embodiments of the inventive concept, the inter-gate dielectric layer IGD may be configured to have a multi-layered structure only between the floating gate FG and the word lines WLs.

The selection line pattern SLP may be surrounded by the middle gate dielectric layer MGD including double layers MGD1and MGD2in a similar manner as the floating gate FG.

A three-dimensional nonvolatile memory device will be described below with reference toFIGS. 6 and 7. Hereinafter, with respect to the nonvolatile memory device according to the first and second embodiments of the inventive concept, same or similar components will be omitted or briefly described, and different components (e.g., selection line layer) will be described.

Referring toFIGS. 6 and 7, the floating gates FGs may selectively be interposed only between the side of the semiconductor pillar PL and the word lines WLs. In addition, the floating gates FGs are interposed between the interlayer insulating layers110(seeFIG. 6) adjacent to each other and may perpendicularly be spaced from one another along the semiconductor pillar PL. At this time, the gate insulating layer143may locally be interposed between the side of the semiconductor pillar PL and the floating gates FGs. Alternatively, the gate insulating layer143may extend along the side of the semiconductor pillar PL. Except for a surface coming in contact with the gate insulating layer143, the remaining surface of the floating gate FG may be surrounded by the inter-gate dielectric layer IGD. The inter-gate dielectric layer IGD may have a stacked structure of oxide/nitride/oxide (IGD1/IGD2/IGD3).

The gate insulating layer143may be only interposed between the selection lines USL and LSL and the semiconductor pillar PL. That is, unlikeFIG. 2orFIG. 4, the memory device ofFIG. 6may not include a different conductivity pattern such as a floating gate between the selection lines USL and LSL and the semiconductor pillar PL.

A three-dimensional nonvolatile memory device will be described below with reference toFIGS. 8 and 9. Hereinafter, with respect to the nonvolatile memory devices according to the first to third embodiments of the inventive concept, same or similar components will be omitted or briefly described, and different components (e.g., selection line layer) will be described.

Referring toFIGS. 8 and 9, interlayer insulating patterns115and conductive line patterns LSL, WL, and USL may alternately be stacked on a substrate100, repeatedly. Out of the conductive line patterns LSL, WL, and USL, the uppermost layer may be used as an upper selection line USL, the lowermost layer may be used as a lower selection line LSL, and remaining conductive line patterns may be used as word lines WLs.

The conductive line patterns LSL, WL, and USL may be a line shape extending in the same direction. One stack constituted by the conductive line patterns LSL, WL, and USL may be isolated from a neighboring stack. At this time, the conductive line patterns used as word lines WLs may be connected to each other on the same layer such that the same voltage is applied thereto.

Line-shaped isolation insulating pattern180may be disposed between the adjacent conductive line patterns LSL, WL, and USL.

A plurality of semiconductor pillars PLs, which penetrate the stacked interlayer insulating patterns115and the conductive line patterns LSL, WL, and USL, may be disposed on the substrate100. The semiconductor pillars PLs may be spaced from each other in a row between the adjacent isolation insulating patterns180. The semiconductor pillars PLs may arranged in the form of a planar matrix.

Silicide layers121bmay be interposed into interfaces between the isolation insulating patterns180and the conductive line patterns LSL, WL, and USL. The silicide layers121bmay locally be disposed at the surface of the conductive line patterns LSL, WL, and USL coming in contact with the isolation insulating patterns180.

Methods of fabricating the three-dimensional nonvolatile memory devices according to the embodiments of the inventive concept will be described below.

FIGS. 10 through 16illustrate methods of fabricating a three-dimensional nonvolatile memory device according to first embodiments of the inventive concept.

Referring toFIG. 10, interlayer insulating layers110and conductive layers120may alternately be stacked on a substrate100, repeatedly. The substrate100may include an impurity region105(for example, well region). Out of the stacked layers110and120, the uppermost layer may be an interlayer insulating layer. The number of stacked conductive layers may be changed by the capacity of the nonvolatile memory device. The interval between the conductive layers120may be determined by adjusting the thickness of the interlayer insulating layers110.

The interlayer insulating layers110and the conductive layers120may be stacked in the form of a plate on a memory cell of the substrate100

At this time, with respect to the interlayer insulating layers110and the conductive layers120, the area may gradually reduce in the order in which the interlayer insulating layers110and the conductive layers120are stacked from the substrate100. For instance, edges of the interlayer insulating layers110and the conductive layers120may have a staircase shape. The interlayer insulating layers110and the conductive layers120may be formed by repeatedly carrying out a depositing process and a patterning process, respectively. Alternatively, after all of the interlayer insulating layers110and the conductive layers120are stacked, each layer may selectively be patterned layer-by-layer.

The interlayer insulating layers110may include a silicon oxide layer and/or a silicon nitride layer. The conductive layers120may include a lower conductive layer122and an upper conductive layer126that are sequentially stacked from the substrate100. A middle conductive layer124may be stacked between the lower conductive layer122and the upper conductive layer126. The lower conductive layer122, the upper conductive layer126, and the middle conductive layer124may have the same etch selectivity. For instance, the lower conductive layer122, the upper conductive layer126, and the middle conductive layer124may be formed of the same material. The conductive layers may contain polysilicon and/or metal material.

The upper conductive layer126may be patterned in the form of a line.

Referring toFIG. 11, a plurality of first openings131may be formed by etching the stacked interlayer insulating layers110and the conductive layers120. The first openings131penetrate the stacked interlayer insulating layers110and the conductive layers120. For instance, a mask pattern (not illustrated) is formed on the uppermost layer of the interlayer insulating layers110, and an anisotropic etching is selectively performed on the interlayer insulating layers110and the conductive layers120exposed by the mask pattern. The impurity region105of the substrate100may be exposed to bottom faces of the first openings131, and the interlayer insulating layers110and the conductive layers120may be exposed to inner walls of the first openings131. The first openings131may be a circular type, and the diameter of the first openings131may be smaller than a horizontal distance between the adjacent first openings131. Furthermore, the first openings131may be provided in the form of a planar matrix.

Referring toFIGS. 11 and 12, conductive patterns121may be formed by selectively recessing the conductive layers120exposed to the inner walls of the first openings131. For instance, an isotropic etching may be performed on the resulting structure ofFIG. 11. The isotropic etching may be performed such that the conductive layers120are selectively etched compared to other layers. The conductive patterns121may include a lower conductive pattern123and an upper conductive pattern127that are sequentially stacked from the substrate100. Middle conductive patterns125may be stacked between the lower conductive pattern123and the upper conductive pattern127. The middle conductive patterns125may be used as a control gate (or word line). When the conductive patterns121are formed, at the same time the inner walls of the first openings131constituted by the conductive layers120are selectively expanded. Consequently, second openings132may be formed.

The second openings132may have the same bottom face as the first openings131. Meanwhile, the inner walls of the second openings132may be constituted by the interlayer insulating layers110and the conductive patterns121. The second openings132may include expansions133surrounded by the adjacent interlayer insulating layers110and the conductive patterns121between the adjacent interlayer insulating layers110. The width or diameter of the expansions133may be larger than that of the openings surrounded by the interlayer insulating layers110. Accordingly, the expansions133may be viewed as expansions relative to the openings132or may be viewed as recesses relative to the interlayer insulating layers110. Stated differently, sidewalls of the conductive patterns125that are exposed by the openings132are recessed relative to sidewalls of the interlayer insulating layers110that are exposed by the openings, to thereby define expansions133between portions of adjacent insulating layers that are exposed by the recessing of the sidewalls of the conductive layers127.

Referring toFIG. 13, a first insulating layer141may be formed on the resulting structure ofFIG. 12. The first insulating layer141may conformally be formed on the resulting structure ofFIG. 12. That is, the first insulating layer141may be formed along the inner walls and the bottom faces of the second openings132. At this time, the first insulating layer141may be formed on the surfaces of the interlayer insulating layers110and the conductive patterns121exposed to the inner faces of the expansions133. The first insulating layer141may be a single layer or multiple layers. The first insulating layer141may be a composite layer of oxide/nitride/oxide. According to another embodiment of the inventive concept, the first insulating layer141may be formed of high dielectric constant materials.

The first insulating layer141may be formed by a deposition. For instance, the first insulating layer141may be formed by an atomic layer deposition (including modified process of atomic layer deposition) and/or a chemical vapor deposition (including modified processes such as Low Pressure Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition).

Referring toFIG. 14, a buried conductive layer151may be formed to fill the inside of the second openings132. The buried conductive layer151may fill the expansions133. The buried conductive layer151may be formed to cover the uppermost layer of the interlayer insulating layers. The buried conductive layer151may be formed of a conductive polysilicon.

Referring toFIG. 15, third openings134may be formed by performing the anisotropic etching with respect to the buried conductive layer151. The anisotropic etching may be performed using the interlayer insulating layers110as an etching mask. The anisotropic etching may be performed to expose the upper surface of the substrate100. Hereby, since a part of the buried conductive layer151remains in the expansions133, buried conductive patterns152may be formed. In addition, since the first insulating layer141formed on the inner walls of the second openings132, except for the expansions133, is selectively removed by the anisotropic etching, first insulating patterns142may locally be formed in the expansions133. Accordingly, the interlayer insulating layers110and the buried conductive patterns152may be exposed to the inner walls of the third openings134. At this time, the first insulating patterns142may surround other surfaces of the buried conductive patterns152except for the side exposed to the inner walls of the third openings134.

Alternatively, a planarization process may be performed on the buried conductive layer151to expose the upper surface of the uppermost layer of the interlayer insulating layers110. Subsequently, a mask pattern (not illustrated) may be formed on the uppermost layer of the interlayer insulating layers110to expose the buried conductive layer151formed in the second openings132. The anisotropic etching may selectively be performed on the buried conductive layer151using the mask pattern as an etching mask. After the buried conductive layer151is etched, the third openings134may be formed by removing the first insulating layer141formed on the bottom face of the exposed second openings132. At this time, the first insulating layer141may remain on the sidewalls of the third openings134. That is, the first insulating patterns142, which surround the buried conductive patterns of different layers, may be connected to each other along the inner walls of the third openings134.

Referring toFIG. 16, an oxidation process may be performed on the resulting structure ofFIG. 15. The oxidation process may be a thermal oxidation. Through the oxidation, an oxide layer may be formed on the surfaces of the buried conductive patterns152exposed to the inner walls of the third openings134. At this time, the upper surface of the substrate100, which is exposed to the bottom faces of the third openings134, may be also oxidized. The oxide layer formed on the bottom faces of the third openings134may be removed by the anisotropic etching. As a result, a gate insulating layer143may selectively be formed on the surface of the buried conductive patterns152exposed to the inner walls of the third openings134. The gate insulating layer143may be also formed by a radical oxidation process.

The third openings134may be filled with semiconductor materials. At this time, the uppermost layer of the interlayer insulating layers110may be covered with the semiconductor materials. The uppermost layer of the interlayer insulating layers110is exposed by the planarization process, and the semiconductor pillars PLs may then be formed in the third openings134. The semiconductor materials may include polycrystalline or single crystalline semiconductor.

The bit lines BLs may be formed on the semiconductor pillars PLs. A conductive layer is formed on the semiconductor pillars PLs and the uppermost layer of the interlayer insulating layers110. The bit lines BLs may then be formed by patterning the conductive layer. For this reason, the semiconductor pillars PLs may electrically be connected to the bit lines BLs.

FIGS. 17 and 18illustrate methods of fabricating a three-dimensional nonvolatile memory device according to second embodiments of the inventive concept. With respect to the method of fabricating the three-dimensional nonvolatile memory device according to the first embodiment of the inventive concept, same or similar components will be omitted or briefly described.

Referring toFIG. 17, a first insulating layer141may be formed on the resulting structure ofFIG. 12. The first insulating layer141may be double layers. The first insulating layer141may include a first sub-insulating layer144and a second sub-insulating layer145. The first sub-insulating layer144may be formed by an oxidation process. Accordingly, the first sub-insulating layer144may selectively be formed on the exposed surface of the conductive patterns121. Moreover, the upper surface of the substrate100may be oxidized by the oxidation process.

The second sub-insulating layer145may conformally be formed on the resulting structure. That is, the second sub-insulating layer145may be formed along the inner walls of the second openings132, the expansions133, and the bottom faces of the second openings132. The second sub-insulating layer145may be formed of high dielectric constant materials. The second sub-insulating layer145may be formed by a deposition. As a result, the first sub-insulating layer144and the second sub-insulating layer145may selectively be stacked on the exposed surface of the conductive patterns121.

Referring toFIG. 18, as described above, the buried conductive patterns152containing a conductive polysilicon are formed in the expansions133, and the third openings134may be formed. In this case, the buried conductive patterns152correspond to the sides of the third openings134. Furthermore, since the second sub-insulating layer145formed on the inner walls of the third openings134, except for the expansions133, is selectively removed by the anisotropic etching, second sub-insulating patterns146may be formed in the expansions133. Accordingly, the interlayer insulating layers110and the buried conductive patterns152may be exposed to the inner walls of the third openings134. At this time, the second sub-insulating patterns146may surround other surfaces of the buried conductive patterns152except for the side exposed to the inner walls of the third openings134.

Alternatively, the second sub-insulating patterns146, which surround the buried conductive patterns of different layers, may be connected to each other along the inner walls of the third openings134.

The gate insulating layer143may selectively be formed on the inner walls of the third openings134. The gate insulating layer143may be formed by a deposition and an anisotropic etching. For instance, the gate insulating layer143may be formed by an atomic layer deposition (including modified process of atomic layer deposition) and/or a chemical vapor deposition (including modified processes such as Low Pressure Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition). The insulating layer may conformally be formed on the resulting structure by the deposition. Subsequently, through the anisotropic etching, it can remove the insulating layer formed on the bottom faces of the third openings134and the uppermost layer of the interlayer insulating layers110.

Referring back toFIG. 4, the semiconductor pillars PLs may be formed in the third openings134. The semiconductor pillars PLs may have the upper surfaces that are substantially equal to the uppermost layer of the interlayer insulating layers110in height. The semiconductor materials may include polycrystalline and/or single crystalline semiconductor. The bit lines BLs may be formed on the semiconductor pillars PLs.

FIGS. 19 through 29illustrate methods of fabricating a three-dimensional nonvolatile memory device according to third embodiments of the inventive concept.

Referring toFIG. 19, a lower interlayer insulating layer110aand a lower conductive layer122may be stacked on the substrate100in this order. The substrate100may include the impurity region105(for example, well region).

Referring toFIG. 20, a mask pattern (not illustrated) may be formed on the lower conductive layer122. The anisotropic etching may selectively be performed on the lower conductive layer122using the mask pattern as an etching mask. For this reason, lower openings130apenetrating the lower conductive layer122may be formed. At this time, the lower openings130amay be formed to expose the lower interlayer insulating layer110aand the substrate110. The mask pattern may be removed.

Referring toFIG. 21, a middle buried insulating layer110bmay be formed on the substrate100to fill the lower openings130a. Middle conductive layers124and middle interlayer insulating layers110cmay alternately be stacked on the middle buried insulating layer110b. Before the middle conductive layers124are formed, the middle buried insulating layer110bmay be planarized. The middle buried insulating layer110bon the lower conductive layer122may have the same thickness as the middle interlayer insulating layer110con the middle conductive layer124.

Referring toFIG. 22, a mask pattern (not illustrated) may be formed on the uppermost layer of the middle interlayer conductive layers110c. The mask pattern may be formed using a mask equal to a photo mask used for forming the lower openings130a. The anisotropic etching may selectively be performed on the middle conductive layers124and the middle interlayer insulating layers110cusing the mask pattern as an etching mask. For this reason, first middle openings130b130amay be formed to penetrate the middle conductive layers124and the middle interlayer insulating layers110c. At this time, the anisotropic etching may be performed using the middle buried insulating layer110bas an etch stop layer. An upper surface of the middle buried insulating layer110bis exposed to the bottom face of the first middle openings130b, and the middle conductive layers124and the middle interlayer insulating layers110cmay be exposed to the inner wall of the first middle openings130b.

Referring toFIG. 23, the middle conductive layers124, which are exposed to the inner wall of the first middle openings130b, may selectively be recessed. For this reason, middle conductive patterns125may be formed. The middle conductive patterns125may be used as a control gate (or word line). At the same time, the inner walls of the first middle openings130b, which are provided with the middle conductive layers124, may selectively be expanded. Consequently, second middle openings130cmay be formed. For instance, the isotropic etching may be performed on the resulting structure ofFIG. 22. The isotropic etching may be performed such that the middle conductive layers124are selectively etched compared to other layers.

The second middle openings130cmay have the same bottom face as the first middle openings130b. Meanwhile, the inner walls of the second middle openings130cmay be provided with the middle interlayer insulating layers110cand the middle conductive patterns125. The second middle openings130bmay include expansions133surrounded by the neighboring interlayer insulating layers110and the middle conductive patterns125between the neighboring interlayer insulating layers110. The diameter of the expansions133may be larger than that of the openings surrounded by the middle interlayer insulating layers110c.

Referring toFIG. 24, a sacrificial pattern110dmay be formed to fill the second middle openings130c. At this time, the sacrificial pattern110dmay be formed to fill the expansions133. The sacrificial pattern110dmay be formed by the deposition and planarlization. The sacrificial pattern110dmay have the upper surface that is substantially equal to the uppermost layer of the middle interlayer insulating layers110cin height. The sacrificial pattern110dmay be formed of materials having the etch selectivity with respect to the interlayer insulating layers110and the conductive layers120. For instance, the interlayer insulating layers110may contain a silicon nitride, the conductive layers120may contain a conductive polysilicon and/or metal, and the sacrificial pattern110dmay contain a silicon oxide.

An upper conductive layer126and an upper interlayer insulating layer110emay sequentially be stacked on the sacrificial pattern110dand the uppermost layer of the middle interlayer insulating layers110c. The upper conductive layer126may be patterned in the form of a line.

Referring toFIG. 25, a mask pattern (not illustrated) may be formed on the upper interlayer insulating layer110e. The mask pattern may be formed using a mask (e.g., reticle) equal to a photo mask used for forming the lower openings130aand/or the first middle openings130b. The anisotropic etching may selectively be performed on the upper interlayer insulating layer110eand the upper conductive layer126using the mask pattern as an etching mask. For this reason, an upper surface of the sacrificial pattern110dmay be exposed.

The sacrificial pattern110dmay selectively be removed. The sacrificial pattern110dmay be formed of materials having the etch selectivity different from that of the conductive layers122and126, the conductive patterns125, and the interlayer insulating layers110. Accordingly, through the isotropic etching, the conductive layers122and126, the conductive patterns125, and the interlayer insulating layers110are not etched or are etched to a minimum, while the sacrificial pattern110dmay selectively be etched. The sacrificial pattern110dis removed, and then the second middle openings130cmay be again formed.

The middle buried insulating layer110bmay be exposed to the bottom face of the second middle openings130c. The anisotropic etching may selectively be performed on the exposed middle buried insulating layer110busing the interlayer insulating layers110as an etching mask. Consequently, the first openings135may be formed to penetrate the upper conductive layer126, the middle conductive patterns125, and the lower conductive layer122and expose the upper surface of the substrate100.

The substrate100may be exposed to the bottom face of the first openings135. Further, the interlayer insulating layers110, the conductive layers122and126, and the conductive patterns125may be exposed to the inner wall of the first openings135. At this time, the first openings135may be a circular type. In addition, the first openings135may be a planar matrix shape. The first openings135may have different diameter for each region. For instance, the diameter of the first openings135penetrating the interlayer insulating layers110, the upper conductive layer126, and the lower conductive layer122may be smaller than that of the first openings135penetrating the middle conductive patterns125. That is, the first openings135may include the expansions133having a partially expansive diameter.

The interlayer insulating layers110, the conductive layers122and126, and the conductive patterns125may be stacked in the form of a plate on the memory cell of the substrate100. At this time, with respect to the interlayer insulating layers110, the conductive layers122and126, and the conductive patterns125, the area may gradually reduce in the order in which the interlayer insulating layers110, the conductive layers122and126, and the conductive patterns125are stacked from the substrate100. For instance, edges of the interlayer insulating layers110, the conductive layers122and126, and the conductive patterns125may have a staircase shape.

The interlayer insulating layers110may be formed of a silicon oxide and/or a silicon nitride. At least the sacrificial pattern110dmay be formed of materials that are selectively etched during the etching compared to the upper interlayer insulating layer110eand the middle buried insulating layer110b.

The conductive layers122and126and the conductive patterns125may include a polysilicon layer or metal layer. Moreover, the conductive layers122and126and the conductive patterns125may be formed of the same material or different material. At this time, at least the middle conductive patterns125may be formed of the same material.

Referring toFIG. 26, a first insulating layer141may conformally be formed on the resulting structure ofFIG. 21. That is, the first insulating layer141may be formed along the inner walls and the bottom face of the first openings135. At this time, the first insulating layer141may be formed on the surfaces of the interlayer insulating layers110and the middle conductive patterns125exposed to the inner face of the expansions133. The first insulating layer141may be a single layer or multiple layers. The first insulating layer141may be formed of high dielectric constant materials.

The first insulating layer141may be formed by the deposition. For instance, the first insulating layer141may be formed by an atomic layer deposition (including modified process of atomic layer deposition) and/or a chemical vapor deposition (including modified processes such as Low Pressure Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition). The first insulating layer141may further include an oxide layer that is selectively formed on the surface of the middle conductive patterns125exposed to the inner wall of the first openings135.

Referring toFIGS. 27 and 28, a buried conductive layer151may be formed to fill the inside of the first openings135. The buried conductive layer151may fill the expansions133. The buried conductive layer151may be formed of a conductive polysilicon.

Second openings136may be formed by performing the anisotropic etching with respect to the buried conductive layer151. The anisotropic etching may be performed using the upper interlayer insulating layers110eas an etching mask. The anisotropic etching may be performed to expose the upper surface of the substrate100. Consequently, since a part of the buried conductive layer151remains in the expansions133, buried conductive patterns152may be formed to serve as a floating gate. In addition, since the first insulating layer141formed on the inner walls of the first openings135, except for the expansions133, is selectively removed by the anisotropic etching, a first insulating pattern142serving as an interlayer insulating layer may be formed in the expansions133. Accordingly, the interlayer insulating layers110, the buried conductive patterns152serving as a floating gate, the upper conductive layer126, and the lower conductive layer122may be exposed to the inner walls of the second openings136. At this time, the first insulating pattern142may surround other surfaces of the buried conductive patterns152except for the side exposed to the inner walls of the second openings136.

Alternatively, the first insulating patterns142, which surround different floating gates, may be connected to each other along the inner walls of the second openings136.

Referring back toFIG. 6, the gate insulating layer143may selectively be formed on the upper conductive layer126, the buried conductive patterns152, and the lower conductive layer122exposed to the inner walls of the second openings136by performing the oxidation process and the anisotropic etching with respect to the resulting structure ofFIG. 28. Alternatively, the gate insulating layer143may extend along the inner walls of the second openings136by the deposition and anisotropic etching.

The second openings136may be filled with semiconductor materials, and then the semiconductor pillars PLs may be formed in the second openings136. The semiconductor materials may include polycrystalline or single crystalline semiconductor.

The bit lines BLs may be formed on the semiconductor pillars PLs.

FIG. 29illustrates methods of fabricating a three-dimensional nonvolatile memory device according to fourth embodiments of the inventive concept. With respect to the methods of fabricating the three-dimensional nonvolatile memory device according to the first to third embodiments of the inventive concept, same or similar components will be omitted or briefly described.

Referring toFIG. 29, the anisotropic etching may be performed to isolate the conductive patterns121stacked between the semiconductor pillars PLs of the resulting structure ofFIG. 16. By the anisotropic etching, line openings137may be formed to penetrate the stacked interlayer insulating layers110and conductive patterns121, and isolated conductive patterns121amay be formed. Moreover, interlayer insulating patterns115may be formed by patterning the interlayer insulating layers110.

Subsequently, silicide layers121bmay be formed on the surfaces of the isolated conductive patterns121aexposed to the inner walls of the line openings137by a silicidation process. At this time, the upper surface of the semiconductor pillars PLs can be protected by an insulating layer (not illustrated). The silicidation process may include metal layer deposition, heat treatment, and unreacted metal removal.

Subsequently, the line openings137may be buried with insulating materials, and the bit lines BLs may be formed on the semiconductor pillars PLs to electrically connect with the semiconductor pillars PLs.

The processes may be applicable to the method of fabricating the memory devices according to the above-described embodiments of the inventive concept.

FIG. 30illustrates an electronic device200including one or more nonvolatile memory devices according to various embodiments of the inventive concept. The electronic device200may be used in a wireless communication device such as PDA, a laptop computer, a mobile computer, a web tablet, a wireless phone, a cell phone, a digital music player and/or in all devices that can transmit and receive data in a wired and/or wireless environment.

The electronic device200may include a controller210, an input/output device220such as, a keypad, a keyboard, or a display, a memory230, and a wireless interface240, which are combined to each other through a bus250. The controller210may include at least one microprocessor, digital signal processor, microcontroller or the like. The memory230may be used to store instructions to be executed by the controller210. Moreover, the memory230may be used to store a user data. The memory230includes a nonvolatile memory device according to various embodiments of the inventive concept.

The electronic device200may use a wireless interface240to transmit data to a wireless communication network communicating using a RF signal or to receive data from network. The wireless interface240may include an antenna, a wireless transceiver and so on.

The electronic system200may be used in a communication interface protocol of a third generation communication system such as CDMA, GSM, NADC, E-TDMA, WCDMA, and CDMA2000.

FIG. 31illustrates a memory system including a nonvolatile memory device according to various embodiments of the inventive concept.

The memory system300may include a memory device310for storing mass data and a memory controller320. The memory controller320controls the memory device310so as to read data stored in the memory device310and/or to write data into the memory device310in response to read/write requests of a host330. The memory controller320may constitute an address mapping table for mapping an address provided from the host330(a mobile device or a computer system) into a physical address of the memory device310. The memory310includes one or more nonvolatile memory devices according to various embodiments of the inventive concept.

Embodiments of the inventive concept may include a three-dimensional nonvolatile memory device with the floating gates. According to various embodiments of the inventive concept, since the floating gates are stacked to be isolated from each other, it can prevent charges stored in the floating gates from being diffused into another cell after the floating gates are programmed.

Accordingly, the reliability of semiconductor devices can be improved, and the malfunction of memory devices can be reduced or prevented.

In addition, since the floating gates are formed using the etch selectivity between different layers, it can be formed by a simple operation.