SPDT switch with high linearity

A single-pole double-throw switch. In some embodiments, the switch includes a first switching transistor connected between a common terminal of the single-pole double-throw switch and a first switched terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switched terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the second switching transistor.

FIELD

One or more aspects of embodiments according to the present disclosure relate to switches, and more particularly to an SPDT switch with high linearity.

BACKGROUND

Switches (e.g., single-pole, double-throw (SPDT) switches) used for routing radio frequency and millimeter-wave signals may be fabricated using transistors and used in various applications, including, for example, transmit-receive switching for a transceiver. The performance of such switches may be limited in some designs, however, because of a loss of linearity that may result from insufficient bootstrapping, or because of return loss degradation that may result from the presence of parasitic capacitance associated with on-chip coupling capacitors.

Thus, there is a need for an improved design for an SPDT switch.

SUMMARY

According to an embodiment of the present disclosure, there is provided a single-pole double-throw switch, including: a first switching transistor connected between a common terminal of the single-pole double-throw switch and a first switched terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switched terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the second switching transistor.

In some embodiments, the gate of the first auxiliary transistor is connected to the gate of the second switching transistor.

In some embodiments, the gate of the second auxiliary transistor is connected to the gate of the first switching transistor.

In some embodiments, the single-pole double-throw switch further includes a first coupling capacitor connected between the first switched terminal of the single-pole double-throw switch and the first switching transistor.

In some embodiments, the single-pole double-throw switch further includes a second coupling capacitor connected between the second switched terminal of the single-pole double-throw switch and the second switching transistor.

In some embodiments: a channel width of the first auxiliary transistor is at most as great as a channel width of the first switching transistor, and a channel width of the second auxiliary transistor is at most as great as a channel width of the second switching transistor.

In some embodiments: the channel width of the first auxiliary transistor is at most 50% of the channel width of the first switching transistor, and the channel width of the second auxiliary transistor is at most 50% of the channel width of the second switching transistor.

In some embodiments: the channel width of the first auxiliary transistor is at most 35% of the channel width of the first switching transistor, and the channel width of the second auxiliary transistor is at most 35% of the channel width of the second switching transistor.

In some embodiments: the first switching transistor is connected directly to the common terminal without an intervening coupling capacitor, and the second switching transistor is connected directly to the common terminal without an intervening coupling capacitor.

According to an embodiment of the present disclosure, there is provided a transmit-receive circuit including: a single-pole double-throw switch having a common terminal, a first switched terminal, and a second switched terminal; a low-noise amplifier having an input connected to the first switched terminal, and a power amplifier having an output connected to the second switched terminal, the single-pole double-throw switch including: a first switching transistor connected between the common terminal of the single-pole double-throw switch and the first switched terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and the second switched terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the second switching transistor.

In some embodiments, the gate of the first auxiliary transistor is connected to the gate of the second switching transistor.

In some embodiments, the gate of the second auxiliary transistor is connected to the gate of the first switching transistor.

In some embodiments, the transmit-receive circuit further includes a first coupling capacitor connected between the first switched terminal of the single-pole double-throw switch and the first switching transistor.

In some embodiments, the transmit-receive circuit further includes a second coupling capacitor connected between the second switched terminal of the single-pole double-throw switch and the second switching transistor.

In some embodiments: a channel width of the first auxiliary transistor is at most as great as a channel width of the first switching transistor, and a channel width of the second auxiliary transistor is at most as great as a channel width of the second switching transistor.

In some embodiments: the channel width of the first auxiliary transistor is at most 50% of the channel width of the first switching transistor, and the channel width of the second auxiliary transistor is at most 50% of the channel width of the second switching transistor.

In some embodiments: the channel width of the first auxiliary transistor is at most 35% of the channel width of the first switching transistor, and the channel width of the second auxiliary transistor is at most 35% of the channel width of the second switching transistor. In some embodiments: the first switching transistor is connected directly to the common terminal without an intervening coupling capacitor, and the second switching transistor is connected directly to the common terminal without an intervening coupling capacitor.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments of an SPDT switch with high linearity provided in accordance with the present disclosure and is not intended to represent the only forms in which the present disclosure may be constructed or utilized. The description sets forth the features of the present disclosure in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent functions and structures may be accomplished by different embodiments that are also intended to be encompassed within the scope of the disclosure. As denoted elsewhere herein, like element numbers are intended to indicate like elements or features.

Referring toFIG. 1A, in some related art SPDT switch circuits, insufficient bootstrapping may compromise the linearity of the circuit. For example, when the first switching transistor200of the switch is turned on and the second switching transistor210of the switch is turned off, an input signal105present at the first switched terminal (Input B) may be present at the common node T (as a result of the first switching transistor200of the switch being turned on), and the same signal may also be present on the gate of the first switching transistor200, as a result of capacitive coupling between the main terminals (the source and the drain) of the first switching transistor200and the gate of the first switching transistor200(through internal capacitance in the first switching transistor200, i.e., through the gate-source capacitance of the first switching transistor200, and through the gate-drain capacitance of the first switching transistor200). As a result, the voltage between the gate and the main terminals is constant (i.e., it does not fluctuate with the signal) and equal to the DC bias voltage across these terminals. For example, if the gate bias is 1 V as shown, and the bias voltages of the main terminals are each 0 V as shown, then the gate is at a voltage that is 1 V greater than either main terminal (i.e., Vgs=Vgd=1 V). This behavior, of the gate voltage following the voltages of the main terminals of the transistor, as a result of capacitive coupling, so that the AC voltages on all three terminals are the same, may be referred to as “bootstrapping”. It will be understood that in the circuit ofFIG. 1A, neither transistor has a fixed source and a fixed drain; instead, one or the other of the main terminals may act as the drain at any point in time (and the other may act as the source) depending on the direction of the voltage across the main terminals.

In the circuit ofFIG. 1A, bootstrapping may fail to accomplish the same effect with respect to the second switching transistor210, which is turned off, because the signal110at the second switched terminal (Input A) may differ from the signal at the common node T (as illustrated, the signal110at the second switched terminal is zero, and the signal at the common node T is equal to the signal105at the first switched terminal). Because of this difference, the AC signal on the gate of the second switching transistor210may be a combination (e.g., a weighted average) of the signals at the two main terminals of the second switching transistor210(both of which are coupled to the gate by capacitive coupling), and (unlike the case for the first switching transistor200) the AC components of the voltages between the gate and the main terminals may therefore not vanish. The non-vanishing voltages between the gate and the main terminals may cause the conductivity of the channel of the second switching transistor210to be modulated by the AC signal, resulting in reduced linearity. Referring toFIG. 1B, in some embodiments, coupling capacitors may be used to make possible the application of bias voltages to the main terminals of both the first switching transistor200and the second switching transistor210. In such an embodiment, the linearity of the switch may be improved; the presence of the coupling capacitors and their associated parasitic capacitances, however, may result in degradation of both input return loss (S11) and output return loss (S22).

Referring toFIG. 2, in some embodiments, a circuit for an SPDT switch includes (like the circuits ofFIGS. 1A and 1B) a first switching transistor200and a second switching transistor210. The first switching transistor200and the second switching transistor210route signals in the SPDT switch, so that, for example, if the first switching transistor200is turned on, and the second switching transistor210is turned off, the first switched terminal215is electrically connected (or just “connected” for brevity) to the common terminal220and the common terminal220is not connected to the second switched terminal225. The circuit further includes a first auxiliary transistor230connected between the gate of the first switching transistor200and the common terminal220, a second auxiliary transistor240connected between the gate of the second switching transistor210and the common terminal220, a first coupling capacitor245, and a second coupling capacitor247. The gate of the first auxiliary transistor230is connected to the gate of the second switching transistor210, and the gate of the second auxiliary transistor240is connected to the gate of the first switching transistor200, as shown.

The bias voltages of the SPDT switch may each be selected from one of two voltages that may be referred to, respectively, as a “low” voltage (e.g., 0 V, as shown) and a “high” voltage (e.g., 1 V, as shown). These bias voltages may be supplied by a control circuit connected to four bias resistors206,208,216,218, as discussed in further detail below. The respective values of the high and low voltages may be selected to be any two voltage values for which the high voltage is sufficiently greater than the low voltage that (i) when the gate of a transistor of the SPDT switch is at the high voltage and the two main terminals of the transistor are at the low voltage, the transistor is turned on, and (ii) when the gate of a transistor of the SPDT switch is at the low voltage and the two main terminals of the transistor are at the high voltage, the transistor is turned off. Moreover, coupling capacitors at the common terminal220(which are present in the embodiment ofFIG. 1B) are not needed in the embodiment ofFIG. 2, because in the embodiment ofFIG. 2there is no need to maintain different bias voltages at the second main terminals204,214, of the first and second switching transistors200,210.

In a first state of the SPDT switch, in which the first switching transistor200is turned on and the second switching transistor210is turned off (and which is illustrated inFIG. 2), the DC voltage at the gate of the first switching transistor200is high (as a result of a high bias applied to a first gate bias resistor206by the control circuit), the DC voltage at the first main terminal202of the first switching transistor200is low (as a result of a low bias applied to a first terminal bias resistor208by the control circuit), and the DC voltage at the second main terminal204of the first switching transistor200is low (as a result of the first switching transistor200being turned on). Signals for the first state of the SPDT switch are shown inFIG. 2. A first signal250(having a nonzero AC component) is present at the first switched terminal215, and a second signal255(having no AC component) is present at the second switched terminal225.

As a result of the first switching transistor200being turned on, the AC signal250present at the first switched terminal215is transmitted (through the first switching transistor200) to the common terminal220. The DC voltage at the gate of the second switching transistor210is low (as a result of a low bias applied to a second gate bias resistor216by the control circuit). The DC voltage at the gate of the second auxiliary transistor240is high, as a result of the high bias applied to the first gate bias resistor206by the control circuit. The DC voltage at both of the main terminals of the second auxiliary transistor240is low, the DC voltage at a first main terminal242of the second auxiliary transistor240being low as a result of the low bias applied to the second gate bias resistor216by the control circuit, and the DC voltage at a second main terminal244of the second auxiliary transistor240being low as a result of the common terminal220being at the low DC voltage. The second auxiliary transistor240is therefore turned on, and it causes the AC signal at the common terminal220(which is substantially equal to the AC signal250present at the first switched terminal215) to appear at the gate of the second switching transistor210. In the first state, the first auxiliary transistor230is turned off.

It may be seen from the foregoing that in the first state, the second auxiliary transistor240remedies the problem of insufficient bootstrapping described above in the context ofFIG. 1A, and that in the embodiment ofFIG. 2, in the first state, the AC signal250is present, substantially unattenuated, at the gate of the second switching transistor210. As a result, the operating point of the second switching transistor210is consistent, substantially irrespective of the RF signal swing, and high linearity may result.

In the second state, in which the second switched terminal225is connected to the common terminal220and the first switched terminal215is not connected to the common terminal220, the bias voltages applied by the control circuit are reversed (a high bias is applied to the first terminal bias resistor208and to the second gate bias resistor216, and a low bias is applied to the second terminal bias resistor218and to the first gate bias resistor206). In the second state, the first switching transistor200and the second auxiliary transistor240are turned off, and the second switching transistor210and the first auxiliary transistor230are turned on. In the second state, the first auxiliary transistor230performs the function performed in the first state by the second auxiliary transistor240, i.e., it connects the common terminal220and the gate of the first switching transistor200, so that the AC signal is the same at the two nodes; as such, it remedies the problem of insufficient bootstrapping that would, in some embodiments, cause degraded linearity in the absence of the first auxiliary transistor230.

In some embodiments an SPDT switch is used as a transmit-receive select switch in a radio frequency or millimeter-wave transceiver. The first switched terminal215may be fed by a power amplifier305, and the second switched terminal225may feed a low noise amplifier315. The common terminal220may be connected to an antenna (e.g., through an antenna matching network). In operation, when the transceiver is transmitting, the SPDT switch may be in the first state, allowing a signal from the power amplifier305to propagate to the antenna, and when the transceiver is receiving, the SPDT switch may be in the second state, allowing a signal from the antenna to propagate to the low noise amplifier315. By disconnecting the respective unused signal path in each of the first (transmitting) state and the second (receiving) state, the SPDT switch may help to reduce or eliminate various problems (e.g., instability of the power amplifier305, noise from the power amplifier305degrading the signal received by the low noise amplifier315, and increased insertion loss and reduced return loss for the signals travelling in both directions) that might occur were both amplifiers connected directly to the antenna matching network without the intervening SPDT switch.

In some embodiments, an SPDT switch according to the circuit ofFIG. 2may exhibit superior performance to an otherwise similar circuit constructed according toFIG. 1A(e.g., using identical switching transistors and identical (albeit more) coupling capacitors, and lacking the auxiliary transistors of the circuit ofFIG. 2). For example, an SPDT switch constructed according to the circuit ofFIG. 2may exhibit a 3 dB (or more, e.g., 10 dB) higher (e.g., a 3 dBm higher) 1-dB-compression point (i.e., better linearity) than an otherwise similar circuit constructed according toFIG. 1A. Moreover, an SPDT switch constructed according to the circuit ofFIG. 2may exhibit better robustness to modelling limitations, and to process, voltage, and temperature variations, than an otherwise similar circuit constructed according toFIG. 1A.

The transistors of the SPDT switch may be field effect transistors as shown, e.g., metal oxide semiconductor field effect transistors (MOSFETs). N-channel MOSFETs may be used, both because N-channel MOSFETs may have higher majority carrier mobility than P-channel MOSFETs, and because, if the SPDT switch is connected to a ground-referenced source or load (e.g., a ground-referenced antenna), the signals transmitted by the SPDT switch may be near ground, and N-channel MOSFETs may be better able to transfer such signals than P-channel MOSFETs. The first auxiliary transistor230may be smaller than the first switching transistor200(e.g., the first auxiliary transistor230may have a channel width that is between 30% and 50% of the channel width of the first switching transistor200), or that is at most equal to the channel width of the first switching transistor200(e.g., the first auxiliary transistor230may have a channel width that is between 30% and 100% of the channel width of the first switching transistor200). Similarly, the second auxiliary transistor240may have a channel width that is between 30% and 100% of the channel width of the second switching transistor210.

As used herein, the two principal terminals of a transistor (e.g., the source and the drain, for a MOSFET, or the collector and the emitter, for a bipolar transistor) may be referred to as the “main” terminals of the transistor, and the terminal used to control the transistor (e.g., the gate, for a MOSFET, or the base, for a bipolar transistor) may be referred to as the “control” terminal of the transistor. As used herein, when the connections to a transistor are described with terminology used for two-terminal devices, it is the connections to the main terminals of the transistor that are described. For example, a transistor that is “connected between” two nodes of a circuit has a first one of the main terminals of the transistor connected to a first one of the two nodes and a second one of the main terminals of the transistor connected to a second one of the two nodes. As another example, when two transistors are said to be connected “in series” (as in the case of a CMOS inverter), a main terminal of one of the two transistors is connected to a main terminal of the other of the two transistors.

Although exemplary embodiments of an SPDT switch with high linearity have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Accordingly, it is to be understood that an SPDT switch with high linearity constructed according to principles of this disclosure may be embodied other than as specifically described herein. The invention is also defined in the following claims, and equivalents thereof.