Method, apparatus and system for responding to a row hammer event

Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

BACKGROUND

1. Technical Field

Embodiments of the invention are generally related to memory management, and more particularly to the control of memory refresh operations.

2. Background Art

With advances in computing technology, computing devices are smaller and have much more processing power. Additionally, they include more and more storage and memory to meet the needs of the programming and computing performed on the devices. The shrinking size of the devices together with the increased storage capacity is achieved by providing higher density devices, where the atomic storage units within a memory device have smaller and smaller geometries.

With successive generations of increasingly dense memory devices, intermittent failures have become more frequent. For example, some existing DDR3 based systems experience intermittent failures with heavy workloads. Researchers have traced the failures to repeated access to a single row of memory within the refresh window of the memory cell. For example, for a 32 nm process, if a row is accessed 550K times or more in the 64 millisecond refresh window, the physically adjacent wordline to the accessed row has a very high probability of experiencing data corruption. The row hammering or repeated access to a single row can cause migration across the passgate. The leakage and parasitic currents caused by the repeated access to one row cause data corruption in a non-accessed physically adjacent row. The failure issue has been labeled as a ‘row hammer’ or ‘row disturb’ issue by the DRAM industry where it is frequently seen.

Recently, targeted row refresh technologies have been introduced to mitigate the effects of row hammering. Various operations to facilitate targeted row refreshes tend to complicate the timing of other processes in a memory subsystem. As memory technologies continue to scale, it is expected that reliance on targeted row refresh techniques increase. This increased reliance poses a challenge to protecting the performance of DRAM and other types of memory systems.

DETAILED DESCRIPTION

Embodiments discussed herein variously provide techniques and/or mechanisms to facilitate a targeted refresh specific to a row of memory in a memory device. The row to be refreshed may, for example, be at risk of being a victim of row hammering at an adjacent target row. In an embodiment, a dynamic random access memory (DRAM) or other memory device detects an indication—e.g. received from a memory controller coupled thereto—that a particular target row is subject to row hammering.

In response to such an indication, the memory device may operate in a mode which facilitates preparations for an expected future—but, in an embodiment, not yet received—command to perform one or more operations for implementing a targeted row refresh. While operating in the mode, the memory device may keep track of a particular bank which includes the target row and one or more victim rows physically adjacent to the target row. While in the mode, but after preparations for a targeted row refresh have begun, the memory device may support access—e.g. read access, write access, etc.—to another bank or banks of the memory device which do not include the target row and victim row(s). In an embodiment, the memory device automatically exit the mode after an indication that all expected targeted row refreshes which are associated with the detected hammer event have been performed.

FIG. 1illustrates elements of a system100for implementing a targeted row refresh according to an embodiment. System100may include memory device110coupled to memory controller120. Memory device110may include any of a variety of types of memory technology that have adjacent rows of memory cells, where data is accessible via a wordline or the equivalent. In one embodiment, memory device110includes dynamic random access memory (DRAM) technology. Memory device110may be an integrated circuit package within a larger memory device (not shown) of system100. For example, memory device110may be a DRAM device of a memory module such as a dual in-line memory module (DIMM).

Memory device110may include memory resources140, which represents one or more logical and/or physical groups of memory. An example of one such grouping of memory is a bank150of memory resources140. Bank150may include an array of storage elements arranged in rows and columns. By way of illustration and not limitation, bank150may include row112and one or both of rows114,116physically adjacent to row112. There is no requirement for the number of rows and columns of a given bank to be equal, and in fact they are typically not equal.

In an embodiment, memory resources140comprise a plurality of banks including bank150. Some or all of such a plurality of banks may, for example, be disposed on a single integrated circuit chip (not shown) of memory device110. In an embodiment, the plurality of banks consist of banks in an integrated circuit package—e.g. of a 3D stacked memory device wherein the banks variously reside on a different chips of an IC chip stack.

Memory device110may include access logic170to facilitate, at least in part, access to memory resources140—e.g. where such access if provided for servicing one or more commands from memory controller120. Access logic170may include, or operate in conjunction with, logic of memory device110which provides resource access according to conventional techniques—e.g. where functionality of access logic170supplements such conventional techniques with additional functionality discussed herein. By way of illustration and not limitation, access logic170may include or couple to column logic142and row logic144, which are used to decode an access instruction to the proper memory location within bank150. Column logic142and/or row logic144may further provide functionality for accessing one or more other banks of memory resources140.

Memory controller120may send commands or instructions to memory device110over a command bus (e.g., a command/address (C/A) bus), which are then interpreted by memory device110. Memory device110may decode the command information to perform a variety of access functions within the memory, and decode address information via column logic142and row logic144. The logic may access a specific location in memory with a combination of a column address strobe or signal (CAS) and a row address strobe or signal (RAS). Rows of memory may be implemented in accordance with known memory architectures or their derivatives. Briefly, a row of memory may include one or more addressable columns of memory cells, as identified by the CAS generated by column logic142. The rows may each be variously addressable via the RAS generated by row logic144.

Memory resources140may include one or more rows that, during some operation of memory device100, are the targets of repeated access within a time window. Such a row may be subject to a row hammer condition. In many modern memory devices, the architecture of the semiconductor layout causes one or more physically adjacent rows to be at risk of becoming corrupted. The row or rows at risk of becoming corrupted due to row hammer condition are referred to herein as victim rows. At a given time during operation of system100, memory resources140may include target row112of bank150, which is a row of memory subject to hammering, or being accessed repeatedly within a given time period. The target row112is the target of the row hammer event. The one or more rows at risk of becoming corrupted due to row hammer of target row112are illustrated with victim row114and victim row116of bank150. Either or both of victim rows114,116may be at risk, depending on the physical layout of memory device110.

It will be understood that different memory device manufacturers use different logic and architectures to utilize the memory resources of the devices. For example, different memory device manufacturers may use different offsets to map between logical memory addresses used in a host processor and the physical memory addresses used internally to memory device110. In one embodiment, memory controller120utilizes the same logical memory addresses as used by a host processor (not shown) of system100. Thus, in one embodiment, memory controller120may provide a row address to memory device110indicating a particular row. The memory controller120may indicate the row address in conjunction with and/or as part of a command that it issues to memory device110.

However, in certain applications, memory controller120may not have access to a physical address of target row112and/or information describing, for example, the address offset between target row112and one or each of the physically adjacent victim rows114,116. Moreover, in the absence memory controller120specifying an address of victim row114or victim row116, memory device110may include logic to identify that victim row114or victim row116is to be a target of a targeted refresh to address hammering of target row112.

In an embodiment, memory controller120generates, in response to detecting a row hammer event, one or more commands122for causing memory device110to perform one or more targeted refreshes each of a respective row. In one embodiment, one or more commands122include a command or sequence of commands for refreshing a particular row of memory resources140. For example, in one embodiment, such a sequence may include an Activate command specifying activation of a potential victim row, followed by a Precharge command for that same potential victim row. Any of a variety of additional or alternative commands which explicitly specify such a potential victim row may be included in one or more commands122, according to different embodiments.

Detector130represents hardware and/or software or other logic that enables system100to detect a row hammer event. The mechanism or mechanisms used to detect the row hammer condition may not be limiting on certain embodiments. In an embodiment, detector130determines when target row112experiences repeated accesses within a threshold. Detector130may include hardware and/or logic at memory device110, memory controller120, and/or external to either or both of memory device110and memory controller120.

The mechanisms of detector130may include, for example, some way of determining a number of times a row is accessed, as well as determining the period of time in which the accesses occur. The row hammer event may not simply be about how many times a row is accessed, but how many times in a given time period. Once a row is refreshed, the conditions that could cause data corruption may be overcome. Thus, the time period for the monitoring should, in an embodiment, be based at least in part on the refresh rate. An exchange of one or more commands122, to overcome conditions that would otherwise cause data corruption, may take place in between normally scheduled refresh event that may occur periodically on a refresh cycle.

Memory device110may further include row hammer (RH) response logic160to perform one or more operations which facilitate performance of a targeted refresh. In response to detector130detecting an indication of a row hammer event, memory device110may be configured for operation in a mode for memory device110to prepare for servicing some or all of the one or more commands122. For example, based on configuration of memory device110to operate in such a mode, RH response logic160may perform one or more operations which facilitate a later performance of one or more targeted refreshes each of a respective victim row—e.g. a respective one of victim rows114,116. In an embodiment, the one or more operations are performed by RH response logic160before memory device110receives some, or any, of one or more commands122.

The one or more operations performed by RH response logic160may include, for example, activating circuitry—e.g. in access logic170—to prevent one or more types of access to memory resources140which might interfere with, delay or otherwise affect operations to implement a targeted row refresh. By way of illustration and not limitation, RH response logic160may signal that read access and/or write access to bank150is to be prevented at least temporarily.

Alternatively or in addition, the one or more commands performed by RH response logic160may include determining address information for a victim row (or victim rows) associated with a target row which is being hammered. Determining such address information may include performing a search or calculation to generate a result identifying an address, an address offset, an address mapping and/or the like as corresponding to a victim row for the detected row hammer event. Such a result may be available for use before memory device110receives a particular command which is to trigger such use to facilitate a targeted row refresh.

While memory device110is configured for operation in such a mode—e.g. during or after operations to prepare for a targeted refresh of a row in bank150, but before memory controller120subsequently triggers the targeted refresh—memory device110may support access to one or more banks (not shown) of memory resources140other than bank150. For example, access logic170may be configured to selectively block read access and/or write access to bank150, but to allow such read access and/or write access to another bank or banks of memory resources140.

FIG. 2illustrates elements of a system200according to an embodiment for performing operations in preparation for a targeted row refresh. System200may include a memory device coupled to host processor240via memory controller220, and can be one example of a system in accordance with system100ofFIG. 1. By way of illustration and not limitation, system200includes memory device DRAM210coupled to memory controller220. Memory controller220may be coupled in turn to host processor240.

Host processor240may be any type of processing unit, processor, or microcontroller. Host processor240may perform the primary execution of operations in system200. In an embodiment, some or all operations executed by host processor240originate from instructions and/or data stored in DRAM210. DRAM210may be a memory device in accordance with any of various embodiments described herein. DRAM210may include memory resources214comprising, for example, some or all of the features of memory resources140. In one embodiment, DRAM210is a volatile memory, or a memory device whose contents are non-deterministic if power is interrupted to the device. Thus, a volatile memory requires a regular power source to allow it to refresh the memory cells to keep the data from become lost or corrupted.

DRAM210may include hardware connectors (not shown) that interface with corresponding hardware connectors (not shown) of memory controller220. Memory access from host processor240typically goes through memory controller220. In one embodiment, memory controller220is part of host processor240. In an alternate embodiment, memory controller is part of a supporting “chipset” or hardware logic that provides an infrastructure for power and interface logic for a hardware platform of which host processor240is a part.

Certain embodiments are implemented entirely within a memory controller including some or all of the features of memory controller220. As mentioned above, a detector may enable memory controller220to identify a row hammer condition to be able to respond to the row hammer condition with one or more commands for implementing a targeted refresh. Detect logic230is illustrated as being part of memory controller220, and represents some or all of the logic needed to detect row hammering in system200. Memory controller220may further include command logic235, which represents hardware, software or other logic for memory controller220to perform its functions of managing memory access to DRAM210.

DRAM210may include logic (not shown), such as that of RH response logic160, to perform one or more operations in preparation for an expected future implementation of a targeted row refresh. In response to detect logic230detecting an indication of a row hammer event, command logic235may send one or more commands to configure a particular operational mode of DRAM210. In response to being so configured, DRAM210may prepare at least in part for performance of a targeted refresh—e.g. where such preparations are performed before command logic235subsequently triggers DRAM210to perform the targeted refresh.

While DRAM210is configured for operation in the mode, command logic235may send to DRAM210a command to access a particular bank of memory resources214. DRAM210may service the request after the one or more operations which are in preparation for the targeted row refresh, but before the memory controller triggers the DRAM210to perform the targeted row refresh. In an embodiment, servicing the request includes performing an access—e.g. including a read access and/or a write access—of a bank other than a bank which is to be accessed by the targeted row refresh.

In an illustrative scenario according to one embodiment, memory resources214includes a plurality of banks250a, . . . ,250n, where bank250aincludes a row252and at least one other row—illustrated by rows254,256—which is physically adjacent to row252. At some point in time during operation of system200, detect logic230may receive an indication that row252is a target of row hammering which poses a threat to data integrity in either or both of victim rows254,256. In response to detect logic230detecting hammering of target row252, command logic235may send a command—e.g. a mode register set (MRS) command—to place DRAM210into a mode for facilitating a future targeted refresh of either of victim rows254,256.

In response to being placed in such a mode, DRAM210may prepare at least in part for an expected future targeted row refresh—e.g. where such preparations are completed before memory controller220subsequently sends to DRAM210a command addressed to or otherwise targeting a victim row. In a time between DRAM210being set in the mode and the triggering of DRAM210to perform the targeted refresh, memory controller may send one or more commands to access another bank of memory resources214, such as bank250n. DRAM210may service the command before memory controller220triggers a targeted refresh of victim row254(or of victim row256).

FIG. 3illustrates elements of a method300for controlling a memory device according to an embodiment. Method300may be performed by a memory controller including some or all of the features of memory controller220, for example. In an embodiment, method300is performed to control a memory device, such as memory device110, which includes a first bank and a second bank, the first bank including a first row and a second row physically adjacent to the first row. In an embodiment, an integrated circuit chip of the memory device includes both the first bank and the second bank.

Method300may include, at310, receiving an indication that repeated access to the first row of the memory device exceeds a threshold. The indication may include any of a variety of indicia of a row hammer event including, but not limited to, a command from a host, a control signal from the memory device, a signal exchanged between detect logic and command logic of the memory controller, and/or the like. By way of illustration and not limitation, detect logic of the memory controller maintain or otherwise keep track of a count of accesses of the first row and/or an amount of time over which such accesses takes place. At a given time—e.g. at one of a plurality of scheduled intervals—the detect logic may compare a current count of the accesses to a threshold number. Based on the comparison, the detect logic of the memory controller may identify that the threshold has been exceeded. Alternatively, the memory device may include this or other such detect logic, where the memory device communicates to the memory controller that a threshold number of accesses to the first row has been exceeded. Certain embodiments are not limited with respect to the particular mechanism by which the indication received at310might be generated.

In an embodiment, method300includes, at320, configuring the memory device for operation in a first mode in response to the indication received at310. Based on the first mode, the memory device may perform one or more operations in preparation for a targeted refresh of the second row. By way of illustration and not limitation, command logic of the memory controller may send a MRS command to write configuration information to one or more mode registers of the memory device.

Such configuration information may include one or more bit values to enable the operational mode. In an embodiment, the configuring at320includes writing to a mode register an identifier of the bank—e.g. the first bank—which is the target of the indicated row hammering. For brevity, the term “reference bank” is used herein to indicate a bank which is being subject to a particular instance of row hammering. The identifier of the reference bank may, for example, be provided to the memory device in an MRS command, a next command subsequent to such an MRS command, or in some other signaling which the memory device is configured to recognize as being associated with the instance of the mode set at320.

Method300may further include, at330, sending a first command, wherein the memory device accesses the second bank to service the first command after performance of the one or more operations. The accessing of the second bank to service the first command is also while the memory device is configured for operation in the first mode. In an embodiment, the first command is for a type of access—e.g. including read access and/or a write access—which, at the time of first command is serviced, the memory device provides for the second bank but not for the first bank. Such selective restriction of access to the first bank may be based on the mode of the memory device which is configured at320.

In an embodiment, method300further includes, at340, sending a second command to the memory device after the first command is sent, wherein the memory device performs the targeted refresh of the second row in response to the second command. The second command may include, for example, one of an Activate command specifying activation of the second row, and a Precharge command for the second row.

FIG. 4illustrates elements of a memory device400for performing a targeted row refresh according to an embodiment. Memory device400may include some or all of the features of memory device110, for example.

Memory device400may include memory resources460comprising a plurality of banks470a, . . . ,470n. Two or more banks of memory resources460—e.g. including banks470a,470n—may each be included in a single integrated circuit chip of memory device400. In an embodiment, bank470aincludes a row472and one or more other rows, represented by the illustrative rows474,476, which are each physically adjacent to target row472. In an illustrative scenario according to one embodiment, some row of memory resources460—e.g. row472—may be subject to row hammering which poses a risk to data integrity of one or more adjacent rows. In such a scenario, row472may be considered a target row and one or each of adjacent rows474,476may be considered a victim row.

Memory device400may further include detect logic410which, in response to detection of a row hammer event, is to configure the memory device for operation in a first mode. By way of illustration and not limitation, detect logic410may receive an indication that repeated access to the target row472exceeds a threshold. The indication may include, for example, a MRS command which memory device400receives from a memory controller (not shown). Configuring memory device400may include, for example, detect logic410writing to a mode register420configuration information to specify enablement of the first mode. Alternatively of in addition, detect logic410may store to mode register420information to identify bank470aas being the reference bank for one or more expected future targeted row refresh. Memory device400may further include response logic430—e.g. including some or all of the features of RH response logic160—to operate based on the first mode. In an embodiment, such operation includes response logic430performing, in response to the indicated hammering of target row472, one or more operations which aid in preparation for a targeted refresh of victim row474and/or a targeted refresh of victim row476.

By way of illustration and not limitation, response logic430may perform operations to lock bank470afrom one or more types of access which might otherwise impede or are not in the service of, performing a targeted row refresh. Alternatively or in addition, response logic430may search for, calculate and/or otherwise identify address information for a victim row based, for example, on an address of the identified target row472. In an embodiment, memory device400includes or otherwise has access to an address map400for use in identifying such address information. For example, response logic430may perform a lookup of reference information in address map440to identify an offset in logical addressing between physically adjacent rows, an assignment of a logical address to a redundant row in memory and/or any other such information for determining a physical address of victim row474and/or a physical address victim row476.

Memory device400may further include access logic450to service a first command after performance of the one or more operations, where memory device400receives the first command from a memory controller. The first command may, for example, include a write command, read command, or other such command to access one or more rows of bank470n. Servicing the first command may include access logic450accessing bank470nwhile memory device400is configured for operation in the first mode. In an embodiment, access logic450further performs a targeted refresh of a victim row of bank470a—e.g. one or victim rows474,476—in response to a second command which the memory device receives from the memory controller after the first command.

FIG. 5illustrates elements of a method500for operating a memory device according to an embodiment. Method500may be performed by a memory device including some or all of the features of memory device110, for example.

In an embodiment, method500includes, at510, configuring the memory device for operation in a first mode. The memory device may comprise a first bank and a second bank, where the first bank includes a first row and a second row physically adjacent to the first row. In an embodiment, an integrated circuit chip of the memory device includes the first bank and the second bank. The configuring at510may be in response to an indication that repeated access to some row of the first bank—e.g. the first row—exceeds a threshold.

Based on the configured first mode, method500may further include, at520, performing one or more operations in preparation for a targeted refresh of the second row, the one or more operations in response to the indication. The one or more operations may include, for example, activating logic to restrict an access to the first bank other than an access for a targeted refresh. Alternatively or in addition, the one or more operations may include determining address information corresponding to the second row. By way of illustration and not limitation, determining such address information may include accessing address map information to determine an address offset, a redundant row address and/or the like. The address map information may specify, for example, an offset between physically adjacent rows of the memory device.

After performance of the one or more operations at520, method500may further comprise, at530, servicing a first command from a memory controller, including accessing the second bank while the memory device is configured for operation in the first mode. In an embodiment, method500further includes, at540, performing the targeted refresh of the second row. Performance of the targeted row refresh at540may be in response to a second command received by the memory device from the memory controller after the first command. In an embodiment, method500further includes the memory device maintaining a count of accesses to the first bank subsequent to the mode being set. For example, circuitry such as that of response logic430may maintain such a count to keep track of whether all expected targeted row refreshes, associated with the hammering of the first row, have been completed. In response to the count reaching a threshold value—indicating all victim rows have been refreshed—the memory device may automatically reconfigure itself to discontinue operation according to the mode.

FIG. 6is a timing diagram600illustrating an exchange of commands from a memory controller to a memory device according to an embodiment. Timing diagram600may represent an exchange from memory controller120to memory device110, for example.

In timing diagram600, PRE All610represents a command to precharge all banks of the memory device prior to enablement of a mode to prepare for a future targeted row refresh. MRS TRR enable620represents a mode register set command to place the memory device in such a mode. By way of illustration and not limitation, MRS TRR enable620may set in a mode register MR2of the memory device a bit A11which is for specifying a state of activation of the mode. The arrangement of information in MR2(or other such mode register) may be set forth in a synchronous DRAM (SDRAM) standard which, for example, is compatible in one or more respects with DDR3, DDR4 or other such standard of the Joint Electron Devices Engineering Council (JEDEC). MRS TRR enable620may further write information—e.g. to bits A8and A2:A0of MR2—to specify a particular bank as being the reference bank for the current instance of the mode. In an alternate embodiment, the reference bank is identified to the memory device by an address associated with another command—e.g. an activate command—which is immediately subsequent to the MRS TRR enable620.

In the illustrative exchange of timing diagram600, such a subsequent command is represented by Act B0TR(n)630, which activates the target row n in reference bank B0. In an embodiment, the memory device detects in response to Act B0TR(n)630that bank B0is the reference bank, and that row n of B0is the row which is being hammered. Act B0TR(n)630may be provided, for example, after a delay tMODwhich is needed for processing any mode register set command.

In an embodiment, MRS TRR enable620, in combination with Act B0TR(n)630, causes the memory device to perform one or more operations in preparation for an expected future targeted row refresh of a victim row which is physically adjacent to row n of reference bank B0. To allow for performance of the one or more operations, some delay may be required between the memory device receiving Act B0TR(n)630and the memory device receiving some next memory access command. Such a delay may, for example, be at least equal to (1.5)(tRAS), where tRAS is a row active time parameter. In an embodiment, tRAS is on the order of 50 nanoseconds (ns) to 70 ns.

The memory device may allow access to any of a plurality of banks at least during a period of time P1from the memory device receiving MRS TRR enable620to the memory device being ready to operate in the configured mode. However, during a period of time P2after preparations to operate in the mode, the memory device may, in an embodiment, restrict access to the reference bank—in this case bank B0—from one or more types of access which do not facilitate a targeted row refresh. In the illustrative exchange of timing diagram600, one such targeted row refresh is represented by a command PRE B0640for precharging B0and a subsequent combination of commands Act B0TR(n−1)650to activate bank B0and to perform a targeted refresh of victim row (n−1) in bank B0. Another such targeted row refresh is represented by a command PRE B0660for precharging B0and a subsequent combination of commands Act B0TR(n+1)670to activate bank B0and to perform a targeted refresh of victim row (n+1) in bank B0.

During period P2, the memory device may support any of a variety of other commands (not shown) each to access a respective bank other than B0, where such access is provided before all targeted row refreshes of victim rows (n−1) and (n+1) have been completed. In an embodiment the memory device may count the number of accesses to bank B0since the current instance of the mode was set. Based on the count, control logic of the memory device may detect that a last victim row has been refreshed and in response, automatically bring the memory device out of the mode—e.g. by writing over information which MRS TRR enable620wrote to a mode register. Bringing the memory device out of the mode may commence a period of time P3—e.g. after another command PRE B0680for precharging B0—during which read access, write access and or other types of access are again supported for bank B0. However, a delay period tMODmay again be required before the memory device can service a command from the memory controller.

FIG. 7is a block diagram of an embodiment of a computing system in which row hammer protection may be implemented. System700represents a computing device in accordance with any embodiment described herein, and may be a laptop computer, a desktop computer, a server, a gaming or entertainment control system, a scanner, copier, printer, or other electronic device. System700may include processor720, which provides processing, operation management, and execution of instructions for system700. Processor720may include any type of microprocessor, central processing unit (CPU), processing core, or other processing hardware to provide processing for system700. Processor720controls the overall operation of system700, and may be or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.

Memory subsystem730represents the main memory of system700, and provides temporary storage for code to be executed by processor720, or data values to be used in executing a routine. Memory subsystem730may include one or more memory devices such as read-only memory (ROM), flash memory, one or more varieties of random access memory (RAM), or other memory devices, or a combination of such devices. Memory subsystem730stores and hosts, among other things, operating system (OS)736to provide a software platform for execution of instructions in system700. Additionally, other instructions738are stored and executed from memory subsystem730to provide the logic and the processing of system700. OS736and instructions738are executed by processor720.

Memory subsystem730may include memory device732where it stores data, instructions, programs, or other items. In one embodiment, memory subsystem includes memory controller734, which is a memory controller in accordance with any embodiment described herein, and which provides row hammer protection mechanisms. In one embodiment, memory controller734provides commands to memory device732each based on a detected row hammer condition. The commands may be for memory device732to perform targeted refreshes for respective potential victim rows.

Processor720and memory subsystem730are coupled to bus/bus system710. Bus710is an abstraction that represents any one or more separate physical buses, communication lines/interfaces, and/or point-to-point connections, connected by appropriate bridges, adapters, and/or controllers. Therefore, bus710may include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (commonly referred to as “Firewire”). The buses of bus710may also correspond to interfaces in network interface750.

System700may also include one or more input/output (I/O) interface(s)740, network interface750, one or more internal mass storage device(s)760, and peripheral interface770coupled to bus710. I/O interface740may include one or more interface components through which a user interacts with system700(e.g., video, audio, and/or alphanumeric interfacing). Network interface750provides system700the ability to communicate with remote devices (e.g., servers, other computing devices) over one or more networks. Network interface750may include an Ethernet adapter, wireless interconnection components, USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces.

Storage760may be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid state, or optical based disks, or a combination. Storage760holds code or instructions and data762in a persistent state (i.e., the value is retained despite interruption of power to system700). Storage760may be generically considered to be a “memory,” although memory730is the executing or operating memory to provide instructions to processor720. Whereas storage760is nonvolatile, memory730may include volatile memory (i.e., the value or state of the data is indeterminate if power is interrupted to system700).

Peripheral interface770may include any hardware interface not specifically mentioned above. Peripherals refer generally to devices that connect dependently to system700. A dependent connection is one where system700provides the software and/or hardware platform on which operation executes, and with which a user interacts.

FIG. 8is a block diagram of an embodiment of a mobile device in which row hammer protections may be implemented. Device800represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wireless-enabled e-reader, or other mobile device. It will be understood that certain of the components are shown generally, and not all components of such a device are shown in device800.

Device800may include processor810, which performs the primary processing operations of device800. Processor810may include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor810include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting device800to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, device800includes audio subsystem820, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions may include speaker and/or headphone output, as well as microphone input. Devices for such functions may be integrated into device800, or connected to device800. In one embodiment, a user interacts with device800by providing audio commands that are received and processed by processor810.

Display subsystem830represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device. Display subsystem830may include display interface832, which may include the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface832includes logic separate from processor810to perform at least some processing related to the display. In one embodiment, display subsystem830includes a touchscreen device that provides both output and input to a user.

I/O controller840represents hardware devices and software components related to interaction with a user. I/O controller840may operate to manage hardware that is part of audio subsystem820and/or display subsystem830. Additionally, I/O controller840illustrates a connection point for additional devices that connect to device800through which a user might interact with the system. For example, devices that may be attached to device800might include microphone devices, speaker or stereo systems, video systems or other display device, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller840may interact with audio subsystem820and/or display subsystem830. For example, input through a microphone or other audio device may provide input or commands for one or more applications or functions of device800. Additionally, audio output may be provided instead of or in addition to display output. In another example, if display subsystem includes a touchscreen, the display device also acts as an input device, which may be at least partially managed by I/O controller840. There may also be additional buttons or switches on device800to provide I/O functions managed by I/O controller840.

In one embodiment, I/O controller840manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, global positioning system (GPS), or other hardware that may be included in device800. The input may be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

In one embodiment, device800includes power management850that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem860may include memory device(s)862for storing information in device800. Memory subsystem860may include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory860may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of system800.

In one embodiment, memory subsystem860includes memory controller864(which could also be considered part of the control of system800, and could potentially be considered part of processor810). Memory controller864monitors for a row hammer condition. For example, memory controller864may monitor the requests to certain memory addresses, and log how many times a specific address is the subject of a request. In an embodiment, memory controller864issues commands for targeted refreshes of potential victim rows of memory862.

Connectivity870may include multiple different types of connectivity. To generalize, device800is illustrated with cellular connectivity872and wireless connectivity874. Cellular connectivity872refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, LTE (long term evolution—also referred to as “4G”), or other cellular service standards. Wireless connectivity874refers to wireless connectivity that is not cellular, and may include personal area networks (such as Bluetooth), local area networks (such as WiFi), and/or wide area networks (such as WiMax), or other wireless communication. Wireless communication refers to transfer of data through the use of modulated electromagnetic radiation through a non-solid medium. Wired communication occurs through a solid communication medium.

Peripheral connections880include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that device800could both be a peripheral device (“to”882) to other computing devices, as well as have peripheral devices (“from”884) connected to it. Device800commonly has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on device800. Additionally, a docking connector may allow device800to connect to certain peripherals that allow device800to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, device800may make peripheral connections880via common or standards-based connectors. Common types may include a Universal Serial Bus (USB) connector (which may include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other type.

In one aspect, a memory device comprises a first bank including a first row and a second row physically adjacent to the first row, a second bank, wherein an integrated circuit chip of the memory device includes the first bank and the second bank and detect logic to configure the memory device for operation in a first mode in response to an indication that repeated access to the first row exceeds a threshold. The memory device further comprises row hammer response logic to operate based on the first mode, including the row hammer response logic to perform, in response to the indication, one or more operations in preparation for a targeted refresh of the second row. The memory device further comprises access logic to service a first command from a memory controller after performance of the one or more operations, including the access logic to access the second bank while the memory device is configured for operation in the first mode, the access logic further to perform the targeted refresh of the second row in response to a second command received by the memory device from the memory controller after the first command.

In an embodiment, the row hammer response logic to perform the one or more operations includes the row hammer response logic to activate logic to restrict an access to the first bank other than an access for a targeted refresh. In another embodiment, the row hammer response logic to perform the one or more operations includes the row hammer response logic to determine address information corresponding to the second row. In another embodiment, the row hammer response logic to determine address information corresponding to the second row includes the row hammer response logic to determine an offset between logical addresses of physically adjacent rows.

In another embodiment, the detect logic is further to maintain a count of a number of accesses to the first bank subsequent to configuration of the memory device to operate in the first mode, the detect logic further to compare the count to a threshold number. In another embodiment, the memory device is to automatically exit the first mode in response to the count exceeding the threshold number. In another embodiment, the memory device further comprises a mode register, wherein the detect logic to configure the first mode includes the detect logic to write to the mode register. In another embodiment, the row hammer response logic is further to signal to the memory controller that repeated access to the first row exceeds the threshold.

In another aspect, a method at a memory device comprises configuring the memory device for operation in a first mode in response to an indication that repeated access to a first row exceeds a threshold. The memory device comprises a first bank including the first row and a second row physically adjacent to the first row, and a second bank, wherein an integrated circuit chip of the memory device includes the first bank and the second bank. The method further comprises, based on the first mode, performing in response to the indication one or more operations in preparation for a targeted refresh of the second row. The method further comprises servicing a first command from a memory controller after performance of the one or more operations, including accessing the second bank while the memory device is configured for operation in the first mode, and performing the targeted refresh of the second row in response to a second command received by the memory device from the memory controller after the first command.

In an embodiment, performing the one or more operations includes activating logic to restrict an access to the first bank other than an access for a targeted refresh. In another embodiment, performing the one or more operations includes determining address information corresponding to the second row. In another embodiment, determining the address information corresponding to the second row includes determining an offset between logical addresses of physically adjacent rows. In another embodiment, the method further comprises maintaining a count of a number of accesses to the first bank subsequent to configuration of the memory device to operate in the first mode, and comparing the count to a threshold number. In another embodiment, the method further comprises automatically exiting the first mode in response to the count exceeding the threshold number. In another embodiment, configuring the memory device for operation in the first mode includes writing to a mode register of the memory device. In another embodiment, the method further comprises signaling the memory controller that repeated access to the first row exceeds the threshold.

In another aspect, a memory controller comprises detect logic to receive an indication that repeated access to a first row of a memory device exceeds a threshold. The memory device comprises a first bank including the first row and a second row physically adjacent to the first row, and a second bank, wherein an integrated circuit chip of the memory device includes the first bank and the second bank. The memory controller further comprises command logic to configure the memory device for operation in a first mode in response to the indication, wherein based on the first mode, the memory device performs one or more operations in preparation for a targeted refresh of the second row. The command logic is further to send a first command, wherein the memory device accesses the second bank to service the first command after performance of the one or more operations and while the memory device is configured for operation in the first mode. The command logic is further to send a second command to the memory device after the first command is sent, wherein the memory device performs the targeted refresh of the second row in response to the second command.

In an embodiment, the indication is based on the memory device identifying the first row as a target of a row hammer event. In another embodiment, the one or more operations restrict an access to the first bank other than an access for a targeted refresh. In another embodiment, the one or more operations determine address information corresponding to the second row. In another embodiment, the command logic to configure the memory device for operation in the first mode includes the command logic to write to a mode register of the memory device. In another embodiment, the command logic is to write to the mode register information identifying the first bank as a reference bank for an instance of the mode.

In another aspect, a method at a memory controller comprises receiving an indication that repeated access to a first row of a memory device exceeds a threshold, wherein the memory device comprises a first bank including the first row and a second row physically adjacent to the first row, and a second bank, wherein an integrated circuit chip of the memory device includes the first bank and the second bank. The method further comprises configuring the memory device for operation in a first mode in response to the indication, wherein based on the first mode, the memory device performs one or more operations in preparation for a targeted refresh of the second row. The method further comprises sending a first command, wherein the memory device accesses the second bank to service the first command after performance of the one or more operations and while the memory device is configured for operation in the first mode. The method further comprises sending a second command to the memory device after the first command is sent, wherein the memory device performs the targeted refresh of the second row in response to the second command.

In an embodiment, the indication is based on the memory device identifying the first row as a target of a row hammer event. In another embodiment, the one or more operations restrict an access to the first bank other than an access for a targeted refresh. In another embodiment, the one or more operations determine address information corresponding to the second row. In another embodiment, configuring the memory device for operation in the first mode includes the memory controller writing to a mode register of the memory device. In another embodiment, the memory controller writes to the mode register information identifying the first bank as a reference bank for an instance of the mode.