Majority voting processing device, semiconductor memory device, and majority voting method for information data

A majority voting processing device performs majority voting on respective bits of information data piece including r-number of bits (r is an integer of 2 or greater). The device includes a memory including a plurality of memory element groups each including r-number of memory elements that store data for the corresponding r-number of bits, respectively, the plurality of memory element groups each being provide for one address. A memory access unit writes each bit of the information data piece in k-number (k is an odd number of 3 or greater) of the memory elements in the memory element group corresponding to one address, and reads out the k-number of bits written in the k-number of the memory elements corresponding to that one address. A majority voter that performs majority voting on the k-number of bits read out from the memory by the memory access unit.

BACKGROUND OF THE INVENTION

Technical Field

Embodiments described herein relate to a majority voting processing device that obtains information data with the highest probability by majority voting, a semiconductor memory device including the majority voting processing device, and a majority voting method for information data.

Background Art

A semiconductor memory in which the reliability of written information data is enhanced by majority voting is known (see Japanese Patent Application Laid-open Publication No. H3-57048 (Patent Document 1), for example).

The semiconductor memory of Patent Document 1 is configured to receive an information data piece to be written therein and to write the same information data piece as that information data piece into three memory cell arrays, each of which has independent 8-bit input/output ports. When the data is to be read out, the semiconductor memory selects one information data piece from the three information data pieces each having 8 bits through majority voting, and outputs the information data piece as output data.

SUMMARY OF THE INVENTION

The semiconductor memory of Patent Document 1 requires three memory cell arrays each having independent input/output ports, which causes a problem of increasing the circuit size of the overall device.

If majority voting is to be conducted on the read-out information data pieces using one memory cell array only, one information data piece needs to be written in three addresses, for example, and in a reading process, the information data is read out from those three addresses consecutively, and those three information data pieces are subjected to majority voting.

Thus, in order to perform majority voting with one memory cell array only, three data latches are required in a stage preceding to the majority voting circuit so that those three information data pieces are held until all three information data pieces are read out from the one memory cell array. The circuit size of each of the data latches increases as the bit number of the information data piece increases, and therefore, the size of the entire device would increase.

An object is to provide a majority voting processing device that can perform majority voting on information data pieces without increasing the device size, a semiconductor memory device, and a majority voting method for information data.

A majority voting processing device of one or more embodiments is a majority voting processing device performing majority voting on respective bits of information data piece including r-number of bits (r is an integer of 2 or greater), including: a memory including a plurality of memory element groups each including r-number of memory elements that store data for the corresponding r-number of bits, respectively, the plurality of memory element groups each being provide for one address; a memory access unit writes each bit of the information data piece in k-number (k is an odd number of 3 or greater) of the memory elements in the memory element group corresponding to one address, and reads out the k-number of bits written in the k-number of the memory elements corresponding to that one address; and a majority voter that performs majority voting on the k-number of bits read out from the memory by the memory access unit.

A semiconductor memory device of one or more embodiments is a semiconductor storage device having a memory cell array including a plurality of memory element groups each including r-number (r is an integer of 2 or greater) of memory cells that store data for respective r-number of bits, the plurality of memory element groups each being provided for one address, the semiconductor storage device, comprising: a memory access unit writes each bit of the information data piece in k-number (k is an odd number of 3 or greater) of the memory cells in the memory element group corresponding to one address, and reads out the k-number of bits written in the k-number of the memory cells corresponding to that one address; and a majority voter that performs majority voting on the k-number of bits read out from the memory cell array by the memory access unit.

A majority voting method of one or more embodiments is a majority voting method of information data in which an information data piece of r-number of bits (r is an integer of 2 or greater) is written in k-number of places (k is an odd number of 3 or greater) in a memory that includes a plurality of memory element groups each including r-number of memory elements that store data for the respective r-number of bits, the plurality of memory element groups each being provided for one address, and majority voting is performed on respective bits of the same bit digit of the k-number of information data pieces read out from the k-number of places for each bit digit, the method including: writing, for each bit of the information data piece, that one bit into k-number of memory elements corresponding to one address; and reading out the k-number of bits written in the k-number of memory elements corresponding to one address at the same time, and performing majority voting on those k-number of bits that are read out.

In an embodiment, the following processes are performed to write an information data piece of r bits in k-number of places in a memory that includes a plurality of memory element groups each including r-number of memory elements that store data for the respective r bits, the memory element group functioning as a unit of an address, and to perform majority voting on the information data piece read out from the k-number of places for each bit.

First, for every bit of the information data piece, that one bit is written into k-number of memory elements corresponding to one address. Thereafter, the k-number of bits written in the k-number of memory elements corresponding to one address are read out, and majority voting is performed on those k-number of bits that are read out.

This way, the respective bits of k-number of read-out data pieces that are subjected to majority voting are read out at the same time for the same bit digit by one read-out access to the single memory, and therefore, majority voting can be performed directly on those k-number of bits that are read out.

As a result, according to one embodiment, data latches in a stage preceding to the majority voter circuit can be eliminated, which makes it possible to perform majority voting on the information data pieces without increasing the device size.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a block diagram showing a schematic configuration of a semiconductor memory device200, which functions as the majority voting processing device of an embodiment. In the present specification and claims, the term “majority voting” refers to a logic circuit in which multiple inputs are received and one output is generated based on the value of the majority of inputs. In embodiments, the multiple inputs may refer to data bits that all correspond to a same address and the majority voting calculation may determine the value to be output when the address is accessed.

The semiconductor memory device200includes a memory cell array101, a control unit102, a row decoder103, a column decoder104, and a data input/output unit105.

The memory cell array101includes bit lines B0to Bm (m is an integer of 2 or greater) and word lines W0to Wn (n is an integer of 2 or greater) arranged to intersect with the bit lines B0to Bm. Furthermore, at each of the intersections of the bit lines B and the word lines W, a memory cell MC connected to one bit line B and one word line W is disposed. In one embodiment, a memory cell MC includes one or more transistors. However, embodiments are not limited only to semiconductor-type transistors, but include any memory device capable of storing a bit of data with a row decoder and column decoder.

Each memory cell MC receives a selection voltage applied via a word line W connected to the memory cell MC and a write-in voltage applied via a bit line B connected to the memory cell MC, and writes a data bit therein in accordance with the selection voltage and the write-in voltage. Also, each memory cell MC applies, to a bit line B connected to the memory cell MC, a current corresponding to the data bit written therein in accordance with the selection voltage applied via a word line W connected to the memory cell MC and the read-out voltage applied via the corresponding bit line B.

The control unit102receives a memory access signal MAC indicating a write-in command, read-out command, and the like, and an address AD from outside the semiconductor memory device200. In addition, the control unit102receives an operation mode signal MOD indicating one of the majority voting mode and the normal mode from outside the semiconductor memory device200.

The control unit102generates a word line selection signal for selecting one of the word lines W0to Wn based on the address AD, and supplies this signal to the row decoder103.

When the memory access signal MAC indicates a read-out command, the control unit102supplies a read-out command signal RC to the data input/output unit105, and when the memory access signal MAC indicates a write-in signal, the control unit102supplies a write-in command signal WC to the data input/output unit105.

Furthermore, the control unit102generates an address SA specifying a plurality of bit lines to be subjected to the write-in access and an address SB specifying a plurality of bit lines B to be subjected to the read-out access, among the bit lines B0to Bm, and supplies those addresses to the column decoder104.

When the operation mode signal MOD indicates the majority voting mode, the control unit102generates the address SA and address SB that gradually change over time in one write-in access or read-out access.

The row decoder103applies a selection voltage to one word line W among the word lines W0to Wn in the memory cell array101, based on the word line selection signal supplied by the control unit102.

The column decoder104selects a plurality of bit lines B specified by the address SA and address SB among the bit lines B0to Bm as a bit line group to be accessed. The number of the plurality of bit lines B selected as the bit line group to be accessed is the same as the number of the data bit lines D0to D20connected to the data input/output unit105, or in other words, 21 lines. The column decoder104connects 21 bit lines B, which are to be accessed among the bit lines B0to Bm, to the data bit lines D0to D20, respectively.

The data input/output unit105receives the operation mode signal MOD and the information data DIN [20:0] made up of the 0-th bit to 20-th bit from outside the semiconductor memory device200as well as the read-out command signal RC and write-in command signal WC from the control unit102. In embodiments, the operation mode signal MOD and the information data DIN [20:0] may be received from a controller, such as a processor chip running instructions to control data input/output operations. The controller may be located in a same device as the semiconductor memory device200or may be received from another computer connected to the semiconductor memory device200.

If the data input/output unit105receives the write-in command signal WC when the operation mode signal MOD indicates the normal mode, the data input/output unit105generates write-in voltages each having a voltage value corresponding to the logic level of each bit of the information data DIN. That is, the data input/output unit105generates the 0-th to 20-th write-in voltages respectively corresponding to the 0-th to 20-th bits of the information data DIN. The data input/output unit105applies the generated 0-th to 20-th write-in voltages to the data bit lines D0to D20, respectively. As a result, the 0-th to 20-th write-in voltages are applied to the 21 bit lines B selected as the access target among the bit lines B0to Bm in the memory cell array101, through the data bit lines D0to D20, respectively.

If the data input/output unit105receives the read-out command signal RC when the operation mode signal MOD indicates the normal mode, the data input/output unit105first applies a read-out voltage to the 21 bit lines B selected as the read-out access target among the bit lines B0to Bm, through the data bit lines D0to D20. The data input/output unit105individually detects the current flowing through each bit line B or the voltage of each bit line B through the data bit lines D0to D20. The data input/output unit105determines whether the logic level of each of the 0-th to 20-th bits, which is the read-out data of each bit, is 1 or 0, based on the detected current or voltage. Thereafter, the data input/output unit105outputs the read-out data DOT [20:0] made up of the 0-th to 20-th bits each having the logic level indicated by the determination results described above.

If the data input/output unit105receives the write-in command signal WC when the operation mode signal MOD indicates the majority voting mode, the data input/output unit105generates write-in voltages each having a voltage value corresponding to the logic level of each bit of the information data DIN. That is, the data input/output unit105generates the 0-th to 20-th write-in voltages respectively corresponding to the 0-th to 20-th bits of the information data DIN. The data input/output unit105divides the 0-th to 20-th write-in voltages into write-in voltage groups each made of three write-in voltages, and selects one write-in voltage from each of the write-in voltage groups. The data input/output unit105applies the write-in voltage selected from each write-in voltage group to three data bit lines D among the data bit lines D0to D20at the same time.

If the data input/output unit105receives the read-out command signal when the operation mode signal MOD indicates the majority voting mode, the data input/output unit105conducts the read-out process described below.

That is, the data input/output unit105first applies a read-out voltage to the 21 bit lines B selected as the read-out access target among the bit lines B0to Bm, through the data bit lines D0to D20. The data input/output unit105individually detects the current flowing through each bit line B or the voltage of each bit line B through the data bit lines D0to D20. The data input/output unit105determines whether the logic level of each of the 0-th to 20-th bits, which is the read-out data of each bit, is 1 or 0, based on the detected current or voltage. Next, the data input/output unit105performs majority voting on three bits, which is the read-out data each read out by the three data bit lines D, and obtains the result as the read-out data for one bit. The data input/output unit105conducts the read-out process every time a plurality of bit lines B as the target of the read-out access change. Through this process, the data input/output unit105outputs the read-out data MDOT[20:0] made up of the 0-th to 20-th bits that were obtained by the majority voting performed for each bit.

FIG. 2is a block diagram showing an example of the internal configuration of the column decoder104and the data input/output unit105to perform the majority voting described above.

The column decoder104and the data input/output unit105have a data conversion unit DCV, an address control unit ACN, and memory access blocks BK0to BK20each corresponding to the data bit lines D0to D20.

FIG. 2illustrates the internal configuration of the memory access blocks BK0to BK2corresponding to the data bit lines D0to D2, respectively, among the memory access blocks BK0to BK20. In the actual configuration, one majority voter MV is provided for three memory access block BK, but inFIG. 2, only one majority voter MV for the memory access blocks BK0to BK2is shown. That is, in the column decoder104and the data input/output unit105, seven majority voters MV, one of which is shown inFIG. 2, are provided for the 21 memory access blocks BK.

As shown inFIG. 2, each memory access block BK has the same internal configuration, or in other words, includes a latch10, selectors30and60, and a sense amplifier70, and the only difference is the data bit line D and the bit line B connected thereto. InFIG. 2, each memory access block BK includes a group of memory cells MC and a group of bit lines B connected to one word line W0in the memory cell array101, in order to illustrate the connection configuration between each memory access block BK and the bit lines B.

In the example ofFIG. 2, 84 memory cells MC0to MC83are connected to one word line W0. The memory cells MC0, MC4, MC8, . . . , MC80of the memory cells MC0to MC83are a group of memory elements corresponding to address [0000] indicated by the address AD, for example. The memory cells MC1, MC5, MC9, . . . , MC81of the memory cells MC0to MC83are a group of memory elements corresponding to address [0001] indicated by the address AD, for example. The memory cells MC2, MC6, MC10, . . . , MC82of the memory cells MC0to MC83are a group of memory elements corresponding to address [0002] indicated by the address AD, for example. The memory cells MC3, MC7, MC11, . . . , MC83of the memory cells MC0to MC83are a group of memory elements corresponding to address [0003] indicated by the address AD, for example.

Below, the operation of the latch10, the selectors30and60, and the sense amplifier70of each of the memory access blocks BK0to BK2will be explained.

The selector30of BK0selects one bit line from the bit lines B0to B3of the memory cell array101based on the bit line select signal a[3:0] supplied from the address control unit ACN, and electrically connects the selected bit line to the data bit line D0. The selector60of BK0selects one bit line from the bit lines B0to B3based on the bit line select signal b[3:0] supplied from the address control unit ACN, and electrically connects the selected bit line to the data bit line LL. The sense amplifier70of BK0detects a current flowing through the data bit line LL or a voltage of the data bit line LL, and identifies whether the logic level of the data bit read out through the data bit line LL is 0 or 1, based on the detected current value or voltage value. The sense amplifier70supplies data bit R0, which is a data bit having the identified logic level, to the latch10and the majority voter MV. The latch10of BK0holds and outputs the data bit R0as a read-out data DOT[0] for the 0-th bit of the read-out data.

The selector30of BK1selects one bit line from the bit lines B4to B7of the memory cell array101based on the bit line select signal a[3:0], and electrically connects the selected bit line to the data bit line D1. The selector60of BK1selects one bit line from the bit lines B4to B7based on the bit line select signal b[3:0], and electrically connects the selected bit line to the data bit line LL. The sense amplifier70of BK1detects a current flowing through the data bit line LL or a voltage of the data bit line LL, and determines whether the logic level of the data bit read out through the data bit line LL is 0 or 1, based on the detected current value or voltage value. The sense amplifier70supplies data bit R1, which is a data bit having the identified logic level, to the latch10and the majority voter MV. The latch10of BK1holds and outputs the data bit R1as a read-out data DOT[1] for the first bit of the read-out data.

The selector30of BK2selects one bit line from the bit lines B8to B11of the memory cell array101based on the bit line select signal a[3:0], and electrically connects the selected bit line to the data bit line D2. The selector60of BK2selects one bit line from the bit lines B8to B11based on the bit line select signal b[3:0], and electrically connects the selected bit line to the data bit line LL. The sense amplifier70of BK2detects a current flowing through the data bit line LL or a voltage of the data bit line LL, and determines whether the logic level of the data bit read out through the data bit line LL is 0 or 1, based on the detected current value or voltage value. The sense amplifier70supplies data bit R2, which is a data bit having the identified logic level, to the latch10and the majority voter MV. The latch10of BK2holds and outputs the data bit R2as a read-out data DOT[2] for the second bit of the read-out data.

The majority voter MV includes a majority voting calculation circuit20and latches10ato10ceach with an enable terminal. The majority voting calculation circuit20performs majority voting on the data bits R0to R2, and generates a data bit RD having the logic level obtained as the result of the majority voting. The majority voting calculation circuit20supplies the data bit RD to the latches10ato10c. In embodiments, the majority voting calculation circuit20may be a logic circuit receiving as inputs the data bits R0to R2, and, based on the value of the inputs R0to R2, generating the output data bit RD according to the value of the majority of the inputs R0to R2. WhileFIG. 2describes data bits R0to R2, embodiments are not limited to only three data bits representing data read out from memory cells. Instead, embodiments encompass any odd number of data bits representing data read out from an odd number of memory cells.

The latch10atakes in the data bit RD when the bit line selection signal b[0] that corresponds to the address [0000], among the bit line selection signal b[3:0], has the logic level of 1, for example, and maintains the logic level of the data bit RD as long as the logic level of the bit line selection signal b[0] is 0. The latch10aoutputs a data bit having the maintained logic level as read-out data MDOT[0] representing the 0-th bit of the read-out data.

The latch10btakes in the data bit RD when the bit line selection signal b[1] that corresponds to the address [0001], among the bit line selection signal b[3:0], has the logic level of 1, for example, and maintains the logic level of the data bit RD as long as the logic level of the bit line selection signal b[1] is 0. The latch10boutputs a data bit having the maintained logic level as read-out data MDOT[1] representing the first bit of the read-out data.

The latch10ctakes in the data bit RD when the bit line selection signal b[2] that corresponds to the address [0002], among the bit line selection signal b[3:0], has the logic level of 1, for example, and maintains the logic level of the data bit RD as long as the logic level of the bit line selection signal b[2] is 0. The latch10coutputs a data bit having the maintained logic level as read-out data MDOT[2] representing the second bit of the read-out data.

The data conversion unit DCV receives the operation mode signal MOD, the write-in command signal WC, the read-out command signal RC, and the information data DIN constituted of the 0th to 20th bits. The data conversion unit DCV converts the respective bits of the information data DIN to write-in voltages each having a voltage value corresponding to the logic level of the bit in accordance with the write-in command signal WC, thereby obtaining the 0th to 20th write-in voltages.

When the operation mode signal MOD indicates the normal mode, the data conversion unit DCV applies the generated 0th to 20th write-in voltages to the data bit lines D0to D20.

On the other hand, when the operation mode signal MOD indicates the majority voting mode, the data conversion unit DCV first divides the 0th to 20th write-in voltages into write-in voltage groups each made of three write-in voltages, and selects one write-in voltage from each of the write-in voltage groups sequentially. Then, the data input/output unit105applies the write-in voltage selected for each write-in voltage group as described above to three data bit lines D among the data bit lines D0to D20at the same time.

The address control unit ACN receives the read-out command signal RC, the write-in command signal QC, the operation mode signal MOD, and addresses SA and SB.

When the operation mode signal MOD indicates the normal mode, the address control unit ACN generates the bit line selection signal a[3:0] in which the logic level of one signal indicated by the address SA is set to 1, and the logic level of the other signals is set to 0. The address control unit ACN also generates the bit line selection signal b[3:0] in which the logic level of one signal indicated by the address SB is set to 1, and the logic level of the other signals is set to 0. When the address control unit ACN receives the write-in command signal WC, the address control unit ACN supplies the bit line selection signal a[3:0] to the selector30of each memory access block BK. When the address control unit ACN receives the read-out command signal RC, the address control unit ACN supplies the bit line selection signal b[3:0] to the selector60of each memory access block BK.

On the other hand, if the operation mode signal MOD indicates the majority voting mode, the address control unit ACN conducts the following processes.

That is, when the address control unit ACN receives the write-in command signal WC, the address control ACN generates the bit line selection signal a[3:0] in which one of the bit line selection signals a[0], a[1], a[2], and a[3] is set to the logic level1in this order. When the address control unit ACN receives the write-in command signal WC, the address control unit ACN supplies the bit line selection signal a[3:0] to the selector30of each memory access block BK. When the address control unit ACN receives the read-out command signal RC, the address control ACN generates the bit line selection signal b[3:0] in which one of the bit line selection signal b[0], b[1], b[2], and b[3] is set to the logic level in this order. The address control unit ACN supplies the bit line selection signal b[3:0] to the selector60of each memory access block BK, and supplies the bit line selection signal b[2:0] to the majority voter MV.

Below, the memory access (writing and reading) operation by the memory access blocks BK0to BK2and the majority voter MV illustrated inFIG. 2will be explained by using the 0th to second bits out of the 0th to 21st bits of the information data DIN to be written as an example. In the descriptions below, the 0th bit of the information data DIN is indicated as bit d0, the first bit is d1, and the second bit is bit d2.

FIG. 3is a time chart showing the operation to write the information data DIN including the bits d0to d2into the memory cells MC0, MC4, and MC8corresponding to the address [0000] indicated by the address AD, and the operation to read the information data DIN from those memory cells.

The data conversion unit DCV generates the 0th to second write-in voltages corresponding to the logic levels of the bits d0to d2of the information data DIN, and supplies the respective voltages to the memory access blocks BK0to BK2via the data bit lines D0to D2. The address control unit ACN supplies, to the selector30of each memory access block BK0to BK2, the bit line selection signal a[3:0] in which the logic level of the bit line selection signal a[0] is set to 1, and the logic level of a[1] to a[2] is set to 0 based on the address SA.

This way, the bit d0of the information data DIN is written in the memory cell MC0, the bit d1is written in the memory cell MC4, and the bit d2is written in the memory cell MC8.

Thereafter, in accordance with the read-out command signal RC of the logic level1, the address control unit ACN supplies, to the selector60of each memory access block BK0to BK2, the bit line selection signal b[3:0] in which the logic level of the bit line selection signal b[0] is set to 1, and the logic level of b[1] to b[3] is set to 0 based on the address SB.

This way, the data bit R0representing the bit d0is read out from the memory cell MC0, and this data bit R0is output as the read-out data DOT[0]. The data bit R1representing the bit d1is read out from the memory cell MC4, and this data bit R0is output as the read-out data DOT[1]. Furthermore, the data bit R2representing the bit d2is read out from the memory cell MC8, and this data bit R0is output as the read-out data DOT[2].

As described above, in the normal mode, the bits d0to d2in the information data DIN are written in the three memory cells (MC0, MC4, and MC11) corresponding to the address [0000], respectively, via the data bit lines D0to D2, in accordance with the write-in command signal WC. Those bits d0to d2are read out from the three memory cells in accordance with the read-out command signal RC, and output as the read-out data DOT[0] to DOT[2], respectively.

Thus, in the normal mode, the data input/output unit105outputs the read-out data DOT [20:0] including the read-out data DOT[0] to DOT [2] as the official read-out data.

FIG. 4is a time chart showing the operation to write the information data DIN including the bits d0to d2into the memory cell group connected to the word line W0, and the operation to read the information data DIN from the memory cell group when the operation mode signal MOD indicates the majority voting mode.

First, as shown inFIG. 4, the control unit102supplies the write-in command signal WC having the successive pulse strings of the logic level1to the address control unit ACN and the data conversion unit DCV.

The data conversion unit DCV takes in the information data DIN including the bits d0to d2, one bit at a time, at the same timing as the timing of each pulse of the write-in command signal WC as shown inFIG. 4.

First, the data conversion unit DCV generates the 0th write-in voltage corresponding to the logic level of the bit d0of the information data DIN, and supplies the voltage to the respective memory access blocks BK0to BK2via the data bit lines D0to D2at the same time. Thereafter, in accordance with the first part with the logic level1of the write-in command signal WC, the address control unit ACN supplies, to the selector30of each memory access block BK0to BK2, the bit line selection signal a[3:0] in which the logic level of the bit line selection signal a[0], which corresponds to the address [0000], is set to 1, and the logic level of a[1] to a[3] is set to 0 as shown inFIG. 4.

This way, the bit d0of the information data DIN is written in the memory cells MC0, MC4, and MC8corresponding to the address [0000].

Next, the data conversion unit DCV generates the first write-in voltage corresponding to the logic level of the bit d1of the information data DIN, and supplies the voltage to the respective memory access blocks BK0to BK2via the data bit lines D0to D2at the same time. Thereafter, in accordance with the second part with the logic level1of the write-in command signal WC, the address control unit ACN supplies, to the selector30of each memory access block BK0to BK2, the bit line selection signal a[3:0] in which the logic level of the bit line selection signal a[1], which corresponds to the address [0001], is set to 1, and the logic level of a[0], a[2], and a[3] are set to 0 as shown inFIG. 4.

This way, the bit d1of the information data DIN is written in the memory cells MC1, MC5, and MC9corresponding to the address [0001].

Next, the data conversion unit DCV generates the second write-in voltage corresponding to the logic level of the bit d2of the information data DIN, and supplies the voltage to the respective memory access blocks BK0to BK2via the data bit lines D0to D2at the same time. Thereafter, in accordance with the third part with the logic level1of the write-in command signal WC, the address control unit ACN supplies, to the selector30of each memory access block BK0to BK2, the bit line selection signal a[3:0] in which the logic level of the bit line selection signal a[2], which corresponds to the address [0002], is set to 1, and the logic level of a[0], a[1], and a[3] is set to 0 as shown inFIG. 4.

This way, the bit d2of the information data DIN is written in the memory cells MC2, MC6, and MC10corresponding to the address [0002].

Thereafter, as shown inFIG. 4, the control unit102supplies the read-out command signal RC having the successive pulse strings of the logic level1to the address control unit ACN and the data conversion unit DCV.

In accordance with the first part with the logic level1of the read-out command signal RC, the address control unit ACN supplies, to the selector60of each memory access block BK0to BK2, the bit line selection signal b[3:0] in which the logic level of the bit line selection signal b[0], which corresponds to the address [0000], is set to 1, and the logic level of b[1] to b[3] is set to 0 as shown inFIG. 4.

This way, the data bits R0, R1, and R2, which all represent the bit d0, are read out from the respective memory cells MC0, MC4, and MC8that correspond to the address [0000]. The majority voting calculation circuit20of the majority voter MV performs majority voting on the logic levels of the data bits R0, R1, and R2, and supplies the result to the latches10ato10cas the data bit RD representing the bit d0. In this case, only the latch10a, of the latches10ato10c, takes in the data bit RD representing the bit d0in accordance with the bit line selection signal b[0] of the logic level1, and outputs this data as the read-out data MDOT[0] representing the 0th bit of the read-out data.

Next, in accordance with the second part with the logic level1of the read-out command signal RC, the address control unit ACN supplies, to the selector60of each memory access block BK0to BK2, the bit line selection signal b[3:0] in which the logic level of the bit line selection signal b[1], which corresponds to the address [0001], is set to 1, and the logic level of b[0], b[2], and b[3] are set to 0 as shown inFIG. 4.

This way, the data bits R0, R1, and R2, which all represent the bit d1, are read out from the respective memory cells MC1, MC5, and MC9that correspond to the address [0001]. The majority voting calculation circuit20performs majority voting on the logic levels of the data bits R0, R1, and R2, and supplies the result to the latches10ato10cas the data bit RD representing the bit d1. In this case, only the latch10b, of the latches10ato10c, takes in the data bit RD representing the bit d1in accordance with the bit line selection signal b[1] of the logic level1, and outputs this data as the read-out data MDOT[1] representing the first bit of the read-out data.

Next, in accordance with the third part with the logic level1of the read-out command signal RC, the address control unit ACN supplies, to the selector60of each memory access block BK0to BK2, the bit line selection signal b[3:0] in which the logic level of the bit line selection signal b[2], which corresponds to the address [0002], is set to 1, and the logic level of b[0], b[1], and b[3] is set to 0 as shown inFIG. 4.

This way, the data bits R0, R1, and R2, which all represent the bit d2, are read out from the respective memory cells MC2, MC6, and MC10that correspond to the address [0002]. The majority voting calculation circuit20performs majority voting on the logic levels of the data bits R0, R1, and R2, and supplies the result to the latches10ato10cas the data bit RD representing the bit d2. In this case, only the latch10c, of the latches10ato10c, takes in the data bit RD representing the bit d2in accordance with the bit line selection signal b[2] of the logic level1, and outputs this data as the read-out data MDOT[2] representing the second bit of the read-out data.

That is, in the majority voting mode, the read-out data MDOT[20:0] including the read-out data MDOT[0] to MDOT[2] described above is output as the official read-out data.

In the configuration illustrated inFIG. 2where the memory cell array101including a plurality of storage element groups each made up of 21 memory cells MC that correspond to 21 bits, respectively, and each corresponding to one address (AD) is used, the majority voting process is performed on information data pieces as follows.

First, for every bit of the information data DIN, that one bit is written into three memory cells MC corresponding to one address. Then, those three bits written in the three memory cells MC corresponding to one address is read out as the data bits R0to R2, and the majority voting is performed on the read-out three data bits R0to R2.

This way, the respective bits of three pieces of information data to be subjected to the majority voting are read out at the same time for the same bit digit through one access to the single memory cell array101. Thus, the majority voting calculation circuit20can directly perform the majority voting on the read-out three bits.

This makes it possible to eliminate the need to provide data latches in a stage preceding the majority voting calculation circuit20, which is required when the information data pieces that are subjected to the majority voting are written in k-number of different addresses, and those information data pieces are read out successively from the respective addresses through k-number of accesses. As a result, with the configuration illustrated inFIG. 2, it is possible to perform majority voting on the information data pieces without increasing the device size.

FIG. 5is a block diagram showing another example of the internal configuration of the column decoder104and the data input/output unit105.

The configuration ofFIG. 5is the same as that ofFIG. 2except that the data conversion unit DCV is replaced with a data conversion unit DCVa, and dual-input selectors S0to S3are additionally provided in each memory access block BK.FIG. 5does not show the internal configuration of the majority voter MV or the address control unit ACN.

Below, the configuration illustrated inFIG. 5will be explained, mainly focusing on the data conversion unit DCVa and the dual-input selectors S0to S3.

When the data conversion unit DCVa receives the information data DIN made up of the 0th to 20th bits, the data conversion unit DCVa generates the 0th to 20th write-in voltages V0to V20each having a voltage value corresponding to the logic level of each of the 0th to 20th bits.

When the operation mode signal MOD indicates the normal mode, the data conversion unit DCVa supplies the generated write-in voltages V0to V20to the corresponding memory access blocks BK via the data bit lines D0to D20, respectively.

On the other hand, when the operation mode signal MOD indicates the majority voting mode, the data conversion unit DCVa divides the write-in voltages V0to V20into write-in voltage groups each including three write-in voltages, and supplies each write-in voltage group to three memory cell blocks BK. For example, the data conversion unit DCVa supplies the write-in voltage group including the write-in voltages V0to V2, out of the write-in voltages V0to V20, respectively to the three memory cell blocks BK0to BK2illustrated inFIG. 5.

The respective dual-input selectors S0to S3in each memory cell block BK are supplied with the operation mode signal MOD. The duel-input selectors S0to S3are respectively connected to the corresponding bit lines B. Furthermore, out of the two input terminals of each of the dual-input selectors S0to S3, one input terminal is applied with one write-in voltage included in the write-in voltage group, and the other input terminal is connected to the selector30.

When the operation mode signal MOD indicates the normal mode, each of the dual-input selectors S0to S3connects the bit line B connected thereto and the selector30. This makes each memory cell block BK illustrated inFIG. 5have the circuit configuration equivalent to each memory cell block illustrated inFIG. 2.

On the other hand, when the operation mode signal MOD indicates the majority voting mode, each of the dual-input selectors S0to S3applies the received write-in voltage to the corresponding memory cell MC via the corresponding bit line B connected thereto, without going through the selector30. As a result, different write-in voltages are applied to the plurality of memory cells MC provided for the respective bits of the information data DIN at the same time.

FIG. 6is a time chart showing the operation to write the information data DIN including the bits d0to d2into the memory cell group connected to the word line W0, and the operation to read the information data DIN from the memory cell group in the majority voting mode.

First, as shown inFIG. 6, the control unit102supplies the write-in command signal WC of the logic level1to the address control unit ACN and the data conversion unit DCVa.

In accordance with the write-in command signal WC, the data conversion unit DCVa supplies the write-in voltages V0to V2corresponding to the bits d0to d2of the information data DIN to the memory cell blocks BK0to BK2, respectively.

The dual-input selectors S0to S2of the memory cell block BK0apply the write-in voltages V0to V2to the memory cells MC0to MC2via the bit lines B0to B2. This way, as illustrated inFIG. 6, the bit d0of the information data DIN is written in the memory cell MC0, the bit d1is written in the memory cell MC1, and the bit d2is written in the memory cell MC2.

The dual-input selectors S0to S2of the memory cell block BK1apply the write-in voltages V0to V2to the memory cells MC4to MC6via the bit lines B4to B6. This way, as illustrated inFIG. 6, the bit d0of the information data DIN is written in the memory cell MC4, the bit d1is written in the memory cell MC5, and the bit d2is written in the memory cell MC6.

The dual-input selectors S0to S2of the memory cell block BK2apply the write-in voltages V0to V2to the memory cells MC8to MC10via the bit lines B8to B10. This way, as illustrated inFIG. 6, the bit d0of the information data DIN is written in the memory cell MC8, the bit d1is written in the memory cell M9, and the bit d2is written in the memory cell MC10.

Thereafter, as shown inFIG. 6, the control unit102supplies the read-out command signal RC having the successive pulse strings of the logic level1to the address control unit ACN and the data conversion unit DCVa.

In accordance with the first part with the logic level1of the read-out command signal RC, the address control unit ACN supplies, to the selector60of each memory access block BK0to BK2, the bit line selection signal b[3:0] in which the logic level of the bit line selection signal b[0], which corresponds to the address [0000], is set to 1, and the logic level of b[1] to b[3] are set to 0 as shown inFIG. 6.

This way, the data bits R0, R1, and R2, which all represent the bit d0, are read out from the respective memory cells MC0, MC4, and MC8that correspond to the address [0000] as illustrated inFIG. 6. The majority voting calculation circuit20of the majority voter MV performs majority voting on the logic levels of the data bits R0to R2, and supplies the result to the latches10ato10cas the data bit RD representing the bit d0. In this case, only the latch10a, of the latches10ato10c, takes in the data bit RD representing the bit d0in accordance with the bit line selection signal b[0] of the logic level1, and outputs this data as the read-out data MDOT[0] representing the 0th bit of the read-out data.

Next, in accordance with the second part with the logic level1of the read-out command signal RC, the address control unit ACN supplies, to the selector60of each memory access block BK0to BK2, the bit line selection signal b[3:0] in which the logic level of the bit line selection signal b[1], which corresponds to the address [0001], is set to 1, and the logic level of b[0], b[2], and b[3] is set to 0 as shown inFIG. 6.

This way, the data bits R0, R1, and R2, which all represent the bit d1, are read out from the respective memory cells MC1, MC5, and MC9that correspond to the address [0001] as illustrated inFIG. 6. The majority voting calculation circuit20performs majority voting on the logic levels of the data bits R0, R1, and R2, and supplies the result to the latches10ato10cas the data bit RD representing the bit d1. In this case, only the latch10b, of the latches10ato10c, takes in the data bit RD representing the bit d1in accordance with the bit line selection signal b[1] of the logic level1, and outputs this data as the read-out data MDOT[1] representing the first bit of the read-out data.

Next, in accordance with the third part with the logic level1of the read-out command signal RC, the address control unit ACN supplies, to the selector60of each memory access block BK0to BK2, the bit line selection signal b[3:0] in which the logic level of the bit line selection signal b[2], which corresponds to the address [0002], is set to 1, and the logic level of b[0], b[1], and b[3] is set to 0 as shown inFIG. 6.

This way, the data bits R0, R1, and R2, which all represent the bit d2, are read out from the respective memory cells MC2, MC6, and MC10that correspond to the address [0002] as illustrated inFIG. 6. The majority voting calculation circuit20performs majority voting on the logic levels of the data bits R0, R1, and R2, and supplies the result to the latches10ato10cas the data bit RD representing the bit d2. In this case, only the latch10c, of the latches10ato10c, takes in the data bit RD representing the bit d2in accordance with the bit line selection signal b[2] of the logic level1, and outputs this data as the read-out data MDOT[2] representing the second bit of the read-out data.

With the configuration ofFIG. 5, in a manner similar to the configuration ofFIG. 2, the respective bits of the three read-out data pieces that are subjected to the majority voting can be read out, as the data bits R0to R2, by one read-out access at the same time for the same bit digit in the majority voting mode. This eliminates the need to provide three data latches, which are configured to hold respective read-out data pieces until all three read-out data pieces are obtained, in the stage preceding to the majority voting calculation circuit20that performs majority voting.

As a result, with the configuration ofFIG. 5as well, the overall size of the device can be reduced as in the configuration ofFIG. 2.

Furthermore, with the configuration ofFIG. 5, when the information data DIN is to be written in the majority voting mode, the respective bits of the information data can be written in the memory cell array101at the same time in a manner similar to the data writing in the normal mode. Thus, the data can be written more rapidly and easily as compared to the case in which the respective bits of the information data DIN are written in a certain order in the time-division manner as inFIG. 4.

In the respective embodiments described above, the bit number of the information data DIN that is subjected to the majority voting was 21 bits, but it is not limited thereto. The majority voting calculation circuit20performs majority voting on the three data bits R0to R2, but the majority voting may be performed on any odd-number data bits equal to or greater than 3 according to embodiments.

That is, the majority voting processing device of one embodiment a memory (such as a solid-state memory device or memory portion of a semiconductor chip), a memory access unit, and a majority voter as described above to perform majority voting on the respective bits of the information data piece made up of r-number of bits (r is an integer of 2 or greater).

The memory (101) includes a plurality of memory element groups each made up of r-number of memory elements that store data for the corresponding r-number of bits, respectively, the plurality of memory element groups each being provided for one address. The memory access unit (BK0to BK20, ACN, and DCV) writes each bit of the information data piece (DIN) in k-number (k is an odd number of 3 or greater) of memory elements in the memory element group corresponding to one address, and reads out the k-number of bits written in the k-number of memory elements corresponding to one address. The majority voter (MV) performs majority voting on the k-number of bits read out from the memory by the memory access unit.