Method of forming vias for multilevel metallization

A method is provided for forming a via for multilevel metallization of an integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed over the integrated circuit. A first dielectric layer is then, formed over the first conductive layer. A second dielectric layer over the first dielectric layer and a second conductive layer is formed over the second dielectric layer. A photoresist layer is formed and patterned over the second conductive layer to expose a portion of the second conductive layer. The second conductive layer is etched to form an opening exposing a portion of the second dielectric layer. The second dielectric layer is then etched in the opening to form partially sloped sidewalls sloping outward at an upper surface of the dielectric layer. The photoresist layer is removed. The remaining second dielectric layer and the first electric layer is then anisotropically etched in the opening exposing the portion of the first conductive layer in the opening. The second conductive layer is then removed. A third conductive layer is deposited over the second dielectric layer and in the opening.

FIELD OF THE INVENTION 
The present invention relates generally to semiconductor integrated circuit 
processing, and more specifically to forming vias for multilevel 
metallization. 
BACKGROUND OF THE INVENTION 
In semiconductor circuits, interconnect layers or multilevel metallization 
is necessary for the proper operation of the various devices fabricated. 
Interconnect signal lines make contact with lower conductive layers in the 
integrated circuit through vias in an insulating layer. For best operation 
of the devices, the lower conductive layer cannot be damaged during 
formation of the contact vias. 
Various interlevel insulating layers are deposited on the integrated 
circuit during formation of the devices. These layers separate the 
conductive layers from each other. One method to form contact vias through 
these insulating layers utilizes a photoresist layer to define the via 
locations. An anisotropic etch is then performed to open the vias. Due to 
the increased topography of submicron devices, the thicknesses of the 
interlevel insulating layers are significantly different in various 
regions of the die. The differences in thicknesses requires prolonged 
etching of the insulating layers to insure good electrical contact in all 
of the vias. During the prolonged anisotropic etch, however, the etch 
chemistry causes a chemical reaction to take place between the 
photoresist, the interlevel insulating layers and the lower conductive 
layer. Typically, during the etch process, polymers are created which 
adhere to the sidewalls of the via. 
As known in the prior art, the polymers are removed or dissolved through 
the use of a solvent, acid or plasma etch. Due to the submicron dimensions 
of the vias and the restriction on use of caustic chemicals, the removal 
of these polymers poses a formidable task. Retaining any of the polymer 
build up causes difficulties in achieving high standards of reliability of 
the devices. Removal of all of the polymeric material, however, may result 
in a substantial amount of the underlying conductive layer to be removed. 
Additionally, the acid or plasma etch can remove some of the insulating 
layer, which enlarges the size of the via. 
Therefore, it would be desirable to provide a technique for forming contact 
vias in integrated circuits which prevents the formation of such polymeric 
films. 
SUMMARY OF THE INVENTION 
The invention may be incorporated into a method for forming a semiconductor 
device structure, and the semiconductor device structure formed thereby, 
by forming an opening in a dielectric layer exposing a portion of an 
underlying first conductive layer wherein the dielectric has partially 
sloped sidewalls sloping outward at an upper surface of the dielectric 
layer. A second conductive layer is then formed over the dielectric layer 
and in the opening.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The process steps and structures described below do not form a complete 
process flow for manufacturing integrated circuits. The present invention 
can be practiced in conjunction with integrated circuit fabrication 
techniques currently used in the art, and only so much of the commonly 
practiced process steps are included as are necessary for an understanding 
of the present invention. The figures representing cross-sections of 
portions of an integrated circuit during fabrication are not drawn to 
scale, but instead are drawn so as to illustrate the important features of 
the invention. 
Referring to FIG. 1, an integrated circuit device is to be formed on a 
silicon substrate 10. Transistor gate electrodes 12 are formed over the 
substrate 10 as is well known in the art. Gate electrodes 12 are formed 
over a gate oxide layer 14. Sidewall oxide spacers 16 are formed along the 
sidewalls of the gate electrodes 12 and gate oxide 14. A planarizing 
dielectric layer 18 is formed over the integrated circuit, preferably 
borophosphorous silicate glass (BPSG). 
A first opening 19 is made through the planarizing layer 18 to expose a 
portion of the underlying substrate 10. A first conductive layer 20 is 
formed over the planarizing layer 18 and in the opening 19. Layer 20 is 
typically patterned and etched to form an interconnect contacting an 
underlying active region at the bottom of opening 19. The first conductive 
layer 20 typically has a thickness of between approximately 3000 to 15,000 
angstroms. Layer 20 is preferably a refractory metal such as titanium, 
titanium nitride or an aluminum/silicon/copper alloy or any suitable 
refractory metal used in the art. A conformal first interlevel dielectric 
layer 22, such as plasma oxide, is formed over the first conductive layer 
20 and the planarizing dielectric layer 18. Layer 22 will typically have a 
thickness of between approximately 3000 to 5000 angstroms. 
Planarization of the integrated circuit is important for future device 
fabrication. A planarizing layer 24, such as a spin-on-glass, may formed 
over the first dielectric layer 22 and etched back to form a planarized 
layer. Deposition and patterning of the various layers may be varied to be 
made consistent with process flows for the devices being fabricated. 
Device fabrication up to this stage utilizes conventional process steps 
well known in the art. 
A second dielectric layer 26, such as oxide, is formed over the first 
dielectric layer 22. Layer 26 typically has a thickness of between 5000 to 
7000 angstroms. The depth of layers 22 and 26 must be sufficient enough 
that when etching these layers in subsequent steps, a via of the proper 
shape is formed. 
A second conductive layer 28 is deposited over the dielectric layer 26. 
Layer 28 will typically have a thickness of between approximately 300 to 
1000 angstroms. Layer 28 is again preferably a refractory metal such as 
titanium, titanium nitride or an aluminum/silicon/copper alloy or any 
suitable metal used in the art. A photoresist layer 30 is formed over 
conductive layer 28. Photoresist layer 30 is patterned to form an opening 
32. 
Referring to FIG. 2, the second conductive layer 28 is selectively etched 
using the dielectric layer 26 as an etch stop. Dielectric layer 26 is then 
isotropically etched to form partially sloped sidewalls at an upper 
portion of the sidewalls. The isotropic etch may be a wet or dry etch 
which forms an opening or via 34 in layer 26. The etch process is a timed 
etch and therefore only part of layer 26 may be etched away in via 34. 
Alternatively, all of layer 26 in via 34 may be etched away and part of 
layer 22 may also be etched away in via 34, depending upon the length of 
time of the etch. 
Referring to FIG. 3, photoresist layer 30 is removed. The first dielectric 
layer 22 and any remaining portion of layer 26 is then anisotropically 
etched to form an opening or via 36 exposing the first conductive layer 20 
in the opening. The anisotropic etch is typically a dry etch process. With 
the photoresist removed, there can be no chemical reaction between the 
photoresist, the oxide layers and tile underlying metal layer during the 
etching process of the oxide layers. No complex chemical compounds, such 
as polymers, will build up along the sidewalls of the oxide layers 22, 26. 
There is no need to remove any such compounds, thus simplifying the 
process. 
Referring to FIG. 4, the second conductive layer 28 is then etched away. 
During this etch, a portion of the first conductive layer 20 may also be 
etched away. A third conductive layer 38 is then deposited over the second 
dielectric layer 26 and in the opening 32 to contact to the lower first 
conductive layer 20. Layer 38 typically has a thickness of between 
approximately 8000 to 20,000 angstroms and is preferably a refractory 
metal or an alloy such as those identified above. If layer 28 is not 
removed, it becomes an integral part of the upper conductive layer 38. 
However, there may be step coverage problems under layer 28 where the 
sidewalls of oxide layer 26 slope outward from the via. 
One advantage of the present invention, is that in forming layer 28 before 
the via is etched in the oxide layers, an opening can first be etched 
through layer 28 using the underlying oxide layer 26 as an etch stop. Once 
the photoresist layer 30 is removed, the etch chemistry cannot cause a 
chemical reaction between the composition of the photoresist chemicals and 
the underlying oxide and metal layers. Etching the via exposing the 
underlying metal layer 20 can be performed without the inherent problem of 
such a chemical reaction resulting in unwanted chemical compounds which 
then have to be removed. 
As will be appreciated by those skilled in the art, the process steps 
described above can be used with nearly any conventional process flow. 
While the invention has been particularly shown and described with 
reference to a preferred embodiment, it will be understood by those 
skilled in the art that various changes in form and detail may be made 
therein without departing from the spirit and scope of the invention.