Inter-set wear-leveling for caches with limited write endurance

A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N−1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N−1 memory location swap operations, and resets every (N2−N) memory location swap operations. The first and second registers track a relationship between logical locations and physical locations of the cache sets.

TECHNICAL FIELD

The present disclosure generally relates to memories and caches. More specifically, the present disclosure relates to inter-set wear-leveling for caches with limited write endurance.

BACKGROUND

For high-speed digital electronics that may be used for wireless communications or other application, non-volatile memories are used. Non-volatile memories, such as resistive random access memory (ReRAM) and phase-change random access memory (PCRAM), however, have limited write endurance. Write endurance can be defined as the number of program/cycles that can be applied to a block of memory before the storage media becomes unreliable, and is usually calculated by estimating how often and how thoroughly the memory is used. In other words, write endurance measures the service life of a certain type of storage media.

Wear-leveling is a technique that is used to prolong the write endurance (e.g., service life) of storage media, and is part of cache design. One wear-leveling approach arranges data so that re-writes are evenly distributed across the storage medium. In this way, no single block fails due to a high concentration of write cycles. Other approaches to wear-leveling may include dynamically updating a map every time a write occurs, the map subsequently linking the written block to a new block. Another approach statically keeps the blocks the same without replacing them, but periodically rotates the blocks so they may be used by other data.

Wear-leveling for non-volatile memories (e.g., which may also be used in the main memories for computers) is well known and well explored. Nevertheless, when using wear-leveling for on-chip caches, traditional wear-leveling approaches that are usually employed for non-volatile memories exhibit too much performance overhead. Therefore, the high performance overhead inhibits the effectiveness of year-leveling techniques for caches having limited write endurance.

SUMMARY

According to one aspect of the present disclosure, a cache controller to inter-set wear-level a cache memory is described. The cache controller includes a first register that updates after each memory location swap operation on cache sets of the cache memory, and resets at each N−1 memory location swap operations. N is a number of cache sets in the cache memory. The cache controller further includes a second register that updates after every N−1 memory location swap operations on the cache sets of the cache memory, and resets every (N2−N) memory location swap operations. The first register and the second register may track a relationship between logical locations and physical locations of the cache sets.

According another aspect of the present disclosure, a method for inter-set wear-leveling a cache memory is described. The method includes dynamically rotating cache sets of the cache memory by performing memory location swap operations on the cache sets when a number of memory write operations to the cache memory reaches a threshold value. Each swap operation may include clearing the contents from only the swapped cache sets, while leaving memory contents of other cache sets intact. The method also includes tracking the swapped cache sets to convert a logical cache set number to a physical cache set number.

According to a further aspect of the present disclosure, a cache controller to inter-set wear-level a cache memory is described. The cache controller includes a means for dynamically rotating cache sets of the cache memory by performing memory location swap operations on the cache sets when a number of memory write operations to the cache memory reaches a threshold value. Each swap operation may include clearing the contents from only the swapped cache sets, while leaving memory contents of other cache sets intact. The cache controller further includes a means for tracking the swapped cache sets to convert a logical cache set number to a physical cache set number.

According another aspect of the present disclosure, a method for inter-set wear-leveling a cache memory is described. The method includes the step of dynamically rotating cache sets of the cache memory by performing memory location swap operations on the cache sets when a number of memory write operations to the cache memory reaches a threshold value. Each swap operation may include clearing the contents from only the swapped cache sets, while leaving memory contents of other cache sets intact. The method also includes the step of tracking the swapped cache sets to convert a logical cache set number to a physical cache set number.

DETAILED DESCRIPTION

Memories such as static random access (SRAM) and embedded dynamic RAM (eDRAM) are commonly used for on-chip cache design in modern microprocessors. Modern computers and devices also specify larger on-chip caches, but the scalability of traditional SRAM or eDRAM caches is increasingly constrained by technology limitations such as leakage power and cell density. Recently, new non-volatile memory (NVM) technologies such as, for example, phase-change random access memory (RAM) spin-torque transfer RAM, and resistive RAM have been explored as promising alternative memory technologies to be used for on-chip caches. Compared to traditional memories such as SRAM and eDRAM, these emerging non-volatile memory technologies have common advantages of high density, low standby power, low voltage, better scalability and non-volatility. However, their adoption is hampered by their limited write endurance. This problem will be amplified by the existing cache management policies resulting in unbalanced write traffic on cache blocks because such policies are not write variation aware. These policies were originally designed for SRAM caches and result in significant non-uniformity in terms of writing to cache blocks, which causes heavily-written cache blocks to fail much faster or earlier than most other blocks.

Many wear-leveling techniques have been proposed to extend the lifetime of non-volatile memory technologies, but the difference between cache and main memory operational mechanisms make the existing wear-leveling techniques for non-volatile memories inadequate for non-volatile caches. To address these issues and to reduce inter-set write variations, a swap-shift scheme is provided to reduce cache inter-set write variations for non-volatile memory caches. The scheme has a very small hardware overhead, only using one global counter and two global registers. By adopting this scheme, the lifetime of low-level on-chip non-volatile memory caches can be improved.

Write variation is a significant concern in designing any cache or memory subsystem that use non-volatile memories with limited write endurance. Large write variation may greatly degrade product lifetime, because only a small subset of memory cells that experience the worst-case write traffic can result in a dead cache or memory subsystem even when the majority of the cells are far from wear-out.

FIG. 1is a diagram of an example cache memory100including a cache controller140for inter-set wear-leveling of the cache memory100according to an aspect of the present disclosure. A cache memory100includes a page number102, a set number104, a byte number106, a cache way108, a tag portion110, a data portion112, a cache block114, cache sets116, a tag sense amplifier118a, a data sense amplifier118b, a tag output120, a comparator122, a logic gate124, a cache group126, a select circuitry128and a word output130.

An address in the cache memory100may include a page number102, a set number104and a byte number106. In one implementation, the page number102may be a virtual page number. The set number104corresponds to one of the cache sets116. A cache block114includes a tag portion110and a data portion112. The tag portion110may contain part of the address of the actual data in the data portion112, or other identifying information to locate the data in the data portion112. The data portion112contains the actual data. The one of the cache sets116is one set of cache blocks114, as can be seen by the horizontal grouping inFIG. 1. The cache way108is another group of cache blocks114, but in a vertical grouping, as can be seen inFIG. 1. The tag sense amplifier118aand data sense amplifier118bsense logic levels from the cache entries so the data is properly interpreted (as a 1 or 0) when output.

The data at the tag output120, which is the output of the tag sense amplifier118a, may contain a page frame number, a valid bit and coherence bits. The data from the tag output120is then compared to the page number102by the comparator122, which sees if the two values are equal. If the values are equal and there is a hit, then the output of the comparator122is input, along with the output of the data sense amplifier118b, into the logic gate124. The output of the logic gate124appears in the cache group126. In one implementation, one of the cache groups126contains multiple words. The cache group126is input into a select circuitry128which uses the byte number106as a select input. The output of the select circuitry128using the byte number106as the select input is the word output130.

FIG. 1is also an example block diagram for an n-way set-associative cache, and there may be other types of caches used for the present disclosure. A set-associative cache can be made of several direct-mapped caches operated in parallel (for example, one direct-mapped cache could be a cache entry including the tag portion110and the data portion112). The data read-out may be controlled by a tag comparison with the page number102as well as the block-valid bit (which can be part of the tag or metadata entry) and the page permissions (part of the page number102). The cache column size may also equal the virtual memory page size, and the cache index may not use pits from the page number102or virtual page number.

Individual ones of the cache blocks114are grouped into one of the cache sets116in one direction, and into a cache way108in another direction. The cache blocks114may also have load distributions, depending on how often they are written to. Some of the cache blocks114are heavily written to and others of the cache blocks114are rarely written. Therefore, this causes inter-set write variation. Inter-set write variation occurs among the cache sets116that vary in terms of writing activity. That is, the cache blocks114from one of the cache sets116may be written more or less than the cache blocks114from another of the cache sets116. Furthermore, when different cache sets116are written to as a whole compared to others of the cache sets116, inter-set write variation also occurs.

In this configuration, the cache controller140evenly distributes writing traffic to the different rows and to the different columns for the cache ways108. Although the cache ways108are shown as occupying columns and the cache sets116are shown as occupying rows inFIG. 1, the implementation of the cache memory100is not limited to this configuration. In particular, the cache ways108may occupy rows or other structures that may not be columns within the cache memory100, and the cache sets116may occupy columns or other structures that may not be rows within the cache memory100.

Main memory wear-leveling techniques usually use data movement to implement the address re-mapping. This is because in main memory, the data cannot be lost and can be moved to a new position after each re-mapping. Nevertheless, data movement operations always incur area and performance overhead. First, data movement needs a temporary data storage location to receive the data. Second, one cache set movement involves several block read and write operations. Therefore, the cache port is blocked during the data movement and system performance is consequentially degraded. When one example data movement scheme is extended from main memory to being applied to memory caches, one additional cache set (the gap set) is added and the data from one set to the gap set is moved periodically. Because cache techniques are more performance sensitive, main memory wear-leveling techniques cannot be used directly. Therefore, the use of data movement may be reconsidered when designing cache inter-set wear-leveling techniques.

Another option for implementing set address re-mapping for non-volatile memory caches is to perform data invalidation. Cache line invalidations can be used because the data in caches can be read back again later from lower-level memories. This special feature of caches provides a new opportunity designing cache inter-set wear-leveling techniques.

Compared to data movement, invalidations do not incur any area overhead. Therefore, one aspect of the present disclosure modifies previous main memory wear-leveling techniques and enhances them by using a swap-shift wear-leveling scheme to reduce the inter-set write variation in non-volatile memory caches using invalidations.

In contrast to existing wear-leveling techniques for non-volatile main memories, the swap-shift scheme is designed for non-volatile memory caches. The swap-shift scheme uses data invalidation instead of data movement when changing the set address mapping in order to decrease both the area and the performance overhead.

One configuration of the swap-shift scheme shifts the mapping of cache physical sets to rotate the stored data between sets. Nevertheless, shifting all cache sets at one time results in a significant performance overhead. To solve this problem, the swap-shift scheme of the cache controller140only swaps the mapping of two sets at one time, and all cache sets can be shifted by one step after a complete swap rotation.

In this configuration, the cache controller140includes a global counter142that is used in the swap-shift scheme to store the number of memory write operations to the cache, which is denoted by the variable name “numWrite.” The cache controller140also includes a swap register144(SwapReg) the is used to store the current swapping value. SwapReg is initially set to 0 and cyclically changed from 0 to N−1, where N is the number of sets in the cache. The cache controller140further includes a shift register146(ShiftReg) that stores the current shifting value. ShiftReg is changed from 0 to N cyclically. These two values, SwapReg and ShiftReg, are used by the cache controller140to control two types of rotations in the shift-swap scheme, the swap rotation and the shift rotation.

First, the swap rotation is described. SwapReg is incremented by 1 when numWrite is equal to a specific predefined threshold (“threshold”), and one swap rotation occurs when SwapReg is moved by N−1 steps. Therefore, one swap rotation consists of N−1 swaps.

Second, the shift rotation will be described. ShiftReg is incremented by 1 after each swap rotation, and one shift rotation occurs when ShiftReg is moved by N steps. Therefore, each shift rotation consists of N swap rotations.

FIG. 2is a diagram200showing an example rotation for wear-leveling according to an aspect of the present disclosure. The diagram200includes a cache structure202and a set of rotation boxes204,206,208,210,212,214,216and218. The cache structure202is any structure that includes cache blocks114, cache ways108or cache sets116, and may include the entirety of the cache memory100itself, although for simplicity the cache structure202is represented as having a group of cache sets202a,202b,202cand202d. The first cache set202a, the second cache set202b, the third cache set202cand the fourth cache set202dare example cache sets shown for the rotation example of the diagram200, although the number of cache sets or sub-structures of the cache structure202is not limited to four. The rotation process is now be described.

In rotation box204, the cache structure202is in its initial position, with the first cache set202alabeled with a “0”, the second cache set202blabeled with a “1”, the third cache set202clabeled with a “2”, and the fourth cache set labeled with a “3”. There may also be data stored within each of the cache sets202a,202b,202cand202d. A SwapReg counter counts the number of times the cache sets have been swapped. The counter may be initialized to 0. A ShiftReg counter counts the number of times the entirety of the cache structure202has shifted positions (in that all of the cache sets within the cache structure202has been moved one position) may also be initialized and set to 0. The conventional approach for rotation uses a temporary block and clears all the cache sets or cache structures over time. Nevertheless, with the implementation shown in the diagram200, a temporary block is not used, nor are the data contents of the cache sets deleted or flushed. This is true because the data is not actually swapped and kept in the same location or position. Only the positions of the cache sets are being swapped, and only the contents from the swapped cache sets are cleared, leaving the contents of all the other cache sets intact. Each of the cache sets are also moved to their new location and new data is auto-loaded into the new cache set, without having to move any data. Again, the only thing that is swapped is the location of the cache sets. Everything is done with swap operations, instead of actually moving data.

In rotation box206, the position of the first cache set202a(0) is swapped with the position of the second cache set202b(1). As a result, the second cache set202b(1) is now the very first or top cache set, and the first cache set202a(0) becomes the second cache set, next to or below the first cache set202a(0). In one implementation, once this swap occurs, new data will be auto-reloaded into the new cache sets once in their new positions. In one implementation, the swapped cache sets will retain their data, so new data will not be auto-reloaded into the cache sets once they are swapped. The SwapReg counter, which counts the number of times the cache sets have been swapped, may also be incremented by 1. In rotation box208, the position of the first cache set202a(0) (now in the second position, the old position of the second cache set202b(1)) is swapped with the position of the third cache set202c(2). Now, the third cache set202c(2) becomes the second position (former position of the second cache set202b(1)), and the first cache set202a(0) becomes the third position (former position of the third cache set202c(2)). The SwapReg counter may be then be incremented by 1 again.

In the rotation box210, the position of the first cache set202a(0) (now in the third position, the old position of the third cache set202c(2)) is swapped with the position of the fourth cache set202d(3). Now, the fourth cache set202d(3) becomes the third position (former position of the third cache set202c(2)), and the first cache set202a(0) becomes the fourth position (former position of the fourth cache set202d(3)). The SwapReg counter may then be initialized because all the cache sets have been shifted, and the ShiftReg counter becomes incremented because after three rounds of swapping, all the registers within the cache structure202have been shifted by one position.

Continuing on to the rotation box212, the position of the second cache set202b(1) is swapped with the position of the third cache set202c(2). Now, the second cache set202(b) (1) becomes the second position (former position of the third cache set202c(2)), and the third cache set202c(2) becomes the first position (former position of the second cache set202b(1)). The SwapReg counter also becomes incremented by 1. In rotation box214, the position of the second cache set202b(1) is swapped with the position of the fourth cache set202d(3). Now, the fourth cache set202d(3) becomes the second position (former position of the second cache set202b(1)), and the fourth cache set202d(3) becomes the second position (former position of the second cache set202b(1)). The SwapReg counter also increments by 1. In rotation box216, the position of the second cache set202(b) (1) is swapped with the position of the first cache set202(a) (0). Now, the second cache set202(b) (1) becomes the fourth position (former position of the first cache set202a(0)), and the first cache set202a(0) becomes the third position (former position of the second cache set202b(1)). The SwapReg counter is then initialized and the ShiftReg counter increments by 1 because after another three rounds of swapping, all the registers within the cache structure202have been shifted by two positions.

In one implementation, the contents of the entire cache are not flushed because everything is done by swap operations. Furthermore, swap operations do not involve any performance degradation. By using swap operations to perform the swapping, “shift up” operations and/or tracking does not occur. In one implementation, the data is not swapped, just the positions, and the data is then reloaded into the new swapped location. In one implementation, the data in un-used positions is simply discarded, such as invalid cache sets. In one implementation, for one swap, the contents of the cache set corresponding to the SwapReg counter position (e.g., cache-register[SwapReg]) and the contents of the cache set corresponding to the SwapRea counter plus one (e.g., cache-register[SwapReg+1]) may be discarded. Then, their physical locations are swapped. After N−1 swaps, where N is the number of cache sets in the cache structure, all the physical locations within the cache structure (each of the cache sets are all shifted by 1.

In one implementation, the SwapReg and ShiftReg counters may be implemented as the swap register144and the shift register146of the cache controller140for storing data, as shown inFIG. 1. In this case, the registers are implemented as some sort of numerical data that keeps track of the value for their respective counters.

FIG. 3is a logic flowchart300showing the operation of a cache controller for wear-leveling a cache memory according to an aspect of the present disclosure.FIG. 3shows how the ShiftReg and SwapReg counters are updated in a wear-leveling system with respect to writing activity. In block302, it is determined whether there has been a cache write. If there is a cache write, then in block304, a cache write counter known as “numWrite” is incremented by one. If there is not a cache write, the process goes back to before block302. The numWrite counter also triggers when to swap. There is also some predetermined threshold value that determines how many writes is enough to initiate a swap of a cache set. For example, in block306, it is determined whether the numWrite counter is equal to the predetermined threshold. If so, then in block308, a swap is initiated, updating the numWrite counter to a zero value and updating the SwapReg counter to the value of (SwapReg+1) mod (N−1). Mod is the modulo operator and N is the total number of cache sets in the selected cache structure. In block306, if the numWrite counter is not equal to the predetermined threshold, then the process goes back to block304. In block310, it is determined whether the SwapReg counter is equal to zero. If so, then in block312, the ShiftReg counter is updated to the value of (ShiftReg+1) mod N. This shifts the entire cache structure by one. In block310, if the value of the SwapReg counter is not equal to zero, then the process goes back to block308.

FIG. 3may also be expressed by the following pseudo code:

FIG. 4is a logic flowchart400showing the operation of a cache controller for wear-leveling a cache memory according to an aspect of the present disclosure.FIG. 4shows a global counter404storing a numWrite counter that represents the number of writes, each write represented by the cache write action402. The SwapReg counter (reflected as “SwapReg”) and the ShiftReg counter (expressed as “ShiftReg”) may be implemented as data registers for respectively storing the SwapReg and ShiftReg values.

As described with respect toFIG. 3, if there is a cache write402, then the global counter404is increased. If the global counter is equal to a predetermined threshold value at406, at block408a swap occurs, updating the SwapReg counter to the value of (SwapReg+1) mod (N−1), where mod is the modulo operator and N is the number of total cache sets. If SwapReg is zero (410), then in block412, the ShiftReg counter is updated to the value of (ShiftReg+1) mod N.

When a logical set (LS) number comes in as a logical set number input414, the physical set (PS) number can be computed as a physical set number output418based on three different situations.

First, as shown in logic box416, if the logical set number input414is equal to the SwapReg value, it means that this logical set is exactly the cache set that should be swapped in this rotation. Therefore, the physical set is mapped to the current shift value of ShiftReg and output as the physical set number output418.

Second, as also shown in logic box416, if the logical set number input414is larger than the SwapReg value, it means that this cache set has not been shifted in this rotation and keeps the same mapping as the last rotation. Therefore, the physical set is mapped to LS+ShiftReg. In one implementation, the mapping is done by taking the (LS+ShiftReg) value and performing a modulo operation with N, the number of cache sets, and then assigning the resulting value to the physical set.

Third, as also shown in logic box416, if the logical set number input414is smaller than the SwapReg value (the else clause), it means that this cache set has been shifted in this rotation. Therefore, the physical set is mapped to LS+ShiftReg+1. In one implementation, mapping is done by taking the (LS+ShiftReg+1) value and performing a modulo operation with N, the number of cache sets, and then assigning the resulting value to physical set.

Three operations similar to the operations discussed above occur in logic box422, but for the physical set input number424in order to compute a logical set number output420.

When the cache line needs to be written back into the lower level memory, the logical set address is re-generated. The mapping from physical set to logical set is symmetrical. This mapping scheme can also be verified as can be seen inFIG. 2. Because SwapReg and ShiftReg are changed along with increasing write counts, the mapping between logical set and physical set is changing all the time, which ensures the writes to different physical sets are balanced, reducing write variations.

Compared to conventional cache architectures, the set index translation in the shift-swap wear-leveling scheme only adds a simple arithmetic operation and can be merged into the row-decoder. In addition, this one-cycle latency overhead is only paid on higher-level cache misses that access lower-level caches.

FIG. 5is a process flow diagram500illustrating a method for wear-leveling according to an aspect of the present disclosure. In block502, a number of memory write operations are counted by a global counter by incrementing the global counter by one for every memory write operation. In block504, when the global counter is equal to a predetermined threshold value, a swap operation is performed and a swap counter is incremented by one. Also, performing the swap operation includes remapping the swapped cache sets, which in turn includes placing dirty data within the two swapped cache sets into the write back buffer and invalidating the other data in the two swapped cache sets.

In block506, when the swap counter is equal to N−1, a shift counter is incremented by one and the swap counter is set back to zero. N is the number of cache sets in the cache memory. In block508, when the shift counter is equal to N, the shift counter is set back to zero. In block510, an input cache set number is converted into an output cache set number. The input or output cache set number may be the logical set number or the physical set number.

FIG. 6is a process flow diagram600illustrating a method for wear-leveling according to an aspect of the present disclosure. In block610, it is determined whether a number of memory write operations to a cache memory (e.g., numWrites) has reached a predetermined threshold. If so, in block612a memory location swap operation is performed on two cache sets. In block614, the contents from one of the two swapped cache sets are cleared, in block616, the memory contents of the other of the swapped two cache sets are left intact. In block618, the swapping of the cache set is tracked. In block620, a logical cache set number is converted to a physical cache set number. If the number of write operations has not reached the threshold, the process remains at block610.

In the swap-shift wear-leveling scheme, the inter-set write variation reduction is related to the number of shift rotations during the experimental time. Assuming there are N sets in the cache, one shift rotation includes N swap rotations and one swap rotation in the swap-shift scheme needs N−1 swaps. After each shift rotation, all cache sets are shifted by N steps and logical set indices are mapped to their original positions. Therefore, the more rounds the cache is shifted, the more evenly the write accesses are distributed to each cache set.

According to a further aspect of the present disclosure, a cache controller for wear-leveling of a cache memory is described. The cache controller includes a means for dynamically rotating cache sets of the cache memory by performing a plurality of memory location swap operations on the cache sets when a number of memory write operations to the cache memory reaches a threshold value. Each swap operation may include clearing contents from only swapped cache sets, while leaving memory contents of other cache sets intact. The dynamically rotating means may be the cache controller140. The apparatus further includes a means for tracking the swapped cache sets to convert a logical cache set number to a physical cache set number. The tracking means may be the cache controller140, the global counter142, the swap register144, and/or the shift register146. In another aspect, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

FIG. 7is a block diagram showing an exemplary wireless communication system700in which an aspect of the disclosure may be advantageously employed. For purposes of illustration,FIG. 7shows three remote units720,730, and750and two base stations740. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units720,730, and750include IC devices725A,725C, and725B that include the disclosed cache memory. It will be recognized that other devices may also include the disclosed cache memory, such as the base stations, switching devices, and network equipment.FIG. 7shows forward link signals780from the base station740to the remote units720,730, and750and reverse link signals790from the remote units720,730, and750to base stations740.

InFIG. 7, remote unit720is shown as a mobile telephone, remote unit730is shown as a portable computer, and remote unit750is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, or other devices that store or retrieve data or computer instructions, or combinations thereof. AlthoughFIG. 7illustrates remote units according to the aspects of the disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the disclosure may be suitably employed in many devices, which include the disclosed cache memory.

FIG. 8is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the cache memory disclosed above. A design workstation800includes a hard disk801containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation800also includes a display802to facilitate design of a circuit810or a semiconductor component812, such as a cache memory. A storage medium804is provided for tangibly storing the circuit design810or the semiconductor component812. The circuit design810or the semiconductor component812may be stored on the storage medium804in a file format such as GDSII or GERBER. The storage medium804may be a CD-ROM, digital versatile disc (DVD), hard disk, flash memory, or other appropriate device. Furthermore, the design workstation800includes a drive apparatus803for accepting input from or writing output to the storage medium804.

Data recorded on the storage medium804may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium804facilitates the design of the circuit design810or the semiconductor component812by decreasing the number of processes for designing semiconductor wafers.