Image sensor using backside illumination photodiode and method for manufacturing the same

A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.

BACKGROUND

1. Technical Field

The present disclosure relates to a technology for manufacturing an image sensor using a backside illumination photodiode, and more particularly, to an image sensor using a backside illumination photodiode and a method for manufacturing the same, in which a process may be simplified and a misalignment margin may be secured when bonding two wafers.

2. Related Art

FIG. 1illustrates the structure of a conventional image sensor which is manufactured through a 3D CIS (CMOS image sensor) manufacturing process.

Referring toFIG. 1, an image sensor100includes a top wafer100T which has a plurality of top metal layers110T, a plurality of top vias120T and a plurality of top bonding pads130T, and a bottom wafer100B which has a plurality of bottom metal layers110B, a plurality of bottom vias120B and a plurality of bottom bonding pads130B.

The plurality of top metal layers110T which are formed in the top wafer100T are respectively electrically connected to the top bonding pads130T through the top vias120T with a corresponding number.

Similarly, the plurality of bottom metal layers110B which are formed in the bottom wafer100B are respectively electrically connected to the bottom bonding pads130B through the bottom vias120B with a corresponding number.

The top wafer100T and the bottom wafer100B are electrically connected by the top bonding pads130T and the bottom bonding pads130B which are formed to face each other.

In this way, the conventional image sensor100has a structure in which the top wafer100T and the bottom wafer100B are electrically connected with each other by the top bonding pads130T which are formed to correspond to the number of the top metal layers110T in the top wafer100T and the bottom bonding pads130B which are formed to correspond to the number of the bottom metal layers110B in the bottom wafer100B.

However, the image sensor100structured in this way may be encountered with a problem in that the characteristics of pixels are likely to deteriorate due to the parasitic capacitance induced in the pluralities of bonding pads130T and130B. Also, another problem may be caused in that a process margin is likely to become insufficient due to a misalignment.

SUMMARY

Various embodiments are directed to electrically connecting two wafers by using the vias of one wafer of a first wafer and a second wafer and the bonding pads of the other wafer when manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process.

Also, various embodiments are directed to electrically connecting two wafers by using the vias of the two wafers when manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process.

In an embodiment, an image sensor using backside illumination photodiodes may include: a plurality of first metal layers formed in a first wafer including a plurality of backside illumination photodiodes which sense light incident from a backside and output signals and a plurality of transfer transistors which transfer the signals outputted from the backside illumination photodiodes, to floating diffusion nodes, the plurality of first metal layers being electrically connected with the floating diffusion nodes, respectively; a plurality of second metal layers formed in a second wafer including a plurality of pixel transistors which process signals transferred through the floating diffusion nodes and transfer processed signals, the plurality of second metal layers being electrically connected with the pixel transistors, respectively; a plurality of first bonding vias formed in the first wafer, and having one ends which are electrically connected to the first metal layers, respectively; a plurality of second bonding vias formed in the second wafer, and having one ends which are electrically connected to the second metal layers, respectively; and a plurality of bonding pads formed in the first wafer, and having one ends which are electrically connected with the other ends, respectively, of the first bonding vias and the other ends which are electrically connected with the other ends, respectively, of the second bonding vias.

In an embodiment, an image sensor using backside illumination photodiodes may include: a plurality of first metal layers formed in a first wafer including a plurality of backside illumination photodiodes which sense light incident from a backside and output signals and a plurality of transfer transistors which transfer the signals outputted from the backside illumination photodiodes, to floating diffusion nodes, the plurality of first metal layers being electrically connected with the floating diffusion nodes, respectively; a plurality of second metal layers formed in a second wafer including a plurality of pixel transistors which process signals transferred through the floating diffusion nodes and transfer processed signals, the plurality of second metal layers being electrically connected with the pixel transistors, respectively; a plurality of first bonding vias formed in the first wafer, and having one ends which are electrically connected to the first metal layers, respectively; a plurality of second bonding vias formed in the second wafer, and having one ends which are electrically connected to the second metal layers, respectively; and a plurality of bonding pads formed in the second wafer, and having one ends which are electrically connected with the other ends, respectively, of the second bonding vias and the other ends which are electrically connected with the other ends, respectively, of the first bonding vias.

In an embodiment, an image sensor using backside illumination photodiodes may include: a plurality of first metal layers formed in a first wafer including a plurality of backside illumination photodiodes which sense light incident from a backside and output signals and a plurality of transfer transistors which transfer the signals outputted from the backside illumination photodiodes, to floating diffusion nodes, the plurality of first metal layers being electrically connected with the floating diffusion nodes, respectively; a plurality of second metal layers formed in a second wafer including a plurality of pixel transistors which process signals transferred through the floating diffusion nodes and transfer processed signals, the plurality of second metal layers being electrically connected with the pixel transistors, respectively; a plurality of first bonding vias formed in the first wafer, and having one ends which are electrically connected to the first metal layers, respectively; and a plurality of second bonding vias formed in the second wafer, and having one ends which are electrically connected to the second metal layers, respectively, and the other ends which are electrically connected to the other ends of the first bonding vias, respectively.

In an embodiment, an image sensor using backside illumination photodiodes may include: a plurality of first metal layers formed in a first wafer including a plurality of backside illumination photodiodes which sense light incident from a backside and output signals, a plurality of transfer transistors which transfer the signals outputted from the backside illumination photodiodes, to floating diffusion nodes, and a plurality of pixel transistors for transferring the output signals of the backside illumination photodiodes to corresponding pixels, the plurality of first metal layers being electrically connected with the pixel transistors, respectively; a plurality of second metal layers formed in a second wafer including a plurality of logic transistors for processing signals outputted through the pixel transistors, the plurality of second metal layers being electrically connected with the logic transistors, respectively; a plurality of first bonding vias formed in the first wafer, and having one ends which are electrically connected to the first metal layers, respectively; a plurality of second bonding vias formed in the second wafer, and having one ends which are electrically connected to the second metal layers, respectively; and a plurality of bonding pads formed in the first wafer, and having one ends which are electrically connected with the other ends, respectively, of the first bonding vias and the other ends which are electrically connected with the other ends, respectively, of the second bonding vias.

In an embodiment, a method for manufacturing an image sensor using backside illumination photodiodes may include: (a) forming a plurality of backside illumination photodiodes which sense light incident from a backside and output signals and a plurality of transfer transistors which transfer the output signals of the backside illumination photodiodes to floating diffusion nodes, in a first wafer, and forming a plurality of first bonding vias which are electrically connected with the floating diffusion nodes, in an interlayer dielectric layer of the first wafer; (b) forming a plurality of pixel transistors for processing the output signals of the backside illumination photodiodes and transferring processed signals, in a second wafer, forming a plurality of second bonding vias which are electrically connected with the pixel transistors, in an interlayer dielectric layer of the second wafer, and forming bonding pads on the second bonding vias; and (c) bonding the first wafer and the second wafer, and electrically connecting the first bonding vias and the bonding pads with each other.

In an embodiment, a method for manufacturing an image sensor using backside illumination photodiodes may include: (a) forming a plurality of backside illumination photodiodes which sense light incident from a backside and output signals and a plurality of transfer transistors which transfer the output signals of the backside illumination photodiodes to floating diffusion nodes, in a first wafer, and forming a plurality of first bonding vias which are electrically connected with the floating diffusion nodes, in an interlayer dielectric layer of the first wafer; (b) forming a plurality of pixel transistors for processing the output signals of the backside illumination photodiodes and transferring processed signals, in a second wafer, and forming a plurality of second bonding vias which are electrically connected with the pixel transistors, in an interlayer dielectric layer of the second wafer; and (c) bonding the first wafer and the second wafer, and electrically connecting the first bonding vias and the second bonding vias with each other.

DETAILED DESCRIPTION

Exemplary embodiments will be described below in more detail with reference to the accompanying drawings. The disclosure may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the disclosure.

FIG. 2illustrates an example of a pixel circuit to which an image sensor using a backside illumination photodiode in accordance with an embodiment is applied. The pixel circuit includes a first wafer circuit block210and a second wafer circuit block220.

The first wafer circuit block210includes a photodiode PD, a transfer transistor Tx, and a first floating diffusion node FDT. The second wafer circuit block220includes a second floating diffusion node FDB, a reset transistor Rx, a drive transistor Dx, and a select transistor Sx.

The charges produced by the sensing operation of the photodiode PD are transferred to the first floating diffusion node FDTthrough the transfer transistor Tx which is formed in a first wafer.

In a second wafer, the drive transistor Dx and the select transistor Sx are electrically connected in series between a power terminal VDD and an output terminal VOUT, and the charges transferred through the first floating diffusion node FDTare transferred to the gate of the drive transistor Dx through the second floating diffusion node FDBwhich is formed in the second wafer.

Accordingly, an output voltage corresponding to the light sensed through the photodiode PD is supplied to a corresponding pixel through the drive transistor Dx and the select transistor Sx. In the second wafer, the reset transistor Rx is electrically connected between the power terminal VDD and the gate of the drive transistor Dx. The reset transistor Rx plays the role of supplying the voltage of the power terminal VDD to the gate of the drive transistor Dx and thereby resetting the second floating diffusion node FDBwhich is electrically connected with the drive transistor Dx, in a reset mode.

FIG. 3is a schematic cross-sectional view illustrating an image sensor using a backside illumination photodiode in accordance with an embodiment.

Referring toFIG. 3, an image sensor300includes a first wafer300T which has a plurality of first metal layers310T, a plurality of first bonding vias320T and a plurality of bonding pads330T, and a second wafer300B which has a plurality of second metal layers310B and a plurality of second bonding vias320B.

The first wafer300T may be a top wafer, and a second wafer300B may be a bottom wafer.

The plurality of first metal layers310T which are formed in the first wafer300T are respectively electrically connected to the bonding pads330T through the first bonding vias320T with a corresponding number.

In comparison with this, in the second wafer300B, bonding pads are omitted, and one ends of the second bonding vias320B are formed to a bonding surface340as an interface where the first wafer300T and the second wafer300B contact each other when they are bonded. The plurality of second metal layers310B which are formed in the second wafer300B are respectively electrically connected to the second bonding vias320B with a corresponding number.

The electrical connection of the first wafer300T and the second wafer300B is implemented by the bonding pads330T and the second bonding vias320B which are formed to face each other. The physical coupling of the first wafer300T and the second wafer300B may be realized in a variety of ways such as nitride bonding, metal bonding and oxide bonding.

The materials of the first bonding vias320T and the bonding pads330T of the first wafer300T and the second bonding vias320B of the second wafer300B may include Cu although they are not specifically limited, and in this case, a dual damascene process may be applied.

The first wafer300T may include backside illumination photodiodes which sense light incident from a backside and output signals, and transfer transistors which transfer the signals outputted from the backside illumination photodiodes, to floating diffusion nodes. One terminals of the transfer transistors are electrically connected to the backside illumination photodiodes, and the other terminals of the transfer transistors are electrically connected to the first bonding vias320T.

The second wafer300B may include pixel transistors (for example, reset transistors, drive transistors and select transistors) for transferring signals corresponding to the light sensed through the backside illumination photodiodes, to corresponding pixels, and logic transistors which are formed in a peripheral circuit region to process the signals outputted from the pixel transistors. One terminals of the pixel transistors are electrically connected to the second metal layers310B.

Each of the first wafer300T and the second wafer300B may include an interlayer dielectric layer.

FIG. 4is a schematic cross-sectional view illustrating an image sensor using a backside illumination photodiode in accordance with another embodiment. When comparingFIG. 4withFIG. 3, a difference resides in that bonding pads are omitted in a first wafer and are formed in a second wafer and the first wafer and the second wafer are bonded by the vias of the first wafer and the bonding pads of the second wafer.

Referring toFIG. 4, an image sensor400includes a first wafer400T which has a plurality of first metal layers410T and a plurality of first bonding vias420T, and a second wafer400B which has a plurality of second metal layers410B, a plurality of second bonding vias420B and a plurality of bonding pads430B.

The first wafer400T may be a top wafer, and a second wafer400B may be a bottom wafer.

In the first wafer400T, bonding pads are omitted, and one ends of the first bonding vias420T are formed to a bonding surface440as an interface where the first wafer400T and the second wafer400B contact each other when they are bonded. The plurality of first metal layers410T which are formed in the first wafer400T are respectively electrically connected to the first bonding vias420T with a corresponding number.

In comparison with this, the plurality of second metal layers410B which are formed in the second wafer400B are respectively electrically connected to the bonding pads430B through the second bonding vias420B with a corresponding number.

The electrical connection of the first wafer400T and the second wafer400B is implemented by the first bonding vias420T and the bonding pads430B which are formed to face each other. The physical coupling of the first wafer400T and the second wafer400B may be realized in a variety of ways such as nitride bonding, metal bonding and oxide bonding.

The materials of the first bonding vias420T of the first wafer400T and the second bonding vias420B and the bonding pads430B of the second wafer400B may include Cu although they are not specifically limited, and in this case, a dual damascene process may be applied.

The first wafer400T may include backside illumination photodiodes which sense light incident from a backside and output signals, and transfer transistors which transfer the signals outputted from the backside illumination photodiodes, to floating diffusion nodes. One terminals of the transfer transistors are electrically connected to the backside illumination photodiodes, and the other terminals of the transfer transistors are electrically connected to the first bonding vias420T.

The second wafer400B may include pixel transistors (for example, reset transistors, drive transistors and select transistors) for transferring signals corresponding to the light sensed through the backside illumination photodiodes, to corresponding pixels, and logic transistors which are formed in a peripheral circuit region to process the signals outputted from the pixel transistors. One terminals of the pixel transistors are electrically connected to the second metal layers410B.

Each of the first wafer400T and the second wafer400B may include an interlayer dielectric layer.

FIG. 5is a schematic cross-sectional view illustrating an image sensor using a backside illumination photodiode in accordance with still another embodiment.

Referring toFIG. 5, an image sensor500includes a first wafer500T which has a plurality of first metal layers510T and a plurality of first bonding vias520T, and a second wafer500B which has a plurality of second metal layers510B and a plurality of second bonding vias520B.

The first wafer500T may be a top wafer, and a second wafer500B may be a bottom wafer.

The plurality of first metal layers510T which are formed in the first wafer500T are respectively electrically connected with the first bonding vias520T with a corresponding number.

In the same manner, the plurality of second metal layers510B which are formed in the second wafer500B are respectively electrically connected with the second bonding vias520B with a corresponding number.

The electrical connection of the first wafer500T and the second wafer500B is implemented by the first bonding vias520T and the second bonding vias520B which are formed to face each other. The physical coupling of the first wafer500T and the second wafer500B may be realized in a variety of ways such as nitride bonding, metal bonding and oxide bonding.

The materials of the first bonding vias520T of the first wafer500T and the second bonding vias520B of the second wafer500B may include Cu although they are not specifically limited, and in this case, a dual damascene process may be applied.

The first wafer500T may include backside illumination photodiodes which sense light incident from a backside and output signals, and transfer transistors which transfer the signals outputted from the backside illumination photodiodes, to floating diffusion nodes. One terminals of the transfer transistors are electrically connected to the backside illumination photodiodes, and the other terminals of the transfer transistors are electrically connected to the first bonding vias520T.

The second wafer500B may include pixel transistors (for example, reset transistors, drive transistors and select transistors) for transferring signals corresponding to the light sensed through the backside illumination photodiodes, to corresponding pixels, and logic transistors which are formed in a peripheral circuit region to process the signals outputted from the pixel transistors. One terminals of the pixel transistors are electrically connected to the second metal layers510B.

Each of the first wafer500T and the second wafer500B may include an interlayer dielectric layer.

The size of the first bonding vias520T and the size of the second bonding vias520B are not specifically limited, and may be the same with or different from each other according to a design rule.

(a) and (b) ofFIG. 6illustrate examples of electrically connecting two wafers through bonding vias as inFIG. 5. That is to say, (a) and (b) ofFIG. 6are views illustrating examples of the structures of vias in the case where the sizes of a first metal layer610T and a second metal layer610B are different from each other.

First, (a) ofFIG. 6shows an example of forming a first bonding via620T and a second bonding via620B in the case where the size of the first metal layer610T is larger than the size of the second metal layer610B. In other words, there are shown the structures of the first bonding via620T and the second bonding via620B in the case where the relationship between a width (or diameter) “b” of the first metal layer610T and a width (or diameter) “a” of the second metal layer610B is b>a.

In such a case, in the first bonding via620T, a portion, which contacts the first metal layer610T, a portion, which contacts a bonding surface640as an interface where a first wafer600T and a second wafer600B contact each other when they are bonded, and an intermediate portion, which connects the two portions, are all formed uniformly to have the width “b”.

In comparison with this, in the second bonding via620B, a portion, which contacts the second metal layer610B, is formed to have the width “a” (for example, a=0.4 μm) in correspondence to the size of the second metal layer610B, a portion, which contacts the bonding surface640, is formed to have the width “b” (for example, b=0.8 μm) in the same manner as the corresponding surface of the first bonding via620T, and an intermediate portion, which connects the two portions, is formed to be inclined (for example, to an angle of 3° to 10°), by changing a via etch recipe.

By doing this, when connecting two vias with different pitches, the sizes of bonding contact surfaces may be determined to be the same with each other, and thereby, a bonding force may be increased.

(b) ofFIG. 6shows an example of forming a first bonding via620T and a second bonding via620B in the case where the size of the first metal layer610T is smaller than the size of the second metal layer610B. In other words, there are shown the structures of the first bonding via620T and the second bonding via620B in the case where the relationship between a width (or diameter) “a” of the first metal layer610T and a width (or diameter) “b” of the second metal layer610B is b>a. Because the structures of the first bonding via620T and the second bonding via620B define a reverse symmetry with respect to the structures of (a) ofFIG. 6, detailed descriptions thereof will be omitted.

FIG. 7is a flow chart to assist in the explanation of a method for manufacturing an image sensor using a backside illumination photodiode in accordance with an embodiment, andFIG. 8is of cross-sectional views of an image sensor, illustrating image sensor manufacturing processes according to the method ofFIG. 7.

The method for manufacturing an image sensor using a backside illumination photodiode in accordance with the embodiment will be described below in detail with reference toFIGS. 7 and 8.

First, as shown in (a) ofFIG. 8, on a first wafer810, backside illumination photodiodes811, which sense light incident from a backside and output signals, and transfer transistors812, which transfer the signals outputted from the backside illumination photodiodes811, to floating diffusion nodes, are formed (S710).

Then, as shown in (b) ofFIG. 8, first vias821, which are electrically connected with the transfer transistors812, are formed in a first interlayer dielectric layer820on the first wafer810, and first metal layers822are formed on the first vias821(S720).

As shown in (c) ofFIG. 8, first bonding vias823are formed on the first metal layers822(S730).

For reference, the first bonding vias823perform the same function as the first bonding vias420T ofFIG. 4.

At the same time with forming the backside illumination photodiodes811, the transfer transistors812, the first vias821for electrical connection of circuits and the first bonding vias823for electrical connection of wafers, on the first wafer810as described above, the following elements are formed on a second wafer830.

As shown in (d) ofFIG. 8, on the second wafer830, pixel transistors831(for example, reset transistors, drive transistors and select transistors) for transferring signals corresponding to the light sensed through the backside illumination photodiodes811, to corresponding pixels are formed (S740).

Next, as shown in (e) ofFIG. 8, second vias841, which are electrically connected with the pixel transistors831, are formed in a second interlayer dielectric layer840on the second wafer830, and second metal layers842are formed on the second vias841(S750).

As shown in (f) ofFIG. 8, second bonding vias843and bonding pads844are sequentially formed on the second metal layers842(S760).

For reference, the second bonding vias843perform the same function as the second bonding vias420B ofFIG. 4.

Thereafter, as shown in (g) ofFIG. 8, the first interlayer dielectric layer820on the first wafer810and the second interlayer dielectric layer840on the second wafer830are bonded with each other, and at this time, the first bonding vias823in the first interlayer dielectric layer820and the bonding pads844in the second interlayer dielectric layer840are electrically connected with each other (S770).

Thereupon, as shown in (h) ofFIG. 8, a passivation process, a process for forming color filters850and a process for forming microlenses860are performed (S780), and finally, a process for forming pads870is performed (S790).

While it was described above as an example that the first bonding vias823on the first wafer810and the bonding pads844on the second wafer830are electrically connected with each other, it is to be noted that the disclosure is not limited to such, and it is possible to electrically connect the bonding pads of a first wafer and bonding vias of a second wafer through appropriate processes.

FIG. 9is a flow chart to assist in the explanation of a method for manufacturing an image sensor using a backside illumination photodiode in accordance with another embodiment, andFIG. 10is of cross-sectional views of an image sensor, illustrating image sensor manufacturing processes according to the method ofFIG. 9.

The method for manufacturing an image sensor using a backside illumination photodiode in accordance with another embodiment will be described below in detail with reference toFIGS. 9 and 10.

First, as shown in (a) ofFIG. 10, on a first wafer1010, backside illumination photodiodes1011, which sense light incident from a backside and output signals, and transfer transistors1012, which transfer the signals outputted from the backside illumination photodiodes1011, to floating diffusion nodes, are formed (S910).

The transfer transistors1012play the role of transferring the signals outputted from the backside illumination photodiodes1011, to the floating diffusion nodes.

Then, as shown in (b) ofFIG. 10, first vias1021and first metal layers1022are formed in a first interlayer dielectric layer1020on the first wafer1010(S920).

As shown in (c) ofFIG. 10, first bonding vias1023are formed in the first interlayer dielectric layer1020(S930).

For reference, the first bonding vias1023perform the same function as the first bonding vias520T ofFIG. 5.

At the same time with forming the backside illumination photodiodes1011, the transfer transistors1012, the first vias1021and the first bonding vias1023on the first wafer1010as described above, the following elements are formed on a second wafer1030.

As shown in (d) ofFIG. 10, on the second wafer1030, pixel transistors1031(for example, reset transistors, drive transistors and select transistors) for transferring signals corresponding to the light sensed through the backside illumination photodiodes1011, to corresponding pixels are formed (S940).

The pixel transistors1031function to transfer the signals transferred through the floating diffusion nodes from the backside illumination photodiodes1011, to the corresponding pixels.

Next, as shown in (e) ofFIG. 10, second vias1041and second metal layers1042are formed in a second interlayer dielectric layer1040on the second wafer1030(S950).

As shown in (f) ofFIG. 10, second bonding vias1043are formed in the second interlayer dielectric layer1040(S960).

For reference, the second bonding vias1043perform the same function as the second bonding vias520B ofFIG. 5.

Thereafter, as shown in (g) ofFIG. 10, the first interlayer dielectric layer1020on the first wafer1010and the second interlayer dielectric layer1040on the second wafer1030are bonded with each other, and at this time, the first bonding vias1023on the first wafer1010and the second bonding vias1043on the second wafer1030are electrically connected with each other (S970).

Thereupon, as shown in (h) ofFIG. 10, a passivation process, a process for forming color filters1050and a process for forming microlenses1060are performed (S980), and finally, a process for forming pads1070is performed (S990).

Meanwhile, in an embodiment different from the above-described embodiments, a first wafer may include pixel transistors (for example, reset transistors, drive transistors and select transistors) in addition to backside illumination photodiodes, transfer transistors and floating diffusion nodes. In this case, first metal layers are electrically connected to pixel regions. In a second wafer, logic transistors for processing the signals outputted from the pixel transistors are formed and are electrically connected with the first wafer.

As is apparent from the above descriptions, when manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. As a consequence, the manufacturing process may be simplified since the number of pad forming processes is decreased to one half, and thereby, the manufacturing cost may be reduced.

Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of both the first and second wafers. As a consequence, the manufacturing yield may be increased since a process margin for a misalignment is secured, and the characteristic of a pixel may be improved since parasitic capacitance is reduced.

Further, in the case of bonding wafers in which pitches of top and bottom metals are different, since the sizes of bonding contact surfaces are determined to be the same, a bonding force may be increased.