ADC background calibration timing

A background calibrating, skip and fill, analog/digital converter (ADC) generates an output data sequence having successive data elements representing magnitudes of successive samples of an analog input signal (X) acquired during successive cycles of a clock signal. The ADC normally samples the analog input signal during most clock cycles, but occasionally executes a calibration cycle in which it samples a reference signal of known magnitude, determines the error in its output data, and calibrates itself to eliminate the error. The ADC calculates a magnitude of data elements of the output sequence corresponding to samples of the input signal that were skipped during a calibration cycle by interpolating preceding and succeeding sample values. The ADC initiates a calibration cycle when a variation in magnitudes of at least two most recent samples of the input signal has remained within a first predetermined limit, provided that a predetermined minimum number of clock signal cycles have occurred since the calibration timing circuit last initiated a calibration cycle. The ADC may also refrain from initiating a calibration cycle unless a magnitude of a most recent sample of input signal is within a second predetermined limit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates in general to analog/digital converters (ADCs) and in particular to a method and apparatus for timing background calibration in an ADC.

2. Description of Related Art

FIG. 1depicts a typical prior art, self-calibrating, analog-digital converter (ADC)22for digitizing an analog input signal X to produce a digital data sequence Y′ representing the voltage of signal X at successive edges of a clock signal CLK. Input signal X passes through a switch24to the input of an ADC26. In response to each edge of clock signal CLK, ADC26samples signal X and produces a “raw”, uncalibrated, digital output sequence Y supplied as input to a calibration circuit28. For example, calibration circuit28may act as a lookup table, altering the value of each element of sequence Y′ as necessary to compensate for errors in the output sequence Y of ADC26, thereby to produce a corresponding element of output sequence Y′. During a calibration process, a calibration control circuit30supplies a reference signal VREF of various known voltages as input to ADC26via switch24, monitors ADC output Y to determine its error, and supplies programming data to calibration circuit28configuring it to appropriately compensate for detected errors in Y. WhileFIG. 1depicts an ADC22including a calibration circuit28for altering the output of ADC26, other self-calibrating ADCs use other approaches to calibration. For example, calibration control circuit30could calibrate ADC26by adjusting the gain and offset of an input amplifier within ADC26, thereby eliminating the need for calibration circuit28.

The errors in the output of ADC26arise due to various “non-ideal” effects associated with its internal components, including the settling time of its internal sample and hold amplifier, the finite gain and offset of its internal amplifier(s), and reflections and other effects due to component mismatches. These sources of error typically limit the speed and accuracy of ADC26and impose stringent requirements on its component design that can prolong design time and increase hardware cost. By compensating for errors in the output of ADC26, calibration circuit28can reduce the severity of the ADC's component design requirements, thereby reducing design time and hardware cost.

ADC calibration techniques fall into two categories: foreground calibration and background calibration. ADC22ofFIG. 1employs foreground calibration wherein calibration control circuit30calibrates ADC22only once, during a start-up period following power-on when ADC22is not actively digitizing input signal X to produce output sequence Y′. After programming calibration circuit28, calibration control circuit30signals switch24to supply input signal X to ADC26so that ADC22enters its normal mode of operation, continuously digitizing input signal X to produce output sequence Y′. The main drawback to foreground calibration is that since the ADC is calibrated only once at startup, the ADC can drift out of calibration over time. Operating characteristics of components of ADC26can change over time, for example due to temperature changes and circuit aging, and such changes can cause the error in output data sequence Y to drift. ADCs employing background calibration repeatedly carry out the calibration process “in the background” while the ADC is digitizing an analog input signal to update ADC calibration from time-to-time to compensate for drift in ADC error.

FIG. 2illustrates a prior art self-calibrating ADC31employing a form of background calibration. Here the analog signal X being digitized provides an input to a high-speed, but inaccurate, ADC32as well as to a lower speed, but highly accurate, ADC34. A calibration circuit36modifies the output sequence Y of ADC32to compensate for errors, thereby to produce the digitizer output sequence Y′. A calibration control circuit38compares each element of the output sequence Yrof ADC34to an element of output sequence Y of ADC32representing a concurrently acquired sample of input signal X to determine the error in sequence Y and then appropriately adjusts the programming of calibration circuit36. This approach has the disadvantage of requiring a highly accurate ADC34not subject to errors that drift over time, and such an ADC can be difficult and expensive to design and implement. U.S. Pat. No. 6,606,042 issued Aug. 12, 2003 to Sonkusale et al teaches this type of background calibration method in the context of a pipelined ADC.

The article by I. Galton, “Digital Cancellation of D/A Converter Noise in Pipelined A/D converters,”IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47 no. 3, pp. 185–196, March 2000, discusses another approach to background calibration wherein a known pseudo-random reference signal is added to the normal analog input to produce a modified input to the ADC. The value of the reference signal is then subtracted from the raw ADC output data to produce the digital data representing the analog input signal. A calibration control circuit uses statistical analysis techniques to extract the ADC error from the raw ADC output data so that it can determine how to appropriately adjust the raw data to compensate for the ADC error. One disadvantage to this approach is that adding the reference signal to the input signal reduces the usable dynamic range of the normal input.

According to sampling theory, the information carried by an analog signal can be fully preserved by discrete-time samples when an ADC's sampling rate is higher than twice the highest frequency components of the signal. For a “Nyquist rate” ADC, the sampling rate just meets that criterion. When an ADC uses a sampling rate higher than needed, it has extra resources available to do the calibration in the background. Once in a while it can replace the normal analog input signal with a reference signal of known magnitude to check the ADC's error. The ADC later fills in the output data sequence with output data representing the sample of the normal analog input signal that was “skipped” during the calibration cycle by interpolating preceding and subsequent sample values. This “skip and fill” type of background calibration works well but adds overhead by requiring a higher than normal sampling speed.

FIG. 3depicts a self-calibrating ADC42employing skip and fill background calibration. A switch44normally passes analog input signal X to an ADC46producing output sequence Y. A delay circuit48delays Y by a number of clock cycles to produce an output sequence Ya. A switch50normally supplies sequence Yaas an input sequence Ybto a calibration circuit52programmed to adjust values of elements of sequence Ybto compensate for errors in sequence Y caused by ADC46. A timer circuit54periodically sends a SKIP signal to a calibration control circuit56telling it to carry out a calibration procedure wherein it supplies a known reference voltage as input to ADC46via switch44in place of input signal X for one cycle of clock signal CLK so that calibration control circuit56can monitor Y and adjust the programming of calibration circuit52as necessary. During each clock cycle in which ADC46receives reference signal VREF, rather than input signal X, ADC output signal Y will reflect the magnitude of VREF rather than the magnitude of input signal X. Delay circuit48delays Y for K cycles of clock signal CLK, so during the Kthclock cycle following a cycle in which ADC46digitizes VREF, the value of the current element of sequence Yawill reflect the magnitude of reference signal VREF rather than input signal X. Calibration control circuit56therefore signals switch50to pass the output Ycof an interpolation filter58, rather than Yaas input Ybto calibration circuit52. Interpolation filter58uses interpolation to estimate an appropriate value of the current element of Ycas a function of values of proceeding and succeeding elements of the Y sequence. The K cycle delay of the delay circuit48matches the processing latency of the interpolation filter58. For example,FIG. 4shows the value of Ybas a function of time in a case where calibration control circuit56performs a calibration operation on every fourth cycle of the CLK signal. Thus, interpolation filter58provides the value of Ycon clock cycles4,8,12,16, and20although in practice, the calibration process is carried out much less frequently. Since changes in error of ADC46normally occur relatively slowly, the average time between calibration cycles can usually be made quite long without significantly affecting the ability of the calibration process to compensate for changes in ADC46.

U.S. Pat. No. 6,473,012 discloses a “randomized timing” type of skip and fill background calibration. To implement that kind of skip and fill background calibration, timer54could be a random or pseudo-random time interval generator that asserts the SKIP signal with randomly or pseudo-randomly varying time intervals. Thus, as illustrated inFIG. 5, calibration cycles might occur, for example, at2,5,10,14, and20. Randomized timing skip and fill background calibration avoids overlooking any periodic error pattern in Y that could be missed using a fixed timing skip and fill background calibration technique.

In either type of skip and fill background calibration, interpolation filter58estimates the values of skipped samples of input signal X based on values interpolated from neighboring samples. The interpolated values will have some error, but if a highly accurate, finite impulse response (FIR) filter with many taps implements interpolation filter58, the interpolation errors can be very small. However, a high performance interpolation filter58not only requires substantial hardware but also introduces long latency because it has to buffer sample data over a long period before and after a skipped sample to accurately interpolate the skipped value.

What is needed is an ADC using skip and fill background calibration that can achieve relatively high interpolation accuracy using an interpolation filter having a relatively small number of taps and having a relatively short latency.

SUMMARY OF THE INVENTION

A background calibrating, skip and fill, analog/digital converter (ADC) generates an output data sequence having successive data elements representing magnitudes of successive samples of an analog input signal (X) acquired during successive cycles of a clock signal. The ADC normally samples the analog input signal during most clock cycles, but occasionally executes a calibration cycle in which it samples a reference signal of known magnitude, determines the error in its output data, and calibrates itself to eliminate the error. An interpolation filter within the ADC calculates a magnitude of data elements of the output sequence corresponding to samples of the input signal that were skipped during a calibration cycle by interpolating preceding and succeeding sample values.

In accordance with one aspect of the invention, the ADC initiates a calibration cycle when a variation in magnitudes of at least two most recent samples of the input signal has remained within a first predetermined limit. This improves the accuracy of the interpolation filter because the interpolation need only interpolate between data elements that are relatively similar in magnitude.

In accordance with another aspect of the invention, the ADC refrains from initiating a calibration cycle until a predetermined minimum number of clock signal cycles have occurred since the calibration timing circuit last initiated a calibration cycle.

In accordance with a further aspect of the invention, the ADC may also refrain from initiating a calibration cycle unless a magnitude of a most recent sample of the input signal is within a second predetermined limit.

The claims appended to this specification particularly point out and distinctly claim the subject matter of the invention. However those skilled in the art will best understand both the organization and method of operation of what the applicant(s) consider to be the best mode(s) of practicing the invention by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.

DETAILED DESCRIPTION OF THE INVENTION

The invention relates to a self-calibrating analog/digital converter (ADC) employing an improved “skip and fill” background calibration. While the specification below describes example implementations of the invention believed to be the best modes of practicing the invention, other implementations of the invention are possible. Thus, the claims appended to the specification, rather than the descriptions of the example implementations of the invention described below, are intended to define the true scope of the invention.

FIG. 6depicts a self-calibrating ADC62in accordance with the invention for generating an output data sequence Y′ representing magnitudes of successive samples of an analog input signal X acquired on successive edges of a clock signal CLK. A switch64, controlled by a control signal CONT1, normally passes analog input signal X as an input signal Z to an ADC66producing a digital data sequence Y representing magnitudes of successive samples of analog signal X. A delay circuit68delays Y by a number of clock cycles to produce an output sequence Ya. A switch70controlled by a control signal CONT2, normally supplies sequence Yaas an input sequence Ybto a calibration circuit72programmed to adjust values of elements of sequence Ybto compensate for errors in sequence Y caused by ADC66.

ADC62employs a “skip and fill” type of background calibration wherein a calibration control circuit75, supplying control signals CONT1and CONT2, occasionally signals switch64to pass a reference signal VREF of known magnitude as the input signal Z to ADC66for one cycle of the CLK signal. Calibration control circuit75compares the value of the element of output sequence Y of ADC66produced in response to VREF to its expected value to determine the error in ADC66, and then calculates and supplies calibration data to calibration circuit72to update its programming so that it compensates for the error in ADC66output sequence Y.

During each clock cycle in which ADC66receives reference signal VREF, rather than input signal X, ADC output signal Y will reflect the magnitude of VREF rather than the magnitude of input signal X. Delay circuit68delays sequence Y for K cycles of clock signal CLK, so during the Kthclock cycle following a cycle in which ADC66digitizes VREF, the value of the current element of sequence Yawill reflect the magnitude of reference signal VREF rather than input signal X. Calibration control circuit75therefore signals switch70to pass the output Ycof an interpolation filter73, rather than Yaas input Ybto calibration circuit72. Interpolation filter73, suitably a finite-impulse response (FIR) filter, uses interpolation to estimate an appropriate value of the current element of Ycas a function of values of preceding and succeeding elements of the Y sequence. The K cycle delay of the delay circuit68matches the processing latency of the interpolation filter73, a function of the number of succeeding elements the filter uses in the calculation. Thus for each sample of analog input signal X that is skipped during a calibration cycle, interpolation filter73subsequently fills in the missing data element with an estimated value Ycfor that sample.

When ADC66samples analog signal X at a frequency more than twice that of its highest frequency component, it is possible for interpolation filter73to accurately estimate the value of a skipped sample of analog signal X through interpolation of magnitudes of several preceding and succeeding samples. However, the accuracy of the interpolation is an increasing function of the number of neighboring samples of signal X interpolation filter73uses when calculating a value for a missing sample, which is in turn an increasing function of the cost and complexity of the interpolation filter.

The invention relates to the manner in which calibration control circuit75determines when to skip a sample and carry out a calibration cycle. In particular, calibration control circuit carries out a calibration cycle only at times when the analog input signal is not varying much so that the magnitude of a skipped sample will be very similar to the magnitudes of the neighboring samples interpolation filter73uses when interpolating the skipped sample magnitude. For example,FIG. 7shows a sample being skipped and interpolated at time5because samples at times3and4were very close together in magnitude. An FIR interpolation filter73having only a relatively few taps could accurately estimate the magnitude of the analog input signal sample at time5based on the sampled magnitude of only a few preceding and succeeding samples because the analog signal value is not changing rapidly around time5. Similarly, samples were skipped and filled at times12and17because the analog signal X sample values were relatively stable at times10and11, and at times15and16. Since interpolation filter73need only interpolate between samples that are close together in magnitude, it can provide a very accurate estimate of the value of the skipped sample without having to implement an expensive and sophisticated interpolation scheme.

ADC62ofFIG. 6includes a calibration timing circuit77for asserting a signal CAL to tell calibration control circuit75when to initiate each calibration cycle. Calibration timing circuit77counts the number of CLK signal cycles since the last calibration cycle. When its count reaches a predetermined limit (for example 100), calibration timing circuit77monitors the magnitude of the analog input signal X to determine when it has been relatively stable for two CLK signal cycles in that it has changed by less than some predetermined maximum. When it detects a period of stability, calibration timing circuit77resets its internal CLK signal cycle count and asserts its output CAL signal to tell calibration control circuit75to initiate another calibration cycle. Thus, calibration timing circuit77initiates a calibration cycle whenever input signal X has been relatively stable, but only after a predetermined number of CLK signal cycles have occurred since the most recent calibration cycle.

The skipped samples of the analog input signal must always be separated by at least the delay of interpolation circuit73. For example, when interpolation circuit73is implemented by a symmetrical 9-tap FIR filter, the latency of the interpolation will be 4 CLK signal cycles. In such case calibration cycles should be separated by at least four CLK signal cycles or interpolation filter73won't have enough valid data samples to perform the interpolation for the skipped samples. Calibration timing circuit77could provide any arbitrary lower limit on the spacing between calibration cycles, as long as the number of CLK cycles between calibration cycles exceeds the interpolation delay. For example, it might provide for a minimum 100-cycle interval between calibration cycles even though the interpolation delay is only 4 cycles. In most applications it would not be necessary to perform a calibration cycle very often to keep the ADC properly calibrated because the error associated with a typical ADC66normally changes only slowly over time.

Calibration timing circuit77could monitor the magnitude of analog input signal X in various ways to determine times when it has been relatively stable. For example it could directly monitor input signal X or, if the latency of ADC66is not too large, calibration timing circuit77could monitor the most significant bits of its output sequence Y. Or, as discussed below, when ADC66is a pipelined ADC, calibration timing circuit77could monitor the low-resolution output(s) of the ADC's first stage(s).

FIG. 8depicts an example implementation of calibration timing circuit77ofFIG. 6that directly monitors the analog input signal X. A coarse (low resolution) ADC74digitizes input signal X in response to the same clock signal CLK controlling the sample timing of the higher resolution ADC66ofFIG. 6to produce a digital data sequence Yd. A register76delays Ydby one CLK signal cycle to produce a digital data sequence Ye, A comparator78compares current elements of the Ydand Yesequences and asserts its output signal MATCH when they are of the same value. Since ADC74has relatively coarse resolution, concurrent elements of the Ydand Yesequences will match even though the actual magnitude of analog input signal X changes by a small amount between successive samples. Thus the MATCH signal indicates when the analog input signal has been relatively stable for one clock cycle. A counter80counts down from a predetermined number (MIN—INTERVAL) on each edge of the CLK signal asserts an ENABLE signal when the count reaches 0. When comparator78thereafter asserts the MATCH signal, an AND gate82asserts the CAL signal to initiate a calibration cycle. The CAL signal also resets counter80. Thus the calibration timing circuit ofFIG. 8initiates a calibration cycle only when both of the following two conditions are true:

1. A number of CLK signal cycles since the last calibration cycle is at least as large as the number specified by MIN INTERVAL.

2. The value of Yd has remained stable, to within the resolution of ADC74, for two CLK signal cycles.

FIG. 9illustrates a modified version of calibration timing circuit77ofFIG. 8wherein an absolute value circuit83, a comparator84and AND gate86have been added. Absolute value circuit83finds the absolute value of Ydand comparator84compares |Yd| to a reference value MAXV and asserts an enable signal EN when |Yd| is less than MAXV. AND gate86ands the output of AND gate82with enable signal EN to produce the CAL signal. This embodiment of calibration timing circuit77helps to improve the accuracy of the interpolation by ensuring that input signal X ofFIG. 6is of low magnitude at the time a sample is skipped. When input signal X is small, the error introduced by interpolation is also small.

Thus the calibration timing circuit ofFIG. 9initiates a calibration cycle only when all of the following three conditions are true:

1. A number of CLK signal cycles since the last calibration cycle is at least as large as the number specified by MIN INTERVAL.

2. The value of Yd has remained stable, to within the resolution of ADC74, for two CLK signal cycles.

3. The magnitude of Yd is currently less than the value of MAXV.

The calibration timing circuit77ofFIG. 8or9requires a coarse ADC74to directly monitor analog signal X, but if the latency of ADC66ofFIG. 6is not too large, it is possible to use the most significant bits of the output sequence Y of ADC66to provide the Ydinput to register76since those bits of sequence Y would be equivalent to the output of coarse ADC74. Alternatively a quantizer could quantize the output of ADC66to supply the Ydinput to register76. In either case ADC74could be eliminated.

It is also possible to eliminate coarse ADC74ofFIG. 8or9when ADC66is a pipelined ADC, because a pipelined ADC includes an internal coarse ADC that could supply Yd.FIG. 10illustrates an example pipelined ADC including a set of N stages S(1)–S(N). Each Kth stage S(K) digitizes its input signal with relatively low resolution to produce output data yKrepresenting its input signal magnitude and also produces an analog residue signal rKsupplied as the input signal to the next stage. The magnitude of the output residue signal rKof stage S(K) is proportional to the difference between the magnitude represented by YKand the magnitude of stage input signal rK-1, where the analog input signal X acts as input to stage S(1). A set of shift registers90delay each signal y1by N−K clock cycles to produce separate portions of the ADC output data sequence Y. If the pipelined ADC ofFIG. 10were to implement ADC66ofFIG. 6, then the output y1of stage S(1) could provide the Ydinput to register76, provided stage S(1) has appropriate resolution.

As discussed above, the invention relates primarily to how calibration control circuit75acquires information regarding the error in the output of ADC66from which it determines how to adjust ADC calibration. Methods by which a calibration control circuit calibrates an ADC once the error information is known are well known in the prior art. WhileFIG. 6is an example of a self-calibrating ADC62in accordance with the invention employing a calibration circuit72to adjust its output sequence, other embodiments of the invention may employ other calibration mechanisms. For example, rather than adjusting a calibration circuit72at the output of ADC62, calibration control circuit75could directly adjust internal parameters of ADC66. For example, calibration control circuit75might adjust a gain and offset of an internal input signal amplifier within ADC66. In such case calibration circuit72can be omitted, with sequence Ybdirectly providing output sequence Y′.

The foregoing specification and the drawings depict exemplary embodiments of the best mode(s) of practicing the invention, and elements or steps of the depicted best mode(s) exemplify the elements or steps of the invention as recited in the appended claims. However the appended claims are intended to apply to any mode of practicing the invention comprising the combination of elements or steps as described in any one of the claims, including elements or steps that are functional equivalents of the example elements or steps of the exemplary embodiment(s) of the invention depicted in the specification and drawings.