POWER CONTROL DEVICE WITH SNUBBER CIRCUIT

An energy-efficient power control device, which employs a snubber circuit only during the risk of voltage spikes during fast switching, includes a buck converter, a power supply unit (PSU), a peak detecting circuit, a snubber circuit, and a logic circuit. The power control device supplies power to an input terminal of an electronic device. The snubber circuit is connected to the buck converter. The logic circuit is connected between the peak detecting circuit and the snubber circuit and determines whether the buck converter is under the heavy load or a light load according to the voltage, and connects the snubber circuit when the buck converter is under the heavy load, and disconnects the snubber circuit when the buck converter is under the light load.

DETAILED DESCRIPTION

FIG. 1is a circuit of power control device100of one embodiment. The power control device100supplies power to an input terminal200of an electronic device (not shown). The power control device100includes a buck converter10, a power supply unit (PSU)12, a peak detecting circuit30, a snubber circuit50, and a logic circuit70. The PSU12provides a direct current voltage Vin to the buck converter10. The buck converter10includes a controller11which is utilized to output a stable working voltage for the input terminal200. The peak detecting circuit30is electronically connected between the buck converter10and the logic circuit70. The peak detecting circuit30detects a voltage Vx of the buck converter10. The buck converter10provides the voltage Vx to a load (not shown) of the input terminal200. The voltage Vx varies with the load presented by the input terminal200. For example, if the load of the input terminal200becomes greater, the voltage Vx must become greater to make sure that the input terminal200is in a normal working state.

The snubber circuit50is electrically connected to the buck converter10. The logic circuit70is electrically connected to the snubber circuit50and defines a reference voltage value Vref. The logic circuit70compares the reference voltage value Vref with the voltage Vx detected by the peak detecting circuit30to generate a comparison and controls the snubber circuit50to work or to stop working based on the result of the comparison.

When the peak detecting circuit30detects that the voltage Vx is high, the logic circuit70determines that the buck converter10is under a heavy load and controls the snubber circuit50to work so as to protect the buck converter10. When the peak detecting circuit30detects that the voltage Vx is low, the logic circuit70determines that the buck converter10is under a light load and controls the snubber circuit50to stop working so as to cancel the drain of power taken by the snubber circuit50itself.

The buck converter10includes the controller11, a first switch Q1, a second switch Q2, an inductor L, and a filter capacitor C1. In this embodiment, the first switch Q1and the second switch Q2are field-effect transistors. Gate electrodes of the first switch Q1and the second switch Q2are electronically connected to the controller11. The controller11adjusts voltages of the gate electrodes to selectively close or open the first switch Q1and the second switch Q2. In this embodiment, the controller11is a pulse width modulation integrated circuit (PWM IC) chip. The controller11sends pulse width modulation signals to the first switch Q1and the second switch Q2, and adjusts duty ratio of the pulse width modulation signals to regulate turn-on times of the first switch Q1and the second switch Q2.

The first switch Q1and the second switch Q2are connected in series between the PSU12and the ground to obtain a node13between the first switch Q1and the second switch Q2, and a voltage of the node13is equal to the voltage Vx. A drain electrode of the first switch Q1is electronically connected to the PSU12, and a source electrode of the first switch Q1is electronically connected to a drain of the second switch Q2. A source electrode of the second switch Q2is grounded. A first end of the inductor L is electronically connected to the drain electrode of the second switch Q2, and a second end of the inductor L is electronically connected to ground through the filter capacitor C1. The input terminal200is connected in parallel with the filter capacitor C1.

When the controller11allows the first switch Q1to close (turn on), and allows the second switch Q2to open (turn off), the PSU12provides power to the input terminal200via the first switch Q1and the inductor L, and the inductor L stores electromagnetic energy. When the controller11allows the first switch Q1to open (turn off), and allows the second switch Q2to close (turn on), the inductor L acts like a voltage source and provides power to the input terminal200. Therefore, the first switch Q1alternately opens or closes and the voltage Vx is generated as PWM signals as shown inFIG. 2.

The peak detecting circuit30defines a detecting terminal301and an output terminal302. The detecting terminal301is electrically connected to the node13of the buck converter10and is utilized to detect the voltage Vx. The output terminal302is electrically connected to the logic circuit70. As shown inFIG. 2, the peak detecting circuit30converts the voltage Vx having an irregular waveform into an output voltage Vout having a sawtooth and more regular waveform and the output terminal302outputs the output voltage Vout.

In the embodiment, a time difference between peaks of the sawtooth waveform is very small and the output voltage Vout is similar to a smooth and constant voltage. In other words, the peak detecting circuit30converts the voltage Vx into a DC voltage Vout, the DC voltage Vout is proportional to the peak value of the voltage Vx, therefore, as the peak value of the voltage Vx becomes greater, the output voltage Vout also becomes greater. The logic circuit70compares the output voltage Vout with the reference voltage value Vref to determine whether the buck converter10is under a heavy load or the light load.

Referring toFIG. 2, the peak detecting circuit30includes a follower31, an amplifier32, and an RC circuit33. The RC circuit33is an integral circuit. The RC circuit33is composed of a resistor Ra and a capacitor Ca connected in parallel. The follower31tracks the voltage Vx to be integrated within the RC circuit33and outputs the sawtooth waveform voltage Vout to the logic circuit70.

The snubber circuit50includes a resistor R and a snubber capacitor C2connected in series. The drain electrode of the second switch Q2is connected to the resistor R. The snubber capacitor C2is connected to ground via the logic circuit70.

The logic circuit70includes a comparator71and a control switch73. The comparator71includes a first input terminal701, a second input terminal702, and an output terminal703. The control switch73includes a control terminal731, a first open terminal732, and a second open terminal733. The first input terminal701is electrically connected to the output terminal302of the peak detecting circuit30. The second input terminal702is electrically connected to the reference voltage Vref. The output terminal703is electrically connected to the control terminal731. The first open terminal732is electrically connected to the snubber capacitor C2and the second open terminal733is grounded.

The comparator71compares the output voltage Vout of the peak detecting circuit30with the reference voltage Vref. When the output voltage Vout of the peak detecting circuit30is greater than the reference voltage Vref, the comparator71controls the control switch73to close, and the snubber circuit50is activated and works to protect the buck converter10. When the output voltage Vout of the peak detecting circuit30is less than the reference voltage Vref, the comparator71controls the control switch73to open, and the snubber circuit50is cut off and stops working to avoid power being consumed by the snubber circuit50.

In the embodiment, the first input terminal701is a normal phase one and the second input terminal702is an abnormal phase one. The control switch73is a NMOS transistor. When the output voltage Vout of the peak detecting circuit30is greater than the reference voltage Vref, the buck converter10is under the heavy load, and the comparator71outputs a high level signal and controls the control switch73to close. When the output voltage Vout of the peak detecting circuit30is less than the reference voltage Vref, the buck converter10is under the light load, and the comparator71outputs a low level signal and controls the control switch73to open.

The working process of the power control device100is described as below. The PSU12provides the input voltage Vin to the buck converter10, and then the controller11sends PWM signals to the first switch Q1and the second switch Q2to selectively close or open the first switch Q1and the second switch Q2. The peak detecting circuit30detects the voltage Vx, and the logic circuit70compares the voltage Vx with the reference voltage Vref. If the voltage Vx is greater than the reference voltage Vref, the buck converter10is deemed to be under the heavy load. The peak detecting circuit30triggers the comparator71to close the control switch73. Thus, the snubber circuit50is connected in parallel with the second switch Q2to decrease and protect against any voltage spike of the voltage Vx. If the voltage Vx is less than the reference voltage Vref, the buck converter10is deemed to be under the light load. The peak detecting circuit30triggers the comparator71to open the control switch73and thus disconnect the snubber circuit50. Thus, the snubber circuit50is disconnected from the second switch Q2and power loss is avoided.

The peak detecting circuit30determines whether the buck converter10is under the heavy load or the light load. If the buck converter10is under the heavy load, the peak detecting circuit30triggers the comparator71to allow the snubber circuit50to connect in parallel with the second switch Q2, to decrease any voltage spike. If buck converter10is under the light load, the peak detecting circuit30triggers the comparator71to allow the snubber circuit50to be disconnected from the second switch Q2and the power drain represented by the snubber circuit50is avoided.