PoP device

A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.

BACKGROUND

Electronics can be divided into a simple hierarchy consisting of devices such as integrated circuit (IC) chips, packages, printed circuit boards (PCB), and a system. The package is the interface between an electronic device, such as a computer chip, and a PCB. The devices are made from semiconductor materials, such as silicon. The IC chips can be assembled into a package, such as a quad flat pack (QFP), a pin grid array (PGA), or a ball grid array (BGA), for example using wire bonding (WB), tape automated bonding (TAB), or flip chip (FC) bumping assembly techniques. A packaged device is attached either directly to a printed wiring board or to another type of substrate, which is defined as a second level of packaging.

In BGA packaging technology, a semiconductor or IC chip is mounted on a front surface of a substrate, and a plurality of conductive elements such as solder balls are arranged in a matrix array, customarily referred to as ball grid array, on a back surface of the substrate. The ball grid array allows the semiconductor package to be bonded and electrically connected to an external PCB or other electronic devices. The BGA package may be employed in a memory component such as Dynamic Random Access Memory (DRAM) and other memory devices.

Package-on-Package (PoP) is an integrated circuit packaging technique to allow vertically combining, for example, discrete logic and memory BGA packages. Two or more packages are installed on top of one another, e.g. stacked, with a standard interface to route signals between them. This allows higher density, for example in the mobile telephone/smartphone market.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.

Described herein are embodiments of a PoP device with a three-dimensional (3D) fan-out structure and a method for forming the PoP device. For example, the PoP device with the 3D fan-out structure may be a memory device or component. The PoP device may comprise a chip package, such as a PoP die and an embedded chip both encapsulated in a molding compound, a BGA, and a redistribution layer (RDL) for coupling the encapsulated PoP die and embedded chip to the BGA to achieve a 3D fan-out structure. The embedded chip may be bonded to a surface of the PoP die using an adhesive layer or a thermal interface material (TIM).

The RDL may allow electrical coupling between the BGA and interconnects of the encapsulated PoP die and embedded chip, thus achieving a fan-out structure without using or forming through vias, such as Through-Silicon vias (TSVs) or Through-Mold vias (TMVs). The RDL can be used for interconnecting the BGA and the encapsulated PoP die and embedded chip instead of a laminate interconnection layer, which is typically formed with TSVs or other interconnect structures to electrically couple a die or package to a BGA. Since a laminate interconnection layer is typically thicker than a RDL, replacing a laminate interconnection layer with a RDL reduces the vertical dimension of the device, i.e., the thickness of the PoP device, which may be beneficial and more suitable for compact electronic devices. Additionally, using a RDL instead of a laminate interconnection layer removes the need for forming vias (e.g., TSVs) and/or other interconnect structures to couple the BGA to the embedded chip and the chip package, which may simplify and reduce cost of device manufacture.

Embodiments are described herein with respect to a specific context, namely a PoP die, an embedded chip, a RDL, and a BGA that form together a PoP device with a 3D fan-out structure. Other embodiments may also be applied, such as for other fan-out structures where multiple layers of IC chips or packages are stacked vertically and then coupled through a RDL to a BGA or similar interconnect packages.

Throughout the various figures and discussion, like reference numbers refer to like components. Also, although singular components may be depicted throughout some of the figures, this is for simplicity of illustration and ease of discussion. A person having ordinary skill in the art will readily appreciate that such discussion and depiction can be and usually is applicable for many components within a structure.

FIG. 1illustrates a cross section of an embodiment of a PoP device100having a 3D fan-out structure, according to an embodiment. For example, the PoP device100may correspond to a memory device or component, such as a DRAM device or component. The PoP device100may comprise a PoP die10(or other chip package), an embedded chip20coupled to the PoP die10, a molding compound that encapsulates the PoP die10and the embedded chip20, a RDL30coupled to the encapsulated PoP die10and embedded chip20, and a BGA40coupled to the RDL30. The components or layers, above, of the PoP device100may be positioned and stacked with respect to one another as shown inFIG. 1.

The PoP die10may be formed and obtained using any suitable semiconductor fabrication processes. The PoP die10may comprise a plurality of stacked chips12, which may have different dimensions. The stacked chips12may comprise one or more semiconductor layers (e.g., silicon and/or other semiconductor materials), one or more conductive layers, one or more dielectric layers, or combinations thereof. The stacked chips12may be encapsulated by a second molding compound11and positioned on a substrate18. For example, the PoP die10may include two silicon chips of different dimensions stacked on top of each other on the substrate18and surrounded from the top and sides by the second molding compound11. The two stacked chips12and the second molding compound11are supported by the substrate18. The substrate18may be, for example, a silicon substrate (such as a silicon chip), a silicon or glass interposer, a printed circuit board (PCB), an organic laminate substrate, or the like.

The PoP die10may also comprise a plurality of pads15, which may be positioned on both sides of the substrate18and connected across the substrate18through vias16(e.g., through vias). The pads15on one side of the substrate (on the side of the stacked chips12) may be connected to the stacked chips12through bonding wires14. The pads15on the other side of the substrate18(opposite to the stacked chips12) may be bonded to a plurality of interconnects17, for instance in the form of solder balls or spheres (e.g., C4bumps) or, in other embodiments, other suitable bonding structures. The bonding wires14, pads15, and vias16provide electrical coupling between the stacked chips12and the interconnects17.

The embedded chip20may be formed on a surface of the PoP die10and may comprise a silicon chip22(or other semiconductor chip) and a bonding layer21that bonds the silicon chip22to the substrate18of the PoP die10. In an embodiment, the bonding layer21may be an adhesive layer formed of a glue or a lamination layer formed of a foil. In another embodiment, a TIM may be used as the bonding layer21to bond the silicon chip22to the substrate18. The TIM may make contact with the stacked chips12using through vias that may be formed in the substrate18to provide a thermally conductive connection between the silicon chip22and the stacked chips12. The TIM may be a thermal paste, such as a silicone rubber with thermally-conductive fillers such as aluminum oxide and/or boron nitride.

The embedded chip20may also comprise one or more metallic and dielectric layers formed between the silicon chip22and the RDL30. The layers may provide a suitable electrical connection between the silicon chip22and the RDL30and include a plurality of pads23(e.g., aluminum or other suitable metal pads), a passivation (dielectric) layer24, and a first polymer layer27, which may be arranged as shown inFIG. 1. The passivation layer24and the first polymer layer27may be patterned structures (discontinuous across the surface) to allow proper coupling between the pads15and the RDL30.

The RDL30may comprise a second polymer layer31and a conductive layer32. The second polymer layer31may be a second polymer layer that is formed or deposited onto the first polymer layer27. The conductive layer32may be a metal layer, for example an aluminum, copper, titanium, polysilicon, or gold layer. The RDL30may also comprise a third polymer layer33formed or deposited onto the conductive layer32. As described above, the function of the RDL30is to provide electrical coupling between the embedded chip20and the BGA40without the formation of through vias (e.g., TSVs or TMVs). The second polymer layer31, the conductive layer32, and the third polymer layer33may be patterned to allow proper coupling between the pads15and the BGA40, i.e., through contact with interconnects17and the conductive layer32that provide the electrical coupling between the pads15and the BGA40. In an embodiment, a plurality of Under-Bump Metallization (UBM) elements41may be formed on the surface of the RDL30to bond the BGA40to the embedded chip20. The UBM elements41may be coupled to surface portions of the third polymer layer33and to the conductive layer32. The BGA40includes a plurality of conductive elements42, such as conductive spheres or micro bumps, which are arranged in an array (or other orderly pattern) and placed in contact with the UBM elements41.

As described above, the RDL30is used to couple the PoP die10and the embedded chip20to the BGA. As such, the RDL30can replace a laminate interconnection layer, which is typically used to bond and electrically couple a chip package to a BGA. Using the RDL30instead substantially reduces the overall thickness of the PoP device100(in the vertical or top-bottom direction ofFIG. 1). For example, the molding compound25that encapsulates the PoP die10and the embedded chip20may have a thickness equal or close to 550 micrometers (μm), the BGA40may have a thickness equal or close to 240 μm, and the RDL30may have a thickness equal or close to about 25 μm, while a typical thickness of a laminate interconnection layer is around 500 μm or more. Thus, using the RDL30reduces the overall thickness of the 3D fan-out structure from about 1,400 μm to about 800 μm, i.e., a reduction of more than 40 percent. The reduced thickness of the structure enables better packaging and integration for smaller devices, such as in smartphones, computer tablets, laptops, or other consumer devices. Further, the RDL30provides the electrical coupling between the components of the 3D fan-out structure (the PoP device100) without the formation of through vias, which facilitates fabrication and reduces cost.

FIGS. 2athrough 2hillustrate a process to form the PoP device100according to an embodiment. Although this embodiment is discussed with steps performed in a particular order, steps may be performed in any logical order.FIG. 2aillustrates an adhesive layer coating step, where an adhesive layer60may be disposed, for example laminated, on the carriers50. The adhesive layer60may be formed of a glue or may be a lamination layer formed of a foil. The carrier50may be any suitable substrate that provides (during intermediary steps of the fabrication process) mechanical support for carrying a plurality of stacked layers of the 3D fan-out structure. The carrier50may be, for example, a silicon substrate, a silicon or glass interposer, a PCB, an organic laminate substrate, or the like.

FIG. 2billustrates a first chip placement step, where a plurality of PoP dies10, e.g., an array of PoP dies10, may be placed on the adhesive layer60. In other embodiments, other types of chip packages may be placed on the adhesive layer60. The PoP dies10may be formed on the adhesive layer60or placed using any suitable method of placing the PoP dies10onto the adhesive layer60and integrating the PoP dies10into a manufacturing process flow. In one embodiment, the PoP dies10(without the interconnects17) may be attached to a transfer layer or substrate (not shown). The transfer layer may be utilized to place the PoP dies10over the adhesive layer60, e.g., using a flip-chip process. The placement of the PoP dies10may be performed by flipping the transfer layer (with the PoP dies10attached) and positioning the PoP dies10properly onto the adhesive layer50. The transfer layer may be removed after the PoP dies10have been flipped and placed on the adhesive layer50, for instance using a stripping or etching process to remove the material of the transfer layer from PoP dies10. The interconnects17may then be placed with the pads15on the surface of the PoP dies10.

FIG. 2cillustrates a second chip placement step, where a plurality of embedded chips20, e.g., an array of embedded chips20, may be aligned with and placed onto the PoP dies10. The embedded chips20may be formed and aligned appropriately on the PoP dies10. As shown inFIG. 2c, each of the embedded chips20may be aligned and positioned around the center of the exposed surface of a PoP die10, between the interconnects17(e.g., two solder balls) on the opposite sides of the PoP die10. Similar to the placement step of the PoP dies10, the embedded chips20may be formed on the PoP die10or placed using any suitable method of placing the embedded chips20onto the PoP die10and integrating the embedded chips20into a manufacturing process flow. In one embodiment, the embedded chips20(without the connector elements26) may be attached to a transfer layer or substrate (not shown). The transfer layer may be utilized to place the embedded chips20over the PoP dies10, e.g., using a flip-chip process. The placement of the embedded chips20may be performed by flipping the transfer layer (with the embedded chips20attached) and positioning the embedded chips20properly onto the PoP dies10. The transfer layer may be removed after the embedded chips20have been flipped and placed on the PoP dies10, for instance using a stripping or etching process to remove the material of the transfer layer from embedded chips20. The connector elements26may then be placed on the surface of the embedded chips20. The connector elements26inFIG. 2cmay correspond to the pads23inFIG. 1or may be any other suitable interconnect structures, such as bumps, bond pads, wire bonds, or the like.

FIG. 2dillustrates a molding step, where the molding compound25may be formed to encapsulate the PoP dies10and the embedded chips20on the adhesive layer60. The molding compound25may comprise a polymer, a molding underfill, the like, or a combination there of. The molding compound25may be formed by wafer level molding to envelope the PoP dies10and the embedded chips20(from the top and the sides) on the adhesive layer60.

FIG. 2eillustrates a grinding step, where the molding compound25may be partially grinded or otherwise removed (e.g., etched) to expose connector elements26at the top surface of the embedded chips20and at least top portions of the interconnects17(e.g., solder balls) of the PoP dies10. The thickness of the molding compound25may be reduced, for example, by a grinding or polishing process to expose the connector elements26and the interconnects17.

FIG. 2fillustrates a RDL formation step, where the RDL30may be formed on top of the thinned (or polished) molding compound25, the connector elements26, and the solder balls17. The conductive layer32of the RDL30may be formed (e.g., deposited) and patterned (e.g., using lithography processes or steps) to be in contact with exposed top surface portions of connector elements26and the interconnects17, as shown inFIG. 2f. A polymer layer39of the RDL30may be formed to extend along exposed top surfaces of the molding compound25, the conductive layer32, the connector elements26, and the interconnects17. The polymer layer39inFIG. 2fmay correspond to the second polymer layer31and the third polymer layer33inFIG. 1.

FIG. 2gillustrates a ball mount step, where the BGA40may be bonded to the RDL30. The conductive elements42of the BGA40may be placed into contact with the conductive layer32of the RDL30. In an embodiment, the BGA40may be coupled to the RDL30using a stencil print process. The conductive elements42of the BGA40may be coupled to UBM elements (not shown) in the RDL30that are formed on the conductive layer32. The conductive elements42may be C4bumps, micro bumps, or the like and may comprise a material such as tin, silver, lead-free tin, copper, the like, or a combination thereof. In another embodiment, the BGA40may be coupled to RDL30by another chip bonding process that does not utilize UBM elements in the RDL30. The conductive layer32of the RDL30provides electrical coupling between the conductive elements42of the BGA40(on one side) and both the connector elements26of the embedded chips20and the interconnects17of the PoP dies10. This removes the need of using a laminate interconnection layer to bond the chip/die package to the BGA to achieve a 3D fan-out structure, and hence reduces overall structure thickness, removes the need for forming through vias, and reduces cost.

FIG. 2hillustrates removing the carrier50and adhesive layer60(not shown) and obtaining separate and individual chip/die packages. Each chip/die package may correspond to one PoP device100with a 3D fan-out structure, which may be, for example, to a memory chip component. To obtain a plurality of separate and similar 3D fan-out structures, the carrier50may be de-bonded (e.g., de-taped) from the remaining layers/components on top of the carrier50. In an embodiment, the carrier50may be removed by dissolving or etching the adhesive layer60that bonds the carrier50to the packaged components/layers. When the carrier50is de-bonded or removed, the remaining bonded layers comprise the molding compound25encapsulating the PoP dies10and the embedded chips20, the RDL30, and the BGA40.

To obtain a plurality of similar chip/die packages, a chip saw, patterned etch, laser, or the like step may then be implemented to separate the remaining bonded layers vertically along the lines between the adjacent PoP dies10. The resulting individual chip/die packages may be flipped to obtain similar PoP devices100that have the 3D fan-out structure. The resulting PoP devices100may be separately sold, shipped, used, and/or integrated in devices or other packages. The PoP devices100may be integrated in devices or other packages, where the BGA40at the bottom is used to electrically couple components of the PoP die10and the embedded chip22to other devices or packages. For instance, a PoP device100(as shown inFIG. 2h) may be placed on top of another chip package or a PCB and may be electrically coupled to multiple components through the conductive elements42of the BGA40.