Integrated circuit current metering using voltage variation detection circuit

An apparatus is disclosed, including a monitoring circuit, a translation circuit, a first filter circuit, a second filter circuit, and an interface. The monitoring circuit may be configured to receive a plurality of code values indicative of a voltage level of a power supply signal. The translation circuit may be configured to translate a particular code value to a corresponding voltage value of a plurality of voltage values. The first filter circuit may be configured to filter one or more of the plurality of voltage values to generate a plurality of filtered voltage values. The second filter circuit may be configured to generate a plurality of current values using one or more of the plurality of filtered voltage values and based on an impulse response of the power supply signal. The interface may be configured to send one or more of the plurality of current values to a functional circuit.

BACKGROUND

Technical Field

The embodiments disclosed within relate to computing systems, and more particularly, to monitoring current in an integrated circuit.

Description of the Related Art

Integrated circuits (ICs), such as, for example, systems-on-a-chip (SoCs) or processor units, may be used in various computing systems, such as, for example desktop computers, laptop computers, database servers, cloud computing servers, network switches, and the like. Power consumption of these computing systems may be monitored for various reasons. For example, power consumption of an IC in a laptop computer may be monitored to assess the IC's impact on battery life. An IC in a database or cloud computing server may be monitored to assess the IC's impact on heat generated in the server.

ICs may place variable loads on a power supply circuit providing power to the IC. As an IC transitions between periods of time of high activity and low activity, a current consumed by the IC may transition between corresponding periods of high current consumption and low current consumption. In some computing systems, current consumed by one or more ICs may be tracked and used to determine an up-to-date current load being placed on a power supply.

SUMMARY

Various embodiments of an apparatus and a method for implementing and managing a communication link are disclosed. Broadly speaking, an apparatus is contemplated in which the apparatus may include a monitoring circuit, a translation circuit, a first filter circuit, a second filter circuit, and an interface. The monitoring circuit may be configured to receive a plurality of code values indicative of a voltage level of a power supply signal included in a power distribution network of an integrated circuit. The translation circuit may be configured to translate a particular code value of the plurality of code values to a corresponding voltage value of a plurality of voltage values. The first filter circuit may be configured to filter one or more of the plurality of voltage values to generate a plurality of filtered voltage values. The second filter circuit may be configured to generate a plurality of current values using one or more of the plurality of filtered voltage values and based on an impulse response of the power supply signal. The interface may be configured to send one or more of the plurality of current values to a functional circuit.

In a further embodiment, the translation circuit may be further configured to translate the particular code value using a temperature value. In one embodiment, the apparatus may include a memory. The first filter circuit may be further configured to retrieve at least one coefficient value from the memory and filter the one or more of the plurality of reduced rate voltages using the at least one coefficient value.

In another embodiment, the first filter circuit may include a finite impulse response filter. The at least one coefficient value may be based on a cutoff frequency associated with the power supply signal. In an embodiment, the apparatus may include a memory. The second filter circuit may be further configured to retrieve data indicative of the impulse response of the power supply signal from the memory and generate the plurality of current values using the data.

In a further embodiment, the second filter circuit may include a finite impulse response filter. The data indicative of the impulse response may also be indicative of an inverse convolution relationship between the voltage level of the power supply signal and an amount of current sourced by the power supply signal. In one embodiment, the functional circuit may be configured to modify at least one operating parameter based on the subset of the plurality of current values.

DETAILED DESCRIPTION OF EMBODIMENTS

Current consumption of SoCs or processor units may be monitored for a variety of uses. For example, high current consumption may place stress on a power source or may lead to increasing temperatures of a computing system. By identifying an increase in current consumption or a high current consumption for an extended amount, a processor in a computing system may be able to adjust an operating condition to mitigate the current consumption and possibly avoid a condition that could lead to a fault in the computing system.

Current may be measured in various ways. For example, a known impedance may be included in a power supply signal's path and a voltage drop across this impedance may indicate an amount of current flowing through the path. This method, however, may require having an accurate value for the impedance in order to make accurate current measurements, and such accuracy may be costly or difficult to manufacture consistently.

Some processors are powered from a power signal from a voltage or current regulating circuit. Some regulating circuits, such as, for example, switching regulators, generate an output signal with a lower voltage level than a source signal by repeatedly coupling, and then de-coupling, an output signal node to the source signal. Each occurrence of coupling the output node to the source signal may produce a current pulse onto the output node. A power distribution circuit may generate a voltage signal from a series of the current pulses from the regulating circuit. In some embodiments, the power distribution circuit may include circuits that implement a transfer function to generate a particular voltage level based on the amount of current received via the series of current pulses. The relationship between the particular voltage level and the current pulses may be referred to as an “impulse response.” An amount of current may be determined if the transfer function of the impulse response and a voltage level are known. Embodiments disclosed herein may demonstrate systems and methods for determining a current using values of a voltage level and an inverse of a transfer function used by a voltage generation circuit.

FIG. 1illustrates a block diagram of an embodiment of a system including a system-on-a-chip (SoC), a power supply, and an impedance circuit. In the illustrated embodiment, the system includes SoC100coupled to impedance circuit111, which, in turn, is coupled to power supply109. SoC100includes power distribution network (PDN)101coupled to SoC current monitor (SCM)102. SCM102is further coupled to clock generation circuit (CGC)104and power management controller (PMC)103. SoC100further includes several functional circuits105athrough105c.

Power supply109may correspond to any suitable circuit for supplying a power signal to SoC100. In the illustrated embodiment, power supply109corresponds to a switching voltage regulator capable of providing one or more current signals with a suitable average voltage level. Switching voltage regulators may produce a current signal with a voltage level that periodically rises above and then falls below the average voltage level as a power source is switched on and off, also referred to herein as power supply “ripple.” Impedance circuit111, in the illustrated embodiment, includes components such as, for example, resistors, capacitors, and inductors that may provide some compensation for the power supply ripple. In addition, impedance circuit111may provide storage for excess charge when current demand from SoC100is low and then source the stored charge as current to SoC100when the current demand is high. Impedance circuit111may, however, slow a response time from power supply109to changes in current demand from SoC100. The slowed response time may cause voltage level drops in response to sudden increases in current consumption of SoC100, or voltage level peaks in response to sudden decreases in current consumption.

Feedback signal118is sent to power supply109from SoC100. A voltage level of feedback signal118may provide an indication to power supply109of how much current SoC100is using at a given point in time. Power supply109may then use this feedback to adjust the current signals sent to SoC100. Using feedback signal118, power supply109may be capable of maintaining an adequate amount of charge stored in impedance circuit111to prevent SoC100from being current starved, which could result in faulty operation of SoC100. Feedback signal118, may not, however, capture smaller fluctuations in current consumption in SoC100that could be useful for determining if SoC100is consuming an unsafe amount of current that could lead to a rise of die temperature to a point at which SoC fails to operate efficiently or correctly.

SoC100, in the illustrated embodiment, corresponds to an IC that includes circuits for distributing and managing power signals and clock signals to a plurality of functional circuits105a-105c(collectively referred to as105) also included in SoC100. PDN101receives at least one power signal from power supply109, via impedance circuit111. The power signal includes a current that PDN101uses to generate one or more voltage signals, including voltage signal119, for distribution throughout SoC100. PDN101distributes voltage signal119to one or more functional circuits105. The voltage level of the voltage signal119may fluctuate based on a process for generating voltage signal119from the received current as well as from changes in power consumption by functional circuits105as activity in functional circuits105that are coupled to voltage signal119change over time.

SCM102receives voltage data120from PDN101that, in the illustrated embodiment, corresponds to coded values indicative of the voltage level of voltage signal119. Values of voltage data120may be based on the voltage generation process used by PDN101to generate voltage signal119. SCM102may receive a series of these coded values that each correlate to a voltage level of voltage signal119at a particular point in time. This series of coded values is translated into a series of voltage values, which are then processed through a decimation filter, and then an inverse convolution filter to produce a series of current values that correlate to the current consumption of some or all of the circuits coupled to voltage signal119. The series of current values may reflect power consumption in SoC100over a period of time. SCM102may send one or more of the current values to PMC103, CGC104, and/or any of functional circuits105. Further details of SCM102are disclosed below.

PMC103, in the illustrated embodiment, controls power modes for various circuits in SoC100, such as, for example, functional circuits105. PMC103may determine which power mode each of functional circuits105enters. For example, PMC103may indicate that functional circuit105ais in a reduced power state, while indicating that functional circuits105band105care in active states. If functional circuit105ais needed, then PMC103may switch functional circuit105ato the active state. In some embodiments, PMC103may de-couple functional circuit105afrom the voltage signal119, thereby powering functional circuit105adown, a process referred to herein as “power gating.”

CGC104generates one or more clock signals in the illustrated embodiment and distributes the clock signals to functional circuits105. PDN101, SCM102and PMC103may also receive one or more clock signals from CGC104. In addition, CGC104may adjust a frequency of any of the one or more clock signals, reducing a frequency of a particular clock signal at times when circuits using the particular clock signal are inactive, and vice versa. Similar to PMC103, CGC104may disable or block a particular functional circuit105from receiving a clock signal when the particular functional circuit105is inactive, a process referred to herein as “clock gating.”

PMC103and CGC104may use the current values received from SCM102to determine if and when to clock gate or power gate one or more functional circuits105in response to a present level of current consumption. For example, in response to a determination that current consumption is rising to or exceeding an upper threshold of current consumption for SoC100, PMC103and/or CGC104may power gate or clock gate inactive functional circuits to allow more current to be available for active circuits. For example, SoC100may have a typical operating current of 500 milliamps (mA) with a maximum rating of 1 amp (A). An upper threshold may be set at 800 mA or 900 mA such that power gating or clock gating may be activated before the current consumption reaches the 1 A maximum rating. In other embodiments, the upper threshold may be set using other considerations, such as, e.g., an amount of current a power supply is capable of providing, or a thermal characteristic of the SoC related to current consumption. In some cases, CGC104may, instead of clock gating, reduce a frequency of clock signals to less active functional circuits105or to functional circuits105that are active but processing lower priority tasks, thereby allowing more current for higher priority tasks. In some embodiments, CGC104may reduce a frequency of signals to all functional circuits until a determination is made that the current consumption has dropped below the upper threshold.

Functional circuits105may correspond to any suitable circuits included in an SoC. For example, functional circuits105may include any combination of processor cores, cache memories, networking interfaces, memory interfaces, communication modules, and the like. Although three functional circuits are shown for clarity, any number of functional circuits may be used in various embodiments.

It is noted that the embodiment of the system illustrated inFIG. 1is merely one example. In other embodiments, different numbers and configurations of circuits are possible and contemplated.

Turning now toFIG. 2, a block diagram of an embodiment of an SoC current monitoring circuit is shown. SCM202may correspond to an embodiment of SCM102inFIG. 1. SCM202includes voltage monitor203coupled to translation circuit205, which, in turn, is coupled to low pass (LP) filter207. LP filter207is coupled to current filter209, which is then coupled to interface213. Voltage monitor203receives voltage data220as input and interface213sends current value222as output.

Similar to the description above regarding SCM102inFIG. 1, SCM202, in the illustrated embodiment, receives values, in the form of voltage data220, from PDN101. Voltage data220may include coded values indicative of a voltage level of a voltage signal generated by PDN101, such as, for example, voltage signal119. In various embodiments, voltage monitor203receives voltage data220as a serial stream of data bits, a parallel data input across multiple wires, or any suitable combination thereof. The coded values are received periodically at a particular sampling rate. For example, in one embodiment, voltage data220may provide coded values at a sampling rate of 2.2 gigahertz (GHz), or1coded sample provided approximately every 455 picoseconds (psec). Voltage monitor203provides the received coded values to translation circuit205.

In the illustrated embodiment, translation circuit205includes a memory for storing entries for converting the coded values received from voltage monitor203into voltage level values223, corresponding to voltage levels of voltage signal119. In addition to the memory, translation circuit205may also include logic circuits for receiving the coded values from voltage monitor203as well as additional data, such as environmental or operational conditions, for example, or data corresponding to a current operating temperature. Using an appropriate entry in the memory, translation circuit205produces a value representing a voltage level for each coded value received. Voltage level values223are sent to LP filter207.

LP filter207, in one embodiment, receives voltage level values223from translation circuit205and filters out values that represent high frequency changes in the level of voltage signal119. For example, a large change in the values between two or more successively received voltage level values223may correspond to a short-term switching noise or other type of noise on voltage signal119. If values for current that reflect longer term power consumption usage, rather than short term spikes in consumption, are desired, then a low pass filter may be used to attenuate short term changes and better represent longer term power usage in the SoC. LP filter may employ a particular cutoff frequency, attenuating rapid changes associated with frequencies that are higher than the cutoff frequency and, instead, returning voltage level values223corresponding to the longer-term power consumption.

In some embodiments, LP filter207may additionally be used to decimate the sampling rate of voltage data220. Continuing with the previous example in which a sampling rate of 2.2 GHz is employed, this sampling rate results in 2200 samples every microsecond. While this sampling rate may be used for some tasks, this may provide more data samples than needed for determining current consumption. Decimation of voltage level values223may include using a particular number of successive values to generate one filtered voltage level value. LP filter207generates a number of filtered voltage level values224based on a decimation factor or ratio. For every particular number of voltage level values223received, LP filter207generates one filtered voltage level value. For example, LP filter207may be designed for a decimation factor of 16, or 32, or any other suitable number. In regards to the above-referenced example, a decimation factor of 22 may be used, resulting in 100 filtered voltage level values224generated every microsecond. These filtered voltage level values224are sent to current filter209.

Current filter209, in the illustrated embodiment, receives filtered voltage level values224and generates corresponding current values222. Current filter209includes a finite impulse response (FIR) filter to generate current values222. The FIR filter uses multiple coefficients that are multiplied, one at a time, by the received filtered voltage level values224and then added to a total value. The coefficients may be determined based on several factors corresponding to the generation of voltage signal119from signals received from power supply109. For example, referring toFIG. 1, the factors may include a process used by power supply109to generate a power signal, the arrangement and values of components used in impedance circuit111, and/or a process used in PDN101to generate voltage signal119. For example, PDN101may utilize a convolution formula based on the relationship between impedance in the power signal path (e.g. impedance circuit111) and current to determine a voltage level at which to set voltage signal119. Current filter209may utilize an inverse of this convolution formula to determine a current value222for a given filtered voltage level value224and based on a known impedance. Additional details of the operation of a FIR-based current filter are disclosed later.

Current values222are sent by current filter209to interface213to be distributed to appropriate circuits. Interface213, in various embodiments, may include a wire coupled to the appropriate circuits, or may include one or more registers and a data bus interface. Each current value222may be sent to all appropriate circuits in parallel or may be address to one or more particular circuits.

The embodiment of SCM202illustrated inFIG. 2is merely an example for demonstrative purposes. Various functional circuit blocks have been omitted for clarity. In various embodiments, different functional circuit blocks may be included and are contemplated. Furthermore,FIG. 2merely illustrates logical arrangement of the various circuit blocks and is not intended to demonstrate a physical layout of the illustrated circuit blocks.

Moving now toFIG. 3, a block diagram depicting another embodiment of an SoC current monitoring circuit is shown. SCM302, similar to SCM202inFIG. 2, may correspond to an embodiment of SCM102inFIG. 1. SCM302includes voltage monitor303coupled to translation circuit305, which, in turn, is coupled to random access memory (RAM)306. Low pass (LP) filter307is coupled to RAM306, RAM308and first-in, first-out (FIFO) buffer310. Current filter309is coupled to FIFO buffer310, to RAM311and to interface313. Voltage monitor303receives voltage data320as input, translation circuit305receives temperature values321as input. Interface313sends current value322as output.

SCM302, in the illustrated embodiment, includes some similar circuits to SCM202. Similarly named and numbered circuit blocks inFIG. 3perform as described above in regards toFIG. 2, except as disclosed below. Voltage monitor303receives values, in the form of voltage data320, from a power distribution network, such as, e.g., PDN101inFIG. 1at a particular sampling rate. The values of voltage data320are passed into translation circuit305to be transformed into voltage level values323. Translation circuit305receives temperature values321from a temperature sensor elsewhere in SoC100, or external to SoC100. Based on values of a present temperature value321and voltage data320, an entry stored in translation circuit305is read. In various embodiments, the read entry may correspond to a present voltage level value323, or the read entry may be combined with the present voltage data to calculate the corresponding present voltage level value. The corresponding voltage level value is stored in RAM306.

LP filter307reads the stored voltage level values323from RAM306, as well as coefficient values325from RAM308. As described for LP filter207, LP filter307attenuates voltage level values that indicate rapid changes corresponding to a frequency greater than a cutoff frequency of LP filter307. In the illustrated embodiment, LP filter307includes a decimation filter designed to attenuate high frequency variations in voltage level values323. In addition, the decimation filter reduces a sampling rate of voltage level values by generating one filtered voltage level value324for every predetermined number of read voltage level values323. As previously disclosed herein, a decimation factor, or decimation ratio, determines how many values of voltage level values323are used to determine one value of filtered voltage level values324. In one example, a decimation ratio of 22 may be used such that 22 values of voltage level values323are used to determine one value of filtered voltage level values324. In some embodiments, the decimation filter may include multiple stages. Filtered voltage level values324may be stored into FIFO buffer310after they are generated by LP filter307.

In the illustrated embodiment, RAM308may be loaded with coefficient values325upon a power-on event or an assertion of a reset signal. Coefficient values326may remain constant, unless updated by a software or firmware update to a system memory of a computing system that includes SCM302. Coefficient values325may remain in the same location in RAM308throughout the operation of SCM302.

Current filter309, as described above for current filter209, generates current values322based on filtered voltage level values324. In the illustrated embodiment, current filter309uses a FIR filter to implement an inverse convolution function that determines current values322based on a voltage level and a known impedance value. RAM311may be used to store coefficient values326that relate to the inverse convolution function. Current filter309reads one or more filtered voltage level values324from FIFO buffer310and a corresponding number of coefficient values326from RAM311. A read coefficient may be combined with a read filtered voltage level value to generate a respective term. A number of generated terms may then be combined together to generate a current value322. For example, in one embodiment, 512 generated terms may be used to generate each current value322. Upon generating a current value322, current filter309sends the value to interface313, similar to as described above for interface213.

In the illustrated embodiment, filtered voltage level values324stored in FIFO buffer310are shifted in a memory array of FIFO buffer310after each read. For example, a first filtered voltage level value324read from location N in the memory will be written back into location N+1. Similarly, a second filtered voltage level value324read from location N−1 is written back into location N at the same time that the first filtered voltage level value324is written back into location N+1. The shifting of data occurs upon receiving a new filtered voltage level value324. The oldest filtered voltage level value324(e.g., the value that has been in FIFO buffer310for the longest amount of time and is in the last location in the memory) may be discarded upon receiving a new filtered voltage level value324. Each received filtered voltage level value324may be read and used to generate multiple terms before it is discarded.

Coefficient values326, in contrast to values in FIFO buffer310, may remain in the same location in RAM311throughout the operation of SCM302. In the illustrated embodiment, RAM311may be loaded with coefficient values326upon a power-on event or an assertion of a reset signal. Similar to coefficient values325, coefficient values326may remain constant unless updated through a software or firmware update to a system memory.

The example depicted inFIG. 3is merely one embodiment. In other embodiments, additional circuit blocks may be included. The illustrated circuit blocks may be arranged in another order in some embodiments.

Turning toFIG. 4, a block diagram of an embodiment of an inverse convolution filter is illustrated. In various embodiments, inverse convolution filter400may be included in current filter209or309, inFIGS. 2 and 3, respectively. Inverse convolution filter400includes FIFO buffer410, including portions410aand410b, and coefficient storage (coeffs)412, including portions412aand412b. Both FIFO buffer410and coefficient storage412are coupled to multipliers413aand413b. Multipliers413aand413bare coupled to adders414aand414b, which are respectively coupled to summation registers (sum)415aand415b. Both summation registers415aand415bare coupled to adder416, which, in turn, is coupled to current data register417. Inverse convolution filter400receives filtered voltage level values424from a source such as LP filter307in SCM302ofFIG. 3. Inverse convolution filter generates current values422as an output.

In the illustrated embodiment, inverse convolution filter400receives filtered voltage level values424and determines current values422based on one or more of the received values and coefficient values stored in coefficient storage412. Operations performed by, and the coefficients used by, inverse convolution filter400are based on a process used to generate a power supply signal, such as, for example, voltage signal119inFIG. 1, that is generated by PDN101. As previously described, PDN101generates voltage signal119from current signals received from power supply109via impedance circuit111. Power supply109uses feedback from SoC100to adjust the provided current signal supplied to SoC100, thus creating a cyclic process that results in current signal fluctuations. To mitigate fluctuations in voltage level on voltage signal119, PDN101uses a transfer function for generating voltage signal119based on the received current from power supply109. Using an inverse of this transfer function, a value for current may be generated based on a determined voltage level.

The transfer function used by PDN101may be represented in the time domain by equation 1.
v(t)=i(t)*h(t)  (1)

In equation 1, “v” represents voltage, “i” represents current, “t” represents time and “h” represents the transfer function. To determine current based on a known voltage value, equation 1 is solved for i(t), as shown in equation (2).
i(t)=v(t)*h−1(t)  (2)

To determine current, therefore, h−1(t), i.e., the inverse transfer function, is calculated. To determine current using the inverse transfer function at a given point in time, a differentiation operation may be used. To simplify calculations, the time domain functions may be replaced by matrix domain functions. The inverse transfer function may be expressed as a circular, square N×N convolution matrix, H[T]. Similarly, voltage and current may be expressed as 1×M matrix vectors, V[T] and I[T], respectively. Substituting these matrix domain functions into equation 2 results in equation 3.
I[T]=V[T]*H−1[T]  (3)

Determining a current vector, I[T], in the matrix domain, therefore, involves multiplying a determined voltage vector, V[T], by a matrix of the inverse transfer function, H−1[T]. This is approximately equivalent to de-convolution of the voltage with impulse response. Since the inverse transfer matrix is of a circular, square form, the coefficients of a given row or column of H−1[T] may correspond to coefficients of a finite impulse response (FIR) filter. Convolving this FIR filter with a series of time-based voltage level values can determine corresponding current values.

In the illustrated embodiment, filtered voltage level values424received from LP filter307are stored in FIFO buffer410. The values stored in FIFO buffer410represent V[T] from equation 3. Coefficients corresponding to H−1[T] are stored in coefficient storage412. To determine I[T], each filtered voltage level value424is multiplied by a subset of the coefficients, one at a time, and added together. To increase the speed of the calculations, inverse convolution filter400divides FIFO buffer410and coefficient storage412in half, such that filtered voltage level values424stored in FIFO buffer410aare multiplied by coefficients stored in coefficient storage412aand filtered voltage level values424stored in FIFO buffer410bare multiplied by coefficients stored in coefficient storage412b. Multiplier413amultiplies values from FIFO buffer410aby coefficients from coefficient storage412a. The product is added to summation register415aby adder414a. A similar process is performed in parallel to values from FIFO buffer410band coefficient storage412busing multiplier413b, adder414band summation register415b. Values in summation registers415aand415bare then added together by adder416and stored in current data register417. Current data register417provides the stored value as current values422.

In various embodiments, FIFO buffer410and/or coefficient storage412may be included as part of inverse convolution filter400or separate from inverse convolution filter400as part of an SoC current monitoring circuit such as SCM302inFIG. 3. Inverse convolution filter400may receive a clock signal (not shown) to synchronize the operations performed on the values in FIFO buffer410and coefficient storage412.

It is noted thatFIG. 4is merely one example embodiment. In other embodiments, additional circuits may be included.FIG. 4is not intended to represent a physical arrangement of the illustrated circuits, merely a logical presentation.

Moving toFIG. 5, a flowchart for an embodiment of a method for operating an SoC current monitoring circuit is shown. Method500may be applicable to an SoC current monitoring circuit, such as SCM202or SCM302inFIGS. 2 and 3, respectively, used to monitor current in an SoC such as SoC100inFIG. 1. Referring collectively toFIG. 1,FIG. 3, and method500ofFIG. 5, the method may begin in block501.

Code values that are based on a power signal are received (block502). In the current embodiment, a monitoring circuit, such as, for example, voltage monitor303, receives a plurality of code values that each indicates a voltage level of the power signal at a particular point in time. The plurality of code values may be received from a power distribution network, such as, for example, PDN101inFIG. 1. PDN101may generate the code values based on a process for generating a voltage signal for providing power to circuits in an SoC.

Code values are translated into voltage values (block504). In the illustrated embodiment, the code values received by voltage monitor303are used to access entries in translation circuit305. Each code value may have a respective entry in a memory in translation circuit305that corresponds to a particular voltage level. In some embodiments, translation circuit305may include additional entries for each code value. One entry may be selected based on a combination of the code value and an operating condition, such as, for example, a value from a temperature sensor.

The voltage values are filtered (block506). The code values received by voltage monitor303may be received at a particular rate, corresponding to a sampling rate. The code values may be translated into voltage values at the same rate, using translation circuit305. In the illustrated embodiment, the sampling rate of the voltage values may be reduced, or decimated, by using LP filter307to generate one decimated voltage value based on a number of voltage values from translation circuit305. The number of voltage values used may be any suitable number, such as, for example, any number from 16 to 32. In such an embodiment, one decimated voltage value may be generated for every 32 voltage values from translation circuit305. LP filter307, in addition to decimating the voltage values, may filter the voltage values to attenuate high frequency changes in the voltage values, and thereby generating filtered voltage values. Sudden changes between two or more consecutive voltage values may be indicative of noise on the voltage signal. LP filter307attenuates such noise spikes so the longer-term power consumption of SoC100may be determined by SCM302.

Current values are generated from the filtered voltage values (block508). In the illustrated embodiment, current filter309receives the filtered voltage values from LP filter307and generates current values indicative of a current consumed in SoC100. To determine current values from the filtered voltage values, current filter309may include an inverse convolution filter, such as inverse convolution filter400inFIG. 4. As described above, inverse convolution filter400may utilize coefficients whose values are based on the generation of voltage signal119by PDN101. The coefficients may correspond to an inverse of a transfer function used to generate voltage signal119based on a current signal from a power supply. By applying these coefficients to the filtered voltage values, current values may be determined.

The current values are sent to at least one functional circuit (block510). The current values generated by current filter may be sent to an interface such as interface313. Interface313may be coupled to one or more functional blocks, for example, via a data bus. In some embodiments, interface313may include a register that may be accessed by the one or more functional circuits to retrieve a current value. The one or more functional circuits may utilize one or more of the current values to adjust an operating parameter, such as, for example, a frequency of a clock signal or level of a voltage signal. The method may end in block511.

It is noted that method500ofFIG. 5is merely an example. Variations of the disclosed method are possible. For example, different numbers and different orders of the presented blocks may be employed. For example, in other embodiments, operations in blocks506and508may be in reverse order or may be completed in parallel.

Turning now toFIG. 6, a flowchart for an embodiment of a method for operating an inverse convolution filter is depicted. Method600may correspond to operations performed in block510of method500inFIG. 5. The operations of method600may be applicable to an inverse convolution filter, such as inverse convolution filter400inFIG. 4that may be used in an SoC current monitoring circuit such as SCM302inFIG. 3, which is included in an SoC such as SoC100inFIG. 1. Referring collectively to SoC100ofFIG. 1, inverse convolution filter400ofFIG. 4, and method600, the method may begin in block601.

Coefficient values are determined based on power supply characteristics (block602). In the illustrated embodiment, coefficients corresponding to a matrix of an inverse transfer function, such as shown above in equation 3. PDN101generates voltage signal119based on a current signal from power supply109using a transfer function that approximates the current signal as an impulse response. The coefficient values may be determined by calculating an inverse of this transfer function. The calculation of the coefficient values may occur during a design of SoC100based on simulations, or, in other embodiments, may be determined from empirical data collected on manufactured devices during testing or evaluation of SoC100. During operation of SoC100, the coefficient values are stored in a memory such as, for example, RAM311or coefficient storage412.

A coefficient value and a filtered voltage level data value are read (block604). In one embodiment, LP filter307filters voltage level values323, and stores the values in FIFO buffer310as filtered voltage level values324. In some embodiments, FIFO buffer310may correspond to FIFO buffer410inFIG. 4. Inverse convolution filter400reads a particular one of filtered voltage level values324from FIFO buffer410, as well as a particular coefficient value from coefficient storage412. If the particular filtered voltage level value324is read from FIFO buffer410a, then the particular coefficient value is read from coefficient storage412a, and vice versa if the particular filtered voltage level value324is read from FIFO buffer410b.

A term is generated based on the read coefficient and the read filtered voltage level data value (block606). In the illustrated embodiment, inverse convolution filter400multiplies the particular coefficient value and the particular filtered voltage level value324using either multiplier413aor413b. For example, if the values are read from FIFO buffer410band coefficient storage412b, then multiplier413bgenerates a product of the two values. The generated product is then added to summation register415busing adder414b.

The generated term is added to a sum (block608). Continuing the example from above, inverse convolution filter400adds the generated term stored in sum415bto another generated term stored in summation register415aand stores the value in current data register417. In various embodiments, each of summation registers415aand415bmay include the addition of a number of filtered voltage level values324multiplied by respective coefficients before being added and stored in current data register417as one of current values422.

The read filtered voltage level data value is stored in a next address in FIFO buffer410(block610). Inverse convolution filter400, in the illustrated embodiment, stores the particular filtered voltage level value324back into FIFO buffer410at a subsequent address to the address that the particular filtered voltage level value324was read from. Each value read from FIFO buffer410is shifted through addresses in FIFO buffer410such that each filtered voltage level value324may be multiplied by a different coefficient value each time it is read from FIFO buffer410. A filtered voltage level value324read from a last address in FIFO buffer410amay be stored back into a first address in FIFO buffer410b, allowing, in some embodiments, each filtered voltage level value324to be multiplied by each coefficient stored in coefficient storage412aand412b. The method ends in block611.

Method600ofFIG. 6is merely an example. In other embodiments, different operations and different numbers of operations are possible and contemplated. Operations may be performed in a different order and, in some embodiments, may be performed in parallel.