Circuit having integrated heating structure for parametric trimming

An integrated circuit (IC) includes a heated portion. The heated portion/IC includes a substrate having a topside semiconductor surface having circuitry configured to provide a circuit function. A pre-metal dielectric (PMD) layer is on the topside semiconductor surface. A metal interconnect stack is on the PMD. A trim portion includes one or more temperature sensitive circuit components which affect a temperature behavior of the IC. The heated portion extends over and beyond an area of the trim portion having an integrated heating structure including at least a first heater formed from a metal interconnect level that includes a first plurality of winding segments which have a varying pitch. A heat spreader formed from a second metal interconnect layer is between trim portion and the first heater. Thermal plugs are lateral to the temperature sensitive circuit components and thermally couple the heat spreader to the topside semiconductor surface.

FIELD

Disclosed embodiments relate to the field of integrated circuits having integrated heaters for parametric trimming.

BACKGROUND

Multi-temperature trimming of an integrated circuit (IC) device at wafer test, final test, or in the field application can be achieved by using an integrated (on-chip) heater to introduce a temperature rise over a specific area of the substrate (e.g., silicon). For example, one IC device that may be trimmed comprises a precision analog device, such as voltage reference or analog to digital converter (ADC), which comprises both passive devices (resistors, capacitors) and active devices (e.g., transistors) configured to provide the desired circuit function.

However, with known multi-temperature parametric trimming methods, the temperature both across the heated region above the substrate (e.g., thin film resistors or polysilicon resistors within a dielectric) and in the heated region within the substrate (e.g., transistors or diffused resistors on silicon) below can both have a significantly non-uniform temperature distribution. Moreover, there can be a significant temperature differential between the heated region above the substrate where the thin film resistors or polysilicon resistors reside and in the substrate where active devices (e.g., transistors) and passive devices (e.g., diffused resistors) reside. When trimming the IC device to minimize its temperature dependence, non-uniform temperature distributions introduce trimming errors, preventing the IC from being trimmed to a more optimal operating point, thus limiting the obtainable level of precision of the IC device.

SUMMARY

Disclosed embodiments include integrated circuits (ICs) having an integrated heating structure including at least one heater, a heat spreader, and thermal heat plugs which thermally couple the heat spreader to the topside semiconductor surface (e.g., silicon) of the substrate. The heating structure is over a portion of the IC referred to herein as the “heated portion”. The heater(s) include a varying feature (e.g., segment) pitch. The varying pitch provides a non-uniform-surface power profile, which provides a more uniform temperature profile in the heated portion of the IC during heated parametric trimming operations.

One or more temperature sensitive circuit components which affect the temperature behavior of the IC are in a trim portion. The area of the heater and heat spreader of the heated portion extends over and beyond the area of the trim portion. The integrated heating structure can be used to heat the temperature sensitive circuit components in the trim portion during parametric trimming, where the temperature sensitive circuit components may include precision analog components that comprise both passive and active devices.

Disclosed ICs provide a more uniform temperature profile across the heated portion above the substrate, in the heated portion within the substrate below, and between the heated portion above the substrate and the heater. Such ICs reduce trimming errors, allowing disclosed ICs to be trimmed to a more optimal operating point, thus improving the obtainable level of precision of disclosed IC devices. Multi-temperature trimming can also now be performed with a more uniform temperature rise that more closely matches an externally induced temperature rise, providing a better environment for low-cost trimming for improved temperature performance of disclosed ICs.

One disclosed embodiment comprises an IC including a substrate having a topside semiconductor surface with active circuitry and passive circuitry configured to provide a circuit function, such as a voltage reference, for example. A pre-metal dielectric (PMD) layer is on the topside semiconductor surface. A metal interconnect stack is on the PMD layer including metal interconnect levels having inter-level dielectric layers (ILDs) therebetween. A trim portion includes one or more temperature sensitive circuit components which affect the temperature behavior of the IC. The heated portion extends over and beyond an area containing the trim portion having an integrated heating structure including at least a first heater formed from a metal interconnect level that includes a first plurality of winding segments which have a varying pitch. A heat spreader formed from a second metal interconnect layer is between the trim portion and the first heater. Thermal plugs are lateral to the temperature sensitive circuit components which thermally couple the heat spreader to the topside semiconductor surface.

An operating point of the IC can be permanently programmed (changed) to significantly reduce parametric temperature drift by application of heat provided by a disclosed heating structure when biased. More uniform heating provided by disclosed integrated heating structures is applicable to any component in the trim portion residing in the IMD or in the substrate region below the heater. The components in the IDM can be one or more of resistors of film (e.g., polysilicon, SiCr, NiCr) or metal (e.g., aluminum or copper), as well as capacitors (which can be metal or metal-TiN types), or inductors. The components in the substrate can include all varieties of resistor, silicon controlled rectifiers (SCRs), bipolars, metal-oxide-semiconductor field-effect transistors (MOSFETs), varactors, opto-electronic devices, and hall devices, for example.

DETAILED DESCRIPTION

FIG. 1Ais a cross-sectional depiction of a portion of an IC referred to as a heated portion100which includes an example integrated heating structure for heating active and passive circuit trim components in a trim portion101that is within the heated portion100during parametric trimming, according to an example embodiment. The trim portion101includes temperature sensitive circuit components. Heated portion100includes a substrate105having a topside semiconductor surface106shown as a p-epi layer including circuitry configured to provide a circuit function shown as simply an npn bipolar transistor110which can be any active device and passive circuitry shown as semiconductor (nwell) resistors109. A PMD layer111is on the topside semiconductor surface106. The substrate105can comprise silicon, silicon-germanium, or another substrate that provides a topside semiconductor surface106. Although no isolation structure is shown, disclosed ICs can include junction isolation or dielectric isolation.

A metal interconnect stack130is on the PMD layer111and comprises a plurality of metal interconnect levels shown as metal 1 (M1), metal 2 (M2) and metal 3 (M3) having interlevel dielectric (ILD) layers therebetween. The . . . shown inFIG. 1Aindicates the possible presence of additional metal interconnect levels. ILD122is between M1 and M2, and ILD123is between M2 and M3. Disclosed ICs can have as few as 2 metal interconnect levels, or up to 7, 8, or more metal interconnect levels. In a 2 metal level embodiment, a heater and a heat spreader can be placed over IMD resistors, such as polysilicon resistors, where the metallic connections to the ends of the resistors are made outside of the heated portion.

Trim portion101includes at least one temperature sensitive circuit component configured for trimming shown as trim resistors126aand126bpositioned above the PMD layer111and connected as part of the IC. The trim resistors126aand126bcomprise the circuitry that can be controlled to permanently alter the electrical resistance during the application of heat generated by disclosed heaters when biased, such as the first heater135described below. The materials for trim resistors126a,126bcan comprise doped polysilicon or other thin film resistor materials, such as metal, for example, high-sheet resistance metal-silicon layers, for example, silicon plus chromium (SiCr). In addition, the temperature sensitive circuit component for trimming can reside in the IMD and include capacitors which can be metal to metal capacitors as well as M1-TiN capacitors. Heated portion100generally also includes resistors formed in the topside semiconductor surface106, such as n+ or p+ diffused resistors, shown as nwell resistors109inFIG. 1A.

At least a first heater135is formed from a first of the metal interconnect levels shown inFIG. 1Aas M3. The first heater135comprises a first plurality of winding segments which have a varying pitch (seeFIG. 2Afor an example first heater layout that shows varying the metal pitch of the segments) which extend over, and fully enclose (i.e. extend over) the trim resistors126aand126b, active circuitry including the npn bipolar transistor110, and nwell resistors109as shown inFIG. 1Ato allow more uniform heating of these circuit elements which are part of temperature sensitive circuitry. In one particular embodiment the first heater135comprises a circular (concentric element) structure.

Heated portion100also includes a heat spreader140formed from a second of the plurality of metal interconnect layers shown as formed from M2 positioned between the trim resistors126a,126band the first heater135. Heat spreader140generally comprises a single metal sheet (or plate). Heated portion100also includes a plurality of thermal plugs143lateral to the trim resistors126a,126bwhich provide thermal coupling between the heat spreader140and the topside semiconductor surface106.

The inclusion of heat spreader140coupled to thermal plugs143provides efficient heat transfer to the topside semiconductor surface106reducing overall thermal time-constants during heating. Some thermal plugs143can be seen to provide direct thermal contact between the heat spreader140and the topside semiconductor surface106. Thermal plugs143can comprise vias in the PMD layer111filled with metal. In one embodiment, the thermal plugs143comprise tungsten filled vias.

In one embodiment the heat spreader140is both thermally and electrically connected via the thermal plugs143to the substrate by connection to the topside semiconductor surface106. Connection to the substrate will typically cause the Faraday shield to assume a ground potential, but in other embodiments the thermal plugs may be connected to other substrate regions so other (non-zero) Faraday shield voltages may be realized. For thermal coupling reasons, thermal plugs143can provide a continuous encirclement for the passive and active component that resides in the trim portion101.

The first heater135is electrically floating. During heating operations, however, first heater135will be connected to a power source, via a switch. The heat spreader140and thermal plugs143can be floating, but also can be connected to a circuit ground. When the heat spreader140and thermal plugs143are configured in a Faraday shield arrangement, connecting the heat spreader140and thermal plugs143to the circuit ground allows enclosure of the temperature sensitive circuit components in the trim portion101in a grounded Faraday shield. Shielding eliminates undesirable capacitive coupling from the first heater135or heater(s), which will have a switched voltage, to the temperature sensitive circuit components in trim portion101during trimming.

Although not shown, as noted above, the IC associated with heated portion100can include a switch structure to allow switchably coupling a power source to turn the first heater135on and off when desired to control heating of the heated portion100. The switch structure can be on the same die as the IC, or external to IC.

FIG. 1Bis a cross-sectional depiction of a heated portion150of an IC including an integrated heating structure comprising a first heater135and a second heater136for heating active and passive circuit components in a trim portion within the heated portion during parametric trimming, according to an example embodiment. Heated portion150has a metal interconnect stack130aon the PMD layer111and comprises a plurality of metal interconnect levels shown as metal 1 (M1), metal 2 (M2), metal 3 (M3) and metal 4 (M4), having ILD layers therebetween shown as ILD122between M1 and M2 and ILD123between M2 and M3 and ILD124between M3 and M4. First heater135is shown formed from M3 and second heater136is shown formed from M4. SeeFIG. 2Bfor an example second heater layout that shows varying the metal pitch of the heater segments.

FIG. 2Ashows an example heater200having an example metal pattern including a plurality of winding segments with varying segment pitch which can be used for the first heater135shown inFIG. 1A, according to an example embodiment. IINand IOUTrepresent the locations current is forced into heater200and out from heater200, respectively, when biased during heated trimming operations. The pitch (center-to-center spacing) between adjacent horizontally oriented segments can be seen to be at a minimum at the top and bottom of heater200, a maximum at the center of heater200, with the segment pitch linearly decreasing from the center to both the top and the bottom of heater200. The maximum segment spacing can be seen to be at least two (2) times the minimum segment spacing.

Disclosed segment pitch variations can be other than linearly variations. The pitch variation is generally a decreasing function of distance from the heater edge. A linear function has been found to work well and its slope is easily determined. More complicated functions can also be used, for example a parabola, or an exponential. The optimum values of the coefficients for these functions could be determined analytically or numerically. The optimum values would be those that minimize the variation of temperature over the distance from heater edge to heater center. An arbitrary function is also possible and its form can be determined by the method of calculus of variations.

FIG. 2Bshows an example heater250having an example metal pattern including a plurality of winding segments with varying pitch which can be used for the second heater136shown inFIG. 1B, according to an example embodiment. The pitch (center-to-center spacing) between adjacent vertically oriented segments can be seen to at a minimum at the left and right of heater250, a maximum at the center of heater250, with the segment pitch linearly decreasing from the center to both the left and right of heater250. As with heater200, disclosed segment pitch variations can be other than linearly variations.

The stacking of heater200and heater250can be seen to provide orthogonal heaters. As defined herein the orthogonal condition is where the segments in the respective heaters are oriented 90°±10° relative to each other (80 to 100 degrees). The orthogonal condition has been found to provide the best heating uniformity in the case of two stacked heaters200and250. Other embodiments include 3 stacked heaters at about 60 degree increments relative to one another and 4 stacked heaters at about 45 degree increments relative to one another. Stated generally, the plurality (N) of stacked heaters can be angled at 180°/N±10° relative to one another.

FIG. 3illustrates a high level depiction of a construction of an IC300into which one or more disclosed integrated heating structures may be incorporated to heat portions of the IC such as heated portion100shown inFIG. 1Athat include a trim portion101therein having temperature sensitive circuit components, according to an example embodiment. Trim portion101is shown including a passive components sub-portion101a, an active components sub-portion101b, and passive and an active components sub-portion101c.

For example, IC300can comprise a precision analog device (e.g., a voltage reference or analog to digital converter). IC300includes circuitry324configured to provide a circuit function, which realizes and carries out desired functionality of IC300, such as that of an analog IC. The capability of circuitry324provided by IC300may vary, for example ranging from a simple device to a complex device. The specific functionality contained within circuitry324is not of importance to disclosed embodiments.

FIG. 4provides temperature rise on the vertical axis in ° C. vs. lateral distance in μm from the center of the heater for a disclosed single variable pitch heater and a single uniform pitch heater, both 212 ohms, that demonstrates disclosed variable pitch heaters improve lateral temperature uniformity. The temperature rise is based on a calculated Rth (° C./W) and 1 Watt of applied power to the 212 ohm heater.

FIG. 5provides temperature rise on the vertical axis in ° C. vs. vertical distance in μm from the center of the heater for a disclosed first and second variable pitch heater oriented orthogonal to one another and a first and second uniform pitch heater, with each heater being 212 ohms, that demonstrates disclosed variable pitch heaters improves vertical temperature uniformity. The temperature rise is based on 1 Watt of applied power to the 212 ohm heaters. In general, the heater size (area) should be large enough to cover the trim portion that is to achieve the temperature rise. The temperature rise should be large enough so that it is easily distinguishable against the thermal noise background. The temperature rise and heater size determine the required power. The heater resistance can be adjusted to be compatible with the required power, circuit voltage levels, and available control elements.

FIGS. 6 and 7are contour maps of temperature rise. A normalization factor was applied to the x and y axes by software. The contour lines are lines of constant temperature rise. The curves are traced out as x and y are varied and the temperature rise is held constant. The vertical and horizontal axes in bothFIGS. 6 and 7represents distance. For example, the vertical axis inFIGS. 6 and 7is the same as the horizontal axis inFIG. 5, where the temperature is plotted vs. vertical distance.

FIG. 6is a contour map of temperature rise provided by disclosed first and second variable pitch heaters oriented orthogonal to one another.FIG. 7is a contour map of temperature rise provided by first and second fixed pitch heaters oriented orthogonal to one another. A comparison of the contour data inFIG. 6to that ofFIG. 7evidences disclosed first and second variable pitch heaters provide a significant improvement in temperature uniformity as compared to first and second fixed pitch heaters by providing a smaller temperature variation.

As described above, disclosed embodiments vary the pitch of the metal segments of the heaters, across the trim portions of the IC containing the temperature sensitive circuit components. Addition of disclosed heat spreaders and thermal plugs augment uniform heating of the trim area by the heaters and reduce the overall thermal time-constants which allow more uniform heating of temperature sensitive circuit components, such as resistor components in the ILD (thin film resistors/polysilicon resistors) and those in the topside semiconductor surface (e.g., silicon). No additional mask layers are required to implement disclosed integrated heating structures.

Disclosed integrated heating structures are expected to have a broad range of applications that can benefit from internally induced, rapid, and uniform temperature rises within an area of temperature sensitive circuitry, since they can replace known costly, multi-point production temperature trim with low-cost, room temperature production trim and meet the same parametric performance. For example, ICs requiring accurate, temperature stable, current, voltage or resistance can benefit from disclosed embodiments.

Disclosed embodiments can be integrated into a variety of assembly flows to form a variety of different semiconductor IC devices and related products. The assembly can comprise single semiconductor die or multiple semiconductor die, such as PoP configurations comprising a plurality of stacked semiconductor die. A variety of package substrates may be used. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, CMOS, BiCMOS and MEMS.

Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.