IMAGE SENSOR NEGATIVE SUPPLY CHARGE PUMP TIMING

An Image sensor includes image sensor cells, each configured to accumulate charge corresponding to light incident thereon, a first driver connected to a power supply node, where the first driver generates control signals for a first image sensor cell based on a voltage of the power supply node, where the first image sensor cell generates an image signal in response to the control signals, and the image signal is based on the accumulated charge of the first image sensor cell. The image sensor also includes an ADC generating a digital representation of the image signal, and a switching voltage generator selectively generating the voltage of the power supply node in response to an enable signal, where the enable signal causes the switching voltage generator to not generate the voltage of the power supply node while the image signal is generated.

TECHNICAL FIELD

The subject matter described herein relates to image sensors, and more particularly to image sensors having low read noise.

BACKGROUND

Image sensor performance is affected by resolution of ADCs used to convert sensed data voltages to digital signals. Circuit techniques for implementing compact ADCs is needed in the art.

SUMMARY

One inventive aspect is an image sensor. The Image sensor includes a plurality of image sensor cells, each configured to accumulate charge corresponding to light incident thereon, a first driver connected to a power supply node, where the first driver is configured to generate one or more control signals for a first image sensor cell based on a voltage of the power supply node, where the first image sensor cell is configured to generate an image signal in response to the control signals, and where the image signal is based on the accumulated charge of the first image sensor cell. The image sensor also includes an analog to digital converter (ADC), configured to receive the image signal of the first image sensor cell and to generate a digital representation of the image signal, and a switching voltage generator configured to selectively generate the voltage of the power supply node in response to an enable signal, where the enable signal causes the switching voltage generator to not generate the voltage of the power supply node while the image signal is generated.

In some embodiments, the voltage of the power supply node is less than a ground voltage.

In some embodiments, the enable signal causes the switching voltage generator to generate the voltage of the power supply node while the first image sensor cell is reset.

In some embodiments, resetting the first image sensor cell includes discharging a capacitance storing previously accumulated charge.

In some embodiments, the first image sensor cell is configured to additionally generate an initialization image signal for the ADC, where the ADC is configured to receive the initialization image signal from the first image sensor cell and to generate a digital representation of the initialization image signal.

In some embodiments, the enable signal causes the switching voltage generator to not generate the voltage of the power supply node while the initialization image signal is generated.

In some embodiments, during a first period of time the first image sensor cell generates the initialization image signal and the image signal, and a number of other image sensor cells generate other initialization image signals and other image signals, and during a second period of time the enable signal causes the switching voltage generator to generate the voltage of the power supply node.

In some embodiments, the second period of time follows the first period of time.

In some embodiments, the first and second periods of time are sequentially repeated.

In some embodiments, the enable signal causes the switching voltage generator to generate the voltage of the power supply node during a time when the first image sensor cell is not reset, does not generate the image signal, and does not generate the initialization image signal.

Another inventive aspect is a method of using an image sensor. The method includes, with each of a plurality of image sensor cells, accumulating charge corresponding to light incident thereon, with a first driver connected to a power supply node, generating one or more control signals for a first image sensor cell based on a voltage of the power supply node, and, with the first image sensor cell, generating an image signal in response to the control signals, where the image signal is based on the accumulated charge of the first image sensor cell. The method also includes, with an analog to digital converter (ADC), receiving the image signal of the first image sensor cell, and generating a digital representation of the image signal, and, with a switching voltage generator, generating the voltage of the power supply node in response to an enable signal, where the enable signal causes the switching voltage generator to not generate the voltage of the power supply node while the image signal is generated.

In some embodiments, the voltage of the power supply node is less than a ground voltage.

In some embodiments, the enable signal causes the switching voltage generator to generate the voltage of the power supply node while the first image sensor cell is reset.

In some embodiments, resetting the first image sensor cell includes discharging a capacitance storing previously accumulated charge.

In some embodiments, the method also includes, with the first image sensor cell, generating an initialization image signal for the ADC, and with the ADC, receiving the initialization image signal from the first image sensor cell and generating a digital representation of the initialization image signal.

In some embodiments, the enable signal causes the switching voltage generator to not generate the voltage of the power supply node while the initialization image signal is generated.

In some embodiments, during a first period of time the first image sensor cell generates the initialization image signal and the image signal, and a number of other image sensor cells generate other initialization image signals and other image signals, and during a second period of time the enable signal causes the switching voltage generator to generate the voltage of the power supply node.

In some embodiments, the second period of time follows the first period of time.

In some embodiments, the first and second periods of time are sequentially repeated.

In some embodiments, the enable signal causes the switching voltage generator to generate the voltage of the power supply node during a time when the first image sensor cell is not reset, does not generate the image signal, and does not generate the initialization image signal.

DETAILED DESCRIPTION

Particular embodiments of the invention are illustrated herein in conjunction with the drawings.

Various details are set forth herein as they relate to certain embodiments. However, the invention can also be implemented in ways which are different from those described herein. Modifications can be made to the discussed embodiments by those skilled in the art without departing from the invention. Therefore, the invention is not limited to particular embodiments disclosed herein.

Circuit features of image sensor circuits providing high resolution image read data are described herein with reference to certain embodiments. Some of the features are illustrated in the figures. For example, the figures illustrate TX drivers and their negative supply connection system which drive the image cells of the array. The TX drivers have their negative supplies selectably connectable to each of three negative supplies. The negative supply connectability allows for negative supply connection management resulting in improved noise isolation performance.FIG. 1is a schematic diagram of an embodiment of an image sensor array.FIGS. 2-5illustrate a sensor array cell, its TX drivers, their negative supply connection operation to isolate noise.FIG. 6illustrates a timing relationship between operation of a negative voltage charge pump and a read period.

FIG. 1is a schematic diagram of an embodiment of an image sensor array100. Image sensor array100includes four image sensor cells110, row reset buffers120, row read buffers130, and ADCs140. Image sensor array100is an example only. Image sensor arrays having different features may alternatively be used.

Each of the image sensor cells110includes a photodiode, one or more switches configured to selectively receive signals from the row reset and row read buffers connected thereto. In response to the received signals, the switches cooperatively cause each of the image sensor cells110to accumulate charge with a storage capacitance according to an amount of light incident thereon, to deliver an image data signal to the one of the ADCs140based on the accumulated charge, to initialize the input of one of the ADCs140, and to initialize the charge storage capacitance.

The ADCs140are configured to generate digital words corresponding with the analog voltage at their respective input nodes. Accordingly, the digital words generated by the ADCs correspond with and are a digital representation of the charge accumulated by the image sensor cells110.

The charge stored in the image sensor cells110is a result of accumulated charge conducted by the respective photodiodes, as understood by those of skill in the art, between a time when the charge storage capacitance of image sensor cells110are initialized and a time when the image data signal is received by one of the ADCs140.

The rows of image sensor cells110are successively read, and the digital words generated by the ADCs140are successively stored in a memory (not shown) to generate image data representing an image sensed by the entire sensor array100, as understood by those of skill in the art. Furthermore, image data representing multiple images may be successively sensed by the sensor array100, and stored in the memory.

FIG. 2is a schematic diagram of an embodiment of an image sensor array cell200connected to peripheral circuitry. The image sensor array cell includes photodiode210, Access transistor220, reset transistor230, source follower transistor240, and ADC transistor250. The peripheral circuitry includes ADC260, reset driver235, TX driver225, and row select driver255.

FIG. 3is a timing diagram illustrating functionality of the image sensor array cell ofFIG. 2.

During time T1, the data node of phototransistor210is reset. Time T1may be considered a cell reset time, during which the data node of each of the image sensor array cells in a particular row of an image sensor is reset.

During time T1, reset driver235causes the reset node to be high, and TX driver225causes the TX node to be high. The voltage value of the high voltage at the TX node may, for example, be positive, and greater than a ground voltage. In addition, the row select driver255causes the row select node to be low. Because the row select node is low, ADC transistor250is not conductive, and the ADC input node is isolated from activity occurring within the image sensor array cell.

During time T1, in response to the reset node being high, reset transistor230is conductive. In addition, in response to the TX node being high, the access transistor220is conductive. Because the reset transistor230is conductive the voltage at node FD is equal to the voltage of the power supply node connected to the drain of reset transistor230. In addition, because the access transistor220is conductive, the voltage at the data node of the phototransistor210is also equal to the power supply voltage (Vdd).

At the end of time T1, reset driver235causes the reset node to be low, and TX driver225causes the TX node to be low. The voltage value of the low voltage at the TX node may, for example, be negative, less than the ground voltage. In response to the reset node being low, reset transistor230is nonconductive, and in response to the TX node being low, access transistor is nonconductive. In some embodiments, at the end of time T1, reset driver235does not cause the reset node to be low, and reset transistor230remains conductive.

Because at least access transistor220is nonconductive, the data node of phototransistor210is no longer held at the power supply voltage. As understood by those of skill in the art, photodiode210conducts charge according to the light it receives. Accordingly, starting with the end of time T1, the voltage at the data node of phototransistor210is reduced by photodiode210according to the light received by photodiode210.

During time T2, the ADC input node is reset. Time T2may be considered an ADC reset or zero or initialization time, during which the ADC input nodes of the image sensor are reset or initialized or zeroed to a starting value as part of or in preparation for a read operation for reading data from the pixels of a particular row of the image sensor.

During time T2, the reset driver235causes the reset node to be or to remain high, and the row select driver255causes the row select node to be high. In addition the TX driver225causes the TX node to be low. Because the TX node is low, access transistor220is not conductive, and the data node of the phototransistor210is isolated from activity occurring within the image sensor array cell.

During time T2, in response to the reset node being high, reset transistor230is conductive. In addition, in response to the row select node being high, the ADC transistor250is also conductive. Because the reset transistor230is conductive, the voltage at node FD is equal to the power supply voltage. Because the voltage at node FD is equal to the power supply voltage, source follower transistor240is conductive.

Because both source follower transistor240and ADC transistor250are conductive, source follower transistor240and ADC transistor250conduct charge from the power supply connected to the drain of source follower transistor240to the ADC input node. In response, the voltage at the ADC input node approaches a value equal to the power supply voltage minus a threshold voltage value Vt of source follower transistor240, as understood by those of skill in the art.

In alternative embodiments, at the end of time T2, the reset driver235causes the reset node to become low, and the row select driver255causes the row select node to become low. In response to the reset node being low, reset transistor230becomes nonconductive. In some embodiments, the resent select node becomes low, and the ADC transistor250also becomes nonconductive. In some embodiments, at the end of time T2, row select driver255does not cause the row select node to be low, and ADC transistor250remains conductive.

In some embodiments, the pixel reset time of a particular row of the image sensor occurs during or near the time the ADC initialization time occurs as part of or in preparation for reading data from the pixels of another row of the image sensor.

During time T3, ADC260generates a first digital voltage D0encoding the voltage at the ADC input node. Accordingly, first digital voltage D0encodes the value Vdd−Vt.

During time T4, the TX driver225causes the voltage at the TX node to become equal to the ground voltage. In alternative embodiments, the TX driver225does not change the voltage at the TX node at time T4, such that the voltage at the TX node remains at the voltage value less than the ground voltage.

During time T5, the TX driver225causes the voltage at the TX node to become high, and the row select driver255either causes the row select node to become high or continues to cause the row select node to be high. In addition, the reset driver235causes the voltage at the reset node to remain low, such that the reset transistor230remains nonconductive.

In response to the voltage at the TX node becoming high, access transistor220becomes conductive. Because access transistor220is conductive and reset transistor230is nonconductive, the voltage at node FD becomes equal or substantially equal to the voltage (Vdata) at the data node of the phototransistor210.

In addition, in response to the row select node being high, row select transistor250is or becomes conductive. Furthermore, because ADC transistor250is conductive, a current sink (not shown) connected to the ADC input node causes the voltages at the ADC input node and the source node of the source follower transistor240to drop. In some embodiments, the current sink is part of the ADC260. In some embodiments, the current sink is not part of the ADC260, but is connected elsewhere to the ADC input node.

As understood by those of skill in the art, the current sink causes the voltages at the ADC input node and the source node of the source follower transistor242drop to a value equal to the voltage at the node FD minus a threshold voltage value Vt of source follower transistor240.

Accordingly, during time T5, the voltage at the ADC input node becomes equal to Vdata−Vt.

During time T6, the TX driver225causes the voltage at the TX node to become equal to the ground voltage, and the row select driver255causes the row select node to become low.

In response to the voltage at the TX node becoming the ground voltage, access transistor220becomes nonconductive, and the data node becomes isolated from the node FD. In addition, in response to the voltage at the row select node becoming low, the ADC input node becomes isolated from the source follower transistor240.

During time T7, the TX driver225causes the voltage at the TX node to become equal to the low voltage less than the ground voltage.

During time T8, ADC260generates a second digital voltage D1encoding the voltage at the ADC input node. Accordingly, second digital voltage D1encodes the value Vdata−Vt.

A controller, not shown, may receive both first and second digital voltages D0and D1, and may determine the image data of the illustrated read operation as a difference between first and second digital voltages D0and D1.

FIG. 4is a schematic diagram of an embodiment of TX drivers and their negative supply connection system. As shown, the TX drivers respectively provide TXi and TXj signals for image array sensor cells i and j, which provide image data to ADC460at the ADC input node. Certain functionality of the negative supply connection system comprising multiplexer's420, bond pads430and440, capacitor Cext, internal negative supply at node INT, external negative supply node EXT, and switch470, is described herein is used with TX drivers410and first and second image sensor cells i and j. In addition, negative supply connection systems having similar or identical features as those discussed herein may be used with other drivers for other types of image sensor cells, as understood by those of skill in the art.

As shown, negative supply node negv is connected to external negative supply node EXT through bond pad440.

Furthermore, the negative supply terminal of each TX driver410is connected to an output of a multiplexer420. In addition, each multiplexer has a first data input connected to the ground supply node gnd, a second data input connected to external negative supply node EXT, and a third data input connected to internal negative supply node INT. Furthermore, each multiplexer has a control input (not shown) which is used to select which of the data inputs is electrically connected with the multiplexer output.

As discussed in further detail elsewhere herein, each row of image sensor cells experiences a reset operation and a read operation. In some embodiments, a controller (not shown) causes the multiplexer420for a particular row experiencing a read operation to connect the negative supply terminal of the TX driver410for the particular row to the external negative supply node EXT during the read operation. In addition, the controller causes the multiplexer for certain or all rows not experiencing a read operation to connect the negative supply terminal of the TX driver410for the certain or all rows to the internal negative supply node INT during the read operation of the particular row.

The parasitic capacitance of the internal negative supply node INT is represented inFIG. 4as parasitic capacitor Cp. In embodiments of image sensors having many rows of image sensor cells, the value of parasitic capacitor Cp may be large. For example in some embodiments the value of parasitic capacitor Cp may be about 10 nF. The value of parasitic capacitor Cp is large at least partly because the internal negative supply node INT is connected to the TX nodes of many rows of the image sensor through the multiplexers420and TX drivers410.

In this embodiment, the negative voltage at external negative supply node EXT is generated by any suitable voltage source. The negative voltage generated by the voltage source is provided to external capacitor Cext, which is connected to each of external negative supply node EXT and ground supply node gnd through bond pads440and430, respectively.

In some embodiments, cells i and j, TX drivers410, and multiplexers420are integrated in a single integrated circuit package. In addition, external capacitor Cext may external to the integrated circuit package, and may be connected to external negative supply node EXT and to internal negative supply node INT through pins of the package, as understood by those of skill in the art.

In this embodiment, switch470is configured to connect internal negative supply node INT with external supply node EXT according to signal EN.

FIG. 5is a timing diagram illustrating functionality of the TX drivers and their negative supply connection system illustrated inFIG. 4while driving a first image sensor cell i and a second image sensor cell j, which are instantiations of the image sensor cell inFIG. 2, where first and second image sensor cells i and j are in different pixel rows of the image sensor. In some embodiments, a number of intervening pixel rows are between the respective pixel rows of first and second image sensor cells i and j. In this embodiment, the pixel reset time of the row of first image sensor cell i occurs while the ADC initialization time occurs as part of or in preparation for a reading data from the the row of second image sensor cell j. The time T1illustrated inFIG. 5corresponds with time T1ofFIG. 3with respect to the pixel reset time of the first image censor cell i. The times T2-T8illustrated inFIG. 5respectively correspond with like labeled times T2-T8ofFIG. 3with respect to the ADC input initialization and reading operations of the second image censor cell j.

During a time not illustrated and prior to the times illustrated inFIG. 5, second image sensor cell j experiences a pixel reset time similar or identical to that illustrated and discussed with respect to time T1ofFIG. 3. In addition, during a time not illustrated and after the times illustrated inFIG. 5, first image sensor cell i experiences an ADC initialization and pixel read operation similar or identical to that illustrated and discussed with respect to times T2-T8ofFIG. 3.

During time T1, the multiplexor420connected to the TX driver410for cell i receives a first control signal causing the negative supply terminal of the TX driver410for cell i to be connected to ground supply gnd instead of the internal negative supply node INT. The controller may generate the first control signal because the row of cell i is not experiencing a pixel read operation during time T1.

During time T1, the multiplexor420connected to the TX driver410for cell j receives a second control signal causing the negative supply terminal of the TX driver410for cell j to be connected to the internal negative supply node INT. The controller may generate the second control signal because the row of cell j is not experiencing a pixel read operation during time T1.

During time T1, the data node of the phototransistor of cell is reset because reseti, the reset node of cell i and TXi, the TX node of cell i are high, as discussed above with reference toFIGS. 2 and 3. In addition, during time T1, enable signal EN causes switch470to connect internal negative supply node INT with external supply node EXT.

During time T1, enable signal EN causes switch470to isolate internal negative supply node INT from external supply node EXT.

During time T2, the ADC input node of cell j is initialized because resetj, the reset node of cell j and row select j, the row select node of cell j, are high, as discussed above with reference toFIGS. 2 and 3. In addition, during time T2, enable signal EN causes switch470to connect internal negative supply node INT from external supply node EXT.

Furthermore, during time T2, the multiplexor420connected to the TX driver410for cell j receives a control signal causing the negative supply terminal of the TX driver410for cell j to be connected to the external negative supply node EXT, for example, as a result of the row of cell j experiencing or being prepared to experience a pixel read operation.

During time T3, during time T3, the multiplexor420connected to the TX driver410for cell i receives a control signal causing the negative supply terminal of the TX driver410for cell i to be connected to the internal negative supply node INT, and the multiplexor420connected to the TX driver410for cell j continues to receive the control signal causing the negative supply terminal of the TX driver410for cell j to be connected to the external negative supply node EXT.

In addition, during time T3, enable signal EN causes switch470to isolate internal negative supply node INT from external supply node EXT.

In addition, ADC460generates a first digital voltage D0encoding the initialization voltage at the ADC input node. Accordingly, first digital voltage D0encodes the value Vdd−Vt, as discussed above with reference toFIGS. 2 and 3.

Because the negative supply terminal of the TX driver410for cell j is connected to the external negative supply node EXT, and the external negative supply node EXT is isolated from internal negative supply node INT, the unsettled voltage changes on the internal negative supply node INT caused by the TX driver410for cell i sinking current to the internal negative supply node INT during time T1does not couple to cell j and consequently does not couple to the ADC input node. As a result, the first digital voltage D0generated by ADC460is not corrupted by noise coupled from cell i to cell j.

During time T4, the multiplexor420connected to the TX driver410for cell j receives a control signal causing the negative supply terminal of the TX driver410for cell j to be connected to ground supply node gnd. Accordingly, the voltage at node TXj increases from the negative voltage value to ground during time T4. In addition, during time T4, the multiplexor420connected to the TX driver410for cell i continues to receive the control signal causing the negative supply terminal of the TX driver410for cell i to be connected to the internal negative supply node INT.

Furthermore, during time T4j, enable signal EN continues to cause switch470to isolate internal negative supply node INT from external supply node EXT.

During time T5, cell j causes the voltage at the ADC input to change according to the voltage at the data node of cell j, as discussed above with reference toFIGS. 2 and 3. In addition, during time T5, enable signal EN continues to cause switch470to isolate internal negative supply node INT from external supply node EXT. Furthermore, during time T5, the multiplexor420connected to the TX driver410for cell j continues to receive the control signal causing the negative supply terminal of the TX driver410for cell j to be connected to ground supply node gnd, and the multiplexor420connected to the TX driver410for cell i continues to receive the control signal causing the negative supply terminal of the TX driver410for cell i to be connected to the internal negative supply node INT.

During time T6, the FD node of cell j is disconnected from the data node of cell j, as discussed above with reference toFIGS. 2 and 3.

Furthermore, during time T6, the multiplexor420connected to the TX driver410for cell j continues to receive the control signal causing the negative supply terminal of the TX driver410for cell j to be connected to ground supply node gnd, and the multiplexor420connected to the TX driver410for cell i continues to receive the control signal causing the negative supply terminal of the TX driver410for cell i to be connected to the internal negative supply node INT.

During time T7, the multiplexor420connected to the TX driver410for cell j receives a control signal causing the negative supply terminal of the TX driver410for cell j to be connected to the external negative supply node EXT. Accordingly, the voltage at node TXj decreases from the ground voltage to the negative voltage value of the external negative supply node EXT.

Furthermore, during time T7, the multiplexor420connected to the TX driver410for cell i continues to receive the control signal causing the negative supply terminal of the TX driver410for cell i to be connected to the internal negative supply node INT.1

In addition, at time T7, enable signal EN continues to cause switch470to isolate internal negative supply node INT from external negative supply node EXT.

During time T8, the multiplexor420connected to the TX driver410for cell i continues to receive the control signal causing the negative supply terminal of the TX driver410for cell i to be connected to the internal negative supply node INT, and the multiplexor420connected to the TX driver410for cell j continues to receive the control signal causing the negative supply terminal of the TX driver410for cell j to be connected to the external negative supply node EXT.

Furthermore, during time T8, ADC260generates a second digital voltage D1encoding the voltage at the ADC input node. Accordingly, second digital voltages D1encodes the value Vdata−Vt, as discussed above with reference toFIGS. 2 and 3. In addition, during time T8, enable signal EN continues to cause switch470to isolate internal negative supply node INT from external supply node EXT.

Because the negative supply terminal of the TX driver410for cell j is connected to the external negative supply node EXT, and the external negative supply node EXT is isolated from internal negative supply node INT, the voltage changes on the internal negative supply node INT caused noise or delayed settling does not couple to cell j and consequently does not couple to the ADC input node. As a result, the second digital voltage D1generated by ADC460is not corrupted by noise coupled to cell j through the negative supply terminal of the TX driver410for cell j.

A controller, not shown, may receive both first and second digital voltages D0and D1, and may determine the image data of the illustrated read operation as a difference between first and second digital voltages D0and D1.

FIG. 6is a timing waveform diagram illustrating a timing relationship between operation of the charge pump450and a read period, during which the image sensor cells are read. As understood by those of skill in the art, the timing waveform diagram of is an example only, and the principles discussed herein may be applied to other embodiments.

The EN waveform indicates periods during which switch470is conductive and charge pump circuit450is enabled.

The RESET 1 and RESET N waveforms respectively indicate periods during which row 1 through row N of the image sensor are reset. Each row of image sensor cells may be reset using a process similar or identical to that discussed above with reference toFIGS. 2-5during times T1.

The READ N/2 and READ N/2−1 waveforms respectively indicate periods during which row N/2 through row N/2−1 of the image sensor are read. Each row of image sensor cells may be read using a process similar or identical to that discussed above with reference toFIGS. 2-5during times T2-T8.

During time T1, an asynchronous negative supply voltage refresh occurs. During time T1, the switch470is closed, such that the external negative supply node EXT is electrically connected with the internal negative supply node INT. In addition, charge pump450is enabled, such that the voltage at the connected internal and external negative supply nodes INT and EXT is caused to change so as to become or become closer to a target negative supply voltage value according to a feedback system, as understood by those of skill in the art.

During time T2, read operations occur for the image sensor array cells of the image sensor or occur for a portion of the image sensor array cell of the image sensor. For example, each row of image sensor cells may be reset and data read therefrom using processes similar or identical to that discussed above with reference toFIGS. 2-5.

During the reset portions of time T2, the switch470is closed, such that the external negative supply node EXT is electrically connected with the internal negative supply node INT while each row of image sensor cells are reset. In addition, charge pump450is enabled, such that the voltage at the connected internal and external negative supply nodes INT and EXT is caused to change so as to become or become closer to the target negative supply voltage value during the reset portions of time T2.

During part of the read portions of time T2, the switch470is closed, such that the external negative supply node EXT is electrically connected with the internal negative supply node INT while the ADC input nodes are reset, for example, using a process similar or identical to that discussed above with reference to time T2ofFIGS. 2-5. In addition, charge pump450is enabled, such that the voltage at the connected internal and external negative supply nodes INT and EXT is caused to change so as to become or become closer to a target negative supply voltage value according to a feedback system, as understood by those of skill in the art.

In addition, during part of the read portions of time T2, the switch470is open, such that the external negative supply node EXT is electrically disconnected from the internal negative supply node INT while data of each row of image sensor cells are read, for example, using a process similar or identical to that discussed above with reference to times T3-T8ofFIGS. 2-5. In addition, charge pump450is disabled, such that the voltage at the connected internal and external negative supply nodes INT and EXT is not caused to change by charge pump450while data of each row of image sensor cells are read.

Because the external negative supply node EXT is electrically disconnected from the internal negative supply node INT during the read portions of time T2, noise on the internal negative supply node INT, for example, caused by reset activity, is isolated from the row of image sensor cells being read, so that the read operation is not or is substantially not affected by noise on the internal negative supply node INT.

As understood by those of skill in the art, because of the switching or clocked charge pumping activity, charge pump450causes voltage excursions in the negative voltage it generates. However, because charge pump450is disabled during the read portions of time T2, the charge pumping activity of charge pump450ceases during the read portions of time T2. Accordingly, during the read portions of time T2, charge pump450does not cause voltage excursions in the negative voltage of the row of image sensor cells being read, so that the read operation is not affected by charge pumping activity of charge pump450.

During time T3, an asynchronous negative supply voltage refresh occurs. During time T3, the switch470is closed, such that the external negative supply node EXT is electrically connected with the internal negative supply node INT. In addition, charge pump450is enabled, such that the voltage at the connected internal and external negative supply nodes INT and EXT is caused to change so as to become or become closer to a target negative supply voltage value according to a feedback system, as understood by those of skill in the art.

In some embodiments, for each occurrence of time T1, multiple periods of times T2and T3are consecutively repeated.