Integrated circuit with high voltage junction structure

The high voltage integrated circuit comprises a P substrate. An N well barrier is disposed in the substrate. Separated P diffusion regions forming P wells are disposed in the substrate for serving as the isolation structures. The low voltage control circuit is located outside the N well barrier. A floating circuit is located inside the N well barrier. In order to develop a high voltage junction barrier in between the floating circuit and the substrate, the maximum space of devices of the floating circuit is restricted.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an integrated circuit, and more particularly to a high voltage integrated circuit.

2. Description of the Prior Art

A variety of power supplies and motor drivers utilize the bridge circuits to control a power source to the load. The bridge circuit normally has a high-side transistor connected to the power source and a low-side transistor connected to ground. A common node between the high-side transistor and low-side transistor is coupled to the load. As transistors are controlled to alternately conduct, the voltage of the common node swings between the voltage of the power source and the ground. Therefore the control of high-side transistor requires a charge pump circuit and/or a floating driver in order to fully turn on the high-side transistor. In recent development, many floating circuits are disclosed in U.S. Pat. No. 6,344,959 (Milazzo), U.S. Pat. No. 6,781,422 (Yang) and U.S. Pat. No. 6,836,173 (Yang).

FIG. 1shows a high-side transistor drive circuit, in which a circuit10is the floating driver. A capacitor40provides a supply voltage to the floating driver10. A voltage VDcharges the capacitor40through a diode45once the low-side transistor30is switched on. The ground reference of the capacitor40is pulled to the level of the voltage source VIN when the high-side transistor20is turned on. This happens, because turning on the high-side transistor20shifts the bridge circuit into a low impedance state.

SUMMARY OF THE INVENTION

Accordingly, an objective of the present invention is to provide a monolithic IC process to integrate the low-voltage control circuits with a high-voltage floating drive circuit. Furthermore, the integration is achieved by using a typical IC process, so as to accomplish the low cost and high production yield.

According to an embodiment of the present invention, a high voltage integrated circuit comprises a P substrate. An N diffusion region containing N conductivity type forms an N well barrier disposed in the substrate. Separated P diffusion regions containing the P conductivity type form P wells are disposed in the substrate for serving as the isolation structures. The low voltage control circuit is located outside the N well barrier. A floating circuit is located inside the N well barrier. A high voltage junction barrier is formed to isolate the control circuit and the floating circuit. Furthermore, in order to develop a high voltage junction barrier between the floating circuit and the substrate, the maximum space of devices of the floating circuit is restricted.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2is a top view of an integrated circuit with high voltage junction structure according to an embodiment of present invention. The integrated circuit includes a P substrate50, an N diffusion region containing N conductivity type. The N diffusion region forms an N well barrier60disposed in the P substrate50. A low voltage control circuit300is located outside the N well barrier60. A floating circuit200is located inside the N well barrier60. The voltage supplied to the floating circuit200is a fixed voltage, as shown inFIG. 1, the voltage supply is connected to the capacitor40. The ground reference of the voltage supply is thus floated and the ground reference of the transistors in floating drive10is also floated.

FIG. 3shows a voltage distribution when 500V is applied to the floating circuit200. A high voltage junction barrier is formed to isolate the control circuit300from the floating circuit200. Furthermore, the restricted space D between devices of the floating circuit200converge the electrical field to develop a high voltage junction barrier between the floating circuit200and the substrate50.

FIG. 4is a cross-sectional view of a proposed integration circuit, in which P diffusion regions containing the P conductivity type forms P regions65disposed in the P substrate50for serving as the isolation structures. P regions65help to form depletion regions for serving as the isolation structures. The control circuit300and the floating circuit200include N type MOSFET devices and P type MOSFET devices. The N type MOSFET device in the floating circuit200comprises a first N diffusion region containing N conductivity type, which forms an N well70disposed in the substrate50. A first P diffusion region containing the P conductivity type forms a P region71located in the N well70. A first drain diffusion region having the N+ conductivity type, which forms a drain region72disposed in the first N diffusion region. A first source diffusion region having the N+ conductivity type forms a source region74. A conduction channel is developed between the source region74and the drain region72. A first contact diffusion region containing P+ conductivity type forms a contact region75. The first P diffusion region encloses the source region74and the contact region75. The P type MOSFET device comprises a second N diffusion region containing N conductivity type, which forms an N well80disposed in the substrate50. A second P diffusion region containing the P conductivity type forms a P region81located in the N well80. A second drain diffusion region having the P+ conductivity type forms a drain region82disposed in the second P diffusion region. A second source diffusion region having the P+ conductivity type forms a source region85. A conduction channel is developed between the source region85and the drain region82. A second contact diffusion region containing N+ conductivity type forms a contact region84. The second N diffusion region encloses the source region85and the contact region84.

The N type MOSFET device in the control circuit300comprises a third N diffusion region containing N conductivity type, which forms an N well90disposed in the substrate50. A third P diffusion region containing the P conductivity type forms a P region91located in the N well90. A third drain diffusion region having the N+ conductivity type, which forms a drain region92disposed in the third N diffusion region. A third source diffusion region having the N+ conductivity type forms a source region94. A conduction channel is developed between the source region94and the drain region92. A third contact diffusion region containing P+ conductivity type forms a contact region95. The third P diffusion region encloses the source region94and the contact region95.

FIG. 5shows a depletion region100between the two high voltage barriers101when a high voltage is applied to the floating circuit200. Because the maximum space D between devices of the floating circuit200is limited, which help to develop the high voltage junction barrier101between the floating circuit200and the substrate50.