Information processing apparatus, and control method and storage medium therefor

An information processing apparatus capable of suppressing a secondary battery from being charged with an amount of charge current that can apply excessive load on the secondary battery, without a backup power source function of the secondary battery being impaired. When determining that a predetermined type of data is stored in a DRAM to be backed up by the secondary battery, the information processing apparatus selects a first constant current circuit and quickly charges the secondary battery with a large charge current output from the first constant current circuit. When determining that the predetermined type of data is not stored in the DRAM, the information processing apparatus selects a second constant current circuit and normally charges the secondary battery with a small charge current output from the second constant current circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an information processing apparatus, a control method therefor, and a storage medium storing a program for executing the control method.

2. Description of the Related Art

A secondary battery such as a lithium battery or a nickel hydride battery is used as a temporary backup power source at shutdown of power supply from a power source. For example, an image processing apparatus has a secondary battery that supplies backup power enabling a volatile memory of the apparatus such as a DRAM to retain facsimile image data, etc. at shutdown of power supply from, e.g., a commercially available AC power source to the image processing apparatus.

Such a backup secondary battery is provided for accidental short-time power shutdown such as power outage, and is generally charged to become a predetermined charged state, e.g., a fully-charged state. However, if the fully-charged secondary battery is further charged to an overcharged state, the battery performance is deteriorated. Accordingly, techniques have been proposed in which when a fully-charged state of the secondary battery is detected, a shift is made to trickle charge where the battery is charged with an amount of current for compensating only for self-discharge of the battery.

In these techniques, when the battery voltage reaches a predetermined voltage, a fully-charged state is detected and a shift is made to the trickle charge. However, a relation between battery voltage and battery charge state varies depending on peripheral temperature, and accordingly, a fully-charged state cannot be properly detected in some cases without using a temperature sensor. Thus, there has been proposed a technique for starting normal charge at power-on and for making a changeover from normal charge to trickle charge when a predetermined time period (e.g., 12 hours to 16 hours) has lapsed from the start of the normal charge.

Another proposed technique is to reduce power consumption by not performing data backup at shutdown of power supply or at power-saving in a case where there is no backup object data such as facsimile image data (see, for example, Japanese Laid-open No. H08-129511).

However, it takes several hours for the secondary battery to be charged by the normal charge to a fully-charged state. Accordingly, if an image processing apparatus or the like is started up in a state where the secondary battery is almost discharged, a time period over which a data backup operation can be performed becomes extremely short immediately after the start of the apparatus, so that the backup power source function of the secondary battery is impaired.

Also known is quick charge in which an amount of charge current is increased as compared to that in the normal charge to thereby shorten a time period required for battery charge. However, there is a fear that overcharge is caused, if the quick charge using a large amount of charge current per unit time is performed in a state where the battery charge state cannot be detected with accuracy due to a change in peripheral temperature.

SUMMARY OF THE INVENTION

The present invention provides an information processing apparatus capable of suppressing a secondary battery from being charged with an amount of charge current that can apply excessive load on the secondary battery, without a backup power source function of the secondary battery being impaired, and provides a control method and a storage medium for the information processing apparatus.

According to one aspect of this invention, there is provided an information processing apparatus, which comprises a volatile storage unit, a first supply unit configured to supply electric power to the storage unit, a second supply unit configured to supply electric power to the storage unit in a case where the first supply unit becomes unable to supply electric power to the storage unit, a charging unit configured to charge the supply unit by a first charging method or by a second charging method capable of charging more quickly than the first charging method, and a control unit configured to perform control such that the charging unit charges the second supply unit by the first charging method in a case where there is no predetermined data in the storage unit and such that the charging unit charges the second supply unit by the second charging method in a case where there is the predetermined data in the storage unit.

With this invention, it is possible to suppress a secondary battery from being charged with an amount of charge current that can apply excessive load on the secondary battery, without a backup power source function of the secondary battery being impaired.

Further features of the present invention will become apparent from the following description of an exemplary embodiment with reference to the attached drawings.

DESCRIPTION OF THE EMBODIMENTS

The present invention will now be described in detail below with reference to the drawings showing a preferred embodiment thereof.

FIG. 1schematically shows in block diagram the construction of a battery charger, which is an information processing apparatus according to one embodiment of this invention.

InFIG. 1, reference numeral100denotes a battery charger. The battery charger100of this embodiment is configured to charge a secondary battery1(second supply unit) serving as a backup power source for a DRAM23(volatile storage unit) for use by an image processing apparatus (not shown) to store image data, for example. It should be noted that this invention is not limited to this embodiment, but is applicable to any battery charger (information processing apparatus) for charging a secondary battery serving as a backup power source for a volatile memory.

The battery charger100includes a CPU5, clock IC6, primary battery20, sleep control circuit18, and power unit8.

The power unit8is connected to an AC power source (not shown), and generates, from AC power supplied from the AC power source, DC power to be supplied to the battery charger100and to the image processing apparatus mounted with the battery charger100. The power unit8includes a primary power source10that outputs the DC power as long as the AC power is supplied from the AC power source, and a secondary power source11that stops outputting the DC power when the image processing apparatus is in a sleep state.

The CPU5is supplied with the power from the secondary power source11. Since the power consumption of the CPU5is relatively large, the power supply to the CPU5is stopped in this embodiment when the image processing apparatus is in the sleep state.

The CPU5is connected through a bus (not shown) to a ROM (not shown) and to the DRAM23, and controls operations of various parts of the battery charger100by executing a program read from the ROM. The CPU5outputs to the clock IC6interface signals15according to which the clock IC6is set and clock information is read from the clock IC6.

The clock IC6is supplied with power from a primary battery20such as a dry battery or a lithium battery, and is operable unless the primary battery20is exhausted, even if the AC power supply from the AC power source is shut down. The clock IC6outputs an interrupt output16to the sleep control circuit18when an alarm time set beforehand in the clock IC6by the CPU5is reached.

The sleep control circuit18is supplied with power from the primary power source10of the power unit8. If the interrupt output16is output from the clock IC6when the power unit8is in a sleep state, the sleep control circuit18outputs a wakeup signal17to cause the power unit8to wake up from the sleep state.

The battery charger100further includes first and second constant current circuits31,32, charge current selection switch7, battery voltage detection circuit9, OR circuit3, DC/DC converter21, power source selection switch22, and flip-flop circuit (hereinafter, referred to as the FF circuit)4.

The CPU5outputs a charge/non-charge signal14to the FF circuit4.

The FF circuit4outputs to the OR circuit3an FF signal13which is set according to the charge signal14from the CPU5and reset according to the non-charge signal14from the CPU5.

The battery voltage detection circuit9mainly includes a comparator, and detects a voltage across the secondary battery1. When detecting a secondary battery voltage less than a voltage at which the secondary battery1is regarded as being in a fully-charged state, the battery voltage detection circuit9outputs a non-full charge detection signal27to the OR circuit3.

The OR circuit3outputs to the first and second constant current circuits31,32an OR output of the non-full detection signal27from the battery voltage detection circuit9and the FF signal13from the FF circuit4. The OR circuit3is supplied with power from the primary power source10.

The first and second constant current circuits31,32are supplied with power from the primary power source10. The first constant current circuit31is configured to output a first charge current34to be used to charge the secondary battery1, and the second constant current circuit32is configured to output a second charge current35to be used to charge the secondary battery1and less than the first charge current34. The constant current circuits31,32are each mainly comprised of transistors, and the secondary battery1is a lithium ion battery or a nickel hydride battery.

The first and second constant current circuits31,32are each supplied with the OR output33from the OR circuit3. If the OR output33is at ON, the first and second constant current circuits31,32output the first and second charge currents34,35, respectively. On the other hand, if the OR output33from the OR circuit3is at OFF, the constant current circuits31,32stop outputting the charge currents.

The charge current selection switch7selects either the first constant current circuit31or the second constant current circuit32in accordance with a charge current selection signal26from the CPU5. If the first constant current circuit31is selected by the selection switch7and if the OR output33is at ON, the secondary battery1is quickly charged with the large charge current34from the first constant current circuit31. On the other hand, if the second constant current circuit32is selected by the selection switch7and if the OR output33is at ON, the secondary battery1is normally charged with the small charge current35from the second constant current circuit32.

The DC/DC converter21generates backup power24from the output power of the secondary battery1, and outputs the backup power24to the power source selection switch22.

The power source selection switch22selects either the DC power from the primary power source10or the backup power24output from the DC/DC converter21. If the power unit8is supplied with AC power from the AC power source, the power source selection switch22selects the DC power from the primary power source10(first supply unit), and outputs the DC power as power25to the DRAM23. On the other hand, if the AC power supply from the AC power source to the power unit8is shut down due to power outage or the like, the selection switch22selects the backup power24output from the DC/DC converter21, and outputs the backup power24as the power25to the DRAM23.

The DRAM23operates with the power25output from the power source selection switch22, and is used by the CPU5to execute a program and to store image data. The DRAM23is backed up by the power of the secondary battery1and retains image data stored in the RAM23when the AC power supply to the power unit8is shut down. In other words, the secondary battery1serves as a backup power source for the DRAM23.

FIG. 2shows in flowchart the procedures of a charge control process executed by the CPU5of the battery charger100.

In the charge control process ofFIG. 2, the CPU5(control unit) detects a charged amount of the secondary battery1based on a secondary battery voltage detected by the battery voltage detection circuit9(step S101), and determines whether the charged amount of the secondary battery1is equal to or larger than a predetermined charged amount (step S102). In this embodiment, whether or not the secondary battery1is in a fully-charged state is determined in step S102. It should be noted that the predetermined charged amount is not limited to the charged amount that corresponds to the fully-charged state. For example, the predetermined charged amount can be equal to 90% of the charged amount corresponding to the fully-charged state. This also applies to a predetermined charged amount for use in a determination in step S202ofFIG. 3described later.

If it is determined in step S102that the secondary battery1is in the fully-charged state (i.e., if YES to step S102), the charge control process is completed. In that case, the FF signal13of the FF circuit4is reset according to the non-charge signal14from the CPU5and the non-full charge detection signal27is not output from the battery voltage detection circuit9(seeFIG. 1). As a result, the OR output33from the OR circuit3becomes OFF, so that the first and second constant current circuits31,32(charging unit) stop outputting the charge currents.

If it is determined in step S102that the secondary battery1is not in the fully-charged state (i.e., if NO to step S102), whether a predetermined type of data (described later) is stored in the DRAM23is determined (step S103). If it is determined that such data is stored in the DRAM23(i.e., if YES to step S103), the first constant current circuit31is selected by the charge current selection switch7, thereby performing the quick charge (step S104). In the quick charge, the secondary battery1is charged with the first charge current34(e.g., of 1 A) output from the first constant current circuit31. Specifically, according to the non-full detection signal27from the battery voltage detection circuit9, the OR output33from the OR circuit3becomes ON, so that the first and second charge currents34,35are respectively output from the first and second constant current circuits31,32and the secondary battery1is charged with the first charge current34from the first constant current circuit31selected by the selection switch7according to the charge current selection signal26from the CPU5(seeFIG. 1).

On the other hand, if it is determined that the predetermined type of data is not stored in the DRAM23(i.e., if NO to step S103), the second constant current circuit32is selected by the charge current selection switch7, thereby performing the normal charge (step S105). In the normal charge, the secondary battery1is charged with the second charge current35(e.g., of 200 mA) output from the second constant current circuit32. Specifically, according to the non-full detection signal27from the battery voltage detection circuit9, the OR output33from the OR circuit3becomes ON, so that the charge currents34,35are respectively output from the constant current circuits31,32and the secondary battery1is charged with the charge current35from the constant current circuit32selected by the selection switch7according to the charge current selection signal26from the CPU5(seeFIG. 1).

The battery charger100of this embodiment is configured to charge the secondary battery1serving as the backup power source for the DRAM23mounted to the image processing apparatus. The predetermined type of data is, e.g., image data received in a reception job such as confidential fax reception or memory reception, or image data printed in a PDL print job, or image data transmitted in a transmission job such as scheduled FAX, SMB, E-mail, and I-FAX. In other words, the predetermined type of data is data to be printed on a recording medium or data to be transmitted and received between an apparatus mounted with the battery charger and other apparatus.

As described above, according to the charge control process ofFIG. 2, the secondary battery1is normally charged with the predetermined charge current, i.e., with predetermined amount of power (more generally, the secondary battery1is charged by a first charging method) when the predetermined type of data (more generally, predetermined data) is not stored in the DRAM23, but quickly charged with an amount of power larger than the predetermined amount of power (more generally, charged by a second charging method) when the predetermined type of data is stored in the DRAM23. It is therefore possible to suppress the secondary battery1from being charged with an amount of current that can apply excessive load on the secondary battery1, without impairing the backup power source function of the secondary battery1.

Since the secondary battery1is suppressed from being overcharged by limitedly performing the quick charge, the secondary battery charge control can be realized by using a relatively low-priced circuit construction such as the battery voltage detection circuit9comprised of a comparator and the like.

FIG. 3shows in flowchart the procedures of another charge control process executed by the CPU5of the battery charger100.

In steps S201to S203of the charge control process ofFIG. 3, the same processing as that in steps S101to S103inFIG. 2is carried out. Specifically, the CPU5detects a charged amount of the secondary battery1based on a voltage detected by the battery voltage detection circuit9(step S201), and determines whether the secondary battery1is in the fully-charged state (step S202). If the secondary battery1is in the fully-charged state, the charge control process is completed.

On the other hand, if it is determined in step S202that the secondary battery1is not in the fully-charged state, whether or not the predetermined type of data is stored in the DRAM23is determined (step S203). If it is determined that such data is not stored in the DRAM23, the charge control process is completed.

If it is determined in step S203that the predetermined type of data is stored in the DRAM23(i.e., if YES to step S203), the CPU5determines whether a setting time has elapsed from the start of charging, while referring to a built-in timer (step S204). The setting time is set to a time period required for the secondary battery1to be charged to a charge state where a required data backup operation time is ensured. If the setting time has elapsed from the start of charging (i.e., if YES to step S204), the CPU5outputs the charge current selection signal26according to which the selection switch7operates to select the second constant current circuit32, thereby performing the normal charge (step S205). Then, the charge control process is completed.

On the other hand, if it is determined in step S204that the setting time has not elapsed from the start of charging (i.e., if NO to step S204), the CPU5outputs the charge current selection signal26according to which the selection switch7operates to select the first constant current circuit31, thereby performing the quick charge (step S206), whereupon the process returns to step S203.

As described above, according to the charge control process ofFIG. 3, the secondary battery1is normally charged with the predetermined amount of power, if the predetermined type of data is stored in the DRAM23and if the predetermined time period has elapsed from the start of charging. On the other hand, the secondary battery1is quickly charged with the amount of power larger than the predetermined amount of power, if the predetermined type of data is stored in the DRAM23and if the predetermined time period has not elapsed from the start of charging. It is therefore possible to suppress the secondary battery1from being charged with an amount of current that can apply excessive load on the secondary battery1, without impairing the backup power source function of the secondary battery1.

In addition, with the charge control process ofFIG. 3, since the quick charge is performed until the setting time has elapsed from the start of charging, it is possible to ensure the required data backup operation time by using a relatively low-priced circuit construction such as the battery voltage detection circuit9comprised of a comparator and the like, without causing the secondary battery1to be overcharged.

Other Embodiments

Aspects of the present invention can also be realized by a computer of a system or apparatus (or devices such as a CPU or MPU) that reads out and executes a program recorded on a memory device to perform the functions of the above-described embodiment, and by a method, the steps of which are performed by a computer of a system or apparatus by, for example, reading out and executing a program recorded on a memory device to perform the functions of the above-described embodiment. For this purpose, the program is provided to the computer for example via a network or from a recording medium of various types serving as the memory device (e.g., computer-readable medium).

This application claims the benefit of Japanese Patent Application No. 2010-226723, filed Oct. 6, 2010, which is hereby incorporated by reference herein in its entirety.