Multi-layer printed wiring board

A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring is arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multi-layer printed circuit board. This application is based on Japanese Patent application No. 2006-347849, the disclosure of which is incorporated herein by reference.

2. Description of Related Art

In recent years, the package shape of a semiconductor device (hereafter, to be referred to as a logic part) for controlling a storage unit such as a memory is changed from a lead type to a CSP (Chip Size Package) type in which power source pins, ground pins and input/output pins can be arranged in a high density. At the same time, the increase in the number of the pins in the package is advanced, and restriction on pattern design of the printed circuit board on which the package is mounted is also increased.

FIGS. 1 to 3show the outer appearance of a logic part.FIG. 1is a top view of the logic part,FIG. 2is a side view, andFIG. 3is a view showing the rear side of the logic part. As shown inFIG. 3, many terminals are arranged on the rear side of the logic part. It should be noted that inFIG. 3, terminals for power sources and ground pins are shown inside the dashed line.

The configuration of the printed circuit board for mounting the above logic part will be described below with reference toFIGS. 4 to 8. InFIGS. 5 to 8, an inter-layer connection component1for the connection between wiring layers, a conductor pattern2, and a mounting pad of the logic part are shown inFIGS. 5 to 8.FIG. 4shows a part mounting surface of the printed circuit board,FIG. 5shows a rear surface thereof, andFIGS. 6 and 7show the inner wiring layers, respectively.FIG. 8is an expanded view of a portion of the part mounting surface.

As shown inFIG. 4, a large number of mounting pads3for mounting the logic part are provided on the part mounting surface in correspondence to terminals on the rear surface of the logic part. Conductors for signal lines are connected to the respective mounting pads3. Here, a conductor pattern2extending on the part-mounting surface is connected to the mounting pad3arranged on the relatively outer section side.

On the other hand, by a wiring only on the part mounting surface, the signal line cannot be connected to the mounting pad3arranged on the central section side among the mounting pads3. This is because a space between the mounting pads3is occupied by the conductor patterns2extending for the mounting pads3on the relatively outer section side. Thus, an inter-layer connection component1is arranged to connect the mounting pad3on the central section side. That is, as shown inFIGS. 6 and 7, in the inner layer, the conductor pattern2as the signal line is extended to the central section and connected through the inter-layer connection component1to the mounting pad3on the part mounting surface.

As the above-mentioned inter-layer connection component1, there are known a through-hole penetrating from the front to the rear of the board, a lead insertion hole described in a first conventional example (Japanese Laid Open Patent Application (JP-P2000-4086A)) and a via-holes described in a second conventional example (Japanese Laid Open Patent Application (JP-A-Heisei, 10-322027)).

If the via-hole and the lead insertion hole are used as the inter-layer connection components1, it is possible to selectively connect a segment between the wiring layers. However, they require the manufacturing steps whose number is greater than that of the through-hole. Thus, in a memory mounting printed circuit board, the penetration through-holes have been used as the inter-layer connection components.

In association with the increase in the number of pins in the logic part, wiring layers in the printed circuit board trend to be increased. As a specific example, when a wiring rule is considered in which one conductive pattern is arranged between the penetration through-holes, one wiring layer is required to be added to the printed circuit board each time the terminals of the logic part are increased for one line.FIGS. 6 and 7show such states. The increase in the wiring layer causes severe restriction on the printed circuit board design for a memory module. In the printed circuit board for the memory module, since the current form factors such as a socket are used, it is difficult to change the thickness of the printed circuit board. That is, the number of the layers must be increased without any change in the total thickness of the printed circuit board, and the thickness for one layer must be made thin. However, in case of the trial to make the thickness of each layer thin, a limit is in the process of manufacturing a fine structure of a conductor wiring and a constraint is from the viewpoint of the characteristic impedance of the wiring. Specifically, in the current memory module printed circuit board, it is difficult to exceed the 10 layers.

Also, the increase in the number of pins in the logic part is required to be attained without any increase in the impedances of a power source wiring and a ground wiring on the printed circuit board. Anti-pads5to protect a short-circuit are required to be arranged at the positions corresponding to the penetration through-holes in all of the power source and ground layers in the printed circuit board.FIG. 9is a diagram showing the anti-pad5. InFIG. 9, the inter-layer connection component1, a conductor6, and a space4to prevent the short-circuit are shown.

FIG. 10shows a design example of the power source layer and ground layer in the board design shown inFIGS. 4 to 8. As shown inFIG. 10, a power source and ground area6is removed by the anti-pads5. That is, the power source and ground area is removed, resulting in the increase in the impedances of the power source and ground wirings in the printed circuit board.

Therefore, the printed circuit board is demanded in which the number of pins in the logic part can be increased while suppressing the increase in the impedances of the power source and the ground wiring.

Also, in the memory module, the memories and the logic parts must be efficiently mounted on the printed circuit board. Thus, parts for decreasing the impedances of the power source and the ground wirings can be efficiently mounted on the opposite side to the logic parts,FIGS. 11 and 12show this situation.

FIG. 11shows an example in which a typical logic part8and impedance decreasing parts9(9ato9e) such as a chip capacitor are mounted on a printed circuit board7, andFIG. 12shows an example in which the logic part8for the memory module, the memories10aand10band an impedance decreasing part9are mounted on a printed circuit board7. As shown inFIG. 11, in case of a typical module, many impedance decreasing parts9can be mounted on the printed circuit board7on the side opposite to the logic part8. On the contrary, in case of the memory module shown inFIG. 12, the memories10must be mounted on the printed circuit board7on the side opposite to the logic part8. Accordingly, the number of the mountable impedance decreasing parts9is extremely reduced. Thus, in the printed circuit board on which the memories are mounted, it is difficult to desirably decrease the impedance. That is, in particular, in the printed circuit board on which the memories are mounted, a technique is demanded that the increase of the impedance can be suppressed.

SUMMARY

An object of the present invention is provide a multi-layer printed circuit board that can suppress the increase in the impedance.

In a first aspect of the present invention, a multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring are arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.

According to the present invention, a multi-layer printed circuit board that can suppress the increase in the impedance is provided.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a multi-layer printed circuit board of embodiments of the present invention will be described in detail with reference to the attached drawings.

First Embodiment

FIG. 13is a top view of a multi-layer printed circuit board11according to a first embodiment of the present invention, andFIG. 14is a rear view showing the rear surface thereof. As shown inFIGS. 13 and 14, areas12(12ato12u) for mounting memories, an area13for mounting a logic part and board connectors14(14a,14b) are provided on the top and rear surfaces of the multi-layer printed circuit board11.

FIGS. 15 and 16are expanded views of portions of the multi-layer printed circuit board11shown inFIGS. 13 and 14. As shown inFIGS. 15 and 16, many terminals15are arranged in each of the areas12and the area13for connections to the logic part and the memories.

FIG. 17is a cross sectional view along the line AA′ shown inFIG. 15. As shown inFIG. 17, the multi-layer printed circuit board11has a structure in which a plurality of wiring layers (10 layers;16ato16k) are laminated. It should be noted that in this embodiment, a case that the wiring layers of 10 layers are laminated is described. However, the present invention can be applied to a case of 3 layers or more.

InFIG. 17, terminals15ato15dfor mounting a logic part8are shown on the uppermost layer16aamong the plurality of wiring layers16ato16k. Also, terminals17aand17bfor the board connector14are provided on the uppermost layer16aand the lowermost layer16kamong the plurality of wiring layers16ato16k, respectively. Among the plurality of wiring layers16ato16k, the wiring layer16dis an inner power source layer, and the wiring layer16gis a ground layer.

Inter-layer connection components18are connected to the respective terminals15ato15d. These inter-layer connection components18are blind via-holes for carrying out the selective connections between the plurality of wiring layers. It should be noted that in this specification, the blind via-hole implies an inter-layer connection component for carrying out the connection between the layers without penetrating any wiring layer. Among the inter-layer connection components18, the inter-layer connection component18corresponding to the terminal15dextends to the wiring layer16cand is connected to a wiring19aformed on the wiring layer16c. The wiring19ais connected through a different inter-layer connection component to the terminal17a. That is, the terminal15dfor the logic part is electrically connected to the terminal17afor the board connector. Similarly, the inter-layer connection component18connected to the terminal15bextends to the wiring layer16hand is connected to the wiring19bformed on the wiring layer16h. The wiring19bis connected through a different inter-layer connection component to the terminal17b. That is, the terminal15bfor the logic part is electrically connected to the terminal17bfor the board connector.

In this way, since the blind via-holes are used as the inter-layer connection components18, the wiring19bconnected with the logic part terminal15band the board connector terminal17band the wiring19aconnected with the logic part terminal15dand the board connector terminal17acan be laid on a same section. Since the inter-layer connection component18connected to the terminal15ddoes not extend to the wiring layer16h, the wiring19bis not required to make a detour in a direction that is not parallel to the paper surface. This fact contributes to the improvement of the wiring density.

Also, when the wiring layers16dand16gare the power source and ground layers, there is no case that the inter-layer connection components18corresponding to the terminal15dpenetrate through the power source and ground layers. Accordingly, the areas of the power source and ground layers can be made larger than those in a case that the penetration through-holes are used as the inter-layer connection components18. Also, even when the power source and ground layers16dand16gare reference layers of the wirings19aand19b, the transmission line configuration, which is electrically uniform, can be attained without any suffering from the shape influence of the inter-layer connection components18.

In succession, the wiring layout of the wiring layer as the inner layer will be described.FIG. 18is a diagram showing the wiring layout on the wiring layer (a first wiring layer)16hamong the plurality of wiring layers16ato16k.FIG. 19is an expanded view of a region R shown inFIG. 18.

FIG. 19shows the arrangement of the plurality of inter-layer connection components18and the wirings19. A plurality of the inter-layer connection components18are the blind via-holes as mentioned above. Among the plurality of inter-layer connection components18, the inter-layer connection component18connected to the first wiring layer16his shown as a black circle. It should be noted that although being not electrically connected to any wiring19on the first layer16h, an inter-layer connection component16formed to extend the first layer16hin a lamination direction without a connection is shown as if it is connected to the first layer16h. Also, the inter-layer connection component18bthat is not connected to the first layer16his shown by using a dotted line. On the other hand, the wiring19functions together with a different wiring as a differential wiring.

Among all the inter-layer connection components18shown inFIG. 19, the inter-layer connection component18ais adjacent to the inter-layer connection component18b. On the other hand, when only the inter-layer connection components18connected to the first layer16hare considered, the inter-layer connection component18ais adjacent to the inter-layer connection component18cwhile putting the position corresponding to the inter-layer connection component18bbetween them.

In such a layout, the number Na of the wirings19that can be laid between the inter-layer connection component18aand the inter-layer connection component18bwill be described with reference toFIG. 21.FIG. 21shows the wirings19of the number Na laid between the inter-layer connection components18(18aand18b) adjacent to each other. It is supposed that the outer dimensions of the inter-layer connection components18aand18care D1and D2, respectively, a minimal space between the (n)-th and (n+1)-th wirings19in view of the designing and manufacturing rules is Gn, a width of the n-th wiring19is Wn, minimal spaces between the inter-layer connection components18and the wirings adjacent thereto are E1, E2, respectively, and a distance between the centers of the inter-layer connection components18is P. In this case, as shown inFIG. 21, the wirings can be arranged for the number that satisfies the equation of P≧{(W1+W2+ . . . +WNa-1+WNa)+(G1+G2+ - - - +GNa-1)+(E1)+(E2)+(D1+D2)/2}. Oppositely, the wirings for the number that can satisfy the above equation can be laid. It should be noted that the width of a segment exceeding 50% of the wiring length is defined as Wnin the above equation, when the wiring width Wnchanges in the middle of the wiring, as shown inFIGS. 22A and 22B. Also, if there is no segment exceeding 50%, the width of the segment having the longest length of the wiring is defined as Wn. In addition, if the inter-layer connection component18ais, for example, circular, the foregoing “outer dimension” indicates an “outer diameter”.

In the example shown inFIG. 19, the number Na of the wirings19that can be laid between the inter-layer connection component18aand the inter-layer connection component18cis 7 at the maximum because of the above-mentioned restraint on the number of wirings19. Actually, the 7 wirings19are laid. It should be noted that the inter-layer connection component18bis the blind via-hole that is not connected to the first layer16h, and does not prevent the arrangement of the wirings19.

On the other hand,FIG. 20shows an example when the inter-layer connection component18b′ is assumed to be a penetration through-hole, for the sake of a comparison. In the example shown inFIG. 20, the existence of the inter-layer connection component18b′ cannot be ignored. Thus, the maximal number Nb of the wirings that can be laid between the inter-layer connection components18a′ and18b′ is smaller than the number when the blind via-hole is used, and is 5.

In this way, as can be understood from the comparison betweenFIG. 19andFIG. 20, since the inter-layer connection component18bis the blind via-hole, many wirings, e.g., 7 wirings can be laid between the inter-layer connection components adjacent to each other in this embodiment.

Also, in the example shown inFIG. 20, the inter-layer connection component18b′ serves as an obstacle. Accordingly, there is a case that the width of the wiring19′ must be made thin between the inter-layer connection component18a′ and18′. When the wiring width is changed depending on the position, the characteristics of transmission signals are not uniform. That is, this example indicates that the wirings are not electrically uniform. On the contrary, in the example shown inFIG. 19, the wirings19are constant in width, and are the electrically uniform wirings. In particular, when the wiring19is the differential wiring, the wiring cannot be laid on a different layer. Therefore, as described in the example shown inFIG. 20, the width of the wiring19′ must be made thin and laid in many cases.

Moreover, in the example shown inFIG. 20, the wiring19′ is required to extend while being bent in order to avoid the inter-layer connection component18b′. The bent segment has influence on the characteristic impedance of the wiring pattern and results in the factor that degrades the quality of the transmission signal. On the contrary, in the example shown inFIG. 19, the wiring19can extend straightly, and the bent segment can be reduced, which is preferable from the viewpoint of the signal quality.

Next, the shapes of the layouts of the power source and ground layers will be described.FIG. 23shows a layout of the wiring layer16din the multi-layer printed circuit board according to this embodiment. That is,FIG. 23shows the layout of the power source layer. It should be noted that a layout of the ground layer that is the wiring layer16gis also similar. On the other hand,FIG. 24shows the shape of the power source layer in the example in which all of the inter-layer connection components18′ are assumed to be the penetration through-holes, for a comparison.

As can be understood from the comparison betweenFIG. 23andFIG. 24, since the inter-layer connection component18is the penetration through-hole, the number of the openings (the anti-pads) formed in the power source layer is decreased in this embodiment. That is, it is known that the impedance increase in the power source layer can be minimized since the area of the conductor can be set large.

Also, as described in this embodiment, the use of the blind via-hole improves the quality of the transmission signal from the viewpoint of a stub (branch). The quality of the transmission signal and the stub will be described with reference toFIGS. 25 to 27.FIG. 25shows a sectional shape of a printed circuit board when a penetration through-hole is used as the inter-layer connection component18. On the other hand,FIGS. 26 and 27are sectional views when the blind via-hole is used as the inter-layer connection component18. In all the examples shown inFIGS. 25 to 27, the wiring provided in the wiring layer16ois connected to the terminal mounted on the uppermost layer16lthrough the inter-layer connection component18. However, although the inter-layer connection component18penetrates through the board in the example shown inFIG. 25, the inter-layer connection component18only extends to the wiring layer16oin the example shown inFIG. 26. Also, in the example shown inFIG. 27, the inter-layer connection component18extended to the wiring layer16p.

In the example shown inFIG. 25, among the inter-layer connection components18, the segment (a stub29) between the wiring layer16oand the wiring layer16rserves as a capacitive load. Such a capacitive load results in a factor that degrades the quality of the transmission signal. On the contrary, in the examples shown inFIGS. 26 and 27, the stub segment is perfectly removed (FIG. 26) or reduced (FIG. 27). That is, since the inter-layer connection component18is formed as the blind via-hole, the stub29can be removed or reduced, which can prevent the quality degradation in the transmission signal that is caused by the existence of the stub.

Second Embodiment

Next, the multi-layer printed circuit board according to a second embodiment of the present invention will be described below with reference toFIGS. 28 to 32.FIGS. 28 to 32are diagrams showing the wiring layouts of the respective wiring layers in the multi-layer printed circuit board11according to this embodiment,FIG. 28shows a mounting surface20on which the memories are mounted,FIG. 29shows a rear surface21,FIG. 30shows an inner wiring layer22, andFIG. 31shows a power source and ground layer23. Also,FIG. 32is a sectional view of the multi-layer printed circuit board11. As shown inFIG. 32, the rear surface layer21, the power source and ground layer23, the inner wiring layer22and the mounting surface20are laminated in this order in the multi-layer printed circuit board11. This multi-layer printed circuit board11contains penetration through-holes and blind via-holes as the inter-layer connection components18.

As shown inFIG. 28, many terminals24for mounting the memories are arranged on the mounting surface20. Wirings25extending on the mounting surface20are connected to terminals24located on the outer side, among the terminals24. On the other hand, the wirings25extending from the inter-layer connection components18are connected to the terminals24located on the central side.

As shown inFIG. 30, in the inner wiring layer22, wirings26are connected to the inter-layer connection components18on the outer side. The wirings26are not connected to the inter-layer connection components18on the central side. The inter-layer connection components18on the central side are formed to penetrate through the power source and ground layer23and further extend to the rear surface21of the lowermost layer.

As shown inFIGS. 29 and 32, only the inter-layer connection components18on the central side are connected to the rear surface21. The wirings27extending on the rear surface21are connected to the inter-layer connection components18on the central side.

As shown inFIG. 31, in the power source and ground layer23, anti-pads28are formed only in the positions corresponding to the inter-layer connection components18on the central side. The inter-layer connection components18connected to the wirings26on the inner wiring layer22are not required to further extend to the lower layer side. Thus, this has no influence on a layout of the power source and ground layer23. In this embodiment, an area of the anti-pad region in the power source and ground layer23can be reduced, as compared with the penetration through-holes shown inFIG. 10. As a result, the area of a conductor region in the power source and ground layer23can be increased, which can suppress the impedance increase that is caused by the formation of the anti-pads28.

Although the present invention has been described above in connection with several embodiments thereof, it would be apparent to those skilled in the art that those embodiments are provided solely for illustrating the present invention, and should not be relied upon to construe the appended claims in a limiting sense.