Apparatus and method for ground fault monitoring

An apparatus for ground fault monitoring comprises a voltage bus, a high resistance midpoint grounding (HRMG) current limiting circuit, and a ground fault sense circuit. The voltage bus comprises a first and second voltage bus lines. The HRMG current limiting circuit comprises first and HRMG resistors. The HRMG current limiting circuit also comprises a positive sense resistor coupled across the base and emitter terminals of a first transistor and a negative sense resistor coupled across the base and emitter terminals of a second transistor. The ground fault sense circuit is configured to generate a ground fault signal indicative of a ground fault condition existing between the voltage bus and a common ground node.

TECHNICAL FIELD

Aspects of the disclosure relate to output power distribution, and more particularly to ground fault protection.

BACKGROUND

High voltage DC power can be used in applications requiring a lot of power. High voltage DC power supplies can provide high voltage such as, for example, 250 Vdc, 360 Vdc, 380 Vdc, 400 Vdc, and the like. Industries incorporating high voltage DC supplies include data centers and telecommunications applications, for example. In the case of a ground fault, current level limiting and shutoff time duration are important design parameters to eliminate or lessen high voltage effects that can be experienced via conduction exposure to a faulted system.

SUMMARY

In accordance with one aspect of the present disclosure, an apparatus for ground fault monitoring comprises a voltage bus, a power supply, a high resistance midpoint grounding (HRMG) current limiting circuit, and a ground fault sense circuit. The voltage bus comprises a first voltage bus line and a second voltage bus line. The power supply comprises a power generation device. The HRMG current limiting circuit comprises a first HRMG resistor coupled with the first voltage bus line, wherein a first current flowing through the first HRMG resistor from the first voltage bus line flows toward a common ground node and comprises a second HRMG resistor coupled with the second voltage bus line, wherein a second current flowing through the second HRMG resistor from the common ground node flows toward the second voltage bus line. The HRMG current limiting circuit also comprises a positive sense resistor and a negative sense resistor. The ground fault sense circuit comprises a first transistor having a base terminal and an emitter terminal, wherein the positive sense resistor is coupled across the base and emitter terminals of the first transistor, and comprises a second transistor having a base terminal and an emitter terminal, wherein the negative sense resistor is coupled across the base and emitter terminals of the second transistor. The ground fault sense circuit is configured to generate a ground fault signal indicative of a ground fault condition existing between the first voltage bus line and the common ground node and between the second voltage bus line and the common ground node.

In accordance with another aspect of the present disclosure, a method of generating a ground fault signal comprises supplying power to a voltage bus, the voltage bus comprises a first voltage bus line and a second voltage bus line, sensing a first current flowing between the first and second voltage bus lines via a negative sense resistor, and sensing a second current flowing between the first and second voltage bus lines via a positive sense resistor. The method further comprises controlling a first transistor into a conduction mode or a non-conduction mode based on the second current, controlling a second transistor into the conduction mode or the non-conduction mode based on the first current, generating a ground fault signal indicative of the absence of any ground fault condition in response to the first and second transistors being in the non-conduction mode, and changing the ground fault signal to indicate a ground fault condition in response to either of the first or the second transistors being in the conduction mode.

DETAILED DESCRIPTION

Examples of the present disclosure will now be described more fully with reference to the accompanying drawings. The following description is merely exemplary in nature and is not intended to limit the present disclosure, application, or uses.

FIG.1is a schematic block diagram illustrating a power circuit100with ground fault protection according to an example. The power circuit100includes a power supply unit101generating a high voltage and supplying the high voltage to a voltage bus102,103. For example, a controller104coupled to and controlling a voltage converter105causes the voltage converter105to supply a positive DC voltage to the positive bus line102and a negative DC voltage to the negative bus line102. The positive and negative DC voltages are positive and negative with respect to a common ground106. The voltage converter105can provide DC voltages of 250 Vdc, 360 Vdc, 380 Vdc, 400 Vdc, and the like. The high voltage provided to the voltage bus102,103is supplied to a load107coupled thereto.

With such high voltages, circuit protection is provided across the voltage bus102,103. A first protection circuit includes a high resistance midpoint grounding (HRMG) current limiting circuit108. The HRMG current limiting circuit108provides current limiting in the event that current flows from the positive voltage bus102or the negative voltage bus103to the common ground106, which may occur, for example, via a fault in the power supply101or via grounding of the positive or negative voltage bus102,103by a human being. To limit the current, the HRMG current limiting circuit108includes a first HRMG resistor109between the positive voltage bus102and the common ground106and includes a second HRMG resistor110between the negative voltage bus103and the common ground106.

While the HRMG current limiting circuit108functions to limit current in the case of coupling the positive or negative voltage bus102,103to the common ground106via a current path outside of the first and second HRMG resistors109,110, additional ground fault protection is provided via a ground fault sense circuit111. The ground fault sense circuit111is coupled to the HRMG current limiting circuit108to sense a ground fault between the positive voltage bus102and the common ground106and to sense a ground fault between the negative voltage bus103and the common ground106. The ground fault sense circuit111is also coupled with the controller104of the power supply101to supply a ground fault signal112to the controller104that indicates the absence or existence of a ground fault. In response to detecting in the ground fault signal112that a ground fault exists, the controller104may operate to shut down voltage generation by the voltage converter105in an example. Embodiments of the ground fault sense circuit111are described hereinbelow.

FIG.2is a schematic diagram of the power circuit100ofFIG.1with ground fault protection according to a first example. As shown, the HRMG current limiting circuit108includes additional resistors coupled in series with the first and second HRMG resistors109,110. A negative sense resistor113is serially coupled between the first HRMG resistor109and the common ground106on the positive voltage side. The node formed between the serially-coupled first HRMG and negative sense resistors109,113will be referred to herein as a negative sense node114. A positive sense resistor115is serially coupled between the second HRMG resistor110and the common ground106on the negative voltage side. The node formed between the serially-coupled second HRMG and positive sense resistors110,115will be referred to herein as a positive sense node116.

The ground fault sense circuit111includes a first transistor (Q1)117having its base terminal coupled with the common ground106, its emitter terminal coupled with the positive sense node116, and its collector terminal coupled to the ground fault signal line112. A second transistor (Q2)118has its base terminal coupled with the negative sense node114, its emitter terminal coupled with the common ground106, and its collector terminal coupled with the ground fault signal line112. A pull-up resistor119coupled between the ground fault signal line112and a positive voltage, VCC(e.g., 5V), provides an active-high logic level signal to the controller104in response to both the first and second transistors117,118being simultaneously in their off states (e.g., non-conducting modes).

When no ground fault condition exists between either of the positive or negative voltage buses102,103and the common ground106, the voltage across the positive and negative sense resistors115,113is below the threshold voltage (e.g., the voltage drop between the base and the emitter terminals) sufficient to cause either respective transistor117,118to transition into its on state (e.g., conducting mode). In one example, a resistance value of the positive and negative sense resistors115,113may be equal and set to a value such that the current that flows therethrough from the positive and negative voltage buses102,103causes the voltage across the sense resistors115,113to fall below the threshold. For example, for a base-emitter voltage drop of 0.7V, the operating voltage across the positive and negative sense resistors115,113may be 0.4V. Accordingly, neither transistor117,118transitions into its on state in the absence of a ground fault condition. As such, the ground fault signal112remains at a logic high level when no ground fault condition is in effect.

Circuit response to a positive side ground fault condition will now be described. A positive side ground fault can occur via the creation of an additional current path between the positive voltage bus102and the common ground106. The additional current path may be created via component failure in the power circuit100such as the component failure of one or more components of the voltage converter105in an example. In another example, a human being may touch the positive voltage bus102and create the additional current path to the common ground106. The additional current path can form a lower resistance path to the common ground106than the resistance of the current path formed by the first HRMG resistor109and the negative sense resistor113(i.e., a positive HRMG current path). Accordingly, current from the positive voltage bus102will prioritize the additional current path over the positive HRMG current path. As a result, current flowing in the current path formed by the second HRMG resistor110and the positive sense resistor115(i.e., a negative HRMG current path) increases, causing the voltage across the positive sense resistor115to increase. This increase raises the voltage level at or above the threshold voltage of the first transistor117, causing the first transistor117to turn on and bringing the logic level of the ground fault signal112to a logic low value. A Zener diode (D)120coupled between the base and emitter terminals of the first transistor117helps to maintain the ground fault signal112close to 0V (e.g., a diode voltage drop below ground) since the base terminal is coupled to ground and the voltage of the emitter terminal is below 0V (e.g., −0.7V) during the positive side ground fault condition. In response to the current from the positive voltage bus102prioritizing the additional current path over the positive HRMG current path, the current in the positive HRMG current path decreases, which further decreases the voltage across the negative sense resistor113. Thus, the base voltage of the second transistor118remains below its threshold voltage, and the second transistor118remains in the off state.

Circuit response to a negative side ground fault condition will now be described. A negative side ground fault can occur via the creation of an additional current path between the negative voltage bus103and the common ground106. As with the positive side ground fault condition, the additional current path may be created via component failure in the power circuit100such as the component failure of one or more components of the voltage converter105in an example. In another example, a human being may touch the negative voltage bus103and create the additional current path to the common ground106. The lower resistance additional current path causes current from the negative voltage bus103to prioritize the additional current path over the negative HRMG current path. As a result, current flowing in the current path formed by the first HRMG resistor109and the negative sense resistor113increases, causing the voltage across the negative sense resistor113to increase. This increase raises the voltage level at or above the threshold voltage of the second transistor118, causing the second transistor118to turn on and bringing the logic level of the ground fault signal112to a logic low value. In response to the current from the negative voltage bus103prioritizing the additional current path over the negative HRMG current path, the current in the negative HRMG current path decreases, which further decreases the voltage across the positive sense resistor115. Thus, the base voltage of the first transistor117remains below its threshold voltage, and the first transistor117remains in the off state.

As illustrated inFIG.2, the controller104receives the ground fault signal112from the ground fault sense circuit111. When the ground fault signal112is a logic high signal, no positive or negative side ground fault condition is in effect. Accordingly, the controller104may control the voltage converter105to operate in a normal operating condition according to its control conditions to generate the designed bus voltage to the load (FIG.1). However, in response to receiving a logic low signal from the ground fault sense circuit111via the ground fault signal112, the controller is configured to disable the supply of high voltage to the voltage bus102,103. In one embodiment, the controller104may control the voltage converter105to cease voltage generation via the voltage converter105. In another embodiment, the controller104may disconnect the supply of the high voltage to the voltage bus102,103while the voltage converter105continues to generate high voltage. The control by the controller104to cease the supply of high voltage to the voltage bus102,103ceases current flow between both of the positive and negative voltage buses102,103and the common ground106through any of the positive or negative HRMG current paths and the additional current path that initiated a ground fault condition.

FIG.3illustrates examplary ideal waveforms showing changes in a ground fault signal in response to activation of the ground fault protection ofFIG.2according to an example. In a first waveform121, example voltages of the base terminal of the second transistor (Q2)118are illustrated. A second waveform122illustrates example voltages of the base terminal of the first transistor (Q1)117. The example voltages of the ground fault signal112are illustrated in a third waveform123. The operating voltage of the voltage converter105is illustrated in a fourth waveform124.

During a first time period between t0and t1, no ground fault condition exists. As explained above, when no alternate current path exists between the voltage buses102,103and the common ground106, the base terminal voltages of the first and second transistors117,118remain below their respective threshold voltages. Thus, neither of the first or second transistors117,118is in a conduction mode. Accordingly, the ground fault signal112is at a logic high level during the first time period t0-t1.

At time t1, the positive side ground fault condition described herein is initiated. As explained above, during the positive side ground fault condition, the voltage level at or above the threshold voltage of the first transistor117causes the first transistor117to turn on and bring the logic level of the ground fault signal112to a logic low value. At some time t2after the start of the positive side ground fault condition at t1, the controller104causes the voltage converter105to cease delivery of the high DC voltage to the voltage buses102,103.

FIG.4illustrates examplary ideal waveforms showing changes in a ground fault signal in response to activation of the ground fault protection ofFIG.2according to another example. WhileFIG.3illustrates a positive side ground fault condition, the waveforms inFIG.4illustrate a negative side ground fault condition. Similar toFIG.3, no ground fault condition exists in the first time period between t0and t1. Thus, neither of the first or second transistors117,118is in a conduction mode, and the ground fault signal112is at a logic high level during the first time period t0-t1.

At time t1, the negative side ground fault condition described herein is initiated. As explained above, during the negative side ground fault condition, the voltage level at or above the threshold voltage of the second transistor118causes the second transistor118to turn on and bring the logic level of the ground fault signal112to a logic low value. At some time t2after the start of the negative side ground fault condition at t1, the controller104causes the voltage converter105to cease delivery of the high DC voltage to the voltage buses102,103.

FIG.5is a schematic diagram of the power circuit100ofFIG.1with ground fault protection according to a second example. Components and reference numerals in common with those discussed above with respect toFIG.2are illustrated inFIG.5, and circuit coupling and functionality for the common components may be referenced in the discussion above.

As shown, the HRMG current limiting circuit108includes no additional resistor between the first HRMG resistor109and the common ground106. A negative sense node126serially couples the negative sense resistor113to a third HRMG resistor125. A positive sense node128serially couples the positive sense resistor115to a fourth HRMG resistor127. The negative voltage bus103forms a negative HRMG node129coupled with each of the positive and negative sense resistors115,113.

The ground fault sense circuit111includes a first transistor (Q1)130having its base terminal coupled with the positive sense node128, its emitter terminal coupled with the negative HRMG node129, and its collector terminal coupled to the ground fault signal line112. A second transistor (Q2)131has its base terminal coupled with the negative sense node126, its emitter terminal coupled with the negative HRMG node129, and its collector terminal coupled with the base terminal of a third transistor132. The emitter terminal of the third transistor132is coupled with the negative HRMG node129, and its collector terminal is coupled with the ground fault signal line112. The collector terminal of the second transistor131and the base terminal of the third transistor132are further coupled with a second pull-up resistor133coupled to a pull-up voltage (e.g., VCC) and with a capacitor134coupled with the negative HRMG node129. The pull-up resistor133and the capacitor134serve as a turn on bias for the third transistor132and provide additional filtering. The first pull-up resistor119provides a high logic level signal (e.g., with respect to the negative HRMG node129) to the controller104in response to no ground fault condition existing during operation of the power circuit100.

When no ground fault condition exists between either of the positive or negative voltage buses102,103and the common ground106, the resistance value of the negative sense resistor113is designed to generate a voltage sufficient to meet at least the threshold voltage of the second transistor131to cause the second transistor131to be in or transition into its on state. As a result of being in its on state, the second transistor131causes the voltage supplied to the base terminal of the third transistor132to be below the transition voltage of the third transistor132. Thus, the third transistor132is in or transitions into its off state. The resistance value of the positive sense resistor115is designed to generate a voltage below the threshold voltage of the first transistor130such that the threshold voltage of the first transistor130is not met. In this manner, the first transistor130is in or transitions into its off state. With both of the first and third transistors130,132being in their off states, the high logic signal supplied through the pull-up resistor119is present on the ground fault signal line112during the absence of a ground fault condition.

Circuit response to a positive side ground fault condition will now be described. A positive side ground fault can occur as described herein. As a result of being in the positive side ground fault condition, current flowing in the negative HRMG node129is increased. Accordingly, the voltage generated across the positive sense resistor115is increased to at least the threshold voltage of the first transistor130so that the first transistor130transitions into its on state. Simultaneously, current flowing through the negative sense resistor113is also increased. However, since the threshold voltage of the second transistor131was previously met in the absence of the positive side ground fault condition, the second transistor131remains in its on state, and no state transition occurs in the second transistor131. With the transition of the first transistor130from its off state into its on state, the voltage level of the ground fault signal112changes from a logic high signal to a logic low signal. The controller104, sensing the logic level change, may react accordingly to control the high voltage supplied to the voltage bus102,103as described above.

Circuit response to a negative side ground fault condition will now be described. A negative side ground fault can occur as described herein. As a result of being in the negative side ground fault condition, current flowing in the negative HRMG node129is decreased in favor of flowing through the negative HRMG current path. The positive sense resistor115, already failing to generate a voltage sufficient to meet the threshold voltage of the first transistor130, generates an even lower voltage. Thus, the first transistor130remains in its off mode that existed during no ground fault condition. The voltage generated by the negative sense resistor113, however, changes from a value sufficient to meet the threshold voltage of the second transistor131to a value lower than the threshold voltage. Therefore, the generated voltage fails to maintain the voltage sufficient to keep the second transistor131in its on state. As a result, the second transistor131transitions into its off state. With the second transistor131in its off state, the pull-up resistor133coupling the base terminal of the third transistor132to the pull-up voltage (e.g., VCC) provides a voltage based on the pull-up voltage that is sufficient to at least meet the threshold voltage of the third transistor132. Thus, the third transistor132transitions into its on state and causes the voltage level of the ground fault signal112to change from a logic high signal to a logic low signal. The controller104may thus react accordingly to control the high voltage supplied to the voltage bus102,103as described above.

FIG.6illustrates examplary ideal waveforms showing changes in a ground fault signal in response to activation of the ground fault protection ofFIG.5according to an example. In a first waveform135, example voltages of the base terminal of the third transistor (Q3)132are illustrated. A second waveform136illustrates example voltages of the base terminal of the second transistor (Q2)131. A third waveform137illustrates example voltages of the base terminal of the first transistor (Q1)130. The example voltages of the ground fault signal112are illustrated in a fourth waveform138. The operating voltage of the voltage converter105is illustrated in a fifth waveform139.

During a first time period between t0and t1, no ground fault condition exists. As explained above, when no alternate current path exists between the voltage buses102,103and the common ground106, the base terminal voltages of the first and third transistors130,132remain below their respective threshold voltages. Thus, neither of the first or third transistors130,132is in a conduction mode. Accordingly, the ground fault signal112is at a logic high level during the first time period t0-t1.

At time t1, the positive side ground fault condition described herein is initiated. As explained above, during the positive side ground fault condition, the voltage level at or above the threshold voltage of the first transistor130causes the first transistor130to turn on and bring the logic level of the ground fault signal112to a logic low value. At some time t2after the start of the positive side ground fault condition at t1, the controller104causes the voltage converter105to cease delivery of the high DC voltage to the voltage buses102,103.

FIG.7illustrates examplary ideal waveforms showing changes in a ground fault signal in response to activation of the ground fault protection ofFIG.5according to another example. WhileFIG.6illustrates a positive side ground fault condition, the waveforms inFIG.7illustrate a negative side ground fault condition. Similar toFIG.6, no ground fault condition exists in the first time period between t0and t1. Thus, neither of the first or third transistors130,132is in a conduction mode, and the ground fault signal112is at a logic high level during the first time period t0-t1.

At time t1, the negative side ground fault condition described herein is initiated. As explained above, during the negative side ground fault condition, the voltage level at the base terminal of the second transistor131falls below the threshold voltage of the second transistor131. As a result, the second transistor131turns off and allows the voltage provided to the base terminal of the third transistor132to meet the threshold value of the third transistor132, which causes the third transistor132to turn on and bring the logic level of the ground fault signal112to a logic low value. At some time t2after the start of the negative side ground fault condition at t1, the controller104causes the voltage converter105to cease delivery of the high DC voltage to the voltage buses102,103.

Embodiments of the invention provide simple, low cost, and easy to install solutions that integrate with the electrical system of the power circuit100to provide intelligent shutdown of power generation and/or supply to the power bus102,103in response to a ground fault condition.

While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the present disclosure. Additionally, while various embodiments of the present disclosure have been described, it is to be understood that aspects of the present disclosure may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description but is only limited by the scope of the appended claims.