Dual flat non-leaded semiconductor package

A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.

BACKGROUND OF THE INVENTION

The present invention generally relates to semiconductor packages and more particularly to semiconductor packages and methods of making Dual Flat Non-Leaded (DFN) semiconductor packages.

Quad Flat Non-Leaded (QFN) semiconductor packages are well known in the art. QFN semiconductor packages are widely used in high pin out IC package applications. For example, a QFN semiconductor package is disclosed in U.S. patent application Publication 2002/0177254 entitled “Semiconductor Package and Method for Making the Same”. The disclosed semiconductor package includes a plurality of connection pads and an embedded die. The connection pads at least partially enclose a die receiving area. An insulator is disposed in the die receiving area and the die is attached to the insulator. The die has a plurality of die bond pads. A plurality of connectors connect the die bond pads to respective connection pads. An encapsulant at least partially encapsulates the connection pads, insulator and die. The connection pads and insulator have exposed surfaces on an outer surface of the encapsulant. The exposed surfaces are substantially co-planar with the outer surface of the encapsulant. A resulting semiconductor package is shown inFIG. 1AandFIG. 1B.

It has been proposed to use DFN semiconductor packages in power MOSFET applications. In power MOSFET applications a major concern relates to thermal and electrical performance as well as to thermally induced stresses to the semiconductor package. QFN packages of the prior art do not provide the requisite thermal properties for such applications.

There is therefore a need in the art for a DFN semiconductor package having good thermal and electrical performance properties. Preferably such a DFN semiconductor package provides for an effective thermal dissipation path. Preferably such a DFN semiconductor package provides for reduced electrical resistance and inductance.

SUMMARY OF THE INVENTION

In accordance with one aspect of the invention, a DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.

In accordance with another aspect of the invention, a DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead having an expanded area, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, the die bonding pad and drain lead providing a thermal dissipation path for the die, and an encapsulant covering the die, drain lead, gate lead and source lead.

In accordance with yet another aspect of the invention, a method of making a DFN semiconductor package includes the steps of forming a leadframe having a die bonding area with an integral drain lead, a gate lead and a source lead, bonding a die to the die bonding area, coupling a die source bonding area with the source lead, coupling a die gate bonding area with the gate lead, and encapsulating the die, the drain lead, the gate lead and the source lead.

DETAILED DESCRIPTION OF THE INVENTION

The present invention generally provides a power MOSFET DFN semiconductor package exhibiting improved thermal and electrical characteristics.

In a first aspect of the invention and with reference toFIG. 2A, a DFN semiconductor package generally designated200may include a leadframe210fabricated of copper, aluminum, nickel or other good electrical and thermal conductive material. Leadframe210may be fabricated using metal plating or general manufacturing techniques. Leadframe210may include a drain portion220fused to drain leads260, a source portion or lead230and a gate portion or lead240. A power MOSFET die250may be attached to a die bonding pad300(FIG. 3A). Drain portion220may include four drain leads260to provide a six lead package.

Power MOSFET die250may include a patterned active area including a source bonding area270and a gate bonding area280. A bottom portion of the power MOSFET die250(not shown) may include a drain bonding area.

With reference toFIG. 3A, the drain portion220includes the die bonding pad300integrally formed or fused with the drain leads260. When the drain bonding area of the power MOSFET die250is attached to the die bonding pad300using a conductive epoxy or solder, and considering that the drain portion220includes an exposed bottom portion720(FIG. 2B), a thermal dissipation path is provided.

The source lead230(FIG. 2A) may be larger than in conventional semiconductor packages to enable the use of an increased number of source wires285which preferably are formed from gold or copper. Increasing the number of source wires285advantageously decreases the semiconductor package200resistance significantly. Additionally, as the DFN semiconductor package200has no external leads, the overall size of the package is reduced allowing for the use of shorter source lead230, drain leads260and gate lead240thereby reducing package resistance and inductance.

The leadframe210, power MOSFET die250and source and gate wires285,290may be encapsulated by an encapsulant500formed or resin or other suitable material as shown inFIG. 5. Drain leads260, the gate lead240and the source lead230are shown disposed a distance internally of the encapsulant500. With reference toFIG. 6, a land pattern600for a PCB to which the DFN semiconductor package200may be mounted includes a standard pitch between drain lead mounting portions610and a standard dimension620. Disposing the drain leads260, the gate lead240and the source lead230a distance from an edge of the encapsulant500(FIG. 5AandFIG. 5B) provides for reduced short circuiting between devices and for higher device density.

In another aspect of the invention and with reference toFIG. 2B, a 15 DFN semiconductor package generally designated700may include the source lead230, the gate lead240and the drain leads260disposed at an edge of an encapsulant710.

In another aspect of the invention and with reference toFIG. 4, a DFN semiconductor package generally designated400includes a leadframe41020having an expanded drain portion420. Expanded drain portion420provides for an eight lead DFN semiconductor package400having six drain leads440.

In another aspect of the invention and with reference toFIG. 3B, a DFN semiconductor package generally designated800may include a first drain portion810and a second drain portion815having drain leads820and82525respectively. First drain portion810may include a first die bonding pad830integrally formed with the drain lead820and the second drain portion815may include a second die bonding pad835integrally formed with the drain lead825. First drain portion810may have associated therewith a first gate lead840and a first source lead845. First source lead845may include an expanded surface area to accommodate more source bonding wires. Second drain portion815may have associated therewith a second gate lead850and a second source lead855. Second source lead855may include an expanded surface area to accommodate more source bonding wires. The first drain portion810and the second drain portion815may fused together to provide a common drain device (not shown).

The DFN semiconductor package of the invention provides for a non-leaded semiconductor package having reduced resistance and inductance and improved thermal conductivity. By providing a source lead having an expanded surface area, an increased number of source wires may be used to reduce package resistance and inductance. Integrally forming the drain bonding pad with the drain leads provides a thermal dissipation path through the bottom of the DFN semiconductor package.