Specialized parity detection system for wide memory structure

A parity detection scheme for a wide memory structure of RAM memory chips provides an auxiliary RAM parity memory chip to store parity data for each corresponding input line of each memory chip corresponding for each address of each memory chip. This parity data is compared to comparable parity data which is read-out of any corresponding address of each of said memory chips.

FIELD OF THE INVENTION 
This disclosure relates to circuitry and systems for proving out data 
transfer integrity when data bits are placed in a wide memory structure 
which can be verified by use of specialized parity check circuitry. 
CROSS REFERENCES TO RELATED APPLICATIONS 
This disclosure is related to other patent applications involving similar 
subject matter as follows: 
U.S. Ser. No. 848,073, filed Apr. 4, 1986 by inventors Dongsung R. Kim and 
Reinhard K. Kronies, entitled "Parity Detection System for Wide Bus 
Circuitry", which issued as U.S. Pat. No. 4,710,935 on Dec. 1, 1987. 
U.S. Ser. No. 904,443, filed Sept. 8, 1986 by inventors Dongsung R. Kim and 
Reinhard K. Kronies, and entitled "Enhanced Parity Detection for Wide 
ROM/PROM Memory Structure". 
BACKGROUND OF THE INVENTION 
Many types of memory chip structures are used in the course of digital 
circuitry, the simplest memory structure of which is when the memory chips 
are merely one bit wide. For example, a memory with organization such as a 
4K by 1 represents the situation where the memory structure is one bit 
wide and the memory unit can store 4,092 bits of memory and each 
individual bit-space can be addressed in order to output the particular 
data bit which resides in that memory space. 
The conventional parity check detection circuitry which is used for such a 
memory structure (which is made up by one bit wide memory chips) is 
provided by adding a single parity bit to each word wherein the parity bit 
is stored into the memory together with the written-in word during the 
Write time. Subsequently, when the particular word and its parity bit is 
read out, then a new parity check is accomplished by checking the parity 
for the particular word that was read out during the Read time. 
This scheme works adequately as long as the memory chips used are merely 
one bit wide in their organization since, in this case, any single chip 
failure would result in a single bit failure and thus be detected by the 
Read-out of the word and its parity bit. 
However, increasingly today, the memory chips used in memory structure are 
organized according to multi-bit widths, such as 1K by 4. Under these 
conditions the normal detection scheme of adding a parity bit to the 
writing of a wide word and then detecting the parity bit after the reading 
out of the word would cause the system to miss many single chip failures 
since this can result in no failure to a 4 bit failure. 
Since the memory structures used very often consist of multi-bit width 
memory chips, as for example, in such designs as control stores and 
look-up tables, it is most desirable to have a more accurate parity 
detection scheme to overcome the inaccuracies inherent in the prior types 
of parity checking.

DESCRIPTION OF A PREFERRED EMBODIMENT 
As seen in FIG. 1, a typical multi-bit wide memory structure is shown 
wherein a series of units shown as multiple width RAM chips, 20.sub.1, 
20.sub.2 --20.sub.q are shown to provide a structured memory storage unit 
20 which is fed by a bus from a source means along a number (n) of data 
bit lines. 
Each memory chip address may be "m" bits for 2.sup.m locations, and each 
line-group of 4 bit lines of the memory data bus is fed into the four data 
inputs to the RAM memory chip. These inputs, as shown in FIG. 1, are 
designated as chip bit k.sub.0, k.sub.1, k.sub.2, and k.sub.3. The inputs 
to RAM 20.sub.q would be designated as k.sub.q0, k.sub.q1, k.sub.q2, and 
k.sub.q3. 
As seen in FIG. 1, the RAM memory structure is provided with an address bus 
10 which is used to select which specific locations in the individual 
memory chips will be used for data to be temporarily stored. Additionally, 
each RAM memory chip has a Write enable (WE) line which selects whether 
the memory can be written into or can be read-out from. 
Thus, the series of "n" memory data bus lines carrying data bits (FIG. 1) 
are shown at the left as coming from a source and then being input into 
addressed locations in a series of memory chip units after which they can 
be read out and placed on the memory bus of "n" lines for transfer to a 
destination. The source means, for example, may be a processor which has 
an output data bus of "n" lines. Likewise, the destination means may, for 
example, consist of an external memory unit which receives data on the bus 
having "n" bit-lines. 
As will be seen in FIG. 1, each memory chip has an input set of "four" 
lines, which number of inputs may be designated as "k" since the memory 
chip may have more or less than the 4 lines shown. Thus, the letter "k" 
will designate the number of data bit lines such that each particular 
memory chip is characterized as having k input lines and k output lines. 
It will be noted that each bit k.sub.0 of each of the memory chips is 
connected to an exclusive OR gate 30. Likewise, each k.sub.1 bit line of 
the RAM memory chips is connected to an exclusive OR gate 31. Likewise, 
bit k.sub.2 for each of the memory chip inputs is connected to an 
exclusive OR gate 32 and each input bit k.sub.3 of each of the memory 
chips is connected to the exclusive OR gate 33. 
Each of the exclusive OR gates 30 through 33 will provide a particular 
parity output signal designated as P.sub.0, P.sub.1, P.sub.2 and P.sub.3. 
These may be designated as a first set of resultant parity data. These 
outputs are fed to the RAM parity memory chip 22 in a fashion which 
correlates the input bit k with the corresponding input bit k of each of 
the series of RAM memory chips. 
On the output side of the RAM memory chips 20.sub.1 through 20.sub.q, there 
is the Read-out side of the memory bus. In a similar fashion to the input 
or Write-in side, the Read-out side of the memory bus provides connections 
which connect each corresponding k bit line of each memory chip to a 
particular exclusive OR gate. Thus, the exclusive OR gate 40 connects all 
the k.sub.0 lines; the exclusive OR gate 41 connects all the k.sub.1 bit 
lines; the exclusive OR gate 42 connects each of the k.sub.2 bit lines; 
while the exclusive OR gate 43 connects each of the bit lines k.sub.3. 
Additionally, it will be seen that the co-relating "k" outputs of the 
auxiliary RAM parity memory chip 22 also connect the correspondng bit 
lines to exclusive OR gates 40, 41, 42 and 43. 
The second set of exclusive OR gates have respective resultant parity data 
lines designated PE.sub.0, PE.sub.1, PE.sub.2 and PE.sub.3. These series 
of output lines are fed to an OR gate 50, whereby any inconsistency 
between the outputs of the corresponding parity chip bit lines of RAM 
parity chip 22 and the corresponding parity sum of k output lines of each 
memory chip will cause a resultant parity error signal to occur at the 
moment of inconsistency. 
As will be noted from the connections shown in FIG. 1, the RAM parity 
memory chip 22 has a series of address locations which correspond to the 
same set of address locations in the RAM memory chips 20.sub.1, 20.sub.2 
--20.sub.q. 
Thus, for each set of input data on the source lines which are placed in a 
particular address in the wide memory structure of the memory system, 
there will also be written-in a set of corresponding bits P.sub.0, 
P.sub.1, P.sub.2 and P.sub.3 which will be placed in the corresponding 
address location inside the RAM parity memory chip 22. 
Thereafter, on the Read operation, when a specific memory area is addressed 
in order to place data bits on the destination side of the memory 
structure, it will be seen that the same particular memory area is 
addressed on the RAM parity memory chip in order to provide an output of 
parity bits which correspond to that particular address. These then can be 
transmitted to each of the exclusive OR gates 40, 41, 42 and 43 for 
comparison with the other inputs to each of these gates in order to see 
whether parity consistency has been maintained or there is a parity error. 
If there is an inconsistency in any one of the inputs to gates 40 through 
43, then the parity error signal PE.sub.0, PE.sub.1, PE.sub.2 or PE.sub.3 
will indicate this parity error such that any difference in the states of 
the parity error output lines will be revealed by the OR gate 50 in order 
to provide a parity error signal on line 52. 
Thus, it can be seen that if a memory structure is made of memory chips 
that are k bits wide and the number of data bit lines in the bus is "n" 
lines, then it will be seen that if "n" is divided by "k", the number of 
memory chips required can be given the value of "q". 
Thus, "q" equals "n" divided by "k" (q=n/k). 
The particular parity detection scheme involved provides that even though 
multi-width memory structures are used, there will be no loss of accuracy 
in parity detection should an entire memory chip fail or should one 
portion of a memory chip fail. 
In any case, any type of failure in the memory chip will be detected by the 
parity detection system, since each bit line of data on the input or 
"Write" side is checked to provide a parity bit to the RAM parity chip 
which can then be checked with its corresponding bit line data on the 
"Read" or output side of the memory structure in order to provide a parity 
error output signal which can be used to flag a suitable processor unit in 
order to reschedule or retry the data transmission. 
There has been described herein a specialized parity detection scheme for a 
wide memory structure which overcomes the difficulties which are presented 
when using the standard parity type detection scheme wherein each word of 
memory is provided with a parity bit which is then read out of memory with 
its parity bit and checked to see whether the read-out parity checks with 
the written-in parity bit to overcome the limitations whereby the old 
standard-type parity detection scheme, which system could not be 
completely accurate in its detection of misduplication or lost bits in the 
course of writing into and reading out of a memory structure. 
While certain variations of the above described concepts may be made in 
structure, it should be understood that the disclosed invention is to be 
defined and encompassed by the following claims: