Method for high speed sensing for extra low voltage DRAM

A method and apparatus are provided for sensing in low voltage DRAM memory cells. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first and second NMOS transistor, each having a source and a first and second PMOS transistor, each having a source. The method further includes the steps of maintaining the voltage of the sources of the first and second NMOS transistors at a first voltage during normal operation and lowering the voltage of the sources of the first and second NMOS transistors from the first voltage to a second voltage during a read operation.

FIELD OF THE INVENTION

The invention relates to electrical circuits and more specifically to DRAM memory circuits and sensing the state thereof.

BACKGROUND

In a dynamic random access memory (“DRAM”), data is stored as a logic high value (e.g., “1”) or logic low value (e.g., “0”) by the presence or absence of charge on a capacitor within an individual memory cell. After the data has been stored as a charge on the capacitor, the charge gradually leaks off and the data becomes corrupted. Therefore, a “refresh” cycle must be performed before passage of sufficient time for the data to become corrupted, to maintain the integrity of the data.

To read data from a memory array, the array is typically placed in a read mode to obtain the data currently stored in a row of memory cells. An individual datum is typically accessed through the cell address, which identifies a memory cell by its row and column in the array.

FIG. 1illustrates a prior art DRAM circuit100having a first storage bit132and a second storage bit126. First storage bit132is passed by a first PMOS transistor130, and second storage bit126is passed by a second PMOS transistor128. PMOS transistor130is coupled to sense amplifier102via bit line BL, and PMOS transistor128is coupled to sense amplifier102via bit line bar ZBL. Sense amplifier102includes pre-charge circuit104, back-to-back inverter112and two NMOS transistors122,124, which have their gates tied to column selection line SL. Pre-charge circuit104is comprised of three NMOS transistors106,108,110, which have their gates tied to equalization line EQ.

The back-to-back inverter112is comprised of two PMOS transistors114,116and two NMOS transistors118,120. Both NMOS transistors118,120have low threshold voltages for reasons discussed below. The gates of NMOS transistor120and PMOS transistor116are tied together and coupled to both the bit line bar ZBL and the drains of NMOS transistor118and PMOS transistor114, which are also tied together. The gates of NMOS transistor118and PMOS transistor114are tied together and coupled to the bit line BL, and the drains of NMOS transistor120and PMOS transistor116, which are also tied together. The sources of the PMOS transistors114,116are tied together, as are the sources of the NMOS transistors118,120. The sources of the PMOS transistors114,116are also coupled to a high voltage source VDDvia line SP and PMOS transistor134. PMOS transistor134has its gate connected to control line CL1. The sources of the NMOS transistors118,120are coupled to ground VSSvia line SN.

With reference toFIGS. 1 and 2, the reading of a “0” from the first storage bit132of prior art DRAM circuit100is now discussed. Initially at time t=0, DRAM circuit100is in normal operation (i.e., retaining previously stored data, but not being written to, read from or refreshed) and equalization line EQ is coupled to a logic “1” signal, When equalization line EQ is coupled to a logic “1,” the three NMOS transistors106,108,110of pre-charge circuit104are in the “on” state, and lines ZBL and BL are charged to the voltage of VBL, The voltage of VBLis typically half the voltage of VDD(assuming a VSSvoltage of 0.0 volts). Also in this state, control line CL1is connected to a high voltage signal, which turns PMOS transistor134to the “off” state resulting in VDDbeing disconnected from sense amplifier112.

The read cycle begins at time t=1, when equalization line EQ is coupled to a logic “0” signal. PMOS transistor130, which controls the first storage bit132, is selected by transitioning line WL from a high voltage to low voltage. The transition of line WL from a high voltage to a low voltage turns PMOS transistor130from the “off” state to the “on” state. With PMOS transistor130on, the voltage of the first storage bit132is then coupled to bit line BL. Since bit line BL has a larger bit line capacitance than the capacitance of the capacitor of the first bit132, the voltage of line BL is pulled down slightly.

Line SP is then coupled to VDDby having control line CL1transition from a high voltage to a low voltage, which transitions PMOS transistor134from the “off” state to the “on” state. With PMOS transistor134on, the voltage of VDDis then connected to the gates of both PMOS transistors114and116of the back-to-back inverter112, thereby changing the PMOS transistors114,116from the “off” state to the “on” state. The turning on of PMOS transistors114and116pulls down the voltage of line BL while the voltage of line ZBL is pulled up. The pulling down of line BL and pulling up of line ZBL occurs because VDDpulls up the voltage of line ZBL via PMOS transistor114, and VSSpulls down the voltage of line BL via NMOS transistor120.

FIG. 2is a diagram showing voltage versus time and illustrates certain signals of DRAM circuit100as they transition during the normal operating phase and the read phase. Of particular interest are the signals of lines ZBL and BL as they illustrate the slow transitioning from their initial voltage level at VBLat time t−1 to their respective voltage levels at VDDand VSSat time t=2. As illustrated inFIG. 2, the transition of both BL and ZBL from their initial voltage to their final voltages is slow, as the slopes of the lines indicate a gradual transition.

Due to the continually shrinking size of integrated circuits, the operating voltage VDDis continually being reduced, which reduces the ability of VDDto pull up ZBL. The reduced ability of VDDto pull up ZBL results in a delay in the transition of ZBL (an increase in the time between t=1 and t=2), and slowing the speed at which the circuit functions.

Some attempts to speed up the pulling up of ZBL by VDDhave been made, including boosting the voltage level of VDDduring the reading cycle. However, the boosting of VDDduring the reading cycle increases power consumption of the DRAM circuit and does not dramatically speed up the reading time of a “0” from the storage bit. To help increase the ability of VSSto pull down the voltage on line BL, NMOS transistors118,120are typically low threshold voltage transistors. Manufacturing circuits with different threshold voltages requires additional manufacturing processing, as all of the transistors of the circuit cannot be formed by the same steps. The additional manufacturing steps, such as additional photolithographic steps, drive up the time and cost of production.

Therefore, it is desirable in the art to provide an apparatus and method which overcomes the disadvantages of the prior art.

SUMMARY OF THE INVENTION

An improved DRAM circuit and a method for high speed sensing in extra low voltage DRAM circuits are described herein. In one embodiment the DRAM circuit comprises at least one memory cell including a capacitor, a transistor and at least one sense amplifier. The at least one sense amplifier includes a pre-charge circuit and a back-to-back inverter. The back-to-back inverter has at least one PMOS transistor and at least one NMOS transistor, wherein the source of the at least one PMOS transistor is coupled to a first voltage source which has a voltage higher than ground. The source of the at least one NMOS transistor is coupled to a switch, wherein the switch is operable to connect the source of the NMOS transistor to one of a second voltage source set at ground and a third voltage source set at a negative voltage relative to the voltage of the second voltage source.

In another exemplary embodiment, the DRAM circuit comprises at least one memory cell and at least one sense amplifier connected to the memory cell. The at least one sense amplifier includes a pre-charge circuit connected to a first voltage source and a back-to-back inverter connected to the pre-charge circuit. The back-to-back inverter comprises a first PMOS transistor having a source, a second PMOS transistor having a source, a first NMOS transistor having a source and a second NMOS transistor having a source. The sources of the first and second PMOS transistors are connected to a second voltage source and the sources of the first and second NMOS transistors are configured to selectively connect to one of a third positive voltage source and a fourth voltage source having a lower voltage than the voltage of the third voltage source.

In another exemplary embodiment, the disclosure relates to a method of high speed sensing of a DRAM circuit comprising the steps of providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first NMOS transistor having a source, a second NMOS transistor having a source, a first PMOS transistor having a source and a second PMOS transistor having a source. The method further includes the steps of maintaining the voltage of the sources of the first and second NMOS transistors at a first voltage during normal operation and lowering the voltage of the sources of the first and second NMOS transistors from the first voltage to a second voltage during a refresh operation.

DETAILED DESCRIPTION

This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description.

FIG. 3illustrates an exemplary DRAM circuit300according to one embodiment of the present invention. Note that a DRAM circuit generally includes multiple DRAM cells and various additional periphery circuitry (e.g., write circuitry, word line decoders, digital line decoders, additional equalization, and the like). However, for the purposes of clarity and brevity, additional DRAM cells and periphery circuitry are not shown or described herein.

DRAM circuit300includes a first storage bit302and a second storage bit306. First storage bit302is coupled to a PMOS transistor304, which is also coupled to bit line BL. Second storage bit306is coupled to a PMOS transistor308, which is also coupled to the bit line bar ZBL. Sense amplifier310is connected to both the first storage bit302and second storage bit306via the bit line BL and the bit line bar ZBL. Sense amplifier310includes a pre-charge circuit312, a back-to-back inverter320and two NMOS transistors330,332. The gates of NMOS transistors330and332are coupled to the column selection line SL. Pre-charge circuit312includes three NMOS transistors314,316,318, each having its gate coupled to the equalization line EQ.

Back-to-back inverter320includes two PMOS transistors322,324and two NMOS transistors326,328. NMOS transistors326and328may be formed by the same process as all of the other MOS transistors in DRAM circuit300because NMOS transistors326and328do not need to have low threshold voltages. Because all of the MOS transistors of the exemplary DRAM cell300may be made by the same process, and the extra photolithography steps (that were used for low threshold voltage NMOS) are no longer required, the process time and expense of manufacturing DRAM cell300are reduced. The gates of PMOS transistor322and NMOS transistor326are tied together and connected to both the bit line BL and the drains of PMOS transistor324and NMOS transistor328. The drains of PMOS transistor324and NMOS transistor328are also tied together. The gates of PMOS transistor324and NMOS transistor328of back-to-back inverter320are tied together and connected to the bit line bar ZBL and the drains of PMOS transistor322and NMOS transistor326, which are also tied together. The sources of PMOS transistors322and324are tied together and coupled to a high voltage source VDDvia line SP and PMOS transistor340, which has its gate tied to control line CL1. The sources of the NMOS transistors326and328are tied together and coupled to a switch334via line SN.

Switch334is operable between two voltage sources, VBBand VSS, which are set at different voltages. VSSis typically set at ground, and VBBis set at a voltage lower than that of VSS. In a preferred embodiment, VBBis set to a negative voltage between approximately −0.2 volts and −0.4 volts (assuming VSS=0.0 volts). However, those skilled in the art will appreciate that other suitable voltages for VBBmay be used. Switch334may be implemented through a variety of methods. In a preferred embodiment, switch334includes two NMOS transistors336,338coupled together at a node342. Node342is also connected to line SN as illustrated inFIG. 3. The gate of NMOS transistor336is coupled to control line CL2, and the gate of NMOS transistor338is coupled to control line CL3. When the DRAM circuit300is in the normal operating mode (i.e., retaining previously stored data, but not being written to, read from or refreshed), switch334connects line SN is to VSS. In a preferred embodiment, line SN is coupled to VSSby connecting line CL2to a high voltage signal to turn on NMOS transistor336, and connecting control line CL3to a low voltage signal to turn off NMOS transistor338. When a read or refresh sequence is performed, switch334is coupled to VBBas explained below.

With reference toFIG. 3, which is an exemplary schematic of a DRAM circuit, andFIG. 4, which illustrates a timing diagram of the DRAM circuit, the reading operation of a “0” in the first storage bit302is now described. At time t=0, circuit300is in the normal operation state, in which it is retaining previously stored data, but is not reading, writing or refreshing a storage bit. In this mode, the equalization line EQ is high, which turns on NMOS transistors314,316and318of the pre-charge circuit312. This results in lines ZBL and BL being pre-charged with the voltage of VBL. In a preferred embodiment, voltage VBLis generally from about 0.5VDDto approximately 0.55VDD, although other voltages may be used. Also in this mode, switch334is coupled to line SN, and is configured to couple line SN with VSS, which is set at ground. The coupling of line SN with VSSis accomplished by having a high voltage signal on control line CL2which turns on NMOS transistor336, and having a low voltage signal on control line CL3, which turns off NMOS transistor338. With NMOS transistor336on and NMOS transistor338off, the voltage of VSSdevelops at node342. Also in this state, line SP is disconnected from VDDby having a high voltage signal on control line CL1, which turns off PMOS transistor340. With line SP floating and line SN set at ground, both of the PMOS transistors322,324and NMOS transistors326,328of the back-to-back inverter320are in the “off” state.

When a read or refresh of DRAM circuit300is initiated, line EQ is turned to the “off” state by connecting it to ground. This causes the voltages of BL and ZBL to float at approximately VBL. At time t=1, line WL is used to turn PMOS transistor304on, by transitioning it from a high voltage to a low voltage. However, alternative embodiments (not shown) utilize other transistors (instead of PMOS transistors) to couple capacitors302and306to lines BL and ZBL, respectively. When line WL transitions from high to low at time t=1, PMOS transistor304turns on, and the voltage of the connected capacitor302starts to develop on line BL. Line SP is then coupled to VDDby transitioning the voltage signal on CL1from a high voltage signal to a low voltage signal, which turns on PMOS transistor340. Line SN is switched from VSSto VBBvia switch334. The orientation of switch334is changed by transitioning line CL2from a high voltage signal to a low voltage signal turning off NMOS transistor336, and by transitioning line CL3from a low voltage signal to a high voltage signal to turn on NMOS transistor338. With NMOS transistor338in the “on” state, the voltage of node342is pulled down to the voltage of VBB.

Because the voltage of VBBis approximately −0.2V to about −0.4V, the voltage difference between line SN and line SP is greater than the voltage difference would be if line SN were coupled to ground. This enables line BL to more quickly transition down from VBLto a logic “0”. In addition to line BL transitioning from VBLto a logic “0” state more quickly, more charge can be removed from the capacitor302. With less charge on the capacitor, the “0” logic value stored in memory is more definite because a larger voltage difference exists between the capacitor and the pre-charge voltage VBL. Accordingly, the more definite the “0” value in storage is, the less frequently the cell needs to be refreshed, because it takes longer for sufficient charge to leak onto the capacitor to result in an indefinite signal. Since the circuit needs to be refreshed less frequently, the power consumed by the circuit is reduced.FIG. 4illustrates the transition of line BL from VBLat time t=1 to a logic “0” state at time t=2. The steep slope of line BL from time t=1 to time t=2 is faster than the transitioning of BL illustrated in the circuit100inFIG. 2.

FIG. 5is a diagram of voltage versus time comparing the transition of various signals for the read or refresh cycle of a logic “0” state of circuit100with the same signals in circuit300. The read or refresh of the value of capacitors132and302are illustrated inFIG. 5where time is designated as the x-axis and voltage is designated as the y-axis. DRAM circuits100and300are in the normal operation mode at time t=0. At this time, line EQ is a logic “1” and lines BL and ZBL are charged with VBL. At time t=1, line EQ begins to transition from a high to a low as the read or refresh cycle commences. The value “0” recorded in bits132,302begins to develop on bit line BL at time t=2 and soon thereafter line ZBL begins to be pulled high by PMOS transistors114and322of circuit100and the exemplary embodiment circuit300, respectively. At time t=3, line BL of the circuit300has been pulled all the way to zero; however, in contrast, line BL of prior art circuit100is still transitioning to zero.

FIG. 6illustrates an exemplary DRAM circuit600according to another embodiment. With regards toFIGS. 3 and 6, like features in the two figures are indicated by a reference numeral inFIG. 6having the same two least significant digits as the feature inFIG. 3, but increased by300. For example, transistor604inFIG. 6can be the same structure as transistor304inFIG. 3. DRAM circuit600includes a first storage bit602and a second storage bit606. First storage bit602is coupled to a PMOS transistor604, which is also coupled to bit line BL. Second storage bit606is coupled to a PMOS transistor608, which is also coupled to the bit line bar ZBL. Sense amplifier610is connected to both the first storage bit602and second storage bit606via the bit line BL and the bit line bar ZBL, respectively. Sense amplifier610includes a pre-charge circuit612, a back-to-back inverter620and two NMOS transistors630and632. The gates of NMOS transistors630and632are coupled to the column selection line SL. Pre-charge circuit612includes three NMOS transistors614,616,618, each having its gate coupled to the equalization line EQ.

Back-to-back inverter620includes two PMOS transistors622and624and two NMOS transistors626and628. The gates of PMOS transistor622and NMOS transistor626are tied together and connected to both the bit line BL and the drains of PMOS transistor624and NMOS transistor628, which are also tied together. The gates of PMOS transistor624and NMOS transistor628of back-to-back inverter620are tied together and connected to the bit line bar ZBL and the drains of PMOS transistor622and NMOS transistor626, which are also tied together. The sources of PMOS transistors622and624are tied together and coupled to a switch644via line SP. Likewise, the sources of the NMOS transistors626and628are tied together and coupled to a switch634via line SN.

Switch644is operable between two voltage sources VDDand VPP, which are both set to voltages higher than ground. In a preferred embodiment, VPPis set at a voltage from about VDD+0.2 volts to about VDD+0.6 volts. Switch644may be implemented through a variety of methods. In a preferred embodiment, switch644includes two PMOS transistors646,648coupled together at a node650. Node650is also connected to line SP as illustrated inFIG. 6. The gate of PMOS transistor646is coupled to control line CL1, and the gate of PMOS transistor648is coupled to control line CL4. When the DRAM circuit600is in the normal operating mode (i.e., retaining previously stored data, but not being written to, read from or refreshed), line SP is coupled to VDDthrough switch644. In a preferred embodiment, line SP is coupled to VDDby connecting control line CL4to a low voltage signal, which turns on PMOS transistor648, and connecting control line CL1to a high voltage signal, which turns off PMOS transistor646. When a read or refresh sequence is performed, switch644is coupled to VPPby transitioning the voltage signal on control line CL4from a low voltage to a high voltage and transitioning the voltage signal on control line CL1from a high voltage to a low voltage.

The reading operation of a “0” in the first storage bit602of exemplary DRAM circuit600is now described. Initially, DRAM circuit600is in the normal operation state, in which it is retaining previously stored data, but is not reading, writing or refreshing a storage bit. In this mode, the equalization line EQ is high, which turns on NMOS transistors614,616and618of the pre-charge circuit612. This results in lines ZBL and BL being pre-charged with the voltage of VBL. In a preferred embodiment, voltage VBLis generally from about 0.5VDDto approximately 0.6VDD, although other voltages may be used. Also in this mode, switch634is coupled to line SN, and is configured to couple line SN with VSS, which is set at ground. The coupling of line SN with VSSis accomplished by having a high voltage signal on control line CL2which turns on NMOS transistor636, and having a low voltage signal on control line CL3, which turns off NMOS transistor638. With NMOS transistor636on and NMOS transistor638off, the voltage of VSSdevelops at node642.

Also in this state, line SP is floating by disconnecting SP from VDDand VPPby having high voltage signals on control lines CL1and CL4. In the active region (sensing region) control line CL1is on, and a high voltage is applied. In the equalize region nodes line SN, line SP, bit line BL, and bit line bar ZBL are pulled to VBL. A high voltage signal on control line CL1turns off PMOS transistor646, and a high voltage signal on control line CL4turns off PMOS transistor648. Both of the PMOS transistors622,624and NMOS transistors626,628of the back-to-back inverter620are in the “off” state.

When a read or refresh of DRAM circuit600is initiated, line EQ is turned to the “off” state by connecting it to ground. This causes the voltages of BL and ZBL to float at approximately VBL. Then, line WL is used to turn PMOS transistor604on, by transitioning it from a high voltage to a low voltage. However, alternative embodiments (not shown) utilize other transistors (instead of PMOS transistors) to couple capacitors602and606to lines BL and ZBL, respectively. When line WL transitions from high to low, PMOS transistor604turns on, and the voltage of the connected capacitor602begins to develop on bit line BL. Line SP is then coupled to VDDby transitioning the voltage signal on control line CL1from a high voltage signal to a low voltage signal, turning on PMOS transistor648. Line SN is switched from VSSto VBBvia switch634. The orientation of switch634is changed by transitioning control line CL2from a high voltage signal to a low voltage signal turning off NMOS transistor336, and by transitioning control line CL3from a low voltage signal to a high voltage signal to turn on NMOS transistor338. With NMOS transistor338in the “on” state, the voltage of node642is pulled down to the voltage of VBB. In the active region (sensing region) CL1and CL3are in the “on” state, and CL4,CL3are in the “off” state. Thus, VPPand VBBare applied. In the equalize region (word line WL turned off) nodes SN, SP, BL, ZBL are all pulled to VBLWith respect to the reading speed at low voltage, while in the writing mode or refresh mode, SP/SN do not switch to VPP/VBB, and instead just use VDDand VSS.

Because the voltage of VBBis approximately −0.2V to about −0.4V, the voltage difference between line SN and line SP is greater than the voltage difference would be if line SN were coupled to ground. This enables line BL to more quickly transition down from VBLto a logic “0”. In addition to line BL transitioning from VBLto a logic “0” state more quickly, more charge can be removed from the capacitor302. With less charge on the capacitor, the “0” logic value stored in memory is more definite because a larger voltage difference exists between the capacitor and the pre-charge voltage VBL. Accordingly, the more definite the “0” value in storage is, the less frequently the cell needs to be refreshed, because it tales longer for sufficient charge to leak onto the capacitor to result in an indefinite signal. Since the circuit needs to be refreshed less frequently, the power consumed by the circuit is reduced.