DISPLAY PANEL AND DISPLAY DEVICE

Provided is a display panel. The display panel includes: a base substrate; a plurality of pixel units disposed on the base substrate, wherein the pixel unit includes a pixel circuit and a light-emitting element; a constant voltage line, configured to provide a constant voltage to the pixel circuit; and a plurality of shield electrodes, wherein at least one of the plurality of shield electrodes corresponds to at least one pixel circuit, an orthographic projection of the at least one of the plurality of shield electrodes on the base substrate is at least partially overlapped with an orthographic projection of the corresponding at least one pixel circuit on the base substrate, at least part of the plurality of shield electrodes are connected, and the at least part of the plurality of shield electrodes are electrically connected to the constant voltage line.

TECHNICAL FIELD

The present disclosure relates to the field of display devices, and particularly relates to a display panel and a display device.

BACKGROUND OF THE INVENTION

Organic light-emitting diode (OLED) display panels are common display panels and are more and more widely applied in display devices such as mobile phones, tablet computers, digital cameras and the like, due to the advantages of self-luminance, wide viewing angle, high contrast, low power consumption, high response speed, and the like.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure provide a display panel and a display device. The technical solutions are as follows.

According to some embodiments of the present disclosure, a display panel is provided. The display panel includes:a base substrate;a plurality of pixel units disposed on the base substrate, wherein the pixel unit includes a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element;a constant voltage line, configured to provide a constant voltage to the pixel circuit; anda plurality of shield electrodes, wherein at least one of the plurality of shield electrodes corresponds to at least one pixel circuit, an orthographic projection of the at least one of the plurality of shield electrodes on the base substrate is at least partially overlapped with an orthographic projection of the corresponding at least one pixel circuit on the base substrate, at least part of the plurality of shield electrodes are connected, and the at least part of the plurality of shield electrodes which are connected are electrically connected to the constant voltage line.

In some embodiments, the plurality of shield electrodes include a plurality of groups of shield electrodes, wherein each group of the plurality of groups of shield electrodes is extended in a first direction, and the plurality of groups of shield electrodes are arranged in a second direction, the first direction intersecting the second direction, and both the first direction and the second direction being parallel to the base substrate.

In some embodiments, the at least part of the plurality of shield electrodes are connected by a connecting portion, wherein the connecting portion includes at least one of:a first connecting portion connected between at least two of the plurality of shield electrodes that are arranged in the first direction;a second connecting portion connected between at least two of the plurality of shield electrodes that are arranged in the second direction; anda third connecting portion connected between at least two of the plurality of shield electrodes that are arranged in a third direction, the third direction intersecting the first direction and the second direction, and being parallel to the base substrate.

In some embodiments, the first direction is an extension direction of the constant voltage line.

In some embodiments, the base substrate is provided with a first display region and a second display region, the first display region being on at least one side of the second display region;the pixel unit includes a first pixel unit and a second pixel unit, whereinthe first pixel unit is disposed in the first display region;the pixel circuit of the second pixel unit is disposed in the first display region, the light-emitting element of the second pixel unit is disposed in the second display region, and the pixel circuit and the light-emitting element of the second pixel unit are connected by a conductive line; andin a direction perpendicular to the base substrate, the shield electrode is disposed between the conductive line and the pixel circuit.

In some embodiments, the first display region includes a main display region and an auxiliary display region, wherein the main display region is on at least one side of the auxiliary display region, and the auxiliary display region is adjacent to the second display region; andthe pixel circuit of the second pixel unit is disposed in the auxiliary display region.

In some embodiments, the shield electrode connected to the constant voltage line is disposed in the main display region or the auxiliary display region.

In some embodiments, the display panel further includes: a first power line, a first initialization signal line and a reset control signal line;wherein the pixel circuit includes a drive transistor, a first gate signal line, a second gate signal line, a first reset transistor, and a storage capacitor; whereina first electrode of the drive transistor is connected to the first power line, a gate of the drive transistor is connected to the first gate signal line, the first gate signal line is connected to the second gate signal line, the second gate signal line is connected to a second electrode of the first reset transistor, a first electrode of the first reset transistor is connected to the first initialization signal line, and a gate of the first reset transistor is connected to the reset control signal line; anda first electrode of the storage capacitor is connected to the gate of the drive transistor, and a second electrode of the storage capacitor is connected to the first power line.

In some embodiments, in the second direction, the second electrodes of the storage capacitors of adjacent pixel circuits are connected with each other, at least two of the shield electrodes arranged in the second direction are connected by the second connecting portion, and an orthographic projection of the second connecting portion on the base substrate is at least partially overlapped with an orthographic projection of a connecting portion between the connected second electrodes on the base substrate; or

in the second direction, the second electrodes of the storage capacitors of adjacent pixel circuits are spaced apart.

In some embodiments, an orthographic projection of at least one of following structures on the base substrate is at least partially within an orthographic projection of the shield electrode on the base substrate:the gate of the drive transistor;the first gate signal line;the second gate signal line;the second electrode of the first reset transistor; anda connecting portion between the second electrode of the storage capacitor and the first power line.

In some embodiments, the display panel further includes: a gate line and a data line; wherein the pixel circuit further includes a data writing transistor; wherein a gate of the data writing transistor is connected to the gate line, a first electrode of the data writing transistor is connected to the data line, and a second electrode of the data writing transistor is connected to the first electrode of the drive transistor.

In some embodiments, the pixel circuit further includes a threshold compensation transistor and a block; wherein a first electrode of the threshold compensation transistor is connected to the second electrode of the drive transistor, and a second electrode of the threshold compensation transistor is connected to the second gate signal line, and a gate of the threshold compensation transistor is connected to the gate line;the threshold compensation transistor includes a first channel and a second channel, the first channel and the second channel being connected by a conductive connecting portion; andthe block is connected to the first power line, and an orthographic projection of the block on the base substrate is at least partially overlapped with an orthographic projection of the conductive connecting portion on the base substrate.

In some embodiments, the block is connected to the first power line through a second via hole, wherein an orthographic projection of the second via hole on the base substrate is at least partially within an orthographic projection of the shield electrode on the base substrate.

In some embodiments, the orthographic projection of the block on the base substrate is partially overlapped with an orthographic projection of the second gate signal line on the base substrate.

In some embodiments, the display panel further includes: a light-emitting control signal line, wherein the pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor; whereina gate of the first light-emitting control transistor is connected to the light-emitting control signal line, a first electrode of the first light-emitting control transistor is connected to the first power line, and a second electrode of the first light-emitting control transistor is connected to the first electrode of the drive transistor; anda gate of the second light-emitting control transistor is connected to the light-emitting control signal line, a first electrode of the second light-emitting control transistor is connected to the second electrode of the drive transistor, and a second electrode of the second light-emitting control transistor is connected to the light-emitting element.

In some embodiments, the display panel further includes: a second initialization signal line, wherein the pixel circuit further includes a second reset transistor; wherein a gate of the second reset transistor is connected to the reset control signal line, a first electrode of the second reset transistor is connected to the second initialization signal line, and a second electrode of the second reset transistor is connected to the second electrode of the second light-emitting control transistor.

In some embodiments, the constant voltage line includes the first power line or the first initialization signal line.

In some embodiments, the shield electrode includes an Al layer, a Mo layer, or an Al layer and a Ti layer that are alternately laminated.

According to some embodiments of the present disclosure, a display device is provided. The display device includes the display panel described above.

DETAIL DESCRIPTION

To make the objectives, technical solutions, and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the accompanying drawings.

Terms used in the embodiments of the present disclosure are only used to illustrate the embodiments of the present disclosure, but not intended to limit the present disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of the present disclosure have the general meanings as usually understood by those of ordinary skill in the art to which the present disclosure pertains. “First”, “second”, “third”, and similar words used in this specification and in the claims do not denote any order, quantity or importance, but are merely intended to distinguish between different constituents. Similarly, the terms “one”, “a/an”, and similar words are not meant to be limiting, but rather denote the presence of at least one. “Comprising”, “including”, and similar words mean that element or article appearing before “comprising” or “including” includes the elements or articles and their equivalent elements appearing behind “comprising” or “consisting”, without excluding any other elements or articles. “Connected to”, “connected with”, and similar expressions are not restricted to physical or mechanical connections, but includes direct and indirect electrical connections. “Upper”, “lower”, “left”, “right”, and the like are only used to indicate a relative positional relationship, and when the absolute position of the described object is changed, the relative positional relationship is changed accordingly.

In a display device, a front camera occupies the space of a display panel, which reduces the screen-to-body ratio. In some display devices, the under-screen camera technology is adopted to arrange the camera under the display panel, so as to prevent the camera from affecting the screen-to-body ratio. The under-screen camera technology is a new technology for increasing the screen-to-body ratio of a display device.

FIG.1is a schematic structural diagram of a display panel in the related art. As shown inFIG.1, the display region of the display panel generally includes a first display region R1and a second display region R2. The second display region R2is a light-transmissive display region and corresponds to the under-screen camera. A light-emitting element and a pixel circuit are arranged in the first display region R1, while only the light-emitting element is arranged in the second display region R2, and no pixel circuit is arranged in the second display region R2. The pixel circuit configured to drive the light-emitting element arranged in the second display region R2is arranged in the first display region R1, in order to reduce blocking of light by the pixel circuit and increase light transmission of the second display region R2, thereby improving the photographing effect of the under-screen camera.

The light-emitting element in the second display region R2is connected to the pixel circuit in the first display region R1by a conductive line, that is, the conductive line extends from the second display region R2to the first display region R1. The conductive line and the pixel circuit in the first display region R1are coupled to each other to form capacitance, which affects the display effect of a partial region of the display panel. In the related art, a shield electrode is provided in the display panel to isolate the pixel circuit from the conductive line, thereby reducing the influence on the display effect. However, when the shield electrode is provided, the shield electrode needs to be connected to a constant voltage line providing a constant voltage. However, the shield electrode is usually connected to the constant voltage line via a via hole. With many via holes being provided, not only the difficulty of manufacturing a display panel is increased, but also the region above the via holes is recessed, resulting in the structures in the region above the via holes to be uneven.

FIG.2is a schematic structural diagram of a display panel according to some embodiments of the present disclosure. As shown inFIG.2, the display panel includes a base substrate BS and a plurality of pixel units100. The pixel units100are disposed on the base substrate BS.FIG.2illustratively shows only three pixel units100.

The base substrate BS is provided with a first display region R1and a second display region R2. The first display region R1is on at least one side of the second display region R2. For example, in some embodiments, the first display region R1surrounds the second display region R2. That is, the second display region R2is surrounded by the first display region R1.

The position of the second display region R2is set based on demands. For example, in the embodiments of the present disclosure, the second display region R2is in the middle at the top of the base substrate BS. In other embodiments, the second display region R2also is on the left or on the right at the top of the base substrate BS.

The second display region R2is a light-transmissive display region. In the display device, a photosensitive sensor, e.g., a camera, is arranged in correspondence to the second display region R2. The second display region R2is light-transmissive to some extent such that the camera corresponding to the second display region R2is capable of photographing normally and is also capable of displaying. The first display region R1is configured to display.

FIG.3is a schematic diagram of a pixel unit according to some embodiments of the present disclosure. As shown inFIG.3, the pixel unit100includes a pixel circuit100aand a light-emitting element100b. The pixel circuit100ais configured to drive the light-emitting element100b. For example, the pixel circuit100ais configured to provide a driving current to drive the light-emitting element100bto emit light. Different light-emitting elements emit the same or different colors of light. Generally, the plurality of light-emitting elements100binclude a plurality of red light-emitting elements, a plurality of green light-emitting elements, and a plurality of blue light-emitting elements. Some display panels further include light-emitting elements that emit other colors of light, such as white light-emitting elements. The specific color of light emitted by the light-emitting element is set according to the display requirements of the display panel.

In order to increase the light transmittance of the second display region R2, only the light-emitting element is disposed in the second display region R2, and the pixel circuit driving the light-emitting element of the second display region R2is disposed in the first display region R1. That is, the light-emitting element and the pixel circuit are arranged separately in order to increase the light transmittance of the second display region R2.

FIG.4is a schematic structural diagram of a display panel according to some embodiments of the present disclosure. As shown inFIG.4, in the display panel, the pixel unit100includes a first pixel unit101and a second pixel unit102. The light-emitting element and pixel circuit of the first pixel unit101are both disposed in the first display region R1; the pixel circuit100aof the second pixel unit102is disposed in the first display region R1, and the light-emitting element100bof the second pixel unit102is disposed in the second display region R2.

In the embodiments of the present disclosure, the first pixel unit101includes a first light-emitting element30and a first pixel circuit10. The second pixel unit102includes a second light-emitting element40and a second pixel circuit20. The first pixel unit101is disposed in the first display region R1. The second pixel circuit20of the second pixel unit102is disposed in the first display region R1, and the second light-emitting element40of the second pixel unit102is disposed in the second display region R2.

The second pixel circuits20are spaced apart between the plurality of first pixel circuits10. For example, in the embodiments of the present disclosure, at most one second pixel circuit20is disposed between adjacent two first pixel circuits10.

The second light-emitting element40and the second pixel circuit20of the same second pixel unit102are disposed in the same row. For example, as shown inFIG.4, the second light-emitting element40and the second pixel circuit20connected to the second light-emitting element40are disposed in the same row. That is, the light-emitting signals of the second light-emitting elements40come from the same row of second pixel circuits20.

In the embodiments of the present disclosure, since the second pixel circuit20driving the second light-emitting element40is disposed in the first display region R1, the second display region R2has higher light transmittance, and the under-screen camera corresponding to the second display region R2can receive enough ambient light for normal photographing, without the need to form holes in the display panel, or perform other processing on the display panel. With the second light-emitting element40in the second display region R2, the second display region R2still has the display capability, and thus the display panel has a better display effect.

The second pixel circuit20and the second light-emitting element40are connected by a conductive line L1, and the conductive line L1extends from the first display region R1to the second display region R2. One end of the conductive line L1is connected to the second pixel circuit20, and the other end of the conductive line L1is connected to the second light-emitting element40.

In some embodiments, the conductive line L1is made from a transparent conductive material. For example, the conductive line L1is made from a conductive oxide material. The conductive oxide material includes, but is not limited to, indium tin oxide (ITO). By making the conductive line L1with a transparent conductive material, the conductive line L1blocks less light, thereby reducing the effect of the conductive line L1on the display effect.

In some embodiments, the distribution density of the second light-emitting elements40in the second display region R2is the same as the distribution density of the first light-emitting elements30in the first display region R1. The distribution density of the light-emitting elements refers to the number of the light-emitting elements distributed in a unit area. The higher the distribution density, the higher the resolution, whereas the lower the distribution density, the lower the resolution. The distribution density of the second light-emitting elements40is the same as the distribution density of the first light-emitting elements30, that is, the resolution of the second display region R2is the same as the resolution of the first display region R1. The resolution of the first display region R1is the same as the resolution of the second display region R2, which can further improve the display effect of the display panel.

In other embodiments, the distribution density of the second light-emitting elements40is greater than or less than the distribution density of the first light-emitting elements30. That is, the resolution of the second display region R2is greater or less than the resolution of the first display region R1.

The light-emitting area of a single second light-emitting element40is the same as the light-emitting area of a single first light-emitting element30. The light-emitting area of the light-emitting element refers to the area of the orthographic projection of the light-emitting region of the light-emitting element on the base substrate BS. The light-emitting area has a certain effect on luminance. In order to achieve the same luminance, the light-emitting element with a smaller light-emitting area usually needs to be driven by a larger current or voltage, while the lifetime of the light-emitting element will be shortened when it's driven by a larger current or voltage. In the present disclosure, since the light-emitting area of the second light-emitting element40is the same as the light-emitting area of the first light-emitting element30, the second light-emitting element40and the first light-emitting element30are driven by the current at the same strength or voltage at the same strength, such that the lifetime of the second light-emitting element40approximates the lifetime of the first light-emitting element30.

In some other embodiments, the light-emitting area of the single second light-emitting element40is smaller than the light-emitting area of the single first light-emitting element30, to further increase the light transmittance of the second display region R2, thereby increasing the photographing effect of the under-screen camera.

As shown inFIG.4, each pixel unit100further includes a connecting element CE0. Each pixel circuit100ais connected to the light-emitting element100bby the connecting element CE0. That is, the first pixel circuit10is connected to the first light-emitting element30by a connecting element CE0, and the second pixel circuit20is connected to the second light-emitting element40by a connecting element CE0.

FIG.5is a schematic diagram of a conductive line in a display panel according to some embodiments of the present disclosure.FIG.5illustratively shows a plurality of conductive lines L1. The plurality of conductive lines L1are disposed in the same conductive line pattern layer. For example, the plurality of conductive lines L1are formed of the same conductive layer through a patterning process. Alternatively, the plurality of conductive lines L1are disposed in several different conductive line pattern layers, different conductive line pattern layers are separated from each other by an insulating layer, and the conductive lines L1in the same conductive line pattern layer are formed of the same conductive layer through the patterning process. A plurality of conductive line pattern layers are provided to prevent the conductive lines L1in the same conductive line pattern layer from being too dense, thereby reducing the accuracy requirement of the patterning process performed on the conductive line pattern layer. In some other embodiments, the same conductive line L1is disposed in different conductive line pattern layers. For example, one conductive line L1includes two segments disposed in two conductive line pattern layers, and the two segments are connected through a via hole.

Referring toFIG.2, the first display region R1includes a main display region Rb and an auxiliary display region Ra. The main display region Rb is on at least one side of the auxiliary display region Ra, and the auxiliary display region Ra is adjacent to the second display region R2. For example, in the embodiments of the present disclosure, the main display region Rb surrounds the auxiliary display region Ra, that is, the auxiliary display region Ra is surrounded by the main display region Rb. The auxiliary display region Ra surrounds the second display region R2. The second pixel circuit20is disposed in the auxiliary display region Ra.

The pixel circuit of the second pixel unit102is disposed in the region adjacent to the second display region R2, such that the second pixel circuit20and the second light-emitting element40can be connected by a shorter conductive line L1, which makes it easier to arrange the circuit structure of the display panel. In addition, the shorter conductive line L1has smaller resistance.

In other embodiments, the first display region R1only includes the main display region Rb, and the second pixel circuit20is disposed in the main display region Rb. For example, the second pixel circuits20and the first pixel circuits10are alternately arranged in the main display region Rb, and the conductive line L1extends from the main display region Rb to the second display region R2.

Two ends of the conductive line L1are connected to the second pixel circuit20and the second light-emitting element40. For example, one end of the conductive line L1is connected to the second pixel circuit20through a via hole, and the other end of the conductive line L1is connected to the second light-emitting element40through a via hole.

FIG.6is a schematic structural diagram of a display panel according to some embodiments of the present disclosure. As shown inFIG.6, there is an overlapping region between the conductive line L1and the pixel circuit100athat is disposed between the second pixel circuit20and the second light-emitting element40, that is, the orthographic projection of the conductive line L1on the base substrate BS is partially overlapped with the orthographic projection of the pixel circuit100aon the base substrate BS. As a result, the conductive line L1and the pixel circuit100awhich are overlapped with each other are coupled to form parasitic capacitance, resulting a luminance difference between some of the light-emitting elements, thereby resulting in display defects, such as mura. In the auxiliary display region Ra, the conductive line L1and the pixel circuit are coupled with each other, which easily causes the auxiliary display region Ra to be darker. For example, the auxiliary display region Ra is significantly darker at a high grayscale than at a lower grayscale.

As shown inFIG.6, in order to avoid the defects caused by the parasitic capacitance formed due to the coupling between the conductive line L1and the pixel circuit100a(e.g., the first pixel circuit10and the second pixel circuit20inFIG.6) which are overlapped with each other, the display panel further includes a constant voltage line L0and a plurality of shield electrodes SE. The constant voltage line L0is configured to provide a constant voltage to the pixel circuit100a.

At least one shield electrode SE corresponds to at least one pixel circuit100a. The orthographic projection of the shield electrode SE on the base substrate BS is at least partially overlapped with the orthographic projection of the corresponding at least one pixel circuit100aon the base substrate BS. The shield electrode SE is electrically connected to the constant voltage line L0, that is, the shield electrode SE can maintain a constant potential under the action of the constant voltage line L0, thereby playing a shielding effect, which can reduce the coupling between the conductive line L1and the pixel circuit100a.

In a direction perpendicular to the base substrate BS, the shield electrode SE is disposed between the conductive line L1and the pixel circuit100a. That is, in the direction perpendicular to the base substrate BS, the shield electrode SE separates the conductive line L1from the pixel circuit100a, such that the shield electrode SE plays a better shielding effect. In the embodiments of the present disclosure, after the pixel circuit is formed, the shield electrode SE is formed first, the conductive line L1is formed, and then the light-emitting element is formed, such that the shield electrode SE is disposed between the conductive line L1and the first gate signal line SL1.

In the embodiments of the present disclosure, the shield electrodes SE are distributed in the main display region Rb and the auxiliary display region Ra. The second pixel circuit20is disposed in the auxiliary display region Ra, such that the conductive line L1extends directly from the auxiliary display region Ra to the second display region R2without passing through the main display region Rb. That is, the conductive line L1is disposed between the auxiliary display region Ra and the second display region R2. The conductive line L1basically does not interact with the pixel circuit in the main display region Rb, and the shield electrode SE in the auxiliary display region Ra plays a shielding effect for the conductive line L1and the pixel circuit100a. In addition, the shield electrode SE is also provided in the main display region Rb to ensure the consistency between patterns in the patterning process. Therefore, the patterns are also formed and the shield electrodes SE are manufactured in the main display region Rb.

As shown inFIG.6, the plurality of shield electrodes SE include a plurality of groups of shield electrodes. Each group of the plurality of groups of shield electrodes extends in a first direction Y, and the plurality of groups of shield electrodes are arranged in a second direction X. The first direction Y and the second direction X intersect and are both parallel to the base substrate BS. In the embodiments of the present disclosure, the second direction X is perpendicular to the first direction Y. That is, the plurality of shield electrodes SE are distributed in an array in a plurality of rows and a plurality of columns. The column direction is the first direction Y, and the row direction is the second direction X.

As shown inFIG.6, at least part of the shield electrodes SE are connected, and in the connected shield electrodes SE, part of the shield electrodes SE are connected to the constant voltage line L0. For example, part of the shield electrodes SE are connected to the constant voltage line L0through a first via hole H21, as shown inFIG.6.

The shield electrodes SE are connected with each other by a connecting portion.FIG.7is a schematic structural diagram of three connected shield electrodes according to some embodiments of the present disclosure. As shown inFIG.7, a second connecting portion SE2is provided between at least two shield electrodes SE arranged in the second direction X, and the shield electrodes SE arranged in the second direction X are connected with each other by the second connecting portion SE2. One of the shield electrodes SE is connected to the constant voltage line L0through the first via hole H21. InFIG.7, no second connecting portion SE2is provided on the left side of the shield electrode SE connected to the constant voltage line L0. However, in other embodiments, the second connecting portion SE2is provided on the left side of the shield electrode SE connected to the constant voltage line L0, such that the shield electrodes SE are connected with the adjacent shield electrodes SE on two sides by the second connecting portion SE2.

At least part of the plurality of shield electrodes SE are connected with each other such that several shield electrodes are connected as a whole. For example,FIG.6illustratively shows six shield electrodes SE which are connected as a whole. In the connected shield electrodes SE, only part of the shield electrodes SE are connected to the constant voltage line L0through the via holes. For example, inFIG.6, in the six connected shield electrodes SE, only one shield electrode SE is connected to the constant voltage line L0through a via hole. Compared with the case where each shield electrode SE is connected to the constant voltage line L0through a via hole, the total number of the via holes is reduced, and the manufacturing difficulty is reduced.

As each conductive line L1is overlapped with a plurality of pixel circuits100a, and one pixel circuit100aalso is overlapped with a plurality of conductive lines L1, the conductive line L1is directly above the via hole. As described above, the region above the via hole is recessed, resulting in the structures in the region above the via hole to be uneven, which affects the manufacture of the conductive line L1. For example, when the conductive line L1is manufactured through the patterning process, during exposure, the amount of exposure in the recess and the amount of exposure outside the recess is somewhat different. As a result, the line width of the formed conductive line L1in the recess and the line width outside the recess are unequal, which affects the signals transmitted in the conductive line L1. In the embodiments of the present disclosure, at least part of the plurality of shield electrodes SE are connected with each other, and in the connected shield electrodes SE, only part of the shield electrodes SE are connected to the constant voltage line L0through the via holes, which reduces the total number of the via holes and alleviates the situation that the traces above the via holes become thinner. For example, as shown inFIG.7, the number of the via holes is reduced, and thus the possibility that the conductive line L1is directly above the via hole is reduced, thereby alleviating or even avoiding the situation that the line widths of the conductive line L1are unequal.

As shown inFIG.6, the plurality of shield electrodes SE arranged in the direction which is parallel to the base substrate BS and intersects the extension direction of the constant voltage line L0are connected with each other. In the embodiments of the present disclosure, the constant voltage line L0extends in the first direction Y, and the plurality of shield electrodes SE arranged in the second direction X are connected with each other.

The orthographic projection of the first light-emitting element30on the base substrate BS is at least partially overlapped with the orthographic projection of the first pixel circuit10on the base substrate BS.

As shown inFIG.6, the shield electrode SE connected to the constant voltage line L0is disposed in the main display region Rb.

In the embodiments of the present disclosure, the plurality of shield electrodes SE disposed in the same row in the auxiliary display region Ra are connected with each other, and the shield electrodes SE disposed in the same row in the main display region Rb are connected to the constant voltage line L0. That is, no first via hole H21is provided in the auxiliary display region Ra. The second pixel circuit20is disposed in the auxiliary display region Ra, that is, the conductive line L1extends from the auxiliary display region Ra to the second display region R2. In this way, the conductive line L1is completely prevented from passing right above the first via hole H21, and the first via hole H21is also prevented from adversely affecting the conductive line L1.

In some other embodiments, the plurality of shield electrodes SE in the same column are connected with each other. For example,FIG.8is a schematic diagram showing distribution of shield electrodes according to some embodiments of the present disclosure. As shown inFIG.8, a first connecting portion SE1is provided between at least two shield electrodes SE arranged in the first direction Y, that is, the first connecting portion SE1is provided between adjacent shield electrodes SE arranged in the same column, and the adjacent shield electrodes SE are connected by the first connecting portion SE1.

For example,FIG.9is a schematic diagram showing distribution of shield electrodes according to some embodiments of the present disclosure. As shown inFIG.9, a third connecting portion SE3is provided between at least two shield electrodes SE arranged in a third direction. The third direction intersects the first direction Y and the second direction X, and is parallel to the base substrate BS. The third direction is inclined relative to the first direction Y and the second direction X, and the plurality of shield electrodes SE in adjacent two rows are sequentially connected in a misaligned manner by a plurality of third connecting portions SE3.

For example,FIG.10is a schematic diagram showing distribution of shield electrodes according to some embodiments of the present disclosure. As shown inFIG.10, the display panel is provided with both the first connection portion SE1and the second connecting portion SE2, such that the plurality of shield electrodes SE are connected into a mesh.

For example,FIG.11is a schematic diagram showing distribution of shield electrodes according to some embodiments of the present disclosure. As shown inFIG.11, the display panel is provided with both the second connecting portion SE2and the third connecting portion SE3, such that the plurality of shield electrodes SE are connected into a mesh.

The display panel is provided with at least one of the first connecting portion SE1, the second connecting portion SE2, and the third connecting portion SE3, to connect the plurality of shield electrodes SE. For example, the first connecting portion SE1and the third connecting portion SE3also are provided.

FIG.12is a circuit diagram of a pixel circuit according to some embodiments of the present disclosure. The pixel circuit is a common low temperature poly-silicon (LTPS) AMOLED pixel circuit in the related art. In some embodiments, the pixel circuit is a 7T1C circuit, including 7 transistors and 1 capacitor. In some other embodiments, the pixel circuit is a 7T2C circuit, a 6T1C circuit, a 6T2C circuit, or a 9T2C circuit, and the embodiments of the present disclosure are illustrated by taking the 7T1C circuit as an example.

As shown inFIG.12, the pixel circuit includes six switching transistors, one drive transistor T1and one storage capacitor Cst. The six switching transistors includes a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, and a second reset transistor T7. The transistor includes a gate, a first electrode and a second electrode. One of first electrode and the second electrode of the transistor is a source and the other one is a drain. The light-emitting element100bincludes a first electrode E1, a second electrode E2, and a light-emitting functional layer disposed between first electrode E1and second electrode E2. For example, the first electrode E1is an anode and the second electrode E2is a cathode. Generally, the threshold compensation transistor T3and the first reset transistor T6adopt a dual-gate thin film transistor (TFT) to reduce the leakage current.

The display panel further includes a gate line GT, a data line DT, a first power line PL1, a second power line PL2, a light-emitting control signal line EML, a first initialization signal line INL1, a second initialization signal line INL2, a reset control signal line RST, and the like. For example, in other embodiments, the reset control signal line RST includes two types of reset control signal lines, i.e., a first reset control signal line and a second reset control signal line. The first reset control signal line is configured to control the first reset transistor T6and the second reset control signal line is configured to control the second reset transistor T7.

The gate line GT is configured to provide a scan signal SCAN to the pixel unit100.

The data line DT is configured to provide a data signal DATA, i.e., a data voltage VDATA, to the pixel unit100.

The first power line PL1is configured to provide a constant first voltage signal VDD to the pixel unit100, and the second power line PL2is configured to provide a constant second voltage signal VSS to the pixel unit100. The potential of the first voltage signal VDD is higher than the potential of the second voltage signal VSS.

The light-emitting control signal line EML is configured to provide a light-emitting control signal EM to the pixel unit100.

The first initialization signal line INL1is configured to provide a first initialization signal Vinit1to the pixel unit100. The second initialization signal line INL2is configured to provide a second initialization signal Vinit2to the pixel unit100. For example, the first initialization signal Vinit1and the second initialization signal Vinit2are constant voltage signals, and the magnitude of the first initialization signal Vinit1and the magnitude of the second initialization signal Vinit2maybe between, but are not limited to be between, the first voltage signal VDD and the second voltage signal VSS. For example, the potential of the first initialization signal Vinit1and the potential of the second initialization signal Vinit2are lower than or equal to the potential of the second voltage signal VSS.

In some embodiments, the first initialization signal line INL1and the second initialization signal line INL2are connected to each other, and are both configured to provide the initialization signals Vinit to the pixel unit100. That is, the first initialization signal Vinit1and the second initialization signal Vinit2are equal, both being Vinit.

The reset control signal line RST is configured to provide a reset control signal RESET1or RESET2to the pixel unit100.FIG.13is a schematic structural diagram of a pixel circuit according to some embodiments of the present disclosure. The pixel circuit shown inFIG.13corresponds to the first pixel circuit10that is in the upper right corner ofFIG.6and connected to the constant voltage line L0. In the two first reset transistors T6shown inFIG.13, the first reset transistor T6in the lower part is the first reset transistor T6in the row of pixel circuits adjacent to the pixel circuit shown inFIG.13. In the two second reset transistors T7shown inFIG.13, the second reset transistor T7in the upper part is the second reset transistor T7in another row of pixel circuits adjacent to the pixel circuit shown inFIG.13. In the embodiments of the present disclosure, in the pixel units in different rows, for example, in the pixel units in adjacent two rows, the gate T60of the first reset transistor T6in the pixel circuit in one row of pixel units and the gate T70of the second reset transistor T7in the pixel circuit in the other row of pixel units are connected to the same reset control signal line RST, such that the reset control signal line RST can be reused to control the first reset transistor T6and the second reset transistor T7. When the first reset transistor T6is reset, the reset control signal line RST connected to the gate T60of the first reset transistor T6provides the reset control signal RESET1, and when the second reset transistor T7is reset, the reset control signal line RST connected to the gate T70of the second reset transistor T7provides the reset control signal RESET2.

The reset control signal line RST is also configured to provide other signals. For example, in some embodiments, the first reset transistor T6is controlled by means of the first reset control signal line and the second reset transistor T7is controlled by means of the second reset control signal line. In this case, the first reset control signal line is configured to provide a reset control signal to the first reset transistor T6, and the second reset control signal line is configured to provide a scan signal SCAN to the second reset transistor T7.

As shown inFIG.12, the drive transistor T1is electrically connected to the light-emitting element100b, and the drive transistor T1is configured to output a driving current under the action of the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS, or the like, so as to drive the light-emitting element100bto emit light.

Exemplarily, the light-emitting element100bis an organic light-emitting diode, and the light-emitting element100bemits red light, green light, blue light, white light, or the like under the drive of the corresponding pixel circuit100a. For example, one pixel includes, but is not limited to, a pixel unit emitting red light, a pixel unit emitting green light, and a pixel unit emitting blue light. The number of the pixel units included in one pixel and the light-emitting color of each pixel unit are set based on needs. The turn-on or turn-off, the luminance and light-emitting duration of the light-emitting element is controlled under the action of the drive transistor T1, the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS, and the like.

As shown inFIG.12, the gate T20of the data writing transistor T2is connected to the gate line GT, the first electrode T21of the data writing transistor T2is connected to the data line DT, and the second electrode T22of the data writing transistor T2is connected to the first electrode T11of the drive transistor T1.

The gate T30of the threshold compensation transistor T3is connected to the gate line GT, the first electrode T31of the threshold compensation transistor T3is connected to the second electrode T12of the drive transistor T1, and the second electrode T32of the threshold compensation transistor T3is connected to the gate T10of the drive transistor T1.

The gate T40of the first light-emitting control transistor T4is connected to the light-emitting control signal line EML, the first electrode T41of the first light-emitting control transistor T4is connected to the first power line PL1, and the second electrode T42of the first light-emitting control transistor T4is connected to the first electrode T11of the drive transistor T1. The gate T50of the second light-emitting control transistor T5is connected to the light-emitting control signal line EML, the first electrode T51of the second light-emitting control transistor T5is connected to the second electrode T12of the drive transistor T1, and the second electrode T52of the second light-emitting control transistor T5is connected to the first electrode E1of the light-emitting element100b.

The first reset transistor T6is connected to the gate T10of the drive transistor T1, and is configured to reset the gate T10of the drive transistor T1. The second reset transistor T7is connected to the first electrode E1of the light-emitting element100b, and is configured to reset the first electrode E1of the light-emitting element100b. For example, as shown inFIG.12, the first electrode T61of the first reset transistor T6is connected to the first initialization signal line INL1, the second electrode T62of the first reset transistor T6is connected to the gate T10of the drive transistor T1, and the gate T60of the first reset transistor T6is connected to the reset control signal line RST.

The gate T70of the second reset transistor T7is connected to the reset control signal line RST, the first electrode T71of the second reset transistor T7is connected to the second initialization signal line INL2, and the second electrode T72of the second reset transistor T7is connected to the second electrode T52of the second light-emitting control transistor T5. That is, the second electrode T72of the second reset transistor T7is connected to the first electrode E1of the light-emitting element100b.

The first initialization signal line INL1is connected to the gate of the drive transistor T1through the first reset transistor T6. The second initialization signal line INL2is connected to the first electrode E1of the light-emitting element100bthrough the second reset transistor T7. In the embodiments of the present disclosure, the first initialization signal line INL1and the second initialization signal line INL2are two signal lines, which are insulated from each other to input signals respectively. In other embodiments, the first initialization signal line INL1and the second initialization signal line INL2are connected with each other so as to input the same initialization signal.

As shown inFIG.12, the first electrode Ca of the storage capacitor Cst is connected to the gate T10of the drive transistor T1, and the second electrode Cb of the storage capacitor Cst is connected to the first power line PL1.

A node N1is shown inFIG.12. Capacitance is formed between the node N1and the conductive line L1, and the shield electrode SE separates the node N1from the conductive line L1to achieve a shielding effect.

As shown inFIG.13, the pixel circuit further includes a first gate signal line SL1and a second gate signal line SL2.

The first electrode T11of the drive transistor T1is connected to the first power line PL1, the gate T10of the drive transistor T1is connected to the first gate signal line SL1, and the first gate signal line SL1is connected to the second gate signal line SL2. The second gate signal line SL2is connected to the second electrode T62of the first reset transistor T6, the first electrode T61of the first reset transistor T6is connected to the first initialization signal line INL1, and the gate T60of the first reset transistor T6is connected to the reset control signal line RST. The first electrode Ca of the storage capacitor Cst is connected to the gate T10of the drive transistor T1, and the second electrode Cb of the storage capacitor Cst is connected to the first power line PL1.

In the embodiments of the present disclosure, in the direction intersecting the extension direction of the constant voltage line L0, for example, in the second direction X, the second electrodes Cb of the storage capacitors Cst of the adjacent pixel circuits100aare connected with each other, and the orthographic projection of the second connecting portion SE2between the connected shield electrodes SE on the base substrate BS is at least partially overlapped with the orthographic projection of the connecting portion Cb1between the connected second electrodes Cb on the base substrate BS.

The connecting portion Cb1between the connected second electrodes Cb is blocked by the second connecting portion SE2, which can achieve a certain shielding effect, thereby weakening the coupling between the connecting portion Cb1between the connected second electrodes Cb and other structure in the display panel.

In some other embodiments, in the direction intersecting the extension direction of the constant voltage line L0, for example, in the second direction X, the second electrodes Cb of the storage capacitors Cst of the adjacent pixel circuits100aare spaced apart from each other, which is beneficial to the RC type load of the first power line PL1.

In the embodiments of the present disclosure, one end of the first gate signal line SL1is connected to the gate T10of the drive transistor T1through a via hole H1, and the other end of the first gate signal line SL1is connected to the second electrode T62of the first reset transistor T6through a via hole H2. The first gate signal line SL1is also referred to as a third connecting bridge CE1.

The pixel circuit further includes a first connecting bridge CE2, a second connecting bridge CE3, and the third connecting bridge CE1. One end of the first connecting bridge CE2is connected to the first initialization signal line INL1through a via hole H4, and the other end of the first connecting bridge CE2is connected to the first electrode T61of the first reset transistor T6through a via hole H5.

One end of the second connecting bridge CE3is connected to the second initialization signal line INL2through a via hole H6, and the other end of the second connecting bridge CE3is connected to the first electrode T71of the second reset transistor T7through a via hole H7.

The first power line PL1is connected to the first electrode T41of the first light-emitting control transistor T4through a via hole H8, and the first power line PL1is connected to the second electrode Cb of the storage capacitor Cst through a via hole H9.

The data line DT is connected to the first electrode T21of the data writing transistor T2through a via hole H0.

The shield electrode SE and the constant voltage line L0are provided in order to stabilize the potential on the first gate signal line SL1and the potential on the second gate signal line SL2, i.e., the potential of the first node N1. The constant voltage line L0is configured to provide a constant voltage to the pixel circuit. The shield electrode SE is connected to the constant voltage line L0, to stabilize the potential on the shield electrode SE, thereby achieving a shielding effect. The orthographic projection of the first gate signal line SL1on the base substrate BS is within the orthographic projection of the shield electrode SE on the base substrate BS.

In order that the shield electrode SE can achieve a better shielding effect so as to increase the shielding strength, the orthographic projection of at least one or all of the gate T10of the drive transistor T1, the first gate signal line SL1, the second gate signal line SL2, the second electrode T62of the first reset transistor T6, and the connecting portion between the second electrode Cb of the storage capacitor Cst and the first power line PL1on the base substrate BS is completely within the orthographic projection of the shield electrode SE on the base substrate BS.

To further mitigate the display defects and to improve the display effect, the distance between the boundary of the orthographic projection of each of the gate T10of the drive transistor T1, the first gate signal line SL1, the second gate signal line SL2, the second electrode T62of the first reset transistor T6, and the connecting portion between the second electrode Cb of the storage capacitor Cst and the first power line PL1on the base substrate BS and the boundary of the orthographic projection of the shield electrode SE on the base substrate BS is no less than 1.75 μm.

For example, the distance between the boundary of the orthographic projection of the first gate signal line SL1on the base substrate BS and the boundary of the orthographic projection of the shield electrode SE on the base substrate BS is not less than 1.75 μm. Exemplarily, the distance between the boundary of the orthographic projection of the first gate signal line SL1on the base substrate BS and the boundary of the orthographic projection of the shield electrode SE on the base substrate BS is 2.33 μm.

For example, the orthographic projection of the second gate signal line SL2on the base substrate BS is also within the orthographic projection of the shield electrode SE on the base substrate BS, and the distance between the boundary of the orthographic projection of the second gate signal line SL2on the base substrate BS and the boundary of the orthographic projection of the shield electrode SE on the base substrate BS is not less than 1.75 μm.

In some embodiments, the first gate signal line SL1and the second gate signal line SL2are made from different materials. For example, the material of the first gate signal line SL1includes metal, and the material of the second gate signal line SL2includes a semiconductor material, which are conducted to be a conductive material.

In some embodiments, the constant voltage line L0includes the first power line PL1or the first initialization signal line INL1. For example, in the embodiments of the present disclosure, the first power line PL1is used as the constant voltage line L0to save wiring. In other embodiments, the first initialization signal line INL1is used as the constant voltage line to save wiring. The constant voltage line L0is not limited to include the first power line PL1and the first initialization signal line INL1, and all the signal lines providing a constant voltage in the pixel circuit can be taken as the constant voltage line L0. Certainly, in some other embodiments, a signal line providing a constant voltage also is added as the constant voltage line L0.

As shown inFIG.13, the pixel circuit100afurther includes a block BK. In the embodiments of the present disclosure, the threshold compensation transistor T3is a dual-gate thin film transistor, and the threshold compensation transistor T3includes a first channel CN1and a second channel CN2. The first electrode T31of the threshold compensation transistor T3is connected to the second electrode T12of the drive transistor T1, the second electrode T32of the threshold compensation transistor T3is connected to the second gate signal line SL2, and the gate T30of the threshold compensation transistor T3is connected to the gate line GT. The first channel CN1and the second channel CN2are connected by a conductive connecting portion CP. The block BK is connected to the first power line PL1, and the orthographic projection of the block BK on the base substrate BS is at least partially overlapped with the orthographic projection of the conductive connecting portion CP on the base substrate BS.

The conductive connecting portion CP is blocked by the block BK. In the embodiments of the present disclosure, the block BK of the pixel unit in an adjacent column is configured to block the conductive connecting portion CP of the threshold compensation transistor T3of the pixel unit in the current column.

As shown inFIG.13, the block BK is connected to the first power line PL1through a second via hole Hk. The orthographic projection of the second via hole Hk on the base substrate BS is at least partially within the orthographic projection of the shield electrode SE on the base substrate BS.

In the embodiments of the present disclosure, the orthographic projection of the second via hole Hk on the base substrate BS is completely within the orthographic projection of the shield electrode SE on the base substrate BS.

In some embodiments, the orthographic projection of the block BK on the base substrate BS is partially overlapped with the orthographic projection of the second gate signal line SL2on the base substrate BS, such that the block BK can also achieve a certain a shielding effect for the second gate signal line SL2. Thus, the shield electrode SE and the block BK form a double shielding effect for the second gate signal line SL2, which helps stabilize the potential of the second gate signal line SL2.

FIG.14is a sectional view along I-I ofFIG.13. As shown inFIG.14, a buffer layer BL is disposed on the base substrate BS, an isolation layer BR is disposed on the buffer layer BL, an active layer LY0is disposed on the isolation layer BR, a first insulating layer ISL1is disposed on the active layer LY0, a first conductive layer LY1is disposed on the first insulating layer ISL1, a second insulating layer ISL2is disposed on the first conductive layer LY1, a second conductive layer LY2is disposed on the second insulating layer ISL2, a third insulating layer ISL3is disposed on the second conductive layer LY2, and a third conductive layer LY3is disposed on the third insulating layer ISL3.

The aforementioned connecting element CE0includes a connecting electrode CE01and a connecting electrode CE02. The third conductive layer LY3includes the connecting electrode CE01. The connecting electrode CE01is connected to the second electrode T52of the second light-emitting control transistor T5through a via hole H3penetrating through the first insulating layer ISL1, the second insulating layer ISL2and the third insulating layer ISL3. A fourth insulating layer ISL4and a fifth insulating layer ISL5are disposed on the third conductive layer LY3, and a fourth conductive layer LY4is disposed on the fourth insulating layer ISL4and the fifth insulating layer ISL5. The fourth conductive layer LY4includes the connecting electrode CE02, and the connecting electrode CE02is connected to the connecting electrode CE01through a via hole H22penetrating through the fourth insulating layer ISL4and the fifth insulating layer ISL5. A sixth insulating layer ISL6is disposed on the fourth conductive layer LY4.

FIG.13shows the first pixel circuit. The first light-emitting element30is connected to the connecting electrode CE02through a via hole H31penetrating through the sixth insulating layer ISL6. The light-emitting element100bincludes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL between the first electrode E1and the second electrode E2.

For the second pixel circuit, in the section at the same position as that inFIG.13, the conductive line L1is connected to the connecting electrode CE02through the via hole H31.

The channel of each transistor and the first electrode and the second electrode on two sides of the channel are disposed in the active layer LY0. The reset control signal line RST, the gate line GT, the gate T10of the drive transistor (the first electrode Ca of the storage capacitor Cst), and the light-emitting control signal line EML are disposed in the first conductive layer LY1. The first initialization signal line INL1, the second electrode Cb of the storage capacitor Cst, and the second initialization signal line INL2are disposed in the second conductive layer LY2. The data line DT, the first power line PL1, the first gate signal line SL1, the first connecting bridge CE2, the second connecting bridge CE3, and the connecting electrode CE01are disposed in the third conductive layer LY3. The shield electrode SE is disposed in the fourth conductive layer LY4.

During the process of manufacturing the display panel, a self-aligned process is adopted to perform a conducting process on a semiconductor pattern layer by using the first conductive layer LY1as a mask. The semiconductor pattern layer is formed by patterning a semiconductor thin film. For example, the semiconductor pattern layer is heavily doped through an ion implantation process, such that the portion, not covered by the first conductive layer LY1, of the semiconductor pattern layer is conducted to form a source region (e.g., the first electrode T11) and a drain region (e.g., the second electrode T12) of the drive transistor T1, a source region (e.g., the first electrode T21) and a drain region (e.g., the second electrode T22) of the data writing transistor T2, a source region (e.g., the first electrode T31) and a drain region (e.g., the second electrode T32) of the threshold compensation transistor T3, a source region (e.g., the first electrode T41) and a drain region (e.g., the second electrode T42) of the first light-emitting control transistor T4, a source region (e.g., the first electrode T51) and a drain region (e.g., the second electrode T52) of the second light-emitting control transistor T5, a source region (e.g., the first electrode T61) and a drain region (e.g. the second electrode T62) of the first reset transistor T6, and a source region (e.g., the first electrode T71) and the drain region (e.g., the second electrode T72) of the second reset transistor T7.

The portion, covered by the first conductive layer LY1, of the semiconductor pattern layer retains the semiconductor properties, and forms a channel region of the drive transistor T1, a channel region of the data writing transistor T2, a channel region of the threshold compensation transistor T3, a channel region of the first light-emitting control transistor T4, a channel region of the second light-emitting control transistor T5, a channel region of the first reset transistor T6, and a channel region of the second reset transistor T7.

For example, as shown inFIG.13, the second electrode T72of the second reset transistor T7and the second electrode T52of the second light-emitting control transistor T5are integrally formed; the first electrode T51of the second light-emitting control transistor T5, the second electrode T12of the drive transistor T1, and the first electrode T31of the threshold compensation transistor T3are integrally formed; the first electrode T11of the drive transistor T1, the second electrode T22of the data writing transistor T2, and the second electrode T42of the first light-emitting control transistor T4are integrally formed; and the second electrode T32of the threshold compensation transistor T3and the second electrode T62of the first reset transistor T6are integrally formed. In some embodiments, as shown inFIG.13, the first electrode T71of the second reset transistor T7and the first electrode T61of the first reset transistor T6are integrally formed.

In some embodiments, the channel regions of the transistors are made from monocrystalline silicon, polycrystalline silicon (e.g., low temperature poly-silicon), or a metal oxide semiconductor material (e.g., IGZO, AZO, etc.). In an example, the transistors are P-type low temperature poly-silicon (LTPS) thin film transistors. In another example, the threshold compensation transistor T3and the first reset transistor T6which are directly connected to the gate of the drive transistor T1are metal oxide semiconductor thin film transistors, that is, the channels of the transistors are made from a metal oxide semiconductor material (e.g., IGZO, AZO, etc.). The metal oxide semiconductor thin film transistor has a lower leakage current, which helps reduce the leakage current of the gate of the drive transistor T1.

In some embodiments, the transistors include thin film transistors in a plurality of structures, for example, a top-gate structure, a bottom-gate structure, or a dual-gate structure. In an example, the threshold compensation transistor T3and the first reset transistor T6which are directly connected to the gate of the drive transistor T1are dual-gate thin film transistors, which helps reduce the leakage current of the gate of the drive transistor T1.

As shown inFIG.14, the display panel further includes a pixel defining layer PDL and a photo spacer PS. The pixel defining layer PDL is provided with an opening OPN for defining the light-emitting area (light-exiting area, effective light-emitting area) of the pixel unit. The photo spacer PS is configured to support the fine metal mask when the light-emitting functional layer FL is formed.

The opening OPN is the light-exiting region of the pixel unit. The light-emitting functional layer FL is disposed on the first electrode E1of the light-emitting element100b, and the second electrode E2of the light-emitting element100bis disposed on the light-emitting functional layer FL. For example, the first electrode E1is the anode of the light-emitting element100b, and the second electrode E2is the cathode of the light-emitting element100b, which is not limited thereto.

An encapsulation layer CPS is disposed on the light-emitting element100b. The encapsulation layer CPS includes a first encapsulation layer CPS1, a second encapsulation layer CPS2, and a third encapsulation layer CPS3. Exemplarily, the first encapsulation layer CPS1and the third encapsulation layer CPS3are inorganic material layers, and the second encapsulation layer CPS2is an organic material layer.

For example, in the embodiments of the present disclosure, each pixel circuit100ais provided with any one of the aforementioned shield electrodes SE. That is, both the first pixel circuit10of the first pixel unit101and the second pixel circuit20of the second pixel unit102are provided with any one of the aforementioned shield electrodes SE.

For example, the shield electrode SE includes an Al layer, a Mo layer, or an Al layer and a Ti layer that are alternately laminated. That is, the shield electrode SE is a single-layered metal layer structure, or is multi-layered metal layer structures that are alternately laminated.

For example, the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, and the fourth conductive layer LY4are all made from a metal material. For example, the first conductive layer LY1and the second conductive layer LY2are made from a metal material, including but being not limited to, nickel, aluminum, and the like. For example, the third conductive layer LY3and the fourth conductive layer LY4are made from a material, including but being not limited to, titanium, aluminum, and the like. For example, the third conductive layer LY3and the fourth conductive layer LY4are both structures of three sub-layers of Ti/Al/Ti, which is not limited thereto. For example, the base substrate is a glass substrate or a polyimide substrate, which is not limited thereto, and the base substrate is selected based on needs. For example, the buffer layer BL, the isolation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, the fourth insulating layer ISL4, the fifth insulating layer ISL5, and the sixth insulating layer ISL6are all made from an insulating material. The materials of the first electrode E1and the second electrode E2of the light-emitting element are selected based on needs. In some embodiments, the first electrode E1is made from, but not limited to, at least one of a transparent conductive metal oxide and argentum. For example, the transparent conductive metal oxide includes, but is not limited to, indium tin oxide (ITO). For example, the first electrode E1adopts a laminated structure of three sub-layers of ITO/Ag/ITO. In some embodiments, the second electrode E2is made from a metal with a low power function, including, but being not limited to, at least one of magnesium and argentum.

The embodiments of the present disclosure further provide a method for manufacturing a display panel. Referring toFIG.2toFIG.14, the method is applicable for manufacturing the display panel provided in at least one of the embodiments of the present disclosure. The method is as follows.(1) A buffer layer BL and an isolation layer BR are formed on a base substrate BS.(2) A semiconductor thin film is formed on the isolation layer BR.(3) The semiconductor thin film is patterned to form a semiconductor pattern layer.(4) A first insulating layer ISL1is formed on the semiconductor pattern layer.(5) A first conductive thin film is formed on the first insulating layer ISL1, and the first conductive thin film is patterned to form a first conductive layer LY1.(6) The semiconductor pattern layer is doped by using the first conductive layer LY1as a mask to form an active layer LY0.(7) A second insulating layer ISL2is formed on the first conductive layer LY1.(8) A second conductive thin film is formed on the second insulating layer ISL2, and the second conductive thin film is patterned to form a second conductive layer LY2.(9) A third insulating layer ISL3is formed on the second conductive layer LY2.(10) At least one of the first insulating layer ISL1, the second insulating layer ISL2, and the third insulating layer ISL3is patterned to form a via hole.(11) A third conductive thin film is formed and the third conductive thin film is patterned to form a third conductive layer LY3. The various components in the third conductive layer LY3are connected to the structures under the third conductive layer LY3through via holes.(12) A fourth insulating layer ISL4and a fifth insulating layer ISL5are formed, and the fourth insulating layer ISL4and the fifth insulating layer ISL5are patterned to form via holes.(13) A fourth conductive thin film is formed and the fourth conductive thin film is patterned to form a fourth conductive layer LY4.(14) A sixth insulating layer ISL6and a transparent conductive layer are formed. The transparent conductive layer includes a conductive line L1.(15) A first electrode E1of a light-emitting element is formed.(16) A pixel defining layer PDL and a photo spacer PS are formed.(17) A light-emitting functional layer FL is formed.(18) A second electrode E2of the light-emitting element is formed.(19) An encapsulation layer CPS is formed.

The embodiments of the present disclosure further provide a display device. The display device includes the display panel as shown in any one ofFIG.2toFIG.14.

As shown inFIG.15, the display device includes a display panel DS and a photosensitive sensor SS, i.e., a camera. The photosensitive sensor SS is disposed on the back side of the display panel DS and is opposite to the second display region R2. The display panel DS includes a front face and a back face which are opposite, and the front face is generally for display.

For example, the display device is a full screen display device installed with an under-screen camera. For example, the display device includes an OLED or a product including an OLED. For example, the display device includes a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop, a navigator including the display panel described above, or any product or component with a display function.

FIG.16is a working timing diagram of a pixel circuit. As shown inFIG.16, in the display period of one frame, the driving method of a pixel unit includes a first reset stage t1, a stage t2of data writing, threshold compensation and second resetting, and a light-emitting stage t3. The gate of the drive transistor T1is reset when the reset control signal RESET1is at a low potential, and the first electrode E1(e.g., anode) of the light-emitting element100bis reset when the scan signal SCAN is at a low potential. For example, as shown inFIG.16, when the scan signal SCAN is at a low potential, the data voltage VDATA is written in, and meanwhile the threshold voltage Vth of the drive transistor T1is acquired, and the data voltage VDATA containing data information on the data line is stored in the storage capacitor Cst. When an electronic signal of the light-emitting control signal line EML is at a low potential, the light-emitting element100bemits light, and the voltage of the first node N1is maintained (the light-emitting stability of the light-emitting element100b) due to the storage capacitor Cst. During the driving process of the pixel circuit10, in the light-emitting stage, the storage capacitor is configured to maintain the voltage signal, to form a voltage between the gate and the source of the drive transistor, thereby controlling the drive transistor to form a driving current to drive the light-emitting element100bto emit light.

As shown inFIG.16, in the reset stage t1, the light-emitting control signal EM is set as a turn-off voltage, the reset control signal RESET1is set as a turn-on voltage, the reset control signal RESET2is set as a turn-off voltage, and the scan signal SCAN is set as a turn-off voltage.

As shown inFIG.16, in stage t2of data writing, threshold compensation and second resetting, the light-emitting control signal EM is set as a turn-off voltage, the reset control signal RESET1is set as a turn-off voltage, the reset control signal RESET2is set as a turn-on voltage, and the scan signal SCAN is set as a turn-on voltage.

As shown inFIG.16, in light-emitting stage t3, the light-emitting control signal EM is set as a turn-on voltage, the reset control signal RESET1is set as a turn-off voltage, the reset control signal RESET2is set as a turn-off voltage, and the scan signal SCAN is set as a turn-off voltage.

As shown inFIG.16, the first voltage signal ELVDD and the second voltage signal ELVSS are both constant voltage signals. For example, the potential of the initialization signal Vinit is between the potential of the first voltage signal ELVDD and the potential of the second voltage signal ELVSS.

For example, in the embodiments of the present disclosure, the turn-on voltage refers to a voltage turning on the first electrode and the second electrode of the corresponding transistor, and the turn-off voltage refers to a voltage turning off the first electrode and the second electrode of the corresponding transistor. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V), and the turn-off voltage is a high voltage (e.g., 5V); when the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V), and the turn-off voltage is a low voltage (e.g., 0V). The driving waveforms shown inFIG.16are illustrated by taking the P-type transistor as an example in which the turn-on voltage is a low voltage (e.g., 0V) and the turn-off voltage is a high voltage (e.g., 5V), which is not limited thereto.

In the first reset stage t1, the light-emitting control signal EM is the turn-off voltage, the reset control signal RESET1is the turn-on voltage, the reset control signal RESET2is the turn-off voltage, and the scan signal SCAN is the turn-off voltage. At this time, the first reset transistor T6is turned on, while the second reset transistor T7, the data writing transistor T2, the threshold compensation transistor T3, the first light-emitting control transistor T4and the second light-emitting control transistor T5are turned off. The first reset transistor T6transmits the first initialization signal Vinit1(initialization voltage Vinit) to the gate of the drive transistor T1and is stored in the storage capacitor Cst, to reset the drive transistor T1and eliminate data stored at the previous time of (previous frame) light-emitting.

In the stage t2of data writing, threshold compensation and second resetting, the light-emitting control signal EM is the turn-off voltage, the reset control signal RESET1is the turn-off voltage, the reset control signal RESET2is the turn-on voltage, and the scan signal SCAN is the turn-on voltage. At this time, the data writing transistor T2and the threshold compensation transistor T3are turned on, and the second reset transistor T7is turned on. The second reset transistor T7transmits the second initialization signal Vinit2(initialization voltage Vinit) to the first electrode E1of the light-emitting element100b, to reset the light-emitting element100b. The first light-emitting control transistor T4, the second light-emitting control transistor T5, and the first reset transistor T6are turned off. At this time, the data writing transistor T2transmits the data voltage VDATA to the first electrode of the drive transistor T1, that is, the data writing transistor T2receives the scan signal SCAN and the data voltage VDATA and writes the data voltage VDATA to the first electrode T11of the drive transistor T1based on the scan signal SCAN. The threshold compensation transistor T3is turned on to conduct the drive transistor T1into a diode structure, thereby charging the gate T10of the drive transistor T1. After charging is completed, the gate voltage of the drive transistor T1is VDATA+Vth, wherein VDATA is the data voltage and Vth is the threshold voltage of the drive transistor T1. That is, the threshold compensation transistor T3receives the scan signal SCAN and performs threshold voltage compensation on the gate voltage of the drive transistor T1based on the scan signal SCAN. In this stage, the voltage difference between two ends of the storage capacitor Cst is ELVDD-VDATA-Vth.

In the light-emitting stage t3, the light-emitting control signal EM is the turn-on voltage, the reset control signal RESET1is the turn-off voltage, the reset control signal RESET2is the turn-off voltage, and the scan signal SCAN is the turn-off voltage. The first light-emitting control transistor T4and the second light-emitting control transistor T5are turned on, while the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6, and the second reset transistor T7are turned off. The first voltage signal ELVDD is transmitted through the first light-emitting control transistor T4to the first electrode T10of the drive transistor T1. The gate voltage of the drive transistor T1maintains at VDATA+Vth, the light-emitting current I flows into the light-emitting element100bthrough the first light-emitting control transistor T4, the drive transistor T1, and the second light-emitting control transistor T5, and the light-emitting element100bemits light. That is, the first light-emitting control transistor T4and the second light-emitting control transistor T5receive the light-emitting control signal EM and control the light-emitting element100bto emit light based on the light-emitting control signal EM.

For example, the proportion of the duration of the light-emitting stage t3to the display period of one frame is adjustable. The luminance is controlled by adjusting the proportion of the duration of the light-emitting stage t3to the display period of one frame. For example, the proportion of the duration of the light-emitting stage t3to the display period of one frame is adjusted by controlling the scan driving circuit or a driving circuit additionally provided in the display panel.

In the embodiments of the present disclosure, the structures in the same layer are formed of the same film layer through the same patterning process. For example, the structures in the same layer are disposed on the surface, away from the base substrate, of the same structure.

It should be noted that the thicknesses of the layers or regions are scaled up in the drawings used to describe the embodiments of the present disclosure in order to clearly show the structures, and the proportion between the various dimensions is merely illustrative and does not represent actual proportional relationship. It will be appreciated that when a structure such as a layer, film, region or substrate is referred to as being “on” or “under” another structure, it may be “directly on” or “directly under” the other structure or an intervening structure may exist.

In the embodiments of the present disclosure, the patterning or patterning process may include a photoetching process only, or may include a photoetching process and an etching process, or may include printing, ink jetting and other processes for forming a predetermined pattern. The photoetching process includes film forming, exposure, development, and the like for forming a pattern by using photoresist, a mask, an exposure machine, or the like. The corresponding patterning process may be selected according to the structure formed in the embodiments of the present disclosure.

The foregoing descriptions are merely optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, and improvements within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.