Method of establishing when to propagate the output of a multiplexer

A method for establishing when to propagate the output of a multiplexer using a timing analyzer. The method uses not only the enabling edges, but also the disabling edges, of control signals to the multiplexer.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates generally to integrated circuits more particularly, 
to a method of accurately determining propagation delays through 
multiplexers used in such circuits. 
2. DESCRIPTION OF THE RELATED ART 
In high speed integrated circuit design, e.g., the design of 
microprocessors, performance verification of the circuit design is 
accomplished by using timing analyzers which simulate the operation of the 
product being designed. Such analyzers function, for example, to calculate 
the amount of time that it takes for a particular signal to be propagated 
from a first circuit location to a second circuit location. In performing 
that function, the analyzers calculate the propagation delays through the 
individual circuit devices in the path between the first and second 
circuit locations. 
One type of circuit device that is very commonly used in high speed 
integrated circuit design is a digital multiplexer composed of either 
passgates or tristate gates. A multiplexer has a plurality of sets of data 
input signals and a plurality of control signal inputs. The logic states 
of the control signal inputs determine which set of data input signals 
appear at the output of the device at any particular time. For example, 
the 2.times.1 multiplexer shown in FIG. 1 has two sets of data input 
signals, I1 and I2, and two control signal inputs, C1 and C2. The value of 
the output of the multiplexer is the value of input 11 when the control 
signals C1 and C2 have logic states of "1" and "0," respectively. In order 
for the value of the output of the multiplexer to assume the value of data 
input I2, the control signal C1 is switched from a logic "1" to a logic 
"0" and the control signal C2 is switched from a logic "0" to a logic "1," 
as shown in FIG. 2. 
In actual circuits, disabling control edge 200 of control input signal C1 
can occur much later in time than the enabling control edge 201 of control 
input signal C2, as shown in FIG. 2. In other words, both passgates 101 
and 102 in FIG. 1 are enabled for the period of time, t.sub.c, between the 
enabling edge 201 of control input signal C2 and the disabling edge 200 of 
control signal C1, which results in a large contention current flowing 
through passgates 100 and 101 during the time t.sub.c. Until control 
signal C1 actually turns off, control signal C2 cannot drive a proper 
value to the output of the multiplexer. Thus, the time at which the value 
of the output of the multiplexer is the value of input I2 has been "pushed 
out" from the leading edge of control signal C2. 
Heretofore, static timing analyzers have only used the enabling edge of 
control signals to determine when to propagate the output of a multiplexer 
and have ignored the potential interaction described above between the 
disabling edge of a control signal and the enabling edge of a control 
signal. Accordingly, critical timing paths and functional race conditions 
may have been missed. 
SUMMARY OF THE INVENTION 
In accordance with the present invention, a method is provided for 
accurately calculating propagation delay through a multiplexer using a 
static timing analyzer. This method measures delays through a multiplexer 
from both an enabling and a disabling edge of each control signal rather 
than just the enabling edge. This method also proposes an alternate method 
where the delay coming off an enabling edge of a control signal is delayed 
until the disabling edge of a control signal, if the disabling edge comes 
after the enabling edge.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS 
Illustrative embodiments of the invention are described below. In the 
interest of clarity, not all features of an actual implementation are 
described in this specification. It will of course be appreciated that in 
the development of any such actual embodiment, numerous 
implementation-specific decisions must be made to achieve the developers' 
specific goals, such as compliance with system-related and 
business-related constraints, which will vary from one implementation to 
another. Moreover, it will be appreciated that such a development effort 
might be complex and time-consuming, but would nevertheless be a routine 
undertaking for those of ordinary skill in the art having the benefit of 
this disclosure. 
With reference to FIGS. 1 and 2, a multiplexer 102 in an integrated circuit 
is composed of passgates or tristate gates 100 and 101. While multiplexer 
102 is depicted as a 2.times.1 multiplexer for ease of illustration, those 
skilled in the art will appreciate that the method of the present 
invention is applicable to any size multiplexer. 
In accordance with the present invention, in multiplexer 102 delays will be 
propagated from both the disabling edge 200 of control signal C1 and the 
enabling edge 201 of C2. In a static timing tool, timing analysis is done 
by calculating delays through one circuit path at a time. Because of this 
limitation, the tool cannot do a simultaneous interaction analysis between 
C1-Out and C2-Out paths and hence does not understand the contention 
between control signal C1 and C2. Since a disabling control signal (like 
edge 200 of C1) does not generate a new logic value at the output, this 
edge has been ignored before, for timing analysis. Though the disabling 
edge does not generate a new logic value, it does, however, affect when an 
actual logic value can be driven to the output through an enabled path. 
This time domain dependency between edge 200 of C1 and 201 of C2 can be 
captured by propagating a delay from edge 200 of C1, since this edge 
indicates the end of contention. But since a disabling edge does not 
generate a new logic value at the output, a pseudo delay value is 
propagated from disabling edge 200 of C1. This mechanism of propagating a 
pseudo delay from a disabling edge can capture the contention situation in 
the multiplexer and can hence do a proper timing delay analysis through 
it. Another proposed way to capture this contention using static timing 
analysis method is to postpone the propagation delay coming off edge 201 
of C2 until edge 200 of C1. 
In accordance with the present invention, a timing analyzer is provided 
having circuitry to implement the propagation of the output of a 
multiplexer as described herein. 
The particular embodiments disclosed above are illustrative only, as the 
invention may be modified and practiced in different but equivalent 
manners apparent to those skilled in the art having the benefit of the 
teachings herein. Furthermore, no limitations are intended to the details 
of construction or design herein shown, other than as described in the 
claims below. It is therefore evident that the particular embodiments 
disclosed above may be altered or modified and all such variations are 
considered within the scope and spirit of the invention. Accordingly, the 
protection sought herein is as set forth in the claims below.