Semiconductor devices including a stress pattern

Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2018-0108380 filed on Sep. 11, 2018 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to semiconductor devices. To increase the integration of an integrated circuit device, a multi-gate transistor including a fin-shaped or nanowire-shaped silicon body on a substrate and a gate on the silicon body has been proposed. Because a multi-gate transistor can utilize a three-dimensional channel, it can be scaled.

Further, current control capability of the multi-gate transistor can be improved without increasing a gate length thereof. A short channel effect (SCE) in which the electrical potential of the channel region is affected by the drain voltage can be effectively reduced and/or suppressed in the multi-gate transistor. A layer containing a stress material may be formed in a silicon body of fin type to increase a carrier mobility in a channel region of a semiconductor device.

SUMMARY

According to example embodiments of the inventive concepts, a semiconductor device may include a substrate. The semiconductor device may include a fin structure including a stress pattern and a semiconductor pattern that are sequentially stacked on the substrate. The semiconductor device may include a field insulation layer on a portion of the fin structure. The semiconductor device may include a gate electrode on the fin structure. The gate electrode may intersect the fin structure and extend in a first direction. Moreover, the stress pattern may include a first oxide pattern and a second oxide pattern that are spaced apart from each other in a second direction that is different from the first direction.

According to example embodiments of the inventive concepts, a semiconductor device may include a substrate. The semiconductor device may include a fin structure including a stress structure and a first semiconductor region that are sequentially stacked on the substrate. The semiconductor device may include a field insulation layer on a portion of the fin structure. The semiconductor device may include a gate electrode on the fin structure and the field insulation layer. The gate electrode may intersect the fin structure. The stress structure may include a first oxide region including germanium. The stress structure may include a second oxide region that is spaced apart from the first oxide region. The second oxide region may include germanium. Moreover, the stress structure may include a second semiconductor region between the first oxide region and the second oxide region. The second semiconductor region may be free of germanium.

According to example embodiments of the inventive concepts, a semiconductor device may include a substrate. The semiconductor device may include a fin structure on the substrate. The semiconductor device may include a field insulation layer on a sidewall portion of the fin structure. The semiconductor device may include a gate electrode on the fin structure, and the gate electrode may intersect the fin structure. Moreover, the fin structure may include a first semiconductor layer, a stress region, and a second semiconductor layer that are sequentially stacked on the substrate. The stress region may include an oxide including germanium. A first angle between an upper surface of the first semiconductor layer and a first line parallel to an upper surface of the substrate may be different from a second angle between a lower surface of the second semiconductor layer and a second line parallel to the upper surface of the substrate.

DETAILED DESCRIPTION

Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. However, the inventive concepts may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein.

In the drawings of the semiconductor device according to example embodiments of the inventive concepts, a fin transistor (FinFET) including a channel region of fin type is illustrated, but the inventive concepts are not limited thereto. The semiconductor device according to example embodiments of the inventive concepts may include a tunneling transistor, a three dimensional transistor, a transistor including a nanowire-shaped channel, or a transistor including nanosheet-shaped channel region. The semiconductor device according to embodiments of the inventive concepts may include a bipolar junction transistor, a lateral double diffused transistor (LDMOS), or the like.

FIG. 1is a layout diagram illustrating a semiconductor device according to example embodiments.FIG. 2is a cross-sectional view taken along line A-A ofFIG. 1, illustrating a semiconductor device according to example embodiments.FIG. 3is a cross-sectional view taken along line B-B ofFIG. 1, illustrating a semiconductor device according to example embodiments.FIG. 4is an enlarged view of portion S ofFIG. 3.FIG. 5is a graph illustrating a change in a germanium concentration along a first scan line P1-P2ofFIG. 4.

Referring toFIGS. 1 to 5, a semiconductor device according to example embodiments may include a substrate100, a first fin structure FS, a field insulation layer105, a first gate structure GS1, a second gate structure GS2, source/drain regions150, and an interlayer insulation layer160.

The substrate100may be a bulk silicon substrate, or a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate100may include for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, but is not limited thereto.

The substrate100may include a first fin structure FS. The first fin structure FS may protrude from the substrate100. The first fin structure FS may extend in a first direction X parallel to an upper surface of the substrate100.

The first fin structure FS may include a first semiconductor pattern110, a stress pattern120, and a third semiconductor pattern130sequentially stacked on the substrate100.

The first semiconductor pattern110may protrude from the substrate100and may extend in a first direction X. The first semiconductor pattern110may be a portion of the substrate100or may include an epitaxial layer grown from the substrate100.

The first semiconductor pattern110may include a first semiconductor material. For example, the first semiconductor material may include silicon (Si) or germanium (Ge). The fin structure FS may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. Hereinafter, it will be described that the first semiconductor pattern110includes silicon.

The stress pattern120may be formed on the first semiconductor pattern110. The stress pattern120may extend in the first direction X.

The stress pattern120may include an oxide of a second semiconductor material. The second semiconductor material may be a material having an oxidation rate faster than that of the first semiconductor material. For example, when the first semiconductor material is silicon, the second semiconductor material may be germanium (Ge). The stress pattern120may include at least one of silicon-germanium oxide, silicon-germanium-carbide oxide, and germanium oxide.

In some embodiments, the stress pattern120may include a plurality of oxide patterns. For example, as shown inFIGS. 2 to 4, the stress pattern120may include a first oxide pattern122and a second oxide pattern124. The first oxide pattern122and the second oxide pattern124may be spaced apart from each other with a second semiconductor pattern126therebetween. The stress pattern120may include the second semiconductor pattern126. In some embodiments, the stress pattern120may include three or more oxide patterns spaced apart from each other.

Moreover, though the term “pattern” is used in examples herein to describe elements110,122,124,126, and130, these elements may comprise respective layers/regions and are not limited to patterns. Accordingly, elements110,122,124,126, and130may be referred to herein as a first semiconductor layer/region, a first oxide layer/region, a second oxide layer/region, a second semiconductor layer/region, and a third semiconductor layer/region, respectively. Similarly, element120may be a structure/region that is not limited to a pattern, and thus may be referred to herein as a “stress structure” or “stress region.” Additionally or alternatively, element130may be referred to herein using the term “first” or the term “second,” and element110may be referred to herein using the term “second” or the term “third,” as these terms do not necessarily imply a particular sequence in a fin structure FS.

In some embodiments, the first oxide pattern122and the second oxide pattern124may be spaced apart from each other in a third direction Z vertical (e.g., perpendicular) to the upper surface of the substrate100. The first oxide pattern122, the second semiconductor pattern126, and the second oxide pattern124may be vertically stacked on the substrate100. The first oxide pattern122, the second semiconductor pattern126, and the second oxide pattern124may extend in the first direction X.

The first oxide pattern122and the second oxide pattern124may include an oxide of the second semiconductor material. The first oxide pattern122and the second oxide pattern124may include at least one of silicon-germanium oxide, silicon-germanium-carbide oxide, and germanium oxide.

In some embodiments, the second semiconductor pattern126may be free of (i.e., may not include) germanium (Ge). For example, the second semiconductor pattern126may include the first semiconductor material, for example, silicon (Si).

The third semiconductor pattern130may be formed on the stress pattern120. The third semiconductor pattern130may extend in the first direction X. In some embodiments, the third semiconductor pattern130may be a channel region of an NMOS transistor.

The third semiconductor pattern130may directly contact one of the first oxide pattern122and the second oxide pattern124. For example, the third semiconductor pattern130may directly contact an upper surface of the second oxide pattern124.

The third semiconductor pattern130may include a third semiconductor material. The third semiconductor material may be a material having an oxidation rate slower than that of the second semiconductor material. In some embodiments, the third semiconductor material may be the same as the first semiconductor material. For example, the third semiconductor pattern130may include silicon (Si).

In some embodiments, a semiconductor layer including silicon germanium (SiGe), silicon germanium carbide (SiGeC), or germanium (Ge) may be oxidized by an oxidation process, thus forming the stress pattern120including the first oxide pattern122and the second oxide pattern124. However, a semiconductor layer including silicon (Si) having an oxidation rate slower than that of silicon-germanium (SiGe), silicon-germanium-carbide (SiGeC), or germanium (Ge) may not be oxidized by the oxidation process, thus forming the first semiconductor pattern110and the third semiconductor pattern130.

In some embodiments, the stress pattern120may apply a tensile stress to the third semiconductor pattern130. This may be caused by, for example, characteristics of the oxidation process for forming the stress pattern120. For example, the semiconductor layer including silicon-germanium (SiGe), silicon-germanium-carbide (SiGeC), or germanium (Ge) may be expanded during the oxidation process, such that the stress pattern120may be formed. Thus, the tensile stress may be applied to the third semiconductor pattern130, such that a carrier mobility in the third semiconductor pattern130may be increased.

In some embodiments, referring toFIG. 4, a width W4of the first oxide pattern122and a width W5of the second oxide pattern124may be greater than a width W1of the first semiconductor pattern110, a width W2of the second semiconductor pattern126, or a width W3of the third semiconductor pattern130. Herein, the term “width” means a width in a second direction Y parallel to the upper surface of the substrate100and crossing the first direction X. In some embodiments, the semiconductor layer including silicon-germanium (SiGe), silicon-germanium-carbide (SiGeC), or germanium (Ge) may be expanded during the oxidation process, thus forming the first oxide pattern122having the width W4and the second oxide pattern124having the width W5.

In some embodiments, the width W4of the first oxide pattern122may be the same as the width W5of the second oxide pattern124, but is not limited thereto. In some embodiments, the width W4of the first oxide pattern122may be greater than the width W5of the second oxide pattern124.

The width W1of the first semiconductor pattern110, the width W2of the second semiconductor pattern126, and the width W3of the third semiconductor pattern130may be the same, but are not limited thereto. In some embodiments, the width W1of the first semiconductor pattern110may be greater than the width W2of the second semiconductor pattern126, and the width W2of the second semiconductor pattern126may be greater than the width W3of the third semiconductor pattern130.

The field insulation layer105may be formed on the substrate100. The field insulation layer105may be on (e.g., may cover) portions of sidewalls of the first fin structure FS. For example, the first fin structure FS may be defined by the field insulation layer105.

In some embodiments, a height H1of an upper surface of the field insulation layer105may be higher than a height of an uppermost surface of the stress pattern120with respect to the upper surface of the substrate100. For example, the field insulation layer105may completely cover sidewalls of the stress pattern120. A lower portion of the third semiconductor pattern130may be buried in the field insulation layer105.

The field insulation layer105may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but is not limited thereto.

In some embodiments, a germanium concentration in the first oxide pattern122and the second oxide pattern124may be greater than a germanium concentration in the field insulation layer105. In some embodiments, referring toFIG. 5, a scan line P1-P2crossing the first oxide pattern122along the second direction Y may be defined. The germanium concentration may rapidly increase from a boundary surface of the first oxide pattern122toward the inside of the first oxide pattern122along the scan line P1-P2.

InFIGS. 3 and 4, it is illustrated that a boundary between the first oxide pattern122and the field insulation layer105and a boundary between the second oxide pattern124and the field insulation layer105are visible, but the inventive concepts are not limited thereto. In some embodiments, since the field insulation layer105, the first oxide pattern122, and the second oxide pattern124include oxide, the boundary between the first oxide pattern122and the field insulation layer105and the boundary between the second oxide pattern124and the field insulation layer105may not appear visibly.

The first gate structure GS1and the second gate structure GS2may be formed on the first fin structure FS and the field insulation layer105. The first gate structure GS1and the second gate structure GS2may intersect the first fin structure FS. For example, the first gate structure GS1and the second gate structure GS2may be spaced apart from each other in the first direction X and may extend in the second direction Y.

The first gate structure GS1may include a first gate insulation layer142, a first gate electrode144, first gate spacers146, a first gate trench GT1defined by the first gate spacers146, and a first capping pattern148.

The second gate structure GS2may include a second gate insulation layer242, a second gate electrode244, second gate spacers246, a second gate trench GT2defined by the second gate spacers246, and a second capping pattern248.

The first gate insulation layer142may be interposed between the first fin structure FS and the first gate electrode144. The second gate insulation layer242may be interposed between the first fin structure FS and the second gate electrode244. In some embodiments, the first gate insulation layer142may extend along a sidewall and a bottom surface of the first gate trench GT1, and the second gate insulation layer242may extend along a sidewall and a bottom surface of the second trench GT2.

The first gate insulation layer142and the second gate insulation layer242may include a high-k dielectric layer including a high-k dielectric material having a grater dielectric constant than that of silicon oxide. The first gate insulation layer142and the second gate insulation layer242may include hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

The first gate electrode144may be formed on the first gate insulation layer142. The second gate electrode244may be formed on the second gate insulation layer242. The first gate electrode144may fill at least a portion of the first gate trench GT1. The second gate electrode244may fill at least a portion of the second gate trench GT2.

The first gate electrode144and the second gate electrode244may include, for example, titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), or a combination thereof. In some embodiments, the first gate electrode144and the second gate electrode244may include, for example, silicon or silicon germanium.

The first gate electrode144and the second gate electrode244may each be formed of a single layer. In some embodiments, the first gate electrode144and the second gate electrode244may each include a work function adjusting layer and a filling layer on the work function adjusting layer. The work function adjusting layer may include, for example, Ti, titanium nitride (TiN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), Ta, tantalum nitride (TaN), or a combination thereof, but is not limited thereto. The filling layer may include, for example, W, Al, Co, Cu, ruthenium (Ru), nickel (Ni), platinum (Pt), Ni—Pt, TiN, or a combination thereof.

The first gate spacers146may be formed on sidewalls of the first gate electrode144. The second gate spacers246may be formed on sidewalls of the second gate electrode244.

The first gate spacers146and the second gate spacers246may each include, for example, silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, or a combination thereof.

The first capping pattern148may be formed on the first gate electrode144. The second capping pattern248may be formed on the second gate electrode244.

The first capping pattern148and the second capping pattern248may each include, for example, silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, or a combination thereof.

In some embodiments, the first gate spacers146may be formed on the sidewalls of the first gate electrode144and sidewalls of the first capping pattern148, and the second gate spacers246may be formed on the sidewalls of the second gate electrode244and sidewalls of the second capping pattern248. For example, referring toFIG. 2, the first gate electrode144may fill a portion of the first gate trench GT1, and the first capping pattern148may fill a remaining portion of the first gate trench GT1. The second gate electrode244may fill a portion of the second gate trench GT2, and the second capping pattern248may fill a remaining portion of the second gate trench GT2.

In some embodiments, the first capping pattern148may be formed on an upper surface of the first gate electrode144and upper surfaces of the first gate spacers146. The second capping pattern248may be formed on an upper surface of the second gate electrode244and upper surfaces of the second gate spacers246.

In some embodiments, the first and second capping patterns148and248may be omitted.

In some embodiments, the first gate structure GS1and the second gate structure GS2may be formed by the same process.

The source/drain regions150may be formed in the first fin structure FS. The source/drain regions150may be formed in the third semiconductor pattern130at opposite sides of the first gate electrode144and at opposite sides of the second gate electrode244.

The source/drain regions150may each include an epitaxial layer formed on first fin structure FS. For example, the source/drain regions150may each be an epitaxial pattern filling a source/drain trench formed in the third semiconductor pattern130. In some embodiments, the source/drain regions150may each be an impurity region formed in the third semiconductor pattern130.

In some embodiments, the source/drain regions150may each be an elevated source/drain region having an upper surface protruding over/higher than the upper surface of the first fin structure FS.

In some embodiments, the source/drain regions150may each include an undercut formed below the first gate structure GS1and the second gate structure GS2. This may be caused by characteristics of an etch process of forming the source/drain trench. However, the inventive concepts are not limited thereto. For example, the source/drain regions150may not each include the undercut.

The interlayer insulation layer160may be formed on the field insulation layer105and the source/drain regions150. The interlayer insulation layer160may be on (e.g., may cover) the sidewalls of the first and second gate structures GS1and GS2.

In some embodiments, the interlayer insulation layer160may further include an etch stop layer extending along upper surfaces of the source/drain regions150.

FIGS. 6 to 9are cross-sectional views illustrating a semiconductor device according to example embodiments.FIGS. 6 to 9are cross-sectional views taken along line A-A ofFIG. 1. For convenience of explanation, elements duplicated with the examples described above will be described in brief or omitted.

Referring toFIG. 6, in a semiconductor device according to example embodiments, the first semiconductor pattern110, the second semiconductor pattern126, and the third semiconductor pattern130may have respectively sloped surfaces110US,126LS,126US, and130US.

For example, an upper surface of the first semiconductor pattern110may have a first surface110US having an acute angle with respect to the upper surface of the substrate100. A lower surface of the second semiconductor pattern126may have a second surface126LS having an acute angle with respect to the upper surface of the substrate100. An upper surface of the second semiconductor pattern126may have a third surface126US having an acute angle with respect to the upper surface of the substrate100. A lower surface of the third semiconductor pattern130may have a fourth surface130LS with respect to the upper surface of the substrate100. The first to fourth surfaces110US,126LS,126US, and130LS may each extend in the first direction X. This may be caused by, for example, characteristics of an oxidation process of forming the stress pattern120.

A height of the first surface110US of the first semiconductor pattern110may increase as a distance from each sidewall of the first semiconductor pattern110increases. A height of the second surface126LS of the second semiconductor pattern126may be reduced as a distance from each sidewall of the second semiconductor pattern126increases. Thus, as an example, the first oxide pattern122of dumbbell shape may be formed.

A height of the third surface126US of the second semiconductor pattern126may increase as a distance from each sidewall of the second semiconductor pattern126increases. A height of the fourth surface130LS of the third semiconductor pattern130may be reduced as a distance from each sidewall of the third semiconductor pattern130increases. Thus, as an example, the second oxide pattern124of dumbbell shape may be formed.

Referring toFIG. 7, in a semiconductor device according to example embodiments, the first fin structure FS may further include a first connection pattern112and a second connection pattern132.

The first connection pattern112may cross/extend through the first oxide pattern122to connect the first semiconductor pattern110and the second semiconductor pattern126. The second connection pattern132may cross/extend through the second oxide pattern124to connect the second semiconductor pattern126and the third semiconductor pattern130. The first connection pattern112and the second connection pattern132may extend in the first direction X.

The first connection pattern112and the second connection pattern132may include the second semiconductor material. For example, the first connection pattern112and the second connection pattern132may include at least one of silicon germanium (SiGe), silicon germanium carbide (SiGeC), and germanium (Ge).

In the oxidation process for forming the stress pattern120, a portion (e.g., a central portion) of a semiconductor layer including silicon germanium (SiGe), silicon germanium carbide (SiGeC), or germanium (Ge) may not be oxidized, thus forming the first connection pattern112and the second connection pattern132.

Referring toFIG. 8, in a semiconductor device according to example embodiments, a portion of the stress pattern120may directly contact the upper surface of the substrate100. For example, a lower surface of the first oxide pattern122of the stress pattern120may directly contact the upper surface of the substrate100.

In some embodiments, the first semiconductor pattern (see, e.g.,110ofFIG. 3) may be omitted. Thus, a lower surface of the stress pattern120may directly contact the upper surface of the substrate100. For example, a lower surface of the the first oxide pattern122of the stress pattern120may directly contact the upper surface of the substrate100.

In some embodiments, as a thickness of the stress pattern120is adjusted, the tensile stress applied to the third semiconductor pattern130by the stress pattern120may be adjusted. Herein, the term “thickness” means a thickness in the third direction Z.

Referring toFIG. 9, in a semiconductor device according to example embodiments, a height H3of an upper surface of the field insulation layer105may be lower than a height H4of an uppermost surface of the stress pattern120with respect to the upper surface of the substrate100.

The field insulation layer105may not vertically overlap (e.g., may expose) at least a portion of the stress pattern120. In addition, the third semiconductor pattern130may not contact the field insulation layer105.

The height H3of the upper surface of the field insulation layer105may be higher than a height of the upper surface of the second semiconductor pattern126with respect to the upper surface of the substrate100as shown inFIG. 9, but the inventive concepts are not limited thereto.

In some embodiments, the height H3of the upper surface of the field insulation layer105may be lower than a height of the upper surface of the second semiconductor pattern126with respect to the upper surface of the substrate100. In some embodiments, the height H3of the upper surface of the field insulation layer105may be lower than a height of an upper surface of the first semiconductor pattern110with respect to the upper surface of the substrate100.

FIGS. 10 and 11are cross-sectional views illustrating a semiconductor device according to example embodiments.FIG. 10is a cross-sectional view taken along line A-A ofFIG. 1.FIG. 11is a cross-sectional view taken along line B-B ofFIG. 1. For convenience of explanation, elements duplicated with the examples described above will be described in brief or omitted.

Referring toFIGS. 10 and 11, the first oxide pattern122and the second oxide pattern124may be spaced apart from each other in the first direction X.

The first direction X may be, for example, a longitudinal extension direction of the first fin structure FS. The first oxide pattern122, the second semiconductor pattern126, and the second oxide pattern124may be sequentially located (e.g., positioned/arranged) along the first direction X. The first oxide pattern122and the second oxide pattern124may each extend in the first direction X.

In some embodiments, the first oxide pattern122may be overlapped by the first gate electrode144, and the second oxide pattern124may be overlapped by the second gate electrode244. For example, the first oxide pattern122may cross the first gate electrode144, and the second oxide pattern124may cross the second gate electrode244. Thus, the first oxide pattern122may apply the tensile stress to the third semiconductor pattern130between the first oxide pattern122and the first gate electrode144. In addition, the second oxide pattern124may apply the tensile stress to the third semiconductor pattern130between the second oxide pattern124and the second gate electrode244.

In some embodiments, the second semiconductor pattern126may not be overlapped by the first gate electrode144and the second gate electrode244.

FIGS. 12 to 16are cross-sectional views illustrating a semiconductor device according to example embodiments.FIGS. 13 and 15are cross-sectional views taken along line C-C ofFIG. 12.FIG. 14is a graph illustrating a change in a germanium concentration along a second scan line P3-P4ofFIG. 13.FIG. 16is a graph illustrating a change in a germanium concentration along a second scan line P5-P6ofFIG. 15. For convenience of explanation, elements duplicated with the examples described above will be described in brief or omitted.

Referring toFIGS. 12 to 16, in a semiconductor device according to example embodiments, a first angle θ1formed between an extension line of an upper surface of the first semiconductor pattern110and a line parallel to the upper surface of the substrate100may be different from a second angle θ2formed between an extension line of a lower surface of the third semiconductor pattern130and a line parallel to the upper surface of the substrate100.

In some embodiments, as shown inFIG. 13, the first angle θ1formed between an extension line of the first surface110US of the first semiconductor pattern110and a line parallel to the upper surface of the substrate100may be greater than the second angle θ2formed between an extension line of the fourth surface130LS of the third semiconductor pattern130and a line parallel to the upper surface of the substrate100. The second angle θ2may be an acute angle, but is not limited thereto. For example, the fourth surface130LS of the third semiconductor pattern130may be parallel to the upper surface of the substrate100.

In this case, a germanium concentration in the stress pattern120may increase as a distance from the upper surface of the substrate100increases. For example, as shown inFIG. 14, a second scan line P3-P4crossing the stress pattern120in the third direction Z may be defined. The germanium concentration in the stress pattern120may increase along the second scan line P3-P4.

As shown inFIG. 14, the germanium concentration in the stress pattern120may exponentially increase along the second scan line P3-P4, but the inventive concepts are not limited thereto. For example, the germanium concentration in the stress pattern120may linearly increase along the second scan line P3-P4.

In some embodiments, as shown inFIG. 15, the first angle θ1formed between an extension line of the first surface110US of the first semiconductor pattern110and a line parallel to the upper surface of the substrate100may be smaller than the second angle θ2formed between an extension line of the fourth surface130LS of the third semiconductor pattern130and a line parallel to the upper surface of the substrate100. The first angle θ1may be an acute angle, but is not limited thereto. For example, the first surface110US of the third semiconductor pattern130may be parallel to the upper surface of the substrate100.

In this case, a germanium concentration in the stress pattern120may decrease as a distance from the upper surface of the substrate100increases. For example, as shown inFIG. 16, a third scan line P5-P6crossing the stress pattern120in the third direction Z may be defined. The germanium concentration in the stress pattern120may decrease along the third scan line P5-P6.

As shown inFIG. 16, the germanium concentration in the stress pattern120may exponentially decrease along the third scan line P5-P6, but the inventive concepts are not limited thereto. For example, the germanium concentration in the stress pattern120may linearly decrease along the third scan line P5-P6.

FIGS. 17 to 19are cross-sectional views illustrating a semiconductor device according to example embodiments.FIGS. 18 and 19are cross-sectional views taken along line D-D ofFIG. 17. For convenience of explanation, elements duplicated with the examples described above will be described in brief or omitted.

Referring toFIGS. 17 to 19, in a semiconductor device according to example embodiments, an angle formed between an extension line of a lower surface of the second semiconductor pattern126and a line parallel to the upper surface of the substrate100may be different from an angle formed between an extension line of an upper surface of the second semiconductor pattern126and a line parallel to the upper surface of the substrate100.

In some embodiments, as shown inFIG. 18, an angle formed between an extension line of the second surface126LS of the second semiconductor pattern126and a line parallel to the upper surface of the substrate100may be greater than an angle formed between an extension line of the third surface126US of the second semiconductor pattern126and a line parallel to the upper surface of the substrate100. In this case, a germanium concentration in the first oxide pattern122may be lower than a germanium concentration in the second oxide pattern124. The third surface126US of the second semiconductor pattern126may be parallel to the upper surface of the substrate100. In some embodiments, the third surface126US of the second semiconductor pattern126may be sloped at an acute angle with respect to the upper surface of the substrate100.

In this case, in some embodiments, a shortest (e.g., minimum) distance D1between the first semiconductor pattern110and the second semiconductor pattern126may be smaller than a shortest (e.g., minimum) distance D2between the second semiconductor pattern126and the third semiconductor pattern130.

In some embodiments, as shown inFIG. 19, an angle formed between an extension line of the second surface126LS of the second semiconductor pattern126and a line parallel to the upper surface of the substrate100may be smaller than an angle formed between an extension line of the third surface126US of the second semiconductor pattern126and a line parallel to the upper surface of the substrate100. In this case, a germanium concentration in the first oxide pattern122may be greater than a germanium concentration in the second oxide pattern124. The third surface126US of the second semiconductor pattern126may be parallel to the upper surface of the substrate100. In some embodiments, the third surface126US of the second semiconductor pattern126may be sloped at an acute angle with respect to the upper surface of the substrate100.

In this case, in some embodiments, a shortest (e.g., minimum) distance D1between the first semiconductor pattern110and the second semiconductor pattern126may be greater than a shortest (e.g., minimum) distance D2between the second semiconductor pattern126and the third semiconductor pattern130.

In some embodiments, an angle formed between an extension line of the first surface110US of the first semiconductor pattern110and a line parallel to the upper surface of the substrate100may be substantially the same as an angle formed between an extension line of the second surface126LS of the second semiconductor pattern126and a line parallel to the upper surface of the substrate100. Thus, a profile of the first surface110US of the first semiconductor pattern110and a profile of the second surface126LS of the second semiconductor pattern126may be symmetrical to each other with respect to the first oxide pattern122.

In some embodiments, an angle formed between an extension line of the fourth surface130LS of the third semiconductor pattern130and a line parallel to the upper surface of the substrate100may be substantially the same as an angle formed between an extension line of the third surface126US of the second semiconductor pattern126and a line parallel to the upper surface of the substrate100. Thus, a profile of the third surface126US of the second semiconductor pattern126and a profile of the fourth surface130LS of the third semiconductor pattern130may be symmetrical to each other with respect to the second oxide pattern124.

FIGS. 20 to 22are cross-sectional views illustrating a semiconductor device according to example embodiments.FIG. 21is a cross-sectional view taken along line E-E ofFIG. 20.FIG. 22is a cross-sectional view taken along line F-F ofFIG. 20. For convenience of explanation, elements duplicated with the examples described above will be described in brief or omitted.

Referring toFIGS. 20 to 22, in a semiconductor device according to example embodiments, the first oxide pattern122and the second oxide pattern124may be sequentially arranged in the first direction X. An angle formed between an extension line of each of an upper surface and a lower surface of the first oxide pattern122and a line parallel to the upper surface of the substrate100may be different from an angle formed between an extension line of each of an upper surface and a lower surface of the second oxide pattern124and a line parallel to the upper surface of the substrate100.

For example, an upper surface of the first semiconductor pattern110contacting the first oxide pattern122may include a fifth surface110US1. A lower surface of the third semiconductor pattern130contacting the first oxide pattern122may include a sixth surface130LS1. The upper surface of the first semiconductor pattern110contacting the second oxide pattern124may have a seventh surface110US2. The lower surface of the third semiconductor pattern130contacting the second oxide pattern124may include an eighth surface130LS2.

A third angle θ3formed between an extension line of the fifth surface110US1of the first semiconductor pattern110and a line parallel to the upper surface of the substrate100may be smaller than a fifth angle θ5formed between an extension line of the seventh surface110US2of the first semiconductor pattern110and a line parallel to the upper surface of the substrate100. A fourth angle θ4formed between an extension line of the sixth surface130LS1of the third semiconductor pattern130and a line parallel to the upper surface of the substrate100may be smaller than a sixth angle θ6formed between an extension line of the eighth surface130LS2of the third semiconductor pattern130and a line parallel to the upper surface of the substrate100.

In this case, a first germanium concentration in the first oxide pattern122may be greater than a second germanium concentration in the second oxide pattern124. In some embodiments, as shown in the drawings, the fifth surface110US1of the first semiconductor pattern110and the sixth surface130LS1of the third semiconductor pattern130may be sloped at an acute angle with respect to the upper surface of the substrate100. In some embodiments, the fifth surface110US1of the first semiconductor pattern110and the sixth surface130LS1of the third semiconductor pattern130may be parallel to the upper surface of the substrate100.

In some embodiments, the third angle θ3may be substantially the same as the fourth angle θ4. A profile of the fifth surface110US1of the first semiconductor pattern110and the sixth surface130LS1of the third semiconductor pattern130may be symmetrical to each other with respect to the first oxide pattern122. In some embodiments, the fifth angle θ5may be substantially the same as the sixth angle θ6. A profile of the seventh surface110US2of the first semiconductor pattern110and the eighth surface130LS2of the third semiconductor pattern130may be symmetrical to each other with respect to the second oxide pattern124.

In some embodiments, as the first germanium concentration in the first oxide pattern122and the second germanium concentration in the second oxide pattern124are adjusted, the tensile stress applied to the third semiconductor pattern130may be adjusted. For example, the tensile stress applied to a portion of the third semiconductor pattern130between the first gate electrode144and the stress pattern120and the tensile stress applied to a portion of the third semiconductor pattern130between the second gate electrode244and the stress pattern120may be separately adjusted.

FIGS. 23 to 27are cross-sectional views illustrating a semiconductor device according to example embodiments.FIGS. 24 and 26are cross-sectional views taken along line G-G ofFIG. 23.FIGS. 25 and 27are cross-sectional views taken along line H-H ofFIG. 23. For convenience of explanation, elements duplicated with the examples described above will be described in brief or omitted.

Referring toFIGS. 23 to 27, in a semiconductor device, the substrate100may include a base substrate102and a buried insulation layer (BOX)104. The fin structure FS may directly contact an upper surface of the buried insulation layer104.

The base substrate102may include a semiconductor material. The base substrate102may be, for example, a silicon substrate, but is not limited thereto.

The buried insulation layer104may be formed on the base substrate102. The buried insulation layer104may include, for example, silicon oxide, but is not limited thereto.

In some embodiments, as shown inFIGS. 24 and 25, the first semiconductor pattern (see, e.g.,110ofFIG. 2) in the first fin structure FS may be omitted. Thus, a lower surface of the stress pattern120may directly contact an upper surface of the buried insulation layer104.

In some embodiments, as shown inFIGS. 26 and 27, the first semiconductor pattern110of the first fin structure FS may directly contact the upper surface of the buried insulation layer104.

In some embodiments, the stress pattern120may include the first oxide pattern122, the second semiconductor pattern126, and the second oxide pattern124as described in the above examples.

FIGS. 28 to 30are cross-sectional views illustrating a semiconductor device according to example embodiments.FIG. 29is a cross-sectional view taken along line I-I ofFIG. 28.FIG. 30is a cross-sectional view taken along line J-J ofFIG. 28. For convenience of explanation, elements duplicated with the examples described above will be described in brief or omitted.

Referring toFIGS. 28 to 30, in a semiconductor device according to example embodiments, the substrate100may include a first region I and a second region II. The first region I and the second region II may be spaced apart from each other or may be connected to each other.

The first region I and the second region II may be one of a logic region, an SRAM region, and an input/output region. The first region I and the second region II may be regions in which same functions may be performed or may be regions in which different functions may be performed.

As an example, a semiconductor device formed in the first region I may be the semiconductor device described with reference toFIGS. 1 to 5. In some embodiments, a semiconductor device formed in the first region I may be any of the semiconductor devices described with reference toFIGS. 6 to 27.

A semiconductor device formed in the second region II of the substrate100may include a second fin structure FSA, a third gate structure GS3, and a fourth gate structure GS4.

The second fin structure FSA may protrude from the substrate100. The second fin structure FSA may extend in a fourth direction P parallel to an upper surface of the substrate100. The second fin structure FSA may be a portion of the substrate100or may include an epitaxial layer grown from the substrate100.

The second fin structure FSA may include a semiconductor material, for example, silicon or germanium. In some embodiments, the second fin structure FSA may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-III compound semiconductor. In some embodiments, the second fin structure FSA may include substantially the same material as the first semiconductor pattern110.

The third gate structure GS3and the fourth gate structure GS4may be formed on the second fin structure FSA and the field insulation layer105. The third gate structure GS3and the fourth gate structure GS4may cross the second fin structure FSA. For example, the third gate structure GS3and the fourth gate structure GS4may be spaced apart from each other in the fourth direction P and may extend in a fifth direction Q parallel to the upper surface of the substrate100and crossing the fourth direction P.

The third gate structure GS3may include a third gate insulation layer342, a third gate electrode344, third gate spacers346, a third gate trench GT3defined by the third gate spacers346, and a third capping pattern348.

The fourth gate structure GS4may include a fourth gate insulation layer442, a fourth gate electrode444, fourth gate spacers446, a fourth gate trench GT4defined by the fourth gate spacers446, and a fourth capping pattern448.

In some embodiments, transistors of different types may be formed in the first region I and the second region II, respectively. For example, a semiconductor device formed in the first region I may be an NMOS transistor, and a semiconductor device formed in the second region II may be a PMOS transistor. Alternatively, a semiconductor device formed in the first region I may be a PMOS transistor, and a semiconductor device formed in the second region II may be an NMOS transistor. In some embodiments, a transistor of the same type may be formed in each of the first region I and the second region II.

FIGS. 31 to 37are views illustrating stages in a method of fabricating a semiconductor device according to example embodiments.FIGS. 31, 34 and 36are cross-sectional views taken along line A-A′ ofFIG. 1.FIGS. 32, 33, 35, and 37are cross-sectional views taken along line B-B′ ofFIG. 1. For convenience of explanation, elements duplicated with the examples described above will be described in brief or omitted.

Referring toFIGS. 31 and 32, a preliminary semiconductor pattern FSp including the first semiconductor pattern110, a preliminary stress pattern120p, and the third semiconductor pattern130may be formed on the substrate100.

The first semiconductor pattern110, the preliminary stress pattern120p, and the third semiconductor pattern130may be sequentially stacked on the substrate100. In addition, the first semiconductor pattern110, the preliminary stress pattern120p, and the third semiconductor pattern130may extend in the first direction X.

The first semiconductor pattern110may include a first semiconductor material, for example, silicon (Si).

The preliminary stress pattern120pmay include a second semiconductor material, for example, a semiconductor material having an oxidation rate faster than that of the first semiconductor material. For example, the preliminary stress pattern120pmay include one of silicon-germanium oxide, silicon-germanium-carbide oxide, and germanium oxide.

The preliminary stress pattern120pmay include the second semiconductor pattern126, a fourth semiconductor pattern122p, and a fifth semiconductor pattern124p. The second semiconductor pattern126may be interposed between the fourth semiconductor pattern122pand the fifth semiconductor pattern124p.

In some embodiments, the fourth semiconductor pattern122p, the second semiconductor pattern126, and the fifth semiconductor pattern124pmay be sequentially stacked on the substrate100. The second semiconductor pattern126, the fourth semiconductor pattern122p, and the fifth semiconductor pattern124pmay extend in the first direction X.

The fourth semiconductor pattern122pand the fifth semiconductor pattern124pmay include the second semiconductor material. For example, the fourth semiconductor pattern122pand the fifth semiconductor pattern124pmay include at least one of silicon germanium (SiGe), silicon germanium carbide (SiGeC), and germanium (Ge).

In some embodiments, the second semiconductor pattern126may not include germanium (Ge). For example, the second semiconductor pattern126may include the first semiconductor material. For example, the second semiconductor pattern126may include silicon (Si).

The third semiconductor pattern130may include a third semiconductor material. The third semiconductor material may be a semiconductor material having an oxidation rate slower than that of the second semiconductor material. For example, the third semiconductor pattern130may include silicon (Si).

The first semiconductor pattern110, the preliminary stress pattern120p, and the second semiconductor pattern126may be formed by patterning a plurality of semiconductor patterns sequentially stacked on the substrate100using a mask pattern310as an etch mask.

Referring toFIG. 33, the field insulation layer105may be formed on sidewalls of the preliminary fin structure FSp.

The field insulation layer105may completely cover the sidewalls of the preliminary fin structure FSp.

The field insulation layer105may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but is not limited thereto.

Referring toFIGS. 34 and 35, the first fin structure FS including the stress pattern120may be formed.

For example, the fourth semiconductor pattern122pand the fifth semiconductor pattern124pmay be oxidized by performing an oxidation process OP. The oxidation process OP may include, for example, a wet oxidation process, but is not limited thereto.

The fourth semiconductor pattern122pand the fifth semiconductor pattern124pincluding silicon germanium (SiGe), silicon germanium carbide (SiGeC), or germanium (Ge) may be oxidized by performing the oxidation process OP to form the first oxide pattern122and the second oxide pattern124, respectively. However, the first semiconductor pattern110, the second semiconductor pattern126, and the third semiconductor pattern130that each include silicon (Si) having an oxidation rate slower than that of silicon germanium (SiGe), silicon germanium carbide (SiGeC), or germanium (Ge) may not be oxidized by the oxidation process OP. Thus, the stress pattern120including the first oxide pattern122, the second semiconductor pattern126, and the second oxide pattern124may be formed in the first fin structure FS.

Referring toFIGS. 36 and 37, a recess process may be performed on the field insulation layer105.

Thus, the field insulation layer105may expose at least a portion of the third semiconductor pattern130.

A height H1of an upper surface of the field insulation layer105may be higher than a height H2of an uppermost surface of the stress pattern120, with respect to the upper surface of the substrate100, but the inventive concepts are not limited thereto. For example, the height H1of the upper surface of the field insulation layer105may be lower than the height H2of the uppermost surface of the stress pattern120, with respect to the upper surface of the substrate100.

In some embodiments, the mask pattern310may be removed during or after the recess process.

The first gate structure GS1, the second gate structure GS2, the source/drain regions150, and the interlayer insulation layer160may be formed on the first fin structure FS. Accordingly, the semiconductor device as described with reference toFIGS. 2 and 3may be fabricated.

FIGS. 38 to 39are views illustrating stages in a method of fabricating a semiconductor device according to example embodiments.FIG. 38is a cross-sectional view taken along line A-A ofFIG. 1.FIG. 39is a cross-sectional view taken along line B-B ofFIG. 1. For convenience of explanation, elements duplicated with the examples described above will be described in brief or omitted.

Referring toFIGS. 38 and 39, the preliminary fin structure FSp including the first semiconductor pattern110, the preliminary stress pattern120p, and the second semiconductor pattern126may be formed on the substrate100.

The preliminary stress pattern120pmay include the second semiconductor pattern126, the fourth semiconductor pattern122p, and the fifth semiconductor pattern124p. The second semiconductor pattern126may be interposed between the fourth semiconductor pattern122pand the fifth semiconductor pattern124p.

In some embodiments, the fourth semiconductor pattern122p, the second semiconductor pattern126, and the fifth semiconductor pattern124pmay be sequentially arranged in a first direction X. The fourth semiconductor pattern122pand the fifth semiconductor pattern124pmay each extend in the first direction X.

The same processes as described with reference toFIGS. 33 to 37may be performed. The first gate structure GS1, the second gate structure GS2, source/drain regions150, and the interlayer insulation layer160may be formed on the first fin structure FS. Accordingly, the semiconductor device described with reference toFIGS. 10 and 11may be fabricated.

FIGS. 40 to 42are views illustrating stages in a method of fabricating a semiconductor device according to example embodiments.FIG. 40is a cross-sectional view taken along line C-C ofFIG. 12.FIGS. 41 and 42are graphs illustrating a change in a germanium concentration along a fourth scan line P7-P8ofFIG. 40. For convenience of explanation, elements duplicated with the examples described above will be described in brief or omitted.

FIG. 40, the preliminary fin structure FSp including the first semiconductor pattern110, the preliminary stress pattern120p, and the second semiconductor pattern126may be formed.

In some embodiments, the germanium concentration in the preliminary stress pattern120pmay be changed as a distance from the upper surface of the substrate100increases. For example, the fourth scan line P7-P8crossing the preliminary stress pattern120pin the third direction Z may be defined. The germanium concentration in the preliminary stress pattern120pmay be changed along the fourth scan line P7-P8.

For example, as shown inFIG. 41, the germanium concentration in the preliminary stress pattern120pmay increase along the fourth scan line P7-P8.

Next, the same processes as described with reference toFIGS. 33 to 37may be performed. The first gate structure GS1, the second gate structure GS2, the source/drain regions150, and the interlayer insulation layer160may be formed on the first fin structure FS. Accordingly, the semiconductor device described with reference toFIGS. 13 and 14(or15and16) may be fabricated.

For example, as shown inFIG. 42, the germanium concentration in the preliminary stress pattern120pmay decrease along the fourth scan line P7-P8.

Next, the same processes as described with reference toFIGS. 33 to 37may be performed. The first gate structure GS1, the second gate structure GS2, the source/drain regions150, and the interlayer insulation layer160may be formed on the first fin structure FS. Accordingly, the semiconductor device described with reference toFIG. 15may be fabricated.

Though the present inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present disclosure as defined by the following claims.