Reduced cap layer erosion for borderless contacts

A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices, and more particularly to a method of forming borderless contacts and structure thereof.

BACKGROUND

Semiconductors are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. Integrated circuits typically include multiple transistors fabricated in single crystal silicon. It is common for there to be millions of integrated circuits or semiconductor devices on a single semiconductor product. One type of semiconductor device is a semiconductor storage device, such as a dynamic random access memory (DRAM), which uses a charge to store information.

Semiconductor devices are fabricated by sequentially depositing, patterning, and doping many insulating, conductive and semiconductor layers. Portions of integrated circuits are often connected to subsequently formed upper layers by forming holes over the circuits and then filling the holes with semiconductor or conductive material to form vias or contacts. The term “contact” used herein refers also to vias.

One method of making contact to an underlying electronic circuit or component region is by forming borderless contacts, as shown inFIGS. 1 and 2.FIG. 1illustrates a perspective view of a wordline and bitline wiring structure disposed over a memory array such as a DRAM device100.FIG. 2shows a cross-sectional view of the DRAM device100shown in FIG.1. Component regions102which may comprise DRAM memory cells are formed in a workpiece120. Wordlines104are positioned perpendicular to bitlines1112, with each intersection of a wordline104and bitline112being proximate a DRAM memory cell or component region102so that the cell can be accessed (e.g., read from or written to). A nitride cap layer106is disposed over the top of each wordline104, and nitride sidewall spacers108are formed over the sidewalls of the wordlines104and the nitride cap layer106, as shown. The nitride cap layer106and sidewall spacers108provide electrical isolation for the wordlines104from subsequently formed bitlines112and borderless contacts114.

An insulating material (not shown) is disposed between adjacent bitlines112and contacts114. The insulating material is deposited, and the insulating material is patterned with the bitline112and contact114pattern. The bitlines112and contacts114are formed simultaneously in a damascene process as the insulating material is filled with a conductive material. The shape of the contacts114is defined by the sidewall spacers108; thus, the contacts114are self-aligned with the underlying component regions102which may comprise a source or drain of an access transistor for a DRAM cell, for example. This self-aligning method of making contact to component regions102is referred to as a borderless contact114technique. Borderless contacts114are used often in the manufacturing of memory devices and other semiconductor device applications.

A problem with prior art borderless contact114formation methods and structures is that the nitride cap layer106can be eroded during the various etch processes, such as a reactive ion etch (RIE) which is often used to manufacture the device. If an excessive amount of the nitride cap layer106is eroded away, then shorts can be created between the wordlines104and bitlines112, causing device failures and decreasing yields. For example, the insulating material the bitlines112and contacts114are formed in typically comprises an oxide. An etch selective to nitride is used to etch the oxide to form the bitline112and contact114pattern. However, this selective etch process may also etch away a portion or all of the nitride cap layer106. As semiconductor devices are made smaller, reduced bitline capacitance is required, resulting in thinner insulating layers, further contributing to the nitride cap layer106erosion problem.

Thus, what is needed in the art is a method of manufacturing borderless contacts that preserves the nitride cap layer106.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention, which provide an improved method of manufacturing borderless contacts and structure thereof.

In accordance with a preferred embodiment of the present invention, a method of manufacturing a borderless contact includes providing a workpiece, the workpiece having at least one component region and a first insulating layer formed over the at least one component region, and depositing a first conductive material over the workpiece. A first etch selectivity material is deposited over the first conductive material, a second etch selectivity material is deposited over the first etch selectivity material, and the second etch selectivity material, the first etch selectivity material and the first conductive material are etched to form a plurality of first conductive lines. The second etch selectivity material, first etch selectivity material and first conductive lines include sidewalls, and the second etch selectivity material includes a top surface. The method includes forming sidewall spacers on the sidewalls of the second etch selectivity material, first etch selectivity material and first conductive lines, depositing a liner over exposed portions of the workpiece, the sidewall spacers and the second etch selectivity material top surface, and depositing a second insulating layer over the liner to a height greater than the top surface of the second etch selectivity material. The second insulating layer is patterned with a pattern for a plurality of second conductive lines, the second conductive lines being positioned in a different direction than the first conductive lines, and the liner is removed from at least over the component region. The first insulating layer is removed from over the component region, and a second conductive material is deposited over the second insulating layer to fill the pattern for the plurality of second conductive lines, forming a plurality of second conductive lines and a borderless contact beneath at least one second conductive line abutting the at least one component region.

In accordance with another preferred embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a workpiece, the workpiece having a plurality of component regions and a first insulating layer formed over the component regions, depositing a first conductive material over the workpiece, and depositing a first etch selectivity material over the first conductive material. The method includes depositing a second etch selectivity material over the first etch selectivity material, etching the second etch selectivity material, the first etch selectivity material and the first conductive material to form a plurality of first conductive lines, the second etch selectivity material, first etch selectivity material and first conductive lines comprising sidewalls, the second etch selectivity material comprising a top surface, and depositing a second insulating layer having the same etch selectivity as the first etch selectivity material over the second etch selectivity material and exposed portions of the workpiece. The second insulating layer is anisotropically etched to form sidewall spacers on the sidewalls of the second etch selectivity material, first etch selectivity material and first conductive lines, and a nitride liner is deposited over exposed portions of the workpiece, the sidewall spacers and the second etch selectivity material top surface. A third insulating layer is deposited over the nitride liner to a height greater than the top surface of the second etch selectivity material, and the third insulating layer is patterned with a pattern for a plurality of second conductive lines, the second conductive lines being positioned in a different direction than the first conductive lines. The nitride liner is removed from the component regions, and the first insulating layer is removed from over the component region using an etch process selective to the first etch selectivity material, also removing a portion of the second etch selectivity material. A second conductive material is deposited over the second insulating layer to fill the pattern for the plurality of second conductive lines, forming a plurality of second conductive lines and a borderless contact beneath at least one second conductive line abutting the at least one component region.

In accordance with yet another preferred embodiment of the present invention, a semiconductor device includes a workpiece, the workpiece having at least one component region and a first insulating layer formed over the workpiece. A plurality of first conductive lines are disposed over the workpiece, a first etch selectivity material is disposed over the first conductive lines, and a second etch selectivity material is disposed over the first etch selectivity material. A sidewall spacer is disposed on the sidewalls of the second etch selectivity material, first etch selectivity material and first conductive lines. A second insulating layer is disposed over at least the sidewall spacer, the second insulating layer having a height greater than the top surface of the second etch selectivity material. A plurality of second conductive lines is disposed within the second insulating layer over the first conductive lines, the second conductive lines being positioned in a different direction than the first conductive lines. A borderless contact extends beneath a portion of at least one second conductive line to abut the workpiece component region, the borderless contact abutting a portion of the sidewall spacer.

Advantages of preferred embodiments of the present invention include preserving the first etch selectivity layer during the etch processes to open the various material layers from over the component regions, preventing shorting of the wordlines to subsequently formed bitlines during the formation of the borderless contacts. Embodiments of the present invention result in fewer device failures and improved yields.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to preferred embodiments in a specific context, namely a semiconductor memory device. The invention may also be applied, however, to other semiconductor device applications.

FIG. 3shows a cross-sectional view of a semiconductor device200that will be manufactured in accordance with a preferred embodiment of the present invention. First, a workpiece220is provided. The workpiece220preferably comprises a semiconductor wafer, and may include a semiconductor substrate comprising silicon or other semiconductor materials covered by an insulating layer, for example. The workpiece may also include active components or circuits formed in the front end of line (FEOL). The workpiece may comprise silicon oxide over single-crystal silicon, for example. The workpiece may include other conductive layers or other semiconductor elements, e.g. transistors, diodes, etc. Compound semiconductors, GaAs, InP, Si/Ge, or SiC, as examples, may be used in place of silicon. The workpiece220preferably comprises component regions202formed thereon. Embodiments of the present invention provide a method of forming a borderless contact abutting the component regions202, to be described further herein.

The workpiece220includes an isolation oxide222formed at the top portion thereof. The workpiece220may include a plurality of deep trenches224formed therein, wherein each deep trench224includes a capacitor adapted to store a bit of data. The bottom of the deep trenches224have been lined with an insulator226that functions as a capacitor dielectric, and the deep trenches224are filled with a semiconductive material228to form one of the plates of the capacitor. A buried strap230is formed at a top portion of each deep trench capacitor.

In the drawing shown, the access transistors for the deep trench storage capacitors are positioned vertically. For example, a gate oxide232is disposed between a semiconductive material234, and the component region202comprises a source or drain of the access transistor. However, embodiments of the present invention also are useful in memory cells having lateral access transistors. Shallow trench isolation (STI) regions218are formed within the workpiece220and filled with an insulator such as high density plasma (HDP) oxide, for example. The STI is used to isolate active areas from one another.

A gate conductor material236is deposited over the isolation oxide222and semiconductive material234, as shown. The gate conductor material236preferably comprises polysilicon and a metal, such as a silicide, deposited in a thickness of about 1000 to 2000 Angstroms, for example. Alternatively, the gate conductive material236may comprise other conductive materials such as tungsten, as an example.

A first etch selectivity material238is deposited over the gate conductor material236. The first etch selectivity material238preferably comprises silicon nitride, and may alternatively comprise silicon oxycarbide (silicon combined with oxygen, carbon and nitrogen) or other materials, for example. The first etch selectivity material238preferably comprises a thickness of about 1000 to 2000 Angstroms, for example.

A second etch selectivity material240is deposited over the first etch selectivity material238, as shown in FIG.4. The second etch selectivity material240preferably comprises an oxide such as silicon dioxide, and alternatively the second etch selectivity material240may comprise other materials that provide etch selectivity to the first etch selectivity material238. For example, the second etch selectivity material240may alternatively comprise silicon oxycarbide (if the first etch selectivity material238does not comprise silicon oxycarbide) or other materials. The second etch selectivity material240preferably comprises a thickness of about 250 to 750 Angstroms, for example. The second etch selectivity material240may be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD), as examples.

A photoresist242is deposited over the second etch selectivity material240, as shown in FIG.5. The photoresist242is patterned and used as a mask to pattern the underlying second etch selectivity material240, first etch selectivity material238, and gate conductor material236, as shown. The photoresist242preferably comprises a thickness of between about 3000 and 5000 Angstroms, for example. With the patterned photoresist242left remaining over the top of the second etch selectivity material240, the workpiece220is exposed to a non-selective etch process to etch the second etch selectivity material240, first selectivity material238and gate conductor material236, forming a plurality of conductive lines which in one embodiment comprise wordlines236, as shown in FIG.5. The non-selective etch process may comprise CF4, CHF3, and/or combinations thereof, as an example, although other etch chemistries may alternatively be used.

The first etch selectivity material238and second etch selectivity material240comprise the same pattern as the wordlines236after the etch processes. The first etch selectivity material238, second etch selectivity material240and wordlines236comprise sidewalls. The second etch selectivity material240has a top surface. The gate conductor material236functions as a gate contact for the underlying capacitor, and also as a wordline236for the memory cell array. For example, the wordline236extends in and out of the paper, and resides over a plurality of memory cells in the row.

The patterned first etch selectivity material238corresponds to the nitride cap layer106shown in the prior art structure ofFIGS. 1 and 2, for example. In accordance with embodiments of the present invention, it is desired that none of the first etch selectivity material238be removed in the subsequent formation of bitlines and borderless contacts, to be discussed further herein.

After the gate conductor material236is etched, the photoresist242is removed, and a thin oxide layer244is formed on the sidewalls of the gate conductor material or wordlines236, as shown in FIG.6. The thin oxide layer244may be formed by exposing the workpiece220to oxygen and then heating it, for example. The thin oxide layer244preferably comprises a thickness of between about 50 and 150 Angstroms, for example. The thin oxide layer244is typically not formed on the sidewalls of the first etch selectivity material238and second etch selectivity material240, for example.

An insulating layer246is deposited over the top surface of the workpiece220to cover the exposed portions of the isolation oxide222, the top surface of the second etch selectivity material240, sidewalls of the first and second etch selectivity materials238and240, and thin oxide layer244, as shown in FIG.6. The insulating layer246preferably comprises silicon nitride, and alternatively may comprise other materials, as examples. The insulating layer246preferably comprises a material with the same etch selectivity as the first etch selectivity material238in one embodiment of the present invention.

The insulating layer246is etched, preferably using an anisotropic etch process, for example, to remove the insulating layer246from the top surface of the second etch selectivity material240and from over the top surface of the isolation oxide222over the component region202, as shown in FIG.7. Sidewall spacers248are left residing adjacent the sidewalls of the first etch selectivity material238, second etch selectivity material240, and adjacent the thin oxide layer244on the sidewalls of the gate conductor material236. The sidewall spacers248comprise a thickness of about 150 to 300 Angstroms, for example.

A nitride liner250is deposited over the exposed portions of the isolation oxide222, the sidewall spacers248, and the top surface of the second etch selectivity material240, as shown in FIG.8. The nitride liner250preferably comprises silicon nitride and alternatively may comprise other nitride materials deposited in a thickness of about 50 to 200 Angstroms, for example.

A first insulating layer252is deposited over the nitride liner250, as shown in FIG.9. The first insulating layer252preferably comprises borophosphosilicate glass (BPSG), and may alternatively comprise other insulating materials such as silicon dioxide, for example. The first insulating layer252preferably comprises doped oxide, which is deposited and then reflowed by heating the workpiece220. The first insulating layer252preferably entirely fills the space between the patterned wordlines236, first etch selectivity material238, and second etch selectivity material240, and more preferably, extends to a height greater than the top surface of the second etch selectivity material240, as shown. The first insulating layer252may then be polished back to produce a smooth top surface over the first insulating layer252. Next, a second insulating layer254is deposited over the first insulating layer252. The second insulating layer254preferably comprises tetraethoxysilate (TEOS) and may alternatively comprise other insulators, such as fluorinated silicon dioxide or low dielectric constant materials, as examples. The second insulating layer254preferably comprises a thickness of between about 1000 to 4000 Angstroms, for example. The second insulating layer254may be deposited by CVD or other deposition techniques.

A photoresist (not shown) is deposited over the second insulating layer254, and the photoresist is patterned with the pattern for bitlines that run in a direction different from the wordline236direction. The pattern from the photoresist is transferred to the second insulating layer254and first insulating layer252, for example, by etching the insulating layer252/254using the photoresist as a mask, as shown inFIG. 10, forming the pattern258for the bitlines. The etch chemistry for etching the first and second insulating layers252and254may comprise C4F8, CH2F2, Ar and/or combinations thereof, as an example, although other etch chemistries may alternatively be used. The photoresist may then be removed, or may be consumed in the pattern transfer step.

In one preferred embodiment, a separate mask and patterning step is not required to form the borderless contacts. Rather, the pattern256for the borderless contacts is formed due to the fact that the borderless contacts will be formed immediately beneath the bitline pattern258between the patterned wordlines236, first etch selectivity material238, and second etch selectivity material240. In another embodiment, a separate mask (not shown) may be used to pattern the borderless contacts. In either embodiment, the borderless contact allows the density of the memory cells and contacts to be increased.

Note that inFIGS. 10-13, the pattern258for only one bitline is shown; however, there may be a plurality of bitline patterns258formed elsewhere on the workpiece220in locations of the memory cell array extending into and out of the page, for example. Typically in a memory cell array, for example, there are hundreds or thousands of parallel bitlines and wordlines.

The nitride liner246remains residing over the isolation oxide222and top surface of the second etch selectivity material240at this point of the process flow. However, the top corner edges of the nitride liner250may be partially removed during the etch process of the first insulating layer252and the second insulating layer254, not shown. The nitride liner250is next exposed to an etch process to remove the nitride liner250from at least the top surface of the second etch selectivity material240and from over the top surface of the isolation oxide222, as shown in FIG.11. The nitride liner250etch may comprise an anisotropic etch, in one embodiment of the invention, for example. The etch chemistry for etching the nitride liner250may comprise an etch that etches nitride selective to oxide, such as CH3F, CHF3, CO2, O2and/or combinations thereof, and may alternatively comprise other etch chemistries, as examples.

Next, the workpiece220is exposed to an oxide etch selective to the material of the first etch selectivity material238in order to remove the isolation oxide222from over the component regions202. For example, if the first etch selectivity material238comprises a nitride, then an etch selective to nitride is used. This selective etch process may also remove at least a portion of the second etch selectivity material240from over the top surface of the first etch selectivity material238, as shown in FIG.12. The etch chemistry for etching isolation oxide222may comprise C4F8, CO, Ar and/or combinations thereof, as an example, although other etch chemistries may alternatively be used.

Advantageously, because of the presence of the second etch selectivity material240, the first etch selectivity material238is prevented from being etched or removed during the process of opening the region of the workpiece220over the top surface of the component region202(by removing the isolation oxide222, nitride liner250and first and second insulating layers252and254) to make electrical contact with borderless contacts. Note that a small top portion of the sidewall spacers248may reside above the top surface of the first etch selectivity material238, after the etch process to remove the isolation oxide222and second etch selectivity material240described herein. The process flow may include an optional final non-selective etch process to remove any residuals such as nitrides or oxides prior to depositing a conductive material, to ensure good contact between the borderless contact and the component region of the workpiece.

Next, a conductive material is deposited over the second insulating layer254in order to fill the patterns256and258for the bitlines and borderless contacts, respectively, as shown in FIG.13. The excess conductive material is removed from the top surface of the second insulating layer254, for example, using a chemical mechanical polish (CMP). Borderless contacts260aand260bare formed during the damascene fill process beneath the bitlines262that are also formed. The borderless contacts260aand260bmake electrical contact with and directly abut the component regions202aand202b, respectively. In one embodiment, the component regions202aand202bmay comprise memory cells, and in another embodiment, the component regions202aand202bcomprise the source or drain of an access transistor for storage capacitors224aand224bof memory cells, respectively.

Processing of the semiconductor device200is then continued to complete the structure. Note that there may be other processes or steps included in the process flow that have not been described herein because they are not directed to the present invention. For example, the component region202may be doped at one or more stages of manufacturing, e.g., a light doping prior to the sidewall spacer248formation, and then a heavier doping after the sidewall spacer248formation, to improve electrical contact to the subsequently formed borderless contacts260aand260b.

The first etch selectivity material238has been described as a nitride, and the second etch selectivity material240has been described as an oxide, herein. However, alternatively, the first etch selectivity material238may comprise an oxide, and the second etch selectivity material240may comprise a nitride. In preferred embodiments of the present invention, the first and selectivity materials238and240comprise materials having different etch selectivities.

Embodiments of the present invention achieve technical advantages as a method of forming borderless contacts260aand260band structure for same in which the first etch selectivity material238is preserved and not removed during the etch processes to open the various material layers, e.g., second insulating layer254, first insulating layer252, nitride liner250and isolation oxide222, from over the component regions202aand202b. Because the first etch selectivity material238is not removed and remains in place, shorting of the wordlines236to subsequently formed bitlines262is prevented, in accordance with embodiments of the present invention. Therefore, embodiments of the present invention result in fewer device failures and improved yields.