Scheduling cache traffic in a tile-based architecture

A tile-based system for processing graphics data. The tile based system includes a first screen-space pipeline, a cache unit, and a first tiling unit. The first tiling unit is configured to transmit a first set of primitives that overlap a first cache tile and a first prefetch command to the first screen-space pipeline for processing, and transmit a second set of primitives that overlap a second cache tile to the first screen-space pipeline for processing. The first prefetch command is configured to cause the cache unit to fetch data associated with the second cache tile from an external memory unit. The first tiling unit may also be configured to transmit a first flush command to the screen-space pipeline for processing with the first set of primitives. The first flush command is configured to cause the cache unit to flush data associated with the first cache tile.

BACKGROUND OF THE INVENTION

Field of the Invention

Embodiments of the present invention relate generally to graphics processing and, more specifically, to scheduling cache traffic in a tile-based architecture.

Description of the Related Art

Some graphics subsystems for rendering graphics images implement a tiling architecture, where one or more render targets, such as a frame buffer, are divided into screen space partitions referred to as tiles. In such a tiling architecture, the graphics subsystem rearranges work such that the work associated with any particular tile remains in an on-chip cache for a longer time than with an architecture that does not rearrange work in this manner. This rearrangement helps to improve memory bandwidth as compared with a non-tiling architecture.

In some tiling architectures, tile-oriented data is stored in a cache. When primitives associated with a particular tile are processed, the data for that tile is fetched from an external memory into the cache. Similarly, at some points in time during operation of the tiling unit, the cache flushes data stored in the cache out to the external memory unit. Generally speaking, the points in time at which the data is fetched from and flushed to the external memory unit are determined by standard caching mechanisms. For example, typically, data associated with a particular tile is fetched when the tile is ready to be processed. Data is typically fetched at this point in time because there is likely no data related to the particular tile in the cache, and thus a cache miss results. However, because of the latency associated with fetching data from external memory, fetching data when the tile is ready to be processed may delay processing operations on the tile. During such delays, the screen-space portion of the graphics pipeline cannot make forward progress on the particular tile, which can negatively impact overall system performance.

As the foregoing has demonstrated, what is needed in the art is more effective approach to accessing and caching tile-oriented data in a tile-based architecture.

SUMMARY OF THE INVENTION

One embodiment of the present invention sets forth a tile-based system for processing graphics data. The tile based system includes a first screen-space pipeline, a cache unit, and a first tiling unit. The first tiling unit is configured to transmit a first set of primitives that overlap a first cache tile and a first prefetch command to the first screen-space pipeline for processing, and transmit a second set of primitives that overlap a second cache tile to the first screen-space pipeline for processing. The first prefetch command is configured to cause the cache unit to fetch data associated with the second cache tile from an external memory unit.

DETAILED DESCRIPTION

System Overview

FIG. 1is a block diagram illustrating a computer system100configured to implement one or more aspects of the present invention. As shown, computer system100includes, without limitation, a central processing unit (CPU)102and a system memory104coupled to a parallel processing subsystem112via a memory bridge105and a communication path113. Memory bridge105is further coupled to an I/O (input/output) bridge107via a communication path106, and I/O bridge107is, in turn, coupled to a switch116.

In operation, I/O bridge107is configured to receive user input information from input devices108, such as a keyboard or a mouse, and forward the input information to CPU102for processing via communication path106and memory bridge105. Switch116is configured to provide connections between I/O bridge107and other components of the computer system100, such as a network adapter118and various add-in cards120and121.

As also shown, I/O bridge107is coupled to a system disk114that may be configured to store content and applications and data for use by CPU102and parallel processing subsystem112. As a general matter, system disk114provides non-volatile storage for applications and data and may include fixed or removable hard disk drives, flash memory devices, and CD-ROM (compact disc read-only-memory), DVD-ROM (digital versatile disc-ROM), Blu-ray, HD-DVD (high definition DVD), or other magnetic, optical, or solid state storage devices. Finally, although not explicitly shown, other components, such as universal serial bus or other port connections, compact disc drives, digital versatile disc drives, film recording devices, and the like, may be connected to I/O bridge107as well.

In various embodiments, memory bridge105may be a Northbridge chip, and I/O bridge107may be a Southbrige chip. In addition, communication paths106and113, as well as other communication paths within computer system100, may be implemented using any technically suitable protocols, including, without limitation, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol known in the art.

In some embodiments, parallel processing subsystem112comprises a graphics subsystem that delivers pixels to a display device110that may be any conventional cathode ray tube, liquid crystal display, light-emitting diode display, or the like. In such embodiments, the parallel processing subsystem112incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry. As described in greater detail below inFIG. 2, such circuitry may be incorporated across one or more parallel processing units (PPUs) included within parallel processing subsystem112. In other embodiments, the parallel processing subsystem112incorporates circuitry optimized for general purpose and/or compute processing. Again, such circuitry may be incorporated across one or more PPUs included within parallel processing subsystem112that are configured to perform such general purpose and/or compute operations. In yet other embodiments, the one or more PPUs included within parallel processing subsystem112may be configured to perform graphics processing, general purpose processing, and compute processing operations. System memory104includes at least one device driver103configured to manage the processing operations of the one or more PPUs within parallel processing subsystem112.

In various embodiments, parallel processing subsystem112may be integrated with one or more other the other elements ofFIG. 1to form a single system. For example, parallel processing subsystem112may be integrated with CPU102and other connection circuitry on a single chip to form a system on chip (SoC).

It will be appreciated that the system shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of CPUs102, and the number of parallel processing subsystems112, may be modified as desired. For example, in some embodiments, system memory104could be connected to CPU102directly rather than through memory bridge105, and other devices would communicate with system memory104via memory bridge105and CPU102. In other alternative topologies, parallel processing subsystem112may be connected to I/O bridge107or directly to CPU102, rather than to memory bridge105. In still other embodiments, I/O bridge107and memory bridge105may be integrated into a single chip instead of existing as one or more discrete devices. Lastly, in certain embodiments, one or more components shown inFIG. 1may not be present. For example, switch116could be eliminated, and network adapter118and add-in cards120,121would connect directly to I/O bridge107.

FIG. 2is a block diagram of a parallel processing unit (PPU)202included in the parallel processing subsystem112ofFIG. 1, according to one embodiment of the present invention. AlthoughFIG. 2depicts one PPU202, as indicated above, parallel processing subsystem112may include any number of PPUs202. As shown, PPU202is coupled to a local parallel processing (PP) memory204. PPU202and PP memory204may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or memory devices, or in any other technically feasible fashion.

In some embodiments, PPU202comprises a graphics processing unit (GPU) that may be configured to implement a graphics rendering pipeline to perform various operations related to generating pixel data based on graphics data supplied by CPU102and/or system memory104. When processing graphics data, PP memory204can be used as graphics memory that stores one or more conventional frame buffers and, if needed, one or more other render targets as well. Among other things, PP memory204may be used to store and update pixel data and deliver final pixel data or display frames to display device110for display. In some embodiments, PPU202also may be configured for general-purpose processing and compute operations.

In operation, CPU102is the master processor of computer system100, controlling and coordinating operations of other system components. In particular, CPU102issues commands that control the operation of PPU202. In some embodiments, CPU102writes a stream of commands for PPU202to a data structure (not explicitly shown in eitherFIG. 1orFIG. 2) that may be located in system memory104, PP memory204, or another storage location accessible to both CPU102and PPU202. A pointer to the data structure is written to a pushbuffer to initiate processing of the stream of commands in the data structure. The PPU202reads command streams from the pushbuffer and then executes commands asynchronously relative to the operation of CPU102. In embodiments where multiple pushbuffers are generated, execution priorities may be specified for each pushbuffer by an application program via device driver103to control scheduling of the different pushbuffers.

As also shown, PPU202includes an I/O (input/output) unit205that communicates with the rest of computer system100via the communication path113and memory bridge105. I/O unit205generates packets (or other signals) for transmission on communication path113and also receives all incoming packets (or other signals) from communication path113, directing the incoming packets to appropriate components of PPU202. For example, commands related to processing tasks may be directed to a host interface206, while commands related to memory operations (e.g., reading from or writing to PP memory204) may be directed to a crossbar unit210. Host interface206reads each pushbuffer and transmits the command stream stored in the pushbuffer to a front end212.

As mentioned above in conjunction withFIG. 1, the connection of PPU202to the rest of computer system100may be varied. In some embodiments, parallel processing subsystem112, which includes at least one PPU202, is implemented as an add-in card that can be inserted into an expansion slot of computer system100. In other embodiments, PPU202can be integrated on a single chip with a bus bridge, such as memory bridge105or I/O bridge107. Again, in still other embodiments, some or all of the elements of PPU202may be included along with CPU102in a single integrated circuit or system of chip (SoC).

In operation, front end212transmits processing tasks received from host interface206to a work distribution unit (not shown) within task/work unit207. The work distribution unit receives pointers to processing tasks that are encoded as task metadata (TMD) and stored in memory. The pointers to TMDs are included in a command stream that is stored as a pushbuffer and received by the front end unit212from the host interface206. Processing tasks that may be encoded as TMDs include indices associated with the data to be processed as well as state parameters and commands that define how the data is to be processed. For example, the state parameters and commands could define the program to be executed on the data. The task/work unit207receives tasks from the front end212and ensures that GPCs208are configured to a valid state before the processing task specified by each one of the TMDs is initiated. A priority may be specified for each TMD that is used to schedule the execution of the processing task. Processing tasks also may be received from the processing cluster array230. Optionally, the TMD may include a parameter that controls whether the TMD is added to the head or the tail of a list of processing tasks (or to a list of pointers to the processing tasks), thereby providing another level of control over execution priority.

PPU202advantageously implements a highly parallel processing architecture based on a processing cluster array230that includes a set of C general processing clusters (GPCs)208, where C≥1. Each GPC208is capable of executing a large number (e.g., hundreds or thousands) of threads concurrently, where each thread is an instance of a program. In various applications, different GPCs208may be allocated for processing different types of programs or for performing different types of computations. The allocation of GPCs208may vary depending on the workload arising for each type of program or computation.

Memory interface214includes a set of D of partition units215, where D≥1. Each partition unit215is coupled to one or more dynamic random access memories (DRAMs)220residing within PPM memory204. In one embodiment, the number of partition units215equals the number of DRAMs220, and each partition unit215is coupled to a different DRAM220. In other embodiments, the number of partition units215may be different than the number of DRAMs220. Persons of ordinary skill in the art will appreciate that a DRAM220may be replaced with any other technically suitable storage device. In operation, various render targets, such as texture maps and frame buffers, may be stored across DRAMs220, allowing partition units215to write portions of each render target in parallel to efficiently use the available bandwidth of PP memory204.

A given GPCs208may process data to be written to any of the DRAMs220within PP memory204. Crossbar unit210is configured to route the output of each GPC208to the input of any partition unit215or to any other GPC208for further processing. GPCs208communicate with memory interface214via crossbar unit210to read from or write to various DRAMs220. In one embodiment, crossbar unit210has a connection to I/O unit205, in addition to a connection to PP memory204via memory interface214, thereby enabling the processing cores within the different GPCs208to communicate with system memory104or other memory not local to PPU202. In the embodiment ofFIG. 2, crossbar unit210is directly connected with I/O unit205. In various embodiments, crossbar unit210may use virtual channels to separate traffic streams between the GPCs208and partition units215.

Again, GPCs208can be programmed to execute processing tasks relating to a wide variety of applications, including, without limitation, linear and nonlinear data transforms, filtering of video and/or audio data, modeling operations (e.g., applying laws of physics to determine position, velocity and other attributes of objects), image rendering operations (e.g., tessellation shader, vertex shader, geometry shader, and/or pixel/fragment shader programs), general compute operations, etc. In operation, PPU202is configured to transfer data from system memory104and/or PP memory204to one or more on-chip memory units, process the data, and write result data back to system memory104and/or PP memory204. The result data may then be accessed by other system components, including CPU102, another PPU202within parallel processing subsystem112, or another parallel processing subsystem112within computer system100.

As noted above, any number of PPUs202may be included in a parallel processing subsystem112. For example, multiple PPUs202may be provided on a single add-in card, or multiple add-in cards may be connected to communication path113, or one or more of PPUs202may be integrated into a bridge chip. PPUs202in a multi-PPU system may be identical to or different from one another. For example, different PPUs202might have different numbers of processing cores and/or different amounts of PP memory204. In implementations where multiple PPUs202are present, those PPUs may be operated in parallel to process data at a higher throughput than is possible with a single PPU202. Systems incorporating one or more PPUs202may be implemented in a variety of configurations and form factors, including, without limitation, desktops, laptops, handheld personal computers or other handheld devices, servers, workstations, game consoles, embedded systems, and the like.

Operation of GPC208is controlled via a pipeline manager305that distributes processing tasks received from a work distribution unit (not shown) within task/work unit207to one or more streaming multiprocessors (SMs)310. Pipeline manager305may also be configured to control a work distribution crossbar330by specifying destinations for processed data output by SMs310.

In one embodiment, GPC208includes a set of M of SMs310, where M≥1. Also, each SM310includes a set of functional execution units (not shown), such as execution units and load-store units. Processing operations specific to any of the functional execution units may be pipelined, which enables a new instruction to be issued for execution before a previous instruction has completed execution. Any combination of functional execution units within a given SM310may be provided. In various embodiments, the functional execution units may be configured to support a variety of different operations including integer and floating point arithmetic (e.g., addition and multiplication), comparison operations, Boolean operations (AND, OR, XOR), bit-shifting, and computation of various algebraic functions (e.g., planar interpolation and trigonometric, exponential, and logarithmic functions, etc.). Advantageously, the same functional execution unit can be configured to perform different operations.

In operation, each SM310is configured to process one or more thread groups. As used herein, a “thread group” or “warp” refers to a group of threads concurrently executing the same program on different input data, with one thread of the group being assigned to a different execution unit within an SM310. A thread group may include fewer threads than the number of execution units within the SM310, in which case some of the execution may be idle during cycles when that thread group is being processed. A thread group may also include more threads than the number of execution units within the SM310, in which case processing may occur over consecutive clock cycles. Since each SM310can support up to G thread groups concurrently, it follows that up to G*M thread groups can be executing in GPC208at any given time.

Additionally, a plurality of related thread groups may be active (in different phases of execution) at the same time within an SM310. This collection of thread groups is referred to herein as a “cooperative thread array” (“CTA”) or “thread array.” The size of a particular CTA is equal to m*k, where k is the number of concurrently executing threads in a thread group, which is typically an integer multiple of the number of execution units within the SM310, and m is the number of thread groups simultaneously active within the SM310.

Although not shown inFIG. 3A, each SM310contains a level one (L1) cache or uses space in a corresponding L1 cache outside of the SM310to support, among other things, load and store operations performed by the execution units. Each SM310also has access to level two (L2) caches (not shown) that are shared among all GPCs208in PPU202. The L2 caches may be used to transfer data between threads. Finally, SMs310also have access to off-chip “global” memory, which may include PP memory204and/or system memory104. It is to be understood that any memory external to PPU202may be used as global memory. Additionally, as shown inFIG. 3A, a level one-point-five (L1.5) cache335may be included within GPC208and configured to receive and hold data requested from memory via memory interface214by SM310. Such data may include, without limitation, instructions, uniform data, and constant data. In embodiments having multiple SMs310within GPC208, the SMs310may beneficially share common instructions and data cached in L1.5 cache335.

Each GPC208may have an associated memory management unit (MMU)320that is configured to map virtual addresses into physical addresses. In various embodiments, MMU320may reside either within GPC208or within the memory interface214. The MMU320includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile or memory page and optionally a cache line index. The MMU320may include address translation lookaside buffers (TLB) or caches that may reside within SMs310, within one or more L1 caches, or within GPC208.

In graphics and compute applications, GPC208may be configured such that each SM310is coupled to a texture unit315for performing texture mapping operations, such as determining texture sample positions, reading texture data, and filtering texture data.

In operation, each SM310transmits a processed task to work distribution crossbar330in order to provide the processed task to another GPC208for further processing or to store the processed task in an L2 cache (not shown), parallel processing memory204, or system memory104via crossbar unit210. In addition, a pre-raster operations (preROP) unit325is configured to receive data from SM310, direct data to one or more raster operations (ROP) units within partition units215, perform optimizations for color blending, organize pixel color data, and perform address translations.

It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Among other things, any number of processing units, such as SMs310, texture units315, or preROP units325, may be included within GPC208. Further, as described above in conjunction withFIG. 2, PPU202may include any number of GPCs208that are configured to be functionally similar to one another so that execution behavior does not depend on which GPC208receives a particular processing task. Further, each GPC208operates independently of the other GPCs208in PPU202to execute tasks for one or more application programs. In view of the foregoing, persons of ordinary skill in the art will appreciate that the architecture described inFIGS. 1-3Ain no way limits the scope of the present invention.

Graphics Pipeline Architecture

FIG. 3Bis a conceptual diagram of a graphics processing pipeline350that may be implemented within PPU202ofFIG. 2, according to one embodiment of the present invention. As shown, the graphics processing pipeline350includes, without limitation, a primitive distributor (PD)355; a vertex attribute fetch unit (VAF)360; a vertex, tessellation, geometry processing unit (VTG)365; a viewport scale, cull, and clip unit (VPC)370; a tiling unit375, a setup unit (setup)380, a rasterizer (raster)385; a fragment processing unit, also identified as a pixel shading unit (PS)390, and a raster operations unit (ROP)395.

The PD355collects vertex data associated with high-order surfaces, graphics primitives, and the like, from the front end212and transmits the vertex data to the VAF360.

The VAF360retrieves vertex attributes associated with each of the incoming vertices from shared memory and stores the vertex data, along with the associated vertex attributes, into shared memory.

The VTG365is a programmable execution unit that is configured to execute vertex shader programs, tessellation programs, and geometry programs. These programs process the vertex data and vertex attributes received from the VAF360, and produce graphics primitives, as well as color values, surface normal vectors, and transparency values at each vertex for the graphics primitives for further processing within the graphics processing pipeline350. Although not explicitly shown, the VTG365may include, in some embodiments, one or more of a vertex processing unit, a tessellation initialization processing unit, a task generation unit, a task distributor, a topology generation unit, a tessellation processing unit, and a geometry processing unit.

The vertex processing unit is a programmable execution unit that is configured to execute vertex shader programs, lighting and transforming vertex data as specified by the vertex shader programs. For example, the vertex processing unit may be programmed to transform the vertex data from an object-based coordinate representation (object space) to an alternatively based coordinate system such as world space or normalized device coordinates (NDC) space. The vertex processing unit may read vertex data and vertex attributes that is stored in shared memory by the VAF and may process the vertex data and vertex attributes. The vertex processing unit415stores processed vertices in shared memory.

The tessellation initialization processing unit is a programmable execution unit that is configured to execute tessellation initialization shader programs. The tessellation initialization processing unit processes vertices produced by the vertex processing unit and generates graphics primitives known as patches. The tessellation initialization processing unit also generates various patch attributes. The tessellation initialization processing unit then stores the patch data and patch attributes in shared memory. In some embodiments, the tessellation initialization shader program may be called a hull shader or a tessellation control shader.

The task generation unit retrieves data and attributes for vertices and patches from shared memory. The task generation unit generates tasks for processing the vertices and patches for processing by later stages in the graphics processing pipeline350.

The task distributor redistributes the tasks produced by the task generation unit. The tasks produced by the various instances of the vertex shader program and the tessellation initialization program may vary significantly between one graphics processing pipeline350and another. The task distributor redistributes these tasks such that each graphics processing pipeline350has approximately the same workload during later pipeline stages.

The topology generation unit retrieves tasks distributed by the task distributor. The topology generation unit indexes the vertices, including vertices associated with patches, and computes (U,V) coordinates for tessellation vertices and the indices that connect the tessellated vertices to form graphics primitives. The topology generation unit then stores the indexed vertices in shared memory.

The tessellation processing unit is a programmable execution unit that is configured to execute tessellation shader programs. The tessellation processing unit reads input data from and writes output data to shared memory. This output data in shared memory is passed to the next shader stage, the geometry processing unit445as input data. In some embodiments, the tessellation shader program may be called a domain shader or a tessellation evaluation shader.

The geometry processing unit is a programmable execution unit that is configured to execute geometry shader programs, thereby transforming graphics primitives. Vertices are grouped to construct graphics primitives for processing, where graphics primitives include triangles, line segments, points, and the like. For example, the geometry processing unit may be programmed to subdivide the graphics primitives into one or more new graphics primitives and calculate parameters, such as plane equation coefficients, that are used to rasterize the new graphics primitives.

The geometry processing unit transmits the parameters and vertices specifying new graphics primitives to the VPC370. The geometry processing unit may read data that is stored in shared memory for use in processing the geometry data. The VPC370performs clipping, culling, perspective correction, and viewport transform to determine which graphics primitives are potentially viewable in the final rendered image and which graphics primitives are not potentially viewable. The VPC370then transmits processed graphics primitives to the tiling unit375.

The tiling unit375is a graphics primitive sorting engine that resides between a world space pipeline352and a screen space pipeline354, as further described herein. Graphics primitives are processed in the world space pipeline352and then transmitted to the tiling unit375. The screen space is divided into cache tiles, where each cache tile is associated with a portion of the screen space. For each graphics primitive, the tiling unit375identifies the set of cache tiles that intersect with the graphics primitive, a process referred to herein as “tiling.” After tiling a certain number of graphics primitives, the tiling unit375processes the graphics primitives on a cache tile basis, where graphics primitives associated with a particular cache tile are transmitted to the setup unit380. The tiling unit375transmits graphics primitives to the setup unit380one cache tile at a time. Graphics primitives that intersect with multiple cache tiles are typically processed once in the world space pipeline352, but are then transmitted multiple times to the screen space pipeline354.

Such a technique improves cache memory locality during processing in the screen space pipeline354, where multiple memory operations associated with a first cache tile access a region of the L2 caches, or any other technically feasible cache memory, that may stay resident during screen space processing of the first cache tile. Once the graphics primitives associated with the first cache tile are processed by the screen space pipeline354, the portion of the L2 caches associated with the first cache tile may be flushed and the tiling unit may transmit graphics primitives associated with a second cache tile. Multiple memory operations associated with a second cache tile may then access the region of the L2 caches that may stay resident during screen space processing of the second cache tile. Accordingly, the overall memory traffic to the L2 caches and to the render targets may be reduced. In some embodiments, the world space computation is performed once for a given graphics primitive irrespective of the number of cache tiles in screen space that intersects with the graphics primitive.

The setup unit380receives vertex data from the VPC370via the tiling unit375and calculates parameters associated with the graphics primitives, including, without limitation, edge equations, partial plane equations, and depth plane equations. The setup unit380then transmits processed graphics primitives to rasterizer385.

The rasterizer385scan converts the new graphics primitives and transmits fragments and coverage data to the pixel shading unit390. Additionally, the rasterizer385may be configured to perform z culling and other z-based optimizations.

The pixel shading unit390is a programmable execution unit that is configured to execute fragment shader programs, transforming fragments received from the rasterizer385, as specified by the fragment shader programs. Fragment shader programs may shade fragments at pixel-level granularity, where such shader programs may be called pixel shader programs. Alternatively, fragment shader programs may shade fragments at sample-level granularity, where each pixel includes multiple samples, and each sample represents a portion of a pixel. Alternatively, fragment shader programs may shade fragments at any other technically feasible granularity, depending on the programmed sampling rate.

In various embodiments, the fragment processing unit460may be programmed to perform operations such as perspective correction, texture mapping, shading, blending, and the like, to produce shaded fragments that are transmitted to the ROP395. The pixel shading unit390may read data that is stored in shared memory.

The ROP395is a processing unit that performs raster operations, such as stencil, z test, blending, and the like, and transmits pixel data as processed graphics data for storage in graphics memory via the memory interface214, where graphics memory is typically structured as one or more render targets. The processed graphics data may be stored in graphics memory, parallel processing memory204, or system memory104for display on display device110or for further processing by CPU102or parallel processing subsystem112. In some embodiments, the ROP395is configured to compress z or color data that is written to memory and decompress z or color data that is read from memory. In various embodiments, the ROP395may be located in the memory interface214, in the GPCs208, in the processing cluster array230outside of the GPCs, or in a separate unit (not shown) within the PPUs202.

The graphics processing pipeline may be implemented by any one or more processing elements within PPU202. For example, one of the SMs310ofFIG. 3Acould be configured to perform the functions of one or more of the VTG365and the pixel shading unit390. The functions of the PD355, the VAF360, the VPC450, the tiling unit375, the setup unit380, the rasterizer385, and the ROP395may also be performed by processing elements within a particular GPC208in conjunction with a corresponding partition unit215. Alternatively, graphics processing pipeline350may be implemented using dedicated fixed-function processing elements for one or more of the functions listed above. In various embodiments, PPU202may be configured to implement one or more graphics processing pipelines350.

In some embodiments, the graphics processing pipeline350may be divided into a world space pipeline352and a screen space pipeline354. The world space pipeline352processes graphics objects in 3D space, where the position of each graphics object is known relative to other graphics objects and relative to a 3D coordinate system. The screen space pipeline354processes graphics objects that have been projected from the 3D coordinate system onto a 2D planar surface representing the surface of the display device110. For example, the world space pipeline352could include pipeline stages in the graphics processing pipeline350from the PD355through the VPC370. The screen space pipeline354could include pipeline stages in the graphics processing pipeline350from the setup unit380through the ROP395. The tiling unit375would follow the last stage of the world space pipeline352, namely, the VPC370. The tiling unit375would precede the first stage of the screen space pipeline354, namely, the setup unit380.

In some embodiments, the world space pipeline352may be further divided into an alpha phase pipeline and a beta phase pipeline. For example, the alpha phase pipeline could include pipeline stages in the graphics processing pipeline350from the PD355through the task generation unit. The beta phase pipeline could include pipeline stages in the graphics processing pipeline350from the topology generation unit through the VPC370. The graphics processing pipeline350performs a first set of operations during processing in the alpha phase pipeline and a second set of operations during processing in the beta phase pipeline. As used herein, a set of operations is defined as one or more instructions executed by a single thread, by a thread group, or by multiple thread groups acting in unison.

In a system with multiple graphics processing pipeline350, the vertex data and vertex attributes associated with a set of graphics objects may be divided so that each graphics processing pipeline350has approximately the same amount of workload through the alpha phase. Alpha phase processing may significantly expand the amount of vertex data and vertex attributes, such that the amount of vertex data and vertex attributes produced by the task generation unit is significantly larger than the amount of vertex data and vertex attributes processed by the PD355and VAF360. Further, the task generation unit associated with one graphics processing pipeline350may produce a significantly greater quantity of vertex data and vertex attributes than the task generation unit associated with another graphics processing pipeline350, even in cases where the two graphics processing pipelines350process the same quantity of attributes at the beginning of the alpha phase pipeline. In such cases, the task distributor redistributes the attributes produced by the alpha phase pipeline such that each graphics processing pipeline350has approximately the same workload at the beginning of the beta phase pipeline.

Please note, as used herein, references to shared memory may include any one or more technically feasible memories, including, without limitation, a local memory shared by one or more SMs310, or a memory accessible via the memory interface214, such as a cache memory, parallel processing memory204, or system memory104. Please also note, as used herein, references to cache memory may include any one or more technically feasible memories, including, without limitation, an L1 cache, an L1.5 cache, and the L2 caches.

Tiled Caching

FIG. 4is a conceptual diagram of a cache tile410(0) that the graphics processing pipeline350ofFIG. 3Bmay be configured to generate and process, according to one embodiment of the present invention. As shown, the cache tile410(0) represents a portion of a screen space400and is divided into multiple raster tiles420.

The screen space400represents one or more memory buffers configured to store rendered image data and other data transmitted by functional units within the graphics processing pipeline350. In some embodiments, the one or more memory buffers may be configured as one or more render targets. The screen space represents a memory buffer configured to store the image rendered by the graphics processing pipeline. The screen space400may be associated with any number of render targets, where each render target may be configured independently of other render targets to include any number of fields. Each field within a render target may be configured independently of other fields to include any number of bits. Each render target may include multiple picture elements (pixels), and each pixel may, in turn, include multiple samples. In some embodiments, the size of each cache tile may be based on the size and configuration of the render targets associated with the screen space. In operation, once rendering completes, the pixels in the one or more render targets may be transmitted to a display device in order to display the rendered image.

By way of example, a set of render targets for the screen space400could include eight render targets. The first render target could include four fields representing color, including red, green, and blue component colors, and transparency information associated with a corresponding fragment. The second render target could include two fields representing depth and stencil information associated with the corresponding fragment. The third render target could include three fields representing surface normal vector information, including an x-axis normal vector, a y-axis normal vector, and a z-axis normal vector, associated with the corresponding fragment. The remaining five render targets could be configured to store additional information associated with the corresponding fragment. Such configurations could include storage for various information, including, without limitation, 3D positional data, diffuse lighting information, and specular lighting information.

Each cache tile410represents a portion of the screen space400. For clarity, only five cache tiles410(0)-410(4) are shown inFIG. 4. In some embodiments, cache tiles may have an arbitrary size in X and Y screen space. For example, if a cache tile were to reside in a cache memory that also is used to store other data, then the cache tile could be sized to consume only a specific portion of the cache memory. The size of a cache tile may be based on a number of factors, including, the quantity and configuration of the render targets associated with the screen space400, the quantity of samples per pixel, and whether the data stored in the cache tile is compressed. As a general matter, a cache tile is sized to increase the likelihood that the cache tile data remains resident in the cache memory until all graphics primitives associated with the cache tile are fully processed.

The raster tiles420represent a portion of the cache tile410(0). As shown, the cache tile410(0) includes sixteen raster tiles420(0)-420(15) arranged in an array that is four raster tiles420wide and four raster tiles420high. In systems that include multiple GPCs208, processing associated with a given cache tile410(0) may be divided among the available GPCs208. In the example shown, if the sixteen raster tiles of cache tile410(0) were processed by four different GPCs208, then each GPC208could be assigned to process four of the sixteen raster tiles420in the cache tile410(0). Specifically, the first GPC208could be assigned to process raster tiles420(0),420(7),420(10), and420(13). The second GPC208could be assigned to process raster tiles420(1),420(4),420(11), and420(14). The third GPC208could be assigned to process raster tiles420(2),420(5),420(8), and420(15). The fourth GPC208would then be assigned to process raster tiles420(3),420(6),420(9), and420(12). In other embodiments, the processing of the different raster tiles within a given cache tile may be distributed among GPCs208or any other processing entities included within computer system100in any technically feasible manner.

FIG. 5illustrates a graphics subsystem configured to implement cache tiling, according to one embodiment of the present invention. As shown, the graphics subsystem500includes a front end unit212, a first world-space pipeline352(0), a second world-space pipeline352(1), a crossbar unit520(“XBAR”), a first tiling unit575(0), a second tiling unit575(1), a first screen-space pipeline354(0), and a second screen-space pipeline354(1).

The graphics subsystem500includes at least two instances of the screen-space pipeline354and the world-space pipeline352, for increased performance. The graphics subsystem500also includes a crossbar unit520for transmitting work output from the first world-space pipeline352(0) and the second world-space pipeline352(1) to the first tiling unit575(0) and the second tiling unit575(1). Although depicted inFIG. 5with two instances of the world-space pipeline352and the screen-space pipeline354, the teachings provided herein apply to graphics pipelines having any number of world-space pipelines352and screen-space pipelines354.

The functionality of the world-space pipelines352and the screen-space pipelines354are implemented by processing entities such as general processing clusters (GPC)208, described above. In one embodiment, the first world-space pipeline352(0) may be implemented in a first GPC208(0) and the second world-space pipeline352(1) may be implemented in a second GPC208(1). As a general matter, each screen-space pipeline354may be implemented in a different GPC208, and in a similar fashion, each world-space pipeline352may be implemented in a different GPC208. Further, a given GPC208can implement a world-space pipeline352and also a screen-space pipeline354. For example, the first GPC208(0) may implement both the first world-space pipeline352(0) and the first screen-space pipeline354(0). In embodiments that include more than one screen-space pipeline354, each screen-space pipeline354is associated with a different set of raster tiles420for any particular render target.

Each of the pipeline units in the world-space pipelines352(i.e., primitive distributor355, vertex attribute fetch unit360, vertex, tessellation, geometry processing unit365, and viewport scale, cull, and clip unit370) and in the screen-space pipelines354(i.e., setup380, rasterizer385, pixel shader390, and ROP395) depicted inFIG. 5functions in a similar manner as described above with respect toFIGS. 1-4.

A device driver103transmits instructions to the front end unit212. The instructions include primitives and commands to bind render targets, arranged in application-programming-interface order (API order). API order is the order in which the device driver103specifies that the commands should be executed and is typically specified by an application executing on CPU102. For example, an application may specify that a first primitive is to be drawn and then that a second primitive is to be drawn.

When the front end unit212receives the instructions from the device driver103, the front end unit212distributes tasks associated with the instructions to the world-space pipelines352for processing. In one embodiment, the front end unit212assigns tasks to the first world-space pipeline352(0) and the second world-space pipeline352(1) in round-robin order. For example, the front end unit212may transmit tasks for a first batch of primitives associated with the instructions to the first world-space pipeline352(0) and tasks for a second batch of primitives associated with the instructions to the second world-space pipeline352(1).

The first world-space pipeline352(0) and second world-space pipeline352(1) each process tasks associated with the instructions, and generate primitives for processing by the first screen-space pipeline354(0) and the second screen-space pipeline354(1). The first world-space pipeline352(0) and second world-space pipeline352(1) each include a bounding box generator unit (not shown) that determines to which screen space pipeline—the first screen-space pipeline354(0) or the second screen-space pipeline354(1)—each primitive should be transmitted. To make this determination, the bounding box generator unit generates bounding boxes for each primitive, and compares the bounding boxes to raster tiles420. If a bounding box associated with a primitive overlaps one or more raster tiles associated with a particular screen-space pipeline354, then the bounding box generator unit determines that the primitive is to be transmitted to that screen-space pipeline354. A primitive may be transmitted to multiple screen-space pipelines354if the primitive overlaps raster tiles420associated with more than one screen-space pipeline354. After the world-space pipelines352generate the primitives, the world-space pipelines352transmit the primitives to the crossbar unit530, which transmits the primitives to the corresponding tiling units375as specified by the bounding box generator unit.

The tiling units575receive primitives from the crossbar unit520. Each tiling unit575accepts and stores these primitives until the tiling unit575decides to perform a flush operation. Each tiling unit575decides to perform a flush operation when one or more resource counters maintained by the tiling units575indicates that a resource has exceeded a threshold.

Upon receiving primitives, a tiling unit575updates several resource counters associated with the primitives. The resource counters are configured to track the degree of utilization of various resources associated with the primitives received by the tiling units575. Resources are either global resources or local resources. Global resources are pools of resources that are shared by all screen-space pipelines354and world-space pipelines352. Local resources are resources that not shared between screen-space pipelines354or between world-space pipelines352. Several examples of local and global resources are now provided.

One type of local resource is a primitive storage space for storing primitives in a tiling unit575. Each tiling unit575includes a primitive storage space that is maintained independently of primitive storage space for other tiling units575. When a tiling unit575receives a primitive, some of the primitive storage space is occupied by the primitive. Because only a limited amount of primitive storage space exists for each tiling unit575, exceeding a threshold amount of storage space in a particular tiling unit575causes the tiling unit575to perform a flush operation.

One type of global resource is a vertex attribute circular buffer. The vertex attribute circular buffer includes circular buffer entries that include vertex attributes. The vertex attribute circular buffer is available to units in the graphics subsystem500for reading vertex attributes associated with primitives. Each circular buffer entry in the vertex attribute circular buffer occupies a variable amount of storage space. Each tiling unit575maintains a count of the amount of space occupied by circular buffer entries associated with primitives in the tiling unit575.

In one embodiment, the vertex attribute circular buffer may be structured as a collection of smaller per-world-space-pipeline circular buffers. Each per-world-space pipeline circular buffer is associated with a different world-space pipeline352. If memory space associated with any of the per-world-space-pipeline circular buffers exceed a threshold value, then the associated tiling unit performs a flush operation.

Another type of global resource is a pool of constant buffer table indices. At the application-programming-interface level, an application programmer is permitted to associate constants with shader programs. Different shader programs may be associated with different constants. Each constant is a value that may be accessed while performing computations associated with the shader programs. The pool of constant buffer table indices is a global resource by which constants are associated with shader programs.

When a tiling unit575performs a flush operation, the tiling unit575iterates through all of the cache tiles410, and for each cache tile410, generates a cache tile batch that includes primitives that overlap the cache tile410, and transmits the cache tile batches to the associated screen-space pipeline354. Each tiling unit575is associated with a different screen-space pipeline354. Thus, each tiling unit575transmits cache tile batches to the associated screen-space pipeline354.

The tiling unit575transmits these cache tile batches to the screen-space pipeline354associated with the tiling unit as the cache tile batches are generated. The tiling unit575continues to generate and transmit cache tile batches in this manner for all cache tiles410associated with a render target. In one embodiment, the tiling unit575determines which primitives overlap a cache tile410by comparing a border of the cache tile410with bounding boxes associated with the primitives and received from the bounding box unit.

The cache tile batches flow through the screen-space pipelines354in the order in which the tiling unit575generates the cache tile batches. This ordering causes the units in the screen-space pipelines354to process the primitives in cache tile order. In other words, the screen-space pipelines354process primitives that overlap a first cache tile, and then process primitives that overlap a second cache tile, and so on.

Conceptually, each cache tile batch can be thought of as beginning at the point in time at which the tiling unit575began accepting primitives after the previous flush operation. In other words, even though the cache tile batches are transmitted to and processed by the screen-space pipelines354sequentially, each cache tile batch logically begins at the same point in time. Of course, because the cache tiles generally do not overlap in screen space, sequential processing in this manner generally produces the desired results.

Scheduling Cache Traffic in a Tiling Architecture

In operation, when the tiling unit575transmits cache tile batches to a screen-space pipeline354, the screen-space pipeline354processes the triangles in the cache tile batches and writes pixel data, such as color data, to memory locations, specified for the particular data. These memory locations typically specify particular locations in an external memory unit, such as PP memory204. A caching hierarchy including an L2 cache (as described above with respect to, e.g.,FIG. 3A) acts as an intermediate store for the data, and serves to provide quicker access to most recently accessed and/or most commonly accessed data. Because the L2 cache does not have the capacity to store all data that is stored in the external memory unit, the L2 cache is configured to exchange some data resident in the L2 cache for data that is not resident in the L2 cache. In other words, the L2 cache must write data out to the external memory unit and also read data in from the external memory unit from time to time. The L2 cache manages writing data out to the external memory unit, and requesting data from the external memory unit according to a set of caching policies.

The data transmitted by the screen-space pipeline354specifies a particular memory location. When the L2 cache receives a request to access (i.e., read or write) a particular memory location from the screen-space pipeline354, the L2 cache determines whether the L2 cache stores a cache line corresponding to the memory location. If the L2 cache does store such a cache line, then the memory access is deemed a “hit,” and the L2 cache accesses the data at that cache line, and provides that data back to the screen-space pipeline354. If the L2 cache does not store such a cache line, then the memory access is deemed a “miss,” and the L2 cache fetches the corresponding data from an external memory unit, such as PP memory204. Requesting data from an external memory unit in this manner is typically associated with a large amount of latency. Once the data has been fetched from the external memory unit, the L2 cache stores the data in a corresponding cache line and returns the data to the screen-space pipeline354.

From time to time, “dirty data” stored in the L2 cache is written back to the external memory unit. Data is dirty if the data has been altered since being read from the external memory unit to the L2 cache. The data is written back to the external memory unit according to a set of cache eviction policies. The L2 cache keeps track of dirty data by maintaining a dirty bit for each of the cache lines. A value of “0” means that the cache line is not dirty, and a value of “1” means that the cache line is dirty.

Because of the large amount of latency typically associated with fetching data from the external memory unit and writing data out to the external memory unit, oftentimes, during processing, there may be periods of latency. These periods of latency are generally caused by the fact that the screen-space pipeline354can process data much more quickly than the latency associated with reading data from or writing data out to an external memory unit from the L2 cache.

FIG. 6is a conceptual illustration of a composite graph600depicting memory traffic, according to one embodiment of the present invention. As shown, the composite graph600includes a pipeline graph602and an L2 cache graph620. The pipeline graph602depicts requests transmitted by the screen-space pipeline354for data. These requests include read and/or write requests to specified memory locations. The L2 cache graph620depicts traffic between L2 and an external memory unit, such as PP memory204. This traffic includes L2 requests from the external memory unit due to cache misses, as well as dirty data write-outs from the L2 cache caused by cache eviction.

The horizontal axis for both the pipeline graph602and the L2 cache graph620is of course time, which advances from left to right. The pipeline graph602and the L2 cache graph620are generally aligned in time, meaning that two events that occur in the same horizontal position in the pipeline graph602and the L2 cache graph620occur at approximately same time. The composite graph600depicts a sequence of events at some intermediate time in the operation of the tiling unit575. In other words, prior to the events depicted inFIG. 6, the tiling unit575has processed other cache tile batches, and after the events depicted inFIG. 6, the tiling unit575processes additional cache tile batches.

The pipeline graph602illustrates processing periods604, in which the screen-space pipeline354is processing data, and thus generating memory access requests, and idle periods606, in which the screen-space pipeline354is not processing data, and thus not generating memory access requests. The processing periods604generally occur when the L2 cache stores the cache lines needed for the cache tile associated with a particular processing period604. The idle periods606generally occur when the L2 cache does not store some of the data requested by the screen-space pipeline354. Because some of the requested data are not stored in the L2 cache, the L2 cache must request the data from an external memory unit. Because requesting data from the external memory unit incurs a large amount of latency, the screen-space pipeline354is relatively idle, meaning that the screen-space pipeline354stalls while waiting for the data to be read in from the external memory unit. To put it another way, the screen-space pipeline354can process data more quickly than the latency associated with a cache miss. Therefore, when a cache miss occurs, a large amount of time is consumed fetching the data associated with the cache miss.

During the processing periods604, the screen-space pipeline354typically writes to many different memory locations. Thus, at some point during the processing of a cache tile, many cache lines have dirty bits that are set to “1.” The L2 cache is configured to begin evicting data when a number of dirty lines exceeds a certain threshold, or for other reasons. In typical operation, processing a cache tile may cause this threshold to be exceeded and the L2 cache to begin evicting cache lines associated with the cache tile. This eviction is reflected in eviction periods621. Eviction periods621, in the L2 cache graph620, indicate traffic between the L2 cache and an external memory unit associated with the eviction.

Additionally, after a processing period604has completed for a particular cache tile, a new cache tile begins, because the work associated with the new cache tile is “next” in the screen-space pipeline. In other words, the primitives associated with the next cache tile are subsequent to the primitives associated with the current cache tile, and thus flow through the screen-space pipeline354following the primitives associated with the current cache tile. Work associated with this new cache tile requests access to data at particular memory locations. At this point in time, cache lines associated with these particular memory locations are not resident in the L2 cache, because the cache tile has not been processed recently, and thus the cache lines for the cache tile had been evicted at some earlier time. The L2 cache thus requests that those cache lines be read in from the external memory unit. Because the data associated with the current cache tile has not yet been read into the L2 cache, processing in the screen-space pipeline354stalls. In other words, because no data associated with the current cache tile is resident in the L2 cache, the memory accesses requested by the screen-space pipeline354must wait until the requested cache lines are written to the L2 cache. Therefore, the screen-space pipeline354experiences an idle period606while waiting for the next fetch period622to bring in the requested cache lines from the external memory unit.

Because the eviction associated with a particular cache tile typically happens towards the end of processing of that cache tile, the eviction generally coincides in time with fetch requests caused by processing the next cache tile. Thus, during eviction periods621, the L2 cache consumes bandwidth to the external memory unit at a similar time that such bandwidth is consumed during cache fetch periods622. Because the cache evict periods621may overlap with the cache fetch periods622, a maximum bandwidth for data transfer between the L2 cache and the external memory unit may be reached, which means that data required for the next cache tile is not transmitted to the L2 cache quickly enough for the screen-space pipeline354to be able to proceed without interruption. In other words, the screen-space pipeline354accesses data more quickly than that data is fetched into the L2 cache. Therefore, the screen-space pipeline354experiences some interruptions during idle periods606, which are caused by the requested data not being resident in the L2 cache, due to the latency between the L2 cache and the external memory unit.

As the foregoing demonstrates, the screen-space pipeline354typically experiences processing periods604followed by idle periods606. For example, a first processing period604(0), associated with a first cache tile occurs, and then an idle period606(0) occurs. Similarly, a second processing period604(1), followed by a second idle period606(1), and a third processing period604(2), followed by a third idle period606(3) occur. Also during the first cache tile, a first fetch period622(0) occurs during the first processing period604(0), followed by no-traffic period624(0), and then a first eviction period621(1). Similarly, during a second cache tile, a second fetch period622(1), a second no-traffic period624(1), and a second eviction period621(2) occur. Finally, during a third cache tile, a third fetch period622(2), a third no-traffic period624(2), and a third eviction period626(2) occur. A portion of a fourth cache tile is shown, represented by idle period606(2), and by eviction period621(3) and fetch period622(3). Each of the idle periods606represents a period during which the screen-space pipeline354must suspend some processing, and thus represents a reduction in processing efficiency. Improved efficiency may be obtained by reducing periods of latency caused by traffic between the L2 cache and the external memory unit. Techniques for reducing delay in the screen-space pipeline354associated with latency are described below with respect toFIGS. 7-9.

FIG. 7is a conceptual depiction of the tiling unit575configured to schedule memory traffic to manage latency, according to one embodiment of the present invention. As shown, the tiling unit575generates commands701and transmits the commands701to the screen-space pipeline354.

To generate the commands701, the tiling unit575receives primitives from the crossbar unit530and generates cache tile batches as described above with respect toFIG. 5. In typical operation, the tiling unit575includes a scissor rectangle702before each cache tile batch706to inform the screen-space pipeline354to process work only for the portion of a render target identified by the scissor rectangle702. For each cache tile batch706, the scissor rectangle702specifies the portion of the render target that is associated with the cache tile for the cache tile batch706.

In addition to the cache tile batches706and associated scissor rectangles702, the tiling unit575is also configured to transmit prefetch commands704and cache flush commands708. The prefetch commands704are configured to cause the L2 cache to fetch data from an external memory unit and store that data in cache lines in the L2 cache. The flush commands708are configured to cause the L2 cache to evict specified dirty cache lines. In some embodiments, the tiling unit575is configured to transmit only flush commands and not prefetch commands, or only prefetch commands and not flush commands.

In order to reduce latency associated with fetching data from the external memory unit for each cache tile, the tiling unit575transmits the prefetch commands704and flush commands708to the screen-space pipeline354in a certain order. More specifically, the tiling unit575transmits a prefetch command for a subsequent cache tile prior to transmitting the cache tile batch706for a current cache tile. Additionally, after transmitting the cache tile batch706for the current cache tile, the tiling unit575transmits a flush command708for the current cache tile.

The prefetch commands704and flush commands708flow through the screen-space pipeline354in the order specified by the tiling unit575(i.e., in the order transmitted by the tiling unit575to the screen-space pipeline354). When the prefetch command704arrives at ROP395, ROP395transmits a command to the L2 cache to cause the L2 cache to read specified data from an external memory unit. The external memory unit transmits the specified data to the L2 cache and the L2 cache stores that data. When the flush command arrives at ROP395, ROP395transmits a command to the L2 cache to cause the L2 cache to evict specified data. The L2 cache transmits dirty data to the external memory unit and may choose to invalidate cache lines with no dirty data, so that such data is not written to the external memory unit.

The commands701from tiling unit575include commands in the following order, where references to “first,” “second,” and “third” cache tiles refer to the order in which cache tile batches associated with those cache tiles are transmitted to the screen-space pipeline354. The tiling unit575transmits a first scissor rectangle702(0) for a second cache tile (“cache tile 1”) to the screen-space pipeline, followed by a prefetch command704(0) for cache tile 1. Subsequently, the tiling unit575transmits a scissor rectangle702(1) for a first cache tile (“cache tile 0”), followed by a cache tile batch706(0) for cache tile 0 and then a flush command708(0) for cache tile 0. The tiling unit575next transmits a scissor rectangle702(2) for a third cache tile (“cache tile 2”), followed by a prefetch command704(2) for cache tile 2. Then, the tiling unit575transmits a scissor rectangle702(3) for cache tile 1, followed by the cache tile batch706(1) for cache tile 1 and then a flush command708(1) for cache tile 1.

In some embodiments, the prefetch commands704and flush commands708may specify a subset of a cache tile to prefetch or flush. More specifically, both the prefetch commands704and the flush commands708can specify the subset of a cache tile that is actually affected by primitives in a particular cache tile batch706. If primitives in a cache tile batch706do not affect a certain portion of a cache tile, then the data associated with those portions do not need to be read into the L2 cache.

For the flush commands708, the tiling unit575has already searched through the primitives stored in the tiling unit575and determined which primitives overlap the current cache tile. Therefore, the tiling unit575may use this information to limit the flush command708to the area encompassed by those primitives.

For the prefetch command704, in some embodiments, the tiling unit575first searches through all the primitives stored in the tiling unit575to determine which primitives overlap the cache tile associated with the prefetch command704(which is a cache tile subsequent to the current cache tile). Then, the tiling unit575determines, based on those primitives, what portion of the cache tile to prefetch. Because searching through all of the primitives in this manner may consume a considerable amount of time, in other embodiments, the prefetch command704may simply prefetch data associated with the entire cache tile.

FIG. 8is a conceptual illustration of a composite graph800depicting memory traffic, according to one embodiment of the present invention. As shown, the composite graph800includes a pipeline graph802and an L2 cache graph820. The pipeline graph802depicts requests transmitted by the screen-space pipeline354for data. These requests include read and/or write requests to specified memory locations. The L2 cache graph820depicts traffic between L2 and an external memory unit, such as PP memory204. This traffic includes L2 requests from the external memory unit due to cache misses, as well as dirty data write-outs from the L2 cache caused by cache eviction.

The horizontal axis for both the pipeline graph802and the L2 cache graph820is of course time, which advances from left to right. The pipeline graph802and the L2 cache graph820are generally aligned in time, meaning that two events that occur in the same horizontal position in the pipeline graph802and the L2 cache graph820occur at approximately same time.

The pipeline graph802and L2 cache graph820depict a sequence of events at some intermediate time in the operation of the tiling unit575. In other words, prior to the events depicted inFIG. 8, the tiling unit575has processed other cache tile batches, and after the events depicted inFIG. 8, the tiling unit575processes additional cache tile batches. The first event in pipeline graph802is a flush command for a previous tile (marked as “tile −1”). Thus, the L2 cache starts transmitting data associated with tile −1 to an external memory unit, as indicated by flush traffic822(0) for cache tile −1. The second event in pipeline graph802is a prefetch command806(0) for tile 1, which causes the L2 cache to request data associated with cache tile 1 to be read from the external memory unit into the L2 cache, as reflected in prefetch traffic824(0). Prefetch traffic824(0) and flush traffic822(0) may occur in approximately the same period, and may saturate the L2 cache-to-external memory unit bandwidth. However, because the prefetch operation806(0) is performed significantly prior to processing the cache tile batch associated with that prefetch operation806(0) (that is, cache tile 1), the data associated with cache tile 1 is resident in the L2 cache when the cache tile batch for cache tile 1 is processed.

After the data associated with cache tile −1 has been written out to the external memory unit and the data for cache tile 1 has been read in to the L2 cache, an idle period826(0) occurs. In this idle period826(0), substantially no traffic is flowing between the external memory unit and the L2 cache. The idle period826(0) lasts until the screen-space pipeline354finishes processing cache tile 0, at which point the screen-space pipeline354processes the flush tile 0 command804(1) and the prefetch tile 2806(1) command. In response to the flush tile 0 command804(1) and the prefetch tile 2 command806(2), the L2 cache starts evicting data associated with cache 0 to the external memory unit and starts reading in data for cache tile 2. Again, an idle period826(1) comes after the flush traffic822(1) associated with cache tile 0 and the prefetch traffic824(1) associated with cache tile 2. The screen-space pipeline354then starts processing data for cache tile 1, which is already in the cache because the data was prefetched by prefetch command824(0).

After the screen-space pipeline354has finished processing data for cache tile 1, the screen-space pipeline354transmits a flush tile 1 command804(2) and a prefetch tile 3 command806(2) to the L2 cache. In response, the L2 cache begins to flush data associated with cache tile 1 and to fetch data associated with cache tile 3. After transmitting the prefetch command806(2), the tiling unit575causes tile 2 to be processed by transmitting the third cache tile batch808(2). Once again, after the flush traffic822(2) and the prefetch traffic824(2) complete, there is an idle period826(2).

The flush commands804and prefetch commands806cause data stored in the L2 cache to be prefetched and evicted in an orderly manner. This orderly prefetching and eviction allows data associated with any particular cache tile to be resident in the L2 cache prior to beginning processing the cache tile, which helps to reduce the amount of latency associated with the cache tile. The orderly eviction allows data associated with a particular cache tile to be written out to an external memory unit early, which means that bandwidth is freed up for later traffic.

FIG. 9is a flow diagram of method steps for scheduling cache traffic in a tile-based architecture, according to one embodiment of the present invention. Although the method steps are described in conjunction with the systems ofFIGS. 1-8, persons skilled in the art will understand that any system configured to perform the method steps, in any order, falls within the scope of the present invention.

As shown, a method900begins in step902, where the tiling unit575receives a set of primitives. In step904, the tiling unit575designates a cache tile as a current cache tile. In step906, the tiling unit575determines which primitives overlap the current cache tile. In step908, the tiling unit575designates the cache tile after the current cache tile as the subsequent cache tile. In step910, the tiling unit575issues a command to prefetch data associated with the subsequent cache tile to the screen-space pipeline354. The command to prefetch data associated with the subsequent cache tile travels down the screen-space pipeline354until the prefetch command arrives at ROP395, which transmits the prefetch command to the L2 cache to fetch data from the external memory unit.

In step912, the tiling unit575issues the primitives that overlap the current cache tile to the screen-space pipeline354for processing. In step914, the tiling unit575issues a command to flush data associated with the current cache tile from the L2 cache. The flush command travels down the pipeline until the flush command arrives at ROP395, which transmits the flush command to the L2 cache. The L2 cache flushes the data specified by the L2 command to the external memory unit. In step916, the tiling unit575determines if there are more cache tiles to process. If there are more cache tiles to process, then the method proceeds to step920, in which the tiling unit575designates the subsequent cache tile as the current cache tile. If there are not more cache tiles to process, then the method proceeds to step918, in which the tiling unit575waits to perform another flush operation.

In sum, a tiling unit receives primitives and generates cache tile batches. The tiling unit inserts prefetch commands and flush commands in between each cache tile batch to inform the L2 cache to prefetch and flush data associated with the cache tile batches. More specifically, before a first cache tile, the tiling unit inserts a prefetch command to prefetch the cache tile after the first cache tile. Also, after a particular cache tile batch, the tiling unit inserts a flush command to cause the L2 cache to flush data associated with that cache tile batch. In some embodiments, the prefetch commands and flush commands are configured to cause the L2 cache to prefetch and flush only a subset of the corresponding cache tiles that corresponds to the primitives in the corresponding cache tile batch.

One advantage of the disclosed approach is that by prefetching data early, the data is available in the L2 cache before the cache tile that corresponds to that data. Therefore, the amount of latency associated with cache misses is reduced. Another advantage is that by flushing data associated with a cache tile early, idle bandwidth is consumed to flush the data. If the data were not flushed early, then the data might be caused to be flushed at a later time, during which the bandwidth might be needed for other operations. Thus, instantaneous memory bandwidth consumption associated with writing data into the cache and out of the cache for each cache tile is reduced (overall bandwidth remains the same). Another advantage is that by restricting either or both of the prefetch and flush commands to only the data associated with primitives in a particular cache tile batch, memory bandwidth consumption is further reduced.

The invention has been described above with reference to specific embodiments. Persons of ordinary skill in the art, however, will understand that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The foregoing description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Therefore, the scope of embodiments of the present invention is set forth in the claims that follow.