Capacitor-based digital-to-analog converter for low voltage applications

A digital-to-analog converter (DAC) compatible with CMOS technology and operable in low voltage applications. An input capacitor stores a charge sample according to a digital input signal and a previous output analog signal. An analog output circuit has a feedback capacitor to share the charge sample and accordingly generate a current output analog signal from an output node. The output node may be continually connected to the input capacitor through a pass resistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to capacitor-based digital-to-analog converters (DAC), and in particular to a DAC operable at a low supply voltage.

2. Description of the Related Art

Current hi-fi audio applications generally record audio data in a digital form such that playback requires digital-to-analog conversion. During playback, over-sampling DACs have become popular due to low cost, high performance and high yield. Direct-charge transfer is one of the most general methods of implementing over-sampling DACs because of insensitivity to clock jitter and low slew rate requirement.

FIG. 1shows a conventional direct-charge transfer (DCT) DAC10. DCT DAC10is a kind of switched-capacitor circuit. As shown in FIG. 17 several switches S0-S4cooperate with capacitors C1and C2, and an operational amplifier (OP), where the switches control interaction between all other elements therein. In order to integrate with other circuits in a chip, DCT DAC10is usually implemented by way of CMOS fabrication technology, where a PMOS transistor, a NMOS transistor and a pass gate (the combination of one PMOS and one NMOS) are common candidates for implementing a switch. MOS switches, however, experience difficulty conducting signals at levels near half of the supply voltage especially when the supply voltage is low. Therefore, it is not easy to design a DCT DAC with a low supply voltage.

BRIEF SUMMARY OF THE INVENTION

Embodiments of the invention provide a digital-to-analog converter (DAC). The DAC comprises an input capacitor and an analog output circuit. The input capacitor stores a charge sample according to a digital input signal and a previous output analog signal. The analog output circuit has a feedback capacitor to share the charge sample and accordingly generates a current output analog signal from an output node.

Embodiments of the invention further provide a method for digital-to-analog conversion. A charge sample according to a digital input signal and a previous output voltage level is stored in an input capacitor. The charge sample is then shared by a feedback capacitor to accordingly generate a current output voltage level.

Embodiments of the invention further provide a device capable of operating during first and second phases. The device comprises an input capacitor, an analog output circuit, and a pass resistor. The input capacitor has first and second terminals. The analog output circuit comprises a feedback capacitor and an operational amplifier. The feedback capacitor is connected between the output node and the inverted terminal of the operational amplifier, and the non-inverted terminal of the operational amplifier is connected to a reference voltage. The pass resistor is connected between the first terminal of the input capacitor and the output node of the operational amplifier. During the first phase, the first terminal of the input capacitor is connected to one of two voltage sources according to a digital input signal, and the second terminal of the input capacitor is connected to the reference voltage. During the second phase, the first terminal of the input capacitor is disconnected from the two voltage sources, and the second terminal of the input capacitor is disconnected from the reference voltage and connected to the inverted terminal.

DETAILED DESCRIPTION OF THE INVENTION

The operation of DCT DAC10inFIG. 1is first detailed in order to have a better comprehension of the current invention.

Generally, each switch inFIG. 1, except switches S0and S1, receives either an inverted or a non-inverted clock signal and is controlled by a clock. Some of the clock-controlled switches inFIG. 1are short while others are open, and vice versa. Thus, there are two operating phases for DCT DAC1, alternatively occurring, a sampling phase when the non-inverted clock signal is at a logic low level, for example, and an integration phase when the non-inverted clock signal is at a logic high level.FIGS. 2aand2bshow DCT DAC10ofFIG. 1during sampling and integration phases, respectively.

InFIG. 2a, even though switches S0and S1are omitted, either switch S0or S1is short to provide to the positive terminal of capacitor C2an input voltage Vin(t) according to the current digital signal that is going to be converted during the current sampling phase. For example, if the current digital signal is logic “1”, switch S0is short and S1is open, such that Vin(t) equals the high voltage level Vdd of power VDD. Conversely, if the current digital signal is logic “0”, switch S0is open and S1is short, such that Vin(t) equals the low voltage level ground of power GND. Switch S3, omitted, is short during the sampling phase to fix the negative terminal of capacitor C2at a reference voltage Vref. Therefore, during the sampling phase, input capacitor C2stores a charge sample, Q20, proportional to the voltage difference between Vin(t) and Vref, as shown in formula (1):
Q20=C20*(Vin(t)−Vref),  (1)

where C20is the capacitance of capacitor C2.

Concurrently, as shown inFIG. 2a, switches S2and S4are open, and the inverted and non-inverted input terminals of OP, isolated from input voltage Vin(t), remain in this condition before changing to the current sampling phase. Hereinafter, the output voltage of OP is defined as Vo(t−1) during the most recent integration phase and Vo(t) during the next subsequent integration phase. Since both input terminals of OP remain in the same condition as during the most recent integration phase, the output voltage of OP remains at Vo(t−1) during the current sampling phase. The inverted input terminal of OP is virtually kept at reference voltage Vref, and Q10, the charge at the positive terminal of capacitor C1during this sampling phase, can be shown in formula (2):
Q10=C10*(Vo(t−1)−Vref),  (2)

where C10is the capacitance of capacitor C2.

During the integration phase inFIG. 2b, both switches S0and S1are open regardless of the current digital signal. Switches S4and S2are omitted fromFIG. 2bbecause they are short while switch S3is open. Since the negative terminals of capacitors C1and C2are connected only to each other, capacitors C1and C2are connected in parallel and share the total charge on capacitors C1and C2. The charge on capacitors C1and C2is redistributed until capacitors C1and C2have equal voltage drop Vc, as shown in formula (3):
Vc=(Q10+Q20)/(C10+C20).  (3)

Capacitor C2and operational amplifier OP together act as an analog output circuit100, outputting an analog voltage signal having a voltage level of Vo(t) at the end of integration phase. Capacitor C2is a feedback capacitor, sharing the charge sample in capacitor C1and providing a feedback path to virtually maintain the inverted input terminal of OP at reference voltage Vref. Vo(t), the output voltage level for this integration phase, therefore equals the summation of reference voltage Vrefand the voltage drop Vcacross capacitor C2, as shown in formula (4):
Vo(t)=Vc+Vref.  (4)

A combination of formulas (1)-(4), Vo(t) is summarily shown in formula (5):
Vo(t)=(C10/(C10+C20))*Vo(t−1)+(C20/(C10+C20))*Vin(t).  (5)

Therefore, DCT DAC10, acting as a low pass filter as shown in formula (5), can convert a digital signal to analog signal Vo(t).

As previously mentioned, switches S0-S4are MOS switches if DCT DAC10is implemented by CMOS process technology, and MOS switches cannot conduct signal well if a supply voltage is very low.

FIGS. 3aand3bare two illustrations regarding to NMOS and PMOS switches, respectively, each on the left showing a turned-on MOS switch connected to a loading capacitor and on the right showing scale indicating the voltage range at which voltage Vpat one end of the turned-on MOS can fully pass the turned-on MOS to the loading capacitor at the other end of the turned-on MOS. As shown inFIG. 3a, a NMOS switch is turned on when its gate is supplied with supply voltage level Vdd. The shaded area of the scale on the right ofFIG. 3aindicates that only if Vpis less than (Vdd−Vtn), it can pass the NMOS switch, wherein Vtnis the threshold voltage of the NMOS switch. The unshaded area of the scale, having a voltage range of Vtnunder Vdd, is a forbidden range where a NMOS switch cannot act as a switch. Similarly, the scale on the right ofFIG. 3bhas an unshaded area, having a voltage range of Vtpabove ground and showing a forbidden range where a PMOS switch cannot act as a switch.

FIG. 4illustrates the difficulty for MOS switches to be switches when the supply voltage decreases. Even though each of NMOS and PMOS switches has a forbidden range, the combination of NMOS and PMOS switches may provide a continuous full range from ground to supply voltage Vdd to pass signal voltage Vp. As shown on the left ofFIG. 4, at least one of a PMOS and NMOS switches acts as a switch to pass signal voltage Vpeven if signal voltage Vpfalls into one the two forbidden ranges. Supply voltage decreases as semiconductor technology advances. The right ofFIG. 4indicates a dead zone D, where neither the PMOS nor NMOS switch can pass signal voltage Vp. As supply voltage decreases, threshold voltages of NMOS and PMOS switches decrease correspondingly but generally at a rate less than that for the supply voltage. Thus, if the supply voltage decreases to a certain level, as shown on the right ofFIG. 4, the two forbidden ranges for PMOS and NMOS switches inevitably overlap such that a dead zone D, where signal voltage Vpcannot pass NMOS and PMOS switches, appears. In other words, a MOS switch, regardless that it is a NMOS switch, a PMOS switch, or a combination thereof, cannot be employed to pass a signal voltage if the signal voltage has a possibility to fall into the dead zone D.

As the operation of DCT DAC10inFIG. 1shows, each switch S0and S1can be implemented by either PMOS or NMOS switch since both are designed to pass a signal voltage with a fixed voltage level of either Vdd or ground. Switches S2-S3, if reference voltage Vrefis optionally designed to be Vdd or ground, can also be implemented by either PMOS or NMOS switches. Switch S4is unique, however, dedicated to conducting charge back and forth between the positive terminals of capacitors C1and C2during integration phase when the positive terminal of capacitor C1, equivalent to the output terminal of DCT DAC10, has a voltage level possibly ranging from ground to Vdd. As a result, if the supply voltage for DCT DAC10is very low, switch S4cannot be implemented by any MOS switch, or, otherwise, switch S4does not pass to capacitor C2the signal voltage at the output terminal of DCT DAC10when the signal voltage is within a dead zone. In other words, DCT DAC10ofFIG. 1cannot be implemented by way of convenient and commonly-adopted CMOS process technology.

FIG. 5shows a DCT DAC20according to embodiments of the invention. DCT DA20inFIG. 5is substantially the same as DCT DAC10inFIG. 13except switch S4inFIG. 1is replaced by a pass resistor RpinFIG. 5. For illustration only, the same symbols are used inFIGS. 1 and 5for corresponding elements. If implemented by conventional CMOS process technology, pass resistor Rpcan be a poly resistor, a well resistor, a diffusion resistor, or the like. Unlike DCT DAC10inFIG. 1, DCT DAC20inFIG. 5is compatible with CMOS process technology.

Operation of DCT DAC20inFIG. 5is explained as follows to demonstrate replacement of switch S4by pass resistor Rpresulting in a functional DAC.

Switches S0-S3inFIG. 5are under control of a clock signal as that previously described for switches S0-S3inFIG. 1. There are, therefore, sampling and integration phases for DCT DAC5, alternatively occurring.FIGS. 6aand6bshow DCT DAC20ofFIG. 5during sampling and integration phases, respectively.

As can be expected,FIG. 6ais similar toFIG. 2a, differing in the presence of resistor Rpcoupled between the output terminal of OP and the positive terminal of capacitor C1and turned-on resistor Rscoupled to the input voltage Vin(t) and to the positive terminal of capacitor C1. Turned-on resistor Rsis an equivalent resistor of the turned-on switch either S0or S1depending on the current digital signal. The resistances of resistors Rsand Rpare defined as Rs0and Rp0, respectively. Following the principles used in the description ofFIG. 2a, during the current sampling phase, capacitor C2inFIG. 6astores a charge sample, Q20, proportional to the voltage difference between Ve(t) and Vref, as shown in formula (6):
Q20=C20*(Ve−Vref),  (6)

where Veis the voltage level at the positive terminal of capacitor C2during the current sampling phase.

Ve, as generated from a voltage divider with resistors Rsand Rpconnected in series and two end terminals respectively powered by output voltage Vo(t−1) and input voltage Vin(t), is determined by both output voltage Vo(t−1) and input voltage Vin(t) and can be shown in formula (7):
Ve=((Rp0/(Rs0+Rp0))*Vin(t)+((Rs0/(Rs0+Rp0))*Vo(t−1).  (7)

Accordingly, Q20is influenced by not only input voltage Vin(t) but also output voltage Vo(t−1).

FIG. 6bis similar toFIG. 2b, differing in the presence of resistor Rpcoupled between the output terminal of OP and the positive terminal of capacitor C1. If Rp0is low enough that the charge redistribution in DCT DAC20ofFIG. 6breaches a substantially stable condition at the end of the current integration phase, resistor Rpis negligible andFIG. 6bcompletely equalsFIG. 2b. Under this assumption and following the principles used forFIG. 2b, at the end of the current integration phase, output voltage V(t) for DCT DAC20ofFIG. 6bcan be shown in formula (8):
Vo(t)=(C10/(C10+C20))*Vo(t−1)+(C20/(C10+C20))*Ve.  (8)

Comparing formula (8) with formula (5), only slightly differences occur in the last variables of these two formulas. The last variable in formula (8) is Vewhile the last variable in formula (5) is Vin(t). As shown in formula (7), Veis determined by Vin(t) and Vo(t−1) with different weightings decided by Rs0and Rp0. If Rp0is very large in comparison with Rs0, the weighting for Vo(t−1) in formula (7) approaches 0 such that the influence from Vo(t−1) is negligible and Veis substantially equal to Vin(t). Accordingly, formula (8) is substantially the same as formula (5), proving that DCT DAC20inFIG. 5is a functional DAC substantially the same as DCT DAC10inFIG. 1.

In summary, there are two assumptions to make DCT DAC20inFIG. 5a functional DAC. The first assumption is that resistance Rp0of pass resistor Rpis low enough to stabilize the charge redistribution at the end of an integration phase. The required duration to complete charge redistribution is determined by the RC time constant of a corresponding circuit with all relevant elements, which in the case ofFIG. 6binclude pass resistor Rpand capacitors C1and C2. If the RC time constant is substantially lower than the duration of the corresponding circuit to operation, the corresponding circuit is deemed stable after the duration. Therefore, it is suggested that Rp0*(C10+C20) is 12%, or preferably 8%, lower than the integration duration Tintof an integration phase. The second assumption is that resistance Rp0is relatively high enough to ignore the influence of feedback from output voltage V0(t). This second assumption can be satisfied by making Rp0much higher than Rs0. It is suggested that Rp0is 1000%, or preferably 1500%, larger than Rs0.

DCT DAC20inFIG. 5lacks switch S4inFIG. 1, which has a MOS switch and is unable to properly operate in low voltage applications. DCT DAC20rather introduces pass resistor Rpsuch that DCT DAC20can be implemented in common CMOS technology and operate in low voltage applications.