PIXEL CIRCUIT AND SOLID-STATE IMAGING DEVICE

A pixel circuit (300) includes a photoreceptor circuit block (PR) configured to generate a photoreceptor signal. An analog-to-digital converter stage (500) is configured to compare a first input photoreceptor signal with at least one first threshold voltage and to compare a second input photoreceptor signal with at least one second threshold voltage. An electronic switch assembly (310) is configured to pass the photoreceptor signal to the first comparison in a first operating state and to pass the photoreceptor signal to the second comparison in a second operating state.

FIELD OF THE INVENTION

The present disclosure relates to a pixel circuit and a solid-state imaging device. In particular, the present disclosure is related to the field of event detection sensors reacting to changes in light intensity, such as dynamic vision sensors (DVS).

BACKGROUND

Computer vision deals with how machines and computers can gain high-level understanding from digital images or videos. Typically, computer vision methods aim at excerpting, from raw image data obtained through an image sensor, that type of information the machine or computer uses for other tasks.

Many applications such as machine control, process monitoring or surveillance tasks are based on the evaluation of the movement of objects in the imaged scene. Conventional image sensors with a plurality of pixels arranged in an array of pixels deliver a sequence of still images (frames). Detecting moving objects in the sequence of frames typically involves elaborate and expensive image processing methods.

Event detection sensors like DVS tackle the problem of motion detection by delivering only information about the position of changes in the imaged scene. Unlike image sensors that transfer large amounts of image information in frames, transfer of information about pixels that do not change can be omitted, resulting in a sort of in-pixel data compression. The in-pixel data compression removes data redundancy and facilitates high temporal resolution, low latency, low power consumption, and high dynamic range with little motion blur. DVS are thus well suited especially for solar or battery powered compressive sensing or for mobile machine vision applications where the motion of the system including the image sensor has to be estimated and where processing power is limited due to limited battery capacity. In principle the architecture of DVS allows for high dynamic range and good low-light performance, in particular in the field of computer vision.

It is desirable to further improve the inherently high temporal resolution of pixel circuits and solid-state imaging devices adapted for event detection like DVS.

SUMMARY OF INVENTION

Typically, a pixel of a solid-state imaging device implementing event detection includes a photoreceptor conversion block (photoreceptor module) and a pixel back-end. The photoreceptor conversion block includes at least one photoelectric conversion element per pixel and outputs a photoreceptor signal, wherein a voltage level of the photoreceptor signal depends on the intensity of light detected by the photoelectric conversion element. The pixel back-end processes the photoreceptor signal and generates event information each time a change in light intensity exceeds predefined threshold values. The event information includes information about the position of the pixel for which the light intensity exceeded the threshold. Parts of the pixel back-end may be shared between two more pixels. A controller may retrieve the event information from the various pixel circuits, e.g., at regular intervals or on demand.

The present disclosure mitigates shortcomings of conventional pixel circuits of solid-state imaging devices suitable for event detection.

To this purpose, a pixel circuit according to the present disclosure includes a photoreceptor circuit block that is configured to generate a photoreceptor signal, wherein a voltage level of the photoreceptor signal may depend on the intensity of light detected in a photoelectric conversion element. An analog-to-digital converter stage includes a first input and a second input. The analog-to-digital converter stage is configured to compare a signal based on a first input signal applied to the first input with at least one first threshold voltage and to compare a signal based on a second input signal applied to the second input with at least one second threshold voltage. An electronic switch assembly is configured to pass the photoreceptor signal to the first input in a first operating state and to the second input in a second operating state.

The electronic switch assembly facilitates sequentially passing the photoreceptor signal from one single photoreceptor circuit block to at least two inputs of an analog-to-digital converter stage. The analog-to-digital converter stage comparing the input signals on the at least two inputs with predefined thresholds enables processing separately two or more input signals derived from the same photoelectric conversion element. With the electronic switch assembly enabling sequentially passing the photoreceptor signal derived from a single photoelectric conversion device to the multiple inputs of the analog-to-digital converter stage it is possible to decouple to some degree the step of sampling light intensity in the pixel circuit and the step of reading out the event information from the pixel circuit.

In particular, passing the photoreceptor signal from a first one of the analog-to-digital converter stage inputs to a second one after detection of an event by processing the photoreceptor signal applied to the first one of the analog-to-digital converter stage inputs enables the detection of changes in light intensity even before the previous event detected by the pixel circuit has been retrieved from an output stage of the pixel circuit. Temporal resolution can be increased and the probability of information loss can be reduced.

DETAILED DESCRIPTION

FIG.1Ais a block diagram of a solid-state imaging device600employing event-based change detection. The solid-state imaging device600includes a pixel array610with one or more pixels611, wherein each pixel611includes a photoelectric conversion element PD. The pixel array610may include one single photoelectric conversion element PD or may be a one-dimensional pixel array with the photoelectric conversion elements PD of all pixels arranged along a straight or meandering line (line sensor). In particular, the pixel array610may be a two-dimensional array, wherein the photoelectric conversion elements PDs of the pixels611may be arranged along straight or meandering rows and along straight or meandering lines.

The illustrated embodiment shows a two dimensional array of pixels611, wherein the pixels611are arranged along straight rows and along straight columns running orthogonal to the rows. Each pixel611converts incoming light into digital, e.g. binary event data Ev indicating a change of the light intensity, e.g. an increase by at least an upper threshold amount and/or a decrease by at least a lower threshold amount. Each pixel611may temporary store the event data Ev.

A controller650performs a sequential control of the processes in the solid-state imaging device600. For example, the controller650may control a threshold generation circuit630that determines and supplies thresholds to individual pixels611in the pixel array610. A readout circuit620provides control signals for addressing the individual pixels611and outputs event position information. The event position information includes information about the position of those pixels611in the array of pixels611, whose stored event data Ev indicate an event.

FIG.1Bshows details of one of the pixels611of the pixel array610illustrated inFIG.1A. Each pixel611includes a photoreceptor circuit block PR and is assigned to a pixel back-end619. Each complete pixel back-end619may be assigned to one single photoreceptor circuit block PR. Alternatively, a pixel back-end619or parts thereof may be assigned to two or more photoreceptor circuit blocks PR, wherein a shared portion of the pixel back-end619may be sequentially connected to the assigned photoreceptor circuit blocks PR in a multiplexed manner.

The photoreceptor circuit block PR includes a photoelectric conversion element PD, e.g. a photodiode. The photoelectric conversion element PD converts impinging light9into a photocurrent Iphoto through the photoelectric conversion element PD. The amount of the photocurrent Iphoto depends on the light intensity of the impinging light9, wherein in the range of interest the photocurrent Iphoto increases with increasing intensity of the detected light.

A photoreceptor circuit PRC converts the photocurrent Iphoto into a photoreceptor signal Vpr. The voltage of the photoreceptor signal Vpr is a function of the photocurrent Iphoto, wherein in the range of interest the voltage of the photoreceptor signal Vpr increases with increasing photocurrent Iphoto.

A voltage memory circuit612temporarily holds a memory voltage Vmem which amount depends on a previously evaluated voltage of the photoreceptor signal Vpr. The voltage memory circuit612updates the memory voltage Vmem when the pixel611has detected an event.

In particular, the voltage memory circuit612may include a memory capacitor613that receives the photoreceptor signal Vpr such that a first electrode of the memory capacitor613carries an amount of charge that depends on the photoreceptor signal Vpr and thus the intensity of light received by the photoelectric conversion element PD. A second electrode of the memory capacitor613is connected to a floating comparator node (inverting input) of a comparator circuit614. A differential voltage Vdiff at the comparator node varies with changes in the photoreceptor signal Vpr.

The comparator circuit614compares the differential voltage Vdiff, which corresponds to the voltage difference between the current photoreceptor signal Vpr and the memory voltage Vmem, in other words the difference between the current photoreceptor signal Vpr and the past photoreceptor signal, with a threshold Vb. The comparator circuit614can be in each pixel back-end619, or can be shared between a subset (for example a column) of pixels611. According to an example, each pixel611includes a pixel back-end619including a comparator circuit614, such that the comparator circuit614is integral to the pixel611and each pixel has a dedicated comparator circuit614.

A memory element615may sample digital event data Ev reflecting the comparator output signal Vcomp output by the comparator circuit614, e.g. in response to a sample signal from the controller650. The memory element615may include a sampling circuit (for example a switch and a parasitic or explicit capacitor) and/or a digital memory circuit such as a latch or a flip-flop. In one embodiment, the memory element615may be a sampling circuit. The memory element615may be configured to store event data Ev including one, two or more binary bits. For example, the event data Ev may include a first bit indicating an increase of the photoreceptor signal Vpr to beyond an upper threshold and a second bit indicating a decrease of the photoreceptor signal Vpr to below a lower threshold.

An output signal of the memory element615(or another signal derived from the comparator output signal Vcomp) may control the voltage memory circuit612to set the inverting input of the comparator circuit614to a predefined potential in order to store the current voltage level of the photoreceptor signal Vpr as new memory voltage Vmem. The memory element615may be located in the pixel611or in the readout circuit620as shown inFIG.1A. The output signal of the memory element615may be controlled in response to the content of the memory element615.

In addition or in the alternative, a global reset signal received from the controller650may control the voltage memory circuit612to set the inverting input of the comparator circuit614to a predefined potential.

The solid-state imaging device600is operated as follows: A change in light intensity of incident radiation9translates into a change of the voltage level of the photoreceptor signal Vpr. Either continuously or at predetermined point in times designated by the controller650, the comparator circuit614compares the differential voltage Vdiff at the inverting input (comparator node) to a threshold voltage Vb applied on its non-inverting input. If the differential voltage exceeds the threshold voltage Vb, the controller650operates the memory element615to store the comparator output signal Vcomp, e.g. as digital event data Ev.

If the state of the stored comparator output signal (event data) indicates a change in light intensity AND the global reset signal GlobalReset (controlled by the controller650) is active, the voltage memory circuit612may reset the differential voltage Vdiff to a known level, wherein the memory voltage Vmem across the memory capacitor613is updated.

The memory element615may store the event data Ev indicating a change of the light intensity detected by the photoelectric conversion element PD by more than the threshold voltage Vb.

The solid state imaging device600may output event position information identifying those pixels611where a light intensity change has been detected. For example, the position information may include the row number and the column number of the pixel611in the pixel array610.

A detected light intensity change at a given pixel is called an event. More specifically, the term ‘event’ means that the photoreceptor signal representing and being a function of light intensity of a pixel611has changed by an amount greater than or equal to a threshold applied by the controller650through the threshold generation circuit630. To transmit an event, the address of the corresponding pixel611is transmitted along with data indicating whether the light intensity change was positive or negative. The data indicating whether the light intensity change was positive or negative may include one further single bit.

To detect light intensity changes between current and previous instances in time, each pixel611stores a representation of the light intensity at the previous instance in time. More concretely, each pixel611stores a memory voltage Vmem representing the photoreceptor signal Vpr at the time of the last event registered at the concerned pixel611and generates a differential voltage Vdiff representing the difference between the voltage level of the photoreceptor signal Vpr at the time of the last event registered at the concerned pixel611and the current photoreceptor signal Vpr at this pixel611(Vdiff=Vpr−Vmem).

To detect events, the differential voltage Vdiff at the comparator node may be first compared to a first threshold +Vb to detect an increase in light intensity (ON-event), and the comparator output is sampled on a (explicit or parasitic) capacitor or stored in a flip-flop. Then the differential voltage Vdiff at the comparator node may be compared to a second threshold −Vb to detect a decrease in light intensity (OFF-event) and the comparator output is sampled on a (explicit or parasitic) capacitor or stored in a flip-flop. Alternatively, the comparator circuit614may compare the differential voltage Vdiff to both thresholds +Vb, −Vb simultaneously.

The global reset signal is sent to all pixels611, and in each pixel611this global reset signal may be logically ANDed with the sampled comparator outputs to reset only those pixels where an event has been detected. Then the sampled comparator output voltages (event data Ev) are read out, and the corresponding pixel addresses sent to a data receiving device.

FIG.2shows a pixel circuit300according to the present disclosure. The pixel circuit300includes a photoreceptor circuit block PR, an electronic switch assembly310and an analog-to-digital converter stage500. The photoreceptor circuit block PR generates a photoreceptor signal Vpr. The analog-to-digital converter stage500includes a first input and a second input. The analog-to-digital converter stage500compares a signal based on a first input signal applied to the first input with at least one first threshold voltage and compares a signal based on a second input signal applied to the second input with at least one second threshold voltage. The electronic switch assembly310passes the photoreceptor signal Vpr from the photoreceptor circuit block PR to the first input in a first operating state and passes the photoreceptor signal Vpr to the second input in a second operating state.

The photoreceptor circuit block PR may include a photoelectric conversion element PD. The photoelectric conversion element PD may be or may include one or more photodiodes or another type of photosensors. The photoelectric conversion element PD converts light9impinging on a sensitive surface of the photoelectric conversion element PD into a photocurrent Iphoto through the photoelectric conversion element PD. The amount of the photocurrent Iphoto is a function of the light intensity of the impinging light9, wherein the photocurrent Iphoto increases with increasing intensity of the detected light9.

A photoreceptor circuit PRC converts the photocurrent Iphoto into a photoreceptor signal Vpr. The voltage of the photoreceptor signal Vpr is a function of the photocurrent Iphoto, wherein the voltage of the photoreceptor signal Vpr increases with increasing photocurrent Iphoto. The photoreceptor signal Vpr may be available at an output of the photoreceptor circuit block PR.

The electronic switch assembly310includes at least a first electronic switch311with a first side electrically connected to the output of the photoreceptor circuit block PR and includes a second electronic switch312with a first side electrically connected to the output of the photoreceptor circuit block PR. The electronic switch assembly310may include more than the two electronic switches311,312, wherein the first side of each further electronic switch is electrically connected to the output of the photoreceptor circuit block PR.

Electrically connected electronic elements may be electrically connected through a direct, permanent low-resistive connection, e.g., through a conductive line. The term “electrically connected” may include connection through other electronic elements provided and suitable for permanent and/or temporary signal transmission and/or transmission of energy. For example, electronic elements may also be electrically connected through electronic switches such as transistors or transistor circuits, e.g. MOSFETs, transmission gates, and others.

Each of the electronic switches311,312may include one n-channel MOSFET (metal-oxide-semiconductor field effect transistor), one p-channel MOSFET, or a combination of two or more MOSFETs. For example, each electronic switch311,312may be or may include a transmission gate with the source-to-drain paths of an n-channel MOSFET and a p-channel MOSFET electrically connected in parallel.

The analog-to-digital converter stage500derives digital event data Ev1, Ev2 from each of the input signals. For example, the analog-to-digital converter stage500may be configured to perform a 1-bit analog-to-digital conversion with or without sign with respect to each input signal. Event data Ev1 may include two bits and event data Ev2 may include two bits, wherein in each case a first bit indicates whether or not the input signal or a signal derived from the input signal exceeds an upper threshold and the second bit indicates whether or not the input signal or a signal derived from the input signal falls below a lower threshold.

The analog-to-digital converter stage500may include at least a first converter stage100and a second converter stage200. The first converter stage100generates first event data Ev1 on the basis of the first input signal. The second converter stage200generates second event data Ev2 from the second input signal.

In particular, a second side of the first electronic switch311and an input of the first converter stage100are electrically connected. A second side of the second electronic switch312and an input of the second converter stage100are electrically connected. The analog-to-digital converter stage500may include more than the first and second converter stages100,200, wherein the input of any further converter stage is electrically connected with a second side of a further electronic switch of the electronic switch assembly310.

The first and second converter stages100,200may include different electronic circuits or may share some electronic circuits. In each case, the first and second converter stages100,200are capable to process the input signals applied to the first and second inputs of the analog-to-digital converter stage500independently from each other such that processing of the first input signal is without effect on the result of the processing of the second input signal and such that processing of the second input signal is without effect on the result of the processing of the first input signal.

The first converter stage100outputs first event data Ev1 indicating whether or not the first converter stage100detects an event. The second converter stage200outputs second event data Ev2 indicating whether or not the second converter stage200detects an event.

Each converter stage100,200may first derive a signal from the input signal and may then convert the signal derived from the input signal into event data Ev1, Ev2. For example, each converter stage100,200may subtract a variable offset voltage (memory voltage) from the photoreceptor signal Vpr to obtain a differential voltage and may then convert the differential voltage into the digital event data Ev1, Ev2. The variable offset voltage may be equal to a voltage level of the photoreceptor signal Vpr at that point in time when the precedent event data Ev1, Ev2 of the respective converter stage100,200is retrieved from the pixel circuit300.

A memory circuit399, which may include the memory element615as described with respect toFIG.2, stores the event data Ev1, Ev2 and from the stored event data Ev1, Ev2 a controller650retrieves event position information EvPos. At the same time the controller650may reset the event data Ev1, Ev2.

A first control circuit391controls the electronic switch assembly310based on at least one output signal of the analog-to-digital converter stage500. In particular, the operating state of the electronic switch assembly310may change in response to a change of the event data Ev1, Ev2, i.e., in response to a detected event.

The first control circuit391may control the electronic switch assembly310in a way such that the first electronic switch311passes the photoreceptor signal Vpr to the first converter stage100in a first operating state and to the second converter stage200in a second operating state.

The first control circuit391may switch the electronic switch assembly310into the second operating state, when a first output signal of the analog-to-digital converter stage500indicates that the first input signal exceeds an upper first threshold or falls below a lower first threshold. The first input signal exceeds the upper first threshold when a voltage level of the first input signal exceeds a voltage level of the upper first threshold. The first input signal falls below the lower first threshold when a voltage level of the first input signal falls below a voltage level of the lower first threshold.

The first control circuit391may switch the electronic switch assembly310into the first operating state, when a second output signal of the analog-to-digital converter stage500indicates that the second input signal exceeds an upper second threshold or falls below a lower second threshold. The second input signal exceeds the upper second threshold when a voltage level of the second input signal exceeds a voltage level of the upper second threshold. The second input signal falls below the lower second threshold when a voltage level of the second input signal falls below a voltage level of the lower second threshold.

In the first operating state, the first electronic switch311is “on” and connects the output of the photoreceptor circuit block PR and the first input of the analog-to-digital converter stage500, whereas the second electronic switch312may be “off” and the second input of the analog-to-digital converter stage500is disconnected from the output of the photoreceptor circuit block PR.

In the second operating state, the first electronic switch311may be “off” and the first input of the analog-to-digital converter stage500is disconnected from the output of the photoreceptor circuit block PR, whereas the second electronic switch312is “on” and electrically connects the output of the photoreceptor circuit block PR and the second input of the analog-to-digital converter stage500.

Operation of the pixel circuit300may start with the electronic switch assembly310being in the first operating state and passing the photoreceptor signal Vpr to the first converter stage100. When the first converter stage100detects an event, the memory circuit399stores corresponding first event data Ev1 until such time as the controller650retrieves and/or resets the first event data Ev1.

Conventionally, with no second converter stage200, events occurring in the time period between event setting and event resetting either overwrite the event data (if the first converter stage100remains active and the photoreceptor signal returns to a previous level) or are missed (if the first converter stage100is deactivated and the photoreceptor signal Vpr again changes).

Instead, in the pixel circuit300detection of an event by the first converter stage100triggers the first control circuit391to control the second electronic switch312to pass the photoreceptor signal Vpr to the second converter stage200. The second converter stage200is capable of detecting events starting almost immediately after event detection in the first converter stage100.

Simultaneously, the first control circuit391may control the first electronic switch312to disconnect the photoreceptor signal Vpr from the first converter stage100. The first event data Ev1 is save from being overwritten before being read out. The probability for losing significant information is reduced.

Disconnecting the photoreceptor signal Vpr from the first converter stage100may avoid that the first event data Ev1 is overwritten when the photoreceptor signal Vpr returns to a previous value. The capacitive load of the photoreceptor signal Vpr remains unaffected. Capacitive loading is reduced and therefore speed may be improved. In addition, operation of the second converter stage200can be decoupled from switching processes in the second converter stage100, which otherwise could adversely affect operation of the second converter stage200.

The electronic switch assembly310enables sequentially passing the photoreceptor signal Vpr from one single photoreceptor circuit block PR to at least two inputs of the analog-to-digital converter stage500. The analog-to-digital converter stage500processes the input signals on the at least two inputs under consideration of predefined threshold voltages and allows separated processing of the two or more input signals.

In particular, passing the photoreceptor signal Vpr from a first one of the converter stages100,200to a second one after the detection of an event by processing the photoreceptor signal Vpr applied to the first one of the converter stages100,200, enables the detection of further changes in light intensity even before the previous event detected by the pixel circuit300has been retrieved from the pixel circuit300.

In the pixel circuit300illustrated inFIG.3Athe first comparator stage100includes a first converter circuit120and a first voltage memory circuit110electrically connected in series between the first electronic switch311and the first converter circuit120. The second comparator stage200includes a second converter circuit220and a second voltage memory circuit210electrically connected in series between the second electronic switch312and the second converter circuit220.

The first voltage memory circuit110is electrically connected to the first electronic switch311of the electronic switch assembly310. The first voltage memory circuit110generates a first differential voltage Vdiff1, e.g. by subtracting a variable first offset voltage from the first input signal. The second voltage memory circuit210is electrically connected to the second electronic switch312of the electronic switch assembly310. The second voltage memory circuit210generates a second differential voltage Vdiff2, e.g. by subtracting a variable second offset voltage from the second input signal.

The variable first offset voltage (first memory voltage) is equal to or approximates to a high degree the voltage level of the first input voltage at that preceding point in time at which the preceding first event data Ev1 has been read out from the pixel circuit300. The first offset voltage may result from the voltage drop a stored charge generates across a first memory capacitor. Accordingly, the second variable offset voltage is equal to or approximates to a high degree the voltage level of the second input voltage at that preceding point in time at which the preceding second event data Ev2 has been read out from the pixel circuit300. The second offset voltage results from the voltage drop a stored charge generates across a second memory capacitor, by way of example.

The first converter circuit120generates the first event data Ev1 based on the first input signal and the second converter circuit220generates the second event data Ev2 based on the second input signal.

In particular, the first converter circuit120converts the first differential voltage Vdiff1 into the first event data Ev1 by 1-bit analog-to-digital conversion with or without sign and the second converter circuit120converts the second differential voltage Vdiff2 into the second event data Ev2 by 1-bit analog-to-digital conversion with or without sign.

Further inFIG.3A, the analog-to-digital converter stage500simultaneously compares the signal derived from the first input signal with the upper first threshold and with the lower first threshold. In addition, the analog-to-digital converter stage500simultaneously compares the signal derived from the second input signal with the upper second threshold and with the lower second threshold.

In particular, the first converter circuit120may include a first upper comparator121comparing the first differential voltage Vdiff1 with a positive first threshold voltage +Vb1 and a first lower comparator122comparing, at the same time, the first differential voltage Vdiff1 with a negative first threshold voltage −Vb1. The first upper comparator121outputs a first upper event bit Ev1h indicating whether or not the first differential voltage Vdiff1 exceeds the positive first threshold voltage +Vb1. The first lower comparator122outputs a first lower event bit Ev1l indicating whether or not the first differential voltage Vdiff1 falls below the negative first threshold voltage −Vb1.

For example, logic “1” at the output of the first upper comparator121may indicate that the first differential voltage Vdiff1 exceeds the upper threshold. Logic “1” at the output of the first lower comparator122may indicate that the first differential voltage Vdiff1 falls below the lower threshold. Each logic “1” indicates an event. Logic “0”s at both outputs indicate the absence of events.

The second converter circuit220may include a second upper comparator221comparing the second differential voltage Vdiff2 with a positive second threshold voltage +Vb2 and a second lower comparator222comparing the second differential voltage Vdiff2 with a negative second threshold voltage −Vb2. The second upper comparator221outputs a second upper event bit Ev2h indicating whether or not the second differential voltage Vdiff2 exceeds the positive second threshold voltage +Vb2. The second lower comparator222outputs a second lower event bit Ev21 indicating whether or not the second differential voltage Vdiff2 falls below the negative second threshold voltage −Vb2.

The first and second upper threshold voltages +Vb1, +Vb2 may be equal or approximately equal. The first and second lower threshold voltages −Vb1, −Vb2 may be equal or approximately equal. The positive and negative threshold voltages of the same converter circuit120,220may have the same or approximately the same amount.

The memory circuit399may include four 1-bit storage elements for temporarily storing the event data bits Ev1h, Ev1l, Ev2h, Ev21. The storage elements may include latches or sample/hold circuits, by way of example. The memory circuit399passes the event data bits to a controller650according to a predetermined protocol with or without handshake. For example, the controller650may check and reset the event data Ev at regular intervals and/or as needed.

The first control circuit391may close the second electronic switch312and open the first electronic switch311after detection of an event for the first differential voltage Vdiff1. The first control circuit391may close the first electronic switch311and open the second electronic switch312after detection of an event for the second differential voltage Vdiff2.

InFIG.3Bthe analog-to-digital converter stage500includes a shared converter circuit150that sequentially, e.g. alternatingly, generates the first event data Ev1 based on the first input signal and the second event data Ev2 based on the second input signal.

In particular, both the first converter stage100and the second converter stage200may use the shared converter circuit150. The shared converter circuit150may include a shared upper comparator151alternatingly comparing the first differential voltage Vdiff1 and the second differential voltage Vdiff2 with a positive threshold voltage +Vb and a shared lower comparator152alternatingly comparing the first differential voltage Vdiff1 and the second differential voltage Vdiff2 with a negative threshold voltage −Vb.

A supplementary electronic switch153may alternatingly connect the comparator input of the shared converter circuit150with an output of the first voltage memory circuit110or with an output of the second voltage memory circuit210.

The supplementary electronic switch153may include one n-channel MOSFET (metal-oxide-semiconductor field effect transistor), one p-channel MOSFET, or a combination of two or more MOSFETs. For example, the supplementary electronic switch153may be or may include a transmission gate with the source-to-drain paths of an n-channel MOSFET and a p-channel MOSFET electrically connected in parallel.

The supplementary electronic switch153may switch synchronously or almost synchronously with the electronic switch assembly310. For example, the supplementary electronic switch153may connect the output of the first voltage memory circuit110with the input of the shared converter circuit150in the first operating state. The supplementary electronic switch153may connect the output of the second voltage memory circuit210with the input of the shared converter circuit150in the second operating state.

FIG.4refers to details of the first and second voltage memory circuits110,210in the pixel circuits300ofFIGS.3A and3B.

In particular, the pixel circuit300may include a first memory capacitor111and a first voltage memory reset circuit112, wherein the first memory capacitor111is electrically connected in series between the first electronic switch311and the first memory reset circuit112. In addition, the pixel circuit300includes a second memory capacitor211and a second voltage memory reset circuit212, wherein the second memory capacitor211is electrically connected in series between the second electronic switch312and the second memory reset circuit212.

A first electrode of the first memory capacitor111and the second side of the first electronic switch311are electrically connected. A second electrode of the first memory capacitor111is electrically connected with the first voltage memory reset circuit112. In a reset mode, the first voltage memory reset circuit112resets the comparator node of the first converter circuit120(and the first differential signal Vdiff1) to a predetermined voltage Vref1. In a tracking mode of the first voltage memory reset circuit112, the first differential signal Vdiff1 follows the voltage difference between the photoreceptor signal Vpr and a first memory voltage Vmem1 dropping across the first memory capacitor111.

Accordingly, a first electrode of the second memory capacitor211and the second side of the second electronic switch312are electrically connected. A second electrode of the second memory capacitor211is electrically connected with the second voltage memory reset circuit212. In a reset mode, the second voltage memory reset circuit212resets the comparator node of the second converter circuit220(and the second differential signal Vdiff2) to a predetermined voltage Vref2. In a tracking mode of the second voltage memory reset circuit212, the second differential signal Vdiff2 follows the voltage difference between the photoreceptor signal Vpr and a second memory voltage Vmem2 dropping across the second memory capacitor211.

An auxiliary control circuit393controls the first and second memory reset circuits112,212based on at least one output signal of the analog-to-digital converter stage500or the memory circuit399. In particular, the auxiliary control circuit393may control the first and second memory reset circuits112,212in response to a change of at least one of the output signals of the analog-to-digital converter stage500.

The predetermined voltages Vref1, Vref2 may be equal or approximately equal. The predetermined voltages Vref1, Vref2 may be static voltages. For example, the predetermined voltages Vref1, Vref2 may be 0V or any other voltage permanently obtained by voltage dividers and/or reference voltage sources from the supply voltages of the pixel circuit300. Alternatively, the predetermined voltages may be only temporarily provided, e.g. only during the second operating modes of the voltage memory reset circuits112,212.

InFIG.5the first converter circuit120includes a first single comparator123and the second converter circuit220includes a second single comparator223. The lower and upper thresholds are sequentially supplied to the non-inverting comparator input through the threshold generation circuit630. The event data for the two thresholds may be passed to different memory elements of the memory circuit399.

For the reset mode of the first memory reset circuit112, the threshold voltage Vb may be set to a predetermined voltage with a voltage level in the middle between the lower threshold and the upper threshold, e.g. about 0V. In the reset mode, the first memory reset circuit112connects the output of the first single comparator123with the inverting input of the first single comparator123. The resulting first differential signal Vdiff1 may approximate the inherent offset voltage of the first single comparator123. By applying the same reset mechanism to all pixel circuits300of a pixel array610, the effect of different offset voltages may be compensated. The same applies to the second memory reset circuit212and the second converter circuit220with a second single comparator223accordingly.

FIG.6shows a pixel circuit300with the first memory reset circuit112including a first voltage amplifier113, a first feedback capacitor114and a first switching element119. The first memory reset circuit112is configured such that in an off-state of the first switching element119the first feedback capacitor114is effective between an input and an output of the first voltage amplifier113and such that in an on-state of the first switching element119the first feedback capacitor114is short-circuited.

Accordingly, the second memory reset circuit212includes a second voltage amplifier213, a second feedback capacitor214and a second switching element219. The second memory reset circuit212is configured such that in an off-state of the second switching element219the second feedback capacitor214is effective between an input and an output of the second voltage amplifier213and such that in an on-state of the second switching element219the second feedback capacitor214is short-circuited.

Each of the first and second switching elements119,219may include one n-channel MOSFET (metal-oxide-semiconductor field effect transistor), one p-channel MOSFET, or a combination of two or more MOSFETs. For example, each of the first and second electronic switching elements119,219may be or may include a transmission gate with the source-to-drain paths of an n-channel MOSFET and a p-channel MOSFET electrically connected in parallel.

In the reset mode of the first memory reset circuit112, the first switching element119is “on” and short-circuits the electrodes of the first feedback capacitor114, which is discharged. The first voltage amplifier113is effectively in unity gain feedback and the voltage VA1 at the inverting input of the first voltage amplifier113is forced to VSS plus the offset voltage of the first voltage amplifier113.

In the tracking mode, the first electronic switch311is “on”. The first switching element119is “off” and the first feedback capacitor114is charged through the first memory capacitor111. The output voltage of the first voltage amplifier113changes accordingly to correct the voltage at the virtual ground at its inverting input. As a result, the first differential signal Vdiff1 proportionately follows the photoreceptor signal Vpr.

Accordingly, in the reset mode of the second memory reset circuit212, the second switching element219is “on” and short-circuits the electrodes of the second feedback capacitor214, which is discharged. The second voltage amplifier213is effectively in unity gain feedback and the voltage VA2 at the inverting input of the second voltage amplifier213is forced to VSS plus the offset voltage of the second voltage amplifier213.

In the tracking mode, the second electronic switch312is “on”. The second switching element219is “off” and the second feedback capacitor214is charged through the second memory capacitor211. The output voltage of the second voltage amplifier213changes accordingly to correct the voltage at the virtual ground at its inverting input. As a result, the second differential signal Vdiff2 proportionately follows the photoreceptor signal Vpr.

The first memory reset circuit112in the first converter stage120may be in the reset mode as long as the electronic switch assembly310passes the photoreceptor signal Vpr to the input of the second converter stage200in order to avoid integrating noise and/or leakage current in the first voltage memory circuit110. Accordingly, the second memory reset circuit212in the second converter stage220may be in the reset mode as long as the electronic switch assembly310passes the photoreceptor signal Vpr to the input of the first converter stage100in order to avoid integrating noise and/or leakage current in the second voltage memory circuit210.

The pixel circuit300includes an auxiliary control circuit393that controls the first switching element119such that the first switching element119switches to the off-state when the electronic switching assembly310changes to the first operating state and such that the first switching element119switches to the on-state when the electronic switching assembly310changes to the second operating state. In addition, the auxiliary control circuit393controls the second switching element219such that the second switching element219switches to the off-state when the electronic switching assembly310changes to the second operating state and switches to the on-state when the electronic switching assembly310changes to the first operating state.

In other words, the first voltage memory reset circuit112is predominantly in the reset mode when the second electronic switch312passes the photoreceptor signal Vpr to the second converter stage200. The first voltage memory reset circuit112is predominantly in the tracking mode when the first electronic switch311passes the photoreceptor signal Vpr to the first converter stage100. The second voltage memory reset circuit212is predominantly in the reset mode when the first electronic switch311passes the photoreceptor signal Vpr to the first converter stage100. The second voltage memory reset circuit212is predominantly in the tracking mode when the second electronic switch312passes the photoreceptor signal Vpr to the second converter stage200.

FIG.7Ashows a pixel circuit300with a first control circuit391and an auxiliary control circuit393andFIG.7Bshows a time diagram for voltage signals in the pixel circuit300.

The first control circuit391includes OR gates396connected to the four outputs of the analog-to-digital converter stage500. The OR gates396generate a pixel event signal Ev_any indicating that the analog-to-digital converter stage500has detected any kind of event. Logic “1” of the pixel event signal Ev_any may indicate detection of an event.

A digital frequency divider circuit397may output complementary binary first control signals sw, nsw. The first binary control signal sw controls the first electronic switch311, wherein a logic “1” may turn on the first electronic switch311. The inverted first binary control signal nsw controls the second electronic switch312, wherein a logic “1” may turn on the second electronic switch312. The digital frequency divider circuit397may include a binary counter clocked by the pixel event signal Ev_any, e.g. a positive edge triggered D flip flop in feedback, e.g. with the inverting output connected to the data input (“D”).

The complementary first binary control signals sw, nsw change with any incoming leading edge of the pixel event signal Ev_any. As soon as any of the converter stages100,200detects an event, the electronic switching assembly310passes the photoreceptor signal Vpr to the other converter stage200,100.

In addition, the first control circuit391may receive further event data from the memory circuit399and may hold both memory reset circuits112,212in the reset mode after both converter stages100,200have detected an event and as long as none of the events has been acknowledged by the controller650.

The auxiliary control circuit393receives the first binary control signals sw, nsw and outputs complementary second binary control signals dsw, dnsw, which are delayed with respect to the first binary control signals sw, nsw by at least one gate propagation delay. The second binary control signal dsw controls the second switching element219, wherein logic “1” may turn on the second switching element219. The inverted second binary control signal dnsw controls the first switching element119, wherein logic “1” may turn on the first switching element119.

In particular, the auxiliary control circuit393is configured to delay, by at least one gate propagation delay, trailing and falling edges of the second control signals controlling the first and second switching elements119,219with respect to corresponding edges of the first control signals controlling the first and second electronic switches311,312.

FIG.7Bshows a time diagram of the pixel event signal Ev_any, the complementary first control signals sw, nsw and the complementary second control signals dsw, dnsw for a given, slowly changing photoreceptor signal Vpr. In addition, the time diagram shows the first differential signal Vdiff1 at the inverting input of the first converter circuit120and the second differential signal Vdiff2 at the inverting input of the second converter circuit220ofFIG.7A.

At t=t0 the first electronic switch311is “on” (sw=“1”) and the first switching element119is “off” (dnsw=“0”). The first electronic switch311passes the photoreceptor signal Vpr to the first converter stage100. The first converter stage100is in the tracking mode and checks the first differential signal Vdiff1 (“Vdiff1=Vi_1−Vmem1”) against the upper and lower thresholds.

The second electronic switch312is “off” (nsw=“0”) and the second switching element119is “on” (dsw=“1”). The second electronic switch312decouples the second converter stage200from the photoreceptor signal Vpr and the second input voltage Vin_2 remains unchanged.

Starting from t=t0 the photoreceptor signal Vpr gradually rises. The first input signal Vin_1 and the first differential signal Vdiff1 rise accordingly until at t=t1 the first differential signal Vdiff1 exceeds the upper threshold of the first converter stage100. The corresponding output signal of the first comparator stage100changes to “1” and the pixel event signal Ev_any rises.

At t=t2 the rising edge of the pixel event signal Ev_any triggers a synchronous change of the first binary control signals sw, nsw.

At t=3 the edges of the first binary control signals sw, nsw trigger switching of the first and second electronic switches311,312. In addition the first binary control signals sw, nsw trigger a synchronous change of the complementary second control signals dsw, dnsw. The trailing and rising edges of the second control signals dsw, dnsw may be delayed by one gate propagation delay.

With sw changing from “1” to “0”, the first electronic switch311switches from “on” to “off” and decouples the photoreceptor signal Vpr from the first converter stage100. With nsw changing from “0” to “1” the second electronic switch312switches from “off” to “on” and passes the photoreceptor signal Vpr to the second converter stage200such that the second input signal Vin_2 starts tracking the photoreceptor signal Vpr.

At t=t4, the first switching element119turns “on” (dnsw=“1”), wherein the first converter stage100changes into the reset mode. In the reset mode the first voltage amplifier113is effectively in unity gain feedback and the voltage VA1 at the inverting input of the first voltage amplifier113is forced to VSS plus the offset voltage of the first voltage amplifier113. The first differential signal Vdiff1 is approximately 0V and safely within the margins set by the upper and lower threshold. The second switching element219turns “off” (dsw=“0”), wherein the second converter stage200changes into the tracking mode. In the tracking mode, the second differential signal Vdiff2 qualitatively follows the photoreceptor signal Vpr. As long as the second differential signal Vdiff2 is within the margin, both outputs of the first converter stage100are reset to “0” and, as a consequence, the pixel event signal Ev_any changes to “0”.

After t=t4, the first converter stage100and the second converter stage200have changed their operational mode.

In first periods A1 only the first converter stage100is active and in the tracking mode. In second periods A2 only the second converter stage200is active and in the tracking mode. In intermediate periods A0, which are comparatively short, the analog-to-digital converter stage500is in an idle state without tracking the photoreceptor signal Vpr.

FIG.8shows a pixel circuit300with a collision detection circuit380that outputs a collision detection signal col_d based on output signals of the analog-to-digital converter stage500.

In particular, the memory circuit399may include storage elements397holding the event data and a handshake circuit398. Each storage element397may store one bit event data according to the output signals of the comparator stages100,200. The handshake circuit398communicates with the controller650and resets a storage element397after the controller650has acknowledged receipt of the information about the content of the storage element397.

The collision detection circuit380may include two OR gates381. Each OR gate may output “1” if at least one of the event data bits assigned to the same converter stage100,200indicates an event. A “1” at the output of an AND gate382indicates that the memory circuit399holds event data for both converter stages100,200. The output of the AND gate may set a latch383outputting the collision detection signal col_d to the controller650. The controller650may reset the latch383for acknowledging receipt of the collision detection signal col_d.

FIG.9shows a pixel circuit300with a collision control circuit395that controls at least the electronic switch assembly310based on the collision detection signal col_d. In response to an active collision detection signal cold, the collision control circuit395may effect that both converter stages100,200are simultaneously in the reset mode for some time. Insofar, the collision control circuit395may overwrite the effect of the first control circuit391and the auxiliary control circuit393.

A further logic gate may combine the collision detection signal col_d with a collision configuration signal col_cfg generated by the controller650in order to activate/deactivate the collision control circuit395according to settings in the controller650.

FIG.10refers to an analog-to-digital converter stage500including a shared converter circuit150that sequentially, e.g. alternatingly, generates the first event data based on the first input signal and the second event data based on the second input signal as shown inFIG.3B.

A first buffer circuit141is electrically connected between the first voltage memory circuit110and the supplementary electronic switch153. A second buffer circuit142is electrically connected between the second voltage memory circuit210and the supplementary electronic switch153. The first and second buffer circuits141,142may include sample/hold circuits and/or amplifying stages.

FIG.11shows two pixel circuits300, each of them including a photoreceptor circuit block PR and a pixel back-end301. Each photoreceptor circuit block PR includes a photoelectric conversion element PD and a photoreceptor circuit PRC outputting a photoreceptor signal Vpr. Each pixel back-end301includes an electronic switch assembly with a first electronic switch311and with a second electronic switch312, an analog-to-digital converter stage500and a control unit390. A controller650receives and acknowledges the event data Ev.

The control unit390may include the memory circuit399, the first control circuit391, the auxiliary control circuit393, and, if applicable, the collision detection circuit380and/or the collision control circuit395as described with reference toFIGS.3-10. For each pixel300the controller650evaluates and, if applicable, resets the event data Ev and outputs event position information EvPos identifying pixels300that have detected an event.

FIG.12shows a photoreceptor circuit block PR including an intensity readout circuit740. The intensity readout circuit740transforms the photocurrent Iphoto flowing through the photoelectric conversion element PD into a voltage signal Vpix with a voltage level depending on a magnitude of the photocurrent Iphoto.

The intensity readout circuit740may be adapted to determine the magnitude of the photocurrent Iphoto through the photoelectric conversion element PD of the photoreceptor circuit block PR at given points in time and outputs the voltage signal Vpix, which voltage level depends on the photocurrent Iphoto on a vertical signal line VSL. The vertical signal line VSL may be shared by all pixels arranged along the same column of pixels in the pixel array.

In the illustrated embodiment of the intensity readout circuit740, an n-channel anti-blooming MOSFET745and an n-channel decoupling MOSFET746are electrically connected in series between the high supply voltage VDD and the photoelectric conversion device PD. The anti-blooming MOSFET745and the decoupling MOSFET746are controlled by fixed bias voltages Vbias3, Vbias4 applied to the gates of the MOSFETs745,746. Additional elements, e.g. a controlled path of a feedback portion of the photodetector circuit PRC may be electrically connected in series between the decoupling MOSFET746and the photoelectric conversion device PD.

Decoupling MOSFET746may basically decouple the photodetector circuit PRC from voltage transients at the center node748between the MOSFETs746,747. Anti-blooming MOSFET745may ensure that the voltage at the center node748does not fall below a certain level given by the difference between Vbias4 and the threshold voltage of the anti-blooming MOSFET745in order to ensure proper operation of the photodetector circuit PRC.

The source of an n-channel transfer MOSFET741is electrically connected to the center node748. A drain of the re-channel transfer MOSFET741is electrically connected to the gate of an n-channel amplifier MOSFET743. The gate of the n-channel transfer MOSFET741receives a transfer signal TX.

The drain of an n-channel reset MOSFET742is electrically connected to the high supply potential VDD. A source of the reset MOSFET742is electrically connected to the gate of the amplifier MOSFET743and to the drain of the transfer MOSFET741. The gate of the reset MOSFET742receives a reset signal RESET.

The reset signal RESET switches on the reset MOSFET742for a short time such that the gate of the amplifier MOSFET743is set to a potential close to the high supply potential VDD. With the reset MOSFET742switched off again, when the transfer signal TX switches on the transfer MOSFET741, an amount of charge proportional to the magnitude of the photocurrent Iphoto is discharged from the gate of the amplifier MOSFET743.

The amplifier MOSFET743, an n-channel selection MOSFET744, a vertical signal line VSL and an n-channel current source MOSFET621with biased gate are electrically connected in series in this order between the high supply potential VDD and the low supply potential VSS. The gate of the selection MOSFET744receives a selection signal Sel. When the selection signal Sel switches on the selection MOSFET744, a voltage signal Vpix with a voltage level proportional to the amount of charge on the gate of the amplifier MOSFET743drops across the drain/source path of the current source MOSFET621.

The current source MOSFET621and a column amplifier circuit622for amplifying and/or buffering the voltage signal Vpix may be integrated in the readout circuit620of the solid-stage imaging device600as illustrated inFIG.1A. The column amplifier circuit622further processes the voltage signal Vpix, which voltage level is a function of the photocurrent Iphoto at that point in time, when the transfer MOSFET741has been in the on state.

Alternative embodiments of the intensity readout circuit740may be realized without transfer MOSFET, wherein the reset MOSFET may replace the anti-blooming MOSFET745, and wherein the source of such reset MOSFET is directly connected to the gate of the amplifier MOSFET743.

In the photoreceptor circuit block ofFIG.12, the intensity detection circuit740and the photoreceptor circuit PRC for event detection are electrically connected in series with respect to the photocurrent Iphoto, wherein evaluation of intensity and detection of events may be performed substantially contemporaneously.

The photoreceptor circuit block PR inFIG.13includes a photocurrent routing circuit707,747. The photocurrent routing circuit707,747electrically connects the photoelectric conversion element PD with the photoreceptor circuit PRC in a first operating state. The photocurrent routing circuit707,747electrically connects the photoelectric conversion element PD with the intensity readout circuit740in a second operating state.

In addition, the photocurrent routing circuit707,747disconnects the photoelectric conversion element PD from the intensity readout circuit740in the first operating state and disconnects the photoelectric conversion element PD from the photoreceptor circuit PRC in the second operating state.

The photocurrent routing circuit707,747may include two electronic switches, e.g. MOSFETs. For example, a source of an n-channel first transfer MOSFET707is electrically connected to the cathode of the photoelectric conversion element PD. A drain of the first transfer MOSFET707is electrically connected to the input of the photoreceptor circuit PRC.

A source of an n-channel second transfer MOSFET747is electrically connected to the cathode C of the photoelectric conversion element PD. A drain of the second transfer MOSFET747is electrically connected to the source of the reset MOSFET742and to the gate of the amplifier MOSFET743as described with respect toFIG.12.

The gate of the first transfer MOSFET707receives a first transfer signal TGD1. The gate of the second transfer MOSFET747receives a second transfer signal TG1. When the first transfer signal TGD1 switches on the first transfer MOSFET707and the second transfer signal TG1 switches off the second transfer MOSFET747, the photoreceptor circuit block PR is in an event detection mode. When the first transfer signal TGD1 switches off the first transfer MOSFET707and the second transfer signal TG1 switches on the second transfer MOSFET747, the photoreceptor circuit block PR is in an intensity readout mode.

Since in the intensity readout mode the photoreceptor circuit PRC for event detection is disconnected from the photoelectric conversion element PD, the intensity readout may be more precise and may deliver better image quality.

FIG.14is a perspective view showing an example of a laminated structure of a solid-state imaging device23020with a plurality of pixels arranged matrix-like in array form. Each pixel includes at least one photoelectric conversion element.

The solid-state imaging device23020has the laminated structure of a first chip (upper chip)910and a second chip (lower chip)920.

The laminated first and second chips910,920may be electrically connected to each other through TC(S)Vs (Through Contact (Silicon) Vias) formed in the first chip910.

The solid-state imaging device23020may be formed to have the laminated structure in such a manner that the first and second chips910and920are bonded together at wafer level and cut out by dicing.

In the laminated structure of the upper and lower two chips, the first chip910may be an analog chip (sensor chip) including at least one analog component of each pixel, e.g., the photoelectric conversion elements arranged in array form. For example, the first chip910may include only the photoelectric conversion elements.

Alternatively, the first chip910may include further elements of each photoreceptor circuit block. For example, the first chip910may include, in addition to the photoelectric conversion elements, at least some or all of the n-channel MOSFETs of the photoreceptor circuit blocks. Alternatively, the first chip910may include each element of the photoreceptor circuit blocks.

The first chip910may also include parts of the pixel back-ends301. For example, the first chip910may include the memory capacitors, or, in addition to the memory capacitors, sample/hold circuits and/or buffer circuits electrically connected between the memory capacitors and the event-detecting comparator circuits. Alternatively, the first chip910may include the complete pixel back-ends. With reference toFIG.1A, the first chip910may also include at least portions of the readout circuit620, the threshold generation circuit630and/or the controller650.

The second chip920may be mainly a logic chip (digital chip) that includes the elements complementing the circuits on the first chip910to the solid-state imaging device23020. The second chip920may also include analog circuits, for example circuits that quantize analog signals transferred from the first chip910through the TCVs.

The second chip920may have one or more bonding pads BPD and the first chip910may have openings OPN for use in wire-bonding to the second chip920.

The solid-state imaging device23020with the laminated structure of the two chips910,920may have the following characteristic configuration:

The electrical connection between the first chip910and the second chip920is performed through, for example, the TCVs. The TCVs may be arranged at chip ends or between a pad region and a circuit region. The TCVs for transmitting control signals and supplying power may be mainly concentrated at, for example, the four corners of the solid-state imaging device23020, by which a signal wiring area of the first chip910can be reduced.

FIGS.15and16show possible allocations of elements of the pixel300across the first chip910and the second chip920ofFIG.14.

The photoreceptor circuit PRC includes an amplifier portion and a feedback portion. The amplifier portion may include or consist of an inverting amplifier element, e.g. an n-channel MOSFET (metal oxide semiconductor field effect transistor). Alternatively, the amplifier portion may include an amplifier circuit with more than one transistor. In particular, the amplifier portion may be configured as common source amplifier circuit.

An output of the amplifier portion supplies the photoreceptor signal Vpr and feeds back to the input of the amplifier portion through the feedback portion. The feedback portion may include or consist of an amplifier element, e.g. an n-channel MOSFET in source-follower configuration. Alternatively, the feedback portion may include a p-channel MOSFET with fixed gate bias or a feedback circuit with more than one element.

The photoreceptor circuit PRC defines a predetermined current-to-voltage transfer characteristic. According to an example, the predetermined current-to-voltage transfer characteristic may be a logarithmic current-to-voltage transfer characteristic.

The feedback portion includes a controlled path, wherein a current through the controlled path is controlled in response to the feedback signal.

An input of the photoreceptor circuit PRC is electrically connected to the photoelectric conversion element PD. For example, the controlled path of the feedback portion and the photoelectric conversion element PD may be electrically connected in series.

In particular, the photoreceptor circuit PRC may include an n-channel feedback MOSFET717. A source of the feedback MOSFET717is connected to a cathode of the photoelectric conversion element PD. An anode of the photoelectric conversion element PD is electrically connected to a low supply voltage VSS. The photoreceptor circuit PRC further includes a common source amplifier including a n-channel amplifier MOSFET715and a load element. The source of the amplifier MOSFET715is electrically connected to the low supply potential VSS. The load element is electrically connected between the high supply potential VDD and the drain of the amplifier MOSFET715. The load element may include the controlled path of a p-channel load MOSFET716with the gate electrically connected to a bias potential Vbias. The bias potential Vbias may be fixed.

InFIG.15the first chip910includes the photoelectric conversion element PD and the n-channel MOSFETs of the photoreceptor circuit block PR. The second chip920includes the p-channel load MOSFET716of the photoreceptor circuit block PR and the pixel back-ends301. One through contact via915per pixel300passes the photoreceptor signal Vpr from the first chip910to the second chip920.

Typically, the first chip910includes a p-type substrate and formation of p-channel MOSFETs may imply the formation of n-doped wells separating the p-type source and drain regions of the p-channel MOSFETs from each other and from further p-type regions. Avoiding the formation of p-channel MOSFETs may therefore simplify the manufacturing process of the first chip910.

InFIG.16the first chip910includes the photoelectric conversion element PD. The second chip920includes the n-channel MOSFETs and the p-channel load MOSFET716of the photoreceptor circuit block PR and the pixel back-end301. For each pixel300, one single through contact via915passes the photocurrent Iphoto from the first chip910to the second chip920. The total number of through contact vias915for the pixels is not greater than the number of pixels such that the first chip910is less complex.

FIG.17illustrates schematic configuration examples of solid-state imaging devices23010,23020.

The single-layer solid-state imaging device23010illustrated in part A ofFIG.17includes a single die (semiconductor substrate)23011. Mounted and/or formed on the single die23011are a pixel region23012(photoelectric conversion elements), a control circuit23013(readout circuit, threshold generation circuit, controller), and a logic circuit23014(pixel back-end). In the pixel region23012, pixels are disposed in an array form. The control circuit23013performs various kinds of control including control of driving the pixels. The logic circuit23014performs signal processing.

Parts B and C ofFIG.17illustrate schematic configuration examples of multi-layer solid-state imaging devices23020with laminated structure. As illustrated in parts B and C ofFIG.17, two dies (chips), namely a sensor die23021(first chip) and a logic die23024(second chip), are stacked in a solid-state imaging device23020. These dies are electrically connected to form a single semiconductor chip.

With reference to part B ofFIG.17, the pixel region23012and the control circuit23013are formed or mounted on the sensor die23021, and the logic circuit23014is formed or mounted on the logic die23024. The logic circuit23014may include at least parts of the pixel back-ends301with the pixel circuits300as described with reference to the previous FIGS. The pixel region23012includes at least the photoelectric conversion elements.

With reference to part C ofFIG.17, the pixel region23012is formed or mounted on the sensor die23021, whereas the control circuit23013and the logic circuit23014are formed or mounted on the logic die23024.

According to another example (not illustrated), the pixel region23012and the logic circuit23014, or the pixel region23012and parts of the logic circuit23014may be formed or mounted on the sensor die23021, and the control circuit23013is formed or mounted on the logic die23024.

The imaging section12031may be or may include a solid-state imaging device for event detection with pixel circuits according to the embodiments of the present disclosure. The imaging section12031may output the electric signal as event position information identifying pixels having detected an event. The light received by the imaging section12031may be visible light, or may be invisible light such as infrared rays or the like.

The in-vehicle information detecting unit12040detects information about the inside of the vehicle and may be or may include a solid-state imaging device for event detection and with pixel circuits according to the embodiments of the present disclosure. The in-vehicle information detecting unit12040is, for example, connected with a driver state detecting section12041that detects the state of a driver. The driver state detecting section12041, for example, includes a camera that includes the solid-stage imaging device and that is focused on the driver. On the basis of detection information input from the driver state detecting section12041, the in-vehicle information detecting unit12040may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

The sound/image output section12052transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example ofFIG.18, an audio speaker12061, a display section12062, and an instrument panel12063are illustrated as the output device. The display section12062may, for example, include at least one of an on-board display or a head-up display.

FIG.19is a diagram depicting an example of the installation position of the imaging section12031, wherein the imaging section12031may include imaging sections12101,12102,12103,12104, and12105.

The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying the pixel circuits according to the embodiments for obtaining event-triggered image information, also short events can be tracked. Temporal resolution is enhanced, less motion information is lost and the vehicle control system operates more reliable.

Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

The solid-state imaging device according to the present disclosure may be any device used for analyzing and/or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, the solid-state imaging device may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

Specifically, in the field of image reproduction, the solid-state imaging device may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, the solid-state imaging device may be integrated in an in-vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.

In the field of home appliances, the solid-state imaging device may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly the solid-state imaging device may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and/or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the solid-state imaging device may be integrated in any type of sensor, e.g. a solid-state image device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.

In the field of security, the solid-state imaging device can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, the solid-state imaging device can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, the solid-state imaging device can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the solid-state imaging device can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.

(1) A photoreceptor circuit block, including:a pixel circuit that includes a photoreceptor circuit block configured to generate a photoreceptor signal;an analog-to-digital converter stage including a first input and a second input, wherein the analog-to-digital converter stage is configured to compare a signal based on a first input signal applied to the first input with at least one first threshold voltage and to compare a signal based on a second input signal applied to the second input with at least one second threshold voltage; andan electronic switch assembly configured to pass the photoreceptor signal to the first input in a first operating state and to pass the photoreceptor signal to the second input in a second operating state.

(2) The pixel circuit according to (1), further includinga first control circuit configured to control the electronic switch assembly based on at least one output signal of the analog-to-digital converter stage.

(3) The pixel circuit according to any of (1) to (2),wherein the analog-to-digital converter stage is configured to simultaneously compare the signal derived from the first input signal with an upper first threshold and with a lower first threshold.

(4) The pixel circuit according to any of (1) to (3),wherein the analog-to-digital converter stage includes a first converter stage configured to generate first event data based on the first input signal, and a second converter stage configured to generate second event data based on the second input signal.

(5) The pixel circuit according to (4),wherein the first converter stage includes a first converter circuit for generating the first event data based on the first input signal, and wherein the second converter stage includes a second converter circuit for generating the second event data based on the second input signal.

(6) The pixel circuit according to (4),wherein the analog-to-digital converter stage includes a shared converter circuit configured to sequentially generate the first event data based on the first input signal and the second event data based on the second input signal.

(7) The pixel circuit according to any of (1) to (6), wherein the analog-to-digital converter stage includes:a first voltage memory circuit electrically connected to a first electronic switch of the electronic switch assembly and configured to generate a first differential voltage by subtracting a first memory voltage from the first input signal; anda second voltage memory circuit electrically connected to a second electronic switch of the electronic switch assembly and configured to generate a second differential voltage by subtracting a second memory voltage from the second input signal.

(8) The pixel circuit according to any of (1) to (7), further including:a first memory capacitor and a first voltage memory reset circuit, wherein the first memory capacitor is electrically connected in series between the first electronic switch and the first memory reset circuit, anda second memory capacitor and a second voltage memory reset circuit, wherein the second memory capacitor is electrically connected in series between the second electronic switch and the second memory reset circuit.

(9) The pixel circuit according to (8),wherein each of the first and second memory reset circuits includes a voltage amplifier, a feedback capacitor and an switching element, wherein the memory reset circuit is configured such that in an off-state of the switching element the feedback capacitor is effective between input and output of the voltage amplifier and in an on-state of the switching element the feedback capacitor is short-circuited.

(10) The pixel circuit according to (9), further including:an auxiliary control circuit configured to control the switching elements such thatthe first switching element switches to the off-state when the electronic switching assembly changes to the first operating state and switches to the on-state when the electronic switching assembly changes to the second operating state; andthe second switching element switches to the off-state when the electronic switching assembly changes to the second operating state and switches to the on-state when the electronic switching assembly changes to the first operating state.

(11) The pixel circuit according to (10),wherein the auxiliary control circuit is configured to delay, by at least one gate propagation delay, trailing and falling edges of second control signals controlling the first and second switching elements with respect to corresponding edges of first control signals controlling the electronic switch assembly.

(12) The pixel circuit according to any of (1) to (11), further including:a collision detection circuit configured to output a collision detection signal based on output signals of the analog-to-digital converter stage.

(13) The pixel circuit according to (12), further including:a collision control circuit configured to control at least the electronic switch assembly based on the collision detection signal.

(14) A solid-state imaging device, including:a pixel array including a plurality of pixel circuits, wherein photoelectric conversion elements of the pixel circuits are arranged in matrix form and wherein each pixel circuit includes:a photoreceptor circuit block configured to generate a photoreceptor signal;an analog-to-digital converter stage including a first input and a second input, wherein the analog-to-digital converter stage is configured to compare a signal based on a first input signal applied to the first input with at least one first threshold voltage and to compare a signal based on a second input signal applied to the second input with at least one second threshold voltage; andan electronic switch assembly configured to pass the photoreceptor signal to the first input in a first operating state and to pass the photoreceptor signal to the second input in a second operating state.

(15) The solid-state imaging device according to (14), further including:a collision detection circuit configured to output a collision detection signal based on output signals of the analog-to-digital converter stage; anda controller configured to control the electronic switch assembly in response to a change of the collision detection signal.