Semiconductor device

A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.

This application claims priority from Korean Patent Application No. 10-2018-0056538 filed on May 17, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to a semiconductor device.

2. Description of the Related Art

A semiconductor device includes an integrated circuit (IC) including a metal-oxide-semiconductor field-effect transistor (MOSFET). As sizes and design rules of semiconductor devices are gradually reduced, MOSFETs are increasingly rapidly downscaled. The downscaling of the MOSFETs may cause a short channel effect, thereby degrading operating characteristics of the semiconductor devices. Thus, research has been conducted into various methods for forming semiconductor devices having better performance by overcoming limitations due to an increase in the integration density of the semiconductor devices.

Furthermore, an IC aims to obtain high operation reliability and low power consumption. Accordingly, research has also been conducted into methods for forming a device having higher reliability and lower power consumption in a smaller space.

SUMMARY

Aspects of the present disclosure provide a semiconductor device having improved operation performance.

According to an aspect of the present inventive concept, there is provided a semiconductor device, the semiconductor device comprising first to fourth cells sequentially disposed on a substrate in a first direction, first to third diffusion break structures configured to space the first to fourth cells apart from each other, the first diffusion break structure being interposed between the first and second cells, the second diffusion break structure being interposed between the second and third cells, and the third diffusion break structure being interposed between the third and fourth cells, a first fin structure configured to protrude from the substrate and extend in the first direction, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure in a second direction intersecting the first direction and extend in the first direction, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures and first to fourth gate electrodes configured to extend in the second direction on the first and second fin structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, wherein each of the first to fourth gate electrodes interests the first fin structure at an n region of the substrate and interests the second fin structure at a p region of the substrate, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.

According to another aspect of the present inventive concept, there is provided a semiconductor device, the semiconductor device comprising a substrate comprising an n region and a p region, a first fin provided with the substrate in the n region, and extending in a first direction, a second fin provided with the substrate in the p region, and extending in the first direction, the second fin being spaced apart from the first fin in a second direction intersecting the first direction, a gate electrode configured to extend in the second direction on the first and second fins, a field insulating film configured to be in contact with a side surface of the first fin in the first direction, a first dummy gate formed on the n region and formed on a top surface of the field insulating film and a top surface of the first fin, the first dummy gate being configured to extend in the second direction; and a single diffusion break film formed on the p region and aligned with the first dummy gate in the second direction, the single diffusion break film being in contact with the side surface of the second fin in the first direction.

According to still another aspect of the present inventive concept, there is provided a semiconductor device, the semiconductor device comprising a substrate, a first power rail and a second power rail configured to extend in a first direction on the substrate, the first and second power rails being spaced apart from each other in a second direction intersecting the first direction, a first fin configured to protrude from the substrate and extend in the first direction, a second fin configured to protrude from the substrate and extend in the first direction, the second fin being spaced apart from the first fin in the second direction, a first diffusion break structure and a second diffusion break structure configured to define both ends of the first and second fins and a gate electrode configured to extend on the first and second fins in the second direction, wherein the first fin is a fin nearest to the first power rail in the second direction, the second fin is a fin nearest to the second power rail in the second direction, and the first fin and the second fin have no fins between them in the second direction.

It should be noted that objects of the present disclosure are not limited to the above-described objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following descriptions.

DETAILED DESCRIPTION

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 1 to 3, 4A, 4B, 5A, and 5B.

FIG. 1is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure, andFIG. 2is a cross-sectional view taken along line A-A′ ofFIG. 1.FIG. 3is a cross-sectional view taken along line B-B′ ofFIG. 1.FIG. 4Ais a cross-sectional view taken along line C-C′ ofFIG. 1.FIG. 5Ais a cross-sectional view taken along line D-D′ ofFIG. 1.

Referring toFIGS. 1 to 3, 4A, and 4B, the semiconductor device according to some exemplary embodiments of the present disclosure may include a substrate100, first to fourth cells C1to C4, first to fifth diffusion break structures B1to B5, a first fin structure Fs1, a second fin structure Fs2, first to fourth gate electrodes G1to G4, a first gate insulating film310, a first capping film340, first spacers350, first source and drain regions400, second source and drain regions401, a first interlayer insulating film510, a second interlayer insulating film520, a first contact410, a second contact411, and the like. The semiconductor device may be a semiconductor chip.

A first direction X may be any one direction of lateral directions. A second direction Y may be a direction intersecting the first direction X, for example, a direction perpendicular to the first direction X. A third direction Z may be a direction intersecting both the first direction X and the second direction Y. For example, the third direction Z may be a direction perpendicular to both the first direction X and the second direction Y. In this case, the first direction X and the second direction Y may be lateral directions perpendicular to each other, and the third direction Z may be a vertical direction. For example, the first direction X, the second direction Y, and the third direction Z may be directions orthogonal to each other.

The substrate100may be formed of at least one semiconductor material selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium phosphide (GaP), gallium arsenide (GaAs), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), and indium phosphide (InP). Further, a silicon on insulator (SOI) substrate may be used as the substrate100.

The substrate100may have a plurality of cells formed thereon. Specifically, the substrate100may include first to fourth cells C1to C4. The first to fourth cells C1to C4may be sequentially disposed in the first direction X. Each of the first to fourth cells C1to C4may be defined by first to fifth diffusion break structure B1to B5.

Specifically, the first cell C1may be defined by the first diffusion break structure B1and the second diffusion break structure B2, and the fourth cell C4may be defined by the fourth diffusion break structure B4and the fifth diffusion break structure B5. The second diffusion break structure B2may be located between the first cell C1and the second cell C2, and the third diffusion break structure B3may be located between the second cell C2and the third cell C3. The fourth diffusion break structure B4may be located between the third cell C3and the fourth cell C4.

The first to fourth cells C1to C4may each be different circuit modules. For instance, the first cell C1may be a master latch circuit module of a master-slave latch, and the second cell C2may be a slave latch circuit module of the master-slave latch. The third cell C3may be a clock circuit module, and the fourth cell C4may be an output circuit module. Accordingly, the first to fourth cells C1to C4may function as a flip-flop circuit module all together. However, the present disclosure is not limited thereto. Each of the first to fourth cells C1to C4may include one standard cell or a plurality of standard cells. A standard cell refers to a unit cell having a specific function, for example, an AND gate, an OR gate, an inverter, and the like.

The first to fifth diffusion break structures B1to B5may insulate the first to fourth cells C1to C4from each other. For example, the first to fifth diffusion break structures B1to B5may separate the first to fourth cells C1to C4from each other so that the first to fourth cells C1to C4may operate as modules having different functions.

The substrate100may include an n region Rn and a p region Rp. As described below, an N-type metal-oxide-semiconductor (NMOS) transistor may be formed in the n region Rn, while a P-type metal-oxide-semiconductor (PMOS) transistor may be formed in the p region Rp. As shown in the drawings, the n region Rn and the p region Rp may be regions that are adjacent to each other in the second direction Y. Accordingly, each of the first to fourth cells C1to C4is included in the n region Rn and the p region Rp, and the n region Rn and the p region Rp may be aligned with each other in the first direction X. For example, as shown inFIG. 1, all the n regions Rn may be disposed above in the second direction Y, and all the p regions Rp may be disposed below in the second direction Y. In the semiconductor device according to some exemplary embodiments of the present disclosure, positions of the n region Rn and the p region Rp may be exchanged.

The first fin structure Fs1may extend in the first direction X. The first fin structure Fs1may be located in the n region Rn. The first fin structure Fs1may be separated into first to fourth fins F1to F4by the first to fifth diffusion break structures B1to B5. The first to fourth fins F1to F4may be disposed in the first to fourth cells C1to C4, respectively. In this case, although the first to fourth fins F1to F4are aligned with each other in the first direction X, the first to fourth fins F1to F4may not be aligned with each other in some embodiments.

The second fin structure Fs2may extend in the first direction X. The second fin structure Fs2may be spaced apart from the first fin structure Fs1in the second direction Y. The second fin structure Fs2may be located in the p region Rp. The second fin structure Fs2may be separated into fifth to eighth fins F5to F8by the first to fifth diffusion break structures B1to B5. The fifth to eighth fin F5to F8may be disposed in the first to fourth cells C1to C4, respectively. In this case, although the fifth to eighth fins F5to F8are aligned in the first direction X, the fifth to eighth fins F5to F8may not be aligned with each other in some embodiments.

The first fin structure Fs1and the second fin structure Fs2may protrude from the substrate100in the third direction Z, for example, a vertical direction. The first fin structure Fs1and the second fin structure Fs2may be portions of the substrate100and include an epitaxial layer grown from the substrate100. The first fin structure Fs1and the second fin structure Fs2may include, for example, silicon (Si) or silicon germanium (SiGe).

The first fin structure Fs1and the second fin structure Fs2may be located different distances from centers of the first to fourth cells C1to C4in the second direction Y. For example, a position of the first fin structure Fs1may not be symmetrical to a position of the second fin structure Fs2in the second direction Y. Further, the first fin structure Fs1and the second fin structure Fs2may include a compound semiconductor, for example, a Group IV-IV compound semiconductor or a Group III-V compound semiconductor.

For example, when the first fin structure Fs1and the second fin structure Fs2include the Group IV-IV compound semiconductor, first to sixth fins F1to F6may include a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn) or a compound obtained by doping the binary compound or the ternary compound with a Group IV element.

For example, when the first fin structure Fs1and the second fin structure Fs2include the Group III-V compound semiconductor, the first fin structure Fs1and the second fin structure Fs2may include one of a binary compound, a ternary compound, or a quaternary compound obtained by combining at least one Group-III element of aluminum (Al), gallium (Ga), and indium (In) with one Group-V element of phosphorus (P), arsenic (As), and antimony (Sb).

In the semiconductor device according to exemplary embodiments of the present disclosure, it is assumed that the first fin structure Fs1and the second fin structure Fs2include silicon.

The first to fourth gate electrodes G1to G4may extend in the second direction Y. Each of the first to fourth gate electrodes G1to G4may be disposed on the first fin structure Fs1and the second fin structure Fs2across both the first fin structure Fs1and the second fin structure Fs2.

The first gate electrode G1may be disposed in the first cell C1, and the second gate electrode G2may be disposed in the second cell C2. The third gate electrode G3may be disposed in the third cell C3, and the fourth gate electrode G4may be disposed in the fourth cell C4. In this case, the number of each of the first to fourth gate electrodes G1to G4may vary according to need and purpose. Although two first gate electrodes G1, two second gate electrodes G2, one third gate electrode G3, and one fourth gate electrode G4are illustrated inFIG. 1for brevity, the present disclosure is not limited thereto.

The first to fourth gate electrodes G1to G4may all have the same first width W1. As used herein, an expression “the same” may be a concept including a minute difference caused by a manufacturing process.

A first power rail P1may extend in the first direction X. A second power rail P2may extend in the first direction X and be spaced apart from the first power rail P1in the second direction Y. The first power rail P1and the second power rail P2may be interconnecting wires formed over the first to fourth gate electrodes G1to G4.

In example embodiments, the first power rail P1may be electrically connected to a ground voltage (e.g., GND or VSS) or a negative voltage less than the ground voltage, and the second power rail P2may be electrically connected to a power supply voltage (e.g., VDD or VCC) or an internal power supply voltage (e.g., Vint) generated from an internal voltage generator circuit of the semiconductor device. For example, each of the first to fourth cells C1to C4may be provided with the ground voltage or the negative voltage through the first power rail P1, and the power supply voltage or the internal power supply voltage through the second power rail P2.

In example embodiments, the first to fifth diffusion break structures B1to B5may have different structures in the n region Rn and the p region Rp. Specifically, each of the first to fifth diffusion break structures B1to B5may have a double diffusion break film in the n region Rn and two single diffusion break films in the p region Rp. Accordingly, the first to fifth diffusion break structures B1to B5may have a structure including a mixed diffusion break (MDB) film in which the double diffusion break film and the single diffusion break film are mixed.

In this case, the double diffusion break film and the single diffusion break film may be formed simultaneously or at different times for each. That is, although the formation of the MDB film may be performed at one time through a series of sequential operations, the MDB film may be finally formed through several discrete operations that are temporally separated by other processes. The double diffusion break film and the single diffusion break film may include the same material or different materials.

Each of the first to fifth diffusion break structures B1to B5may include two dummy gate electrodes. Specifically, the second diffusion break structure B2may include a first dummy gate electrode DG1and a second dummy gate electrode DG2, and the third diffusion break structure B3may include a third dummy gate electrode DG3and a fourth dummy gate electrode DG4. The fourth diffusion break structure B4may include a fifth dummy gate electrode DG5and a sixth dummy gate electrode DG6.

In example embodiments, a dummy gate electrode comprises one or more layers formed at the same level and adjacent to a normal gate electrode. A dummy gate electrode is patterned from the same layer(s) forming such normal gate electrode. For example, a dummy gate electrode may be simultaneously formed with a normal gate electrode with the same processes that deposit and pattern the layer(s). In general, dummy gate electrodes in semiconductor devices are not effective to cause transmission of data to external devices. For instance, a dummy gate electrode may not be electrically connected to gates of cells of the semiconductor device, or if a dummy gate electrode is electrically connected to gates of dummy cells (e.g., dummy source and drain) of the semiconductor device, such dummy gate electrodes may not be activated or if activated, may not result in communication of any data in such dummy cells to a source external to the semiconductor device.

The first to sixth dummy gate electrodes DG1to DG6may extend in the second direction Y and be disposed parallel to the first to fourth gate electrodes G1to G4. The first to sixth dummy gate electrodes DG1to DG6and the first to fourth gate electrodes G1to G4may be spaced the same distance apart from each other in the first direction X. That is, the first to sixth dummy gate electrodes DG1to DG6and the first to fourth gate electrodes G1to G4may be electrode structures formed at constant intervals and used as gate electrodes or dummy gate electrodes as needed. Accordingly, like the gate electrodes, the dummy gate electrodes may have the first width W1in the first direction X.

The double diffusion break film may include two dummy gate electrodes, while the single diffusion break film may occupy a space corresponding to one dummy gate electrode. Accordingly, an MDB film in which one double diffusion break film and two single diffusion break films are connected in the second direction Y may occupy a space corresponding to two dummy gate electrodes. For example, each of the first to fifth diffusion break structures B1to B5may occupy a space corresponding to two dummy gate electrodes.

The second fin F2may be separated from the third fin F3by the third diffusion break structure B3on the substrate100. Further, the sixth fin F6may be separated from the seventh fin F7by the third diffusion break structure B3on the substrate100. Specifically, referring toFIG. 2, the second fin F2may be separated from the third fin F3by a first trench T1. The first trench T1may be partially filled with a first field insulating film200.

The first field insulating film200may be formed on the substrate100, cover portions of sidewalls of the first fin structure Fs1and the second fin structure Fs2, and expose upper portions of the first fin structure Fs1and the second fin structure Fs2.

The first field insulating film200may include a material capable of applying stress to the first fin structure Fs1. When the first field insulating film200applies stress to a channel of a transistor formed in the first fin structure Fs1, the mobility of electrodes serving as carriers may be improved.

The second gate electrode G2and the third gate electrode G3may be formed on the second fin F2and the third fin F3, respectively. The second gate electrode G2and the third gate electrode G3may include the first gate insulating film310, a first work-function metal320, and a first fill metal330in the n region Rn.

The first gate insulating film310may include an interface film including a silicon oxide film and a high-k dielectric film including a high-k dielectric material. The high-k dielectric film may include a high-k dielectric material having a higher dielectric constant than the silicon oxide film. The high-k dielectric material may include, for example, at least one of silicon oxynitride, silicon nitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate, but the present disclosure is not limited thereto.

In this case, the high-k dielectric film may include a dipole forming material to control a threshold voltage of a gate electrode (Hereinafter, a threshold voltage may be referred to with respect to a transistor in a cell). Here, the dipole forming material may include at least one of lanthanum (La), neodymium (Nd), europium (Eu), dysprosium (Dy), holmium (Ho), and ytterbium (Yb). However, the present disclosure is not limited thereto.

The first work-function metal320may be formed on the first gate insulating film310. The first work-function metal320may include an n-type work-function control material. The n-type work-function control material may include at least one of titanium nitride (TiN), tantalum nitride (TaN), and titanium aluminum carbide (TiAlC). However, the present embodiment is not limited thereto.

The first fill metal330may be formed on the first work-function metal320. The first fill metal330may include at least one of tungsten (W) and titanium nitride (TiN), but the present disclosure is not limited thereto.

The second gate electrode G2and the third gate electrode G3may be used as gate electrodes of NMOS transistors in the n region Rn due to the first work-function metal320and the first fill metal330.

The first capping film340may be disposed on each of the second gate electrode G2and the third gate electrode G3. The first capping film340may include silicon nitride, but the present disclosure is not limited thereto.

First spacers350may be disposed on side surfaces of the second gate electrode G2, the third gate electrode G3, and the first capping film340. Although the first spacers350are exemplarily illustrated as a single film in the drawings, the first spacers350may be multiple spacers formed by stacking a plurality of films. Each of the multiple spacers that form the first spacers350may have an I shape, an L shape, or a combination thereof according to manufacturing process or purpose. The first spacers350may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), and a combination thereof.

The third dummy gate electrode DG3and the fourth dummy gate electrode DG4may have similar structures to the second gate electrode G2and the third gate electrode G3, respectively. The third dummy gate electrode DG3and the fourth dummy gate electrode DG4may include a first dummy gate insulating film210, a first dummy work-function metal220, and a first dummy fill metal230.

In this case, the first dummy gate insulating film210may include the same material as the first gate insulating film310and have the same thickness as the first gate insulating film310. Similarly, the first dummy work-function metal220may include the same material as the first work-function metal320and have the same thickness as the first work-function metal320. The first dummy fill metal230may include the same material as the first fill metal330.

However, each of the third dummy gate electrode DG3and the fourth dummy gate electrode DG4may be formed on top surfaces of the second fin F2and the third fin F3and a top surface of the first field insulating film200. Accordingly, each of the third dummy gate electrode DG3and the fourth dummy gate electrode DG4may have a stepped bottom surface along steps between the first field insulating film200and the second fin F2and the third fin F3. Since the first dummy gate insulating film210and the first dummy work-function metal220are formed along the stepped bottom surface, the first dummy gate insulating film210and the first dummy work-function metal220may also have stepped bottom surfaces. In addition, the first dummy fill metal230, which fills the remaining space, may also have a stepped bottom surface.

A first dummy capping film240may be disposed on each of the third dummy gate electrode DG3and the fourth dummy gate electrode DG4. The first dummy capping film240may include the same material as the first capping film340and have the same thickness as the first capping film340.

The first source and drain regions400may be disposed to sides of the second gate electrode G2, the third gate electrode G3, the third dummy gate electrode DG3, and the fourth dummy gate electrode DG4. The first source and drain regions400may include an epitaxial layer formed using an epitaxial process. Further, the first source and drain regions400may be elevated source and drain regions. The first source and drain regions400located in the n region Rn may include, for example, a silicon (Si) epitaxial layer or a silicon carbide (SiC) epitaxial layer. In this case, the first source and drain regions400may include SiP or SiPC that is heavily doped with phosphorous (P).

The first interlayer insulating film510may cover top surfaces of the substrate100, the first source and drain regions400, and the first field insulating film200. The first interlayer insulating film510may fill spaces between side surfaces of gate electrodes and dummy gate electrodes. A top surface of the first interlayer insulating film510may be coplanar with top surfaces of the first spacers350, first dummy spacers250, the first capping film340, and the first dummy capping film240.

The second interlayer insulating film520may be formed on the first interlayer insulating film510. Each of the first interlayer insulating film510and the second interlayer insulating film520may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material having a lower dielectric constant than silicon oxide.

The first contact410may be formed through the first interlayer insulating film510and the second interlayer insulating film520and in contact with the first source and drain regions400. The first contact410may be formed to a greater depth than the top surfaces of the first source and drain regions400. A silicide may be formed at an interface between the first contact410and the first source and drain regions400. A barrier metal may be formed on surfaces of the first contact410which are in contact with the first interlayer insulating film510, the second interlayer insulating film520, and the first source and drain regions400.

Each of the second gate electrode G2and the third gate electrode G3in the p region Rp may include the first gate insulating film310, the first work-function metal320, a second work-function metal325, and the first fill metal330.

The second work-function metal325may be formed on the first work-function metal320. The second work-function metal325may include a p-type work-function control material. The p-type work-function control material may include at least one of TiN, TaN, and TiAlC. However, the present embodiment is not limited thereto. The first fill metal330may be formed on the second work-function metal325.

The second gate electrode G2and the third gate electrode G3may be used as a gate electrode of a PMOS transistor in the p region Rp due to the first work-function metal320, the second work-function metal325, and the first fill metal330.

The third diffusion break structure B3may include two single diffusion break films600instead of the third dummy gate electrode DG3and the fourth dummy gate electrode DG4. Each of the single diffusion break films600may be formed in each of a second trench T2and a third trench T3.

The second trench T2may be formed to a relatively great depth at a position where the third dummy gate electrode DG3is located, while the third trench T3may be formed to a relatively great depth at a position where the fourth dummy gate electrode DG4is located. Accordingly, the second trench T2and the third trench T3may separate the sixth fin F6and the seventh fin F7and, simultaneously, define an isolated fin FI. The isolated fin FI may be a portion of the second fin structure Fs2, which is isolated by the two single diffusion break films600.

The second trench T2and the third trench T3formed in the p region Rp may have a smaller width than the first trench T1formed in the n region Rn. However, the present embodiment is not limited thereto.

Lower side surfaces of the single diffusion break film600may be defined by the sixth fin F6, the seventh fin F7, and the isolated fin FI, while upper side surfaces of the single diffusion break film600may be defined by the first dummy spacers250. For example, the first dummy spacers250may be located on side surfaces of the single diffusion break film600.

Since each of the single diffusion break films600is located at positions where the existing third dummy gate electrode DG3and fourth dummy gate electrode DG4are located, each of the single diffusion break films600may have the same first width W1as the third dummy gate electrode DG3and the fourth dummy gate DG4. In addition, a top surface of the single diffusion break film600may be at the same level as top surfaces of the first capping film340and the first interlayer insulating film510.

The single diffusion break film600may include a material capable of applying stress to the second fin structure Fs2. When the single diffusion break film600applies stress to a channel of a transistor formed in the second fin structure Fs2, the mobility of holes serving as carriers may be improved.

The second source and drain regions401may be disposed to sides of the second gate electrode G2and the third gate electrode G3. Further, dummy source and drain regions402may be disposed on the isolated fin FI between the single diffusion break films600.

The second source and drain regions401and the dummy source and drain regions402may include an epitaxial layer formed using an epitaxial process. Further, the second source and drain regions401and the dummy source and drain regions402may be elevated source and drain regions. The second source and drain regions401and the dummy source and drain regions402located in the p region Rp may include, for example, a SiGe epitaxial layer.

Outer circumferential surfaces of the first source and drain regions400, the second source and drain regions401, and the dummy source and drain regions402may have at least one of a diamond shape, a circular shape, and a rectangular shape. InFIG. 4A, a diamond shape (or a pentagonal or hexagonal shape) is illustrated as an example.

A process of forming the single diffusion break film600may be performed after a process of forming the second source and drain regions401and the dummy source and drain regions402. Accordingly, the dummy source and drain regions402may be formed to a side of each of the single diffusion break films600.

In the semiconductor device according to some exemplary embodiments of the present disclosure, a process of forming the single diffusion break film600may be performed before the second source and drain regions401and the dummy source and drain regions402are formed. In this case, the dummy source and drain regions402may not be separately formed on the isolated fin FI.

The second contact411may be formed through the first interlayer insulating film510and the second interlayer insulating film520and formed in contact with the second source and drain regions401. The second contact411may be formed to have a greater depth than top surfaces of the second source and drain regions401. A silicide may be formed at an interface between the second contact411and the second source and drain regions401. A barrier metal may be formed on surfaces of the second contact411, which are in contact with the first interlayer insulating film510, the second interlayer insulating film520, and the second source and drain regions401.

Referring toFIGS. 4A and 5A, a first groove Gr1and a second groove Gr2may be disposed to sides of the third fin F3in a second direction Y. The first groove Gr1and the second groove Gr2may be traces obtained by forming particular fins together with the third fin F3and then cutting partial of the particular fins. Similarly, a third groove Gr3and a fourth groove Gr4may be disposed to sides of the seventh fin F7in the second direction Y. AlthoughFIG. 4Aillustrates an example in which one groove is disposed in each of both sides of the third fin F3and the seventh fin F7, the present embodiment is not limited thereto.

In the semiconductor device according to the present embodiment, a transistor may be implemented using only one fin in each of the n region Rn and the p region Rp. A single fin structure of the semiconductor device may have lower power consumption and higher integration density than a structure using a plurality of fins.

Furthermore, the semiconductor device according to the present embodiment may obtain a relatively wide space margin in an upper contact and an interconnection structure, thereby greatly improving operating reliability of the semiconductor device.

A conventional structure using a plurality of fins may have a more stable distribution in threshold voltage than a single fin structure. A distribution in threshold voltage may affect PMOS transistors having high threshold voltages more significantly. When a double diffusion break film structure is used, the distribution in threshold voltage may be more problematic. That is due to the fact that, as compared to a single diffusion break film structure, the double diffusion break film structure has a layout effect, which causes a rise in threshold voltage of a gate electrode.

However, in the semiconductor device according to the present embodiment, two single diffusion break films may be formed instead of a double diffusion break film in the p region Rp in which a PMOS transistor is formed. Thus, a threshold voltage of the PMOS transistor may be stably controlled so that the semiconductor device may have high reliability and improved operating performance.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 1, 4B, and 5B. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 4Bis a cross-sectional view for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.FIG. 5Bis a cross-sectional view for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.FIG. 4Bis a cross-sectional view taken along line C-C′ ofFIG. 1, andFIG. 5Bis a cross-sectional view taken along line D-D′ ofFIG. 1.

Referring toFIGS. 1, 4B, and 5B, fin cut trenches Fct may be disposed on both sides of a third fin F3and a seventh fin F7. The fin cut trenches Fct may have bottom surfaces located at a lower level than a top surface of a substrate100. Unlike the grooves ofFIGS. 4A and 5A, the fin cut trenches Fct may be traces obtained by deeply removing fins. Although positions of the fin cut trenches Fct are illustrated on both sides of the third fin F3and the seventh fin F7for brevity, the present embodiment is not limited thereto.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 6 and 7. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 6is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure, andFIG. 7is a cross-sectional view taken along line B-B′ ofFIG. 6.

Referring toFIGS. 6 and 7, in the semiconductor device according to some exemplary embodiments of the present disclosure, a dummy gate electrode may be formed on a single diffusion break film600. For example, a third dummy gate electrode DG3and a fourth dummy gate electrode DG4may be formed not only in an n region Rn but also in a p region Rp. That is due to the fact that after the single diffusion break film600is formed, gate electrodes G2and G3and the third and fourth dummy gate electrodes DG3and DG4are formed.

A cross-sectional view taken along line A-A′ ofFIG. 6may be the same asFIG. 2.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 8 and 9. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 8is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure, andFIG. 9is a cross-sectional view taken along line B-B′ ofFIG. 8.

Referring toFIGS. 8 and 9, the semiconductor device according to some exemplary embodiments of the present disclosure may include a double diffusion break film in an n region Rn and include a single diffusion break film in a p region Rp.

In example embodiments, each of first to fourth cells C1to C4may have a p region Rp that is wider than an n region Rn. For example, an n region Rn of a third diffusion break structure B3may include both a third dummy gate electrode DG3and a fourth dummy gate electrode DG4. By contrast, a p region Rp of the third diffusion break structure B3may include only a single diffusion break film600, which extends from the third dummy gate electrode DG3in a second direction Y, and a third gate electrode G3may be formed to extend from the fourth dummy gate electrode DG4in the second direction Y and operate as a third cell C3. In this case, the third cell C3may have two third gate electrode electrodes G3. Naturally, the fourth dummy gate electrode DG4may continuously extend in the second direction Y in the n region Rn so that a dummy gate electrode may be formed even in the p region Rp.

A cross-sectional view taken along line A-A′ ofFIG. 8may be the same asFIG. 2.

The present embodiment may stably control a threshold voltage by using the single diffusion break film600instead of the double diffusion break film in the p region Rp. Further, a wide space margin may be obtained in the p region Rp, thereby improving operating characteristics of the semiconductor device.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 10 and 11. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 10is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure, andFIG. 11is a cross-sectional view taken along line B-B′ ofFIG. 10.

Referring toFIGS. 10 and 11, in a semiconductor device according to some exemplary embodiments of the present disclosure, a diffusion break film610may be disposed between dummy gate electrodes in a p region Rp.

Specifically, a fourth trench T4may be formed between a third dummy gate electrode DG3and a fourth dummy gate electrode DG4. The fourth trench T4may space a sixth fin F6and a seventh fin F7apart from each other in a first direction X. A lower portion of the fourth trench T4may be defined by side surfaces of the sixth fin F6and the seventh fin F7in the first direction X. A middle portion of the fourth trench T4may be defined by side surfaces of the third dummy gate electrode DG3and the fourth dummy gate electrode DG4. An upper portion of the fourth trench T4may be defined by a first interlayer insulating film510and a second interlayer insulating film520.

An insulating liner620may be formed along a sidewall of the fourth trench T4which is defined by the first interlayer insulating film510and the second interlayer insulating film520. The insulating liner620may be formed along the entire sidewall of the fourth trench T4, and a portion of the insulating liner620may be removed so that only a portion of the insulating liner620may remain. Accordingly, the insulating liner620may also remain on another sidewall of the fourth trench T4. Alternatively, the insulating liner620may be completely removed using an etching process and be absent.

The diffusion break film610may completely fill the fourth trench T4. Although the diffusion break film610is illustrated as a single film, the diffusion break film610may have a structure in which a plurality of films are stacked.

In the present embodiment, dummy gate electrodes may be formed in both a p region Rp and an n region Rn, and the diffusion break film610may then be formed only in the p region Rp. For example, a cross-sectional view taken along line A-A′ ofFIG. 10may be the same asFIG. 2. Thus, processes may be relatively simple. Accordingly, a semiconductor device having relatively high reliability may be provided.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 12 and 13. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 12is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure, andFIG. 13is a cross-sectional view taken along line B-B′ ofFIG. 12.

Referring toFIGS. 12 and 13, in the semiconductor device according to some exemplary embodiments of the present disclosure, first to fifth diffusion break structures B1to B5may include a single diffusion break film600not only in a p region Rp but also in an n region Rn. Further, only one single diffusion break film600in each of the fifth diffusion break structures B1to B5, not two single diffusion break films, may extend in a second direction Y.

In the present embodiment, since only one single diffusion break film600in each of the fifth diffusion break structures B1to B5is formed, the integration density of the semiconductor device may be improved. Furthermore, a threshold voltage of a transistor may be stably controlled by reducing a layout effect.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 1, 14, and 15. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 14is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure, andFIG. 15is a cross-sectional view taken along line E-E′ ofFIG. 14.

Referring toFIGS. 1, 14, and 15, in the semiconductor device according to some exemplary embodiments of the present disclosure, a third cell C3may include four third gate electrodes G3. A portion of a first contact410may be electrically connected to a first power rail P1through a third via V3. For example, a ground voltage GND may be provided to the first power rail P1. The first power rail P1may be electrically connected to an epitaxial layer heavily doped with P-type impurities. As an example, the first power rail P1may be electrically connected to the portion of the first contact410through the third via V3. A portion of the first contact410may be connected to a second interconnecting wire M2through a first via V1.

Similarly, a portion of a second contact411may be electrically connected to a second power rail P2through the third via V3. For example, a power supply voltage VCC or VDD may be provided to the second power rail P2. The second power rail P2may be electrically connected to an epitaxial layer heavily doped with N-type impurities. As an example, the second power rail P2may be electrically connected to the portion of the first contact410through the third via V3. A portion of the second contact411may be connected to the second interconnecting wire M2through the first via V1.

A gate contact420may be formed on the third gate electrode G3and connected to a first interconnecting wire M1through a second via V2.

A third interlayer insulating film540may be formed on a second interlayer insulating film520, and a fourth interlayer insulating film550may be formed on the third interlayer insulating film540. The first to third vias V1to V3may be formed through the third interlayer insulating film540, and the first interconnecting wire M1, the second interconnecting wire M2, the first power rail P1, and the second power rail P2may be formed in the fourth interlayer insulating film550.

The first interconnecting wire M1, the second interconnecting wire M2, the first power rail P1, and the second power rail P2may all be formed at the same level. The first to third vias V1to V3may also be formed at the same level under the first interconnecting wire M1, the second interconnecting wire M2, the first power rail P1, and the second power rail P2.

The first contact410, the second contact411, and the gate contact420may be formed at the same level under the first to third vias V1to V3. However, the present embodiment is not limited thereto.

Shapes of the first contact410, the second contact411, the gate contact420, the first interconnecting wire M1, and the second interconnecting wire M2may not necessarily be the same as shown in the drawings, but may be changed as needed.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 1 and 16. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 16is a cross-sectional view for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.FIG. 16is a cross-sectional view taken along line A-A′ ofFIG. 1.

Referring toFIGS. 1 and 16, a top surface of a second field insulating film201may be at the same level as top surfaces of a second fin F2and a third fin F3. Accordingly, bottom surfaces of a third dummy gate DG3and a fourth dummy gate DG4may also be planarly formed without steps. Bottom surfaces of a first dummy gate insulating film210, a first dummy work-function metal220, and a first dummy fill metal230in the third dummy gate DG3and the fourth dummy gate DG4may also be planarly formed.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIG. 17. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 17is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.

Referring toFIG. 17, from among first to fifth diffusion break structures B1to B5, a third diffusion break structure B3and a fourth diffusion break structure B4configured to define a third cell C3may have an MDB film structure, while the remaining first diffusion break structure B1, second diffusion break structure B2, and fifth diffusion break structure B5may simply have a double diffusion break film structure.

For example, the above-described layout effect may be even clearer as a distance between a gate electrode and a diffusion break structure becomes closer. Accordingly, only the third cell C3to which the layout effect may be clearly applied may adopt an MDB film structure so that a p region Rp may have not a double diffusion break film structure but a single diffusion break film structure.

Therefore, in the semiconductor device according to the present embodiment, the difficulty of a process of forming other cells may be reduced, and reliability of other regions may be increased, thereby improving operating characteristics of the entire device and, simultaneously, enabling stable control of a distribution of a threshold voltage of the third cell C3.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 18 and 19. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 18is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure, andFIG. 19is a cross-sectional view taken along line A-A′ ofFIG. 18.

Referring toFIGS. 18 and 19, the semiconductor device according to some exemplary embodiments of the present disclosure may further include a fifth cell C5.

The fifth cell C5may be a cell that is adjacent to or spaced apart from first to fourth cells C1to C4. The fifth cell C5may be included in an n region Rn and a p region Rp like the first to fourth cells C1to C4. A ninth fin F9and a tenth fin F10may be disposed in the fifth cell C5. The ninth fin F9may extend in an n region Rn in a first direction X, and the tenth fin F10may extend in a p region Rp in the first direction X. The ninth fin F9and the tenth fin F10may be spaced apart from each other in a second direction Y.

A fifth gate electrode G5may extend in the second direction Y to cross the ninth fin F9and the tenth fin F10on the ninth fin F9and the tenth fin F10.

In this case, the fifth gate electrode G5may have a first width W1in the first direction X, and first to fourth gate electrodes G1to G4of the first to fourth cells C1to C4may have a second width W2in the first direction X. The second width W2may be different from the first width W1. For example, the second width W2may be greater than the first width W1.

In this case, all dummy gate electrodes including a third dummy gate electrode DG3and a fourth dummy gate electrode DG4and a single diffusion break film600may have the second width W2. That is due to the fact that the dummy gate electrodes and the single diffusion break film600are determined using the same process as a process of patterning gate electrodes.

However, in the semiconductor device according to some exemplary embodiments of the present disclosure, widths of only gate electrodes, excluding the dummy gate electrodes and the single diffusion break film, may be controlled.

In the semiconductor device according to the present embodiment, widths of all gate electrodes of the first to fourth cells C1to C4may be controlled, thereby controlling threshold voltages and distributions thereof. For example, by controlling a width of a gate electrode in the first direction X, a channel length of the gate electrode may be controlled so that a threshold voltage of the gate electrode may be controlled.

Since a distribution of threshold voltage is reduced with an increase in the width of the gate electrode, the distribution of threshold voltage may be reduced by controlling the width of the gate electrode.

Accordingly, even if the semiconductor device according to the present embodiment adopts a single fin structure, a transistor having a stable distribution of threshold voltage may be implemented.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 20 and 21. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 20is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure, andFIG. 21is a cross-sectional view taken along line A-A′ ofFIG. 20.

Referring toFIGS. 20 and 21, in the semiconductor device according to some exemplary embodiments of the present disclosure, gate electrodes of only a third cell C3may be formed to have a second width W2, and gate electrodes of the remaining cells may be formed to have a first width W1. Further, only a diffusion break structure configured to define the third cell C3may adopt an MDB film, while the remaining diffusion break structures may adopt a double diffusion break film.

Therefore, in the present embodiment, the difficulty of a process of forming other cells may be reduced, and reliability of other regions may be increased, thereby improving operating characteristics of the entire device and, simultaneously, enabling stable control of a threshold voltage of the third cell C3.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 22 to 24. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 22is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.FIG. 23is a cross-sectional view taken along lines F-F′ and G-G′ ofFIG. 22.FIG. 24is a cross-sectional view taken along line B-B′ ofFIG. 22.

Referring toFIGS. 22 to 24, the semiconductor device according to some exemplary embodiments of the present disclosure may further include a fifth cell C5. A ninth fin F9and a tenth fin F10may be disposed in the fifth cell C5. The ninth fin F9may extend in an n region Rn in a first direction X, and the tenth fin F10may extend in a p region Rp in the first direction X. The ninth fin F9and the tenth fin F10may be spaced apart from each other in a second direction Y. A fifth gate electrode G5may extend in the second direction Y to cross the ninth fin F9and the tenth fin F10on the ninth fin F9and the tenth fin F10.

First to fifth diffusion break structures B1to B5of the semiconductor device according to some exemplary embodiments of the present disclosure may all have a double diffusion break film structure. Unlike in the fifth cell C5, a threshold voltage of a gate electrode of each of the first to fourth cells C1to C4may be reduced by using a gate electrode structure in the p region Rp.

Specifically, in the fifth cell C5, the fifth gate electrode G5may be formed on the ninth fin F9and the tenth fin F10. The fifth gate electrode G5may include a second gate insulating film1310, a third work-function metal1320, and a second fill metal1330in the n region Rn. A second capping film1340may be formed on the fifth gate electrode G5, and second spacers1350may be formed on side surfaces of the fifth gate electrode G5and the second capping film1340.

Third source and drain regions1400may be formed in both sides of the fifth gate electrode G5in the n region Rn, and a third contact1410may be formed through a first interlayer insulating film510and a second interlayer insulating film520and in contact with the third source and drain regions1400.

The fifth gate electrode G5may include the second gate insulating film1310, the third work-function metal1320, a fourth work-function metal1325, and the second fill metal1330in the p region Rp. The second capping film1340may be formed on the fifth gate electrode G5, and the second spacers1350may be formed on the side surfaces of the fifth gate electrode G5and the second capping film1340.

Fourth source and drain regions1401may be formed in both sides of the fifth gate electrode G5in the p region Rp, and a fourth contact1411may be formed through the first interlayer insulating film510and the second interlayer insulating film520and in contact with the fourth source and drain regions1401.

In this case, the third work-function metal1320may have a first thickness a1in both the n region Rn and the p region Rp.

In contrast, the first to fourth cells C1to C4may have a lower threshold voltage than that of the fifth cell C5in the p region Rp. To this end, a first work-function metal320of each of the first to fourth cells C1to C4may have a second thickness a2which is different from the first thickness a1. For example, the second thickness a2may be greater than the first thickness a1.

In the present embodiment, a structure of a gate electrode in the p region Rp may be changed to adjust a threshold voltage of the gate electrode, thereby facilitating the stabilization of a distribution of the threshold voltage. As a result, even if the semiconductor device has a single fin structure, a threshold voltage may be stabilized so that the semiconductor device may have improved operating characteristics.

In another case, the semiconductor device according to some exemplary embodiments of the present disclosure may adjust a concentration of a dipole material in a gate insulating film and reduce a threshold voltage of a p region Rp. In this case, the above-described separate process of adjusting a thickness may not be needed. Naturally, in the semiconductor device according to some exemplary embodiments of the present disclosure, a threshold voltage may be adjusted by adjusting both a concentration and a thickness.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 22 and 25. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 25is a cross-sectional view for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.FIG. 25is a cross-sectional view taken along line B-B′ ofFIG. 22.

Referring toFIGS. 22 and 25, the semiconductor device according to some exemplary embodiments of the present disclosure may adjust a threshold voltage of a p region Rp of a third cell C3and may not adjust a threshold voltage in other cells. For example, a first work-function metal320of each of the first, second, and fourth gate electrodes G1, G2, and G4may have a first thickness a1and a first work-function metal320of the third gate electrode G3may have a second thickness a2greater than the first thickness a1.

Therefore, in the present embodiment, the difficulty of a process of forming other cells may be reduced, and reliability of other regions may be increased, thereby improving operating characteristics of the entire device and, simultaneously, enabling stable control of a threshold voltage of the third cell C3.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 26 to 28. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 26is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.FIG. 27is a cross-sectional view taken along lines F-F′ and G-G′ ofFIG. 26.FIG. 28is a cross-sectional view taken along line B-B′ ofFIG. 26.

Referring toFIGS. 26 to 28, the semiconductor device according to some exemplary embodiments of the present disclosure may further include a fifth cell C5. A ninth fin F9and a tenth fin F10may be disposed in the fifth cell C5. The ninth fin F9may extend in a first direction X in an n region Rn, and a tenth fin F10may extend in the first direction X in a p region Rp. The ninth fin F9and the tenth fin F10may be spaced apart from each other in a second direction Y. A fifth gate electrode G5may extend in the second direction Y to cross the ninth fin F9and the tenth fin F10on the ninth fin F9and the tenth fin F10.

The fifth gate electrode G5of the fifth cell C5may have a first width W1in the first direction X, and a third work-function metal1320may have a first thickness a1.

By contrast, gate electrodes of first to fourth cells C1to C4may have a second width W2greater than the first width W1in the first direction X, and a first work-function metal320may have a second thickness a2greater than the first thickness a1. That is, the semiconductor device of the present embodiment may control a threshold voltage by adjusting a channel length using a width and adjusting a thickness of a work-function metal of a gate electrode. Thus, a distribution in threshold voltage of the semiconductor device may be stabilized.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIGS. 29 and 30. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 29is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.FIG. 30is a cross-sectional view taken along line B-B′ ofFIG. 29.

Referring toFIGS. 29 and 30, in the semiconductor device according to some exemplary embodiments of the present disclosure, only in a third cell C3, a width of a third gate electrode G3may be controlled to be a second width W2, and a thickness of a first work-function metal320may be controlled to be a second thickness a2so that a threshold voltage may be stably controlled. For example, a width of each of the first, second, and fourth gate electrodes G1, G2, and G4may have a first width W1and a width of the third gate electrode G3may have the second width W2greater than the first width W1. Also, a thickness of a first work-function metal320of each of the first, second, and fourth gate electrodes G1, G2, and G4may have a first thickness a1and a first work-function metal320of the third gate electrode G3may have the second thickness a2greater than the first thickness a1.

Therefore, in the present embodiment, the difficulty of a process of forming other cells may be reduced, and reliability of other regions may be increased, thereby improving operating characteristics of the entire device and, simultaneously, enabling stable control of a threshold voltage of the third cell C3.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIG. 31. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 31is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.

Referring toFIG. 31, the semiconductor device according to some exemplary embodiments of the present disclosure may include a 3-1stfin F3-1. For example, a third cell C3may have a relatively high distribution in threshold voltage due to a layout effect, and a transistor may be formed using a plurality of fins instead of a single fin to stabilize a distribution of an n region Rn.

Accordingly, the present embodiment may reinforce a specific region (i.e., the n region Rn) of the weak third cell C3with the plurality of fins while taking advantage of a single fin in other cells, thereby improving operating characteristics of the entire device.

AlthoughFIG. 31illustrates an example in which the 3-1stfin F3-1is located adjacent to a p region Rp for brevity, the present embodiment is not limited thereto.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIG. 32. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 32is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.

Referring toFIG. 32, the semiconductor device according to some exemplary embodiments of the present disclosure may include a 7-1stfin F7-1. That is, a third cell C3may have a relatively high distribution in threshold voltage due to a layout effect, and a transistor may be formed using a plurality of fins instead of a single fin to stabilize a distribution of a p region Rp.

Accordingly, the present embodiment may reinforce a specific region (i.e., the p region Rp) of the weak third cell C3with the plurality of fins while taking advantages of a single fin in other cells, thereby improving operating characteristics of the entire device.

Hereinafter, a semiconductor device according to some exemplary embodiments of the present disclosure will be described with reference toFIG. 33. The description of components of the present exemplary embodiment which are the same as those of the above-described exemplary embodiment will be omitted or briefly described.

FIG. 33is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.

Referring toFIG. 33, the semiconductor device according to some exemplary embodiments of the present disclosure may include a 3-1stfin F3-1and a 7-1stfin F7-1. For example, since a third cell C3has a relatively high distribution in threshold voltage due to a layout effect, a transistor may be formed using a plurality of fins instead of a single fin.

Accordingly, the present embodiment may reinforce the weak third cell C3with the plurality of fins while taking advantages of a single fin in other cells, thereby improving operating characteristics of the entire device.