Device configured to have a nanowire formed laterally between two electrodes and methods for forming the same

A device configured to have a nanowire formed laterally between two electrodes includes a substrate and an insulator layer established on at least a portion of the substrate. An electrode of a first conductivity type and an electrode of a second conductivity type different than the first conductivity type are established at least on the insulator layer. The electrodes are electrically isolated from each other. The electrode of the first conductivity type has a vertical sidewall that faces a vertical sidewall of the electrode of the second conductivity type, whereby a gap is located between the two vertical sidewalls. Methods are also disclosed for forming the device.

BACKGROUND

The present disclosure relates generally to devices configured to have a nanowire formed laterally between two electrodes, and methods for forming the same.

Since the inception of semiconductor technology, a consistent trend has been toward the development of smaller device dimensions and higher device densities. As a result, nanotechnology has seen explosive growth and generated considerable interest. Nanotechnology is centered on the fabrication and application of nano-scale structures, or structures having dimensions that are often 50 to 100 times smaller than conventional semiconductor structures. Nanowires are included in the category of nano-scale structures.

Nanowires are wire-like structures having diameters on the order of about 1 nm to about 100 nm. Nanowires are suitable for use in a variety of applications, including functioning as conventional wires for interconnection applications or as semiconductor devices. While holding much promise, the practical application of nanowires has been somewhat limited. In particular, providing nanowires, especially laterally positioned nanowires, that can be fabricated in production quantities for a reasonable cost has proven difficult. This may be due, at least in part, to the difficulty involved in producing device platforms that allow for the self-assembly and integration of the nanowire. One difficulty that may be encountered in producing such device platforms is making good electrical contact (using electrodes, connections, or the like) to the nanowires in order to bring electrical signals into the nanowires. Another difficulty that may be encountered in producing such device platforms is forming electrodes having different conductivity types.

Techniques that include suspending nanowires in a solvent, dispersing them on a device platform, and making electrical contacts are generally slow and potentially unreliable processes.

Another potential problem with many nanowire integration techniques is that contamination may result from additional processing.

SUMMARY

A device configured to have a nanowire formed laterally between two electrodes is disclosed herein. The device includes a substrate and an insulator layer established on at least a portion of the substrate. An electrode of a first conductivity type and an electrode of a second conductivity type different than the first conductivity type are established at least on the insulator layer. The electrodes are electrically isolated from each other. The electrode of the first conductivity type has a vertical sidewall that faces a vertical sidewall of the electrode of the second conductivity type, whereby a gap is located between the two vertical sidewalls.

A method for forming a device configured to have a nanowire formed laterally between two electrodes is also disclosed herein. The method includes forming an electrode of a first conductivity type from a silicon layer of a silicon-on-insulator substrate, where the silicon layer has the first conductivity type. A portion of an insulator layer of the silicon-on-insulator substrate is removed so that at least a portion of a substrate surface is exposed. An epitaxial layer is established on at least the exposed portion. The epitaxial layer of the second conductivity type forms an electrode of the second conductivity type that is electrically isolated from the electrode of the first conductivity type.

DETAILED DESCRIPTION

Embodiments of the device disclosed herein are advantageously capable of having nanowire(s) grown laterally between two electrodes. In an embodiment, the device includes at least two electrically isolated electrodes, each of which may have a different conductivity type (e.g., p-type and n-type electrodes). Growth of the nanowire is initiated at one of the electrodes, and a connection is formed at the other of the electrodes. The electrodes of different conductivity types are advantageously capable of having nanowires with multiple segments having different conductivity types or different materials (e.g., different from other segments and/or different from the electrode materials) formed therebetween. The connection between the nanowire and the electrodes and/or between the various segments of the nanowire may advantageously be electrically useful (e.g., an ohmic connection, a junction (i.e., a diode), or the like).

Referring now toFIG. 1A, an embodiment of the method for forming the device10(an embodiment of which is shown inFIG. 1E, another embodiment of which is shown inFIG. 1F, and still another embodiment of which is shown inFIG. 1H) includes establishing an insulator layer14on a substrate12so that a portion16of the substrate surface remains exposed.

In an embodiment, the substrate12is silicon (Si) cut or polished with the surface plane being a (110) crystal lattice plane. Such a substrate12is referred to as a (110) oriented Si substrate. As used herein, the (110) plane is considered to be horizontally oriented with respect to the Cartesian coordinate system. The (110) oriented substrate12further has (111) planes of the Si crystal lattice, at least some of which are approximately perpendicular to and intersect with the horizontally oriented (110) surface of the substrate12. These intersecting (111) planes are referred to herein as vertically oriented (111) planes or surfaces, noting that the (111) planes are approximately vertically oriented relative to the horizontal (110) surface of the substrate12.

As used herein, the term “horizontal” generally refers to a direction or a plane that is parallel with a surface of the substrate12or wafer, while the term “vertical” generally refers to a direction or plane that is substantially or approximately perpendicular to the substrate surface. The specific use of the terms “horizontal” and “vertical” to describe relative characteristics is to facilitate discussion and is not intended to limit embodiments of the present disclosure.

Any suitable insulator layer14may be used. In a non-limitative example embodiment, the insulator layer14is an oxide. An example of an oxide includes, but is not limited to thermally grown silicon dioxide. Non-limitative examples of other suitable materials for the insulator layer14include nitrides, oxynitrides, or the like, or combinations thereof.

The insulator layer14may be established using any suitable growth or deposition technique. A thermal oxide insulator layer may be formed by the oxidation of silicon, which forms silicon dioxide. Various oxide and nitride insulator layers may be established via deposition techniques which include, but are not limited to low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), or any other suitable chemical or physical vapor deposition techniques. In one embodiment, the insulator layer14is established as two separate layers having the exposed portion16of the substrate surface therebetween. In another embodiment, the insulator layer14is grown or deposited as a substantially continuous layer, and is then patterned (e.g., via photolithography) and etched (e.g., via dry or wet chemical etching) to expose the portion16of the substrate surface (as shown inFIG. 1A).

Referring now toFIG. 1B, an epitaxial layer18of a first conductivity type is established on at least the exposed portion16, and in some embodiments, on at least a portion of the insulator layer14adjacent to the exposed portion16. It is to be understood that the exposed portion16acts as a seed for the growth of the epitaxial layer18of the first conductivity type. Generally, the epitaxial layer18is established via thermal chemical vapor deposition. A non-limitative example of the epitaxial layer18includes silicon, and non-limitative examples of the first conductivity type include p-type conductivity or n-type conductivity.

As the epitaxial layer18grows, it may be doped with a dopant that is capable of introducing the first conductivity type to the epitaxial layer18. Dopants for achieving p-type conductivity include, but are not limited to boron, other like elements, or combinations thereof; and dopants for achieving n-type conductivity include, but are not limited to phosphorus, arsenic, antimony, other like elements, or combinations thereof.

The epitaxial layer18of the first conductivity type is established to a predetermined height that is determined, at least in part, by a desirable height for an electrode18′ of the first conductivity type (shown inFIG. 1B). Generally, the predetermined height is higher than a thickness of the insulator layer14. Furthermore, the epitaxial layer18of the first conductivity type may also be established so that it expands laterally across the portion(s) of the insulator layer14adjacent to the exposed portion16. This lateral epitaxial overgrowth continues until the desirable dimensions (e.g., predetermined height, desirable distance over the insulator layer14, etc.) of the epitaxial layer18are achieved.

It is to be understood that the epitaxial layer18of the first conductivity type functions as an electrode18′ of the first conductivity type. Referring now toFIG. 1C, an embodiment of the method includes removing a portion of the epitaxial layer18of the first conductivity type to re-expose a portion16′ of the substrate surface. This forms an electrode18′ of the first conductivity type that is electrically isolated from the substrate12, and any circuitry located therein/thereon.

FIG. 1Ddepicts the establishment of a masking layer15on at least the electrode18′ of the first conductivity type. It is to be understood that the masking layer15aids in protecting the electrode18′ of the first conductivity type during subsequent formation of the epitaxial layer20(shown inFIG. 1E). It is to be understood that the masking layer15may also be established on the insulator layer14. A non-limitative example of the masking layer15is an oxide layer.

Referring now toFIG. 1E, an epitaxial layer20of a second conductivity type is established on the re-exposed portion16′ of the substrate12, and in some embodiments on portion(s) of the insulator layer14adjacent to the re-exposed portion16′. It is to be understood that the re-exposed portion16′ also acts as a seed for the growth of the epitaxial layer20of the second conductivity type. In an embodiment, the epitaxial layer20is established via thermal chemical vapor deposition, and as it grows, it is doped with a dopant capable of introducing the second conductivity type to the epitaxial layer20. A non-limitative example of the epitaxial layer20includes silicon, and non-limitative examples of the second conductivity type include n-type conductivity or p-type conductivity.

It is to be understood that the first and second conductivity types may be the same or different. In a non-limitative example, the epitaxial layer18of the first conductivity type has p-type conductivity, and the epitaxial layer20of the second conductivity type has n-type conductivity, or vice versa. In other embodiments, both the first and second conductivity types have p-type conductivity or n-type conductivity.

The epitaxial layer20of the second conductivity type is established to a predetermined height that is determined, at least in part, by a desirable height for an electrode20′ (shown inFIGS. 1E and 1H),20″ (shown inFIG. 1F) of the second conductivity type. Similar to the epitaxial layer18of the first conductivity type, the epitaxial layer20of the second conductivity type may expand laterally across the portion(s) of the insulator layer14adjacent to the re-exposed portion16′. This lateral epitaxial overgrowth continues until the desirable dimensions (e.g., predetermined height, desirable distance over the insulator layer14, etc.) of the epitaxial layer20are achieved. It is to be understood, however, that the epitaxial layers18,20remain electrically isolated from each other (generally, with at least a portion of the insulator layer14therebetween).

The epitaxial layer20of the second conductivity type functions as an electrode20′ (FIGS. 1E and 1H),20″ (FIG. 1F) of the second conductivity type. As depicted inFIG. 1E, the electrode20′ of the second conductivity type is established on the re-exposed portion16′ of the substrate12, and thus may be electrically connected to any circuitry located in or on the substrate12.

Referring now toFIG. 1F, an embodiment of the method may further include removing a portion of the epitaxial layer20of the second conductivity type to again expose the portion16″ of the substrate surface. It is to be understood that, in an embodiment, some of the epitaxial layer20established on the insulator layer14may also be removed. Removal of the portion(s) of the epitaxial layer20may be accomplished by directional dry etching or wet chemical etching. After removal, an electrode20″ of the second conductivity type is formed that is electrically isolated from the substrate12and any circuitry located therein/thereon.

FIGS. 1E and 1Falso depict the removal of the masking layer15. It is to be understood that the masking layer15is removed from the electrode18′ after the epitaxial layer20of the second conductivity type is formed. Removal of the masking layer15may be accomplished by wet chemical etching processes, dry etching processes (e.g., directional dry etching or isotropic plasma etching), or combinations thereof.

In an alternate embodiment of the method, after the epitaxial layer18of the first conductivity type is established (a non-limitative example of which is shown inFIG. 1B), a portion of the epitaxial layer18may be removed so that another portion of the epitaxial layer18remains on the insulating layer14, on the exposed portion16of the substrate surface, or on both the layer14and the exposed portion16(as shown inFIG. 1G). It is to be understood that if the epitaxial layer18remains on the insulating layer14(and not on the substrate12), an electrode18′ that is electrically isolated from the substrate12is formed (not shown inFIG. 1G); and that if the epitaxial layer18remains on the exposed portion16, an electrode18′″ that is configured to be electrically connected to the substrate12is formed (as shown inFIG. 1G).

In any of the embodiments disclosed herein, it is to be understood that the epitaxial layer18may be established at a desirable height, length, or configuration so that removal of portions of the layer18may be unnecessary.

As depicted inFIG. 1G, a masking layer15may be established on the electrode18′″ for protection of the electrode18′″ during subsequent processing.

FIG. 1Galso depicts the removal of a second portion of the insulator layer14so that a second portion17of the substrate surface is exposed. Removal of the second portion of the insulating layer14may be accomplished using those techniques that are suitable for removing the first portion of the insulator layer14. It is to be understood that the second portion17is formed so that it is isolated from the first portion16.

Referring now toFIG. 1H, an epitaxial layer20of the second conductivity type is established in the second portion17, and optionally on portions of the insulator layer14adjacent to the second portion17. The epitaxial layer20of the second conductivity type forms the electrode20′, which is electrically isolated from the epitaxial layer18and which may be electrically connected to the substrate12. The device10shown inFIG. 1Hhas both the electrode18′″ of the first conductivity type and the electrode20′ of the second conductivity type configured to be electrically connected to the substrate12. It is to be understood that the electrodes18′″,20′ are connected to respective first and second regions of substrate12, and that those regions are electrically isolated from each other.

The epitaxial layer20as shown inFIG. 1Hmay also be partially removed (as described herein) to re-expose the second portion17and to form an electrode20″ (not shown inFIG. 1H) that is established on the insulator layer14and is electrically isolated from the substrate12.

The embodiments of the device10(shown inFIGS. 1E,1F and1H) each has an electrode pair, including one electrode18′,18′″ of the first conductivity type and one electrode20′,20″ of the second conductivity type. The electrode18′,18′″ of the first conductivity type has a vertical sidewall26that faces a vertical sidewall28of the electrode20′,20″ of the second conductivity type. A gap30formed between these sidewalls26,28may have one or more nanowires grown laterally therebetween.

FIGS. 2A through 2Fdepict an embodiment of the method for forming a device10using a silicon-on-insulator (SOI) substrate. As depicted, a pre-purchased or pre-formed SOI substrate includes a substrate12, insulator layer14, and a silicon layer18″ of the first conductivity type. In an embodiment, one or both of the silicon layer18″ and the substrate12of the SOI substrate preferably has (110) crystallographic orientation.

FIG. 2Bdepicts the formation of the electrode18′ of the first conductivity type from the silicon layer18″ of the first conductivity type. Generally, the electrode18′ of the first conductivity type is formed by patterning (e.g., via photolithography) a desirable electrode design in the silicon layer18″ of the first conductivity type, and etching (e.g., via dry etching, wet chemical etching, or combinations thereof) the silicon layer18″ of the first conductivity type to form the electrode18′.

Referring now toFIG. 2C, a portion of the insulator layer14of the SOI substrate is removed to expose a portion16of the substrate surface. The portion of the insulator layer14may be removed by patterning (e.g., via photolithography) a predetermined design on the insulator layer14, and etching (e.g., via dry or wet chemical etching) the insulator layer14to expose the portion16of the substrate surface.

Establishment of the masking layer15on at least the electrode18′ of the first conductivity type is shown inFIG. 2D. As previously described, the masking layer15aids in protecting the electrode18′ of the first conductivity type during subsequent formation of the epitaxial layer20(shown inFIG. 2E).

Referring now toFIG. 2E, an epitaxial layer20of a second conductivity type is established on the exposed portion16of the substrate12, and on at least a portion of the insulator layer14adjacent to the exposed portion16. It is to be understood that the epitaxial layer20of the second conductivity type is established so that it is electrically isolated from the electrode18′ of the first conductivity type. As previously described hereinabove, the exposed portion16acts as a seed for the growth of the epitaxial layer20of the second conductivity type, which may be grown vertically and optionally laterally to predetermined dimensions. Furthermore, the epitaxial layer20may be doped with a dopant configured to introduce the second conductivity type to the epitaxial layer20during growth (e.g., during thermal chemical vapor deposition).

The epitaxial layer20of the second conductivity type functions as the electrode20′ (shown inFIG. 2E),20″ (shown inFIG. 2F) of the second conductivity type. As depicted inFIG. 2E, the electrode20′ of the second conductivity type is established in contact with the substrate12, and thus may be electrically connected to any circuitry located in or on the substrate12.

FIG. 2Fdepicts an embodiment of the device10in which a portion of the epitaxial layer20of the second conductivity type is removed to re-expose the portion16′ of the substrate surface. Removal of the portion(s) of the epitaxial layer20may be accomplished by methods previously described herein. After removal, an electrode20″ of the second conductivity type is formed that is electrically isolated from the substrate12and any circuitry located therein/thereon.

Referring now toFIG. 2G, an alternate embodiment of the device10is depicted. In this embodiment, the epitaxial layer20is established so that it does not grow laterally on portion(s) of the insulator layer14. As depicted, the electrode20′ that is formed from the epitaxial layer20is configured to be electrically connected to the substrate12and any circuitry located therein/thereon.

FIGS. 2E,2F, and2G also depict the removal of the masking layer15. The masking layer15is removed (via any suitable process described herein) after the epitaxial layer20of the second conductivity type is formed.

The devices10shown inFIGS. 2E,2F and2G are capable of having a nanowire formed in a gap30thereof. Similar to the devices shown inFIGS. 1E and 1F, the electrode18′ of the first conductivity type has a vertical sidewall26that faces a vertical sidewall28of the electrode20′,20″ of the second conductivity type to form the gap30.

Referring now toFIGS. 3A through 3G, another embodiment of the method for forming the device10is depicted. As shown inFIG. 3A, in this embodiment, two electrically isolated electrodes18′ of the first conductivity type have been formed in the silicon layer18″ of an SOI substrate. It is to be understood that the embodiment shown in theFIG. 3series may also have the electrodes18′,18′″ of the first conductivity type formed via an epitaxial layer18as described in reference to theFIG. 1series.

Referring now toFIG. 3B, a masking layer15is established on the electrodes18′ of the first conductivity type and optionally on the insulator layer14. It is to be understood that if the masking layer15is formed of a thermal oxide (e.g., silicon dioxide), it may substantially blend with the insulator layer14, such that there is substantially no appreciable difference in the thickness of the originally established insulator layer14. As a non-limitative example, the thickness of the insulator layer14may increase by about 2 nm or 3 nm when a thermal oxide masking layer15is established thereon. It is to be further understood that if the masking layer15is formed of a non-thermal oxide (e.g., LPCVD oxide, LPCVD nitride, PECVD oxide, PECVD nitride, APCVD oxide, PECVD oxynitride, or the like), it may have a substantially uniform thickness over both the electrodes18′ of the first conductivity type and the insulator layer14, thereby increasing the thickness of the insulator layer14by the thickness of the established masking layer15(one non-limitative example of the masking layer15thickness ranges from about 5 nm to about 50 nm).

As depicted inFIG. 3C, this embodiment of the method then includes, in addition to removing a portion of the insulator layer14, also removing a portion of the masking layer15to expose a portion16of the substrate12. Generally, the portion(s) of the layer(s)14,15removed are located near the electrically isolated electrodes18′ of the first conductivity type. In a non-limitative example, the portion(s) of the layer(s)14,15removed are located between the electrically isolated electrodes18′ of the first conductivity type. It is to be understood that after removal, enough of the insulator layer14and masking layer15(if established on the insulator layer14) should remain so that the electrically isolated electrodes20″ (shown inFIGS. 3F-3G) of the second conductivity type may be formed thereon.

Removal of the layer(s)14,15to expose the portion16of the substrate surface may be accomplished by patterning a predetermined design, and etching the layer(s)14,15. It is to be understood that the layer(s)14,15are etched so that the surface of the substrate12is exposed. In a non-limitative example, the predetermined design is patterned via photolithography, and the layer(s)14,15are etched via dry etching or wet chemical etching.

Once the portion16of the substrate surface is exposed, the epitaxial layer20of the second conductivity type is established on the portion16and on portions of the layers14,15adjacent to the portion16, as shown inFIG. 3D. As previously described, the epitaxial layer20may be established vertically (i.e., to a predetermined thickness) and laterally (i.e., extending a predetermined distance over the layers14,15) using thermal chemical vapor deposition and doping. Furthermore, the epitaxial layer20of the second conductivity type is electrically isolated from each of the electrodes18′ of the first conductivity type.

Referring now toFIG. 3E, an optional oxide layer22is established on the masking layer15, the epitaxial layer20of the second conductivity type, and on any exposed portions of the insulator layer14. Plasma enhanced chemical vapor deposition (PECVD) is a non-limitative example of a method that is suitable for establishing the oxide layer22.

FIG. 3Fdepicts the removal of a portion of the oxide layer22(if present) and a portion of the epitaxial layer20of the second conductivity type so that the portion16′ of the substrate surface is re-exposed. The removal of these portions forms two electrodes20″ of the second conductivity type that are electrically isolated from each other, from the electrodes18′ of the first conductivity type, and from the substrate12.FIG. 3Gdepicts the removal of the remaining oxide layer22(if present) and the masking layer15(that remains uncovered by the electrodes of the second conductivity type20″), thereby exposing the electrodes18′ of the first conductivity type and the electrodes20″ of the second conductivity type.

The device10shown inFIG. 3Ghas two electrode pairs, each pair including one electrode18′ of the first conductivity type and one electrode20″ of the second conductivity type. The area between respective vertical sidewalls26,28of the electrodes18′,20″ in a pair is the gap30, which is configured to have nanowire(s) grown laterally therein.

Referring now toFIGS. 4 and 5together, embodiments of the device10similar to the device10shown inFIG. 1Eand inFIG. 3Gare respectively shown. Each of the devices10generally includes the substrate12, the insulator layer14, and one or more pairs of electrodes18′,20′ (shown inFIG. 4) or18′,20″ (shown inFIG. 5), each electrode18′,20′,20″ having a different conductivity type than the other electrode20′,20″,18′ in each pair. The electrode18′ of the first conductivity type has the vertical sidewall26that faces the vertical sidewall28of the electrode20′,20″ of the second conductivity type. The gap30formed between these sidewalls26,28may have one or more nanowires32grown laterally therebetween.

The nanowire32may be formed via any suitable method. A non-limitative example of forming a lateral nanowire32is described in U.S. patent application Ser. No. 10/738,176, filed on Dec. 17, 2003 (U.S. Publication No. 2005/0133476 A1, published Jun. 23, 2005), the specification of which is incorporated herein by reference. Other example methods for forming lateral nanowires32are described in “Ultrahigh-density silicon nanobridges formed between two vertical silicon surfaces” by Islam et al., published in 2004 in volume 14 ofNanotechnologyat pages L5-L8; and “A novel interconnection technique for manufacturing nanowire devices” by Islam et al., published in 2005 in volume 80 ofAppl. Phys. Aat pages 1133-1140.

In the non-limitative example embodiment shown inFIG. 4, the nanowire32and electrodes18′,20′ form a second conductivity type-second conductivity type-first conductivity type-first conductivity type structure, where the nanowire32has a second conductivity type segment CT2(adjacent the second conductivity type electrode20′) and a first conductivity type segment CT1(adjacent the first conductivity type electrode18′). A non-limitative example of such a structure is a p-type-p-type-n-type-n-type (p-p-n-n) structure, which has a p-p junction, a p-n junction, and an n-n junction. The second conductivity type segment CT2of the nanowire32is grown from the electrode20′ of the second conductivity type. During growth of the nanowire32, the second conductivity type segment CT2may be stopped, and a first conductivity type segment CT1may be grown from the second conductivity type segment CT2. In the embodiment shown inFIG. 4, the first conductivity type segment CT1forms a connection with the electrode18′ of the first conductivity type.

FIG. 5shows a non-limitative example embodiment of at least a nanowire32grown in the gap30between each of the two electrode pairs (where each pair includes one electrode18′ of the first conductivity type and one electrode20″ of the second conductivity type). In the first electrode pair A, the nanowire32and electrodes18′,20″ form a first conductivity type-first conductivity type-second conductivity type-second conductivity type structure, where the nanowire32has a first conductivity type segment CT1(adjacent the first conductivity type electrode18′) and a second conductivity type segment CT2(adjacent the second conductivity type electrode20″). A non-limitative example of such a structure is a p-p-n-n structure, having similar junctions to those described in reference toFIG. 4. In the second electrode pair B, the nanowire32and the electrodes20″,18′ form a second conductivity type-first conductivity type-second conductivity type-first conductivity type structure, wherein the nanowire32has a first conductivity type segment CT1(adjacent the second conductivity type electrode20″) and a second conductivity type segment CT2(adjacent the first conductivity type electrode18′). A non-limitative example of such a structure is an n-p-n-p structure, having an n-p junction, a p-n junction, and an n-p junction.

It is to be understood that segments CT1, CT2described herein may also be formed of different materials. Further, it is to be understood that a junction formed between two segments CT1, CT2of different materials is known as a heterojunction.

However, it is to be understood that in the embodiments disclosed herein, any desirable nanowire(s)32may be formed in the gap30. The nanowire(s)32may be formed having any number of segments formed of any suitable materials and/or having any desirable conductivity type. Furthermore, the nanowire(s)32may have any desirable number of junctions (e.g., p-n junction, or the like) formed therein. It is to be further understood that the number of first conductivity type-second conductivity type junctions may be dependent, at least in part, on the spacing between the electrodes18′,18′″,20′,20″ and the conductivity type of the electrodes18′,18′″,20′,20″.