Programmable output buffer

A programmable output buffer providing variable drive strength and slew rate for a given noise limit that includes a driver stage that generates the output of the buffer and a plurality of selectively enabled switching elements, at least a predriver stage providing a plurality of selectable switching elements that enables the selected drive stage switching elements, and a selection means that enables the required predriver switching elements in the desired sequence to provide the desired drive strength and slew rate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to an output buffer and, more particularly, a programmable output buffer with variable driving strengths and variable slew rate.

2. Description of the Related Art

Output buffers in CMOS integrated circuits are used to couple data and control signals to external pins that need to drive different types of load, typically capacitive in nature, hence the output transition timing are dependent on the capacitance value of the load and the driving strength of output buffer. For driving a large capacitive load, the output buffer needs to have larger output drive strength that allows larger current to be sinked and sourced by the load for smaller output transition times. A smaller drive strength would increase the output transition times. On the other hand for a small capacitive load, the output buffer requires only a small output drive strength, and a higher drive strength buffer driving a small load would generate large transient currents resulting in large undesired ground and power bounce in the supply rails and ringing in the system. Also, it dissipates extra power that must be avoided as integrated circuits become smaller and faster. Therefore, an output buffer with programmable driving strength is required such that a desirable output drive strength can be selected depending on the load attached to the output pin. Further, a slew rate limit option is implemented in an output buffer that allows it to operate in slow systems with low noise and ringing.

FIG. 1shows an embodiment in accordance with the U.S. Pat. No. 5,926,651. In this circuit, predrivers made of transistors K34, K35, K36, K37and K38control the pull-up drive strength. Switching on transistor K31gives one value of drive strength (say KX), switching on transistor K32gives another drive strength (say KY) while switching on both transistors K31and K32sets the output buffer with a different drive strength (KX+KY). Thus, the user can select one of the three different driving strengths. Also, the circuit provides variable slew rate for each driving strength by controlling the speed of the switching of driver transistors K31and K32. For each of the driving strength, two slew rate variations are available.

In all such circuits, the maximum noise is generated for higher driving strengths in a fast slew rate option since larger currents are sinked and sourced. As driving strength is reduced, the output delays degrade and the noise reduces since now smaller currents are sourced and sinked. Whereas in case of a slow slew rate the output delays further deteriorate.

This implies that the output delays and supply noise vary widely for various drive strengths and slew variations, and that for lower driving strengths the delays are worse while noise is much lower than the maximum noise that the system can tolerate.

BRIEF SUMMARY OF THE INVENTION

The disclosed embodiments of the invention provide output delays for all driving strengths comparable to the smallest delay that occurs for maximum driving strength without generating any extra noise and to minimizing the noise generated for higher driving strengths. In addition, the invention controls output delays by optimizing delays and noise for various driving strengths and slew rates. The invention further provides, for different driving strengths and slew rates, an optimal balance between the output delays and the noise generated.

For example, in case of lower driving strengths, the output delays and noise can be optimized by speeding up the voltage transitions at the gate of driver transistors while allowing the noise to rise up to the maximum tolerable limits, which would make the output delays for all driving strengths comparable to the smallest delay that occurs for maximum driving strength. This is done at the cost of some extra noise generation at the supply rails but the noise for lower driving strengths will still remain lesser than the maximum noise that is produced with highest driving strength. In slow slew option too, the output delays can be optimized by speeding up operation for lower driving strengths while maintaining the noise at lower levels.

Accordingly, the invention provides a programmable output buffer providing variable drive strength and slew rate for a given noise limit that includes a driver stage that generates the output of the buffer and includes a plurality of selectively enabled switching elements; a predriver stage providing a plurality of selectable switching elements that enables the selected drive stage switching elements; and a selection circuit that enables the required predriver switching elements in the desired sequence to provide the desired drive strength and/or slew rate.

The number of selected driver stage switching elements is determined by the required drive strength and their switching sequence is controlled to optimize the switching noise and delay.

The number and sequence of selected switching elements in the predriver stage is determined by the combination of the desired drive strength and/or slew rate.

The selection circuit is in one embodiment a bit pattern generator.

The predriver stage comprises a pull down predriver stage driving the pull down switching elements of the driver stage and a pull up predriver stage driving the pull up switching elements of the driver stage.

The noise includes ground bounce and supply bounce noise.

The sequential turning on of selected elements is achieved by selecting appropriate paths incorporating different delay elements.

The pull up switching elements of the driver stage are parallel to each other and connected between the first terminal of the power supply and the output of the driver stage.

The pull down switching elements of the driver stage are parallel to each other and connected between the second terminal of the power supply and the output of the driver stage.

The switching elements are pass transistors with their control terminals separately connected to the output of the said predrivers.

The predriver includes a selector receiving inputs from the said selection means, data input and providing a first output lines, each output line is further provided with a additional circuitry for increasing/decreasing speed, to supply desired slew rate.

The invention further provides a method to provide a programmable output buffer providing variable drive strength and slew rate for a given noise limit that includes the steps of providing a driver stage that includes a plurality of selectively enabled switching elements for generating the output of the buffer; connecting a predriver stage to a plurality of selectable switching elements that enables the selected drive stage switching elements; and enabling the required predriver switching elements in the desired sequence to provide the desired drive strength and/or slew rate using a selection means.

The above method further includes determining the number of selected driver stage switching elements by the required drive strength and controlling the switching sequence to optimize the switching noise and delay.

The above method further includes determining the number and sequence of selected switching elements in the predriver stage by the combination of the desired drive strength and/or slew rate.

The above method further includes connecting the pull up predriver stage to the pull up switching elements of the driver stage and a pull down predriver stage to the pull down switching elements of the driver stage.

The above method also includes achieving the sequential turning on of selected elements by selecting appropriate paths incorporating different delay elements.

The above method further includes connecting the pull up switching elements of the driver stage in parallel to each other between the first terminal of the power supply and the output of the driver stage.

The above method further includes connecting pull down switching elements of the driver stage in parallel to each other between the second terminal of the power supply and the output of the driver stage.

In accordance with another embodiment of the invention, a programmable output buffer is provided that includes a driver stage having a plurality of selectively-enabled switching elements configured to generate an output signal that is the output of the buffer; a pull-up predriver stage coupled to a first set of inputs in the driver stage; a pull-down predriver stage coupled to a second set of inputs in the driver stage; a bit pattern generator coupled to the pull-up predriver stage and the pull-down predriver stage and configured to generate a pattern of bits for selectively enabling selectable switching elements in the pull-up predriver stage and the pull-down predriver stage.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 2, shown therein is an embodiment of programmable drive strength output buffer in accordance with an embodiment of the present invention. The instant invention provides a tri-state output buffer with variable slew rate. The output buffer includes a pull-up predriver102and a pull-down predriver103having their outputs PX-PX4and NY0-NY4driving a driver stage101. The predrivers have control signals TR, SLR, TR˜, and SLR˜ and receive input data DATAIN and a bit configuration pattern from a bit pattern generator104. The bit pattern generator104generates the bit pattern depending upon the input it receives from a configuration memory cell105.

The output pin of the driver stage is left floating with all the transistors within the driver stage switched off when the control signal TR is high. When the control signal TR is low, the output buffer is enabled and data at the DATAIN is transmitted to the output pin at a selected output drive strength and slew rate. The slew select signal SLR determines the speed of output transition and noise generated by the driver. The SLR is set to high for enabling the slew limit option, and the inputs to the transistors of driver stage101are shaped to provide the slew limited output. The predrivers102and103keep output slew limited without making the buffer operation slow. For the low SLR, the output buffer-operates in a fast mode and maintains the fast switching transistors of the driver stage101without generating excessive ground noise and without exhausting excessive power.

The output buffer ensures optimum speed in all cases of different driving strengths and slew options, i.e., when higher driving strengths are selected, the inputs to the driver stage101transistors are slowed down to prevent large power and ground bounce in the supply rails without degrading the speed. Similarly for the lower drive strengths, the inputs to drive stage transistors are made fast to get maximum speed response comparable to the speed with higher driving strengths to offset the additional delay due to reduced driving strength. Also for a slew limited case, the inputs of the driver stage transistors are shaped to minimize ground bounce without degrading output transition time.

To select the required driving strength for the output buffer, specific bit patterns are required by the predrivers102and103. A Bit Pattern Generator104generates the required bit patterns. The output buffer is programmed to drive the output load with a specific drive strength by feeding the Bit Pattern Generator104with a set of Configuration Bits that would generate the required bit pattern for the desired driving strength. This bit pattern is fed into the predrivers102and103that, along with other control signals TR and SLR, selectively switch the various transistors of the driver stage101. Following is a Truth Table showing the bit patterns for selecting different drive strengths.

TABLE 1DrivingstrengthI in mATRS22S33S44S55Tristated1X(don't care)I011112I001113I000114I000015I00000
where S22, S33, S44, S55are the output of the bit pattern generator104.

The Bit Pattern Generator104can use different techniques to generate the aforementioned bit patterns for selecting the various driving strength options. One way to select one of the various driving strength options is to directly feed the configuration bits into the predrivers as S22, S23, S24, and S55, which would also reduce the Bit Pattern Generator circuitry. This technique requires the total number of configuration bits be equal to the total number of different driving options. The number of required configuration bits can be reduced by using various combinations of (logn/log2) Configuration Bits for generating ‘n’ different bit pattern for different driving options, which is by adding circuitry to the Bit Pattern Generator104. For example, three different Configuration Bits CB1, CB2and CB3in different combinations can generate bit patterns for a maximum of 8 driving options.

FIG. 3shows the driver stage101in detail. Pad200is the output of the output buffer. The pad200is pulled up by switching on the pull-up PMOS transistors203,204,205,206, and207. The PMOS transistors203,204,205,206, and207, each having a pre determined current driving capacity (for example X), are placed in parallel, connected between the output pad200and the supply Vcc. The NMOS transistors208,209,210,211, and212, again each having a pre-determined current driving capacity (for example “Y”) are placed in parallel, connected between the output pad200and a noisy ground supply Gnd. The inputs PX0PX1, PX2, PX3, and PX4to the pull-up PMOS driver transistors203204,205,206, and207are obtained from the pull-up predriver102and the inputs NY0, NY1, NY2, NY3, and NY4to the pull-down NMOS driver transistors208209,210,211, and212are obtained from the pull-down predriver103. An inherent parasitic package inductance is always present at the power supply terminals, which results in a noisy power supply during the switching of the output200. The instant invention provides an optimization of this and other noises to improve the performance of the output driver. Depending on the input from the bit pattern configuration the driving strength is selected, which switches on a different number and different combinations of the driver transistors. To turn on pull-up transistors203,204,205,206, and207of the driver stage, their respective gate voltages PX0, PX1, PX2, PX3, and PX4are pulled to low. During pull-up of the output, all the NMOS transistors of the driver are switched off. For turning on pull-down transistors208,209,210,211, and212of the driver stage, their respective gate voltages NY0, NY1, NY2, NY3, and NY4are pulled to high. During pull-down of the output, all the PMOS transistors of the driver are switched off.

FIG. 4illustrates the pull-down predriver103in detail. A pull-down drive strength and slew rate selector block31of the pull-down predriver103receives the data, DATAIN and control signals SLR, SLR˜, TR, and TR˜. The programming bit pattern S22, S23, S24, and S55and their complementary bits S2B, S3B, S4B, and S5B are also inputs to the block31. The control signals TR˜ and SLR˜ are the inverted TR and SLR respectively. The tristate option is enabled when the signal TR is high, TR˜ goes low and output of NAND gate34, INN˜=1 independent of DATAIN. This switches off transistor337and switches on transistor340to pull down line NY0. The selector block31also pulls the NY0, NY1, NY2, NY3, and NY4to low switching off all the pull-down driver transistors. On the other hand, for a low control signal TR, TR˜ goes high and the tristate option is disabled and the output of NAND gate34, INN˜ is inverted DATAIN. This allows DATAIN in to pass through the Selector block31and the predriver functions normally. Depending on the drive strength and slew rate selected, different number and combinations of the five outputs Y0, Y1, Y2, Y3, and Y4of the block31switch on that select the desired pull-down strength and slew rate of the output buffer in the following manner.

Since outputs Y0, Y1, Y2, Y3, and Y4of the block31are connected to the outputs NY0, NY1, NY2, NY3, and NY4respectively, the enable/disable status for NY's is exactly the same as those for Y's shown in Table 2. The Y0responds fastest to DATAIN, the response of Y1and Y3is the slowest, while the response of Y2and Y4is intermediate. Therefore, as observed in Table 2, for slew-limit option, the slower Y's, i.e., Y1and Y3, are first switched on followed by faster ones while for the fast option, the faster Y's, i.e., Y2and Y4, are first switched on followed by slower ones The slower Y's, i.e., Y1and Y3, are provided additional pull-up circuits for fast output option. For slew limited output option, the NY1and NY3, which are slower outputs of the pull-down predriver, are preferably switched on while NY2and NY4, which are faster outputs of the pull-down predriver, are switched on only for higher driving strengths. On the other hand, for the fast output option, the faster NY2and NY4are preferably switched on while the slower NY1and NY3are switched on only for higher driving strengths. This technique ensures that for the slew limit case, the output is slew limited and generates minimum noise while for the fast option, the output response speed is maximized, allowing some more noise on the ground rail but keeping it within tolerable limits. The NY0is switched on for any driving strength and responds fastest to DATAIN transition so the NY0is most critical in controlling ground bounce and speed.

When the slew limited is selected for low driving strengths and DATAIN is going high, the NY0is pulled up to Vcc for driving strengths of Y, 2Y, and 3Y at a speed at which the noise is minimized and also the output transition is not delayed excessively. However, NY0is not allowed to rise very fast as the sudden rise forces the output pull-down driver transistors to switch quite fast, generating ground bounce more than the tolerable limit in the fast case. To reduce this noise level, the pull-down predriver of the present invention employs two paths to pull-up NY0. Initially, NY0is pulled up towards Vcc−Vtn with NY0following the Y0through the pass transistor337and rising gradually. After a delay, another pull-up circuit32starts pulling-up the NY0to Vcc. However, for higher driving strengths, since the number of driver transistors that are switching is already high, there is no need for additional pull-up as the output delays are already reduced, and if NY0, which is most critical in generating noise, is not restricted to Vcc−Vtn, it will increase noise levels beyond tolerable limits for the slew case.

When limited slew is selected for driving strengths of 2Y and higher and DATAIN is going high, Y1is switched high after Y0, pulling up NY1to Vcc−Vtn. For driving strengths of 3Y and higher, with DATAIN going high, Y3is also switched high after Y0pulling up NY3to Vcc−Vtp. The pull-up of NY1and NY3to Vcc−Vtn after a delay ensures a minimized noise even for driving strengths of Y, 2Y and 3Y.

For driving strengths higher than 3Y in the slew limited case, the NY2and NY4are switched on but with a further delay with respect to NY1and NY3, respectively. The NY2and NY4are pulled up to Vcc for the slew limit as well as for the fast option. The switching of NY2and NY4is helpful in the slew limit case even though their transition is to Vcc and faster than NY1and NY3because the switching of the slower NY0, NY1, and NY3already have ensured a very small noise generation in the ground rail so the NY2and NY4help speed up the output transition with only a small increase in ground bounce.

For the fast output option and lower driving strengths, when DATAIN is going high, the NY0is pulled-up faster than in the slew limited case by pulling up the NY0to Vcc at a faster rate. However, NY0is not allowed to rise very fast as a sudden raise forces the output pull-down driver transistors to switch very fast, generating large ground bounce that gets coupled to all the circuits sharing the same ground rails. To prevent a sudden rise, the pull-down predriver of the present invention employs two paths to pull-up NY0. Initially, NY0is pulled-up towards Vcc−Vtp with NY0following the Y0through the pass transistor337and rising gradually, charging the gate capacitance of the driver NMOS transistor208exponentially. After a specific delay, another pull-up circuit32starts pulling-up the NY0to Vcc. As driving strength increases, the need for additional pull-up of the NY0reduces, since the number of driver transistors pulling down the output is already higher, resulting in greater noise being generated at the ground rail. So for driving strengths of 4Y, the strength of pull-up of the circuit32is reduced. For maximum driving strength of 5Y, the circuit32is completely switched off.

This technique therefore ensures that for lower driving strengths, the NY0which is most critical in generating ground bounce and in determining the output delays is pulled up fast enough to reduce output delays. For higher driving strengths, when more driver stage pull-down transistors of the output buffer are switched on and ground bounce is already near its maximum tolerable limit, there is no need to further speed up the transition of NY0, and therefore circuit32is either partially or completely switched off, depending on the driving strength selected. Also, for higher driving strengths in the fast output option, the NY0and NY1, which are slower and rise only up to Vcc−Vtn, need to be switched faster and up to Vcc to improve the output transition time. For this, another pull-up circuit33is used for pulling-up the NY1and NY3. The circuit32provides the additional pull-up for NY0required for fast output option for lower driving strengths, and circuit32also provides additional pull-up for the slew limited output option for lower driving strengths.

When SLR=1, i.e., when the fast output option is chosen, the circuit32is enabled for lower driving strengths and disabled for higher driving strengths. For driving strengths of Y, 2Y, and 3Y transistor 324 switches on since SLR˜=0, and transistor325is also on since S4B=0, which allows NY0to rise faster to Vcc that helps reduce output delays for lower driving strengths with minimum noise generation. For higher driving strengths, the circuit32is disabled and NY0rises to Vcc−Vtn gradually due to large gate capacitance of the pull-down transistor208. This gradual rise to voltage Vcc−Vtn ensures that the ground bounce generated by switching the driver stage NMOS transistor208is minimized.

When SLR=0, i.e., for the fast output option, the circuit32is enabled for low driving capability. For driving Y, 2Y, and 3Y strengths, Y1and Y3are both held at low, and transistors320and321of circuit32are on. This switches on circuit32and enhances the speed of rise in NY0, and now the NY0rises up to Vcc and at a faster speed. For a driving strength of 4Y, however, the transistor320is switched off since Y1also rises to Vcc, but transistor321is still on. This reduces the speed at which circuit32pulls up NY0to Vcc. This reduction in speed of pull-up by circuit32is done since the driving strength is already large. If NY0is pulled up at the same high speed as is done for lower driving strengths, the ground bounce would increase considerably. For 5Y driving strength, the circuit32is completely disabled by switching off transistors320and321since driving strength is already large enough so that any further enhancement to the transition of NY0would increase noise on ground rails beyond tolerable limits.

The circuit33also provides an additional pull-up path for NY1and NY3for the fast output option for higher driving strengths. For the driving strength of 4Y, in case of the slew limited option, NY1rises only up to Vcc−Vtn, while for driving strength of 4Y and 5Y, both NY1and NY3rise only up to Vcc−Vtn due to the NMOS transistor338between Y1and NY1and transistor339between Y3and NY3. This, in the slew limited option, is helpful for minimizing noise generation by restricting gate voltages of switching driver transistors, i.e., NY1and NY3only to Vcc−Vtp and the gate voltage rising slowly due to presence of pass transistors338and339. In the fast option, the circuit33ensures that the NY1and NY3are pulled up to Vcc through two paths. Initially the NY1and NY3rise towards Vcc−Vtn due to pass transistors338and339following the rise in Y1and Y3. After a small delay, an additional pull-up circuit33starts to pull up NY1towards Vcc for 4Y driving strength and pull up both NY1and NY3towards Vcc for 5Y driving strength.

When SLR=0, transistor334goes on, and with DATAIN=1, INN˜=0 transistor335goes on and transistor336goes off. Now if the driving strength is less than 4Y, the NY1and NY3are held at low voltage and are not being used. Hence circuit33requires no pull-up action and turning off transistors330and333makes circuit33off since S44and S55are both high for driving strength less than 4Y. For the driving strength of 4Y, NY1needs to be pulled up faster to Vcc for the fast output option. The transistor331is on since Y2B goes low with DATAIN=1 for all driving strengths higher than Y, and transistor330is also on since the 4Y selection bit S44=0. This enables an additional pull-up path for NY1. Similarly for the 5Y driving strength, both NY1and NY3need to be pulled up faster to Vcc so for fast option, transistors332and333are also on. The transistor332is on since Y4B goes low when DATAIN=1 for all driving strengths higher than 2Y, and transistor333also goes on since the 5Y selection bit, S55=0. This enables an additional pull-up path for NY3apart from enabling NY1. When DATAIN is going low, the pull-down NMOS transistors208,209,210, and211are switched off to allow the output of the output buffer to be pulled up to high by the driver stage PMOS pull-up transistors. Thus, with the tristate option disabled, i.e., TR˜=1 and input data, DATAIN=0, the signal INN˜=1 is fed into the selector block31which pulls down its outputs Y1through Y4to low which, in turn, pulls NY1, NY2, NY3, and NY4to low. The Y0is also pulled down by switching on transistor340, since INN˜=1. This turns off all the driver stage pull-down transistors of driver stage101. Proper sizing of transistors of circuits32and33determine the speed of additional pull-up of NY0, NY1, and NY3for fast output option. Further the sizes of transistors337,338, and339are kept small enough to ensure that voltages at NY0, NY1, and NY3rise slower than voltage rise at NY2and NY4.

FIG. 5illustrates the pull-down drive strength and slew rate selector in detail. The selector consists of five distinct lines, each of which drives one of the five pull-down NMOS driver stage transistors. This block provides the right combination of pull-down driver transistors to switch on with appropriate delays between the switching of each driver transistor, for a specific bit pattern generated by the Bit pattern Generator104as described in Table 2. The pull-down drive strength and slew rate selector31provides five different outputs Y0, Y1, Y2, Y3, and Y4and two other signals Y2B and Y4B which are inverted Y2and inverted Y4respectively. The input to the Selector31is the data DATAIN required at the output, connected directly to the block Y0without any intermediate circuit. All the other branches are controlled by transmission gates that control the flow of DATAIN through the four lines Y1, Y2, Y3, and Y4depending on the tristate signal, TR and the bit pattern generated for defining the driving strength of the output buffer.

When TR=1, the tristate option is enabled and the transmission gate401switches to off and thereby disconnects DATAIN from rest of the circuit31except Y0. The signal INN˜ output from NAND gate34is high and switches on the transistors422,423,424and425thereby pulling down the outputs Y0, Y1, Y2, Y3and Y4to 0V. The output Y0being directly connected to DATAIN goes out of the selector block31through a transistor337that switches off when TR=1 and the line NY0is pulled to low by transistor340. This disables all pull-down driver transistors when the tristate option is enabled.

For TR=0 and DATAIN=0, the output of the NAND INN˜ is high turning transistors422,423,424, and425to on, thereby pulling down the outputs Y1, Y3, Y2, and Y4of the selector block31to 0V while Y0is also forced to 0V with transistor340switching off the pull-down driver stage transistors. In this case pull-up driver stage transistors pull up the output at output pin.

When TR=0, and DATAIN going high, the DATAIN goes to transmission gates402and413. The bit S22of the bit pattern generated by the Bit Pattern Generator104controls the transmission gate402while the bit S33controls the transmission gate413. For driving strengths higher than Y, S22=0 and transmission gate402switches to on. Similarly, for a driving strength higher than 2Y, S33=0 and transmission gate413switches to on.

From the Table 2 it is clear that outputs of the selector31is enabled and switch with DATAIN in the order—Y0, Y1, Y3, Y2and Y4with increasing order of driving strengths from Y to 5Y for the slew limited case, while for the fast case, outputs of the Selector31get enabled and switch with DATAIN in the order—Y0, Y2, Y4, Y1, and Y3with increasing order of driving strengths from Y to 5Y.

For the slew limited output option when SLR=1 and DATAIN=1, for driving strength of Y, the transmission gate401is disabled so only Y0switches with DATAIN irrespective of the slew option selected. Bits S22, S33, S44, and S55are all high so transistors406,407,417, and418all go on and pull to low the outputs Y1, Y2, Y3, and Y4, respectively. So only Y0switches to high following the input signal DATAIN=1.

For driving strength of 2Y, transmission gate401is enabled along with transmission gate402since bit S22=0 while bits S33, S44and S55are high. For SLR=1, transmission gate403is on so line40goes high since DATAIN=1, pulling Y1high, and Y0is also high. Also, the transistor410is on since S44=1 and transistor409is on as line40is high which pulls the line41to low. This switches Y2to low and Y2B to high. Since S33=1, transmission gate413is off while transistors417and418are on, pulling line42and43to low, and Y3and Y4also remain low. Since line42and43are both low, transistors419and420are both off. Y0and Y1switch to high following the input signal DATAIN=1.

For a driving strength of 3Y, transmission gates401,402, and413are enabled and bits S44and S55are high. Since SLR is high, transmission gates403and414are on and hence Y1and Y3are at high, and Y0follows the DATAIN. The transistor410is on since S44=1 and transistor409is on as line40is high, which pulls line41low and results in a low Y2and high Y2B. Similarly, transistors420and421are on which pulls the line43to low. This switches Y4to low and Y4B to high. So Y0, Y1, and Y3switch to high following the input signal DATAIN=1.

For a driving strength of 4Y, transmission gates401,402, and413are enabled and the bit S55high. Since SLR is high, transmission gates403and414become on, pulling line40and line42to high switching Y1and Y3to high, and Y0follows DATAIN. The transmission gate405is on since S44=0, pulling line41to high thereby switching Y2to high. The output Y2is switched to high by transmission gate405after Y1pulls to high. The transistor410is switched off since S44=0. Further, the transistor421is on since S55=1 and transistor420is on as line42is high which pulls the line43to low. This switches Y4to low and Y4B to high. So Y0, Y1, Y2, and Y3switch to high following the input signal DATAIN=1.

For a driving strength of 5Y, transmission gates401,402, and413are enabled, and the node Y1and Y3are high, while Y0follows DATAIN. Since S44=0 and S55=0, transmission gates405and416also go on pulling line41and line43to high thereby switching Y2and Y4to high. The output Y2is switched to high by transmission gate405after Y1pulls to high. The output Y4is switched to high by transmission gate405after Y3pulls to high. The transistors410and421are switched off since S44=0 and S55=0. Hence Y0, Y2, Y4, Y1, and Y3switch to high following the input signal DATAIN=1.

When the SLR=0, DATAIN=1 and the fast output option is chosen, in such case for driving strength of Y, transmission gate401is disabled so only Y0switches with DATAIN irrespective of slew option selected. The bits S22, S33, S44and S55are all high so transistors406,407,417, and418all are on and pull to low the outputs Y1, Y2, Y3, and Y4respectively. Hence Y0switches to high following the input signal DATAIN=1.

For a driving strength of 2Y, transmission gates401and402are enabled. The control signal SLR=0 and hence transmission gate404passes DATAIN to line41, pulling Y2to high, and Y0follows DATAIN. The line41switches on the transistor408, and since S44=1 transistor410is also conducting, which pulls down the line40. Since S33=1, transmission gate413is off while transistors417and418are on, pulling line42and43to low, so Y3and Y4also fall to low. Since line42and43are both low, transistors419and420are both off. Y2B and Y4B, being complementary of Y2and Y4respectively, are pulled to low. Hence Y0and Y2switch to high following the input signal DATAIN=1.

For a driving strength of 3Y, transmission gates401,402and413are enabled and bits S44and S55are high. Since SLR is low, transmission gates404and415are on and hence Y2and Y4switch to high, and Y0follows the DATAIN. The transistor410is on since S44=1 and transistor408is on as line41is high, which pulls the line40to low. Similarly, transistor421is on since S55=1 and transistor419is on as line43is high, which pulls the line Y3to low. Y2B and Y4B, being complementary of Y2and Y4respectively, are pulled to low. Hence Y0, Y2and Y4switch to high following the input signal DATAIN=1.

For a driving strength of 4Y, transmission gates401,402, and413are enabled and bit S55being high. Since SLR is low, transmission gates404and415become on, pulling line41and line43to high switching Y2, and Y4to high, while Y0follows the DATAIN. Since S44=0, transmission gate405is on, pulling line40to high and thereby switching Y1to high. The output Y1is switched to high by transmission gate405after Y2pulls to high. The transistor410is switched off since S44=0. Further the transistor421is on since S55=1 and transistor419is on as line43is high, which pulls the line42to low. This switches Y3to low. Hence Y0, Y2, Y4, and Y1switch to high following the input signal DATAIN=1.

For a driving strength of 5Y, transmission gates401,402, and403are enabled. The nodes Y2and Y4are high, and Y0follows the DATAIN. Since S44=0 and S55=0, transmission gates405and416also go on, pulling line40and line42to high, thereby switching Y1and Y3to high. The output Y1is switched to high by transmission gate405after Y2pulls to high. Similarly output Y3is switched to high by transmission gate405after Y4pulls to high. The transistors410and421are switched off since S44=0 and S55=0. Hence Y0, Y1, Y3, Y2, and Y4switch to high following the input signal DATAIN=1.

The sizes of buffer stages and the transmission gates determine the speed at which signal on lines40,41,42, and43reach the outputs Y1, Y2, Y3and Y4of the selector31. Hence, the sizes of transmission gates403and414and sizes of buffer stage411and413determine response in slew limit case and is kept small enough to prevent fast switching of the driver stage transistors that would otherwise cause large bounce in the ground rail. The size of the transmission gates404and415and the size of the buffer stage412and414is kept large enough so that the signal transmitted to the gate of pull-down driver transistors is faster but its size is limited by amount of ground bounce that is tolerable in the system. The sizes of the transmission gates405and416are kept small enough to provide the desired skew between Y1and Y2and between Y3and Y4.

FIG. 6illustrates the pull-up predriver102in detail. The pull-up drive strength and slew rate selector block51of the pull-up predriver receives the data, DATAIN required at the output and the control signals TR, TR˜, SLR and SLR˜. The control signals TR˜ and SLR˜ are the inverted TR and SLR respectively. The programming bit pattern S22, S23, S24, and S55and their complementary signals S2B through S5B are the inputs to the block51. The tristate option is enabled when the control TR is high and the output INP˜ of NOR gate54is low and independent of DATAIN. This switches off transistor537and switches on transistor540to pull up line PX0. The selector block51also pulls the PX1, PX2, PX3, and PX4to high, switching off all the pull-up driver transistors. On the other hand, for a low control signal TR the tristate option is disabled and the output of NOR gate54, INP˜ is inverted DATAIN. This allows DATAIN in to pass through the selector block51and the predriver functions normally. Depending on the drive strength and slew rate selected, the different number and combinations of the five outputs X0, X1, X2, X3, and X4of the block51switch on that select the desired pull-up strength and slew rate of the output buffer in the following manner.

Since all the outputs X0, X1, X2, X3, and X4of the block51are connected to the outputs PX0, PX1, PX2, PX3, and PX4respectively, the enable/disable status for PX's is exactly the same as those for X's shown in Table 3. The X0responds fastest to the DATAIN, the response of X1and X3is the slowest while the response of X2and X4is intermediate. For the slew limited option, the slower X's are first switched on followed by faster ones, while for the fast option, the faster X's are first switched on followed by slower ones. The slower X's are provided additional pull-down circuits for faster pull-down. Therefore, for a slew limited output option, the PX1and PX3, which are slower outputs of the pull-up predriver, are preferably switched on while PX2and PX4, which are faster outputs of the pull-up predriver are switched on for higher driving strengths. On the other hand, for fast output option, the faster PX2and PX4are preferably switched on while slower PX1and PX3are switched on for higher driving strengths. This technique ensures that for the slew limit case, the output is slew limited and generates minimum noise. For the fast option, the output response speed is maximized allowing some more noise on the power rail but keeping it within tolerable limits. The PX0is switched on for any driving strength and responds fastest to DATAIN transition so the PX0is most critical in controlling ground bounce and speed.

When the limited slew is selected for low driving strengths and DATAIN is going low, the PX0is pulled-down at a speed at which the noise is minimized ensuring that the output transition is not delayed excessively. This is achieved by pulling up the PX0to ground for driving strengths of X, 2X and 3X. However, PX0is not allowed to drop very fast since a sudden drop forces the output pull-up driver transistors to switch quite fast, generating power bounce more than the tolerable limit allowed in fast case. To reduce this noise level, the pull-up predriver of the present invention employs two paths to pull-down PX0. Initially, PX0is pulled down towards Vtp with PX0following the X0through the pass transistor537, falling gradually. After a delay, another pull-down circuit52starts pulling-down the PX0to 0V. However, for higher driving strengths, since the number of driver transistors that are switching is already high, there is no need for additional pull-down as the output delays are already reduced. If PX0, which is most critical in generating noise, is not restricted to Vtp, it will increase noise levels beyond tolerable limits for slew case.

In the slew limited case for driving strengths of 2X and higher, when DATAIN is going low, X1switches to low after X0, pulling down PX1to Vtp. For driving strengths of 3X and higher, when DATAIN is going low, X3also switches to low after X0pulling down PX3to Vtp. The pull-down of PX1and PX3to Vtp after a delay ensures a minimized noise even for driving strengths of X, 2X, and 3X.

For driving strengths higher than 3X in the slew limited case, the faster PX2and PX4switch on but with a further delay with respect to PX1and PX3respectively. The PX2and PX4are pulled down to 0V for slew limit as well as for fast option. The switching of PX2and PX4is helpful in the slew limit case even though their transition is to 0V and faster than PX1and PX3because the switching of slower PX0, PX1, and PX3already have ensured less noise generation in the power rail so the PX2and PX4help speed up the output transition with only a small increase in power bounce.

For fast output option and lower driving strengths, when DATAIN goes low, the PX0pulled-down faster than in the slew limited case. However, PX0is not allowed to fall very fast since sudden change forces the output pull-up driver transistors to switch very fast generating large power bounce that gets coupled to all the circuits sharing the same power rails. To prevent this, the pull-up predriver of the present invention employs two paths to pull-down PX0. Initially, PX0is pulled down towards Vtp with PX0following the X0through the pass transistor537and falling gradually, discharging the gate capacitance of the driver PMOS transistor203exponentially. After a specific delay, another pull-down circuit52starts to provide an additional pull-down means for the PX0. However, as driving strength increases, the need for additional pull-down of the PX0reduces since the number of driver transistors pulling up the output is already higher, resulting in greater noise being generated at the power rails.

For driving strengths of 4X, the strength of pull-down of circuit52is reduced. For maximum driving strength of 5X, the circuit52is completely switched off.

This technique therefore ensures that for lower driving strengths, the PX0which is most critical in generating power bounce and in determining the output delays, is pulled down fast enough to reduce output delays, while for higher driving strengths, when more driver stage pull-up transistors of the output buffer are already switched on and power bounce is already near its maximum tolerable limit, there is no need to further speed up the transition of PX0. Therefore circuit52is either partially or completely switched off, depending on the driving strength selected. Further for higher driving strengths in the fast output option, the PX0and PX1, which are slower and fall only up to Vtp need to be switched faster and down to 0V to improve the output transition time, which is by providing another pull-down circuit53for pulling-down the PX1and PX3. The circuit52provides the additional pull-down for PX0for the fast output option for lower driving strengths. Also the circuit52provides additional pull-down for slew limited output option for lower driving strengths.

When SLR=1, the circuit52is enabled for lower driving strengths and disabled for higher driving strengths. For driving strengths of X, 2X, and 3X, transistor524and525are on, which allows PX0to fall faster to 0V that helps reduce output delays for lower driving strengths with minimum noise generation. For higher driving strengths, the circuit52is disabled, and PX0falls to Vtp gradually due to large gate capacitance of the pull-up transistor203. This gradual fall to voltage Vtp ensures that the power bounce generated by switching the driver stage PMOS transistor203is minimized.

When SLR=0, i.e., for fast output option, circuit52is enabled for low driving capability. For driving strengths of X, 2X, and 3X strengths X1and X3are both held at high and so transistors520and521are on. This enhances the speed of fall in PX0, and now the PX0falls down to 0V and at a faster speed. For a driving strength of 4X, however, the transistor520is switched off since X1also falls to 0V, but transistor521is still on. This reduces the speed with which circuit52pulls down PX0to 0V. This reduction in speed of pull-down by circuit52is done since driving strength is already large, and if PX0is pulled down with same high speed as done for lower driving strengths, the power bounce would increase considerably. For 5X driving strength, the circuit52is completely disabled by switching off transistors520and521since driving strength is already large enough. Any further enhancement to the transition of PX0would increase noise on power rails considerably. The circuit53also provides an additional pull-down path for PX1and PX3for fast output option for higher driving strengths. For a driving strength of 4X, PX1falls only to Vtp. For a driving strength of 4X and 5X, both PX1and PX2fall only to Vtp in case of slew limited option due to on PMOS transistor538between X1and PX1and transistor539between X3and PX3. This, the slew limited option is helpful in minimizing noise generation by restricting gate voltages of switching driver transistors, i.e., PX1and PX3only to Vtp and the gate voltage falling slowly due to presence of pass transistors538and539.

In the fast option, the circuit53ensures that the PX1and PX3are pulled down to 0V through two paths. Initially the PX1and PX3fall towards Vtp following the fall in X1and X3. But after a small delay, additional pull-down circuit53starts to pull down PX1towards 0V for 4X driving strength, and pull down both PX1and PX3faster towards 0V for 5X driving strength.

When SLR=0 transistor534is on and when the DATAIN is going low, transistor535is on and transistor536is off. If driving strength is less than 4X, the PX1and PX3are held at a high voltage and are not being used. Hence circuit53requires no pull-down action, and transistors530and533are off.

For a driving strength of 4X, PX1needs to be pulled down faster to 0V for the fast output option. The transistor531is already on since X2B turns high and DATAIN=0 for all driving strengths higher than X and transistor530also goes on since inverted of the 4X selection bit in the bitstream, S4B=1. This enables an additional pull-down path for PX1. Similarly for the 5X driving strength, both PX1and PX3are pulled down faster to 0V. For the fast option, transistors532and533also turn on. The transistor532is already on since X4B goes high with DATAIN=0 for all driving strengths higher than 2X, and transistor533also goes on since the inverted of the 5X selection bit in the bitstream S5B=1. This enables an additional pull-down path for PX3. When DATAIN is going high, the pull-up PMOS transistors203,204,205,206, and207of the driver stage101are required to be switched off to allow the output of the output buffer to be pulled down to low by the driver stage NMOS pull-down transistors. Thus, with the tristate option disabled, i.e., TR=0 and input data, DATAIN=1, the signal INP˜=0 is switched to low, or 0V by the NOR gate54. Thus for INP˜=0, the transistors540,541,542,543, and544are switched on and pull to high all the inputs, PX0, PX1, PX2, PX3, and PX4, turning off all the driver stage pull-up transistors.

FIG. 7illustrates the pull-up drive strength and slew rate selector51in detail. The selector51consists of 5 distinct lines, each of which drives one of the five pull-up PMOS driver stage transistors. This block is for combining right pull-up driver transistors with appropriate delays for a specific bit pattern generated by the Bit pattern Generator104. The selector51provides outputs as X0, X1, X2, X3, X4and signals X2B and X4B, which are inverted X2and inverted X4, respectively. The inputs to selector51are the configuration bits S22, S2B, S33, S3B, S44, S4B, S55, and S5B from the bit pattern generator104and the data DATAIN. The first output from the block X0is directly obtained from DATAIN without any intermediate circuit. All the other branches are controlled by transmission gates that control the flow of DATAIN through the four lines X1, X2, X3, and X4depending on the tristate signal, TR, and the bit pattern generated for defining the driving strength of the output buffer.

When TR=1, the tristate option is enabled, and the transmission gate601switches to off, thereby disconnecting DATAIN from rest of circuit51except X0. The signal INP˜ output from NOR gate54goes low and switches the transistors622,623,624, and625to on, thereby pulling up the outputs X0, X1, X2, X3and X4of the selector block51to Vcc. The output X0being directly connected to DATAIN goes out of the selector block51, but it is also inhibited by a pass transistor537that switches off when TR˜=0 and the line PX0is pulled to high by transistor540. With the control signal TR=0 and DATAIN going low, the pull-up predriver is enabled and the DATAIN goes to transmission gates602and613. The bit S22of the bit pattern generated by the Bit Pattern Generator104controls the transmission gate602, while the bit S33controls the transmission gate613. For driving strengths higher than X, S22=0 and transmission gate602switches to on. Similarly, for a driving strength higher than 2X, S33=0 and transmission gate613switches to on.

From Table 3 it is clear that the outputs of the selector51get enabled and switch with DATAIN in the order—X0, X1, X3, X2, and X4with increasing order of driving strengths from X to 5X for the slew limited case, while outputs of the selector51get enabled and switch with DATAIN in the order—X0, X2, X4, X1and X3with increasing order of driving strengths from X to 5X for the fast case.

When TR˜=1 and DATAIN=1, the output of the NOR gate INP˜ is low, turning transistors622,623,624, and625on, thereby pulling up the outputs X1, X2, X3, and X4of the selector block51to Vcc while X0is also raised high by transistor540.

For the slew limited output case, when SLR=1 and DATAIN=0, for driving strength of X, transmission gate601is disabled and X0switches with DATAIN irrespective of slew option selected. Bits S22, S33, S44and S55are all high so transistors606,607,617and618all go on and pull to high the outputs X1, X2, X3and X4respectively. X0switches to low following the input signal DATAIN=0.

For a driving strength of 2X, transmission gate601is enabled along with transmission gate602since bit S22=0, while bits S33, S44and S55are high. Since SLR=1, transmission gate603is on and DATAIN=0, line60goes low pulling X1to low, X0already being low. The transistor610is on since S44=1 and transistor609is on as line60is low, which pulls the line61high. This switches X2to high and X2B to low. Since S33=1, the transmission gate613is off, while transistors617and618are on pulling line62and63to high, and X3and X4also rise to high. Since line62and63are both low, transistors619and620are both off. Hence X0and X1switch to low following the input signal DATAIN=0.

For a driving strength of 3X, transmission gates601,602, and613are enabled and bits S44and S55are high. While SLR=1, transmission gates603and614are on and hence the nodes X1and X3switch to low and follow the input signal DATAIN=0, X0also being pulled to low. The transistor610is on since S44=1 and transistor609is on as line60is low, which pulls the line61high. This switches X2to high and X2B to low. Similarly, transistor621is on since S55=1 and transistor620is on as line62is low, which pulls the line63high. This switches X4to high and X4B to low. Providing X0, X1and X3low following the input signal DATAIN=0.

For a driving strength of 4X, transmission gates601,602, and613are enabled and bit S55being high. When SLR=1 and DATAIN=0 transmission gates603and614become on pulling line60and line62to low switching X1and X3to low, X0also being low. Since S44=0, transmission gate605also goes on pulling line61to low thereby switching X2to low. The output X2is switched to low by transmission gate605after X1pulls to low. The transistor610is switched off since S44=0. The transistor621is on since S55=1 and transistor620is on as line62is low which pulls the line63high. This switches X4to high and X4B to low. Hence X0, X1, X2, and X3switch to low following the input signal DATAIN=0.

For a driving strength of 5X, transmission gates601,602, and613are enabled and S55bit is low. The nodes X1and X3switch to low following the input signal DATAIN=0, X0also being low. Since S44=0 and S55=0, transmission gates605and616goes on pulling line61and line63to low, thereby switching X2and X4to low. The output X2is switched to low by transmission gate605after X1pulls to low. Similarly, output X4is switched to low by transmission gate605with some delay after X3pulls to low. Transistors610and621are switched off since S44=0 and S55=0. Providing X0, X2, X4, X1, and X3low following the input signal DATAIN=0.

For the fast output case when SLR=0 and DATAIN=0, and for a driving strength of X, transmission gate601is disabled only X0follows DATAIN irrespective of slew option selected. Bits S22, S33, S44and S55are all high, and transistors606,607,617and618all go on and pull to low the outputs X1, X2, X3and X4respectively, hence providing the X0low following the input signal DATAIN=0.

For a driving strength of 2X, transmission gate601is enabled along with transmission gate602since bit S22=0, while bits S33, S44, and S55are high. With SLR=0, the transmission gate604is on, pulling down line61by connecting DATAIN and pulling X2to low, X0is low as it follows DATAIN. The transistor610is on since S44=1 and transistor608is on as line61is low, which pulls the line X1high. Since S33=1, transmission gate613is off while transistors617and618are on, pulling line62and63to low, and X3and X4also remain high. Since line62and63are both low, transistors619and620are both off. X2B and X4B, being complementary of X2and X4respectively, are pulled low, hence providing X0and X2to switch low following the input signal DATAIN=0.

For a driving strength of 3X, transmission gates601,602, and613are enabled, since bits S22and, S33are low while bits S44and S55are high. With the control signal SLR=0, transmission gates604and615are on and X2and X4switch to low and follow the input signal DATAIN=0, with X0also being pulled to low. Also, a transistor610is on since S44=1 and transistor608is on as line61is low, which pulls the line X1high. Similarly, transistor621is on since S55=1 and transistor619is on as line63is low, which pulls the line X3high. The nodes X2B and X4B, being complementary of X2and X4respectively, are pulled to low. Hence providing X0, X2, and X4switch to low following the input signal DATAIN=0.

For a driving strength of 4X, transmission gates601,602, and613are enabled and bit S55is high. The control signal SLR=0, and DATAIN=0, transmission gates604and615become on pulling line61and line63to low and switching X2and X4to low, and X0is low as it follows DATAIN. Since S44=0, transmission gate605switches on pulling net60to low, thereby switching X1to low. The output X1is switched to low by transmission gate605after X2pulls to low. The transistor610is switched off since S44=0. The transistor621is on since S55=1 and transistor619is on as line63is low, which pulls the line X3high. Hence providing X0, X2, X4and X1switch to low following the input signal DATAIN=0.

For a driving strength of 5X, transmission gates601and602are enabled and the bit S55low. The nodes X1, X0, and X3switch to low following the input signal DATAIN=0. Since S44=0 and S55=0, transmission gates605and616go on pulling net60and net62to low, thereby switching X1and X3to low. The output X1is switched to low by transmission gate605after X2pulls to low. Similarly output X3is switched to low by transmission gate605with some delay after X4pulls to low. The transistors610and621are switched off since S44=0 and S55=0. Hence providing X0, X1, X3, X2, and X4switch to low following the input signal DATAIN=0.

The sizes of buffer stages and the transmission gates determine the speed at which signal lines60,61,62, and63reach the outputs X1, X2, X3, and X4of the selector31. Hence, the sizes of transmission gates603and614and sizes of buffer stages611and613determine the response in the slew limit case and is kept small enough to prevent fast switching of the driver stage transistors that would otherwise cause large bounce in the power rail.

The sizes of transmission gates604and615and sizes of buffer stage612and614are kept large enough so that signal transmitted to the gate of the pull-up driver transistors is faster, but its size is limited by the amount of power bounce that is tolerable in the system. Sizes of transmission gates605and616are kept small enough to provide the desired skew between X1and X2and between X3and X4. Similarly, proper sizing of transistors of circuits52and53determine the speed of additional pull-down of PX0, PX1and PX3for fast output option. The sizes of transistors537,538, and539are kept small enough to ensure that voltages at PX0, PX1and PX3rise slower than the voltage rise at PX2and PX4.

The output buffer described herein is programmable for five different driving current values. But it should be clear that an output buffer with a lesser or higher number of driving strength options can be implemented using the output buffer described in the present invention.