DISPLAY DEVICE

According to one embodiment, a display device includes a plurality of display elements and a partition which surrounds each of the plurality of display elements. The display elements each include a lower electrode, an upper electrode opposing the lower electrode and an organic layer disposed between the lower electrode and the upper electrode. The partition includes a conductive lower portion and an upper portion protruding from a side surface of the lower portion. Further, the partition includes an aperture through which the lower portion and the upper portion penetrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-163997 filed Oct. 12, 2022, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

In recent years, display devices to which an organic light-emitting diode (OLED) is applied as a display element have been put into practical use. Such a display element comprises a lower electrode, an organic layer which covers the lower electrode, and an upper electrode which covers the organic layer.

Here, in some cases, a light-receiving element such as a sensor or camera that detects ambient light may be placed over the display area where a plurality of display elements are arranged. In such cases, if the light transparency of the display area is low, the detection accuracy of the light-receiving element may decrease.

DETAILED DESCRIPTION

In general, according to one embodiment, a display device includes a plurality of display elements and a partition which surrounds each of the plurality of display elements. The display elements each include a lower electrode, an upper electrode opposing the lower electrode and an organic layer disposed between the lower electrode and the upper electrode, which emits light in response to a potential difference between the lower electrode and the upper electrode. The partition includes a conductive lower portion and an upper portion protruding from a side surface of the lower portion. Further, the partition includes an aperture through which the lower portion and the upper portion penetrate.

According to such configurations, it is possible to provide a display device comprising a display area with enhanced transparency.

Embodiments will be described with reference to the accompanying drawings.

In the drawings, in order to facilitate understanding, an X-axis, a Y-axis and a Z-axis orthogonal to each other are shown depending on the need. A direction parallel to the X-axis is referred to as a first direction, a direction parallel to the Y-axis is referred to as a second direction, and a direction parallel to the Z-axis is referred to as a third direction. The third direction Z is normal to a plane containing the first direction X and the second direction Y. Further, viewing structural elements parallel to the third direction Z is referred to as plan view.

The display device of this embodiment is an organic electroluminescent display device comprising an organic light-emitting diode (OLED) as a display element, and could be mounted on televisions, personal computers, in-vehicle devices, tablets, smartphones, mobile phones and the like.

First Embodiment

FIG.1is a diagram showing a configuration example of a display device DSP according to the first embodiment. The display device DSP comprises a display panel PNL. The display panel PNL includes a display area DA which displays images and a surrounding area SA around the display area DA.

In this embodiment, the shape of the display panel PNL in plan view is rectangular. Note here that the shape of the display panel PNL in plan view is not limited to rectangular, but may as well be some other shape such as a square, circle or oval.

The display area DA comprises a plurality of pixels PX arranged in a matrix along the first direction X and the second direction Y. The pixels PX each include a plurality of subpixels SP. For example, the pixels PX include a blue subpixel SP1, a green subpixel SP2and a red subpixel SP3. Note that the pixels PX may include a subpixel SP of some other color, such as white, together with or in place of any of the subpixels SP1, SP2and SP3.

The subpixels SP each comprise a pixel circuit1and a display element DE driven by the pixel circuit1. The display element DE is an organic light emitting diode (OLED) as a light emitting element. The pixel circuit1comprises a pixel switch2, a drive transistor3and a capacitor4. The pixel switch2and the drive transistor3are switching elements constituted by thin-film transistors, for example.

A gate electrode of the pixel switch2is connected to a respective scanning line GL for supplying scanning signals to the pixel circuit1. One of source and drain electrodes of the pixel switch2is connected to a respective signal line SL for supplying video signals to the pixel circuit1, and the other is connected to a gate electrode of the drive transistor3and a capacitor4. In the drive transistor3, one of source and drain electrodes is connected to a feed line PL and the capacitor4, and the other is connected to the display element DE.

Note that the configuration of the pixel circuit1is not limited to that of the example shown in the figure. For example, the pixel circuit1may as well comprise more thin-film transistors and capacitors.

The display device DSP further comprises a light receiving element RC and a controller CT. The light receiving element RC is, for example, a dimming sensor (ambient light sensor) that detects ambient light and outputs a detection signal according to the detected light. But it is not limited to this example, but the light receiving element RC may as well be another type of element, such as a camera.

The light receiving element RC is disposed on a rear surface side of the display panel PNL, for example, and overlaps the display area DA. The light receiving element RC has a size larger than one pixel PX, for example. In this case, the light receiving element RC overlaps multiple pixels PX.

The controller CT executes various operations for displaying images on the display area DA, such as supplying signals to the pixel circuits and the like. When the light receiving element RC is a light dimming sensor, the controller CT adjusts the brightness of the image displayed on the display area DA based on a detection signal from the light receiving element RC. More specifically, the controller CT increases the brightness of the image as the outdoor light (ambient light) is stronger, and decreases the brightness of the image as the ambient light is weaker. The controller CT may be mounted on the display panel PNL or on a flexible circuit board connected to the display panel PNL or on a rigid substrate connected to the flexible circuit board.

FIG.2is a schematic plan view showing an example of layout of the subpixels SP1, SP2and SP3. In the example shown inFIG.2, the subpixels SP1and SP2are aligned along the first direction X. The subpixels SP1and SP3as well are aligned along the first direction X. Further, the subpixels SP2and SP3are aligned along the second direction Y.

When the subpixels SP1, SP2and SP3have such a layout, rows in each of which a plurality of subpixels SP1are repeatedly arranged along the second direction Y and rows in each of which subpixels SP2and SP3are arranged alternately along the second direction Y in the display area DA. These rows are alternately arranged along the first direction X.

Note that the layout of the subpixels SP1, SP2and SP3is not limited to that of the example shown inFIG.2. As another example, the subpixels SP1, SP2and SP3may as well be aligned along the first direction X.

In the display area DA, an insulating rib5and a conductive partition6are arranged. The rib5includes pixel apertures AP1, AP2and AP3in the subpixels SP1, SP2and SP3, respectively. In the example shown inFIG.2, the pixel aperture AP2is larger than the pixel aperture AP3and the pixel aperture AP1is larger than the pixel aperture AP2.

The subpixel SP1comprises a lower electrode LE1, an upper electrode UE1and an organic layer OR1each overlapping the pixel aperture AP1. The subpixel SP2comprises a lower electrode LE2, an upper electrode UE2and an organic layer OR2each overlapping the pixel aperture AP2, respectively. The subpixel SP3comprises a lower electrode LE3, an upper electrode UE3and an organic layer OR3each overlapping the pixel aperture AP3.

The portions of the lower electrode LE1, the upper electrode UE1and the organic layer OR1, which overlap the pixel aperture AP1constitutes the display element DE1of the subpixel SP1. The portions of the lower electrode LE2, the upper electrode UE2and the organic layer OR2, which overlap the pixel aperture AP2constitute the display element DE2of the subpixel SP2. The portions of the lower electrode LE3, the upper electrode UE3and the organic layer OR3, which overlap the pixel aperture AP3constitute the display element DE3of the subpixel SP3. The display elements DE1, DE2and DE3may further include a cap layer, which will be described later. The rib5surrounds the display elements DE1, DE2and DE3.

The partition6is placed at the boundary of each pair of subpixels SP adjacent to each other, so as to overlap the rib5in plan view. The partition6includes a plurality of first partitions6xextending along the first direction X and a plurality of second partitions6yextending along the second direction Y.

The first partitions6xare each disposed between each pair of pixel apertures AP1adjacent to each other along the second direction Y and between each pair of pixel apertures AP2and AP3adjacent to each other along the second direction Y. The second partitions6yare each disposed between each pair of pixel apertures AP1and AP2adjacent to each other along the first direction X and between each pair of pixel apertures AP1and AP3adjacent to each other along the first direction X.

In the example shown inFIG.2, the first partitions6xand the second partitions6yare connected to each other. With this structure, the partition6, as a whole, has a lattice-like shape which surrounds the display elements DE1, DE2and DE3and the pixel apertures AP1, AP2and AP3. It can as well be said that the partition6includes apertures in the subpixels SP1, SP2and SP3, respectively, as in the case of the rib5.

The partition6comprises a plurality of apertures H. The apertures H are sufficiently smaller than the pixel apertures AP1, AP2and AP3. In this embodiment, the shape of each of the apertures H in plan view is a regular circle. Note that the shape of the apertures H is not limited to that of this example, but may as well be oval or polygonal. Further, not all of the apertures H need to have the same shape as shown in the figure, but a plurality of apertures H of different shapes may as well be provided.

In the example shown inFIG.2, each aperture H is independent from the pixel apertures AP1, AP2and AP3. As another example, at least one of the plurality of apertures H may be connected to the pixel apertures AP1, AP2and AP3.

In the example shown inFIG.2, the aperture H is provided at each of the intersections of the first partitions6xand the second partitions6y. The aperture H may be provided at all of the intersections present in the display area DA, or at some of these intersections.

When the apertures H are not uniformly arranged in the display area DA, the user may feel unevenness while viewing the display area DA. Therefore, it is preferable that the apertures H should be arranged in a uniform density over the entire display area DA. As another example, the apertures H may be provided in the regions which overlap the light receiving elements RC and not in the surrounding regions thereof.

FIG.3shows a schematic cross-sectional view of the display device DSP taken along line III-III inFIG.2. The display panel PNL comprises a substrate10, a circuit layer11disposed on the substrate10and an organic insulating layer12which covers the circuit layer11.

The circuit layer11includes various circuits and wiring lines, such as the pixel circuit1, scanning lines GL, signal lines SL, and feed lines PL shown inFIG.1. The organic insulating layer12functions as a planarization film that planarizes unevenness created by the circuit layer11.

The lower electrodes LE1, LE2and LE3are disposed on the organic insulating layer12. Although not illustrated in the cross section shown inFIG.3, the lower electrodes LE1, LE2and LE3are connected to the pixel circuits1of the subpixels SP1, SP2and SP3, respectively, via contact holes provided in the organic insulating layer12.

The rib5is disposed on the organic insulating layer12and the lower electrodes LE1, LE2and LE3. End portions of the lower electrodes LE1, LE2and LE3are covered by the rib5.

The partition6includes a lower portion61having conductivity and disposed on the rib5and an upper portion62disposed on the lower portion61. The upper portion62has a width greater than that of the lower portion61. With this configuration, inFIG.3, both end portions of the upper portion62protrude beyond respective side surfaces of the lower portion61. Such a shape of the partition6is referred to as overhanging type.

The organic layer OR1covers the lower electrode LE1through the pixel aperture AP1. The upper electrode UE1covers the organic layer OR1and opposes the lower electrode LE1. The organic layer OR2covers the lower electrode LE2through the pixel aperture AP2. The upper electrode UE2covers the organic layer OR2and opposes the lower electrode LE2. The organic layer OR3covers the lower electrode LE3through the pixel aperture AP3. The upper electrode UE3covers the organic layer OR3and opposes the lower electrode LE3.

In the example shown inFIG.3, the cap layer CP1is disposed on the upper electrode UE1, the cap layer CP2is disposed on the upper electrode UE2, and the cap layer CP3is disposed on the upper electrode UE3. The cap layers CP1, CP2and CP3serve as optical adjustment layers that improve the efficiency of extracting light emitted by the organic layers OR1, OR2and OR3, respectively.

In the following description, a stacked body including the organic layer OR1, the upper electrode UE1and the cap layer CP1is referred to as a thin film FL1, a stacked body including the organic layer OR2, the upper electrode UE2and the cap layer CP2is referred to as a thin film FL2, and a stacked body including the organic layer OR3, the upper electrode UE3and the cap layer CP3is referred to as a thin film FL3.

A portion of the thin film FL1is located on the upper portion62. This portion is separated from a portion of the thin film FL1, which is located below the partition6(the portion which constitutes the display element DE1). Similarly, a portion of the thin film FL2is located on the upper portion62and this portion is separated from a portion of the thin film FL2, which is located below the partition6(the portion which constitutes the display element DE2). Further, a portion of the thin film FL3is located on the upper portion62and the portion is separated from a portion of the thin film FL3, which is located below the partition6(the portion which constitutes the display element DE3).

In the subpixels SP1, SP2, and SP3, first sealing layers SE11, SE12and SE13are respectively disposed to cover the display elements DE1, DE2and DE3individually. The first sealing layer SE11continuously covers the thin film FL1and the partition6around the subpixel SP1. The first sealing layer SE12continuously covers the thin film FL2and the partition6around the subpixel SP2. The first sealing layer SE13continuously covers the thin film FL3and the partition6around the subpixel SP3.

In the example shown inFIG.3, the thin films FL1and FL2on the partition6between the subpixels SP1and SP2are separated from each other. The thin films FL1and FL3on the partition6between the subpixels SP1and SP3are also separated from each other.

In the example shown inFIG.3, the end portions of the first sealing layers SE11and SE12located on the partition6between the subpixels SP1and SP2are separated from each other. The end portions of the first sealing layers SE11and SE13located on the partition6between the subpixels SP1and SP3are also separated from each other.

The first sealing layers SE11, SE12and SE13are continuously covered by the second sealing layer SE2. With the second sealing layer SE2, the display elements DE1, DE2and DE3more securely sealed, thus improving resistance to moisture.

The second sealing layer SE2is covered by the resin layer13. The resin layer13is covered by the third sealing layer SE3. The second sealing layer SE2, the resin layer13and the third sealing layer SE3are provided over at least the entire display area DA, and parts thereof extend to the surrounding area SA.

A resin layer and/or a sealing layer may further be placed on the third sealing layer SE3. Another optical element, a protective film and a substrate such as cover glass or a touch panel may be placed above the third sealing layer SE3, and this substrate may be adhered to the third sealing layer SE3via a transparent adhesive layer such as an optical clear adhesive (OCA).

The light receiving element RC is disposed below the substrate10. The light receiving element RC is supported, for example, by a frame or housing that holds the display panel PNL. A translucent insulating layer or conductive layer may as well be disposed between the light-receiving element RC and the substrate10.

The substrate10is formed of glass, for example. The substrate10may as well be formed of a transparent resin material having flexibility. The organic insulating layer12is formed of an organic insulating material.

The rib5, the first sealing layers SE11, SE12and SE13, the second sealing layer SE2and the third sealing layer SE3are each formed of, for example, an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (SiON). The rib5, the first sealing layers SE11, SE12and SE13, the second sealing layer SE2and the third sealing layer SE3may be formed of different types of inorganic insulating materials, respectively. The rib5may as well be formed of an organic insulating material such as polyimide. The resin layer13is formed of, for example, a resin material such as acrylic resin.

The lower electrodes LE1, LE2and LE3each include an intermediate layer formed of silver (Ag), for example, and a pair of conductive oxide layers which respectively cover an upper surface and lower surface of the intermediate layer, respectively. Each conductive oxide layer can be formed, for example, of a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO).

The upper electrodes UE1, UE2and UE3are each formed, for example, of a metallic material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2and LE3correspond to anodes, and the upper electrodes UE1, UE2and UE3correspond to cathodes.

The organic layers OR1, OR2and OR3have a stacked layer structure of, for example, a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer. The organic layers OR1, OR2and OR3may as well have a so-called tandem structure including multiple light emitting layers.

The cap layers CP1, CP2and CP3are formed, for example, of a stacked layer body of a plurality of transparent thin films. The stacked layer body may as well include, as the plurality of thin films, a thin film formed of an inorganic material and a thin film formed by an organic material. Further, these plurality of thin films have refractive indices different from each other. The material of the thin films which constitute the stacked layer body is different from the material of the upper electrodes UE1, UE2and UE3and also from the material of the first sealing layers SE11, SE12and SE13. The cap layers CP1, CP2and CP3may be omitted.

The lower portion61of the partition6is formed, for example, of aluminum (Al). The lower portion61may as well be formed of an aluminum alloy such as aluminum-neodymium (AlNd) or may have a stacked layer structure of an aluminum layer and an aluminum alloy layer. Further, the lower portion61may include a thin film formed of a metal material different from aluminum or aluminum alloy under the aluminum layer or aluminum alloy layer. Such a thin film can be formed, for example, of molybdenum (Mo).

The upper portion62of the partition6has a stacked layer structure of a thin film formed, for example, of a metal material such as titanium (Ti) and a thin film formed, for example, of a conductive oxide such as ITO. The upper portion62may have a single layer structure of a metal material such as titanium. Further, the upper portion62may as well have a single layer or s stacked layer structure of an inorganic insulating material different from that of the first sealing layers SE11, SE12and SE13.

To the partition6, a common voltage is supplied. The common voltage is supplied to each of the upper electrodes UE1, UE2and UE3, which are in contact with a side surface of the lower portion61. To the lower electrodes LE1, LE2and LE3, a pixel voltage is supplied through the respective pixel circuits1of the subpixels SP1, SP2and SP3.

When a potential difference is created between the lower electrode LE1and the upper electrode UE1, the light emitting layer of the organic layer OR1emits light of a wavelength range of blue color. When a potential difference is created between the lower electrode LE2and the upper electrode UE2, the light emitting layer of the organic layer OR2emits light of a wavelength range of green color. When a potential difference is created between the lower electrode LE3and the upper electrode UE3, the light emitting layer of the organic layer OR3emits light of a wavelength range of red color.

As another example, the light emitting layers of organic layers OR1, OR2and OR3may emit light of the same color (for example, white). In this case, the display device DSP may comprise color filters which convert the light emitted by the light-emitting layers into light of colors corresponding to the subpixels SP1, SP2and SP3, respectively. Further, the display device DSP may as well comprise layers containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of colors corresponding to the subpixels SP1, SP2and SP3, respectively.

FIG.4is a schematic cross-sectional view of the display device DSP taken along line IV-IV inFIG.2. In this drawing, the substrate10, the circuit layer11, the resin layer13and the third sealing layer SE3are omitted.

The lower portion61of the partition6includes a side surface SF. The upper portion62protrudes from the side surface SF. The upper electrode UE1is in contact with the side surface SF. The portion of the side surface SF, which is not covered by the upper electrode UE1is covered by the sealing layer SE11.

The aperture H penetrates the lower portion61and the upper portion62. That is, the aperture H includes holes made in the lower portion61and the upper portion62, respectively. The lower portion61includes an inner surface IF in the aperture H. The upper portion62protrudes to an inner side of the aperture H further than the inner surface IF.

In the example shown inFIG.4, a thin film FL1is disposed on the upper portion62at the right side of the aperture H and a thin film FL2is disposed on the upper portion62at the left side of the aperture H. The thin films FL1and FL2are also disposed on an inner side of the aperture H. The thin films FL1and FL2disposed on the inner side of the aperture H are separated from the thin films FL1and FL2disposed on the upper portion62.

The thin film FL1disposed on the inner side of the aperture H is covered by the sealing layer SE11. Similarly, the thin film FL2disposed on the inner side of the aperture H is covered by the first sealing layer SE12. The first sealing layers SE11and SE12cover the inner surface IF as well.

At least a part of the inner side of the aperture H is filled by the second sealing layer SE2. The second sealing layer SE2continuously covers the first sealing layers SE11and SE12provided on the inner side of the aperture H.

The end portion EP of the lower electrode LE1is located, for example, below the lower portion61and is covered by the rib5. It is preferable that the aperture H should be provided at a position where it does not overlap the lower electrode LE1in plan view. In the example ofFIG.4, the end portion EP is located between the aperture H and the pixel aperture AP1. In this case, the entire aperture H does not overlap the lower electrode LE1. As another example, the aperture H may partially overlap the lower electrode LE1.

The light receiving element RC overlaps at least one aperture H in plan view. The light receiving element RC detects external light transmitted through the display panel PNL. The lower electrode LE1and the partition6have are light-shielding properties. Therefore, most of light L1incident on the display element DE1is shielded by the display panel PNL. The light L1can enter the light-receiving element RC through the space between the end portion EP of the lower electrode LE1and the partition6. However, the light will be extremely weak.

On the other hand, light L2traveling toward the aperture H passes through the display panel PNL without being shielded by the partition6and the lower electrode LE1. The light receiving element RC detects the light L2and outputs a detection signal according to its intensity and chromaticity.

When the wiring lines (scanning lines GL, signal lines SL and feed lines PL, etc.) contained in the circuit layer11shown inFIG.2are located below the partition6, it is preferable that the aperture H should be larger in width than that of the wiring lines. With this configuration, even when the aperture H and the wiring overlap each other, the intensity of light transmitted through the display panel PNL can be increased.

InFIG.4, the configuration of the partition6surrounding the subpixel SP1and its vicinity is mainly shown, but the configuration of the partition6surrounding the subpixels SP2and SP3and its vicinity is also similar to that of the example inFIG.4. In other words, the plurality of apertures H includes apertures H in which the thin film FL3and the first sealing layer SE13are arranged on their inner side. Further, preferably, each aperture H should not overlap any of the lower electrodes LE1, LE2and LE3.

Now, a method of manufacturing the display device DSP will be described.

FIG.5is a flowchart showing an example of a method of manufacturing the display device DSP.FIGS.6to15are schematic cross-sectional views each showing a respective part of the process of manufacturing the display device DSP. InFIGS.6to15, the substrate10and the circuit layer11are omitted from illustration.

In the manufacture of the display device DSP, first, the circuit layer11and the organic insulating layer12are formed on the substrate10(process P1). Further, the lower electrodes LE1, LE2and LE3are formed on the organic insulating layer12(process P2).

After the process P2, the rib5is formed on the lower electrodes LE1, LE2and LE3and the organic insulating layer12(process P3) as shown inFIG.6. Further, the partition6is formed on the rib5(process P4). Note here that the pixel apertures AP1, AP2and AP3of the rib5may be formed before or after the partition6.

In the process P4, first, as shown inFIG.7, a metal layer61a, which gives rise to the lower portion61, is formed on the rib5and the lower electrodes LE1, LE2and LE3, and a thin film62a, which gives rise to the upper portion62, is formed on the metal layer61a. Further, a resist R1is formed over the thin film62aaccording to the shape of the partition6. The resist R1comprises apertures Ha provided at respective locations where the apertures H are to be formed.

After forming the resist R1, as shown inFIG.8, the portion of the thin film62a, which is exposed from the resist R1, is removed, for example, by wet etching. Thus, the upper portion62is formed.

Then, anisotropic dry etching is performed to remove the portion of the metal layer61a, which is exposed from the resist R1as shown inFIG.9. Note that in the dry etching, the portion of the metal layer61a, which is exposed from the resist R1may be left thin.

Subsequently, isotropic wet etching is performed to erode side surfaces of the metal layer61aas shown inFIG.10. In this manner, the lower portion61with more recessed side surfaces than those of the upper portion62is formed, thus completing the partition6. Below the aperture Ha of the resist R1, the aperture H of the partition6is formed by a series of etching processes shown inFIGS.8to10. After the completion of the partition6, the resist R1is removed by a stripping solution as shown inFIG.11.

After the process P4, the display element DE1is formed (process P5). More specifically, as shown inFIG.12, an organic layer OR1is formed on the lower electrodes LE1, LE2and LE3, the rib5and the partition6by vapor deposition (process P11), an upper electrode UE1is formed on the organic layer OR1by vapor deposition (process P12), and a cap layer CP1is formed on the upper electrode UE1by vapor deposition (process P13). Further, the first sealing layer SE11is formed by chemical vapor deposition (CVD) (process P14).

Note that the process P11includes steps of sequentially forming thin films which constitute the organic layer OR1, such as the hole injection layer, hole transport layer, electron blocking layer, light emitting layer, hole blocking layer, electron transport layer, electron injection layer and the like. Further, the process P13includes steps of sequentially forming a plurality of thin films which constitute the cap layer CP1.

The organic layer OR1, the upper electrode UE1, the cap layer CP1and the first sealing layer SE11are formed at least over the entire display area DA, and are disposed not only in the subpixel SP1but also in the subpixels SP2and SP3. The organic layer OR1, the upper electrode UE1, the cap layer CP1and the first sealing layer SE11are formed inside the aperture H as well. The organic layer OR1, the upper electrode UE1and the cap layer CP1are divided by the overhanging partition6.

After the process P14, a resist R2is formed on the first sealing layer SE11as shown inFIG.13(process P15). The resist R2covers the subpixel SP1and a part of the partition6surrounding it.

Then, as shown inFIG.14, the organic layer OR1, the upper electrode UE1, the cap layer CP1and the first sealing layer SE11are patterned using the resist R2as a mask (process P16). This process includes dry etching and wet etching to sequentially remove the portions of the organic layer OR1, upper electrode UE1, cap layer CP1and first sealing layer SE11, which are exposed from the resist R2.

After process P16, the resist R2is removed by a stripping solution and residues such as the resist R2and the like are removed by asking (process P17). Thus, a substrate in which the display element DE1and the first sealing layer SE11are formed in the subpixel SP1can be obtained as shown inFIG.15.

After forming the display element DE1, the display element DE2is formed (process P6). The procedures for forming the display element DE2is similar to those of the processes P11to P17. That is, as in the cases of the processes P11to P14, the organic layer OR2, the upper electrode UE2and the cap layer CP2are formed in sequence by vapor deposition, and the first sealing layer SE12is formed by CVD.

After that, as in the case of the process P15, a resist is placed on the first sealing layer SE12, and as in the case of the process P16, the organic layer OR2, the upper electrode UE2, the cap layer CP2and the first sealing layer SE12are patterned. After this patterning, the resist is removed as in the case of the process P17.

Through the above-described processes, a substrate in which the display element DE1and the first sealing layer SE11are formed in the subpixel SP1and the display element DE2and the first sealing layer SE12are formed in the subpixel SP2, can be obtained.

After forming the display element DE2, the display element DE3is formed (process P7). The procedures for forming the display element DE3are similar to those of the processes P11to P17. That is, as in the cases of the processes P11to P14, the organic layer OR3, the upper electrode UE3and the cap layer CP3are formed in sequence by vapor deposition, and the first sealing layer SE13is formed by CVD.

After that, as in the case of the process P15, a resist is placed on the first sealing layer SE13, and as in the case of the process P16, the organic layer OR3, the upper electrode UE3, the cap layer CP3and the first sealing layer SE13are patterned. After this patterning, the resist is removed as in the case of the process P17.

Through the above-described processes, a substrate in which the display element DE1and the first sealing layer SE11are formed in the subpixel SP1, the display element DE2and the first sealing layer SE12are formed in the subpixel SP2and the display element DE3and the first sealing layer SE13are formed in the subpixel SP3, can be obtained.

After the process P7, the second sealing layer SE2, the resin layer13and the third sealing layer SE3shown inFIG.3are formed in sequence (process P8). Thus, the display device DSP is completed. Note that the above-described manufacturing processes are based on an assumption that the display element DE1is formed first, then the display element DE2, and finally the display element DE3, but the formation order of the display elements DE1, DE2and DE3is not limited to that of this example.

In this embodiment, the partition6of the overhanging state is provided at the boundaries of subpixels SP1, SP2and SP3. In this case, the organic layers OR1, OR2and OR3, the upper electrodes UE1, UE2and UE3and the cap layers CP1, CP2and CP3, which are formed by vapor deposition, are divided by the partition6. By covering the respective layers thus divided, by the first sealing layers SE11, SE12and SE13, the individually sealed display elements DE1, DE2and DE3can be obtained. When the display elements DE1, DE2and DE3are individually sealed, even if a defect such as the entering of moisture occurs in any one of the display elements, the adverse effect which may spread to other display elements can be suppressed.

Further, in this embodiment, the first sealing layers SE11, SE12and SE13are continuously covered by the second sealing layer SE2. With this configuration, the display elements DE1, DE2and DE3can be more reliably sealed.

The lower portion61of the partition6serves to feed electricity to the upper electrodes UE1, UE2and UE3and is formed of a light-shielding metal material such as aluminum. Further, the lower electrodes LE1, LE2and LE3, which reflect light, are arranged in the region surrounded by the partition6. In such a configuration, the light transparency in the display area DA is significantly reduced.

By contrast, in this embodiment, the apertures H are made in the partition6. With this configuration, the transparency of the display panel PNL can be enhanced. When the light transparency of the display panel PNL is increased, external light can be detected through the display panel PNL even if the light receiving element RC is arranged over the display panel PNL, as described above with reference toFIG.4, for example.

In the example ofFIG.2, the aperture H is provided at each of the intersections of the first partitions6xand the second partitions6y. At such intersections, the partition6is thicker, and therefore it is possible to make a larger aperture H as compared to at other parts of the partition6.

In addition to the above, various other advantageous effects can be obtained from this embodiment.

Second Embodiment

The second embodiment will now be described. As to the configurations not specifically referred to, similar ones to those in the first embodiment can be applied.

FIG.16shows a schematic cross-sectional view of a display device DSP of the second embodiment. In this figure, the substrate10, the circuit layer11, the resin layer13and the third sealing layer SE3are omitted from illustration as in the case ofFIG.4.

In this embodiment, the thin films FL1and FL2and the first sealing layers SE11and SE12are not disposed on an inner side of the aperture H. The inner surface IF of the aperture H is covered by the second sealing layer SE2. The recess created in the second sealing layer SE2inside the aperture H is filled by the resin layer13.

InFIG.16, the configuration of the partition6surrounding the subpixel SP1and its vicinity is mainly shown, but the configuration of the partition6surrounding the subpixels SP2and SP3and its vicinity is also similar to that of the example inFIG.16. In other words, in this embodiment, the thin films FL1, FL2and FL3are not disposed on the inner side of each aperture H.

Note here that all the apertures H in the partition6do not necessarily have to have the configuration shown inFIG.16. For example, the thin films FL1, FL2and FL3may be disposed as in the example ofFIG.4on the inner side of at least one aperture H.

Although the thin films FL1, FL2and FL3are translucent, they absorb or reflect some of the light that passes therethrough. In the apertures H where the thin films FL1, FL2and FL3are not disposed as seen in the example ofFIG.16, such absorption or reflection does not occur, and thus the transparency of the display panel PNL can be further enhanced.

Note here that when the thin films FL1, FL2and FL3are not disposed in the apertures H, the rib5may be exposed to the etching of the first sealing layers SE11, SE12and SE13through the apertures H in the patterning process P16shown inFIG.14. When the rib5is formed of the same material as that of the first sealing layers SE11, SE12and SE13, the rib5may be damaged by this etching.

In order to avoid this, it is preferable that at least the topmost surface of the rib5be formed of a material whose etching rate for the first sealing layers SE11, SE12and SE13is lower than that of the first sealing layers SE11, SE12and SE13for this etching. For example, such a relationship of etching rate can be achieved when the first sealing layers SE11, SE12and SE13are formed of silicon nitride and the rib5is formed of silicon oxide or silicon oxynitride.

Third Embodiment

The third embodiment will now be described. As to the configurations not specifically referred to, similar ones to those in the above-provided embodiments can be applied.

FIG.17is a schematic plan view of apertures H according to the third embodiment. In this embodiment, the apertures H have polygonal shapes.

More specifically, a plurality of apertures H arranged in the display area DA include cross-shaped first apertures H1and T-shaped second apertures H2. The first apertures H1are each provided at the intersections where the first partitions6xand the second partitions6yintersect in a cross-shaped manner, respectively. The second apertures H2are each provided at the intersections where the first partitions6xand the second partitions6yare connected in a T-shape manner, respectively.

As in this embodiment, by providing apertures H of different shapes according to the respective shapes of the intersections of the first partitions6xand the second partitions6y, the area of the apertures H can be increased. With this configuration, the transparency of the display panel PNL can be further improved.

Fourth Embodiment

The fourth embodiment will now be described. As to the configurations not specifically referred to, similar ones to those in the above-provided embodiments can be applied.

FIG.18is a schematic plan view of an example of the apertures H according to the fourth embodiment.FIG.19is a schematic plan view showing another example of the apertures H for the fourth embodiment. As shown in these figures, in this embodiment, the apertures H are slits. In the following description, the apertures H shown inFIG.18are referred to as apertures Hx and the apertures H shown inFIG.19are referred to as apertures Hy.

In the example ofFIG.18, the apertures Hx are provided in the first partitions6x. The apertures Hx extend long in the first direction X. The direction of extension of the apertures Hx is parallel to the scanning lines GL shown inFIG.1. For example, the length of the apertures Hx is greater than the width of the pixel apertures AP1, AP2and AP3along the first direction X. The apertures Hx may be formed continuously or intermittently from one end to the other end of the display area DA along the first direction X.

In the example ofFIG.19, the apertures Hy are provided in the second partitions6y. The apertures Hy extend long in the second direction Y. The direction of extension of the apertures Hy is parallel to the signal lines SL shown inFIG.1. For example, the length of the apertures Hy is greater than the width of the pixel apertures AP1, AP2and AP3along the second direction Y. The apertures Hy may be formed continuously or intermittently from one end to the other end of the display area DA along the second direction Y.

For the apertures Hx, Hy, the configuration shown, for example, inFIG.4orFIG.16can be applied. The partitions6with the apertures Hx and Hy can be fabricated by the processes shown inFIGS.6to11, for example. At least a portion of the apertures Hx and Hy overlap the light receiving elements RC shown inFIGS.1and3in plan view.

Note that the partition6may as well include both apertures Hx and Hy. In this case, the apertures Hx and the apertures Hy may be connected respectively at the intersections of the first partitions6xand the second partitions6y.

With such slit-shaped apertures H (Hx and Hy) provided as in this embodiment, the area of the apertures H can be further increased than that of each of the above-provided embodiments. With this configuration, the transparency of the display panel PNL can be further improved.

All of the display devices and manufacturing methods therefor that can be implemented by a person of ordinary skill in the art through arbitrary design changes based on the display devices and the manufacturing methods described above as the embodiments and the modified examples of the present invention come within the scope of the present invention as long as they are in keeping with the spirit of the present invention.

Various modification examples which may be conceived by a person of ordinary skill in the art in the scope of the idea of the present invention will also fall within the scope of the invention. For example, even if a person of ordinary skill in the art arbitrarily modifies the above embodiments by adding or deleting a structural element or changing the design of a structural element, or adding or omitting a process or changing the condition of a process, all of the modifications fall within the scope of the present invention as long as they are in keeping with the spirit of the invention.

Further, other effects which may be obtained from each of the above embodiments and modified examples and are self-explanatory from the descriptions of the specification or can be arbitrarily conceived by a person of ordinary skill in the art are considered to be naturally brought about by the present invention as a matter of course.