Inter-stage matching network to enhance common mode stability

A two stage amplifier with an inter-stage matching network constituted of a first and a second transistor forming a differential first stage, a third and a fourth transistor forming a differential second stage, an on-chip connection path connecting the emitters of the first and second transistor to the emitters of the third and fourth transistors, a first transformation network and a second transformation network. A collector of the first transistor is operatively connected to a base of the third transistor by the first transformation network and a collector of the second transistor is operatively connected to a base of the fourth transistor by the second transformation network. At least one resistor is provided in the on-chip connection path to stabilize the input of the third and fourth transistors.

FIELD OF THE INVENTION

The present invention relates to differential RF/microwave multi-stage integrated circuit amplifiers, and more particularly to inter-stage matching networks to enhance common mode stability in differential amplifier designs.

BACKGROUND OF THE INVENTION

Referring toFIG. 1, integrated Circuit RF/Microwave amplifiers are typically constructed of multiple amplification stages10,11and12connected in series on a single semiconductor die05. First stage10connects to a signal source though an input impedance transformation network (not shown) that may be fabricated on-chip or off-chip, and last stage12connects to a load impedance through an output impedance transformation network (not shown) that also may be fabricated on-chip or off-chip. For amplifiers that have three or more stages, there will be one or more amplifier stages (for example stage11) that are terminated on both their input and output by another amplifier stage. This applies to any amplification stage located between first10and last stage12. The networks connecting these middle stages are referred to as inter-stage transformation networks.

The design and performance of inter-stage transformation networks is a major contributor to overall amplifier performance. Of particular interest for this invention is the role that the inter-stage networks play in preventing unwanted oscillations from occurring in the amplifier. The complexity of the design of inner-stage networks is reduced in many semiconductor technologies due to the presence of through-substrate vias. A through-substrate via is a path that penetrates the top semiconductor substrate surface where the active (and passive) devices are fabricated and connects directly to the bottom semiconductor substrate surface which is a metalized ground plane. The prevalent technology in the field of RF/Microwave amplifiers with through-substrate vias is Gallium Arsenide (GaAs). For technologies such as Si and SiGe, through-substrate vias are not an option since there is no bottom ground plane.

When developing RF/Microwave amplifiers in technologies that lack through-substrate vias, grounding becomes an important and difficult problem. The only means for connecting a Si amplifier circuit to ground is through the use of wirebonds that go between the chip and the package ground plane. The parasitic inductance from these wirebonds introduces a significant amount of inductance between the amplifier circuit and ground.

A common method for overcoming grounding problems is to utilize a differential amplifier topology. As one skilled in the art will understand, a differential amplifier topology allows for a virtual ground to be generated on-chip that will be independent of the amount of wirebond inductance present. By making use of this virtual ground, a high-performance differential circuit may be designed. Any input signal to a differential amplifier may be separated into differential-mode and common-mode components. As the name implies, the differential-mode signal is the primary mode of operation for the amplifier. However the common-mode performance of the amplifier must also be considered to ensure proper amplifier operation.

The virtual ground created in a differential amplifier is only present for differential-mode signals. All of the parasitic wirebond inductance is present for common-mode signals and presents numerous problems. Of particular concern is the reduced stability of the amplifier in the common-mode. The primary cause of the reduced common-mode stability results from the inductance caused by wirebonds13,14, and15. The large inductance associated with wirebond14, which is in series with the emitters of transistors43and44can cause devices43and44to become unstable. This is not a concern for the differential-mode signal since RF current does not flow through the wirebonds as shown by the equivalent differential-mode circuit shown inFIG. 3.

Another approach to reduce the effects of the inductance associated with wirebond14is to reduce the common-mode gain in order to improve the active device's stability. This can be done by adding resistive loss to the inter-stage network that only affects the common-mode signal. This allows for the differential mode signal to be unaffected while helping to stabilize the common-mode.

SUMMARY OF THE INVENTION

The present invention recognizes and addresses the foregoing considerations, and others, of prior art constructions and methods.

These and/or other objects are achieved by an amplifier comprising a first stage having at least one first transistor, and at least one second transistor, a second stage having at least one third transistor, and at least one fourth transistor, a first transformation network having a first ground and a second ground, and a second transformation network having a third ground and a fourth ground. The amplifier has a collector of the at least one first transistor is operatively connected to a base of the at least one third transistor by the first transformation network, a collector of the at least one second transistor is operatively connected to a base of the at least one fourth transistor by the second transformation network, the first ground and the third ground are electrically connected to each other, the second ground and the fourth ground are electrically connected to each other, an emitter of the at least one first transistor and an emitter of the at least one second transistor are electrically connected to the first ground and the third ground, and the second ground and the fourth ground are electrically connected to an emitter of the at least one third transistor and an emitter of the at least one fourth transistor.

In one embodiment, the electrical connection between the second and the fourth grounds and the at least one third and the at least one fourth transistor emitters further comprises a resistor. In another embodiment, the electrical connection between the first and the third grounds and the electrical connection between the second and fourth grounds are connected by at least a resistor. In another embodiment, the electrical connection between the first and the third grounds and the at least one first and the at least one second transistor emitters further comprises a resistor. In yet another embodiment, the electrical connection between the first and the third grounds and the electrical connection between the second and fourth grounds are connected by at least one resistor. In still other embodiments, the at least one first transistor further comprises a plurality of transistors connected in parallel, the at least one second transistor further comprises a plurality of transistors connected in parallel, the at least one third transistor further comprises a plurality of transistors connected in parallel, and the at least one fourth transistor further comprises a plurality of transistors connected in parallel.

In some of the embodiments, the electrical connections contain parasitics, where the parasitics may contain one or more resistive or inductive properties. In some of these embodiments, the at least one first, the at least one second, the at least one third, and the at least one fourth transistors are bipolar junction transistors. In some of these embodiments, the at least one first, the at least one second, the at least one third, and the at least one fourth transistors are bipolar junction transistors. In yet other of these embodiments, the at least one first, the at least one second, the at least one third, and the at least one fourth transistors are field effect transistors. Still in other embodiments, the at least one first, the at least one second, the at least one third, and the at least one fourth transistors are three terminal transconductance amplifier devices.

DETAILED DESCRIPTION OF INVENTION

This invention provides a means for improving common-mode stability in multi-stage differential amplifiers. Common-mode stability is achieved by implementing circuitry to both reduce common-mode gain, provide an on-chip ground path, and to provide stabilizing positive resistance at the active device only for the common-mode. Additionally, effects causing the reduction of amplifier output are minimized by reducing the leakage of signal from one stage of the amplifier to a preceding stage.

Referring toFIG. 2, an on-chip connection35is made from the emitters of transistors41and42to the emitters of transistors43and44. In addition to connecting the emitters of the transistors, connection35also connects to all of the shunt components in inter-stage network36. The addition of on chip-connection35provides an on-chip ground return path for the common-mode RF signal between amplifier stages11and12. On-chip connection35can be modeled as a series inductance between amplifier stages11and12, which is effectively in parallel with the inductances created by wirebonds13and14. The parallel combination of the inductances results in an inductance that is smaller than the inductance of wirebonds13and14individually. However, the resultant parallel inductance is still large enough to cause common-mode stability problems.

To account for the common-mode stability problems caused by the resultant parallel inductance, a resistor,31, is placed between the emitters of transistors43and44and the nearest shunt inter-stage network connection52. Resistor31is a series component in the on-chip ground connection35. The addition of resistor31has no impact on the differential-mode signal, as can be seen inFIG. 3since in the differential mode on-chip connection35effectively is seen as ground. Resistor31, however, does play an important role for common-mode signals, as seen inFIG. 4. In particular, resistor31causes the impedance of the shunt elements connected to node52to have a large positive real component of impedance. This positive real impedance component helps stabilize the input of transistors43and44by cancelling any potential negative real part impedance generated by transistors43and44, in addition to increasing the loss of network36(FIG. 2) for common-mode signals thus reducing the common mode gain of amplifier13.

An appropriate value for resistor31may be determined through the observation of the small-signal stability of amplifier stage11as the value of resistor31is varied. Resistor31should be of a large enough value to ensure that the amplifier is satisfactorily stable. Rollett's stability factor (K) may also be used as an appropriate measure of amplifier stability. As one skilled in the art would recognize, by selecting a value of resistor31that results in a Rollett's stability factor of above one at all frequencies of interest, the amplifier should be unconditionally stable. A practical method for determining an appropriate value of resistor31is by creating an electrical model of the full differential amplifier inFIG. 1, including all wirebond paracitics. One skilled in the art may then use a RF circuit simulator, such as Agilent's Advanced Design System, to simulate this electrical model and observe the stability at the input of amplifier stage11when driven with both differential and common mode signals.

Referring toFIG. 4, the addition of on-chip ground connection35creates a feedback path35for signals from amplifier stage22back into stage21. Current exiting the emitters of transistors43during large-signal excitation has two ground return paths. One path is directly through wirebond14and the other path is through on-chip ground connection35and through wirebond13to ground. This path creates a feedback signal at the emitters of transistors41that may reduce the amount of output power that amplifier stage21is capable of delivering. To prevent the reduction of output power from stage21, an additional resistor32may be placed in on-chip ground connection35to isolate the current due to stage22by forcing it through wirebond14rather than both wirebond13and14. This is of particular concern for large signal levels as both differential-mode and common-mode signals will generate currents that can leak from stage22back trough connection35into stage21.

A suitable value for resistor32may be determined by observing the effect of resistor32on the differential output power at which amplifier stage21compresses. Resistor32should be increased until the compression level of amplifier stage21becomes insensitive to small variations in resistor32. One skilled in the art could perform such an analysis by performing a harmonic balance simulation, utilizing a simulation tool such as Agilent's Advanced Design System, on a complete electrical model of the amplifier inFIG. 1. Such a model should include all wirebond paracitics and incorporate non-linear device models for the active components.

FIG. 5illustrates a high level schematic diagram of the amplifier ofFIG. 2wherein each of the transistors comprises a plurality of transistors, illustrated without limitation as FET transistors. In further detail, the amplifier ofFIG. 5comprises: an on-chip connection35; a plurality of FET transistors41connected in parallel; a plurality of FET transistors42connected in parallel; a plurality of FET transistors43connected in parallel; a plurality of FET transistors44connected in parallel; a first transformation network125; and a second transformation network150. On-chip connection35comprises: a resistor31, denoted R1and connected between node50and node52of on-chip connection35; and a resistor32, denoted R2and connected between node52of on-chip connection35and the common sources of plurality of FET transistors43and plurality of FET transistors44. On-chip connection35connects the common sources of plurality of FET transistors43and44to the common sources of plurality of FET transistors41and42. First transformation network125and second transformation network150form inter-stage network36as described above in relation toFIG. 2. Alternatively, transistors41,42,43and44may be replaced with three terminal transconductance amplifier devices.

While one or more preferred embodiments of the invention have been described above, it should be understood that any and all equivalent realizations of the present invention are included within the scope and spirit thereof. The embodiments depicted are presented by way of example only and are not intended as limitations upon the present invention. Thus, it should be understood by those of ordinary skill in this art that the present invention is not limited to these embodiments since modifications can be made. Therefore, it is contemplated that any and all such embodiments are included in the present invention as may fall within the scope and spirit thereof.