Programmable core for implementing logic change

An apparatus comprising a plurality of fixed logic circuits, wherein each of the fixed logic circuits is configured to receive a plurality of input signals, perform combinational logic operations using the input signals, and produce at least one output signal, and wherein the combinational logic operations are substantially fixed; and a programmable logic core configured to functionally replace a selected subset of the plurality of fixed logic circuits, receive the input signals of the selected subset of the plurality of fixed logic circuits, perform logic operations on the input signals, and produce at least one output signal as the output signal of the selected subset of the plurality of fixed logic circuits, and wherein the logic operations are dynamically changeable.

TECHNICAL FIELD

This description relates to implementing logic changes or additions to a fixed logic system and more specifically to using a programmable logic core for implementing changes or additions to a fixed logic system.

BACKGROUND

The growing complexity of integrated circuits or microchips has led to a gap between what can be designed and what can be verified in a reasonable amount of time. As a result, there are frequently chips that are designed, manufactured, and then considered unusable. There may be numerous reasons why a chip is deemed unusable or in need of modification, but the most common design faults are: design errors or bugs, performance issues, inoperability and non-compliance to a standard. Often when a chip is deemed unsuitable for use, the chip need only be partially redesigned to correct its design faults. Furthermore, usually only a few logic elements need to be changed to fix the design faults.

Currently when a chip needs modification to fix design faults, designers often have two options. The first option is referred to as a “re-spin”. Typically in a re-spin, the entire layout or blueprint for the chip manufacturing is redone or reassembled. The second option is to use unused logic elements that were placed on the chip, called spare-gates, to fix design faults. Often both options require the chip layout to be rebuilt by the manufacturer, but the use of spare-gates or an Engineering Change Order (ECO) is often a more attractive option in terms of cost as only a few metal masks usually need to be rebuilt as opposed to a change of the entire mask set for a re-spin. This usually saves time and money compared to a full re-spin. However, an ECO can handle only a finite number of changes and so the decision may depend on the amount of logic that needs changing.

SUMMARY

A system and/or method for processing information, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

DETAILED DESCRIPTION

FIG. 1is a block diagram of an example embodiment of an apparatus100for implementing logic changes in accordance with the disclosed subject matter. In one embodiment, the apparatus100may include a plurality of fixed logic circuits104and104n, and a programmable logic core102.

In one embodiment, the fixed logic circuit104may receive a plurality of input signals106. In various embodiments, the fixed logic circuit104may include at least one combinational logic block108to produce an output signal110by performing logical operations on the input signals106. In such an embodiment, the combinational logic block108may include various Boolean logic operations (e.g., NAND, NOR, NOT, XOR, etc.), stabilizing logic devices (e.g., flip-flops, latches, etc.), other logic devices, or a combination thereof. These combinational logic operations may be configured in simple or complex fashion to process the input signals106to achieve a desired result. It is understood that while a few illustrative examples of synchronous combinational logic operations are described, the disclosed subject matter is not so limited and may include asynchronous operations, or a mixture thereof.

In various embodiments, the combinational logic operations or combinational logic block108may be substantially fixed. In one embodiment, the combinational logic operations may comprise a plurality of complementary metal oxide semiconductors (CMOS) transistors. In various embodiments, these CMOS transistors may be arranged into gates that perform the logical operations; although it is understood that other technologies may be used and are within the scope of the disclosed subject matter.

In such an embodiment, the majority of the combinational logic operations may be unchangeable once the integrated circuit or circuit in general has been manufactured. In some embodiments, the combinational logic block108may include a number of spare-gates. In such an embodiment, these spare-gates may be unused gates that may be connected via a process similar or analogous to the Engineering Change Order (ECO), as described above. In one embodiment, a change may include effectively “de-soldering” the metal connections between selected used gates, and effectively “re-soldering” a connection with the spare-gates in a desired fashion. In another embodiment, the “soldering” may involve altering a metal mask associated with the manufacture of the fixed logic circuit104and producing another chip. Also, various techniques may be used to make minor but non-trivial changes to optical technology embodiments of the fixed logic circuit104. Therefore, because such alterations may be possible but non-trivial and/or costly, the combinational logic operations108or the fixed logic circuit104may be described as fixed or substantially fixed. Although, it is understood that the above are merely a few illustrative examples to which the disclosed subject matter is not limited.

In some embodiments, the fixed logic circuit104may include errors or otherwise undesirable combinational logic operations. In various embodiments, it may be desirable to ameliorate or fix these errors or undesirable operations. In one embodiment, the apparatus100may include a programmable logic core102. In such an embodiment, the programmable logic core102may be configured to receive a plurality of input signals (e.g., input signals106and106nvia input ports122and122n), perform logic operations on the input signals, and produce at least one output signal (e.g., output signals112and112nvia output ports124and124n). Furthermore, in one embodiment, the programmable logic core102may include logic operations that, unlike the fixed logic circuits104, are dynamically configurable.

In various embodiments, the programmable logic core102may include one or more of a plurality of programmable logic technologies. Various embodiments of programmable logic cores102may include slightly different architecture and programming technology, and thus each may have various respective strengths and weaknesses. It is understood that the programmable logic core102depicted in the disclosed subject matter may be implemented using any programmable logic technologies.

In some embodiments, the programmable logic core102may include a programming technology portion101and a logic block technology portion103. In one embodiment, the programmable technology portion101may include programming technology such as, for example, static random access memory (SRAM), electronically erasable programmable read-only-memory (EEPROM), Anti-fuse, Via™ based technologies, etc. These technologies may offer, in one embodiment, relatively easy configuration and re-configurability when placed in an integrated circuit (IC). In addition, in some embodiments (e.g., SRAM), circuits may use a standard CMOS process and therefore can be easily incorporated into the IC design and fabrication flow.

In one embodiment, the logic block technology portion103may be implemented using, for example, a product term based architecture (e.g., an Altera™ field-programmable gate arrays (FPGA)), a look-up table architecture (e.g., a Xilinx™ FPGA), or another technology. The programmable logic core102may be configured to implement various logic function(s) using the given inputs. In a specific illustrative embodiment, an SRAM programming technology portion101may be configured to use a look-up table (LUT) based logic block technology portion103. Although, it is understood that the above are merely a few illustrative examples to which the disclosed subject matter is not limited.

As described above, in one embodiment, the programmable logic core102may receive input signals122and122n, perform the configured logic operations on the received signals, and produce output signals112and112n. In some embodiments, the fixed logic circuit104may receive the output signal112from the programmable logic core102. In various embodiments, the fixed logic circuit104may be configured to select between the output signal110produced by the combinational logic108and the output signal112produced by the programmable logic core102. In such an embodiment, a selected fixed logic circuit104may be functionally replaced by a portion of the programmable logic core102, as described in more detail below.

In one embodiment, the fixed logic circuit104may include a selection device, such as for example a multiplexer114to select between the output signal110produced by the combinational logic108and the output signal112produced by the programmable logic core102. In such an embodiment, a control signal116may be used to select between the two output signals. In another embodiment, an equivalent selection may occur in fixed logic circuit104nusing selection device114nand control signal116n.

In yet another embodiment, the input signals106from fixed logic circuit104may be received by the programmable logic core102and processed to create output signal112n. In such an embodiment, both fixed logic circuits104and104nmay be functionally replaced. In other embodiments, a plurality of fixed logic circuits may be functionally replaced. In some embodiments, all or a portion of the input signals from the replaced fixed logic circuits may be input to the programmable logic core102, depending upon the needs of the configured logic.

FIG. 2is a block diagram of an example embodiment of an apparatus200for implementing logic changes in accordance with the disclosed subject matter. In one embodiment, the apparatus200may include a fixed logic circuit204, and a programmable logic core202. Apparatus200includes a specific illustrative embodiment showing how the combinational logic operation(s)208of the fixed logic circuit204may be functionally replaced by a portion226of the programmable logic core202.

In one embodiment, the input signals206aand206bmay be input to both the fixed logic circuit204and the programmable logic core202. Within the fixed logic circuit204, the input signals206aand206bmay be processed by combinational logic operation(s)208to produce the output signal210. In the illustrated embodiment, the combinational logic operation may be a Boolean AND. In one embodiment, the output signal210may then be stabilized using a flip-flop218before being ultimately output via signal220. In various embodiments, this output signal220may be an input signal to another fixed logic circuit.

In the specific illustrative embodiment, after the manufacture of the apparatus200, it may be noticed that the combinational logic operation208of the fixed logic circuit204is not correct, in error, or otherwise undesirable. In such an embodiment, the programmable logic core, or a portion thereof, may be dynamically configured to provide an alternative logic operation to that of the fixed logic circuit204. In the illustrated embodiment, the programmable logic core202may be configured to perform an XOR logic operation226on the input signals206aand206b, and output the output signal212.

In one embodiment, the fixed logic circuit204may be configured to route the output signal212of the programmable logic core202as the output of the fixed logic circuit204. In various embodiments, the dynamic routing may occur using a multiplexer214to select between the output signal210of the combinational logic operation208(e.g., the AND gate) or the output signal212of the programmable logic operation226(e.g., the XOR gate). In the illustrated embodiment, a control signal216may be used to determine whether or not the output signal212is dynamically routed or selected as the output of the fixed logic circuit204. In some embodiments, the control signal216may be produced using a programmable switch (not shown). By selecting between the two output signals the fixed logic circuit204may be functionally replaced by the configured portion of the programmable logic core202.

Such a replacement may allow the error or otherwise undesirable result produced by the combinational logic operations208to be changed and/or repaired. In one embodiment, the programmable logic core202may allow designers to test various proposed logic operations before determining the desired logic operation to use. For example in the illustrative embodiment, the programmable logic core202may be programmed to perform the XOR operation. However, if that result too is deemed to be undesirable the programmable logic core202may be re-programmed to perform another operation (e.g., NOR). If that too is deemed undesirable the programmable logic core202may be re-programmed again to perform yet another operation (e.g., NAND). This process may continue until a desired logic operation is found. Furthermore, in yet another embodiment, more fixed logic circuits (not shown) may be functionally replaced by the programmable logic core202if needed or desired. In one embodiment, once a desired logic operation has been determined, the fixed logic circuit204may be altered to reflect the desired logic operation in a subsequent manufacture of the apparatus200(e.g., a “re-spin” of the apparatus200or an integrated circuit comprising the apparatus200).

FIG. 3is a block diagram of an example embodiment of an apparatus300for implementing logic changes in accordance with the disclosed subject matter. In one embodiment, the apparatus300may include a plurality of fixed logic circuits104and104nand the programmable logic core102, as described above in reference toFIG. 1.

However, apparatus300may also illustrate that the plurality of fixed logic circuits104may include stages in a processing pipeline. In various embodiments, a processing pipeline may include a sequence of stages a computer or processing device uses to process data or carry out instructions. In some embodiments, the processing of data may take multiple computer clock cycles. By breaking the processing down into a plurality of smaller steps processing on a subsequent piece of data may be started before the processing of the prior piece of data is fully completed. Frequently, as a stage of a pipeline finishes manipulating data, it hands the results to the next stage and gets another piece of data from the stage before it, moving several pieces of data along the pipeline simultaneously. Visually, one might think of the classic Ford Model-T assembly line as analogous to a pipelined IC architecture. In various embodiments, a device may include multiple pipelines or pipelines that allow for branching.

In one embodiment, the programmable logic core102may be configured to functionally replace a fixed logic circuit104and therefore a stage of the processing pipeline, as described above. In such an embodiment, the programmable logic core102may use the input signals106of one stage104and provide input signals106n(output signals from the programmable logic core's point of view) to the subsequent stage104n.

In another embodiment, the programmable logic core102may be configured to provide additional pipe-stages or functionality. In such an embodiment, the programmable logic core102may be configured to receive input signals106xvia input terminal122xthat are the output signals106xof the last or a given stage104nin the pipeline. The programmable logic core102may be configured to perform logic operations on the input signals106xand produce at least one output signal112xvia output terminal124x. In one embodiment, a selection device114xmay be configured to select whether the output signal112xof the programmable logic core102or the output signal106xof the fixed logic circuit104nis to be output signal120.

In such an embodiment, the programmable logic core102may be configured to include at least one additional stage in the processing pipeline that is dynamically configurable. It is understood that such an additional stage may be added in between two or more existing pipe-stages. Furthermore, it is understood that while such a stage may, in one embodiment, be added for testing purposes, in another embodiment, the additional stage may be used to add additional features not desired or contemplated when the apparatus300was manufactured.

In one embodiment, the plurality of fixed logic circuits (e.g., fixed logic circuits104and104n) may include stabilizing logic devices (e.g., flip-flops118and118n). In one illustrative embodiment, these stabilizing logic devices may allow each pipe-stage to use a differing amount of time to process their respective input signals while conforming to an overall timing requirement; although it is understood that the above is merely one illustrative example to which the disclosed subject matter is not limited. In various embodiments, these stabilizing logic devices may include devices such as flip-flops, latches, etc. In one embodiment, the input signals (e.g., input signals106,106n, and106x) may be the output of a stabilizing logic device (e.g., flip-flops118and118n).

FIG. 4is a block diagram of an example embodiment of a system400for implementing logic changes in accordance with the disclosed subject matter. In one embodiment, the system400may include a programmable logic core402, a plurality of fixed logic circuits404, and a permutation network of switches408. In various embodiments, the system400may include or be included as part of a microchip, integrated circuit, or processor. In some embodiments, the plurality of fixed logic circuits404may be configured to provide superior speed and power usage compared to the programmable logic core402. In some embodiments, the fixed logic circuits404may be optimized due to being synthesized from written source code, or, in another embodiment, laid out manually to perform the specific logic operations. Whereas, the programmable logic core402may be more generic and therefore less optimized.

In one embodiment, the plurality of fixed logic circuits404may include a number of input signals that may be selected as the input signals to the programmable logic core402. In various embodiments, the plurality of fixed logic circuits404may include far more input signals than can be or are desirable to be input into the programmable logic core402. In such an embodiment, the total number of possible input signals may be considered to be relatively very large. From that relatively very large number of total input signals to the fixed logic circuits404, a relatively small number of the possible input signals may be selected to be input into the programmable logic core402. In another embodiment, it may be desirable to make a relatively medium number of input signals available to the programmable logic core402, and then dynamically select a fewer (relatively small) number to actually be routed as inputs to the programmable logic core402. As such, a subset of the fixed logic circuits404may be selected to be replaced or used by the programmable logic core402.

In such an embodiment, the permutation network of switches408may be configured to dynamically route a selected subset of the relatively large number of input signals of the plurality of fixed logic circuits404to a relatively smaller number of the inputs signals of the programmable logic core402. In various embodiments, the permutation network of switches408may include an input permutation network of switches409configured to perform this dynamic routing. In one embodiment, the relatively large number (e.g., 32) of input signals406may be routed from the plurality of fixed logic cores404to the permutation network of switches408.

In one embodiment, the permutation network of switches408may be configured to dynamically map a selected subset of the relatively large number of input signals406from the plurality of fixed logic circuits404to the relatively smaller number (e.g., 8) of input signals422to the programmable logic core402. It is understood that in various embodiments, not all of the input signals422to the programmable logic core402may be used, and therefore, in some of these embodiments the permutation network of switches408may be configured to map the unused portion of the input signals422to a fixed or known value (e.g., “high”, “low”, etc.).

Likewise, in one embodiment, the plurality of fixed logic circuits404may include a number of output signals that may be selected to receive or be mapped to the output signals to the programmable logic core402. In various embodiments, the plurality of fixed logic circuits404may include more output signals than can be or are desirable to be produced by the programmable logic core402. In some embodiments in which the fixed logic circuits404include an output signal selection device, the concern may be the amount of routing needed between the programmable logic core402and the fixed logic circuits404; although, it is understood that the above is merely an illustrative example to which the disclosed subject matter is not limited. In such an embodiment, a number of the possible output signals may be selected to be output from the programmable logic core402. In another embodiment, it may be desirable to make a medium number of output signals available to the programmable logic core402, and then select a fewer number to actually be routed as outputs from the programmable logic core402. As such, a subset of the fixed logic circuits404may be selected to be replaced or used by the programmable logic core402.

In such an embodiment, the permutation network of switches408may be configured to dynamically route a portion of the output signals of the programmable logic core402to a selected subset of the output signals of the plurality of fixed logic circuits404. In various embodiments, the permutation network of switches408may include an output permutation network of switches410configured to perform this dynamic routing.

In one embodiment, a relatively small number (e.g., 4) of output signals424from the programmable logic core402may be routed to the permutation network of switches408. In one embodiment, the permutation network of switches408may be configured to map a relatively small number (e.g., 4) of output signals424from the programmable logic core402to a selected subset of the relatively large number (e.g., 24) of output signals412of the plurality of fixed logic circuits404. It is understood that in various embodiments, not all of the output signals412to the plurality of fixed logic circuits404may be used, and therefore, in some of these embodiments the permutation network of switches408may be configured to map the unused portion of the output signals412to a fixed or known value (e.g., “high”, “low”, etc.).

FIG. 5is a block diagram of an example embodiment of an apparatus500for routing signals in the aid of implementing logic changes in accordance with the disclosed subject matter. In one embodiment, the permutation network of switches508may include a three-stage network of switches. In such an embodiment, the permutation network of switches508may include a wide network stage502, a joint network stage504, and a narrow network stage506. These stages may be configured to map a relatively large number (M) of inputs to a relatively small number (N) of outputs, or vice versa.

FIG. 6is a block diagram of an example embodiment of an apparatus600for routing signals in the aid of implementing logic changes in accordance with the disclosed subject matter. In one embodiment, the permutation network of switches600may include a wide network stage602, a joint network stage604, and a narrow network stage606.FIG. 6illustrates an embodiment in which 8 inputs may be mapped to 4 outputs forming an 8-by-4 permutation network of switches. However, other embodiments may include an M-by-N permutation network of switches configured to map a relatively large number (M) of inputs to a relatively small number (N) of outputs. Also, the terms “inputs” and “outputs” may be relative such that an M-by-N permutation network of switches may be reversed and configured to operate as an N-by-M permutation network of switches. It is understood that the above are merely a few illustrative examples to which the disclosed subject matter is not limited.

In one embodiment, the permutation network of switches600may be configured to map each of a portion of the relatively large number (M) of inputs to one of a relatively small number (N) of outputs. In one embodiment, the wide network stage602may include a relatively large number (M) of inputs (e.g., input terminals IT-1, IT-2, IT-3, IT-4, IT-5, IT-6, IT-7, and IT-8), a relatively large number (M) of intermediate nodes (e.g., intermediate nodes IW-1, IW-2, IW-3, IW-4, IW-5, IW-6, IW-7, and IW-8), and a relatively large number (M) of outputs (e.g., output nodes OW-1, OW-2, OW-3, OW-4, OW-5, OW-6, OW-7, and OW-8). In some embodiments, each node may be a switch or switch node. In one embodiment, the wide network stage602may be configured to map each of a relatively large number (M) of inputs to a plurality of the relatively large number (M) of outputs.

In various embodiments, a wide network stage602implemented as a butterfly network may use log2(N) levels to ultimately map one of the M inputs to N of the outputs of the narrow network stage606of the permutation network of switches600. In the illustrated embodiment shown inFIG. 6, N equals 4, so the wide network stage602is built using log2(4) or two stages of the butterfly network. The nomenclature possibly used to describe the wide network may be M×M−L, where M equals the number of inputs and outputs to the wide network stage602, and L represents the number of levels. In the illustrated embodiment shown inFIG. 6, the wide network stage602includes an 8×8−2 network.

In the illustrative embodiment, the first input terminal IT-1may be mapped to both the first and fifth intermediate nodes IW-1and IW-5. Likewise, in this embodiment, the first intermediate node IW-1may be mapped to both the first and third output nodes OW-1and OW-3, and the fifth intermediate node IW-5may be mapped to both the fifth and seventh output nodes OW-5and OW-7. Therefore, in this embodiment, the wide network stage602may be configured to map first intermediate terminal IT-1to four output nodes OW-1, OW-3, OW-5, and OW-7, or conversely from the four output nodes to the input terminal. A similar mapping may be seen for the other input terminals and output nodes. It is understood that the above are merely a few illustrative examples to which the disclosed subject matter is not limited.

In one embodiment, the joint network stage604may include a relatively large number (M) of inputs (e.g., input nodes IJ-1, IJ-2, IJ-3, IJ-4, IJ-5, IJ-6, IJ-7, and IJ-8), and a relatively small number (N) of outputs (e.g., output nodes OJ-1, OJ-2, OJ-3, and OJ-4). In one embodiment, the joint network stage604may be configured to map each of a relatively small number (N) of outputs to a plurality of the relatively large number (M) of inputs. Using the nomenclature described above, the joint network stage604may be referred to as an 8×4−1 network.

In the illustrative embodiment, the first and second inputs IJ-1and IJ-2may both be mapped to the first output OJ-1. Likewise, in this embodiment, each of the outputs may be mapped to two of the inputs. A similar mapping may be seen for the other input terminals and output nodes. To continue the mapping of the first input terminal IT-1, the four input nodes IJ-1, IJ-3, IJ-5, and IJ-7may be mapped to all four of the output nodes OJ-1, OJ-2, OJ-3, and OJ-4. It is understood that the above are merely a few illustrative examples to which the disclosed subject matter is not limited.

In one embodiment, the narrow network stage606may include a relatively small number (N) of inputs (e.g., input nodes IN-1, IN-2, IN-3, and IN-4), a relatively small number (N) of outputs (e.g., output nodes ON-1, ON-2, ON-3, and ON-4), and relatively small number (N) of output terminals (e.g., output terminals OT-1, OT-2, OT-3, and OT-4). In one embodiment, the narrow network stage606may be configured to map each of a relatively small number (N) of inputs to a plurality of the relatively small number (N) of outputs.

In various embodiments, the narrow network stage606may connect the joint network stage604to the final relatively small (N) number of outputs of the permutation network of switches600. In another embodiment, the narrow network stage606may be implemented based upon the topology of the wide network stage602. In such an embodiment, if the wide network stage602is built using an L level of switches then the narrow network stage606may have one less (L−1) levels of switches. Each level in the wide network stage602may add one level of congestion and it may be desirable, in one embodiment, that the narrow network stage606have the same number of levels minus one to facilitate any bit permutation.

In such an embodiment, the topology of the narrow network stage606may include a reverse or inverse butterfly implementation. In various embodiments, the narrow network stage606may be built using a reverse or inverse butterfly topology when the corresponding wide network stage602is built using a butterfly network. This reverse topology may, in one embodiment, remove possible blocking paths. The nomenclature for this network may be N×N−L, where N is the number of inputs and outputs to the narrow network stage606, and L is the number of levels. The narrow network stage606may then be a 4×4−1 narrow network.

In the illustrative embodiment, the first input IN-1may be mapped to both the first and third outputs ON-1and ON-3. Each of the output nodes may be or may be mapped to an output terminal. Likewise, in this embodiment, each of the inputs may be mapped to two of the outputs. To continue the mapping of the first input terminal IT-1, the four input nodes IN-1, IN-2, IN-3, and IN-4may be mapped to all four of the output nodes ON-1, ON-2, ON-3, and ON-4. A similar mapping may be seen for the other input terminals and output nodes. It is understood that the above are merely a few illustrative examples to which the disclosed subject matter is not limited.

In the illustrative embodiment, the three stages may be cascaded. In such an embodiment, a signal coupled with an input terminal of the permutation network of switches600may be mapped to one of the output terminals of the permutation network of switches600. For example, the first input terminal IT-1may be mapped to any of the output terminals, as described above. Likewise, each of the output terminals may be mapped to one or more of the input terminals. It is understood that the above are merely a few illustrative examples to which the disclosed subject matter is not limited.

FIG. 7is a block diagram of an example embodiment of an apparatus700for routing signals in the aid of implementing logic changes in accordance with the disclosed subject matter. In one embodiment, the permutation network of switches700may include a wide network stage702, a joint network stage704, and a narrow network stage706. In various embodiments, the stages may overlap. In one embodiment, the outputs of the wide network stage702may be the inputs of the joint network stage704. In some embodiments, the outputs of the joint network stage704may be the inputs of the narrow network stage706. In such an embodiment, the permutation network of switches700may comprise24switch nodes arranged in five levels or layers: 1 for the input terminals, 2 for the wide network stage702, 1 for the joint network stage704, and 1 for the narrow network stage706. In various embodiments, each switch nodes may comprise two switches. Therefore, the entire permutation network of switches700may total 48 switches, as described below. In such an embodiment, the permutation network of switches700may include 29% less switches than a comparable cross-bar switch. It is understood that the above are merely a few illustrative examples to which the disclosed subject matter is not limited.

FIG. 8is a block diagram of an example embodiment of an apparatus800for routing signals in the aid of implementing logic changes in accordance with the disclosed subject matter. In one embodiment, the permutation network of switches800may include a wide network stage802, a joint network stage804, and a narrow network stage806. In one embodiment, the permutation network of switches800may include a half-duplex bi-directional permutation network of switches. In such an embodiment, a first portion810of the permutation network of switches may be configured to map a relatively large number of inputs to a relatively small number of outputs. In another embodiment, an input permutation of network switches (e.g., input permutation of network switches409ofFIG. 4) may include the first portion810of the half-duplex bi-directional permutation network of switches800. In such an embodiment, a second portion808of the permutation network of switches may be configured to map a relatively small number of inputs to a relatively large number of outputs. In another embodiment, an output permutation of network switches (e.g., output permutation of network switches410ofFIG. 4) may include the second portion808of the half-duplex bi-directional permutation network of switches800. It is understood that the above is merely an illustrative example to which the disclosed subject matter is not limited.

FIG. 9ais a circuit diagram of an example embodiment of apparatus902in accordance with the disclosed subject matter. Switch902may include a two input to two output switch. In various embodiments, switch nodes such as, for example, the input node IW-1ofFIG. 6may include switch902.FIG. 9bis a circuit diagram of an example embodiment of apparatus904in accordance with the disclosed subject matter. Switch904may include a two input to one output switch. In various embodiments, switch nodes such as, for example, the output node OW-1ofFIG. 6may include switch904. It is understood that the above are merely a few illustrative examples to which the disclosed subject matter is not limited. For example, in one embodiment, including a higher order permutation network of switches a many-to-many, many-to-fewer, or many-to-one switch may be used. In some embodiments, a multiplexer may be used. Furthermore, it is understood that in various embodiments the switches may be bi-directional and that the terms “input” and “output” may be relative.

FIG. 10is a flowchart of an example embodiment of a technique1000for implementing logic changes in accordance with the disclosed subject matter. It is understood thatFIGS. 10aand10brepresent a single flowchart illustrated on two pages. The connector1001provides a way to represent the connection between the two pages. Hereafter and here-before, the flowchart of the technique1000is simply referred to asFIG. 10, as if the flowchart merely occupied a single page.

Block1002illustrates that, in one embodiment, a subset of fixed logic circuits (FLCs) may be selected to be functionally replaced by a portion of a programmable logic core (PLC). In various embodiments, the subset of FLCs may be selected because the selected FLCs produce incorrect, otherwise undesirable results; although, it is understood that other selection criteria may be used and are within the scope of the disclosed subject matter. In some embodiments, a subset of the plurality of fixed logic circuits404ofFIG. 4may be selected, as described above. In some embodiments, the programmable logic core402ofFIG. 4may replace the selected FLCs, as described above.

Block1004illustrates that, in one embodiment, each of the fixed logic circuits may be configured to receive a plurality of input signals, perform combinational logic operations using the input signals, and produce at least one output signal. Block1006illustrates that, in one embodiment, the combinational logic operations of each fixed logic circuit may be substantially fixed, as described above. In some embodiments, the plurality of fixed logic circuits104ofFIG. 1may be configured as described above.

Block1008illustrates that, in one embodiment, selecting may include testing a subset of the fixed logic circuits. In various embodiments, the testing may include testing an integrated circuit or other device after manufacture but before full production; although, it is understood that the above is merely an illustrative example to which the disclosed subject matter is not limited. In some embodiments, a subset of the plurality of fixed logic circuits404ofFIG. 4may be tested, as described above.

Block1010illustrates that, in one embodiment, selecting may include determining if any of the subset of fixed logic circuits produces an undesirable result. In various embodiments, the undesirable result may occur because the fixed logic circuit was incorrectly designed; although, it is understood that the above is merely an illustrative example to which the disclosed subject matter is not limited. In some embodiments, a subset of the plurality of fixed logic circuits404ofFIG. 4may produce an undesirable result, as described above.

Block1012illustrates that, in one embodiment, selecting may include selecting, from the subset of fixed logic circuits that produces an undesirable result, the subset of fixed logic circuits (FLCs) to be functionally replaced. In various embodiments, the selection criteria may be based upon, for example, which fixed logic circuits have been configured to be replaced, the expected extent of changes to the combinational logic design, the availability of the programmable logic core, etc.; although, it is understood that the above are merely a few illustrative examples to which the disclosed subject matter is not limited. In some embodiments, a subset of the plurality of fixed logic circuits404ofFIG. 4may be selected, as described above.

Block1014illustrates that, in one embodiment, a portion of the programmable logic core (PLC) may be configured to produce at least one output signal by performing a logic operation using a plurality of inputs received by the PLC. In one embodiment, the portion of the PLC may be configured to functionally replace the selected FLCs. In various embodiments, the portion of the PLC may be configured to replace stages in a pipelined architecture, as described above. In some embodiments, the programmable logic core402ofFIG. 4may be configured as described above.

Block1016illustrates that, in one embodiment, configuring may include dynamically configuring a plurality of programmable logic devices, included within the PLC, to perform the logic operation. In one embodiment, the dynamic configuration may include the use of a product term based architecture (e.g., an Altera™ FPGA), as described above; although, it is understood that the above is merely an illustrative example to which the disclosed subject matter is not limited. In some embodiments, the programmable logic core402ofFIG. 4may be configured as described above.

Block1018illustrates that, in one embodiment, configuring may include dynamically configuring a look-up table, included within the PLC, to perform the logic operation. In one embodiment, the dynamic configuration may include the use of a look-up table architecture (e.g., a Xilinx™ FPGA), as described above; although, it is understood that the above is merely an illustrative example to which the disclosed subject matter is not limited. In some embodiments, the programmable logic core402ofFIG. 4may be configured as described above.

Block1050illustrates that, in one embodiment, the input signals of the selected subset of FLCs may be dynamically routed to at least a portion of the inputs to the PLC. In one embodiment, the routing may involve the use of a permutation network of switches. In another embodiment, the routing may depend upon the portion of the PLC used to functionally replace the selected FLC(s). In some embodiments, the permutation of network switches408ofFIG. 4may dynamically route the input signals, as described above.

Block1052illustrates that, in one embodiment, routing the input signals may include using an input permutation network of switches. In such an embodiment, the input permutation network of switches may include a first number of inputs to the input permutation network of switches, and a second number of outputs to the input permutation network of switches. It is contemplated that, in one embodiment, the first number may be a relatively large number and the second number may be a relatively small number, as described above. In some embodiments, the input permutation of network switches409ofFIG. 4or the permutation of network switches700ofFIG. 7may dynamically route the input signals, as described above.

Block1054illustrates that, in one embodiment, routing the input signals may include configuring the input permutation network of switches to map each of a portion of the first number of inputs to one of the second number of outputs. In some embodiments, the input permutation of network switches409ofFIG. 4or the permutation of network switches700ofFIG. 7may configured to route the input signals, as described above.

Block1056illustrates that, in one embodiment, the input signals of the selected FLCs may be coupled with at least a portion of the first number of inputs to the input permutation network of switches. Block1058illustrates that, in one embodiment, at least a portion of the second number of outputs to the input permutation network of switches may be coupled with at least a portion of the inputs received by the PLC. In such an embodiment, the input permutation network of switches may facilitate the replacement of the selected FLCs. In some embodiments, the input permutation of network switches409ofFIG. 4or the permutation of network switches700ofFIG. 7may configured to route the input signals, as described above.

Block1060illustrates that, in one embodiment, routing the input signals may include using a wide network stage to map the inputs from the selected FLCs to a plurality of a first number of outputs of the wide network stage, wherein there are a first number of inputs from the selected FLCs. In such an embodiment, the wide network stage602ofFIG. 6may map the inputs, as described above.

Block1062illustrates that, in one embodiment, routing the input signals may include using a joint network stage to map each of a second number of outputs of the joint network stage to a plurality of the first number of outputs of the wide network stage. In various embodiments, the first number of outputs may be relatively large; whereas, the second number of outputs may be relatively small. In such an embodiment, the joint network stage604ofFIG. 6may map the outputs, as described above.

Block1064illustrates that, in one embodiment, routing the input signals may include using a narrow network stage to map each of the second number of outputs of the joint network stage to a plurality of a second number of inputs to the PLC. In such an embodiment, the narrow network stage606ofFIG. 6may map the outputs, as described above.

Block1066illustrates that, in one embodiment, routing the input signals may include using an input portion of a half-duplex bi-directional permutation network of switches. In various embodiments, the input portion of the half-duplex bi-directional permutation network of switches may be dynamically configurable. In such an embodiment, the input portion810of the half-duplex bi-directional permutation network of switches800ofFIG. 8may be used to routing the input signals, as described above.

Block1068illustrates that, in one embodiment, at least a portion of the output signals from the PLC may be dynamically routed to function as the output signals of the selected subset of FLCs. In one embodiment, the routing may involve the use of a permutation network of switches. In another embodiment, the routing may depend upon the portion of the PLC used to functionally replace the selected FLC(s). In yet another embodiment, the routing may use a multiplexer to select between the output signal produced by the PLC and the output signal produced by the combinational logic of the selected FLC, as described above. In some embodiments, the permutation of network switches408ofFIG. 4may dynamically route the output signals, as described above.

Block1070illustrates that, in one embodiment, routing the output signals may include using an output permutation network of switches. In such an embodiment, the output permutation network of switches may include a third number of inputs to the output permutation network of switches, and a fourth number of outputs to the output permutation network of switches. It is contemplated that, in one embodiment, the fourth number may be a relatively large number and the third number may be a relatively small number, as described above. In some embodiments, the output permutation of network switches410ofFIG. 4or the permutation of network switches700ofFIG. 7may dynamically route the output signals, as described above.

Block1072illustrates that, in one embodiment, routing the output signals may include configuring the output permutation network of switches to map each of a portion of the third number of inputs to one of the fourth number of outputs. In some embodiments, the output permutation of network switches410ofFIG. 4or the permutation of network switches700ofFIG. 7may be configured to route the output signals, as described above.

Block1074illustrates that, in one embodiment, the output signals of the PLC may be coupled with at least a portion of the third number of inputs to the output permutation network of switches. Block1076illustrates that, in one embodiment, at least a portion of the fourth number of outputs to the output permutation network of switches may be coupled with at least a portion of the outputs of the FLCs. In such an embodiment, the output permutation network of switches may facilitate the replacement of the selected FLCs. In some embodiments, the output permutation of network switches410ofFIG. 4or the permutation of network switches700ofFIG. 7may be configured to route the output signals, as described above.

Block1078illustrates that, in one embodiment, routing the output signals may include using an output portion of a half-duplex bi-directional permutation network of switches. In various embodiments, the output portion of the half-duplex bi-directional permutation network of switches may be dynamically configurable. In such an embodiment, the output portion808of the half-duplex bi-directional permutation network of switches800ofFIG. 8may be used for routing the output signals, as described above.