Doherty amplifier

An amplifier includes a Doherty amplifier composed of a distributor distributing an input signal to two signals, a carrier amplifier that receives one of the two signals and has a first FET, a peaking amplifier that receives the other one of the two signals and has a second FET, and a combiner that transforms an output impedance of the carrier amplifier and combines outputs of the carrier amplifier and the peaking amplifier, and a voltage controller that changes at least one of a gate voltage and a drain voltage supplied to at least one of the first FET and the second FET in accordance with a frequency of the input signal when the frequency of the input signal varies.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2010-171092 filed on Jul. 29, 2010, the entire contents of which are incorporated herein by reference.

BACKGROUND

(i) Technical Field

A certain aspect of the embodiments discussed herein is related to an amplifier.

(ii) Related Art

A Doherty amplifier is used as radio communications amplifier (see Japanese Patent Application Publication No. 2005-322993). The Doherty amplifier includes a carrier amplifier and a peaking amplifier. The carrier amplifier is an amplifier that primarily amplifies an input signal. The peaking amplifier is an amplifier that amplifies the peak of the input signal. For example, the carrier amplifier always amplifies the input signal. In contrast, the peaking amplifier amplifies the input signal only when the input signal has power equal to or higher than a predetermined level.

The Doherty amplifier includes an impedance transformer composed of, for example, a λ/4 phase line, an inductor and a capacitor. This kind of impedance transformer has a frequency dispersion characteristic for high frequency signals. This may result in a difference between the center frequency of the input signal and the center frequency of the amplifier and may decrease the drain efficiency.

SUMMARY

According to an aspect of the present invention, there is provided a Doherty amplifier including: a Doherty circuit having a carrier amplifier having a first FET, and a peaking amplifier having a second FET; and a voltage controller that controls at least one of a gate voltage and a drain voltage supplied to at least one of the first FET and the second FET in accordance with a frequency of an input signal of the Doherty amplifier.

DETAILED DESCRIPTION

FIG. 1is a circuit diagram of a Doherty amplifier included in an amplifier in accordance with a first embodiment. A Doherty amplifier100includes a carrier amplifier10, a peaking amplifier12, a distributor14and a combiner20. The distributor14distributes an input signal applied to an input terminal16to two paths. For example, the distributor14equally distributes the input signal to two signals. The carrier amplifier10receives one of the two input signals and amplifies the input signal. The peaking amplifier12receives the other input signal and amplifies it. The combiner20has a node at which the output signal of the carrier amplifier10and that of the peaking amplifier12are combined, and λ/4 phase lines22. The λ/4 phase line22is connected to a next stage of the carrier amplifier10. The λ/4 phase line26is connected to the next stage of the node at which the outputs of the carrier amplifier10and the peaking amplifier12are combined. The combiner20adjusts the impedances of the outputs of the carrier amplifier10and the peaking amplifier12, and combines the output signals thereof. The signal output by the combiner20is output via an output terminal18. A λ/4 phase line24is connected to the preceding stage of the peaking amplifier12.

The λ/4 phase line22performs an impedance transformation so that the load connected to the output of the carrier amplifier10is twice the load connected to the output terminal18when power is as low as only the carrier amplifier10operates. In contrast, when power is as high as both the carrier amplifier10and the peaking amplifier12operate, the λ/4 phase line22performs an impedance transformation so that the load connected to the outputs of the carrier amplifier10and the peaking amplifier12is equal to that connected to the output terminal18. The λ/4 phase line24is a line intended to compensate for a phase difference between the carrier amplifier10and the peaking amplifier12due to the λ/4 phase line22associated with the carrier amplifier10. The λ/4 phase line26matches the impedance of the node at which the outputs of the carrier amplifier10and the peaking amplifier12are combined with the characteristic of a stage that is connected to the next stage of the node.

The carrier amplifier10is, for example, a class-A or class-AB amplifier, and always amplifies the distributed signal from the distributor14. The peaking amplifier12is, for example, a class-C amplifier, and amplifies the distributed signal that has a power higher than a predetermined power.

FIG. 2is a graph that illustrates the drain efficiency associated with the output power of the Doherty amplifier. Referring toFIG. 2, when the output power is saturated, the carrier amplifier10and the peaking amplifier12have respective saturated powers. Thus, the drain efficiency is maximized. At an output that is 6 dB lower than the saturated power (6 dB back-off output), only the carrier amplifier10has the saturated power, and the peaking amplifier12does not amplify the signal. This case also has the maximum drain efficiency. Since the drain efficiency is maximized at two output powers, it is possible to obtain a wide range of output power having high drain efficiencies. For example, in many cases, power amplifiers for digital modulation signals are operated at an output power that is 5 dB˜8 dB lower than the saturated power in order to maintain the linearity. The Doherty amplifier is capable of improving the drain efficiency at back-off powers, as illustrated inFIG. 2.

FIG. 3is a block diagram of an amplifier in accordance with a first embodiment. Referring toFIG. 3, an amplifier200includes a digital signal generator40, a digital pre-distortion unit (DPD)42, a digital-to-analog converter (DAC)44, an up converter46, a signal generator50, an amplifier48, the Doherty amplifier100, gate voltage supply circuits30and34, drain voltage supply circuits32and36, a directional coupler52, a bandpass filter58, an antenna60, a down converter54, an analog-to-digital converter (ADC)56, and a voltage controller70.

The digital signal generator40generates a baseband signal, which is a digital signal, and outputs it to the DPD42. The DPD42compensates for a distortion caused when the Doherty amplifier100amplifies the signal. For computation directed to compensating for the distortion characteristic of the Doherty amplifier100, the DPD42stores compensation values used to compensate for distortion of the baseband signal in a table45extended in a built-in memory43. The DPD42_looks up the table45and outputs a digital signal that compensates for a distortion of the baseband signal. The DAC44converts the digital signal from the DPD42to an analog signal. The up converter46converts the analog signal from the DAC44to a frequency of a signal output by the signal generator50, and outputs a resultant RF signal. The amplifier48amplifiers the RF signal from the up converter46, and outputs the amplified RF signal to the Doherty amplifier100.

The Doherty amplifier100amplifies the output of the amplifier48. The structure of the Doherty amplifier100illustrated inFIG. 3is the same as illustrated inFIG. 1, and a description thereof is omitted here. The gate voltage supply circuit30that generates a gate voltage is connected to the gate of a first FET of the carrier amplifier10, and the drain voltage supply circuit32that generates a drain voltage is connected to the drain thereof. The gate voltage supply circuit34that generates a gate voltage is connected to the gate of a second FET of the peaking amplifier12, and the drain voltage supply circuit36that generates a drain voltage is connected to the drain thereof. The directional coupler52distributes the output of the Doherty amplifier100to two signals. One of the two signals passes through the bandpass filter58, which extracts only predetermined frequency components from the received signal. The predetermined frequency components are applied to the antenna60. The other signal is converted to frequencies of the baseband signal by the down converter54, which are then converted to a digital signal by the ADC56. The digital signal thus produced is fed back to the DPD42. Thus, the distortion characteristic of the Doherty amplifier100can be compensated for.

The voltage controller70changes at least one of the gate voltage and the drain voltage supplied to at least one of the first FET and the second FET when the frequency of the RF input signal applied to the Doherty amplifier100varies. The voltage controller70has a table memory for storing a relationship of the frequency of the RF input signal and at least one of the gate voltage and the drain voltage supplied to at least one of the first FET and the second FET. For example, for a predetermined frequency of the RF input signal, at least one of the gate voltage and the drain voltage supplied to at least one of the first and second FETs having a drain efficiency equal to or higher than a predetermined value is measured and stored in the table memory. In this case, the voltage controller70changes at least one of the gate voltage and the drain voltage supplied to at least one of the first and second FETs by referring to the table memory.

It is thus possible to increase the drain efficiency to the predetermined value or greater and to prevent the drain efficiency from decreasing.

FIG. 4is a flowchart of a process by the voltage controller70in accordance with the first embodiment. Referring toFIG. 4, the voltage controller70determines whether there is a variation in the frequency of the RF input signal (step S10). For example, the voltage controller70acquires the frequency of the signal generator50with a predetermined period, and determines there is a frequency variation in the RF input signal. When no frequency variation is observed (No at step S10), the voltage controller70ends the process. In contrast, when a frequency variation is observed (Yes at step S10), the voltage controller70obtains, from the table memory, at least one of the gate voltage and the drain voltage supplied to at least one of the first FET and the second FET (step S12). The voltage controller70sets the voltage acquired at step S12to any of the gate voltage supply circuits30and34and the drain voltage supply circuits32and36in order to change at least one of the gate voltage and the drain voltage supplied to at least one of the first FET and the second FET (step S14). Then, the voltage controller70ends the process.

In the first embodiment, the voltage controller70changes at least one of the gate voltage and the drain voltage supplied to at least one of the first FET and the second FET on the basis of the frequency of the input signal by referring to the table memory when the voltage controller70detects a frequency variation of the RF input signal. For example, when the drain current of the peaking amplifier12increases due to a frequency variation of the RF input signal, the voltage controller70changes the gate voltage of the second FET to decrease the drain current of the peaking amplifier12. It is thus possible to suppress the drain efficiency from decreasing. For example, when the drain current of the carrier amplifier10increases due to a frequency variation of the RF input signal, the voltage controller70changes the gate voltage of the first FET to decrease the drain current of the carrier amplifier10. In contrast, when the drain current of the carrier amplifier10decreases, the voltage controller70changes the gate voltage of the first FET to increase the drain current of the carrier amplifier10. It is thus possible to suppress decrease of the drain efficiency. In an exemplary case where the saturated output decreases due to a frequency variation of the RF input signal, the drain voltages of the first and second FETs are increased. It is thus possible to prevent the saturated output from decreasing.

In the first embodiment, when the frequency of the RF input signal varies, the voltage controller70may execute another control in which the gate voltage and the drain voltage of the first FET are not changed but at least one of the gate voltage and the drain voltage of the second FET is changed in accordance with the frequency of the RF input signal. When there is a frequency variation in the RF input signal, the voltage controller70may execute yet another control in which the drain voltage of the first FET is not changed but the drain voltage of the second FET is increased. In this case, it is preferable that the gate voltages of the first and second FETs are not changed. Since the drain current that flows through the peaking amplifier12is smaller than the drain current that flows through the carrier amplifier10, it is possible to suppress an increase in power consumption of the whole amplifier by increasing the drain voltage of only the peaking amplifier12. It is thus possible to suppress decrease in the drain efficiency.

In the first embodiment, the condition for changing at least one of the gate voltage and the drain voltage supplied to at least one of the first FET and the second FET in accordance with the frequency of the RF input signal is such that the RF signal has a frequency variation so as to exceed a band width having a fractional bandwidth of 3% (approximately 64 MHz) when it is supposed that the Doherty amplifier100is designed to have a center frequency of 2.14 GHz. That is, the above corresponds to a case where the frequency of the RF input signal is lower than 2108 MHz or is higher than 2172 MHz. When the frequency of the RF input signal is within a range having a fractional frequency of 3% with respect to the center frequency of the amplifier, good amplification characteristics and good power efficiency can be obtained easily. In the case where the frequency of the RF input signal exceeds the range having a fractional frequency of 3% with respect to the center frequency of the amplifier, at least one of the gate voltage and the drain voltage supplied to at least one of the first and second FETs is changed, so that decrease in the drain efficiency can be suppressed.

The contents of the table memory may be the results of a measurement conducted previously. The contents of the table memory may be changed dynamically.

The first embodiment has the memory43and the DPD42, which is the distortion compensation part for compensating for distortion of the output signal of the Doherty amplifier100.

FIG. 5is a block diagram of an exemplary configuration of an amplifier in accordance with a second embodiment. Referring toFIG. 5, and amplifier300differs from the amplifier200illustrated inFIG. 3in that the bandpass filter58and the antenna60inFIG. 3are replaced by a switch62, bandpass filters64and65, and antennas66and67. Further, the memory43of the amplifier200stores tables47and49instead of the table45.

Referring toFIG. 5, the switch62switches the output destination of the signal from the directional coupler52in accordance with the frequency band. For example, when the amplifier300is used for a base station of W-CDMA (Wideband Code Division Multiple Access), the switch62is controlled to output the signal from the directional coupler52to the bandpass filter64in a case where the frequency of the RF input signal is in a band of 1.8 to 1.85 GHz (hereinafter, referred to as frequency band1). The switch62is controlled to output the signal from the directional coupler52to the bandpass filter65in a case where the frequency of the RF input signal is in a band of 2.11 to 2.17 GHz (hereinafter, referred to as frequency band2). The bandpass filters64and65extract the corresponding frequency components from the received signals and supply those to the antennas66and67, respectively.

The memory43stores the tables47and49, which are used for distortion compensation processes respectively involved in the frequency bands1and2. The DPD42determines whether the frequency of the RF input signal of the Doherty amplifier100belongs to the frequency band1or the frequency band2, and selects the appropriate one of the two tables47and49for the corresponding distortion compensation process.

In a case where there is a frequency variation of the RF input signal, the voltage controller70changes at least one of the gate voltage and the drain voltage supplied to at least one of the first FET and the second FET in accordance with the frequency of the RF input signal by referring to the table47or49. The tables47and49associate the frequencies of the RF input signals in the frequency bands1and2with at least one of the gate voltage and the drain voltage supplied to be at least one of the first FET and the second FET by the voltage controller70in accordance with the frequency of the RF input signal. The voltage controller70selectively uses the tables47and49in accordance with the frequency band of the RF input signal, and changes at least one of the gate voltage and the drain voltage supplied to at least one of the first FET and the second FET.

The voltage controller70of the second embodiment selectively uses the tables47and49and changes at least one of the gate voltage and the drain voltage supplied to at least one of the first FET and the second FET. It is thus possible to suppress decrease in the drain efficiency.

The present invention is not limited to the specifically described embodiments but may include various embodiments and variations within the scope of the present invention.