Semiconductor device

According to one embodiment, the insulating film is provided between the anode region and the cathode region in the surface of the second semiconductor region. The third semiconductor region is provided inside the second semiconductor region. The third semiconductor region covers a corner of the insulating film on the anode region side. The first electrode contacts the anode region and the third semiconductor region. The second electrode contacts the cathode region. The third electrode is provided on the insulating film and positioned on a p-n junction between the second semiconductor region and the third semiconductor region.

FIELD

BACKGROUND

In a switching element connected to, for example, an inductive load such as a coil or the like, a current flows in a body diode (a parasitic diode) of the switching element when the gate is OFF due to energy stored in the inductive load. This may cause the operation of a thyristor that occurs parasitically between the switching element, a substrate in which the switching element is formed, and other elements formed in the same substrate. And the current may continue to be amplified and may cause thermal destruction of the element to occur.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region of a first conductivity type, an anode region of the first conductivity type, a cathode region of the first conductivity type, an insulating film, a third semiconductor region of a second conductivity type, a first electrode, a second electrode, and a third electrode. The second semiconductor region is provided in a surface of the first semiconductor region. The anode region is provided in a surface of the second semiconductor region. The cathode region is provided in the surface of the second semiconductor region. A first conductivity-type impurity concentration is higher in the cathode region than in the anode region. The insulating film is provided between the anode region and the cathode region in the surface of the second semiconductor region. The third semiconductor region is provided inside the second semiconductor region. The third semiconductor region covers a corner of the insulating film on the anode region side. The first electrode contacts the anode region and the third semiconductor region. The second electrode contacts the cathode region. The third electrode is provided on the insulating film and positioned on a p-n junction between the second semiconductor region and the third semiconductor region.

Embodiments will now be described with reference to the drawings. The same components in the drawings are marked with the same reference numerals.

Although the first conductivity type is described as an n-type and the second conductivity type is described as a p-type in the embodiments recited below, the embodiments are implementable also in the case where the first conductivity type is the p-type and the second conductivity type is the n-type.

The semiconductor device of the embodiment is used in, for example, an H-bridge circuit, an inverter circuit, a DC-DC converter circuit, etc., that outputs a large current.

FIG. 1is a circuit diagram of a circuit including the semiconductor device of the embodiment.

A high-side switching element2and a low-side switching element1are connected in series between a grounding terminal and a power supply line111used as a first line. The power supply line111is connected to a power supply and supplied with a power supply voltage (an input voltage) Vcc.

The high-side switching element2is, for example, a p-channel double diffused metal oxide semiconductor field effect transistor (DMOS). A source terminal (a source electrode) of the high-side switching element2is connected to the power supply line111; and a drain terminal (a drain electrode) of the high-side switching element2is connected to an output line112used as a second line.

The low-side switching element1is, for example, an n-channel MOSFET. A drain terminal (a drain electrode) of the low-side switching element1is connected to the drain terminal of the high-side switching element2and the output line112. A source terminal (a source electrode) of the low-side switching element1is connected to the grounding terminal.

The high-side switching element2and a Schottky barrier diode3(or4) are connected in parallel between the power supply line111and the output line112.

An anode terminal (an anode electrode) of the Schottky barrier diode3(or4) is connected to the output line112; and a cathode terminal (a cathode electrode) of the Schottky barrier diode3(or4) is connected to the power supply line111.

For example, a coil L is connected to the output line112as a load. Accordingly, the high-side switching element2and the Schottky barrier diode3(or4) are connected in parallel between the power supply Vcc and the coil L.

The high-side switching element2, the low-side switching element1, a control circuit that drives these switching elements, and the Schottky barrier diode3(or4) are integrated in one semiconductor chip.

FIG. 2is a schematic cross-sectional view of the Schottky barrier diode3of the embodiment.

FIG. 3is a schematic cross-sectional view of the high-side switching element2of the embodiment and another element (e.g., a logic element5).

The semiconductor device of the embodiment has a structure in which the Schottky barrier diode3, the high-side switching element2, and the logic element5are provided together on the same substrate10.

The substrate (or the semiconductor region)10is a p-type semiconductor substrate and is, for example, a p-type silicon substrate. Also, the semiconductor region that is described below includes mainly silicon. Or, the substrate10and the semiconductor are not limited to silicon and may be, for example, silicon carbide, gallium nitride, etc.

For example, an analog integrated circuit that includes the logic element5is formed in the central region of the semiconductor device having a chip configuration. For example, the high-side switching element2and the Schottky barrier diode3(or4) are formed in the chip peripheral region. For example, the high-side switching element2is formed in a region between the logic element5and the Schottky barrier diode3(or4) in a direction along the front surface of the substrate10.

As shown inFIG. 2andFIG. 3, for example, an insulating separation unit (an insulating film)30that has a Shallow Trench Isolation (STI) structure is provided between the components that need to be insulatively separated in the front surface of the substrate10.

The logic element5and the high-side switching element2are insulatively separated by the insulating separation unit30formed between the logic element5and the high-side switching element2. The high-side switching element2and the Schottky barrier diode3(or4) are insulatively separated by the insulating separation unit30formed between the high-side switching element2and the Schottky barrier diode3(or4).

First, the high-side switching element2will be described with reference toFIG. 3.

The high-side switching element2has a DMOS structure in which the channel is formed by double diffusion and the difference between the lateral diffusion of the diffusion regions is utilized as the effective channel length.

The high-side switching element2includes an n-type semiconductor region11formed in the front surface of the substrate10. The n-type semiconductor region11and the p-type substrate10have a p-n junction; and the n-type semiconductor region11is electrically isolated from the substrate10. For example, the substrate10is grounded; and the n-type semiconductor region11is connected to the source terminal of the high-side switching element2via an n-type semiconductor region24and an n+-type semiconductor region33.

A pair of p-type semiconductor regions26is formed in the front surface of the n-type semiconductor region11; and a p-type semiconductor region23is formed between the p-type semiconductor regions26. The p-type impurity concentration of the p-type semiconductor region23is higher than the p-type impurity concentration of the p-type semiconductor region26.

A p+-type drain region21is formed in the front surface of the p-type semiconductor region23. The p-type impurity concentration of the p+-type drain region21is higher than the p-type impurity concentration of the p-type semiconductor region23.

The two side surfaces of the p+-type drain region21contact the insulating separation unit30formed in the front surface of the p-type semiconductor region26.

A pair of n-type semiconductor regions24is formed in the front surface of the n-type semiconductor region11to be separated respectively from the pair of p-type semiconductor regions26.

A p+-type source region22is formed in the front surface of each of the n-type semiconductor regions24.

Also, the n+-type semiconductor region33is formed in the front surface of each of the n-type semiconductor regions24to be adjacent to the p+-type source region22. The n-type impurity concentration of the n+-type semiconductor region33is higher than the n-type impurity concentration of the n-type semiconductor region24.

The one side surface of the n+-type semiconductor region33contacts the p+-type source region22; and another side surface contacts the insulating separation unit30.

The side surface of the p+-type source region22on the p+-type drain region21side is inside the n-type semiconductor region24. The n-type semiconductor region11is formed between the n-type semiconductor region24and the p-type semiconductor region26.

The front surface region of the n-type semiconductor region24and the front surface region of the n-type semiconductor region11that are formed between the p+-type source region22and the p-type semiconductor region26function as a channel region27.

A gate insulator film29is provided on the channel region27and on the front surface of the p-type semiconductor region26adjacent to the channel region27. A gate electrode28is provided on the gate insulator film29.

A drain electrode31is provided as a fourth electrode on the p+-type drain region21. The p+-type drain region21is electrically connected to and has an ohmic contact with the drain electrode31directly or via a metal silicide region.

A source electrode32is provided as a fifth electrode on the p+-type source region22. The p+-type source region22is electrically connected to and has an ohmic contact with the source electrode32directly or via a metal silicide region.

The source electrode32is provided also on the n+-type semiconductor region33and contacts the n+-type semiconductor region33.

For example, the gate electrode28and the semiconductor regions of the high-side switching element2are formed in planar patterns having stripe configurations.

In the high-side switching element2described above, when a desired gate voltage is applied to the gate electrode28, an inversion layer (a p-channel) is formed in the channel region27; and a current flows between the source electrode32and the drain electrode31via the p+-type source region22, the channel region27, the p-type semiconductor region26, the p-type semiconductor region23, and the p+-type drain region21. The current flows in the p-type semiconductor region26and the p-type semiconductor region23to flow around through the region under the insulating separation unit30.

The insulating separation unit30that is formed on the drain side increases the breakdown voltage of the high-side switching element2. Also, the p-type semiconductor region26that has the p-type impurity concentration that is lower than that of the p+-type drain region21is depleted when the gate is OFF and increases the breakdown voltage.

Also, a breakdown voltage decrease due to the impurity concentration changing abruptly from the p-type semiconductor region26to the p+-type drain region21can be suppressed by providing the p-type semiconductor region23between the p-type semiconductor region26and the p+-type drain region21, where the p-type impurity concentration of the p-type semiconductor region23is between the p-type impurity concentration of the p-type semiconductor region26and the p-type impurity concentration of the p+-type drain region21.

The logic element5will now be described.

The logic element5has, for example, a CMOS structure. A portion of the logic element5(e.g., an n-channel MOSFET) is shown inFIG. 3.

The logic element5includes an n-type semiconductor region13formed in the front surface of the substrate10. The n-type semiconductor region13and the p-type substrate10have a p-n junction; and the n-type semiconductor region13is electrically isolated from the substrate10.

A p-type semiconductor region65is formed in the front surface of the n-type semiconductor region13. An n+-type semiconductor region61and an n+-type semiconductor region62are formed in the front surface of the p-type semiconductor region65. One of the n+-type semiconductor region61or the n+-type semiconductor region62functions as a drain region; and the other functions as a source region.

The gate electrode28is provided, with the insulator film29interposed, on a channel region (the front surface region of the p-type semiconductor region65) between the n+-type semiconductor region61and the n+-type semiconductor region62.

Also, an n-type semiconductor region66is formed in the front surface of the n-type semiconductor region13to be adjacent to the p-type semiconductor region65. An n+-type semiconductor region64is formed in the front surface of the n-type semiconductor region66.

The n-type impurity concentration of the n+-type semiconductor region64is higher than the n-type impurity concentration of the n-type semiconductor region66.

Also, a p+-type semiconductor region63is formed in the front surface of the p-type semiconductor region65. The insulating separation unit30is formed between the p+-type semiconductor region63and the n+-type semiconductor region62. The insulating separation unit30is formed between the p+-type semiconductor region63and the n+-type semiconductor region64.

The Schottky barrier diode3will now be described with reference toFIG. 2.

The Schottky barrier diode3includes an n-type semiconductor region12formed in the front surface of the substrate10. The n-type semiconductor region12and the p-type substrate10have a p-n junction; and the n-type semiconductor region12is electrically isolated from the substrate10. For example, the substrate10is grounded; and the n-type semiconductor region12is connected to a cathode electrode53of the Schottky barrier diode3via an n-type semiconductor region41and an n+-type cathode region43.

Multiple n-type semiconductor regions41and multiple p-type semiconductor regions42are formed in the front surface of the n-type semiconductor region12. For example, the n-type semiconductor regions41and the p-type semiconductor regions42are formed in planar patterns having stripe configurations. The n-type semiconductor regions41and the p-type semiconductor regions42are separated respectively from each other in a direction along the front surface of the substrate10.

The n+-type cathode region43is formed in the front surface of the n-type semiconductor region41. The n-type impurity concentration of the n+-type cathode region43is higher than the n-type impurity concentration of the n-type semiconductor region41.

A p+-type semiconductor region44is formed in the front surface of the p-type semiconductor region42. The p-type impurity concentration of the p+-type semiconductor region44is higher than the p-type impurity concentration of the p-type semiconductor region42.

A pair of p-type semiconductor regions42is formed between a pair of n-type semiconductor regions41. The n-type semiconductor region12is formed between the pair of p-type semiconductor regions42; and an n-type anode region45is formed in the front surface of the n-type semiconductor region12. The anode region45is formed between the pair of p+-type semiconductor regions44.

The n-type impurity concentrations of the anode region45and the n-type semiconductor region12are lower than the n-type impurity concentration of the n-type semiconductor region41.

A metal silicide region47is formed in the front surface of the anode region45; an insulating layer81is formed on the metal silicide region47; and an anode electrode51is provided as a first electrode on the insulating layer81. The insulating layer81is provided on the front surface of the substrate10.

The anode electrode51and the metal silicide region47are connected via a contact52piercing the insulating layer81. The anode electrode51and the contact52are formed from metal materials. The contact52has a Schottky contact with the anode region45via the metal silicide region47.

The anode region45has a Schottky contact with the anode electrode51via the metal silicide region47and the contact52.

A metal silicide region46is formed in the front surface of the cathode region43; the insulating layer81is formed on the metal silicide region46; and the cathode electrode53is provided as a second electrode on the insulating layer81.

The cathode electrode53and the metal silicide region46are connected via a contact54piercing the insulating layer81. The cathode electrode53and the contact54are formed from metal materials. The contact54has an ohmic contact with the cathode region43via the metal silicide region46.

The cathode region43has an ohmic connection with the cathode electrode53via the metal silicide region46and the contact54.

The cathode region43is provided between the insulating separation unit30; and the side surfaces of the cathode region43are adjacent to the insulating separation unit30.

The insulating separation unit30is provided between the cathode region43and the p+-type semiconductor region44. The p+-type semiconductor region44is formed between the insulating separation unit30and the anode region45.

One corner on the bottom side of the insulating separation unit30between the cathode region43and the p+-type semiconductor region44is positioned inside the n-type semiconductor region41; and the other corner is positioned inside the p-type semiconductor region42.

The n-type semiconductor region41covers the corner of the insulating separation unit30on the cathode region43side; and the p-type semiconductor region42covers the corner of the insulating separation unit30on the anode region45side.

A third electrode55is provided on the insulating separation unit30between the cathode region43and the p+-type semiconductor region44. The third electrode55is positioned on a p-n junction50between the p-type semiconductor region42and the n-type semiconductor region12under the insulating separation unit30.

The third electrode55is, for example, a polycrystalline silicon film; and a metal silicide region56is formed in the front surface of the third electrode55.

The insulating layer81is formed on the metal silicide region56; and a portion of the anode electrode51is provided on the insulating layer81. The anode electrode51extends from a region on the anode region45to a region on the third electrode55.

The anode electrode51and the third electrode55are connected via the metal silicide region56and a contact59piercing the insulating layer81. Accordingly, the third electrode55is shorted to the anode electrode51; and the potential of the anode electrode51is applied to the third electrode55.

The metal silicide region47that is formed in the front surface of the anode region45also is formed in the front surface of the p+-type semiconductor region44adjacent to the anode region45. The p+-type semiconductor region44is connected to the anode electrode51via the metal silicide region47and the contact52.

Accordingly, the potential of the anode electrode51is applied to the p-type semiconductor region42via the contact52, the metal silicide region47, and the p+-type semiconductor region44.

For example, the semiconductor regions of the Schottky barrier diode3, the high-side switching element2, and the logic element5described above are formed by ion implantation and subsequent annealing.

The n-type semiconductor region12of the Schottky barrier diode3shown inFIG. 2, the n-type semiconductor region11of the high-side switching element2shown inFIG. 3, and the n-type semiconductor region13of the logic element5shown inFIG. 3are formed by simultaneous processing and have substantially the same depth.

The n-type semiconductor region41of the Schottky barrier diode3, the n-type semiconductor region24of the high-side switching element2, and the n-type semiconductor region66of the logic element5are formed by simultaneous processing.

The p-type semiconductor region42of the Schottky barrier diode3and the p-type semiconductor region23of the high-side switching element2are formed by simultaneous processing.

The p-type semiconductor region26of the high-side switching element2and the p-type semiconductor region65of the logic element5are formed by simultaneous processing.

The n+-type cathode region43of the Schottky barrier diode3, the n+-type semiconductor region33of the high-side switching element2, and the n+-type semiconductor regions61,62, and64of the logic element5are formed by simultaneous processing.

The p+-type semiconductor region44of the Schottky barrier diode3, the p+-type drain region21and the p+-type source region22of the high-side switching element2, and the p+-type semiconductor region63of the logic element5are formed by simultaneous processing.

The third electrode55of the Schottky barrier diode3, the gate electrode28of the high-side switching element2, and the gate electrode28of the logic element5are formed of the same material (e.g., polycrystalline silicon) by simultaneous processing.

Also, a sidewall insulating film82is formed on the side walls of the third electrode55of the Schottky barrier diode3. Although not shown, sidewall insulating films are formed also on the side walls of the gate electrode28of the high-side switching element2and the side walls of the gate electrode28of the logic element5; and the sidewall insulating films are formed by simultaneous processing with the sidewall insulating film82of the Schottky barrier diode3.

As shown inFIG. 2andFIG. 3, the Schottky barrier diode3, the high-side switching element2, and the logic element5are formed respectively in the front surfaces of the n-type semiconductor region12, the n-type semiconductor region11, and the n-type semiconductor region13that are electrically isolated from the substrate10. The Schottky barrier diode3, the high-side switching element2, and the logic element5are not electrically connected to each other via the substrate10. Currents do not flow easily into the substrate10from the Schottky barrier diode3, the high-side switching element2, and the logic element5.

The n-type semiconductor region11of the high-side switching element2and the n-type semiconductor region12of the Schottky barrier diode3are separated from each other inside the p-type substrate10. A p-type semiconductor region (a portion of the substrate10) that is of the opposite conductivity type of the n-type semiconductor region11and the n-type semiconductor region12is formed between the n-type semiconductor region11and the n-type semiconductor region12. Therefore, carrier movement between the n-type semiconductor region11and the n-type semiconductor region12is suppressed; and misoperations of the high-side switching element2and the Schottky barrier diode3do not occur easily.

In the circuit shown inFIG. 1, an average output voltage that is lower than the input voltage Vcc is output to the output line112by switching the high-side switching element2and the low-side switching element1alternately ON and OFF.

When the high-side switching element2is ON and the low-side switching element1is OFF, a current flows in the coil L from the power supply via the high-side switching element2. At this time, charge is stored in the coil L.

When the low-side switching element1is ON and the high-side switching element2is OFF, a current flows in the grounding terminal from an output terminal via the coil L and the low-side switching element1. At this time as well, the current flows and the charge is stored in the coil L.

When the high-side switching element2and the low-side switching element1are switched ON simultaneously, a shoot-through current flows in the grounding terminal from the power supply line111via the switching elements2and1. To avoid this, an interval (dead time) when the switching elements2and1both are OFF is set when setting the duty of ON and OFF of the switching elements2and1.

In the dead time, the gate of the high-side switching element2is OFF; but the current continues to flow in the coil L due to the stored charge. In other words, the drain-side potential of the high-side switching element2becomes higher than the source-side potential of the high-side switching element2; a forward voltage is applied to the body diode (the p-n junction between the p-type semiconductor region23and the n-type semiconductor region11inFIG. 3) that is built into the high-side switching element2; and a recovery current flows in the body diode. At this time, there are cases where a parasitic p-n-p transistor91schematically illustrated by the broken lines inFIG. 1andFIG. 3operates.

In the high-side switching element2, a higher breakdown voltage is realized by a depletion layer spreading from the p-n junction between the n-type semiconductor region11and the p-type substrate10. Therefore, the n-type impurity concentration of the n-type semiconductor region11and the p-type impurity concentration of the p-type substrate10are suppressed to be low.

Because the n-type impurity concentration of the n-type semiconductor region11is low, the recombination current of the base of the parasitic p-n-p transistor91decreases; a base resistance94becomes high; and a current flows easily in the substrate10.

Further, because a parasitic resistance93of the substrate10also is high, the potential of the substrate10increases easily; the base potential of an n-p-n transistor100occurring parasitically in the high-side switching element2, the substrate10, and the logic element5increases; and the parasitic n-p-n transistor100operates easily.

When the parasitic n-p-n transistor100operates, the parasitic p-n-p transistor91does not return to OFF because the base current of the parasitic p-n-p transistor91continues to be supplied; and the parasitic n-p-n transistor100also does not return to OFF because the parasitic p-n-p transistor91continues to operate. In other words, latchup occurs due to the operation of the parasitic thyristor; a large current flows into the logic element5; and there is a risk that breakdown of the logic element5may occur undesirably.

However, according to the embodiment, the Schottky barrier diode3is connected in parallel with the high-side switching element2between the power supply and the coil L.

Accordingly, in the dead time, a coil current I1is dispersed into a current I2that flows in the high-side switching element2and a current I3that flows in the Schottky barrier diode3. This can reduce the current flowing in the substrate10via the parasitic p-n-p transistor91of the high-side switching element2.

The forward voltage of the Schottky barrier diode3is lower than the forward voltage of the body diode (the p-n diode) of the high-side switching element2. For example, for a silicon material, the forward voltage of the Schottky barrier diode is about 0.35 V, while the forward voltage of the p-n diode is 0.6 V or more.

Therefore, the coil current I1flows more easily in the Schottky barrier diode3than in the body diode of the high-side switching element2; and the current flowing in the substrate10can be suppressed by the parasitic p-n-p transistor91.

By the current flowing in the substrate10being suppressed, the potential increase of the substrate10which has a high resistance is suppressed; and the element breakdown due to the latchup due to the parasitic thyristor operation can be prevented.

Also, according to the Schottky barrier diode3of the embodiment shown inFIG. 2, the off-leakage current when a reverse voltage is applied between the anode and cathode is suppressed by the insulating separation unit30provided between the cathode region43and the anode region45.

The p-type semiconductor region42that is formed to cover the corner of the insulating separation unit30on the anode side suppresses the current concentration at the corner vicinity of the insulating separation unit30.

By forming the p-type semiconductor region42, the p-n junction50is formed in the region between the anode region45and the cathode region43.

The third electrode55that is shorted to the anode electrode51is provided above the p-n junction50. The third electrode55functions as a so-called field plate electrode and relaxes the electric field when the reverse voltage of the p-n junction50is applied. In other words, a potential difference between the anode electrode51and the cathode electrode53is applied in the p-n junction50.

Such electric field relaxation due to the third electrode55, the p-type semiconductor region42, and the insulating separation unit30between the anode and cathode increases the breakdown voltage of the Schottky barrier diode3.

Due to the increase of the breakdown voltage, it is possible to further reduce an element pitch P of the Schottky barrier diode3. By reducing the element pitch P, the Schottky barrier diode3that has a low parasitic resistance and a high current capability is possible.

In the dead time described above, the decrease of the parasitic resistance of the Schottky barrier diode3increases the current capability of the Schottky barrier diode3and makes it possible for the coil current I1to substantially not flow in the high-side switching element2. This suppresses the current flowing in the substrate10via the parasitic p-n-p transistor91of the high-side switching element2and suppresses the parasitic thyristor operation of the semiconductor device.

FIG. 4is a schematic cross-sectional view of a Schottky barrier diode4of another embodiment. The same components as those of the Schottky barrier diode3described above and shown inFIG. 2are marked with the same reference numerals, and a detailed description thereof is omitted.

In the Schottky barrier diode4shown inFIG. 4as well, the insulating separation unit (the first insulating film)30is formed between the cathode region43and the anode region45. However, the p-type semiconductor region is not formed at the corner of the insulating separation unit30on the anode side; and the third electrode is not formed on the insulating separation unit30.

The anode region45has a Schottky contact with the anode electrode51via the metal silicide region47formed in the front surface of the anode region45. The metal silicide region47is separated from the insulating separation unit30which is formed with the anode region45interposed.

An insulating film (a second insulating film)83is formed on a front surface12aof the n-type semiconductor region12between the insulating separation unit30and the metal silicide region47.

In the Schottky barrier diode3shown inFIG. 2, the current flows in the cathode region43from the anode region45to flow around under the p-type semiconductor region42.

According to the Schottky barrier diode4shown inFIG. 4, because there is no p-type semiconductor region between the anode region45and the cathode region43, the effective surface area where the current flows can be wide; and the current capability can be high.

Also, according to the Schottky barrier diode4shown inFIG. 4, the metal silicide region47of the anode region45is separated from the insulating separation unit30and does not contact the insulating separation unit30. Therefore, the current concentration at the corner of the insulating separation unit30on the anode side can be relaxed; and effects similar to those of the Schottky barrier diode3ofFIG. 2in which the p-type semiconductor region42is formed at the corner of the insulating separation unit30are obtained.

Namely, in the Schottky barrier diode4ofFIG. 4as well, the off-leakage decreases; and the breakdown voltage of the Schottky barrier diode4increases. The increase of the breakdown voltage makes it possible to reduce the element pitch of the Schottky barrier diode4; and the Schottky barrier diode4that has a low parasitic resistance and a high current capability is possible.

In the dead time described above, the decrease of the parasitic resistance of the Schottky barrier diode4increases the current capability of the Schottky barrier diode4and makes it possible for the coil current I1to substantially not flow in the high-side switching element2. This suppresses the current flowing in the substrate10via the parasitic p-n-p transistor91of the high-side switching element2and suppresses the parasitic thyristor operation of the semiconductor device.

The process of forming the metal silicide region47in the front surface of the anode region45includes a process of forming a metal film on the front surface of the anode region45and a process of causing the metal of the metal film to react with the silicon of the anode region45(the n-type semiconductor region12) by annealing.

According to the embodiment shown inFIG. 4, the insulating film83is pre-formed on the front surface12aof the n-type semiconductor region12adjacent to the insulating separation unit30prior to forming the metal film on the front surface of the n-type semiconductor region12. The insulating film83is formed on the front surface12aof the n-type semiconductor region12between the insulating separation unit30and on the front surface of the anode region45to be metal-silicided.

The metal film is not formed on the front surface12awhere the insulating film83is formed; and the metal silicide region47due to the reaction between the silicon and the metal is not formed in the front surface12a.