Semiconductor device with mechanism for leak defect detection

A semiconductor device includes a plurality of signal terminals, a first power supply terminal, a second power supply terminal, a core circuit coupled to the plurality of signal terminals and the first power supply terminal, a plurality of first transistors coupled between the respective signal terminals and the second power supply terminal, and a plurality of second transistors coupled between the respective signal terminals and a ground potential, wherein the core circuit is configured to make the first transistors conductive and nonconductive alternately and make the second transistors nonconductive and conductive alternately at a time of test operation, such that one of a first transistor and a second transistor being conductive with respect to a given signal terminal requires another one of the first transistor and the second transistor to be nonconductive with respect to the given signal terminal.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based upon and claims the benefit of, priority from the prior Japanese Patent Application No. 2004-374315 filed on Dec. 24, 2004, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device provided with test functions.

2. Description of the Related Art

The SiP (system in package) structure has a configuration in which a plurality of LSI (large scale integrated circuit) chips are provided and connected together inside a single package.FIGS. 1A and 1Bare drawings showing an example of the SiP configuration.FIG. 1Aillustrates a side view of an SiP, andFIG. 1Bshows a plan view of the SiP. The SiP has a structure in which a first chip10and a second chip11are sealed inside a package12. This structure provides a highly functional, small-sized semiconductor device.

In the SiP shown inFIG. 1B, the first chip10and the second chip11have internally-confined terminals13and external-connection terminals14. The internally-confined terminals13serve to connect between the first chip10and the second chip11, and are sealed inside the package12so that no access from the exterior can be made. The external-connection terminals14are connected to the exterior of the package12so as to allow access to be made to the first chip10and the second chip11from the exterior of the package12.

Generally, tests conducted at the time of shipment of LSIs need to make sure that no leak defect is present between LSI terminals. This is done by applying a voltage between adjacent terminals-subjected to inspection and by measuring a current flowing between these terminals so as to check whether a leak current is present between the terminals, i.e., whether there is a leak defect.

In the case of the SiP as illustrated inFIG. 1, no access can be made from the exterior of the package to the terminals (internally-confined terminals13) that provide couplings between the chips inside the package and for which there is no need to exchange signals with the exterior. There is thus a problem that the measurement of leak currents between these terminals cannot be made. In order to conduct a leak defect test with respect to these terminals, either these terminals for which there is no need for external connection should be connected to the exterior or there is a need for a method of measuring inter-terminal leak currents without accessing these terminals from the exterior.

As a method of detecting a leak current without accessing terminals from an exterior, it is conceivable to set the outputs of the terminals equal to HIGH and LOW alternately and to monitor the power supply current consumed by the LSI core.FIG. 2is a drawing for explaining a method of detecting a leak defect of internally-confined terminals. InFIG. 2, the first chip10and the second chip11include core circuits20and21, respectively. The core circuits20and21are coupled to each other via the internally-confined terminals13, and the core circuit20transmits signals to the core circuit21via output buffers22.

InFIG. 2, two adjacent terminals are connected to each other through an inter-terminal short-circuit defect A. With one of these terminals set to HIGH and the other set to LOW, a leak current i2flows through the inter-terminal short-circuit defect A. A power supply voltage VDD supplied from the exterior of the package12to a power supply terminal23is monitored to detect an increase caused by the leak current i2, thereby detecting a short-circuit between terminals.

Patent Document 1 discloses providing a means to supply power separately to all the bear chips on a multi-chip circuit board, and teaches a test procedure by which power is supplied only to a bear chip to be tested among the plurality of bear chips while no power is supplied to the remaining bear chips.

In the method of detecting a leak current by monitoring a power supply current as shown inFIG. 2, a current i1consumed in the core circuit and the leak current i2are combined together when they are measured. In general, most leak defects are not a complete short-circuit between terminals, but are rather a high-resistance connection between terminals. In such a case, the leak current i2has a small current amount compared with the current i1consumed by the core circuit. When current consumption increases due to a leak during the monitoring of consolidated current consumption, therefore, it is difficult to decide whether the increase in the current consumption is caused by a leak or caused by fluctuation of currents consumed by the core circuit.

Accordingly, there is a need for a semiconductor device which can detect an inter-terminal leak defect reliably without accessing terminals.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide a semiconductor device that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.

To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a semiconductor device which includes a plurality of signal terminals, a first power supply terminal, a second power supply terminal, a core circuit coupled to the plurality of signal terminals and the first power supply terminal, a plurality of first transistors coupled between the respective signal terminals and the second power supply terminal, and a plurality of second transistors coupled between the respective signal terminals and a ground potential, wherein the core circuit is configured to make the first transistors conductive and nonconductive alternately and make the second transistors nonconductive and conductive alternately at a time of test operation, such that one of a first transistor and a second transistor being conductive with respect to a given signal terminal requires another one of the first transistor and the second transistor to be nonconductive with respect to the given signal terminal.

According to at least one embodiment of the present invention, the first transistors receiving power supply from the second power supply terminal and the second transistors coupled to the ground are made conductive and nonconductive alternately, thereby assigning the signal terminals to alternating HIGH and LOW. The second power supply terminal is independent of the first power supply terminal for driving the core circuit. Because of this, the amount of a current via the second power supply terminal is almost zero if there is no inter-terminal short-circuit defect. By detecting a current flowing via the second power supply terminal, therefore, the fact that a leak current is caused by an inter-terminal short-circuit defect can be reliably ascertained when such a leak current exists.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3is a circuit diagram showing an example of the configuration of a first embodiment of a semiconductor device according to the present invention. The semiconductor device ofFIG. 3is an SiP having a first chip31and a second chip32provided inside a package33.

The second chip32includes a core circuit34and a plurality of internally-confined terminals35. The internally-confined terminals35are connected to the first chip31.

The first chip31includes a core circuit41, a plurality of internally-confined terminals42, a power supply terminal43to which a power supply voltage VDD is supplied from an exterior, a power supply terminal44to which a power supply voltage VDDLK is supplied from an exterior, a plurality of input buffers45connected to the internally-confined terminals42, NAND gates46-1through46-4, AND gates47-1through47-4with one of their two inputs being a negative logic input, PMOS transistors48-1through48-4, and NMOS transistors49-1through49-4. The example shown inFIG. 3illustrates four internally-confined terminals42and a corresponding circuit configuration. This number is not a limiting example, and may be any other number.

The internally-confined terminals42are input terminals. Signals supplied from the second chip32are supplied as input signals IN1through IN4to the core circuit41via the input buffers45. The PMOS transistors48-1through48-4and the NMOS transistors49-1through49-4serve to set the internally-confined terminals42to HIGH or LOW at the time of testing. The core circuit41sets a test enable signal TestEN, an odd-number test signal TestOdd, and an even-number test signal TestEven, thereby controlling the conductive/nonconductive state of the above-noted transistors via the NAND gates46-1through46-4and the AND gates47-1through47-4.

At the time of normal operation, the test enable signal TestEN is set to LOW. Accordingly, the outputs of the NAND gates46-1through46-4become HIGH, making the PMOS transistors48-1through48-4nonconductive. Further, the outputs of the AND gates47-1through47-4become LOW, thereby making the NMOS transistors49-1through49-4nonconductive. Namely, signals input into the internally-confined terminals42are supplied without any change to the core circuit41via the input buffers45at the time of normal operation.

At the time of test operation, the test enable signal TestEN is set to HIGH. When a test is to be conducted by using odd-number terminals as the plus side, the odd-number test signal TestOdd is set to HIGH, and the even-number test signal TestEven is set to LOW. As a result, as shown inFIG. 3, the outputs of the NAND gates46-1through46-4are set to LOW, HIGH, LOW, and HIGH, respectively, and the outputs of the AND gates47-1through47-4are set to LOW, HIGH, LOW, and HIGH, respectively. As a result, the PMOS transistors48-1through48-4are made conductive, nonconductive, conductive, and nonconductive, respectively, and the NMOS transistors49-1through49-4are made nonconductive, conductive, nonconductive, and conductive, respectively. Namely, the internally-confined terminals42are set to HIGH and LOW alternately.

As shown inFIG. 3, the first internally-confined terminal42(TERMINAL1) and the second internally-confined terminal42(TERMINAL2) have an inter-terminal short-circuit defect A therebetween. In this case, therefore, a leak current flows from the power supply voltage VDDLK to the ground through the conductive PMOS transistor48-1, the inter-terminal short-circuit defect A, and the conductive NMOS transistor49-2. The power supply terminal44for supplying the power supply voltage VDDLK is separate from and independent of the power supply terminal43used for driving the core circuit41and the like. Because of this, the amount of a current flow with respect to the power supply voltage VDDLK is almost zero if there is no inter-terminal short-circuit defect A. By detecting a current flow with respect to the power supply voltage VDDLK, therefore, the fact that a leak current is caused by an inter-terminal short-circuit defect A can be reliably ascertained when such a leak current exists.

When a test is to be conducted by using the even-number terminals as the plus side, the even-number test signal TestEven is set to HIGH, and the odd-number test signal TestOdd is set to LOW. With these settings, the outputs of the NAND gates46-1through46-4are set to HIGH, LOW, HIGH, and LOW, respectively, and the outputs of the AND gates47-1through47-4are set to HIGH, LOW, HIGH, and LOW, respectively. As a result, the PMOS transistors48-1through48-4are made nonconductive, conductive, nonconductive, and conductive, respectively, and the NMOS transistors49-1through49-4are made conductive, nonconductive, conductive, and nonconductive, respectively. Namely, the internally-confined terminals42are set to LOW and HIGH alternately.

In the same manner as previously described, if an inter-terminal short-circuit defect A exists, a leak current flows from the power supply voltage VDDLK to the ground through the conductive PMOS transistor, the inter-terminal short-circuit defect A, and the conductive NMOS transistor. By detecting a current flow with respect to the power supply voltage VDDLK, therefore, the fact that a leak current is caused by an inter-terminal short-circuit defect A can be reliably ascertained when such a leak current exists.

FIG. 4is a circuit diagram showing an example of the configuration of a second embodiment of the semiconductor device according to the present invention. The semiconductor device shown inFIG. 4is an SiP, which includes a first chip51and a second chip52provided inside a package53.

The second chip52includes a core circuit54and a plurality of internally-confined terminals55. The internally-confined terminals55are connected to the first chip51.

The first chip51includes a core circuit61, a plurality of internally-confined terminals62, a power supply terminal63to which a power supply voltage VDD is supplied from an exterior, a power supply terminal64to which a power supply voltage VDDLK is supplied from an exterior, a plurality of AND gates65with one of their two inputs being a negative logic input, OR gates66-1through66-4, OR gates67-1through67-4, NAND gates68-1through68-4, AND gates69-1through69-4with one of their two inputs being a negative logic input, PMOS transistors70-1through70-4, and NMOS transistors71-1through71-4. The example shown inFIG. 4illustrates four internally-confined terminals62and a corresponding circuit configuration. This number is not a limiting example, and may be any other number.

The internally-confined terminals62are output terminals. Data signals Data-1through Data-4output from the core circuit61are transmitted from the internally-confined terminals62to the second chip52after propagating through the AND gates65, the OR gates66-1through66-4, the NAND gates68-1through68-4, the AND gates69-1through69-4, and output circuits comprised of the PMOS transistors70-1through70-4and the NMOS transistors71-1through71-4. Output enable signals EN-1through EN-4output from the core circuit61are set to LOW when there is a need to place the internally-confined terminals62in a floating state, and are set to HIGH during normal data output operations. The core circuit61sets a test enable signal TestEN, an odd-number test signal TestOdd, and an even-number test signal TestEven, thereby controlling the conductive/nonconductive state of the PMOS transistors70-1through70-4and the NMOS transistors71-1through71-4.

At the time of normal operation, the test enable signal TestEN, the odd-number test signal TestOdd, and the even-number test signal TestEven are all set to LOW. Further, as described above, the output enable signals EN-1through EN-4are set to HIGH. Accordingly, the data signals Data-1through Data-4pass through the AND gates65and the OR gates66-1through66-4without any change, and are inverted by the NAND gates68-1through68-4or the AND gates69-1through69-4having a negative logic input, followed by being further inverted by the output circuits (inverters) comprised of the PMOS transistors70-1through70-4and the NMOS transistors71-1through71-4for transmission from the internally-confined terminals62. In this case, the power supply voltage VDDLK is set to the same voltage as the power supply voltage VDD.

At the time of test operation, the test enable signal TestEN is set to HIGH. When a test is to be conducted by using odd-number terminals as the plus side, the odd-number test signal TestOdd is set to HIGH, and the even-number test signal TestEven is set to LOW. As a result, as shown inFIG. 4, the outputs of the NAND gates68-1through68-4are set to LOW, HIGH, LOW, and HIGH, respectively, and the outputs of the AND gates69-1through69-4are set to LOW, HIGH, LOW, and HIGH, respectively. As a result, the PMOS transistors70-1through70-4are made conductive, nonconductive, conductive, and nonconductive, respectively, and the NMOS transistors71-1through71-4are made nonconductive, conductive, nonconductive, and conductive, respectively. Namely, the internally-confined terminals62are set to HIGH and LOW alternately.

As shown inFIG. 4, the first internally-confined terminal62(TERMINAL1) and the second internally-confined terminal62(TERMINAL2) have an inter-terminal short-circuit defect A therebetween. In this case, therefore, a leak current flows from the power supply voltage VDDLK to the ground through the conductive PMOS transistor70-1, the inter-terminal short-circuit defect A, and the conductive NMOS transistor71-2. The power supply terminal64for supplying the power supply voltage VDDLK is separate from and independent of the power supply terminal63used for driving the core circuit61and the like. Because of this, the amount of a current flow with respect to the power supply voltage VDDLK is almost zero if there is no inter-terminal short-circuit defect A. By detecting a current flow with respect to the power supply voltage VDDLK, therefore, the fact that a leak current is caused by an inter-terminal short-circuit defect A can be reliably ascertained when such a leak current exists.

When a test is to be conducted by using the even-number terminals as the plus side, the even-number test signal TestEven is set to HIGH, and the odd-number test signal TestOdd is set to LOW. With these settings, the outputs of the NAND gates68-1through68-4are set to HIGH, LOW, HIGH, and LOW, respectively, and the outputs of the AND gates69-1through69-4are set to HIGH, LOW, HIGH, and LOW, respectively. As a result, the PMOS transistors70-1through70-4are made nonconductive, conductive, nonconductive, and conductive, respectively, and the NMOS transistors71-1through71-4are made conductive, nonconductive, conductive, and nonconductive, respectively. Namely, the internally-confined terminals62are set to LOW and HIGH alternately.

In the same manner as previously described, if an inter-terminal short-circuit defect A exists, a leak current flows from the power supply voltage VDDLK to the ground through the conductive PMOS transistor, the inter-terminal short-circuit defect A, and the conductive NMOS transistor. By detecting a current flow with respect to the power supply voltage VDDLK, therefore, the fact that a leak current is caused by an inter-terminal short-circuit defect A can be reliably ascertained when such a leak current exists.

FIG. 5is a table chart showing allocation of logic values to the terminals of the semiconductor device of the second embodiment shown inFIG. 4in the case of test operation and in the case of normal operation. As shown inFIG. 5, in a LEAK TEST1that sets the odd-number internally-confined terminals62to HIGH, the test enable signal TestEN, the odd-number test signal TestOdd, and the even-number test signal TestEven are set to HIGH, HIGH, and LOW, respectively. The logic values of the data signals Data-1through Data-4and the output enable signals EN-1through EN-4are “don't care”. In a LEAK TEST2that sets the even-number internally-confined terminals62to HIGH, the test enable signal TestEN, the odd-number test signal TestOdd, and the even-number test signal TestEven are set to HIGH, LOW, and HIGH, respectively. The logic values of the data signals Data-1through Data-4and the output enable signals EN-1through EN-4are “don't care”.

At the time of normal operation, the test enable signal TestEN is set to LOW. Setting the output enable signals EN-1through EN-4to LOW results in the outputs being placed in the floating state (high-impedance state). Setting the output enable signals EN-1through EN-4to HIGH results in the outputs having signal levels responsive to the data signals Data-1through Data-4. The odd-number test signal TestOdd and the even-number test signal TestEven are “don't care”.

FIG. 6is a circuit diagram showing an example of the configuration of a third embodiment of the semiconductor device according to the present invention. InFIG. 6, the same elements as those ofFIG. 4are referred to by the same numerals, and a description thereof will be omitted unless necessary.

The semiconductor device shown inFIG. 6is an SiP, and includes a first chip51A and the second chip52provided inside a package53A. The first chip51A includes the core circuit61, the plurality of internally-confined terminals62, the power supply terminal63to which a power supply voltage VDD is supplied from an exterior, the power supply terminal64to which a power supply voltage VDDLK is supplied from an exterior, the plurality of AND gates65with one of their two inputs being a negative logic input, NAND gates81-1through81-4, AND gates82-1through82-4with one of their two inputs being a negative logic input, OR gates83-1through83-4, PMOS transistors84-1through84-4, NMOS transistors85-1through85-4, AND gates86and87, inverters88and89, and PMOS transistors90-1through90-4. The example shown inFIG. 6illustrates four internally-confined terminals62and a corresponding circuit configuration. This number is not a limiting example, and may be any other number.

In the second embodiment shown inFIG. 4, the output circuit (the PMOS transistors70-1through70-4and the NMOS transistors71-1through71-4) used in the normal data output operation is utilized to detect a leak current at the time of test operation. In such a configuration, the PMOS transistors70-1through70-4and the NMOS transistors71-1through71-4need to have sufficient output signal drive capability. To this end, the power supply voltage VDDLK needs to be supplied to these transistors through power supply wires having an equivalent thickness to that of the power supply wires used for the power supply voltage VDD. The independent power supply voltage VDDLK and its transmission path are a layout portion that is separate from the power supply voltage VDD and its transmission path, and that becomes necessary only for the purpose of conducting a test operation according to the present invention. If the wires of this layout portion are thick, they may undesirably become a burden on the designing of the entire layout.

In the third embodiment shown inFIG. 6, the PMOS transistors90-1through90-4for conducting a test operation according to the present invention are provided separately from the output circuits used for the normal output operation, and the power supply voltage VDDLK is supplied to these transistors. The output circuits used for the normal output operation are comprised of the PMOS transistors84-1through84-4and the NMOS transistors85-1through85-4, which receive the normal power supply voltage VDD through normal power supply paths. With this provision, the PMOS transistors84-1through84-4and the NMOS transistors85-1through85-4constituting the output circuits can drive output signals with sufficient drive power.

It suffices to supply a current only for the test purposes to the PMOS transistors90-1through90-4provided for the test purposes. Thus, the power supply wires for supplying the power supply voltage VDDLK do not have to be thick. In the configuration of the second embodiment shown inFIG. 4, the power supply wires for the power supply voltage VDDLK may need to have a thickness of about 30 to 40 micrometers, for example. In the configuration of the third embodiment shown inFIG. 6, on the other hand, the power supply wires for the power supply voltage VDDLK are sufficiently thick even if their thickness is less than about 5 micrometers. The third embodiment can thus reduce an effect of the layout portion necessary for the purpose of test operation on the designing of the entire layout.

The data output operation and test operation are the same as in the second embodiment. Namely, at the time of normal operation, the test enable signal TestEN, the odd-number test signal TestOdd, and the even-number test signal TestEven are all set to LOW. Further, the output enable signals EN-1through EN-4are set to HIGH. With these settings, the data signals Data-1through Data-4output from the core circuit61are transmitted from the internally-confined terminals62to the second chip52. In this case, the PMOS transistors90-1through90-4have the gate node thereof receiving HIGH so as to be nonconductive. Accordingly, the PMOS transistors90-1through90-4do not affect the data output operation in any manner.

At the time of test operation, the test enable signal TestEN is set to HIGH. When a test is to be conducted by using odd-number terminals as the plus side, the odd-number test signal TestOdd is set to HIGH, and the even-number test signal TestEven is set to LOW. As a result, as shown inFIG. 6, the outputs of the NAND gates81-1through81-4are all set to HIGH, and the outputs of the OR gates83-1through83-4are set to LOW, HIGH, LOW, and HIGH, respectively. As a result, the PMOS transistors84-1through84-4are all made nonconductive, and the NMOS transistors85-1through85-4are made nonconductive, conductive, nonconductive, and conductive, respectively.

Further, based on the test enable signal TestEN, the odd-number test signal TestOdd, and the even-number test signal TestEven, a circuit comprised of the AND gates86and87and the inverters88and89sets the gate potentials of the PMOS transistors90-1through90-4to LOW, HIGH, LOW, and HIGH, respectively. As a result, the PMOS transistors90-1through90-4are made conductive, nonconductive, conductive, and nonconductive, respectively. Namely, the internally-confined terminals62are set to HIGH and LOW alternately.

As shown inFIG. 6, the first internally-confined terminal62(TERMINAL1) and the second internally-confined terminal62(TERMINAL2) have an inter-terminal short-circuit defect A therebetween. In this case, therefore, a leak current flows from the power supply voltage VDDLK to the ground through the conductive PMOS transistor90-1, the inter-terminal short-circuit defect A, and the conductive NMOS transistor85-2. The power supply terminal64for supplying the power supply voltage VDDLK is separate from and independent of the power supply terminal63used for driving the core circuit61and the like. Because of this, the amount of a current flow with respect to the power supply voltage VDDLK is almost zero if there is no inter-terminal short-circuit defect A. By detecting a current flow with respect to the power supply voltage VDDLK, therefore, the fact that a leak current is caused by an inter-terminal short-circuit defect A can be reliably ascertained when such a leak current exists.

When a test is to be conducted by using the even-number terminals as the plus side, the even-number test signal TestEven is set to HIGH, and the odd-number test signal TestOdd is set to LOW. In the same manner as described above, detecting a current flow with respect to the power supply voltage VDDLK makes it possible to detect reliably an inter-terminal short-circuit defect.

FIG. 7is a table chart showing allocation of logic values to the terminals of the semiconductor device of the third embodiment shown inFIG. 6in the case of test operation and in the case of normal operation. As shown inFIG. 7, in a LEAK TEST1that sets the odd-number internally-confined terminals62to HIGH, the test enable signal TestEN, the odd-number test signal TestOdd, and the even-number test signal TestEven are set to HIGH, HIGH, and LOW, respectively. The logic values of the data signals Data-1through Data-4and the output enable signals EN-1through EN-4are “don't care”. In a LEAK TEST2that sets the even-number internally-confined terminals62to HIGH, the test enable signal TestEN, the odd-number test signal TestOdd, and the even-number test signal TestEven are set to HIGH, LOW, and HIGH, respectively. The logic values of the data signals Data-1through Data-4and the output enable signals EN-1through EN-4are “don't care”.

At the time of normal operation, the test enable signal TestEN, the odd-number test signal TestOdd, and the even-number test signal TestEven are all set to LOW. Setting the output enable signals EN-1through EN-4to LOW results in the outputs being placed in the floating state (high-impedance state). Setting the output enable signals EN-1through EN-4to HIGH results in the outputs having signal levels responsive to the data signals Data-1through Data-4.

FIG. 8is a timing chart showing an example of signal patterns at the time of test operation with respect to the second and third embodiments. As shown inFIG. 8, the test enable signal TestEN, the odd-number test signal TestOdd, the even-number test signal TestEven, the data signals Data-1through Data-4, and the output enable signals EN-1through EN-4are all set to LOW in the initial state.

After entering into a leak test mode, the test enable signal TestEN, the odd-number test signal TestOdd, the even-number test signal TestEven are set to HIGH, HIGH, and LOW, respectively, for a duration of three clock cycles, for example. During the second clock cycle, for example, a current flow with respect to the power supply voltage VDDLK is measured, thereby detecting a leak current that flows between TERMINAL1through TREMINAL4(seeFIG. 4andFIG. 6).

After this, the test enable signal TestEN, the odd-number test signal TestOdd, the even-number test signal TestEven are set to HIGH, LOW, and HIGH, respectively, for a duration of three clock cycles, for example. During the second clock cycle, for example, a current flow with respect to the power supply voltage VDDLK is measured, thereby detecting a leak current that flows between TERMINAL1through TREMINAL4(seeFIG. 4andFIG. 6).

FIGS. 9A through 9Care drawings for explaining a fourth embodiment of the semiconductor device according to the present invention. In FIGS.9A through9C, the same elements as those ofFIG. 3are referred to by the same numerals, and a description thereof will be omitted unless necessary.

FIG. 9Aillustrates signal settings at the time of normal operation in the configuration of the first embodiment shown inFIG. 3. As illustrated, the core circuit41assigns the test enable signal TestEN and the odd-number test signal TestOdd to LOW, thereby setting the gate potential of the PMOS transistor48-1to HIGH and the gate potential of the NMOS transistor49-1to LOW. With these settings, both the PMOS transistor48-1and the NMOS transistor49-1become nonconductive, so that data input via the internally-confined terminal42is supplied to the core circuit41without being affected.

FIG. 9Bis a drawing showing the configuration of an ESD (electro-static discharge) protection circuit that is provided for the purpose of preventing destruction caused by electrostatic discharge at the signal input portion of a semiconductor chip. The ESD protection circuit shown inFIG. 9Bincludes a PMOS transistor101and an NMOS transistor102. In general, an IC based on the MOS structures is susceptible to static electricity. For example, as a man charged with electrostatic touches a terminal of a chip, charges are discharged through the semiconductor device, resulting in the destruction of the device. In order to prevent such destruction by electrostatic discharge, the ESD protection circuit as shown inFIG. 9Dis provided at the input/output portion of a chip.

FIG. 9Cshows an equivalent circuit to the ESD protection circuit shown inFIG. 9B. This equivalent circuit includes a diode103and a diode104. As a potential at the internally-confined terminal42increases toward a positive potential due to electrostatic charge, the diode103becomes conductive, thereby allowing the charge to escape to the power supply voltage VDD. As the potential at the internally-confined terminal42decreases toward a negative potential due to electrostatic charge, the diode104becomes conductive, thereby allowing the charge to escape to the ground potential. Allowing the energy of electrostatic to escape to a power supply line in this manner can protect the semiconductor device.

As can be understood by inspecting the configuration of the ESD protection circuit shown inFIG. 9B, the configuration of transistors of this ESD protection circuit is the same as the configuration of transistors of the test circuit at the time of normal operation according to the present invention as shown inFIG. 9A. It is thus understood that the PMOS transistor48-1and NMOS transistor49-1of the test circuit of the present invention serve to provide the function of an ESD protection circuit at the time of normal operation.

Accordingly, in the configuration of the first chip31shown inFIG. 3, the PMOS transistors48-1through48-4and NMOS transistors49-1through49-4provided for the purpose of test operation of the present invention also serve as an ESD protection circuit. There is thus no need for an ESD protection circuit to be separately provided while such provision was necessary in the conventional art. In other words, there is no need in the fourth embodiment to provide an ESD protection circuit that was necessary in the related art. The forth embodiment can thus suppress a size increase resulting from the addition of the circuit of the present invention.

In the embodiments described above, a circuit dedicated for the purpose of setting internally-confined terminals to alternating HIGH and LOW is provided. The provision of the dedicated circuit makes it possible to set the internally-confined terminals to alternating HIGH and LOW by simply controlling the logic values of the test enable signal TestEN, the odd-number test enable signal TestOdd, and the even-number test signal TestEven by use of the core circuit. This is advantageous in that operations necessary for testing are simple.

Nonetheless, the present invention is not limited to the configuration in which such a dedicated circuit is provided. For example, instead of providing a dedicated circuit, data signals output from the core circuit (e.g., Data-1through Data-4of the above-described embodiments) may be set to alternating HIGH and LOW for the purpose of conducting a test. In this case, an operation for setting the data signals becomes necessary at the time of test operation, but the proposed configuration is advantageous in a sense that there is no need for a circuit dedicated for data setting.

Namely, the present invention only requires a circuit inside a chip that can be used to set the internally-confined terminals to alternating HIGH and LOW regardless of whether this circuit is a dedicated circuit for outputting setting signals at the time of test or is a core circuit that outputs data output signals.

Further, the above-described embodiments have been directed to an example in which the SiP configuration is used. Notwithstanding this, the present invention is equally applicable to a semiconductor device other than that of the SiP configuration. Namely, the present invention is applicable even if the chip is not provided in an SiP, or is not designed for use in an SiP, but is designed to be used alone. In this case, in order to make sure than there is no leak defect between chip terminals at the time of testing prior to shipment of the chip, an efficient leak defect check can be made by eliminating a series of operations such as bringing a probe or the like in contact with adjacent terminals to be checked, applying voltages, and measuring a current flowing between these terminals. Further, testing can be done even if the number of available pins of the testing apparatus is smaller than the number of signal pins (terminals) of the chip. This allows the use of an inexpensive testing equipment to be used, thereby achieving cost reduction.