DC-DC converter with substantially constant on-time and constant switching frequency

A comparator-system DC-DC converter 1 according to an embodiment of the present invention comprises a control unit 200 which has a comparator section 20, 40 which compares the output voltage of the voltage conversion section with a reference voltage and determines a predetermined ON width of the ON pulse of the control signal Ssw or a predetermined OFF width of the OFF pulse of the control signal Ssw, and frequency control means 25 which compares the control signal Ssw with reference clock Cref and adjusts the ON width or OFF width so that the frequency of the control signal Ssw is constant. The frequency control means 25 detects a state where the output current of the voltage conversion section 100 is 0 A or a state where the output current is going to be 0 A and stops the processing to adjust the ON width or OFF width.

TECHNICAL FIELD

The present invention relates to a comparator-system DC-DC converter.

BACKGROUND ART

DC-DC converters which generate an output voltage that is stabilized by an input voltage are known. A variety of systems have been proposed as means for stabilizing the output voltage of a DC-DC converter. For example, Patent Document 1 mentions a switching DC-DC converter which uses a PWM (pulse width modulation) system. With the PWM system, the output voltage can be stabilized by fixing the switching frequency and adjusting the ON pulse width. There are also switching DC-DC converters which employ a comparator system. With a comparator system, the output voltage can be stabilized by using the comparator to fix the ON pulse width and adjust the OFF pulse width (that is, the switching frequency).

This DC-DC converter is sometimes used as the power source of a PU (Processor Unit) or the like. When the PU moves from a standby state to a processing state, the current consumption increases suddenly. When the output voltage suddenly drops as a result of a sudden increase in the load current, the comparator-system DC-DC converter immediately outputs an ON pulse and, therefore, in comparison with a PWM system which is incapable of outputting a pulse in a predetermined OFF pulse period, the output voltage stabilizes rapidly. Thus, in comparison with a PWM system, a comparator-system DC-DC converter may have the characteristic of a favorable response characteristic with respect to a sudden increase in the load current.

DISCLOSURE OF INVENTION

Problem to be Solved by the Invention

Furthermore, in a comparator-system DC-DC converter, the switching cycle Tf is Tf=Pon+Poff=Vout/Vin×Tf+((Vin−Vout)/Vin)×Tf . . . (Equation (1)) where the ON pulse width is Pon, the OFF pulse width is Poff, the input voltage is Vin, and the output voltage is Vout. Therefore, in cases where Vin and Vout are fixed, the ON pulse width Pon is constant and Poff is therefore fixed uniquely. In other words, with the comparator-system DC-DC converter, because the Pon is constant, if Vin and Vout are fixed, the ON duty for making the output voltage constant is fixed.

Here, for example, when the ambient temperature rises, the internal resistance of the circuit element increases and the internal loss increases. Here, with the comparator-system DC-DC converter, the OFF pulse width grows short and the ON duty increases in order to compensate for the drop in the output voltage due to the increase in the internal loss. Thus, with the comparator-system DC-DC converter, the switching frequency gradually fluctuates due to the fluctuations in the ambient temperature. Otherwise, the OFF pulse width also fluctuates and the switching frequency fluctuates due to fluctuations in the input voltage, output voltage, and output current. Due to fluctuations in the switching frequency, the ripple of the output voltage fluctuates and there is the possibility of a downstream circuit such as the PU operating erroneously. There is also the possibility of EMI countermeasures extending over a wide bandwidth being required.

However, although the switching frequency can be constant for a PWM-system DC-DC converter, in discontinuous mode, which has a period during which the load current is small and the output current is equal to or less than 0 A, the ON pulse width is sometimes excessively narrow. As a result, the possibility of a disturbance of the switching waveform exists. Circuit elements require a high speed characteristic.

Therefore, an object of the present invention is to provide a comparator-system DC-DC converter which is capable of reducing fluctuations in the switching frequency without impairing the response characteristic with respect to a sudden increase in the load current in a continuous load current mode and which is capable of suppressing an excessively narrow ON pulse width in the discontinuous load current mode.

Means for Solving the Problem

The comparator-system DC-DC converter of the present invention comprises a voltage conversion section which has an input terminal to which an input voltage is input and a pair of output terminals, and further has a switching element having one current terminal connected to the input terminal, an inductor having one end connected to the other current terminal of the switching element and another end connected to one of the pair of output terminals, and a smoothing capacitor connected between the pair of output terminals, the voltage conversion section generating an output voltage which is obtained by voltage-converting the input voltage, across the pair of output terminals by controlling the switching element in accordance with a control signal which is a pulse signal; and a control unit which generates the control signal for stabilizing the output voltage of the voltage conversion section. The control unit comprises a comparator section which compares the output voltage of the voltage conversion section with a reference voltage and determines a predetermined ON width of an ON pulse of the control signal or a predetermined OFF width of the OFF pulse of the control signal in accordance with the comparison result; and frequency control means which compares the control signal with a reference clock and adjusts the predetermined ON width of the ON pulse or the predetermined OFF width of the OFF pulse in accordance with the comparison result so that the repetition frequency of the control signal is constant. The frequency control means comprises an adjustment stoppage section which detects a state where an output current which flows in a direction from the switching element of the voltage conversion section toward the inductor is 0 A or a state where the output current is going to be 0 A and generates an adjustment stoppage signal which stops the processing of the frequency control means to adjust the predetermined ON width or the predetermined OFF width.

With the comparator-system DC-DC converter, in continuous load current mode, a predetermined ON width of the ON pulse (predetermined OFF width of the OFF pulse) is also adjusted by frequency control means in cases where the OFF width of the OFF pulse has narrowed as a result of an increase in the output current, for example (in cases where the ON width of the ON pulse has widened) and the frequency of the control signal is kept fixed. Therefore, in the continuous load current mode, fluctuations in the switching frequency can be reduced.

Here, the frequency control means keep the frequency of the control signal constant by adjusting the predetermined ON width of the ON pulse (predetermined OFF width of the OFF pulse). Hence, the ON width of the ON pulse is sometimes excessively narrow in the discontinuous load current mode as is the case with the PWM system.

However, with this comparator-system DC-DC converter, because the processing to adjust the predetermined ON width of the ON pulse (the predetermined OFF width of the OFF pulse) is stopped by the frequency control means in cases where the output current is 0 A or is going to be 0 A in the discontinuous load current mode, a narrowing of the ON width of the ON pulse is suppressed. Hence, in the discontinuous load current mode, a substantial narrowing of the ON width of the ON pulse can be suppressed.

The comparator section preferably comprises a first comparator which detects that the output voltage of the voltage conversion section is smaller than the reference voltage and determines the detection time point as the start time point of the ON pulse (OFF pulse); and a second comparator which detects that a predetermined time has elapsed since the start time point of the ON pulse (OFF pulse) and determines the detection time point as the end time point of the ON pulse (OFF pulse), and wherein the frequency control means preferably comprises an adjustment section which adjusts the predetermined ON width (the predetermined OFF width) by adjusting the predetermined time.

The frequency control means preferably comprises a reference clock generation section which generates the reference clock; and in cases where the frequency control means acquires the adjustment stoppage signal from the adjustment stoppage section, the reference clock generation section preferably temporarily stops the generation of the reference clock and stops the processing to adjust the predetermined ON width or the predetermined OFF width.

With a constitution of this kind, because the generation of the reference clock is temporarily stopped by the reference clock generation means in cases where the adjustment stoppage signal is acquired from the adjustment stoppage section, changes in the results of the comparison between the control signal and reference clock by the frequency control means can be stopped. The processing to adjust the predetermined ON width or the predetermined OFF width performed by the frequency control means can therefore be stopped.

Furthermore, in cases where the frequency control means acquires the adjustment stoppage signal from the adjustment stoppage section, the frequency control means may stop the comparison between the control signal and the reference clock and stop the processing to adjust the predetermined ON width or the predetermined OFF width.

With a constitution of this kind, because the comparison between the control signal and reference clock is stopped by the frequency control means in cases where the adjustment stoppage signal is acquired from the adjustment stoppage section, changes in the result of the comparison between the control signal and reference clock can be stopped. Hence, the processing to adjust the predetermined ON width or predetermined OFF width performed by the frequency control means can be stopped.

In addition, in cases where the adjustment stoppage signal is acquired from the adjustment stoppage section, the frequency control means may stop the processing to adjust the predetermined ON width or the predetermined OFF width by substituting the result of comparing the control signal with the reference clock, with a predetermined fixed value which is determined beforehand.

With a constitution of this kind, because the result of comparing the control signal with the reference clock is substituted with a predetermined fixed value which is determined beforehand by the frequency control means in cases where the adjustment stoppage signal is acquired from the adjustment stoppage section, the processing to adjust the predetermined ON width or the predetermined OFF width can be stopped.

EFFECTS OF THE INVENTION

The present invention makes it possible to obtain a comparator-system DC-DC converter which is capable of reducing fluctuations in the switching frequency without impairing the response characteristic with respect to a sudden increase in the load current in a continuous load current mode and which is able to suppress an excessively narrow ON pulse width in the discontinuous load current mode.

LIST OF ELEMENTS

BEST MODE FOR CARRYING OUT THE INVENTION

Preferred embodiments of the present invention will be described in detail hereinbelow with reference to the drawings. The same reference numerals are assigned to the same parts or to equivalent parts in each of the drawings.

First Embodiment

FIG. 1is a circuit diagram which shows a comparator-system DC-DC converter according to the first embodiment of the present invention. The comparator-system DC-DC converter1shown inFIG. 1is constituted by a voltage conversion section100and a control unit200.

The voltage conversion section100produces, at an output terminal3, an output voltage Vout obtained by voltage-converting the input voltage Vin which is applied to the input terminal2in accordance with a switching control signal Ssw from the control unit200. That is, the voltage conversion section100generates an output voltage Vout across a pair of output terminals which are constituted by an output terminal3and an output terminal (not shown) which is connected to GND5. The voltage conversion section100comprises a switching element11, a diode12, a drive circuit13, an inductor14, and a capacitor15.

The switching element11is an N-type MOSFET and the two terminals thereof constitute a current element. The drain of the switching element11is connected to the input terminal2and the source of the switching element11is connected to the cathode of the diode12. The anode of the diode12is grounded to GND5. The gate of the switching element11is connected to a drive circuit13.

The drive circuit13generates a drive signal in accordance with the switching control signal Ssw from the control unit200and supplies the drive signal to the gate of the switching element11.

One end of the inductor14is connected to the source of the switching element11and the cathode of the diode12. The other end of the inductor14is connected to the output terminal3. A capacitor (smoothing capacitor)15for smoothing the output voltage is connected between the other end of the inductor14and output terminal3, and GND5.

The control unit200generates a switching control signal Ssw for stabilizing the output voltage Vout of the voltage conversion section100. The control unit200comprises a first comparator20, a timer section30, a second comparator40, an SR-FF50, an adjustment section60, an adjustment stoppage section70, and a reference clock generation section80. According to this embodiment, the timer section30, adjustment section60, adjustment stoppage section70, and reference clock generation section80function as frequency control means25.

The positive input terminal of the first comparator20is connected to the output terminal3of the voltage conversion section100and a reference voltage Vref is input to the negative input terminal. The output terminal of the first comparator20is connected to the set terminal of the timer section30and SR-FF50.

The timer section30comprises a fixed current generation circuit31, a timer capacitor32, and a transistor33. The fixed current generation circuit31is connected between the input terminal2and the timer capacitor32and supplies a charging current of a constant value to the timer capacitor32. The fixed current generation circuit31is able to change the value of the charging current in accordance with a frequency control signal Sf from the adjustment section60.

The timer capacitor32is connected between the fixed current generation circuit31and GND5. The transistor33is connected in parallel across the terminals of the timer capacitor32. That is, the drain of the transistor33is connected to the node between the fixed current generation circuit31and one end of the timer capacitor32and the source of the transistor33is connected to GND5. An output voltage Von from the first comparator20is input to the gate of the transistor33.

The node between the fixed current generation circuit31and one end of the timer capacitor32is connected to the positive input terminal of the second comparator40. The output voltage Vout is input to the negative input terminal of the second comparator40. The output terminal of the second comparator40is connected to the reset terminal of the SR-FF50.

The SR-FF50ends the generation of the OFF pulse and starts the generation of the ON pulse of the switching control signal Ssw and ends the generation of the OFF pulse in accordance with the output voltage Von of the first comparator20, and ends the generation of the ON pulse of the switching control signal Ssw and starts the generation of the OFF pulse in accordance with the output voltage Voff of the second comparator40. The control signal Ssw is a pulse signal.

Thus, the first comparator20detects that the output voltage Vout of the voltage conversion section100is smaller than the reference voltage Vref, sets the SR-FF50by producing a high-level pulse voltage Von, and determines the detection time point as the start time point of the ON pulse of the switching control signal Ssw.

In this embodiment, the fixed current generation circuit31receives the input voltage Vin which is connected to the input terminal2. However, as long as the output supply source of the fixed current generation circuit31is at predetermined potential difference with respect to GND5and is capable of supplying the output current required for the fixed current generation circuit31, the fixed current generation circuit31is not limited to the input voltage Vin of input terminal2.

Furthermore, the timer section30resets the voltage across the terminals of the timer capacitor32in accordance with the high-level pulse voltage Von of the first comparator20and subsequently functions as a timer by charging the timer capacitor32by means of a fixed current.

In addition, the second comparator40detects that the voltage across the terminals of the timer capacitor32of the timer section30is equal to or more than the output voltage Vout, that is, detects that a predetermined time has elapsed since the start time point of the ON pulse, and resets the SR-FF50by producing the high level pulse voltage Voff, and determines the detection time point as the end time point of the ON pulse of the switching control signal Ssw.

In other words, the first comparator20and second comparator40function as comparator sections which determine the predetermined ON width of the ON pulse of the switching control signal Ssw.

The adjustment section60receives the switching control signal Ssw and a reference clock Cref which is generated by the reference clock generation section80. The adjustment section60compares the switching control signal Ssw with the reference clock Cref and adjusts the predetermined ON width of the ON pulse so that the frequency of the switching control signal Ssw is constant in accordance with the comparison result. More specifically, the adjustment section60counts the ON pulses of the switching control signal Ssw, counts the reference clocks, and generates the frequency control signal Sf for adjusting the predetermined ON width of the ON pulse so that the count value of the switching control signal Ssw and the count value of the reference clock are equal. In the comparator-system DC-DC converter according to this embodiment, a frequency control signal Sf is a 4-bit digital signal.

The input terminal of the adjustment stoppage section70is connected to one end of the inductor14and the output terminal is connected to the reference clock generation section80. The switching control signal Ssw is input to the reset terminal of the adjustment stoppage section70. The adjustment stoppage section70detects the output current IL that flows in a direction toward the inductor14from the switching element11or the diode12and, in cases where the value of the output current IL is 0 A, stops the processing to adjust the predetermined ON width of the ON pulse. More specifically, the adjustment stoppage section70generates an adjustment stoppage signal Sstop for stopping the reference clock generation section80from the point where the resonance voltage V11produced at one end of the inductor14is detected when the value of the output current IL is 0 A until the time point where the ON pulse of the switching control signal Ssw is produced.

The reference clock generation section80generates the reference clock Cref and stops the generation of the reference clock Cref in accordance with the adjustment stoppage signal Sstop from the adjustment stoppage section70. More specifically, the reference clock generation section80latches the voltage level of the reference clock Cref in accordance with the adjustment stoppage signal Sstop and stops the generation of the reference clock Cref.

The timer section30, adjustment section60, adjustment stoppage section70, and reference clock generation section80will be described next in detail.FIG. 2is a circuit which shows the timer section30ofFIG. 1andFIG. 3is a circuit diagram which shows the adjustment section60ofFIG. 1. Furthermore,FIG. 4is a circuit diagram which shows the adjustment stoppage section70ofFIG. 1andFIG. 5is a circuit diagram which shows the reference clock generation section80ofFIG. 1.

First, the timer section30will be described.FIG. 2shows the fixed current generation circuit31of the timer section30in detail. The fixed current generation circuit31comprises an input voltage division circuit34, a voltage follower35, a resistance element36, a current mirror circuit37, a gm amplifier38, and a digital/analog conversion section (known as a ‘DAC’ hereinbelow)39.

The input voltage division circuit34divides the input voltage Vin which is input from the input terminal2. In this embodiment, the input voltage division circuit34is constituted by resistance elements34aand34bwhich are connected in series between the input terminal2and GND5. The divided voltage between the resistance elements34aand34bis input to the voltage follower35.

The voltage follower35is constituted by an error difference amplifier35aand a transistor35b. In this embodiment, the transistor35bis an n-type MOSFET. The resistance element36is connected between the source of the transistor35band GND5. Furthermore, the current mirror circuit37is connected between the drain of the transistor35band the input terminal2.

The current mirror circuit37is constituted by a transistor37athrough which a reference current determined by the voltage follower35flows and a transistor37bwhich generates a mirror current of the reference current which flows to the transistor37a. In this embodiment, the transistors37aand37bare p-type MOSFETs. The transistor37bsupplies this mirror current to the timer capacitor32.

The DAC39converts the 4-bit digital frequency control signal Sf from the adjustment section60into an analog signal. The output terminal of the DAC39is connected to one input terminal of the gm amplifier38.

The reference voltage Vref2is input to the other input terminal of the gm amplifier38. The output terminal of the gm amplifier38is connected to a node between the transistor37aof the current mirror circuit37and the voltage follower35.

The gm amplifier38functions as a push/pull-type current source, drawing a current from the transistor37aof the current mirror circuit37when the output signal of the DAC39is equal to or more than the reference voltage Vref2, for example, and supplying a current to the voltage follower35when the output signal of the DAC39is smaller than the reference voltage Vref2. In other words, the gm amplifier38increases the charging current of the timer capacitor32when Sf is equal to or more than Vref2and reduces the charging current of the timer capacitor32when Sf is smaller than Vref2.

The adjustment section60will be described next. As shown inFIG. 3, the adjustment section60comprises two counters61and62and an up/down counter68.

A switching control signal Ssw is input to the input terminal of the first counter61and the output voltage of the second counter62is input to the reset terminal of the first counter61. For example, the first counter61is a 4-bit counter. The first counter61counts the ON pulse of the switching control signal Ssw and, in cases where the count value reaches the maximum value ‘1111’, outputs the high-level pulse voltage Vdown and resets the output voltage at the next count of ‘1111’. In addition, the first counter61also resets the output voltage when the output voltage of the second counter62has reached a high level. The output terminal of the first counter61is connected to one input terminal of the up/down counter68.

The reference clock Cref is input to the input terminal of the second counter62and the output voltage of the first counter61is input to the reset terminal of the second counter62. The second counter62is a 4-bit counter, for example. The second counter62counts the reference clock cycles and, in cases where the count value has reached a maximum value ‘1111’, outputs a high-level pulse voltage Vup and resets the output voltage at the next count of ‘1111’. In addition, the second counter62also resets the output voltage when the output voltage of the first counter61has reached a high level. The output terminal of the second counter62is connected to the other input terminal of the up/down counter68.

The up/down counter68receives the pulse voltage from the first counter61and the pulse voltages Vdown and Vup from the second counter62and increases or reduces the count value. In this embodiment, the up/down counter68reduces the count value when a high-level pulse voltage Vdown is input by the first counter61and increases the count value when a high-level pulse voltage Vup is input by the second counter62. The up/down counter68outputs the 4-bit digital frequency control signal Sf to the timer section30.

The adjustment stoppage section70will be described next. As shown inFIG. 4, the adjustment stoppage section70comprises a detected voltage division circuit71, a comparator72, a Zener diode73, and a D-FF74.

The detected voltage division circuit71divides the voltage V11of one end of the inductor14. In this embodiment, the detected voltage division circuit71is constituted by resistance elements71aand71bwhich are connected in series between one end of the inductor14and GND5. The divided voltage between the resistance elements71aand71bis input to the positive input terminal of the comparator72.

The Zener diode73is connected between the positive input terminal of the comparator72and GND5. Here, the voltage V11at one end of the inductor14rises to the input voltage Vin when the switching element11enters an ON state. The Zener diode73is provided in order to provide overvoltage protection for the input terminal of the comparator72.

A reference voltage Vref3is input to the negative input terminal of the comparator72. The comparator72outputs a high-level pulse voltage when the resonance voltage V11is produced at one end of the inductor14and the divided voltage between the resistance elements71aand71bis greater than the reference voltage Vref3. Thus, the comparator72functions as a current detection section which detects the time point at which the output current IL reaches 0 A by detecting the occurrence of the resonance voltage V11at one end of the inductor14. The output terminal of the comparator72is connected to the clock terminal of the D-FF74.

The input voltage Vin is input to the input terminal of the D-FF74and the switching control signal Ssw is input to the reset terminal. The D-FF74generates a high-level adjustment stoppage signal Sstop in the period from the time point at which a high-level pulse voltage is received from the comparator72until the time point at which a high-level switching control signal Ssw is received, that is, the period in which the output current IL is 0 A.

The reference clock generation section80will be described next. As shown inFIG. 5, the reference clock generation section80comprises an oscillator81, an EXOR circuit82, three D-FF83,84, and85.

The adjustment stoppage signal Sstop is input to one input terminal of the EXOR circuit82while the other input terminal is connected to the inverting output terminal of the D-FF83. The output terminal of the EXOR circuit82is connected to the input terminal of the D-FF83.

Clocks from the oscillator81are input to the clock terminal of the D-FF83and the non-inverting output terminal is connected to the clock terminal of the D-FF84.

The input terminal of the D-FF84is connected to the inverting output terminal and the output terminal of the D-FF84is connected to the clock terminal of the D-FF85. Likewise, the input terminal of the D-FF85is connected to the inverting output terminal and the D-FF85outputs the reference clock Cref from the non-inverting output terminal.

Thus, the EXOR82and the D-FF83,84, and85constitute a clock division circuit and generate the reference clock Cref, which is obtained by dividing the clock from the oscillator into eight, when the adjustment stoppage signal Sstop is at a low level. In addition, the clock division circuit latches the voltage level of the reference clock Cref and stops the reference clock Cref when the adjustment stoppage signal Sstop is at a high level signal. In other words, the clock division circuit lowers the frequency of the reference clock Cref when the adjustment stoppage signal Sstop is a high level signal.

The operation of the comparator-system DC-DC converter1will be described next.FIG. 6is a timing chart which shows the respective signal waveforms of the continuous current mode of the comparator-system DC-DC converter1shown inFIG. 1andFIG. 7is a timing chart which shows the respective signal waveforms of the continuous current mode of the adjustment section60shown inFIG. 3.

First, when the input voltage Vin is input to the input terminal2, the switching control signal Ssw is generated by the control unit200. The voltage conversion section100produces a stabilized output voltage Vout at the output terminal3in accordance with the switching control signal Ssw.

Here, in cases where the load current is relatively large, the comparator-system DC-DC converter1operates in continuous current mode in which the output current is always greater than 0 A. Here, the ON pulse width Pon is set so that the switching frequency matches the frequency of the reference clock Cref.

When the output voltage Vout drops and reaches the reference voltage Vref ((a) ofFIG. 6), a high-level pulse voltage Von is generated by the first comparator20((c) ofFIG. 6) and ON pulse Pon is produced from start time point Ta in the switching control signal Ssw by the SR-FF50and the production of the OFF pulse Poff ends at time point Ta ((e) ofFIG. 6). Thereupon, a high level drive signal is generated by the drive circuit13and the switching element11enters an ON state. As a result, the output current IL which flows to the inductor14increases and the output voltage Vout rises ((a) and (b) ofFIG. 6).

When a high-level pulse voltage Von is generated by the first converter20, the transistor33temporarily enters an ON state and the voltage across the terminals of the timer capacitor32is reset, whereupon the timer capacitor32is gradually charged by the fixed current from the fixed current generation circuit31. When the voltage across the terminals of the timer capacitor32reaches the output voltage Vout, a high level pulse voltage Voff is generated by the second comparator40((d) ofFIG. 6), the OFF pulse Poff is produced from time point Tb in the switching control signal Ssw by the SR-FF50, and the production of the ON pulse Pon ends at end time point Tb ((e) ofFIG. 6). Thereupon, the drive signal is changed from a high level to a low level by the drive circuit13and the switching element11enters an OFF state. As a result, the output voltage Vout drops due to the power consumption of the connected load, and the output current IL decreases. The output voltage Vout is stabilized due to the repetition of the above operation.

Further, when the ambient temperature drops, for example, the internal resistance values of the switching element11, diode12, and inductor14or the like, for example, drop and the internal loss is reduced. Thereupon, in order to compensate for a rise in the output voltage Vout, the OFF width of the OFF pulse Poff increases and the ON duty is reduced. Meanwhile, the predetermined ON width of the ON pulse Pon is adjusted by the adjustment section60.

More specifically, because the switching frequency of the switching control signal Ssw is lower than the frequency of the reference clock Cref ((a) and (c) ofFIG. 7), the second counter62ends the count before the first counter61and outputs a high level pulse voltage Vup ((b) ofFIG. 7). However, the output voltage Vdown of the first counter61remains at a low level ((d) ofFIG. 7). As a result, the up/down counter68raises the value of the frequency control signal Sf ((e) ofFIG. 7).

Thereupon, the gm amplifier38draws a current which is proportional to the differential voltage between the frequency control signal Sf and the reference voltage Vref2and increases the charging current of the timer capacitor32. As a result, the time taken for the voltage Vt across the terminals of the timer capacitor32to reach the output voltage Vout grows short and the end time point Tb of the ON pulse Pon is earlier. As a result, the ON width of the ON pulse Pon grows narrow and, because the ON duty is fixed by Vin and Vout, the OFF width of the OFF pulse Poff also narrows and the switching frequency rises. Thus, the adjustment section60controls the switching frequency so that same approaches the frequency of the reference clock Cref and the fluctuations in the switching frequency are therefore reduced.

However, when the ambient temperature rises, for example, the internal resistance values of the switching element11, diode12, and inductor14, and so forth, for example, increase and the internal loss increases. Thereupon, in order to compensate for a drop in the output voltage Vout, the OFF width of the OFF pulse Poff narrows and the ON duty is increased. Meanwhile, the predetermined ON width of the ON pulse Pon is adjusted by the adjustment section60.

More specifically, because the switching frequency of the switching control signal Ssw is higher than the frequency of the reference clock Cref, the first counter61ends the count before the second counter62and outputs a high-level pulse voltage Vdown. However, the output voltage Vup of the second counter62remains at a low level. As a result, the up/down counter68reduces the value of the frequency control signal Sf.

Thereupon, the gm amplifier38outputs a current which is proportional to the differential voltage between the frequency control signal Sf and the reference voltage Vref2and reduces the charging current of the timer capacitor32. As a result, the time taken for the voltage Vt across the terminals of the timer capacitor32to reach the output voltage Vout grows long and the end time point Tb of the ON pulse Pon is delayed. As a result, the ON width of the ON pulse Pon grows increases and, because the ON duty is fixed by Vm and Vout, the OFF width of the OFF pulse Poff also narrows and the switching frequency decreases. Thus, the adjustment section60controls the switching frequency so that same approaches the frequency of the reference clock Cref and the fluctuations in the switching frequency are therefore reduced.

The operation in the discontinuous current mode of the comparator-system DC-DC converter1will be described next. In cases where the load current is relatively small, the comparator-system DC-DC converter1operates in the discontinuous current mode in the period during which the output current is 0 A arises. Here, the adjustment processing to match the switching frequency with the frequency of the reference clock Cref is temporarily stopped and a narrowing of the ON width of the ON pulse is suppressed.

FIG. 8is a timing chart which shows the respective signal waveforms in the discontinuous current mode of the comparator-system DC-DC converter1shown inFIG. 1andFIG. 9is a timing chart which shows the respective signal waveforms of the discontinuous current mode of the reference clock generation section80shown inFIG. 5. Furthermore,FIG. 10is a timing chart which shows the respective signal waveforms of the discontinuous current mode of the adjustment section60shown inFIG. 3.

In the event of a light load with a small load current, the time required to discharge the capacitor15is long and the drop time of the output voltage Vout increases ((a) ofFIG. 8). Hence, the width of the OFF pulse Poff of the switching control signal Ssw increases and the frequency of the switching control signal Ssw drops ((e) ofFIG. 8). Thereupon, in the period of the generation of the OFF pulse Poff, a period P0in which the output current IL is 0 A occurs ((b) ofFIG. 8) and the resonance voltage V11is produced at one end of the inductor14from the time point at which the output current IL is 0 A ((f) ofFIG. 8). The comparator72of the adjustment stoppage section70detects that the resonance voltage V11is greater than the reference voltage Vref3and outputs a high-level pulse voltage. Thereupon, a high-level adjustment stoppage signal Sstop is output by the D-FF74((g) ofFIG. 8). The generation of a high-level adjustment stoppage signal Sstop by the D-FF74continues until the start time point Ta of the generation of the ON pulse Pon in the switching control signal Ssw which is input to the reset terminal ((e) ofFIG. 8). Thus, a high-level adjustment stoppage signal Sstop is generated by the adjustment stoppage section70in the period P0in which the output current IL is 0 A.

When a high-level adjustment stoppage signal Sstop is generated ((a) ofFIG. 9), the output voltage of the EXOR82of the reference clock generation section80is inverted and the level of a non-inverting output voltage Q of the D-FF83is latched and the level of the non-inverting output voltage Q of the D-FF84is latched ((d) ofFIG. 9) in the period P0in which the output current IL is 0 A ((c) ofFIG. 9). As a result, the level of the reference clock Cref output by the D-FF85is latched in the period P0in which the output current IL is 0 A.

Thus, when the adjustment stoppage signal Sstop is generated ((b) ofFIG. 10) by the adjustment stoppage section70in accordance with the resonance voltage V11at one end of the inductor14((a) ofFIG. 10), the voltage level of the reference clock Cref is latched ((c) ofFIG. 10). As a result, the frequency of the reference clock Cref drops so as to approach the frequency of the switching control signal Ssw ((c) and (e) ofFIG. 10), the count of the second counter62is delayed. Thereupon, the generation of the high-level pulse voltage Vup is suppressed ((d) ofFIG. 10), and an increase in the frequency control signal Sf is suppressed ((g) ofFIG. 10). As a result, even when the frequency of the switching control signal Ssw drops in the discontinuous current mode, the adjustment of the ON width of the ON pulse Pon is suppressed and a narrowing of the ON width of the ON pulse Pon is suppressed.

FIG. 11shows the switching frequency characteristic with respect to the load current of the comparator-system DC-DC converter1shown inFIG. 1.FIG. 11shows the simulation effect of a comparator-system DC-DC converter of a comparative example in addition to the simulation effect of the comparator-system DC-DC converter1of this embodiment.

Curve A shows the simulation effect of the comparator-system DC-DC converter1of this embodiment. Curve B shows the simulation effect of a comparator-system asynchronous rectification DC-DC converter of a Comparative Example 1 which is a constitution not comprising the adjustment section60and adjustment stoppage section70of the comparator-system DC-DC converter1of this embodiment. Curve C shows the simulation effect of a comparator-system synchronous rectification DC-DC converter of a Comparative Example 2 which is a constitution not comprising the adjustment stoppage section70of the comparator-system DC-DC converter1of this embodiment.

As indicated by curve C, the comparator-system asynchronous rectification DC-DC converter of Comparative Example 1 produces an increase in the switching frequency as the load current increases in the continuous current mode. Hence, due to fluctuations in the switching frequency in the continuous current mode which is the actual usage state, the ripple of the output voltage fluctuates and there is the possibility of a downstream circuit such as the PU operating erroneously. There is also the possibility of ENI countermeasures extending over a wide bandwidth being required.

Furthermore, as indicated by curve C, the comparator-system synchronous rectification DC-DC converter of Comparative Example 2 sometimes over-reduces the ON width of the switching waveform in an attempt to keep the switching frequency constant when the load current decreases in the discontinuous current mode. Irrespective of whether the load current is small, the loss increases as a result of switching with a narrow ON width being performed at a high frequency. Hence, the power consumed cannot be adequately reduced.

In contrast, as indicated by curve A, the switching frequency can be kept constant in the continuous current mode as a result of providing the adjustment section60and adjustment stoppage section70as per the comparator-system DC-DC converter1of this embodiment, and an excessive narrowing of the ON width can be suppressed by stopping the processing to adjust the switching frequency in the discontinuous current mode.

Thus, according to the comparator-system DC-DC converter1of the first embodiment, in the continuous current mode, the fluctuations in the switching frequency which arise due to fluctuations in the conversion loss due to fluctuations in the ambient temperature, fluctuations in the I/O voltages, and fluctuations in the output current can be reduced without impairing the response characteristic with respect to a sudden increase in the load current. As a result, in the continuous current mode, fluctuations in the output voltage ripple can be reduced and erroneous operation of a downstream circuit such as the PU can be prevented. Furthermore, EMI countermeasures extending over a wide bandwidth are not required, and EMI countermeasures can be carried out inexpensively and in a straightforward manner.

However, in discontinuous current mode, processing to adjust the ON width of the ON pulse can be stopped in the period in which the output current is 0 A. Accordingly, the fact that the ON width of the ON pulse narrows greatly can be suppressed in discontinuous current mode and disturbance of the switching waveform can be reduced. In addition, there is no need to employ costly circuit elements with a high-speed characteristic. In addition, the loss caused by performing switching with a narrow ON width at a high frequency can be suppressed irrespective of whether the load current is small. Hence, the power consumption can be reduced.

Second Embodiment

FIG. 12is a circuit diagram which shows a comparator-system DC-DC converter according to the second embodiment of the present invention. The comparator-system DC-DC converter1A shown inFIG. 12differs from the comparator-system DC-DC converter1in the first embodiment in that the comparator-system DC-DC converter1A comprises a voltage conversion section100A and a control unit200A in place of the voltage conversion section100and control unit200of the comparator-system DC-DC converter1.

The voltage conversion section100A further comprises a resistance element (current detection resistance element)16which is serially connected to the inductor14in the voltage conversion section100. The remaining constitution of the voltage conversion section100A is the same as that of the voltage conversion section100.

The control unit200A differs from the control unit200in that the control unit200A comprises an adjustment stoppage section70A instead of the adjustment stoppage section70of the control unit200. The remaining constitution of the control unit200A is the same as that of the control unit200. In this embodiment, the timer section30, adjustment section60, adjustment stoppage section70A, and reference clock generation section80function as frequency control means25A.

FIG. 13is a circuit diagram which shows an adjustment stoppage section70A shown inFIG. 12. The adjustment stoppage section70A shown inFIG. 13differs from the adjustment stoppage section70in that the adjustment stoppage section70A does not comprise the detected voltage division circuit71and Zener diode73of the adjustment stoppage section70.

The comparator72detects the voltage across the terminals of the resistance element16in order to detect the output current IL. More specifically, the positive input terminal of the comparator72is connected to a node between the inductor14and resistance element16and the negative input terminal is connected to a node between the resistance element16and output terminal Vout. In other words, a voltage V111which is a high voltage is input in continuous current mode to the negative input terminal of the comparator72and a voltage V112which is a low voltage is input to the positive input terminal. The comparator72detects that the voltage V111and voltage V112are to be equal or mutually inverted and outputs a high-level pulse voltage. Thus, the comparator72functions as a current detection section which detects a state where the output current IL is 0 A or a state where the output current is going to be 0 A by detecting the voltage difference between voltage V111and voltage V112. The detection of the state where the output current IL is going to be 0 A can be implemented by applying a predetermined forward-bias voltage to the positive input terminal of the comparator72, for example.

The same benefits as those of the first embodiment can also be obtained by the comparator-system DC-DC converter1A of the second embodiment.

Third Embodiment

FIG. 14is a circuit diagram which shows a comparator-system DC-DC converter according to the third embodiment of the present invention. The comparator-system DC-DC converter1B shown inFIG. 14differs from the comparator-system DC-DC converter1in the first embodiment in that the comparator-system DC-DC converter1B comprises a control unit200B in place of the control unit200of the comparator-system DC-DC converter1. The remaining constitution of the comparator-system DC-DC converter1B is the same as that of the comparator-system DC-DC converter1.

The control unit200B comprises an adjustment section60B in place of the adjustment section60in the control unit200. Furthermore, the control unit200B differs from the control unit200in that the control unit200B uses an externally generated reference clock Cref and does not comprise the reference clock generation section80of the control unit200. The remaining constitution of the control unit200B is the same as that of the control unit200. In this embodiment, the timer section30, adjustment section60B, and adjustment stoppage section70B function as frequency control means25B.

FIG. 15is a circuit diagram which shows the adjustment section60B which is shown inFIG. 14. The adjustment section60B which is shown inFIG. 15differs from the adjustment section60in that the adjustment stoppage signal Sstop which is output by the adjustment stoppage section70is input to each of the control terminals of the first counter61and second counter62. The remaining constitution of the adjustment section60B is the same as that of the adjustment section60.

FIG. 16is a timing chart which shows the respective signal waveforms in the discontinuous current mode of the adjustment section60B which is shown inFIG. 15.

When a high-level adjustment stoppage signal Sstop is input to the first counter61and second counter62((b) ofFIG. 16), the first counter61and second counter62stop counting (time point Ts of (c) ofFIG. 16). In other words, the first counter61and second counter62reset the count values, that is, the output voltages.

As a result, when the output current reaches 0 A in the discontinuous current mode, because the count values are reset prior to the first counter61and second counter62ending the count up to a predetermined value, a high-level pulse voltage Vup is not produced ((d) ofFIG. 16) and the frequency control signal Sf does not rise ((g) ofFIG. 16). As a result, even when the frequency of the switching control signal Ssw drops in the discontinuous current mode, the adjustment of the ON width of the ON pulse Pon is stopped.

Thus, the comparator-system DC-DC converter1B of the third embodiment also allows the same benefits as those of the first embodiment to be obtained.

Fourth Embodiment

FIG. 17is a circuit diagram which shows a comparator-system DC-DC converter according to the fourth embodiment of the present invention. The comparator-system DC-DC converter1C which is shown inFIG. 17differs from the comparator-system DC-DC converter1B in the third embodiment in that the comparator-system DC-DC converter1C comprises a control unit200C in place of the control unit200B of the comparator-system DC-DC converter1B. The remaining constitution of the comparator-system DC-DC converter1C is the same as that of the comparator-system DC-DC converter1B.

The control unit200C differs from the control unit200B in that the control unit200C comprises an adjustment section60C and an adjustment stoppage section70C in place of the adjustment section60B and adjustment stoppage section70of the control unit200B. The remaining constitution of the control unit200C is the same as that of the control unit200B. In this embodiment, the timer section30, adjustment section60C, and adjustment stoppage section70C function as frequency control means25C.

FIG. 18is a circuit diagram which shows the adjustment stoppage section70C which is shown inFIG. 17. The adjustment stoppage section70C which is shown inFIG. 18differs from the adjustment stoppage section70in the third embodiment in that the stoppage section70C further comprises a delay reset signal generation section75. The remaining constitution of the adjustment stoppage section70C is the same as that of the adjustment stoppage section70.

The adjustment stoppage section70C comprises a delay circuit75awhich delays the phase of the switching control signal Ssw, a NOT circuit75bwhich inverts the switching control signal Ssw, and an AND circuit75cthe two input terminals of which are connected to a delay circuit75aand a NOT circuit75b. The adjustment stoppage section70C generates a high-level pulse voltage at the end time point of the ON pulse of the switching control signal Ssw and supplies same to the reset terminal of the D-FF74.

FIG. 19is a circuit diagram which shows an adjustment section60C which is shown inFIG. 17. The adjustment section60C which is shown inFIG. 19differs from the adjustment section60in that the adjustment section60C further comprises a multiplexer69. The remaining constitution of the adjustment section60C is the same as that of the adjustment section60.

One input terminal of the multiplexer69is connected to the output terminal of the up/down counter68and a fixed value is input to the other input terminal. The adjustment stoppage signal Sstop is input to the control terminal of the multiplexer69. The multiplexer69selects the output signal of the up/down counter68when the adjustment stoppage signal. Sstop is a low-level signal and outputs the output signal as the frequency control signal Sf. The multiplexer69selects a fixed value when the adjustment stoppage signal Sstop is a high-level signal and outputs the fixed value as the frequency control signal Sf.

The adjustment stoppage signal Sstop is also input to the control terminal of the up/down counter68.

FIG. 20is a timing chart which shows the respective signal waveforms of the discontinuous current mode of the adjustment stoppage section70C which is shown inFIG. 18. As shown inFIG. 20, when the resonance voltage V11at one end of the inductor14is detected by the comparator72((a) ofFIG. 20), the generation of a high-level adjustment stoppage signal Sstop is started by the D-FF74. Thereafter, a high-level pulse voltage Sr is generated by a delay reset circuit at the end time point Tb of the ON pulse Pon of the switching control signal Ssw ((b) ofFIG. 20) and the generation of the high-level adjustment stoppage signal Sstop is terminated by the D-FF74((c) ofFIG. 20).

When a high-level adjustment stoppage signal Sstop is generated, the up/down counter68stops counting and the multiplexer69changes from the output signal of the up/down counter68to a fixed value and outputs same as the frequency control signal Sf.

Thus, the comparator-system DC-DC converter1C of the fourth embodiment makes it possible to stop the adjustment processing of the ON width of the ON pulse until the ON pulse production period in addition to periods in which the output current is equal to or less than 0 A. As a result, the count of the up/down counter68can be delayed and the adjustment of the ON width of the ON pulse can be suppressed. Therefore, the comparator-system DC-DC converter1C of the fourth embodiment also makes it possible to obtain the same benefits as the third embodiment.

The present invention is not limited to the above embodiments and can be modified in a variety of ways.

Although this embodiment takes the example of a digital circuit which generates a digital frequency control signal Sf as the adjustment section60, an analog circuit which generates an analog frequency control signal Sf is also applicable.FIG. 21is a circuit diagram which shows the adjustment section according to a modified example 1. The adjustment section60X of the modified example 1 shown inFIG. 21comprises a NOR circuit63in place of the up/down counter68in the adjustment section60, a NAND circuit64, two inverters65and66, a charge pump circuit67, and an adjustment capacitor68X. The remaining constitution of the adjustment section60X is the same as that of the adjustment section60.

One input terminal of the NOR circuit63is connected to the output terminal of the first counter61via the inverter65and the other input terminal is connected to the output terminal of the second counter62. The output terminal of the NOR circuit63is connected to the charge pump circuit67.

One input terminal of the NAND circuit64is connected to the output terminal of the second counter62and the other input terminal is connected to the output terminal of the first counter61via the inverter66. The output terminal of the NAND circuit64is connected to the charge pump circuit67.

The charge pump circuit67is constituted by a transistor67aconsisting of an n-type MOSFET, a transistor67bconsisting of a p-type MOSFET, and two fixed current sources67cand67d. The source of the transistor67ais connected to the GND5via the fixed current source67cand the drain of the transistor67ais connected to the drain of the transistor67b. The source of the transistor67bhas an input voltage Vin input thereto via the fixed current source67d. A pulse voltage Vdown which is output by the NOR circuit63and the pulse voltage Vup which is output by the NAND circuit64are input to the respective gates of the transistors67aand67b. The adjustment capacitor68X is connected between the drain of the transistors67aand67band GND5.

In the adjustment section60X, in cases where the frequency of the switching control signal Ssw is lower than the frequency of the reference clock Cref, the first counter61ends the count before the second counter62and generates an output voltage at a high level, and the NAND circuit64outputs a low level pulse voltage Vup. Hence, the capacitor68X is charged by the charge pump circuit67and the level of the frequency control signal Sf rises. However, in cases where the frequency of the switching control signal Ssw is higher than the frequency of the reference clock Cref, the second counter62ends the count before the first counter61and generates an output voltage at a high level, and the NOR circuit63outputs a high-level pulse voltage Vdown. Hence, the capacitor68X is discharged by the charge pump circuit67and the level of the frequency control signal Sf drops.

According to Modified example 1, input voltage Vin is input to the source of the transistor67bvia the fixed current source67d. However, in the case of a power source which comprises a predetermined potential difference from the GND5and which is capable of supplying the output current which is required for the fixed current sources67cand67d, there are no restrictions on the input voltage Vin of the input terminal2.

In addition, a circuit which employs a phase comparator is also applicable to the adjustment section60.FIG. 22is a circuit diagram which shows the adjustment section according to Modified example 2. The adjustment section60Y of Modified example 2 shown inFIG. 22comprises a phase comparator61Y in place of the first and second counters61and62respectively, the NOR circuit63, the NAND circuit64, and the two inverters65and66in the adjustment section60X. The remaining constitution of the adjustment section60Y is the same as that of the adjustment section60X.

The switching control signal Ssw is input to one input terminal of the phase comparator61Y while the reference clock Cref is input to the other input terminal. The phase comparator61Y compares the phase of the switching control signal Ssw with the phase of the reference clock Cref and generates the output voltages Vdown and Vup which have values which correspond with the phase difference between the Ssw and Cref indicated by the comparison result. The phase comparator61Y supplies the output voltage Vdown to the gate of the transistor67aof the charge pump circuit67and supplies the output voltage Vup to the gate of the transistor67bof the charge pump circuit67.

In the adjustment section60Y, in cases where the frequency of the switching control signal Ssw is lower than the frequency of the reference clock Cref, the phase comparator61Y outputs a low-level pulse voltage Vup and the capacitor68X is charged by the charge pump circuit67and the level of the frequency control signal Sf rises. However, in cases where the frequency of the switching control signal Ssw is higher than the frequency of the reference clock Cref, the phase comparator61Y outputs the high-level pulse voltage Vdown and, therefore, the capacitor68X is discharged by the charge pump circuit67and the level of the frequency control signal Sf drops.

Furthermore, this embodiment illustrates an output current detection method which detects the period in which the output current is equal to or less than 0 A by means of a resonance voltage at one end of the inductor14and an output current detection method which detects a state where the output current is equal to or less than 0 A or going to be 0 A by means of the voltage across the two terminals of the resistance element16which is serially connected to the inductor14. However, the output current detection method is not limited to this embodiment. The output current detection method shown inFIG. 23is also applicable, for example.FIG. 23shows the current detection method according to a modified example. As shown inFIG. 23, the serial circuit between the resistance element (current detection resistance element)17and the capacitor (current detection capacitor)18is connected in parallel to the inductor14and the time point at which the output current IL is going to become 0 A or OV may be detected by detecting the time point at which the voltage across the terminals of the capacitor18is 0V or going to be 0V.

In addition, although this embodiment illustrates a method which stops the clock division circuits82,83,84, and85of the reference clock generation section80as the method for stopping the adjustment of the predetermined ON width, the reference clock generation circuit itself may also be stopped.FIG. 24is a circuit diagram which shows the reference clock generation section according to a modified example. The reference clock generation section80X of the modified example shown inFIG. 24is a ring oscillator which comprises a triangular wave generation circuit86, a comparator87, a D-FF circuit88, and a one-shot pulse signal generation circuit89.FIG. 25is a respective part signal waveform for the reference clock generation section according to the modified example.

The triangular wave generation circuit86comprises a fixed current source86awhich is serially connected in order between the terminal to which the input voltage Vin is input and the terminal connected to the GND5, a switch element86b, and a capacitor86c. The triangular wave generation circuit86further comprises a switch element86dwhich is connected in parallel to the capacitor86c. The switch element86benters an ON state when the adjustment stoppage signal Sstop is a low level signal. However, the switch element86denters an ON state when a high-level pulse voltage is output by the one-shot pulse signal generation circuit89. Thus, the triangular wave generation circuit86generates a saw-wave-shaped triangular wave voltage when the adjustment stoppage signal Sstop is a low level signal ((a), (b), and (d) ofFIG. 25). The comparator87compares the triangular wave voltage with reference voltage Vref4from the triangular wave generation circuit86and generates a low-level output voltage when the triangular wave voltage is smaller than the reference voltage Vref4and generates a high-level pulse voltage when the triangular wave voltage is equal to or more than the reference voltage Vref4((b) and (c) ofFIG. 25). The input terminal of the D-FF circuit88is connected to the inverting output terminal and the output voltage from the comparator87is input to the clock terminal. The D-FF circuit88inverts the level of the reference clock Cref in accordance with the pulse voltage from the comparator87. The one-shot pulse signal generation circuit89outputs a pulse voltage when the level of the reference clock Cref is inverted.

Here, when the adjustment stoppage signal Sstop is a high level signal, the switch element86benters an OFF state, the charging of the capacitor is stopped, and the level of the triangular wave voltage from the triangular wave generation circuit86is latched. As a result, the level of the reference clock Cref is latched. Thus, the reference clock generation section80X of the modified example is able to stop the generation of the reference clock Cref by stopping the reference clock generation circuit itself in accordance with the adjustment stoppage signal Sstop.

In addition, in this embodiment, the timer section30controls the ON time width Pon but may also control the OFF time width Poff. In this case, the drive circuit13generates a drive signal such that the switching element11enters an OFF state when the switching control signal Ssw is at a high level. In addition, in this case, the adjustment section60adjusts the OFF time width Poff instead of the ON time width Pon.

Furthermore, the method for changing the ON width of the ON pulse Pon of the switching control signal Sw is not limited to that of this embodiment. Rather, a variety of method forms may be considered. For example, the charging current of the timer capacitor32may be changed by changing the para number of the transistor35bof the voltage follower35, the charging current of the timer capacitor32may be changed by changing the para number of the transistors37aand37bof the current mirror circuit37, or the charging current of the timer capacitor32may be changed by changing the division ratio of the input voltage division circuit34.

Furthermore, although the frequency of the reference clock Cref of the adjustment section60is the same as the frequency of the switching control signal Ssw in this embodiment, the ratio between the frequency of the reference clock Cref and the frequency of the switching control signal Ssw may also be N:M (where M and N are natural numbers). Here, the adjustment section60adjusts the predetermined ON width of the ON pulse of the switching control signal so that the ratio between the count value of the switching control signal Ssw and the count value of the reference clock Cref is M:N. In particular, the frequency of the reference clock Cref is preferably lower than the frequency of the switching control signal Ssw. The current consumption can accordingly be reduced.

Furthermore, although the first counter61counts only the ON pulses of the switching control signal Ssw in this embodiment, the first counter61may also count at least either one of the ON pulses and OFF pulses of the switching control signal Ssw.

In addition, although the output voltage Vout is input to the negative input terminal of the second comparator in this embodiment, a reference voltage may also be input to the negative input terminal of the second comparator.

Furthermore, although a switching-type voltage conversion section which employs a diode rectification system is illustrated as the voltage conversion section in this embodiment, the voltage conversion section may also be a synchronous rectification system switching-type voltage conversion section which employs a switching element instead of the diode12. In this case, the adjustment stoppage section stops the switching element instead of the diode12on the basis of an inverted detection signal.

Although an n-type MOSFET is employed as the switching element11of the voltage conversion section100in this embodiment, a p-type MOSFET may also be employed. In addition, various transistors such as a FET or a bipolar transistor can be applied to the switching element or transistor of this embodiment.