Unified AES-SMS4—Camellia symmetric key block cipher acceleration

Disclosed embodiments relate to a unified Advanced Encryption Standard (AES), SMS4, and Camellia (CML) accelerator. In one example, a processor includes fetch circuitry to fetch a cipher instruction specifying an opcode, a datum, and a key, the opcode to specify one of three cryptographic modes and an operation, decode circuitry to decode the fetched cipher instruction, and execution circuitry to respond to the decoded cipher instruction by performing the operation using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to implement an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers by calculating and then combining two fourth-order polynomials.

FIELD OF THE INVENTION

The field of invention relates generally to computer processor architecture, and, more specifically, to a unified Advanced Encryption Standard (AES), SMS4, andCamellia(CML) accelerator.

BACKGROUND

Symmetric key block ciphers constitute a critical component of all content protection, authentication and key management protocols. Although AES (Advanced Encryption Standard) is a standardized and often de facto standard for most security applications, equivalent geo-specific ciphers like standardized SMS4 (China) and standardizedCamellia(Japan) are increasingly used in IPsec, WAPI, TLS, etc. following OSCCA, ISO/IEC, and NESSIE recommendations, and mandates for usage in different geos.

AES is a symmetric key block cipher encryption standard adopted by the U.S. government starting in 2001. It is widely used across the software ecosystem to protect network traffic, personal data, and corporate IT infrastructure.

SMS4 (now SM4) is a symmetric key block cipher used in the Chinese National Standard for Wireless LAN WAPI (Wired Authentication and Privacy Infrastructure). SMS4 was a proposed cipher to be used in I8 802.11i standard but has so far been rejected by the ISO.

Camellia(CML) is a symmetric key block cipher approved for use by the ISO/IEC, the European Union's NESSIE project and the Japanese CRYPTREC project.Camelliais part of the Transport Layer Security (TLS) cryptographic protocol designed to provide communications security over a computer network such as the Internet.

AES, SMS4 and CML encrypt 128b data with 128b secret key with 10/32/18 rounds of computation, wherein each round involves a different substitute box (Sbox), as well as rotate, scaling, and mixing steps necessitating separate hardware implementations or firmware code.

DETAILED DESCRIPTION OF THE EMBODIMENTS

References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a feature, structure, or characteristic, but every embodiment may not necessarily include the feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a feature, structure, or characteristic is described about an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic about other embodiments if explicitly described.

Disclosed embodiments describe a unified engine that leverages polynomial isomorphism to accelerate AES (Advanced Encryption Standard), SMS4, andCamellia(CML) in a common optimal GF(24)2datapath with in-line key expansion. Disclosed embodiments avoid using lookup tables, which can add cost and area. The disclosed unified AES/SMS4/CML encrypt/decrypt hardware accelerator is expected to provide a significant area improvement over using separate AES/SMS4/CML datapath implementations.

Although AES, SMS4, and CML ciphers may perform similar substitution box (Sbox) operations, they use different Galois field (GF) GF(28) reduction polynomials.

A substitution box (Sbox) is a basic component of symmetric key algorithms which performs substitution. In general, an Sbox may take some number of input bits, m, and transform them into some number of output bits, n, where n is not necessarily equal to m. In mathematics, the finite field with pn elements is denoted GF(pn) and is called the Galois Field (where p is a prime number). The Galois Field is sometimes referred to herein as the unified field or the unified Galois Field.

AES may use the GF(28) reduction polynomial x8+x4+x3+x+1, while SMS4 may use the GF(28) reduction polynomial x8+x7+x6+x5+x4+x2+1, and CML may use X2+x+1, x2+x+9. The choice of reduction polynomial differentiates the logic for Galois Field multiplications and inverse computations, thus requiring the use of separate circuits for AES and SMS4 hardware implementations. Implementing separate dedicated hardware accelerators for AES and SMS4 is clumsy and inefficient and may result in significant area and power overhead.

The embodiments described herein reduce circuit area by avoiding separate hardware for each of AES, SMS, and CML. Instead, disclosed embodiments address AES/SMS/CML encryption and decryption using a single hybrid hardware accelerator that can be reconfigured to support AES, SMS4, or CML encryption and/or decryption. AES, SMS4, and CML ciphers consist of three main components: (1) the addition of a round key to intermediate round data; (2) substitute box (Sbox) operations; and (3) mixing at byte boundaries using XOR or mixed column operations. Of these, the Sbox may include the most area and performance critical operations.

In one embodiment, a 128-bit encrypt/decrypt datapath configured for AES includes 8 Sbox modules to be used for rounding computation and key expansion at a rate of 2.5 clock cycles per round. In other embodiments, the 128-bit encrypt/decrypt datapath can be configured for SMS4, in which case four of the 8 Sbox modules are used for round computation and the other four of the 8 Sbox modules are used for key expansion, to achieve an overall rate of one round per cycle. As to CML, round computation and key expansion each require 8 Sboxes, so an auxiliary key is computed in the initial 4 cycles, followed by 20 cycles of round computation, yielding a throughput of 20 rounds over 25 cycles, or 1.2 clock cycles per round, for 24 cycles.

The hybrid encrypt/decrypt hardware accelerator described herein may result in significant area improvement over separate AES/SMS4 datapath implementations. The area savings may be achieved by using common Galois field inversion circuits, which are expected to require much less circuit area than separate AES/SMS4 Sbox implementations. To avoid the need to have separate implementations, disclosed embodiments select ground and extension field polynomials that work for AES, SMS4, and CML computations. The hybrid AES-SMS4-CML hardware accelerator described herein may be implemented in any logic device, including, but not limited to, a processor, a processor core, a network processor, a mobile processor, a field-programmable gate array (FPGA) and a web server.

Disclosed embodiments include several aspects, features, and advantages, as described and illustrated at least with respect toFIGS. 1-8, including, but not limited to:Cost and energy efficiency is improved by using a shared unified AES-SMS4-CML datapath with in-line key expansion organized around 8 Sboxes 100% for AES and SMS4, and 92% forCamellia. Camelliaencryption involves 18 cycles of round processing plus 4 cycles of key expansion, all of which use 100% of Sboxes. However, theCamelliacipher block performs 2 special operations after round 6 and round 12, for which 2 extra cycles are spent. These 2 special operations do not use Sboxes, so CML utilization is 92%, corresponding to Sboxes being used in 22 of the 24 cycles.In addition to Sbox optimization, other compute intensive operations like AES mix-columns is implemented with multiply-less circuits to match critical path delay across all cipher modes for higher performance.A 2.5 cycle/AES-round architecture leverages the presence ofCamellia's auxiliary key register to hold pre-computed subsequent round keys and to thus eliminate stalls between successive rounds.AES, SMS4 andCamelliarequire a different number of Sboxes at various stages of round compute and key expansion. Embodiments disclosed herein are expected to optimize the area efficiency of implementation for accelerating AES, SMS4, Camelliaciphers, and, instead of implementing block ciphers with separate cipher accelerators, sharing a single, unified accelerator among the multiple block ciphers, thereby saving area.

FIG. 1is a block diagram illustrating processing components for executing a cipher instruction, according to some embodiments. As illustrated, storage101stores cipher instruction(s)103to be executed. As described further below, in some embodiments, computing system100is an SIMD processor to concurrently process multiple elements of packed-data vectors.

In operation, the cipher instruction(s)103is fetched from storage101by fetch circuitry105. The fetched cipher instruction107is decoded by decode circuitry109. The cipher instruction format, which is further illustrated and described with respect toFIGS. 9, 10A-B, and11A-D, has fields (not shown here) is to specify an opcode, a cryptographic mode, an operation, a datum, and a key. The opcode is to describe which block cipher mode to apply, and whether to encrypt or decrypt. Decode circuitry109decodes the fetched cipher instruction107into one or more operations. In some embodiments, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry119). The decode circuitry109also decodes instruction suffixes and prefixes (if used).

In some embodiments, register renaming, register allocation, and/or scheduling circuit113provides functionality for one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), 2) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded cipher instruction111for execution on execution circuitry119out of an instruction pool (e.g., using a reservation station in some embodiments). Register renaming, register allocation, and/or scheduling circuit113is optional, as indicated by its dashed border, insofar as it may occur at a different time in the pipeline, or not at all.

Computing system100also includes cipher accelerator117, which is to perform encryption and decryption according to an Advanced Encryption Standard (AES), SMS4, orCamellia(CML), depending on which mode is selected by the opcode. Cipher accelerator117is illustrated as being incorporated in execution circuitry119, but in some embodiments, the cipher accelerator117is external to the execution circuitry. Cipher accelerator117is further illustrated and described below with respect toFIGS. 2A-8.

Execution circuitry119is to perform the decoded instruction. When the opcode of the decoded instruction calls for a block cipher to be performed according to one of the modes disclosed herein, execution circuitry119configures the cipher accelerator117to perform the cryptograph, be it encoding or decoding. In some embodiments, as further described and illustrated with respect toFIG. 8, cipher accelerator117performs one round (default value), or multiple rounds (as specified by an instruction operand) of the specified algorithm. Execution circuitry119is further described and illustrated below, at least with respect toFIGS. 2A-8, 13A-B and14A-B.

Registers (register file) and/or memory115store data as operands of decoded cipher instruction111to be operated on by execution circuitry119. Exemplary register types include writemask registers, packed data registers, general purpose registers, and floating point registers, as further described and illustrated below, at least with respect toFIG. 12.

In some embodiments, write back circuit121commits the result of the execution of the decoded cipher instruction111. Execution circuitry119and system100are further illustrated and described with respect toFIGS. 2A-8, 13A-B,14A-B, and15-19.

FIG. 2Ais a block diagram illustrating a cipher accelerator, according to some embodiments. Cipher accelerator200supports AES/SMS4/CML round compute and key expansion, which require 16/4/8 and 4/4/8 Sboxes, respectively. As shown, cipher accelerator200includes 128-bit plain/cipher text register202, two, key registers204and205(the latter intended for use by CML, but taken advantage of by AES, as described below), cipher constant generator units206,208, and210, Inverse mix column unit211(for use by AES), multiplexer214to select input data to Sboxes216(which may include FL and FL-1 functions for use byCamellia), mode control unit212to generate control signals for multiplexer214, additional operation units218,220, and222for use by AES, SMS4, andCamellia, and mixed columns unit223for use by AES. Cipher accelerator200further includes multiplexers224and226to select datapath output to be written either into the input data registers202or key registers204and205.

Cipher accelerator200, as illustrated, improves processor cipher throughput and Sbox efficiency. Bing organized around 8 hybrid Sboxes216(and two additional FL and FL-1 functions for use byCamellia), cipher accelerator200maximizes Sbox utilization, achieving 100% utilization in AES and SMS4 modes, and 92% utilization in CM mode, as described above.

In operation, cipher accelerator200, operating in one of three modes, AES, SMS4, and CML, consumes 128-bit plain/cipher text202(d15:0) (consumes plain text when encrypting/consumes cipher text when decrypting) and key (KL15:0) from two 128b registers,202and204, and returns processed data in shift-row/permute-word/permute-DWord order in AES/SMS4/CML modes, respectively.

When operating in CML mode, the CML block cipher running the CML algorithm requires simultaneous access to the base key stored in base key register204and the expanded key stored in an additional auxiliary register (KA15:0)205(register205is opportunistically used for AES key pre-compute to store a key for use in a subsequent clock cycle (explained later in more detail)).

In operation, operand conversion and all GF(24)2computations are confined to within the Sbox and mix-columns/inv. mix-columns units. This eliminates the need for any mapping logic in key expansion datapath, since data is always returned to the pipeline register in its respective native GF(28) domain. This approach also simplifies round constant generation circuit that can be implemented using simple 1b rotate and 8b adder circuits.

FIG. 2Billustrates is a unified round constant generator circuit, according to some embodiments. As shown, unified round constant generator circuit250includes 32-bit constant252, seed registers α1-α4254,256,258, and260, 1-bit rotators262and264, multiplexer266, and four 8-bit adders268to generate 32-bit result270in one of CML, AES, or SMS4 modes. The disclosed embodiments and claims herein are not intended to be limited to any particular constant generator circuit; multiple different such circuits can be used with disclosed embodiments, without limitation.

FIG. 3illustrates round compute and key expansion timing of AES/SMS/CML flows, according to some embodiments. In operation, the cipher accelerator200completes 10 AES encryption rounds with interleaved key expansion in 25 cycles. In SMS4 mode, the 32 SMS4 rounds are computed concurrently with key expansion resulting in 32 cycle latency.

In CML mode, auxiliary key computation spans initial 4 cycles followed by 20 cycles of round compute for 24 cycle latency As shown, in CML mode, the first four clock cycles (cycle0to3) are used for key expansion. Subsequently, cycle4to23(with cycles5-23not shown) are used to compute rounds. Although theCamelliastandard specifies 18 rounds, disclosed embodiment processCamelliain 20 cycles because there is a special FL and FL-1 function after round 6 and round 12 which require 2 extra cycles. So, in CML mode, disclosed embodiments spend four clock cycles for key expansion, two clock cycles for the special FL and FL-1 function, and 18 cycles for round computation. Since disclosed embodiments process 18 rounds in 24 cycles, the CML throughput is approximately 1.3 cycles per round.

In some embodiments, the cipher accelerator200, when operating in CML mode, is to separate the two intra-Feistel CML shuffle functions217(FL/FL-1) from regular Sbox operation, which improves critical-path delay.

AES key expansion requires only 4 out of 8 Sboxes. Hence, explicitly computing next round key in a clock cycle would result in 50% Sbox utilization. In some embodiments, instead of restricting round and key computation to separate cycles, the cipher accelerator expands keys for the next 2 rounds concurrently with cipher processing. As shown, for example, the AES flow rounds based on 16 bytes, and generates key expansion based on 8 bytes, during clocks0-2. The keys generated based on those eight bytes are to serve as keys in both the current round and the next round. The 128b data is processed in 2 cycles in 64b chunks by making use of key that was pre-computed in the previous round. CML auxiliary register stores the extra pre-computed key enabling 2.5 cycle/AES round and 100% Sbox utilization.

Polynomial Optimization

FIG. 4Aillustrates optimal reduction polynomials for an AES-SMS4-CamelliaHybrid Sbox, according to some embodiments. AES and SMS4 standards are defined in GF (28) by AES GF (2)8polynomial x8+x4+x3+x+1, labeled as402, and SMS4 GF (2)8polynomial x8+x7+x6+x5+x4+x2+1, labeled as404. The CML polynomial is defined asCamelliaGF(24)2polynomial x4+x+1, x2+x+9, labeled as406(The comma means 8 bit data is represented in a new format of two 4 bit quantities, which simplifies and reduces the cost and area of the required circuitry because two 4 bit calculations are performed and later combined to form an 80 bit result, rather than to calculate the result in 8-bit format. In operation, the unified cipher datapath is to calculate an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers, the eighth-order polynomial being implemented by calculating. As a cost-reducing optimization, the eighth-order polynomial is implanted by calculating and then combining two fourth-order polynomials. In some embodiments the conversion from 4-bit values to an 8-bit result occurs statically.

Every choice of the unified field results in unique datapath hardware implementation. A two-step optimization approach exhaustively evaluates the isomorphic space, using a parameterized register transfer level (RTL) model of the hardware implementation that provides an estimate of the circuit area for implementing the chosen polynomials of the hybrid Sbox and mapped affine transforms (FIG. 4B). The first step evaluates 23,040 designs for an AES-SMS4 Sbox, yielding x4+x+1, x2+x+8 for optimal mapping providing 1.8× area savings. The second step evaluates 128 possible ways to translate CML to this optimal field through AES and SMS4 polynomials. Though this optimization concept has been explained in the context of minimizing area, it can also be applied to select the Sbox to maximize performance.

FIG. 4Bis a graph illustrating simulated circuit area for various hybrid substitution box (Sbox) polynomial/root combinations, according to some embodiments. The mapping matrix for conversion from GF(28) to GF(24)2and vice versa may be obtained by representing the root Δ of a reduction polynomial f(x) in terms of the roots of a ground-field polynomial g(x) and extension-field polynomial p(x). In one embodiment, the ground-field polynomial and the extension-field polynomial are optimized to be common computations by the Sbox for the first, second, and third block ciphers402,404, and406in the composite field GF(24)2.

Graph425shows the area spread for polynomial exploration across tens of thousands of combinations representing the AES-SMS4-CML isomorphic space, According to some embodiments, the AES-SMS4-CML is exhaustively searched to identify an optimal composite field, GF(24)2composite field that leads to the smallest unified Sbox and smallest cipher accelerator. For ease of illustration, only a small subset of the polynomials is plotted. In one exemplary implementation, an Sbox area of 72·μm2was obtained for the polynomials x4+x+1 (ground field) and x2+x+1 (extension field), labeled at point430of the graph. This is a significant area improvement compared to separate Sbox implementation for the three block ciphers. In various other embodiments, other ground field and extension field polynomials may be used. The actual area of the optimized Sbox may vary, without limitation.

FIG. 4Cis a block flow diagram illustrating a process of selecting an optimal polynomial for a unified Sbox, according to some embodiments. As shown, process450at operation452is to select Polynomial 1: X4+a3X3+a2X2+a1X+a0and at operation454is to select Polynomial 2: X2+αX+β. At454, irreducible instances of Polynomial 1 are selected, and at458, irreducible instances of Polynomial 2 are selected. At460, a GF (24)2Isomorphic field is selected. At462, 2880 MA/MA−1are computed. At464, for each MA, 8 MS/MS−1are computed. At466, Optimal MAand MSare selected from 23,040 choices. At468, 128 MC/MC−1are computed. At470, the optimal MCis selected, and the process ends.

FIG. 5is a block diagram illustrating a Hybrid GF (24)2substitution box (Sbox) with mapped affine and shared inversion circuits, according to some embodiments. As shown, hybrid Sbox510includes an inversion circuit514, a blown-up version of which is shown at502, and eight mapping circuits512,514,518,520,522,524,526, and526, an exemplary, blown-up version of circuit520being shown at550.

AES/SMS4/CML Sbox implementations involve affine transformations and GF(28) inversion that account for a majority of total Sbox area. However, standard specific reduction-polynomial-based inverse computation reduces the potential for logic reuse in conventional designs. In contrast, the hybrid Sbox leverages GF(28) to GF(24)2isomorphism to translate operands from AES/SMS4/CML specific fields to a unique composite field enabling inversion sharing (seeFIG. 4A). Fusion of mapping (MA,MS,MC) and inverse-mapping (MA−1,MS−1,MC−1) matrices for field conversion with existing AES/SMS4/CML affine transforms yield new mapped transforms with similar logic complexity without impacting critical path delay, while reducing Sbox area by replacing8bmultiplication and inversion units with 4b circuits.

Hybrid Sbox510includes an inverse operation514, a blown-up version of which is illustrated at502. As shown, 8-bit inverse operation circuit502includes adders503A and503CX, multipliers503B,503D, and503E, squaring circuit504, and 4-bit inversion operation circuit506. Squaring circuit504is to take the square of 4 bits of the 8-bit input and add eight. 4-bit inverse operation circuit506is smaller and less complex than an 8-bit inverse operation would be. In some embodiments, 4-bit inverse operation is implemented with a lookup table (LUT) and in other embodiments it is calculated with circuitry. The hybrid inverse operation circuit502is much easier to implement and requires less circuit are than would an 8-bit inverter. As can be seen, inverse operation circuit502is to break an input from an 8-bit domain into two 4-bit domains. By translating input operands from their original 8-bit format into two 4-bit operands, making them much cheaper to process. To compute the inverse, you only need to compute with a 4 bit number. After the relatively simple, 4-bit multiplications504and506, two 4-bit outputs are generated and are combined together to form an 8-bit output.

Hybrid Sbox510also includes eight mapping circuits512,514,518,520,522,524,526, and526, an exemplary, blown-up version of which is shown at550. As shown, mapping circuit550is to multiply input X by A, and added by C. Hybrid Sbox510, it should be noted, outputs both So and 2×S0, which will allow the AES cipher block to avoid using a multiplier to perform scaling, as is described further below.

FIG. 6is an Advanced Encryption Standard (AES) multiply-less Mix-Columns circuit, according to some embodiments. According to some disclosed embodiments, a multiplication operation is removed from the AES data flow. Without the optimization, AES data paths perform mix-columns operations by scaling Sbox output bytes with (1,2,2,3). Such scaling circuits require 8b multiplication followed by reduction, which may comprise a significant penalty.

Instead, since SMS4 and CML do not include a multiplication in their flows, disclosed embodiments eliminate the multiplication operation required for performing a complex scaling factors (B,D,E,9). In contrast to conventional serial Sbox followed by mix-columns processing, the unified datapath computes Sbox outputs and their corresponding scaled outputs (×2) concurrently using scaled affine matrices, as illustrated inFIG. 6.

With reference toFIGS. 2 and 5, the Sboxes included in the disclosed cipher accelerator each provide an Sbox output (1×) and a scaled Sbox output (2×), which in some embodiments are added to produce the required scaled output (×3). This eliminates multiplication from the AES mix-columns critical path and balances the critical path delay across all three cipher modes. For inv. mix-columns, input bytes undergo affine scaling that concurrently multiples them with appropriate factors alongside GF(28) to GF(24)2translation prior to Sbox operation (FIG. 4A). The absence of explicit multiplication in AES mix-columns/inv. mix-columns step improves datapath delay.

FIG. 7is a block diagram illustrating a P function for use in performing aCamelliaalgorithm, according to some embodiments. Separating the two intra-Feistel CML shuffle functions (FL/FL−1) from regular Sbox operation, and parallel execution of AES inverse-mix-columns/mix columns with SMS4-Mixing/CML-P (see, e.g.,FIG. 2) steps further improves critical-path delay.

FIG. 8is a block flow diagram illustrating a processor executing a cipher instruction, according to some embodiments. As shown, flow800begins at802, where a computing apparatus, such as a processor, is to fetch, using fetch circuitry, a cipher instruction specifying a datum, a key, and an opcode to specify one of three modes and an operation. In disclosed embodiments, the three modes are AES, SMS4, and CML. At804, the computing apparatus is to decode, using decode circuitry, the fetched cipher instruction. At806, the computing apparatus is to respond to the decoded cipher instruction by using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to calculate an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers, the eighth-order polynomial being implemented by calculating and then combining two fourth-order polynomials. In some embodiments, at808, the processor is to write back execution results and retire the cipher instruction. Operation808is optional, as indicated by its dashed borders, insofar as it may occur at a different time, or not at all.

FIG. 9is a format of a cipher instruction, according to some embodiments. As shown, cipher instruction900includes opcode902(ASC/SM4/CML-ENC/DEC*), and fields to specify source1906(datum) and source2908(key). Cipher instruction900further includes optional fields to specify a number of rounds910([1],10,12,14, 18,24, and, 32), and key length912, in terms of a number of bits. In some embodiments, cipher instruction900also specifies destination904. When destination904is not included, the processor is to write a result of the operation to source1906. As indicated by their dashed borders, destination904, data format910, and key length912are optional, insofar as they may be omitted, in which case source1906serves as the destination, a default number of rounds (1) and a default key length (128), are used. Opcode902is shown as including an asterisk to indicate that it may optionally include additional prefixes or suffixes to specify instruction behaviors. If cipher instruction900does not specify any of the optional parameters, predetermined default values are applied as needed. The format of cipher instruction900is further illustrated and described with respect toFIGS. 10A-B,11A-D.

Instruction Sets

Exemplary Instruction Formats

Generic Vector Friendly Instruction Format

FIGS. 10A-10Bare block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to some embodiments of the invention.FIG. 10Ais a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof according to some embodiments of the invention; whileFIG. 10Bis a block diagram illustrating the generic vector friendly instruction format and class B instruction templates thereof according to some embodiments of the invention. Specifically, a generic vector friendly instruction format1000for which are defined class A and class B instruction templates, both of which include no memory access1005instruction templates and memory access1020instruction templates. The term generic in the context of the vector friendly instruction format refers to the instruction format not being tied to any specific instruction set.

The class A instruction templates inFIG. 10Ainclude: 1) within the no memory access1005instruction templates there is shown a no memory access, full round control type operation1010instruction template and a no memory access, data transform type operation1015instruction template; and 2) within the memory access1020instruction templates there is shown a memory access, temporal1025instruction template and a memory access, non-temporal1030instruction template. The class B instruction templates inFIG. 10Binclude: 1) within the no memory access1005instruction templates there is shown a no memory access, write mask control, partial round control type operation1012instruction template and a no memory access, write mask control, vsize type operation1017instruction template; and 2) within the memory access1020instruction templates there is shown a memory access, write mask control1027instruction template.

The generic vector friendly instruction format1000includes the following fields listed below in the order illustrated inFIGS. 10A-10B.

Base operation field1042—its content distinguishes different base operations.

Augmentation operation field1050—its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In some embodiments, this field is divided into a class field1068, an alpha field1052, and a beta field1054. The augmentation operation field1050allows common groups of operations to be performed in a single instruction rather than 2, 3, or 4 instructions.

Scale field1060—its content allows for the scaling of the index field's content for memory address generation (e.g., for address generation that uses 2scale*index+base).

Displacement Field1062A—its content is used as part of memory address generation (e.g., for address generation that uses 2scale*index+base+displacement).

Displacement Factor Field1062B (note that the juxtaposition of displacement field1062A directly over displacement factor field1062B indicates one or the other is used)—its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N)—where N is the number of bytes in the memory access (e.g., for address generation that uses 2scale*index+base+scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field's content is multiplied by the memory operands total size (N) in order to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field1074(described later herein) and the data manipulation field1054C. The displacement field1062A and the displacement factor field1062B are optional in the sense that they are not used for the no memory access1005instruction templates and/or different embodiments may implement only one or none of the two.

Class field1068—its content distinguishes between different classes of instructions. With reference toFIGS. 10A-B, the contents of this field select between class A and class B instructions. InFIGS. 10A-B, rounded corner squares are used to indicate a specific value is present in a field (e.g., class A1068A and class B1068B for the class field1068respectively inFIGS. 10A-B).

Instruction Templates of Class A

In the case of the non-memory access1005instruction templates of class A, the alpha field1052is interpreted as an RS field1052A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round1052A.1and data transform1052A.2are respectively specified for the no memory access, round type operation1010and the no memory access, data transform type operation1015instruction templates), while the beta field1054distinguishes which of the operations of the specified type is to be performed. In the no memory access1005instruction templates, the scale field1060, the displacement field1062A, and the displacement scale filed1062B are not present.

In the no memory access full round control type operation1010instruction template, the beta field1054is interpreted as a round control field1054A, whose content(s) provide static rounding. While in the described embodiments of the invention the round control field1054A includes a suppress all floating point exceptions (SAE) field1056and a round operation control field1058, alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field1058).

SAE field1056—its content distinguishes whether or not to disable the exception event reporting; when the SAE field's1056content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler.

In the no memory access data transform type operation1015instruction template, the beta field1054is interpreted as a data transform field10546, whose content distinguishes which one of a number of data transforms is to be performed (e.g., no data transform, swizzle, broadcast).

In the case of a memory access1020instruction template of class A, the alpha field1052is interpreted as an eviction hint field10526, whose content distinguishes which one of the eviction hints is to be used (inFIG. 10A, temporal10526.1and non-temporal10526.2are respectively specified for the memory access, temporal1025instruction template and the memory access, non-temporal1030instruction template), while the beta field1054is interpreted as a data manipulation field1054C, whose content distinguishes which one of a number of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; up conversion of a source; and down conversion of a destination). The memory access1020instruction templates include the scale field1060, and optionally the displacement field1062A or the displacement scale field10626.

Memory Access Instruction Templates—Temporal

Memory Access Instruction Templates—Non-Temporal

Instruction Templates of Class B

In the case of the instruction templates of class B, the alpha field1052is interpreted as a write mask control (Z) field1052C, whose content distinguishes whether the write masking controlled by the write mask field1070should be a merging or a zeroing.

In the case of the non-memory access1005instruction templates of class B, part of the beta field1054is interpreted as an RL field1057A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round1057A.1and vector length (VSIZE)1057A.2are respectively specified for the no memory access, write mask control, partial round control type operation1012instruction template and the no memory access, write mask control, VSIZE type operation1017instruction template), while the rest of the beta field1054distinguishes which of the operations of the specified type is to be performed. In the no memory access1005instruction templates, the scale field1060, the displacement field1062A, and the displacement scale filed1062B are not present.

In the no memory access, write mask control, partial round control type operation1010instruction template, the rest of the beta field1054is interpreted as a round operation field1059A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler).

Round operation control field1059A—just as round operation control field1058, its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field1059A allows for the changing of the rounding mode on a per instruction basis. In some embodiments where a processor includes a control register for specifying rounding modes, the round operation control field's1050content overrides that register value.

In the no memory access, write mask control, VSIZE type operation1017instruction template, the rest of the beta field1054is interpreted as a vector length field1059B, whose content distinguishes which one of a number of data vector lengths is to be performed on (e.g., 128, 256, or 512 byte).

In the case of a memory access1020instruction template of class B, part of the beta field1054is interpreted as a broadcast field1057B, whose content distinguishes whether or not the broadcast type data manipulation operation is to be performed, while the rest of the beta field1054is interpreted the vector length field1059B. The memory access1020instruction templates include the scale field1060, and optionally the displacement field1062A or the displacement scale field1062B.

With regard to the generic vector friendly instruction format1000, a full opcode field1074is shown including the format field1040, the base operation field1042, and the data element width field1064. While one embodiment is shown where the full opcode field1074includes all of these fields, the full opcode field1074includes less than all of these fields in embodiments that do not support all of them. The full opcode field1074provides the operation code (opcode).

The augmentation operation field1050, the data element width field1064, and the write mask field1070allow these features to be specified on a per instruction basis in the generic vector friendly instruction format.

Exemplary Specific Vector Friendly Instruction Format

FIG. 11Ais a block diagram illustrating an exemplary specific vector friendly instruction format according to some embodiments of the invention.FIG. 11Ashows a specific vector friendly instruction format1100that is specific in the sense that it specifies the location, size, interpretation, and order of the fields, as well as values for some of those fields. The specific vector friendly instruction format1100may be used to extend the x86 instruction set, and thus some of the fields are similar or the same as those used in the existing x86 instruction set and extension thereof (e.g., AVX). This format remains consistent with the prefix encoding field, real opcode byte field, MOD RIM field, SIB field, displacement field, and immediate fields of the existing x86 instruction set with extensions. The fields fromFIG. 10into which the fields fromFIG. 11Amap are illustrated.

It should be understood that, although embodiments of the invention are described with reference to the specific vector friendly instruction format1100in the context of the generic vector friendly instruction format1000for illustrative purposes, the invention is not limited to the specific vector friendly instruction format1100except where claimed. For example, the generic vector friendly instruction format1000contemplates a variety of possible sizes for the various fields, while the specific vector friendly instruction format1100is shown as having fields of specific sizes. By way of specific example, while the data element width field1064is illustrated as a one bit field in the specific vector friendly instruction format1100, the invention is not so limited (that is, the generic vector friendly instruction format1000contemplates other sizes of the data element width field1064).

The generic vector friendly instruction format1000includes the following fields listed below in the order illustrated inFIG. 11A.

Format Field1040(EVEX Byte0, bits [7:0])—the first byte (EVEX Byte0) is the format field1040and it contains 0x62 (the unique value used for distinguishing the vector friendly instruction format in some embodiments).

The second-fourth bytes (EVEX Bytes1-3) include a number of bit fields providing specific capability.

Data element width field1064(EVEX byte2, bit [7]—W)—is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the datatype (either 32-bit data elements or 64-bit data elements).

EVEX.U1068Class field (EVEX byte2, bit [2]-U)—If EVEX.0=0, it indicates class A or EVEX.U0; if EVEX.0=1, it indicates class B or EVEX.U1.

Alpha field1052(EVEX byte3, bit [7]—EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also illustrated with a)—as previously described, this field is context specific.

Real Opcode Field1130(Byte4) is also known as the opcode byte. Part of the opcode is specified in this field.

MOD R/M Field1140(Byte5) includes MOD field1142, Reg field1144, and R/M field1146. As previously described, the MOD field's1142content distinguishes between memory access and non-memory access operations. The role of Reg field1144can be summarized to two situations: encoding either the destination register operand or a source register operand or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field1146may include the following: encoding the instruction operand that references a memory address or encoding either the destination register operand or a source register operand.

Scale, Index, Base (SIB) Byte (Byte6)—As previously described, the scale field's1050content is used for memory address generation. SIB.xxx1154and SIB.bbb1156—the contents of these fields have been previously referred to with regard to the register indexes Xxxx and Bbbb.

Displacement field1062A (Bytes7-10)—when MOD field1142contains 10, bytes7-10are the displacement field1062A, and it works the same as the legacy 32-bit displacement (disp32) and works at byte granularity.

Full Opcode Field

FIG. 11Bis a block diagram illustrating the fields of the specific vector friendly instruction format that make up the full opcode field, according to some embodiments. Specifically, the full opcode field1074includes the format field1040, the base operation field1042, and the data element width (W) field1064. The base operation field1042includes the prefix encoding field1125, the opcode map field1115, and the real opcode field1130.

Register Index Field

FIG. 11Cis a block diagram illustrating the fields of the specific vector friendly instruction format that make up the register index field, according to some embodiments. Specifically, the register index field1044includes the REX field1105, the REX′ field1110, the MODR/M.reg field1144, the MODR/M.r/m field1146, the VVVV field1120, xxx field1154, and the bbb field1156.

Augmentation Operation Field

FIG. 11Dis a block diagram illustrating the fields of the specific vector friendly instruction format that make up the augmentation operation field according to some embodiments. When the class (U) field1068contains 0, it signifies EVEX.U0 (class A1068A); when it contains 1, it signifies EVEX.U1 (class B1068B). When U=0 and the MOD field1142contains 11 (signifying a no memory access operation), the alpha field1052(EVEX byte3, bit [7]—EH) is interpreted as the rs field1052A. When the rs field1052A contains a 1 (round1052A.1), the beta field1054(EVEX byte3, bits [6:4]—SSS) is interpreted as the round control field1054A. The round control field1054A includes a one bit SAE field1056and a two bit round operation field1058. When the rs field1052A contains a 0 (data transform1052A.2), the beta field1054(EVEX byte3, bits [6:4]—SSS) is interpreted as a three bit data transform field1054B. When U=0 and the MOD field1142contains 00, 01, or 10 (signifying a memory access operation), the alpha field1052(EVEX byte3, bit [7]—EH) is interpreted as the eviction hint (EH) field1052B and the beta field1054(EVEX byte3, bits [6:4]—SSS) is interpreted as a three bit data manipulation field1054C.

When U=1, the alpha field1052(EVEX byte3, bit [7]—EH) is interpreted as the write mask control (Z) field1052C. When U=1 and the MOD field1142contains 11 (signifying a no memory access operation), part of the beta field1054(EVEX byte3, bit [4]—S0) is interpreted as the RL field1057A; when it contains a 1 (round1057A.1) the rest of the beta field1054(EVEX byte3, bit [6-5]—S2-1) is interpreted as the round operation field1059A, while when the RL field1057A contains a 0 (VSIZE1057.A2) the rest of the beta field1054(EVEX byte3, bit [6-5]—S2-1) is interpreted as the vector length field1059B (EVEX byte3, bit [6-5]—L1-0). When U=1 and the MOD field1142contains 00, 01, or 10 (signifying a memory access operation), the beta field1054(EVEX byte3, bits [6:4]—SSS) is interpreted as the vector length field1059B (EVEX byte3, bit [6-5]—L1-0) and the broadcast field1057B (EVEX byte3, bit [4]—B).

Exemplary Register Architecture

FIG. 12is a block diagram of a register architecture according to some embodiments. In the embodiment illustrated, there are 32 vector registers1210that are 512 bits wide; these registers are referenced as zmm0 through zmm31. The lower order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-16. The lower order 128 bits of the lower 16 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15. The specific vector friendly instruction format1100operates on these overlaid register file as illustrated in the below tables.

In other words, the vector length field1059B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length; and instructions templates without the vector length field1059B operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of the specific vector friendly instruction format1100operate on packed or scalar single/double-precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in an zmm/ymm/xmm register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment.

Write mask registers1215—in the embodiment illustrated, there are 8 write mask registers (k0through k7), each 64 bits in size. In an alternate embodiment, the write mask registers1215are 16 bits in size. As previously described, in some embodiments, the vector mask register k0cannot be used as a write mask; when the encoding that would normally indicate k0is used for a write mask, it selects a hardwired write mask of 0xffff, effectively disabling write masking for that instruction.

Alternative embodiments may use wider or narrower registers. Additionally, alternative embodiments may use more, less, or different register files and registers.

Exemplary Core Architectures

In-Order and Out-of-Order Core Block Diagram

InFIG. 13A, a processor pipeline1300includes a fetch stage1302, a length decode stage1304, a decode stage1306, an allocation stage1308, a renaming stage1310, a scheduling (also known as a dispatch or issue) stage1312, a register read/memory read stage1314, an execute stage1316, a write back/memory write stage1318, an exception handling stage1322, and a commit stage1324.

FIG. 13Bshows processor core1390including a front end unit1330coupled to an execution engine unit1350, and both are coupled to a memory unit1370. The core1390may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core1390may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit1330includes a branch prediction unit1332coupled to an instruction cache unit1334, which is coupled to an instruction translation lookaside buffer (TLB)1336, which is coupled to an instruction fetch unit1338, which is coupled to a decode unit1340. The decode unit1340(or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit1340may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core1390includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit1340or otherwise within the front end unit1330). The decode unit1340is coupled to a rename/allocator unit1352in the execution engine unit1350.

The execution engine unit1350includes the rename/allocator unit1352coupled to a retirement unit1354and a set of one or more scheduler unit(s)1356. The scheduler unit(s)1356represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)1356is coupled to the physical register file(s) unit(s)1358. Each of the physical register file(s) units1358represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit1358comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s)1358is overlapped by the retirement unit1354to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit1354and the physical register file(s) unit(s)1358are coupled to the execution cluster(s)1360. The execution cluster(s)1360includes a set of one or more execution units1362and a set of one or more memory access units1364. The execution units1362may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)1356, physical register file(s) unit(s)1358, and execution cluster(s)1360are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)1364). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units1364is coupled to the memory unit1370, which includes a data TLB unit1372coupled to a data cache unit1374coupled to a level 2 (L2) cache unit1376. In one exemplary embodiment, the memory access units1364may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit1372in the memory unit1370. The instruction cache unit1334is further coupled to a level 2 (L2) cache unit1376in the memory unit1370. The L2 cache unit1376is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline1300as follows: 1) the instruction fetch1338performs the fetch and length decoding stages1302and1304; 2) the decode unit1340performs the decode stage1306; 3) the rename/allocator unit1352performs the allocation stage1308and renaming stage1310; 4) the scheduler unit(s)1356performs the schedule stage1312; 5) the physical register file(s) unit(s)1358and the memory unit1370perform the register read/memory read stage1314; the execution cluster1360perform the execute stage1316; 6) the memory unit1370and the physical register file(s) unit(s)1358perform the write back/memory write stage1318; 7) various units may be involved in the exception handling stage1322; and 8) the retirement unit1354and the physical register file(s) unit(s)1358perform the commit stage1324.

Specific Exemplary in-Order Core Architecture

FIG. 14Ais a block diagram of a single processor core, along with its connection to the on-die interconnect network and with its local subset of the Level 2 (L2) cache, according to some embodiments of the invention. In one embodiment, an instruction decoder1400supports the x86 instruction set with a packed data instruction set extension. An L1 cache1406allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit1408and a vector unit1410use separate register sets (respectively, scalar registers1412and vector registers1414) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache1406, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

FIG. 14Bis an expanded view of part of the processor core inFIG. 14Aaccording to some embodiments of the invention.FIG. 14Bincludes an L1 data cache1406A part of the L1 cache1404, as well as more detail regarding the vector unit1410and the vector registers1414. Specifically, the vector unit1410is a 16-wide vector processing unit (VPU) (see the 16-wide ALU1428), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit1420, numeric conversion with numeric convert units1422A-B, and replication with replication unit1424on the memory input. Write mask registers1426allow predicating resulting vector writes.

FIG. 15is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to some embodiments of the invention. The solid lined boxes inFIG. 15illustrate a processor1500with a single core1502A, a system agent1510, a set of one or more bus controller units1516, while the optional addition of the dashed lined boxes illustrates an alternative processor1500with multiple cores1502A-N, a set of one or more integrated memory controller unit(s)1514in the system agent unit1510, and special purpose logic1508.

Thus, different implementations of the processor1500may include: 1) a CPU with the special purpose logic1508being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores1502A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores1502A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores1502A-N being a large number of general purpose in-order cores. Thus, the processor1500may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor1500may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units1506, and external memory (not shown) coupled to the set of integrated memory controller units1514. The set of shared cache units1506may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit1512interconnects the integrated graphics logic1508(integrated graphics logic1508is an example of and is also referred to herein as special purpose logic), the set of shared cache units1506, and the system agent unit1510/integrated memory controller unit(s)1514, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units1506and cores1502-A-N.

In some embodiments, one or more of the cores1502A-N are capable of multithreading. The system agent1510includes those components coordinating and operating cores1502A-N. The system agent unit1510may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores1502A-N and the integrated graphics logic1508. The display unit is for driving one or more externally connected displays.

Exemplary Computer Architectures

Referring now toFIG. 16, shown is a block diagram of a system1600in accordance with one embodiment of the present invention. The system1600may include one or more processors1610,1615, which are coupled to a controller hub1620. In one embodiment the controller hub1620includes a graphics memory controller hub (GMCH)1690and an Input/Output Hub (IOH)1650(which may be on separate chips); the GMCH1690includes memory and graphics controllers to which are coupled memory1640and a coprocessor1645; the IOH1650couples input/output (I/O) devices1660to the GMCH1690. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory1640and the coprocessor1645are coupled directly to the processor1610, and the controller hub1620in a single chip with the IOH1650.

The optional nature of additional processors1615is denoted inFIG. 16with broken lines. Each processor1610,1615may include one or more of the processing cores described herein and may be some version of the processor1500.

The memory1640may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub1620communicates with the processor(s)1610,1615via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection1695.

In one embodiment, the coprocessor1645is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub1620may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources1610,1615in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor1610executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor1610recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor1645. Accordingly, the processor1610issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor1645. Coprocessor(s)1645accept and execute the received coprocessor instructions.

Referring now toFIG. 17, shown is a block diagram of a first more specific exemplary system1700in accordance with an embodiment of the present invention. As shown inFIG. 17, multiprocessor system1700is a point-to-point interconnect system, and includes a first processor1770and a second processor1780coupled via a point-to-point interconnect1750. Each of processors1770and1780may be some version of the processor1500. In some embodiments, processors1770and1780are respectively processors1610and1615, while coprocessor1738is coprocessor1645. In another embodiment, processors1770and1780are respectively processor1610coprocessor1645.

Processors1770and1780are shown including integrated memory controller (IMC) units1772and1782, respectively. Processor1770also includes as part of its bus controller units point-to-point (P-P) interfaces1776and1778; similarly, second processor1780includes P-P interfaces1786and1788. Processors1770,1780may exchange information via a point-to-point (P-P) interface1750using P-P interface circuits1778,1788. As shown inFIG. 17, IMCs1772and1782couple the processors to respective memories, namely a memory1732and a memory1734, which may be portions of main memory locally attached to the respective processors.

Processors1770,1780may each exchange information with a chipset1790via individual P-P interfaces1752,1754using point to point interface circuits1776,1794,1786,1798. Chipset1790may optionally exchange information with the coprocessor1738via a high-performance interface1792. In one embodiment, the coprocessor1738is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

Chipset1790may be coupled to a first bus1716via an interface1796. In one embodiment, first bus1716may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.

As shown inFIG. 17, various I/O devices1714may be coupled to first bus1716, along with a bus bridge1718which couples first bus1716to a second bus1720. In one embodiment, one or more additional processor(s)1715, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus1716. In one embodiment, second bus1720may be a low pin count (LPC) bus. Various devices may be coupled to a second bus1720including, for example, a keyboard and/or mouse1722, communication devices1727and a storage unit1728such as a disk drive or other mass storage device which may include instructions/code and data1730, in one embodiment. Further, an audio I/O1724may be coupled to the second bus1720. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG. 17, a system may implement a multi-drop bus or other such architecture.

Referring now toFIG. 18, shown is a block diagram of a second more specific exemplary system1800in accordance with an embodiment of the present invention. Like elements inFIGS. 17 and 18bear like reference numerals, and certain aspects ofFIG. 17have been omitted fromFIG. 18in order to avoid obscuring other aspects ofFIG. 18.

FIG. 18illustrates that the processors1770,1780may include integrated memory and I/O control logic (“CL”)1772and1782, respectively. Thus, the CL1772,1782include integrated memory controller units and include I/O control logic.FIG. 18illustrates that not only are the memories1732,1734coupled to the CL1772,1782, but also that I/O devices1814are also coupled to the control logic1772,1782. Legacy I/O devices1815are coupled to the chipset1790.

Referring now toFIG. 19, shown is a block diagram of a SoC1900in accordance with an embodiment of the present invention. Similar elements inFIG. 15bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. InFIG. 19, an interconnect unit(s)1902is coupled to: an application processor1910which includes a set of one or more cores1502A-N, which include cache units1504A-N, and shared cache unit(s)1506; a system agent unit1510; a bus controller unit(s)1516; an integrated memory controller unit(s)1514; a set or one or more coprocessors1920which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit1930; a direct memory access (DMA) unit1932; and a display unit1940for coupling to one or more external displays. In one embodiment, the coprocessor(s)1920include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

FIG. 20is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to some embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof.FIG. 20shows a program in a high level language2002may be compiled using an x86 compiler2004to generate x86 binary code2006that may be natively executed by a processor with at least one x86 instruction set core2016. The processor with at least one x86 instruction set core2016represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler2004represents a compiler that is operable to generate x86 binary code2006(e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core2016. Similarly,FIG. 20shows the program in the high level language2002may be compiled using an alternative instruction set compiler2008to generate alternative instruction set binary code2010that may be natively executed by a processor without at least one x86 instruction set core2014(e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif. and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.). The instruction converter2012is used to convert the x86 binary code2006into code that may be natively executed by the processor without an x86 instruction set core2014. This converted code is not likely to be the same as the alternative instruction set binary code2010because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter2012represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code2006.

Further Examples

Example 1 provides an exemplary apparatus comprising: fetch circuitry to fetch a cipher instruction specifying an opcode, a datum, and a key, the opcode to specify one of three cryptographic modes and an operation, decode circuitry to decode the fetched cipher instruction; and execution circuitry, responsive to the decoded cipher instruction, to perform the operation using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to calculate an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers, the eighth-order polynomial being implemented by calculating and then combining two fourth-order polynomials.

Example 2 includes the substance of the exemplary apparatus of Example 1, wherein the execution circuitry comprises a cipher accelerator, wherein the unified cipher datapath comprises eight hybrid Sboxes, and wherein the cipher accelerator further comprises a 128-bit register to hold the specified datum, and two 128-bit registers, one of the two 128-bit registers to be used to hold the specified key, and the other 128-bit register to be used to hold an auxiliary key inCamelliamode, and a next-round key in AES mode.

Example 3 includes the substance of the exemplary apparatus of Example 1, wherein the first cryptographic mode uses an Advanced Encryption Standard (AES) algorithm, wherein the unified cipher datapath comprises eight Sboxes, and wherein the first block cipher is to use the unified cipher datapath to operate at a throughput of 2.5 cycles per round.

Example 4 includes the substance of the exemplary apparatus of Example 1, wherein the second cryptographic mode uses a SMS4 algorithm, wherein the unified cipher datapath comprises eight Sboxes, and wherein the second block cipher is to use four of the eight Sboxes of the unified cipher datapath for round computation, and the other four Sboxes for key expansion, wherein the second block cipher is to use the unified cipher datapath to operate at a throughput of one cycle per round.

Example 5 includes the substance of the exemplary apparatus of Example 1, wherein the third cryptographic mode uses aCamellia(CML) algorithm, wherein the unified cipher datapath comprises eight Sboxes, and wherein the third block cipher is to use the unified cipher datapath to operate at a throughput of 1.3 cycles per round.

Example 6 includes the substance of the exemplary apparatus of Example 1, wherein the execution circuitry comprises a cipher accelerator, wherein the unified cipher datapath comprises eight Sboxes, each of which provides an Sbox output (1×) and a scaled Sbox output (2×), wherein the first, second, and third cryptographic modes use Advanced Encryption Standard (AES), SMS4, andCamellia(CML) algorithms, respectively, and wherein the cipher accelerator attempts to balance a critical path delay across all three cryptographic modes by eliminating multiplication from the AES mode when performing scaling in the first block, and instead adding the Sbox output (1×) and the scaled Sbox output (2×) to generate a required scaled output (3×).

Example 7 includes the substance of the exemplary apparatus of Example 1, wherein the execution circuitry comprises a cipher accelerator, wherein the first, second, and third cryptographic modes use Advanced Encryption Standard (AES), SMS4, andCamellia(CML) algorithms, respectively, and wherein the cipher accelerator is further to enable inversion sharing by translating operands from AES-specific, SMS4-specific, and CML-specific reduction polynomials to a unique, composite field.

Example 8 includes the substance of the exemplary apparatus of Example 1, wherein the execution circuitry comprises a cipher accelerator, wherein the third cryptographic mode uses aCamellia(CML) algorithm, wherein the cipher accelerator is further to include separate circuitry to perform two intra-Feistel CML shuffle functions (FL/FL-1), and wherein the third cipher block is to use the separate circuitry when operating.

Example 9 includes the substance of the exemplary apparatus of Example 1, wherein the opcode is to select the cryptographic mode and to indicate whether to encrypt or decrypt, and wherein the cipher instruction is further to specify a key length and a number of rounds, the key length being one of 128, 192, and 256 bits, and the number of rounds being one of 1, 10, 12, 14, 18, 24, and 32.

Example 10 includes the substance of the exemplary apparatus of Example 1, wherein the apparatus is one of a processor, a processor core, a network processor, a mobile processor, and a web server.

Example 11 provides an exemplary method performed by a computing apparatus, the method comprising: fetching, using fetch circuitry, a cipher instruction specifying a datum, a key, and an opcode to specify one of three cryptographic modes and an operation, decoding, using decode circuitry, the fetched cipher instruction; and responsive to the decoded cipher instruction, performing the specified operation with execution circuitry using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to calculate an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers, the eighth-order polynomial being implemented by calculating and then combining two fourth-order polynomials.

Example 12 includes the substance of the exemplary method of Example 11, wherein the execution circuitry comprises a cipher accelerator, wherein the unified cipher datapath comprises eight hybrid Sboxes, and wherein the cipher accelerator further comprises a 128-bit register to hold the specified datum, and two 128-bit registers, one of the two 128-bit registers to be used to hold the specified key, and the other 128-bit register to be used to hold an auxiliary key inCamelliamode, and a next-round key in AES mode.

Example 13 includes the substance of the exemplary method of Example 11, wherein a first cryptographic mode of the three specified cryptographic modes uses an Advanced Encryption Standard (AES) algorithm, wherein the unified cipher datapath comprises eight Sboxes, and wherein the first block cipher is to use the unified cipher datapath to operate at a throughput of 2.5 cycles per round.

Example 14 includes the substance of the exemplary method of Example 11, wherein a second cryptographic mode of the three specified cryptographic modes uses a SMS4 algorithm, wherein the unified cipher datapath comprises eight Sboxes, and wherein the second block cipher is to use four of the eight Sboxes of the unified cipher datapath for round computation, and the other four Sboxes for key expansion, wherein the second block cipher is to use the unified cipher datapath to operate at a throughput of one cycle per round.

Example 15 includes the substance of the exemplary method of Example 11, wherein a third cryptographic mode of the three specified cryptographic modes uses aCamellia(CML) algorithm, wherein the unified cipher datapath comprises eight Sboxes, and wherein the third block cipher is to use the unified cipher datapath to operate at a throughput of 1.3 cycles per round.

Example 16 includes the substance of the exemplary method of Example 11, wherein the execution circuitry comprises a cipher accelerator, wherein the unified cipher datapath comprises eight Sboxes, each of which provides an Sbox output (1×) and a scaled Sbox output (2×), wherein the first, second, and third cryptographic modes use Advanced Encryption Standard (AES), SMS4, andCamellia(CML) algorithms, respectively, and wherein the cipher accelerator attempts to balance a critical path delay across all three cryptographic modes by eliminating multiplication from the AES mode when performing scaling in the first block, and instead adding the Sbox output (1×) and the scaled Sbox output (2×) to generate a required scaled output (3×).

Example 17 includes the substance of the exemplary method of Example 11, wherein the execution circuitry comprises a cipher accelerator, wherein the first, second, and third cryptographic modes use Advanced Encryption Standard (AES), SMS4, andCamellia(CML) algorithms, respectively, and wherein the cipher accelerator is further to enable inversion sharing by translating operands from AES-specific, SMS4-specific, and CML-specific reduction polynomials to a unique, composite field.

Example 18 includes the substance of the exemplary method of Example 11, wherein the execution circuitry comprises a cipher accelerator, wherein the third cryptographic mode uses aCamellia(CML) algorithm, wherein the cipher accelerator is further to include separate circuitry to perform two intra-Feistel CML shuffle functions (FL/FL-1), and wherein the third cipher block is to use the separate circuitry when operating.

Example 19 includes the substance of the exemplary method of Example 11, wherein the opcode is to select the cryptographic mode and to indicate whether to encrypt or decrypt, and wherein the cipher instruction is further to specify a key length and a number of rounds, the key length being one of 128, 192, and 256 bits, and the number of rounds being one of 1, 10, 12, 14, 18, 24, and 32.

Example 20 includes the substance of the exemplary method of Example 11, wherein the computing apparatus is one of a processor, a processor core, a network processor, a mobile processor, and a web server.

Example 21 provides an exemplary non-transitory machine-readable medium containing instructions, when executed be a processor, to cause the processor to respond to an instruction by: fetching, using fetch circuitry, a cipher instruction specifying a datum, a key, and an opcode to specify one of three cryptographic modes and an operation, decoding, using decode circuitry, the fetched cipher instruction; and responsive to the decoded cipher instruction, performing the specified operation with execution circuitry using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to calculate an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers, the eighth-order polynomial being implemented by calculating and then combining two fourth-order polynomials.

Example 22 includes the substance of the exemplary non-transitory machine-readable medium of Example 21, wherein the execution circuitry comprises a cipher accelerator, wherein the unified cipher datapath comprises eight hybrid Sboxes, and wherein the cipher accelerator further comprises a 128-bit register to hold the specified datum, and two 128-bit registers, one of the two 128-bit registers to be used to hold the specified key, and the other 128-bit register to be used to hold an auxiliary key inCamelliamode, and a next-round key in AES mode.

Example 23 includes the substance of the exemplary non-transitory machine-readable medium of Example 21, wherein a first cryptographic mode of the three specified cryptographic modes uses an Advanced Encryption Standard (AES) algorithm, wherein the unified cipher datapath comprises eight Sboxes, and wherein the first block cipher is to use the unified cipher datapath to operate at a throughput of 2.5 cycles per round.

Example 24 includes the substance of the exemplary non-transitory machine-readable medium of Example 21, wherein a second cryptographic mode of the three specified cryptographic modes uses a SMS4 algorithm, wherein the unified cipher datapath comprises eight Sboxes, and wherein the second block cipher is to use four of the eight Sboxes of the unified cipher datapath for round computation, and the other four Sboxes for key expansion, wherein the second block cipher is to use the unified cipher datapath to operate at a throughput of one cycle per round.

Example 25 includes the substance of the exemplary non-transitory machine-readable medium of Example 21, wherein a third cryptographic mode of the three specified cryptographic modes uses aCamellia(CML) algorithm, wherein the unified cipher datapath comprises eight Sboxes, and wherein the third block cipher is to use the unified cipher datapath to operate at a throughput of 1.3 cycles per round.