A photonic integrated circuit (PIC) is described. This PIC includes an inverse facet mirror on a silicon optical waveguide for optical proximity coupling between two silicon-on-insulator (SOI) chips placed face to face. Accurate mirror facets may be fabricated in etch pits using a silicon micro-machining technique, with wet etching of the silicon <110> facet at an angle of 45° when etched through the <100> surface. Moreover, by filling the etch pit with polycrystalline silicon or another filling material that has an index of refraction similar to silicon (such as a silicon-germanium alloy), a reflecting mirror with an accurate angle can be formed at the end of the silicon optical waveguide using: a metal coating, a dielectric coating, thermal oxidation, or selective silicon dry etching removal of one side of the etch pit to define a cavity.

BACKGROUND

Field

The present disclosure generally relates to the design of photonic integrated circuits (PICs). More specifically, the present disclosure relates to a PIC that includes a surface-normal coupler that couples an optical signal from another PIC.

Related Art

Optical interconnects or links based on silicon photonics have the potential to alleviate inter-chip communication bottlenecks in high-performance computing systems that include a large number of processor chips and memory chips. This is because, relative to electrical interconnects, optical interconnects offer significantly improved: bandwidth, density, power consumption, latency, and range.

Much of the research on silicon photonics has focused on sub-micron silicon-on-insulator (SOI) technologies because they allow both active and passive optical devices to be implemented. Moreover, the use of grating couplers further enables sub-micron silicon-photonic optical links through optical fibers or chip-to-chip direct optical proximity coupling. Using such optical devices, even a multi-chip optical interconnect network with all-to-all full connectivity can be implemented using grating-based surface-normal couplers without any optical waveguide crossing. However, silicon optical waveguides on an SOI platform with a silicon thickness less than 1.5 μm have a different effective index of refraction and group index of refraction for transverse electric (TE) and transverse magnetic (TM) polarization, respectively. Therefore, one of the weaknesses of sub-micron SOI platforms is that most of the optical devices are very polarization-sensitive, which makes it difficult to implement a wavelength-division-multiplexing (WDM) silicon-photonic optical link over fiber.

Alternatively, silicon optical waveguides on a thicker SOI platform (e.g., a silicon layer having a thickness greater than 1.5 μm) can be made with an identical effective index of refraction and group index of refraction for both TE and TM polarizations. Consequently, silicon-photonic optical devices on a thicker SOI platform, e.g., a silicon layer having a thickness of 3 μm, can be polarization-insensitive. Low-loss optical waveguides and other polarization-insensitive WDM optical components for such an SOI platform are available. The recent successful demonstrations of germanium-based high-speed active optical devices on a 3 μm SOI platform, as well as a Franz-Keldysh modulator and a photo-detector, make a thicker SOI platform promising for intra/inter-chip WDM silicon-photonic optical links. However, for a multi-chip application with chip-to-chip interconnects (such as a so-called ‘macrochip’), a compact surface-normal coupler with low loss and broad optical bandwidth is not available for a thicker SOI platform.

In particular, while specially designed grating couplers have been reported for surface-normal coupling for thick SOI platforms with silicon layers having thicknesses of up to 2 μm. However, it is not clear that these grating couplers will be as effective for thicker SOI platforms, such as those with silicon layers having a thickness of 3 μm. Even if the grating couplers work in this regime, the polarization sensitivity of grating couplers may restrict the use of thicker SOI platforms.

For the thicker SOI platforms, it may be possible to utilize a reflecting facet on the optical waveguide for surface-normal coupling. Silicon micro-machining using dry etching of a silicon wafer at an angle can create a reflecting facet at the end of the silicon optical waveguide. When the optical signal in these optical waveguide reaches the reflecting facet etched with a right angle, it may be reflected normal to the surface because of total internal reflection (TIR). While this approach can be implemented as a wafer-scale process, it can be very challenging to create the reflecting facet with good uniformity and repeatability. In principle, laser milling or focused ion beam (FIB) can also be used to create such a reflecting facet on silicon optical waveguides. However, these fabrication techniques are not wafer-scale processes and, thus, are not suitable for low-cost, high-yield volume production.

Hence, what is needed is a surface-normal coupler for use with thicker SOI platforms without the problems described above.

SUMMARY

One embodiment of the present disclosure provides an integrated circuit that includes a substrate, and a buried-oxide layer disposed on the substrate. Moreover, the integrated circuit includes a semiconductor layer, disposed on the buried-oxide layer, having a top surface, where the semiconductor layer includes an etch pit having sides defined by a crystallographic plane of the semiconductor layer, the etch pit extends from the top surface to the buried-oxide layer, and one of the sides includes a mirror facet. Note that the semiconductor layer is included in an optical waveguide that conveys an optical signal. Furthermore, the integrated circuit includes a filling material disposed in the etch pit.

The substrate, the buried-oxide layer and the semiconductor layer may comprise a silicon-on-insulator technology. For example, the semiconductor layer may include silicon.

Moreover, the sides may be at an angle with respect to the top surface. This angle may be associated with the crystallographic plane. For example, the angle may include: 45°, or an angle corresponding to the crystallographic plane and a tilt angle of the substrate during fabrication of the etch pit. In particular, for total internal reflection, the angle may be between 38-52°.

Note that the etch pit may be fabricated using a wet-etching process.

Furthermore, the mirror facet may include: a metal layer disposed on the one of the sides; and/or a dielectric coating disposed on the one of the sides.

Additionally, the integrated circuit may include an oxide layer disposed on the semiconductor layer underneath the mirror facet.

In some embodiments, the semiconductor layer includes: an etch-stop layer disposed under the filling material and above the mirror facet; and a cavity between the mirror facet and a side of the semiconductor layer. For example, the etch-stop layer may include: silicon dioxide and/or silicon nitride.

Note that the filling material may include: polycrystalline silicon, a silicon-germanium alloy, and/or a material having an index of refraction that approximately matches an index of refraction of the semiconductor layer.

Another embodiment provides a system that includes two instances of the integrated circuit having top surfaces that face each other, where these two integrated circuits convey the optical signal between the integrated circuits using surface-normal optical proximity communication.

Another embodiment provides a method for fabricating the integrated circuit that includes the optical waveguide centered on the semiconductor layer in the integrated circuit. During the method, an etch pit is defined in the semiconductor layer disposed on the buried-oxide layer using the wet-etching process, where the etch pit has sides defined by the crystallographic plane of the semiconductor layer, the etch pit extends from the top surface of the semiconductor layer to the buried-oxide layer, and one of the sides of the etch pit includes the mirror facet. Then, a filling material is disposed in the etch pit.

DETAILED DESCRIPTION

Embodiments of a photonic integrated circuit (PIC), a system that includes the PIC, and a method for fabricating the PIC are described. This PIC includes an inverse facet mirror on a silicon optical waveguide for optical proximity coupling between two silicon-on-insulator (SOI) chips placed face to face. Accurate mirror facets may be fabricated in etch pits using a silicon micro-machining technique, for example, by wet etching of the silicon <110> facet at an angle of 45° when etched through the <100> surface. (More generally, the angle may be between 38-52°, which may result in total internal reflection.) Moreover, by filling the etch pit with polycrystalline silicon or another filling material that has an index of refraction similar to silicon (such as a silicon-germanium alloy), a reflecting mirror with an accurate angle can be formed at the end of the silicon optical waveguide using: a metal coating, a dielectric coating, thermal oxidation, or selective silicon dry etching removal of one side of the etch pit to define a cavity.

Using such a compact surface-normal coupler, broadband SOI optical waveguide-to-optical waveguide optical proximity coupling can be achieved with low loss and high density. Moreover, the accurate mirror facet may facilitate an ultra-compact surface-normal coupler. This optical coupling technique may offer good uniformity and repeatability in a wafer-scale process, which may facilitate wafer-scale testing and low-cost, high-yield volume production of the PIC.

We now describe embodiments of the PIC (which is sometimes referred to as a ‘chip’). In this PIC, by lithographically defining accurate openings aligned with a silicon crystallographic plane, an etch pit with an accurate size and facet angles can be fabricated using selective wet etching. When the etch opening on the <100> plane is aligned with the <110> silicon crystallographic plane, etch pits with 45° mirror facets can be obtained with accurate mirror-facet positions. (More generally, the angle may be between 38-52°.) However, direct termination of a silicon optical waveguide using the accurate etch pit mirror facets results in a beam-reflecting direction pointing to the silicon substrate (a so-called ‘negative facet’), which is not ideal for surface-normal coupling. Instead, an inverse mirror facet is typically needed to reflect the optical signal upward (a so-called ‘positive facet’). By filling the etch pit to terminate the silicon optical waveguide, a mirror facet or reflector facet with the desired reflecting angle can be obtained.

FIG. 1presents a block diagram illustrating a side view of a PIC100with an inverse reflecting facet or mirror facet122. This PIC includes substrate110, and a buried-oxide layer112disposed on substrate110. Moreover, PIC100includes a semiconductor layer114, disposed on buried-oxide layer112, having a top surface116, where semiconductor layer114includes an etch pit118having sides defined by a crystallographic plane of semiconductor layer114, etch pit118extends from top surface116to buried-oxide layer112, and one of the sides includes mirror facet122. Note that semiconductor layer114is included in an optical waveguide108that conveys an optical signal. Furthermore, PIC100includes a filling material124disposed in etch pit118, where an index of refraction of filling material124and an index of refraction associated with mirror facet122ensure that the optical signal undergoes total internal reflection from a plane126of buried oxide layer112toward top surface116(i.e., a positive facet). For example, PIC100may include an oxide layer128disposed on semiconductor layer114underneath mirror facet122.

Moreover, the sides may be at an angle130with respect to top surface116. This angle may be associated with the crystallographic plane. For example, angle130may include: 45°, or an angle corresponding to the crystallographic plane and a tilt angle of substrate110during fabrication of etch pit118. In particular, for total internal reflection, the angle may be between 38-52°. Note that etch pit118may be fabricated using a wet-etching process.

Furthermore, filling material124may include: polycrystalline silicon, a silicon-germanium alloy, and/or a material having an index of refraction that approximately matches an index of refraction of semiconductor layer114. The polycrystalline silicon may be deposited at a low temperature and, thus, may be amorphous. Consequently, a chemical mechanical polish may be used to planarize filling material124.

FIG. 2presents a flow diagram illustrating fabrication of the inverse reflecting facet or mirror facet122in PIC100(FIG. 1). In this fabrication process, by opening an etch window on the top <100> of crystallographic plane of semiconductor layer114, etch pit118can be created using a selective wet etch. Etch pit118may have an accurate position defined by the etch window. The facets of etch pit118are automatically terminated at either the <111> or the <110> crystallographic plane of semiconductor layer114(such as silicon) depending on the alignment of the etch window relative to the two crystallographic planes. The facet angle130will be 45° for the <110> facets.

Then, semiconductor layer114is coated with a mask210to cover the entire top surface116except the right-side etch-pit facet. The exposed semiconductor facet can be oxidized using thermal oxidation or using other means to form oxide layer128. After the oxidation, the mask material is removed, and etch pit118is filled with filling material124that has an index of refraction similar to semiconductor layer114(e.g., polycrystalline silicon in the case of a silicon semiconductor layer114). Finally, top surface116is polished.

By replacing a portion of optical waveguide108(FIG. 1) that is etched away with an optical waveguide structure formed by filling material124, a surface-normal coupler is formed for optical waveguide108(FIG. 1) on the left-hand side inFIG. 2by the facet on the right-hand side of etch pit118. Using silicon as an example, because filling material124has a similar index of refraction as the silicon, the optical signal in optical waveguide108(FIG. 1) propagates through the left-hand-side silicon/filling-material interface with little loss. But the right-hand-side etch-pit facet (i.e., mirror facet122inFIG. 1) is a total-internal-reflection mirror with an inverse reflecting facet for the optical signal propagating in optical waveguide108(FIG. 1) because filling material124has a higher index of refraction than the oxidized silicon.

Note that the etch window size can be very small (e.g., less than 10 μm), because it only needs to be big enough to ensure etch pit118terminates at buried-oxide layer112. Moreover, the propagation loss of optical waveguide108(FIG. 1) in filling material124may be negligible, and the position of mirror facet122is lithographically defined, so it can be very accurate. Furthermore, angle130is determined, at least in part, by the crystallographic plane, so it may be accurate, uniform and repeatable, even though oxidation may change angle130slightly because of changes in the material volume from top surface116to buried-oxide layer112.

WhileFIGS. 1 and 2illustrate one approach based on oxidation for fabrication of the mirror facet, in other embodiments different techniques may be used. One of these alternative approaches is shown inFIG. 3, which presents a block diagram illustrating a side view of a PIC300with an inverse reflecting facet or mirror facet310. In this PIC300, semiconductor layer114includes: an etch-stop layer312disposed under filling material124and above mirror facet310; and a cavity314between mirror facet310and a side316of semiconductor layer114. For example, etch-stop layer312may include: silicon dioxide and/or silicon nitride.

FIG. 4presents a flow diagram illustrating fabrication of the inverse reflecting facet or mirror facet310in PIC300(FIG. 3). In this fabrication process, mirror facet310is fabricated by removing one of the etch-pit facets (i.e., side316) using isotropic dry etching. In particular, once etch pit118is formed, a mask410is applied to the right-hand side of etch pit118. Then, filling material124(e.g., polycrystalline silicon) is deposited to completely fill etch pit118.

Next, top surface116is polished, and a mask412(i.e., etch-stop layer312) is deposited to protect semiconductor layer114except for a small area right next to the right-hand side etch-pit facet. Using an isotropic dry etch through the mask opening, the etch-pit facet on the right-hand side can be removed to create cavity314. However, the facet of filling material124will not be affected because it is protected by the etch-stop layer (i.e., mask410). A material with a low index of refraction can be used to fill cavity314, or it can remain unfilled. In this way, an inverse reflecting facet or mirror facet310with accurate angle130(FIG. 3) of 45° (and, more generally, between 38 and 52°) defined solely by the crystallographic plane of semiconductor layer114may be fabricated at the end of optical waveguide108(FIG. 1), which can be used as a surface-normal coupler for optical waveguide108(FIG. 1).

Another alternative approach is shown inFIG. 5, which presents a block diagram illustrating a side view of a PIC500with an inverse reflecting facet or mirror facet510. In this PIC500, mirror facet510may include: a metal or dielectric layer512disposed on one of the sides.

FIG. 6presents a flow diagram illustrating fabrication of the inverse reflecting facet or mirror facet510in PIC500(FIG. 5). In this fabrication process, mirror facet510can be obtained by coating the etch-pit facet with a metal or dielectric layer512. In particular, after etch pit118is fabricated, a metal or dielectric mirror coating is applied on the right-hand side facet of etch pit118. Then, etch pit118is filled with filling material124with an index of refraction similar to that of semiconductor layer114(e.g., polycrystalline silicon). Next, the wafer may be polished to flat. In this way, an inverse reflecting facet or mirror facet510with an accurate angle130of 45° (and, more generally, between 38 and 52°) defined solely by the crystallographic plane may be fabricated at the end of optical waveguide108(FIG. 1), which can be used as a surface-normal coupler for optical waveguide108(FIG. 1).

We now describe the system.FIG. 7presents a block diagram illustrating a side view of a system700that includes two instances of PIC710, such as PIC100(FIG. 1), PIC300(FIG. 3) or PIC500(FIG. 5). In this system, PICs710have top surfaces712that face each other. These PICs710convey optical signal714between PICs710using surface-normal optical proximity communication.

In an exemplary embodiment, semiconductor layer114(FIGS. 1-6) may have a thickness that is greater than 1.5 μm (such as 3 μm). Furthermore, buried-oxide layer112(FIGS. 1-6) may have a thickness between 0.3 and 3 μm (such as 0.8 μm).

Note that system700may include: a VLSI circuit, a switch, a hub, a bridge, a router, a communication system, a storage area network, a data center, a network (such as a local area network), and/or a computer system (such as a multiple-core processor computer system). Furthermore, the computer system may include, but is not limited to: a server (such as a multi-socket, multi-rack server), a laptop computer, a communication device or system, a personal computer, a work station, a mainframe computer, a blade, an enterprise computer, a data center, a portable-computing device, a tablet computer, a supercomputer, a network-attached-storage (NAS) system, a storage-area-network (SAN) system, and/or another electronic computing device. In some embodiments, the computer system may be at one location or may be distributed over multiple, geographically dispersed locations.

Moreover, the preceding embodiments of the PIC and/or the system may include fewer components or additional components. Moreover, the substrates may include: a semiconductor die (such as silicon), a ceramic, an organic material and/or glass.

Although the PICs and the system are illustrated as having a number of discrete items, these embodiments are intended to be functional descriptions of the various features that may be present rather than structural schematics of the embodiments described herein. Consequently, in these embodiments, two or more components may be combined into a single component and/or a position of one or more components may be changed. In addition, functionality in the preceding embodiments may be implemented more in hardware and less in software, or less in hardware and more in software, as is known in the art.

Note that components in the preceding embodiments of the PIC and the system may be fabricated using a wide variety of techniques, as is known to one of skill in the art, including silicon-machining techniques, such as wet etching and dry etching.

We now describe the method.FIG. 8presents a flow diagram illustrating a method800for fabricating a PIC, such as PIC100(FIG. 1), PIC300(FIG. 3) or PIC500(FIG. 5), which includes the optical waveguide centered on the semiconductor layer in the PIC. During this method, an etch pit is defined in the semiconductor layer disposed on a buried-oxide layer using a wet-etching process (operation810), where the etch pit has sides defined by a crystallographic plane of the semiconductor layer, the etch pit extends from a top surface of the semiconductor layer

to the buried-oxide layer, and one of the sides of the etch pit includes a mirror facet. Then, a filling material is disposed in the etch pit (operation812).

In some embodiments of method800, there may be additional or fewer operations. For example, the aforementioned surface-normal coupler can be processed either before or after definition of the optical waveguide in the integrated circuit.

Moreover, the order of the operations may be changed, and/or two or more operations may be combined into a single operation.