Second intercept point (IP2) calibrator and method for calibrating IP2

A second intercept point (IP2) calibrator and a method for calibrating IP2 are disclosed. The IP2 calibrator and the method for calibrating IP2 remove any direct current (DC) offset by comparing a common-mode reference voltage with the common-mode voltage measured between a first output terminal and a second output terminal of a mixer, and calibrates the IP2 of the mixer by comparing the common-mode voltage with a calibration reference voltage. The calibration reference voltage is independent of the common-mode reference voltage and may be a quantized variable voltage generated according to digital control code.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority, under 35 USC §119, of Korean Patent Application No. 2006-116009, filed on Nov. 22, 2006 in the Korean Intellectual Property Office (KIPO), which is incorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the mixer of a direct conversion receiver, and more particularly to a second intercept point (IP2) calibrator that calibrates the IP2 of a direct conversion receiver's mixer and a method of calibrating the IP2.

2. Description of the Related Art

When radio frequency input signals having two or more input frequencies pass through non-linear systems or non-linear circuits, undesired output frequencies that are different from the input frequencies are caused by non-linearity characteristics of the systems or circuits. This phenomenon is referred to as Intermodulation Distortion (IMD). Intermodulation Distortion (IMD) represents distortion caused by “Inter-modulation” (IM) components. The IM components have frequencies corresponding to the sum of the two input frequencies and the difference between the two input frequencies. Thus, when the input signals having two different input frequencies are applied to the non-linear systems or non-linear circuits, the IMD causes interference with modulation and demodulation.

A theoretical point where a linear extension of the second order IMD intersects a linear extension of an input signal is referred to as second intercept point (IP2). The IP2 is an important parameter used to characterize the linearity of a communication system. As a power level of the input signal increases, the power level of the second order IMD also increases, and the point where the power level of the second order IMD intercepts the original power level of the input signal represents the IP2. However, since output power is saturated before the output power reaches theoretical IP2, the real IP2 corresponds to an expected hypothetical output power level where the second order IMD is expected to reach the same amplitude level as the input power level.

A third intercept point (IP3) is significant in the case of communication employing a superheterodyne architecture using an intermediate frequency (IF). A superheterodyne transmitter converts base-band signals into IF signals and converts the IF signals into radio frequency (RF) signals to transmit the RF signals. A superheterodyne receiver converts received RF signals into IF signals and converts the IF signals into base-band signals.

On the other hand, the second intercept point (IP2) is significant in the case of communication employing a direct conversion architecture that does not use IF. A direct conversion transmitter directly converts base-band signals into RF signals to transmit the RF signals. A direct conversion receiver directly converts received RF signals into base-band signals. Because second order IMD occurs at base-band frequencies, the second order IMD causes greater signal distortion than third order IMD. Accordingly, in the direct conversion architecture, there is a need for adjusting the second order IMD to prevent the signal distortion. The linearity of the communication system may increase by achieving high IP2, which reduces the second order IMD.

Generally, a mixer in the direct conversion receiver has an IP2 calibration circuit for adjusting the IP2.

FIG. 7is a circuit diagram of a conventional IP2 calibration circuit.

Referring toFIG. 7, the conventional IP2 calibration circuit includes a mixer10and an IP2 controller20. The mixer10includes a first pair of input terminals2for receiving an RF signal Vrf and a second pair of input terminals4for receiving a local oscillation signal Vlo corresponding to the known carrier frequency of the RF signal Vrf. The mixer10outputs the base-band signal having a frequency equal to the difference between the frequency of the RF signal Vrf and the frequency of the local oscillation signal Vlo. The base-band signal is outputted at a pair of output terminals6.

The IP2 controller20includes load resistors RLP and RLN, and a calibration resistor Rcal. The calibration resistor Rcal is connected in parallel to the load resistor RLP as shown inFIG. 7(or in parallel to RLN, not shown). The calibration resistor Rcal compensates for any mismatch between differential outputs Vop and Von of the mixer10.

A total second order intermodulation (IM2) output voltage is obtained by summing up the IM2 output voltage in common-mode and the IM2 output voltage in differential-mode.

The IM2 output voltage VIM2,cm in common-mode is given by following Expression 1.
VIM2,cm=icm(R+ΔR−Rc)−icm(R−ΔR)=icm(2ΔR−Rc),  [Expression 1]

where Rc denotes a decrease in a resistance value of the load resistor RLP due to the calibration resistor Rcal, and icm denotes a current in common-mode.

The IM2 output voltage VIM2,dm in differential-mode is given by following Expression 2.
VIM2,dm=idm(R+ΔR−Rc)+idm(R−ΔR)=idm(2R−Rc),  [Expression 2]

where Rc denotes the decrease in the resistance value of the load resistor RLP due to the calibration resistor Rcal, and idm denotes a current in the differential-mode.

Therefore, the total IM2 output voltage VIM2 is given by following Expression 3.
VIM2=VIM2,cm+VIM2,dm=Idm(2R−Rc)+icm(2ΔR−Rc)  [Expression 3]

The IP2 is calibrated by adjusting the Rc to reduce the total IM2 output voltage VIM2.

The above-mentioned calibration method has limitations associated with the semiconductor manufacturing process. Since ΔR is in a range of from about 0.1% to 10% of R, Rc is also in a range of from about 0.1% to 10% of R. Additionally, Rcal needs to be ten times to thousand times as large as the resistance of R, thus, when R is tens of KΩ, Rcal needs to be tens of MΩ. Therefore, Rcal is difficult to be implemented in a semiconductor manufacturing process, since a considerably large resistor occupies a large area on a semiconductor substrate. Additionally, the IP2 calibration circuit using a resistive load for IP2 calibration has limitations. For example, a sufficient voltage margin may not be acquired in a structure where a high gain and linearity is required.

For overcoming such limitations, IP2 calibrators using various circuits and methods have been proposed. An IP2 calibration method calibrating a mixer by using a common-mode feedback circuit is disclosed in US Patent Application Publication No. 2006-0145706. An IP2 calibrator using the common-mode feedback circuit may be more easily implemented than the IP2 calibrator inFIG. 1.

However, DC offset may occur when IP2 of the mixer is calibrated by using the common-mode feedback circuit. Further the IP2 characteristic may be degraded when the caused DC offset is removed.

SUMMARY OF THE INVENTION

Some exemplary embodiments of the present invention provide an IP2 calibrator and a method for calibrating IP2 capable of calibrating IP2 of a mixer and removing DC offset. The IP2 calibrator and the method for calibrating IP2 remove any direct current (DC) offset by comparing a common-mode reference voltage with the common-mode voltage measured between a first output terminal and a second output terminal of a mixer, and calibrates the IP2 of the mixer by comparing the common-mode voltage with a calibration reference voltage. The calibration reference voltage is independent of the common-mode reference voltage and may be a multi-level quantized voltage generated according to a digital control code.

In some exemplary embodiments of the present invention, a second intercept point (IP2) calibrator includes a common-mode feedback circuit and an IP2 calibration circuit. The common-mode feedback circuit removes direct current (DC) offset of a mixer by comparing a common-mode reference voltage with the common-mode voltage measured between a first output terminal and a second output terminal of the mixer. The IP2 calibration circuit calibrates IP2 of the mixer by comparing the common-mode voltage with a calibration reference voltage.

In some embodiments, the IP2 calibrator may further include a calibration reference voltage generating circuit that generates the calibration reference voltage based on the common-mode voltage. The calibration reference voltage generating circuit may include a comparator and a feedback loop. The comparator compares the common-mode voltage with the calibration reference voltage. The feedback loop updates the calibration reference voltage according to an output voltage of the comparator. The calibration reference voltage generating circuit may operate in synchronization with a clock signal.

In some embodiments, the feedback loop may include a digital control code generator and a multi-level quantized voltage source. The control code generator generates a digital control code according to (e.g., by sampling) the output voltage of the comparator, and provides the digital control code. The voltage source generates the calibration reference voltage according to the digital control code provided from the control code generator. The control code generator includes a register that stores the generated digital control code.

In some embodiments, the IP2 calibration circuit may include a first feedback circuit and a second feedback circuit. The first feedback circuit changes a first load resistance of the first output terminal by comparing the common-mode voltage with the calibration reference voltage. The second feedback circuit changes a second load resistance of the second output terminal by comparing the common-mode voltage with the calibration reference voltage.

In some exemplary embodiments of the present invention, for calibrating second intercept point (IP2), direct current (DC) offset of a mixer is removed by comparing a common-mode reference voltage with the common-mode voltage measured between a first output terminal and a second output terminal of the mixer. IP2 of the mixer is calibrated by comparing the common-mode voltage with a calibration reference voltage.

In some embodiments, for calibrating IP2 of the mixer, the calibration reference voltage is generated based on the common-mode voltage.

In some embodiments, for generating the calibration reference voltage, the common-mode voltage is compared with the calibration reference voltage. Additionally, the calibration reference voltage may be periodically updated according to a result of the comparison.

In some embodiments, for updating the calibration reference voltage, a digital control code is generated according to the result of the comparison. Additionally, the calibration reference voltage is generated according to the digital control code.

In some embodiments, for calibrating IP2 of the mixer, a load resistance of the first output terminal is changed by comparing the common-mode voltage with the calibration reference voltage. Additionally, a load resistance of the second output terminal is changed by comparing the common-mode voltage with the calibration reference voltage.

Therefore, an IP2 calibration and a removal of a DC offset of a mixer may be efficiently performed by using a common-mode feedback circuit according to an exemplary embodiment of the present invention.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion. The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

FIG. 1is a circuit diagram of a second intercept point (IP2) calibrator100according to an exemplary embodiment of the present invention.

The IP2 calibrator100removes the direct current (DC) offset of a mixer110by comparing a common-mode voltage Vcm with a common-mode reference voltage Vcmref, and calibrates the IP2 of the mixer110by comparing the common-mode voltage with a calibration reference voltage Vcalref.

The IP2 calibrator100includes a common-mode feedback circuit120for removing the DC offset of the mixer110, and a IP2 calibration circuit130for calibrating the IP2 of the mixer110. The common-mode feedback circuit120removes the DC offset of the mixer110by comparing the common-mode voltage Vcm measured between first and second output terminals Voutp and Voutm with the common-mode reference voltage Vcmref. The IP2 calibration circuit130calibrates the IP2 of the mixer110by comparing the common-mode voltage with a calibration reference voltage Vcalref.

The common-mode feedback circuit120includes a current source125, first and second n-type metal oxide semiconductor (NMOS) transistors121and122, first and second p-type metal oxide semiconductor (PMOS) transistors123and124, and first and second common-mode feedback PMOS transistors126and127. The current source125provides a bias current. The first NMOS transistor121has its gate receiving the common-mode voltage Vcm, and its source connected to the current source125. The second NMOS transistor122has its gate receiving the common-mode reference voltage Vcmref, and its source connected to the current source125. The first PMOS transistor123has its gate and its drain commonly connected to the drain of the first NMOS transistor121, and its source connected to a power supply voltage. The second PMOS transistor124that has its gate and its drain commonly connected to the drain of the second NMOS transistor122, and its source connected to the power supply voltage. The first common-mode feedback PMOS transistor126constitutes a current mirror with the second PMOS transistor124. Additionally, the first common-mode feedback PMOS transistor126has its drain connected to the first output terminal Voutp, and its source connected to the power supply voltage. The second common-mode feedback PMOS transistor127constitutes a current mirror with the second PMOS transistor124. Additionally, the second common-mode feedback PMOS transistor127has its drain connected to the second output terminal Voutm, and its source connected to the power supply voltage.

Hereinafter, an operation of the common-mode feedback circuit120will be described.

The current flowing through the first NMOS transistor121is greater than the current flowing through the second NMOS transistor122when the common-mode voltage Vcm is greater than the common-mode reference voltage Vcmref. In this case, the voltage at the gate of the second PMOS transistor124rises, and voltages at the gates of the first and second common-mode feedback PMOS transistors126and127also rise. The source-drain resistance through each of the first and second common-mode feedback PMOS transistors126and127increases when the voltages at the gates of the first and second common-mode feedback PMOS transistors126and127rise. Thus, voltages at the first and second output terminals Voutp and Voutm decrease. The common mode voltage Vcm is an average value measured between the first and second output terminals Voutp and Voutm, and thus the common-mode voltage Vcm decreases.

On the other hand, when the common-mode voltage Vcm is less than the common-mode reference voltage Vcmref, the current flowing through the first NMOS transistor121is less than the current flowing through the second NMOS transistor122. In this case, the voltage at the gate of the second PMOS transistor124falls, and the voltages at the gates of the first and second common-mode feedback PMOS transistors126and127also fall. The source-drain resistance through each of the first and second common-mode feedback PMOS transistors126and127decrease when the voltages at the gates of the first and second common-mode feedback PMOS transistors126and127fall. Accordingly, the voltages at the first and second output terminals Voutp and Voutm increase. The common mode voltage Vcm is the average value measured between the first and second output terminals Voutp and Voutm, and thus the common-mode voltage Vcm increases.

As such, the common-mode voltage Vcm may follow the common-mode reference voltage Vcmref by the common-mode feedback circuit120. Although the common-mode voltage Vcm rises or falls when the DC offset occurs, the common-mode feedback circuit120removes the DC offset by feedback operation.

The IP2 calibration circuit130calibrates the IP2 of the mixer by changing the load resistances of the first and second output terminals Voutp and Voutm by comparing the common-mode voltage Vcm with the calibration reference voltage Vcalref. The IP2 calibration circuit130includes two feedback circuits for performing the calibration. The operation of the IP2 calibration circuit130will be described in greater detail below with reference toFIG. 3.

The IP2 calibrator100may further include a reference voltage generator140that generates the calibration reference voltage Vcalref. The reference voltage generator140receives the common-mode voltage Vcm, and the reference voltage generator140updates the calibration reference voltage Vcalref synchronously with a clock signal CLK. The operation of the reference voltage generator140will now be described in greater detail with reference toFIG. 2.

FIG. 2is a circuit diagram of a reference voltage generator140in the IP2 calibrator ofFIG. 1.

The reference voltage generator140receives the common-mode voltage Vcm and generates therefrom the calibration reference voltage Vcalref. The reference voltage generator140compares the common-mode voltage Vcm with the calibration reference voltage Vcalref, and updates the calibration reference voltage Vcalref according to the result of the comparison.

The reference voltage generator140includes a comparator210that compares the common-mode voltage Vcm with the calibration reference voltage Vcalref, and a feedback loop220that updates the calibration reference voltage Vcalref according to an output of the comparator210.

The reference voltage generator140maintains its reset state while the mixer is turned OFF, and updates the calibration reference voltage Vcalref when the mixer is turned ON. The reference voltage generator140maintains the calibration reference voltage Vcalref when the calibration reference voltage Vcalref reaches a reference voltage. The reference voltage generator140generates the calibration reference voltage Vcalref synchronously with the clock signal CLK.

The feedback loop220generates a digital control code according to the result of the comparison, and generates calibration reference voltage Vcalref corresponding to the digital control code.

The feedback loop220includes a control code generator222that generates the digital control code according to the output of the comparator210, and a voltage source221that generates the calibration reference voltage Vcalref corresponding to the digital control code.

The control code generator222includes a register223that stores the digital control code as a plurality of bits of data, and the control code generator222repeatedly updates the digital control code stored in the register223according to the output of the comparator210. An active hold signal HOLD is provided to the control code generator222when the calibration reference voltage Vcalref reaches the reference voltage, and the control code generator222maintains the digital control code stored in the register223in response to the active hold signal HOLD.

FIG. 3is a circuit diagram of an IP2 calibration circuit in the IP2 calibrator ofFIG. 1.

The IP2 calibration circuit130compares the common-mode voltage Vcm with the calibration reference voltage Vcalref to change the resistances of the first and second output terminals Voutp and Voutm in response to a result of the comparison.

The IP2 calibration circuit130includes a first feedback circuit310that changes the load resistance of the first output terminal Voutp, and a second feedback circuit320that changes the load resistance of the second output terminal Voutm.

The first feedback circuit310includes first and second current sources315and316, first and second NMOS transistors311and312, a first variable resistance317, first and second PMOS transistors313and314, and a first calibration PMOS transistor318. The first and second current sources315and316provide bias currents. The first NMOS transistor311has its gate receiving the common-mode voltage Vcm, and its source connected to the first current source315. The second NMOS transistor312has its gate receiving the calibration reference voltage Vcalref, and its source connected to the second current source316. The first variable resistance317is connected between the source of the first NMOS transistor311and the source of the second NMOS transistor312. The first PMOS transistor313has its gate and its drain commonly connected to the drain of the first NMOS transistor311. The source of the first PMOS transistor313is connected to the power supply voltage. The second PMOS transistor314has its gate and its drain commonly connected to the drain of the second NMOS transistor312. The source of the second PMOS transistor314is connected to the power supply voltage. The first calibration PMOS transistor318constitutes a current mirror with the first PMOS transistor313, and the first calibration PMOS transistor318has its drain connected to the first output terminal Voutp.

The second feedback circuit320includes third and fourth current sources325and326, third and fourth NMOS transistors321and322, second variable resistance327, third and fourth PMOS transistors323and324, and a second calibration PMOS transistor328. The third and fourth current sources325and326provide bias currents. The third NMOS transistor321has its gate receiving the common-mode voltage Vcm, and its source connected to the third current source325. The fourth NMOS transistor322has its gate receiving the calibration reference voltage Vcalref, and its source connected to the fourth current source316. The second variable resistance327is connected between the source of the third NMOS transistor321and the source of the fourth NMOS transistor322. The third PMOS transistor323has its gate and its drain commonly connected to the drain of the third NMOS transistor321. The source of the third PMOS transistor323is connected to the power supply voltage. The fourth PMOS transistor324has its gate and its drain commonly connected to the drain of the fourth NMOS transistor322. The source of the fourth PMOS transistor324is connected to the power supply voltage. The second calibration PMOS transistor328constitutes a current mirror with the third PMOS transistor323, and the second calibration PMOS transistor328has its drain connected to the second output terminal Voutn.

The first feedback circuit310and the second feedback circuit320change the load resistances of the first and second output terminals Voutp and Voutm by a voltage feedback of the common-mode voltage Vcm. Operations of the first feedback circuit310and the second feedback circuit320may be same as an operation of the common-mode feedback circuit120illustrated inFIG. 1.

Meanwhile, the respective gains of the first feedback circuit310and the second feedback circuit320may be changed by adjusting the first and second variable resistances317and327. A difference between the gains of the first feedback circuit310and the second feedback circuit320is used for calibrating IP2 of the mixer.

Hereinafter, there will be an explanation of a reason for using the calibration reference voltage Vcalref instead of the common-mode voltage Vcm in the IP2 calibration circuit.

The gates of the second and fourth NMOS transistors312and322are assumed to receive the common-mode reference voltage Vcmref instead of the calibration reference voltage Vcalref.

FIGS. 4 through 6are signal model equivalent circuit diagrams for explaining development background and operation of the IP2 calibrator100ofFIG. 1.FIG. 4illustrates a small signal model400of the IP2 calibration circuit130ofFIG. 3. Small signal modeling is a common analysis method used in electrical engineering to describe nonlinear devices in terms of linear equations.

Here, an output voltage of the IP calibration circuit130is given by the following Expression 4.

In Expression 4, VIM2, CM is the output voltage of the IP calibration circuit130calculated in common-mode, and VIM2,DM is the output voltage of the IP calibration circuit130calculated in differential-mode. iIM2,CM denotes a common-mode current, and iIM2,DM denotes a differential-mode current.

A resistance difference between the first and second output terminals Voutp and Voutm is given by the following Expression 5.

In Expression 5, Gcalp and Gcalm respectively denote transconductances of equivalent circuits of the first feedback circuit310and the second feedback circuit320inFIG. 3, and Gcmfb denotes a transconductance of an equivalent circuit of the common-mode feedback circuit120inFIG. 1.

Gcalp and Gcalm may be represented as follows
Gcalp=Gcal+ΔGcal, Gcalm=Gcal−ΔGcal

Thus, the resistance difference between the first and second output terminals Voutp and Voutm may be expressed by the following Expression 6.

The gain difference between the first feedback circuit310and the second feedback circuit320increases and a gain of the common-mode feedback circuit decreases with an increase in the resistance difference between the first and second output terminals Voutp and Voutm. The resistance difference between the first and second output terminals Voutp and Voutm in Expression 6 may denote a calibration range.

Therefore, an imbalance of loads (the load resistance of the first output terminal and the load resistance of the second output terminal) of the mixer may be calibrated as given in Expression 6. However, the expression 6 formulated is based on an assumed premise that the current biases of the mixer inFIG. 4are stable. In practice, a differential-mode DC offset occurs when the IP2 of the mixer is calibrated. How the differential-mode DC offset occurs will be described with reference toFIG. 5.

FIG. 5is a small-signal model circuit diagram400of the IP2 calibration circuit130ofFIG. 3for illustrating imbalance of the mixer denoted by an offset current ioffset.

When the imbalance exists, the common-mode voltage Vcm is not identical to the common-mode reference voltage Vcmref despite using the common-mode feedback circuit120.

Now, in the small-signal model ofFIG. 5, a relationship between the common-mode voltage Vcm and the common-mode reference voltage Vcm_ref is given by the following Expression 7.

When the difference between the common-mode voltage Vcm and the common-mode reference voltage Vcmref is defined as a common voltage offset Vcmoffset, the common voltage offset Vcmoffset is given by the Expression 8.

Output currents of the first and second feedback circuits310and320are defined as Expression 9.
Icalm—out=VCMoffsetGcalm
Icalp—out=VCMoffsetGcalp[Expression 9]

The difference current Icaloffset representing the difference between output currents of the first and second feedback circuits310and320is given by the following Expression 10.
Icaloffset=Icalpout−Icalmout=VCMoffset(Gcalp−Gcalm)  [Expression 10]

Expression 11 is a rearrangement of Expression 10.

As represented by Expression 11, the difference between the output currents of the first and second feedback circuits Icaloffset is proportional to the difference of the gains of the first and second feedback circuits310and320, and is inversely proportional to the gain of the common-mode feedback circuit120. Therefore, the gains of the first and second feedback circuits310and320must decrease and the gain of the common-mode feedback circuit120must increase with a reduction of the difference between the output currents of the first and second feedback circuits Icaloffset, thus reducing an effect of the offset current ioffset.

However, the gains of the first and second feedback circuits310and320must increase and the gain of the common-mode feedback circuit120must decrease for extending the calibration range according to Expression 6.

The differential-mode DC offset may occur when an IP2 characteristic is improved, and the IP2 characteristic of the mixer may be worse when the differential-mode DC offset is removed.

For solving such problems, reference voltages of the common-mode feedback circuit120and the IP2 calibration circuit130are set to be different in the IP2 calibrator100ofFIG. 1.

Referring to a small signal model600inFIG. 6of the IP2 calibration circuit130ofFIG. 3, the common-mode reference voltage Vcmref is applied to the common-mode feedback circuit120as the reference voltage. However, the calibration reference voltage Vcalref is applied to the first and second feedback circuits310and320included in the IP2 calibration circuit130. The common-mode reference voltage Vcmref is independent of the calibration reference voltage Vcalref.

Accordingly, the common-mode voltage Vcm may closely follow the common-mode reference voltage Vcmref, and the IP2 characteristic of the mixer may be improved using the IP2 calibration circuit130.

As mentioned above, the IP2 calibrator100and the method for calibrating the IP2 of the mixer may calibrate the IP2 and may remove the differential-mode DC offset.

The IP2 calibrator100and the method for calibrating the IP2 use different reference voltages in contrast to the single reference voltage in a conventional IP2 calibrator700using a conventional common mode feedback method. The different reference voltages are the common-mode reference voltage Vcmref of the common-mode feedback circuit for removing the common-mode DC offset and the calibration reference voltage Vcalref of the IP2 calibration circuit for calibrating IP2. Thus, the IP2 calibrator100and the method for calibrating the IP2 according to exemplary embodiments of the present invention may efficiently remove the differential-mode DC offset and calibrate the IP2.

While the exemplary embodiments of the present invention and their features have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the scope of the invention.