Monolithic integrated circuit (MMIC) structure having composite etch stop layer and method for forming such structure

A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. The etch stop layer includes the etch stop layer comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.

TECHNICAL FIELD

This disclosure relates generally to a Monolithic Integrated Circuit (MMIC) Structure and to a method for selectively etching a dielectric layer using an underling etch stop layer to protect an underling active device passivation layer.

BACKGROUND AND SUMMARY

As is known in the art, as monolithic microwave integrated circuits (MMICs) are designed to operate at ever higher frequencies, the effects of dielectric loading on various MMIC conduction paths (including gates and transmission lines) becomes more pronounced. The minimization of such loading is critical to achieving the desired gain performance.

As is also known in the art, plasma enhanced chemical vapor deposition (PECVD) is widely used for the deposition of silicon nitride, which may act as a passivation layer to passivate components, or act as a capacitor dielectric. This deposition technique however, coats regions of the MMIC where the presence of additional dielectric is not desired and adversely impacts device performance at the higher frequencies.

As described in co-pending patent application Ser. No. 13/849,858, filed Mar. 25, 2013, published in U. S. Patent Application Publication 2014/0284661, published Sep. 25, 2014, assigned to the same assignee as the present patent application, a method was disclosed for forming a semiconductor structure, the entire subject matter thereof being incorporated herein by reference. The method included: providing a semiconductor layer with a transistor device having a control electrode for controlling a flow of carriers between a first electrode and a second electrode; depositing a passivation layer over the first electrode, the second electrode and the control electrode; depositing an etch stop layer on the passivation layer, such etch stop layer being disposed over the control electrode; forming a dielectric layer over the etch stop layer; and etching a window through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode.

In forming such structure it was discovered that chemicals used in the photolithographic processing effected the etch stop layer.

In accordance with this disclosure, the etch stop layer is formed as a composite structure, comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer. With such an arrangement, chemicals used in the photolithographic processing while effecting the second etch stop layer are prevented from effecting the first etch stop layer by the buffer layer.

More particularly, it was found that the etch stop layer described in the above referenced U. S. Patent Application Publication 2014/0284661 was subject to attack from other commonly used process chemicals in standard MMIC fabrication such as ammonia and photoresist developer. Employing a buffer, such as, for example, a silicon dioxide interlayer, effectively creates a double-selective etch-stop layer that survives typical MMIC fabrication processing up to the point where etch-back is required. Post etch-back, it has been found that the residual etch stop material can be removed by timed exposure to ammonia since ammonia acts as a highly selective etchant to Atomic Layer Deposition (ALD) deposited aluminum oxide to PECVD nitride. This removal mitigates impact to RF performance of any residual dielectric associated with the etch-stop layer.

In one embodiment, the first etch stop layer is aluminum oxide.

In one embodiment the buffer layer is silicon dioxide;

In one embodiment, the second etch stop layer is aluminum oxide.

In one embodiment, the transistor device is a field effect transistor.

In one embodiment, the semiconductor layer is a III-V semiconductor material.

In one embodiment, the passivation layer is silicon nitride.

In one embodiment, the dielectric layer is silicon nitride.

In one embodiment, the dielectric layer is Plasma Enhanced Chemical Vapor Deposited (PECVD) silicon nitride

In one embodiment, the first etch stop layer is an atomic layer deposited (ALD) layer.

In one embodiment, the second etch stop layer is an atomic layer deposited (ALD) layer.

DETAILED DESCRIPTION

Referring now toFIG. 1A, a semiconductor structure10is shown having a substrate11, here for example silicon carbide with a GaN semiconductor layer13thereon and a additional semiconductor layer12on semiconductor layer13, layer12is here for example, a III-V semiconductor layer such as for example, here AlGaN. It should be understood that other semiconductors such GaAs, InP, for example, may be used on the suitable substrate. The semiconductor layer12has a transistor device,14, here for example a field effect transistor (FET) device formed therein using any conventional processing to provide source and drain electrodes16,18, respectively as shown, in ohmic contact with the semiconductor layer12and a T-shaped gate electrode20in Schottky contact with the semiconductor layer12and a passivation layer22, here disposed over the source and drain electrodes16and18, and a portion of the semiconductor12as shown. Here for example the passivation layer22is silicon nitride. The gate electrode20controls the flow of carriers in the semiconductors layers12,13between the source and drain electrodes. It is noted that the silicon nitride layer22is spaced from the bottom portion of the vertical sides of the T-shaped gate20.

Next, referring toFIG. 1B, an additional layer24of silicon nitride is uniformly deposited over the entire structure shown inFIG. 1A, including the space in the layer22so that the additional layer abuts the bottom portion of the vertical sides of the T-shaped gate20. Here, for example, the layer24is a 200 Angstrom thick layer of PECVD silicon nitride to provide gate20passivation.

Next, referring to FIG. IC, an etch stop layer structure26is uniformly disposed by Atomic Layer Deposition (ALD) on the passivation layer24. Here, the etch stop layer structure26is a composite layer having: a first etch stop layer26aof here for example, aluminum oxide, on the passivation layer24, a buffer layer26bof here for example silicon dioxide on the first etch stop layer26a, and a second etch stop layer26cof here for example aluminum oxide on the buffer layer26b, as shown inFIG. 1C′. With such an arrangement, chemicals used in the photolithographic processing, to be described, while effecting the second etch stop layer26care prevented from effecting the first etch stop layer26aby the buffer layer26b. Here, the first and second etch stop layers26aand26care here for example, each 25 Angstrom thin layer of Atomic Layer Deposited (ALD) layer of aluminum oxide and layer26bis here for example, silicon dioxide having a thickness of, for example 10 Angstroms to 50 Angstroms.

Next, referring toFIG. 1D, first level active device metallization processing begins by first forming a layer27of photoresist patterned as shown to have formed there-through windows28to expose portions of the etch-stop layer structure26and passivation layers22and24over the source and drain electrodes16,18while covering the other portions of the etch-stop layer26including the portion of the etch-stop layer26over the gate electrode20, as shown. It is noted that the gate electrode20terminates in a conductive gate pad, not shown, (out of the plane shown inFIG. 1D) and this conductive gate pad is also exposed by the windows28in the photoresist layer27. The structure with the windowed photoresist layer27, as shown, is subjected to a dry, for example, plasma, or wet etch, to remove, in a first step, portions of the etch-stop layer26exposed by the windows28and then, in a second step, as shown inFIG. 1E, remove the portions of the underlying silicon nitride passivation layers24and22thereby exposing the source and drain electrodes16and18as well as the not shown, out of plane gate contact pad. The photoresist layer27(FIG. 1D) is then stripped using any conventional removal technique, thereby leaving the structure shown inFIG. 1E.

Next, referring toFIG. 1F, a photoresist layer30is deposited and lithographically processed to have windows32formed therein to expose regions where a first level (level1) metallization is to be formed. This level1metallization will be used to form interconnects for the source and drain electrodes16,18, the gate contact pad (not shown and referred to above) as well as bottom electrodes for capacitors, to be described, and microwave transmission lines and coplanar ground plane structures of the MMIC to be formed.

Referring now also toFIG. 1G, metal34, here for example, a stack of titanium/platinum/gold is deposited on the photoresist layer30(FIG. 1F) and through the windows32therein onto the aforementioned exposed source and drain electrodes16,18, on the aforementioned gate contact pad (not shown) as well as other portions here for example a portion36of the etch stop layer26where a capacitor is to be formed. The photoresist layer30(FIG. 1F) is then stripped from the surface along with any metal34on top of layer30using any conventional removal technique, here including an ammonia wash, thereby resulting in the metal34thereon being lifted off the structure resulting in the structure shown inFIG. 1G.

Next, exposed portions of the second etch stop layer26cof ALD aluminum oxide layer are removed to clean the top surface of the wafer prior to depositing a PECVD silicon nitride layer40(FIG. 11). More particularly, prior to depositing the PECVD silicon nitride layer40, a solvent pro-clean process is used to prepare the wafer surface for the PECVD silicon nitride layer40. Such pro-cleans use chemical agents such as trichloroethylene, acetone, isopropanol, methanol, ammonia, etc. During the pro-clean procedure, the top-most aluminum oxide26cis attacked and is therefore compromised in its ability to act as a good etch stop layer in subsequent processing. However, the silicon dioxide layer26bacts to protect the bottommost aluminum oxide layer26c, allowing for good gate and gate channel protection during the etch to be described in connection withFIG. 1J. It is also noted that the portions of the second etch stop layer26cunder the metal layer section34aof metal layer34where the bottom plate of a capacitor is to be formed in a manner to be described, remains as it is protected by the metal layer section34a.

Next, a photoresist layer42is deposited and photolithographically processed to have a window44formed therein, as shown inFIG. 1J, with the photoresist layer42remaining over the portions of metal34being used, as mentioned above, to provide a bottom plate34afor a capacitor to be formed. The structure is exposed to a dry etch, such as for example, a plasma etch such as reactive ion etching (RIB) or inductively coupled plasma etching (ICP), using sulfur hexafluoride based plasma etchants, or a wet etch. It is noted that the etch process etches away the exposed portions of the silicon nitride layer40at a rate significantly greater than that to the underlying portions of the aluminum oxide layer26a, here for example 100 times greater, thus the aluminum oxide layer26ais considered an etch stop layer since the etching stops at the aluminum oxide layer26a, as indicated inFIG. 1Kafter removal of the photoresist layer42. It is noted that the same etch step that removes the exposed portions of the thick silicon nitride layer40also removes underlying portions of the silicon dioxide layer26bbut the process still leaves the aluminum oxide layer26a, as shown inFIG. 1K. (It is noted that the metal34disposed on the source and drain electrodes16,18as well as the metal34disposed on the out of plane gate conductor pad (not shown) refered to above exposed by the window also acts as an etch stop).

Next, the second level (level2) metallization process begins by depositing a photoresist layer50and pattering the photoresist layer50lithographically to have windows52formed there-through, as shown inFIG. 1L. The windows52expose the metal34used for the source and drain electrode16,18, the gate conductor pad (not shown and described above) and the portion of the silicon nitride dielectric layer40over the bottom metal plate34ato be used as the dielectric for the capacitor being formed. Next metal56, here, for example, a stack of titanium/platinum/gold is deposited on the remaining portions of the photoresist layer50and on the metal34used on the source and drain electrodes16,18, the gate conductor pad (not shown and described above) and the portion of the silicon nitride dielectric layer40to be used for the capacitor being formed. Next, the photoresist layer50(FIG. 1L) is stripped using any conventional removal technique, here including an ammonia wash with the portions of the metal56thereon being lifted off the structure while the remaining portions of the metal56remain on the first-level metal34disposed on source and drain electrode metal16,18, the gate conductor pad (not shown and described above) and the portion of the silicon nitride dielectric disposed on first-level metal34, thereby completing the formation of the capacitor60, the upper plate being designated56aof the MMIC62(FIG. 1M).

Next, the aluminum oxide layer26ais removed from regions unprotected by metal34or silicon nitride layer40, as shown inFIG. 1N, using dilute ammonia. This eliminates the presence of the etch stop layer in the active regions of the MMIC, specifically in the entire region between source and drain contacts, with includes the surface above the transistor channel regions and around the entire gate electrode.

It should be noted that the process described above may be modified so that the composite etch stop layer, shown inFIG. 1C′, may be formed after the structure shown inFIG. 1Gis formed rather than after the structure shown inFIG. 1Bis formed. In such case, structure after performing the process described above in connection withFIGS. 1H-1M, the modified process would result in the structure shown inFIG. 2A. The process described above in connection withFIG. 1Nwould therefore result in the structure shown inFIG. 2B.

A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, the method may be used with bipolar transistors. Accordingly, other embodiments are within the scope of the following claims.