Semiconductor device

A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese patent application No. 2005-191449 filed on Jun. 30, 2005, the content of which is hereby incorporated by reference into this application

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and in particular to a technique effectively applicable to a semiconductor device having power MISFETs (Metal Insulator Semiconductor Field Effect Transistors).

For example, Patent Documents 1 and 2 disclose semiconductor devices for driving a three-phase motor.

For example, Patent Documents 3 and 4 disclose semiconductor devices for DC-DC converter.

For example, Patent Document 5 discloses a processing method for HSOP.

For example, when a circuit for driving a vehicle-mounted motor or any other like motor is constructed, a plurality of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used for this purpose. The plurality of MOSFETs are independently formed in a plurality of packages. The circuit for driving a motor is constructed by mounting these plurality of packages over a mounting board.

In this case, a problem arises because a plurality of semiconductor devices are mounted. A footprint is increased, and downsizing is infeasible.

Consequently, the present inventors considered multi (plural) chip packages (semiconductor devices) of high heat radiation type which allow footprints to be reduced.

A DC-DC converter having two MOSFETs (semiconductor chips) will be taken as an example. In cases where the DC-DC converter has two semiconductor chips mounted over a tab and two MOSFETs are nMOSFET and pMOSFET, a drain can be shared between them. Therefore, the tab need not be divided, and the DC-DC converter is of such construction that two semiconductor chips are mounted over one tab.

In cases where two MOSFETs are both nMOSFET in a DC-DC converter, a drain cannot be shared between them. Therefore, it is required to divide a tab into one for the high-side semiconductor chip of one nMOSFET and one for the low-side semiconductor chip of the other nMOSFET. Thus, the DC-DC converter is of such construction that a semiconductor chip containing an nMOSFET is mounted over each of the two divided tabs. (Refer to Patent Document 3.)

That is, in a DC-DC converter having two MOSFETs (semiconductor chips), a tab is so constructed that it is not divided as in the former of the above examples or so constructed that it is divided into two as in the latter.

In the technology disclosed in Patent Document 1 (Japanese Unexamined Patent Publication No. 2004-273749) a wire is connected to a frame. Therefore, the following problem arises: it is required to ensure areas for wire connection in frames, and this imposes limitation on chip size.

In addition, the following problem can also arise: since wires are bonded astride frames, the switching noise of a low-side transistor element adversely affects a high-side transistor element via the inductance of a wire. As a result, the high-side transistor element can be caused to malfunction.

SUMMARY OF THE INVENTION

An advantage of the invention is to provide a technique that enables downsizing of a semiconductor device having a plurality of chips.

Another advantage of the invention is to provide a technique that enables the enhancement of the heat radiating property of a semiconductor device having a plurality of chips.

The above and further advantages and novel features of the invention will be apparent from the description of this specification and the accompanying drawings.

The following is a brief description of the gist of the representative elements of the invention laid open in this application.

The invention includes: a semiconductor chip including a pMISFET and a semiconductor chip including an nMISFET respectively mounted over first, second, and third tabs; a plurality of leads electrically connected with the individual semiconductor chips; and a sealing portion that seals the first, second, and third tabs and the semiconductor chips. The drains of the pMISFET and nMISFET mounted over each of the first, second, and third tabs are electrically connected with each other.

Also, the invention includes: a semiconductor chip including a pMISFET and a semiconductor chip including an nMISFET respectively mounted over first and second tabs; a plurality of leads electrically connected with the individual semiconductor chips; and a sealing portion that seals the first and second tabs and the semiconductor chips. The drains of the pMISFET and nMISFET mounted over each of the first and second tabs are electrically connected with each other.

Further, the invention includes: first, second, third, and fourth tabs; semiconductor chips including a pMISFET respectively mounted over first and second tabs; semiconductor chips including an nMISFET respectively mounted over third and fourth tabs; a plurality of leads electrically connected with each semiconductor chip; and a sealing portion that seals the first, second, third, and fourth tabs and the semiconductor chips.

The following is a brief description of the gist of the effects obtained by the representative elements of the invention laid open in this application.

In a semiconductor device for driving a three-phase motor, a semiconductor chip including a pMISFET and a semiconductor chip including an nMISFET are mounted over each of first, second, and third tabs. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. This makes it possible to place two of six MISFETs over each of three tabs divided in accordance with the number of phases of the motor and package them in one in a compact manner. As a result, the semiconductor device for driving a three-phase motor, having a plurality of chips can be reduced in size. The back sides of the first, second, and third tabs are exposed from the sealing portion, and the thickness of each tab is greater than the thickness of leads. Therefore, the heat radiating property of the tabs can be enhanced. As a result, the heat radiating property of the semiconductor device for driving a three-phase motor, having a plurality of chips can be enhanced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following description of embodiments, an identical or similar portion will not be repeatedly described as a rule unless the description is especially required.

In the following description of embodiments, one embodiment will be divided into plural sections or embodiments if necessary for convenience. However, they are not independent of one another but are in such relation that one is a modification to or the details, supplementary explanation, or the like of part or all of another.

In cases where a number of elements (including a number of pieces, numeric value, quantity, range, and the like) is cited in the following description of embodiments, the invention is not limited to that specific number. Any number greater or less than that specific number is acceptable. However, this does not apply when otherwise stated, when the invention is obviously limited to that specific number according to the principle, or in other like cases.

Hereafter, detailed description will be given to embodiments of the invention with reference to the drawings. In all the drawings for the explanation of embodiments, members having the same functions will be marked with the same reference numerals, and the repetitive description of them will be omitted.

First Embodiment

FIG. 1is a plan view illustrating an example of the construction of a semiconductor device (for driving a three-phase motor) in a first embodiment of the invention as viewed through its sealing portion;FIG. 2is an equivalent circuit diagram illustrating an example of circuitry for driving a three-phase motor, using the semiconductor device illustrated inFIG. 1;FIG. 3is an equivalent circuit diagram illustrating an example of circuitry in which a semiconductor device in the first embodiment of the invention is applied to HSOP; andFIG. 4is a circuitry diagram illustrating an example of the operation of a drive circuit in which n and pMISFET are incorporated together with respect to the semiconductor device illustrated inFIG. 1.FIG. 5is a circuitry diagram illustrating the operation of a drive circuit in which only nMISFETs are incorporated with respect to a semiconductor device in a comparative example;FIG. 6is a perspective view illustrating an example of the construction of the semiconductor device illustrated inFIG. 1;FIG. 7is a perspective view illustrating an example of the construction of the back side of the semiconductor device illustrated inFIG. 1;FIG. 8is a sectional view illustrating an example of the construction of the semiconductor device illustrated inFIG. 1;FIG. 9is a sectional view illustrating an example of the construction of a semiconductor chip incorporated in the semiconductor device illustrated inFIG. 1; andFIG. 10is a plan view illustrating an example of the construction of the semiconductor chip illustrated inFIG. 9.FIG. 11is a partial plan view illustrating an example of the construction of a lead frame used in the assembly of the semiconductor device illustrated inFIG. 1;FIG. 12is a sectional view illustrating the construction of the lead frame illustrated inFIG. 11, taken along the line A-A ofFIG. 11;FIG. 13is a partial plan view illustrating the construction of a principal part of the lead frame illustrated inFIG. 11; andFIG. 14is a sectional view illustrating the construction of the lead frame illustrated inFIG. 13, taken along the line B-B ofFIG. 13.

FIG. 15is a partial plan view illustrating the construction of a lead frame in a modification to the first embodiment of the invention;FIG. 16is a sectional view illustrating the construction of the lead frame illustrated inFIG. 15, taken along the line A-A ofFIG. 15;FIG. 17is a partial sectional view illustrating an example of the construction of the semiconductor device illustrated inFIG. 1after wire bonding in its assembly; andFIG. 18is a thermal resistance data diagram illustrating an example of the actual measurement data about thermal resistance due to the plate thickness of a tab in a semiconductor device in the first embodiment of the invention.

The semiconductor device in the first embodiment is a semiconductor package for driving a three-phase motor. It is of multichip structure and has a plurality of semiconductor chips each having a MISFET incorporated in it.

The above semiconductor device is of high heat radiation type. In the description of the first embodiment, the HSOP (Heat Sink Small Outline Package)46illustrated inFIG. 1will be taken as an example of the above semiconductor device. Such a semiconductor device is used for in-vehicle applications, for example. However, its applications are not limited to in-vehicle applications but it may be used to drive a common motor or the like.

The HSOP46is a semiconductor package for driving a three-phase motor. As illustrated inFIG. 2, therefore, it has three sets of circuits for driving, each set composed of a p-channel MISFET (hereafter, referred to as “pMISFET”)32and an n-channel MISFET (hereafter, referred to as “nMISFET”)33, in correspondence with three phases. It drives a motor40in three phases by power supply42and a signal from a driver IC (Integrated Circuit)41.

As illustrated inFIG. 3, the HSOP46has three pMISFETs32on the high-supply voltage side (high side) and three nMISFETs33on the low-supply voltage side (low side). It drives the motor40in three phases by the six MISFETs in total. That is, it has three sets of circuits for driving, each set composed of a pMISFET32and an nMISFET33. It causes signals in phases U, V, and W to be individually outputted from drains by the respective circuits, and thus drives the motor40in three phases. Therefore, the HSOP46is a semiconductor device in which p and nMISFETs are incorporated together.

The pMISFETs32and nMISFETs33are those with low breakdown voltage, and their voltage between source and drain is lower than 100V (VDSS<100V).

The HSOP46in the first embodiment has three tabs (first tab34, second tab35, and third tab36) divided in correspondence with the number of phases (three phases) of the motor40as illustrated inFIG. 1. One set of a pMISFET32and an nMISFET33is mounted over each tab. One set of a first semiconductor chip30including a pMISFET32and a second semiconductor chip31including an nMISFET33is mounted over each of the main surfaces34a,35a, and36aof the first tab34, second tab35, and third tab36. (Refer toFIG. 14.)

The three first semiconductor chips30each including a pMISFET32are placed on the high side and the three second semiconductor chips31each including an nMISFET33placed on the low side.

The source pads30cformed over the main surfaces30aof the first semiconductor chips30are electrically connected with corresponding leads37bfor source through conductive wires39. The gate pads30dsimilarly formed are electrically connected with corresponding leads37afor gate through conductive wire39. As illustrated inFIG. 8, the back sides30bof the first semiconductor chips30form drain pads30e. These drain pads30eare electrically connected with tabs through solder43. Further, leads37cfor drain (some of the leads37) and the tabs are integrally joined with each other.

Similarly, the source pads31cformed over the main surfaces31aof the second semiconductor chips31are electrically connected with corresponding leads37bfor source through conductive wires39. The gate pads31dsimilarly formed are electrically connected with corresponding leads37afor gate through conductive wires39. As illustrated inFIG. 8, the back sides31bof the second semiconductor chips31form drain pads31e. These drain pads31eare electrically connected with tabs through solder43. Further, the tabs and leads37cfor drain (some of the leads37) are integrally joined with each other.

Therefore, the first semiconductor chip30and second semiconductor chip31over the first tab34share a drain electrode between them over the tab; the first semiconductor chip30and second semiconductor chip31over the second tab35share a drain electrode between them over the tab; and the first semiconductor chip30and second semiconductor chip31over the third tab36share a drain electrode between them over the tab.

That is, the first tab34, second tab35, and third tab36are respectively electrically connected with the drains of a pMISFET32and an nMISFET33. The drains of the pMISFETs32and the nMISFETs33are electrically connected with each other through each of the first tab34, second tab35, and third tab36.

However, the drain electrodes of MISFETs are not electrically short-circuited between phases because a tab is divided into three in correspondence with the number of phases of the motor40.

FIG. 1illustrates the disposition (G, S, D) of the plurality of leads37composed of leads37afor gate, leads37bfor source, and leads37cfor drain as an example. However, the disposition of the leads is not limited to that illustrated inFIG. 1.

A comparison will be made between a drive circuit with p and nMISFETs incorporated together and a high-side drive circuit with nMISFETs only incorporated with reference toFIG. 4(first embodiment) andFIG. 5(comparative example).

FIG. 4illustrates an example of a drive circuit with p and nMISFETs incorporated together, adopted in the HSOP46in the first embodiment.FIG. 5illustrates a high-side drive circuit with nMISFETs only incorporated as a comparative example.

As illustratedFIG. 4, the pMISFET32can operate as the result of the following: Q1operates and thus the voltage at point A (gate) becomes lower than the potential at point B (source). That is, the drive circuit with p and nMISFETs incorporated together, illustrated inFIG. 4, can be operated with very simple circuitry.

To operate the nMISFET33in the drive circuit inFIG. 5as a comparative example, the voltage at point D (gate) must be higher than the potential at point C (source). Since point C is at substantially the same potential as +B during operation, however, a driver IC101provided with a booster circuit for making the potential at point D higher than that at point C. Therefore, a drive circuit with nMISFETs only incorporated inevitably uses IC, and this complicates the circuit.

Therefore, the drive circuit with p and nMISFETs incorporated together, adopted in the first embodiment can be constructed with more simple circuitry as compared with the drive circuit with nMISFETs only incorporated as a comparative example. Therefore, the circuit with p and nMISFETs incorporated together allows footprints to be reduced.

Description will be given to the details of the construction of the HSOP46in the first embodiment. It has the first tab34, second tab35, and third tab36, which are tabs divided into three in correspondence with three phases. As illustrated inFIG. 1, a first semiconductor chip30including a pMISFET32and a second semiconductor chip31including an nMISFET33are mounted over each tab.

The individual semiconductor chips are electrically connected with corresponding leads37through wires39. More specific description will be given. The gate pads30dof the first semiconductor chips30and the gate pads31dof the second semiconductor chips31are electrically connected with respective corresponding leads37afor gate through wires39. The source pads30cof the first semiconductor chips30and the source pads31cof the second semiconductor chips31are electrically connected with respective corresponding leads37bfor source through wires39.

The drain pads30eof the first semiconductor chips30and the drain pads31eof the second semiconductor chips31are electrically connected with respective tabs through solder43.

Parts of the first tab34, second tab35, third tab36, and a plurality of leads37, the first semiconductor chips30, and the second semiconductor chips31are plastic molded with a sealing portion44formed of sealing resin.

As illustrated inFIG. 7, the respective back sides34b,35b, and36bof the first tab34, second tab35, and third tab36are exposed at the underside of the sealing portion44. As illustrated inFIG. 8andFIG. 14, the respective thickness of the first tab34, second tab35, and third tab36is larger than the thickness of the leads37(twice to three times or so).

As mentioned above, parts (back sides34b,35b, and36b) of the individual tabs that also function as drain terminals are exposed at the underside of the sealing portion44. Each tab is so formed that it is thicker than the leads37. As a result, each tab can be provided with a heat sink function to enhance the heat radiating property of the HSOP46.

FIG. 18illustrates an example of the relation between time and thermal resistance with various tab thicknesses taken as a parameter by actual measurement data. In case of (B) in which the tab is thick (t=1.3 mm) or in case of HSOP (t=1.26 mm), the thermal resistance is lower than in case of (A) in which the tab is thin (t=0.5 mm). Therefore, the heat radiating property of the HSOP46can be enhanced by adopting a thick tab (heat sink). An example of (A) is a surface mount MOSFET, and an example of (B) is a large surface mount MOSFET.

As illustrated inFIG. 8, the wire bonding faces37dof the individual plural leads37are disposed that they are farther from the respective tabs than the tabs' main surfaces34a,35a, and36aon the main surface side. More specific description will be given. Some of the leads37(the leads37cfor drain) are stepped, and thus the wire bonding faces37dof the leads37are so disposed that they are higher than the main surfaces34a,35a, and36aof the individual tabs.

Therefore, the wires39can be prevented from being brought into contact with an edge of the main surface of a chip. Thus, the wires39can be prevented from being short-circuited to a first semiconductor chip30or a second semiconductor chip31.

A plurality of outer leads37eof the plural leads37protruding from side faces of the sealing portion44are bent into gull wing shape as illustrated inFIG. 6andFIG. 8. The surfaces of the outer leads37eand the back sides34b,35b, and36bof the tabs are coated with solder plating45as outer plating.

The first semiconductor chips30and the second semiconductor chips31are formed of silicon, for example. The tabs and the leads are formed of copper alloy, for example. The wires39are aluminum wires or gold wires, for example. The solder43as die bond material is high-melting point solder, for example. Resin paste may be used as die bond material, or Au—Si eutectic bonding may be used. The sealing resin for forming the sealing portion44is epoxy resin, for example.

Description will be given to the configuration of a semiconductor chip incorporated into the HSOP46in the first embodiment with reference toFIG. 9andFIG. 10. Here, the configuration of a semiconductor chip including an nMISFET33will be described as an example.

As illustrated inFIG. 9, this semiconductor chip is formed by preparing a semiconductor substrate (hereafter, simply referred to as “substrate”) obtained by the following processing: an n−-type single-crystal silicon layer1B doped with impurity of n conductivity type is epitaxially grown over the surface of an n+-type single-crystal silicon substrate1A of n conductivity type. This substrate includes: an active cell area ACA in which the active cell of a power MISFET is formed; an inactive cell area NCA in which an inactive cell is formed; a gate wiring area GLA in which wiring electrically connected with the gate electrode of the power MISFET is formed; and a termination area FLR in which field limiting rings are formed. The n+-type single-crystal silicon substrate1A and the n−-type single-crystal silicon layer1B form the drain region of the power MISFET.

There are trenches4formed in the active cell area ACA and the inactive cell area NCA, and there is a trench5formed in the gate wiring area GLA. The substrate is subjected to thermal oxidation, and a silicon oxide film6is formed on the side walls and bottom of the trenches4and5. This silicon oxide film6is the gate insulating film of the power MISFET.

A field insulating film3A is formed over the n−-type single-crystal silicon layer1B, and a silicon oxide film9is deposited over the film.

Further, contact grooves15,16,17, and18are formed in an insulating film14, and a p+-type semiconductor region20is formed at the bottom of the contact grooves15,16,17, and18. This p+-type semiconductor region20is for bringing the wiring into ohmic contact with p−-type semiconductor regions10or p−-type field limiting rings11at the bottom of the contact grooves15,16,17, and18.

In the semiconductor chip, a thin TiW (titanium tungsten) film as a barrier conductor film is deposited over the insulating film14including the interior of the contact grooves15,16,17,18, and19by sputtering, for example. Further, an Al (aluminum) film is formed over the film. The barrier conductor film functions to prevent an undesired reaction layer from being formed by contact between Al and the substrate (Si). The Al film means a film predominantly composed of Al, and it may contain any other metal or the like.

The TiW film and the Al film are etched, and the following are formed: a gate wiring21electrically connected with a gate lead-out electrode8; a source pad (source electrode)22electrically connected with an n+-type semiconductor region12that forms the source region of the power MISFET; and a wiring23that is electrically connected with one of the p−-type field limiting rings11and is electrically connected with the source pad22in a region not shown inFIG. 9. Further, the following are formed: a wiring24electrically connected with a p−-type field limiting ring11that is different from the p−-type field limiting ring11electrically connected with the wiring23; a wiring25electrically connected with an n+-type guard ring region13; and a gate pad (gate electrode) electrically connected with the gate wiring21.

When a plan view is drawn illustrating the way the gate wiring21, source pad22, wirings23,24, and25, and gate pad are formed, that is as illustrated inFIG. 10.FIG. 10illustrates a chip section CHP equivalent to one chip obtained by dividing a substrate into individual chips. The section illustrated inFIG. 9shows the section of this chip section taken along the line A-A.

In the chip section CHP (planar surface), as illustrate inFIG. 10, the active cell area ACA, inactive cell area NCA, gate wiring area GLA, and termination area FLR are so formed that the following is implemented: the inactive cell area NCA encircles the active cell area ACA; the gate wiring area GLA encircles the inactive cell area NCA; and the termination area FLR encircles the gate wiring area GLA.

The n+-type semiconductor region12that forms the source of a power MISFET in the first embodiment is formed in the active cell area ACA and is not formed in the inactive cell area NCA. In cases where the n+-type semiconductor region12is also formed in the inactive cell area NCA, a parasitic MISFET is formed in which: the n+-type single-crystal silicon substrate1A and the n−-type single crystal silicon layer1B are a drain region; the n+-type semiconductor region12is a source region; the gate lead-out electrode8is a gate electrode; and the p−-type semiconductor regions10are channels.

As mentioned above, the gate electrode7and the gate lead-out electrode8are integrally formed and electrically connected with each other. Consequently, the following trouble can occur: when the power MISFET is operated, this parasitic MISFET also operates, and electro-current constriction occurs in a cell in proximity to the peripheral area of the chip. To cope with this, the first embodiment adopts the following construction: the power MISFET cell formed in the active cell area ACA is encircled with the inactive cell area NCA in which a dummy cell with no n+-type semiconductor region12present is formed. Thus, parasitic operation due to such a parasitic MISFET can be prevented. The trouble of an occurrence of electro-current constriction in a cell in proximity to the peripheral area of the power MISFET chip can be thereby prevented.

As illustrated inFIG. 10, the planar pattern of gate electrodes7(trenches4) in the first embodiment is of rectangular mesh. The source pad22formed over the gate electrodes7is electrically connected with the wiring23. A gate pad (gate electrode)26is formed of the same wiring layer as the gate wiring21, source pad22, and wirings23,24, and25are, and is electrically connected with the gate wiring21. The wiring25electrically connected with the n+-type guard ring region13and the wiring24and wiring25electrically connected with the p−-type field limiting rings11are sequentially disposed from the outermost area of the chip section so that the active cell area ACA is encircled with them.

In the semiconductor device (HSOP46) in the first embodiment, the following is implemented in the HSOP46for driving a three-phase motor: a first semiconductor chip30including a pMISFET32and a second semiconductor chip31including an nMISFET33are mounted over each of the first tab34, second tab35, and third tab36. The drains of the pMISFET32and nMISFET33over each tab are electrically connected with each other. Thus, the HSOP46can be reduced in size.

More specific description will be given. Two of six semiconductor chips each including MISFET are placed over each of three tabs divided in correspondence with the number of phases of the motor40. These chips are packaged in one in a compact manner. This makes it possible to reduce the size of the semiconductor device (HSOP46) for driving a three-phase motor, having a plurality of chips.

The respective back sides34b,35b, and36bof the first tab34, second tab35, and third tab36that also function as drain terminals are exposed at the underside of the sealing portion44. Further, each tab is so formed that it is far thicker than the leads37. Thus, each tab can be provided with a heat sink function to enhance the heat radiating property of the HSOP46.

As a result, the heat radiating property of the semiconductor device (HSOP46) for driving a three-phase motor, having a plurality of chips can be enhanced.

The HSOP46in the first embodiment is a semiconductor device of such construction that p and nMISFETs are incorporated together. Description will be given to the effect obtained by this embodiment through comparison with the semiconductor device (HSOP100) illustrated as a comparative example inFIG. 25. This semiconductor device has nMISFETs only incorporated and is so constructed that a tab is divided into four.

In the above description, the drive circuit with p and nMISFETs incorporated together, illustrated inFIG. 4, was compared with the drive circuit with nMISFETs only incorporated, illustrated as a comparative example inFIG. 5. As described through comparison, the drive circuit with p and nMISFETs incorporated together has an advantage that it can be operated with simpler circuitry.

The size of divided tabs is uniform in the HSOP46illustrated inFIG. 1as compared with that of the comparative example. Heat produced by each tab is uniform, and this makes it possible to enhance the reliability of the system. Meanwhile, the HSOP100with nMISFETs only incorporated, illustrated as a comparative example inFIG. 25, involves the following problem. The common tab50for drain is much larger than the other tabs, and heat produced by each tab cannot be made uniform and the enhancement of reliability is difficult to accomplish.

In the HSOP100illustrated as a comparative example inFIG. 25, the source electrodes of the high-side MISFETs and the drain electrodes of the low-side MISFETs are connected with each other through wires39astride tabs. As a result, it is difficult to inspect erroneous connection between tabs (due to sticking solder or the like). When voltage is applied to between tabs in this case, any MISFET is almost short-circuited, and lets a current through it. In the HSOP46in the first embodiment illustrated inFIG. 1, the individual tabs are completely separated from one another, and can be easily inspected for erroneous connection between tabs.

In the HSOP100illustrated as a comparative example inFIG. 25, wires39are bonded to tabs, and thus bonding areas for wires39must be ensured in the tabs. This imposes limitation on chip size. In case of the HSOP46in the first embodiment illustrated inFIG. 1, wires39are not connected to tabs. Therefore, the chip size can be increased as long as the tab size permits. This is highly advantageous in terms of commercialization and assembling operation.

In the HSOP100illustrated as a comparative example inFIG. 25, wires39are bonded astride tabs. Therefore, the switching noise of a low-side MISFET gets into the source electrode of a high-side MISFET via the inductance of a wire39, and shifts a potential. As a result, the risk that its gate electrode is caused to malfunction is increased.

In case of the HSOP46in the first embodiment illustrated inFIG. 1, tabs are completely separated from one another. Therefore, they are not affected by one another, and the reliability of the system can be enhanced.

Description will be given to the assembly of the HSOP46(semiconductor device) in the first embodiment.

FIG. 11andFIG. 12illustrate the configuration of a substantial part of a lead frame38used in the assembly of the HSOP46.

The lead frame38is provided in one package region with a first tab34, second tab35, and third tab36, which are three tabs divided in correspondence with the number of phases of the motor40. A plurality of leads37are provided around them. The first tab34, second tab35, and third tab36are divided by slits38cformed between them.

Each of the plurality of leads37is supported by adjacent leads37and a dam bar38e, and of the plurality of leads37, the leads37cfor drain are integrally joined with the respective tabs. More specific description will be given. Each tab is so constructed that a drain electrode is shared between two semiconductor chips mounted over it. Therefore, the tabs are integrally joined with the leads37cfor drain and supported by the leads37cfor drain.

As illustrated inFIG. 12, each lead37cfor drain is bent and provided with a stepped portion38a. Thus, the wire bonding faces37dof the individual leads37, including the leads37cfor drain, are so disposed that they are farther from the tabs than the main surfaces34a,35a, and36aof the tabs on the main surface side. That is, the wire bonding faces37dof the individual leads37are disposed at a higher level than the main surfaces34a,35a, and36aof the individual tabs are.

In the lead frame38, the plurality of leads37and the first tab34, second tab35, and third tab36much thicker than the leads are integrally formed. They are formed of one contour strip material of copper alloy, for example. The plate thickness of the leads37and that of the tabs can be made different by metal rolling.

As illustrated inFIG. 13andFIG. 14, V-grooves (groove portions)34c,35c, and36care formed at the respective peripheral areas of the main surfaces34a,35a, and36aof the first tab34, second tab35, and third tab36.

Second groove portions38bdeeper than the V-grooves34c,35c, and36care formed in suspending portions38dthat support the outer side portions of the tabs positioned at both ends, of the three tabs.

As illustrated inFIG. 14, a protruding portion38fis formed on the respective side faces of the first tab34, second tab35, and third tab36and in the second groove portions38b. The protruding portions38fcan be formed by crushing or the like.

As a method for varying the thickness of the tabs in the lead frame38, the lead frame38may be formed of two frame materials, different in thickness, as illustrated as a modification inFIG. 15andFIG. 16. That is, the following method may be adopted: the first tab34, second tab35, and third tab36are formed using a thick plate material; the lead frame38is formed using a thin plate material, and then caulking portions38hare formed by caulking to couple together each tab and the lead frame38.

After the lead frame38illustrated inFIG. 11is prepared, die bonding is carried out.

Here, the first semiconductor chips30and the second semiconductor chips31are mounted over the respective tabs with solder43in-between. At this time, of the six semiconductor chips, either the three first semiconductor chips30including a pMISFET32or the three second semiconductor chips31including an nMISFET33are continuously die-bonded. Then, the lead frame38is turned upside down, and the other three semiconductor chips are die-bonded.

As mentioned above, the V-grooves34c,35c, and36care formed at the peripheral areas of the respective main surfaces34a,35a, and36aof the tabs. Therefore, solder43that is melted and runs off during die bonding can be prevented from flowing out by causing the solder43to flow into the V-grooves34c,35c, and36c.

After die bonding, wire bonding is carried out. The electrodes on the main surfaces30aand31aof the semiconductor chips and the corresponding leads37are electrically connected with each other through wires39. At this time, the leads37are disposed at a higher level than the individual tabs as illustrated inFIG. 17. Thus, the wires39can be prevented from being brought into contact with an edge of the main surface of a chip.

As a result, the wires39can be prevented from being short-circuited to a first semiconductor chip30or a second semiconductor chip31.

Thereafter, plastic molding is carried out.

Here, using such sealing resin as epoxy resin, the semiconductor chips, the plurality of wires39, and the like are plastic molded to form the sealing portion44. At this time, plastic molding is carried out so that the back sides34b,35b, and36bof the individual tabs are exposed at the underside of the sealing portion44as illustrated inFIG. 7.

As mentioned above, the protruding portions38fare formed on the side faces of the first tab34, second tab35, and third tab36and in the second groove portions38b. Therefore, bonding power can be enhanced between the sealing resin and each tab.

Thereafter, the dam bars38ein the lead frame38are cut to insulate each lead37from the adjoining leads37.

Thereafter, the outer leads37eare coated with solder plating45to from outer plating. The leads37are cut off from the frame portion38gof the lead frame38, and the outer leads37eare bent and formed (into gull wing shape). This completes the assembly of the HSOP46.

Second Embodiment

FIG. 19is a plan view illustrating an example of the construction of a semiconductor device (with its tab divided into two and for driving a single-phase motor) in a second embodiment of the invention as viewed through its sealing portion;FIG. 20is a rear view illustrating an example of the construction of the back side of the semiconductor device illustrated inFIG. 19, as applied to HSOP; andFIG. 21is an equivalent circuit diagram illustrating an example of the circuitry for driving a single-phase motor in the semiconductor device illustrated inFIG. 19.

The semiconductor device in the second embodiment illustrated inFIG. 19is HSOP47for driving a single-phase motor, and two pMISFETs32and two nMISFETs33are incorporated into the device.FIG. 21is a drawing illustrating an example of an equivalent circuit for driving a single-phase motor. It has two pMISFETs32on the high side and two nMISFETs33on the low side, and drives a motor40in a single phase by the four MISFETs in total. (Refer toFIG. 2for the motor.)

In terms of circuitry, as illustrated inFIG. 19, the HSOP has two sets of circuits for driving, each set composed of a pMISFET32and an nMISFET33, and it drives the motor40in a single phase by these circuits. Therefore, the HSOP47in the second embodiment is also a semiconductor device with p and nMISFETs incorporated together.

The HSOP47has two divided tabs (first tab34and second tab35), and a set of a pMISFET32and an nMISFET33is mounted over each tab. More specific description will be given. A first semiconductor chip30including a pMISFET32and a second semiconductor chip31including an nMISFET33are mounted over the main surface34aof the first tab34; and a first semiconductor chip30including a pMISFET32and a second semiconductor chip31including an nMISFET33are mounted over the main surface35aof the second tab35.

At this time, the two first semiconductor chips30each including a pMISFET32are placed on the high side, and the two second semiconductor chips31each including an nMISFET33are placed on the low side.

The source pads30cformed over the main surfaces30aof the first semiconductor chips30are electrically connected with corresponding leads37bfor source through conductive wire39; the gate pads30dsimilarly formed are electrically connected with corresponding leads37afor gate through conductive wires39. The back sides of the first semiconductor chips30form drain electrodes, and these drain electrodes are electrically connected with the tabs with solder or the like in-between. The tabs and the leads37cfor drain are integrally joined with each other.

Similarly, the source pads31cformed over the main surfaces31aof the second semiconductor chips31are electrically connected with corresponding leads37bfor source through conductive wires39; the gate pads31dsimilarly formed are electrically connected with corresponding leads37afor gate through conductive wires39. The back sides of the second semiconductor chips31from drain electrodes, and these drain electrodes are electrically connected with tabs with solder or the like in-between. The tabs and the leads37cfor drain are integrally joined with each other.

Therefore, the first semiconductor chip30and the second semiconductor chip31over the first tab34share a drain electrode between them over the tab. The first semiconductor chip30and the second semiconductor chip31over the second tab35share a drain electrode between them over the tab. That is, the first tab34and the second tab35are respectively electrically connected with the drains of a pMISFET32and an nMISFET33. The drains of the pMISFETs32and the nMISFETs33are electrically connected with each other through each of the first tab34and the second tab35.

FIG. 19illustrates the disposition (G, S, D) of the plurality of leads37composed of leads37afor gate, leads37bfor source, and leads37cfor drain as an example. However, the disposition of the leads is not limited to that illustrated inFIG. 19.

The HSOP47has a sealing portion44that seals parts of the first tab34, second tab35, and plural leads37, the first semiconductor chips30, and the second semiconductor chips31. As in the HSOP46in the first embodiment, also in the HSOP47, the back sides34band35bof the first tab34and the second tab35are exposed from the sealing portion44as illustrated inFIG. 20.

As in the HSOP46in the first embodiment, also in the HSOP47, each of the first tab34and the second tab35is so formed that it is much thicker than the leads37.

In the semiconductor device (HSOP47) in the second embodiment, the following is implemented in the HSOP47for driving a single-phase motor: a first semiconductor chip30including a pMISFET32and a second semiconductor chip31including an nMISFET33are mounted over each of the first tab34and the second tab35. The drains of the pMISFET32and nMISFET33over each tab are electrically connected with each other. Thus, the HSOP47can be reduced in size. More specific description will be given. Two of four semiconductor chips each including MISFET are placed over each of two divided tabs, and these chips are packaged in one in a compact manner. This makes it possible to reduce the size of the HSOP47for driving a single-phase motor, having a plurality of chips.

The respective back sides34band35bof the first tab34and second tab35that also function as drain terminals are exposed at the underside of the sealing portion44. Further, each tab is so formed that it is thicker than the leads37. Thus, each tab can be provided with a heat sink function to enhance the heat radiating property of the HSOP47.

As a result, the heat radiating property of the HSOP47for driving a single-phase motor, having a plurality of chips can be enhanced.

Other effects obtained by the HSOP47are the same as by the above-mentioned HSOP46, and the repetitive description of them will be omitted.

Third Embodiment

FIG. 22is a plan view illustrating an example of the construction of a semiconductor device (with its tab divided into four and for driving a single-phase motor) in a third embodiment of the invention as viewed through its sealing portion;FIG. 23is a rear view illustrating an example of the construction of the back side of the semiconductor device illustrated inFIG. 22, as applied to HSOP; andFIG. 24is an equivalent circuit diagram illustrating an example of the circuitry for driving a single-phase motor in the semiconductor device illustrated inFIG. 22.

As in the second embodiment, the semiconductor device in the third embodiment illustrated inFIG. 22is HSOP49for driving a single-phase motor, and two pMISFETs32and two nMISFETs33are incorporated into the device.FIG. 24is a drawing illustrating an example of an equivalent circuit for driving a single-phase motor. It has two pMISFETs32on the high side and two nMISFETs33on the low side, and drives a motor40in a single phase by the four MISFETs in total. (Refer toFIG. 2for the motor.)

In terms of circuitry, as illustrated inFIG. 22, the HSOP has four semiconductor chips individually mounted over different tabs. The four semiconductor chips are two first semiconductor chips30each including a pMISFET32and two second semiconductor chips31each including an nMISFET33. The HSOP drives the motor40in a single phase by these circuits. The HSOP49in the third embodiment is also a semiconductor device with p and nMISFETs incorporated together.

The HSOP49has four divided tabs (first tab34, second tab35, third tab36, and fourth tab48), and either a pMISFET32or an nMISFET33is mounted over each tab. The HSOP49in the third embodiment is constructed as follows: first semiconductor chips30each including a pMISFET32are mounted over the main surfaces34aand35aof the first tab34and the second tab35; and second semiconductor chips31each including an nMISFET33are mounted over the main surfaces36aand48aof the third tab36and the fourth tab48.

At this time, the four tabs are arranged in the order of first tab34, third tab36, second tab35, and fourth tab48from either end. Since the pMISFETs32and the nMISFETs33are alternately placed, circuit connection can be easily carried out with respect to the pMISFETs32and the nMISFETs33.

The source pads30cformed over the main surfaces30aof the first semiconductor chips30are electrically connected with corresponding leads37bfor source through conductive wires39; the gate pads30dsimilarly formed are electrically connected with corresponding leads37afor gate through conductive wires39. The back sides of the first semiconductor chips30form drain electrodes, and these drain electrodes are electrically connected with the tabs with solder or the like in-between. The tabs and the leads37cfor drain are integrally joined with each other.

Similarly, the source pads31cformed over the main surfaces31aof the second semiconductor chips31are electrically connected with corresponding leads37bfor source through conductive wire39; the gate pads31dsimilarly formed are electrically connected with corresponding leads37afor gate through conductive wire39. The back sides of the second semiconductor chips31form drain electrodes, and these drain electrodes are electrically connected with the tabs with solder or the like in-between. The tabs and the leads37cfor drain are integrally joined with each other.

FIG. 22illustrates the disposition (G, S, D) of the plurality of leads37composed of leads37afor gate, leads37bfor source, and leads37cfor drain as an example. However, the disposition of the leads is not limited to that illustrated inFIG. 22.

The HSOP49has a sealing portion44that seals parts of the first tab34, second tab35, third tab36, fourth tab48, and plural leads37, the first semiconductor chips30, and the second semiconductor chips31. As in the HSOP46in the first embodiment, also in the HSOP49, the back sides34b,35b,36b, and48bof the first tab34, second tab35, third tab36, and fourth tab48are exposed from the sealing portion44as illustrated inFIG. 23.

As in the HSOP46in the first embodiment, also in the HSOP49, each of the first tab34, second tab35, third tab36, and fourth tab48is so formed that it is much thicker than the leads37.

In the semiconductor device (HSOP49) in the third embodiment, the following is implemented in the HSOP49for driving a single-phase motor: either a first semiconductor chip30including a pMISFET32or a second semiconductor chip31including an nMISFET33is mounted over each of the first tab34, second tab35, third tab36, and fourth tab48. Thus, the HSOP49can be reduced in size. More specific description will be given. Each of four semiconductor chips each including MISFET is placed over each of four divided tabs, and these chips are packaged in one in a compact manner. This makes it possible to reduce the size of the HSOP49for driving a single-phase motor.

The respective back sides34b,35b,36b, and48bof the first tab34, second tab35, third tab36, and fourth tab48that also function as drain terminals are exposed at the underside of the sealing portion44. Further, each tab is so formed that it is thicker than the leads37. Thus, each tab can be provided with a heat sink function to enhance the heat radiating property of the HSOP49.

As a result, the heat radiating property of the HSOP49for driving a single-phase motor, having a plurality of chips can be enhanced.

Other effects obtained by the HSOP49are the same as by the above-mentioned HSOP46, and the repetitive description of them will be omitted.

Up to this point, the invention made by the present inventors has been concretely described based on embodiments of the invention. However, the invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention, needless to add.

An example will be taken. In the above description of the first, second, and third embodiments, the semiconductor device is HSOP with its outer leads37ebent and formed into gull wing shape. The semiconductor device need not be HSOP, and it may be any other semiconductor device, such as SOJ (Small Outline J-leaded Package).

The invention is favorably applicable to an electronic device having a plurality of chips.