Method of manufacturing circuit device

A conductive pattern of a first layer isolated by an isolation trench is formed on a conductive foil, and a plurality of layers of the conductive patterns are formed thereon to create a multilayered wiring structure, and furthermore, a circuit element is mounted and molded with an insulating resin and the back surface of the conductive foil is etched. It is possible to implement a method of manufacturing a circuit device which provides very power saving and is suitable for mass production, then the circuit device having conductive patterns of a multilayered structure are provided.

BACKGROUND OF THE INVENTION

The present invention relates to a method for manufacturing circuit devices, and particularly relates to a method for manufacturing implementing multilayered wiring circuit devices implementing multi layered wiring, that does not require any supporting substrate.

Circuit devices set in electronic equipment are heretofore desired to be made smaller in size, thinner in thickness and lighter in weight because they are used in portable telephones, portable computers, etc.

For example, a semiconductor device will be described as such a circuit device by way of example. As a typical semiconductor device, there is conventionally a packaged semiconductor device sealed by usual transfer-molding. This semiconductor device is mounted on a printed circuit board PS as shown in FIG.19.

In the packaged semiconductor device1, a semiconductor chip2is covered with a resin layer3, and lead terminals4for external connection are led out from side portions of the resin layer3.

Because the lead terminals4are led from the resin layer3to the outside, the whole size of the packaged semiconductor device1is, however, too large to satisfy the request to make it smaller in size, thinner in thickness and lighter in weight.

Therefore, various structures have been developed by various manufacturers in order to make packaged semiconductor devices smaller in size, thinner in thickness and lighter in weight. Recently, the packaged semiconductor devices are developed into Chip Size Packages (CSPs) such as wafer-scale CSPs as large as the chip size, or CSPs a little larger than the chip size.

FIG. 20shows a CSP6which uses a glass epoxy substrate5as a supporting substrate and which is a little larger than the chip size. Here, description will be made on the assumption that a transistor chip T has been mounted on the glass epoxy substrate5.

A first electrode7, a second electrode8and a die pad9are formed on the front surface of the glass epoxy substrate5while a first back-surface electrode10and a second back-surface electrode11are formed on the back surface of the glass epoxy substrate5. The first and second electrodes7and8are electrically connected to the first and second back-surface electrodes10and11via through holes TH respectively. In addition, the bare transistor chip T is firmly fixed to the die pad9. An emitter electrode of the transistor is connected to the first electrode7through a metal fine wire12, and a base electrode of the transistor is connected to the second electrode8through a metal fine wire12. Further, a resin layer13is provided on the glass epoxy substrate5so as to cover the transistor chip T.

The CSP6uses the glass epoxy substrate5to thereby achieve a simple structure extending from the chip T to the back-surface electrodes10and11for external connection, compared with a wafer-scale CSP. Thus, there is a merit that the CSP6can be manufactured inexpensively.

In addition, the CSP6is mounted on a printed circuit board PS as shown in FIG.19. Electrodes and wiring for constituting an electric circuit are provided on the printed circuit board PS, and the CSP6, the packaged semiconductor device1, a chip resistor CR or a chip capacitor CC, etc. are electrically connected and firmly fixed to the printed circuit broad PS.

Then, the circuit constituted on the printed circuit board will be attached to various sets.

Next, a method for manufacturing the CSP will be described with reference toFIGS. 21Ato21D and FIG.22.

First, the glass epoxy substrate5is prepared as a base material (as a supporting substrate), and Cu foils20and21are bonded to both sides of the glass epoxy substrate5through an insulating bonding material respectively (the above step is illustrated in FIG.21A).

Subsequently, the Cu foils20and21corresponding to the first electrode7, the second electrode8, the die pad9, the first back-surface electrode10and the second back-surface electrode11are covered with an etching-proof resist22and patterned. Incidentally, the front surface and the back surface of the glass epoxy substrate5may be patterned separately (the above step is illustrated in FIG.21B).

Subsequently, holes for the through holes TH are formed in the glass epoxy substrate by use of a drill or a laser, and then plated. Thus, the through holes TH are formed. Via the through holes TH, the first and second electrodes7and8are electrically connected to the first and second back-surface electrodes10and11respectively (the above step is illustrated in FIG.21C).

Further, though not shown, the first and second electrodes7and8which will be bonding posts are plated with Ni, while the die pad9which will be a die bonding post is plated with Au. Then, the transistor chip T is die-bonded.

Finally, the emitter electrode and the base electrode of the transistor chip T are connected to the first and second electrodes7and8through the metal fine wires12respectively, and covered with the resin layer13(the above step is illustrated in FIG.21D).

In the above-mentioned manufacturing method, a CSP type electric element using the supporting substrate5is produced. Alternatively, in this manufacturing method, the glass epoxy substrate5may be replaced by a flexible plate as a supporting substrate to produce the CSP type electric element similarly.

On the other hand, a manufacturing method useing a ceramic substrate is shown in the flow chart ofFIG. 22. Aceramic substrate which is a supporting substrate is prepared, and through holes are formed therein. After that, front-surface and back-surface electrodes are printed with conductive paste, and sintered. The following steps up to covering with a resin layer are the same as those in the manufacturing method inFIGS. 21A-21D. However, differently from the flexible sheet or the glass epoxy substrate, the ceramic substrate is very fragile to be chipped easily. Therefore, there is a problem that the ceramic substrate cannot be molded by use of a mold. Thus, the CSP type electric element is produced by potting sealing resin on the ceramic substrate, hardening the sealing resin, polishing the sealing resin to be even, and finally separating the ceramic substrate with the sealing resin individually by use of a dicing apparatus. Also in the case where the glass epoxy substrate is used, there is a fear that the substrate is crushed when it is strongly held by a mold for transfer-molding.

InFIG. 20, the transistor chip T, the connection member7to12, and the resin layer13are essential constituent elements for electric connection with the outside and protection of the transistor. However, it is difficult to provide a circuit element made smaller in size, thinner in thickness and lighter in weight, by using all of such essential elements.

In addition, the glass epoxy substrate5which is a supporting substrate is unnecessary by nature as described above. However, in the manufacturing method, the glass epoxy substrate5cannot be omitted because the glass epoxy substrate5is used as a supporting substrate for bonding electrodes to each other.

Because the glass epoxy substrate5is used, the cost increases. Further, because the glass epoxy substrate5is thick, the circuit element becomes thick. Accordingly, there is a limit in making the circuit element smaller in size, thinner in thickness and lighter in weight.

Further, in the glass epoxy substrate and the ceramic substrate, multilayered wires have to be formed within the substrate. Therefore, the step of forming the through hole for connecting the multi-layered wires is indispensable. Thus, there is a problem that the manufacturing process is prolonged to be unfitted for mass production.

SUMMARY OF THE INVENTION

The invention has been made in consideration of a large number of problems described above and characterized by the steps of preparing a conductive foil and forming an isolation trench having a smaller thickness than that of the conductive foil on the conductive foil in a region excluding a conductive pattern of a first layer, thereby forming the conductive pattern of the first layer, forming plural layers of the conductive pattern on the conductive pattern of the first layer through an interlayer insulating film, incorporating a circuit element into the conductive pattern which is desirable, covering the circuit element and molding a whole surface with an insulating resin, removing the conductive foil in a thick portion where the isolation trench is not provided, and isolating the insulating resin through dicing for each circuit device including the circuit element.

In the invention, the conductive foil forming the conductive pattern is a starting material, and the conductive foil has a support function before the insulating resin is molded and the insulating resin has the support function after the molding. Thus, a multilayered wiring requiring no supporting substrate can be implemented so that the conventional problems can be solved.

Furthermore, the invention is characterized by the steps of preparing a conductive foil and forming plural layers of the conductive pattern through the interlayer insulating films, incorporating a circuit element into the conductive pattern which is desirable, covering the circuit element and molding a whole surface with an insulating resin, removing the conductive foil, and isolating the insulating resin through dicing for each circuit device including the circuit element.

In the invention, furthermore, the conductive foil is a starting material, and the conductive foil has a support function before the insulating resin is molded and the insulating resin has the support function after the molding. Thus, a multilayered wiring requiring no supporting substrate can be implemented so that the conventional problems can be solved.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

First of all, a method of manufacturing a circuit device according to the invention will be described with reference to FIG.1.

The invention shows the method of manufacturing circuit devices including the steps of preparing a conductive foil and forming an isolation trench having a smaller thickness than that of the conductive foil on the conductive foil in a region excluding a conductive pattern of a first layer, thereby forming the conductive pattern of the first layer, forming plural layers of a conductive pattern on the conductive pattern of the first layer through an interlayer insulating film, incorporating a circuit element into the conductive pattern which is desirable, covering the circuit element and molding a whole surface with an insulating resin, removing the conductive foil in a thick portion where the isolation trench is not provided, and separating the insulating resin through dicing for each circuit device.

Although a flow chart shown inFIG. 1is not coincident with the steps described above, the conductive pattern of the first layer is formed in two flow steps of a Cu foil and half etching. In a flow step of forming a multilayered wiring layer, plural layers of the conductive pattern is formed on the conductive foil. A circuit element is fixed to the conductive pattern and the electrode of the circuit element is connected to the conductive pattern in two flow steps of die-bonding and wire-bonding. In a flow step of transfer-molding, molding using the insulating resin is carried out. In a flow step of back-surface Cu foil removing, the conductive foil in the thick portion having no isolation trench is etched. In a flow step of a back-surface treatment, the electrode of the conductive patterns exposed to the back surface are treated. In a flow step of dicing, the insulating resin is subjected to dicing so that the individual circuit elements are separated from each other.

Each step according to the invention will be described below with reference toFIGS. 2to10.

At a first step of manufacturing method of the invention, as shown inFIGS. 2to4, a conductive foil is prepared and an isolation trench having a smaller thickness than that of the conductive foil is formed on the conductive foil in a region except the conductive patterns of a first layer so that the conductive pattern of the first layer is formed.

At the first step, as shown inFIG. 2, a sheet-shaped conductive foil30is first prepared. For the conductive foil30, a material is selected in consideration of the sticking and plating properties of a brazing filler material. For the material, a conductive foil including Cu as a main material, a conductive foil including Al as a main material or a conductive foil including an alloy such as Fe—Ni is employed.

It is preferable that the conductive foil30should have a thickness of about 10 to 300 μm in consideration of subsequent etching. Herein, a copper foil having a thickness of 125 μm (2 ounces) is employed. However, thicknesses of 300 μm or more and 10 μm or less may be basically employed. As will be described below, it is sufficient that an isolation trench31having a smaller thickness than that of the conductive foil30can be formed.

Incidentally, the sheet-like conductive foil30is prepared in the form of a roll wound with a predetermined width, for example, a width of 45 mm. The roll of the conductive foil30may be conveyed for the respective steps which will be described later. Alternatively, the conductive foil30may be prepared in the form of strips each cut in a predetermined dimension, and conveyed for the respective steps which will be described later.

Subsequently, a conductive pattern41of the first layer is formed.

First of all, as shown inFIG. 3, a photoresist (an etching-resistant mask) PR is formed on the Cu foil30, and is patterned to expose the conductive foil30except the regions to be the conductive pattern41. As shown inFIG. 4, then, the conductive foil30is selectively etched through the photoresist PR.

The isolation trench31formed by the etching has a depth of 50-60 μm, for example, and a side surface thereof is roughened. Therefore, bonding to the insulating resin50can be enhanced.

Moreover, while the side wall of the isolation trench31is shown typically straightly, a structure of the side wall is varied depending on a removing method. For the removing step, it is possible to employ wet etching, dry etching, evaporation using a laser and dicing. In case of the wet etching, iron (III) chloride or copper (II) chloride is mainly employed for an etchant. The conductive foil is dipped in the etchant or is showered with the etchant. Since the wet etching is generally carried out non-anisotropically, the side surface has a curved structure.

Furthermore, the dry etching can be carried out anisotropically or non-anisotropically. At the present time, Cu cannot be removed through reactive ion etching but sputtering. Moreover, the etching can be carried out anisotropically or non-anisotropically in accordance with the conditions of the sputtering.

In case of the laser, furthermore, the isolation trench31can be formed by the direct irradiation of a laser beam. In this case, the side surface of the isolation trench31is formed rather straightly.

At a second step of the invention, as shown inFIG. 5A, plural layers of the conductive pattern43are formed on the conductive pattern41of the first layer through an interlayer insulating film42.

In the second step, a multilayered wiring structure can be implemented by providing the interlayer insulating films42and the conductive patterns43. A non-photosensitive thermosetting resin or a photosensitive resist layer is used for the interlayer insulating film42. An epoxy resin and a polyimide resin have been known as the thermosetting resin and are supplied like a liquid or a dry film. A photosensitive epoxy resin, an epoxy acrylate resin and a polyimide resin have been known as the resist layer, and similarly, are supplied like a liquid or a dry film.

At the second step, as shown inFIG. 5B, the conductive pattern41of the first layer is first subjected to chemical polishing, thereby cleaning and roughening the surface, Next, the isolation trench31and the conductive pattern41of the first layer are entirely covered with a thermosetting resin and are heated and cured to form the interlayer insulating film42having a flat surface. Furthermore, a via hole44having a diameter of about 100 μm is formed on the desirable conductive pattern41of the first layer by using a carbon dioxide laser in the interlayer insulating film42. Then, an excimer laser is irradiated to remove an etching residue. Subsequently, a copper plated layer45is formed over the entire interlayer insulating film42and the via hole44. The copper plated layer45is formed by first carrying out electroless plating to have a small thickness of about 0.5 μm over the entire surface and then performing electroplating to have a thickness of about 20 μm such that it is not disconnected due to the step of the via hole44. The copper plated layer45is patterned by using a photoresist so that the conductive pattern43of a second layer is formed.

By repeating the steps described above, plural layers of the conductive pattern43can be provided on the conductive foil30through the interlayer insulating films42. In addition, since plural layers of the conductive pattern43is supported on the conductive foil30forming the conductive pattern41of the first layer, it has such a feature that a multilayered wiring structure can be formed without using a supporting substrate such as a glass epoxy substrate.

Moreover, when the interlayer insulating film42is formed by a photosensitive resist layer at the step, the interlayer insulating film42in a portion photosensitized in a well-known photoresist process is removed with an alkali based solvent, thereby forming the via hole44. Other steps are the same as those in the process of forming the interlayer insulating film42with a thermosetting resin.

At a third step of the invention, as shown inFIG. 6, a circuit element46is incorporated in the desirable conductive pattern43.

A semiconductor element such as a transistor, a diode or an IC chip and a passive element such as a chip capacitor or a chip resistor can be used for the circuit element46. Moreover, a face down semiconductor element such as a CSP or a BGA can also be mounted, which increases a thickness of the circuit device

A bare transistor chip as a semiconductor element46A is die-bonded to a conductive pattern43A, and an emitter electrode and a conductive pattern43B, and a base electrode and the conductive pattern43B are connected through a metal fine wire47fixed by thermal compression ball bonding or ultrasonic wedge bonding. Moreover, a passive element46B such as a chip capacitor is fixed to the conductive pattern43with a brazing filler material such as a solder or a conductive paste.

At a fourth step of the invention, as shown inFIG. 7, the circuit element46is covered and entirely molded with an insulating resin50. In particular, a plurality of circuit devices provided in the conductive foil30are molded by one common mold.

At the fourth step, the insulating resin50completely covers the circuit elements46A and46B and the conductive pattern43, and the conductive pattern43is supported through the insulating resin50.

Moreover, the fourth step can be implemented by transfer-molding, injection-molding, potting or dipping. For a resin material, a thermosetting resin such as an epoxy resin can be applied to the transfer-molding or the potting, and a polyimide resin and a thermoplastic resin such as polyphenylene sulfide can be applied to the injection-molding.

The thickness of the insulating resin50covering the surface of the conductive pattern43is regulated such that a depth of about 100 μm from the top of the metal fine wire47of the circuit element46can be covered. The thickness can be increased or reduced in consideration of strength of the circuit device.

The fourth step features that the conductive foil30to be the conductive pattern41of the first layer acts as a supporting substrate until the insulating resin50is covered. While the supporting substrate5which is not substantially required has been employed to form conductive paths7to11as shown inFIG. 19in the conventional art, the conductive foil30to be the supporting substrate is a material required for an electrode material in the invention. For this reason, there is an advantage that a component can be omitted as much as possible to carry out a work and a cost can also be reduced.

Moreover, the isolation trench31is formed to have a smaller thickness than that of the conductive foil30. Therefore, the conductive foil30is not individually isolated as the conductive pattern41of the first layer. Accordingly, the conductive foil30including the isolation trenches31can be integrally treated as a sheet-shaped conductive foil, and a work for conveying to the mold and mounting onto the mold can be carried out very easily when molding the insulating resin50.

At a fifth step of the invention, as shown inFIG. 8, the conductive foil30in a thick portion having no isolation trench31is removed.

At the fifth step, the back surface of the conductive foil30is removed chemically and/or physically and is isolated as the conductive pattern41. The fifth step is carried out by polishing, grinding, etching or metal evaporation of a laser.

In an experiment, the entire back surface of the conductive foil30is ground by about 60-70 μm by means of a polishing device or a grinding device and the insulating film42filled within the isolation trench is exposed from the isolation trench31s. A surface to be exposed is shown in a dotted line of FIG.7. As a result, the isolation is carried out to form the conductive pattern41of the first layer having a thickness of about 50 μm. Moreover, the entire back surface of the conductive foil30may be subjected to wet etching just before the insulating film42filled within the isolation trench31is exposed, and the entire surface may be then ground by the polishing or grinding device to expose the insulating film42filled within the isolation trench31. Furthermore, the entire back surface of the conductive foil30may be subjected to the wet etching up to the dotted line, thereby exposing the insulating film42filled within the isolation trench31.

As a result, the back surface of the conductive pattern41of the first layer is exposed to the insulating film42filled within the isolation trench31. More specifically, the surface of the insulating film42filled with the isolation trench31and that of the conductive pattern41of the first layer are substantially coincident with each other. In the circuit device according to the invention, therefore, a difference in level between the back surface of the supporting substrate5and the back-surface electrodes10and11is not provided shown in FIG.21D. Therefore, horizontal movement can be exactly carried out by the surface tension of a solder during mounting so that self-alignment can be obtained.

Furthermore, the back-surface treatment of the conductive foil30is carried out to obtain a final structure shown in FIG.9. More specifically, if necessary, the exposed conductive pattern41is covered with a conductive material such as a solder and/or Ag-plating to form the back-surface electrode51. Thus, a circuit device60is finished. It is preferable that the conductive pattern41requiring no back-surface electrode51should be covered with a protective film52such as an epoxy resin based resist material.

At a sixth step according to the invention, as shown inFIG. 10, each circuit device including each circuit element46is separated performing the dicing.

At the sixth step, a large number of circuit devices60are formed on the conductive foil30in a matrix and a black pattern indicates the conductive pattern41of the first layer. A white portion indicates the isolation trench31among the conductive patterns41and among the circuit devices60. The layers of the conductive pattern43and the interlayer insulating film42are provided under the conductive pattern41, and the circuit element46is mounted on the conductive pattern43to be an uppermost layer and is covered with the insulating resin50. That is,FIG. 10shows the state that the circuit device60shown inFIG. 9is turned over.

At the sixth step, a large number of circuit devices60supported integrally with the insulating resin50are bonded to a dicing sheet62and are adsorbed into the mounting table of a dicing device in vacuum, and the insulating film41filled within the isolation trench31is diced along a dicing line56between the circuit devices60through a dicing blade55and is thus separated into the individual circuit device60.

At the sixth step, the dicing blade55completely cuts the insulating resin50to carry out the dicing in a cutting depth reaching the surface of the dicing sheet62thus completely separated into the individual circuit device60. During the dicing, an alignment mark61provided on the inside of a frame-shaped pattern57around each block previously provided at the first step described above is recognized and the dicing is carried out on the basis of the alignment mark61. The dicing is carried out along all the dicing lines56in a vertical direction, and the mounting table is then rotated by 90 degrees and the dicing is carried out along the dicing lines56in a transverse direction, which has been well known.

At the sixth step, moreover, only the interlayer insulating film42filled in the isolation trench31and the insulating resin50are laminated in the dicing line56. Therefore, the dicing blade55does not cut the conductive patterns41and43, resulting in less abrasion. Furthermore, metal burrs are not generated and the dicing can be carried out to obtain a very accurate external shape.

Further, even after this step, the dicing sheet62prevents the circuit devices from being separated individually. Working can be done efficiently also in the following taping step. That is, the circuit devices supported integrally on the dicing sheet62are determined as to whether they are good products or not. Thus, only good products can be withdrawn from the dicing sheet62and received into reception holes of a carrier tape by a suction collet. Accordingly, there is a feature that even very small circuit devices are not once separated individually till they are taped.

First of all, a method of manufacturing a circuit device according to the invention will be described with reference to FIG.11.

The invention comprises the steps of preparing a conductive foil and forming plural layers of the conductive pattern through the interlayer insulating films, incorporating a circuit element into the conductive pattern which is desirable, covering the circuit element and molding a whole surface with an insulating resin, removing the conductive foil, and isolating the insulating resin through dicing for each circuit device including the circuit element.

Although a flow chart shown inFIG. 11is not coincident with the steps described above, a conductive foil supporting a multilayered wiring layer to be formed thereon is prepared in a flow step of a Cu foil. Plural layers of a conductive pattern is formed on the conductive foil in a flow step of forming the multilayered wiring layer. A circuit element is fixed to the conductive pattern and the electrode of the circuit element is connected to the conductive pattern in two flow steps of die-bonding and wire-bonding. In a flow step of transfer-molding, the molding using an insulating resin is carried out. In a flow step of Cu foil removing, the conductive foil is etched. In a flow step of a back-surface treatment, the electrode of the conductive patterns exposed to a back surface is treated. In a flow step of dicing, the insulating resin is subjected to dicing and is separated into an individual circuit element.

Each step according to the invention will be described below with reference toFIGS. 12to18.

At a first step of the invention, as shown inFIG. 12, a conductive foil130is prepared.

At the first step, as shown inFIG. 12, a sheet-shaped conductive foil130is first prepared. For the conductive foil130, a material is selected in consideration of the sticking and plating properties of a brazing filler material. For the material, a conductive foil including Cu as a main material, a conductive foil including Al as a main material or a conductive foil including an alloy such as Fe—Ni is employed.

It is preferable that the conductive foil130should have a thickness of about 10 to 300 μm in consideration of subsequent etching. Herein, a copper foil having a thickness of 125 μm (2 ounces) is employed. However, thicknesses of 300 μm or more and 10 μm or less may be basically employed.

Incidentally, the sheet-like conductive foil30is prepared in the form of a roll wound with a predetermined width, for example, a width of 45 mm. The roll of the conductive foil30may be conveyed for the respective steps which will be described later. Alternatively, the conductive foil30may be prepared in the form of strips each cut in a predetermined dimension, and conveyed for the respective steps which will be described later.

At a second step of the invention, as shown inFIG. 13A, a plurality of layers of conductive patterns143is formed on the conductive foil130through the interlayer insulating film142.

In the second step, a multilayered wiring structure can be implemented by providing the interlayer insulating films142and the conductive patterns143. A non-photosensitive thermosetting resin or a photosensitive resist layer is used for the interlayer insulating film142. An epoxy resin and a polyimide resin have been known as the thermosetting resin and are supplied like a liquid or a dry film. A photosensitive epoxy resin, an epoxy acrylate resin and a polyimide resin have been known as the resist layer, and similarly, are supplied like a liquid or a dry film.

At the second step, as shown inFIG. 13B, the conductive foil130is first subjected to chemical polishing, thereby cleaning and roughening the surface. Next, the conductive film131is entirely covered with a thermosetting resin over the conductive foil130and is heated and cured to form the interlayer insulating film142having a flat surface. Furthermore, a via hole144having a diameter of about 100 μm is formed on the conductive film131by using a carbon dioxide laser in the interlayer insulating film142. Then, an excimer laser is irradiated to remove an etching residue. Subsequently, a copper plated layer145is formed over the whole interlayer insulating film142and the via hole144. The copper plated layer145is formed by first carrying out electroless plating to have a small thickness of about 0.5 μm over the whole surface and then performing electroplating to have a thickness of about 20 μm such that it is not disconnected due to the step of the via hole144. The copper plated layer145is subjected to patterning by using a photoresist so that the conductive pattern143of a second layer is formed.

By repeating the steps described above, a plurality of layers of the conductive pattern143can be provided on the conductive foil130through the interlayer insulating film142. In addition, since the layers of conductive pattern143are supported on the conductive foil130, it has such a feature that a multilayered wiring structure can be formed without using a supporting substrate such as a glass epoxy substrate.

Moreover, when the interlayer insulating film142is formed by a photosensitive resist layer at the second step, the interlayer insulating film142in a portion photosensitized in a well-known photoresist process is removed with an alkali solvent, thereby forming the via hole144. Other steps are the same as those in the process of forming the interlayer insulating film142with a thermosetting resin.

At a third step of the invention, as shown inFIG. 14, a circuit element146is incorporated in the desirable conductive pattern143.

A semiconductor element such as a transistor, a diode or an IC chip and a passive element such as a chip capacitor or a chip resistor can be used for the circuit element146. Moreover, a face down semiconductor element such as a CSP or a BGA can also be mounted, which increases a thickness of the circuit device.

A bare transistor chip as a semiconductor element146A is die-bonded to a conductive pattern143A, and an emitter electrode and a conductive pattern143B, and a base electrode and the conductive pattern143B are connected through a metal fine wire147fixed by thermal compression ball bonding or ultrasonic wedge bonding. Moreover, a passive element146B such as a chip capacitor is fixed to the conductive pattern143with a brazing filler material such as a solder or a conductive paste.

At a fourth step of the invention, as shown inFIG. 15, the circuit element146is covered and entirely molded with an insulating resin150. In particular, a plurality of circuit devices provided in the conductive foil130are molded by one common mold.

At the fourth step, the insulating resin150completely covers the circuit elements146A and146B and the conductive pattern143, and the conductive pattern143is supported through the insulating resin150.

Moreover, the fourth step can be implemented by transfer-molding, injection-molding, potting or dipping. For a resin material, a thermosetting resin such as an epoxy resin can be applied to the transfer-molding or the potting, and a polyimide resin and a thermoplastic resin such as polyphenylene sulfide can be applied to the injection-molding.

The thickness of the insulating resin150covering the surface of the conductive patter143is regulated such that a depth of about 100 μm from the top of the metal fine wire147of the circuit element146can be covered. The thickness can be increased or reduced in consideration of strength of the circuit device.

The fourth step features that the conductive foil130acts as a supporting substrate until the insulating resin150is covered. While the supporting substrate5which is not substantially required has been employed to form conductive paths7to11as shown inFIG. 20in the conventional art, the conductive foil130to be the supporting substrate is a material required for an electrode material in the invention. For this reason, there is an advantage that a component can be omitted as much as possible to carry out a work and a cost can also be reduced. Accordingly, the sheet-shaped conductive foil130can be treated integrally and a work for conveying to the mold and mounting onto the mold can be carried out very easily when molding the insulating resin150.

At a fifth step of the invention, as shown inFIG. 16, the conductive foil130is removed.

At the fifth step, the whole conductive foil130is removed chemically and/or physically and the conductive pattern143of the multilayered wiring is separated from the conductive foil130. The fifth step is carried out by polishing, grinding, etching or metal evaporation of a laser.

More specifically, the entire back surface of the conductive foil130is ground by about 60-70 μm by means of a polishing device or a grinding device and a residual portion is removed chemically by the wet etching, thereby exposing the copper plated layer145forming a back-surface electrode. Moreover, the whole surface of the conductive film130may be subjected to the wet etching, thereby exposing the copper plated layer145forming the back-surface electrode.

As a result, the back surface of the conductive pattern143of the first layer is exposed to the insulating resin150. In the circuit device according to the invention, therefore, a difference in level between the back surface of the supporting substrate5and the back surface electrodes10and11is not provided shown in FIG.20. Therefore, horizontal movement can be exactly carried out by the surface tension of a solder during mounting so that self-alignment can be obtained.

Furthermore, the back-surface treatment of the circuit device160is carried out to obtain a final structure shown in FIG.17. More specifically, if necessary, the exposed conductive film131is covered with a conductive material such as a solder and/or Ag-plating to form the back-surface electrode151. Thus, a circuit device160is finished. It is preferable that the conductive pattern143requiring no back-surface electrode151should be covered with a protective film such as an epoxy resin based resist material.

At a sixth step according to the invention, as shown inFIG. 18, each circuit device including each circuit element146is separated through performing the dicing.

At the sixth step, a large number of circuit devices160are formed in a matrix and a black pattern indicates the conductive pattern143of the first layer (which is not actually shown). A white portion indicates the interlayer insulating film142. The conductive pattern143of the layers and the interlayer insulating film142are provided under the conductive pattern143, and the circuit element146is mounted on the conductive pattern143to be an uppermost layer and is covered with the insulating resin150. That is,FIG. 18shows the state the circuit device160shown inFIG. 17is turned over.

At the sixth step, a large number of circuit devices160supported integrally with the insulating resin150are bonded to a dicing sheet162and are adsorbed into the mounting table of a dicing device in vacuum, and the insulating resin150is diced along a dicing line156between the circuit devices160through a dicing blade155and is separated into the individual circuit device160.

At the sixth step, the dicing blade155completely cuts the insulating resin150to carry out the dicing in a cutting depth reaching the surface of the dicing sheet162so that the insulating resin50is completely separated for the individual circuit device160. During the dicing, an alignment mark161provided on the inside of a frame-shaped pattern157around each block previously provided at the first step described above is recognized and the dicing is carried out on the basis of the alignment mark161. The dicing is carried out along all the dicing lines156in a vertical direction, and the mounting table is then rotated by 90 degrees and the dicing is carried out along the dicing lines56in a transverse direction, which has been well known.

At the sixth step, moreover, only the interlayer insulating film142and the insulating resin150are laminated in the dicing line156. Therefore, the dicing blade155does not cut the conductive pattern143, resulting in less abrasion. Furthermore, a metal spew is not generated and the dicing can be carried out to obtain a very accurate external shape.

Further, even after this step, the dicing sheet62prevents the circuit devices from being separated individually. Working can be done efficiently also in the following taping step. That is, the circuit devices supported integrally on the dicing sheet62are determined as to whether they are good products or not. Thus, only good products can be withdrawn from the dicing sheet62and received into reception holes of a carrier tape by a suction collet. Accordingly, there is a feature that even very small circuit devices are not once separated individually till they are taped.

According to the invention, the conductive foil itself to be the material of the conductive pattern is caused to function as the supporting substrate, the whole body is supported on the conductive foil before the formation of the isolation trench, the mounting of the circuit element or the coating of the insulating resin, and furthermore, the insulating resin is caused to function as the supporting substrate when the conductive foil is to be isolated as each conductive pattern. Accordingly, it is possible to manufacture the circuit element, the conductive foil and the insulating resin at a minimum. As described in the conventional example, it is not necessary to use the supporting substrate in order to originally constitute the circuit device. Consequently, a cost can also be reduced.

According to the invention, moreover, the conductive foil itself to be the material of the conductive pattern is caused to function as the supporting substrate, the whole body is supported on the conductive foil before the mounting of the circuit element or the coating of the insulating resin, and furthermore, the insulating resin is caused to function as the supporting substrate when the conductive foil is to be removed. Accordingly, it is possible to manufacture the circuit element, the conductive foil, the conductive pattern and the insulating resin at a minimum. As described in the conventional example, it is not necessary to use the supporting substrate in order to originally constitute the circuit device. Consequently, a cost can also be reduced.

In the invention, furthermore, the layers of the conductive patterns can be formed on the conductive pattern. In addition, the conductive pattern is supported with the conductive foil or the insulating resin during the manufacturing process. Therefore, a conventional support insulating substrate can be omitted. As a result, a small-sized circuit device can also have a multilayered wiring structure built therein and a supporting substrate thereof can also be omitted. Therefore, it is possible to mass produce a very thin small-sized circuit device.

Furthermore, there is an advantage that the dicing line can be recognized early and reliably by using the alignment mark at the dicing step. In the dicing, only the interlayer insulating film and the insulating resin layer are cut and the conductive pattern is not cut. Consequently, the lifetime of the dicing blade can be prolonged and a metal spew can be prevented from being generated by cutting the conductive foil.

As is apparent fromFIG. 22, finally, the step of forming a through hole and the step of printing a conductor (in a ceramic substrate) can be omitted. Therefore, there is an advantage that the manufacturing process can be shortened considerably as compared with the conventional art and all the steps can be built in. Moreover, a frame mold is never required so that the manufacturing method can give a very short time limit of delivery.