DISPLAY PANEL AND ELECTRONIC DEVICE

A display panel and an electronic device are disclosed. The display panel includes a display area and a bending area located in one side of the display area. A first via hole is defined in a second inorganic layer of the display panel in the bending area. The first via hole penetrates the second inorganic layer and part of the first inorganic layer, so that an area of the first inorganic layer corresponding to the first via hole retain a certain thickness of whole film layer to protect a first transparent substrate, thereby solving the problem of local mura occurring in the position near the bending area in the existing display panel.

FIELD OF INVENTION

The present disclosure relates to the field of display technology, and more particularly, to a display panel and an electronic device.

BACKGROUND OF INVENTION

With the development of display technology, the market demand for display panels with high screen-to-body ratios is becoming more and more urgent. The display panel is developing towards full screen, thinness, and light weight, and the realization of full screens is inseparable from under-screen camera technology. As the name suggests, the under-screen camera technology means to place a front camera under a display panel. The placement of the front camera under the display panel is not difficult, but the difficulty is how to solve the problem of light transmittance in an area of the under-screen camera. In order to effectively enhance the transmittance of the area of the under-screen camera, substrate material of the display panel may be selected from clear polyimide (CPI). However, the clear polyimide has the problems of large thermal stress, water absorption, and large thermal expansion coefficient, which may lead to the occurrence of local mura in the position near a bending area of the display panel.

Therefore, there is a requirement for solving a problem of local mura occurring in the position near the bending area of the existing display panel.

SUMMARY OF INVENTION

Technical Problem

A display panel and an electronic device are disclosed in the present disclosure to solve the technical problem of local mura occurring in the position near the bending area of the existing display panel.

Technical Solutions

In order to solve the aforementioned problem, the technical solutions are disclosed in embodiments of the present disclosure as below:

A display panel is disclosed in the embodiments of the present disclosure, wherein the display panel includes a display area and a bending area located in one side of the display area, wherein the display panel further includes:a first transparent substrate;a first inorganic layer located on one side of the first transparent substrate;a semiconductor layer disposed on one side of the first inorganic layer away from the first transparent substrate; anda second inorganic layer covering on the semiconductor layer and the first inorganic layer;wherein a first via hole is defined in the second inorganic layer in the bending area, and the first via hole penetrates the second inorganic layer and part of the first inorganic layer.

In the display panel disclosed in the embodiments of the present disclosure, the first inorganic layer includes at least one silicon oxide layer and at least one silicon nitride layer.

In the display panel disclosed in the embodiments of the present disclosure, the first inorganic layer includes a first silicon nitride layer covering on the first transparent substrate and a first silicon oxide layer covering one side of the first silicon nitride layer away from the first transparent substrate, and the first via hole penetrates part or all of the first silicon oxide layer to expose the first silicon nitride layer.

In the display panel disclosed in the embodiments of the present disclosure, the first inorganic layer further includes a second silicon nitride layer covering one side of the first silicon oxide layer away from the first silicon nitride layer, and the first via hole further penetrates the second silicon nitride layer.

In the display panel disclosed in the embodiments of the present disclosure, the first inorganic layer includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer, and a second silicon nitride layer which are stacked on the first transparent substrate in order, and the first via hole penetrates the second silicon nitride layer and the second silicon oxide layer to expose the first silicon nitride layer.

In the display panel disclosed in the embodiments of the present disclosure, a thickness of the first silicon oxide layer is smaller than a thickness of the second silicon oxide layer.

In the display panel disclosed in the embodiments of the present disclosure, the first transparent substrate is provided with a plurality of first protrusions in an area corresponding to the first via hole.

In the display panel disclosed in the embodiments of the present disclosure, a surface of the first inorganic layer exposed by the first via hole is provided with a plurality of second protrusions.

In the display panel disclosed in the embodiments of the present disclosure, a thickness of the first inorganic layer exposed by the first via hole ranges from 1000 angstroms to 5000 angstroms.

In the display panel disclosed in the embodiments of the present disclosure, the display panel further includes a function area disposed adjacent to the display area and a first thin film transistor and a second thin film transistor which are disposed in the display area, and the first thin film transistor is disposed close to the function area, wherein the display panel further includes:an electrically conductive electrode layer disposed on one side of the first thin film transistor and the second thin film transistor away from the first transparent substrate, wherein a first pixel electrode is formed in the function area, a second pixel electrode is formed in the display area, the first pixel electrode is connected with the first thin film transistor, and the second pixel electrode is connected with the second thin film transistor.

In the display panel disclosed in the embodiments of the present disclosure, a bridge layer is further disposed between the first thin film transistor and the electrically conductive electrode layer, the bridge layer forms a first bridge electrode in the function area and a second bridge electrode in the display area, the first pixel electrode is connected with the first thin film transistor through the first bridge electrode, and the second pixel electrode is connected with the second thin film transistor through the second bridge electrode.

In the display panel disclosed in the embodiments of the present disclosure, the second inorganic layer includes a gate insulating layer and an interlayer insulating layer which are stacked in order, and the gate insulating layer is disposed to face the semiconductor layer, the semiconductor layer forms a channel region of the first thin film transistor and a channel region of the second thin film transistor and a source region and a drain region located on both sides of the channel region in the display area, and the gate insulating layer covers on the semiconductor layer and the first inorganic layer, wherein the display panel further includes:a gate layer disposed on the gate insulating layer, wherein the gate layer forms a gate of the first thin film transistor and a gate of the second thin film transistor in the display area, and forms a first signal transfer line in the bending area, wherein the interlayer insulating layer covers on the gate layer and the gate insulating layer, the interlayer insulating layer is patterned to form the first via hole, and to form a second via hole in the display area;a first source/drain layer disposed on the interlayer insulating layer, wherein the first source/drain layer forms a first source and a first drain of the first thin film transistor and a first source and a first drain of the second thin film transistor in the display area, and forms a second signal transfer line in the bending area;a first planarization layer covering on the first source/drain layer and the interlayer insulating layer, and filling the first via hole;a second source/drain layer disposed on the first planarization layer, wherein the second source/drain layer forms a second source of the first thin film transistor and a second source of the second thin film transistor in the display area, and forms a plurality of binding lines in the bending area;a second planarization layer covering on the second source/drain layer and the first planarization layer, wherein the bridge layer is disposed on the second planarization layer;a third planarization layer covering on the bridge layer and the second planarization layer, wherein the electrically conductive electrode layer is disposed on the third planarization layer;wherein the gate is disposed corresponding to the channel region, the first source is connected with the source region, the first drain is connected with the drain region, the second source is connected with the first drain, the first bridge electrode and the second bridge electrode are respectively connected with the corresponding second source, the first signal transfer line is connected with the second signal transfer line, and the binding lines are connected with the second signal transfer line.

An electronic device is also disclosed in the embodiments of the present disclosure, wherein the electronic device includes the display panel in one of the aforementioned embodiments.

Beneficial Effect

In the display panel and the electronic device disclosed in the present disclosure, the display panel includes the first inorganic layer, the second inorganic layer, and the second inorganic layer which are stacked on the first transparent substrate. A first via hole is defined in the second inorganic layer in the bending area of the display panel. The first via hole penetrates the second inorganic layer and part of the first inorganic layer, so that an area of the first inorganic layer corresponding to the first via hole retains a certain thickness of whole film layer to protect the first transparent substrate and avoids the influences of water vapor and the etching process of the first via hole on the first transparent substrate. Accordingly, the problem that mura occurs near the bending area due to the exposed first transparent substrate is avoided, and thus the problem of local mura occurring in the position near the bending area in the existing display panel is solved.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The description of each embodiment below refers to respective accompanying drawing(s), so as to illustrate exemplarily specific embodiments of the present disclosure that may be practiced. Directional terms mentioned in the present disclosure, such as “upper”, “lower”, “front”, “back”, “left”, “right”, “inner”, “outer”, “side”, etc., are only directions by referring to the accompanying drawings, and thus the directional terms are used to describe and understand the present disclosure, but the present disclosure is not limited thereto. In the drawings, structurally similar units are labeled by the same reference numerals. In the drawings, for understanding and ease of description, the thickness of some layers and areas is exaggerated. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto.

References are made toFIG.1toFIG.5.FIG.1is a top view of a schematic structural diagram of a display panel disclosed in the embodiments of the present disclosure.FIG.2is a first section view of a schematic structural diagram of a display panel disclosed in the embodiments of the present disclosure.FIG.3is a partial section view of the schematic structural diagram of the display panel inFIG.2.FIG.4andFIG.5are detailed views of a first via disclosed in the embodiments of the present disclosure. The display panel100includes a display area AA, a function area FA arranged adjacent to the display area AA, and a bending area PA located in one side of the display area AA. The bending area PA can be bent to a back of the display panel100to achieve narrow bezel or no bezel. The function area FA may be located at any position in the display area AA. The function area FA can be configured for realizing various functions such as under-screen fingerprint recognition, face recognition, under-screen camera, and can also be configured for displaying, thereby achieving a real full screen.

Specifically, the display panel100further includes a first transparent substrate11, a first inorganic layer12, a semiconductor layer50, and a second inorganic layer20. The first inorganic layer12is located on one side of the first transparent substrate11, and the semiconductor layer50is disposed on one side of the first inorganic layer12away from the first transparent substrate11. The second inorganic layer20covers on the semiconductor layer50and the first inorganic layer12. A first via hole21is defined in the second inorganic layer20in the bending area PA, and the first via hole21penetrates through the second inorganic layer20and part of the first inorganic layer12.

The material of the first transparent substrate11includes clear polyimide (CPI), and the like. The clear polyimide has higher transmittance than yellow polyimide (YPI). Therefore, the use of the clear polyimide can improve the light transmittance of the function area FA. However, the use of the clear polyimide may also lead to many undesirable results. For example, due to high water vapor transmittance of the clear polyimide, the water vapor may enter into the first transparent substrate11when manufacturing the first via hole21. For another example, large thermal stress of the clear polyimide may cause the stress in the bending area PA to expand to the display area AA, thereby resulting in the occurrence of mura in the display area AA near the bending area PA.

In the present disclosure, the first via hole21penetrates part of the first inorganic layer12. That is, the first via hole21penetrates the part of the first inorganic layer12between the semiconductor layer50and the first transparent substrate11, so that the first inorganic layer12with a certain thickness on the first transparent substrate11corresponding to the first via hole21is retained. That is, the first via hole21exposes the first inorganic layer12with a certain thickness. The material of the first inorganic layer12includes one of inorganic materials such as silicon oxide (SiOx) and silicon nitride (SiNx). In the present embodiment, the first inorganic layer12may be formed of single-layer silicon nitride. Silicon nitride has excellent ability to block water vapor. Therefore, the first inorganic layer12with a certain thickness on the first transparent substrate11can protect the first transparent substrate11, thereby avoiding mura caused by the first transparent substrate11used of the clear polyimide.

The film layer structure of each area on the display panel100may be described in detail as below.

The display panel100includes the first transparent substrate11, the second inorganic layer20disposed on one side of the first transparent substrate11, a first thin film transistor T1and a second thin film transistor T2disposed in the second inorganic layer20, and an electrically conductive electrode layer30disposed on one side of the first thin film transistor T1and the second thin film transistor T2away from the first transparent substrate11.

Optionally, the display panel100further includes a third inorganic layer14and a second transparent substrate13. The third inorganic layer14is located on one side of the first transparent substrate11away from the first inorganic layer12, and the second transparent substrate13is located on one side of the third inorganic layer14away from the first transparent substrate11. The material of the second transparent substrate13is equal to the material of the first transparent substrate11, and the material of the third inorganic layer14is equal to the material of the first inorganic layer12, thereby achieving excellent barrier effect against water vapor.

Optionally, both the first transparent substrate11and the second transparent substrate13may be formed by wet film coating, preforming high vacuum dry (HVCD) to remove the solvent after the wet film coating is completed, and then curing the films. High vacuum dry can be used under the conditions of 40° C. to 80° C. and pressures of 0-10 pa for 250 seconds to 550 seconds. Curing can be carried out at a temperature of 400° C. to 450° C. for 30 minutes.

The second inorganic layer20includes a gate insulating layer22and an interlayer insulating layer23which are stacked in order, and the gate insulating layer22is disposed to face the semiconductor layer50.

The display panel100is provided with the first thin film transistor T1and the second thin film transistor T2in the second inorganic layer20of the display area AA. The first thin film transistor T1and the second thin film transistor T2are disposed on the same layer, and the first thin film transistor T1is disposed close to the function area FA.

The electrically conductive electrode layer30is disposed on one side of the first thin film transistor T1and the second thin film transistor T2away from the first transparent substrate11. The electrically conductive electrode layer30forms a first pixel electrode31in the function area FA and a second pixel electrode32in the display area AA. The first pixel electrode31is connected with the first thin film transistor T1, and the second pixel electrode32is connected with the second thin film transistor T2.

Optionally, a bridge layer40is further disposed between the first thin film transistor T1and the electrically conductive electrode layer30. The bridge layer40forms a first bridge electrode41in the function area FA and a second bridge electrode42in the display area AA. The first bridge electrode41extends from the function area FA to the display area AA and is connected to the first thin film transistor T1. The first pixel electrode31is connected to the first thin film transistor T1through the first bridge electrode41, and the second pixel electrode32is connected to the second thin film transistor T2through the second bridge electrode42.

Specifically, the display panel100further includes a gate layer60, a first source/drain layer70, a second source/drain layer80, and a multilayer planarization layer. The semiconductor layer50is disposed on the first inorganic layer12. Optionally, a buffer layer15may be further disposed between the first inorganic layer12and the semiconductor layer50, and the semiconductor layer50is disposed on the buffer layer15. The material of the buffer layer15may include inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON). The buffer layer15can prevent unexpected impurities or pollutants (e.g., moisture, oxygen, etc.) from diffusing from the first transparent substrate11to devices that may be damaged by these impurities or pollutants, and can also provide a flat top surface.

The semiconductor layer50forms a channel region51of the first thin film transistor T1, a channel region51of the second thin film transistor T2, and a source region52and drain region53on both sides of the channel region51in the display region AA. The gate insulating layer22covers on the semiconductor layer50and the first inorganic layer12. Certainly, if the display surface100further includes the buffer layer15, the gate insulating layer22covers on the semiconductor layer50and the buffer layer15.

The gate layer60is disposed on the gate insulating layer22. The gate layer60forms a gate61of the first thin film transistor T1and a gate61of the second thin film transistor T2in the display area AA, and the gates61are disposed corresponding to the channel regions51. Certainly, the gate layer60can further form signal lines such as gate scanning lines63in the display area AA. The gate layer60also forms a first signal transfer line62in the bending area PA, which is connected with the gate scanning line63and is configured to provide scanning signals to the gate61to control the cut off of the corresponding first thin film transistor T1and the second thin film transistor T2.

The interlayer insulating layer23covers on the gate layer60and the gate insulating layer22, and the interlayer insulating layer23is patterned to form the first via hole21in the bending area PA and the second via hole231in the display area AA.

The first via hole21includes a first sub-hole211and a second sub-hole212, and an opening of the first sub-hole211is larger than an opening of the second sub-hole212. The first sub-hole211and the second via231are formed under the same process conditions. The first sub-hole211and the second via hole231both penetrate the interlayer insulating layer23and part of the gate insulating layer22. The second via hole231exposes the corresponding source region52and the drain region53, as shown inFIG.4. Certainly, while forming the first sub-hole211and the second via231, a third via232is further formed in the bending area PA, and the third via232also penetrates through the interlayer insulating layer23and part of the gate insulating layer22to expose the first signal transfer line62.

After the first sub-hole211is formed, the film layer on the bottom of the first sub-hole211is etched by dry etching to form the second sub-hole212. The second sub-hole212penetrates through the gate insulating layer22, the buffer layer15, and part of the first inorganic layer12on the bottom of the first sub-hole211, as shown inFIG.5. When forming the second sub-hole212, by controlling the time of dry etching, the first inorganic layer12with a certain thickness is retained on the first transparent substrate11corresponding to the area of the first via hole21to protect the first transparent substrate11. Optionally, the thickness of the retained first inorganic layer12ranges from 1000 angstroms to 5000 angstroms to ensure excellent barrier effect against water vapor.

The first source/drain layer70is disposed on the interlayer insulating layer23. The first source/drain layer70forms first sources71and first drains72of the first thin film transistor T1and the second thin film transistor T2in the display area AA. The first source71and the first drain72are respectively connected with the corresponding source region52and the drain region53through different second via holes231. Certainly, the first source/drain layer70also forms signal lines such as data lines74in the display area AA.

The first source/drain layer70forms a second signal transfer line73in the bending area PA, and a part of the second signal transfer line73is connected with the corresponding data line74to provide data signals to the corresponding first thin film transistor T1and the second thin film transistor T2. Another part of the second signal transfer line73is connected with the corresponding first signal transfer line62through the third via hole232.

The first planarization layer91covers on the first source/drain layer70and the interlayer insulating layer23, and fills the first via hole21. The first planarization layer91is an organic material. By filling the first planarization layer91in the first via hole21, the bending performance in the bending area PA may be improved, and the process of filling other organic materials in the first via hole21may be simplified.

It can be understood that when manufacturing the first planarization layer91formed of organic material, the organic material solution is usually manufactured on other film layers by the process such as coating or inkjet printing and cured into a film, and the first inorganic layer12retained on the bottom of the first via hole21can effectively prevent the organic material solution from entering the first transparent substrate11to generate free charges in the first transparent substrate11. Moreover, in the photolithography process for manufacturing the first via hole21, there is usually a process of stripping the photoresist. The first inorganic layer12retained on the bottom of the first via hole21can also prevent the stripping liquid for stripping the photoresist from entering into the first transparent substrate11. If the stripping liquid enters the first transparent substrate11, the stripping liquid may permeate into the contact interface between the first transparent substrate11and other substrates due to high water vapor transmittance of the first transparent substrate11, which results in the decrease of the adhesion between the first transparent substrate11and the other substrates. Moreover, since the thermal stress of the first transparent substrate11is large, the stress in the area of the first via hole21tends to expand to the area with low adhesion and extend to the display area AA close to the bending area PA, which leads to the variation of the grain boundary of the semiconductor device of the thin film transistor in said area to further change the characteristic of the thin film transistor, and thus mura occurs in said area. Therefore, the first inorganic layer12retained on the bottom of the first via hole21can further solve the problem of the occurrence of mura in the display area AA close to the bending area PA.

The second source/drain layer80is disposed on the first planarization layer91. The second source/drain layer80forms the second sources81of the first thin film transistor T1and the second thin film transistor T2in the display area AA, and the second sources81are connected with the first drains72through the via holes of the first planarization layer91. The second source/drain layer80further forms a plurality of binding lines82in the bending area PA, and the binding line82is connected with the second signal transfer line73through the via hole of the first planarization layer91.

The second planarization layer92covers on the second source/drain layer80and the first planarization layer91. The bridge layer40is disposed on the second planarization layer92, and the bridge layer40is a transparent electrically conductive electrode layer, which enhances the transmittance of the function area FA. The material of the bridge layer40includes transparent conductive oxide (TCO) material such as ITO, IZO, ZnO, or In2O3. The first bridge electrode41and the second bridge electrode42formed from the bridge layer40are connected with the corresponding second sources81through different via holes of the second planarization layer92.

The third planarization layer93covers on the bridge layer40and the second planarization layer92. The electrically conductive electrode layer30is disposed on the third planarization layer93. The first pixel electrode31and the second pixel electrode32formed from the electrically conductive electrode layer30are respectively connected with the corresponding first bridge electrode41and the second bridge electrode42through different via holes of the third planarization layer93. By disposing the first thin film transistor T1in the display area AA close to the function area FA which is connecting with the first pixel electrode31through the first bridge electrode41, the transmittance of the function area FA can further be improved on the premise of meeting the display function of the function area FA. Optionally, the material of the electrically conductive electrode layer30may be the same as the material of the bridge layer40. Alternatively, the material of the electrically conductive electrode layer30may also be Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and other electrode materials.

Certainly, the display panel100further includes a pixel definition layer94disposed on the electrically conductive electrode layer30and the third planarization layer93. The pixel definition layer94is provided with pixel openings941corresponding to the first pixel electrode31and the second pixel electrode32to expose the first pixel electrode31and the second pixel electrode32.

In one embodiment, reference is made toFIG.6.FIG.6is a second section view of a schematic structural diagram of the display panel disclosed in the embodiments of the present disclosure. Different from the above embodiments, in the display panel101of the present embodiment, the first transparent substrate11is provided with a plurality of first protrusions111in an area corresponding to the first via hole21. The first protrusion111can extend the diffusion and infiltration path of water vapor and reduce the stress expansion caused by the thermal stress of the first transparent substrate11in the area of the first via hole21, so as to achieve the purpose of releasing water vapor and stress. In this way, the problem of the occurrence of mura in the display area AA close to the bending area PA may be further improved. Optionally, the cross-sectional shape of the first protrusion111includes square, trapezoid, triangle, etc. The other descriptions may refer to the above embodiments, and are not redundantly repeated herein.

In one embodiment, reference is made toFIG.7.FIG.7is a third section view of a schematic structural diagram of the display panel disclosed in the embodiments of the present disclosure. Different from the above embodiments, in the display panel102of the present embodiment, the first inorganic layer12adopts a laminated structure to achieve excellent barrier effect against water vapor. The first inorganic layer12includes at least one silicon oxide layer and at least one silicon nitride layer. Specifically, the first inorganic layer12includes a first silicon nitride layer121covering on the first transparent substrate11and a first silicon oxide layer122covering one side of the first silicon nitride layer121away from the first transparent substrate11. The first via hole21penetrates part or all of the first silicon oxide layer122to expose the first silicon nitride layer121. Optionally, the thickness of the first inorganic layer12exposed by the first via hole21ranges from 1000 angstroms to 5000 angstroms. That is, the thickness of the first silicon nitride layer121retained in the area of the first via hole21ranges from 1000 angstroms to 5000 angstroms. The other descriptions may refer to the above embodiments, and are not redundantly repeated herein.

In one embodiment, references are made toFIG.8andFIG.9.FIG.8is a fourth section view of a schematic structural diagram of the display panel disclosed in the embodiments of the present disclosure.FIG.9is a partial section view of the schematic structural diagram of the display panel inFIG.8. Different from the above embodiments, in the display panel103of the present embodiment, the first inorganic layer12further includes a second silicon nitride layer123covering one side of the first silicon oxide layer122away from the first silicon nitride layer121, and the first via hole21further penetrates the second silicon nitride layer123. That is, the first via hole21penetrates the second silicon nitride layer123and part or all of the first silicon oxide layer122of the first inorganic layer12.

Optionally, the thickness of the first silicon nitride layer121ranges from 500 angstroms to 2000 angstroms. The thickness of the first silicon oxide layer122ranges from 2000 angstroms to 6000 angstroms. The thickness of the second silicon nitride layer123ranges from 500 angstroms to 2000 angstroms. The thickness of the first inorganic layer12exposed by the first via hole21ranges from 1000 angstroms to 5000 angstroms. By disposing the first inorganic layer12with laminated structure and retaining the first inorganic layer12with a thickness of 1000 angstroms to 5000 angstroms in the area of the first via hole21, it not only achieves the function of blocking water vapor to protect the first transparent substrate11, but also facilitates adjusting the stress center layer in the bending area PA to avoid increasing the risk of crack of the binding lines82in the bending area PA.

It should be noted that in order to reduce the risk of crack of the binding lines82in the bending area PA, the film layer for disposing the binding lines82is usually adjusted as the stress center layer in the bending area PA. The first inorganic layer12with a certain thickness is retained in the area of the first via hole21, which may cause the stress center layer in the bending area PA to move down, thereby increasing the bending stress on the binding lines82in the bending area PA. Moreover, with the increase of the retained thickness of the first inorganic layer12, the bending stress on the binding lines82in the bending area PA may also increase, as shown inFIG.10.FIG.10is a diagram of a relationship between the retained thickness of the first inorganic layer and the bending stress in the bending area obtained by simulation according to the embodiments of the present disclosure. InFIG.10, the abscissa represents the retained thickness of the first inorganic layer12, and the ordinate represents the bending stress value of the binding lines82in the bending area PA. From the simulation results inFIG.10, it can be seen that the retained thickness of the first inorganic layer12ranges from 1000 angstroms to 5000 angstroms (i.e., 100 nm to 500 nm shown inFIG.10). Although the stress on the binding lines82in the bending area PA increases, the range of increase is quite small. The risk of crack of the binding lines82is not increased basically, thereby ensuring the bending reliability of the bending area. Moreover, since the first inorganic layer12is arranged as a laminated structure, the thickness of the reserved first inorganic layer12tends to be thinned, which is conducive to adjusting the position of the stress center layer in the bending area PA on the premise of blocking water vapor, so as to reduce the risk of crack of the binding lines82.

Furthermore, different from the above embodiments, a double-gate structure is used in the present embodiment. In addition, the bridge layer40also adopts a multi-layer bridge, and the electrically conductive electrode layer30adopts a laminated structure.

Specifically, the gate layer60includes a first gate layer60-1and a second gate layer60-2. Accordingly, the gate insulating layer22also includes a first gate insulating layer22-1and a second gate insulating layer22-2. The first gate insulating layer22-1is located between the semiconductor layer50and the first gate layer60-1. The second gate insulating layer22-2is located between the first gate layer60-1and the second gate layer60-2. The first gate layer60-1forms first gates61-1of the first thin film transistor T1and the second thin film transistor T2in the display area AA, and also forms corresponding gate scanning lines63. The first gate layer60-1forms first signal transfer lines62in the bending area PA. The second gate layer60-2forms second gates61-2of the first thin film transistor T1and the second thin film transistor T2in the display area AA. Certainly, the second gate layer60-2may also form other signal lines in the display area AA and corresponding other signal transfer lines in the bending area PA.

Further, the bridge layer40is arranged as a multi-layer, so that the stress center layer of the bending area PA can be effectively adjusted. The bridge layer40includes a first bridge layer40-1and a second bridge layer40-2. If the first bridge layer40-1is disposed on the second planarization layer92, then there is further a requirement for a fourth planarization layer95correspondingly. The fourth planarization layer95covers on the first bridge layer40-1and the second planarization layer92. The second bridge layer40-2is disposed on the fourth planarization layer95. The third planarization layer93covers on the second bridging layer40-2and the fourth planarization layer95. The first bridging layer40-1forms a first bridge electrode41in the function area FA and a second bridge electrode42in the display area AA. The second bridging layer40-2forms a third bridge electrode43in the function area FA and a fourth bridge electrode44in the display area AA. The first bridge electrode41extends from the function area FA to the display area AA and is connected with the second source81of the first thin film transistor T1. The third bridge electrode43is connected with the first bridge electrode41. The second bridge electrode42is connected with the second source81of the second thin film transistor T2, and the fourth bridge electrode44is connected with the second bridge electrode42.

Further, the electrically conductive electrode layer30is disposed on the third planarization layer93. The electrically conductive electrode layer30includes a first electrically conductive electrode layer30-1and a second electrically conductive electrode layer30-2. The first electrically conductive electrode layer30-1forms a first auxiliary electrode33in the function area FA and a second auxiliary electrode34in the display area AA. The first auxiliary electrode33is connected with the third bridge electrode43, and the second auxiliary electrode34is connected with the fourth bridge electrode44. The second electrically conductive electrode layer30-2forms a first pixel electrode31in the function area FA and a second pixel electrode32in the display area AA. The first pixel electrode31is connected with the first auxiliary electrode33, and the second pixel electrode32is connected with the second auxiliary electrode34. The other descriptions may refer to the above embodiments, and are not redundantly repeated herein.

In one embodiment, reference is made toFIG.11.FIG.11is a fifth section view of a schematic structural diagram of the display panel disclosed in the embodiments of the present disclosure. Different from the above embodiments, in the display panel104of the present embodiment, the first inorganic layer12includes a first silicon oxide layer122, a first silicon nitride layer121, a second silicon oxide layer124, and a second silicon nitride layer123which are stacked on the first transparent substrate11. The first via hole21penetrates through the second silicon nitride layer123and the second silicon oxide layer124to expose the first silicon nitride layer121.

Optionally, the thickness of the first silicon oxide layer122is smaller than the thickness of the second silicon oxide layer124. The thickness of the first silicon oxide layer122ranges from 100 angstroms to 1000 angstroms. The thickness of the first silicon nitride layer121ranges from 500 angstroms to 2000 angstroms. The thickness of the first silicon oxide layer122ranges from 2000 angstroms to 6000 angstroms. The thickness of the second silicon nitride layer123ranges from 500 angstroms to 2000 angstroms. The thickness of the first inorganic layer12exposed by the first via hole21is controlled between 1000 angstroms and 5000 angstroms.

It can be understood that since the barrier effect against water vapor of the silicon oxide is worse than that of the silicon nitride, the first inorganic layer12retained in the bending area PA includes the first silicon oxide layer122and the first silicon nitride layer121as much as possible. Moreover, in order to reduce the thickness of the retained first inorganic layer12, the first silicon oxide layer122may have small thickness. On the premise of meeting the interface adhesion with the first transparent substrate11, the thickness of the retained first inorganic layer12is reduced as much as possible. The second silicon oxide layer124may be penetrated by the first via hole21. That is, the second silicon oxide layer124may be completely etched in the area corresponding to the first via hole21, and the stress matching between silicon oxide and organic substrate material can be effectively adjusted. Accordingly, the second silicon oxide layer124may have large thickness. The other descriptions may refer to the above embodiments, and are not redundantly repeated herein.

In one embodiment, reference is made toFIG.12.FIG.12is a sixth section view of a schematic structural diagram of the display panel disclosed in the embodiments of the present disclosure. Different from the above embodiments, in the display panel105of the present embodiment, a plurality of second protrusions1211are disposed on the surface of the first inorganic layer12exposed by the first via hole21. The first inorganic layer12exposed by the first via hole21includes the first silicon nitride layer121and the first silicon oxide layer122, wherein a plurality of second protrusions1211are disposed on the first silicon nitride layer121. The second protrusions1211can extend the diffusion and infiltration path of water vapor and reduce the stress expansion caused by the thermal stress of the first transparent substrate11in the area of the first via hole21, so as to achieve the purpose of releasing water vapor and stress. In this way, the problem of the occurrence of mura in the display area AA close to the bending area PA can be further improved. Optionally, the cross-sectional shape of the second protrusion1211also includes square, trapezoid, triangle, etc. The other descriptions may refer to the above embodiments, and are not redundantly repeated herein.

Moreover, it should be explained that, in order to realize the display function of the display panel, the display panel of the present disclosure further includes a light-emitting function layer disposed on the pixel definition layer94. In addition, in order to protect the light-emitting function layer, the display panel of the present disclosure further includes a packaging layer disposed on the light-emitting function layer. The display panel105in the aforementioned embodiment is described below as an example.

Specifically, reference is made toFIG.13.FIG.13is a partial detailed structural diagram of the display panel disclosed in the present disclosure. The light-emitting functional layer200includes a light-emitting unit201and a cathode202. The light-emitting unit201is formed of light-emitting materials printed in the pixel opening of the pixel definition layer94. The light-emitting materials of different colors form the light-emitting units of different colors, and the light-emitting units of different colors emit light of different colors, so as to realize the color display of the display panel. For example, the light-emitting unit201may include a red light-emitting unit formed of a red light-emitting material, a green light-emitting unit formed of a green light-emitting material, and a blue light-emitting unit formed of a blue light-emitting material. The red light-emitting unit emits red light, the green light-emitting unit emits green light, and the blue light-emitting unit emits blue light.

The cathode202covers on the light-emitting unit201and the pixel definition layer94. The light-emitting unit201emits light under the cooperative action of the corresponding pixel electrode (e.g., the first pixel electrode31or the second pixel electrode32) and the cathode202.

Optionally, the light-emitting function layer200may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the light-emitting unit201and the pixel electrode, and an electron injection layer (EIL) and an electron transport layer (ETL) disposed between the light-emitting unit201and the cathode202. The hole injection layer receives the holes transmitted by the pixel electrode, and the holes are transmitted to the light-emitting unit201through the hole transport layer. The electron injection layer receives the electrons transmitted by the cathode202, and the electrons are transmitted to the light-emitting unit201through the electron transport layer. The holes and electrons are combined in the light-emitting unit201to generate excitons, which transition from the excited state to the ground state to release energy and emit light.

The packaging layer300covers the light-emitting function layer200to protect the light-emitting unit201of the light-emitting function layer200and to avoid of the intrusion of water vapor, which leads to the failure of the light-emitting unit201. Optionally, the packaging layer300may be encapsulated by thin films. For example, the packaging layer300may be a laminated structure formed by successively stacking three films of the first inorganic packaging layer, the organic packaging layer, and the second inorganic packaging layer, or a laminated structure of more layers.

Certainly, the display panel105of the present disclosure may further include a touch electrode layer, a polarizer, a cover plate, and other structures disposed on one side of the packaging layer300away from the light-emitting function layer200, and the further description is not redundantly repeated herein.

An electronic device is further disclosed in the embodiments of the present disclosure. The electronic device includes the display panel in one of the foregoing embodiments. The electronic device includes electronic devices such as mobile phone, tablet, television.

According to the Aforementioned Embodiments

A display panel and an electronic device are disclosed in the present disclosure. The display panel includes the display area and the bending area located in one side of the display area. The display panel further includes the first transparent substrate, the first inorganic layer located on one side of the first transparent substrate, and the second inorganic layer located on one side of the first inorganic layer away from the first transparent substrate. A first via hole is defined in the second inorganic layer in the bending area. The first via hole penetrates the second inorganic layer and part of the first inorganic layer, so that an area of the first inorganic layer corresponding to the first via hole retain a certain thickness of whole film layer to protect the first transparent substrate and avoid the influences of water vapor and the etching process of the first via hole on the first transparent substrate. Accordingly, the problem that mura occurs near the bending area due to the exposed first transparent substrate is avoided, and thus the problem of local mura occurring in the position near the bending area in the existing display panel is solved.

In the aforementioned embodiments, the description of each embodiment has its own emphasis. The part not detailed in one embodiment may refer to the related description of other embodiments.

The embodiments of the present disclosure are described in detail above. Specific examples are used in this text for illustrating the principles and implementations of the present disclosure. The description of the aforementioned embodiments is merely intended to help understand the methods of the present disclosure and a concept thereof. It can be understood that for those skilled in the art, equivalent substitutions or changes can be made according to the technical scheme of the present disclosure and its inventive concept, and all these substitutions or changes should belong to the protection scope of the claims attached to the present disclosure.