IMAGING ELEMENT, ENDOSCOPE, ENDOSCOPE SYSTEM, AND TESTING METHOD

An imaging element includes: a pixel board including a light receiver including plural pixels, each pixel being configured to generate an imaging signal; a circuit board including a functional circuit, the pixel board being layered on the circuit board; plural wiring portions configured to electrically connect the pixel board and the circuit board to each other and electrically transmit signals between respective layers; a terminal provided on the circuit board, the terminal being electrically connected to each of the plural wiring portions, the terminal being configured to output the imaging signal to an outside of the terminal or receive an external signal from the outside of the terminal; and a switch configured to output, by selective switching, at least one of the imaging signal and an internal signal generated at the circuit board, to the terminal.

BACKGROUND

1. Technical Field

The present disclosure relates to an imaging element, an endoscope, an endoscope system, and a to method, for generation of image data. by imaging of a subject.

2. Related Art

In the related art, a known technique adopted for solid-state imaging devices involves layering, over one another: a first semiconductor board including a sensor circuit including a photoelectric converter; and a second semiconductor board and a third semiconductor board each including a circuit different from the sensor circuit (for example, see International Publication No. 2015/159766). In this technique, interlayer connection between the semiconductor boards is achieved by use of plural electrodes and/or bumps, for example, and signals are thereby input and output between the semiconductor boards. Furthermore, every time one of the semiconductor boards is layered over another one of the semiconductor boards, energization states of the electrodes are tested by predetermined measurement.

SUMMARY

In some embodiments, an imaging element includes: a pixel board including a light receiver arranged on the pixel board, the light receiver including plural pixels that are arranged in a two-dimensional matrix, each pixel being configured to receive light from an outside of the pixel and generate an imaging signal according to quantity of the light received; a circuit board including a functional circuit with a predetermined function, the pixel board being layered on the circuit board; plural wiring portions configured to electrically connect the pixel board and the circuit board to each other and electrically transmit signals between respective layers; a terminal provided on the circuit board, the terminal being electrically connected to each of the plural wiring portions, the terminal being configured to output the imaging signal to an outside of the terminal or receive an external signal from the outside of the terminal; and a switch configured to output, by selective switching, at least one of the imaging signal and an internal signal generated at the circuit board, to the terminal.

In some embodiments, all endoscope includes: the imaging element; and an insertion portion, that to be inserted into a subject, the insertion portion including the imaging element provided at a distal end portion of the insertion portion.

In some embodiments, provided is a testing method of an imaging element including: a pixel board including a light receiver arranged on the pixel board, the light receiver including plural pixels that are arranged in a two-dimensional matrix, each pixel being configured to receive light from an outside, of the pixel and generate an imaging signal according to quantity of the light received; a circuit board including a functional circuit with a predetermined function, the pixel board being layered on the circuit board; plural wiring portions configured to electrically connect the pixel board and the circuit board to each other and electrically transmit signals between respective layers; a terminal provided on the circuit board, the terminal being electrically connected to each of the plural wiring portions, the terminal being configured to output the imaging signal to an outside of the terminal or receive an external signal from the outside of the terminal; and a switch configured to output, by selective switching, at least one of the imaging signal and an internal signal generated at the circuit board, to the terminal, the testing method including: inputting at least a synchronization signal to the imaging element; and determining a defective part of the imaging element based on the imaging signal and the internal signal output from the imaging element.

DETAILED DESCRIPTION

Modes for implementing the present disclosure (hereinafter, referred to as “embodiments”) described hereinafter are endoscope systems each including an imaging device. These embodiments do not limit the disclosure. Any portions that are the same will be assigned with the same reference sign throughout the drawings. The drawings are schematic, and it needs to be noted that relations between thicknesses and widths of members and ratios among the members therein may be different from the actual ones. A portion that differs in dimensions and ratios among the drawings may also be included.

First Embodiment

Configuration of Endoscope System

FIG.1is a diagram schematically illustrating an overall configuration of an endoscope system according to a first embodiment. In an endoscope system1illustrated inFIG.1, images of the interior of the body of a subject, such as a patient, are captured by insertion of an insertion portion of an endoscope into the subject, and display images based on imaging signals captured thereby are displayed on a display device. A user, such as a medical doctor, performs observation of the display images displayed on the display device. The endoscope system1includes an endoscope2, a light source device3, a display device4, and a control device5.

Configuration of Endoscope

A configuration of the endoscope2will be described first.

The endoscope2generates an imaging signal (RAW data) resulting from imaging of the interior of the body of a subject, and outputs the generated imaging signal to the control device5. The endoscope2includes an insertion portion21, an operating unit22, and a universal cord23.

The insertion portion21is inserted into a subject. The insertion portion21has an elongated shape having flexibility. The insertion portion21includes: a distal end portion24including therein an imaging device100described later; a bending portion25that is formed of plural bending pieces and is bendable; and a flexible tube portion26that is connected to a proximal end of the bending portion25, has flexibility, and is elongated.

The distal end portion24is formed by use of, for example, glass fiber. The distal end portion24includes: a light guide (not illustrated in the drawings) forming a light guiding path for illumination light supplied from the light source device3; an illumination optical system provided at a distal end of the light guide; and the imaging device100described later.

The operating unit22includes: a bending knob221that bends the bending portion25upward, downward, leftward, and/or rightward; a treatment tool insertion portion222through which a treatment tool, such as biopsy forceps, an electric knife, or an examination probe, are/is inserted into a body cavity; and plural switches223serving as an operation input unit through which peripheral device operating instruction signals and a pre-freeze signal are input, the peripheral device operating instruction signals being for, in addition to the light source device3and the control device5, peripheral devices, such as an air feeding means, a water feeding means, and a gas feeding means, the pre-freeze signal being for instructing the imaging device100to rapture a still image. The treatment tool inserted from the treatment tool insertion portion222comes out from an opening (not illustrated in the drawings) via a treatment tool channel (not illustrated in the drawings) in the distal end portion24.

The universal cord23includes therein at least the light guide and a cable assembly including one or plural cables bundled together. The cable assembly includes signal lines for transmitting and receiving signals between: the endoscope2and the light source device3; and the control device5. These signal lines include, for example, a signal line for transmitting and receiving captured images (image data), a signal line for transmitting and receiving drive timing signals (synchronization signals and clock signals) for driving the imaging device100, and a signal line for supplying electric power to the imaging device100. The universal cord23includes a connector27that is attachable to and detachable from the light source device3. A coil cable27athat is coil-shaped extends from the connector27. A connector28attachable to and detachable from the control device5is provided at an extended end of the coil cable27a.

Configuration of Light Source Device

A configuration of the light source device3will be described next.

Under control by the control device5, the light source device3supplies illumination light with which the endoscope2irradiates a subject. The light source device3is implemented by use of, for example, a halogen lamp, a laser diode (LD), and a white light emitting diode (LED). The light source device3supplies the illumination light to the distal end portion24of the insertion portion21, via the connector27, the universal cord23, and the insertion portion21. The illumination light is any one of white light and special light (for example, narrow band imaging (NBI) light or infrared light).

Configuration of Display Device

A configuration of the display device4will be described next.

Under control by the control device5, the display device4displays a display image based on an imaging signal input from the control device5. The display device4is implemented by use of a display panel of, for example, organic electroluminescence (EL) or liquid crystal.

Configuration of Control Device

A configuration of the control device5will be described next.

The control device5controls each unit in the endoscope system1. The control device S performs various types of image processing of an imaging signal input from the endoscope2and outputs the processed imaging signal to the display device4. Furthermore, the control device5supplies illumination light to the endoscope2by controlling the light source device3.

Main Parts of Endoscope System

A configuration of main parts of the endoscope2and the control device5described above will be described next.FIG.2is a block diagram illustrating a functional configuration of the main parts of the endoscope2and the control device5.

Main Parts of Endoscope

A functional Configuration Of main parts of the endoscope2Will be described first.

The endoscope2includes the imaging device100, a transmission cable200provided inside the universal cord23, and the connector28.

The imaging device100is arranged the distal end portion24of the endoscope2, generates an imaging signal by capturing an image of the interior of a subject, and outputs this imaging signal to the control device5via the transmission cable200in the universal cord. The imaging device100includes an optical system110and an imaging element120(an imaging module).

By condensing reflected light of illumination light reflected by a subject, the optical system110forms a subject image on light receiving surface of the imaging element120. The optical system110is implemented by use of, for example, one or plural lenses.

By receiving a subject image formed by the, optical system110and photoelectrically converting the subject image, the imaging element120generates an imaging signal. The imaging element120outputs the imaging signal to the control device5via the transmission cable200. The imaging element120is implemented by use of, for example, a complementary metal oxide semiconductor (CMOS). A detailed configuration of the imaging element120will be described later.

The transmission cable200will be described next, The transmission cable200is implemented by use of plural signal lines. Specifically, the transmission cable200is implemented by use of five signal lines, a signal line201, a signal line202, a signal line203, a signal line204, and a signal line205. The signal line201is connected to ground GND. The signal line202transmits power source voltage VDD input from the control device5to the imaging device100. The signal line203transmits, to the imaging device100, a superimposed signal SYNC/DC1input from the connector28and including a synchronization signal SYNC and a predetermined direct current component DC1superimposed on each other. The signal line204transmits a clock signal CLK input from the connector28, to the imaging device100. The signal line205transmits an imaging signal Vout input from the imaging device100, to the connector28.

The connector28will be described next. The connector28is detachably connected to the control device5. The connector28includes an analog front end unit281(hereinafter, referred to as the “AFE unit231”), a signal processing unit282, a driving signal generator283, a power source generator284, and a superimposing unit285.

The AFE unit281generates a digital imaging. signal by performing processing, such as denoising and A/D conversion, of an imaging signal Vout transmitted through the signal line205, and outputs this digital imaging signal to the signal processing unit282.

The signal processing unit282performs predetermined signal processing, for example, format conversion processing and/or can up processing, of a digital imaging signal input from the AFE unit281, and outputs the processed imaging signal to the control device5.

On the basis of a clock signal input from the control device5, the driving signal generator283generates a clock signal CLK and a synchronization signal SYNC for driving the imaging device100, outputs the clock signal CLK to the signal line204, and outputs the synchronization signal SYNC to the superimposing unit285.

The power source generator284generates a direct current component DC1resulting from adjustment of a predetermined voltage input from the control device5to a voltage value for driving a predetermined circuit in the imaging device100, and outputs this direct current component DCI to the superimposing unit285.

The superimposing unit285outputs, to the signal line204, a superimposed signal SYNC/DC1resulting from superimposition of a synchronization signal SYNC and a direct current component DC1on each other, the synchronization signal SYNC having been input from the driving signal generator283, the direct current component DUI having been input from the power source generator284.

A functional configuration of the control device5will be described next.

The control device5includes a power source a clock generator52, an image processing unit53, and a control unit55.

On the basis of electric power input from outside, the power source51generates power source voltage VDD based on the ground GND. The power source51outputs the power source voltage VDD to the power source generator284and to each unit included in the control device5.

The clock generator52generates a clock signal serving as a reference for operation of each unit in the endoscope system1, and outputs this clock signal to the driving signal generator283of the connector28and to the control unit55. The clock generator52is formed by use of a clock module, for example.

Under control by the control unit55, the image processing unit53performs predetermined image processing of an imaging signal input from the signal processing unit82of the connector28, and outputs the processed imaging signal to the display device4. Examples of this predetermined image processing include white balance adjustment processing and demosaicing processing. The image processing unit53is implemented by use of a graphics processing unit (GPU) or a field programmable gate array (FPGA), for example.

The control unit55controls each unit in the endoscope system1. The control unit55is implemented by use of a memory and a processor including hardware, such as a central processing unit (CPU).

Detailed Description of Imaging Element

A detailed configuration of the above described imaging element120will be described next.FIG.3is a diagram illustrating a schematic configuration of the imaging element170.

As illustrated inFIG.3andFIG.4, the imaging element170includes: a first semiconductor board121(a peripheral circuit board) with a functional circuit arranged thereon, the functional circuit having a predetermined function; a second semiconductor board122with a VDD capacitor arranged thereon; a third semiconductor board123with a DCI capacitor arranged thereon; and a fourth semiconductor board124with a light receiver125arranged thereon, the light receiver125including plural pixels that are arranged in a two-dimensional matrix and that each receive light and generate an imaging signal. The imaging element120includes the first semiconductor board121, the Second semiconductor board122, the third semiconductor board123, and the fourth semiconductor board124layered. over one another in this order. Specifically, the imaging element120includes the first semiconductor board121arranged as the undermost layer, the fourth semiconductor board124layered as the topmost layer of the imaging element120, and the light receiver125arranged on a light receiving side thereof. In this first embodiment, the first semiconductor board121, the second semiconductor board122, and the third semiconductor board123function as circuit boards, and the fourth semiconductor board124functions as a pixel board.

Furthermore, transmission channels L1to L6are electrically connected to connection terminals T1to T4provided on the underside of the first semiconductor board121of the imaging element120, and the transmission channels L1to L6are also electrically connected. The first semiconductor board121, the second semiconductor board122, the third semiconductor board123, and the fourth semiconductor board124each include plural terminals therein, and form the plural transmission channels L1to L6that electrically connect these semiconductor boards to one another by, for example, interlayer connection using any one or more selected from a group of electrodes, through silicon vias (TSVs), and bumps. In this first embodiment, the transmission channels L1to L6function as wiring portions and the connection terminals T1to T4function as a terminal. The connection terminals T1to T3function as input terminals and the connection terminal T4functions as an output terminal.

Every time a semiconductor board for the imaging element120is layered, connection states of the transmission channels L1to L6are tested. In a case where any one of the first semiconductor board121, the second semiconductor board122, the third semiconductor board123, and the fourth semiconductor board124has poor connection after they have been mounted in the endoscope2, identifying which one of the transmission channels L1to L6has the failure used to be impossible. For example, in a case where the transmission channel L2, has poor contact, identifying the part causing the poor contact conventionally used to be difficult because the only failure that used to be observable was the inability of the imaging signal Vout to be output from the imaging element120.

In this first embodiment, a switch302is thus provided in the imaging element120. This switch302outputs, by selective switching, at least One of an imaging signal Vout output from the light receiver125and an internal signal, to the connection terminal T4. The internal signal is generated at any one of the first semiconductor board121, the second semiconductor board122, and the third semiconductor board123.

FIG.4is a schematic diagram illustrating a functional configuration of main parts of the first semiconductor board121. As illustrated inFIG.4, the first semiconductor board121includes at least a separator300, a first generator301, the switch302, and an amplifier303.

The separator300separates a direct current component DC1and a synchronization signal SYNC from a superimposed. signal input from the connector28via the connection terminal T2. The separator300transmits the separated direct current component DC1and synchronization signal SYNC, to the fourth semiconductor board124of the topmost layer, via the transmission channel L1and transmission channel L5. Furthermore, each of the direct current component DC1and synchronization signal SYNC separated by the separator300is input to the switch302.

The first generator301is electrically connected to the transmission channel L2and generates, on the basis of the synchronization signal SYNC separated by the separator300, a switching signal for switching output of the switch302. Specifically, the first generator301generates a switching signal according to a synchronization signal SYNC having a predetermined test mode pattern embedded therein. More specifically, the first generator301generates, once per frame of the imaging element120, a switching signal by using a synchronization signal SYNC having, for example, an 8-bit pattern. For example, in a normal mode where the switch302is caused to output an imaging signal Vout from the fourth semiconductor board124, when the first generator301receives a synchronization signal SYNC having a pattern, “11001100”, embedded therein, the first generator301causes the switch302to output an imaging signal Vout. In contrast, in a test mode where the switch302is caused to output a synchronization signal SYNC, when the first generator301receives a synchronization signal SYNC having a pattern, “10101010”, embedded therein, the first generator301causes the switch302to output a synchronization signal SYNC The first generator301is implemented by use of, for example, a semiconductor switch, a multiplexer, and a control register. In this first embodiment, the first generator301functions as a switching signal generator.

The switch302is arranged on the transmission channel L2and transmission channel L5of the separator300and the fourth semiconductor board124and is also arranged on the transmission channel L6of the amplifier303and the fourth semiconductor board124. Specifically, the switch302is electrically connected to each of the separator300and the fourth semiconductor board124. The switch302outputs, by selective switching, at least one of an imaging signal Vout output from the light receiver125and an internal signal generated by any one of the first semiconductor board121, the second semiconductor board122, and the third semiconductor board123, to the connection terminal T4. The switch302is implemented by use of, for example, a semiconductor switch, a multiplexer, and a control register.

The amplifier303amplifies a signal VINinput from the switch302. The signal VINis output to the outside via the connection terminal T4. The amplifier303is implemented by use of a buffer circuit, for example.

Testing Method by Endoscope System

A testing method executed by the endoscope system1will be described next.FIG.5is a flowchart illustrating an outline of the testing method executed by the endoscope system1.

As illustrated inFIG.5, the control unit55causes the driving signal generator283to transmit a synchronization signal SYNC corresponding to a predetermined test mode (Step S101).

Subsequently, on the basis of the synchronization signal SYNC separated by the separator300, the first generator301generates a switching signal according to the test mode and outputs this witch no signal to the switch302(Step S102).

Thereafter, the switch302outputs a signal according to the switching signal input from the first generator301(Step S103).FIG.6is a diagram illustrating correspondence between test modes, output signals output from the imaging element120, determination results, and state results indicating states of the imaging element120. As illustrated inFIG.6, in a case where a switching signal that causes the switch302to output an imaging signal Vout has been input from the first generator301, the switch302outputs an imaging signal Vout input from the fourth semiconductor board124.

Subsequently, the control unit55records, into a recording unit54, an output result that has been input from the endoscope2and the image processing unit53(Step S104) and determines whether or not all of test modes have ended (Step S105). In a case where the control unit55determines that all of the test modes have ended (Step S105: Yes), the endoscope system1proceeds to Step S106described later. On the contrary in a case where the control unit55determines that not all of the test modes have ended (Step S105: No), the endoscope system1returns to Step S101described above.

At Step S106, by controlling the image processing unit53, the control unit55causes the display device4to display information according to all of output results for the test modes recorded in the recording unit54. After step S106, the endoscope system1ends processing.

FIG.7is a diagram associating between the test modes, the determination results, and defective parts that are able to be presumed to be defective from the determination results. As illustrated inFIG.7, the control unit55causes the display device4to display the defective parts according to the output results for the modes. For example, as illustrated inFIG.7, in a case where each of the output results for a first test mode to a third test mode is “good”, the control unit55causes the display device4to display information indicating that the imaging element120is normal. On the contrary, in a case where each of the output results for the first test mode and the second test mode is “good” and the output result for the third test mode is “not good”, the control unit55causes the display device4to display information indicating that a failure is occurring in a peripheral circuit provided on the first semiconductor board121. A user is thereby able to identify any defective part of the imaging element120by checking the information displayed by the display device4.

The first embodiment described above enables external identification of any part causing poor connection because the switch302outputs, by selective switching, at least one of an imaging signal Vout and an internal signal.

Furthermore, the first embodiment enables external identification of any part causing poor connection because the first generator301generates, on the basis of a synchronization signal SYNC separated by the separator300, a switching signal according to a test mode, outputs this switching signal to the switch302, and the switch302is caused to output a signal according to the test mode.

Furthermore, the first embodiment enables reduction in the diameter of the endoscope2because the number of the signal linen in the transmission cable200is able to be reduced by separation of a synchronization signal. SYNC and a direct current component DC1by the separator300.

Second Embodiment

A second embodiment will be described next. In the first embodiment described above, a superimposed signal including a synchronization signal SYNC and a direct current component DCI superimposed on each other is transmitted to the imaging element120, but in the second embodiment, a superimposed signal including a synchronization signal SYNC and a clock signal CLK superimposed on each other is transmitted to an imaging element Main parts of an endoscope system according to the second embodiment will be described hereinafter. The same reference signs will be assigned to components that are the same as those of the above described endoscope system1according to the first embodiment, and detailed description thereof will thus be omitted.

Main Parts of Endoscope System

FIG.8is a block diagram illustrating a functional configuration of main parts of an endoscope and a control device in the endoscope system according to the second embodiment. An endoscope system1A illustrated inFIG.8includes an endoscope2A instead of the above described endoscope2according to the first embodiment. The endoscope2A includes a connector28A and an imaging device100A, instead of the above described connector28and imaging device100according to the first embodiment. The connector28A includes a superimposing unit285A instead of the above described superimposing unit285according to the first embodiment. The superimposing unit285A generates a superimposed signal resulting from superimposition of a clock signal CLK on a synchronization signal SYNC input from the driving signal generator283and transmits this superimposed signal to the imaging device100A.

The imaging device100A includes an imaging element120A, instead of the above described imaging element120according to the first embodiment. The imaging element120A is implemented by use of a CMOS, for example. A detailed configuration of the imaging element120A will be described later.

Detailed Description of Imaging Element

The detailed configuration of the above mentioned imaging element120A will be described next.FIG.9is a diagram illustrating a schematic configuration of the imaging element120A. The imaging element120A illustrated inFIG.9includes a first semiconductor board121A instead of the above described first semiconductor board121.

Main Parts of First Semiconductor Board

FIG.10is a schematic diagram illustrating a functional configuration of main parts of the first semiconductor board121A. The first semiconductor board121A illustrated inFIG.10includes a separator300A, instead of the above described separator300.

The separator300A separates a synchronization signal SYNC and a clock signal CLK, from a superimposed signal input from the connector28A via the connection terminal T2. The separator300A transmits the separated synchronization signal SYNC and clock signal CLK, to the fourth semiconductor board124of the topmost layer, via the transmission channel L1and transmission Channel L2. Furthermore, each of the synchronization signal SYNC and clock signal CLK separated by the separator300A is input to the switch302.

Similarly to the above described imaging element120, the imaging element120A configured as described above outputs, on the basis of a switching signal input to the switch302by the first generator301, any one of the imaging signal Vout, a synchronization signal SYNC, and a clock signal CLK, to the control device5. In this case, by a testing method similar to that according to the first embodiment described above, the control device determines a defective part of the imaging element120A according to a signal output by the imaging element120A and displays a result of this determination on the display device4. As a result, a user is able to identify the defective part of the imaging element120A.

The second embodiment described above enables a part causing poor connection to be identified externally because the switch302outputs, by selective switching, at least one of an imaging signal Vout and an internal signal.

Third Embodiment

A third embodiment will be described next. In this third embodiment, a first semiconductor board has a configuration different from that of the above described first semiconductor board121according to the first embodiment. Main parts of the first semiconductor board according to the third embodiment will be described hereinafter. The same reference signs will be assigned to components that are the same as those of the above described endoscope system1according to the first embodiment, and detailed description thereof will thus be omitted.

Main Parts of First Semiconductor Board

FIG.11is a schematic diagram illustrating a functional configuration of the main parts of the first semiconductor board according to the third embodiment. A first semiconductor board121B in an imaging device120B illustrated inFIG.11further includes an adjuster304, in addition to the above described configuration of the first semiconductor board121according to the first embodiment.

The adjuster304is arranged between output signals from the switch302and the separator300. The adjuster304adjusts the level of the operation range of the amplifier303. The adjuster304includes a resistor R1, a resistor R2, a resistor R3, and a resistor R4. The resistor R1and the resistor R2are electrically connected to signal lines that transmit power source voltage VDD and a direct current component DC1, and output values divided from the power source voltage VDD and direct current component DC1, to the switch302. The resistor R3and the resistor R4are electrically connected to the signal line that transmits the power source voltage VDD and a signal line that transmits a synchronization signal SYNC, and output values divided from the power source voltage VDD and synchronization signal SYNC, to the switch302.

The third embodiment described above enables a part causing poor connection to be identified externally because the switch302outputs, by selective switching, at least one of an imaging signal Vout and an internal signal.

Furthermore, the third embodiment enables output of a stable signal because the adjuster304adjusts the level of operation range of the amplifier303.

Fourth Embodiment

A fourth embodiment will be described next. In this fourth embodiment, a first semiconductor board has a configuration different from that of the above described first semiconductor board121A according to the second embodiment. Main parts of the first semiconductor board according to the fourth embodiment will be described hereinafter. The same reference signs will be assigned to components that are the same as those of the above described endoscope system1according to the first embodiment, and detailed description thereof will thus be omitted.

Main Parts of First Semiconductor Board

FIG.12is a schematic diagram illustrating a functional configuration of the main parts of the first semiconductor board according to the fourth embodiment. A first semiconductor board121C illustrated inFIG.12further includes an adjuster304C in addition to the above described configuration of the first semiconductor board121A according to the second embodiment.

The adjuster304C is arranged between output signals from the switch302and separator300A. The adjuster304C adjusts the level of the operation range of the amplifier303. The adjuster304C includes the resistor R1, the resistor R2, the resistor R3, and the resistor R4. The resistor R1and the resistor R2are connected to signal lines that transmit power source voltage VDD and a clock signal CLK, and output values divided from the power source voltage VDD and clock signal CLK, to the switch307. The resistor R3and the resistor RA are electrically connected to the signal line that transmits the power source voltage VDD and a signal line that transmits a synchronization signal SYNC, and output values divided from the power sources VDD and the synchronization signal SYNC, to the switch307.

The fourth embodiment described above enables a part causing poor connection to be identified externally because the. switch302outputs, by selective switching, at least one of an imaging signal Vout and an internal signal.

Furthermore, the fourth embodiment enables output of a stable signal because the adjuster304C adjusts the level of the operation range of the amplifier303.

Fifth Embodiment

A fifth embodiment will be described next. In this fifth embodiment, a first semiconductor board has a configuration different from that of the above described first semiconductor board121according to the first embodiment. Main parts of the first semiconductor board according to the fifth embodiment will be described hereinafter. The same reference signs will be assigned to components that are the same as those of the above described endoscope system1according to the first embodiment, and detailed description thereof will thus be omitted.

Main Parts of First Semiconductor Board

FIG.13is a schematic diagram illustrating a functional configuration of the main parts of the first semiconductor board according to the fifth embodiment. A first semiconductor board121D illustrated inFIG.13further includes an adjuster304D and a second generator305, in addition to the above described configuration of the first semiconductor board121A according to the second embodiment.

The adjuster304D includes a resistor R5and a resistor R6, in addition to the above described Configuration of the adjuster304C according to the fourth embodiment. The resistor R5and the resistor R6are electrically connected to signal lines that transmit power source voltage VDD and a direct current component DC1generated by the second generator305described later, and output values divided from the power source voltage VDD and direct current component DC1.

the basis of the power source voltage VDD input from the control device5, the second generator305generates a direct current component DC1for driving an imaging element120D, and outputs this direct current component DC1to the fourth semiconductor hoard124and the adjuster304D. The second generator305is implemented by use of, for example, a regulator or a charge pump circuit. In this fifth embodiment, the second generator305functions as a voltage generator.

The fifth embodiment described above enables a part causing poor connection to be identified externally because the switch302outputs, by selective switching, at least one of an imaging signal Vout and an internal signal.

Furthermore, the fifth embodiment enables reduction in the diameter of the endoscope2because: the second generator305generates, on the basis of power source voltage VDD input from the control device5, a direct current component DC1for driving the imaging element120D, and outputs this direct current component DC1to the fourth semiconductor board124and adjuster304D; and the number of signal lines in the transmission cable200is thereby able to be reduced.

Sixth Embodiment

A sixth embodiment will be described next. In the third embodiment described above, only the first semiconductor board121B includes the switch302and adjuster304provided thereon, but in this sixth embodiment, a switch and an adjuster are provided on each semiconductor board. A configuration of an imaging element according to the sixth embodiment will be described hereinafter. The same reference signs will be assigned to components that are the same as those of the above described endoscope system1according to the first embodiment and the above described first semiconductor board121B according to the third embodiment.

Main Parts of Imaging Element

FIG.14is a schematic diagram illustrating a functional configuration of main parts of the imaging element according to the sixth embodiment. An imaging element120E illustrated inFIG.14includes the first semiconductor board121B, a second semiconductor board122E, and a third semiconductor board123E.

Each of the se and semiconductor board122E and third semiconductor board123E further includes a switch302and an adjuster304, in addition to the above described configuration of the second semiconductor board122or the third semiconductor board123according to the first embodiment.

The sixth embodiment described above enables any part causing interlayer poor connection to be identified because the switch302is arranged on each of the first semiconductor board121B, the second semiconductor board122E, and the third semiconductor board123E.

In the sixth embodiment, the switch302is arranged on each of the first semiconductor board121B, the second semiconductor board122E, and the third semiconductor board123E, but without being limited to this configuration, any of these switches302may be omitted as appropriate. For example, the switches302on the first semiconductor board121B and third semiconductor board123E may be omitted, or the switch302on the second semiconductor board122E may be omitted. Of course, any of the adjusters304may also be omitted as appropriate.

Seventh Embodiment

A seventh embodiment will be described next. In the first embodiment described above, the switch302is provided on the first semiconductor board121, but in this seventh embodiment, a switch and an adjuster are provided on a fourth semiconductor board. A configuration of an imaging element according to the seventh embodiment will be described hereinafter. The same reference signs will be assigned to components that are the same as those of the above described endoscope system1according to the first embodiment and the above described first semiconductor board121B according to the third embodiment.

Main Parts of Imaging Element

FIG.15is a schematic diagram illustrating a functional configuration of main parts of the imaging element according to the seventh embodiment. An imaging element120F illustrated inFIG.15includes the first semiconductor board121B, the above described second semiconductor board122E according to the sixth embodiment, the third semiconductor board123, and a fourth semiconductor board124F.

The fourth semiconductor board124F includes a timing generator (TG)126, an amplifier127, the switch302, and the adjuster304, in addition to the above described configuration of the fourth semiconductor board124according to the first embodiment.

According to a synchronization signal SYNC and a clock signal CLK separated by the separator300via the first semiconductor board121B, second semiconductor board122E, and third semiconductor board123, the TG126controls the timing of reading by the light receiver125; the amplifier127; and each unit of the imaging element120F.

The amplifier127amplifies a synchronization signal SYNC and a clock signal CLK input via the adjuster304and switch302and outputs the amplified synchronization signal SYNC and clock signal CLK. Furthermore, the amplifier127amplifies an imaging signal Vout input from the light receiver125and outputs the amplified imaging signal Vout. The amplifier127is implemented by use of a buffer circuit, for example.

The imaging element120F configured as described above enables testing of whether or not a failure is occurring in any of the semiconductor boards by causing each semiconductor board to output a signal according to plural test modes, similarly to the above described first embodiment.

FIG.16is a diagram illustrating correspondence between test modes, output signals output from the imaging element120F, determination results, and state results indicating states of the imaging element120F.FIG.17is a diagram associating between the test modes, the determination results, and defective parts that are able to be presumed to be defective from the determination results.

As illustrated inFIG.16andFIG.17, the control unit55causes the display device4to display any defective parts according to output results for different test modes. For example, as illustrated inFIG.17, in a case where each of the output results for a first test mode to a seventh test mode is “good”, the control unit55causes the display device4to display information indicating that the imaging element120F is normal. In contrast, in a case where the output result for the first test mode is “not good” and the output results for the second test mode to the seventh test mode are “good”, the control unit55causes the display device4to display information indicating that a failure is occurring at the fourth semiconductor board124F. A user is thereby able to identify any defective part of the imaging element120F by checking the information displayed by the display device4.

The seventh embodiment described above enables any part causing interlayer poor connection to be identified because the switch302is arranged on each of the first semiconductor board121B, the second semiconductor board122E, and the fourth semiconductor board124F.

In the seventh embodiment, the switch302is arranged on each of the first semiconductor board121B, the second semiconductor board122E, and the fourth semiconductor board124F, but without being limited to this configuration, any of the switches302may be omitted as appropriate. For example, the switch302of the first semiconductor board121B may be omitted, or the switch302of the second semiconductor board122E may be omitted. Of course, any of the adjusters304may also be omitted as appropriate.

Other Embodiments

Various embodiments may be formed by combination, as appropriate, of plural components disclosed with respect to the above described endoscope systems according to the first to seventh embodiments of the present disclosure. For example, some of the components described with respect to the endoscope system/systems according to any of the above described embodiments of the present disclosure may be eliminated. Furthermore, any components described with respect to the endoscope system/systems according to any of the above described embodiments of the present disclosure may be combined as appropriate.

Furthermore, in the endoscope systems according to the first to seventh embodiments of the present disclosure, the first generator301generates a switching signal on the basis of a test pattern embedded in a synchronization signal SYNC, but the generating of the switching signal is not limited to this example. For example, the first generator301may generate a switching signal on the basis of a voltage value of power source voltage input from the outside. In this case, the first generator301may be implemented by use of, for example, an A/D conversion circuit and a voltage detection circuit, and may output a switching signal in a case where a predetermined voltage (for example, 3 V or less) is detected, the predetermined voltage not being the voltage value of the power source voltage input from the outside, for example, 3.3 V. Of course, the connection terminal T4may be configured to enable bidirectional communication, and in a case where an imaging signal Vout is input, the switch302may output the imaging signal Vout to the outside; and in a case where an external signal is input via the connection terminal T4, the switch302may cause the connection terminal T4to output an internal signal.

Furthermore, the imaging elements according to the first to seventh embodiments of the present disclosure may each include a probing pad provided on the light receiving surface of the fourth semiconductor board, the probing pad being a pad with which a testing probe is to be brought into contact. In this case, after testing of interlayer connections between the semiconductor boards is ended, any exposed part of the probing pad may be sealed with a resin, for example. Furthermore, the “units” described above with respect to the endoscope systems according to the first to seventh embodiments of the present disclosure may be read as “means” or “circuits”. For example, the control unit may be read as a control means or a control circuit.

In the description of the flowcharts in this specification, the context of the processing among the steps is disclosed by use of expressions, such as “firstly”, “thereafter”, and “subsequently”, but sequences in the processing needed for implementation of the disclosure are not uniquely defined by these expressions. That is, the sequences in the processing in the flowcharts described in this specification may be modified as far as no contradiction arises from the modification.

Some of embodiments of the present application have been described in detail hereinbefore on the basis of the drawings, but these are just examples. The disclosure may be implemented in various other modes modified or improved on the basis of the modes described through the present disclosure and knowledge of those skilled in the art.

According to the present disclosure, a part causing poor connection is able to be identified externally.