Control cell management method of ATM switching system

A control cell management method and apparatus of switching system are disclosed. The invention includes storing an address of a pertinent control cell reception buffer buffering a first-arrived new control cell, when the new control cell is received during a transmission of output control cells. Reception processing of the pertinent control cell reception buffer is then performed using the stored address when the transmission of the output control cells is finished.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an Asynchronous Transfer Mode (ATM) switching system and, in particular, to a control cell management method of an ATM switching system.

2. Background of the Related Art

An ATM communication divides a message into a plurality of ATM cells that each have 53 bytes. Once the cells are formatted, they are communicated through a transmission medium.

FIG. 1is a block diagram illustrating a general ATM. The ATM switching system10includes an access switching apparatus11,14, an interconnection network apparatus12, and an operation and maintenance apparatus13. The access switching apparatus11,14performs a switching function with the other base stations1,2,3to which it is connected, the interconnection network apparatus12interconnects each apparatus of the ATM switching system, and the operation and maintenance apparatus13manages and maintains the ATM switching system.

Generally, an ATM cell can be categorized as a user cell, for data transmission between users, and a control cell that processes and controls various calls in order to transmit the user cell. When base station1transmits a user cell, the user cell is transmitted to the access switching apparatus11of the ATM switching system10, is routed in the interconnection network apparatus12, and arrives in a particular destination after passing the access switching apparatus14.

The control cell can be further categorized as a signaling cell, which transmits a control signal between ATM switching systems, and an Inter Processor Communication (IPC) cell that performs communication between each apparatus11,12,13,14of the ATM switching system. The control cell is transmitted to a processor of the access switching apparatus11and performs a function, such as a call connection, a call release, a state report of the access switching apparatus11, within the access switching apparatus.

A signaling cell can be further categorized as a signaling cell for call processing, a contact, a contact acceptance, and a setting. Signaling cells are used for a point-to-point contact set, a point-to-point release, a point-to-point release completion, an inquiry about a state of a pertinent apparatus, a restart, a restart acceptance in connection-management, an addition of another point, an addition acceptance of another point in association of one point-to-multipoint, a removal of the point, and a removal acceptance of the point.

An IPC cell can be used differently in each ATM switching system. An IPC cell is mainly used for communication between the operation and maintenance apparatus13, managing the whole ATM switching system10, and each apparatus of the ATM switching system10. The IPC cell has information regarding the states, inspection, contact registration, and release of each apparatus of the ATM switching system10.

The access switching apparatus11,14of the ATM switching system10is constructed so as to include a plurality of the switching functions of the other base stations. Each access switching apparatus11,14is functionally constructed to correspond with the base station with which it is connected.

FIG. 2is a block diagram illustrating signaling cells for transmission and reception with base stations1,2and IPC cells for transmission and reception with internal devices of the ATM switching system10, when the access switching apparatus11is connected to two other base stations1,2.

FIG. 3is a block diagram illustrating internal units of the access switching apparatus11ofFIG. 1. The access switching apparatus11includes control (signaling) cell transmission and reception buffers23a,23b,24a,24bthat transmit and receive signaling cells with base stations1,2, respectively. Access switching apparatus11has control cell (IPC) transmission and reception buffers23c,23d,24c,24dthat transmit and receive IPC cells with the apparatuses of the ATM switching system10. It has a signaling control cell First-In First-Out (FIFO) management unit22that manages the control (signaling) of the cell transmission and reception buffers23a,23b,24a,24band the cell transmission and reception buffers23c,23d,24c,24d. Additionally, it has a processor21that controls the overall operation of the access switching apparatus11.

In more detail, the first control (signaling) cell transmission FIFO23a(hereinafter, a buffer is referred to as a FIFO) buffers a signaling cell to be transmitted to base station1, the second control (signaling) cell transmission FIFO23bbuffers a signaling cell to be transmitted to base station2, the first control (signaling) cell reception FIFO24abuffers a signaling cell received from base station1, and the second control (signaling) cell reception FIFO24bbuffers a signaling cell received from base station2. Third and fourth control (IPC) cell transmission FIFOs23c,23dbuffer IPC cells to be transmitted to particular internal devices of the ATM switching system10, respectively. Third and fourth control (IPC) cell reception FIFOs24c,24dbuffer IPC cells received from particular internal devices of the ATM switching system10, respectively.

As depicted inFIG. 3, the access switching apparatus11accepts two access lines, buffers the signaling cells and the IPC cells in the eight control cell transmission and reception FIFOs23a˜23d,24a˜24d, and transmits the signaling cells and the IPC cells between the eight control cell transmission and reception FIFOs23a˜23d,24a˜24dand processor21, by jointly controlling a data bus with the processor21. Processor21can transmit or receive only one control cell at a time using the data bus. When communicating cells between the eight FIFOs23a–23d,24a–24dand the processor21, the cells must be prioritized and the bus arbitrated to communicate the cells across the shared bus according to their respective priorities.

Processor21uses a Universal Test Operation Physical Layer Protocol Interface for ATM (UTOPIA) protocol as a master. The UTOPIA protocol is used between an ATM layer device and a physical layer device. The protocol has been standardized in an ATM forum and is capable of performing a seamless communication without affecting an ATM layer, which is a superior layer. The seamless communication is possible, regardless of the interface with a physical layer, due to a clarifying relationship between the ATM layer and a physical layer provided by the UTOPIA protocol.

When there is a control cell to be transmitted, the processor21transmits the control cell to the signaling control cell FIFO management unit22, through an 8-bit data bus, using the UTOPIA interface.

Generally, the transmission of control cells precedes the reception of control cells in priority. Accordingly, when there are control cells to be received during the transmission of control cells, the cells to be received have to wait in the control cell reception FIFO24a˜24d.

After the transmission of the control cells is finished, the signaling control cell FIFO management unit22notifies the control cell reception FIFO, buffering the most recently arrived control cell, and requests a physical layer address of the pertinent control cell reception FIFO. Processor21selects the pertinent control cell reception FIFO to communicate the most recently arrived control cell.

As described above, when a control cell arrives during the transmission of other control cells, the related art ATM switching system does not recognize a first-arrived control cell but recognizes the most recently arrived control cell. When the transmission of control cells is finished, the reception processing of control cells starts with the most recently arrived control cell. Accordingly, the reception processing reverses the order of arrival for the control cells and may unduly delay their communication to the processor21. In other words, processing of a first-arrived control cell in a pertinent control cell reception FIFO can not be performed until all other control cells that subsequently arrived in the other control cell reception FIFOs are processed.

Because the processing of control cells is not performed according to their order of arrival, the control signaling processing speed of the access switching apparatus and the performance of the ATM switching system are diminished.

SUMMARY OF THE INVENTION

An object of the present invention is to improve the performance of an ATM switching system.

Another object is to efficiently manage control cells in their communication between a processor and an ATM processing apparatus using a shared data bus.

Another object of the present invention is to minimize the delay of control cell processing by inspecting the arrival times of control cells in the control cell reception FIFOs, storing an address of a pertinent control cell FIFO buffering a first-arrived control cell, and starting the reception processing with the FIFO buffering the first-arrived control cell, when the transmission of control cells is finished.

In order to achieve the objects of the present invention, there is provided a control cell management method of an ATM switching system including determining priority in the transmission and reception of control cells by a processor, storing an address of a pertinent control cell reception FIFO buffering a first-arrived new control cell, and performing reception processing from the pertinent control cell reception FIFO buffering the first-arrived new control cell, using the stored address when the transmission of control cells is finished.

In order to achieve the objects of the present invention, there is provided a control cell management method of an ATM switching system in accordance with another embodiment of the present invention including determining priority in the transmission and reception of control cells by a processor, when control cells are transmitted and received using a shared data bus between the processor and ATM processing units, inspecting the arrival time of new control cells in each control cell reception FIFO using the data bus, storing an address of a pertinent control cell reception FIFO buffering a first-arrived control cell, receiving the first-arrived control cell from the pertinent control cell reception FIFO, and inspecting the arrival time of new control cells starting from a control cell reception FIFO next to the pertinent control cell reception FIFO.

In order to achieve the objects of the present invention, there is provided a control cell management method of an ATM switching system in accordance with still another embodiment of the present invention including inspecting the arrival time of new control cells in each control cell reception FIFO by a processor by using one data bus between the processor and a FIFO management unit for an ATM process, storing an address of a pertinent control cell reception FIFO buffering a first-arrived control cell, transmitting the stored address of the pertinent control cell reception FIFO to the processor when the transmission is finished, setting a physical layer address of the pertinent control cell reception FIFO by the processor, fetching the first-arrived control cell from the pertinent control cell reception FIFO by using the set physical layer address, transmitting the fetched first-arrived control cell to the processor through the data bus in an available state, and inspecting the arrival times of new control cells starting from a control cell reception FIFO next to the pertinent control cell reception FIFO.

The objects of the present invention may be achieved in whole or in part by a control cell processing method of a switching system, including identifying a first buffer that receives a first-arrived control cell; and communicating the first-arrived control cell to a processor for processing using a shared data bus, before processing a later-arrived control cell.

The objects of the present invention may be further achieved in whole or in part by a control cell switching apparatus, including a processor that processes control cells communicated by the apparatus; a plurality of receive buffers that buffer control cells communicated by an external device to the processor; a shared data bus between the processor and the receive buffers for communicating the control cells; and an input and output (I/O) controller that prioritizes the use of the shared data bus by the receive buffers, wherein the I/O controller identifies a first receive buffer of the receive buffers that receives a first-arriving control cell and communicates the first-arriving control cell to the processor using the shared data bus, before communicating a later-arriving control cell.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring now toFIGS. 3–5D, a UTOPIA level2protocol is used between a processor21and a signaling control cell FIFO management unit22of the access switching apparatus11. The signaling control cell FIFO management unit22includes devices performing functions related to the transmission of control cells from the processor21to a pertinent control cell transmission FIFO, as depicted inFIGS. 4A˜4C. Additionally, it includes devices performing functions related to the reception of control cells from each control cell reception FIFO, as depicted inFIGS. 5A˜5D.

FIG. 4Ais a block diagram illustrating a device of a signaling control cell FIFO management unit22that generates a signal (WCav) indicating the transmission preparation of each control cell transmission FIFO23a–23d.FIG. 4Bis a table illustrating a method for selecting a control cell transmission FIFO to be written a control cell, in accordance with a physical layer address and a transmission enable signal (WEnb) outputted from the processor21.FIG. 4Cis a block diagram illustrating a device of the signaling control cell FIFO management unit22that selects a control cell to be transmitted, in accordance with a transmission enable signal (WEnb) outputted from the processor21.

FIG. 5Ais a block diagram illustrating a device of the signaling control cell FIFO management unit22that generates a signal (RCav) indicating whether any of cell reception FIFOs24a˜24dhas a received control cell.FIG. 5Bis a block diagram illustrating an arbiter of the signaling control cell FIFO management unit22that arbitrates the reception of control cells between the control cell reception FIFOs24a˜24d, by examining each control cell reception FIFO24a˜24dusing a rotational method.FIG. 5Cis a table illustrating a method for selecting a pertinent control cell reception FIFO to read a control cell to the processor21, in accordance with a physical layer address and a reception enable signal (REnb) outputted from the processor21.FIG. 5Dis a block diagram illustrating a device of the signaling control cell FIFO management unit22selecting a control cell to be received, in accordance with a reception enable signal (REnb) outputted from the processor21.

FIG. 6is a flow chart illustrating a control cell management method of an ATM switching system. Priority in the transmission and reception of the control cells within the FIFOs is examined using the rotational method to inspect the arrival of control cells. An address of a pertinent control cell reception FIFO that buffers a first-arrived control cell is stored. When the transmission of control cells is finished, the processor21starts a reception processing of the first-arrived control cell, which arrived during the transmission processing, and then inspects the arrival of control cells starting from the control cell reception FIFO next to the pertinent control cell reception FIFO.

Processor21determines the transmission and reception priority of control cells by operating as a master, as shown at ST11. When higher priority is given to the transmission of control cells than to the reception of control cells, processor21performs the transmission of control cells first. The transmission operation will now be described in more detail.

A first control (signaling) cell transmission FIFO23a, a second control (signaling) cell transmission FIFO23b, a third control (IPC) cell transmission FIFO23c, and a fourth control (IPC) cell transmission FIFO23doutput the WCav1, WCav2, WCav3, WCav4signals, respectively. These signals indicate whether the respective FIFOs are ready to receive a cell from the processor21. As depicted inFIG. 4A, the signaling control cell FIFO management unit22performs an AND logic operation after receiving the WCav1, WCav2, WCav3, WCav4signals and outputs a write ready signal (WCav) to the processor21.

When all of the control cell transmission FIFOs23a˜23dare ready to receive control cells, the processor21selects a physical layer address of a pertinent control cell transmission FIFO and transmits a physical layer address selection signal (SelAddr[1:0]) with the selected physical layer address to the signaling control cell FIFO management unit22. A transmission enable signal (WEnb) is also transmitted to the signaling control cell FIFO management unit22. The signaling control cell FIFO management unit22selects a pertinent control cell transmission FIFO to receive the control cell, in accordance with the physical layer address selection signal (SelAddr[1:0]) and transmission enable signal (WEnb). The control cell is transmitted to the pertinent control cell transmission FIFO via the processor data bus30and the Tx data bus31, in accordance with the transmission enable signal (Wenb).

As depicted inFIG. 4B, when a physical layer address selection signal (SelAddr) and a transmission enable signal (WEnb) are “00” and “1”, respectively, the signaling control cell FIFO management unit22outputs a transmission enable signal (WEnb1) to the first control (signaling) cell transmission FIFO23a. According to this, a control cell is transmitted from the processor21to the first control (signaling) cell transmission FIFO23a. The Wenb signal enables the eight bit data to move from the processor data bus30to the Tx data bus31, as illustrated inFIG. 4C.

While the processor21transmits the control cell as shown at ST12, the signaling control cell FIFO management unit22inspects the arrival of new control cells by examining the four control cell reception FIFOs24a˜24dusing the rotational method, as shown at ST13. When control cells arrive, the first control (signaling) cell reception FIFO24a, second control (signaling) cell reception FIFO24b, third control (IPC) cell reception FIFO24c, and fourth control (IPC) cell reception FIFO24doutput the RCav1RCav2, RCav3, RCav4) signals, respectively. These signals indicate the existence of received cells to be read to the signaling control cell FIFO management unit22.

As depicted inFIG. 5A, the signaling control cell FIFO management unit22performs an OR logic operation of the RCav1, RCav2, RCav3, RCav4signals. By logically OR ing these signals, the signaling control cell FIFO management unit22can determine whether there are newly arrived control cells to be communicated to the processor21. If so, the OR circuit outputs a signal (RCav) to the processor21. In addition, as depicted inFIG. 5B, the signaling control cell FIFO management unit22selects an address of the control cell reception FIFO buffering the first-arrived control cell, as shown at ST14. The selected address is stored in a register of the signaling control cell FIFO management unit22, as shown at ST15.

When the transmission of control cells by the processor21is finished, as shown at ST16, the signaling control cell FIFO management unit22transmits the stored address of the pertinent control cell reception FIFO to the processor21and requests reception processing, as shown at ST17. More descriptively, when the transmission of control cells is finished, the processor21recognizes there is a control cell to be read due to the signal (RCav) outputted from the signaling control cell FIFO management unit22. The signaling control cell FIFO management unit22transmits a physical layer address request signal (ReqAddr[1:0]) to the processor21that requests a physical layer address of the pertinent control cell reception FIFO buffering the first-arrived control cell.

As depicted inFIG. 5C, when the control cell reception FIFO buffering the first-arrived control cell is the third control (IPC) cell reception FIFO24c, the processor21outputs a physical layer address selection signal (SelAddr[1:0]) as “10” to select a physical layer address of the third control (IPC) cell reception FIFO24c. In addition, processor21outputs a read enable signal (REnb) as “1” to the signaling control cell FIFO management unit22. The signaling control cell FIFO management unit22sets the physical layer address of the third control (IPC) cell reception FIFO24cby outputting a signal (REnb3) as an active state in accordance with the signals (SelAddr[1:0], REnb), as shown at ST18. As depicted inFIG. 5D, the signaling control cell FIFO management unit22reads the control cell from the third control (IPC) cell reception FIFO24con Rx data bus32and transmits the control cell to the processor data bus30, under the control of the Renb signal.

While processor21receives the control (IPC) cell from the third control (IPC) cell reception FIFO24c, the signaling control cell FIFO management unit22inspects the arrival of control cells starting from the fourth control (IPC) cell reception FIFO24d, which is the next adjacent control (IPC) cell reception FIFO, as shown at ST19.

FIG. 7is a state diagram of the arbiter ofFIG. 5B. The RCav1, RCav2, RCav3, RCav4signals provided as inputs to the arbiter are identified in association with each state transition, as the first four values preceding the “1.” The physical layer address request signal (ReqAddr[1:0]) generated by the arbiter in response to the four-bit input is identified by the two digits following the “1.” Accordingly, the arbiter generates a two bit output in response to the four bit input.

The arbiter can have four states S1, S2, S3, and S4in accordance with input signals RCav1, RCav2, RCav3, RCav4. For example, when the RCav1, RCav2, RCav3, and RCav4signals have the values of 1, 0, 0, and 0, respectively, while in the S1state, the arbiter generates an output of “00.” In more detail, when only the RCav1signal among the RCav1, RCav2, RCav3, and RCav4signals has a value of “1”, it means a control cell has arrived in the first control (signaling) cell reception FIFO24a, which has outputted the RCav1signal to indicate this circumstance. The arbiter recognizes that the control cell has arrived in the first control (signaling) cell reception FIFO24aand outputs a ReqAddr[1:0] signal bit pattern of “00,” to request a physical layer address of the first control (signaling) cell reception FIFO24a.

In step ST19, processing of the control cell in the third control (IPC) cell reception FIFO24cis performed and, therefore, the arbiter is in the S3state. While in state S3, the signaling control cell FIFO management unit22determines whether a newly arrived control cell has been received by any of the control cell reception FIFOs24a–24d, beginning with a determination in reception FIFO24d. After checking reception FIFO24d, a determination is sequentially made in reception FIFOs24a–24c.

When a bit pattern of “1XXX”, representing the values of RCav4, RCav3, Rcav2, RCav1, respectively, is inputted to the arbiter in the S3state, the arbiter recognizes that a new control cell has arrived in the fourth control (IPC) cell reception FIFO24d. The arbiter generates a bit pattern of “11” to identify the address of the fourth control (IPC) cell reception FIFO24dand makes a transition to the S4state. When a bit pattern of “0XX1” is provided to the arbiter, the arbiter recognizes that a new control cell has not arrived in the fourth control (IPC) cell reception FIFO24dbut has arrived in the first control (signaling) cell reception FIFO24a. Therefore, the arbiter outputs a bit pattern of “00” to identify an address of the first control (signaling) cell reception FIFO24aand makes a transition to the S1state.

As described above, the arbiter inspects the arrival of control cells, performs a reception processing for a control cell reception FIFO buffering a first-arrived control cell, and inspects the arrival of new control cells starting from a control cell reception FIFO next to the control cell reception FIFO presently having a control cell being processed.

As described above, the control cell management method of the ATM switching system in accordance with the present invention inspects the arrival of control cells in the control cell reception FIFO during the transmission of control cells, stores an address of a pertinent control cell reception FIFO buffering a first-arrived control cell, and starts reception processing from the pertinent control cell reception FIFO buffering the first-arrived control cell, when the transmission of control cells is finished. Accordingly, the control cell management method of the ATM switching system in accordance with the present invention can improve a processing speed of an access switching apparatus and the performance of an ATM switching system by minimizing delay in reception processing of control cells.