Semiconductor device having contact structures

A semiconductor device includes: a substrate having a plurality of active regions; a plurality of bit lines extending in a first direction, the plurality of bit lines being separate from the substrate with an insulating layer therebetween; a plurality of first insulating lines extending in a second direction that is different from the first direction, wherein the plurality of first insulating lines intersect the plurality of bit lines and have upper surfaces having levels which are higher than those of upper surfaces of the plurality of bit lines relative to the substrate; and a plurality of first contact structures connected to the plurality of active regions, the plurality of first contact structures being disposed in an area defined by the plurality of bit lines and the plurality of first insulating lines.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2014-0044424, filed on Apr. 14, 2014, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a landing pad.

Elements of semiconductor devices have been reduced or minimized according to the high integration of the semiconductor devices. Accordingly, the width of an interconnection line between the elements and the cross-sectional area of a contact plug that is connected between the elements has been gradually reduced. Due to this, when a lower capacitor electrode is connected to a contact plug having a small cross-sectional area, a contact area with the contact plug may be limited and thus there may be a limit in lowering contact resistance.

SUMMARY

The inventive concept provides a semiconductor device in which a contact plug having a small cross-sectional area is improved and thus contact resistance occurring when connecting the contact plug to a lower capacitor electrode is lowered.

According to an aspect of the inventive concept, there is provided a semiconductor device including: a substrate having a plurality of active regions; a plurality of bit lines extending in a first direction, the plurality of bit lines being separate from the substrate with an insulating layer therebetween; a plurality of first insulating lines extending in a second direction that is different from the first direction, wherein the plurality of first insulating lines intersect the plurality of bit lines and have upper surfaces having levels which are higher than those of upper surfaces of the plurality of bit lines relative to the substrate; and a plurality of first contact structures connected to the plurality of active regions, the plurality of first contact structures being disposed in an area defined by the plurality of bit lines and the plurality of first insulating lines.

The semiconductor device may further include: a plurality of second insulating lines extending in a third direction that is different from the second direction, the plurality of second insulating lines intersecting the plurality of first insulating lines; and a plurality of second contact structures connected to the plurality of first contact structures, the plurality of second contact structures being disposed in an area isolated by the plurality of first insulating lines and the plurality of second insulating lines, wherein one of the first contact structures is disposed to be connected to one of the second contact structures corresponding thereto.

The levels of upper surfaces of the plurality of first insulating lines may be approximately equal to those of upper surfaces of the plurality of second insulating lines.

An upper surface of each of the plurality of second contact structures may be connected to a lower electrode of a capacitor.

The semiconductor device may further include an insulating spacer disposed at a sidewall of each of the plurality of bit lines, wherein the insulating spacer is formed of a same material as the plurality of first insulating lines.

The semiconductor device may further include a plurality of word lines buried in the substrate, wherein the plurality of first insulating lines overlap with the plurality of word lines.

The plurality of first contact structures may be formed of a same material as the plurality of second contact structures.

According to another aspect of the inventive concept, there is provided a semiconductor device including: a substrate having a plurality of active regions; a plurality of bit lines that intersect the plurality of active regions and extend in a first direction: a plurality of first insulating lines extending in a second direction that is different from the first direction; a plurality of first contact structures disposed in an area defined by the plurality of bit lines and the plurality of first insulating lines; a plurality of second insulating lines extending in a third direction that is different from the second direction; and a plurality of second contact structures filled in an area defined by the plurality of first insulating lines and the plurality of second insulating lines, wherein one of the second contact structures is disposed to be connected to one of the first contact structures corresponding thereto.

The plurality of second insulating lines may have a periodic structure based on the third direction.

The plurality of second insulating lines each may have a wavy structure based on the third direction.

The plurality of first contact structures each may have a horizontal cross-sectional area having a first size, and the plurality of second contact structures each may have a horizontal cross-sectional area having a second size that is larger than the first size.

At least one selected from a horizontal section of the first contact structures and a horizontal section of the second contact structures may have a parallelogram shape.

The semiconductor device may further include: an insulating pattern that defines a storage node hole for exposing an upper surface of each of the plurality of second contact structures; and a lower capacitor electrode connected to the upper surface of each of the plurality of second contact structures, the lower capacitor electrode being formed in the storage node hole.

The insulating pattern may include: a plurality of third insulating lines that contact the first insulating lines and extend in a fourth direction; and a plurality of fourth insulating lines that contact the upper surfaces of the second insulating lines and extend in a fifth direction.

The fourth direction may be the same as the second direction, and the fifth direction may be the same as the third direction.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. In the drawings, the same elements are denoted by the same reference numerals and a repeated explanation thereof will not be given.

Hereinafter, the inventive concept will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the inventive concept to one of ordinary skill in the art.

It will be understood that, although the terms “first”, “second”, “third”, etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of exemplary embodiments. For example, a first element may be referred to as a second element, and likewise, a second element may be referred to as a first element without departing from the scope of the inventive concept.

It should also be noted that in some alternative implementations, operations may be performed out of the sequences depicted in the flowcharts. For example, two operations shown in the drawings to be performed in succession may in fact be executed substantially concurrently or even in reverse of the order shown, depending upon the functionality/acts involved.

Modifications of shapes illustrated in the accompanying drawings may be estimated according to manufacturing processes and/or process variation. Accordingly, embodiments of the inventive concept should not be construed as being limited to a specific shape of an area illustrated in the present specification and should include a change in shape which may be caused in manufacturing processes. It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected, or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout the description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Accordingly, the cross-sectional view(s) illustrated herein provide support for a plurality of devices according to various embodiments described herein that extend along two different directions in a plan view and/or in three different directions in a perspective view. For example, when a single active region is illustrated in a cross-sectional view of a device/structure, the device/structure may include a plurality of active regions and device structures thereon, as would be illustrated by a plan view of the device/structure.

FIG. 1Ais a schematic layout of a cell array area of a semiconductor device10according to an embodiment of the inventive concept.

Referring toFIG. 1A, the semiconductor device10includes a plurality of active regions AC formed in a substrate100. The plurality of active regions AC may be separately disposed, and each of the plurality of active regions AC may have a relatively long island shape having a major axis and a minor axis or vice versa.

A plurality of word lines WL extends parallel to one another across the active regions AC in a first direction. Although the first direction is the X-axis direction inFIG. 1A, the inventive concept is not limited thereto. The plurality of word lines WL may be buried in the substrate100.

A plurality of bit line structures BL are formed on the substrate100and extend across the plurality of active regions AC in a second direction, which is different from the first direction. Although the second direction is the Y-axis direction inFIG. 1A, the inventive concept is not limited thereto. The plurality of bit line structures BL each include a bit line and a spacer formed at a sidewall of the bit line and are connected to the plurality of active regions AC via a plurality of direct contacts DC positioned under the bit line.

A plurality of first insulating lines110are formed on the plurality of bit line structures BL and extend parallel to one another in a third direction that is different from the second direction. Although the third direction is the X-axis direction inFIG. 1A, the inventive concept is not limited thereto. The plurality of first insulating lines110extend while covering upper surfaces and sidewalls of the plurality of bit line structures BL and the substrate100exposed between the plurality of bit line structures BL. Levels of upper surfaces of the plurality of first insulating lines110are higher than those of the upper surfaces of the plurality of bit line structures BL. In some embodiments, the third direction is the same as the first direction, and thus, the plurality of first insulating lines110may extend in the same direction as the plurality of word lines WL while overlapping the plurality of word lines WL. In some embodiments, the plurality of first insulating lines110each may have a fence shape.

A plurality of first contact structures120are formed in regions that are defined by the plurality of bit line structures BL and the plurality of first insulating lines110. The plurality of first contact structures120are disposed to be connected to the plurality of active regions AC. In some embodiments, when the plurality of bit line structures BL are not perpendicular to the plurality of first insulating lines110, a horizontal section of each of the plurality of first contact structures120may have a parallelogram shape. In some embodiments, when the plurality of bit line structures BL are perpendicular to the plurality of first insulating lines110, as illustrated inFIG. 1A, a horizontal section of each of the plurality of first contact structures120has a rectangular shape. In some embodiments, the plurality of first contact structures120may be arranged at regular intervals along sidewalls of the plurality of bit line structures and may also be arranged at regular intervals along sidewalls of the plurality of first insulating lines110. In some embodiments, the plurality of first contact structures120may be electrically connected to lower electrodes ST of capacitors. The plurality of first contact structures120may electrically connect the plurality of active regions AC to the lower electrodes ST of the capacitors.

A plurality of second insulating lines130are farmed on the plurality of first contact structures120and the plurality of bit line structures BL and extend parallel to one another in a fourth direction that is different from the second direction and the third direction. Although the fourth direction is a direction between the X-axis direction and the Y-axis direction inFIG. 1A, the inventive concept is not limited thereto. The plurality of second insulating lines130cover upper surfaces and sidewalls of the plurality of bit line structures BL and portions of upper surfaces of the plurality of first contact structures120and contact sidewalls of the plurality of first insulating lines110. The plurality of second insulating lines130extend without bisecting the upper surfaces of the plurality of first contact structures120. Accordingly, only the upper surface of one first contact structure120formed in an area defined by a pair of adjacent bit line structures BL and a pair of adjacent first insulating lines110is exposed in an area defined by a pair of adjacent first insulating lines110and a pair of adjacent second insulating lines130. In some embodiments, levels of the upper surfaces of the plurality of second insulating lines130may be approximately equal to those of upper surfaces of the plurality of first insulating lines110. In some embodiments, the plurality of second insulating lines130may each have a fence shape.

A plurality of second contact structures140are formed in an area defined by the second insulating lines130and the first insulating lines110. One second contact structure140is disposed to be connected to one first contact structure120corresponding thereto. The second contact structures140are electrically connected to the active regions AC via the first contact structures120. When the third direction is the X-axis direction and the fourth direction is a direction between the X-axis direction and the Y-axis direction, a cross-section of each of the second contact structures140may have a parallelogram shape. In some embodiments, each of the first contact structures120may have a horizontal cross-sectional area of a first size, and each of the second contact structures140may have a horizontal cross-sectional area of a second size that is larger than the first size. In some embodiments, the second contact structures140may be arranged at regular intervals along sidewalls of the first insulating lines110and may also be arranged at regular intervals along sidewalls of the second insulating lines130.

An insulating pattern (not shown), which defines a storage node hole for exposing a part of the upper surface or the entire upper surface of each of the second contact structures140, may be formed on the upper surfaces of the first insulating lines110, the upper surfaces of the second insulating lines130, and the upper surfaces of the second contact structures140. One storage node hole is formed so that only the upper surface of one of the second contact structure140corresponding thereto is exposed. The upper surfaces of the second contact structures140, each of which is exposed in the storage node hole, may be connected to the lower electrodes ST of the capacitors. The lower electrodes ST of the capacitors are electrically connected to the first contact structures120and the active regions AC via the second contact structures140.

In this manner, by increasing the levels of the first insulating lines110defining the first contact structures120to use the first insulating lines110as a structure defining the second contact structures140on the first contact structures120, misalignment and contact failure between the first contact structures120and the second contact structures140may be greatly improved.

FIG. 1Bis a schematic layout of a cell array area of a semiconductor device15according to another embodiment of the inventive concept. InFIG. 1B, the same reference numerals asFIG. 1Adenote the same elements asFIG. 1A. Thus, repeated explanations thereof will not be given.

Referring toFIG. 1B, the shapes of second insulating lines131and the shapes of second contact structures141are different from those of the semiconductor device10described with reference toFIG. 1A.

The plurality of second insulating lines131are formed on the first contact structures120and the bit line structures BL and extend parallel to one another with a wave structure in the fourth direction that is different from the second direction and the third direction. Although the fourth direction is the Y-axis direction inFIG. 1B, the inventive concept is not limited thereto. In addition, although the second insulating lines131ofFIG. 1Beach have a wave structure or a zigzag structure, the inventive concept is not limited thereto. For example, the second insulating lines131of the semiconductor device15may have any shape having a periodic structure.

The second insulating lines131cover upper surfaces and sidewalls of the bit line structures BL and portions of upper surfaces of the first contact structures120, and contact sidewalls of the first insulating lines110. The second insulating lines131extend without bisecting the upper surfaces of the first contact structures120. Accordingly, only the upper surface of one first contact structure120formed in an area defined by a pair of adjacent bit line structures BL and a pair of adjacent first insulating lines110is exposed in an area defined by a pair of adjacent first insulating lines110and a pair of adjacent second insulating lines131.

The plurality of second contact structures141are formed in an area defined by the second insulating lines131and the first insulating lines110. Because the second insulating lines131of the semiconductor device15each have a wave structure or a zigzag structure, each of the upper surfaces of the second contact structures141, which is defined by the second insulating lines131, may have a bent rectangular shape or a bent parallelogram shape. One of the second contact structures141is disposed to be connected to one of the first contact structures120corresponding thereto. The second contact structures141are electrically connected to the active regions AC via the first contact structures120. In some embodiments, each of the first contact structures120may have a horizontal cross-sectional area of a first size, and each of the second contact structures141may have a horizontal cross-sectional area of a second size that is larger than the first size. In some embodiments, the second contact structures141may be arranged at regular intervals along sidewalls of the first insulating lines110and may also be arranged at regular intervals along sidewalls of the second insulating lines131.

In some embodiments, an insulating pattern (not shown), which defines a storage node hole for exposing a part of the upper surface or the entire surface of each of the second contact structures141, may be formed on the upper surface of each of the first insulating lines110, the upper surface of each of the second insulating lines131, and the upper surface of each of the second contact structures141. One storage node hole is formed so that only the upper surface of one of the second contact structures141corresponding thereto is exposed. The upper surfaces of the second contact structures141, each of which is exposed in the storage node hole, may be connected to the lower electrodes ST of the capacitors. The lower electrodes ST of the capacitors are electrically connected to the first contact structures120and the active regions AC via the second contact structures141.

In this manner, because the second contact structures141, which are defined by the second insulating lines131each having a periodic structure, may make improved or maximum contact with the first contact structures120and the lower capacitor electrodes ST, misalignment and contact failure may be greatly improved.

FIG. 1Cis a schematic layout of a cell array area of a semiconductor device20according to another embodiment of the inventive concept.FIG. 1Cillustrates a configuration in which some elements are added to the semiconductor device10ofFIG. 1Ato form a capacitor.

Referring toFIG. 1C, an insulating pattern150, which exposes a part of the upper surface or the entire upper surface of each of the second contact structures140, may be formed on the upper surface of each of the first insulating lines110, the upper surface of each of the second insulating lines130, and the upper surface of each of the second contact structures140. The insulating pattern150may include a plurality of third insulating lines153that contact the upper surfaces of the first insulating lines110and extend in a fifth direction, and a plurality of fourth insulating lines155that contact the upper surfaces of the second insulating lines130and extend in a sixth direction. An area, which is defined by a pair of adjacent third insulating lines153and a pair of adjacent fourth insulating lines155, is formed so that only the upper surface of one of the second contact structures140corresponding thereto is exposed.

In some embodiments, the fifth direction may be the same as the third direction, and the sixth direction may be the same as the fourth direction. In other words, the insulating pattern150, which includes the third insulating lines153and the fourth insulating lines155, may be formed to overlap with the first insulating lines110and the second insulating lines130.

In some embodiments, constituent materials of the third insulating lines153may be different from those of the fourth insulating lines155.

In some embodiments, a second horizontal cross-sectional area that is defined by the third insulating lines153and the fourth insulating lines155may be larger than a first horizontal cross-sectional area that is defined by the first insulating lines110and the second insulating lines130.

Upper surfaces of the second contact structures140, which are exposed by the insulating pattern150, which includes the third insulating lines153and the fourth insulating lines155, may be connected to the lower capacitor electrodes ST. An area defined by the insulating pattern150may have a round, oval, or parallelogram shape.

In this manner, because the semiconductor device20includes the insulating pattern150, which includes the third and fourth insulating lines153and155corresponding to the first and second insulating lines110and130, respectively, the second contact structures140may make improved or maximum contact with the lower capacitor electrodes ST, and thus, misalignment and contact failure may be greatly improved.

FIG. 2is a cross-sectional view of a main part of a semiconductor device30according to an embodiment of the inventive concept. A part denoted by “CA” is a cross-sectional view of a cell array area of the semiconductor device30, that is, a portion corresponding to an A-A′ line cross-section and a B-B′ line cross-section ofFIG. 1A, and a part denoted by “CORE/Peri” is a cross-sectional view of a core/peripheral area of the semiconductor device30.

Referring toFIG. 2, the semiconductor device30includes a substrate210including a plurality of active regions214, which are defined by a device isolation layer212, in the cell array area CA and the core/peripheral area CORE/Peri.

In some embodiments, the substrate210may be a semiconductor wafer. In some embodiments, the substrate210includes silicon (Si). In some other embodiments, the substrate210may include a semiconductor element, such as germanium (Ge), or a compound semiconductor, such as a silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the substrate210may have a silicon on insulator (SOI) structure. For example, the substrate210may include a buried oxide (BOX) layer. In some embodiments, the substrate210may include a conductive area, for example, a well doped with impurities or a structure doped with impurities. Also, the substrate200may have various device isolation structures such as a shallow trench isolation (STI) structure.

Various kinds of individual devices may be formed on the substrate210. The individual devices may include various microelectronic devices, such as a metal-oxide-semiconductor field effect transistor (MQSFET), a system large scale integration (LSI) circuit, an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active device, and a passive device. The individual devices may be electrically connected to the active regions214of the substrate210. Also, the individual devices each may be electrically isolated from another adjacent individual device by an insulating layer.

In some embodiments, the device isolation layer212may be formed of oxide, nitride, or a combination thereof. However, the inventive concept is not limited thereto. The device isolation layer212may be a single layer including one kind of insulating layer or layers including a combination of at least two kinds of insulating layers.

An insulating pattern230B is formed on the substrate210, where the insulating pattern230B has a plurality of holes that expose upper surfaces of direct contacts DC and define first contact structures400. The insulating pattern230B may include a first insulating pattern220B and a second insulating pattern222B. In some embodiments, the first insulating pattern220B may be an oxide layer and the second insulating pattern222B may be a nitride layer. However, the inventive concept is not limited thereto. The direct contacts DC each may be formed of single crystal silicon, single crystal germanium, single crystal silicon-germanium, polycrystalline semiconductor doped with impurities, metal (such as aluminum, copper, and tungsten), metal nitride, or a combination thereof. However, the inventive concept is not limited thereto.

Referring to the A-A′ line cross-section ofFIG. 2, a plurality of bit lines260are formed on the substrate210and extend parallel to one another in a first direction. InFIG. 2, as an example, the bit lines260are formed to extend in the Y-axis direction. The bit lines260may include a first conductive pattern226B, a third conductive pattern232B, and a fourth conductive pattern234B. The bit lines260may be connected to the active regions214of the substrate210via the direct contacts DC. In some embodiments, the third conductive pattern232B and the fourth conductive pattern234B each may be formed of titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten silicide (WSi2), or a combination thereof. However, the inventive concept is not limited thereto. In some embodiments, the third conductive pattern232B may include TiSiN, and the fourth conductive pattern234B may include W.

A capping structure270may be formed on the bit lines260. The capping structure270may include a capping layer236B and an insulating layer252B. The capping layer236B may be a silicon nitride layer.

A stacked structure, which includes the bit lines260and the capping structure270, may be covered with a spacer280. The spacer280may be formed at a sidewall of the stacked structure and may cover an upper surface of the stacked structure. The spacer280may include an insulating liner256and insulating spacers S1and S2. The insulating liner256may cover upper surfaces and sidewalls of the bit lines260, and the insulating spacers S1and S2may cover the sidewalls of the bit lines260. In some embodiments, the insulating liner256and the insulating spacers S1and S2may be formed of silicon oxide, silicon nitride, air, or a combination thereof. Although a case in which the insulating spacers S1and S2include a double layer is illustrated inFIG. 2, the inventive concept is not limited thereto. For example, the insulating spacers S1and S2each may include a single layer or a triple layer.

The first contact structure400, which is connected to the active regions214, is formed in an area defined by a pair of adjacent bit lines260and an area defined by a pair of adjacent first insulating lines310. The first insulating lines310are not shown in the A-A′ line cross-section, but are shown in the B-B′ line cross-section. In some embodiments, the first contact structure400may have a lower surface than the level of a main surface of the substrate210. Although inFIG. 2the levels of the upper surfaces of the bit lines260are higher than the level of the upper surface of the first contact structure400, the inventive concept is not limited thereto. In some other embodiments, the levels of the upper surfaces of the bit lines260may be approximately the same as that of the upper surface of the first contact structure400.

The first contact structure400is formed of a conductive material. In some embodiments, the first contact structure400may be an epitaxial layer. For example, the first contact structure400may be formed of single crystal silicon, single crystal germanium, or single crystal silicon-germanium. In some embodiments, the first contact structure400may include a polycrystalline semiconductor layer doped with impurities. For example, the first contact structure400may include a polysilicon layer doped with impurities. In some embodiments, the first contact structure400may include a metal. For example, the first contact structure400may include aluminum, copper, or tungsten. In some embodiments, a metal silicide layer may be formed on the surfaces of the active regions214that contact the first contact structure400. The metal silicide layer may include cobalt silicide.

Referring to the B-B′ line cross-section ofFIG. 2, a plurality of buried word lines WL are formed in the substrate210and extend parallel to one another in a second direction that is different from the first direction. InFIG. 2, the word lines WL are formed to extend in the X-axis direction. The substrate210includes a plurality of word line trenches305formed in the substrate210, a gate dielectric layer310covering bottoms and inside walls of the word line trenches305, the word lines WL filled in lower portions of the word line trenches305covered with the gate dielectric layer310, and a buried insulating layer314that covers upper surfaces of the word lines WL and fills the word line trenches305. In some embodiments, an upper Surface of the buried insulating layer314may be at the same level as an upper surface of the substrate210.

The insulating pattern230B, in which the holes defining the first contact structure400and the holes defining the direct contact DC are formed, is formed on the substrate210.

A plurality of first insulating lines310are formed on the insulating pattern230B and extend parallel to one another in a third direction that is different from the first direction. InFIG. 2, as an example, the first insulating lines310are formed to extend in the X-axis direction. Levels of upper surfaces of the first insulating lines310are higher than those of upper surfaces of the bit lines260. In some embodiments, the third direction is the same as the first direction, and thus, the first insulating lines310may be formed to be overlapped on the word lines WL. In some embodiments, the first insulating lines310may be formed of oxide, nitride, carbide, polymer, or a combination thereof. However, the inventive concept is not limited thereto. In some embodiments, the first insulating lines310each may have a fence shape.

The first contact structure400, which is filled with a conductive material and thus is connected to the active regions214, is formed in an area defined by a pair of adjacent first insulating lines310and a pair of adjacent bit lines260. The bit lines260are not shown in the B-B′ line cross-section, but are shown in the A-A′ line cross-section. In some embodiments, the first contact structure400may have a lower surface than the level of a main surface of the substrate210.

A plurality of second insulating lines510cover portions of the upper surfaces of the bit lines260, the sidewalls of the bit lines260, and a portion of the upper surface of the first contact structure400, and extend parallel to one another in a fourth direction, which is different from the third direction, while contacting portions of the sidewalls of the first insulating lines310. InFIG. 2, as an example, the second insulating lines510are formed to extend between the X-axis direction and the Y-axis direction. Referring to the A-A′ line cross-section, the second insulating lines510contact the upper surfaces and sidewalls of the bit lines260and contact a portion of the upper surface of the first contact structure400. Referring to the B-B′ line cross-section, the second insulating lines510contact portions of the sidewalls of the first insulating lines310and contact a portion of the upper surface of the first contact structure400. The level of the upper surface of the first contact structure400may be lower than that of an upper surface of the first insulating line310.

In some embodiments, the levels of upper surfaces of the second insulating lines510may be approximately equal to those of the upper surfaces of the first insulating lines310. In some embodiments, the first insulating lines310, the second insulating lines510, and the spacer280may be formed of the same material.

A second contact structure610, which is filled with a conductive material and, thus, is connected to the upper surface of the first contact structure400, is formed in an area defined by a pair of adjacent first insulating lines310and a pair of adjacent second insulating lines510. In some embodiments, the second contact structure610may be formed of titanium nitride, titanium silicon nitride, tungsten, tungsten silicide, or a combination thereof. However, the inventive concept is not limited thereto. In some embodiments, the second contact structure610may be formed of the same material as the first contact structure400. In some embodiments, the levels of the upper surfaces of the first insulating lines310, the levels of the upper surfaces of the second insulating lines510, and the level of the upper surface of the second contact structure610may all be the same.

In some embodiments, an insulating pattern730may be formed on the upper surfaces of the first insulating lines310, the upper surfaces of the second insulating lines510, and the upper surface of the second contact structure610, wherein the insulating pattern730defines a storage node hole that exposes the upper surface of the second contact structure610. A capacitor is formed in the storage node hole. The capacitor includes a lower electrode700, a dielectric layer710, and an upper electrode720. In some embodiments, the insulating pattern730may be formed of oxide, nitride, carbide, polymer, or a combination thereof. However, the inventive concept is not limited thereto.

A horizontal cross-sectional view of the semiconductor device30will be described below with reference back toFIG. 1A. The same reference names described with reference toFIG. 1AandFIG. 2denote the same elements although reference numerals differ.

Referring back toFIG. 1A, the semiconductor device30includes bit line structures BL in the first direction (the Y-axis direction), first insulating lines110in the second direction (the X-axis direction), a first contact structure120formed to fill an area defined by the bit line structures BL and the first insulating lines110, second insulating lines130in the third direction (a direction between the X-axis direction and the Y-axis direction) on the first contact structure120and the bit line structures BL, a second contact structure140formed to fill an area defined by the first insulating lines110and the second insulating lines130, and a lower capacitor electrode ST formed on the second contact structure140. Although inFIG. 1A, the first direction is the X-axis direction, the second direction is the Y-axis direction, and the third direction is a direction between the X-axis direction and the Y-axis direction, the inventive concept is not limited thereto.

Referring to the cross-section of the core/peripheral area CORE/Peri., a gate structure is formed on the substrate210including the active regions214defined by the device isolation layer212. In detail, a gate electrode240for a peripheral circuit, which includes a first conductive pattern226A, a third conductive pattern232A, and a fourth conductive pattern234A, is formed on a gate dielectric layer224formed on the substrate210, and the upper surface of the gate electrode240is covered with a capping pattern236A. Both sidewalls of a gate structure in which the gate dielectric layer224, the gate electrode240, and the capping pattern236A are stacked are covered with an insulating spacer242. An insulating thin film244and an insulating layer250are formed on the whole surface of the core/peripheral area CORE/Peri. to cover the gate structure and the insulating spacer242. The insulating layer250may include an interlayer insulating layer246and an insulating layer252. A conductive layer600is formed separate from the substrate210with the insulating layer250placed therebetween. The conductive layer600may include contact plugs that penetrate the insulating layer250and the insulating liner insulating thin film256and thus are connected to the active regions214. In some embodiments, the insulating spacer242may be formed of oxide, nitride, or a combination thereof, and the insulating thin film244may be formed of nitride. However, the inventive concept is not limited thereto. In some embodiments, the interlayer insulating layer246may be a silicon oxide layer formed by a high density plasma (HDP) or flowable chemical vapor deposition (FCVD) method. However, the inventive concept is not limited thereto.

FIGS. 3 to 18Bare cross-sectional views and layouts illustrated according to a process sequence of a method of manufacturing a semiconductor device, according to an embodiment of the inventive concept. A cell array area CA, a core/peripheral area CORE/Peri., a line A-A′, and a line B-B′, illustrated inFIGS. 3 to 18B, are the same as those illustrated inFIG. 2. InFIGS. 3 to 18B, the same reference numerals denote the same elements. Thus, repeated explanations thereof will not be given.

Referring toFIG. 3, a device isolation layer212is formed in a substrate210to define a plurality of active regions214in the cell array area CA and the core/peripheral area CORE/Peri.

Referring to the B-B′ line cross-section of the cell array area CA, a plurality of word line trenches305are formed in the substrate210. The plurality of word line trenches305may extend parallel to one another in the X-axis direction, and each of the word line trenches305may have a line shape intersecting the plurality of active regions214. A gate dielectric layer310is formed to cover lower surfaces and sidewalls of the word line trenches305, and a word line WL and a buried insulating layer314are sequentially formed in each of the word line trenches305. Upper surfaces of the plurality of buried insulating layers314may be about at the same level as an upper surface of the substrate210. In some embodiments, after forming the word lines WL, impurity ions may be implanted in the substrate210at both sides of each of the word lines WL to form source and drain areas in upper surfaces of the active areas214. In some embodiments, before forming the word lines WL, an impurity ion implantation process may be performed to form source and drain areas. The A-A′ line cross-section of the cell array area CA is an area between the word lines WL, and thus the word lines WL are not shown in the A-A′ line cross-section of the cell array area CA.

After sequentially forming a first insulating layer220and a second insulating layer222on the substrate210in both the cell array area CA and the core/peripheral area CORE/Peri., the first insulating layer220and the second insulating layer222are removed from the core/peripheral area CORE/Peri. to expose an active region214of the core/peripheral area CORE/Peri. again. Next, the cell array area CA is covered with a mask pattern (not shown), and then a gate dielectric layer224is formed on the substrate210of the core/peripheral area CORE/Peri. In some embodiments, the first insulating layer220may be an oxide layer, and the second insulating layer222may be a nitride layer. However, the inventive concept is not limited thereto. In some embodiments, the gate dielectric layer224may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide/nitride/oxide (ONO) layer, and a high-k dielectric film having a dielectric constant that is higher than that of the silicon oxide layer.

In the cell array area CA and the core/peripheral area CORE/Peri., a first conductive layer226is formed on the second insulating layer222and the gate dielectric layer224. In some embodiments, the first conductive layer226may be formed of doped polysilicon. However, the inventive concept is not limited thereto.

Referring toFIG. 4, a mask pattern228is formed on the first conductive layer226in both the cell array area CA and the core/peripheral area CORE/Peri. Referring to the A-A′ line cross-section of the cell array area CA, the mask pattern228has an opening that exposes a portion of the first conductive layer226. Next, the first conductive layer226exposed via the opening of the mask pattern228is etched, and a portion of the substrate210and a portion of the device isolation layer212, which are exposed as a result of the etching, are etched to thereby form a direct contact hole DCH that exposes an active region214of the substrate210in the cell array area CA. A photolithography process may be used to form the mask pattern228. The core/peripheral area CORE/Peri. may be covered with the mask pattern228and, thus, may not be exposed to the outside.

Referring toFIG. 5, a second conductive layer having a thickness that is sufficient for filling the direct contact hole DCH is formed in the direct contact hole DCH and on the first conductive layer226after removing the mask pattern228from the cell array area CA and the core/peripheral area CORE/Peri. Next, the second conductive layer is removed so that the second conductive layer remains only in the direct contact hole DCH, and thus, a direct contact DC formed of the second conductive layer remaining in the direct contact hole DCH is formed. The second conductive layer may be formed of doped polysilicon. However, the inventive concept is not limited thereto. When removing the second conductive layer, an etch back or chemical mechanical polishing (CMP) process may be used.

Referring toFIG. 6, a third conductive layer232, a fourth conductive layer234, and a capping layer236are sequentially formed on the first conductive layer226and the direct contact DC in both the cell array area CA and the core/peripheral area CORE/Peri.

Referring toFIG. 7, the cell array area CA is covered with a mask pattern (not shown), and then in the core/peripheral area CORE/Peri., the gate dielectric layer224, the first conductive layer226, the third conductive layer232, the fourth conductive layer234, and the capping layer236are patterned by using a photolithography process. As a result, a gate electrode240for a peripheral circuit, which includes a first conductive pattern226A, a third conductive pattern232A, and a fourth conductive pattern234A, is formed on the gate dielectric layer224. The gate electrode240is covered with a capping pattern236A. After forming an insulating spacer242at both sidewalls of a gate structure in which the gate dielectric layer224, the gate electrode240, and the capping pattern236A are stacked, an insulating thin film244is formed on the whole surface of the core/peripheral area CORE/Peri. to cover the gate structure. Then, a planarized interlayer insulating layer246is formed that covers the gate structure and the insulating thin film244. Although the insulating thin film244is not on the capping pattern236A inFIG. 7, the inventive concept is not limited thereto and the insulating thin film244is initially formed on the capping pattern236A during a process and then the insulating thin film244formed on the capping pattern236A is removed.

Referring toFIG. 8, an insulating layer252is formed on the capping layer236in both the cell array area CA and the core/peripheral area CORE/Peri.

Referring toFIG. 9, the insulating layer252and the capping layer236ofFIG. 8are patterned by using a photolithography process. As a result, referring to the A-A′ line cross-section, a cell mask pattern252B and a capping pattern236B, which are to be used as an etch mask to form a plurality of bit lines, are formed in the cell array area CA. Because the B-B′ line cross-section is an area between bit lines, the insulating layer252and the capping layer236ofFIG. 8are not shown in the B-B′ line cross-section. The insulating layer252is not removed in the core/peripheral area CORE/Peri.

Referring toFIG. 10, a portion of a structure under the cell mask pattern252B and the capping pattern236B is etched by using the cell mask pattern252B and the capping pattern236B as an etch mask. As a result, referring to the A-A′ line cross-section, the first conductive layer226, the third conductive layer232, and the fourth conductive layer234are partially etched, and thus, a plurality of bit lines260each of which includes a first conductive pattern226B, a third conductive pattern232B, and a fourth conductive pattern234B and extends in the Y-axis direction, are formed. The plurality of bit lines260are connected to the active region214via the direct contacts DC. Because the B-B′ line cross-section is an area between the bit lines, all the first conductive layer226, the third conductive layer232, and the fourth conductive layer234ofFIG. 9are not shown in the B-B′ line cross-section.

In some embodiments, a process of forming a material layer of the gate electrode240for a peripheral circuit in the core/peripheral area CORE/Peri ofFIG. 7and a process of forming a material layer of the bit lines260in the cell array area CA ofFIG. 8may be performed by using only one photolithography process. In this case, an etch mask includes mask patterns for defining the gate electrode240and the bit lines260.

Referring toFIG. 11, an insulating liner256may be formed on an upper surface of a resultant structure in which the bit lines260of the cell array area CA were formed. Insulating spacers S1and S2may be formed at a sidewall of each of the bit lines260and cover the insulating liner256.

Referring toFIG. 12, an insulating material300is formed on the whole surface of a resultant structure formed in the cell array area CA ofFIG. 11so as to cover upper surfaces of the bit lines260. A mask pattern (not shown) defining a first insulating line310is formed on the insulating material300, and the insulating material300is etched by using the mask pattern as an etch mask.

In the core/peripheral area CORE/Peri., material layers that are required for forming the cell array area CA may be formed and then be removed. Accordingly, the material layers required for forming the cell array area CA are not illustrated in the core/peripheral area CORE/Peri. ofFIGS. 12 to 15.

Referring to the A-A′ line cross-section ofFIG. 13A, an area in which the insulating material300in a resultant structure of the cell array area CA ofFIG. 12is etched is filled with a constituent material of the first insulating line310and the first insulating line310is formed by etching the insulating material300. The insulating material300and the constituent material of the first insulating line310differ. In some embodiments, the first insulating line310may be formed of silicon oxide, silicon nitride, or a combination thereof. However, the inventive concept is not limited thereto. In some embodiments, the insulating material300may be removed by using a wet etching process.

The first insulating line310includes a plurality of insulating lines extending in the X-axis direction as shown in the B-B′ line cross-section. In this case, areas, which are defined by the plurality of first insulating lines310and the bit lines260extending in the Y-axis direction as shown in the A-A′ line cross-section, are formed. The areas are etched by using the first insulating lines310and the bit lines260as an etch mask so that an active region214under the area is exposed, and thus, holes BCH are formed. The first insulating lines310are not shown in the A-A′ line cross-section.

Referring to the B-B′ line cross-section, the B-B′ line cross-section is an area between the bit lines260, and the first insulating layer220and the second insulating layer222(refer toFIG. 12) under a plurality of holes BCH are removed so that the active region214is exposed. Thus, a first insulating pattern220B and a second insulating pattern222B are formed on the substrate210between the plurality of holes BCH, and the first insulating lines310extend in the X-axis direction. The bit lines260are not shown in the B-B′ line cross-section.

FIG. 13Bis a schematic layout of the cell array area CA illustrated inFIG. 13A. The same reference names that are described with reference toFIG. 13AandFIG. 13Bdenote the same elements although reference numerals differ. A bit line structure BL ofFIG. 13Bis a structure in which the bit line260and the spacer280ofFIG. 13Aare combined with each other.

Referring toFIG. 13B, the semiconductor device30includes a plurality of word lines WL, a plurality of bit line structures BL, and a plurality of first insulating lines110. The word lines WL extend in the X-direction while intersecting active regions AC of a substrate100. The bit line structures BL are connected to the active regions AC via direct contacts DC while intersecting the active regions AC and extend in the Y-axis direction. The first insulating lines110extend in the X-axis direction. A bit line contact hole BCH is formed in an area that is defined by a pair of adjacent bit line structures BL and a pair of adjacent first insulating lines110.

Referring toFIG. 14A, in the cell array area CA, a lower portion of the inside of each of the plurality of holes BCH is filled with a conductive layer to thereby form first contact structures400that are connected to the active region214. Referring to the A-A′ line cross-section, the first contact structures400are formed in the plurality of holes BCH between the bit lines260. In some embodiments, the first contact structures400may cover sidewalls of insulating spacers S1and S2formed at sidewalls of the bit lines260and sidewalls of the first insulating lines310.

Referring to the B-B′ line cross-section, first contact structures400are formed in a plurality of holes BCH between the first insulating lines310. In some embodiments, the upper surfaces of the bit lines260and the upper surfaces of the first contact structures400may be etched so that the levels of the upper surfaces of the bit lines260and the levels of the upper surfaces of the first contact structures400are approximately equal to each other.

FIG. 14Bis a schematic layout of the cell array area CA illustrated inFIG. 14A. The same reference names described with reference toFIG. 14AandFIG. 14Bdenote the same elements although reference numerals differ. A bit line structure BL ofFIG. 14Bis a structure in which the bit line260and the spacer280ofFIG. 14Aare combined with each other.

Referring toFIG. 14B, a plurality of areas that are defined by a plurality of bit line structures BL and a plurality of first insulating lines110are filled with a conductive layer to thereby form the plurality of first contact structures400.

Referring toFIG. 15, an insulating material500is formed on the upper surface of a resultant structure of the cell array area CA ofFIG. 14A. The insulating material500may be formed to cover the first insulating lines310. A mask pattern (not shown), which defines a plurality of second insulating lines510extending in a direction between the X-axis direction and the Y-axis direction, is formed on the insulating material500, and the insulating material500is etched by using the mask pattern as an etch mask.

Referring toFIG. 16A, the insulating material500in a resultant structure of the cell array area CA ofFIG. 15. is etched by using the mask pattern as an etch mask, and an area in which the insulating material500is etched is filled with a constituent material of the second insulating lines510, and the insulating material500is etched to thereby form the second insulating lines510. The insulating material500and the material of the second insulating lines510differ. In some embodiments, the second insulating lines510may be formed of silicon oxide, silicon nitride, or a combination thereof. However, the inventive concept is not limited thereto. In some embodiments, the second insulating lines510may be formed of the same material as the first insulating lines310. In some embodiments, the insulating material500may be removed by using a wet etching process. Referring to the A-A′ line cross-section ofFIG. 16A, the second insulating lines510are formed to contact the upper surfaces and sidewalls of the bit lines260. Referring to the B-B′ line cross-section ofFIG. 16A, the second insulating lines510are formed to contact the upper surfaces and sidewalls of some of the first insulating lines310.

FIG. 16Bis a schematic layout of the cell array area CA illustrated inFIG. 16A. The same reference names described with reference toFIG. 16AandFIG. 16Bdenote the same elements although reference numerals differ. A bit line structure BL ofFIG. 16Bis a structure in which the bit line260and the spacer280ofFIG. 16Aare combined with each other.

Referring toFIG. 16B, first insulating lines110extend in the X-axis direction, and second insulating lines130extend in a direction between the X-axis direction and the Y-axis direction. The second insulating line130covers a portion of the upper surface of a first contact structure120, a portion of the upper surface of the bit line structure BL, and a portion of the upper surface of the first insulating line110. A plurality of second insulating lines130each are formed so as not to bisect the upper surface of the first contact structure120.

Referring toFIG. 17, a conductive layer600is formed on the whole surface of a resultant structure including the cell array area CA and the core/peripheral area CORE/Peri. ofFIG. 16Aso as to cover a lower structure. In detail, trenches550that penetrate the interlayer insulating layer246and the insulating layer252and expose the active region214are formed in the core/peripheral area CORE/Peri. Next, a conductive layer600is formed on the whole surface of a resultant structure with the trenches550formed therein. The conductive layer600filled in the trenches550electrically connects the active region24to an upper interconnection line. In some embodiments, the conductive layer600may be formed by using a damascene process.

Referring toFIG. 18A, an upper side portion of a resultant structure including the cell array area CA and the core/peripheral area CORE/Peri. ofFIG. 17is removed. For example, the upper side portion of the resultant structure may be removed by an etch back or CMP process. As a result, the conductive layer600is divided into several conductive lines due to the first insulating lines310and the second insulating lines510to thereby form a second contact structure610. Referring to the A-A′ line cross-section ofFIG. 18A, a cross-section of the second contact structure610formed by division by the second insulating lines510is shown. Referring to the B-B′ line cross-section ofFIG. 18A, a cross-section of the second contact structure610formed by division by the first insulating lines310and the second insulating lines510is shown. The second contact structure610may have a level that is about the same as those of the upper surfaces of the second insulating lines510or those of the upper surfaces of the first insulating lines310. In the semiconductor device30manufactured by the method described above, there may be little to no variation between a plurality of second contact structures610because the plurality of second contact structures610are formed at one time, and thus, a stable structure thereof may be obtained. In addition, an interconnection process may be performed only in the core/peripheral area CORE/Peri., and thus, a process margin may be increased.

A plurality of capacitors are formed on the upper surfaces of the plurality of second contact structures610to thereby form the semiconductor device30ofFIG. 2. In detail, referring back toFIG. 2, a plurality of insulating patterns730having a plurality of storage node holes are formed on the upper surfaces of the first insulating lines310, the upper surfaces of the second insulating lines510, and the upper surfaces of the second contact structures610so that the upper surfaces of the second contact structures610are exposed. One insulating pattern730is formed so that only the upper surface of one of the second contact structures610corresponding thereto is exposed. A first conductive layer, a dielectric layer, and a second conductive layer may be sequentially formed in each of the plurality of storage node holes to thereby form a capacitor. The capacitor includes a lower electrode700, a dielectric layer710, and an upper electrode720.

FIG. 18Bis a schematic layout of the cell array area CA illustrated inFIG. 18A. The same reference names described with reference toFIG. 18AandFIG. 18Bdenote the same elements although reference numerals differ. A bit line structure BL ofFIG. 18Bis a structure in which the bit line260and the spacer280ofFIG. 18Aare combined with each other.

Referring toFIG. 18B, a plurality of second contact structures140are formed in a plurality of areas that are defined by a pair of first insulating lines110and a pair of second insulating lines130. One of the second contact structures140is disposed to be connected to the upper surface of one of the first contact structures120corresponding thereto.

In some embodiments, a lower capacitor electrode ST is formed on the upper surface of each of the second contact structures140to thereby form the semiconductor device10ofFIG. 1A. One lower capacitor electrode ST is connected to the upper surface of one of the second contact structures140corresponding thereto.

In some embodiments, a plurality of insulating patterns150(refer toFIG. 1C) having a plurality of storage node holes that expose the upper surfaces of the second contact structures140may be formed on the upper surfaces of the first insulating lines110, the upper surfaces of the second insulating lines130, and the upper surfaces of the second contact structures140. One insulating pattern150is formed so that only the upper surface of one of the second contact structures140corresponding thereto is exposed. In some embodiments, when forming the storage node holes at regular intervals, insulating patterns150remaining after defining the storage node holes may have a plurality of third insulating lines153that are parallel to one another and a plurality of fourth insulating lines155that are parallel to one another. Because each of the third insulating lines153and each of the fourth insulating lines155may have the same shape and size as each of the first insulating lines110and each of the second insulating lines130, respectively, the misalignment of a storage node hole defined by a pair of third insulating lines153and a pair of fourth insulating lines155and the misalignment of a second contact structure140defined by a pair of first insulating lines110and a pair of second insulating lines130may be greatly improved.

A lower capacitor electrode ST is formed in each of the storage node holes to thereby form the semiconductor device20ofFIG. 1C.

FIG. 19is a block diagram of a system1000including a semiconductor device according to an embodiment of the inventive concept.

The system1000includes a controller1010, an input/output device1020, a memory device1030, and an interface1040. The system1000may be a mobile system and/or a system for transmitting and/or receiving information. In some embodiments, the mobile system may be, for example, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card. The controller1010, which controls an execution program in the system1000, may be a microprocessor, a digital signal processor, a microcontroller, or a similar device. The input/output device1020may be used to input or output data to or from the system1000. The system1000may be connected to an external device, e.g., a personal computer (PC) or a network, by using the input/output device1020and may exchange data with the external device. The input/output device1020may be, for example, a keypad, a keyboard, or a display.

The memory device1030may store codes and/or data for an operation of the controller1010or may store data processed by the controller1010. The memory device1030may include a semiconductor device according to the above-described embodiments of the inventive concept. For example, the memory device1030may include at least one of the semiconductor devices described with reference toFIGS. 1A to 18B.

The interface1040may be a data transmission path between the system1000and an external device. The controller1010, the input/output device1020, the memory device1030, and the interface1040may communicate with each other via a bus1050. The system1000may be used, for example, in mobile phones, MP3 players, navigation system, portable multimedia players (PMPs), solid state disks (SSDs), and household appliances.

FIG. 20is a block diagram of a memory card1100including a semiconductor device according to an embodiment of the inventive concept.

The memory card1100includes a memory device1110and a memory controller1120.

The memory device1110may store data. In some embodiments, the memory device1110may have nonvolatile characteristics by which data may be maintained intact although the power supply is discontinued. The memory device1110includes a semiconductor device according to the above-described embodiment of the inventive concept. For example, the memory device1110includes at least one of the semiconductor devices described with reference toFIGS. 1A to 18B.

The memory controller1120may read data stored in the memory device1110in response to a read request of a host1130or may store data in the memory device1110in response to a write request of the host1130. The memory controller1120includes a semiconductor device according to the above-described embodiments of the inventive concept. For example, the memory controller1120includes at least one of the semiconductor devices described with reference toFIGS. 1A to 18B.