Semiconductor device including air gaps and method of fabricating the same

This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures. The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalls of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2012-0153806, filed on Dec. 26, 2012, which is incorporated herein by reference in its entirety.

BACKGROUND

Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including air gaps and a method of fabricating the same.

2. Description of the Related Art

In general, a semiconductor device includes a second conductive structure formed between a plurality of first conductive structures, wherein an insulation layer is interposed between the second conductive structure and the first conductive structure. For example, the first conductive structures may include a gate, a bit line, a metal wire, etc., and the second conductive structures may include a contact plug, a storage node contact plug, a bit line contact plug, a via, etc.

As the degree of integration of semiconductor devices increased, an interval between the first conductive structure and the second conductive structure is gradually narrowed. For this reason, parasitic capacitance between the first conductive structure and the second conductive structure is increased. As the parasitic capacitance is increased, the operating speed of the semiconductor device is decreased and a refresh characteristic is deteriorated.

In order to reduce the parasitic capacitance, a method of lowering the dielectric constant of the insulation layer may be used. In semiconductor devices, an insulation layer is chiefly made of silicon oxide or silicon nitride. A silicon oxide layer has a dielectric constant of about 4, and a silicon nitride layer has a dielectric constant of about 7.

A reduction of parasitic capacitance is limited because a silicon oxide or a silicon nitride still has a high dielectric constant. A material having a relatively low dielectric constant has recently been developed, but the dielectric constant of the material may be not so low.

SUMMARY

Exemplary embodiments of the present invention are directed to providing a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures.

In accordance with an exemplary embodiment of the present invention, a method of fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate; forming contact holes between the bit line structures; forming sacrificial spacers over sidewalls of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs.

In accordance with another exemplary embodiment of the present invention, a method of fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate; forming contact holes between the bit line structures; forming sacrificial spacers on sidewalls of the contact holes; forming silicon plugs recessed into the respective contact holes; forming air gaps by removing the sacrificial spacers; forming capping structures capping the air gaps while exposing top surfaces of the silicon plugs; forming ohmic contact layers over the silicon plugs; and forming metal plugs over the ohmic contact layers.

In accordance with still another exemplary embodiment of the present invention, a semiconductor device includes a plurality of bit line structures formed over a substrate; storage node contact holes formed to have sidewalls of the bit line structures exposed therethrough; silicon plugs recessed and formed in the respective storage node contact holes; air gaps formed between the sidewalls of the bit line structures and the silicon plugs; capping layer patterns formed over the air gaps; passivation layers formed over the respective capping layer patterns; and metal plugs formed over the respective silicon plugs, wherein the air gaps are capped with the respective capping layer patterns and passivation layers.

DETAILED DESCRIPTION

FIG. 1is a cross sectional view illustrating a portion of a semiconductor device in accordance with an embodiment of the present invention.

Referring toFIG. 1, semiconductor structures are formed over a substrate101. The semiconductor structure may include a plurality of conductive structures. The conductive structures may include first conductive structures104and second conductive structures109. An air gap110may be formed between the first conductive structure104and the second conductive structure109. A capping layer111and a passivation layer112may be formed over the air gap110.

Each of the first conductive structures104may include a first conductive layer102. The first conductive structure104may have a stack structure including the first conductive layer102and a hard mask layer103. The first conductive layer102may include a silicon-containing layer or a metal-containing layer. The first conductive layer102may be formed by stacking the silicon-containing layer and the metal-containing layer. The first conductive layer102may include polysilicon, metal, metal nitride, metal silicide, or the like. The first conductive layer102may be formed by stacking a polysilicon layer and a metal layer. The metal layer may include tungsten (W). The hard mask layer103may include an insulating material. The hard mask layer103may include oxide or nitride. One of the first conductive structure104and the second conductive structure109may have a line type in which the conductive structure extends in one direction. The other of the first conductive structure104and the second conductive structure109may have a plug type. For example, the first conductive structure104may be a structure having a line type, and the second conductive structure109may be a structure having a plug type. The first conductive structures104may be regularly arranged on the substrate101at regular intervals.

The second conductive structure109may include a second conductive layer106recessed between the first conductive structures104. Each of the second conductive structures109may have a stack structure including the second conductive layer106, an ohmic contact layer107, and a third conductive layer108. The second conductive layer106may include a silicon-containing layer. The second conductive layer106may include a polysilicon layer. The third conductive layer108may include a metal-containing layer. The ohmic contact layer107may include metal silicide, such as cobalt silicide. The third conductive layer108may include metal, metal silicide, metal nitride, or the like. The third conductive layer108may have a stack structure including a barrier layer and a metal layer. The barrier layer may include metal nitride. The third conductive layer108may include a material including titanium (Ti) or tungsten (W) as main ingredients.

The capping layer11may be of a type that caps the air gap110. The capping layer111may include the oxide of the second conductive layer106. In particular, the capping layer111may include the plasma oxide of the second conductive layer106. The capping layer111may include silicon oxide.

Spacers105may be formed over both sidewalls of the first conductive structure104. The spacers105may include an insulating material. The spacers105may include oxide or nitride. The spacers105together with the air gap110, may function to insulate the first conductive structures104from the second conductive structures109.

One of the first conductive structure104and the second conductive structure109may include a gate and a bit line, and the other of the first conductive structure104and the second conductive structure109may include a contact plug. The contact plug may include a storage node contact plug, a landing plug, etc. InFIG. 1, the first conductive layer102of the first conductive structure104may include a bit line, and the second conductive structure109may include a storage node contact plug. Accordingly, the air gap110in may be formed between the bit line and the storage node contact plug. The storage node contact plug may have a structure including the second conductive layer106, the ohmic contact layer107, and the third conductive layer108. The second conductive layer106may become a first plug, the third conductive layer108may become a second plug, and the ohmic contact layer107is formed between the first plug and the second plug. Since the first plug includes a silicon-containing layer and the second plug includes a metal-containing layer, the storage node contact plug may have a stack structure including the silicon-containing plug and the metal-containing plug.

As shown inFIG. 1, the air gap110is formed between the first conductive structure104and the second conductive structure109. The air gap110has a dielectric constant of 1 and reduces parasitic capacitance between the first conductive structure104and the second conductive structure109. Furthermore, the top of the air gap110is sealed by the capping layer111.

The capping layer111for capping the air gap110is made of oxide generated by oxidizing the second conductive layer106. The passivation layer112is formed over the capping layer111. Accordingly, the air gap110may be stably capped. The passivation layer112may include silicon nitride. The passivation layer112is formed over the capping layer111and may be formed over the sidewalls of the ohmic contact layer107and the third conductive layer108.

FIGS. 2A to 2Kshow cross-sectional views showing a method of forming a semiconductor device in accordance with an embodiment of the present invention.

As shown inFIG. 2A, a plurality of first conductive structures24is formed over a substrate21. The substrate21may contain silicon (Si). The substrate21may include a Si or a silicon germanium (SiGe) substrate. Furthermore, the substrate21may include a silicon on insulator (501) substrate.

The first conductive structures24formed over the substrate21may have a line type in which the first conductive structures24are regularly arranged at regular intervals. Each of the first conductive structures24includes a first conductive layer pattern22and a hard mask pattern23. The method for forming the first conductive structures24is described as follows. First, a first conductive layer (not shown) is formed over the substrate21, and the hard mask pattern23is formed over the first conductive layer. Then, the first conductive layer patterns22are formed by etching the first conductive layer by using the hard mask pattern23as an etch mask. The first conductive structures24in each of which the first conductive layer pattern22and the hard mask pattern23are stacked are formed. Each of the first conductive layer patterns22may include a silicon-containing layer and/or a metal-containing layer. For example, the first conductive layer pattern22may include a polysilicon layer or a tungsten layer. Furthermore, the first conductive layer pattern22may be formed by stacking the polysilicon layer and the metal layer. In this case, a barrier layer may be further formed between the polysilicon layer and the metal layer. The first conductive layer patterns22may have a stack structure including a polysilicon layer, a titanium-containing layer, or a tungsten layer. The titanium-containing layer is the barrier layer and may be formed by stacking a Ti layer and a titanium nitride layer.

As shown inFIG. 28, an insulation layer25A is formed over the entire surface including the first conductive structures24. The insulation layer25A may include nitride or oxide. The insulation layer25A may include silicon nitride and/or silicon oxide. The Insulation layer25A includes a material that becomes a spacer.

A sacrificial layer26A is formed over the insulation layer25A. The sacrificial layer26A includes a material that is removed in a subsequent process and that forms an air gap. The sacrificial layer26A includes a material having an etch selectivity to the insulation layer25A. The sacrificial layer26A may include oxide, nitride, or metal nitride. If the insulation layer25A includes oxide, the sacrificial layer26A may include metal nitride or nitride. If the insulation layer25A includes nitride, the sacrificial layer26A may include oxide or metal nitride. The sacrificial layer26A may include silicon oxide, silicon nitride, or titanium nitride (TiN).

As shown inFIG. 2C, dual spacers are formed over both sidewalls of the first conductive structure24. The dual spacers include a spacer25and a sacrificial spacer26. The spacer25is formed by etching the insulation layer25A. The sacrificial spacer26is formed over the sidewall of the spacer25. The sacrificial spacer26may be formed by etching the sacrificial layer26A. In order to form the spacer25and the sacrificial spacer26, an etch-back process may be performed.

An open part27through which the substrate21is exposed is formed between the first conductive structures24because the spacers25and the sacrificial spacers26are formed as described above. After forming the spacers25, an interlayer insulation layer (not shown) may be formed and the open parts27may be formed by etching the interlayer insulation layer. After forming the open parts27, the sacrificial spacers26may be formed over the sidewalls of the open parts27.

The open part27may be formed while the side alts of the sacrificial spacers26are exposed to the open part27. The open part27may have a line type or a contact hole type. For example, if the first conductive structure24includes a bit line structure, the open part27may include a storage node contact hole.

As shown inFIG. 2D, a second conductive layer28A for gap-filling the open parts27is formed. The second conductive layer28A may include a silicon-containing layer. The second conductive layer28A may include a polysilicon layer.

As shown inFIG. 2E, the second conductive layer28A is selectively removed. Accordingly, a second conductive layer pattern28is recessed between the first conductive structures24. In order to form the second conductive layer patterns28, an etch-back process may be performed. The second conductive layer pattern28has a surface that has been recessed lower than a surface of the first conductive structure24. The recessed surface of the second conductive layer pattern28may be controlled so that it is higher than at least the top surface of the first conductive layer pattern22. The second conductive layer pattern28may have a height that may minimize an area where the second conductive layer pattern28faces the first conductive layer pattern22. Thus, parasitic capacitance between the first conductive layer pattern22and the second conductive layer pattern28may be reduced. The second conductive layer patterns28may become contact plugs. If the first conductive structure24includes a bit line structure, the second conductive layer pattern28may become a part of a storage node contact plug. When forming the second conductive layer patterns28, the spacers25and the sacrificial spacers26are not etched owing to selectivity.

As shown inFIG. 2F, the sacrificial spacers26are selectively removed. Accordingly, air gaps29are formed. The air gaps29may be formed over the sidewalls of the second conductive layer patterns28. The air gap29is formed between the second conductive layer pattern28and the first conductive layer pattern22. The insulating structure of the ‘air gap29-spacer25’ is formed between the first conductive layer pattern22and the second conductive layer pattern28.

In order to remove the sacrificial spacers26wet etch or dry etch may be performed. When removing the sacrificial spacers26, the spacers25, the second conductive layer patterns28, and the hard mask patterns23are not damaged owing to selectivity. If the sacrificial spacers26are made of titanium nitride, wet cleaning using a mixed solution of H2SO4and H2O2may be performed.

When the air gaps29are formed as described above, parasitic capacitance between the first conductive layer pattern22and the second conductive layer pattern28is reduced.

As shown inFIG. 2G, capping layers30A are formed over the top surfaces and sidewalls of the second conductive layer patterns28. The capping layer30A may include an insulating material. The capping layer30A may include the oxide of the second conductive layer pattern28. The capping layer30A may include silicon oxide. The capping layer30A may be formed by an oxidization process. Since the second conductive layer pattern28includes a silicon-containing layer, silicon oxide may be formed over the top surfaces and sidewalls of the second conductive layer patterns28by way of the oxidization process. The capping layer30A may be formed to a thickness that does not gap-fill the air gap29. The capping layer30A may be formed by a plasma oxidization method. In this case, the capping layer30A is formed to a thin thickness that does not gap-fill the air gap29. If the capping layer30A is formed by the plasma oxidization method, the capping layer30A is oxidized on the top surface of the second conductive layer pattern28and at the same time the capping layer30A is rapidly oxidized at the top corners of the second conductive layer pattern28. That is, the capping layer30A formed over the top corners of the second conductive layer pattern28has a thickness greater than that of the capping layer30A formed over the top surface of the second conductive layer pattern28. Accordingly, since oxidization is rarely generated on the sidewalls of the second conductive layer pattern28, the capping layer30A that covers the second conductive layer pattern28may be selectively formed.

When the capping layers30A are formed, the air gaps29may be prevented from being open in a subsequent process.

As shown inFIG. 2H, a spacer material31A is formed over the entire surface in which the capping layers30A are formed. The spacer material31A may include an insulating material. The spacer material31A may include silicon nitride. Silicon nitride may be formed by a low pressure chemical vapor deposition (LPCVD) method or a plasma-enhanced chemical vapor deposition (PECVD) method.

As shown inFIG. 2I, the spacer material31A is selectively removed. Accordingly, passivation layers31, each having a spacer type, are formed. After forming the passivation layers31, the capping layers30A may be selectively etched so that the second conductive layer patterns28are exposed. As a result, capping layer patterns30, which expose the top surfaces of the second conductive layer patterns28and cap the air gaps29, and the passivation layers31, which cover the upper sides and sidewalls of the open parts over the capping layer patterns30, are formed. When etching the spacer material, the air gaps29may be prevented from being opened because the capping layer patterns30function as etch barriers.

In another embodiment, after forming the capping layers30A, the capping layers30A may be selectively etched so as to form the capping layer patterns30which expose the top surfaces of the second conductive layer patterns28and cap the air gaps29. Then, after forming the spacer material31A, the spacer material31A is selectively removed so as to form the passivation layers31which cover the upper sides and sidewalls of the open parts over the capping layer patterns30. Accordingly, when etching the spacer material, the air gaps29may be prevented from being opened because the capping layer patterns30function as etch barriers.

Although not shown, voids generated within the first conductive layer patterns28may be removed by performing rapid thermal annealing (RTA) after forming the passivation layers31. Furthermore, after the RTA, ion implantation may be performed as a subsequent process. The ion implantation is performed in order to improve contact resistance.

As shown inFIG. 2J, ohmic contact layers32are formed over the second conductive layer patterns28, respectively. The ohmic contact layer32may include metal silicide. In order to form metal silicide, annealing may be performed after forming a metal layer (not shown) on the entire surface. The metal layer may include a material that may be silicidized. The metal layer may include cobalt (Co). Metal silicide may be formed because the metal layer reacts to the silicon of the second conductive layer pattern28by way of the annealing. The metal silicide may include cobalt silicide. In the present embodiment, the metal silicide may include cobalt silicide having a ‘CoSi2phase’.

Since cobalt silicide having a CoSi2phase is formed as the ohmic contact layer32, contact resistance may be improved and cobalt silicide having sufficient low resistance even in the small area of the open part27having a fine line width may also be formed.

Next, a non-reacted metal layer is stripped. If the non-reacted metal layer is not removed, the metal atoms of the non-reacted metal layer may be diffused downward or the metal atoms of the non-reacted metal layer may generate an abnormal reaction with a metal silicide layer32in a subsequent process. For this reason, the non-reacted metal layer is removed. The non-reacted metal layer may be removed by a cleaning process using wet chemicals. For example, if the non-reacted metal layer is cobalt (Co) the non-reacted metal layer may be removed by H2SO4(SPM) and NH4OH(SC-1)-series chemicals. Incidentally, the non-reacted metal layer may be oxidized using deionized (DI) water and may be primarily removed using H2SO4(SPM), and metallic polymer-series residues may be secondarily removed using NH4OH-series chemicals.

If the wet chemicals are used as described above, both the non-reacted metal layer and metallic polymer may be removed cleanly.

Meanwhile, in order to form cobalt silicide, RTA may be performed at least twice. For example, primary annealing and secondary annealing may be performed. The primary annealing may be performed in a temperature of 400˜600° C. and the secondary annealing may be performed in a temperature of 600˜800° C. Cobalt silicide having a ‘CoSix(x=0.1˜1.5) phase’ is formed by the primary annealing. The cobalt silicide having a ‘CoSix(x=0.1˜1.5)’ phase is changed into cobalt silicide having a ‘CoSi2phase’ by way of the secondary annealing. From among cobalt silicides, cobalt silicide having a ‘CoSi2phase’ has the lowest resistivity. Non-reacted cobalt is removed between the primary annealing and the secondary annealing. The non-reacted cobalt may be removed using mixed chemicals of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2).

As shown inFIG. 2K, third conductive layer patterns33are formed over the ohmic contact layers32. In order to form the third conductive layer patterns33, a polishing process may be performed after forming a third conductive layer that gap-fills the top surfaces of the ohmic contact layers32. The third conductive layer pattern33may include a metal-containing layer. The third conductive layer pattern33may include a tungsten layer. Although not shown, the third conductive layer pattern33may further include a barrier layer. Accordingly, the third conductive layer pattern33may be formed by stacking the barrier layer and the metal-containing layer. The barrier layer may include a material containing titanium (Ti). The barrier layer may be made of titanium (Ti) solely or may be formed by stacking titanium (Ti) and titanium nitride (TiN). If the third conductive layer pattern33includes a material that does not react to the second conductive layer pattern28, the barrier layer may be omitted.

If the third conductive layer patterns33are formed as described above, second conductive structures34each including the second conductive layer pattern28, the ohmic contact layer32, and the third conductive layer pattern33are formed. The air gap29is formed between the first conductive structure24and the second conductive structure34. The second conductive structure34may become a storage node contact plug. The second conductive layer pattern28may become the bottom plug of the storage node contact plug, and the third conductive layer pattern33may become the top plug of the storage node contact plug. Since the second conductive layer pattern28includes the silicon-containing layer and the third conductive layer pattern33includes the metal-containing layer, a contact plug including the silicon-containing layer and the metal-containing layer, that is, a semi-metal contact plug structure, may be formed.

The air gap29may be formed between the first conductive layer pattern22and the second conductive layer pattern28. If the first conductive layer pattern22includes a bit line and the second conductive layer pattern28includes a storage node contact plug, the air gap29may be formed between the bit line and the storage node contact plug. If the first conductive layer pattern22includes a gate electrode and the second conductive layer pattern28includes a contact plug, the air gap29may be formed between the gate electrode and the contact plug.

FIGS. 3A and 3Billustrate comparative examples that are compared with the present embodiment.

Referring toFIGS. 3A and 3B, a plurality of first conductive structures44in each of which a first conductive layer42and a hard mask layer43are stacked is formed over a substrate41, and a second conductive layer46that forms a second conductive structure is formed between the first conductive structures44. An air gap47is formed between the first conductive structure44and the second conductive layer46. Spacers45are formed over the sidewalls of the first conductive structure44.

In the comparison examples, a single insulating material may be used as a capping layer48. The capping layer48may include silicon nitride or silicon oxide. When an insulating material is used as the capping layer48, the capping layer48has to be selectively removed from a surface of the second conductive layer46for a subsequent process.

If the capping layer48is attacked by a subsequent process, however, a self-alignment contact (SAC) fail is generated. If the capping layer48is thickly formed in order to form stable air gaps47, contact resistance may be greatly increased because an area where metal silicide is formed may be greatly reduced.

In particular, if the capping layer48is solely formed there is a problem in that the air gaps47are opened because the capping layer48is attached when etching the capping layer48in order to form metal silicide by opening the top surfaces of the second conductive layers46(refer to reference numeral49).

As a result, as in the present embodiment, when the air gap29is capped with the dual structure of the capping layer pattern30and the passivation layer31using silicon nitride by way of a plasma oxidization process, a top-open margin may be secured and the air gap may also be sufficiently capped.

FIG. 4Ashows memory cells of DRAM,FIG. 4Bis a cross-sectional view of the DRAM taken along line A-A′ ofFIG. 4A, andFIG. 4Cis a cross-sectional view of the DRAM taken along line B-B′ ofFIG. 4A.

Referring toFIGS. 4A, 4B, and 4C, active regions53are defined in a substrate51by way of isolation regions52. Burial gate electrodes56are formed in respective trenches54that cross the active regions53and the isolation regions52. Bit lines61extended in a direction to cross the burial gate electrodes56are formed over the substrate51, and the bit lines61are connected to the active regions53through respective bit line contact plugs60. Storage node contact plugs connected to the respective active regions53are formed. Each of the storage node contact plugs may be formed by stacking a first plug66, an ohmic contact layer70, and a second plug71. The storage node72of a capacitor is formed over each of the second plugs71of the storage node contact plugs.

The storage node contact plug may correspond to the second conductive structure according to the present embodiments, and the bit line may correspond to the first conductive layer pattern of the first conductive structure according to the present embodiments. Accordingly, the air gap67may be formed between the storage node contact plug and the bit line61. The storage node contact plug may include the first plug66and the second plug71and may further include the ohmic contact layer70formed between the first plug66and the second plug71. The ohmic contact layer70may include metal silicide, such as cobalt silicide.

The air gap67is capped with a capping layer68, and a passivation layer69is formed over the capping layer68. The capping layer68and the passivation layer69may correspond to the capping layer according to the present embodiments. Accordingly, the capping layer68may include silicon oxide, and the passivation layer69may include silicon nitride.

A method of fabricating the memory cells is described below with reference toFIGS. 4A, 4B, and 4C.

The substrate51includes a semiconductor material. The substrate51may include a semiconductor substrate. The substrate51may include a silicon substrate and may include, for example, a single crystalline silicon substrate. The isolation regions52may be formed by a shallow trench isolation (STI) process. The active regions53are defined by the isolation regions52. The isolation regions52may be formed by sequentially stacking wall oxide, a liner, and a gap-fill material. The liner may include silicon nitride and silicon oxide. The silicon nitride may include Si3N4, and the silicon oxide may include SiO2. The gap-fill material may include silicon oxide, such as a spin-on insulator (SOD). Furthermore, the gap-fill material may include silicon nitride. In this case, the silicon nitride may be gap-filled using silicon nitride used as a liner.

The trenches54are formed in the active regions53and the isolation regions52at the same time. The trench54may be formed deeper in the isolation region52than in the active region53because of a difference between the etch rates of the active region53and the isolation region52.

Prior to the formation of the burial gate electrodes56, a gate insulation layer55may be formed over surfaces of the trenches54. The burial gate electrodes56are formed by forming a metal containing layer so that the trenches54are gap-filled and then performing an etch-back. The metal-containing layer may include a material including metal, such as titanium (Ti), tantalum (Ta), or tungsten (W), as a major ingredient. The metal-containing layer may include any one selected from the group consisting of tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and tungsten (W). For example, the burial gate electrode56may include TiN, TaN, or W solely or may have a dual-layer layer, such as TiN/W or TaN/W in which W is stacked on TIN or TaN. Furthermore, the burial gate electrode56may include a dual-layer layer, such WN/W in which W is stacked on WN. In addition, the burial gate electrode56may include a metal material having low resistance.

A sealing layer57is formed over the burial gate electrodes56. The sealing layer57may gap-fill the trenches54on the burial gate electrodes56. The sealing layer57may function to protect the burial gate electrode56in a subsequent process. The sealing layer57may include an insulating material. The sealing layer57may include silicon nitride.

After forming the first interlayer insulation layer58, bit line contact holes59are formed by etching the first interlayer insulation layer58and the sealing layer57. The bit line contact plugs60are formed by forming a conductive layer in the bit line contact holes59. Bit line structures, each including the bit line61and a bit line hard mask layer62, are formed over the respective bit line contact plugs60. The bit line contact plug60may include a polysilicon layer or a metal-containing layer. The bit line61may include a tungsten layer and may include a barrier layer, such as Ti/TiN, and a tungsten layer on the barrier layer. The bit line hard mask layer62may include silicon nitride.

Spacers63are formed over both sidewalls of each of the bit line structures. Next, after forming a second interlayer insulation layer64, storage node contact holes65are formed by etching the second interlayer insulation layer64, the first interlayer insulation layer58, and the sealing layer57. After forming sacrificial spacers (not shown) on the sidewalls of the storage node contact holes65, the first plugs66recessed in the storage node contact holes65are formed. The air gaps67are formed by removing the sacrificial spacers.

Next, the capping layers68are formed by oxidizing the surfaces of the first plugs66, and the capping layers68are selectively removed so that the surfaces of the first plugs66are exposed. This process may be performed after an etch-back process for forming the passivation layers69. The air gaps67are capped with the respective capping layers68. The passivation layer69protects the capping layer68.

After forming the ohmic contact layers70on the first plugs66by using metal silicide, the second plugs71are formed over the respective ohmic contact layers70. The second plug71may include a metal-containing layer. The second plug71may include a tungsten layer. Although not shown, the second plug71may further include a barrier layer. Accordingly, the second plug71may have a stack structure including the barrier layer and the metal-containing layer. The barrier layer may include a material including titanium (Ti). The barrier layer may be made of titanium (Ti) solely or may be formed by stacking titanium (Ti) and titanium nitride (TiN).

The storage node72of a capacitor is formed over the second plug71. The storage node72may have a cylinder type and may have a pillar type in other embodiments. Although not shown, a dielectric layer and a plate node may be further formed over the storage node72.

The semiconductor device according to the aforementioned embodiments may be applied to dynamic random access memory (DRAM), but is not limited thereto. The semiconductor device may be applied to static random access memory (SRAM), flash memory, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), and phase change random access memory (PRAM), for example.

FIG. 5is a schematic diagram of a memory card.

Referring toFIG. 5, the memory card200may include a controller210and memory220. The controller210and the memory220may exchange electric signals. For example, the memory220and the controller210may exchange data in response to an instruction from the controller210. Accordingly, the memory card200may store data in the memory220or externally output data from the memory220. The memory220may include air gaps and plugs, such as those described above. The memory card200may be used as a variety of data storage media for a variety of handheld devices. For example, the memory card200may include a memory stick card, a smart media (SM) card, a secure digital (SD) card, a mini-secure digital (mini SD) card, or a multi-media card (MMC), etc.

FIG. 6is a block diagram of an electronic system.

Referring toFIG. 6, the electronic system300may include a processor310, an I/O device330, and a chip320. The processor310, the I/O device330, and the chip320may communicate data with each other by using a bus340. The processor310may function to execute a program and control the electronic system300. The I/O device330may be used to input or output the data of the electronic system300. The electronic system300may be connected to an external device, for example, a personal computer or a network through the I/O device330and may exchange data with the external device. The chip320may store a code and data for the operation of the processor310and process part of an operation assigned by the processor310. For example, the chip320may include air gaps and plugs, such as those described above. The electronic system300may form a variety of electronic control devices that require the chip320. For example, the electronic system300may be used in mobile phones, MP3 players, navigators, solid state disks (SSDs), and household appliances.

This technology has an advantage in that it may reduce parasitic capacitance due to the air gap having a low dielectric constant because the air gap is formed between the conductive structures.

Furthermore, this technology is advantageous in that the air gap may be prevented from being opened in a subsequent process because the passivation layer is formed over the capping layer that caps the air gap and thus the air gap may be stably capped.