RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

BACKGROUND

Modern digital very-large-scale integration (VLSI) circuits commonly operate at supply voltages of around 2.5 volts or below. However, certain integrated circuits (ICs) call for additional on-chip circuits operating at higher voltages. Examples of such high-voltage circuits include input/output (IO) interface circuits with various off-chip system components such as power management switches, analog input circuits conditioning transducer signals, or output analog drive functions for speakers or other actuators.

In order to accommodate different voltage levels, some integrated circuits make use of multiple different gate oxide thicknesses to build both low voltage transistors and high voltage transistors on the same IC chip. However, this method increases process complexity and cost. An alternative solution is to use lateral asymmetric source and drain MOS transistors having a lightly doped n-type gap between the drain and gate (for n-type devices) to enable use of higher drain to source voltages, such as laterally diffused Metal-Oxide-Semiconductor (LDMOS) or drain-extended MOS (DeMOS) which have drain structures capable of operating at higher voltages as compared to conventional symmetric MOS transistors.

In an LDMOS transistor, a lightly doped lateral diffused drain region is constructed between the heavily doped drain contact and the transistor channel region. As the name implies, a lateral current is created between drain and source. A depletion region forms in this lightly doped lateral diffused region resulting in a voltage drop between the drain contact and the transistor gate. With proper design, sufficient voltage may be dropped between the drain contact and the gate dielectric to allow a low gate voltage transistor to be used as a switch for the high voltage.

Some lateral power transistors include “RESURF” regions, which is short for reduced surface electric field regions. For purposes of this patent application, the term “RESURF” is understood to refer to a material which reduces an electric field in an adjacent surface semiconductor region. A RESURF region may be for example a buried semiconductor region (or layer) with an opposite conductivity type from the adjacent semiconductor region (or layer). RESURF structures are described in Appels, et. al., “Thin Layer High Voltage Devices” Philips J, Res. 35 1-13, 1980. The RESURF region(s) for lateral power transistors are generally referred to as buried drift regions.

It is desirable for a power transistor such as an LDMOS to be as close to a perfect switch as possible, i.e., as close to zero resistance in the ON state and an open circuit in the OFF state as possible. Because minimizing die area is crucial to minimizing costs, a key metric for an LDMOS transistor is its specific on-resistance Rsp. The specific on-resistance Rspis defined as the drain-to-source resistance of the transistor in a given amount of area when the transistor is on. Thus Rspcan be expressed as Rsp=Rds(ON)·Area, where Rds(ON)is the drain-to-source on-resistance (the resistance of the LDMOS device in its triode region), and Area is the size of the device. For a switch having a given on-resistance, lower RspLDMOS can consume less silicon area.

SUMMARY

Illustrative embodiments of this disclosure are directed to RESURF-based dual-gate p-n bimodal-conduction laterally-diffused metal oxide semiconductors (LDMOS). In certain illustrative embodiments, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of the semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

In other illustrative embodiments, an n-type source is electrically coupled to a p-type drain. An n-type drain is electrically coupled to a p-type source. A p-type layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-type top layer is disposed above and adjacent to the p-type layer. The n-type top layer serves as an n-type conduction channel between the n-type drain and the n-type source. The n-gate controls current flow in the n-type conduction channel, and the p-gate controls current flow in the p-type conduction channel.

DETAILED DESCRIPTION

FIG. 1is a cross-sectional view of a RESURF-based double-gate laterally diffused metal oxide semiconductor (LDMOS) integrated circuit100with p-n bimodal conduction. The LDMOS integrated circuit100comprises an n-type LDMOS transistor having a p-type transistor embedded therein. The n-type transistor of the LDMOS integrated circuit100will at times be referred to herein as an NMOS device. Similarly, the p-type transistor of the LDMOS integrated circuit100will at times be referred to herein as a PMOS device. The LDMOS integrated circuit100includes an n-type region105formed over a p-type substrate110, and a p-type layer115, sometimes referred to as a RESURF layer, buried within the n-type region105. As used herein, a “p-type” region or layer refers to a region or layer that is positively doped, i.e., doped with a positive charge, while an “n-type” region or layer refers to a region or layer that is negatively doped, i.e., doped with a negative charge. A p-type top layer120of the LDMOS device100is formed on top of the n-type region105and serves as a RESURF region. As mentioned, the p-type buried layer115and the p-type top layer120function as RESURF regions, which means they serve to reduce an electric field in their respective adjacent n-type regions105.

A drain electrode125is coupled to a highly negatively doped (n+) implant130that is embedded in the n-type region105. The drain electrode125serves as the drain of the n-type LDMOS transistor of the integrated circuit100. The drain electrode125of the n-type transistor is also electrically coupled to a second electrical contact135that is coupled to a highly positively doped (p+) implant140, or region, that is embedded in the n-type region105. The second contact135serves as the source of the PMOS transistor that is embedded in the integrated circuit100. The source of the PMOS transistor will at times be referred to herein as the p-source135.

A source electrode145is coupled to a highly negatively doped (n+) implant150that is embedded in a p-type well165within the n-type region105. The source electrode145serves as the source of the n-type LDMOS transistor of the integrated circuit100. The source electrode145of the n-type transistor is also electrically coupled to a second electrical contact170that is coupled to a highly positively doped (p+) implant175that is embedded in the top p-type layer120. The second contact170forms the drain of the PMOS transistor that is embedded in the integrated circuit100. The p-type top RESURF region120thus serves as a drain extension of the PMOS. Said second contact170constituting the drain of the p-type transistor will at times be referred to herein as the p-drain. In an illustrative embodiment, the source electrode145of the n-type transistor is also electrically coupled to a third electrical contact155that is coupled to a highly positively doped (p+) implant160that is embedded in the p-well165. The third contact155forms part of the drain of the PMOS transistor, together with the drain contact170coupled to the top p-type layer120. In such an embodiment, the buried p-type RESURF region115thus serves as a further drain extension of the PMOS.

The voltage present at the n-gate180controls the current flow from the drain125to the source145of the n-type LDMOS transistor of the integrated circuit100. The drain-to-source current Ids-nof the n-type transistor comprises electrons flowing from the source145to the drain125in the top and bottom channels of the n-type region105, as shown inFIG. 1.

The voltage present at the p-gate185controls the current flow from the source135of the p-type transistor to the drain170of the p-type transistor of the integrated circuit100. In an illustrative embodiment, the source-to-drain current Isd-pof the p-type transistor comprises holes flowing from the p-source135to the p-drain170in the top p-type layer120, as shown inFIG. 1. This flow of electrons in one channel (the n-region105) and the flow of holes in the opposite direction in another channel (the top p-type layer120) is referred to herein as p-n bimodal conduction. It is important to note that the bimodal conduction is still unipolar conduction, with the electron and hole flows confined in separate conduction paths.

In an illustrative embodiment, the source-to-drain current Isd-pfurther comprises holes flowing from the p-source135to the p-drain155in the buried p-type layer115. In an illustrative embodiment, the integrated circuit100includes, at spaced intervals in the device width direction (i.e., the 3rddimension ofFIG. 1) of the LDMOS device100, positively doped regions (not shown inFIG. 1) connecting the buried p-type layer115to the p-well165, in order to facilitate current flow between the p-drain155and the buried p-type layer115. For example, in one embodiment such p-type regions are placed at intervals of approximately every 20 μm in the width direction of the LDMOS device100. Placing these p-type regions at spaced intervals as opposed to having a continuous connection between the buried p-type layer115and the p-well165allows current (in the form of holes) to flow between the p-drain155and the buried p-type layer115while still allowing current (in the form of electrons) to flow in the n-type region105between the source145and the bottom channel. Similarly, in an illustrative embodiment, the integrated circuit100also includes, at spaced intervals in the width direction, positively doped regions (not shown inFIG. 1) connecting the buried p-type layer115to the top p-type layer120proximate the p-source135, in order to facilitate current flow between the p-source135and the buried p-type layer115. Placing these p-type regions at spaced intervals as opposed to having a continuous connection between the buried p-type layer115and the top p-type layer120allows current (in the form of holes) to flow between the p-source135and the buried p-type layer115while still allowing current (in the form of electrons) to flow in the n-type region105between the drain125and the top channel. These vertical diffusion connections must be carefully designed to avoid localized premature breakdown in the OFF state.

The high voltage p-n bimodal LDMOS integrated circuit100can block voltage only when both the n-channel105and p-channel120are turned off. The device100can be used as an NMOS transistor when the n-channel is on (conducting), as a PMOS transistor when the p-channel is on, or as a synchronized switch when both channels are on simultaneously. When both the n-channel and p-channel are conducting simultaneously, the total drain-to-source current flow Ids-pnof the bimodal LDMOS device100is equal to the sum of the net drain-to-source current Ids-nof the n-type LDMOS plus the net source-to-drain current Isd-pof the slave PMOS. Thus the total drain-to-source current Ids-pnof the bimodal LDMOS integrated circuit100is enhanced, both in the linear region of the Idscurve and in the saturation region. With electron flow in the n-drift region105and hole flow in the p-type (RESURF) region120, p-n conduction in parallel reduces the specific on-resistance Rspand improves drive current. In the illustrative embodiment wherein the buried p-type RESURF layer115is used as a further drain extension of the slave PMOS by periodically forming vertical p-type connections in the device width direction, bimodal p-n conduction is further enhanced.

FIG. 2is a schematic circuit diagram of a dual-gate p-n bimodal conduction LDMOS transistor. The dual-gate LDMOS transistor100ofFIG. 2illustratively corresponds to the LDMOS integrated circuit ofFIG. 1. Thus elements common toFIGS. 1 and 2are identified with like reference numbers. The LDMOS dual-gate p-n transistor100ofFIG. 2comprises an NMOS transistor200and a PMOS transistor210. NMOS transistor200comprises a drain terminal125, source terminal145, and a gate terminal180. The voltage present at the gate terminal180dictates in part the flow of current from the drain125to the source145, as is described above with respect toFIG. 1. PMOS transistor210comprises a source terminal135, drain terminal170, and a gate terminal185. The voltage present at the gate terminal185dictates in part the flow of current from the source135to the drain170, as is described above with respect toFIG. 1. The drain125of the NMOS transistor200is coupled to the source135of the PMOS transistor210, and the source145of the NMOS transistor200is coupled to the drain170of the PMOS transistor210. Thus the total current flow from the node comprising the n-drain125and the p-source135, to the node comprising the n-source145and the p-drain170, is Ids-n+Isd-p, i.e., the sum of the drain-to-source current Ids-nof the NMOS device200and the source-to-drain current Isd-pof the PMOS device210.

FIG. 3is graph representing drain-to-source current Idsand drain-to-source resistance Rdsas a function of drain-to-source voltage Vdsat maximum gate biases for a dual-gate, bimodal conduction LDMOS such as that shown inFIG. 1. Plot300represents the on-state drain-to-source current Ids-nwhen the dual-gate, bimodal conduction LDMOS100when the device is operated as an NMOS device, i.e., when the voltage at the n-gate180causes the n-channel105to conduct while the voltage at the p-gate185causes the p-channel120to be turned off. Plot310represents the associated on-state drain-to-source resistance Rds-nwhen the LDMOS integrated circuit100is operated as an NMOS device. Plot320represents the on-state drain-to-source current Ids-pnwhen the dual-gate, bimodal conduction LDMOS100when the device is operated as a bimodal conduction p-n device, i.e., when the voltage at the n-gate180causes the n-channel105to conduct while the voltage at the p-gate185simultaneously causes the p-channel120to conduct. Note that when referring to the drain-to-source current Ids-pnof the p-n bimodal LDMOS100, this refers to the current flowing from the drain125of the NMOS transistor200(which is coupled to the source of the PMOS transistor210) to the source145of the NMOS transistor200(which is coupled to the drain170of the PMOS transistor210). Plot330represents the associated on-state drain-to-source resistance Rds-pnwhen the LDMOS integrated circuit100is operated as a bimodal conduction p-n device. As can be seen inFIG. 3, Idsfor both the unimodal NMOS conduction mode300and the bimodal p-n conduction mode320increases in a substantially linear fashion until the device saturates (between 20V and 40V for the illustrative device represented byFIG. 3). Similarly, the on-resistance Rdsfor both the unimodal NMOS conduction mode310and the bimodal p-n conduction mode330increases quite linearly until the device saturates. As can be seen inFIG. 3, operating the LDMOS device100as a bimodal p-n device significantly enhances Ids, and therefore reduces Rds, in both the linear region and the saturation region.

Specific on-resistance Rspfor a power device is usually measured at very low Vds, where the device operates in the linear region. However, the maximum output current in power switching circuits is determined by the saturation drain-to-source current Ids,sat, defined at the saturation voltage Vds,sat, and the thermal dissipation. Also, the on-state current and corresponding drain-to-source voltage Vdsfor a power switch varies with different load conditions. Therefore, it is desirable to have a smaller slope for the linear plot of Rdsvs. Vdswhen the switch is on. As can be seen inFIG. 3, the p-n bimodal conduction enhances the drive current by at least 30% at Vdsof 20V compared to n-type conduction only. With the slave p-gate185fully on, the Rds-pn330dependence on Vdsbefore the device saturates is minimized with a slope of 2.5% increase per volt, which can lead to lower conduction loss and lower thermal dissipation. In contrast, the Rds-n310of n-conduction LDMOS increases with Vdsat a rate of approximately 5% per volt.

FIG. 4is a cross-sectional view of a RESURF-based dual-gate LDMOS integrated circuit400with p-n bimodal conduction. The LDMOS integrated circuit400comprises a p-type LDMOS transistor having an n-type transistor embedded therein. In that sense, the LDMOS device400is the inverse of the LDMOS device100ofFIG. 1, which comprises an n-type LDMOS transistor having a p-type transistor embedded therein. The p-type transistor of the LDMOS integrated circuit400will at times be referred to herein as a PMOS device. Similarly, the n-type transistor of the LDMOS integrated circuit100will at times be referred to herein as an NMOS device. The LDMOS integrated circuit400includes a p-type region405formed over an n-type substrate410, and an n-type RESURF layer415buried within the p-type region405. An n-type top layer420of the LDMOS device400is formed on top of the p-type region405and serves as a RESURF region. As mentioned, the n-type buried layer415and the n-type top layer420function as RESURF regions, which means they serve to reduce an electric field in their respective adjacent p-type regions405.

A drain electrode425is coupled to a highly positively doped (p+) implant440that is embedded in the p-type region405. The drain electrode425serves as the drain of the p-type LDMOS transistor of the integrated circuit400. The drain electrode425of the p-type transistor is also electrically coupled to a second electrical contact435that is coupled to an n+ implant430, or region, that is embedded in the p-type region405. The second contact435serves as the source of the NMOS transistor that is embedded in the integrated circuit400. The source of the NMOS transistor will at times be referred to herein as the n-source435.

A source electrode445is coupled to a p+ implant460that is embedded in an n-type well165within the n-type region405. The source electrode445serves as the source of the p-type LDMOS transistor of the integrated circuit400. The source electrode445of the n-type transistor is also electrically coupled to a second electrical contact470that is coupled to an n+ implant475that is embedded in the top n-type layer420. The second contact470forms the drain of the NMOS transistor that is embedded in the integrated circuit400. The n-type top RESURF region420thus serves as a drain extension of the NMOS. The second contact470constituting the drain of the n-type transistor will at times be referred to herein as the n-drain. In an illustrative embodiment, the source electrode445of the p-type transistor is also electrically coupled to a third electrical contact455that is coupled to a highly negatively doped (n+) implant450that is embedded in the n-well465. The third contact455forms part of the drain of the NMOS transistor, together with the drain contact470coupled to the top n-type layer420. In such an embodiment, the buried n-type RESURF region415thus serves as a further drain extension of the NMOS.

The voltage present at the p-gate485controls the current flow from the source445to the drain425of the p-type LDMOS transistor of the integrated circuit400. The source-to-drain current Isd-pof the p-type transistor comprises holes flowing from the source445to the drain425in the top and bottom channels of the p-type region405, as shown inFIG. 4.

The voltage present at the n-gate480controls the current flow from the drain470of the n-type transistor to the source435of the n-type transistor of the integrated circuit400. In an illustrative embodiment, the drain-to-source current Ids-nof the n-type transistor comprises electrons flowing from the n-source435to the n-drain470in the top n-type layer420, as shown inFIG. 4.

In an illustrative embodiment, the drain-to-source current Ids-nfurther comprises electrons flowing from the n-source435to the n-drain455in the buried n-type layer415. In an illustrative embodiment, the integrated circuit400includes, at spaced intervals in the device width direction (i.e., the 3rddimension ofFIG. 4) of the LDMOS device400, positively doped regions (not shown inFIG. 4) connecting the buried n-type layer415to the n-well465, in order to facilitate current flow between the n-drain455and the buried n-type layer415. For example, in one embodiment such n-type regions are placed at intervals of approximately every 20 μm in the width direction of the LDMOS device400. Placing these n-type regions at spaced intervals as opposed to having a continuous connection between the buried n-type layer415and the n-well465allows current (in the form of electrons) to flow between the n-drain455and the buried n-type layer115while still allowing current (in the form of holes) to flow in the p-type region405between the source445and the bottom p-channel. Similarly, in an illustrative embodiment, the integrated circuit400also includes, at spaced intervals in the device width direction, negatively doped regions (not shown inFIG. 1) connecting the buried n-type layer415to the top n-type layer420proximate the n-source435, in order to facilitate current flow between the n-source435and the buried n-type layer415. Placing these n-type regions at spaced intervals as opposed to having a continuous connection between the buried n-type layer415and the top n-type layer420allows current (in the form of electrons) to flow between the n-source435and the buried n-type layer415while still allowing current (in the form of holes) to flow in the p-type region405from the top p-channel to the drain425.

FIG. 5is a cross-sectional view of a RESURF-based double-gate LDMOS integrated circuit500with p-n bimodal conduction. The LDMOS integrated circuit500is similar to the LDMOS integrated circuit100ofFIG. 1but includes two n-gates580,590and a continuous connection between the p-buried layer515and the p-well565. The LDMOS integrated circuit100comprises an n-type LDMOS transistor having a p-type transistor embedded therein. The LDMOS integrated circuit500includes an n-type region505formed over a p-type substrate510, and a p-type RESURF layer515buried within the n-type region505. A p-type top layer520of the LDMOS device500is formed on top of the n-type region505and serves as a RESURF region.

A drain electrode525is coupled to a highly negatively doped (n+) implant530that is embedded in the n-type region505. The drain electrode525serves as the drain of the n-type LDMOS transistor of the integrated circuit500. The drain electrode525of the n-type transistor is also electrically coupled to a second electrical contact535that is coupled to a highly positively doped (p+) implant540, or region, that is embedded in the n-type region505. The second contact535serves as the source of the PMOS transistor that is embedded in the integrated circuit500.

A source electrode545is coupled to an n+ implant550that is embedded in a p-type well565within the n-type region505. The source electrode545serves as the source of the n-type LDMOS transistor of the integrated circuit500. The source electrode545of the n-type transistor is also electrically coupled to a second electrical contact570that is coupled to a p+ implant575that is embedded in the top p-type layer520. The second contact570forms the drain of the PMOS transistor that is embedded in the integrated circuit500. The p-type top RESURF region520thus serves as a drain extension of the PMOS. The second contact570constituting the drain of the p-type transistor will at times be referred to herein as the p-drain. In an illustrative embodiment, the source electrode545of the n-type transistor is also electrically coupled to a third electrical contact555that is coupled to a p+ implant560that is embedded in the p-well565. The third contact555forms part of the drain of the PMOS transistor, together with the drain contact570coupled to the top p-type layer520. In such an embodiment, the buried p-type RESURF region515thus serves as a further drain extension of the PMOS.

The voltage present at the p-gate585controls the current flow from the source535of the p-type transistor to the drain570of the p-type transistor of the integrated circuit500. In the illustrative embodiment ofFIG. 5, the source-to-drain current Isd-pof the p-type transistor comprises holes flowing from the p-source535to the p-drain570in both the top p-type layer520and in the buried p-type layer515. As shown inFIG. 5, the buried p-type layer is continuously connected to the p-well565(as opposed to the spaced-apart connections described with respect toFIG. 1), in order to facilitate current flow between the p-drain555and the buried p-type layer515. In an illustrative embodiment, the integrated circuit500also includes, at spaced intervals in the device width direction (i.e., the 3rddimension ofFIG. 5) of the LDMOS device500, positively doped regions595connecting the buried p-type layer515to the top p-type layer520proximate the p-source535, in order to facilitate current flow between the p-source535and the buried p-type layer515. Placing these p-type regions at spaced intervals as opposed to having a continuous connection between the buried p-type layer515and the top p-type layer520allows current (in the form of holes) to flow between the p-source535and the buried p-type layer515while still allowing current (in the form of electrons) to flow in the n-type region505from the drain525to the top n-channel.

In an illustrative embodiment, the dopant concentration of the buried p-type layer515is variable, with the concentration being highest adjacent to the p-well565and gradually decreasing as the distance from the p-well565increases, to a minimum dopant concentration at the end of the buried p-type layer515most distal to the p-well565, i.e., the end nearest the n-drain525.

Because the LDMOS device500ofFIG. 5has a continuous connection between the buried p-type layer515and the p-well565, this continuous connection forms a barrier between the n-gate580and the bottom channel of the n-type region505. Therefore, the LDMOS integrated circuit500ofFIG. 5includes a second n-gate590. The voltage present at the first n-gate580controls the current flow from the drain525to the source545via the top channel of the n-type region505, while the second n-gate590controls the current flow from the drain525to the source545via the bottom channel of the n-type region505. The drain-to-source current Ids-nof the n-type transistor comprises electrons flowing from the source545to the drain525in the top and bottom channels of the n-type region505, as shown inFIG. 5.

It is noted that the embodiments disclosed herein are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure. Furthermore, in some instances, some features may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the broad inventive concepts disclosed herein.