Low-power supply voltage level detection circuit and method

An input power supply voltage level detection circuit and method are presented. The circuit includes a main detector core and a two-inverter buffer block that can include a first inverter and a second inverter. The circuit receives a voltage input signal and outputs a voltage output signal that is substantially equal to either the voltage input signal or ground, depending on whether the voltage input signal has reached a threshold voltage. The threshold voltage is defined by component characteristics of the main detector core and the two-inverter buffer block. The circuit can receive a hysteresis input signal, tied to the voltage input signal or the ground, that allows the threshold voltage to have a first threshold value when the voltage input signal increases and a second threshold value when the voltage input signal decreases. A power down input signal can also be received that allows the circuit to be powered down.

BACKGROUND

The present invention is related to power supply voltage level detection and control for use in electronic circuits.

2. Related Art

Previous voltage level detectors consume large amounts of power and current and do not maintain a constant threshold voltage over process and temperature variations. Therefore, what is needed is a low-power, input power supply voltage level detection circuit that maintains a substantially constant threshold voltage over process and temperature variations and keeps current consumption as low as possible.

SUMMARY

An input power supply voltage level detection circuit and method are presented. The circuit includes a main detector core and a two-inverter buffer block that can include a first inverter and a second inverter. The circuit receives a voltage input signal and outputs a voltage output signal that is substantially equal to either the voltage input signal or ground, depending on whether the voltage input signal has reached a threshold voltage. In an example embodiment, the voltage output signal substantially equals the ground when the voltage input signal is below the threshold voltage and substantially equals the voltage input signal otherwise. The threshold voltage is defined by component characteristics of the main detector core and the two-inverter buffer block.

The circuit can receive a hysteresis input signal, tied to the voltage input signal or the ground, that allows the threshold voltage to have a first threshold value when the voltage input signal increases and a second threshold value when the voltage input signal decreases. This prevents erratic fluctuation of the voltage output signal when the voltage input signal hovers just above and just below the threshold voltage.

A power down input signal can also be received by the circuit that allows the circuit to be powered down when the circuit is not needed.

One useful example application of this input power supply voltage level detection circuit is to determine whether a battery used as a power supply can supply sufficient power. Another useful example application of this input power supply voltage level detection circuit is in a power-on-reset (POR) circuit. For example, a power-on-reset of a circuit or system can be conducted if the voltage input signal drops below the threshold voltage as detected by the input power supply voltage level detection circuit. It will be apparent to a person skilled in the pertinent art(s) that this detection circuit can also be employed in a variety of other applications.

An advantage of this input power supply voltage level detection circuit includes keeping the threshold voltage substantially constant over process and temperature variations. Another advantage includes keeping the power consumption of the detection circuit as low as possible, which can be important when current consumption concerns are critical. A further advantage is that a startup circuit is not required.

The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers may indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number may identify the drawing in which the reference number first appears.

DETAILED DESCRIPTION OF THE INVENTION

While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art(s) will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present invention. It will be apparent to a person skilled in the pertinent art(s) that this invention can also be employed in a variety of other applications.

FIG. 1is a block diagram of an input power supply voltage level detection circuit100, according to various embodiments of the present invention. Circuit100includes a voltage input108, a ground112, a main detector core102and a two-inverter buffer block103. Main detector core102receives a voltage input signal Vddand a ground signal Vssand outputs a main detector core output signal114, an analog signal, at main detector core output105. The two-inverter buffer block103receives voltage input signal Vdd, ground signal Vss, and main detector core output signal114, converts main detector core output signal114to a digital signal, and outputs a voltage output signal VOUTat a voltage output110. Voltage output signal VOUTis substantially equal to voltage input signal Vddor ground signal Vssdepending on whether voltage input signal Vddhas reached a threshold voltage. The threshold voltage can be defined by the characteristics of components of main detector core102and two-inverter buffer block103.

The two-inverter buffer block103can include a first inverter104and a second inverter106. First inverter104receives voltage input signal Vdd, ground signal Vss, and main detector core output signal114(from main detector core102), and outputs a first inverter output signal116at a first inverter output107. Second inverter106receives voltage input signal Vdd, ground signal Vssand first inverter output signal116, and outputs voltage output signal VOUTat voltage output110. As stated above, voltage output signal VOUTis substantially equal to voltage input signal Vddor ground signal Vssdepending on whether voltage input signal Vddhas reached a threshold voltage. The threshold voltage can be defined by the characteristics of components of main detector core102and first inverter104.

Input power supply voltage level detection circuit100can optionally include a hysteresis input118that can provide a hysteresis input signal HYS to main detector core102. Hysteresis input signal HYS allows the threshold voltage to have a first threshold value when voltage input signal Vddincreases and a second threshold value when voltage input signal Vdddecreases. This prevents erratic fluctuation of voltage output signal VOUTwhen voltage input signal Vddhovers just above and just below the threshold voltage. This will be discussed in more detail below with reference toFIG. 4.

Input power supply voltage level detection circuit100can optionally include a power down input120that can provide a power down input signal PWDN to main detector core102. Power down input signal PWDN allows input power supply voltage level detection circuit100to be powered down when circuit100is not needed.

FIG. 2is a schematic diagram of an input power supply voltage level detection circuit200, according to an embodiment. Circuit200includes voltage input108, ground112, optional hysteresis input118, main detector core102, and two-inverter buffer block103(including first inverter104and second inverter106), as shown inFIG. 1. InFIG. 2, main detector core102is shown to include resistors232and234and transistors236,238,240, and242. A first end of resistor232is coupled to voltage input108. Transistor236includes a source coupled to a second end of resistor232and a gate coupled to optional hysteresis input118. Transistor238includes a source coupled to the second end of resistor232and a gate coupled to ground112. A first end of resistor234is coupled to drains of transistors236and238at the location of main detector core output105(shown inFIG. 1) that outputs main detector core output signal114. Transistor240includes a drain and gate both coupled to a second end of resistor234, and a source coupled to ground112. Transistor242includes a source and drain both coupled to ground112and a gate coupled to the drains of transistors236and238(at main detector core output105). Transistor242is used as a capacitor to make the circuit more immune to noise and fast input transitions and spikes. The embodiment shown inFIG. 2shows transistors236and238as PMOS transistors and transistors240and242as NMOS transistors. However, these transistors are not limited to these types of transistors.

First inverter104includes transistors244,246, and248. The gates of transistors244,246, and248are coupled to each other and to the drains of transistors236and238as well as the gate of transistor242(at main detector core output105). A source of transistor244is coupled to voltage input108. A source of transistor246is coupled to a drain of transistor244. A source of transistor248is coupled to ground112. The drains of transistors246and248are coupled to each other at the location of first inverter output107(shown inFIG. 1), which outputs first inverter output signal116. The embodiment shown inFIG. 2shows transistors244and246as PMOS transistors and transistor248as an NMOS transistor. However, these transistors are not limited to these types of transistors.

Second inverter106includes transistors250and252. The gates of transistors250and252are coupled to each other and to the drains of transistors246and248(at first inverter output107, shown inFIG. 1). A source of transistor250is coupled to voltage input108. A source of transistor252is coupled to ground112. The drains of transistors250and252are coupled to each other at the location of voltage output110, which outputs voltage output signal VOUT. The embodiment shown inFIG. 2shows transistor250as a PMOS transistor and transistor252as an NMOS transistor. However, these transistors are not limited to these types of transistors.

The threshold voltage obtained by input power supply voltage level detection circuit200depends on the component characteristics of main detector core102and first inverter104. For example, the sizing of resistors232and234, the sizing of transistors236,238,240,244,246, and248, and the ratio of transistors244and246to transistor248, all play an important role in defining the threshold voltage.

The functionality of circuits100/200can be described briefly as follows. Voltage input signal Vddis received at main detector core102. Main detector core102provides main detector core output signal114, which can be an analog signal, to two-inverter buffer block103. The two-inverter buffer block103converts main detector core output signal114to a digital voltage output signal VOUT. A threshold voltage is defined by component characteristics of main detector core102and two-inverter buffer block103(specifically, first inverter104). The value of voltage output signal VOUTdepends on whether voltage input signal Vddhas reached the threshold voltage. If voltage input signal Vddhas not reached the threshold voltage, then voltage output signal VOUTis substantially equal to ground112. If voltage input signal Vddhas reached the threshold voltage, then voltage output signal VOUTis substantially equal to voltage input signal Vdd. If optional hysteresis input118is used, the threshold voltage can have a first value when voltage input signal Vddincreases and a second value when voltage input signal Vdddecreases, which is useful in preventing erratic fluctuation of voltage output signal VOUTwhen voltage input signal Vddhovers just above and just below the threshold voltage. If optional power down input120is used (see circuit100ofFIG. 1), power down input signal PWDN can allow circuit100to be powered down when circuit100is not needed. For example, if circuit100is powered down using power down input signal PWDN, then instead of depending on a threshold voltage, voltage output signal VOUTis a floating (high impedance) voltage output signal. The functionality of circuits100/200(and also500) is further described below.

FIG. 3is a graph300showing voltage output signal VOUTversus voltage input signal Vdd, according to an embodiment. If input power supply voltage level detection circuit200is in operation, as voltage input signal Vddincreases, voltage output signal VOUTwill remain low (e.g., 0 volts) until voltage input signal Vddreaches threshold voltage VT, as shown by line portion382. Once voltage input signal Vddreaches threshold voltage VT, then voltage output signal VOUTsubstantially equals Vdd, as shown by line portion384. If voltage input signal Vdddecreases, the same graph can be followed in the opposite direction if optional hysteresis input118is not used. Once voltage input signal Vdddecreases to below threshold voltage VT, voltage output signal VOUTwill drop back to low (e.g., 0 volts).

If optional hysteresis input118is used, the threshold voltage can have a first value when voltage input signal Vddincreases and a second value when voltage input signal Vdddecreases. Hysteresis input118can be tied to voltage input108or ground112. When hysteresis input118is tied to ground112, the value of the voltage threshold is lower than when hysteresis input118is tied to voltage input108. This is because there is a lower resistance over transistors236/238when hysteresis input118is tied to ground112versus when it is tied to voltage input108.

As stated earlier, using hysteresis input118is useful in preventing erratic fluctuation of voltage output signal VOUTwhen voltage input signal Vddhovers just above and just below the threshold voltage. For example, assume voltage input signal Vddhas a nominal value of 3 volts, and that the characteristics of the components of an input power supply voltage level detection circuit are such that the threshold voltage (e.g., VT) is 1.5 volts. If voltage input signal Vddwavers between, for example, 1.6 volts and 1.4 volts, then voltage output signal VOUTwill fluctuate between a low voltage value (e.g., 0 volts) and the value of voltage input signal Vdd. In order to minimize erratic fluctuations of voltage output signal VOUT, it is useful to use hysteresis input118to provide a second threshold value for when voltage input signal Vdddecreases. When hysteresis input118is used, the threshold voltage (e.g., VT) can have a value of 1.5 volts, for example, when voltage input signal Vddincreases, and can have a value of 1.2 volts, for example, when voltage input signal Vdddecreases.

FIG. 4is a graph400depicting the effect of using hysteresis input118to define two threshold values. If input power supply voltage level detection circuit200is in operation and hysteresis input118is used, then as voltage input signal Vddincreases, voltage output signal VOUTwill remain low (e.g., 0 volts) until voltage input signal Vddreaches threshold voltage VT1, as shown by line portion382(similar to that shown in graph300ofFIG. 3). Once voltage input signal Vddreaches threshold voltage VT1, then voltage output signal VOUTincreases (depicted by arrow490) to substantially equal Vdd, as shown by line portion384(similar to that shown in graph300ofFIG. 3). In the alternative, if voltage output signal VOUTsubstantially equals voltage input signal Vdd, and voltage input signal Vddis decreasing, VOUTsubstantially equals voltage input signal Vdduntil Vdddrops below threshold voltage VT2, as shown by line portion486. Once voltage input signal Vdddrops below threshold voltage VT2, then voltage output signal VOUTdecreases (depicted by arrow492) to low voltage (e.g., 0 volts), as shown by line portion488.

Using hysteresis input118is optional, although there are advantages to using it, as described above. If using an input power supply voltage level detection circuit in a power-on-reset circuit, the hysteresis input118would be useful.

FIG. 5is a schematic diagram of an input power supply voltage level detection circuit500, according to an embodiment that includes a power down signal input. Circuit500is substantially the same as circuit200(shown inFIG. 2) but includes power down input120(as shown optionally inFIG. 1) that provides power down input signal PWDN to transistors594and596. Transistor594is placed between resistor232and transistors236/238such that a source of transistor594is coupled to the second end of resistor232, a drain of transistor594is coupled to the sources of transistors236and238, and a gate of transistor594is coupled to power down input120. Transistor596is placed between voltage input108and transistor244such that a source of transistor596is coupled to voltage input108, a drain of transistor596is coupled to the source of transistor244, and a gate of transistor596is coupled to power down input120. During normal operation of circuit500, power down input signal PWDN is low. A high power down input signal PWDN can be used to power down circuit500when it is not needed, for example, such that voltage output signal VOUTwill be a floating (high impedance) voltage output signal. This feature can be used when it is desired to save power. The embodiment shown inFIG. 5shows transistors594and596as PMOS transistors. However, these transistors are not limited to this type of transistor.

A method600of controlling an input power supply level in a circuit, according to the above-described embodiments, is shown inFIG. 6. Method600starts at step602and immediately proceeds to step604. In step604, a voltage input signal is received at a main detector core. In step610, a main detector core output signal is output. The main detector core output signal can be an analog signal. In step612, the voltage input signal and the main detector core output signal are received at a two-inverter buffer block. Method600can include converting the main detector core output signal to a digital signal at the two-inverter buffer block. In step614, a voltage output signal is output that is substantially equal to the voltage input signal or a ground, depending on whether the voltage input signal has reached a threshold voltage. For example, the voltage output signal is substantially equal to the voltage input signal if the voltage input signal is at or above the threshold voltage, and is substantially equal to ground otherwise. The threshold voltage can be defined by component characteristics of the main detector core and the two-inverter buffer block. Method600terminates at step618.

An optional step606includes receiving a hysteresis input signal at the main detector core that allows a threshold voltage to have a first value when the voltage input signal increases and a second value when the voltage input signal decreases. Step606is useful in preventing erratic fluctuation of the voltage output signal when the voltage input signal hovers just above and just below the threshold voltage. The hysteresis input signal is tied to either the voltage input signal or ground. The threshold voltage has a higher value when the hysteresis input signal is substantially equal to the voltage input signal than when the hysteresis input signal is substantially equal to ground.

Another optional step608includes receiving a power down input signal at the main detector core that can allow the circuit to be powered down. Step608can be used to save power when input power supply level control is not needed. For example, when the power down signal does not indicate a power-down (e.g., the power down signal is low), the circuit can operate normally (as described above), and when the power down signal indicates a power-down (e.g., the power down signal is high), the circuit can be “powered down” at step616such that the voltage output signal that is output at step616is a floating (high impedance) voltage output signal. The method would then terminate at step618.

Step612can include the steps shown inFIG. 7. Step612starts with step702and immediately proceeds to step704. In step704, the voltage input signal and the main detector core output signal are received at a first inverter. In step706, a first inverter output signal is output. In step708, the voltage input signal and the first inverter output signal are received at a second inverter. In step710, the method returns to step614.

Step614can include the steps shown inFIG. 8. Step614starts with step802and immediately proceeds to step804. In step804, the voltage input signal is monitored. In step806, it is determined whether the voltage input signal has reached the threshold voltage. If the voltage input signal has not reached the threshold voltage, the method returns to step804. If the voltage input signal has reached the threshold voltage, the method proceeds to step808. In step808, it is determined whether the voltage input signal is increasing or decreasing. If the voltage input signal is increasing, the method proceeds to step810. Alternatively, if the voltage input signal is decreasing, the method proceeds to step812. In step810, the voltage output signal is output as substantially equal to the voltage input signal, and the method returns to step618at step814. In step812, the voltage output signal is output as substantially equal to ground, and the method returns to step618at step814.

Method600can further conduct a power-on-reset of a circuit or system, where the power-on-reset resets the circuit or system if the voltage input signal drops below the threshold voltage, for example.

The input power supply voltage level detection circuit embodiments described above provide a number of advantages. One advantage is that the circuit keeps the threshold voltage substantially constant over process and temperature variations. Another advantage is that the circuit keeps its power consumption as low as possible, which can be important when current consumption concerns are critical. A further advantage is that a startup circuit is not required.