Chip stacking structure and fabricating method of the chip stacking structure

A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 101118718, filed on May 25, 2012. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

TECHNICAL FIELD

The disclosure relates to a chip stacking structure and a fabricating process of the chip stacking; more specifically, the disclosure relates to a three-dimensional chip stacking structure and a fabricating process of the three-dimensional chip stacking.

BACKGROUND

In recent years, the electronic industry develops and prospers under the guidance of Moore's Law. However, with the needs such as enhancing the computing speed of electronic products, the techniques run into bottlenecks. Three-dimensional integrated circuit integration (3D IC integration) techniques has become one of answers to the current issue that the performance of the electronic products has to meet the needs.

Compared with conventional package techniques, 3D IC integration techniques have many advantages. For example, sizes of devices are smaller, signal loss is reduced, and electrical properties perform better, all of which are due to the utilization of a through silicon via (TSV).

The TSV has become one of the important cores in 3D IC integration techniques, and the fabrication costs of the TSV have to be considered carefully. In a three-dimensional integrated circuit system in package (3D IC SiP) structure having a typical TSV interposer, the TSV interposer carries chips above and below by utilizing microbump structures, and connects to a substrate or a printed circuit board (PCB) via a solder bump structure.

Usually, five steps are required to fabricate a TSV structure:

First step, laser drilling process or deep reactive ion etch (DRIE) process are utilized to form a via.

Second step, a plasma enhanced chemical vapor deposition (PECVD) method is utilized to deposit a dielectric deposition.

Third step, a physical vapor deposition (PVD) method is utilized to deposit a barrier/electroplating seed layer.

Fourth step, copper electroplating is utilized to fill the via (via Cu-filling).

Fifth step, a chemical and mechanical polishing (CMP) process is utilized to remove protruding or extra material.

Fabrication costs for the aforementioned five steps are listed from high to low as: PVD>PECVD>CMP>Electroplating>Etching.

More specifically, the 3D IC integration technique is one of the most effective structures for enhancing performance of electrical products, allows a plurality of chips to interconnect with one another and integrates more computing capability, memory, and other functions in a very small apparatus. However, the conventional 3D IC integration utilizing a TSV requires the use of processes such as PVD and PECVD. As a result, a technical limitation exists as an aspect ratio is hardly improved (a via cannot be completely filled with copper). Moreover, fabrication costs of a TSV is very high due to issues like costly vacuuming, dry process equipment and consumption materials.

Accordingly, it is urgent and requires solutions for solving an issue of high costs in making through silicon via (TSV) in terms of solving a technical problem of 3D IC integration.

SUMMARY

In one embodiment, the chip stacking structure includes a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor. The carrier has a first surface and a second surface opposite to each other, and the carrier has at least one through hole. The first redistribution layer is disposed on the first surface of the carrier. The second redistribution layer is disposed on the second surface of the carrier. The first chip is disposed on the first surface of the carrier and electrically connected with the first redistribution layer. The second chip is disposed on the second surface of the carrier and electrically connected with the second redistribution layer. The conductor is disposed on one of the first chip and the second chip, and the conductor is disposed in the through hole, and the first chip and the second chip are electrically connected by the conductor, wherein a gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.

In another embodiment, the fabricating method of the chip stacking structure is providing a carrier having a first surface and a second surface opposite to each other, wherein the carrier has at least one through hole, and a first redistribution layer is disposed on the first surface of the carrier, and a second redistribution layer is disposed on the second surface of the carrier; providing at least one first chip facing the first surface of the carrier; providing at least one second chip facing the second surface of the carrier, wherein at least one conductor is disposed on one of the first chip and the second chip; and having the conductor pass through a through hole and electrically connect the first chip and the second chip, wherein a gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.

In order to make the aforementioned features and advantages of the disclosure more comprehensible, embodiments accompanying figures are described in detail below.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

FIG. 1is a schematic view of a chip stacking structure according to an embodiment of the disclosure. Referring toFIG. 1, a chip stacking structure100includes a carrier110, a first redistribution layer120, a second redistribution layer130, at least one first chip140, at least one second chip150, and at least one conductor160. The carrier110has a first surface112and a second surface114opposite to each other. The carrier110has at least one through hole H. The first redistribution layer120is disposed on the first surface112of the carrier110. The second redistribution layer130is disposed on the second surface114of the carrier110. The first chip140is disposed on the first surface112of the carrier110and electrically connected with the first redistribution layer120. The second chip150is disposed on the second surface114of the carrier110and electrically connected with the second redistribution layer130. The conductor160is disposed on one of the first chip140and the second chip150. The conductor160is disposed in the through hole H, and the first chip140and the second chip150are electronically connected by the conductor160, wherein a gap D is formed between the conductor160and an inner wall of the carrier110which surrounds the through hole H.

That “the conductor160is disposed on one of the first chip140and the second chip150” indicates that the conductor160may be fabricated together with the first chip140, or that the conductor160may be fabricated together with the second chip150. The conductor160may be a conductive wire, a conductive pillar, or a conductive pad, suitable for passing through the through hole H of the carrier110. In addition, the conductor160may be selected from Au, Cu, Ni, Ag, and combinations thereof. Later, inFIG. 5AtoFIG. 5H, a process of fabricating the conductor160on the first chip140or on the second chip150will be described in details.

Referring toFIG. 1, the first chip140and the second chip150are electrically connected to each other via the conductor160which is disposed in the through hole H, and the gap D is formed between the conductor160and the inner wall of the carrier110which surrounds the through hole H. More specifically, a metallization process is not performed in the through hole H of the chip stacking structure100.

Furthermore, the gap D may be filled with air or inert gas. When the gap D is filled with inert gas, the conductor160is not prone to be oxidized, and an operation of the chip stacking structure100remains smooth. In addition, the gap D may be filled with an insulating filler to enhance a structural strength of the chip stacking structure100.

FIG. 2Ais a partially enlarged schematic view of the first chip ofFIG. 1. Referring toFIG. 1andFIG. 2Atogether, the first chip140may includes a first substrate142, a first circuit layer144, a first patterned insulating layer146, and a first microbump148. The first circuit layer144is disposed on the first substrate142. The first patterned insulating layer146covers the first circuit layer144, and the first patterned insulating layer146exposes a part of the first circuit layer144. The first microbump148is disposed in contact with the exposed first circuit layer144. The conductor160may be connected with the first microbump148.

Referring toFIG. 2Aagain, the first substrate142may be a silicon wafer, including a silicon substrate142aand a silicon oxide layer142b. And the first microbump148may include a plurality of film layers148a,148b, and148cbeing stacked. For example, the film layer148ais a TiW film layer, the film layer148bis a Cu film layer, and the film layer148cis a Ni film layer.

FIG. 2Bis a partially enlarged schematic view of the second chip ofFIG. 1. Referring toFIG. 1andFIG. 2Btogether, the second chip150may includes a second substrate152, a second circuit layer154, a second patterned insulating layer156, and a second microbump158. The second circuit layer154is disposed on the second substrate152. The second patterned insulating layer156covers the second circuit layer154, and the second patterned insulating layer156exposes a part of the second circuit layer154. The second microbump158is disposed in contact with the exposed second circuit layer154.

Referring toFIG. 2Bagain, the second substrate152may be a silicon wafer, including a silicon substrate152aand a silicon oxide layer152b. And the second microbump158may include a plurality of film layers158a,158b, and158cbeing stacked. For example, the film layer158ais a TiW film layer, the film layer158bis a Cu film layer, and the film layer158cis a Ni film layer.

In the embodiment illustrated inFIG. 2AandFIG. 2B, the conductor160is fabricated on the first chip140, but not on the second chip150. However, various embodiments are also applicable; i.e. the conductor160is fabricated on the second chip150, but not on the first chip140, or the conductor160is fabricated on both the first chip140and the second chip150but in a way of a staggered arrangement. Regardless of ways of fabricating the conductor160, the ultimate goal is to insert the conductor160properly into the through hole H so as to assemble the carrier110, the first chip140, and the second chip150.

Referring toFIG. 1again, the first microbump148may also be connected between the first chip140and the first redistribution layer120, so that a plurality of the first chips140may be electrically connected with one another via the first redistribution layer120and transmit electrical signals. The first microbump148allows the first chip140to steadily bond to the first surface112of the carrier110so as to enhance the structural strength of the chip stacking structure100.

Similarly, the second microbump158may be connected between the second chip150and the second redistribution layer130, so that a plurality of the second chips150may be electrically connected with one another via the second redistribution layer130and transmit electrical signals. The second microbump158allows the second chip150to steadily bond to the second surface114of the carrier110so as to enhance the structural strength of the chip stacking structure100.

Referring toFIG. 1, the chip stacking structure100further includes a carrier board170and a solder ball180. The carrier board170has a third redistribution layer172. The carrier board170may be a printed circuit board (PCB) having a circuit pattern thereon. The solder ball180is disposed between the second redistribution layer130and the third redistribution layer172.

Accordingly, the chip stacking structure100has a simple structure which can replace an expensive conventional through silicon via (TSV) by using the through hole H with the conductor160. Since the through hole H on the carrier110does not require additional metallization process, fabrication costs of the chip stacking structure100may be reduced effectively.

FIG. 3AandFIG. 3Bare schematic views of a fabricating method of a chip stacking structure of the disclosure. Referring toFIG. 1andFIG. 3AtoFIG. 3Btogether, a fabricating method of the chip stacking structure may include following steps, and orders of steps may be properly modified by people having ordinary skill in the art. In addition, the same elements are indicated with the same numbers.

As shown inFIG. 2andFIG. 3A, the carrier110is provided, having the first surface112and the second surface114opposite to each other. The carrier110has the at least one through hole H, and the first redistribution layer120is disposed on the first surface112of the carrier110. The second redistribution layer130is disposed on the second surface114of the carrier110.

As shown inFIG. 2andFIG. 3B, the at least one first chip140is provided, which faces the first surface112of the carrier110; and the at least one second chip150is provided, which faces the second surface114of the carrier110, wherein the at least one conductor160is disposed on one of the first chip140and the second chip150. In this embodiment, the first chip140has the conductor160.

As shown with arrows inFIG. 3B, the conductor160passes through the through hole H and electrically connects the first chip140and the second chip150, wherein the gap D is formed between the conductor160and the inner wall of the carrier110which surrounds the through hole H.

Positioning marks and a positioning apparatus may be utilized to ensure that the conductor160is aligned precisely to the through hole H, so that the carrier110, the first chip140, and the second chip150are assembled together to fabricate the chip stacking structure100. Detailed implementation forms of each component of the chip stacking structure100are described as the aforementioned, and will not be repeated herein.

Referring toFIG. 2andFIG. 3B, a method of forming the through hole H may be laser drilling method or ion etching method. When ion etching method is utilized, a deep reactive ion etch (DRIE) process may be utilized. The chip stacking structure100is to form the through hole H on the carrier110, and does not require to electroplate a depositing conductive layer in the through hole H as a conventional TSV does.

FIG. 4AtoFIG. 4Gshow schematic fabrication flowcharts of a carrier according to an embodiment of the disclosure. Referring toFIG. 4AtoFIG. 4Ga method of providing the carrier110includes following steps.

First, as shown inFIG. 4A, a carrier wafer110A is provided, having a first surface112and a second surface114opposite to each other, and a non-through hole UH having a pre-determined depth is formed on the first surface112of the carrier wafer110A. The laser drilling method or the deep reactive ion etch (DRIE) may be utilized to perform a fabrication of the non-through hole UH.

Then, as shown inFIG. 4B, the first redistribution layer120is formed on the first surface112. A method of forming the first redistribution layer120may be utilizing a physical sputtering process to deposit metals, and then forming the first redistribution layer120having patterned circuits utilizing a lithography etching method. In addition, when the first redistribution layer120is formed on the first surface112, the first microbump148may also be formed on the first surface112. The first microbump148(as illustrated inFIG. 1andFIG. 2A) is connected with the first redistribution layer120.

Next, as shown inFIG. 4C, a support wafer SW is provided, which bonds to the first surface112of the carrier wafer110A and supports the carrier wafer110A.

Then, as shown inFIG. 4D, a thickness of the carrier wafer110A is removed partially (as marked with the dotted lines) from the second surface114of the carrier wafer110A, so that the non-through hole UH is exposed from the second surface114to form the through hole H. The step may be performed utilizing a chemical mechanical polishing.

Next, as shown inFIG. 4D, the second redistribution layer130is formed on the second surface114. A method of forming the second redistribution layer130may be utilizing a physical sputtering process to deposit metals, and then forming the second redistribution layer130having patterned circuits utilizing a lithography etching method. In addition, when the second redistribution layer130is formed on the second surface114, the second microbump158may also be formed on the second surface114(as illustrated inFIG. 1andFIG. 2B). The second microbump158is connected with the second redistribution layer130.

Then, as shown inFIG. 4E, a solder ball180is provided and connected with the second redistribution layer130.

Next, as shown inFIG. 4F, the carrier wafer110A is disposed on a dicing tape T via the solder ball180, and the support wafer SW is removed.

Later, as shown inFIG. 4G, the carrier wafer110A is diced (as shown with the dotted lines for dicing inFIG. 4G) and forms the carrier110having the at least one through hole H.

The aforementioned is an example of a fabricating process of providing the carrier110. Any proper modification to the design made by people having ordinary skill in the art by referring to the aforementioned descriptions of the disclosure is within the scope of the claims of the disclosure.

FIG. 5AtoFIG. 5Hshow schematic fabrication flowcharts of a first chip or a second chip having a conductor. To understand related fabricating processes, please refer toFIG. 1,FIG. 2AtoFIG. 2B, andFIG. 5AtoFIG. 5I. The conductor160may be fabricated on the first chip140, or the conductor160may be fabricated on the second chip150, or the conductor160may be fabricated on both the first chip140and the second chip150, as long as the carrier110, the first chip140, and the second chip150may be assembled.

A fabricating method related to one of the first chip140and the second chip150may includes following steps.

First, as shown inFIG. 5A, a wafer200is provided. The wafer200goes through a cleaning process to facilitate a subsequent lithography etching process and an electroplating process.

Next, as shown inFIG. 5B, an electroplating seed layer210is formed on the wafer200, which may be formed by utilizing a physical sputtering method. A material of the electroplating seed layer210may be Cu.

Then, as shown inFIG. 5C, a patterned photoresist layer230is formed and covers the electroplating seed layer210, and the patterned photoresist layer230has an opening232that exposes the electroplating seed layer210.

Then, as shown inFIG. 5D, the electroplating process is performed to form the conductor160. The conductor160is connected with the exposed electroplating seed layer210. The conductor160includes a solder joint layer160aand a copper layer160b.

Next, as shown inFIG. 5E, the patterned photoresist layer230is removed. Also as shown inFIG. 5F, a reflow process may also be performed to the solder joint layer160aand forms the solder joint layer160ainto a smooth shape.

Then, as shown inFIG. 5G, a plurality of the conductors160formed on the wafer200are illustrated. A plurality of the first chips140or the second chips150are formed on the wafer200. As shown inFIG. 5H, the wafer200is diced to form the first chips140having the conductors160or the second chips150having the conductors160.

Later, the carrier110, the first chips140, and the second chips150may be assembled to form the chip stacking structure100.

In conclusion, the chip stacking structure of the disclosure has a simple structure that may replace the expensive conventional TSV by using the through hole with the conductor. Since the through hole on the carrier does not require additional metallization process, fabrication costs of the chip stacking structure may be reduced effectively.

Although the disclosure has been disclosed by the above embodiments, they are not intended to limit the disclosure. It will be apparent to those of ordinary skill in the art that modifications and variations to the disclosure may be made without departing from the spirit and scope of the disclosure. In view of the foregoing, the protection scope of this disclosure falls within the appended claims.