Stage and emission control driver having the same

Provided herein may be a stage and an emission control driver having the same. The stage may include an output unit configured to supply a voltage of a first or second power supply to a first output terminal depending on voltages of first and second nodes, an input unit configured to control the voltages of the second node and a third node, a first signal processing unit configured to control the voltage of the first node, and supply a voltage corresponding to the first node to a second output terminal, a second signal processing unit including a second capacitor coupled between the third node and a fifth node, the second signal processing unit being configured to control the voltage of the first node, and control a potential difference between opposite terminals of the second capacitor, and a third signal processing unit configured to control the voltage of the second node.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to, and the benefit of, Korean patent application number 10-2018-0138314 filed on Nov. 12, 2018, the entire disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Various embodiments of the present disclosure relate to a stage, and an emission control driver having the same.

2. Description of Related Art

An organic light emitting display (OLED) has advantages in that the response speed thereof is high, and in that it is operated with low power consumption.

An emission control driver provided in the OLED may control emission times of pixels by supplying emission control signals to emission control lines. For this operation, the emission control driver includes a plurality of stages coupled to the respective emission control lines.

Each of the stages may include a plurality of transistors and a capacitor. Frequent charge and discharge operations of the capacitors provided in the stages may increase power consumption of the OLED that is operated with low power.

SUMMARY

Various embodiments of the present disclosure are directed to a stage configured such that a capacitor provided in the stage may be prevented from being charged or discharged while an emission control signal is maintained at a low voltage, and an emission control driver having the stage.

An embodiment of the present disclosure may provide a stage including an output unit configured to supply a voltage of a first power supply or a voltage of a second power supply to a first output terminal depending on a voltage of a first node and on a voltage of a second node, an input unit configured to control the voltage of the second node and a voltage of a third node in response to signals supplied to a first input terminal, a second input terminal, and a fourth input terminal, a first signal processing unit configured to control the voltage of the first node in response to the voltage of the second node, and to supply a voltage corresponding to the first node to a second output terminal, a second signal processing unit including a second capacitor coupled between the third node and a fifth node, the second signal processing unit being configured to control the voltage of the first node in response to the signal supplied to the second input terminal and to a signal supplied to a third input terminal, and being configured to control a potential difference between opposite terminals of the second capacitor in response to the signal supplied to the second input terminal and the voltage of the first power supply, and a third signal processing unit configured to control the voltage of the second node in response to the voltage of the first power supply and the signal supplied to the fourth input terminal.

The first power supply may be set to a gate-off voltage, and the second power supply may be set to a gate-on voltage.

The signal supplied to the first input terminal may include a start signal or a signal output from the first output terminal of a preceding stage, and the signal supplied to the fourth input terminal may include a control node start signal or a signal output from the second output terminal of the preceding stage.

The signal output from the first output terminal of the preceding stage or the start signal may overlap at least once with a first clock signal including the signal supplied to the second input terminal.

The signal output from the second output terminal of the preceding stage or the control node start signal may have a phase that is inverted from a phase of the signal output from the first output terminal of the preceding stage or the start signal.

The signal supplied to the second input terminal may include a first clock signal, and the signal supplied to the third input terminal may include a second clock signal.

The input unit may include a first transistor coupled between the first input terminal and the second node, and including a gate electrode coupled to the second input terminal, and a fourth transistor coupled between the fourth input terminal and the third node, and including a gate electrode coupled to the second input terminal.

The output unit may include a ninth transistor coupled between the first power supply and the first output terminal, and including a gate electrode coupled to the first node, and a tenth transistor coupled between the first output terminal and the second power supply, and including a gate electrode coupled to the second node.

The first signal processing unit may include an eighth transistor coupled between the first power supply and the first node, and including a gate electrode coupled to the second node, and a first capacitor coupled between the first power supply and the first node.

The second signal processing unit may include a fifth transistor coupled between the first power supply and the fifth node, and including a gate electrode coupled to the second input terminal, a sixth transistor coupled between the fifth node and the third input terminal, and including a gate electrode coupled to the third node, and a seventh transistor coupled between the fifth node and the first node, and including a gate electrode coupled to the third input terminal.

While the voltage of the second power supply is supplied to the first output terminal, the potential difference between the opposite terminals of the second capacitor may remain constant.

The third signal processing unit may include a second transistor coupled between the first power supply and a seventh node, and including a gate electrode coupled to the third node, a third transistor coupled between the seventh node and the third input terminal, and including a gate electrode coupled to the second node, and a third capacitor coupled between the seventh node and the second node.

The stage may further include a first stabilization unit coupled between the second signal processing unit and the third signal processing unit, and configured to control a voltage drop width of the third node, and a second stabilization unit coupled between the second node and a fourth node coupled to the first input terminal, the second stabilization unit being configured to control a voltage drop width of the second node.

The first stabilization unit may include an eleventh transistor coupled between the third signal processing unit and the third node, and including a gate electrode coupled to the second power supply.

The second stabilization unit may include a twelfth transistor coupled between the second node and the fourth node, and including a gate electrode coupled to the second power supply.

The input unit may include a first transistor coupled between the first input terminal and the second node, and including a gate electrode coupled to the second input terminal, a fourth transistor coupled between an eighth node and the third node, a sixteenth transistor coupled between the first power supply and the eighth node, and including a gate electrode coupled to the first input terminal, and a seventeenth transistor coupled between the eighth node and the second power supply, and including a gate electrode coupled to the first input terminal, and the fourth input terminal may be coupled to the first input terminal.

The second signal processing unit may include a fifth transistor coupled between the third input terminal and the fifth node, and including a gate electrode coupled to the second input terminal, a sixth transistor coupled between the fifth node and the third input terminal, and including a gate electrode coupled to the third node, and a seventh transistor coupled between the fifth node and the first node, and including a gate electrode coupled to the third input terminal.

The third signal processing unit may include a third capacitor coupled between the sixth node and a seventh node, and is configured to control a potential difference between opposite terminals of the third capacitor in response to the first power supply and the signals supplied to the first input terminal, the second input terminal, and the fourth input terminal.

The third signal processing unit may further include a second transistor coupled between the first power supply and the seventh node, and including a gate electrode coupled to the third node, a third transistor coupled between the seventh node and the third input terminal, and including a gate electrode coupled to the sixth node, and a fifteenth transistor coupled between the sixth node and the second node, and including a gate electrode coupled to the sixth node.

The input unit may include a first transistor coupled between the first input terminal and the second node, and including a gate electrode coupled to the second input terminal, a fourth transistor coupled between the fourth input terminal and the third node, and including a gate electrode coupled to the second input terminal, and a thirteenth transistor coupled between the first input terminal and the sixth node, and including a gate electrode coupled to the second input terminal.

While the voltage of the second power supply is supplied to the first output terminal, the potential difference between the opposite terminals of the third capacitor may remain constant.

The stage may further include a first stabilization unit coupled between the second signal processing unit and the third signal processing unit, and configured to control a voltage drop width of the third node, a second stabilization unit coupled between the second node and a fourth node that is coupled to the first input terminal, and configured to control a voltage drop width of the fourth node, and a third stabilization unit coupled between the input unit and the third signal processing unit, and configured to control a voltage drop width of the sixth node.

The input unit may include a first transistor coupled between the first input terminal and the second node, and including a gate electrode coupled to the second input terminal, a fourth transistor coupled between an eighth node and the third node, a thirteenth transistor coupled between the first input terminal and the sixth node, and including a gate electrode coupled to the second input terminal, a sixteenth transistor coupled between the first power supply and the eighth node, and including a gate electrode coupled to the first input terminal, and a seventeenth transistor coupled between the eighth node and the second power supply, and including a gate electrode coupled to the first input terminal, and the fourth input terminal may be coupled to the first input terminal.

An embodiment of the present disclosure may provide an emission control driver including a plurality of stages to supply emission signals to emission control lines. Each of the plurality of stages may include an output unit configured to supply a voltage of a first power supply or a second power supply to a first output terminal depending on voltages of a first node and a second node, an input unit configured to control the voltage of the second node and a voltage of a third node in response to signals supplied to a first input terminal, a second input terminal, and a fourth input terminal, a first signal processing unit configured to control the voltage of the first node in response to the voltage of the second node, and to supply a voltage corresponding to the first node to a second output terminal, a second signal processing unit including a second capacitor coupled between the third node and a fifth node, the second signal processing unit being configured to control the voltage of the first node in response to the signal supplied to the second input terminal and a signal supplied to a third input terminal, and to control a potential difference between opposite terminals of the second capacitor in response to the signal supplied to the second input terminal and the first power supply, and a third signal processing unit configured to control the voltage of the second node in response to the signal supplied to the first input terminal and the signal supplied to the fourth input terminal.

A 1st stage of the plurality of stages may include a 1st output unit configured to supply the voltage of the first power supply or the second power supply to a 1st first-output terminal depending on voltages of a 1st first-node and a 1st second-node, a 1st input unit configured to control the voltage of the 1st second-node and a voltage of a 1st third-node in response to a signal supplied to a 1st first-input terminal and a signal supplied to a 1st second-input terminal, a 1st first-signal processing unit configured to control the voltage of the 1st first-node in response to the voltage of the 1st second-node, and to supply a voltage corresponding to the 1st first-node to a 1st second-output terminal, a 1st second-signal processing unit coupled to the 1st third-node and configured to control the voltage of the 1st first-node in response to the signal supplied to the 1st second input terminal and the signal supplied to a 1st third input terminal, and a 1st third-signal processing unit configured to control the voltage of the 1st second-node in response to the signal supplied to the 1st first-input terminal.

A signal output from the 1st second-output terminal may be supplied to the fourth input terminal of a 2nd stage.

The first input terminal may be supplied with a signal output from the first output terminal of a preceding stage or a start signal, and the fourth input terminal may be supplied with a signal output from the second output terminal of the preceding stage or a control node start signal.

The signal output from the first output terminal of the preceding stage or the start signal may overlap at least once with a first clock signal supplied to the second input terminal, and the signal output from the second output terminal of the preceding stage or the control node start signal may include a signal having a phase that is inverted from a phase of the signal output from the first output terminal of the preceding stage or the start signal.

The input unit may include a first transistor coupled between the first input terminal and the second node, and including a gate electrode coupled to the second input terminal, and a fourth transistor coupled between the fourth input terminal and the third node, and including a gate electrode coupled to the second input terminal.

The output unit may include a ninth transistor coupled between the first power supply and the first output terminal, and including a gate electrode coupled to the first node, and a tenth transistor coupled between the first output terminal and the second power supply, and including a gate electrode coupled to the second node.

The first signal processing unit may include an eighth transistor coupled between the first power supply and the first node, and including a gate electrode coupled to the second node, and a first capacitor coupled between the first power supply and the first node.

The second signal processing unit may include a fifth transistor coupled between the first power supply and the fifth node, and including a gate electrode coupled to the second input terminal, a sixth transistor coupled between the fifth node and the third input terminal, and including a gate electrode coupled to the third node, and a seventh transistor coupled between the fifth node and the first node, and including a gate electrode coupled to the third input terminal.

While the voltage of the second power supply is supplied to the first output terminal, the potential difference between the opposite terminals of the second capacitor may remain constant.

The third signal processing unit may include a second transistor coupled between the first power supply and a seventh node, and including a gate electrode coupled to the third node, a third transistor coupled between the seventh node and the third input terminal, and including a gate electrode coupled to the second node, and a third capacitor coupled between the seventh node and the second node.

The emission control driver may further include a first stabilization unit coupled between the second signal processing unit and the third signal processing unit, and configured to control a voltage drop width of the third node, and a second stabilization unit coupled between the second node and a fourth node that is coupled to the first input terminal, the second stabilization unit being configured to control a voltage drop width of the second node.

The first stabilization unit may include an eleventh transistor coupled between the third signal processing unit and the third node, and including a gate electrode coupled to the second power supply, and the second stabilization unit may include a twelfth transistor coupled between the second node and the fourth node, and including a gate electrode coupled to the second power supply.

The input unit may include a first transistor coupled between the first input terminal and the second node, and including a gate electrode coupled to the second input terminal, a fourth transistor coupled between an eighth node and the third node, a sixteenth transistor coupled between the first power supply and the eighth node, and including a gate electrode coupled to the first input terminal, and a seventeenth transistor coupled between the eighth node and the second power supply, and including a gate electrode coupled to the first input terminal, and wherein the fourth input terminal is coupled to the first input terminal.

The second signal processing unit may include a fifth transistor coupled between the third input terminal and the fifth node, and including a gate electrode coupled to the second input terminal, a sixth transistor coupled between the fifth node and the third input terminal, and including a gate electrode coupled to the third node, and a seventh transistor coupled between the fifth node and the first node, and including a gate electrode coupled to the third input terminal.

The third signal processing unit may include a third capacitor coupled between a sixth node and a seventh node, and controls a potential difference between opposite terminals of the third capacitor in response to the first power supply and the signals supplied to the first input terminal, the second input terminal, and the fourth input terminal.

The third signal processing unit may further include a second transistor coupled between the first power supply and the seventh node, and including a gate electrode coupled to the third node, a third transistor coupled between the seventh node and the third input terminal, and including a gate electrode coupled to the sixth node, and a fifteenth transistor coupled between the sixth node and the second node, and including a gate electrode coupled to the sixth node.

The input unit may include a first transistor coupled between the first input terminal and the second node, and including a gate electrode coupled to the second input terminal, a fourth transistor coupled between the fourth input terminal and the third node, and including a gate electrode coupled to the second input terminal, and a thirteenth transistor coupled between the first input terminal and the sixth node, and including a gate electrode coupled to the second input terminal.

While the voltage of the second power supply is supplied to the first output terminal, the potential difference between the opposite terminals of the third capacitor may remain constant.

The emission control driver may further include a first stabilization unit coupled between the second signal processing unit and the third signal processing unit and configured to control a voltage drop width of the third node, a second stabilization unit coupled between the second node and a fourth node that is coupled to the first input terminal, the second stabilization unit being configured to control a voltage drop width of the fourth node, and a third stabilization unit coupled between the input unit and the third signal processing unit, and configured to control a voltage drop width of the sixth node.

The input unit may include a first transistor coupled between the first input terminal and the second node, and including a gate electrode coupled to the second input terminal, a fourth transistor coupled between an eighth node and the third node, a thirteenth transistor coupled between the first input terminal and the sixth node, and including a gate electrode coupled to the second input terminal, a sixteenth transistor coupled between the first power supply and the eighth node, and including a gate electrode coupled to the first input terminal, and a seventeenth transistor coupled between the eighth node and the second power supply, and including a gate electrode coupled to the first input terminal, and the fourth input terminal may be coupled to the first input terminal.

DETAILED DESCRIPTION

Various embodiments are described herein with reference to sectional illustrations that are schematic illustrations of embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Further, specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. Thus, embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting. Additionally, as those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

It will be understood that when an element, layer, region, or component is referred to as being “on,” “connected to,” or “coupled to” another element, layer, region, or component, it can be directly on, connected to, or coupled to the other element, layer, region, or component, or one or more intervening elements, layers, regions, or components may be present. However, “directly connected/directly coupled” refers to one component directly connecting or coupling another component without an intermediate component. Meanwhile, other expressions describing relationships between components such as “between,” “immediately between” or “adjacent to” and “directly adjacent to” may be construed similarly. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

FIG. 1is a diagram illustrating a display device in accordance with embodiments of the present disclosure.

Referring toFIG. 1, a display device in accordance with an embodiment of the present disclosure may include a display unit10, a scan driver20, a data driver30, an emission control driver40, and a timing controller50.

The display unit10may include a plurality of pixels PX that are coupled with scan lines S1to Sn, data lines D1to Dm, and emission control lines E1to En, and that are arranged in the form of a matrix. The pixels PX may receive scan signals through the scan lines S1to Sn, may receive data signals through the data lines D1to Dm, and may receive emission control signals through the emission control lines E1to En. The pixels PX may emit light at luminances corresponding to data signals supplied from the data lines D1to Dm when scan signals are supplied from the scan lines S1to Sn to the pixels PX.

The scan driver20may be coupled with the plurality of scan lines S1to Sn, may generate scan signals in response to a scan driving control signal SCS from the timing controller50, and may output the generated scan signals to the scan lines S1to Sn. The scan driver20may be formed of a plurality of stage circuits. When scan signals are sequentially supplied to the scan lines S1to Sn, the pixels PX may be selected on a horizontal line basis (e.g., on a line-by-line basis).

The data driver30may be coupled to the plurality of data lines D1to Dm, may generate data signals based on compensated image data DATA′ and a data driving control signal DCS from the timing controller50, and may output the generated data signals to the data lines D1to Dm. Each time a scan signal is supplied, the data signals supplied to the data lines D1to Dm may be supplied to pixels PX selected by the scan signal. Then, the pixels PX may charge voltages corresponding to the data signals.

The emission control driver40may be coupled with the emission control lines E1to En, may generate emission control signals in response to an emission driving control signal ECS from the timing controller50, and may output the generated emission control signal to the emission control lines E1to En. The emission control driver40may be formed of a plurality of stage circuits, and may control emission periods of the pixels PX by supplying the emission control signals to the emission control lines E1to En.

The timing controller50may receive image data DATA, synchronization signals Hsync and Vsync, a clock signal CLK, etc. for controlling display of an image corresponding to the image data DATA. The timing controller50may image-process the input image data DATA, may generate compensated image data DATA′ suitable for image display of the display unit10, and may output the compensated image data DATA′ to the data driver30. The timing controller50may generate driving control signals SCS, DCS, and ECS for controlling the operations of the scan driver20, the data driver30, and the emission control driver40based on the synchronization signals Hsync and Vsync and the clock signal CLK. In detail, the timing controller50may generate a scan driving control signal SCS to supply the scan driving control signal SCS to the scan driver20, may generate a data driving control signal DCS to supply the data driving control signal DCS to the data driver30, and may generate an emission driving control signal ECS to supply the emission driving control signal ECS to the emission control driver40.

Referring toFIG. 2, the emission control driver40in accordance with an embodiment of the present disclosure may include a plurality of stages401,402,403, . . . to supply emission control signals to the emission control lines E1to En. In the present embodiment, for the sake of explanation, only three stages401,402, and403are illustrated.

The stages401,402, and403may be driven by a start signal FLM and first and second clock signals CLK1and CLK2, and may respectively output emission control signals EM1, EM2, and EM3. The emission driving control signal ECS provided from the timing controller50may include the start signal FLM and the first and second clock signals CLK1and CLK2. Here, the stages401,402, and403may be implemented as the same circuit.

Each of the stages401to403includes a first input terminal101, a second input terminal102, a third input terminal103, and a first output terminal104.

The first input terminal101may be supplied with a start signal FLM or an emission control signal EM[i−1] of the preceding stage. The second input terminal102and the third input terminal103may be supplied with any one of the first and second clock signals CLK1and CLK2. A signal output to the first output terminal104may be used as an emission control signal EM.

The first stage401of the stages401,402, and403may receive the start signal FLM, and each of the stages402and403other than the first stage401may receive the respective emission control signal EM1, EM2, EM3of the preceding stage. Furthermore, the first stage401may directly receive the first and second clock signals CLK1and CLK2, and each of the stages402and403other than the first stage401may receive any one of the first and second clock signals CLK1and CLK2from the preceding stage. In detail, the third stage403, which is an odd-numbered stage other than the first stage401, may receive the first clock signal CLK1from the preceding stage, and may directly receive the second clock signal CLK2. The second stage402, which is an even-numbered stage, may directly receive the first clock signal CLK1, and may receive the second clock signal CLK2from the preceding stage.

In an embodiment of the present disclosure, the stages401,402, and403may be driven by a control node start signal FQB, and may output respective control node signals QB. The emission driving control signal ECS provided from the timing controller50may include the control node start signal FQB.

In this embodiment, each of the stages401,402, and403may further include a fourth input terminal105and a second output terminal106. The fourth input terminal105may be supplied with the control node signal QB or the control node start signal FQB of the preceding stage. The second output terminal106may output the control node signal QB. The control node signal QB output from the second output terminal106may be supplied to the fourth input terminal105of the following/subsequent stage.

The first stage401of the stages401,402, and403may receive the control node start signal FQB, and each of the stages402and403other than the first stage401may receive the control node signal QB of the preceding stage.

The first stage401may output a first emission control signal EM1in response to the start signal FLM, the control node start signal FQB, and the first and second clock signals CLK1and CLK2, and may transmit the second clock signal CLK2, the first emission control signal EM1, and a first control node signal QB1to the second stage402.

The second stage402may output a second emission control signal EM2in response to the first clock signal CLK1, and in response to the second clock signal CLK2, the first emission control signal EM1, and the first control node signal QB1that are transmitted from the first stage401, and may transmit the first clock signal CLK1, the second emission control signal EM2, and the second control node signal QB2to the third stage403.

The third stage403may output a third emission control signal EM3in response to the second clock signal CLK2, and in response to the first clock signal CLK1, the second emission control signal EM2, and the second control node signal QB2that are transmitted from the second stage402, and may transmit the second clock signal CLK2, the third emission control signal EM3, and the third control node signal QB3to a fourth stage.

However, in various embodiments of the present disclosure, the control node signal QB is not necessarily required. In other words, in an embodiment, the control node signal QB may be replaced with the emission control signal EM.

FIG. 3is a circuit diagram illustrating a stage illustrated inFIG. 2in accordance with a first embodiment of the present disclosure. AlthoughFIG. 3illustrates only an i-th stage for the sake of explanation, the stages illustrated inFIG. 2may have the same structure as that of the i-th stage to be described below.

Referring toFIG. 3, a stage400in accordance with the first embodiment of the present disclosure may include an input unit410, an output unit420, a first signal processing unit430, a second signal processing unit440, a third signal processing unit450, and first and second stabilization units461and462.

The output unit420may supply the voltage of a first power supply VDD or a second power supply VSS to a first output terminal104depending on voltages of a first node N1and a second node N2. To this end, the output unit420may include a ninth transistor M9and a tenth transistor M10.

The ninth transistor M9is coupled between the first power supply VDD and the first output terminal104. A gate electrode of the ninth transistor M9may be coupled to the first node N1. The ninth transistor M9may be turned on or off depending on the voltage of the first node N1. Here, the voltage of the first power supply VDD that is supplied to the first output terminal104when the ninth transistor M9is turned on may be used as an emission control signal EM[i] of an i-th emission control line Ei.

The tenth transistor M10is coupled between the first output terminal104and the second power supply VSS. A gate electrode of the tenth transistor M10is coupled to the second node N2. The tenth transistor M10may be turned on or off depending on the voltage of the second node N2.

The input unit410may control the voltages of the second node N2, a third node N3, and a fourth node N4in response to signals supplied to a first input terminal101, a second input terminal102, and a fourth input terminal105. To this end, the input unit410may include a first transistor M1and a fourth transistor M4.

The first transistor M1is coupled between the first input terminal101and the fourth node N4. A gate electrode of the first transistor M1is coupled to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the first transistor M1may be turned on to electrically couple the first input terminal101with the fourth node N4.

A first electrode of the fourth transistor M4is coupled to the fourth input terminal105, and a second electrode thereof is coupled to the third node N3via an eleventh transistor M11. A gate electrode of the fourth transistor M4is coupled to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the fourth transistor M4may be turned on to electrically couple the fourth input terminal105with the third node N3.

The first signal processing unit430may control the voltage of the first node N1in response to a voltage of the fourth node N4. The first signal processing unit430may supply the voltage of the first power supply VDD to the second output terminal106in response to the voltages of the first node N1and the fourth node N4. To this end, the first signal processing unit430may include an eighth transistor M8and a first capacitor C1.

The eighth transistor M8is coupled between the first power supply VDD and the first node N1. A gate electrode of the eighth transistor M8may be coupled to the fourth node N4. The eighth transistor M8may be turned on or off depending on the voltage of the fourth node N4. Here, the voltage of the first power supply VDD that is supplied to the second output terminal106when the eighth transistor M8is turned on may be used as a control node signal QB[i].

The first capacitor C1is coupled between the first power supply VDD and the first node N1. The first capacitor C1may charge a voltage to be applied to the first node N1. Furthermore, the first capacitor C1may stably maintain the voltage of the first node N1.

The second signal processing unit440is coupled to the third node N3, and may control the voltage of the first node N1in response to a signal input to the third input terminal103. To this end, the second signal processing unit440may include a seventh transistor M7, a sixth transistor M6, a fifth transistor M5, and a second capacitor C2.

A first terminal of the second capacitor C2is coupled to the third node N3, and a second terminal thereof is coupled to a fifth node N5.

The seventh transistor M7is coupled between the fifth node N5and the first node N1. A gate electrode of the seventh transistor M7is coupled to the third input terminal103. When the second clock signal CLK2is supplied to the third input terminal103, the seventh transistor M7may be turned on to electrically couple the fifth node N5with the first node N1.

The sixth transistor M6is coupled between the fifth node N5and the third input terminal103. A gate electrode of the sixth transistor M6is coupled to the third node N3. The sixth transistor M6may be turned on or off depending on the voltage of the third node N3.

The fifth transistor M5is coupled between the first power supply VDD and the fifth node N5. A gate electrode of the fifth transistor M5is coupled to the second input terminal102. The fifth transistor M5may be turned on or off in response to the first clock signal CLK1supplied to the second input terminal102.

The third signal processing unit450may control the voltage of the third second N2in response to the voltage of the first power supply VDD and the signal supplied to the fourth input terminal105. To this end, the third signal processing unit450may include a second transistor M2, a third transistor M3, and a third capacitor C3.

A first electrode of the third capacitor C3is coupled to a seventh node N7, and a second electrode thereof is coupled to a second node N2.

The second transistor M2is coupled between the first power supply VDD and the seventh node N7. A gate electrode of the second transistor M2is coupled to the third node N3. The second transistor M2may be turned on or off depending on the voltage of the third node N3.

The third transistor M3is coupled between the seventh node N7and the third input terminal103. A gate electrode of the third transistor M3is coupled to the second node N2. The third transistor M3may be turned on or off depending on the voltage of the second node N2.

The first stabilization unit461is coupled between the second signal processing unit440and the third signal processing unit450. The first stabilization unit461may limit a voltage drop width of the third node N3. To this end, the first stabilization unit461may include the eleventh transistor M11.

The eleventh transistor M11is coupled between the fourth input terminal105and the third node N3. A gate electrode of the eleventh transistor M11is coupled to the second power supply VSS. The eleventh transistor M11may be set to a turned-on state.

The second stabilization unit462is coupled between the fourth node N4and the second node N2. The second stabilization unit462may limit a voltage drop width of the second node N2. To this end, the second stabilization unit462may include a twelfth transistor M12.

The twelfth transistor M12is coupled between the second node N2and the fourth node N4. A gate electrode of the twelfth transistor M12is coupled to the second power supply VSS. The twelfth transistor M12may be set to a turned-on state.

FIG. 4is a waveform diagram illustrating an operation of the stage illustrated inFIG. 3. For the sake of explanation,FIG. 4illustrates the operation of only the i-th stage.

Referring toFIG. 4, each of the first clock signal CLK1and the second clock signal CLK2may have a cycle of two horizontal periods (2H), and the first clock signal CLK1and the second clock signal CLK2may be supplied in different horizontal periods. In other words, the second clock signal CLK2may be set to a signal shifted by a half cycle (e.g., one horizontal period (1H)) from the first clock signal CLK1.

When the clock signals CLK1and CLK2are supplied, the second input terminal102and the third input terminal103may be set to the voltage of the second power supply VSS. When the clock signals CLK1and CLK2are not supplied, the second input terminal102and the third input terminal103may be set to the voltage of the first power supply VDD.

When the start signal FLM (or the emission control signal EM) is supplied, the first input terminal101may be set to the voltage of the first power supply VDD. When the start signal FLM (or the emission control signal EM) is not supplied, the first input terminal101may be set to the voltage of the second power supply VSS.

Furthermore, the start signal FLM (or the emission control signal EM) to be supplied to the first input terminal101may be set to overlap at least once with the first clock signal CLK1to be supplied to the second input terminal102. To this end, the start signal FLM (or the emission control signal EM) may have a width greater than that of the first clock signal CLK1and, for example, may be supplied during four horizontal periods (4H). In this case, a first emission control signal to be supplied to the first input terminal101of the following stage may also overlap at least once with the second clock signal CLK2to be supplied to the second input terminal102of the following stage.

The control node start signal FQB (or the control node signal QB) may have a phase inverted from that of the start signal FLM (or the emission control signal EM). In other words, when the control node start signal FQB (or the control node signal QB) is supplied, the fourth input terminal105may be set to the voltage of the second power supply VSS. When the control node start signal FQB (or the control node signal QB) is not supplied, the fourth input terminal105may be set to the voltage of the first power supply VDD.

Furthermore, the control node start signal FQB (or the control node signal QB) to be supplied to the fourth input terminal105may be set to overlap at least once with the first clock signal CLK1to be supplied to the second input terminal102. To this end, the control node start signal FQB (or the control node signal QB) may have a width greater than that of the first clock signal CLK1and, for example, be supplied during four horizontal periods (4H). In this case, the control node signal QB to be supplied to the fourth input terminal105of the following stage may also overlap at least once with the second clock signal CLK2to be supplied to the second input terminal102of the following stage.

Furthermore, the control node start signal FQB (or the control node signal QB) to be supplied to the fourth input terminal105may be set to overlap with the emission control signal EM to be supplied to the first input terminal101.

A process of the operation will be described. First, at a first time t1, the first clock signal CLK1may be supplied to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the first transistor M1, the fourth transistor M4, and the fifth transistor M5may be turned on.

When the fifth transistor M5is turned on, the voltage of the first power supply VDD may be supplied to the fifth node N5. Thereby, the high voltage may be supplied to the second electrode of the second capacitor C2.

When the first transistor M1is turned on, the first input terminal101and the fourth node N4may be electrically coupled to each other. Here, because the twelfth transistor M12remains turned on, the first input terminal101may also be electrically coupled with the second node N2via the fourth node N4. Here, during the first time t1, the emission control signal EM[i−1] (or the start signal FLM) of the preceding stage may not be supplied to the first input terminal101, so that a low voltage (e.g., VSS) may be supplied to the fourth node N4and the second node N2. When the low voltage is supplied to the second node N2and the fourth node N4, the third transistor M3, the eighth transistor M8, and the tenth transistor M10may be turned on.

When the third transistor M3is turned on, the third input terminal103and the seventh node N7may be electrically coupled to each other. Because the second clock signal CLK2is not supplied to the third input terminal103at the first time t1, the high voltage may be supplied to the seventh node N7. However, the third capacitor C3may charge a voltage corresponding to the turned-on state of the third transistor M3.

When the eighth transistor M8is turned on, the voltage of the first power supply VDD may be supplied to the first node N1. Hence, the ninth transistor M9may be turned off. As the high voltage is supplied to the first node N1, the high voltage may be supplied to a second electrode of the first capacitor C1. Because a first electrode of the first capacitor C1is coupled with the first power supply VDD and thus has a high voltage, a potential difference between the opposite electrodes of the first capacitor C1may have a low level (e.g., may be small or minimal).

When the eighth transistor M8is turned on, the voltage of the first power supply VDD may be supplied to the second output terminal106. Hence, at the first time t1, the control node signal QB[i] is not supplied to the second output terminal106.

When the tenth transistor M10is turned on, the voltage of the second power supply VSS may be supplied to the first output terminal104. Therefore, during the first time t1, the emission control signal EM[i] may not be supplied to the emission control line Ei.

When the fourth transistor M4is turned on, the control node signal QB[i−1] (or the control node start signal FQB) of the preceding stage that is supplied to the fourth input terminal105may be supplied to the third node N3via the eleventh transistor M11that remains turned on. During the first time t1, the control node signal QB[i−1] of the preceding stage may not be supplied to the fourth input terminal105, so that the high voltage may be supplied to the third node N3. When the high voltage is supplied to the third node N3, the second transistor M2and the sixth transistor M6may be turned off. Furthermore, the high voltage may be supplied to a first electrode of the second capacitor C2coupled to the third node N3. Because the high voltage is supplied to the second electrode of the second capacitor C2, a potential difference between the opposite electrodes of the second capacitor C2may have a low level.

At a second time t2, the supply of the first clock signal CLK1to the second input terminal102may be interrupted. When the supply of the first clock signal CLK1is interrupted, the first transistor M1, the fourth transistor M4, and the fifth transistor M5may be turned off. Here, the first node N1and the second node N2may respectively maintain the voltages of the preceding period due to the first capacitor C1and the third capacitor C3(e.g., due to the respective potential difference between opposite terminals of the first and third capacitors C1and C3remaining constant). Because the first node N1remains in the high voltage state, the ninth transistor M9may remain turned off. Because the second node N2remains in the low voltage state, the third transistor M3, the eighth transistor M8, and the tenth transistor M10may remain turned on.

At the second time t2, the second clock signal CLK2may be supplied to the third input terminal103. When the second clock signal CLK2is supplied to the third input terminal103, the seventh transistor M7may be turned on.

When the seventh transistor M7is turned on, the first node N1and the fifth node N5may be electrically coupled to each other. Thereby, the fifth node N5may remain in the high voltage state, and the potential difference between the opposite electrodes of the second capacitor C2may be maintained at the low level.

As such, while the emission control signal EM[i] is not supplied to the emission control line Ei, the potential difference between the opposite electrodes of the second capacitor C2may be stably maintained. Hence, the capacitor C2may be prevented from being charged or discharged, and the power consumption may be consequently reduced.

At the second time t2, the low-level second clock signal CLK2may be supplied to the seventh node N7. Therefore, the low voltage is supplied to the seventh node N7. Then, the voltage of the second node N2may be maintained at a voltage (a 2-step low voltage) that is less than the voltage of the second power supply VSS by coupling of the third capacitor C3.

At a third time t3, the emission control signal EM[i−1] of the preceding stage may be supplied to the first input terminal101. The first clock signal CLK1may be supplied to the second input terminal102. The control node signal QB[i−1] of the preceding stage may be supplied to the fourth input terminal105. When the first clock signal CLK1is supplied to the second input terminal102, the first transistor M1, the fourth transistor M4, and the fifth transistor M5may be turned on.

When the fifth transistor M5is turned on, the voltage of the first power supply VDD may be supplied to the fifth node N5. Thereby, the high voltage may be supplied to the second electrode of the second capacitor C2.

When the first transistor M1is turned on, the first input terminal101, the fourth node N4, and the second node N2may be electrically coupled to each other. Then, the fourth node N4and the second node N2may be set to the high voltage by the emission control signal EM[i−1] of the preceding stage that is supplied to the first input terminal101. When the fourth node N4and the second node N2are set to the high voltage, the third transistor M3, the eighth transistor M8, and the tenth transistor M10may be turned off.

When the fourth transistor M4is turned on, the fourth input terminal105and the third node N3may be electrically coupled to each other. Then, the third node N3may be set to the low voltage by the control node signal QB[i−1] of the preceding stage that is supplied to the fourth input terminal105. When the third node N3is set to the low voltage, the second transistor M2and the sixth transistor M6may be turned on. Furthermore, the low voltage may be supplied to the first electrode of the second capacitor C2coupled to the third node N3. Because the high voltage is supplied to the second electrode of the second capacitor C2, the second capacitor C2may be charged, and a potential difference between the opposite electrodes of the second capacitor C2may be set to a high level.

When the second transistor M2is turned on, the voltage of the first power supply VDD may be supplied to the seventh node N7. Because the high voltage is supplied to a first electrode of the third capacitor C3that is coupled to the seventh node N7and the high voltage is supplied to a second electrode of the third capacitor C3that is coupled to the second node N2, the third capacitor C3may be discharged, and a potential difference between the opposite electrodes of the third capacitor C3may be set to a low level.

When the sixth transistor M6is turned on, the second clock signal CLK2that is supplied to the third input terminal103may be supplied to the fifth node N5. Because the second clock signal CLK2is not supplied to the third input terminal103at the third time t3, the high voltage may be supplied to the fifth node N5.

At a fourth time t4, the second clock signal CLK2may be supplied to the third input terminal103. When the second clock signal CLK2is supplied to the third input terminal103, the seventh transistor M7may be turned on.

When the seventh transistor M7is turned on, the fifth node N5and the first node N1may be electrically coupled to each other. Here, the low-level second clock signal CLK2that is supplied to the third input terminal103via the sixth transistor M6that remains turned on may be supplied to the fifth node N5and the first node N1. When the low voltage is supplied to the first node N1, the ninth transistor M9may be turned on.

When the ninth transistor M9is turned on, the voltage of the first power supply VDD may be supplied to the first output terminal104. The voltage of the first power supply VDD that is supplied to the first output terminal104may be supplied to the i-th emission control line Ei as the emission control signal EM[i].

Because the first node N1is set to the low voltage, the control node signal QB[i] may be supplied to the second output terminal106.

At a fifth time t5, the first clock signal CLK1may be supplied to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the first transistor M1, the fourth transistor M4, and the fifth transistor M5may be turned on.

When the fifth transistor M5is turned on, the voltage of the first power supply VDD may be supplied to the fifth node N5. Thereby, the high voltage may be supplied to the second electrode of the second capacitor C2.

When the first transistor M1is turned on, the first input terminal101, the fourth node N4, and the second node N2may be electrically coupled to each other. Then, the fourth node N4and the second node N2may remain in the high voltage state by the emission control signal EM[i−1] of the preceding stage that is supplied to the first input terminal101.

When the fourth transistor M4is turned on, the fourth input terminal105and the third node N3may be electrically coupled to each other. Then, the third node N3may remain in the low voltage state by the control node signal QB[i−1] of the preceding stage that is supplied to the fourth input terminal105. Furthermore, the first electrode of the second capacitor C2coupled to the third node N3may remain in the low voltage state. Because the high voltage is supplied to the second electrode of the second capacitor C2, the second capacitor C2may be charged, and the potential difference between the opposite electrodes of the second capacitor C2may be maintained at the high level.

When the second transistor M2is turned on, the voltage of the first power supply VDD may be supplied to the seventh node N7. Because the high voltage is supplied to the first electrode of the third capacitor C3that is coupled to the seventh node N7and the high voltage is supplied to the second electrode of the third capacitor C3that is coupled to the second node N2, the third capacitor C3may be discharged, and the potential difference between the opposite electrodes of the third capacitor C3may be maintained at the low level.

When the sixth transistor M6is turned on, the second clock signal CLK2that is supplied to the third input terminal103may be supplied to the fifth node N5. Because the second clock signal CLK2is not supplied to the third input terminal103at the fifth time t5, the high voltage may be supplied to the fifth node N5.

Because the ninth transistor M9remains turned on at the fifth time t5, the emission control signal EM[i] may remain in the supply state.

The operation at a sixth time t6is the same as that at the fourth time t4; therefore, a repeated detailed description thereof will be omitted. During the sixth time t6, the emission control signal EM[i] may remain in the supply state.

The operation after a seventh time t7is the same as that at the first time t1and the second time t2. After the seventh time t7, the supply of the emission control signal EM[i−1] (or the start signal FLM) of the preceding stage and the control node signal QB[i−1] (or the control node start signal FQB) of the preceding stage is interrupted. Therefore, the emission control signal EM[i] may not be output. While the emission control signal EM[i] is not supplied after the seventh time t7, as shown in the description of the operation pertaining to the first time t1and the second time t2, the potential difference between the opposite electrodes of the second capacitor C2may be maintained at the low level, and the potential difference between the opposite electrodes of the third capacitor C3may be maintained at the high level.

In other words, in the present disclosure, while the emission control signal EM[i] is disabled, the second capacitor C2and the third capacitor C3may be neither charged nor discharged. Therefore, the power consumption of the display device may be reduced.

FIG. 5is a circuit diagram illustrating a stage illustrated inFIG. 2in accordance with a second embodiment of the present disclosure. InFIG. 5, the same reference numerals are used to designate the same components as those ofFIG. 3, and a repeated detailed description thereof will be omitted.

Referring toFIG. 5, the stage400-1in accordance with the second embodiment of the present disclosure may include an input unit410-1, an output unit420-1, a first signal processing unit430-1, a second signal processing unit440, a third signal processing unit450, and first and second stabilization units461and462.

The input unit410-1may control the voltages of a third node N3and a fourth node N4in response to signals supplied to a first input terminal101and a second input terminal102. To this end, the input unit410-1may include a first transistor M1, a fourth transistor M4, a sixteenth transistor M16, and a seventeenth transistor M17.

The first transistor M1is coupled between the first input terminal101and the fourth node N4. A gate electrode of the first transistor M1is coupled to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the first transistor M1may be turned on to electrically couple the first input terminal101with the fourth node N4.

A first electrode of the fourth transistor M4is coupled to an eighth node N8, and a second electrode thereof is coupled to the third node N3via an eleventh transistor M11. A gate electrode of the fourth transistor M4is coupled to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the fourth transistor M4may be turned on to electrically couple the eighth node N8with the third node N3.

The sixteenth transistor M16is coupled between a first power supply VDD and the eighth node N8. A gate electrode of the sixteenth transistor M16is coupled to the first input terminal101. The sixteenth transistor M16may be formed of a P-type transistor. When a low voltage is supplied to the first input terminal101, the sixteenth transistor M16may be turned on so that a high voltage may be supplied to the eighth node N8.

The seventeenth transistor M17is coupled between the eighth node N8and the second power supply VSS. A gate electrode of the seventeenth transistor M17is coupled to the first input terminal101. The seventeenth transistor M17may be formed of an N-type transistor. When a high voltage is supplied to the first input terminal101, the seventeenth transistor M17may be turned on so that a low voltage may be supplied to the eighth node N8.

The first signal processing unit430-1may control the voltage of the first node N1in response to a voltage of the fourth node N4. The first signal processing unit430-1may supply the voltage of the first power supply VDD to the first node N1in response to the voltage of the fourth node N4. To this end, the first signal processing unit430-1may include an eighth transistor M8and a first capacitor C1.

The eighth transistor M8is coupled between the first power supply VDD and the first node N1. A gate electrode of the eighth transistor M8may be coupled to the fourth node N4. The eighth transistor M8may be turned on or off depending on the voltage of the fourth node N4.

The first capacitor C1is coupled between the first power supply VDD and the first node N1. The first capacitor C1may charge a voltage to be applied to the first node N1. Furthermore, the first capacitor C1may stably maintain the voltage of the first node N1.

In the second embodiment of the present disclosure, the emission control signal EM[i−1] of the preceding stage may be inverted using the sixteenth transistor M16and the seventeenth transistor M17that are formed of inverters (e.g., that collectively form an inverter), and then supplied to the third node N3. In this case, the stage400-1according to the second embodiment has the same configuration as that ofFIG. 3except that the control node signal QB[i−1] of the preceding stage is replaced with the emission control signal EM[i−1] of the preceding stage (e.g., the fourth input terminal is effectively the same as, or is coupled to, the first input terminal101). Therefore, detailed description of the process of the operation will be omitted.

FIG. 6is a circuit diagram illustrating a stage illustrated inFIG. 2in accordance with a third embodiment of the present disclosure. InFIG. 6, the same reference numerals are used to designate the same components as those ofFIG. 3, and a repeated detailed description thereof will be omitted.

Referring toFIG. 6, a stage400-2in accordance with the third embodiment of the present disclosure may include an input unit410, an output unit420, a first signal processing unit430, a second signal processing unit440, and a third signal processing unit450.

The stage400-2according to the third embodiment, except that the first and second stabilization units461and462are omitted, has the same configuration as that ofFIG. 3. Therefore, detailed description of the process of the operation will be omitted.

FIG. 7is a circuit diagram illustrating a stage illustrated inFIG. 2in accordance with a fourth embodiment of the present disclosure. InFIG. 7, the same reference numerals are used to designate the same components as those ofFIG. 3, and a repeated detailed description thereof will be omitted.

Referring toFIG. 7, the stage400-3in accordance with the fourth embodiment of the present disclosure may include an input unit410, an output unit420, a first signal processing unit430, a second signal processing unit440-3, a third signal processing unit450, and first and second stabilization units461and462.

The second signal processing unit440-3is coupled to a third node N3, and may control the voltage of a first node N1in response to a signal input to a third input terminal103. To this end, the second signal processing unit440-3may include a seventh transistor M7, a sixth transistor M6, a fifth transistor M5, and a second capacitor C2.

A first terminal of the second capacitor C2is coupled to the third node N3, and a second terminal thereof is coupled to a fifth node N5.

The seventh transistor M7is coupled between the fifth node N5and the first node N1. A gate electrode of the seventh transistor M7is coupled to the third input terminal103. When the second clock signal CLK2is supplied to the third input terminal103, the seventh transistor M7may be turned on to electrically couple the fifth node N5with the first node N1.

The sixth transistor M6is coupled between the fifth node N5and the third input terminal103. A gate electrode of the sixth transistor M6is coupled to the third node N3. The sixth transistor M6may be turned on or off depending on the voltage of the third node N3.

The fifth transistor M5is coupled between the third input terminal103and the fifth node N5. A gate electrode of the fifth transistor M5is coupled to the second input terminal102. The fifth transistor M5may be turned on or off in response to the first clock signal CLK1supplied to the second input terminal102.

The stage400-3according to the fourth embodiment, except that the fifth transistor M5of the second signal processing unit440-3is coupled to the third input terminal103rather than the first power supply VDD, has the same configuration as that ofFIG. 3. Therefore, detailed description of the process of the operation will be omitted.

FIG. 8is a circuit diagram illustrating a stage illustrated inFIG. 2in accordance with a fifth embodiment of the present disclosure. AlthoughFIG. 8illustrates only an i-th stage for the sake of explanation, the stages illustrated inFIG. 2may have the same structure as that of the i-th stage to be described below.

Referring toFIG. 8, the stage400-4in accordance with the fifth embodiment of the present disclosure may include an input unit410-4, an output unit420, a first signal processing unit430, a second signal processing unit440, a third signal processing unit450-4, and first to third stabilization units461,462, and463.

The output unit420may supply the voltage of a first power supply VDD or a second power supply VSS to a first output terminal104depending on voltages of a first node N1and a second node N2. To this end, the output unit420may include a ninth transistor M9and a tenth transistor M10.

The ninth transistor M9is coupled between the first power supply VDD and the first output terminal104. A gate electrode of the ninth transistor M9may be coupled to the first node N1. The ninth transistor M9may be turned on or off depending on the voltage of the first node N1. Here, the voltage of the first power supply VDD that is supplied to the first output terminal104when the ninth transistor M9is turned on may be used as an emission control signal EM[i] of an i-th emission control line Ei.

The tenth transistor M10is coupled between the first output terminal104and the second power supply VSS. A gate electrode of the tenth transistor M10is coupled to the second node N2. The tenth transistor M10may be turned on or off depending on the voltage of the second node N2.

The input unit410-4may control the voltages of a third node N3and a fourth node N4in response to signals supplied to a first input terminal101, a second input terminal102, and a fourth input terminal105. To this end, the input unit410-4may include a first transistor M1, a fourth transistor M4, and a thirteenth transistor M13.

The first transistor M1is coupled between the first input terminal101and the fourth node N4. A gate electrode of the first transistor M1is coupled to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the first transistor M1may be turned on to electrically couple the first input terminal101with the fourth node N4.

A first electrode of the fourth transistor M4is coupled to the fourth input terminal105, and a second electrode thereof is coupled to the third node N3via an eleventh transistor M11. A gate electrode of the fourth transistor M4is coupled to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the fourth transistor M4may be turned on to electrically couple the fourth input terminal105with the third node N3.

A first electrode of the thirteenth transistor M13is coupled to the first input terminal101, and a second electrode thereof is coupled to a sixth node N6via a fourteenth transistor M14. A gate electrode of the thirteenth transistor M13is coupled to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the thirteenth transistor M13may be turned on to electrically couple the first input terminal101with the sixth node N6.

The first signal processing unit430may control the voltage of the first node N1in response to a voltage of the fourth node N4. The first signal processing unit430may supply the voltage of the first power supply VDD to the second output terminal106in response to the voltages of the first node N1and the fourth node N4. To this end, the first signal processing unit430may include an eighth transistor M8and a first capacitor C1.

The eighth transistor M8is coupled between the first power supply VDD and the first node N1. A gate electrode of the eighth transistor M8may be coupled to the fourth node N4. The eighth transistor M8may be turned on or off depending on the voltage of the fourth node N4. Here, the voltage of the first power supply VDD that is supplied to the second output terminal106when the eighth transistor M8is turned on may be used as a control node signal QB[i].

The first capacitor C1is coupled between the first power supply VDD and the first node N1. The first capacitor C1may charge a voltage to be applied to the first node N1. Furthermore, the first capacitor C1may stably maintain the voltage of the first node N1.

The second signal processing unit440is coupled to the third node N3, and may control the voltage of the first node N1in response to a signal input to the third input terminal103. To this end, the second signal processing unit440may include a seventh transistor M7, a sixth transistor M6, a fifth transistor M5, and a second capacitor C2.

A first terminal of the second capacitor C2is coupled to the third node N3, and a second terminal thereof is coupled to a fifth node N5.

The seventh transistor M7is coupled between the fifth node N5and the first node N1. A gate electrode of the seventh transistor M7is coupled to the third input terminal103. When the second clock signal CLK2is supplied to the third input terminal103, the seventh transistor M7may be turned on to electrically couple the fifth node N5with the first node N1.

The sixth transistor M6is coupled between the fifth node N5and the third input terminal103. A gate electrode of the sixth transistor M6is coupled to the third node N3. The sixth transistor M6may be turned on or off depending on the voltage of the third node N3.

The fifth transistor M5is coupled between the first power supply VDD and the fifth node N5. A gate electrode of the fifth transistor M5is coupled to the second input terminal102. The fifth transistor M5may be turned on or off in response to the first clock signal CLK1supplied to the second input terminal102.

The third signal processing unit450-4may control the voltage of the sixth node N6in response to the voltage of the third node N3and a signal input to the third input terminal103. To this end, the third signal processing unit450-4may include a second transistor M2, a third transistor M3, a fifteenth transistor M15, and a third capacitor C3.

A first electrode of the third capacitor C3is coupled to a seventh node N7, and a second electrode thereof is coupled to the sixth node N6.

The second transistor M2is coupled between the first power supply VDD and the seventh node N7. A gate electrode of the second transistor M2is coupled to the third node N3. The second transistor M2may be turned on or off depending on the voltage of the third node N3.

The third transistor M3is coupled between the seventh node N7and the third input terminal103. A gate electrode of the third transistor M3is coupled to the sixth node N6. The third transistor M3may be turned on or off depending on the voltage of the second node N2.

The fifteenth transistor M15is coupled between the sixth node N6and the second node N2. A gate electrode of the fifteenth transistor M15is coupled to the sixth node N6. The fifteenth transistor M15is connected in the form of a diode to allow current to flow from the second node N2to the sixth node N6.

The first stabilization unit461is coupled between the second signal processing unit440and the third signal processing unit450-4. The first stabilization unit461may limit a voltage drop width of the third node N3. To this end, the first stabilization unit461may include the eleventh transistor M11.

The eleventh transistor M11is coupled between the fourth input terminal105and the third node N3. A gate electrode of the eleventh transistor M11is coupled to the second power supply VSS. The eleventh transistor M11may be set to a turned-on state.

The second stabilization unit462is coupled between the fourth node N4and the second node N2. The second stabilization unit462may limit a voltage drop width of the fourth node N4. To this end, the second stabilization unit462may include a twelfth transistor M12.

The twelfth transistor M12is coupled between the second node N2and the fourth node N4. A gate electrode of the twelfth transistor M12is coupled to the second power supply VSS. The twelfth transistor M12may be set to a turned-on state.

The third stabilization unit463is coupled between the input unit410-4and the third signal processing unit450-4. The third stabilization unit463may limit a voltage drop width of the sixth node N6. To this end, the first stabilization unit463may include the fourteenth transistor M14.

The fourteenth transistor M14is coupled between the thirteenth transistor M13and the sixth node N6. A gate electrode of the fourteenth transistor M14is coupled to the second power supply VSS. The fourteenth transistor M14may be set to a turned-on state.

FIG. 9is a waveform diagram illustrating an operation of the stage illustrated inFIG. 8. For the sake of explanation,FIG. 9illustrates the operation of only the i-th stage.

Referring toFIG. 9, each of the first clock signal CLK1and the second clock signal CLK2may have a cycle of two horizontal periods (2H), and the first clock signal CLK1and the second clock signal CLK2may be supplied in different horizontal periods. In other words, the second clock signal CLK2may be set to a signal shifted by a half cycle (e.g., one horizontal period (1H)) from the first clock signal CLK1.

When the clock signals CLK1and CLK2are supplied, the second input terminal102and the third input terminal103may be set to the voltage of the second power supply VSS. When the clock signals CLK1and CLK2are not supplied, the second input terminal102and the third input terminal103may be set to the voltage of the first power supply VDD.

When the start signal FLM (or the emission control signal EM[i−1] of the preceding stage) is supplied, the first input terminal101may be set to the voltage of the first power supply VDD. When the start signal FLM (or the emission control signal EM[i−1] of the preceding stage) is not supplied, the first input terminal101may be set to the voltage of the second power supply VSS.

Furthermore, the start signal FLM (or the emission control signal EM[i−1] of the preceding stage) to be supplied to the first input terminal101may be set to overlap at least once with the first clock signal CLK1to be supplied to the second input terminal102. To this end, the start signal FLM (or the emission control signal EM) may have a width that is greater than that of the first clock signal CLK1and, for example, may be supplied during four horizontal periods (4H). In this case, a first emission control signal to be supplied to the first input terminal101of the following stage may also overlap at least once with the second clock signal CLK2to be supplied to the second input terminal102of the following stage.

The control node start signal FQB (or the control node signal QB) may have a phase that is inverted from that of the start signal FLM (or the emission control signal EM). In other words, when the control node start signal FQB (or the control node signal QB[i−1] of the preceding stage) is supplied, the fourth input terminal105may be set to the voltage of the second power supply VSS. When the control node start signal FQB (or the control node signal QB[i−1] of the preceding stage) is not supplied, the fourth input terminal105may be set to the voltage of the first power supply VDD.

Furthermore, the control node start signal FQB (or the control node signal QB[i−1] of the preceding stage) to be supplied to the fourth input terminal105may be set to overlap at least once with the first clock signal CLK1to be supplied to the second input terminal102. To this end, the control node start signal FQB (or the control node signal QB) may have a width greater than that of the first clock signal CLK1and, for example, be supplied during four horizontal periods (4H). In this case, the control node signal QB to be supplied to the fourth input terminal105of the following stage may also overlap at least once with the second clock signal CLK2to be supplied to the second input terminal102of the following stage.

Furthermore, the control node start signal FQB (or the control node signal QB[i−1] of the preceding stage) to be supplied to the fourth input terminal105may be set to overlap with the start signal FLM (or the emission control signal EM[i−1] of the preceding stage) to be supplied to the first input terminal101.

A process of the operation will be described. First, at a first time t1, the first clock signal CLK1may be supplied to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the first transistor M1, the fourth transistor M4, the fifth transistor M5, and the thirteenth transistor M13may be turned on.

When the fifth transistor M5is turned on, the voltage of the first power supply VDD may be supplied to the fifth node N5. Thereby, the high voltage may be supplied to the second electrode of the second capacitor C2.

When the first transistor M1is turned on, the first input terminal101and the fourth node N4may be electrically coupled to each other. Here, because the twelfth transistor M12remains turned on, the first input terminal101may also be electrically coupled with the second node N2via the fourth node N4. Here, at the first time t1, the emission control signal EM[i−1] (or the start signal FLM) of the preceding stage may not be supplied to the first input terminal101, so that a low voltage (e.g., VSS) may be supplied to the fourth node N4and the second node N2. When the low voltage is supplied to the fourth node N4, the eighth transistor M8and the tenth transistor M10may be turned on.

When the eighth transistor M8is turned on, the voltage of the first power supply VDD may be supplied to the first node N1. Hence, the ninth transistor M9may be turned off. As the high voltage is supplied to the first node N1, the high voltage may be supplied to the second electrode of the first capacitor C1. Because a first electrode of the first capacitor C1is coupled with the first power supply VDD and thus has a high voltage, a potential difference between the opposite electrodes of the first capacitor C1may have a low level/may be low.

When the eighth transistor M8is turned on, the voltage of the first power supply VDD may be supplied to the second output terminal106. Hence, at the first time t1, the control node signal QB[i] is not supplied to the second output terminal106.

When the tenth transistor M10is turned on, the voltage of the second power supply VSS may be supplied to the first output terminal104. Therefore, during the first time t1, the emission control signal EM[i] may not be supplied to the emission control line Ei.

When the fourth transistor M4is turned on, the control node signal QB[i−1] (or the control node start signal FQB) of the preceding stage that is supplied to the fourth input terminal105may be supplied to the third node N3via the eleventh transistor M11that remains turned on. Here, during the first time t1, the control node signal QB[i−1] of the preceding stage may not be supplied to the fourth input terminal105, so that the high voltage may be supplied to the third node N3. When the high voltage is supplied to the third node N3, the second transistor M2and the sixth transistor M6may be turned off. Furthermore, the high voltage may be supplied to a first electrode of the second capacitor C2coupled to the third node N3. Because the high voltage is supplied to the second electrode of the second capacitor C2, a potential difference between the opposite electrodes of the second capacitor C2may have a low level.

When the thirteenth transistor M13is turned on, the first input terminal101is electrically coupled with the sixth node N6via the fourteenth transistor M14that remains turned on. Here, at the first time t1, the emission control signal EM[i−1] of the preceding stage may not be supplied to the first input terminal101, so that the low voltage may be supplied to the sixth node N6. When the low voltage is supplied to the sixth node N6, the third transistor M3and the fifteenth transistor M15may be turned on.

The fifteenth transistor M15is coupled in the form of a diode between the sixth node N6and the second node N2.

When the third transistor M3is turned on, the third input terminal103and the seventh node N7may be electrically coupled to each other. Because the second clock signal CLK2is not supplied to the third input terminal103at the first time t1, the high voltage may be supplied to the seventh node N7. Because the high voltage is supplied to the first electrode of the third capacitor C3coupled to the seventh node N7and the low voltage is supplied to the second electrode thereof, a potential difference between the opposite electrodes of the third capacitor C3may have a high level. Here, the voltage of the second node N2may be maintained at a voltage (a 2-step low voltage) that is less than the low-level voltage by coupling of the third capacitor C3.

At a second time t2, the supply of the first clock signal CLK1to the second input terminal102may be interrupted. When the supply of the first clock signal CLK1is interrupted, the first transistor M1, the fourth transistor M4, the fifth transistor M5, and the thirteenth transistor M13may be turned off. Here, the first node N1and the second node N2may maintain the voltages of the preceding period by the first capacitor C1and the third capacitor C3. Because the first node N1remains in the high voltage state, the ninth transistor M9may remain turned off. Because the second node N2remains in the low voltage state, the third transistor M3, the eighth transistor M8, and the tenth transistor M10may remain turned on.

At the second time t2, the second clock signal CLK2may be supplied to the third input terminal103. When the second clock signal CLK2is supplied to the third input terminal103, the seventh transistor M7may be turned on.

When the seventh transistor M7is turned on, the first node N1and the fifth node N5may be electrically coupled to each other. Thereby, the fifth node N5may remain in the high voltage state, and a potential difference between the opposite electrodes of the second capacitor C2may be maintained at the low level.

At the second time t2, the low-level second clock signal CLK2may be supplied to the seventh node N7. Therefore, a low-level voltage is supplied to the seventh node N7. Here, the voltage of the sixth node N6may be set to a voltage (two step low voltage) that is less than the low voltage by the fifteenth transistor M15connected in the form of a diode, and a potential difference between the opposite electrodes of the third capacitor C3may be maintained at the high level.

As such, while the emission control signal EM[i] is not supplied to the emission control line Ei, the potential difference between the opposite electrodes of each of the second capacitor C2and the third capacitor C3may be stably maintained. Hence, the capacitor C2and the third capacitor C3may be prevented from being charged or discharged (e.g., may have a degree of charging or discharging thereof reduced), and the power consumption may be consequently reduced.

At a third time t3, the emission control signal EM[i−1] of the preceding stage may be supplied to the first input terminal101. The first clock signal CLK1may be supplied to the second input terminal102. The control node signal QB[i−1] of the preceding stage may be supplied to the fourth input terminal105. When the first clock signal CLK1is supplied to the second input terminal102, the first transistor M1, the fourth transistor M4, the fifth transistor M5, and the thirteenth transistor M13may be turned on.

When the fifth transistor M5is turned on, the voltage of the first power supply VDD may be supplied to the fifth node N5. Thereby, the high voltage may be supplied to the second electrode of the second capacitor C2.

When the first transistor M1is turned on, the first input terminal101, the fourth node N4, and the second node N2may be electrically coupled to each other. Then, the fourth node N4and the second node N2may be set to the high voltage by the emission control signal EM[i−1] of the preceding stage that is supplied to the first input terminal101. When the fourth node N4and the second node N2are set to the high voltage, the eighth transistor M8and the tenth transistor M10may be turned off.

When the fourth transistor M4is turned on, the fourth input terminal105and the third node N3may be electrically coupled to each other. Then, the third node N3may be set to a low voltage by the control node signal QB[i−1] of the preceding stage that is supplied to the fourth input terminal105. When the third node N3is set to the low voltage, the second transistor M2and the sixth transistor M6may be turned on. Furthermore, the low voltage may be supplied to the first electrode of the second capacitor C2coupled to the third node N3. Because the high voltage is supplied to the second electrode of the second capacitor C2, the second capacitor C2may be charged, and a potential difference between the opposite electrodes of the second capacitor C2may be set to a high level.

When the second transistor M2is turned on, the voltage of the first power supply VDD may be supplied to the seventh node N7. Hence, the high voltage may be supplied to the first electrode of the third capacitor C3coupled to the seventh node N7.

When the sixth transistor M6is turned on, the second clock signal CLK2that is supplied to the third input terminal103may be supplied to the fifth node N5. Because the second clock signal CLK2is not supplied to the third input terminal103at the third time t3, the high voltage may be supplied to the fifth node N5. Here, the driving performance of the sixth transistor M6may be enhanced by coupling of the second capacitor C2.

When the thirteenth transistor M13is turned on, the first input terminal101is electrically coupled with the sixth node N6via the fourteenth transistor M14that remains turned on. Here, at the third time t3, the emission control signal EM[i−1] of the preceding stage may be supplied to the first input terminal101, so that a high voltage may be supplied to the sixth node N6. When the high voltage is supplied to the sixth node N6, the third transistor M3and the fifteenth transistor M15may be turned off.

Because the high voltage is supplied to the second electrode of the third capacitor C3that is coupled to the sixth node N6and the high voltage is supplied to the first electrode of the third capacitor C3, the third capacitor C3may be discharged, and a potential difference between the opposite electrodes of the third capacitor C3may be set to a low level.

At a fourth time t4, the second clock signal CLK2may be supplied to the third input terminal103. When the second clock signal CLK2is supplied to the third input terminal103, the seventh transistor M7may be turned on.

When the seventh transistor M7is turned on, the fifth node N5and the first node N1may be electrically coupled to each other. Here, the low-level second clock signal CLK2that is supplied to the third input terminal103may be supplied to the fifth node N5and the first node N1via the sixth transistor M6that remains turned on. When the low voltage is supplied to the first node N1, the ninth transistor M9may be turned on.

When the ninth transistor M9is turned on, the voltage of the first power supply VDD may be supplied to the first output terminal104. The voltage of the first power supply VDD that is supplied to the first output terminal104may be supplied to the i-th emission control line Ei as the emission control signal EM[i].

Because the first node N1is set to the low voltage, the control node signal QB[i] may be supplied to the second output terminal106.

At a fifth time t5, the first clock signal CLK1may be supplied to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the first transistor M1, the fourth transistor M4, the fifth transistor M5, and the thirteenth transistor M13may be turned on.

When the fifth transistor M5is turned on, the voltage of the first power supply VDD may be supplied to the fifth node N5. Thereby, the high voltage may be supplied to the second electrode of the second capacitor C2.

When the first transistor M1is turned on, the first input terminal101, the fourth node N4, and the second node N2may be electrically coupled to each other. Then, the fourth node N4and the second node N2may remain in the high voltage state by the emission control signal EM[i−1] of the preceding stage that is supplied to the first input terminal101.

When the fourth transistor M4is turned on, the fourth input terminal105and the third node N3may be electrically coupled to each other. Then, the third node N3may remain in the low voltage state by the control node signal QB[i−1] of the preceding stage that is supplied to the fourth input terminal105. Furthermore, the low voltage may be supplied to the first electrode of the second capacitor C2coupled to the third node N3. Because the high voltage is supplied to the second electrode of the second capacitor C2, the second capacitor C2may be charged, and the potential difference between the opposite electrodes of the second capacitor C2may be maintained at the high level.

When the second transistor M2is turned on, the voltage of the first power supply VDD may be supplied to the seventh node N7. Hence, the high voltage may be supplied to the first electrode of the third capacitor C3coupled to the seventh node N7.

When the sixth transistor M6is turned on, the second clock signal CLK2that is supplied to the third input terminal103may be supplied to the fifth node N5. Because the second clock signal CLK2is not supplied to the third input terminal103at the fifth time t5, the high voltage may be supplied to the fifth node N5. Here, the driving performance of the sixth transistor M6may be enhanced by coupling of the second capacitor C2.

When the thirteenth transistor M13is turned on, the first input terminal101is electrically coupled with the sixth node N6via the fourteenth transistor M14that remains turned on. Here, at the third time t3, the emission control signal EM[i−1] of the preceding stage may be supplied to the first input terminal101, so that a high voltage may be supplied to the sixth node N6. When the high voltage is supplied to the sixth node N6, the third transistor M3and the fifteenth transistor M15may be turned off.

Because the high voltage is supplied to the second electrode of the third capacitor C3that is coupled to the sixth node N6and the high voltage is supplied to the first electrode of the third capacitor C3, the third capacitor C3may be discharged, and a potential difference between the opposite electrodes of the third capacitor C3may be maintained at the low level.

The operation at a sixth time t6is the same as that at the fourth time t4; therefore, a repeated detailed description thereof will be omitted. During the sixth time t6, the emission control signal EM[i] may remain in the supply state.

The operation after a seventh time t7is the same as that at the first time t1and the second time t2. After the seventh time t7, the supply of the emission control signal EM[i−1] (or the start signal FLM) of the preceding stage and the control node signal QB[i−1] (or the control node start signal FQB) of the preceding stage is interrupted. Therefore, the emission control signal EM[i] may not be output. While the emission control signal EM[i] is not supplied after the seventh time t7, as shown in the description of the operation pertaining to the first time t1and the second time t2, the potential difference between the opposite electrodes of the second capacitor C2may be maintained at the low level, and the potential difference between the opposite electrodes of the third capacitor C3may be maintained at the high level.

In other words, in the present disclosure, while the emission control signal EM[i] is disabled, the second capacitor C2and the third capacitor C3may be neither charged nor discharged. Therefore, the power consumption of the display device may be reduced.

FIG. 10is a circuit diagram illustrating a stage illustrated inFIG. 2in accordance with a sixth embodiment of the present disclosure. InFIG. 10, the same reference numerals are used to designate the same components as those ofFIG. 8, and a repeated detailed description thereof will be omitted.

Referring toFIG. 10, the stage400-5in accordance with the sixth embodiment of the present disclosure may include an input unit410-5, an output unit420, a first signal processing unit430-5, a second signal processing unit440, a third signal processing unit450-4, and first to third stabilization units461,462, and463.

The input unit410-5may control the voltages of a third node N3and a fourth node N4in response to signals supplied to a first input terminal101, and a second input terminal102. To this end, the input unit410-5may include a first transistor M1, a fourth transistor M4, a thirteenth transistor M13, a sixteenth transistor M16, and a seventeenth transistor M17.

The first transistor M1is coupled between the first input terminal101and the fourth node N4. A gate electrode of the first transistor M1is coupled to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the first transistor M1may be turned on to electrically couple the first input terminal101with the fourth node N4.

A first electrode of the fourth transistor M4is coupled to an eighth node N8, and a second electrode thereof is coupled to the third node N3via an eleventh transistor M11. A gate electrode of the fourth transistor M4is coupled to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the fourth transistor M4may be turned on to electrically couple the eighth node N8with the third node N3.

A first electrode of the thirteenth transistor M13is coupled to the first input terminal101, and a second electrode thereof is coupled to a sixth node N6via a fourteenth transistor M14. A gate electrode of the thirteenth transistor M13is coupled to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the thirteenth transistor M13may be turned on to electrically couple the first input terminal101with the sixth node N6.

The sixteenth transistor M16is coupled between a first power supply VDD and the eighth node N8. A gate electrode of the sixteenth transistor M16is coupled to the first input terminal101. The sixteenth transistor M16may be formed of a P-type transistor. When a low voltage is supplied to the first input terminal101, the sixteenth transistor M16may be turned on so that a high voltage may be supplied to the eighth node N8.

The seventeenth transistor M17is coupled between the eighth node N8and a second power supply VSS. A gate electrode of the seventeenth transistor M17is coupled to the first input terminal101. The seventeenth transistor M17may be formed of an N-type transistor. When a high voltage is supplied to the first input terminal101, the seventeenth transistor M17may be turned on so that a low voltage may be supplied to the eighth node N8.

The first signal processing unit430-5may control the voltage of the first node N1in response to a voltage of the fourth node N4. The first signal processing unit430-5may supply the voltage of the first power supply VDD to the first node N1in response to the voltage of the fourth node N4. To this end, the first signal processing unit430-5may include an eighth transistor M8and a first capacitor C1.

The eighth transistor M8is coupled between the first power supply VDD and the first node N1. A gate electrode of the eighth transistor M8may be coupled to the fourth node N4. The eighth transistor M8may be turned on or off depending on the voltage of the fourth node N4.

The first capacitor C1is coupled between the first power supply VDD and the first node N1. The first capacitor C1may charge a voltage to be applied to the first node N1. Furthermore, the first capacitor C1may stably maintain the voltage of the first node N1.

In the sixth embodiment of the present disclosure, the emission control signal EM[i−1] of the preceding stage may be inverted using the sixteenth transistor M16and the seventeenth transistor M17that are formed as an inverter, and may then be supplied to the third node N3. In this case, the stage400-5according to the sixth embodiment has the same configuration as that ofFIG. 8except that the control node signal QB[i−1] of the preceding stage is replaced with the emission control signal EM[i−1] of the preceding stage. Therefore, detailed description of the process of the operation will be omitted.

FIG. 11is a circuit diagram illustrating a stage illustrated inFIG. 2in accordance with a seventh embodiment of the present disclosure. InFIG. 11, the same reference numerals are used to designate the same components as those ofFIG. 8, and a repeated detailed description thereof will be omitted.

Referring toFIG. 11, a stage400-6in accordance with the seventh embodiment of the present disclosure may include an input unit410-4, an output unit420, a first signal processing unit430, a second signal processing unit440, and a third signal processing unit450-4.

The stage400-6according to the seventh embodiment has the same configuration as that ofFIG. 8except that the first to third stabilization units461,462, and463are omitted. Therefore, detailed description of the process of the operation will be omitted.

FIG. 12is a circuit diagram illustrating a stage illustrated inFIG. 2in accordance with an eighth embodiment of the present disclosure. InFIG. 12, the same reference numerals are used to designate the same components as those ofFIG. 8, and a repeated detailed description thereof will be omitted.

Referring toFIG. 12, the stage400-7in accordance with the eighth embodiment of the present disclosure may include an input unit410-4, an output unit420, a first signal processing unit430, a second signal processing unit440-7, a third signal processing unit450-4, and first to third stabilization units461,462, and463.

The second signal processing unit440-7is coupled to a third node N3, and may control the voltage of a first node N1in response to a signal input to a third input terminal103. To this end, the second signal processing unit440-7may include a seventh transistor M7, a sixth transistor M6, a fifth transistor M5, and a second capacitor C2.

A first terminal of the second capacitor C2is coupled to the third node N3, and a second terminal thereof is coupled to a fifth node N5.

The seventh transistor M7is coupled between the fifth node N5and the first node N1. A gate electrode of the seventh transistor M7is coupled to the third input terminal103. When the second clock signal CLK2is supplied to the third input terminal103, the seventh transistor M7may be turned on to electrically couple the fifth node N5with the first node N1.

The sixth transistor M6is coupled between the fifth node N5and the third input terminal103. A gate electrode of the sixth transistor M6is coupled to the third node N3. The sixth transistor M6may be turned on or off depending on the voltage of the third node N3.

The fifth transistor M5is coupled between the third input terminal103and the fifth node N5. A gate electrode of the fifth transistor M5is coupled to the second input terminal102. The fifth transistor M5may be turned on or off in response to the first clock signal CLK1supplied to the second input terminal102.

The stage400-7according to the eighth embodiment has the same configuration as that ofFIG. 8except that the fifth transistor M5of the second signal processing unit440-7is coupled to the third input terminal103rather than the first power supply VDD. Therefore, detailed description of the process of the operation will be omitted.

In each of the embodiments described with reference toFIGS. 3 to 12, the stages may be formed of the same circuit. However, in some embodiments of the present disclosure, stages may be formed of different circuits. Hereinafter, these embodiments will be described in more detail with reference toFIGS. 13 and 14.

FIG. 13is a circuit diagram illustrating a first embodiment of a structure including stages formed of different circuits in accordance with the present disclosure. For the sake of explanation,FIG. 13illustrates only a first stage401and a second stage402.

Referring toFIG. 13, the first stage401may include an input unit411, an output unit421, a first signal processing unit431, a second signal processing unit441, and a third signal processing unit451.

The output unit421may supply the voltage of a first power supply VDD or a second power supply VSS to a first output terminal104depending on voltages of a first node N1and a second node N2. To this end, the output unit421may include a ninth transistor T9and a tenth transistor T10.

The ninth transistor T9is coupled between the first power supply VDD and the first output terminal104. A gate electrode of the ninth transistor T9is coupled to the first node N1. The ninth transistor T9may be turned on or off depending on the voltage of the first node N1. Here, the voltage of the first power supply VDD that is supplied to the first output terminal104when the ninth transistor T9is turned on may be used as an emission control signal of the first emission control line E1.

The tenth transistor T10is coupled between the first output terminal104and the second power supply VSS. A gate electrode of the tenth transistor T10is coupled to the second node N2. The tenth transistor T10may be turned on or off depending on the voltage of the second node N2.

The input unit411may control the voltages of a third node N3and the second node N2in response to signals supplied to a first input terminal101and a second input terminal102. To this end, the input unit411may include a first transistor T1, a second transistor T2, and a third transistor T3.

The first transistor T1is coupled between the first input terminal101and the second node N2. A gate electrode of the first transistor T1is coupled to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the first transistor T1may be turned on to electrically couple the first input terminal101with the second node N2.

The second transistor T2is coupled between the third node N3and the second input terminal102. A gate electrode of the second transistor T2is coupled to the second node N2. When the first clock signal CLK1is supplied to the second input terminal102, the first transistor T1may be turned on to electrically couple the first input terminal101with the gate electrode of the second transistor T2.

The third transistor T3is coupled between the third node N3and the second power supply VSS. A gate electrode of the third transistor T3is coupled to the second input terminal102. When the first clock signal CLK1is supplied to the second input terminal102, the third transistor T3may be turned on so that the voltage of the second power supply VSS may be supplied to the third node N3.

The first signal processing unit431may control the voltage of the first node N1in response to a voltage of the second node N2. To this end, the first signal processing unit431may include an eighth transistor T8and a third capacitor C3.

The eighth transistor T8is coupled between the first power supply VDD and the first node N1. A gate electrode of the eighth transistor T8is coupled to the second node N2. The eighth transistor T8may be turned on or off depending on the voltage of the second node N2. Here, the voltage of the first power supply VDD that is supplied to the second output terminal106when the eighth transistor T8is turned on may be supplied to a fourth input terminal105of the second stage402as a control node signal QB.

The third capacitor C3is coupled between the first power supply VDD and the first node N1. The third capacitor C3may charge a voltage to be applied to the first node N1. Furthermore, the third capacitor C3may stably maintain the voltage of the first node N1.

The second signal processing unit441is coupled to the third node N3, and may control the voltage of the first node N1in response to a signal input to the third input terminal103. To this end, the second signal processing unit441may include a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2.

The first capacitor C1is coupled between the second node N2and the third input terminal103. The first capacitor C1may charge a voltage to be applied to the second node N2. The first capacitor C1controls the voltage of the second node N2in response to the second clock signal CLK2supplied to the third input terminal103.

A first terminal of the second capacitor C2is coupled to the third node N3, and a second terminal thereof is coupled to the seventh transistor T7.

The sixth transistor T6is coupled between the second terminal of the second capacitor C2and the third input terminal103. A gate electrode of the sixth transistor T6is coupled to the third node N3. The sixth transistor T6may be turned on or off depending on the voltage of the third node N3.

The seventh transistor T7is coupled between the second terminal of the second capacitor C2and the first node N1. A gate electrode of the seventh transistor T7is coupled to the third input terminal103. When the second clock signal CLK2is supplied to the third input terminal103, the seventh transistor T7may be turned on to electrically couple the second terminal of the second capacitor C2with the first node N1.

The third signal processing unit451may control the voltage of the second node N2in response to the voltage of the third node N3and a signal input to the third input terminal103. To this end, the third signal processing unit451may include a fourth transistor T4and a fifth transistor T5.

The fourth transistor T4and the fifth transistor T5are coupled in series between the first power supply VDD and the second node N2. A gate electrode of the fourth transistor T4is coupled to the third input terminal103. The fourth transistor T4may be turned on when the second clock signal CLK2is supplied to the third input terminal103. A gate electrode of the fifth transistor T5is coupled to the third node N3. The fifth transistor T5may be turned on or off depending on the voltage of the third node N3.

In other embodiments, the first stage401may further include the first stabilization unit461and the second stabilization unit462that have been described with reference toFIGS. 3 to 7.

The second stage402may have a configuration that is different from that of the first stage401, and may be formed of any one of the circuits in accordance with the embodiments described with reference toFIGS. 3 to 12.

Although inFIG. 13the second stage402has been illustrated as having the configuration in accordance with the embodiment ofFIG. 3, this is only for illustrative purposes, and the present disclosure is not limited thereto.

FIG. 14is a circuit diagram illustrating a second embodiment of a structure including stages formed of different circuits in accordance with the present disclosure. For the sake of explanation,FIG. 14illustrates only a first stage401-1and a second stage402. InFIG. 14, the same reference numerals are used to designate the same components as those ofFIG. 13, and a repeated detailed description thereof will be omitted.

Referring toFIG. 14, the first stage401-1may include an input unit411, an output unit421, a first signal processing unit431, a second signal processing unit441-1, and a third signal processing unit451-1.

The second signal processing unit441-1is coupled to the third node N3, and may control the voltage of a first node N1in response to a signal input to a third input terminal103. To this end, the second signal processing unit441-1may include a sixth transistor T6, a seventh transistor T7, and a second capacitor C2.

A first terminal of the second capacitor C2is coupled to the third node N3, and a second terminal thereof is coupled to the seventh transistor T7.

The sixth transistor T6is coupled between the second terminal of the second capacitor C2and the third input terminal103. A gate electrode of the sixth transistor T6is coupled to the third node N3. The sixth transistor T6may be turned on or off depending on the voltage of the third node N3.

The seventh transistor T7is coupled between the second terminal of the second capacitor C2and the first node N1. A gate electrode of the seventh transistor T7is coupled to the third input terminal103. When the second clock signal CLK2is supplied to the third input terminal103, the seventh transistor T7may be turned on to electrically couple the second terminal of the second capacitor C2with the first node N1.

The third signal processing unit451-1may control the voltage of a second node N2in response to the voltage of the third node N3and a signal input to the third input terminal103. To this end, the third signal processing unit451-1may include a fourth transistor T4, a fifth transistor T5, and a first capacitor C1.

The fourth transistor T4and the fifth transistor T5are coupled in series between the first power supply VDD and the third input terminal103. A gate electrode of the fifth transistor T5is coupled to the third node N3. The fifth transistor T5may be turned on or off depending on the voltage of the third node N3.

A gate electrode of the fourth transistor T4is coupled to the third input terminal103. The fourth transistor T4may be turned on when the second clock signal CLK2is supplied to the third input terminal103.

The first capacitor C1is coupled between a common node between the fourth transistor T4and the fifth transistor T5and the second node N2.

The second stage402may have a configuration that is different from that of the first stage401-1, and may be formed of any one of the circuits in accordance with the embodiments described with reference toFIGS. 3 to 12.

Although inFIG. 14the second stage402has been illustrated as having the configuration in accordance with the embodiment ofFIG. 3, this is only for illustrative purposes, and the present disclosure is not limited thereto.

In a stage and in an emission control driver having the same in accordance with embodiments of the present disclosure, a capacitor provided in the stage may be prevented from being charged or discharged while an emission control signal is maintained at a low voltage, whereby the power consumption of a display device may be reduced.

Furthermore, in a stage and an emission control driver having the same in accordance with embodiments of the present disclosure, the voltage of a certain node remains constant during a period in which the emission control signal is supplied. Thereby, the driving reliability may be secured.

It will be understood to those skilled in the art that the present disclosure may be implemented in different specific forms without changing the technical ideas or essential characteristics. Therefore, it should be understood that the exemplary embodiments are only for illustrative purposes and do not limit the bounds of the present invention. It is intended that the bounds of the present disclosure are defined by the accompanying claims, and various modifications, additions and substitutions, which can be derived from the meaning, scope and equivalent concepts of the accompanying claims, fall within the bounds of the present disclosure.