Array of memory cells, methods used in forming an array of memory cells, methods used in forming an array of vertical transistors, and methods used in forming an array of capacitors

A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.

TECHNICAL FIELD

Embodiments disclosed herein pertain to arrays of memory cells, to methods used in forming an array of memory cells, to methods used in forming an array of vertical transistors, to method used in forming an array of vertical transistors, and to methods used in forming an array of capacitors.

BACKGROUND

Memory cells may be or non-volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated therefrom by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. The gate insulator may be capable of being programmed between at least two retentive capacitive states whereby the transistor is non-volatile. Alternately, the gate insulator may not be so capable whereby the transistor is volatile. Regardless, field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate.

A capacitor is another type of electronic component that may be used in a memory cell. A capacitor has two electrical conductors separated by electrically insulating material. Energy as a charge may be electrostatically stored within such material. Depending on composition of the insulator material, that stored field will be volatile or non-volatile. For example, a capacitor insulator material including only SiO2will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a capacitor and/or memory cell. The polarization state of the ferroelectric material can be changed by application of suitable programming voltages and remains after removal of the programming voltage (at least for a time). Each polarization state has a different charge-stored capacitance from the other, and which ideally can be used to write store) and read a memory state without reversing the polarization state until such is desired to be reversed. Less desirable, in some memory having ferroelectric capacitors the act of reading the memory state can reverse the polarization. Accordingly, in such instances, upon determining the polarization state, a re-write of the memory cell is conducted to put the memory cell into the pre-read state immediately after its determination. Regardless, a memory cell incorporating a ferroelectric capacitor ideally is non-volatile due to the bi-stable characteristics of the ferroelectric material that forms a part of the capacitor. Other programmable materials may be used as a capacitor insulator to render capacitors non-volatile.

Capacitors and transistors may of course be used in integrated circuitry other than memory circuitry and fabricated into arrays that may or may not be at least part of a memory array.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention include methods used in forming an array of capacitors, for example as may be used in memory or other integrated circuitry. Embodiments of the invention also encompass methods used in forming an array of memory cells, for example comprising a plurality of vertical transistors that are above a plurality of capacitors. Embodiments of the invention also encompass an array of memory cells independent of method of manufacture. Example embodiments of methods of forming an array of memory cells are first described with reference toFIGS.1-23.

Referring toFIGS.1-3, such show an example substrate construction8comprising an array or array area10that has been fabricated relative to a base substrate11. Substrate11may comprise any of conductive/conductor/conducting, semi conductive/semiconductor/semiconducting, and insulative/insulator/insulating (i.e., electrically herein) materials. Various materials are above base substrate11. Materials may be aside, elevationally inward, or elevationally outward of theFIGS.1-3-depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within base substrate11. Control and/or other peripheral circuitry for operating components within a memory array may also be fabricated and may or may not be wholly or partially within a memory array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. As used in this document, a “sub-array” may also be considered as an array.

An example vertical stack12is above base substrate11. Such comprises transistor material14directly above and directly against a first capacitor electrode material16. Example vertical stack12is also shown as comprising insulator material21(e.g., silicon dioxide and/or silicon nitride). Transistor material14in one embodiment comprises top source/drain region material13directly above channel region material15, and in one such embodiment comprises bottom source/drain region material17directly under channel region material15. Alternately, channel region material15may be directly against first capacitor electrode material16, with an uppermost portion of material16functioning as a bottom/source drain region. Regardless, first capacitor electrode material16comprises one or more conductive materials (intrinsic electrical resistance of 0.0001 to 1.0 ohm·cm), for example elemental tungsten atop conductively-doped polysilicon or atop additional metal material other than elemental tungsten. By way of examples only, materials13,15, and17may comprise one or more of appropriately-doped crystalline semiconductor material, such as one or more of silicon, germanium, and so-called III/V semiconductor materials (e.g., GaAs, InP, GaP, and GaN), with source/drain region materials13and17being sufficiently doped to be conductive and channel region material15being undoped or sufficiently doped to be semiconductive to conduct in an “on” state and to not conduct in an “off” state of the vertical transistors being formed.

A mask20has been formed above vertical stack12. Such is shown as comprising mask lines22extending along a column direction24, for example, along which digitlines (not-yet-shown) will be formed. Mask20may be considered as a first mask20in comparison to an example second mask (not-yet-shown) described below and may be sacrificial (e.g., comprising photoresist and/or hard-masking material). Masks formed herein may be formed using pitch multiplication.

Referring toFIGS.4and5, and in one embodiment, first mask20has been used to subtractively etch (e.g., anisotropically) both transistor material14and thereafter first capacitor electrode material16to form a plurality of walls26horizontally-elongated in column direction24and that individually comprise transistor material14and first capacitor electrode material16(e.g., in an etching step using first mask20in a single common masking step for the etching of materials14and16as shown). The processing shown byFIGS.4and5may cause walls26to be tapered inFIG.5(not shown) whereby the sides of walls26are not vertical, for example being wider at their bottoms than at their tops (not shown).

FIGS.6and7show subsequent removal of first mask20(not shown) and filling of space between walls26with insulating material45(e.g., silicon dioxide and/or silicon nitride).

Referring toFIGS.8and9, a mask28(e.g., a second mask28) has been formed after the forming of first mask20(not shown) and comprises mask lines30that extend along a row direction27in which, in one embodiment, gate lines (not-yet-shown) of vertical transistors will be formed. In one embodiment, walls26are formed before forming such gate lines (not-yet-shown).

FIGS.10-13show using second mask28to subtractively etch (e.g., anisotropically) both transistor material14and thereafter first capacitor electrode material16of walls26to form a plurality of pillars25individually comprising transistor material14and first capacitor electrode material16. In one embodiment and as shown, such has also formed a plurality of trenches32that are individually longitudinally-elongated in and extend along row direction27aside first capacitor electrode material16of pillars25. The processing shown byFIGS.10-13may cause pillars25to be tapered inFIG.12(not shown; and/or inFIG.13as referred to above with respect toFIG.5[not shown]) whereby the sides of pillars25are not vertical, for example being wider at their bottoms than at their tops (not shown). Width of pillars25and spacing there-between is shown as being the same in directions24and27although such need not be so, for example with spacing between pillars25in one or both of directions24and27being less at the tops and/or bottoms of pillar25(not shown).

The above processing is but one example of using a mask (e.g.,28) to subtractively etch both transistor material14and thereafter first capacitor electrode material16to form a plurality of pillars25that individually comprise transistor material14and first capacitor electrode material16(e.g., in an etching step using mask28in a single common masking step for the etching of materials14and16, and regardless of whether an earlier mask [e.g.,20] was used). Alternately, only a single mask may be used to form pillars25(not shown and less ideal).

Referring toFIGS.14and15, a capacitor insulator34(e.g., silicon dioxide, silicon nitride, high-k material, and/or ferroelectric material) has been formed in trenches32aside first capacitor electrode material16of pillars25. A second capacitor electrode material36has been formed in trenches32laterally-outward of capacitor insulator34. Second capacitor electrode material36and first capacitor electrode material16may be of the same composition or of different compositions relative one another. Such may be deposited to collectively line and overfill trenches32followed by planarizing such back at least to tops of mask lines30(e.g., when such remain at least at this point of the example method[s]).

FIGS.16and17show vertical recessing (e.g., by etching) of second capacitor electrode material36(and in one embodiment also capacitor insulator34) to form conductive lines46that are individually longitudinally-elongated horizontally and in individual trenches32. Individual conductive lines46comprise a second capacitor electrode40of individual capacitors42that have been formed. In one embodiment and as shown, individual conductive lines46comprise a shared second capacitor electrode40of immediately-row-adjacent capacitors42(FIG.17) and interconnect individual second capacitor electrodes40longitudinally along immediately-adjacent rows44of capacitors42(FIG.16) (along individual conductive lines46). First capacitor electrode material16of individual pillars25comprises a first capacitor electrode41of individual capacitors42. In some embodiments, capacitors42may be considered as being arrayed in columns99. In one embodiment, conductive lines46have tops48that are below tops50of first capacitor electrode material16. In one embodiment, conductive lines46have bottoms52that are above bottoms54of first capacitor electrode material16. In one embodiment, conductive lines46are directly electrically coupled together, for example as is schematically shown by an interconnect line47whereby, for example, second capacitor electrodes40are common to all capacitors42within array10. Such interconnection may occur during, earlier than, or later than the example processing shown byFIGS.16and17.

A plurality of gate lines62is formed above conductive lines46, for example as is shown inFIGS.18and19. Such show formation of insulator material58(e.g., silicon dioxide and/or silicon nitride) having a top surface59that has been used at least in part to define a bottom of gate lines62. For example,FIGS.18and19show formation of gate insulator60followed by formation of gate lines62that extend along row direction27. By way of example only, gate insulator60may be formed by a conformal deposition followed by an anisotropic spacer-like etch thereof, followed by deposition of conductive material for gate lines62, and followed by an anisotropic spacer-like etch thereof. Alternately, as an example, gate insulator60might not be subjected to an anisotropic spacer-like etch prior to forming the conductive material of gate lines62(not shown). Such are but a couple of examples of forming a plurality of gate lines62above conductive lines46, with gate lines62individually being operatively laterally-proximate channel regions (e.g., defined by channel region material15) of transistor material14of pillars25and extending along row direction27. Example gate lines62are shown as being on two of opposing sides of channel region material15, although such may only be on one side thereof or may be gate-all-around (neither being shown inFIGS.18and19). When on two opposing sides, individual pairs of such gate lines62may be directly electrically coupled together, for example as is schematically shown by a respective interconnect line49. Regardless, transistor material14of individual pillars25and its laterally-proximate gate line(s)62comprise a vertical transistor64.

Referring toFIGS.20-22, mask28(not shown) has been removed, insulator material61(e.g., silicon dioxide and/or silicon nitride) has been formed to fill space between vertical transistors64, and thereafter a plurality of digitlines66has been formed that are individually above gate lines62and extend along column direction24. Digitlines66individually are electrically coupled (e.g., directly electrically coupled) to individual vertical transistor64(e.g., to individual top source/drain regions13). An array of memory cells68has thereby been formed with, in one embodiment, memory cells68individually comprising a single vertical transistor64and a single capacitor42(a 1T-1C memory cell). In one embodiment and as shown, conductive lines46individually are directly under individual gate lines62(FIGS.21and22). In one embodiment, mask28(not shown) comprises sacrificial horizontal mask lines30and that are not removed until after forming gate lines62.

FIGS.22and23schematically show optional inclusion/addition of a select device53(e.g., any suitable select device such as a diode, transistor, etc.) connected to first capacitor electrode41by an interconnect line51.

Processing as described above whereby transistor material and first capacitor electrode material there-below are patterned at the same time (e.g., in an etching step using mask28in a single common masking step for the etching of materials14and16, and regardless of whether an earlier mask [e.g.,20] was used) may reduce the number of critical masks and attendant critical alignments thereof.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

An alternate example method is next described with reference toFIGS.24-37with respect to a construction8aof an array10ain fabrication. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “a” or with different numerals.

FIG.24corresponds in processing sequence to that ofFIG.2, with mask lines22abeing shown with peppering for clarity.FIG.25corresponds in processing sequence to that ofFIG.8. Further, for ease of representation, mask lines30inFIG.25are shown as being of the same width as inFIG.8. Mask lines22ainFIG.24are shown as being one third the width as shown inFIG.2and as being of a different x/y-axis layout. Alternate layouts and widths may be used, for example and by way of example only with mask lines22abeing of the same width and x/y layout as inFIG.24(not shown) and mask lines30inFIG.25being wider than shown. Regardless, and in one embodiment, mask lines30of mask28are wider than mask lines22aof mask20athan in the above-described embodiments and resultant individual pillars25a(at least initially and not-yet-shown) will thereby be of different horizontal cross-sectional shape than that with respect to the first-described embodiments (e.g., being horizontally-elongated [e.g., rectangular] as opposed to an example horizontally square shape as shown by way of example in the first-described embodiments and as will be apparent from the continuing discussion).

FIGS.26-28show subsequent example processing largely corresponding to that described above through and toFIGS.18and19of construction8. Pillars25ahave been formed which in some embodiments may be considered as first pillars25a. Insulator material61has been formed and additionally has then been vertically recessed relative to mask lines30. In some embodiments, insulator material61may be considered as being masking material (e.g., at least part of a masking material) that has been formed aside mask lines30. In one example embodiment and as shown, alternate example conductive lines46ahave been formed that have a trough-like shape (e.g., in a vertical cross-section as shown inFIG.28), and in such one embodiment, with the trough thereof being filled with solid insulator material23(e.g., silicon dioxide and/or silicon nitride.

Referring toFIG.29, masking material63(e.g., silicon carbide) has been formed atop insulator material61aside mask lines30. Such may be formed, for example, by deposition of material63to overfill void space left from the recessing of insulator material61followed by planarizing material63back at least to top surfaces of mask lines30.

Referring toFIG.30, mask lines30(not shown) have been removed and a conformal layer of material90(e.g., silicon nitride) has been deposited to less-than-fill void space in masking material61and/or63resulting from the removal of mask lines30.FIGS.31and32show material90having been subjected to a spacer-like etch to form sidewall-spacer lines65in such void space.

Referring toFIGS.33-35, masking material63and side-wall-spacer lines65have been used to comprise a mask67while etching first pillars25a(not so designated inFIGS.33-35) to bifurcate them into two second pillars70that individually comprise a vertical transistor64a.FIGS.36and37show example subsequent removal of masking material63(not shown) and sidewall-spacer lines65(not shown), followed by formation of insulator material72(e.g., silicon dioxide and/or silicon nitride) and digitlines66. Accordingly, and in some embodiments, capacitors42aand/or memory cells68ahave also been formed.

In one embodiment and as shown, such bifurcating has occurred after forming gate lines62. In one embodiment and as shown, individual gate lines62are operatively laterally-adjacent only one side of the channel region (e.g., material15) of individual vertical transistors64a. Regardless, and in one embodiment, the bifurcating occurs after forming capacitor insulator34and after forming second capacitor electrode material36.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

Another example embodiment method used in forming an array of memory cells is next described with reference toFIGS.38-50. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “b” or with different numerals.

Referring toFIGS.38-40, a plurality of first pillars25bhave been formed that individually comprise first capacitor electrodes41. Sacrificial material29(e.g., silicon dioxide) has been formed laterally about first pillars25b. In one embodiment, an etch-stop material31(e.g. silicon nitride) has been formed atop sacrificial material29.

A plurality of vertical transistors is formed above the sacrificial material and above the first pillars.FIGS.41-44show example formation of second pillars71directly above and that are directly electrically coupled to first pillars25b(e.g., largely analogous to processing described with respect to the first-described embodiments). Second pillars71individually comprise a channel region (e.g., channel region material15) and a top source/drain region (e.g., top source/drain region material13) there-above. In one embodiment and as shown, second pillars71also individually comprise a bottom source/drain region17directly below the channel region and directly against one of first pillars25b.

FIGS.45and46show subsequent example processing largely corresponding to that described above through and toFIGS.18and19of construction8. Mask lines30(not shown) have been removed and insulator material61covers sides and tops of second pillars71, gate insulator60, and gate lines62.FIG.47is a very diagrammatic, reduced-scale, transparent, and perspective representation of construction8bofFIGS.45and46, First pillars25band second pillars71are shown as being circular in horizontal cross-section for clarity and ease of depiction.

Referring toFIG.48, such is a figure like that ofFIG.47but showing example subsequent processing to that shown byFIGS.45-47. Access openings33have been formed through insulator material61and through etch-stop material31(when present). Thereafter, sacrificial material29(not shown) has been removed from being laterally about first capacitor electrodes41(e.g., by isotropic etching selectively relative to materials61,31, and16).

Referring toFIGS.49and50, such show subsequent processing whereby capacitor insulator34and second capacitor electrode material36have been formed. Accordingly, and in one example, second capacitor electrode material36forms a common second capacitor electrode plate40bthat is laterally about first capacitor electrodes41as opposed to being conductive lines running laterally there-adjacent. Capacitors42b(FIG.49) have thereby been formed. Digitlines (not shown) can be formed to directly electrically couple with vertical transistors64as described above with respect to other embodiments. Further, any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, a method used in forming an array (e.g.,10) of memory cells (e.g.,68,68a) comprises forming a vertical stack (e.g.,12) comprising transistor material (e.g.,14) directly above and directly against a first capacitor electrode material (e.g.,16), A mask (e.g.,28,67) is used to suhtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars (e.g.,25,70) that individually comprise the transistor material and the first capacitor electrode material. Capacitors (e.g.,42,42a) are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors (e.g.,64,64a) are formed above the capacitors and that individually comprise the transistor material of the individual pillars. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, a method used in forming an array (e.g.,10) of memory cells (e.g.,68,68a) comprises forming a vertical stack (e.g.,12) comprising transistor material (e.g.,14) directly above and directly against a first capacitor electrode material (e.g.,16). A mask (e.g.,28,67) is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars (e.g.,25,70) that individually comprise the transistor material and the first capacitor electrode material. A capacitor insulator (e.g.,34) is formed aside the first capacitor electrode material of the pillars and a second capacitor electrode material (e.g.,36) is formed laterally-outward of the capacitor insulator. A plurality of gate lines (e.g.,62) is formed above the second capacitor electrode material. Individual of the gate lines extend along a row direction (e.g.,27) and are operatively laterally-proximate channel regions of the transistor material of individual of the pillars. The transistor material of the individual pillars and its laterally-proximate gate line comprising comprise a vertical transistor (e.g.,64). A plurality of digitlines (e.g.,66) is formed and that are individually above the gate lines and extend along a column direction (e.g.,24). Individual of the digitlines are electrically coupled to individual of the vertical transistors. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, a method used in forming an array (e.g.,10) of vertical transistors (e.g.,64, and regardless of whether capacitors and/or memory cells are formed) comprises forming a vertical stack (e.g.,12) comprising transistor material (e.g.,14). Time-spaced first and second masks (e.g.,20and28, respectively) are used to subtractively etch the transistor material to form a plurality of first pillars (e.g.,25a) individually comprising the transistor material. The second mask is formed after the first mask and comprises horizontally-elongated mask lines (e.g.,30). Masking material (e.g.,63) is formed aside the mask lines. The mask lines are removed and sidewall-spacer lines (e.g.,65) are formed in void space in the masking material formed from the removing of the mask lines. The masking material and sidewall-spacer lines are used to comprise a mask (e.g.,67) while etching the first pillars to bifurcate them into two second pillars (e.g.,71) that individually comprise a vertical transistor (e.g.,64a). Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, a method used in forming an array e.g.,10) of capacitors (e.g.,42, and regardless of whether transistors and/or memory cells are formed) comprises using time-spaced first and second masks (e.g.,20and28, respectively) to subtractively etch first capacitor electrode material (e.g.,16) to form a plurality of first pillars (e.g.,25a) individually comprising the first capacitor electrode material. The second mask is formed after the first mask and comprises horizontally-elongated mask lines (e.g.,30). Masking material (e.g.,63) is formed aside the mask lines. The mask lines are removed and sidewall-spacer lines (e.g.,65) are formed in void space in the masking material formed from the removing of the mask lines. The masking material and sidewall-spacer lines comprise a mask (e.g.,67) that is used while etching the first pillars to bifurcate them into two second pillars (e.g.,71) that individually comprise a first capacitor electrode comprising the first capacitor electrode material. A capacitor insulator (e.g.,34) is aside the first capacitor electrode material and a second capacitor electrode material (e.g.,36) is laterally-outward of the capacitor insulator. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, a method used in forming an array (e.g.,10b) of memory cells (e.g.,68) comprises forming a plurality of first pillars (e.g.,25b) individually comprising first capacitor electrodes (e.g.,41). Sacrificial material (e.g.,29) is formed laterally about the first pillars. A plurality of vertical transistors (e.g.,64) is formed above the sacrificial material and above the first pillars. The vertical transistors individually comprise a second pillar (e.g.,71) directly above and directly electrically coupled to the first pillars. The second pillars individually comprise a channel region (e.g., material15) and a top source/drain region (e.g., material13) there-above. After forming the second pillars, the sacrificial material is removed from being laterally about the first pillars. After removing the sacrificial material, a capacitor insulator (e.g.,34) is formed aside the first capacitors of the first pillars and a second capacitor electrode (e.g.,40) is formed laterally-outward of the capacitor insulator. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

Alternate embodiment constructions may result from method embodiments described above, or otherwise. Regardless, embodiments of the invention encompass memory arrays independent of method of manufacture. Nevertheless, such memory arrays may have any of the attributes as described herein in method embodiments. Likewise, the above-described method embodiments may incorporate, form, and/or have any of the attributes described with respect to device embodiments.

In one embodiment, an array (e.g.,10) of memory cells (e.g.,68,68a) comprises a plurality of capacitors (e.g.,42) in rows (e.g.,44) along a row direction (e.g.,27) and in columns (e.g.,99) along a column direction (e.g.,24). The capacitors individually comprise a first capacitor electrode (e.g.,41), a second capacitor electrode (e.g.,40) laterally-outward of the first capacitor electrode, and a capacitor insulator (e.g.,34) between the first and second capacitor electrodes. A plurality of vertical transistors (e.g.,64) is in the rows and columns above the plurality of capacitors. The vertical transistors individually comprise a top source/drain region (e.g., material13), a bottom source/drain region (e.g., material17), and a channel region (e.g., material15) vertically there-between. Individual of the vertical transistors are directly electrically coupled to individual of the first capacitor electrodes. A plurality of gate lines (e.g.,64) are individually operatively laterally-proximate the channel regions along individual of the rows. A plurality of digitlines (e.g.,66) are included and that are individually above the gate lines and are electrically coupled to the top source/drain regions along individual of the columns. A plurality of conductive lines (e.g.,46,46a) are included, that are individually longitudinally-elongated in and extend along the row direction aside and are directly against the capacitor insulator and that are below the gate lines. Individual of the conductive lines comprise the second capacitor electrode of individual of the capacitors. The individual conductive lines comprise a shared of the second capacitor electrodes of immediately-row-adjacent of the capacitors and interconnect the individual second capacitor electrodes longitudinally along immediately-adjacent of the rows. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

The above processing(s) or construction(s) may be considered as being relative to an array of components formed as or within a single stack or single deck of such components above or as part of an underlying base substrate (albeit, the single stack/deck may have multiple tiers). Control and/or other peripheral circuitry for operating or accessing such components within an array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., CMOS under-array). Regardless, one or more additional such stack(s)/deck(s) may be provided or fabricated above and/or below that shown in the figures or described above. Further, the array(s) of components may be the same or different relative one another in different stacks/decks and different stacks/decks may be of the same thickness or of different thicknesses relative one another. Intervening structure may be provided between immediately-vertically-adjacent stacks/decks (e.g., additional circuitry and/or dielectric layers). Also, different stacks/decks may be electrically coupled relative one another. The multiple stacks/decks may be fabricated separately and sequentially (e.g., one atop another), or two or more stacks/decks may be fabricated at essentially the same time.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

Further, “directly above”, “directly below”, and “directly under” require at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Also, use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Analogously, use of “below” and “under” not preceded by “directly” only requires that some portion of the stated region/material/component that is below/under the other be elevationally inward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).

Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Where one or more example composition(s) is/are provided for any material, that material may comprise, consist essentially of, or consist of such one or more composition(s). Further, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.

Any use of “row” and “column” in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features and along which components have been or may be formed. “Row” and “column” are used synonymously with respect to any series of regions, components, and/or features independent of function. Regardless, the rows may be straight and/or curved and/or parallel and/or not parallel relative one another, as may be the columns. Further, the rows and columns may intersect relative one another at 90° or at one or more other angles (i.e., other than the straight angle).

The composition of any of the conductive/conductor/conducting materials herein may be metal material and/or conductively-doped semiconductive/semi conductor/semiconducting material. “Metal material” is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compound(s).

Herein, any use of “selective” as to etch, etching, removing, removal, depositing, forming, and/or formation is such an act of one stated material relative to another stated material(s) so acted upon at a rate of at least 2:1 by volume. Further, any use of selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials at a rate of at least 2:1 by volume for at least the first 75 Angstroms of depositing, growing, or forming.

Unless otherwise indicated, use of “or” herein encompasses either and both.

CONCLUSION

In some embodiments, a method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars.

In some embodiments, a method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. A capacitor insulator is formed aside the first capacitor electrode material of the pillars and a second capacitor electrode material is formed laterally-outward of the capacitor insulator. A plurality of gate lines is formed above the second capacitor electrode material. Individual of the gate lines extend along a row direction and are operatively laterally-proximate channel regions of the transistor material of individual of the pillars. The transistor material of the individual pillars and its laterally-proximate gate line comprise a vertical transistor. A plurality of digitlines is formed that are individually above the gate lines and extend along a column direction. Individual of the digitlines are electrically coupled to individual of the vertical transistors.

In some embodiments, a method used in forming an array of vertical transistors comprises forming a vertical stack comprising transistor material. Time-spaced first and second masks are used to subtractively etch the transistor material to form a plurality of first pillars that individually comprise the transistor material. The second mask is formed after the first mask and comprises horizontally-elongated mask lines. Masking material is formed aside the mask lines. The mask lines are removed and sidewall-spacer lines are formed in the void space in the masking material formed from the removal of the mask lines. The masking material and sidewall-spacer lines are used to comprise a mask while etching the first pillars to bifurcate them into two second pillars that individually comprise a vertical transistor.

In some embodiments, a method used in forming an array of capacitors comprises using time-spaced first and second masks to subtractively etch first capacitor electrode material to form a plurality of first pillars that individually comprise the first capacitor electrode material. The second mask is formed after the first mask and comprises horizontally-elongated mask lines. Masking material is formed aside the mask lines. The mask lines are removed and form sidewall-spacer lines in the void space in the masking material formed from the removal of the mask lines. The masking material and sidewall-spacer lines are used to comprise a mask while etching the first pillars to bifurcate them into two second pillars that individually comprise a first capacitor electrode comprising the first capacitor electrode material. A capacitor insulator is formed aside the first capacitor electrode material and a second capacitor electrode material is formed laterally-outward of the capacitor insulator.

In some embodiments, a method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. Time-spaced first and second masks are used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. The second mask is formed after the first mask and comprises mask lines that extend along a row direction. The subtractive etch using the second mask comprising the mask lines forms a plurality of trenches that are individually longitudinally-elongated in and extend along the row direction aside the first capacitor electrode material of the pillars. A capacitor insulator is formed in the trenches aside the first capacitor electrode material of the pillars and a second capacitor electrode material is formed in the trenches laterally-outward of the capacitor insulator to form conductive lines that are individually in individual of the trenches. Individual of the conductive lines comprise a second capacitor electrode of individual capacitors. The individual conductive lines comprise a shared of the second capacitor electrodes of immediately-row-adjacent of the capacitors and interconnect the individual second capacitor electrodes longitudinally along immediately-adjacent rows of the capacitors. A plurality of gate lines is formed above the conductive lines. Individual of the gate lines are operatively laterally-proximate channel regions of the transistor material of the pillars and extend along the row direction. The transistor material of the individual pillars and its laterally-proximate gate line comprise a vertical transistor. A plurality of digitlines is formed that are individually above the gate lines and extend along a column direction. The digitlines individually are electrically coupled to individual of the vertical transistors.

In some embodiments, a method used in forming art array of memory cells comprises forming a plurality of first pillars individually comprising first capacitor electrodes. Sacrificial material is formed laterally about the first pillars. A plurality of vertical transistors is formed above the sacrificial material and above the first pillars. The vertical transistors individually comprise a second pillar directly above and directly electrically coupled to the first pillars. The second pillars individually comprise a channel region and a top source/drain region there-above. After forming the second pillars, the sacrificial material is removed from being laterally about the first pillars. After removing the sacrificial material, a capacitor insulator is formed aside the first capacitors of the first pillars and a second capacitor electrode is laterally-outward of the capacitor insulator.

In some embodiments, an array of memory cells comprises a plurality of capacitors in rows along a row direction and in columns along a column direction. The capacitors individually comprise a first capacitor electrode. A second capacitor electrode is laterally-outward of the first capacitor electrode. A capacitor insulator is between the first and second capacitor electrodes. A plurality of vertical transistors is in the rows and columns above the plurality of capacitors. The vertical transistors individually comprise a top source/drain region, a bottom source/drain region, and a channel region vertically there-between. Individual of the vertical transistors are directly electrically coupled to individual of the first capacitor electrodes. A plurality of gate lines individually is operatively laterally-proximate the channel regions along individual of the rows. A plurality of digitlines individually are above the gate lines and electrically coupled to the top source/drain regions along individual of the columns. A plurality of conductive lines individually are longitudinally-elongated in and extend along the row direction aside and are directly against the capacitor insulator and that are below the gate lines. Individual of the conductive lines comprise the second capacitor electrode of individual of the capacitors. The individual conductive lines comprise a shared of the second capacitor electrodes of immediately-row-adjacent of the capacitors and interconnect the individual second capacitor electrodes longitudinally along immediately-adjacent of the rows.