Clocking synchronization method and apparatus

Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.

TECHNICAL FIELD

The present disclosure relates to the fields of computing and communication. More particularly, the present disclosure relates to clocking synchronization between communication nodes, e.g., between Peripheral Component Interconnect Express (PCIe) host and endpoint communication nodes. In various embodiments, clocking synchronization comprises spread spectrum clocking (SSC) synchronization.

BACKGROUND

Many communication standards require SSC on their clocks in order to reduce peak Electro Magnetic Interference (EMI) or Radio Frequency Interference (RFI) to other platform components such as wireless modems, memory or neighboring devices that are prone to this radiation and potentially leads to malfunction. However, with SSC enabled, input/output (I/O) interfaces often call for a common reference clock (Refclk) architecture, in which every communication node gets a copy with a set skew spec. For example, for PCIe, a widely employed serial communication standard, its Refclk is specified at 100 MHz+/−300 Parts-Per-Million (PPM) with 0 to −0.5% SSC spread with modulation range of 30 to 33 KHz to mitigate EMI/RFI. The skew is to be less than 12 ns between host/device. The requirement is difficult to achieve. One solution to compensate this servo phase-locking mechanism with common Refclk is to add elastic buffers, with large buffer depth to mitigate maximum peak-to-peak jitter, and periodically broadcast SKIP Ordered Sets that are ignored by the receiver. However, such solution adds cost in terms of latency, power and die area.

DETAILED DESCRIPTION

To address the challenges discussed in the background section, apparatuses and methods associated with clocking synchronization are disclosed herewith In various embodiments, an endpoints/slave communication node synchronizes its clock to the host communication node during clock training, prior to link training. In various embodiments, during clock training, the endpoint/slave communication node synchronizes its clocking to the host communication node, after performing static phase measurement of the recovered clock of the host communication node. During static phase measurement, parts-per-million (PPM) correction for use during subsequent clocking synchronization is determined. During subsequent clocking synchronization, the determined PPM correction is applied. For SSC synchronization, additionally, SSC pattern from the host communication node is continuously monitored, and SSC pattern of the endpoint/slave communication node is adjusted to sync the subsequent generated SSC with the SSC of the host communication node.

Aspects of the disclosure are disclosed in the accompanying description. Alternate embodiments of the present disclosure and their equivalents may be devised without parting from the spirit or scope of the present disclosure. It should be noted that like elements disclosed below are indicated by like reference numbers in the drawings.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The description may use the phrases “in an embodiment,” or “In some embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.

Referring now toFIG. 1, wherein an overview of a computing device having communication nodes incorporated with the clocking synchronization technology of the present disclosure, in accordance with various embodiments, is illustrated. As shown, computing system100includes communication nodes102and152. In various embodiments, computing system100may be a computing platform or a computing device, where communication nodes102and152are physically coupled to each other, via a communication bus, e.g., communication node102being a PCIe host and communication node152being a PCIe endpoint, coupled with each other via a PCIe bus. In other embodiments, computing system100may be a network of computing devices where communication nodes102and152are computing devices communicatively coupled with each other over a wired connection, e.g., Ethernet, or a wireless connection, e.g., Zigbee, Bluetooth®, WiFi, or 4G/5G.

Regardless of the embodiments, each of communication nodes102and152may be viewed as having a plurality of layers, application layer112/162, transaction layer114/164, data link layer116/166, and physical layer118/168. Application layer112/162is an abstraction layer that specifies the shared communications protocols and interface methods used by communication nodes102and152, e.g., PCIe protocols and interface methods or Transmission Control Protocol (TCP) and Internet Protocol (IP) protocols and interface methods. The Transaction layer114/164is the starting point in the assembly of outbound transmit (Tx) Transaction Layer Packets (TLPs), and the end point for disassembly of inbound receive (Rx) TLPs. Data link layer116/166provides the functional and procedural means to transfer data packets between communication nodes102and152and might provide the means to detect and possibly correct errors that may occur in physical layer118/168. Physical layer118/168consists of the electronic circuits for transmitting and receiving raw data bits. The bit stream may be grouped into code words or symbols, and converted to a physical signal that is transmitted over a transmission medium, which may be a wire or free space.

In various embodiments, physical layers118/168can be further considered as having logical sub-block122/172and electrical sub-block124/174. Logical sub-block122/172includes circuitry for performing various logical operations, such as clock/link training and management132/182, encoding, error correction, and so forth. Electrical sub-block124/174includes Tx and Rx circuitry for performing various physical operations such as carrier sensing, collision detection, signal modulation, and so forth. In various embodiments, clock/link training and management132/182may be performed at initial bring-up of a host device, at 0 PPM event detection, or at system initiated flow after host bring up, such as online bring-up of a new endpoint or host socket.

In various embodiments, clock/link training and management132/182includes the clocking synchronization technology140of the present disclosure. During the clock training period, prior to link training, communication node152may synchronize its clocking to that of communication node102. As alluded to earlier, communication node152first performs static phase measurement of the recovered clock of communication node102, including measurement of PPM and determination of PPM correction to be made during subsequent clocking synchronization. Thereafter, communication node152synchronizes its clocking to communication node102. In various embodiments, clocking synchronization comprises SSC synchronization. For these embodiments, communication node102provides communication node152with SSC pattern, and communication node152continuously monitors the SSC pattern of communication node102, and adjusts its own SSC pattern, applying determined PPM correction, to synchronize its SSC to communication node102. In other embodiments, PPM correction may also be performed independent of SSC synchronization, e.g., to compensate for different temperature drift.

In a first set of embodiments, to synchronize SSC, communication nodes102and152use the same reference clock frequency, but the SSC is generated independently within input/output (I/O) clocking PPM specification. For these embodiments, the Rx of communication node152detects 0 PPM or slope change events, and generates in response, the SSC sync signal to commence SSC synchronization. The Rx of communication node152further generates static offset to compensate for reference clocks PPM misalignment. In a second set of embodiments, to synchronize SSC, a message based approach is employed by communication nodes102and152instead, with communication node102providing 0 PPM event messages to communication node152. In still a third set of embodiments, the master phase lock loop (PLL) of communication node102is charged with the responsibility of sending the SSC sync signal to communication node152.

These and other aspects of the clocking synchronization technology of the present disclosure will be further described below with references toFIGS. 2-6.

Referring now toFIG. 2, wherein an overview of an example clock and link training process, according to various embodiments, is illustrated. As shown, for the illustrated embodiments, example clock and link training process200between a host communication node (or simply, Host), and an endpoint/slave communication node (or simply endpoint or EP), e.g., communication nodes102and152ofFIG. 1, includes operations performed at stages202-214. In alternate embodiments, process200may include more or less operations, or with some of the operations performed in different order.

Process200starts at stage202. At stage202, Host and EP exchanges clock training handshake. On successful completion of the clock training handshake, process200proceeds to stage204. At stage204, Host instructs EP to start static phase measurement (SSPM). Next, at stage206, Host sends to EP clock pattern for clock training. On receipt, in addition to performing clock training, EP further detects for static phase, measures and determines PPM correction for use during subsequent clocking synchronization. At completion of static phase and PPM measurement, and PPM correction determination, at stage208, EP notifies Host with an acknowledgement (ACK).

Next, at stage210, Host instructs EP to start clocking synchronization (STC) while continuing with clock training. For SSC synchronization, Host further provides EP with SSC pattern. In response, EP continuously monitors the Host's SSC pattern, adjusts its own SSC patterns, applying PPM correction, and synchronizes its SSC to Host. On completion of clocking synchronization and clock training, at stage212, EP notifies Host with an acknowledgement (ACK).

Next, at stage214, Host and EP jointly perform link training.

Referring now toFIG. 3, wherein an overview of example transmit (Tx) and receive (Rx) clocks generation and distribution for transmitting data and moving Rx data to local clock domain, according to various embodiments, is illustrated. Example Tx and Rx clocks generation and distribution for transmitting data and moving Rx data to local clock domain are illustrated in the context of a set of serial communication embodiments. For the illustrated embodiments, each serial communication node, e.g., a PCIe host or endpoint, which may be communication node102or152ofFIG. 1, includes data serializer302, data deserializer308, Tx clock distribution circuitry304and Rx clock distribution circuitry, coupled with each other as shown.

In various embodiments, Tx clock distribution circuitry304is arranged to generate Tx clock, based on a received digital clock (dcoout). Similarly, Rx clock distribution circuitry306is arranged to generate Rx clock, based on the received digital clock (dcoout). Serializer302is arranged to serialize the Tx data for transmission (serdata) using Tx clock. Deserializer302is arranged to deserialize the received data and output Rx data, using Rx clock.

Referring now toFIG. 4, wherein recovered clock based SSC synchronization, according to various embodiments, is illustrated. As described earlier, an endpoint/slave communication node synchronizing its SSC to a host communication node, recovers the host's clock from the incoming data stream, and performs static phase measurement during clock training, including PPM measurement and correction determination, to be applied during subsequent SSC synchronization. As typical SSC modulating frequency is 30 KHz to 33 KHz, initial lock sync can take ˜30 us. To reduce this latency, during an initial clock training interval402, training pattern, can be sent from the host communication node to the endpoint/slave communication node at higher modulating frequency with reduced SSC amplitude (For example −100 PPM down spread at 1 MHz). The SSC amplitude may be further reduced in later training intervals404and406. Once SSC training with reduced SSC amplitude and higher modulating frequency completed, upon acknowledgement from EP, host can revert back to functional SSC modulating frequency, i.e., 30 KHz to 33 KHz, and amplitude, i.e., 5000 ppm in this example, interval406.

In various embodiments, an endpoint communication node may start tracking recovered clock from a host communication node, upon receiving STSSC (STart Spread SynC) message during the initial training interval402. The host communication node may keep sending SSC pattern until receiving the ACK message, as earlier described. In various embodiments, an endpoint communication node may further take into account of flight delay of the ACK message for switching to functional SSC pattern. In other embodiments, where modulation frequency and amplitude are the same as the functional SSC pattern, the endpoint communication node may not need to account for the flight delay of the ACK message before switching to link training.

Referring now toFIGS. 5a-5f, wherein component views of various communication nodes equipped with the clocking synchronization technology of the present disclosure, according to various SSC embodiments, are illustrated.FIGS. 5a-5billustrate the first set of embodiments, where 0 PPM or slop change events in an SSC pattern of the host communication node (on which the SSC sync signal is based) are detected by the endpoint/slave communication node.FIGS. 5c-5dillustrate the second set of embodiments, based at least in part on the provision of 0 PPM event messages (on which the SSC sync signal is based) from the host communication node to the endpoint communication node.FIGS. 5e-5fillustrate the third set of embodiments, based at least in part on the provision of the SSC sync signal from the master PLL of a host communication node to an endpoint communication node.FIGS. 5a-5bwill be first described, and thenFIGS. 5c-5fwill be described in terms of their differences fromFIGS. 5a-5b.

As illustrated inFIGS. 5a-5b, a communication node500a/500bincludes clock/link training and management logic502, control logic and phase/frequency lock detector504, clock data recovery (CDR)506, auxiliary loop phase frequency detector/time digital converter (PFD/TDC), static phase measurement (SPM) & SSC detection/controller unit510, local PLL512and divider528, coupled to each other as shown. In various embodiments, local PLL512includes main loop PFD/TDC524, fractional modulator514, SSC modulator516, feed forward correction (FFC)518, loop filter520and digitally controlled oscillator/voltage controlled oscillator (DCO/VCO)522, coupled to each other as shown.

Clock/link training and management logic502is arranged to manage the overall clock/link training process, e.g., the clock/link training process200. Control logic and phase/frequency lock detector504is arranged to detect for phase/frequency lock. CDR506is arranged to recover the clock signal from the incoming data stream, e.g., a serial data (serdata) stream. Auxiliary loop PFD/TDC508is arranged to detect and output signals indicating the phase difference between the clock recovered from the incoming data stream, and the clock of communication node500a. SPM & SSC detection/controller unit510is arranged to determine the static offset in the recovered clock signal. Local PLL512is arranged to apply PPM and fractional corrections to the generation of the SSC, and synchronize the generated SSC with the host communication node. Divider528is arranged to divide and provide local PLL's SSC output to auxiliary loop PFD/TDC508.

In the embodiments ofFIG. 5a, main loop PFD/TDC524is arranged to receive and forward reference clock (refclk) to FFC518. Fractional modulator514is arranged to receive fractional modulation pattern data and control signal from SPM & SSC detection/controller unit510and SSC pattern data from SSC modulator516, and apply fractional modulation to the fractional modulation pattern data. Fractional modulator514outputs the fractionally modulated pattern data to FFC518and divider526. SSC modulator516is arranged to receive SSC enable and SSC pattern data and control signals from SPM & SSC detection/controller unit510, and output SSC pattern data for fractional modulator514. FFC518is arranged to receive Refclk from main loop PFD/TDC524, PPM corrections from SPM & SSC detection/controller unit510and fractional correction from fractional modulator514, and apply the PPM correction and fractional correction to Refclk. FFC518outputs the PPM and fractional corrected phase error to loop filter520. Loop filter520is arranged to filter the phase error, allowing only the desired frequency band to pass through to DCO/VCO522. DCO/VCO is arranged to receive the pass through component of Refclk, and generates the output digital clock (dcoout), which is also feedback to main loop PFD/TDC524via divider526.

In various embodiments, during clock training period, frequency/phase detection includes determination of static offset of the recovered clock signal. SSC synchronization training is accomplished by sending initial SSC pattern over data lanes. SPM & SSC detection/controller unit510detects 0 PPM or slope change events and provides SSC enable to SSC modulator516in local PLL512.

In various embodiments, during clock training, transmitted data can be at lower frequency with integer multiples of intended transmission (e.g., if 10 GHz is the intended operational transmission frequency, the transmission frequency during clock training can be at 1 GHz).

In various embodiments, initially local PLL loop512is closed with local reference clock Refclk, and FFC518is set to zero. Upon initial lock acquisition based on Refclk, PPM differences between DCO/VCO and the recovered clock is determined using Aux Loop PFD/TDC508during Start Static Phase Measurement (SSPM) sequence. Measured static phase is then translated and provided to FFC518to compensate for PPM difference. As described earlier, clock pattern is continuously sent by the host communication node until it receives acknowledgement from the endpoint/slave communication node.

Main difference between the embodiments ofFIGS. 5aand 5bis, for the embodiments ofFIG. 5a, SSC modulation is through feedback divider526in local PLL512, whereas for the embodiments ofFIG. 5b, SSC modulation is through direct control of DCO/VCO522.

FIGS. 5c-5dillustrate a set of alternative message based embodiments. In these embodiments, communication node500c/500dis similarly constituted as communication node500a/500bhaving clock/link training and management logic502, control logic and phase/frequency lock detector504, CDR506, auxiliary loop PFD/TDC, SPM & SSC detection/controller unit510, local PLL512and divider528, coupled to each other as shown. Further, local PLL512includes main loop PFD/TDC524, fractional modulator514, SSC modulator516, FFC518, loop filter520and DCO/VCO522, coupled to each other as shown. Elements502-522are similarly constituted, and arranged to perform the tasks as earlier described for the embodiments ofFIGS. 5a-5b.

However, in the message base embodiments ofFIGS. 5c-5d, communication node500c/500dfurther includes endpoint controller530, arranged to receive from the host communication node 0 PPM indicator messages (in lieu of detecting for such events by SPM & SSC detection/controller unit510). In response, endpoint controller530generates the SSC sync signal for SPM& SSC detection/controller unit510, which in turn, generates the SSC enable signal for SSC modulator516of local PLL512as earlier described.

In these embodiments, training packets can still be similar based on initial clock pattern to remove PPM differences between the host and endpoint communication nodes, if the Refclks are independent. While the additional endpoint controller530to receive the 0 PPM event messages is additionally required, the complexity of SPM & SSC detection/controller unit510may be reduced, as slope change detection or 0 PPM detection is not needed in SPM & SSC detection/controller unit510.

Similarly, the main difference between the embodiments ofFIGS. 5cand 5dis, for the embodiments ofFIG. 5c, SSC modulation is through feedback divider526in local PLL512, whereas for the embodiments ofFIG. 5d, SSC modulation is through direct control of DCO/VCO522.

FIGS. 5e-5fillustrate yet another set of alternate SSC sync signal embodiments. In these embodiments, communication node500e/500fis similarly constituted as communication nodes500a/500band500c/500dhaving clock/link training and management logic502, control logic and phase/frequency lock detector504, CDR506, auxiliary loop PFD/TDC, SPM & SSC detection/controller unit510, local PLL512and divider528, coupled to each other as shown. Further, local PLL512includes main loop PFD/TDC524, fractional modulator514, SSC modulator516, FFC518, loop filter520and DCO/VCO, coupled to each other as shown. Elements502-522are similarly constituted, and arranged to perform the tasks as earlier described for the embodiments ofFIGS. 5a-5band 5c-5d.

However, in these SSC sync signal base embodiments, SPM & SSC detection/controller unit510of communication node500e/500fis arranged to receive SSC sync signal534from the PLL of the host communication node, via a sideband channel between the two communication nodes. SSC Sync signal534is generated by the master PLL of host communication node, and transmitted at the SSC frequency rate to endpoint/slave communication node500e/500f. In various embodiments, the SSC sync signal534can be of pulse form whenever SSC enabled or 0 PPM event occurred.

Similar to the embodiments ofFIGS. 5c-5d, training packets can still be similar based on initial clock pattern to remove PPM differences between the host and endpoint communication nodes, if the Refclks are independent. These embodiments require the additional sideband interface for the SSC sync signal534, however, the complexity of SPM & SSC detection/controller unit510may be reduced, as slope change detection or 0 PPM detection is not needed in SPM & SSC detection/controller unit510. Further, as withFIGS. 5aand 5b, or5cand5d, the main difference between the embodiments ofFIGS. 5eand 5fis, for the embodiments ofFIG. 5e, SSC modulation is through feedback divider526in local PLL512, whereas for the embodiments ofFIG. 5f, SSC modulation is through direct control of DCO/VCO.

Further, in some embodiments, among all three sets of embodiments, the designated “master” host may have a fail-over mode. For these embodiments, the host containing the master PLL for SSC Sync can fail, and the system can dynamically designate a new device to be the host. Accordingly, the PPM correction logic is further provided with holdover detection logic to maintain current PPM and SSC profile until the new master can be designated by the platform.

Referring now toFIG. 6, wherein an example clocking synchronization process, according to various SSC embodiments, is illustrated. As shown, for the illustrated embodiments, SSC synchronization process600includes operations performed at blocks602-620. In various embodiments, the operations may be performed by the corresponding circuit elements of a communication node earlier described with references toFIGS. 5a-5f.

Process600starts at block602. At block602, attempt is made to acquire the PLL lock by a communication node using a local reference clock, while performing static phase measurement during a clock training period. At block604, a determination is made on whether the PLL lock is acquired. If a result of the determination at block604is negative, process600returns to block602, where attempt to acquire the PLL lock continues. Eventually, when the result of the determination at block604is affirmative, process600proceeds to block606.

At block606, an auxiliary loop with a recovered clock from a CDR of the endpoint communication node is added for PPM measurement and correction. Next, at block608, a determination is made on the PPM training status. If a result of the determination at block606indicates PPM training is not completed, process600returns to block606, where PPM measurement and correction continues. Eventually, when the result of the determination at block608indicates PPM training complete, process600proceeds to either block610,614or618to perform SSC synchronization.

Process600proceeds from block608to block610if SSC synchronization is based on detecting 0 PPM or slope change events in the recovered clock. At block610, the endpoint communication node locks on to the initial SSC pattern transmitted by the host communication node. Next, at block612, the endpoint communication node enables local SSC modulation when static phase offset/slop change matches. From block612, process600proceeds to block620, where the endpoint communication node continuously monitors and makes adjustment so its SSC pattern sync up with the SSC pattern of the host communication node. For these embodiments, continuous monitoring includes continuous detection for 0 PPM or slope event events in the recovered clock.

Process600proceeds from block608to block618if SSC synchronization is based on a SSC sync signal provided by the master PLL of the host communication node. At block618, the endpoint communication node enables local SSC modulation when the master PLL SSC sync signal arrives. From block618, process600proceeds to block620, where the communication node continuously monitors and makes adjustment so its SSC pattern sync up with the SSC pattern of the host communication node. For these embodiments, continuous monitoring includes continuous monitoring for the SSC sync signal from the master PLL of the host communication node.

Process600proceeds from block608to block614if SSC synchronization is based on 0 PPM event messages (or packets). At block614, the endpoint communication node enables local SSC modulation after compensating for SSC enable detection from the transmitter of the counterpart communication node. From block614process600proceeds to block620, where the endpoint communication node continuously monitors and makes adjustment so its SSC pattern sync up with the SSC pattern of the host communication node. For these embodiments, continuous monitoring includes continuous monitoring for the 0 PPM event messages (or packets) from the host communication node.

Referring now toFIG. 7, wherein an example computing platform that may be suitable for use to practice the present disclosure, according to various embodiments, is illustrated. As shown, computing platform700may include one or more system-on-chips (SoCs)702, ROM703and system memory704. Each SoCs702may include one or more processor cores (CPUs), one or more graphics processor units (GPUs), one or more accelerators, such as computer vision (CV) and/or deep learning (DL) accelerators. ROM703may include basic input/output system services (BIOS)705. CPUs, GPUs, and CV/DL accelerators may be any one of a number of these elements known in the art. Similarly, ROM703and BIOS705may be any one of a number of ROM and BIOS known in the art, and system memory704may be any one of a number of volatile storage known in the art.

Additionally, computing platform700may include persistent storage devices706. Example of persistent storage devices706may include, but are not limited to, flash drives, hard drives, compact disc read-only memory (CD-ROM) and so forth. Further, computing platform700may include one or more input/output (I/O) interfaces708to interface with one or more I/O devices720. Example I/O devices may include, but are not limited to, display, keyboard, cursor control and so forth. Computing platform700may also include one or more communication interfaces710(such as network interface cards, modems and so forth). Communication devices may include any number of communication devices known in the art. Examples of communication devices may include, but are not limited to, networking interfaces for Bluetooth®, Near Field Communication (NFC), WiFi, Cellular communication (such as LTE 4G/5G) and so forth. The elements may be coupled to each other via system bus711, which may represent one or more buses. In the case of multiple buses, they may be bridged by one or more bus bridges (not shown).

Each of these elements may perform its conventional functions known in the art. In particular, ROM703may include BIOS7405having a boot loader. System memory704and mass storage devices706may be employed to store a working copy and a permanent copy of the programming instructions implementing the operations associated with one or more operating systems and/or application, collectively referred to as computational logic722. The various elements may be implemented by assembler instructions supported by processor core(s) of SoCs702or high-level languages, such as, for example, C, that can be compiled into such instructions.

In various embodiments, bus711may include one or more PCIe buses. One or more of SoC702, ROM703, memory704, persistent storage706, communication interface710, and I/O device interfaces708may be a PCIe host or endpoint communication node, incorporated with the clocking synchronization technology of the present disclosure, as earlier described with references toFIGS. 1-6.

As will be appreciated by one skilled in the art, the present disclosure may be embodied as methods or computer program products. Accordingly, the present disclosure, in addition to being embodied in hardware as earlier described, may take the form of an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to as a “circuit,” “module” or “system.” Furthermore, the present disclosure may take the form of a computer program product embodied in any tangible or non-transitory medium of expression having computer-usable program code embodied in the medium.FIG. 8illustrates an example computer-readable non-transitory storage medium that may be suitable for use to store instructions that cause an apparatus, in response to execution of the instructions by the apparatus, to practice selected aspects of the present disclosure. As shown, non-transitory computer-readable storage medium802may include a number of programming instructions804. Programming instructions804may be configured to enable a device, e.g., computing platform700, in response to execution of the programming instructions, to implement (aspects of) one or more operating systems and/or applications. In alternate embodiments, programming instructions804may be disposed on multiple computer-readable non-transitory storage media802instead. In still other embodiments, programming instructions804may be disposed on computer-readable transitory storage media802, such as, signals.

Thus various example embodiments of the present disclosure have been described including, but are not limited to:

Example 1 is a communication node, comprising: a phase lock loop (PLL) arranged to generate a clock; a phase frequency detector (PFD) coupled to the PLL to determine parts-per-million (PPM) differences between the PLL and a recovered clock, during a start static phase measurement (SSPM) sequence of a clock training period; and a static phase measurement (SPM) controller coupled to the PLL and the auxiliary loop PFD, and arranged to measure static phase of the recovered clock, receive the PPM differences determined, and provide PPM correction to the PLL to compensate for the PPM differences determined during subsequent clocking synchronization.

Example 2 is example 1, wherein the clocking synchronization comprises spread spectrum clocking (SSC) synchronization; the PLL includes a SSC modulator; and the SPM controller is further arranged to detect a 0 PPM or slope change event in the recovered clock, and in response to a detection of the 0 PPM event, provide a SSC enable signal to the SSC modulator.

Example 3 is example 2, wherein the SPM controller is further arranged to provide SSC pattern data to the SSC modulator; and wherein the SSC modulator generates SSC adjustments, based at least in part on the SSC pattern data.

Example 4 is example 2, wherein the PLL further comprises a digitally controlled oscillator (DCO), and wherein to determine the PPM differences between the recovered clock and the PLL, the auxiliary loop PFD determines the PPM differences between the DCO and the recovered clock.

Example 5 is example 4, wherein the PLL generates the SSC via control of the DCO by the SSC modulator.

Example 6 is example 4, wherein the PLL includes a feedback divider coupled to the DCO; and the PLL generates the SSC using the feedback divider.

Example 7 is example 2 further comprising a local controller to receive 0 PPM event messages from another communication node, and in response to the receipt, generates a SSC sync signal for the SPM controller; wherein the other communication node is a host, and the communication node is an endpoint.

Example 8 is example 2, wherein the SPM controller is further arranged to receive a SSC sync signal from another communication node; wherein the other communication node is a host, and the communication node is an endpoint.

Example 9 is any one of examples 1-8, wherein the PLL is initially closed with a local reference clock (Refclk), and the PLL further comprises a feed forward correction block to receive and apply the PPM correction to compensate for the PPM differences determined.

Example 10 is any one of examples 1-8, wherein the PLL further comprises a fractional modulator; wherein the SPM controller is further arranged to provide factional modulation pattern data to the fractional modulator; and wherein the fractional modulator is arranged to generate fractional correction, based at least in part on factional modulation pattern data.

Example 11 is example 9 or 10, wherein the communication node is a peripheral component interconnect express (PCIe) communication node.

Example 12 is a method for communication, comprising: performing, by an endpoint communication node, clock training handshake with a host communication node; entering, by the endpoint communication node, a clock training period, on successful performance of the clock training handshake; entering, by the endpoint communication node, a start static phase measurement (SSPM) sequence of clock training period, and receiving clocking pattern from the host communication node; and processing, by the endpoint communication node, the clocking pattern to determine parts-per-million (PPM) differences with the host communication node, to be applied to compensate for the PPM differences determined during subsequent clocking synchronization.

Example 13 is example 12, wherein clocking synchronization comprises spread spectrum clocking (SSC) synchronization, and the clocking pattern comprises SSC pattern; wherein the method further comprises: locking, by the endpoint communication node, onto the SSC pattern; enabling, by the endpoint communication node, local SSC modulation when static phase offset or slope change matches; and monitoring, by the endpoint communication node, continuously the SSC pattern, and adjusting its SSC pattern to match the monitored SSC pattern for subsequent generation of SSC signals.

Example 14 is example 12, wherein clocking synchronization comprises spread spectrum clocking (SSC) synchronization, and the clocking pattern comprises SSC pattern; wherein the method further comprises: enabling, by the endpoint communication node, local SSC modulation when a SSC sync signal arrives; and monitoring, by the endpoint communication node, continuously the SSC pattern, and adjusting its SSC pattern to match the monitored SSC pattern for subsequent generation of SSC signals.

Example 15 is example 12, wherein clocking synchronization comprises spread spectrum clocking (SSC) synchronization, and the clocking pattern comprises SSC pattern; wherein the method further comprises: enabling, by the endpoint communication node, local SSC modulation after compensating for SSC enable detection; enabling, by the endpoint communication node, local SSC modulation when static phase offset matches; and monitoring, by the endpoint communication node, continuously the SSC pattern, and adjusting its SSC pattern to match the monitored SSC pattern for subsequent generation of SSC signals.

Example 16 is any one of examples 12-15, wherein the endpoint communication node is a peripheral component interconnect express (PCIe) endpoint communication node.

Example 17 is a communication node, comprising: a physical layer having a logical sub-block, and an electrical sub-block; wherein the logical sub-block includes clock and link training and management logic arranged to: perform clock training handshake with an endpoint communication node; instruct the endpoint communication node to start static phase measurement as part of the clock training, on successful completion of the clock training handshake; provide clock pattern to the endpoint communication node until receipt of an acknowledgement from the endpoint communication node; and instruct the endpoint communication node to start clocking synchronization, on receipt of the acknowledgment.

Example 18 is example 17, wherein clocking synchronization comprises spread spectrum clocking (SSC) synchronization; the clock and link training and management logic is further arranged to provide the endpoint communication node with SSC pattern, on instructing endpoint communication node to start SSC synchronization; wherein the acknowledgement is a first acknowledgment; and wherein the clock and link training and management logic is arranged to provide the endpoint communication node with the SSC pattern, until receipt of a second acknowledgment.

Example 19 is example 18, wherein clock and link training and management logic is further arranged to proceed to cooperate with the endpoint communication node to perform link training on receipt of the second acknowledgment.

Example 20 is any one of examples 17-19, wherein the communication node is a peripheral component interconnect express (PCIe) host communication node.

Example 21 is a communication node, comprising: a physical layer having a logical sub-block, and an electrical sub-block; wherein the logical sub-block includes clock and link training and management logic arranged to: perform clock training handshake with a host communication node; receive instruction from the host communication node to start static phase measurement as part of the clock training, on successful completion of the clock training handshake; receive clock pattern from the host communication node; provide an acknowledgement to the host communication node on successful completion of the static phase measurement; receive instruction from the host communication node to start clocking synchronization; and start clocking synchronization to the host communication node.

Example 22 is example 21, wherein clocking synchronization comprises spread spectrum clocking (SSC) synchronization; the clock and link training and management logic is further arranged to receive from the endpoint communication node with SSC pattern; wherein the acknowledgement is a first acknowledgment; and wherein the clock and link training and management logic is arranged to provide to the host communication node a second acknowledgment, on completion of SSC synchronization.

Example 23 is example 22, wherein clock and link training and management logic is further arranged to proceed to cooperate with the host communication node to perform link training on provision of the second acknowledgment.

Example 24 is any one of examples 21-23, wherein the communication node is a peripheral component interconnect express (PCIe) endpoint communication node.