Pulsed state retention power gating flip-flop

A flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is configured to maintain the logic state of the flip-flop in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered. A clock pulse that clocks the flip-flop is derived from the associated clock signal.

BACKGROUND

This disclosure relates generally to a flip-flop and, more specifically, to a pulsed state retention power gating flip-flop.

2. Related Art

State retention power gating (SRPG) is a technique employed in flip-flops to reduce static leakage current by powering down certain components of the flip-flop during periods of inactivity. Reducing power consumption of electronic devices during periods of inactivity is commonly employed in battery-powered devices, such as mobile telephone handsets. Conventional SRPG flip-flop configurations have saved a logic state (‘0’ or ‘1’) of an SRPG flip-flop in a retention latch prior to power-down. A common flip-flop configuration is a master-slave configuration in which a master latch feeds a slave latch. At least one conventional SRPG flip-flop configuration has maintained power to the slave latch (to preserve a current logic state) when other components of the SRPG flip-flop, including the master latch, are power-gated (i.e., power is removed from the master latch and other components). In general, the slave latch (which has acted as a retention latch and has remain powered during a power-down condition) has consumed a non-significant amount of static leakage current in the power-down state.

U.S. Pat. No. 7,164,301 (hereinafter “the '301 patent”) discloses an imbalanced state retention power gating (SRPG) flip-flop that forces a known state upon power-up, depending upon the state being stored, to save additional static leakage current. More specifically, the '301 patent discloses removing power from a slave latch (in addition to an associated master latch) that is in a predetermined state prior to power-down to save additional static leakage current in the power-down state.

With reference toFIG. 1, a conventional non-pulsed SRPG flip-flop100is illustrated. The flip-flop100includes a retention latch130, which includes inverters102and104and pass gates106and108. First terminals of the pass gates106and108are coupled to an input of the inverter102and second terminals of the pass gates106and108are coupled to an output of the inverter104. An output of the inverter102is coupled to an input of the inverter104. The pass gate108is turned on when a clock (CPN) signal (which is an inverted version of a clock (CPI) signal) is in a high logic state and the pass gate106is turned on when a power-down (PD) signal is in a high logic state, i.e., when the flip-flop100is not in a deep sleep (power-down) mode. A first input of an inverting multiplexer120is configured to receive a data (D) signal and a second input of the multiplexer120is configured to receive a test input (TI) signal. A control input of the multiplexer120is configured to receive a test enable (TE) signal that, when asserted, selects the TI signal such that a scan function may be performed. An output of the multiplexer120is coupled to a first terminal of pass gate118, which is turned on when the CPN signal is in a high logic state. A second terminal of the pass gate118is coupled to an input of inverter116and a first terminal of pass gate114, which is turned on when the CPI signal is in a high logic state.

A second terminal of the pass gate114is coupled to an output of an inverter112, whose input is coupled to an output of the inverter116. An input of inverter122is coupled to the output of the inverter116and the input of the inverter112. A functional latch140is formed by the inverters112and116and the pass gate114. An output of the inverter122is coupled to a first terminal of a pass gate124, which is turned on when the CPI signal is in a high logic state. A second terminal of the pass gate124is coupled to a drain of n-channel metal-oxide semiconductor field-effect transistor (MOSFET)128, an input of an inverter126, and a first terminal of pass gate110, which is turned on when the PDN signal is in a high logic state. A second terminal of the pass gate110is coupled to an input of the inverter102. In general, the flip-flop100has a relatively high CPI pulse high time requirement. Moreover, the flip-flop100requires the maintenance of multiple signals (i.e., the CPN and PDN signals) when the flip-flop100is in a power-down mode, requires that the CPN signal be in a certain state when entering and exiting the power-down mode, and employs a relatively large number of devices in a speed path (data input (D) to data output (Q) path) which causes the flip-flop100to have a relatively high propagation delay.

In general, pulsed SRPG flip-flops are designed to reduce a speed path delay by reducing the number of components in the speed path of a flip-flop. For example, U.S. Patent Application Publication No. 2006/0197571 (hereinafter “the '571 application”) discloses a multi-threshold complementary metal-oxide semiconductor (MTCMOS) pulsed SRPG flip-flop that includes a scan function that is input into a retention latch of the flip-flop to, apparently, reduce the number of components in the speed path of the flip-flop. As is known, an MTCMOS circuit usually employs low threshold voltage (general power (GP)) CMOS transistors to implement a desired function during normal operation (power-up) mode and high threshold voltage (low power (LP)) CMOS transistors to reduce leakage current during a sleep (power-down) mode. In general, the pulsed SRPG flip-flops disclosed in the '571 application have a relatively high leakage current when in a power-down mode, require the maintenance of multiple signals when in a power-down mode, and require that a clock signal be in a high logic state when going into power-down in order to save a current state of the flip-flop in a retention latch.

What is needed is a pulsed state retention power gating flip-flop that exhibits lower leakage currents when in a power-down state.

DETAILED DESCRIPTION

In the following detailed description of exemplary embodiments of the invention, specific exemplary embodiments in which the invention may be practiced are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, architectural, programmatic, mechanical, electrical and other changes may be made without departing from the spirit or scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and their equivalents. In particular, although the preferred embodiment is described below in conjunction with a processor system of a subscriber station, such as a cellular handset, it will be appreciated that the present invention is not so limited and may be embodied in a variety of functional blocks included within various devices, e.g., personal digital assistants (PDAs), digital cameras, portable storage devices, audio players, computer systems, and portable gaming devices, for example. As is used herein, the term “coupled” includes a direct connection between elements (devices) and an indirect connection between elements (devices) achieved with one or more intervening elements (devices). The terms “latch” and “flip-flop,” as used herein, are interchangeable.

Various embodiments of the present disclosure are directed to a pulsed state retention power gating (SRPG) flip-flop that has a relatively low leakage current (equal to or less than about 143 pA) while in a power-down state and a relatively low number of gates in a speed path (D input to Q output) of the flip-flop. The flip-flop has a relatively low (e.g., 100 pS) setup-time plus clock-to-Q time, which is particularly advantageous in higher frequency applications (e.g., 1 GHz and higher frequencies). While the disclosed flip-flops have a hold-time requirement of approximately 150 pS (due to the nature of how a pulse is generated), the flip-flops may be advantageously employed in signals paths that have setup-time issues but do not have hold-time issues. In general, the only limitations on minimum pulse width are that the minimum pulse width be wide enough to ensure that data is properly written to a functional latch of the flip-flop and that an input clock signal does not prematurely turn off a NAND gate that is used to generate the pulse (seeFIGS. 4 and 5). In at least one embodiment, the SRPG flip-flop implements a scan function and in this embodiment the SRPG flip-flop includes three stages (a multiplexer, a pass gate, and an inverter) in the speed path. In another embodiment, the SRPG flip-flop does not implement a scan function and in this embodiment the SRPG flip-flop includes two stages (a pass gate and an inverter) in the speed path. A pulsed SRPG flip-flop, configured according to various embodiments of the present disclosure, does not appreciably increase area, size, or power requirements on a chip in which the pulsed SRPG flip-flop is employed. In various embodiments, each device in the speed path of the flip-flop can be a high-speed device (e.g., a general power (GP) low threshold voltage device) without negatively impacting leakage currents when the flip-flop is in a power-down mode (due to the fact that the high-speed devices are not powered in the power-down mode). The GP devices may be, for example, high voltage threshold (HVT) or standard voltage threshold (SVT) GP devices.

In various embodiments, the SRPG flip-flop includes a functional latch and a retention latch. In general, the retention latch employs low power (LP) devices to reduce leakage current when the flip-flop in a power-down mode. The LP devices may be, for example, HVT or SVT LP devices. Data is transferred between the retention latch and the functional latch using contention. That is, when data is written from the functional latch to the retention latch, GP devices in the functional latch over power weaker low power (LP) devices in the retention latch. When data is written from the retention latch to the functional latch, secondary steering switches (e.g., metal-oxide semiconductor field-effect transistors (MOSFETs)) are employed to aid the LP devices in the retention latch to over power the GP devices in the functional latch. In another embodiment, LP devices may be employed in both the retention latch and the functional latch. In this case, transfer of data between a functional latch and a retention latch may also be achieved using contention by employing different size devices, by employing different voltage threshold devices, or by employing both different size devices and different voltage threshold devices.

In one embodiment, data is continuously written from the functional latch to the retention latch. In another embodiment, the retention latch is only written prior to entering a power-down mode, which generally reduces operating power requirements. In at least one embodiment, the flip-flop utilizes two control signals (i.e., a write (W) signal and a read (RD) signal) to transfer data between the functional and retention latches. In one embodiment, only the W signal is maintained while the flip-flop is in the power-down mode. While the discussion herein is directed to the use of n-channel and p-channel MOSFETs, it should be appreciated that in many applications any type of switches, e.g., bipolar junction transistors (BJTs), may be employed in various applications. Moreover, in various applications, the channel type of the MOSFET employed may be changed. More generally, the MOSFET devices may be thought of as insulated gate FETs (IGFETS).

According to one aspect of the present disclosure, a flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is configured to maintain the logic state of the flip-flop in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered. A clock pulse (that clocks the flip-flop) is derived from the associated clock signal.

According to another aspect of the present disclosure, a method of operating a flip-flop includes receiving a first indication that a functional latch of the flip-flop is to enter a power-down mode. In this embodiment, the functional latch includes first devices. Data is transferred from the functional latch to a retention latch of the flip-flop prior to entering the power-down mode. The retention latch includes second devices that are over-powered by the first devices to effect the transfer of the data from the functional latch to the retention latch. Following the transfer of the data from the functional latch to the retention latch, the functional latch and the retention latch are disconnected and power is removed from the functional latch.

According to yet another embodiment, a processor system includes a processor register that includes a memory element. The memory element includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the memory element in a power-up mode. The retention latch is configured to maintain the logic state of the memory element in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered.

With reference toFIG. 2, a pulsed state retention power gating (SRPG) flip-flop200, which is configured according to an embodiment of the present disclosure, is illustrated. The flip-flop200includes a retention latch240, a functional latch250, and a pulse generator (not shown specifically inFIG. 2) that provides two clock (CPN and CPI) signals (seeFIGS. 4 and 5). The retention latch includes inverters202and204, which are powered by a continuous power supply (VDDC) when power is removed from other components of the flip-flop200during a power-down mode. An input of the inverter202is coupled to an output of the inverter204and an input of the inverter204is coupled to an output of the inverter202. A first terminal (drain) of a first switch (n-channel MOSFET)206is coupled to the input of the inverter204and a second terminal (source) of the switch206is coupled to an output of inverter214and a first terminal of pass gate218. A first terminal (drain) of a second switch (n-channel MOSFET)208is coupled to the output of the inverter204and a second terminal (source) of the switch208is coupled to an output of inverter216, an input of the inverter214, and a first terminal (drain) of switch (n-channel MOSFET)226.

Control terminals (gates) of the switches206and208are configured to receive a write (W) signal, which dictates whether the retention latch240is coupled to the functional latch250, which includes the inverters214and216and the pass gate218. The W signal may be maintained in an asserted state during normal operation of the flip-flop200or may be maintained in a non-asserted state until just prior to power-down. In this case, the W signal is asserted just prior to power-down to write a value of the functional latch250to the retention latch240. The W signal is then maintained in a non-asserted state during the power-down mode to reduce leakage currents and isolate the functional latch250from the retention latch240. In at least one embodiment, the devices in block242are low power (LP) devices and the devices not in block242are general power (GP) devices. However, as noted above, different size devices, different voltage threshold devices, or both different size devices and different voltage threshold devices may be implemented in the functional latch250and the retention latch240to achieve the same functionality. A second terminal (source) of the switch226is coupled to a second terminal (source) of a switch (n-channel MOSFET)228and a first terminal (drain) of switch (n-channel MOSFET)230. A second terminal (source) of the switch230is coupled to a common point (e.g., ground) and a control terminal (gate) of the switch230is configured to receive a read (RD) signal that is asserted when data is read out of the retention latch240and into the functional latch250.

The switches226and228function as steering switches that facilitate writing from the retention latch240(which employs LP devices) to the functional latch (which employs GP devices, in at least one embodiment). A first terminal (drain) of the switch228is coupled to an input of the inverter216, an input of the inverter224, and second terminals of pass gates218and222. A control terminal (gate) of the switch226is coupled to the output of the inverter202and a control terminal (gate) of the switch228is coupled to the input of the inverter202. An inverting multiplexer220includes a first input that is configured to receive a data (D) signal, a second input that is configured to receive a test in (TI) signal, and a select input that is configured to receive a test enable (TE) signal, which, when asserted, selects the TI signal for implementing a scan function. An output of the multiplexer220is coupled to a first terminal of the pass gate222and an output of the inverter224provides an output (Q) signal. The pass gate222is turned on when a clock (CPI) signal is in a high logic state and the pass gate218is turned on when a clock (CPN) signal is in a high logic state. The CPI signal is in a high logic state when the CPN signal is in a low logic state and the CPI signal is in a low logic state when the CPN signal is in a high logic state. As such, the pass gate218is turned on when the pass gate222is turned off and the pass gate218is turned off when the pass gate222is turned on.

In various implementations, the pass gate218may be omitted (i.e., replaced with a short). The inverter214is coupled to a power supply (VDD) via a switch (p-channel MOSFET)210. More specifically, a first terminal (drain) of the switch210is coupled to the power supply VDD and a second terminal (source) of the switch210is coupled to a power input terminal of the inverter214. When the flip-flop200enters a power-down mode the power supply VDD is removed, e.g., goes to zero volts. A control terminal (gate) of the switch210is configured to receive a read (RD) signal, which is in a low logic state during normal operation of the flip-flop200and is in a high logic state when the data in the retention latch240is read into the functional latch250. The inverter216is coupled to the power supply VDD via a switch (p-channel MOSFET)212. More specifically, a first terminal (drain) of the switch212is coupled to the power supply VDD and a second terminal (source) of the switch212is coupled to a power input terminal of the inverter216. A control terminal (gate) of the switch212is configured to receive a power-down (PD) signal, which is in a low logic state during normal operation of the flip-flop200and is in a high logic state when the flip-flop200is in a power-down mode. The second terminals of the switches210and212are coupled together and, as such, the inverters receive power from the power supply VDD whenever either the RD or PD signals are in a low logic state, assuming that the power supply VDD is configured to provide power.

With reference toFIG. 3, a pulsed state retention power gating (SRPG) flip-flop300, which is configured according to another embodiment of the present disclosure, is illustrated. The flip-flop300is similar to the flip-flop200, except that the flip-flop300does not implement a scan function (i.e., does not include an input multiplexer). The flip-flop300includes a retention latch340, a functional latch350, and a pulse generator (not shown specifically inFIG. 3) that provides two clock (CPN and CPI) signals (seeFIGS. 4 and 5). The retention latch includes inverters302and304, which are powered by a continuous power supply (VDDC) when power (supplied by power supply VDD) is removed from other components of the flip-flop300during power-down. An input of the inverter302is coupled to an output of the inverter304and an input of the inverter304is coupled to an output of the inverter302. A first terminal (drain) of a first switch (n-channel MOSFET)306is coupled to the input of the inverter304and a second terminal (source) of the switch306is coupled to an output of inverter314and a first terminal of pass gate318. A first terminal (drain) of a second switch (n-channel MOSFET)308is coupled to the output of the inverter304and a second terminal (source) of the switch308is coupled to an output of inverter316, an input of the inverter314, and a first terminal (drain) of switch (n-channel MOSFET)326.

Control terminals (gates) of the switches306and308receive a write (W) signal, which dictates whether the retention latch340is coupled to the functional latch350, which includes the inverters314and316. The W signal may be maintained in an asserted state during normal operation of the flip-flop300or may be maintained in a non-asserted state until just prior to power-down. In this case, the W signal is asserted just prior to power-down to write a value of the functional latch350to the retention latch340. The W signal is then maintained in a non-asserted state during the power-down mode to reduce leakage currents. In this embodiment, the devices in block342are low power (LP) devices and the devices not in block342are, in at least one embodiment, general power (GP) devices. A second terminal (source) of the switch326is coupled to a second terminal (source) of a switch (n-channel MOSFET)328and a first terminal (drain) of switch (n-channel MOSFET)330. A second terminal (source) of the switch330is coupled to a common point (e.g., ground) and a control terminal (gate) of the switch330receives a read (RD) signal that is asserted when data is read out of the retention latch340and into the functional latch350.

In various implementations, the pass gate318may be replaced with a short. The inverter314is coupled to the power supply VDD via a switch (p-channel MOSFET)310. More specifically, a first terminal (drain) of the switch310is coupled to the power supply VDD and a second terminal (source) of the switch310is coupled to a power input terminal of the inverter314. A control terminal (gate) of the switch310is configured to receive a read (RD) signal, which is in a low logic state during normal operation of the flip-flop300and is in a high logic state when the data in the retention latch340is read into the functional latch350. The inverter316is coupled to the power supply VDD via a switch (p-channel MOSFET)312. More specifically, a first terminal (drain) of the switch312is coupled to the power supply VDD and a second terminal (source) of the switch312is coupled to a power input terminal of the inverter316. A control terminal (gate) of the switch312is configured to receive a power-down (PD) signal, which is in a low logic state during normal operation of the flip-flop300and is in a high logic state when the flip-flop300is in a power-down mode. The second terminals of the switches310and312are coupled together.

The switches326and328function as steering switches that facilitate writing from the retention latch340(which employs LP devices) to the functional latch (which employs GP devices, in at least one embodiment). A first terminal (drain) of the switch328is coupled to an input of the inverter316, an input of the inverter324, and second terminals of pass gates318and322. A control terminal (gate) of the switch326is coupled to the output of the inverter302and a control terminal (gate) of the switch328is coupled to the input of the inverter302. A first terminal of the pass gate322is configured to receive a data (D) signal and an output of the inverter324provides an output (QN) signal. In this embodiment, the pass gate322is turned on when the CPI signal is in a high logic state and the pass gate318is turned on when the CPN signal is in a high logic state. The CPI signal is in a high logic state when the CPN signal is in a low logic state and the CPI signal is in a low logic state when the CPN signal is in a high logic state. As such, the pass gate318is turned on when the pass gate322is turned off and the pass gate318is turned off when the pass gate322is turned on.

FIG. 4shows a pulse generator400that includes a buffer402, a NAND gate406, and inverters404and408. An input of the buffer402is configured to receive a clock (CP) signal and an output of the buffer402is coupled to an input of the inverter404. An output of the inverter404is coupled to a first input of the NAND gate406and a second input of the NAND gate406is configured to receive the CP signal. An output of the NAND gate406provides the CPN signal and is coupled to an input of the inverter408. An output of the inverter408provides the CPI signal. It should be appreciated that a pulse width of the CPI signal is dictated by a difference in propagation delay (attributable to the buffer402and the inverter404) between the signals provided at the first and second inputs of the NAND gate406. The pulse width of the CP signal can be virtually any length, providing that the CP signal does not prematurely cause the NAND gate406to turn off (i.e., the pulse width of the CP signal should be wider than the propagation delay through buffer402and the inverter404).

FIG. 5shows a pulse generator500that includes a buffer chain502, a NAND gate506, and inverters504and508. An input of the buffer chain502is configured to receive a clock (CP) signal and an output of the buffer502is coupled to an input of the inverter504. An output of the inverter504is coupled to a first input of the NAND gate506and a second input of the NAND gate506is configured to receive the CP signal. An output of the NAND gate506provides the CPN signal and is coupled to an input of the inverter508. An output of the inverter508provides the CPI signal. It should be appreciated that a pulse width of the CPI signal is dictated by a difference in propagation delay (attributable to the buffer chain502and the inverter504) between the signals provided at the first and second inputs of the NAND gate506. The pulse width of the CP signal can also be virtually any length, providing that the CP signal does not prematurely cause the NAND gate506to turn off (i.e., the pulse width of the CP signal should be wider than the propagation delay through buffer chain502and the inverter504). It should be appreciated that the pulse generators400and500may be configured to receive other signals, e.g., a reset signal, an enable signal, and a set signal, which are considered well within the level of one of ordinary skill in the art, based on the present disclosure.

FIG. 6depicts an exemplary processor system600that includes a processor602having at least one central processing unit (CPU) core604coupled to an on-chip level 1/level 2 (L1/L2) cache subsystem606. The processor602is configured to execute an application appropriate software system (e.g., an operating system and one or more applications). The subsystem606is coupled to an off-chip cache subsystem608, which may include L2 and/or level 3 (L3) cache, depending upon the architecture of the processor602. For example, the processor602may include both L1 and L2 cache on-chip. In this case the subsystem608may only incorporate L3 cache. As another example, the processor602may only include L1 cache, in which case the subsystem608may include both L2 and L3 cache. In either case, the cache subsystem608is coupled to the main memory610. In a typical embodiment, the L1, L2 and L3 cache each comprise an application appropriate amount of static random access memory (SRAM) and the main memory comprises an application appropriate amount of dynamic random access memory (DRAM). The CPU604may also include registers (memory elements) which may be configured according to various aspects of the present disclosure. More specifically, the registers of the CPU604or various paths of the CPU604may include memory elements configured in a similar manner to the flip-flop200ofFIG. 2or the flip-flop300ofFIG. 3. The flip-flops disclosed herein may be encoded within one or more design files (e.g., design files for a processor integrated circuit) on one or more computer readable storage media, e.g., compact disk read-only memory (CD-ROM), etc.

With reference toFIG. 7, a process700is illustrated for powering up and powering down devices of a memory element (e.g., a flip-flop), which may be configured according to various embodiments of the present disclosure. Without loss of generality, the process700is described in conjunction with the flip-flop200ofFIG. 2. In block702the process700is initiated, at which point control transfers to decision block704. In block704, it is determined whether a first indication (that the functional latch250of the flip-flop200is to enter a power-down mode) is received. If the first indication is received in block704, control transfers to block706, where the functional latch250of the flip-flop200is connected (using the switches206and208) to a retention latch240of the flip-flop200. Next, in block708, data is transferred from the functional latch250to the retention latch240, prior to entering the power-down mode. In this case, the retention latch240includes second devices that are over-powered by first devices of the functional latch250to effect the transfer of the data from the functional latch250to the retention latch240. Then, in block710, the functional latch250is disconnected (using the switches206and208) from the retention latch240(following the transfer of the data from the functional latch250to the retention latch240). Next, in block712, power is removed (e.g., the power supply VDD is disabled) from the functional latch250. From block712, control transfers to block714, where the process700terminates until another event is detected.

In block704, when the first indication is not received, control transfers from block704to decision block716. In block716, it is determined whether a second indication that the functional latch250is to enter a power-up mode is received. If the second indication is not received in block716, control transfers to block714. If the second indication is received in block716, control transfers to block718, where the functional latch250is connected (using the switches206and208) to the retention latch240. Next, in block720, power is provided to the functional latch250. Then, in block722, a selected node of the functional latch250is connected to a low voltage node using a steering switch (including the switches226,228and230) to facilitate transfer of the data from the retention latch240to the functional latch250. In this case, the selected node is based on the data stored in the retention latch240. Following block722, control transfers to block724, where the functional latch250is disconnected from the retention latch240following the transfer of the data from the retention latch240to the functional latch250, and then to block714.

Accordingly, a number of techniques have been disclosed herein that generally provide a pulsed state retention power gating flip-flop that has reduced leakage current when in a power-down state.

As used herein, a software system can include one or more objects, agents, threads, subroutines, separate software applications, two or more lines of code or other suitable software structures operating in one or more separate software applications, on one or more different processors, or other suitable software architectures.

As will be appreciated, the processes in preferred embodiments of the present invention may be implemented using any combination of computer programming software, firmware or hardware. As a preparatory step to practicing the invention in software, the computer programming code (whether software or firmware) according to a preferred embodiment will typically be stored in one or more machine readable storage mediums such as fixed (hard) drives, diskettes, optical disks, magnetic tape, semiconductor memories such as read-only memories (ROMs), programmable ROMs (PROMs), etc., thereby making an article of manufacture in accordance with the invention. The article of manufacture containing the computer programming code is used by either executing the code directly from the storage device, by copying the code from the storage device into another storage device such as a hard disk, random access memory (RAM), etc., or by transmitting the code for remote execution. The method form of the invention may be practiced by combining one or more machine-readable storage devices containing the code according to the present disclosure with appropriate standard computer hardware to execute the code contained therein. An apparatus for practicing the techniques of the present disclosure could be one or more computers and storage systems containing or having network access to computer program(s) coded in accordance with the present disclosure.