High frequency divider state correction circuit

The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The received value is transmitted to a third flip flop. In one aspect, the received value transmitted to the third flip flop comprises an unaltered received value. In another aspect, the received value transmitted to the third flip flop comprises transmitting an altered received value. This allows for an incorrect state within the state machine to change to a correct state after a few clock pulses.

This Application relates to “High Frequency Divider Circuit With Data Path Correction”, AUS920031086US1 filed concurrently herewith.

TECHNICAL FIELD

The present invention relates generally to error correction and, more particularly, to error correction in a state machine circuit.

BACKGROUND

There is a type of incrementer called a high frequency divider. In a high frequency divider, the values within the incrementer change in a predefined fashion, but not necessarily by a mathematical addition or subtraction. For instance, 000000 could be the first state, 000001 could be the second number, 000011 could be the third, 000111 could be the fourth, 001111 could be the fifth, 011111 could be the sixth, 111111 could be the seventh, 011111 could be the eighth state, and so on. The values could represent the generation of a square wave, although other uses are also possible. The particular incrementing from state value to state value is a function of the internal logic of the high frequency divider.

However, there is a problem with high frequency dividers. One such problem is if the system starts up in an invalid state. For instance, what if it starts in state 010101? This can happen when a system first powers up, as the states of the latches within the system can be indeterminate. Alternatively, a catastrophic event can happen, such as an electromagnetic pulse. If this happens, the states within the divide by 8 counter can be forced into an undesired state.

However, in conventional technology, if left uncorrected, the states could cycle from one undesired state to another undesired state, without ever becoming a desired state and getting back on track. The system can be reset, and a preloaded “seed” state can be entered into the system. However, this is time-wise an expensive proposition, and errors can creep in if the initial “seed” state is somehow inaccurate. If an electromagnetic pulse changes the state within the circuit to an invalid state or sequence. This invalid state or sequence should be deleted, which costs additional time and circuitry area, and a system reset is issued, which also costs additional time.

Therefore, there is a need to ensure that a desired state is arrived at after a certain number of state transitions in a manner that addresses at least some of the problems associated with the prior art.

SUMMARY OF THE INVENTION

The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The received value is transmitted to a third flip flop. In one aspect, the received value transmitted to the third flip flop comprises an unaltered received value. In another aspect, the received value transmitted to the third flip flop comprises transmitting an altered received value.

DETAILED DESCRIPTION

In the remainder of this description, a processing unit (PU) may be a sole processor of computations in a device. In such a situation, the PU is typically referred to as an MPU (main processing unit). The processing unit may also be one of many processing units that share the computational load according to some methodology or algorithm developed for a given computational device. For the remainder of this description, all references to processors shall use the term MPU whether the MPU is the sole computational element in the device or whether the MPU is sharing the computational element with other MPUs, unless otherwise indicated.

It is further noted that, unless indicated otherwise, all functions described herein may be performed in either hardware or software, or some combination thereof. In a preferred embodiment, however, the functions are performed by a processor, such as a computer or an electronic data processor, in accordance with code, such as computer program code, software, and/or integrated circuits that are coded to perform such functions, unless indicated otherwise.

Turning toFIG. 1A, disclosed is a divide by 8 stateflow diagram with allowed and unallowed states. InFIG. 1A, an unallowed stateflow transitions into an allowed stateflow after a specifically defined state or a set of states occurs. Generally, in reference toFIG. 1A, a specifically defined non-allowed state is detected, such as 00110011 or 00110000, and an internal change of a value occurs within the high frequency divider circuit, thereby kicking the state of the internal D Latch into a desired state, such as 00000001 or 10000000, instead of 00011001 or 10011000, which would have been the result in conventional technology.

For instance, inFIG. 1A, what if the undesired state of 01100111 arose at power up? By the internal logic of the circuitry (a shift right, and then invert the value shifted from rightmost bit and wrapped around the to the leftmost bit), this would become 00110011, a second unallowed state. By a similar logic, this would then transition into 00011001. However, the transition diagram ofFIG. 1Aaddresses this problem.

Turning now toFIG. 1B, illustrated is a divide by 6 stateflow. An unallowed stateflow transitions into an allowed stateflow after a specifically defined state occurs. Generally, in reference toFIG. 1B, a specifically defined non-allowed state is detected as 001100, a circuit transitions into a allowed state 100000, instead of 100110, an unallowed state.

Turning now toFIG. 2, illustrated is a divide by 8 state circuit200. A D type flip flop (DFF)1215has a clock signal input into its C input from a clock source235. The Q output of DFF1215(q1signal state) is coupled to the D input of a DFF2220. The Q output of DFF1220(q2signal state) is coupled to the D input of a DFF3225. The Q output of DFF3225(q3signal state) is coupled to the D input of a DFF4230. The Q inverted output of DFF4230(q4signal state) is fed back into and coupled coupled to the D input of a DFF2215.

The Q states of DFF1, DFF2, DFF3and DFF4215,220,225,230are coupled to a logical operator210. The logical operator210is coupled to a gate of the DFF2220. In other implementations, only flip flops215,220and225are used. Gate Memory205can be used to introduce a time delay. Otherwise, there could be problems with substantially simultaneous feedback, and the logic states might not converge, an error condition. This configuration enables the state transition from the undesired states to desired states ofFIG. 1A.

Turning now toFIG. 3, illustrated are the internal workings300of a conventional D flip flop, such as DFF1215, DDF3225, and DFF4230. As is illustrated regarding a flip flop, there are two inputs, input1(D, for data input) and input2(C, for a clock input). Flip flops have applicability as memory devices. The flip flop DFF3225is actually comprised of 2 different latches,310and320.

As is understood by those of skill in the art, if a flip-flop is enabled by a clock signal, the flip flop will pass on the signal data state from the input to the output on the data, or Q line. However, if the flip flop is disabled by a clock signal, the input D value will not be propagated to the output, and instead the previously stored D value will be output of the D input.

InFIG. 3, of DFF1215, for instance, there are two D latches coupled in series, latch310and latch320. If the input value for D is 1, and the clock value is enabled, the qint1value is also the same as the D value, and the qintb value is the inverted value of qintB. However, due to a logical “not” operator330, the second D latch320is disabled. This means that, no matter what the qint value is in this circuit, the previous qint value is what is output as the Q value. In other words, with the clock being “high”, the output of DFF1215can not change, as it “remembers” and outputs the previous state.

However, for instance, in the next clock pulse, the input clock pulse goes “low”. Therefore, the input data does not propagate from the Data input to the Q or qint output in this flip flop, and the qint value of the previous clock cycle is retained by this first D latch310. However, because the input clock value is inverted to “high”, the second flip flop propagated the qint value into the output Q, the “3” value. Hence, for the DFF1215to change an output state, it takes at least one full clock cycle, and it only accepts as input data states from alternating clock cycles.

Turning back toFIG. 2, this means that, for instance, the values 00000011can be used in the system. On the next clock cycle, the value becomes 00000001. As has been explained above, there is an internal state (qint1, qint2, qint3) etc, which is illustrated as non-underline, and a state q1, q2, q3and so on, which is illustrated as underlined. The state changes because the inversion that occurs at the output of DFF4230, which is fed back in as data into the D port of the DFF1215. As is seen by the desired states transition illustrated inFIG. 1A, the states are stepped through the system, the last flip-flop inverting and transferring the inverted value back to the input.

However, if an undesired state comes up, the system200can work as follows. For instance, what if a conventional divide by 8 system starts as 01100111 as its starting state? A conventional system would then transition to 00110011, also an invalid state, without correction this would further transition to 00011001.

However, the logic ofFIG. 2is configured to transition to 00000001instead of 00011001, an allowed state. InFIG. 2, the second bit of the state 00xxxxxx, is used to overwrite the next 3 bits in the state, to become 00000xxx. Similarly, an invalid state of 00110000transitions to 10000000instead of 10011000. In other words, the first output state (q1) also becomes q2internal and q2out and q3internal, as will be illustrated inFIG. 1A.

The system200detects invalid states can be as follows. The outputs q1, q2(inverted) and q3are input into the OR110. When xxxxxxxx(“x” a variable), have the values of x0x1x0xx, the OR gate output becomes negative, the output invalidb state goes low, and there is enabled a transition from an unallowed state to an allowed state. Turning briefly toFIG. 1A, this transition happens at both 00110011and 00110000, as is shown inFIG. 1A, and only in those states does the transition to a desired state happen.

Turning now toFIG. 4, illustrated are the internal working400with latches410,420of DFF220, the flip flop in which state transitions occur when the logical operator110detects a specified error state condition. The logical operator of NOT (the inverter)330ofFIG. 3is replaced by an XOR430. An XOR, as is understood by those of skill in the art, gives a true value if both values are different, and a false value (value of zero) if both input values are the same In the context ofFIG. 2, this means that the OR output is 0 for a specific predefined non-allowed state, and 1 for an allowed state or a non-specified non-allowed state. Then, this becomes the “gate” value into DFF2220flip flop.

InFIG. 4, when the gate value output by the OR gate210is “one”, and the C value input is a “1”, the output value is a “0”, which means that the flip flop220is behaving like a prior art flip flop, and the XOR is behaving as an inverter. Similarly, if the gate value is “one” and the C value input is a “0”, the output value is a “1”, which means the XOR logical operator430is active as an inverter to the C value.

InFIG. 4, when the gate value is “zero”, and the C value input is a “1”, the XOR output value is a “1”, which means that the flip flop220is not behaving like a prior art flip flop, and the same value for D is being propagated through both D1latch1and D Latch2. Similarly, if the gate value is “zero” and the C value input is a “0”, the XOR output value is a “0”, which is sent as a C input to D Latch2420, and the previous states are stored in D1latch1and D2latch2.

In other words, when the output of OR210, the gate input to the XOR430, is zero, the D latch1410and the D Latch2420both have the same clock values within DFF2115. In the context ofFIG. 2, this means when gate3ofFIG. 4is zero, for a negative clock pulse, the qint value still does not change. However, unlike the prior art, the Q output value does not change either. Therefore, the qint and the q value are both “locked,” which is unlikeFIG. 3, and the Q output value does not change.

Furthermore, if the input clock pulse is positive and the gate input is zero, the input D value propagates through both D latches410,420, through qint2and then out through Q. Also, because the clock state is positive as input into DFF3225, the qint of the third flip flop q3int is also equal to q2. In other words, D value becomes Q, which was not true in the prior art.

In other words, for a gate value of 0, and a positive clock cycle, the q1value gets propagated to the qint2value and the q2output value, and the q3int value. In the context ofFIG. 1A, this means that instead of 00110000becoming the unallowed state of 10011000, it becomes 10000000, thereby forcing from an undesired state to a desired state. Likewise, the state after 00110011, which would have been 00011001, is instead 00000001, as the q1value gets propagated and copied through to q3int.

Turning now toFIG. 5, illustrated is an alternative embodiment of a divider circuit500. A D type flip flop (DFF)1510has a clock signal input into its C input. The Q output of DFF1510(q1signal state) is coupled to the D input of a DFF2520. The Q output of DFF2520(q2signal state) is coupled to a circuit550. The output of the circuit550is coupled to the D input of a DFF3530. The Q output of DFF3530(q3signal state) is coupled to the D input of a DFF4540. The outputs q1, q2, q3and q4can be selected by selectors512,522,532,542, thereby configuring the circuit500as a divide by 2, 4, 6 or 8 correction circuit.

A divider correction circuit550is coupled between the inverted output of DFF2520(q2b) and the data input into DFF3530. As is understood by those of skill in the art, the voltage produced by a CMOS circuit is a function of a supply voltage, and which transistors of the CMOS circuit are turned on and off. Correction circuit550is one embodiment of logic implementing the truth table of Table 1 below.

TABLE 1Truth Table for Correction Circuit 550.Q1bQ2bQ3bD3new00010011010001101001101011001110

In the above truth table, q1b(inverted output of DFF1510) is employed, Q2b(inverted output of DFF2520) is employed, and q3b(inverted output of DFF3530) is employed. InFIG. 5, the circuit550is coupled between the inverted output of Q2band the data input into D3, thereby creating the D3new value. The circuit550can work substantially as follows.

In the system500, q1B (inverted) value, the q2b(inverted) value, and the q3b(inverted) value are input into the circuit550. If q1bis a zero, D3new equals the opposite of q2B. The state of q3or q3bis not a factor in the above truth table.

However, if q1bequals a one, and if q2bequals a zero, and if q3bequals zero, then D3new is set to equal one. Hence, error correction arises.

Furthermore, there is no state among the desired states that would create a “skip” to an undesired state. For instance, if q1and q3equal zero of a desired state, this would be x0xxx0xxBy definition of the truth table ofFIG. 5, this would then become x0x0x0xxor x0x1x11x0xx. In other words, if q1and q2are zero, then q2is automatically zero, so in other words, there is no state that creates a problem.

As is understood by those of skill the art, the voltage across the drain and source of a CMOS circuit is a function of overall function of the circuit and whether the circuit is turned on or off. In550, this is one embodiment of logic corresponding to the following truth table. The truth table represents two conditions wherein Q1does not equal D2new.

In the system500, we are using q1b(inverted) value, and the q3b(inverted) value, so there is an actual change of state when q1bequals D3new. This occurs when q0is 0 and q3is 0. Therefore, the next value input into the next flip-flop after this is also zero, and both q3and qint3becomes 0 instead of 1, the value of Q1. InFIG. 1, this correlates to 00011001becomes 00000001and 10011000becoming 10000000. In other words, for the q1and q3output values of 1, q3int becomes zero.

Furthermore, there is no state among the desired states that would create a “skip” to an undesired state. For instance, if q1and q3equal zero in a desired state, this would be x0xxx0xxBy definition of the truth table ofFIG. 5, this would then become x0x0x0xx. By the type of frequency division that is done in this graph, if q1and q3are zero, then q2has to be zero, in the desired states. Therefore, there is no state that creates a problem.

Turning now toFIG. 6, illustrated are simulated waveform diagram of the operation of the diagram. As is illustrated, even if a q1to q4waveform starts out in an incorrect state, it transitions into a correct sequence of 1s and 0s after a few clock transitions.

It is understood that the present invention can take many forms and embodiments. Accordingly, several variations may be made in the foregoing without departing from the spirit or the scope of the invention. The capabilities outlined herein allow for the possibility of a variety of programming models. This disclosure should not be read as preferring any particular programming model, but is instead directed to the underlying mechanisms on which these programming models can be built.