Method and device for generating delay signal

For generating a delay signal, a series of source signals based on the same high frequency signal are first provided. Every adjacent two of the source signals have a phase difference of a certain clock unit therebetween. A first and a second output signals are then generated on the basis of the plurality of source signals at a first and a second time points selected as desired. The first and the second output signals are processed by a logic operation to obtain the accurate and adjustable delay signal. For obtaining the first and the second output signals, the source signals are duplicated at first, and then respectively processed in response to respective clock signals.

FIELD OF THE INVENTION

The present invention relates to a method and a device for generating a delay signal, and more particularly to a method and a device for generating an accurate and adjustable delay signal under a high-frequency system.

BACKGROUND OF THE INVENTION

Many problems in microprocessor design arise with the increasing operational speed, of the microprocessor. For example, synchronizing signals crossing different chips is a big issue to be solved.

Please refer toFIG. 1A, in which a chip scheme consisting of three chips is exemplified. The signals crossing the chips are illustrated in FIG.1B. The way for the third chip C3to receive a cross-chip signal from the first chip C1can be a direct path from the first chip C1or a path through the second chip C2. That is, the first chip C1directly transmits a cross-chip signal CS3to the third chip C3, or the first chip C1transmits a first cross-chip signal CS1to the second chip C2, and then the second chip C2transmits a second cross-chip signal CS2to the third chip C3. It is assumed that the cross-chip signal CS2is transmitted to the third chip C3after a time period t13. Generally, it is required that the cross-chip signal CS2has to synchronize the cross-chip signal CS3or be kept a constant phase difference t23from the cross-chip signal CS3as shown in FIG.1B.

In prior art, a delay cell (not shown) is used to generate a delay signal DS to the first chip C1to result in a constant delay period t12of the cross-chip signal CS3, thereby maintaining the desired phase difference of t23between the cross-chip signals CS2and CS3. However, the cross-chip signal CS2is generated after the transmission of the cross-chip signal S1from the first chip C1to the second chip C2, and it is difficult in practice to determine the accurate time for the cross-chip signal CS2to reach the third chip C3. Many uncertain factors have to be taken into considerations. The uncertain factors include pad delay, PCB (printed circuit board) delay, and any other factors resulting from manufacturing processes or layout. The constant delay of the delay cell cannot flexibly follow the possible change of the actual time for the cross-chip signal CS2to reach the third chip C3due to the uncertain factors, particularly arising for the manufacturing processes or layout. Accordingly, the desired constant phase difference t23between the cross-chip signals CS2and CS3cannot be assured of. In a high-frequency system, the misaligning problem is even significant. As is understood, the acceptable deviation is relatively low in a high-frequency system. The inaccurate phase difference t23between the cross-chip signals CS2and CS3is subject to the error function of the third chip C3.

SUMMARY OF THE INVENTION

Therefore, it is an object of the present invention to provide a device and a method for generating an accurate and adjustable delay signal so as to assure of the desired constant phase difference between the cross-chip signals in a high-frequency system.

A first aspect of the present invention relates to a method for generating a delay signal. The method comprises steps of providing a plurality of source signals, every adjacent two of which have a phase difference of a certain clock unit; generating a first and a second output signals at a first and a second time points based on the plurality of source signals; and processing the first and the second output signals by a logic operation to obtain the delay signal.

Preferably, the plurality of source signals are generated from a high-frequency signal by a phase-locked loop (PLL) device. The plurality of source signals can be a series of increasingly lagging signals or a series of increasingly leading signals.

In one embodiment, the logic operation is an XOR operation.

In one embodiment, the step of generating the first and the second output signals comprises sub-steps of: deriving a first and a second signal groups from the plurality of source signals; selecting a signal from the first signal group at the first time point as the first output signal; and selecting a signal from the second signal group at the second time point as the second output signal.

Preferably, the first and the second signal groups are obtained by duplicating the plurality of source signals.

Preferably, the first and the second time points are predetermined, and located by counting operations in response to a first and a second clock signals, respectively.

Preferably, the first output signal is generated based on the same first edges of selected two of the plurality of source signals, and the second output signal is generated based on the same second edges of selected two of the plurality of source signals. For example, the first and the second edges are both rising edges.

Preferably, a delay period of the delay signal is determined by the same third edges of the first and the second output signals. The third edges can be both rising edges or both falling edges.

In one embodiment, the first and the second signal groups are divided into a first and a second plurality of signal sub-groups, and the first and the second output signals are generated from one of the first plurality of signal sub-groups and one of the second plurality of signal sub-groups, respectively.

Preferably, all source signals in the selected one of the first plurality of signal sub-groups are at the same first level at the first time point, and all source signals in the selected one of the second plurality of signal subgroups are at the same second level at the second time point. For example, the first and the second levels are both low levels.

A second aspect of the present invention relates to a device for generating a delay signal. The device comprises a source-signal generator generating and outputting N counts of source signals in response to a high frequency signal, every adjacent two of the N counts of source signals having a phase difference of a certain clock unit; a source-signal selector coupled to the source-signal generator, and selecting a first and a second ones of the N counts of source signals to be outputted at a first and a second time points in response to a first and a second clock signals as a first and a second output signals, respectively, and a logic operator coupled to the source-signal selector, and logically operating the first and the second output signals to obtain the delay signal.

In one embodiment, the source-signal generator is a phase-locked loop (PLL) device.

In one embodiment, the source-signal selector includes: a selection-signal generating circuit generating a first and a second selection signal sets in response to the N counts of source signals and the first and the second clock signals; a first multiplexing circuit coupled to the selection-signal generating circuit, and allowing the first one of the N counts of source signals to be outputted as the first output signal in response to the first selection signal; and a second multiplexing circuit coupled to the selection-signal generating circuit, and allowing the second one of the N counts of source signals to be outputted as the second output signal in response to the second selection signal.

In one embodiment, the first multiplexing circuit includes M1counts of multiplexers receiving different portions of the N counts of source signals, respectively, and allowing M1onesamong the N counts of source signals to be outputted as M1counts of multiplexing output signals in response to M1counts of selection signals included in the first selection signal set, and the second multiplexing circuit includes M2counts of multiplexers for receiving different portions of the N counts of source signals, respectively, and allowing M2ones among the N counts of source signals to be outputted as M2counts of multiplexing output signals in response to M2counts of selection signals included in the second selection signal set.

Preferably, the source-signal selector further includes: a first signal synthesizing circuit coupled to the first multiplexing circuit for synthesizing the M1counts of multiplexing output signals into the first output signal; and a second signal synthesizing circuit coupled to the second multiplexing circuit for synthesizing the M2counts of multiplexing output signals into the second output signal.

In one embodiment, each of the first and the second signal synthesizing circuits includes an OR gate.

Alternatively, the first signal synthesizing circuit includes: M1counts of AND gates coupled to the selection-signal generating circuit, the M1counts of multiplexers and the source-signal generator, performing an AND operation of M1counts of decoding signals, the M1counts of multiplexing output signals and M1counts of specific signals, and outputting M1counts of gate output signals, respectively; and a first OR gate coupled to the M1counts of AND gates, and performing a first OR operation of the M1counts of gate output signals to obtain the first output signal. The second signal synthesizing circuit includes: M2counts of AND gates coupled to the selection-signal generating circuit, the M2counts of multiplexers and the source-signal generator, performing an AND operation of M2counts of decoding signals, the M2counts of multiplexing output signals and M2counts of specific signals, and outputting M2counts of gate output signals, respectively; and a second OR gate coupled to the M2counts of AND gates, and performing a second OR operation of the M2counts of gate output signals to obtain the second output signal.

In one embodiment, each of the M1counts of specific signals is identical to one of the source signals, and kept at least P counts of clock cycles of the first clock signal leading or lagging all the source signals inputted into the corresponding multiplexer, and each of the M2counts of specific signals is identical to one of the source signals, and kept at least P counts of clock cycles of the second clock signal leading or lagging all the source signals inputted into the corresponding multiplexer.

In one embodiment, the selection-signal generating circuit comprises: a first selection signal decoder generating the M1counts of decoding signals in response to the first clock signal; M1counts of operating units, each coupled to the first selection signal decoder and outputting an output control signal in response to one of the M1counts of decoding signals and (N/M1) ones of the N counts of source signals; M1counts of output units, each coupled to the first selection signal decoder and one of the M1counts of operating units, and outputting one of the M1counts of selection signals in response to the first clock signal, one of the M1counts of decoding signals and one of the M1counts of output control signals; a second selection signal decoder generating the M2counts of decoding signals in response to the second clock signal; M2counts of operating units, each coupled to the second selection signal decoder and outputting an output control signal in response to one of the M2counts of decoding signals and (N/M2) ones of the N counts of source signals; M2counts of output units, each coupled to the second selection signal decoder and one of the M2counts of operating units, and outputting one of the M2counts of selection signals in response to the second clock signal, one of the M2counts of decoding signals and one of the M2counts of output control signals;

Preferably, each of the M1operating units is an OR gate for performing an OR operation of the (N/M1) ones of the N counts of source signals, and each of the M2counts of operating units is an OR gate for performing an OR operation of the (N/M2) ones of the N counts of source signals.

Preferably, each of the M1and M2counts of output units is a transparent latch.

In one embodiment, the logic operator comprises: a storage unit for storing therein the first and the second output signals; and a logic operation unit coupled to the storage unit and logically operating the first and the second output signals to obtain the delay signal.

Preferably, the storage unit includes a first and a second T flip-flops for storing therein the first and the second output signals, respectively, and the logic operation unit is an XOR gate.

Alternatively, the storage unit includes a first and a second R-S latches for storing therein the first and the second output signals, respectively, and the logic operation unit is an XOR gate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

For generating a delay signal, a series of source signals based on the same high frequency signal are first provided. Every adjacent two of the source signals have a phase difference of a certain clock unit therebetween. For example, a phase-locked loop (PLL) device is used to generate the series of source signals, and eight increasingly lagging source signals P0˜P7are shown inFIG. 2A. Afirst and a second output signals are then generated on the basis of the plurality of source signals at a first and a second time points. By properly setting the output timing of the first and the second signals, a delay signal with an accurate and adjustable period can be obtained, which will be described hereinafter with reference toFIGS. 2B and 2C.

Referring toFIG. 2B, it is set that that two of the source signals, e.g. P1and P3, are selected to be outputted at the time points t1and t3so that the first and the second output signals toggle at the time points t1and t3, which are located within the first positive half-cycle of the high frequency signal, respectively. Then, the first and the second signal are processed with a logic operation, e.g. an XOR operation to obtain a delay signal with a delay period d1. Likewise, the source signals P5and P7are selected to be outputted at time points t5and t7to toggle the first and the second output signals again. The XOR operation of the first and the second signals results in another delay signals with a delay period d2. Similarly, when source signals P2and P6are selected to be outputted at time points t18and t22, which are located within the second positive half-cycle of the high frequency signal, a delay signal with a larger delay period d3can be obtained. When source signals P0and P2are selected to be outputted at time points t32and t34, which are located within the third positive half-cycle of the high frequency signal, a delay signal with a delay period d4can be obtained. Therefore, in this manner, the delay period is accurate and adjustable as desired.

The selection and output of different pairs of source signals differentiate the delay period as described above. Therefore, the time deviation resulting from the uncertain factors and unable to be solved in the prior art can be compensated by properly adjusting the delay period of the delay signal according to the present invention. In other words, the phase difference t23between the cross-chip signals CS2and CS3as shown inFIGS. 1A and 1Bcan be made constant.

Of course, if the delay periods for any of the positive half cycles of the high frequency signal are required to be constant, the same pairs of source signals can be used for all cycles to achieve this purpose. For example, when a constant delay period of 5 clock cycles is required, source signals, P1and P6can be selected to toggle the first and the second output signals at time points (t1, t6), (t17, t22), (t33, t38), . . . . After the XOR operation of the first and the second output signals, equal and accurate delay periods d5, d6, d7, . . . can be obtained.

As for the process of generating the first and the second output signals in response to the selected source signals, an example will be described hereinafter with reference to the simplified flowchart of FIG.3.

After the series of source signals as shown inFIG. 2Aare generated in response to a high frequency signal (Step31), the source signals are copied to include a first and a second signal groups (Step32). In response to a first clock signal, one of the source signals in the first signal group is selected to be outputted as the first output signal at a first point (Step33). Likewise, one of the source signals in the second signal group is selected to be outputted as the first output signal at a first point in response to a second clock signal (Step34).

In order to avoid the toggling operation contributing to the selection and output of source signals affects the electric levels of the first and the second output signals, it is preferred that the first and the second signal groups are further divided into several sub-groups, respectively. For example, there are N counts of source signals generated in response to the high frequency signal, and duplicated to include N counts of source signals in the first signal group and identical N counts of source signals in the second signal group. The N counts of source signals in the first signal group are further divided into M1counts of subgroups, each of which includes (N/M1) source signals. Likewise, the N counts of source signals in the second signal group are further divided into M2counts of sub-groups, each of which includes (N/M2) source signals.

Since all source signals in a selected one of the M1counts of sub-groups and all source signals in a selected one of the M2counts of sub-groups are kept at the same low level for generating the first and the second output signals, respectively, the electric levels of the first and the second output signals would not be affected by the toggling operation during the selection and output of the source signals.

The first and the second output signals are then processed by the XOR operation to determine the delay period (FIG. 3, Step35).

A device for generating a delay signal in response to a multiple signal source based on the above conception is referred to FIG.4. The device comprises a source-signal generator41, a source-signal selector42and a logic operator43. In order to describe the present invention clearly, the symbols N, M1and M2appearing inFIG. 3are exemplified as 32, 4 and 4, respectively. In other words, the source-signal generator41generates and outputs 32 source signals S0˜S31in response to a high frequency signal HFS, and every adjacent two of the 32 source signals S0˜S31have a phase difference of one clock unit, as are similar to the signals shown in FIG.2A. The source-signal selector42is coupled to the source-signal generator41for receiving the source signals S0˜S31, and duplicates the source signals S0˜S31into a first and a second signal groups. Each of the signal groups includes 32 source signals S0˜S31. In response to a first clock signals CK1, one of the 32 source signals in the first signal group is selected and outputted at a first time point. In response to the second clock signals CK2, one of the 32 source signals in the second signal group is selected and outputted at a second time point. The first and the second time points are predetermined according to the required delay period, and located by counting operations in response to the first and the second clock signals, respectively. Then, the logic operator43coupled to the source-signal selector logically operates the first and the second output signals, e.g. by an XOR operation, to obtain the delay signal.

The embodiments and operations of the source-signal generator41, the source-signal selector42and the logic operator43will be described hereinafter for further description of the present device. Please refer toFIGS. 5A and 5Bthat illustrates the source-signal selector42involving the generation of the first and the second output signals. The source-signal selector42comprises a first multiplexing circuit421, a second multiplexing circuit422, a selection-signal generating circuit423, a first signal synthesizing circuit424and a second signal synthesizing circuit425interconnected as shown in the figures. The first multiplexing circuit421includes four multiplexers MUX1, MUX2, MUX3and MUX4, and the first signal synthesizing circuit424includes four AND gates AND1, AND2, AND3and AND4and one OR gate OR1(FIG.5A). On the other hand, the second multiplexing circuit422includes four multiplexers MUX5, MUX6, MUX7and MUX8, and the second signal synthesizing circuit425includes four AND gates AND5, AND6, AND7and AND8and one OR gate OR3(FIG.5B).

First of all, the 32 source signals S0˜S31generated by the source-signal generator41(FIG. 4) are duplicated and provided for both of the first multiplexing circuit421and the second multiplexing circuit422. The 32 source signals S0˜S31are divided into four equal portions, wherein each portion includes eight non-repetitive source signals, and inputted into the four multiplexers MUX1, MUX2, MUX3and MUX4, respectively. On the other hand, in response to the 32 source signals S0˜S31and a first and a second clock signals CK1and CK2inputted into the selection-signal generating circuit423, a first and a second selection signal sets are generated. The first selection signal set includes four selection signals SS1, SS2, SS3and SS4provided for the four multiplexers MUX1, MUX2, MUX3and MUX4, respectively. In response to respective selection signals SS1, SS2, SS3and SS4, four source signals are selected and outputted by the four multiplexers MUX1, MUX2, MUX3and MUX4, respectively, as multiplexing output signals MS1, MS2, MS3and MS4. Afterwards, AND operations are performed by the AND gates AND1, AND2, AND3and AND4. In the AND gate AND1, an AND operation of a first decoding signal DS1from the selection-signal generating circuit423, which will be described later, a specific source signal that is S24in this example and will be described later, and the multiplexing output signal MS1are performed to obtain a gate output signal GS1. In a similar way, gate output signals GS2, GS3and GS4can also be obtained by AND) operations of corresponding decoding signals DS2, DS3and DS4, multiplexing output signals MS2, MS3and MS4, and specific source signals S16, S8and S0. The gate output signals GS1, GS2, GS3and GS4are further inputted into the first OR gate OR1to be OR-operated, thereby obtaining the first output signal.

Likewise, the second selection signal set includes four selection signals SS5, SS6, SS7and SS8provided for the four multiplexers MUX5, MUX6, MUX7and MUX8, respectively. In response to respective selection signals SS5, SS6, SS7and SS8, four source signals are selected and outputted by the four multiplexers MUX5, MUX6, MUX7and MUX8, respectively, as multiplexing output signals MS5, MS6, MS7and MS8. Afterwards, AND operations are performed by the AND gates AND5, AND6, AND7and AND8. In the AND gate AND5, an AND operation of a fifth decoding signal DS5from the selection-signal generating circuit423, which will be described later, a specific source signal that is S24in this example and will be described later, and the multiplexing output signal MS5are performed to obtain a gate output signal GS5. In a similar way, gate output signals GS6, GS7and GS8can also be obtained by AND operations of corresponding decoding signals DS6, DS7and DS8, multiplexing output signals MS6, MS7and MS8, and specific source signals S16, S8and S0. The gate output signals GS5, GS6, GS7and GS8are further inputted into the second OR gate OR2to be OR-operated, thereby obtaining the second output signal.

It is to be noted that the invention can work even if signal synthesizing circuits424and425do not include those AND gates AND1˜AND8, and the OR gates OR1and OR2directly process the multiplexing output signals MS1˜MS8instead of the gate output signals GS1˜GS8. The presence of the AND gates AND1˜AND8, however, permits two or more delay periods in one positive half cycle of the high frequency signal. For example, as shown inFIG. 2B, two delay periods d1and d2are generated within the first positive half cycle of the high frequency signal.

The specific source signals, such as S24, S16, S8and S0used in the above embodiment, are required to be four clock cycles leading or lagging all the source signals inputted into the corresponding multiplexers. Such requirement is for avoiding the effect of the unused source signals on the first and the second output signals. For example, as shown inFIG. 5A, the eight source signals inputted into the multiplexer MUX2are S27˜S20, and the source signal S16leading all the source signals S27˜S20by four clock cycles of the first clock signal is selected as the specific source signal to be inputted in and operated by the AND gate AND2. Accordingly, when the specific source signal S16is at a low level, the gate output signal GS2is assured to be at a low level no matter what the states of the eight source signals S27˜S20are. In other words, the source signals S27˜S20have no effect on the electric state of the first output signal. In another example, as shown inFIG. 5B, the eight source signals inputted into the multiplexer MUX7are S19˜S12, and the source signal S8leading all the source signals S19˜S12by four clock cycles of the second clock signal is selected as the specific source signal to be inputted in and operated by the AND gate AND7. Accordingly, when the specific source signal S8is at a low level, the gate output signal GS7is assured to be at a low level no matter what the states of the eight source signals S19˜S12are. In other words, the source signals S19˜S12have no effect on the electric state of the second output signal.

The decoding signals DS1˜DS8are generated by the selection-signal generating circuit423, which will be described herein with reference to FIG.6. The selection-signal generating circuit423includes a first and a second selection signal decoder4233and4234. The first selection signal decoder4233is coupled to four operating units OU1, OU2, OU3and OU4and four output units PU1, PU2, PU3and PU4, and the second selection signal decoder4234is coupled to four operating units OU5, OU6, OU7and OU8and four output units PU5, PU6, PU7and PU8. In response to the first and the second clock signals, decoding signals DS1˜DS4and decoding signals DS5˜DS8are generated by the first and the second selection signal decoder4233and4234, respectively. The decoding signals DS1˜DS4are inputted into the four operating units OU1, OU2, OU3and OU4along with the four sub-groups of source signals to generate four output control signals OC1, OC2, OC3and OC4, respectively. For example, the output control signal OC1is outputted by the operating unit OU1in response to the decoding signal DS1and the source signals S3, S2, S1, S0, S31, S30, S29and S28. Likewise, the decoding signals DS5˜DS6are inputted into the four operating units OU5˜OU8along with the four corresponding sub-groups of source signals to generate four output control signals OC5, OC6, OC7and OC8, respectively. Then, the output units PU1˜PU8coupled to the operating units OU1˜OU8receive the output control signals OC1˜OC8and the decoding signals DS1˜DS8, and output the selection signals SS1˜SS8to the multiplexers MUX1˜MUX8in response to the first and the second clock signals, respectively. The decoding signals DS1˜DS8are further transmitted to the AND gates AND1˜AND8for the operations mentioned above with reference toFIGS. 5A and 5B.

In this embodiment, each of the operating units OU1˜OU8can be an OR gate to perform OR operation of the eight source signals belonging to the same sub-group. Each of the output units PU1˜PU8can be a transparent latch.

After the first and the second output signals are obtained, they are inputted into the logic operator43, as shown inFIG. 4, to be logically operated, thereby obtaining the delay signal with desired delay length. Please refer to FIG.7A. The logic operator43includes a storage unit431and a logic operation unit433. The storage unit431includes a first and a second T flip-flops4311and4312for respectively storing therein the first and the second input signals received from the source-signal selector42. The first and the second output signals are then processed by an XOR operation in the logic operation unit433that is implemented by an XOR gate.

Another embodiment of the logic operator43is shown in FIG.7B. The logic operator43includes a storage unit432and a logic operation unit433. The storage unit432includes a first and a second R-S latches4321and4322for respectively storing therein the first and the second input signals received from the source-signal selector42. The first and the second output signals are then processed by an XOR operation in the logic operation unit433that is implemented by an XOR gate.

By using the present method and device to generate a delay signal, the delay signal is accurate, and the delay period is adjustable. Therefore, the desired constant phase difference between the cross-chip signals in a high-frequency system can be assured of.