Intrusion detection and communication

An intrusion detection system disclosed herein includes a detector circuit that measures a change in value of impedance of an interconnection circuitry. A decoder coupled to the detector decodes the measured value of the change in the impedance of the interconnection circuitry to determine existence of an abnormal condition. In an example implementation of the intrusion detection system, the change in the value of the impedance of the interconnection circuitry is represented by a change in the phase delay on the interconnection circuitry. An implementation of the intrusion detection circuit terminates communication using the interconnection circuitry upon detection of the abnormal condition. The intrusion detection system is further configured to interpret the abnormal condition as a communication signal to the interconnection circuitry.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. 13/334,054, entitled “Side Channel Communications” and filed concurrently herewith, which is specifically herein incorporated by reference for all that it discloses and teaches. This application takes priority from U.S. Provisional Patent Application No. 61/525,142, entitled “Side Channel Communications” and filed on Aug. 18, 2011, which is incorporated herein by reference for all that is discloses and teaches.

BACKGROUND

Electronic devices communicate with each other using a number of different methods. For example, integrated circuits (ICs) use input and output pins to communicate with other ICs or other devices. Such input and output pins are connected to other components or ICs using communication lines such as wires, traces, cables, etc. Because such communication lines connecting the devices carry information, they are natural targets for hackers or other parties that are interested in getting unauthorized access to the information being communicated on such communication lines. For example, by tapping an external lead onto a wire connecting two devices, a third party can access information being communicated on that wire and/or affect the information being communicated between the two devices. Furthermore, such communication lines between electronic devices are also the likely locations for integrating external unauthorized devices such as probes, which also affect the performance of the electronic devices and the ICs. For example, addition of the external components drains power, therefore, affecting the length of battery usage.

The security of the communications between the devices on a circuit board can be improved by encrypting the communication between the devices on the circuit board. However, such encryption does not necessarily prevent simple intrusion or attacks. Furthermore, such encryption techniques also do not defend against a determined adversary that is interested in capturing a large volume of communications for off-line decryption analysis. Moreover, using such encryption techniques adversely affects the speed of communication between the devices and the time necessary for processing of the communicated information.

SUMMARY

Implementations described and claimed herein address the foregoing problems by providing an intrusion detection system for detecting intrusion or tampering of digital circuitry. The intrusion detection system includes a circuit board including various integrated circuits (ICs) and an interconnection circuitry connecting the ICs. A detector circuit measures a change in the value of an impedance of the interconnection circuitry to generate a difference signal. A decoder circuit coupled to the detector circuit decodes the difference signal to determine the existence of an abnormal condition such as an intrusion of the circuit board. The intrusion detection system sends a notification signal to an authority if an intrusion of the circuit board is detected.

DETAILED DESCRIPTIONS

The intrusion detection system disclosed herein allows detecting external intrusion into a circuit board by measuring a change in the operating characteristic of an interconnection circuitry of the circuit board. For example, the impedance of an interconnection circuitry connecting two integrated circuits (ICs) located on the circuit board is monitored to determine any abnormal changes in the impedance. If an intruder, such as a hacker, attempts to tamper with the circuit board, such tampering changes the impedance of the interconnection circuitry. The intrusion detection system monitors the value of such impedance to detect any tampering.

In an implementation of the intrusion detection system, a phase delay for a signal communicated on an interconnection circuitry between two ICs is used to monitor the impedance of the external connection pin. Monitoring such phase delay allows proper communication, for instance to keep two external signals synchronized. Because the length and other characteristics of the interconnection circuitry, such as the resistance, the temperature, the inductance, etc., connecting the two ICs are not known in advance, the phase delay is computed dynamically during an initial (or subsequent) calibration phase. For example, a baseline value of the phase delay for the signal transmitted on the interconnection circuitry is stored in a memory and compared with the periodically measured value of the phase delay. A decoder circuit evaluates the difference between the baseline value of the phase delay and the measured value of the phase delay. In the absence of any tampering of the circuit board, such difference is expected to be less than a threshold value. Therefore, if the value of such difference is above the threshold value, the detector generates an intrusion detection signal representing circuit board tampering or intrusion. The phase delay is dynamically affected by additional factors such as temperature, but these effects are much smaller compared to effect of either the length of the wire (that cannot change dynamically) or the additional impedance of a tampering device.

In one implementation, the intrusion detection system includes an actuator circuit that terminates communication using the internal circuit in response to receiving the intrusion detection signal. In an alternative implementation, the actuator circuit causes the internal circuit to operate in a specialized debugging mode in response to receiving the intrusion detection signal. Other implementations of the intrusion detection system monitor multiple internal circuitries on a circuit board to detect presence of external intrusion. In yet alternative implementation, the actuator interprets the intrusion detection signal to generate a communication signal communicated by the circuit board via an external transmitter.

FIG. 1illustrates example data sources and flows for an intrusion detection system100for a device using a circuit board102. In one implementation, the circuit board102is a digital circuit using various digital components, such as CMOS digital components, field-programmable gate array (FPGA) components, etc. The circuit board102includes a first internal circuit106communicating with a second internal circuit108using an interconnection circuitry110. In one implementation, the first internal circuit106and the second internal circuit108are integrated circuits (ICs). The first internal circuit106and the second internal circuit108communicate with each other and with other components of the circuit board102using various input/output pins112. The phase delay relationship between the first internal circuit106and the second internal circuit108is relatively stable if no changes are made to the operating characteristics and operating conditions of the circuit board102, and especially the interconnection circuitry110linking the two ICs. Furthermore, the phase delay between the first internal circuit106and the second internal circuit108can be measured by implementing simple digital logic structures inside the internal circuits106and108.

Such phase delay relationship between the first internal circuit106and the second internal circuit108depends, upon other things, on the impedance of the interconnection circuitry110. The impedance of interconnection circuitry110is a function of a number of parameters, including the capacitance, the resistance, and the inductance on the interconnection circuitry110. Specifically, the impedance of the interconnection circuitry110depends on the structural characteristics of the interconnection circuitry110, the structural characteristics of the first internal circuit106, and the structural characteristics of the second internal circuit108. Typically, the impedance of the interconnection circuitry110does not change substantially from its initial value after the manufacturing of the circuit board102.

The impedance of the interconnection circuitry110affects various operating characteristics of the interconnection circuitry110, such as the phase delay for the signals communicated over the interconnection circuitry110, the slew rate of the signals communicated over the interconnection circuitry110, etc. For example, a signal diagram120illustrates the timeline for communications between the first internal circuit106and the second internal circuit108. Specifically, the signal diagram120illustrates a signal122being communicated from the first internal circuit106to the second internal circuit108. For example the signal122is a square wave signal that communicates particular information from the first internal circuit106to the second internal circuit108.

The impedance of the interconnection circuitry110affects the time at which the output on the interconnection circuitry110crosses VH, the threshold voltage for a logic “1” value of the signal122. This is illustrated by the actual value of the signal124on the interconnection circuitry110. As shows in the signal diagram120, a slew time tslew126represents the time it takes for the signal124on the interconnection circuitry110to rise to the threshold voltage VH. The slew time tslew126also represents the time it takes for the signal124on the interconnection circuitry to decline from its peak value to the lower threshold voltage VL.

The slew time tslew126is detected by a detector130. In one implementation of the intrusion detection system100, the detector saves the slew time tslew126as the baseline delay132. For example, the baseline delay132is saved in a memory on the circuit board102. The baseline delay132depends on the operational characteristics of the interconnection circuitry110. Specifically, the baseline delay132depends on the cumulative capacitive, resistive, and inductive load of the various wires and other pins connected to a source internal circuit generating the signal on the interconnection circuitry110, such as the first internal circuit106, the delay characteristics of the source internal circuit generating the signal, and the drive strength of the signal generated by the source internal circuit generating the signal.

In one implementation, the baseline delay132is determined relatively soon after the manufacturing of the circuit board102. In such an implementation, the baseline delay132is stored in a non-volatile memory (not shown) on the circuit board102for future field use. In an alternative implementation, the baseline delay132is determined upon first use of the circuit board102in the field. In such a case, the baseline delay132also reflects the environmental operating condition of the circuit board102.

FIG. 1also illustrates an instance of an intrusion detection system140where a circuit board142is tampered with by an external tampering device160. The circuit board142includes a first internal circuit146communicating with a second internal circuit148using an interconnection circuitry150. The first internal circuit146and the second internal circuit148communicate with each other and with other components of the circuit board142using various input/output pins152. The impedance of interconnection circuitry150is a function of a number of parameters, including the capacitance, the resistance, and the inductance of the interconnection circuitry150. Specifically, the impedance of the interconnection circuitry150depends on the structural characteristics of the interconnection circuitry150, the structural characteristics of the first internal circuit146, and the structural characteristics of the second internal circuit148.

The tampering device160communicates with the interconnection circuitry150using a sensing wire162. For example, the tampering device160is a sensor probe that is configured to read the information being communicated over the interconnection circuitry150. In such a case, the tampering device160connects to the interconnection circuitry using a probe wire used as the sensing wire162. In an alternative case, the tampering device160not only reads information being communicated over the interconnection circuitry150, but it also changes such information being communicated over the interconnection circuitry150. The connection of the sensing wire162to the interconnection circuitry150affects the operating characteristics, such as the impedance of the interconnection circuitry150. The change in the impedance of the interconnection circuitry150also causes a change in the phase delay for the signal being communicated over the interconnection circuitry150. For example, in a particular case, the connection of the sensing wire162to the interconnection circuitry150increases the capacitance of the interconnection circuitry150. Such increased capacitance of the interconnection circuitry150causes the phase delay and the slew rate of the signal being communicated over the interconnection circuitry150to increase as well. In another alternative implementation, the tampering device160replaces the first internal circuit146. Such replacing of the internal circuit146also affects the operating characteristics, such as the impedance of the interconnection circuitry150, which in turn, causes a change in the phase delay for the signal being communicated over the interconnection circuitry150.

A signal diagram170illustrates the timeline for the communication between the first internal circuit146and the second internal circuit148in the presence of the tampering device160and the sensing wire162. Specifically, the signal diagram170illustrates a signal172being communicated from the first internal circuit146to the second internal circuit148. For example the signal172is a square wave signal that communicates particular information from the first internal circuit146to the second internal circuit148.

The impedance of the interconnection circuitry150affects the point at which the output on the interconnection circuitry150crosses VH, the threshold voltage for a logic “1” value of the signal172. This is illustrated by the actual value of the signal174on the interconnection circuitry150. As shows in the signal diagram170, a slew time tslew176represents the time it takes for the signal174on the interconnection circuitry150to rise to the threshold voltage VH. The slew time tslew176also represents the time it takes for the signal174on the interconnection circuitry150to decline from its peak value to the lower threshold voltage VL.

The slew time tslew176is detected by a detector180. In one implementation of the intrusion detection system100, the detector saves the slew time tslew176as the test delay182. For example, the test delay182is saved in a memory on the circuit board142. The test delay182depends on the operational characteristics of the interconnection circuitry150. Specifically, the test delay182depends on the cumulative capacitive, resistive, and inductive loads of the various wires and other pins connected to a source internal circuit generating the signal on the internal circuit150, such as the first internal circuit146, the delay characteristics of such source internal circuit, and the drive strength of the signal generated by such source internal circuit.

Because the interconnection circuitry150is connected to the sensor wire162, the operating characteristics of the interconnection circuitry150are different than the operating characteristics of the interconnection circuitry110. As a result, the test delay182is also different from the baseline delay132. In the illustrated implementation of the circuit board142, the test delay182is greater than the baseline delay132. This is also represented by the slew time tslew176being larger than the slew time tslew126. Thus, in effect, the signal174takes longer time to reach the threshold voltage VHcompared to the time taken by the signal124to reach the threshold voltage VH.

The baseline delay132and the test delay182are communicated to a decoder190. The decoder190analyzes the values of the baseline delay132and the test delay182to determine if there has been any tampering with the circuit board142. For example, the decoder190calculates the difference between the baseline delay132and the test delay182and evaluates the difference to determine if there has been any tampering with the circuit board142. If the difference between the baseline delay132and the test delay182is larger than a threshold difference, the decoder190determines that there has been some kind of tampering with the circuit board142.

The value of the threshold used by the decoder190to determine whether a difference between the baseline delay132and the test delay182signifies a tampering of the circuit board142is determined based on expected variances in the operating characteristics of the circuit board142. For example, the phase delay on the interconnection circuitry150is expected to vary from the baseline delay132within a small range due to changes in the operating condition of the circuit board140, the changes in the temperature of the circuit board140, etc. In one implementation, the threshold value used by the decoder190is changed periodically to reflect such changes in the operating conditions of the circuit board140.

Upon detection of tampering with the circuit board140, the decoder190generates an intrusion detection signal192. In one implementation, the intrusion detection signal192is a binary signal that indicates whether there has been a tampering with the circuit board140. In an alternative implementation, the intrusion detection signal192also identifies the level of intrusion. For example, if the difference between the baseline delay132and the test delay182is significantly large, the decoder190generates an intrusion detection signal192that also quantifies the size of such difference. In such an implementation, the analysis of the intrusion detection signal192also allows the intrusion detection system100to determine the type of tampering with the circuit board140.

The intrusion detection signal192is communicated to an actuator194that is configured to take an action in response to the intrusion detection signal192. For example, the actuator194causes the circuit board140to enter into a specialized debugging mode where the user of the circuit board140can easily test the functioning of the circuit board140. In one implementation, such debugging mode operation of the circuit board140is implemented in a manner so that no external debugging connections are required. In an alternative implementation, the actuator194causes the communication over the interconnection circuitry150to be terminated so that the tampering device160cannot access any further information being communicated over the interconnection circuitry150. Furthermore, the actuator194also communicates the information about the tampering to an external authority or other entity monitoring the functioning of the circuit board140.

In an alternative implementation, the internal circuits106and108are configured to self-monitor any tampering with various interconnection circuits attached to their input/output pins. For example, the internal circuit106is configured to monitor an operating characteristic of the interconnection circuit150attached to its output pin. In such an implementation, a change in the operating characteristic of the interconnection circuit150causes the first internal circuit106to terminate any outgoing communication, including any communication with the second internal circuit108using the interconnection circuit150.

While the intrusion detection system100uses the phase delay relationship between various internal circuits on a circuit board to determine presence of the circuit board tampering, in an alternative implementation, other operating characteristics, such as the timing of communication between the internal circuits is used to determine such presence of tampering.

FIG. 2illustrates alternative example data sources and flows for an intrusion detection system200. Specifically, the intrusion detection system200includes a circuit board202including a first internal circuit206communicating with a second internal circuit208using an interconnection circuitry210. The first internal circuit206and the second internal circuit208communicate with each other and with other components of the circuit board202using various input/output pins212. The timing for the communication over the interconnection circuitry210is a function of various operational characteristics of the circuit board202, including the impedance of the interconnection circuitry210.

A signal diagram220illustrates the timeline for communications between the first internal circuit206and the second internal circuit208. Specifically, the signal diagram220illustrates a timing222between a transmit time224when a signal is transmitted from the first internal circuit206and a receipt time226when the signal is received at the second internal circuit208. In one implementation, the first internal circuit206and the second internal circuit208cooperate with each other to share the value of the transmit time224and the receipt time226. For example, if the timing222is determined at the second internal circuit208, the first internal circuit206communicates the transmit time224to the second internal circuit208with respect to a shared clock signal. The detector230stores the timing222as the baseline timing232.

FIG. 2also illustrates an instance of the intrusion detection system240where a circuit board242is tampered with by an external tampering device260. The circuit board242is illustrated to have a first internal circuit246communicating with a second internal circuit248using an interconnection circuitry250. The first internal circuit246and the second internal circuit248communicate with each other and with other components of the circuit board242using various input/output pins252. The timing for the communication over the interconnection circuitry250is a function of various operational characteristics of the circuit board242, including the impedance of the interconnection circuitry250.

A signal diagram270illustrates the timeline for communications between the first internal circuit246and the second internal circuit248. Specifically, the signal diagram270illustrates a timing272between a transmit time274when a signal is transmitted from the first internal circuit246and a receipt time276when the signal is received at the second internal circuit248. The detector280stores the timing272as the test timing282.

Each of the baseline timing232and the test timing282are communicated to a decoder290. The decoder290analyzes the values of the baseline timing232and the test timing282to determine if there has been any intrusion of the circuit board242. For example, the decoder290calculates the difference between the baseline timing232and the test timing282and evaluates the difference to determine if there has been any tampering with the circuit board242. If the difference between the baseline timing232and the test timing282is larger than a threshold difference, the decoder290determines that there has been some kind of tampering with the circuit board242.

Upon detection of tampering with the circuit board240, the decoder290generates an intrusion detection signal292. In one implementation, the intrusion detection signal292is a binary signal that indicates whether there has been a tampering with the circuit board240. In an alternative implementation, the intrusion detection signal292also identifies the level of intrusion. The intrusion detection signal292is communicated to an actuator294that is configured to take an action in response to the intrusion detection signal292. For example, the actuator294causes the circuit board240to enter into a specialized debugging mode where the user of the circuit board240can easily test the functioning of the circuit board240. In an alternative implementation, the actuator294causes the communication over the interconnection circuitry250to be terminated so that the tampering device260cannot access any further information being communicated over the interconnection circuitry250.

FIG. 3illustrates alternative example data sources and flows for an intrusion detection system300. The intrusion detection system300includes a circuit board302including various components. Specifically, the circuit board302includes a first internal circuit306and a second internal circuit308. In one implementation, each of the first internal circuit306and a second internal circuit308are ICs that communicate with each other and with other components of the circuit board302using various input/output pins312. For example, the first internal circuit306and the second internal circuit308communicate with each other using an interconnection circuitry310that is attached to such input/output pins312.

The intrusion detection system300also includes an internal clock314on the circuit board302to generate a clock signal. While the illustrated implementation of the intrusion detection system300illustrates the internal clock314as being external to the first internal circuit306and the second internal circuit308, in an alternative implementation, the internal clock314is implemented on one of the first internal circuit306and the second internal circuit308using the existing components of one of the first internal circuit306and the second internal circuit308.

The second internal circuit308includes a variable delay element316that delays an incoming signal318on the interconnection circuitry310by a variable amount of delay. The incoming signal318is a signal communicated to the second internal circuit308from the first internal circuit306. The variable delay element316outputs a delayed incoming signal320that is input to an alignment detection module322. The alignment detection module322measures the phase delay of the delayed incoming signal320using the clock signal generated by the internal clock314to determine the phase delay on the delayed incoming signal320.

The phase delay relationship between the first internal circuit306and the second internal circuit308is expected to be relatively stable if no changes are made to the first internal circuit306, the second internal circuit308, and the interconnection circuitry310. As a result, a predetermined amount of phase delay is expected between a signal received at the second internal circuit308from the first internal circuit306and an internal signal generated by the second internal circuit308. Such predetermined amount of phase delay is expected to be relatively stable. To detect the changes in the phase delay relationship between the first internal circuit306and the second internal circuit308, the variable delay element316delays the incoming signal318by the expected amount of phase delay.

The intrusion detection system300includes a tampering device330that is communicatively connected to the interconnection circuitry310via a sensing wire332. In one implementation, the tampering device330is a probe that is configured to read the information being communicated over the interconnection circuitry310. Connecting the sensing wire332to the interconnection circuitry310affects the capacitance, the resistance, and/or the inductance on the interconnection circuitry310, resulting in a changed impedance of the interconnection circuitry310. The changed impedance affects that relatively stable phase delay relationship between the first internal circuit306and the second internal circuit308. As a result, the phase delay on the incoming signal318varies from its stable state value. The alignment detection module322detects such change in the phase delay of the incoming signal318from its stable state value.

The functioning of the alignment detection module322is explained in further detail in a signal diagram340. The clock signal342illustrates the clock signal generated by the internal clock314. The signal344illustrates the delayed incoming signal320in the absence of any changes to the operating characteristics of the circuit board302. The signal344has a slew rate of346, which indicates the time required for the signal344to rise from a low value to VH. The slew rate346is measured using the clock signal342. In one implementation, the slew rate346in the absence of any tampering with the circuit board302is stored in a memory360of the circuit board as the baseline slew rate. For example, the memory360is a random access memory (RAM), a read only memory (ROMs), or other types of memory implemented in the circuit board302.

The signal348illustrates the delayed incoming signal320in the presence of the tampering device330and the sensing wire332. The signal348has a slew rate of350, which indicates the time required for the signal348to rise from a low value to VH. In the illustrated implementation, the presence of the tampering device330and the sensing wire332affects the operating characteristics of the interconnection circuitry310in such a manner so as to increase the slew rate of the delayed incoming signal320. However, in an alternative case, the presence of the tampering device330and the sensing wire332affects the operating characteristics of the interconnection circuitry310in such a manner so as to decrease the slew rate of the delayed incoming signal320. The slew rate350is measured using the clock signal342. The slew rate350in the presence of tampering with the circuit board302is also stored in a memory360of the circuit board as the test slew rate.

Given that the difference between the slew rate344and the slew rate350is generally small, an implementation of the intrusion detection system300uses an internal clock with a very high clock speed. For example, in one implementation, such internal clock speed is up to ten times the clock speed generally used by the first internal circuit306and the second internal circuit308. In alternative implementations, other methods for determining phase delay, such as a method using a binary search operation that iteratively delays an incoming signal over a number of cycles is used. Yet alternatively, a calibration system that track transition of the signal244or a calibration system that stores the known patterns of the signal244to track the changes to the slew rate are used. An example of such calibration system is the method used to measure input signal delay in a double data rate synchronous dynamic memory system that uses a calibration state machine that locks on particular cycle/edge of an input signal to subsequently measure the changes to the input signal delay.

The intrusion detection system300also includes a decoder370that is configured to decode the change in the phase delay relationship between the first internal circuit306and the second internal circuit308. For example, the decoder370evaluates a difference between the baseline slew rate and the test slew rate to determine presence of tampering of the circuit board302. If the difference is relatively small, the decoder370determines that there is no tampering with the circuit board302. However, if the difference is relatively large, the decoder370generates an output signal representing tampering with the circuit board302. In one implementation, the decoder370uses a threshold value to evaluate the difference between the baseline slew rate and the test slew rate. In such implementation, if such difference is higher than the threshold, the decoder370generates an output signal representing tampering with the circuit board302.

The decoder370communicates the output signal to an actuator380. The actuator380is configured to take various actions in response to the output signal from the decoder370. For example, if the output signal from the decoder370specifies tampering with the circuit board302, the actuator380causes the circuit board302to enter into a debugging mode. In one implementation of the intrusion detection system300, the circuit board302operates in a specialized debugging mode that allows a user to test the operation of the circuit board302without any specialized external debugging ports implemented on the circuit board302during manufacturing of the circuit board302. In an alternative implementation, the actuator380ceases communication between the first internal circuit and306and the second internal circuit308to minimize the tampering device330getting any further useful information. The actuator380also generates a signal to an authority, such as an operator of the system using the circuit board302with a notification about the tampering with the circuit board302.

While the implementation of the intrusion detection system300allows detecting tampering or hacking with the circuit board302using the phase delay relationship between two internal circuits, in an alternative implementation, such phase delay relationships between two internal circuits can also be used for communicating information to the circuit board.

FIG. 4illustrates an implementation of a communication system400using the phase delay relationships of various internal circuits on a circuit board402. The communications system400includes a number of external transmitters304-310that are configured to communicate with the circuit board402. The circuit board402includes various interconnection circuitries414,418,416, and420. Each of the interconnection circuitries414,418,416, and420is configured to communicate between various internal circuits. For example, the interconnection circuitry414communicates between a first internal circuit A1and a second internal circuit A2.

The external transmitters404-410are configured to transmit external information signals to the interconnection circuitries414-420by affecting the phase delay relationships on the interconnection circuitries414-420. For example, the external transmitter404sends a signal424to the interconnection circuitry A414, the external transmitter406sends a signal426to the interconnection circuitry B416, etc. Specifically, each of the external transmitters404-410is configured to send a signal to a particular interconnection circuitry of the receiver device302so as to affect the phase delay relationship between two internal circuits connected by that particular interconnection circuitry. Thus, for example, the external transmitter404sends the signal424to the interconnection circuitry A414so as to affect the phase delay relationship between the internal circuit A1and the internal circuit A2.

Each of the interconnection circuitries414-420is associated with one of the decoders434-440. Each of the decoders434-440is configured to measure and decode the change in the phase delay characteristics of the corresponding interconnection circuitries414-420. For example, the decoder A434is configured to measure a phase delay and a change in the phase delay on the interconnection circuitry414. Furthermore, the decoder A434is also configured to store such measured value of the phase delay, a value of the change in the phase delay, etc., into a memory of the decoder A434.

The communication signal424from the external transmitter A404causes the phase delay on the interconnection circuitry414to change. For example, a positive communication signal424causes the phase delay on the interconnection circuitry414to increase. The decoder A434measures such change in the phase delay and compares the change to a threshold value. If the decoder A434determines that the detected change in the phase delay is above the threshold, it generates a bit “1” as the information communicated by the external transmitter A404.

In a similar manner, the other external transmitters406,408,410also send information to the interconnection circuitries416,418,420. The corresponding decoders436,438,440decode the information communicated by the signals426,428,430to generate output bits. The implementation of the communications system400illustrates that when the decoder A434generates a bit “1” as the value of the information communicated by the external transmitter404, the other decoders436,438,440generate output bit values of “0,” “1,” and “0.” As a result, cumulative output from the decoders434-440is “1010”450.

While the communications system400illustrates the circuit board402as having four interconnection circuitries414-420, in an alternative implementation, a greater or a lesser number of interconnection circuitries is provided. Furthermore, in an alternative implementation, each of the external transmitters404-410is implemented on a same transmitter device and a single decoder device is used to implement each of the decoders434-440.

The maximum transfer rate that can be achieved by the communications system400depends on a number of factors including the number of distinct channels used for communicating with the circuit board402, the distinct changes in phase delays on the interconnection circuitries414-420used for communication, the range over which the phase delay is varied, the speed at which the external transmitters404-410affect the phase delays on the interconnection circuitries414-420, etc.

FIG. 5illustrates example operations500for an intrusion detection system for detection of tampering with a circuit board. A receiving operation502receives an incoming signal at an internal circuit. For example, the incoming signal is a signal from a first internal circuit on the circuit board to a second internal circuit on the circuit board. The phase delay of the incoming signal from the first internal circuit compared to a signal generated by the second internal circuit is a function of the operating characteristics of the first internal circuit, the operating characteristics of the second internal circuit, and the operating characteristics of an interconnection circuitry connecting the first internal circuit and the second internal circuit. Such phase delay is generally stable in absence of any changes to the operating characteristics.

A delaying operation504delays the incoming signal iteratively so that the phase of an internal clock signal and the phase of the delayed incoming signal are approximately locked. In one implementation, the delaying operation504delays the incoming signal iteratively according to a binary search process until the phase of the delayed incoming signal and the phase of an internal clock are approximately locked. Subsequently, a calculating operation506calculates the phase delay of the delayed incoming signal. In one implementation, the calculating operation506calculates the slew rate of the delayed incoming signal and uses he slew rate as the representation of the phase delay of the delayed incoming signal.

A determining operation508determines the difference between the calculated phase delay and a baseline phase delay. In one implementation, the baseline phase delay between the incoming signal from the first internal circuit compared to an internal signal generated by the second internal circuit is stored on a memory of the circuit board. For example, such baseline phase delay is calculated at the time the circuit board is used for the first time in the field. In an alternative implementation, the baseline phase delay is changed over time to reflect the changes in the operating condition of the circuit board. In one implementation, the difference between the calculated phase delay and the baseline phase delay is the difference between the calculated slew rate and a baseline slew rate stored in the memory on the circuit board.

Subsequently, an evaluating operation510evaluates the difference between the calculated phase delay and a baseline phase delay. In one implementation, the evaluating operation510compares such difference with a threshold value. The threshold value used by the evaluating operation is stored in a memory of the circuit board and specifies what level of phase delay is considered significant in representing an intrusion of the circuit board. For example, a relatively small difference between the calculated phase delay and a baseline phase delay is considered to be a result of minor changes in the operating conditions of the circuit board and therefore do not represent an intrusion to the circuit board.

If the evaluating operation510determines that the value of the difference is less than the threshold value, a notification operation516notifies that no intrusion has taken place. In which case, no further action is taken. On the other hand, if the evaluating operation510determines that the value of the difference is greater than or equal to the threshold value, a generating operation518generates an intrusion detection signal. In one implementation, the generating operation518also includes qualitative and/or quantitative information into the intrusion detection signal. For example, the intrusion detection signal includes the amount by which the difference between the calculated phase delay and a baseline phase delay is higher than the threshold.

Subsequently, a terminating operation520terminates communication in the interconnection circuitry. In an alternative implementation, the terminating operation also notifies an authority, such as a user or the circuit board about the potential tampering of the circuit board. Subsequently, an evaluating operation522evaluates the intrusion detection signal. For example, if there is any qualitative and/or quantitative information included in the intrusion detection signal, the evaluating operation522evaluates such information to determine the appropriate course of action. Thus, if the difference between the calculated phase delay and a baseline phase delay is larger than the threshold value by only a small amount, the evaluating operation determines that the circuit board operations can continue for all internal circuits except for the interconnection circuitry on which the intrusion is detected. However, if the difference between the calculated phase delay and a baseline phase delay is significantly larger than the threshold value, the evaluating operation determines that the entire circuit board be operated in a special debugging mode.

FIG. 6illustrates example operations600for determining phase delay of an incoming signal at an internal circuit on a circuit board. For example, the operations600are used to determine a change in the slew rate of an incoming signal at an internal circuit. An implementation of the intrusion detection system disclosed herein uses the operations600to determine a delay in a signal received at an input pin of an internal circuit. The operations600illustrate calculating the phase delay of an incoming signal using an internal clock signal generated on a second internal circuit. For example, the internal clock signal is a 100 MHz clock signal. An operation602receives the incoming signal. In the illustrated example operations600, the incoming signal from a first internal circuit is also a 100 MHz clock signal. Thus, the periods of both the internal clock signal and the incoming signal are 10.0 ns.

A sampling operation604samples the incoming signal at the positive edge of the internal clock signal with 0.0 ns delay. Subsequently an evaluating operation606evaluates the sampled value of the incoming signal. If the sampled value of the incoming signal is 1, the incoming signal has changed before the positive edge of the internal clock signal. In this case, a binary search operation608performs a binary search to determine the approximate amount of delay.

Specifically, the binary search operation608iteratively delays the incoming signal by delay amounts over a number of cycles with the delay amount for each cycle being increased or decreased by an amount of delay that is equal to half the increment/decrement of the previous cycle. The binary search operation determines the approximate amount of delay between the incoming signal and the internal clock signal when the sampling for a given cycle produces the value of 1 whereas the sampling for the next cycle produces a value of 0.

On the other hand, if the evaluating operation606determines the sampled value of the incoming signal to be 0, the positive edge of the internal clock signal has occurred before the positive edge of the incoming signal. In this case, a delaying operation610delays the incoming signal by more than half the clock cycle, somewhere between 5 and 10 ns. Subsequently, the control is passed to the binary search operation608.

The embodiments of the invention described herein are implemented as logical steps in one or more computer systems. The logical operations of the present invention are implemented (1) as a sequence of processor-implemented steps executing in one or more computer systems and (2) as interconnected machine or circuit modules within one or more computer systems. The implementation is a matter of choice, dependent on the performance requirements of the computer system implementing the invention. Accordingly, the logical operations making up the embodiments of the invention described herein are referred to variously as operations, steps, objects, or modules. Furthermore, it should be understood that logical operations may be performed in any order, unless explicitly claimed otherwise or a specific order is inherently necessitated by the claim language.

The above specification, examples, and data provide a complete description of the structure and use of exemplary embodiments of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended. Furthermore, structural features of the different embodiments may be combined in yet another embodiment without departing from the recited claims.