Thin film transistor array substrate and display apparatus

A thin film transistor array substrate and a display apparatus are disclosed. The thin film transistor array substrate includes a number of scan lines, data lines and pixel units. Each of the pixel units includes a thin film transistor and a pixel electrode. The thin film transistor includes a gate electrode, a source electrode and a drain electrode. The gate electrode is electrically connected to one of the scan lines, the source electrode is electrically connected to one of the data lines, and the drain electrode is electrically connected to the pixel electrode. The source electrode is arranged in a same layer as the data lines while the drain electrode and the source electrode are respectively arranged in different layers. Therefore, the implementation of the present disclosure may augment the PPI (Pixel units per Inch) of display apparatus without reducing its aperture ratio and product yield ratio.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a 35 U.S.C. § 371 National Phase conversion of International (PCT) Patent Application No. PCT/CN2017/107152, filed on Oct. 20, 2017, which claims foreign priority to Chinese Patent Application No. 201710927745.6, filed on Sep. 27, 2017 in the State Intellectual Property Office of China, the entire contents of which are hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure generally relates to the display field, and in particular to a thin film transistor array substrate and a display apparatus.

BACKGROUND

In_Cell is a panel configuration integrating the touch panel (TP) in a thin film transistor liquid crystal display (TFT-LCD), which may make the panel (or the whole apparatus) thinner and lighter. For an ordinary In_Cell panel, augmenting the PPI (Pixel units per Inch) of the panel usually results in a decrease of the aperture ratio and the product yield ratio of the pixel units.

SUMMARY

The present disclosure provides a thin film transistor array substrate and a display apparatus for augmenting the PPI of the display apparatus without reducing its aperture ratio and product yield ratio.

To solve the above-mentioned problem, a technical scheme adopted by the present disclosure is to provide a thin film transistor array substrate, including: a glass substrate; a plurality of scan lines formed on the glass substrate; a plurality of data lines crossing the scan lines; a plurality of pixel units formed at the crossing points of the scan lines and the data lines, each of the pixel units including a thin film transistor and a pixel electrode connected to the thin film transistor, wherein, the thin film transistor comprises a gate electrode, a source electrode and a drain electrode, the gate electrode is electrically connected to one of the scan lines, the source electrode is electrically connected to one of the data lines, the drain electrode is electrically connected to the pixel electrode, the source electrode is arranged in a same layer as the data lines, the drain electrode and the source electrode are respectively arranged in different layers; an active layer arranged above the glass substrate, wherein the gate electrode is arranged above the active layer, the scan lines are arranged on a same layer as the gate electrode, the source electrode and the drain electrode are arranged above the gate electrode and electrically connected to the active layer respectively, and the drain electrode is arranged above the source electrode; and a black matrix arranged between the glass substrate and the active layer, configured to prevent light from the glass substrate entering the active layer.

To solve the above-mentioned problem, another technical scheme adopted by the present disclosure is to provide a thin film transistor array substrate, including: a glass substrate; a plurality of scan lines formed on the glass substrate; a plurality of data lines crossing the scan lines; and a plurality of pixel units formed at the crossing points of the scan lines and the data lines; wherein, each of the pixel units comprising a thin film transistor and a pixel electrode connected to the thin film transistor, the thin film transistor comprises a gate electrode, a source electrode and a drain electrode, the gate electrode is electrically connected to one of the scan lines, the source electrode is electrically connected to one of the data lines, the drain electrode is electrically connected to the pixel electrode, the source electrode is arranged in a same layer as the data lines, the drain electrode and the source electrode are respectively arranged in different layers.

To solve the above-mentioned problem, another technical scheme adopted by the present disclosure is to provide a display apparatus, including a thin film array substrate, wherein the thin film array substrate includes: a glass substrate; a plurality of scan lines formed on the glass substrate; a plurality of data lines crossing the scan lines; and a plurality of pixel units formed at the crossing points of the scan lines and the data lines; wherein, each of the pixel units comprising a thin film transistor and a pixel electrode connected to the thin film transistor, the thin film transistor comprises a gate electrode, a source electrode and a drain electrode, the gate electrode is electrically connected to one of the scan lines, the source electrode is electrically connected to one of the data lines, the drain electrode is electrically connected to the pixel electrode, the source electrode is arranged in a same layer as the data lines, the drain electrode and the source electrode are respectively arranged in different layers.

The present disclosure provides a thin film transistor array substrate and a display apparatus. The thin film transistor array substrate may include a glass substrate, a plurality of scan lines formed on the glass substrate, a plurality of data lines crossing the scan lines, and a plurality of pixel units formed at the crossing points of the scan lines and the data lines. Each of the pixel units may include a thin film transistor and a pixel electrode connected to the thin film transistor. The thin film transistor may include a gate electrode, a source electrode and a drain electrode. The gate electrode is electrically connected to one of the scan lines, the source electrode is electrically connected to one of the data lines, and the drain electrode is electrically connected to the pixel electrode. The source electrode is arranged in a same layer as the data lines while the drain electrode and the source electrode are respectively arranged in different layers. Since the source electrode and the data line are in the same layer while the source electrode and the drain electrode are in different layers, the distance between the drain electrode and the data line will not be reduced when smaller pixel units are made by reducing the distance between two adjacent data lines, i.e., the limit of the drain electrode may be eliminated. Therefore, the position of the drain electrode and the source electrode may be kept and their sizes may be large enough to assure the aperture ratio and the product yield ratio of the pixel units. That is to say, the implementation of the present disclosure may allow augmenting the PPI of the display apparatus without reducing its aperture ratio and product yield ratio of the pixel units.

DETAILED DESCRIPTION

The disclosure will now be described in detail with reference to the accompanying drawings and examples. Apparently, the embodiments described are merely a portion but not all of the embodiments of the present disclosure. Embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts should all belong to the protection scope of the present disclosure.

Referring toFIGS. 1-3,FIG. 1is a schematic diagram of a thin film transistor array substrate according to an embodiment of the present disclosure.FIG. 2is a cross-section view of the pixel unit taken along the line I-II ofFIG. 1.FIG. 3is an enlarged view of the pixel unit of the thin film transistor array substrate ofFIG. 1. As shown inFIG. 1, the thin film transistor array substrate10of this embodiment may include a glass substrate11, multiple scan lines12formed on the glass substrate11, multiple data lines13crossing the scan lines12and multiple pixel units14formed at the crossing points of the scan lines12and the data lines13. Each of the pixel units14may include a thin film transistor T and a pixel electrode100connected to the thin film transistor T.

Referring toFIGS. 2 and 3, in this embodiment, the thin film transistor T may include a gate electrode G, a source electrode S and a drain electrode D. The gate electrode G may be electrically connected to the scan line12. The source electrode S may be electrically connected to the data line13. The drain electrode D may be electrically connected to the pixel electrode100. In this embodiment, the source electrode S may be arranged in a same layer as the data line13while the drain electrode D and the source electrode S are respectively arranged in different layers.

Since the source electrode S and the data line13are in the same layer and the source electrode S and the drain electrode D are in different layers, the distance between the drain electrode D and the data line13will not be reduced when the pixel units14with smaller sizes are made by reducing the distance between two adjacent data lines13, i.e., the limit of the drain electrode D may be eliminated. Therefore, the position and size of the drain electrode D and the source electrode S may be kept and their sizes may be large enough to assure the aperture ratio and the product yield ratio of the pixel units. That is to say, the implementation of the present disclosure may allow augmenting the PPI of the display apparatus without reducing its aperture ratio and product yield ratio of the pixel units14.

In this embodiment, the thin film transistor array substrate10may further include an active layer16disposed above the glass substrate11. The gate electrode G may be disposed above the active layer16and in the same layer as the scan line12. The source electrode S and the drain electrode D may be disposed above the gate electrode G, wherein the drain electrode D may be disposed above the source electrode S. The source electrode S and the drain electrode D may be electrically connected to the active layer16respectively.

In other embodiments, the drain electrode D may be arranged below the source electrode S and the data line13, or in other position as long as the source electrode S and the data line13are in different layers and the active layer16is electrically connected to the pixel electrode100.

In this embodiment, the thin film transistor array substrate10may further include a first insulating layer17, a second insulating layer18, a third insulating layer19and a fourth insulating layer101. The first insulating layer17may be arranged between the active layer16and the gate electrode G. The second insulating layer18may be arranged between the gate electrode G and the source electrode S. The second insulating layer18may define a first guiding hole103which is not closed by the first insulating layer17such that the active layer16may be exposed. The source electrode S may be electrically connected to the active layer16through the first guiding hole103. The third insulating layer19may be arranged between the source electrode S and the drain electrode D. The third insulating layer19may define a second guiding hole104. Neither the first insulating layer17nor the second insulating layer18closes the second guiding hole104such that the active layer16may be exposed. The drain electrode D may be electrically connected to the active layer16through the second guiding hole104. The fourth insulating layer101may be arranged on the drain electrode D. The fourth insulating layer101may define a third guiding hole105for exposing the drain electrode D. The pixel electrode100may be arranged on the fourth insulating layer101electrically connected to the drain electrode D through the third guiding hole105.

In this embodiment, the gate electrode G, the source electrode S and the drain electrode D may include three different metal materials or other conducting materials. Alternatively, they may include the same metal material or conducting material.

In this embodiment, the thin film transistor array substrate10may provide touch function. The thin film transistor array substrate10may further include touch control signal lines15. The touch control signal line15may be arranged in the same layer as the drain electrode D. The touch control signal line15and the drain electrode D may include the same material and formed with one photolithography process such that the cost will not be increased. In other embodiments, the touch control signal line15and the drain electrode D may include different materials.

The touch control signal line15may be disposed above the data line13and parallel to the data line13. Since the number of the touch control signal lines15is determined by the number of touch control units, and the number of touch control units is less than the pixel units, not all the data lines13have a touch control signal line15disposed above. More specifically, referring toFIG. 3, the pixel units Sub1, Sub2and Sub3are pixel units in a same line which may display different colors. Among the pixel units in the same line, at least one of two adjacent pixel units14does not have the touch control signal line15disposed above. As shown inFIG. 3, the pixel units Sub2and Sub3may have the touch control signal lines15disposed above while the pixel unit Sub1does not. Among the pixel units in a same line, the distance d1between the drain electrode D and the touch control signal line15may be larger than the distance d2between the drain electrode D and the data line13of an adjacent pixel unit, which is the configuration of Sub2. Since the touch control signal line15is parallel to the data line13, the distance d between the drain electrode D of the pixel unit Sub2and its data line13may be larger than the distance d2between the drain electrode D and the data line13of the adjacent pixel unit. Alternatively, the distance d2between the drain electrode D and the touch control signal line15may be larger than the distance d1between the drain electrode D of a pixel unit and its data line13, which is the configuration of Sub3. Similarly, the distance d1between the drain electrode D of the pixel unit Sub3and its data line13may be smaller than the distance d2between the drain electrode D and the data line13of an adjacent pixel unit. Therefore, the electrical connection of the drain electrode D and the touch control signal line15may be avoided such that the pixel units may function normally when the size of the pixel units are reduced. As a result, it is possible to augment the PPI of panel.

It should be noted that for the pixel unit Sub1which does not include the touch control signal line15, the distance d1between its drain electrode D and its data line13may be equal to the distance d2between its drain electrode D and the data line13of an adjacent pixel unit.

Referring toFIG. 2, the thin film transistor array substrate10may further include a black matrix102. The black matrix102may be arranged between the glass substrate11and the active layer16. The black matrix102may be configured to prevent light from the glass substrate11entering the active layer16.

Correspondingly, the implementation of the present disclosure may allow augmenting the PPI of display apparatus without reducing the aperture ratio and product yield ratio of its pixel units14.

Referring toFIG. 4, the present disclosure further provides a display apparatus.

As shown inFIG. 4, according to an embodiment, the display apparatus40may include a thin film transistor array substrate41, a color filter substrate42and a liquid crystal layer43. The thin film transistor array substrate41and the color filter substrate42may be disposed correspondingly. The liquid crystal layer43may be arranged between the thin film transistor array substrate41and the color filter substrate42. The thin film transistor array substrate41is the thin film transistor array substrate10as set forth and will not be described hereon.

As a conclusion, the implementation of the present disclosure allow augmenting the PPI of display apparatus without reducing the aperture ratio and product yield ratio of its pixel units14.

The foregoing is merely embodiments of the present disclosure, and is not intended to limit the scope of the disclosure. Any transformation of equivalent structure or equivalent process which uses the specification and the accompanying drawings of the present disclosure, or directly or indirectly application in other related technical fields, are likewise included within the scope of the protection of the present disclosure.