Thin film transistor array substrate and fabricating method thereof

A thin film transistor array substrate and a fabricating method thereof are disclosed. First, a substrate is provided. A patterned transparent conductive layer is then formed on the substrate. Next, a patterned first metal layer is formed to form a plurality of scan lines and a plurality of gates. Thereafter, a gate insulation layer is formed over the substrate. Moreover, a patterned semiconductor layer is formed to form a channel layer above the gates. The semiconductor layer is patterned with the same mask as that for patterning the transparent conductive layer. Additionally, a patterned second metal layer is formed to form a plurality of data lines, a plurality of sources, and a plurality of drains. After that, a dielectric layer is formed over the substrate. Finally, pixel electrodes are formed on the dielectric layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 95141894, filed Nov. 13, 2006. All disclosure of the Taiwan application is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an active device array substrate and a fabricating method thereof. More particularly, the present invention relates to a thin film transistor (TFT) array substrate and a fabricating method thereof.

2. Description of Related Art

Currently, the multimedia technology has become very developed due to the advancement of semiconductor devices or display apparatuses. As to displays, liquid crystal display (LCD) having such characteristics as high image quality, high space efficiency, low power consumption, and no radiation has become the mainstream in the display market.

An LCD panel includes a thin film transistor (TFT) array substrate, a color filter substrate, and a liquid crystal layer between the two. Generally speaking, the TFT array substrate has a plurality of pixel structures arranged as an array, and the pixel structures of a conventional TFT array substrate have to go through at least 5 mask processes to be completed. The first mask process is to define gates, scan lines, and common lines, the second mask process is to define a channel layer, the third mask process is to define sources, drains, and data lines, the fourth mask process is to define a passivation layer, and the fifth mask process is to define pixel electrodes.

Moreover, each of the pixel electrodes covers one of the common lines to form a storage capacitor. Generally speaking, the higher the aperture ratio of the pixel structures is, the higher the luminous efficiency of the entire LCD is. The common lines may affect the aperture ratio of the pixel structures since they are located below the pixel electrode. To resolve this problem, transmissive conductive material such as indium tin oxide (ITO) may be adopted as the material of the common lines to improve the aperture ratio of the pixel structures. However, an additional mask process for defining the common lines is required when fabricating the common lines with conductive material, thus, the manufacturing cost is increased, and since the resistance of the conductive material is higher than that of conventionally used metal material, power consumption and accordingly signal distortion may be caused.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to provide a method of fabricating a thin film transistor (TFT) array substrate, wherein transmissive common lines are fabricated with less mask processes to simplify the fabricating process and further to reduce fabricating cost.

The present invention is also directed to a TFT array substrate of low fabricating cost, and the TFT array substrate has improved pixel aperture ratio.

The present invention is further directed to a TFT array substrate having high pixel aperture ratio, wherein the common lines of the TFT array substrate have both transmissive and very good conductive characteristics such that signal distortion is reduced.

As embodied and broadly described herein, the present invention provides a method of fabricating a TFT array substrate. The fabricating method includes following steps. First, a substrate is provided. A plurality of patterned first transparent conductive patterns and a plurality of patterned second transparent conductive patterns are then formed on the substrate. Next, a patterned first metal layer is formed to form a plurality of scan lines, wherein each scan line extends a gate on the corresponding first transparent conductive pattern and to form a connecting metal pattern between each two adjacent second transparent conductive patterns for connecting the two adjacent second transparent conductive patterns, so as to form a plurality of common lines parallel to the scan lines. Thereafter, a gate insulation layer is formed over the substrate. Besides, a patterned semiconductor layer is formed on the gate insulation layer to form a channel layer above each gate and a semiconductor pattern above each second transparent conductive pattern, wherein the semiconductor layer is patterned with the same mask as that for forming the first transparent conductive patterns and the second transparent conductive patterns. Moreover, a patterned second metal layer is formed to form a plurality of data lines intersecting with the scan lines and the connecting metal patterns and to form source and drain respectively at two sides of each channel layer, wherein each source is connected to the corresponding data line. After that, a patterned dielectric layer is formed over the substrate to cover the channel layers, the semiconductor patterns, and the data lines, the sources and drains, wherein the dielectric layer has a plurality of contact window openings for respectively exposing the drains. Next, a plurality of pixel electrodes are formed on the dielectric layer, and each pixel electrode is electrically connected to the corresponding drain via the corresponding contact window opening.

According to an embodiment of the present invention, the transparent conductive patterns may be fabricated with the same material as the material of the pixel electrodes.

According to an embodiment of the present invention, an ion doping process is further performed after or while forming the semiconductor layer so as to form an ohmic contact layer on the surface of the semiconductor layer.

According to an embodiment of the present invention, the step of forming the dielectric layer comprises sequentially forming a passivation layer and a planarization layer.

The present invention further provides a method of fabricating a TFT array substrate. The fabricating method includes following steps. First, a substrate is provided. A patterned transparent conductive layer is then formed on the substrate to form a plurality of transparent conductive patterns and a plurality of common lines. Next, a patterned first metal layer is formed to form a plurality of scan lines, wherein each scan line extends a gate on the corresponding transparent conductive pattern. Besides, a gate insulation layer is formed over the substrate. After that, a patterned semiconductor layer is formed on the gate insulation layer to form a channel layer above each gate and a semiconductor pattern above each common line, wherein the semiconductor layer may be patterned with the same mask as that for patterning the transparent conductive layer, for example. Moreover, a patterned second metal layer is formed to form a plurality of data lines intersecting with the scan lines and to form source and drain respectively at two sides of each channel layer, wherein each source is connected to the corresponding data line. Thereafter, a patterned dielectric layer is formed over the substrate to cover the channel layers, the semiconductor patterns, and the data lines, the sources and drains, wherein the dielectric layer has a plurality of contact window openings for respectively exposing the drains and separating two ends of the semiconductor pattern so as to form a floating semiconductor pattern. Next, a plurality of pixel electrodes is formed on the dielectric layer, wherein each pixel electrode is electrically connected to the corresponding drain via the corresponding contact window opening.

According to an embodiment of the present invention, the transparent conductive layer may be fabricated with the same material as that of the pixel electrodes.

According to an embodiment of the present invention, an ion doping process is further performed after or while forming the semiconductor layer, so as to form an ohmic contact layer on the surface of the semiconductor layer.

According to an embodiment of the present invention, the step of forming the dielectric layer includes sequentially forming a passivation layer and a planarization layer.

The present invention provides a TFT array substrate including a substrate, a plurality of scan lines, a plurality of data lines, a plurality of first transparent conductive patterns, a plurality of gates, a plurality of second transparent conductive patterns, a plurality of connecting metal patterns, a gate insulation layer, a plurality of channel layers, a plurality of semiconductor patterns, a plurality of sources and drains, a dielectric layer, and a plurality of pixel electrodes. The scan lines are disposed on the substrate. The first transparent conductive patterns are disposed on the substrate and are adjacent to their corresponding scan lines. The gates are disposed on the first transparent conductive patterns and are electrically connected to the corresponding scan lines. The second transparent conductive patterns are disposed on the substrate and are arranged in parallel to their corresponding scan lines. At least one of the connecting metal patterns is respectively disposed between two adjacent second transparent conductive patterns for connecting the two adjacent second transparent conductive patterns, so as to form a plurality of common lines parallel to the scan lines. The gate insulation layer covers the scan lines, the first transparent conductive patterns, the gates, the second transparent conductive patterns, and the connecting metal patterns. The channel layers are disposed on the gate insulation layer above the gates and are corresponding to the first transparent conductive patterns. The semiconductor patterns are corresponding to the second transparent conductive patterns and are disposed on the gate insulation layer above the second transparent conductive patterns. The sources and drains are respectively disposed at two sides of the channel layers. The data lines are disposed on the gate insulation layer and are electrically connected to the sources, and the data lines intersect with but are not electrically connected to the scan lines and the connecting metal patterns. The patterned dielectric layer is disposed over the channel layers, the semiconductor patterns, the data lines, the sources and drains, and the dielectric layer has a plurality of contact window openings for respectively exposing the drains. The pixel electrodes are disposed on the dielectric layer and each pixel electrode is electrically connected to the corresponding drain via the corresponding contact window opening.

According to an embodiment of the present invention, the material of the first transparent conductive patterns comprises indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or combinations thereof.

According to an embodiment of the present invention, the material of the channel layers and the semiconductor patterns comprises amorphous silicon.

According to an embodiment of the present invention, the material of the second transparent conductive patterns comprises ITO, IZO, AZO or combinations thereof.

According to an embodiment of the present invention, the TFT array substrate further comprises an ohmic contact layer disposed between each channel layer and the corresponding source and drain.

According to an embodiment of the present invention, the dielectric layer comprises a passivation layer and a planarization layer disposed on the passivation layer.

The present invention further provides a TFT array substrate including a substrate, a plurality of scan lines, a plurality of data lines, a plurality of transparent conductive patterns, a plurality of gates, a plurality of semiconductor patterns, a gate insulation layer, a plurality of channel layers, a plurality of common lines, a plurality of sources and drains, a patterned dielectric layer, and a plurality of pixel electrodes. The scan lines and the data lines are disposed on the substrate. The transparent conductive patterns are disposed on the substrate and are adjacent to their corresponding scan lines. The gates are disposed on the transparent conductive patterns and are connected to the corresponding scan lines. The common lines are disposed on the substrate and are parallel to the scan lines. The gate insulation layer covers the scan lines, the transparent conductive patterns, the common lines, and the gates. The data lines are disposed on the gate insulation layer and are electrically connected to the sources, and the data lines intersect with but are not electrically connected to the scan lines and the common lines. The channel layers are corresponding to the transparent conductive patterns and are disposed on the gate insulation layer above the gates. The semiconductor patterns are corresponding to the common lines and are disposed on the gate insulation layer above the common lines. The sources and drains are respectively disposed at two sides of the channel layers. The patterned dielectric layer is disposed over the channel layers, the semiconductor patterns, the data lines, the sources and drains, and the dielectric layer has a plurality of contact window openings for respectively exposing the drains. The pixel electrodes are disposed on the dielectric layer and each pixel electrode is electrically connected to the corresponding drain via the corresponding contact window opening.

According to an embodiment of the present invention, the transparent conductive patterns and the common lines are made of the same film.

According to an embodiment of the present invention, the material of the semiconductor layer includes amorphous silicon.

According to an embodiment of the present invention, the material of the transparent conductive patterns and the common lines includes indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO) or combinations thereof.

According to an embodiment of the present invention, the TFT array substrate further includes an ohmic contact layer disposed between each channel layer and the corresponding source and drain.

According to an embodiment of the present invention, the dielectric layer includes a passivation layer and a planarization layer disposed on the passivation layer.

According to the fabricating method of a TFT array substrate in an embodiment of the present invention, at least a part of each common line is fabricated with transparent conductive material to improve pixel aperture ratio, and the transparent conductive patterns for forming the common lines may be defined with the same mask as that for defining the semiconductor layer to reduce the required mask processes and further to reduce the fabricating cost. Moreover, in the present invention, the common lines on the TFT array substrate may also be formed by connecting the metal patterns and the transparent conductive patterns so that the common lines may have lower resistance, accordingly the power consumption of the TFT array substrate may be reduced and signal distortion may be avoided.

The present invention further provides a liquid crystal panel comprising the TFT array substrate according to the embodiments of the present invention, an opposite substrate and a liquid crystal layer disposed therebetween is provided. The opposite substrate may be a color filter or a substrate including another common electrode.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

DESCRIPTION OF EMBODIMENTS

First Embodiment

FIGS. 1A˜1Hare cross-sectional views illustrating the fabricating flow of a thin film transistor (TFT) array substrate according to a first embodiment of the present invention, andFIGS. 2A˜2Eare top views illustrating the fabricating flow of the TFT array substrate according to the first embodiment of the present invention. Referring toFIG. 1AandFIG. 2A, first, a substrate110is provided, and the substrate110has a plurality of pixel preset regions P arranged as an array (only two pixel preset regions P are illustrated demonstratively inFIG. 2A), and each pixel preset region P has an active device region A and a capacitor region C. A patterned transparent conductive layer112is then formed on the substrate110to form a first transparent conductive pattern112ain each active device region A and a second transparent conductive pattern112bin each capacitor region C.

To be specific, the transparent conductive layer112may be formed by depositing a transparent conductive material on the substrate110through chemical vapor deposition (CVD). A mask process is then performed to the deposited transparent conductive material to form the first transparent conductive pattern112aand the second transparent conductive pattern112b. The material of the transparent conductive layer112may be indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO) or combinations thereof.

After that, referring toFIG. 1BandFIG. 2B, a patterned first metal layer is formed within the pixel preset regions P of the substrate110to form a plurality of scan lines114a, wherein the scan line114ain each pixel preset region P extends a gate114bon the corresponding first transparent conductive pattern112a, and to form a connecting pattern for connecting two adjacent second transparent conductive patterns112b, for example to form a connecting metal pattern114cbetween two adjacent second transparent conductive patterns112b. To be specific, the first metal layer may be formed by depositing one or more metal materials over the substrate110through physics vapor deposition (PVD), and a mask process is then performed to pattern the metal material, so as to form the scan lines114a, the gates114b, and the connecting metal patterns114c, simultaneously. The foregoing metal material may be a low resistance material such as aluminum, gold, copper, molybdenum, chromium, titanium, aluminum alloy, aluminum magnesium alloy, molybdenum alloy or combinations thereof.

It should be specified here that the connecting metal patterns114cmay connect the second transparent conductive patterns112bin two adjacent pixel preset regions P, so as to form a plurality of common lines CL parallel to the scan lines114a. It should be noted here that since some of the common lines CL in the present invention are fabricated with transparent conductive material, the aperture ratio of the pixel preset regions P is improved. Moreover, since the resistance of the connecting metal patterns114cfor connecting the second transparent conductive patterns112bis lower than that of ITO, thus, the common lines CL fabricated with metal material in the present invention have both lower resistance and better conductivity. Next, a gate insulation layer116is formed over the substrate110. The material of the gate insulation layer116may be SiN or SiO formed with TEOS (tetraethoxysilane) as a reactive gas source.

Next, referring toFIG. 1CandFIG. 2C, a patterned semiconductor layer118is formed on the gate insulation layer116to form a channel layer118aabove each gate114band a semiconductor pattern118babove each second transparent conductive pattern112b. Generally speaking, the semiconductor layer118may be formed by depositing amorphous silicon over the substrate110through CVD. A mask process is then performed to pattern the amorphous silicon deposited on the gate insulation layer116, so as to form the channel layers118aand the semiconductor patterns118b.

To reduce the contact resistance between the channel layers118aand the metal material, actually an ion doping process may be further performed to form an ohmic contact layer119aand a doped semiconductor layer119bon the surface of the semiconductor layer118after or while forming the semiconductor layer118. It should be noted here that the semiconductor layer118is patterned with the same mask as that for patterning the transparent conductive layer112which includes the first transparent conductive patterns112aand the second transparent conductive patterns112b.

In the present invention, the common lines CL are composed of the second transparent conductive patterns112band the connecting metal patterns114c, wherein the second transparent conductive patterns112bare patterned with the same mask as that for patterning the semiconductor layer118, and the connecting metal patterns114c, the scan lines114a, and the gates114bare formed through the same mask process. Thus, compared to conventional technique, an additional mask for defining the common lines CL is not required in the present invention, accordingly, the fabricating cost is reduced.

Next, referring toFIG. 1D, a metal material121is formed over the substrate110to cover parts of the gate insulation layer116, the ohmic contact layer119a, and the doped semiconductor layer119b. After that, referring toFIG. 1EandFIG. 2D, portion of the metal material121is removed and the metal material121is patterned to form a patterned second metal layer120and further to form a plurality of data lines120aintersecting with the scan lines114aand a source120S and a drain120D at two sides of each channel layer118a. Furthermore, the doped semiconductor layer119babove the second transparent conductive patterns112bis also removed while the portion of the metal material121is removed. Each source120S is connected to the corresponding data line120a. The data lines120aintersect with the common lines CL where the connecting metal patterns114care located.

In another embodiment of the present invention, the aforementioned step ofFIG. 1Dmay be replaced by a backward exposure process to form the structure as shown inFIG. 1E. Specifically, referring toFIG. 1I, a photoresist layer R1is formed to cover the ohmic contact layer119a, the doped semiconductor layer119b, and the gate insulation layer116, wherein the photoresist layer R1may be made of a positive-type photoresist. Then, as shown inFIG. 1J, a backward exposure is conducted to the photoresist layer R1by using the gates114bas a mask. If the gates114are made of opaque metal material, regions of the photoresist layer R1above the gates114bare not exposed. Next, referring toFIG. 1K, the photoresist layer R1is developed, and the unexposed regions of the photoresist layer R1are remained. Thereafter, as shown inFIG. 1L, the remained photoresist layer R1above the gates114bis used as a mask to remove the doped semiconductor layer119babove the second transparent conductive patterns112b. The doped semiconductor layer119bmay be removed through dry etching, for example, oxygen or a CFxbased gas is used as a reactive gas source and a bias is supplied to the reactive gas source to form plasma, and an anisotropic etching is performed to the doped semiconductor layer119bwith the plasma. Then, the remained photoresist layer R1is removed. Next, referring toFIG. 1M, a metal material121is formed over the substrate110to cover parts of the gate insulation layer116, the ohmic contact layer119a, and the semiconductor pattern118b. Then, similarly, the metal material121is patterned to form a patterned second metal layer120and further to form a plurality of data lines120aintersecting with the scan lines114aand a source120S and a drain120D at two sides of each channel layer118a, as shown inFIG. 1E.

After the step ofFIG. 1E, a patterned dielectric layer130is formed over the substrate110as shown inFIG. 1F. To be specific, the step of forming the dielectric layer130may include sequentially forming a passivation layer132and a planarization layer134. The material of the passivation layer132may be silicon oxide, silicon nitride, or silicon oxynitride, and the material of the planarization layer134may be polyimide or organic material. Referring toFIG. 1G, contact window openings H1are then formed in the dielectric layer130for exposing the drains120D.

Next, referring toFIG. 1HandFIG. 2E, pixel electrodes140are formed on the dielectric layer130. To be specific, first, a transparent electrode material is deposited on the dielectric layer130and the transparent electrode material is filled into the contact window openings H1. The transparent electrode material may be the same material as that of the transparent conductive layer112. Next, a mask process is performed to the transparent electrode material to define a pixel electrodes140in each pixel preset region P, and the pixel electrode140is electrically connected to the corresponding drain120D via the corresponding contact window opening H1. The common lines CL, which includes the second transparent conductive patterns112band the connecting metal patterns114c, and the pixel electrodes140over the common lines CL form storage capacitors. As described above, the TFT array substrate100in the present invention has been completed. The common lines CL of the TFT array substrate100have low resistance; accordingly, the TFT array substrate100in the present invention has low power consumption.

The TFT array substrate100fabricated with foregoing method is illustrated inFIG. 1HandFIG. 2E, which includes a substrate110, scan lines114a, data lines120a, first transparent conductive patterns112a, second transparent conductive patterns112b, connecting metal patterns114c, gates114b, sources120S, drains120D, a gate insulation layer116, channel layers118a, semiconductor patterns118b, a dielectric layer130, and pixel electrodes140. The scan lines114aand the data lines120aare disposed on the substrate110to form a plurality of pixel preset regions P on the substrate110, and each pixel preset region P contains an active device region A and a capacitor region C.

The first transparent conductive patterns112aare disposed in the corresponding active device regions A. The gates114bare disposed on the first transparent conductive patterns112a, and are electrically connected to the corresponding scan lines114a. The second transparent conductive patterns112bare disposed in the corresponding capacitor regions C. At least one of the connecting metal patterns114cis respectively disposed between two adjacent second transparent conductive patterns112b. The connecting metal patterns114cmay connect the second transparent conductive patterns112bin adjacent pixel preset regions P to form the common lines CL which are parallel to the scan lines114a.

The gate insulation layer116covers the scan lines114a, the first transparent conductive patterns112a, the second transparent conductive patterns112b, the gates114b, and the connecting metal patterns114c. The channel layers118aare corresponding to the first transparent conductive patterns112aand are disposed on the gate insulation layer116above the gates114b. The semiconductor patterns118bare corresponding to the second transparent conductive patterns112band are disposed on the gate insulation layer116above the second transparent conductive patterns112b. AS shown inFIG. 1H, the sources120S and the drains120D are respectively disposed at two sides of the channel layers118a. The dielectric layer130may include a passivation layer132and a planarization layer134disposed on the passivation layer132. The dielectric layer130covers the channel layers118a, the semiconductor patterns118b, the ohmic contact layer119a, the data lines120a, the sources120S, and the drains120D. The pixel electrode140are formed on the dielectric layer130and electrically connected to the corresponding drain120D via the corresponding contact window opening H1to complete a TFT. Furthermore, the pixel electrodes140and the corresponding common lines CL form storage capacitors.

Second Embodiment

FIGS. 3A˜3Hare cross-sectional views illustrating the fabricating flow of a TFT array substrate according to a second embodiment of the present invention, andFIGS. 4A˜4Fare top views illustrating the fabricating flow of the TFT array substrate according to the second embodiment of the present invention. Referring toFIG. 3AandFIG. 4A, a substrate110is first provided and the substrate110has a plurality of pixel preset regions P arranged as an array (only two pixel preset regions P are illustrated demonstratively inFIG. 4A). Each of the pixel preset regions P has an active device region A and a capacitor region C. A patterned transparent conductive layer112is then formed on the substrate110to form a first transparent conductive pattern112ain each active device region A and a second transparent conductive pattern112bin each capacitor region C. It should be noted here that the second transparent conductive patterns112bin adjacent pixel preset regions P are connected to each other to form the common lines CL on the substrate110. In other words, in two or more adjacent preset regions P, the second transparent conductive patterns112bare disposed continuously and formed into one piece or one single layer on the substrate110.

To be specific, the transparent conductive layer112may be formed by depositing transparent conductive material on the substrate110through CVD. A mask process is then performed to the deposited transparent conductive material to form the first transparent conductive patterns112aand the second transparent conductive patterns112bthereby the common lines CL are formed. The material of the transparent conductive layer112may be ITO, IZO, AZO or combinations thereof.

Referring toFIG. 3BandFIG. 4B, a patterned first metal layer114is formed over the substrate110to form a plurality of scan lines114aand gates114b. The scan line114ain each pixel preset region P extends the gate114bon the corresponding first transparent conductive pattern112a. To be specific, the first metal layer114may be formed by depositing one or more metal materials over the substrate110through PVD, and a mask process is then performed to pattern the metal material for example, so as to form the scan lines114aand the gates114b. Next, a gate insulation layer116is formed over the substrate110. The material of the gate insulation layer116may be SiN or SiO formed with TEOS as a reactive gas source.

Thereafter, referring toFIG. 3CandFIG. 4C, a patterned semiconductor layer118is formed on the gate insulation layer116to form a channel layer118aabove each gate114band a semiconductor pattern118babove each second transparent conductive pattern112b. Generally speaking, the semiconductor layer118may be formed by depositing amorphous silicon over the substrate110through CVD. A mask process is then performed to pattern the amorphous silicon deposited on the gate insulation layer116, so as to form the channel layers118aand the semiconductor patterns118b.

To reduce the contact resistance between the channel layers118aand the metal material which may be formed for a source or a drain of a TFT, actually an ion doping process may be further performed to form an ohmic contact layer119aand a doped semiconductor layer119bon the surface of the semiconductor layer118after or while forming the semiconductor layer118. It should be emphasized here that the semiconductor layer118may be patterned with the same mask as that for patterning the transparent conductive layer112including the first transparent conductive patterns112aand the second transparent conductive patterns112b. Thus, compared to conventional technique, an additional mask for defining the common lines CL is not required in the present invention so that the fabricating cost is reduced. Moreover, since the common lines CL in the present invention are fabricated with transparent conductive material, the aperture ratio of the pixel preset regions P is improved.

After that, referring toFIG. 3D, a metal material121is formed over the substrate110to cover parts of the gate insulation layer116, the doped semiconductor layer119b, and the ohmic contact layer119a. Next, referring toFIG. 3EandFIG. 4D, the metal material121is patterned to form a patterned second metal layer120and further to form a plurality of data lines120awhich intersect with the scan lines114aand a source120S and a drain120D respectively disposed at two sides of each channel layer118a. Furthermore, the doped semiconductor layer119babove the second transparent conductive patterns112bmay be also removed while the portion of the metal material121is removed. Each source120S is connected to the corresponding data line120a.

In another embodiment of the present invention, the aforementioned step ofFIG. 3Dmay be replaced by a backward exposure process to form the structure as shown inFIG. 3E. Specifically, referring toFIG. 3I, a photoresist layer R2is formed to cover the ohmic contact layer119a, the doped semiconductor layer119b, and the gate insulation layer116, wherein the photoresist layer R2may be made of a positive-type photoresist. Then, as shown inFIG. 3J, a backward exposure is conducted to the photoresist layer R2by using the gates114bas a mask. If the gates114are made of opaque metal material, regions of the photoresist layer R2above the gates114bare not exposed. Next, referring toFIG. 3K, a portion of the photoresist layer R2is developed, and the unexposed regions of the photoresist layer R2are remained. Thereafter, the remained photoresist layer R2above the gates114bis used as a mask to remove the doped semiconductor layer119babove the second transparent conductive patterns112bto expose the semiconductor pattern118b. The doped semiconductor layer119bmay be removed through dry etching, for example, oxygen or a CFx, based gas is used as a reactive gas source and a bias is supplied to the reactive gas source to form plasma, and an anisotropic etching is performed to the doped semiconductor layer119bwith the plasma. Then, the remained photoresist layer R2is removed, as shown inFIG. 3L. Next, referring toFIG. 3M, a metal material121is formed over the substrate110to cover parts of the gate insulation layer116, the ohmic contact layer119a, and the semiconductor pattern118b. Then, similarly, the metal material121is patterned to form a patterned second metal layer120and further to form a plurality of data lines120aintersecting with the scan lines114aand a source120S and a drain120D respectively disposed at two sides of each channel layer118a, as shown inFIG. 3E.

After the step ofFIG. 3E, a dielectric layer130is formed over the substrate110as shown inFIG. 3F. To be specific, the step of forming the dielectric layer130may include sequentially forming a passivation layer132and a planarization layer134. The material of the passivation layer132may be silicon oxide, silicon nitride, or silicon oxynitride, and the material of the planarization layer134may be polyimide or organic material. Next, referring toFIG. 3GandFIG. 4E, contact window openings H2are formed in the dielectric layer130for exposing the drains120D. Moreover, slits H3and H4are formed in the dielectric layer130and through the semiconductor pattern118bfor separating two ends of each semiconductor patterns118b, so as to form a floating semiconductor pattern118c.

After that, referring toFIG. 3HandFIG. 4F, pixel electrodes140are formed on the dielectric layer130. To be specific, a transparent electrode material is first deposited on the dielectric layer130, and the transparent electrode material is filled in the contact window openings H2to electrically connect with the drain120D. The transparent electrode material may be the same material as that of the transparent conductive layer112.

Thereafter, a mask process is performed to the transparent electrode material to form a pixel electrode140in each pixel preset region P, and the pixel electrode140may be electrically connected to the corresponding drain120D via the corresponding contact window opening H2. The transparent electrode material in or over the slits H3and H4can be removed all together while patterning the transparent electrode material, so as to electrically insulate the floating semiconductor patterns118cfrom other films. The pixel electrodes140are located over the common lines CL to form storage capacitors along with the corresponding common lines CL. As described above, the TFT array substrate200in the present invention has been completed.

As for forming the floating semiconductor patterns118c, for another example, slits may be formed before the dielectric layer130is formed thereon. More specifically, after forming the semiconductor patterns118b, slits may be formed in the semiconductor patterns118b, thereby the floating semiconductor patterns118ccan be formed. Then, the dielectric layer130is entirely formed thereon.

The TFT array substrate200fabricated with foregoing method is illustrated inFIG. 3HandFIG. 4E, which includes a substrate110, scan lines114a, data lines120a, first transparent conductive patterns112a, second transparent conductive patterns112b, gates114b, sources120S, drains120D, a gate insulation layer116, channel layers118a, semiconductor patterns118b, a dielectric layer130, and pixel electrodes140. The scan lines114aand the data lines120aare disposed on the substrate110to define a plurality of pixel preset regions P on the substrate110, and each of the pixel preset regions P has an active device region A and a capacitor region C.

Moreover, the first transparent conductive patterns112aare disposed within the corresponding active device regions A. The gates114bare disposed on the first transparent conductive patterns112aand are electrically connected to the corresponding scan lines114a. The second transparent conductive patterns112bare disposed within the corresponding capacitor regions C, and the second transparent conductive patterns112bin adjacent pixel preset regions P are connected to each other to form the common lines CL which are parallel to the scan lines114a.

In the present invention, the gate insulation layer116covers the scan lines114a, the first transparent conductive patterns112a, the second transparent conductive patterns112b, and the gates114b. The channel layers118aare corresponding to the first transparent conductive patterns112aand are disposed on the gate insulation layer116above the gates114b. The semiconductor patterns118bare corresponding to the second transparent conductive patterns112band are disposed on the gate insulation layer116above the second transparent conductive patterns112b. As shown inFIG. 3H, the sources120S and the drains120D are respectively disposed at two sides of the channel layers118a. The dielectric layer130may include a passivation layer132and a planarization layer134disposed on the passivation layer132. The dielectric layer130may cover the channel layers118a, the ohmic contact layer119a, the semiconductor patterns118b, the data lines120a, the sources120S, and the drains120D. The pixel electrodes140are formed on the dielectric layer130and electrically connected to the corresponding drain120D via the corresponding contact window opening H2to complete a TFT. Furthermore, the pixel electrodes140and the corresponding common lines CL form storage capacitors.

In summary, according to the fabricating method of a TFT array substrate in the present invention, the semiconductor layer is patterned with the same mask as that for patterning the transparent conductive layer, thus, no additional mask is required for forming the common lines. Compared with conventional technique, the fabricating method of a TFT array substrate in the present invention can reduce the fabricating cost effectively. Moreover, since at least some of the common lines are fabricated with transparent conductive material, the pixel aperture ratio can be improved, and since the common lines of the TFT array substrate may also be formed by connecting a metal material and a transparent conductive material, the common lines have low resistance and so that the TFT array substrate has low power consumption and signal distortion can be avoided. A liquid crystal panel can use the TFT array substrate according to the embodiments of the present invention. The liquid crystal panel comprising the TFT array substrate according to the embodiments of the present invention, an opposite substrate and a liquid crystal layer disposed therebetween is provided. The opposite substrate may be a color filter or a substrate including another common electrode.