Solid state devices having fine pitch structures

In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.

TECHNICAL FIELD

Embodiments of the present invention relate to the manufacture and processing of semiconductor wafers, and more particularly to methods for forming devices having very fine pitch features.

BACKGROUND

Today's electronic devices contain sophisticated circuits, many of which have been made possible by fabricating highly dense arrays of conductors and components. These conductors and components are typically fabricated by using photolithographic techniques. As the demand for more complex circuits (and higher capacity in memory devices made from these complex circuits) increases, however, the need to form even finer features rises. In the case of memory devices, higher-capacity storage requires finer conductors and spacing.

The limits to photolithographic techniques are related to the desired feature size and the wavelength of the light used to project an image on the semiconductor substrate. This projection is performed using reticules that can be very costly to produce. For this reason, it is desirable to limit the number of reticules required. As the extreme limits of the photolithographic process are approached, however, the spreading of the edges of the projected images can cause artifacts where these edges overlap and form undesired projected images due to the additive nature of the process. One way to avoid this effect is to maintain a greater spacing between desired features so as to avoid the edge overlapping. This greater spacing prevents the tight packing of lines desired for high density memory arrays, however.

A technique to retain the tight packing of lines while avoiding this additive edge effect is double-patterning, a technique in which one mask is used to project the image of only a subset of desired features (e.g., even-numbered array lines), thereby leaving wider spacing between those even lines so as to avoid the additive edge effect. A second mask is then used to project the remaining features (e.g., odd-numbered array lines, centered in the spaces between the even-numbered lines) and thus create the desired high density packing. The downside to this technique is the increase in the number of required masks.

In the case of diode-array memories in particular, the need for smaller diode formation to fit within the pattern of finer conductors and spacing introduces additional problems. For example, the vertically formed diode at each memory cell location is sometimes created by overlapping a row and column line thereby forming a square (or nearly square) feature which is the footprint of the vertical diode. However, in those methods in which the square feature is a hole in which a diode is grown, the corners can cause the formation of stacking faults while silicon is epitaxially grown in the holes. Also, these corners can be a source of current leakage in the formed diodes during operation. In addition, the information-storage element formed using the diode of a diode-array memory must have a consistent dimension across all instances of the element across die in order to prevent variations in the operating parameters that would render both the programming voltages and currents as well as the read threshold between a one bit and a zero bit difficult to calibrate. A need therefore exists for a way to create high-density arrays of elements using a minimum number of masks.

SUMMARY

Embodiments of the present invention include creation of tightly packed features required for (e.g.) high-density diode array memories (or any other similar structures) without the need for high-density photolithographic masks or double-patterning, and also the creation of diodes without corners from the overlap of a tightly packed row feature with a tightly packed column feature. In one embodiment, a plurality of rows of hardmask material are created using a photolithographic step; the rows are spaced out to correspond to only every other bit or wordline in an array. The remaining rows (placed in-between the photolithographic rows) are formed via deposition of the hardmask material after, in one embodiment, deposition of another material to create sidewall “cushion” spaces adjacent to the photolithographic rows. In another embodiment, a plurality of rows of insulating material are created in a photolithographic step, again corresponding to only every other bit or wordline in an array. A layer of hardmask material is then deposited on the rows of insulating material such that sidewalls of hardmask material are grown laterally from the rows of insulating material.

In one aspect, a method for forming an array includes forming a plurality of rows of hardmask material above one or more layers of insulating material, forming a plurality of columns of hardmask material above the plurality of rows of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes.

A first subset of the plurality of rows may be formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step. The first subset of the plurality of rows may be separated by a distance corresponding to double a distance between array bitlines, and wherein the second subset of the plurality of rows are deposited between the first subset of the plurality of rows. The deposition step may include forming sidewall hardmask features on the sides the first subset of the plurality of rows and depositing the second subset of the plurality of rows, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step. Forming the plurality of rows of hardmask material may include forming a plurality of rows of insulating material and depositing a layer of hardmask material on top of the plurality of rows of insulating material. A first subset of the plurality of columns may be formed by a lithographic step and wherein a second subset of the plurality of columns are thereafter formed by a deposition step. The deposition step may include forming sidewall hardmask features on the sides the first subset of the plurality of columns and depositing the second subset of the plurality of columns; wherein a thickness of sidewall material in the sidewall hardmask features may be defined by the deposition step. Etching the holes may include performing a selective etch of the insulating material, wherein the insulating material may include at least two different types of insulating materials, and wherein selectively etched hole may include a first diameter etched in a first type of insulating material and a second diameter larger than the first diameter etched in a second type of insulating material. An electronic circuit in electrical communication with the array may be formed.

In another aspect, An electronic circuit in the form of an array includes features that have been formed by forming a plurality of rows of hardmask material above one or more layers of insulating material, forming a plurality of columns of hardmask material above the plurality of rows of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes.

A first subset of the plurality of rows may be formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step. The deposition step may include forming sidewall hardmask features on the sides the first subset of the plurality of rows and depositing the second subset of the plurality of rows, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step. A first subset of the plurality of columns may be formed by a lithographic step and wherein a second subset of the plurality of columns are thereafter formed by a deposition step. The deposition step may include forming sidewall hardmask features on the sides the first subset of the plurality of columns and depositing the second subset of the plurality of columns, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step.

In another aspect, an electronic system includes one or more array circuits; the array circuits include features that have been formed by forming a plurality of rows of hardmask material above one or more layers of insulating material, forming a plurality of columns of hardmask material above the plurality of rows of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes.

A first subset of the plurality of rows may be formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step. The deposition step may include forming sidewall hardmask features on the sides the first subset of the plurality of rows and depositing the second subset of the plurality of rows, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step. A first subset of the plurality of columns may be formed by a lithographic step and wherein a second subset of the plurality of columns are thereafter formed by a deposition step. The deposition step may include forming sidewall hardmask features on the sides the first subset of the plurality of columns and depositing the second subset of the plurality of columns, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step. The holes in which memory cells are formed may have corners and these corners may be rounded.

These and other objects, along with advantages and features of the present invention herein disclosed, will become more apparent through reference to the following description, the accompanying drawings, and the claims. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.

DETAILED DESCRIPTION

Embodiments of the present invention include a means and method to form very fine features in a semiconductor process as would be required for high-density electronic memory devices and to do so consistently. Consistency is especially important for resistive memory cells because variation in the processing of the individual memory cells can lead to variation across the wafer and even across a single die that can result in difficulty in calibrating the sense amp level of the output stage of the die. This is because a slight difference in the size of the resistive change memory element can result in a significant resistance difference when reading. If this difference is too great from one area on a given die to another, it can be difficult to set a threshold level which determines the cross over point between a one bit and a zero bit. Likewise, if the difference is too great from one area on a given die to another, it can be difficult to set a programming voltage and/or current level that will reliably set or reset the information storage element at a given bit location.

Photolithographic techniques will print features, but these features will have variation at their edges. This is typical of photolithography. This not much of a problem when the features are large relative to the range at the edges where this variation occurs, but as the features become very small, the variation of the edges becomes a much larger portion of the overall feature. Even when features are printed using double-exposure techniques, this variation from each exposure of the double exposure pair will combine to create even greater variance. To pattern a hole for forming a memory cell consisting of a vertical diode and phase-change memory element, photolithographic techniques are used to double-pattern a square feature by first patterning a stripe in one direction and then patterning a stripe in an orthogonal direction; where the two stripes overlap, a square is patterned. (Because of the variation at the edges and the additive nature of the two exposures, the corners are least exposed whereas the center is most exposed and, as a result, a more circular feature will be created. This circular pattern is desirable when fabricating a memory cell consisting of a vertical diode and phase-change memory element, particularly because sharper corners in the hole for which the diode is to be formed can result in more stacking faults when depositing the semiconducting material to form the diode—e.g., as will be the case when forming a silicon diode with an epitaxial deposition technique. However, when the memory cell elements are formed by patterning and forming a line in one direction to overlap a line patterned and formed in an orthogonal direction, the corners will be much sharper.) The present invention includes a means and method to pattern less critical aspects of a pattern of features (such as the spaces between critically patterned lines) in a way that minimizes variation of the more critical features such as conductive lines and memory cell elements.

In one embodiment of the present invention, precision deposition techniques are used to form an etch mask by sidewall deposition. Referring toFIG. 1, a portion of a partly processed silicon wafer10is depicted showing part of a series of bitlines11that have been formed and that are separated by spaces12made of reverse doped silicon, shallow trench dielectric isolation (STI), or the like as is well understood by those skilled in the art.FIG. 2shows this portion of the wafer after depositing a series of electrically insulating layers such as silicon oxide21, silicon nitride22, and silicon oxide23; any number, type, or order of insulating layers are is within the scope of the present invention, however, and the present invention is not limited to only the depicted layers. A layer of polysilicon24is deposited on the insulating layers21,22,23; this polysilicon layer24is later used as a hardmask, as explained in greater detail below. As depicted inFIG. 3, the polysilicon24is patterned and etched into rows31; these rows31are generally positioned above every other space12between the bitlines11. By forming these polysilicon rows31above every other space12(each row31having generally the same width as the underlying space12), the spaces32between the polysilicon rows31may be roughly three times as wide as the polysilicon rows31themselves and, as a result, the photolithographic difficulty to pattern these polysilicon rows31is reduced and double patterning to form these rows may be avoided.

InFIG. 4, a deposited layer of conformal silicon oxide41is deposited on top of the polysilicon31and silicon oxide23. The conformal silicon oxide layer41may be deposited with a precision deposition process such as atomic layer deposition (ALD) having a thickness equal to the desired feature size (in this case, a measure across the holes to be formed to fabricate the memory cells). This deposited layer of conformal silicon oxide41may be etched back (as depicted inFIG. 5) using (for example) a side-wall spacer etch-back technique as is well understood by those skilled in the art. A layer of polysilicon is next deposited across the wafer to fill in the spaces52between deposited sidewalls51.

As shown inFIG. 6, the wafer is planarized (e.g., as by chemical-mechanical polishing or CMP) to form rows61of hardmask material above the spaces12between the bitlines11. Note that there is now a polysilicon row61above every space12between the bitlines11; every other of these polysilicon rows61was formed by patterning the initial layer of polysilicon24and the remaining rows were formed by depositing polysilicon across the wafer to fill in the spaces52between deposited sidewalls51.

InFIG. 7, a layer of polysilicon71is deposited in preparation of generally repeating the steps depicted inFIGS. 3 through 6for an orthogonal hardmask pattern.

As depicted inFIG. 8, this polysilicon71is patterned and etched into columns81; these columns are generally positioned where every other space between the memory cells is to be formed. Each column81may have generally the same width as the desired memory cell space. The spaces82between the polysilicon columns81may be roughly three times as wide as the polysilicon columns81themselves and, as a result, the photolithographic difficulty to pattern these polysilicon columns81is reduced and double patterning to form these columns may be avoided.

InFIG. 9, a deposited layer of conformal silicon oxide91is deposited. This layer may be deposited with a precision deposition process such as atomic-layer deposition (ALD) having a thickness equal to the desired feature size (in this case, the orthogonal measure across the holes to be formed to fabricate the memory cells as was depicted inFIG. 4). This deposited layer of conformal silicon oxide91is etched back (as depicted inFIG. 10) using a side-wall spacer etch-back technique as is well understood by those skilled in the art. A layer of polysilicon may be next deposited across the wafer to fill in the spaces102between deposited sidewalls101.

As shown inFIG. 11, the wafer is planarized (e.g., as by chemical-mechanical polishing or CMP) to form columns111of hardmask material to protect the spaces between the memory cells. Note that there is now a polysilicon column111between every intended memory cell; every other of these polysilicon columns111was formed by patterning the deposited layer of polysilicon71and the remaining rows were formed by depositing polysilicon across the wafer to fill in the spaces102between deposited sidewalls101.

InFIG. 12, a deep dielectric etch is performed to form holes121down to the bitlines11using the remaining polysilicon hardmask material in rows61and columns111(originally deposited in layers24and71, respectively). Once the holes121are etched for the memory cell formation, the remaining hardmask polysilicon (in columns61and111) on the surface is removed by (for example) filling the holes with BARC131(as depicted inFIG. 13). BARC may etch at a rate approximately equal to that of the polysilicon hardmask material; a polysilicon/BARC etch, therefore, may remove the surface BARC and the polysilicon hardmask material remaining on the surface (and, in some embodiments, partly remove the BARC material in the holes121), as depicted inFIG. 14. As depicted inFIG. 15, any BARC remaining in the holes121may then be removed with a descum step as is well understood by those skilled in the art. A selective epitaxial silicon growth step is may be used to grow crystalline silicon161in the holes all the way to the surface as depicted inFIG. 16. This crystalline silicon161may be planarized (e.g., by CMP) as depicted inFIG. 17and then partly etched back to form cups181as depicted inFIG. 18. An implant is next performed to form the P-N junction (or P-i-N junction) of the diodes. For example, if the bitlines11are formed of N-type silicon and the epitaxial silicon of the diodes is formed of intrinsic or N-type silicon, the anodes191are created by implanting to turn the anodes (tops) of the diodes into P-type silicon as shown inFIG. 19.

InFIG. 20A, the cups181are widened by an anisotropic etch, but this etch is selective to etch oxide faster than nitride resulting in a narrow band201near the middle of the cup. That is, as also shown inFIG. 20B, a diameter D2of the cups181is greater for the portions of the cups181in which the sidewalls of said cups181are constructed with oxide, and a diameter D1is smaller for the portion of the cups181in which the sidewalls of said cups are constructed with nitride. This narrowing near the center of the cup will result in an increase in current density in the final device. To further enhance this effect, a conformal layer of silicon nitride211is deposited (e.g., by ALD as depicted inFIG. 21) and then etched back to expose the top contact221of the diode's anode (e.g., by an isotropic spacer etchback as is well known to those skilled in the art as depicted inFIG. 22). Note that this etch back removes a portion of the nitride narrowing spacer band201where a top surface of that spacer is exposed to this vertical etch. To prevent the removal of this narrowing band, the height of the initial layer22must be large enough to absorb any over-etch needed to assure that the anode contact is cleared. The cups are then filled by ALD or the like with the information storage element material231such as a chalcogenide alloy like GST as is known to those skilled in the art and as is depicted inFIG. 23. This is then planarized (e.g., by CMP) as is depicted inFIG. 24to form individual information storage elements241at each memory cell. From this point to the end of the process, standard processing (e.g., back end of line, BEOL, processing) is utilized to pattern and create top contacts and vias441and metal column lines442for the cross-point selection of individual memory cells (as depicted inFIG. 44).

The above description of an embodiment of the present invention enables the patterning and creation of memory cell elements using only two critical masks and in a way that creates the volume in which the cell is created such that the dimensions of that volume do not suffer from the variation inherent in a photolithographic patterning process. The width and length of the volume in which the memory cell is formed is determined by the thickness in conformal deposition steps (as depicted inFIGS. 4 and 9). While this sequence of steps results in a precisely dimensioned opening in which to form a memory cell, the squared off corners surrounding the volume wherein the epitaxially grown silicon for the diodes is deposited may result in stacking faults in that deposited silicon which could cause leakage currents. To address this, a slight modification to the above sequence of steps enables rounding of these corners while keeping the essence of the present invention as described above. A first such modification approach would be to add a spacer deposition and etch back sequence, as is done around the gates of small feature MOS transistors and is well known to those skilled in the art. This would involve depositing a thin conformal coating of nitride or other non-conductive or dielectric material in the hole prior to epi-silicon growth (i.e., at the point depicted byFIG. 15). Such a conformal deposition (very much like the conformal deposition depicted atFIG. 21) will not significantly reduce the size of the hole opening, but will be thickest in the corners of the hole where the material contacts two walls, resulting in a rounding of those corners. This deposition would be followed by a brief isotropic etch (very much like the conformal deposition depicted atFIG. 22) to clear the silicon surface at the bottom of the hole where the epi-silicon would be selectively grown. A second modification approach is as follows.

FIG. 25again shows this portion of the wafer at the point after that depicted inFIG. 1. In this instance, a series of layers such as silicon oxide251, silicon nitride252, silicon oxide253, polysilicon254(to be used later as a hardmask), and silicon oxide top mask material255is deposited. This top mask oxide material255is patterned and etched into rows261(these rows are generally positioned above every other space12between the bitlines11. As depicted inFIG. 26, by forming these top mask oxide material rows261above every other space12(each row261having generally the same width as the underlying space12less a “cushion thickness”, as described below), the spaces262between the top mask oxide material rows261are be more than three times as wide as the top mask oxide material rows261themselves and, as a result, the photolithographic difficulty to pattern these top mask oxide material rows261is reduced, and double patterning to form these rows may be avoided. Note that the reduction of the width of the rows by a “cushion thickness” may be achieved by slightly overexposing the photolithographic patterning of those rows. This “cushion thickness” is put back (as depicted inFIG. 27) with the deposition (e.g., by ALD) of a conformal layer of silicon oxide271equal in thickness to that “cushion thickness.” While this restores the width of the rows to that which was patterned according to the steps corresponding toFIG. 3, the benefit is that in this case, a layer of etch stop material271is formed in the bottom of the spaces262. InFIG. 28, this etch stop layer271is more easily visible under a deposited layer of conformal polysilicon281. This etch stop layer271is deposited with a precision deposition process such as atomic layer deposition (ALD) having a thickness equal to the desired feature size (in this case, a measure across the holes to be formed to fabricate the memory cells). This deposited etch stop layer of conformal polysilicon281is etched back (as depicted inFIG. 29) using a side-wall spacer etch-back technique as is well understood by those skilled in the art. A layer of silicon oxide301is next deposited across the wafer to fill in the spaces292between deposited sidewalls291, as shown inFIGS. 29 and 30.

As shown inFIG. 31, the wafer is planarized (e.g., as by chemical-mechanical polishing, CMP) to form rows311of hardmask material above the bitlines11. Note that there is now a polysilicon row311above each bitline11; these polysilicon rows311were formed by forming rows of sidewall spacers from the deposited layer of polysilicon281.

InFIG. 32, a layer of polysilicon321is deposited to form an etch stop and, inFIG. 33, a layer of silicon oxide331is deposited in preparation of generally repeating the steps depicted inFIGS. 26 through 31for an orthogonal hardmask pattern.

As depicted inFIG. 34, this silicon oxide331is patterned and etched into columns341(these columns are generally positioned where every other space between the memory cells are to be formed). As was depicted inFIG. 26and as is now depicted here inFIG. 34, by forming these top mask oxide material columns341above every other space between the memory cells (each column341having generally the same width as the underlying space between the memory cells less a “cushion thickness,” as was described above), the spaces342between the top mask oxide material columns341may be more than three times as wide as the top mask oxide material columns341themselves and, as a result, the photolithographic difficulty to pattern these top mask oxide material columns341is reduced and double patterning to form these columns may well be avoided. Note that the reduction of the width of the columns by a “cushion thickness” can be achieved by slightly overexposing the photolithographic patterning of those columns. This “cushion thickness” is put back (as depicted inFIG. 35) with the deposition (e.g., by ALD) of a conformal layer of silicon oxide351equal in thickness to that “cushion thickness.” While this restores the width of the columns to that which was patterned according to the steps corresponding toFIG. 3, the benefit is that in this case, a layer of etch stop material351is formed in the bottom of the spaces342. InFIG. 35, this etch stop layer351is more easily visible under a deposited layer of conformal polysilicon352. This etch stop layer352is deposited with a precision deposition process such as atomic-layer deposition (ALD) having a thickness equal to the desired feature size (in this case, a measure across the holes to be formed to fabricate the memory cells). This deposited etch stop layer of conformal polysilicon352is etched back (as depicted inFIG. 36) using a side-wall spacer etch-back technique as is well understood by those skilled in the art. A layer of silicon oxide is next deposited across the wafer to fill in the spaces362between deposited sidewalls361.

As shown inFIG. 37, the wafer is planarized (e.g., by chemical-mechanical polishing or CMP) to form columns371of hardmask material above the spaces between the memory cells, similar to (but orthogonal to) the rows of hardmask material depicted inFIG. 31.

FIG. 38depicts a series of directional (i.e., anisotropic) etches alternating between oxide etches and silicon etches. InFIG. 38A, an oxide etch removes surface oxide to stop on and expose the underlying hardmask layer formed of polysilicon321and311. InFIG. 38B, a silicon etch removes now-exposed hardmask material, stopping on oxide. InFIG. 38C, this oxide-stopping material is removed using another oxide etch to stop on and expose a second complex hardmask. InFIG. 38D, a short-timed silicon etch is performed, timed to just remove the surface hardmask material that connects the small cubes of surface hardmask material above each memory cell. Finally, inFIG. 38E, an oxide etch removes any remaining surface oxide.

FIG. 39depicts the wafer following a short non-directional (i.e., isotropic) etch. This brief, timed etch removes a small amount of the exposed hardmask material such that the corners of the structures (which are exposed on two sides) are removed faster and, resultantly, are rounded off. This step is followed by the deposition of a conformal layer of oxide401(as depicted inFIG. 40) which is then planarized (as depicted inFIG. 41) resulting in a square (with rounded corners)411of hardmask material above each memory cell surrounded by oxide412. This oxide412may serve as an etchmask when openings are formed through hardmask layer254(as depicted inFIG. 42); the resulting hardmask formed from layer254facilitates the formation of deep holes (through layers253,252and251) to form the memory cells.

First, as depicted inFIG. 42A, the exposed round-corner squares of hardmask material are removed using a silicon etch. Second, as depicted inFIG. 42B, a brief, timed oxide etch removes the small layer of oxide remaining below each of the exposed round-corner squares of hardmask material just removed, but without removing all of the oxide that was between the exposed round-corner squares of hardmask material just removed. Alternatively, the exposed round-corner squares of hardmask material and the small layer of oxide remaining below each of the exposed round-corner squares of hardmask material may be removed by extending the planarization step described in the step corresponding toFIG. 41. As depicted inFIG. 42C, a directional (i.e., anisotropic) silicon etch is next used to remove the hardmask material above each memory cell. Optionally, as depicted inFIG. 42D, a brief non-directional (i.e., isotropic) silicon etch may also be performed to further round the corners of the openings in the hardmask layer. Finally, as depicted inFIG. 43(as was done in the step corresponding toFIG. 12), a deep dielectric etch is performed to form holes431down to the bitlines11using the remaining polysilicon hardmask material from layer254. Once the holes431are etched for the memory cell formation, the process continues with those steps corresponding toFIGS. 13 through 24, and then, from that point to the end of the process using standard processing (e.g., back end of line or “BEOL” processing) to pattern and create top contacts and metal column lines for the cross-point selection of individual memory cells (as depicted inFIG. 44).

The present invention may be used to implement cross-point memory arrays wherein the memory arrays' surrounding circuitry is also implemented using embodiments of the present invention; these arrays may be one of many tiles or sub-arrays in a larger device or an array within a 3-D arrangement of arrays or tiles. In such a memory device, the storage cells can incorporate field-emitters, diodes or other non-linear conductor devices that conduct current better in one direction than the other for a given applied voltage. The non-linear conductive devices of the memory array, while typically include diodes, may alternatively be constructed as three-layer devices (e.g., bipolar transistors) or four-layer devices (e.g., P-N-P-N diodes or SCRs).FIG. 45, for example, is a block diagram of an array500constructed in accordance with any of the above embodiments of the present invention; a row read-write circuit502and a column read-write circuit504may be similarly constructed. The row/column circuits502,504may include sense amps, drivers, or any other such circuits known in the art. Other circuits506may also be included, such as memory/bus I/O circuits or any other circuits known in the art.

The storage element may be a fuse, an antifuse, a resistance-change material such as a phase-change material (including a chalcogenide in which the programmed resistivity can be one of two resistance values and, in the case of more than one bit per cell storage cells, in which the programmed resistivity can be one of three or more resistance values), a resistance that can be altered electrically or by heating, or a field-emitter element programming mechanism including an element for which the resistance or the volume is changeable and programmable.

Memory devices incorporating embodiments of the present invention may be applied to memory devices and systems for storing digital text, digital books, digital music (such as MP3 players and cellular telephones), digital audio, digital photographs (wherein one or more digital still images can be stored including sequences of digital images), digital video (such as personal entertainment devices), digital cartography (wherein one or more digital maps can be stored, such as GPS devices), and any other digital or digitized information as well as any combinations thereof.

Devices incorporating embodiments of the present invention may be embedded or removable, and may be interchangeable among other devices that can access the data therein. Embodiments of the invention may be packaged in any variety of industry-standard form factor, including compact flash, secure digital, multimedia cards, PCMCIA cards, memory stick, any of a large variety of integrated circuit packages including ball-grid arrays, dual in-line packages (DIPs), SOICs, PLCCs, TQFPs, and the like, as well as in proprietary form factors and custom designed packages. These packages can contain just the memory chip, multiple memory chips, one or more memory chips along with other logic devices or other storage devices such as PLD's, PLA's, micro-controllers, microprocessors, controller chips or chip-sets or other custom or standard circuitry.

Systems incorporating memory devices comprising embodiments of the present invention have the advantages of high density, non-volatile memory. Such systems could provide long term storage as a solid state storage device instead of or in addition to rotating media storage (e.g., magnetic disks, read only or read/write optical disks, and the like) and/or network based storage. Such systems could be in the form of a desk-top computer system, a hand-held device (such as a tablet computer or a laptop computer), a communication device (such as a cell phone, a smart phone, a portable wirelessly networked device for music, video or other purposes, or the like), and/or any other system based device having data storage.

The foregoing description of an example of embodiments of the present invention; variations thereon have been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description.