Stacked capacitor-type semiconductor storage device and manufacturing method thereof

First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a cell structure of dynamic RAM (i.e. DRAM), for example, more specifically, a STC (Stacked Capacitor)-type semiconductor storage device in which a memory cell capacitor is formed above a bit line so as to be self-aligned with the bit line, and relates to a manufacturing method thereof.

2. Description of the Related Art

Recently, a semiconductor storage device, particularly, a DRAM has been integrated greatly. Accordingly, a percentage of a unit storage element is showing a tendency to further increase. For this reason, a three-dimensional memory cell capacitor and a three-dimensional memory cell transistor are indispensable for obtaining enough capacity (not less than 20 fF) to read/write. As a result, a cell structure using a trench-type capacitor or STC-type capacitor is generally used.

In addition, in the cell using the STC-type capacitor, a technique for forming a memory cell capacitor so that it is self-aligned with a bit line is important to greater-scale integration. As a method of manufacturing the conventional STC-type capacitor, a memory cell is suggested as described in, for example, M. Fukumoto et al., “Stacked capacitor cell technology for 16 M DRAM using double self aligned contacts”, ESSDERC 90, pp. 461-464, 1990.FIGS. 13 through 15show its example.

FIG. 13shows a plan view of the memory cell. InFIG. 13,201is a channel region,202is a gate electrode pattern,203is a bit line contact,204is a bit line pattern,205is a storage node contact pattern, and206is a storage node electrode pattern.

FIGS. 14A through 14Cshow manufacturing steps of a cross-sectional view taken along line14—14in FIG.13. As shown inFIG. 14A, an element separating oxide film52, a MOS transistor for transmitting data, not shown, a first inter-layer insulating film53, a bit line contact, not shown, a bit line54, and a second inter-layer insulating film55made of BPSG film are formed on a semiconductor substrate51. Next, a storage node contact56which reaches the semiconductor substrate51is formed in the first and second inter-layer insulating films53and55which is located between the bit lines54—54by the known lithography method and the RIE (Reactive Ion Etching) method.

Next, as shown inFIG. 14B, an HTO (High Temperature Oxide) film57is deposited over the whole surface, and the whole surface is etch-backed by the RIE method. Then, as shown inFIG. 14C, a side wall spacer58constituted by the HTO film57is formed on the first and second inter-layer insulating films exposed in the storage node contact56.

If the storage node contact pattern205shown inFIG. 13is not aligned with the bit line pattern204, the following problems arise. As shown inFIG. 15A, when the storage node contact56is formed, the bit line54is exposed from the first and second inter-layer insulating films53and55. In this state, as shown inFIG. 15B, the HTO film57is deposited on the whole surface, the whole surface is etch-backed by the RIE method. Then, as shown inFIG. 15C, the side wall spacer58is formed in the storage node contact56so as to be on the bit line54and the side wall of the second inter-layer insulating film55. However, since a part of the bit line54is exposed from a gap of the side wall spacer58, the storage node, not shown, which is formed later and the bit line54are short-circuited.

In addition, when the whole surface of the HTO film57is etch-backed, since the HTO film57and the second inter-layer insulating film55are made of silicon oxide, sufficient selectivity cannot be obtained. Therefore, it becomes difficult to control thicknesses of the insulating film on the bit line54and the second inter-layer insulating film55.

Furthermore, when the storage node contact56is formed, since a contact opening and a contact gap are minute, it is difficult to form a resist pattern. Moreover, the storage node contact56does not have a desired shape, i.e. square shape, and as shown by broken lines inFIG. 13, it has a circular shape. The circular shape has a diameter which is a minimum dimension of the diameter when the storage node contact56is inscribed in a square pattern. The contact area decreases, thereby increasing contact resistance. Moreover, since the storage node contact56reaches the semiconductor substrate51, an aspect ratio becomes large. As a result, the yield of the contact opening is not efficient, and thus it is difficult to plug up the storage node.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductor storage device which is capable of preventing a short-circuit of a contact and a wiring, forming the contact so that the contact is self-aligned, and securely controlling a thickness of a film formed on the wiring, forming a fine contact with an excellent yield of an opening of the contact, and filling up the contact, and relates to a manufacturing method thereof.

In order to achieve the above object, a semiconductor storage device of the present invention comprises:a first insulating film formed on a semiconductor substrate;first and second wirings arranged on the first insulating film at a predetermined interval, the first and second wirings composed of a conductive film, and a second insulating film on the conductive film;a contact hole formed between the first and second wirings, and on the first insulating film between the first and second wirings; anda third insulating film formed in the contact hole, the third insulating film being formed at least on a side wall of the conductive film and a side wall of the first insulating film.

In addition a method of manufacturing a semiconductor storage device comprises the steps of:forming a first insulating film on a semiconductor substrate;forming a conductive film on the first insulating film;forming a protective film on the conductive film;etching the protective film and conductive film locally and forming first and second wirings;forming a second insulating film between the first and second wirings;etching the second insulating film and first insulating film locally by using the protective film as a mask and forming a contact hole between the first and second wirings; andforming a third insulating film at least on a side wall of the conductive film and on a side wall of the first insulating film in the contact hole.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following describes embodiments of the present invention with reference to the drawings.

FIGS. 1A through 1Dshow the first embodiment of the present invention. As shown inFIG. 1A, a first insulating film1made of silicon oxide is formed on a semiconductor substrate11. A conductive film2, such as tungsten (W), a second insulating film3made of silicon oxide, and a third insulating film4made of silicon nitride are formed on the first insulating film1. Thereafter, the third insulating film4, the second insulating film3and the conductive film2are patterned by using a desired wiring pattern so that a wiring L is formed.

Next, as shown inFIG. 1B, a fourth insulating film5made of silicon oxide is deposited on the whole surface, and the surface is planarized by the CMP (Chemical Mechanical Polishing) method. As shown inFIG. 1C, a photo-resist6is formed on the fourth insulating film5by using a desired contact hole pattern. The fourth and first insulating films5and1are etched by the RIE method under an etching condition that a selectivity to the fourth and first insulating films5and1and the third insulating film4is high, and then a contact hole CH is formed.

Next, the resist6is removed, and the fifth insulating film7is deposited on the whole surface. The fifth insulating film7is etch-backed by the RIE method, and as shown inFIG. 1D, a side wall spacer7acomposed of the fifth insulating film7is formed on a side wall of the contact hole CH. The side wall spacer7ais formed on side walls of the first insulating film1, the conductive film2, the second insulating film3, the third insulating film4and the fourth insulating film5.

Since the conductive film2is protected by the third insulating film4, at the timing of etching it by the RIE method, even if alignment is not obtained on a mask, the conductive film2is not exposed. Therefore, even when a conductive layer is formed in the contact hole CH, a short-circuit between the conductive film2and the conductive layer can be prevented.

FIGS. 2A through 2Cshow a second embodiment of the present invention. Here, the parts described in the first embodiment are indicated by the same reference numerals. The manufacturing steps up to the formation of a desired wiring L are the same as the first embodiment. After the wiring L is formed, the fourth insulating film5is deposited on the whole surface, and as shown inFIG. 2A, the surface of the fourth insulating film5is planarized by the CMP method. At this time, the fourth insulating film5is planarized with the upper surface of the third insulating film4by using the third insulating film4as a stopper of CMP.

Next, the photo-resist6is formed by using a desired contact hole pattern. As shown inFIG. 2B, the fourth and first insulating films5and1are etched by the RIE method under the etching condition that the selectivity to the fourth and first insulating films5and1and the third insulating film4is high. Then, the contact hole CH is formed.

After the resist6is removed, the fifth insulating film7is deposited on the whole surface. When the whole surface of the fifth insulating film7is etch-backed by the RIE method, as shown inFIG. 2C, the side wall spacer7acomposed of the fifth insulating film7is formed on the side wall of the contact hole.

Also in this embodiment, the conductive film2is protected by the third insulating film4. For this reason, at the time of etching by the RIE method, even if the alignment is not obtained on a mask, the conductive film2is not exposed. Therefore, even when a conductive layer is formed in the contact hole CH, the short-circuit between the conductive film2and the conductive layer can be prevented. Moreover, since a thickness of the insulating film on the conductive film2is defined by the thicknesses of the second and third insulating films, controllability is satisfactory.

In the first and second embodiments, the material of the fifth insulating film7is, for example, silicon nitride film, silicon oxide film, or a composite film of a silicon nitride film and a silicon oxide film. A dielectric constant of the fifth insulating film7is set smaller than a silicon nitride film.

FIGS. 3 and 4Athrough4C show a third embodiment of the present invention, and the parts described in the first and second embodiments are indicated by the same reference numerals. InFIGS. 4A through 4C, the semiconductor substrate is omitted. As shown inFIGS. 1A and 2A, the manufacturing steps up to the formation of the wiring L are the same as the first and second embodiments. The wiring L is formed by using a strip-like wiring pattern8shown in FIG.3. Thereafter, the fourth insulating film5made of silicon oxide is deposited on the whole surface, and as shown inFIG. 4A, the fourth insulating film5is planarized with the upper surface of the third insulating film4by the CMP method.

Next, the photo-resist6shown inFIG. 4Bis formed by using a linear/space contact hole pattern9which intersects perpendicularly to the wiring pattern8as shown in FIG.3. Then, the fourth and first insulating films5and1are etched by the RIE method under the etching condition that the selectivity to the fourth and first insulating films5and1and the third insulating film4is high, and a contact hole is formed between the wirings.

Next, the resist6is removed, and the fifth insulating film7is deposited on the whole surface. Then, the fifth insulating film7is etch-backed by the RIE method so that, as shown inFIG. 4C, the side wall spacer7ais formed in the contact hole CH by the fifth insulating film7. The widths of wiring pattern8and the contact hole pattern9are set to a minimum dimension which is defined by the design rule.

In this embodiment, since the conductive film2is protected by the third insulating film4, at the time of etching by the RIE method, even if the alignment is not obtained on the mask, the conductive film2is not exposed. Therefore, even when a conductive layer is formed in the contact hole CH, the short-circuit between the conductive film2and the conductive layer can be prevented. Moreover, since the thickness of the insulating film on the conductive film2is defined by the thickness of the second and third insulating film, controllability is satisfactory. Moreover, since the contact hole pattern9has a linear/space shape, the contact hole can be easily formed. Further, when the linear/space contact hole pattern is used, the contact hole has a square shape whose side has a minimum dimension defined by the design rule. Therefore, since the contact hole does not have a circular shape which is inscribed in a square shape having a minimum dimension side unlike the conventional manner, the contact area can be made larger, thereby decreasing the contact resistance.

The following describes a fourth embodiment of the present invention with reference toFIG. 5,FIGS. 6A through 6J,FIGS. 7A through 7G,FIGS. 8A and 8B, andFIGS. 9A through 9E. The fourth embodiment relates to a case where the present invention is applied to a method of manufacturing the STC-type DRAM cell.

FIG. 5is a plan view which shows a mask pattern applied to the fourth embodiment, andFIGS. 6A through 6J,FIGS. 7A through 7G,FIGS. 8A and 8B,FIGS. 9A through 9Eshow the steps of manufacturing according to the fourth embodiment. Namely:FIGS. 6A and 7Ashow the first step;FIGS. 6B and 7Bshow the second step;FIGS. 6C and 7Cshow the third step;FIGS. 6D and 7Dshow the fourth step;FIGS. 6E and 7Eshow the fifth step;FIGS. 8A and 7Fshow the sixth step;FIGS. 8B and 7Gshow the seventh step;FIGS. 6F and 9Ashow the eighth step;FIGS. 6G and 9Bshow the ninth step;FIGS. 6H and 9Cshow the tenth step;FIGS. 6I and 9Dshow the eleventh step; andFIGS. 6J and 9Eshow the twelfth step.

InFIG. 5,101represents an element separating pattern for forming an element separating region,102represents a gate electrode pattern for forming a gate electrode,103represents a plug pattern for forming a plug,104represents a bit line contact pattern for forming a bit line contact,105represents a bit line pattern for forming a bit line,106represents a storage node contact pattern for forming a storage node contact, and107represents a storage node electrode pattern for forming a storage node electrode.

As shown inFIGS. 6A and 7A, an element separating oxide film12is formed on the semiconductor substrate11by using the STI (Shallow Trench Isolation) technique and using the element separating pattern101show inFIG. 5as a mask.

Next, a gate oxide film, not shown, is formed on the semiconductor substrate11. As shown inFIGS. 6B and 7B, an N-type polysilicon film13, a tungsten silicide film14and a silicon nitride film15are deposited on the gate oxide film in this order. Thereafter, the silicon nitride film15and the tungsten silicide film14and the N-type polysilicon film13are patterned by using the gate electrode pattern102shown inFIG. 5, and a MOSFET gate electrode G is formed. Next, ions of N-type impurity such as As are implanted into the semiconductor substrate11on the gate oxide film so that a source/drain diffusion layer16is formed. Thereafter, a silicon nitride film17is deposited on the whole surface, and the silicon nitride film17is etch-backed so that a side wall spacer17acomposed of the silicon nitride film is formed on the side wall of the gate electrode G.

Next, as shown inFIGS. 6C and 7C, a BPSG film18is deposited on the whole surface, and the surface of the BPSG film18is planarized by using the CMP method and using the silicon nitride film15as the stopper. Then, as shown inFIGS. 6D and 7D, a resist19is applied to the whole surface, and an etching mask19ais formed by using the plug pattern103shown in FIG.5and using the lithography method. The BPSG film18is etched by using the RIE method and using the etching mask19aand the silicon nitride film15as the mask under the etching condition that the selectivity to the BPSG film18and the silicon nitride film15is high. With this step, the contact hole20is formed so as to be self-aligned with the gate electrode G.

Next, after the resist19is removed, as shown inFIGS. 6E and 7E, an N-type polysilicon film21is deposited on the whole surface. Thereafter, the surface of the N-type polysilicon film21is planarized by using the CMP method and using the silicon nitride film15and the BPSG film18as a stopper. At the same time, a plug21ais formed in the contact hole20by the N-type polysilicon film21.

As shown inFIG. 8A and 7F, a BPSG film22is deposited on the whole surface, and a contact hole23is formed by using the bit line contact pattern104shown in FIG.5. The position of the contact hole23corresponds to the aforementioned contact hole20. Next, a tungsten film24is selectively grown on the exposed N-type polysilicon thin film21so that the contact hole23is plugged up with the tungsten film24.

A glue layer, not shown, is formed on the whole surface, and as shown inFIGS. 8B and 7G, a tungsten film25, a silicon oxide film26and a silicon nitride film27are deposited in this order. Therefore, the silicon nitride film27, the silicon oxide film26, the tungsten film25and the glue layer are patterned by using the bit line pattern105shown inFIG. 5so that a bit line BL connected to the plug21is formed.

Next, as shown inFIGS. 6F and 9A, a silicon oxide film28is deposited on the whole surface, and the surface of the silicon oxide film28is planarized by using the CMP method and using the silicon nitride film27as a stopper. Then, a resist29is applied to the whole surface, and as shown inFIG. 6G, an etching mask29ais formed by using the lithography method and using the storage node contact pattern106shown in FIG.5. Thereafter, the silicon oxide film28is etched by using the RIE method and using the etching mask29aand the silicon nitride film27as a mask. The etching condition in this case is such that the selectivity of the silicon oxide film28and the silicon nitride film27is high. With this step, a contact hole30is formed so as to be self-aligned with the bit line BL.

After the resist29is removed, as shown inFIGS. 6H and 9C, a silicon oxide film31is deposited on the whole surface. Thereafter, a side wall spacer31a composed of the silicon oxide film31is formed on the side wall of the contact hole30by using the etch-back method. As shown inFIGS. 6I and 9D, an N-type polysilicon film32is deposited on the whole surface, and the surface of the N-type polysilicon film32is planarized by using the CMP method and using the silicon nitride film27and the silicon oxide film28as a stopper. At the same time, a plug32ais formed in the contact hole30by the N-type polysilicon film32.

Next, as shown inFIGS. 6J and 9E, a ruthenium film33is deposited on the whole surface by the sputtering method, and it is patterned by using the storage node electrode pattern107shown in FIG.5. Thereafter, a high dielectric film such as a BST (Barium Strontium Titanate) film34and a ruthenium film35are deposited on the whole surface, and a storage capacitor is formed. Then, a wiring layer, etc., not shown, is formed by a known method, and thus the DRAM is finished.

In accordance with the fourth embodiment, in the STC-type DRAM cell, the bit line is protected by a silicon nitride insulating film. For this reason, even if the storage node contact pattern is not aligned with the bit line pattern, exposure of the bit line can be prevented at the time of etching. Moreover, since the insulating film on the bit line is defined by its thickness, the controllability is satisfactory.

In addition, since the storage node contact pattern has a line/space shape, the storage node contact can be prevented from becoming round, thereby making it possible to make the shape of the storage node contact a square whose side has a minimum dimension. Therefore, the contact area can be made large, thereby decreasing the contact resistance.

In addition, since the storage node contact does not reach the substrate and it is connected to the source/drain domain through the conductive plug, an aspect ratio can be lowered. Therefore, the storage node can be easily plugged up, and thus the yield of the contact opening can be improved.

Furthermore, when the silicon oxide insulating film is used as the side wall spacer, the capacity of the bit line can be prevented from increasing, thereby increasing the operating speed and decreasing current consumption.

FIGS. 10A and 10Bshow a fifth embodiment of the present invention. Here, the parts shown inFIGS. 1A through 4Care indicated by the same reference numerals, and only parts not shown inFIGS. 1A through 4Care described. In the second and third embodiments, the second insulating film3and the third insulating film4(in the fourth embodiment, the silicon oxide film26and the silicon nitride film27) are provided on the conductive layer2. The material of the third insulating film4(in the fourth embodiment, the silicon nitride film27) has the following conditions:(1) when the silicon oxide film is subject to RIE, the selectivity with the silicon oxide film is large;(2) when the silicon oxide film is subject to CMP, the selectivity with the silicon oxide film is large;(3) when the plug is subject to CMP, the selectivity with the plug is large; and(4) an insulating film.

However, as mentioned above, the third insulating film4(in the fourth embodiment, the film27) is composed of the silicon nitride film. The silicon nitride film has a large capacity and decreases the speed of signal transfer through the wiring. Therefore, it is desirable to remove the silicon nitride film.

Therefore, in the fifth embodiment, when the fifth insulating film7is etch-backed, the etching time is made slightly longer, and as shown inFIG. 10A, the fifth insulating film7formed on the side wall of the third insulating film4is removed. Thereafter, as shown inFIG. 10B, the third insulating film4is removed by the process using thermal phosphoric acid. The same effects as the first through fourth embodiments can be obtained in the present embodiment, and a decrease in the speed of signals transfer through the wiring can be obtained. In such a manner, when the third insulating film is removed, the above-mentioned conditions (3) and (4) are not necessary. The present embodiment explains the case of the silicon nitride film, but a conductive film such as polysilicon may be used.

FIGS. 11A through 11Cshow a sixth embodiment of the present invention. In the first through fifth embodiments, the third insulating film4is provided on the second insulating film3, but a conductive film can be provided on the second insulating film3as long as the conditions (1) and (2) are satisfied. In the sixth embodiment, a polysilicon film41is provided on the second insulating film3. Since the polysilicon film41has a higher selectivity with the silicon oxide film, like the first through fourth embodiments, when the silicon oxide film5is etched, the wiring can be protected. However, since the polysilicon film41has conductivity, it should be removed in order to avoid a short-circuit with another film.

Therefore, as shown inFIG. 11A, the fifth insulating film7formed on the side wall of the polysilicon film41is removed like the fifth embodiment. Next, as shown inFIG. 11B, a polysilicon film42is deposited on the whole surface. Thereafter, as shown inFIG. 11C, the polysilicon films41and42are removed by the CMP method, and the contact hole is plugged up by the polysilicon film42. At this time, the silicon oxide film3functions as a stopper. The same effects as the fifth embodiment can be obtained in the present embodiment.

FIG. 12shows a seventh embodiment of the present invention, more specifically, a modification of the sixth embodiment. In the present embodiment, a ruthenium film43, for example, is formed on the second insulating film3, and a ruthenium film44is deposited on the whole surface. Next, in order to manufacture an electrode, the ruthenium film44is etched by using a predetermined pattern, and the ruthenium film44and the ruthenium film43are removed.

The film on the second insulating film3and the film deposited on the whole surface are made of ruthenium. For this reason, when manufacturing an electrode, even if the pattern is slightly misaligned as shown inFIG. 12, no problem arises.

In addition, the material of the film on the second insulating film3is not limited to ruthenium, so a metallic film, for example, which is similar to the film44deposited on the whole surface may be used as long as the aforementioned conditions (1) and (2) are satisfied.