WINDOW-BASED ENVELOPE TRACKING IN A MULTI-ANTENNA TRANSMISSION CIRCUIT

Window-based envelope tracking in a multi-antenna transmission circuit is provided. The multi-antenna transmission circuit includes a power amplifier circuit that amplifies multiple radio frequency (RF) signals concurrently based on a modulated voltage, an envelope tracking integrated circuit (ETIC) that generates the modulated voltage based on a modulated target voltage, and a transceiver circuit that generates the RF signals and the modulated target voltage. The RF signals may be modulated across a wide modulation bandwidth, but the ETIC may have a lower bandwidth limit. Such bandwidth disparity can cause a ripple(s) in the modulated voltage and, consequently, lead to distortions in the RF signals. Herein, the transceiver circuit is configured to perform window-based envelope tracking to thereby determine and add a compensation term(s) in the modulated target voltage. As a result, it is possible to suppress the ripple(s) and prevent distortions in the RF signals across the wide modulation bandwidth.

FIELD OF THE DISCLOSURE

The technology of the disclosure relates generally to a transmission circuit that amplifies and transmits a radio frequency (RF) signal modulated across a wide range of modulation bandwidth.

BACKGROUND

Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capability in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

The redefined user experience relies on higher data rates offered by advanced fifth generation (5G) and 5G new radio (5G-NR) technologies, which typically transmit and receive radio frequency (RF) signals in millimeter wave spectrums. Given that the RF signals are more susceptible to attenuation and interference in the millimeter wave spectrums, the RF signals are typically amplified by state-of-the-art power amplifiers to help boost the RF signals to a higher power before transmission.

Envelope tracking (ET) is a power management technology designed to improve operating efficiency and/or linearity performance of the power amplifiers. In an ET power management circuit, a power management integrated circuit (PMIC) is configured to generate a time-variant ET voltage based on a time-variant voltage envelope of the RF signals, and the power amplifiers are configured to amplify the RF signals based on the time-variant ET voltage. Understandably, the better the time-variant ET voltage is aligned with the time-variant voltage envelope in time and amplitude, the better the performance (e.g., efficiency and/or linearity) that can be achieved at the power amplifiers. However, the time-variant ET voltage can become misaligned from the time-variant voltage envelope in time and/or amplitude due to a range of factors (e.g., group delay, impedance mismatch, etc.). As such, it is desirable to always maintain good alignment between the time-variant voltage and the time-variant voltage envelope and across a wide modulation bandwidth.

SUMMARY

Embodiments of the disclosure relate to window-based envelope tracking in a multi-antenna transmission circuit. The multi-antenna transmission circuit includes a power amplifier circuit that amplifies multiple radio frequency (RF) signals concurrently based on a modulated voltage, an envelope tracking integrated circuit (ETIC) that generates the modulated voltage based on a modulated target voltage, and a transceiver circuit that generates the RF signals and the modulated target voltage. In a non-limiting example, the RF signals can be preprocessed based on a codeword and emitted simultaneously from multiple antennas to form an RF beam. The RF signals may be modulated across a wide modulation bandwidth (e.g., >200 MHz). However, the ETIC may have a bandwidth limit lower than the modulation bandwidth of the RF signals. Such bandwidth disparity can cause a ripple(s) in the modulated voltage and, consequently, lead to distortions in the RF signals. Herein, the transceiver circuit is configured to perform window-based envelope tracking on the RF signals to thereby determine and add a compensation term(s) (digital or analog) in the modulated target voltage. As a result, it is possible to suppress the ripple(s) and prevent distortions in the RF signals across the wide modulation bandwidth.

In one aspect, a multi-antenna transmission circuit is provided. The multi-antenna transmission circuit includes a power amplifier circuit. The power amplifier circuit is configured to amplify multiple RF signals each having a respective one of a plurality of time-variant power envelopes based on a modulated voltage. The multi-antenna transmission circuit also includes an ETIC. The ETIC is configured to generate the modulated voltage based on a modulated target voltage. The multi-antenna transmission circuit also includes a transceiver circuit. The transceiver circuit includes a signal processing circuit. The signal processing circuit is configured to generate the multiple RF signals from a time-variant digital input vector. The transceiver circuit also includes an envelope detector circuit. The envelope detector circuit is configured to generate multiple time-variant amplitude envelopes based on the time-variant digital input vector to each correspond to a respective one of the multiple time-variant power envelopes. The transceiver circuit also includes a target voltage circuit. The target voltage circuit is configured to generate the modulated target voltage based on a selected time-variant amplitude envelope among the multiple time-variant amplitude envelopes.

In another aspect, a wireless device is provided. The wireless device includes a multi-antenna transmission circuit. The multi-antenna transmission circuit includes a power amplifier circuit. The power amplifier circuit is configured to amplify multiple RF signals each having a respective one of a plurality of time-variant power envelopes based on a modulated voltage. The multi-antenna transmission circuit also includes an ETIC. The ETIC is configured to generate the modulated voltage based on a modulated target voltage. The multi-antenna transmission circuit also includes a transceiver circuit. The transceiver circuit includes a signal processing circuit. The signal processing circuit is configured to generate the multiple RF signals from a time-variant digital input vector. The transceiver circuit also includes an envelope detector circuit. The envelope detector circuit is configured to generate multiple time-variant amplitude envelopes based on the time-variant digital input vector to each correspond to a respective one of the multiple time-variant power envelopes. The transceiver circuit also includes a target voltage circuit. The target voltage circuit is configured to generate the modulated target voltage based on a selected time-variant amplitude envelope among the multiple time-variant amplitude envelopes.

In another aspect, a method for performing window-based envelope tracking in a multi-antenna transmission circuit is provided. The method includes amplifying multiple RF signals each having a respective one of multiple time-variant power envelopes based on a modulated voltage. The method also includes generating the modulated voltage based on a modulated target voltage. The method also includes generating the plurality of RF signals from a time-variant digital input vector. The method also includes generating multiple time-variant amplitude envelopes based on the time-variant digital input vector to each correspond to a respective one of the multiple time-variant power envelopes. The method also includes generating the modulated target voltage based on a selected time-variant amplitude envelope among the multiple time-variant amplitude envelopes.

DETAILED DESCRIPTION

Embodiments of the disclosure relate to window-based envelope tracking in a multi-antenna transmission circuit. The multi-antenna transmission circuit includes a power amplifier circuit that amplifies multiple radio frequency (RF) signals concurrently based on a modulated voltage, an envelope tracking integrated circuit (ETIC) that generates the modulated voltage based on a modulated target voltage, and a transceiver circuit that generates the RF signals and the modulated target voltage. In a non-limiting example, the RF signals can be preprocessed based on a codeword and emitted simultaneously from multiple antennas to form an RF beam. The RF signals may be modulated across a wide modulation bandwidth (e.g., >200 MHz). However, the ETIC may have a bandwidth limit lower than the modulation bandwidth of the RF signals. Such bandwidth disparity can cause a ripple(s) in the modulated voltage and, consequently, lead to distortions in the RF signals. Herein, the transceiver circuit is configured to perform window-based envelope tracking on the RF signals to thereby determine and add a compensation term(s) (digital or analog) in the modulated target voltage. As a result, it is possible to suppress the ripple(s) and prevent distortions in the RF signals across the wide modulation bandwidth.

FIG.1is a schematic diagram of an exemplary multi-antenna transmission circuit10wherein a transceiver circuit12is configured according to embodiments of the present disclosure to perform window-based envelope tracking to suppress a ripple(s) in a modulated voltage VCCreceived by a power amplifier circuit14. Herein, the multi-antenna transmission circuit10also includes an ETIC16and an antenna circuit18.

The power amplifier circuit14includes multiple power amplifiers20(1)-20(X) and the antenna circuit18includes multiple antennas22(1)-22(X). Each of the power amplifiers20(1)-20(X) is configured to amplify a respective one of multiple RF signals24(1)-24(X), each of which is associated with a respective one of multiple time-variant power envelopes PIN-1-PIN-X, based on the modulated voltage VCCand provide the respective one of the RF signals24(1)-24(X) to a respective one of the antennas22(1)-22(X). The antennas22(1)-22(X) are configured to simultaneously radiate the amplified RF signals24(1)-24(X) in one or more polarizations (e.g., horizontal and/or vertical). In context of the present disclosure, the RF signals24(1)-24(X) are preprocessed based on a beamforming codeword(s) to ensure that the antennas22(1)-22(X) can radiate the RF signals24(1)-24(X) in an RF beam.

The ETIC16is coupled to the power amplifier circuit14via a conductive path26and configured to generate the modulated voltage VCCbased on a modulated target voltage VTGT. The transceiver circuit12is configured to generate the modulated target voltage VTGTand provide the modulated target voltage VTGTto the ETIC16.

Notably, the ETIC16can be associated with an inductive ETIC impedance LETICand the conductive path26can be associated with an inductive trace impedance LTRACE. As such, the ETIC16and the conductive path26can collectively present a total inductive impedance (LETIC+LTRACE) to the power amplifier circuit14. The power amplifier circuit14and the antenna circuit18, on the other hand, can collectively present a total load impedance RLOAD, which is primarily a resistance, to the ETIC16. The total load impedance RLOADmay interact with the modulate voltage VCCto cause a load current ILOAD.

Specifically, the ETIC16is configured to provide the modulated voltage Von to an output stage in each of the power amplifiers20(1)-20(X). In this regard,FIG.2is a schematic diagram providing an exemplary illustration of an output stage28in each of the power amplifiers20(1)-20(X) of the power amplifier circuit14inFIG.1. Common elements betweenFIGS.1and2are shown therein with common element numbers and will not be re-described herein.

The output stage28can include at least one transistor30, such as a bipolar junction transistor (BJT) or a complementary metal-oxide semiconductor (CMOS) transistor. Taking the BJT as an example, the transistor30can include a base electrode B, a collector electrode C, and an emitter electrode E. The base electrode B is configured to receive a bias voltage VBIAS, and the collector electrode C is coupled to the conductive path26to receive the modulated voltage VCCand output a respective one of the amplified RF signals24(1)-24(X) to a respective one of the antennas22(1)-22(X).

The modulated voltage VCCcan cause a respective one of multiple modulated currents ICC-1-ICC-Xin the output stage28. Each of the modulated currents ICC-1-ICC-Xis a function of a respective one of the time-variant power envelopes PIN-1-PIN-X. In this regard, the amplified RF signals24(1)-24(X) will each be associated with a respective one of multiple time-variant output power envelopes POUT-1-POUT-Xthat is a function of the modulated voltage VCCand the respective one of the modulated currents ICC-1-ICC-X.

With reference back toFIG.1, the total inductive impedance (LETIC+LTRACE) may exhibit a memory effect that can cause degraded RF performance in the multi-antenna transmission circuit10. Moreover, the total inductive impedance (LETIC+LTRACE) can interact with each of the modulated currents ICC-1-ICC-Xto create a ripple in the modulated voltage VCCat the collector electrode C of the transistor30in each of the power amplifiers20(1)-20(X). In this regard, it is desirable to suppress the ripple in the modulated voltage VCCto help improve RF performance of the multi-antenna transmission circuit10.

In this regard, as described in detail below, the transceiver circuit12is configured to perform window-based envelope tracking to determine at least one voltage compensation VTERMthat can suppress the ripple in the modulated voltage VCC. Accordingly, the transceiver circuit12can add the determined voltage compensation VTERMin the modulated target voltage VTGTto thereby suppress the ripple in the modulated voltage VCCand improve the RF performance of the multi-antenna transmission circuit10.

According to an embodiment of the present disclosure, the transceiver circuit12includes a signal processing circuit32, an envelope detector circuit34, and a target voltage circuit36. Specifically, the signal processing circuit32is configured to generate the RF signals24(1)-24(X) from a time-variant digital input vector bMOD→.

The envelope detector circuit34is configured to generate multiple time-variant amplitude envelopes AIN-1-AIN-X, each of which is in a digital format and corresponds to a respective one of the time-variant power envelopes PIN-1-PIN-X, based on the time-variant digital input vector bMOD→. Accordingly, the target voltage circuit36can be configured to generate a combination of the voltage compensation VTERMand the modulated target voltage VTGTbased on the time-variant amplitude envelopes AIN-1-AIN-X.

Specific embodiments of the signal processing circuit32, the envelope detector circuit34, and the target voltage circuit36are now described.FIG.3is a schematic diagram of the signal processing circuit32in the transceiver circuit12inFIG.1. Common elements betweenFIGS.1and3are shown therein with common element numbers and will not be re-described herein.

According to an embodiment, the signal processing circuit32includes a modulator circuit38and a beamformer circuit40. The modulator circuit38is configured to generate a modulated RF signal42from the time-variant digital input vector bMOD→. In a non-limiting example, the modulated RF signal42is modulated to a carrier frequency, such as a millimeter wave (mmWave) frequency, for transmission via the antenna circuit18. The beamformer circuit40, on the other hand, is configured to preprocess the modulated RF signal42based on a beamforming codeword to generate the RF signals24(1)-24(X). The beamforming codeword is a set of complex coefficients that collectively cause the antennas22(1)-22(X) to simultaneously radiate the RF signals24(1)-24(X) in the RF beam.

FIG.4is a schematic diagram of the envelope detector circuit34in the transceiver circuit12inFIG.1. Common elements betweenFIGS.1and4are shown therein with common element numbers and will not be re-described herein.

In an embodiment, the digital input vector bMOD→may be so generated to include an in-phase (I) component and a quadrature (Q) component. In this regard, the digital input vector bMOD→will be associated with a time-variant amplitude √{square root over (I2+Q2)}. Thus, the envelope detector circuit34is configured to include an amplitude detector circuit44that can detect the time-variant amplitude √{square root over (I2+Q2)} of the time-variant digital input vector bMOD→. The envelope detector circuit34further includes multiple scaler circuits46(1)-46(X). Each scaler circuit46(1)-46(X) is configured to scale the detected time-variant amplitude √{square root over (I2+Q2)} based on a respective one of multiple scaling factors β1-βXto thereby generate a respective one of the time-variant amplitude envelopes AIN-1-AIN-X.

Notably, the envelope detector circuit34may not have any knowledge about the time-variant power envelopes PIN-1-PIN-X. As such, the scaling factors β1-βXneed to be so determined to correlate the amplitude envelopes AIN-1-AIN-Xwith the time-variant power envelopes PIN-1-PIN-X, respectively. In one embodiment, the scaling factors β1-βXmay be predetermined and stored in the envelope detector circuit34. In another embodiment, the scaling factors β1-βXmay be dynamically determined and provided to the envelope detector circuit34.

With reference back toFIG.1, according to an embodiment of the present disclosure, the target voltage circuit36includes a voltage processing circuit48, a current processing circuit50, a combiner circuit52, and a digital-to-analog converter (DAC)54. Specifically, the voltage processing circuit48is configured to generate a digital target voltage VDTGTbased on a selected time-variant amplitude envelope among the time-variant amplitude envelopes AIN-1-AIN-X. The current processing circuit50is configured to generate the compensation term VTERM, which is a digital compensation term, based on all the time-variant amplitude envelopes AIN-1-AIN-X. The combiner circuit52is configured to add the compensation term VTERMinto the digital target voltage VDTGTand the DAC54is configured to convert the digital target voltage VDTGTinto the modulated target voltage VTGT.

FIG.5is a schematic diagram of the voltage processing circuit48in the transceiver circuit12inFIG.1. Common elements betweenFIGS.1and5are shown therein with common element numbers and will not be re-described herein.

According to an embodiment of the present disclosure, the voltage processing circuit48includes a multiplexer56, a windowed peak detector circuit58, a lookup table (LUT) circuit60, a current estimator62, an equalizer64, and a combiner66. The multiplexer56is configured to output the selected time-variant amplitude envelope among the time-variant amplitude envelopes AIN-1-AIN-X. In an embodiment, the selected time-variant amplitude envelope is a maximum time-variant amplitude envelope PIN-MAX (PIN-MAX E (PIN-1-PIN-X)) of the time-variant amplitude envelopes AIN-1-AIN-X.

The windowed peak detector circuit58is configured to detect a set of peak amplitudes APK-1-APK-Y(Y<X) of the selected time-variant amplitude envelope (a.k.a. PIN-MAX) by performing window-based envelope tracking.FIGS.6A and6Bare graphic diagrams providing exemplary illustrations of the window-based envelope tracking as performed by the transceiver circuit12inFIG.1.

In a nutshell, the window-based envelope tracking involves taking one or more amplitude samples of the selected time-variant amplitude envelope (a.k.a. PIN-MAX) in each of multiple sampling windows W1-WN and select one or more highest ones of the amplitude samples taken in each of the multiple sampling windows W1-WNto thereby generate the set of peak amplitudes APK-1-APK-Y. Herein, an exact number of the amplitude samples that are sampled in each of the multiple sampling windows W1-WNis denoted by a grouping factor K (K≥1).

In a non-limiting example, the grouping factor K can be determined based on a modulation bandwidth of the RF signals24(1)-24(X). Herein, the grouping factor K is equal to one (K=1) if the modulation bandwidth is below a defined threshold (e.g., 200 MHz). In this regard, the windowed peak detector circuit58will take one amplitude sample of the selected time-variant amplitude envelope (a.k.a. PIN-MAX) in each of the multiple sampling windows W1-WN. As such, the set of peak amplitudes APK-1-APK-Ywill be the same as the amplitude samples taken in the sampling windows W1-WN.

In contrast, the grouping factor K will be greater than one (e.g., K>1) if the modulation bandwidth is above or equal to the defined threshold. As an example, if the grouping factor K is set to be equal to two (K=2), the windowed peak detector circuit58will take two amplitude samples of the selected time-variant amplitude envelope (a.k.a. PIN-MAX) in each of the multiple sampling windows W1-WN. Accordingly, the set of peak amplitudes APK-1-APK-Ywill include one-half (½) of the amplitude samples taken in the sampling windows W1-WN.

In an embodiment, the windowed peak detector circuit58may receive a bandwidth indication68, for example from a digital baseband circuit (not shown) that generates the digital input vector bMOD→, that indicates the modulation bandwidth and determines the grouping factor K accordingly.

FIG.6Aprovides an exemplary illustration of the windowed peak detector circuit58inFIG.5configured to take two amplitude samples70(K=2) in each of the multiple sampling windows W1-WN.FIG.6Bprovides an exemplary illustration of the windowed peak detector circuit58inFIG.5configured to select a peak amplitude 72 from the amplitude samples70taken in each of the multiple sampling windows W1-WNto thereby generate the set of peak amplitude samples APK-1-APK-Y.

With reference back toFIG.5, the LUT circuit60is configured to generate the digital target voltage VDTGTbased on the set of peak amplitudes APK-1-APK-Ydetected in the sampling windows W1-WN. The current estimator62is configured to estimate the load current ILOADin the power amplifier circuit14, which is a function of the modulated voltage VCCand the total load impedance RLOAD(ILOAD=VCC/RLOAD). The equalizer64is configured to generate a load current compensation term VTERM-LOAD to suppress the ripple in the modulated voltage VCCthat is caused by the estimated load current ILOAD. The combiner66is configured to add the load current compensation term VTERM-LOAD to the digital target voltage VDTGT.

FIG.7is a schematic diagram of the current processing circuit50in the transceiver circuit12inFIG.1. Common elements betweenFIGS.1and7are shown therein with common element numbers and will not be re-described herein.

Herein, the current processing circuit50includes multiple current LUT circuits74(1)-74(X), a summing circuit76, and a filter circuit78. The current LUT circuits74(1)-74(X) are each configured to generate a respective one of multiple digital current terms ITERM-1-ITERM-Xthat correspond to a respective one of the time-variant amplitude envelopes AIN-1-AIN-X. The summing circuit76is configured to sum up the digital current terms ITERM-1-ITERM-Xto generate a time-variant digital current term ITERM. The filter circuit78is configured to generate the compensation term VTERMbased on the time-variant digital current term ITERMto compensate for the ripple in the modulated voltage VCCthat is a function of the total inductive impedance (LETIC+LTRACE) presented at the power amplifier circuit14.

The current processing circuit50may also include an adjustable delay circuit80. The adjustable delay circuit80may be coupled between the summing circuit76and the filter circuit78. The adjustable delay circuit80may be configured to introduce an adjustable delay term τ1into the time-variant digital current term ITERM. The adjustable delay term τ1may be determined (e.g., via experiment) to cause the modulated currents ICC-1-ICC-Xto each be time aligned with the modulated voltage VCCat the power amplifier circuit14.

With reference back toFIG.5, the voltage processing circuit48may include a second delay circuit82. The second delay circuit82may introduce a second adjustable delay term τ2into the modulated digital target voltage VDTGT.

With reference back toFIG.3, the signal processing circuit32may include a third delay circuit84. The third delay circuit84may be configured to introduce a third adjustable delay term τ3into the digital input vector bMOD→. In this regard, the adjustable delay term τ1, the second adjustable delay term τ2, and/or the third adjustable delay term τ3may be adjusted to ensure proper alignment among the modulated voltage VCC, the modulated currents ICC-1-ICC-X, and the time-variant power envelope PIN-1-PIN-Xat the power amplifier circuit14.

In an embodiment, the signal processing circuit32may also include a windowing buffer86. The windowing buffer86may be configured to temporally buffer the digital input vector bMOD→based on the grouping factor K. The signal processing circuit32may further include a memory digital predistortion (mDPD) circuit88. The mDPD circuit88can be configured to digitally pre-distort the digital input vector bMOD→before the modulator circuit38generates the modulated RF signal42.

FIG.8is a schematic diagram of an exemplary multi-antenna transmission circuit90configured according to an alternative embodiment of the present disclosure. Common elements betweenFIGS.1and8are shown therein with common element numbers and will not be re-described herein.

The multi-antenna transmission circuit90includes a target voltage circuit91, which further includes a voltage processing circuit92, a current processing circuit94, an analog combiner96, and multiple DACs98(1)-98(X). The DACs98(1)-98(X) are configured to convert the amplitude envelopes AIN-1-AIN-Xinto analog amplitude envelopes. The voltage processing circuit92is configured to generate the modulated target voltage VTGT, which is an analog target voltage, based on the analog amplitude envelopes. The current processing circuit94is configured to generate the compensation term VTERM, which is an analog compensation term, based on the analog amplitude envelopes. The analog combiner96is configured to add the compensation term VTERMinto the modulated target voltage VTGT.

The multi-antenna transmission circuit10ofFIG.1and the multi-antenna transmission circuit90ofFIG.8can be provided in a user element (e.g., a wireless device) to enable memory distortion neutralization according to embodiments described above. In this regard,FIG.9is a schematic diagram of an exemplary user element100wherein the multi-antenna transmission circuit10ofFIG.1and the multi-antenna transmission circuit90ofFIG.8can be provided.

Herein, the user element100can be any type of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element100will generally include a control system102, a baseband processor104, transmit circuitry106, receive circuitry108, antenna switching circuitry110, multiple antennas112, and user interface circuitry114. In a non-limiting example, the control system102can be a field-programmable gate array (FPGA), as an example. In this regard, the control system102can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry108receives radio frequency signals via the antennas112and through the antenna switching circuitry110from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

The baseband processor104processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor104is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

For transmission, the baseband processor104receives digitized data, which may represent voice, data, or control information, from the control system102, which it encodes for transmission. The encoded data is output to the transmit circuitry106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas112through the antenna switching circuitry110. The multiple antennas112and the replicated transmit and receive circuitries106,108may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

In an embodiment, it is possible to perform window-based envelope tracking in the multi-antenna transmission circuit10ofFIG.1and the multi-antenna transmission circuit90ofFIG.8based on a process. In this regard,FIG.10is a flowchart of an exemplary process200for performing window-based envelope tracking in the multi-antenna transmission circuit10ofFIG.1and the multi-antenna transmission circuit90ofFIG.8.

Herein, the process200includes amplifying the RF signals24(1)-24(X), each of which has a respective one of the time-variant power envelopes PIN-1-PIN-X, based on the modulated voltage VCC(step202). The process200also includes generating the modulated voltage VCCbased on the modulated target voltage VTGT(step204). The process200also includes generating the plurality of RF signals24(1)-24(X) from the time-variant digital input vector bMOD→(step206). The process200also includes generating the time-variant amplitude envelopes AIN-1-AIN-Xbased on the time-variant digital input vector bMOD→to each correspond to a respective one of the time-variant power envelopes PIN-1-PIN-X(step208). The process200also includes generating the modulated target voltage VTGTbased on a selected time-variant amplitude envelope among the time-variant amplitude envelopes AIN-1-AIN-X(step210).