Method of manufacturing a semiconductor device with capacitor electrodes

A semiconductor device and a method of manufacturing thereof can be gained wherein the occurrence of defects can be prevented and it is possible to reduce the manufacturing cost. The semiconductor device includes a capacitor electrode, an insulating layer and a wiring layer. The capacitor electrode is formed on the semiconductor substrate. The insulating film which is formed on the capacitor electrode has a trench which exposes part of the capacitor electrode and has an upper surface. The wiring layer fills in the inside of the trench, has an upper surface and is connected with the capacitor electrode. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a manufacturing method thereof, in particular to a semiconductor device with capacitor electrodes and a manufacturing method thereof.

2. Description of the Background Art

Conventionally a DRAM (Dynamic Random Access Memory) as one of the semiconductor devices is known.FIG. 9is a schematic cross section view showing a semiconductor device according to a prior art. The semiconductor device according to a prior art is described with reference to FIG.9.

Referring toFIG. 9, the semiconductor device is a DRAM which includes a field effect transistor and a capacitor formed on a semiconductor substrate101. The capacitor stores an electric charge as a memory signal. And the field effect transistor works as a switching element which controls the storage of the electric charge to the capacitor. Conductive regions102ato102eare formed in the main surface of the semiconductor substrate101with gaps between the regions. The conductive regions102ato102dbecome source and drain regions of the field effect transistors. A gate insulating film103ato103cis formed on the semiconductor substrate101above the channel regions located between the conductive regions102ato102d. Gate electrodes104ato104care formed on the gate insulating film103ato103c. A side wall insulating film105ato105fis formed on the side walls of the gate electrodes104ato104c. A coating insulating film106ato106cis formed on the gate electrodes104ato104c. A field effect transistor is formed of the gate electrode104a, the gate insulating film103aand conductive regions102aand102bas the source and drain regions, respectively. Another field effect transistor is formed of the gate electrode104b, the gate insulating film103band the conductive regions102band102cas the source and drain regions, respectively. Still another field effect transistor is formed of the gate electrode104c, the gate insulating film103cand the conductive regions102cand102das the source and drain regions, respectively.

The first interlayer insulating film107is formed on the coating insulating film106ato106c, the side wall insulating film105ato105fand the main surface of the semiconductor substrate101. Contact holes108aand108bare formed in the regions located above the conductive regions102band102cin the first interlayer insulating film107. Conductive material film109aand109b, such as a doped polysilicon film, is filled in inside the contact holes108aand108b. The second interlayer insulating film110is formed on the first interlayer insulating film107. A contact hole111ais formed in the second interlayer insulating film110in the regions located above the conductive material film109b. In addition, a contact hole111bis formed in the region located above the conductive region102ein the main surface of the semiconductor substrate101by removing part of the first and the second interlayer insulating films107and110. A conductive material film115aand115b, such as a tungsten film, is filled in inside of the contact holes111aand111b, respectively. The first wiling layers112aand112bare formed on the conductive material film115aand115b, respectively.

The third interlayer insulating film113is formed on the first wiling layer112aand112band the second interlayer insulating film110. A contact hole114is formed in the reference located above the conductive material film109aby removing part of the second and of the third interlayer insulating films110and113. A conductive material film116is filled in inside of the contact hole114.

The fourth interlayer insulating film117is formed on the third interlayer insulating film113. A contact hole150is formed in the region located above the first wiring layer112bby removing part of the third and the fourth interlayer insulating films113and117. A conductive material film151is filled in inside of the contact hole150.

The fifth interlayer insulating film118is formed on the fourth interlayer insulating film117. An aperture part119is formed in the regions located above the conductive material film116by removing part of the fourth and the fifth interlayer insulating film117and118. A capacitor lower electrode120which is connected to the conductive material film116is formed inside of the aperture part119. A dielectric film121is formed so as to extend from the capacitor lower electrode120to the upper surface of the fifth interlayer insulating film118. A capacitor upper electrode122is formed on the dielectric film121so as to fill in the inside of the aperture part119and to extend over the upper surface of the fifth interlayer insulating film118. A capacitor is formed of the capacitor lower electrode120, the dielectric film121and the capacitor upper electrode122.

The sixth interlayer insulating film123is formed on the capacitor upper electrode122and the fifth interlayer insulating film118. A contact hole152ais formed in the region located above the capacitor upper electrode122of the sixth interlayer insulating film123. A contact hole152bis formed in the region located above the conductive material film151by removing part of the fifth and the sixth interlayer insulating films118and123. A conductive material film153aand153b, such as a tungsten film, is filled in inside of the contact holes152aand152b. The conductive material film153ais connected to the capacitor upper electrode122. The conductive material film153bis connected to the conductive material film151. The second wiring layer154aand154b, made of aluminum or the like, is formed on the conductive material film152aand152b. The second wiring layer154ais utilized to fix the potential of the capacitor upper electrode122. In a semiconductor device such as a DRAM, as shown inFIG. 9, a plurality of memory cells with capacitors are arranged in a matrix form on the substrate101. Then, an interlayer insulating film (not shown) is formed on the second wiring layer154aand154b.

As for semiconductor devices as represented by DRAM the demand for miniaturization and high levels of integration continues to grow strongly. Therefore, the size of a memory cell of a DRAM as shown inFIG. 9is becoming smaller and smaller. However, it is necessary to store a specific amount of electric charge in a capacitor which stores an electric charge in a memory cell. Therefore, capacitor structures which are in the form of extending in the vertical direction, such as a cylindrical type capacitor as shown in the figures or a thick film type capacitor, have been adopted for the purpose of securing the capacitance of the capacitors while making the size of the memory cells smaller. On the other hand, it is necessary to connect the first wiring112b, which is connected to the conductive region102e, with the second wiling layer154bvia the contact holes152band150for the purpose of supplying a signal to, or of fixing the potential of, the conductive region102e, or the like, which is located below the capacitor upper electrode122. At this time, the contact hole152a, located above the capacitor upper electrode122, and the contact hole152b, located below the second wiring layer154b, have different depths due to the structure of the capacitor. Thereby, in the case that those contact holes152aand152bare formed in one etching step, it is necessary to continue the etching until the contact hole152bachieves a predetermined depth. At this time, the capacitor upper electrode122undergoes excessive etching at the bottom of the contact hole152a. As a result of this, the problem arises that the capacitor upper electrode122receives damage or the contact hole152apenetrates the capacitor upper electrode122. Therefore, conventionally the etching step of forming the contact hole152aand the etching step of forming the contact hole152bare carried out separately. As a result of this, the number of steps for a process of the semiconductor device has increased and this becomes the cause of increased manufacturing cost of a semiconductor device.

In addition, overlapping mask errors in the lithography process for forming the second wiring layer154aand154band the lithography process for forming contact holes152aand152bmake the positions of the second wiring layer154aand154band the contact holes152aand152bshift. In this case, the second wiring layer154aand the capacitor upper electrode122are not connected and, therefore, defects occur in the semiconductor device.

In addition, together with the miniaturization of semiconductor devices the wiring width, the wiling height (section area of the wiring) and the gap between wires of the second wiling layer154aand154bneed to be made smaller. However, as the section area of wires becomes smaller in this way the wire resistance of the second wiring layer154aand154bincreases. Such an increase of the wire resistance leads to a wiling delay. As a result of this some necessary characteristics, such as operational speed, fail to be achieved in the semiconductor device and, in some cases, defects nonetheless occur.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a semiconductor device and a process for the same wherein it is possible to prevent the occurrence of defects and to reduce the manufacturing cost.

A semiconductor device according to one aspect of this invention includes capacitor electrodes, an insulating film and a wiring layer. Capacitor electrodes are formed on the semiconductor substrate. The insulating film, formed on the capacitor electrodes, has trenches, which expose parts of the capacitor electrodes, and an upper surface. The wiling layer is filled in inside of the trenches, has an upper surface and is connected to the capacitor electrodes. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.

In this way, the wires connected to the capacitor electrodes can be in a so-called damascene wiling structure and, therefore, the process for the semiconductor device can be simplified to a greater degree than in the prior art.

In addition, conventionally the capacitor electrodes and a wiring layer, made of aluminum or the like, are connected via a conductive material film, such as tungsten plugs, formed inside of the contact holes. Therefore, the connection interface between the wiring layer and the conductive material film becomes a connection interface between different types of materials, which enhances the interface resistance, or the like, and, therefore, the resistance against electromigration has been reduced. In the present invention, however, the wiling layer is of the damascene wiling structure while parts of the capacitor electrodes are exposed in the trenches so that the lower surface of the wiling layer is in the state directly connected to the capacitor electrodes. Therefore, it is not necessary to form tungsten plugs. Therefore, the resistance against electromigration of the wiring layer can be prevented from becoming reduced.

In addition, by forming trenches in the insulating film and by filling in the inside of the trenches with a conductive material film, the formation of the wiring layer and the contact of the wiring layer with the capacitor electrodes can be implemented at the same time and, therefore, no problem occurs wherein the contact holes and the wiring layer, which is supposed to be formed above these contact holes, become shifted in position, as in the prior art. Accordingly, the occurrence of defects due to such a position shift can be prevented.

In addition, since the upper surface of the wiring layer and the upper surface of the insulating film are located approximately on the same plane, no step exists due to this wiring layer on the upper surface of this wiring layer. Therefore, in the case that another insulating film, or the like, is formed on the insulating film, no step is formed on the upper surface of that other insulating film due to the steps on the upper surface of the wiring layer. Accordingly, in the case that an upper layer wiling layer, or the like, is formed on that other insulating film, defects such as a discontinuity of the upper layer wiring layer due to the above described steps can be prevented from occurring.

In addition, there are cases where another wiring layer formed in the same layer as the wiring layer and the above described conductive region are connected for the purpose of supplying a signal to a conductive region located below the capacitor electrodes. At this time, in a region which is not overlapped with the capacitor electrodes in the same plane, it is necessary to form another contact hole which reaches the above described conductive region, a conductive material film which is filled in inside of that other contact hole and another wiring layer connected to the conductive material film in the insulating film. On the other hand, conventionally a contact hole is formed for the connection between the capacitor electrodes and the wiling layer. Then, since this contact hole and the above described other contact hole have different depths, it is necessary to form them in separate etching steps, respectively. This is because the semiconductor device is miniaturized so as to have a structure where the capacitors extend in the vertical direction and the difference of the depths between the contact hole and the above described other contact hole becomes, increasingly, larger. In the present invention, however, no contact hole is formed on the capacitor electrodes and the lower surface of the wiling layer directly contacts the capacitor electrodes. That is to say, even when the semiconductor device is miniaturized it is not necessary to form a plurality of contact holes of which the depths are different, as in a prior art and, therefore, the manufacturing process of the semiconductor device can be further simplified.

The semiconductor device, according to the above described one aspect of the present invention, may include conductive regions located below the insulating film. It is preferable that contact holes which reach to the conductive regions and the other trenches which are connected to these contact holes are formed in the insulating film. Moreover, the semiconductor device according to the above described one aspect of the present invention, preferably, includes another wiling layer which is filled in inside of the other trenches and the contact holes.

In this case, the other wiling layer formed in the insulating film can be formed in a so-called dual damascene process wherein the inside of the contact holes and the inside of the other trenches are filled in with a conductive material film. Then, as described in the manufacturing process below, the other trenches wherein the above described other wiling layer is located and the trenches where the wiling layer is located are formed in the same etching step so that, in the case that the other wiling layer is formed as described above, the increase in the number of manufacturing steps can be limited to the minimum. Therefore, the increase of the manufacturing cost of the semiconductor device can be held down.

In the semiconductor device according to the above described one aspect of the present invention, the trenches and the other trenches of the insulating film may be formed so as to extend, approximately, in parallel.

In this case, the first wiring layer which contacts the lower surface of the capacitor electrodes can be formed so as to extend parallel the second wiring layer. Accordingly, the contact area between the capacitor electrodes and the wiring layer can be increased and, therefore, the electric contact between the capacitor electrodes and the wiring layer can be made more failure proof.

In the semiconductor device according to the above described one aspect of the present invention, the trenches of the insulating film may include a plurality of aperture parts.

In this case, the contact area between the wiring layer and the capacitor electrodes can be arbitrarily changed by changing the areas of bottoms of the aperture parts. As a result of this, the electric resistance value between the wiring layer and the capacitor electrodes can be arbitrarily changed.

In addition, in the case that the trenches include a plurality of aperture parts in this way and the wiring layer is formed inside of the aperture parts, respectively, an upper layer wiring layer which is located above the wiring layer, may be formed so as to make a connection between respective wiling layer formed inside of the aperture layers.

In the semiconductor device according to the above described one aspect of the present invention, it is preferable that the wiring layer includes copper.

In this case, copper has a lower electrical resistance value than aluminum, which is conventionally used as a material for the wiring layer. Accordingly, in the case that copper is used for the material for the wiring layer the wiring resistance can be reduced more than in the prior art. Therefore, the occurrence of the wiring delay can be prevented.

In the semiconductor device according to the above described one aspect of the present invention, it is preferable that a barrier metal layer is formed on the inside walls of said trenches.

In this case, the barrier metal layer can prevent materials, such as copper, which form the wiring layer from defusing into the insulating film or the capacitor electrodes.

In a method of manufacturing a semiconductor device according to another aspect of the present invention, capacitor electrodes are formed on a semiconductor substrate. An insulating film which has an upper surface is formed on the capacitor electrodes. In the insulating film trenches are formed so as to expose parts of the capacitor electrodes. A conductive material film is formed so as to fill in inside of the trenches and to extend to the upper surface of the insulating film. By removing the conductive material film which is located on the upper surface of the insulating film and by removing parts of the conductive material film which is located on the surface of the trenches in the insulating film, a wiring layer which is made of the conductive material film which fills in inside of the trenches and has an upper surface which is located on, approximately, the same plane as the upper surface of the insulating film is formed.

Here, in a process for a wiring layer which is connected to the capacitor electrodes according to a prior art, the step of forming contact holes in the insulating film, the step of forming a conductive material film inside of the contact holes, the step of removing extra conductive material film located on the upper surface of the insulating film, the step of forming a conductive material film which becomes a wiring layer on the surface of the contact holes and the step of forming a wiling layer by partially removing this conductive material film through etching using a resist film as a mask and carried out. That is to say, according to the process for a semiconductor device in a prior art, the etching steps and the film formation steps are carried out twice, respectively. In the present invention, however, by making the wiring layer electrically connected to the capacitor electrodes have a so-called damascene wiling structure, the step of forming trenches in the insulating film, the step of forming a conductive material film which becomes the wiling layer inside of those trenches and the subsequent step of removing the conductive material film located on the upper surface of the insulating film using a chemical mechanical polishing method (CMP method), or the like, which make up a fewer number of steps than in a prior art, can, together, form the wiling layer. As a result of this, the process for a semiconductor device can be simplified. And by following these steps the semiconductor device according to the present invention can be easily manufactured.

In the method of manufacturing a semiconductor device according to above described other aspect of the present invention, conductive regions located beneath the insulating film may be formed and contact holes which reach to the conductive regions may be formed in the insulating film. The step of forming trenches may include the formation of the other trenches in the regions located above the contact holes of the insulating film. The step of forming the conductive material film may include the formation of a conductive material film which becomes the other wiling layer so as to fill in the inside of the contact holes and the other trenches.

In this case, the step of forming the other trenches located above the contact holes and the step of forming trenches which reach to the capacitor electrodes can be carried out simultaneously. Then, since the wiring layer formed inside of the trenches is directly connected to the capacitor electrodes, it is not necessary to form contact holes into which tungsten plugs, or the like, are filled in separately from the wiling layer on the capacitor electrodes as in the prior art. Therefore, the process for a semiconductor device can be simplified to a greater degree than in a prior art.

In addition, in the case that the depth of the trenches and the other trenches which are formed in one etching step in the insulating film is set at approximately the same distance from the upper surface of the insulating film to the upper surface of capacitor electrodes, excessive etching of the capacitor electrodes at the bottoms of the trenches can be prevented in this etching step. Therefore, the capacitor electrodes can be prevented from undergoing damage through excessive etching.

In the method of manufacturing a semiconductor device according to the above described other aspect of the present invention, the step of forming trenches may include the formation of trenches which extend approximately parallel to the other trenches.

In this case, the one wiring layer which extends in parallel to the other wiling layer and of which the lower surface contacts the upper surface of the capacitor electrodes can be formed. Accordingly, the contact area between the capacitor electrodes and the wiring layer can be increased. As a result of this, the electric connection between the capacitor electrodes and the wiling layer can be made without fail.

In the method of manufacturing a semiconductor device according to the above described other aspect of the present invention, the step of forming trenches may include the formation of a plurality of aperture parts in the insulating film so as to expose parts of the capacitor electrodes.

In this case, by changing the area of the bottoms of the aperture parts the contact area between the wiring layer and the capacitor electrodes can be arbitrarily changed.

In the method of manufacturing a semiconductor device according to the above described other aspect of the present invention, it is preferable for the conductive material film to include copper.

In this case, as a material of the wiling layer copper, of which the electric resistance value is lower than aluminum which is conventionally used, can be used for the wiring layer.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent form the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following embodiments of the present invention are described with reference to the drawings. Here, the same, or the corresponding parts, are denoted by the same reference numerals, of which the descriptions are not repeated in the following figures.

Referring toFIGS. 1 and 2, the first embodiment of a semiconductor device according to the present invention is described.

Referring toFIGS. 1 and 2, the semiconductor device is a DRAM which includes a field effect transistor and a capacitor formed on a semiconductor substrate1. The capacitor stores an electric charge as a memory signal. In addition, the field effect transistor works as a switching element which controls the storage of the electric charge in the capacitor. Conductive regions2ato2eare formed on the main surface of the semiconductor substrate1with gaps between regions. The conductive regions2ato2dbecome the source and drain regions of the field effect transistor. A gate insulating film3ato3cis formed on the semiconductor substrate1above the channel regions located between the conductive regions2ato2d. The gate electrodes4ato4care formed on the gate insulating film3ato3c. A side wall insulating film5ato5fis formed on the side walls of the gate electrodes4ato4c. A covering insulating film6ato6c, which is made of a silicon nitride film, is formed on the gate electrodes4ato4c. A field effect transistor is formed of the gate electrode4a, the gate insulating film3aand the conductive regions2aand2bas the source and drain regions. Another field effect transistor is formed of the gate electrode4b, the gate insulating film3band the conductive regions2band2cas the source and drain regions. Still another field effect transistor is formed of the gate electrode4c, the gate insulating film3cand the conductive regions2cand2das the source and drain regions.

A first interlayer insulating film7is formed on the covering insulating film6ato6c, the side wall insulating film5ato5f, and the main surface of the semiconductor substrate1. Contact holes8aand8bare formed in the regions located above the conductive regions2band2cof the first interlayer insulating film7. A conductive material film9aand9b, such as a doped polysilicon film, is filled in inside the contact holes8aand8b. A second interlayer insulating film10is formed on the first interlayer insulating film7. A contact hole11ais formed in the region located above the conductive material film9bof the second interlayer insulating film10. In addition, a contact hole11bis formed in the region located above the conductive region2ein the main surface of the semiconductor substrate1by removing part of the first and the second interlayer insulating films7and10through etching. A conductive material film15aand15b, such as a tungsten film or a doped polysilicon film, is filled in inside of the contact holes11aand11b, respectively. A first wiring layer12a, which is made of doped polysilicon, is formed on the conductive material film15a. And a first wiring layer12b, which is made of doped polysilicon, is formed as a conductive region on the conductive material film15b.

A third interlayer insulating film13is formed on the first wiring layer12aand12band the second interlayer insulating film10. A contact hole14is formed in the region located above the conductive material film9aby removing part of the second and the third interlayer insulating films10and13. A conductive material film16is filled in inside of the contact hole14.

A fourth interlayer insulating film17is formed on the third interlayer insulating film13. A fifth interlayer insulating film18is formed on the fourth interlayer insulating film17. An aperture part19is formed in the region located above the conductive material film16by removing part of the fourth and the fifth interlayer insulating films17and18. A capacitor lower electrode20, which is connected to the conductive material film16, is formed inside of the aperture part19. A dielectric film21is formed so as to extend from the capacitor lower electrode20to the upper surface of the fifth interlayer insulating film18. A capacitor upper electrode22is formed, on the dielectric film21, as a capacitor electrode so as to fill in inside of the aperture part19and to extend to the upper surface of the fifth interlayer insulating film18. A capacitor is formed of the capacitor lower electrode20, the dielectric film21and the capacitor electrode22.

A sixth interlayer insulating film23is formed as an insulating film on the capacitor upper electrode22and the fifth interlayer insulating film18. A damascene wiling trench25ais formed as a trench in the sixth interlayer insulating film23so as to expose part of the upper surface of the capacitor upper electrode22. In addition, a contact hole24is formed in the region located above the first wiring layer12bof the third to the sixth interlayer insulating films13,17,18and23. A damascene wiring trench25bis formed as another trench in the region located above the contact hole24of the sixth interlayer insulating film23. The damascene wiring trenches25aand25bare formed so as to extend, approximately, parallel to each other. Then, part of the upper surface of the capacitor upper electrode22is exposed at the bottom of the damascene wiring trench25a. Therefore, the contact area between the capacitor upper electrode22and a barrier metal layer34awhich is formed inside of the damascene wiring trench25acan be made large. Accordingly, the electric contact between the capacitor upper electrode22and the conductive material film26aas a damascene wiling layer can be made without fail via the barrier metal layer34a.

A barrier metal layer34aand34bis formed inside of the damascene wiling trenches25aand25bas well as inside of the contact hole24. A conductive material film26ais formed as a wiring layer on the barrier metal layer34aso as to fill in the inside of the damascene wiring trench25a. In addition, a conductive material film26bis formed as another wiring layer on the barrier metal layer34bso as to fill in the inside of the damascene wiling trench25band the inside of the contact hole24. This conductive material film26aand26bis of the so-called damascene wiring type. The upper surface of the conductive material film26aand26band the upper surface of the sixth interlayer insulating film23are located on approximately the same plane. Copper, for example, can be used as the conductive material film26aand26b.

As described above, in the case that copper is used as a material for the conductive material film26aand26bas a wiring layer the wiring resistance can be reduced since copper has the lower electric resistance value than aluminum, which is a conventional wiring material. Therefore, the occurrence of the wiring delay can be prevented. In addition, since the barrier metal layer34aand34bis formed materials such as copper which forms the conductive materials film26aand26bcan be prevented from diffusing into the sixth interlayer insulating film23, or the like.

In addition, the conductive material film26ais utilized so as to fix the potential of the capacitor upper electrode22. In the semiconductor device according to the present invention, a plurality of memory cells which include capacitors and field effect transistors as shown inFIG. 1are arranged in a matrix form on the substrate1.

Here, in a process for a wiring layer154a, which is connected to a capacitor upper electrode122according to a prior art as shown inFIG. 9, the step of forming a contact hole152ain the sixth interlayer insulating film123, the step of forming a conductive material film inside of the contact hole152a, the step of forming a conductive material film153a, such as a tungsten plug, filled in inside of the contact hole152aby removing the extra conductive material film located on the upper surface of the sixth interlayer insulating film123, the step of forming a conductive material film which becomes the wiring layer154aon the contact hole152aand the step of forming the wiring layer154aby partially removing this conductive material film through etching using a resist film as a mask are carried out. That is to say, in the process for a semiconductor device according to a prior art etching steps and film formation steps are carried out twice, respectively.

Referring toFIG. 1, however, by making the wiring layer which includes a conductive material film26aelectrically connected to the capacitor upper electrode22be a damascene wiring structure according to the present invention, a fewer number of steps than in the prior art: the step of forming a damascene wiring trench25ain the sixth interlayer insulating film23, the step of forming a conductive material film which becomes the wiring layer so as to extend from the inside of this damascene wiring trench25ato the upper surface of the sixth interlayer insulating film23and the subsequent step of forming the conductive material film26aby removing the conductive material film located on the upper surface of the sixth interlayer insulating film23using a CMP method, or the like, as shown in the process described later, are necessary for forming the wiling layer. As a result of this, the process for the semiconductor device can be simplified.

In addition, in the semiconductor device according to the present invention as shown inFIG. 1, the damascene wiling, which includes a conductive material film26aas the wiring layer which is connected to the capacitor upper electrode22, is used and the lower surface of the damascene wiling is in the condition connected with the capacitor upper electrode22via the barrier metal layer34a. Therefore, it is not necessary to form the contact hole152a(seeFIG. 9) and the conductive material film153a, such as a tungsten plug (see FIG.9), as in the prior art. Therefore, the interface between different types of materials which is formed between the wiring layer154aand the conductive material film153a, such as a tungsten plug, in the conventional semiconductor device does not exist in the semiconductor device according to the present invention. Accordingly, the resistance against electromigration in the wiring layer connected to the capacitor upper electrode22can be prevented from being reduced.

In addition, in the semiconductor device as shown inFIG. 1, the formation of the conductive material film26aas the wiring layer and the connection between that conductive material film26aand the capacitor upper electrode22are implemented simultaneously by forming a damascene wiring trench25ain the sixth interlayer insulating film23and by filling in the inside of that damascene wiling trench25awith the conductive material film. Therefore, no problem arises wherein the contact hole152a(seeFIG. 9) and the wiling layer154a(seeFIG. 9) are shifted in position due to the error in the lithography processing step as in the prior art. Accordingly, the occurrence of defects due to such a position shift can be prevented.

In addition, since the upper surface of the conductive material film26aand the upper surface of the sixth interlayer insulating film23are located approximately on the same plane, no step is formed on the upper surface of this sixth interlayer insulating film23due to the conductive material film26a. Therefore, in the case that another insulating film, or the like, is formed on the sixth interlayer insulating film23, the deterioration of the planarity on the top surface of the other insulating film, due to the step on the upper surface of the sixth interlayer insulating film23, can be prevented. Accordingly, in the case that an upper layer wiling layer, or the like, is formed on the other insulating film, defects such as a discontinuity of the upper layer wiring layer due to the deterioration of the planarity on the upper surface of the other insulating film can be prevented from occurring.

Next, the process of a semiconductor device as shown inFIGS. 1 and 2is described referring toFIGS. 3to6.

First, an insulating film which becomes the gate insulating film3ato3c(seeFIG. 3) is formed on the main surface of a semiconductor substrate1such as a silicon wafer (see FIG.3). A conductive material film which becomes the gate electrodes4ato4c(seeFIG. 3) is formed on this insulating film. A resist film having a gate electrode pattern is formed on this conductive material film. By partially removing the conductive material film and the insulating film using this resist film as a mask the gate electrodes4ato4cand the gate insulating film3ato3care formed. Next, by implanting a conductive impurity into the main surface of the semiconductor substrate1using the gate electrodes4ato4c, or the like, as a mask, the conductive regions2ato2e(seeFIG. 3) are formed. Moreover, the conductive region2emay be formed in advance by implanting a conductive impurity into the main surface of the semiconductor substrate1using the resist film, or the like, as a mask.

The side wall insulating film5ato5fand the covering insulating film6ato6care formed on the side walls and on the upper surface of the gate electrodes4ato4c. The first interlayer insulating film7(seeFIG. 3) is formed on the covering insulating film6ato6cand on the side wall insulating film5ato5fby using a CVD method (Chemical Vapor Deposition method), or the like. A resist film (not shown) which has a hole pattern is formed on the first interlayer insulating film7. By using this resist film as a mask part of the first interlayer insulating film7is partially removed through etching. After that, the resist film is removed. In this way, the contact holes8aand8b(seeFIG. 3) are formed. A conductive material film is formed so as to fill in inside of the contact holes8aand8band to extend to the upper surface of the first interlayer insulating film7. By removing the conductive material film located on the upper surface of the first interlayer insulating film7through etching, or the like, the conductive material film9aand9b(seeFIG. 3) is formed.

The second interlayer insulating film10(seeFIG. 3) is deposited on the first interlayer insulating film7by using a CVD method, or the like. A resist film which has a hole pattern is formed on the second interlayer insulating film10. By partially removing the second interlayer insulating film10using the film as a mask, the contact holes11aand11b(seeFIG. 3) are formed, The upper surface of the conductive material film9bis exposed at the bottom of the contact hole11a. And the conductive region2eis exposed at the bottom of the contact hole11b. After that, the resist film is removed. A conductive material film which fills in inside of the contact holes11aand11band which extends to the upper surface of the second interlayer insulating film10is formed by using a sputtering method, or the like. As for the material of the conductive material film, tungsten, for example, or the like, can be used. Part of the conductive material film which is located on the upper surface of the second interlayer insulating film10is removed. In this way, the conductive material film15aand15bis formed.

After that, a conductive material film is formed on the second interlayer insulating film10. A resist film which has a wiring pattern is formed on this conductive material film. By partially removing the conductive material film through etching, the first wiring layer12aand12b(seeFIG. 3) is formed. After that, the resist film is removed. The third interlayer insulating film13is formed on the first wiring layer12aand12bby using a CVD method, or the like. A resist film which has a hole pattern is formed on the third interlayer insulating film13. By using the resist film as a mask the second and third interlayer insulating film10and13are partially removed through etching, or the like, and, thereby, the contact hole14(seeFIG. 3) is formed. After that, the resist film is removed. Next, a conductive material film which fills in the inside of the contact hole14and which extends to the upper surface of the third interlayer insulating film13is formed. By removed the conductive material film which is located on the upper surface of the third interlayer insulating film13, the conductive material film16is formed.

The fourth interlayer insulating film17is formed on the third interlayer insulating film13by using a CVD method, or the like. The fifth interlayer insulating film18is formed on the fourth interlayer insulation layer17by using a CVD method, or the like. The resist film (not shown) which has a hole pattern is formed on the fifth interlayer insulating film18. By using the resist film as a mask the fourth and the fifth interlayer insulating film17and18are partially removed through etching and, thereby, the aperture part19is formed. The conductive material film16is exposed at the bottom of the aperture part19. After that, the resist film is removed.

A conductive material film which becomes the capacitor lower electrode is formed so as to extend from the inside of the aperture part19to the upper surface of the fifth interlayer insulating film18. Next, a resist film (not shown) is formed on the conductive material film so as to fill in the inside of the aperture part19in the regions located inside of the aperture part19. After that, the conductive material film which is located on the upper surface of the fifth interlayer insulating film18is removed through dry etching. Here, in the step of removing this conductive material film, a CMP method may be used. After that, the resist film is removed. In this way, the capacitor lower electrode20which is made of a conductive material film is formed inside of the aperture part19.

Next, a dielectric film is formed so as to extend from the capacitor lower electrode20inside of the aperture part19to the upper surface of the fifth interlayer insulating film18. A conductive material film which becomes the capacitor upper electrode22is formed on the dielectric film. A resist film which has a mask pattern is formed on the conductive material film using the resist film as a mask the conductive material film and the dielectric film are partially removed and, thereby, the dielectric film21and the capacitor upper electrode22which make up the capacitor are formed. Here, as for the materials for the capacitor lower electrode20and the capacitor upper electrode22, polysilicon, amorphous silicon, or the like, can be used. In addition, in the case that a dielectric film such as BST or PZT is used as the material for the dielectric film21, metals such as platinum or ruthenium, high melting point metal such as titanium, titanium nitride or a film consisting of a plurality of these layers may be used as the materials for the capacitor lower electrode20and capacitor upper electrode22.

Next, the sixth interlayer insulating film23is formed on the capacitor upper electrode22. A resist film27which has a hole pattern is formed on the sixth interlayer insulating film23. In this way, a structure as shown inFIG. 3is gained.

Next, as shown inFIG. 4, by using the resist film27as a mask the third to the sixth interlayer insulating film13,17,18and23are partially removed through etching and, thereby, the contact hole24is formed. After that, the resist film27is removed.

Next, as shown inFIG. 5, a resist film28which has a pattern for the damascene wiling trenches is formed on the sixth interlayer insulating film23.

Next, as shown inFIG. 6, by using the resist film28as a mask, the sixth interlayer insulating film23is partially removed through etching and, thereby, the damascene wiring trenches25aand25bare formed. The upper surface of the capacitor upper electrode22is exposed at the bottom of the damascene wiling trench25a. After that the resist film28is removed.

In this way, by exposing the capacitor upper electrode22through etching for forming the damascene wiring trenches25aand25b, the damascene wiling layer including the conductive material film26aelectrically connected to the capacitor upper electrode22can be formed without separately forming a contact hole, as shown in a prior art. Accordingly, the process for a semiconductor device can be simplified to a greater extent than in a prior art.

In addition, though the contact hole152awhich is located on the capacitor upper electrode22(seeFIG. 9) and another contact hole152bof which the depth is different and which is located in another region are formed through different etching steps in a prior art, a wiring layer including the conductive material film26bwhich is located inside of the contact hole24and the damascene wiring trench25bis formed through a so-called dual damascene process and, in addition, the damascene wiling trench25afor the wiring layer which is connected to the capacitor upper electrode and the damascene wiring trench25bconnected to the contact hole24are formed through the same etching step and, thereby, the process for a semiconductor device can be simplified according to the present invention. Therefore, the manufacturing cost of the semiconductor device can be reduced.

In addition, the depth of the damascene wiling trenches25aand25bare made approximately equal to the depth from the upper surface of the sixth interlayer insulating film23to the upper surface of the capacitor upper electrode22and, thereby, the capacitor upper electrode22can be prevented from being excessively etched. And since the upper surface of the capacitor upper electrode22is exposed at the bottom of the damascene wiling trench25a, the barrier metal layer34aand the capacitor upper electrode22can be made to contact without fail as described below. Accordingly, the capacitor upper electrode22via the barrier metal layer34aand the entire lower surface of the conductive material film26used as a damascene wiling layer can be connected via the barrier metal layer34a. As a result of this, electric contact between the capacitor upper electrode22and the conductive material film26used as a damascene wiling layer can be made without fail.

Following the step shown inFIG. 6, a barrier metal layer is formed inside of the damascene wiling trenches25aand25bas well as inside the contact hole24. A conductive material film made up of copper, or the like, is formed on the barrier metal layer so as to fill in inside of the damascene wiring trenches25aand25bas well as the inside of the contact hole24and to extend to the upper surface of the sixth interlayer insulating film23. Then, the barrier metal layer and the conductive material film located on the upper surface of the sixth interlayer insulating film23are removed by using a CMP method, or the like. In this way, the barrier metal layer34aand34bas well as the conductive material film26aand26bwhich becomes the damascene wiring type are formed.

In this way, the semiconductor device as shown inFIGS. 1 and 2can be gained.

Referring toFIGS. 7 and 8a semiconductor device of the second embodiment according to the present invention is described.

Referring toFIGS. 7 and 8the semiconductor device is a DRAM, which basically includes the same structure as the semiconductor device of the first embodiment according to the present invention as shown inFIGS. 1 and 2. In the semiconductor device as shown inFIGS. 7 and 8, however, a plurality of contact holes32are formed on the capacitor upper electrode22instead of the damascene wiring trench. The depth of the contact hole32is set so as to be approximately equal to the depth of the damascene wiring trench25b. A barrier metal layer34ais formed inside of this contact hole32in the same way as in the damascene wiring trench25aas shown inFIG. 1. Aconductive material film26a, which includes copper or the like so as to fill in into the contact hole32, is formed on the barrier metal layer34a.

Then, the seventh interlayer insulating film29is formed on the sixth interlayer insulating film. A contact hole30ais formed in the seventh interlayer insulating film29above the contact hole32. A damascene wiling trench31is formed above this contact hole30a. A barrier metal layer35ais formed inside of the contact hole30aand inside of the damascene wiring trench31. A conductive material film33, such as copper, is formed on the barrier metal layer35aso as to fill in the inside of the contact hole30aand the inside of the damascene wiling trench31. The damascene wiring trench31is formed so as to extend in the direction approximately vertical to the paper surface. The conductive material film33is connected, via the contact hole30a, to each of the conductive material films26awhich are located inside of a plurality of contact holes32which are formed so as to be lined up in the direction perpendicular to the paper surface.

In addition, a contact hole30bis formed in the region located above the conductive material film26b. A barrier metal layer35bis formed inside of the contact hole30b. A conductive material film33, such as copper, is formed on the barrier metal layer35bso as to fill in the inside of the contact hole30b.

Here, the contact area between the conductive material film26aand the capacitor upper electrode22can be changed by changing the plane shape of the contact hole32.

The semiconductor device as shown inFIGS. 7 and 8can be processed, basically, by the same steps as in the process for a semiconductor device according to the first embodiment of the present invention as shown inFIGS. 3to6. That is to say, after carrying out the steps as shown inFIGS. 3 and 4, in the step as shown inFIG. 5a hole pattern for forming contact holes32is formed in the regions located above the capacitor upper electrodes22of the resist film28instead of the pattern for the damascene wiring trenches. After that, the step as shown inFIG. 6is carried out. Then, the semiconductor device as shown inFIGS. 7 and 8can be gained by forming the seventh interlayer insulating film29, the contact holes30aand30band the conductive material film33.