Semiconductor device and method for manufacturing the same

A semiconductor device includes a semiconductor element including a semiconductor substrate having an element region, a laminated film formed on the semiconductor substrate and including a low dielectric constant insulating film, and a laser-machined groove provided to cut at least the low dielectric constant insulating film. The semiconductor element is connected to a wiring substrate via a bump electrode. An underfill material is filled between the semiconductor element and the wiring substrate. The fillet length Y (mm) of the underfill material satisfies a condition of Y>−0.233X+3.5 (where X>0, and Y>0) with respect to the width X (μm) of the laser-machined groove.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-255755, filed on Sep. 21, 2006; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method for manufacturing the same.

2. Description of the Related Art

A manufacturing process of a semiconductor device is broadly divided into a step of partitioning a semiconductor wafer into a plurality of element regions by a lattice-shaped dicing line and forming an integrated circuit in each of element regions, a step of cutting the semiconductor wafer along the dicing line to section the respective element regions as semiconductor elements (semiconductor chips), and a step of mounting the semiconductor element on a wiring substrate and packaging it.

To cope with the miniaturization and speeding up of the semiconductor element, the application of low dielectric constant insulating film (Low-k film) which is effective in suppressing a wiring delay (RC delay) (suppression of delay especially by reduction in parasitic capacitance C of wiring) to semiconductor element is promoted. As constituent materials of the Low-k film, for example, fluorine-doped silicon oxide (SiOF), carbon-doped silicon oxide (SiOC), organic silica, porous bodies of them and the like are used.

To a cutting step of a semiconductor wafer, blade dicing which cuts the semiconductor wafer by mechanically cutting it by using a diamond blade is generally applied. When the semiconductor wafer using a Low-k film is cut by blade dicing, there is the problem of easily causing film peeling, cracks and the like due to brittleness and low adhesion strength of the Low-k film. Therefore, prior to blade dicing of the semiconductor wafer having the Low-k film, it is proposed to irradiate laser beam along the dicing line partitioning respective element regions to cut the Low-k film (see JP-A2005-252196 (KOKAI), and JP-A 2006-108489 (KOKAI)).

Concerning the mounting structure (package structure) of the semiconductor element, an FC-BGA (Flip Chip-Ball Grid Alley) package having flip-chip connection in which a wiring path of the semiconductor element and the substrate is short in order to exhibit the performance of the semiconductor element sufficiently is known. In FC-BGA package, the structure in which a heat sink is bonded on the semiconductor element is applied, in order to enhance heat release performance from the semiconductor element which is connected on the wiring substrate. A lid for sealing the semiconductor element is allowed to have the function as the heat sink, and this is bonded to the back surface of the semiconductor element.

The lid which is also used as the heat sink is generally composed of a metal material from the viewpoint of heat release performance. When the package structure including the lid is applied to the semiconductor element having the Low-k film, film peeling in a thermal cycle test (TCT) which is an environment life test becomes a problem. Thermal stress at the time of TCT gives tremendous stress to an edge portion (chip edge) of the semiconductor element existing between the substrate and the lid (heat sink), and this causes film peeling from the chip edge. Because the Low-k film has low film strength of itself and low adhesion to other films, there is the problem of easily causing film peeling on TCT.

Concerning film peeling by a machining damage to the Low-k film at the time of dicing, the film peeling is suppressed by reducing a mechanical damage by applying laser machining. However, film peeling due to the Low-k film also occurs by addition of stress to the chip edge based on the package structure, in addition to the mechanical damage at the time of dicing. Film peeling of the Low-k film based on the package structure cannot be sufficiently suppressed by only the preventive measures against film peeling by application of laser machining. Therefore, in order to enhance manufacturing yield and reliability as the final semiconductor package, suppression of film peeling of the Low-k film based on the package structure is required.

SUMMARY OF THE INVENTION

A semiconductor device according to an aspect of the present invention comprises: a semiconductor element including a semiconductor substrate having an element region, a laminated film formed on the semiconductor substrate and having a low dielectric constant insulating film, and a laser-machined groove provided to enclose the element region, cutting at least the low dielectric constant insulating film of the laminated film, and having a width X (μm); a wiring substrate connected to the semiconductor element via a bump electrode; and an underfill material filled between the semiconductor element and the wiring substrate, and having a fillet shape with a fillet length Y (mm), and in that the fillet length Y (mm) of the underfill material satisfies a condition of Y>−0.233X+3.5 (where X>0, and Y>0) with respect to the width X (μm) of the laser-machined groove.

A method for manufacturing a semiconductor device according to an aspect of the present invention comprises: irradiating a laser beam to a semiconductor wafer having a laminated film including a low dielectric constant insulating film, along a dicing region partitioning a plurality of element regions, to form a laser-machined groove cutting at least the low dielectric constant insulating film of the laminated film and having a width X (μm); cutting the semiconductor wafer along the dicing region by using a blade, to produce semiconductor elements by sectioning the plurality of element regions; connecting the semiconductor element to a wiring substrate via a bump electrode; and fixing the semiconductor element with an underfill material filled between the semiconductor element and the wiring substrate, the underfill material having a fillet shape with a fillet length Y (mm), and in that the underfill material is formed with the fillet length Y (mm) satisfying a condition of Y>−0.233X+3.5 (where X>0, and Y>0) with respect to the width X (μm) of the laser-machined groove.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a mode for carrying out the present invention will be described with reference to the drawings.FIG. 1is a sectional view showing an embodiment of a semiconductor package to which a semiconductor device of the present invention is applied, andFIG. 2is a sectional view showing a part of it by enlarging it. A semiconductor package (semiconductor device)1shown in these drawings has a structure of electrically and mechanically connecting a semiconductor element (semiconductor chip)2and a wiring substrate3with a bump electrode (ball electrode)4constituted of a metallic bump such as a solder bump. The semiconductor element2is connected to the wiring substrate3by flip-chip connection.

The bump electrode4is connected to an electrode pad (not illustrated) of the semiconductor element2and a connecting pad (not illustrated) provided at a top surface of the wiring substrate3respectively. A resin is filled in a gap portion between the semiconductor element2and the wiring substrate3as an underfill material5and solidified. The underfill material5has a fillet shape. Namely, the underfill material5has a fillet5awhich is formed by the resin filled into the gap portion lying off the outer periphery of the semiconductor element2and creeping up the side surface of the semiconductor element2.

The semiconductor element2has an Si substrate6as a semiconductor substrate and a laminated film7which is formed on a surface of the Si substrate6. The Si substrate6has an element region on which an integrated circuit including a transistor and the like (not illustrated) is formed. The laminated film7is formed on a surface6aof the Si substrate6having the element region. The laminated film7constitutes a multilayer wiring film, a protection film and the like, and has a low dielectric constant insulating film (Low-k film) as an interlayer insulating film of the multilayer wiring film. The laminated film7has a local layer8, an intermediate layer9, a semi-global layer10, a global layer11and a passivation layer12formed on the Si substrate6in sequence as shown in, for example,FIG. 3.

The intermediate layer9has a film structure of a four-layer structure of a low dielectric constant insulating film13, a SiOxfilm14such as a TEOS film, and a SiCN film15. The intermediate layer9has a Cu wiring not illustrated in the drawing, and the low dielectric constant insulating film13functions as the interlayer insulating film of the Cu wiring. The local layer8, the semi-global layer10, the global layer11, and the passivation layer12are constituted of the SiOxfilm14such as a TEOS film, a fluorine-doped silica glass (FSG) film16, a non-doped silica glass (NSG) film17, an SiNxfilm18, an Si film19using SiH4, and the like.

A low dielectric constant material having a relative dielectric constant (k value) of 3.3 or less is used for the low dielectric constant insulating film13. As examples of the low dielectric constant insulating film13, a fluorine-doped silicon oxide film (SiOF film), a carbon-doped silicon oxide film (SiOC film), an organic-silica film, a HSQ (hydrogen silsesquioxane) film, a MSQ (methyl silsesquioxane) film, a BCB (benzocyclobutene) film, a PAE (polyarylether) film, a PTFE (polytetrafluoroethylene) film, and further porous films thereof are shown.

The laminated film7is provided with a groove (laser-machined groove)20formed by removing a part of the laminated film7with a laser beam to cut at least the low dielectric constant insulating film13. The laser-machined groove20is formed at the outer peripheral side of the semiconductor element2to enclose the element region (active area) of the Si substrate6. By such a laser-machined groove20, film peeling of the laminated film7based on the machining damage of blade dicing, film peeling especially due to the low dielectric constant insulating film13is suppressed. The laser-machined groove20is preferably formed by being machined to the depth at which the Si substrate6is exposed, the depth of, for example, 1 μm or more.

A bottom surface of the laser-machined groove20is preferably constituted of the Si substrate6. Thereby, the laminated film7can be completely cut by the laser-machined groove20. In forming such a laser-machined groove20with favorable repeatability, the laser beam is preferably irradiated to machine a part of the Si substrate6. In securing cutting performance of the laminated film7, a width X of the laser-machined groove20is preferably set at 3 μm on the Si substrate6. The width X of the laser-machined groove20shows the width of the groove bottom surface. In the laser-machined groove20in which the bottom surface is constituted of the Si substrate6, the width X corresponds to the minimum machined width of the Si substrate6.

In the semiconductor package1of the embodiment, the laser-machined groove20is allowed to have not only the function of cutting the laminated film7, but also the function of suppressing film peeling due to the mounting structure of the semiconductor element2. Therefore, in consideration of a length (fillet length) Y of the fillet5aof the underfill material5as will be described later, the width X of the laser-machined groove20is set. As will be described in detail later, thermal stress added to the laminated film7is relieved as a result that the underfill material5is filled in the laser-machined groove20provided at the outer peripheral portion of the semiconductor element2. Accordingly, film peeling of the laminated film7due to the mounting structure of the semiconductor element2can be suppressed.

As the underfill material5which is filled between the semiconductor element2and the wiring substrate3, for example, an epoxy resin, an acrylic resin, an amine resin, a silicon resin, polyimide resin and the like are used. An underfill resin with a Young's modulus in a range of 5 to 15 GPa and a thermal expansion coefficient in a range of 20 to 40 ppm is especially preferably used.

When the Young's modulus of the underfill resin is less than 5 GPa, there is the fear that stress occurs to the bump electrode4which connects the semiconductor element2and the wiring substrate3, and a crack occurs to the bump electrode4to break the bump electrode4. When the Young's modulus exceeds 15 GPa, warpage of the semiconductor element2follows the warpage of the wiring substrate3and becomes large to be a cause of film peeling from the chip edge. When the thermal expansion coefficient of the underfill resin is less than 20 ppm, it cannot follow the extension of the wiring substrate3, and becomes the cause of breaking the wiring of the wiring substrate3. When the thermal expansion coefficient exceeds 40 ppm, the warpage of the semiconductor element2follows the warpage of the wiring substrate3and becomes large, and becomes the cause of film peeling from the chip edge.

The outer peripheral portion of the underfill material5has the fillet shape. The length Y of the fillet5aof the underfill material5is preferably set at 1 mm or more in achieving uniformity or the like of the coating and filling state of the underfill material5. However, in this case, in consideration of the width X of the laser-machined groove20of the semiconductor element2, the fillet length Y is set. The fillet length Y of the underfill material5shows the maximum length of the fillet5awhich lies off the outer peripheral surface of the semiconductor element2(length of the bottom portion of the fillet5a).

For the wiring substrate3on which the semiconductor element2is mounted, a multilayer wiring substrate to which an insulating substrate such as, for example, a resin substrate, a ceramics substrate, and a glass substrate is applied as the base material is used. As the wiring substrate3to which a resin substrate is applied, an ordinary multilayer copper-clad laminate (multilayer printed wiring board) and the like are cited. An external connection terminal21constituted of a solder bump or the like is provided at the undersurface side of the wiring substrate3. The external connection terminal21is electrically connected to the semiconductor element2via a wiring network by an inner layer wiring and a surface wiring of the bump electrode4and the wiring substrate3.

A vessel-shaped lid22is disposed on the wiring substrate3to seal the semiconductor element2. The lid22also has the function as the heat sink which releases the heat of the semiconductor element2outside the package in addition to the function as the sealing vessel which hermetically seals the semiconductor element2. Accordingly, the outer peripheral end portions of the lid22is hermetically bonded to the wiring substrate3, and in addition to this, the lid22is joined to the back surface of the semiconductor element2via, for example, a thermal compound (TIM material)23. The lid22is generally constituted of a metallic material (Cu or the like) excellent in thermal conductivity.

Next, the manufacturing process of the semiconductor package1according to the embodiment will be described with reference toFIGS. 4 to 6.FIG. 4is a plane view showing a constitution of a semiconductor wafer,FIG. 5is a plane view showing a part of the semiconductor wafer shown inFIG. 4(a region Z enclosed by the square) by enlarging it, andFIG. 6is a sectional view taken along the line A to A inFIG. 5. A semiconductor wafer31shown inFIGS. 4,5and6includes a plurality of element regions32,32. . . , and a dicing region (dicing line)33provided to be in a lattice shape to partition these element regions32. Reference numeral34denotes a ring frame.

The element region32is enclosed by a chip ring35, and an element structure such as a transistor, various kinds of circuits, wirings and the like are formed in the chip ring35. The semiconductor element2is formed by cutting the semiconductor wafer31along the dicing region (dicing line)33to section the element regions32. The element region32has the laminated film7formed on the surface6aof the Si substrate6as described above. The dicing region33is similar to the element region32in the sectional structure and has the Si substrate6and the laminated film7.

On dicing the semiconductor wafer31having the laminated film7, a laser beam is first irradiated to the laminated film7in the dicing region33, and a part of the laminated film7is removed to form the laser-machined groove20. The laser beam is irradiated to the portion (dicing region33) corresponding to the outside of the element region (active area)32. The laser beam is irradiated along the outer periphery of the chip ring35. Thereby, the laser-machined groove20which cuts the laminated film7is formed. The laser-machined groove20is formed to enclose the entire outer periphery of each of the element regions32.

Next, the semiconductor wafer31is cut by using a blade. A portion corresponding to an area further outside the laser-machined groove20(central portion of the dicing region33) is cut with a diamond blade or the like, and each of the element regions32is sectioned to produce the semiconductor element2. Reference numeral36in the drawing shows a cut portion by the blade. As shown inFIGS. 7 and 8, blade dicing may be applied onto the laser-machined groove20. By superimposing the laser dicing region and the blade dicing region, the area of the dicing region33can be reduced. In any case, the laser-machined groove20remains in the outer peripheral portion of the semiconductor element2after being segmented.

Next, a solder ball or the like is loaded on the semiconductor element2to form the bump electrode4, and after flux for connection is coated thereon, the bump electrode4on the semiconductor element2and the wiring substrate3are connected by flip-chip connection. The underfill resin is filled in a gap between the semiconductor element2and the wiring substrate3, and is cured to fix the semiconductor element2with the underfill material5. Thereafter, the thermal compound (TIM material)23is coated on the back surface of the semiconductor element2to joint the lid22to it. Finally, solder balls or the like are fitted to the undersurface of the wiring substrate3to form the external connection terminal21, and thereby, the semiconductor package1of an FC-BGA structure is produced.

In the aforementioned production process, the semiconductor packages1with the width X of the laser-machined groove20fixed to 5 μm, and the fillet lengths Y of the underfill material5set at 1.5 mm and 2.0 mm were produced. The thermal cycle test (TCT) at 125° C. to −55° C. was conducted for these semiconductor packages1. The cumulative fraction defective due to film peeling of the chip edge after the TCT is shown inFIG. 9. As is known fromFIG. 9, as compared with the case where the fillet length Y was set at 1.5 mm, the defective occurred after a longer temperature cycle when the fillet length Y was set at 2.0 mm. By setting the fillet length Y to be longer, reliability against film peeling of the chip edge by the TCT is enhanced.

Based on this point, the result of checking the presence or absence of a film peeling defective after the TCT when the width X of the laser-machined groove20and the fillet length Y of the underfill material5were changed is shown inFIG. 10. The semiconductor element2with the outer shape of 14×14 mm was used, and presence or absence of occurrence of film peeling defective after the TCT with 1000 cycles was checked. InFIG. 10, the crosses represent the products to which film peeling of the chip edge occurred after the TCT with 1000 cycles, whereas the circles represent the products to which film peeling of the chip edge did not occur after the TCT with 1000 cycles. As the concrete examples,FIGS. 11 to 13show the result of checking the presence or absence of occurrence of film peeling under the various kinds of conditions.FIGS. 11 to 13show the analytic images by scanning acoustic tomograph (SAT).

FIG. 11shows the observation result of the semiconductor package with the condition of the point A inFIG. 10(the groove width X: 5 μm, the fillet length Y: 1.5 mm) after the TCT with 1000 cycles.FIG. 12shows the observation result of the semiconductor package with the condition of the point B inFIG. 10(the groove width X: 5 μm, the fillet length Y: 2 mm) after the TCT with 1000 cycles.FIG. 13shows the observation result of the semiconductor package with the condition of the point C inFIG. 10(the groove width X: 10 μm, the fillet length Y: 1.5 mm) after the TCT with 1000 cycles. In these drawings, the portions which look white are the portions where film peeling occurred. Whereas under the conditions of the point A and the point B inFIG. 10, film peeling occurred, film peeling did not occur under the condition of the point C.

With respect to the conditions other than the points A, B and C, the TCT was conducted for the semiconductor packages with the groove width X and the fillet length Y changed, and it was checked whether or not film peeling occurred after 1000 cycles. The result shows that in the semiconductor packages1with selection of the conditions within the area in which the fillet length Y with respect to the groove width X is set to be longer than the line of [Y=−0.233X+3.5] inFIG. 10, occurrence of film peeling can be suppressed after the TCT with 1000 cycles. By setting the fillet length Y of the underfill material5to be long, and by setting the width X of the laser-machined groove20to be wide, reliability of the semiconductor package1for the TCT (reliability against the film peeling of the chip edge) can be enhanced.

When a TCT is conducted for the semiconductor package1of the FC-BGA structure, deformation due to thermal stress occurs to the semiconductor package1based on the difference of the thermal expansion coefficients of the semiconductor element2and the lid22, the difference of thermal expansion coefficients of the semiconductor element2and the wiring substrate3and the like. The stress based on the deformation is applied to the end portion (chip edge) of the semiconductor element2which is connected to the wiring substrate3. By the stress applied to the chip edge, film peeling occurs to the laminated film7of the semiconductor element2. Especially, because the low dielectric constant insulating film13has low film strength of itself and low adhesion strength to the other materials, film peeling easily occurs when the stress is applied to the chip edge.

For film peeling due to thermal stress at the time of a TCT, the fixing force of the chip edge is increased and stress is relieved by making the fillet length Y of the underfill material5long. Accordingly, film peeling of the laminated film7due to the TCT can be suppressed. As described above, the fillet length Y is preferably set to be 1 mm or more to make the filling state of the underfill material5uniform. Further, in suppressing the film peeling of the laminated film7with favorable repeatability, the fillet length Y is preferably set to be 1.5 mm or more.

As the fillet length Y of the underfill material5is made longer, reliability against a TCT is enhanced (margin against occurrence of film peeling increases), but since other components may be loaded near the semiconductor element2depending on a package design, the fillet length Y is restricted. In consideration of the restriction by design, the fillet length Y is preferably set at 5 mm or less, more preferably 3.5 mm or less.

For relieving the stress applied to the chip edge during TCT, the fillet length Y and the laser-machined groove20provided along the outer periphery of the semiconductor element2effectively function. Specifically, the laser-machined groove20suppresses film peeling of the laminated film7at the time of dicing, and remains as an empty groove in the outer peripheral portion of the semiconductor element2after being segmented. When the semiconductor element2having such a laser-machined groove20is applied to the semiconductor package1of the FC-BGA structure, the underfill material5is also filled into the laser-machined groove20when the underfill material5is filled between the semiconductor element2and the wiring substrate3.

The underfill material5filled in the laser-machined groove20functions as the fixing material for the end surface of the laminated film7. By increasing the width X of the laser-machined groove20, the fixing force of the end surface of the laminated film7by the underfill material5increases. Accordingly, film peeling of the laminated film7due to a TCT can be suppressed. Even when the fillet length Y of the underfill material5cannot be sufficiently made long, film peeling of the laminated film7due to TCT can be suppressed with favorable repeatability by increasing the width X of the laser-machined groove20.

In more reliably increasing the fixing strength of the end surface of the laminated film7by the underfill material5which is filled in the laser-machined groove20, the width X of the laser-machined groove20is preferably set at 5 μm or more. However, if the width of the laser-machined groove20is made too wide, increase or the like of the dicing region of the semiconductor element2is caused, and therefore, the width X of the laser-machined groove20is preferably set at 40 μm or less, more preferably at 20 μm or less. Even when the width X of the laser-machined groove20cannot be sufficiently large, film peeling of the laminated film7by a TCT can be suppressed with favorable repeatability by making the fillet length Y of the underfill material5long.

As described above, the fillet length Y of the underfill material5and the width X of the laser-machined groove20are respectively restricted, but by increasing the fixing force of the end portion of the laminated film7based on the constitutions of both of them, film peeling of the laminated film7based on the mounting structure of the semiconductor element2can be suppressed with favorable repeatability. By selecting the conditions in which the fillet length Y with respect to the width X of the laser-machined groove20is made longer than the line of [Y=−0.233X+3.5] inFIG. 10, film peeling of the laminated film7after TCT can be suppressed without greatly changing the design conditions of the semiconductor package1and the semiconductor element2from the conventional package structure.

FIG. 12shows the result of evaluating the adhesiveness of the film to the chip edge by an m-ELT method (modified-Edge Lift off Test). Them-ELT method is the evaluation method which calculates the fracture energy which causes film peeling. First, an epoxy resin with a known thermal property is coated on the test film as a measurement sample and cured. By contracting the epoxy resin by lowering the temperature of the sample, peeling stress is applied to the end portion of the test film. The remaining stress of the epoxy resin is obtained from the temperature at which peeling occurs at the end portion of the test film, and from the remaining stress, the fracture energy (adhesion strength) of the test film is calculated.

As is known fromFIG. 12, the strength of the film single body is 0.274 MPa·m1/2, whereas the adhesion strength of the film at the chip edge when laser machined is increased by 30% or more to be 0.361 MPa·m1/2when the laser machined width is 13.2 μm. For reference, the adhesion strength when step cut is performed with a blade is shown. In this case, the effect of increasing strength is smaller as compared with the case of applying laser machining. Further, as the machined width by laser becomes larger, adhesion of the chip edge is improved. This corresponds to the effect by the laser machined width.

As described above, by applying the structure and manufacturing process in which the width X (μm) of the laser-machined groove20of the semiconductor element2and the fillet length Y (mm) of the underfill material5satisfy the condition of Y>−0.233X+3.5 (where X>0, and Y>0), film peeling of the laminated film7based on the mounting structure of the semiconductor element2(FC-BGA structure) can be suppressed with favorable repeatability. The manufacturing yield, reliability of the semiconductor package1in which the semiconductor element2having the laminated film7including the low dielectric constant insulating film13is connected on the wiring substrate3can be significantly enhanced. The semiconductor package (semiconductor device)1of the FC-BGA structure excellent in reliability can be produced with high yield.

The present invention is not limited to the above described embodiment, but the present invention can be applied to semiconductor devices having various kinds of structures and their manufacturing methods, and manufacturing methods of semiconductor devices having various kinds of process steps. Such semiconductor devices and their manufacturing methods are considered to be included in the present invention. The embodiment of the present invention can be expanded or changed within the scope of the technical idea of the present invention, and the extended and changed embodiments are considered to be included in the technical scope of the present invention.