Latency-Reduced Quantum Error Detection Graph Decoding

Systems and methods for error detection in a quantum computing system are provided. In one example, the method includes obtaining a multidimensional quantum error detection graph. The multidimensional quantum error detection graph represents one or more quantum error detection measurements across a time period. The method includes determining a partitioning scheme and a fusing scheme for the multidimensional quantum error detection graph based at least in part on a decoding latency and a fusing latency. The method includes partitioning the multidimensional quantum error detection graph into a plurality of blocks based at least in part on the partitioning scheme. The method includes decoding each of the plurality of blocks. The method includes fusing the plurality of blocks into a decoded detection graph based at least in part on the fusing scheme. The method includes operating a quantum computing system based at least in part on the decoded detection graph.

FIELD

The present disclosure relates generally to quantum computing systems and more particularly to error correction for quantum computing systems.

BACKGROUND

Quantum computing is a computing method that takes advantage of quantum effects, such as superposition of basis states and entanglement to perform certain computations more efficiently than a classical digital computer. In contrast to a digital computer, which stores and manipulates information in the form of bits, e.g., a “1” or “0,” quantum computing systems can manipulate information using quantum bits (“qubits”). A qubit can refer to a quantum device that enables the superposition of multiple states, e.g., data in both the “0” and “1” state, and/or to the superposition of data, itself, in the multiple states. In accordance with conventional terminology, the superposition of a “0” and “1” state in a quantum system may be represented, e.g., as a|0+b|1The “0” and “1” states of a digital computer are analogous to the |0and |1basis states, respectively of a qubit.

SUMMARY

One example aspect of the present disclosure is directed to a computer-implemented method. The method includes obtaining, by one or more computing devices, a multidimensional quantum error detection graph. The multidimensional quantum error detection graph represents one or more quantum error detection measurements across a time period. The method includes determining, by the one or more computing devices, a partitioning scheme and a fusing scheme for the multidimensional quantum error detection graph based at least in part on a decoding latency and a fusing latency. The method includes partitioning, by the one or more computing devices, the multidimensional quantum error detection graph into a plurality of blocks based at least in part on the partitioning scheme. The method includes decoding, by the one or more computing devices, each of the plurality of blocks. The method includes fusing, by the one or more computing devices, the plurality of blocks into a decoded detection graph based at least in part on the fusing scheme. The method includes operating a quantum computing system based at least in part on the decoded detection graph.

These and other features, aspects, and advantages of various embodiments of the present disclosure will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate example embodiments of the present disclosure and, together with the description, explain the related principles.

DETAILED DESCRIPTION

Example aspects of the present disclosure are directed to systems, devices, and computer-implemented methods for error detection in quantum computing systems. More particularly, example aspects are directed to the decoding of multidimensional quantum error detection graphs for use in a quantum error correction process. For instance, a quantum error correction process may include reducing the error rate of logical qubits of a quantum computing system by detecting and tracking physical errors within the system. Uncorrected physical errors can generate errors in the logical qubit, but the quantum computing system may be configured to permit identification and tracking of the physical errors. In this way, operations can be implemented (e.g., at a classical processing level) to mitigate effects of such physical errors and lead to improved performance of a quantum computing system.

For instance, in some embodiments, each logical qubit may be encoded in a plurality of physical qubits. For instance, a code (e.g., a topological code, such as a surface code) may encode a logical qubit using a plurality of data qubits and a plurality of measurement qubits. The measurement qubits may be configured such that their respective states can be measured to detect physical errors (e.g., errors of the physical qubits and/or of their measurement). These error detection measurements can be measured over a time period and subsequently combined to build an error detection graph, with the weights of the graph links corresponding to an associated error probability.

Over time, detection graphs may become sizable and cumbersome, and the process of decoding these graphs becomes costly (e.g., in terms of time or latency). Latency of decoding may be defined as a time interval between the time in which all measurements needed to determine a logical observable first become available to the time a prediction of the observable is available. Latency of decoding will limit the logical clock speed of a fault-tolerant quantum computer. As such, there is a need within the field for a process capable of effectively and efficiently decoding a detection graph so timely operations may be conducted on a quantum computing system to correct potential errors.

Techniques for leveraging error correlations may be computationally expensive. For example, some techniques require processing all error detection measurements to determine a first set of results, adjusting the probabilities of certain error detection measurements according to known correlations among the first set of results, and then re-processing all error detection measurements with the adjusted probabilities. For real-time tracking of quantum errors, intervals between subsequent error detection measurements are generally on the scale of microseconds, and the iterative global processing of the entire set of error detection measurements can result in substantial computational overhead.

Advantageously, systems and methods according to example aspects of the present disclosure allow for the creation and operation of a decoding system that can parallelize its work across space and time by partitioning a quantum error detection graph into separate decoding blocks that can be independently decoded and fusing the results from each block into one overall decoding prediction that can subsequently be used to operate a quantum computing system.

For example, in some embodiments, a computer-implemented method can include the process by which one or more computing devices receive a multidimensional quantum error detection graph. The quantum error detection graph may represent quantum error detection measurements across a time period. The computer-implemented method can partition the quantum error detection graph into a plurality of blocks, decode the individual blocks, and fuse the individual blocks together to obtain a decoded graph, which can then be used to operate the quantum computing system.

More specifically, in some examples, a plurality of fusion tree data structures may be generated for the detection graph. Each fusion tree data structure may include a partitioning scheme for partitioning the detection graph into a plurality of blocks (e.g., right rectangular prisms) and a schedule of fusions. The latency of each fusion tree may be estimated using two functions: (1) a function for estimating decoding time for each block; and (2) a function for estimating fusing time for two or more blocks. A latency optimal fusion tree (LOFT) process may be implemented to determine a fusion tree that reduces the latency of the decoder.

The inputs to the LOFT process may include the quantum error detection graph along with at least one arbitrary function that estimates the costs of (a) decoding within a quantum error detection block and (b) fusing two adjacent quantum error detection blocks. The LOFT process may determine from a range of partitioning and fusing schemes for the weighted quantum error detection graph which partitioning and fusing scheme will have the best latency and select the partitioning and fusing scheme for decoding the quantum error detection block.

Systems and methods according to example aspects of the present disclosure can provide for a number of technical effects and benefits, including but not limited to improvements to computing technology (e.g., quantum computing technology). For instance, example aspects of the present disclosure can provide for reduced evaluation time of error information and/or evaluating error information in a scalable manner. Example aspects of the present disclosure also provide a unique focus on low latency, which is an important aspect of efficient quantum computers. This is especially beneficial in real-world (e.g., noisy) quantum computing applications, which present a need for rapid, real-time error tracking on an increasing number of qubits.

FIG.1depicts an example quantum computing system100. The system100is an example of a system of one or more classical computers and/or quantum computing devices in one or more locations, in which the systems, components, and techniques described below can be implemented. Those of ordinary skill in the art, using the disclosures provided herein, will understand that other quantum computing devices or systems can be used without deviating from the scope of the present disclosure.

The system100includes quantum hardware102in data communication with one or more classical processors104. The classical processors104can be configured to execute computer-readable instructions stored in one or more memory devices to perform operations, such as any of the operations described herein. The quantum hardware102includes components for performing quantum computation. For example, the quantum hardware102includes a quantum system110, control device(s)112, and readout device(s)114(e.g., readout resonator(s)). The quantum system110can include one or more multi-level quantum subsystems, such as a register of qubits (e.g., qubits120). In some implementations, the multi-level quantum subsystems can include superconducting qubits, such as flux qubits, charge qubits, transmon qubits, gmon qubits, spin-based qubits, and the like.

The type of multi-level quantum subsystems that the system100utilizes may vary. For example, in some cases it may be convenient to include one or more readout device(s)114attached to one or more superconducting qubits, e.g., transmon, flux, gmon, xmon, or other qubits. In other cases, ion traps, photonic devices or superconducting cavities (e.g., with which states may be prepared without requiring qubits) may be used. Further examples of realizations of multi-level quantum subsystems include fluxmon qubits, silicon quantum dots or phosphorus impurity qubits.

Quantum circuits may be constructed and applied to the register of qubits included in the quantum system110via multiple control lines that are coupled to one or more control devices112. Example control devices112that operate on the register of qubits can be used to implement quantum gates or quantum circuits having a plurality of quantum gates, e.g., Pauli gates, Hadamard gates, controlled-NOT (CNOT) gates, controlled-phase gates, T gates, multi-qubit quantum gates, coupler quantum gates, etc. The one or more control devices112may be configured to operate on the quantum system110through one or more respective control parameters (e.g., one or more physical control parameters). For example, in some implementations, the multi-level quantum subsystems may be superconducting qubits and the control devices112may be configured to provide control pulses to control lines to generate magnetic fields to adjust the frequency of the qubits.

The quantum hardware102may further include readout devices114(e.g., readout resonators). Measurement results108obtained via measurement devices may be provided to the classical processors104for processing and analyzing. In some implementations, the quantum hardware102may include a quantum circuit and the control device(s)112and readout devices(s)114may implement one or more quantum logic gates that operate on the quantum hardware102through physical control parameters (e.g., microwave pulses) that are sent through wires included in the quantum hardware102. Further examples of control devices include arbitrary waveform generators, wherein a DAC (digital to analog converter) creates the signal.

The readout device(s)114may be configured to perform quantum measurements on the quantum system110and send measurement results108to the classical processors104. In addition, the quantum hardware102may be configured to receive data specifying physical control qubit parameter values106from the classical processors104. The quantum hardware102may use the received physical control qubit parameter values106to update the action of the control device(s)112and readout devices(s)114on the quantum system110. For example, the quantum hardware102may receive data specifying new values representing voltage strengths of one or more DACs included in the control devices112and may update the action of the DACs on the quantum system110accordingly. The classical processors104may be configured to initialize the quantum system110in an initial quantum state, e.g., by sending data to the quantum hardware102specifying an initial set of parameters106.

In some implementations, the readout device(s)114can take advantage of a difference in the impedance for the |0and |1states of an element of the quantum system, such as a qubit, to measure the state of the element (e.g., the qubit). For example, the resonance frequency of a readout resonator can take on different values when a qubit is in the state |0or the state |1, due to the nonlinearity of the qubit. Therefore, a microwave pulse reflected from the readout device114carries an amplitude and phase shift that depend on the qubit state. In some implementations, a Purcell filter can be used in conjunction with the readout device(s)114to impede microwave propagation at the qubit frequency.

In some embodiments, the quantum system110can include a plurality of qubits120arranged, for instance, in a two-dimensional grid122. For clarity, the two-dimensional grid122depicted inFIG.1includes 4×4 qubits, however in some implementations the system110may include a smaller or a larger number of qubits. In some embodiments, the multiple qubits120can interact with each other through multiple qubit couplers, e.g., qubit coupler124. The qubit couplers can define nearest neighbor interactions between the multiple qubits120. In some implementations, the strengths of the multiple qubit couplers are tunable parameters. In some cases, the multiple qubit couplers included in the quantum computing system100may be couplers with a fixed coupling strength.

In some implementations, each qubit in the multiple qubits120can be operated using respective operating frequencies, such as an idling frequency and/or an interaction frequency and/or readout frequency and/or reset frequency. The operating frequencies can vary from qubit to qubit. For instance, each qubit may idle at a different operating frequency. The operating frequencies for the qubits120can be chosen before a computation is performed.

In some implementations, the multiple qubits120may include data qubits, such as qubit126and measurement qubits, such as qubit128. A data qubit is a qubit that participates in a computation being performed by the system100. A measurement qubit is a qubit that may be used to determine an outcome of a computation performed by the data qubit. That is, during a computation an unknown state of the data qubit is transferred to the measurement qubit using a suitable physical operation and measured via a suitable measurement operation performed on the measurement qubit.

In some examples, the qubit grid122may act as a quantum surface code. As illustrated inFIG.2, qubit grid122can be an interlaced qubit grid of one or more data qubits126and/or one or more measurement qubits128. For instance, some of all of the data qubits126can be used to implement a time series of quantum gate operations defining a quantum algorithm across some or all data qubits126. A data qubit126can be surrounded by measurement qubits128. Additionally and/or alternatively, a measurement qubit128can be positioned within a square or other surface defined by two or more (e.g., four) data qubits126. The measurement qubits128can be configured to provide readouts and/or measure errors (e.g., parity) in outputs of the data qubits126. Error can be detected based on parity or differences between the measurement qubits128surrounding or near a data qubit126.

FIG.1depicts one example quantum computing system that can be used to implement the methods and operations according to example aspects of the present disclosure. Other quantum computing systems can be used without deviating from the scope of the present disclosure.

FIG.2depicts an overview of at least a portion of an error detection process for a quantum computing system (e.g., the quantum computing system ofFIG.1) according to example embodiments of the present disclosure.FIG.2depicts example generation of an error detection graph130from an example qubit grid122(e.g., a surface code). The error detection graph130may have an x-axis and y-axis corresponding to the x-y spatial dimensions of the surface code. The error detection graph130may have a z-axis corresponding to time. The error detection graph130may have nodes corresponding to detection events (e.g., endpoints of mismatched parity). For instance, in some implementations, a computing system can receive error information including coordinates describing endpoints of mismatched parity (e.g., between data qubits and/or measurement qubits). This may be used to build the error detection graph130. The error detection graph130may be provided to a decoder140which may decode portions of the error detection graph130in parallel. Decoding the error detection graph130may include, in some examples, solving for a minimum cost alternating path between pairs of endpoints to provide a decoded graph150. The minimum cost alternating path can be indicative of a most likely source of error resulting in the mismatched parity at the endpoints. Thus, the minimum cost alternating path can be indicative of a position of the qubit at which an error has occurred. In some cases, these errors can propagate through a quantum computation, and so prompt detection and/or correction can be beneficial.

According to example aspects of the present disclosure, a quantum error detection graph130may be partitioned into blocks for parallel processing by the decoder140. The blocks may be decoded in parallel and fused back together to reduce latency. According to examples aspects of the present disclosure, a LOFT process145may be implemented, for instance, by a classical computing system, to determine the best way to partition the error detection graph into blocks (e.g., rectangular prisms), decode each individual block, and fuse the blocks back together to reduce latency of the decoding process.

FIG.3depicts example partitioning of an error detection graph130. More particularly,FIG.3depicts two different partitioning schemes for partitioning the error detection graph130. In partitioning scheme202, the error detection graph130is partitioned into blocks202.1,202.2,202.3. . .202.nby partitioning in the time dimension (z-axis). Each of the blocks202.1,202.2,202.3, . . .202.nmay be decoded (e.g., in parallel) and fused back together to provide a decoded error detection graph. In the partitioning scheme202, each block202.1,202.2,202.3. . .202.nhave equal size.

In partitioning scheme204, the error detection graph130is partitioned into blocks204.1,204.2, . . .204.27, . . .204.nby portioning in the time dimension (z-axis) as well as in the spatial dimensions (x-dimension and y-dimension) associated with the qubit grid122(e.g., surface code). Each of the blocks204.1,204.2, . . .204.27. . .204.nmay be decoded (e.g., in parallel) and fused back together to provide a decoded error detection graph. In the partitioning scheme204, each block204.1,204.2, . . .204.27, . . .204.nhave equal size.

FIG.3depicts two example partitioning schemes for purposes of illustration and discussion. Those of ordinary skill in the art, using the disclosures provided herein, will understand that the error detection graph130may be partitioned and fused back together in a variety of ways. According to example aspects of the present disclosure, a LOFT process may be implemented to determine an optimal way to partition and fuse blocks to reduce latency in processing the error detection graph130.

Each block202.1,202.2,202.3. . .202.nor block204.1,204.2, . . .204.27, . . .204.nmay have a volume. Moreover, there may be an area between adjacent blocks that are fused together. For instance, referring to block202.1as an example, the block202.1may have a volume V and a boundary area A for fusing with block202.2. The cost of decoding a block with volume V is c1*V. The cost of fusing blocks having a boundary area A between the blocks is c2*A.

As used herein, the individual decoding blocks are illustrated as right rectangular prisms. Those of ordinary skill in the art, using the disclosures provided herein, will understand that the blocks may have other suitable shapes without deviating from the scope of the present disclosure.

The LOFT process may determine which fusion tree (e.g., partitioning scheme and fusion scheme) may provide the best latency (e.g. least latency) for decoding an error detection graph. The inputs of the LOFT process may be the error detection graph along with two functions that estimate costs/latency for decoding a block and costs/latency for fusing two blocks together. One example function for estimating costs/latency associated with fusing blocks may provide a constant latency/cost for fusing two blocks. Another example function for estimating costs/latency associated with fusing blocks may provide a cost/latency proportional to the boundary area A between two blocks. The decoding costs/latency associated with decoding blocks may be determined, for instance, using a union-find based algorithm and/or a minimum weight perfect matching (MWPM) algorithm.

According to example aspects of the present disclosure, the LOFT process may determine a plurality of fusion tree data structures for an error detection graph.FIG.4depicts a representation of an example fusion tree250according to example aspects of the present disclosure. Each fusion tree250includes two components. The first component is the partitioning scheme252for partitioning the error detection graph130(e.g., partitioning scheme202) into a plurality of blocks. The second component is a tree data structure254that specifies a partial ordering in which the blocks (e.g., blocks202.1,202.2, and202.3) are fused together.

As shown, the blocks202.1(Block A),202.2(Block B), and202.3(Block C) are represented by leaf nodes in the tree data structure254. In the example ofFIG.4, blocks202.1and202.2are fused to generate a fused block represented by node256. The fused block represented by node256is then fused with block202.3to generate the fused block represented by node258. Aspects of the present disclosure are discussed with reference to binary trees for purposes of illustration and discussion. Those of ordinary skill in the art, using the disclosures provided herein, will understand that aspects of the present disclosure may be implemented with tree structures of any degree (e.g., ternary trees, etc.).

There may be multiple fusion trees for each partitioning scheme. For instance,FIG.5depicts another example fusion tree260associated with the partitioning scheme252. In the example ofFIG.5, the fusion tree260includes two components. The first component is the partitioning scheme252for partitioning the error detection graph130(e.g., partitioning scheme202) into a plurality of blocks. The second component is a tree data structure264that specifies a partial ordering in which the blocks (e.g., blocks202.1,202.2, and202.3) are fused together.

As shown, the blocks202.1(Block A),202.2(Block B), and202.3(Block C) are represented by leaf nodes in the tree data structure264. In the example ofFIG.5, blocks202.2and202.3are fused to generate a fused block represented by node266. The fused block represented by node266is then fused with block202.1to generate the fused block represented by node268.

Aspects of the present disclosure are directed to determining a fusion tree that provides optimal latency for decoding an error detection graph. For instance, given a detection graph G=(V, E), a fusion tree W for G is a tuple W=(L, T), where:(1) L is a list L=[S1, . . . , Sn] of disjoint subsets of V whose union is V (the set of detector vertices in the matching graph). This is an example partitioning scheme.(2) A rooted tree T with root node labeled r and n leaf nodes labeled 1, . . . , n. This is the tree data structure.

A fusion tree W specifies a procedure for decoding on the graph G. The Siare the blocks. The n leaf nodes correspond to S1, . . . , Sn, respectively. Each block may be decoded individually, starting as soon as its final measurement is available. The blocks are then fused according to T, where each internal node corresponds to a fusion of its children.

To estimate the latency of decoding with a fusion tree W=(L, T), the time to decode within a block and the time to fuse two blocks together is estimated. For instance, suppose that each vertex v∈V has a time coordinate t(v) at which it becomes available. For convenience, given subset S⊂V, define

The latency of decoding a subset S of V is defined as the difference between t(S) and the time at which the decoding of S is completed. Suppose we have access to two functions:

(1) Tdecode(S) returns the time to decode a set S.

(2) Tfuse(S1, S2) returns the time to fuse the outputs of decoding on S1 and S2 separately into an output of decoding on S1␣S2.

Tfuse and Tdecode can be arbitrary functions. As discussed above, Tfuse may provide a constant latency/cost for fusing two blocks. Another example function for estimating costs/latency associated with fusing blocks may provide a cost/latency proportional to the boundary area A between two blocks. Tdecode may include, for instance, a union-find based algorithm and/or a minimum weight perfect matching (MWPM) algorithm. In some examples, empirically-observed detection frequencies for each vertex in G can be used to better estimate Tfuse and Tdecode. In some examples, Tfuse and Tdecode may include a lookup table of latency/costs based on, for instance, size of blocks or other parameters.

The latency W of a fusion tree may be determined as follows. Each vertex v∈T corresponds to an intermediate decoding output for some subset S(v). This output will become available at some time, as follows. A leaf node of T, labeled i, corresponds to decoding within block Si. This process may start exactly at t(Si) (i.e., as soon as possible). Then the output will become available at time t(i):=t(Si)+Tdecode(Si).

An interior node v∈T with children c1, c2 corresponds to a fusion of the outputs of those children. This process will start at max(t(c1), t(c2)) and complete in time Tfuse(S(c1), S(c2)). Therefore, t(v):=max(t(c1), t(c2))+Tfuse(S(c1), S(c2)).

The latency of decoding the graph G with a fusion tree W=(L, T) is denoted Latency(W). From the preceding, Latency(W)=t(r)−t(V), where r is the root node of T. Given W and G, it is easy to compute Latency(W). We can use recursion starting from the root node, or simply build up t(v) for each node v∈T starting from the leaves.

In some examples, the LOFT process may choose W that minimizes Latency(W) for some G. One example LOFT process algorithm is provided below:

Consider an example where T is a binary tree and all interior nodes correspond to fusing right rectangular prisms to produce a right rectangular prism. Two functions to estimate latency for fusion Tfuse, Tdecode, have been defined for t: V→[0, ∞) as defined above. The min_latency(S) may be defined recursively in pseudocode as follows:

Dynamic programming may be used in some examples to take advantage of the fact that there are only polynomially many subsets S (i.e., the rectilinear prisms in V). The resulting algorithm is as follows:

FIG.6depicts example partitioning schemes that may be determined by a LOFT process according to example embodiments of the present disclosure. As demonstrated inFIG.6, a variety of possible solutions may be determined. For instance, partitioning scheme182includes no partitioning. Partitioning scheme184includes partitions along the time dimension into unequal block sizes. Partitioning scheme186includes partitions along the time dimension into unequal block sizes. Partitioning scheme188includes partitions along the time dimension into unequal block sizes. Partitioning scheme190includes partitions along the spatial (x- and/or y-dimensions) and time dimension into unequal block sizes.

FIG.7depicts a flow chart of an example method200according to example embodiments of the present disclosure. The operations may be implemented by a quantum and/or classical computing system. For instance, the operations may be implemented by the computing system300(e.g., one or more processors312of the computing system) depicted inFIG.10. The method200illustrates operations performed in a particular order for purposes of illustration and discussion. Those of ordinary skill in the art, using the disclosures provided herein, will understand the various operations of any of the methods described herein can be adapted, modified, rearranged, omitted, include steps not illustrated, and/or expanded in various ways without deviating from the scope of the present disclosure.

At (202), the method includes obtaining a multidimensional quantum error detection graph. The multidimensional quantum error detection graph may represent one or more quantum error detection measurements across a time period. For instance, the method may include obtaining the quantum error detection graph130. The quantum error detection measurements may be derived from a surface code. For instance, the quantum error detection measurements may result from parity between qubits (e.g., data qubits126and measurement qubits128) in a surface code.

At (204), the method includes determining a partitioning scheme and a fusing scheme for the multidimensional quantum error detection graph based at least in part on a decoding latency and a fusing latency. For instance, the method may implement a LOFT process145as described with reference toFIGS.2-6to determine the partitioning scheme and the fusing scheme to reduce latency.

FIG.8depicts a flow chart of determining a partitioning scheme and a fusing scheme according to example embodiments of the present disclosure. The operations may be implemented by a quantum and/or classical computing system. For instance, the operations may be implemented by the computing system300(e.g., one or more processors312of the computing system) depicted inFIG.10.FIG.8illustrates operations performed in a particular order for purposes of illustration and discussion. Those of ordinary skill in the art, using the disclosures provided herein, will understand the various operations of any of the methods described herein can be adapted, modified, rearranged, omitted, include steps not illustrated, and/or expanded in various ways without deviating from the scope of the present disclosure.

At (252), determining a partitioning scheme and a fusing scheme may include generating a plurality of fusion tree data structures. Each fusion tree data structure may include data indicative of a candidate partitioning scheme and data indicative of a candidate fusing scheme associated with the candidate partitioning scheme. Example fusion tree data structure are discussed with reference toFIGS.4and5.

At (254), determining a partitioning scheme and a fusing scheme may include selecting one of the plurality of fusion tree data structures as a selected fusion tree data structure based on a decoding latency associated with the candidate partitioning scheme and a fusing latency associated with the candidate fusing scheme. For instance, one or more functions may be used to estimate a latency associated with each candidate partition scheme and a latency associated with a candidate fusing scheme. One example function for estimating costs/latency associated with fusing blocks may provide a constant latency/cost for fusing two blocks. Another example function for estimating costs/latency associated with fusing blocks may provide a cost/latency proportional to the boundary area A between two blocks. The decoding costs/latency associated with decoding blocks may be determined, for instance, using a union-find based algorithm and/or a minimum weight perfect matching (MWPM) algorithm. In some examples, the candidate fusion tree data structure with least latency may be selected as the selected fusion tree data structure.

At (256), determining a partitioning scheme and a fusing scheme may include determining the partitioning scheme and the fusing scheme for the multidimensional quantum error detection graph based at least in part on the selected fusion tree data structure. For instance, the candidate partitioning scheme and the candidate fusing scheme associated with the selected fusion tree data structure may be determined as the partitioning scheme and the fusing scheme respectively.

Referring back toFIG.7at (206), the method200may include partitioning the multidimensional quantum error detection graph into a plurality of blocks based at least in part on the partitioning scheme. The blocks may be right rectangular prisms in some examples. However, the blocks may have other suitable shapes without deviating from the scope of the present disclosure. In some examples, the blocks may have equal size as illustrated inFIG.3. In some examples, the blocks may have unequal sizes as illustrated inFIG.6. The partitioning scheme may partition the quantum error detection graph in the time dimension. In some examples, the partitioning scheme may partition the quantum error detection graph in the spatial (e.g., x- and/or y-dimensions) and the time dimension.

At (208), the method may include decoding each of the plurality of blocks. For instance, decoding each of the blocks may include solving for a minimum cost alternating path between pairs of endpoints to provide a decoded graph. The minimum cost alternating path can be indicative of a most likely source of error resulting in the mismatched parity at the endpoints. Thus, the minimum cost alternating path can be indicative of a position of the qubit at which an error has occurred.

At (210), the method may include fusing plurality of blocks into a decoded detection graph based at least in part on the fusing scheme. The fusing scheme may be the fusing scheme determined at (204) using, for instance, the LOFT process.

At (212), the method may include operating a quantum computing system based at least in part on the decoded detection graph. For instance, the method may include implementing one or more error correction processes based on the decoded detection graph.

FIG.9depicts a flow chart diagram of one example error correction process according to example embodiments of the present disclosure. The operations may be implemented by a quantum and/or classical computing system. For instance, the operations may be implemented by the computing system300(e.g., one or more processors312of the computing system) depicted inFIG.10.FIG.9illustrates operations performed in a particular order for purposes of illustration and discussion. Those of ordinary skill in the art, using the disclosures provided herein, will understand the various operations of any of the methods described herein can be adapted, modified, rearranged, omitted, include steps not illustrated, and/or expanded in various ways without deviating from the scope of the present disclosure.

At (262), operating the quantum computing system may include identifying one or more qubit(s) at which an error has occurred from the decoded detection graph. As discussed above, the decoded detection graph may include data indicative of a position of the qubit at which an error has occurred.

At (264), operating the quantum computing system may include performing a corrective action at the qubit. In some examples, the corrective action may include resetting the qubit, calibrating the qubit, implementing a quantum gate at the qubit to compensate for the error, or other suitable quantum computing operation. In some examples, the corrective action may include implementing a classical computing process to compensate for the error at the qubit (e.g., modifying an output to compensate for the error).

FIG.10depicts a block diagram of an example computing system300that can be used to implement the systems and methods according to example embodiments of the present disclosure, such as the methods discussed with reference toFIGS.7-9. The system300includes a classical computing system310and a quantum computing system330that are communicatively coupled over a network350. One or more aspects of any of the methods described herein can be implemented on the classical computing system310and/or the quantum computing system330.

The classical computing system310can include any type of computing device (e.g., classical computing device). The classical computing system310includes one or more processors312and a memory314. The one or more processors312can include any suitable processing device (e.g., a processor core, a microprocessor, an ASIC, a FPGA, a controller, a microcontroller, etc.) and can be one processor or a plurality of processors that are operatively connected. The memory314can include one or more non-transitory computer-readable storage mediums, such as RAM, ROM, EEPROM, EPROM, flash memory devices, magnetic disks, etc., and combinations thereof. The memory314can store data316(e.g., qubit parameters, measurements, etc.) and instructions318which are executed by the processor312to cause the classical computing system310to perform operations, such as one or more aspects of any of the method disclosed herein. The classical computing system310can be configured to process error information (e.g., error detection graphs320) obtained by measuring outputs of a quantum system (e.g., quantum system340) to identify errors in quantum computations according to example embodiments of the present disclosure.

The quantum computing system330includes one or more processors332and a memory334. The one or more processors332can include suitable processing device (e.g., a processor core, a microprocessor, an ASIC, a FPGA, a controller, a microcontroller, etc.) and can be one processor or a plurality of processors that are operatively connected. The memory334can include one or more non-transitory computer-readable storage mediums, such as RAM, ROM, EEPROM, EPROM, flash memory devices, magnetic disks, etc., and combinations thereof. The memory334can store data336and instructions338which are executed by the processor332to cause the quantum computing system330to perform operations, such as implementation of a quantum circuit having one or more quantum gates on a quantum system340having a plurality of qubits and obtaining associated measurements (e.g., error detection graphs320). The quantum computing system330can be similar to the quantum computing system discussed and described with reference toFIG.1. Other suitable quantum computing systems can be used without deviating from the scope of the present disclosure.

The network350can be any type of communications network, such as a local area network (e.g., intranet), wide area network (e.g., Internet), or some combination thereof and can include any number of wired or wireless links. In general, communication over the network350can be carried via any type of wired and/or wireless connection, using a wide variety of communication protocols (e.g., TCP/IP, HTTP, SMTP, FTP), encodings or formats (e.g., HTML, XML), and/or protection schemes (e.g., VPN, secure HTTP, SSL). In some implementations, the network350may be omitted such that the classical computing system310is in direct signal communication with quantum computing system330.

Implementations of the digital, classical, and/or quantum subject matter and the digital functional operations and quantum operations described in this specification can be implemented in digital electronic circuitry, suitable quantum circuitry or, more generally, quantum computational systems, in tangibly-implemented digital and/or quantum computer software or firmware, in digital and/or quantum computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term “quantum computing systems” may include, but is not limited to, quantum computers/computing systems, quantum information processing systems, quantum cryptography systems, or quantum simulators.

Implementations of the digital and/or quantum subject matter described in this specification can be implemented as one or more digital and/or quantum computer programs (e.g., one or more modules of digital and/or quantum computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, data processing apparatus). The digital and/or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits/qubit structures, or a combination of one or more of them. Alternatively or in addition, the program instructions can be encoded on an artificially-generated propagated signal that is capable of encoding digital and/or quantum information (e.g., a machine-generated electrical, optical, or electromagnetic signal) that is generated to encode digital and/or quantum information for transmission to suitable receiver apparatus for execution by a data processing apparatus.

The terms quantum information and quantum data refer to information or data that is carried by, held, or stored in quantum systems, where the smallest non-trivial system is a qubit (i.e., a system that defines the unit of quantum information). It is understood that the term “qubit” encompasses all quantum systems that may be suitably approximated as a two-level system in the corresponding context. Such quantum systems may include multi-level systems, e.g., with two or more levels. By way of example, such systems can include atoms, electrons, photons, ions or superconducting qubits. In many implementations the computational basis states are identified with the ground and first excited states, however it is understood that other setups where the computational states are identified with higher level excited states (e.g., qubits) are possible.

The term “data processing apparatus” refers to digital and/or quantum data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing digital and/or quantum data, including by way of example a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer, or multiple digital and quantum processors or computers, and combinations thereof. The apparatus can also be, or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array), or an ASIC (application-specific integrated circuit), or a quantum simulator, i.e., a quantum data processing apparatus that is designed to simulate or produce information about a specific quantum system. In particular, a quantum simulator is a special purpose quantum computer that does not have the capability to perform universal quantum computation. The apparatus can optionally include, in addition to hardware, code that creates an execution environment for digital and/or quantum computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

A digital or classical computer program, which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a digital computing environment. A quantum computer program, which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and translated into a suitable quantum programming language, or can be written in a quantum programming language, e.g., QCL, Quipper, Cirq, etc..

A digital and/or quantum computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub-programs, or portions of code. A digital and/or quantum computer program can be deployed to be executed on one digital or one quantum computer or on multiple digital and/or quantum computers that are located at one site or distributed across multiple sites and interconnected by a digital and/or quantum data communication network. A quantum data communication network is understood to be a network that may transmit quantum data using quantum systems, e.g. qubits. Generally, a digital data communication network cannot transmit quantum data, however a quantum data communication network may transmit both quantum data and digital data.

The processes and logic flows described in this specification can be performed by one or more programmable digital and/or quantum computers, operating with one or more digital and/or quantum processors, as appropriate, executing one or more digital and/or quantum computer programs to perform functions by operating on input digital and quantum data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA or an ASIC, or a quantum simulator, or by a combination of special purpose logic circuitry or quantum simulators and one or more programmed digital and/or quantum computers.

For a system of one or more digital and/or quantum computers or processors to be “configured to” or “operable to” perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. For one or more digital and/or quantum computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by digital and/or quantum data processing apparatus, cause the apparatus to perform the operations or actions. A quantum computer may receive instructions from a digital computer that, when executed by the quantum computing apparatus, cause the apparatus to perform the operations or actions.

Digital and/or quantum computers suitable for the execution of a digital and/or quantum computer program can be based on general or special purpose digital and/or quantum microprocessors or both, or any other kind of central digital and/or quantum processing unit. Generally, a central digital and/or quantum processing unit will receive instructions and digital and/or quantum data from a read-only memory, or a random access memory, or quantum systems suitable for transmitting quantum data, e.g. photons, or combinations thereof.

Some example elements of a digital and/or quantum computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and digital and/or quantum data. The central processing unit and the memory can be supplemented by, or incorporated in, special purpose logic circuitry or quantum simulators. Generally, a digital and/or quantum computer will also include, or be operatively coupled to receive digital and/or quantum data from or transfer digital and/or quantum data to, or both, one or more mass storage devices for storing digital and/or quantum data, e.g., magnetic, magneto-optical disks, or optical disks, or quantum systems suitable for storing quantum information. However, a digital and/or quantum computer need not have such devices.

Digital and/or quantum computer-readable media suitable for storing digital and/or quantum computer program instructions and digital and/or quantum data include all forms of non-volatile digital and/or quantum memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks; and quantum systems, e.g., trapped atoms or electrons. It is understood that quantum memories are devices that can store quantum data for a long time with high fidelity and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

Control of the various systems described in this specification, or portions of them, can be implemented in a digital and/or quantum computer program product that includes instructions that are stored on one or more tangible, non-transitory machine-readable storage media, and that are executable on one or more digital and/or quantum processing devices. The systems described in this specification, or portions of them, can each be implemented as an apparatus, method, or electronic system that may include one or more digital and/or quantum processing devices and memory to store executable instructions to perform the operations described in this specification.

Aspects of the disclosure have been described in terms of illustrative implementations thereof. Numerous other implementations, modifications, or variations within the scope and spirit of the appended claims can occur to persons of ordinary skill in the art from a review of this disclosure. Any and all features in the following claims can be combined or rearranged in any way possible. Accordingly, the scope of the present disclosure is by way of example rather than by way of limitation, and the subject disclosure does not preclude inclusion of such modifications, variations or additions to the present subject matter as would be readily apparent to one of ordinary skill in the art. Moreover, terms are described herein using lists of example elements joined by conjunctions such as “and,” “or,” “but,” etc. It should be understood that such conjunctions are provided for explanatory purposes only. Lists joined by a particular conjunction such as “or,” for example, can refer to “at least one of” or “any combination of” example elements listed therein, with “or” being understood as “and/or” unless otherwise indicated. Also, terms such as “based on” should be understood as “based at least in part on.”

Those of ordinary skill in the art, using the disclosures provided herein, will understand that the elements of any of the claims, operations, or processes discussed herein can be adapted, rearranged, expanded, omitted, combined, or modified in various ways without deviating from the scope of the present disclosure. Some of the claims are described with a letter reference to a claim element for exemplary illustrated purposes and is not meant to be limiting. The letter references do not imply a particular order of operations. For instance, letter identifiers such as (a), (b), (c), . . . , (i), (ii), (iii), . . . , etc. can be used to illustrate operations. Such identifiers are provided for the ease of the reader and do not denote a particular order of steps or operations. An operation illustrated by a list identifier of (a), (i), etc. can be performed before, after, or in parallel with another operation illustrated by a list identifier of (b), (ii), etc.