Replacement metal gate stack for diffusion prevention

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.

BACKGROUND

The present invention generally relates to semiconductor devices and more particularly to fabricating semiconductor structures having a gate stack that may prevent unwanted diffusion to a gate dielectric interface.

Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FET) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. Most common among these may be metal-oxide-semiconductor field effect transistors (MOSFET), in which a gate structure may be energized to create an electric field in an underlying channel region of a substrate, by which charge carriers are allowed to travel through the channel region between a source region and a drain region of the substrate. The gate structure may be formed above the channel region and may generally include a gate dielectric layer as a part of or underneath other gate elements. The gate dielectric layer may include an insulator material, which may prevent leakage currents from flowing into the channel region when a voltage is applied to a gate electrode, while allowing the applied voltage to set up a transverse electric field in the channel region in a controllable manner.

In a replacement metal gate (RMG) fabrication approach, a dummy gate may be formed in the substrate. The dummy gate may be patterned and etched from a polysilicon layer above the substrate, over a portion of one or more fins formed from the substrate. In some cases, the dummy gate may be formed surrounding a nanowire or above a semiconductor-on-insulator (SOI) substrate. Gate spacers may be formed on opposite sidewalls of the dummy gate. The dummy gate and the gate spacers may then be surrounded by an interlevel dielectric (ILD) layer. Later, the dummy gate may be removed from between the gate spacers, as by, for example, an anisotropic vertical etch process such as a reactive ion etch (RIE). This may create a recess between the gate spacers where a metal gate, or gate electrode, may then be formed. A gate dielectric layer may be generally configured below the metal gate, although one or more layers of workfunction metals may be generally located between the gate dielectric layer and the metal gate. This sequence of layers including the gate dielectric layer, the workfunction metals and the metal gate may be referred to as a metal gate stack.

SUMMARY

The ability to manufacture semiconductor structures including a high-k gate dielectric layer protected from unwanted diffusion may facilitate advancing the capabilities of current CMOS technology.

According to one embodiment of the present disclosure, a method of forming a semiconductor structure may include depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate, a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer may be deposited above the gate dielectric substantially filling the recess and then the protective layer may be selectively recessed to the gate dielectric layer until a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer may be recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. During the recessing of the first portion of the gate dielectric layer, the protective layer may protect the second portion of the gate dielectric layer. The protective layer may be removed and a conductive barrier may be deposited above the recessed first portion of the gate dielectric layer. A metal gate may be formed above the conductive barrier and a capping layer may be formed above the metal gate with the conductive barrier separating the capping layer from the recessed first portion of the gate dielectric layer.

According to another embodiment of the present disclosure, a semiconductor structure may include a gate structure formed above a substrate, the gate structure may include a metal gate above a conductive barrier, and a gate dielectric layer below the conductive barrier and a capping layer above the gate structure. The conductive barrier may separate the capping layer from the gate dielectric layer.

According to another embodiment of the present disclosure, a semiconductor structure may include a first gate structure and a second gate structure, with a length of the second gate structure being greater than a length of the first gate structure, and a capping layer above the first gate structure and the second gate structure. The first gate structure may include a first metal gate above a first conductive barrier, and a first gate dielectric layer below the first conductive barrier, with the first conductive barrier separating the capping layer from the first gate dielectric layer. The second gate structure may include a second metal gate above a second conductive barrier, and a second gate dielectric layer below the first conductive barrier, with the capping layer being in contact with the second gate dielectric layer.

DETAILED DESCRIPTION

As integrated circuits continue to scale downward in size, CMOS technology has focused on high-k dielectric materials having dielectric constants greater than that of silicon dioxide (SiO2) as possible gate dielectric layers. However, unwanted diffusion from subsequently formed layers, especially of oxygen (O2) atoms and hydroxide (OH−) ions, may impact the functioning and effectiveness of the high-k dielectric materials forming the gate dielectric layer. When O2or/and OH−diffuse into the gate dielectric layer the threshold voltage and the effective workfunction of the system may be affected, thereby decreasing device performance. This problem may be particularly noticeable in FET devices including gate structures with a length less than or equal to 20 nm. For example,FIG. 1is a cross-sectional view of a semiconductor structure10depicting a typical gate stack configuration after the replacement of a dummy gate (not shown) by a metal gate50. As may be observed inFIG. 1, a diffusion path between a capping layer60and a gate dielectric layer20may be established allowing the diffusion of O2and OH−(indicated by arrows) from the capping layer60to the gate dielectric layer20which in turn may negatively affect the device threshold voltage and workfunction performance. Accordingly, improving the formation of gate stacks may prevent the diffusion of O2and OH−to the gate dielectric layer hence enhancing device performance and increasing product yield and reliability.

A method of forming a semiconductor structure including a conductive barrier that may reduce the diffusion of O2and OH−to the gate dielectric layer is described in detail below by referring to the accompanying drawings inFIGS. 2-14, in accordance with an illustrative embodiment of the present disclosure. According to an exemplary embodiment, O2and OH−diffusion to the gate dielectric layer may be reduced by recessing the gate dielectric layer prior to the deposition of a workfunction metal. The workfunction metal (hereinafter “conductive barrier”) conductive barrier may be formed above the recessed gate dielectric layer acting as a barrier to block possible diffusion paths that may allow for the migration of O2and OH−to the gate dielectric layer. The conductive barrier may be conformally deposited above the recessed gate dielectric layer reducing the diffusion of O2and OH−from subsequently formed layers.

Referring now toFIG. 2, a semiconductor structure100may be provided or fabricated. The semiconductor structure100may include dummy gates110above a substrate140. Source-drain regions130may be adjacent to the substrate140on opposite sides of the dummy gates110, separated from the dummy gates110by gate spacers124. Hard masks112may cover a top surface of the dummy gates110.

At this point of the manufacturing process, the semiconductor structure100may include one or more field effect transistor (FET) devices. For example, the semiconductor structure100may include a short-gate device126and a long-gate device128. In an exemplary embodiment, the short gate device126may include a length varying between approximately 3 nm to approximately 20 nm, while the long-gate device128may include a length of approximately 50 nm to approximately 150 nm. In CMOS technology, gate structures of different lengths may be formed in a substrate in order to meet certain design requirements and to improve short-channel effect control. A constant threshold voltage (Vt) may be desired between short-gate devices and long-gate devices for optimal performance. However, owing to the length ratio between short-gate devices and long-gate devices, migration of O2and OH−to the high-k dielectric material forming the gate dielectric layer may have a stronger impact on short-gate devices causing a shift in the required Vt. In such cases, Vt variability between devices having different gate lengths may be considerable and may negatively affect the overall performance of the device.

In the depicted embodiment, the semiconductor structure100is a fin field effect transistor (finFET) so that the substrate140may be a semiconductor fin. In such embodiments, the substrate140may be a semiconductor-on-insulator (SOI) substrate, where a buried insulator layer (not shown) separates a base substrate (not shown) from a top semiconductor layer. The components of the semiconductor structure100, including the semiconductor fin, may then be formed in or adjacent to the top semiconductor layer. In other embodiments, the substrate140may be a bulk substrate which may be made from any of several known semiconductor materials such as, for example, silicon, germanium, silicon-germanium alloy, carbon-doped silicon, carbon-doped silicon-germanium alloy, and compound (e.g. III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide.

While embodiments depicted inFIGS. 2-14refer to a finFET device, a person of ordinary skill in the art will understand that the method described will apply equally to planar SOI, ETSOI and/or nanowire devices.

The dummy gates110may have a height ranging from approximately 10 nm to approximately 200 nm, preferably approximately 50 nm to approximately 100 nm. The dummy gates110may include a sacrificial dielectric layer (not shown) and a sacrificial gate electrode (not shown). The sacrificial dielectric layer may be made of any known dielectric material such as silicon oxide or silicon nitride. The sacrificial gate electrode may be made of, for example, an amorphous or polycrystalline silicon material. Other suitable materials for the sacrificial dielectric layer and the sacrificial gate electrode known in the art may also be used. The sacrificial dielectric layer and the sacrificial gate electrode may be formed by any suitable deposition technique known in the art, including atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), or liquid source misted chemical deposition (LSMCD).

The hard masks112may be formed above the dummy gates110to protect the dummy gates110during subsequent fabrication processes. The hard masks112may be made of an insulating material, such as, for example, silicon nitride, silicon oxide, silicon oxynitrides, or a combination thereof, may have a thickness ranging from approximately 5 nm to approximately 50 nm, and may be formed by any suitable deposition technique known in the art, including ALD, CVD, PVD, MBD, PLD, or LSMCD.

Gate spacers124may be formed on sidewalls of the dummy gates110. The gate spacers124may be made of any insulating material, such as silicon nitride, silicon oxide, silicon oxynitrides, or a combination thereof, and may have a thickness ranging from approximately 2 nm to approximately 100 nm, preferably approximately 2 nm to approximately 25 nm. The gate spacers124may be made of the same material as the hard masks112. In a preferred embodiment, the hard masks112and the gate spacers124may be made of silicon nitride. The gate spacers124may be formed by any method known in the art, including depositing a conformal silicon nitride layer (not shown) over the dummy gates110and removing unwanted material from the conformal silicon nitride layer using a ansiotropic etching process such as, for example, reactive ion etching (RIE) or plasma etching. Methods of forming spacers are well-known in the art and other methods are explicitly contemplated. Further, in various embodiments, the gate spacers124may include one or more layers. While the gate spacers124are herein described in the plural, the gate spacers124may consist of a single spacer surrounding the dummy gates110.

The source-drain regions130may be formed on the substrate140adjacent to the gate spacers124on opposite sides of the dummy gates110. While, the short-gate device126and the long-gate device128are depicted as adjacent and sharing a common gate, this may not be true of all embodiments. Numerous methods of forming source-drain regions are known in the art, any of which may be used to form the source-drain regions130. In some embodiments, the source-drain regions130may be formed by doping portions of the substrate140. In other embodiments, the source-drain regions130may be formed by growing epitaxial semiconductor regions adjacent to the substrate140. The epitaxial semiconductor regions may extend above and/or below the top surface of the substrate140as shown.

With continued reference toFIG. 2, an ILD layer132may deposited above the semiconductor structure100. The ILD layer132may fill the gaps between two adjacent devices, such as the short-gate device126and the long-gate device128, and other existing devices within the semiconductor structure100. The ILD layer132may include any suitable dielectric material, for example, silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics and may be formed using any suitable deposition techniques including ALD, CVD, plasma enhanced CVD, spin on deposition, or PVD. In some embodiments, various barriers or liners (not shown) may be formed below the ILD layer132. The ILD layer132may be thinned, for example by a chemical mechanical planarization/polish (CMP) technique, so that a top surface of the ILD layer132may be approximately coplanar with a top surface of the short-gate device126and the long-gate device128. After CMP, the ILD layer132may have a thickness ranging from approximately 10 nm to approximately 120 nm.

Referring now toFIG. 3, the hard masks112(FIG. 2) and the dummy gates110(FIG. 2) may be removed. Removal of the hard masks112(FIG. 2) and the dummy gates110(FIG. 2) may create first gate recesses302. The hard mask112(FIG. 2) and the dummy gates110(FIG. 2) may be removed by any suitable etching process known in the art capable of selectively removing the hard masks112and the dummy gates110without substantially removing material from the gate spacers124or the ILD layer132. In an exemplary embodiment, the dummy gates110(FIG. 2) may be removed, for example, by a reactive ion etching (RIE) process capable of selectively removing silicon to remove the sacrificial gate electrode (not shown) and a hydrofluoric acid-containing wet etch to remove the sacrificial gate dielectric layer (not shown).

Referring now toFIG. 4, gate dielectric layers420may be formed within the first gate recesses302(FIG. 3). The gate dielectric layers420may include an insulating material including, but not limited to: oxide, nitride, oxynitride or silicate including metal silicates and nitrided metal silicates. In some embodiments, the gate dielectric layers420may include an oxide such as, for example, SiO2, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, and mixtures thereof. In an exemplary embodiment, the gate dielectric layers420may include hafnium oxide (HfO2). The physical thickness of the gate dielectric layers420may vary, but typically the gate dielectric layers420may have a thickness ranging from approximately 0.5 nm to approximately 10 nm. More preferably the gate dielectric layers420may have a thickness ranging from approximately 0.5 nm to approximately 3 nm. The gate dielectric layers420may be formed by any suitable deposition technique known in the art, such as, for example, CVD, plasma-assisted CVD, ALD, evaporation, reactive sputtering, chemical solution deposition or other like deposition processes.

Referring now toFIG. 5, sacrificial layers520may be conformally deposited above the gate dielectric layers420. The sacrificial layers520may protect the gate dielectric layers420during etching of a protective layer630shown inFIG. 8. In embodiments where the annealing ambient is inert, formation of the sacrificial layer520may not be required. The sacrificial layer520may include any suitable workfunction metal such as Zr, W, Ta, Hf, Ti, Al, Ru, Pa, metal oxide, metal carbide, metal nitride, transition metal aluminides (e.g. Ti3Al, ZrAl), TaC, TiC, TaMgC), and any combination of those materials. In one embodiment the sacrificial layer520may include titanium nitride (TiN). The sacrificial layer520may have a thickness ranging from approximately 0.5 nm to approximately 100 nm. The sacrificial layer520may be deposited by any suitable deposition method known in the art such as CVD or ALD. Deposition of the sacrificial layer520may form second gate recesses304above the sacrificial layer520.

Referring now toFIG. 6, a protective layer630may be blanket deposited above the semiconductor structure100. The protective layer630may substantially fill the second gate recesses304(FIG. 5). The protective layer630may protect the long-gate device128(FIG. 2) during subsequent processing steps. Since changes in Vt have been primarily observed in short-gate devices, any device including a gate structure with a length greater than or equal to 50 nm may need to be covered by the protective layer630in order to continue with the processing steps. The protective layer630may include any suitable organic spin material. In one embodiment, the protective layer630may include an optical planarizing layer (OPL) or spin-on carbon layer. The protective layer630may be deposited by any suitable deposition method known in the art such as CVD or reflowable carbon layer. It should be noted that the material selected to form the protective layer630may be able to fill the second gate recesses304(FIG. 5) in the short-gate device126(FIG. 2). More specifically, the material forming the protective layer630may be capable of substantially fill any recess having a width of approximately 1 nm or less and a depth of approximately 120 nm.

Referring now toFIG. 7, a masking layer730may be formed above the protective layer630, covering an area corresponding to the long-gate device128(FIG. 2). The masking layer730may protect the long-gate device128(FIG. 2) during subsequent etching of the protective layer630described inFIG. 8. The steps involved in forming the masking layer730are typical and well known to those skilled in the art.

Referring now toFIG. 8, the protective layer630in the short-gate device126may be recessed. The protective layer630may be partially removed from the short-gate device126, so that a portion of the protective layer630may remain within the short-gate device126. The height of the remaining portion of the protective layer630within the short-gate device126may act as an etch-stop indicator during subsequent recessing of the gate dielectric layer420and the sacrificial layer520in the short-gate device126(FIG. 9). The remaining portion of the protective layer630within the short-gate device126may have a height ranging from approximately 1 nm to approximately 100 nm. A dry-etch process may be conducted to partially remove the protective layer630from the short-gate device126, although any other suitable etching technique may also be considered. In an exemplary embodiment where the protective layer630is spin-on carbon, the protective layer630may be removed by, for example, a dry etch chemistry including N2, H2and CHF3. After partially removing the protective layer630from the short-gate device126, the masking layer730(FIG. 7) may now be removed. The steps involved in removing the masking layer730(FIG. 7) are typical and well known to those skilled in the art.

Referring now toFIG. 9, the gate dielectric layer420and the sacrificial layer520in the short-gate device126may be recessed. The protective layer630may protect the long-gate device128during etching of the gate dielectric layer420and the sacrificial layer520in the short-gate device126to prevent recessing the gate dielectric layer420and the sacrificial layer520in the long-gate device128. The gate dielectric layer420and the sacrificial layer520may be recessed until they are approximately coplanar with the remaining portion of the protective layer630within the short-gate device126. The gate dielectric layer420and the sacrificial layer520may be recessed selectively to the protective layer630by means of any suitable etching technique known in the art. In an exemplary embodiment where the protective layer630is spin-on carbon, the gate dielectric layer420is HfO2and the sacrificial layer520is TiN, the gate dielectric layer420and the sacrificial layer520may be recessed by, for example, a dry etch chemistry including N2, H2and CHF3.

Referring now toFIG. 10, the protective layer630(FIG. 9) may be removed from the short-gate device126and the long-gate device128. In this embodiment, the sacrificial layer520may protect the gate dielectric layers420during removal of the protective layer630. The protective layer630(FIG. 9) may be removed by means of any suitable etching technique. In an exemplary embodiment where the protective layer630(FIG. 9) is spin-on carbon, the protective layer630may be removed by, for example, a dry etch chemistry including N2, H2and CHF3.

Referring now toFIG. 11, the sacrificial layers520(FIG. 10) may be removed from the short-gate device126and the long-gate device128to expose the gate dielectric layers420in the short-gate device126and the long-gate device128. Any suitable etching technique may be used to remove the sacrificial layers520(FIG. 10) from the short-gate and the long-gate devices126,128. In an exemplary embodiment where the sacrificial layers520are TiN and the gate dielectric layers420are HfO2, the sacrificial layers520may be removed by, for example, a wet etch mixture of NH4OH and H2O2.

Referring now toFIG. 12, conductive barriers840may be conformally deposited above the gate dielectric layers420in the short-gate device126and the long-gate device128. The conductive barrier840in the short-gate device126may substantially cover a top surface of the recessed gate dielectric layer420in the short-gate device126which may in turn eliminate any diffusion path between a subsequently formed capping layer960(FIG. 14) and the gate dielectric layer420in the short-gate device126. The conductive barriers840may include any suitable workfunction metal including, but not limited to, Zr, W, Ta, Hf, Ti, Al, Ru, Pa, metal oxide, metal carbide, metal nitride, transition metal aluminides (e.g. Ti3Al, ZrAl), TaC, TiC, TaMgC), and any combination of those materials. In one exemplary embodiment the conductive barriers840may include TiN and TiC. The conductive barriers840may have a thickness ranging from approximately 2 nm to approximately 100 nm. The conductive barriers840may be deposited by any suitable deposition technique known in the art, for example by ALD, CVD, PVD, MBD, PLD, or LSMCD. Deposition of the conductive barriers840may form third gate recesses306above the conductive barrier840.

Referring now toFIG. 13, metal gates950may be deposited above the conductive barriers840substantially filling the third gate recesses306within the short-gate device126and the long-gate device128. The metal gates950may include a metal with lower resistivity (higher conductivity) than the conductive barriers840. In one embodiment, the metal gates950may include tungsten (W) or aluminum (Al). A CMP process may be conducted to remove excessive materials from the semiconductor structure100so that a top surface of the metal gates950may be substantially coplanar with a top surface of the ILD layer132.

Referring now toFIG. 14, a capping layer960may be formed above the short-gate device126and the long-gate device128. The capping layer960may be made of substantially the same material as the gate spacers124(FIG. 12). In some embodiments, the capping layer960may include silicon nitride and may have a thickness ranging from approximately 15 nm to approximately 45 nm. The capping layer960may be formed by any deposition method known in the art, for example, by CVD or ALD. It should be noted that by recessing the gate dielectric layer420in the short-gate device126prior to forming the conductive barriers840, any possible O2and OH−diffusion path between the capping layer960and the gate dielectric layer420in the short-gate device126may be eliminated.

Therefore, recessing the gate dielectric layer420prior to forming the conductive barrier840, particularly in short-gate devices may substantially block diffusion paths that may allow the migration of O2and OH−from the capping layer960to the gate dielectric layer420. As a result, the threshold voltage and the workfunction of the system may not be affected by the diffusion of O2or/and OH−to the gate dielectric layer420in the short-gate device126enhancing device performance and increasing product yield and reliability, and the diffusion path from the capping layer960to the gate dielectric layer420may be cut without changing the traditional gate stack configuration which may improve process cost-effectiveness.