Power inverter system and method of starting same at high DC voltage

A power inverter system includes a plurality of power semiconductor switching devices. Each switching device includes a corresponding gate turn off resistance configured to increase during starting up periods of the inverter system such that the open circuit voltage of a corresponding power source providing power to the power inverter system does not exceed the switching device blocking voltage ratings during the corresponding switching turn-off periods. The starting up period is the time required to bring the corresponding power source voltage from its open circuit voltage level to a predetermined voltage which constitutes a safe operating condition for the plurality of power semiconductor switching devices.

BACKGROUND

This invention relates generally to the field of solar power generation and, more particularly, to methods and systems to allow for a high DC source voltage in a solar power inverter system.

Solar power generation is becoming a progressively larger source of energy throughout the world. Solar power generation systems typically include one or more photovoltaic arrays (PV arrays) having multiple interconnected solar cells that convert solar energy into DC power through the photovoltaic effect. In order to interface the output of the PV arrays to a utility grid, a power converter system is used to change the DC current and DC voltage output of the PV array into a 60/50 Hz AC current waveform that feeds power to the utility grid.

Various power converter systems exist for interfacing the DC output of a PV array (or other DC power source) with the AC grid. One implementation of a power converter system includes two stages, a boost converter stage and an inverter stage. The boost converter stage controls the flow of DC power from the PV array to a DC bus or DC link (hereinafter referred to as the “DC link”). The inverter stage converts the power supplied to the DC link into a suitable AC waveform that can be output to the AC grid.

Situations arise in which it is necessary to accommodate a PV array (or other DC power source) that has a high open-circuit voltage, such as an open-circuit voltage that is very close to the blocking voltage rating of the semiconductor devices employed in the power inverter system. E.g. array open circuit voltage is 1000 Vdc and the blocking voltage of the semiconductor devices is 1200 Vdc. Power inverter semiconductor devices, such as insulated gate bipolar transistors (IGBTs), are typically selected to accommodate the maximum power voltage of the PV array, not the open-circuit voltage of the PV array. The limiting factor in starting up at high voltage is the voltage overshoot at turn-off of the IGBTs.

In view of the foregoing, there is a need for a solar power inverter system and method of operation that allows for a high DC source voltage during start-up conditions. The inverter system should prevent the DC link voltage from reaching or exceeding the inverter system semiconductor device blocking voltage(s) during PV inverter start-up.

BRIEF DESCRIPTION

One embodiment of the present disclosure is directed to a power inverter system, comprising:

a DC to AC inverter comprising a plurality of power semiconductor switching devices;

a DC link coupling DC power to the inverter, the DC link comprising a DC link capacitor; and

a controller configured to increase a gate turn off resistance for each of the power semiconductor switching devices only during starting up periods of the inverter system such that the DC link voltage does not exceed the power semiconductor switching device blocking voltage rating during the corresponding switching turn-off periods, wherein the starting up period is the time required to bring a corresponding DC power source voltage from an open circuit voltage to a predetermined voltage which constitutes a safe operating condition for the plurality of power semiconductor switching devices.

Another embodiment of the present disclosure is directed to a method of operating a power inverter system, the method comprising:

providing an inverter comprising a plurality of power semiconductor switching devices, a DC link comprising a capacitor, and an inverter controller;

coupling a DC voltage source to the inverter via the DC link capacitor; and

subsequent to coupling the DC voltage source to the inverter, increasing a gate turn off resistance for each of the semiconductor power switching devices only during its corresponding starting up periods such that the DC link voltage does not exceed the respective power semiconductor switching device blocking voltage rating during the corresponding switching turn-off periods, wherein the starting up period is the time required to bring the DC source voltage from an open circuit voltage to a predetermined voltage which constitutes a safe operating condition for the plurality of power semiconductor switching devices.

According to yet another embodiment, a power inverter system comprises a plurality of power semiconductor switching devices, each switching device comprising a corresponding gate turn off resistance configured to increase during starting up periods of the inverter system such that the open circuit voltage of a corresponding power source providing power to the power inverter system does not exceed the switching device blocking voltage ratings during the corresponding switching turn-off periods, wherein the starting up period is the time required to bring the corresponding power source voltage from its open circuit voltage level to a predetermined voltage which constitutes a safe operating condition for the plurality of power semiconductor switching devices.

While the above-identified drawing figures set forth alternative embodiments, other embodiments of the present invention are also contemplated, as noted in the discussion. In all cases, this disclosure presents illustrated embodiments of the present invention by way of representation and not limitation. Numerous other modifications and embodiments can be devised by those skilled in the art which fall within the scope and spirit of the principles of this invention.

DETAILED DESCRIPTION

FIG. 1depicts a block diagram of a two stage PV power inverter system10used to convert DC power22generated by a PV array12into AC power28suitable for feeding an AC power grid20. The first stage of power inverter system10can include a DC to DC converter14, such as a boost converter, that provides DC power24to a DC link26. The DC link26couples the DC to DC converter14to an inverter16which operates as the second stage of the PV inverter system10. Inverter16converts the DC power24on the DC link26to AC power28suitable for being supplied to an AC power grid20. DC to DC converter14can be a part of or integral with inverter16or can be a separate stand alone structure from inverter16. In addition, more than one converter14can be coupled to the same inverter16through one or more DC links.

PV inverter system10includes a control system18that is configured to control both the DC to DC boost converter14and the DC to AC inverter16. For instance, control system18can be configured to regulate the output of the DC to DC converter14pursuant to a control method that adjusts the duty cycle (switching speed) of the switching devices (IGBTs or other power electronic devices) used in the DC to DC converter14. Control system18can also be configured to regulate the output of inverter16by varying the modulation commands provided to inverter16. The modulation commands control the pulse width modulation of the inverter16and can be used to vary the real and reactive output power of the inverter16. Control system18can be independent from DC to DC boost converter14and DC to AC inverter16or may be integrated into one or both of the respective system stages14,16.

When PV inverter system10is operating in steady state conditions, control system18can regulate the DC link voltage24of the DC link26(and, correspondingly, the PV array source voltage of the PV array12) by adjusting the AC output of inverter16. For instance, control system18can regulate the DC link voltage24of the DC link26by controlling the AC current output of inverter16. In steady state conditions, the inverter16is typically controlled to provide real power flow (i.e., the real part of the vector product of the inverter output AC voltage and the inverter output AC current) to the AC grid20that is equal to the power supplied to the DC link26by DC to DC converter14. Varying the output AC current of the inverter16will result in a change to the output AC voltage of the inverter16, based on the impedance of one or more output transformers and the utility grid20. Adjusting the output AC voltage of the inverter16will correspondingly induce a change in the DC link voltage24of the DC link26.

In situations in which it is necessary to accommodate a PV array12(or other DC power source) having a high open-circuit voltage, it is desirable to maintain the DC link voltage24less than the open-circuit voltage of the PV array12. By maintaining the DC link voltage24less than the open-circuit voltage of the PV array12, the PV array source voltage provided by the PV array12to the PV inverter system10can also be maintained less than the open-circuit voltage of the PV array12, such as at the maximum power voltage of the PV array12. In steady-state conditions, the control system18can regulate the DC link voltage24to be less than the open-circuit voltage of the PV array12by controlling the output of inverter16. Starting up a PV inverter system when the open circuit voltage of the connected PV array is very close to the blocking voltage rating of the PV inverter semiconductor power devices, e.g. array open circuit voltage is 1000 Vdc and the blocking voltage of the semiconductor devices is 1200 Vdc, can however be problematic due to DC link voltage overshoot.

FIG. 2illustrates the PV inverter system10depicted inFIG. 1modified with power semiconductor device38gate current limiting resistors40. A limiting factor when starting up PV inverter system10is the DC link voltage overshoot at turn-off of the semiconductor power devices38that may comprise, for example, insulated gate bipolar transistors (IGBT)s. The DC link26voltage overshoot is generally represented by Vdc_overshoot=L*di/dt. The DC link voltage overshoot therefore is actually not dependent on the current magnitude, but on the current growth rate and the inductance in the commutation path. This voltage overshoot is only an issue at turning off the IGBT devices38. Turning on the IGBT devices38does not present voltage overshoot issues.

The present inventors alone recognized that operating a PV inverter system, such as PV inverter system10depicted inFIG. 1, when the open circuit voltage of the connected PV array12is very close to the inverter semiconductor power device38blocking voltage rating, e.g. array open circuit voltage is 1000 Vdc and the semiconductor power device38blocking voltage rating is 1200 Vdc, is possible if the semiconductor power device currents are turned-off at a very low di/dt rate via large gate resistors40such as depicted inFIG. 2. The present inventors further recognized that operating the semiconductor power devices38in combination with large gate resistance40advantageously provides the desired low di/dt rate, but at an undesirable level of power device38operating efficiency; and that the foregoing undesirable losses can be reduced through a reduction of current and switching frequency during this operating mode that lasts for only a very short period of time for a PV array12.

According to one embodiment, the large value gate resistor(s)40are switched back to a smaller nominal resistance value when the PV array voltage reaches its maximum power point (MPP) voltage, which is about 20% lower than the open circuit voltage of the PV array12. According to another embodiment, the gate resistor(s)40comprise variable resistance devices that linearly or non-linearly reduce the value of semiconductor power device gate resistance as the PV array voltage continues to drop in value approaching MPP voltage.FIG. 5, for example, illustrates a voltage clamping gate control architecture100that operates to reduce the switching device gate resistances40in a stepwise fashion during start-up conditions as the gate voltage reduces from an initial open circuit voltage102to the MPP voltage104according to one embodiment.

AlthoughFIG. 2illustrates a three-phase AC output for inverter16, those of ordinary skill in the art, using the disclosures provided herein, should readily understand that inverter16can similarly provide a single-phase AC output or other multi-phase AC output as desired without deviating from the scope of the present invention. Inverter16uses one or more inverter bridge circuits that include power devices38, such as IGBTs and diodes that are used to convert the DC power on DC link26into a suitable AC waveform. For instance, in certain embodiments, inverter16uses pulse-width-modulation (PWM) to synthesize an output AC voltage at the AC grid frequency. The output of inverter16can be controlled by providing gate timing commands to the IGBTs38of the inverter bridge circuits of inverter16according to well known PWM control techniques. The output AC current flowing from inverter16has components at the PWM chopping frequency and the grid frequency.

PV inverter system10may also include a PV array voltage sensor42. PV array voltage sensor42monitors the voltage of the PV array12and provides feedback signals to control system18. The control system18can make adjustments to the semiconductor power device38gate resistance40or other operating parameters of PV inverter system10, e.g. semiconductor power device38switching frequency, based on the PV array voltage detected by PV array voltage sensor42.

FIG. 3is a simplified block diagram illustrating a PV inverter system50according to another embodiment. PV inverter system50is similar to PV inverter system10, except PV inverter system50does not employ a DC-DC converter such as boost converter14described herein with reference toFIGS. 1 and 2. PV inverter system50can be seen to include a DC to AC inverter control unit19. According to one embodiment, inverter control unit19is configured to control the switching frequency of the inverter semiconductor power devices38and to also control the gate resistance value for each semiconductor power device38. According to one aspect, the switching frequency is reduced below its normal operating value and the gate resistance is increased above its normal operating value when the PV array12open circuit voltage is very close to the semiconductor power device blocking voltage rating, e.g. array open circuit voltage is 1000 Vdc and the blocking voltage of the semiconductor power devices are 1200 Vdc. According to one embodiment, when the voltage generated by the PV array12reaches the MPP voltage, which is about 20% lower than the open circuit voltage of the PV array12, the gate turn off resistor40employed during semiconductor power device38turn-off is switched back to a smaller value via control unit19. According to another embodiment, one or more gate resistors40comprise a variable resistance device that reduces in value in response to signals received from control unit19as the PV array voltage output reduces in value.

FIG. 4is a flow diagram illustrating a starting procedure60for the power converter systems1,50according to one embodiment. Starting procedure60advantageously avoids any requirements for additional hardware necessary to pull down the voltage of the PV array12during start-up conditions. Starting procedure60further advantageously negates the necessity for using semiconductor power devices with higher rated blocking voltages, e.g. 1700V IGBTs, that reduce the efficiency and increase the system cost.

With continued reference toFIG. 4, starting procedure60commences by connecting the DC voltage source, e.g. PV array12, to the PV inverter system10,50as represented in step62. The DC link voltage is preferably less than the open-circuit voltage Voc of PV array12. According to one embodiment, the controller18,19can operate the DC link at a first DC link voltage by controlling the AC output of inverter16. PV array voltage sensor(s)42can be used to determine if PV array12is operating at an open-circuit voltage or other voltage.

Subsequent to coupling the PV array12to PV inverter system10,50, controller18,19functions to quickly increase the gate turn off resistance40of each semiconductor power device, e.g. IGBTs, during starting up period, to a value that is larger than its nominal operating value if the monitored PV array voltage is very close to the semiconductor power device blocking voltage rating, as represented in step64. According to one embodiment, the semiconductor power device switching frequency during the respective starting up period is also reduced to a value that is lower than its nominal operating value if the monitored PV array voltage is very close to the semiconductor power device blocking voltage rating.

Upon reaching the PV array MPP tracking voltage which is about 20% lower than the open circuit voltage of the PV array, controller18,19operates to switch the corresponding turn off gate resistance(s)40back to a smaller nominal operating value according to one embodiment, as represented in step66. According to one embodiment, controller18,19tracks the PV array voltage to linearly or non-linearly reduce the corresponding gate resistance(s)40as the PV array voltage continues to reduce in value approaching MPP voltage.

2. Those skilled in the art will readily appreciate that semiconductor power switching device gate resistance(s) and switching frequencies will depend upon the particular application, system architecture, and semiconductor power switching device(s) employed in the power inverter system. The switching characteristics and gate resistance can be accomplished with or without the use of algorithmic software, depending upon the particular application. Algorithmic software, if employed, would reside within the controller18,19according to one embodiment. According to one embodiment, the controller18,19is configured to change the gate turn-off resistance for each power semiconductor switching device38at zero vector instance of the SVM (Space vector modulator). Zero vector as used herein is defined as the switching configuration of the power semiconductor devices38in a DC to AC inverter16that provides zero voltage at the inverter output. (e.g. a positive zero vector in a three-phase two-level DC/AC inverter occurs when all upper IGBTs are turned on and lower IGBTs are turned off. A negative zero vector will happen when all upper IGBTs are turned off and lower IGBTs are turned on). According to another embodiment, the controller18,19is further configured to increase the gate turn off resistance during a zero/low voltage ride through (ZVRT/LVRT) event of the DC to AC inverter16.