NEXFET NGEN3.2 MV DUAL SHIELD OXIDE DAMAGE SOLUTION

A method of fabricating a semiconductor device includes etching a first trench and a second trench in an epitaxial layer over a semiconductor and forming a dielectric liner within the trenches. A photoresist layer is formed within the trenches and over the epitaxial layer and given a post-exposure bake at a first temperature. The photoresist layer is then given an adhesion-promoting bake at a greater second temperature; The photoresist layer is then removed from a top portion the trenches, thereby exposing a top portion of the dielectric liner and leaving a remaining portion of the photoresist in a bottom portion of the trenches. The exposed dielectric liner is etched, thereby leaving a remaining portion of the dielectric liner in the top portion of the trenches. The remaining portion of the photoresist is removed and the trenches are filled with a polysilicon layer.

FIELD OF THE DISCLOSURE

Disclosed implementations relate generally to the field of semiconductor devices, and more particularly, but not exclusively, to improved formation of polysilicon shield arrays.

SUMMARY

Dual shield field plates refer to field plates in which the polysilicon in the field plates has different widths in two separate portions of the field plate, as differentiated from single shield field plates in which the polysilicon has a same width in all portions of the field plate. In order to prevent certain defects that occur during the fabrication of dual shield field plates that are intended to operate at higher voltages, e.g. 75 V or greater, depicted implementations increase the width of the outermost trench or trenches of the trenches in which the dual shield field plates are fabricated. While such implementations may be expected to improve the defect rate of such integrated circuits employing the dual shield field plates and improve device breakdown voltage performance and reliability, no particular result is a requirement of unless explicitly recited in a particular claim.

In one aspect, an implementation of a method of fabricating an integrated circuit semiconductor device is disclosed. The method includes etching a group of trenches in a semiconductor surface layer of a substrate, the group of trenches including an outermost trench having a first width and remaining trenches of the group of trenches having a second width that is less than the first width, the outermost trench formed at an edge of the group of trenches; forming a dielectric liner in the group of trenches; etching the dielectric liner in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner while maintaining a full thickness of the dielectric liner in a lower portion of the group of trenches; and filling the group of trenches with a polysilicon layer.

In another aspect, an implementation of a method of fabricating a semiconductor device is disclosed. The method includes etching a plurality of trenches in a semiconductor surface layer of a substrate and forming a dielectric liner within the trenches. A photoresist layer is formed over a top surface of the semiconductor surface layer and filling the trenches. A first post-exposure bake of the photoresist layer is performed at a first temperature. A second post-exposure bake of the photoresist layer is performed at a greater second temperature. The photoresist layer is partially removing from the trenches, and the dielectric liner in an upper portion of the plurality of trenches is etched to remove a partial thickness of the dielectric liner while maintaining a full thickness of the dielectric liner in a lower portion of the plurality of trenches. The photoresist is then removed from the trenches and the plurality of trenches which are then filled with a polysilicon layer.

DETAILED DESCRIPTION

Specific implementations will now be described in detail with reference to the accompanying figures. In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding. However, it will be apparent to one of ordinary skill in the art that the implementations may be practiced without one or more specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

U.S. Pat. No. 10,720,499 (hereinafter the '499 patent), which issued Jul. 21, 2020 in the name of Ya Ping Chen et al., and which is hereby incorporated by reference in its entirety, depicts the fabrication of polysilicon field plates in trenches etched into the substrate of a semiconductor wafer. One implementation of the '499 patent describes trenches in which a dielectric liner is formed in the trenches, e.g., by thermally growing a first oxide layer, followed by deposition of a second oxide layer using, e.g., sub-atmospheric chemical vapor deposition (SACVD). After filling the trenches with a photoresist, the photoresist can be patterned and developed such that the trenches that will form dual shield field plates have the photoresist removed from an upper portion of the trenches, while a lower portion of the trenches are still covered with the photoresist. Other portions of the substrate, which may include additional trenches, also remain covered with the photoresist. The exposed trenches are wet etched to remove the second oxide layer in the upper portion of the trenches, while the second oxide layer in the lower portion of the trenches is protected by the remaining photoresist. The photoresist can then be removed from the substrate, leaving trenches that have two different widths of dielectric liner, depending on the depth within the trench. The resulting trenches are filled with polysilicon to provide the desired configuration for the field plates.

In one implementation in the '499 patent, the dual shield field plates depicted were designed to operate at about 45 V and were etched to a depth of about 3 μm. When the methods described in the '499 patent were extended to dual shield field plates designed to operate at about 100 V, the depth of the trenches was increased to about 6 μm.

FIG.4Adepicts a cross-section400A through a group of trenches402and trenches404after completion of the wet etch described above in trenches having a depth of about 6 μm. The trenches402are being fabricated to serve as dual shield field plates, while the trenches404are not intended as dual shield field plates and remain covered with photoresist406. Etching of the trench402A, the trench402B, and the trench402C has proceeded as desired, while an issue has been identified in the trench402D. The photoresist406in the trench402D has pulled away from one wall of the trench402D, allowing the etchant to attack the exposed wall.

FIG.4Bdepicts a cross-section400B through a similar group of the trenches402and the trenches404after the photoresist406has been removed from the substrate and polysilicon408has been formed in each of the trenches402and the trenches404. The trench402E, the trench402F, and the trench402G all provide a dual shield field plate that can operate as desired, but the trench402H does not provide the desired shape and includes a defect that may affect operation of the chip. The problem of the photoresist406pulling away from one wall of the trench402D inFIG.4Aand causing the resulting misshapen dual shield field plate in the trench402H ofFIG.4Bwas only identified in the outermost trench402.

FIG.5Adepicts the stresses in a cross-section500A of a substrate after the wet etch to remove the second oxide layer from an upper portion of trenches502, which are intended as dual shield field plates; additional trenches502(not specifically shown) are located to the left of the depicted trenches502. As a trench502A and a trench502B are etched, the localized stress around these trenches remains evenly balanced due to the similar etching occurring on either side of the trench502A and the trench502B. However, as a trench502C is etched, the localized stress in the trench502C increases because the photoresist and the silicon oxide are being removed from the trench502B, but not from the trench504A. This imbalance in the forces acting on the trench502C appears to be the cause of photoresist506pulling away from one wall of the trench502C, which results in an incorrectly formed dual shield field plate.

FIG.5Bdepicts a graph500B showing the changes in the wafer radius of curvature across several elements of fabrication. The radius of curvature can be an indicator of stress, which is increased by the high density of the trench pattern in this application. It is known that the greater the radius of curvature, the less stress is present. The three lines are the results for three different wafers, demonstrating the differences that can occur between wafers. The left side of the graph500B begins after the formation of the second silicon oxide layer, which in this implementation was deposited by SACVD. At this point, the wafer top surface has a compressive stress and radius of curvature around26arbitrary units.

The second point was taken after formation of the photoresist in the trenches and a soft bake to remove liquid from the photoresist. The soft bake generates tensile stress on the front side of the wafer, increasing the wafer radius of curvature to about 28 arbitrary units. The third point was determined after exposure of the pattern to light. The exposure changes the chemical characteristics of the photoresist in the upper portions of the exposed trenches, e.g., the trenches for dual shield field plates. This decreases the tensile stress, so the wafer becomes more compressive compared to the second point.

A fourth point in graph500B is taken after a post-exposure bake and development of the photoresist, followed by a hard bake, which can be performed, e.g., at 110° C. The removal of photoresist from the substrate surface and from upper portions of some, but not all, trenches can continue to release tensile stress and provide greater compressive stress, and are believed to cause the identified photoresist pullback.

FIG.6AandFIG.6Bdepict a cross-section600A and a cross-section600B respectively of a group of trenches having similar depths of about 3.5 μm. The cross-sections are shown after removal of the photoresist and partial removal of the upper trench oxide using a wet etch and compares the results of leaving different levels of photoresist in the trenches.FIG.6Adepicts a trench602A, a trench602B, and a trench602C, which have been wet etched to a depth of about 2400 nm, while a trench604A has not been etched. The trench602A and the trench602B have been successfully etched, but in the trench602C the photoresist606is again shown to have pulled away from one sidewall. In contrast,FIG.6Bdepicts a trench602D, a trench602E, and a trench602F that have been wet etched to a lesser depth of about 1030 nm, leaving a greater amount of photoresist in the trenches; a trench604B has not been etched. The imbalance of stress at the trench602F has not reached a point that has triggered photoresist pull-back. Thus, the depth of the photoresist remaining in the trench can affect the photoresist pullback during the wet etch.

FIGS.7A and7Bdepict respective cross-sections of a substrate after the wet etch. Each cross-section shows a group of trenches having similar depths of about 6 μm but having different thicknesses of the second silicon oxide layer and thus different widths in the lower portion of the trenches. A cross-section700A includes a trench702A, a trench702B, and a trench702C, each of which has been etched; a trench704A has not been etched. Each of the trench702A, the trench702B, and the trench702C has resulted in a photoresist cross-section width of about 280 nm. In the cross-section700A, the trench702A and the trench702B were etched normally, although the trench702C shows photoresist pull-back from the wall and a distinct defect in the resulting trench.

A cross-section700B includes a trench702D, a trench702E, and a trench702F, each of which has been etched; a trench704B has not been etched. Each of the trench702D, the trench702E, and the trench702F has resulted in a photoresist cross-section width of about 640 nm. In a cross-section700B, all of the trenches702have been successfully etched without defects, demonstrating that the width of photoresist in the lower portion of the trench can also affect the photoresist pullback during the wet etch.

U.S. Pat. No. 11,417,736, incorporated herein by reference in its entirety, describes solutions that include providing a wider penultimate trench in a trench array to reduce or eliminate pull-back of the photoresist in the penultimate trench. The Applicant has further determined that in addition, or alternatively, photoresist pull-back may be reduced or eliminated by providing an additional photoresist bake after a baseline post-exposure bake (PEB). The additional bake may increase adhesion of the photoresist to the trench sidewalls and/or reduce accumulated stress in the photoresist remaining on the substrate surface. Implementations of the present disclosure may be used without providing a wider penultimate trench in the array, thereby providing uniform trench size which may be advantageous or desirable in some cases

FIG.1AthroughFIG.1Jdepict respective cross-sections of a semiconductor device100at various points in the fabrication of power metal-oxide-semiconductor field effect transistors (MOSFETs) that includes field plates. Field plates often function to reduce an electric field in an adjacent semiconductor region. A field plate may be for example a semiconductor region with an opposite conductivity type from the adjacent semiconductor region. The process described herein depicts N-type metal oxide semiconductor (NMOS) FETs, although it should be clear to one having ordinary skill in the art to use the information in these descriptions to also form P-type metal oxide semiconductor (PMOS) transistors. This can be accomplished by substituting n-doped regions for p-doping and vice versa so that examples can also include PMOS transistors.

FIG.1Adepicts a cross-section of a semiconductor device100A that is in fabrication in and over a substrate101. The substrate101includes a semiconductor surface layer103, which extends to a top surface103A, and an N+ region105below the semiconductor surface layer103. In some examples the semiconductor surface layer103is a doped epitaxial layer, e.g. n-doped. A group of trenches102, which includes a field plate trench102A, a field plate trench102B, a field plate trench102C, and a penultimate field plate trench102D, have been formed in semiconductor surface layer103. The penultimate field plate trench102D is an outermost one of the trenches102. While only one trench104is shown to the right of the trenches102, any number of trenches may be present to the right or left of the trenches102. The illustrated trench104is the leftmost of the one or more trenches formed to the right of the trenches102, and may be referred to as a termination trench104. The field plate trench102A, the field plate trench102B, the field plate trench102C, and the field plate trench102D will be used to form dual shield field plates. The termination trench104, which in one implementation is optional, is a feature designed for the outer edge of the device (e.g., on a die) to ensure that when voltage is applied to the device the device does not experience a premature voltage breakdown occurring at its outer edge. In one implementation, the termination trench104is a single shield field plate.

Additional field plate trenches102are generally formed in the semiconductor surface layer103, e.g., to the left of the field plate trenches102shown in the semiconductor device100A; the field plate trench102D is the outermost of the field plate trenches and is formed on an edge of the field plate trenches102. In one implementation, several hundred field plate trenches102are provided in a semiconductor surface layer103. In the semiconductor device100A, once the field plates are completed, a power MOSFET may be formed between the current field plate trench102A and the field plate trench102B; a MOSFET may also be formed between the field plate trench102C and the field plate trench102D.

A field oxide106has been formed between the field plate trench102B and the field plate trench102C, between the field plate trench102D and the termination trench104, and in other regions of the semiconductor surface layer103. The field oxide106may be formed by a shallow trench isolation (STI) process, as shown inFIG.1A, or by a local oxidation of silicon (LOCOS) process. Several N-type vertical drift regions108have also been formed in the semiconductor surface layer103, e.g., between the field plate trench102A and the field plate trench102B and also between the field plate trench102C and the field plate trench102D.

In the illustrated example all the trenches102have a same width112, in contrast to some examples provided in the '736 patent. In some other examples of the present disclosure the trenches102may have different widths such as described in the '736 patent. For example the penultimate trench102D may be wider than the trenches102A,102B and102C.

In one implementation of the semiconductor device100A, which may be designed to operate at 100 V, the field plate trenches102and the termination trench104may be 6 μm to 7 μm deep; the field plate trenches102and the termination trench104may be 1.2 μm to 1.4 μm wide. The vertical drift region108may be 2.0 μm to 2.4 μm wide, and have an average doping density of about 4e16 atoms/cm3to about 6e16 atoms/cm3.

FIG.1Bdepicts a cross-section of semiconductor device100B after the formation of a dielectric liner116on the top surface103A of the semiconductor surface layer103and on the sidewalls and bottom of the field plate trenches102and the termination trench104. In one implementation, the dielectric liner116includes a first dielectric layer118, e.g., a thermally grown oxide layer, and a second dielectric layer120, e.g., a deposited silicon dioxide layer, formed on the first dielectric layer118. In one implementation, the first dielectric layer118may be 50 nm to 300 nm thick. In one implementation, the first dielectric layer118may be 80 nm to 150 nm thick. In one implementation, the second dielectric layer120may be 80 nm to 500 nm thick, such as being 80 nm to 200 nm thick, or 150 nm to 200 nm thick. The second dielectric layer120may be formed by an SACVD process using dichlorosilane and oxygen. Alternately, the second dielectric layer120may be formed by a plasma enhanced chemical vapor deposition (PECVD) process using tetraethyl orthosilicate, also known as tetraethoxysilane (TEOS). The second dielectric layer120may be subsequently densified in an anneal step.

FIG.1Cdepicts a cross-section of a semiconductor device100C after formation of a photoresist layer122. The photoresist layer122generally includes a liquid and is used to coat the top surface103A and to fill the field plate trenches102and the termination trench104. Once the photoresist layer122has been applied to the substrate101, a soft bake is performed to remove solvent from the photoresist layer122. The photoresist layer122can be a positive photoresist, which as is known in the art is degraded by light so that a developer can dissolve away the regions that were exposed to light, leaving behind a coating where the mask was placed. The thickness of the photoresist layer122applied may be a function of the trench depth (and width or area) to ensure complete trench filling. After developing, the photoresist layer122generally remains in 20% to 80% of the depth of the field plate trenches102, but is not removed in the termination trench104. The target may be to leave 50%+/−10% of the depth of photoresist layer122in the field plate trenches102.

FIG.1Ddepicts a cross-section of a semiconductor device100D after exposing the photoresist layer122with a mask and then partially removing the photoresist layer122so that the photoresist layer122is removed in an upper portion121of the field plate trenches102, while not removing the photoresist layer122over the termination trench104. A PEB161is performed, which may be a bake for a time and temperature consistent with process guidelines provided by the photoresist manufacturer, e.g. 100° C.-110° C. for a few minutes. After the PEB The edge of the developed photoresist122has a relatively vertical sidewall, which may include a concave profile as illustrated.

FIG.1Eillustrates the semiconductor device100C after an additional, adhesion-promoting, bake162. The additional bake may result in the sidewall profile of the photoresist122shrinking and adopting a convex profile, as illustrated. The adhesion-promoting bake123may include heating the device100C to a temperature in a range from about 125° C. to about 150° C. for a duration in a range from about 180 s to about 220 s, e.g. about 140° C. for about 200 s. Conditions consistent with these values are expected to result in increased adhesion between the photoresist122and the second dielectric layer120, e.g. by promoting chemical bonding or van der Waals attraction between the photoresist122and the second dielectric layer120without significant chemical degradation of the photoresist122.

Referring toFIG.1F, exposed portions of the second dielectric layer120have been etched to remove the second dielectric layer120from the upper portion121of the field plate trenches102. The etchant may be selected to stop on the first dielectric layer118. In the lower portion123of the field plate trenches102, the second dielectric layer120and the first dielectric layer118are both protected during this etch by the photoresist layer122, as is the termination trench104.

The etching of the second dielectric layer120in the upper portion121of the field plate trenches102can comprise a wet etch. The wet etch can comprise using a buffered hydrofluoric acid (HF) solution. An example buffered HF solution is 10 parts of 40 percent ammonium fluoride in deionized water and 1 part of 49 percent HF in deionized water. This example buffered HF etch exhibits an etch rate for densified SACVD silicon dioxide that is more than twice an etch rate for thermal oxide.

The etching of the second dielectric layer120in the upper portion121of the field plate trenches102can also comprise a dry etch. If dry etching is used, the dielectric liner116can be a dielectric stack (not specifically shown) comprising a bottom layer of silicon oxide, a layer of silicon nitride on the bottom layer, and a top layer of silicon oxide. An example dry etch for this purpose is a high selectivity carbon/fluorine-based plasma etch using an RF power of 1200 W with 12 standard cubic centimeters per minute (sccm) C4F8, 5 sccm 02, 100 sccm Ar, 95 sccm CO, using a 200 second etch time. The etch time used generally depends on the target depth. This plasma etch can provide an etch rate of oxide/silicon nitride of greater than 10 and an etch rate of silicon oxide/silicon of greater than 10. This plasma etch can stop on silicon nitride and avoid silicon damage.

FIG.1Gdepicts a cross-section of a semiconductor device100D after the photoresist layer122is stripped. Each of the field plate trench102A, the field plate trench102B, the field plate trench102C, and the field plate trench102D now has only the first dielectric layer118in the upper portion121of the trench and both the first dielectric layer118and the second dielectric layer120in the lower portion123of the trench. The termination trench104includes both the first dielectric layer118and the second dielectric layer120throughout the depth of the trench.

FIG.1Hdepicts a cross-section of a semiconductor device100F after forming a polysilicon layer124to fill the field plate trenches102and the termination trench104. Formation of the polysilicon layer124is followed by etching to remove excess polysilicon. Chemical mechanical polishing (CMP) may be used for the polysilicon removal. The polysilicon layer124may be for example, 500 nm to 700 nm thick over the top surface103A as formed. The polysilicon layer124may be doped in-situ, for example with phosphorus, to have an average doping density of about 1e18 atoms/cm3to about 5e18 atoms/cm3. Alternatively, the polysilicon layer124may be doped by ion implanting dopants, for example phosphorus, at a dose of about 1e14 atoms/cm2to about 1e16 atoms/cm2, and subsequently annealed between about 900° C. and about 1000° C. for 10 to 60 minutes.

As seen in semiconductor device100F, removal of the polysilicon layer124overburden has produced dual shield field plates125A . . .125D in the field plate trenches102and a single shield field plate127in the termination trench104. In some contexts the dual shield field plate125D may be referred to as an outermost dual shield field plate125, and the single shield field plate127may be referred to as a terminating field plate127. As seen, the outermost dual shield field plate125D is located between the terminating field plate127and remaining ones of the dual shield field plates125, e.g. the dual shield field plates125A . . .125C.

In the described implementations, respective power MOSFETs are formed next between the dual shield field plate125A and the dual shield field plate125B, and also between the dual shield field plate125C and the dual shield field plate125D. In one implementation, the power MOSFETs are vertical trench gate MOSFETs. In one implementation, the power MOSFETs are planar gate MOSFETs. Examples of both vertical trench gate MOSFETs with the described dual shield field plates125and planar gate MOSFETs with the described dual shield field plates125are shown respectively inFIG.1GandFIG.1H. Additional details of the formation of the vertical trench gate MOSFET may be found in the '499 patent.

FIG.1Idepicts a cross-section of a semiconductor device100G in which vertical trench gate MOSFETs126have been formed between respective pairs of the dual shield field plates125. Each vertical trench gate MOSFET126includes the N+ region105, which forms a drain contact region and a respective N-type vertical drift region108. A gate electrode or gate128is disposed on a gate dielectric layer130that contacts a p-body region132. The gate128is laterally separated from each adjacent field plate125by the semiconductor material of the substrate101. In one implementation, the gate128can also be formed within the field plate trenches102above the field plate125and separated by the gate dielectric130.

An n-type source region134, which can be doped N+, is disposed abutting the gate dielectric layer130and the p-body region132abuts the vertical drift region108. A p-type body contact region136extends from the top surface103A of the semiconductor surface layer103to the p-body region132. A source electrode140that generally comprises a metal layer is conductively coupled to the source region134, to the p-body contact region136, to the polysilicon layer124in the dual shield field plates125, and also to the polysilicon layer124in the single shield field plate127.

The source electrode140may be directly and conductively coupled to a top surface of the polysilicon layer124as depicted inFIG.1G. The gate128is conductively isolated from the source electrode140, for example by a dielectric gate cap layer138as shown. The vertical trench gate MOSFET126may be laterally isolated from other circuitry in the semiconductor device100, for example by the field oxide106.

FIG.1Jdepicts a cross-section of a semiconductor device100H in which planar gate MOSFETs156have been formed between respective pairs of the dual shield field plates125, e.g., a planar gate MOSFET156A has been formed between the dual shield field plate125A and the dual shield field plate125B and a planar gate MOSFET156B has been formed between the dual shield field plate125C and the dual shield field plate125D. Each of the planar gate MOSFETs156includes a gate176(e.g., a polysilicon gate) with sidewall spacers188, a gate dielectric175, a source180, a p-body174and p+ body contacts182. The source electrode158may again be directly and conductively coupled to a top surface of the polysilicon layer124. The dual shield field plates125and the termination field plate127are the same as shown inFIG.1Gabove.

FIG.2depicts a method200of fabricating a semiconductor device according to an implementation of the disclosure. The method200includes etching205a group of trenches in a semiconductor surface layer of a substrate, the group of trenches including an outermost trench. A dielectric liner is then formed210in the group of trenches. A photoresist layer215is formed within the trenches and over the semiconductor surface layer. A post exposure bake is performed220at a first temperature, and an adhesion-promoting bake is performed220at a second greater temperature. The photoresist layer is removed225from an upper portion of the trenches, and a portion of the dielectric liner is removed230from the exposed portion of the trenches. The dielectric liner is etched230in the exposed portion of the trenches to remove a partial thickness of the dielectric liner while maintaining a full thickness of the dielectric liner in a lower portion of the group of trenches. The group of trenches are then filled235with a polysilicon layer.

FIG.2AthroughFIG.2Ceach provide either further details that may be included in the method200or else additional elements that may be part of the method200.FIG.2Adepicts additional details of the method200in which forming the dielectric liner includes thermally growing240a first silicon dioxide layer and forming a second silicon dioxide layer on the first silicon dioxide layer and further notes that after etching the dielectric liner in the upper portion of the group of trenches, the dielectric liner in the lower portion of the group of trenches is245at least 50% thicker than the dielectric liner in the upper portion of the group of trenches.

FIG.2Bdepicts additional elements that may be included in the method200, i.e., etching250a termination trench in the semiconductor surface layer, then forming255the dielectric liner in the termination trench, protecting260the dielectric liner in the termination trench during the etching of the dielectric liner, and filling265the termination trench with the polysilicon layer.

FIG.2Cdepicts the additional element of forming270a power MOSFET between a first trench and a second trench of the group of trenches. The power MOSFET includes a drain having a drain contact, a vertical drift region in the semiconductor surface layer over the drain, and each of a gate, a body, and a source over the vertical drift region.

FIG.3depicts a method300of fabricating a semiconductor device according to an implementation of the disclosure. The method300includes etching305a group of field plate trenches in a semiconductor surface layer of a substrate. The outermost field plate trench is formed on an edge of the group of field plate trenches. A dielectric liner is formed310in the group of field plate trenches and photoresist is formed315over the substrate including over the dielectric liner in the group of field plate trenches and exposed. A post-exposure bake is performed320at a first bake temperature, and an adhesion-promoting bake is performed at a greater second temperature. The photoresist in the group of field plate trenches is developed325to remove the photoresist in an upper portion of the group of field plate trenches. The photoresist remains in a lower portion of the group of field plate trenches. The dielectric liner in the upper portion of the group of field plate trenches is etched330while the dielectric liner in the lower portion of the group of field plate trenches is protected by the photoresist. The photoresist is then removed335from the lower portion of the group of field plate trenches and the group of field plate trenches are filled340with a polysilicon layer.

FIG.3Afurther defines that forming the dielectric liner includes345thermally growing a first silicon dioxide layer and forming a second silicon dioxide layer on the first silicon dioxide layer using SACVD. Additionally, after etching the dielectric liner, the dielectric liner in the lower portion of the group of field plate trenches is350at least 50% thicker than the dielectric liner in the upper portion of the group of field plate trenches.

FIG.3Bdefines that etching the group of field plate trenches includes etching355a termination trench in the semiconductor surface layer and that forming the dielectric liner includes forming360the dielectric liner in the termination trench.FIG.3Cadds to method300the element of forming365a power MOSFET between a first field plate trench and a second field plate trench of the group of field plate trenches. The power MOSFET includes a drain having a drain contact, a vertical drift region in the semiconductor surface layer over the drain, and a gate, a body, and a source over the vertical drift region

Applicant has disclosed a semiconductor device and a method of fabricating the semiconductor device, which includes dual shield field plates designed to operate at high voltages, e.g., in the range of 75-150 V. In one implementation, the semiconductor device may be designed to operate at 100 V. The described method is expected to minimize or eliminate defects caused by photoresist pullback in the outermost of the dual shield field plates by increasing the width of the outermost trench used to form the dual shield field plates.

Although various implementations have been shown and described in detail, the claims are not limited to any particular implementation or example. None of the above Detailed Description should be read as implying that any particular component, element, step, act, or function is essential such that it must be included in the scope of the claims. Reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described implementations that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Accordingly, those skilled in the art will recognize that the exemplary implementations described herein can be practiced with various modifications and alterations within the spirit and scope of the claims appended below.