Semiconductor storage device and control method of semiconductor storage device

A semiconductor storage device includes: a storage element that holds data; a bit line that is coupled to the storage element and in which step-down to reference voltage causes data held in the storage element to be inverted, a first step-down circuit that steps down bit line voltage to a first predetermined value equal to or below the reference voltage, the bit line voltage being voltage applied to the bit line; and a control circuit that detects a first voltage change based on a first output from a first inverter which has a voltage dependence of an occurring delay and a second output from a second inverter in which a voltage dependence of an occurring delay is larger than that of the first inverter, and that controls a step-down amount of the bit line voltage by the first step-down circuit depending on an amount of the detected first voltage change.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2022-39622, filed on Mar. 14, 2022, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a semiconductor storage device and a control method of the semiconductor storage device.

BACKGROUND

With miniaturization of semiconductor devices, manufacturing variation in memory cells has become large relative to nominal voltage. As a result, in memory cells used in a processor using dynamic voltage and frequency scaling (DVFS), a write margin decreases at low voltage, and this increases an occurrence rate of a write failure. For example, in a low-power-consumption device or the like in which power supply voltage is set to a low level, the yield of memory cells decreases.

Japanese Laid-open Patent Publication No. 2010-257554 is disclosed as related art.

SUMMARY

According to an aspect of the embodiments, a semiconductor storage device includes: a storage element that holds data; a bit line that is coupled to the storage element and in which step-down to reference voltage causes data held in the storage element to be inverted, a first step-down circuit that steps down bit line voltage to a first predetermined value equal to or below the reference voltage, the bit line voltage being voltage applied to the bit line; and a control circuit that detects a first voltage change based on a first output from a first inverter which has a voltage dependence of an occurring delay and a second output from a second inverter in which a voltage dependence of an occurring delay is larger than that of the first inverter, and that controls a step-down amount of the bit line voltage by the first step-down circuit depending on an amount of the detected first voltage change.

DESCRIPTION OF EMBODIMENTS

DVFS is a method of dynamically changing a power supply voltage and an operation frequency of a processor depending on a processing load. Examples of memory cells used in a processor using DVFS include static random-access memory (SRAM) memory cells.

Various write assist circuits have been proposed as measures against the margin decrease at low voltage. Examples of the write assist circuits include a negative-bit-line circuit that assists writing to memory cells by stepping down a bit line potential to a negative potential.

In recent years, the number of processors adopting DVFS has increased to improve performance per power of processors. Accordingly, demanded operation voltage for memory cells has expanded from minimum voltage to high voltage in the technology and, from a viewpoint of performance competition, the memory cells are demanded to operate at maximum voltage at which aging deterioration of elements is acceptable.

The negative-bit-line write assist circuit is described. In writing of data to a memory cell, a potential of one bit line of a bit line pair precharged to an H level is changed from the H level to an L level. A data holding node on one side of a latch forming the cell is thereby forcibly stepped down to L via a transfer gate, and this inverts the entire latch. The writing is thus completed. However, when manufacturing variation of transistors forming the memory cells is large, there may occur a failure in which the held data is not inverted even if one bit line is completely changed from the H level to the L level. Complementary metal oxide semiconductor (CMOS) is often used for the memory cells, and an occurrence rate of such a failure is high at low voltage.

Accordingly, the negative-bit-line write assist circuit is coupled to a path extending from the bit line pair to Vdd. The bit line pair and a coupling node thereof is isolated from Vss by the write assist circuit, and are set to a floating state. A buffer mounted in the write assist circuit drives a coupling capacitance to the coupling node to step down the potential of one bit line, to be stepped down to the L level, to a negative potential lower than Vss, and thereby assists the inversion of data held in the memory cell. The magnitude of the negative potential is determined by a capacitance ratio between a bit line parasitic capacitance and the coupling capacitance.

However, in the method described above, when the voltage is increased, voltage obtained by adding positive voltage having a magnitude of the negative potential is applied between a gate and a source of the transfer gate of the memory cell. The reliability of the transistor may be thus adversely affected. For example, when the DVFS method in which the power supply voltage and the operation frequency are dynamically changed is adopted to increase power efficiency of a large scale integrator (LSI), application of voltage to the memory cell is limited to voltage obtained by subtracting voltage corresponding to the negative potential from the maximum rated voltage, and this is a constraint in the case where high-speed operation is desired.

As a countermeasure against these problems, a technique has been proposed in which the capacitance of the step-up circuit is replaced with a variable capacitance that decreases as the power supply voltage increases. A technique has been also proposed in which, when a Vdd detector detects high voltage, a step-down circuit and a step-up circuit are simultaneously operated to reduce the potential drop of the bit line.

The technique in which the capacitance of the step-up circuit is replaced with the variable capacitance that decreases as the power supply voltage increases discloses that using a variable capacitance with a voltage dependence enables reduction of the potential drop in the bit line, and proposes several structures as such variable capacitive element. However, there is no variable capacitance that has a capacitance of 0 when the maximum rated voltage is applied. Accordingly, the upper limit of the voltage that may be applied to the LSI is limited, and the operation frequency obtainable by the application of high voltage also decreases by an amount corresponding to this limitation. Since the assist operation is executed also in a high voltage range where the assist does not have to be executed, wasteful power is generated.

In the technique in which the step-down circuit and the step-up circuit are simultaneously operated to reduce the potential drop of the bit line, setting of not dropping the potential of the bit line below Vss in the high voltage range may be achieved. However, the number of arranged capacitive elements that occupy a large area of the assist circuit have to be doubled, and the area of the assist circuit increases. The assist operation is executed also in the high voltage range where the assist does not have to be executed as in Embodiment 1, and the simultaneous operation of the step-down circuit and the step-up circuit leads to very large wasteful power.

The disclosed technique has been made in view of the above circumstances, and an object thereof is to provide a semiconductor storage device and a control method of the semiconductor storage device that suppress a decrease in reliability and save power.

Embodiments of a semiconductor storage device and a control method of the semiconductor storage device disclosed in the present application are described below in detail based on the drawings. The semiconductor storage device and the control method of the semiconductor storage device disclosed in the present application are not limited to the following embodiments.

FIG.1is a schematic configuration diagram of an LSI. The LSI1is, for example, a processor. The LSI1includes a plurality of cores2and a level (L) 2 cache4. L1 caches3are mounted in the cores2. A plurality of SRAMs10are mounted in the L1 caches3and the L2 cache4. The SRAMs10are semiconductor storage devices. As illustrated inFIG.1, each of the SRAMs10includes memory cell arrays5. The SRAM10also includes word drivers, write/sense amplifiers, and a decoder.

FIG.2is a configuration diagram of the SRAM according to the embodiment. The SRAM10includes a memory cell100, a write amplifier101, a step-down circuit102, and a Vdd dependence generation circuit103. The SRAM10also includes a bit line Bit and a bit line/Bit. The bit line Bit and the bit line/Bit are coupled to each other at a coupling node a via transistors T3and T4. The SRAM10includes a word line WL, input paths of a write enable signal WE and a write data signal WD, and an NMOS transistor T5. A drain of the NMOS transistor T5is coupled to the coupling node a, and a source of the NMOS transistor T5is coupled to Vss.

The memory cell100is a storage element, and a plurality of memory cells100are mounted in each of the memory cell arrays5illustrated inFIG.1. Each memory cell100includes transfers T1and T2, a CMOS inverter INV2having an output node D, and a CMOS inverter INV1having an output node /D.

The output node /D of the CMOS inverter INV1is coupled to the transfer T1, and the CMOS inverter INV1is coupled to the bit line Bit via the transfer T1. The output node D of the CMOS inverter INV2is coupled to the transfer T2, and the CMOS inverter INV2is coupled to the bit line /Bit via the transfer T2. An input node of the CMOS inverter INV1is coupled to an output node D of the CMOS inverter INV2. Meanwhile, an input node of the CMOS inverter INV2is coupled to the output node /D of the CMOS inverter INV1.

Gates of the transfers T1and T2are coupled to the word line WL. A terminal of the transfer T1opposite to a coupling end to the CMOS inverter INV1is coupled to the bit line Bit. A terminal of the transfer T2opposite to a coupling end to the CMOS inverter INV2is coupled to the bit line /Bit.

The write amplifier101includes AND circuits G1and G3, an inverter G2, and the NMOS transistors T3and T4.

A source of the NMOS transistor T3is coupled to the bit line Bit, and a drain of the NMOS transistor T3is coupled to the coupling node a. A gate of the NMOS transistor T3is coupled to an output node of the AND circuit G1. A drain of the NMOS transistor T4is coupled to the bit line /Bit, and a source of the NMOS transistor T4is coupled to the coupling node a. A gate of the NMOS transistor T4is coupled to an output node of the AND circuit G3.

The write enable signal WE is inputted into one of input terminals of each of the AND circuits G1and G3. The write data signal WD is inputted into the other input terminal of the AND circuit G1. An output terminal of the inverter G2is coupled to the other input terminal of the AND circuit G3. The write data signal WD is inputted into an input terminal of the inverter G2.

The step-down circuit102includes a buffer G4and a coupling capacitance C1. The step-down circuit102is an example of a “first step-down circuit”.

An input terminal of the buffer G4is coupled to an ASSIST ENX terminal that outputs an assist signal for dropping the voltage of the bit line Bit and the bit line /Bit to a negative potential. An output terminal of the buffer G4is coupled to the coupling capacitance C1. The ASSIST ENX terminal is coupled to a gate of the NMOS transistor T5.

The coupling capacitance C1is coupled to the output terminal of the buffer G4and a path coupling the coupling node a to the NMOS transistor T5.

The Vdd dependence generation circuit103includes an inverter chain131, an inverter chain132, and a NAND circuit133. The inverter chain131is an example of a “first inverter”. The inverter chain132is an example of a “second inverter”.

One of input terminals of the NAND circuit133is coupled to an EN′ terminal that is an output terminal of the inverter chain131. The other input terminal of the NAND circuit133is coupled to an ENX′ terminal that is an output terminal of the inverter chain132. An EN_NPLS terminal that is an output terminal of the NAND circuit133is coupled to the ASSIST ENX terminal.

In the inverter chain131, an even number of stages of gates in which a voltage dependence of a delay is small are arranged in series. The voltage dependence of the delay being small means a delay amount that decreases with a voltage increase is small. Conversely, the voltage dependence of the delay being large means the delay amount that decreases with the voltage increase is large. In the inverter chain132, an odd number of stages of gates in which the voltage dependence of the gate delay is large are arranged in series.

The voltage dependence of the gate delay may vary depending on, for example, a voltage threshold of a transistor, a circuit configuration such as multi-stage stacking of transistors, a combination thereof, or the like.FIG.3is a diagram illustrating the voltage dependence of the gate delay in the case where the voltage threshold of the transistor is varied. The horizontal axis ofFIG.3represents the power supply voltage (Vdd), and the vertical axis represents a delay variation. A graph11illustrates a delay variation of a transistor with a small voltage threshold of a delay. A graph13illustrates a delay variation of a transistor with a large voltage threshold of a delay. A graph12illustrates a delay variation of a transistor with a voltage threshold of a delay between those in the graph11and the graph13.

As illustrated in the graph13, it may be said that the transistor with the large voltage threshold has a large delay variation, and has a large voltage dependence. Conversely, as illustrated in the graph11, it may be said that the transistor having the small voltage threshold has a small delay variation, and has a small voltage dependence.

Accordingly, for example, in the inverter chain131, many stages of the transistors with the small voltage threshold inFIG.3are arranged, and this makes the voltage dependence of the delay small. In the inverter chain132, many stages of the transistors with the large voltage threshold inFIG.3are arranged, and this makes the voltage dependence of the delay large.

The number of stages of gates in each inverter chain is set such that, when Vdd is in a low voltage range, the delay of the inverter chain132is larger than the delay of the inverter chain131and, when Vdd is in a high voltage range, the delay of the inverter chain132is equal to or smaller than the delay of the inverter chain131.

The write enable signal WE is inputted into an EN terminal that is an input terminal of the inverter chain131and the inverter chain132.

When Vdd is in the low voltage range, since the delay of the inverter chain132is larger than the delay of the inverter chain131, the EN terminal changes from L that is a Vss level to H that is a Vdd level, and this causes a negative pulse to be generated from the EN_NPLS terminal. Conversely, when Vdd is in the high voltage range, since the delay of the inverter chain132is equal to or smaller than the delay of the inverter chain131, no negative pulse is generated from the EN_NPLS terminal even if the EN terminal changes from L that is the Vss level to H that is the Vdd level.

FIG.4is a diagram illustrating relationships between the level of Vdd and the width of the negative pulse. The vertical axis of each of graphs151to153represents voltage, and the horizontal axis represents a lapse of time. The graph151illustrates an operation waveform of each of signals in the case where Vdd is in the low voltage range. The graph152illustrates an operation waveform of each of the signals in the case where Vdd is in an intermediate voltage range between the low voltage range and the high voltage range. The graph153illustrates an operation waveform of each of the signals in the case where Vdd is in the high voltage range. Relationships between the magnitude of Vdd and the negative pulse generated at the EN_NPLS terminal are described with reference toFIG.4.

A waveform161illustrates a voltage change at the EN terminal of Vdd dependence generation circuit103. A waveform162illustrates a voltage change at the EN′ terminal of the inverter chain131. A waveform163illustrates a voltage change at the ENX′ terminal of the inverter chain132. A waveform164illustrates a voltage change at the EN_NPLS terminal of the NAND circuit133.

The case where Vdd is in the low voltage range is described. As illustrated in the graph151, the EN terminal changes from L to H at a timing T11. Then, the EN′ terminal changes from L to H at a timing T12that is a point where a period T18has elapsed from the timing T11, and the EN_NLPS terminal of the NAND circuit133thereby changes from H to L (step S1), the period T18being the delay of the inverter chain131. For example, before the timing T12, the EN′ terminal is L and the ENX′ terminal is H, the EN_NLPS terminal of the NAND circuit133is thus H. After the timing T12, the EN′ terminal and the ENX′ terminal are both H, the EN_NLPS terminal of the NAND circuit133is thus L.

In this case, a period T19that is a delay, from the timing T11, of the inverter chain132with the large voltage dependence is longer than the period T18that is the delay, from the timing T11, of the inverter chain131with the small voltage dependence. Accordingly, the ENX′ terminal changes from H to L at a timing T13that is later than the timing T12and that is a point where the period T19has elapsed from the timing T11(step S2). The negative pulse outputted from the EN_NLPS terminal is thereby generated. Processing indicated by the arrows in the graphs152and153also correspond to the respective processing illustrated in the graph151.

As illustrated in the graph152, when Vdd increases from the low voltage range to the intermediate voltage range, the delay times of both of the inverter chains131and132become shorter. Accordingly, the change of the EN′ terminal from L to H occurs at a timing T14earlier than the timing T12. The change of the ENX′ terminal from H to L occurs at a timing T15earlier than the timing T13. Note that, since the voltage dependence of the inverter chain132is larger than that of the inverter chain131, a degree at which the delay of the inverter chain132is shortened is greater than that of the inverter chain131. Accordingly, an interval between the timing T14and the timing T15is shorter than an interval between the timing T12and the timing T13. For example, the width of the negative pulse outputted from the EN_NLPS terminal becomes smaller.

As illustrated in the graph153, when the voltage further increases and Vdd reaches the high voltage range, the delay times of both of the inverter chains131and132become even shorter. The change of the EN′ terminal from L to H thereby occurs at a timing T16earlier than the timing T14. The change of the ENX′ terminal from H to L occurs at a timing T17earlier than the timing T15. Note that an interval between the timing T16and the timing T17is even shorter than the interval between the timing T14and the timing T15. In this case, the EN_NLPS terminal returns to H before completely dropping from H to L. The negative pulse is thus not generated as illustrated in the graph153.

Description continues by returning toFIG.2. Changing the numbers of stages of gates and a combination of voltage dependencies in the inverter chains131and132adjusts voltage at which no negative pulse is generated.

An operation in data writing to the SRAM10is described next. Before writing to the memory cell100, the bit lines Bit and/Bit are precharged to H. The word line WL is L, and the write enable signal WE is L. The ASSIST EXT terminal is H. At this time, the outputs of the AND circuits G1and G3are L, the NMOS transistors T3and T4are off, and the NMOS transistor T5is on. The coupling node a is L.

The data writing to the memory cell100is performed by changing the word line WL from L to H to turn on the transfers T1and T2of the memory cell100and then transitioning the write enable signal WE from L to H. At this time, the write data signal WD turns on the NMOS transistor T3or the NMOS transistor T4depending on inputted data, and either the bit line Bit or/Bit is stepped down to Vss. An internal node of the memory cell100is thereby forcibly set to L, and normal writing is completed. For example, when the write data signal WD is H, the NMOS transistor T3is turned on, and the bit line Bit is stepped down to Vss.

The transition of the write enable signal WE from L to H causes the EN terminal common to the inverter chain131and the inverter chain132of the Vdd dependence generation circuit103to simultaneously transition from L to H.

When Vdd is in the low voltage range, for example, is about 0.5 V, the delay at the EN′ terminal of the inverter chain131is earlier than the delay at the ENX′ terminal of the inverter chain132. Accordingly, signals of opposite phases depending on a difference between the delays are inputted into the NAND circuit133. A negative pulse is thereby generated at the ASSIST_ENX terminal that is equal to the output of the EN_NPLS terminal of the NAND circuit133. This negative pulse is generated behind the write enable signal WE by a time equal to the delay of the inverter chain131. The normal writing performed by stepping down the aforementioned bit line Bit to Vss is completed within the delay time of the negative pulse with respect to the write enable signal WE.

The negative pulse generated at the ASSIST_ENX terminal turns off the NMOS transistor T5coupling the bit line Bit to Vss during a period in which L due to the negative pulse continues. The bit line Bit and the coupling node a are thereby isolated from Vss while at L to be brought into a floating state, and are set to 0 V that is an initial potential.

Immediately after the turn-off of the NMOS transistor T5, the negative pulse drives the coupling capacitance C1from H to L via the buffer G4. The bit line Bit that is 0 V due to the floating is thereby further stepped down to a negative potential below Vss by a (V) that is predetermined voltage. For example, the bit line Bit is boosted to a negative potential in response to a leading edge of the negative pulse, and assist of stepping down the bit line Bit to the negative potential continues for the period of the pulse width. The internal node of the memory cell100is thus more strongly stepped down, and the SRAM10may secure a write margin in the memory cell100. The predetermined voltage a is determined based on a capacitance ratio between a parasitic capacitance of the bit lines Bit and /Bit and the coupling capacitance C1. The bit line Bit is then reset to Vss in response to the change from L to H due to the trailing edge of the negative pulse.

The operation in the low voltage range such as, for example, at 0.5 V has been described above. Next, the case where the voltage increases from the low voltage range is described. The voltage dependence of the delay of the inverter chain132is larger than the voltage dependence of the delay of the inverter chain131. An increase in voltage thus reduces the delay difference between the inverter chain131and the inverter chain132. For example, the assist period equal to the width of the negative pulse generated at the ASSIST ENX terminal becomes shorter. When the voltage reaches or exceeds a certain level, no negative pulse is generated at the ASSIST ENX terminal, and the ASSIST ENX terminal is fixed at H level. Thus, no assist is performed. Since the Vdd dependence generation circuit103and the step-down circuit102do not operate in the state where there is no assist, the bit line Bit does not fall below Vss. Accordingly, in a voltage range in which the assist does not have to performed, such as, for example, at 0.9 V, no negative pulse is generated at the ASSIST ENX terminal. This may suppress application of stress equal to or above the power supply voltage to the transfer T1of the memory cell100. Wasteful power consumption due to the assist may also be reduced.

In the case of the high voltage, unlike in the case of the low voltage, a situation where a write operation margin is insufficient seldom occurs even in a CMOS. Thus, a probability of a failure occurring in the memory cell100may be maintained at a low value even without the stepping-down of the bit line Bit to a negative potential.

FIG.5is a diagram illustrating an operation waveform of each of signals in the SRAM according to Embodiment 1. Next, a voltage change in each of the signals in the data writing in the semiconductor storage device according to Embodiment 1 is described with reference toFIG.5. Also in this case, the case where the data writing is performed by, for example, setting the write data signal WD to H to turn on the NMOS transistor T3and step down the bit line Bit to Vss is described as an example.

The vertical axis of each of graphs211to213inFIG.5represents voltage, and the horizontal axis represents a lapse of time. The graph211illustrates an operation waveform of each of signals in the case where Vdd is in the low voltage range. The graph212illustrates an operation waveform of each of the signals in the case where Vdd is in the intermediate voltage range between the low voltage range and the high voltage range. The graph213illustrates an operation waveform of each of the signals in the case where Vdd is in the high voltage range.

A waveform201inFIG.5illustrates a voltage change of the write enable signal WE. A waveform202illustrates a voltage change at the ASSIST ENX terminal. A waveform203illustrates a voltage change in the bit line Bit. A waveform204illustrates a voltage change at the output node D. A waveform205illustrates a voltage waveform at the output node /D. A potential200illustrates Vss that is a reference for each of the bit line Bit, the output node D, and the output node /D.

The operation waveforms of the respective signals in the case where Vdd is in the low voltage range that are illustrated in the graph211are described. When the data writing is performed, the write enable signal WE changes from L to H as illustrated by the waveform201(step S3). In response to this, the bit line Bit changes from H to L as illustrated by the waveform203(step S4). When the bit line Bit changes to L, the output node D that is a cell internal node is stepped down to L as illustrated by the waveform204(step S5).

In this case, the ASSIST ENX terminal changes from H to L as illustrated by the waveform202(step S6). The ASSIST ENX terminal is L during a period L1, and then changes to H (step S7). This voltage change at the ASSIST ENX terminal generates a negative pulse with a pulse width of the period L1. The bit line Bit is boosted to the negative potential a as illustrated by the waveform203in response to the leading edge of the negative pulse (step S8). The internal node of the memory cell100is thereby more strongly stepped down. The negative potential continues in the bit line Bit during the period L1of the pulse width. The bit line Bit is then reset to Vss in response to the change from L to H due to the trailing edge of the negative pulse (step S9). The D signal then returns from the negative voltage state to Vss (step S10), and is maintained at L. The writing of data to the memory cell100is thus completed.

As illustrated by the graph212, when Vdd increases from the low voltage range to the intermediate voltage range, the delay difference between the inverter chain131and the inverter chain132decreases. The assist period L1that is the width of the negative pulse generated at the ASSIST ENX terminal thereby becomes shorter. Although the assist period L1becomes shorter, the bit line Bit is stepped down to the negative potential a as illustrated by the waveform203of the graph212and, in response to this, the output node D that is the cell internal node is also stepped down to the negative potential a as illustrated by the waveform204of the graph212, also in this case. The writing to the memory cell100is thereby more strongly performed.

Meanwhile, when Vdd reaches the high voltage range, the delay difference between the inverter chain131and the inverter chain132further decreases as illustrated by the graph213. The assist period L1that is the width of the negative pulse generated at the ASSIST ENX terminal thereby disappears as illustrated by the waveform202of the graph213. When Vdd becomes even higher, a decrease in voltage generated in the waveform202also disappears, and the ASSIST ENX terminal is fixed to H. In this case, the bit line Bit drops to Vdd, but is not stepped down to a negative potential below Vdd as illustrated by the waveform203of graph213.

As described above, the Vdd dependence generation circuit103corresponds to an example of a “control unit”, detects the power supply voltage based on a first output from a first inverter which has a voltage dependence of an occurring delay and a second output from a second inverter in which a voltage dependence of an occurring delay is larger than that of the first inverter, and controls a step-down amount of the bit line voltage by the first step-down circuit depending on the amount of the detected power supply voltage. For example, the Vdd dependence generation circuit103causes the step-down circuit102to step down the bit line to the negative potential a that is a first predetermined value, during a period of a difference between a timing of the first output in response to an input of a predetermined signal to the EN terminal and a timing of the second output in response to the input of the same predetermined signal.

FIG.6is a flowchart of data rewriting processing in the low voltage range in the SRAM according to Embodiment 1. The flow of the data rewriting processing in the low voltage range in the SRAM10according to the present embodiment is described next with reference toFIG.6. In this section, description is given of the case where writing is performed by stepping down the voltage of the bit line Bit.

The word line WL changes from L to H, and the transfers T1and T2of the memory cell100are turned on (step S101).

The write enable signal WE then transitions from L to H (step S102).

Next, data is inputted by using the write data signal WD (step S103).

The NMOS transistor T3is turned on in response to the input with the write data signal WD, and the bit line Bit is stepped down to Vss (step S104).

The transition of the write enable signal WE from L to H causes the EN terminal common to the inverter chain131and the inverter chain132of the Vdd dependence generation circuit103to simultaneously transition from L to H (step S105).

The EN′ terminal of the inverter chain131then transitions from L to H (step S106).

The EN_NPLS terminal then transitions from H to L, and the leading edge of the negative pulse is generated at the ASSIST_ENX terminal (step S107).

The negative pulse generated at the ASSIST_ENX terminal turns off the NMOS transistor T5coupling the bit line Bit to Vss. The negative pulse also drives the coupling capacitance C1from H to L via the buffer G4. The bit line Bit that is 0 V due to the floating is thereby further stepped down to the negative potential below Vss by the predetermined voltage (step S108).

The ENX′ terminal then transitions from H to L with a delay corresponding to a difference between the delay of the inverter chain131and the delay of the inverter chain132(step S109).

Next, the EN_NPLS terminal transitions from L to H, and the trailing edge of the negative pulse is generated at the ASSIST_ENX terminal (step S110).

The bit line Bit is then reset to Vss in response to the change from L to H due to the trailing edge of the negative pulse (step S111).

FIG.7is a flowchart of data rewriting processing in the high voltage range in the SRAM according to Embodiment 1. The flow of the data rewriting processing in the high voltage range in the SRAM10according to the present embodiment is described next with reference toFIG.7. Also in this section, description is given of the case where writing is performed by stepping down the voltage of the bit line Bit.

The word line WL changes from L to H, and the transfers T1and T2of the memory cell100are turned on (step S121).

The write enable signal WE then transitions from L to H (step S122).

Next, data is inputted by using the write data signal WD (step S123).

The NMOS transistor T3is turned on in response to the input with the write data signal WD, and the bit line Bit is stepped down to Vss (step S124).

The transition of the write enable signal WE from L to H causes the EN terminal common to the inverter chain131and the inverter chain132of the Vdd dependence generation circuit103to simultaneously transition from L to H (step S125).

The EN′ terminal of the inverter chain131then transitions from L to H (step S126).

Since the difference between the delay of the inverter chain131and the delay of the inverter chain132is small in the high voltage range, the ENX′ terminal transitions from H to L before the EN_NPLS terminal transitions from H to L (step S127). The bit line Bit is thereby maintained at Vss without being stepped down to the negative potential.

As described above, in the semiconductor storage device according to the present embodiment, when Vdd is low voltage, the voltage of the bit line is dropped to the negative potential below Vss in the data writing and, when Vdd is high voltage, the voltage of the bit line is dropped to Vss in the data writing.

For example, in the technique in which the capacitance of the step-up circuit is replaced by the variable capacitance that decreases as the power supply voltage increases, the assist circuit operates in all voltage ranges. Accordingly, wasteful power is generated in a range where no failure occurs even without the assist. When the maximum rated voltage is applied to the memory cell, voltage equal to or above the maximum rated voltage is applied to the memory cell due to the assist circuit, and thus a characteristic deterioration or a problem in reliability occurs.

Meanwhile, in the semiconductor storage device according to the present embodiment, the write assist is automatically, completely canceled at high voltage. Accordingly, deterioration of the memory cell may be reduced. In the semiconductor storage device according to the present embodiment, an operation voltage may be freely set as long as the operating voltage is equal to or below the maximum rated voltage. Accordingly, use of the semiconductor storage device according to the present embodiment may expand an operation speed range to the maximum and also improve power efficiency of the LSI in the DVFS method. Wasteful power due to assist that does not have to be performed may also be reduced.

In the technique of simultaneously operating the step-down circuit and the step-up circuit to reduce the potential drop in the bit line, the write assist may be completely canceled in the high voltage range. However, in order to achieve this, the step-down circuit and the step-up circuit are simultaneously operated.

Meanwhile, in the semiconductor storage device according to the present embodiment, the step-down circuit may be shut down. Accordingly, it is possible to suppress the size of the capacitive element occupying a large area in the assist circuit to a small size, and also reduce wasteful power for canceling the assist in the high voltage range. In the semiconductor storage device according to the present embodiment, it is possible to automatically change the assist amount stepwise and suppress a power increase due to the assist to the minimum.

Although a processor or the like may control a write assist circuit of a mounted memory, this design leads to an increase in development cost for logic design, implementation, signal distribution, and timing design for the control of the write assist circuit. Meanwhile, in the case of the semiconductor storage device according to the present embodiment, an LSI designer may freely perform DVFS settings or the like while suppressing the development cost by using the memory cell incorporating the write assist.

FIG.8is a configuration diagram of an SRAM according to Embodiment 2. The SRAM10according to the present embodiment is different from that in Embodiment 1 in that the assist for dropping the bit line Bit to the negative potential is maintained for a certain period. The SRAM10according to the present embodiment further includes an inverter G5and a dynamic gate104. Description of a function of each of parts that are the same as those in Embodiment 1 are omitted in the following description.

In the Vdd dependence generation circuit103, the write enable signal WE is inputted into the EN terminal that is the input terminal. In the Vdd dependence generation circuit103, the EN_NPLS terminal that is the output terminal of the negative pulse is coupled to an input of the inverter G5.

The inverter G5generates a trg signal that is a signal obtained by converting the negative pulse outputted from the Vdd dependence generation circuit103to a positive pulse. The inverter G5inputs the trg signal into an EN terminal of the dynamic gate104.

The dynamic gate104includes a PC terminal and the EN terminal that are two input terminals and an OUT terminal that is an output terminal. The PC terminal of the dynamic gate104is coupled to a precharge line PC to which a control instruction is outputted. The OUT terminal of the dynamic gate104is coupled to the ASSIST ENX terminal.

FIG.9is a circuit diagram illustrating an example of the dynamic gate. The PC terminal of the dynamic gate104extends from a gate of a P-channel FET switch coupled to Vdd. The EN terminal of the dynamic gate104extends from a gate of an N-channel FET switch arranged between Vss and the FET switch to which the PC terminal is coupled. A coupling point between the FET switch to which the PC terminal is coupled and the FET switch to which the EN terminal is coupled is coupled to the OUT terminal, and an H keeper141is arranged between the coupling point and the OUT terminal.

FIG.10is a diagram illustrating operation waveforms of the dynamic gate. The vertical axis ofFIG.10represents voltage and the horizontal axis represents a lapse of time. A graph21illustrates a waveform of an input signal to the PC terminal, a graph22illustrates a waveform of an input signal to the EN terminal, and a graph23illustrates a waveform of an output signal from the OUT terminal.

In the dynamic gate104, a negative pulse having a width of a period T21is inputted from the precharge line PC into the PC terminal as illustrated in the graph21, with the trg signal inputted into the EN terminal being L as illustrated in the graph22. In the dynamic gate104, the output from the OUT terminal is thereby precharged to H during the period T22corresponding to the period T21as illustrated by the graph23. In the dynamic gate104, even when the period T21elapses and the PC terminal returns to H, the H keeper141continuously maintains the output from the OUT terminal at H during a period T23as illustrated in the graph23. Then, a change of the trg signal inputted into the EN terminal to H ends the period T23, and the output from the OUT terminal of the dynamic gate104changes from H to L. In the dynamic gate104, an input of the negative pulse from the precharge line PC in the next cycle resets the output from the OUT terminal to H, and the operation illustrated inFIG.10is repeated. The dynamic gate104is an example of a “holding circuit”. The period T23is an example of a “predetermined period”.

FIG.11is a diagram illustrating an operation waveform of each of signals in the SRAM according to Embodiment 2. An operation of the SRAM10according to the present embodiment is described next with reference toFIG.11. The vertical axis of each of graphs221to223inFIG.11represents voltage, and the horizontal axis represents a lapse of time. The graph221illustrates an operation waveform of each of signals in the case where Vdd is in the low voltage range. The graph222illustrates an operation waveform of each of the signals in the case where Vdd is in the intermediate voltage range between the low voltage range and the high voltage range. The graph223illustrates an operation waveform of each of the signals in the case where Vdd is in the high voltage range.

Prior to the transition of the write enable signal WE from L to H, in the dynamic gate104, the negative pulse is applied to the PC terminal, the output from the OUT terminal is reset to H, and the ASSIST ENX terminal changes from L to H (step S21). Next, when the write enable signal WE changes from L to H, the bit line Bit is dropped to Vss. When Vdd is a low voltage, the Vdd dependence generation circuit103generates the negative pulse upon the change of the write enable signal WE from L to H (step S22). The inverter G5generates the trg signal obtained by converting the negative pulse outputted from the Vdd dependence generation circuit103to the positive pulse, and inputs the trg signal into the EN terminal of the dynamic gate104(step S23). In the dynamic gate104, inputting the trg signal into the EN terminal changes the output from the OUT terminal from H to L (step S24). The ASSIST ENX terminal thereby changes from H to L, and the bit line Bit is driven to the negative potential (step S25). Processing indicated by the arrows in the graph222correspond to the respective processing described in the graph221. Processing indicated by the arrows in the graph223correspond to the processing of steps S21to S23in the graph221.

As Vdd increases, the trg signal inputted into the EN terminal becomes narrower as illustrated in the graph222. When the voltage further increases and Vdd reaches a high voltage range, no negative pulse is generated in the Vdd dependence generation circuit103, and the trg signal also becomes small. Accordingly, the bit line Bit does not drop to the negative potential below Vss.

As described above, in the semiconductor storage device according to the present embodiment, when Vdd is low voltage, the ASSIST ENX terminal transitions from H to L, and is then held at L until the reset is performed with the input signal from the precharge line PC in the next cycle. During the period in which the ASSIST ENX terminal is held at L, the bit line remains at the negative potential. Since the semiconductor storage device according to Embodiment 1 performs the assist only during the period of the pulse width, it is preferable to increase the step-down amount of the bit line to some extent for sufficient assist. Meanwhile, in the semiconductor storage device according to the present embodiment, since the assist period may be extended, the assist intensity may be relatively small. Accordingly, it is possible to reduce the capacitance for the assist and suppress the area and power of the assist circuit.

In the semiconductor storage device according to the present embodiment, the assist is completely canceled in the high voltage range. Accordingly, it is possible to apply voltage up to the maximum rated voltage to the SRAM without being restricted by the withstanding voltage of the memory cell. The semiconductor storage device according to the present embodiment suppresses the operation of the step-down circuit itself by canceling the assist. Accordingly, the power consumption may be suppressed to a low level in the high voltage range.

FIG.12is a configuration diagram of an SRAM according to Embodiment 3. The SRAM10according to the present embodiment is different from that in Embodiment 2 in that the step-down amount of the bit line Bit is changed depending on voltage. In the following description, description of the function of each of the already-described parts is omitted.

The Vdd dependence generation circuit103according to the present embodiment has two outputs, and these outputs vary in voltage at which no pulses is generated therefrom. The Vdd dependence generation circuit103includes an inverter chain134in addition to the inverter chain131and the inverter chain132. The Vdd dependence generation circuit103also includes a NAND circuit135in addition to the NAND circuit133.

In the inverter chain134, an even number of stages of gates including transistors in which the voltage dependence of the gate delay is large are arranged in series. For example, in the inverter chain134, the voltage dependence of the delay is large. An input terminal of the inverter chain134is coupled to the output terminal of the inverter chain132. An ENX″ terminal that is an output terminal of the inverter chain134is coupled to one of input terminals of the NAND circuit135. The inverter chain134is an example of a “third inverter”.

The one input terminal of the NAND circuit135is coupled to the ENX″ terminal that is the output terminal of the inverter chain134. The other input terminal of the NAND circuit135is coupled to the EN′ terminal that is the output terminal of the inverter chain131.

In this section, the output terminal of the NAND circuit133is referred to as an EN_NPLS1terminal, and an output terminal of the NAND circuit135is referred to as an EN_NPLS2terminal.

The EN_NPLS1terminal that is the output terminal of the NAND circuit133is coupled to the input terminal of the inverter G5. The EN_NPLS2terminal that is the output terminal of the NAND circuit135is coupled to an input terminal of an inverter G7. An output signal of the inverter G5is referred to as a trg1signal, and an output signal of the inverter G7is referred to as a trg2signal.

The trg1signal outputted from the inverter G5is inputted into an EN terminal of a dynamic gate104A. The trg2signal outputted from the inverter G7is inputted into an EN terminal of a dynamic gate104B. PC terminals of both of the dynamic gates104A and104B are coupled to the precharge line PC. An OUT terminal that is an output terminal of the dynamic gate104A is coupled to an ASSIST ENX1terminal. An OUT terminal that is an output terminal of the dynamic gate104B is coupled to an ASSIST ENX2terminal.

A step-down circuit102A includes the buffer G4and the coupling capacitance C1. The input terminal of the buffer G4is coupled to the ASSIST ENX1terminal. An output terminal of the buffer G4is coupled to the coupling capacitance C1. The coupling capacitance C1is coupled to a portion between the coupling node a and the NMOS transistor T5.

A step-down circuit102B includes a buffer G6and a coupling capacitance C2. An input terminal of the buffer G6is coupled to the ASSIST ENX2terminal. An output terminal of the buffer G6is coupled to the coupling capacitance C2. The coupling capacitance C2is coupled to a portion between the coupling node a and the NMOS transistor T5. The ASSIST ENX2terminal is coupled to a gate of the NMOS transistor T5. The step-down circuits102A and102B are examples of a “first step-down circuit” and a “second step-down circuit”.

As described above, the SRAM10according to the present embodiment is provided with two sets of control circuits, a set of the step-down circuit102A and the dynamic gate104A being a control circuit thereof and a set of the step-down circuit102B and the dynamic gate104B being a control circuit thereof, and the sets are coupled respectively to the two output terminals of the Vdd dependence generation circuit103.

An operation of the SRAM10according to the present embodiment is described. When Vdd is in the low voltage range, both of the step-down circuits102A and102B operate. As the voltage of Vdd increases, the step-down circuit102A stops, and eventually both of the step-down circuits102A and102B stop operating. Although the case where two sets of control circuits are provided has been described in this section, three or more sets of control circuits each including the step-down circuit102and the dynamic gate104may be provided. In a configuration including multiple sets of control circuits, when Vdd is in the low voltage range, all step-down circuits102operate. As Vdd increases, the number of the operating step-down circuits102decreases, and eventually all step-down circuits102stop operating.

FIG.13is a diagram illustrating operation waveforms of the Vdd dependence generation circuit according to Embodiment 3. The vertical axis of each of graphs301to303inFIG.13represents voltage, and the horizontal axis represents a lapse of time. The graph301illustrates an operation waveform of each of signals in the case where Vdd is in the low voltage range. The graph302illustrates an operation waveform of each of the signals in the case where Vdd is in the intermediate voltage range between the low voltage range and the high voltage range. The graph303illustrates an operation waveform of each of the signals in the case where Vdd is in the high voltage range.

An output from the EN′ terminal and an output from the ENX″ terminal of the inverter chain134are inputted into the NAND circuit135. The NAND circuit135outputs a signal from the EN_NPLS2terminal. Both of the EN_NPSL1terminal and the EN_NPSL2terminal are dropped to L at a timing at which the output from the EN′ terminal changes to H (step S31). The EN_NPSL1terminal returns to H at a timing at which the ENX′ terminal changes to L (step S32). The EN_NPSL2terminal returns to H at a timing at which the ENX″ terminal changes to L (step S33).

Processing indicated by the arrows in the graph302correspond to the respective processing in the graph301. Processing indicated by the arrows in the graph303correspond to the processing of steps S31and S33in the graph301.

Since the delay at the ENX″ terminal is larger than that at the ENX′ terminal depending on the delay by the inverter chain134, a negative pulse generated at the EN_NPLS2terminal has a larger width than the negative pulse generated at the EN_NPLS1terminal. Accordingly, when Vdd is in the low voltage range, the negative pulses are generated at both of the EN_NPLS1terminal and the EN_NPLS2terminal as illustrated in the graph301. When the voltage of Vdd is increased, the negative pulse at the EN_NPLS1terminal disappears, and the negative pulse generated at the EN_NPLS2terminal remains as illustrated in the graph302. When the voltage of Vdd is further increased and reaches the high voltage range, no negative pulse is generated at the EN_NPLS1terminal or the EN_NPLS2terminal as illustrated in the graph303.

Assume that a potential desirable for writing at expected minimum voltage is Vss-2aand a capacitance desirable for generating this potential is C. In this case, the coupling capacitances C1and C2are set such that a sum thereof is C. Adjusting the number of stages and the voltage dependence of the delay in each of the inverter chains131,132, and134forming the Vdd dependence generation circuit103enables adjustment of the width of the corresponding negative pulse, and enables adjustment of voltage at which the corresponding negative pulse disappears. For example, the adjustment may be made such that, when the voltage reaches a level at which writing at Vss-a is possible, the generation of the pulse at the EN_NPLS1terminal stops.

FIG.14is a diagram illustrating operation waveforms of the SRAM according to Embodiment 3. The vertical axis of each of graphs311to313inFIG.14represents voltage, and the horizontal axis represents a lapse of time. The graph311illustrates an operation waveform of each of signals in the case where Vdd is in the low voltage range. The graph312illustrates an operation waveform of each of the signals in the case where Vdd is in the intermediate voltage range between the low voltage range and the high voltage range. The graph313illustrates an operation waveform of each of the signals in the case where Vdd is in the high voltage range.

When Vdd is in the low voltage range, as illustrated in the graph311, the PC signals are inputted from the precharge line PC into the dynamic gates104A and104B, and both of the ASSIST_ENX1terminal and the ASSIST_ENX2terminal change to H (step S34). Then, the trg1signal is inputted into the dynamic gate104A and the OUT terminal changes to H. This causes the ASSIST_ENX1terminal to change from L to H (step S35). Similarly, the trg2signal is inputted into the dynamic gate104B and the OUT terminal changes to H. This causes the ASSIST_ENX2terminal to change from L to H (step S36). Both of the step-down circuits102A and102B thereby operate to step down the bit line Bit to Vss-2a(step S37).

Processing indicated by the arrows in the graph312correspond to the processing of steps S34, S36, and S37in the graph311. A processing indicated by the arrow in the graph313corresponds to the processing of steps S34in the graph311.

When the voltage of Vdd is increased and reaches the level at which writing at Vss-a is possible, the generation of the negative pulse at the EN_NPLS1terminal stops, and the trg1signal disappears as illustrated in the graph312. In this case, the operation of the step-down circuit102A stops, and the operation of the step-down circuit102B continues to step down the bit line Bit to Vss-a.

When Vdd reaches the high voltage range and reaches a level at which writing at Vss is possible, the generation of the negative pulse at the EN_NPLS2terminal also stops, and the trg2signal disappears as illustrated in the graph313. In this case, the operations of both of the step-down circuits102A and102B stop, and the bit line Bit is stepped down only to Vss.

As described above, in the semiconductor storage device according to the present embodiment, the step-down amount of the bit line changes stepwise depending on the level of the voltage. Accordingly, it is possible to reduce wasteful power and suppress deterioration of the memory cell to the minimum by reducing the voltage applied to the memory cell. Although the configuration including two sets of the Vdd dependence generation circuits and the step-down circuits is described in this section, the effects may be improved by increasing the number of the sets.

Although the configuration using the dynamic gates has been described above, a similar configuration may be incorporated in the configuration of Embodiment 1 using no dynamic gates.

Next, Embodiment 4 is described. A SRAM10according to the present embodiment is different from that in Embodiment 2 in that voltage at which the generation of the drive pulse of the step-down circuit102stops is adjustable. In the following description, description of the function of each of the already-described parts is omitted.

In the Vdd dependence generation circuit103according to the present embodiment, the voltage at which the generation of the drive pulse of the step-down circuit102stops is adjusted by using an external signal. In the Vdd dependence generation circuit103, one or both of the number of stages in the inverter chain131that determines the leading edge of the negative pulse and that has the small voltage dependence and the number of stages in the inverter chain132that determines the trailing edge of the negative pulse and that has the large voltage dependence may be switched from the outside. In the Vdd dependence generation circuit103, the width of the negative pulse to be outputted is thereby changed and, as a result, the voltage at which the pulse disappears is adjusted.

FIG.15is a configuration diagram of the SRAM according to Embodiment 4.FIG.15is an example in which the number of stages in the inverter chain132having the large voltage dependence is adjusted in three levels. The Vdd dependence generation circuit103according to the present embodiment includes inverter chains136and137in addition to the inverter chains131and132. Each of the inverter chains136and137is an example of a “fourth inverter”. The Vdd dependence generation circuit103also includes selectors401to403. The Vdd dependence generation circuit103also includes the NAND circuit133.

FIG.16is a circuit diagram of the selectors. Each of the selectors401to403is in a conductive state when a signal inputted in to an SEL terminal is H, and is in a cut-off state when the signal is L. For example, the inputs into the SEL terminals of the selectors401to403may be, as signals, SEL[0:2] that are 3-bit signals. In this case, the SEL[0:2] signals in which the input to the selector corresponding to the stage number to be selected is H and the inputs to the other selectors are L are inputted into the selectors401to403. This switches the width of the negative pulse, for example, the voltage at which the negative pulse disappears, in the Vdd dependence generation circuit103.

An example of setting the width of the negative pulse is described. Description is given assuming that, among SEL[0:2] that are 3-bit signals, a signal inputted into the selector401is SEL[0], a signal inputted into the selector402is SEL[1], and a signal inputted into the selector403is SEL[2]. As for the width of the negative pulse outputted from the Vdd dependence generation circuit103, one of the selectors401to403whose SEL terminal receives H becomes conductive. The combined number of stages in the inverter chains132and136that is selected when SEL[1] is set to H is set to a value obtained based on a manufacturing variation center value. The number of stages in the inverter chain132that is selected when SEL[0] is set to H is smaller than the number of stages selected when SEL[1] is set to H. The number of stages in the inverter chain137that is selected when SEL[2] is set to H is larger than the number of stages selected when SEL[1] is set to H.

In this case, if the voltage at which the assist is canceled is deviated from the center value due to manufacturing variation and, for example, the assist is canceled at voltage at which the execution of assist is still preferable, SEL[2] is set to H to increase the pulse width. If the assist is not canceled though the assist does not have to be executed, SEL[0] is set to H to reduce the pulse width. Selecting the selectors401to403as described above allows the SRAM10according to the present embodiment to achieve appropriate assist even when manufacturing variation occurs.

Next, Embodiment 5 is described. Assume a case where the SRAM10that is described in Embodiment 4 and whose assist cancel voltage is adjustable is used. In this case, if the cancel voltage is deviated from the center value due to manufacturing variation, it is preferable to correct this deviation. Accordingly, in the present embodiment, a test is performed by using a test circuit50in which a replica of the SRAM10is mounted, and if the cancel voltage is deviated from the center value due to manufacturing variation, an adjustment amount for correcting the deviation is determined and reflected in the actual SRAM10. In the following description, description of the function of each of the already-described parts is omitted.

FIG.17is a configuration diagram including an LSI tester, a test circuit, and a pulse width setting circuit according to Embodiment 5. In the present embodiment, an LSI tester53, the test circuit50, and a pulse width setting circuit51are provided. In this example, the SRAM10has the configuration illustrated inFIG.15.

When the cancel voltage is deviated from the center value due to manufacturing variation in use of the SRAM10described in Embodiment 4, the LSI tester53, the test circuit50, and the pulse width setting circuit51adjust the timing of assist to correct this deviation. The test circuit50checks the deviation from the center value of the pulse disappearance voltage, for example, the assist cancel voltage of the Vdd dependence generation circuit103built in the SRAM10. The pulse width setting circuit51stores a setting of optimal pulse width obtained from a result of a test by the test circuit50, and distributes values of this setting to the SEL terminals of the selectors401to403in the Vdd dependence generation circuit103included in the SRAM10ofFIG.15.

The LSI tester53comprehensively controls various tests in the LSI1. For example, the LSI tester53comprehensively controls tests related to the SRAM10by the test circuit50and the pulse width setting circuit51.

FIG.18is a configuration diagram of the test circuit according to Embodiment 5. As illustrated inFIG.18, the test circuit50includes a Vdd dependence generation circuit replica501obtained by making minimum circuit modifications and minimum layout modifications associated therewith to the Vdd dependence generation circuit103built in the SRAM10illustrated inFIG.15. Using the Vdd dependence generation circuit replica501may minimize deviations of the characteristics between the test circuit50and the Vdd dependence generation circuit103of the SRAM10. The test circuit50includes NAND circuits511and512, inverters513to515, dynamic gates516to518, and flip-flops521to523.

The Vdd dependence generation circuit replica501includes an inverter chain502in which the voltage dependence of the delay is small and inverter chains503to505in which the voltage dependence of the delay is large. Each of the inverter chains502,504and505has an even number of stages, and the inverter chain503has an odd number of stages. A signal from an EN′ terminal of the inverter chain502determines a leading edge of a negative pulse to be generated. Signals outputted from an ENX′0terminal, an ENX′1terminal, and an ENX′ terminal of the inverter chains503to505determine a trailing edge of the negative pulse to be generated.

The Vdd dependence generation circuit replica501also includes selectors506to508and a NAND circuit509. Each of the selectors506to508has, for example, the circuit configuration illustrated inFIG.16. The test circuit50including the Vdd dependence generation circuit replica501corresponds to an example of a “test execution unit”.

In the Vdd dependence generation circuit103illustrated inFIG.15, the coupling of the output terminals of the inverter chains132,136, and137is switched with the selectors401to403to input the signal into one NAND circuit133, and one negative pulse is thereby generated. Meanwhile, in the Vdd dependence generation circuit replica501, the EN′ terminal is commonly coupled to one input terminals of the NAND circuits509,511, and512. The ENX′0terminal is coupled to the other input terminal of the NAND circuit509, the ENX′1terminal is coupled to the other input terminal of the NAND circuit511, and the ENX′2terminal is coupled to the other input terminal of the NAND circuit512. The NAND circuits509,511, and512thereby generate three negative pulses varying in width. Desirably, the NAND circuits509,511, and512have the same shape. Outputs of the NAND circuits509,511, and512are converted to positive pulses in the inverters513to515, respectively, and the positive pulses are inputted into the dynamic gates516to518.

Each of the dynamic gates516to518has, for example, the circuit configuration illustrated inFIG.9. The signals S[2:0] outputted from the dynamic gates516to518are inputted into data terminals of the flip-flops521to523that are positive-edge triggered D-type flip-flops in which a scan function is implemented. For example, the flip-flop521has a circuit configuration illustrated inFIG.19.FIG.19is a diagram illustrating an example of the circuit configuration of the flip-flop mounted in the test circuit.

FIG.20is a diagram illustrating an example of test patterns in Embodiment 5.FIG.21is a timing chart of the test patterns in Embodiment 5. An operation of the test circuit50is described with reference toFIGS.20and21. In a pattern #0, the PC terminals of the dynamic gates516to518change as illustrated inFIG.21due to the negative pulse in the precharge line PC denoted by “N” inFIG.20. The signals S[2:0] outputted from the dynamic gates516to518are thereby precharged to H. The signals S[2:0] precharged to H are taken in from D terminals of the respective flip-flops521to523due to positive pulses at CLK terminals of the respective flip-flops521to523denoted by “P” inFIG.20, and are all initialized to H. Next, in a test pattern #1, the EN terminal of the inverter chain502in the Vdd dependence generation circuit replica501changes from L to H. As illustrated inFIG.19, negative pulses are thereby generated in the outputs of the NAND circuits509,511, and512depending on the voltage. The negative pulses are inverted by the inverters513to515, and are inputted into the EN terminals of the dynamic gates516to518. At this time, the output of the dynamic gate in which the pulse is generated among the dynamic gates516to518change from H to L. Results of the pulse generation from the dynamic gates516to518are taken in by the respective flip-flops521to523illustrated inFIG.21due to the positive pulses at the CLK terminals of the respective flip-flops521to523. Next, in patterns #2and #3, SM terminals of the respective flip-flops521to523are set to 1 as illustrated inFIG.21, and the flip-flops521to523are set to a scan shift mode. Each time the positive pulses are inputted into the CLK terminals, the flip-flops521to523sequentially output the taken-in results of pulse generation from SO terminals. Repeating the above test while changing the voltage allows the test circuit50to obtain the number of stages in the inverter chains503to505at which the negative pulse outputted by the Vdd dependence generation circuit replica501disappears. For example, the test circuit50may obtain a correlation between the voltage and the setting of SEL[2:0] in the selectors506to508.

FIG.22is a diagram illustrating an example of test results in Embodiment 5.FIG.22illustrates a table of values of the signals S[2:0] outputted from the dynamic gates516to518when a range of measurement voltage from minimum voltage Vmin to Vmax is divided into nine levels of V [0:8] and the test pattern #1is run at each voltage level, the sets of values for the respective voltage levels arranged in ascending order of voltage. In the table ofFIG.22, an output L indicates that a pulse has been generated, and an output H indicates that no pulse has been generated. The maximum voltage at which execution of assist is preferable is a standard value presented by a semiconductor manufacturer based on manufacturing variation and the number of mounted memory cells100. In this example, the maximum voltage at which execution of assist is preferable is set to the value V[2] two steps above Vmin. For example, a range541is a voltage range in which execution of assist is preferable. The minimum voltage at which no assist is executed is set to a value obtained by subtracting the potential difference by which the bit line Bit is stepped down from Vss by the assist, from the maximum rated voltage that is a specification of the semiconductor manufacturer. In this example, the minimum voltage at which no assist is executed is set to the value V[6] two steps below Vmax. For example, a range542is a voltage range in which no assist is executed.

In this case, such a setting that the test results are L in the voltage range V[2:0] and are H in the voltage range V[8:6] is preferable as the setting for executing the assist. In this example of test results, the signals S[0] and S[1] satisfy this condition. Since power consumption and stress on the element are smaller in the case where the cancel of the assist with the voltage increase is performed earlier, the signal S[0] is the optimal condition. Accordingly, in this example of test result, setting SEL[0] to H is optimal for the signals to be inputted into the selectors401to403of the Vdd dependence generation circuit103.

FIG.23is a configuration diagram illustrating an example of the pulse width setting circuit. In the pulse width setting circuit51according to the present embodiment, each of FUSE elements551to553and a corresponding one of reading circuits554to556form a group, and the pulse width setting circuit51includes as many groups as the number of selection signals of the selectors401to403of the Vdd dependence generation circuit103illustrated inFIG.15. Since the Vdd dependence generation circuit103illustrated inFIG.15performs selection with 3 bits of SEL[2:0] that are signals inputted into the selectors401to403, an example for 3 bits will be described in this section. The setting, obtained by the test circuit50, of SEL[2:0] that are signals to be inputted into the Vdd dependence generation circuit103is written into the FUSE elements551to553. Each of the reading circuits554to556outputs H when the corresponding one of coupled FUSE elements551to553is broken by the writing of the setting, and outputs L when the corresponding one of coupled FUSE elements551to553is not broken. For example, laser fuses, electric fuses, or the like are used as the FUSE elements551to553. For example, the reading circuits554to556include circuits that determine presence or absence of breakage by causing currents to flow through the FUSE elements551to553for a short period just after power on, and store results of the determination in latches, or the like.

FIG.24is a flowchart of operations of the test circuit and the pulse width setting circuit according to Embodiment 5. A flow of the operations of the test circuit50and the pulse width setting circuit51according to the present embodiment is described next with reference toFIG.24. The case where the Vdd dependence generation circuit103performs selection with 3 bits of SEL[2:0] that are signals inputted into the selectors401to403is described as an example. Hereinafter, the signal of each bit is represented by S[n] (n=0, 1, or 2).

At the start of the test, the LSI tester53sets the voltage V of the power supply to Vmin (step S201).

The test circuit50then runs, for example, the predetermined test pattern illustrated inFIG.18once (step S202).

Next, the LSI tester53determines whether or not the voltage V of the power supply is Vmax or higher (step S203). When the voltage V is below Vmax (step S203: No), the LSI tester53steps up the voltage V of the power supply by a predetermined step (V=V+step) (step S204). The processing then returns to step S202.

Meanwhile, when the voltage V is Vmax or higher (step S203: Yes), the LSI tester53collects the test results and obtains the test results as illustrated inFIG.20(step S205).

Next, the LSI tester53obtains the number L[n] of L and the number H[n] of H in SEL[n] (step S206). For example, the LSI tester53stores the number of pulses generated in each output, for example, the number of outputs of L in each signal S[n], across all voltage levels V, as a variable L[n] on a tester program. The LSI tester53also stores the number of times the pulse is not generated, for example, the number of outputs of H, as a variable H[n] on the tester program.

Appropriate pulse conditions are H[n]≥HP and L[n]≥LP, where LP is the number of steps of the voltage range in which execution of assist is preferable as illustrated in the range541ofFIG.20, and HP is the number of steps of the voltage range in which no assist is executed as illustrated in the range542.

The LSI tester53sets n=0 (step S207). Next, the LSI tester53determines whether or not n is 2 or smaller (step S208). When n is larger than 2 (step S208: No), the LSI tester53determines that the tested SRAM10is defective (step S209), and terminates the test.

Meanwhile, when n is 2 or smaller (step S208: Yes), the LSI tester53determines whether or not H[n]≥HP and L[n]≥LP are satisfied (step S210). When at least one of conditions of H[n] being smaller than HP and L[n] being smaller than LP is satisfied (step S210: No), the LSI tester53increments n by one (step S211), and returns to step S208.

Meanwhile, when H[n]≥HP and L[n]≥LP are satisfied (step S210: Yes), the LSI tester53determines that the optimal width of the negative pulse is achieved with S[n] at that point, and sets k=n by setting S[k] to be set to H to S[n] at that point (step S212).

Next, the LSI tester53performs writing to the pulse width setting circuit51such that S[k] is set to H (step S213). One of the fuse elements551to553in the pulse width setting circuit51corresponding to S[k] is thereby broken. The optimal pulse width is thus set for the Vdd dependence generation circuit103of the SRAM10.

The LSI tester53then performs a normal LSI test (step S214). The LSI tester53performs pass/fail determination of the SRAM10for which the setting has been performed, based on test results (step S215).

As described above, the test circuit and the pulse width setting circuit according to the present embodiment determine the optimal pulse width for the SRAM by using the replica of the Vdd dependence generation circuit mounted in the SRAM, and determine the input of signals to the selectors such that the determined pulse width is set. Accordingly, it is possible to automatically correct the assist cancel voltage to the optimal voltage without concerning about the deviation of the assist cancel voltage from the center value due to manufacturing variation.

Next, Embodiment 6 is described. In Embodiment 5, the standard value presented by the semiconductor manufacturer based on the number of mounted memory cells100and the manufacturing variation is used as the maximum voltage at which the execution of assist is preferable. This standard value includes a margin to cover variation of a final center of the memory cell100, and the assist is excessive depending on an actual final center value of the memory cell100. Accordingly, it is more preferable to use setting that matches the actual finish of the memory cell100for the assist.

The pulse width setting circuit51according to the present embodiment is different from that in Embodiment 5 in that the pulse width of the Vdd dependence generation circuit103of the SRAM10may be changed by scan shift.FIG.25is a configuration diagram of the pulse width setting circuit according to Embodiment 6. In the following description, description of the function of each of the already-described parts is omitted.

In the pulse width setting circuit51, outputs of the flip-flops521to523, corresponding to SEL[2:0] that are the signals inputted into the selectors401to403of the Vdd dependence generation circuit103illustrated inFIG.15, are coupled as follows. The output of the flip-flop523is coupled to an input of the flip-flop522, and the output of the flip-flop522is coupled to an input of the flip-flop521. Accordingly, every time the positive pulse is inputted into the CK terminal, data inputted from the SI terminal is stored in the flip-flop523, the flip-flop522, and the flip-flop521in this order by scan shift.

FIG.26is a flowchart of operations of a test circuit and the pulse width setting circuit according to Embodiment 6. A flow of the operations of the test circuit50and the pulse width setting circuit51according to the present embodiment is described next with reference toFIG.26. The case where the Vdd dependence generation circuit103performs selection with 3 bits of SEL[2:0] that are signals inputted into the selectors401to403is described as an example. Hereinafter, the signal of each bit is represented by S[n] (n=0, 1, or 2).

At the start of the test, the LSI tester53sets the voltage V of the power supply inputted into the test circuit50to Vmin (step S301).

The test circuit50then runs, for example, the predetermined test pattern illustrated inFIG.18once (step S302).

The pulse width setting circuit51performs initialization by setting SEL[2:n] of the Vdd dependence generation circuit103built in the SRAM10to 0 (step S303).

The test circuit50then sets n in SEL[n] to 0 (step S304).

The test circuit50then sets SEL[n] to H (step S305).

Next, the test circuit50writes SEL[2:0] to the pulse width setting circuit51by scan (step S306). A signal in which SEL[n] is set to H is thereby inputted in SEL[2:n] of the Vdd dependence generation circuit103built in the SRAM10.

The LSI tester53then executes an SRAM function test of the SRAM10(step S307).

The test circuit50determines whether n is equal to or greater than 2 which is the maximum number (step S308). When n is smaller than 2 (step S308: No), the pulse width setting circuit51performs initialization by setting SEL[2:n] of the Vdd dependence generation circuit103built in the SRAM10to 0 (step S309).

Next, the test circuit50increments n in SEL[n] by one (step S310). The test circuit50then returns to step S305.

Meanwhile, when n is 2 or larger (step S308: Yes), the test circuit50determines whether or not the voltage V of the power supply is Vmax or higher (step S311). When the voltage V is below Vmax (step S311: No), the LSI tester53steps up the voltage V of the power supply by a predetermined step (V=V+step) (step S312). The processing then returns to step S302.

Meanwhile, when the voltage V is Vmax or higher (step S311: Yes), the test circuit50collects the test results (step S313).FIG.27is a diagram of an example of the test results obtained in Embodiment 6. For example, the test circuit50obtains a test result601and an SRAM function test result602obtained by running the test pattern as illustrated inFIG.27. As illustrated inFIG.27, the test result601obtained by running the test pattern is similar to the test result obtained in Embodiment 5. A range603in the test result601is a voltage range in which no assist is executed. Meanwhile, the SRAM function test result602illustrates information collected for each voltage step in which a result of determination of whether or not the function of the SRAM10in each pulse width setting has normally operated is represented by P (pass) in the case where the function has normally operated and by F (fail) in the case where the function has failed to operate. In this case, the pulse width for which F is registered in the SRAM function test result602is not suitable for use.

Conditions for an appropriate pulse width obtained from the test results inFIG.27are such conditions that the function of the SRAM10operates normally at all voltage steps, and no pulse is generated in the voltage range in which no assist is executed. In the case ofFIG.27, signals that satisfy these conditions are the signals S[1] and S[2]. Out of these signals, the signal S[1] having a narrow pulse width is optimal from the viewpoint of reducing power and stress to the memory cell100. The LSI tester53thus executes calculation for obtaining the optimal pulse width as described below.

Next, the LSI tester53counts the number of times no pulse is generated in each output, for example, the number of H in each SEL[n] in the test result601, across all voltage levels from the test results obtained by the test circuit50, and stores the number as H[n] (step S314).

The LSI tester53counts the number of F in SEL[n] in the SRAM function test result602, and stores the number as F[n] (step S315).

When the number of voltage steps in which no assist is executed is represented by HP as in Embodiment 5, the appropriate pulse conditions are H[n]≥HP and F[n]=0. In the case ofFIG.25, HP is 3. When there are a plurality of n satisfying these conditions, n with the smallest pulse width is optimal. Such n may be obtained by performing the determination from n=0 and selecting n satisfying the conditions first.

Next, the LSI tester53determines whether or not n is 2 or smaller (step S317). When n is larger than 2 (step S317: No), the LSI tester53determines that the tested SRAM10is defective (step S318), and terminates the test.

Meanwhile, when n is 2 or smaller (step S317: Yes), the LSI tester53determines whether or not H[n]≥HP and F[n]≥0 are satisfied (step S319). When at least one of conditions of H[n] being smaller than HP and F[n] being smaller than 0 is satisfied (step S319: No), the LSI tester53increments n by one (step S320), and returns to step S317.

Meanwhile, when H[n]≥HP and F[n]≥0 are satisfied (step S319: Yes), the LSI tester53determines that the optimal width of the negative pulse is achieved with S[n] at that point, and sets k=n by setting S[k] to be set to H to S[n] at that point (step S321).

At the activation of the LSI1, the pulse width setting circuit51sets SEL[k]=H in the Vdd voltage dependent circuit103of the SRAM10by scan (step S322). For example, a value of SEL[2:0] that gives the obtained optimal pulse width is stored in a read-only memory (ROM) or the like outside the LSI1, and is sent to the pulse width setting circuit51by a joint test action group (JTAG) or the like at the power on to perform the setting.

As described above, according to the method of Embodiment 6, it is possible to match the voltage at which execution of assist is preferable to the capability of the actual memory cell, instead of the standard value presented by the semiconductor manufacturer and including the margin. As a result, the power and the stress on the memory cell due to the assist may be thus suppressed to the minimum.

According to the method of the present embodiment, it is possible to test the SRAM while changing the voltage at which the assist is canceled. Accordingly, the setting matching the actual finish of the memory cell may be achieved. As a result, it is possible to set voltage at which power is saved most and the stress applied to the memory cell is minimized, as the voltage at which the assist is canceled.

Next, Embodiment 7 is described.FIG.28is a configuration diagram of a pulse width setting circuit according to Embodiment 7. A test circuit50according to the present embodiment is similar to the test circuit50illustrated inFIG.18.

In the pulse width setting circuit51, each of the FUSE elements551to553, a corresponding one of the reading circuits554to556, and a corresponding one of the flip-flops521to523form a group, and the pulse width setting circuit51includes as many groups as the number of selection signals of the selectors401to403of the Vdd dependence generation circuit103illustrated inFIG.15.

The flip-flops521to523are positive-edge triggered D-type flip-flops in which a scan function is implemented. Output terminals of the reading circuits554to556are coupled to data input terminals of the flip-flops521to523.

When the SM terminals of the flip-flops521to523are L, the flip-flops521to523obtain data read from the FUSE elements551to553. When the SM terminals of the flip-flops521and522are H, each of the flip-flops521and522takes in the output of the flip-flop522or523of the previous stage by scan shift.

FIG.29is a flowchart of operations of the test circuit and the pulse width setting circuit according to Embodiment 7. A flow of the operations of the test circuit50and the pulse width setting circuit51according to the present embodiment are described next with reference toFIG.29.

The LSI tester53, the test circuit50, and the pulse width setting circuit51execute processing of obtaining correlations of the power supply voltage with the pulse disappearance and the SRAM function test (step S401). For example, the LSI tester53, the test circuit50, and the pulse width setting circuit51execute the processing of steps S301to S311in the flow illustrated inFIG.26as specific processing corresponding to the processing of obtaining the correlations.

Next, the LSI tester53, the test circuit50, and the pulse width setting circuit51execute processing of determining SEL[2:0] that are the selection signals of the selectors401to403of the Vdd dependence generation circuit103(step S402). For example, the LSI tester53, the test circuit50, and the pulse width setting circuit51execute the processing of steps S313to S321in the flow illustrated inFIG.26as specific processing corresponding to the processing of determining SEL[2:0].

The pulse width setting circuit51then breaks the fuse element [k] corresponding to SEL[k] determined to be H among the fuse elements551to553(step S403).

According to the method of the present embodiment, it is possible to reflect the results of the SRAM function test performed for all pulse width settings and determine the optimal pulse width depending on the manufacturing variation. According to the method of the present embodiment, writing the determination result of the optimal pulse width to the FUSE element allows omitting of loading of the setting from an external ROM or the like at the time of system operation, and the operation cost may be suppressed.

Next, Embodiment 8 is described.FIG.30is a configuration diagram including a test circuit and a pulse width setting circuit according to Embodiment 8. In the present embodiment, the SRAM10illustrated inFIG.15is used in which the voltage at which the assist is canceled is adjustable, and the voltage at which the assist is canceled is set based on the results of the SRAM function test. In the present embodiment, a test and pulse width setting circuit801is provided.

FIG.31is a configuration diagram of the test and pulse width setting circuit. The test and pulse width setting circuit801detects a setting in which the negative pulse generated in the Vdd dependence generation circuit103built in the SRAM10disappears at each voltage level, and holds the detected setting. The test and pulse width setting circuit801sets the held setting as SEL[2:0] that are the signals for selecting the selectors401to403of the Vdd dependence generation circuit103built in each SRAM10.

The test and pulse width setting circuit801includes the Vdd dependence generation circuit replica501, the NAND circuits511and512, the inverters513to515, the dynamic gates516to518, XOR circuits811to813, and the flip-flops521to523. The Vdd dependence generation circuit replica501, the NAND circuits511and512, the inverters513to515, and the dynamic gates516to518perform operations similar to those in Embodiment 5.

One input terminals of the XOR circuits811to813are coupled to output terminals of the dynamic gates516to518, respectively. The other input terminal of the XOR circuit811is coupled to the output terminal of the dynamic gate517. The other input terminal of the XOR circuit812is coupled to the output terminal of the dynamic gate518. The other input terminal of the XOR circuit813is coupled to Vss.

The XOR circuit811outputs a signal S[0] that is an exclusive OR of signals P[0] and P[1] outputted from the dynamic gates516and517. The XOR circuit812outputs a signal S[1] that is an exclusive OR of signals P[1] and P[2] outputted from the dynamic gates517and518. The XOR circuit813outputs a signal S[2] that is an exclusive OR of Vss and the signal P[2] outputted from the dynamic gate518.

The flip-flops521to523take in the signals S[2:0] outputted from the respective XOR circuits811to813, respectively.

FIG.32is a diagram illustrating an example of a pulse disappearance setting detection pattern.FIG.33is a timing chart of the pulse disappearance setting detection pattern.

The test and pulse width setting circuit801runs a pattern #00in the pulse disappearance setting detection pattern820to clear the flip-flops521to523to 1. Next, the test and pulse width setting circuit801runs a pattern #01in the pulse disappearance setting detection pattern820to generate pulses to be taken into the flip-flops521to523. When each of the patterns #00and #01is run, in actual, the test and pulse width setting circuit801changes each signal at timings illustrated inFIG.31.

FIG.34is a diagram illustrating changes in internal signals in the case where the pulse disappearance setting detection pattern is run. The internal signals are the signals P[2:0] outputted from the dynamic gates516to518and the signals S[2:0] outputted from the XOR circuits811to813.

When the pulse disappearance setting detection pattern820is run while the power supply voltage is changed, the signals P[2:0] and S[2:0] change as illustrated inFIG.34. As described above, when the pulse width is reduced from P[2] to P[0] at each voltage level, H is outputted at a change point where the pulse disappears, from one of the XOR circuits811to813corresponding to the disappearance of the pulse, and L is outputted from the other XOR circuits. For example, the test and pulse width setting circuit801runs the pulse disappearance setting detection pattern820at voltage below the voltage at which no assist is executed, and this enables setting of the voltage at which the assist is canceled for the Vdd dependence generation circuit103depending on the voltage at which the pulse disappears. Then, when the SRAM10passes the SRAM function test by the LSI tester53, it is confirmed that there is no problem in canceling the assist at the set voltage in the SRAM10.

FIG.35is a flowchart of an operation of the test and pulse width setting circuit according to Embodiment 8. A flow of the operation of the test and pulse width setting circuit801according to the present embodiment is described next with reference toFIG.35.

At the start of the test, the LSI tester53sets the voltage V of the power supply to Vmin (step S501).

The test and pulse width setting circuit801then runs, for example, the predetermined pulse disappearance setting detection pattern820illustrated inFIG.32once (step S502). The test and pulse width setting circuit801thereby sets the Vdd dependence generation circuit103of the SRAM10such that the assist is canceled at the voltage V.

The LSI tester53executes the SRAM function test on the SRAM10with the cancellation of the assist at the voltage V set. The LSI tester53then determines whether or not the SRAM10passes the SRAM function test (step S503).

When the SRAM10passes the SRAM function test (step S503: Yes), the LSI tester53reduces the voltage V by voltage corresponding to a predetermined step (step S504). The processing then returns to step S502.

Meanwhile, when the SRAM10fails the SRAM function test (step S503: No), the LSI tester53sets voltage one step above the voltage V at that time, as Vpset that is optimal assist cancel voltage. For example, the LSI tester53sets Vpset=V+step (step S505). Next, the LSI tester53notifies the test and pulse width setting circuit801of Vpset.

The test and pulse width setting circuit801sets the voltage V to Vpset (step S506).

The test and pulse width setting circuit801then runs the pulse disappearance setting detection pattern820again (step S507), and resets the voltage at which the assist of the SRAM10is canceled, to Vpset.

The LSI tester53then executes a normal LSI test on the SRAM10(step S508). The LSI tester53performs pass/fail determination based on the result of the LSI test (step S509).

FIG.36is a flowchart of an operation of a system in which the SRAM according to Embodiment 8 is mounted. A flow of the operation of the system in which the SRAM10is mounted is described next with reference toFIG.36, the SRAM10subjected to the setting by the test and pulse width setting circuit801according to the present embodiment. The test and pulse width setting circuit801writes Vpset, determined in step S506of the flow ofFIG.35, to, for example, a ROM external to the LSI1.

The LSI1is activated by being powered on (step S511).

The LSI1reads Vpset from the external ROM by using an LSI activation program, and sets the voltage V to Vpset (step S512).

Next, the LSI1runs the pulse disappearance setting detection pattern820, and sets the voltage at which the assist is canceled, for the Vdd dependence generation circuit103of the SRAM10in the LSI1(step S513).

In the LSI1, the voltage V is returned to a normal setting without turning-off of the power supply (step S514). The LSI1then shifts to a normal operation (step S515).

As described above, the test and pulse width setting circuit according to the present embodiment determines the lower limit of the assist cancel voltage by gradually reducing the assist cancel voltage while performing the SRAM function test. The test and pulse width setting circuit may thereby set the lower limit of the voltage at which the assist is canceled, according to the finish of the memory cell at that time, without being restricted to the standard value presented by the semiconductor manufacturer. Accordingly, the power increase and the stress on the memory cell due to the assist may be suppressed to the minimum.