Capacitor of semiconductor device and manufacturing method for the same

The present invention generally relates to a capacitor of a semiconductor device and a method of manufacturing such capacitors that improve the processing yield and the reliability of device operation by forming the plate electrode from a p-type polysilicon, thereby improving device resistance to write operation failures resulting from concentration of holes in the plate electrode terminal during a data write operation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Generally, a storage electrode and a plate electrode are formed of an n-typed polysilicon layer doped with phosphorus ‘P’. FIG. 1 a is cross-sectional view illustrating a conventional capacitor electrode and FIG. 1 b is a cross-sectional view illustrating another conventional capacitor electrode. FIG. 2 a and FIG. 2 b are cross-sectional views illustrating depletion and accumulation phenomena of the conventional capacitor. FIG. 1 a is a conventional method of forming an electrode of a capacitor. A undoped polysilicon layer 10 is formed and then a P 2 O 5 film 12 is formed on the polysilicon layer 10 by exposing the polysilicon layer 10 to a gaseous doping source in a diffusion chamber. P of the P 2 O 5 film is diffused into the polysilicon layer, forming an n-typed polysilicon layers, and then the P 2 O 5 12 is removed. Here, a gas mixture of POCl 3 and O 2 is used as the doping source. FIG. 1 b illustrates another conventional method of forming an electrode of a capacitor. By performing Chemical Vapor Deposition process using a gas mixture of either SiH 4 and PH 3 or Si 2 H 6 and PH 3 or a combination thereof, a P-doped polysilicon layer 14 is formed. As shown in FIG. 2 a , an electrode of a capacitor 20 formed by the conventional method comprises a storage electrode 22 which is an n-type polysilicon layer, the main carrier of which is an electron, a plate electrode 24 separated by a dielectric film 26 . When a positive (&plus;) voltage is applied to the storage electrode 22 , a depletion of the main carrier occurs and a depletion region 28 is formed. Also, as shown in FIG. 2 b , when a positive voltage is applied to the plate electrode 24 , an electron accumulation occurs and an accumulation region 30 is formed. These characteristics of an operation of a capacitor are as follows: FIG. 3 is a cross-sectional view illustrating a “1” data write operation of the conventional capacitor, FIG. 4 is a cross-sectional view illustrating a “0” data write operation, and FIG. 5 is a capacitance graph in accordance with a bias voltage of the conventional capacitor. First, when storing a data “1” in a capacitor 20 , 0V is applied to a storage electrode 22 and—V ss /2 to a plate electrode 24 , and, as shown in FIG. 3 , more depletion occurs closer to the interface of the storage electrode 22 and the dielectric 26 . When storing a data “0” in the capacitor 20 , 0V is applied to the storage electrode 22 and &plus;V cc /2 to the plate electrode 24 . As a result, as shown in FIG. 4, a depletion region 28 is formed close to the interface of the plate electrode 24 with the dielectric 26 . As described above, when the impurity concentration is not fully saturated, the depletion phenomenon is intensified as the voltages applied to electrodes increase in electrodes of capacitor formed by the conventional method. As shown in FIG. 5 , when the amount of the impurity dose is small, the desired capacitance of approximately 25 fF cannot be obtained and write operation failures occur. There is a limit in increasing the amount of doping in order to prevent the depletions mentioned above. Because the lower storage electrode is formed with a higher aspect ratio during manufacturing process of plate electrodes, phosphorus, with its relatively lower turnover rate compared to Si, cannot move fully into the inside of the electrode, thereby decreasing doping concentration of electrodes actually formed. The problem described above cannot be overcome since the aspect ratio increases are necessary to maintain capacitance as devices become smaller and the distance between storage electrodes decreases. Hereafter, a capacitor of a semiconductor device and manufacturing method for the same will be explained in detail referring to the attached drawings. FIG. 6 is a cross-sectional view of a capacitor formed in accordance with the present invention. A capacitor comprises a storage electrode 42 formed of an n-type polysilicon layer, a plate electrode 44 formed of a p-type polysilicon layer separated by a dielectric film 46 . Since the main carriers of plate electrode 44 are holes as a result of forming plate electrode 44 of the capacitor 40 from a p-type polysilicon layer, holes are concentrated on the ends of the plate electrode and a capacitance does not decrease when 0V is applied to a storage electrode and &plus;V cc /2 to a plate electrode during the write operation of data “0” write to the capacitor. As a result, the reliability of “0” data write operation is improved. The p-type polysilicon layer is formed by doping B on a undoped polysilicon layer through ex-situ or in-situ methods. As an example of ex-situ method, there is provided a first method of ion-implanting B or BF 2 after forming an undoped polysilicon layer. There is provided a second method of forming an oxide film doped with B on the surface of the polysilicon layer by reacting B 2 H 6 , BF 3 or BCl 3 with O 2 , and then diffusing B from oxide film into the polysilicon layer. There is provided a third method for coating a liquid source such as BBr 3 or (CH 2 O) 3 B on the surface of a undoped polysilicon layer and then diffusing B into the polysilicon layer. Also, there is provided an in-situ method of forming a p-type polysilicon layer doped with B by reacting B 2 H 6 , BF 3 or BCl 3 with SiH 4 or Si 2 H 6 in a CVD device. As is apparent from the above description, in accordance with the present invention, a capacitor of a semiconductor device and manufacturing method for the same is provided by forming a plate electrode from a B-doped polysilicon layer, applying 0V to a storage electrode and &plus;V cc /2 to a plate electrode when “0” data is written, thereby preventing holes, which are the main carriers in the plate electrode, from being concentrated on the ends of plate electrode. Accordingly, it is possible to prevent the degradation of capacitance, and improve processing yield, and improve the reliability of device operation.