Group III-nitride based vertical power device and system

A vertical power device is disclosed, the device having a top side and a bottom side, and the device comprising (i) a substrate; (ii) a layered group III-Nitride based device stack formed atop the substrate; (iii) a first vertical group III-Nitride based device and a second vertical group III-Nitride based device formed in the group III-Nitride based device stack, wherein the first vertical group III-Nitride based device and the second vertical group III-Nitride based device are electrically connected; and (iv) a first vertical device isolation structure that isolates the first vertical group III-Nitride based device from the second vertical group III-Nitride based device. Also disclosed are a vertical power system integrating vertical power devices and a process for fabricating a vertical power device.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a non-provisional patent application claiming priority to European Patent Application No. 19153573.1 filed Jan. 24, 2019, the contents of which are hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure is directed, in general, to a vertical power device, and, more specifically, to a group III-Nitride based vertical power device. The present disclosure further relates to a vertical power device system and a fabrication process.

BACKGROUND

In recent years, the integration of power devices has seen increasing demand in electronic power applications due to the possibility of achieving small scale power systems with orders of magnitude increase in switching speeds. With the rise of popularity of new materials, such as group III-Nitride based materials, some of these limitations may be overcome. Gallium nitride (GaN) is one of the most common group III-Nitride based materials which offers drastic reduction in energy consumption, reduction in size, weight, and cost, and increase in power conversion performance. However, conventional technologies and methods still have their limitations in the integration of power devices, such as high cost and inefficiency.

Monolithic integration technology has enabled the fabrication of power devices with various GaN devices. Several research studies have reported on monolithic integration of GaN components. These studies described the use of an isolating substrate for isolating the power devices and the use of trenches for creating contacts to connect the power devices.

Furthermore, lateral devices have been used in such integration, wherein the contacts of the lateral devices are accessible from one side. However, for a vertical device the terminals of the devices which need to be interconnected can be located on opposite sides of the substrate, making integration of vertical devices less trivial.

Therefore, there is a need in the art to provide a more reliable and efficient device that integrates group III-Nitride based devices in the same vertical power device.

SUMMARY

The present disclosure provides an improved vertical power device and system which do not show one or more of the above-mentioned disadvantages.

Additional and alternative aspects of the disclosure may be understood from the following.

An aspect of the present disclosure provides a vertical power device having a top side and a bottom side, the vertical power device comprising (i) a substrate; (ii) a layered group III-Nitride based device stack formed atop the substrate, the group III-Nitride based device stack comprising a body layer of a first conduction type between a lower layer and an upper layer of a second conduction type; and (iii) a first vertical group III-Nitride based device and a second vertical group III-Nitride based device formed in the group III-Nitride based device stack wherein the first vertical group III-Nitride based device and the second vertical group III-Nitride based device are electrically connected, the first vertical group III-Nitride based device comprising a first top contact and a first bottom contact, and the second vertical group III-Nitride based device comprising a second top contact and a second bottom contact, the first and second top contacts being formed at the top side, and the first and second bottom contacts being formed at the bottom side.

The vertical power device further comprises a first vertical device isolation structure that isolates the first vertical group III-Nitride based device from the second vertical group III-Nitride based device. Such integration of high power and high speed switching devices on a single vertical power device has several advantages. As a result of forming the contacts of the vertical group III-Nitride based devices at the top and bottom of the vertical power device, the vertical group III-Nitride based devices may be efficiently integrated on the vertical power device, wherein the top and bottom contacts can be clearly located on opposite sides of the vertical power device.

In embodiments according to the present disclosure, the first vertical device isolation structure may extend through at least the group III-Nitride based device stack, and may extend further through any conductive parts of the substrate, stopping in an isolating part, e.g. a buried oxide in the case of SOI or in an isolating substrate. As a result, the vertical power device allows for easy isolation of parts of the first and second vertical III-Nitride based devices. The vertical power device may allow for efficient integration of two or more devices on the vertical power device, allowing for either parallel or serial connection of power devices of the same type (transistors) or different types (transistors and diodes).

In embodiments according to the present disclosure, the first vertical device isolation structure may be formed at least partially through the substrate. In this way, the bottom contacts of the first and second vertical group III-Nitride based devices can be isolated by means of the first vertical device isolation structure, possibly in combination with other means of isolation, such as isolating layers which may be comprised in the substrate. Therefore, the first vertical device isolation structure may provide reliable isolation of at least the bottom contacts, such as those of the first and second vertical group III-Nitride devices.

In embodiments according to the present disclosure, the electrical connection of the first and second vertical group III-Nitride based devices may comprise a first vertical deep via which extends from the top side up to at least the lower layer of the group III-Nitride based GaN device stack, and a first via isolation region which isolates the first vertical deep via from the first top contact, the upper layer, and the body layer, the first via isolation region being provided at least around the first vertical deep via in at least the upper layer and the body layer.

In embodiments according to the present disclosure, the electrical connection of the first vertical group III-Nitride based device and the second vertical group III-Nitride based device may further comprise a lateral interconnect which is formed at the top side over the first vertical device isolation structure, wherein the first vertical deep via electrically connects the lateral interconnect and at least the lower layer, and wherein the first isolation region further isolates the lateral interconnect.

As a result of this electrical connection through the structure, the vertical power device requires less packaging material and/or bondwires. Consequently, the electrical connection may reduce interconnection parasitics and switching transients which can improve the reliability of the vertical group III-Nitride based power devices and the efficiency of the vertical power device.

Furthermore, since the vertical power device allows for the expansion of monolithic integration from lateral planar devices to vertical devices, particularly, vertical group III-Nitride based devices, the vertical power device may achieve a more compact form factor and reduced overall price.

In embodiments according to the present disclosure, the first vertical deep via may extend from the lateral interconnect down to the first bottom contact of the first vertical group III-Nitride based device, such that the first and second vertical group III-Nitride based devices are connected in series. Such a series electrical connection allows for efficiently integrating vertical group III-Nitride based devices by electrically connecting the bottom side reference to the top side.

In embodiments according to the present disclosure, the first vertical deep via may be formed adjacent to the first vertical device isolation structure. As a result, the vertical power device can be processed using less material, and, therefore, achieve a more compact form factor.

In embodiments according to the present disclosure, at least one of the first and second top contact may be formed on the upper layer, wherein a body contact is connected to the at least one of the first and second top contact, the body contact being formed on the body layer. As a result, a more reliable connection can be formed on the body layer, which may improve the efficiency of the vertical power device. Therefore, the vertical power device may efficiently be able to handle high current and withstand high voltage.

In embodiments according to the present disclosure, the first and second vertical group III-Nitride based devices may be connected in parallel. The configuration of the top contacts and the bottom contacts on opposite sides of the vertical power device allows for efficient parallel connection of vertical group III-Nitride based devices. As a result, fewer interconnects may be used, leading to a more compact form factor and reduced overall price.

Another aspect of the present disclosure provides a vertical power system, as defined in the claims, integrating at least one of the vertical power devices described herein.

Another aspect of the present disclosure provides a method, as defined in the claims, for manufacturing a vertical power device as described herein.

DETAILED DESCRIPTION

The following descriptions are of example embodiments and are not considered limiting in scope. Any reference herein to the disclosure is not intended to restrict or limit the disclosure to exact features of any one or more of the example embodiments disclosed in the present specification.

Moreover, the terms top, bottom, over, under, and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. The terms so used are interchangeable under appropriate circumstances and the embodiments described herein can operate in other orientations than described or illustrated herein.

A first embodiment of a vertical power device100according to the disclosure will be described with reference toFIGS. 1A and 1B. The vertical power device100has a top side101aand a bottom side101band comprises a substrate102atop which a layered group III-Nitride based device stack104is formed.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIG. 1A, the group III-Nitride based device stack104comprises layers having a group III species and nitrogen. The group III species may include one or more elements in group III of the Periodic Table, including B, Al, Ga, In, or Tl. The III-Nitride layer can be a compound that includes multiple Group III elements. The group III-Nitride based device stack104may include layers comprising binary compounds such as AlN, InN, or GaN, ternary compounds such as AlxGa1-xN (0≤x≤1) or InxGa1-xN (0≤x≤1) quaternary compounds such as InxAlyGa1-x-yN (0≤x,y≤1) or quinary compounds such as GaxIn(1-x)AsySbzN(1-y-z)(0≤x,y,z≤1). Throughout this disclosure, we refer to the III-Nitride based device as a III-N device.

In embodiments according to the present disclosure, the III-N device stack104comprises a plurality of semiconductor layers having a body layer104bof a first conduction type between a lower layer104cand an upper layer104aof a second conduction type. The conduction types may be an n-type or a p-type and may be achieved using methods known in the art, such as doping. For example, the body layer104bmay be n-type, and the lower layer104cand the upper layer4amay be p-type. In another example, the body layer104bmay be p-type, and the lower layer104cand the upper layer104amay be n-type. Furthermore, the layers104a,104b,104cmay each comprise one or more layers. As shown inFIG. 1A, the lower layer may comprise two lower layers104cand104d. Furthermore, each of the lower layers104c,104dmay comprise one or more layers (not shown). The layers of the III-N device stack104may be undoped, unintentionally doped, or doped with donor or acceptor dopants. Methods for doping the layers of the III-N device stack are known in the art. The lower layer104dcan, for example, be a highly doped layer to form, for example, a low resistive contact. The doping concentration of the dopant in the lower layer104dmay be in the range of 1E18-5E19 cm−3. In some examples, the lower layer104cwill be lowly doped, so that a high off-state potential can be sustained over the layer. The doping concentration of the dopant in the lower layer104cmay be in the range of 1E15-1E17 cm−3. In some examples, the body layer104bwill be lowly doped, but with a doping concentration higher than that in the lower layer104c, so that the depletion layer does not extend too far into this layer. The doping concentration of the dopant in the body layer104bmay be in the range of 5E16-5E18 cm−3. In some examples, the upper layer104awill be highly doped to form, for example, a low resistive contact. The doping concentration of the dopant in the upper layer104amay be in the range of 1E18-5E19 cm−3. Furthermore, the doping concentration of the dopant in the upper layer104aand the lower layer104dmay be similar or different.

Furthermore, the plurality of semiconductor layers of the III-N device stack104may be epitaxially grown using methods known in the art, such as a process or processes based on molecular beam epitaxy, halide vapour phase epitaxy, physical vapour deposition, or chemical vapour deposition (CVD), such as metalorganic CVD (MOCVD). Other means of forming the layers of the III-N device stack104now known or later developed are contemplated herein as well. Furthermore, the III-N device stack104may further comprise one or more interlayers (not shown) interposed between the layers of the III-N device stack104. The one or more interlayers may comprise solely, or a combination of, hydrogen silsesquioxane (HSQ), silicon nitride (SiN), aluminium nitride (AlN), aluminium indium nitride (AlInN), titanium nitride (TiN), tantalum nitride (TaN), or aluminium gallium nitride (AlGaN). In some examples, the one or more interlayers may be of the same composition as that of the layer atop of which the one or more interlayers are formed, and may, for example, be GaN based. Furthermore, the one or more interlayers may be intrinsic (i.e., pure or undoped).

In embodiments according to the present disclosure, e.g. the embodiment shown inFIG. 1A, the plurality of semiconductor layers may further have a nucleation layer104eon top of which the lower layers104cand104dmay be formed, for instance on top of which the lower layer104dmay be formed. The plurality of semiconductor layers may further comprise the nucleation layer104eand a buffer layer104f. The nucleation layer104emay be formed on top of the substrate102. The nucleation layer104eis provided for growing the III-N device stack104on the substrate102. The nucleation layer104emay comprise one or more III-N compounds, which may be similar to the compounds comprised in the GaN device stack104. The nucleation layer104emay further comprise deep-level dopants, such as III-N compounds. The nucleation layer104emay further comprise ionized contaminants. A concentration of the deep-level dopants may be at least as high as a concentration of the ionized contaminants. Thus, the nucleation layer104emay be inducting or insulating. The plurality of semiconductor layers may further comprise a buffer layer104fformed atop the nucleation layer104e. The buffer layer104fmay be provided for, but not limited to, reducing defects and compensating stress in the vertical III-N device stack104due to lattice mismatch. Compounds comprised in the buffer layer104fare known in the art, such as high-temperature or low-temperature compounds, such as a combination of III-Nitride materials. The buffer layer104fmay also comprise one or more superlattices, or multiple layer structures with alternating layers of III-Nitride materials, e.g. for stress compensation. The resistivity and/or conductivity of the nucleation layer104eand/or the buffer layer104fcan be modified by using dopants.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIG. 1A, the substrate102may comprise a carrier layer102c. The carrier layer102cmay be an inducting carrier layer or an insulating carrier layer. Examples of an inducting carrier layer may be Si, SiC, or other inducting material known in the art. Examples of an insulating carrier layer may be highly resistive bulk GaN, poly-AlN, or any other way known in the art for insulating the carrier layer102c. The substrate102may further comprise a handling layer102datop of which the carrier layer102cis formed. The handling layer102dmay be provided for handling the vertical power device100.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIG. 1A, the layered III-N device stack104may further comprise one or more passivation layers. In particular, the layered III-N device stack104may comprise a first passivation layer103formed atop the upper layer104a. The first passivation layer103may be provided for protecting the III-N device stack104from environmental influences, such as electrical and chemical contaminants. The first passivation layer103may be provided for protecting at least the top side101aof the vertical power device100. Compounds comprised in the first passivation layer103are known in the art, such as aluminium oxide (Al2O3), titanium dioxide (TiO2), hafnium dioxide (HfO2), silicon oxide (SiO2), silicon nitride (Si3N4), silicon nitride/amorphous silicon (SiNx/a-Si), silicon nitride/silicon rich silicon nitride (SiNx/Si-rich-SiNx), and/or polyamides.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIG. 1A, the vertical power device100comprises a first vertical III-N device “Device1” and a second vertical III-N device “Device2” formed in the III-N device stack104. The first vertical III-N device comprises a first top contact111aand a first bottom contact111b, and the second vertical III-N device comprises a second top contact121aand a second bottom contact121b. The first and second top contacts111a,121aare formed at the top side101aof the vertical power device100, and the first and second bottom contacts111b,121bare formed at the bottom side101bof the vertical power device100. The first and second top contacts111a,121amay be formed by forming one or more front metallization layers. The first and second bottom contacts111b,121bmay be formed by forming one or more back metallization layers.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIG. 1A, the first top contact111aand the second top contact121amay extend into the III-N device stack104. Each of the first and second top contacts111a,121amay extend in one or more of the upper layer104a, the body layer104b, or the lower layer104c,104d. In some examples, at least one of the first and second top contacts111a,121ais formed on the upper layer104a. Furthermore, a first and second body contact111c,121cmay be connected to the at least one of the first and second top contacts111a,121a. In some examples, at least one of the body contacts111c,121cis formed in the body layer104b, and the corresponding top contact111a,121ais formed in the upper layer104a.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIG. 1A, the first bottom contact111band the second bottom contact121bmay be formed in the substrate102in the buffer layer104fand the nucleation layer104e, such that the bottom contacts111b,121bform an ohmic contact with the layered III-N device stack104, such as with the lower layer104d. The first bottom contact111band the second bottom contact121bmay be further formed in the lower layer104dforming an ohmic contact with the lower layer104d. As shown inFIG. 1A, the first and second bottom contacts111b,121bmay be formed in the substrate102and in contact with the lower layer104dof the III-N device stack104. The first and second bottom contacts111b,121bmay be formed by one or more metal conductors, which may be isolated from each other, or which may be electrically connected to each other via a conductive layer of the substrate, such as for example the handling layer102dor the carrier layer102c. In alternative embodiments, the first and second bottom contacts111b,121bmay be formed as a single bottom contact in the substrate102.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIGS. 1A and 1B, at least one of the first and second vertical III-N devices may further comprise a first and/or second gate112,122. InFIG. 1A, the gate(s)112,122may comprise a gate electrode112a,122aand a gate dielectric112b,122b. The gate(s)112,122may be formed on the lower layer104c, particularly the gate dielectric112b,122bmay be formed on the lower layer104c. The gate dielectric112b,122bis provided for electrically insulating the gate electrode112a,122afrom the vertical III-N device stack104. Other means of producing a discontinuity between the vertical III-N device stack104and the gate electrode112a,122acan be for using a Schottky contact, for example, or by having a gate electrode112a,122aformed on the body layer104b. A second passivation layer105may be formed atop the first passivation layer103which is formed atop the III-N device stack104. Furthermore, a third passivation layer106may be formed atop the second passivation layer105. The second and third passivation layers105,106may be similar to or different from the first passivation layer103.

In what follows, example ranges for thickness of each of layers in the vertical power device100will be provided. For the passivating dielectric layers103,105,106, the range can be in the order of 10 nm to 5 μm, such as in the order of 10 nm to 2 μm. For the upper layer104a, the range can be in the order of 100-500 nm. For the body layer104b, the range can be in the order of 200 nm to 1 μm. For the lower layer104c, the range can be in the order of 0.5-100 μm, the thickness and doping level of this layer will determine the breakdown of the component, e.g. assuming optimal doping level for a GaN drift, a thickness of 1 μm gives a theoretical maximum breakdown of ˜300V, for a thickness of 3 μm the breakdown voltage is ˜1 kV, and for 10 μm it is around 2.5 kV. For the lower layer104d, the range can be in the order of 1-10 μm. For the nucleation layer104e, the range can be in the order of 100-500 nm. For the buffer layer104f, the range can be in the order of 100 nm-2 μm. For the carrier layer102c, the range can be in the order of 100-2 μm. For the handling layer102d, the range can be in the order of 0.725-1.1 μm.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIG. 1A, the vertical power device100further comprises at least a first vertical device isolation structure117that isolates the first vertical III-N device from the second vertical III-N device. The first vertical device isolation structure117may be formed as a trench isolation module by recessing through at least the upper layer104a, the body layer104b, and the lower layer104c, extending to the lower layer104d. The first vertical isolation structure117may further extend through the first passivation layer103, may further extend through the second passivation layer105, and may further extend through the third passivation layer106. In some examples, the first vertical device isolation structure117may be formed as a deep trench isolation module by recessing further through at least the III-N device stack104such that direct connections through the layers of the layered III-N device stack104are interrupted. The first vertical device isolation structure117may further extend through at least part of the substrate102stopping in an isolating part of the substrate. As shown inFIG. 1A, the first vertical device isolation structure117may further extend into the substrate102, such as through any conductive parts of the substrate, e.g. the carrier layer102cwhich can be conductive, and stopping in an isolating part of the substrate, e.g. the handling layer102dwhich can be insulating. The first vertical device isolation structure117may further extend through the handling layer102d, such as if the handling layer102ddoes not have isolating properties. Alternatively, if the handling layer102ddoes not have isolating properties (i.e., is conductive), and if the first vertical device isolation structure117extends through parts of the substrate stopping in the handling layer102d, then the bottom contacts111b,121bmay be isolated from each other by other means known in the art, e.g. by depositing a dielectric in between the bottom contacts111b,121band the handling layer102d. The dielectric may be further deposited in between the bottom contacts111b,121band other parts of the substrate102thereby allowing the bottom contacts111b,121bto be electrically connected to the relevant layer(s) and isolated from each other.

The first vertical device isolation structure117is formed at least between the first and second vertical III-N devices to isolate at least their top and gate contacts from each other. The first vertical device isolation structure117may be further formed surrounding the first vertical III-N device and the second vertical III-N device, to isolate them from further devices. In embodiments, the first vertical device isolation structure117may isolate portions of one or more conductive layers of the substrate102and thus isolate the first bottom contact111band the second bottom contact121bfrom each other and/or further bottom contacts of further devices.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIG. 1A, the first and second vertical III-N devices, or parts thereof, may be electrically connected through any layer or layers in the vertical III-N device stack104and/or substrate102. Thus, the first vertical device isolation structure117may be provided for selectively connecting and/or insulating any layer or layers in the vertical III-N device stack104and/or substrate102. Other means of electrically connecting the first and second vertical III-N devices will be described in further detail below.

A second embodiment of a vertical power device200according to the disclosure will be described with reference toFIGS. 2A and 2B. The vertical power device200corresponds in many aspects and/or features to the vertical power device100of the first embodiment ofFIGS. 1A and 1B. Therefore, only the differences will be described in detail for the sake of brevity.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIGS. 2A and 2B, the vertical power device200comprises a first vertical III-N device “Device1,” a second vertical III-N device “Device2,” and a third vertical III-N device “Device3” formed in the III-N device stack204, which may comprise layers204a-204fwhich may be the same as layers104a-104fdescribed above, on top of substrate202, which may comprise layers202c-202dwhich may be the same as layers102c-102ddescribed above, and covered by one or more passivation layers203,205,206, which may be the same as layers103,105,106. The first vertical III-N device comprises a first top contact211aand a first bottom contact211b, the second vertical III-N device comprises a second top contact221aand a second bottom contact221b, and the third vertical III-N device comprises a third top contact231aand a third bottom contact231b. The first top and bottom contacts211a,211cand the second top and bottom contacts221a,221bmay be formed using metallization layers in the same manner as has been described for the contacts111a,111b,121a,121babove. The first vertical III-N device comprises a gate212, comprising a gate electrode212aand a gate dielectric212b, which may be formed in the same way as has been described for gates112,122above.

The vertical power device200comprises a first vertical device isolation structure217that isolates the first vertical III-N device from the second vertical III-N device. The third vertical III-N device may be isolated from the first and second vertical III-N devices by a second vertical device isolation structure227.

The third vertical III-N device may be formed in a similar manner as is described herein for the first or second III-N devices. The first, second, and third vertical III-N devices and their top, bottom, and/or gate contacts may be isolated or electrically connected in a manner similar to the isolation or electrical connections described elsewhere herein.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIGS. 2A and 2B, the vertical power device200may comprise homogeneous and/or heterogeneous vertical III-N devices. In other words, the first, second, and third vertical III-N devices may be similar or different. In embodiments, each of the first, second, and third vertical III-N devices may be one of a thyristor, transistor, power (intrinsic) diode, or Schottky diode.FIG. 1Ashows the vertical power device100which comprises two transistors. InFIG. 2A, the first, second, and third vertical III-N devices are respectively a transistor, a power diode (with the top contact221ain contact with the body layer204band using pn-junction, resp. np-junction204b-204c) and a Schottky diode (with the top contact231ain contact with the lower layer204cand forming a Schottky barrier therewith).

The substrate202may further comprise a buried oxide layer202bformed between the carrier layer202cand the handling layer202d. For example, the buried oxide layer202bcan comprise SiO2when the substrate is a SOI. The thickness of the buried oxide layer202bmay be in the range of 0.5-2 μm, such as 0.5-1.5 μm. The carrier layer202cmay comprise one or more layers, e.g. a carrier layer and a buried oxide layer as for the case of SOI.

The second vertical device isolation structure227may be formed in a manner as has been described above for the first vertical device isolation structure117, such that the first and second vertical device isolation structure217,227may be formed in a similar or different manner in the same vertical power device200. InFIG. 2A, the first and second vertical device isolation structures217,227may extend through the III-N device stack204and at least part of the substrate202. InFIG. 2B, the second vertical device isolation structure227may be formed around the second vertical III-N device and/or the third vertical III-N device, in a manner as has been described above for the first vertical device isolation structure117. The first and second vertical device isolation structures217,227may be formed in similar and/or different layers in the vertical power device200. In the embodiment shown inFIG. 2A, the first and the second vertical device isolation structures217,227are formed in all the layers of the vertical III-N device stack204and in the carrier layer202cextending to the buried oxide layer202b. In another example, the first vertical device isolation structure217may instead extend only in the layers of the vertical device stack204and not in the substrate202. In this example, the first and second bottom contacts211b,221bmay be electrically connected via the carrier layer202cof the substrate, whereas the third bottom contact231bmay be isolated from the second bottom contact221b.

A third embodiment of a vertical power device300according to the disclosure will be described with reference toFIGS. 3A and 3B. The vertical power device300corresponds in many aspects and/or features to the vertical power devices100,200of the first and second embodiments ofFIGS. 1A, 1B, 2A, and 2B. Therefore, only the differences will be described in detail for the sake of brevity.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIGS. 3A and 3B, the vertical power device300comprises a first vertical III-N device “Device1” and a second vertical III-N device “Device2,” formed in the III-N device stack304, which may comprise layers304a-304fwhich may be the same as layers104a-104fdescribed above, on top of substrate302, which may comprise layers302c-302dwhich may be the same as layers102c-102ddescribed above, and covered by one or more passivation layers303,305,306, which may be the same as layers103,105,106. Furthermore, the substrate302may further comprise a buried oxide layer (not shown) which may be the same as layer202b. The first vertical III-N device comprises a first top contact311aand a first bottom contact311b, the second vertical III-N device comprises a second top contact321aand a second bottom contact321b. The first and second vertical III-N devices respectively comprise first and second gates312,322. The gates each comprise a gate electrode312a,322aand a gate dielectric312b,322b, which may be formed in the same way as has been described for gates112,122above.

The vertical power device300comprises a first vertical device isolation structure317that isolates the first vertical III-N device from the second vertical III-N device. The vertical device isolation structure317may be formed in a manner as has been described above for the first vertical device isolation structure117,217.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIGS. 3A and 3B, the vertical power device300may further comprise a first lateral interconnect313which may be formed at the top side301aover the first vertical device isolation structure317. The first lateral interconnect313may be formed on the third passivation layer306at the top side301aof the vertical power device300. The first lateral interconnect313may be formed on the first or second passivation layers303,305, wherein part of the second and/or third passivation layers305,306may be recessed thereby allowing the first lateral interconnect313to be formed in the recessed part. The first lateral interconnect313extends at least partly over the second top contact321ato make electrical contact therewith.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIGS. 3A and 3B, the vertical power device300may further comprise a power metal316, which may be formed on the first top contact311a. The power metal316may extend through the second and third passivation layers305,306. Furthermore, a fourth passivation layer307may be formed on the third passivation layer306and partially over the power metal316and the first lateral interconnect313. As shown inFIG. 3A, the power metal316forms an upwards extension of the first top contact311aand the first lateral interconnect313forms an upwards extension of the second top contact321a.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIG. 3A, the vertical power device300may further comprise a first vertical deep via314which may be formed extending from the top side301aup to at least the lower layer304c,304dof the III-N device stack304, so as to electrically connect the first lateral interconnect318(and hence the top contact321aof the second device) to the respective lower layer304c,304d. The vertical power device300may further comprise a first via isolation region318which may be formed in the upper layer304aand body layer304b. The first via isolation region318may further extend through at least one of the passivation layers303,305,306. The first via isolation region318is provided for isolating the first lateral interconnect313and the first vertical deep via314from the conductive layers of the III-N stack and hence the first top contact311aand the gate312. As shown, the first via isolation region318may be formed around the first vertical deep via314in at least the upper layer304aand the body layer304b. Furthermore, the first lateral interconnect313may extend from over the second top contact321ato an area over the first via isolation region318in between the first and second top contacts311a,321a. As shown inFIG. 3A, the first vertical deep via314and/or the first via isolation region318may be formed adjacent to the first vertical device isolation structure317in between the first and second top contacts311a,321a. The first vertical deep via314forms an electrical connection between the first lateral interconnect313and the lower layer304c,304d. Thus, the second top contact321amay be electrically connected to at least the lower layer304c,304dof the III-N device stack304. Such a connection may be used to determine a voltage reference from the first vertical III-N device.

A fourth embodiment of a vertical power device400according to the disclosure will be described with reference toFIGS. 4A and 4B. The vertical power device400corresponds in many aspects and/or features to the vertical power devices100,200,300of the first, second, and third embodiments ofFIGS. 1A, 1B, 2A, 2B, 3A and 3B. Therefore, only the differences will be described in detail for the sake of brevity.

In embodiments according to the present disclosure, e.g. the embodiment shown inFIGS. 4A and 4B, the vertical power device400comprises a first vertical III-N device “Device1” and a second vertical III-N device “Device2,” formed in the III-N device stack404, which may comprise layers404a-404dwhich may be the same as layers104a-104ddescribed above, on top of substrate402, which may comprise layers402c-402dwhich may be the same as layers102c-102ddescribed above, and covered by one or more passivation layers403,405,406,407which may be the same as layers303,305,306,307. Furthermore, the substrate402may further comprise a buried oxide layer (not shown) which may be the same as layer202b. The first vertical III-N device comprises a first top contact411aand a first bottom contact411b, and the second vertical III-N device comprises a second top contact421aand a second bottom contact421b. The first and second vertical III-N devices respectively comprise first and second gates412,422. The gates each comprise a gate electrode412a,422aand a gate dielectric412b,422b, which may be formed in the same way as has been described for gates112,122above.

In the same way as in the embodiment ofFIGS. 3A-B, the vertical power device400comprises a first vertical device isolation structure417that isolates the first vertical III-N device from the second vertical III-N device. The vertical device isolation structure417may be formed in a manner as has been described above for the first vertical device isolation structure117,217.

In the same way as in the embodiment ofFIGS. 3A-B, the vertical power device400comprises a first lateral interconnect413over the first vertical device isolation structure417. The first lateral interconnect413extends at least partly over the second top contact421ato make electrical contact therewith. In the same way as in the embodiment ofFIGS. 3A-B, the vertical power device400comprises a power metal416, formed on the first top contact411a.

Similar to the embodiment ofFIGS. 3A-B, the vertical power device400comprises a first vertical deep via414. In the embodiment ofFIGS. 4A-B, the via414extends from the first lateral interconnect413at least up to a conductive layer of the substrate402and/or, as shown, up to the first bottom contact411b. In this way, the first vertical deep via414forms an electrical connection between the first lateral interconnect413and the first bottom contact411b. Consequently, the second top contact421amay be electrically connected to the first bottom contact411b. In this way, the first vertical III-N device and the second vertical III-N device may be electrically connected in a series connection (i.e. their drain-source paths are connected in series).

In the same way as in the embodiment ofFIGS. 3A-B, the vertical power device400comprises a first via isolation region418formed in the upper layer404aand body layer404b, for isolating the first lateral interconnect413and the first vertical deep via414from the conductive layers of the III-N stack and hence the first top contact411aand the gate412.

In embodiments according to the present disclosure (not shown), e.g. based on the embodiment shown inFIGS. 1A-B, the first vertical III-N device and the second vertical III-N device may be connected in parallel. The parallel connection may comprise a top lateral connection of the top contacts111a,121aand a bottom lateral connection of the bottom contacts111b,121b. In order to facilitate the top lateral connection, the first III-N device may be provided in mirror image compared to what is shown inFIGS. 1A-B, i.e. with the first top contact112aadjacent to the first vertical device isolation structure117in between the devices.

The above described embodiments for electrically connecting the first and second vertical III-N devices in series or parallel are in no way limiting to other means of connecting the first and second vertical III-N devices. The means described in this disclosure and other means known in the art may be used to electrically connect the first and second vertical III-N devices, such as, but not limited to, electrically connecting the second top contact to the first gate, the second gate to the first gate, the second gate to the first bottom contact, etc.

A fifth embodiment of a vertical power device500according to the disclosure will be described with reference toFIGS. 5A and 5B. The vertical power device500corresponds in many aspects and/or features to the vertical power devices100,200,300,400of the first, second, third, and fourth embodiments ofFIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B. Therefore, only the differences will be described in detail for the sake of brevity.

In the same way as inFIGS. 2A-B, the vertical power device500comprises a first vertical III-N device “Device1,” a second vertical III-N device “Device2,” and a third vertical III-N device “Device3” formed in the III-N device stack504, which may comprise layers504a-504fwhich may be the same as layers104a-104fdescribed above, on top of substrate502, which may comprise layers502c-502dwhich may be the same as layers202c-202ddescribed above, and covered by one or more passivation layers503,505,506,507which may be the same as layers303,305,306,307. The first vertical III-N device comprises a first top contact511aand a first bottom contact511b, the second vertical III-N device comprises a second top contact521aand a second bottom contact521b, and the third vertical III-N device comprises a third top contact531aand a third bottom contact531b. The first vertical III-N device comprises a gate512, comprising a gate electrode512aand a gate dielectric512b, which may be formed in the same way as has been described for gates112,122above. The first, second, and third vertical III-N devices are respectively a transistor, a power diode (with the top contact521ain contact with the body layer504band using pn-junction, resp. np-junction504b-504c), and a Schottky diode (with the top contact531ain contact with the lower layer504cand forming a Schottky barrier therewith).

In the same way as inFIGS. 2A-B, the vertical power device500comprises a first vertical device isolation structure517that isolates the first vertical III-N device from the second vertical III-N device. The third vertical III-N device is isolated from the first and second vertical III-N devices by a second vertical device isolation structure527.

Similar toFIGS. 4A-B, the devices are connected in series, i.e. the first bottom contact511bis connected to the second top contact521a, and the second bottom contact522bis connected to the third top contact531a. The series connection is provided by first, resp. second lateral interconnects513,523and first, resp. second vertical deep via514,524, the latter being isolated from the conductive layers of the III-N stack by means of first, resp. second via isolation regions518,528.

In embodiments according to the present disclosure, at least one of the first, second, and third vertical III-N devices may further comprise a first, second, and/or third gate. For example, if the first, second, and third vertical III-N devices are transistors, then these transistors may comprise a first, second, and third gate.

The above described embodiments for electrically connecting at least two of the first, second, and third vertical III-N devices in series or parallel are in no way limiting to other means of connecting the first and second vertical III-N devices. The means described in this disclosure and other means known in the art may be used to electrically connect at least two of the first, second, and third vertical III-N devices, such as, but not limited to, electrically connecting the third top contact to the second gate, the third gate to the second gate, the third gate to the second bottom contact, etc.

A sixth embodiment of a vertical power device600according to the disclosure will be described with reference toFIGS. 15A and 15B. The vertical power device600corresponds in many aspects and/or features to the vertical power devices100,200,300,400,500of the first, second, third, fourth, and fifth embodiments ofFIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B, 5A, and 5B. Therefore, only the differences will be described in detail for the sake of brevity.

In the same way as inFIGS. 2A-B, the vertical power device600comprises a first vertical III-N device “Device1,” a second vertical III-N device “Device2,” and a third vertical III-N device “Device3” formed in the III-N device stack604, which may comprise layers604a-604fwhich may be the same as layers104a-104fdescribed above, on top of substrate602, which may comprise layers602b-602dwhich may be the same as layers202b-202ddescribed above, and covered by one or more passivation layers603,605,606which may be the same as layers103,105,106. The first vertical III-N device comprises a first top contact611aand a first bottom contact611b, the second vertical III-N device comprises a second top contact621aand a second bottom contact621b, and the third vertical III-N device comprises a third top contact631aand a third bottom contact631b. The first vertical III-N device comprises a gate612, comprising a gate electrode612aand a gate dielectric612b, which may be formed in the same way as has been described for gates112,122above. The first, second, and third vertical III-N devices are respectively a transistor, a power diode (with the top contact621ain contact with the body layer604band using pn-junction, resp. np-junction604b-604c), and a Schottky diode (with the top contact631ain contact with the lower layer604cand forming a Schottky barrier therewith).

InFIGS. 15A-B, the vertical power device600comprises a first vertical device isolation structure617that isolates the first vertical III-N device from the second vertical III-N device. The third vertical III-N device is isolated from the first and second vertical III-N devices by a second vertical device isolation structure627. As shown inFIGS. 15A-B, the first vertical device isolation structure617and/or the second vertical isolation structure627are formed extending from the top of the vertical power device600to the lower layer604d. In the embodiment shown inFIG. 15A-B, the first, second, and third bottom contacts611b,621b,631bare electrically connected through the lower layer604d, i.e. the vertical devices share a common drain.

The vertical power devices according to the disclosure, e.g. the vertical power devices100,200,300,400,500,600described above, can be integrated into vertical power systems, comprising an electrical power circuit and one or more of the vertical power devices, connected to other components via the respective top and bottom contacts. In embodiments, multiple ones of the vertical power devices may be arranged adjacent to each other, such that their top, resp. bottom contacts may be easily interconnected by means of interconnects on the top, resp. bottom side of the vertical power system.

The vertical power system may be one of a rectifier, attenuator, switch, or inverter, wherein a rectifier may be one of a half-bridge rectifier, full-bridge rectifier, half-wave rectifier, or full-wave rectifier.

Furthermore, the vertical power system may be a three-phase system, such as a three-phase rectifier, three-phase attenuator, three-phase switch, or three-phase inverter, wherein the three-phase rectifier may be one of a three-phase half-bridge rectifier, three-phase full-bridge rectifier, three-phase half-wave rectifier or three-phase full-wave rectifier. Such a three-phase system may comprise at least three same vertical power devices according to the present disclosure arranged in a side-by-side relationship.

Embodiments of a process flow for manufacturing vertical power devices100,200,300,400,500,600ofFIGS. 1-5 and 15according to the disclosure will be described with reference toFIGS. 6-14.FIG. 6shows a substrate2comprising substrate layers2c-2d(in the finished vertical power devices100,200,300,400,500,600, this corresponds to substrates102,202,302,402,502,602), wherein a III-N device stack4comprising III-N layers4a-4f(in the finished vertical power devices100,200,300,400,500,600this corresponds to III-N device stacks104,204,304,404,504,604) is formed on top of the substrate2and a first passivation layer3(in the finished vertical power devices100,200,300,400,500,600, this corresponds to first passivation layers103,203,303,403,503,603) is formed on top of the III-N device stack4.

FIG. 7shows the substrate2, III-N device stack4, and passivation layer3which may be formed on top of each other as described above, wherein a first via isolation region18is formed (in the finished vertical power devices300,400,500,600, this corresponds to first via isolation regions318,418,518,618), which is known in the art as a shallow recess isolation structure or an implant isolation structure. This first via isolation region18is formed in at least the upper layer4aand the body layer4b. Processes for forming the first via isolation region18are known in the art, such as, trench isolation by recessing through at least the upper and body layers4a,4bor implant isolation.

FIG. 8shows the result of steps of forming at least one gate12(in the finished vertical power devices100,200,300,400,500,600, this corresponds to gates112,122,212,312,322,412,422,512,612) in the III-N device stack4, comprising gate dielectric12band gate electrode12a. Processes for forming the gate12are known in the art and may, for example, comprise etching and deposition steps. A second passivation layer5(in the finished vertical power devices100,200,300,400,500,600, this corresponds to second passivation layers105,205,305,405,505,605) may be formed on the first passivation layer3and the gates12. A process for forming the second passivation layer5is known in the art and may, for example, comprise a deposition step.

FIG. 9shows the result of forming first and second top contacts11a,21a(in the finished vertical power devices100,200,300,400,500,600, this corresponds to first and second top contacts111a,121a,221a,221a,311a,321a,411a,421a,511a,521a,621a) in the III-N device stack4, particularly in at least the upper layer4a, possibly also in the body layer4b, possibly also partly in the lower layer4c. A first and second body contact11c,21cmay be formed on the body layer4b, wherein the relative top contact11a,21ais formed on the upper layer4a. The body contact11c,21cis electrically connected to the relative top contact11a,21a. Processes for forming the top contacts are known in the art and may, for example, comprise etch and deposition steps. Furthermore, a third passivation layer6(in the finished vertical power devices300,400,500, this corresponds to third passivation layers306,406,506) may be formed atop the second passivation layer5. A process for forming the third passivation layer6is known in the art and may, for example, comprise a deposition step.

FIG. 10shows the result of forming a first vertical device isolation structure17(in the finished vertical power devices100,200,300,400,500,600, this corresponds to first vertical device isolation structures117,217,317,417,517,617) as a deep trench isolation module by recessing through at least the III-N device stack4and possibly (as shown) at least partly through the substrate2. In particular, the first vertical device isolation structure17may extend through at least the III-N device stack4as described in the first embodiment. The first vertical device isolation structure17may be further extended in at least one layer of the substrate2and/or at least one of the passivation layers3,5,6as described in herein. Furthermore, the first vertical device isolation structure17may be formed adjacent to or partially in the first via isolation region18.

FIG. 11shows the result of forming a vertical deep via14(in the finished vertical power devices300,400,500this corresponds to vertical deep vias314,414,514,524) through the vertical device isolation structure17, a power metal16(in the finished vertical power devices300,400,500, this corresponds to power metals316,416,516) on the first top contact11aand a lateral interconnect13(in the finished vertical power devices300,400,500, this corresponds to first, resp. second lateral interconnect313,413,513,523) on the second top contact21aand extending over the first vertical device isolation structure17. Processes for forming these structures are known in the art and may, for example, comprise etch and deposition steps. Furthermore, a fourth passivation layer7(in the finished vertical power devices300,400,500, this corresponds to first vertical device isolation structures307,407,507) may be formed on the third passivation layer6and partially over the power metal16and the first lateral interconnect13. A process for forming the third passivation layer7is known in the art and may, for example, comprise a deposition step.

FIG. 12shows that a temporary bonding layer8may be provided on the top side. The temporary bonding layer8may be provided for temporarily bonding the structure formed in the preceding steps to a temporary bonding substrate9. The temporary bonding layer8may comprise an adhesive known in the art such as a thermoplastic adhesive (removable high-temperature spin-on adhesive), thermoset adhesive, low temperature waxes, hydrocarbon oligomers and polymers, acrylates, epoxy, silicones, etc. The temporary bonding may reduce the risk of breaks and other damage of the formed structure in subsequent processing steps.

FIG. 13shows the step of recessing in the bottom side of the structure formed in the preceding steps to form vias15extending from the bottom side up through at least part of the substrate2, particularly through the handling layer2d, carrier layer2c, nucleation layer2band the buffer layer2a, an in some examples up to the lower layer4dof the III-N stack4. The vias15are provided for allowing a first and second bottom power metal to be formed in a subsequent step.

FIG. 14shows a finished vertical power device according to the present disclosure, after formation of the bottom contacts11b,21bin the previously formed vias15. Gate contacts for applying voltages to the gates12are formed in a different plane from the cross-section shown inFIG. 14and are therefore not visible in this Figure. The applied power metal may extend to the outside of the bottom side of the vertical power device, thereby electrically connecting the metal in a number of the vias15and forming the first bottom contact11band the second bottom contact21b. An additional passivation layer (not shown) may be formed on the substrate2on the bottom side of the vertical power device1, thereby partially covering the first and second bottom contacts11b,21b. The additional passivation layer may be provided for isolating the first bottom contact11bfrom the second bottom contact21b. The additional passivation layer may further protect the bottom contacts11b,21bfrom environmental influences.