System and method to change data window

A system to change a data window may include a plurality of registers. Each of the plurality of registers is operative, when activated, to receive data from a bi-directional data bus at a respective input. Each of the plurality of registers is activated in a predetermined sequence to latch a respective portion of the data from the bi-directional data bus so that each respective portion of the data has a longer data window at an output of each of the plurality of registers than at the respective input of each of the plurality of registers.

BACKGROUND

As computer and communication technology becomes more advanced, there is an increasing demand for faster digital communication within computers and communications devices. Use of a common clock, or system core clock, for the transmission and reception of data on different devices or circuits, such as communication between a processor and a memory device, may result in inefficient or inaccurate transfer of data at high speeds. A separate clock signal, or strobe signal, can be used to transmit data between devices. However, there tends to be uncertainty associated with timing of the data and the strobe signal relative to the system core clock.

DETAILED DESCRIPTION

FIG. 1depicts an example of a system10that can be employed to change a data window for DATA received from a data bus22. The system10includes an enable system12that generates one or more enable signals14based on a reset signal16and a strobe signal18. The reset signal16can be provided, for example, by associated circuitry such as a memory device, to initialize a read sequence for the system10to receive data from the data bus22. The strobe signal18corresponds to a separate clock signal to which DATA from the data bus22is timed. The data bus22from which DATA is received may be a bi-directional or a unidirectional bus. For example, the bus may be a double-data rate (DDR) bus, which can be employed for interconnecting one or more associated devices (e.g., processors, memory modules, or other circuits) to the system10.

The input registers of register system20may be any kind of digital device or circuit capable of transferring data from an input to an output upon some triggering condition. Examples may include a flip-flop, latch, or any other state-dependent or digital switching device known in the art. Register system20thus receives the DATA from the data bus22, such as by latching the received DATA into input registers in a predetermined sequence based on enable signals14and the strobe signal18.

The timing relationship of the enable signals14and the strobe signal18relative to each other causes input registers in the register system20to activate in the predetermined sequence. The activation of the register system20by the strobe signal18may occur at every rising edge of the strobe signal, every falling edge of the strobe signal, or, in the case of a DDR bus, registers in the register system can be activated at both every rising edge and every falling edge of the strobe signal18. As a result of the activation of the input registers and enabling of such registers in the predetermined sequence, the register system20maintains the state of the DATA latched from the bus22for an extended duration and provides corresponding intermediate data (DATA INT) at24. The intermediate data DATA INT thus has a duration, or data window, that is substantially longer than the duration as provided on the data bus22prior to entering the register system20. For example, each word of the DATA on data bus22may have a duration that is a fractional part (e.g., about one-half) of a strobe cycle, whereas the representation of the same data at24can have a duration that is greater than one strobe cycle (e.g., about two strobe cycles). Sequential portions of the widened data DATA INT can also overlap based on activation of the register system20by the strobe signal18and the enable signal18. The register system20thus widens or stretches each bit in the DATA stream and provides the widened data as DATA INT24to facilitate subsequent use of such data.

The register system20can provide the DATA INT24to an output system26. The output system26can include a set of output registers, which may be identical in type and in quantity to the type and quantity of input registers contained in register system20. Output system26receives an output enable signal28and a clock signal30. The output system26latches the plurality of lines of the data DATA INT24from the register system20in a predetermined sequence based on the output enable signal28and the clock signal30. It is the arrangement and timing of the output enable signal28and the clock signal30relative to each other that cause the output registers in the output system20to activate in the predetermined sequence. The clock signal30may be a system core clock generated, for example, by a frequency generator circuit. The output system26, in turn, provides output data (DATA OUT)32at the frequency of the clock signal30. For example, the DATA OUT signal32can be a multiple bit data stream synchronized relative to the clock signal30, such as two or more parallel data lines corresponding to overlapping respective portions of the data provided by the register system20. The conversion of the data into a multiple bit output stream32may be accomplished using multiplexers or any other multi-state switching devices.

FIG. 2illustrates another example of a system50that operates to extend a data window for data received from a data bus51. In the example of the system50, it is assumed that the data is received from a bi-directional DDR bus, but it should be known and appreciated that the system50could be suited to receive data from other types of data bus structures.

The system50ofFIG. 2includes an enable system52which receives a reset signal54and a strobe signal56as inputs. The strobe signal56may also be part of the bi-directional DDR bus51. The reset signal54can be generated from a device separate from the system50, such as a memory device. In the example ofFIG. 2, the enable system52generates a pair of enable signals, EN1and EN2, based on the reset signal54and the strobe signal56. The enable system52provides the enable signals EN1and EN2as inputs to a register system58. The register system58also receives a data signal60and the strobe signal56. The data signal60transmits data via the bi-directional DDR bus51to the register system58. The data can be single bit or multi-bit data. The strobe signal56is a periodic clock signal timed to the data signal60, which is also received from the bi-directional DDR bus51.

The register system58includes a set of input registers70,72,74, and76. The respective input registers70,72,74, and76in the register system58are enabled based on the enable signals EN1and EN2. Specifically, as depicted in system50, enable signal EN1enables input registers70and76, while enable signal EN2enables input registers72and74. The input registers70,72,74, and76are depicted as D flip-flops, but it should be understood and appreciated by those skilled in the art that other types of devices can be utilized for acquiring the data from the bus51. In the example ofFIG. 2, and as demonstrated with reference toFIG. 3, the pair of enable signals EN1and EN2of the system50can be inverted relative to each other. However, other combinations of signals which can be employed for enabling the input devices in the register system58will be understood and appreciated by those skilled in the art, of which the signals may vary according to the types of devices utilized to latch the data60from the bus51.

The register system58receives the strobe signal56, the data signal60, and enable signals EN1and EN2. Strobe signal56triggers the activation of input registers70,72,74, and76to latch the DATA from the data bus51based on the respective enable signal, either EN1or EN2. In the example ofFIG. 2, each of the input registers70and76are enabled when the respective enable signal EN1is high (i.e. logic 1). Similarly, input registers72and74are enabled when the respective enable signal EN2is high. The input registers (or other switching devices)70,72,.74, and76could be enabled by signals having different logic levels from that shown and described herein.

In the example of system50, the input registers72and76include inverted clock inputs for receiving the strobe signal56. The DATA signal60can be received from a bi-directional DDR bus, such that the DATA signal is timed in synchronization with the strobe signal56. For example, the DATA signal60can be timed so that every rising edge and every falling edge of the strobe signal56is aligned with a corresponding data bit in the DATA signal. To facilitate latching data into the input registers70,72,74, and76in a predetermined sequence, input registers70and74are activated to latch data bits timed to the rising edge of strobe signal56, and input registers72and76are activated to latch data bits timed to the falling edge of strobe signal56.

FIG. 3demonstrates a timing diagram150for the system50illustrated inFIG. 2. For purposes of describing the timing diagram150, like reference numbers will be used to describe the signals as they correspond to the various signals of the system50described inFIG. 2. The DATA signal60is depicted in the timing diagram150as a series of four data bits, A, B, C, and D. The data bits A, B, C, and D correspond to four sequential bits that could be received as DATA from the bus51(e.g., a bi-directional DDR bus). As such, the data bits A, B, C, and D are depicted in the timing diagram150as being timed to both rising and falling edges of the strobe signal56to account for the double data-rate of the bus. Additionally, because the DDR bus is bi-directional in the example of the system50ofFIG. 2, the strobe signal56can be active during a read sequence with read data, as described herein, and the strobe signal can be active during a write sequence with write data on the bus51. Accordingly, during a write sequence, the register204may toggle an unknown number of times between read sequences, but data will not be latched due to the absence of the reset signal at54. The strobe signal56can be in tri-state condition152between read and write sequences.

The timing diagram150demonstrates the relationship between the strobe signal56and the enable signals EN1and EN2to latch the input registers70,72,74, and76ofFIG. 2in a predetermined sequence. In the example of the system50, the predetermined sequence of data latching is that the input registers70,72,74, and76latch each bit of the DATA sequentially into respective registers. Each of the input registers70,72,74, and76latches the DATA from the bus51according to the data at the input while the latch is enabled by the respective enable signal and its clock input is asserted by the strobe signal56to activate the respective register. The input register70latches the bit A from the DATA signal60at a rising edge of strobe signal56while the enable signal EN1is high at the enable input. The input register70thus outputs an intermediate signal INT1corresponding to the bit A latched from data signal60. Next, the input register72latches the bit B from the DATA signal60upon a falling edge of the strobe signal56while the enable signal EN2is high at the enable input. The input register72thus outputs an intermediate signal INT2corresponding to the bit B latched from the data signal60. Next, the input register74latches the bit C from the DATA signal60upon a rising edge of the strobe signal56while the enable signal EN2is high at the enable input. The input register74thus outputs an intermediate signal INT3corresponding to the bit C latched from the DATA signal60. Finally, the input register76latches the bit D from the DATA signal60upon a falling edge of the strobe signal56while the enable signal EN1is high at the enable input. The input register76thus outputs an intermediate signal INT4corresponding to the bit D latched from the, DATA signal60. In this way, each of the input registers70,72,74, and76latches a separate data bit sequentially at every half duty-cycle of the strobe signal56, such that each output INT1, INT2, INT3, and INT4is delayed by a half of a period of the strobe cycle56from the output that preceded it in the sequence.

The enable signals EN1and EN2are illustrated in the timing diagram150to be in the appropriate states to latch data bits A, B, C, and D into input registers70,72,74, and76. It is the time duration of the states of the enable signals EN1and EN2relative to when the input registers70,72,74, and76are activated that operates to extend the data window of the data bits A, B, C, and D of the intermediate signals INT1, INT2, INT3, and INT4relative to the data bits A, B, C, and D on the DATA signal60timed to the strobe signal56on the data bus51. For example, as described above, the input register70latches the data bit A when the enable signal EN1is high and the register is activated by a rising edge of the strobe signal56. However, the input register70does not load another data bit at the next rising edge of the strobe signal56because the enable signal70is low (i.e. logic 0). Accordingly, the data bit A remains latched in the input register70for two cycles of the strobe signal56, thus extending the data window of the bit A by about four times the duration that it appears in the DATA signal60on the bi-directional DDR bus51. The other input registers72,74, and76operate in a similar manner with different combinations of states of the enable signals EN1and EN2and the strobe signal56;

It should be understand that, as will be further demonstrated with regard toFIG. 4, the enable signals EN1and EN2, as depicted in the example of the system50and the corresponding timing diagram150, change state at a rising edge of the strobe signal56. Because the input registers70and74in the example of system50are also latched on a rising edge of the strobe signal56, a delay time gap154has been illustrated in the timing diagram150to demonstrate that there is a slight time delay from the point at which the input registers70and74latch the data bits A and C, respectively, and when the enable signals EN1and EN2change state from the same event. It should be noted that the timing diagram150ofFIG. 3is an otherwise ideal timing diagram and thus contains no other propagation or switching delays, though inherent propagation and switching delays may be present.

Referring back toFIG. 2, the register system58thus provides the intermediate data signals INT1, INT2, INT3, and INT4as inputs to a set of output registers80,82,84, and86in an output system88. Output system88also receives as inputs an OUTPUT ENABLE signal90and a clock signal92. For example, the clock signal92may be the system core clock, such as can be generated by a frequency generator. The OUTPUT ENABLE signal may be provided by a device separate from the system50, such as by a memory device. An inverter96inverts the output enable signal90to provide an inverted OUTPUT ENABLE signal94to the output system88. The intermediate data signals INT1, INT2, INT3, and INT4, which have a wider data window than the respective data bits in the DATA signal60, are latched into the output registers80,82,84, and86in a predetermined sequence based on the relationship of the OUTPUT ENABLE signal90(or corresponding inverted OUTPUT ENABLE signal94) and the clock signal92. In the example of system50, pairs of the output registers activate to latch data simultaneously.

For example, turning once again toFIG. 3, when the OUTPUT ENABLE signal90is high, a rising edge of the clock signal92will simultaneously latch the data bit A on the intermediate signal INT1into the output register80and the data bit B on the intermediate signal INT2into the output register82, respectively. Output registers80and82will thus simultaneously output signals Q1and Q2, respectively. Accordingly, when the output enable signal90is low, and thus the inverted output enable signal94is high, a rising edge of the clock signal92will simultaneously latch the data bit C on the intermediate signal INT3into the output register84and the data bit D on the intermediate signal INT4into the output register86, respectively. Output registers84and86will thus simultaneously output signals Q3and Q4, respectively.

Because the output registers80,82,84, and86in the output system88are triggered using the clock signal92, and not the strobe signal56, as are the input registers70,72,74, and76in the register system58, there is an inherent amount of uncertainty of timing in the system50. The timing uncertainty is based on the timing of the DATA signal60, which is timed to the strobe signal56, relative to the timing of the clock signal92. This timing uncertainty is demonstrated in the timing diagram150ofFIG. 3by a dashed line156, which is aligned at a rising edge of the clock signal92, but is not aligned with a known point on the strobe signal56. The uncertainty between the relative timing of the strobe signal56and the clock signal92makes it difficult to synchronize the data timed to the strobe signal56to the clock signal92, such that, for example, errors resulting from metastability may occur in the transfer of data between two devices communicating at high speed, such as a processor and a memory device. This timing uncertainty is tolerated by the system50because of the extension of the data window of the data in the intermediate data signals INT1, INT2, INT3, and INT4resulting from the predetermined sequence in which the input registers70,72,74, and76of the register system58are latched.

The advantages of the extension of the data window associated with the intermediate data signals INT1, INT2, INT3, and INT4is apparent with regard to the latching of the output registers80,82,84, and86. In the example of the system50and the timing diagram150, pairs of output registers,80and82as one pair and84and86as the other pair, respectively, activate to latch data concurrently using the output enable signal90, or inverted output enable signal94, and the clock signal92. Due to the extended data window of the data bits A, B, C, and D in the intermediate data signals INT1, INT2, INT3, and INT4, there is a substantial time overlap of latched data between sequential intermediate data signals INT1, INT2, INT3, and INT4. Because of the overlap, at the rising edge of clock signal92at the dashed line156, output registers80and82simultaneously latch the data bits A and B, respectively, into the output signals Q1and Q2. To ensure that the data bits A and B are latched simultaneously, the rising edge of the clock signal92that triggers the activation of the output registers80and82occurs within the window of time that the data bits A and B overlap in the intermediate data signals INT1and INT2, respectively. This window of time is depicted in timing diagram150as the time between dashed lines158and160, which represents an extended window in which activation of the output registers80and82can occur to provide the multi-bit output data Q1and Q2synchronized with the clock signal92with a high degree of certainty. That is, the extended time window in which data bits A and B overlap mitigates uncertainty of data capture that otherwise may exist due to the occurrence of a metastable condition between the input data and the output data. More specifically, as long as the time between dashed lines158and160is greater than or equal to a setup-and-hold time of the output registers80and82, metastability of the data latched in the output registers80and82may be prevented, regardless of the relative timing between the strobe signal56and the clock signal92.

Thus, as demonstrated by the example of the system50and the timing diagram150, the approach described herein can extend the data window of data latched at the outputs of the registers70,72,74and76as well as provide overlap between sequential data at the outputs of the registers70,72,74and76. The amount of overlap between sequential data latched at the outputs of the registers70,72,74and76provides an extended window to facilitate latching and of data by the output registers80,82,84and86synchronized relative to the system clock. As a result, the setup-and-hold time of the output registers80and82as well as for registers84and86resides within the extended window corresponding to the amount of overlap between sequential data at the output of the registers70,72,74and76. The extended window thus enables latching data with reduced uncertainty relative to many conventional approaches. It should further be appreciated that, as depicted in the timing diagram150ofFIG. 3, the same operation occurs to create an extended data window between the intermediate data signals INT3and INT4for the latching of the data bits C and D into the output registers84and86with reduced uncertainty.

Referring back toFIG. 2, the outputs of the output registers80,82,84, and86are coupled to provide the output signals Q1, Q2, Q3, and Q4to an output system, which could include, as demonstrated inFIG. 2, output switches100and102of the system50. The output switches100and102can provide the output signals Q1, Q2, Q3, and Q4as a multiple bit output stream, indicated inFIG. 2as output signals OUT0and OUT1. As an example, the output switches100and102may be implemented as multiplexers or any other kind of multi-state switching device known in the art. In the example ofFIG. 2, the OUTPUT ENABLE signal90controls the output switches100and102to provide the output signals OUT0and OUT1. That is, the OUTPUT ENABLE signal90toggles output switch100between the signals Q1and Q3to provide the output signal OUT0, and the OUTPUT ENABLE signal90toggles the output switch102between the signals Q2and Q4to generate the output signal OUT1. While the output states of the switches100and102are demonstrated in the example of the system50as being controlled by the OUTPUT ENABLE signal90, it should be appreciated by one skilled in the art that the output switches100and102can be controlled by a number of other means to generate the desired resultant output signals OUT0and OUT1, such as, for example, by using the clock signal92.

The timing diagram150ofFIG. 3also demonstrates the relationship between the output signals OUT0and OUT1from the output switches100and102, respectively, and the output enable signal90which toggles the output switches between states. As depicted in timing diagram150, the output switches100and102change states at every change of state of the output enable signal90, thus resulting in a separate pair of output data bits switched from the outputs of the output registers80,82,84, and86.

It should be understood and appreciated that there are a number of ways to achieve the results of the system50to extend the data window for data received from a data bus, and that the results achieved are thus not limited to the example of the system50. For example, another system could achieve similar or same results utilizing more or less input registers, output registers, and output switches. Different combinations of input signals, or alternatively time shifted signals, could also achieve similar or the same results as that depicted in the system50and the corresponding timing diagram150.

FIG. 4depicts an example of an enable system200that may be used to generate one or more enable signals for enabling operation of a register system, such as described herein. For example, the enable system200can be employed to generate the enable signals EN1and EN2in the system50ofFIG. 2. The enable system200includes a D flip-flop204that receives a STROBE signal202at a clock input for activating the flip-flop. The flip-flop204has an output206that drives an input of another D flip-flop208and an XOR gate210. Additionally, the output206of the flip-flop204is fed back to an input of the flip flop204through an inverter212. The circuit arrangement associated with the flip-flop204results in a change of state at the output206at every rising edge of strobe signal202.

The flip-flop208receives a RESET signal214as an enable input and receives a CLOCK signal216at a clock input that is used to trigger activation of the flip-flop. The CLOCK signal216may be a system core clock generated, for example, by a frequency generator, a timer, oscillator circuit, or other circuitry (internal or external) that may provide a system clock. The D flip-flop208drives an inverter218, which provides an inverted version of the input from the flip-flop as a second input to the XOR gate210. The XOR gate210provides an enable signal EN1at an output220of the XOR gate. An inverter222inverts the signal at220to provide another enable signal EN2, which is out of phase relative to EN1.

By way of example, when a read sequence begins, the RESET signal214changes state to a low condition, which disables the flip-flop208. This causes the flip-flop208to maintain its present state corresponding to the signal at206just prior to the RESET signal214going low (regardless of the state of the clock signal216). The flip-flop204is activated based on the STROBE signal202, which, prior to a read sequence, may be in a tri-state or a constant state condition. Accordingly, the flip-flop204maintains its output206at a constant state prior to a read sequence, causing the output of inverter218to maintain a constant state inverted from output206prior to a read sequence. The result is that the output220of the XOR gate210in the example of circuit200prior to a read sequence is a logic 1. Therefore, in the example of circuit200, prior to a read sequence, EN1is a logic 1 and EN2is a logic 0 (see, e.g.,FIG. 3).

After the RESET signal214has changed to a low condition, the STROBE signal202begins to cycle. At every rising edge of the strobe signal202, the D flip-flop204is triggered, causing the output206to change state. Because the output206is alternating states at every rising edge of the strobe signal202during a read sequence, and because the output of inverter218remains constant, the output220from the XOR gate210alternates states with every rising edge of the strobe signal202during the read sequence. Thus, the enable signals EN1and EN2change state (inverted relative each other) at every rising edge of strobe signal202during a read sequence, such that each enable signal EN1and EN2has a period that is greater than (e.g., twice) the period of the strobe signal.

It should be understood and appreciated that there are a number of ways to generate the enable signals required to latch data into the set of input registers in the predetermined sequence, and that the results achieved are thus not limited to the example of the system200. For example, more or less enable signals could be generated with different phase shifts relative to each other. Enable signals could change states at all times, and not just during a read sequence. The system200is merely an example circuit to generate enable signals such as could be used by the example of the system50.

FIG. 5depicts an example of a system250for changing the data window to facilitate acquisition of data from a bus252. In the example ofFIG. 5, the bus252is a bi-directional data bus. The bi-directional data bus252can be configured to communicate data to and from a number of devices, such as a memory system256, which could be, for example, a dynamic random access memory (DRAM). The bi-directional data bus252could also be configured to communicate data to and from one or more other devices258. For example, one or more processors254can communicate with the memory system256or other additional devices258, such as for reading data from or writing data to the memory system or other devices. The other devices may be, for example, peripheral devices, network or communication devices, or additional processing devices. The data transferred across the bus252can be accompanied by a strobe signal to facilitate its transfer through the bus.

The system250can further include a data path system260interconnected between the processor254and the bi-directional data bus252. The data path system260includes a data read path262for reading data from the memory256or the other devices258. The data read path262also includes a system264for changing the data window of the data being read to facilitate its acquisition from the bi-directional data bus252. Particularly, the system264can receive data and strobe signals from the bi-directional data bus252and operate to widen the data window associated with such data. For instance, the system264can latch the data sequentially into a register system and output the data as a multi-bit data stream, indicated at266, to the processor254.

Additionally, the data path system260can also include a data write path268that is operative to write data received from the processor254to the memory system256and/or to the other device(s)258. The data write path268writes data through the bi-directional data bus252as strobed data that includes a data signal and a strobe signal. While, for purposes of simplicity of illustration, the data and strobe signals are shown for each of the data read path262and the data write path268, those skilled in the art will understand that typically the same lines can be employed for reading and writing data and for providing the strobe signals between the data paths and the bus252.

In view of the foregoing structural and functional features described above, certain methods will be better appreciated with reference toFIGS. 6 and 7. It is to be understood and appreciated that the illustrated actions, in other embodiments, may occur in different orders and/or concurrently with other actions. Moreover, not all illustrated features may be required to implement a method. It is to be further understood that the following methodologies can be implemented in hardware (e.g., analog or digital circuitry, such as may be embodied in an application specific integrated circuit or a computer system), software (e.g., as executable instructions stored on a computer readable media or running on one or more computer systems), or any combination of hardware and software.

FIG. 6depicts an example of a method270. The method includes receiving data from a bi-directional data bus, as shown at272. A strobe signal associated with the data received from the bi-directional data bus is also received at274. At276, respective portions of the data from the bi-directional data bus are latched in a predetermined sequence to provide latched data based on the strobe signal and at least one enable signal such that each respective portion of the latched data has a longer data window than a data window of for the data that is received from the data bus and the data windows of at least some respective portions of the latched data in the predetermined sequence overlap.

FIG. 7depicts an example of another flow diagram for a method300that can be employed to change a data window. At302, a read sequence is activated to enable data to be read from a data bus, such as a bi-directional DDR bus. The activation of the reset sequence may involve asserting a reset signal to initialize a read sequence. At304, data is provided via the bi-directional data bus. At306, a strobe signal associated with the data on the bus is also provided. The timing of the strobe signal relative to the data, for example, can be one piece of data (e.g., a bit or plural bits) per each rising edge of the strobe signal. In the case of a bi-directional DDR bus, one data bit can be provided with each rising edge and another data bit for each falling edge of the strobe signal.

At308, one or more enable signals are generated. The enable signals are employed to enable a set of input registers. There could be any number of one or more enable signals, typically depending on the configuration of hardware and number of input registers being employed to latch data from the bus. For instance, a pair of enable signals that are out of phase relative to each other can be employed for enabling respective sets of registers for latching data in a predetermined sequence.

At310, a determination is made as to whether an enable signal is present at a given input registerito enable the register. If the enable signal is present, the method proceeds to312, at which point a determination is made as to whether the strobe signal activates registeri. For example, the strobe signal may activate register1when a rising edge of the strobe signal or a falling edge of the strobe signal is provided at a corresponding clock input of the registers. After register1is activated, the method300proceeds to314where data (e.g., a bit) is latched into registeri.

After the data has been latched into registeri, the method proceeds to316to determine if there is additional data to read from the bi-directional data bus. If there is additional data on the bi-directional data bus, the method300proceeds to318to increment to a next input registeriand then looping back to310. If there is no additional data on the bi-directional data bus, the method300proceeds to320regarding output registerj.

The method300also proceeds from314to320for implementing another part of the method300, namely for propagating the data latched at314through an output registerj. At320, the method is idle until an output enable signal enables a given output registerj. When the output enable signal enables the output registerj, the method proceeds to324. At324, the method maintains the state of the output registerjuntil activated by a clock signal. The clock signal may activate the output registerj, for example, at a rising edge (or a falling edge) of the clock signal. Once registerjis activated, the method proceeds to324to latch intermediate data into the output registerj. After the data bit has been latched into registerj, the method proceeds to326where data output switches can be toggled to provide a multi-bit output signal (e.g., on a two or more bit bus). The output switches may be multiplexers or any other kind of multi-state switching device known in the art. The toggling of the output switches may occur in response to the output enable signal, a rising edge of the system clock, or some other predefined event to achieve the desired output timing.

At328, the method300then determines if additional data has been provided to the output registerjfrom the input registers at328. If there is additional data, the method300proceeds to330for incrementing to a next output register and looping back to316to propagate such additional data through the next output registerj. If, at328, there is no additional data input to the output registerjfrom the input registeri, the method300proceeds to332where the read sequence for acquiring data from the bi-directional data bus is deactivated. This could be accomplished by changing the state of a reset signal, for example. After the read sequence has been deactivated, the method300ends at334.

It is to be understood and appreciated that the branching of the method from314to both316and318is to demonstrate that more than one unit of data can be propagated according to the method300through more than one register as part of the read sequence. It is to be further understood that data can also be propagated concurrently through more than one input register as well as concurrently through more than one output register.