ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS

An array substrate includes a substrate, first power supply signal lines, data lines and fan-out lines. The fan-out lines each include a first sub-line and a second sub-line; an end of the second sub-line is electrically connected to the first sub-line, another end of the second sub-line is electrically connected to a single data line, and the second sub-line is insulated from remaining data lines of the data lines. The first sub-line and main structures of the data lines are disposed in a same layer. An orthographic projection, on the substrate, of a first sub-line passing through a column of sub-pixel regions is substantially located between an orthographic projection, on the substrate, of a first power supply signal line passing through the column of sub-pixel regions and an orthographic projection, on the substrate, of a data line passing through the column of sub-pixel regions.

TECHNICAL FIELD

The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel and a display apparatus.

BACKGROUND

At present, organic light-emitting diode (OLED) display apparatuses have been widely used due to their characteristics of self-luminescence, quick response, wide viewing angle, being capable of being manufactured on flexible substrates and the like. The OLED display apparatuses each include a plurality of sub-pixels; each sub-pixel includes a pixel driving circuit and a light-emitting device, and the pixel driving circuit drives the light-emitting device to emit light, so as to achieve display.

SUMMARY

In an aspect, an array substrate is provided. The array substrate includes a substrate, a plurality of first power supply signal lines, a plurality of data lines and a plurality of fan-out lines. The substrate has a display area and a peripheral area. The plurality of first power supply signal lines are located on a first side of the substrate and located in the display area; the plurality of first power supply signal lines each extend in a first direction and are sequentially arranged in a second direction; the second direction intersects the first direction, and the second direction and the first direction are both parallel to the substrate. The plurality of data lines are located on the first side of the substrate and located in the display area; the plurality of data lines each extend in the first direction and are sequentially arranged in the second direction; a data line is adjacent to a first power supply signal line. The plurality of fan-out lines are located on the first side of the substrate; the plurality of fan-out lines each include a first sub-line and a second sub-line; the first sub-line extends in the first direction and extends from the peripheral area to the display area; the second sub-line extends in the second direction and is located in the display area; an end of the second sub-line is electrically connected to the first sub-line, another end of the second sub-line is electrically connected to a single data line of the plurality of data lines, and the second sub-line is insulated from remaining data lines of the plurality of data lines.

Main structures of the plurality of data lines are located on a side of the first power supply signal lines away from the substrate, and the first sub-line and the main structures of the plurality of data lines are disposed in a same layer. The display area has sub-pixel regions in a plurality of rows and a plurality of columns; an orthographic projection, on the substrate, of a first sub-line passing through a column of sub-pixel regions is substantially located between an orthographic projection, on the substrate, of a first power supply signal line passing through the column of sub-pixel regions and an orthographic projection, on the substrate, of a data line passing through the column of sub-pixel regions.

In some embodiments, the peripheral area includes a lead-out region located on a side of the display area; the first sub-line extends from the lead-out region to the display area, and a length of at least one first sub-line is not greater than half a dimension of the display area in the first direction.

In some embodiments, a direction from a center line, in the second direction, of the display area to any side of the display area in the second direction is a first setting direction; lengths of portions, located in the display area, of first sub-lines of all first sub-lines included in the plurality of fan-out lines sequentially decrease in the first setting direction.

In some embodiments, the main structures of the plurality of data lines each include a plurality of main lines; at least part of the plurality of data lines each further include at least one jumper wire, and the at least one jumper wire and the first power supply signal lines are disposed in another same layer; in a same data line, at least one jumper wire and main lines are alternately electrically connected to one other through via holes; the second sub-line and the plurality of main lines are arranged in the same layer, and each of at least one second sub-line crosses a jumper wire of at least one data line. In some embodiments, the array substrate further includes an active film layer disposed between the at least one jumper wire and the substrate; a jumper wire has an extension portion, and an end of the extension portion is connected to the active film layer through a via hole.

In some embodiments, a minimum closed graphic region where all second sub-lines, located on a same side of a center line of the display area in the second direction, are located is a first wiring region; at least a portion, located within the first wiring region, of each of data lines passing through the first wiring region is provided with a jumper wire.

In some embodiments, a direction from a center line, in the second direction, of the display area to any side of the display area in the second direction is a first setting direction; numbers of jumper wires respectively included in data lines firstly increase and then decrease in the first setting direction.

In some embodiments, of all the data lines passing through the first wiring region, a data line of which a portion located within the first wiring region has a greatest number of jumper wires is a first-type data line, and data lines other than the first-type data line are second-type data lines.

A portion, located outside the first wiring region, of each of all the second-type data lines is provided with a jumper wire; a number of jumper wires included in each of all the second-type data lines is equal to a number of jumper wires included in the first-type data line.

In some embodiments, an end of the first sub-line connected to the second sub-line is a first end, and another end of the first sub-line is a second end; a direction from the second end to the first end is a second setting direction; of each of all the second-type data lines, the jumper wire located within the first wiring region and the jumper wire located outside the first wiring region are arranged in the second setting direction.

In some embodiments, a portion, located outside the first wiring region, of each of all the data lines passing through the first wiring region is provided with a jumper wire; a number of jumper wires included in each data line is equal; jumper wires included in all the data lines passing through the first wiring region are arranged in rows in the first direction.

In some embodiments, the array substrate includes a first source-drain metal layer located on the first side of the substrate and a second source-drain metal layer located on a side of the first source-drain metal layer away from the substrate. The first power supply signal lines and the at least one jumper wire are located in the first source-drain metal layer, and the first sub-line, the second sub-line and the plurality of main lines are located in the second source-drain metal layer.

In some embodiments, the second sub-line is located in a layer different from the layer in which the main structures of the plurality of data lines are located.

In some embodiments, the array substrate includes at least one gate metal layer located on the first side of the substrate, a first source-drain metal layer located on a side of the at least one gate metal layer away from the substrate and a second source-drain metal layer located on a side of the first source-drain metal layer away from the substrate. The second sub-line is disposed in any gate metal layer, the first power supply signal lines are disposed in the first source-drain metal layer, and the first sub-line and the main structures of the plurality of data lines are disposed in the second source-drain metal layer.

In some embodiments, the array substrate includes a plurality of first initial signal lines located on the first side of the substrate and located in the display area. The plurality of first initial signal lines each extend in the second direction; the plurality of first initial signal lines are located in a layer different from a layer in which the second sub-line is located; an orthographic projection, on the substrate, of a first initial signal line corresponding to a row of sub-pixel regions at least partially overlaps with an orthographic projection, on the substrate, of a second sub-line corresponding to the row of sub-pixel regions.

In some embodiments, the array substrate further includes a plurality of second initial signal lines located on the first side of the substrate and located in the display area. The plurality of second initial signal lines each extend in the first direction. The plurality of second initial signal lines are located in a layer different from the layer in which the plurality of first initial signal lines are located, and the plurality of second initial signal lines are electrically connected to the plurality of first initial signal lines through another via holes; an orthographic projection, on the substrate, of another first sub-line corresponding to the column of sub-pixel regions at least partially overlaps with an orthographic projection, on the substrate, of a second initial signal line corresponding to the column of sub-pixel regions.

In some embodiments, the second initial signal lines and the at least one jumper wire are located in the another same layer, and a second initial signal line is located between a jumper wire and a first power supply signal line; the second initial signal line has an avoidance portion bent towards a side where the first power supply signal line is located, and at least a portion of the jumper wire is located within an avoidance space defined by the avoidance portion.

In another aspect, an array substrate is provided. The array substrate includes a substrate, a plurality of first power supply signal lines, a plurality of data lines and a plurality of fan-out lines. The substrate has a display area and a peripheral area. The plurality of first power supply signal lines are located on a first side of the substrate and located in the display area; the plurality of first power supply signal lines each extend in a first direction and are sequentially arranged in a second direction; the second direction intersects the first direction, and the second direction and the first direction are both parallel to the substrate. The plurality of data lines are located on the first side of the substrate and located in the display area; the plurality of data lines each extend in the first direction and are sequentially arranged in the second direction; a data line is adjacent to a first power supply signal line. The plurality of fan-out lines are located on the first side of the substrate. A fan-out line includes a first sub-line and a second sub-line; the first sub-line extends in the first direction and extends from the peripheral area to the display area; the second sub-line extends in the second direction and is located in the display area; an end of the second sub-line is electrically connected to the first sub-line, another end of the second sub-line is electrically connected to a single data line of the plurality of data lines, and the second sub-line is insulated from remaining data lines of the plurality of data lines.

Main structures of the data lines are located on a side of the first power supply signal lines away from the substrate, and the first sub-line and the main structures of the data lines are disposed in a same layer.

The array substrate has pixel driving circuits in a plurality of rows and a plurality of columns; an orthographic projection, on the substrate, of the first sub-line passing through a column of pixel driving circuits is located between an orthographic projection, on the substrate, of a first power supply signal line passing through the column of pixel driving circuits and an orthographic projection, on the substrate, of a data line passing through the column of pixel driving circuits.

In yet another aspect, a display panel is provided. The display panel includes the array substrate as described in any one of the above embodiments, a light-emitting device layer and an encapsulation layer. The light-emitting device layer is located on a side of the array substrate away from the substrate; the encapsulation layer is located on a side of the light-emitting device layer away from the array substrate.

In yet another aspect, a display apparatus is provided. The display apparatus includes the display panel as described in any one of the above embodiments, a flexible circuit board and a main control circuit board. The peripheral area of the display panel includes a lead-out region and a bonding region that are located on a side of the display area, and the bonding region is located on a side of the lead-out region away from the display area. An end of the flexible circuit board is bonded in the bonding region; the main control circuit board is electrically connected to another end of the flexible circuit board.

DETAILED DESCRIPTION

In the description of some embodiments, the terms such as “connected” and derivatives thereof may be used. For example, the term “connected” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.

In the description of some embodiments, the term “corresponding” may be used. For example, in the description of some embodiments, the term “corresponding” may be used to describe that a line corresponds to a region, so as to indicate that an orthographic projection of the line on a plane overlaps with an orthographic projection of the region on the plane. For another example, in the description of some embodiments, the term “corresponding” may be used to describe that a line corresponds to another line, so as to indicate that the line is electrically connected to the another line.

In the description of some embodiments, the term “crossing” may be used. For example, in the description of some embodiments, the term “crossing” may be used to describe that a line crosses another line, so as to indicate that an orthographic projection of the line on a plane intersects an orthographic projection of the another line on the plane.

In the description of some embodiments, the term “passing through” may be used. For example, in the description of some embodiments, the term “passing through” may be used to describe that a line passes through a region, so as to indicate that an orthographic projection of the line on a plane partially or completely overlaps with an orthographic projection of the region on the plane.

The phase “based on” as used herein is meant to be open and inclusive, since a process, a step, a calculation or other action that is “based on” one or more of stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

As used herein, the term “substantially” includes a stated value and an average value within an acceptable range of deviation of a particular value. The acceptable range of deviation is determined by a person of ordinary skill in the art in view of measurement in question and errors associated with measurement of a particular quantity (i.e., limitations of a measurement system).

As used herein, the term “perpendicular” includes a stated condition and a condition similar to the stated condition, a range of the similar condition is within an acceptable range of deviation, and the acceptable range of deviation is determined by a person of ordinary skill in the art, considering measurement in question and errors associated with measurement of a particular quantity (i.e., limitations of a measurement system). The term “perpendicular” includes absolute perpendicularity and approximate perpendicularity, and an acceptable range of deviation of the approximate perpendicularity may be, for example, a deviation within 5°.

It will be understood that, in a case where a layer or an element is referred to as being on another layer or a substrate, it may be that the layer or the element is directly on the another layer or the substrate, or there may be a middle layer between the layer or the element and the another layer or the substrate.

Some embodiments of the present disclosure provide a display apparatus.FIG.1Ais a structural diagram of the display apparatus, in accordance with some embodiments. Referring toFIG.1A, the display apparatus100is a product having a function of displaying images (including an image in stationary or an image in motion (which may be a video)). For example, the display apparatus100may be any one of a display, a television, a billboard, a digital photo frame, a laser printer having a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a portable camcorder, a view finder, a navigator, a vehicle, a large-area wall, a household appliance, an information inquiry device (e.g., a business inquiry device for a department of e-government, bank, hospital, electricity or the like) and a monitor.

The display apparatus100includes a display panel200. Referring toFIG.1B, the display panel200is provided with a plurality of sub-pixels210therein; the sub-pixels210are each a minimum unit of the display panel200for performing image display, and each sub-pixel210may display a single color, such as a red color (R), a green color (G) or a blue color (B). The display panel200is provided with red sub-pixels, green sub-pixels and blue sub-pixels therein, so as to adjust luminance (gray scales) of sub-pixels of different colors. Thus, display of a plurality of colors may be achieved by a color combination and a color superimposition, so that full-color display of the display panel200is achieved. As shown inFIG.1D, each sub-pixel210includes a light-emitting device OLED and a pixel driving circuit211used for driving the light-emitting device OLED to emit light.

Referring toFIG.1C, the display panel200includes an array substrate300, a light-emitting device layer400and an encapsulation layer500that are stacked in sequence. The array substrate300, the light-emitting device layer400and the encapsulation layer500will be respectively described below.

For example, as shown inFIG.1E, the array substrate300includes a substrate310, a plurality of functional layers sequentially arranged on the substrate310, and insulating layers (e.g., a gate insulating layer and a buffer layer) each located between two adjacent functional layers. Referring toFIG.1D, the substrate310has a display area AA and a peripheral area BB located on at least one side of the display area AA. The peripheral area BB may surround the display area AA.

Referring toFIG.1E, the functional layers in the array substrate300may include an active film layer380, a first gate metal layer Gate1, a second gate metal layer Gate2, a first source-drain metal layer SD1and a second source-drain metal layer SD2; the active film layer380, the first gate metal layer Gate1, the second gate metal layer Gate2, the first source-drain metal layer SD1and the second source-drain metal layer SD2are used for forming a plurality of pixel driving circuits211. The plurality of pixel driving circuits211are disposed in the display area AA. In addition, the functional layers may be further used for forming signal lines each transmitting a signal to a pixel driving circuit211. Referring toFIG.1D, the signal lines may include first power supply signal lines Vdd, data lines Dt, initial signal lines Vt, gate scanning signal lines G, light-emitting control signal lines Em and reset signal lines Rst. The first power supply signal line Vdd is configured to transmit a first power supply signal, such as a voltage drain drain (VDD) signal, to the pixel driving circuit211; the data line Dt is configured to transmit a data signal to the pixel driving circuit211; the initial signal lines Vt is configured to transmit an initial signal Vt to the pixel driving circuit211; the gate scanning signal lines G is configured to transmit a gate scanning signal to the pixel driving circuit211; the light-emitting control signal lines Em is configured to transmit a light-emitting control signal to the pixel driving circuit211; the reset signal lines Rst is configured to transmit a reset signal to the pixel driving circuit211.

Referring toFIG.1E, the light-emitting device layer400includes an anode layer AND, a light-emitting layer EML and a cathode layer CTD. The light-emitting device layer400is configured to form a plurality of light-emitting devices OLED. The light-emitting device OLED is electrically connected to the pixel driving circuit211, so that the pixel driving circuit211drives the light-emitting device OLED to emit light.

The encapsulation layer500may cover the light-emitting devices OLED and encapsulate the light-emitting devices OLED, so as to prevent moisture and oxygen in the external environment from entering the display panel200.

Referring toFIG.1F, in some implementations, a peripheral area BB of the array substrate300is provided with a first fan-out region B1, a bending region B2, a second fan-out region B3, a test circuit region B4, a chip region B5and a bonding region B6. The array substrate300includes the substrate310, and the substrate310includes the peripheral area BB and the display area AA. A display area AA of the array substrate300and the display area AA of the substrate310are a same region, and the peripheral area BB of the array substrate300and the peripheral area BB of the substrate310are a same region.

The first fan-out region B1is provided with lead-out portions of the data lines Dt therein, and the data lines Dt are gathered in the first fan-out region B1; the second fan-out region B3is provided with lead-out portions of the first power supply signal lines Vdd, and the first power supply signal lines Vdd are gathered in the second fan-out region B3; the test circuit region B4is provided with a display screen test circuit therein; the chip region B5is provided with a driver integrated circuit (IC) bonded therein; the bonding region B6is provided with a plurality of pins therein, and the display panel200may be electrically connected to a flexible circuit board via the plurality of pins. It will be noted that the bending region B2is made of a flexible material, and may be bendable; the bending region B2, the second fan-out region B3, the test circuit region B4, the chip region B5and the bonding region B6need to be folded onto a back surface of the display panel200, thereby reducing a width of a bezel of the display panel200and satisfying a requirement for “a small chin” of the display panel200.

In another implementation, the first fan-out region is designed to be inside the display area AA. That is, fan-out lines in the first fan-out region are gathered in the display area AA, so that the width of the bezel of the display panel is reduced. For example, referring toFIG.1G, the array substrate300is provided with data lines Dt and fan-out lines214therein, and the data lines Dt each extend in a first direction Y. A fan-out line214includes a first sub-line2141extending in the first direction Y and a second sub-line2142extending in a second direction X, and the first direction Y intersects the second direction X. For example, the first direction Y may be perpendicular to the second direction X. The first sub-line2141extends from the peripheral area BB to the display area AA; an end of the second sub-line2142is electrically connected to an end of the first sub-line2141located in the display area AA, and another end of the second sub-line242away from the first sub-line2141is electrically connected to one of the data lines Dt. so that the fan-out line214may transmit a data signal to the data line Dt corresponding to the fan-out line214. It will be noted that “the data line Dt corresponding to the fan-out line214” here refers to the data line Dt electrically connected to the fan-out line214.

In the array substrate300provided in the implementations, referring toFIG.1F, the first fan-out region B1is disposed in the peripheral area BB, the first fan-out region B1is not folded onto the back surface of the display panel200after the bending region B2, the second fan-out region B3, the test circuit region B4, the chip region B5and the bonding region B6are folded onto the back surface of the display panel, and thus the first fan-out region B1forms the bezel of the display panel200. In the array substrate300provided in the implementation shown inFIG.1G, the fan-out lines214are gathered in the display area AA, which is equivalent to arranging the first fan-out region in the display area AA, so that the first fan-out region is not in the bezel of the display panel200after the bending region B2, the second fan-out region B3, the test circuit region B4, the chip region B5and the bonding region B6are folded onto the back surface of the display panel200. As a result, the bezel of the display panel200may be narrowed.

In some examples, the initial signal lines are disposed in the first source-drain metal layer SD1, and the first power supply signal lines Vdd and the data lines Dt are disposed in the second source-drain metal layer SD2, so that a distance between the data lines Dt and an underlying structure is relatively large. As a result, a capacitance of a capacitor formed by the data lines Dt and the underlying structure (e.g., the first gate metal layer Gate1, the second gate metal layer Gate2or the active film layer380) is relatively small, so that the display panel200may support high-frequency display. However, the first sub-line2141and the second sub-line2142of the fan-out line214are both disposed in a third source-drain metal layer. When the display panel200is manufactured, there is a need to add two masks specially for the fan-out lines214. For example, after the second source-drain metal layer SD2is manufactured, there is a need to manufacture a planarization layer to cover the second source-drain metal layer SD2; and then, the third source-drain metal layer is formed on the planarization layer. In order to ensure signal lines in the third source-drain metal layer to be electrically connected to underlying structures (e.g., the second source-drain metal layer SD2, the first source-drain metal layer SD1and the second gate metal layer Gate2), there is a need to punch the planarization layer to enable the third source-drain metal layer to be connected to the underlying structures (e.g., the second source-drain metal layer SD2, the first source-drain metal layer SD1and the second gate metal layer Gate2) through respective via holes. A mask is needed for punching the planarization layer, and another mask is needed for manufacturing the fan-out lines214. Thus, two additional masks are needed for forming the fan-out lines214. Therefore, in these examples, when the array substrate300is manufactured, a relatively large number of masks are needed, so that a cost is relatively high.

In summary, the array substrate300in the display panel200provided in the above examples cannot achieve the high-frequency design by using a relatively small number of masks.

In light of this, some embodiments of the present disclosure provide an array substrate300, referring toFIGS.2A and2B, the array substrate300includes a substrate310, a plurality of first power supply signal lines Vdd, a plurality of data lines Dt and a plurality of fan-out lines320.

Referring toFIGS.2A and2B, the substrate310has a display area AA and a peripheral area BB, and the display area AA has sub-pixel regions330arranged in a plurality of rows and a plurality of columns. The sub-pixel regions330in the display area AA may be arranged in an array. Pixel driving circuits211may be respectively disposed in the sub-pixel regions330, so that the pixel driving circuits211are arranged in the array on the substrate310.

A first power supply signal line Vdd and a data line Dt both corresponding to a same column of sub-pixel regions are all located within the column of sub-pixel regions, and the first power supply signal line Vdd and the data line Dt both corresponding to the same column of sub-pixel regions are all electrically connected to pixel driving circuits in the same column. It will be noted that “a first power supply signal line Vdd corresponding to a column of sub-pixel regions” refers to that an orthographic projection of the first power supply signal line Vdd on the substrate310is located within the column of sub-pixel regions. Similarly, “a data line Dt corresponding to a column of sub-pixel regions” refers to that an orthographic projection of the data line Dt on the substrate310is located within the column of sub-pixel regions.

The plurality of first power supply signal lines Vdd are located on a first side3101(as shown inFIG.1E) of the substrate310and located in the display area AA. The plurality of first power supply signal lines Vdd each extend in a first direction Y and are sequentially arranged in a second direction X. The second direction X intersects the first direction Y, and the second direction X and the first direction Y are both parallel to the substrate310. The first direction Y may be perpendicular to the second direction X. Sub-pixel regions330in each column of sub-pixel regions may be sequentially arranged in the first direction Y, and sub-pixel regions330in each row of sub-pixel regions may be sequentially arranged in the second direction X. The first power supply signal line Vdd extends in the first direction Y, so as to transmit a first power supply signal to the pixel driving circuits in the column of sub-pixel regions.

The plurality of data lines Dt are located on the first side3101of the substrate310and located in the display area AA. Referring toFIGS.2A and2B, the plurality of data lines Dt each extend in the first direction Y and are sequentially arranged in the second direction X. A data line Dt is adjacent to a first power supply signal line Vdd. The data line Dt extends in the first direction Y, so as to transmit a data signal to the respective pixel driving circuit in the column of sub-pixel regions.

The plurality of fan-out lines320are located on the first side3101of the substrate310. Referring toFIGS.2A and2B, a fan-out line320includes a first sub-line321and a second sub-line322. The first sub-line321extends in the first direction Y and extends from the peripheral area BB to the display area AA. The second sub-line322extends in the second direction X and is located in the display area AA. An end of the second sub-line322is electrically connected to the first sub-line321, another end of the second sub-line322is electrically connected to a data line Dt of the plurality of data lines Dt, and the second sub-line322is insulated from remaining data lines Dt of the plurality of data lines Dt.

In some examples, referring toFIG.2A, the plurality of fan-out lines320are electrically connected to a part of the plurality of data lines Dt in a one-to-one correspondence. The fan-out lines320each include a second sub-line322. It will be understood that the second sub-lines322may be electrically connected to the part of the plurality of data lines Dt in a one-to-one correspondence. In some examples, the data lines electrically connected to the fan-out lines320are respectively disposed on two sides, in the second direction X, of data lines not electrically connected to the fan-out lines320. In addition, a part of the data lines not electrically connected to the fan-out lines320and a part of first sub-lines321may be arranged alternately. That is, the part of the data lines not electrically connected to the fan-out lines320may be each located between two first sub-lines321.

In some other examples, referring toFIG.2B, the plurality of fan-out lines320are electrically connected to the plurality of data lines Dt in a one-to-one correspondence, and a fan-out line320may transmit a data signal to a data line Dt corresponding to the fan-out line320. The fan-out lines320each include a second sub-line322. It will be understood that the second sub-lines322may be electrically connected to the plurality of data lines Dt in a one-to-one correspondence.

The end of the second sub-line322is electrically connected to an end of the first sub-line321located in the display area AA, and the other end of the second sub-line322is electrically connected to the data line Dt corresponding thereto. The second sub-line322may cross data lines Dt not corresponding to the second sub-line322, and extend to the data line Dt corresponding to the second sub-line322and be electrically connected to the data line Dt. The second sub-line322is electrically connected to the data line Dt corresponding thereto and insulated from the data lines Dt that the second sub-line322crosses. It will be noted that a second sub-line322is electrically connected to one of the plurality of data lines Dt, the second sub-line322and the data line Dt that are electrically connected to each other correspond to each other, and a data line Dt and a second sub-line322that are not electrically connected to each other do not correspond to each other. It can be seen from the above that the term “cross” refers to that an orthographic projection of the second sub-line322on the substrate310intersects orthographic projections, on the substrate310, of the data lines Dt that the second sub-line322crosses. Referring toFIG.3A, in the region A3and the region A4, a second sub-line322crosses data lines Dt. In the region A5and the region A6, orthographic projections of second sub-lines322on the substrate310do not intersect orthographic projections of respective data lines Dt on the substrate310. That is, the second sub-lines322do not cross the respective data lines Dt.

In some examples, as shown inFIGS.2A and2B, there are M columns of sub-pixel regions and N rows of sub-pixel regions that are disposed in the substrate310. The N rows of sub-pixel regions sequentially arranged in the first direction Y are a first row L1of sub-pixel regions, a second row L2of sub-pixel regions, . . . , an N-th row LN of sub-pixel regions. The M columns of sub-pixel regions sequentially arranged in the second direction X are a first column R1of sub-pixel regions, a second column R2of sub-pixel regions, . . . , an M-th column RM of sub-pixel regions.

In some examples, the part of the data lines Dt are electrically connected to the fan-out lines320, respectively. In this case, the number of the fan-out lines320is less than M. Of course, in some other examples, as shown inFIG.2B, the plurality of data lines Dt are electrically connected to the fan-out lines320in a one-to-one correspondence. In this case, there are M data lines Dt disposed in the array substrate300, and thus there are M fan-out lines320, i.e., M second sub-lines322and M first sub-lines321, disposed in the array substrate300.

As shown inFIGS.2A and2B, in the second sub-lines322, a second sub-line32201that is electrically connected to a data line Dt01corresponding to the first column R1of sub-pixel regions crosses a data line Dt02corresponding to the second column R2of sub-pixel regions, a data line Dt03corresponding to the third column R3of sub-pixel regions and so on; the second sub-line32201is insulated from the data line Dt02corresponding to the second column R2of sub-pixel regions, the data line Dt03corresponding to the third column R3of sub-pixel regions and so on.

For example, an insulating layer may be provided between the second sub-line322and the data lines Dt that the second sub-line322crosses, so that the second sub-line322is insulated from the data lines Dt that the second sub-line322crosses.

In addition, referring toFIG.1F, in the display panel200provided in some implementations, the first fan-out region B1is disposed in the peripheral area BB, the first fan-out region B1is not folded onto the back surface of the display panel200after the bending region B2, the second fan-out region B3, the test circuit region B4, the chip region B5and the bonding region B6are folded onto the back surface of the display panel200, and thus the first fan-out region B1forms the bezel of the display panel200. In the array substrate300provided in some embodiments of the present disclosure, the fan-out lines320are gathered in the display area AA, which is equivalent to arranging the first fan-out region in the display area AA. As a result, after the bending region B2, the second fan-out region B3, the test circuit region B4, the chip region B5and the bonding region B6are folded onto the back surface of the display panel200, the bezel of the display panel200does not include the first fan-out region, so that the bezel of the display panel200may be narrowed.

Main structures of the data lines Dt are located on a side of the first power supply signal lines Vdd away from the substrate310. In some embodiments, the main structures of the data lines Dt are each a complete data line Dt. In some other embodiments, referring toFIG.3A, the main structures of the data lines Dt each include a plurality of main lines Dta; two adjacent main lines Dta are electrically connected to each other via a jumper wire Dtb, so as to constitute a complete data line Dt. The main structures of the data lines Dt are located on the side of the first power supply signal lines Vdd away from the substrate310. Thus, a distance between the data lines Dt and an underlying structure (e.g., the second gate metal layer Gate2, the first gate metal layer Gate1or the active film layer380) is relatively large, so that a capacitance created between the data lines Dt and the underlying structure is relatively small. As a result, it is possible to support the high-frequency display of the display panel200. For example, the first power supply signal lines Vdd are disposed in the first source-drain metal layer SD1, and the main structures of the data lines Dt are disposed in the second source-drain metal layer SD2.

The first sub-line321and the main structures of the data lines Dt are disposed in a same layer. The main structures of the data lines Dt and the first sub-line321are disposed in the same layer, which makes it possible to manufacture the main structures of the data lines Dt and the first sub-line321by using a same mask, so that there is no need to provide another mask for manufacturing the first sub-line321. Therefore, a relatively small number of masks may be used during a process of manufacturing the display panel200, thereby saving the cost.

Referring toFIGS.2A and2B, an orthographic projection, on the substrate310, of a first sub-line321passing through a column of sub-pixel regions330is substantially located between an orthographic projection, on the substrate310, of a corresponding first power supply signal line Vdd passing through the column of sub-pixel regions330and an orthographic projection, on the substrate310, of a data line Dt passing through the column of sub-pixel regions330.

It will be noted that “a first sub-line321passing through a column of sub-pixel regions” refers to that an orthographic projection of the first sub-line321on the substrate310is located within a part or all of the sub-pixel regions in the column. Similarly, “a corresponding first power supply signal line Vdd passing through a column of sub-pixel regions” refers to that an orthographic projection of the first power supply signal line Vdd on the substrate310is located within a part or all of the sub-pixel regions in the column; “a data line Dt passing through a column of sub-pixel regions” refers to that an orthographic projection of the data line Dt on the substrate310is located within a part or all of the sub-pixel regions in the column.

Moreover, it will be noted that a description that the orthographic projection, on the substrate310, of the first sub-line321passing through the column of sub-pixel regions is substantially located between the orthographic projection, on the substrate310, of the corresponding first power supply signal line Vdd passing through the column of sub-pixel regions and the orthographic projection, on the substrate310, of the data line Dt passing through the column of sub-pixel regions may include but is not limited to the following cases: {circle around (1)} the orthographic projection of the first sub-line321is located between the orthographic projection of the first power supply signal line Vdd and the orthographic projection of the data line Dt that are located within the same column of sub-pixel regions; {circle around (2)} a main body portion of the orthographic projection of the first sub-line321is located between the orthographic projection of the first power supply signal line Vdd and the orthographic projection of the data line Dt that are located in the same column of sub-pixel regions; that is, the first sub-line321may partially overlap with the first power supply signal line Vdd and/or the data line Dt of which the first power supply signal line Vdd and the data line Dt are located in the same column of sub-pixel regions; {circle around (3)} an orthographic projection of a middle line of the first sub-line321is located between an orthographic projection of a middle line of the first power supply signal line Vdd and an orthographic projection of a middle line of the data line Dt that are located in the same column of sub-pixel regions.

In some examples, multiple first sub-lines321may each pass through a different column of sub-pixel regions. In this case, a first sub-line321corresponds to a column of sub-pixel regions. In some other examples, multiple first sub-lines321may each pass through a same column of sub-pixel regions. In this case, the column of sub-pixel regions correspond to the multiple first sub-lines321. In some examples, referring toFIGS.3A and3B, a column of sub-pixel regions correspond to two first sub-lines321, and the two first sub-lines321corresponding to the column of sub-pixel regions are respectively a first first sub-line321A and a second first sub-line321B.

Referring toFIGS.3A and3B, the first first sub-line321A, a first power supply signal line Vdd and a data line Dt all correspond to the same column of sub-pixel regions, and an orthographic projection of the first first sub-line321A on the substrate310is located between an orthographic projection of the first power supply signal line Vdd on the substrate310and an orthographic projection of the data line Dt on the substrate310. Therefore, the first first sub-line321A is non-overlapping with the first power supply signal line Vdd, so that crosstalk created between a data signal on the first first sub-line321A and a first power supply signal on the first power supply signal line Vdd may be avoided.

In summary, the array substrate300provided in the embodiments of the present disclosure may satisfy the requirement for the high-frequency display of the display panel200; furthermore, there is no need to provide additional mask for the provision of the first sub-line321. As a result, the number of masks used during the process of manufacturing the display panel200is reduced, thereby saving the cost.

Based on the array substrate300provided in some of the above embodiments, a wiring manner of the fan-out lines320disposed in the array substrate300will be described below.

In some embodiments, referring toFIGS.2A,2B and4A, the peripheral area BB includes a lead-out region B10located on a side of the display area AA. The first sub-lines321each extend from the lead-out region B10to the display area AA.

In some examples, referring toFIG.4A, the lead-out region B10includes a bending region B2, a second fan-out region B3and a test circuit region B4. A chip region B5is provided on a side of the lead-out region B10away from the display area AA. The first sub-lines321may each extend to the chip region B5, and the first sub-lines321are bonded and electrically connected to a driver IC in the chip region B5. In some examples, referring toFIG.2A, the plurality of fan-out lines320are electrically connected to the part of the plurality of data lines Dt in a one-to-one correspondence. The data lines Dt not electrically connected to the fan-out lines320each extend to the chip region B5through the lead-out region B10.

In some other examples, the lead-out region B10does not include the bending region B2, and there is no chip region B5provided on the side of the lead-out region B10away from the display area AA. In this case, referring toFIG.4B, the lead-out region B10includes the second fan-out region B3and the test circuit region B4, and a bonding region B6is provided on the side of the lead-out region B10away from the display area AA. In this case, the first sub-lines321may each extend to the bonding region B6through the lead-out region B10and be electrically connected to a plurality of pins in the bonding region B6. The driver IC is bonded to a flexible circuit board, and the flexible circuit board is bonded to the plurality of pins in the bonding region. In this example, the flexible circuit board is folded onto the back surface of the display panel200. In some examples, referring toFIG.2A, the plurality of fan-out lines320are electrically connected to the part of the plurality of data lines Dt in a one-to-one correspondence. The data lines Dt not electrically connected to the fan-out lines320each extend to the bonding region B6through the lead-out region B10.

In some embodiments, referring toFIGS.2A,2B,4A and4B, a direction from a center line340, in the second direction X, of the display area AA to any side of the display area AA in the second direction X is a first setting direction. The display area AA is divided into two display sub-regions by the center line340of the display area AA in the second direction X, and a direction from the center line340to any display sub-region is the first setting direction. For example, the two display sub-regions are a first region A1and a second region A2. In the first region A1, a direction represented by the arrow C1is the first setting direction; in the second region A2, a direction represented by the arrow C2is the first setting direction.

In some examples, referring toFIGS.2A,2B,4A and4B, lengths of portions, located in the display area AA, of the first sub-lines321sequentially decrease in the first setting direction. In any display sub-region, lengths of portions, located in the display area AA, of first sub-lines321sequentially decrease in the first setting direction. That is, in the first region A1, lengths, in the first direction Y, of portions, located in the display area AA, of first sub-lines321sequentially decrease in the first setting direction C1; in the second region A2, lengths, in the first direction Y, of portions, located in the display area AA, of other first sub-lines321sequentially decrease in the first setting direction C2.

In each display sub-region, referring toFIGS.2A and2B, the first sub-lines321each extend to a different row of sub-pixel regions. Thus, the second sub-lines322electrically connected to the first sub-lines321each correspond to a different row of sub-pixel regions, so that the second sub-lines322each extend to a different data line Dt and is electrically connected to the respective data line Dt.

A direction from an end of a second sub-line322connected to a first sub-line321to a data line Dt electrically connected to the second sub-line322is an extending direction of the second sub-line322. Extending directions of second sub-lines322respectively located on two sides of the center line340are opposite to each other. The extending direction of the second sub-line322is the same as a first setting direction of a display sub-region where the second sub-line322is located.

In some embodiments, as shown inFIGS.2A and2B, a length G1of at least one first sub-line321is not greater than half a dimension G2of the display area AA in the first direction Y.

In some examples, lengths of some of the first sub-lines321may be each not greater than half the dimension of the display area AA in the first direction Y, and lengths of remaining first sub-lines321may be each greater than half the dimension of the display area AA in the first direction Y. In some other examples, lengths of all the first sub-lines321may be each not greater than half the dimension of the display area AA in the first direction Y.

Of course, in some other implementations, the lengths of all the first sub-lines321may be each greater than half the dimension of the display area AA in the first direction Y.

For example, there are M columns of sub-pixel regions and N rows of sub-pixel regions that are disposed in the substrate310. In some examples, referring toFIG.2A, the plurality of fan-out lines320may be electrically connected to a part of all the data lines Dt in a one-to-one correspondence. In this case, the number of the fan-out lines320may be less than M. In some other examples, referring toFIG.2B, the plurality of fan-out lines320may be electrically connected to all the data lines Dt in a one-to-one correspondence. In this case, there are M data lines Dt disposed in the array substrate300, and thus there are M fan-out lines320disposed in the array substrate300. That is, M second sub-lines322may be electrically connected to M first sub-lines321in a one-to-one correspondence.

For example, referring toFIGS.2A and2B, the dimension G2of the display area AA in the first direction Y is greater than a dimension of the display area AA in the second direction X, and in the display area AA, the number of the rows of the sub-pixel regions330is greater than the number of the columns of the sub-pixel regions330. That is, N is greater than M.

In some examples, referring toFIGS.2A and2B, a row of sub-pixel regions may correspond to multiple second sub-lines322, and the multiple second sub-lines322corresponding to the same row of sub-pixel regions each pass through different sub-pixel region(s)330. That is, orthographic projections, on the substrate310, of the multiple second sub-lines322corresponding to the same row of sub-pixel regions are non-overlapping with each other. Therefore, multiple first sub-lines321may be enabled to extend to a same row of sub-pixel regions, which may reduce a maximum dimension of the first sub-lines321in the first direction Y. For example, a row of sub-pixel regions may correspond to two second sub-lines322, and correspondingly, the two of the first sub-lines321may extend to the same row of sub-pixel regions. For example, a first sub-line321, the farthest away from the center line340, in the first region A1and a first sub-line321, the farthest away from the center line340, in the second region A2both extend to the first row L1of sub-pixel regions. In this case, the first row L1of sub-pixel regions correspond to two second sub-lines321.

Based on the examples where a row of sub-pixel regions may correspond to two second sub-lines321, referring toFIG.2A, in a case where the plurality of fan-out lines320may be electrically connected to the part of all the data lines Dt in a one-to-one correspondence, the number of the second sub-lines322is less than M. In this case, in the N rows of sub-pixel regions, the number of rows of sub-pixel regions where the second sub-lines322are disposed is less than M/2. For convenience of description, the number of the rows of the sub-pixel regions where the second sub-lines322are disposed is defined as Q. Therefore, the first sub-line321with the maximum dimension in the first direction Y may pass through at least the Q rows of sub-pixel regions; where Q is less than M/2.

Referring toFIG.2B, in a case where the plurality of fan-out lines320may be electrically connected to all the data lines Dt in a one-to-one correspondence, in the N rows of sub-pixel regions, M/2 rows of sub-pixel regions may overlap with orthographic projections of the M second sub-lines322on the substrate310, and remaining (N-M/2) rows of sub-pixel regions are non-overlapping with the orthographic projections of the second sub-lines322on the substrate310. In this case, the first sub-line321with the maximum dimension in the first direction Y passes through at least the M/2 rows of sub-pixel regions.

In some examples, referring toFIGS.2A and2B, in a display sub-region, two adjacent first sub-lines321may respectively extend to two adjacent rows of sub-pixel regions, and a second sub-line322connected to the first sub-line321that is the farthest away from the center line340extends in the first row L1of sub-pixel regions.

In this case, referring toFIG.2A, in the case where the plurality of fan-out lines320may be electrically connected to the part of all the data lines Dt in a one-to-one correspondence, the first sub-line321with the maximum dimension in the first direction Y may pass through from the first row L1of sub-pixel regions to a Q-th row of sub-pixel regions. That is, the first sub-line321with the maximum dimension in the first direction Y passes through Q rows of sub-pixel regions. N is greater than M (which means that M/2 is less than N/2), and Q is less than M/2, so that the first sub-line321with the maximum dimension in the first direction Y passes through less than N/2 sub-pixel regions330. As a result, a length, in the display area AA, of any first sub-line321is not greater than half the dimension of the display area AA in the first direction Y.

Referring toFIG.2B, in the case where the plurality of fan-out lines320may be electrically connected to all the data lines Dt in a one-to-one correspondence, the first sub-line321with the maximum dimension in the first direction Y may pass through from the first row L1of sub-pixel regions to an (M/2)-th row of sub-pixel regions. That is, the first sub-line321with the maximum dimension in the first direction Y passes through M/2 rows of sub-pixel regions. N is greater than M (which means that M/2 is less than N/2), so that the first sub-line321with the maximum dimension in the first direction Y passes through less than N/2 sub-pixel regions330. As a result, a length, in the display area AA, of any first sub-line321is not greater than half the dimension of the display area AA in the first direction Y.

In some other examples, in a display sub-region, two adjacent first sub-lines321may respectively extend to two adjacent rows of sub-pixel regions, and there may be multiple rows of sub-pixel regions between a second sub-line322that is closest to the lead-out region B10and the lead-out region B10. For example, there may be P rows of sub-pixel regions between the second sub-line322that is closest to the lead-out region B10and the lead-out region B10. In this case, the first sub-line321with the maximum dimension in the first direction Y passes through (P+M/2) rows of sub-pixel regions.

In yet other examples, in a display sub-region, two adjacent first sub-lines321may respectively extend to two rows of sub-pixel regions that are arranged at intervals. In this case, two respective second sub-lines322, adjacent to each other in the first direction Y, are respectively disposed in the two rows of sub-pixel regions that are arranged at intervals. For example, there are one or more rows of sub-pixel regions between two rows of sub-pixel regions where two second sub-lines322, adjacent to each other in the first direction Y, are respectively located.

In yet other examples, in a display sub-region, there is none of the rows of sub-pixel regions or one row of sub-pixel regions or multiple rows of sub-pixel regions between two rows of sub-pixel regions where two second sub-lines322, adjacent to each other in the first direction Y, are respectively located. In a case where there is none of the rows of sub-pixel regions between two rows of sub-pixel regions where two second sub-lines322, adjacent to each other in the first direction Y, are respectively located, the two rows of sub-pixel regions, in which the two second sub-lines322adjacent to each other in the first direction Y are respectively located, are adjacent to each other.

In some embodiments, referring toFIGS.2A and2B, the closer a first sub-line321is to the center line340of the display area AA in the second direction X, the farther a second sub-line322connected to the first sub-line321is away from the lead-out region B10. The farther the second sub-line322is away from the lead-out region B10, the closer a data line Dt connected to the second sub-line322is to the center line340of the display area AA in the second direction X.

For example, the center line340of the display area AA in the second direction X extends in the first direction Y.

In the display sub-region, in the first setting direction, the second sub-lines322to which the first sub-lines321are electrically connected gradually approach the lead-out region B10. A second sub-line322, to which a first sub-line321the closest to the center line340is electrically connected, is the farthest away from the lead-out region B10. Therefore, the second sub-lines322to which the first sub-lines321are electrically connected do not overlap. The first sub-line321the farthest away from the center line340of the display area AA in the second direction X is electrically connected to a data line Dt the farthest away from the center line340, and a dimension of the first sub-line321in the first direction Y is the smallest; the first sub-line321the closest to the center line340of the display area AA in the second direction X is electrically connected to a data line Dt the closest to the center line340, and a dimension of the first sub-line321in the first direction Y is the largest.

For example, referring toFIGS.2A and2B, the first row L1of sub-pixel regions correspond to a second sub-line32201the closest to the lead-out region B10, and the data line Dt01to which the first column R1of sub-pixel regions correspond is electrically connected to the second sub-line32201to which the first row L1of sub-pixel regions correspond, so that the data line Dt01to which the first column R1of sub-pixel regions correspond does not cross any one of the second sub-lines322. The data line Dt02to which the second column R2of sub-pixel regions correspond is electrically connected to a second sub-line32202to which the second row L2of sub-pixel regions correspond, so that the data line Dt02to which the second column R2of sub-pixel regions correspond may cross the second sub-line32201to which the first row L1of sub-pixel regions correspond, and so on.

In the above wiring manner, the fan-out lines320may be relatively short, which may save the cost.

In some embodiments, referring toFIG.4A, all the first sub-lines321are substantially symmetric with the center line340of the display area AA in the second direction X as a line of symmetry. Moreover, all the second sub-lines322are substantially symmetric with the center line340of the display area AA in the second direction X as a line of symmetry. In the embodiments of the present disclosure, the phrase “substantially symmetric” refers to that a difference between a distance between a structure located on a side of the center line340and the center line340and a distance between a structure located on another side of the center line340and the center line340is within 5%.

Referring toFIG.4A, the fan-out lines320are symmetrically arranged in the array substrate300, and the first sub-lines321may be gathered in a middle of the lead-out region B10. The center line340of the display area AA in the second direction X is also a center line340of the lead-out region B10in the second direction X, and the middle of the lead-out region B10is a partial region extending to the two sides with the center line340of the lead-out region B10in the second direction X as the center, and a dimension, in the second direction X, of the middle of the lead-out region B10is less than a dimension, in the second direction X, of the entire lead-out region B10.

All the first sub-lines321and all the second sub-lines322are each substantially symmetric with the center line340of the display area AA in the second direction X as the line of symmetry. That is, the fan-out lines320are substantially symmetric with the center line340as the line of symmetry. As a result, a total structure of the fan-out lines320is regular, which facilitates processing, so that convenience of production and processing is improved.

In some embodiments, referring toFIGS.3A and3B, a main structure of the data line Dt includes a plurality of main lines Dta, and the data line Dt further includes at least one jumper wire Dtb; the jumper wire Dt and the first power supply signal line Vdd are disposed in a same layer; in the same data line Dt, the jumper wire(s) Dtb and the main lines Dta are alternately electrically connected to one another through via holes K.

The main lines Dta are disposed on the side of the first power supply signal line Vdd away from the substrate310, and the jumper wire(s) Dtb and the first power supply signal line Vdd are disposed in the same layer. Thus, the main lines Dta are disposed in a layer different from a layer where the jumper wire(s) Dtb are disposed, and the adjacent main line Dta and jumper wire Dtb may be electrically connected to each other through a via hole K.

In some examples, a dimension, in the first direction Y, of the main line Dta is greater than a dimension, in the first direction Y, of the jumper wire Dtb.

In some examples, each data line Dt includes main lines Dta and jumper wire(s) Dtb that are arranged alternately. In some other examples, some data lines Dt (e.g., the data line Dt01to which the first column R1of sub-pixel regions correspond as shown inFIGS.2A and2B) each include only a main line Dta and no jumper wire Dtb; remaining data lines Dt (e.g., the data line Dt02to which the second column R2of sub-pixel regions correspond and the data line Dt03to which the third column R3of sub-pixel regions correspond as shown inFIG.2B) each include main lines Dta and jumper wires Dtb that are arranged alternately.

In some examples, referring toFIG.3B, a data line Dt may be provided with a jumper wire Dtb only at a position where the data line Dt passes through a second sub-line322. In some other examples, referring toFIG.3A, a data line Dt may be further provided with a jumper wire Dtb at another position, in addition to a position where the data line Dt passes through a second sub-line322.

In some embodiments, referring toFIG.3A, the second sub-lines322and the main lines Dta are disposed in the same layer, and each of at least one second sub-line322crosses a jumper wire Dtb of at least one data line Dt. Here, the term “cross” refers to that an orthographic projection of the second sub-line322on the substrate310intersects an orthographic projection of the jumper wire Dtb on the substrate310, and an orthographic projection, on the substrate310, of an end of the second sub-line322away from a respective first sub-line321does not coincide with the orthographic projection of the jumper wire Dtb on the substrate310. For example, referring toFIG.3A, in the region A3and the region A4, a second sub-line322crosses jumper wires Dtb. In the region A5and the region A6, data lines Dt each coincide with an end of a respective second sub-line322away from a respective first sub-line321. That is, in the region A5and the region A6, the second sub-lines322do not cross the respective data lines Dt.

Data line(s) Dt each further include at least one jumper wire Dtb, and at least one second sub-line322crosses a jumper wire Dtb of at least one data line Dt. In some examples, it is possible that only a single data line Dt of the plurality of data lines Dt is provided with jumper wire(s) Dtb, and a second sub-line322crosses the single data line Dt. In some other examples, it is possible that some of the plurality of data lines Dt are each provided with jumper wire(s) Dtb, and a second sub-line322may cross all the jumper wires Dtb of the plurality of data lines Dt. In yet other examples, it is possible that at least some of the plurality of data lines Dt are each provided with jumper wire(s) Dtb, and the second sub-lines322may respectively cross all the jumper wires Dtb of the plurality of data lines Dt. In yet other examples, it is possible that at least some of the plurality of data lines Dt are each provided with jumper wire(s) Dtb, the second sub-lines322may respectively cross some of all the jumper wires Dtb of the plurality of data lines Dt, and an orthographic projection, on the substrate310, of the rest of all the jumper wires Dtb of the plurality of data lines Dt is non-overlapping with the orthographic projections of the second sub-lines322on the substrate310.

The second sub-lines322and the main lines Dta are disposed in the same layer, and the first sub-lines321and the main lines Dta are disposed in the same layer, so that the fan-out lines320and the main lines Dta are disposed in the same layer. Thus, the fan-out lines320and the main lines Dta may be formed during a same process by using a same mask, so that there is no need to provide additional mask for the fan-out lines320. As a result, the number of masks used during the process of manufacturing the display panel200is reduced, thereby saving the cost. For example, referring toFIGS.3A and3B, the first sub-lines321, the second sub-lines322and the main lines Dta are disposed in the second source-drain metal layer SD2.

The second sub-lines322and the main lines Dta are disposed in the same layer, and the jumper wires Dtb are disposed in the layer different from the layer where the main lines Dta are disposed. Thus, the second sub-lines322are disposed in the layer different from the layer where the jumper wires Dtb are disposed. A second sub-line322may cross jumper wire(s) Dtb of data lines Dt not corresponding thereto, so that the second sub-line322may be insulated from the data lines Dt not corresponding thereto. For example, referring toFIGS.3A and3B, the jumper wires Dtb are disposed in the first source-drain metal layer SD1.

An arrangement manner of the jumper wires Dtb is described in some of the above embodiments, and a connection manner between the data line Dt and the second sub-line322will be described below based on the embodiments in which the data line Dt includes the jumper wire(s) Dtb.

In some embodiments, a second sub-line322may be electrically connected to a main line Dta of a data line Dt to which the second sub-line322corresponds. For example, referring toFIG.3A, a second sub-line322ncorresponds to a data line Dtn; at a position where the data line Dtn is electrically connected to the second sub-line322n, the data line Dtn is provided with no jumper wire Dtb, but provided with a main line Dta. Thus, the second sub-line322nis electrically connected to the main line Dta of the data line Dtn, and the main line Dta of the data line Dtn passes through an end of the second sub-line322n.

In some embodiments, as shown inFIG.5, a minimum closed graphic region where all second sub-lines322, located on a same side of the center line340of the display area AA in the second direction X, are located is a first wiring region350. Referring toFIG.5, an end of a second sub-line322connected to a first sub-line321is a third end3221, and another end of the second sub-line322away from the first sub-line321is a fourth end3222. The first wiring region350includes a first edge351and a second edge352. The first edge351passes through third ends3221of multiple second sub-lines322. The second edge352passes through fourth ends3222of multiple second sub-lines322.

It will be noted that the first edge351is a straight line. In some examples, in a display sub-region, the first edge351may pass through third ends3221of all the second sub-lines322. In some other examples, the first edge351may be a fitted straight line of the third ends3221of all the second sub-lines322. In this case, in the display sub-region, the first edge351may pass through only third ends3221of some of all the second sub-lines322, and third ends3221, that the first edge351not passes through, of remaining second sub-lines322may be distributed on two sides of the first edge351; alternatively, in the display sub-region, the third ends3221of all the second sub-lines322are distributed on the two sides of the first edge351.

Similarly, the second edge352is a straight line. In some examples, in a display sub-region, the second edge352may pass through fourth ends3222of all the second sub-lines322. In some other examples, the second edge352may be a fitted straight line of the fourth ends3222of all the second sub-lines322. In this case, in the display sub-region, the second edge352may pass through only fourth ends3222of some of all the second sub-lines322, and fourth ends3222, that the second edge352not passes through, of remaining second sub-lines322may be distributed on two sides of the second edge352; alternatively, in the display sub-region, the fourth ends3222of all the second sub-lines322are distributed on the two sides of the second edge352.

The first edge351and the second edge352may intersect at a point, and two ends of the second sub-line32201the closest to the lead-out region B10may respectively intersect the first edge351and the second edge352. The first edge351, the second edge352and the second sub-line32201that is the closest to the lead-out region B10may enclose the first wiring region350.

In some examples, the two sides of the center line340, in the second direction X, of the display area AA are each provided with a first wiring region350.

For example, referring toFIG.5, the first wiring region350may be an obtuse triangle region.

In some other examples, the closer a first sub-line321is to the center line340of the display area AA in the second direction X, the farther a second sub-line322to which the first sub-line321is connected is away from the lead-out region B10; the farther a second sub-line322is away from the lead-out region B10, the farther a data line Dt to which the second sub-line322is connected is away from the center line340of the display area AA in the second direction X. In this case, the first wiring region350is an acute triangle region.

The first wiring region350where the second sub-lines322are located is described in some of the above embodiments, and a second wiring region360where first sub-lines321are located will be described below.

In some embodiments, as shown inFIG.5, a minimum closed graphic region, in which all first sub-lines321located on a same side of the center line340, in the second direction X, of the display area AA are located, is a second wiring region360.

For example, referring toFIG.5, an end of a first sub-line321connected to a second sub-line322is a first end3211; the second wiring region360includes a third edge361. In a display sub-region, the third edge361passes through first ends3211of multiple first sub-lines321. It will be noted that, in the display sub-region, the third edge361may pass through only first ends3211of some of all the first sub-lines321. In this case, the third edge361may be a fitted straight line of first ends3221of all the first sub-lines321. The first ends3211of the first sub-lines321are connected to the third ends3221of the respective second sub-lines322, so that the third edge361coincides with the first edge351.

The third edge361includes a fifth end3611and a sixth end3612that are opposite to each other, the fifth end3611is connected to the first sub-line321the farthest away from the center line340, and the sixth end3612intersects the center line340.

The third edge361, the center line340, the first sub-line321the farthest away from the center line340and a partial edge363of the display area AA may enclose the second wiring region360.

For example, referring toFIG.5, the second wiring region360is a right trapezoid region.

In some embodiments, referring toFIGS.7to10, the obtuse triangle region has two obtuse angle edges, an obtuse angle edge, with a relatively large length, coincides with an oblique edge of the right trapezoid region, and the length of the obtuse angle edge, with the relatively large length, is equal to a length of the oblique edge of the right trapezoid region.

For example, the two obtuse angle edges of the obtuse triangle region are the first edge351and the second sub-line322that is the closest to the lead-out region B10, a length of the first edge351is greater than a length of the second sub-line322the closest to the lead-out region B10, and thus the obtuse angle edge, with the relatively large length, of the obtuse triangle region is the first edge351. The third edge361is the oblique edge of the right trapezoid region, and the third edge361and the first edge351coincide with each other and have a same length.

An arrangement manner of the jumper wires Dtb will be described below with reference to the first wiring region350and the second wiring region360.

In some embodiments, as shown inFIGS.6to10, at least a portion, located within the first wiring region350, of each data line Dt passing through the first wiring region350is provided with jumper wire(s) Dtb.

In some examples, only the portion, located within the first wiring region350, of each data line Dt passing through the first wiring region350is provided with the jumper wire(s) Dtb, so that the number of jumper wires Dtb provided in each data line Dt is relatively small. As a result, each data line Dt has relatively small loading.

For example, referring toFIG.7, of each data line Dt passing through the first wiring region350, only the portion located within the first wiring region350is provided with jumper wires Dtb, and portions located outside the first wiring region350are each a main line Dta.

For example, except for a designated sub-pixel region, a data line Dt is provided with a jumper wire Dtb at each portion passing through a sub-pixel region330. An orthographic projection, on the substrate310, of the data line Dt and an orthographic projection, on the substrate310, of a second sub-line322corresponding to the data line Dt intersect in the designated sub-pixel region, and the orthographic projection, on the substrate310, of the data line Dt and an orthographic projection, on the substrate310, of a second sub-line322not corresponding to the data line Dt may intersect in another sub-pixel region other than the designated sub-pixel region. In addition, it will be noted that a dimension, in the first direction Y, of a jumper wire Dtb is less than a dimension, in the first direction Y, of a sub-pixel region330. That is, the jumper wire Dtb cannot pass through the entire sub-pixel region330.

In some embodiments, the direction from the center line340, in the second direction X, of the display area AA to any side, in the second direction X, of the display area AA is the first setting direction; numbers of jumper wires Dtb respectively included in all data lines Dt firstly increase and then decrease in the first setting direction.

Referring toFIG.7,FIG.7shows a wiring manner in the first region A1in some embodiments; in the first region A1, the numbers of jumper wires Dtb respectively included in all the data lines Dt firstly increase and then decrease in the first setting direction C1.

In some examples, referring toFIGS.2A,2B and5, in a display sub-region, the numbers of second sub-lines322that the data lines Dt sequentially arranged in the first setting direction respectively crosses firstly increase and then decrease. For example, the jumper wires Dtb may be disposed only in the first wiring region350, so that the number of jumper wires Dtb disposed in a data line Dt is equal to the number of second sub-lines322that the data line Dt crosses. In this case, the numbers of jumper wires Dtb respectively disposed in the data lines Dt passing through the first wiring region350firstly increase and then decrease in the first setting direction.

The above embodiments will be described by considering the first region A1as an example. Referring toFIG.5, in the first region A1, a data line Dt07to which the seventh column R7of sub-pixel regions correspond crosses one second sub-line322, and correspondingly, the data line Dt07may be provided with one jumper wire Dtb therein; a data line Dt06to which the sixth column R6of sub-pixel regions correspond crosses two second sub-lines322, and correspondingly, the data line Dt06may be provided with two jumper wires Dtb therein; a data line Dt05to which the fifth column R5of sub-pixel regions correspond crosses three second sub-lines322, and correspondingly, the data line Dt05may be provided with three jumper wires Dtb therein.

A data line Dt04to which the fourth column R4of sub-pixel regions correspond crosses three second sub-lines322, and correspondingly, the data line Dt04may be provided with three jumper wires Dtb therein; the data line Dt03to which the third column R3of sub-pixel regions correspond may cross the second sub-line32201to which the first row L1of sub-pixel regions correspond and the second sub-line32202to which the second row L2of sub-pixel regions correspond (that is, the data line Dt03to which the third column R3of sub-pixel regions correspond may cross two second sub-lines322), and correspondingly, the data line Dt03is provided with two jumper wires Dtb therein; the data line Dt02to which the second column R2of sub-pixel regions correspond may cross the second sub-line32201to which the first row L1of sub-pixel regions correspond (that is, the data line Dt02to which the second column R2of sub-pixel regions correspond may cross one second sub-line322), and correspondingly, the data line Dt02is provided with one jumper wire Dtb therein; the data line Dt01to which the first column R1of sub-pixel regions correspond does not cross any one second sub-line322, and correspondingly, the data line Dt01is provided with no jumper wire Dtb therein.

In some embodiments, the jumper wires Dtb may be disposed only in the first wiring region350. In some other embodiments, referring toFIGS.8to10, of each data line Dt passing through the first wiring region350, not only the portion located within the first wiring region350is provided with the jumper wires Dtb, but also the portion located outside the first wiring region350is provided with the jumper wires Dtb. For example, the number of jumper wires Dtb in each data line Dt passing through the first wiring region350may be equal, so that the loading of each data line Dt is the same. In this example, referring toFIG.3A, in addition to a position where the data line Dt passes through a second sub-line322, the data line Dt may be further provided with a jumper wire Dtb at another position.

In some embodiments, referring toFIGS.7to10, of all the data lines Dt passing through the first wiring region350, a data line of which a portion located within the first wiring region350has the greatest number of jumper wires Dtb is a first-type data line Dtc, and data lines other than the first-type data line Dtc are second-type data lines Dtd.

The number of jumper wires Dtb included in the portion, located within the first wiring region350, of the first-type data line Dtc is greater than the number of jumper wires Dtb included in a portion, located within the first wiring region350, of each second-type data line Dtd.

For example, referring toFIG.5, in the first region A1, the first sub-line321the farthest away from the center line340is a designated first sub-line321C. In the plurality of data lines Dt, two data lines Dt (i.e., the data line Dt04and the data line Dt05) adjacent to the designated first sub-line321C each pass through the first wiring region350and cross the greatest number of second sub-lines322, which means that portions, located within the first wiring region350, of the two data lines Dt adjacent to the designated first sub-line321C each have the greatest number of jumper wires Dtb, so that the two data lines Dt adjacent to the designated first sub-line321C are each the first-type data line Dtc.

In some embodiments, referring toFIGS.8to10, a portion, located outside the first wiring region350, of each second-type data line Dtd is provided with jumper wire(s) Dtb. The number of jumper wires Dtb included in each second-type data line Dtd is equal to the number of jumper wires Dtb included in the first-type data line Dtc. Thus, the number of jumper wires Dtb in each data line Dt passing through the first wiring region350is equal, so that the loading of each data line Dt passing through the first wiring region350is the same.

In some embodiments, referring toFIG.5, the end of the first sub-line321connected to the respective second sub-line322is the first end3211, and the other end of the first sub-line321is a second end3212; a direction from the second end3212to the first end3211is a second setting direction D. The direction represented by the arrow D is the second setting direction.

Referring toFIG.9, of each second-type data line Dtd, the jumper wires Dtb located within the first wiring region350and the jumper wires Dtb located outside the first wiring region350are arranged in the second setting direction D. The jumper wires Dtb located outside the first wiring region350are all located on a side of the first wiring region350away from the lead-out region B10.

In some examples, referring toFIG.9, only the portion, located within the first wiring region350, of the first-type data line Dtc is provided with jumper wires Dtb; the portion, located within the first wiring region350, of the second-type data line Dtd is provided with jumper wires Dtb, and the portion, located outside the first wiring region350, of the second-type data line Dtd is also provided with jumper wires Dtb.

For example, the number of second sub-lines322that the first-type data line Dtc crosses is equal to the number of jumper wires Dtb in the first-type data line Dtc. The number of second sub-lines322that the second-type data line Dtd crosses is less than the number of second sub-lines322that the first-type data line Dtc crosses. In this way, after the second-type data line Dtd passes through the first wiring region350in the first direction Y, every time the second-type data line Dtd passes through a sub-pixel region330, a jumper wire Dtb is provided, until the number of jumper wires Dtb in the second-type data line Dtd is equal to the number of jumper wires Dtb in the first-type data line Dtc.

In some examples, referring toFIG.9, a rectangular region371is defined by taking the second sub-line322the closest to the lead-out region B10and a portion, passing through the first wiring region350, of a straight line on which the designated first sub-line321C is located as two adjacent edges; jumper wires Dtb of data lines Dt passing through the rectangular region371are all disposed in the rectangular region371. In the rectangular region371, except for a designated sub-pixel region, a data line Dt is provided with a jumper wire Dtb at each portion passing through a sub-pixel region330. It will be noted that a dimension, in the first direction Y, of a jumper wire Dtb is less than a dimension, in the first direction Y, of a sub-pixel region330, and the jumper wire Dtb cannot pass through the entire sub-pixel region330.

A parallelogram region372is defined by taking the first edge351and a portion, passing through the first wiring region350, of a straight line on which a designated second sub-line322C is located as two adjacent edges; jumper wires Dtb of data lines Dt passing through the parallelogram region372are all disposed in the parallelogram region372. In the parallelogram region372, except for a designated sub-pixel region, a data line Dt is provided with a jumper wire Dtb at each portion passing through a sub-pixel region330. The number of jumper wires Dtb in each data line Dt passing through the rectangular region371is equal to the number of jumper wires Dtb in each data line Dt passing through the parallelogram region372.

In addition to the above examples, in some other embodiments, referring to FIGS.8and10, a portion, located outside the first wiring region350, of each data line Dt passing through the first wiring region350is provided with jumper wires Dtb; the number of jumper wires Dtb in each data line Dt is equal. Jumper wires Dtb included in all the data lines Dt passing through the first wiring region350are arranged in rows in the first direction Y. The number of jumper wires Dtb in each data line Dt is equal, so that the loading of each data line Dt is the same.

For example, the data lines Dt passing through the first wiring region350include the first-type data line(s) Dtc and the second-type data lines Dtd; in each of the first-type data line(s) Dtc and the second-type data lines Dtd, the portion located within the first wiring region350and the portion located outside the first wiring region350are each provided with jumper wires Dtb.

Firstly, it will be understood that a second sub-line322and a data line Dt that are electrically connected to each other correspond to each other, and the data line Dt and the second sub-line322corresponding to each other intersect at a designated sub-pixel region. In some embodiments, the second sub-line322is electrically connected to a main line Dta of the data line Dt corresponding to the second sub-line322. For example, the data line Dt and the respective second sub-line322intersect at the designated sub-pixel region, and the second sub-line322is electrically connected to the main line Dta of the respective data line Dt. Thus, the data line Dt is provided with no jumper wire Dtb at a portion passing through the designated sub-pixel region corresponding to the data line Dt. That is, the portion of the data line Dt passing through the designated sub-pixel region330is the main line Dta.

In some examples, referring toFIG.8, as for each data line Dt, every time the data line Dt passes through a sub-pixel region330except for a respective designated sub-pixel region330(which is not shown inFIG.8and may refer to the sub-pixel region330inFIG.6), a jumper wire Dtb is provided. It will be noted that a dimension, in the first direction Y, of a jumper wire Dtb is less than a dimension, in the first direction Y, of a sub-pixel region330. That is, the jumper wire Dtb cannot pass through the entire sub-pixel region330. For example, there are N sub-pixel regions330in a column of sub-pixels, a data line Dt passes through the N sub-pixel regions330, and thus there are (N-1) jumper wires Dtb disposed in the data line Dt. In this case, the jumper wires Dtb of the plurality of data lines Dt may be arranged in rows in the second direction X.

In these embodiments, all sub-pixel regions330, except for designated sub-pixel regions330respectively corresponding to all the data lines Dt, are each provided with a jumper wire Dtb therein. In this case, referring toFIG.11A, a sub-pixel region330located in the second wiring region360is provided with main lines Dta, a jumper wire Dtb and a first sub-line321therein, but is provided with no second sub-line therein. Referring toFIG.11B, a sub-pixel region330located outside both the first wiring region350and the second wiring region360is provided with main lines Dta and a jumper wire Dtb therein, but is provided with no first sub-line and no second sub-line therein.

In some other embodiments, a sub-pixel region330located outside both the first wiring region350and the second wiring region360may be provided with a first sub-line and a second sub-line therein. The first sub-line and the second sub-line that in the sub-pixel region330located outside both the first wiring region350and the second wiring region360each serve as a dummy line, which is electrically connected to a first power supply signal line Vdd or a second power supply signal line Vss instead of being electrically connected to a data line Dt, so as to reduce a voltage drop of a signal on the first power supply signal line Vdd or the second power supply signal line Vss. Moreover, it is possible to avoid accumulation of static electricity generated by the first sub-line and the second sub-line that each serving as the dummy line.

In addition to the above embodiments, in some other embodiments, referring toFIG.10, the display area AA includes a rectangular region373, the second edge352is a diagonal of the rectangular region373, and an edge of the rectangular region373passes through the second sub-line322the closest to the lead-out region B10. In the rectangular region373, a data line Dt is provided with a jumper wire Dtb at each portion passing through a sub-pixel region except for a designated sub-pixel region, so that the number of jumper wires Dtb in each data line Dt is equal.

For example, the second sub-line322the closest to the lead-out region B10corresponds to an n-th row of sub-pixel regions, where n is greater than or equal to 1; the first sub-line321with the maximum dimension in the first direction Y passes through N/2 rows of sub-pixel regions. In this case, every time a portion, passing through from the n-th row of sub-pixel regions to a (n+N/2)-th row of sub-pixel regions, of a data line Dt passes through a sub-pixel region330except for a designated sub-pixel region corresponding to the data line Dt, a jumper wire Dtb may be provided. As a result, there are (N/2-1) jumper wires Dtb disposed in each data line Dt.

In some embodiments, there are multiple rows of sub-pixel regions between the second sub-line322the closest to the lead-out region B10and the lead-out region B10, and there is no jumper wire Dtb disposed in the multiple rows of sub-pixel regions located between the second sub-line322the closest to the lead-out region B10and the lead-out region B10.

The wiring manner of the fan-out lines320in the array substrate300is described above, and the pixel driving circuits included in the array substrate300will be described below.

In some embodiments, the array substrate300includes the plurality of pixel driving circuits211, and each pixel driving circuit211includes a plurality of transistors. In some embodiments, a structure of the pixel driving circuit in the embodiments of the present disclosure varies, which may be set according to actual needs. For example, the structure of the pixel driving circuit may include “2T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C”. Here, “T” represents a thin film transistor, the number before the “T” represents the number of thin film transistors; “C” represents a storage capacitor C, and the number before the “C” represents the number of storage capacitors C. Hereinafter, the description will be introduced by considering the pixel driving circuit with the structure of “7T1C” as an example.

Referring toFIG.12, the pixel driving circuit211may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7and a capacitor C. Signal lines electrically connected to the pixel driving circuit211include a gate scanning signal line G, a first reset signal line Rst1, a second reset signal line Rst2and a light-emitting control signal line Em.

A gate of the first transistor T1is electrically connected to the first reset signal line Rst1, a first electrode of the first transistor T1is electrically connected to an initial signal line Vt, and a second electrode of the first transistor T1is electrically connected to a driving node A; a gate of the second transistor T2is electrically connected to the gate scanning signal line G, a first electrode of the second transistor T2is electrically connected to a second electrode of the third transistor T3, and a second electrode of the second transistor T2is electrically connected to the driving node A; a gate of the third transistor T3is electrically connected to the driving node A; a gate of the fourth transistor T4is electrically connected to the gate scanning signal line G, a first electrode of the fourth transistor T4is electrically connected to a data line Dt, and a second electrode of the fourth transistor T4is electrically connected to a first electrode of the third transistor T3; a gate of the fifth transistor T5and a gate of the sixth transistor T6are both electrically connected to the light-emitting control signal line Em, a first electrode of the fifth transistor T5is electrically connected to a first power supply signal line Vdd, a second electrode of the fifth transistor T5is electrically connected to the first electrode of the third transistor T3, a first electrode of the sixth transistor T6is electrically connected to the second electrode of the third transistor T3, and a second electrode of the sixth transistor T6is electrically connected to an anode of a light-emitting device OLED; a gate of the seventh transistor T7is electrically connected to the second reset signal line Rst2, a first electrode of the seventh transistor T7is electrically connected to another initial signal line Vt, a second electrode of the seventh transistor T7is electrically connected to the anode of the light-emitting device OLED, and a cathode of the light-emitting device OLED is electrically connected to a second power supply signal line Vss.

In some embodiments, the initial signal lines Vt connected to the same pixel driving circuit211include two first initial signal lines Vt1. For convenience of distinction, referring toFIG.12, a first initial signal line Vt1electrically connected to the first electrode of the first transistor T1may be defined as a first initial signal sub-line Vt11, and another first initial signal line Vt1electrically connected to the first electrode of the seventh transistor T7is defined as a second initial signal sub-line Vt12.

In some embodiments, all the transistors in the pixel driving circuit211may be each a P-type transistor, and the P-type transistor is turned on when a gate thereof receives a low-voltage signal. In some other embodiments, all the transistors in the pixel driving circuit211may be each an N-type transistor, and the N-type transistor is turned on when a gate thereof receives a high-voltage signal. In addition, in yet other embodiments, some transistors in the pixel driving circuit211are each the N-type transistor, and the remaining transistors are each the P-type transistor. For example, the first transistor T1and the second transistor T2are each the N-type transistor, and the remaining transistors are each the P-type transistor. It will be noted that “the high-voltage signal” and “the low-voltage signal” are popular expressions. In general, a turn-on condition of the N-type transistor is that a gate-source voltage difference is greater than a threshold voltage of the N-type transistor (that is, a gate voltage of the N-type transistor is greater than a sum of a source voltage of the N-type transistor and the threshold voltage of the N-type transistor), and the threshold voltage of the N-type transistor is a positive value, and thus a gate voltage signal enabling the N-type transistor to be turned on is referred to as the high-voltage signal; a turn-on condition of the P-type transistor is that an absolute value of a gate-source voltage difference is greater than a threshold voltage of the P-type transistor, and the threshold voltage of the P-type transistor is a negative value (that is, a gate voltage of the P-type transistor is less than a sum of a source voltage of the P-type transistor and the threshold voltage of the P-type transistor), and thus a gate voltage signal enabling the P-type transistor to be turned on is referred to as the low-voltage signal. The phrases “high” and “low” of “the high-voltage signal” and “the low-voltage signal” are described relative to a reference voltage (e.g., 0V).

Film layer structures in the array substrate300provided in some embodiments of the present disclosure will be described based on the pixel driving circuit211disclosed in the above embodiments.

In some embodiments, referring toFIGS.13A and13B, the array substrate300includes the active film layer380, the first gate metal layer Gate1and the second gate metal layer Gate2that are sequentially arranged on the substrate310. The active film layer380includes active layers of the plurality of transistors in the pixel driving circuit211, and an active layer of each transistor includes a first electrode region, a second electrode region and a channel region that connects the first electrode region and the second electrode region. Referring toFIG.14,FIG.14shows a structure of the active film layer380and a position of the active layer of each transistor in the active film layer380.

The first gate metal layer Gate1and the second gate metal layer Gate2will be described below with reference to the active film layer380.

Referring toFIGS.15and16, the first gate metal layer Gate1includes the second reset signal line Rst2, the light-emitting control signal line Em, the gate scanning signal line G and the first reset signal line Rst1that are sequentially arranged in the first direction Y, and the second reset signal line Rst2, the light-emitting control signal line Em, the gate scanning signal line G and the first reset signal line Rst1each extend in the second direction X.

A portion, passing through a channel region of a respective transistor, of each of the above signal lines may serve as a gate of the respective transistor. Referring toFIG.16, the gate of the first transistor T1is located in the first reset signal line Rst1, and a portion, passing through the channel region of the first transistor T1, of the first reset signal line Rst1serves as the gate of the first transistor T1.

Referring toFIG.16, the gate of the second transistor T2and the gate of the fourth transistor T4are located in the gate scanning signal line G; in a sub-pixel region330, the gate scanning signal line G sequentially passes through the channel region of the second transistor T2and the channel region of the fourth transistor T4in the second direction X; of the gate scanning signal line G, a portion passing through the channel region of the second transistor T2and a portion passing through the channel region of the fourth transistor T4serve as the gate of the second transistor T2and the gate of the fourth transistor T4, respectively.

Referring toFIG.16, the gate of the sixth transistor T6and the gate of the fifth transistor T5are located in the light-emitting control signal line Em; in the sub-pixel region330, the light-emitting control signal line Em sequentially passes through the channel region of the sixth transistor T6and the channel region of the fifth transistor T5in the second direction X; a portion, passing through the channel region of the sixth transistor T6, of the light-emitting control signal line Em serves as the gate of the sixth transistor T6, and a portion, passing through the channel region of the fifth transistor T5, of the light-emitting control signal line Em serves as the gate of the fifth transistor T5.

Referring toFIG.16, the gate of the seventh transistor T7is located in the second reset signal line Rst2, and a portion, passing through the channel region of the seventh transistor T7, of the second reset signal line Rst2serves as the gate of the seventh transistor T7.

It will be noted that the active layers of the plurality of pixel driving circuits211are arranged in an array on the substrate310, and a row of pixel driving circuits211correspond to a second reset signal line Rst2, a light-emitting control signal line Em, a gate scanning signal line G and a first reset signal line Rst1.

In addition to the above signal lines, referring toFIGS.15and16, a first plate Cst1of the capacitor C is formed in the first gate metal layer Gate1, and a portion of the first plate Cst1overlapping with the channel region of the third transistor T3serves as the gate of the third transistor T3.

The first gate metal layer Gate1is described above, and the second gate metal layer Gate2will be described below.

Referring toFIG.17, a plurality of first initial signal lines Vt1are formed in the second gate metal layer Gate2, and the plurality of first initial signal lines Vt1each extend in the second direction X and are sequentially arranged in the first direction Y. Every two first initial signal lines Vt1pass through a same row of sub-pixel regions, and a row of pixel driving circuits211may be electrically connected to two first initial signal lines Vt1. The two first initial signal lines Vt1electrically connected to the row of pixel driving circuits211are the first initial signal sub-line Vt11and the second initial signal sub-line Vt12. The first initial signal sub-line Vt11is electrically connected to the first electrode of the first transistor T1, and the second initial signal sub-line Vt12is electrically connected to the first electrode of the seventh transistor T7.

In addition, referring toFIG.17, a second plate Cst2of the capacitor C is formed in the second gate metal layer Gate2. Referring toFIG.13B, of the capacitor C, an orthographic projection of the first plate Cst1on the substrate310overlaps with an orthographic projection of the second plate Cst2on the substrate310. The second plate Cst2may be electrically connected to the first power supply signal line Vdd, so that a first power supply signal transmitted from the first power supply signal line Vdd may be transmitted to the second plate Cst2. The first power supply signal is a constant voltage signal, so that voltages of second plates Cst2in all the pixel driving circuits211are equal to one another. Therefore, referring toFIG.17, the second plates Cst2in all the pixel driving circuits211may be electrically connected to one another.

Based on the film layer structures in the array substrate300provided in the above embodiments, in some embodiments, referring toFIGS.18A and18B, the array substrate300further includes the first source-drain metal layer SD1located on the first side of the substrate310and the second source-drain metal layer SD2located on a side of the first source-drain metal layer SD1away from the substrate310. Referring toFIG.19A, the first power supply signal lines Vdd and the jumper wires Dtb are located in the first source-drain metal layer SD1. Referring toFIGS.19B and20A, the first sub-lines321, the second sub-lines322and the main lines Dta are located in the second source-drain metal layer SD2.

Firstly, the first source-drain metal layer SD1and the second source-drain metal layer SD2that are in the first wiring region350will be described.

For example, referring toFIG.19A, in the first wiring region350, first power supply signal lines Vdd are disposed in the first source-drain metal layer SD1, and the first power supply signal lines Vdd each extend in the first direction Y and are sequentially arranged in the second direction X. A first power supply signal line Vdd corresponds to a column of sub-pixel regions. That is, a column of pixel driving circuits211are electrically connected to the first power supply signal line Vdd. The first power supply signal line Vdd may be electrically connected to the second plate Cst2of the capacitor C and the first electrode of the fifth transistor T5through respective via holes. In addition, jumper wires Dtb are disposed in the first source-drain metal layer SD1, and a jumper wire Dtb is disposed in a sub-pixel region330.

For example, referring toFIGS.19B and19C, second sub-lines322each extending in the second direction X are disposed in the second source-drain metal layer SD2, and the second sub-lines322are sequentially arranged in the first direction Y. Main lines Dta are also disposed in the second source-drain metal layer SD2; a separation gap is provided between two main lines Dta that are adjacent in the first direction Y, and a second sub-line322may pass through the separation gap.

Referring toFIGS.19C and19D, the main lines Dta and the jumper wires Dtb are alternately arranged in the first direction Y, and a main line Dta may be connected to a jumper wire Dtb through a via hole.

Next, the first source-drain metal layer SD1and the second source-drain metal layer SD2that are in the second wiring region360will be described.

For example, in the second wiring region360, the first source-drain metal layer SD1includes first power supply signal lines Vdd, and a layout of the first power supply signal lines Vdd is the same as a layout of the first power supply signal lines Vdd in the first wiring region350, which may refer toFIG.19Aand will not be repeated here. Here, it will be noted that, in some embodiments, there is no jumper wire Dtb formed in the second wiring region360. In some other embodiments, there may be jumper wires Dtb formed in the second wiring region360. That is, a layout, located in the second wiring region360, of the first source-drain metal layer SD1is the same as a layout, located in the first wiring region350, of the first source-drain metal layer SD1.

In some embodiments, referring toFIG.18A, the active film layer380is disposed between the jumper wires Dtb and the substrate310, and a jumper wire Dtb is connected to the active film layer380through a via hole.

In some embodiments, referring toFIG.18A, a jumper wire Dtb has an extension portion Dtb1, and an end of the extension portion Dtb1is connected to the active film layer380through a via hole.

In some examples, referring toFIG.18A, the jumper wire Dtb further includes a main portion Dtb2; an end of the main portion Dtb2is connected to another end of the extension portion Dtb1; two ends of the main portion Dtb2are electrically connected to two main lines Dta through via holes, respectively; the end of the extension portion Dtb1away from the main portion Dtb2is electrically connected to the first electrode region of the fourth transistor T4(which is not shown inFIG.18Aand may refer to the fourth transistor T4inFIG.14) through a via hole.

In some examples, referring toFIG.19C, an orthographic projection of the extension portion Dtb1on the substrate310at least partially coincide with an orthographic projection of a main line Dta on the substrate310. In this case, the extension portion Dtb1is at least partially located within a range where the main line Dta located, so that the extension portion Dtb1may not cause additional metal blocking. As a result, a light transmittance of the display panel200is ensured, so that the display panel200may support an under-screen fingerprint technology.

Referring toFIGS.20A,20B and20C, the second source-drain metal layer SD2includes first sub-lines321; each column of sub-pixel regions correspond to two first sub-lines321, and an orthographic projection of a first first sub-line321A on the substrate310is located between an orthographic projection of a data line Dt on the substrate310and an orthographic projection of a first power supply signal line Vdd on the substrate310.

Other than the scheme in which the second sub-lines322and the main lines Dta are disposed in the second source-drain metal layer SD2, in some embodiments, the second sub-line322is located in a layer different from a layer where the main structures of the data lines Dt are located.

For example, the second sub-line322may be disposed in any one of the first gate metal layer Gate1and the second gate metal layer Gate2. The second sub-line322may be electrically connected to the main structures of the data lines Dt through respective via holes.

In some embodiments, the array substrate300further includes at least one gate metal layer located on the first side of the substrate310, a first source-drain metal layer SD1located on a side of the at least one gate metal layer away from the substrate310and a second source-drain metal layer SD2located on a side of the first source-drain metal layer SD1away from the substrate310. As shown inFIG.24, the second sub-line322is disposed in any one of the gate metal layer, the first power supply signal lines Vdd are disposed in the first source-drain metal layer SD1, and the first sub-line321(not shown inFIG.24) and the main structures of the data lines Dt are disposed in the second source-drain metal layer SD2.

For example, the at least one gate metal layer includes the first gate metal layer Gate1and the second gate metal layer Gate2, and the second sub-lines322may be disposed in the first gate metal layer Gate1or the second gate metal layer Gate2. In this case, the second sub-lines322and one of the first gate metal layer Gate1and the second gate metal layer Gate2may be manufactured during a same process, which makes it possible to use a same mask. As a result, there is no need to provide additional mask for providing the second sub-lines322, so that the cost is saved.

The first sub-lines321and the main structures of the data lines Dt are disposed in the second source-drain metal layer SD2. In this case, the main structures of the data lines Dt may be each a complete data line Dt, the second sub-lines322are located in the layer different from the layer where the data lines Dt are located, so that the second sub-lines322are insulated from the data lines Dt through an insulating layer between the film layers.

In some embodiments, referring toFIG.21, the array substrate300further includes a plurality of first initial signal lines Vt1located on the first side of the substrate310and located in the display area AA. The plurality of first initial signal lines Vt1each extend in the second direction X, and the plurality of first initial signal lines Vt1are located in a layer different from the layer in which the second sub-lines322are located. Referring toFIG.21, an orthographic projection, on the substrate310, of a first initial signal line Vt1corresponding to a row of sub-pixel regions at least partially overlaps with an orthographic projection, on the substrate310, of a second sub-line322passing through the row of sub-pixel regions.

The first initial signal line Vt1at least partially overlaps with the second sub-line322, which may cause a layout of the signal lines in the array substrate300to be compact, so as to reduce the area of the sub-pixel. As a result, the pixels per inch (PPI) of the display panel is improved. In addition, the second sub-line322overlaps with the first initial signal line Vt1, and there is no crosstalk created between the two, so that an accuracy of a transmission of a data signal on the second sub-line322is ensured. Moreover, the second sub-line322overlaps with the first initial signal line Vt1, which may not cause additional metal blocking, so that the light transmittance of the display panel200is ensured. As a result, the display panel200may support the under-screen fingerprint technology.

For example, a row of pixel driving circuits211may be electrically connected to two first initial signal lines Vt1, and the two first initial signal lines Vt1electrically connected to the row of pixel driving circuits211are a first initial signal sub-line Vt11and a second initial signal sub-line Vt12. Referring toFIG.17, the first initial signal sub-line Vt11and the second initial signal sub-line Vt12are located on two sides, in the first direction Y, of the second plate Cst2of the capacitor C.

Referring toFIG.21, an orthographic projection, on the substrate310, of a second sub-line322to which a row of sub-pixel regions correspond may at least partially overlap with an orthographic projection, on the substrate310, of a second initial signal sub-line Vt12to which the row of sub-pixel regions correspond. In some examples, the orthographic projection of the second sub-line322on the substrate310may be completely located within the orthographic projection of the second initial signal sub-line Vt12on the substrate310. In some other examples, a portion of the orthographic projection of the second sub-line322on the substrate310may be located within the orthographic projection of the second initial signal sub-line Vt12on the substrate310, and the other portion of the orthographic projection of the second sub-line322on the substrate310may be located outside the orthographic projection of the second initial signal sub-line Vt12on the substrate310.

In some embodiments, referring toFIG.19A, the array substrate300further includes a plurality of second initial signal lines Vt2, and the plurality of second initial signal lines Vt2are located on the first side of the substrate310and located in the display area AA. The plurality of second initial signal lines Vt2each extend in the first direction Y. The plurality of second initial signal lines Vt2are located in a layer different from the layer in which the plurality of first initial signal lines Vt1are located, and the plurality of second initial signal lines Vt2are electrically connected to the plurality of first initial signal lines Vt1through via holes.

In some examples, in a case where the two first initial signal lines Vt1electrically connected to the row of pixel driving circuits211are the first initial signal sub-line Vt11and the second initial signal sub-line Vt12, referring toFIG.21, a second initial signal line Vt2may be electrically connected to the first initial signal sub-line Vt11through a via hole, and the second initial signal line Vt2and the first initial signal sub-line Vt11transmit an initial signal together, so as to reduce a voltage drop of the initial signal line Vt during a transmission.

In some examples, the second initial signal line Vt2may be located in the first source-drain metal layer SD1, and the first initial signal sub-line Vt11and the second initial signal sub-line Vt12are both located in the second source-drain metal layer SD2.

In some embodiments, referring toFIG.20B, an orthographic projection, on the substrate310, of a second initial signal line Vt2passing through a column of sub-pixel regions at least partially overlaps with an orthographic projection, on the substrate310, of a first sub-line321passing through the column of sub-pixel regions.

For example, the second source-drain metal layer SD2includes the first sub-lines321, a column of sub-pixel regions correspond to two first sub-lines321, and the two first sub-lines321are the first first sub-line321A and the second first sub-line321B. Referring toFIG.20B, the second initial signal line Vt2at least partially overlaps with the second first sub-line321B, which may cause the layout of the signal lines in the array substrate300to be compact. In addition, the second first sub-line321B overlaps with the second initial signal line Vt2, and there is no crosstalk created between the two, so that the accuracy of the transmission of the data signal on the second sub-line322is ensured. Moreover, the second initial signal line Vt2overlaps with the second first sub-line321B, which may not cause additional metal blocking, so that the light transmittance of the display panel200is ensured. As a result, the display panel200may support the under-screen fingerprint technology.

The orthographic projection, on the substrate310, of the first sub-line321(i.e., the second first sub-line321B) at least partially overlaps with the orthographic projection, on the substrate310, of the second initial signal line Vt2corresponding to the column of sub-pixel regions. In some examples, the orthographic projection of the second first sub-line321B on the substrate310may completely overlap with the orthographic projection of the second initial signal line Vt2on the substrate310. In some other examples, a portion of the orthographic projection of the second first sub-line321B on the substrate310may be located within the orthographic projection of the second initial signal line Vt2on the substrate310, and the other portion of the orthographic projection of the second first sub-line321B on the substrate310may be located outside the orthographic projection of the second initial signal line Vt2on the substrate310.

In some examples, referring toFIGS.19A and19C, the second initial signal lines Vt2and the jumper wires Dtb are located in the same layer, and a second initial signal line Vt2is located between a jumper wire Dtb and a first power supply signal line Vdd; the second initial signal line Vt2has an avoidance portion Vt20, bent towards a side where the first power supply signal line Vdd is located, formed therein, and at least a portion of the jumper wire Dtb is located within an avoidance space defined by the avoidance portion Vt20.

In some examples, the second initial signal lines Vt2and the jumper wires Dtb may be disposed in the second source-drain metal layer SD2. As for a second initial signal line Vt2, a jumper wire Dtb and a first power supply signal line Vdd that correspond to a same column of sub-pixel regions, the second initial signal line Vt2is located between the jumper wire Dtb and the first power supply signal line Vdd.

At least a portion of the jumper wire Dtb is located within the avoidance space defined by the avoidance portion Vt20. In some examples, a portion of the jumper wire Dtb is located within the avoidance space. In some other examples, the entire jumper wire Dtb is located within the avoidance space.

In some examples, as shown inFIG.19A, the second initial signal line Vt2includes first lines Vt21and avoidance portions Vt20that are alternately arranged in the first direction Y, and the avoidance portion Vt20may avoid the jumper wire Dtb also located in the first source-drain metal layer SD1. The avoidance portion Vt20and the jumper wire Dtb that correspond to the same column of sub-pixel regions may be arranged in the second direction X.

In some examples, referring toFIG.19A, the avoidance portion Vt20includes a second line Vt22and two third lines Vt23, two third lines Vt23and the second line Vt22define an avoidance region; the first line Vt21and the second line Vt22are alternately arranged in the first direction Y. As for the second initial signal line Vt2, the jumper wires Dtb and the first power supply signal line Vdd that correspond to the same column of sub-pixel regions, a distance between the first line Vt21and the first power supply signal line Vdd is greater than a distance between the second line Vt22and the first power supply signal line Vdd. The first line Vt21and the second line Vt22that are adjacent to each other are electrically connected via a third line Vt23, the first line Vt21and the second line Vt22each extend in the first direction Y, and the third line Vt23substantially extends in the second direction X.

Some embodiments of the present disclosure provide an array substrate300(as shown inFIGS.2A and2B) including a substrate310, a plurality of first power supply signal lines Vdd, a plurality of data lines Dt and a plurality of fan-out lines320.

The substrate310has a display area AA and a peripheral area BB. The plurality of first power supply signal lines Vdd are located on a first side3101(as shown inFIG.1E) of the substrate310and located in the display area AA.

The plurality of first power supply signal lines Vdd each extend in the first direction Y and are sequentially arranged in the second direction X. The second direction X intersects the first direction Y, and the second direction X and the first direction Y are both parallel to the substrate310. The plurality of data lines Dt are located on the first side of the substrate310and located in the display area AA. The plurality of data lines Dt each extend in the first direction Y and are sequentially arranged in the second direction X. A data line Dt is adjacent to a first power supply signal line Vdd.

The plurality of fan-out lines320are located on the first side of the substrate310. Referring toFIGS.2A and2B, a fan-out line320includes a first sub-line321and a second sub-line322. The first sub-line321extends in the first direction Y and extends from the peripheral area BB to the display area AA. The second sub-line322extends in the second direction X and is located in the display area AA. An end of the second sub-line322is electrically connected to the first sub-line321, another end of the second sub-line322is electrically connected to a data line Dt of the plurality of data lines Dt, and the second sub-line322is insulated from the remaining data lines Dt of the plurality of data lines Dt. As shown inFIGS.3A and3B, a main structure of the data line Dt is located on the side of the first power supply signal lines Vdd away from the substrate310; the first sub-lines321and the main structures of the data lines Dt are disposed in the same layer.

The array substrate300has pixel driving circuits211in a plurality of rows and a plurality of columns; an orthographic projection, on the substrate310, of a first sub-line321passing through a column of pixel driving circuits is located between an orthographic projection, on the substrate310, of a first power supply signal line Vdd electrically connected to the column of pixel driving circuits and an orthographic projection, on the substrate310, of a data line Dt electrically connected to the column of pixel driving circuits.

The description that a first sub-line321passes through a column of pixel driving circuits refers to that an orthographic projection of the first sub-line321on the substrate310overlaps with orthographic projections, on the substrate310, of some or all of pixel driving circuits211in the column of pixel driving circuits.

The pixel driving circuits211in the plurality of rows and the plurality of columns are disposed in the display area AA of the substrate310. Pixel driving circuits211in a column are sequentially arranged in the first direction Y. Pixel driving circuits211in a row are sequentially arranged in the second direction X.

A first power supply signal line Vdd is electrically connected to a column of pixel driving circuits, so that the first power supply signal line Vdd may provide a first power supply signal for the column of pixel driving circuits. A data line Dt is electrically connected to a column of pixel driving circuits, so that the data line Dt may provide data signals for respective pixel driving circuits in the column.

In the array substrate300provided in some embodiments of the present disclosure, the first sub-lines321and the main structures of the data lines Dt are disposed in the same layer, which makes it possible to manufacture the main structures of the data lines Dt and the first sub-line321by using the same mask, so that there is no need to provide additional mask for manufacturing the first sub-line321. Therefore, a relatively small number of masks may be used during the process of manufacturing the display panel200, thereby saving the cost.

Some embodiments of the present disclosure provide a display panel200. Referring toFIG.1C, the display panel200includes the array substrate300provide in the above embodiments, a light-emitting device layer400and an encapsulation layer500. The light-emitting device layer400is located on a side of the array substrate300away from the substrate310; the encapsulation layer500is located on a side of the light-emitting device layer400away from the array substrate300.

The light-emitting device layer400includes a plurality of light-emitting devices OLED. The light-emitting device layer400includes an anode layer AND, a light-emitting layer and a cathode layer that are sequentially arranged on the planarization layer. Referring toFIG.22, the anode layer AND includes a plurality of anode patterns ANDO each used for forming an anode of a light-emitting device OLED.

Referring toFIG.23, the anode layer AND is provided with a pixel definition layer PDL formed thereon; the pixel definition layer PDL is provided with a plurality of pixel openings PDLO formed therein, and the light-emitting layer may be disposed in the pixel openings PDLO.

The encapsulation layer500covers the light-emitting devices OLED and encapsulate the light-emitting devices OLED, so as to prevent a lifetime of the OLED display panel200from being shortened due to a fact that moisture and oxygen in the external environment enter the display panel200and damage organic materials in the light-emitting devices OLED.

A display apparatus100provided in some embodiments of the present disclosure includes the display panel200provided in any one of the above embodiments. Thus, the display apparatus100provided in the embodiments of the present disclosure has all beneficial effects of the display panel200provided in any one of the above embodiments, which will not be repeated here.

Referring toFIG.4A, the display panel200includes a display area AA and a peripheral area BB, and the peripheral area BB of the display panel200includes a lead-out region B10and a bonding region B6that are located on a side of the display area AA, and the bonding region B6is located on a side of the lead-out region B10away from the display area AA. It will be noted that the display panel200includes the array substrate300, the array substrate300includes the display area AA and the peripheral area BB, the display area AA of the display panel200and the display area AA of the array substrate300are a same region, the peripheral area BB of the display panel200and the peripheral area BB of the array substrate300are a same region.

In some embodiments, the lead-out region B10may include the bending region B2, the second fan-out region B3and the test circuit region B4that are provided in the above embodiments. Functions of the bending region B2, the second fan-out region B3and the test circuit region B4are described above, which will not be repeated here.

In some embodiments, the display panel200further includes a flexible circuit board and a main control circuit board; an end of the flexible circuit board is bonded in the bonding region B6, and the main control circuit board is electrically connected to another end of the flexible circuit board.

In some examples, referring toFIG.4A, the lead-out region B10includes the bending region B2, the second fan-out region B3and the test circuit region B4. The display panel200further includes a chip region B5, the lead-out region B10is located between the chip region B5and the display area AA, and the bonding region B6is located on a side of the chip region B5away from the lead-out region B10. The first sub-line321may pass through the lead-out region B10and extend the chip region B5, and a driver IC is bonded, in the chip region B5, to the first sub-line321. The first power supply signal line Vdd extends to the bonding region B6through the lead-out region B10and the chip region B5. The bonding region B6is provided with a plurality of pins therein; lead-out portions of the first power supply signal lines Vdd may be gathered in the second fan-out region B3of the lead-out region B10, and the lead-out portions of the first power supply signal lines Vdd may be electrically connected to part of the pins in the bonding region B6passing through the lead-out region B10and the chip region B5. Thus, the main control circuit board may transmit, through the part of the pins, the first power supply signal to the lead-out portions of the first power supply signal lines Vdd through the flexible circuit board, so that the first power supply signal is transmitted to the first power supply signal lines Vdd.

In some other examples, referring toFIG.4B, the lead-out region B10does not include the bending region, and there is no chip region provided on the side of the lead-out region B10away from the display area AA. In this case, the lead-out region B10includes the second fan-out region B3and the test circuit region B4, and the bonding region B6is disposed on the side of the lead-out region B10away from the display area AA. In this case, the first sub-line321may extend to the bonding region B6through the lead-out region B10and be electrically connected to the plurality of pins in the bonding region B6. The driver IC is bonded to the flexible circuit board, and the flexible circuit board is bonded to the plurality of pins in the bonding region B6. In these examples, the flexible circuit board is folded onto a back surface of the display panel200.