Bidirectional drain to drain stacked FET gating circuit

A bidirectional power FET circuit for AC application has a plurality of pairs of enhancement mode power FETs. Each pair has first and second power FETs connected drain to drain in series relation. The pairs are stacked in series between first and second main terminals. A plurality of gating circuits, one gating circuit for each power FET pair, are stacked in series for driving the power FET pairs sequentially into conduction from a single gate terminal.

BACKGROUND AND SUMMARY 
The invention relates to power FETs (field effect transistors), and more 
particularly to a plurality of FETs stacked in series and capable of 
handling bidirectional current, for AC application. 
Power FETs are known in the art. A FET is unidirectional and conducts 
current from one main terminal to another in response to gate drive on a 
third terminal. This three terminal arrangement is widely accepted, and is 
compatible with standard circuit applications. 
The stacking of power FETs in unidirectional applications is also known. 
Stacking is the interconnection of multiple devices in configurations that 
result in capabilities beyond those of a single device. The stacking of 
multiple power FETs in series results in higher voltage capability, and a 
better ratio of ON resistance to breakdown voltage. For example, 
connecting a pair of 100 volt devices in series results in a total voltage 
capability of 200 volts. The ON resistance in an individual power FET is 
proportional to the blocking voltage raised to the 2.6 power. Thus, 
doubling the blocking voltage in a single device would result in an ON 
resistance which is increased more than six times. Stacking of a pair of 
devices affords the increased voltage blocking capability but with lower 
ON resistance. Various problems encountered in stacking include voltage 
isolation, and differing gate triggering levels. Each of the gates wants 
to reference to a different level, but it is desirable to drive all the 
gates from the same source via a single gate terminal. 
In order to control a load driven by an AC power source, a plural FET 
arrangement must be bidirectional, i.e. pass current in both directions. 
It is desirable that the plural FET circuit be a three terminal device 
which is compatible with most packaging environment. 
The present invention addresses and solves the need for AC voltage 
capability in a series stack plural FET arrangement. The FETs are 
bidirectionally stacked drain to drain, and have a particularly simple and 
effective stacked gating arrangement.

DETAILED DESCRIPTION 
The drawing shows a three terminal bidirectional FET circuit 2 comprising a 
plurality of pairs 4 and 6 of enhancement mode power FETs connected in 
series between first and second main terminals T1 and T2. Each pair 
comprises first and second power FETs connected drain to drain in series 
relation, for example FETs 8 and 10 of pair 4, and FETs 12 and 14 of pair 
6. My copending application Ser. No. 390,721, filed June 21, 1982, shows a 
pair of FETs connected drain to drain. 
FIG. 1 shows the FET circuit connected across a load 16, an AC power source 
18 and ground. The inherent reverse characteristic diodes 20, 22, 24 and 
26 of the power FETs are also shown, as is known in the art. When the 
device is in the ON state, and terminal T2 is positive with respect to 
terminal T1, current flows from terminal T2 through diode 26, through FET 
12, through diode 22, through FET 8 to terminal T1. When terminal T2 goes 
negative, current flows from T1 through diode 20, through FET 10, through 
diode 24, through FET 14 to terminal T2. 
A plurality of gating circuits such as 28 and 30 are provided, one gating 
circuit for each pair of power FETs for driving the latter into 
conduction. The gating circuits are stacked in series for driving the 
pairs of power FETs sequentially into conduction from a single gate 
terminal T3 driven by gating voltage source 32. In preferred form, each 
circuit comprises a FET as shown at respective gating FETs 34 and 36. The 
first gating circuit 28 connects gate terminal T3 via connection 38 to the 
gate of the first power FET 8 of the first pair 4 and also connects the 
gate terminal T3 via connection 38 through first gating FET 34 and 
connection 40 to the gate of the second power FET 10 of the first pair 4. 
The second gating circuit 30 connects gating terminal T3 through the first 
gating FET 34 and via connection 40 the gate of the first power FET 12 of 
the second pair 6, and connects gate terminal T3 through first gating FET 
34 and via connection 40 through second gating FET 36 to the gate of the 
second power FET 14 of the second pair 6. 
In operation, a positive gating signal at T3 charges the gate of n channel 
power FET 8 to turn the latter ON. This positive signal at connection 38 
also biases the source of p channel gating FET 34 positively with respect 
to the latter's gate which is referenced to ground via connection 42 to 
terminal T1. Gating FET 34 thus conducts and charges the gate of n channel 
power FET 10 through connection 40 rendering FET 10 conductive. The 
positive signal at point 40 also charges the gate of n channel power FET 
12 rendering the latter conductive since its source is referenced to 
ground at T1 upon conduction of FETs 8 and 10. The positive signal at 
point 40 also biases the source of p channel gating FET 36 positively with 
respect to the latter's gate which is tied via connection 44 to the source 
of power FET 10, which source is at ground potential of terminal T1 upon 
conduction of FETs 8 and 10. Gating FET 36 is thus turned ON and current 
flows therethrough to the gate of n channel power FET 14 to turn the 
latter ON. Zener diodes 46, 48 and 50 provide gate to source protection 
for the power FETs. Zener diodes 52, 54, 56 and 58 provide overvoltage 
protection for the gating circuitry and power FETs when in reverse 
conduction. Zener diodes 54 and 58 also provide gate charging current when 
in forward conduction. 
In preferred form, if there are n pairs of power FETs, then n+1 fast gate 
turn-off circuits such as 60, 62 and 64 are provided. These fast gate 
turn-off circuits provide fast discharge or depletion therethrough of 
power FET gate charge due to the gate to source capacitance of the power 
FETs, enabling fast turn-off. The first turn-off circuit 60 services the 
first power FET 8 of the first pair. The last turn-off circuit 64 services 
the second power FET 14 of the last pair. The remaining turn-off circuits 
such as 62 service the common source power FETs such as 10 and 12 in 
adjacent pairs such as 4 and 6, i.e. the remaining fast turn-off circuit 
such as 62 each service two power FETs such as 10 and 12. 
Fast turn-off circuitry 60 is like that shown in my copending application 
Ser. No. 390,482, filed June 21, 1982, and facilitates fast turn-off by 
rapidly draining the stored energy in the gate to source capacitance of 
power FET 8. Fast turn-off circuitry 60 includes bipolar PNP transistor 66 
whose emitter to base junction is forward biased at turn-off of power FET 
8 due to the residual positive charge on the gate of the latter. Thus, 
when gate drive is removed from gate terminal T3, the base of transistor 
66 is pulled negative with respect to its emitter by resistor 70, whereby 
transistor 66 goes into conduction. Current flowing through transistor 66 
supplies base drive for an NPN bipolar transistor 68, driving the latter 
into conduction. Conduction of transistor 68 draws base current from 
transistor 66 whereby to latch transistors 66 and 68 into conduction in a 
regenerative loop. Conduction of transistors 66 and 68 discharge the gate 
of power FET 8 to thus facilitate faster turn-off thereof. Resistor 72 
provides a means to unlatch transistors 66 and 68 when the charge on the 
gate of FET 8 has been depleted. Reverse blocking diode 74 insures turn-on 
of transistors 66 and 68. 
Alternative fast turn-off circuitry for any or all of the fast turn-off 
circuits is shown at 64. Upon removal of gate drive, the base of PNP 
bipolar transistor 76 goes low with respect to its emitter which is 
connected to the base of another PNP bipolar transistor 78 in Darlington 
relation, such that transistors 76 and 78 are rendered conductive due to 
the relative positive charge on the emitter of transistor 78 which is 
connected to the gate of power FET 14. Reverse blocking diode 80 provides 
the requisite voltage drop between the emitter of transistor 78 and the 
base of transistor 76, and resistor 82 provides the requisite return path, 
to enable turn-on of Darling transistor pair 76 and 78, to thus quickly 
discharge the residual positive stored charge in the gate to source 
capacitance in power FET 14. 
In other embodiments, the fast turn-off circuitry 60, 62, and/or 64 may be 
like that shown in my copending application Ser. Nos. 390,720 or 390,481, 
filed June 21, 1982. In the former, a fast turn-off circuit is provided by 
a JFET in the gate circuit of the power FET which is connected to the same 
gate drive terminal as the power FET. The JFET becomes conductive upon 
turn-off of the power FET due to removal of gate drive. Conduction of the 
JFET provides faster discharge therethrough of residual stored charge on 
the power FET gate, whereby to facilitate faster turn-off. A zener diode 
is connected in the gating circuitry and has a greater breakover voltage 
than the pinch-off voltage of the JFET, such that during turn-on, gate 
drive first pinches off the JFET and then charges up the power FET gate to 
drive the power FET into conduction. In the latter, nonregenerative 
bipolar transistor means is provided in the gate circuit of the FET to 
facilitate fast turn-off without reverse gating current and its attendant 
auxiliary power supply. 
It is recognized that various modifications are possible within the scope 
of the appended claims.