Method of forming an ESD detector and structure therefor

In one embodiment, and electro-static discharge detector is formed with a plurality of channels and is configured to detect a positive electro-static discharge and a negative electro-static discharge.

BACKGROUND OF THE INVENTION

The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structures.

In the past, the electronics industry utilized various circuits to detect an electro-static discharge. Most prior circuits required an antenna to form a signal and then used electrical circuits to process the signal from the antenna. The size of the antenna made it difficult to place the prior ESD apparatus within an integrated circuit. The antenna also increased the cost of the ESD apparatus.

Other ESD apparatus that did not use an antenna could only detect a positive electro-static discharge. This limited the usefulness of the apparatus.

Accordingly, it is desirable to have a method of forming an ESD detector that reduces the cost of the ESD detector, that can be integrated onto an integrated circuit, and that can detect both positive and negative electro-static discharge events.

For simplicity and clarity of the illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-Channel devices, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1schematically illustrates a generalized block diagram of an electronics apparatus10. Apparatus10generally includes a memory element that is used to store digital information. Apparatus10can be a variety of equipment types such as a digital music player, a digital video camera, a cell phone, or other type of apparatus. Many such apparatus have connectors, such as a connector11, which is used to connect to other equipment. Such connectors can cause apparatus10to be susceptible to electro-static discharge (ESD). For example, apparatus10may be in the process of transferring data to or from the memory when an ESD occurs. The ESD may result in transferring incorrect data, or cause the data to be corrupted or lost, or cause other malfunctions of apparatus10. Apparatus10generally includes an interconnect substrate12that is used to interconnect electronic components of apparatus10such as to connect a controller13to the memory or to electrically connect connector11to controller13. Interconnect substrate12may be printed circuit (PC) board or a flex tape or other type of interconnect substrate that are well known to those skilled in the art. Apparatus10also includes an electro-static discharge (ESD) detector17that generally is interconnected to connector11and controller13on interconnect substrate12. ESD detector17has a signal input18that generally is connected to connector11and an output19that provides an output signal to controller13or to another component of apparatus10.

FIG. 2schematically illustrates a portion of an exemplary embodiment of ESD detector17. In addition to signal input18and output19, ESD detector17includes a power input or voltage input20and a power return or voltage return21that are connected to receive an operating voltage for operating some of the elements within detector17. In a battery-powered apparatus, input20and return21may be connected to the respective positive and negative terminals of the battery in order to receive an operating voltage and operating power. As will be seen further hereinafter, detector17is configured to detect either a positive electro-static discharge or a negative electro-static discharge. Detector17also is configured to form an ESD detection signal on output19indicating the detection of either the negative electro-static discharge or the positive electro-static discharge. Detector17includes a positive ESD detection channel22that is utilized to detect the occurrence of the positive electro-static discharge and a negative ESD detection channel37that is utilized to detect the occurrence of the negative electro-static discharge. Detector17also includes a pulse generator49that is utilized to form the ESD detection signal or control signal indicating the detection of either the negative electro-static discharge or the positive electro-static discharge. An output transistor61and a resistor62assist in forming the ESD detection signal.

In the preferred embodiment, positive ESD detection channel22includes a pair of back-to-back diodes23and24that are connected between input18and return21, a second pair of back-to-back diodes26and27that are connected between input18and a node28, a zener diode31and a resistor30that are connected between node28and return21, inverters33and34that have an input connected to node28, and a transistor35. Transistor35allows the output of channel22to be ORed together with the output of channel37. In the preferred embodiment, negative ESD detection channel37includes a pair of back-to-back diodes39and40, a resistor42connected between input20and diodes39and40, another pair of back-to-back diodes43and44, and transistors46and48along with a resistor47. Diodes23and24also function as a voltage limiting circuit for channel37. Each of diodes23,24,26,27,39,40,43, and44may be formed as a plurality of series connected diodes. Connecting two or more diodes in series can be used to form a desired voltage drop. In the preferred embodiment, each of diodes23,24,26,27,39,40,43, and44are two series connected polysilicon diodes. The preferred embodiment of pulse generator49includes a latch50and a delay circuit formed by inverters53-57, a capacitor55, and a transistor59. When detector17is assembled onto an interconnect substrate, such as substrate12illustrated inFIG. 1, the interconnect substrate generally has parasitic inductance and resistance that are formed between input18and return21as illustrated by an inductor14and a resistor15that are shown in dashed lines (FIG. 1). This parasitic inductance and resistance can affect the shape and duration of the current and voltage that is formed at input18in response to a positive or negative electro-static discharge. When an electrode-static discharge occurs, there is generally a large voltage and current spike that occurs over a brief period of time. Generally, the peak current and peak voltage occurs over a period of a few nanoseconds, typically less than two nanoseconds (2 nsec.) and could last for only about one nanosecond (1 nsec.). The current generally decreases to a plateau for another time interval usually around twenty (20) nanoseconds and slowly decreases over another twenty to forty (20-40) nanoseconds. The peak value of the current could be as high as twenty to thirty amperes (20 to 30 amps) and the peak voltage could be between two thousand and eight thousand volts (2000-8000 V). The size and response time of the elements of channels22and37preferably are configured to detect the voltage during the time interval of the peak voltage and conduct the peak current. Detector17is configured to detect ESD events and provide the ESD detection signal on output19within one nanosecond (1 nsec.) of receiving the initial ESD voltage as specified in the International Electrotechnical Commission (IEC) specification commonly referred to as IEC 61000-4-2 (level 2) specification. The International Electrotechnical Commission has an address at 3, rue de Varembé, 1211 Genève 20, Switzerland.

Upon receiving a positive ESD, the large ESD voltage attempts to force input18to a positive voltage relative to return21and to a voltage value that is large relative to the voltage between input20and return21. The large positive ESD voltage generally is one thousand volts (1000 V) or greater. However, diodes23and24function as a voltage limiting circuit that limits the positive voltage formed on input18to a value that is near a positive threshold voltage or threshold of the voltage limiting circuit. The positive threshold of the voltage limiting circuit is the reverse voltage of diode24plus the forward voltage of diode23. As the voltage on input18(relative to return21) reaches the positive threshold of the voltage limiting circuit, diode23begins to conduct in the forward direction and diode24conducts in the reverse direction. Consequently, diodes23and24generally are formed to conduct currents of at least seven to twenty amperes (7-20 amps) and preferably at least thirty amperes (30 amps). Diodes23and24are formed with a very large width, preferably at least one thousand five hundred to two thousand (1500-2000) microns wide, so that diodes23and24can conduct the large ESD currents. Because of the large width, diodes23and24do not have a sharp knee, thus, the voltage on input18may increase slightly above the positive threshold. Consequently, the voltage limiting circuit limits the voltage on input18to a voltage value that is less than the peak positive ESD voltage value and is near to the positive threshold. The voltage on input18generally increases no more that about thirty to fifty percent (30%-50%) greater than the positive threshold. For example, the positive threshold of the voltage limiting circuit may be around fourteen volts (14 V) which may limit the voltage on input18to a voltage of about twenty volts (20 V).

Diodes26and27along with diode31and resistor30form a positive translator circuit that translates the voltage on input18to a lower voltage on node28. The threshold of the positive translator circuit is the reverse voltage of diode26plus the forward voltage of diode27. This is approximately the value of the voltage on input18that current begins to flow through diodes26and27. A first portion of the ESD current from input18is conducted through diodes23and24. This first portion of the ESD current generally is a majority of the current resulting from the ESD event. After the voltage on input18reaches the threshold of the positive translator circuit, a second portion of the ESD current from input18begins to flow through diodes26and27to node28and then through resistor30and possibly through diode31. This second portion of the ESD current is generally smaller, therefore, the width of diodes23and24generally is usually about twenty to fifty (20-50) and preferably about forty (40) times greater than the width of diodes26and27.

The current through resistor30forms a voltage on node28. As the value of the voltage on input18increases, the current through resistor30increases and forms a voltage that is large enough to trigger inverter33and force the output of inverter33low. Thus, the voltage on input18reaches the threshold of channel22(the threshold of the positive translator circuit plus the input threshold of inverter33). Diode31preferably is a zener diode so that the voltage on node28can be limited to a voltage that is less than the maximum voltage that can be sustained by the input of inverter33. For example, diodes26and27may be formed to have a threshold of about fourteen volts (14 V) and diode31may have a zener voltage of about five volts (5 V) which would limit the maximum voltage on node28to about five to six volts (5-6 V).

Inverters33and34in addition to transistor35form a shaping circuit that shapes the analog ESD voltage and current into a digital signal. The low from inverter33forces the output of inverter34high. The high from inverter34enables transistor35which pulls the set input of latch50low thereby setting latch50. Setting latch50forces the Q output high to enable transistor61and force output19low to form the ESD detection signal on output19. The high Q output is also used to form a delay that establishes a pulse width of the ESD detection signal. The high Q output forces the output of inverter53low and the output of inverter54high. Capacitor55slows the rise time of the output of inverter54so that inverter56is delayed from receiving the high from inverter54. As capacitor55charges past the threshold of inverter56, the output of inverter56goes low thereby forcing the output of inverter57high to enable transistor59and reset latch50. Resetting latch50forces the Q output low to disable transistor61and allow resistor62to pull output19back high. Thus, generator49receives the positive detect signal from channel22and forms the ESD detection signal on output19as a pulse having a width that is controlled by the string of inverters53-57and capacitor55.

A negative ESD attempts to force input18to a negative voltage having a value that is much less than the voltage on return21. The negative ESD voltage is generally negative one thousand volts (−1000 V) or more. However, the voltage limiting circuit of diodes23and24limits the negative voltage on input18to a negative value that is near the negative threshold of the voltage limiting circuit (the reverse voltage of diode23plus the forward voltage of diode24). As the voltage on input18reaches the negative threshold of the voltage limiting circuit, diode24begins to conduct in the forward direction and diode23conducts in the reverse direction. Because of the soft knee, the voltage on input18may become slightly more negative than the negative threshold similarly to the condition explained for the positive ESD. Consequently, the voltage limiting circuit limits the voltage on input18to a negative voltage value (relative to return21) that is less negative than the peak negative ESD voltage value and that is near the negative threshold of the voltage limiting circuit. For example, diodes23and24may have a negative threshold of around fifteen volts (15 V) which may limit the voltage on input18to a value of approximately minus twenty volts (−20 V).

Diodes39and40and resistor42function as a negative voltage translator circuit that translates the negative voltage on input18to a less negative voltage on the gate of transistor46. The threshold of the negative voltage translator circuit is the forward voltage of diode39plus the reverse voltage of diode40. As the voltage difference between the voltage on input20minus the voltage on input18becomes just slightly greater than the threshold of the negative voltage translator circuit, diode39begins to conduct in the forward direction relative to diode39and diode40begins to conduct in the reverse direction relative to diode40. The difference between the voltage on input20minus the voltage on input18is referred to hereinafter as the delta voltage (Vd) as shown below:
Vd=V20−V18whereVd—is the delta voltage,V20—is the voltage on input20relative to return21, andV18—is the voltage on input18relative to return21.

As diodes39and40begin to conduct, current begins to flow from input20through resistor42and diodes39and40. As the voltage on input18becomes more negative, the current through resistor42increases until the voltage across resistor42is greater than the threshold voltage of transistor46, and transistor46begins to conduct. This value of the delta voltage (Vd) that causes transistor46to conduct is the threshold voltage of negative ESD detection channel37. For example, if the voltage on input20is three volts (3V) and if diodes23and24limit the voltage on input18to minus twenty volts (−20 V), the delta voltage (Vd) is twenty three volts (23V). If diodes39and40have a threshold voltage of around fifteen volts (15 V), then the gate-to-source (Vgs) that is applied to transistor46is about eight volts (8V). If the threshold voltage of transistor46is five volts (5V), then the threshold of channel37is twenty volts (20 V) and transistor46becomes enabled when input18has a voltage of about minus seventeen volts (−17V). Thus, the negative translator circuit translates the large negative ESD voltage on input18to a lower voltage on the gate of transistor46.

Transistors46and48in addition to resistor47form a shaping circuit that shapes the analog ESD voltage and current into a digital signal. Enabling transistor46pulls the gate of transistor48high thereby enabling transistor48which pulls the output of channel37low. The low on the output of channel37functions as the negative detect signal. The low negative detect signal sets latch50to form the ESD detection signal as a pulse on output19as described previously for the setting of latch50from the positive detect signal.

The majority of the negative ESD current flows through diodes23and24. A portion of the negative ESD current flows through resistor42and diodes39and40. The value of resistor42is chosen to limit the Vgs that is applied to transistor46to a value that is less than the maximum Vgs that transistor46can withstand. In the preferred embodiment, resistor42is approximately one hundred fifty (150) ohms and typically limits the applied Vgs to about four to five volts. Diodes43and44are coupled across the gate and source of transistor46in order to protect transistor46by limiting the maximum Vgs that is applied to transistor46. Diodes39,40,43, and44usually are formed similar to diodes26and27since each of diodes39,40,43, and44conduct less current than diodes23and24. The forward voltage of diode43plus the reverse voltage of diode44generally is less than the maximum Vgs that can be sustained by transistor46. For example, the combined voltages of diodes43and44may be about seven volts (7 V).

As can be seen fromFIG. 1, detector17supplies the ESD detection signal to controller13. Controller13may then perform a variety of algorithms to prevent the ESD from affecting the data of apparatus10. Controller13may cause a re-read of a disk drive in order to retrieve valid data, or may initiate an error checking algorithm in order to detect data that may be changed by the ESD.

During normal operation of detector17(FIG. 2) without an electro-static discharge (ESD) event, diodes23and24,26and27, and39and40have a very high impedance so that detector17does not disturb the normal data signals received on connector11. These data signals generally have a maximum voltage that is less than the threshold voltage of diodes23and24, diodes26and27, and diodes39and40.

In order to facilitate this functionality for detector17, a cathode of diode24is connected to input18and an anode is connected to an anode of diode23which has a cathode connected to return21. A cathode of diode26is connected to input18and an anode is connected to an anode of diode27which has a cathode connected to node28. The input of inverter33is connected to node28and the output is connected to the input of inverter34which has an output connected to a gate of transistor35. The first terminal of resistor30is connected to node28and to a cathode of diode31. A second terminal of resistor30is connected to return21and an anode of diode31is connected to return21. A source of transistor35is connected to return21and a drain is connected to the set input of latch50. A cathode of diode39is connected input18and an anode is connected to an anode of diode40which has a cathode connected to a gate of transistor46. A first terminal of resistor42is connected to a gate of transistor46and a second terminal is connected to input20. A cathode of diode44is connected to an anode of diode43which has a cathode connected to input20. A source of transistor46is connected to input20and a drain is commonly connected to a gate of transistor48and a first terminal of resistor47. A second terminal of resistor47is connected to return21and to a source of transistor48. A drain of transistor48is connected to the set input of latch50. The Q output from latch50is commonly connected to a gate of transistor61and to the input of inverter53. An output of inverter53is connected to an input of inverter54which has an output commonly connected to an input of inverter56and a first terminal of capacitor55. A second terminal of capacitor55is connected to return21. An output of inverter56is connected to an input of inverter57which has an output connected to a gate of transistor59. A source of transistor59is connected to return21and a drain is connected to the reset input of latch50. A source of transistor61is connected to return21and a drain is connected to output19into a first terminal of resistor62. A second terminal of resistor62is connected to input20.

FIG. 3schematically illustrates an enlarged plan view of a portion of an embodiment of a semiconductor device or integrated circuit70that is formed on a semiconductor die71. Detector17is formed on die71. Die71may also include other circuits that are not shown inFIG. 3for simplicity of the drawing. Detector17and device or integrated circuit70are formed on die71by semiconductor manufacturing techniques that are well known to those skilled in the art. In one embodiment, detector17is formed on a semiconductor substrate as an integrated circuit having four external leads18-21.

In view of all of the above, it is evident that a novel device and method is disclosed. Included, among other features, is forming an ESD detector to have a first channel to detect a first ESD event and a second channel to detect a second ESD event. Configuring the ESD detector to limit the maximum value of the voltage that is applied to some of the detector circuits to a value that is less than the maximum ESD voltage facilities detecting the ESD. Translating the voltage to a second lower value facilitates forming a signal indicating that the ESD is detected. Using two separate channels facilitates detecting a positive and also a negative ESD.

While the subject matter of the invention is described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. For example, the limiting circuits may be formed from other voltage limiting circuits as long as the circuit limits the maximum input voltage to be less than the peak ESD voltage. The voltage translators may be formed from other translator circuits as long as the other circuits translates the maximum voltage to a voltage that is less than the maximum allowable input voltage of the circuits used to form the detection signals. Additionally, other circuits may be used instead of the circuits used for pulse generator49. Additionally, the word “connected” is used throughout for clarity of the description, however, it is intended to have the same meaning as the word “coupled”. Accordingly, “connected” should be interpreted as including either a direct connection or an indirect connection.