MEMORY SYSTEM

According to one embodiment, a memory system includes a plurality of nonvolatile semiconductor memories configured to hold data, or a conversion table for converting a logical address of the data into a physical address of the data, a table memory configured to hold the conversion table, an interface configured to exchange data and a table with the plurality of nonvolatile semiconductor memories based on a command issue request.

DETAILED DESCRIPTION

In general, according to one embodiment, a memory system includes a plurality of nonvolatile semiconductor memories configured to hold data, or a conversion table for converting a logical address of the data into a physical address of the data,

a table memory configured to hold the conversion table,

an interface configured to exchange data and a table with the plurality of nonvolatile semiconductor memories based on a command issue request, and

a controller configured to determine, when a logical address is supplied from a host device, whether the logical address is set in the conversion table held in the table memory,

specify another conversion table in which the logical address is set, if the logical address is not set in the conversion table,

request the interface to issue a command for reading out the specified other conversion table, to the nonvolatile semiconductor memory,

read out the other conversion table, and update the conversion table in the table memory to the other conversion table,

convert the logical address into a physical address based on the conversion table held in the table memory, if the logical address is set in the conversion table, or if the conversion table in the table memory is updated to the other conversion table,

request the interface to issue a command for reading out data held at the physical address, to the nonvolatile semiconductor memory corresponding to the physical address, and

determine, if a logical address for which no read command issue is requested exists among logical addresses supplied from the host device, whether the logical address is set in the conversion table held in the table memory, even while the interface is issuing a command for reading out the data or the conversion table from the nonvolatile semiconductor memory.

Details of the embodiment will be explained below with reference the accompanying drawings. Note that in the following explanation, the same reference numerals denote constituent elements having almost the same functions and arrangements, and a repetitive explanation will be made only when necessary. Note also that each embodiment to be explained below exemplarily discloses an apparatus and/or method for embodying the technical idea of the present invention, and the technical idea of the embodiment does not specify the materials, shapes, structures, layouts, and the like of components to those described below. The technical idea of the embodiment can variously be changed within the scope of the appended claims.

Embodiment

Configuration of Memory System

An outline of the basic configuration of a memory system100according to this embodiment will be explained below with reference toFIG. 1.

As shown inFIG. 1, a memory system100includes a memory controller (to be also simply referred to as a controller)100a, and a plurality of NAND flash memory chips (to be also referred to as NAND flashes, NAND memories, NAND chips, flash memories, memory chips, or chips)110. Note that this embodiment includes n+1 (n is an integer of 1 or more) NAND flash memory chips (chips0to n) as an example. When it is unnecessary to distinguish between the NAND flash memory chips, they will simply be referred to as chips or the NAND flash memory chips110. When it is necessary to distinguish between the NAND flash memory chips110, they will be referred to as chips0to n.

Also, this embodiment will be explained by using the NAND flash memory chips, but the present embodiment is not necessarily limited to this.

A host device200controls the memory system100by issuing, e.g., a command (i.e., a command normalized by an SD memory card, and a command issued by the host device200will also be referred to as a host command) to the memory system100. Also, the memory controller100acontrols the NAND flash memory chips110by issuing a NAND interface command (to be referred to as a NAND command or the like) to the NAND flash memory chips110.

The memory controller100aincludes a host interface (host I/F)101, a memory buffer102, a CPU (Central Processing Unit)103, a bus104, a volatile instruction memory105and a firmware table memory (to be also referred to as an FW table memory hereinafter)106(when it is unnecessary to distinguish between the instruction table memory105and FW table memory106, they will simply be called volatile memories in some cases), an ECC (Error Correcting Code) circuit107, and a flash interface (flash I/F)108.

The host interface101is connected to the host device (external device)200such as a personal computer via a data bus300, and further connected to the bus104. The host device200and memory system100exchange data and the like via the host interface101.

The memory buffer102is connected to the host interface101, and further connected to the bus104. The memory buffer102receives, via the host interface101, data transmitted from the host device200to the memory system100, and temporarily holds the data. Also, the memory buffer102temporarily holds data to be transmitted from the memory system100to the host device200via the host interface101.

The CPU103controls the operation of the whole memory system100. The CPU103controls all the NAND flash memory chips110based on data (instructions or control programs) stored in the volatile memories. More specifically, the CPU103reads out control programs (instruction codes) stored in an IROM (Instruction ROM) (not shown) and IRAM (Instruction RAM) (not shown) via the bus104, decodes the instruction codes, and executes predetermined processes based on the instruction codes. For example, the CPU103executes a predetermined process on the NAND flash memory chip110in accordance with a command received from the host device200in accordance with a control program.

The IROM is a nonvolatile memory, the IRAM is a volatile memory, and each memory stores a pure operation program (an instruction code of the CPU103) necessary for the CPU to operate.

The instruction table memory105is, e.g., a volatile memory, and stores, e.g., instruction codes for accessing the NAND flash memory chips110. The instruction table memory105holds coded sequences (instruction codes) necessary to access the NAND flash memory chips110.

The FW table memory106is connected to the bus104. The FW table memory106is, e.g., a volatile memory, and holds, e.g., control programs to be executed by the CPU103. More specifically, the FW table memory106is used as a temporary buffer for the work of the CPU103. For example, the FW table memory106is a memory for holding, as a temporary buffer, a logical-physical conversion table (to be simply referred to as a table in some cases) for converting a logical address to be accessed from the host device200into a physical address, and FW use information.

Note that data to be held in the instruction table memory105and FW table memory106are stored in the NAND flash memory chips110. For example, in accordance with a READ command issued by the CPU103after the memory system100is powered on, various kinds of data are read out from the NAND flash memory chips110and supplied to the instruction table memory105and FW table memory106.

The logical-physical conversion table is a table for associating a physical address in a memory cell array11of the NAND flash memory chip110(to be described later) with a logical address managed by the host device200. The CPU103can convert a logical address supplied from the host device200into a physical address by referring to the logical-physical conversion table, and read out data corresponding to the logical address from the NAND flash memory chip110. The physical address indicates, e.g., information of a physical block address and physical page address.

In this embodiment, the logical-physical conversion table is prepared for each chip. More specifically, logical-physical conversion tables0to n are prepared. Logical-physical conversion table0is held in chip0, and physical addresses in chip0are set. Similarly, logical-physical conversion table1is held in chip1, and physical addresses in chip1are set. However, this is merely an example, and the present embodiment is not limited to this. For example, it is also possible to prepare one logical-physical conversion table for every plurality of chips, or prepare a plurality of logical-physical conversion tables for one chip. Also, each chip holds its own logical-physical conversion table in this embodiment, but the present embodiment is not limited to this, and one chip may hold all logical-physical conversion tables.

The CPU103sequentially updates the set contents of the logical-physical conversion tables by, e.g., writing data in and erasing data from the NAND flash memory chips110.

In this embodiment, the FW table memory106holds one logical-physical conversion table. The CPU103reads out a new logical-physical conversion table from the NAND flash memory chip110, and updates the logical-physical conversion table in the FW table memory106.

Also, in this embodiment, the instruction table memory105and the FW table memory106will simply be called volatile memories in some cases.

The ECC circuit107is connected to the memory buffer102, instruction table memory105, and FW table memory106. The ECC circuit107receives write data from the host device200via the memory buffer102, adds an error correcting code to the write data, and supplies the write data having the error correcting code to, e.g., the memory buffer102or flash interface108. Also, the ECC circuit107receives data supplied from the NAND flash memory chip110via the flash interface108, performs error correction on the data by using an error correcting code, and supplies the error-corrected data to, e.g., the memory buffer102, instruction table memory105, or FW table memory106.

The flash interface108is connected to the ECC circuit107, bus104, and instruction table memory105. Also, the n+1 NAND flash memory chips (chips0to n) are connected to the flash interface108via a data bus400. The CPU103and firmware (FW) request the flash interface108to issue a NAND command to each chip. In response to this request, the flash interface108exchanges data with each chip without intervening the CPU103.

Note that data (e.g., instructions and control programs) to be stored in the instruction table memory105and FW table memory106are data associated with a basic instruction set, e.g., data necessary to control the NAND flash memory chips110, or data necessary for the basic operation of the memory system100. For example, if the data associated with this basic instruction set do not exist in the volatile memories, the memory system100cannot respond to a command request from the host device200.

The data (e.g., instructions and control programs) associated with this basic instruction set are held in the NAND flash memory chips110. In addition, various instruction sets unique to processes different from the basic instruction set are held in the NAND flash memory chips110.

<Overall Arrangement of NAND Flash Memory>

Next, an outline of the arrangement of the NAND flash memory chip110according to the embodiment will be explained with reference toFIG. 2.FIG. 2is a block diagram schematically showing the basic arrangement of the NAND flash memory chip110according to the embodiment.

As shown inFIG. 2, the NAND flash memory chip110includes the memory cell array11, a bit line controller12, a column decoder13, a data input/output buffer14, a data input/output terminal15, a row decoder16, a control circuit17, a control signal input terminal18, and a source line controller19.

The memory cell array11includes a plurality of bit lines BL, a plurality of word lines WL, and a source line SL. The memory cell array11includes a plurality of blocks BLK in each of which electrically programmable memory cell transistors (to be also simply referred to as, e.g., memory cells) MT are arranged in a matrix. The memory cell transistor MT has a stacked gate including a control gate electrode and a charge storage layer (e.g., a floating gate electrode), and stores multilevel data in accordance with the change in threshold of the transistor, which is determined by a charge amount injected into the floating gate electrode. The memory cell transistor MT may also have a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure in which electrons are trapped in a nitride film.

The bit line controller12includes a sense amplifier (not shown) for sensing and amplifying the voltage of the bit line BL in the memory cell array11, and a data storage circuit (not shown) for latching data to be written. The bit line controller12reads out data from the memory cell transistor MT in the memory cell array11via the bit line BL, detects the state of the memory cell transistor MT via the bit line BL, and writes data in the memory cell transistor MT by applying a write control voltage to the memory cell transistor MT via the bit line BL.

The column decoder13selects the data storage circuit in the bit line controller12, and outputs data of the memory cell transistor MT, which is read out to the data storage circuit, from the data input/output terminal15to the outside (the memory controller100a) via the data input/output buffer14.

The data input/output buffer14receives data from the data input/output terminal15, and the received data is stored in the data storage circuit selected by the column decoder13. Also, the data input/output buffer14outputs data outside via the data input/output terminal15.

The data input/output terminal15receives various commands such as write, read, erase, and status read, and addresses, in addition to write data.

The row decoder16selects one block BLK and sets other blocks BLK in an unselected state, in a data read, write, or erase operation. That is, the row decoder16applies voltages necessary for a read, write, or erase operation to the word lines WL and select gate lines VSGS and VSGD of the memory cell array11.

The source line controller19controls the voltage of the source line SRC.

The control circuit17controls the memory cell array11, bit line controller12, column decoder13, data input/output buffer14, row decoder16, and source line controller19. The control circuit17includes a boosting circuit (not shown) for boosting the power supply voltage. The control circuit17boosts the power supply voltage as needed by the boosting circuit, and applies the boosted voltage to the bit line controller12, column decoder13, data input/output buffer14, row decoder16, and source line controller19.

The control circuit17controls the operation in accordance with control signals externally input via the control signal input terminal18, and commands input from the data input/output terminal15via the data input/output buffer14. That is, the control circuit17generates desired voltages for data programming, verify, read, and erase in accordance with the control signals and commands, and applies the voltages to the individual units of the memory cell array11.

For example, the memory cell array11performs data write and read page by page. As shown inFIG. 3, each page is, a memory space of a set of a plurality of memory cell transistors, and a unique physical address is allocated to the page. Each memory cell transistor MT changes the threshold voltage in accordance with the number of electrons stored in a charge storage layer CS, and stores information corresponding to the threshold voltage. A NAND string is formed by connecting the current paths (sources/drains SD) of the memory cell transistors MT in series, and selection transistors S1and S2are connected to the two ends of the NAND string. The other end of the current path of the selection transistor S2is connected to the bit line BL, and the other end of the current path of the selection transistor S1is connected to the source line SL.

Word lines WL0to WL63extend in the WL direction, and are connected to control gate electrodes CG of a plurality of memory cell transistors MT belonging to the same row. The memory cell transistors MT are formed at the intersections of the bit lines BL and word lines WL. A select gate line SGD extends in the WL direction, and is connected to all selection transistors S2in the block. A select gate line SGS extends in the WL direction, and is connected to all selection transistors S1in the block. A plurality of memory cell transistors MT connected to the same word line WL form a page.

As shown inFIG. 4, the memory cell array11includes a memory cell array91including a plurality of memory cell transistors, and a page buffer92for exchanging data with the memory cell transistors. The page buffer92holds data of one page. When writing data in the memory cell array11, the memory controller100atransmits a write command, a page address indicating the write destination, and write data of one page to the memory cell array11. The memory cell array11stores the write data received from the memory controller100ain the page buffer92, and writes the write data in memory cells designated by the page address from the page buffer92. When starting this write operation to the memory cells, the memory cell array11outputs a busy signal indicating that the operation is in progress, to the memory controller100a. When successively writing data, the same operation as above is performed for the next page address after the busy signal is switched to a ready signal.

When reading out data from the memory cell array11, the memory controller100atransmits a read command and a page address indicating the read source to the memory cell array11. The memory cell array11reads out data of one page to the page buffer92from memory cells designated by the page address. When staring this read operation from the memory cells, the memory cell array11outputs a busy signal to the memory controller100a. After the busy signal is switched to a ready signal, the readout data stored in the page buffer92is output to the memory controller100a. When successively reading out data, the same operation as above is performed for the next page address.

The memory cell transistor MT can take two or more states having different threshold voltages. That is, the memory cell array11can also be configured so that one memory cell can store multilevel data (multi-bit data). In a memory thus capable of storing multilevel data, a plurality of pages are allocated to one word line.

Also, the memory cell array11erases data block by block. Each block includes a plurality of pages having consecutive physical addresses. However, the memory cell array11is not necessarily limited to a NAND flash memory.

The memory system100according to this embodiment adopts a memory interleave system capable of simultaneously programming a plurality of memory chips in parallel.

That is, this interleave system can start programming chip1while chip0is busy, and then can start programming chip0while chip1is busy.

<Operation of Memory System>

The operation of the memory system100when the host device200successively reads out a plurality of data from the NAND flash memory chips110by using the above-described interleave system will be explained below with reference toFIG. 5.

When successively reading out a plurality of data from the NAND flash memory chips110, the memory system100according to this embodiment first determines the addresses of data requested by the host device200.

Then, the memory system100issues a command for reading out data or a logical-physical conversion table from a given NAND flash memory chip110, and at the same time requests the issue of a NAND command for reading out a logical-physical conversion table corresponding to data to be read out next from another NAND flash memory chip110, by using the interleave system.

The memory system100receives a host command (a command issued by the host is called a host command) and a logical address from the host device200via the data bus300. The CPU103sequentially reads out data corresponding to the logical address supplied from the host device200.

The CPU103determines whether the logical address to be read is set in the logical-physical conversion table expanded in the FW table memory106.

If the CPU103determines in step S1002that the received logical address is not set in the logical-physical conversion table expanded in the FW table memory106, the CPU103determines, by the firmware (FW), a logical-physical conversion table in which the received logical address is set. Then, the CPU103determines whether there is a chip from which data or a table is currently being read out, or a chip for which a read operation is scheduled to be performed.

If the CPU103determines in step S1003that there is a chip from which data or a table is currently being read out or a chip for which a read operation is scheduled to be performed, the CPU103determines whether this chip is the same as the chip from which a logical-physical conversion table is to be read out. If this chip is the same as the chip from which a logical-physical conversion table is to be read out, the CPU103repeats the operation in step S1003.

If the CPU103determines in step S1004that the chip for which a read operation is presently being performed or the chip for which a read operation is scheduled to be performed is not the same as the chip from which a logical-physical conversion table is scheduled to be read out, the CPU103requests the flash interface108to issue a NAND command for reading out a logical-physical conversion table to the chip for which no read operation is presently being performed and which holds the logical-physical conversion table, and issue a NAND command for reading out data by using the logical-physical conversion table. Consequently, the flash interface108issues various NAND commands to the target chip. Meanwhile, the CPU103and FW continue step S1011.

If the CPU103determines in step S1003that there is no corresponding chip, the CPU103requests the flash interface108to issue a NAND command for reading out the logical-physical conversion table to the chip holding the logical-physical conversion table. Consequently, the flash interface108issues various NAND commands to the target chip. Meanwhile, the CPU103and FW continue step S1011.

If the CPU103determines in step S1002that the received logical address is set in the logical-physical conversion table expanded in the FW table memory106, the CPU103grasps a chip storing the data to be read out. Then, the CPU103determines whether there is a chip from which data or a table is currently being read out, or a chip for which a read operation is scheduled to be performed.

If the CPU103determines in step S1007that there is a chip from which data or a table is currently being read out or a chip for which a read operation is scheduled to be performed, the CPU103determines whether this chip is the same as the chip from data is to be read out. If this chip is the same as the chip from which data is to be read out, the CPU103repeats the determining operation in step S1007.

If the CPU103determines in step S1008that the chip for which a read operation is presently being performed or the chip for which a read operation is scheduled to be performed is not the same as the chip from which data is to be read out, the CPU103requests the flash interface108to issue a NAND command for reading out the data, by the interleave system. Consequently, the flash interface108issues various NAND commands to the target chip. Meanwhile, the CPU103and FW continue step S1011.

If the CPU103determines in step S1007that there is neither a chip from which data or a table is presently being read out nor a chip for which a read operation is scheduled to be performed, the CPU103requests the flash interface108to issue a NAND command for reading out the data. Consequently, the flash interface108issues various NAND commands to the target chip. Meanwhile, the CPU103and FW continue step S1011.

After the CPU103requests the flash interface108to issue a read command for the data in steps S1005, S1006, S1009, and S1010, the CPU103determines whether the host device200has made preparations to issue NAND commands for reading out all data corresponding to the logical addresses supplied from the host device200. If the CPU103determines that the host device200has not made preparations to issue NAND commands for reading out all data corresponding to the logical addresses supplied from the host device200, the process returns to step S1002even while data or a conversion table is being read out from a chip. If the CPU103determines that the host device200has made preparations to issue NAND commands for reading out all data corresponding to the logical addresses supplied from the host device200, the CPU103terminates the operation.

<Functions and Effects of Memory System According to This Embodiment>

When successively reading out a plurality of data, the memory system100according to the above-described embodiment reads out data or a logical-physical conversion table from a given NAND flash memory chip110, and at the same time reads out a logical-physical conversion table corresponding to data to be read out next, from another NAND flash memory chip110.

This makes it possible to shorten the data output waiting time, and improve the performance of successive read of a plurality of data. Consequently, a plurality of data can rapidly be read out from the memory system100.

To exhibit the effects of this embodiment, a practical example in which the host device200sequentially reads out data A and B from the memory system100will be explained below with reference toFIG. 6. (A) inFIG. 6is a sequence diagram showing the relationship between the host device200, the memory system100, and chips, and indicating the practical example according to this embodiment. (B) inFIG. 6is a sequence diagram showing the relationship between the host device200, the memory system100, and chips, and indicating a comparative example according to this embodiment.

The waveform of “Data line300” shown inFIG. 6is a waveform indicating the ready/busy state of the memory system100when viewed from the host device200. The waveform of “Chip0” shown inFIG. 6is a waveform indicating the ready/busy state of chip0. The waveform of “Chip1” shown inFIG. 6is a waveform indicating the ready/busy state of chip1.

In this example, physical address A of data A is set in logical-physical conversion table A, and physical address B of data B is set in logical-physical conversion table B. Also, in this example, logical-physical conversion table A and data A are stored in chip0, and logical-physical conversion table B and data B are stored in chip1. Furthermore, in this example, logical-physical conversion table A is expanded in the FW table memory106.

An operation by which the memory system100sequentially successively reads out data A and B from the NAND flash memory chips110in this case will be explained below.

A practical example according to this embodiment when the host device200issues a host command for reading out data A and B to the memory system100will be explained with reference to (A) inFIG. 6. Note that the host device200supplies logical address A corresponding to data A and logical address B corresponding to data B to the memory system100so as to sequentially read out data A and B.

At time T0, the CPU103performs logical-physical conversion on logical address A, among logical addresses supplied from the host device200, which corresponds to data A to be read out first. Before that, the CPU103determines whether logical address A is contained in a logical-physical conversion table expanded in the FW table memory106(step S1002inFIG. 5).

If the CPU103determines that logical address A is contained in the logical-physical conversion table expanded in the FW table memory106, the CPU103converts logical address A into physical address A by using the FW table memory106(step S1007inFIG. 5). Also, the CPU103determines whether there is a chip from which data or a table is currently being read out (step S1007inFIG. 5). If the CPU103determines that there is no chip from which data or a table is presently being read out, the CPU103requests the flash interface108to issue physical address A (Add in (A) inFIG. 6) and a NAND command (Command in (A) inFIG. 6) for setting the data address of data A, to chip0having physical address A (step S1010inFIG. 5).

At time T1, the CPU103performs logical-physical conversion on logical address B supplied from the host device200, because no NAND command is issued for physical address B corresponding to logical address B (step S1011inFIG. 5).

Before that, the CPU103determines whether logical address B is contained in the logical-physical conversion table expanded in the FW table memory106(step S1002inFIG. 5).

If the CPU103determines that logical address B is not contained in the logical-physical conversion table expanded in the FW table memory106, the CPU103determines whether there is a chip from which data or a table is currently being read out (step S1003inFIG. 5). If the CPU103determines that there is a chip from which data or a table is presently being read out, the CPU103determines whether the chip for which a read operation is presently being performed is the same as a chip storing the logical-physical conversion table containing logical address B (step S1004inFIG. 5). If the CPU103determines that the chip for which a read operation is presently being performed is not the same as the chip storing the logical-physical conversion table containing logical address B, the CPU103requests the flash interface108to issue, to chip1, a NAND command for setting the table address of logical-physical conversion table B in which logical address B of data B is set, by using the interleave system (step S1005inFIG. 5).

At time T2, the input of the NAND command and physical address A to chip0is completed, and the data line between chip0and the memory controller100ais set in the busy state during that.

Thus, when the memory system100starts executing a host command, the memory system100is set in the busy state when viewed from the host device200. The memory system100is kept in the busy state when viewed from the host device200, until chip0outputs data A to the memory controller100a. This busy time is the total time of a time during which the FW performs a read (or write) operation, and the busy time between the memory controller100aand each chip.

At time T3, the input of the NAND command and the address of the logical-physical conversion table for converting logical address B to chip1is completed, and the data line between chip1and the memory controller100ais set in the busy state.

At time T4, physical address A is set in chip0, and the flash interface108issues a NAND command for reading data A based on the request from the CPU103.

At time T5, the address of logical-physical conversion table B is set in chip1, and the flash interface108issues a NAND command for reading out logical-physical conversion table B based on the request from the CPU103.

At time T6, data A is supplied from chip0to the memory controller100avia the data bus400.

Also, when data A is read out from chip0, the memory system100changes from the busy state to the ready state when viewed from the host device200.

At time T7, logical-physical conversion table B is read out from chip1to the memory controller100a, and set in the FW table memory106.

At time T8, the memory controller100areads out data A, and then reads out data B. Consequently, the data line300changes to the busy state again until data B is read out.

At time T9, the CPU103converts logical address B supplied from the host device200into physical address B by referring to the FW table memory106, and the flash interface108issues a NAND command for setting the address of physical address B to chip1having physical address B.

At time T10, the input of physical address B to chip1is completed, and the data line between chip1and the memory controller100ais set in the busy state during that.

At time T11, the CPU103issues a NAND command for reading out data B to chip1.

At time T12, data B is read out from chip1to the memory controller100a. Consequently, the data bus300changes from the busy state to the ready state.

As described above, the memory system100according to this embodiment can almost simultaneously issue NAND commands to different chips by using the interleave system.

Comparative Example

Next, the comparative example of this embodiment will be explained with reference to (B) inFIG. 6. In this comparative example, a memory system having no interleave system will be explained. Since the memory system according to the comparative example has no interleave system, neither data nor a read NAND command cannot be issued to a given chip while data or a table is read out from another chip. Accordingly, no read NAND command cannot be issued to a given chip until the execution of a NAND command issued to another chip is completed. As indicated by (B) inFIG. 6, therefore, after one data is read out, processing for the next data is performed. Consequently, when reading out data A and B in (A) and (B) ofFIG. 6, the difference between the time required for the memory system100according to this embodiment to read out data A and B and the time required for the memory system according to the comparative example to read out data A and B is a time Tx.

As described above, the memory controller100aaccording to this embodiment issues a command for loading a logical-physical conversion table from chip1while issuing a data read command to chip0. Therefore, while data is read out from chip0, logical-physical conversion table B can be read out from chip1. This makes it possible to reduce the busy time compared to the operation by which logical-physical conversion table B is read out after data A is read out.

Note that in the above-described practical example, the memory controller100aissues a command for loading a logical-physical conversion table while issuing a data read command. However, the present embodiment is not limited to this, and it is also possible to issue a command for loading a logical-physical conversion table corresponding to data to be read out next while issuing a command for reading out a logical-physical conversion table.

Also, the host device200performs the data read operation in the above-described embodiment and practical example. However, the present embodiment is not necessarily limited to this, and this embodiment is also applicable to an operation by which the host device200issues a write command to the memory system100.