Method and system for controller hold-margin of semiconductor memory device

A system for controlling a hold-margin in a semiconductor memory device includes a programmable RC network communicatively coupled to a delay logic circuit, a latch clock generator and a latch circuit. A delay associated with a clock path is induced using a combination of a logic circuit and a wire placed across at least one of a column and a row of the semiconductor memory device. A delay associated with the data path is induced using a combination of the delay logic circuit and at least one of the load cell and a wire routed across at least one of a column and a row of the semiconductor memory device. The system controls the hold-margin based on the delay associated with the data path and the delay associated with the clock path.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Indian Patent Application No. 201841011733 filed on Mar. 28, 2018, in the Indian Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present application relates to a semiconductor memory device, and more particularly to a method and system for controlling a hold-margin of a semiconductor memory device.

BACKGROUND

A System On Chip (SOC) includes a semiconductor memory device (e.g., on-chip memory or the like). Usually 10% to 40% of an area of the SOC is occupied by the on-chip memory. The on-chip memory can be a Static Random-Access Memory (SRAM), a Read-Only Memory (ROM), and a register file. The on-chip memory contains two types of hardware circuits (e.g., bitcell array circuit and periphery circuit). The bitcell array circuit includes an array of bitcells. Each bitcell stores 1-bit of data. The periphery circuit includes logic gates to control a read operation and a write operation.

A hold margin of the on-chip-memory indicates a delay between an internal clock signal and a data signal (e.g., address signal, enable signal, or the like). The hold margin corresponds to a data path delay (D2) greater than an internal clock path delay (D1) as shown inFIG. 1. Conventionally the data signal is delayed to meet a hold margin.FIG. 1shows implementation of the delay using logic gates in the data path. A circuit100includes a clock generator102, a set of delay logics104a-104c, a logic106, a latch clock generator108, a latch110, a decoder112, a set of input/output (IO) circuits114a-114c. The latch clock generator108is connected to the latch110, where the latch110is connected to the decoder112. The clock generator102, the set of delay logics104a-104c, the logic106, and the latch clock generator108are included in a control block150.

Since the logic gate delay varies across Process, Voltage and Temperature (PVT) corners, the number of delay logics104a-104crequired are very high to satisfy the hold margin across the PVT range. This results in limiting performance of a compiler associated with the SOC. Further, the number of delay logics104a-104cplaced is based on the biggest instance, so small instances will unnecessarily contain an extra delay, which hampers performance of the semiconductor memory device.

Further, the required amount of delay to meet the hold margin is different for different sizes of the semiconductor memory device. Further, the same number of delay logics104a-104cis placed inside the control block150, regardless of the different sizes of the semiconductor memory device. Thus, the number of delay cells cannot be changed based on the size of the semiconductor memory device and the delay required for biggest instance (i.e., large numbers of usage of the10circuit) is used in smaller instances (i.e., less numbers of usage of the10circuit) as well. This hampers performance of the smaller instances.

SUMMARY

Embodiments herein disclose a method for controlling a hold-margin of a semiconductor memory device. The method includes inducing a delay associated with a clock path using a combination of a logic circuit and a wire placed across at least one of a column and a row of the semiconductor memory device. Further, the method includes inducing a delay associated with a data path using a combination of at least one delay logic circuit and at least one load cell and a wire placed across at least one of a column and a row of the semiconductor memory device. Further, the method includes controlling the hold-margin based on the delay associated with the data path and the delay associated with the clock path.

Embodiments herein disclose a system for controlling a hold-margin in a semiconductor memory device. The system includes at least one delay logic circuit, a latch clock generator, a clock generator, and a programmable resistor-capacitor (RC) network. The clock generator generates a clock signal and a data path. The programmable RC network is communicatively coupled to the at least one delay logic circuit, the latch clock generator and a latch circuit. A delay associated with the clock path is induced using a combination of a logic circuit and a wire placed across at least one of a column and a row of the semiconductor memory device. A delay associated with the data path is induced using a combination of the at least one of a delay cell and at least one of load cell and a wire placed across at least one of a column and a row of the semiconductor memory device. The system is configured to control the hold-margin based on the the delay associated with the data path and the delay associated with the clock path.

DETAILED DESCRIPTION

The terms first level and second level, high and low and 1 and 0, as used in the following description may be used to describe various logic states as known in the art. Particular voltage values of the second and first levels are defined arbitrarily with regard to individual circuits. Furthermore, the voltage values of the second and first levels may be defined differently for individual signals such as a clock and a digital data signal. Although specific circuitry has been set forth, it will be appreciated by those skilled in the art that not all of the disclosed circuitry is required to practice the disclosure. Moreover, certain well known circuits have not been described, to maintain focus on the disclosure. Similarly, although the description refers to logical “0” and logical “1” or low and high in certain locations, one skilled in the art appreciates that the logical values can be switched, with the remainder of the circuit adjusted accordingly, without affecting operation of the present disclosure.

Embodiments herein provide a system for controlling a hold-margin in a semiconductor memory device. The system includes at least one delay logic circuit, a latch clock generator, a clock generator, and a programmable resistor-capacitor (RC) network. The clock generator generates a clock signal and a data path. The programmable RC network is communicatively coupled to the at least one delay logic circuit, the latch clock generator and the latch circuit. A delay associated with a clock path is induced using combination of a logic circuit and a wire placed across at least one of a column and a row of the semiconductor memory device. A delay associated with the data path is induced using a combination of the at least one delay logic circuit, at least one of a load cell and a wire placed across at least one of a column and a row of the semiconductor memory device. The system is configured to control the hold-margin based on the the delay associated with the data path and the delay associated with the clock path.

In an embodiment, the delay associated with the clock path is induced using a combination of the logic circuit and the wire placed across the column of the semiconductor memory device. The delay associated with the data path is induced using a combination of at least one of the delay logic circuits and at least one of the load cell and the wire placed across the column of the semiconductor memory device. The system is configured to control the hold-margin based on the delay associated with the data path and the delay associated with the clock path.

In an embodiment, the delay associated with the clock path is induced using a combination of the logic circuit and the wire placed across the column of the semiconductor memory device. The delay associated with the data path is induced using a combination of at least one of the delay logic circuits and at least one of the load cell and the wire placed across a plurality of columns of the semiconductor memory device. The system is configured to control the hold-margin based on the delay associated with the data path and the delay associated with the clock path.

In an embodiment, the delay associated with the clock path is induced using a combination of the logic circuit and the wire placed across the row of the semiconductor memory device. The delay associated with the data path is induced using a combination of at least one of the delay logic circuit and at least one of the load cell and the wire placed across the row of the semiconductor memory device. The system is configured to control the hold-margin based on the delay associated with the data path and the delay associated with the clock path.

In an embodiment, the delay associated with the clock path is induced using a combination of the logic circuit and the wire placed across the row of the semiconductor memory device. The delay associated with the data path is induced using a combination of at least one of the delay logic circuit and at least one of the load cell and the wire placed across the plurality of rows of the semiconductor memory device. The system is configured to control the hold-margin based on the delay associated with the data path and the delay associated with the clock path.

In an embodiment, the delay associated with the clock path is induced using a combination of the logic circuit and the wire placed across a combination of the row and the column of the semiconductor memory device. The delay associated with the data path is induced using a combination of at least one of the delay logic circuit and at least one of the load cell and the wire placed across the combination of the row and the column of the semiconductor memory device. The system is configured to control the hold-margin based on the delay associated with the data path and the delay associated with the clock path.

In an embodiment, the delay associated with the clock path is induced using a combination of the logic circuit and the wire placed across a combination of the row and the column of the semiconductor memory device. The delay associated with the data path is induced using a combination of at least one of the delay logic circuit and at least one of the load cell and the wire placed across the combination of the plurality of rows and the plurality of columns of the semiconductor memory device. The system is configured to control the hold-margin based on the delay associated with the data path and the delay associated with the clock path.

In an embodiment, the system is configured to determine a required amount of the delay associated with the data path to control the hold margin when the number of columns are minimum.

In an embodiment, the system is configured to determine a required amount of the delay associated in the data path to control the hold margin when the number of columns are maximum.

In an embodiment, the system is configured to control the hold-margin of the semiconductor memory device using the programmable RC network based on at least a difference between the required amount of the delay associated with the data path when the number of columns are maximum and the required amount of the delay associated with the data path when the number of columns are minimum.

In an embodiment, the system is configured to determine the required amount of the delay associated with the data path to control the hold margin when the number of rows are minimum.

In an embodiment, the system is configured to determine a required amount of the delay in the data path to control the hold margin when the number of rows are maximum.

In an embodiment, the system is configured to control the hold-margin of the semiconductor memory device using the programmable RC network based on at least a difference between the required amount of the delay associated with the data path when the number of rows are maximum and the required amount of the delay associated with the data path when the number of rows are minimum.

In an embodiment, the hold margin is a parasitic delay based hold margin.

In an embodiment, the hold margin can be referred to as an internal hold margin of the SRAM.

In an embodiment, the hold-margin corresponds to a difference between the delay associated with the data path and the delay associated with the clock path.

In an embodiment, the delay associated with the data path is based on operation of the least one delay logic circuit along with a programmable RC network.

In an embodiment, the system is configured to manage the at least one hold-margin across a PVT corner.

Unlike related-art circuits, the disclosed system and method can be used to control the parasitic delay based hold-margin in a high-speed memory (e.g., SRAM, a ROM, or the like). The disclosed system and method can be used to improve the performance of the high-speed memory. In an example, for a compiler (e.g., 28 nm RA1HC compiler, SS28LPP_RA1HC compiler, or the like), 2% to 6% of performance gain has been achieved, based on the size of the memory.

The disclosed system and method can be used to reduce the logic gate in a control block of the semiconductor memory device because a lesser delay cell requirement exists in the semiconductor memory device. This results in an area gain, in some cases where the area of a macro is limited by the control block. In related-art circuits, a physical area occupied by the semiconductor memory device is greater due to the control block requiring more area for a greater amount of the delay logic cells. Such greater area results in increasing the cost of a circuit design. But, the disclosed method can be used to reduce the system design cost as the hold-margin is controlled based on the delay associated with the data path and the delay associated with the clock path and the delay associated with the data path is implemented using the wire placed across the column and the row of the semiconductor memory device. In advanced technology semiconductor memory device, a logic gate variation is higher compared to an RC delay variation, so that the method will be more effective with technology scaling. In the disclosed circuits, the wire is placed across the column and the row of the semiconductor memory device, so as to reduce the delay cell variation in the semiconductor memory device.

The disclosed method can be implemented in the compiler (e.g., 28 nm SS28RA1HC memory compiler, 10 nm RF2HS memory compiler, or the like), an SRAM compiler, a wireless communication device, a TV, an embedded system, an application processor, or any other digital SoC or Integrated Circuit (IC).

Referring now to the drawings and more particularly toFIGS. 2 through 6, where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments.

FIG. 2is a circuit diagram200illustrating an RC-network delay across columns for a latch clock generation, according to an embodiment as disclosed herein.

In general, a semiconductor memory device (e.g., SRAM, ROM, register files, or the like) includes a memory cell array (not shown) having a plurality of memory cells (not shown) arranged in a matrix of rows and columns. A plurality of word lines (not shown) is arranged to correspond to the respective rows of the memory cells. A plurality of bit lines (not shown) is arranged to correspond to the respective columns of the memory cells. The wire contains parasitic resistance (not shown), and the load cell connected to the wire is nothing but capacitance.

Specifically, the memory cells are placed individually at the respective points of intersection between the word line and the bit line pairs. The memory cells thus arranged as the matrix compose the memory cell array for storing information.

Referring to theFIG. 2, the circuit diagram200includes a control block150, a latch110, a decoder112, input/output circuits (IO-0114a-114c), and a set of loads116a-116n, where the control block150includes a clock generator102, a delay logic104, a logic circuit106and a latch clock generator108. A clock input and an enable input (e.g., data input, address input or the like) are provided to the clock generator102. The clock generator102provides a Node A, where the Node A is a diverging point for a clock path (D1) and a data path (D2). The clock path (D1) comprises the logic circuit106and a wire routed across columns of the semiconductor memory device. The latch clock generator108is coupled with the latch110, where the latch110is coupled with the decoder112.

A delay associated with the clock path (D1) is induced using combination of the logic circuit106and the wire routed across the columns of the semiconductor memory device. A data path (D2) is implemented using a combination of delay logic104, loads116a-116n, and a wire placed across the columns of the semiconductor memory device to fix the hold margin. The delay associated with the data path (D2) is induced using a combination of the delay logic104, at least one of the loads116a-116nand the wire placed across the columns of the semiconductor memory device. The clock path (D1) and the data path (D2) converge at a Node B, such that a data path delay (TD2) is more than a clock path delay (TD1).

Further, the size of the programmable RC network is a function of a memory size (IO-0to IO-n114a-114c), “n” increases/decreases as a size of the memory increases/decreases, so that the delay provided by the RC-network scales along with “n”. The RC network delay variation is less compared to the delay cell variation across PVT corners. This results in achieving higher performance of the semiconductor memory device.

Further, a latch clock can be identified based on the latch110. By traversing the latch clock, the latch clock generator108can be identified, and an input to the latch clock generator108can be detected if the input is routed across rows/columns.

FIG. 3is a circuit diagram300illustrating the RC-network delay across rows for the latch clock generation, according to an embodiment as disclosed herein. The semiconductor memory device including the memory cell array (not shown) having the plurality of memory cells (not shown) arranged in the matrix of rows and columns. The plurality of word lines (not shown) is arranged to correspond to the respective rows of the memory cells. The plurality of bit lines (not shown) is arranged to correspond to the respective columns of the memory cells. The wire contains parasitic resistance (not shown), and the load cell connected to the wire is nothing but capacitance.

The circuit diagram300includes the control block150, the latch110, the decoders112a-112d, and the set of loads116a-116n, where the control block150includes the clock generator102, the delay logic104, the logic circuit106and the latch clock generator108. The clock input and the enable input are provided to the clock generator102. The latch clock generator108is connected with the latch110. The latch110is connected with the decoder112d.

The clock generator102provides the Node A, where the Node A is the diverging point for the clock path (D1) and the data path (D2). The clock path (D1) comprises the logic circuits106and wire placed across rows of the semiconductor memory device. The delay associated with the clock path (D1) is induced using a combination of the logic circuit106and the wire routed across the rows of the semiconductor memory device.

The data path (D2) is implemented using a combination of the delay logic104, the loads116a-116nand the wire placed across rows of the semiconductor memory device to fix the hold margin. The delay associated with the data path (D2) is induced using a combination of the delay cell104, at least one of loads116a-116nand the wire placed across the rows of the semiconductor memory device. The clock path (D1) and the data path (D2) converge at Node B, such that the data path delay (TD2) is more than clock path delay (TD1) (i.e., hold margin=TD2−TD1>0).

FIG. 4is a circuit diagram400illustrating an RC-network delay across rows and columns for latch clock generation, according to an embodiment as disclosed herein.

Referring to theFIG. 4, the semiconductor memory device including the memory cell array (not shown) having the plurality of memory cells (not shown) arranged in the matrix of rows and columns. The plurality of word lines (not shown) is arranged to correspond to the respective rows of the memory cells. The plurality of bit lines (not shown) is arranged to correspond to the respective columns of the memory cells. The wire contains parasitic resistance (not shown), and the load cell connected to the wire is nothing but capacitance.

The circuit diagram400includes the control block150, the latches110aand110b, the decoder112a-112e, the10circuits114a-114c, and a set of loads116a-116c, where the control block150includes the clock generator102, the delay logic104, the logics106aand106b, and the latch clock generator108. The clock input and the enable input are provided to the clock generator102. The latch clock generator108is connected with the latch110aand110b. The latch110ais connected with the decoder112c. The latch110bis connected to the decoder112d.

The clock generator102provides the Node A, where the Node A is the diverging point for the clock path (D1) and the data path (D2).

In the circuit diagram400, two hold margins (e.g., HM1and HM2) exist, where the HM1=D2_HM1−D1_HM1, and the HM2=D2_HM2−D1_HM2. The diverging point for both HM1and HM2is the same (i.e., NODE A).

The delay associated with the clock path (D1) is induced using a combination of the logic circuits106aand106band the wire placed across the columns and rows of the semiconductor memory device.

The delay associated with the data path (D1) is induced using a combination of the delay cell104, at least one of loads116a-116f, and the wire placed across the columns and the rows of the semiconductor memory device.

Further, the converging point (i.e., target point) for HM1is NODE B_HM1and for HM2is Node B_HM2. The data path (D2_HM1and D2_HM2) is implemented using a combination of the delay logic104, loads116a-116f, and the wire placed across rows and columns of the semiconductor memory device to fix the hold margin

FIG. 5is a circuit diagram500illustrating the RC-network delay across rows and columns for a different latch clock generation, according to an embodiment as disclosed herein.

Referring toFIG. 5, the semiconductor memory device including the memory cell array (not shown) having the plurality of memory cells (not shown) arranged in the matrix of rows and columns. The plurality of word lines (not shown) is arranged to correspond to the respective rows of the memory cells. The plurality of bit lines (not shown) is arranged to correspond to the respective columns of the memory cells. The wire contains parasitic resistance (not shown), and the load cell connected to the wire is nothing but capacitance.

The circuit diagram500includes the control block150, the latch110, the set of decoders112a-112e, the IO circuits114a-114c, and the set of loads116a-116f, where the control block150includes the clock generator102, the delay logics104aand104b, the logics106aand106b, and the latch clock generators108aand108b. The clock input and the enable input are provided to the clock generator102. The latch clock generator108bis connected with the latch circuit110. The latch circuit110is connected with the decoder112e.

In the circuit diagram500, two hold margins (i.e., HM1and HM2) exist, where the HM1=D2_HM1−D1_HM1, and the HM2=D2_HM2−D1_HM2. The diverging point for HM1is NODE A_HM1and for HM2is NODE A_HM2. The converging point for HM1is NODE B_HM1and for HM2is Node B_HM2.

In this design, different latch clock generators108aand108bare used for the two hold margins.

The delay associated with the clock paths (D1_HM1and D1_HM2) is induced using a combination of the logic circuits106aand106band the wire routed across the columns and the rows of the semiconductor memory device. The data path (i.e., D2_HM1) is implemented using a combination of the delay logic104a, the loads106a-106cand the wire placed across the rows of the semiconductor memory device, whereas the data path (i.e., D2_HM2) is implemented using combination of the delay logic104b, the loads116d-116fand the wire spread across columns of the semiconductor memory device.

In an embodiment, the two hold margins (HM1and HM2) exist: (1) HM1=D2_HM1−D1_HM1and (2) HM2=D2_HM2−D1_HM2. In this scheme different latch clock generators are used for the two hold margins. Data path D2_HM1is implemented using a combination of delay logic, wire and loads spread across rows, whereas the data path D2_HM2is implemented using a combination of delay logic, wire and loads spread across columns.

FIG. 6is a flow diagram600illustrating a method for controlling the hold-margin of the semiconductor memory device, according to an embodiment as disclosed herein. At602, the method includes inducing the delay associated with the clock path (D1) using a combination of the logic106and the wire placed across at least one of the column and the row of the semiconductor memory device. At604, the method includes inducing the delay associated with the data path (D2) using a combination of the delay cell104, at least one load and the wire placed across at least one of the column and the row of the semiconductor memory device. At606, the method includes controlling the hold-margin based on the delay associated with the data path (D2) and the delay associated with the clock path (D1).

The disclosed method can be used to determine the required amount of delay associated with the delay logic104in the data path (D2) to control the hold margin when the number of columns are minimum.

The disclosed method can be used to determine the required amount of delay in the data path (D2) to control the hold margin when the number of columns are maximum.

The disclosed method can be used to control the hold-margin of the semiconductor memory device using the programmable RC network based on at least a difference between the required amount of delay associated with the data path (D2) when the number of columns is maximum and the required amount of the delay associated with the data path (D2) when the number of columns is minimum.

The disclosed method can be used to determine the required amount of delay associated with the delay logic104in the data path (D2) to control the hold margin when the number of rows is minimum.

In an embodiment, the method can be used to determine a required amount of delay in the data path (D2) to control the hold margin when the number of rows is maximum.

In an embodiment, the method can be used to control the hold-margin of the semiconductor memory device using the programmable RC network based on a difference between the required amount of delay associated with the data path (D2) when the number of rows is maximum and the required amount of delay associated with the data path (D2) when the number of rows is minimum.

The embodiments disclosed herein can be implemented through at least one software program running on at least one hardware device and performing network management functions to control the elements. The elements shown in theFIGS. 2 to 6include blocks, elements, actions, acts, steps, or the like which can be at least one of a hardware device, or a combination of hardware device and software module.