High speed interface design

The embodiments of the present invention are directed toward the design of routing patterns, including elements such as contacts, traces, and vias, for high speed differential signal pairs in integrated circuit package substrates.

FIELD

This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to package substrate routing designs for high speed signals.

BACKGROUND

Integrated circuits are operating at ever increasing speeds. For example, integrated circuits for markets such as communication and storage are often embedded with multiple cores that send and receive signals at speeds greater than about two and one-half gigabits per second, which is defined herein to be a high speed signal or a high speed device.

As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar.

Integrated circuits are typically formed into packaged devices with a package substrate. The package substrate provides all of the electrical connections to the integrated circuit, and provides separate electrical connections to another structure, typically referred to as the printed circuit board. Thus, as the terms are used herein, there are three different structure types used in an electrical circuit, which structures are the integrated circuit, the printed circuit board, and the interface between the integrated circuit and the printed circuit board, which is the package substrate. As contemplated herein, the integrated circuit does not at any time physically contact the printed circuit board, and the printed circuit board and the package substrate are physically separate elements that are manufactured at different times and using different processes.

The distinction between the printed circuit board and the package substrate is further exemplified by the time at which they are electrically connected to the integrated circuit. The package substrate is considered to be a part of the packaged integrated circuit, and the integrated circuit is typically not shipped from the integrated circuit manufacturer until it is assembled as a packaged device with the package substrate. However, the packaged substrate is typically assembled with the printed circuit board in a different facility at a later time by a purchaser of the packed integrated circuit. Thus, one skilled in the art is able to quickly distinguish between a printed circuit board and a package substrate.

The typical construction and routing used by current technology package substrates tends to be unable to adequately handle the high speed signals used by some integrated circuit applications. What is needed, therefore, is a system of routing high speed signals in a manner that overcomes the problems and achieves the goals, such as those described above, at least in part.

SUMMARY

The above and other needs are met by a routing pattern for high speed signals for a package substrate. Traces for the high speed signals are disposed in trace pairs for differential pairs of high speed signals. The traces in a trace pair have substantially similar lengths, and are bounded along substantially their entire lengths by grounded guard traces. The traces have arcing corners, and straight portions of the traces have a length between the arcing corners and other reflecting portions of the traces that is not an integer multiple of a minimum time between transitions of the high speed signals.

Contacts for the high speed signals are connected to the high speed signal traces, where differential pairs of contacts are associated with the differential pairs of high speed signals. The contacts are exclusively disposed adjacent an edge of the package substrate, with a first of the contacts in the differential pair of contacts disposed closer to the edge of the package substrate than a second of the contacts in the differential pair. The contacts are disposed such that a line through the differential pair of contacts is substantially perpendicular to the edge of the package substrate.

The first contact in the differential pair of contacts is designated a positive contact and the second contact in the differential pair of contacts is designated a negative contact. All of the differential pairs of contacts are consistently disposed with the positive contact and the negative contact in a consistent position in each differential pair of contacts relative to the edge of the package substrate. The high speed contacts are disposed at a set orthogonal first distance one from another, and all contacts for the high speed signals are disposed from contacts for lower speed signals by a distance of more than (2)1/2times the set orthogonal first distance.

Vias for the high speed signals are connected to the high speed signal traces, where differential pairs of vias are associated with the differential pairs of high speed signals. The vias are disposed at a set orthogonal second distance one from another, and all vias for the high speed signals are disposed from vias for lower speed signals by a distance of more than (2)1/2times the set orthogonal second distance.

Plane metal is disposed symmetrically around the high speed vias and the high speed contacts. Redundant power vias are disposed adjacent a border of the package substrate where an integrated circuit edge is designed to reside. The redundant power vias connect in a straighter line between contacts on a first side of the package substrate, power planes, and contacts on an opposing second side of the package substrate than do other power vias. Power traces have a width that is greater than a width of the high speed signal traces.

DETAILED DESCRIPTION

According to the preferred embodiments of the present invention, a targeted combination of design measures are applied to a package substrate, so that it can adequately handle high speed signals without unacceptable signal loss or other degradation.FIG. 1depicts a high speed signal routing layer of a package substrate10. High speed differential signals, such as receiver signals, transmitter signals, and clocks, are routed with high speed differential pair traces12that have matched lengths, so as to avoid adding duty cycle distortion. These high speed differential pair traces12are further routed with grounded guard traces14to their connections16, which provides noise isolation for the high speed differential pair traces12. In addition, spacing between the high speed differential pair traces12is set at a value that is appropriate to the package, and provides impedance control on the high speed differential traces12.

The traces12for the high speed differential signals are routed with arcing corners18instead of angled corners20, such as those on the guard traces14, power traces, ground traces, and lower speed signal traces. The smoothly arcing, non-angled corners18help to reduce signal reflection along the traces12, which tends to become more prevalent at high signal speeds. Other traces22, such as those for analog signals, are preferably routed with wide metal traces, meaning that the traces22are wider than the traces12used for the high speed differential pair traces12, to reduce the inductance and resistance on the traces22.

In addition, all distances56between the reflections at the arcing corners18of the high speed signal traces12is preferably kept at a length that is something other than an integer multiple of a “bit time” of the high speed signal on the trace12. A “bit time” is defined herein as the minimum time between signal transitions on the high speed trace12, where the minimum time is defined by the protocol data rate, and a signal transition is defined as the signal transitioning from one logical state to another logical state, such as from a zero to a one, or from a one to a zero. Given the velocity of the waveform through the trace12material, one can calculate the time between reflections in an given specific case. The package substrate10design, specifically the straight lengths of the traces12between the arcing corners18, can then be adjusted so that major transitions (impedance mismatches) are not an integer number of bit times apart, meaning that the signal transitions will not be unduly disturbed by the reflections along the high speed signal routing trace12.

High speed differential signals are routed to balls24and26at the edge28of the package substrate10, as depicted inFIG. 2. Differential paired balls24and26at the terminus of the high speed differential signal traces12are disposed in an orientation that is perpendicular to the package substrate edge28, and all such differential pairs of connections24and26are consistently assigned with the same polarity relative to the package substrate edge28. As depicted inFIG. 2, all the connections24and26for the high speed signals are oriented with the positive signal connection24of the differential pair disposed adjacent the edge28of the package substrate10, and the negative signal connections26of the differential pair disposed farther from the edge28of the package substrate10.

It is appreciated that this is by way of example only, and that in other embodiments the negative signal connection26of the differential pair can be disposed adjacent the edge28of the package substrate10, and the positive signal connection24of the differential pair can be disposed farther from the edge28of the package substrate10.

High speed signal balls24and26are isolated from all lower speed signal balls30by more than a distance of the square root of two times the ball pad pitch36, which eliminates all orthogonally adjacent and diagonally adjacent signal ball positions from the high speed signal balls24and26as candidate positions for lower speed signal balls30. This tends to further reduce cross talk between the signals. The positions adjacent the high speed signal balls24and26can be occupied by combinations of power connections32and ground connections34. The arrangements of the high speed signal connections24and26, power connections32, ground connections34, and low speed signal connections30as depicted inFIG. 2are by way of example and not limitation, except as described otherwise herein.

Differential vias38for the high speed signals are spaced as appropriate for the package substrate10and the required frequency, while other non-differential vias40, such as power vias, are spaced by at least twice the distance as the high speed differential vias38, to reduce impedance mismatch, as depicted inFIG. 3. Spacing between planes42and high speed via capture pads or ball pads44is increased as appropriate for the required frequency, and plane metal42is disposed in a symmetrical pattern around the high speed pads44on the same layer, again to reduce impedance mismatch.

Redundant power vias46are added near a location of the package substrate10where the edge of the integrated circuit56that is mounted on the package substrate10is disposed. This may or may not be near the edge28of the package substrate10. The redundant power vias46run from connections48such as bump pads on one side of the package substrate10to power planes50and connections52such as ball pads on an opposing side of the package substrate10in a line that is as direct as possible, so as to reduce inductance and bump to ball resistance, as depicted inFIG. 4. These redundant power vias46are in addition to standard power vias54, that are disposed at a more interior location of the package substrate10, and do not necessarily take a straight line course between the connections on either side of the package substrate10.

The present invention can be applied to any package technology, cross section, ball count, body size, or varying bump and ball pitches. It is applicable to any integrated circuit package technology, such as BGA, CSP, etc., in either ceramic or plastic types, and in either wire bond or flip chip versions.