Resonant switched transformer converter

An electronic converter comprises first and second electronic switches that are connected between positive input and output terminals, where an intermediate node between the first and second electronic switches represents a first switching node. Third and fourth electronic switches are connected between the positive output terminal and a negative input terminal, where an intermediate node between the third and fourth electronic switches represents a second switching node. A first terminal of a primary winding of a transformer is connected to the second switching node, and a capacitor and inductance are connected in series between a second terminal of the primary winding and the first switching node. Fifth and sixth electronic switches are connected between the positive output terminal and a negative output terminal, where a first terminal of the secondary winding is connected to an intermediate node between the fifth and sixth electronic switches.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Italian Application No. IT 102019000006719, filed on May 10, 2019, which application is hereby incorporated herein by reference.

TECHNICAL FIELD

The embodiments of the present disclosure refer to electronic converters.

BACKGROUND

Power-supply circuits, such as AC/DC or DC/DC switching power supplies, are well known in the art. There exist many types of electronic converters, which are principally divided into isolated and non-isolated converters. For instance, non-isolated electronic converters are the converters of the “buck”, “boost”, “buck-boost”, “Ćuk”, “SEPIC”, and “ZETA” type. Instead, isolated converters are, for instance, converters of the “flyback”, “forward”, “half-bridge”, and “full-bridge” type. Such types of converters are well known to the person skilled in the art.

FIG. 1is a schematic illustration of a DC/DC electronic converter20. In particular, a generic electronic converter20comprises two input terminals200aand200bfor receiving a DC voltage Vinand two output terminals12aand12bfor supplying a DC voltage VOUT. For example, the input voltage Vinmay be supplied by a DC current generator10, such as a battery, or may be obtained from an AC voltage by means of a rectifier circuit, such as a diode bridge, and possibly a filtering circuit. Instead, the output voltage Voutmay be used for supplying a load30.

In general, as is well known, an electronic switching converter20comprises one or more reactive elements, such as capacitances and/or inductances, and one or more electronic switches that manage transfer of energy from the input200a/200bto the reactive element or elements and/or from the reactive element or elements to the output202a/202b.

Power distribution is continuously evolving from various points of view, such as power density, efficiency, and cost of the solution.

For instance, it is desirable to find converter solutions that are more efficient and at the same time compact and easy to use for the applications in which a scaling of the input voltage Vinby a factor NCONVis required, i.e., VOUT=Vin/NCONV. For instance, such voltage converters of a step-down type are widely used in the field of power management, for example in the context of computers, such as servers.

For instance, to meet the increasingly stringent requisites of power density it is necessary to reduce the size of the magnetic components (inductances, such as inductors or transformers) and, to do this, it is necessary to increase the operating frequency of the system. However, as is well known, as the operating frequency increases, also the switching losses increase in a linear way. Hence, as the switching frequency of the system increases, it is necessary to minimise the switching losses, for instance, by increasing the speed of the switches, such as the FETs (Field-Effect Transistors), for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). To meet these increasingly stringent requirements for high efficiency, there have thus been developed switching elements with increasing performance, for example in terms of switching speed and figure of merit (resistance Rdson of the MOSFETs in the closed condition multiplied by the charge Qg required until the MOSFET closes).

The demand for switches/MOSFETs with higher switching speed hence makes it possible to increase the switching frequency in order to reduce the magnetic components (inductances) and thus increase the power density of the conversion systems. However, the use of faster transistors calls for the development of more costly technologies with a major impact on the cost of the final solution of the converter.

Another way to minimise the switching losses is to get the switches/MOSFETs to function in ZVS (Zero-Voltage Switching) or ZCS (Zero-Current Switching) conditions, or else to get the switches to function with lower voltages, for example the MOSFETs to function with lower drain-to-source voltages VDS. For instance, solutions have been developed for getting the FETs to work with a fraction of input voltage Vin. In this context, the document U.S. Pat. No. 9,916,517 may, for example, be cited.

SUMMARY

Considering the foregoing, an object of various embodiments of the present description is to provide more efficient electronic converters.

According to one or more embodiments, the above object is achieved by means of an electronic converter having the distinctive elements set forth specifically in the ensuing claims.

The claims form an integral part of the technical teaching of the description provided herein.

As mentioned previously, various embodiments regard an electronic converter. In various embodiments, the electronic converter comprises a positive input terminal and a negative input terminal for receiving an input voltage, and a positive output terminal and a negative output terminal for supplying an output voltage, where the negative output terminal is connected to the negative input terminal.

In various embodiments, a first electronic switch and a second electronic switch are connected between the positive input terminal and the positive output terminal, where the intermediate node between the first and second electronic switches represents a first switching node.

In various embodiments, a third electronic switch and a fourth electronic switch are connected between the positive output terminal and the negative input terminal, where the intermediate node between the third and fourth electronic switches represents a second switching node.

In various embodiments, the electronic converter comprises a transformer, which includes a primary winding and a secondary winding. A first terminal of the primary winding is connected to the second switching node, and a capacitor and an inductance (which is implemented with an inductor and/or the dispersion inductance of the transformer) are connected in series between a second terminal of the primary winding and the first switching node.

In various embodiments, a fifth electronic switch and a sixth electronic switch are connected between the positive output terminal and the negative output terminal, where a first terminal of the secondary winding is connected to the intermediate node between the fifth and sixth electronic switches.

In various embodiments, a second terminal of the secondary winding is connected to the first terminal of the primary winding.

Alternatively, the electronic converter may comprise a seventh electronic switch and an eighth electronic switch connected between the positive output terminal and the negative output terminal, where the second terminal of the secondary winding is connected to the intermediate node between the seventh and eighth electronic switches.

In various embodiments, the electronic converter comprises a control circuit configured for generating respective driving signals for the first, second, third, and fourth electronic switches in such a way as to repeat the following switching steps during a switching cycle:during a first switching step, closing the first and third electronic switches and opening the second and fourth electronic switches; andduring a second switching step, opening the first and third electronic switches and closing the second and fourth electronic switches.

For instance, the first, second, third, and fourth electronic switches may be implemented with FETs, for example MOSFETs.

The fifth and sixth electronic switches and possibly the seventh and eighth electronic switches may be implemented with electronic switches with control terminal, such as FETs, for example MOSFETs, or may comprise a diode or be obtained with a diode.

In particular, using electronic switches with control terminal, the control circuit can also generate respective driving signals for the fifth and sixth electronic switches in such a way as to:open the fifth electronic switch and close the sixth electronic switch, during the first switching step; andclose the fifth electronic switch and open the sixth electronic switch, during the second switching step.

Instead, when the fifth and sixth electronic switches comprise a respective diode, these diodes may be configured in such a way that:the diode of the fifth electronic switch is open and the diode of the sixth electronic switch is closed, during the first switching step; andthe diode of the fifth electronic switch is closed and the diode of the sixth electronic switch is open, during the second switching step.

Likewise, when the electronic converter comprises the seventh and eighth electronic switches in the form of electronic switches with control terminal, the control circuit can also generate respective driving signals for the seventh and eighth electronic switches, in such a way as to:close the seventh electronic switch and open the eighth electronic switch, during the first switching step; andopen the seventh electronic switch and close the eighth electronic switch, during the second switching step.

Instead, when the seventh and eighth electronic switches comprise a respective diode, these diodes may be configured in such a way that:the diode of the seventh electronic switch is closed and the diode of the eighth electronic switch is open, during the first switching step; andthe diode of the seventh electronic switch is open and the diode of the eighth electronic switch is closed, during the second switching step.

In various embodiments, the first switching step and the second switching step have the same duration.

In various embodiments, the capacitor and the inductance define a resonant circuit with a resonance period. In this case, the duration of the first switching step may be between 0.7 and 1.3 times the resonance half-period, preferably between 0.9 and 1.1 time the resonance half-period, preferably one resonance half-period.

In various embodiments, the electronic converter comprises a further positive output terminal for supplying a further output voltage. In this case, the transformer can have a center-tapped secondary winding comprising a first secondary winding and a second secondary winding, where the intermediate node between the first secondary winding and the second secondary winding is connected to the further positive output terminal.

In various embodiments, the electronic converter further comprises a ninth electronic switch connected between the second electronic switch and the positive output terminal, where the ninth electronic switch is configured for connecting the second electronic switch:to the positive output terminal; orto the negative input terminal; oroptionally to the further positive output terminal.

In various embodiments, the electronic converter comprises a tenth electronic switch connected between the first terminal of the primary winding and the second switching node, where the tenth electronic switch is configured for connecting the first terminal of the primary winding:to the second switching node; orto a reference voltage.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In the ensuing description various specific details are illustrated aimed at providing an in-depth understanding of the embodiments. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that various aspects of the embodiments will not be obscured.

The references used herein are provided merely for convenience and hence do not define the sphere of protection or the scope of the embodiments.

In the ensuingFIGS. 2 to 8, parts, elements, or components that have already been described with reference toFIG. 1are designated by the same references used previously in this figure; the description of these elements presented previously will not be repeated in order not to burden the present detailed description.

FIG. 2shows a first embodiment of an electronic converter20aaccording to the present disclosure. Also in this case, the electronic converter20acomprises:two input terminals200aand200bconfigured for receiving a DC input voltage Vin; andtwo output terminals202aand202bconfigured for supplying a DC output voltage Vout;

In the embodiment considered, the negative output terminal202bis connected (for example, directly) to the negative input terminal200b, which represents a reference voltage, for example, ground GND.

In the embodiment considered, four electronic switches Q1, Q2, Q3, and Q4are connected (for example, directly) in series between the input terminals200aand200b. For instance, in various embodiments, the switches Q1, Q2, Q3, and Q4are FETs, preferably n-channel FETs, for example MOSFETs. Consequently, in the embodiment considered, a first terminal of the switch Q1is connected (for example, directly) to the terminal200a, and the second terminal of the switch Q1is connected (for example, directly) to a first terminal of the switch Q2, which thus represents a first switching node PH1. The second terminal of the switch Q2is connected (for example, directly) to a first terminal of the switch Q3, which thus represents a second switching node SN. The second terminal of the switch Q3is connected (for example, directly) to a first terminal of the switch Q4, which thus represents a third switching node PH2. Finally, the second terminal of the switch Q4is connected (for example, directly) to the terminal200b.

In the embodiment considered, the node SN is connected (for example, directly) to the output terminal202a.

In the embodiment considered, the electronic converter20afurther comprises:a capacitor CRES;an inductor LRES; anda transformer T, comprising a primary winding T1and a secondary winding T2with a given turn ratio N:1.

In particular, in the embodiment considered, the capacitor CRES, the inductor LRES, and the primary winding T1of the transformer T are connected (for example, directly) in series between the nodes PH1(node intermediate between the switches Q1and Q2) and PH2(node intermediate between the switches Q3and Q4). For instance, in the embodiment considered, a first terminal of the capacitor CRESis connected (for example, directly) to the node PH1, the second terminal of the capacitor CRESis connected (for example, directly) to a first terminal of the inductor LRES, and the second terminal of the inductor LRESis connected (for example, directly), through the primary winding T1, to the node PH2. In general, in the embodiment considered, the positions of the capacitor CRESand of the inductor LRESmay also be reversed.

For instance, the capacitance of the capacitor CRESmay be between 1 μF and 300 μF, and/or the inductance of the inductor LRESmay be between 10 nH and 1 μH.

In the embodiment considered, the secondary winding T2is connected by means of a rectifier circuit R to the output terminals202aand200b.

In particular, in the embodiment considered, the rectifier circuit comprises four electronic switches Q5, Q6, Q7, and Q8, where:the switches Q5and Q6are connected (for example, directly) between the terminals202aand202b, where a first terminal of the secondary winding T2of the transformer T is connected to the intermediate point between the switches Q5and Q6; andthe switches Q7and Q8are connected (for example, directly) between the terminals202aand202b, where a second terminal of the secondary winding T2of the transformer T is connected to the intermediate point between the switches Q7and Q8.

Consequently, the electronic switches Q5, Q6, Q7, and Q8are configured for reversing the connection of the secondary winding T2to the output terminals202aand202b.

For instance, in various embodiments, the switches Q1, Q2, Q3, and Q4are FETs, preferably n-channel FETs, for example MOSFETs. In various embodiments, the electronic switches Q5, Q6, Q7, and Q8may also comprise or consist of diodes in such a way as to implement a diode-bridge rectifier R.

In various embodiments, a further capacitor may be connected also between the terminals202aand202bin order to filter the output voltage Vout.

In the embodiment considered, the electronic converter20afurther comprises a control circuit210, such as an analog circuit and/or a digital circuit, for example, a microprocessor programmed via software code, configured for generating respective driving signals DRV1, . . . , DRV4for the switches Q1, . . . , Q4, and possibly the driving signals DRV5, . . . , DRV8for the switches Q5, . . . , Q8.

For instance, as will be described in greater detail hereinafter, the control circuit210is configured for generating the driving signals DRV1, . . . , DRV4for the switches Q1, . . . , Q4, and possibly the driving signals DRV5, . . . , DRV8for the switches Q5, . . . , Q8in such a way that the following two operating intervals are repeated periodically:during a first interval A, the switches Q1, Q3, Q6, and Q7are closed and the switches Q2, Q4, Q5, and Q8are open (seeFIG. 3A); andduring a second interval B, the switches Q2, Q4, Q5, and Q8are closed and the switches Q1, Q3, Q6, and Q7are open (seeFIG. 3B).

Consequently, as illustrated inFIG. 4, during the first interval A having a duration TA, the node PH1is connected to the terminal200a/voltage Vinand, during the second interval B having a duration TB, the node PH1is connected to the terminal202a/voltage Vout. Instead, during the first interval A with duration TA, the node PH2is connected to the terminal202a/voltage Voutand, during the second interval B with duration TB, the node PH2is connected to the terminal202b/reference voltage (ground).

In particular, as illustrated inFIG. 3Aand considering also the fact that the output voltage Voutis lower than the input voltage Vin(Vout<Vin), during step A the current IPRIthat traverses the primary winding T1flows from the terminal200a(voltage Vin), through the switch Q1, the network LRES/CRES, the primary winding T1of the transformer T, the switch Q3, and finally to the output terminal202a. Instead, the current ISECthat traverses the secondary winding T2of the transformer T (which by definition is equal to the current of the primary divided by N) flows from the terminal202b(ground), through the switch Q6, the secondary winding T2, and the switch Q7, to the terminal202a.

In particular, by appropriately sizing the components, the (positive) current IPRIwill comprise an oscillation with a resonant period TRES:
TRES=2π·√{square root over (LRES·CRES)}  (1)

In various embodiments, the duration TAis chosen so that it substantially corresponds to a half-period of the aforesaid oscillation, for example, 0.7 (TRES/2)<TA<1.3 (TRES/2), preferably 0.9 (TRES/2)<TA<1.1 (TRES/2).

During this step A, the capacitance CRESis hence on average charged to a voltage VCRES,A:
VCRES,A=Vin−(N+1)·Vout(2)

Instead, as illustrated inFIG. 3B, during step B, the current IPRIthat traverses the primary winding T1flows from the terminal200b(reference voltage, for example, ground), through the switch Q4, the primary winding T1of the transformer T, the network LRES/CRES, the switch Q2, and finally to the output terminal202a. Instead, the current ISECthat traverses the secondary winding T2of the transformer T (which by definition is equal to the current of the primary divided by N) flows from the terminal202b(ground), through the switch Q8, the secondary winding T2, and the switch Q5, to the terminal202a.

During this step B, the capacitance CRESis hence on average charged to a voltage VCRES,B:
VCRES,B=(N+1)·Vout(3)

Consequently, also in this case, the (negative) current IPRIwill comprise an oscillation with the resonant period TRES. In various embodiments, the duration TBis chosen so that it substantially corresponds to one half-period of the aforesaid oscillation, for example 0.7 (TRES/2)<TB<1.3 (TRES/2), preferably 0.9 (TRES/2)<TB<1.1 (TRES/2).

In various embodiments, the duration TAcorresponds to the duration TB, i.e., TA=TB. Consequently, in various embodiments, the control circuit210can generate two driving signals:a first driving signal for driving the switches Q1, Q3(and possibly Q6and Q7), where this signal has a constant frequency f determined according to the period TRESand a working cycle of 50%; anda second driving signal for driving the switches Q2, Q4(and possibly Q5and Q8), which corresponds to the first driving signal inverted.

Consequently, in the simplest case, the first driving signal may correspond to a clock signal supplied by an oscillator, such as a voltage-controlled oscillator (VCO), and the second driving signal may be obtained by supplying the first driving signal to an analog inverter.

In various embodiments, the electronic converter is hence non-regulated and works with a constant switching period TSW=TA+TB.

In general, the switching period TSWmay comprise also a first (brief) interval TD1between the intervals TAand TB, and a second (brief) interval TD2between the intervals TBand TA; i.e., TSW=TA+TB+TD1+TD2. These intervals (which like the intervals TAand TBmay be constant) may be useful for achieving a ZVS switching condition of the switches Q1, . . . , Q4. In particular, in this case, the duration TAshould be chosen in such a way that the current IPRIis positive at the end of the interval A and the duration TBshould be chosen in such a way that the current IPRIis negative at the end of the interval B. For instance, in various embodiments, the durations TAand TBare slightly shorter than the resonance half-period; for example, TA(and likewise TB) may be between 0.7 and 0.99 of TRES/2.

In general, the transformer T may be modelled as an ideal transformer, a dispersion inductance (typically connected in series to the primary winding T1), and a magnetisation inductance (typically connected in parallel with the primary winding T1). Consequently, in various embodiments, the inductor LRESmay also be implemented with the dispersion inductance of the transformer T, or the inductance LRESmay correspond to the sum of the inductance of an inductor (connected in series with the primary winding T1) and the dispersion inductance of the transformer T.

Through the law of charge balancing on the capacitor CRESin steps A and B, it is hence possible to write the conversion ratio NCONVof the electronic converter as follows:
NCONV=Vin/Vout=2N+2  (4)
i.e., the conversion ratio NCONVis mainly determined by the turn ratio N:1 of the transformer T. In particular, as may be noted from Eq. (4), the conversion ratio NCONVpresents an additional coefficient equal to 2; this means that the transformer T can be sized with a transformation ratio decreased by 1.

For instance, for an LLC electronic converter, the conversion ratio NCONVcorresponds to 2 N. Consequently, assuming a number of turns on the secondary equal to 4, such an LLC converter would require 8 turns on the primary to achieve a conversion ratio NCONVof 4:1. Instead, with the solution proposed, the same conversion ratio NCONVcan be obtained with a number of turns on the primary reduced to 4.

As mentioned previously, one or more of the switches Q1, . . . , Q8may be FETs, such as MOSFETs.

For instance,FIG. 5shows an embodiment in which the switches Q1, . . . , Q4are n-channel FETs, such as MOSFETs. In this case, a drain terminal of the transistor Q1is connected to the terminal200a, a source terminal of the transistor Q1is connected to a drain terminal of the transistor Q2, a source terminal of the transistor Q2is connected to a drain terminal of the transistor Q3, a source terminal of the transistor Q3is connected to a drain terminal of the transistor Q4, and a source terminal of the transistor Q4is connected to the terminal200b.

In the embodiment considered, also the rectifier circuit R is implemented with four n-channel FETs. In this case, a drain terminal of the transistor Q7is connected to the terminal202a, a source terminal of the transistor Q7is connected to a drain terminal of the transistor Q8, and a source terminal of the transistor Q8is connected to the terminal202b. Likewise, a drain terminal of the transistor Q5is connected to the terminal202a, a source terminal of the transistor Q5is connected to a drain terminal of the transistor Q6, and a source terminal of the transistor Q6is connected to the terminal202b.

FIG. 5shows also the fact that the switches Q5, . . . , Q7may comprise or consist of diodes. For instance,FIG. 5also shows the body diodes of the transistors Q1, . . . , Q8, and these body diodes (with their cathode connected to the drain terminal and their anode connected to the source terminal) of the transistors Q5, . . . , Q8implement a diode-bridge rectifier. In any case, using transistors for these switches, the electrical losses caused by these switches can be reduced.

FIG. 6shows a second embodiment of an electronic converter20a. In particular, as described previously, the switches Q3/Q4and also the switches Q7/Q8, are both connected between the terminals202aand202band are driven in a synchronous way. It is thus possible to join the switching nodes of these two half-bridges and use just one half-bridge.

Consequently, in the embodiment considered, the switches Q7/Q8have been removed as compared to what is illustrated inFIG. 2. Hence, a terminal of the secondary winding T2remains connected to the intermediate point between the switches Q5and Q6. Instead, the second terminal of the secondary winding T2is no longer connected to the switches Q7/Q8, but is now connected to the intermediate point between the switches Q3(which is now denoted by the reference Q3_Q7) and Q4(which is now denoted by the reference Q4_Q8), i.e., the node PH2.

The advantage of this structure is that the construction of the transformer T could benefit from a simplification. In fact, just three terminals are required, and in practice the resulting structure of the transformer T is that of an auto-transformer. However, the current circulating in the pair of switches Q3_Q7and Q4_Q8is now equal to IPRI+ISEC, i.e., (N+1)·IPRI, which should be taken into consideration during sizing of the switches.

The inventor has noted that the structure proposed may also be generalised to obtain different gains using one and the same transformer T. In fact, this makes it possible to avoid sizing and customising of the transformer T for each type of converter. Using the same transformer T for different conversion ratios NCONVit is possible to have different conversion ratios by modifying just some connections of the topology presented.

In particular, as shown inFIG. 8, and as compared toFIG. 6, the following modifications have been made, which can also be used individually:the transformer T is a center-tapped transformer, which thus comprises a first secondary winding T2aand a second secondary winding T2bconnected in series;a first switch S1(ninth electronic switch) has been added, which makes it possible to set the voltage on the node SN at a first reference voltage, and consequently the voltage that is applied to the node PH1(Vinor the voltage on the node SN on the basis of switching of the switches Q1and Q2); anda second switch S2(tenth electronic switch) has been added, which makes it possible to connect the node PH2to the intermediate point between the switches Q3/Q3_Q7and Q4/Q4_Q8, or to a second reference voltage CM.

In general, the switches S1and/or S2may be implemented with:one or more electronic switches, and/ora mechanical connection, for example by providing metal slots on a printed circuit and fixing (for example, soldering) a jumper, such as a 0-Ω resistor, between two metal slots.

Basically, the center-tapped transformer makes it possible to obtain on the intermediate node of the secondary winding T2(between the windings T2aand T2b) an output voltage Vout2that corresponds to one half of the output voltage Vout, i.e., Vout2=Vout/2.

In particular, the switches Q5and Q6are again connected between the terminals202aand202b, where the terminal202bis connected to the terminal200bthat represents a reference voltage, for example, ground GND. Moreover, the switches Q3_Q7and Q4_Q8are again connected between the terminals202aand202b. In addition, the secondary winding T2(which comprises the windings T2aand T2b) is connected between the intermediate point between the switches Q5/Q6and the intermediate point between the switches Q3_Q7/Q4_Q8.

In the embodiment considered, the electronic converter comprises a further output terminal202c, which is connected (for example, directly) to the intermediate node between the windings T2aand T2b. Consequently, the voltage Vout2between the terminals202cand202bcorresponds to one half of the voltage Voutbetween the terminals202aand202b.

In the embodiment considered, the switches Q1and Q2are once again connected in series between the terminal200aand the node SN. Moreover, the capacitor CRESand the inductor LRESare connected in series to the primary winding T1between the node PH1(intermediate node between the switches Q1and Q2) and the node PH2.

As explained previously, the switch S1makes it possible to set the voltage on the node SN to a reference voltage. For instance, in the embodiment considered, the switch S1is configured for connecting the node SN:to the terminal202a(which corresponds to the embodiment illustrated inFIG. 6); orto the terminal200b(ground); oroptionally to the terminal202c.

Instead, the switch S2is configured for connecting the terminal of the primary winding T1/node PH2:to the intermediate point (now designated by the reference SEC) between the switches Q3_Q7and Q4_Q8(which corresponds to the embodiment illustrated inFIG. 6), orto a second reference voltage CM.

In general, the reference voltage CM corresponds to a non-switching common-mode voltage, such as GND, Vout, or Vout2. Consequently, in various embodiments considered, the switch S1is configured for enabling connection of the node PH2to the node200a,200b, or200c.

Hence, when the node SN is connected (e.g., via the switch S1) to the terminal202a, and the node PH2is connected (e.g., via the switch S2) to the intermediate point SEC between the switches Q3_Q7and Q4_Q8, the converter20apresents the configuration illustrated inFIG. 6. Instead, when the node SN is connected (e.g., via the switch S1) to the terminal200b, and the node PH2is connected (e.g., via the switch S2) to the voltage CM, for instance to the terminal200b, the converter20apresents the configuration of a traditional LLC converter, in which the secondary winding T2may even be isolated from the primary winding T1.

However, other configurations with different conversion ratios NCONVmay also be implemented. In particular, it is possible to define two conversion-ratio tables Vin/Voutand Vin/Vout2according to the connection of the switches S1and S2:

Hence, the converter ofFIG. 8makes it possible to obtain the same conversion ratio using different transformation ratios (N) of the transformer. The optimal transformation ratio may be obtained as a function of the characteristics of the conversion. For instance, it may be useful to minimise the total number of windings in order to reduce the resistance of the windings themselves. Other considerations may be made, such as the maximum value of drain-to-source voltage VDSpresent on the MOSFETs. In this case, the transformation ratio may be sized to have a maximum value VDSwithin certain pre-set limits.

For instance, if the aim were to obtain a conversion ratio equal to 5 for the voltage Vout, the minimum transformation ratio N would be 1.5 if the configuration S1=Voutand S2=SEC is adopted. Considering that the minimum number of turns on the secondary of the center-tapped transformer T is equal to 1+1, the primary winding T1should have 3 turns. If, instead, the output VOUT2is used to have a conversion ratio equal to 5, once again considering a number of turns on the secondary equal to 1+1, the minimum transformation ratio N is 1 if the configuration S1=Vout2and S2=CM is used. The second option is thus more interesting from the standpoint of the number of turns of the transformer but calls for transistors Q3_Q7, Q4_Q8, Q5, and Q6with twice the voltage BVDSS(Drain-to-Source Breakdown Voltage) as compared to the first solution.