Memory hub with integrated non-volatile memory

A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for receiving memory access requests, a non-volatile memory having memory configuration information stored therein, and a memory controller coupled to the high-speed interface and the non-volatile memory. The memory controller includes registers into which the memory configuration information is loaded and is operable to output memory requests in response to receiving memory access requests from the high-speed interface and in accordance with the memory configuration information loaded in the registers. A method for initializing a memory sub-system is also provided. The method includes loading configuration registers of a plurality of memory hubs with the configuration information provided by a respective one of a plurality of embedded non-volatile memories integrated in the respective memory hub.

TECHNICAL FIELD

The present invention relates to memory systems, and more particularly, to memory modules having a memory hub and an integrated non-volatile memory for storing module specific information.

BACKGROUND OF THE INVENTION

Conventional computer systems include system memory, which is typically used to store information, such as instructions of a software application to be executed by a processor, as well as data that is processed by the processor. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.

Generally, the system memory of a computer system takes the form of one or more memory modules that includes several integrated circuit memory devices mounted on a printed circuit board. Examples of the types of memory devices include asynchronous dynamic random access memories (“DRAMs”) and synchronous DRAMs (“SDRAMs”). Typically, the memory modules are removably plugged into connectors located on a motherboard of the computer system. The size of the computer system's memory can be increased by plugging additional memory modules into the motherboard. Memory modules are commercially available in standardized configurations, such as a single in-line memory module (“SIMM”) and a double in-line memory module (“DIMM”), which match the connectors. The memory modules are electrically coupled to the memory controller, processor, and other devices also mounted on the mother-board using standardized memory interfaces, as well known. These standardized memory interfaces generally include a data bus, an address bus, and a control/status bus.

Often included on the printed circuit board of a memory module is a non-volatile memory in which module specific information, such as timing information, memory type, and manufacturing information, is stored. The non-volatile memory of each module can be coupled to the memory controller on the mother board through a serial bus and the connector in which the memory module is inserted. The module specific information stored in the non-volatile memory is accessed by the computer system at start-up to initialize the memory controller so that it can communicate with the memory devices of the memory module. Additionally, the basic input/output system (BIOS) or operating system of the computer system may further access the module specific information through the serial bus in performing various tasks.

A memory system that has been developed as an approach to increasing system memory bandwidth employs multiple memory devices coupled to the processor through a “memory hub.” In a memory hub architecture, or a hub-based memory sub-system, a system controller or memory controller is coupled over a high speed data link to several memory modules. Typically, the memory modules are coupled in a point-to-point or daisy chain architecture such that the memory modules are connected one to another in series. Each memory module includes a memory hub that is coupled to the corresponding high speed data links and a number of memory devices on the module, with the memory hubs efficiently routing memory requests and responses between the controller and the memory devices over the high speed data links.

A non-volatile memory is still included on the memory module for providing module specific information to the system controller of the host computer system, in the same manner as the memory module for the standard system memory configuration previously discussed. That is, the system controller is coupled through a serial bus and module connector to the non-volatile memory in order to read the module specific information as part of initializing the computer system. With the addition of a memory hub to the memory module, a printed circuit board having more space is required. However, in some applications, such as in hand-held computing devices or portable computers, space allocated to memory modules is at a premium, and consequently, increasing the size of the printed circuit board to accommodate the additional components is undesirable. Additionally, the time for completing initialization of the computer system upon power up will be limited by the speed at which the non-volatile memory of each of the memory modules in a system memory can be accessed and the information transferred to the system controller over the serial bus. In applications where the demand for processing capability is immediate, minimizing the time for initializing the computer system is desirable.

SUMMARY OF THE INVENTION

In one aspect of the present invention, a memory hub having an integrated non-volatile memory for storing configuration information is provided. The configuration information can be copied directly from the non-volatile memory into storage registers in the memory hub. The memory hub for a hub-based memory sub-system includes a high-speed interface for receiving memory access requests, a non-volatile memory having memory configuration information stored therein, and a memory controller coupled to the high-speed interface and the non-volatile memory. The memory controller includes registers into which the memory configuration information is loaded and is operable to output memory requests in response to receiving memory access requests from the high-speed interface and in accordance with the memory configuration information loaded in the registers. In another aspect of the present invention, a method for initializing a memory sub-system is provided. The method includes loading configuration registers of a plurality of memory hubs with the configuration information provided by a respective one of a plurality of embedded non-volatile memories integrated in the respective memory hub.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention are directed to a memory hub coupled to a non-volatile memory for access to information that can be copied directly from the non-volatile memory into storage registers in the memory hub. In embodiments having the non-volatile memory integrated with the memory hub, initialization time when powering on a host system can be reduced since the module specific information can be copied directly to configuration registers in the memory hub. Moreover, having the module specific information copied directly to the configuration registers in the memory hub allows for a host system to interface with the system memory without the need to accommodate any specific characteristics of the system memory, thus, providing a more controlled environment to which the host system may interface. Certain details are set forth below to provide a sufficient understanding of various embodiments of the invention. However, it will be clear to one skilled in the art that the invention may be practiced without these particular details. In other instances, well-known circuits, control signals, and timing protocols have not been shown in detail in order to avoid unnecessarily obscuring the invention.

FIG. 1illustrates a computer system100according to one embodiment of the present invention. The computer system100includes a processor104for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor104includes a processor bus106that normally includes an address bus, a control bus, and a data bus. A host bridge110is also coupled to the processor bus106. The host bridge110is also coupled through an input/output (I/O) bus118to an I/O channel120through which one or more input and output devices can be coupled. Examples of the I/O bus118would be the PCI or ISA bus standards. Some common devices that would be coupled to the I/O channel120would be network interface cards, modems or bus adapter cards for SCSI or Fibre Channel device support. A peripheral control124is coupled to the I/O bus118. Examples of peripheral control124devices in personal computer chipsets would be the south bridge or the I/O controller hub. The peripheral control124block would generally support many of the standard I/O interface functions in the system (which are not shown in the diagram) such as keyboard and mouse, which allow an operator to interface with the computer system100. Plus common output devices such as a printer, coupled to the processor104to store data or retrieve data from internal or external storage media (not shown). Examples of typical storage devices include hard and floppy disks, tape casssettes, and compact disk read-only memories (CD-ROMs). Peripheral control124would also typically be the controller or bus master for a relatively slow serial bus such as Inter-IC (I2C) or System Management Bus (SMBus) that is used by the system for housekeeping tasks such as capabilities reporting, configuration and health monitoring. The previously described components generally define a host system101. The elements of the host system101are conventional, and can be implemented using designs and circuitry known by those ordinarily skilled in the art.

A system memory132is coupled to the host system101, more specifically, the host bridge110, through a high-speed bus134. The system memory132is represented inFIG. 1by a memory hub based memory system that includes one or more memory modules, each of which includes a memory hub (not shown). As will be explained in more detail below, a memory hub controls access to memory devices of the memory module on which the memory hub is located. The high-speed bus134can be a bi-directional bus that couples together the memory hubs of the memory modules in various configurations. For example, the high-speed bus134can couple the memory modules together in a point-to-point configuration where information on the high-speed bus134must travel through the memory hubs of “upstream” memory modules to reach a “downstream” destination. It will be appreciated, however, that a high-speed link134providing topologies other than the point-to-point arrangement may also be used. For example, a high-speed link134providing a coupling arrangement in which a separate high-speed bus (not shown) is used to couple each of the memory modules of the system memory132to the host bridge110may also be used. A switching topology may also be used in which the host bridge110is selectively coupled to each of memory module of the system memory132through a switch (not shown). Other topologies that may be used will be apparent to one skilled in the art.

Additionally, the high-speed link134coupling the memory modules to the memory hub controller may be an electrical or optical communication path. However, other types of communications paths can be used for the high-speed link134as well. In the event the high-speed link134is implemented as an optical communication path, the optical communication path may be in the form of one or more optical fibers. In such case, the host bridge110and the memory modules of the system memory132will include an optical input/output port or separate input and output ports coupled to the optical communication path, as well known in the art.

The system memory132is also coupled to the peripheral control124through system serial busses136. As shown inFIG. 1, the system memory132is coupled to the peripheral control124through a serial bus clock line and a serial bus data line, such as an Inter-IC (I2C) bus or a System Management Bus (SMBus), which are well known in the art. As will be explained in greater detail below, the system serial busses136can be used by the host system to access information from the system memory132, such as system memory configuration information, as well known in the art.

FIG. 2illustrates a computer system200according to another embodiment of the present invention. The computer system200includes a host system201that includes the same components as the host system101(FIG. 1). Consequently, each of the components will not be described again in detail in the interest of brevity. However, in the computer system200, the system memory132is coupled to the processor104through the high-speed bus134. In contrast, in the computer system100, the system memory132is coupled to the host bridge110through the high-speed bus134. The architecture of the computer system200may be preferable where immediate access to the system memory132by the processor is desirable, such as for computer systems designed for data intensive processing applications.

FIG. 3shows a partial block diagram of a memory module300according to an embodiment of the present invention. The memory module300can be used in the system memory132(FIG. 1). The memory module300includes a memory hub140coupled to several memory devices240a–240ithrough a memory device bus system150. The memory device bus system150normally includes a control bus, an address bus, and a data bus, as known in the art. However, it will be appreciated by those ordinarily skilled in the art that other memory device bus systems, such as a bus system using a shared command/address bus, may also be used without departing from the scope of the present invention. InFIG. 3, the memory devices240a–240iare illustrated as synchronous dynamic random access memory (“SDRAM”) devices. However, memory devices other than SDRAM devices may also be used. It will be further appreciated that the arrangement of the memory devices240a–240i, and the number of memory devices can be modified without departing from the scope of the present invention.

As previously mentioned, the memory hub140controls access to memory devices240a–240iof the memory module300. Thus, memory requests and responses between the host system and the memory devices240a–240ican be efficiently routed by the memory hub140over the high-speed bus134. It will be appreciated that the system memory132will typically include multiple memory modules, each having its own memory hub140, which are coupled together by the high-speed bus134. Computer systems employing this architecture can have a higher bandwidth because a host system can leverage the memory hubs140of the system memory132to access a memory device on one memory module while a memory device on another memory module is responding to a prior memory access. For example, the host system can output write data to one of the memory devices in the system memory132while another memory device in the system memory132is preparing to provide read data to the processor. Moreover, this architecture also provides for easy expansion of the system memory without concern for degradation in signal quality as more memory modules are added.

FIG. 4illustrates a partial block diagram of a memory hub400according to an embodiment of the present invention. The memory hub400can be substituted for the memory hub140(FIG. 3). The memory hub400includes a memory controller402coupled to a high-speed interface404through a memory hub bus410. The high-speed interface404is coupled to the high-speed bus134in order for the memory controller402to communicate with the host system. The memory hub bus410can be implemented using conventional designs well known in the art. For example, the memory hub bus410can include a bus having bi-directional signal lines for receiving and transmitting signals between the memory controller402and the high-speed interface404.

The high-speed interface404is conventional, and includes conventional circuitry used for transferring data, command, and address information through the high-speed bus134. As well known, such circuitry includes transmitter and receiver logic known in the art. It will be appreciated that those ordinarily skilled in the art have sufficient understanding to modify the high-speed interface404to be used with specific types of communication paths, and that such modifications to the high-speed interface404can be made without departing from the scope of the present invention. For example, in the event the high-speed bus134to which the high-speed interface404is coupled is implemented using an optical communications path, the high-speed interface404will include an optical input/output port that can convert optical signals into electrical signals for operation of the memory hub400.

The memory controller402is coupled to the memory device bus150(FIG. 3). The memory controller402performs the same functions as a conventional memory controller by providing control and address signals to the memory devices240a–240icoupled to the memory device bus150, and provides data signals to and receives data signals from the memory devices240a–240ias well. However, the nature of the signals sent and received by the memory controller402will correspond to the nature of the signals that the memory devices240a–240icoupled to the memory device bus150are adapted to send and receive. That is, the memory controller402is specially adapted to the memory devices240a–240ito which the memory controller402is coupled. More specifically, the memory controller402is specially adapted to provide and receive the specific signals received and generated, respectively, by the memory device240a–240ito which it is coupled. In an alternative embodiment, the memory controller402is capable of operating with memory devices240a–240ioperating at different clock frequencies. As a result, the memory controller402can isolate the processor104from changes that may occur at the interface between the memory hub400and memory devices240a–240icoupled to the memory device bus150, and consequently, provide a more controlled environment to which the memory devices240a–240imay interface.

Configuration registers403are included in the memory controller402. As will be explained in more detail below, the configuration registers403are typically loaded with module specific information upon power up. The module specific information can then be used by the memory controller402for initialization so that it can communicate most effectively with the memory devices of the memory module on which the memory hub400is located.

The memory hub400also includes a non-volatile memory406coupled to the memory controller402through a first configuration path412and further coupled to the high-speed interface404through a second configuration path414. As will be explained in more detail below, the non-volatile memory406is used to store module specific information that is used by the memory controller402during initialization. The non-volatile memory406can be implemented using conventional non-volatile memory, such as FLASH memory or other types of electrically erasable programmable read-only memory (EEPROM). The non-volatile memory406is preferably embedded memory formed as part of the memory hub400, and can be of a relatively small capacity, such as 256 Kbits or 512 Kbits. However, other types of non-volatile memory, and different capacities can be used as well without departing from the scope of the present invention.

The memory controller402, high-speed interface404, and non-volatile memory406are also coupled to a local system serial bus420. The local system serial bus420can be coupled to a host system through a system serial bus, such as the system serial bus136shown inFIGS. 1 and 2. The non-volatile memory406is used to store information specific to the memory module on which the memory hub400is located. Examples of the module specific information includes timing information for the memory devices of the memory module, memory module configuration data, memory device type, manufacturer data, and the like.

As previously mentioned, in conventional memory modules, the module specific information is typically accessed by a host system upon start-up to properly initialize the host memory controller so that it can communicate most effectively with the memory devices of the memory module. In contrast, however, the non-volatile memory406is integrated with the memory hub400so that the module specific information can be accessed and copied directly from the non-volatile memory406to appropriate configuration registers403in the memory controller402when the host system is powered on. In embodiments having the non-volatile memory406integrated with the memory hub400, and having the module specific information copied directly to the configuration registers403, initialization time when powering on a host system can be reduced. Moreover, having the module specific information copied directly to the configuration registers403of the memory hub400allows for a host system to interface with the memory module without the need for the host system to accommodate any specific characteristics of the memory module or the memory devices on the memory module. Thus, the host system can interact with a system memory generically, relying on the memory hub400to manage the specifics of the memory module.

The non-volatile memory406can also store module specific information used by a host system as well, such as memory module capacity, memory module clock speed, and the like. Such information is often used by the basic input/output system (BIOS), the operating system, or application software in performing various tasks. For module specific information that should be provided to the host system in which the memory module is located, the information can be provided through the high-speed interface404to the host system via the configuration path414and the high-speed bus134. Alternatively, in embodiments of the present invention having the local system serial bus420, the module specific information can be provided though a system serial bus that is coupled to the local system serial bus420.