Grid array pattern for crosstalk reduction

A printed circuit board (PCB) assembly may include a component capable of sending or receiving high-speed differential signal pairs, a package that is connected to the component, and a PCB connected to the package. The PCB assembly may be used to support a first high-speed differential signal pair that includes a first differential signal and a second differential signal. The first differential signal may be capable of causing crosstalk onto a particular differential signal, of a second high-speed differential signal pair, while propagating through the PCB assembly. A set of interconnects may be used to intelligently route the first differential signal pair within the package and/or within the PCB. The set of interconnects may include a first interconnect to route the first differential signal away from the particular differential signal and a second interconnect to route the second differential signal toward the particular differential signal.

BACKGROUND

A printed circuit board (PCB) assembly may include one or more components to facilitate transmitter and receiver signal routing for high speed data connections. For example, the PCB assembly may include a PCB, a grid array (GA) package, and an integrated circuit, wherein the high-speed signals travel to and from the integrated circuit by traveling through the PCB and the GA package. Additionally, high speed signals may carry information at rates of 25 Gigabits per second (Gbps) or greater, which may cause significant signal integrity disturbances as a result of reflection, cross-talk, and ground bounce. The signal integrity disturbances may result in reduced network performance.

SUMMARY

According to some possible implementations, a printed circuit board (PCB) may include a set of pads associated with facilitating a connection through a package and to a component. The set of pads may include a set of via pads and a set of grid array (GA) pads. The PCB may include a set of vias electrically connected to the set of via pads and to a set of layers that may be perpendicular to the set of vias. The set of vias may be used to support high-speed differential signal pairs and may be connected to one or more non-ground layers of the set of layers. The high-speed differential signal pairs may include a first high-speed differential signal pair. The first high-speed differential signal pair may include a first differential signal and a second differential signal. The first differential signal may be capable of causing crosstalk onto a particular differential signal, of a second high-speed differential signal pair, while propagating through the package. The PCB may include a set of interconnects that electrically connect the set of via pads to the set of GA pads. The set of interconnects may include a first interconnect to route the first differential signal away from the particular differential signal of the second high-speed differential signal pair, and a second interconnect to route the second differential signal toward the particular differential signal. The routed second differential signal may be capable of causing an amount of crosstalk onto the particular differential signal that is proportional to an amount of crosstalk that the first differential signal is capable of causing within the package.

According to some possible implementations, a printed circuit board (PCB) assembly may include a component capable of sending or receiving high-speed differential signal pairs, a package that is connected to the component, and a PCB connected to the package. A set of pads may be connected to the package or to the PCB to facilitate a connection between the PCB and the component. The set of pads may include a set of package via pads, a set of package grid array (GA) pads, a set of PCB via pads, and a set of PCB GA pads. The set of package via pads may be connected to a set of package vias and the set of PCB pads may be connected to a set of PCB vias. The set of package vias and the set of PCB vias may to be used to support high-speed differential signal pairs that include a first high-speed differential signal pair. The first high-speed differential signal pair may include a first differential signal and a second differential signal. The first differential signal may be capable of causing crosstalk onto a particular differential signal, of a second high-speed differential signal pair, while propagating through a particular package via, of the set of package vias. A set of interconnects may be used to connect package pads to package GA pads or may be used to connect PCB pads to PCB GA pads. The set of interconnects may include a first interconnect to route the first differential signal away from the particular differential signal, and may include a second interconnect to route the second differential signal toward the particular differential signal.

According to some possible implementations, a package may include a set of pads associated with facilitating a connection between a printed circuit board (PCB) and one or more components. The set of pads may include a set of via pads and a set of grid array (GA) pads. A set of vias may be electrically connected to the set of via pads and to a set of layers that are perpendicular to the set of vias. The set of vias may be used to support high-speed differential signal pairs and may be connected to one or more non-ground layers of the set of layers. The high-speed differential signal pairs may include a first high-speed differential signal pair that includes a first differential signal and a second differential signal. The first differential signal may be capable of causing crosstalk onto a particular differential signal, of a second high-speed differential signal pair, while propagating through a particular via, of the set of vias. A set of interconnects may electrically connect the set of via pads to the set of GA pads. The set of interconnects may include a first interconnect to route the first differential signal away from the particular differential signal, and a second interconnect to route the second differential signal toward the particular differential signal. The first interconnect may traverse through a non-ground layer and the second interconnect may traverse through a different non-ground layer.

DETAILED DESCRIPTION

A printed circuit board (PCB) assembly may include one or more components to facilitate transmitter and receiver signal routing for high speed data connections. For example, the PCB assembly may include a PCB, a package, and an integrated circuit, wherein high-speed signals travel to and from the integrated circuit by traveling through the PCB and the package. The package may include a grid array (GA), such as a ball grid array (BGA), which is an array of solder balls that are used to conduct electrical signals between the integrated circuit and the PCB on which the integrated circuit is placed.

The PCB may include one or more material layers that mechanically support and electrically connect electronic components using conductive pathways. The conductive pathways may be etched from copper sheets laminated onto a non-conductive substrate. The pathways may be organized as a number of layers on the PCB in order to increase the signal transmission density of the PCB.

PCBs may be used in high frequency applications. For example, a PCB may be populated with an integrated circuit used to enable high speed serial links (e.g., speeds at or above 56 gigabytes per second (Gbps))) to and from the PCB, as may be utilized for an Ethernet switch, a serializer/deserializer (SerDes), and/or the like. In this case, use of higher speed serial links may cause a significant increase in signal integrity disturbances, such as crosstalk. One type of crosstalk, far end crosstalk (FEXT), may occur when a first signal (referred to as a crosstalk aggressor signal) causes crosstalk onto a second signal (referred to as a crosstalk victim signal), wherein the signal propagation of the crosstalk aggressor signal and the crosstalk victim signal are traveling in the same direction.

In some cases, differential signaling may be used in a high speed application. For example, a differential signal pair may include two complimentary signals (e.g. a positive signal and a negative signal), and the two complimentary signals may be routed through the PCB assembly. Additionally, the differential signal pair may cause FEXT on a neighboring signal (e.g., a signal traveling within a threshold distance of the differential signal pair), in which case one of the differential signals may be a crosstalk aggressor signal and the neighboring signal may be a crosstalk victim signal.

Additionally, FEXT may be reduced by separating a distance between the crosstalk aggressor signal and the crosstalk victim signal using one or more ground vias (i.e., vias that are connected to a ground layer). For example, by adding a ground via between vias that support the crosstalk aggressor signal and the crosstalk victim signal, the signals may be far enough apart to reduce or eliminate FEXT.

However, as speeds of the serial links increase, the amount of FEXT between a crosstalk aggressor signal and a crosstalk victim signal may correspondingly increase. In this case, the distance between the crosstalk aggressor signal and the crosstalk victim signal may need to be increased to offset the increase in FEXT. One solution is to increase the number of ground vias between the vias that support the signals. Increasing the number of ground vias on the PCB reduces a number of vias available for sending and/or receiving signals, thereby reducing potential throughout of the PCB.

Some implementations described herein provide a GA space design pattern to be implemented on one or more parts of a PCB assembly to reduce or eliminate FEXT by enabling crosstalk (e.g., FEXT) cancellation. For example, a PCB assembly may include a PCB that is connected to a package, and the package may be connected to a component (e.g., an integrated circuit). In this case, the PCB assembly may be used to route high-speed differential signal pairs to and from the component.

As an example to illustrate routing through the PCB assembly, a first high-speed differential signal pair may be routed from a first part of the component (e.g., a transmitter part) to a second part of the component (e.g., a receiver part). In this example, a first differential signal of the first high-speed differential signal pair may be routed from the first part of the component, through a first package via (e.g., toward the PCB), through a GA space between the package and the PCB, through a first PCB via (e.g., toward a bottom portion of the PCB), through a non-ground layer of the PCB to a second PCB via, through the second PCB via of the PCB (e.g., toward a top portion of the PCB), through a second package via (e.g., toward the component), and may end at the second part of the component.

In some cases, the first differential signal of the first high-speed differential signal pair (referred to as a FEXT aggressor signal) may cause increasing amounts of FEXT onto a differential signal of a second high-speed differential signal pair (referred to as a FEXT victim signal). For example, the first high-speed differential signal pair may propagate through package vias at a same time and in a same direction as the second high-speed differential signal pair. Additionally, the package vias used to propagate the first differential signal pair and package vias used to propagate the second differential signal pair may be within close physical proximity of each other. As such, the FEXT aggressor signal may cause an increasing amount of FEXT onto the FEXT victim signal as the signals propagate through respective package vias.

To eliminate or reduce crosstalk such as FEXT, a GA space design pattern may be implemented on the package, on the PCB, or on a combination of the package and the PCB, to enable FEXT cancellation. For example, because the FEXT victim signal incurs an increasing amount of FEXT while propagating through the package via, a GA space design pattern may be used to cause a decreasing amount of FEXT in the PCB, such that the decrease in the amount of FEXT in the PCB offsets the increase in the amount of FEXT in the package, thereby reducing or eliminating FEXT via FEXT cancellation. As an example, the GA space design pattern may use a first interconnect to route the FEXT aggressor signal (i.e., the first differential signal of the first high-speed differential signal) away from the FEXT victim signal and may use a second interconnect to route a second differential signal, of the first high-speed differential signal, toward the FEXT victim signal. This may cause the second differential signal to become the FEXT aggressor signal during signal propagation within the PCB, and allows for FEXT cancellation because the second high-speed differential signal has a polarity that is opposite to that of the first high-speed differential signal.

Additionally, to achieve FEXT cancellation between FEXT within the package and FEXT within the PCB, the GA space design pattern may need to delay match the first high-speed differential signal pair. The first high-speed differential signal pair may be delay matched when the first differential signal propagates at a same rate as the second differential signal, such that the two differential signals travel from a first location to a second location in approximately the same time period. To delay match the first high-speed differential signal pair, the GA space design may design the first interconnect and the second interconnect to be of lengths that ensure delay matching, where the lengths may be based on differences in package via length versus PCB via length, differences in package via diameter versus PCB via diameter, differences in velocity of propagation of signals within different layers of the package and/or PCB, and/or the like.

In this way, the GA space design pattern enables FEXT cancellation to reduce or eliminate FEXT. Additionally, the GA space design pattern improves cross-sectional bandwidth of the PCB and/or the package, increases signal density, and/or improves throughput of the PCB assembly by reducing a number of ground vias that need to be placed between vias that support actual traffic to and from the component.

FIGS. 1A-1Care diagrams of an overview of a grid array (GA) GA design pattern implemented on an example apparatus100described herein.FIGS. 1A-1Cshow GA space design pattern that enables FEXT cancellation (e.g., partial FEXT cancellation, complete FEXT cancellation, etc.).

As shown inFIG. 1A, the GA space design pattern may be implemented on a printed circuit board (PCB) that is part of a PCB assembly. As shown inFIG. 1B, the GA space design pattern may be implemented on a package that is part of the PCB assembly. As shown inFIG. 1C, the GA space design pattern may be implemented on a combination of the PCB and the package.

As shown inFIG. 1A, the PCB assembly may include a package with a set of package vias (shown as package via102, package via104, package via106, and package via108) that are attached to a set of package via pads (shown as package via pad110, package via pad112, package via pad114, and package via pad116). Furthermore, the package may include a set of package grid array (GA) pads (shown as package GA pad118, package GA pad120, package GA pad122, and package GA pad124), such as package ball grid array (BGA) pads that are attached to a set of solder balls that are used to connect the package to a PCB.

Additionally, the PCB may include a set of PCB GA pads (shown as PCB GA pad126, PCB GA pad128, PCB GA pad130, and PCB GA pad132), such as a set of PCB BGA pads. Furthermore, the PCB may include a set of PCB via pads (shown as PCB via pad134, PCB via pad136, PCB via pad138, and PCB via pad140) that are attached to a set of PCB vias (shown as PCB via142, PCB via144, PCB via146, and PCB via148).

Additionally, the PCB assembly may be used to route high-speed differential signal pairs to and from a component. In some cases, high-speed differential signal pairs may serve as FEXT aggressor signal pairs and may cause crosstalk, such as FEXT, onto a differential signal of another high-speed differential signal pair.

As shown as an example, FEXT aggressor signal pair150may include a first FEXT aggressor signal with a negative polarity (N1) and a second FEXT aggressor signal with a positive polarity (P1). To illustrate signal propagation of the FEXT aggressor signal pair, the first FEXT aggressor signal (N1) may propagate through package via106, through package via pad114, through package GA pad122, through a solder ball connected to package GA pad122, through PCB GA pad130, through interconnect154(via laser microvia156), through PCB via pad140, and through PCB via148. Additionally, the second FEXT aggressor signal (P1) may propagate through package via108, through package via pad116, through package GA pad124, through a solder ball connected to package GA pad124, through PCB GA pad132, through interconnect152, through PCB via pad138, and through PCB via146.

As shown, interconnect152and interconnect154may be designed in a manner that enables FEXT cancellation. For example, even if the first FEXT aggressor signal (N1) causes increased amounts of FEXT onto the FEXT victim signal (P0) while propagating through package via106, interconnect154may be designed to route the first FEXT aggressor signal (N1) away from the FEXT victim signal (P0), and interconnect152may be designed to route the second FEXT aggressor signal (P1) toward the FEXT victim signal. In this case, interconnect154may route the first FEXT aggressor signal to PCB via148, and interconnect152may route the second FEXT aggressor signal to PCB via146, thereby enabling the second FEXT aggressor signal (P1) to cause a decreasing amount of FEXT onto the FEXT victim signal (P0) while propagating through PCB via146.

Additionally, interconnect152and interconnect154may be designed to connect PCB GA pads to PCB via pads at different layers of the PCB. For example, the PCB may include a set of layers that are perpendicular to the set of PCB vias. In this case, interconnect152and interconnect154may be designed to connect PCB GA pads to PCB via pads at different layers to avoid causing a short circuit. This is illustrated by interconnect152connecting PCB GA pad132to PCB via pad138at a first layer (e.g., layer 1 of the PCB) and by interconnect154connecting PCB GA pad130to PCB via pad140at another layer (e.g., layer 3 of the PCB). Additionally, to connect interconnect154from PCB GA pad130to PCB via pad140through the other layer, interconnect154may have to traverse through one or more microvias (shown as laser microvia156). In this way, interconnect152and interconnect154enable FEXT cancellation without risk of FEXT aggressor signal pair150causing a short circuit.

In some implementations, to ensure that an accurate amount of FEXT cancellation occurs, the GA space design pattern may include lengths for interconnect152and/or interconnect154that ensure that the FEXT aggressor signals are delay matched. For example, assume a time needed for the FEXT aggressor signals to propagate through package vias is equal to a time needed for the FEXT aggressor signals to propagate through PCB vias. In this case, a length of interconnect152and a length of interconnect154may ensure proper delay matching by being equal.

In some cases, the GA space design pattern may include lengths for interconnect152and/or interconnect154that are based on a number of different factors that influence delay matching. For example, the GA space design pattern may include lengths of interconnect152and interconnect154that offset a difference in a total distance that the first FEXT aggressor signal (N1) and the second FEXT aggressor signal (P1) propagate through the package in relation to a total distance that the first FEXT aggressor signal (N1) and the second FEXT aggressor signal (P1) propagate through the PCB.

As an example, assume PCB via146and PCB via148are longer than package via106and package via108. If interconnect152and interconnect154were of equal length, the second FEXT aggressor signal would travel through PCB via146for a longer distance than the first FEXT aggressor signal would travel through package via106. This would cause the decreases in FEXT from the second FEXT aggressor signal to exceed the FEXT increases caused by first FEXT aggressor signal (which may cause FEXT in an opposite direction). Instead, the GA space design pattern may include a length of interconnect152that is longer than a length of interconnect154, thereby ensuring that the FEXT aggressor signal pair is delay matched.

Additionally, or alternatively, the GA space design pattern may include lengths of interconnect152and interconnect154that offset a difference between package via diameter and PCB via diameter. For example, if package vias and PCB vias have different diameters, FEXT aggressor signals traveling through the package vias and the PCB vias may have different velocity of propagation speeds. As an example, if package vias have larger diameters than PCB vias, and interconnect152and interconnect154are of equal length, the FEXT aggressor signal pairs may not delay match. Instead, either interconnect152or interconnect154may be designed to be longer than the other to offset a difference between package via diameter and PCB via diameter.

Additionally, or alternatively, the GA space design pattern may include lengths of interconnect152and interconnect154that offset a difference in a velocity of propagation of FEXT aggressor signals while propagating through interconnect152and interconnect154. For example, different layers of the PCB may use different transmission lines (e.g., microstrip, stripline, and/or the like) that have different velocities of propagation. Because interconnect152and interconnect154are located at different layers to prevent a short circuit, the differential signals propagating through interconnect152and interconnect154may propagate at different velocities. To offset this, the GA space design pattern may include interconnect152and interconnect154such that an interconnect located at a layer with a faster velocity of propagation is longer than an interconnect located at a layer with a slower velocity of propagation.

In some implementations, the PCB assembly may be designed with one or more ground vias between the FEXT aggressor signal pair and the FEXT victim signal. For example, depending on a differential signal speed (e.g., 112 gigabytes per second (Gbps), 224 Gbps, etc.), ground vias may need to be implemented in addition to the above-described GA space design pattern to ensure that FEXT is reduced or eliminated. However, it is to be noted that a number of ground vias that would be used in conjunction with the GA space design pattern will always be less than a number of ground vias that would be used if the GA space design pattern was not implemented, thereby improving cross-sectional bandwidth of the PCB and/or the package relative to a conventional architecture of a PCB assembly (e.g., that does not utilize the GA space design pattern).

By designing interconnect154to route the first FEXT aggressor signal away from the FEXT victim signal, by designing interconnect152to route the second FEXT aggressor signal toward the FEXT victim signal, and by designing interconnect152and interconnect154in a manner that delay matches the FEXT aggressor signals, the GA space design pattern is able to enable FEXT cancellation. Furthermore, enabling FEXT cancellation reduces a number of ground vias that need to be placed between vias that support actual traffic to and from the component, thereby improving cross-sectional bandwidth of the PCB and/or the package, increasing signal density, improving throughput of the PCB assembly, and/or the like.

As shown inFIG. 1B, the GA space design pattern may be implemented on the package. For example, rather than place interconnect152and interconnect154within the PCB (as shown inFIG. 1A), the GA space design pattern may be implemented on the package.

To illustrate signal propagation of the FEXT aggressor signal pair, the first FEXT aggressor signal (N1) may propagate through package via106, through package via pad114, through interconnect152, through package GA pad124(e.g., a package ball grid array (BGA) pad), through a solder ball connected to package GA pad124, through PCB GA pad132(e.g., a PCB BGA pad), through PCB via pad140, and through PCB via148. Additionally, the second FEXT aggressor signal (P1) may propagate through package via108, through package via pad116, through interconnect154(via laser microvia158and laser microvia156), through package GA pad122, through a solder ball that connects to package GA pad122, through PCB GA pad130, through PCB via pad138, and through PCB via146.

As shown, the GA space design pattern may include a structure for interconnect152and interconnect154that enables FEXT cancellation, in a same manner described above. Additionally, the GA space design pattern may include lengths for interconnect152and interconnect154that are based on a number of different factors that influence delay matching, as each described above.

In this way, the GA space design pattern may enable FEXT cancellation. Furthermore, enabling FEXT cancellation reduces a number of ground vias that need to be placed between vias that support actual traffic to and from the component, thereby improving cross-sectional bandwidth of the package and/or the PCB, increasing signal density, improving throughput of the PCB assembly, and/or the like.

As shown inFIG. 1C, the GA space design pattern may be implemented on a combination of the PCB and the package. For example, rather than place interconnect152and interconnect154on the PCB, or rather than place interconnect152and interconnect154on the package, the GA design pattern may be implemented to place either interconnect152or interconnect154on the PCB and either interconnect154or interconnect152on the package.

In some cases, as shown, interconnect152may be implemented on the package and interconnect154may be implemented on the PCB. To illustrate signal propagation of the FEXT aggressor signal pair, the first FEXT aggressor signal (N1) may propagate through package via106, through package via pad114, through package GA pad124(e.g., a package ball grid array (BGA) pad, through a solder ball connected to package GA pad124, through PCB GA pad132(e.g., a PCB BGA pad), through interconnect152, through PCB via pad140, and through PCB via148. Additionally, the second FEXT aggressor signal (P1) may propagate through package via108, through package via pad116, through interconnect154, through package GA pad122, through a solder ball connected to package GA pad122, through PCB GA pad130, through PCB via pad138, and through PCB via146. In other cases, interconnect152may be implemented on the PCB and interconnect154may be implemented on the package, and signal propagation may occur in a similar manner.

As shown, the GA space design pattern may include a structure for interconnect152and interconnect154that enables FEXT cancellation, in a similar manner as described above. Additionally, the GA space design pattern may include lengths for interconnect152and interconnect154that are based on a number of different factors that influence delay matching, as each described above.

In this way, the GA space design pattern may enable FEXT cancellation. Furthermore, enabling FEXT cancellation reduces a number of ground vias that need to be placed between vias that support actual traffic to and from the component, thereby improving cross-sectional bandwidth of the package and/or the PCB, increasing signal density, improving throughput of the PCB assembly, and/or the like.

As indicated above,FIGS. 1A-1Care provided merely as an example. Other examples are possible and may differ from what was described with regard toFIGS. 1A-1C. For example, there may be additional elements of apparatus100, fewer elements of apparatus100, different elements of apparatus100, or differently arranged elements of apparatus100than those shown inFIGS. 1A-1C. An element may be a via, a pad, a solder ball, a solder bump, and/or any other hardware included within the package and/or the PCB. Furthermore, two or more elements shown inFIGS. 1A-1Cmay be implemented within a single element, or a single element shown inFIGS. 1A-1Cmay be implemented as multiple, distributed elements. Additionally, or alternatively, elements of example apparatus100may perform one or more functions described as being performed by other elements of example apparatus100.

FIG. 2is a diagram of an example apparatus200that includes a component205, a set of component pads210, a set of solder bumps215, a package220, a set of package via pads225, a set of package grid array (GA) pads230(e.g., package ball grid array (BGA) pads, package land grid array (LGA) pads, and/or the like), a set of package vias235, a set of solder balls240, a set of PCB via pads245, a set of PCB GA pads250(e.g., PCB BGA pads, PCB LGA pads, and/or the like), a PCB255, a set of PCB vias260, a set of interconnects (e.g., interconnect265, interconnect270, interconnect,275, interconnect280, and/or the like), and/or the like.

In some implementations, component205may include a serializer/deserializer (SerDes) application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a bus, a power supply, an integrated circuit, an optical module, and/or the like.

In some implementations, package220may include a substrate (e.g., a non-conductive substrate) that includes mechanical support for component205. In some implementations, PCB255may include a substrate that includes mechanical support for package220. Additionally, or alternatively, package220and/or PCB255may include electrical connections for component205using, for example, component pads210, package via pads225, package GA pads230, package vias235, solder balls240, PCB via pads245, PCB GA pads250, and/or PCB vias260, conductive traces, and/or other features etched from laminated sheets (e.g., copper sheets or sheets made from another conductive material).

In some implementations, package220may include multiple layers, and conductors on different layers may be connected with package vias235. In some implementations, PCB255may include multiple layers, and conductors on different layers may be connected with PCB vias260.

In some implementations, package via235may provide an electrical connection between different layers and/or surfaces of package220. For example, package via235may include a hole, in package220, that is plated with a conductive material to provide the electrical connection. WhileFIG. 2depicts two package vias235of the same length, it is to be understood that other implementations include package vias235that extend to particular layers of package220and/or include different lengths. In some implementations, PCB via260may provide an electrical connection between different layers and/or surfaces of PCB255. For example, PCB via260may include a hole, in PCB255, that is plated with a conductive material to provide the electrical connection.

In some implementations, package vias235and/or PCB vias260may serve as, for example, a transmitter (TX) via, a receiver (RX) via, and/or a ground via, as described below. A TX via may serve as a package via235and/or a PCB via260used for transmission of a signal output by component205. In some implementations, package220and/or PCB255may include a pair of TX vias used to carry a differential signal pair (e.g., a positive signal and a negative signal) transmitted by component205(e.g., for differential signaling). In some implementations, an RX via may serve as a package via235and/or a PCB via260used for reception of a signal to be received by component205. In some implementations, package220and/or PCB255may include a pair of RX vias used to carry a differential signal pair to be received by component205. In some implementations, a ground via may serve as a package via235and/or a PCB via260used for electrical grounding of component205. In some implementations, a ground via may be used to carry a ground signal to component205, may be used to provide a ground connection for power, and/or the like.

In some cases, PCB255may support multiple packages220and/or multiple components205. For example, PCB255may connect to multiple packages220and/or multiple components205to allow signals to be routed from one component205to one or more additional components205. As an example, a transmitter signal (or transmitter signals in the case of a differential signal pair) may be routed from a first component205, through a package via235of a first package220, through a first PCB via260(which may extend one or more layers below a first layer), through a layer connected to a bottom portion of the first PCB via260, to one or more additional PCB vias260. Additionally, the transmitter signal may be routed upward through another PCB via260(e.g., a PCB via260that may be used to reach a second component205), through a package via235of a second package220, and to the second component205. In other cases, a package220may support multiple components205.

In some implementations, package via235and/or PCB via260may include, at each layer of package220and/or PCB255, a pad that provides electrical connections between copper traces on the layer or an anti-pad that defines a non-conductive “void” around the package via235and/or PCB via260to insulate the package via235and/or PCB via260from that layer.

A number of example layers are shown in association with package220(e.g., “L1-L7) and in association with PCB255(e.g., “L1-L9”). Each layer may include conductive traces (e.g., copper traces) that route power, signal, and/or ground communication paths through package220and/or PCB255. Each layer may be generally electrically isolated from one another, and may be potentially connected through package vias235or PCB vias260. In some implementations, a layer may be a power layer or a ground layer. For example, PCB255may include an alternating pattern of ground layers and power layers.

In some implementations, and as shown inFIG. 2, PCB vias260may extend to different layers of PCB255. For example, as shown inFIG. 2, a first via260may extend from a first layer (e.g., “L1”) to a second layer (e.g., “L3”), and a second via may extend from the first layer (e.g., “L1”) to a ninth layer (e.g., “L9”).

In some implementations, different package vias235and/or PCB vias260may be different types of vias. For example, package via235and/or PCB via260may be a laser drilled microvia, a short plated-through hole via, a stacked microvia, a skip via, and/or the like. In some implementations, particular fabrication techniques may be used to extend a package via235to a particular layer of package220and/or a PCB via260to a particular layer of PCB255(e.g., a backdrilling technique, a stacking technique, etc.).

In some implementations, solder ball240may include a mounting mechanism for mounting package220to PCB255. Additionally, or alternatively, solder bump215may include a mounting mechanism for mounting component205to package220. In some implementations, package220may be mounted to the PCB255using the set of solder balls240(e.g., by heating the set of solder balls240and causing the set of solder balls240to melt). In some implementations, the set of solder balls240may be arranged in a grid array (GA). In this case, multiple PCB vias260may be arranged in an array (e.g., an array of PCB vias260) according to the GA pattern of solder balls240(e.g., to provide electrical connectivity for package220mounted to PCB255).

A set of solder balls240is an example of a mounting mechanism that may be used to mount package220to PCB255. Additionally, a set of solder bumps215is an example of a mounting mechanism that may be used to mount component205to package220.

In some implementations, other mounting mechanisms may be used, such as a surface-mount technology (SMT) mechanism (e.g., one or more pins, a pin grid array, one or more leads, one or more flat contacts, and/or the like), a through-hole technology (e.g., one or more leads on the integrated circuit may be inserted into PCB vias260), a land grid array (LGA) (i.e., a flat surface contact with no solder balls), and/or the like.

In some implementations, a set of interconnects may be used as part of a GA space design pattern. For example, interconnect265and interconnect270may be used as part of a GA space design pattern that is located within package220and enables FEXT cancellation between package220and PCB255, as described elsewhere herein. As another example, interconnect275and interconnect280may be used as part of GA space design pattern that is located within PCB255and enables FEXT cancellation between package220and PCB255, as described elsewhere herein. As another example, a combination of interconnects (e.g., interconnect265and interconnect280, interconnect275and interconnect270, etc.) may be used as part of a GA space design pattern that is located both in package220and PCB255and enables FEXT cancellation between package220and PCB255, as described elsewhere herein.

WhileFIG. 2includes a particular number of package vias235and/or PCB vias260, it should be understood that other implementations include different numbers of package vias235and/or PCB vias260that extend to and/or from different layers of package220and/or PCB255. Additionally, whileFIG. 2includes an example of a particular layout of interconnects, it is to be understood that in other examples, a layout of interconnects may be of different sizes, have different physical locations, have a different number of interconnects, be located entirely in the package, be located entirely in the PCB, be located in both the package and the PCB, and/or the like.

FIG. 3is an example implementation300of a GA pin-out pattern. For example, the example GA pin-out pattern shown inFIG. 3may enable package220to mount to PCB255(e.g., to provide electrical connectivity for package220mounted to PCB255using solder balls240). In other words, the example GA pin-out pattern shown inFIG. 3may correspond to a pattern of an array of PCB vias260of PCB255. Additionally, or alternatively, the example GA pin-out pattern shown inFIG. 3may enable package220to mount to component205(e.g., to provide electrical connectivity for package220mounted to component205using solder bumps215). In other words, the example GA pin-out pattern shown inFIG. 3may correspond to a pattern of any array of package vias235of package220.

As shown inFIG. 3, the GA pin-out pattern may include differential TX pin pairs for transmission of signals output by component205, and differential RX pin pairs for reception of signals to be received by component205.

In some implementations, different differential pin pairs may provide and/or receive signals using different package vias235and/or PCB vias260. Additionally, or alternatively, different package vias235may extend to different layers of package220and/or different PCB vias260may extend to different layers of PCB255as described in connection withFIG. 2. For example, a first group of differential RX pin pairs (shown as RX pin pair310-1,310-2,310-3, and310-4) may correspond to PCB vias260that extend to a first layer of PCB255(e.g., layer 3, layer 5, layer 9, etc.), and a second group of differential RX pin pairs (shown as RX pin pair320-1,320-2,320-3, and320-4) may correspond to PCB vias260that extend to a second layer of PCB255(e.g., layer 9, layer 5, layer 3, etc.). That is, various differential RX pin pairs may receive signals using different PCB vias260.

Additionally, or alternatively, a first group of differential TX pin pairs (shown as TX pin pair330-1,330-2,330-3, and330-4) may correspond to PCB vias260that extend to a layer of PCB255(e.g., layer 9, layer 5, layer 3, etc.), and/or a second group of differential TX pin pairs (shown as TX pin pair340-1,340-2,340-3, and340-3) may correspond to PCB vias260that extend to a fourth layer of PCB255(e.g., layer 3, layer 5, layer 9, etc.). That is, various differential TX pin pairs may transmit signals using different PCB vias260.

In some implementations, the GA pin-out pattern shown inFIG. 3may be used to support high-speed differential signals that are at least 56 megabytes per second (Mbps). For example, for 56 Mbps differential signals, the GA pin-out pattern may have a ground via between each TX differential signal pair that is near another TX differential signal pair. Additionally, the GA pin-out pattern may have a ground via between each TX differential signal pair that is near another differential signal pair. Additionally, the GA pin-out pattern may have a ground via between each RX differential signal pair that is near another RX differential signal pair. Additionally, the GA pin-out pattern may have a ground via between a TX differential signal pair that is near an RX differential signal pair.

As another example, for 112 Mbps differential signals, the GA pin-out pattern may have a ground via between each TX differential signal pair that is near another TX differential signal pair. Additionally, the GA pin-out pattern may have a ground via between each RX differential signal pair that is near another RX differential signal pair. Additionally, the GA pin-out pattern may have two ground vias between a TX differential signal pair that is near an RX differential signal pair.

As another example, for 224 Mbps differential signals, the GA pin-out pattern may have two ground vias between each TX differential signal pair that is near another TX differential signal pair. Additionally, the GA pin-out pattern may have two ground vias between each RX differential signal pair that is near another RX differential signal pair. Additionally, the GA pin-out pattern may have three ground vias between a TX differential signal pair that is near an RX differential signal pair.

This GA pin-out pattern allows for more cross-sectional bandwidth of package220and/or PCB255than a GA pin-out pattern for a PCB assembly that is unable to rely on the GA space design pattern to enable FEXT cancellation. For example, without the GA space design pattern to enable FEXT cancellation, the GA pin-out pattern would only be able to support high-speed differential signals that are 112 Mbps if the GA pin-out pattern included two ground layers between each TX differential signal pair that is near another TX differential signal pair, two ground layers between each RX differential signal pair that is near another RX differential signal pair, and three ground layers between a TX differential signal pair that is near an RX differential signal pair. In this way, the GA space design pattern is able to improve cross-sectional bandwidth of package220and/or PCB255relative to conventional GA schemes that are unable to achieve FEXT cancellation.

WhileFIG. 3depicts a particular GA pin-out pattern, it should be understood that other implementations include other GA pin-out patterns. Additionally, while implementations herein describe differential pin pairs corresponding to PCB vias260that extend to particular layers of PCB255, other implementations include differential pin pairs that extend to other layers of PCB255.

In this way, the GA space design pattern enables FEXT cancellation to reduce or eliminate FEXT. Additionally, the GA space design pattern improves cross-sectional bandwidth of the PCB and/or the package, increases signal density, and/or improves throughput of the PCB assembly by reducing a number of ground vias that need to be placed between vias that support actual traffic to and from the component.