An interconnect is described that comprises an interconnect channel, and two channel couplers coupled to the two ends of the interconnect channel through respective stoppers that provide a gap between the channel couplers and the interconnect channel. Each channel coupler can comprise a coplanar waveguide, a microstrip line, and a patch-antenna based coupler. The interconnect can enable communication between integrated circuits using signal waves having a frequency between 100 GHz and 3 THz.

BACKGROUND

Technical Field

This disclosure relates to electronic circuits. More specifically, this disclosure relates to a sub-terahertz (THz)/THz interconnect.

Related Art

Semiconductor technology advancements generate two side effects. On the one hand, the advancements speed up data processing and reduce energy consumption per bit. On the other hand, these advancements keep increasing transmission data rate requirements and keep increasing the gap from interconnect capabilities. Some experts envision that the energy used for data communication is orders of magnitude higher than the energy used for data processing and storage (see e.g., E. Yablonovitch, SRC Workshop, Asheville, 2005). Therefore, in the near future, majority of the energy is expected to be consumed by data communication.

SUMMARY

Some embodiments described herein feature an interconnect that comprises (1) an interconnect channel that can have a middle portion, a first end portion, and a second end portion, (2) a first channel coupler that can be coupled to the first end portion of the interconnect channel through a first stopper, wherein the first stopper can provide a first coupling gap between the first channel coupler and the first end portion of the interconnect channel, and (3) a second channel coupler that can be coupled to the second end portion of the interconnect channel through a second stopper, wherein the second stopper can provide a second coupling gap between the second channel coupler and the second end portion of the interconnect channel. The first end portion can include a first bend to guide signal waves between the middle portion and the first channel coupler, and the second end portion can include a second bend to guide signal waves between the middle portion and the second channel coupler.

In some embodiments, the first channel coupler can be electrically coupled to a transmitter and/or a receiver in a first integrated circuit (IC). Likewise, the second channel coupler can be electrically coupled to a transmitter and/or a receiver in a second IC. Additionally, in some embodiments, the interconnect, the first IC, and the second IC can be packaged in an IC package. Specifically, in some embodiments, the interconnect, the first IC, and the second IC can be fabricated using the same planar silicon process on a single die.

In some embodiments, each channel coupler can comprise (1) a coplanar waveguide, (2) a patch-antenna based coupler, and (3) a microstrip line. The microstrip line can be coupled between the coplanar waveguide and the patch-antenna based coupler, and the patch-antenna based coupler can be coupled to an end portion of the interconnect channel through a stopper. The coplanar waveguide can be coupled to a transmitter or a receiver in an IC.

A transmitter on a first IC can provide a communication signal having a frequency between 100 gigahertz (GHz) and 3 THz to the coplanar waveguide, which can provide the signal to the microstrip line. The microstrip line can provide the signal to the patch-antenna based coupler. From the patch-antenna based coupler, the signal can pass through the stopper and through the interconnect channel to the other end of the interconnect channel. At the other end, the interconnect channel can provide the signal to the patch-antenna based coupler, which can provide the signal to the microstrip line. Next, the microstrip line can provide the signal to coplanar waveguide, which can then provide the signal to a receiver on a second IC.

In some embodiments, the interconnect channel can be comprised of silicon with a relative permeability of approximately 11.9. Moreover, the silicon can have a resistivity greater than 5000 Ω-cm. In some embodiments, the bends in the first and second end portions of the interconnect channel can have a radius of curvature greater than 0.4 millimeters. In some embodiments, each stopper can be comprised of a dielectric material, such as SU-8.

DETAILED DESCRIPTION

Overview

Some embodiments described herein feature sub-THz and/or THz interconnects that comprise channels and couplers that are compatible with a planar silicon process to realize high energy efficiency and high bandwidth density. Some embodiments include techniques to transmit multiple data streams through one physical channel by using different multiplexing schemes: including Time Division Multiplexing, Frequency Division Multiplexing, Wavelength Division Multiplexing, Mode Division Multiplexing, Polarization Division Multiplexing, etc.

The unique spectrum position of the sub-THz/THz interconnect (e.g., signal frequencies between 100 GHz to 3 THz), sitting between microwave and optical frequencies, allows the interconnect to leverage the advantages from both optic and electronic approaches. Low loss sub-THz/THz channels similar to optic fibers greatly relax interconnect link budget. Concurrently, a silicon based transceiver, scaling with technology, keeps interconnect bandwidth and efficiency improving at the same pace with device speed and maintains low manufacture cost and high reliability. Therefore, the THz interconnect aims to resolve the last centimeter issue for inter- and intra- chip links that have not been achieved by neither electronic nor optic interconnects.

Some advantages of embodiments described herein include, but are not limited to, (1) low cost due to the compatibility with existing mainstream semiconductor technologies with minimum fabrication changes, (2) high reliability due to the usage of mainstream semiconductor technologies, (3) high bandwidth and bandwidth density due to ultra high carrier frequency at sub-THz/THz and small channel size, (4) low loss due to dielectric waveguide material, and (5) scale friendly with semiconductor processes to match with technology advancement.

Interconnect Channel

The choice of channel material should consider several factors: 1) being compatible with silicon processing; 2) having large permittivity to concentrate the field along the channel for low loss and result in small channel size for large bandwidth density. Therefore, in some embodiments, high resistivity (HR) silicon dielectric, with relative permittivity around 11.9, is chosen as the channel material. The high resistivity (HR>5,000 Ω-cm) of the silicon dielectric reduces the propagation loss.

The advantages of dielectric waveguides over metallic waveguides include: (1) lower cutoff frequencies to allow further shrinking of the channel cross-section with less performance degradation for higher bandwidth density; (2) lower losses at high frequencies for better efficiency; (3) easier integration with silicon processes without significantly increasing fabrication complexity. Additionally, the large dielectric constant of silicon, around 11.9, facilitates to confine the field inside the channel to reduce propagation losses.

FIG. 1Aillustrates an interconnect channel in accordance with some embodiments described herein. Interconnect channel100can be a silicon based dielectric channel, and can have width W and thickness T, and can comprises a middle portion having length L, and two end portions that have a bend with radius of curvature R to guide signal waves to and from planar ICs.FIG. 1Bpresents a plot of the effective index versus propagation signal frequency for different modes of the interconnect channel illustrated inFIG. 1Ain accordance with some embodiments described herein.FIG. 1Cpresents a plot of the channel insertion loss for the interconnect channel illustrated inFIG. 1Ain accordance with some embodiments described herein. The embodiment that was simulated inFIGS. 1B and 1Chad the following dimensions: W=500 μm, T=400 μm, L=6 mm, and R=300 μm.FIG. 1Bdemonstrates the capability of the interconnect channel to support large bandwidth, andFIG. 1Cdemonstrates that the channel has a<1 dB insertion loss over a broad frequency band. InFIG. 1C, “S21” represents the “S” parameter from “port1” to “port2,” i.e., “S21” represents the power transferred from “port1” to “port2.” “Port1” can correspond to one of the ends of interconnect channel100, and “port2” can correspond to the other end (interconnect channel100is symmetrical with respect to the two ends, so it doesn't matter which end is called “port1” for computing the “S21” parameter).

As explained above, to couple signals between two planar ICs, a bending structure is used. The bending structure has several tradeoffs. First, it is preferred that the bending radius be small to be compact and low profile so that the channels are reliable. On the other hand, when the radius is too small, the propagating waves tend to leak outside of the channel to cause large losses. To choose optimal radius, extensive simulation of the wave propagation based on different radius was performed. The simulation results show that the majority of the field is confined within the channel due to the large permittivity difference between silicon and the air. A simulation of the H-field distribution of a bending structure with the radius of 200 μm shows that some of field leaks out of the channel and increases the propagation loss. The S21and S11values were determined from simulation for radius values of 200, 300, and 400 μm. From the simulation results, it was found that S11values are less than −20 dB and S21values are less than −1 dB for all the three cases, with S21improving with a larger radius. Simulation results also indicated that further increasing of the radius higher than 400 μm results in incremental improvement in insertion loss, which indicates that wave leakage becomes less significant.

Channel Coupler

The channel coupler also needs to be compatible with planar silicon processes, with minimum changes of the fabrication procedure. In addition, the generated field should be convenient to couple to the channel with minimum coupling loss. Therefore, some embodiments described herein use a patch-antenna based coupler, which is completely compatible with silicon processes, and the perpendicular propagation pattern of the patch-antenna based coupler matches with channel feeding.

In some embodiments, a liquid crystalline polymer (e.g., Rogers 3850) with 1 mil thickness and dielectric constant of 2.9, can be used as the antenna substrate. The coupling structure consists of a coplanar waveguide (CPW), a via-less transition from the CPW to a microstrip line, the microstrip line, and the patch-antenna based channel coupler. All the metal, except the bottom copper-based ground, is for minimum oxidization. To simplify the coupler fabrication, a via-less CPW to microstrip line transition is adopted. Specifically, the bottom metal is ac-coupled through the thin substrate. Furthermore, by choosing ground plane width much smaller than the signal wavelength, higher order modes can be avoided to reduce insertion loss.

FIG. 2Aillustrates a top view of a channel coupler in accordance with some embodiments described herein. Channel coupler200includes coplanar waveguide202, microstrip line204, and patch-antenna based coupler206. The dimensions shown inFIG. 2Aare for illustration purposes only and are not intended to limit the scope of the instant application.FIG. 2Bpresents a plot of the S11parameter (which represents the reflected power at port1) for the channel coupler shown inFIG. 2Ain accordance with some embodiments described herein. As can be seen from the plot shown inFIG. 2B, a channel coupler that has the dimensions shown inFIG. 2Aresults in a −10 dB bandwidth of 4.8 GHz.

Interconnect Structure

To accurately control the coupling gap between the coupler and the channel, a stopper made of low loss dielectric material can be employed. For example, SU-8 can be used as the stopper material. With a dielectric constant of 2.9, the SU-8 stopper changes the coupler resonant frequency and the feeding impedance. The final coupler sizes (400 μm×500 μm) with SU-8 can therefore be adjusted by using electromagnetic simulation or measurement tools to resonate around 200 GHz.

FIG. 3Aillustrates a side view of an interconnect in accordance with some embodiments described herein.FIG. 3Ais for illustration purposes only (in particular, the components shown inFIG. 3Aare not necessarily drawn to scale). Interconnect300includes interconnect channel302and channel couplers304and306. Channel couplers304and306can be communicatively coupled to the two ends of interconnect channel302through stoppers308and310, respectively. Channel couplers304and306can be electrically coupled to transmitters or receivers in ICs312and314, respectively.FIG. 3Billustrates a three dimensional view of an interconnect in accordance with some embodiments described herein. In one embodiment, the total loss through the link path was approximately 5.1 dB at 200 GHz.

Fabrication Process

FIG. 4illustrates a process for fabricating an interconnect channel in accordance with some embodiments described herein. The interconnect channel can be fabricated based on lithography and deep reactive ion etching (DRIE). First, a thick (˜17 μm) photoresist (PR) can be patterned on the high resistance (HR) silicon wafer and hard-baked (patterning step402). Using cool grease, the HR silicon wafer can be bonded on the top of a handle wafer (bonding step404). The HR wafer can then be etched by DRIE process (DRIE step406). After removing the cool grease, the individual channels can be separated.

FIG. 5illustrates a process for fabricating a patch-antenna based coupler in accordance with some embodiments described herein. Specifically, a patch-antenna based coupler can be fabricated using lithography and physical vapor deposition (PVD). In patterning step502, an adhesive and a liquid crystalline polymer (e.g., “Rogers 3850” shown inFIG. 5) can be bonded on the top of a handle silicon wafer (shown as “Si” inFIG. 5). Then the top copper can be etched off. The antenna pattern can then be defined by a layer of photoresist (shown as “PR” inFIG. 5).

In PVD step504, a layer of titanium (50 nm) and gold (300 nm) can be evaporated onto the substrate to form the top metal by a lift-off process (shown as “Au” inFIG. 5). Next, in stopper construction step506, a 200-μm thick dielectric (e.g., SU8-2075) layer can be patterned to construct the dielectric stopper. To support the channel and facilitate assembly, a 3D printed holder with a low dielectric constant material (about 2.7) can be utilized, which has a negligible effect on the signal propagation based on full-wave simulation.

FIG. 6illustrates an IC package in accordance with some embodiments described herein. Specifically, IC package602can include ICs604and608that can communicate with each other via interconnect606. Specifically, ICs604and608can include transmitters and/or receivers that can send and/or receive sub-THz or THz communication signals (e.g., communication signals having a frequency between 100 GHz and 3 THz) through interconnect606. As described in this disclosure, interconnect606can be fabricated using the same planar silicon process that is used for fabricating ICs604and608. Specifically, in some embodiments, ICs604and608and interconnect606can be fabricated on the same die.

Sample Measurement Results

An interconnect was fabricated with channel length 6 mm, bend radius is 300 μm, and channel thickness 400 μm, and the measured S parameters were compared with the simulated results. Specifically, for the fabricated interconnect, the peak S21was −11.6 dB, which presents a 6.5 dB performance degradation compared to simulation results. The resonant frequency was shifted from 200 GHz to 190 GHz.

To verify performance sensitivity, the channel thickness was varied from 300 μm to 500 μm. The S11did not vary significantly for different thickness channels, which indicates that the frequency response is not determined by the channel, which is consistent with the simulation results. The magnitude of insertion loss S21varied with channel thickness. The larger the thickness, the lower the insertion loss tends to be. When the thickness is larger than 450 μm the magnitude of S21did not vary significantly.

The foregoing description has been presented to enable any person skilled in the art to make and use the embodiments. The described embodiments are not intended to be exhaustive or to limit the present invention. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein are applicable to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present invention is to be accorded the widest scope consistent with the principles and features disclosed herein. The scope of the present invention is defined by the appended claims.