Variable gain amplifier circuit

A variable gain amplifier circuit includes: an operational amplifier having a non-inverting input terminal applied with a predetermined voltage; a feedback resistor having one end connected to an inverting input terminal of the operational amplifier and the other end connected to an output terminal of the operational amplifier; and a variable resistor having one end applied with an input voltage and the other end connected to the inverting input terminal of the operational amplifier.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority to Japanese Patent Application No. 2009-242711, filed Oct. 21, 2009, of which full contents are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a variable gain amplifier circuit.

2. Description of the Related Art

In an integrated circuit such as an optical pickup IC, a variable gain amplifier circuit which amplifies an input signal with a desired gain may be used.FIG. 2depicts a configuration of a typical variable gain amplifier circuit (hereinafter, VGA: Variable Gain Amplifier)100(see, e.g., Japanese Laid-Open Patent Publication No. 2008-301035). The VGA100includes an operational amplifier110, resistors120to122, switches130,131, and a capacitor140. It is assumed that the resistance values of the resistors120to122are R0to R2, respectively. For example, when only the switch130is turned on, the resistor121is connected between an inverting input terminal and an output terminal of the operational amplifier110. Therefore, the magnitude of the direct-current gain of the VGA100is R1/R0. For example, when only the switch131is turned on, the magnitude of the direct-current gain of the VGA100is R2/R0. As such, ON/OFF of the switches130,131is controlled, to change the magnitude of the direct-current gain of the VGA100. The capacitor140connected between the inverting input terminal and the output terminal of the operational amplifier110has a capacitance which limits the frequency band of the VGA100.

The resistors130,131are feedback resistors and have parasitic capacitances. Therefore, if the switches130,131are switched ON/OFF, a capacitance value of a feedback loop of the operational amplifier110may be changed and a phase margin of the operational amplifier110may deteriorate. If the phase margin of the operational amplifier110deteriorates, the VGA100may oscillate.

SUMMARY OF THE INVENTION

A variable gain amplifier circuit according to an aspect of the present invention, includes: an operational amplifier having a non-inverting input terminal applied with a predetermined voltage; a feedback resistor having one end connected to an inverting input terminal of the operational amplifier and the other end connected to an output terminal of the operational amplifier; and a variable resistor having one end applied with an input voltage and the other end connected to the inverting input terminal of the operational amplifier.

Other features of the present invention will become apparent from descriptions of this specification and of the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

At least the following details will become apparent from descriptions of this specification and of the accompanying drawings.

FIG. 1is a diagram illustrating a configuration of an optical pickup IC10according to an embodiment of the present invention. The optical pickup IC10is a circuit that receives laser light from an optical pickup (not shown), to be converted into an electric signal, for example. The optical pickup IC10includes a photodiode20, a current-voltage converting circuit21, a VGA22, buffer amplifiers23,24, and terminals25,26.

The photodiode20generates a current I1corresponding to intensity of the received laser light.

The current-voltage converting circuit21is a circuit that converts the current I1into a voltage V1, and includes an operational amplifier30and a resistor31. A reference voltage Vref1is applied to a non-inverting input terminal of the operational amplifier30. The resistor31is connected between an inverting input terminal and an output terminal of the operational amplifier30. Therefore, the output terminal of the operational amplifier30generates the voltage V1which varies around the reference voltage Vref1according to the product of a current value of the current I1and a resistance value of the resistor31.

The VGA22is a circuit that amplifies the voltage V1with a gain which is based on setting data, and includes a control circuit40, resistors50to53, a capacitor55, NMOS transistors60,61, and an operational amplifier70.

The control circuit40controls ON/OFF of the NMOS transistors60,61based on, e.g., two-bit setting data which is input from, e.g., a microcomputer (not shown). The control circuit40includes a memory that stores the setting data. The control circuit40turns off both of the NMOS transistors60,61if setting data (0, 0) is input thereto, and turns on the NMOS transistor60and turns off the NMOS transistor61if setting data (1, 0) is input thereto. The control circuit40turns off the NMOS transistor60and turns on the NMOS transistor61, if setting data (0, 1) is input thereto. The control circuit40turns on both of the NMOS transistors60,61, if setting data (1, 1) is input thereto.

The resistors50to52are connected in series between the output terminal of the operational amplifier30and an inverting input terminal of the operational amplifier70. A node connected to the resistor50(first resistor) and the resistor51is connected to a drain of the NMOS transistor60(switch element), and a node connected to the resistor51and the resistor52is connected to a source of the NMOS transistor60. The node connected to the resistor51and the resistor52is connected to a drain of the NMOS transistor61(switch element), and a node connected to the resistor52and the inverting input terminal of the operational amplifier70is connected to the source of the NMOS transistor61. Therefore, a resistance value of a resistor connected between the output terminal of the operational amplifier30and the inverting input terminal of the operational amplifier70, i.e., a resistor on the input side of the operational amplifier70, is changed in accordance with the state of the NMOS transistors60,61. The resistors50to52correspond to a variable resistor, the resistors51,52correspond to a second resistor, and the NMOS transistors60,61correspond to a switch circuit.

The resistor53is a feedback resistor connected between the inverting input terminal and the output terminal of the operational amplifier70. The capacitor55is connected between the inverting input terminal and the output terminal of the operational amplifier70as is the case with the resistor53. Therefore, the operational amplifier70operates as an inverting amplifier circuit that inverts and amplifies the voltage V1with a ratio between the impedance of the resistor on the input side of the operational amplifier70and the impedance of the resistor53and the condenser55. Since a reference voltage Vref2is applied to a non-inverting input terminal of the operational amplifier70, a voltage V2of the output terminal of the operation amplifier varies around the reference voltage Vref2.

The buffer amplifier23outputs to the terminal25a voltage Vout1obtained by amplifying the voltage V2with a predetermined gain. The buffer amplifier24outputs to the terminal26a voltage Vout2obtained by inverting and amplifying the voltage V2with a predetermined gain. The voltage V2is amplified by the buffer amplifiers23,24in a differential manner.

==Direct-Current Gain of VGA22==

A description will be given of the voltage V2output from the VGA22when different setting data are set. In an embodiment according to the present invention, the resistance values of the resistor50, the resistor51, the resistor52, and the resistor53are denoted by R0, r1, r2, and R1, respectively, and the on-resistances of the NMOS transistor60and the NMOS transistor61are denoted by Ron1and Ron2, respectively. It is assumed that each of the on-resistances Ron1and Ron2is sufficiently smaller than the resistances r1, r2. The resistors50to52and the NMOS transistor60,61are designed such that the resistance values R0, r1, and r2satisfy R0>>r1>r2and that the resistance values R0, r1//Ron1, and r2//Ron2satisfy R0>>r1//Ron1>r2//Ron2. Therefore, a combined resistor determined by the resistor52and the on-resistance Ron2is smaller than a combined resistor determined by the resistor51and the on-resistance Ron1, and values of the combined resistors serially connected to the resistor50in decreasing order of resistance value from the resistor50side. It is also assumed that the reference voltage Vref2is 0 (zero) V, for example.

Both of the NMOS transistors60,61are turned off if the setting data (0, 0) is set in the control circuit40, and thus, a direct-current gain A(0, 0) of the VGA22is −R1/(R0+r1+r2). The direct-current gain of the VGA22corresponding to the setting data (0, 0) set in the control circuit40will hereinafter be denoted as the direct-current gain A(0, 0).

If the setting data (1, 0) is set in the control circuit40, the NMOS transistor60is turned on and the NMOS transistor61is turned off. Therefore, a direct-current gain A(1, 0) is −R1/(R0+r1//Ron1+r2). Thus, the voltage V2is expressed as follows:
V2=(−R1/(R0+r1//Ron1+r2))×V1  (2).

If the setting data (0, 1) is set in the control circuit40, the NMOS transistor60is turned off and the NMOS transistor61is turned on. Thus, a direct-current gain A(0, 1) is −R1/(R0+r1+r2//Ron2). Therefore, the voltage V2is expressed as follows:
V2=(−R1/(R0+r1+r2//Ron2))×V1  (3).

If the setting data (1, 1) is set in the control circuit40, both of the NMOS transistors60,61are turned on. Thus, a direct-current gain A(1, 1) is −R1/(R0+r1//Ron1+r2//Ron2). Therefore, the voltage V2is as follows:
V2=(−R1/(R0+r1//Ron1+r2//Ron2))×V1  (4).

As described above, each of the on-resistances Ron1and Ron2is sufficiently smaller than the resistances r1, r2, and R0>>r1>r2is satisfied. Therefore, the magnitudes of the direct-current gains of the VGA22satisfy A(1, 1)>A(1, 0)>A(0, 1)>A(0, 0). As such, in the VGA22according to an embodiment of the present invention, the direct-current gain is able to be changed in accordance with the setting data.

==Operation of Optical Pickup IC10==

A description will be given of the operation of the optical pickup IC10. It is assumed that the setting data (1, 1) is set in the control circuit40, for example.

When laser light from an optical pickup (not shown) is received by the photodiode20, the voltage V1is generated in accordance with the intensity of the laser light. The voltage V1is amplified with the direct-current gain A(1, 1), and is output as the voltage V2to the buffer amplifiers23,24. As a result, the voltage V2is differentially amplified and is output as the voltages Vout1and Vout2to the terminals25and26, respectively.

The description has been given of the optical pickup IC10according to an embodiment of the present invention. In the VGA22of an embodiment of the present invention, in order to change the direct-current gain, a resistance value of the resistor on the input side of the operational amplifier70is changed without the resistor53provided on the feedback loop of the operational amplifier70being changed. Therefore, since a capacitance value of the feedback loop of the operational amplifier70does not change in the VGA22, the effect of the feedback loop on the phase margin of the operational amplifier70can be reduced. Thus, as compared to a common VGA such as those in which a resistor provided on the feedback loop is changed, for example, the VGA22stably operates.

In the VGA22, the resistors50to52connected in series are provided between the node applied with the voltage V1, i.e., the output terminal of the operational amplifier30and the inverting input terminal of the operational amplifier70. The resistors51,52are provided with the NMOS transistors60,61in parallel. In an embodiment of the present invention, the resistance value on the input side of the operational amplifier70can easily be changed by the NMOS transistors60,61being switched on/off.

Among the serially connected resistors50to52, the resistor50applied with the voltage V1is not connected in parallel with an NMOS transistor, etc. Therefore, in the VGA22, a reference direct-current gain is R1/R0, which is determined by a ratio between the resistance value R0of the resistor50and the resistance value R1of the resistor53.

In the VGA22, the two NMOS transistors60,61which are controlled by two-bit setting data are connected in parallel with the resistors51,52, respectively. Therefore, the VGA22can acquire four different direct-current gains. As such, in the VGA22, the resistance value on the input side is changed by the two resistors and the two NMOS transistors, however, n resistors serially connected on the input side of the operational amplifier70and NMOS transistors respectively connected in parallel with the n resistors may be provided, for example. In this case, 2ndifferent direct-current gains can be acquired. For example, even if n resistors are used, a combined resistor is calculated more easily when n resistors are connected in series, as compared to the case in which n resistors are connected in parallel. Therefore, particularly if the number of resistors which are connected on the input side of the operational amplifier70is increased, the burden in design can be alleviated by connecting n resistors in series as in the case of an embodiment of the present invention.

The on-resistances Ron1, Ron2are generally changed in accordance with drain-source voltages of the NMOS transistors60,61, respectively. In an embodiment of the present invention, the resistance value R0of the resistor50is set greater than each of the resistance values r1, r2of the resistors51,52. Therefore, even if the voltage V1is significantly changed, change in each of the voltages of the resistors51,52is smaller than change in the voltage of the resistor50. That is, in the VGA22, even if the voltage V1is significantly changed, the change can be reduced in the drain-source voltages of the NMOS transistors60,61. Therefore, in the VGA22, since change in the on-resistances Ron1, Ron2is small relative to change in the voltage V1, an accurate direct-current gain can be acquired.

In an embodiment of the present invention, the resistance value r1of the resistor51is set greater than the resistance value r2of the resistor52. Therefore, even if the voltage V1is significantly changed, change in the voltage of the resistor52is reduced. That is, in the VGA22, even if the voltage V1is significantly changed, change in the drain-source voltage of the NMOS transistor61can be reduced. Specifically, for example, when the drain-source voltage of the NMOS transistor61is denoted by Vds, if the setting data (0, 1) is set, Vds=((r2//Ron2)/(R0+r1+r2//Ron2))×V1is satisfied. It is assumed herein that the source voltage of the NMOS transistor61is equivalent to Vref2=0V. When the numerator and the denominator on the right-hand side of the voltage Vds are divided by (R0+r1), Vds=((r2//Ron2)/(R0+r1))/(1+(r2//Ron2)/(R0+r1)))×V1is obtained. As described above, since the resistance value r1>the resistance value r2is satisfied, (r2//Ron2)/(R0+r1) is smaller as compared with the case of the resistance value r1<the resistance value r2, for example. As a result, in an embodiment of the present invention, even if the voltage V1is significantly changed, a value of the on-resistance Ron2of the NMOS transistor60is substantially constant, since change in the voltage Vds is suppressed. Therefore, in the VGA22according to an embodiment of the present invention, an accurate direct-current gain can be acquired.

The above embodiments of the present invention are simply for facilitating the understanding of the present invention and are not in any way to be construed as limiting the present invention. The present invention may variously be changed or altered without departing from its spirit and encompass equivalents thereof.