Enhanced flip-chip die architecture

A method of assembling a multi-chip electronic device into a thin electronic package entails inverting a flip-chip die arrangement over a hollow substrate, stacking additional dies on the hollow substrate to form a multi-chip electronic device, and encapsulating the multi-chip electronic device. Containment of the encapsulant can be achieved by joining split substrate portions, or by reinforcing a hollow unitary substrate, using a removable adhesive film. Use of the removable adhesive film facilitates surrounding the multi-chip electronic device with the encapsulant. The adhesive film can also prevent encapsulant from creeping around the substrate to an underside of the substrate that supports solder ball pads for subsequent attachment to a ball grid array (BGA) or a land grid array (LGA).

BACKGROUND

1. Technical Field

The present disclosure relates to electronic packaging of microelectronic devices.

2. Description of the Related Art

A trend in microelectronics packaging is reduction of the electronic package dimensions—both the package footprint and the package thickness—while continuing to provide greater functionality. It is now customary to stack multiple integrated circuit dice, electrically connect the dice using wire bonds, and encapsulate the stack into a single electronic package. The packaged multi-chip electronic device can then be surface-mounted to a printed circuit board (PCB) by forming a two-dimensional array of solder balls on an underside of the packaged device. Such PCBs can then be installed in, for example, mobile electronic devices such as smart phones, tablet computers, global positioning system (GPS) mapping devices, digital cameras, and the like. Each generation of such mobile devices demands smaller and thinner electronic packages, while providing more functions to consumers. Enhanced functionality requires more complex integrated circuits, and more dice stacked into the electronic package.

BRIEF SUMMARY

A method of assembling a multi-chip electronic device into a thin electronic package entails inverting a flip-chip die arrangement over an open region in a substrate carrier, stacking additional dies on the split substrate carrier, and encapsulating the multi-chip electronic device. The split substrate carrier can be a two-part substrate, a single substrate that has been split, or a hollow unitary substrate. Containment of the encapsulant in a split substrate can be achieved by joining split substrate portions using a removable adhesive film. Containment of the encapsulant in the split substrate can be reinforced by the adhesive. Use of the adhesive facilitates surrounding the multi-chip electronic device with the encapsulant. The adhesive can also prevent encapsulant from creeping around the substrate to an underside of the substrate that supports a solder ball connection pad (e.g., a ball grid array (BGA) or a land grid array (LGA)).

DETAILED DESCRIPTION

It will be appreciated that, although specific embodiments of the present disclosure are described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is not limited except as by the appended claims.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter may be practiced without these specific details. In some instances, well-known structures and methods of semiconductor processing comprising embodiments of the subject matter disclosed herein have not been described in detail to avoid obscuring the descriptions of other aspects of the present disclosure.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter may be practiced without these specific details. In some instances, well-known structures and methods of semiconductor processing comprising embodiments of the subject matter disclosed herein have not been described in detail to avoid obscuring the descriptions of other aspects of the present disclosure.

Reference throughout the specification to insulating materials or semiconducting materials can include various materials other than those used to illustrate specific embodiments of the transistor devices presented. The term encapsulant should not be construed narrowly to limit an encapsulant to a molding compound, for example, but rather, the term “encapsulant” is broadly construed to cover any compounds that can be used to provide environmental protection for encapsulated circuitry.

Reference throughout the specification to conventional thin film deposition techniques for depositing silicon nitride, silicon dioxide, metals, or similar materials include such processes as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electro-less plating, and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to certain deposition techniques should not be limited to those described. For example, in some circumstances, a description that references CVD may alternatively be done using PVD, or a description that specifies electroplating may alternatively be accomplished using electro-less plating. Furthermore, reference to conventional techniques of thin film formation may include growing a film in-situ. For example, in some embodiments, controlled growth of an oxide to a desired thickness can be achieved by exposing a silicon surface to oxygen gas or to moisture in a heated chamber.

Reference throughout the specification to conventional photolithography techniques, known in the art of semiconductor fabrication for patterning various thin films, include a spin-expose-develop process sequence involving a photoresist. Such a photolithography sequence entails spinning on the photoresist, exposing areas of the photoresist to ultraviolet light through a patterned mask, and developing away exposed (or alternatively, unexposed) areas of the photoresist, thereby transferring a positive or negative mask pattern to the photoresist. The photoresist mask can then be used to etch the mask pattern into one or more underlying films. Typically, a photoresist mask is effective if the subsequent etch is relatively shallow, because photoresist is likely to be consumed during the etch process. Otherwise, the photoresist can be used to pattern a hard mask, which in turn, can be used to pattern a thicker underlying film.

In the description that follows, the terms “dies,” “dice,” “chips” “semiconductor chips,” and “integrated circuit chips” are used interchangeably. Specific embodiments are described herein with reference to examples of electronic packages that have been produced; however, the present disclosure and the reference to certain materials, dimensions, and the details and ordering of processing steps are exemplary and should not be limited to those shown.

FIG. 1shows a high-level packaging process90for packaging a multi-chip electronic device according to one embodiment described herein. The packaging process90permits assembly of a multi-chip electronic device into a thin package.

At92, a flip-chip die arrangement is inverted over a split substrate carrier. In one embodiment, the split substrate carrier is a hollow substrate in which a trough or a cavity has been formed. Alternatively, the split substrate can be a two-part substrate comprising two detached portions. As a further alternative, the split substrate can be two independent die, which are each fully functional circuits on their own substrates that are brought close to each other, with a selected space between them. The two separate substrates are placed with a set distance between them, thus have a split that separates them. This is therefore one more example of a split substrate. The flip-chip die arrangement includes at least two integrated circuit chips, thus constituting a multi-chip electronic device.

At93, an adhesive can be attached to an underside of the split substrate carrier. If the split substrate carrier is for two different die, the adhesive joins the two die, each of them being one portion of the split substrate. These two portions provide containment for an encapsulant. If the split substrate carrier has a continuous underside, as would be the case for a hollow substrate, with a recess to provide the hollow region, the adhesive may not be needed, and if so, it is not used; however, if desired, the adhesive provides structural reinforcement to enhance containment for an encapsulant. The adhesive may be in the form of an adhesive tape, or an adhesive film, for example.

At94, additional integrated circuit chips can be stacked on the split substrate carrier to add functionality to the multi-chip electronic device.

At95, the multi-chip electronic device can be surrounded by an encapsulant. The encapsulant may be, for example, a standard molding compound, or a specialized molding compound having a selected viscosity. The encapsulant is intended to fill a hollow part of the hollow substrate carrier. A curing process may be used to harden the encapsulant and strengthen the package.

At96, the adhesive can be removed.

At97, the encapsulant can be cured to solidify or harden the encapsulant material.

At98, solder balls can be attached to the underside of the split substrate carrier for subsequent mounting onto a PCB.

Details of the packaging process90are presented below, with reference toFIGS. 2A-6B.

FIGS. 2A and 2Bdescribe and show a flip-chip die attach arrangement100that includes first and second integrated circuit chips102and104, respectively. The integrated circuit chips102and104contain circuitry for providing various functions such as, for example, digital or analog signal processing, memory, wireless communications, and the like. The integrated circuit (IC) chips102and104are, in general, two different types of IC chips.

At106, the IC chips102and104can be fabricated on separate semiconductor wafers108and110respectively, (e.g., silicon wafers, III-V semiconductor wafers, etc.). However, the IC chips102and104could potentially be the same type of IC chips, for example, two memory chips, or two processors. Following the wafer fabrication process106, post-processing steps may include back grinding the wafers (112) and sawing the wafers (114) into the individual first and second IC chips102and104.

At116, the first IC chip102, sometimes called the daughter, can be joined to the second IC chip104, sometimes called the mother, using a process which is well known to those skilled in the art as a flip-chip die attach process. In a flip-chip die attach process, instead of using wire bonds to electrically couple circuitry on the respective dies, a matrix of solder balls118can be fabricated on a side of the first IC chip102, for attachment to bond pads120formed on a side of the second IC chip104. In turn, an arrangement of solder balls122(e.g., one or more arrays) can be formed around a perimeter of the second IC chip104for subsequent attachment to a split substrate carrier as shown below.

With reference toFIGS. 3A and 3B, at123, the flip-chip die attach arrangement100can be inverted and attached to a split substrate carrier via the solder balls122. In the embodiment shown, the split substrate carrier is in the form of a two-die split substrate124having a left die126and a right die128. However, the split substrate carrier may otherwise be a unitary substrate in which a trough or a cavity is formed as a hollow part of the substrate. The hollow substrate carrier can be made of a polymer material such as that which is used to make printed circuit boards (PCBs). Alternatively, the split substrate carrier can be a semiconductor substrate.

In the embodiment shown inFIG. 3B, the split substrate124is composed of two separate and independent die126and128. Each of these die126and128are composed of operating semiconductor circuits, such as logic or microprocessor circuits each formed in a monocrystalline silicon substrate. The two die126and128are brought adjacent to each other and positioned for coupling to a carrier or adhesive138having a selected space134between them. In this embodiment, as shown, the operating circuits on126and128will also provide electrical output via bond pads120, as explained later herein. Accordingly, there is a bond pad on a first surface of each of126and128, respectively, to receive the solder balls122from the flip-chip die104. These signals can be processed and handled by the logic circuitry in their respective die126and128or, alternatively, can be routed through to the bond pads120, depending on the function of the circuit and the design characteristics.

In another alternative, the split substrate may be two substrates which have no logic circuits thereon, and merely perform the substrate support function and provide electrical connection from the die104to the bond pads120. As a further alternative, in one embodiment the split substrate124may include portions126and128, which are actually two parts of the same substrate, which extend as fingers during the assembly process but are subsequently severed from a larger unitary substrate during a final dicing step. The split substrate124can therefore be composed of any two suitable electrically conductive components126and128having electrical traces which are placed adjacent to each other having a selected space134therebetween to receive the flip-chip assembly of dies104and102.

In one embodiment, the ball pads132extend from the bottom of substrates126and128as shown. In another embodiment, they are flush with the bottom of substrates126and128and do not extend past the bottom surface. Namely, they are recessed into the substrates instead of extending out of them.

An underside130of the split substrate124further includes solder ball pads132for electrically coupling to a ball grid array as described below. The solder ball pads132are thus made of a conductive material that bonds with solder, such as a metal typically used for interconnect circuitry, e.g., copper, aluminum, AlCu alloys, and the like. The left and right substrate portions126and128of the split substrate124are spaced apart from one another by a gap134, over which the first IC chip102is suspended such that the first IC chip102extends into the gap134.

At136, the left and right substrate portions126and128of the split substrate124can be joined using an adhesive138to bridge the gap134. The adhesive can be attached to the underside130of each of the left and right substrate portions126and128. The adhesive138can be an adhesive tape such as an acrylic tape. Alternatively, the adhesive138can be an adhesive film that is deposited or dispensed as a liquid and then cured, such as polyimide film. The adhesive138can have a thickness of about 200 μm so that it covers and protects the solder ball pads132. The resulting structure shown inFIG. 3Bcan be structured as a two-die or a four-die multi-chip stack139. Alternatively, the structure shown inFIG. 3Bcan be a four-die multi-chip stack.

In one embodiment, substrate portions126and128merely provide electrical conductivity from the flip-chip arrangement to the solder ball pads132. Alternatively, in the embodiment shown, substrates126and128are active electrical die which contain logic circuits, and thus provide an additional two die in the multi-chip stack139, making, in the example shown inFIG. 3B, a four-die multi-chip stack139.

With reference toFIGS. 4A,4B, and4C, at140, a third integrated circuit chip142can optionally be stacked on top of the second IC chip104and secured with a first glue layer144, e.g., a conventional die film attach (DAF) adhesive material. Such a material is available from, for example, the Dow Corning Corporation of Midland, Mich. The resulting structure shown inFIG. 4Bis a three-die multi-chip stack145.

At146, a fourth integrated circuit chip148can optionally be stacked on top of the third IC chip142and secured with a second glue layer150. Desirably, each of the first, second, third, and fourth IC chips are placed so that they are approximately centered laterally about a central axis152. The third and fourth IC chips142and148can provide additional functionality to the overall multi-chip electronic device. The resulting structure shown inFIG. 4Cis a six-die multi-chip stack154; however, it can be a three- or four-die stack if split substrate portions126and128are not die and if die142is merely an interposer board. In some embodiments, additional IC chips can be added to the four-die multi-chip stack154.

With reference toFIGS. 5A and 5B, at156the multi-chip stack154can be cured using a standard electronic package curing technique which can set the glue (e.g., DAF).

At158, wire bonds160can be attached between some or all of the IC chips (e.g.,104,142, and148) that are joined by the glue layers, (e.g.,144and150). Additional wire bonds162can be attached between such IC chips and the split substrate124.

In the example shown inFIG. 5B, bond wires160are shown going from a top die148to an intermediate die142. Of course, the bonding wires160could extend from the top die148all the way to the split substrate126and128. In the embodiment in which the split substrate126and128are composed of fully functional integrated circuit dies, the placement of the bonding wires on the split substrate portions126and128will be to the appropriate bonding pads and will provide for interconnection of the electrical functionality of the six-die with respect to each other, thus drastically reducing the electrical interconnection that must take place outside of the packaged stack. For example, if die142is a highly complex microprocessor, and dies126and128contain memory chips for interaction with the processor, then all the interconnections between the processor and the memory can take place inside the encapsulated package. Encapsulated signals are fed out through the bond pads120of the split substrate portions126and128. Some of the bond pads120may be processed directly to the microprocessor die142, while others provide address and data pins to the memory circuits126and128.

The designer of the die can use their design skills to select the location and type of die to be used in the multi-chip package. For example, in some instances it may be desired to have the bonding pads on the memory chips as in the example shown inFIG. 5B, with separate die126and128. Alternatively, the die126and128may be simply A-D converters which convert analog data in some portions to digital data so that it may be handled by the digital logic circuits on the respective die142and148in the package. Alternatively, the split substrate portions126and128may be merely interconnection substrates that contain trace lines in order to provide electrical connection to the bonding pads132and do not, in and of themselves, contain any transistors or other integrated circuit components.

FIGS. 6A and 6Bdescribe an encapsulation process164that can be facilitated by the presence of the adhesive138. At164, an encapsulant166(e.g., a molding compound) can be set to flow around the multi-chip stack154so as to fill space surrounding the multi-chip stack154, including filling the gap134underneath the multi-chip stack154, referred to by the term underfill. Achieving a successful underfill, in which a viscous liquid encapsulant reaches and fills interstitial spaces around the multi-chip stack154, is facilitated by the adhesive138providing containment of the encapsulant. If the split substrate carrier is a unitary substrate, such as a hollow substrate, the adhesive138can provide reinforcement to the underside of the hollow substrate carrier, which reinforced containment can prevent warpage, or alternatively, no adhesive138is used. Such containment or reinforced containment ensures that the volume of encapsulant is not reduced by leakage through the gap134. Furthermore, containment by the adhesive138in particular ensures that the volume of encapsulant166is not reduced by the encapsulant creeping around the split substrate124to the underside130of the split substrate124. Still further, use of the adhesive138protects the solder ball pads132from coming into contact with the encapsulant166. Contact of the solder ball pads132with the encapsulant166may chemically contaminate the solder ball pads132, which could compromise their electrical conductivity. Additionally or alternatively, contact of the solder ball pads132with the encapsulant166may leave behind a residue that could compromise electrical conductivity by blocking or restricting current flow at the surface of the solder ball pads132. Use of the adhesive138can address these concerns.

The encapsulation process164can be further facilitated by judicious placement of the multi-chip stack154with respect to the gap134. In particular, achieving a successful underfill of the encapsulant166into the gap134depends on passing the encapsulant166through a narrow entrance168between the suspended first IC chip102and the split substrate124, the narrow entrance168being about 0.1 μm wide. Thus, control and selection of the dimensions of the first and second IC chips102and104during the wafer sawing process114can be a factor affecting underfill. In addition, accurate and precise registration of the first IC chip102relative to the second IC chip104during the flip-chip die attach process116can also be a factor affecting the underfill. Furthermore, accurate and precise registration of the inverted flip-chip die arrangement100relative to the split substrate124during the attachment process123can be a factor affecting the underfill.

An encapsulant166having a lower viscosity may be used to improve underfill capability. Typically, the flip-chip die attach process uses a specialized molding compound. Molding compounds are typically made of polymer resin, composed of 80%-90% fillers having diameters within the range of about 55-75 μm. With the use of a hollow substrate carrier, an ordinary molding compound can be used instead. Ordinary molding compounds tend to have a smaller filler size or a distribution of fillers that improves flowability through the narrow entrance168.

It is noted that the narrow entrance168might experience a large degree of mechanical stress, which can be observed during thermal cycling. One reason for such stress may be a difference in the coefficients of thermal expansion for different materials such as silicon, solder, and molding compound that may all be present near the narrow entrance168. When encapsulant is present at the narrow entrance168and replaces the substrate material in the gap134, the encapsulant can absorb and thereby reduce some of the mechanical stress.

The encapsulating process164may optionally include one or more curing steps that accelerate solidification of the encapsulant166, depending on the encapsulant material used. The curing steps may occur at any process step following the encapsulation step.

At170, once the encapsulant is stable, the adhesive138can be removed. If the adhesive138is an adhesive tape, the tape may be removed by manually pulling off the tape. If the adhesive138is an adhesive film such as, for example, a polyimide film, the adhesive138may be removed, for example, either by peeling off the adhesive film, or by dissolving the adhesive film in a fluid remover. If the adhesive film material is photo-sensitive, the fluid remover can be a developer. Otherwise, the fluid remover can be a wet chemical etchant or a plasma etchant. A final thickness174of the packaged multi-chip electronic device can be about 600 μm. This final thickness represents a significant reduction in thickness of over 50% or more, compared with available electronic packages for a four-die multi-chip stack154. It may be a reduction of over 100% for a six-die stack. Such a reduction in thickness provides flexibility to either include an additional die or simply provide a thinner packaged product.

At172, solder balls176can be attached to the underside130of the split substrate124at the protected surfaces of the solder ball pads132using a conventional attach process. The solder balls176can be in the form of a ball grid array (BGA) or a land grid array (LGA). The solder balls176can have a diameter of about 250 μm.