METHOD FOR MANUFACTURING SEMICONDUCTOR MEMBER

There is provided a method for manufacturing a semiconductor member, the method including: preparing a processing target comprising a wafer composed of a conductive semiconductor and a mask disposed on a top surface of the wafer; and photoelectrochemically etching the wafer by immersing the processing target in an etching solution and irradiating light from a top surface side of the wafer, wherein in the photoelectrochemical etching of the wafer, an outer portion of the mask of the wafer is etched to form a protrusion under the mask, and a first side surface and a second side surface are etched until an entire width between the mutually opposing first side surface and second side surface of the protrusion is depleted, to automatically stop the etching of the first side surface and the second side surface.

TECHNICAL FIELD

The present invention relates to a method for manufacturing a semiconductor member.

DESCRIPTION OF RELATED ART

A semiconductor member with a structure formed in a semiconductor material is widely used in a semiconductor element and the like. For example, a fin field effect transistor with a fin structure formed as a gate portion is known (for example, see Patent literature 1). For example, a structure used in a semiconductor element is preferably formed in a precise shape because it affects operating characteristics of the device. Patent Literature 1: International Publication No. 2017/047286

SUMMARY OF THE INVENTION

One object of the present invention is to provide a novel method for manufacturing a semiconductor member used in a semiconductor element and the like.

According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor member, the method including:preparing a processing target comprising a wafer composed of a conductive semiconductor and a mask disposed on a top surface of the wafer; andphotoelectrochemically etching the wafer by immersing the processing target in an etching solution and irradiating light from a top surface side of the wafer,wherein in the photoelectrochemical etching of the wafer,an outer portion of the mask of the wafer is etched to form a protrusion under the mask, anda first side surface and a second side surface are etched until an entire width between the mutually opposing first side surface and second side surface of the protrusion is depleted, to automatically stop the etching of the first side surface and the second side surface.

A novel method for manufacturing a semiconductor member

used in a semiconductor element and the like is provided.

DETAILED DESCRIPTION OF THE INVENTION

A method for manufacturing a semiconductor member according to an embodiment of the present invention will be described. Here, explanation will be given by citing a field effect transistor (FET), which is a semiconductor element, as an example of the semiconductor member according to an embodiment. The semiconductor member according to the embodiment may include only a semiconductor member, or as in this example, it may include a semiconductor member and other member such as an electrode. Further, the use of the semiconductor member manufactured by the manufacturing method of the embodiment does not have to be limited to FET.

The structure and operation of the FET100according to the embodiment will be described for example.FIGS.1A and1Bare a cross-sectional view and a top view, respectively, schematically illustrating the FET100according to an embodiment. The FET100includes a semiconductor member10, a gate electrode20, a source electrode30, and a drain electrode40. The FET100may include other member such as an insulating film as necessary.

The semiconductor member10is composed of a semiconductor material having conductivity by containing an n-type conductive impurity (hereinafter also simply referred to as an impurity) at a predetermined concentration. As the semiconductor material constituting the semiconductor member10, a material that can be etched by photoelectrochemical (PEC) etching can be used as appropriate, and for example, gallium nitride (GaN), silicon carbide (SiC), etc., are used. In addition to a wide gap semiconductor such as GaN, a conventional compound semiconductor such as gallium arsenide (GaAs) and indium phosphide (InP) may be used. Here, explanation will be given, using GaN containing an n-type impurity such as silicon (Si) as an example of the semiconductor material constituting the semiconductor member10.

The semiconductor member10used in the FET100of this example includes a substrate11and a layer12epitaxially grown on the substrate11(hereinafter referred to as a drift layer12). A protrusion16(hereinafter referred to as a gate protrusion16) is formed on the drift layer12by the manufacturing method (processing method) according to the embodiment, specifically, by PEC etching. The gate protrusion16has a width W (seeFIG.3C). As will be described in detail later, the width W of the gate protrusion16is determined by the carrier concentration of the drift layer12. In other words, the carrier concentration of the drift layer12, that is, the impurity concentration added to the drift layer12, is set so that a predetermined width W can be obtained.

For example, by setting the carrier concentration of the drift layer12to about 1×1016/cm3, the width W of the gate protrusion16can be set to 600 nm (seeFIG.6A). By lowering the carrier concentration of the drift layer12, the width W of the gate protrusion16can be widened, and by increasing the carrier concentration of the drift layer12, the width W of the gate protrusion16can be narrowed (seeFIG.6A). The width W of the gate protrusion16(more specifically, the width W of the narrowest portion of the gate protrusion16) is preferably 200 nm or more and 2000 nm or less. The carrier concentration of the drift layer12is set so that the width W of the gate protrusion16falls within such a range. Depending on the semiconductor material used (because the width of the depletion layer depends on the dielectric constant of the semiconductor material), the relationship between the carrier concentration of the drift layer12and the width W of the gate protrusion16may be varied to some extent. The precise relationship between the carrier concentration of the drift layer12and the width W of the gate protrusion16in the used semiconductor material may be determined, for example, by a preliminary experiment, and the carrier concentration of the drift layer12may be set based on the determined precise relationship.

The gate protrusion16is formed on the top surface of the semiconductor member10, that is, on the top surface of the drift layer12, and a recess15(hereinafter referred to as a gate recess15) is formed on the outer side of the gate protrusion16(in planer view).

The gate recess16functions as a gate portion of the FET100. In this example, the FET100is a FinFET, and as illustrated inFIG.1B, the gate protrusion16(hatched portion upward to the right) has a fin-like (linear) shape.

The height of the gate protrusion16(that is, the depth of the gate recess15) may be set as appropriate, and is, for example, about1um. The height of the gate protrusion16is the thickness of the gate portion in a current flow direction, and when it is too thin (too low), it is not preferable from a viewpoint of a current control. Therefore, it is preferable that the height of the gate protrusion16, that is, the depth of PEC etching when forming the gate protrusion16, is, for example, 500 nm or more.

A gate electrode20is disposed on the inner surface of the gate recess15and at least on the side surface of the gate protrusion16. The gate electrode20is disposed on one side surface of the gate protrusion16and on the other side surface opposite to this side surface so as to sandwich the side portion of the gate protrusion16from both sides. The gate electrode20is connected to a gate pad21disposed on the top surface of the semiconductor member10, and connected to an external circuit via the gate pad21.

A gate voltage is applied to the side surface of the gate protrusion16by the gate electrode20. By controlling the gate voltage, the carrier distribution within the gate protrusion16is changed to switch the FET100between the ON state and the OFF state. As will be described later in detail, since the gate protrusion16formed by the manufacturing method of the embodiment is fully depleted, the FET100is of a normally-off type. That is, the ON operation of applying a predetermined positive voltage to the gate electrode20increases the number of electrons in the gate protrusion16, and the FET100can be set in the ON state.

FIGS.1A and1Billustrate a Schottky-type gate electrode structure in which the gate electrode20is disposed directly on the side surface of the gate protrusion16. However, if necessary, a MOS type gate electrode structure may be used in which the gate electrode20is disposed on the side surface of the gate protrusion16with a gate insulating film interposed therebetween.

A source electrode30is disposed on the top surface of the gate protrusion16(on one side of the gate protrusion16in a vertical direction). The source electrode30is connected to a source pad31disposed on the top surface of the semiconductor member10, and connected to an external circuit via the source pad31. A drain electrode40is disposed on the bottom surface of the semiconductor member10, that is, on the bottom surface of the substrate11(on the other side of the gate protrusion16in the vertical direction).

By applying a gate voltage to the gate electrode20and setting the FET100in the ON state while a predetermined voltage is applied between the source electrode30and the drain electrode40, the FET100can be operated so that a drain current flows in a thickness direction (vertical direction) of the semiconductor member10.

A method for manufacturing the FET100will be described for example. The gate protrusion16is formed on the top surface of a flat semiconductor member10a (hereinafter referred to as a wafer10a) on which the gate protrusion16has not yet been formed (on the top surface of the drift layer12). The semiconductor member10is obtained by forming the gate protrusion16on the wafer10a. The method for manufacturing the FET100according to the embodiment is characterized in that the gate protrusion16is formed by PEC etching, as will be described later in detail.

Thereafter, appropriately using a known technique for patterning a metal film, a known technique for patterning an insulating film, etc., the FET100is manufactured by forming the gate electrode20, source electrode30, drain electrode40, and other member such as an insulating film on the semiconductor member10.

The step of forming the gate protrusion16by PEC etching will be described in detail.FIG.2Ais a cross-sectional view schematically illustrating a processing target150in PEC etching according to the embodiment. The processing target150includes a wafer10a and a mask160. The wafer10a includes the substrate11and the drift layer12, as described above. The mask160is disposed on the top surface of the wafer10a(on the top surface of the drift layer12) in a region where the gate protrusion16is to be formed. As the mask160, a resist mask, a hard mask, etc., may be used as appropriate. It is preferable that the mask160has a light-shielding property that does not transmit light231irradiated in PEC etching, which will be described later.

FIG.2Bis a cross-sectional view schematically illustrating the PEC etching apparatus200according to the embodiment. An etching solution (electrolyte)220is contained in a container210, and the processing target150is immersed in the etching solution220. A processing target side electrode241is disposed on the bottom surface of the wafer10a (on the bottom surface of the substrate11), and the processing target150is immersed in the etching solution220while the object-side electrode241and the bottom and side surfaces of the wafer10a are covered with a coating member244such as a resist so as not to be exposed to the etching solution220(so as not to make electrical contact with the etching solution220). Thereby, an opening region of the mask160on the top surface of the wafer10a (on the top surface of the drift layer12) is selectively exposed to the etching solution220.

As the etching solution220, an etching solution capable of PEC etching the semiconductor material constituting the wafer10a (more specifically, the semiconductor material constituting the drift layer12), may be used as appropriate (potassium hydroxide aqueous solution, phosphoric acid aqueous solution, etc.). The etching solution220may be alkaline or acidic as necessary. As will be described later, the pH of the etching solution220is appropriately adjusted according to the width W of the gate protrusion16, and the etching solution220corresponding to a suitable pH is used.

One end of a wiring242(covered with insulation) is connected to the processing target side electrode241. An etching solution side electrode243is attached to the other end of the wiring242, and the etching solution side electrode243is immersed in the etching solution220. A voltage source240is disposed in the middle of the wiring242. The voltage source240applies a predetermined etching voltage for performing PEC etching, between the processing target side electrode241and the etching solution side electrode243, that is, between the wafer10aand the etching solution220.

With an etching voltage applied between the wafer10aand the etching solution220, light231for performing PEC etching is irradiated from the light source230onto the top surface of the wafer10a, that is, the top surface of the drift layer12, which is the surface to be etched. In this way, PEC etching is performed to the wafer10a.

FIGS.3A to3Care schematic cross-sectional views illustrating portions of the wafer10a and the semiconductor member10near the mask160during PEC etching according to an embodiment. SeeFIG.3A. As the etching voltage, a voltage that is positive on the wafer10a side and negative on the etching solution220side is applied. Light231is irradiated, having a wavelength corresponding to a larger energy than the bandgap of the semiconductor material constituting the top surface of the wafer10a, which is the region to be etched.

A depletion layer10D (hatched portion upward to the right) is formed on the top surface of the wafer10a. Due to optical excitation caused by irradiation of the light231onto the upper surface of the wafer10a, pairs of electrons and holes are generated in the surface layer of the top surface. Due to a negative voltage applied to the etching solution220, the holes are guided to the top surface side of the wafer10a(etching solution220side). Etching progresses as the semiconductor material is oxidized by the holes and an oxide is dissolved in the etching solution. In an example where the wafer10ais composed of GaN, etching progresses in such a manner that GaN is decomposed into gallium (Ga) and nitrogen (N) by the holes, gallium is oxidized by oxygen contained in the etching solution220to generate gallium oxide, and gallium oxide is dissolved in an acidic or alkaline etching solution220. Electrons generated in pairs with holes are guided to the bottom surface side of the wafer10a.

SeeFIG.3B. By etching the outer portion of the mask160of the wafer10a(in planer view) to form the gate recess15, the gate protrusion16is formed under the mask160(the gate protrusion16remains under the mask160.) As the etching of the bottom surface of the gate recess15progresses (as the gate recess15becomes deeper), the etching of the side surface of the gate protrusion16, which is the side surface of the gate recess15, also progresses. That is, the etching of the mutually opposing side surfaces16aand16bof the gate protrusion16progresses, and the width of the gate protrusion16becomes narrower.

It is preferable that the light231has a light component that is obliquely incident on the top surface of the wafer10aso that the side surface16aand the side surface16bof the gate protrusion16are easily irradiated with the light231. Further, by etching the side surfaces16aand16b, the width of the gate protrusion16becomes narrower than the width of the mask160. Therefore, it is preferable to form the mask160with a width slightly wider than a final width W of the gate protrusion16desired to be obtained.

The holes move by diffusing a non-depleted region of the wafer10a. At the stage where the width of the gate protrusion16is sufficiently wide, specifically, in the gate protrusion16, at the stage where the non-depleted region remains between the depletion layer10D formed on the side surface16aand the depletion layer10D formed on the side surface16b, etching of the side surfaces16aand16bprogresses as the holes move through the non-depleted region.

SeeFIG.3C. Since the holes can no longer move at a stage when the width of the gate protrusion16is narrowed to a width W which is a width corresponding to the depletion layer10D formed over an entire width of the gate protrusion16, the etching of the side surfaces16aand16bis automatically stopped.

After the width of the gate protrusion16reaches the width W and the etching of the side surfaces16aand16bstops, and when the etching progresses until the depth of the gate recess15reaches a predetermined depth, the PEC etching is completed by stopping the irradiation of the light231.

The FET100in this example is a FinFET, and the mask160includes a linear portion (in planer view). In the step of the PEC etching, the gate protrusion16is formed, including a linear portion having a width W of 200 nm or more and 2000 nm or less at the narrowest portion (in planer view).

As described above, the step of forming the gate protrusion16by PEC etching (method for manufacturing the semiconductor member10according to the embodiment) includes the step of preparing the processing target150, and the step of performing PEC etching to the wafer10a by immersing the processing target150in the etching solution220and irradiating the wafer10a with light231from the top surface side.

In the step of PEC etching the wafer10a, by etching the outer portion of the mask160of the wafer10a, the gate protrusion16is formed under the mask160, and by etching the side surfaces16aand16buntil the entire width between the mutually opposing side surfaces16aand16bof the gate protrusion16is depleted, the etching of the side surfaces16aand16bis automatically stopped.

The width W of the gate protrusion16formed according to the embodiment is determined by the width of the depletion layer10D. As will be described below, the width of the depletion layer10D is determined by the carrier concentration of the semiconductor member10, more specifically, the carrier concentration of the portion where the gate protrusion16is formed (drift layer12in this example), and the pH of the etching solution220. Accordingly, even when there is an error in the size of the mask160, the width W of the gate protrusion16can be precisely controlled by the carrier concentration and the pH of the etching solution220.

In a FinFET type power device, a threshold voltage for switching on/off is determined by the width W of the gate protrusion16which is the gate portion. Therefore, it is preferable to precisely control the width W. The preferable width W is estimated as follows.

An example of a Schottky gate electrode structure in which the semiconductor member10is composed of GaN and the gate electrode20is composed of gold (Au) will be shown for example. The depletion layer width Wp in a Schottky junction is represented by the following formula1.

Wherein εris a relative dielectric constant 9.5 of GaN, ε0is a dielectric constant 8.85×10−12F/m of vacuum, Φbiis a built-in potential, V is an applied voltage, q is an elementary charge 1.60×10−19C, and n is a carrier concentration of GaN.

The built-in potential Φbiis represented by the following formula2.

wherein ΦBis a Schottky barrier 1 eV in the contact between GaN and Au, k is a Boltzmann constant 1.38×10−23J/K, t is an absolute temperature 300 K, and NCis an effective state density 2.59×1024/m3of a GaN conduction band.

Since the width W of the gate protrusion16is formed to be twice the depletion layer width WD, the entire width of the gate protrusion16is depleted when the voltage V is applied to the gate electrode20. FIG.

6A is a table showing the dependence of a value twice the depletion layer width WD(that is, a value of the width W of the fully depleted gate protrusion16) at each carrier concentration n, on the applied voltage V when the Schottky barrier ΦBis 1 eV.

The carrier concentration n is varied to 5×1015/cm3, 8×1015/cm3, 1×1016/cm3, and 2×1016/cm3. The applied voltage V is varied from +0.2V to −0.35V in steps of 0.05V (50 mV). The width W is shown in unit of nm. A GaN power device with a withstand voltage of 2.5 kV when the carrier concentration n is 5×1015/cm3, and a GaN power device with a withstand voltage of 1.5 kV when the carrier concentration n is 1×1016/cm3, can be realized.

Regarding a specific carrier concentration n, when the width W of the gate protrusion16is the value shown in this table, the FinFET reaches exactly the OFF state at the applied voltage V. That is, this applied voltage V is a threshold value. For example, when the carrier concentration n is 1×1016/cm3, the width W is 600 nm, and the applied voltage V is 0, the entire width W is depleted and the FinFET is set in the OFF state.

A design in which the FinFET is set exactly in the OFF state (pinch-off) when the applied voltage V is 0, will be considered.FIG.6Bis a table showing the allowable error of the width W of the gate protrusion16when the allowable error of the threshold value is ±50 mV and ±100 m V. When the allowable error of the threshold voltage is ±50-100 mV, the allowable error of the width W of the gate protrusion 16 is ±10-50 nm. It is very difficult to suppress the allowable error of the width W of the gate protrusion16to such a low level using conventional lithography.

In the embodiment, the gate protrusion16is formed by PEC etching, as described above. A barrier height of the semiconductor member10in contact with the etching solution220is controlled by pH of the etching solution220. Accordingly, the depletion layer width WDin PEC etching, that is, the width W of the gate protrusion16to be formed, is controlled by the pH of the etching solution220.

More specifically, by adjusting the pH of the etching solution

220so as to be equivalent to the Schottky barrier ΦBin a Schottky electrode structure to be produced, the depletion layer width WDin PEC etching can be adjusted to be equal to the depletion layer width WDin the case of the applied voltage of V=0 in the Schottky electrode structure. In this way, it is possible to form the gate protrusion16having the width W so as to be exactly set in the OFF state at the applied voltage V of0when the Schottky electrode structure is formed.

As described above, the width W of the gate protrusion16according to the embodiment can be precisely controlled by the carrier concentration n and the pH of the etching solution220. With a current growth technique, wafer in-plane variation in the carrier concentration n can be suppressed to about ±2% on average. For example, when the carrier concentration n is 1×1016/cm3±2%, the wafer in-plane allowable error in the width W is ±6 nm and can be ±10 nm or less.

For example, in a comparative embodiment in which the gate protrusion16is formed using a combination of ultraviolet lithography using a stepper and dry etching, the yield of the element remains at about 50%. In contrast, in the gate protrusion 16 formed by the PEC etching of the embodiment as described above, the allowable error in the width W can be suppressed to ±10 nm or less. Therefore, the yield can be improved.

In the comparative embodiment using dry etching, there is a concern that damage to a semiconductor crystal may occur due to dry etching.

In contrast, in the embodiment, since the gate protrusion16is formed by PEC etching, which is wet etching, damage to the semiconductor crystal is suppressed. Further, in the embodiment, the width W can be determined by automatically stopping etching in a width direction of the gate protrusion16. Further, in the embodiment, since the fully depleted gate protrusion16can be formed, the obtained FET100can be of a normally-off type.

Next, a FET100according to a modified example of the above-described embodiment will be described.FIGS.4A and4Bare a cross-sectional view and a top view, respectively, schematically illustrating the FET100according to a first modified example.

In the embodiment described above, the FET100having a Schottky type (or MOS type) gate electrode structure is shown for example. The gate electrode structure is not limited thereto. As a first modified example, an FET100having a pn-type gate electrode structure will be shown for example.

In the first modified example, the gate recess15is filled with a semiconductor layer13(hatched portion upward to the left) of a conductivity type (that is, p-type) opposite to that of the drift layer12. The gate electrode20is formed on the semiconductor layer13. The gate voltage is applied via the semiconductor layer13to the pn junction formed by the semiconductor layer13and the gate protrusion16.

Regarding the method for manufacturing the FET100according to the first modification, the steps up to the step of forming the gate protrusion16are the same as in the above-described embodiment. After forming the gate protrusion16, the semiconductor layer13is formed, for example, by regrowth. If necessary, polishing may be performed to flatten the top surface of the semiconductor member10on which the semiconductor layer13has been grown. Thereafter, the FET100according to the first modified example is manufactured by forming the gate electrode20, the source electrode30, the drain electrode40, and other member such as an insulating film on the semiconductor member10.

FIG.5is a top view schematically illustrating the FET100according to the second modified example. In the above-described embodiment, the FET100having a fin-shaped (linear) gate protrusion16was shown for example. The shape of the gate protrusion16is not limited thereto. As a second modified example, the FET100(nanorod transistor) having a rod-shaped (island-shaped) gate protrusion16is shown for example. In the nanorod transistor, the gate electrode20is formed to surround an entire circumference of the gate protrusion16(in planer view).

Regarding the method for manufacturing the FET100according to the second modified example, the step of forming the gate protrusion16is different from the above-described embodiment. In this example, the mask160includes an island-shaped portion (in planer view). In the PEC etching step, the gate protrusion16is formed, including an island-shaped portion having a width W of 200 nm or more and 2000 nm or less at the narrowest portion (in planer view). After forming the gate protrusion16, by forming the gate electrode20, the source electrode30, the drain electrode40, and other member such as an insulating film on the semiconductor member10, the FET100according to the second modified example is manufactured.

Regarding the FET100according to the first modified example and the second modified example, similarly to the embodiments described above, advantages are the same, such as the ability to precisely control the width W by forming the fully depleted gate protrusion16by PEC etching.

<Preferable Aspects of the Present Invention>

Hereinafter, preferable aspects of the present invention will be supplementarily described.

A method for manufacturing a semiconductor member, the method including:preparing a processing target comprising a wafer composed of a conductive semiconductor and a mask disposed on a top surface of the wafer; andphotoelectrochemically etching the wafer by immersing the processing target in an etching solution and irradiating light from a top surface side of the wafer,wherein in the photoelectrochemical etching of the wafer,an outer portion of the mask of the wafer is etched to form a protrusion under the mask, anda first side surface and a second side surface are etched until an entire width between the mutually opposing first side surface and second side surface of the protrusion is depleted, to automatically stop the etching of the first side surface and the second side surface.

The method for manufacturing a semiconductor member according to supplementary description 1,wherein the mask includes a linear portion, andin the photoelectrochemical etching the wafer, the protrusion including the linear portion having a narrowest width of 200 nm or more and 2000 nm or less is formed.

The method for manufacturing a semiconductor member according to supplementary description1,wherein the mask includes an island-shaped portion, andin the photoelectrochemical etching of the wafer, the protrusion including the island-shaped portion having a width of 200 nm or more and 2000 nm or less at a narrowest portion is formed.

The method for manufacturing a semiconductor member according to any one of supplementary descriptions 1 to 3, the method further including:forming a gate electrode that applies a gate voltage to a side surface of the protrusion, a source electrode disposed on one side of the protrusion in a vertical direction, and a drain electrode disposed on the other side of the protrusion in the vertical direction.