Uniform masking for wafer dicing using laser and plasma etch

Uniform masking for wafer dicing using laser and plasma etch is described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits having bumps or pillars includes uniformly spinning on a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

BACKGROUND

Embodiments of the present invention pertain to the field of semiconductor processing and, in particular, to methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon.

2) Description of Related Art

In semiconductor wafer processing, integrated circuits are formed on a wafer (also referred to as a substrate) composed of silicon or other semiconductor material. In general, layers of various materials which are either semiconducting, conducting or insulating are utilized to form the integrated circuits. These materials are doped, deposited and etched using various well-known processes to form integrated circuits. Each wafer is processed to form a large number of individual regions containing integrated circuits known as dice.

Following the integrated circuit formation process, the wafer is “diced” to separate the individual die from one another for packaging or for use in an unpackaged form within larger circuits. The two main techniques that are used for wafer dicing are scribing and sawing. With scribing, a diamond tipped scribe is moved across the wafer surface along pre-formed scribe lines. These scribe lines extend along the spaces between the dice. These spaces are commonly referred to as “streets.” The diamond scribe forms shallow scratches in the wafer surface along the streets. Upon the application of pressure, such as with a roller, the wafer separates along the scribe lines. The breaks in the wafer follow the crystal lattice structure of the wafer substrate. Scribing can be used for wafers that are about 10 mils (thousandths of an inch) or less in thickness. For thicker wafers, sawing is presently the preferred method for dicing.

With sawing, a diamond tipped saw rotating at high revolutions per minute contacts the wafer surface and saws the wafer along the streets. The wafer is mounted on a supporting member such as an adhesive film stretched across a film frame and the saw is repeatedly applied to both the vertical and horizontal streets. One problem with either scribing or sawing is that chips and gouges can form along the severed edges of the dice. In addition, cracks can form and propagate from the edges of the dice into the substrate and render the integrated circuit inoperative. Chipping and cracking are particularly a problem with scribing because only one side of a square or rectangular die can be scribed in the <110> direction of the crystalline structure. Consequently, cleaving of the other side of the die results in a jagged separation line. Because of chipping and cracking, additional spacing is required between the dice on the wafer to prevent damage to the integrated circuits, e.g., the chips and cracks are maintained at a distance from the actual integrated circuits. As a result of the spacing requirements, not as many dice can be formed on a standard sized wafer and wafer real estate that could otherwise be used for circuitry is wasted. The use of a saw exacerbates the waste of real estate on a semiconductor wafer. The blade of the saw is approximate 15 microns thick. As such, to insure that cracking and other damage surrounding the cut made by the saw does not harm the integrated circuits, three to five hundred microns often must separate the circuitry of each of the dice. Furthermore, after cutting, each die requires substantial cleaning to remove particles and other contaminants that result from the sawing process.

Plasma dicing has also been used, but may have limitations as well. For example, one limitation hampering implementation of plasma dicing may be cost. A standard lithography operation for patterning resist may render implementation cost prohibitive. Another limitation possibly hampering implementation of plasma dicing is that plasma processing of commonly encountered metals (e.g., copper) in dicing along streets can create production issues or throughput limits.

SUMMARY

Embodiments of the present invention include methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon.

In an embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits having bumps or pillars includes uniformly spinning on a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

In an embodiment, a system for dicing a semiconductor wafer having a plurality of integrated circuits includes a factory interface. A laser scribe apparatus is coupled with the factory interface. A plasma etch chamber is coupled with the factory interface. A deposition chamber is coupled with the factory interface. The deposition chamber is for uniformly spinning on a mask above a semiconductor wafer.

In an embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves uniformly spinning on a mask above a silicon substrate. The mask is composed of a layer covering and protecting integrated circuits disposed on the silicon substrate. The integrated circuits include metal bumps or pillars disposed above a layer of low K material. The method also involves patterning the mask and the layer of low K material with a laser scribing process to expose regions of the silicon substrate between the integrated circuits. The method also involves etching the silicon substrate through the exposed regions to form singulated integrated circuits.

DETAILED DESCRIPTION

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon, are described. In the following description, numerous specific details are set forth, such as femtosecond-based laser scribing and plasma etching conditions and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known aspects, such as integrated circuit fabrication, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

A hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch may be implemented for die singulation. The laser scribe process may be used to cleanly remove a mask layer, organic and inorganic dielectric layers, and device layers. The laser etch process may then be terminated upon exposure of, or partial etch of, the wafer or substrate. The plasma etch portion of the dicing process may then be employed to etch through the bulk of the wafer or substrate, such as through bulk single crystalline silicon, to yield die or chip singulation or dicing.

One or more embodiments described herein are directed to approaches for spin coating for uniform masking on bumps/metal pillars and saw street/wafer field for wafer dicing. In the phase of IC chip singulation, the IC chips typically bear a polymer film layer (e.g., polyimide) on the die surface for the purposes of stress relieving and mask around bump pads. Hence, for the laser scribing plus plasma etch dicing processing, a mask layer is typically required to be added on top of the wafer undergoing singulation. Such a mask layer will likely be removed following singulation. The removal, however, should be performed without damaging or contaminating any pre-existing polymer layer and bump pads on IC chips.

In addition to the above described possible need for masking material, it may be very challenging to achieve a balance between the thickness of a mask material coating on top of bumps/metal pillars and the dicing street. Using conventional spin coating processing, the mask material is typically coated thicker on the dicing street compared to the bump/metal pillar top portion. In order to achieve higher throughput for a laser scribing process performed prior to an etch process and maximum amount of material ablation during laser scribing, a more conformal coating may be required. However, development of a spin process may be required to provide uniform coating.

Conventional wafer dicing approaches include diamond saw cutting based on a purely mechanical separation, initial laser scribing and subsequent diamond saw dicing, or nanosecond or picosecond laser dicing. For thin wafer or substrate singulation, such as 50 microns thick bulk silicon singulation, the conventional approaches have yielded only poor process quality. Some of the challenges that may be faced when singulating die from thin wafers or substrates may include microcrack formation or delamination between different layers, chipping of inorganic dielectric layers, retention of strict kerf width control, or precise ablation depth control. Embodiments of the present invention include a hybrid laser scribing and plasma etching die singulation approach that may be useful for overcoming one or more of the above challenges.

In accordance with an embodiment of the present invention, a combination of laser scribing (e.g., femtosecond-based) and plasma etching is used to dice a semiconductor wafer into individualized or singulated integrated circuits. In one embodiment, femtosecond-based laser scribing is used as an essentially, if not totally, non-thermal process. For example, the femtosecond-based laser scribing may be localized with no or negligible heat damage zone. In an embodiment, approaches herein are used to singulated integrated circuits having ultra-low k films. With convention dicing, saws may need to be slowed down to accommodate such low k films. Furthermore, semiconductor wafers are now often thinned prior to dicing. As such, in an embodiment, a combination of mask patterning and partial wafer scribing with a femtosecond-based laser, followed by a plasma etch process, is now practical. In one embodiment, direct writing with laser can eliminate need for a lithography patterning operation of a photo-resist layer and can be implemented with very little cost. In one embodiment, through-via type silicon etching is used to complete the dicing process in a plasma etching environment.

Thus, in an aspect of the present invention, a combination of femtosecond-based laser scribing and plasma etching may be used to dice a semiconductor wafer into singulated integrated circuits.FIG. 1illustrates a top plan of a semiconductor wafer to be diced, in accordance with an embodiment of the present invention.FIG. 2illustrates a top plan of a semiconductor wafer to be diced that has a dicing mask formed thereon, in accordance with an embodiment of the present invention.

Referring toFIG. 1, a semiconductor wafer100has a plurality of regions102that include integrated circuits. The regions102are separated by vertical streets104and horizontal streets106. The streets104and106are areas of semiconductor wafer that do not contain integrated circuits and are designed as locations along which the wafer will be diced. Some embodiments of the present invention involve the use of a combination femtosecond-based laser scribe and plasma etch technique to cut trenches through the semiconductor wafer along the streets such that the dice are separated into individual chips or die. Since both a laser scribe and a plasma etch process are crystal structure orientation independent, the crystal structure of the semiconductor wafer to be diced may be immaterial to achieving a vertical trench through the wafer.

Referring toFIG. 2, the semiconductor wafer100has a mask200deposited upon the semiconductor wafer100. In one embodiment, the mask is spun on to achieve an approximately 20-150 micron thick layer. The mask200and a portion of the semiconductor wafer100are patterned with a laser scribing process to define the locations (e.g., gaps202and204) along the streets104and106where the semiconductor wafer100will be diced. The integrated circuit regions of the semiconductor wafer100are covered and protected by the mask200. The regions206of the mask200are positioned such that during a subsequent etching process, the integrated circuits are not degraded by the etch process. Horizontal gaps204and vertical gaps202are formed between the regions206to define the areas that will be etched during the etching process to finally dice the semiconductor wafer100.

FIG. 3is a Flowchart300representing operations in a method of dicing a semiconductor wafer including a plurality of integrated circuits, in accordance with an embodiment of the present invention.FIGS. 4A-4Gillustrate cross-sectional views of a semiconductor wafer including a plurality of integrated circuits during performing of a method of dicing the semiconductor wafer, corresponding to operations of Flowchart300, in accordance with an embodiment of the present invention.

Referring to operation302of Flowchart300, and correspondingFIGS. 4A-4D, a mask402is formed above a semiconductor wafer or substrate404. The mask402is composed of a layer covering and protecting integrated circuits including metallic bumps or pillars499formed on the surface of semiconductor wafer404. Specifically, in an embodiment, referring toFIG. 4A, a 300 mm wafer404is held in pace by a vacuum wafer chuck498. A mask forming material (e.g., coating material)490is dispensed by manual or auto dispensing, as depicted inFIG. 4B. Referring toFIG. 4C, clockwise480and anti-clockwise481rotation of vacuum wafer chuck498is performed, e.g., using machine control software. As a result, the mask forming material490is uniformly dispensed across the top surface of wafer404to provide a uniform mask coating495, as depicted inFIG. 4D. The uniform mask coating495is uniform (e.g., entirely or essentially conformal) with saw streets, wafer fields and bumps/pillars499on the surface of wafer404.

Thus, in an embodiment, a method of spin coating for uniform masking on bumps/metal pillars and saw street/wafer field is provided. In one or more embodiment, such a mask layer enables up to 500 micron etch depth, is applicable to thin wafer (film+frame) scenarios, is applicable to pre-thin scenarios, provides for subsequent clean ablation with a laser, is applicable atop polyimide (PI) or molding compounds, is removable without oxidizing bumps/pillars, is removable without changing properties of under-layers, and/or has uniform thickness on the bump/metal pillar top and saw street.

In an embodiment, the applied mask layer on the bump/metal pillar wafer is ready for die singulation upon dispensing and forming of the conformal layer. By contrast, conventional die singulation methods, e.g., diamond saw, laser scribing, etc., use one step die singulation where a thin protective material is spin coated prior to die singulation to protect the bumps/metal pillars. In such approaches, there is not necessarily a need for having a uniform protective coating rather than merely providing protective layer of any thickness and topography. Uneven distribution of mask material on the bump/metal pillar top compared to the saw street does not a measurable difference in such convention dicing operations. On the other hand, in accordance with embodiments described herein, a laser scribe and plasma etch process generally involves a laser scribed wafer subjected to a plasma etch process. During the plasma etch process portion of the operation, the etchant used etches the silicon wafer on the saw street to singulate individual die and consumes generally an equal amount of mask material from the bump/metal pillar top and saw street. In one embodiment, a spinning method is used to provide balanced mask material in both locations and also to provide a uniform coating around circular shape bumps/metal pillars.

In an embodiment, a bubble-free coating is provided on a wafer and bump/pillar surface for a variety of coating viscosities. Coating materials having a range of possible viscosities may be applied on top of the bumped/pillar wafer using manual and automatic disense system. Conventionally, industry usage involves only clockwise or anticlockwise rotation which may result in a non-uniform coverage of coated material around the bumps or pillars. Specifically, centrifugal forces act on the coating material encounters during clockwise or anticlockwise rotation. In one embodiment, a combination of clockwise and anti-clockwise rotation with a periodic interval of time for every rotation is used to provide uniform coating of masking material including on the bump/pillar structures. In an embodiment, different thicknesses of the mask material are achieved by using different spinning speeds and coating materials of differing viscosity. In an embodiment, introduction of temperature bias on the coating material via the dispense system also affects uniformity of the coating on and around the bump/metallic pillar structures as well as the wafer field and saw street. The above described mask material dispense and spin condition may be applicable to coating material with water solubility and non-water solubility.

Advantages of the above uniform coating approach may include, but are not limited to, one or more of the ability to achieve good balance between mask functionality and process simplicity, e.g., the use of a water soluble film as a mask for ease of post etch mask removal, the ability to enable use of common low-cost water soluble materials, and the ability to provide uniform coating for protecting the metallic bump/pillar structures during the plasma etch process in a laser plus plasma die singulation process. The methods described herein may also be applicable to other semiconductor manufacturing processes having a need for uniform coating at the micron and sub-micron scale.

In an embodiment, in the context of a laser plus plasma die singulation process, a uniform mask coating is provided on approximately 30 to 50 micron copper interconnect bumps and approximately 50 micron tall copper pillar, e.g., on 300 mm wafers. In one embodiment, for a coating thickness of approximately 30 to 40 microns the uniformity achieved is approximately +/−10%, even over topography, which can be scaled down further with variation of mask material, chemical formulation, and, possibly, temperature. In one embodiment, the coating material for forming the uniform mask is water-soluble and is not photo-sensitive. In a specific embodiment, a polyvinyl alcohol (PVA) based material (e.g., with solid content) is used having a viscosity approximately in the range of the 100s to the 1000s of centipoises. In an embodiment, a uniform coating of approximately 20 microns is used for a laser plus plasma singulation process for an approximately 50 micron wafer with additional 50 micron bump height. In another embodiment, a uniform coating of approximately 35 microns is used for a laser plus plasma singulation process for an approximately 500 micron wafer with additional 50 micron bump height. In the latter case, however, a uniform coating as thick as approximately 150 microns may be used. In an embodiment, approximately 1 micron of uniform mask coating is consumed for every approximately 20-30 microns of etched silicon. In an embodiment, an optional ash between laser and etch processes consumes approximately 7-8 microns of uniform mask coating.

Referring toFIGS. 4E-4G, the etching portion of the dicing process is illustrated. For the sake of convenience, mask402and wafer404are depicted once again, but without the illustration of bumps and pillars. Instead, inFIG. 4E, intervening streets407formed between each of the integrated circuits406are emphasized. However, it is to be understood that the bumps/pillars499and uniform mask coating495are still contemplated in the following description.

In an embodiment, semiconductor wafer or substrate404is composed of a material suitable to withstand a fabrication process and upon which semiconductor processing layers may suitably be disposed. For example, in one embodiment, semiconductor wafer or substrate404is composed of a group IV-based material such as, but not limited to, crystalline silicon, germanium or silicon/germanium. In a specific embodiment, providing semiconductor wafer404includes providing a monocrystalline silicon substrate. In a particular embodiment, the monocrystalline silicon substrate is doped with impurity atoms. In another embodiment, semiconductor wafer or substrate404is composed of a III-V material such as, e.g., a III-V material substrate used in the fabrication of light emitting diodes (LEDs).

In an embodiment, semiconductor wafer or substrate404has disposed thereon or therein, as a portion of the integrated circuits406, an array of semiconductor devices. Examples of such semiconductor devices include, but are not limited to, memory devices or complimentary metal-oxide-semiconductor (CMOS) transistors fabricated in a silicon substrate and encased in a dielectric layer. A plurality of metal interconnects may be formed above the devices or transistors, and in surrounding dielectric layers, and may be used to electrically couple the devices or transistors to form the integrated circuits406. Materials making up the streets407may be similar to or the same as those materials used to form the integrated circuits406. For example, streets407may be composed of layers of dielectric materials, semiconductor materials, and metallization. In one embodiment, one or more of the streets407includes test devices similar to the actual devices of the integrated circuits406.

Referring to operation304of Flowchart300, and correspondingFIG. 4F, the mask402is patterned with a laser scribing process to provide a patterned mask408with gaps410, exposing regions of the semiconductor wafer or substrate404between the integrated circuits406. As such, the laser scribing process is used to remove the material of the streets407originally formed between the integrated circuits406. In accordance with an embodiment of the present invention, patterning the mask402with the femtosecond-based laser scribing process includes forming trenches412partially into the regions of the semiconductor wafer404between the integrated circuits406, as depicted inFIG. 4F.

In an embodiment, patterning the mask406with the laser scribing process includes using a laser having a pulse width in the femtosecond range. Specifically, a laser with a wavelength in the visible spectrum plus the ultra-violet (UV) and infra-red (IR) ranges (totaling a broadband optical spectrum) may be used to provide a femtosecond-based laser, i.e., a laser with a pulse width on the order of the femtosecond (10−15seconds). In one embodiment, ablation is not, or is essentially not, wavelength dependent and is thus suitable for complex films such as films of the mask402, the streets407and, possibly, a portion of the semiconductor wafer or substrate404.

FIG. 5illustrates the effects of using a laser pulse in the femtosecond range versus longer frequencies, in accordance with an embodiment of the present invention. Referring toFIG. 5, by using a laser with a pulse width in the femtosecond range heat damage issues are mitigated or eliminated (e.g., minimal to no damage502C with femtosecond processing of a via500C) versus longer pulse widths (e.g., damage502B with picosecond processing of a via500B and significant damage502A with nanosecond processing of a via500A). The elimination or mitigation of damage during formation of via500C may be due to a lack of low energy recoupling (as is seen for picosecond-based laser ablation) or thermal equilibrium (as is seen for nanosecond-based laser ablation), as depicted inFIG. 5.

Laser parameters selection, such as pulse width, may be critical to developing a successful laser scribing and dicing process that minimizes chipping, microcracks and delamination in order to achieve clean laser scribe cuts. The cleaner the laser scribe cut, the smoother an etch process that may be performed for ultimate die singulation. In semiconductor device wafers, many functional layers of different material types (e.g., conductors, insulators, semiconductors) and thicknesses are typically disposed thereon. Such materials may include, but are not limited to, organic materials such as polymers, metals, or inorganic dielectrics such as silicon dioxide and silicon nitride.

A street between individual integrated circuits disposed on a wafer or substrate may include the similar or same layers as the integrated circuits themselves. For example,FIG. 6illustrates a cross-sectional view of a stack of materials that may be used in a street region of a semiconductor wafer or substrate, in accordance with an embodiment of the present invention.

Referring toFIG. 6, a street region600includes the top portion602of a silicon substrate, a first silicon dioxide layer604, a first etch stop layer606, a first low K dielectric layer608(e.g., having a dielectric constant of less than the dielectric constant of 4.0 for silicon dioxide), a second etch stop layer610, a second low K dielectric layer612, a third etch stop layer614, an undoped silica glass (USG) layer616, a second silicon dioxide layer618, and a layer of spun-on mask620, with relative thicknesses depicted. Copper metallization622is disposed between the first and third etch stop layers606and614and through the second etch stop layer610. In a specific embodiment, the first, second and third etch stop layers606,610and614are composed of silicon nitride, while low K dielectric layers608and612are composed of a carbon-doped silicon oxide material.

Under conventional laser irradiation (such as nanosecond-based or picosecond-based laser irradiation), the materials of street600behave quite differently in terms of optical absorption and ablation mechanisms. For example, dielectrics layers such as silicon dioxide, is essentially transparent to all commercially available laser wavelengths under normal conditions. By contrast, metals, organics (e.g., low K materials) and silicon can couple photons very easily, particularly in response to nanosecond-based or picosecond-based laser irradiation. For example,FIG. 7includes a plot700of absorption coefficient as a function of photon energy for crystalline silicon (c-Si,702), copper (Cu,704), crystalline silicon dioxide (c-SiO2,706), and amorphous silicon dioxide (a-SiO2,708), in accordance with an embodiment of the present invention.FIG. 8is an equation800showing the relationship of laser intensity for a given laser as a function of laser pulse energy, laser pulse width, and laser beam radius.

Using equation800and the plot700of absorption coefficients, in an embodiment, parameters for a femtosecond laser-based process may be selected to have an essentially common ablation effect on the inorganic and organic dielectrics, metals, and semiconductors even though the general energy absorption characteristics of such materials may differ widely under certain conditions. For example, the absorptivity of silicon dioxide is non-linear and may be brought more in-line with that of organic dielectrics, semiconductors and metals under the appropriate laser ablation parameters. In one such embodiment, a high intensity and short pulse width femtosecond-based laser process is used to ablate a stack of layers including a silicon dioxide layer and one or more of an organic dielectric, a semiconductor, or a metal. In a specific embodiment, pulses of approximately less than or equal to 400 femtoseconds are used in a femtosecond-based laser irradiation process to remove a mask, a street, and a portion of a silicon substrate.

By contrast, if non-optimal laser parameters are selected, in a stacked structures that involve two or more of an inorganic dielectric, an organic dielectric, a semiconductor, or a metal, a laser ablation process may cause delamination issues. For example, a laser penetrate through high bandgap energy dielectrics (such as silicon dioxide with an approximately of 9 eV bandgap) without measurable absorption. However, the laser energy may be absorbed in an underlying metal or silicon layer, causing significant vaporization of the metal or silicon layers. The vaporization may generate high pressures to lift-off the overlying silicon dioxide dielectric layer and potentially causing severe interlayer delamination and microcracking. In an embodiment, while picoseconds-based laser irradiation processes lead to microcracking and delaminating in complex stacks, femtosecond-based laser irradiation processes have been demonstrated to not lead to microcracking or delamination of the same material stacks.

In order to be able to directly ablate dielectric layers, ionization of the dielectric materials may need to occur such that they behave similar to a conductive material by strongly absorbing photons. The absorption may block a majority of the laser energy from penetrating through to underlying silicon or metal layers before ultimate ablation of the dielectric layer. In an embodiment, ionization of inorganic dielectrics is feasible when the laser intensity is sufficiently high to initiate photon-ionization and impact ionization in the inorganic dielectric materials.

In accordance with an embodiment of the present invention, suitable femtosecond-based laser processes are characterized by a high peak intensity (irradiance) that usually leads to nonlinear interactions in various materials. In one such embodiment, the femtosecond laser sources have a pulse width approximately in the range of 10 femtoseconds to 500 femtoseconds, although preferably in the range of 100 femtoseconds to 400 femtoseconds. In one embodiment, the femtosecond laser sources have a wavelength approximately in the range of 1570 nanometers to 200 nanometers, although preferably in the range of 540 nanometers to 250 nanometers. In one embodiment, the laser and corresponding optical system provide a focal spot at the work surface approximately in the range of 3 microns to 15 microns, though preferably approximately in the range of 5 microns to 10 microns.

The spacial beam profile at the work surface may be a single mode (Gaussian) or have a shaped top-hat profile. In an embodiment, the laser source has a pulse repetition rate approximately in the range of 200 kHz to 10 MHz, although preferably approximately in the range of 500 kHz to 5 MHz. In an embodiment, the laser source delivers pulse energy at the work surface approximately in the range of 0.5 uJ to 100 uJ, although preferably approximately in the range of 1 uJ to 5 uJ. In an embodiment, the laser scribing process runs along a work piece surface at a speed approximately in the range of 500 mm/sec to 5 m/sec, although preferably approximately in the range of 600 mm/sec to 2 m/sec.

The scribing process may be run in single pass only, or in multiple passes, but, in an embodiment, preferably 1-2 passes. In one embodiment, the scribing depth in the work piece is approximately in the range of 5 microns to 50 microns deep, preferably approximately in the range of 10 microns to 20 microns deep. The laser may be applied either in a train of single pulses at a given pulse repetition rate or a train of pulse bursts. In an embodiment, the kerf width of the laser beam generated is approximately in the range of 2 microns to 15 microns, although in silicon wafer scribing/dicing preferably approximately in the range of 6 microns to 10 microns, measured at the device/silicon interface.

Laser parameters may be selected with benefits and advantages such as providing sufficiently high laser intensity to achieve ionization of inorganic dielectrics (e.g., silicon dioxide) and to minimize delamination and chipping caused by underlayer damage prior to direct ablation of inorganic dielectrics. Also, parameters may be selected to provide meaningful process throughput for industrial applications with precisely controlled ablation width (e.g., kerf width) and depth. As described above, a femtosecond-based laser is far more suitable to providing such advantages, as compared with picosecond-based and nanosecond-based laser ablation processes. However, even in the spectrum of femtosecond-based laser ablation, certain wavelengths may provide better performance than others. For example, in one embodiment, a femtosecond-based laser process having a wavelength closer to or in the UV range provides a cleaner ablation process than a femtosecond-based laser process having a wavelength closer to or in the IR range. In a specific such embodiment, a femtosecond-based laser process suitable for semiconductor wafer or substrate scribing is based on a laser having a wavelength of approximately less than or equal to 540 nanometers. In a particular such embodiment, pulses of approximately less than or equal to 400 femtoseconds of the laser having the wavelength of approximately less than or equal to 540 nanometers are used. However, in an alternative embodiment, dual laser wavelengths (e.g., a combination of an IR laser and a UV laser) are used.

Referring to operation306of Flowchart300, and correspondingFIG. 4G, the semiconductor wafer404is etched through the gaps410in the patterned mask408to singulate the integrated circuits406. In accordance with an embodiment of the present invention, etching the semiconductor wafer404includes etching the trenches412formed with the femtosecond-based laser scribing process to ultimately etch entirely through semiconductor wafer404, as depicted inFIG. 4G.

In an embodiment, etching the semiconductor wafer404includes using a plasma etching process. In one embodiment, a through-silicon via type etch process is used. For example, in a specific embodiment, the etch rate of the material of semiconductor wafer404is greater than 25 microns per minute. An ultra-high-density plasma source may be used for the plasma etching portion of the die singulation process. An example of a process chamber suitable to perform such a plasma etch process is the Applied Centura® Silvia™ Etch system available from Applied Materials of Sunnyvale, Calif., USA. The Applied Centura® Silvia™ Etch system combines the capacitive and inductive RF coupling, which gives much more independent control of the ion density and ion energy than was possible with the capacitive coupling only, even with the improvements provided by magnetic enhancement. This combination enables effective decoupling of the ion density from ion energy, so as to achieve relatively high density plasmas without the high, potentially damaging, DC bias levels, even at very low pressures. This results in an exceptionally wide process window. However, any plasma etch chamber capable of etching silicon may be used. In an exemplary embodiment, a deep silicon etch is used to etch a single crystalline silicon substrate or wafer404at an etch rate greater than approximately 40% of conventional silicon etch rates while maintaining essentially precise profile control and virtually scallop-free sidewalls. In a specific embodiment, a through-silicon via type etch process is used. The etch process is based on a plasma generated from a reactive gas, which generally a fluorine-based gas such as SF6, C4F8, CHF3, XeF2, or any other reactant gas capable of etching silicon at a relatively fast etch rate. In an embodiment, the mask layer408is removed after the singulation process, as depicted inFIG. 4G.

Accordingly, referring again to Flowchart300andFIGS. 4A-4F, wafer dicing may be preformed by initial laser ablation through a mask layer, through wafer streets (including metallization), and partially into a silicon substrate. The laser pulse width may be selected in the femtosecond range. Die singulation may then be completed by subsequent through-silicon deep plasma etching. A specific example of a materials stack for dicing is described below in association withFIGS. 9A-9D, in accordance with an embodiment of the present invention.

Referring toFIG. 9A, a materials stack for hybrid laser ablation and plasma etch dicing includes a mask layer902, a device layer904, and a substrate906. The mask layer, device layer, and substrate are disposed above a die attach film908which is affixed to a backing tape910. In an embodiment, the mask layer902is a spin-on mask layer such as the spin-on layers described above in association with mask402. The device layer904includes an inorganic dielectric layer (such as silicon dioxide) disposed above one or more metal layers (such as copper layers) and one or more low K dielectric layers (such as carbon-doped oxide layers). The device layer904also includes streets arranged between integrated circuits, the streets including the same or similar layers to the integrated circuits. The substrate906is a bulk single-crystalline silicon substrate.

In an embodiment, the bulk single-crystalline silicon substrate906is thinned from the backside prior to being affixed to the die attach film908. The thinning may be performed by a backside grind process. In one embodiment, the bulk single-crystalline silicon substrate906is thinned to a thickness approximately in the range of 50-100 microns. It is important to note that, in an embodiment, the thinning is performed prior to a laser ablation and plasma etch dicing process. In an embodiment, the spin-on mask layer902is an approximately 20-150 micron thick layer and the device layer904has a thickness approximately in the range of 2-3 microns. In an embodiment, the die attach film908(or any suitable substitute capable of bonding a thinned or thin wafer or substrate to the backing tape910) has a thickness of approximately 20 microns.

Referring toFIG. 9B, the mask902, the device layer904and a portion of the substrate906are patterned with a femtosecond-based laser scribing process912to form trenches914in the substrate906. Referring toFIG. 9C, a through-silicon deep plasma etch process916is used to extend the trench914down to the die attach film908, exposing the top portion of the die attach film908and singulating the silicon substrate906. The device layer904is protected by the spin-on mask layer902during the through-silicon deep plasma etch process916.

Referring toFIG. 9D, the singulation process may further include patterning the die attach film908, exposing the top portion of the backing tape910and singulating the die attach film908. In an embodiment, the die attach film is singulated by a laser process or by an etch process. Further embodiments may include subsequently removing the singulated portions of substrate906(e.g., as individual integrated circuits) from the backing tape910. In one embodiment, the singulated die attach film908is retained on the back sides of the singulated portions of substrate906. Other embodiments may include removing the spin-on mask layer902from the device layer904. In an alternative embodiment, in the case that substrate906is thinner than approximately 50 microns, the laser ablation process912is used to completely singulate substrate906without the use of an additional plasma process.

Subsequent to singulating the die attach film908, in an embodiment, the masking layer902is removed from the device layer904. In an embodiment, the singulated integrated circuits are removed from the backing tape910for packaging. In one such embodiment, the patterned die attach film908is retained on the backside of each integrated circuit and included in the final packaging. However, in another embodiment, the patterned die attach film908is removed during or subsequent to the singulation process.

Referring again toFIGS. 4A-4F, the plurality of integrated circuits406may be separated by streets407having a width of approximately 10 microns or smaller. The use of a femtosecond-based laser scribing approach, at least in part due to the tight profile control of the laser, may enable such compaction in a layout of integrated circuits. For example,FIG. 10illustrates compaction on a semiconductor wafer or substrate achieved by using narrower streets versus conventional dicing which may be limited to a minimum width, in accordance with an embodiment of the present invention.

Referring toFIG. 10, compaction on a semiconductor wafer is achieved by using narrower streets (e.g., widths of approximately 10 microns or smaller in layout1002) versus conventional dicing which may be limited to a minimum width (e.g., widths of approximately 70 microns or larger in layout1000). It is to be understood, however, that it may not always be desirable to reduce the street width to less than 10 microns even if otherwise enabled by a femtosecond-based laser scribing process. For example, some applications may require a street width of at least 40 microns in order to fabricate dummy or test devices in the streets separating the integrated circuits.

Referring again toFIGS. 4A-4F, the plurality of integrated circuits406may be arranged on semiconductor wafer or substrate404in a non-restricted layout. For example,FIG. 11illustrates freeform integrated circuit arrangement allowing denser packing. The denser packing may provide for more die per wafer versus grid alignment approaches, in accordance with an embodiment of the present invention. Referring toFIG. 11, a freeform layout (e.g., a non-restricted layout on semiconductor wafer or substrate1102) allows denser packing and hence more die per wafer versus grid alignment approaches (e.g., a restricted layout on semiconductor wafer or substrate1100). In an embodiment, the speed of the laser ablation and plasma etch singulation process is independent of die size, layout or the number of streets.

A single process tool may be configured to perform many or all of the operations in a hybrid laser ablation and plasma etch singulation process. For example,FIG. 12illustrates a block diagram of a tool layout for laser and plasma dicing of wafers or substrates, in accordance with an embodiment of the present invention.

Referring toFIG. 12, a process tool1200includes a factory interface1202(FI) having a plurality of load locks1204coupled therewith. A cluster tool1206is coupled with the factory interface1202. The cluster tool1206includes one or more plasma etch chambers, such as plasma etch chamber1208. A laser scribe apparatus1210is also coupled to the factory interface1202. The overall footprint of the process tool1200may be, in one embodiment, approximately 3500 millimeters (3.5 meters) by approximately 3800 millimeters (3.8 meters), as depicted inFIG. 12.

In an embodiment, the laser scribe apparatus1210houses a femtosecond-based laser. The femtosecond-based laser is suitable for performing a laser ablation portion of a hybrid laser and etch singulation process, such as the laser abalation processes described above. In one embodiment, a moveable stage is also included in laser scribe apparatus1200, the moveable stage configured for moving a wafer or substrate (or a carrier thereof) relative to the femtosecond-based laser. In a specific embodiment, the femtosecond-based laser is also moveable. The overall footprint of the laser scribe apparatus1210may be, in one embodiment, approximately 2240 millimeters by approximately 1270 millimeters, as depicted inFIG. 12.

In an embodiment, the one or more plasma etch chambers1208is configured for etching a wafer or substrate through the gaps in a patterned mask to singulate a plurality of integrated circuits. In one such embodiment, the one or more plasma etch chambers1208is configured to perform a deep silicon etch process. In a specific embodiment, the one or more plasma etch chambers1208is an Applied Centura® Silvia™ Etch system, available from Applied Materials of Sunnyvale, Calif., USA. The etch chamber may be specifically designed for a deep silicon etch used to create singulate integrated circuits housed on or in single crystalline silicon substrates or wafers. In an embodiment, a high-density plasma source is included in the plasma etch chamber1208to facilitate high silicon etch rates. In an embodiment, more than one etch chamber is included in the cluster tool1206portion of process tool1200to enable high manufacturing throughput of the singulation or dicing process.

The factory interface1202may be a suitable atmospheric port to interface between an outside manufacturing facility with laser scribe apparatus1210and cluster tool1206. The factory interface1202may include robots with arms or blades for transferring wafers (or carriers thereof) from storage units (such as front opening unified pods) into either cluster tool1206or laser scribe apparatus1210, or both.

Cluster tool1206may include other chambers suitable for performing functions in a method of singulation. For example, in one embodiment, in place of an additional etch chamber, a deposition chamber1212is included. The deposition chamber1212may be configured for mask deposition on or above a device layer of a wafer or substrate prior to laser scribing of the wafer or substrate, e.g., by a uniform spin-on process. In one such embodiment, the deposition chamber1212is suitable for depositing a uniform layer with a conformality factor within approximately 10%. In another embodiment, in place of an additional etch chamber, a wet/dry station1214is included. The wet/dry station may be suitable for cleaning residues and fragments, or for removing a mask, subsequent to a laser scribe and plasma etch singulation process of a substrate or wafer. In an embodiment, a metrology station is also included as a component of process tool1200.

The exemplary computer system1300includes a processor1302, a main memory1304(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory1306(e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory1318(e.g., a data storage device), which communicate with each other via a bus1330.

The computer system1300may further include a network interface device1308. The computer system1300also may include a video display unit1310(e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device1312(e.g., a keyboard), a cursor control device1314(e.g., a mouse), and a signal generation device1316(e.g., a speaker).

The secondary memory1318may include a machine-accessible storage medium (or more specifically a computer-readable storage medium)1331on which is stored one or more sets of instructions (e.g., software1322) embodying any one or more of the methodologies or functions described herein. The software1322may also reside, completely or at least partially, within the main memory1304and/or within the processor1302during execution thereof by the computer system1300, the main memory1304and the processor1302also constituting machine-readable storage media. The software1322may further be transmitted or received over a network1320via the network interface device1308.

In accordance with an embodiment of the present invention, a machine-accessible storage medium has instructions stored thereon which cause a data processing system to perform a method of dicing a semiconductor wafer having a plurality of integrated circuits with bumps or pillars. The method includes uniformly spinning on a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps. Regions of the semiconductor wafer are exposed between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

Thus, uniform masking for wafer dicing using laser and plasma etch has been disclosed.