Method for fast frequency acquisition in a phase locked loop

The method of the present invention provides fast frequency acquisition in a PLL. The peak voltage for a phase error signal is detected at time t.sub.p and a voltage controlled oscillator warp voltage is sampled at t.sub.p. The new warp voltage to the voltage controlled oscillator is set to what the warp voltage was at t.sub.p. The bandwidth of the loop is then narrowed and the warp voltage is averaged over a number of samples. The warp voltage is then set to the average warp voltage and the loop bandwidth is widened.

FIELD OF THE INVENTION 
The present invention relates generally to the field of communications and 
particularly to phase locked loops used in digital communications. 
BACKGROUND OF THE INVENTION 
When a mobile radiotelephone is handed off from one radiotelephone cell to 
another, it typically must change from the frequency that was used in the 
old cell to a new frequency that will be used in the new cell. This 
hand-off takes place while the radiotelephone is in a call, and therefore 
must be done quickly enough to avoid a drop in the audio signal. This drop 
will cause a gap in conversation in the call. The U.S. Digital Cellular 
specifications require that the frequency difference between the receiver 
and the incoming signal be within .+-.200 Hz. The receiver, therefore, 
must quickly lock onto the new frequency to stay within these limits. 
A phase locked loop (PLL) is typically used in the radiotelephone to change 
from one frequency to another. PLLs are discussed in A. Blanchard, Phase 
Locked Loops: Application to Coherent Receiver Design 281-292 (1976) and 
F. Gardner, Phaselock Techniques (1979). One method for decreasing the 
PLLs lock time is to use an adaptive bandwidth filter to narrow the 
signal's bandwidth when the phase error crosses the zero axis. The problem 
with this method, however, is that it takes a relatively large amount of 
time for the voltage controlling the voltage controlled oscillator (VCO), 
the warp voltage, to reach zero. There is a resulting need for a method to 
greatly reduce the time for a PLL to lock onto a frequency. 
SUMMARY OF THE INVENTION 
The method of the present invention provides fast frequency acquisition in 
a PLL. The PLL being comprised of a frequency detector that outputs an 
error signal, an integrating filter that converts the frequency error to a 
phase error, a loop filter that outputs a warp voltage, and a VCO that is 
controlled by the warp voltage. The peak voltage for the phase error 
signal is detected at time t.sub.p and the warp voltage is sampled at 
t.sub.p. The warp voltage to the VCO is set to what the warp voltage was 
at t.sub.p. The bandwidth of the loop is then narrowed and the warp 
voltage is averaged over a number of samples. The warp voltage is then set 
to the average warp voltage and held there.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
The frequency acquisition method of the present invention greatly reduces 
the time required for a communication receiver to lock onto the frequency 
of an incoming signal. By detecting the peak voltage of the phase error 
and the voltage of the warp voltage at the time of this peak, the PLL's 
VCO can be reset to this warp voltage, thereby greatly reducing the lock 
time. 
The PLL of the present invention, illustrated in FIG. 1, is comprised of 
the frequency detector (101), a loop filter (102), an integrating filter 
(104), and a VCO (103). The frequency detector (101) generates an error 
signal, V.sub.e (t). This signal is converted to a phase error by the 
integrating filter (104). The loop filter (102) integrates the phase error 
signal, generating the warp voltage. The warp voltage controls the 
frequency of the VCO (103). The various voltages of the PLL with reference 
to FIG. 1, are as follows: 
EQU v.sub.1 (t)=e.sup.j(.DELTA..omega.t.sbsp.1.sup.+.theta.t.sbsp.1.sup.) 
EQU v.sub.2 
(t)=e.sup.j(.DELTA..omega.(t.sbsp.1.sup.-t.sbsp.2.sup.)+.theta.t.sbsp.1.su 
p.-.theta.t.sbsp.2.sup.) 
EQU v.sub.3 (t)=(-1)e.sup.j4(.DELTA..omega.(t.sbsp.1.sup.-t.sbsp.2.sup.)) 
The Laplace domain representation of the PLL is illustrated in FIG. 2. A 
derivation of the frequency detector characteristic function is as 
follows: 
EQU v.sub.e 
(t)=Im{e.sup.j4(.theta..sbsp.1.sup.(t)-.theta..sbsp.1.sup.(t-T.sbsp.s.sup. 
)-.theta..sbsp.2.sup.(t)+.theta..sbsp.2.sup.(t-T.sbsp.s.sup.)) }=sin 
{4(.theta..sub.1 (t)-.theta..sub.1 (t-T.sub.s)-.theta..sub.2 
(t)+.theta..sub.2 (t-T.sub.s))}. 
After linearizing the loop and transforming to the Laplace domain, 
##EQU1## 
Therefore, 
##EQU2## 
Equating V.sub.o (s) to s.theta..sub.2 (s)/K.sub.v, the closed loop 
response becomes 
##EQU3## 
The detector can be approximated by the term 4K.sub.o s, where K.sub.o is a 
gain constant. Because conventional phase detectors are characterized by a 
constant in the Laplace domain, a pole was introduced by the integrating 
filter (104) as F.sub.1 (s)=K.sub.1 /s. The second stage of the loop 
filter is the active integrator denoted by F.sub.2 (s). In response to a 
step change in frequency by the incoming signal, the error signal, V.sub.e 
(t), will be driven towards zero. Since V.sub.i (t) is the integral of the 
error signal, F.sub.1 (s) will produce a pulse at its output. The pulse 
will peak when the error signal changes polarity and the amplitude of the 
pulse will be proportional to the frequency offset. The filter, F.sub.2 
(s), will integrate this pulse to produce the desired step response 
voltage, V.sub.warp (t), to control the VCO output frequency. 
The frequency acquisition algorithm of the present invention is illustrated 
in FIG. 3. The algorithm is first initialized by setting counter registers 
LD.sub.-- CNT and LD.sub.-- AVG.sub.-- CNT to zero (401). V.sub.imax, the 
maximum value of V.sub.i (t), the integrator output, at the present point 
in time, is also set to zero. Tempwarp is the new sample of the warp 
voltage, V.sub.warp, sampled at the time of V.sub.imax. 
First the PLL in FIG. 1 is run once to get samples of V.sub.i (t) and 
V.sub.warp (t) and the LD.sub.-- CNT register is incremented by one (402). 
If fifty samples have not been taken (403), V.sub.i is compared to the 
last V.sub.imax (404). If the current sample is greater, it is stored as 
the new V.sub.imax, the new V.sub.warp sample is stored as the temporary 
warp voltage, tempwarp, and the LD.sub.-- CNT register is set to zero 
(405). Since the LD.sub.-- CNT register is set to zero every time a new 
V.sub.imax is found, the process of the present invention will retrieve 50 
samples beyond the last maximum value of V.sub.i. This greatly reduces the 
possibility that the last V.sub.imax was due to noise. 
Once the process has gone 50 samples past the last V.sub.imax (406), that 
V.sub.imax is the peak of the V.sub.i (t) waveform. V.sub.warp is now 
assigned the value of tempwarp (405), causing the sharp drop at t.sub.p 
illustrated in FIG. 4. Tempwarp is assigned to V.sub.warp for the next 
five times the loop is run (408 and 409). Once the process gets past 100 
samples (410), the loop bandwidth is narrowed to attenuate the modulation 
(411) and V.sub.warp is averaged for 500 samples (412 and 414). This is 
done by incrementing LD.sub.-- AVG.sub.-- CNT each time through the 
process. After LD.sub.-- AVG.sub.-- CNT reaches 501, V.sub.warp is set 
equal to the average warp voltage (413), LD.sub.-- AVG, found during this 
time and held there. The PLL is now locked onto the proper frequency. 
Other methods for finding the peak voltage for V.sub.i can also be used 
while remaining within the scope of the present invention. Such a method 
includes differentiating and filtering the detector output to detect the 
peak. Also, in applications where the detector output is not readily 
available, the warp voltage driving the VCO could be differentiated and 
used to detect the peak. If a more common phase error detector was used, 
the integrating filter is not required. The peak of the phase detector 
output could be used to reset the warp voltage to its value corresponding 
to time t.sub.p. 
In summary, a process for quickly acquiring frequency lock in a PLL has 
been shown. This is accomplished by setting the VCO's warp voltage equal 
to the warp voltage that occurred at the same time as the peak phase error 
.