Frequency dividing apparatus and related method

A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and a controlling device arranged to generate the first reset signal at least according to a programming input signal; wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.

BACKGROUND

The present invention relates to a frequency dividing apparatus and the related method, and more particularly to a high speed dual-modulus prescaler and the related method.

A frequency divider is commonly used for converting a high frequency clock signal into a low frequency clock signal. For example, a frequency divider may be used in a feedback loop of a frequency synthesizer. A conventional frequency divider comprises a plurality of cascaded dual-modulus prescalers, and each dual-modulus prescaler has two different frequency divisors. By individually controlling each of the plurality of cascaded dual-modulus prescalers to operate under one of the divisors, the frequency divider is capable of dividing a high frequency clock signal into a low frequency clock signal by an adjustable total divisor. However, in the modern semiconductor manufacturing technology, when a low supply voltage is applied to the frequency divider, some of the dual-modulus prescalers may operate abnormally. More specifically, for those dual-modulus prescalers in the front-end of the frequency divider, the dual-modulus prescalers deal with clock signal having higher frequency than those in the back-end of the frequency divider. The front-end dual-modulus prescalers may operate abnormally in the low supply voltage and high frequency environment due to the critical mode timing control. For example, when a control signal triggers the dual-modulus prescaler to switch from a first divisor into a second divisor, the control signal may not timely switch the dual-modulus prescaler under the low supply voltage and high frequency environment. As a result, the dual-modulus prescaler may still use the first divisor to divide the input clock signal after the triggering of the control signal. Therefore, how to increase the operating speed of a dual-modulus prescaler under the low supply voltage and high frequency environment is an urgent problem in the field of frequency divider.

SUMMARY

One of the objectives of the present embodiment is to provide a high speed dual-modulus prescaler and the related method.

According to a first embodiment of the present invention, a frequency dividing apparatus is disclosed. The frequency dividing apparatus comprises a plurality of latching devices and a controlling device. The plurality of latching devices are arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal. The controlling device is arranged to generate the first reset signal at least according to a programming input signal, wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.

According to a second embodiment of the present invention, a frequency dividing method is disclosed. The frequency dividing method comprises: using a plurality of latching devices to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; generating the first reset signal at least according to a programming input signal; and using the first reset signal to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.

DETAILED DESCRIPTION

Please refer toFIG. 1, which is a diagram illustrating a frequency dividing apparatus100according to a first embodiment of the present invention. The frequency dividing apparatus100may be a dual-modulus prescaler. The frequency dividing apparatus100comprises a plurality of latching devices, i.e. a first latching device102and a second latching device104, arranged to selectively generate an output signal Fo having a first oscillating frequency f1or a second oscillating frequency f2different from the first oscillating frequency f1according to an input clock signal Fin and a first reset signal Srst1. Therefore, the first latching device102in combination with the second latching device104can be regarded as a prescaler logic1022. The controlling device106is arranged to generate the first reset signal Srst1according to a programming input signal Sp, the input clock signal Fin, a mode control signal Modin, and the output signal Fo. In this embodiment, the frequency dividing apparatus100has two divisors, one divisor is two and the other divisor is three. When the frequency dividing apparatus100divides the input clock signal Fin by two, the output signal Fo having the first oscillating frequency f1is outputted. When the frequency dividing apparatus100divides the input clock signal Fin by three, the output signal Fo having the second oscillating frequency f2is outputted. It is noted that the divisors are not the limitations of the present invention. Moreover, the first oscillating frequency f1and the second oscillating frequency f2are depended on the frequency of the input clock signal Fin.

According to the embodiment, the first reset signal Srst1is arranged to reset the first latching device102to make the prescaler logic1022to generate the output signal Fo having the second oscillating frequency f2. More specifically, when the first reset signal Srst1is a high voltage level Vdd, the first reset signal Srst1resets the first latching device102to make the prescaler logic1022to divide the input clock signal Fin by three. When the first reset signal Srst1is a low voltage level Vgnd, the first reset signal Srst1does not reset the first latching device102to make the prescaler logic1022to divide the input clock signal Fin by two.

In addition, the first latching device102has a clock terminal ck receiving the input clock signal Fin, a reset terminal rst receiving the first reset signal Srst1, a data input terminal D receiving the output signal Fo, and a data output terminal Q outputting a first latching signal S11. The second latching device104has a clock terminal ck receiving an inverse input clock signal of the input clock signal Fin, a data input terminal D receiving the first latching signal S11, a first data output terminal Q outputting a second latching signal S12, and a second data output terminal Q_bar outputting the output signal Fo.

The controlling device106comprises a first AND gate106a, a third latching device106b, a second AND gate106c, and a fourth latching device106d. The first AND gate106ahas a first input terminal receiving the second latching signal S12, a second input terminal receiving the mode control signal Modin, which is received from to the next dual-modulus prescaler, and an output terminal outputting a first logical signal Ss1. The third latching device106bhas a clock terminal ck receiving the input clock signal Fin, a data input terminal D receiving the first logical signal Ss1, and a first data output terminal Q outputting a third latching signal S13. The third latching signal S13can be regarded as a mode output signal Modout, which is provided to the previous dual-modulus prescaler. The second AND gate106chas a first input terminal receiving the third latching signal S13, a second input terminal receiving the programming input signal Sp, and an output terminal outputting a second logical signal Ss2. The fourth latching device106dhas a clock terminal ck receiving the inverse input clock signal of the input clock signal Fin, a data input terminal D receiving the second logical signal Ss2, and a first data output terminal Q outputting the first reset signal Srst1.

According to the embodiment, a conducting path108is arranged to directly connect between the reset terminal rst of the first latching device102and the first data output terminal Q of the fourth latching device106dfor conducting the first reset signal Srst1to the first latching device102. Accordingly, once the first reset signal Srst1is generated, the first reset signal Srst1can immediately reset the first latching device102without passing through any logical stage. Therefore, the arrangement of the conducting path108can shorten the transmission time of the first reset signal Srst1. Moreover, another conducting path110is arranged to directly connect between the data input terminal D of the first latching device102and the second data output terminal Q_bar of the second latching device104to shorten the transmission time of the output signal Fo transmitted from the second data output terminal Q_bar of the second latching device104to the data input terminal D of the first latching device102.

More specifically, please refer toFIG. 2, which is a timing diagram illustrating the input clock signal Fin, the output signal Fo, the second latching signal S12(which is the inverse of the output signal Fo), the mode control signal Modin, the first reset signal Srst1, and the first latching signal S11according to an embodiment of the present invention. It is assumed that the programming input signal Sp is in the high voltage level Vdd in this embodiment. Before the time t1, the voltage levels of the mode control signal Modin and the first reset signal Srst1are the low voltage level Vgnd, thus the frequency dividing apparatus100divides the frequency of the input clock signal Fin by two. At time t1, the frequency dividing apparatus100receives the high voltage level Vdd of the mode control signal Modin from the next frequency dividing apparatus (not shown), meaning that the frequency dividing apparatus100needs to divide the frequency of the input clock signal Fin by three in the next period of input clock signal Fin. At time t2, the rising edge of the input clock signal Fin controls the second latching device104to output the low voltage level Vgnd of the output signal Fo and to output the high voltage level Vdd of the second latching signal S12. Meanwhile, at time t2, the rising edge of the input clock signal Fin controls the first latching device102to read the low voltage level Vgnd of the output signal Fo. Then, at time t3, the falling edge of the input clock signal Fin controls the first latching device102to change the voltage level of the first latching signal S11into the low voltage level Vgnd from the high voltage level Vdd. After a delay time td, the voltage level of the first latching signal S11is changed to the low voltage level Vgnd from the high voltage level Vdd at time t4. Meanwhile, at time t3, the falling edge of the input clock signal Fin controls the fourth latching device106dto read the high voltage level Vdd of the second logical signal Ss2(not shown inFIG. 2). Then, at time t4, the rising edge of the input clock signal Fin controls the fourth latching device106dto output the high voltage level Vdd of the first reset signal Srst1. Then, the first latching device102is reset by the high voltage level Vdd of the first reset signal Srst1in the time interval from t4to t6. Accordingly, the falling edge of the input clock signal Fin at time t5does not change the voltage level of the first latching signal S11to the high voltage level Vdd from the low voltage level Vgnd. In other words, the first latching signal S11is kept at low voltage level Vgnd for another one period of the input clock signal Fin until time t7as shown inFIG. 7. When the first latching signal S11is kept at low voltage level Vgnd until time t7, the voltage level of the output signal Fo as well as the second latching signal S12is also kept intact for another one period of the input clock signal Fin until time t8. Accordingly, the frequency dividing apparatus100divides the frequency of the input clock signal Fin by three from the time t2to the time t8.

It is noted that, to successfully divide the frequency of the input clock signal Fin by three from the time t2to the time t8, the high voltage level Vdd of the first reset signal Srst1should be timely reset the first latching device102otherwise the first latching device102will outputs the high voltage level Vdd at time t5. More specifically, when the voltage level of the first reset signal Srst1is changed to the high voltage level Vdd at time t4, the voltage level of the output signal Fo also changes to the high voltage level Vdd at about time t4. If the high voltage level Vdd of the first reset signal Srst1is not transmitted to the first latching device102to reset the first latching device102before time t5, the falling edge at the time t5may control the first latching device102to output the high voltage level Vdd. According to the embodiment, the conducting path108shortens the transmission time of the first reset signal Srst1such that the high voltage level Vdd of the first reset signal Srst1can timely reset the first latching device102as shown inFIG. 2.

Please refer toFIG. 3, which is a schematic diagram illustrating the frequency dividing apparatus100according to an embodiment of the present invention. The frequency dividing apparatus100is a true single phase clock (TSPC) circuit. The first latching device102comprises four P-type transistors M1, M2, M3, M4, and four N-type transistors M5, M6, M7, M8. The gates of P-type transistor M1and the N-type transistor M5receive the output signal Fo. The gates of P-type transistors M2, M3, and the N-type transistor M7receive the input clock signal Fin. The gate of the N-type transistor M8receives the first reset signal Srst1. The first latching signal S11is outputted at the drain of the P-type transistor M4.

The second latching device104comprises two P-type transistors M9, M10, and three N-type transistors M11, M12, M13. The gates of the P-type transistor M9and the N-type transistor M12receive the first latching signal S11. The gate of N-type transistor M11receives the input clock signal Fin. The output signal Fo is outputted at the drain of P-type transistor M9. The second latching signal S12is outputted at the drain of the P-type transistor M10.

The first AND gate106acomprises two P-type transistors M14, M15, and two N-type transistors M16, M17. The gate of the P-type transistor M15receives the second latching signal S12. The gates of the P-type transistor M14and the N-type transistor M16receive the input clock signal Fin. The gate of the N-type transistor M16receives the mode control signal Modin. The first logical signal Ss1is outputted at the drain of the P-type transistor M15.

The third latching device106bcomprises two P-type transistors M18, M19, and one N-type transistor M20. The gates of P-type transistor M18and N-type transistor M20receive the first logical signal Ss1. The gate of P-type transistor M19receives the input clock signal Fin. The third latching signal S13is outputted at the drain of the P-type transistor M19.

The second AND gate106ccomprises two P-type transistors M21, M22, and three N-type transistors M23, M24, M25. The gates of P-type transistor M21and N-type transistor M24receive the third latching signal S13. The gate of N-type transistor M23receives the input clock signal Fin. The gates P-type transistor M22and N-type transistor M25receive the programming input signal Sp. The second logical signal Ss2is outputted at the drain of the P-type transistor M21.

The fourth latching device106dcomprises one P-type transistor M26, and two N-type transistors M27, M28. The gate of the P-type transistor M26and the N-type transistor M28receive the second logical signal Ss2. The gate of N-type transistor M27receives the input clock signal Fin. The first reset signal Srst1is outputted at the drain of P-type transistor M26.

It is noted that the connectivity of the circuit elements in the frequency dividing apparatus100is shown inFIG. 3, thus the detailed description is omitted here for brevity.

According toFIG. 3, it is assumed that the voltage levels of the third latching signal S13and the programming input signal Sp are the high voltage level Vdd. When the voltage at the gate of the N-type transistor M23is changed to high voltage level Vdd from the low voltage level Vgnd, i.e. the rising edge of the input clock signal Fin, then the voltage (i.e. the second logical signal Ss2) at the drain of the P-type transistor M21is discharged to the low voltage level Vgnd from the high voltage level Vdd. Then, the voltage (i.e. the first reset signal Srst1) at the drain of the P-type transistor M26is charged to the high voltage level Vdd from the low voltage level Vgnd. The high voltage level Vdd of the first reset signal Srst1will directly discharge the voltage at the drain of the P-type transistor M4to the low voltage level Vgnd from the high voltage level Vdd via the conducting path108, i.e. to reset the first latching device102. In other words, the rising edge at the gate of the N-type transistor M23only passes two logical stages (i.e. the second AND gate106cand the fourth latching device106d) to reset the first latching device102. Therefore, the conducting path108directly connected between the fourth latching device106dand the first latching device102shortens the transmission time of the first reset signal Srst1such that the high voltage level Vdd of the first reset signal Srst1can timely reset the first latching device102.

It should be noted that the above mentioned high voltage level Vdd and the low voltage level Vgnd may not be the fixed voltage levels. The high voltage level Vdd and the low voltage level Vgnd may deviate from their predetermined voltage levels due to the voltage drop between the drain and the source of a transistor.

Please refer toFIG. 4, which is a diagram illustrating a frequency dividing apparatus400according to a second embodiment of the present invention. The frequency dividing apparatus400may be a dual-modulus prescaler. The frequency dividing apparatus400comprises a plurality of latching devices, i.e. a first latching device402and a second latching device404, arranged to selectively generate an output signal Fo′ having a first oscillating frequency f1′ or a second oscillating frequency f2′ different from the first oscillating frequency f1′ according to an input clock signal Fin′ and a first reset signal Srst1′. The first latching device402in combination with the second latching device404can be regarded as a prescaler logic4022. The controlling device406is arranged to generate the first reset signal Srst1′ and a second reset signal Srst2′ according to a programming input signal Sp′, the input clock signal Fin′, a mode control signal Modin′, and the output signal Fo′. Similar to the first embodiment, the frequency dividing apparatus400has two divisors, one divisor is two and the other divisor is three.

According to this embodiment, the first reset signal Srst1′ is arranged to reset the first latching device102′ to make the prescaler logic4022to generate the output signal Fo′ having the second oscillating frequency f2′. Similar to the first embodiment, when the first reset signal Srst1′ is a high voltage level Vdd′, the first reset signal Srst1′ resets the first latching device402to make the prescaler logic4022to divide the input clock signal Fin′ by three. When the first reset signal Srst1′ is a low voltage level Vgnd′, the first reset signal Srst1′ does not reset the first latching device402to make the prescaler logic4022to divide the input clock signal Fin′ by two.

On the other hand, the second reset signal Srst2′ is arranged to reset the controlling device406, and the second reset signal Srst2′ is an inverse signal of the first reset signal Srst1′. Therefore, when the second reset signal Srst2′ is the low voltage level Vgnd′, the second reset signal Srst2′ resets the controlling device406. When the second reset signal Srst2′ is the high voltage level Vdd′, the second reset signal Srst2′ does not reset the controlling device406.

The prescaler logic4022is similar to the prescaler logic1022of the frequency dividing apparatus100. Therefore, the detailed description of the prescaler logic4022is omitted here for brevity.

For the controlling device406, the controlling device406also comprises a first AND gate406a, a third latching device406b, a second AND gate406c, and a fourth latching device406d. The connectivity of the controlling device406is similar to the connectivity of the controlling device106except that another conducting path406eis directly connected between the fourth latching device406dand the first AND gate406afor transmitting the second reset signal Srst2′. More specifically, in this embodiment, the fourth latching device406dfurther has a clock terminal ck receiving the inverse input clock signal of the input clock signal Fin′, a data input terminal D receiving the second logical signal Ss2′, a first data output terminal Q outputting the first reset signal Srst1′, and a second data output terminal Q_bar outputting the second reset signal Srst2′. The first AND gate406ahas a first input terminal receiving the second latching signal S12′, a second input terminal receiving the mode control signal Modin′, which is received from to the next dual-modulus prescaler, a third input terminal receiving the second reset signal Srst2′, and an output terminal outputting a first logical signal Ss1′.

Accordingly, in this embodiment, the first conducting path408is arranged to directly connect between the reset terminal rst of the first latching device402and the first data output terminal Q of the fourth latching device406dfor conducting the first reset signal Srst1′ to the first latching device402, and the second conducting path406eis arranged to directly connect between the second output terminal Q_bar of the fourth latching device406dand the third input terminal of the first AND gate406afor conducting the second reset signal Srst2′ to the first AND gate406a.

Therefore, once the first reset signal Srst1′ and the second reset signal Srst2′ are generated, the first reset signal Srst1′ and the second reset signal Srst2′ can immediately reset the first latching device402and the first AND gate406arespectively without passing through any logical stage. In other words, the arrangement of the conducting path408and the conducting path406ecan shorten the transmission time of the first reset signal Srst1and the second reset signal Srst2respectively. It is noted that another conducting path410is also arranged to directly connect between the data input terminal D of the first latching device402and the second data output terminal Q_bar of the second latching device404to shorten the transmission time of the output signal Fo′ transmitted from the second data output terminal Q_bar of the second latching device404to the data input terminal D of the first latching device402.

Please refer toFIG. 5, which is a schematic diagram illustrating the frequency dividing apparatus400according to an embodiment of the present invention. The frequency dividing apparatus400is a true single phase clock (TSPC) circuit. The first latching device402comprises four P-type transistors M1′, M2′, M3′, M4′, and four N-type transistors M5′, M6′, M7′, M8′. The second latching device404comprises two P-type transistors M9′, M10′, and three N-type transistors M11′, M12′, M13′. The first AND gate406acomprises three P-type transistors M14′, M15′, M16′, and two N-type transistors M17′, M18′. The third latching device406bcomprises two P-type transistors M19′, M20′, and one N-type transistor M21′. The second AND gate406ccomprises two P-type transistors M22′, M23′, and three N-type transistors M24′, M25′, M26′. The fourth latching device406dcomprises two P-type transistor M27′, M28′, and three N-type transistors M29′, M30′, M31′. It is noted that the connectivity of the circuit elements in the frequency dividing apparatus400is shown inFIG. 5, thus the detailed description is omitted here for brevity.

In comparison with the frequency dividing apparatus100as shown inFIG. 3, the frequency dividing apparatus400further comprises the P-type transistors M16′, M28′, the N-type transistor M31, and the conducting path406e, in which the P-type transistor M28′ in combination with the N-type transistor M31are arranged to generate the second reset signal Srst2′ according to the first reset signal Srst1′, the conducting path406eis arranged to transmit the second reset signal Srst2′, and the P-type transistor M16′ is arranged to reset the first AND gate406a.

Please refer toFIG. 6, which is a diagram illustrating a frequency dividing apparatus600according to a third embodiment of the present invention. The frequency dividing apparatus600may be a dual-modulus prescaler. The frequency dividing apparatus600comprises a plurality of latching devices, i.e. a first latching device602and a second latching device604, and an AND gate605, arranged to selectively generate an output signal Fo″ having a first oscillating frequency f1″ or a second oscillating frequency f2″ different from the first oscillating frequency f1″ according to an input clock signal Fin″ and a first reset signal Srst1″. The first latching device602in combination with the second latching device604and the AND gate605can be regarded as a prescaler logic6022. The controlling device606is arranged to generate the first reset signal Srst1″ according to a programming input signal Sp″, the input clock signal Fin″, a mode control signal Modin″, and the output signal Fo″. Similar to the first embodiment, the frequency dividing apparatus400has two divisors, one divisor is two and the other divisor is three.

According to this embodiment, the first reset signal Srst1″ is arranged to reset the first latching device102″ to make the prescaler logic6022to generate the output signal Fo″ having the second oscillating frequency f2″. Similar to the first embodiment, when the first reset signal Srst1″ is a high voltage level Vdd″, the first reset signal Srst1″ resets the first latching device602to make the prescaler logic6022to divide the input clock signal Fin″ by three. When the first reset signal Srst1″ is a low voltage level Vgnd″, the first reset signal Srst1″ does not reset the first latching device602to make the prescaler logic6022to divide the input clock signal Fin″ by two.

The controlling device606also comprises a first AND gate606a, a third latching device606b, a second AND gate606c, and a fourth latching device606d. The controlling device606is similar to the controlling device106of the frequency dividing apparatus100. Therefore, the detailed description of the controlling device606is omitted here for brevity.

For the prescaler logic6022, the prescaler logic6022further comprises the AND gate605, in which the AND gate605has a first input terminal coupled to the second output terminal Q_bar of the second latching device604for receiving the output signal Fo″, a second input terminal coupled to the second output terminal Q_bar of the fourth latching device606d, and an output terminal coupled to the data input terminal D of the first latching device602.

The conducting path608is arranged to directly connect between the reset terminal rst of the first latching device602and the first data output terminal Q of the fourth latching device606dfor conducting the first reset signal Srst1″ to the first latching device602. Therefore, once the first reset signal Srst1″ is generated, the first reset signal Srst1″ can immediately reset the first latching device602without passing through any logical stage. In other words, the arrangement of the conducting path608can shorten the transmission time of the first reset signal Srst1″.

Please refer toFIG. 7, which is a schematic diagram illustrating the frequency dividing apparatus600according to an embodiment of the present invention. The frequency dividing apparatus600is a true single phase clock (TSPC) circuit. The AND gate605comprises three P-type transistors M1″, M2″, M3″, and two N-type transistors M4″, M5″. The first latching device602comprises two P-type transistors M6″, M7″, and three N-type transistors M8″, M9″, M10″. The second latching device604comprises two P-type transistors M11″, M12″, and three N-type transistors M13″, M14″, M15″. The first AND gate606acomprises two P-type transistors M16″, M17″, and two N-type transistors M18″, M19″. The third latching device606bcomprises two P-type transistors M20″, M21″, and one N-type transistor M22″. The second AND gate606ccomprises two P-type transistors M23″, M24″, and three N-type transistors M25″, M26″, M27″. The fourth latching device606dcomprises two P-type transistors M28″, M29″, and three N-type transistors M30″, M31″, M32″. It is noted that the connectivity of the circuit elements in the frequency dividing apparatus600is shown inFIG. 7, thus the detailed description is omitted here for brevity.

In comparison with the frequency dividing apparatus100as shown inFIG. 3, the frequency dividing apparatus400further comprises the AND gate605, i.e. the three P-type transistors M1″, M2″, M3″, and the two N-type transistors M4″, M5″. The AND gate605in combination with the conducting path610is utilized to save certain DC (Direct current) current, and the delay introduced by the AND gate605in combination with the conducting path610is not critical.

In summary, the procedure of implementing the above embodiments can be summarized into the process inFIG. 8, which is a flowchart illustrating a frequency dividing method800according to an embodiment of the present invention. The frequency dividing method800is described in accordance with the frequency dividing apparatus100, and this is not a limitation of the present invention. Provided that substantially the same result is achieved, the steps of the flowchart shown inFIG. 8need not be in the exact order shown and need not be contiguous, that is, other steps can be intermediate. The frequency dividing method800comprises:

Step802: Use the first latching device102and the second latching device104to selectively generate the output signal Fo having the first oscillating frequency f1or the second oscillating frequency f2different from the first oscillating frequency f1according to the input clock signal Fin and the first reset signal Srst1;

Step804: Generate the first reset signal Srst1according to the programming input signal Sp, the input clock signal Fin, the mode control signal Modin, and the output signal Fo;

Step806: Use the conducting path108to directly conduct the first reset signal Srst1to the first latching device102; and

Step808: Use the first reset signal Srst1to reset the first latching device102to make the prescaler logic1022to generate the output signal Fo′ having the second oscillating frequency f2.

Briefly, according to the above embodiments, a conducting path is arranged to directly transmit a reset signal to the prescaler logic in order to timely reset the first latching device (e.g.102) of the prescaler logic when the prescaler logic needs to divide the input clock signal by three. Therefore, the prescaler logic may correctly divide the high frequency input clock in dual modes (e.g. the divisor of 2 or 3) under the low supply voltage and high frequency environment.