Apparatus and method for testing semiconductor memory devices, capable of selectively changing frequencies of test pattern signals

There are provided an apparatus and method for testing semiconductor memory devices, in which the frequencies of test pattern signals can be selectively changed. The test apparatus includes a main tester, an input frequency converter, and an output frequency converter. The main tester generates first input test signals with a first frequency, a first program control signal, and a second program control signal, receives first output test pattern signals with the first frequency, and determines an operating performance of a semiconductor memory device. The input frequency converter converts the first input test pattern signals into second input test pattern signals with a second frequency in response to the first program control signal, and applies the second input test pattern signals to the semiconductor memory device. The output frequency converter converts the second output test pattern signals with the second frequency received from the semiconductor memory device into the first output test pattern signals in response to the second program control signal and outputs the first output test pattern signals. The test apparatus and method can test semiconductor memory devices with a high operating frequency by selectively changing the frequencies of test pattern signals.

BACKGROUND OF THE INVENTION

This application claims the priority of Korean Patent Application No. 2003-58777, filed on Aug. 25, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.

FIELD OF THE INVENTION

The present invention relates to an apparatus for testing semiconductor devices, and more particularly, to an apparatus for testing semiconductor memory devices and a method for using the same.

DESCRIPTION OF THE RELATED ART

Semiconductor memory devices are generally subjected to testing before they are sold. The testing of the semiconductor memory devices includes three different tests: a DC parametric test, a dynamic functional test, and an AC parametric test.

In the DC parametric test, DC characteristics such as a source current, a leakage current, and output voltage characteristics of a semiconductor memory device are verified. In the dynamic functional test, it is determined whether a semiconductor memory device performs predetermined operations correctly when actually operating. In the AC parametric test, AC characteristics of a semiconductor memory device, that is, time-dependent parameters of a semiconductor memory device, are measured.

The dynamic functional test is performed under normal operating conditions of the semiconductor memory device. In the dynamic functional test, a test apparatus generates pattern signals, outputs the pattern signals to the semiconductor memory device to be tested, compares signals output from the semiconductor memory device with reference signals, and determines whether the semiconductor memory device is operating correctly. A conventional test apparatus for testing semiconductor memory devices is disclosed in U.S. Pat. No. 5,978,949.

FIG.1is a block diagram of a conventional test apparatus101and a semiconductor memory device102. The test apparatus101includes a test signal generator110and a defect analyzer120. The test signal generator110includes a first timing generator111, a first algorithmic pattern generator (ALPG)112, a format controller113, a driver114, and a first reference voltage generator115. The defect analyzer120includes a comparator121, a second reference voltage generator122, a digital comparator123, a second timing generator124, a second ALPG125, and a memory126. Output terminals of the driver114are respectively connected one-to-one to the input terminals of the semiconductor memory device102, and the output terminals of the semiconductor memory device102are respectively connected to input terminals of the comparator121.

The driver114of the test signal generator110generates a plurality of pattern signals DR1through DRN (N is an integer greater than two) and outputs the plurality of pattern signals DR1through DRN to the semiconductor memory device102. Then, the semiconductor memory device102outputs a plurality of signals CP1through CPN to the comparator121of the defect analyzer120, in response to the plurality of pattern signals DR1through DRN. The defect analyzer120compares the plurality of signals CP1through CPN with predetermined reference signals and stores the compared result in the memory126.

The conventional test apparatus101can test semiconductor memory devices with a relatively low operating frequency of 250 MHz with a bus throughput of 500 Mbps. However, as high-frequency semiconductor memory devices are being developed, a test apparatus capable of testing such high-frequency semiconductor memory devices is required. Existing test systems can test semiconductor memory devices with operating frequencies up to 500 MHz with a bus throughput of 1 Gbps. Therefore, conventional test systems cannot determine operation characteristics of semiconductor memory devices with higher operating frequencies.

SUMMARY OF THE INVENTION

The present invention provides an apparatus and method for testing a semiconductor memory device with a high operating frequency by selectively changing the frequencies of test pattern signals.

According to an aspect of the present invention, there is provided an apparatus for testing a semiconductor memory device comprising a main tester, an input frequency converter, and an output frequency converter.

The main tester generates a plurality of first input test pattern signals with a first frequency, a first program control signal, and a second program control signal, receives a plurality of first output test pattern signals with the first frequency, and detects an operating performance of a semiconductor memory device. The input frequency converter converts the first input test pattern signals into a plurality of second input test pattern signals with a second frequency in response to the first program control signal, and outputs the second input test pattern signals to the semiconductor memory device. The output frequency converter converts a plurality of second output test pattern signals with the second frequency received from the semiconductor memory device into the first output test pattern signals in response to the second program control signal and outputs the first output test pattern signals.

In one embodiment, the first input test pattern signals are first parallel data signals and the second input test pattern signals are first serial data signals, the input frequency converter includes a plurality of input signal converters, each of which receives a predetermined number of the first parallel data signals and outputs one of the first serial data signals, the first output test pattern signals are second parallel data signals and the second output test pattern signals are second serial data signals, and the output frequency converter includes a plurality of output signal converters, each of which receives one of the second serial data signals and outputs a predetermined number of the second parallel data signals. Each of the plurality of input signal converters can comprise: a control register, which is programmed in response to the first program control signal and outputs first and second control signals; a serial converter, which is enabled or disabled in response to the first control signal, converts the predetermined number of the first parallel data signals into the one of the first serial data signals when the serial converter is enabled, and outputs one of the first serial data signals; and a first delay device, which sets a first delay time in response to the second control signal, delays the one of the first serial data signals by the first delay time, and outputs the delayed one of the first serial data signals. The first delay times of the first delay devices are not necessarily set the same for all of input signal converters. The control register can further output a third control signal, and each of the input signal converters can further include a second delay device that sets a second delay time in response to the third control signal, delays the delayed one of the first serial data signals by the second delay time, and outputs the twice delayed one of the first serial data signals. The second delay time of the second delay device can be equal for all of the input signal converters. The number of the first parallel data signals to be input to each of the input signal converters can be determined according to a frequency of the first parallel data signals and an operating frequency of the semiconductor memory device to be tested. The first program control signal can include an identification signal for each of the input signal converters.

In one embodiment, each of the plurality of output signal converters comprises: a control register, which is programmed in response to the second program control signal and outputs first and second control signals; a first delay device, which sets a first delay time in response to the second control signal, delays the one of the second serial data signals by the first delay time, and outputs the delayed one of the second serial data signals; and a parallel converter, which is enabled or disabled in response to the first control signal, converts the one of the second serial data signals received from the first delay device into a predetermined number of the second parallel data signals when the parallel converter is enabled, and outputs the converted result.

In one embodiment, the first delay times of the first delay devices are not necessarily the same for all of output signal converters. The control register can further output a third control signal, and each of the input signal converters can further include a second delay device that sets a second delay time in response to the third control signal, delays the delayed one of the second serial data signals by the second delay time, and outputs the twice delayed one of the second serial data signals. In one embodiment, the second delay time of the second delay device is equal for all of the output signal converters. In one embodiment, the number of the second parallel data signals to be output from each of the output signal converters is determined according to a frequency of the second parallel data signals and an operating frequency of the semiconductor memory device to be tested. In one embodiment, the second program control signal includes an identification signal for each of the output signal converters.

In one embodiment, the main tester comprises: a test signal generator, which generates the first input test pattern signals; a defect analyzer, which receives the first output test pattern signals and detects the operating performance of the semiconductor memory device; a logic signal generator, which generates a first logic signal and a second logic signal; a first controller, which outputs the first program control signal in response to the first logic signal; and a second controller, which outputs the second program control signal in response to the second logic signal. In one embodiment, the first controller and the second controller are mode register set signal generators. In one embodiment, the first controller and the second controller are CMOS signal generators. According to another aspect of the present invention, there is provided a test apparatus for testing a plurality of semiconductor memory devices, the apparatus comprising a main tester, a plurality of input frequency converters, and a plurality of output frequency converters.

The main tester generates a plurality of first input test pattern signals with a first frequency, a first program control signal and a second program control signal, receives a plurality of first output test pattern signals with the first frequency, and determines operating performances of semiconductor memory devices. The input frequency converters convert the first input test pattern signals into a plurality of second input test pattern signals with a second frequency in response to the first program control signal, and output the second input test pattern signals to corresponding semiconductor memory devices. The input frequency converters are simultaneously enabled in response to the first program control signal. The output frequency converters convert a plurality of second output test pattern signals with the second frequency received from the semiconductor memory devices into the first output test pattern signals in response to the second program control signal, and output the first output test pattern signals. When one of the output frequency converters is enabled in response to the second program control signal, the remaining output frequency converters are disabled.

According to still another aspect of the present invention, there is provided a method of testing a semiconductor memory device comprising: (a) determining a number of first input test pattern signals to be generated; (b) connecting a main tester, a input frequency converter, and an output frequency converter, according to the determined number of the first input test pattern signals; (c) generating a first program control signal and a second program control signal and setting first output delay times of the input frequency converter and the output frequency converter; (d) connecting the semiconductor memory device between the input frequency converter and the output frequency converter; and (e) generating the first input test pattern signals, receiving first output test pattern signals, and determining an operating performance of the semiconductor memory device.

According to still yet another aspect of the present invention, there is provided a method of testing a plurality of semiconductor memory devices comprising: (a) determining a number of first input test pattern signals to be generated; (b) connecting a main tester, input frequency converters and output frequency converters by external data lines according to the determined number of the first input test pattern signals; (c) generating a first program control signal and a second program control signal and setting first output delay times of the input frequency converters and the output frequency converters; (d) connecting the semiconductor memory devices between the respective input frequency converters and output frequency converters; and (e) generating the first input test pattern signals, receiving first output test pattern signals, and determining an operating performance of each of the semiconductor memory devices.

In one embodiment, step (e) comprises: (e1) generating the first program control signal, thereby enabling all of the input frequency converters; (e2) inputting the first input test pattern signals to the input frequency converters; (e3) generating the second program control signal, thereby enabling the output frequency converters individually; (e4) receiving the first output test pattern signals from the enabled output frequency converter and determining an operating performance of a corresponding semiconductor memory device; and (e5) repeating steps (e3) and (e4) until all semiconductor memory devices are tested.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2is a block diagram of a test apparatus200and a semiconductor memory device300according to a first embodiment of the present invention. The test apparatus200includes a main tester201, an input frequency converter202, and an output frequency converter203. Output pins216of the main tester201are connected to input pins DIP1through DIPT (T is an integer greater than one) of the input frequency converter202. Also, the input pins227of the main tester201are connected to output pins COP1through COPT of the output frequency converter203.

The input frequency converter202and the output frequency converter203can be separated from the main tester201. Also, the input frequency converter202and the output frequency converter.203can be included in a single chip.

A high-frequency memory device300to be tested is connected between the input frequency converter202and the output frequency converter203. That is, output pins DOP1through DOPT of the input frequency converter202are connected to input pins301of the semiconductor memory device300, respectively, and input pins CIP1through CIPT of the output frequency converter203are connected to output pins302of the semiconductor memory device300, respectively.

The main tester201includes a test signal generator210, a defect analyzer220, a first controller230, a second controller240, and a logic signal generator250.

The test signal generator210includes a first timing generator211, a first ALPG212, a first format controller213, a first reference voltage generator214, and a driver215. The defect analyzer220includes a comparator221, a second reference voltage generator222, a digital comparator223, a second timing generator224, a second ALPG225, and a memory226. The logic signal generator250includes a third timing generator251, a third ALPG252, and a third format controller253.

InFIG. 2, it is shown that the first ALPG212, the second ALPG225, and the third ALPG252are separated from one another, in order to facilitate the understanding of the operations of the main tester201. Likewise, it is shown that the first timing generator211, the second timing generator224, and the third timing generator251are separated from one another, in order to facilitate the understanding of the operations of the main tester201.

The first timing generator211generates a first clock signal. A test period is determined by the period of the first clock signal. The first ALPG212generates pre-programmed logic data signals in synchronization with the first clock signal. The first format controller213outputs the logic data signals output from the first ALPG212to the driver215in synchronization with the first clock signal. The driver215amplifies the logic data signals to have an amplitude equal to a first reference voltage generated by the first reference voltage generator214, and outputs a plurality of parallel data signals DR1through DRK, . . . , DRM through DRN (K and M are integers greater than two with N=M+(K−1)) as test pattern signals.

The third timing generator251generates a third clock signal. The third ALPG252generates pre-programmed logic data signals in synchronization with the third clock signal. The third format controller253receives the logic data signals output from the third ALPG252and outputs a first logic signal LOG1and a second logic signal LOG2in synchronization with the third clock signal.

The first controller230controls the input frequency converter202in response to the first logic signal LOG1, and the second controller240controls the output frequency converter203in response to the second logic signal LOG2.

The first controller230and the second controller240can be mode register set signal generators or CMOS signal generators. When the first controller230and the second controller240are mode register set signal generators, mode register set signals MRS1and MRS2are output respectively to the input frequency converter202and the output frequency converter203, and when the first controller230and the second controller240are CMOS signal generators, first and second CMOS signals CMOS1and CMOS2, each including a clock signal SCK, a command signal CMD and a data signal SIO, are output to the input frequency converter202and the output frequency converter203, respectively.

Referring toFIG. 2, a case where the first controller230and the second controller240are CMOS signal generators will is described. The first controller230and the input signal converters SDI1through SDIT are connected by one line. However, the first controller230and the input signal converters SDI1and SDIT can be connected through a plurality of lines each transmitting the clock signal SCK, the command signal CMD, and the data signal SIO as the CMOS signal CMOS1. Similarly, the second controller240and the output signal converters SDO1through SDOT can be connected through a plurality of lines.

The input frequency converter202includes a plurality of input signal converters SDI1through SDIT. Each of the plurality of input signal converters SDI1through SDIT is initialized in response to the first CMOS signal CMOS1and the output delay of each of the input signal converters SDI1through SDIT is set by the first CMOS signal CMOS1.

The output frequency converter203includes a plurality of output signal converters SDO1through SDOT. Each of the output signal converters SDO1through SDOT is initialized by the second CMOS signal CMOS2and the output delay of each of the output signal converters SDO1through SDOT is set by the second CMOS signal CMOS2.

The input signal converters SDI1through SDIT receive the parallel data signals DR1through DRK, . . . , DRM through DRN, and output serial data signals DRS1through DRST, respectively. For example, the input signal converter SDI1converts the parallel data signals DR1through DRK into the serial data signal DRS1and outputs the serial data signal DRS1.

Here, the frequencies of the serial data signals DRS1through DRST can depend on the number of the parallel data signals DR1through DRK, . . . , DRM through DRN input to each of the input signal converters SDI1through SDIT.

For example, it is assumed that the main tester201outputs the plurality of parallel data signals DR1through DRK, . . . , DRM through DRN with a frequency of 250 MHz. Then, when 20 parallel data signals DR1through DR20, . . . , DRM through DR(M+19) are input to each of the input signal converters SDI1through SDIT, the input signal converters SDI1through SDIT output serial data signals DRS1through DRST at 2.5 GHz.

Also, when 10 parallel data signals DR1through DR10, . . . , DRM through DR(M+9) are input to each of the input signal converters SDI1through SDIT, the input signal converters SDI1through SDIT output serial data signals DRS1through DRST at 2.5 GHz.

As described above, the input signal converters SDI1through SDIT convert the parallel data signals DR1through DRK, . . . , DRM through DRN with a low frequency into serial data signals DRS1through DRST with a high frequency.

The plurality of serial data signals DRS1through DRST are respectively input to the input pins301of the semiconductor memory device300. The semiconductor memory device300outputs the serial data signals CPS1through CPST through the output pins302, in response to the serial data signals DRS1through DRST.

The output signal converters SDO1through SDOT respectively convert the high-frequency serial data signals CPS1through CPST output from the output pins302into low-frequency parallel data signals CP1through CPK, . . . , CPM through CPN. Each of the output signal converters SDO1through SDOT output the same number of parallel data signals as the number of input signals input to each of the input signal converters SDI1through SDIT. For example, the output signal converter SDO1converts the serial data signal CPS1into the plurality of parallel data signals CP1through CPK. If the input signal converter SDI1receives 10 parallel data signals DR1through DR10, the output signal converter SDO1also outputs 10 parallel data signals CP1through CP10. As a result, the low-frequency parallel data signals CP1through CPK, . . . , CPM through CPN are input to the comparator221.

The comparator221compares the parallel data signals CP1through CPK, . . . , CPM through CPN with a second reference voltage and outputs results of the comparison. The second reference voltage is generated by the second reference voltage generator222. The digital comparator223compares the output signals of the comparator221with logic data signals output from the second ALPG225in synchronization with the second clock signal, and stores results of the comparison in the memory226. The memory226stores the signals output by the digital comparator223in response to an address signal generated by the second ALPG225.

The plurality of input signal converters SDI1through SDIT will now be described in more detail with reference toFIGS. 3A and 3B.

FIG. 3Ais a block diagram of an input signal conversion unit according to a second embodiment of the present invention, andFIG. 3Bis a block diagram showing an input signal conversion unit according to a third embodiment of the present invention. InFIGS. 3A and 3B, the input signal converter SDI1is shown, however, the input signal converters SDI2through SDIT are implemented in the same manner as the input signal converter SDI1.

Referring toFIG. 3A, the input signal converter SDI1includes a control register410, a serial converter420, and a delay device430. The serial converter420includes an input register421, an internal clock generator422, a phase locked loop (PLL)423, a serializer424, and an output buffer425. The control register410is programmed by the first CMOS signal CMOS1received from the first controller230and outputs a plurality of control signals SCTL1and SCLT2.

The input register421receives a plurality of parallel data signals DR1through DRK from the driver215, temporally stores the signals, and outputs the plurality of parallel data signals DR1through DRK in response to an internal clock signal ICLK, which is generated by the internal clock generator422in response to a reference clock signal REF_CLK.

The PLL423receives the reference clock signal REF_CLK and generates a plurality of clock signals CK1through CK3. The serializer424is enabled or disabled in response to the control signal SCTL1. The serializer424receives the plurality of parallel data signals DR1through DRK from the input register421, and converts the plurality of parallel data signals DR1through DRK into a serial data signal DRS1in response to the plurality of clock signals CK1through CK3.

That is, the serializer424converts the plurality of parallel data signals DR1through DRK with a low frequency, such as 100 MHz, into the serial data signal DRS1with a high frequency, such as 1.5 GHz. The output buffer425outputs the serial data signal DRS1to the input pins301of a semiconductor memory device.

The delay device430is connected between the serializer424and the output buffer425. The delay device430sets a delay time in response to the control signal SCTL2and delays and outputs the serial data signal DRS1by the set delay time.

The delay device430compensates for skews between the serial data signal DRS1and serial data signals DRS2through DRST output from the input signal converters SDI2through SDIT.

More specifically, traces formed on a PCB, to respectively connect the input signal converters SDI1through SDIT with the input pins301of the semiconductor memory device have different lengths. As a result, times at which the serial data signals DRS1through DRST are respectively input to the input pins301of the semiconductor memory device are different from one another. Such skews between the serial data signals DRS1through DRST are compensated for by adjusting the delay time of the delay devices430of each of the input signal converters SDI1through SDIT.

That is, if the delay time of the delay device430of each of the input signal converters SDI1through SDIT is adjusted according to the lengths of the respective traces, the serial data signals DRS1through DRST can be simultaneously input to the semiconductor memory device300. Accordingly, the skews between the serial data signals DRS1through DRST are compensated for by the delay device430.

Referring toFIG. 3B, the input signal converter SDI1includes a control register440, a serial converter450, a first delay device460, and a second delay device470. The serial converter450includes an input register451, an internal clock generator452, a PLL453, a serializer454, and an output buffer455. The input signal converter SDI1ofFIG. 3Bis implemented in the same manner as the input signal converter SDI1ofFIG. 3Aexcept for two differences. A detailed description for the configuration and operation of the input signal converter ofFIG. 3Bis omitted except for the two differences.

A first difference is that the control register440further outputs a control signal SCTL3. A second difference is that the input signal converter SDI1includes the first delay device460and the second delay device470.

The first delay device460and the second delay device470are connected in series between the serializer454and the output buffer455. The first delay device460sets a first delay time in response to the control signal SCTL2, and the second delay device470sets a second delay time in response to the control signal SCTL3. The first delay device460delays the serial data signal DRS1received from the serializer454by the first delay time. Here, the first delay device460performs the same function as the delay device430ofFIG. 3A. Accordingly, the detailed description for the operation of the first delay device460is omitted.

The second delay device470delays the delayed serial data signal DRS1received from the first delay device460by the second delay time.

Here, the second delay times of the second delay device470of each of the input signal converters SDI1through SDIT are all equal and can be changed as necessary. As a result, the times at which the serial data signals DRS1through DRST are respectively input to the input pins301of the semiconductor memory device300, become faster or are delayed by the second delay device470. Accordingly, as the second delay time is changed, a valid data margin on the input side of the semiconductor memory device300can be estimated.

Next, referring toFIGS. 4A and 4B, the plurality of output signal converters SDO1through SDOT will be described in more detail.FIG. 4Ais a block diagram of an output signal conversion unit according to a fourth embodiment of the present invention, andFIG. 4Bis a block diagram of an output signal conversion unit according to a fifth embodiment of the present invention.

InFIGS. 4A and 4B, the output signal converter SDO1is shown, however, the output signal converters SDO2through SDOT are implemented in the same manner as the output signal converter SDO1.

Referring toFIG. 4A, the output signal converter SDO1includes a control register510, a parallel converter520, and a delay device530. The parallel converter520includes an input buffer521, a PLL522, a de-serializer523, and an output register524.

The control register510is programmed by a CMOS signal CMOS2received from the second controller240and outputs a plurality of control signals PCTL1and PCTL2. The input buffer521receives a serial data signal CPS1from the output pins302of the semiconductor memory device.

The delay device530is connected between the input buffer521and the de-serializer523. The delay device530sets a delay time in response to the control signal PCTL2and delays the serial data signal CPS1by the delay time.

The delay device530compensates for skews between the serial data signal CPS1and serial data signals CPS2through CPST input to the other output signal converters SDO2through SDOT.

More specifically, traces formed on a PCB, to respectively connect the output signal converters SDO1through SDOT with the output pins302of the semiconductor memory device, have different lengths. As a result, the times at which the serial data signals CPS1through CPST are respectively input to the respective de-serializers523of the output signal converters SDO1through SDOT are different from one another.

Such skews between the serial data signals CPS1through CPST are compensated for by adjusting the delay times of the respective delay devices530of the output signal converters SDO1through SDOT.

That is, if the delay times of the respective delay devices530of the output signal converters SDO1through SDOT are controlled according to the respective trace lengths, the serial data signals CPS1through CPST can be simultaneously input to the respective de-serializers523of the output signal converters SDO1through SDOT. Accordingly, the skews between the serial data signals CPS1through CPST are compensated for by the delay device530.

The de-serializer523is enabled or disabled in response to the control signal PCTL1. The de-serializer523receives the serial data signal CPS1from the delay device530and converts the serial data signal CPS1into a plurality of parallel data signals CP1through CPK in response to a plurality of clock signals CK1through CK3.

More specifically, the de-serializer523converts the serial data signal CPS1with a high frequency, such as 1.5 GHz, into the plurality of parallel data signals CP1through CPK with a low frequency, such as 100 MHz. The plurality of clock signals CK1through CK3are generated by the PLL522. Also, the de-serializer523generates a recovery clock signal RXCLK. The output register524receives the plurality of parallel data signals CP1through CPK and outputs the plurality of parallel data signals CP1through CPK to the comparator221in synchronization with the recovery clock signal RXCLK. As a result, the parallel data signals CP1through CPK with a low frequency are input to the comparator221.

Referring toFIG. 4B, the output signal converter SDO1includes a control register540, a parallel converter550, a first delay device560, and a second delay device570. The parallel converter550includes an input buffer551, a PLL552, a de-serializer553, and an output register554.

The output signal converter SDO1ofFIG. 4Bis implemented in the same manner as the output signal converter SDO1ofFIG. 4Aexcept for two differences. Accordingly, a detailed description for the configuration and operation of the output signal converter SDO1ofFIG. 4Bis omitted except for the two differences.

A first difference is that the control register540further outputs a control signal PCTL3. A second difference is that the output signal converter SDO1ofFIG. 4Bincludes the first delay device560and the second delay device570.

The first delay device560and the second delay device570are connected in series between the de-serializer553and the input buffer551. The first delay device560sets a first delay time in response to the control signals PCTL2and the second delay device570sets a second delay time in response to the control signal PCTL3. The first delay device560delays the serial data signal CPS1received from the input buffer551by the first delay time. The first delay device560performs the same function as the delay device530ofFIG. 4A. Accordingly, the detailed description for the operation of the first delay device560is omitted.

The second delay device570delays the delayed serial data signal CPS1received from the first delay device560by the second delay time.

Here, the second delay times of the respective second delay devices570of the output signal converters SDO1through SDOT are equal and can be changed as necessary. As a result, the times at which the serial data signals CPS1through CPST are respectively input to each of the de-serializers553of the output signal converters SDO1through SDOT, is shifted ahead or is delayed by the second delay device570. Accordingly, as the second delay time is changed, a valid data margin on the output side of the semiconductor memory device300can be measured.

Next, a method of testing a high-frequency semiconductor memory device using the test apparatus, according to a sixth embodiment of the present invention, will be described with reference toFIGS. 2,3B,4B and5.

FIG. 5is a flowchart illustrating a method of testing semiconductor memory devices using the test apparatus200, according to a sixth embodiment of the present invention.

Referring toFIG. 5, the number of test pattern signals, that is, the number of parallel data signals DR1through DRN, to be output from the main tester201is determined in step1101. The main tester201is connected with the input frequency converter202and the output frequency converter203according to the decided number of the test pattern signals in step1102.

More specifically, the number of the parallel data signals DR1through DRN to be input to the input frequency converter202is determined according to an operating frequency of a semiconductor memory device300to be tested and the frequencies of the parallel data signals DR1through DRN. Also, the number of the output signals of the output frequency converter203is equal to the number of the parallel data signals DR1through DRN.

For example, it is assumed that the operating frequency of the semiconductor memory device300is 2.5 GHz and the main tester201outputs the parallel data signals DR1through DRN at a frequency of 250 MHz.

The input pins DIP1through DIPT of the input signal converters SDI1through SDIT are connected to the output pins216of the main tester201so that 20 parallel data signals DR1through DR20, . . . , DRM through DR(M+19) are respectively input to the input signal converters SDI1through SDIT of the input frequency converter202. Also, the output pins COP1through COPT of the output signal converters SDO1through SDOT are connected to the input pins227of the main tester201so that the output signal converters SDO1through SDOT of the output frequency converter203output the 20 parallel data signals CP1through CP20, . . . , CPM through CP(M+19), respectively.

Next, the main tester201sets first output delay times of the input frequency converter202and the output frequency converter203in step1103. More specifically, in the main tester201, the first controller230outputs the first CMOS signal CMOS1in response to the first logic signal LOG1received from the third format controller253of the logic signal generator250. The respective control registers440of the input signal converters SDI1through SDIT are programmed by the first CMOS signal CMOS1and output a plurality of control signals SCTL1through SCTL2. The first controller230outputs the first CMOS signal CMOS1for each of the input signal converters SDI1through SDIT.

That is, the first CMOS signal CMOS1output from the first controller230includes an identification signal (hereinafter, referred to as ID signal) for each of the input signal converters SDI1through SDIT. Accordingly, the plurality of input signal converters SDI1through SDIT can be independently programmed by the first CMOS signal CMOS1.

The delay times of the respective first delay devices460of the input signal converters SDI1through SDIT are set in response to the control signal SCTL2. The delay times of the first delay devices460are not necessarily set equally.

The second controller240of the main tester201outputs the second CMOS signal CMOS2in response to the second logic signal LOG2received from the third format controller253. The second CMOS signal CMOS2output from the second controller240includes an ID signal for each of the output signal converters SDO1through SDOT. Accordingly, the output signal converters SDO1through SDOT can be independently programmed by the second CMOS signal CMOS2.

The respective control registers540of the output signal converters SDO1through SDOT are programmed by the second CMOS signal CMOS2and output a plurality of control signals PCTL1through PCTL2. The delay times of the respective first delay devices560of the plurality of output signal converters SDO1through SDOT are set in response to the control signal PCTL2. The delay times of the first delay devices560are not necessarily set equally.

Thereafter, the semiconductor memory device300is connected between the input frequency converter202and the output frequency converter203in step1104. That is, the output pins DOP1through DOPT of the plurality of input signal converters SDI1through SDIT are connected to the input pins301of the semiconductor memory device300and the input pins CIP1through CIPT of the plurality of output signal converters SDO1through SDOT are connected to the output pins302of the semiconductor memory device300.

The main tester201generates the test pattern signals, that is, the parallel data signals DR1through DRK, . . . , DRM through DRN and outputs the test pattern signals to the plurality of input signal converters SDI1through SDIT. Thereafter, the main tester201receives parallel data signals CP1through CPK, . . . , CPM through CPN from the plurality of output signal converters SDO1through SDOT and estimates an operating performance of the semiconductor memory device300in step1105.

By changing second output delay times of the input frequency converter202and the output frequency converter203, valid data margins of the input and output signals of the semiconductor memory device300are determined in step1106.

That is, the respective control registers440of the input signal converters SDI1through SDIT are programmed by the first CMOS signal CMOS1and further output control signals SCTL3.

The second delay time of the respective second delay device470of each of the input signal converters SDI1through SDIT is set in response to the control signal SCTL3. The second delay times of the second delay devices470are set equal in all of the input signal converters SDI1through SDIT.

Also, the respective control registers540of the output signal converters SDO1through SDOT are programmed by the second CMOS signal CMOS2and further output control signals PCTL3. The delay times of the respective second device570of the plurality of output signal converters SDO1through SDOT are set in response to the control signal PCTL3. The second delay times of the second delay devices570are set equal in all of the output signal converters SDO1through SDOT.

FIG. 6is a block diagram of a test apparatus600which selectively changes the frequencies of test pattern signals according to a seventh embodiment of the present invention and semiconductor memory devices D1through DS.

InFIG. 6, the test apparatus600includes a main tester601, a plurality of input frequency converters FI1through FIS, and a plurality of output frequency converters FO1through FOS. The configuration and operation of the main tester601is the same as those of the main tester201ofFIG. 2, and therefore the detailed description thereof is omitted. Also, inFIG. 6, for convenience of the description, only a driver611, a comparator621, a first controller630, and a second controller640are shown, while other components of the main tester601are omitted. Also, the first controller630and the second controller640implemented by CMOS signal generators inFIG. 6can, however, be implemented by mode register set signal generators.

The first controller630and the second controller640output first and second CMOS signals CMOS1and CMOS2each including a clock signal SCK, a command signal CMD, and a data signal SIO.

The plurality of input frequency converters FI1through FIS and the plurality of output frequency converters FO1through FOS can be connected to the main tester601or separated therefrom. Also, the plurality of input frequency converters FI1through FIS and the plurality of output frequency converters FO1through FOS can be implemented by a single chip.

High frequency semiconductor memory devices D1through DS to be tested are respectively connected between the plurality of input frequency converters FI1through FIS and the plurality of output frequency converters FO1through FOS.

The plurality of input frequency converters FI1through FIS include a plurality of input signal converters DI11through DI1T, . . . , DIS1through DIST (T and S are integers greater than one), and the plurality of output frequency converters FO1through FOS include a plurality of output signal converters DO11through DO1T, . . . , DOS1through DOST.

For example, the input signal converter DI11converts the parallel data signals DR1through DRK into a serial data signal DRS1.

The frequency of each of the serial data signals DRS1through DRST is changed according to the number of the parallel data signals DR1through DRK, . . . , DRM through DRN respectively input to the input signal converters DI11through DI1T, . . . , DIS1through DIST.

It is assumed that the main tester601outputs the plurality of parallel data signals DR1through DRK, . . . , DRM through DRN at a frequency of 250 MHz. When 20 parallel data signals DR1through DR20, . . . , DRM through DR(M+19) are input to each of the input signal converters DI11through DI1T, . . . , DIS1through DIST, the input signal converters DI11through DI1T, . . . , DIS1through DIST output the serial data signals DRS1through DRST of 2.5 GHz.

As described above, the input signal converters DI11through DI1T, . . . , DIS1through DIST convert the parallel data signals DR1through DRK, . . . , DRM through DRN with a low frequency into the serial data signals DRS1through DRST with a high frequency.

The serial data signals DRS1through DRST are input to the semiconductor memory devices D1through DS, respectively. Each of the semiconductor memory devices D1through DS output a plurality of serial data signals CPS1through CPST in response to the serial data signals DRS1through DRST.

The output signal converters DO11through DO1T, . . . , DOS1through DOST convert the serial data signals with a high frequency received from the semiconductor memory devices D1through DS into a plurality of parallel data signals CP1through CPK, . . . , CPM through CPN with a low frequency. Each of the output signal converters DO11through DO1T, . . . , DOS1through DOST output the same number of parallel data signals as the number of signals input to each of the input signal converters DI11through DI1T, . . . , DIS1through DIST.

For example, the output signal converter DO11converts the serial data signal CPS1into the parallel data signals CP1through CPK. If the input signal converter DI11receives 10 parallel data signals DR1through DR10, the output signal converter D011outputs the 10 parallel data signals CP1through CP10. As a result, the parallel data signals CP1through CPK, . . . , CPM through CPN with a low frequency are input to the comparator622.

Each of the input signal converters DI11through DI1T, . . . , DIS1through DIST is initialized in response to the first CMOS signal CMOS1output from the first controller630and programmed by the first CMOS signal CMOS1to be enabled or disabled, thereby setting an output delay time.

The first CMOS signal CMOS1includes an ID (indentification) signal for each of the input signal converters DI11through DI1T, . . . , DIS1through DIST. Accordingly, the input signal converters DI11through DI1T, . . . , DIS1through DIST are independently programmed by the first CMOS signal CMOS1.

Each of the output signal converters DI11through DI1T, . . . , DIS1through DIST are initialized in response to the second CMOS signal CMOS2output from the second controller640and programmed by the second CMOS signal CMOS2to be enabled or disabled, thereby setting an output delay time.

The second CMOS signal CMOS2includes an ID signal for each of the output signal converters DO11through DO1T, . . . , DOS1through DOST. Accordingly, the output signal converters DO11through DO1T, . . . , DOS1through DOST are independently programmed by the second CMOS signal CMOS2.

InFIG. 6, the first controller630and the input signal converters DI11through DI1T, . . . , DIS1through DIST connected to each other by a single line can however be connected through a plurality of lines respectively transmitting a clock signal SCK, a command signal CMD, and a data signal SIO, as the first CMOS signal CMOS1. Similarly, the second controller640and the output signal converters DO11through DO1T, . . . , DOS1through DOST can also be connected by a plurality of lines.

The configuration and operation of each of the input signal converters DI11through DI1T, . . . , DIS1through DIST are the same as those of the input signal converters SDI1ofFIGS. 3A and 3B, and therefore, a detailed description thereof are not repeated. Also, the configuration and operation of each of the output signal converters DO11through DO1T, . . . , DOS1through DOST are the same as those of the output signal converters SDO1ofFIGS. 4A and 4B, and therefore the detailed descriptions thereof are not repeated.

A method of testing the semiconductor memory devices D1through DS using the test apparatus600described above will now be described with reference toFIGS. 6 through 8.

FIG. 7is a flowchart illustrating a method of testing semiconductor memory devices using the test apparatus that selectively changes the frequencies of the test pattern signals, according to an eighth embodiment of the present invention ofFIG. 6.FIG. 8is a flowchart illustrating a method of estimating operating performances of the semiconductor memory devices shown inFIG. 7.

Referring toFIG. 7, the number of test pattern signals, that is, the number of the parallel data signals DR1through DRN to be output from the main tester601, is determined in step1210. The main tester601, the input frequency converters FI1through FIS, and the output frequency converters FO1through FOS are connected to each other by the external data lines CWI1through CWIT and CWO1through CWOT according to the determined number of the parallel data signals DR1through DRN in step1220.

More specifically, the number of the parallel data signals DR1through DRN to be input to each of the input frequency converters FI1through FIS is determined according to the operating frequencies of the semiconductor memory devices D1through DS to be tested and the frequencies of the parallel data signals DR1through DRN.

Also, the number of the output signals of the output frequency converters FO1through FOS is set equal to the number of the parallel data signals DR1through DRN.

For example, it is assumed that the main tester601outputs the parallel data signals DR1through DRN at 250 MHz. It is also assumed that the operating frequencies of the semiconductor memory devices D1through DS are 2.5 GHz. Then, the input pins IP11through IPIT, . . . , IPS1through IPST of the input signal converters DI11through DI1T, . . . , DIS1through DIST are connected to the output pins612of the driver611of the main tester601by external data lines CWI1through CWIT, so that 20 parallel data signals DR1through DR20, are input to each of the input signal converters DI11through DIS1and 20 parallel data signals DRM through DR(M+19) are input to each of the input signal converters DI1T through DIST.

Also, the output pins OP11through OP1T, . . . , OPS1through OPST of the output signal converters DO11through DO1T, . . . , DOS1through DOST are connected to the input pins622of the comparator621of the main tester601so that each of the output signal converters DO11through DOS1outputs 20 parallel data signals CP1through CP20and each of the output signal converters DO1T through DOST outputs 20 parallel signals CPM through CP(M+19).

Next, the main tester601sets first output delay times of the input frequency converters FI1through FIS and the output frequency converters FO1through FOS in step1230. More specifically, the first controller630of the main tester601outputs the first CMOS signal CMOS1. The respective input signal converters DI11through DI1T, . . . , DIS1through DIST of the input frequency converter FI1through FIS are programmed by the first CMOS signal CMOS1, thereby setting the first output delay time.

The first output delay times of the input signal converters DI11through DI1T, . . . , DIS1through DIST are not necessarily set to be equal. As a result, the semiconductor memory devices D1through DS simultaneously receive serial data signals DRS1through DRST from the input signal converters DI11through DI1T, . . . , DIS1through DIST.

The first controller630outputs the first CMOS signal CMOS1for each of the input signal converters DI11through DI1T, . . . , DIS1through DIST. That is, the first CMOS signal CMOS1output from the first controller630includes an ID signal for each of the input signal converters DI11through DI1T, . . . , DIS1through DIST. Accordingly, the input signal converters DI11through DI1T, . . . , DIS1through DIST can be independently programmed by the first CMOS signal CMOS1.

The second controller640of the main tester601outputs the second CMOS signal CMOS2. The second CMOS signal CMOS2includes an ID signal for each of the output signal converters DO11through DO1T, . . . , DOS1through DOST. Accordingly, the output signal converters D011through DO1T, . . . , DOS1through DOST can be independently programmed by the second CMOS signal CMOS2.

Each of the output signal converters DO11through DO1T, . . . , DOS1through DOST is programmed by the second CMOS signal CMOS2, thereby setting a first output delay time.

The first output delay times of the output signal converters DO11through DO1T, . . . , DOS1through DOST are not necessarily set to be equal. As a result, the plurality of output signal converters DO11through DO1T, . . . , DOS1through DOST simultaneously receive the serial data signals CPS1through CPST from the semiconductor memory devices D1through DS.

The semiconductor memory devices D1through DS are then respectively connected between the input frequency converters FI1through FIS and the output frequency converters FO1through FOS in step1240. For example, the output terminals of the input signal converters DI11through DI1T of the input frequency converter FI1are connected to the input terminals of the semiconductor memory device D1and the input terminals of the output signal converters DO11through DO1T of the output frequency converter FO1are connected to the output terminals of the semiconductor memory device D1.

Thereafter, the main tester601generates test pattern signals, that is, the parallel data signals DR1through DRK, . . . , DRM through DRN and determines the operating performances of the semiconductor memory devices D1through DS in step1250. Step1250will now be described in more detail with reference toFIG. 8.

First, the first controller630outputs the first CMOS signal CMOS1and enables the input frequency converters FI1through FIS connected to the semiconductor memory devices D1through DS in step1251. Then, the driver611outputs the test pattern signals, that is, the parallel data signals DR1through DRK, . . . , DRM through DRN to the input frequency converters FI1through FIS in step1252. The parallel data signals DR1through DRK, . . . , DRM through DRN are simultaneously input to the input frequency converters FI1through FIS.

The parallel data signals DR1through DRK, . . . , DRM through DRN with low frequencies are converted into serial data signals DRS1through DRST with high frequencies by the input frequency converters FI1through FIS. Each of the semiconductor memory devices D1through DS outputs serial data signals CPS1through CPST in response to the serial data signals DRS1through DRST.

The serial data signals CPS1through CPST are output to the output frequency converters FO1through FOS, respectively. The output frequency converters FO1through FOS respectively convert the serial data signals CPS1through CPST with high frequencies into the parallel data signals CP1through CPK, . . . , CPM through CPN with low frequencies.

Then, the second controller640outputs the second CMOS signal CMOS2and enables each of the output frequency converters FO1through FOS individually in step1253. That is, when one of the output frequency converter FO1through FOS is enabled, the remaining output frequency converters are disabled.

The main tester601receives the output signals of the enabled output frequency converters and determines the operating performance of a corresponding semiconductor memory device in step1254. For example, when the output frequency converter FO1is enabled, the main tester601receives the parallel data signals CP1through CPK, . . . , CPM through CPN from the output frequency converter FO1and compares the parallel data signals CP1through CPK, . . . , CPM through CPN with reference signals, thereby measuring the performance of the semiconductor memory device D1. The main tester601determines whether a next semiconductor memory device to be estimated exists in step1255. When the semiconductor memory device to be estimated exists in step1255, the method is returned to step1253, and when no next semiconductor memory device to be estimated exists, the method is terminated.

Referring toFIG. 7, by changing the second output delay times of the input frequency converters FI1through FIS and the output frequency converters FO1through FOS, valid data margins of the input and output signals of the semiconductor memory devices D1through DS are determined in step1260.

That is, the respective input signal converters DI11through DI1T, . . . , DIS1through DIST of the input frequency converters FI1through FIS are respectively programmed by the first CMOS signal CMOS1, thereby setting the second output delay time.

The second output delay times of the input signal converters DI11through DI1T, . . . , DIS1through DIST are set to be equal. As a result, the times at which the semiconductor memory devices D1through DS receive the serial data signals DRS1through DRST can be changed simultaneously.

Also, the respective output signal converters DO11through DO1T, . . . , DOS1through DOST of the output frequency converters FO1through FOS are respectively programmed by the second CMOS signal CMOS2, thereby simultaneously setting the second output delay time.

At this time, the second output delay times of the output signal converters DO11through DO1T, . . . , DOS1through DOST are set equally. As a result, the times at which the output signal converters DO11through DO1T, . . . , DOS1through DOST receive the serial data signals CPS1through CPST output from the semiconductor memory devices D1through DS, can be changed at the same time.

Similarly to step1253, the input frequency converters FI1through FIS are simultaneously enabled in response to the first CMOS signal CMOS1and the output frequency converters FO1through FOS are enabled singly in response to the second COMS signal CMOS2, in step1254. As a result, the main tester601can measure a valid data margin for each semiconductor memory device.

FIG. 9is a block diagram of a test apparatus700that selectively changes the frequency of a test pattern signal and semiconductor memory devices D1through DS, according to a ninth embodiment of the present invention.

Referring toFIG. 9, the test apparatus700includes a main tester701, a plurality of input frequency converters FI1through FIS, and a plurality of output frequency converters FO1through FOS.

Here, the test apparatus700has the same configuration as the test apparatus600ofFIG. 6except for a few differences, and therefore, a detailed description for the configuration and operation of the test apparatus700, except for the differences, is omitted.

When semiconductor memory devices D1through DS to be tested have input/output pins having input/output functions, both the output terminals of the input frequency converters FI1through FIS and the input terminals of the plurality of output frequency converters FO1through FOS are connected to input/output pins D1P through DSP of the semiconductor memory devices D1through DS.

As described above, the test apparatus and method according to exemplary embodiments of the present invention can test semiconductor memory devices with a high frequency by selectively changing the frequencies of test pattern signals.

Also, the test apparatus and method according to exemplary embodiments of the present invention can test semiconductor memory devices with various operating frequencies and can simultaneously test a plurality of semiconductor memory devices, thereby reducing testing costs.