Semiconductor devices

Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2015-0081701, filed on Jun. 10, 2015 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference herein in its entirety.

BACKGROUND

The present disclosure relates to semiconductor devices. As recent memory devices have been highly integrated and downsized, the size of active regions has been also reduced in a semiconductor substrate. Thus, the gate resistance and the threshold voltage may increase due to the decrease of the gate width and the channel length in cell transistors. Particularly, the decrease of the channel length in a metal oxide semiconductor field effect transistor (MOSFET) may cause the deterioration of gate channel characteristics, which is a phenomenon known as a short channel effect.

In addition, the size reduction of the active region may increase proximity between the gate electrode and the source junction and between the gate electrode and the drain junction, thus generating an excessive electric field between the gate electrode and the source/drain junctions that may cause a gate-induced drain leakage (GIDL). Further, the gate current may pass toward the source/drain junctions, which is a phenomenon known as current leakage.

Accordingly, the size reduction of semiconductor devices has brought about various technologies for addressing the short channel effect and current leakage. For example, it has been suggested to provide a fin gate structure in which the gate electrode protrudes into a fin shape and to expand the channel, or to provide a gate-all-around (GAA) structure in which the channel is enclosed by the gate electrode, or to provide a multichannel structure in which a single gate electrode contacts a plurality of the channels, or to provide various vertical transistors including one of the above fin gate structures, GAA structures, or multichannel structures. Moreover, a nano wire channel transistor has been suggested for high performance with a low power. In a nano wire channel transistor, the channel of the GAA structure is replaced with a nano wire channel.

However, the size reduction of semiconductor devices may increase parasitic capacitance and electrical resistance as well as the short channel effect and current leakage, so that a vertical transistor may benefit from decreasing the parasitic capacitance and the electrical resistance for a stable operation. Particularly, when the line width of the gate electrode is decreased to a few/several nanometers, the width of the gate spacer also decreases and as a result, the parasitic capacitance may become very high between the gate electrode and the adjacent contact. In addition, the width reduction of the gate electrode and the contact may increase the electrical resistance of the gate electrode and the contact.

SUMMARY

Various example embodiments of present inventive concepts may provide semiconductor devices in which the gate electrode is positioned in an insulation layer under an active fin and has a beneficially/sufficiently low capacitance between the gate electrode and the contact. Moreover, some example embodiments of present inventive concepts provide methods of manufacturing the semiconductor devices.

According to some embodiments of present inventive concepts, a semiconductor device may include a semiconductor substrate including a base body and a body insulator on the base body. The body insulator may extend in a first direction and may include a channel trench that extends in a second direction. The semiconductor device may include a semiconductor region on the body insulator around the channel trench. The semiconductor device may include a channel connected with the semiconductor region across the channel trench in the first direction. The semiconductor device may include a gate structure enclosing the channel and filling the channel trench along the second direction. The gate structure may include a first portion, including a first thickness, on the channel and a second portion, including a second thickness thicker than the first thickness, that fills the channel trench.

In some embodiments, the semiconductor substrate may be a silicon-on-insulator (SOI) substrate that includes the base body, the body insulator, and a semiconductor layer on the body insulator such that the channel trench extends between the semiconductor layer and the base body. Moreover, the channel may include a single nanowire contacting the semiconductor region across the channel trench in the first direction such that end portions of the channel are on the body insulator at respective sides of the channel trench.

According to some embodiments, the semiconductor device may include a gate spacer between the first portion of the gate structure and the semiconductor region and extending upward from one of the end portions of the channel. The semiconductor device may include an insulating region on the gate structure such that an upper surface of the insulating region is coplanar with an upper surface of the gate spacer. Moreover, the semiconductor device may include a contact structure contacting the semiconductor region adjacent the gate spacer.

In some embodiments, an upper surface of the first portion of the gate structure may be lower than the upper surface of the gate spacer. Moreover, a lower surface of contact structure may be lower than a lower surface of the first portion of the gate structure and higher than an upper surface of the second portion of the gate structure.

According to some embodiments, the semiconductor device may include an insulation interlayer on the semiconductor region such that an upper surface of the contact structure, the upper surface of the gate spacer, and the upper surface of the insulating region are coplanar with an upper surface of the insulation interlayer.

In some embodiments, the contact structure may include a lower contact region including a first width in the semiconductor region. Moreover, the contact structure may include an upper contact region connected to the lower contact region in one body and including a second width that is wider than the first width such that the upper contact region extends to contact the gate spacer.

According to some embodiments, the gate structure may include a third portion that is connected to the second portion of the gate structure and extends in the first direction, so that a third width of the third portion of the gate structure is wider than a fourth width of the second portion of the gate structure.

In some embodiments, the channel may include a plurality of unit channels vertically spaced apart by a same gap distance and contacting the semiconductor region in the first direction such that opposite end portions of a lowermost unit channel are on the body insulator, the second portion of the gate structure is between the lowermost unit channel and the base body, and the first portion of the gate structure is on an uppermost unit channel.

According to some embodiments, the semiconductor device may include a gate spacer between the first portion of the gate structure and the semiconductor region and extending upward from an end portion of the uppermost unit channel. The semiconductor device may include a channel spacer between a pair of neighboring unit channels and between the gate structure and the semiconductor region. The semiconductor device may include an insulating region on the gate structure such that an upper surface of the insulating region is coplanar with an upper surface of the gate spacer. Moreover, the semiconductor device may include a contact structure that contacts the semiconductor region adjacent the gate spacer.

In some embodiments, the channel spacer may have a same width as the gate spacer such that the gate spacer vertically overlaps the channel spacer and a side surface of the channel spacer is vertically aligned with a side surface of the gate spacer.

According to some embodiments, the contact structure may include a first contact region including a first width in the semiconductor region. The contact structure may include a second contact region connected to the first contact region in one body and including a second width that is wider than the first width such that the second contact region extends to contact the gate spacer. Moreover, the gate structure may include a third portion between the second portion and the base body. The third portion of the gate structure may extend in the first direction such that a third width of the third portion of the gate structure is wider than a fourth width of the second portion of the gate structure.

A method of manufacturing a semiconductor device, according to some embodiments, may include forming a dummy gate line on a fin-shaped active region that protrudes from a body insulator of a semiconductor substrate. The method may include forming a semiconductor region on the fin-shaped active region adjacent the dummy gate line such that the dummy gate line is separated from the semiconductor region by a gate spacer and such that source and drain regions are on opposite sides of the dummy gate line, respectively. The method may include removing the dummy gate line to expose the fin-shaped active region and to form a gate trench and a channel that contacts the semiconductor region through the gate trench. The method may include forming a channel trench under the channel by partially removing the body insulator in the gate trench such that the channel trench is connected with the gate trench and a bottom of the channel trench is spaced apart from the channel. The method may include forming a preliminary gate structure that fills the channel trench and the gate trench and encloses the channel. Moreover, the method may include forming a gate structure including an upper surface lower than an upper surface of the gate spacer. The gate structure may include a first portion in the channel trench and including a first thickness and a second portion overlapping the channel and including a second thickness that is thinner than the first thickness of the first portion of the gate structure.

In some embodiments, the fin-shaped active region may include a semiconductor material, and forming the semiconductor region may include epitaxially growing single crystalline silicon from the fin-shaped active region. Moreover, forming the channel may include forming an insulation interlayer pattern on the semiconductor region such that the gate spacer and the dummy gate line are exposed through the insulation interlayer pattern. Forming the channel may include removing the dummy gate line from the substrate by an etching process using the insulation interlayer pattern and the gate spacer as an etching mask, thereby forming the gate trench through which the fin-shaped active region is exposed. Forming the channel may include forming the fin-shaped active region in the gate trench into the channel connected to the semiconductor region.

According to some embodiments, forming the preliminary gate structure may include planarizing a gate insulation layer and a gate conductive layer, to form a gate insulation pattern on a surface of the channel and on a side surface of the gate spacer in the gate trench, and to provide a preliminary gate conductive pattern that fills the channel trench and the gate trench. Moreover, forming the gate structure may include removing an upper portion of the preliminary gate conductive pattern until the preliminary gate conductive pattern remains on the channel to a thickness smaller than a depth of the channel trench, so that the second thickness is thinner than the first thickness and an upper portion of the gate trench is formed into a recess.

In some embodiments, the method may include forming an insulating region in the recess such that an upper surface of the insulating region is coplanar with an upper surface of the insulation interlayer pattern. Moreover, the method may include forming a contact structure penetrating through the insulation interlayer pattern and contacting the semiconductor region.

According to some embodiments, forming the contact structure may include forming a lower contact region including a first width in the semiconductor region. Moreover, forming the contact structure may include forming an upper contact region connected to the lower contact region in one body and including a second width that is wider than the first width such that the upper contact region extends to contact the gate spacer.

A semiconductor device, according to some embodiments, may include a substrate including a semiconductor base and an insulator on the semiconductor base. The semiconductor device may include a source/drain region on the substrate. The semiconductor device may include a semiconductor channel adjacent the source/drain region. The semiconductor device may include a gate structure including a first portion on the channel and a second portion in the insulator of the substrate, such that the channel is between the first and second portions of the gate structure. Moreover, the semiconductor device may include a contact structure in the source/drain region. The contact structure may have an end portion adjacent a side surface of the channel.

In some embodiments, the source/drain region may be a source region, and the semiconductor device may include a drain region on the substrate. Moreover, the channel and the first portion of the gate structure may be between the source region and the drain region.

According to some embodiments, a first thickness of the first portion of the gate structure may be thinner than a second thickness of the second portion of the gate structure. The semiconductor device may include an insulating region on the first portion of the gate structure. Moreover, a third thickness of the insulating region may be thicker than the first thickness of the first portion of the gate structure.

In some embodiments, the substrate may be a Silicon-on-Insulator (SOI) substrate, and the semiconductor channel may be provided by a fin-shaped semiconductor layer that protrudes from the insulator of the SOI substrate. Moreover, the semiconductor device may include a gate spacer including an uppermost surface that is coplanar with an uppermost surface of the insulating region.

A semiconductor device, according to some embodiments, may include a fin-shaped semiconductor layer providing a channel of the semiconductor device. The semiconductor device may include a gate structure including a first portion including a first thickness above the channel and a second portion including a second thickness below the channel and thicker than the first thickness. The semiconductor device may include an insulating region on the first portion of the gate structure. The insulating region may include a third thickness thicker than the first thickness. Moreover, the semiconductor device may include a contact structure that extends adjacent a portion of a side surface of the channel.

In some embodiments, the second portion of the gate structure may include different first and second widths. One of the first and second widths of the second portion of the gate structure may be wider than a third width of the first portion of the gate structure. The semiconductor device may include a source/drain region that contacts the channel. Moreover, a fourth width of the contact structure may be outside of the source/drain region and may be wider than a fifth width of the contact structure that is in the source/drain region.

According to some embodiments, the channel may be a gate-all-around (GAA) channel or a nanowire channel. Moreover, the semiconductor device may include a gate spacer including an uppermost surface that is coplanar with an uppermost surface of the insulating region.

Therefore, according to various embodiments, the overlap area of the contact structure and the gate structure may decrease while increasing the overlap area of the contact structure and the supplementary insulating member, thus the overlap area between the contact structure and the gate structure may be limited to being between the contact structure and the covering portion, and parasitic capacitance may be sufficiently reduced/minimized between the contact structure and the gate structure. Particularly, parasitic capacitance between the contact structure and the gate structure may be sufficiently reduced/prevented even when the gate spacer may become narrow due to the size reduction of the semiconductor device.

In addition, the upper portion of the contact structure and the lower portion of the gate structure may be horizontally expanded and thus the surface area of the contact structure and the gate structure may increase. Thus, the electrical resistance of the contact structure and the gate structure may be stable and reliable in spite of the size reduction of the semiconductor device

DETAILED DESCRIPTION

Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the spirit and teachings of this disclosure and so the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout the description.

It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a “first” element could be termed a “second” element without departing from the teachings of the present embodiments.

Accordingly, the cross-sectional view(s) illustrated herein provide support for a plurality of devices according to various embodiments described herein that extend along two different directions in a plan view and/or in three different directions in a perspective view. For example, when a single active region is illustrated in a cross-sectional view of a device/structure, the device/structure may include a plurality of active regions and transistor structures (or memory cell structures, gate structures, etc., as appropriate to the case) thereon, as would be illustrated by a plan view of the device/structure.

FIG. 1Ais a plan view illustrating a semiconductor device in accordance with some example embodiments of present inventive concepts.FIGS. 1B and 1Care cross-sectional views cut along a line I-I′ and a line II-II′ ofFIG. 1A, respectively. InFIGS. 1A to 1C, the line I-I′ extends along a fin shaped active region of the semiconductor device and the line II-II′ extends along a gate line of the semiconductor device.

Referring toFIGS. 1A to 1C, the semiconductor device1000may include a semiconductor substrate100having a base body101and a body insulator102covering the base body101and having a channel trench CT that may extend in a second direction y, a semiconductor junction300arranged on the body insulator102around the channel trench CT, a channel Ch connected with the semiconductor junction300across the channel trench CT, and a gate structure500enclosing the channel Ch and filling the channel trench CT in the second direction y. The gate structure500may include a covering portion520acovering the channel Ch and having a covering thickness T1and a filling portion520bfilling up the channel trench CT and having a filling thickness T2greater than the covering thickness T1.

For example, the semiconductor substrate100may include any substrates as long as the substrate may include an insulator by which upper and lower portions of the substrate may be electrically separated, together with semiconductor characteristics. In some example embodiments, the substrate100may include a silicon-on-insulator (SOI) substrate in which a pair of silicon layers may be separated by an insulation layer. Thus, the substrate100may include a semiconductor base body101, a body insulator102covering the base body101and a semiconductor substrate layer that may cover the body insulator102and may be formed into the channel Ch of the semiconductor device1000.

The semiconductor device1000may include a logic device, an image sensor device such as a CMOS image sensor and a memory device such as a flash memory device and DRAM device. Thus, the substrate100may be varied in accordance with characteristics and requirements of the semiconductor devices1000.

The base body101may include single crystalline silicon and the body insulator102may include silicon oxide. The semiconductor substrate layer may include single crystalline silicon that may be formed into the channel Ch of the semiconductor device1000.

The channel trench CT may be recessed to a sufficient depth from the surface of the body insulator102and may extend in the second direction y along which a gate line may extend. The gate structure500may be partially inserted into the channel trench CT and a plurality of the gate structures500may be connected in a line in the second direction y as the gate line of the semiconductor device1000. Therefore, since the height of the gate structure at each cell may be reduced, the contact area between the gate structure and the gate spacer210may be reduced and thus the parasitic capacitance may be sufficiently reduced between the contact structure620and the gate conductive pattern520.

An active region may be defined on the semiconductor substrate layer and may be isolated from surroundings by the underlying body insulator102. In some example embodiments, the semiconductor substrate layer may protrude into a plurality of line-shaped fins on the body insulator102along the first direction x, so the nearest/neighboring line-shaped fin may be isolated by the body insulator102. That is, the line-shaped fin may function as the active region and the body insulator102may function as a device isolation layer. Hereinafter, the line-shaped fin type active region defined by the body insulator102is referred to as an active fin.

The semiconductor junction (e.g., a semiconductor region)300may be provided on the active fin and may include source junctions310and drain junctions320opposite to each other with respect to the gate structure500. Thus, the active fin may be connected to the semiconductor junction300and the active fin interposed between the source and drain junctions310and320may function as a channel for moving charges from the source junction310to the drain junction320. The semiconductor junction300may be referred to herein as a semiconductor region. Moreover, the source junctions310and drain junctions320may be referred to herein as source and drain regions, respectively.

The semiconductor junction300may, in one example, include semiconductor materials that may be grown from the active fin and may comprise p type or n type dopants.

In some example embodiments, an epitaxial layer may be formed on the active fin and p-type or n-type dopants may be implanted into the epitaxial layer, thereby forming the source and drain junctions310and320. Thus, the semiconductor junction300may be formed into an elevated source and drain (ESD) structure in such a configuration that an upper surface of the semiconductor junction300may be higher than an upper surface of the channel Ch.

The semiconductor junction300may comprise any material selected from the group consisting of silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC), indium gallium arsenide (InGaAs) and combinations thereof. The dopants of the semiconductor junction300may be implanted as deep as depths/levels of the channel Ch.

The source junction310and the drain junction320may be connected with each other by the channel Ch and the channel Ch may be enclosed by the gate structure500. Thus, the channel Ch may be operated by the gate structure500and may function as a switch element for selectively moving the charges.

The channel Ch may include a nano wire structure that may be arranged on the body insulator102and may be connected with the source and drain junctions310and320. Particularly, a single nano wire extending in the first direction x may be provided as the channel Ch and may make contact with the semiconductor junction300across the channel trench CT in such a configuration that both end portions of the channel Ch may be positioned on the body insulator102at both sides of the channel trench CT, respectively.

Since some of the semiconductor substrate layer on the body insulator102may be formed into the channel Ch, the compositions of the channel Ch may be varied according to those of the semiconductor layer. For example, the channel Ch may comprise any materials selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe), indium gallium arsenide (InGaAs), indium arsenide (InAs), gallium antimonide (GaSb), indium antimonide (InSb) and combinations thereof. In some example embodiments, the channel Ch may include silicon (Si) since the active fin may be formed of silicon (Si).

Particularly, the channel Ch may be enclosed by the gate structure500and thus the charge flow through the channel Ch may be controlled by a gate current that may be applied to the gate structure500.

For example, the gate structure500may include a gate insulation pattern510enclosing the channel Ch and a gate conductive pattern520on the gate insulation pattern510in such a way that the channel trench CT and a lower portion of the gate trench GT may be filled with the gate conductive pattern520. A supplementary insulating member611may be further arranged on the gate conductive pattern520and an upper portion of the gate trench GT may be filled with the supplementary insulating member611. Therefore, the gate structure500may be isolated from surroundings and protected from subsequent processes. The supplementary insulating member611may be referred to herein as an insulating region.

Since the upper portion of the gate trench GT may be defined by the gate spacer210and the gate structure500and may be filled with the supplementary insulating member611, the overlap area of the contact structure620and the gate structure500that may be opposite to each other with respect to the gate spacer210(hereinafter, referred to as capacitance area) may be reduced and thus the parasitic capacitance between the contact structure620and the gate structure500may be reduced when the semiconductor device1000may be sufficiently downsized. For example, the supplementary insulating member611may comprise any material of silicon oxide, silicon nitride and silicon oxynitride.

The gate structure500may be shaped in a line extending in the second direction y, so that the supplementary insulating member611may also be shaped in a line extending in the second direction y.

The gate spacer210may also extend in the second direction y and may cover both sides of the gate structure500and the supplementary insulating member611. Particularly, an upper surface of the gate spacer210may be coplanar with an upper surface of the supplementary insulating member611.

A lower portion of the gate conductive pattern520may be inserted into the channel trench CT and thus the gate conductive pattern520may be partially arranged in the body insulator102. In contrast, an upper portion of the gate conductive pattern520may be arranged adjacent to the channel Ch in such a way that an upper surface of the gate conductive pattern520may be lower than an upper surface of the semiconductor junction300. Therefore, the gate conductive pattern520may include the covering portion520athat may be protruded over the channel Ch and may overlap (e.g., cover) an upper portion of the channel Ch and the filling portion520bthat may fill up the channel trench CT and may extend under (e.g., cover) a lower portion of the channel Ch. Thus, the channel Ch may be enclosed by the covering portion520aand the filling portion520b.

Particularly, the covering portion520amay have a covering thickness T1on the channel Ch and the filling portion520bmay have a filling thickness T2below the channel Ch in such a configuration that the covering thickness T1may be smaller than the filling thickness T2. The covering portion520amay have the covering thickness T1as small as possible on the condition that the channel Ch is sufficiently covered with gate conductive materials and the filling portion520bmay have a sufficient thickness for compensating for the deterioration of the electric characteristics caused by the height reduction of the gate structure500. Thus, the filling thickness T2may be sufficiently greater than the covering thickness T1and thus the gate structure500may be arranged in a reverse structure such that a larger portion thereof may be arranged below the channel Ch and a smaller portion thereof may be arranged on the channel Ch.

As a result, the contact area between the gate spacer210and the supplementary insulating member611may increase and the contact area between the gate spacer210and the gate conductive pattern520may be reduced/minimized in the semiconductor device1000, which may reduce the parasitic capacitance between the contact structure620and the gate structure500. For example, the filling thickness T2may be about 1.5 to about 2.5 times of the covering thickness T1.

In some example embodiments, the channel trench CT may be formed by an over-etch process against the body insulator102to a depth of about 1.0 to about 1.5 times of the thickness t of the channel Ch and an upper portion of the gate conductive pattern520may be partially removed from the substrate100until the covering thickness T1may be smaller than the depth/thickness of the channel trench CT.

The gate insulation pattern510may comprise dielectric materials such as silicon oxide, silicon oxynitride, high-k materials having a dielectric constant greater than silicon oxide and combinations thereof. Examples of the dielectric materials for the gate insulation pattern510may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), aluminum oxide (Al2O3) and combinations thereof. The gate conductive pattern520may comprise conductive materials such as doped polysilicon, metal and combinations thereof. Examples of the conductive materials for the gate conductive pattern520may include aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbon nitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN) and combinations thereof.

The gate structure500may be spaced apart from the semiconductor junction300and the gate spacer210may be interposed between the gate structure500and the semiconductor junction300, so that a side surface of the gate spacer210may make contact with the gate insulation pattern510and an opposite side surface of the gate spacer210may make contact with the semiconductor junction300. Thus, the gate structure500and the semiconductor junction300may be electrically separated from each other by the gate spacer210. For example, the gate spacer210may include silicon nitride and an upper surface of the gate spacer210may be coplanar with upper surfaces of the gate insulation pattern510and the supplementary insulating member611.

An insulation interlayer pattern410may be arranged on the substrate100in such a way that the semiconductor junction300may be covered by the insulation interlayer pattern410and the gate spacer210and the supplementary insulating member611may be exposed through the insulation interlayer pattern410. The contact structure620may penetrate into the semiconductor junction300through the insulation interlayer pattern410. For example, the contact structure620may include a single plug that may be inserted into the semiconductor junction300through the insulation interlayer pattern410, preferably to a position close to the channel Ch.

Particularly, an upper surface of the insulation interlayer pattern410may be coplanar with the upper surfaces of the gate spacer210and the supplementary insulating member611. The contact structure620may make contact with a wiring structure or a capacitor that may be arranged on the insulation interlayer pattern410.

Since the supplementary insulating member611may be coplanar with the upper surfaces of the insulation interlayer pattern410and the gate spacer210and may be arranged on the gate conductive pattern520, the gate spacer210may make contact with the insulation materials across a larger contact area than the gate spacer210may contact the conductive materials.

In conventional semiconductor devices, the gate conductive pattern is positioned substantially at the same height, the contact structure and the gate structure may be opposite to each other in the first direction with respect to the gate spacer. Thus, a size reduction may reduce the thickness of the gate spacer, which may increase the parasitic capacitance between the contact structure and the gate structure in the conventional semiconductor device.

In contrast, in some example embodiments of the semiconductor devices, a larger portion of the gate conductive pattern520may be arranged under the channel Ch rather than on the channel Ch and the supplementary insulating member611may be arranged on the gate conductive pattern520in such a configuration that the upper surface of the supplementary insulating member611may be coplanar with the upper surface of the gate spacer210. Therefore, the capacitance area between the contact structure620and the gate conductive pattern520, which may be opposite to each other with respect to the gate spacer210, may be sufficiently reduced.

In some example embodiments, the supplementary insulating member611may have a height H of about 20 nm to about 40 nm from the upper surface of the gate conductive pattern520.

Accordingly, the capacitance area between the contact structure620and the gate structure500may be reduced to an area just between the contact structure620and the covering portion520a, so that the parasitic capacitance may be reduced/minimized between the contact structure620and the gate structure500in spite of the reduction of the width Wgs of the gate spacer210.

Further, the contact resistance of the contact structure620and the gate resistance of the gate structure500may also decrease just by increasing the width of the contact structure620and the gate conductive pattern520.

Since the supplementary insulating member611may be arranged on the gate conductive pattern520and may comprise insulation materials instead of conductive materials and the contact structure620may face the supplementary insulating member611, with the gate spacer210therebetween, the contact structure620may be expanded over the gate spacer210and thus the surface area of the contact structure620may increase without any increase of the parasitic capacitance. In addition, the process margin may also increase in forming the contact structure620.

In the same way, the channel trench CT may also be expanded in the first direction x to thereby form an expansion trench and as a result, the lower portion of the gate conductive pattern520may also be expanded in the first direction x. Therefore, the surface area of the gate conductive pattern520may increase and the electrical resistance of the gate structure500may decrease. That is, the gate driving voltage may decrease just by expanding the channel trench CT in the body insulator102.

FIG. 2Ais a plan view illustrating a modification of the semiconductor device shown inFIG. 1A.FIGS. 2B and 2Care cross-sectional views cut along a line I-I′ and a line II-II′ ofFIG. 2A, respectively. InFIGS. 2A to 2C, the modified semiconductor device has substantially the same structures as the semiconductor device shown in FGIS.1A to1C, except that the contact structure and the gate conductive pattern are expanded, so the same reference numerals denote the same elements inFIGS. 1A to 1C. Further detailed descriptions on the same elements may be omitted hereinafter.

Referring toFIGS. 2A to 2C, the gate structure500may include an expanded gate conductive pattern525having a covering portion525a, a filling portion525band an expanding portion525c. The covering portion525amay cover the upper portion of the channel Ch and the filling portion525bmay cover the lower portion of the channel Ch and fill up the channel trench CT. The expanding portion525cmay be provided under the filling portion525band may fill an expanded trench ET that may be communicated/connected with the channel trench CT. The expanded trench ET may be arranged under the channel trench CT and may have a second width W2larger than a first width W1of the channel trench CT. The covering portion525aand the filling portion525bmay have substantially the same structures as the covering portion520aand the filling portion520bof the semiconductor devices1000shownFIGS. 1B and 1C, thus any further descriptions on the covering portion525aand the filling portion525bmay be omitted.

An etching process for forming the channel trench CT may be further performed against the body insulator102and an additional trench may be formed contiguously/consecutively to the channel trench CT in such a way that the additional trench may be expanded in the first direction x, so that the expanded trench ET may be formed under the channel trench CT to the second width W2greater than the first width W1of the channel trench CT. In some example embodiments, the expanded trench ET may have a depth of about 2 nm to about 3 nm.

Gate conductive materials may be filled into the gate trench GT, the channel trench CT and the expanded trench ET, and the expanding portion525cmay be formed in the expanded trench ET as well as the covering portion525ain the gate trench GT and the filling portion525bin the channel trench CT, thereby forming the expanded gate conductive pattern525. Since the surface area of the gate structure500may increase due to the expanded portion525c, the electrical resistance of the gate structure500may decrease and as a result, the driving voltage applied to the gate structure500may also be decreased. Particularly, when the widths of the gate trench GT and the channel trench CT may decrease unexpectedly and thus the widths of the covering portion525aand the filling portion525bmay be over reduced, the expanding portion525cmay compensate for the reduction of the covering portion525aand the filling portion525b, thereby reducing/preventing the increase of the overall resistance of the gate structure500.

Further, an upper portion of the contact structure620may be expanded in the first direction x, thereby forming an expanded contact structure625to cover the gate spacer210. That is, the expanded contact structure625may include a lower contact625a(e.g., a lower contact region) inserted into the semiconductor junction300and having a lower width Wland an upper contact625b(e.g., an upper contact region) making contact with both of the semiconductor junction300and the gate spacer210in one body with the lower contact625a. The upper contact625bmay have an upper width Wugreater than the lower width Wlof the lower contact625a. The lower contact625aand the upper contact625bmay be referred to herein as respective contact regions.

The lower contact625amay include a contact plug that may be inserted into the semiconductor junction300and the upper contact625bmay be combined with the lower contact625ain one body and be extended in the first direction x to cover the gate spacer210. As a result, the upper width Wuof the upper contact625bmay be greater than the lower width Wlof the lower contact625a, thereby decreasing the contact resistance and increasing the process margin for forming the expanded contact structure625.

While some example embodiments disclose that the upper contact625bmay expand in the first direction x until the gate spacer210may be covered with the upper contact625band the supplementary insulating member611(e.g., an insulating/insulation region) may make contact with the upper contact625b, the upper contact625bmay, in some embodiments, extend/expand over the supplementary insulting member611such that the supplementary insulation member611may be partially overlapped by the upper contact625bas long as a pair of the neighboring upper contacts625bmay be electrically separated from each other by the supplementary insulting member611.

In addition, while some example embodiments disclose the lower contact625amay penetrate a single insulation interlayer pattern410and may make contact with the semiconductor junction300, a multilayer structure may be provided as the insulation interlayer pattern410and the lower contact625amay penetrate at least one of the layers in the multilayer structure.

According to the above example embodiments of the semiconductor device1000, the gate structure may fill up the channel trench in the body insulator and may enclose the channel in such a configuration that the filling portion of the gate structure filling in the channel trench has a greater width than the covering portion of the gate structure on the channel and the covering portion may be lower than the gate spacer. The supplementary insulating member may be positioned on the gate structure in such a way that the upper surface of the supplementary insulating member may be coplanar with the upper surface of the gate spacer.

Therefore, the overlap area of the contact structure and the gate structure may decrease and the overlap area of the contact structure and the supplementary insulating member may increase, thereby sufficiently reducing/minimizing the parasitic capacitance between the contact structure and the gate structure. Particularly, the parasitic capacitance between the contact structure and the gate structure may be sufficiently reduced/prevented even when the gate spacer may become narrow due to a size reduction of the semiconductor device.

In addition, the upper portion of the contact structure and the lower portion of the gate structure may be horizontally expanded and thus the surface area of the contact structure and the gate structure may increase. Thus, the electrical resistance of the contact structure and the gate structure may be stable and reliable in spite of a size reduction of the semiconductor device.

FIGS. 3A to 14Bare views illustrating the processing steps for a method of manufacturing the semiconductor devices shown inFIGS. 1A to 1C. InFIGS. 3A to 14B, the alphabetic letter A in each figure number denotes a plan view of each processing step and the alphabetic letter B in each figure number denotes a cross-sectional view cut along the line I-I′ inFIG. 1A.

Referring toFIGS. 3A and 3B, the semiconductor substrate100having the body insulator102may be provided for manufacturing the semiconductor device1000.

For example, a silicon-on-insulator (SOI) substrate may be provided as the semiconductor substrate100in which the body insulator102may be formed on the base body101comprising silicon (Si) and the semiconductor substrate layer103may be formed on the body insulator102.

The base body101may include a semiconductor plate comprising single crystalline silicon and a silicon oxide layer may be formed on the base body101by an oxidation process. The oxide layer on the base body101may be provided as the body insulator102. Any other insulation layer, as an alternative to the silicon oxide layer, may be utilized as the body insulator102as long as a pair of the neighboring active fins may be electrically insulated by the insulation layer and the insulation layer may have a sufficient etching selectivity with respect to the gate spacer210and the channel Ch in a subsequent etching process.

The semiconductor substrate layer103may be formed to a sufficient thickness on the body insulator102and may comprise semiconductor materials such as silicon (Si). Various semiconductor materials may be utilized for the substrate layer103as long as the substrate layer103may function as an active region for manufacturing the semiconductor device1000.

In some example embodiments, the substrate layer103may include single crystalline silicon (Si) and may be formed into the channel Ch in a subsequent process.

Referring toFIGS. 4A and 4B, the active fin110may be formed on the body insulator102in such a way that the active fin110may protrude from the body insulator102and may be shaped into a line extending in the first direction x

For example, a mask pattern may be formed on the substrate layer103and the substrate layer103may be partially removed from the body insulator102by an etching process using the mask pattern an etching mask. A dry etching process such as a reactive ion etching (ME) process may be used for removing the substrate layer103.

Thus, the residuals of the substrate layer103on the body insulator102may be formed into the active fin110that may protrude from the body insulator102and may function as an active region on which conductive structures of the semiconductor device1000may be arranged. In such a case, the body insulator102may function as a device isolation layer and neighboring ones of the active fins110may be isolated from each other by the body insulator102.

Referring toFIGS. 5A and 5B, a dummy gate layer120amay be formed on the substrate100to a sufficient thickness to cover the active fin110and a dummy mask pattern M may be formed on the dummy gate layer120ain a shape of a line extending in the second direction y.

For example, the dummy gate layer120amay include polysilicon having an etching rate larger than that of the active fin110in a subsequent etching process and the dummy mask pattern M may include silicon nitride having an etching selectivity with respect to polysilicon.

Particularly, the active fin110may extend in the first direction x and the dummy mask pattern M may extend in the second direction y substantially perpendicular to the first direction x. Therefore, the active fin110and the dummy mask pattern M may be perpendicular to each other.

Referring toFIGS. 6A and 6B, the dummy gate layer120amay be partially removed from the substrate100by an etching process using the dummy mask pattern M as an etching mask, thereby forming the dummy gate line120extending in the second direction y.

The dummy gate layer120aexposed by the dummy mask pattern M may be removed from the substrate100and thus the active fin110and the body insulator102may be exposed to surroundings and the dummy gate layer120acovered by the dummy mask pattern M may remain on the substrate100in a shape of a line extending in the second direction y, thereby forming the dummy gate line120along the second direction y. Thus, the active fin110extending in the first direction x may be partially covered by the dummy gate line120extending in the second direction y.

Since the active fin110and the dummy gate line120may cross each other, the active fin110may be divided into two portions by the dummy gate line120and each of the divided portions of the active fin110may be formed into source and drain junctions/regions in a subsequent process.

Referring toFIGS. 7A and 7B, the gate spacer210may be formed on each sidewall of the dummy gate line120so that the gate spacer210may also extend in the second direction y at each side of the dummy gate line120. For example, the dummy gate line120may include silicon nitride.

Referring toFIGS. 8A and 8B, the semiconductor junction300(e.g., a semiconductor region) may be formed on the active fin110that may be exposed by the gate spacer210and the dummy gate line120.

For example, a single crystalline layer may be formed on portions of the active fin110by an epitaxial growth process using the active fin110as a seed layer, thereby forming a semiconductor growth layer on the active fin110that may make contact with a side surface of the gate spacer210. The semiconductor growth layer may include silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC) and combinations thereof in consideration of electric characteristics of the semiconductor device1000.

Then, a plurality of dopants may be implanted into the semiconductor growth layer by an ion implantation process, thereby forming the semiconductor junction300including the source junction310and the drain junction320. One of p-type dopants or n-type dopants may be implanted into the divided portions of the active fin110. Particularly, the semiconductor junction300may be formed into an elevated structure by the epitaxial growth process and the dopants may be implanted around the active fin110. Thus, the dummy gate line120may be separated from the semiconductor junction300by the gate spacer210and the source and drain junctions310and320may be arranged at both sides of the dummy gate line120, respectively. The source and drain junctions310and320may be formed at both ends the channel Ch.

The epitaxial growth process and the implantation process may be performed in-situ with each other, and thus the dopant concentration may be uniform in the semiconductor junction300and the electrical resistance of the semiconductor junction300may be reduced/minimized.

The active fin110under the dummy gate line120may be formed into the channel Ch through which the source and drain junctions310and320may be connected.

Referring toFIGS. 9A and 9B, the insulation interlayer pattern410may be formed on the semiconductor junction300and the gate spacer210, and the dummy gate line120may be exposed through the insulation interlayer pattern410.

An insulation interlayer may be formed on the substrate100to a sufficient thickness to cover the semiconductor junction300, the gate spacer210and the dummy gate line120. Then, the insulation interlayer may be partially removed from the substrate100by a planarization process until the gate spacer210and the dummy gate line120may be exposed. The dummy mask pattern M may be removed in the planarization process together with the insulation interlayer.

Accordingly, the insulation interlayer may remain just on the semiconductor junction300to thereby form the insulation interlayer pattern410through which the gate spacer210and the dummy gate line120may be exposed.

Various materials may be utilized for the insulation interlayer pattern410as long as the insulation interlayer pattern410may have a sufficient etching selectivity with respect to the dummy gate line120in an etching process for removing the dummy gate line120. For example, the insulation interlayer pattern410may include one of silicon oxide, silicon nitride and silicon oxynitride.

Referring toFIGS. 10A and 10B, the dummy gate line120may be removed from the body insulator102until the active fin110may be exposed, thereby forming a gate trench GT through which the active fin110may be exposed. The active fin110in the gate trench GT may be formed into the channel Ch extending in the first direction x and making contact with the semiconductor junction300.

The dummy gate line120may be removed from the body insulator102by an etching process using the gate spacer210and the insulation interlayer pattern410as an etching mask, to thereby form the gate trench GT that may be defined by a pair of the gate spacers210and the body insulator102and may have a first gate space GS1. Since the active fin110may have an etching selectivity with respect to dummy gate line120, the active fin110may function as an etch stop member to the etching process for forming the gate trench GT and the active fin110may be exposed through the gate trench GT.

The active fin110in the gate trench GT may be formed into the channel Ch of which the end portions may make contact with the source and drain junctions310and320, respectively.

Since the channel Ch may be formed from the substrate layer103on the body insulator102and the source and drain junctions310and320may be locally grown from some portions of the substrate layer103close to both sides of the dummy gate line120, the channel Ch and the source/drain junctions310and320may be connected on the body insulator102.

Referring toFIGS. 11A and 11B, the body insulator102that may be exposed through the gate trench GT may be further removed/etched from the substrate100, thereby forming the channel trench CT that may be communicated/connected with the gate trench GT.

For example, the body insulator102may be further etched off from the substrate100by an anisotropic etching process using the gate spacer210as an etching mask. Since the active fin110may include single crystalline silicon and the body insulator102may include silicon oxide, the body insulator102may be much more rapidly etched off than the active fin110in the anisotropic etching process. Thus, the body insulator102under the active fin110may be recessed with the same width of the gate trench GT in a shape of a line extending along the second direction y, thereby forming the channel trench CT having the second gate space GS2that may be communicated/connected with the first gate space GS1. The second gate space GS2may be referred to herein as a recess.

The active fin110partially etched off by the anisotropic etching process may be formed into the channel Ch that may be spaced apart from the bottom of the channel trench CT. Thus, the channel Ch may cross over the channel trench CT along the first direction x and both end portions of the active fin110that may be covered with the gate spacer210may be connected to the semiconductor junction300without being etched.

The depth of the channel trench CT may be controlled by the variation of the process conditions of the anisotropic etching process in consideration of the characteristics of the gate structure500and the thickness t of the channel Ch. In some example embodiments, the channel trench CT may have the same depth as the width t of the channel Ch.

Particularly, the channel Ch may be formed into a nano wire that may cross over the channel trench CT in the first direction x and may be enclosed by the gate conductive pattern520in a subsequent process such as by forming a gate all-around channel (GAA).

In a modified example embodiment, a bottom portion of the channel trench CT may be expanded in the first direction x and the expanded trench ET may be further formed under the channel trench CT.

FIG. 11Cis a cross-sectional view illustrating a processing step for further forming the expanded trench ET under the channel trench CT.

Referring toFIG. 11C, when the etching process for forming the channel trench CT may reach the terminal point, the process conditions of the etching process may be changed into isotropic conditions from the anisotropic conditions and the isotropic over etching process may be performed to the body insulator102. Thus, the body insulator102may be further etched off in both of the first direction x and a depth direction, thereby forming the expanded trench ET having a second width W2greater than the first width W1of the channel trench CT and communicated/connected with the channel trench CT. Therefore, the size of the expanded trench ET may be varied by the process conditions of the isotropic over etching process in view of the size of the gate structure500that may be inserted into the body insulator102.

The expanded portion525cof the expanded gate structure525inFIG. 2Bmay be formed by filling the expanded trench ET with gate conductive materials.

Referring toFIGS. 12A and 12B, a preliminary gate structure500amay be formed in the gate trench GT and the channel trench CT in such a way that the channel Ch may be enclosed by the preliminary gate structure500a.

For example, the preliminary gate structure500amay be formed by node-separating a stack layer of a gate insulation layer and a gate conductive layer at each gate trench GT by a planarization process in such a way that a gate insulation pattern510may be formed on a surface of the channel Ch and the side surface of the gate spacer210in the gate trench GT and a preliminary gate conductive pattern529may be filled into the channel trench CT and the gate trench GT. Particularly, the gate insulation layer may be formed on the body insulator102along a surface profile of the substrate100having the gate trench GT and the channel trench CT. Thus, the gate insulation layer may be formed on side surfaces of the gate trench GT and on upper surfaces of the insulation interlayer pattern410and the gate spacer210. In such a case, the channel Ch may be enclosed and covered by the gate insulation layer. Then, the gate conductive layer may be formed on the gate insulation layer to a sufficient thickness to fill up the channel trench CT and the gate trench GT, and then the gate conductive layer and the gate insulation layer may be planarized until a top surface of the insulation interlayer pattern410and the gate spacer210may be exposed. Therefore, the gate insulation layer and the gate conductive layer may be node-separated by the gate trench GT, thereby forming the preliminary gate structure500ahaving the gate insulation pattern510and the preliminary gate conductive pattern529.

The gate insulation pattern510may comprise dielectric materials such as silicon oxide, silicon oxynitride, high-k materials having a dielectric constant greater than silicon oxide and combinations thereof. Examples of the dielectric materials for the gate insulation pattern510may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), aluminum oxide (Al2O3) and combinations thereof. The preliminary gate conductive pattern529may comprise conductive materials such as doped polysilicon, metal and combinations thereof. Examples of the conductive materials for the preliminary gate conductive pattern529may include aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbon nitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN) and combinations thereof.

In some example embodiments, the body insulator102and the gate insulation pattern510may include silicon oxide and the gate spacer210may include silicon nitride. Thus, the gate insulation pattern510may be formed only on the channel Ch and the side surfaces of the gate trench GT and may not be formed on the side surfaces and the bottom of the channel trench CT. However, the gate insulation pattern510may be formed on the side surfaces and the bottom of the channel trench CT when the compositions of the gate insulation pattern510and the body insulator102may be changed.

Referring toFIGS. 13A and 13B, an upper portion of the preliminary gate structure500amay be removed from the substrate100, and thus the gate structure500may be formed in a lower portion of the gate trench GT and the channel trench CT.

For example, the preliminary gate conductive pattern529may be partially etched from the substrate100by an etching process using the gate spacer210and the insulation interlayer pattern410as an etching mask, and thus the upper portion of the preliminary gate conductive pattern529may be etched off from the gate trench GT. Therefore, the upper portion of the gate trench GT may be opened again and a supplementary insulation hole SH may be provided at the upper portion of the gate trench GT.

In such a case, the preliminary gate conductive pattern529may be etched in such a way that the channel Ch may be sufficiently covered by the residuals of the preliminary gate conductive pattern529while an upper surface of the residuals of the preliminary gate conductive pattern529may be lower than the upper surface of the semiconductor junction300around the channel Ch.

In some example embodiments, the preliminary gate conductive pattern529may be etched to a depth of about 20 nm to about 40 nm, so that the supplementary insulation hole SH may have the depth of about 20 nm to about 40 nm from the upper surface of the gate spacer210.

Accordingly, the preliminary gate conductive pattern529may be formed into the gate conductive pattern520that may cover the channel Ch and simultaneously fill up the channel trench CT. Thus, the gate conductive pattern520may include a covering portion520athat may protrude from the channel Ch to a covering thickness T1and may cover an upper portion of the channel Ch and a filling portion520bthat may fill up the channel trench CT with a filling thickness T2and may cover a lower portion of the channel Ch. Particularly, the covering thickness T1of the covering portion520amay be controlled to be smaller than the filling thickness T2of the filling portion520b. The covering portion520amay be exposed to surroundings through the supplementary insulation hole SH.

In a modified example embodiment, the gate insulation pattern510in the supplementary insulation hole SH may be further removed from the gate spacer210if necessary.

The same process as described in detail with reference toFIGS. 12A to 13Bmay be performed to the substrate100having the expanded trench ET shown inFIG. 11C, thereby forming the expanded gate conductive pattern525including the expanded portion525cshown inFIG. 2B.

Referring toFIGS. 14A and 14B, the supplementary insulating member611may be formed in the supplementary insulation hole SH in such a way that an upper surface of the supplementary insulating member611may be coplanar with the upper surface of the insulation interlayer pattern410.

For example, a supplementary insulating layer may be formed on the insulation interlayer pattern410to a sufficient thickness to fill up the supplementary insulation hole SH. Then, the supplementary insulating layer may be planarized until the upper surface of the insulation interlayer pattern410may be exposed, thereby forming the supplementary insulating member611in the supplementary insulation hole SH. Therefore, the supplementary insulating member611may have a height H of about 20 nm to about 40 nm.

Various insulation materials may be utilized for the supplementary insulating layer as long as the supplementary insulating layer may be sufficiently adhered to the covering portion520aof the gate conductive pattern520. For example, the supplementary insulating layer may include any one of silicon oxide, silicon nitride, silicon oxynitride and combinations thereof.

Referring toFIGS. 15A and 15B, the contact structure620may penetrate through the insulation interlayer pattern410and may make contact with the semiconductor junction300.

For example, an additional insulation layer612may be formed on the substrate100having the insulation interlayer pattern410, the gate spacer210and the supplementary insulating member611, and the contact structure620may penetrate through the additional insulation layer612and the insulation interlayer pattern410.

The additional insulation layer612may include any one of silicon oxide, silicon nitride, silicon oxynitride and combinations thereof. Otherwise, the additional insulation layer612may have the same materials as the insulation interlayer pattern410.

Particularly, the supplementary insulating member611and the additional insulation layer612may include the same materials that may be formed on the substrate100in the same process. The supplementary insulating layer may be planarized to a uniform thickness on the insulation interlayer pattern410, thereby forming the additional insulation layer612together with the supplementary insulating member611in one body. In such a case, the supplementary insulating member611and the additional insulation layer612may have the same insulation materials.

A contact hole618may be formed through the additional insulation layer612and the insulation interlayer pattern410, and a conductive layer may be formed on the additional insulation layer612to a sufficient thickness to fill up the contact hole618. Then, the conductive layer may planarized until an upper surface of the additional insulation layer612may be exposed, thereby forming the contact structure620filling up the contact hole618and making contact with the semiconductor junction300. The contact structure620may include low-resistive metals such as tungsten (W), titanium (Ti), tantalum (Ta) and aluminum (Al).

In some embodiments, a metal silicide layer may be formed between the semiconductor junction300and the contact structure620, thereby reducing contact resistance of the contact structure620.

Thereafter, wiring structures connected to the contact structure620and other upper conductive structures may be further formed on the additional insulation layer612together with a passivation layer enclosing the wiring structure and the upper conductive structures, thereby manufacturing the semiconductor devices1000.

In some modified example embodiments, an upper portion of the contact structure620may be enlarged to thereby decrease the contact resistance thereof.

FIG. 15Cis a cross-sectional view illustrating a processing step for a method of enlarging the upper portion of the contact structure shown inFIG. 15B.

Referring toFIG. 15C, an expanded contact hole619may be formed on/into the semiconductor junction300through the additional insulation layer612and the insulation interlayer pattern410. The expanded contact hole619may include an upper hole619bpenetrating through the additional insulation layer612and the insulation interlayer pattern410and a lower hole619arecessed in the semiconductor junction300.

For example, after forming the contact hole618by the same process as described in detail with reference toFIG. 15B, the additional insulation layer612and the insulation interlayer pattern410may be further horizontally removed in the first direction x, so that an upper portion of the contact hole618may be expanded in the first direction x. Thus, the contact hole618maintained unchanged in the semiconductor junction300may be formed in the lower hole619ahaving a lower width Wland the expanded contact hole619expanded in the additional insulation layer612and the insulation interlayer pattern410may be formed to include the upper hole619bhaving an upper width Wu.

Particularly, an upper portion of the gate spacer210may be removed from the substrate100together with the insulation interlayer pattern410when expanding the upper portion of the contact hole618, so that an upper surface of the gate spacer210may be exposed through the upper hole619b. When the insulation interlayer pattern410and the gate spacer210may comprise the same materials and the supplementary insulating member611may comprise different materials from the insulation interlayer pattern410and the gate spacer210, the upper hole619bmay be accurately/precisely expanded over the gate spacer210and the side surface of the supplementary insulating member611may be exposed through the upper hole619b.

Thereafter, conductive materials may be filled into the expanded contact hole619to thereby form the expanded contact structure625of which the upper portion may be expanded over the gate spacer210in the first direction x.

Thus, the expanded contact structure625may include a lower contact625athat may be inserted into the semiconductor junction300and having the lower width Wland an upper contact625bmaking contact with both of the semiconductor junction300and the gate spacer210in one body with the lower contact625a. The upper contact625bmay have the upper width Wugreater than the lower width Wl. That is, the expanded structure625may include a plug that may be inserted into the semiconductor junction300and an expansion top integrally formed with the plug in one body and having an enlarged surface area.

Therefore, the expanded contact structure625may have a larger surface area than the contact structure620, thereby reducing the contact resistance and increasing the process margin for forming the contact structure.

While some example embodiments disclose that the supplementary insulating member611may be exposed through the upper hole619band thus the upper hole619bmay be defined by the supplementary insulating pattern611, a side portion of the supplementary insulating member611may be further removed together with the gate spacer210and the upper hole619bmay partially overlap the supplementary insulating member611. In such a case, the supplementary insulating member611may be overlapped by the upper contact625bas long as neighboring ones of the upper contacts625bmay be electrically separated from each other by the supplementary insulting member611.

According to the above example embodiments of the method of manufacturing semiconductor devices, the channel trench CT may be formed under the channel Ch in the body insulator102and the gate structure500may be formed to fill up the channel trench CT and to enclose the channel Ch. The gate structure500may include the covering portion520aon the channel Ch and the filling portion520bin the channel trench CT. The covering portion520amay have a covering thickness T1as small/thin as possible on the condition that the channel Ch may be sufficiently covered with gate conductive materials and the filling portion520bmay have a sufficient thickness T2for compensating for the deterioration of the electric characteristics caused by the height reduction of the gate structure500.

Thus, the filling thickness T2may be sufficiently greater than the covering thickness T1and the gate structure500may be arranged in a reverse structure such that a larger portion may be arranged below the channel Ch and a smaller portion may be arranged on the channel Ch. Therefore, the overlap area of the contact structure620and the gate structure500may decrease and thus the parasitic capacitance may be reduced/minimized between the contact structure620and the gate structure500. Particularly, the parasitic capacitance between the contact structure620and the gate structure500may be sufficiently reduced/prevented even when the gate spacer210may become narrow due to a size reduction of the semiconductor device1000.

In addition, the upper portion of the contact structure620and the lower portion of the gate structure500may be horizontally expanded and thus the surface area of the contact structure620and the gate structure500may increase. Thus, the electrical resistance of the contact structure620and the gate structure500may be stable and reliable in spite of the size reduction of the semiconductor device1000.

FIG. 16Ais a plan view illustrating a semiconductor device in accordance with some example embodiments of present inventive concepts.FIGS. 16B and 16Care cross-sectional views cut along a line I-I′ and a line II-II′ ofFIG. 16A, respectively. InFIGS. 1A to 1C, the line I-I′ extends along a fin shaped active region of the semiconductor device and the line II-II′ extends along a gate line of the semiconductor device. The semiconductor device inFIGS. 16A to 16Chas substantially the same structures as the semiconductor device inFIGS. 1A to 1C, except for the number/quantity of channels. Thus, inFIGS. 16A to 16C, the same reference numerals denote the same elements inFIGS. 1A to 1Cand any further detailed descriptions on the same elements may be omitted hereinafter,

Referring toFIGS. 16A to 16C, the semiconductor device1001in accordance with some example embodiments of present inventive concepts may include the channel Ch having a plurality of unit channels Ch1to Ch3that may be vertically spaced apart by the same gap distance on and over the body insulator102and make contact with the semiconductor junction300in the first direction x.

In some example embodiments, the channel Ch may include a lowermost unit channel Ch1arranged on the body insulator102and crossing over the channel trench CT, a middle unit channel Ch2spaced apart from the lowermost unit channel Ch1in a third direction z by the gap distance and extending in parallel with the lowermost unit channel Ch1and an uppermost unit channel Ch3spaced apart from the middle unit channel Ch2in the third direction z by the gap distance and extending in parallel with the middle unit channel Ch2. The channel Ch may also include four or more unit channels as the channel Ch. In such a case, the middle unit channel includes all of the other unit channels except for the uppermost and the lowermost unit channels.

The lowermost unit channel Ch1, the middle unit channel Ch2and the uppermost unit channel Ch3may be individually connected to the semiconductor junction300, so that each of the unit channels Ch1to Ch3may function as an individual flow path of the charges between the source junction310and the drain junction320. For example, each of the unit channels Ch1to Ch3may include a nano wire structure.

An inter-channel space ICS inFIG. 26Bmay be provided between the neighboring unit channels along the third direction z and may be filled with the gate conductive pattern520in a following process. Thus, each of the unit channels Ch1to Ch3may be individually enclosed by the gate conductive pattern520and the channel Ch may be formed into the GAA structure.

A channel spacer290may be interposed between the gate conductive pattern520and the semiconductor junction300in the inter-channel space ICS, so that the semiconductor junction300may be electrically isolated from the gate conductive pattern520by the channel spacer290in the inter-channel space ICS.

That is, the channel spacer290may make contact with a pair of the neighboring unit channels, the semiconductor junction300and the gate conductive pattern520in the inter-channel space ICS, so that the neighboring unit channels, the semiconductor junction300and the gate conductive pattern520may be electrically isolated from one another in the inter-channel space ICS.

The gate structure500may include the gate insulation pattern510enclosing each of the unit channels Ch1to Ch3and the gate conductive pattern520filling up a lower portion of the gate trench GT, the inter-channel space(s) ICS and the channel trench CT. The gate structure500may be shaped into a line extending in the first direction x.

Particularly, a lower portion of the gate structure500may be inserted into the body insulator102in such a configuration that the channel trench CT may be filled up with the gate structure500and an upper portion of the gate structure500may be arranged around the uppermost unit channel Ch3in such a configuration that the uppermost unit channel Ch3may be sufficiently covered with the gate structure500and an upper surface of the gate conductive pattern520may be lower than an upper surface of the semiconductor junction300. Thus, the gate conductive pattern520may include the covering portion520athat may protrude from the uppermost unit channel Ch3and may cover an upper portion of the uppermost unit channel Ch3, and the filling portion520bthat may fill the channel trench CT and may cover a lower portion of the lowermost unit channel Ch1.

In such a case, the covering portion520amay have the covering thickness T1as small as possible on the condition that the uppermost unit channel Ch3may be sufficiently covered with gate conductive pattern520and the filling portion520bmay have a sufficient thickness for compensating for the deterioration of the electric characteristics caused by the height reduction of the gate conductive pattern520. Therefore, the filling thickness T2of the filling portion520bmay be greater than the covering thickness T1.

The covering portion520amay be electrically isolated from the semiconductor junction300by the gate spacer210and the gate conductive pattern520in the inter-channel space ICS may be electrically isolated from the semiconductor junction300by the channel spacer290. In some example embodiments, the width Wcs of the channel spacer290may be the same as the width Wgs of the gate spacer210, thus the channel spacer290may be vertically overlapped by the gate spacer210, and may have the uppermost unit channel Ch3therebetween. Moreover, a first of the channel spacers290may vertically overlap a second of the channel spacers290, and the first and second channel spacers290may have the middle unit channel Ch2therebetween. That is, the side surfaces of the channel spacer290may be vertically aligned with a side surface of the gate spacer210in the gate trench GT. The filling portion520bmay be electrically isolated from its surroundings by the body insulator102.

The supplementary insulating member611may be positioned on the gate conductive pattern520and thus the gate conductive pattern520may be protected from its surroundings. Particularly, the upper surface of the supplementary insulating member611may be coplanar with the upper surface of the gate spacer210.

Therefore, the gate spacer210may make contact with insulation materials across a larger contact area than the gate spacer210may contact with conductive materials. Thus, the capacitance area between the contact structure620and the gate conductive pattern520, which may be opposite to each other with respect to the gate spacer210, may be sufficiently reduced, so that the parasitic capacitance may be reduced/minimized between the contact structure620and the gate structure500. That is, the parasitic capacitance may be effectively limited to being between the contact structure620and the covering portion520a, and thus the parasitic capacitance between the contact structure620and the gate structure500may be sufficiently reduced in spite of the reduction of the width Wgs of the gate spacer210.

In addition, the filling thickness T2of the filling portion520bmay be greater than the covering thickness T1in the semiconductor device1001. The covering portion520amay have the covering thickness T1as small as possible on the condition that the uppermost unit channel Ch3may be sufficiently covered with the gate conductive pattern520and the filling portion520bmay have a sufficient thickness for compensating for the deterioration of the electric characteristics caused by the height reduction of the gate conductive pattern520.

Thus, the filling thickness T2may be sufficiently greater than the covering thickness T1and the gate structure500may be arranged in a reverse structure such that a larger portion may be arranged below the channel Ch and a smaller portion may be arranged on/above the channel Ch.

Therefore, the overlap area of the contact structure620and the gate structure500may decrease and thus the parasitic capacitance may be reduced/minimized between the contact structure620and the gate structure500even when the gate spacer210may become narrow due to the size reduction of the semiconductor device1001.

In addition, the upper portion of the contact structure620and the lower portion of the gate structure500may be horizontally expanded, and thus the surface area of the contact structure620and the gate structure500may increase.

Since the supplementary insulating member611may be arranged on the gate conductive pattern520and may comprise insulation materials instead of conductive materials and the contact structure620may face the supplementary insulating member611(with the gate spacer210intervening between the contact structure620and the supplementary insulating member611), the contact structure620may be expanded over the gate spacer210and as a result, the surface area of the contact structure620may increase without any increase of the parasitic capacitance, thereby reducing the contact resistance of the contact structure620. In addition, the process margin may also increase in forming the contact structure620.

In the same way, the channel trench CT may also be expanded in the first direction x to thereby form an expansion trench and as a result, the lower portion of the gate conductive pattern520may also be expanded in the first direction x. Therefore, the surface area of the gate conductive pattern520may increase and the electrical resistance of the gate structure500may decrease. That is, the gate driving voltage may decrease just by expanding the channel trench CT in the body insulator102.

FIG. 17Ais a plan view illustrating a modification of the semiconductor device shown inFIG. 16A.FIGS. 17B and 17Care cross-sectional views cut along a line I-I′ and a line II-II′ ofFIG. 17A, respectively. InFIGS. 17A to 17C, the modification of the semiconductor device has substantially the same structures as the semiconductor device1001shown inFIGS. 16A to 16C, except that the contact structure and the gate conductive pattern are expanded, so the same reference numerals denote the same elements inFIGS. 16A to 16C. Further detailed descriptions on the same elements may be omitted hereinafter.

Referring toFIGS. 17A to 17C, the gate structure500may include an expanded gate conductive pattern525having a covering portion525a, a filling portion525band an expanding (e.g., expanded) portion525c. The covering portion525amay cover the upper portion of the uppermost unit channel Ch3and the filling portion525bmay cover the lower portion of the lowermost unit channel Ch1and fill up the channel trench CT. The expanding portion525cmay be provided under the filling portion525band may fill an expanded trench ET that may be communicated/connected with the channel trench CT.

The expanded trench ET may be arranged under the channel trench CT and may have a second width W2larger than a first width W1of the channel trench CT. The covering portion525a, the filling portion525band the expanding portion525cmay have substantially the same structures as the covering portion520a, the filling portion520band the expanding portion525cof the semiconductor devices1000shownFIGS. 2B and 2C, thus any further descriptions on the covering portion525a, the filling portion525band the expanding portion525cmay be omitted.

Since the surface area of the gate structure500may increase due to the expanded portion525c, the electrical resistance of the gate structure500may decrease and as a result, the driving voltage applied to the gate structure500may also be decreased. Particularly, when the widths of the gate trench GT and the channel trench CT may decrease unexpectedly and thus the widths of the covering portion525aand the filling portion525bmay be over reduced, the expanding portion525cmay compensate for the reduction of the covering portion525aand the filling portion525b, thereby reducing/preventing the increase of the overall resistance of the gate structure500.

Further, an upper portion of the contact structure620may be expanded in the first direction x, thereby forming an expanded contact structure625to cover the gate spacer210. That is, the expanded contact structure625may include a lower contact625ainserted into the semiconductor junction300and having a lower width Wland an upper contact625bmaking contact with both of the semiconductor junction300and the gate spacer210in one body with the lower contact625a. The upper contact625bmay have an upper width Wugreater than the lower width Wlof the lower contact625a.

The lower contact625aand the upper contact625bmay have substantially the same structures as the lower contact625aand the upper contact625bof the semiconductor device1000shownFIGS. 2B and 2C, thus any further descriptions on the lower contact625aand the upper contact625bmay be omitted.

The increase of the surface area of the expanded contact structure625may decrease the contact resistance and increase the process margin for forming the expanded contact structure625.

According to the above example embodiments of the semiconductor device, the gate structure may fill up the channel trench in the body insulator and may enclose a plurality of the unit channels in such a configuration that the filling portion of the gate structure filling in the channel trench has a greater width than the covering portion of the gate structure on the channel and the covering portion may be lower than the gate spacer. The supplementary insulating member may be positioned on the gate structure in such a way that the upper surface of the supplementary insulating member may be coplanar with the upper surface of the gate spacer. Therefore, the parasitic capacitance may be reduced/minimized between the contact structure and the gate structure. In addition, the electrical resistance of the contact structure and the gate structure may be stable and reliable in spite of the size reduction of the semiconductor device.

FIGS. 18A to 32Bare views illustrating the processing steps for a method of manufacturing the semiconductor devices shown inFIGS. 16A to 16C. InFIGS. 18A to 32B, the alphabetic letter A in each figure number denotes a plan view of each processing step and the alphabetic letter B in each figure number denotes a cross-sectional view cut along the line I-I′ ofFIG. 16A.

Referring toFIGS. 18A and 18B, a sacrificial layer104and a semiconductor layer105may be formed on the semiconductor substrate100having the body insulator102.

For example, a silicon-on-insulator (SOI) substrate may be provided as the semiconductor substrate100in which the body insulator102may be formed on the base body101comprising silicon (Si) and the semiconductor substrate layer103may be formed on the body insulator102. The substrate100may have substantially the same structures as the substrate100described in detail with reference toFIGS. 3A and 3B, thus any further detailed descriptions on the substrate100may be omitted.

A plurality of the sacrificial layers104and a plurality of the semiconductor layers105may be alternately formed on the substrate layer103. For example, a first sacrificial layer104amay be formed on the substrate layer103and a first semiconductor layer105amay be formed on the first sacrificial layer104a. Further, a second sacrificial layer104bmay be formed on the first semiconductor layer105aand a second semiconductor layer105bmay formed on the second sacrificial layer104b. A third sacrificial layer104cmay be formed on the second semiconductor layer105b.

For example, the sacrificial layer104and the semiconductor layer105may be formed on the substrate100by a deposition process such as a CVD process or a PVD process. The sacrificial layer104may include silicon germanium (SiGe) or indium phosphorous (InP) and the semiconductor layer105may include single crystalline silicon just like the substrate layer103. However, various semiconductor materials may be utilized for the semiconductor layer105as long as the semiconductor layer105may have sufficient etching selectivity with respect to the sacrificial layer104. For example, the semiconductor layer105may include semiconductor compositions including the elements of Group III to Group V.

Since the substrate layer103and the semiconductor layer105may be formed into the channel Ch of the semiconductor device1001, the number/quantity of the semiconductor layers105may be varied according to the number/quantity of the unit channels of the channel Ch. In some example embodiments, the channel Ch may include three unit channels Ch1to Ch3, and the first and the second semiconductor layers105aand105bmay be formed on the substrate100.

Referring toFIGS. 19A and 19B, a stacked active fin112may be formed on the body insulator102by the same process as described in detail with reference toFIGS. 4A and 4Bin such a way that the stacked active fin112may protrude from the body insulator102and may be shaped into a line extending in the first direction x. The stacked active fin112may include a sacrificial pattern106having a plurality of sacrificial fins106ato106cand a semiconductor pattern107having a plurality of semiconductor fins107ato107c. The semiconductor fins107ato107cand the sacrificial fins106ato106cmay be alternately stacked on the body insulator102, thereby forming the stacked active fin112.

The substrate layer103may be formed into the first semiconductor fin107aof the semiconductor pattern107and the first and the second semiconductor layers105aand105bmay be formed into the second and third semiconductor fins107band107cof the semiconductor pattern107. The first to third sacrificial layers104ato104cmay be formed into the first to third sacrificial fins106ato106cof the sacrificial pattern106. The first semiconductor fin107amay be arranged on the body insulator102, and the first to third sacrificial fins106ato106cmay be alternately arranged on the first to third semiconductor fins107ato107c, respectively.

Referring toFIGS. 20A to 22B, a dummy gate layer120amay be formed on the substrate100to a sufficient thickness to cover the stacked active fin112and a dummy mask pattern M may be formed on the dummy gate layer120ain a shape of a line extending in the second direction y. The dummy gate layer120amay be partially removed from the substrate100by an etching process using the dummy mask pattern M as an etching mask, thereby forming the dummy gate line120extending in the second direction y. The gate spacer210may be formed on each sidewall of the dummy gate line120so that the gate spacer210may also extend in the second direction y at each side of the dummy gate line120.

The stacked active fin112may extend in the first direction x and the dummy gate line120and the gate spacer210may extend in the second direction y, and thus the stacked active fin112may be partially covered with the dummy gate line120and the gate spacer210. In some example embodiments, a central portion of the third sacrificial fin106cmay be covered with the dummy gate line120and the gate spacer210, and both sides of the third sacrificial fin106cmay be exposed to surroundings.

The dummy gate layer120a, the dummy gate line120and the gate spacer210may be formed on the substrate100by substantially the same process(es) as described in detail with reference toFIGS. 5A to 7B, so any further descriptions for forming the dummy gate layer120a, the dummy gate line120and the gate spacer210may be omitted.

Then, the semiconductor junction300may be formed on the stacked active fin112that may be uncovered by the gate spacer210and the dummy gate line120by the same process as described with reference toFIGS. 8A and 8B. For example, a single crystalline layer may be formed on the exposed portions of the stacked active fin112by an epitaxial growth process using the stacked active fin as a seed layer, thereby forming a semiconductor growth layer on the stacked active fin112that may make contact with a side surface of the gate spacer210. Then, a plurality of dopants may be implanted onto the semiconductor growth layer by an ion implantation process, thereby forming the semiconductor junction300including the source junction310and the drain junction320, as illustrated inFIGS. 23A and 23B. One of p-type dopants or n-type dopants may be implanted onto the exposed portions of the stacked active fin112.

Particularly, the semiconductor junction300may be formed into an elevated structure by the epitaxial growth process and the dopants may be implanted around the stacked active fin112. Thus, the dummy gate line120may be separated from the semiconductor junction300by the gate spacer210and the source and drain junctions310and320may be arranged at both sides of the dummy gate line120, respectively. The stacked active fin112under the dummy gate line120may be formed into the channel Ch through which the source and drain junctions310and320may be connected.

Referring toFIGS. 24A to 25B, the insulation interlayer pattern410may be formed on the semiconductor junction300in such a way that the gate spacer210and the dummy gate line120may be exposed through the insulation interlayer pattern410. Then, the dummy gate line120may be removed from the body insulator102until the stacked active fin112may be exposed, thereby forming a gate trench GT through which the stacked active fin112may be exposed.

The insulation interlayer pattern410and the gate trench GT may be formed on the substrate100by substantially the same process(es) as described in detail with reference toFIGS. 9A to 10B, so any further descriptions for forming the insulation interlayer pattern410and the gate trench GT may be omitted.

The gate trench GT may be defined by a pair of the gate spacers210and the body insulator102and may have a first gate space GS1. The stacked active fin112may be exposed through the gate trench GT.

Referring toFIGS. 26A and 26B, the sacrificial pattern106amay be partially removed from the stacked active fin112in the gate trench GT, thereby forming sacrificial fin residuals290aon each of the semiconductor fins107ato107cand an inter-channel trench IT communicated/connected with the gate trench GT. The sacrificial fin residuals290amay remain on end portions of each semiconductor fins107ato107cin a vertical line with the gate spacer210. Thus, the inter-channel space ICS between the neighboring semiconductor fins107ato107cmay be defined by the sacrificial fin residuals290ato thereby form the inter-channel trench IT similarly to how the first gate space GS1may be defined by the gate spacer210to thereby form the gate trench GT.

The sacrificial pattern106may be removed from the stacked active fin112by a wet etching process or a dry etching process in which the semiconductor pattern107may have an etching selectivity with respect to the sacrificial pattern106.

Particularly, when the sacrificial pattern106may include silicon germanium (SiGe) and the semiconductor pattern107may include silicon (Si), the sacrificial pattern106may be removed by a wet etching process using an etchant in which an etching rate of silicon germanium (SiGe) may be greater than that of silicon (Si). For example, examples of the etchant for removing the sacrificial pattern may include a mixture of hydrogen peroxide (H2O2), hydrogen fluoride (HF) and acetic acid (CH3COOH), a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and de-ionized water and a mixture of peracetic acid.

In some example embodiments, the sacrificial pattern106may be removed from the stack active fin112by an anisotropic etching process using the gate spacer210as an etching mask, thus the sacrificial pattern106may be etched off along a vertical surface profile of the gate trench GT. That is, some portion of the sacrificial pattern106that may be overlapped by the gate spacer210in the third direction z may remain without being etched, to form the sacrificial fin residuals290a. The inter-channel space ICS communicated/connected with the first gate space GS1may be defined by the sacrificial fin residuals290ato form the inter-channel trench IT communicated/connected with the gate trench GT.

Referring toFIGS. 27A and 27B, the sacrificial fin residuals290amay be formed into the channel spacer290and the semiconductor pattern107may be formed into the channel Ch including first to third unit channels Ch1to Ch3.

For example, a thermal oxidation process may be performed on/to the substrate100having the sacrificial fin residuals290afor a sufficient time for fully oxidizing silicon germanium (SiGe) of the sacrificial fin residuals290a, thereby forming the channel spacer290that may comprise silicon germanium oxide. Since silicon germanium (SiGe) may be much more rapidly oxidized than silicon (Si), the semiconductor pattern107may be much less oxidized than the sacrificial fin residuals290ain the same oxidation process and the silicon oxide layer may be formed to a sufficiently small thickness on the semiconductor pattern107.

The semiconductor fins107ato107cspaced apart by the inter-channel space ICS and the channel spacer290may be formed into the unit channels Ch1to Ch3that may cross over the gate trench GT and may make contact with the semiconductor junction300. The inter-channel space ICS may be separated from the semiconductor junction300by the channel spacer290.

Referring toFIGS. 28A and 28B, the body insulator102that may be exposed through the gate trench GT and the inter-channel space ICS may be further removed from the substrate100, thereby forming the channel trench CT that may be communicated/connected with the gate trench GT and the inter-channel trench IT.

For example, the body insulator102may be further etched off from the substrate100by an anisotropic etching process using the gate spacer210and the channel spacer290as an etching mask.

Since the semiconductor fins107ato107cmay include single crystalline silicon and the body insulator102may include silicon oxide, the body insulator102may be much more rapidly etched off than the semiconductor fins107ato107cin the anisotropic etching process. Thus, the body insulator102under the first semiconductor fin107amay be recessed with the same width of the gate trench GT in a shape of line extending along the second direction y, thereby forming the channel trench CT having the second gate space GS2that may be communicated with the inter-channel space ICS the first gate space GS1. The depth of the channel trench CT may be controlled by the variation of the process conditions of the anisotropic etching process in consideration of the characteristics of the gate structure500and the width t of the unit channel Ch1to Ch3. In some example embodiments, the channel trench CT may have the same depth as the width t of the unit channels Ch1to Ch3.

Particularly, the unit channels Ch1to Ch3may be formed into a nano wire that may cross over the channel trench CT and traverse the gate trench GT in the first direction x and may be enclosed by the gate conductive pattern520in a subsequent process such as gate all-around channel (GAA).

The channel trench CT may be formed in the body insulator102by the same process as described in detail with reference toFIGS. 11A to 11B, so any further descriptions for forming the channel trench CT may be omitted.

In some embodiments, a bottom portion of the channel trench CT may be expanded in the first direction x and the expanded trench ET may be further formed under the channel trench CT by the same process as described in detail with reference toFIG. 11C. Thus, the expanding portion525cof the expanded gate conductive pattern525inFIG. 17Bmay be formed by filling up the expanded trench ET with gate conductive materials.

Referring toFIGS. 29A and 29B, a preliminary gate structure500amay be formed in the gate trench GT, the inter-channel trench IT and the channel trench CT in such a way that the unit channels Ch1to Ch3may be individually enclosed by the preliminary gate structure500a.

For example, the preliminary gate structure500amay be formed by node-separating a stack layer of a gate insulation layer and a gate conductive layer at each gate trench GT by a planarization process in such a way that a gate insulation pattern510may be formed on a surface of the unit channels Ch1to Ch3and the side surfaces of the gate spacer210and the channel spacer290and then a preliminary gate conductive pattern529may be formed in the channel trench CT, the inter-channel trench IT and the gate trench GT. Particularly, the gate insulation layer may be formed on the body insulator102along a surface profile of the substrate100having the gate trench GT and the channel trench CT. Thus, the gate insulation layer may be formed on side surfaces of the gate trench GT and inter-channel trench IT and on upper surfaces of the insulation interlayer pattern410and the gate spacer210. In such a case, the unit channels Ch1to Ch3may be individually enclosed and covered by the gate insulation layer. Then, the gate conductive layer may be formed on the gate insulation layer to a sufficient thickness to fill up the channel trench CT to the gate trench GT, and then the gate conductive layer and the gate insulation layer may be planarized until a top surface of the insulation interlayer pattern410and the gate spacer210may be exposed. Therefore, the gate insulation layer and the gate conductive layer may be node-separated by the gate trench GT, thereby forming the preliminary gate structure500ahaving the gate insulation pattern510and the preliminary gate conductive pattern529.

In some example embodiments, the body insulator102and the gate insulation pattern510may include silicon oxide and the gate spacer210may include silicon nitride. Thus, the gate insulation pattern510may be formed only on the channel Ch and the side surfaces of the gate spacer210and the channel spacer290and may not be formed on the side surfaces and the bottom of the channel trench CT.

Referring toFIGS. 30A and 30B, an upper portion of the preliminary gate structure500amay be removed from the substrate100, thus the gate structure500may be formed in a lower portion of the gate trench GT, the inter-channel trench IT and the channel trench CT.

For example, the preliminary gate conductive pattern529may be partially etched from the substrate100by an etching process using the gate spacer210and the insulation interlayer pattern410as an etching mask, thus the upper portion of the preliminary gate conductive pattern529may be etched off from the gate trench GT. Therefore, the upper portion of the gate trench GT may be opened again and a supplementary insulation hole SH may be provided at the upper portion of the gate trench GT.

In such a case, the preliminary gate conductive pattern529may be etched in such a way that the uppermost unit channel Ch3may be sufficiently covered by the residuals of the preliminary gate conductive pattern529while an upper surface of the residuals of the preliminary gate conductive pattern529may be lower than the upper surface of the semiconductor junction300around the uppermost unit channel Ch3.

Accordingly, the preliminary gate conductive pattern529may be formed into the gate conductive pattern520that may enclose the channel Ch and simultaneously fill up the inter-channel trench IT and the channel trench CT. Thus, the gate conductive pattern520may include a covering portion520athat may be protruded from the uppermost unit channel Ch3to a covering thickness T1and may cover an upper portion of the uppermost unit channel Ch3and a filling portion520bthat may fill up the channel trench CT with a filling thickness T2and may cover a lower portion of the lowermost unit channel Ch1. The covering portion520aand the filling portion520bmay be integrally combined with a middle portion filling the inter-channel trench IT, thereby forming the gate conductive pattern520by which the unit channels Ch1to Ch3may be individually enclosed.

Referring toFIGS. 31A and 31B, the supplementary insulating member611may be formed in the supplementary insulation hole SH in such a way that an upper surface of the supplementary insulating member611may be coplanar with the upper surface of the insulation interlayer pattern410. For example, the supplementary insulating layer may include any one of silicon oxide, silicon nitride, silicon oxynitride and combinations thereof. The supplementary insulating member611may be formed in the supplementary insulation hole SH by the same process as described in detail with reference toFIGS. 14A to 14B, so any further descriptions for forming the channel trench CT may be omitted.

Referring toFIGS. 32A and 32B, the contact structure620penetrating through the insulation interlayer pattern410and making contact with the semiconductor junction300may be formed by the same process as described in detail with reference toFIGS. 15A and 15B. The contact structure620may include low-resistive metals such as tungsten (W), titanium (Ti), tantalum (Ta) and aluminum (Al). In some embodiments, a metal silicide layer may be further formed between the semiconductor junction300and the contact structure620, thereby reducing contact resistance of the contact structure620.

Thereafter, wiring structures connected to the contact structure620and other upper conductive structures may be further formed on the additional insulation layer612together with a passivation layer enclosing the wiring structure and the upper conductive structures, thereby manufacturing the semiconductor devices1001.

In modified example embodiments, an upper portion of the contact structure620may be enlarged to thereby decrease the contact resistance thereof.

FIG. 32Cis a cross-sectional view illustrating a processing step for a method of enlarging the upper portion of the contact structure shown inFIG. 32B.

Referring toFIG. 32C, an expanded contact hole619may be formed into the semiconductor junction300through the additional insulation layer612and the insulation interlayer pattern410. The expanded contact hole619may include an upper hole619bpenetrating through the additional insulation layer612and the insulation interlayer pattern410and a lower hole619arecessed in the semiconductor junction300. Thereafter, conductive materials may be filled into the expanded contact hole619to thereby form the expanded contact structure625of which the upper portion may be expanded over the gate spacer210in the first direction x.

Thus, the expanded contact structure625may include a lower contact625athat may be inserted into the semiconductor junction300and having the lower width Wland an upper contact625bmaking contact with both of the semiconductor junction300and the gate spacer210in one body with the lower contact625a. The upper contact625bmay have the upper width Wugreater than the lower width Wl.

The expanded contact structure625may have a larger surface area than the contact structure620, thereby reducing the contact resistance and increasing the process margin for forming the contact structure.

The expanded contact structure625may be formed in the expanded contact hole619by the same process as described in detail with reference toFIG. 15C, so any further descriptions for forming the expanded contact structure625may be omitted.

According to the above example embodiments of the method of manufacturing semiconductor devices, the channel trench may be formed in the body insulator and a plurality of channels may be stacked on the body insulator. The gate structure may be formed to fill up the channel trench and to enclose each of the channels. The gate structure may include the covering portion on the uppermost channel and the filling portion in the channel trench. The covering portion may have the covering thickness as small as possible on condition that the uppermost channel may be sufficiently covered with gate conductive materials and the filling portion may have a sufficient thickness for compensating for the deterioration of the electric characteristics caused by the height reduction of the gate structure.

An upper portion of the gate conductive pattern of the gate structure may be replaced with the supplementary insulating member, so that the overlap area between the contact structure and the gate structure may be reduced just between the contact structure and the protruding portion. Therefore, the parasitic capacitance may be reduced/minimized between the contact structure and the gate structure.

The above-described semiconductor devices with reference toFIGS. 1A to 32Cmay be used for transistors of various digital or analogue circuits. In addition, the above-described semiconductor devices may also be used as a high voltage transistor or a low voltage transistor.

For example, some example embodiments of the semiconductor devices may be utilized as high voltage transistors of peripheral circuit for the flash memory devices or EEPROM (electrically erasable and programmable read only memory) devices that may be operated by a high voltage power.

Particularly, some example embodiments of the semiconductor devices may be used for transistors for a high voltage driving integrated circuit (IC) device that may require a driving power over about 10V. For example, the driving IC device for an LCD apparatus may require the driving power of about 20V to about 30V and the driving IC device for a plasma display panel (PDP) may require the driving power of about 100V or more. The above-described semiconductor devices may be sufficiently applied to the transistor of the driving IC device for the LCD apparatus or the PDP apparatus as well as a mobile display apparatus.

FIG. 33is a schematic block diagram illustrating a display apparatus including the semiconductor devices in accordance with some example embodiments of present inventive concepts.

Referring toFIG. 33, the display apparatus2000may include a display drive IC (DDI) device2100, a main processing unit (MPU)2200connected to the DDI device2100and processing image signals and a display panel2300driven by the DDI device2100and displaying images in response to the image signals.

The DDI device2100may include a controller2110, a power supply circuit2120, a driver block2130and a memory block2140.

The controller2110may decode the instructions transferred from the MPU2200and may control each operation block of the DDI device2100in response to the instructions. The power supply circuit2120may generate a driving power in response to a control signal of the controller2110. The driver block2130may drive the display panel2300to operate by using the driving power. The display panel2300may include a flat panel such as an LCD panel and a PDP panel as well as a mobile display panel.

The memory block2140may temporarily store the instructions that may be applied to the controller2110, the control signals that may be generated from the controller2110and various processing data for operating the display apparatus2000. Thus, the memory block2140may include a plurality of random access memory (RAM) devices and/or read only memory (ROM) devices.

Particularly, the power supply circuit2120, the driver block2130and the memory block2140may include a plurality of the semiconductor devices exemplarily described in detail with reference toFIGS. 1 to 32C.

The size of the DDI device2100may be reduced and the occupancy area of the power supply circuit2120, the driver block2130and the memory block2140may decrease in accordance with the recent technical trends of small size and thickness of the display apparatus2000, so that the line widths of the semiconductor devices in each of the power supply circuit2120, the driver block2130and the memory block2140may be extremely small. However, the parasitic capacitance between the contact structure and the gate structure may be sufficiently reduced/prevented in spite of the size reduction of the semiconductor devices in the DDI device2100. Therefore, the DDI device2100may be operated with high reliability in spite of small occupancy area and small size.

In addition, the expansion of the upper portion of the contact structure and the lower portion of the gate structure may increase the surface area of the contact structure and the gate structure to thereby decrease the electrical resistance at the contact structure and the gate structure of the semiconductor device in the DDI device2100.

FIG. 34is a circuit diagram illustrating a CMOS SRAM including the semiconductor devices in accordance with some example embodiments of present inventive concepts.

Referring toFIG. 34, the CMOS SRAM device3000may include a pair of driving transistors3100. Each of the driving transistors3100may include a PMOS transistor3110connected to a power terminal Vdd, an NMOS transistor3120connected to a ground terminal and a transfer transistor3130. The source electrode of the transfer transistor3130may be connected to a common node of the PMOS transistor3110and the NMOS transistor3120. The power terminal Vdd may be connected to the source electrode of the PMOS transistor3110and the ground terminal may be connected to the source electrode of the NMOS transistor3120. A word line WL may be connected to a gate electrode of the transfer transistor3130. A bit line BL may be connected to a drain electrode of one of the pair of the transfer transistor3130and a complementary bit lineBLmay be connected to a drain electrode of the other transfer transistor3130.

The example embodiments of the semiconductor devices described with reference toFIGS. 1A to 32Cmay be applied to at least one of the PMOS transistor3110, the NMOS transistor3120and the transfer transistor3130. Thus, although the CMOS SRAM device3000may be downsized and as a result, the semiconductor devices in the PMOS transistor3110, NMOS transistor3120and the transfer transistor3130may have small line widths and occupancy areas, the parasitic capacitance between the contact structure and the gate structure may be sufficiently reduced/prevented/minimized, thereby increasing the operation reliability and stability of the CMOS SRAM3000together with high integration degree.

FIG. 35is a circuit diagram illustrating a CMOS NAND device including the semiconductor devices in accordance with some example embodiments of present inventive concepts.

Referring toFIG. 35, the CMOS NAND device4000may include a pair of CMOS transistors to which different signals may be applied. The PMOS transistor and the NMOS transistor of the CMOS transistor may include the example embodiments of the semiconductor devices described with reference toFIGS. 1A to 32C.

Thus, the CMOS NAND device4000may be sufficiently downsized without any increase of the parasitic capacitance between the contact structure and the gate structure, thereby increasing the memory capacity of the CMOS NAND device4000without deterioration of operation reliability.

FIG. 36is a block diagram illustrating a memory apparatus including the semiconductor devices in accordance with some example embodiments of present inventive concepts.

Referring toFIG. 36, the memory apparatus5000may include a memory unit5100and a memory controller5200controlling the operation of the memory unit5100. The memory controller5200may control data reading from the memory unit5100and/or data storing to the memory unit5100in response to a host signal from a host5300.

The memory unit5100and the memory controller5200may include example embodiments of the semiconductor devices described in detail with reference toFIGS. 1A to 32C.

Thus, the parasitic capacitance between the contact structure and the gate structure may be sufficiently reduced/prevented/minimized when the semiconductor device may be downsized and thus the line width of the semiconductor device may decrease. Therefore, the memory apparatus5000may be downsized with high memory capacity without any deterioration of the operational reliability.

FIG. 37is a block diagram illustrating an electronic system having the semiconductor devices in accordance with some example embodiments of present inventive concepts.

Referring toFIG. 37, the electronic system6000may include a controller6100, an input/output (I/O) unit6200, a memory unit6300and a wireless interface6400that may be electrically interconnected with one another via a bus line6500.

The controller6100may include any one of a microprocessor, a digital signal processor and the like. The I/O unit6200may include a keypad, a keyboard and a display device.

The memory unit6300may store the instructions executed by the controller6100and the user data processed by the controller6100.

The electronic system6000may transfer and receive data in a wireless communication network by using the wireless interface6400. The wireless interface6400may include an antenna and/or wireless transceiver.

The electronic system6000may include a wireless communication system or a wireless data communicator having a third generation communication interface protocol such as a code division multiple access (CDMA), a global system for mobile communications (GSM), a North America digital cellular communications (NADC), an extended-time division multiple access (E-TDMA) and a wide band code division multiple access (WCDMA).

The electronic system6000may include example embodiments of the semiconductor devices described with reference toFIGS. 1A to 32C. Thus, the parasitic capacitance may be reduced/impeded between the contact structure and the gate structure of each semiconductor device in at least one of the controller6100, the input/output (I/O) unit6200, the memory unit6300and the wireless interface6400, thereby downsizing the electronic system6000without any deterioration of the operational reliability.

According to the example embodiments of the semiconductor devices and the method of manufacturing thereof, the channel trench may be formed in the body insulator of the substrate and the channel may be arranged or stacked on the body insulator across the channel trench. The gate structure may fill up the channel trench and enclose the channel in such a configuration that an upper surface of the gate structure may be lower than an upper surface of the gate spacer and may be close to the channel. Thus, the gate structure may include a covering portion protruding from the channel and a filling portion recessed into the channel trench. The covering portion may have the covering thickness smaller than the filling thickness of the filling portion. The upper portion of the gate structure may be replaced with the supplementary insulating member in the gate trench.

Therefore, the overlap area of the contact structure and the gate structure may decrease while increasing the overlap area of the contact structure and the supplementary insulating member, thus the overlap area between the contact structure and the gate structure may be limited to being between the contact structure and the covering portion and the parasitic capacitance may be sufficiently reduced/minimized between the contact structure and the gate structure. Particularly, the parasitic capacitance between the contact structure and the gate structure may be sufficiently reduced/prevented even when the gate spacer may become narrow due to the size reduction of the semiconductor device.

In addition, the upper portion of the contact structure and the lower portion of the gate structure may be horizontally expanded and thus the surface area of the contact structure and the gate structure may increase. Thus, the electrical resistance of the contact structure and the gate structure may be stable and reliable in spite of the size reduction of the semiconductor device.