Structure and method for forming capacitors for a three-dimensional NAND

Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.

CROSS-REFERENCE TO RELATED APPLICATIONS AND INCORPORATION BY REFERENCE

This application claims priority to PCT/CN2019/095069 filed on Jul. 8, 2019, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure generally relates to the field of semiconductor technology, and more particularly, to a method for forming a three-dimensional (3D) memory.

BACKGROUND

As memory devices are shrinking to smaller die size to reduce manufacturing cost and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. A three-dimensional (3D) memory architecture can address the density and performance limitation in planar memory cells.

In a conventional 3D memory, operation of memory cells need high voltage and capacitors are usually implemented as voltage booster. Currently integrated circuits for a 3D memory mainly use capacitors such as metal-oxide-silicon (MOS) capacitors, metal-oxide-metal (MOM) capacitors or polysilicon-oxide-polysilicon (POP) capacitors. As the development of 3D memory (e.g., 3D NAND flash memory) towards high density and high capacity memory cells, the number of devices (e.g., transistors) and the number of metal wirings are continuously increasing. In the meantime, to reduce manufacturing cost, the area of a memory chip remains largely unchanged. Therefore, devices in a 3D memory chip have been scaled down to smaller and smaller dimensions. Because capacitance is proportional to the area of a capacitor, a two-dimensional (2D) capacitor needs large silicon area in order to provide sufficient capacitance for the integrated circuitry of a 3D memory. To further increase capacitance, the thickness of the dielectric layer (e.g., silicon oxide) between the two electrodes of a capacitor can be thinned down. However, a capacitor with a very thin dielectric layer can suffer various reliability issues. Therefore, there is a need for a capacitor which can provide sufficiently large capacitance for the 3D memory within a reduced silicon area on a wafer.

BRIEF SUMMARY

Embodiments of a three-dimensional (3D) capacitor structure for a memory device and methods for forming the same are described in the present disclosure.

One aspect of the present disclosure provides a method for forming a 3D capacitor for a memory device, which includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The first capacitor electrode is electrically connected with the deep well. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer. The method further includes bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array, such that at least one peripheral device of the peripheral circuitry is electrically connected with at least one memory cell of the memory array. The method also includes forming, on a second side of the first substrate, one or more trenches inside the deep well, where the first and second sides are opposite sides of the first substrate. The method further includes disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.

In some embodiments, forming the 3D capacitor also includes thinning the first substrate from the second side after bonding the first and second interconnect layers. In some embodiments, thinning the first substrate includes exposing the deep well on the second side of the first substrate.

In some embodiments, forming the 3D capacitor further includes disposing a capping layer on the second side of the first substrate prior to forming one or more trenches.

In some embodiments, forming the 3D capacitor also includes forming a deep trench isolation to define an active area for the three-dimensional capacitor. In some embodiments, forming the deep trench isolation includes forming a through-silicon-trench penetrating through the first substrate and exposing a portion of the first interconnect layer, and disposing an insulating material inside the through-silicon-trench. In some embodiments, forming the deep trench isolation includes forming a through-silicon-trench penetrating through the first substrate prior to forming the one or more trenches, and exposing a portion of the first interconnect layer. In some embodiments, the through-silicon-trench has a width smaller than twice of a thickness of the capacitor dielectric layer.

In some embodiments, forming capacitor contacts includes disposing a conductive material on the sidewalls of the capacitor dielectric layer inside the one or more trenches, and removing the conductive material outside the one or more trenches. In some embodiments, removing the conductive material outside the one or more trenches includes chemical mechanical polishing.

In some embodiments, forming the 3D capacitor also includes forming a second capacitor electrode on the capacitor contacts on the second side of the first substrate.

In some embodiments, the bonding of the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array includes dielectric-to-dielectric bonding and metal-to-metal bonding at a bonding interface.

Another aspect of the present disclosure provides a 3D capacitor for a memory device that includes a deep well formed on a second side of a first substrate. A first side of the first substrate, opposite of the second side, includes a plurality of peripheral devices and a first interconnect layer. The 3D capacitor also includes a first capacitor electrode electrically connected with the deep well. The 3D capacitor further includes one or more trenches inside the deep well, and a capacitor dielectric layer on sidewalls of the one or more trenches. The 3D capacitor also includes capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches, and a second capacitor electrode disposed on the capacitor contacts.

In some embodiments, the first interconnect layer on the first side of the first substrate is bonded with a second interconnect layer of a memory array on a second substrate, such that at least one peripheral device on the first substrate is electrically connected with at least one memory cell of the memory array.

In some embodiments, the 3D capacitor also includes a deep trench isolation. The deep trench isolation penetrates through the first substrate and defines an active area for the three-dimensional capacitor.

In some embodiments, the deep trench isolation is filled with an insulating material such as silicon oxide, silicon nitride or silicon oxynitride.

In some embodiments, the capacitor dielectric layer includes silicon oxide, silicon nitride or silicon oxynitride.

In some embodiments, the capacitor dielectric layer is a high-k dielectric material, including hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, lanthanum oxide, or a combination of two or more thereof.

In some embodiments, the one or more trenches penetrate through the deep well and extend into the first interconnect layer.

In some embodiments, the one or more trenches penetrate through a portion of the deep well on the first substrate.

In some embodiments, the capacitor contacts on the sidewalls of the capacitor dielectric layer inside the one or more trenches include tungsten, copper, aluminum, titanium, nickel, cobalt, titanium nitride, tantalum nitride, or a combination of two or more thereof.

DETAILED DESCRIPTION

It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology can be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, can be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” can be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or process step in addition to the orientation depicted in the figures. The apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate includes a “top” surface and a “bottom” surface. The top surface of the substrate is typically where a semiconductor device is formed, and therefore the semiconductor device is formed at a top side of the substrate unless stated otherwise. The bottom surface is opposite to the top surface and therefore a bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer has a top side and a bottom side where the bottom side of the layer is relatively close to the substrate and the top side is relatively away from the substrate. A layer can extend over the entirety of an underlying or overlying structure, or can have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any set of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive and contact layers (in which contacts, interconnect lines, and/or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

In the present disclosure, for ease of description, “tier” is used to refer to elements of substantially the same height along the vertical direction. For example, a word line and the underlying gate dielectric layer can be referred to as “a tier,” a word line and the underlying insulating layer can together be referred to as “a tier,” word lines of substantially the same height can be referred to as “a tier of word lines” or similar, and so on.

In the present disclosure, the term “horizontal/horizontally/lateral/laterally” means nominally parallel to a lateral surface of a substrate, and the term “vertical” or “vertically” means nominally perpendicular to the lateral surface of a substrate.

As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate.

Various embodiments in accordance with the present disclosure provide structures and fabricating methods for vertical capacitors with higher density and less consumption of silicon area on a wafer. By using vertical capacitors instead of conventional two-dimensional (2D) capacitors, the overall memory density and manufacturing cost of a 3D NAND flash memory can be improved.

FIG. 1illustrates a top-down view of an exemplary three-dimensional (3D) memory device100, according to some embodiments of the present disclosure. The 3D memory device100can be a memory chip (package), a memory die or any portion of a memory die, and can include one or more memory planes101, each of which can include a plurality of memory blocks103. Identical and concurrent operations can take place at each memory plane101. The memory block103, which can be megabytes (MB) in size, is the smallest size to carry out erase operations. Shown inFIG. 1, the exemplary 3D memory device100includes four memory planes101and each memory plane101includes six memory blocks103. Each memory block103can include a plurality of memory cells, where each memory cell can be addressed through interconnections such as bit lines and word lines. The bit lines and word lines can be laid out perpendicularly (e.g., in rows and columns, respectively), forming an array of metal lines. The direction of bit lines and word lines are labeled as “BL” and “WL” inFIG. 1. In this disclosure, memory block103is also referred to as a “memory array” or “array.” The memory array is the core area in a memory device, performing storage functions.

The 3D memory device100also includes a periphery region105, an area surrounding memory planes101. The periphery region105contains many digital, analog, and/or mixed-signal circuits to support functions of the memory array, for example, page buffers, row and column decoders and sense amplifiers. Peripheral circuits use active and/or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as would be apparent to a person of ordinary skill in the art.

It is noted that, the arrangement of the memory planes101in the 3D memory device100and the arrangement of the memory blocks103in each memory plane101illustrated inFIG. 1are only used as an example, which does not limit the scope of the present disclosure.

Referring toFIG. 2, an enlarged top-down view of a region108inFIG. 1is illustrated, according to some embodiments of the present disclosure. The region108of the 3D memory device100can include a staircase region210and a channel structure region211. The channel structure region211can include an array of memory strings212, each including a plurality of stacked memory cells. The staircase region210can include a staircase structure and an array of contact structures214formed on the staircase structure. In some embodiments, a plurality of slit structures216, extending in WL direction across the channel structure region211and the staircase region210, can divide a memory block into multiple memory fingers218. At least some slit structures216can function as the common source contact for an array of memory strings212in channel structure regions211. A top select gate cut220can be disposed in the middle of each memory finger218to divide a top select gate (TSG) of the memory finger218into two portions, and thereby can divide a memory finger into two programmable (read/write) pages. While erase operation of a 3D NAND memory can be carried out at memory block level, read and write operations can be carried out at memory page level. A page can be kilobytes (KB) in size. In some embodiments, region108also includes dummy memory strings for process variation control during fabrication and/or for additional mechanical support.

FIG. 3illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory array structure300, according to some embodiments of the present disclosure. The memory array structure300includes a substrate330, an insulating film331over the substrate330, a tier of lower select gates (LSGs)332over the insulating film331, and a plurality of tiers of control gates333, also referred to as “word lines (WLs),” stacking on top of the LSGs332to form a film stack335of alternating conductive and dielectric layers. The dielectric layers adjacent to the tiers of control gates are not shown inFIG. 3for clarity.

The control gates of each tier are separated by slit structures216-1and216-2through the film stack335. The memory array structure300also includes a tier of top select gates (TSGs)334over the stack of control gates333. The stack of TSG334, control gates333and LSG332is also referred to as “gate electrodes.” The memory array structure300further includes memory strings212and doped source line regions344in portions of substrate330between adjacent LSGs332. Each memory strings212includes a channel hole336extending through the insulating film331and the film stack335of alternating conductive and dielectric layers. Memory strings212also includes a memory film337on a sidewall of the channel hole336, a channel layer338over the memory film337, and a core filling film339surrounded by the channel layer338. A memory cell340can be formed at the intersection of the control gate333and the memory string212. The memory array structure300further includes a plurality of bit lines (BLs)341connected with the memory strings212over the TSGs334. The memory array structure300also includes a plurality of metal interconnect lines343connected with the gate electrodes through a plurality of contact structures214. The edge of the film stack335is configured in a shape of staircase to allow an electrical connection to each tier of the gate electrodes.

InFIG. 3, for illustrative purposes, three tiers of control gates333-1,333-2, and333-3are shown together with one tier of TSG334and one tier of LSG332. In this example, each memory string212can include three memory cells340-1,340-2and340-3, corresponding to the control gates333-1,333-2and333-3, respectively. In some embodiments, the number of control gates and the number of memory cells can be more than three to increase storage capacity. The memory array structure300can also include other structures, for example, TSG cut, common source contact and dummy channel structure. These structures are not shown inFIG. 3for simplicity.

To achieve higher storage density, the number of vertical WL stacks of a 3D memory or the number of memory cells per memory string has been greatly increased, for example, from 24 stacked WL layers (i.e. 24 L) to 128 layers or more. To further reduce the size of a 3D memory, the memory array can be stacked on top of the peripheral circuitry or vice versa. For example, the peripheral circuitry can be fabricated on a first substrate and the memory array can be fabricated on a second substrate. Then the memory array and the peripheral circuitry can be connected through various interconnects by bonding the first and second substrates together. As such, not only the 3D memory density can be increased, but also communication between the peripheral circuitry and memory array can achieve higher bandwidth and lower power consumption since the interconnect lengths can be shorter through substrate (wafer) bonding.FIGS. 4-8, 9A-9G, 10, 11A-11C, 12A-12C and 13illustrate the structures and methods for forming a 3D memory device where peripheral circuitry is connected with memory array through wafer bonding, according to some embodiments of the present disclosure.

With the increase in the density and performance of the 3D memory device, improvement in the peripheral circuitry is also needed to provide functional support for the memory array, for example, reading, writing and erasing the data of the memory cells. Among the peripheral devices, capacitors are used to regular voltages in a 3D memory device, for example, boosting voltage for erasing memory data. Accordingly,FIGS. 4-8, 9A-9G, 10, 11A-11C, 12A-12C and 13illustrate a 3D capacitor of a memory device at various process stages, according to some embodiments of the present disclosure.

FIG. 4illustrates a cross-section of an exemplary peripheral circuitry400of a 3D memory device according to some embodiments of the present disclosure. The peripheral circuitry400can include a first substrate430, where the first substrate430can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, glass, III-V compound, any other suitable materials or any combinations thereof. In some embodiments, the first substrate430can be double-side polished prior to peripheral device fabrication. In this example, the first substrate430includes surfaces on the top and bottom sides (also referred to as a first side430-1and a second side430-2, or a front side and a backside, respectively) both polished and treated to provide a smooth surface for high quality semiconductor devices. The first and second sides are opposite sides of the first substrate.

The peripheral circuitry400can include one or more peripheral devices450on a first side430-1of the first substrate430. The peripheral device450can be formed “on” the first substrate430, in which the entirety or part of the peripheral device450is formed in the first substrate430(e.g., below the top surface of the first substrate430) and/or directly on the first substrate430. The peripheral device450can include any suitable semiconductor devices, for example, metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs), diodes, resistors, capacitors, inductors, etc. Among the semiconductor devices, p-type and/or n-type MOSFETs (i.e., CMOS) are widely implemented in logic circuit design, and are used as examples for the peripheral device450in the present disclosure. In this example, the peripheral circuitry400is also referred to CMOS wafer400.

A peripheral device450can be either a p-channel MOSFET or an n-channel MOSFET and can include, but not limited to, an active device region surrounded by shallow trench isolation (STI)452, a well454formed in the active device region with n-type or p-type doping, a gate stack456that includes a gate dielectric, a gate conductor and/or a gate hard mask. The peripheral device450can also include a source/drain extension and/or halo region (not shown inFIG. 4), a gate spacer458and a source/drain460locating on each side of the gate stack. The peripheral device450can further include a silicide contact area (not shown) in the top portion of the source/drain. Other known devices can be also formed on the first substrate430. The structure and fabrication method of the peripheral device450, are known to those skilled in the art, and are incorporated herein for entirety.

The STI452can be formed through patterning the substrate using lithography and etching, filling an insulating material and polishing the insulating material to form a coplanar surface on the first substrate430. An insulating material for STI can include silicon oxide, silicon oxynitride, TEOS, low-temperature oxide (LTO), high temperature oxide (HTO), silicon nitride, etc. An insulating material for STI452can be disposed using techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), low pressure chemical vapor deposition (LPCVD), high density plasma (HDP) chemical vapor deposition, rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), sputtering, thermal oxidation or nitridation, or combinations thereof. The forming of STI452can also include a high temperature annealing step to densify the disposed insulating material for improved electrical isolation. Other STI structures can be employed, as would be apparent to a person of ordinary skill in the art.

The well454of the peripheral device450can include a p-type doping for n-channel MOSFET and an n-type doping for p-channel MOSFET, and is called p-well and n-well, respectively. The dopant profile and concentration of the well454affects the device characteristics of the peripheral device450. For MOSFET devices with low threshold voltage (Vt), the well454can be doped with lower concentration, and can form low-voltage p-well or low-voltage n-well. For MOSFET with high Vt, the well454can be doped with higher concentration, and can form high-voltage p-well or high-voltage n-well. In some embodiments, to provide electrical isolation from a p-type substrate, a deep n-well can be formed underneath a high-voltage p-well for an n-channel MOSFET with high Vt. In some embodiments, a depth of the well454can be deeper than a depth of the STI452.

The forming of an n-well can include any suitable n-type dopant, such as phosphorus, arsenic, antimony, etc., and/or any combination thereof. The forming of a p-well can include any suitable p-type dopant, for example boron. The dopant incorporation can be achieved through ion implantation followed by activation anneal, or through in-situ doping during epitaxy for the active device region.

The gate stack456of the peripheral device450can be formed by a “gate first” scheme, where the gate stack456is disposed and patterned prior to source/drain formation. The gate stack456of the peripheral device450can also be formed by a “replacement” scheme, where a sacrificial gate stack can be formed first and then replaced by a high-k dielectric layer and a gate conductor after source/drain formation.

In some embodiments, the gate dielectric can be made of silicon oxide, silicon nitride, silicon oxynitride, and/or high-k dielectric films such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, or lanthanum oxide films, and/or combinations thereof. The gate dielectric can be disposed by any suitable methods such as CVD, PVD, PECVD, LPCVD, RTCVD, sputtering, MOCVD, ALD, thermal oxidation or nitridation, or combinations thereof.

In some embodiments, the gate conductor can be made from a metal or metal alloy, such as tungsten, cobalt, nickel, copper, or aluminum, and/or combinations thereof. In some embodiments, the gate conductor can also include a conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), etc. The gate conductor can be formed by any suitable deposition methods, for example, sputtering, thermal evaporation, e-beam evaporation, ALD, PVD, and/or combinations thereof.

In some embodiments, the gate conductor can also include a poly-crystalline semiconductor, such as poly-crystalline silicon, poly-crystalline germanium, poly-crystalline germanium-silicon and any other suitable material, and/or combinations thereof. In some embodiments, the poly-crystalline material can be incorporated with any suitable types of dopant, such as boron, phosphorous, or arsenic, etc. In some embodiments, the gate conductor can also be an amorphous semiconductor with aforementioned materials.

In some embodiments, the gate conductor can be made from a metal silicide, including WSix, CoSix, NiSix, or AlSix, etc. The forming of the metal silicide material can include forming a metal layer and a poly-crystalline semiconductor using similar techniques described above. The forming of metal silicide can further include applying a thermal annealing process on the deposited metal layer and the poly-crystalline semiconductor layer, followed by removal of unreacted metal.

The gate spacer458can be formed through disposing an insulating material and then performing anisotropic etching. The insulating material for the gate spacer458can be any insulator, including silicon oxide, silicon nitride, silicon oxyntiride, TEOS, LTO, HTO, etc. The gate spacer458can be disposed using techniques such as CVD, PVD, PECVD, LPCVD, RTCVD, MOCVD, ALD, sputtering, or combinations thereof. The anisotropic etching of the gate spacer458includes dry etching, for example reactive ion etching (ME).

A gate length L of the gate stack456between the source/drain460is an important feature of the MOSFET. During operation of a MOSFET, a top portion of the well underneath the gate stack456can conduct current from source to drain, and is so called channel of the MOSFET. The gate length L (also referred to as channel length) determines the magnitude of drive current of a MOSFET and is therefore scaled down aggressively for logic circuits. The gate length L can be less than about 100 nm. In some embodiments, the gate length can be in a range between about 5 nm to about 30 nm. Patterning of the gate stack with such a small dimension is very challenging, and can use techniques including optical proximity correction, double exposure and/or double etching, self-aligned double patterning, etc.

In some embodiments, the source/drain460of the peripheral device450is incorporated with high concentration dopants. For n-type MOSFETs, the dopant for source/drain460can include any suitable n-type dopant, such as phosphorus, arsenic, antimony, etc., and/or any combination thereof. For p-type MOSFETs, the dopant for source/drain460can include any suitable p-type dopant, for example boron. The dopant incorporation can be achieved through ion implantation followed by dopant activation anneal. The source/drain460can be made of the same material as the first substrate430, for example, silicon. In some embodiments, the source/drain460of the peripheral device450can be made of a different material from the first substrate430to achieve high performance. For example, on a silicon substrate, the source/drain460for a p-type MOSFETs can include SiGe and the source/drain460for an n-type MOSFETs can be incorporated with carbon. The forming of the source/drain460with a different material can include etching back the substrate material in the source/drain area and disposing new source/drain material using techniques such as epitaxy. Doping for source/drain460can also be achieved through in-situ doping during epitaxy.

The peripheral device450can also have an optional source/drain extension and/or halo region (not shown inFIG. 4) along each side of the gate stack456. The source/drain extension and/or halo region locates inside the active device region below the gate stack, and is implemented mainly for improved short channel control for the peripheral device450with a channel length less than about 0.5 μm. The forming of the source/drain extension and/or halo region can be similar to the forming of the source/drain460, but may use different implantation conditions (e.g., dose, angle, energy, species, etc.) to obtain optimized doping profile, depth or concentration.

The peripheral device450can be formed on the first substrate430with a planar active device region (as shown inFIG. 4), where the direction of MOSFET's channel and current flow is parallel to a surface of the first substrate430. In some embodiments, the peripheral device450can also be formed on the first substrate430with a 3D active device region, for example a so-called “FINFET” in a shape like a “FIN” (not shown), where the gate stack of the MOSFET is wrapped around the FIN, and the MOSFET's channel lies along three sides of the FIN (top and two sidewalls under the gate). The structure and methods for FINFET device are known to those skilled in the art and are not discussed further in present disclosure.

In some embodiments, the peripheral circuitry400can include a peripheral interconnect layer462(or a first interconnect layer) on the first side430-1, above the peripheral devices450, to provide electrical connections between different peripheral devices450and external devices (e.g., power supply, another chip, I/O device, etc.). The peripheral interconnect layer462can include one or more interconnect structures, for example, one or more vertical contact structures464and one or more lateral conductive lines466. The contact structure464and conductive line466can broadly include any suitable types of interconnects, such as middle-of-line (MOL) interconnects and back-end-of-line (BEOL) interconnects. The contact structure464and conductive line466in the peripheral circuitry400can include any suitable conductive materials such as tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicides (WSix, CoSix, NiSix, AlSix, etc.), metal alloys, or any combination thereof. The conductive materials can be deposited by one or more thin film deposition processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof.

The peripheral interconnect layer462can further include an insulating layer468. The insulating layer468in the peripheral interconnect layer462can include insulating materials, for example, silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide (such as F-, C-, N- or H-doped oxides), tetraethoxysilane (TEOS), polyimide, spin-on-glass (SOG), low-k dielectric material such as porous SiCOH, silsesquioxan (SSQ), or any combination thereof. The insulating materials can be deposited by one or more thin film deposition processes such as CVD, PVD, PECVD, ALD, high-density-plasma CVD (HDP-CVD), sputtering, spin-coating, or any combination thereof.

InFIG. 4, two conductive levels470-1and470-2(also referred to as “metal levels”) are illustrated as an example, where each metal level470(e.g.,470-1or470-2) include the contact structures464and the conductive lines466. The conductive lines466of the same metal level are located at the same distance from the first substrate430. The number of metal levels470for the peripheral circuitry400is not limited and can be any number optimized for the performance of the 3D memory.

The peripheral interconnect layer462can be formed by stacking metal levels470from bottom to the top of the peripheral circuitry400. In the example of the peripheral circuitry400inFIG. 4, the bottom metal level470-1can be formed first and then the upper metal level470-2can be formed on top of the bottom metal level470-1. Fabrication processes of each metal level470can include, but not limited to, disposing a portion of the insulating layer468with a thickness required for the metal level, patterning the portion of the insulating layer468using photo lithography and dry/wet etching to form contact holes for the contact structures464and the conductive lines466, disposing conductive materials to fill the contact holes for the contact structures464and the conductive lines466, and removing excessive conductive materials outside the contact holes by using planarization process such as chemical mechanical polishing (CMP) or reactive ion etching (ME).

In some embodiments, peripheral circuitry400also includes one or more substrate contacts472, where the substrate contacts472provide electrical connections to the first substrate430. The substrate contact472can include one or more conductive levels470with multiple tiers of vertical contact structures464and lateral conductive lines466. InFIG. 4, substrate contact472with one tier of contact structure and conductive line is shown as an example, where the vertical contact structure of the substrate contact472extends through the insulating layer468and electrically contacts the first substrate430.

In some embodiments, the topmost conductive lines466(e.g.,466-2inFIG. 4) can be exposed as the top surface of the peripheral circuitry400, where the topmost conductive lines466-2can be directly connected with the conductive lines on another chip or an external device.

In some embodiments, the topmost conductive lines466-2can be embedded inside the insulating layer468(as shown inFIG. 4), where the insulating material on top of the conductive lines466provide scratch protection during shipping or handling. Electrical connections to the topmost conductive lines466can be established later by forming metal VIAs, or simply by etching back the insulating layer468using dry/wet etching.

The peripheral device450, however, is not limited to MOSFET. The structures of the other devices, for example diodes, resistors, capacitors, inductors, BJTs, etc., can be formed simultaneously during MOSFETs fabrication through different mask design and layout. To form devices other than MOSFETs, process steps can be added or modified in a MOSFET's process flow, for example, processes to obtain different dopant profiles, film thicknesses or material stacks, etc. In some embodiments, the peripheral device450other than MOSFET can also be fabricated with additional design and/or lithography mask levels to achieve specific circuit requirements.

In some embodiments, a plurality of the peripheral devices450can be used to form any digital, analog, and/or mixed-signal circuits for the operation of the peripheral circuitry400. The peripheral circuitry400can perform, for example, row/column decoding, timing and control, reading, writing and erasing data of the memory array, etc.

In some embodiments, a 3D capacitor can be formed for the peripheral circuitry400. For example, a deep well455can be formed in the first substrate430while forming the wells454for MOSFETs. The deep well455can be p-type doped or n-type doped. The n-type dopant can be phosphorus, arsenic, antimony, etc. The p-type dopant can be, for example, boron. The dopant incorporation can be achieved through ion implantation from the first side430-1of the first substrate430, followed by activation anneal. In some embodiments, the deep well455can be formed on the first side430-1of the first substrate430through epitaxy and in-situ doping. The implantation for the deep well455can be performed right before or after the implantation for the well454. The dopant activation anneal for deep well455can be performed simultaneously as that for the well454.

In some embodiments, the deep well455can have a depth in a range between 1 μm to 5 μm. In some embodiments, the deep well455is highly doped. For example, the deep well455can be doped to 1×1018cm−3or higher.

In some embodiments, a deep well contact473can be formed to provide electrical connections to the deep well455and can serve as one of the two electrodes (e.g., anode) of a 3D capacitor. As such, the deep well contact473is also referred to as the first capacitor electrode. In some embodiments, the deep well contact473forms ohmic contact with the deep well455. The deep well contact473can form electrical connection with corresponding circuits of the peripheral circuitry400through the contact structures464and the conductive lines466in the peripheral interconnect layer462. For example, The deep well contact473can be connected with the ground, the substrate contact472of the first substrate430, the source or drain460or the gate stack456of peripheral device450, etc.

The deep well contacts473can be formed inside the insulating layer468and can include one or more contact structures464and one or more conductive lines466. In some embodiments, the deep well contact473is similar to substrate contact472and can include one tier of vertical contact structure and lateral conductive line. In some embodiments, the deep well contact473can be formed simultaneously with the contact structures464, conductive lines466and/or the substrate contact472.

FIG. 5illustrates a cross-section of an exemplary 3D memory array500, according to some embodiments of the present disclosure. The 3D memory array500(also referred to as memory array) can be a 3D NAND memory array and can include a second substrate530, the memory cells340and an array interconnect layer562(or a second interconnect layer). The second substrate530can be similar to the first substrate430. The array interconnect layer562can be similar to the peripheral interconnect layer462and can be formed using similar materials and similar processes. For example, interconnect structures (e.g., contact structures564and conductive lines566) and insulating layer568of the array interconnect layer562are similar to the interconnect structures (e.g., contact structures464, conductive lines466) and insulating layer468of the peripheral interconnect layer462, respectively.

In some embodiments, the 3D memory array500can be a memory array for 3D NAND Flash memory in which the memory cells340can be stacked vertically as the memory strings212. The memory string212extends through a plurality of conductor layer574and dielectric layer576pairs. The plurality of conductor/dielectric layer pairs are also referred to herein as an “alternating conductor/dielectric stack”578. The conductor layers574and the dielectric layers576in alternating conductor/dielectric stack578alternate in the vertical direction. In other words, except the ones at the top or bottom of the alternating conductor/dielectric stack578, each conductor layer574can be sandwiched by two dielectric layers576on both sides, and each dielectric layer576can be sandwiched by two conductor layers574on both sides. The conductor layers574can each have the same thickness or have different thicknesses. Similarly, the dielectric layers576can each have the same thickness or have different thicknesses. In some embodiments, the alternating conductor/dielectric stack578includes more conductor layers or more dielectric layers with different materials and/or thicknesses than the conductor/dielectric layer pair. The conductor layers574can include conductor materials such as W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, silicides (e.g., NiSix, WSix, CoSix, TiSix) or any combination thereof. The dielectric layers576can include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown inFIG. 5, each memory string212can include the channel layer338and the memory film337. In some embodiments, the channel layer338includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, the memory film337is a composite layer including a tunneling layer, a storage layer (also known as “charge trap/storage layer”), and a blocking layer. Each memory string212can have a cylinder shape (e.g., a pillar shape). The channel layer338, the tunneling layer, the storage layer, and the blocking layer are arranged along a direction from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon nitride, or any combination thereof. The blocking layer can include silicon oxide, silicon nitride, high dielectric constant (high-k) dielectrics, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the memory film337includes ONO dielectrics (e.g., a tunneling layer including silicon oxide, a storage layer including silicon nitride, and a blocking layer including silicon oxide).

In some embodiments, each conductor layer574in alternating conductor/dielectric stack578can act as the control gate for each memory cell of memory string212(for example control gates333inFIG. 3). As shown inFIG. 5, the memory string212can include the lower select gate332(e.g., a source select gate) at a lower end of the memory string212. The memory string212can also include the top select gate334(e.g., a drain select gate) at an upper end of the memory string212. As used herein, the “upper end” of a component (e.g., memory string212) is the end further away from second substrate530in the z-direction, and the “lower end” of the component (e.g., memory string212) is the end closer to second substrate530in the z-direction. As shown inFIG. 5, for each memory string212, the drain select gate334can be above the source select gate332. In some embodiments, the select gates332/334include conductor materials such as W, Co, Cu, Al, doped silicon, silicides, or any combination thereof.

In some embodiments, the 3D memory array500includes an epitaxial layer580on an lower end of the channel layer338of the memory string212. The epitaxial layer580can include a semiconductor material, such as silicon. The epitaxial layer580can be epitaxially grown from a semiconductor layer582on the second substrate530. The semiconductor layer582can be un-doped, partially doped (in the thickness direction and/or the width direction), or fully doped by p-type or n-type dopants. For each memory string212, the epitaxial layer580is referred to herein as an “epitaxial plug.” The epitaxial plug580at the lower end of each memory string212can contact both the channel layer338and a doped region of semiconductor layer582. The epitaxial plug580can function as the channel of the lower selective gate332at the lower end of memory string212.

In some embodiments, the array device further includes multiple contact structures214of word lines (also referred to as word line contacts) in the staircase region210. Each word line contact structure214can form electrical contact with the corresponding conductor layer574in the alternating conductor/dielectric stack578to individually control the memory cell340. The word line contact structure214can be formed by dry/wet etching of a contact hole, followed by filling with a conductor, for example, W, Ti, TiN, Cu, TaN, Al, Co, Ni, or any combination thereof.

As shown inFIG. 5, the 3D memory array500also includes bit line contacts584formed on the top of the memory strings212to provide individual access to the channel layer338of the memory strings212. The conductive lines connected with the word line contact structures214and the bit line contacts584form word lines and bit lines of the 3D memory array500, respectively. Typically the word lines and bit lines are laid perpendicular to each other (e.g., in rows and columns, respectively), forming an “array” of the memory.

In some embodiments, the 3D memory array500also includes a substrate contact572of the second substrate530. The substrate contact572can be formed using similar material and process as the substrate contact472of the first substrate430. The substrate contact572can provide electrical connection to the second substrate530of the 3D memory array500.

FIG. 6illustrates a cross-section of an exemplary 3D memory device600, according to some embodiments of the present disclosure. The 3D memory device600includes the peripheral circuitry400fabricated on the first substrate430and the 3D memory array500fabricated on the second substrate530. In this example, the peripheral circuitry400is flipped upside down and joined with the 3D memory array500with direct bonding or hybrid bonding. At a bonding interface688, the peripheral circuitry400and the 3D memory array500are electrically connected through a plurality of interconnect VIAs486/586.

In some embodiments, the bonding interface688of the 3D memory device600situates between the insulating layer468of the peripheral interconnect layer462and the insulating layer568of the array interconnect layer562. Interconnect VIAs486and586can be joined at bonding interface688to electrically connect any conductive line466or contact structure464of the peripheral interconnect layer462and any conductive line566or contact structure564of the array interconnect layer562. As such, the peripheral circuitry400and the 3D memory array500can be electrically connected.

In some embodiments, the bonding interface688of the 3D memory device600situates inside a bonding layer690. In this example, the interconnect VIAs486and586extend through the bonding layer690and also form electrical connections between any conductive line466or contact structure464of the peripheral interconnect layer462and the conductive line566or contact structure564of the array interconnect layer562. As such, the peripheral circuitry400and the 3D memory array500can also be electrically connected.

In some embodiments, the bonding layer690can be disposed on top of the peripheral circuitry400(inFIG. 4) and/or the 3D memory array500(inFIG. 5) prior to bonding process. The bonding layer690can include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride or any combination thereof. The bonding layer690can also include adhesion materials, for example, epoxy resin, polyimide, dry film, photosensitive polymer, etc. The bonding layer690can be formed by one or more thin film deposition processes such as CVD, PVD, PECVD, ALD, high-density-plasma CVD (HDP-CVD), sputtering, spin-coating, or any combination thereof.

In some embodiments, after forming the bonding layers690, the interconnect VIAs486and586can be formed for the peripheral circuitry400and the 3D memory array500, respectively. The interconnect VIAs486/586can include metal or metal alloy such as copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof. The metal or metal alloy of the interconnect VIAs486/586can be disposed by one or more thin film deposition processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof.

The fabrication process of the interconnect VIAs486/586can further include, but not limited to, photolithography, wet/dry etching, planarization (e.g., CMP, or RIE etch-back), etc.

In some embodiments, the peripheral circuitry400and the 3D memory array500can be bonded together at die level (e.g., die-to-die, or chip-to-chip) or at wafer level (e.g., wafer-to-wafer or chip-to-wafer), depending on the product design and manufacturing strategy. Bonding at wafer level can provide high throughput, where all the dies/chips on the first substrate430with the peripheral circuitry400can be joined simultaneously with the second substrate530with the 3D memory array500. Individual 3D memory device600can be diced after wafer bonding. On the other hand, bonding at die level can be performed after dicing and die testing, where functional dies of the peripheral circuitry400and 3D memory array500can be selected first and then bonded to form 3D memory device600, enabling higher yield of 3D memory device600.

In some embodiments, during the bonding process, the peripheral interconnect layer462can be aligned with the array interconnect layer562when the interconnect VIAs486of the peripheral circuitry400are aligned with corresponding interconnect VIAs586of the 3D memory array500. As a result, corresponding interconnect VIAs486/586can be connected at the bonding interface688and the 3D memory array500can be electrically connected with the peripheral circuitry400.

In some embodiments, the peripheral circuitry400and the 3D memory array500can be joined by hybrid bonding. Hybrid bonding, especially metal/dielectric hybrid bonding, can be a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives), which obtains metal-metal bonding and dielectric-dielectric bonding simultaneously.

In some embodiments, the peripheral circuitry400and the 3D memory array500can be bonded by using the bonding layer690. At the bonding interface688, the bonding can take place between silicon nitride to silicon nitride, silicon oxide to silicon oxide, or silicon nitride to silicon oxide, in addition to metal to metal bonding. In some embodiments, the bonding layer can also include an adhesive material to enhance bonding strength, for example, epoxy resin, polyimide, dry film, etc.

In some embodiments, a treatment process can be used to enhance the bonding strength at the bonding interface688. The treatment process can prepare the surfaces of array interconnect layer562and the peripheral interconnect layer462so that the surfaces of the insulating layers562/462form chemical bonds. The treatment process can include, for example, plasma treatment (e.g. with F, Cl or H containing plasma) or chemical process (e.g., formic acid). In some embodiments, the treatment process can include a thermal process that can be performed at a temperature from about 250° C. to about 600° C. in a vacuum or an inert ambient (e.g., with nitrogen or Argon). The thermal process can cause metal inter-diffusion between the interconnect VIAs486and586. As a result, metallic materials in the corresponding pairs of the interconnect VIAs can be inter-mixed with each other or forming alloy after the bonding process.

After bonding the peripheral and array interconnect layers together, at least one peripheral device of the peripheral circuitry400fabricated on the first substrate430can be electrically connected with at least one memory cell of the 3D memory array500fabricated on the second substrate530.

FIG. 6illustrates an embodiment that the peripheral circuitry400is bonded on top of the 3D memory array500. In some embodiments, the 3D memory array500can be bonded on top of the peripheral circuitry400.

Through bonding, the 3D memory device600can function similar to a 3D memory where peripheral circuitry and memory array are fabricated on the same substrate (as shown inFIG. 1). By stacking the 3D memory array500and the peripheral circuitry400on top of each other, the density of the 3D memory device600can be increased. In the meantime, the bandwidth of the 3D memory device600can be increased because of the interconnect distance between the peripheral circuitry400and the 3D memory array500can be reduced by using the stacked design.

FIG. 7illustrates a cross-sectional view of a 3D memory device700, according to some embodiments of the present disclosure. The 3D memory device700resembles the 3D memory device600inFIG. 6, also including the peripheral circuitry400and the 3D memory array500, where the peripheral circuitry400is bonded to the 3D memory array500at the bonding interface688. The 3D memory device700can be formed by thinning the first substrate430of the peripheral circuitry400after forming the 3D memory device600through bonding.

In some embodiments, the first substrate430of the peripheral circuitry400can be thinned down from the backside430-2(or the second side) to expose the deep well455. In some embodiments, substrate thinning process can include one or more of grinding, dry etching, wet etching, and chemical mechanical polishing (CMP). The thickness of the first substrate430after thinning can be in a range between 1 μm to 5 μm.

FIG. 8illustrates a cross-sectional view of a 3D memory device800, according to some embodiments of the present disclosure. The 3D memory device800can be formed by disposing a capping layer892on the backside430-2(or the second side) of the first substrate430. The capping layer892can be any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide (such as F-, C-, N- or H-doped oxides), tetraethoxysilane (TEOS), polyimide, spin-on-glass (SOG), low-k dielectric material such as porous SiCOH, silsesquioxan (SSQ), or any combination thereof. The insulating materials can be deposited by one or more thin film deposition processes such as CVD, PVD, PECVD, ALD, high-density-plasma CVD (HDP-CVD), sputtering, spin-coating, or any combination thereof. After deposition, the capping layer892covers the entire surface of the first substrate430including the deep well455.

FIG. 9Aillustrates a cross-sectional view of a 3D memory device900, according to some embodiments of the present disclosure, wherein the 3D memory device900includes a plurality of trenches994and a through-silicon-trench (TST)995formed on the backside430-2(the second side) of the first substrate430. In this example, through-silicon-trench995penetrates through the capping layer892and the entire first substrate430, exposing the insulating layer468at the bottom of the trenches. In some embodiments, the trenches994can be similar to the TST995and can extend through the capping layer892and the entire first substrate430, exposing the insulating layer468at the bottom of the trenches (as shown inFIG. 9A). In some embodiments, the trenches994can extend through the capping layer892into the deep well455of the first substrate430, but leaving a portion of the deep well455at the bottom of the trenches.

The trenches994and TST995can be formed by using photolithography and etching. The etching process used for the trenches994and TST995can include wet chemical etching, reactive ion etching (ME), high-aspect ratio plasma etching, or any combination thereof. In some embodiments, the silicon of the first substrate430can be etched by alternating plasma etching using SF6chemistry and protection film deposition using C4F8chemistry. In some embodiments, the trenches994and TST995can be formed sequentially, e.g., the TST995can be formed first and then the trenches994can be formed, or vice versa.

In some embodiments, the width d1of the TST995can be narrower than the width d2of the trenches994. In some embodiments, the TST995can be formed inside the deep well455(as shown inFIG. 9A).

In some embodiments, ion implantation can be performed after forming the trenches994to modify doping profile or concentration in the deep well455along sidewalls of the trenches994.

InFIG. 9A, region901highlights a precursor region for a 3D capacitor according to some embodiments of the present disclosure, and will be further discussed in detail.

FIG. 9Billustrates an enlarged cross-sectional view of the region901of the 3D memory device900inFIG. 9A, andFIG. 9Cillustrates a corresponding layout of region901, according to some embodiments of the present disclosure. InFIG. 9C, the capping layer892is omitted to show the underlying layers in the top-down view and the deep well contacts473are shown as reference.

In some embodiments, the TST995forms an enclosed area, a capacitor precursor region903. The TST995can isolate the capacitor precursor region903from other devices on the first substrate430, i.e., the TST995defines an active area for a 3D capacitor. As such, the capacitor precursor region903is also referred to as the active area for a 3D capacitor.

In some embodiments, TST995can be formed by etching through the deep well455, i.e., the TST995is sandwiched or surrounded by the deep well455(as shown inFIGS. 9B and 9C.)

In some embodiments, TST995can be formed by etching through the relatively lightly doped area of the first substrate430, i.e., TST995situates outside the deep well455(as shown inFIGS. 9D and 9E). In this example, the capacitor precursor region903enclosed by the TST995includes both deep well455and a portion of lightly doped first substrate430.

InFIG. 9C, the trenches994are laid out in squares and arranged in an array. In some embodiments, the trench994can be rectangular, circular, or any other shape. The arrangement of trenches994can be interdigitated fingers (shown inFIG. 9F), concentric circles (shown inFIG. 9G), etc. For simplicity, layout inFIG. 9Cwill be used as examples in the following descriptions to illustrate structures and methods for forming a 3D capacitor for a memory device. It is known to the person skilled in the art to reproduce similar features for other layouts and designs.

FIG. 10illustrates a cross-sectional view of a 3D memory device1000, according to some embodiments of the present disclosure. The 3D memory device1000includes a capacitor dielectric layer1096disposed on the 3D memory device900inFIG. 9A. The capacitor dielectric layer1096can be any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, and/or high-k dielectric films such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, or lanthanum oxide films, and/or combinations thereof. The capacitor dielectric layer1096can be disposed by any suitable methods such as CVD, PVD, PECVD, LPCVD, RTCVD, sputtering, MOCVD, ALD, thermal oxidation or nitridation, or combinations thereof.

In some embodiments, the capacitor dielectric layer1096is conformal, covering horizontal and vertical surfaces with similar thickness, i.e., t1is about the same dimension as t2inFIG. 10. In some embodiments, the capacitor dielectric layer1096can have a different thickness on horizontal and vertical surfaces, i.e., t1≠t2. In some embodiments, the thicknesses t1and t2of the capacitor dielectric layer1096can be in a range of 10 nm to 2000 nm.

In some embodiments, the width d1of the TST995inFIG. 9Acan be narrower than the width d2of the trenches994. In this example, the capacitor dielectric layer1096can completely fill up the TST995to form a deep trench isolation (DTI)1093if the thickness t1of the capacitor dielectric layer1096is more than half the width d1of the TST995. In the meantime, after depositing the capacitor dielectric layer1096, trench994can have an opening994′, wherein the opening994′ can have a width d3equivalent to d2-2t1.

In some embodiments, the formation of DTI1093and the deposition of the capacitor dielectric layer1096can be performed sequentially. For example, the TST995can be formed first from the backside430-2of the first substrate430, followed by deposition of an insulating material inside the TST995to form DTI1093. In this example, the insulating material for the DTI1093can have a thickness larger enough to completely fill up the TST995. As an option, the insulating material for the DTI1093outside the TST995can be removed by planarization process such as chemical-mechanical-polishing (CMP) or RIE. The trench994can then be formed, followed by deposition of the capacitor dielectric layer1096. In this example, the insulating material for the DTI1093can be different from the capacitor dielectric layer1096.

FIG. 11Aillustrates a cross-sectional view of a 3D memory device1100, according to some embodiments of the present disclosure. The 3D memory device1100includes a capacitor contact1198formed inside the opening994′ of the 3D memory device1000inFIG. 10, wherein the capacitor contact1198covers a sidewall of the capacitor dielectric layer1096inside the trench994.

The capacitor contact1198can be made from any suitable conductive material, for example, a metal or metal alloy such as tungsten, cobalt, nickel, copper, or aluminum, and/or combinations thereof. In some embodiments, the capacitor contact1198can also include a conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), etc. The capacitor contact1198can be formed by any suitable deposition methods, for example, sputtering, thermal evaporation, e-beam evaporation, ALD, PVD, and/or combinations thereof.

In some embodiments, the capacitor contact1198can also include a poly-crystalline semiconductor, such as poly-crystalline silicon, poly-crystalline germanium, poly-crystalline germanium-silicon and any other suitable material, and/or combinations thereof. In some embodiments, the poly-crystalline material can be incorporated with any suitable types of dopant, such as boron, phosphorous, or arsenic, etc. In some embodiments, the capacitor contact1198can also be an amorphous semiconductor of the aforementioned materials. The poly-crystalline and amorphous semiconductors can be doped with p-type or n-type dopants. The dopants can be incorporated inside the poly-crystalline and amorphous semiconductors by processes such as ion implantation, in-situ doping during deposition, etc. The n-type dopants can be boron and the p-type dopants can be phosphorus or arsenic.

In some embodiments, the capacitor contact1198can be a metal silicide, including WSix, CoSix, NiSix, or AlSix, etc. The forming of the metal silicide material can include depositing a poly-crystalline semiconductor and a metal layer inside the opening994′ using similar techniques described above. The forming of metal silicide can further include applying a thermal annealing process on the deposited metal layer and the poly-crystalline semiconductor layer. In some embodiments, unreacted metal after silicide formation can be removed by, for example, wet chemical etching.

In some embodiments, capacitor contact1198can be coplanar with the capping layer892by implementing a planarization process, for example CMP or RIE, after depositing the conductive material of the capacitor contact1198. The corresponding structure is shown inFIG. 11A. In this example, the planarization process removes excessive conductive material of the capacitor contacts1198and the capacitor dielectric layer1096outside the trenches994.

In some embodiments, the planarization process removes excessive conductive material of the capacitor contacts1198outside trenches994and stops on or into the capacitor dielectric layer1096. As such, at least a portion of the capacitor dielectric layer1096remains on the capping layer892. In this example, the capacitor contact1198can be coplanar with the capacitor dielectric layer1096on top of the capping layer892(not shown inFIG. 11A).

FIG. 11Billustrates an enlarged cross-sectional view of the region1101of the 3D memory device1100inFIG. 11A, andFIG. 11Cillustrates the corresponding top-down view of the region1101, according to some embodiments of the present disclosure. InFIG. 11C, the capping layer892is omitted to show the underlying layers in the top-down view and the deep well contacts473are shown as reference.

In some embodiments, the capacitor contact1198and the capacitor dielectric layer1096are exposed from the second side (backside)430-2of the first substrate430after planarization of the capacitor contact1198. In this example, the capacitor contact1198covers a sidewall of the capacitor dielectric layer1096and the capacitor dielectric layer1096covers a sidewall994sof the trench994.

As shown inFIGS. 11B and 11C, a 3D capacitor1195is formed in the region1101of the 3D memory device1100. The 3D capacitor1195includes a plurality of vertical capacitors1197inside the active area903defined by the deep trench isolation1093, wherein the DTI1093isolates the 3D capacitor1195from other devices of the 3D memory device1100. Each vertical capacitor1197includes the capacitor dielectric layer1096sandwiched between the capacitor contact1198and the deep well455, wherein the capacitor contact1198is surrounded by the capacitor dielectric layer1096and the capacitor dielectric layer1096is surrounded by the deep well455.

FIG. 12Aillustrates a cross-sectional view of a 3D memory device1200, according to some embodiments of the present disclosure. The 3D memory device1200includes a second capacitor electrode1299on the capacitor contacts1198on the second side430-2of the first substrate430. The second capacitor electrode1299forms electrical connections with the capacitor contacts1198.

In some embodiments, the second capacitor electrode1299can be made from any suitable conductive materials such as a metal or metal alloy, for example, tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicides (WSix, CoSix, NiSix, AlSix, etc.), or any combination thereof. The conductive materials can be deposited by one or more thin film deposition processes such as CVD, PECVD, PVD, ALD, electroplating, electroless plating, sputtering, evaporation, or any combination thereof.

In some embodiments, the second capacitor electrode1299can be patterned using, for example, photolithography and wet/dry etching. In some embodiments, the second capacitor electrode1299can also be patterned with damascene process, where the damascene process can include, but not limited to, depositing an insulating layer, patterning the insulating layer, depositing a metallic material and performing CMP.

FIG. 12Billustrates an enlarged cross-sectional view of a region1201of the 3D memory device1200inFIG. 12A, andFIG. 12Cillustrates the corresponding top-down view of the region1201, according to some embodiments of the present disclosure. InFIG. 12C, the capping layer892is omitted to show the underlying layers in the top-down view and the deep well contacts473are shown as reference.

In some embodiments, the second capacitor electrode1299can be connected with all the capacitor contacts1198enclosed inside the active area903defined by the DTI1093, providing a common cathode for the 3D capacitor1195, while the deep well contacts473provide a common anode for the 3D capacitor1195. In some embodiments, the second capacitor electrode1299can be the anode and the deep well contacts473can be the cathode of the 3D capacitor1195. As shown inFIG. 12B, the 3D capacitor1195includes the deep well455extending through the entire first substrate430from the first side430-1to the second side430-2opposite of the first side430-1. The deep trench isolation1093extends completely through the first substrate430and defines the active area for the 3D capacitor1195. In some embodiments, the deep trench isolation1093penetrates completely through the deep well455. In some embodiments, the deep trench isolation1093penetrates completely through the lightly doped area of the first substrate430.

In some embodiments, the capacitance of the 3D capacitor1195can be the sum of the vertical capacitors1197. As such, increasing the number of the vertical capacitors1197can increase the capacitance of the 3D capacitor1195. In addition, increasing the capacitance of the vertical capacitor1197can increase the overall capacitance of the 3D capacitor1195. For example, increasing depth “h” of the vertical capacitors1197can increase the capacitance of the 3D capacitor1195. In some embodiments, increasing thickness of the deep well455can allow deeper vertical capacitors1197. In some embodiments, using capacitor dielectric layer1096with higher dielectric constant can also increase the capacitance of the vertical capacitor1197and the 3D capacitor1195.

In some embodiments, the vertical capacitor1197has a square cross-section where the width d2is determined at formation of trench994(seeFIG. 9A). In this example, the effective device area of the vertical capacitor1197is determined by 4d2·h. To reduce area consumption on a wafer (e.g., the first substrate430), the structure of the vertical capacitor1197can allow scaling the width d2without scarifying the capacitance by increasing the depth “h”. Therefore, comparing with traditional 2D capacitors, vertical capacitor1197and 3D capacitor1195can provide high density and high capacitance for the 3D memory device1200.

FIG. 13illustrates an exemplary fabrication process1300for forming the 3D memory devices shown inFIGS. 4-8, 9A-9G, 10, 11A-11C and 12A-12C, in accordance with some embodiments. It should be understood that the operations shown in fabrication process1300are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. In some embodiments, some process steps of exemplary fabrication process1300can be omitted or include other process steps that are not described here for simplicity. In some embodiments, process steps of method1300can be performed in a different order and/or vary.

As shown inFIG. 13, fabrication process1300starts at process step S1310, in which a peripheral circuitry is formed on a first side of a first substrate. In some embodiments, the forming of the peripheral circuitry includes forming one or more peripheral devices and a peripheral interconnect layer. The forming of the peripheral circuitry further includes forming a deep well and a deep well contact (or a first capacitor electrode) on the first side of the first substrate. As an example, the peripheral circuitry can be the peripheral circuitry400shown inFIG. 4, including the peripheral device450and the peripheral interconnect layer462. The fabrication process for the peripheral circuitry can be similar to fabrication process for the peripheral circuitry400.

In some embodiments, the deep well, such as the deep well455inFIG. 4, can be formed by ion implantation prior to well implantation for the peripheral devices. Forming the deep well can also include an activation annealing. The deep well can also be formed by epitaxy and in-situ doping. An epitaxial layer can be deposited as a blank film on the first substrate or can be deposited in a selected region on the first substrate where silicon oxide or nitride can be used as an mask during the epitaxy process.

In some embodiments, the deep well contact (or the first capacitor electrode), such as the deep well contact473inFIG. 4, can be formed during middle-end-of-line and/or back-end-of-line fabrication for the peripheral interconnect layer. The deep well contact can include one or more vertical contact structures and lateral conductive lines. The forming of the deep well contact can include forming a trench by etching through an insulating layer (e.g., insulating layer468) and filling the trench with a conductive material. The conductive material can be patterned by conventional lithography and wet/dry etching or by planarization process such as CM′ and/or RIE etch back. The forming of the deep well contact can also include dual damascene process, for example, etching the insulating layer468for both vertical contact structure and lateral conductive line prior to the deposition of the conductive material and planarization process.

In some embodiments, a plurality of peripheral interconnect VIAs can be formed for the peripheral circuitry400. The peripheral interconnect VIAs can be the interconnect VIAs486inFIG. 6, and can be made of similar material. The peripheral interconnect VIAs are formed to make electrical connections for the peripheral circuitry. The fabrication processes for the peripheral interconnect VIA include, lithography, trench formation using wet/dry etching, disposing and filling conductive material inside the trench, and removing excess materials outside the trench by using a planarization process such as CMP.

In some embodiments, a bonding layer can be disposed on the peripheral circuitry. The bonding layer can be the bonding layer690inFIG. 6, and can be fabricated using similar techniques.

At process step S1320, a 3D memory array is formed on a second substrate. In some embodiments, the 3D memory array can be the 3D memory array500inFIG. 5. The 3D memory array can include a plurality of memory cells and an array interconnect layer, for example, the memory cells340and the array interconnect layer562. In some embodiments, the 3D memory array is a 3D NAND flash memory and can include at least a memory string (e.g., the memory string212) and a staircase structure.

In some embodiments, fabrication of the 3D memory array500can include forming a plurality of dielectric layer pairs (also referred to herein as an “alternating dielectric stack”) with a first dielectric layer576and a second dielectric layer (not shown in figures) that is different from first dielectric layer576. In some embodiments, the first dielectric layer can be silicon oxide and the second dielectric layer can be silicon nitride. Alternating dielectric stack can be formed by one or more thin film deposition processes such as CVD, PVD, ALD, sputtering, or any combination thereof.

In some embodiments, fabrication of the 3D memory array500can also include forming a staircase structure at an end of the alternating dielectric stack by using multiple etch-trim processes.

In some embodiments, fabrication of the 3D memory array500can also include removing the second dielectric layer and replacing with a conductor layer574to form an alternating conductor/dielectric stack578. The replacement of the second dielectric layers with conductor layers574can be performed by wet etching the second dielectric layers selective to first dielectric layers576and filling the structure with conductor layers574. The conductor layer574includes polysilicon, W, Co, Ti, TiN, Ta, TaN, Al, Ni, silicides, etc., and can be filled by CVD, ALD, etc.

In some embodiments, fabrication of the 3D memory array500can further include forming a plurality of memory strings212penetrating alternating conductor/dielectric stack578. In some embodiments, fabrication processes to form memory strings212can include forming a channel layer338that extends vertically through alternating conductor/dielectric stack578. In some embodiments, channel layer338can be an amorphous silicon layer or a polysilicon layer formed by using a thin film deposition process, such as a CVD, ALD, etc.

In some embodiments, fabrication processes to form memory strings212can further include forming a memory film337between the channel layer338and the plurality of conductor/dielectric layer pairs in alternating conductor/dielectric stack578. Memory film337can be a composite dielectric layer, such as a combination of multiple dielectric layers such as a blocking layer, a storage layer, and a tunneling layer.

The blocking layer can be used for blocking the outflow of the electronic charges. In some embodiments, the blocking layer can be a silicon oxide layer or a combination of silicon oxide/silicon oxynitride/silicon oxide (SiO2—SiON—SiO2) multi-layer stack. In some embodiments, the blocking layer includes high dielectric constant (high-k) dielectrics (e.g., aluminum oxide). In one example, the blocking layer includes a silicon oxide layer formed by In-Situ Steam Generation (ISSG) oxidation after a silicon nitride deposition process.

The storage layer can be used for storing electronic charges. The storage and/or removal of charges in the storage layer can impact the on/off state and/or a conductance of the semiconductor channel. The storage layer can include polycrystalline silicon (polysilicon) or silicon nitride. The storage layer can include one or more films of materials including, but are not limited to, silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride, or any combination thereof. In some embodiments, the storage layer can include a nitride layer formed by using one or more deposition processes.

The tunneling layer can be used for tunneling electronic charges (electrons or holes). The tunneling layer can be dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the tunneling layer can be an oxide layer formed by using a deposition process.

In some embodiments, fabrication of the 3D memory array500can further include forming an epitaxial layer580at an end of memory string212. In some embodiments, epitaxial layer580can be formed in the second substrate, and correspond to each memory string212as an epitaxial plug580. Epitaxial layer580can be implanted to a desired doping level.

In some embodiments, fabrication of the 3D memory array500can further include forming multiple word line contacts. As illustrated inFIG. 5, each word line contact structure214can extend vertically to form electrical contact to a corresponding conductor layer574of the staircase structure, wherein each conductor layer574can individually control a memory cell of memory strings212. In some embodiments, fabrication processes to form word line contact structures214include forming a vertical opening through an insulating layer568using dry/wet etch process, followed by filling the opening with conductive materials such as W, Co, Cu, Al, doped poly-silicon, silicides, or any combination thereof. The conductive materials can be disposed by ALD, CVD, PVD, plating, sputtering, or any combination thereof.

In some embodiments, fabrication of the 3D memory array500can further include forming the array interconnect layer562, which can electrically connect the memory strings with word lines and bit lines. As shown inFIG. 5, in some embodiments, the array interconnect layer562can include one or more contact structures564and conductive lines566in the insulating layer568. In some embodiments, fabrication processes to form array interconnect layer562include forming the insulating layer568, followed by forming a plurality of bit line contacts584in contact with memory strings212in the insulating layer568. The insulating layer568can include one or more layers of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The insulating layer568can be formed by one or more thin film deposition processes such as CVD, PVD, PECVD, ALD, high-density-plasma CVD (HDP-CVD), sputtering, spin-coating, or any combination thereof. Bit line contacts584can be formed by forming openings in the insulating layer568, followed by filling the openings with conductive materials such as W, Co, Cu, Al, Ti, TiN, Ta, TaN, doped silicon, silicides, or any combination thereof, deposited by CVD, PVD, sputtering, evaporating, plating, or any combination thereof.

In some embodiments, fabrication processes to form array interconnect layer562further include forming one or more conductive lines566and one or more contact structures564in the insulating layer568. Conductor layers and contact layers can include conductor materials such as W, Co, Cu, Al, Ti, Ta, TiN, TaN, doped silicon, silicides, or any combination thereof. Conductor layers and contact layers can be formed by any suitable known BEOL methods.

In some embodiments, other structures can also be formed on the 3D memory array, for example, a bonding layer, a plurality of interconnect VIAs and a substrate contact, which are illustrated inFIGS. 5 and 6, as the bonding layer690, the interconnect VIAs586and the substrate contact572.

In some embodiments, the bonding layer690can be disposed on the 3D memory array500after completing the array interconnect layer562. The bonding layer690can include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride or any combination thereof. The bonding layer690can also include adhesion materials, for example, epoxy resin, polyimide, dry film, photosensitive polymer, etc. The bonding layer690can be formed by one or more thin film deposition processes such as CVD, PVD, PECVD, ALD, high-density-plasma CVD (HDP-CVD), sputtering, spin-coating, or any combination thereof.

In some embodiments, the interconnect VIAs586can be formed in the array interconnect layer562, electrically connected with one or more of the conductive lines566and/or the contact structures564on the 3D memory array500. The fabrication process of the interconnect VIA586can be similar to the interconnect VIA486.

At process step S1330, the peripheral circuitry can be bonded to the 3D memory array to form a 3D memory device, wherein the 3D memory device can be the 3D memory device600inFIG. 6.

In some embodiments, the peripheral circuitry400and the 3D memory array500can be bonded together at die level (e.g., die-to-die, or chip-to-chip) or at wafer level (e.g., wafer-to-wafer or chip-to-wafer), depending on the product design and manufacturing strategy. Bonding at wafer level can provide high throughput, where all the dies/chips on the first substrate with the peripheral circuitry400can be joined simultaneously with the second substrate with the 3D memory array500. Individual 3D memory device600can be diced after wafer bonding. On the other hand, bonding at die level can be performed after dicing and die test, where functional dies of the peripheral circuitry400and 3D memory array500can be selected first and then bonded to form 3D memory device600, enabling higher yield of 3D memory device600.

In some embodiments, the 3D memory array500can be flipped upside down and positioned above the peripheral circuitry (or vice versa). The array interconnect layer562of the 3D memory array500can be aligned with the peripheral interconnect layer462of the peripheral circuitry400.

In some embodiments, aligning the array interconnect layer562with peripheral interconnect layer462is performed by aligning interconnect VIAs586of the 3D memory array500with corresponding interconnect VIAs486of the peripheral circuitry400. As a result, corresponding interconnect VIAs can be connected at a bonding interface688and the 3D memory array500can be electrically connected with the peripheral circuitry400.

In some embodiments, the peripheral circuitry400and the 3D memory array500can be joined by hybrid bonding. Hybrid bonding, especially metal/dielectric hybrid bonding, can be a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives), which obtains metal-metal bonding and dielectric-dielectric bonding simultaneously. As illustrated inFIG. 6, the 3D memory array500can be joined with the peripheral circuitry400, thereby forming the bonding interface688.

In some embodiments, a bonding layer can be formed on the peripheral circuitry400and/or 3D memory array500prior to hybrid bonding. At the bonding interface688, the bonding can take place between silicon nitride to silicon nitride, silicon oxide to silicon oxide, or silicon nitride to silicon oxide, in addition to metal to metal bonding. In some embodiments, the bonding layer can also include an adhesive material to enhance bonding strength, for example, epoxy resin, polyimide, dry film, etc.

In some embodiments, a treatment process can be used to enhance the bonding strength at the bonding interface688. The treatment process can prepare the surfaces of array interconnect layer562and the peripheral interconnect layer462so that the surfaces of the insulating layers568/468form chemical bonds. The treatment process can include, for example, plasma treatment (e.g. with F, Cl or H containing plasma) or chemical process (e.g., formic acid). In some embodiments, the treatment process can include a thermal process that can be performed at a temperature from about 250° C. to about 600° C. in a vacuum or an inert ambient (e.g., with nitrogen or Argon). The thermal process can cause metal inter-diffusion between the interconnect VIAs586and486. As a result, metallic materials in the corresponding pairs of the interconnect VIAs can be inter-mixed with each other or forming alloy after the bonding process.

At process step S1340, the first substrate can be thinned after bonding. The thinning process can be performed from a second side (or backside) of the first substrate, wherein the second side of the first substrate is opposite the first side, further away from the peripheral devices. After thinning, the deep well can be exposed from the second side of the first substrate.

In some embodiments, a handle wafer (e.g., glass, plastic, or silicon) can be attached to the second substrate prior to the thinning process. In some embodiments, substrate thinning process can include one or more of grinding, dry etching, wet etching, and chemical mechanical polishing (CMP).

After thinning the first substrate, a capping layer can be deposited on the second side of the first substrate. The capping layer can be the capping layer892inFIG. 8, and can be made from similar material using similar process.

At process step S1350, a plurality of trenches (e.g., trenches994inFIG. 9A) are formed inside the deep well. The trenches can be formed by patterning the capping layer and the deep well. The patterning process can include photolithography and wet/dry etching. The patterning process can be performed from the second side of the first substrate. In some embodiments, the trenches penetrates through the deep well455or the first substrate430. In some embodiments, the trenches extend into a portion of the deep well455.

In some embodiments, a through-silicon-trench (TST), for example, TST995inFIG. 9Acan be formed simultaneously as the trenches994. In some embodiments, the TST995can have a width narrower than the trenches994.

At process step S1360, a capacitor dielectric layer is disposed on sidewalls of trench994and TST995. The capacitor dielectric layer can be the capacitor dielectric layer1096inFIG. 10, and can be made from a similar material using a similar process.

In some embodiments, a deep trench isolation (e.g., the deep trench isolation1093) can be formed after depositing the capacitor dielectric layer1096in the TST995, as shown inFIG. 10. In this example, the capacitor dielectric layer1096completely fills up the TST995, while leaving openings in trenches994.

At process step S1370, an capacitor contact is formed on a sidewall of the capacitor dielectric layer1096inside the trench994. The capacitor contact can be the capacitor contact1198inFIG. 11A, and can be made from similar material using a similar process.

At process step S1380, a second capacitor electrode (e.g., the second capacitor electrode1299inFIG. 12) is formed on top of the capacitor contacts, forming electrical connections with the capacitor contacts1198.

In some embodiments, the deep trench isolation can be formed before the formation of the trenches994. In this example, the TST995can be formed in the first substrate first, followed by deposition of an insulating material inside the TST995. The insulating material can be any suitable insulator, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS, spin-on-glass, etc. Prior to patterning the trenches994, an optional planarization process can be used, for example, chemical-mechanical-polishing. The process can then resume with the formation of the trenches994. In this example, the TST995and trenches994can have different depth and the TST995can be filled with the insulating material different from the capacitor dielectric layer1096.

The present disclosure describes various embodiments of a three-dimensional (3D) capacitor for a memory device and methods of making the same.

In some embodiments, a method for forming a 3D capacitor for a memory device includes forming, on a first side of a first substrate, a peripheral circuitry including a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode, wherein the first capacitor electrode is electrically connected with the deep well. The method also includes forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method further includes bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array, such that at least one peripheral device of the peripheral circuitry is electrically connected with at least one memory cell of the memory array. The method also includes forming, on a second side of the first substrate, one or more trenches inside the deep well, wherein the first and second sides are opposite sides of the first substrate. The method further includes disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.

In some embodiments, a 3D capacitor for a memory device includes a deep well formed on a second side of a first substrate, wherein a first side of the first substrate, opposite of the second side, includes a plurality of peripheral devices and a first interconnect layer. The 3D capacitor also includes a first capacitor electrode electrically connected with the deep well. The 3D capacitor further includes one or more trenches inside the deep well, and a capacitor dielectric layer on sidewalls of the one or more trenches. The 3D capacitor also includes capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches, and a second capacitor electrode disposed on the capacitor contacts.