Phase/frequency detector for tracking receivers

A receiving device within a digital electronic system includes a sampling unit, a voter block, and a local clock phase adjustment unit. The sampling unit samples an input line at three points in time at intervals of one half of a bit period. The sampling unit delivers the values obtained in the sampling process to the voter block. The voter block determines whether to deliver an up or a down vote to the local clock phase adjustment unit. The voter block communicates with the local clock phase adjustment unit via up and down control signals. The local clock phase adjustment unit determines whether the local clock phase should be adjusted, and if so, whether to advance or delay the local clock phase. If certain meta-stable conditions are observed by the voter block, the voter block will vote in one direction in order to push the system out of the meta-stable condition.

FIELD OF THE INVENTION

The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of detecting clock phase information embedded in data streams.

BACKGROUND OF THE INVENTION

Many digital electronic systems, including computer systems, include more than a single device. The multiple devices within a system may be coupled to each other by way of interconnects. One type of interconnect may be based on serial data delivery from a transmitting device to a receiving device.

The purpose of an interconnect is to transport data reliably from one point to another. For reliable re-construction of data, the timing reference, i.e. clock edge positions, used by the receiving device should resemble the timing references used at the transmitting device.

One of the most commonly used receiver architectures for high-speed serial data transmission is based on recovering a clock embedded in the received data by tracking the phase of that received data. High data rates mean the receiving devices need to operate within shrinking timing windows and therefore requiring accurate phase tracking.

DETAILED DESCRIPTION

In general, one embodiment of a receiving device within a digital electronic system includes a sampling unit, a voter block, and a local clock phase adjustment unit. The sampling unit samples an input line at three points in time at intervals of one half of a bit period. The sampling unit delivers the values obtained in the sampling process to the voter block. The voter block determines whether to deliver an up or a down vote to the local clock phase adjustment unit, the up and down votes depending on the sample values. The voter block communicates with the local clock phase adjustment unit via up and down control signals. The local clock phase adjustment unit determines whether the local clock phase should be adjusted, and if so, whether to advance or delay the local clock phase.

The clock phase adjustment unit may include a programmable threshold level. The clock phase adjustment unit may store up and down votes communicated by the voter block. When the number of up votes outnumbers the number of down votes by at least the threshold value, then the local clock phase adjuster will delay the local clock phase. Similarly, when the number of down votes outnumbers the number of up votes by at least the threshold value, then the local clock phase adjuster will advance the local clock phase.

In one case, the first and third sample values may be equal and the second sample value may differ from the first and third sample values. This case represents a meta-stable condition and may occur during an initial acquisition period. In order to push the system out of the meta-stable condition, the voter block will deliver an up vote to the local clock phase adjuster. A number of up votes will cause the local clock phase adjuster unit to delay the local clock phase. Another embodiment may have the voter block delivering down votes to the local clock phase adjuster unit in response to the meta-stable condition.

FIG. 1is a block diagram of an example system including a receiving device110and a transmitting device120. The receiving device110and the transmitting device120are coupled by a data line125. The receiving device includes a sampling unit112, a voter block114, and a phase adjustment unit116. The sampling unit112receives input from the data line125via an input signal113. For this example embodiment, the data line125is part of a serial interconnect used to couple together the receiving device110and the transmitting device120. The sampling unit112is coupled to the voter block114via a D0signal, an E0signal, and a D1signal. The voter block114communicates with the phase adjustment unit116using an up signal117and a down signal119. A local clock signal115is provided to the sampling unit by the phase adjustment unit116.

The sampling unit112samples the input line113every one half bit period. Three sample values are delivered to the voter block via the D0, E0, and D1signals. The D0signal represents a first sample value, the E0signal represents a second value sampled one half bit period following the first sample, and the D1signal represents a third value sampled one half bit following the second sample. The voter block114receives the D0, E0, and D1signals and determines whether to deliver an up vote, a down vote, or no vote to the phase adjustment unit116. The voter block114makes determinations on how to vote according to Table 1, below.

The basis for the described algorithm is as follows. If there was a transition of the input line113during a two bit window, then D0will be different from D1. In such a case the value of E0determines if the local clock115used for sampling is either leading or lagging with respect to the observed transition. The situations where D0equals D1but D0and D1are not equal to E0represent meta-stable conditions that may occur during an initialization period. In this example embodiment, the voter block114will deliver “up” votes to the phase adjustment unit116in order to push the system out of the meta-stable condition.

FIG. 2is a timing diagram showing a transition on the input line113where the transition falls within a bit period n+1. Local clock115phases are labeled210,220, and230. The interval between the phase210and the phase220and between220and230is one half bit period.

During bit period n, the input line113is sampled at time210. The sample value D0in this case has a value of “1”. A second sample of the input line113is taken at time220. The sample value E0in this case has a value of “1” because the input line113transition has not yet taken place. During bit period n+1, the input line113is sampled at time230. The input line113is now observed to have transitioned and the sample value D1has a value of “0”. According to Table 1, for the case where D0=1, E0=1, and D1=0, the voter block114will assert the up signal117indicating to the phase adjustment unit116that for the most recent transition the local clock phase lead the data transition edge.

FIG. 3is a timing diagram showing a transition on the input line113where the transition falls within a bit period n. During bit period n, the input line113is sampled at time210. The sample value D0in this case has a value of “1”. A second sample of the input line113is taken at time220. The sample value E0 in this case has a value of “0” because the input line113transition has taken place. During bit period n+1, the input line113is sampled at time230. The input line113is again observed to be at a logically low level and the sample value D1has a value of “0”. According to Table 1, for the case where D0=1, E0=0, and D1=0, the voter block114will assert the down signal119indicating to the phase adjustment unit116that for the most recent transition the local clock phase lagged the data transition edge.

The phase adjustment unit116may include a programmable threshold level. The phase adjustment unit116may track up and down votes communicated by the voter block. When the number of up votes outnumbers the number of down votes by at least the threshold value, then the phase adjustment unit116will delay the local clock115phase. Similarly, when the number of down votes outnumbers the number of up votes by at least the threshold value, then the phase adjustment unit will advance the local clock phase.