Semiconductor device with reduced vertical height

A semiconductor device includes a channel structure arranged on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers arranged on the substrate and surrounding the channel structure, the plurality of insulating layers spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; and a plurality of second gate electrodes surrounding the channel structure. Between adjacent insulating layers from among the plurality of insulating layers are arranged a first gate electrode from among the plurality of first gate electrodes spaced apart along the first direction from a second gate electrode from among the plurality of second gate electrodes.

CROSS-REFERENCE TO RELATED APPLICATION

A claims for priority under 35 U.S.C. § 119 is made to Korean Patent Application No. 10-2019-0075225, filed on Jun. 24, 2019 in the Korean Intellectual Property Office, the entirety of which is incorporated herein by reference.

BACKGROUND

The inventive concepts herein relate to semiconductor devices and manufacturing methods of semiconductor devices, and more particularly to semiconductor devices including a channel structure extending in a vertical direction and manufacturing methods of such semiconductor devices.

As the degree of integration of memory devices increases, memory devices having vertical transistor structure in contrast to generally planar transistor structure have been developed. Memory devices having vertical transistor structure include a channel structure extending in a vertical direction on a substrate. However, as the integration degree of memory devices increases, the number of gate electrode layers stacked in the vertical direction increases, and thus the difficulty of manufacturing processes may increase.

SUMMARY

The inventive concepts provide a semiconductor device including a plurality of pairs of gate electrodes having reduced height in a vertical direction.

The inventive concepts provide a manufacturing method of a semiconductor device to prevent collapsing or falling of a mold stack during processes of forming a plurality of pairs of gate electrodes having reduced height in a vertical direction.

Embodiments of the inventive concepts provide a semiconductor device including a channel structure arranged on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers arranged on the substrate and surrounding the channel structure, the plurality of insulating layers spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; and a plurality of second gate electrodes surrounding the channel structure. Between adjacent insulating layers from among the plurality of insulating layers are arranged a first gate electrode from among the plurality of first gate electrodes spaced apart along the first direction from a second gate electrode from among the plurality of second gate electrodes.

Embodiments of the inventive concepts further provided a semiconductor device including a channel structure arranged on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers arranged on the substrate and surrounding the channel structure, the plurality of insulating layers being apart from each other in the first direction; a plurality of pairs of gate electrodes respectively arranged between adjacent insulating layers from among the plurality of insulating layers, each of the pairs of gate electrodes including a first gate electrode and a second gate electrode spaced apart from each other; and cover insulating layer structures surrounding the channel structure between the first gate electrode and the second gate electrode of each of the plurality of pairs of gate electrodes, the cover insulating layer structures covering edge portions of the plurality of pairs of gate electrodes.

Embodiments of the inventive concepts still further provide a semiconductor device including a channel structure arranged on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers arranged on the substrate and surrounding the channel structure, the plurality of insulating layers spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; and a plurality of second gate electrodes surrounding the channel structure. Between adjacent insulating layers from among the plurality of insulating layers are arranged a first gate electrode from among the plurality of first gate electrodes spaced apart along the first direction from a second gate electrode from among the plurality of second gate electrodes, and an air space between the first gate electrode and the second gate electrode.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the inventive concepts will be described in detail with reference to the accompanying drawings.

FIG.1illustrates an equivalent circuit diagram of a memory cell array MCA of a semiconductor device according to example embodiments of the inventive concepts. More particularly,FIG.1illustrates an equivalent circuit diagram of a vertical NAND (VNAND) flash memory device having a vertical channel structure.

Referring toFIG.1, the memory cell array MCA may include a plurality of memory cell strings MS arranged in a vertical direction (Z direction inFIG.1) on a substrate (not shown). Each of the plurality of memory cell strings MS may include a plurality of memory cells MC1, MC2, . . . , MCn−1, and MCn, at least one string select transistor SST, and a ground select transistor GST, which are connected in series to each other. The plurality of memory cells MC1, MC2, . . . , MCn−1, and MCn may store data, and the plurality of word lines WL1, WL2, WLn−1, and WLn may be respectively connected to memory cells MC1, MC2, . . . , MCn−1, and MCn to control the corresponding memory cells MC1, MC2, MCn−1, and MCn.

A gate terminal of a ground selection transistor GST of the memory cell strings MS may be connected to a ground selection line GSL, and a source terminal of the ground selection transistor GST may be connected to a common source line CSL. Gate terminals of the string selection transistors SST may be connected to string selection lines SSL, a source terminal of the lowermost string selection transistor SST may be connected to a drain terminal of the memory cell MCn, and a drain terminal of the uppermost string selection transistor SST may be connected to a respective one of a plurality of bit lines BL1, BL2, BLm (i.e., BL). AlthoughFIG.1exemplarily illustrates that each memory cell strings MS includes one ground selection transistor GST and two string selection transistors SST, unlike this case, a plurality of for example one or more than three ground selection transistors GST and string selection transistors SST may be formed in each memory cell strings MS. That is, each of the memory cell strings MS may include one or more ground selection transistors GST and one or more string selection transistors SST.

When a signal is applied to the gate terminal of the string selection transistor SST via the string selection line SSL, signals applied via the plurality of bit lines BL may be applied to the plurality of memory cells MC1, MC2, . . . , MCn−1, and MCn to perform a data write operation. When a signal is applied to the gate terminal of the ground selection transistor GST via the ground selection line GSL, an erase operation of the plurality of memory cells MC1, MC2, . . . , MCn−1, and MCn may be performed.

FIG.2illustrates a plan view of a representative configuration of a semiconductor device100, according to example embodiments of the inventive concepts.FIG.3illustrates a cross-sectional view taken along line A1-A1′ inFIG.2, andFIG.4illustrates an enlarged view of a region CX1inFIG.3. InFIG.2, only some components of the semiconductor device100are schematically illustrated for convenience of illustration and understanding.

Referring toFIGS.2through4, a substrate110may include a memory cell region MCR, a connection region CON, and a peripheral circuit region PERI. The memory cell array MCA may be on the memory cell region MCR, and the memory cell array MCA may include a NAND memory device having a vertical channel structure driven in the manner described above with reference toFIG.1. A peripheral circuit transistor190T for driving the memory cell array MCA may be on the peripheral circuit region PERI, and the peripheral circuit transistor190T may include a peripheral circuit active region192, a peripheral circuit gate electrode194on the peripheral circuit active region192, and a peripheral circuit contacts196connected to the peripheral circuit active region192and the peripheral circuit gate electrode194. The connection region CON may be an area in which a pad portion PAD for connecting the memory cell array MCA in the memory cell region MCR to the peripheral circuit transistor190T is formed.

The substrate110may have a main surface110M extending in a first direction (X direction) and a second direction (Y direction). The substrate110may include a semiconductor material such as for example a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium. The substrate110may be provided as a bulk wafer or an epitaxial layer. In other embodiments, the substrate110may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

On the memory cell region MCR of the substrate110, a plurality of insulating layers120may extend in the first direction (X direction) and the second direction (Y direction) parallel with the main surface110M of the substrate110, and may be apart from each other in a third direction (Z direction) perpendicular to the main surface110M of the substrate110.

Each of a plurality of pairs of gate electrodes130may be between two adjacent insulating layers120among the plurality of insulating layers120. Each pair of gate electrodes130may include a first gate electrode130X and a second gate electrode130Y apart from each other in a third direction (Z direction). For example, an insulating layer120may be on the main surface110M of the substrate110, a first gate electrode130X and a second gate electrode130Y (that is, one pair of gate electrodes130) may be on the insulating layer120, and another insulating layer120may be on the second gate electrode130Y. A first top insulating layer122may be on an uppermost pair of gate electrodes130.

The first gate electrode130X may include a first conductive barrier layer132X and a first metal layer134X that are sequentially arranged above a top surface of the insulating layer120disposed below. The second gate electrode130Y may include a second conductive barrier layer132Y and a second metal layer134Y that are sequentially arranged on a bottom surface of the insulating layer120disposed above. For example, the first conductive barrier layer132X and the first metal layer134X may be on the top surface of a lower insulating layer120among the two adjacent insulating layers120, and the second conductive barrier layer132Y and the second metal layer134Y may be on the bottom surface of an upper insulating layer120among the two adjacent insulating layers120. For example, the first metal layer134X may face the second metal layer134Y between two adjacent insulating layers120, the first conductive barrier layer132X may be between the lower insulating layer120among the two adjacent insulating layers120and the first metal layer134X, and the second conductive barrier layer132Y may be between the upper insulating layer120among the two adjacent insulating layers120and the second metal layer134Y.

In example embodiments, the first conductive barrier layer132X and the second conductive barrier layer132Y may for example include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), titanium (Ti), tantalum (Ta), or a combination thereof. The first metal layer134X and the second metal layer134Y may for example include at least one of cobalt (Co), tungsten (W), nickel (Ni), ruthenium (Ru), copper (Cu), aluminum (Al), a silicide thereof, and an alloy thereof.

In example embodiments, the first gate electrode130X may have a first thickness t11of about 1 to about 30 nm in the third direction (Z direction), and the second gate electrode130Y may have a second thickness t12of about 1 to about 30 nm in the third direction (Z direction). However, the first thickness t11and the second thickness t12of the first gate electrode130X and the second gate electrode130Y are not limited thereto, respectively.

In example embodiments, the plurality of pairs of gate electrodes130may correspond to the ground selection line GSL, the word lines WL1, WL2, . . . , WLn−1, and WLn, and the string selection line SSL. For example, the lowermost first gate electrode130X may function as the ground selection line GSL, the uppermost second gate electrode130Y may function as the string selection line SSL, and the remaining first gate electrodes130X and the remaining second gate electrodes130Y may function as the word lines WL1, WL2, . . . , WLn−1, and WLn. In some embodiments, the uppermost first gate electrode130X arranged directly under the uppermost second gate electrode130Y may function as a dummy word line. In other embodiments, the lowermost pair of gate electrodes130(for example, the lowermost first gate electrode130X and the lowermost second gate electrode130Y) may function as the ground selection line GSL, the uppermost pair of gate electrodes130(for example, the uppermost first gate electrode130X and the uppermost second gate electrode130Y) may function as the string selection line SSL, and the remaining pairs of gate electrodes130may function as the word lines WL1, WL2, . . . , WLn−1, and WLn). Accordingly, the memory cell string MS in which the ground selection transistor GST, the string selection transistor SST, and the memory cells MC1, MC2, . . . , MCn−1, and MCn therebetween are connected in series may be provided.

As illustrated inFIG.2, a plurality of word line cut regions WLC may extend in parallel with the main surface110M of the substrate110in the first direction (X direction). The plurality of pairs of gate electrodes130between a pair of word line cut regions WLC may constitute one block, and the pair of word line cut regions WLC may define a width in the second direction (Y direction) of the plurality of pairs of gate electrodes130.

A plurality of channel structures150may extend in the vertical direction (Z direction) passing through the plurality of pairs of gate electrodes130from the main surface110M of the substrate110in the memory cell region MCR. The plurality of channel structures150may be apart from each other at certain intervals in the first direction (X direction), the second direction (Y direction), and a fourth direction (for example, a diagonal direction). The plurality of channel structures150may be in a zigzag shape or staggered shape.

Each of the plurality of channel structures150may be inside a channel hole150H passing through the plurality of pairs of gate electrodes130, the insulating layers120, and the first top insulating layer122. A gate insulating layer152and a channel layer154may be sequentially arranged on an inner wall of the channel hole150H, and a filling insulating layer156filling a remaining space of the channel hole150H may be arranged on the channel layer154. A conductive plug158contacting the channel layer154and blocking an entrance of the channel hole150H may be arranged on a top side of the channel hole150H. In other embodiments, the filling insulating layer156may be omitted, and the channel layer154may be formed in a pillar shape to fill the remaining portion of the channel hole150H.

The gate insulating layer152may have a structure including a tunneling dielectric layer152X, a charge storage layer152Y, and a blocking dielectric layer152Z that are sequentially formed on sidewalls of the channel layer154. In other words, the blocking dielectric layer152Z, the charge storage layer152Y, and the tunneling dielectric layer152X may be sequentially arranged on the inner wall of the channel hole150H. Relative thicknesses of the tunneling dielectric layer152X, the charge storage layer152Y, and the blocking dielectric layer152Z that constitute the gate insulating layer152are not limited to those illustrated inFIG.4and may be variously modified.

The tunneling dielectric layer152X may include for example silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage layer152Y may be an area in which electrons having passed through the tunneling dielectric layer152X from the channel layer154are stored and may include for example silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The blocking dielectric layer152Z may include for example silicon oxide, silicon nitride, or a metal oxide having a higher dielectric constant than silicon oxide. The metal oxide may include for example hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

The first gate electrode130X of each pair of gate electrodes130may be apart from the second gate electrode130Y in the third direction (Z direction) by a cover insulating layer structure140. The cover insulating layer structure140may include a first cover insulating layer142, an air space144, and a second cover insulating layer146. The first cover insulating layer142may surround a sidewall of the channel structure150, and the second cover insulating layer146may cover an edge portion130XE of the first gate electrode130X adjacent to the word line cut region WLC and an edge portion130YE of the second gate electrode130Y adjacent to the word line cut region WLC. The air space144may denote a space limited by the first cover insulating layer142and the second cover insulating layer146between the first gate electrode130X and the second gate electrode130Y.

For example, when the first cover insulating layer142is formed by using an insulating material having a poor step coverage, and then the second cover insulating layer146is formed by using an insulating material having a poor step coverage, a portion of the space between the first gate electrode130X and the second gate electrode130Y may remain unfilled by the first cover insulating layer142or the second cover insulating layer146, and the remaining unfilled space may be referred to as the air space144.

The first cover insulating layer142may surround a sidewall of the channel structure150, and the first cover insulating layer142may contact a sidewall of the gate insulating layer152. As illustrated inFIG.4, the first cover insulating layer142may include a recess142R, and a first protrusion152ZP may be formed in a portion of the sidewall of the gate insulating layer152facing the recess142R (for example, on a portion of the sidewall of the blocking dielectric layer152Z). However, a shape and size of the recess142R or a shape and size of the first protrusion152ZP are not limited to those illustrated inFIG.4.

In some embodiments, at least one of the plurality of first cover insulating layers142at different vertical levels may not include the recess142R, and in this case, a portion of the gate insulating layer152contacting the first cover insulating layer142may have sidewalls extending substantially vertically. In some embodiments, at least one recess142R of the plurality of first cover insulating layers142at different vertical levels may have greater depth than the recesses142R of the remaining first cover insulating layers142. The first protrusion152ZP contacting the at least one recess142R may further outwardly protrude with respect to the first protrusions152ZP contacting the remaining recesses142R.

As exemplarily illustrated inFIG.4, the second cover insulating layer146may cover the edge portion130XE of the first gate electrode130X and the edge portion130YE of the second gate electrode130Y, and in addition, may cover a sidewall120S of the insulating layer120adjacent to the word line cut region WLC. With respect to the sidewall120S of the insulating layer120adjacent to the word line cut region WLC, the edge portion130XE of the first gate electrode130X may be inwardly recessed (for example, toward the channel structure150). For example, a sidewall of the first conductive barrier layer132X may be inwardly recessed with respect to the sidewall120S of the insulating layer120, and a sidewall of the first metal layer134X may be inwardly recessed with respect to the sidewall120S of the insulating layer120or the sidewall of the first conductive barrier layer132X. As exemplarily illustrated inFIG.4, the second cover insulating layer146may include a sidewall profile of a curved surface conforming to the sidewall120S of the insulating layer120, the sidewall of the first gate electrode130X, and the sidewall of the second gate electrode130Y. In other embodiments, unlike illustrated inFIG.4, the second cover insulating layer146may have a planar sidewall profile substantially extending in the vertical direction.

A separation distance d11between the first gate electrode130X and the second gate electrode130Y may be about 1 to about 30 nm, but is not limited thereto. As the first gate electrode130X and the second gate electrode130Y are arranged apart from each other in a space between two adjacent insulating layers120, the first gate electrode130X may have a relatively small first thickness t11in the third direction (Z direction), the second gate electrode130Y may have a relatively small second thickness t12in the third direction (Z direction), and the separation distance d11between the first gate electrode130X and the second gate electrode130Y may also be relatively small.

On the substrate110, a plurality of common source lines180vertically overlapping the plurality of word line cut regions WLC may be arranged in the first direction (X direction). Insulating spacers182may be on both sidewalls of the plurality of common source lines180. For example, the second cover insulating layer146and the insulating spacer182may be between the plurality of pairs of gate electrodes130and the common source line180. The plurality of common source lines180are illustrated as having a bottom surface at the same level as the main surface110M of the substrate110inFIG.3, but in other embodiments the plurality of common source lines180may extend to a level lower than the main surface110M of the substrate110.

A plurality of common source regions112may be in the substrate110under the common source line180and may extend in the first direction (X direction). The plurality of common source regions112may be impurity regions including n-type impurities heavily doped thereon. The plurality of common source regions112may function as a source region for supplying current to the plurality of memory cells MC1, MC2, . . . , MCn−1, and MCn. The plurality of common source regions112may be at positions where the plurality of common source regions112overlap the plurality of word line cut regions WLC.

A second top insulating layer124may be on the first top insulating layer122, and the bit line BL may extend in the second direction (Y direction) on the second top insulating layer124. A bit line contact BLC may be between the bit line BL and the conductive plug158, and the second top insulating layer124may surround the bit line contact BLC.

As illustrated inFIG.2, in one block, an uppermost pair of gate electrodes130may be separated into two portions by a string separation insulating layer174, in a plan view. Although not illustrated, the string separation insulating layer174may extend from the same level as the top surface of the first top insulating layer122to a level lower than a bottom surface of the uppermost pair of gate electrodes130.

In the connection region CON, the plurality of pairs of gate electrodes130may extend to form the pad portion PAD. The plurality of pairs of gate electrodes130may extend to have a shorter length in the first direction (X direction) as a vertical distance of the plurality of pairs of gate electrodes130from the main surface110M of the substrate110increases. The pad portion PAD may refer to portions of the plurality of pairs of gate electrodes130that are configured in a step shape. The second top insulating layer124may be above the plurality of pairs of gate electrodes130constituting the pad portion PAD, and a pad contact172, which passes through the second top insulating layer124and is connected to the plurality of pairs of gate electrodes130, may be arranged in the connection region CON.

As illustrated inFIG.2, a plurality of dummy channel structures D150may pass through the plurality of pairs of gate electrodes130from the main surface110M of the substrate110and extend in the third direction (Z direction) in the connection region CON. The dummy channel structure D150may be formed to secure structural stability of the semiconductor device100in the fabrication process of the semiconductor device100. Each of the plurality of dummy channel structures D150may have the same structure as the channel structure150. The plurality of dummy channel structures D150may have a greater width than the channel structures150, but is not limited thereto.

In general, as the degree of integration of semiconductor devices increases, a vertical height of semiconductor devices may increase, and due to a relatively large vertical height of a mold stack of the semiconductor devices, defects such as collapsing or falling of the mold stack may occur during a process of removing a sacrificial layer for forming a gate electrode.

However, according to the semiconductor device100of embodiments of the inventive concepts, as an example, in a gate space GS (refer toFIG.15) from which one sacrificial layer310(refer toFIG.14) has been removed, that is, in the space between two adjacent insulating layers120, a pair of gate electrodes130including the first gate electrode130X and the second gate electrode130Y apart from each other may be formed. Accordingly, the first gate electrode130X and the second gate electrode130Y may have relatively small thicknesses t11and t12, respectively, and the separation distance d11between the first gate electrode130X and the second gate electrode130Y may be relatively small. Thus, the vertical height of the semiconductor device100may be relatively reduced, and the occurrence of defects due to collapsing or falling of mold stacks during the fabrication process of the semiconductor device100may be reduced or prevented.

FIG.5illustrates a cross-sectional view of a semiconductor device100A according to example embodiments of the inventive concepts, andFIG.6illustrates an enlarged cross-sectional view of a region CX1inFIG.5. InFIGS.5and6, similar reference numbers to those inFIGS.1through4may denote similar components, and description of features inFIGS.5and6that are similar to features inFIGS.1through4may be omitted from the following for brevity.

Referring toFIGS.5and6, the semiconductor device100A may include a plurality of pairs of gate electrodes130A, and the plurality of pairs of gate electrodes130A may include a recess region130R formed on sidewalls facing the channel structure150. In addition, the first cover insulating layer142may include the recess142R, and a gate insulating layer152A may include the first protrusion152ZP on a sidewall portion that contacts the recess142R of the first cover insulating layer142and a second protrusion152YP on a sidewall portion that contacts the recess region130R of the plurality of pairs of gate electrodes130A. The second protrusion152YP may protrude more outwardly (for example, in a direction toward the word line cut region WLC) than the first protrusion152ZP.

In example embodiments, as the gate electrode130A includes the recess region130R, a distance between the gate electrode130A and the channel layer154may be greater than a distance between the gate electrode130and the channel layer154of the semiconductor device100described with reference toFIGS.2through4.

The gate insulating layer152A may include a tunneling dielectric layer152XA, a charge storage layer152YA, and a blocking dielectric layer152ZA, and the charge storage layer152YA and the blocking dielectric layer152ZA may be arranged in the second protrusion152YP. As the charge storage layer152YA is arranged in the second protrusion152YP, a separation distance from the channel layer154to the charge storage layer152YA may be relatively large, and accordingly, a charge transfer path from the channel layer154to the charge storage layer152YA may be relatively long. Thus, data loss due to a phenomenon that the charge stored in the charge storage layer152YA of one memory cell is spread to a portion of the charge storage layer152YA of an adjacent memory cell (that is, in the same direction as the extension direction of the channel layer154) may be prevented.

In the fabrication process according to the example embodiments, the recess region130R may be formed by removing a portion of a preliminary conductive barrier layer132L (refer toFIG.27) and a portion of a preliminary metal layer134L (refer toFIG.27) which are exposed at an inner wall of the channel hole150HA in a lateral direction (a horizontal direction). Next, the gate insulating layer152A may be formed on the inner wall of the channel hole150HA, and then, the second protrusion152YP of the gate insulating layer152A may be formed in the recess region130R.

According to the semiconductor device100A of embodiments of the inventive concepts, as an example, in the gate space GS (refer toFIG.15) from which one sacrificial layer310(refer toFIG.14) has been removed, that is, in the space between two adjacent insulating layers120, a pair of gate electrodes130including the first gate electrode130X and the second gate electrode130Y apart from each other may be formed. Thus, the vertical height of the semiconductor device100A may be relatively reduced, and an occurrence of defects due to collapsing or falling of the mold stack during the fabrication process of the semiconductor device100A may be reduced or prevented. In addition, since the gate insulating layer152A includes the second protrusion152YP, data loss may be prevented, and reliability of the semiconductor device100A may be improved.

FIG.7illustrates a cross-sectional view of a semiconductor device100B according to example embodiments of the inventive concepts. InFIG.7, the same reference numerals as those inFIGS.1through6may denote the same components, and description of features inFIG.7that are similar to features inFIGS.1through6may be omitted from the following for brevity.

Referring toFIG.7, a cover insulating layer structure140B may be between the first gate electrode130X and the second gate electrode130Y, and the cover insulating layer structure140B may include a cover insulating layer142B substantially filling the entire space between the first gate electrode130X and the second gate electrode130Y. A top surface of the cover insulating layer142B may contact a bottom surface of the second metal layer134Y, and a bottom surface of the cover insulating layer142B may contact a top surface of the first metal layer134X. A sidewall142BS of the cover insulating layer142B adjacent to the word line cut region WLC may be aligned with sidewalls of the first metal layer134X and the second metal layer134Y, as illustrated inFIG.7. In other embodiments, the sidewall142BS of the cover insulating layer142B adjacent the word line cut region WLC may be inwardly recessed (for example, in a direction toward the channel structure150) with respect to the sidewalls of the first metal layer134X and the second metal layer134Y. In other embodiments, the sidewall142BS of the cover insulating layer142B adjacent to the word line cut region WLC may outwardly protrude (for example, in a direction toward the common source line180) with respect to the sidewalls of the first metal layer134X and the second metal layer134Y.

In example embodiments, the cover insulating layer142B may include a low-k insulation material. For example, the low-k insulation material may include fluorosilicate glass (FSG), carbon doped silicon oxide (SIOC), a spin-on dielectric (SOD) material, or an ultra-low-k (ULK) material. For example, the cover insulating layer142B may be formed by an atomic layer deposition process or a chemical vapor deposition process using the low-k insulation material. In other embodiments, the cover insulating layer142B may include for example silicon oxide, silicon oxynitride, silicon nitride, etc.

In a process according to the example embodiments, the sacrificial layer310(refer toFIG.14) may be removed through the channel hole150H, the preliminary conductive barrier layer132L (refer toFIG.16) and the preliminary metal layer134L (refer toFIG.16) may be conformally formed on an inner wall of the gate space GS (refer toFIG.15) in which the sacrificial layer310has been removed, and the cover insulating layer142B may be formed to entirely fill the remaining inside of the gate space GS. In this case, the semiconductor device100B described with reference toFIG.7may be formed.

According to the semiconductor device100B of embodiments of the inventive concepts, as an example, in the gate space GS in which sacrificial layer310has been removed, that is, in a space between two adjacent insulating layers120, a pair of gate electrodes130including the first gate electrode130X and the second gate electrode130Y apart from each other may be formed. Thus, the vertical height of the semiconductor device100B may be relatively reduced, and the occurrence of defects due to collapsing or falling of the mold stack during the fabrication process of the semiconductor device100B may be reduced or prevented.

FIG.8illustrates a cross-sectional view of a semiconductor device100C according to example embodiments of the inventive concepts. InFIG.8, the same reference numerals as those inFIGS.1through7may denote the same components, and description of features inFIG.7that are similar to features inFIGS.1through7may be omitted from the following for brevity.

Referring toFIG.8, a first gate electrode130XC may include a first metal layer134XC, and a second gate electrode130YC may include a second metal layer134YC. In other words, in the semiconductor device100C, the first conductive barrier layer132X and the second conductive barrier layer132Y included in the semiconductor device100described with reference toFIGS.2through4may be omitted. A top surface of the first metal layer134XC may contact the cover insulating layer structure140, and a bottom surface of the first metal layer134XC may contact the top surface of an insulating layer120below it. In addition, a top surface of the second metal layer134YC may contact the bottom surface of the insulating layer120above it, and a bottom surface of the second metal layer134YC may contact the cover insulating layer structure140.

In example embodiments, the first metal layer134XC and the second metal layer134YC may include any one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), titanium (Ti), tantalum (Ta), cobalt (Co), tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), a silicide thereof, and an alloy thereof.

In a process according to example embodiments, the sacrificial layer310(refer toFIG.14) may be removed through the channel hole150H (refer toFIG.14), and the preliminary metal layer134L (refer toFIG.16) may be conformally formed on the inner wall of the gate space GS in which the sacrificial layer310has been removed. In this case, the semiconductor device100C described with reference toFIG.8may be formed.

According to the semiconductor device100C of embodiments of the inventive concepts, as an example, in the gate space GS in which one sacrificial layer310has been removed, that is, in a space between two adjacent insulating layers120, a pair of gate electrodes130C including the first gate electrode130XC and the second gate electrode130YC apart from each other may be formed. Thus, the vertical height of the semiconductor device100C may be relatively reduced, and the occurrence of defects due to collapsing or falling of the mold stack during the fabrication process of the semiconductor device100C may be reduced or prevented.

FIG.9illustrates a cross-sectional view of a semiconductor device100D according to example embodiments. InFIG.9, the same reference numerals as those inFIGS.1through8may denote the same components, and description of features inFIG.9that are similar to features inFIGS.1through8may be omitted from the following for brevity.

Referring toFIG.9, a bottom gate electrode130D may be between two lowermost insulating layers120. The bottom gate electrode130D may substantially fill an entire space between the lowermost two insulating layers120, and the bottom gate electrode130D may have a thickness greater than that of each of the first gate electrode130X and the second gate electrode130Y included in the pair of gate electrodes130.

A channel structure150D may include a first gate insulating layer152D1on a sidewall of the channel hole150H, a first channel layer154D1on the sidewall of the channel hole150H, a second channel layer154D2at a bottom portion of the channel hole150H, a second gate insulating layer152D2between a sidewall of the second channel layer154D2and the bottom gate electrode130D, the filling insulating layer156, and the conductive plug158. A top surface of the second channel layer154D2may be at a level higher than a top surface of the bottom gate electrode130D. The second channel layer154D2may include a semiconductor layer formed by using a selective epitaxial growth process from the main surface110M of the substrate110exposed at the bottom portion of the channel hole150H. The second gate insulating layer152D2may include silicon oxide formed by a thermal oxidation process, but is not limited thereto. The first gate insulating layer152D1and the first channel layer154D1may be similar to the gate insulating layer152and the channel layer154described with reference toFIGS.2through4, respectively.

FIG.10illustrates a cross-sectional view of a semiconductor device100E according to example embodiments of the inventive concepts. InFIG.10, the same reference numerals as those inFIGS.1through9may denote the same components, and description of features inFIG.10that are similar to features inFIGS.1through9may be omitted from the following for brevity.

Referring toFIG.10, the semiconductor device100E may further include a first semiconductor layer162and a second semiconductor layer164sequentially arranged on the main surface110M of the substrate110, and the plurality of insulating layers120and the plurality of pairs of gate electrodes130may be alternately arranged on the second semiconductor layer164. The first semiconductor layer162may include polysilicon doped with impurities or polysilicon undoped with impurities, and the second semiconductor layer164may also include polysilicon doped with impurities or polysilicon undoped with impurities. The first semiconductor layer162may function as a common source line extension region and may be a portion corresponding to the common source line CSL inFIG.1. The second semiconductor layer164may function as a support layer to prevent a mold stack from collapsing or falling in the process of removing a sacrificial layer for forming the first semiconductor layer162.

The channel structure150E may pass through the first semiconductor layer162and the second semiconductor layer164and extend to a level lower than the main surface110M of the substrate110. A portion in which a gate insulation layer152E is separated may be formed at a bottom of the channel structure150E, and in the portion in which the gate insulation layer152E is separated, a sidewall154W of a channel layer154E may be surrounded by the first semiconductor layer162. In addition, a bottom surface of the channel layer154E may be surrounded by the gate insulating layer152E and may not contact the substrate110, but the inventive concepts are not limited thereto.

FIG.11illustrates a cross-sectional view of a semiconductor device200according to example embodiments of the inventive concepts. InFIG.11, the same reference numerals as those inFIGS.1through10may denote the same components, and description of features inFIG.11that are similar to features inFIGS.1through10may be omitted from the following for brevity.

Referring toFIG.11, a bottom substrate210may be at a lower vertical level than the substrate110, and in the bottom substrate110an active region (not shown) may be defined by an isolation layer222in the bottom substrate210, and on the active region a plurality of driving transistors230T may be formed. The plurality of driving transistors230T may include a driving circuit gate structure232and an impurity region212in a portion of the bottom substrate210on both sides of the driving circuit gate structure232.

Over the bottom substrate210, a plurality of wiring layers242, a plurality of contact plugs246connecting each of the plurality of wiring layers242or connecting between the plurality of wiring layers242and the driving transistor230T, and a bottom interlayer insulating layer250covering the plurality of wiring layers242and the plurality of contact plugs246may be arranged.

The substrate110may be on the bottom interlayer insulating layer250. On the substrate110, the plurality of insulating layers120, the plurality of pairs of gate electrodes130, the cover insulating layer structure140, and the channel structure150may be arranged.

FIGS.12through26illustrate schematic diagrams of a fabrication method of the semiconductor device100according to a process sequence, according to example embodiments of the inventive concepts.FIGS.12through26are cross-sectional views corresponding to cross-sections along the line A1-A1′ inFIG.2. InFIGS.12through26, the same reference numerals as those inFIGS.1through11may denote the same components.

Referring toFIG.12, the plurality of insulating layers120and a plurality of sacrificial layers310may be alternately formed on the main surface110M of the substrate110. In example embodiments, the plurality of insulating layers120may include an insulating material such as silicon oxide or silicon oxynitride, and the plurality of sacrificial layers310may include for example silicon nitride, silicon oxynitride, or polysilicon doped with impurities, etc.

Next, although not illustrated, the pad portion PAD (refer toFIG.2) may be formed by sequentially patterning the plurality of insulating layers120and the plurality of sacrificial layers310in the connection region CON. In example embodiments, the pad portion PAD may be formed to have a step shape having a difference in top surface levels in the first direction (X direction) as described previously.

Next, the first top insulating layer122covering the uppermost sacrificial layer310and the pad portion PAD may be formed. The first top insulating layer122may include an insulating material such as silicon oxide and silicon oxynitride.

Referring toFIG.13, a mask pattern (not illustrated) may be formed on the first top insulating layer122, and a word line cut opening320H may be formed by etching the first top insulating layer122, the plurality of insulating layers120, and a portion of the plurality of sacrificial layers310by using the mask pattern as an etching mask. Next, a word line cut insulating layer320may be formed by using an insulating material inside the word line cut opening320H.

Referring toFIG.14, the channel hole150H may be formed by etching portions of the first top insulating layer122, the plurality of insulating layers120, and the plurality of sacrificial layers310. The channel hole150H may extend to a level lower than the main surface110M of the substrate110.

Referring toFIG.15, by removing the plurality of sacrificial layers310exposed at the sidewall of the channel hole150H, the plurality of gate spaces GS may be formed at positions where the plurality of sacrificial layers310have been removed. Sidewalls of the word line cut insulating layers320may be exposed in the plurality of gate spaces GS. In example embodiments, a removing process of the plurality of sacrificial layers310may be a wet etching process using a phosphoric acid solution as an etchant.

Referring toFIG.16, the preliminary conductive barrier layer132L and a preliminary metal layer134L may be sequentially formed on the inner walls of the channel holes150H and the plurality of gate spaces GS. The preliminary conductive barrier layer132L and the preliminary metal layer134L may be conformally formed on the surfaces of the insulating layers120exposed at the inner walls of the channel hole150H and the plurality of gate spaces GS, on sidewalls of the word line cut insulating layers320exposed in the plurality of gate spaces GS and on the first top insulating layer122. The inside of the channel hole150H and the plurality of gate spaces GS are not entirely filled.

Referring toFIG.17, a preliminary first cover insulating layer142L may be formed on the preliminary metal layer134L arranged on the inner wall of the channel hole150H. The preliminary first cover insulating layer142L may include an insulating material having poor step coverage characteristics and may fill a portion of the plurality of gate spaces GS communicated with the channel hole150H. Accordingly, a portion of the plurality of gate spaces GS that are relatively far from the channel hole150H may not be filled by the preliminary first cover insulating layer142L, but may remain empty.

Referring toFIG.18, a portion of the preliminary first cover insulating layer142L arranged on (or over) the first top insulating layer122and on the inner wall of the channel hole150H may be removed, and the plurality of first cover insulating layers142may be formed in the plurality of gate spaces GS. Accordingly, the preliminary metal layer134L may be exposed again on the sidewall and the bottom portion of the channel hole150H. In example embodiments, a process for removing a portion of the preliminary first cover insulating layer142L may be a wet etching process. In some embodiments, after the wet etching process, the plurality of first cover insulating layers142may include the recess142R, which is inwardly recessed with respect to the preliminary metal layer134L on the sidewall of the channel hole150H.

Referring toFIG.19, portions of the preliminary metal layer134L and the preliminary conductive barrier layer132L on the inner wall of the channel hole150H may be removed, and accordingly, the plurality of insulating layers120may be exposed at the inner wall of the channel hole150H.

In example embodiments, by performing a first wet etching process using a first etchant capable of removing the preliminary metal layer134L, a portion of the preliminary metal layer134L on the inner wall of the channel hole150H may be first removed to expose the surface of the preliminary conductive barrier layer132L. Next, by performing a second wet etching process using a second etchant capable of removing the preliminary conductive barrier layer132L, a portion of the preliminary conductive barrier layer132L on the inner wall of the channel hole150H may be removed. However, the removal process of the portion of the preliminary conductive barrier layer132L and the portion of the preliminary metal layer134L is not limited to the above-described etching processes.

For example, a portion of the preliminary conductive barrier layer132L and a portion of the preliminary metal layer134L that cover the sidewall120S of the insulating layer120on the inner wall of the channel hole150H may be removed by a wet etching process, and the sidewall120S of the insulating layer120may be exposed. In addition, a portion of the preliminary conductive barrier layer132L and a portion of the preliminary metal layer134L on the first top insulating layer122may be removed together, and a top surface of the first top insulating layer122may be exposed again.

Referring toFIG.20, the blocking dielectric layer152Z, the charge storage layer152Y, and the tunneling dielectric layer152X may be sequentially formed on the inner wall of the channel hole150H to form the gate insulating layer152. The gate insulating layer152may contact the sidewall of the first cover insulating layer142on the inner wall of the channel hole150H, and for example, the first protrusion152ZP conforming to a shape of the recess142R may be formed in the portion of the gate insulating layer152contacting the recess142R of the first cover insulating layer142. However, the shape or size of the recess142R and the first protrusion152ZP are not limited to those illustrated inFIG.20.

Referring toFIG.21, by performing an anisotropic etching process or an etch-back process on the gate insulating layer152, a portion of the gate insulating layer152covering the bottom portion of the channel hole150H may be removed. By the anisotropic etching process or the etch-back process, a portion of the substrate110exposed at the bottom portion of the channel hole150H may be further removed to a certain depth.

Next, the channel layer154may be conformally formed on the inner wall of the channel hole150H. The filling insulating layer156filling a remaining portion of the channel hole150H may be formed by using an insulating material on the channel layer154. By removing a portion of the channel layer154and a portion of the filling insulating layer156(and a portion of the gate insulating layer152) which are arranged in the top portion of the channel hole150H by an etch-back process, and by filling the removed portions of the top portion of the channel hole150H with a conductive material, the conductive plug158may be formed.

Referring toFIG.22, a mask pattern (not shown) may be formed on the first top insulating layer122and the word line cut insulating layer320(refer toFIG.21), and a portion of the word line cut insulating layer320may be removed by using the mask pattern as an etching mask, to form a word line cut opening320HA. Next, by performing a wet etching process, the remaining portion of the word line cut insulating layer320, the first top insulating layer122, and the plurality of insulating layers120may be further removed by a certain thickness. The word line cut opening320HA may further laterally extend by the wet etching process, and the sidewall120S of the insulating layer120may be inwardly recessed with respect to a sidewall of the preliminary conductive barrier layer132L (for example, in a direction toward the channel structure150).

Referring toFIG.23, portions of the preliminary metal layer134L and the preliminary conductive barrier layer132L on the inner wall of the word line cut opening320HA may be removed, and accordingly, the plurality of gate spaces GS may communicate with and be exposed at the word line cut opening320HA.

In example embodiments, by performing the first wet etching process using a first etchant capable of removing the preliminary conductive barrier layer132L, a portion of the preliminary conductive barrier layer132L on the inner wall of the word line cut opening320HA may be first removed to expose the surface of the preliminary metal layer134L. Next, by performing a second wet etching process using a second etchant capable of removing the preliminary metal layer134L, a portion of the preliminary metal layer134L on the inner wall of the word line cut opening320HA may be removed. As a result, a portion of the preliminary conductive barrier layer132L and a portion of the preliminary metal layer134L that surround the gate space GS on the inner wall of the word line cut opening320HA may be removed, and accordingly, the gate space GS may communicate with or be connected to the word line cut opening320HA. However, the removal process of the portion of the preliminary conductive barrier layer132L and the portion of the preliminary metal layer134L is not limited to the above-described etching processes.

For example, a portion of the preliminary metal layer134L and a portion of the preliminary conductive barrier layer132L, which extend in the vertical direction (Z direction) and are arranged on the side wall of the word line cut insulating layer320(refer toFIG.21), from among the preliminary metal layer134L and the preliminary conductive barrier layer132L, may be removed, and accordingly, only a portion of the preliminary metal layer134L and a portion of the preliminary conductive barrier layer132L that are arranged on the top surface and the bottom surface of the insulating layer120may remain. The preliminary metal layer134L may be at a level lower than the preliminary conductive barrier layer132L at an upper portion of one gate space GS, and the preliminary metal layer134L may be at a level higher than the preliminary conductive barrier layer132L at a lower portion of one gate space GS.

For example, a portion of the preliminary conductive barrier layer132L on the top surface of the lower insulating layer120among the two adjacent insulating layers120may be referred to as the first conductive barrier layer132X, a portion of the preliminary metal layer134L on the first conductive barrier layer132X over the top surface of the lower insulating layer120may be referred to as the first metal layer134X, a portion of the preliminary conductive barrier layer132L on the bottom surface of the top insulating layer120among two adjacent insulating layers120may be referred to as the second conductive barrier layer132Y, and a portion of the preliminary metal layer134L on the second conductive barrier layer132Y under the bottom surface of the top insulating layer120may be referred to as the second metal layer134Y. Here, in one gate space GS between two adjacent insulating layers120, the first gate electrode130X including the first conductive barrier layer132X and the first metal layer134X, and the second gate electrode130Y including the second conductive barrier layer132Y and the second metal layer134Y may be formed. Accordingly, the first gate electrode130X and the second gate electrode130Y may have a mirrored-symmetric shape with respect to each other based on the center line in the vertical direction (Z direction) of the gate space GS. The first gate electrode130X and the second gate electrode130Y may be apart from each other in the vertical direction (Z direction) in the memory cell region MCR.

Referring toFIG.24, the second cover insulating layer146may be formed on the top surface of the first top insulating layer122and on an inner wall of the word line cut opening320HA. The second cover insulating layer146may be formed by using an insulating material having poor step coverage characteristics, and the second cover insulating layer146may fill a portion of the plurality of gate spaces GS communicated or connected with the word line cut opening320HA. Some region of the plurality of gate spaces GS located relatively far from the word line cut opening320HA may remain empty without being filled by the second cover insulating layer146, and the empty region may be referred to as the air space144. The air space144may denote a space that is defined between the first gate electrode130X and the second gate electrode130Y in the vertical direction (Z direction), and between the first cover insulating layer142and the second cover insulating layer146in the horizontal direction (X direction or Y direction). The shape and size of the air space144are not limited to those illustrated inFIG.24. Here, the first cover insulating layer142, the air space144, and the second cover insulating layer146may be referred to as the cover insulating layer structure140.

Referring toFIG.25, the insulating spacer182may be formed on the inner wall of the word line cut opening320HA. In example embodiments, the insulating spacer182may be formed to entirely fill the word line cut opening320HA on the second cover insulating layer146. In other embodiments, unlike as illustrated inFIG.25, the insulating spacer182may be formed to have a relatively small thickness on the second cover insulating layer146, and a portion of the word line cut opening320HA may not be filled by the insulating spacer182.

Referring toFIG.26, a mask pattern (not illustrated) may be formed on the insulating spacer182, and a portion of the insulating spacer182may be removed by using the mask pattern as an etching mask to expose the main surface110M of the substrate110. The common source region112may be formed in a portion of the substrate110under the insulating spacer182by implanting impurities into the exposed substrate110. Next, the common source line180may be formed by using a conductive material in a portion where the insulating spacer182has been removed.

Referring toFIG.3again, the second top insulating layer124may be formed on the first top insulating layer122, and the bit line contact BLC that passes through the second top insulating layer124and electrically contacts the channel structure150via the conductive plug1598may be further formed. Next, the bit line BL that is connected to the bit line contact BLC and extends in the second direction (Y direction) may be further formed on the second top insulating layer124.

The semiconductor device100may be completed by performing the above-described processes.

According to the fabrication method of the semiconductor device100described above, the sacrificial layer310exposed by the channel hole150H may be removed, then the preliminary conductive barrier layer132L and the preliminary metal layer134L may be formed in the gate space GS from which the sacrificial layer310has been removed, portions of the preliminary conductive barrier layer132L and the preliminary metal layer134L (that is, portions extending in the vertical direction of the preliminary conductive barrier layer132L and the preliminary metal layer134L) may be removed by using the channel hole150H, and thereafter, other portions of the preliminary conductive barrier layer132L and the preliminary metal layer134L (that is, portions extending in the vertical direction of the preliminary conductive barrier layer132L and the preliminary metal layer134L) may be removed by using the word line cut opening320HA. Accordingly, in a gate space GS where one sacrificial layer310has been removed, that is, in a space between two adjacent insulating layers120, the pair of gate electrodes130including the first gate electrode130X and the second gate electrode130Y apart from each other may be formed.

Accordingly, the first gate electrode130X and the second gate electrode130Y may have relatively small thicknesses t11and t12(refer toFIG.4), respectively, and the separation distance d11(refer toFIG.4) between the first gate electrode130X and the second gate electrode130Y may be relatively small. Thus, the vertical height of the semiconductor device100may be relatively reduced, and the occurrence of defects due to collapsing or falling of the mold stack during the fabrication process of the semiconductor device100, for example, during the removal process of the sacrificial layer310, may be reduced or prevented.

FIGS.27and28illustrate schematic diagrams of a fabrication method of the semiconductor device100A according to a process sequence, according to example embodiments of the inventive concepts.

First, the plurality of first cover insulating layers142may be formed in the plurality of gate spaces GS by performing the processes described with reference toFIGS.12through19, and the plurality of insulating layers120may be exposed at the inner wall of the channel hole150HA.

Referring toFIG.27, by performing a wet etching process, the preliminary conductive barrier layer132L and the preliminary metal layer134L exposed at the inner wall of the channel hole150HA may be further etched in a lateral direction. Accordingly, the sidewalls of the preliminary conductive barrier layer132L and the preliminary metal layer134L may be inwardly recessed with respect to the sidewalls120S of the plurality of insulating layers120(for example, in a direction toward the word line cut insulating layer320), and the recess region130R may be formed in a space where the preliminary conductive barrier layer132L and the preliminary metal layer134L have been removed. In addition, the sidewalls of the preliminary conductive barrier layer132L and the preliminary metal layer134L may be inwardly recessed (for example, in a direction toward the word line cut insulation layer320) with respect to the sidewall of the first cover insulating layer142.

In example embodiments, by performing a first wet etching process using a first etchant capable of removing the preliminary metal layer134L, a portion of the preliminary metal layer134L on the inner wall of the channel hole150HA may be first etched in a lateral direction, and then, by performing a second wet etching process using a second etchant capable of removing the preliminary conductive barrier layer132L, a portion of the preliminary conductive barrier layer132L on the inner wall of the channel hole150HA may be removed in a lateral direction. However, the etching process in the lateral direction of the preliminary conductive barrier layer132L and the preliminary metal layer134L is not limited to the above-described example.

Referring toFIG.28, the blocking dielectric layer152ZA, the charge storage layer152YA, and the tunneling dielectric layer152XA may be sequentially formed on the inner wall of the channel hole150HA to form the gate insulating layer152A. The gate insulating layer152A may contact the sidewall of the first cover insulating layer142on the inner wall of the channel hole150H, and for example, the first protrusion152ZP conforming to the shape of the recess142R may be formed in the portion of the gate insulating layer152A contacting the recess142R of the first cover insulating layer142. In addition, the gate insulating layer152A may contact the sidewalls of the preliminary conductive barrier layer132L and the preliminary metal layer134L on the inner wall of the channel hole150HA, and for example, the second protrusion152YP conforming to the shape of the recess region130R may be formed in a portion of the gate insulating layer152that contacts the recess region130R of the preliminary conductive barrier layer132L and the preliminary metal layer134L. However, the shapes or sizes of the first protrusion152ZP and the second protrusion152YP are not limited to those illustrated inFIG.28.

Thereafter, the semiconductor device100A may be completed by performing the processes described with reference toFIGS.21through26.

According to the fabrication method of the semiconductor device100A according to the example embodiments described above, the occurrence of defects due to collapsing or falling of the mold stack in the fabrication process of the semiconductor device100A may be reduced or prevented. In addition, since the gate insulating layer152A includes the second protrusion152YP, data loss may be prevented, and reliability of the semiconductor device100A may be improved.

While the inventive concepts have been particularly shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.