Nonvolatile memory devices and methods of fabricating the same

A nonvolatile memory device includes a plurality of first control gate electrodes, second control gate electrodes, first storage node films, and second storage node films. The first control gate electrodes are recessed into a semiconductor substrate. Each second control gate electrode is disposed between two adjacent first control gate electrodes. The second control gate electrodes are disposed on the semiconductor substrate over the first control gate electrodes. The first storage node films are disposed between the semiconductor substrate and the first control gate electrodes. The second storage node films are disposed between the semiconductor substrate and the second control gate electrodes. A method of fabricating the nonvolatile memory device includes forming the first storage node films, forming the first control gate electrodes, forming the second storage node films, and forming the second control gate electrodes.

PRIORITY STATEMENT

This application claims priority from Korean Patent Application No. 10-2006-0071570, filed on Jul. 28, 2006, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.

BACKGROUND

Example embodiments relate to semiconductor memory devices and methods of fabricating the semiconductor memory devices. Also, example embodiments relate to semiconductor memory devices including recess-type gate electrodes and methods of fabricating the semiconductor memory devices including recess-type gate electrodes.

2. Description of Related Art

With recent development in increasing a speed and miniaturization of semiconductor products, such semiconductor products require more high-integrated and high-speed semiconductor memory devices. Accordingly, instead of related art planar structures, memory devices having three-dimensional structures are being introduced. For example, a semiconductor memory device with a three-dimensional structure has a recess-type control gate electrode extended into a semiconductor substrate.

Such a nonvolatile memory device with a three-dimensional structure has a wide channel region and accordingly has a high operating speed, compared to the related art planar structures. However, the increase in integration of a semiconductor memory with a three-dimensional structure has a limitation. This is because impurity doping regions such as source and drain regions still occupy wide portions in a semiconductor memory device with a three-dimensional structure. Particularly, in a “not and” (NAND) structure semiconductor memory having excellent integration, source regions and drain regions which are positioned alternately has a wide region, which hinders increase of integration.

SUMMARY

Example embodiments may provide nonvolatile memory devices allowing higher integration.

Example embodiments also may provide methods of fabricating the nonvolatile memory devices.

According to example embodiments, nonvolatile memory devices may include a plurality of first control gate electrodes. Each first control gate electrode may be formed so as to be recessed into a semiconductor substrate. A plurality of second control gate electrodes may be formed in such a manner that each second control gate electrode may be disposed between two adjacent parts of the plurality of first control gate electrodes. The plurality of second control gate electrodes may be formed on the semiconductor substrate, over the plurality of first control gate electrodes. A plurality of first storage node films may be disposed between the semiconductor substrate and the plurality of first control gate electrodes, respectively. A plurality of second storage node films may be disposed between the semiconductor substrate and the plurality of second control gate electrodes, respectively.

The first control gate electrodes and the second control gate electrodes may be disposed in one or more NAND structures.

The nonvolatile memory device further may include a plurality of first channel regions surrounding the first control gate electrodes that may be formed near the surface of the semiconductor substrate; and/or a plurality of second channel regions that may be formed near the surface of the semiconductor substrate, below the second control gate electrodes. One or more of the first channel regions may be electrically connected to one or more of the second channel regions.

The nonvolatile memory device further includes a device isolation layer formed on the semiconductor substrate, so that active regions of the semiconductor substrate are defined to be extended across the plurality of first control gate electrodes and the plurality of second control gate electrodes.

According to example embodiments, methods of fabricating nonvolatile memory devices may include: forming a plurality of storage node films to be recessed into a semiconductor substrate; forming a plurality of first control gate electrodes to be recessed into the semiconductor substrate, on the plurality of first storage node films; forming a plurality of second storage node films on the semiconductor substrate, each second storage node film disposed between adjacent two of the plurality of first control gate electrodes; and/or forming a plurality of second control gate electrodes on the plurality of second storage node film, over the plurality of first control gate electrodes.

The methods of fabricating nonvolatile memory devices may further include, before forming the plurality of first storage node films, forming a device isolation layer on the semiconductor substrate so as to define active regions of the semiconductor substrate extended across the plurality of first control gate electrodes and/or the plurality of second control gate electrodes.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments will now be described more fully with reference to the accompanying drawings. Embodiments may, however, be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope to those skilled in the art. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.

It will be understood that when a component is referred to as being “on,” “connected to,” or “coupled to” another component, it may be directly on, connected to, or coupled to the other component or intervening components may be present. In contrast, when a component is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another component, there are no intervening components present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein for ease of description to describe one component and/or feature to another component and/or feature, or other component(s) and/or feature(s), as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

Reference will now be made to example embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals may refer to the like components throughout.

Nonvolatile memory devices according to example embodiments may include electrically erasable programmable read-only memories (EEPROMs) and/or flash memory devices. The flash memory devices may include silicon oxide nitride oxide silicon (SONOS) memory devices.

FIGS. 1,3, and5are views for explaining nonvolatile memory devices and methods of fabricating the nonvolatile memory devices, according to example embodiments. Hereinafter, referring toFIGS. 5 and 6Athrough6D, a nonvolatile memory device according to an example embodiment will be described. The nonvolatile memory device may include a plurality of first control gate electrodes145and/or a plurality of second control gate electrodes165.

A plurality of first storage node films135may be disposed between the plurality of first control gate electrodes145and a semiconductor substrate105, respectively. A plurality of second storage node films155may be disposed between the plurality of second control gate electrodes165and the semiconductor substrate105, respectively. The first control gate electrodes145and the second control gate electrodes165may be alternately arranged. For example, the second control gate electrodes165may be respectively disposed between two adjacent first control gate electrodes145. The number of the first control gate electrodes145and/or the number of the second control gate electrodes165shown in the example embodiment is for illustration purposes only. The number of the first control gate electrodes145and/or the number of the second control gate electrodes165may be more than, the same as, or less than shown. The number of the first control gate electrodes145may be greater than, equal to, or less than the number of the second control gate electrodes165.

For example, the first control gate electrodes145may be recessed into the semiconductor substrate105and/or the second control gate electrodes165may be formed on the semiconductor substrate105. The first control gate electrodes145and/or the second control gate electrodes165may be formed, for example, with step heights on the semiconductor substrate105. One or more of the first control gate electrodes145may be called, for example, “recess type” control gate electrodes or “trench type” control gate electrodes, and one or more of the second control gate electrodes165may be called, for example, “planar type” control gate electrodes. Of course, one or more of the first control gate electrodes145may not be “recess type” or “trench type” control gate electrodes. Similarly, one or more of the second control gate electrodes165may not be “planar type” control gate electrodes.

In the nonvolatile memory device according to an example embodiment, the first control gate electrodes145and/or the second control gate electrodes165may be used as word lines. By controlling the first control gate electrodes145and/or the second control gate electrodes165, data may be programmed and/or erased, to and/or from, the first storage node films135and/or the second storage node films155. A part of the semiconductor substrate105may be used, for example, as bit lines. In an example embodiment, the first control gate electrodes145and the second control gate electrodes165may be alternately arranged, thereby forming a NAND structure.

Example embodiments of the semiconductor substrate105may include bulk semiconductor wafer (i.e., a silicon wafer, a germanium wafer, and/or a silicon-germanium wafer). In addition or in the alternative, the semiconductor substrate105may include a semiconductor epitaxial layer on a bulk semiconductor wafer. The first storage node films135and/or the second storage node films155may include, for example, a polysilicon layer, a silicon nitride layer, dots made of metal and/or silicon, and/or nano-crystal made of metal or silicon, in order to store charges. The first control gate electrodes145and/or the second control gate electrodes165may include, for example, a polysilicon layer, a metal layer, and/or a metal silicide layer.

In addition or in the alternative, a plurality of first tunneling insulation films130may be respectively disposed between the first storage node films135and the semiconductor substrate105, and/or a plurality of first blocking insulation films140may be respectively disposed between the first storage node films135and the first control gate electrodes145. Also, a plurality of second tunneling insulation films150may be respectively disposed between the second storage node films155and the semiconductor substrate105, and/or a plurality of second blocking insulation films160may be respectively disposed between the second storage node films155and the second control gate electrodes165.

For example, the first tunneling insulation films130and/or the second tunneling insulation films150may include an insulating film (i.e., an oxide film and/or a nitride film) allowing tunneling of charges. The first blocking insulation films140and/or the second blocking insulation films160may include a proper insulation film, for example, an oxide film, a nitride film, and/or a film with a high dielectric constant K.

In example embodiments, the second control gate electrodes165may be disposed higher than the first control gate electrodes145, so that the second control gate electrodes165may not be electrically connected with the first control gate electrodes145. A plurality of first channel regions170may be respectively defined, for example, near semiconductor substrate regions which surround the first control gate electrodes145, and a plurality of second channel regions175may be respectively defined, for example, near semiconductor substrate regions below the second control gate electrodes165. When a turn-on voltage is applied to the first control gate electrodes145and/or the second control gate electrodes165, the first channel regions170and/or the second channel regions175may function as channels allowing current to flow.

In example embodiments, if the first control gate electrodes145and/or the second control gate electrodes165may be formed with different heights in such a manner that their edges may be adjacent to each other, the first channel regions170may be electrically connected with the second channel regions175. Further, as illustrated inFIG. 6A, the edges of the first channel regions170may overlap the edges of the second channel regions175. By overlapping of the first channel regions170and/or the second channel regions175, a current may continuously flow, for example, without a separate impurity doping region (i.e., without source regions and/or drain regions).

For example, in a nonvolatile memory device with a NAND structure, it may be unnecessary to form one or more impurity doping regions between the first control gate electrodes145and/or the second control gate electrodes165that act as word lines. Accordingly, integration of a nonvolatile memory device may be greatly improved compared with related art techniques. If the width of an impurity doping region is similar to the width of one of the first control gate electrodes145and/or one of the second control gate electrodes165, integration of the nonvolatile memory device according to an example embodiment may be double the integration of the related art techniques.

However, in order to further enhance reliability in electrical connections of the first channel regions170and/or the second channel regions175, an impurity doping region (not shown) may be formed, for example, between each first channel region170and each second channel region175. In this case, the impurity doping region may be defined between each first control gate electrode145and each second control gate electrode165near the surface of the semiconductor substrate105. Accordingly, in this case, the width of the impurity doping region may be greatly reduced compared to the related art techniques. The impurity doping region may be doped, for example, with a conductive-type material different from the semiconductor substrate.

Also, a plurality of device isolation layers127may be formed on the semiconductor substrate105in order to define active regions105a (seeFIGS. 1 and 3) on the semiconductor substrate105. For example, the active regions105a may extend across the first control gate electrodes145and/or the second control gate electrodes165, and the device isolation layers127may surround the active regions105a. Accordingly, the nonvolatile memory device may have an array structure. Parts in which the device isolation layers127may be formed may be called “field regions”, corresponding to the active regions105a.

For example, the device isolation layers127may include a plurality of first insulation films115and/or a plurality of second insulation films125. The first insulation films115and/or the second insulation films125may be disposed, for example, with step heights. The first control gate electrodes145and/or the second control gate electrodes165may extend onto the device isolation layers127. For example, the first control gate electrodes145may be formed on the second insulation films125and/or the second control gate electrodes165may be formed on the first insulation films115. Accordingly, the first control gate electrodes145and/or the second control gate electrodes165may be formed, for example, on the device isolation layers127with the same step height as on the active regions105a.

However, according to another example embodiment, the first control gate electrodes145and/or the second control gate electrodes165may be formed on the device isolation layers127with a step height different from that on the active regions105a.

If the nonvolatile memory device is a flash memory device with a NAND structure, selection gate electrodes (not shown) may be further formed on the first control gate electrodes145and/or the second control gate electrodes165over the semiconductor substrate105.

Hereinafter, a method of fabricating the nonvolatile memory device will be described.

Referring toFIGS. 1 and 2Athrough2D, device isolation layers127may be formed on a semiconductor substrate105in order to define active regions105aon the semiconductor substrate105. In more detail, in order to define the active regions105a, a plurality of first trenches110may be formed in the semiconductor substrate105. For example, the plurality of first trenches110may be formed using photolithography and/or etching. Successively, a plurality of first insulation films115may be formed, for example, to fill up the first trenches110. The first insulation films115may be formed using a related art insulation film deposition method, for example, using a chemical vapor deposition (CVD) method and/or a planarization method.

A plurality of second trenches120may be formed in the semiconductor substrate105, across the first trenches110. When the second trenches120may be formed or before the second trenches120may be formed, portions of the first insulation films115located at intersections of the first trenches110and the second trenches120may be removed. Accordingly, the depths of the corresponding parts of the second trenches120that intersect the first trenches110may be deeper, for example, than the depths of the first trenches110. A plurality of second insulation films125may be formed to fill up the depths of the corresponding parts of the second trenches120that intersect the first trenches110. For example, the second insulation films125may be formed in a manner to contact the first insulation films115.

In example embodiments, by the plurality of second trenches120, step heights or grooves may be formed in the active regions105a, and by the first insulation films115and/or the second insulation films125, step heights or grooves may be formed in the device isolation layers127. The parts in which the device isolation layers127may be formed may be called “field regions”, corresponding to the active regions105a.

Referring toFIGS. 3 and 4Athrough4D, a plurality of first tunneling insulation films130may be formed, for example, on the surface region of the semiconductor substrate105exposed by the second trenches120. For example, the first tunneling insulation films130may be formed using a thermal oxidation method and/or the CVD method. Successively, a plurality of first storage node films135may be formed on the first tunneling insulation films130. For example, the first storage node films135may be formed using the CVD method.

A plurality of first blocking insulation films140may be formed on the first storage node films135. A plurality of first control gate electrodes145may be formed on the first blocking insulation films140to fill up the second trenches120. For example, by forming a conductive layer to fill up the second trenches120and planarizing the resultant layer, a plurality of first gate electrodes145may be formed. Accordingly, the first control gate electrodes145may be recessed into the semiconductor substrate105. In the field regions, the first control gate electrodes145may be disposed on the second insulation films125.

In another example embodiment, the first tunneling insulation films130and the first blocking insulation films140may have different shapes.

Referring toFIGS. 5 and 6Athrough6D, a plurality of second tunneling insulation films150may be formed on a portion of the semiconductor substrate regions between the second trenches120. For example, the second tunneling insulation films150may be formed using the thermal oxidation method and/or the CVD method. Successively, a plurality of second storage node films155may be formed on the second tunneling insulation films150. For example, the second storage node films155may be formed using the CVD method.

At this point, for example, a plurality of second blocking insulation films160may be formed on the second storage node films155. A plurality of second control gate electrodes165may be formed on the second blocking insulation films160. For example, by forming a conductive layer on the semiconductor substrate105and patterning the resultant layer, the second control gate electrodes165may be formed. Accordingly, the second control gate electrodes165may be respectively formed, for example, with a planar structure between two first control gate electrodes145. In the field regions, the second control gate electrodes165may be disposed on the first insulation films115.

Because the first control gate electrodes145may be respectively disposed with the same or different step heights from the second control gate electrodes165in a manner to be adjacent to each other, the plurality of first channel regions170and the plurality of second channel regions175may be defined so that the first channel regions170may be electrically connected with the second channel regions175near the surface of the semiconductor substrate105. Also, in another example embodiment, by performing impurity doping on semiconductor substrate regions exposed between the first control gate electrodes145and the second control gate electrodes165, it may be possible to form impurity doping regions between the first channel regions170and the second channel regions175, respectively.

In another example embodiment, the second tunneling insulation films150and the second blocking insulation films160may have different shapes.

Finally, a wiring structure may be formed by methods known to those of ordinary skill in the art.