Detecting and estimating the pose of an object using a neural network model

An object detection neural network receives an input image including an object and generates belief maps for vertices of a bounding volume that encloses the object. The belief maps are used, along with three-dimensional (3D) coordinates defining the bounding volume, to compute the pose of the object in 3D space during post-processing. When multiple objects are present in the image, the object detection neural network may also generate vector fields for the vertices. A vector field comprises vectors pointing from the vertex to a centroid of the object enclosed by the bounding volume defined by the vertex. The object detection neural network may be trained using images of computer-generated objects rendered in 3D scenes (e.g., photorealistic synthetic data). Automatically labelled training datasets may be easily constructed using the photorealistic synthetic data. The object detection neural network may be trained for object detection using only the photorealistic synthetic data.

TECHNICAL FIELD

The present disclosure relates to pose detection, and more particularly to detecting the pose of an object using a neural network model.

BACKGROUND

Detecting an object and determining the pose of the object is important for human-robot interaction. Conventional neural network systems for object detection and pose estimation require training using large amounts of labeled training data comprising real-world data (road scenes, etc.). Labeled training data is typically generated by gathering real images that are manually labelled which is very time-consuming. In contrast, large amounts of synthetic training data may be generated easily and labeled automatically. One of the key challenges of using synthetic training data has been to bridge the so-called reality gap, so that neural networks trained on synthetic data operate correctly when exposed to real-world data. There is a need for addressing these issues and/or other issues associated with the prior art.

SUMMARY

An object detection neural network receives an input image including an object and generates belief maps for vertices of a bounding volume that encloses the object. The belief maps are used, along with three-dimensional (3D) coordinates defining the bounding volume, to compute the pose of the object in 3D space during post-processing. When multiple objects are present in the image, the object detection neural network may also generate vector fields for the vertices. A vector field comprises vectors pointing from the vertex to a centroid of the object enclosed by the bounding volume defined by the vertex. The object detection neural network may be trained using images of computer-generated objects rendered in 3D scenes (e.g., photorealistic synthetic data). Automatically labelled training datasets may be easily constructed using the photorealistic synthetic data. The object detection neural network may be trained for object detection using only the photorealistic synthetic data.

A method, computer readable medium, and system are disclosed for estimating the pose for an object. An image including an object is received and processed by a neural network model to generate a belief map corresponding to a location of a keypoint associated with the object, the belief map comprising a probability value for each pixel of the image. A pose for the object is estimated based on the location.

A method, computer readable medium, and system are disclosed for generating synthetic images for training a neural network model. A three-dimensional (3D) object of interest within a 3D scene is rendered to produce a rendered image of the object of interest. Task-specific training data corresponding to the object of interest is computed, where the task-specific training data comprises a belief map indicating a centroid location within the rendered image for a geometric center of the object of interest. The task-specific training data corresponding to the object of interest and the input image are included as a test pair in a synthetic training dataset for training a neural network.

DETAILED DESCRIPTION

Detecting an object and estimating the pose of the object is important for human-robot interaction. For example, an integrated robotic system uses estimated poses to solve tasks such as pick-and-place, object handoff, and path following. In an embodiment, the pose is a 6 degrees-of-freedom (6-DoF) pose. In the context of the following description, a 6-DoF pose is defined by (x, y, z) coordinates in three-dimensional (3D) space and an orientation, for example roll, pitch, and yaw. An object detection neural network may be trained to detect one or more objects of interest within an image captured by a single camera and estimate the pose of each detected object in 3D space. In the context of the following description, the image may include other objects in addition to an object of interest. The object detection neural network is trained to detect the object of interest and ignore the other objects. The object detection neural network may be trained to detect multiple instances of an object of interest of the same object class. The object detection neural network may be trained to detect objects of interest of different object classes. In the following description, an object of interest is a rigid object that may be referred to simply as an object.

The object detection neural network receives an input image including an object and generates belief maps and vector fields for vertices of a bounding volume that encloses the object. A belief map is a probability map for the image over image space. The belief maps and vector fields are used to estimate 3D coordinates defining the bounding volume, from which the pose of the object in 3D space is computed during post-processing. The object detection neural network may be trained using images of computer-generated objects rendered in 3D scenes (e.g., photorealistic synthetic data). Training datasets including photorealistic synthetic data may be easily generated. In an embodiment, the object detection neural network is trained using only photorealistic synthetic data. In an embodiment, the object detection neural network is trained using a combination of photorealistic synthetic data and real data. The object detection neural network may be trained to detect and estimate the pose of objects accurately even when changes occur in the environment such as lighting conditions, camera intrinsics, clutter, and so forth.

FIG. 1Aillustrates a block diagram of a pose estimation system100, in accordance with an embodiment. The pose estimation system100includes a keypoint module110, a set of multi-stage modules105, and a pose unit120. Although the pose estimation system100is described in the context of processing units, one or more of the keypoint module110, set of multi-stage module105, and a pose unit120may be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the keypoint module110may be implemented by a GPU, CPU (central processing unit), or any processor capable of processing an image to generate keypoint data. In an embodiment, parallel processing unit (PPU)300ofFIG. 3is configured to implement the pose estimation system100. Furthermore, persons of ordinary skill in the art will understand that any system that performs the operations of the pose estimation system100is within the scope and spirit of embodiments of the present disclosure.

The pose estimation system100receives an image captured by a single camera. The image may include one or more objects for detection. In an embodiment, the image comprises color data for each pixel in the image without any depth data. The pose estimation system100first detects keypoints associated with the object and then estimates 2D projections of vertices defining a bounding volume enclosing the object associated with the keypoints. The keypoints may include a centroid of the object and vertices of a bounding volume enclosing the object. The keypoints are not explicitly visible in the image, but are instead inferred by the pose estimation system100. In other words, an object of interest is visible in the image, except for portions of the object that may be occluded, and the keypoints associated with the object of interest are not explicitly visible in the image. The 2D locations of the keypoints are estimated by the pose estimation system100using only the image data. The pose unit120recovers a 3D pose of an object using the estimated 2D locations, camera intrinsic parameters, and dimensions of the object.

The keypoint module110receives an image including an object and outputs image features. In an embodiment, the keypoint module110includes multiple layers of a convolutional neural network. In an embodiment, the keypoint module110comprises the first ten layers of the Visual Geometry Group (VGG-19) neural network that is pre-trained using the ImageNet training database, followed by two 3×3 convolution layers to reduce the feature dimension from 512 to 256, and from 256 to 128. The keypoint module110outputs 3 channels of features, one for each channel (e.g., RGB).

The image features are input to a set of multi-stage modules105. In an embodiment, the set of multi-stage modules105includes a first multi-stage module105configured to detect a centroid of an object and additional multi-stage modules105configured to detect vertices of a bounding volume that encloses the object in parallel. In an embodiment, the set of multi-stage modules105includes a single multi-stage module105that is used to process the image features in multiple passes to detect the centroid and the vertices of the bounding volume serially. In an embodiment, the multi-stage modules105are configured to detect vertices without detecting the centroid.

Each multi-stage module105includes T stages of belief map units115. In an embodiment, the number of stages is equal to six (e.g., T=6). The belief map unit115-1is a first stage, the belief map unit115-2is a second stage, and so on. The image features extracted by the keypoint module110are passed to each of the belief map units115within a multi-stage module105. In an embodiment, the keypoint module110and the multi-stage modules105comprise a feedforward neural network that takes as input an RGB image of size w×h×3 and branches to produce two different outputs such as, e.g., belief maps. In an embodiment, w=640 and h=480. The stages of belief map units115operate serially, with each stage (belief map unit115) taking into account not only the image features but also the outputs of the immediately preceding stage.

Stages of belief map units115within each multi-stage module105generate a belief map for estimation of a single 2D location associated with the object in the image. A first belief map comprises probability values for a centroid of the object and additional belief maps comprise probability values for the vertices of a bounding volume that encloses the object.

In an embodiment, the 2D locations of detected vertices are 2D coordinates of 3D bounding vertices that each enclose an object and are projected into image space in the scene. By representing each object by a 3D bounding box, an abstract representation of each object is defined that is sufficient for pose estimation yet independent of the details of the object's shape. When the bounding volume is a 3D bounding box, nine multi-stage modules105may be used to generate belief maps for the centroid and eight vertices in parallel. The pose unit125estimates the 2D coordinates of the 3D bounding box vertices projected into image space and then infers the object location and pose in 3D space from perspective-n-point (PnP), using either traditional computer vision algorithms or another neural network. PnP estimates the pose of an object using a set of n locations in 3D space and projections of the n locations in image space. In an embodiment, the pose estimation system100infers, in real time, the 3D poses of known objects within clutter from a single RGB image.

In an embodiment, the stages of belief map units115are each convolutional neural network (CNN) stages. When each stage is a CNN, each stage leverages an increasingly larger effective receptive field as data is passed through the neural network. This property enables the stages of belief map units115to resolve ambiguities by incorporating increasingly larger amounts of context in later stages.

In an embodiment, the stages of belief map units115receive 128-dimensional features extracted by the keypoint module110. In an embodiment, the belief map unit115-1comprises three 3×3×128 layers and one 1×1×512 layer. In an embodiment, the belief map unit115-2is a 1×1×9 layer. In an embodiment, the belief map units115-3through115-T are identical to the first stages, except that each receives a 153-dimensional input (128+16+9=153) and includes five 7×7×128 layers and one 1×1×128 layer before the 1×1×128 or 1×1×16 layer. In an embodiment, each of the belief map units115are of size w/8 and h/8, with rectified linear unit (ReLU) activation functions interleaved throughout.

FIG. 1Billustrates an input image and the input image and detected vertices of bounding volumes enclosing object of interests, in accordance with an embodiment. The detected vertices are projected from 3D space into the image space.

FIG. 1Cillustrates an input image and projected vertices associated with an object of interest, and belief maps and a detected vertex of a bounding volume enclosing the object of interest, in accordance with an embodiment. The input image includes a toy car that is an object of interest and other objects. The pose estimation system100receives the input image and estimates 2D locations of keypoints including at least 4 of 8 vertices of the bounding volume. The pose estimation system100may also receive the centroid of the bounding volume. The centroid of the bounding volume approximates, and in some cases equals, the centroid of the object. Each stage of the belief map units115receives the image features and belief map generated by the previous stage to produce a belief map corresponding to either the centroid or one of the vertices. As shown inFIG. 1C, a belief map140-1corresponding to a front-left-bottom vertex of the bounding volume and having two peaks is generated by a first stage, namely the belief map unit115-1. The second stage, namely the belief map unit115-2, processes the image features and the belief map140-1to produce a belief map140-2also having two peaks. A fifth stage processes the image features and a belief map generated by the fourth stage to produce a belief map140-5also having two peaks. Finally, a 6th stage (T=6), namely the belief map unit115-T, processes the image features and the belief map140-5to produce a belief map140-6having a single peak indicating a detected vertex. The multi-stage process allows the multi-stage module105to refine the predictions by incorporating more context, over multiple stages.

FIG. 1Dillustrates a flowchart of a method130for estimating the pose of an object, in accordance with an embodiment. Although method130is described in the context of a processing unit, the method130may also be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the method130may be executed by a GPU (graphics processing unit), CPU (central processing unit), or any processor capable of detecting one or more objects, generating belief maps and vector fields for the detected objects, and estimating the poses of the detected objects. Furthermore, persons of ordinary skill in the art will understand that any system that performs method130is within the scope and spirit of embodiments of the present disclosure.

At step135, the pose estimation system100receives an image including an object. At step136, the keypoint module110and the stages of belief map units115process the image to generate a belief map corresponding to a location of a keypoint associated with the object. The belief map comprises a probability value for each pixel of the image. In an embodiment, a separate belief map is generated for each vertex of a bounding volume that encloses the object. In an embodiment, a belief map is generated for the centroid of the bounding volume that encloses the object. At step138, the pose unit120estimates the pose for the object based on the centroid location and the vector field. In an embodiment, the pose unit120is configured to estimate the pose using only four locations of bounding box vertices. When one or more bounding volume vertices are occluded in an image, the location of the centroid of the bounding volume may be used by the pose unit120to compute a location of the object in 3D space. When one or more bounding volume vertices are occluded in an image, the location of the centroid of the bounding volume and locations of a portion of the bounding volume vertices may be used by the pose unit120to compute the pose of the object.

When multiple objects of interest are present in an image, additional information may be needed to associate detected vertices of bounding volumes with particular objects. In an embodiment, a vector field is computed for each detected vertex, where the vector field comprises a vector pointing from the detected vertex to the closest centroid of a bounding volume for each pixel in the image.

FIG. 1Eillustrates a block diagram of another pose estimation system150, in accordance with an embodiment. The pose estimation system150includes a keypoint module110, a set of multi-stage modules155, and a pose unit125. Although the pose estimation system150is described in the context of processing units, one or more of the keypoint module110, set of multi-stage module155, and a pose unit125may be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the keypoint module110may be implemented by a GPU, CPU (central processing unit), or any processor capable of processing an image to generate keypoint data. In an embodiment, parallel processing unit (PPU)300ofFIG. 3is configured to implement the pose estimation system100. Furthermore, persons of ordinary skill in the art will understand that any system that performs the operations of the pose estimation system100is within the scope and spirit of embodiments of the present disclosure.

As described in conjunction withFIG. 1A, the keypoint module110receives an image including an object and outputs image features. The image features are input to a set of multi-stage modules155. In an embodiment, the set of multi-stage modules155includes a first multi-stage module155configured to detect a centroid of an object and additional multi-stage modules155configured to detect vertices of a bounding volume that encloses the object in parallel. In an embodiment, the set of multi-stage modules155includes a single multi-stage module155that is used to process the image features in multiple passes to detect the centroid and the vertices of the bounding volume serially.

Each multi-stage module155includes T stages of belief map units115and T stages of vector field units120. In an embodiment, the number of stages is equal to six (e.g., T=6). The belief map unit115-1and vector field unit145-1are a first stage, the belief map unit115-2and vector field unit145-2are a second stage, and so on. The image features extracted by the keypoint module110are passed to each of the belief map units115and the vector field units145within a multi-stage module155. In an embodiment, the keypoint module110and the multi-stage modules155comprise a feedforward neural network that takes as input an RGB image of size w×h×3 and branches to produce two different outputs such as, e.g., belief maps and vector fields. In an embodiment, w=640 and h=480. The stages of belief map units115and the stages of vector field units145operate serially, with each stage (belief map unit115and corresponding vector field unit145) taking into account not only the image features but also the outputs of the immediately preceding stage.

Stages of belief map units115within each multi-stage module155generate a belief map for estimation of a single 2D location associated with the object in the image. A first belief map comprises probability values for a centroid of the object and additional belief maps comprise probability values for the vertices of a bounding volume that encloses the object. Stages of vector field units145within the multi-stage modules155output vector fields for the detected vertices. The vector fields are used by the pose unit125to assign each vertex of a bounding volume to one object when multiple objects are present in the image. In an embodiment, when a difference between an angle of the vector field for a vertex and a direction from the vertex to the centroid of an object is within an angular threshold value, the vertex is assigned to the object.

In an embodiment, the 2D locations of detected vertices are 2D coordinates of 3D bounding vertices that each enclose an object and are projected into image space in the scene. By representing each object by a 3D bounding box, an abstract representation of each object is defined that is sufficient for pose estimation yet independent of the details of the object's shape. When the bounding volume is a 3D bounding box, nine multi-stage modules155may be used to generate belief maps for the centroid and eight vertices in parallel. The pose unit125estimates the 2D coordinates of the 3D bounding box vertices projected into image space and then infers the object location and pose in 3D space from perspective-n-point (PnP), using either traditional computer vision algorithms or another neural network. PnP estimates the pose of an object using a set of n locations in 3D space and projections of the n locations in image space. In an embodiment, the pose estimation system150infers, in real time, the 3D poses of known objects within clutter from a single RGB image.

In an embodiment, the stages of belief map units115and the stages of vector field units145are each convolutional neural network (CNN) stages. When each stage is a CNN, each stage leverages an increasingly larger effective receptive field as data is passed through the neural network. This property enables the stages of belief map units115and the stages of vector field units145to resolve ambiguities by incorporating increasingly larger amounts of context in later stages.

In an embodiment, the stages of belief map units115and the stages of vector field units145receive 128-dimensional features extracted by the keypoint module110. In an embodiment, the belief map unit115-1and vector field unit145-1each comprise three 3×3×128 layers and one 1×1×512 layer. In an embodiment, the belief map unit115-2is a 1×1×9 layer. In an embodiment, the vector field unit145-2is a 1×1×16 layer. In an embodiment, the belief map units115-3through115-T and the vector field units145-3through145-T are identical to the first stages, except that each receives a 153-dimensional input (128+16+9=153) and includes five 7×7×128 layers and one 1×1×128 layer before the 1×1×128 or 1×1×16 layer. In an embodiment, each of the belief map units115and the vector field units120are of size w/8 and h/8, with rectified linear unit (ReLU) activation functions interleaved throughout.

Let Bv,tc∈+wt×htbe the belief map of type v∈V, of class c∈C, and of stage t=1 . . . T, where V includes the 8 vertex types (front-top-left etc.) as well as the centroid, C is the set of rigid objects (e.g., soup can, toy cars, etc.), and T is the total number of belief map units115. In an embodiment, the number of belief map units115equals a number of vector field units145. Each vector field unit145outputs a vector field Vv,tc∈wt×ht×2that indicates the direction from each pixel to the corresponding centroid. In an embodiment, T=6, and wt=w/2 and ht=h/2 for all but the last stage.

After the set of belief map units115have processed an image, there may be more than one object of the same class represented in the belief maps that are output to the pose unit125. The vector field for each vertex points each pixel toward the direction of the object's centroid and may be used for inferring object instances during a postprocessing step performed by the pose unit125. In an embodiment, the pose unit125applies a heuristic algorithm to the belief maps and vector fields to associate detected vertex locations with a complete object. In greater detail, in an embodiment, local maxima are found in the belief maps, where a peak of the centroid belief map is used for object detection confidence. Centroid peaks with confidence values below a certain threshold are discarded. For each vertex peak (peak in a belief map for a vertex), a normalized vector {right arrow over (v)} given by the vector field for the vertex is compared with the vector created from the vertex peak to every centroid, {right arrow over (ct)}, where i indicates the centroid. Assignments of vertices to centroids are based on both distance and angle between {right arrow over (v)} and {right arrow over (ci)} in a greedy manner, e.g., a vertex is associated with a centroid only when the angle is lower than a predetermined threshold value. Multiple assignments are solved by favoring a lower distance to the candidate centroid.

After associating vertices with objects, the pose unit125may use PnP to retrieve the pose of the object. Specifically, in an embodiment, the 2D locations of the detected vertices of the bounding volume, the camera intrinsics, and the object dimensions are used to recover the final translation and rotation of the object with respect to the camera (e.g., the 3D position and orientation of objects in the scene, often referred to a 6-DoF pose).

The ability to determine the pose of an object in space from a single image enables a robot to interact with a human nearby, e.g., perform pick-and-place of objects, handing an object to the person, receive an object handed off from a person, or watching the person handling the object for imitation learning (path following). In an embodiment, the pose estimation system150estimates the pose of one or more objects in an image in real time for the purpose of enabling the robot to manipulate the objects. In an embodiment, the object is a rigid, known object for which the pose estimation system150is trained to learn the appearance and shape of the object. Through training, the pose estimation system150, generalizes to a variety of environments including extreme lighting conditions and is able to estimate the pose of an object in a cluttered scene.

FIG. 1Fillustrates a flowchart of another method160for estimating the pose of an object, in accordance with an embodiment. Although method160is described in the context of a processing unit, the method160may also be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the method160may be executed by a GPU (graphics processing unit), CPU (central processing unit), or any processor capable of detecting one or more objects, generating belief maps and vector fields for the detected objects, and estimating the poses of the detected objects. Furthermore, persons of ordinary skill in the art will understand that any system that performs method160is within the scope and spirit of embodiments of the present disclosure.

At step135, the post estimation system150receives an image including an object. At step165, the keypoint module110and the stages of belief map units115process the image to identify a centroid location for a geometric center of the object. At step170the keypoint module110and the stages of vector field units145process the image to generate a vector field comprising a vector pointing toward the centroid location for each pixel in the image. In an embodiment, a separate vector field is generated for each vertex of a bounding volume that encloses the object. At step175, the pose unit125estimates the pose for the object based on the centroid location and the vector field.

Training and testing a deep neural network is a time-consuming and expensive task which typically involves collecting and manually annotating a large amount of data for supervised learning. This requirement is problematic when the task demands either expert knowledge, labels that are difficult to specify manually, or images that are difficult to capture in large quantities with sufficient variety. For example, 3D poses or pixelwise segmentation can take a substantial amount of time for a human to manually label a single image.

In contrast to 2D object detection, for which labeled bounding boxes are relatively easy to annotate, 3D object detection requires labeled data that is almost impossible to generate manually. The labor-intensive nature of the process impedes the ability to generate training data with sufficient variation. Also modern computer vision approaches tend to rely upon training and testing on similarly distributed datasets, e.g., the training and testing sets come from video sequences captured by the same camera under similar lighting and environmental conditions. As it turns out, these systems often struggle to robustly adapt to significantly different data distributions, for example, settings in which the lighting conditions or camera intrinsics are changed. To overcome these difficulties, in an embodiment, the pose estimation system100or150may be trained solely on synthetic data with the specific goal of causing the keypoint module110and the multi-stage module(s)105to better generalize to different conditions. A synthetic training dataset that is automatically labeled may be generated using both domain randomization and photorealistic synthetic data.

Domain randomization intentionally abandons photorealism by randomly perturbing the environment in non-photorealistic ways (e.g., by adding random textures) to force a neural network model to learn to focus on the essential features of images. More specifically, the neural network model is trained to detect objects of interest and ignore other objects in the images. In an embodiment, the generated training data is used to train a neural network model for the task of object detection. In an embodiment, the generated training data is used to train a neural network model for the task of instance segmentation. In an embodiment, the generated training data is used to train a neural network model for the task of semantic segmentation.

In an embodiment, the reality gap is spanned by training the pose estimation system100with a combination of domain randomized synthetic data and photorealistic synthetic data. In an embodiment, training data generated using domain randomization includes synthetic input images generated by rendering 3D objects of interest on a 2D background image. The 3D objects of interest are objects that the pose estimation system100or150is trained to detect. In an embodiment, the photorealistic synthetic training data includes synthetic input images generated by rendering 3D objects of interest in a 3D scene. Importantly, the 3D objects of interest may interact with other objects in the 3D scene and other 3D objects of interest.

In an embodiment, the generated training data includes a synthetic input image including at least one rendered object of interest paired with task-specific training data corresponding to the at least one rendered object of interest. In an embodiment, the task-specific training data for object detection and pose estimation is belief maps and vector fields for the keypoints of the rendered object of interest.

FIG. 2Aillustrates a block diagram of a synthetic training data generation system200, in accordance with an embodiment. The training data generation system200includes a graphics processing unit (GPU)205, the training data computation unit210, and an input image generator220. Although the training data generation system200is described in the context of processing units, one or more of the GPU205, the training data computation unit210, and the input image generator220may be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. In an embodiment, parallel processing unit (PPU)300ofFIG. 3is configured to implement the synthetic training data generation system200. Furthermore, persons of ordinary skill in the art will understand that any system that performs the operations of the synthetic training data generation system200is within the scope and spirit of embodiments of the present disclosure.

In order to avoid overfitting to a particular dataset distribution, the training data may include a combination of domain randomized synthetic data and photorealistic synthetic data to train the pose estimation system100or150that is robust to light changes, camera variation and texture. In an embodiment, the photorealistic synthetic data is a photorealistic falling things (FAT) dataset that provides context. The photorealistic falling things dataset includes real-world 3D objects placed in different virtual environments, where the real-world 3D objects are allowed to fall under the weight of gravity, and to collide with each other and with surfaces in the virtual environment, interacting in physically plausible ways. In an embodiment, domain randomization provides diversified poses by including rendered images of the object(s) of interest and various distractor objects, overlaid textures, backgrounds, object poses, lighting, and/or noise in front of a background image. The process of generating the photorealistic synthetic data is described first.

To generate the photorealistic synthetic data the GPU205receives scene data, one or more 3D synthetic objects (object of interest), and rendering parameters. The GPU205processes the 3D object(s) according to the rendering parameters to generate a rendered image including one or more instances of the 3D objects within a virtual scene defined by the scene data. Importantly, a rendered 3D object is an image of a synthetic object of interest and is not a photorealistic image or an object extracted from a photorealistic image.

The rendering parameters specify aspects of a 3D scene including the 3D synthetic object(s) of interest to be rendered and, therefore, may affect the appearance of the rendered 3D synthetic object(s) of interest. In an embodiment, the position of the virtual camera with respect to the 3D scene (e.g., azimuth, elevation, etc.) is defined by the rendering parameters. In an embodiment, an orientation of the virtual camera with respect to the 3D scene (e.g., pan, tilt, and roll) is defined by the rendering parameters. In an embodiment, the position and/or the orientation of the virtual camera with respect to the 3D scene (e.g., pan, tilt, and roll) is randomly determined by the synthetic training data generation system200. In an embodiment, a number and position of one or more point lights is defined by the rendering parameters. In an embodiment, the number and position of one or more point lights is randomly determined by the synthetic training data generation system200. In an embodiment, a planar light for ambient light is defined by the rendering parameters. In an embodiment, visibility of a ground plane in the 3D scene is defined by the rendering parameters.

In an embodiment, a set of 3D objects includes a number of household objects that are randomly sampled and allowed to fall in front of the virtual camera in three different virtual environments (e.g., a kitchen, sun temple, and forest) to produce rendered images. During the data generation process, the objects are allowed to fall under the modeled force of gravity, as well as to collide with one another and with the surfaces in the virtual scene. While the objects “fall,” the rendering parameters may be defined to rapidly adjust the virtual camera to be positioned at random azimuths, elevations, and distances with respect to the fixation point to collect data. In an embodiment, the azimuth ranged from −120° to +120° (to avoid collision with a wall, when present), elevation from 5° to 85°, and distance from 0.5 m to 1.5 m.

The task-specific training data computation unit210receives the rendered image(s) and computes task-specific training data. The training data is computed based only on the rendered object(s) of interest. In an embodiment, the task is object detection and the training data computation unit210computes bounding volumes for the rendered image(s) of the object(s) of interest. The training data computation unit210may receive location coordinates from the input image generator220defining a location in the input image for each rendered image of an object of interest. The training data computation unit210computes ground truth belief maps and vector fields for each bounding volume as the training data.

In an embodiment, the ground truth belief maps are generated by placing 2D Gaussians at the vertex locations defining the bounding volume with a=2 pixels. In an embodiment, the ground truth vector fields are generated by setting pixels to the normalized x- and y-components of the vector pointing toward the object's centroid. Only the pixels within a predetermined (e.g., 3-pixel) radius of each ground-truth vertex are set to the normalized component values and all other pixels remaining are set at zero. Wherever two vertices reside within the predetermined radius, one of pixel vertices is selected at random to be used for generating the components.

In an embodiment, the training data comprise a set of ground truth belief maps and ground truth vector fields for each rendered image of an object of interest. The training data is not included as part of the input image, but is instead paired with the input image to produce a test pair for generated labeled training data for training a neural network model. During supervised training of a neural network model, the training data corresponding to the rendered 3D object(s) are compared with an output generated by the neural network model when the input image is processed by the neural network model.

The input image generator220receives the rendered image of the virtual scene including the object(s) and outputs the rendered image as the input image. The input image is paired with the training data to produce a test pair for generated synthetic training data for training a neural network model. The rendered objects of interest are 3D synthetic objects that a neural network model may be trained to detect and/or segment. In an embodiment, the input image generator220is omitted.

To expand pose distribution and avoid overfitting to a particular set of 3D objects, a domain randomized dataset including the same 3D objects may be generated. The process of generating domain randomized training data places the 3D objects within a virtual environment consisting of various distractor objects in front of a 2D background image. In an embodiment, the distractor objects are geometric shapes (e.g., cones, pyramids, spheres, cylinders, partial toroids, arrows, pedestrians, trees, etc.). Images are generated by defining the rendering parameters to randomly vary distractor objects, overlay textures on the 3D objects and/or distractor objects, vary backgrounds, vary distractor and/or 3D object poses, vary lighting, and/or include noise.

To generate domain randomized images, the GPU205renders the 3D objects of interest to produce rendered images of objects of interest. The GPU205also renders the distractor objects according to the rendering parameters to produce rendered images of the distractor objects. Importantly, a rendered image of the distractor object is an image of a synthetic distractor object and is not a photorealistic image or an object extracted from a photorealistic image. The rendering parameters may specify a position and/or orientation of the distractor object and/or 3D object in a 3D space, a position and/or orientation of a virtual camera, one or more texture maps, one or more lights including color, type, intensity, position and/or orientation, and the like. In an embodiment, the distractor object may be rendered according to different rendering parameters to produce additional rendered images of the distractor object. Similarly, in an embodiment, the 3D object may be rendered according to different rendering parameters to produce additional rendered images of the 3D object. In an embodiment, one or more different distractor objects may be rendered according to the same or different rendering parameters to produce additional rendered images of the distractor object. Similarly, in an embodiment, one or more different 3D objects may be rendered according to the same or different rendering parameters to produce additional rendered images of the 3D object.

The input image generator220receives the rendered image(s) of the distractor object(s), the rendered image(s) of the 3D object(s), and a background image. In an embodiment, the background image is a 2D image. The background image may be produced by rendering a 3D scene. In an embodiment, the background image is selected from a set of background images. In an embodiment, the background image is randomly selected by the synthetic training data generation system200.

The input image generator220constructs an input image that combines the background image, the rendered image(s) of the 3D object(s), and the rendered image(s) of the distractor object(s), positioning the rendered 3D object(s) and distractor object(s) at various positions within the input image. In an embodiment, the number of rendered 3D objects and the position and/or rotation for each rendered 3D object and/or distractor object is defined by the rendering parameters. In an embodiment, the number of rendered 3D objects and the position and/or rotation for each rendered 3D object and/or distractor object is randomly determined by the input image generator220.

The training data computation unit210does not receive the rendered image(s) of the distractor objects because training data is computed based only on the rendered 3D object(s) (objects of interest). In an embodiment, the task is pose estimation and the neural network model that is trained should ignore the rendered image(s) of the distractor object(s) and detect the rendered image(s) of the 3D object(s) and then estimate poses of the detected object(s).

Incorporation of the rendered distractor objects into the input image improves object detection and/or estimation accuracy for neural network models trained using the training dataset generated by the synthetic training data generation system200. The various rendering parameters may have varying influences on the performance of a neural network model trained using the training dataset. In an embodiment, a neural network model is trained using only the training dataset that is generated using synthetic objects of interest. In an embodiment, a neural network model is trained using the task-specific training dataset that is generated using synthetic objects of interest and a lesser amount of synthetic distractor objects.

FIG. 2Billustrates a flowchart of a method230for generating labeled synthetic training data, in accordance with an embodiment. Although method230is described in the context of a processing unit, the method230may also be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the method230may be executed by a GPU (graphics processing unit), CPU (central processing unit), or any processor capable of rendering 3D objects, constructing images, and computing belief maps and vector fields. Furthermore, persons of ordinary skill in the art will understand that any system that performs method230is within the scope and spirit of embodiments of the present disclosure.

At step235, the GPU205renders a 3D object of interest within a 3D scene to produce a rendered image including the object of interest. The 3D object of interest is rendered according to the rendering parameters. In an embodiment, the GPU205renders the 3D object of interest using different rendering parameters to produce additional rendered images of the object of interest. In an embodiment, the GPU205renders a distractor object to produce a rendered image of the distractor object that is included in the rendered image.

At step240, task-specific training data corresponding to the object of interest is computed by the training data computation unit210. In an embodiment, the task-specific training data comprises a belief map indicating a centroid location within the rendered image for a geometric center of the 3D object of interest. In an embodiment, the centroid location corresponds to a centroid of a bounding volume enclosing the rendered object of interest.

At step245, the task-specific training data corresponding to the object of interest and the input image are included as a test pair in a synthetic training dataset for training a neural network. In an embodiment, the synthetic training dataset is stored in a memory. In an embodiment, the synthetic training dataset that is generated by the synthetic training data generation system200is simultaneously used to train a neural network model, such as the pose evaluation system100. In other words, the training of the neural network model is performed concurrently with generation of the synthetic training data.

FIG. 2Cillustrates a block diagram of neural network model training system250, in accordance with an embodiment. The neural network model training system250includes a pose estimation neural network225and a loss function unit270. In an embodiment, the pose estimation neural network225comprises the pose estimation system100or150with the pose unit120or125, respectively, omitted to produce output data as the belief maps and the vector fields.

Although the neural network model training system250is described in the context of processing units, one or more of the pose estimation neural network225and the loss function unit270may be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the pose estimation neural network225may be implemented by a GPU205, CPU (central processing unit), or any processor capable of implementing a neural network model. In an embodiment, parallel processing unit (PPU)300ofFIG. 3is configured to implement the neural network model training system250. Furthermore, persons of ordinary skill in the art will understand that any system that performs the operations of the neural network model training system250is within the scope and spirit of embodiments of the present disclosure.

During training, the input images for test pairs included in the training dataset are processed, according to weights, by the pose estimation neural network225to generate output data. The output data and task-specific training data for the test pairs are processed by the loss function unit270. In an embodiment, to avoid the vanishing gradients problem during training, the loss function unit270computes a loss at the output of each multi-stage module105, using the L2loss for the belief maps and vector fields. The loss function unit270generates updated weights to reduce differences between the task-specific training data and the output data. When the differences are reduced to a predetermined value, training is complete.

The training dataset generated by the synthetic training data generation system200may be used to train the pose estimation neural network225to accomplish complex tasks such as object detection and pose estimation with performance comparable to more labor-intensive (and therefore more expensive) datasets.

The method130for detecting and estimating the pose of an object uses the multi-stage module105or155employing multiple stages to refine ambiguous estimations of the 2D locations of projected vertices of a 3D bounding volume that encloses the object. The 2D locations are then used by the pose unit110or150to predict an estimated pose, assuming known camera intrinsics and object dimensions. The pose estimation system100or150can retrieve the poses of objects in occluded environments.

The method230for generating and combining both non-photorealistic synthetic (domain randomized) and photorealistic synthetic for training the pose estimation system100or150bridges the reality gap for real-world applications. Using a combination of non-photorealistic domain randomized data and photorealistic data leverages the strengths of both types of data, complementing one another and yielding results that are better than those achieved by either alone. Synthetic data has an additional advantage in that overfitting to a particular dataset distribution is avoided, thus producing a pose estimation system100or150that is robust to lighting changes, camera variations, and backgrounds.

Parallel Processing Architecture

FIG. 3illustrates a parallel processing unit (PPU)300, in accordance with an embodiment. In an embodiment, the PPU300is a multi-threaded processor that is implemented on one or more integrated circuit devices. The PPU300is a latency hiding architecture designed to process many threads in parallel. A thread (e.g., a thread of execution) is an instantiation of a set of instructions configured to be executed by the PPU300. In an embodiment, the PPU300is a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data in order to generate two-dimensional (2D) image data for display on a display device such as a liquid crystal display (LCD) device. In other embodiments, the PPU300may be utilized for performing general-purpose computations. While one exemplary parallel processor is provided herein for illustrative purposes, it should be strongly noted that such processor is set forth for illustrative purposes only, and that any processor may be employed to supplement and/or substitute for the same.

One or more PPUs300may be configured to accelerate thousands of High Performance Computing (HPC), data center, and machine learning applications. The PPU300may be configured to accelerate numerous deep learning systems and applications including autonomous vehicle platforms, deep learning, high-accuracy speech, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and the like.

As shown inFIG. 3, the PPU300includes an Input/Output (I/O) unit305, a front end unit315, a scheduler unit320, a work distribution unit325, a hub330, a crossbar (Xbar)370, one or more general processing clusters (GPCs)350, and one or more memory partition units380. The PPU300may be connected to a host processor or other PPUs300via one or more high-speed NVLink310interconnect. The PPU300may be connected to a host processor or other peripheral devices via an interconnect302. The PPU300may also be connected to a local memory comprising a number of memory devices304. In an embodiment, the local memory may comprise a number of dynamic random access memory (DRAM) devices. The DRAM devices may be configured as a high-bandwidth memory (HBM) subsystem, with multiple DRAM dies stacked within each device.

The NVLink310interconnect enables systems to scale and include one or more PPUs300combined with one or more CPUs, supports cache coherence between the PPUs300and CPUs, and CPU mastering. Data and/or commands may be transmitted by the NVLink310through the hub330to/from other units of the PPU300such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). The NVLink310is described in more detail in conjunction withFIG. 5B.

The I/O unit305is configured to transmit and receive communications (e.g., commands, data, etc.) from a host processor (not shown) over the interconnect302. The I/O unit305may communicate with the host processor directly via the interconnect302or through one or more intermediate devices such as a memory bridge. In an embodiment, the I/O unit305may communicate with one or more other processors, such as one or more the PPUs300via the interconnect302. In an embodiment, the I/O unit305implements a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus and the interconnect302is a PCIe bus. In alternative embodiments, the I/O unit305may implement other types of well-known interfaces for communicating with external devices.

The I/O unit305decodes packets received via the interconnect302. In an embodiment, the packets represent commands configured to cause the PPU300to perform various operations. The I/O unit305transmits the decoded commands to various other units of the PPU300as the commands may specify. For example, some commands may be transmitted to the front end unit315. Other commands may be transmitted to the hub330or other units of the PPU300such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the I/O unit305is configured to route communications between and among the various logical units of the PPU300.

In an embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the PPU300for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (e.g., read/write) by both the host processor and the PPU300. For example, the I/O unit305may be configured to access the buffer in a system memory connected to the interconnect302via memory requests transmitted over the interconnect302. In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU300. The front end unit315receives pointers to one or more command streams. The front end unit315manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the PPU300.

The front end unit315is coupled to a scheduler unit320that configures the various GPCs350to process tasks defined by the one or more streams. The scheduler unit320is configured to track state information related to the various tasks managed by the scheduler unit320. The state may indicate which GPC350a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. The scheduler unit320manages the execution of a plurality of tasks on the one or more GPCs350.

The scheduler unit320is coupled to a work distribution unit325that is configured to dispatch tasks for execution on the GPCs350. The work distribution unit325may track a number of scheduled tasks received from the scheduler unit320. In an embodiment, the work distribution unit325manages a pending task pool and an active task pool for each of the GPCs350. The pending task pool may comprise a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC350. The active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by the GPCs350. As a GPC350finishes the execution of a task, that task is evicted from the active task pool for the GPC350and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC350. If an active task has been idle on the GPC350, such as while waiting for a data dependency to be resolved, then the active task may be evicted from the GPC350and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the GPC350.

The work distribution unit325communicates with the one or more GPCs350via XBar370. The XBar370is an interconnect network that couples many of the units of the PPU300to other units of the PPU300. For example, the XBar370may be configured to couple the work distribution unit325to a particular GPC350. Although not shown explicitly, one or more other units of the PPU300may also be connected to the XBar370via the hub330.

The tasks are managed by the scheduler unit320and dispatched to a GPC350by the work distribution unit325. The GPC350is configured to process the task and generate results. The results may be consumed by other tasks within the GPC350, routed to a different GPC350via the XBar370, or stored in the memory304. The results can be written to the memory304via the memory partition units380, which implement a memory interface for reading and writing data to/from the memory304. The results can be transmitted to another PPU304or CPU via the NVLink310. In an embodiment, the PPU300includes a number U of memory partition units380that is equal to the number of separate and distinct memory devices304coupled to the PPU300. A memory partition unit380will be described in more detail below in conjunction withFIG. 4B.

In an embodiment, a host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU300. In an embodiment, multiple compute applications are simultaneously executed by the PPU300and the PPU300provides isolation, quality of service (QoS), and independent address spaces for the multiple compute applications. An application may generate instructions (e.g., API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU300. The driver kernel outputs tasks to one or more streams being processed by the PPU300. Each task may comprise one or more groups of related threads, referred to herein as a warp. In an embodiment, a warp comprises 32 related threads that may be executed in parallel. Cooperating threads may refer to a plurality of threads including instructions to perform the task and that may exchange data through shared memory. Threads and cooperating threads are described in more detail in conjunction withFIG. 5A.

FIG. 4Aillustrates a GPC350of the PPU300ofFIG. 3, in accordance with an embodiment. As shown inFIG. 4A, each GPC350includes a number of hardware units for processing tasks. In an embodiment, each GPC350includes a pipeline manager410, a pre-raster operations unit (PROP)415, a raster engine425, a work distribution crossbar (WDX)480, a memory management unit (MMU)490, and one or more Data Processing Clusters (DPCs)420. It will be appreciated that the GPC350ofFIG. 4Amay include other hardware units in lieu of or in addition to the units shown inFIG. 4A.

In an embodiment, the operation of the GPC350is controlled by the pipeline manager410. The pipeline manager410manages the configuration of the one or more DPCs420for processing tasks allocated to the GPC350. In an embodiment, the pipeline manager410may configure at least one of the one or more DPCs420to implement at least a portion of a graphics rendering pipeline. For example, a DPC420may be configured to execute a vertex shader program on the programmable streaming multiprocessor (SM)440. The pipeline manager410may also be configured to route packets received from the work distribution unit325to the appropriate logical units within the GPC350. For example, some packets may be routed to fixed function hardware units in the PROP415and/or raster engine425while other packets may be routed to the DPCs420for processing by the primitive engine435or the SM440. In an embodiment, the pipeline manager410may configure at least one of the one or more DPCs420to implement a neural network model and/or a computing pipeline.

The PROP unit415is configured to route data generated by the raster engine425and the DPCs420to a Raster Operations (ROP) unit, described in more detail in conjunction withFIG. 4B. The PROP unit415may also be configured to perform optimizations for color blending, organize pixel data, perform address translations, and the like.

Each DPC420included in the GPC350includes an M-Pipe Controller (MPC)430, a primitive engine435, and one or more SMs440. The MPC430controls the operation of the DPC420, routing packets received from the pipeline manager410to the appropriate units in the DPC420. For example, packets associated with a vertex may be routed to the primitive engine435, which is configured to fetch vertex attributes associated with the vertex from the memory304. In contrast, packets associated with a shader program may be transmitted to the SM440.

The SM440comprises a programmable streaming processor that is configured to process tasks represented by a number of threads. Each SM440is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently. In an embodiment, the SM440implements a SIMD (Single-Instruction, Multiple-Data) architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. All threads in the group of threads execute the same instructions. In another embodiment, the SM440implements a SIMT (Single-Instruction, Multiple Thread) architecture where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but where individual threads in the group of threads are allowed to diverge during execution. In an embodiment, a program counter, call stack, and execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. When execution state is maintained for each individual thread, threads executing the same instructions may be converged and executed in parallel for maximum efficiency. The SM440will be described in more detail below in conjunction withFIG. 5A.

The MMU490provides an interface between the GPC350and the memory partition unit380. The MMU490may provide translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In an embodiment, the MMU490provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in the memory304.

FIG. 4Billustrates a memory partition unit380of the PPU300ofFIG. 3, in accordance with an embodiment. As shown inFIG. 4B, the memory partition unit380includes a Raster Operations (ROP) unit450, a level two (L2) cache460, and a memory interface470. The memory interface470is coupled to the memory304. Memory interface470may implement 32, 64, 128, 1024-bit data buses, or the like, for high-speed data transfer. In an embodiment, the PPU300incorporates one memory interface470per pair of memory partition units380, where each pair of memory partition units380is connected to a corresponding memory device304. For example, PPU300may be connected to up to Y memory devices304, such as high bandwidth memory stacks or graphics double-data-rate, version 5, synchronous dynamic random access memory, or other types of persistent storage.

In an embodiment, the memory interface470implements an HBM2 memory interface and Y equals half U. In an embodiment, the HBM2 memory stacks are located on the same physical package as the PPU300, providing substantial power and area savings compared with conventional GDDR5 SDRAM systems. In an embodiment, each HBM2 stack includes four memory dies and Y equals 4, with HBM2 stack including two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits.

In an embodiment, the memory304supports Single-Error Correcting Double-Error Detecting (SECDED) Error Correction Code (ECC) to protect data. ECC provides higher reliability for compute applications that are sensitive to data corruption. Reliability is especially important in large-scale cluster computing environments where PPUs300process very large datasets and/or run applications for extended periods.

In an embodiment, the PPU300implements a multi-level memory hierarchy. In an embodiment, the memory partition unit380supports a unified memory to provide a single unified virtual address space for CPU and PPU300memory, enabling data sharing between virtual memory systems. In an embodiment the frequency of accesses by a PPU300to memory located on other processors is traced to ensure that memory pages are moved to the physical memory of the PPU300that is accessing the pages more frequently. In an embodiment, the NVLink310supports address translation services allowing the PPU300to directly access a CPU's page tables and providing full access to CPU memory by the PPU300.

In an embodiment, copy engines transfer data between multiple PPUs300or between PPUs300and CPUs. The copy engines can generate page faults for addresses that are not mapped into the page tables. The memory partition unit380can then service the page faults, mapping the addresses into the page table, after which the copy engine can perform the transfer. In a conventional system, memory is pinned (e.g., non-pageable) for multiple copy engine operations between multiple processors, substantially reducing the available memory. With hardware page faulting, addresses can be passed to the copy engines without worrying if the memory pages are resident, and the copy process is transparent.

Data from the memory304or other system memory may be fetched by the memory partition unit380and stored in the L2 cache460, which is located on-chip and is shared between the various GPCs350. As shown, each memory partition unit380includes a portion of the L2 cache460associated with a corresponding memory device304. Lower level caches may then be implemented in various units within the GPCs350. For example, each of the SMs440may implement a level one (L1) cache. The L1 cache is private memory that is dedicated to a particular SM440. Data from the L2 cache460may be fetched and stored in each of the L1 caches for processing in the functional units of the SMs440. The L2 cache460is coupled to the memory interface470and the XBar370.

The ROP unit450performs graphics raster operations related to pixel color, such as color compression, pixel blending, and the like. The ROP unit450also implements depth testing in conjunction with the raster engine425, receiving a depth for a sample location associated with a pixel fragment from the culling engine of the raster engine425. The depth is tested against a corresponding depth in a depth buffer for a sample location associated with the fragment. If the fragment passes the depth test for the sample location, then the ROP unit450updates the depth buffer and transmits a result of the depth test to the raster engine425. It will be appreciated that the number of memory partition units380may be different than the number of GPCs350and, therefore, each ROP unit450may be coupled to each of the GPCs350. The ROP unit450tracks packets received from the different GPCs350and determines which GPC350that a result generated by the ROP unit450is routed to through the Xbar370. Although the ROP unit450is included within the memory partition unit380inFIG. 4B, in other embodiment, the ROP unit450may be outside of the memory partition unit380. For example, the ROP unit450may reside in the GPC350or another unit.

FIG. 5Aillustrates the streaming multi-processor440ofFIG. 4A, in accordance with an embodiment. As shown inFIG. 5A, the SM440includes an instruction cache505, one or more scheduler units510, a register file520, one or more processing cores550, one or more special function units (SFUs)552, one or more load/store units (LSUs)554, an interconnect network580, a shared memory/L1 cache570.

As described above, the work distribution unit325dispatches tasks for execution on the GPCs350of the PPU300. The tasks are allocated to a particular DPC420within a GPC350and, if the task is associated with a shader program, the task may be allocated to an SM440. The scheduler unit510receives the tasks from the work distribution unit325and manages instruction scheduling for one or more thread blocks assigned to the SM440. The scheduler unit510schedules thread blocks for execution as warps of parallel threads, where each thread block is allocated at least one warp. In an embodiment, each warp executes 32 threads. The scheduler unit510may manage a plurality of different thread blocks, allocating the warps to the different thread blocks and then dispatching instructions from the plurality of different cooperative groups to the various functional units (e.g., cores550, SFUs552, and LSUs554) during each clock cycle.

A dispatch unit515is configured to transmit instructions to one or more of the functional units. In the embodiment, the scheduler unit510includes two dispatch units515that enable two different instructions from the same warp to be dispatched during each clock cycle. In alternative embodiments, each scheduler unit510may include a single dispatch unit515or additional dispatch units515.

Each SM440includes a register file520that provides a set of registers for the functional units of the SM440. In an embodiment, the register file520is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file520. In another embodiment, the register file520is divided between the different warps being executed by the SM440. The register file520provides temporary storage for operands connected to the data paths of the functional units.

Each SM440comprises L processing cores550. In an embodiment, the SM440includes a large number (e.g., 128, etc.) of distinct processing cores550. Each core550may include a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes a floating point arithmetic logic unit and an integer arithmetic logic unit. In an embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. In an embodiment, the cores550include 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

Tensor cores configured to perform matrix operations, and, in an embodiment, one or more tensor cores are included in the cores550. In particular, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In an embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

In an embodiment, the matrix multiply inputs A and B are 16-bit floating point matrices, while the accumulation matrices C and D may be 16-bit floating point or 32-bit floating point matrices. Tensor Cores operate on 16-bit floating point input data with 32-bit floating point accumulation. The 16-bit floating point multiply requires 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with the other intermediate products for a 4×4×4 matrix multiply. In practice, Tensor Cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements. An API, such as CUDA 9 C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use Tensor Cores from a CUDA-C++ program. At the CUDA level, the warp-level interface assumes 16×16 size matrices spanning all 32 threads of the warp.

Each SM440also comprises M SFUs552that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like). In an embodiment, the SFUs552may include a tree traversal unit configured to traverse a hierarchical tree data structure. In an embodiment, the SFUs552may include texture unit configured to perform texture map filtering operations. In an embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texels) from the memory304and sample the texture maps to produce sampled texture values for use in shader programs executed by the SM440. In an embodiment, the texture maps are stored in the shared memory/L1 cache470. The texture units implement texture operations such as filtering operations using mip-maps (e.g., texture maps of varying levels of detail). In an embodiment, each SM340includes two texture units.

Each SM440also comprises N LSUs554that implement load and store operations between the shared memory/L1 cache570and the register file520. Each SM440includes an interconnect network580that connects each of the functional units to the register file520and the LSU554to the register file520, shared memory/L1 cache570. In an embodiment, the interconnect network580is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file520and connect the LSUs554to the register file and memory locations in shared memory/L1 cache570.

The shared memory/L1 cache570is an array of on-chip memory that allows for data storage and communication between the SM440and the primitive engine435and between threads in the SM440. In an embodiment, the shared memory/L1 cache570comprises 128 KB of storage capacity and is in the path from the SM440to the memory partition unit380. The shared memory/L1 cache570can be used to cache reads and writes. One or more of the shared memory/L1 cache570, L2 cache460, and memory304are backing stores.

Combining data cache and shared memory functionality into a single memory block provides the best overall performance for both types of memory accesses. The capacity is usable as a cache by programs that do not use shared memory. For example, if shared memory is configured to use half of the capacity, texture and load/store operations can use the remaining capacity. Integration within the shared memory/L1 cache570enables the shared memory/L1 cache570to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data.

When configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. Specifically, the fixed function graphics processing units shown inFIG. 3, are bypassed, creating a much simpler programming model. In the general purpose parallel computation configuration, the work distribution unit325assigns and distributes blocks of threads directly to the DPCs420. The threads in a block execute the same program, using a unique thread ID in the calculation to ensure each thread generates unique results, using the SM440to execute the program and perform calculations, shared memory/L1 cache570to communicate between threads, and the LSU554to read and write global memory through the shared memory/L1 cache570and the memory partition unit380. When configured for general purpose parallel computation, the SM440can also write commands that the scheduler unit320can use to launch new work on the DPCs420.

The PPU300may be included in a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and the like. In an embodiment, the PPU300is embodied on a single semiconductor substrate. In another embodiment, the PPU300is included in a system-on-a-chip (SoC) along with one or more other devices such as additional PPUs300, the memory204, a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like.

In an embodiment, the PPU300may be included on a graphics card that includes one or more memory devices304. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, the PPU300may be an integrated graphics processing unit (iGPU) or parallel processor included in the chipset of the motherboard.

Exemplary Computing System

FIG. 5Bis a conceptual diagram of a processing system500implemented using the PPU300ofFIG. 3, in accordance with an embodiment. The exemplary system565may be configured to implement the methods130,160, and230shown inFIGS. 1D, 1F, and 2B, respectively. The processing system500includes a CPU530, switch510, and multiple PPUs300each and respective memories304. The NVLink310provides high-speed communication links between each of the PPUs300. Although a particular number of NVLink310and interconnect302connections are illustrated inFIG. 5B, the number of connections to each PPU300and the CPU530may vary. The switch510interfaces between the interconnect302and the CPU530. The PPUs300, memories304, and NVLinks310may be situated on a single semiconductor platform to form a parallel processing module525. In an embodiment, the switch510supports two or more protocols to interface between various different connections and/or links.

In another embodiment (not shown), the NVLink310provides one or more high-speed communication links between each of the PPUs300and the CPU530and the switch510interfaces between the interconnect302and each of the PPUs300. The PPUs300, memories304, and interconnect302may be situated on a single semiconductor platform to form a parallel processing module525. In yet another embodiment (not shown), the interconnect302provides one or more communication links between each of the PPUs300and the CPU530and the switch510interfaces between each of the PPUs300using the NVLink310to provide one or more high-speed communication links between the PPUs300. In another embodiment (not shown), the NVLink310provides one or more high-speed communication links between the PPUs300and the CPU530through the switch510. In yet another embodiment (not shown), the interconnect302provides one or more communication links between each of the PPUs300directly. One or more of the NVLink310high-speed communication links may be implemented as a physical NVLink interconnect or either an on-chip or on-die interconnect using the same protocol as the NVLink310.

In an embodiment, the signaling rate of each NVLink310is 20 to 25 Gigabits/second and each PPU300includes six NVLink310interfaces (as shown inFIG. 5B, five NVLink310interfaces are included for each PPU300). Each NVLink310provides a data transfer rate of 25 Gigabytes/second in each direction, with six links providing 300 Gigabytes/second. The NVLinks310can be used exclusively for PPU-to-PPU communication as shown inFIG. 5B, or some combination of PPU-to-PPU and PPU-to-CPU, when the CPU530also includes one or more NVLink310interfaces.

In an embodiment, the NVLink310allows direct load/store/atomic access from the CPU530to each PPU's300memory304. In an embodiment, the NVLink310supports coherency operations, allowing data read from the memories304to be stored in the cache hierarchy of the CPU530, reducing cache access latency for the CPU530. In an embodiment, the NVLink310includes support for Address Translation Services (ATS), allowing the PPU300to directly access page tables within the CPU530. One or more of the NVLinks310may also be configured to operate in a low-power mode.

FIG. 5Cillustrates an exemplary system565in which the various architecture and/or functionality of the various previous embodiments may be implemented. The exemplary system565may be configured to implement the methods130,160, and230shown inFIGS. 1D, 1F, and 2B, respectively.

As shown, a system565is provided including at least one central processing unit530that is connected to a communication bus575. The communication bus575may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). The system565also includes a main memory540. Control logic (software) and data are stored in the main memory540which may take the form of random access memory (RAM).

The system565also includes input devices560, the parallel processing system525, and display devices545, e.g. a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display or the like. User input may be received from the input devices560, e.g., keyboard, mouse, touchpad, microphone, and the like. Each of the foregoing modules and/or devices may even be situated on a single semiconductor platform to form the system565. Alternately, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user.

Further, the system565may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) through a network interface535for communication purposes.

Computer programs, or computer control logic algorithms, may be stored in the main memory540and/or the secondary storage. Such computer programs, when executed, enable the system565to perform various functions. The memory540, the storage, and/or any other storage are possible examples of computer-readable media.

The architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system. For example, the system565may take the form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device, a television, workstation, game consoles, embedded system, and/or any other type of logic.

Graphics Processing Pipeline

In an embodiment, the PPU300comprises a graphics processing unit (GPU). The PPU300is configured to receive commands that specify shader programs for processing graphics data. Graphics data may be defined as a set of primitives such as points, lines, triangles, quads, triangle strips, and the like. Typically, a primitive includes data that specifies a number of vertices for the primitive (e.g., in a model-space coordinate system) as well as attributes associated with each vertex of the primitive. The PPU300can be configured to process the graphics primitives to generate a frame buffer (e.g., pixel data for each of the pixels of the display).

An application writes model data for a scene (e.g., a collection of vertices and attributes) to a memory such as a system memory or memory304. The model data defines each of the objects that may be visible on a display. The application then makes an API call to the driver kernel that requests the model data to be rendered and displayed. The driver kernel reads the model data and writes commands to the one or more streams to perform operations to process the model data. The commands may reference different shader programs to be implemented on the SMs440of the PPU300including one or more of a vertex shader, hull shader, domain shader, geometry shader, and a pixel shader. For example, one or more of the SMs440may be configured to execute a vertex shader program that processes a number of vertices defined by the model data. In an embodiment, the different SMs440may be configured to execute different shader programs concurrently. For example, a first subset of SMs440may be configured to execute a vertex shader program while a second subset of SMs440may be configured to execute a pixel shader program. The first subset of SMs440processes vertex data to produce processed vertex data and writes the processed vertex data to the L2 cache460and/or the memory304. After the processed vertex data is rasterized (e.g., transformed from three-dimensional data into two-dimensional data in screen space) to produce fragment data, the second subset of SMs440executes a pixel shader to produce processed fragment data, which is then blended with other processed fragment data and written to the frame buffer in memory304. The vertex shader program and pixel shader program may execute concurrently, processing different data from the same scene in a pipelined fashion until all of the model data for the scene has been rendered to the frame buffer. Then, the contents of the frame buffer are transmitted to a display controller for display on a display device.

FIG. 6is a conceptual diagram of a graphics processing pipeline600implemented by the PPU300ofFIG. 3, in accordance with an embodiment. The graphics processing pipeline600is an abstract flow diagram of the processing steps implemented to generate 2D computer-generated images from 3D geometry data. As is well-known, pipeline architectures may perform long latency operations more efficiently by splitting up the operation into a plurality of stages, where the output of each stage is coupled to the input of the next successive stage. Thus, the graphics processing pipeline600receives input data601that is transmitted from one stage to the next stage of the graphics processing pipeline600to generate output data602. In an embodiment, the graphics processing pipeline600may represent a graphics processing pipeline defined by the OpenGL® API. As an option, the graphics processing pipeline600may be implemented in the context of the functionality and architecture of the previous Figures and/or any subsequent Figure(s).

As shown inFIG. 6, the graphics processing pipeline600comprises a pipeline architecture that includes a number of stages. The stages include, but are not limited to, a data assembly stage610, a vertex shading stage620, a primitive assembly stage630, a geometry shading stage640, a viewport scale, cull, and clip (VSCC) stage650, a rasterization stage660, a fragment shading stage670, and a raster operations stage680. In an embodiment, the input data601comprises commands that configure the processing units to implement the stages of the graphics processing pipeline600and geometric primitives (e.g., points, lines, triangles, quads, triangle strips or fans, etc.) to be processed by the stages. The output data602may comprise pixel data (e.g., color data) that is copied into a frame buffer or other type of surface data structure in a memory.

The data assembly stage610receives the input data601that specifies vertex data for high-order surfaces, primitives, or the like. The data assembly stage610collects the vertex data in a temporary storage or queue, such as by receiving a command from the host processor that includes a pointer to a buffer in memory and reading the vertex data from the buffer. The vertex data is then transmitted to the vertex shading stage620for processing.

The vertex shading stage620processes vertex data by performing a set of operations (e.g., a vertex shader or a program) once for each of the vertices. Vertices may be, e.g., specified as a 4-coordinate vector (e.g., <x, y, z, w>) associated with one or more vertex attributes (e.g., color, texture coordinates, surface normal, etc.). The vertex shading stage620may manipulate individual vertex attributes such as position, color, texture coordinates, and the like. In other words, the vertex shading stage620performs operations on the vertex coordinates or other vertex attributes associated with a vertex. Such operations commonly including lighting operations (e.g., modifying color attributes for a vertex) and transformation operations (e.g., modifying the coordinate space for a vertex). For example, vertices may be specified using coordinates in an object-coordinate space, which are transformed by multiplying the coordinates by a matrix that translates the coordinates from the object-coordinate space into a world space or a normalized-device-coordinate (NCD) space. The vertex shading stage620generates transformed vertex data that is transmitted to the primitive assembly stage630.

The primitive assembly stage630collects vertices output by the vertex shading stage620and groups the vertices into geometric primitives for processing by the geometry shading stage640. For example, the primitive assembly stage630may be configured to group every three consecutive vertices as a geometric primitive (e.g., a triangle) for transmission to the geometry shading stage640. In some embodiments, specific vertices may be reused for consecutive geometric primitives (e.g., two consecutive triangles in a triangle strip may share two vertices). The primitive assembly stage630transmits geometric primitives (e.g., a collection of associated vertices) to the geometry shading stage640.

The geometry shading stage640processes geometric primitives by performing a set of operations (e.g., a geometry shader or program) on the geometric primitives. Tessellation operations may generate one or more geometric primitives from each geometric primitive. In other words, the geometry shading stage640may subdivide each geometric primitive into a finer mesh of two or more geometric primitives for processing by the rest of the graphics processing pipeline600. The geometry shading stage640transmits geometric primitives to the viewport SCC stage650.

In an embodiment, the graphics processing pipeline600may operate within a streaming multiprocessor and the vertex shading stage620, the primitive assembly stage630, the geometry shading stage640, the fragment shading stage670, and/or hardware/software associated therewith, may sequentially perform processing operations. Once the sequential processing operations are complete, in an embodiment, the viewport SCC stage650may utilize the data. In an embodiment, primitive data processed by one or more of the stages in the graphics processing pipeline600may be written to a cache (e.g. L1 cache, a vertex cache, etc.). In this case, in an embodiment, the viewport SCC stage650may access the data in the cache. In an embodiment, the viewport SCC stage650and the rasterization stage660are implemented as fixed function circuitry.

The viewport SCC stage650performs viewport scaling, culling, and clipping of the geometric primitives. Each surface being rendered to is associated with an abstract camera position. The camera position represents a location of a viewer looking at the scene and defines a viewing frustum that encloses the objects of the scene. The viewing frustum may include a viewing plane, a rear plane, and four clipping planes. Any geometric primitive entirely outside of the viewing frustum may be culled (e.g., discarded) because the geometric primitive will not contribute to the final rendered scene. Any geometric primitive that is partially inside the viewing frustum and partially outside the viewing frustum may be clipped (e.g., transformed into a new geometric primitive that is enclosed within the viewing frustum. Furthermore, geometric primitives may each be scaled based on a depth of the viewing frustum. All potentially visible geometric primitives are then transmitted to the rasterization stage660.

The rasterization stage660converts the 3D geometric primitives into 2D fragments (e.g. capable of being utilized for display, etc.). The rasterization stage660may be configured to utilize the vertices of the geometric primitives to setup a set of plane equations from which various attributes can be interpolated. The rasterization stage660may also compute a coverage mask for a plurality of pixels that indicates whether one or more sample locations for the pixel intercept the geometric primitive. In an embodiment, z-testing may also be performed to determine if the geometric primitive is occluded by other geometric primitives that have already been rasterized. The rasterization stage660generates fragment data (e.g., interpolated vertex attributes associated with a particular sample location for each covered pixel) that are transmitted to the fragment shading stage670.

The fragment shading stage670processes fragment data by performing a set of operations (e.g., a fragment shader or a program) on each of the fragments. The fragment shading stage670may generate pixel data (e.g., color values) for the fragment such as by performing lighting operations or sampling texture maps using interpolated texture coordinates for the fragment. The fragment shading stage670generates pixel data that is transmitted to the raster operations stage680.

The raster operations stage680may perform various operations on the pixel data such as performing alpha tests, stencil tests, and blending the pixel data with other pixel data corresponding to other fragments associated with the pixel. When the raster operations stage680has finished processing the pixel data (e.g., the output data602), the pixel data may be written to a render target such as a frame buffer, a color buffer, or the like.

It will be appreciated that one or more additional stages may be included in the graphics processing pipeline600in addition to or in lieu of one or more of the stages described above. Various implementations of the abstract graphics processing pipeline may implement different stages. Furthermore, one or more of the stages described above may be excluded from the graphics processing pipeline in some embodiments (such as the geometry shading stage640). Other types of graphics processing pipelines are contemplated as being within the scope of the present disclosure. Furthermore, any of the stages of the graphics processing pipeline600may be implemented by one or more dedicated hardware units within a graphics processor such as PPU300. Other stages of the graphics processing pipeline600may be implemented by programmable hardware units such as the SM440of the PPU300.

The graphics processing pipeline600may be implemented via an application executed by a host processor, such as a CPU. In an embodiment, a device driver may implement an application programming interface (API) that defines various functions that can be utilized by an application in order to generate graphical data for display. The device driver is a software program that includes a plurality of instructions that control the operation of the PPU300. The API provides an abstraction for a programmer that lets a programmer utilize specialized graphics hardware, such as the PPU300, to generate the graphical data without requiring the programmer to utilize the specific instruction set for the PPU300. The application may include an API call that is routed to the device driver for the PPU300. The device driver interprets the API call and performs various operations to respond to the API call. In some instances, the device driver may perform operations by executing instructions on the CPU. In other instances, the device driver may perform operations, at least in part, by launching operations on the PPU300utilizing an input/output interface between the CPU and the PPU300. In an embodiment, the device driver is configured to implement the graphics processing pipeline600utilizing the hardware of the PPU300.

Various programs may be executed within the PPU300in order to implement the various stages of the graphics processing pipeline600. For example, the device driver may launch a kernel on the PPU300to perform the vertex shading stage620on one SM440(or multiple SMs440). The device driver (or the initial kernel executed by the PPU400) may also launch other kernels on the PPU400to perform other stages of the graphics processing pipeline600, such as the geometry shading stage640and the fragment shading stage670. In addition, some of the stages of the graphics processing pipeline600may be implemented on fixed unit hardware such as a rasterizer or a data assembler implemented within the PPU400. It will be appreciated that results from one kernel may be processed by one or more intervening fixed function hardware units before being processed by a subsequent kernel on an SM440.

Machine Learning

Neural networks rely heavily on matrix math operations, and complex multi-layered networks require tremendous amounts of floating-point performance and bandwidth for both efficiency and speed. With thousands of processing cores, optimized for matrix math operations, and delivering tens to hundreds of TFLOPS of performance, the PPU300is a computing platform capable of delivering performance required for deep neural network-based artificial intelligence and machine learning applications.

It is noted that the techniques described herein may be embodied in executable instructions stored in a computer readable medium for use by or in connection with a processor-based instruction execution machine, system, apparatus, or device. It will be appreciated by those skilled in the art that, for some embodiments, various types of computer-readable media can be included for storing data. As used herein, a “computer-readable medium” includes one or more of any suitable media for storing the executable instructions of a computer program such that the instruction execution machine, system, apparatus, or device may read (or fetch) the instructions from the computer-readable medium and execute the instructions for carrying out the described embodiments. Suitable storage formats include one or more of an electronic, magnetic, optical, and electromagnetic format. A non-exhaustive list of conventional exemplary computer-readable medium includes: a portable computer diskette; a random-access memory (RAM); a read-only memory (ROM); an erasable programmable read only memory (EPROM); a flash memory device; and optical storage devices, including a portable compact disc (CD), a portable digital video disc (DVD), and the like.

It should be understood that the arrangement of components illustrated in the attached Figures are for illustrative purposes and that other arrangements are possible. For example, one or more of the elements described herein may be realized, in whole or in part, as an electronic hardware component. Other elements may be implemented in software, hardware, or a combination of software and hardware. Moreover, some or all of these other elements may be combined, some may be omitted altogether, and additional components may be added while still achieving the functionality described herein. Thus, the subject matter described herein may be embodied in many different variations, and all such variations are contemplated to be within the scope of the claims.

To facilitate an understanding of the subject matter described herein, many aspects are described in terms of sequences of actions. It will be recognized by those skilled in the art that the various actions may be performed by specialized circuits or circuitry, by program instructions being executed by one or more processors, or by a combination of both. The description herein of any sequence of actions is not intended to imply that the specific order described for performing that sequence must be followed. All methods described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context.

The use of the terms “a” and “an” and “the” and similar references in the context of describing the subject matter (particularly in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The use of the term “at least one” followed by a list of one or more items (for example, “at least one of A and B”) is to be construed to mean one item selected from the listed items (A or B) or any combination of two or more of the listed items (A and B), unless otherwise indicated herein or clearly contradicted by context. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation, as the scope of protection sought is defined by the claims as set forth hereinafter together with any equivalents thereof. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illustrate the subject matter and does not pose a limitation on the scope of the subject matter unless otherwise claimed. The use of the term “based on” and other like phrases indicating a condition for bringing about a result, both in the claims and in the written description, is not intended to foreclose any other conditions that bring about that result. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention as claimed.