Apparatuses including contacts in a peripheral region

Apparatuses and methods for manufacturing semiconductor memory devices are described. An example method includes: forming first interconnects; forming first dielectric layers above the first interconnects in a peripheral region; removing portions of the first dielectric layers to form first openings through the first dielectric layers in the peripheral region to expose the first interconnects at bottoms of the first openings; depositing first conductive material in the peripheral region to form first contact portions in the first openings; forming second dielectric layers on the first dielectric layers and the first contact portions in the peripheral region; removing second portions of the second dielectric layers to form second openings through the second dielectric layers to expose the first contact portions at bottoms of the second openings; depositing second conductive material to form a plurality of second contact portions in the corresponding first openings; and forming second interconnects on the second contact portions.

BACKGROUND

High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. To reduce chip size, a distance between signal lines has become shorter. A semiconductor device may also include contacts, (e.g., vias) in a peripheral region. The contacts may transmit signals between transistors on the substrate and signal lines in upper layers of the semiconductor device. To form contacts, opening are created by etching layers above the substrate. Recently, contacts have become taller because of the increased height of the semiconductor devices. The semiconductor devices often include several layers of conductive, semi-conductive, and dielectric materials to form the various circuits of the semiconductor device. Due to taller height of the multiple layers of conductive, semi-conductive, and dielectric materials, openings (e.g., openings for vias, contacts, etc.) have become deeper. Deeper openings present challenges in forming (e.g., etching) the openings. For example, deeper etching results in openings with a larger cross-section. As a result, adjacent contacts with a larger cross-section created in the openings tend to become a short circuit, which is undesirable.

DETAILED DESCRIPTION

Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. Other embodiments may be utilized, and structure, logical and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

FIG.1is a diagram of a top view of a structure of a portion100of a semiconductor device100in accordance with an embodiment of the present disclosure.FIG.2Ais a diagram of a vertical cross-sectional view of a structure of another portion200including the portion100of a semiconductor device in accordance with an embodiment of the present disclosure.FIG.2Bis a diagram of another vertical cross-sectional view of the structure of the other portion200including the portion100of the semiconductor device in accordance with the embodiment of the present disclosure.

In some embodiments, the portion100of the semiconductor device inFIG.1may be included in a peripheral region204of the semiconductor device200. The semiconductor device100may include a substrate110. In the following description, the position “above” is oriented with the substrate110at a bottom of the semiconductor device100. In some embodiments, the substrate110may extend in a plane that may include a direction112and another direction114different from the direction112. In some embodiments, the direction114may be perpendicular to the direction112.FIG.1may be viewed from above, that is a direction perpendicular to the directions112and114. The vertical cross sectional view of the portion200inFIG.2Ais a view along the segments V1in the direction112. The other vertical cross sectional view of the portion200inFIG.2Bis a view along the segments V2in the direction114.

The semiconductor device100may include interconnects102a-102ddisposed above the substrate110. In some embodiments, the interconnects102a-102dmay extend in parallel to one another in the direction112. In some embodiments, the interconnects102a-102dmay include conductive material, such as copper or aluminum, for example. In some embodiments, the interconnects102a-102dmay be formed in a wiring layer (e.g., a metal1 layer). The semiconductor device100may include interconnects104a-104dabove the interconnect102a-102d. In some embodiments, the interconnects104a-104dmay extend in parallel to one another in the direction114, perpendicular to the direction112. In some embodiments, the interconnects104a-104dmay include conductive material, such as copper or aluminum, for example. In some embodiments, the interconnects104a-104dmay be formed in another wiring layer (e.g., a metal2 layer).

The semiconductor device100may include contacts that couple interconnects102a-102dto interconnects104a-104d. Each of the contacts may include conductive portions that extend through various layers between the interconnects102a-102dand interconnects104a-104d. For example, contacts214a-214hare shown inFIGS.2A and2B. The contacts214a-214hinclude contact portions106a-106gand contact portions108a-108g, respectively.

Each of the contact portions106a-106gmay be disposed on one of the interconnects102a-102d. For example, the contact portions106a,106c, and106emay be disposed on the interconnect102a. The contact portion106gmay be disposed on the interconnect102b. The contact portions106b,106d, and106fmay be disposed on the interconnect102c. The contact portion106hmay be disposed on the interconnect102d.

As shown in the top view ofFIG.1, each of the contact portions106a-106hhas a cross section. The cross section of each of the contact portions106a-106hhas a length in the direction112and a width DL1less than the length in the direction114. In some embodiments, the cross section may have an oval shape. The cross section may have a long diameter DL1in the direction112and a short diameter in the direction114. In some embodiments, the short diameter is less than a sum of a width W1of each of the interconnects102a-102dand an interval Int1between adjacent interconnects of the interconnects102a-102d. In some embodiments, the short diameter of the cross section may be less than the width W1of each of the interconnects102a-102d. Thus, the adjacent interconnects of the interconnects102a-102dmay not be short-circuited from one another through the contact portions106a-106h.

Each of the contact portions108a-108gmay be disposed on a corresponding contact portion of the contact portions106a-106g. The interconnects104a-104dmay be disposed on one or more corresponding contact portions of the contact portions108a-108g. For example, the interconnect104amay be disposed on the contact portions108aand108b. The interconnect104bmay be disposed on the contact portions108cand108d. The interconnect104cmay be disposed on the contact portions108eand108f. The interconnect104dmay be disposed on the contact portions108gand108h.

As shown in the top view ofFIG.1, each of the contact portions108a-108hhas a cross section. The cross section of each of the contact portions108a-108hhas a length DL2in the direction114and a width less than the length in the direction112. In some embodiments, the cross section of each of the contact portions108a-108hmay have an oval shape. The cross section of each of the contact portions108a-108hmay have a long diameter DL2in the direction114and a short diameter in the direction112. In some embodiments, the short diameter is less than a sum of a width W2of each of the interconnects104a-104dand an interval Int2between adjacent interconnects of the interconnects104a-104d. In some embodiments, the short diameter of the cross section of each of the contact portions108a-108hmay be less than the width W2of each of the interconnects104a-104d. The adjacent contact portions, such as the contact portions108aand108c,108cand108e,108band108d,108dand108fmay be apart from each other. Thus, the adjacent interconnects of the interconnects104a-104dmay not be short-circuited from one another through the contact portions108a-108h.

The contact portions106a-106hand the contact portions108a-108hmay include conductive material. In some embodiments, the contact portions106a-106hand the contact portions108a-108hmay include the same conductive material. In some embodiments, the conductive material may be tungsten. In some embodiments, the contact portions106a-106hand the contact portions108a-108hmay include different conductive materials.

In some embodiment, the semiconductor device100may be a memory device (e.g., a dynamic random access memory (DRAM)) including memory cells206inFIG.2A, for example.

The semiconductor device100may further include a memory array region202. The memory array region202may include the memory cells206. Each memory cell of the memory cells206may include a transistor (e.g., a transistor212aor a transistor212b) on the substrate110. In some embodiments, the transistor (e.g., a transistor212aor a transistor212b) may be a metal-oxide-semiconductor field-effect transistor (MOSFET) in the DRAM, for example.

Each memory cell of the memory cells206may include a capacitor (e.g., the capacitor210aor the capacitor210bofFIG.2A) on the corresponding transistor (e.g., the transistor212aor the transistor212b, respectively). Each capacitor (e.g., the capacitor210aor the capacitor210b) may store a value representing a binary data bit. In some embodiments, each capacitor (e.g., the capacitor210aor the capacitor210b) may have a pillar structure extending in a direction perpendicular to the substrate110. Each capacitor (e.g., the capacitor210aor the capacitor210b) may include a lower capacitor electrode at one end of the pillar structure and an upper capacitor electrode at another end of the pillar structure. The lower capacitor electrode of each capacitor (e.g., the capacitor210aor the capacitor210b) may be coupled to the corresponding transistor (e.g., the transistor212aor the transistor212b, respectively).

The semiconductor device100may include a power supply line208that may provide a power supply voltage. The power supply line208may include conductive material, such as tungsten, for example. The power supply line208may include a portion in the memory array region202and another portion in the peripheral region204. The portion of the power supply line208in the memory array region202is disposed above upper capacitor electrodes of the memory cells206and coupled to the upper capacitor electrodes of the memory cells206. The other portion of the power supply line208in the peripheral region204is disposed under the interconnects102a-102d. In some embodiments, the interconnects102a-102dmay be disposed on the other portion of the power supply line208in the peripheral region204. The contact portions106a-106hmay be disposed on the interconnects102a-102d. In some embodiments, a height of the portion of the power supply line208in the memory array region202and a height of the contact portions106a-106hmay be substantially the same.

The semiconductor device100may include a dielectric layer216above the portion of the power supply line208in the peripheral region204. In some embodiments, a top surface of the dielectric layer may have the same height as the height of the portion of the power supply line208in the memory array region202. The contact portions106a-106hmay be disposed in the dielectric layer216. The semiconductor device100may include a dielectric layer218. The dielectric layer218may be disposed across the memory array region202and the peripheral region204. A portion of the dielectric layer218in the peripheral region204may be disposed on the dielectric layer216and the contact portions106a-106h. A portion of the dielectric layer218in the memory array region202may be disposed on the portion of the power supply line208in the memory array region202. In some embodiments, the contact portions108a-108hmay be disposed in the dielectric layer218. In some embodiments, the dielectric layers216and218may include silicon oxide (SiO2).

The following describes methods of forming apparatuses, such as the semiconductor device100according to the embodiments with reference toFIG.3AtoFIG.6B. The dimensions and the ratios of dimensions of each portion in each drawing do not necessarily coincide with the dimensions and the ratios of dimensions of the actual semiconductor device.

FIG.3Ais a diagram of a vertical cross-sectional view of one schematic structure of a portion300of a semiconductor device100in accordance with an embodiment of the present disclosure.FIG.3Bis a diagram of another vertical cross-sectional view of the one schematic structure of the portion300of the semiconductor device100in accordance with the embodiment of the present disclosure. The vertical cross sectional view of the portion300inFIG.3Ais a view in the direction114. The other vertical cross sectional view of the portion300inFIG.3Bis a view in the direction112. In some embodiments, the portion300of the semiconductor device100may be an intermediate structure that is used to fabricate the portion200ofFIGS.2A and2B.

The portion300inFIG.3Aincludes the memory array region202and the peripheral region204of the semiconductor device100. In some embodiments, the semiconductor device100may include the substrate110across the memory array region202and the peripheral region204. In some embodiments, the substrate110may include a single-crystal silicon, for example.

In some embodiments, the portion300may include the memory cells206in the memory array region202ofFIG.3A. As described earlier with reference toFIG.2A, each memory cell of the memory cells206may include a transistor (e.g., the transistor212aor the transistor212bofFIG.2A) on the substrate110and a corresponding capacitor (e.g., the capacitor210aor the capacitor210bofFIG.2A) on the transistor. In some embodiments, conductive material may be deposited in the memory array region202and the peripheral region204. The conductive material may be, for example, tungsten. The conductive material may be deposited on the substrate110in the peripheral region204and above the capacitors, including the capacitors210aand210b, of the memory cells206in the memory array region202. The power supply line208may be formed from the deposited conductive material.

In some embodiments, the conductive material may be deposited concurrently in the memory array region202and the peripheral region204. Thus, the power supply line208may be formed on the substrate110in the peripheral region204and above the capacitors of the memory cells206in the memory array region202to be coupled to upper capacitor electrodes of the memory cells206.

FIG.4Ais a diagram of a vertical cross-sectional view of one schematic structure of a portion400of a semiconductor device100in accordance with an embodiment of the present disclosure.FIG.4Bis a diagram of another vertical cross-sectional view of the one schematic structure of the portion400of the semiconductor device100in accordance with the embodiment of the present disclosure. The vertical cross sectional view of the portion400inFIG.4Ais a view in the direction114. The other vertical cross sectional view of the portion400inFIG.4Bis a view in the direction112. In some embodiments, the portion400of the semiconductor device100may be an intermediate structure that is used to fabricate the portion200ofFIGS.2A and2B.

The portion400includes the memory array region202and the peripheral region204of the semiconductor device100. A dielectric layer402may be disposed on the power supply line208in the peripheral region204. In some embodiments, the dielectric layer402may include dielectric material. The dielectric material may include, for example, silicon oxide (SiO2). The dielectric material may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). In some embodiments, the interconnects102a-102dmay be formed in the dielectric layer402in the peripheral region204. In some embodiments, the conductive material may be deposited and excessive portions of the conductive material around the interconnects102a-102dmay be removed. Then dielectric material may be deposited to form the dielectric layer402. The dielectric layer402may cover the interconnects102a-102d, and a top portion of the dielectric layer402may be removed to expose top surfaces of the interconnects102a-102d. In other embodiments, the dielectric layer402may be formed and openings may be provided in the dielectric layer402to form the interconnects102a-102din the openings. Thus, in some embodiments, the interconnects102a-102dmay be disposed above the power supply line208in the peripheral region204.

The conductive material may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). The conductive material may be, for example, copper or aluminum. As shown inFIG.4A, adjacent interconnects of the interconnects102a-102dmay be spaced apart from one another with an interval. The interconnects102a-102dmay be insulated from one another by the dielectric layer402. As shown inFIG.4B, the interconnects102a-102dmay extend over the power supply line208in the peripheral region204that may extend in the direction112.

FIG.5Ais a diagram of a vertical cross-sectional view of one schematic structure of a portion500of a semiconductor device100in accordance with an embodiment of the present disclosure.FIG.5Bis a diagram of another vertical cross-sectional view of the one schematic structure of the portion500of the semiconductor device100in accordance with the embodiment of the present disclosure. The vertical cross sectional view of the portion500inFIG.5Ais a view in the direction114. The other vertical cross sectional view of the portion500inFIG.5Bis a view in the direction112. In some embodiments, the portion500of the semiconductor device100may be an intermediate structure that is used to fabricate the portion200ofFIGS.2A and2B.

One or more dielectric layers502may be formed above the interconnects102a-102dand the dielectric layers402. In some embodiments, the dielectric layer216ofFIGS.2A and2Bmay include the dielectric layer402and the one or more dielectric layers502. In some embodiments, the one or more dielectric layers502may include dielectric material. The dielectric material may include, for example, silicon oxide (SiO2). The dielectric material may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). In some embodiments, a height508of a top surface of the one or more dielectric layers502from the substrate110and a height510of the power supply line208from the substrate110in the memory array region202may be substantially the same.

Portions of the one or more dielectric layers502may be removed to form openings. In some embodiments, removing the portions of the one or more dielectric layers502may be performed by photopatterning a mask and dry-etching a pattern in the mask to form the openings.FIG.5Cis a schematic diagram of a mask506in accordance with an embodiment of the present disclosure. In some embodiments, the mask506may be disposed above the dielectric layer502. For example, using lithography, the mask506may be disposed including a pattern of holes504a-504h. The holes504a-504hmay correspond to cross sections of the contact portions106a-106h. In some embodiments, the holes504a-504hmay be in an oval shape. In some embodiments, each of the holes504a-04hmay have a long diameter in the direction112. The holes504a,504cand504emay be disposed above the interconnect102a. The holes504gmay be disposed above the interconnect102b. The holes504b,504dand504fmay be disposed above the interconnect102c. The hole504hmay be disposed above the interconnect102d.

Dry-etching through the holes504ato504hmay be performed to remove the portions of the one or more dielectric layers502. The portions of one or more dielectric layers502under the holes504a-504hnot covered by the mask506may be exposed for etching. In some embodiments, dry etching may be performed until the etching is stopped by the interconnects102a-102d. Thus, the portions of one or more dielectric layers502under the holes504a-504hmay be removed and the openings may be formed. The openings may expose the interconnects102a-102dat bottoms of the openings. In post-etching process (e.g., dry ashing and wet cleansing), the mask506may be removed.

In some embodiments, conductive material may be deposited on the one or more dielectric layers502in the openings to form the contact portions106a-106hin the openings. Forming the contact portions106a-106hin the holes504a-504hresult in the contact portions106a-106hhaving an oval shape with a long diameter DL1in the direction112as shown inFIG.2B. The conductive material may be, for example, tungsten. The conductive material may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). The contact portions106a-106hmay be disposed on the interconnects102a-102d. In some embodiments, a height510of the portion of the power supply line208in the memory array region202and a height508of the contact portions106a-106hmay be substantially the same.

FIG.6Ais a diagram of a vertical cross-sectional view of one schematic structure of a portion600of a semiconductor device100in accordance with an embodiment of the present disclosure.FIG.6Bis a diagram of another vertical cross-sectional view of the one schematic structure of the portion600of the semiconductor device100in accordance with the embodiment of the present disclosure. The vertical cross sectional view of the portion600inFIG.6Ais a view in the direction114. The other vertical cross sectional view of the portion600inFIG.6Bis a view in the direction112. In some embodiments, the portion600of the semiconductor device100may be an intermediate structure that is used to fabricate the portion200ofFIGS.2A and2B.

One or more dielectric layers218may be formed above the contact portions106a-106hand the one or more dielectric layers502in the peripheral region204, and on the power supply line208in the memory array region202. In some embodiments, the dielectric layer218may include dielectric material. The dielectric material may include, for example, silicon oxide (SiO2). The dielectric material may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

Portions of the one or more dielectric layers218may be removed to form openings. In some embodiments, removing the portions of the one or more dielectric layers218may be performed by photopatterning a mask and dry-etching a pattern in the mask to form the openings.FIG.6Cis a schematic diagram of a mask602in accordance with an embodiment of the present disclosure. In some embodiments, the mask602may be disposed above the dielectric layer218. For example, using a lithography, the mask602may be disposed including a pattern of holes604a-604h. The holes604a-604hmay correspond to cross sections of the contact portions108a-108h. In some embodiments, the holes604a-604hmay be in an oval shape. In some embodiments, each of the holes604a-604hmay have a long diameter in the direction114. The holes604a,604cand604emay be disposed above the interconnect102a. The holes604gmay be disposed above the interconnect102b. The holes604b,604dand604fmay be disposed above the interconnect102c. The hole604hmay be disposed above the interconnect102d.

Dry-etching through the holes604a-604hmay be performed to remove the portions of the one or more dielectric layers218. The portions of one or more dielectric layers218under the holes604a-604hnot covered by the mask602may be exposed for etching. In some embodiments, dry etching may be performed until the etching is stopped by the contacts. Thus, the portions of one or more dielectric layers502under the holes504a-504hmay be removed and the openings may be formed. The openings may expose the contact portions106a-106hat bottoms of the openings. In post-etching process (e.g., dry ashing and wet cleansing), the mask602may be removed.

In some embodiments, conductive material may be deposited on the one or more dielectric layers502to form contact portions108a-108hin the openings. Forming the contact portions108a-108hin the holes604a-604hresult in the contact portions108a-108hhaving an oval shape with a long diameter DL2in the direction114as shown inFIG.2A. The conductive material may be, for example, tungsten. The conductive material may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

Interconnects104a-104dinFIG.1may be disposed on the one or more dielectric layers218and the contact portions108a-108hin the one or more dielectric layers218. The interconnects104a-104dmay extend in the direction114. Forming the interconnects104a-104dmay be similar to forming the interconnects102a-102din the dielectric layer402previously described with reference to and shown inFIGS.4A and4B, thus the description of forming the interconnects104a-104dis omitted for brevity. As shown inFIG.1, the interconnect104amay be disposed on the contact portions108aand108b, the interconnect104bmay be disposed on the contact portions108cand108d, the interconnect104cmay be disposed on the contact portions108eand108f, and the interconnect104dmay be disposed on the contact portions108gand108h.

In the description above, contacts are formed in two steps; however, a number of steps to form contacts are not limited to two. Forming contacts (e.g., vias) in a peripheral region in a plurality of etching steps, instead of one etching step, openings would have a smaller cross-section unlike contacts formed using one etching step. Each contact may have an oval-shape cross section having a long diameter in a direction that each interconnect coupled to each contact extends. Thus, a short circuit between adjacent interconnects may be prevented.

Although various embodiments have been disclosed in the present disclosure, it will be understood by those skilled in the art that the scope of the disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this disclosure will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying embodiments. Thus, it is intended that the scope of at least some of the present disclosure should not be limited by the particular disclosed embodiments described above.