Signal processing device and method for providing oscillating signal in the signal processing device

A signal processing device includes a signal processing chip and a conducting path. The signal processing chip includes: a first port capable of receiving a first oscillating signal; a second port capable of outputting a second oscillating signal derived from the first oscillating signal; and a third port. The conducting path is external to the signal processing chip and coupled to the second port and the third port, and the conducting path is capable of transmitting the second oscillating signal outputted from the second port to the third port.

BACKGROUND

The present invention relates to a signal processing device and a method for providing an oscillating signal in the signal processing device, and more particularly to a signal processing device that uses fewer oscillators, and a related method.

In a mobile system, a baseband chip can be utilized for performing various kinds of baseband coding/decoding operations, such as audio or video signal processing. In such a system, a precise clock signal should be given to the baseband chip to generate reference clock signals for the functional circuit blocks in the baseband chip. More specifically, an analog RTC (Real-time-clock) block is capable of receiving the precise clock signal, and generating the reference clock signals for the functional circuit blocks in the baseband chip. Conventionally, the precise clock signal is generated by a crystal oscillator external to the baseband chip and the analog RTC block as the crystal oscillator has a relatively stable electrical characteristic. The price of the crystal oscillator can be a problem when dealing with the BOM (Bill of Materials) cost of the mobile system, however. Therefore, how to generate a reference clock signal for the baseband chip while saving the cost of the mobile system has become a problem in this field.

SUMMARY

One of the objectives of the present embodiment is to provide a signal processing device that does not use a crystal oscillator, and a related method.

According to a first embodiment, a signal processing device is disclosed. The signal processing device comprises a signal processing chip and a conducting path. The signal processing chip comprises a first port, a second port, and a third port. The first port is capable of receiving a first oscillating signal. The second port is capable of outputting a second oscillating signal derived from the first oscillating signal. The conducting path is external to the signal processing chip and is coupled to the second port and the third port. The conducting path is capable of transmitting the second oscillating signal outputted from the second port to the third port.

According to a second embodiment, a method for providing an oscillating signal in a signal processing device signal processing device is disclosed. The method comprises: receiving a first oscillating signal by a first port of a signal processing chip; outputting a second oscillating signal derived from the first oscillating signal by a second port of the signal processing chip; and providing a conducting path coupled to the second port and the third port to transmit the second oscillating signal outputted from the second port to the third port, wherein the conducting path is externally coupled to the signal processing chip.

DETAILED DESCRIPTION

Please refer toFIG. 1.FIG. 1is a diagram illustrating a signal processing device100according to an embodiment of the present invention. The signal processing device100may include a signal processing chip102, a conducting path104, and a controllable oscillator106. The signal processing chip102can be utilized for performing various kinds of signal processing, for example, baseband coding/decoding operations such as audio or video signal coding/decoding. The signal processing chip102may include a first port1022, a second port1024, a third port1026. In some embodiments, the signal processing chip102may further include a fourth port1028, an operating circuit1030, and a frequency divider1032. The controllable oscillator106can be coupled to the first port1022and is capable of providing a first oscillating signal Sosc1. The first oscillating signal Sosc1can be provided by the controllable oscillator106according to a supply voltage Vdd, which means that the controllable oscillator106is not a crystal oscillator. Those skilled in the art should understand that a crystal oscillator is a self-oscillating device which does not need a supply power. The present controllable oscillator106may be, for example, a voltage-controlled oscillator (VCO), a voltage-controlled crystal oscillator (VCXO), a temperature-compensated crystal oscillator (TCXO) or a voltage-controlled temperature-compensated crystal oscillator (VCTCXO), etc.

In this preferred embodiment, the oscillating signal (i.e., So) generated/provided by the controllable oscillator106can first be input to a radio-frequency (RF) transceiver circuit108, and the first oscillating signal Sosc1can then be provided from the RF transceiver circuit108and input to the signal processing chip102. The RF transceiver circuit108may be located between the signal processing chip102and the controllable oscillator106on a circuit board. With the RF transceiver circuit108, the signal processing chip102may be blocked from the interference signal generated by the controllable oscillator106. It should be noted that, in this embodiment, the frequency of the oscillating signal So is substantially equal to the frequency of the first oscillating signal Sosc1, but this is not a limitation of the present invention. Furthermore, the oscillating signal So generated/provided by the controllable oscillator106can also be directly input into the signal processing chip102to be the first oscillating signal Sosc1if the controllable oscillator106is located close enough to the signal processing chip102on a circuit board and then the interference signal generated by the controllable oscillator106may not be a serious issue for the signal processing chip102.

The first port1022is capable of receiving the first oscillating signal Sosc1. The frequency divider1032, which may be a phase-locked loop (PLL) and can be coupled between the first port1022and the second port1024, is capable of dividing the first oscillating signal Sosc1to generate/provide a second oscillating signal Sosc2. The second port1024is capable of outputting the second oscillating signal Sosc2. The conducting path104, which can be external to the signal processing chip102and coupled to the second port1024and the third port1026, is capable of transmitting the second oscillating signal Sosc2output from the second port1024to the third port1026.

The operating circuit1030is coupled to the third port1026, and the operating circuit1030is capable of receiving the second oscillating signal Sosc2via the third port1026and using the received second oscillating signal Sosc2as a real-time clock of the signal processing device100. In other words, the operating circuit1030can receive the second oscillating signal Sosc2to generate/provide reference clock signal(s) for the functional circuit block(s) in the signal processing chip102or the signal processing device100. Furthermore, the operating circuit1030can include an analog RTC (Real-time-clock) block capable of receiving the second oscillating signal Sosc2as a real-time-clock for counting the time of a mobile system including the signal processing device100. It should be noted that the fourth port1028can also be coupled to the operating circuit1030, wherein the third port1026and the fourth port1028can form a crystal oscillator input port, and the fourth port1028can be unused when the signal processing device100is under an operation mode. For example, the fourth port1028may be left as an open circuit when the signal processing device100is under the operation mode.

Please refer toFIG. 1again. A conventional mobile system may include a conventional crystal oscillator110having two output terminals N1, N2: one is required to couple to the third port1026and the other is required to couple to the fourth port1028, i.e. the dashed line inFIG. 1. In this preferred embodiment, the conventional crystal oscillator110is omitted, and the real-time clock is now generated/provided by the controllable oscillator106. Therefore, the third port1026is coupled to the conducting path104for receiving the second oscillating signal Sosc2to be the real-time clock, and the fourth port1028can be left unused or simply as an open circuit.

In some embodiments, the controllable oscillator106can be arranged to generate/provide the oscillating signal for the RF transceiver circuit108, then the frequency (e.g., 26 MHz, 13 MHz, etc.) of the first oscillating signal Sosc1may be higher than the required frequency (e.g., 32.768 KHz, etc.) of the operation circuit1030. Therefore, the frequency divider1032can further be provided to perform a frequency dividing operation upon the first oscillating signal Sosc1with an oscillating frequency substantially equal to, for example, 26 MHz, to generate/provide the second oscillating signal Sosc2with an oscillating frequency substantially equal to, for example, 32.768 KHz. When the second oscillating signal Sosc2is generated/provided in the signal processing chip102, the second oscillating signal Sosc2can further be output from the signal processing chip102via the second port1024, and then be again input to the operation circuit1030of the signal processing chip102via the conducting path104and the third port1026. This is because, except for the operation circuit1030, the signal processing chip102may be a digital circuit, and there may not be a conducting path provided for an oscillating signal, i.e. the second oscillating signal Sosc2, in the digital circuit to transmit to the operating circuit1030internally. In other words, the operating circuit1030may only recognize the real-time-clock input from the third port1026or the fourth port1028. It should be noted that, the second port1024may be implemented by a general purpose input/output (GPIO) pin, which is easy to be generated/provided when designing the signal processing chip102.

According to the above-mentioned arrangement, the BOM (Bill of Materials) cost of the mobile system can be reduced since the conventional crystal oscillator110can be omitted. Meanwhile, the area of printed circuit board (PCB) required by the signal processing device100can also be reduced due to the lack of the conventional crystal oscillator110.

A method for providing an oscillating signal in a signal processing device, such as the signal processing device100inFIG. 1, may be summarized inFIG. 2.FIG. 2is a flowchart illustrating a method200for providing an oscillating signal (e.g. the second oscillating signal Sosc2) in a signal processing device (e.g. the signal processing device100) according to a second embodiment of the present invention. The embodiment is illustrative only, the steps of the flowchart shown inFIG. 2need not be in the exact order shown and need not be contiguous; that is, other steps can be intermediate. Besides, one or more steps inFIG. 2can be omitted according to different design requirements. The method200includes the following steps:

Step202: Provide a signal processing chip (e.g. the signal processing chip102) having a first port (e.g. the first port1022), a second port (e.g. the second port1024), and a third port (e.g. the third port1026);

Step204: Receive a first oscillating signal (e.g. the first oscillating signal Sosc1) by the first port;

Step206: Output a second oscillating signal (e.g. the second oscillating signal Sosc2) derived from the first oscillating signal by the second port; and

Step208: Provide a conducting path (e.g. the conducting path104) coupled to the second port and the third port to transmit the second oscillating signal outputted from the second port to the third port, wherein the conducting path is externally coupled to the signal processing chip.

In step204, the first oscillating signal can be generated/provided by a controllable oscillator (e.g. the controllable oscillator106) according to a supply voltage, in which the controllable oscillator is not a crystal oscillator. In some embodiments, the controllable oscillator can be arranged to generate/provide the oscillating signal for an RF transceiver circuit, then the frequency (e.g. 26 MHz, 13 MHz, etc.) of the first oscillating signal may be higher than the required frequency (e.g. 32.768 KHz, etc.) of the real-time-clock block (e.g. a portion of or the entire operating circuit1030) of the signal processing chip. Therefore, a frequency dividing operation can be performed upon the first oscillating signal with an oscillating frequency substantially equal to, for example, 26 MHz, to generate/provide the second oscillating signal with an oscillating frequency substantially equal to, for example, 32.768 KHz. After performing the frequency dividing operation upon the first oscillating signal to generate/provide the second oscillating signal, the second oscillating signal can further be outputted from the signal processing chip via the second port, and then be again input to the real-time-clock block via the conducting path and the third port (steps206,208). Accordingly, the conventional crystal oscillator can be omitted, and the BOM cost and PCB area of the signal processing device, such as the signal processing device100, can be saved.