DIFFERENTIALLY PROGRAMMABLE MAGNETIC TUNNEL JUNCTION DEVICE AND SYSTEM INCLUDING SAME

A memory device, an integrated circuit component including an array of the memory devices, and an integrated device assembly including the integrated circuit component. The memory devices includes a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.

TECHNICAL FIELD

This disclosure relates generally to magnetic tunnel junction devices.

BACKGROUND

Spintronics is the study of intrinsic spin of the electron in solid-state devices. In spintronics, spin transfer torque (STT) and spin orbit torque (SOT) mechanisms manipulate local magnetizations controlled by external magnetic fields. STT refers to the effect by a spin polarized charge current in magnetic materials when there exists a magnetization spatial gradient. SOT results from pure spin current, with no net charge currents generated by the associated spin Hall effect (SHE).

The mechanisms in SOT and STT have been leveraged in SOT and STT magnetic tunnel junction (MTJ) devices, which are magnetic state devices used as digital memory in magnetic random access memory devices (MRAMs). Current solutions use digital SOT and STT MTJ MRAMs in a number of different implementations, including in in-memory compute applications, and for example in artificial intelligence operations. In such cases, multiple MTJs may be used as multiple memory cells in a MRAM, and the corresponding computation is in turn performed on the detector side. The use of multiple MTJ cells in a MRAM may cause the operation of the MRAM device to suffer from inefficiencies, for example in terms of energy and space consumption.

DETAILED DESCRIPTION

Some embodiments provide a memory device including: a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.

Advantageously, embodiments provide an energy, time and space efficient memory computing device able to store multiple memory states.

The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

In the description of the instant figures, “vertical” refers to the “z” direction, and “horizontal” refers to the “x” direction or the “y” direction, which directions are shown by way of the coordinate systems provided in the figures.

FIG.1Aillustrates a typical material stack100afor a giant spin Hall effect (GSHE) Spin Torque Switching based magnetic tunnel junction (MTJ) according to one embodiment of the disclosure. In one embodiment, the MTJ stack comprises of free magnetic layer (FM1), MgO tunneling oxide layer, a fixed magnetic layer (FM2) with a Synthetic Anti-Ferromagnet (SAF) layer, which may be CoFe/Ru based, and an antiferromagnet (AFM) layer. The SAF layer allows for cancelling the dipole fields around the free magnetic layer. A wide combination of materials can be used for material stacking in the MTJ stack ofFIG.1A.

The write electrode comprises a GSHE metal which may be, according to the state of the art, be made of β-Tantalum (β-Ta), β-Tungsten (β-W), Pt, Copper (Cu) doped with elements such as Iridium, Bismuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the periodic table. In one embodiment, the write electrode transitions into a normal high conductivity metal (e.g., Cu) at ends thereof to minimize the write electrode resistance.

FIG.1Bis a top view130of the stack100aofFIG.1A. InFIG.1B, the magnet is oriented along the width of the GSHE electrode for appropriate spin injection. The magnetic cell is subjected to a write operation by applying a write charge current Iwvia the GSHE electrode. The direction of the magnetic writing is decided by the direction of the applied charge current. Positive currents along the +y direction produce a spin injection current with transport direction along the +z direction and spins pointing to the +x direction.

FIG.1Cis a cross-section240of the GSHE material that shows the direction of spin currents and charge currents as decided by SHE in metals. The injected spin current in-turn produces spin torque to align the magnet in the +x or −x direction. The transverse spin current {right arrow over (I)}s={right arrow over (I)}↑−{right arrow over (I)}↓with spin direction {circumflex over (σ)} for a charge current {right arrow over (I)}cin the write electrode is expressed as:

where:
Pshe=({right arrow over (I)}↑−{right arrow over (I)}↓)/({right arrow over (I)}↑+{right arrow over (I)}↓) is the Spin Hall injection efficiency which is the ratio of magnitude of transverse spin current to lateral charge current;
w is the width of the magnet;
t is the thickness of the GSHE metal electrode;
λsfis the spin flip length in the GSHE metal; and
θGSHEis the spin Hall angle for the GSHE-metal to FM1 interface.
The injected spin angular momentum responsible for spin torque is given by:

It is pointed out that those elements ofFIGS.2A and2Bhaving the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

FIGS.2A and2Bshow a MTJ SOT MRAM bit cell200, according to one embodiment of the disclosure. In one embodiment, bit cell200is a three terminal device, similar to the device100ofFIGS.1A-1C, compared to a two terminal bit cell that would be used with a STT MTJ. In this particular embodiment, read and write bit line (BL) terminals are decoupled from one another forming the first two terminals, and the source line (SL), also referred to as the select line, forms the third terminal.

In one embodiment, bit cell200comprises an MTJ stack or MTJ device202that is located between an electrode201including a AFM material (AFM electrode)201, and a second electrode209.

In one embodiment, as shown inFIG.2B, bit cell200comprises transistor M1with one of its drain/source terminals coupled to the AFM electrode201, and the other of its source/drain terminals coupled to the SL. In one embodiment, transistor M1is an n-type transistor e.g., NMOS. In one embodiment, transistor M1is a p-type transistor.

As shown more specifically inFIGS.2A and2B, bit cell200is a three terminal device presenting two paths, a write path as indicated by Iw, which basically writes the state of the device by writing the resistance of the MTJ device (through deterministically coding the magnetization state of the FM1 layer); and a read path along a length of the MTJ device, which can be used to read the resistance by applying a read current Irin this vertical path and then measuring the resultant voltage using sense amplifier.

FIG.2Bmore clearly shows the three terminals of the bit cell200, including a BL read terminal T1connected to the read bit line, a terminal T2at one end of AFM electrode201, and a terminal T3at another end of AFM electrode201. Transistor M1in the shown embodiment ofFIG.2Bis shown as having been connected to terminal T3at one of its source/drain terminals. Iw is shown as flowing along a length of the AFM electrode201between terminals T2and T3, representing the write path for the write bit line.

MTJ device202includes a free ferromagnetic (FM1) layer204, a fixed or reference ferromagnetic layer (FM2) layer208, and a tunnel barrier (TB) layer206between the FM1 layer204and FM2 layer208. A wide combination of materials can be used for material stacking of the MTJ device202.

In certain aspects and in at least some embodiments of the present invention, certain terms hold certain definable meanings. For example, the “free” ferromagnetic layer magnetic layer is a ferromagnetic layer adapted to store at least two computational variables. A “fixed” ferromagnetic layer is a magnetic layer with fixed magnetization (magnetically harder than the free magnetic layer). In one embodiment, the free layer may be complex and made of two separate magnetic layers with a coupler layer in between. In one embodiment, the fixed layer is complex and made of two magnets with a coupler layer in between. In yet another embodiment, both the free layer and the fixed layer may be complex.

In one embodiment, AFM electrode201may be directly coupled to the write BL. In one embodiment, the read BL may be coupled to another terminal of the MTJ device. In one embodiment, the word line (WL) may be coupled to the gate terminal of transistor M1. In one embodiment, select transistor M1may be placed in saturation mode to overcome the existing limitation in highly scaled MRAM arrays.

In one embodiment, to write data to bit cell200, spin current is injected in the free magnetic layer of the MTJ device which is in direct contact with the AFM electrode201. In one embodiment, to read data from bit cell200, a sense amplifier may sense the read BL and SL.

According to some embodiments, the AFM material of the AFM electrode201may include an antiferromagnetic metal spin orbit torque (SOT) material/spin Hall effect (SHE) material, such as, for example, PtMn, IrMn or FeMn, and the like. A SOT material or SHE material refers to a material that exhibits strong spin orbit coupling or SHE effects.

For example, in one embodiment, the AFM material may comprise a metal antiferromagnet material such as an antiferromagnet material including at least one of Co, Fe, Ni, MnGa, MnGeGa, Bct-Ru, or alloys thereof. In yet another embodiment, the AFM layer may comprise quasi-two-dimensional triangular antiferromagnet materials including Ni1-xMxGa2S4 where M=Mn, Fe, Co or Zn or transition metal di-chalcogenides/topological insulators such as BiSe2, WTe2, WSe2, MoSe2 and the like, IrMn, PtMn, NiMn or other triangular, Kagomi, chiral or hexagonal antiferromagnets either in their single crystal form or in their amorphous alloy form in various compositions.

The stack of materials of the FM1 layer204, in the shown embodiment, in order from bottom to top above the AFM electrode201may include: a multilayer stack of layers including distinct layers ferromagnetic materials (multilayer FM stack)214including, in the shown embodiment, alternating layers of Co and Ni, a layer including a coupler material (coupler layer)216, and a layer including a high tunneling magnetoresistance (TMR) free magnetic material (high TMR free layer)228. The high TMR free layer228is disposed adjacent the TB layer206.

For example, in one embodiment, the multilayer FM stack214may include alternating layers of a first ferromagnetic material and a second ferromagnetic material. In another embodiment, the multilayer FM stack214may include distinct layers, where at least two of the layers include different ferromagnetic materials with respect to one another.

For example, in one embodiment, coupler layer216may include Ru, Ir, W, or Ta. The coupler material of the coupling layer216is to couple the magnetization state of the high TMR free layer228to that of the superlattice214.

For example, in one embodiment, the TB layer206may include a TB material such as MgO, Al2O3, EuO, or their alloys.

The FM2 layer208is disposed adjacent the TB material, and may include a layer including a high TMR fixed magnetic material (high TMR fixed layer)226, a layer including a coupler material (coupler layer)218on the high TMR fixed layer, a SAF/pinning layer224on the coupler layer219, and a capping structure212on the SAF pinning layer224including alternating layers of capping metal.

For example, in one embodiment, any of high TMR free layer228or high TMR fixed layer226may comprise a high TMR material such as CoαXβPtλwhere (X=Cu, Ni, Mn, Cr) alloy, wherein α ranges from 20 to 50, β ranges from 0 to 30, and λ ranges from 40 to 60, with the proviso that=α+β+λ=100. An example high TMR material for any of layers226or228may include Co40Cu10Pt50alloy, which is ferromagnetic. In one embodiment, the high TMR material may have a FCC or rhombohedral crystal structure along (111) orientation or a HCP crystal structure along (0002) orientation such that it exhibits PMA. The thickness of the high TMR layers226or228may be from 20 A to 100 A. The high TMR layers226or228may be formed by PVD at a temperature range from 150° C. to 450° C. The high TMR layers226or228may also be formed using other techniques or processes as well.

The SAF/pinning layer224allows for cancelling the dipole fields around the free magnetic layer. The SAF/pinning layer224may comprise any of the materials listed for the AFM layer201above.

Coupler layer219may aid the SAF/pinning layer in pinning the fixed layer, and centers the magnetic hysteresis loop by overcoming the dipole field between the fixed and the free magnetic layers. In one embodiment, the coupler layer may comprise Ru, Ir, W, or Ta.

In other embodiments, other materials may be used to form the MTJ device.

The AFM-FM interface207of the AFM-FM1 bilayer results in an exchange bias in the magnetic behavior of the FM1 layer. The exchange bias is exhibited by way of an in-plane magnetic field at the AFM-FM1 layer interface207. In the example embodiment ofFIGS.2A and2B, the AFM-FM1 bilayer interface, by virtue of the AFM electrode being made of a SHE metal, further generates SHE effects by virtue of the application of a write current Iwalong a length of the AFM electrode201. Thus, inFIGS.2A and2B, by flowing Iwin the +y direction for example, by virtue of SHE, once can cause a spin current Iswithin the AFM layer201, which in turn causes a change in the direction of the magnetization within the FM1204layer. Thus, through application of Iw, one can deterministically switch the perpendicular magnetization of the FM1 layer.

A property of the shown MTJ device202is its ability to cause intermediate switching levels or states for the magnetization of FM1 layer for different amplitudes of Iw, meaning that the FM1 layer may not necessary switch its magnetization as a whole, but rather exhibit multidomain switching behavior with various levels of magnetization states for the FM1 layer, the levels depending on the amplitude of spin current Isfrom AFM layer201, leading to multiple (i.e. more than two) resistance values of the MTJ device202corresponding to different levels of magnetization of domains within the FM1 layer.

A reason behind the ability of FM1 layer204to exhibit multiple magnetization states is that the FM1 layer is to exhibit magnetization switching via domain nucleation, that is, via magnetic nucleation within discrete domains separate by domain walls inside the FM1 layer, such as in the multilayer FM stack214. For the magnetization of the entire FM1 layer to switch in a uniform manner, additional energy would be necessary to propagate the domain nucleation uniformly across domain boundaries. The MTJ device200has a configuration from that of existing FM and heavy metal electrode systems (such as the GSHE electrode ofFIGS.1A-1C) where the metal electrode includes metals such as cobalt, iron, boron and tantalum. In the latter kind of system, once a domain nucleates to a given magnetization states, the domain propagation energy is low enough that the domain nucleation (and hence associated magnetization state) propagates and switch the entirely of the FM1 layer. In AFM-FM bilayer configuration of embodiments, as shown by way of example inFIGS.2A and2B, domain propagation does not happen ready, leading to multiple nucleation events contributing to discrete domains of magnetization states for different values of the write current Iw. Thus, more than two value for Iwcan allow a coding of multiple magnetization states within MTJ device202.

The larger the area of the AFM-FM interface207, the more magnetization states one may be able to fit within an MTJ device in a SOT MRAM. The exchange interaction or exchange bias at interface207is brought about by the quantum effect of spins in the AFM material and in the material of the FM1 layer at the interface207. The exchange bias promotes creation of domain walls within the FM1 layer which in turn makes possible the provision of intermediate resistance states of the MTJ device as a whole. The provision of a structure such as that ofFIG.2B, or ofFIG.3to be described below, including a AFM electrode201and a FM1 layer, TB layer and FM2 layer structure on the AFM electrode201, will make it possible to obtain resistances from the MTJ devices that are measurable by a sense amplifier (such resistances, for one example of a MTJ device according to embodiments, may for example be in the order of thousands of Ohms, for example between 5000 and 10,000 Ohms.

An effect of the multilayer FM stack214is to make the programming of multiple resistances of the MTJ device possible. In the shown example ofFIGS.2A and2B, the FM stack214includes a superlattice of alternating Co and Ni layers, which causes the perpendicular anisotropy (perpendicular to the in-plane direction of AFM-FM interface207) that allows the direction of magnetization of the FM1 layer204to point in the +z or −z direction. For some common ferromagnetic materials such as Co, Fe or Bo, an AFM electrode may not present an ideal solution to achieving a perpendicular (vertical) ferromagnetism. However, in a multilayered structure such as that of FM stack214, the perpendicular ferromagnetism relies on the interface between the various ferromagnetic materials, such as cobalt and nickel in the shown example ofFIGS.2A and2B, and not as much on the AFM-FM interface207. Therefore, having a FM stack of differing and/or alternating FM materials may be advantageous in achieving perpendicular anisotropy where multi-domain magnetic switching is desired to allow the programming of multiple resistances in a same MTJ device.

A vertical/perpendicular magnetization direction for the FM1 layer is more controllable, and makes for a more compact MTJ devices where relying on an in-plane magnetization direction would have required a MTJ device with a much larger footprint. Having a FM stack with multiple layers of different FM materials achieves multiple magnetization domains by among other things presenting multiple interfaces, where each interface adds to the energy that would be required to make the magnetization within the FM1 layer uniform and to overcome the FM1 layer shape anisotropy.

FIG.3illustrates a MTJ STT MRAM bit cell300, according to one embodiment of the disclosure. Bit cell300is a two terminal device. The MTJ device302has a configuration similar to the MTJ device202ofFIG.2A, except that AFM electrode301inFIG.3is shorter and is used only as a single terminal rather than being connected to two terminals as in AFM electrode201, and, therefore, the descriptions of the various layers of MTJ302will be omitted here. For the STT-MRAM, the read and write current paths for bit cell300are identical. Write current Iwrepresents a spin polarized charge current which flows through a magnetization spatial gradient of the FM2 layer and the FM1 layer. Iwcauses the generation of a spin current Isat the AFM-FM interface between the AFM electrode201and FM1 layer204, and along with the in-plane magnetization at the AFM-FM interface207, causes a resistance state to be coded into the MTJ202based on the amplitude of Iw. Reading various resistance states of the MTJ device302involve applying a current Ireadacross the top and bottom electrodes209and201, and determining the voltage across the two electrodes to determine resistance.

Reference is now made toFIG.4, which shows another embodiment of a MTJ SOT MRAM bit cell400. The embodiment of the bit cell400ofFIG.4may be used for example in a neural network circuit where bit cells such as bit cells400are connected serially, such that a resistance state of one MTJ, as represented by the voltage drop for example between T1and T3, may be used to provide a bias input into the read path or read bit line of a next MTJ within the neural network circuit. In the shown bit cell400ofFIG.4, we have a four transistor architecture example where a MTJ according to some embodiments, such as MTJ202ofFIG.2A, is connected at its read terminal T1to one of a source/drain region of a transistor M4. Terminal T2is connected to one of a source/drain region of a transistor M2, and terminal T2is connected to one of a source/drain region of a transistor M1. T3is further connected to one of the source/drain region of a transistor M3, the other source/drain of which corresponds to a read bit line of a next MTJ. M4and M3share a common gate voltagePROGand M1and M2share a common gate voltage PROG. The path between T2and T3represents the write path or the write bit line, while the read path is between T1and T3.

In the program phase, when a resistance is to be written into the MTJ202ofFIG.4, PROG is brought high (a voltage pulse is supplied to the gates of M1and M2to have M1and M2conduct, and in this way to generate Iw between T2and T3, andPROGis low. That means that we have these two transistors conducting and we have this path open. Depending on the absolute value of the program voltage applied at PROG, we will have a different amount of current Iw and hence a different amount of FM1 layer magnetism switching, and thus a different resistance programmed into the MTJ. The resistance may for example correspond to a weight used for modeling in a neural network to implement machine learning.

During a read operation, PROG is turned off, M1and M2are not conducting, and no Iw flows.PROGis brought high (a voltage pulse is applied to the gates of transistors M3and M4), which means that Ireadflows between T1and T3. The voltage drop across MTJ202, and hence the voltage at T3, will depend on the resistance of the MTJ202. This voltage is applied at one of the source/drain regions of M3, which then determines the amount of voltage applied at one of the source/drain of the M1connected to the T1of the next neuron or bit cell. The Ireadat the next MTJ may therefore correspond to the input voltage input to a previous neuron multiplied by the conductance of that neuron as programmed during our program cycles. In this manner, a bit cell using a MTJ according to embodiments may be used as a synapse in a neural network.

Referring now toFIG.5A, a neuromorphic computing system500ais shown including M pre-neurons (or an array of previous bit cells including MTJs), an array of synapse such as an array of bit cells such as bit cell200ofFIG.2Br bit cell400ofFIG.4, and N post neurons (or an array of subsequent bit cells including MTJs). For resistance readouts, corresponding to weight determination in a neuromorphic computing system implementing, for example, machine learning, the array of previous neurons, with an array of corresponding programmed resistances, may be connected to the inputs T1of bit cells according to some embodiments. The previous neurons are supplying a voltage to the bit cells of the synapse array. There would therefore need to be M×N weights in the synapse array. The currents generated in the synapse array, will have different values based on the different connection branches between the previous neurons and the bit cells within the synapse. The currents may be summed at the output of the synapse array, and converted back into a voltage that corresponds to a weighted sum of the voltages at the input of the synapse array, and so forth through the neural network.

Reference is now made toFIG.5B, which shows a probabilistic computing system500b,an emerging a computing paradigm including neurons similar to the ones described in the context ofFIG.5. System500bincludes a N×N square array of neurons to provide square weights, the neurons for example including SOT bit cells similar to those shown inFIGS.2A and2B. The square array of weights supplies Vin into an array of N neurons, for example including SOT bit cells similar to those shown inFIGS.2A and2B, and uses as its input the Vout from the N neurons.

According to some embodiments, the output of each array of neurons, for example a square or rectangular array, may be connected to a sense amplifier, which may sense the sum of the currents from the array of neurons.

Advantageously, embodiments provide MTJ devices that are differentially programmable, making such devices useful as bit cells that can serve as neurons or synapses in a neural network. The differential programmability of resistances for each MTJ devices makes it possible to have each MTJ devices exhibit more than two logical values (0 and 1), such as a spread of resistance values between 0 and 1 as determined by the write current applied to the MTJ device. Thus, instead of a digital MTJ devices, embodiments make possible the provision of analog MTJ devices.

FIG. 6 illustrates a two terminal 1T-1MTJ (Magnetic Tunnel Junction) bit cell600for STT-MRAM. The MTJ in the bit cell600may have configuration according to some embodiments, such as the configuration of the MTJ302ofFIG.3. For the STT-MRAM, the read and write current paths for bit cell600are identical. To write a logical high to bit cell600, the bit line is raised relative to the source line, and to write a logical low to bit cell600, the bit line is lowered relative to the source line. To read from bit cell600, the source line is set to logical low and MTJ resistance is sensed using a weak current (e.g., ⅛thof the write current Iw).

FIG.7shows is a cross sectional view720of 1T-1MTJ SOT MRAM bit-cell200, according to one embodiment of the disclosure. In one embodiment, the source and drain regions of transistor M1are coupled to metal layers for trench contacts (TCN) and in turn couple to MOC and MOB lines respectively, where MOC and MOB are segments of metal in the MO layer. In one embodiment, MOC is a continuous line for a row of bit-cells in an array. In one embodiment, source line (SL) is coupled to MOC. In one embodiment, MOB is coupled to M2layer through via V1, first metal layer (M1), and via V2. In one embodiment, via V2couples to M2B (segment in M2layer) and is indirectly coupled to write BL through M2C. In one embodiment, M2B is coupled to M2C through via V2, another segment of M1, and back to M2C through another via V2coupled to M1, as shown in the dotted region. In one embodiment, MTJ device202is located in regions of via V3, M3, and via V4. One end of the MTJ device202is coupled to M2B through via V3while the other end of the MTJ device is coupled to read BL on M4through via V4. In this embodiment, M2B is the AFM electrode201with SHE material. The MTJ layer may be located in a back end of the complementary metal oxide semiconductor (CMOS) stack occupying the vertical location of V3-M3-V4. M2C (on M2) BL write, M4BL read, and MO SL may be shared between bit-cells. In this latter embodiment, the local AFM electrode interconnects with SHE material, which are directly coupled to free magnet layer of the respective MTJ devices of the two bit-cells, are not shared between bit-cells i.e., AFM electrode SHE interconnect may not be shared with adjacent cells of a row of bit-cells.

In some embodiments, the contacts, electrodes, interconnects and non-magnetic conductors shown or described herein may be formed of non-magnetic metal (e.g., Cu, Ag, etc.).

FIG.8is a cross-sectional side view of an integrated circuit device assembly800that may include any of the MTJ devices disclosed herein. In some embodiments, the integrated circuit device assembly800may include an array of MTJ devices for a neural network system. The integrated circuit device assembly800includes a number of components disposed on a circuit board802(which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly800includes components disposed on a first face840of the circuit board802and an opposing second face842of the circuit board802; generally, components may be disposed on one or both faces840and842. Some of the integrated circuit components discussed below with reference to the integrated circuit device assembly800may take the form of any suitable ones of the embodiments of the MTJ devices, array of MTJ devices, or dies including MTJ devices disclosed herein.

In some embodiments, the circuit board802may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board802. In other embodiments, the circuit board802may be a non-PCB substrate. The integrated circuit device assembly800illustrated inFIG.8includes a package-on-interposer structure836coupled to the first face840of the circuit board802by coupling components816. The coupling components816may electrically and mechanically couple the package-on-interposer structure836to the circuit board802, and may include solder balls (as shown inFIG.8), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure836may include an integrated circuit component820coupled to an interposer804by coupling components818. The coupling components818may take any suitable form for the application, such as the forms discussed above with reference to the coupling components816. Although a single integrated circuit component820is shown inFIG.8, multiple integrated circuit components may be coupled to the interposer804; indeed, additional interposers may be coupled to the interposer804. The interposer804may provide an intervening substrate used to bridge the circuit board802and the integrated circuit component820.

The integrated circuit component820may be a packaged or unpacked integrated circuit product that includes one or more MTJ devices as described herein and/or one or more other suitable components. A packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate with the integrated circuit dies and package substrate encapsulated in a casing material, such as a metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component820, a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer804. The integrated circuit component820can comprise one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I/O controller, memory, or network interface controller. In some embodiments, the integrated circuit component820can comprise one or more additional active or passive devices such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

In embodiments where the integrated circuit component820comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).

In addition to comprising one or more processor units, the integrated circuit component820can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof

Generally, the interposer804may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer804may couple the integrated circuit component820to a set of ball grid array (BGA) conductive contacts of the coupling components816for coupling to the circuit board802. In the embodiment illustrated inFIG.8, the integrated circuit component820and the circuit board802are attached to opposing sides of the interposer804; in other embodiments, the integrated circuit component820and the circuit board802may be attached to a same side of the interposer804. In some embodiments, three or more components may be interconnected by way of the interposer804.

In some embodiments, the interposer804may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer804may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer804may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer804may include metal interconnects808and vias810, including but not limited to through hole vias810-1(that extend from a first face850of the interposer804to a second face854of the interposer804), blind vias810-2(that extend from the first or second faces850or854of the interposer804to an internal metal layer), and buried vias810-3(that connect internal metal layers).

In some embodiments, the interposer804can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer804comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer804to an opposing second face of the interposer804.

The interposer804may further include embedded devices814, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer804. The package-on-interposer structure836may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board

The integrated circuit device assembly800may include an integrated circuit component824coupled to the first face840of the circuit board802by coupling components822. The coupling components822may take the form of any of the embodiments discussed above with reference to the coupling components816, and the integrated circuit component824may take the form of any of the embodiments discussed above with reference to the integrated circuit component820.

The integrated circuit device assembly800illustrated inFIG.8includes a package-on-package structure834coupled to the second face842of the circuit board802by coupling components828. The package-on-package structure834may include an integrated circuit component826and an integrated circuit component832coupled together by coupling components830such that the integrated circuit component826is disposed between the circuit board802and the integrated circuit component832. The coupling components828and830may take the form of any of the embodiments of the coupling components816discussed above, and the integrated circuit components826and832may take the form of any of the embodiments of the integrated circuit component820discussed above. The package-on-package structure834may be configured in accordance with any of the package-on-package structures known in the art.

FIG.9is a block diagram of an example electrical device900that may include one or more of the MTJ devices disclosed herein. For example, any suitable ones of the components of the electrical device900may include one or more of the integrated circuit device assemblies800, integrated circuit components820, MTJ devices as disclosed herein, or integrated circuit dies including MTJ devices as disclosed herein, and may be arranged in any of the MTJ devices disclosed herein. A number of components are illustrated inFIG.9as included in the electrical device900, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device900may be attached to one or more motherboards mainboards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the electrical device900may not include one or more of the components illustrated inFIG.9, but the electrical device900may include interface circuitry for coupling to the one or more components. For example, the electrical device900may not include a display device906, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device906may be coupled. In another set of examples, the electrical device900may not include an audio input device924or an audio output device908, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device924or audio output device908may be coupled.

The electrical device900may include a memory904, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory904may include memory that is located on the same integrated circuit die as the processor unit902. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, the electrical device900can comprise one or more processor units902that are heterogeneous or asymmetric to another processor unit902in the electrical device900. There can be a variety of differences between the processing units902in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units902in the electrical device900.

In some embodiments, the electrical device900may include a communication component912(e.g., one or more communication components). For example, the communication component912can manage wireless communications for the transfer of data to and from the electrical device900. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

In some embodiments, the communication component912may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component912may include multiple communication components. For instance, a first communication component912may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component912may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component912may be dedicated to wireless communications, and a second communication component912may be dedicated to wired communications.

The electrical device900may include battery/power circuitry914. The battery/power circuitry914may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device900to an energy source separate from the electrical device900(e.g., AC line power).

The electrical device900may include a display device906(or corresponding interface circuitry, as discussed above). The display device906may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device900may include an audio output device908(or corresponding interface circuitry, as discussed above). The audio output device908may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.

The electrical device900may include an audio input device924(or corresponding interface circuitry, as discussed above). The audio input device924may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device900may include a Global Navigation Satellite System (GNSS) device918(or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device918may be in communication with a satellite-based system and may determine a geolocation of the electrical device900based on information received from one or more GNSS satellites, as known in the art.

The electrical device900may include another output device910(or corresponding interface circuitry, as discussed above). Examples of the other output device910may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The electrical device900may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device900may be any other electronic device that processes data. In some embodiments, the electrical device900may comprise multiple discrete physical components. Given the range of devices that the electrical device900can be manifested as in various embodiments, in some embodiments, the electrical device900can be referred to as a computing device or a computing system.

FIG.10is a flow chart of a process1000according to some embodiments. At operation1002, the process includes providing a first electrically conductive layer including an antiferromagnetic (AFM) material (AFM electrode) on a substrate; at operation1004, the process includes providing a first layer including a multilayer stack of adjacent layers comprising ferromagnetic materials on the first electrically conductive layer. At operation1006, the process includes providing a second layer on the first layer; at operation1008, the process includes providing a third layer on the second layer, the third layer including a ferromagnetic material. At operation1010, the process includes forming a photoresist mask on a surface of the third layer facing away from the second layer; at operation1012, the process includes performing lithography by patterning a stack formed by the first layer, second layer and third layer in alignment with the photoresist mask to form a memory stack. At operation1014, the process includes patterning a second electrically conductive layer on the memory stack.

In embodiments, the phrase “A is located on B” means that at least a part of A is in direct physical contact or indirect physical contact (having one or more other features between A and B) with at least a part of B.

In the instant description, “A is adjacent to B” means that at least part of A is in direct physical contact with at least a part of B.

In the instant description, “B is between A and C” means that at least part of B is in or along a space separating A and C and that the at least part of B is in direct or indirect physical contact with A and C.

In the instant description, “A is attached to B” means that at least part of A is mechanically attached to at least part of B, either directly or indirectly (having one or more other features between A and B).

In the instant description, “A comprises a material including B” means that at least part of A is made of a material that includes B, although A may comprise materials in addition to the material that includes B as well.

The description may use the phrases “in an embodiment,” “according to some embodiments,” “in accordance with embodiments,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.

“Coupled” as used herein means that two or more elements are in direct physical contact, or that that two or more elements indirectly physically contact each other, but yet still cooperate or interact with each other (i.e. one or more other elements are coupled or connected between the elements that are said to be coupled with each other). The term “directly coupled” means that two or more elements are in direct contact.

As used herein, the term “module” refers to being part of, or including an ASIC, an electronic circuit, a system on a chip, a processor (shared, dedicated, or group), a solid state device, a memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.

As used herein, “electrically conductive” in some examples may refer to a property of a material having an electrical conductivity greater than or equal to 107Siemens per meter (S/m) at 20 degrees Celsius. Examples of such materials include Cu, Ag, Al, Au, W, Zn and Ni.

As used herein, an “integrated circuit component” may include one or more microelectronic dies.

In the corresponding drawings of the embodiments, signals, currents, electrical biases, or magnetic or electrical polarities may be represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, polarity, current, voltage, etc., as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

Throughout the specification, and in the claims, the term “connected” means a direct connection, such as electrical, mechanical, or magnetic connection between the elements that are connected, without any intermediary devices. The term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the elements that are connected or an indirect connection, through one or more passive or active intermediary devices. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

EXAMPLES

Some non-limiting example embodiments are set forth below.

Example 1 includes a memory device including: a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material.

Example 2 includes the subject matter of Example 1, wherein the AFM material includes at least one of: Co; Fe; Ni; Mn and Ga; Mn, Ge, and Ga; Bct and Ru; MnGa, MnGeGa, or Bct-Ru; Ni, Ga, S and one of Mn, Fe, Co or Zn; Bi and Se; W and Te; W and Se; Mo and Se; Mn and one of Ir, Pt or Ni; or a triangular, Kagomi, chiral or hexagonal AFM material that is either in a single crystal form or in an amorphous alloy form.

Example 3 includes the subject matter of Example 1, wherein respective ones of adjacent layers of a pair of the adjacent layers of the multilayer stack include respective ferromagnetic materials.

Example 4 includes the subject matter of Example 3, wherein the adjacent layers of the multilayer stack include alternating layers of a first ferromagnetic material and a second ferromagnetic material different from the first ferromagnetic material.

Example 5 includes the subject matter of Example 4, wherein the adjacent layers of the multilayer stack include alternating adjacent layers of Co and Ni.

Example 6 includes the subject matter of Example 1, wherein: the first layer includes a layer comprising a high tunneling magnetoresistance (high TMR) material (high TMR free layer) including Co, X and Pt, wherein X=Cu, Ni, Mn or Cr, the high TMR free layer adjacent one side of the second layer; and the third layer includes a layer comprising a high TMR material (high TMR fixed layer), the high TMR fixed layer adjacent another side of the second layer opposite the one side of the second layer, wherein the high TMR material of the high TMR free layer includes Co, X and Pt, wherein X=Cu, Ni, Mn or Cr, and is one of identical to or different from the high TMR material of the high TMR fixed layer.

Example 7 includes the subject matter of Example 6, the high TMR material of any one of the high TMR free layer or the high TMR fixed layer including CoαXβPtλ, wherein: X=Cu, Ni, Mn or Cr; α ranges from 20 to 50; β ranges from 0 to 30; λ ranges from 40 to 60; and α+β+λ=100.

Example 8 includes the subject matter of Example 6, wherein the first layer includes a layer comprising at least one of Ru, Ir, W, or Ta between the multilayer stack and the high TMR free layer. Example 9 includes the subject matter of Example 1, wherein the second layer includes: Mg and O; Al and O; Eu and O; or an alloy including O and at least one of Mg, Al or Eu.

Example 10 includes the subject matter of Example 1, wherein the third layer includes a synthetic antiferromagnetic layer.

Example 11 includes the subject matter of Example 1, wherein the memory device corresponds to a magnetic tunnel junction (MTJ) magnetic random access memory (MRAM) memory device, and the memory stack includes a MTJ device.

Example 12 includes the subject matter of Example 11, wherein the first electrode corresponds to a first terminal of the memory device, the second electrode includes a second terminal of the memory device at one end thereof, and a third terminal of the memory device at another end thereof, the memory device corresponding to a spin orbit torque (SOT) memory device.

Example 13 includes the subject matter of Example 12, wherein the second electrode has a footprint that extends beyond a footprint of the MTJ device.

Example 14 includes the subject matter of Example 1, wherein the first electrode corresponds to a first terminal of the memory device, and the second electrode corresponds to a second terminal of the memory device, the memory device corresponding to a spin orbit torque (STT) memory device.

Example 15 includes the subject matter of Example 14, wherein the second electrode has a footprint that corresponds to a footprint of the MTJ device.

Example 16 includes the subject matter of Example 1, further including a metal-oxide-semiconductor field-effect transistor electrically connected to at least one of the first electrode or the second electrode.

Example 17 includes an integrated circuit component including: an array of memory devices, individual ones of the memory devices including: a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material; and one or more sense amplifiers connected to second electrodes of the array of memory devices.

Example 18 includes the subject matter of Example 17, wherein the AFM material includes at least one of: Co; Fe; Ni; Mn and Ga; Mn, Ge, and Ga; Bct and Ru; MnGa, MnGeGa, or Bct-Ru; Ni, Ga, S and one of Mn, Fe, Co or Zn; Bi and Se; W and Te; W and Se; Mo and Se; Mn and one of Ir, Pt or Ni; or a triangular, Kagomi, chiral or hexagonal AFM material that is either in a single crystal form or in an amorphous alloy form.

Example 19 includes the subject matter of Example 17, wherein respective ones of adjacent layers of a pair of the adjacent layers of the multilayer stack include respective ferromagnetic materials.

Example 20 includes the subject matter of Example 19, wherein the adjacent layers of the multilayer stack include alternating layers of a first ferromagnetic material and a second ferromagnetic material different from the first ferromagnetic material.

Example 21 includes the subject matter of Example 20, wherein the adjacent layers of the multilayer stack include alternating adjacent layers of Co and Ni.

Example 22 includes the subject matter of Example 17, wherein: the first layer includes a layer comprising a high tunneling magnetoresistance (high TMR) material (high TMR free layer) including Co, X and Pt, wherein X=Cu, Ni, Mn or Cr, the high TMR free layer adjacent one side of the second layer; and the third layer includes a layer comprising a high TMR material (high TMR fixed layer), the high TMR fixed layer adjacent another side of the second layer opposite the one side of the second layer, wherein the high TMR material of the high TMR free layer includes Co, X and Pt, wherein X=Cu, Ni, Mn or Cr, and is one of identical to or different from the high TMR material of the high TMR fixed layer.

Example 23 includes the subject matter of Example 22, the high TMR material of any one of the high TMR free layer or the high TMR fixed layer including CoαXβPtλ, wherein: X=Cu, Ni, Mn or Cr; α ranges from 20 to 50; β ranges from 0 to 30; λ ranges from 40 to 60; and α+β+λ=100.

Example 24 includes the subject matter of Example 22, wherein the first layer includes a layer comprising at least one of Ru, Ir, W, or Ta between the multilayer stack and the high TMR free layer.

Example 25 includes the subject matter of Example 17, wherein the second layer includes: Mg and O; Al and O; Eu and O; or an alloy including O and at least one of Mg, Al or Eu.

Example 26 includes the subject matter of Example 17, wherein the third layer includes a synthetic antiferromagnetic layer.

Example 27 includes the subject matter of Example 17, wherein the memory device corresponds to a magnetic tunnel junction (MTJ) magnetic random access memory (MRAM) memory device, and the memory stack includes a MTJ device.

Example 28 includes the subject matter of Example 27, wherein the first electrode corresponds to a first terminal of the memory device, the second electrode includes a second terminal of the memory device at one end thereof, and a third terminal of the memory device at another end thereof, the memory device corresponding to a spin orbit torque (SOT) memory device.

Example 29 includes the subject matter of Example 28, wherein the second electrode has a footprint that extends beyond a footprint of the MTJ device.

Example 30 includes the subject matter of Example 17, wherein the first electrode corresponds to a first terminal of the memory device, and the second electrode corresponds to a second terminal of the memory device, the memory device corresponding to a spin orbit torque (STT) memory device.

Example 31 includes the subject matter of Example 30, wherein the second electrode has a footprint that corresponds to a footprint of the MTJ device.

Example 32 includes the subject matter of Example 17, further including a metal-oxide-semiconductor field-effect transistor electrically connected to at least one of the first electrode or the second electrode.

Example 33 includes an integrated circuit device assembly including: a printed circuit board; and a plurality of integrated circuit components attached to the printed circuit board, at least one of the integrated circuit components including: an array of memory devices, individual ones of the memory devices including: a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material; and one or more sense amplifiers connected to second electrodes of the memory devices.

Example 34 includes the subject matter of Example 33, wherein the AFM material includes at least one of: Co; Fe; Ni; Mn and Ga; Mn, Ge, and Ga; Bct and Ru; MnGa, MnGeGa, or Bct-Ru; Ni, Ga, S and one of Mn, Fe, Co or Zn; Bi and Se; W and Te; W and Se; Mo and Se; Mn and one of Ir, Pt or Ni; or a triangular, Kagomi, chiral or hexagonal AFM material that is either in a single crystal form or in an amorphous alloy form.

Example 35 includes the subject matter of Example 33, wherein respective ones of adjacent layers of a pair of the adjacent layers of the multilayer stack include respective ferromagnetic materials.

Example 36 includes the subject matter of Example 35, wherein the adjacent layers of the multilayer stack include alternating layers of a first ferromagnetic material and a second ferromagnetic material different from the first ferromagnetic material.

Example 37 includes the subject matter of Example 36, wherein the adjacent layers of the multilayer stack include alternating adjacent layers of Co and Ni.

Example 38 includes the subject matter of Example 33, wherein: the first layer includes a layer comprising a high tunneling magnetoresistance (high TMR) material (high TMR free layer) including Co, X and Pt, wherein X=Cu, Ni, Mn or Cr, the high TMR free layer adjacent one side of the second layer; and the third layer includes a layer comprising a high TMR material (high TMR fixed layer), the high TMR fixed layer adjacent another side of the second layer opposite the one side of the second layer, wherein the high TMR material of the high TMR free layer includes Co, X and Pt, wherein X=Cu, Ni, Mn or Cr, and is one of identical to or different from the high TMR material of the high TMR fixed layer.

Example 39 includes the subject matter of Example 38, the high TMR material of any one of the high TMR free layer or the high TMR fixed layer including CoαXβPtλ, wherein: X=Cu, Ni, Mn or Cr; α ranges from 20 to 50; β ranges from 0 to 30; λ ranges from 40 to 60; and α+β+λ=100.

Example 40 includes the subject matter of Example 38, wherein the first layer includes a layer comprising at least one of Ru, Ir, W, or Ta between the multilayer stack and the high TMR free layer.

Example 41 includes the subject matter of Example 33, wherein the second layer includes: Mg and O; Al and O; Eu and O; or an alloy including O and at least one of Mg, Al or Eu.

Example 42 includes the subject matter of Example 33, wherein the third layer includes a synthetic antiferromagnetic layer.

Example 43 includes the subject matter of Example 33, wherein the memory device corresponds to a magnetic tunnel junction (MTJ) magnetic random access memory (MRAM) memory device, and the memory stack includes a MTJ device.

Example 44 includes the subject matter of Example 43, wherein the first electrode corresponds to a first terminal of the memory device, the second electrode includes a second terminal of the memory device at one end thereof, and a third terminal of the memory device at another end thereof, the memory device corresponding to a spin orbit torque (SOT) memory device.

Example 45 includes the subject matter of Example 44, wherein the second electrode has a footprint that extends beyond a footprint of the MTJ device.

Example 46 includes the subject matter of Example 33, wherein the first electrode corresponds to a first terminal of the memory device, and the second electrode corresponds to a second terminal of the memory device, the memory device corresponding to a spin orbit torque (STT) memory device.

Example 47 includes the subject matter of Example 46, wherein the second electrode has a footprint that corresponds to a footprint of the MTJ device.

Example 48 includes the subject matter of Example 33, further including a metal-oxide-semiconductor field-effect transistor electrically connected to at least one of the first electrode or the second electrode.

Example 49 includes a method to be performed at a memory device including a memory stack coupled between a first electrode and a second electrode, the method including: performing a write operation on the memory device including: determining an amplitude of a write current Iwto be generated along the second electrode, Iwbased on a desired resistance of the memory stack, the desired resistance being one of more than two resistances programmable to the memory stack; causing the write current Iwto flow along the second electrode to program the desired resistance to the memory stack; and performing a read operation on the memory device including; causing a read current to flow from the first electrode to the second electrode; and determining a resistance of the memory stack.

Example 50 includes the subject matter of Example 49, further including, during the read operation, controlling a read current of a subsequent memory device electrically coupled to the memory device by using the read current flowing from the first electrode to the second electrode.

Example 51 includes the subject matter of Example 49, further including controlling the read current flowing from the first electrode to the second electrode by using a read current from a prior memory device electrically coupled to the memory device.