MEMORY SYSTEM AND METHOD

A memory system includes a nonvolatile memory device and a controller configured to generate page data of a first predetermined size, which includes a plurality of error correction frames, each of which has a second predetermined size, and write the generated page data into the nonvolatile memory device. The plurality of error correction frames includes a first error correction frame and a second error correction frame. The first error correction frame includes first data and a first error correction data for correcting the first data. The second error correction frame includes second data and a second error correction data for correcting the second data. The first error correction frame and the second error correction frame partially overlap with each other. An overlapping area of the first and second error correction frames includes a part of the first data and a part of the second data.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-110657, filed Jul. 5, 2023, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a memory system and a method.

BACKGROUND

A memory system calculates, from data, a parity for error correction of the data. The memory system generates an error correction code (ECC) frame of a fixed size that includes the data and the parity. The memory system writes the ECC frame into a memory device.

The memory system may write variable-length data into the memory device. One example of the variable-length data is compressed data. When the variable-length data is written, the ECC frame may include invalid data depending on the size of the variable-length data.

DETAILED DESCRIPTION

Embodiments provide a memory system and a method where a storage area is effectively used.

In general, according to an embodiment, a memory system includes a nonvolatile memory device and a controller configured to generate page data of a first predetermined size, which includes a plurality of error correction frames, each of which has a second predetermined size, and write the generated page data into the nonvolatile memory device. The plurality of error correction frames in the generated page data includes a first error correction frame and a second error correction frame subsequent thereto. The first error correction frame includes first data and a first error correction data for correcting the first data. The second error correction frame includes second data and a second error correction data for correcting the second data. The first error correction frame and the second error correction frame partially overlap with each other. An overlapping area of the first and second error correction frames includes a part of the first data and a part of the second data.

Hereinafter, embodiments will be described with reference to the drawings. The following description is an example of a device or a method for implementing the technical ideas of the embodiments, and the technical ideas of the embodiments are not limited in structures, shapes, arrangement, materials, and the like of components to those described below. Of course, modifications that can be easily conceived by those skilled in the art are included in the range of the disclosure. To clarify the description, in the drawings, the size, thickness, planar dimension, shape, or the like of each of elements may be changed from an actual embodiment and schematically illustrated. A plurality of drawings may also include elements having different dimensional relationships or ratios. In a plurality of drawings, corresponding elements are represented by the same reference numerals, and the repeated description may not be made. Some elements may be represented by a plurality of names. However, the names are merely examples, and the use of other names for the elements is not denied. The use of other names for elements that are not represented by a plurality of names is also not denied. In the following description, “connection” represents not only direct connection but also connection via another element.

First Embodiment

FIG.1is a diagram illustrating an example of the summary of a configuration of a memory system10according to a first embodiment. The memory system10includes a nonvolatile memory device12. An example of the nonvolatile memory is a NAND flash memory. In the memory system10, an interface14for exchanging a command and data with a host (not illustrated inFIG.1) is provided.

The memory device12stores a plurality of pages. Each page includes a plurality of ECC frames.FIG.1illustrates an example where one page includes four ECC frames. The ECC frame includes data and a parity. Examples of sizes are as follows. The size of the data is 1024 bytes, the size of the parity is 118 bytes, the size of the ECC frame is 1142 bytes, and the size of the page is 4568 bytes.

The page may consist of a single ECC frame instead of a plurality of ECC frames.

During writing, the memory system10calculates a parity of 118 bytes from a plurality of (for example, 8 pieces) of units of data of 128 bytes (1024 bytes in total). The memory system10generates an ECC frame of 1142 bytes from the data and the parity, and writes the ECC frame into the memory device12.

During reading, the memory system10reads the ECC frame from the memory device12, and takes out the parity and the data from the ECC frame. The memory system10executes error correction of the data based on the parity. To reduce a memory usage or to improve a data transmission rate, the memory system10may compress data, and may write the compressed data into the memory device12.

FIG.2is a diagram illustrating a comparative example of a configuration of ECC frames when a comparative memory system compresses data and writes the compressed data into a memory device.

The ECC frame includes a data area24, an invalid area26, and a parity area28. The data area24includes a data stream D. The data stream D corresponds to the data inFIG.1. The invalid area26includes invalid data. An example of a size of each of the areas24,26, and28is as follows. The total size of the data area24and the invalid area26is 1024 bytes. The size of the parity area28is 118 bytes. The size of each of the data area24and the invalid area26is variable.

The comparative memory system compresses unit data of a fixed size, for example, 128 bytes, and adds at least one piece of compressed data into the data area24of an ECC frame0as the data stream D. An example of a compression method is a lossless compression method. In the lossless compression method, the compressed data has a variable-length size.

When the size of the data stream D exceeds 1024 bytes, that is, when the data area24has no free area, the comparative memory system stops adding the compressed data into the data area24. Since the compressed data has a variable-length size, a timing when the data area24has no free area is generally a timing when a part of the compressed data has already been added into the data area24.

For example, when the data area24has no free area at a timing at which a part of compressed data of unit data22has been added into the data area24of the ECC frame0as a data stream D0, the comparative memory system stops adding the compressed data. After stopping the adding, the comparative memory system adds the entirety of the compressed data of the unit data22into a head portion of the data area24of an ECC frame1as a data stream D1. Hereinafter, the comparative memory system sequentially adds the compressed data into the data area24of the ECC frame1.

A part of the compressed data of the unit data22that is included in the data area24of the ECC frame0is invalid data that cannot be used even after being read later. When the adding of a part of the compressed data is stopped, the data area24including the invalid data is changed to the invalid area26. The average size of the invalid area26varies depending on conditions and is, for example, about several tens of bytes per ECC frame. Therefore, several percentages of the storage area of the memory device may be the invalid area(s)26.

The comparative memory system calculates a parity P0based on the data stream D0in the data area24. The memory system10adds the parity P0into the parity area28.

FIG.3is a diagram illustrating another comparative example of a configuration of ECC frames when a comparative memory system compresses data and writes the compressed data into a memory device. A data compression method and sizes of data and each area are the same as those of the comparative example ofFIG.2.

An ECC frame other than a final ECC frame of a page includes a data area34of 1024 bytes and a parity area38of 118 bytes, and does include no invalid area. The final ECC frame of the page includes a data area of 1024 bytes, a parity area, and an invalid area.

The comparative memory system compresses data in units of 128 bytes, and adds at least one piece of compressed data of a variable-length size into the data area34as the data stream D.

When the size of the data stream D exceeds 1024 bytes, that is, when the data area34has no free area, the memory system10stops adding the compressed data into the data area34.

For example, when the data area34has no free area at a timing at which a part of compressed data of data32has been added into the data area34of the ECC frame0, the comparative memory system stops adding the compressed data into the data area34of the ECC frame0. After stopping the adding, the comparative memory system adds the remaining part of the compressed data of the data32into a head portion of the data area34of the ECC frame1as the data stream D0. Hereinafter, the comparative memory system sequentially adds the compressed data into the data area34of the ECC frame1.

The comparative memory system calculates the parity P0based on the data area34of the ECC frame0and the data stream D0in the data area34of the ECC frame1. The comparative memory system adds the parity P0into the parity area38.

In the example ofFIG.2, the data area24of the ECC frame1includes the entirety of the compressed data of the unit data22of 128 bytes as the data stream D1. Therefore, each of the ECC frames includes the invalid area26. In the example ofFIG.3, one piece of compressed data of the data32of 128 bytes is divided into two pieces of sub-compressed data. Each of the two ECC frames0and1includes two pieces of sub-compressed data as the data stream D0. The final ECC frame of the page may include an invalid area, but the other ECC frames include no invalid area. Therefore, the size of the invalid area in the example ofFIG.3is less than the size of the invalid area in the example ofFIG.2.

However, in the example ofFIG.3, to read one piece of the unit data32, two ECC frames may need to be read. Therefore, during data reading, the number of times of data communication with a host32increases, a band of the interface is more consumed, and the performance may be deteriorated.

FIGS.4A and4Bare diagrams illustrating an example of a configuration of ECC frames in the memory system10according to the first embodiment.

Each page includes four ECC frames. Two adjacent ECC frames have an overlapping area.FIG.4Aillustrates an example of a configuration of ECC frames0and1.FIG.4Billustrates an example of a configuration of ECC frames2and3.

The ECC frame0includes six areas R0to R5. The size of each of the areas R0, R1, R2, and R3is fixed. The total size of the areas R4and R5is fixed. The size of each of the areas R4and R5is variable. The size of the area R0is the same as the total size of the areas R4and R5.

The area R0includes a head portion of the data stream D0. The area R1includes a header H0. The header H0represents an address of the memory device12corresponding to the head of the data stream D0. The area R2includes the parity P0of the data stream D0. The areas R3and R4include the data stream D0. The area R5includes a head portion of the data stream D1.

The areas R4and R5are also included in the ECC frame1and are overlapping areas of the ECC frame0and the ECC frame1. An end portion of the data stream D0is added up to halfway (area R4) of the overlapping area. The data stream D1is added from halfway (area R5) of the overlapping area.

The ECC frame1includes seven areas R4to R10. The size of each of the areas R6, R7, and R8is fixed. The total size of the areas R9and R10is fixed. The size of each of the areas R9and R10is variable. The total size of the areas R9and R10is the same as the total size of the areas R4and R5.

The area R6includes a header H1. The header H1represents an address of the memory device12where the head of the data stream D1is stored. The area R7includes a parity P1of the data stream D1. The areas R8and R9include the data stream D1. The area R10includes a head portion of a data stream D2.

The areas R9and R10are also included in the ECC frame2and are overlapping areas of the ECC frame1and the ECC frame2. An end portion of the data stream D1is added up to halfway (area R9) of the overlapping area. The data stream D2is added from halfway (area R10) of the overlapping area.

The ECC frame2includes seven areas R9to R15. The size of each of the areas R11, R12, and R13is fixed. The total size of the areas R14and R15is fixed. The size of each of the areas R9and R10is variable. The total size of the areas R9and R10is the same as the total size of the areas R4and R5.

The area R11includes a header H2. The header H2represents an address of the memory device12corresponding to the head of the data stream D2. The area R12includes a parity P2of the data stream D2. The areas R13and R14include the data stream D2. The area R15includes a head portion of a data stream D3.

The areas R14and R15are also included in the ECC frame3and are overlapping areas of the ECC frame2and the ECC frame3. An end portion of the data stream D2is added up to halfway (area R14) of the overlapping area. The data stream D3is added from halfway (area R15) of the overlapping area.

The ECC frame3includes six areas R14to R19. The size of each of the areas R16and R17is fixed.

The area R16includes a header H3. The header H3represents an address of the memory device12corresponding to the head of the data stream D3. The area R17includes a parity P3of the data stream D3. The area R18includes the data stream D3. The area R19is an invalid area including invalid data. The invalid area R19corresponds to the invalid area26(FIG.2).

The sizes of the areas R1, R6, R11, and R16including the header are the same as each other. The sizes of the areas R2, R7, R12, and R17including the parities are the same as each other. The total size of the overlapping areas R4and R5, the total size of the overlapping areas R9and R10, and the total size of the overlapping areas R14and R15are the same as each other.

The memory system10according to the first embodiment generates ECC frames such that some of adjacent ECC frames overlap each other. Each ECC frame includes the entirety of one data stream, and non-final ECC frames of one page do not include the invalid area R19. A boundary between a first data stream and a second data stream is positioned in the overlapping area. As a result, the invalid area of the memory device can be reduced without increasing the number of times of data transmission during reading.

All the boundaries between the two data streams do not need to be positioned in the overlapping areas. At least one of the boundaries between the two data streams does not need to be positioned in the overlapping area.FIGS.5A and5Bare diagrams illustrating another example of the configuration of the ECC frames in the memory system10according to the first embodiment.

Each page includes four ECC frames. Two adjacent ECC frames have an overlapping area.FIG.5Aillustrates an example of a configuration of the ECC frames0and1.FIG.5Billustrates an example of a configuration of the ECC frames2and3.

The ECC frame0includes six areas R30to R35. The size of each of the areas R30, R31, R32, and R35is fixed. The sizes of the areas R33and R34are variable. The size of the area R30is the same as the size of the area R35.

The area R30includes a head portion of the data stream D0. The area R31includes the header H0. The header H0represents an address of the memory device12corresponding to the head of the data stream D0. The area R32includes the parity P0of the data stream D0. The area R33includes the data stream D0. The area R34includes invalid data. The invalid area R34corresponds to the invalid area26(FIG.2).

The area R35is also included in the ECC frame1and is an overlapping area of the ECC frame0and the ECC frame1. The overlapping area R35includes the head portion of the data stream D1of the ECC frame1without including the data stream D0of the ECC frame0.

The ECC frame1includes six areas R35to R40. The total size of the areas R36and R37is fixed. The size of the area R38is variable. The total size of the areas R39and R40is fixed. The total size of the areas R36and R37is the same as the size of the area R35.

The area R36includes the header H1. The header H1represents an address of the memory device12corresponding to the head of the data stream D1. The area R37includes the parity P1of the data stream D1. The area R38includes the data stream D1.

The areas R39and R40are also included in the ECC frame2and are overlapping areas of the ECC frame1and the ECC frame2. An end portion of the data stream D1is added up to halfway (area R39) of the overlapping area. The data stream D2is added from halfway (area R40) of the overlapping area.

The ECC frame2includes seven areas R39to R45. The size of each of the areas R41, R42, and R43is fixed. The total size of the areas R44and R45is fixed. The size of each of the areas R44and R45is variable. The total size of the areas R39and R40is the same as the total size of the areas R44and R45.

The area R41includes the header H2. The header H2represents an address of the memory device12where the head of the data stream D2is stored. The area R42includes the parity P2of the data stream D2. The areas R43and R44include the data stream D2. The area R45includes the head portion of the data stream D3.

The areas R44and R45are also included in the ECC frame3and are overlapping areas of the ECC frame2and the ECC frame3. An end portion of the data stream D2is added up to halfway (area R44) of the overlapping area. The data stream D3is added from halfway (area R45) of the overlapping area.

The ECC frame3includes six areas R44to R49. The size of each of the areas R46and R47is fixed. The total size of the areas R48and R49is fixed. The size of each of the areas R48and R49is variable.

The area R46includes the header H3. The header H3represents an address of the memory device12corresponding to the head of the data stream D3. The area R47includes the parity P3of the data stream D3. The area R48includes the data stream D3. The area R49is an invalid area including invalid data. The invalid area R49corresponds to the invalid area26(FIG.2).

The sizes of the areas R31, R36, R41, and R46including the header are the same as each other. The sizes of the areas R32, R37, R42, and R47including the parity are the same as each other. The size of the overlapping area R35, the total size of the overlapping areas R39and R40, and the total size of the overlapping areas R44and R45are the same as each other.

In the example ofFIGS.5A and5B, the overlapping area R35of the ECC frame0and the ECC frame1does not include the data stream D0of the ECC frame0and does not include the head portion of the data stream D1of the ECC frame1. Therefore, the invalid area R34is generated in the ECC frame0.

When the probability that a boundary between two data streams is positioned in the overlapping area increases, the size of the invalid area is small. When all the boundaries between the two data streams are positioned in the overlapping areas, the size of the invalid area is the smallest. To implement the ECC frames ofFIGS.4A and4B, when the number of pieces of compressed data increases by one, the amount of increase in the size of the data stream (in other words, the amount of decrease in the free size of the data area) only needs to be less than or equal to the size of the overlapping area. When uncompressed data is in units of 128 bytes, the maximum size of compressed data can be 128 bytes plus 1 bit. When the number of pieces of compressed data increases by one, the maximum value of the amount of increase in the size of the data stream is 128 bytes plus 1 bit. Therefore, as long as the size of the overlapping area of the ECC frames is set to 128 bytes plus 1 bit, the ECC frames ofFIGS.4A and4Bare generated. Even with the size of 128 bytes, the ECC frames ofFIGS.4A and4Bare generated with high probability.

When the size of the overlapping area increases, the size of the parity area also increases. Therefore, the size of the data area decreases. As the size of the overlapping area decreases less than 128 bytes, the ECC frames ofFIGS.5A and5Bare generated with high probability.

In the examples ofFIGS.4A to5B, the areas other than the overlapping areas, for example, the areas R1, R6, R11, and R16include the header. However, the overlapping area may include the header depending on the performance and the cost required for the memory system. For example, the head or the end of the overlapping area may include the header. A memory device other than the memory device that stores data may include the header.

Formats (the size/storage location of the data stream, the size/storage location of the parity, and the like) of four ECC frames that partially overlap with adjacent ECC frames may be the same as or different from each other. When the formats are the same, plural types of parity generation processes or error correction processes are not necessary, and only one type of parity generation process or error correction process may be used.

In the memory system10according to the first embodiment, when variable-length data such as compressed data is stored, the invalid area can be reduced. In the comparative example illustrated inFIG.2, each of the ECC frames includes one invalid area. However, in the first embodiment illustrated inFIGS.4A and4B, four frames (page) include one invalid area. Therefore, the number of invalid areas can be reduced to about ¼, and the size of the data stream can be increased.

In the first embodiment illustrated inFIGS.4A to5B, even when any unit data (128 bytes) is sent to the host, the number of ECC frames that is required to be decoded and decompressed is one. In the comparative example illustrated inFIG.3, a plurality of (generally, two; however, when the size of the unit data is large, three or more) ECC frames include one piece of compressed data of unit data. To obtain one piece of unit data, a plurality of ECC frames may need to be decoded and decompressed. In the first embodiment illustrated inFIGS.4A to5B, only one ECC frame needs to be decoded and decompressed to obtain one piece of unit data. In the first embodiment illustrated inFIGS.4A to5B, as compared to the comparative example illustrated inFIG.3, the number of times of data communication with the host32during data reading is reduced, the consumption of the band of the interface is reduced, and the performance is improved.

The advantage of the first embodiment will be described using specific values.FIGS.6A and6Bare diagrams illustrating an example of specific sizes of the ECC frames in the memory system10according to the first embodiment. InFIGS.6A and6B, the size (unit: byte) is filled in each of the regions ofFIGS.4A and4B.

It is assumed that the storage area of the memory device12illustrated inFIG.1includes a page (4568 bytes) including four ECC frames. It is assumed that the size of the data area of the ECC frame is 1024 bytes. It is assumed that the memory system10compresses one unit data (128 bytes) and generates a data stream from a plurality of pieces of compressed data. It is assumed that the error correction capability required for the memory system10is 60 bits per ECC frame. When a BCH code is used as the ECC, a code that satisfies the following relationship can be implemented, where p (bit) represents the size of the parity, k (bit) represents the size of the compressed data, and t represents the number of correctable bits per ECC frame (m represents an integer).

Here, t=60, and k=8192 (=1024×8). The minimum value of m that satisfies Expressions 1 and 2 is 14. Based on Expression 1, the minimum value of the parity bit length p is 840 bits (105 bytes). The minimum value of the size required for four ECC frames is 4516 (=(1024+105)×4) bytes. The size of four ECC frames has surplus 52 bytes compared to the page size (4568 bytes). In the comparative example illustrated inFIG.2, simply by increasing the size of the ECC frame, the storage capacity can be improved by about 52 bytes per page.

Next, the improvement of the storage capacity according to the first embodiment will be described. In the ECC frames according to the first embodiment, compared to the ECC frames illustrated inFIG.3, the size of the overlapping area (128 bytes that is the same as the data unit) and the size of the header (2 bytes) are increased, and the size of the ECC frames is increased. Therefore, the error correction capability needs to be increased correspondingly.FIGS.6A and6Billustrate an example of the configuration of the ECC frames where the size of the parity is increased as much as possible to improve the error correction capability while maintaining the total data size per page to be 4096 bytes.

It is assumed that the size of the ECC frame is 1238 bytes (data: 1120 bytes+header: 2 bytes+parity: 116 bytes). The number of correctable bits is 66 bits (=p/m=116×8/14). The number of correctable bits (66 bits) is 1.1 (=6.6/6.0) times of 60 bits that is the original number of bits. An increase rate in the number of correctable bits corresponds to an increase rate of 1.097 (=1238/1129) in the size of the ECC frames.

It is assumed that the average size per invalid area is 40 bytes. In the comparative example illustrated inFIG.2, the size of the invalid area per page is 160 bytes. In the first embodiment illustrated inFIGS.6A and6B, the size of the invalid area per page is 40 bytes. The size of the invalid area according to the first embodiment illustrated inFIGS.6A and6Bis reduced by 120 bytes as compared to the comparative example illustrated inFIG.2. That is, it can be said that the storage capacity is improved by 120 bytes. The amount of improvement of the storage capacity in the comparative example illustrated inFIG.2is 52 bytes. Therefore, in the first embodiment, it can be said that the storage capacity can be improved by 68 bytes (=120-52) per page (data: 4096 bytes) as compared to the comparative example.

FIG.7is a diagram illustrating an example of an information processing system1according to the first embodiment. The information processing system1includes the memory system10and the host32.

The host32is an information processing apparatus that accesses the memory system10. The memory system10may be used as a main storage of the host32. The memory system10may be built in the host32, or may be provided outside the host32and connected to the host32via a cable or a network. The host32may be a server (e.g., storage server) that stores a large amount of various types of data in the memory system10. The host32may be a personal computer. The memory system10may be a system for business use that is incorporated into a server of a data center or the like. The memory system10may be a system for personal use that is incorporated into a personal computer. Examples of the memory system10include a solid state drive (SSD) and a hard disk drive (HDD). In the following, the memory device12will be referred to as the NAND flash memory12.

The memory system10includes the NAND flash memory12, a dynamic random access memory (DRAM)44, and a controller42. Instead of the NAND flash memory12, a NOR flash memory, a magneto-resistive random access memory (MRAM), a phase change random access memory (PRAM), a resistive random access memory (ReRAM), or a ferroelectric random access memory (FeRAM) may be used. The NAND flash memory12includes a memory cell array including a plurality of memory cells that are arranged in a matrix configuration. The memory cell array may have a two-dimensional structure or a three-dimensional structure.

The DRAM44is an example of a volatile memory. The DRAM44is, for example, a DRAM based on a double data rate3low voltage (DDR3L) specification. The DRAM44includes a write buffer46, a read buffer48, and an address conversion table50. Data that is supplied from the host32to the memory system10and is being written into or is not written into the NAND flash memory12is stored in the write buffer46. Data that is read from the NAND flash memory12and is being transmitted to or is not transmitted to the host32is stored in the read buffer48. The DRAM44functions as a temporary buffer for data that is used during the operation of the memory system10or software that is executed in the controller42. The DRAM44may be provided in the controller42without providing the outside of the controller42. As the volatile memory, a static random access memory (SRAM) capable of high-speed access may be used instead of the DRAM44.

According to a command transmitted from the host32, the controller42compresses data transmitted from the host32and writes the compressed data into the NAND flash memory12, or reads compressed data from the NAND flash memory12and decompresses the read data. The controller42may be configured with a circuit such as a system on a chip (SoC). The controller42controls an operation of the memory system10. The controller42includes a host interface (referred to as a host I/F circuit)52, a CPU54, a NAND interface (referred to as a NAND I/F circuit)56, a DRAM interface (referred to as a DRAM I/F circuit)58, a compression circuit60, a decompression circuit62, an ECC encoder64, and an ECC decoder66.

The host I/F circuit52communicates with the host32. The communication with the host32is based on, for example, PCI Express® specification. The host I/F circuit52receives a command from the host32.

The NAND I/F circuit56is a memory control circuit that controls the NAND flash memory12under the control of the CPU54. The NAND I/F circuit56and the NAND flash memory12are connected to each other via a plurality of channels Ch. The NAND flash memory12includes a plurality of memory chips. The plurality of memory chips are connected to the channels, respectively.

The DRAM I/F circuit58is a DRAM control circuit that controls the DRAM44under the control of the CPU54.

The compression circuit60compresses data transmitted from the host32using a lossless compression method. The compressed data is variable-length data. The ECC encoder64generates an ECC frame from the compressed data. The NAND I/F circuit56writes ECC frames of one page into the NAND flash memory12.

The NAND I/F circuit56reads page data including a target ECC frame from the NAND flash memory12. The ECC decoder66executes an error correction process of the compressed data extracted from the ECC frame. The decompression circuit62decompresses the compressed data on which the error correction process is executed using a lossless decompression method. The host I/F circuit52transmits the decompressed data to the host32.

Some or all of the compression circuit60, the decompression circuit62, the ECC encoder64, and the ECC decoder66may be implemented by the CPU54executing firmware. Some or all of the compression circuit60, the decompression circuit62, the ECC encoder64, and the ECC decoder66may be provided outside the memory system10. The outside of the memory system10is, for example, the host32or a server to which the host32is further connected.

FIG.8is a diagram illustrating an example of the address conversion table50according to the first embodiment. The address conversion table50stores: an ECC frame ID corresponding to a host address; and information (referred to as an offset) of a head location of a data area in the ECC frame identified with the ECC frame ID.

FIG.9is a flowchart illustrating an example of a write process according to the first embodiment. The write process illustrated inFIG.9is executed each time a write command is issued from the host32.

The CPU54receives the write command transmitted from the host32(S102).

The CPU54writes write data into the write buffer46according to the content of the write command, and also writes a host address designated by the write command into the write buffer46(S104). The write data is data in units of a predetermined size. The predetermined size is, for example, 128 bytes.

The CPU54notifies write completion to the host32(S106), and ends the process. The notification may be skipped.

FIG.10is a flowchart illustrating the example of the write process according to the first embodiment. When data for four ECC frames is stored in the write buffer46, the write process illustrated inFIG.10is executed once.FIGS.11A to11Care diagrams illustrating an example of generating ECC frames according to the first embodiment.

The CPU54reads the unit data stored in the write buffer46, compresses the unit data using the compression circuit60, and links a plurality of pieces of compressed data to generate a first data stream D0for a first ECC frame (S108).FIG.11Aillustrates an example of the unit data read from the write buffer46.

When the first unit data is read, the CPU54sets the compressed data as the data stream D0. When the second or subsequent unit data is read, the CPU54adds the compressed data to the data stream D0, and sets the addition result as a new data stream D0.

The CPU54generates the data stream such that the compressed data of the unit data of 128 bytes is necessarily added to one data stream without being divided and added to two data streams. When the size of a certain data stream exceeds an upper limit size as a result of adding certain compressed data to the certain data stream, the CPU54adds the certain compressed data to the next data stream of the certain data stream without adding the certain compressed data to the certain data stream.

The ECC frame has a fixed size. Since the compressed data is variable-length data, the size of the data stream needs to be the upper limit size or less. The upper limit size varies depending on the data stream. The upper limit size of the first data stream D0is 1120 bytes. The upper limit size of a second data stream D1is 992 bytes+α0. α0 represents a surplus size of a difference between the upper limit size of the first data stream D0and the actual size of the first data stream D0. The upper limit size of a third data stream D2is 992 bytes+α1. α1 represents a surplus size of a difference between the upper limit size of the second data stream D1and the actual size of the second data stream D1. The upper limit size of a fourth data stream D3is 992 bytes+α2. α2 represents a surplus size of a difference between the upper limit size of the third data stream D2and the actual size of the third data stream D2.

For example, assuming that the size of the first data stream D0is 1110 bytes and the surplus size is 10 bytes, the CPU54generates the second data stream D1having a size of 992+10=1002 bytes or less.

The CPU54reads the unit data stored in the write buffer46, compresses the unit data using the compression circuit60, and links the compressed data to generate the second to fourth data stream D1to D3for second to fourth ECC frames (S110).FIG.11Billustrates an example of the data streams D0to D3.

The CPU54adds IDs of the ECC frames and data locations (offsets) in the ECC frames in which the data streams D0to D3are included into the address conversion table50(FIG.8) (S112).

The CPU54calculates headers H0to H3to be inserted into the data streams D0to D3(S114). A head location of the first data stream D0is a head location of the ECC frame, and thus the header H0is always 0. Therefore, the header H0may not exist. However, by adding the header, the formats of the four ECC frame can be made the same. Therefore, a decoding process by the ECC decoder66can be unified.

Assuming that the size of the first data stream D0is 1110 bytes, the second data stream D1is arranged in a second half (10 bytes) area of an overlapping area (128 bytes) of the ECC frames0and1. Since a head location of the second data stream D1is at the118(=128-10) byte location from the head of the ECC frame1, the header H1is 118. Similarly, the remaining headers H2and H3are also generated.FIG.11Cillustrates an example of the arrangement of the data streams and the headers in the ECC frames.

The CPU54generates ECC parities P0to P3for the data streams D0to D3and the headers H0to H3, respectively, and inserts the ECC parities P0to P3into the ECC frames0to3(S116). Two adjacent ECC frames partially overlap each other, and data of the overlapping area are used for generating the parities of the two adjacent ECC frames.

The CPU54writes the four ECC frames generated as described above as data of one page into the NAND flash memory12via the NAND I/F circuit56(S118). One example of the page to be written into the NAND flash memory12is the same as illustrated inFIGS.6A and6B.

FIG.12is a flowchart illustrating an example of a read process according to the first embodiment.FIGS.13A to13Eare diagrams illustrating an example of a data decompression process according to a first embodiment.

The CPU54receives a read command transmitted from the host32(S202).

The CPU54determines whether data corresponding to a host address designated by the read command is stored in the write buffer46(S204).

When the CPU54determines that the data corresponding to the host address is stored in the write buffer46(S204; YES), the CPU54transmits the data to the host32(S206).

When the CPU54determines that the data corresponding to the host address is not stored in the write buffer46(S204; NO), the CPU54reads the ECC frame ID and the offset corresponding to the host address from the address conversion table50(S208).FIG.13Aillustrates an example of a page to be written into the NAND flash memory12.FIG.13Ais the same asFIGS.6A and6B.

The CPU54reads page data including the ECC frame represented by the ECC frame ID from the NAND flash memory12via the NAND I/F circuit56(S210).FIG.13Billustrates an example of the read ECC frames. Each of the ECC frames also includes data of adjacent ECC frames.

The CPU54executes an error correction process of the ECC frame using the ECC decoder66based on the parity in the ECC frame (S212).FIG.13Cillustrates an example of the ECC frame on which the error correction process is executed.

The CPU54obtains the header from the ECC frame (S214). The CPU54obtains the data stream from the ECC frame based on the header (S216).FIG.13Dillustrates an example of the data streams D1and D2.

The CPU54decompresses the data stream using the decompression circuit62to acquire a plurality of pieces of data (uncompressed data) (S218).FIG.13Eillustrates an example of a plurality of pieces of uncompressed data. The decompression circuit62cannot recognize the end of the data stream. Therefore, an algorithm capable of decompressing data even when an accurate data size cannot be determined is used. In a method of compressing 0 of 8 bytes into 1 bit, even when the size of compressed data cannot be determined, the decompression process can be executed. When a decompression method that requires an accurate size of compressed data is used, a data arrangement where the overlapping area includes the header may be adopted.

The CPU54refers to the address conversion table50, selects data represented by the offset in the acquired data, and transmits the selected data to the host32(S220).

The CPU54notifies read completion to the host32(S222). The notification may be skipped.

In the memory system10according to the first embodiment, even when surplus uncompressed data is acquired by decompressing compressed data in a situation where the end of the compressed data is not recognized, an offset representing valid data is written in the address conversion table50at the stage of the write process. Therefore, the selection of surplus uncompressed data can be prevented. Thus, the memory system10can transmit only correct data to the host32(S220).

In the first embodiment, the ECC frames include the overlapping area, and the overlapping area includes the data streams of two ECC frames. Therefore, the ECC frames can effectively use the storage area without including the invalid area.

Second Embodiment

FIGS.14A and14Bare diagrams illustrating a specific example of a configuration of ECC frames in a memory system10according to a second embodiment. In the first embodiment, the ECC frame other than the overlapping area includes the parity. In the second embodiment, two types of parities p and P are calculated. The overlapping area includes the parity p of the second type. The ECC frame other than the overlapping area includes the parity P of the first type and the parity p of the second type. An example of the parity p of the second type is a horizontal parity. An example of the parity P of the first type is a vertical parity.

As inFIGS.1,6A and6B, one page includes four ECC frames, and two adjacent ECC frames in the four ECC frames overlap each other. In each of the ECC frames, the data stream D is divided into areas having a predetermined size. The area of the ECC frame other than the overlapping area includes data of the plurality of divided areas. The memory system10calculates the horizontal parity p for each of the divided areas. The horizontal parity p is adjacent to data of the divided area. The overlapping area of the ECC frame0includes an end portion of a data stream0and a head portion of a data stream1. The size of data DO of the head of the ECC frame0is the same as the size of data in the overlapping area. The memory system10calculates the vertical parity P0for the data streams0and1in the ECC frame0. The vertical parity P0is adjacent to the parity p of the data DO of the head in the ECC frame0. In the ECC frames1to3, the vertical parity P1, P2, and P3are adjacent to the corresponding overlapping areas at the heads of the ECC frames1,2, and3, respectively.

In the second embodiment, the overlapping area includes the horizontal parity p that is shared by the two ECC frames. Therefore, a parity that is used for one ECC frame and a parity that is used for another ECC frame do not need to be separately stored, and the size of the parity can be reduced.

Third Embodiment

FIG.15is a diagram illustrating a specific example of a configuration of ECC frames in a memory system10according to a third embodiment. In the first and second embodiments, the four ECC frames are linked to each other using the overlapping area. However, in the third embodiment, two ECC frames are linked to each other using the overlapping area.FIG.15illustrates a specific example of a configuration of ECC frames0and1.

The ECC frame0includes data streams D0and D1and a parity P0. The parity P0is calculated from the data streams D0and D1, and the size of the parity P0is fixed. A head portion of the ECC frame0includes the parity P0. The overlapping area includes an end portion of the data stream D0and a head portion of the data stream D1. The parity P0and the data streams D0and D1are arranged in ascending order of address. As a result, the parity P0and the data streams D0and D1are written and read in this order.

The ECC frame1includes the data streams D0and D1and a parity P1. The parity P1is calculated from the data streams D0and D1, and the size of the parity P1is fixed. An end portion of the ECC frame0includes the parity P1. The overlapping area includes the end portion of the data stream D0and the head portion of the data stream D1. The parity P1and the data streams D1and DO are arranged in descending order of address. As a result, the parity P1and the data streams D1and DO are written and read in this order. Alternatively, the parity P1and the data streams D1and DO may be written and read in ascending order of address, and the data order may be changed at the stage of, for example, the ECC process.

In the third embodiment, the head location of a data stream D1is shifted from an end portion of the ECC frame1by the amount of the parity. Therefore, the header is unnecessary, and the storage capacity increases.

Even in the example ofFIG.15, although the end location or the size of the data stream cannot be determined, as described in the first embodiment, there is no problem as long as a decompression algorithm capable of decompressing data without using an accurate data size is used.

Fourth Embodiment

In the above-described embodiments, when a certain ECC frame is read, a part of a data stream of an adjacent ECC frame is also read. Therefore, when one ECC frame is read, the amount of data transmitted from the NAND flash memory12to the controller42slightly increases. However, when the ECC frames including the overlapping area are continuously read, the amount of data transmitted from the NAND flash memory12to the controller42can be reduced by reading the overlapping area only once.

FIG.16is a diagram illustrating an example of an operation of sequentially reading four continuous ECC frames0to3in the fourth embodiment. After reading up to the end of the ECC frame0, the memory system10starts reading from the header H1adjacent to the overlapping area of the ECC frame1. After reading up to the end of the ECC frame1, the memory system10starts reading from the header H2adjacent to the overlapping area of the ECC frame2. After reading up to the end of the ECC frame2, the memory system10starts reading from the header H3adjacent to the overlapping area of the ECC frame3.

As such, in each of the ECC frames, the overlapping area positioned in the head portion is read only once without being read twice, and the amount of data transmission can be reduced by three times the size of the overlapping area.

Two or more embodiments among the first embodiment to the fourth embodiment may be combined.