Transistors with dual gate conductors, and associated methods

A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.

BACKGROUND

Metal-oxide-semiconductor field effect transistors, often referred to as MOSFETS, are widely used in electronic devices, such as for switching or amplification. MOSFETS are capable of achieving fast switching speeds, which makes them well suited for use in high-frequency applications. Additionally, MOSFETS are relatively simple to control because they are voltage-controlled, instead of current-controlled, devices.

Lateral double-diffused metal-oxide-semiconductor field effect transistors, often referred to as LDMOS transistors, are a class of MOSFETS where drain-to-source voltage is blocked within the transistors' semiconductor material primarily in a lateral direction. LDMOS transistors are often combined with other circuitry in integrated circuits, especially in power applications or radio-frequency applications.

FIG. 1is a cross-sectional view of a conventional n-channel LDMOS transistor100including a silicon semiconductor structure102, a source electrode104, a gate structure106, and a drain electrode108. Source electrode104is stacked on a top surface110of silicon semiconductor structure102in a source region112of LDMOS transistor100, and drain electrode108is stacked on top surface110in a drain region114of LDMOS transistor100. Gate structure106includes a gate electrode116, a polysilicon layer117, and a silicon dioxide layer118stacked in a gate region120of LDMOS transistor100. Silicon semiconductor structure102includes a p-type substrate122, an n-well124, a p-body126, a source p+ region128, a source n+ region130, and a drain n+ region132. N-well124is formed on p-type substrate122, and p-body126is formed in n-well124under source electrode104. Drain n+ region132is formed in n-well124and contacts drain electrode108. Each of source p+ region128and source n+ region130is formed in p-body126and contacts source electrode104. Each of source n+ region130and drain n+ region132is more heavily doped than n-well124, and source p+ region128is more heavily doped than p-body126.

When positive voltage VDSis applied across drain electrode108and source electrode104, a p-n junction at the interface of n-well124and p-body126is reversed biased. Consequentially, essentially no current flows from drain electrode108to source electrode104by default. The relative dopant concentration of drain n+ region132and n-well124causes a portion of n-well124referred to as a drift region134to carry the majority of voltage VDS, thereby enabling LDMOS transistor100to support a relatively large value of VDSwithout breakdown.

A positive voltage VGSapplied between gate electrode116and source electrode104creates negative charges in silicon semiconductor structure102under silicon dioxide layer118, causing a minority-carrier channel to form in a region136of p-body126. This channel has excess electrons and will therefore conduct current. Consequentially, current will flow in the lateral138direction through silicon semiconductor structure102from drain n+ region132to source n+ region130when VGSexceeds a threshold value and VDSis a positive value.

DETAILED DESCRIPTION OF THE EMBODIMENTS

A recent innovation in the field of LDMOS transistors is the development of vertical gate transistors with a dielectric layer including a plurality of dielectric sections, to promote high transistor performance and small transistor pitch. For example,FIG. 2is a cross-sectional view of a LDMOS transistor200including a vertical gate with three dielectric sections. LDMOS transistor200includes a silicon semiconductor structure202, a vertical gate204, a source electrode206, a drain electrode208, and a gate electrode210. Silicon semiconductor structure202includes a base layer212, an n-type layer214, a p-body region216, a source p+ region218, a source n+ region220, and a drain n+ region222.

Vertical gate204includes a gate conductor224and a gate dielectric layer226each disposed in a trench228of silicon semiconductor structure202. Gate conductor224extends from an outer surface232into silicon semiconductor structure202in a thickness direction230, and gate dielectric layer226includes a first dielectric section234, a second dielectric section236, and a third dielectric section238.

Each dielectric section234,236, and238separates gate conductor224from silicon semiconductor structure202by a respective separation distance. In particular, first dielectric section234separates gate conductor224from a drain portion240of n-type layer214in lateral direction242by a first separation distance t1. Additionally, second dielectric section236separates gate conductor224from a well portion244of n-type layer214in thickness direction230by a second separation distance t2, and second dielectric section236also separates gate conductor224from a source portion246of n-type layer214in lateral direction242by second separation distance t2. Third dielectric section238separates gate conductor224from p-body region216by a third separation distance t3.

Each of first separation distance t1, second separation distance t2, and third separation distance t3is different from each other of first separation distance t1, second separation distance t2, and third separation distance t3. Such differences in separation distances may advantageously enable achieving both high breakdown voltage and low on-resistance of LDMOS transistor200. In particular, values of each of first, second, and third separation distances t1, t2, and t3affect different respective characteristics of LDMOS transistor200. For example, gate-to-drain breakdown voltage of LDMOS transistor200increases with increasing value of first separation distance t1, while value of second separation distance t2affects electric field distribution, gate-to-drain capacitance, and accumulation resistance in n-type layer214. Value of third separation distance t3, in turn, affects threshold voltage and gate-to-source breakdown voltage of LDMOS transistor200. Specifically, threshold voltage decreases with decreasing value of third separation distance t3, while gate-to-source breakdown voltage of LDMOS transistor200increases with increasing value of third separation distance t3.

Forming gate dielectric layer226of first, second, and third dielectric sections234,236, and238enables each of respective first, second, and third separation distances t1, t2, and t3to be independently selected, thereby helping LDMOS transistor200achieve both high breakdown voltage and low on-resistance. For example, first separation distance t1may be selected to achieve a high gate-to-drain breakdown voltage, while second separation distance t2may be independently selected to achieve a desired balance between accumulation conductance and uniform electric field distribution, to promote low on-resistance while achieving high breakdown voltage. If gate dielectric layer226were instead formed of a single dielectric layer having uniform thickness, the dielectric layer thickness would need to be chosen to achieve a sufficiently high gate-to-drain breakdown voltage, thereby resulting in a less than optimum thickness of the dielectric layer adjacent to well portion244and source portion246of n-type layer214, which would increase on-resistance. As another example, the ability of first, second, and third separation distances t1, t2, and t3to be independently selected enables t1and t2to be selected without being constrained by a value of t3required to achieve desired gate control, thereby further enabling t1and t2to be selected to achieve high breakdown voltage and low on-resistance, respectively. As yet another example, the ability to independently select first and second separation distances t1and t2enables doping profile of n-type layer214to be different in drain portion240of n-type layer214than in source portion246of n-type layer214and in well portion244of n-type layer214, further enabling LDMOS transistor200to achieve high breakdown voltage and low on-resistance. Third separation distance t3is, for example, less than each of first separation distance t1and second separation distance t2.

While LDMOS transistor200has significant advantageous features, LDMOS transistor200may be difficult to manufacture. For example, it may be difficult to form third dielectric section238without damaging first and second dielectric sections234and236. As another example, it may be difficult to achieve a desired profile of trench228with gate dielectric layer226having a varying thickness.

Applicant has developed new LDMOS transistors and methods for forming the new transistors which at least partially overcome one or more of the drawbacks discussed above. These new LDMOS transistors include a plurality of gate conductors, which facilitate transistor production, promote flexibility in transistor configuration, and/or promote small transistor pitch. Additionally, certain embodiments of the transistor formation methods use one or more of the plurality of gate conductors to protect a drain portion and a well portion of a gate dielectric layer, while forming a source portion of the gate dielectric layer. Additionally, certain embodiments of the transistor formation methods are compatible with complementary metal oxide semiconductor (CMOS) processes and can be leveraged to form trench capacitors.

FIGS. 3 and 4illustrate one embodiment of the new LDMOS transistors developed by Applicant. In particular,FIG. 3is a top plan view of a LDMOS transistor300including a vertical gate with two gate conductors, andFIG. 4is a cross-sectional view of LDMOS transistor300taken along line4A-4A ofFIG. 3. LDMOS transistor300includes a silicon semiconductor structure302, a vertical gate304, a source electrode306, a drain electrode308, and a first gate electrode310.

Silicon semiconductor structure302includes a base layer312, an n-type layer314, a p-body region316, a source p+ region318, a source n+ region320, and a drain n+ region322. Base layer312is, for example, an n-type high-voltage well in a silicon substrate, a p-type silicon substrate, a p-type reduced surface field effect (RESURF) layer, or an n-type epitaxial layer grown over a p-type silicon substrate. N-type layer314is disposed over base layer312in a thickness direction324, and p-body region316is disposed in n-type layer314adjacent to an outer surface326of silicon semiconductor structure302. Source p+ region318and source n+ region320are each disposed in p-body region316, and drain n+ region322is disposed in n-type layer314adjacent to outer surface326. Source p+ region318has a greater p-type dopant concentration than p-body region316, and each of source n+ region320and drain n+ region322has a greater n-type dopant concentration than n-type layer314.

Silicon semiconductor structure302can include additional impurity regions without departing from the scope hereof. Additionally, the locations of source p+ region318and source n+ region320within p-body region316can be varied. For example, in an alternate embodiment (not illustrated), source p+ region318is disposed behind source n+ region320within p-body region316. Furthermore, source p+ region318could be omitted without departing from the scope hereof.

One or more regions of silicon semiconductor structure302optionally has a graded dopant concentration. For example, in some embodiments, n-type layer314has a graded n-type dopant concentration where n-type dopant concentration is greatest near drain n+ region322, and p-body region316has a graded p-type dopant concentration where p-type dopant concentration is greatest near source n+ region320. In certain embodiments, n-type layer314is configured to have n-type dopant gradient concentrations which help maximize accumulation conductance while maintaining desired breakdown voltage of LDMOS transistor300. Additionally, although the impurity regions of silicon semiconductor structure302are delineated by straight lines inFIGS. 3 and 4for illustrative simplicity, the actual shape of impurity regions of silicon semiconductor structure302may vary from that illustrated without departing from the scope hereof. For example, p-body region316may have a rounded or irregular bottom surface instead of the straight-line bottom surface illustrated inFIG. 4.

Vertical gate304includes a first gate conductor328, a second gate conductor330, a first separation dielectric layer332, and a gate dielectric layer334, each disposed in a trench336of silicon semiconductor structure302. Depth of trench336is selected, in part, according to required breakdown voltage of LDMOS transistor300. Breakdown voltage magnitude increases with increasing depth of trench336in thickness direction324. Each of first gate conductor328and second gate conductor330extends from outer surface326into silicon semiconductor structure302in thickness direction324. First separation dielectric layer332separates first gate conductor328from second gate conductor330within trench336in each of thickness direction324and a lateral direction338, where lateral direction338is orthogonal to thickness direction324. First gate conductor328is adjacent to a drain region340of LDMOS transistor300in lateral direction338, and first gate conductor328is also adjacent to a well region344of LDMOS transistor300in thickness direction324. Second gate conductor330is adjacent to a source region342of LDMOS transistor300in lateral direction338. Well region344is below vertical gate304in thickness direction324. Source region342and drain region340are each disposed on opposite sides of vertical gate304in lateral direction338.

Gate dielectric layer334includes a first dielectric section346, a second dielectric section348, and a third dielectric section350. Gate dielectric layer334separates each of first gate conductor328and second gate conductor330from silicon semiconductor structure302. Each of first gate conductor328and second gate conductor330is disposed between source n+ region320and drain n+ region322in lateral direction338. The fact that LDMOS transistor300has a vertical gate instead of a horizontal gate minimizes length of LDMOS transistor300in lateral direction338, thereby promoting small transistor size and high transformer performance. First dielectric section346separates first gate conductor328from drain region340of LDMOS transistor300in lateral direction338by a first separation distance t1. Second dielectric section348separates first gate conductor328from well region344of LDMOS transistor300in thickness direction324by a second separation distance t2, and second dielectric section348also separates first gate conductor328from source region342of LDMOS transistor300in lateral direction338by second separation distance t2. Third dielectric section350separates second gate conductor330from source region342by a third separation distance t3in lateral direction338, and third dielectric section350is adjacent to at least p-body region316and source n+ region320in lateral direction338. Gate dielectric layer334could be modified to have additional dielectric sections, such as to enable further optimization of LDMOS transistor300. For example, in one alternate embodiment, second dielectric section348is split into two dielectric sections, such that first gate conductor328is separated from source region342of LDMOS transistor300in lateral direction338by a separation distance different from second separation distance t2. Additionally, gate dielectric layer334could be modified to have fewer dielectric sections, such as to reduce complexity of manufacturing LDMOS transistor300, without departing from the scope hereof.

The values of each of first, second, and third separation distances t1, t2, and t3affect different respective characteristics of LDMOS transistor300in a manner similar to that discussed above with respect toFIG. 2. In certain embodiments, each of first separation distance t1, second separation distance t2, and third separation distance t3are different from each other, and separation distances t1, t2, and t3are selected, for example, as discussed above with respect toFIG. 2, to achieve both high breakdown voltage and low on-resistance of LDMOS transistor300. In a particular embodiment, third separation distance t3is less than each of first separation distance t1and second separation distance t2.

In certain embodiments, each of first gate conductor328and second gate conductor330are formed of a polysilicon material. First separation dielectric layer332, first dielectric section346, second dielectric section348, and third dielectric section350are formed, for example, of silicon dioxide or a high-K dielectric material such as one or more of HfO2, TiO2, ZrO2, and HfAlOx. In some embodiments, first separation dielectric layer332, first dielectric section346, second dielectric section348, and third dielectric section350are formed of a common dielectric material, while in some other embodiments, at least two of first separation dielectric layer332, first dielectric section346, second dielectric section348, and third dielectric section350are formed of different dielectric materials.

Source electrode306is disposed on outer surface326and is electrically coupled to each of source p+ region318and source n+ region320. Drain electrode308is disposed on outer surface326and is electrically coupled to drain n+ region322, and first gate electrode310is disposed on outer surface326and is electrically coupled to each of first gate conductor328and second gate conductor330. In some embodiments, a respective silicide layer (not shown) and/or other conductive layer is disposed between silicon semiconductor structure302and each of source electrode306, drain electrode308, and first gate electrode310. In some alternate embodiments, source electrode306is replaced with two separate electrodes electrically coupled to source p+ region318and source n+ region320, respectively.

When positive voltage VDSis applied between drain electrode308and source electrode306, a p-n junction formed at the interface of n-type layer314and p-body region316is reversed biased, so that very little current flows between drain electrode308and source electrode306by default. However, a positive voltage VGSapplied between first gate electrode310and source electrode306creates negative charges in semiconductor structure302adjacent to third dielectric section350in lateral direction338, causing a minority-carrier channel to form in a portion of p-body region316approximately indicated by dashed-line354. This channel has excess electrons and therefore conducts electric current through p-body region316from n-type layer314to source n+ region320. Consequentially, current will flow from drain n+ region322to source n+ region320when VGSexceeds a threshold value and VDSis a positive value. The threshold value is established, in part, by the dopant concentration in p-body region316and by the value of third separation distance t3. For example, threshold voltage can be reduced by decreasing p-type dopant concentration in p-body region316adjacent to third dielectric section350and/or by decreasing the value of third separation distance t3. Source p+ region318forms an ohmic contact between p-body region316and source electrode306to help prevent a parasitic bipolar junction transistor (not shown) in silicon semiconductor substrate302from activating.

First gate conductor328, for example, helps protect a drain portion (first dielectric section346) and a well portion (second dielectric section348) of gate dielectric layer334when forming a source portion (third dielectric layer350) of the gate dielectric layer334. Additionally, although first gate conductor328and second gate conductor330are electrically coupled to a common electrode, i.e., first gate electrode310in LDMOS transistor300, first gater conductor328and second gate conductor330could alternately be electrically coupled to different respective electrodes to allow additional flexibility in configuring LDMOS transistor300. For example,FIG. 5is a cross-sectional view of an LDMOS transistor500which is similar to LDMOS transistor300but with first gate conductor328and second gate conductor330electrically coupled to different respective electrodes. In particular, first gate conductor328is electrically coupled to a first gate electrode510, and second gate conductor330is electrically coupled to a second gate electrode556. In certain applications of LDMOS transistor500, LDMOS transistor500is switched via second gate electrode556by driving second gate electrode556between at least two different voltages, and first gate electrode510is connected to a steady-state voltage source, e.g., to ground or a non-zero power supply rail, to decouple gate capacitance from switching of LDMOS transistor500.

The new LDMOS transistors developed by Applicant are not limited to including two gate conductors but instead could include one or more additional gate conductors. For example,FIG. 6is a top plan view of a LDMOS transistor600including a vertical gate with three gate conductors, andFIG. 7is a cross-sectional view of LDMOS transistor600taken along line7A-7A ofFIG. 6. LDMOS transistor600is similar to LDMOS transistor300ofFIGS. 3 and 4, but with vertical gate304replaced with a vertical gate604. Vertical gate604includes a first gate conductor628, a second gate conductor630, a third gate conductor658, a first separation dielectric layer632, a second separation dielectric660layer, and a gate dielectric layer634each disposed in trench336. Gate dielectric layer634includes a first dielectric section646, a second dielectric section648, and a third dielectric section650which are analogous to first dielectric section346, second dielectric section348, and third dielectric section350, respectively. Gate dielectric layer634separates each of first gate conductor628, second gate conductor630, and third gate conductor658from silicon semiconductor structure302.

Third gate conductor658is disposed in a bottom of trench336such that third gate conductor is adjacent to well region344of LDMOS transistor600in thickness direction324. Second gate conductor628is disposed over third gate conductor658in thickness direction324, and second separation dielectric layer660separates first gate conductor628from third gate conductor658in vertical gate604in thickness direction324. Each of first gate conductor628and second gate conductor630extends from outer surface326into silicon semiconductor structure302in thickness direction324. First separation dielectric layer632separates first gate conductor628from second gate conductor630within trench336in each of thickness direction324and lateral direction338. First gate conductor628is adjacent to drain region340of LDMOS transistor300in lateral direction338, and second gate conductor630is adjacent to source region342of LDMOS transistor300in lateral direction338. LDMOS transistor600optionally further includes a third gate electrode (not shown) electrically coupled to third gate conductor658.

The new LDMOS transistors disclosed herein could further include a p-type RESURF layer below the vertical gate in the thickness direction. For example,FIG. 8is a cross-sectional view of a LDMOS transistor800which is similar to LDMOS transistor300ofFIGS. 3 and 4but with base layer312embodied by a base layer812including a p-type RESURF layer862disposed on an n-type base864in thickness direction324. In LDMOS transistor800, p-type RESURF layer862is adjacent to n-type layer314, and p-type RESURF layer862and n-type layer314collectively create an additional depletion region to promote uniform electric field distribution in n-type layer314. As another example,FIG. 9is a cross-sectional view of a LDMOS transistor900, which is similar to LDMOS transistor300ofFIGS. 3 and 4but further including a p-type RESURF layer962disposed in n-type layer314below vertical gate304. P-type RESURF layer962and n-type layer314collectively create an additional depletion region to promote uniform electric field distribution in n-type layer314.

One possible application of the LDMOS transistors disclosed herein is in an integrated circuit, such as an integrated circuit including one or more instances of the present LDMOS transistors along with one or more other type of transistors. For example,FIG. 10is a cross-sectional view of a portion of an integrated circuit1000including an instance of LDMOS transistor300and a complementary metal oxide semiconductor (CMOS) transistor1002sharing silicon semiconductor structure302and partially separated in a lateral direction1004by a shallow isolation trench1006. Shallow isolation trench1006is filled with a dielectric material1008. CMOS transistor1002is, for example, part of driver circuit (not shown) which controls switching of LDMOS transistor300. CMOS transistor1002is optionally electrically coupled to LDMOS transistor300via one or more electrical conductors1010of integrated circuit1000, as symbolically illustrated inFIG. 10. CMOS transistor1002includes a CMOS p-body-region1012, a CMOS source n+ region1014, a CMOS drain n+ region1016, and a CMOS gate structure1018. CMOS p-body region1012is disposed in silicon semiconductor structure302, and each of CMOS source n+ region1014and CMOS drain n+ region1016is disposed in CMOS p-body region1012adjacent to outer surface326. CMOS gate structure1018is disposed on outer surface326between CMOS source n+ region1014and CMOS drain n+ region1016in lateral direction1004.

One possible application of the LDMOS transistors disclosed herein is in a switching power converter. For example,FIG. 11schematically illustrates a buck converter1100including two instances of LDMOS transistor300, hereinafter referred to as LDMOS transistor300(1) and LDMOS transistor300(2). LDMOS transistors300(1) and300(2) are schematically illustrated inFIG. 11to promote illustrative clarity. Buck converter1100further includes an input port1102electrically coupled to an input power source (not shown), an input capacitor1104, an inductor1106, an output capacitor1108, an output port1110electrically coupled to a load (not shown), first driver circuitry1112, second driver circuitry1116, and a controller1120.

Input port1102is electrically coupled across a positive input node1122and a reference node1124. Input capacitor1104is electrically coupled across positive input node1122and reference node1124, and input capacitor1104provides a path for input ripple current drawn by buck converter1100. Drain electrode308of LDMOS transistor300(1) is electrically coupled to positive input node1122, and source electrode306of LDMOS transistor300(1) is electrically coupled to a switching node Vx. Gate electrode310of LDMOS transistor300(1) is electrically coupled to first driver circuitry1112. Drain electrode308of LDMOS transistor300(2) is electrically coupled to switching node Vx, and source electrode306of LDMOS transistor300(2) is electrically coupled to reference node1124. Gate electrode310of LDMOS transistor300(2) is electrically coupled to second driver circuitry1116. LDMOS transistors300(1) and300(2), first driver circuitry1112, and second driver circuitry1116collectively form a switching circuit1128. Inductor1106is electrically coupled between switching node Vxand a positive output node1130, and output port1110is electrically coupled across positive output node1130and reference node1124. Output capacitor1108is electrically coupled across positive output node1130and reference node1124, and output capacitor1108provides a path for output ripple current generated by buck converter1100.

Controller1120controls switching of switching circuit1128to transfer power from the power source (electrically coupled to input port1102) to the load (electrically coupled to output port1110). In particular, controller1120controls first driver circuitry1112to repeatedly switch gate electrode310of LDMOS transistor300(1) between two different voltage magnitudes, to repeatedly create and destroy a minority-carrier channel in p-body region316of LDMOS transistor300(1). Consequentially, LDMOS transistor300(1) repeatedly switches between its conductive and non-conductive states under the control of controller1120. Controller1120also controls second driver circuitry1116to repeatedly switch gate electrode310of LDMOS transistor300(2) between two different voltage magnitudes to cause LDMOS transistor300(2) to repeatedly switch between its conductive and non-conductive states. Controller1120controls switching of LDMOS transistor300(2) such that it provides a freewheeling function, or in other words, so that LDMOS transistor300(2) provides a path for current flowing through inductor1106when LDMOS transistor300(1) is in its non-conductive state. In some embodiments, controller1120controls switching of switching circuit1128to regulate one or more parameters of buck converter1100, such as input voltage Vin, input current Iin, input power Pin, output voltage Vout, output current Iout, and output power Pout. Connections between controller1120and other components of buck converter1100are not shown to promote illustrative clarity.

One or more of LDMOS transistors300(1) and300(2) could be replaced with an instance of LDMOS transistor500, LDMOS transistor600, LDMOS transistor800, or LDMOS transistor900. Additionally, it should be appreciated that the LDMOS transistors disclosed herein are not limited to use in a buck converter, or even to use in a switching power converter. For example, the LDMOS transistors disclosed herein could alternately be used in an amplifier.

Discussed below are several methods for manufacturing vertical gates of LDMOS transistors, where the vertical gates include a plurality of gate conductors. The methods may be used, for example, to form the vertical gates of LDMOS transistors300,500,600,800, and900. It should be appreciated, however, that the vertical gates of LDMOS transistors300,500,600,800, and900could be manufactured by methods other than those discussed below. Additionally, the manufacturing methods discussed below could be used to manufacture vertical gates of LDMOS transistors other than LDMOS transistors300,500,600,800, and900.

FIG. 12illustrates a method1200for forming a vertical gate of a LDMOS transistor including two gate conductors, andFIG. 13A-13Killustrates in cross-sectional views one example of using method1200to form a vertical gate similar to vertical gate304of LDMOS transistor300.FIGS. 12 and 13are best viewed together. In step1202, a trench dielectric layer is formed in a trench of a silicon semiconductor structure. In one example of step1202illustrated inFIG. 13A, a trench dielectric layer1302is formed in trench336of silicon semiconductor structure302. Trench dielectric layer1302is formed, for example, of silicon dioxide or a high-K dielectric material such as one or more of HfO2, TiO2, ZrO2, and HfAlOx. In step1204, the trench is filled with a first conductive material. In one example of step1204illustrated inFIG. 13B, trench336is filled with a first conductive material1304. First conductive material1304is, for example, polysilicon, and in one embodiment, step1304includes planarizing first conductive material1304to form a flat top surface1306.

In step1206, a portion of the first conductive material is removed from the trench. In one example of step1206illustrated inFIGS. 13C and 13D, first conductive material1304is patterned with a masking material1308, e.g., with photoresist, and a portion of first conductive material1304not covered by masking material1308is removed to from first gate conductor328. Presence of first gate conductor layer328after completion of step1206advantageously helps protect portions of trench dielectric layer1302covered by first gate conductor layer328during subsequent steps of method1200.

Step1208is performed after step1206. In step1208, a portion of the trench dielectric layer is removed in a first area of the trench. In one example of step1208illustrated inFIG. 13E, a portion of trench dielectric layer1302is removed in an area1310of trench336, using remaining masking material1308as a mask, to leave first dielectric section346and second dielectric section348. The remaining masking material1308is subsequently removed. In step1210, a first separation dielectric layer is disposed on the first conductive material in the trench. In one example of step1210illustrated inFIGS. 13F and 13G, dielectric material1312is disposed in trench336, and extraneous dielectric material1312is removed from sidewall1314of trench336to form first dielectric separation layer332. In step1212, a source portion of a gate dielectric layer is formed in the first area of the trench. In one example of step1212illustrated inFIG. 13H, third dielectric section350is formed in area1306of trench336. In step1214, a portion of the trench not containing the first conductive material is filled with a second conductive material. In one example of step1214illustrated inFIG. 13I, the remaining unfilled portion of trench336is filled with a second conductive material to form second gate conductor330.

Step1216in optional. In step1216, electrical interface to the first and second conductive material is provided. In one example of step1216illustrated inFIG. 13J, a silicide layer1316or other conductive layer is disposed on each of first gate conductor328and second gate conductor330, and first gate electrode310is disposed on silicide layer1316, such that first gate electrode310is electrically coupled to each of first gate conductor328and second gate conductor330. In another example of step1216illustrated inFIG. 13K, respective silicide layers1318and1320are disposed on first gate conductor328and second gate conductor330, and first gate electrode510and second gate electrode556are respectively disposed on silicide layers1318and1320to obtain a vertical gate similar to that illustrated inFIG. 5.

Method1200is optionally performed in parallel with and/or in serial with one or more additional methods for forming other elements of an LDMOS transistor. For example, in one embodiment, method1200is performed with one or more additional methods to form a source region and a drain region of an LDMOS transistor.

FIG. 14illustrates a method1400for forming a vertical gate of a LDMOS transistor including three gate conductors, andFIG. 15A-15Eillustrates in cross-sectional views one example of using method1400to form a vertical gate similar to vertical gate604of LDMOS transistor600.FIGS. 14 and 15are best viewed together. As discussed below, third conductive material is first disposed in a trench to form a third gate conductor, and certain steps of method1200(FIG. 12) are then performed to form first and second gate conductors.

In step1402, a trench dielectric layer is formed in a trench of a silicon semiconductor structure. In one example of step1402illustrated inFIG. 15A, a trench dielectric layer1502is formed in trench336of silicon semiconductor structure302. Trench dielectric layer1502is formed, for example, of silicon dioxide or a high-K dielectric material such as one or more of HfO2, TiO2, ZrO2, and HfAlOx. In step1404, the trench is filled with a third conductive material. In one example of step1404illustrated inFIG. 15B, trench336is filled with a third conductive material1504. Third conductive material1504is, for example, polysilicon, and in one embodiment, step1404includes planarizing third conductive material1504to form a flat top surface1506.

In step1406, a portion of the third conductive material is removed from the trench to form a third gate conductor. In one example of step1406illustrated inFIG. 15C, a portion of third conductive material1504is removed from trench336to form third gate conductor658. In step1408, a second separation dielectric layer is disposed on the third conductive material. In one example of step1408illustrated inFIG. 15D, second separation dielectric layer660is disposed on third gate conductor658. In step1410, steps1204-1214of method1200are performed to form first and second gate conductors, and step1216of method1200is optionally also performed. In one example of step1410illustrated inFIG. 15E, steps1204-1216of method1200are performed to form a vertical gate similar to vertical gate604ofFIG. 6.

Certain embodiments of the above-discussed methods for forming vertical gates of LDMOS transistors may be adapted to form trench capacitors. For example,FIG. 16illustrates a method1600for forming a trench capacitor, andFIG. 17A-17Eillustrates in cross-sectional views an example of forming a trench capacitor according to method1600.FIG. 18A-18Fillustrates in cross-sectional views another example of forming a trench capacitor according to method1600.FIGS. 16-18are best viewed together.

In step1602, a capacitor dielectric layer is formed in a trench of a silicon semiconductor structure. In one example of step1602illustrated inFIG. 17A, a capacitor dielectric layer1702is formed in a trench1704of a silicon semiconductor structure1706. In another example of step1602illustrated inFIG. 18A, a capacitor dielectric layer1802is formed in a trench1804of a silicon semiconductor structure1806. Capacitor dielectric layers1702and1802are formed, for example, of silicon dioxide or a high-K dielectric material such as one or more of HfO2, TiO2, ZrO2, and HfAlOx. In step1604, the trench is filled with a first conductive material. In one example of step1604illustrated inFIG. 17B, trench1704is filled with a first conductive material1708. In another example of step1604illustrated inFIG. 18B, trench1804is filled with a first conductive material1808. First conductive materials1708and1808are, for example, polysilicon, and in one embodiment, step1604includes planarizing first conductive material1708and first conductive material1808to form flat top surfaces1710and1810, respectively.

In step1606, a portion of the first conductive material is removed from the trench to form a first capacitor conductor. In one example of step1606illustrated inFIGS. 17C and 17D, first conductive material1708is patterned with a masking material1712, e.g., with photoresist, and a portion of first conductive material1708not covered by masking material1712is removed to form first capacitor conductor1714. In another example of step1606illustrated inFIGS. 18C and 18D, first conductive material1808is patterned with a masking material1812, e.g., with photoresist, and a portion of first conductive material1808not covered by masking material1812is removed to form first capacitor conductor1814.

Step1608is optional. In step1608, a spacer dielectric layer is disposed on the first conductive material in the trench. Step1608is not performed in the example ofFIG. 17, but step1608is performed in the example ofFIG. 18. In one example of step1608illustrated inFIG. 18E, a spacer dielectric layer1816is disposed on first capacitor conductor1814. In step1810, a portion of the trench not containing the first conductive material is filled with a second conductive material to form a second capacitor conductor. In one example of step1610illustrated inFIG. 17E, a portion of trench1704not containing first capacitor conductor1714is filled with second conductive material to form a second capacitor conductor1718and yield a trench capacitor1720. In another example of step1610illustrated inFIG. 18F, a portion of trench1804not containing first capacitor conductor1814is filled with second conductive material to form a second capacitor conductor1818to yield a trench capacitor1820.

In trench capacitor1720, first capacitor conductor1714and second capacitor conductor1718each extend from an outer surface1722of silicon semiconductor structure1706in a thickness direction1724. Capacitor dielectric layer1702separates each of first capacitor conductor1714and second capacitor conductor1718from silicon semiconductor structure1706. In trench capacitor1820, first capacitor conductor1814and second capacitor conductor1818each extend from an outer surface1822of silicon semiconductor structure1806in a thickness direction1824. First capacitor conductor1814has an U-shape, and second capacitor conductor1818is disposed within first capacitor conductor1814, as seen when the trench capacitor is viewed cross-sectionally in a plane extending in a lateral direction1826and in thickness direction1824.

Electrical interface to trench capacitors1720and1820can be achieved in several possible manners. For example,FIG. 19is a top plan view of a trench capacitor1920, andFIG. 20is a cross-sectional view of trench capacitor1920taken along lines20A-20A ofFIG. 19. Trench capacitor1920is an embodiment of trench capacitor1720where electrical interface to one side of a dielectric layer is achieved using silicon semiconductor structure1706. In particular, trench capacitor1920includes first and second impurity regions1924and1926in silicon semiconductor structure1706, where first and second impurity regions1924and1926are either p-doped or n-doped. First impurity region1924and second impurity region1926are disposed on opposite sides of trench1704in a lateral direction1928. Trench capacitor1922further includes a first electrode1930, a second electrode1932, and a third electrode1934. First electrode1930is electrically coupled to first impurity region1924, second electrode1932is electrically coupled to second impurity region1926, and third electrode1934is electrically coupled to each of first capacitor conductor1714and second capacitor conductor1718. Capacitor dielectric layer1702serves as a capacitive dielectric layer in trench capacitor1920, as symbolically shown by capacitor symbols inFIG. 20.

Current flows from first and second electrodes1930and1932through silicon semiconductor structure1706to reach capacitor dielectric layer1702in trench capacitor1920, and silicon semiconductor structure1706may exhibit non-linear conductivity as a function of voltage. Consequently, the capacitance value of trench capacitor1920may vary as a function of voltage applied to trench capacitor1920. Such non-linearity in capacitance can be significantly reduced, or even essentially eliminated, by reducing or eliminating need for capacitor current to flow through semiconductor material.FIG. 21is a top plan view of a trench capacitor2120, andFIG. 22is a cross-sectional view of trench capacitor2120taken along lines22A-22A ofFIG. 21. Trench capacitor2120is an embodiment of trench capacitor1720where electrical interface to a dielectric layer is achieved without using silicon semiconductor structure1706.

Trench capacitor2120includes an additional dielectric layer2124disposed over each of first capacitor conductor1714and second capacitor conductor1718in a thickness direction2126. Additional dielectric layer2124is formed, for example, of silicon dioxide or a high-K dielectric material such as one or more of HfO2, TiO2, ZrO2, and HfAlOx. Trench capacitor2120additionally includes an electrically conductive interface layer2128disposed on additional dielectric layer2124in thickness direction2126. In some embodiments, electrically conductive interface layer2128is formed of polysilicon. Additionally, in particular embodiments, trench capacitor2120is part of an integrated circuit including both LDMOS and CMOS devices, and first capacitor conductor1714and second capacitor conductor1718are formed using method1600, and electrically conductive interface layer2128is formed using a CMOS process. Additional dielectric layer2124serves as a capacitive dielectric layer in trench capacitor2120, as symbolically shown by capacitor symbols inFIG. 22. Electrical interface to first capacitor conductor1714and second capacitor conductor1718is achieved via an electrode2130electrically coupled to electrically conductive interface layer2128and one or more additional electrodes (not shown) electrically coupled to first capacitor conductor1714and second capacitor conductor1718.

FIG. 23is a top plan view of a trench capacitor2320, andFIG. 24is a cross-sectional view of trench capacitor2320taken along lines24A-24A ofFIG. 23. Trench capacitor2320is an embodiment of trench capacitor1820where electrical interface to a dielectric layer is achieved without using silicon semiconductor structure1806. Trench capacitor2320includes electrodes2322,2324, and2326. Each of electrodes2322and2324is electrically coupled to first capacitor conductor1814, and electrode2326is electrically coupled to second capacitor conductor1818. Consequently, spacer dielectric layer1816serves as a capacitive dielectric layer in trench capacitor2320, as symbolically shown by capacitor symbols inFIG. 24.

The methods disclosed herein for forming vertical gates of LDMOS transistors and for forming trench capacitors can be used to form both LDMOS transistor gates and trench capacitors in a single integrated circuit. For example,FIG. 25schematically illustrates an integrated circuit2500include a LDMOS transistor2504, driver circuitry2560, and a trench capacitor2506, each disposed in a silicon semiconductor structure2508. LDMOS transistor2502is, for example, one of LDMOS transistor300, LDMOS transistor500, LDMOS transistor600, LDMOS transistor800, or LDMOS transistor900. Driver circuitry2504is configured to generate a gate control signal2510to drive the gate of LDMOS transistor2502, and driver circuitry2504is powered from a power rail2512. Trench capacitor2506is electrically coupled across power rail2512to provide decoupling on power rail2512. Trench capacitor2506is, for example, one of trench capacitor1720, trench capacitor1820, trench capacitor1920, trench capacitor2120, or trench capacitor2320.

Combinations of Features

Features described above may be combined in various ways without departing from the scope hereof. The following examples illustrate some possible combinations:

(A1) A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor may include a silicon semiconductor structure and a vertical gate. The vertical gate may include (1) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (2) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (3) a gate dielectric layer separating each of first the gate conductor and the second gate conductor from the silicon semiconductor structure.

(A2) In the LDMOS transistor denoted as (A1), the first separation dielectric layer may separate the first gate conductor from the second gate conductor in each of the thickness direction and a lateral direction, the lateral direction being orthogonal to the thickness direction.

(A3) In any one of the LDMOS transistors denoted as (A1) and (A2), the first gate conductor may be adjacent to a drain region of the LDMOS transistor in the lateral direction.

(A4) In any one of the LDMOS transistors denoted as (A1) through (A3), the second gate conductor may be adjacent to a source region of the LDMOS transistor in the lateral direction.

(A5) In any one of the LDMOS transistors denoted as (A1) through (A4), the silicon semiconductor structure may include (1) a base layer, (2) an n-type layer disposed over the base layer in a thickness direction, (3) a p-body region disposed in the n-type layer, (4) a source n+ region disposed in the p-body region, and (5) a drain n+ region disposed in the n-type layer. Each of the first gate conductor and the second gate conductor may be disposed between the source n+ region and the drain n+ region in the lateral direction.

(A6) The LDMOS transistor denoted as (A5) may further include (1) a source electrode electrically coupled to the source n+ region, (2) a drain electrode electrically coupled to the drain n+ region, and (3) a first gate electrode electrically coupled to the first gate conductor.

(A7) In the LDMOS transistor denoted as (A6), the first gate electrode may be additionally electrically coupled to the second gate conductor.

(A8) The LDMOS transistor denoted as (A6) may further include a second gate electrode electrically coupled to the second gate conductor.

(A9) In any one of the LDMOS transistors denoted as (A5) through (A8), the base layer may be selected from the group consisting of an n-type high-voltage well in a silicon substrate, a p-type silicon substrate, and an n-type epitaxial layer.

(A10) Any one of the LDMOS transistors denoted as (A5) through (A9) may further include a p-type reduced surface field effect (RESURF) layer disposed below the vertical gate in the thickness direction.

(A11) In any one of the LDMOS transistors denoted as (A1) through (A10), the vertical gate may further includes (1) a third gate conductor and (2) a second separation dielectric layer separating the first gate conductor from the third gate conductor within the vertical gate.

(A12) In the LDMOS transistor denoted as (A11), the second separation dielectric layer may separate the first gate conductor from the third gate conductor in the thickness direction.

(A13) In any one of the LDMOS transistors denoted as (A11) and (A12), the gate dielectric layer may further separate the third gate conductor from the silicon semiconductor structure.

(A14) In any one of the LDMOS transistors denoted as (A11) through (A13), the first gate conductor may be adjacent to a drain region of the LDMOS transistor in the lateral direction, the second gate conductor may be adjacent to a source region of the LDMOS transistor in the lateral direction, and the third gate conductor may be adjacent to a well region of the LDMOS transistor in the thickness direction.

(A15) In any one of the LDMOS transistors denoted as (A1) through (A14), the gate dielectric layer may include a least three dielectric sections, each of the at least three dielectric sections separating the gate conductor from the silicon semiconductor structure by a respective separation distance, each of the respective separation distances being different from each other of the respective separation distances.

(A16) In any one of the LDMOS transistors denoted as (A1) through (A15), the first separation dielectric layer may be formed of silicon dioxide.

(A17) In any one of the LDMOS transistors denoted as (A1) through (A15), the first separation dielectric layer may be formed of one or more high-K dielectric materials.

(A18) In the LDMOS transistor denoted as (A17), the one or more high-K dielectric materials may include at least one of HfO2, TiO2, ZrO2, and HfAlOx.

(B1) An integrated circuit may include (1) any one of the LDMOS transistors denoted as (A1) through (A18) and (2) a trench capacitor, including (i) a first capacitor conductor and a second capacitor conductor each extending from the first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in the thickness direction, and (ii) a capacitor dielectric layer separating each of the first capacitor conductor and the second capacitor conductor from the silicon semiconductor structure.

(B2) The integrated circuit denoted as (B1) may further include a spacer dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate.

(B3) In any one of the integrated circuits denoted as (B1) and (B2), the second capacitor conductor may be disposed within the first capacitor conductor, as seen when the trench capacitor is viewed cross sectionally in a plane extending in the thickness direction and in a lateral direction, the lateral direction being orthogonal to the thickness direction.

(B4) In any one of the integrated circuits denoted as (B1) through (B3), the first capacitor conductor may have an U-shape, as seen when the trench capacitor is viewed cross-sectionally in the plane extending in the thickness direction and in the lateral direction.

(B5) Any one of the integrated circuits denoted as (B1) through (B4) may further include (1) an additional dielectric layer disposed over each of the first capacitor conductor and the second capacitor conductor in the thickness direction and (2) an electrically conductive interface layer disposed on the additional dielectric layer in the thickness direction.

(B6) Any one of the integrated circuits denoted as (B1) through (B5) may further include driver circuitry configured to drive the vertical gate of the LDMOS transistor, wherein (1) the driver circuitry is powered from a first power rail and (2) the trench capacitor is electrically coupled across the first power rail.

(C1) A method for forming a vertical gate of a lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor may include the steps of (1) forming a trench dielectric layer in a trench of a silicon semiconductor structure, (2) filling the trench with a first conductive material, (3) removing a portion of the first conductive material from the trench, (4) after the step of removing the portion of the first conductive material from the trench, removing a portion of the trench dielectric layer in a first area of the trench, (5) disposing a first separation dielectric layer on the first conductive material in the trench, (6) forming a source portion of a gate dielectric layer in the first area of the trench, and (7) filling a portion of the trench not containing the first conductive material with a second conductive material.

(C2) The method denoted as (C1) may further include, before filing the trench with the first conductive material, (1) filing the trench with a third conductive material, (2) removing a portion of the third conductive material from the trench, and (3) after the step of removing the portion of the third conductive material from the trench, disposing a second separation dielectric layer on the third conductive material.

(C3) In any one of the methods denoted as (C1) and (C2), the step of removing the portion of the first conductive material from the trench may include (1) patterning the first conductive material with masking material and (2) etching a surface of the first conductive material not covered by the masking material.

(C4) In any one of the methods denoted as (C1) through (C3), the step of disposing the first separation dielectric layer on the first conductive material in the trench may include (1) disposing dielectric material in the trench and (2) removing extraneous dielectric material from a sidewall of the trench.

(C5) Any one of the methods denoted as (C1) through (C4) may further include, after the step of filling the portion of the trench not containing the first conductive material with the second conductive material, (1) disposing a silicide layer on each of the first conductive material and the second conductive material and (2) disposing a first gate electrode on the silicide layer, such that the first gate electrode is electrically coupled to each of the first conductive material and the second conductive material.

(C6) Any one of the methods denoted as (C1) through (C4) may further include, after the step of filling the portion of the trench not containing the first conductive material with the second conductive material, (1) disposing a first silicide layer and a second silicide layer on each of the first conductive material and the second conductive material, respectively and (2) disposing a first gate electrode and a second gate electrode on the first silicide layer and the second silicide layer, respectively, such that the first gate electrode is electrically coupled to the first conductive material and the second gate electrode is electrically coupled to the second conductive material.

(D1) A method for forming an integrated circuit may include (1) forming a vertical gate of a LDMOS transistor according any one of the methods denoted as (C1) through (C6) and (2) executing at least the following steps to form a trench capacitor: (i) forming a capacitor dielectric layer in a second trench of the silicon semiconductor structure, (ii) filling the second trench with a third conductive material, (iii) removing a portion of the third conductive material from the second trench, and (iv) filling a portion of the second trench not containing the third conductive material with a fourth conductive material.

(D2) The method denoted as (D1) may further include after the step of removing the portion of the third conductive material but before the step of filling the second trench with the fourth conductive material, disposing a spacer dielectric layer on the third conductive material in the second trench.

Changes may be made in the above devices, methods, and systems without departing from the scope hereof. For example, the n-channel LDMOS transistors discussed above could be modified to be p-channel LDMOS transistors. It should thus be noted that the matter contained in the above description and shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover generic and specific features described herein, as well as all statements of the scope of the present devices, methods, and systems, which, as a matter of language, might be said to fall therebetween.