Semiconductor device

According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, and third semiconductor regions, a first member, and a first insulating member. A direction from the first electrode toward the second electrode is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the second partial region toward the first partial region crosses the first direction. The third partial region is between the second partial region and the second semiconductor region in the first direction. The third semiconductor region is provided between the third partial region and the second semiconductor region. The first insulating member includes a first insulating region and a second insulating region. The first insulating region is between the third partial region and the first member. The second insulating region is between the third semiconductor region and the third electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-018037, filed on Feb. 5, 2020; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments of the invention generally relate to a semiconductor device.

BACKGROUND

For example, it is desirable to improve the characteristics of a semiconductor device such as a transistor or the like.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first member, and a first insulating member. A direction from the first electrode toward the second electrode is along a first direction. The first semiconductor region is of a first conductivity type, and includes a first partial region, a second partial region, and a third partial region. A second direction from the second partial region toward the first partial region crosses the first direction. The second semiconductor region is of the first conductivity type. The third partial region is between the second partial region and the second semiconductor region in the first direction. The third semiconductor region is provided between the third partial region and the second semiconductor region, and is of a second conductivity type. A direction from the third semiconductor region toward the third electrode is along the second direction. A direction from the first partial region toward the first member is along the first direction. A direction from the third partial region toward the first member is along the second direction. The first insulating member includes a first insulating region and a second insulating region. The first insulating region is between the third partial region and the first member in the second direction. The second insulating region is between the third semiconductor region and the third electrode in the second direction. The first member is electrically connected to the first partial region. The first member is electrically connected to the second electrode, or capable of being electrically connected to the second electrode. A resistivity of the first member is greater than a resistivity of the first partial region and less than a resistivity of the first insulating member. According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first member, and a first insulating member. A direction from the first electrode toward the second electrode is along a first direction. The first semiconductor region is of a first conductivity type, and includes a first partial region, a second partial region, and a third partial region. A second direction from the second partial region toward the first partial region crosses the first direction. The second semiconductor region is of the first conductivity type. The third partial region is between the second partial region and the second semiconductor region in the first direction. The third semiconductor region is provided between the third partial region and the second semiconductor region, and is of a second conductivity type. A direction from the third semiconductor region toward the third electrode is along the second direction. A direction from the first partial region toward the first member is along the first direction. A direction from the third partial region toward the first member is along the second direction. The first insulating member includes a first insulating region and a second insulating region. The first insulating region is between the third partial region and the first member in the second direction. The second insulating region is between the third semiconductor region and the third electrode in the second direction. The first member is electrically connected to the first partial region. The first member is electrically connected to the second electrode, or capable of being electrically connected to the second electrode. The first member includes at least one selected from the group consisting of a first material, a second material, a third material, a fourth material, a fifth material, and a sixth material. The first material includes Si, N, and O. The second material includes a Si—N bond, a N—O bond, and a N—N bond. The third material includes a Si—N bond, a N—H bond, and a N—N bond. The fourth material includes Si, C, and a first element. The first element includes at least one selected from the group consisting of B and N. The fifth material includes Si, O, and a second element. The second element includes at least one selected from the group consisting of Fe, Au, Ni, Ta, W, and Ti. The sixth material includes a third element and a fourth element. The third element includes at least one selected from the group consisting of In, Al, and Ga. The fourth element includes at least one selected from the group consisting of P, As, B, Fe, Au, Ni, Ti, Ta, W, and Ti. According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a first member, and a first insulating member. A direction from the first electrode toward the second electrode is along a first direction. The first semiconductor region is of a first conductivity type, and includes a first partial region, a second partial region, and a third partial region. A second direction from the second partial region toward the first partial region crosses the first direction. The second semiconductor region is of the second conductivity type. The third partial region is between the second partial region and the second semiconductor region in the first direction. A direction from the first partial region toward the first member is along the first direction. A direction from the third partial region toward the first member is along the second direction. The first insulating member includes a first insulating region, and is between the third partial region and the first member in the second direction. The first member is electrically connected to the first partial region. The first member is electrically connected to the second electrode, or capable of being electrically connected to the second electrode. A resistivity of the first member is greater than a resistivity of the first partial region and less than a resistivity of the first insulating member.

In the specification and drawings, components similar to those described previously in an antecedent drawing are marked with like reference numerals, and a detailed description is omitted as appropriate.

First Embodiment

FIG. 1is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment.

As shown inFIG. 1, the semiconductor device110according to the embodiment includes a first electrode51, a second electrode52, a third electrode53, a first semiconductor region11, a second semiconductor region12, a third semiconductor region13, a first member31, and a first insulating member40.

The direction from the first electrode51toward the second electrode52is along a first direction. The first direction is taken as a Z-axis direction. One direction perpendicular to the Z-axis direction is taken as an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.

The first semiconductor region11includes a first partial region11a, a second partial region11b, and a third partial region11c. A second direction from the second partial region11btoward the first partial region11acrosses the first direction (the Z-axis direction). The second direction is, for example, the X-axis direction. The first semiconductor region11is of a first conductivity type.

The second semiconductor region12is of the first conductivity type. The third partial region11cof the first semiconductor region11is between the second partial region11band the second semiconductor region12in the first direction (the Z-axis direction).

The third semiconductor region13is provided between the third partial region11cand the second semiconductor region12in the Z-axis direction. The third semiconductor region13is of a second conductivity type.

For example, the first conductivity type is an n-type, and the second conductivity type is a p-type. The first conductivity type may be the p-type, and the second conductivity type may be the n-type. Hereinbelow, the first conductivity type is taken to be the n-type, and the second conductivity type is taken to be the p-type.

The direction from the third semiconductor region13toward the third electrode53is along the second direction (e.g., the X-axis direction). For example, a direction from a portion of the second semiconductor region12toward a portion of the third electrode53may be along the X-axis direction. A direction from a portion of the third partial region11ctoward a portion of the third electrode53may be along the X-axis direction.

The direction from the first partial region11atoward the first member31is along the first direction (the Z-axis direction). The direction from the third partial region11ctoward the first member31is along the second direction (the X-axis direction).

The first insulating member40includes a first insulating region41and a second insulating region42. The first insulating region41is between the third partial region11cand the first member31in the second direction (the X-axis direction). The second insulating region42is between the third semiconductor region13and the third electrode53in the second direction.

The first electrode51is, for example, a drain electrode. The second electrode52is, for example, a source electrode. The third electrode53is, for example, a gate electrode. A current that flows between the first electrode51and the second electrode52can be controlled by controlling the potential of the third electrode53. The potential of the third electrode53is, for example, a potential that is referenced to the potential of the second electrode52. The semiconductor device110is, for example, a transistor. For example, the second insulating region42functions as a gate insulating film.

In the example, the semiconductor device110includes a fourth semiconductor region14and a fifth semiconductor region15. The fourth semiconductor region14is electrically connected to the second electrode52. The fourth semiconductor region14is of the second conductivity type (e.g., the p-type). For example, the concentration of the impurity of the second conductivity type in the fourth semiconductor region14is greater than the concentration of the impurity of the second conductivity type in the third semiconductor region13.

The fifth semiconductor region15is provided between the first electrode51and the first semiconductor region11. The fifth semiconductor region15is of the first conductivity type (e.g., the n-type). For example, the concentration of the impurity of the first conductivity type in the fifth semiconductor region15is greater than the concentration of the impurity of the first conductivity type in the first semiconductor region11.

For example, the concentration of the impurity of the first conductivity type in the second semiconductor region12is greater than the concentration of the impurity of the first conductivity type in the first semiconductor region11.

The first to fifth semiconductor regions11to15include, for example, silicon. These semiconductor regions may include a compound semiconductor. The impurity of the first conductivity type (the n-type) includes, for example, at least one selected from the group consisting of As and P when the first to fifth semiconductor regions11to15include silicon. The impurity of the second conductivity type (the p-type) includes, for example, at least one selected from the group consisting of B and Al.

The concentration of the impurity of the first conductivity type in the first semiconductor region11is, for example, not less than 1×1016/cm3and not more than 1×1017/cm3. The concentration of the impurity of the first conductivity type in the second semiconductor region12is, for example, not less than 1×1018/cm3and not more than 5×1019/cm3. The concentration of the impurity of the second conductivity type in the third semiconductor region13is, for example, not less than 5×10′6/cm3and not more than 1×1018/cm3. The concentration of the impurity of the second conductivity type in the fourth semiconductor region14is, for example, not less than 1×1018/cm3and not more than 5×1019/cm3. The concentration of the impurity of the first conductivity type in the fifth semiconductor region15is, for example, not less than 5×1018/cm3and not more than 5×1019/cm3.

The first semiconductor region11is, for example, an n−-region. The second semiconductor region12is, for example, an n+-region. The third semiconductor region13is, for example, a p−-region. The fourth semiconductor region14is, for example, a p+-region. The fifth semiconductor region15is, for example, an n+-region.

For example, the second electrode52contacts the second semiconductor region12and the fourth semiconductor region14.

In the example, at least a portion of the first member31is between the first partial region11aand at least a portion of the third electrode53in the first direction (the Z-axis direction). The first insulating member40includes a third insulating region43. The third insulating region43is between the first member31and the third electrode53in the Z-axis direction. The third insulating region43electrically insulates the first member31and the third electrode53.

In the example, the semiconductor device110further includes a second insulating member48. The second insulating member48electrically insulates between the third electrode53and the second electrode52.

The first insulating member40and the second insulating member48include, for example, silicon oxide (e.g., SiO2). The first insulating member40and the second insulating member48may include, for example, at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide.

The first member31is electrically connected to the first partial region11a. For example, the first member31contacts the first partial region11a.

The first member31is electrically connected to the second electrode52. Or, the first member31is capable of being electrically connected to the second electrode52. In the example ofFIG. 1, the semiconductor device110includes a first conductive portion61. The first conductive portion61electrically connects the first member31and the second electrode52. An interconnect61L is provided in the example ofFIG. 1. The interconnect61L passes through a position outside the cross section ofFIG. 1and electrically connects the first member31and the second electrode52. A terminal61T may be provided as shown inFIG. 1. The terminal61T is electrically connected to the first conductive portion61. The terminal61T may be electrically connected to the second electrode52by an interconnect or the like that is not included in the semiconductor device110.

For example, the resistivity of the first member31is greater than the resistivity of the first partial region11aand less than the resistivity of the first insulating member40. For example, the resistivity of the first member31is greater than the resistivity of the first semiconductor region11. The resistivity of the first member31may be greater than the resistivities of the first to third electrodes51to53. The first member31is, for example, a “high resistance film”.

According to the embodiment, for example, a micro current can flow in the first member31in the off-state. Thereby, for example, the electric field in the third partial region11c(e.g., a mesa region) can be made uniform. For example, a source-drain charge amount Qoss can be reduced. Thereby, for example, the loss can be suppressed. For example, the power consumption can be reduced. For example, the electric field that is applied to the gate insulating film can be reduced. For example, high reliability is obtained. According to the embodiment, for example, a semiconductor device can be provided in which the characteristics can be improved.

The first member31may include various materials such as the following. The first member31includes, for example, at least one selected from the group consisting of a first material, a second material, a third material, a fourth material, a fifth material, and a sixth material. The first material includes, for example, Si, N, and O.

The second material includes, for example, Si, N, and O.

The second material includes, for example, a Si—N bond, a N—O bond, and a N—N bond. The second material includes, for example, oxygen-doped SIPOS (Semi-insulating Poly-crystalline Silicon). The second material is, for example, a mixed material of SiH4, N2O, and N2.

The third material includes Si, N, and O. The third material includes, for example, a Si—N bond, a N—H bond, and a N—N bond. The third material is, for example, nitrogen-doped SIPOS. The third material is a mixed material of SiH4, NH3, and N2.

The fourth material includes, for example, Si, C, and a first element. The first element includes at least one selected from the group consisting of B and N. The fifth material includes, for example, Si, O, and a second element. The second element includes at least one selected from the group consisting of Fe, Au, Ni, Ta, W, and Ti. The sixth material includes, for example, a third element and a fourth element. The third element includes at least one selected from the group consisting of In, Al, and Ga. The fourth element includes at least one selected from the group consisting of P, As, B, Fe, Au, Ni, Ti, Ta, W, and Ti.

For example, the first member31can be provided with the appropriate resistivity by such materials. Thereby, as described above, a semiconductor device can be provided in which the characteristics can be improved.

In one example, the resistivity of the first member31is not less than 5×107Ωcm and not more than 8×1011Ωcm.

For example, the configuration of the semiconductor device110illustrated inFIG. 1may be provided at the end (a peripheral region) of the semiconductor device. Or, for example, the configuration of the semiconductor device110illustrated inFIG. 1may be provided in an inner portion of the semiconductor device.

FIG. 2is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

As shown inFIG. 2, the semiconductor device111according to the embodiment includes a first counter member31C in addition to the first electrode51, the second electrode52, the third electrode53, the first semiconductor region11, the second semiconductor region12, the third semiconductor region13, the first member31, and the first insulating member40. Other than the portions of the semiconductor device111described below, the semiconductor device111may have a configuration similar to that of the semiconductor device110.

As shown inFIG. 2, the third partial region11cis between the first counter member31C and the first member31in the second direction (the X-axis direction).

The first insulating member40further includes a first counter insulating region41C. The first counter insulating region41C is between the first counter member31C and the third partial region11cin the second direction (the X-axis direction). The first semiconductor region11further includes a first counter partial region11aC. The second partial region lib is between the first counter partial region11aC and the first partial region11ain the second direction. The direction from the first counter partial region11aC toward the first counter member31C is along the first direction (the Z-axis direction).

The first counter member31C is electrically connected to the first counter partial region11aC. For example, the first counter member31C contacts the first counter partial region11aC.

For example, the resistivity of the first counter member31C is greater than the resistivity of the first partial region11aand less than the resistivity of the first insulating member40. For example, the resistivity of the first counter member31C is greater than the resistivity of the first counter partial region11aC. For example, the first counter member31C includes at least one selected from the group consisting of the first material, the second material, the third material, the fourth material, the fifth material, and the sixth material described above.

For example, the third partial region11cis interposed between the first member31and the first counter member31C with the first insulating region41and the first counter insulating region41C interposed.

In the semiconductor device111, for example, a micro current can flow in the first member31and the first counter member31C in the off-state. Thereby, for example, the electric field in the third partial region11c(e.g., the mesa region) can be made uniform. For example, the source-drain charge amount Qoss can be reduced. For example, the loss can be suppressed thereby. For example, the power consumption can be reduced. For example, the electric field that is applied to the gate insulating film can be reduced. For example, high reliability is obtained. According to the embodiment, for example, a semiconductor device can be provided in which the characteristics can be improved.

As shown inFIG. 2, the semiconductor device111may further include a third counter electrode53C. In the example, the third counter electrode53C is provided between the first counter member31C and the second electrode52. For example, the third counter electrode53C functions as a gate electrode. In the example, a second counter insulating member48C is provided between the third counter electrode53C and the second electrode52.

Multiple structures (structures that include the first member31and the third electrode53) illustrated inFIG. 2may be provided. For example, such multiple structures are arranged along the X-axis direction.

For example, the first member31and the first counter member31C have band configurations extending in the Y-axis direction. For example, the third electrode53and the third counter electrode53C have band configurations extending in the Y-axis direction. For example, the Y-axis direction crosses a plane including the first and second directions.

As shown inFIGS. 1 and 2, the first member31includes a first end31aand a second end31b. The second end31bis between the first partial region11aand the first end31ain the first direction (the Z-axis direction). The position in the first direction (the Z-axis direction) of the first end31ais between the position in the first direction of the second end31band the position in the first direction of a boundary13B between the third partial region11cand the third semiconductor region13. For example, the first end31ais the upper end of the first member31. The boundary13B is the lower end of the third semiconductor region13. For example, the upper end of the first member31is lower than the lower end of the third semiconductor region13. The increase of the electric field at the p-n junction portion can be suppressed thereby.

As shown inFIG. 1, the length along the second direction (the X-axis direction) of the first insulating region41is taken as a length t41. The length along the second direction (the X-axis direction) of the second insulating region42is taken as a length t42. The length t42is less than the length t41. Appropriate electrical characteristics (e.g., the threshold voltage, etc.) are easily obtained by setting the length t42(the thickness) of the second insulating region42, which corresponds to the gate insulating film, to be short.

For example, it is favorable for the length t42to be not less than 10 nm and not more than 100 nm. For example, it is favorable for the length t41to be not less than 20 nm and not more than 250 nm. In one example, the length t42is not less than 45 nm but less than 55 nm, and the length t41is not less than 90 nm and not more than 110 nm.

Examples of characteristics of the semiconductor device111of will now be described. In the following examples, the first counter member31C has a configuration and characteristics that are similar to those of the first member31, and the third counter electrode53C has a configuration and characteristics that are similar to those of the third electrode53.

FIGS. 3 and 4are graphs illustrating characteristics of the semiconductor device.

FIG. 3shows an example of simulation results of the relationship between the blocking voltage and the resistivity of the first member31. The horizontal axis ofFIG. 3is a resistivity R1of the first member31. The vertical axis ofFIG. 3is a blocking voltage BV. As shown inFIG. 3, a high blocking voltage BV is obtained when the resistivity R1of the first member31is 5×107Ωcm or more.

FIG. 4shows an example of simulation results of the relationship between the drain current and the resistivity of the first member31. The horizontal axis ofFIG. 4is the resistivity R1of the first member31. The vertical axis ofFIG. 4is a drain current Id.FIG. 4shows a current component I1flowing through the first member31, and a current component I2flowing through the third partial region11c. As shown inFIG. 4, the current component I1increases as the resistivity R1decreases. For example, the current component I1is greater than the current component I2when the resistivity R1is 8×1012Ωcm or less.

In the embodiment, it is favorable for the resistivity of the first member31to be, for example, not less than 5×107Ωcm and not more than 8×1011Ωcm. Thereby, for example, a high blocking voltage BV is obtained. The current component I1can be effectively increased thereby; for example, the electric field in the third partial region11ccan be effectively made uniform. For example, the source-drain charge amount Qoss can be effectively reduced.

FIG. 5is a graph illustrating a characteristic of the semiconductor device.

FIG. 5shows an example of simulation results of the relationship between the blocking voltage and the thickness (the length t41) of the first member31. The horizontal axis ofFIG. 5is the thickness (the length t41) of the first member31. The vertical axis ofFIG. 5is the blocking voltage BV. As shown inFIG. 5, the blocking voltage BV increases as the thickness (the length t41) of the first member31decreases. For example, a particularly high blocking voltage BV is obtained when the length t41is not less than 20 nm and not more than 250 nm. In the embodiment, it is favorable for the length t41to be not less than 20 nm and not more than 250 nm. A high blocking voltage BV is easily obtained thereby. The length t41may be not less than 20 nm and not more than 200 nm.

FIG. 6is a graph illustrating characteristics of semiconductor devices.

FIG. 6illustrates simulation results of the depth-direction distribution of the electric field in the third partial region11c.FIG. 6illustrates a characteristic of the semiconductor device111including the first member31, and a characteristic of a semiconductor device119of a reference example. In the semiconductor device119, the resistivity of the first member31is 1×1010Ωcm, and an insulating film is provided between the first member31and the first partial region11a. The horizontal axis ofFIG. 6is a position pZ in the Z-axis direction (the depth direction). The vertical axis is an electric field EF. InFIG. 6, the region where the position pZ is about 1 μm to about 5 μm corresponds to the depth at which the first member31is provided.

As shown inFIG. 6, peaks of the electric field EF occur at the positions of the upper and lower ends of the first member31for the semiconductor device119of the reference example. Conversely, for the semiconductor device111, the electric field EF is substantially uniform. Thus, in the embodiment, the electric field EF is easily made uniform.

FIG. 7is a graph illustrating characteristics of the semiconductor devices.

FIG. 7shows an example of simulation results of the relationship between the blocking voltage and the concentration of the impurity of the first conductivity type (the n-type) in the first semiconductor region11. The horizontal axis ofFIG. 7is a concentration C1of the impurity. The vertical axis is the blocking voltage BV.FIG. 7illustrates the characteristics of the semiconductor device111and the semiconductor device119.

As shown inFIG. 7, the blocking voltage BV abruptly decreases as the concentration C1of the impurity increases for the semiconductor device119. For the semiconductor device111, a high blocking voltage BV can be maintained even when the concentration C1is high. This is caused by the uniformity of the electric field EF being high in the embodiment.

In the embodiment, for example, the concentration C1of the impurity can be higher when obtaining the same blocking voltage as the reference example. For the same concentration C1, the blocking voltage BV that is obtained in the embodiment can be greater than that of the reference example.

FIGS. 8 to 10are graphs illustrating characteristics of the semiconductor devices.

These figures show examples of simulation results of characteristics when changing the concentration C1of the impurity in the first semiconductor region11. InFIGS. 8 to 10, the horizontal axis is the blocking voltage BV. The vertical axis ofFIG. 8is an on-resistance RonA when the gate voltage is 10 V. The vertical axis ofFIG. 9is the source-drain charge amount Qoss discharged for a drain voltage in the range of 0 V to 50 V. The vertical axis ofFIG. 10is the product of the on-resistance RonA and the charge amount Qoss. These figures show the characteristics of the semiconductor device111and the characteristics of the semiconductor device119of the reference example.

As shown inFIG. 8, compared to the semiconductor device119, at least one of a high blocking voltage BV or a low on-resistance RonA is obtained for the semiconductor device111. As shown inFIG. 9, compared to the semiconductor device119, at least one of a high blocking voltage BV or a small charge amount Qoss is obtained for the semiconductor device111. As shown inFIG. 10, compared to the semiconductor device119, at least one of a high blocking voltage BV or a small product of the on-resistance RonA and the charge amount Qoss is obtained for the semiconductor device111.

For example, a blocking voltage BV of 104 V will now be focused upon. When referenced to the reference example, the on-resistance RonA can be reduced 23% in the semiconductor device111. For example, this is because the concentration C1of the impurity in the first semiconductor region11can be high because a uniform electric field EF is obtained in the semiconductor device111. For example, focusing on the blocking voltage BV of 104 V, when referenced to the reference example, the charge amount Qoss can be reduced 74% in the semiconductor device111. For example, focusing on the blocking voltage BV of 104 V, when referenced to the reference example, the product of the on-resistance RonA and the charge amount Qoss can be reduced 80% in the semiconductor device111.

Thus, according to the embodiment, the trade-off between the blocking voltage BV and the on-resistance RonA can be improved. According to the embodiment, the trade-off between the blocking voltage BV and the charge amount Qoss can be improved. According to the embodiment, the trade-off between the blocking voltage BV and the product of the on-resistance RonA and the charge amount Qoss can be improved.

Several examples of semiconductor devices according to the embodiment will now be described. In the following description, portions that are similar to the semiconductor device110or the semiconductor device111are omitted as appropriate.

FIGS. 11 to 15are schematic cross-sectional views illustrating semiconductor devices according to the first embodiment.

In a semiconductor device112according to the embodiment as shown inFIG. 11, the first conductive portion61includes a first conductive region61aand a second conductive region61b. For example, the first conductive region61acontacts the first end31a. The second conductive region61bextends in the Z-axis direction. The second conductive region61bcontacts the first conductive region61aand the second electrode52. The first member31and the second electrode52may be electrically connected by such a first conductive portion61.

As in a semiconductor device113according to the embodiment shown inFIG. 12, the first conductive portion61may extend along the Z-axis direction. For example, the first conductive portion61contacts the first member31and the second electrode52. As shown inFIG. 12, the first counter member31C may be electrically connected to the second electrode52by a first counter conductive portion61C.

As shown inFIG. 13, a semiconductor device114according to the embodiment includes a sixth semiconductor region16. The sixth semiconductor region16is provided between the first partial region11aand the first member31. The sixth semiconductor region16is of the first conductivity type. The sixth semiconductor region16is electrically connected to the first partial region11aand the first member31. The concentration of the impurity of the first conductivity type in the sixth semiconductor region16is greater than the concentration of the impurity of the first conductivity type in the first semiconductor region11. The sixth semiconductor region16is, for example, an n+-region. By providing the sixth semiconductor region16, the first partial region11aand the first member31are electrically connected stably with a low contact resistance.

In a semiconductor device115according to the embodiment as shown inFIG. 14, in the first semiconductor region11, the concentration of the impurity is higher in the first partial region11a, the second partial region11b, and the first counter partial region11aC than in the third partial region11c(e.g., the n−-region). Thus, the concentration of the impurity of the first conductivity type in the third partial region11cmay be less than the concentration of the impurity of the first conductivity type in the first partial region11a.

As shown inFIG. 15, a semiconductor device116according to the embodiment includes a seventh semiconductor region17. The seventh semiconductor region17is provided between the third partial region11cand the third semiconductor region13. The seventh semiconductor region17is of the first conductivity type. The concentration of the impurity of the first conductivity type in the seventh semiconductor region17is less than the concentration of the impurity of the first conductivity type in the third partial region11c. The seventh semiconductor region17is, for example, an n−-region. By providing the seventh semiconductor region17, for example, the blocking voltage BV can be improved when the gate voltage is negative.

In the semiconductor devices112to116as well, a semiconductor device can be provided in which the characteristics can be improved.

FIG. 16is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

In the semiconductor device120according to the embodiment as shown inFIG. 16, the first semiconductor region11further includes a fourth partial region11d. The second partial region11bis between the fourth partial region11dand the first partial region11ain the second direction (the X-axis direction). The third electrode53is between the fourth partial region lid and the second electrode52in the first direction (the Z-axis direction). The first insulating member40includes the third insulating region43. The third insulating region43is between the fourth partial region11dand the third electrode53in the first direction (the Z-axis direction).

FIG. 17is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

In the semiconductor device121according to the embodiment as shown inFIG. 17, the first counter member31C is further provided in the configuration of the semiconductor device120.

In the semiconductor devices120and121, the third electrode53is at a different position from the first member31in the X-axis direction. In the semiconductor devices120and121as well, for example, a micro current can flow in the first member31and the first counter member31C in the off-state. For example, the electric field in the third partial region11c(e.g., the mesa region) can be made uniform. For example, the source-drain charge amount Qoss can be reduced. Thereby, for example, the loss can be suppressed. For example, the power consumption can be reduced. For example, the electric field that is applied to the gate insulating film can be reduced. For example, high reliability is obtained. In the semiconductor devices120and121as well, for example, a semiconductor device can be provided in which the characteristics can be improved.

FIGS. 18 to 20are schematic cross-sectional views illustrating semiconductor devices according to the first embodiment.

As shown inFIG. 18, a semiconductor device122according to the embodiment includes a second conductive portion62. The second conductive portion62is electrically connected to the second electrode52. As in the example ofFIG. 18, for example, the second conductive portion62may be electrically connected to the second electrode52by an interconnect62L.

The second conductive portion62is between the fourth partial region lid and the third electrode53in the first direction (the Z-axis direction). The first insulating member40includes a fourth insulating region44. The fourth insulating region44is between the fourth partial region lid and the second conductive portion62in the first direction (the Z-axis direction). The third insulating region43is between the second conductive portion62and the third electrode53in the first direction. For example, the reverse transfer capacitance can be reduced by the second conductive portion62.

As in a semiconductor device123according to the embodiment shown inFIG. 19, the first conductive portion61may include the first conductive region61aand the second conductive region61b. The first counter conductive portion61C may include a first counter conductive region61aC and a second counter conductive region61bC.

As in a semiconductor device124according to the embodiment shown inFIG. 20, the second conductive portion62may be provided in the semiconductor device123. The interconnect62L (referring toFIG. 18) may be provided in the semiconductor device124.

In the semiconductor devices122to124as well, a semiconductor device can be provided in which the characteristics can be improved.

Second Embodiment

FIG. 21is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment.

As shown inFIG. 21, the semiconductor device130according to the embodiment includes the first electrode51, the second electrode52, the first semiconductor region11, the second semiconductor region12, the first member31, and the first insulating member40.

The direction from the first electrode51toward the second electrode52is along the first direction (e.g., the Z-axis direction). The first semiconductor region11includes the first partial region11a, the second partial region11b, and the third partial region11c. The first semiconductor region11is of the first conductivity type. The second direction from the second partial region11btoward the first partial region11acrosses the first direction. The second direction is, for example, the X-axis direction.

The second semiconductor region12is of the second conductivity type. The third partial region11cis between the second partial region11band the second semiconductor region12in the first direction (the Z-axis direction).

The direction from the first partial region11atoward the first member31is along the first direction (the Z-axis direction). The direction from the third partial region11ctoward the first member31is along the second direction (the X-axis direction). The first insulating member40includes the first insulating region41. The first insulating region41is between the third partial region11cand the first member31in the second direction (the X-axis direction). The first member31is electrically connected to the first partial region11a. Or, the first member31is capable of being electrically connected to the second electrode52. For example, at least one of the interconnect61L or the terminal61T described in reference toFIGS. 1 and 2may be provided. Thereby, the first member31is capable of being electrically connected to the second electrode52. The semiconductor device130is, for example, a diode.

The resistivity of the first member31is, for example, greater than the resistivity of the first partial region11aand less than the resistivity of the first insulating member40. For example, the first member31may include at least one selected from the group consisting of the first material, the second material, the third material, the fourth material, the fifth material, and the sixth material described above.

By providing such a first member31, for example, the concentration of the electric field can be suppressed. Thereby, a semiconductor device can be provided in which the characteristics can be improved.

FIG. 22is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment.

As in the semiconductor device131according to the embodiment shown inFIG. 22, the first counter member31C and the first counter conductive portion61C may be included. The first insulating member40may include the first counter insulating region41C. In the semiconductor device131as well, a semiconductor device can be provided in which the characteristics can be improved.

An example of a method for manufacturing a semiconductor device according to the embodiment will now be described. An example of a method for manufacturing the semiconductor device111will be described.

FIGS. 23A, 23B, 24A, 24B, 25A, 25B, and 26are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the embodiment.

As shown inFIG. 23A, for example, an n-type semiconductor layer that is used to form the first semiconductor region11is formed on the fifth semiconductor region15(e.g., a semiconductor substrate). The thickness of the n-type semiconductor layer is, for example, 8.75 μm. For example, the n-type semiconductor layer is formed by epitaxial growth.

As shown inFIG. 23B, a trench is formed by removing a portion of the n-type semiconductor layer after forming a silicon oxide film used as a mask; and an insulating film40F (e.g., a SiO2film) is formed from the surface portion of the n-type semiconductor layer by thermal oxidation. The insulating film40F is used to form at least a portion of the first insulating member40. The thickness of the insulating film40F is, for example, not less than 20 nm and not more than 250 nm.

As shown inFIG. 24A, the insulating film40F that is positioned on the bottom portion of the trench and the top portion of the n-type semiconductor layer is removed by dry etching; subsequently, a film31F that is used to form the first member31is formed. The film31F may be, for example, polysilicon including an impurity with a low concentration. The film31F may be, for example, an InP film including Fe. A portion of the film31F is removed by etching.

As shown inFIG. 24B, for example, a polysilicon film that includes an impurity with a high concentration is formed as the first conductive portion61.

As shown inFIG. 25A, insulating films (e.g., SiO2films) that are used to form the third insulating region43and the second insulating region42are formed, and the third electrode53is formed. Unnecessary films are removed as necessary.

As shown inFIG. 25B, the second insulating member48is formed, and the third semiconductor region13and the second semiconductor region12are formed by introducing a p-type impurity and introducing an n-type impurity.

The first electrode51and the second electrode52are formed as shown inFIG. 26. Thereby, for example, the semiconductor device111is obtained.

According to the embodiments, a semiconductor device can be provided in which the characteristics can be improved.

Moreover, all semiconductor devices practicable by an appropriate design modification by one skilled in the art based on the semiconductor devices described above as embodiments of the invention also are within the scope of the invention to the extent that the spirit of the invention is included.