METHODS AND STRUCTURES FOR LOW TEMPERATURE HYBRID BONDING

A semiconductor element is provided with a micro-structured metal layer over conductive features of a hybrid bonding surface. The micro-structured metal layer comprises fine metal grain microstructure, such as nanograins. The micro-structured metal layer can be formed over the conductive features by providing a metal oxide and reducing the metal oxide to metal. The micro-structured metal layer can be formed selectively if the metal oxide is formed by oxidation. When directly bonded to another element, the micro-structured metal layer forming strong bonds at the bonding interface can substantially reduce annealing temperature.

BACKGROUND

Field

The field relates to direct bonding of microelectronics, and more particularly to hybrid bonding.

Description of the Related Art

The microelectronics industry has experienced tremendous growth over the past decades. However, the thirst of the market for ever higher input/output (I/O) density and faster connection between chips has been unquenchable. This demand has driven integrated circuit (IC) system designs into 3D architectures. Solder bumps and micro-bumps can provide vertical interconnects between chips by using small metal bumps on dies as one form of wafer-level packaging. Hybrid bonding can provide a solution for superior density of interconnect features.

Hybrid bonding, such as the DBI® technology commercially available from Adeia of San Jose, CA, avoids the use of metal bumps, and instead connects dies in packages using direct metal-to-metal (e.g., copper-to-copper) conductive feature connections. In the bonding layer of each bonding element conductive features, such as metal contact pads, are embedded in a dielectric material. The hybrid bonding surface can be planarized by chemical mechanical polishing (CMP) and cleaned to remove particles and contaminants. Plasma activation can create active sites on the dielectric of the hybrid bonding surface of at least one of the two elements to be bonded. The two bonding elements are aligned precisely as they are brought together in a bonding equipment and the active sites on the bonding surfaces bond to each other. The dielectric bonding can be processed at room temperature. An annealing process can aid in bonding aligned conductive features, and can also strengthen bonds between the dielectric materials.

While hybrid bonding has greatly improved the ability to form high density and reliable connections between microelectronics, there remains a need to improve yield, reduce cost and/or reduce thermal budget consumption.

DETAILED DESCRIPTION

Annealing temperatures and annealing durations for forming direct conductor-to-conductor (e.g., metal-to-metal) bonding is of great importance in the fabrication of directly bonded components. Lower annealing temperatures and/or shorter annealing durations are desirable, for example, for reduced consumption of thermal budget and reduced stressed due to CTE mismatch. Various bonding layer structures and methods for producing such bonded semiconductor elements can be implemented to achieve lower annealing temperatures to sufficiently fuse contact pads or other conductive features of the bonded semiconductor elements together. One way in which annealing temperatures can be lowered includes providing a microstructure for the material of the conductive features, which can achieve bonding with lower annealing temperature. Providing conductive materials with microstructures, such as nanograins, can be expensive, however, and can also introduce greater contaminants into the conductors.

FIGS.1-5illustrate an example embodiment of a fabrication process for forming a microstructure for conductive features, such as contact pads.FIG.1shows a schematic cross-sectional view of at least a portion of a microelectronic structure100, such as a semiconductor element, microelectronic element or a dielectric element. The microelectronic structure100can comprise a base substrate102, such as a bulk semiconductor material (e.g., silicon), an interposer substrate, a semiconductor package substrate, a flat panel substrate, or a dielectric substrate. The base substrate102can comprise active circuitry and/or other devices formed at least partially therein. A base nonconductive or dielectric material layer104can be provided over the base substrate102with conductive features110embedded therein. A first nonconductive or dielectric layer106can be provided over the dielectric material layer104. Intervening vias112can be embedded in the first dielectric layer106. A second nonconductive or dielectric layer108can be provided over the first dielectric layer106and a patterned conductive material can be at least partially embedded therein to provide conductive features. In some embodiments, the conductive features can be provided by deposition and etching. In the illustrated embodiment, a stage of damascene processing is shown. Trenches are formed in the upper or second dielectric layer108, which are then filled with a conductive material114. The conductive material114may overfill the cavities, including an overburden over field regions of the second dielectric layer108. A barrier layer116may be provided between the second dielectric layer108and the conductive material114to limit diffusion of the conductive material114into the second dielectric layer108and to serve as an adhesion layer between the conductive material114and the second dielectric layer108. In some embodiments, separate adhesion and barrier layers may be provided prior to filling the damascene cavities.

In some embodiments, a seed layer may be disposed on the barrier layer116, such as by copper sputtering. In some embodiments, the conductive material114and the intervening vias112are formed together, e.g., by a dual damascene process, in which case the barrier layer116can be omitted between the conductive material114and the intervening vias112.

InFIG.1each of the first dielectric layer106and the second dielectric layer108can comprise an inorganic dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc. In some embodiments, one or both of the first dielectric layer106and the second dielectric layer108can be a low-k dielectric material, e.g., porous silicon oxide, organosilicate glass (SiCOH), or amorphous carbon. In still other embodiments, the dielectric layers may comprise polymeric materials. Each or any of the conductive features, including the intervening vias112, the conductive material114, and the underlying conductive feature110can comprise a metal, such as copper, nickel, chromium, gold, indium, tin, platinum, silver, ruthenium, molybdenum, palladium, cobalt, zinc, tungsten, tantalum, titanium, aluminum, a metal silicide, and alloys thereof, or a non-metal conductive material, e.g., doped silicon.

Referring toFIG.2, the element100may go through an annealing process if desired to optimize grain structure of the conductive features. Subsequently, the excess conductive material114and the barrier layer116disposed on the top surface of the second dielectric layer108, and possibly a top portion of the dielectric layer108, can be removed to leave a planarized upper surface118, such as by CMP. The planarization may be suitable for direct bonding, as described herein. After planarization, the conductive contact material portions114are confined in their isolated cavities, and thus become conductive features114a, as shown inFIG.2. The conductive features114acan be conductive vias or contact pads or other conductive functional or nonfunctional features, such as dummy pads, lateral traces, or the upper ends of vias such as through substrate vias (TSVs).

The conductive features110,112,114amay be characterized by a crystalline microstructure with grains. In general, average grain size of the crystalline structure of the conductive feature110,112.114amay range from 0.2 μm to 5 μm or even larger. Factors that can influence grain size of the crystal structure in a conductive feature may include the width of the conductive feature, the impurity content in the conductive feature and the thermal history of the conductive feature. For example, grain size may be bigger for a wider conductive feature. For conventionally plated copper conductive features, for example, the impurity content is typically less than 20 ppm, e.g., less than 10 ppm.

In some embodiments, the conductive material114may be deposited over the first dielectric layer106, patterned to form conductive material114a.The second dielectric layer108is subsequently formed over dielectric layer106and embedding the patterned conductive material114a,—forming a non-planar dielectric layer. The non-planar second dielectric layer108and the conductive features114acan be planarized, e.g., with CMP methods, to form the smooth planar upper surface118suitable for direct bonding.

The upper surface118of the element100includes an upper surface of the second dielectric layer108and upper surfaces of the conductive features114a.The top layer of the element100, including the second dielectric layer108and the conductive features114aof the illustrated embodiment, can be referred to as a hybrid bonding layer, and the upper surface118can be prepared to be directly bonded to another semiconductor element or dielectric element without an adhesive layer. The skilled artisan will appreciate that in other embodiments, the processes described herein can be applied to more complicated or simpler structures than shown inFIG.2, such as greater or fewer metallization levels between the device level and the bonding layer. The skilled artisan will also appreciate that the processes and structures described herein are also applicable to non-IC microelectronic elements, such as, without limitation, passive devices, MEMS, interposers, other packaging substrates, etc.

As shown inFIG.3, top portions of the conductive features114aare selectively removed (e.g., by etching) to form recesses122. The depth of the recesses122can be between about 1 nm and 100 nm, for example, between about 3 nm and 80 nm, or between about 5 nm and 60 nm. In some embodiments, deeper recesses can be formed, e.g., between about 10 nm and 150 nm or even deeper, depending in part upon the structure of the conductive features114aand the amount of underlying metal that can drive expansion. The skilled artisan will appreciate that the recesses122ofFIG.3can be formed by a separate recessing operation after planarization and annealing, as shown, or can be the result of the CMP process described above with respect toFIG.2with proper selection of physical components (e.g., pad hardness, speed) and chemical components (e.g., selectivity of the slurry) to leave the conductive features114arecessed as shown inFIG.3. In some embodiments, instead of recessing, the conductive features114amay protrude over the upper surface of the second dielectric layer108. The thickness of the protrusion (not shown) can be between about 1 nm and 30 nm, for example, between about 3 nm and 20 nm, or between about 5 nm and 30 nm. In some embodiments, thicker protrusions can be formed, e.g., between about 10 nm and 50 nm or even thicker. In some embodiments, there is no recess nor protrusion, and the conductive features114aare formed coplanar with the upper surface118of the second dielectric layer108.

InFIG.4, the element100has been exposed to an oxidation environment that oxidizes upper portions of the conductive features114a.The oxidation process can be a plasma oxidization (e.g., by exposure to an oxygen-containing plasma), thermal oxidization, ozone exposure, or wet oxidation (e.g., by exposure to inorganic or organic peroxides). In an example, the element100ofFIG.3can be subjected to an ashing process, in which products of oxygen-containing plasma are supplied to the element. Such a process is referred to as “ashing” because it is traditionally employed for burning off organic photoresist. As illustrated inFIG.4, during the oxidation process, oxygen can react with the upper surfaces of the conductive features114a.As such a metal oxide layer124forms on the conductive features114aas a result of oxidation of a metal of the conductive feature114a.The metal oxide layer124grown in such a manner tends to have a microstructure, for example, characterized by nanograins, that differs from the larger grain-sized microstructure of the conductive features110,112,114a.For example, the nanograins may have an average grain size (e.g., average of maximum grain dimensions) in the range of about 2 nm to 100 nm, e.g., an average grain size in a range of about 5 nm to 60 nm, or in a range of about 8 nm to 80 nm. As shown inFIG.4. the addition of oxygen into the layer and the growth of oxide with a microstructure (e.g., nanograins) may cause the resultant metal oxide layer124to protrude above the upper dielectric surface of the hybrid bonding layer. Also depending on the depth of the recess122or the height of the protrusion, the formed metal oxide layer124may be recessed below the upper surface118, for example, by between about 2 nm to 10 nm or even more, or may protrude over the upper surface118.

In the embodiment shown inFIG.4, the metal oxide layers124are formed by oxidation of the upper surfaces of the conductive features114awhich comprise a metal. One advantage of oxidation is that the metal oxide layers124can be formed selectively on the conductive features114ato controlled depth. However, metal oxide grains can be formed at the upper surface of the conductive features114ain other ways. For example, the metal oxide layers124can be formed by sputtering (e.g., reactive sputtering) metal oxide grains onto the upper surfaces of the conductive features114a.As an example, the metal oxide layers124can be formed by spin-coating metal oxide grains onto the upper surfaces of the conductive features114a.As another example, the metal oxide layers124can be formed by electrolytic or electroless deposition methods, chemical vapor deposition (CVD) methods or atomic later deposition (ALD) methods. In such embodiments, separate patterning processes may be employed to either prevent formation of the metal oxide over the dielectric field regions, or to remove any metal oxide from over the dielectric field regions of the upper surface118.

Each of the methods set forth above may produce different microstructures of the metal oxide grains in the metal oxide layers124. For example, the oxidation process, as illustrated inFIG.4, may cause metal oxide to grow from the existing upper surfaces of the conductive features114a.As such, the microstructure of the metal oxide grains may carry unique signature of the grain forming process. Further, different oxidation agents, for example, products of in situ or remote oxygen plasma, thermal oxidation, wet chemical oxidation, or electrolytic oxidation, may cause different and unique signatures. If the oxide grains are deposited, whether by sputtering or by spin-coating, on the conductive features114ato form the metal oxide layers124, the microstructure of the metal oxide grains may show unique signature of the specific deposition process. Other processes, e.g., electrolytic methods or CVD methods, may have their unique signatures in the microstructures of the formed oxide grains. The metal oxide nanograins may be spherical, cubic, acicular, in the form of nanofibers, or other shapes.

In each of the methods described above, the size of the deposited metal oxide grains may be controlled through process control. The size or diameter of the metal oxide grains may be determined through routine experimentation, e.g., on the scale of nanometers, (e.g., an average size of a maximum dimension in a range of about 2 nm to 100 nm, in a range of about 5 nm to 60 nm, or in a range of about 8 nm to 80 nm), for desired results with respect to bonding conditions and yield.

Referring toFIG.5, the element100may be exposed to an environment to chemically reduce the metal oxide in the metal oxide layers124to a layer of metal grains or conductive material. The chemical reduction can be accomplished by exposure to a reducing ambient, such as, for example, hydrogen-containing plasma, water vapor plasma, hydrogen gas, or forming gas. Consequently, the metal oxide layers124may be at least partially transformed to a metal layer126, as shown inFIG.5. The metal layer126may take the form of nanograins and resemble a powder, flakes, needle like, or grains with spherical and non-spherical shapes. While shown with a reduced thickness relative to the metal oxide layers124ofFIG.4, the oxidation and reduction process nevertheless results in at least partial filling of the recess122because the microstructure of the resultant metal layer126may have reduced density relative to the metal prior to oxidation. In some embodiments, the reduced metal layer126with a microstructure (e.g., nanograins) may protrude over the upper surface118.

For example, the metal oxide reduction process may comprise an annealing process in a reducing environment, such as with forming gas at an elevated temperature for a predetermined duration (e.g., at 25° C.-150° C. for 3 minutes to 90 minutes). The skilled artisan will appreciate that the temperature and duration of the reduction anneal may differ depending upon the reducing strength of the reducing environment. As such, the metal layer126can be at least partially sintered (or densified) if needed. The metal oxide reduction process may be accomplished under atmospheric pressure, in a reducing liquid or fluid, or in vacuum with a hydrogen ion bearing plasma. In one embodiment, the plasma may be hydrogen plasma, ammonia plasma, water vapor plasma, or a combination of helium or other inert gas and at least one of the mentioned reducing constituents. In one embodiment, the reducing source may comprise a liquid or fluid comprising dimethylamine borane or formic acid.

Experiments have been conducted to oxidize a copper surface of a contact pad by ashing (exposure to products of an oxygen-containing plasma) for 21 minutes, followed by reducing the resultant copper oxide to copper by annealing for 2 hours at 120° C. in the presence of forming gas.FIG.6Ais a scanning electron microscope (SEM) image showing an upper surface132of a copper contact pad in an element prior to oxidation and reduction process. As can be seen, the surface132is smooth. The experimental data shows that the upper surface132of the copper contact pad is recessed by about 16 nm with a surface roughness of about 1.2 nm RMS. In comparison,FIG.6Bshows an SEM image of an upper surface134of the copper contact pad following the oxidation and reduction process. The experimental data reveals that the upper surface134of the reduced copper surface is recessed by about 7.8 nm with a surface roughness of about 2.6 nm RMS. This means that the ashing process increases the roughness of the copper surface from about 1.2 nm RMS to about 2.6 nm RMS, while the recess of the surface decreases from 16 nm to 7.8 nm due to the formation of the copper oxide on the upper surface of the copper contact pad. The experimental data further shows that upon the reduction of the copper oxide, the upper surface134of the reduce copper oxide is recessed by about 8.9 nm with a surface roughness of about 2.2 nm RMS. The increased depth of the recess of upper surface134from about 7.8 nm to about 8.9 nm is indicative of densification of the reduction process. Similarly noted is the increase of the surface from about 1.2 nm RMS of the unoxidized upper surface132to about 2.2 nm RMS of the upper surface124after oxidation and reduction. Evidently, the upper surface134of the reduced metal pad is characterized by having a microstructure of ultra fine grains (e.g., nanograins). Measurements of the grains revealed that the size for the grains is in the range of about 5 nm-60 nm. For other metal materials, e.g., nickel, chromium, gold, indium, tin, platinum, silver, ruthenium, molybdenum, nickel, cobalt, palladium, zinc, tungsten, tantalum, titanium, aluminum, a metal silicide, and alloys thereof, used to make the contact pad, the grain size may be in a range of about 2 nm to 100 nm. The skilled artisan will appreciate that the roughness of the upper surface134of the reduced copper oxide depends on the oxidation process and the subsequent reduction process, including the reducing temperature.

While illustrated and discussed herein as a separate micro-structured metal layer126over the conductive features114a,as shown inFIG.5, the skilled artisan will appreciate that this description is a semantic choice and the metal layer126can be considered part of the conductive features114a.In some embodiments, particularly where the metal layer126is formed by oxidation and reduction, the material of the metal layer126will be the same as that of the underlying conductive features114a,and only the microstructure will differentiate the remainder of the conductive features114afrom the overlying metal layer126. In other embodiments, particularly where the metal layer126is formed by metal oxide deposition and reduction, the metal layer126may be the same or may differ from the remainder of the conductive features114ain both its microstructure and material composition, depending on the composition of the deposited metal oxide.

The microstructure of the metal layer126having ultra small metal grains may be favorable for hybrid bonding when compared to conventional microstructure of the metal, e.g., the conductive features110,112,114a,as described above with respect toFIG.2. For example, the crystalline structure of copper generally comprises large grains, e.g., typically larger than 200 nm or on the order of microns in size or even larger. The structure of copper contact pad surface shown inFIG.6B, which is characterized by ultra small grains, e.g., nanograins, can achieve good quality direct contact pad to contact pad bonding at lower temperatures than copper contact pad without the illustrated microstructure. Without being limited by theory, it is believed that the microstructure left by the oxidation and reduction processes effectively increases diffusion and lowers the fusing temperature of a metal when compared to the same metal without the microstructure. Therefore, when two semiconductor elements are directly bonded together, if at least one of the elements has the conductive features114awith the metal nanograins in the metal layer126as shown inFIG.6B, the metal grains at the bonding surface118can be fused with the conductive features of the other semiconductor element at a lower annealing temperature, when compared with bonding two semiconductor elements without the micro-structured metal layer126. Reduced depth of recesses after the oxidation and reduction processes, when compared to the recess depth just prior to the oxidation and reduction (from 16 nm to 8.9 nm in the example above forFIGS.6A-6B), also confirms the resultant microstructure occupying greater volume than the same metal without the oxidation and reduction. The conducted experiments also indicate remarkably high yield and low electrical resistance for oxidized and reduced conductive features, despite employing lower annealing temperatures for forming the metal-to-metal bonds in hybrid bonding.

In practice, during an activation and/or termination process, the upper surface118or218or both may be exposed to nitrogen bearing plasma (for example nitrogen plasma, forming gas plasma, ammonia plasma, nitrogen containing water vapor plasma). As such, the upper surface134ofFIG.6Bcomprising reduced metal nanograins can adsorb more nitrogen atomic species or moieties compared conventional metal pads, such as the unoxidized and smooth upper surface132. The higher nitrogen absorption may be due to the larger surface area of the metallic nanograins in layer134. Upon hybrid bonding, after the high temperature annealing step, the bonded structure having reduced metal nanograins at bonding surface134may contain higher nitrogen content compared to bonded structure having smooth bonding surface132. For example, the nitrogen content within a bonded structure having metal grain layers with the upper surfaces134may be at least 50 ppm or 500 ppm higher than the nitrogen content at equivalent locations in a bonded structure having contact pads with initially smooth upper surfaces132. As such, the nitrogen content within the bonded conductive features of the presently disclosed bonded structures may be 50 ppm-1000 ppm and even 10000 ppm higher than conventional bonded structures. In some embodiments, the nitrogen content within the conductive features may be at least 250 ppm higher than the nitrogen content of the redistribution layer (RDL) or back end of line (BEOL) layer beneath the bonded conductive features. In some embodiments, the bonded conductive features may comprise oxygen or hydrogen content that are higher than the oxygen or hydrogen content of the RDL or BEOL layer beneath the bonded conductive features.

FIGS.7-9illustrate an example embodiment of another fabrication process to form a microstructure in contact pads favorable for a lower annealing temperature. Similar toFIG.1, the process ofFIGS.7-9starts with the element100, having the conductive material114overburdening trenches formed in the second dielectric layer108. The element100may be subjected to an annealing process. Subsequently, the excess conductive material114may be removed and planarized, e.g., by CMP. However, the planarization stops above the barrier layer116that is disposed on the upper surface of the second dielectric layer108, leaving a thin layer of conductive material114above the barrier layer116. Thus, the conductive material114is shown planarized inFIG.7, but not fully removed from over the second dielectric layer108.

Referring toFIG.8, the element100is exposed to an oxidation environment to oxidize upper portions of the conductive material114, including the thin layer of conductive material114on top of the barrier layer116. As withFIG.4, the oxidation process can be a plasma oxidation, thermal oxidization, ozone exposure, or wet or chemical oxidation. After oxidation, the upper portions of the conductive material114, including the conductive material114on top of the barrier material116above the second dielectric layer108, are oxidized, forming a metal oxide layer134into the upper portions of cavities formed in the second dielectric layer108, as shown inFIG.8. As with the metal oxide layers124inFIG.4, the metal oxide layer134can comprise ultra small metal oxide grains, and may be considered nanograins. The ultra small metal oxide grains can thus have an average size in the nanometer range of about 2 nm-100 nm, about 5 nm-60 nm, or about 8 nm-80 nm.

InFIG.9, the element100may be exposed to an environment that chemically reduces all or a part of the metal oxide layer134to metal. The chemical reduction environment can be a reducing ambient, such as hydrogen plasma, water vapor plasma, hydrogen gas, or forming gas. As with respect to the metal layer126shown inFIG.5, the metal oxide layer134may be transformed to a metal layer136comprising a microstructure, such as the nanograins described elsewhere herein. The reducing environment may range from vacuum to atmospheric pressure and may be performed in a range of about 10° C. to 180° C. such as about 20° C. to 100° C. Subsequently, the metal layer136can be at least partially sintered or densified if needed, e.g., through an annealing process at an elevated temperature for a predetermined duration. The metal layer136can comprise a nanostructure, such as nanograins, as described with respect toFIG.5.

The element100shown inFIG.9may be planarized to remove the excess metal above the barrier layer116and the barrier layer116in the field regions, to achieve the cross-sectional structure of the element100ofFIG.5. The element100can be cleaned and prepared for direct bonding to another element. The preparation steps may comprise exposing either or both of the upper surfaces118and210of the respective substrate100and substrate200to nitrogen plasma, rinsing the bonding surfaces to remove any spurious deleterious particles, and drying the substrates before the bonding operation.

In other embodiments, the metal oxide layer134inFIG.8and the barrier layer116over an upper surface of the second dielectric layer108may be first planarized, e.g., by CMP methods, to form a planar bonding surface comprising a second dielectric upper surface and the conductive features114aeach with a segregated metal oxide layer comprising nanograins. Subsequently, the individual metal oxide layers on top of the respective conductive features114acan be reduced to form respective metal layers.

Referring toFIG.10, the first element100fromFIG.5or9(after planarization) and a second element200are ready to be bonded to form a bonded structure1. While the first element100comprises the metal layer126, having a microstructure as a result of the oxidation and reduction process, on each of the conductive features114aat the bonding surface118, the second element200does not have such a metal layer with a microstructure on its conductive features214. In other embodiments, the second element200can include metal layers having microstructures just like the first element100. As shown inFIG.10, the conductive features214of the second element200are aligned with the corresponding conductive features114aof the first element100. After alignment of the conductive features114a,214, the second element200is moved along a direction220, e.g., operated by a bonding equipment, to be directly bonded with the first element100.

InFIG.11, the second element200is directly bonded to the first element100without an intervening adhesive. The bonding surface118of the first element100and/or a bonding surface218of the second element200may be activated prior to the hybrid bonding process. As such the dielectric layer208of the second element200can be directly bonded to the second dielectric layer108of the first element100. The initial direct bonding of the dielectric surfaces may be performed at room temperature. At this stage, the conductive features214of the second element200are not (fully) bonded to the conductive features114aof the first element100. In some embodiments, the conductive features114a,214of both elements100,200are recessed relative to their surrounding dielectric layers108,208such that there is a gap between the corresponding conductive features114a,214at the stage ofFIG.11.

Moving toFIG.12, the bonded structure1is subjected to an annealing process to heat the bonded elements100and200to an elevated temperature for a predetermined duration. During the annealing process, conductive features114aof the first element100can expand due to the CTE mismatch between the metallic material of the conductive features114a(and any underlying metal features) and the surrounding second dielectric material108. Also due to the CTE mismatch, the conductive features214of the second element200can have a tendency to expand. The expansion of the conductive features114a,214causes the in situ formed nanograin metal layer126of the conductive feature114ato press against and be bonded or fused with the corresponding conductive features214of the element200. In some embodiments, the higher surface mobility of the nanograins metal layer126can lower the melting point due to the microstructure of the metal layer126, facilitating interdiffusion across an initial interface with the conductive features214. The interdiffusion and grain growth can increase the grain size of the nanograins metal layer126from nanometer scale to micron scale. The grain size at the bonding interface or across the bonding interface may range from 0.2 μm to more than 5 μm, depending on the width of the bonded conductive features, for example contact pads, upper ends of vias or TSVs.

Experiments have shown that at certain annealing temperature and duration settings a continuous bonded region may be formed across the interface of the bonded elements. This bonded structure is illustrated schematically as the bonded region230inFIG.13. In this way, mechanical bonding and electrical connection between the conductive features114aof the first element100and the conductive features214of the second element200may be optimally established.

Referring toFIG.13, due to the CTE mismatch between the conductive features and the surrounding dielectric materials, the conductive features114aand the corresponding conductive features214are pressed against each other. The metal layer126of the conductive features114ashown inFIG.12may be bonded or fused with the opposite conductive features214. In some embodiments, the force developed from the CTE mismatch during bonding at the elevated annealing temperature may cause the conductive features114aand214in the bonded region230at the hybrid bonding interface to swell outward, forming a sidewall structure bulging out sideways. In some embodiments, there may not be bulging sidewall at the bonding interface. The profile and the microstructure of the bonded region230may depend on the annealing temperature and the annealing duration, in addition to the microstructure between the conductive features at the time of bonding. As described earlier, the higher surface mobility of the metal layer126can lower the bonding or melting temperature of the metal layer126, facilitating interdiffusion across the bonding interface with the conductive feature214. The interdiffusion and grain growth may consume the nanograins, increasing the grain size of the nanograins of the metal layer126from nanometer scale to micron scale. The grain size at the bonding interface or across the bonding interface may range from 0.2 μm to more than 5 μm, depending on the width of the bonded conductive features, for example contact pads, upper ends of vias or TSVs.

The bonded conductive features114aand214may have higher nitrogen content compared to bonding processes without micro-structured metal layers on conductive features. For example, the nitrogen content within a bonded structure applying the metal grain layers bonding principles may be at least 50 ppm or 500 ppm higher than the nitrogen content at equivalent locations in a bonded structure having contact pads without such nanograins or microstructure. In some embodiments, the nanograins in the reduced metal layer may melt at the bonding interface, fusing with the grains from the opposing bonding surfaces.

Whether any residual microstructural signature from the metal layer126remains in the bonded structure1, differentiating grain structures at the interface from more remote locations of the conductive features114a,214, can depend upon the annealing temperature and duration.

As discussed above with respect toFIGS.6A and6B, the small grains left by the oxidation and reduction process can help achieve lower annealing temperature with good quality direct bonding of conductive features, when compared with bonding two semiconductor elements without the micro-structured metal layer126. In some embodiments, optimal hybrid bonding can be achieved when both the first element100and the second element200have micro-structured surfaces for both of the conductive features114aand214. However, when either one of the first and second elements100and200includes a micro-structured metal layer on its conductive features114aor214, annealing temperature can be substantially reduced. For example, if the conductive features114aof the first element100and the conductive features214of the second element200are both made of copper without a micro-structured (e.g., nanograin) layer between them, the annealing temperature may be 250° C. or higher to achieve equivalent resistance and yield. When one of the first and second elements100and200has micro-structures metal layers126on its conductive features114aor214, the annealing temperature may be reduced to below about 250° C., below about 200° C., or below about 180° C. For example, the anneal temperature for directly bonding the conductive features114ato conductive features214can be reduced to temperatures in a range of about 150° C. to 250° C., 100° C. to 200° C., or 80° C. to 180° C. In some embodiments, the annealing process may be performed in a microwave oven. In this case, the microwave radiation frequency may be tuned to be absorbed by the conductive features, such as the conductive features214,114aand reduced metal layer126. The localized absorption of the microwave radiation by metal layer126can induce locally improved mobility of metal from the conductive nanograins in the metal layer126, thus bonding or fusing the metal layer126on the conductive feature114aof the element100with the conductive feature214of the element200. The localized metal atom mobility may consume the nanograins of metal layer126to form larger grains at the bonding interface or across the bonding interface. The skilled artisan will appreciate that during annealing process temperature is increased to facilitate diffusion of chemical elements without necessarily reaching the melting point of the materials of the bonded structure. The increased diffusion may transfer the conductive features at or near the bonding interface to a different crystal structure or phase and may fuse the conductive features together. In some embodiments, a portion of the metal layer126may by incorporated in a crystalline grain structure or grain boundary disposed around the bonding interface due to the increased diffusion.

The scale of temperature reduction for equivalent annealing effectiveness may be related to the size and material of the metal grains formed in the metal layer126. For example, the annealing temperature for metal grains sized 10 nanometers may be significantly lower than the annealing temperature for metal grains sized 50 nanometers.

One of the thermal challenges of hybrid bonding is bonding of conductive features having varying widths. For example, the bond temperature (or annealing temperature) for bonding substrates having conventional copper contact pads with widths of 10 μm to 50 μm may be about 250° C. However, the bonding temperature for narrower conventional copper contact pads (e.g., with widths of 0. 3 μm to 2 μm) may be higher and may range from 375° C. to 400° C. During annealing the thermal expansion of copper features within damascene cavities with widths or pitches smaller than 10 μm is smaller than thermal expansion of the copper features with widths or pitches greater than 10 μm. With few exceptions, the smaller the width of the damascene conductive structure, the smaller the thermal expansion during anneal, thus calling for higher anneal temperatures. One of the advantages of having metal nanograins in the metal layer126is that the bonding temperature may be less dependent upon the widths or pitches of the conductive features. Thus, the conductive features114aof the element100, comprising contact pads, dummy pads, lateral traces, upper ends of vias or TSVs, and/or other through substrate conductors, having widths or pitches ranging from 0.05 to 50 μm, having nanograin layers126formed thereon, can be bonded below 300° C. or even below 250° C. In some embodiments, the bonding surface118or218or both comprises conductive features (e.g., contact pads, dummy pads, lateral traces, vias, and/or through substrate conductors) may have widths or pitches ranging between 0.05 μm and 100 μm (e.g., between about 0.25 μm and 50 μm, or between 1 μm and 40 μm). These conductive features114aexposed at the bonding surfaces118or218may comprise the metal layers126having nanograins for lower and consistent bonding temperature or annealing temperature. In some embodiments a thin layer of a second conductive material having nanograins may be coated over or incorporated in the conductive features114aor218.

One of the advantages of bonding elements or substrates with nanograin microstructure of the present disclosure is that substrates with large difference in CTEs can be bonded at lower temperatures. A first element or substrate with a CTE of X1 and comprising conductive features with a width less than 10 μm at its bonding surface can be bonded to a second substrate with a CTE of X2 (e.g., where X2 is greater than X1 by at least 4 ppm/° C.) at temperatures from 100° C. to 250° C. (e.g., from 125° C. to 240° C.) as opposed to 350° C. to 400° C. when the first substrate and the second substrate have small or no difference in CTEs. The lower temperature bonding reduces the stress related to large CTE mismatch. In some embodiments, the bonding surfaces of the first and second substrates having different CTEs can comprise conductive features (pads, traces, vias, TSVs, etc.) having widths less than 50 μm, e.g., less than 10 μm. In some embodiments, the bonding surfaces of the first and second substrates having different CTEs can comprise conductive features (pads, traces, vias, TSVs, etc.) having pitches less than 150 μm, e.g., less than 50 μm, less than 10 μm.

In some embodiments, the conductive features114aof the first element100ofFIG.5can comprise a first metal material, e.g., copper, nickel, gold, indium, molybdenum, cobalt, zinc, tungsten, tantalum, or titanium, aluminum, manganese, magnesium, palladium, tin, silver, indium, gallium, or alloys thereof; and the conductive features214in the second element200can comprise a second metal material from the same list of materials listed above. In this way, the first metal material of the conductive features114aand the second material of the conductive features214can be made of the same metal material or different metal materials. In either case, a micro-structured metal layer126may be formed according to the processes described with respect toFIGS.1-9on the conductive features114aand having the same metallic material as the conductive features114a.The metal layer126can substantially reduce the bonding or annealing temperature. In some embodiments, the metal material forming the conductive features114aand the conductive features214may be a high melting point metal with melting point higher than copper, e.g., cobalt or molybdenum. The metal layer126can be formed on the conductive features114aand having the same metallic material as the conductive features114ato substantially reduce the annealing temperature. In other embodiments, for example where a metal oxide layer is deposited and then reduced (as opposed to grown by oxidation and reduced), the metal of the micro-structured metal layer126can be different from the metal of the conductive features114aon which it is formed.

In some high temperature implementations, the conductive features of a second element having a metal or non-metal conductive material with a melting point higher than that of copper (e.g., about 1083° C.) can be bonded to the metal layers126in the first element. For example, the conductive material with melting point higher than copper may be molybdenum, cobalt, tungsten, tantalum, titanium, manganese, nickel, palladium, platinum, rhodium, carbon, or their respective high temperature alloys. The metal layers126in the first element may comprise nanograins of the high melting point metal or non-metal material of the conductive features of the second element. In some embodiments, the composition of the metal layers126may be different from that of the conductive features of the second element the metal layers126to be bonded to. For example, the metal layers126comprising copper nanograins may be bonded to a conductive nickel contact pad of the second element at about 250° C. Upon bonding, the copper nanograins of the metal layer126can be inter diffused with the nickel contact pad to form a nickel copper alloy at the bonding interface. The skilled artisans will appreciate that a conductive material with a high melting point may require a higher annealing temperature. In some embodiments, each of the bonding layers126forms an alloy with the conductive feature of the bonded second element.

In some embodiments, the metal layers126may be configured to facilitate bonding dissimilar first and second conductive features. For example, the composition of the bonding metal layers126may be different from those of the conductive features114a,214of the first and second element100,200to be bonded. In some embodiments, the metal layers126comprising copper nanograins may be formed on the conductive features114aof the first element100, and bonded to the conductive features214of the second element200at about 250° C. (including the annealing process). For example, the metal layers126comprising copper nanograins may be formed on the first conductive features114acomprising nickel. Subsequently, the metal layers126may be bonded to the second conductive features214comprising cobalt at a temperature less than 300° C., e.g., less than 250° C. (including the annealing process). The melting point of the metal layers126, which comprises copper, is substantially lower than a melting point of the first conductive features114a,which comprises nickel, and a melting point of the second conductive features214, which comprises cobalt. Without the nanograin bonding layers126, bonding dissimilar conductive features comprising nickel and cobalt could entail anneal at temperatures higher than 370° C., e.g., higher than 400° C. In some embodiments, for example, the metal layers126comprising copper, nickel, or cobalt, or combinations thereof, that have nanograin microstructure may be formed on the first conductive features114acomprising tungsten or molybdenum, and subsequently bonded to the second conductive feature214comprising tungsten or molybdenum at a temperature less than 375° C., e.g., less than 325° C. (including annealing process). In this case, without the nanograin bonding layer126, significantly higher temperatures, such as higher than 800° C., e.g., higher than 1000° C. may be needed to accomplish metal bonding, which may not be feasible for hybrid bonding many devices due to limited thermal budgets.

To the extend both elements100,200to individual device dies, the process illustrated inFIGS.10-13can represent die-to-die (D2D) hybrid bonding involving a micro-structured metal layer at the bonding interface. The micro-structured metal layer can also be applied to wafer-to-wafter (W2W) hybrid bonding and die-to-wafer (D2W) hybrid bonding to reduce annealing temperature.

FIGS.14-15illustrates a hybrid bonding process to bond two wafer elements300and400together to form a W2W bonded structure2. InFIG.14, the element300is a wafter that includes a plurality of die modules301that may be identical to each other. The plurality of die modules301may also not be identical to each other but may be arranged in the first wafer element300for subsequent singulation. Each of the die modules301includes one or more contact pads314(or other conductive features configured for contacting other conductive features) that are embedded in a dielectric layer308. A micro-structured metal layer326is shown on each contact pad314at the bonding surface of the first wafer element300. The metal layer326may comprise ultra small metal grains, e.g., nanograins.FIG.14also shows the second wafer element400that includes a plurality of die modules401, with each of the die modules401facing a corresponding die module301of the first wafer element300. Each of the die modules401includes one or more contact pads414that are embedded in a dielectric layer408. Both of the wafer elements300,400are sufficiently planarized for direct bonding. One or both of the wafer elements300,400may be activated, and the wafer elements300,400are bonded together. In the illustrated embodiment, only the first wafer element300is provided with the micro-structured metal layer326on its contact pads314; in other embodiments, such a micro-structured metal layer can be provided on the contact pads of both wafers.

Referring toFIG.15, the bonded structure2including the wafer elements300and400may go through an annealing process at an elevated temperature for a predetermined duration. As explained with respect toFIG.12, during the annealing process, due to the CTE mismatch between the metallic material of the contact pads314,414and the surrounding dielectric material308,408, each contact pad314,414can expand. As such, the contact pads314,314are bonded or fused with the metal layer326therebetween. The microstructure of the metal layer326can lower the bonding temperature and facilitate interdiffusion and grain necking between the contact pads314,414, as described above with respect toFIGS.5-6B. The bonding between the metal layer326on the contact pads314and the contact pads414may result in a continuous bonded region230, as shown inFIG.13. As such, good quality bonding and electrical connection between the contact pads314of the first wafer element300and the contact pads414of the second wafer element400may be established. Residual signatures of the metal layers326may or may not remain in the bonded structure2after annealing, depending upon the annealing conditions and whether the metal layers326were formed by reducing oxide of the same metal(s) or different metal(s) from that or those of the contact pads314.

As discussed above when at least one of the wafer elements300,400includes a micro-structured metal layer over its respective contact pad314,414, the bonding or annealing temperature can be substantially reduced. In some embodiments, the bonding surface of substrate300,400or both comprises metal layers326over conductive features314(contact pads, dummy pads, lateral traces, vias, through substrate conductors) having widths or pitches in the range between about 0.05 μm and 100 μm (e.g., between about 0.25 μm and 50 μm or between about 1 μm and 40 μm). The metal layers326exposed at the bonding surface can comprise conductive metal nanograins as described herein. In some embodiments a thin layer of a second conductive material (not shown) may be coated over or incorporated in the metal nanograins layers326. The metal layers326may comprise an alloy, for example an alloy comprising copper, tin, indium, gallium, aluminum, manganese, zinc magnesium, gold, palladium, platinum, or nickel. In some embodiments, the conductive features414of the element may comprise a second nanograin metal layer formed thereon (not shown).

As shown inFIG.16, a top surface of the W2W bonded structure2may be coated with a protective layer440. In some embodiments, the bonded structure2may be coated with a top protective layer440on the top surface and a bottom protective layer (not shown) on a bottom surface of the bonded structure2contacting a dicing sheet350. Subsequently, the bonded structure2may be singulated, e.g., by mechanical dicing, e.g., sawing, laser dicing, or plasma dicing, to separate the plurality of bonded modules3. Sidewalls of individual dies301,401of the bonded modules3will be flush with one another, as they are formed by a common singulation process. InFIG.16, during the singulation process the bonded structure2may be supported by the dicing sheet350. The singulated bonded structure3with the protective layer440is cleaned to remove the protective layer440and other unwanted debris from the top and bottom surfaces and sides of singulated modules3and the dicing sheet350. The cleaning step may comprise stripping off the protective layer440with a suitable solution or solvent. For example, a resist stripper or developer may be applied to dissolve the protective layer440. The stripping step may be followed by a rinsing step, for example, rinsing the plurality of singulated bonded modules3and the dicing sheet350with deionized (DI) water or other liquids and drying the cleaned bonded modules3the dicing sheet350. The drying step may comprise, for example, spin-drying the singulated bonded structure2. The bottom protective layer (not shown) maybe removed in subsequent processes.

FIGS.17-21illustrates a hybrid bonding process to bond dies to a wafer for D2W bonding. Referring toFIG.17, a wafer element500comprises a plurality of die modules that may be identical to each other or not identical to each other but can be arranged for subsequent singulation. Each of the die modules may include one or more contact pads514(or other conductive features) that are embedded in a dielectric layer508, and may be recessed relative to the dielectric layer508as disclosed herein. As shown inFIG.17, the wafer element500is supported by a dicing sheet550and is coated with a protective layer540. Subsequently, the wafer element500is singulated, e.g., by mechanical dicing, laser dicing, or plasma dicing, to separate the plurality of die modules into dies501. In some embodiments, both top and bottom sides of the substrate500may be coated with the top protective layer540and a bottom protective layer (not shown) that can contact the dicing sheet550during the singulation step. At this point, the plurality of die modules are supported by the dicing sheet550, keeping the original lateral positions relative to each other. In some embodiments, the upper surface518of the wafer element500may be activated before coating of the protective layer540. In some embodiments, the upper surface518of the wafer element500may be not activated before the coating process.

InFIG.18, the protective layer540is stripped, exposing the upper bonding surface518of each singulated die501. The singulated dies501with the protective layer540is cleaned to remove the protective layer540and other unwanted debris from the surfaces and sides of singulated dies501and the dicing sheet550. The cleaning step may comprise stripping off the protective layer540with a suitable solution or solvent, as stated above. The stripping step may be followed by a rinsing step, for example, rinsing the singulated dies501and the dicing frame550with DI water or other liquids and drying the cleaned substrates. The drying step may comprise, for example, spin-drying the singulated dies501and the dicing frame550. The bottom protective layer (not shown) maybe removed in subsequent processes.

Note that the individual die modules may have been tested using probe pads of the wafer element500prior to singulation to form the dies501, or may be tested after singulation and removal of the protective layer540, such that only known good dies (KGD) are employed in the subsequent bonding.

InFIG.19, the plurality of dies501mounted on the dicing sheet550may be prepared for direct bonding. The preparation may comprise the previously described cleaning, rinsing and drying. The preparation steps may further include exposing the bonding surface to an activation process to activate the upper surface518of each die501if the upper surface518is not already activated. The activation process may include exposing the plurality of dies501to products of a plasma562(e.g., remote or in situ oxygen-containing and/or nitrogen-containing plasma) in a treatment chamber560for a period of time. Subsequently the die modules501may be rinsed and dried.

InFIG.20, the plurality of dies501may be individually picked and placed at corresponding die modules601of a host wafer element600, forming a temporary bond. Alternatively, the dies501may be mounted to a carrier and “gang” placed on the wafer600with individual die501aligned with individual die module601. At this point a dielectric layer508of each die501is initially bonded to a dielectric layer608of a corresponding die module601the wafer element600. Each die module601of the element600includes one or more contact pads614that are embedded in a dielectric layer608. As described with respect to the first wafer element300ofFIG.14, a micro-structured metal layer626in provided on each contact pad614at the bonding surface of the die modules601, e.g., selectively formed by oxidation and reduction, for hybrid bonding. The metal layer626may comprise ultra small metal grains, e.g., nanograins. The initial bonding of the dies501to the wafer element600can be conducted at room temperature, and aligned contact pads514,614, including the intervening metal layer626, can still have gaps between them at this stage.

In some embodiments, each of the plurality of dies501may comprise at least a TSV or a through substrate conductive feature exposed on the back surface of the die501that is opposite to the bonding surface. The back surfaces of the dies501may be cleaned and dried. The back surfaces of the dies501may be prepared for bonding. For each of the dies501, an additional die having TSV conductive features may be bonded on the prepared back surface to form a two-die stack over the wafer element600after hybrid bonding. In some embodiments, the stacked dies may comprise 3, 4, 5, and up to 20 dies stacked on top of each other over the wafer element600after hybrid bonding. The bonded stacked structure of dies may be annealed to bond the various conductive features in the stacked structure. In some embodiments each of the dies501may have micro-structured metal layer formed over contact pads514at their bonding surfaces.

Referring toFIG.21, the D2W bonded structure4including the dies501and the wafer element600is subjected to an annealing process at an elevated temperature for a predetermined duration. As described with respect toFIG.12andFIG.15, during the annealing process, due to the CTE mismatch between the metallic material of the contact pads514,614and the surrounding dielectric material508,608each contact pad514,614can expand. Accordingly, the contact pad614is pressed against and bonded/fused with the corresponding contact pad514with the micro-structured metal layer626therebetween. The metal layer626substantially lowers the anneal temperature for metal-to-metal bonding and encourages interdiffusion and resultant grain necking across the interface, as described above withFIGS.5-6. The bonding between the metal grain layer626and the contact pad514may result in a continuous bonded region, as discussed with respect toFIG.13. As such, good quality bonding and electrical connection between the contact pads614of the wafer element600and the contact pads514of the wafer element500may be established. As discussed above, when at least one of the wafer element600and the wafer element500(e.g., the die modules501) includes a micro-structured metal layer in each respective contact pad514or614, annealing temperature can be substantially reduced. Residual signatures of the metal layer626may or may not remain in the bonded structure4after annealing, depending upon the annealing conditions and whether the metal layers626were formed by reducing oxide of the same metal(s) or different metal(s) from that or those of the contact pads614.

Subsequently, the bonded structure4may be singulated, e.g., by mechanical dicing, laser dicing, or plasma dicing, to separate into the plurality of bonded modules, each comprising a die501and die module601hybrid bonded together. Each singulated bonded module can be similar to a D2D bonded structure1ofFIG.12. In some embodiments, after singulation, for each bonded module the die501may be smaller than the corresponding die module601of the host wafer element600. In some embodiments, the backside of the wafer element600maybe coated with a protective layer (not shown), the backside protective layer contacting the dicing sheet (not shown) that supports the wafer element600. After the dicing or singulation step, the singulated bonded structure is cleaned to remove the protective layer and other unwanted debris from the surfaces and sides of singulated bonded D2W structure and the dicing sheet (not shown). The cleaning step may comprise stripping off the protective layer with a suitable solution or solvent. For example, a resist stripper or developer may be applied to dissolve the protective layer. The stripping step may be followed by a rinsing step, for example, rinsing the singulated bonded structure and the dicing sheet with DI water or other liquids and drying the cleaned bonded structure. The drying step may comprise, for example spin-drying the singulated bonded structure and the dicing sheet.

Although shown and discussed with the example of semiconductor dies and wafers, the skilled artisan will appreciate that the micro-structured layer of metal on contact pads in a hybrid bonding layer, can be provided for other types of microelectronic elements. For example, such microelectronic elements may include an interposer, a semiconductor package, a flat panel, a dielectric substrate, surface mount devices, passive devices, MEMS devices, etc.

A die or a chip can refer to any suitable type of integrated device die. A wafer is a thin slice of material usually in a round shape for semiconductor device fabrication. After fabrication processes a wafer in general can include a plurality of dies formed thereon. For example, the integrated device dies can comprise an electronic component such as an integrated circuit (such as a processor die, a controller die, or a memory die), a microelectromechanical systems (MEMS) die, an optical device, or any other suitable type of device die. In some embodiments, the electronic component can comprise a passive device such as a capacitor, inductor, or other surface-mounted device. Circuitry (such as active components like transistors) can be patterned at or near active surface(s) of the die in various embodiments. The active surface may be on a side of the die which is opposite the backside of the die. The backside may or may not include any active circuitry or passive devices.

An integrated device die can comprise a bonding surface and a back surface opposite the bonding surface. The bonding surface can have a plurality of conductive bond pads including a conductive bond pad, and a non-conductive material proximate to the conductive bond pad. In some embodiments, the conductive bond pads of the integrated device die can be directly bonded to the corresponding contacts of the substrate or wafer without an intervening adhesive, and the non-conductive material of the integrated device die can be directly bonded to a portion of the corresponding non-conductive material of the substrate or wafer without an intervening adhesive. Directly bonding without an adhesive is described throughout U.S. Pat. Nos. 7,126,212; 8,153,505; 7,622,324; 7,602,070; 8,163,373; 8,389,378; 7,485,968; 8,735,219; 9,385,024; 9,391,143; 9,431,368; 9,953,941; 9,716,033; 9,852,988; 10,032,068; 10,204,893; 10,434,749; and 10,446,532, the contents of each of which are hereby incorporated by reference herein in their entirety and for all purposes. The skilled artisan will readily appreciate that the techniques taught in the incorporated patents can be modified by provision of a micro-structured metal layer between conductive features, by providing a metal oxide layer and reducing it as taught herein.

Various embodiments disclosed herein relate to directly bonded structures in which two or more elements can be directly bonded to one another without an intervening adhesive. Such processes and structures are referred to herein as “direct bonding” processes or “directly bonded” structures. Direct bonding can involve bonding of one material on one element and one material on the other element (also referred to as “uniform” direct bond herein), where the materials on the different elements need not be the same, without traditional adhesive materials. Direct bonding can also involve bonding of multiple materials on one element to multiple materials on the other element (e.g., hybrid bonding).

In some implementations (not illustrated), each bonding layer has one material. In these uniform direct bonding processes, only one material on each element is directly bonded. Example uniform direct bonding processes include the ZIBOND® techniques commercially available from Adeia of San Jose, CA. The materials of opposing bonding layers on the different elements can be the same or different, and may comprise elemental or compound materials. For example, in some embodiments, nonconductive bonding layers can be blanket deposited over the base substrate portions without being patterned with conductive features (e.g., without pads). In other embodiments, the bonding layers can be patterned on one or both elements, and can be the same or different from one another, but one material from each element is directly bonded without adhesive across surfaces of the elements (or across the surface of the smaller element if the elements are differently-sized). In another implementation of uniform direct bonding, one or both of the nonconductive bonding layers may include one or more conductive features, but the conductive features are not involved in the bonding. For example, in some implementations, opposing nonconductive bonding layers can be uniformly directly bonded to one another, and through substrate vias (TSVs) can be subsequently formed through one element after bonding to provide electrical communication to the other element.

In various embodiments, the bonding layers can comprise a non-conductive material such as a dielectric material or an undoped semiconductor material, such as undoped silicon, which may include native oxide. Suitable dielectric bonding surface or materials for direct bonding include but are not limited to inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or can include carbon, such as silicon carbide, silicon oxycarbonitride, low K dielectric materials, SiCOH dielectrics, silicon carbonitride or diamond-like carbon or a material comprising a diamond surface. Such carbon-containing ceramic materials can be considered inorganic, despite the inclusion of carbon. In some embodiments, the dielectric materials at the bonding surface do not comprise polymer materials, such as epoxy (e.g., epoxy adhesives, cured epoxies, or epoxy composites such as FR-4 materials), resin or molding materials.

In other embodiments, the bonding layers can comprise an electrically conductive material, such as a deposited conductive oxide material, e.g., indium tin oxide (ITO), as disclosed in U.S. Provisional Patent Application No. 63/524,564, filed Jun. 30, 2023, the entire contents of which is incorporated by reference herein in its entirety for providing examples of conductive bonding layers without shorting contacts through the interface.

In direct bonding, first and second elements can be directly bonded to one another without an adhesive, which is different from a deposition process and results in a structurally different interface compared to that produced by deposition. In one application, a width of the first element in the bonded structure is similar to a width of the second element. In some other embodiments, a width of the first element in the bonded structure is different from a width of the second element. The width or area of the larger element in the bonded structure may be at least 10% larger than the width or area of the smaller element. Further, the interface between directly bonded structures, unlike the interface beneath deposited layers, can include a defect region in which nanometer-scale voids (nanovoids) are present. The nanovoids may be formed due to activation of one or both of the bonding surfaces (e.g., exposure to a plasma, explained below).

The bond interface between non-conductive bonding surfaces can include a higher concentration of materials from the activation and/or last chemical treatment processes compared to the bulk of the bonding layers. For example, in embodiments that utilize a nitrogen plasma for activation, a nitrogen concentration peak can be formed at the bond interface. In some embodiments, the nitrogen concentration peak may be detectable using secondary ion mass spectroscopy (SIMS) techniques. In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding surface to a nitrogen-containing plasma) can replace OH groups of a hydrolyzed (OH-terminated) surface with NH2molecules, yielding a nitrogen-terminated surface. In embodiments that utilize an oxygen plasma for activation, an oxygen concentration peak can be formed at the bond interface between non-conductive bonding surfaces. In some embodiments, the bond interface can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. The direct bond can comprise a covalent bond, which is stronger than van Der Waals bonds. The bonding layers can also comprise polished surfaces that are planarized to a high degree of smoothness.

In direct bonding processes, such as uniform direct bonding and hybrid bonding, two elements are bonded together without an intervening adhesive. In non-direct bonding processes that utilize an adhesive, an intervening material is typically applied to one or both elements to effectuate a physical connection between the elements. For example, in some adhesive-based processes, a flowable adhesive (e.g., an organic adhesive, such as an epoxy), which can include conductive filler materials, can be applied to one or both elements and cured to form the physical (rather than chemical or covalent) connection between elements. Typical organic adhesives lack strong chemical or covalent bonds with either element. In such processes, the connections between the elements are weak and/or readily reversed, such as by reheating or defluxing.

By contrast, direct bonding processes join two elements by forming strong chemical bonds (e.g., covalent bonds) between opposing nonconductive materials. For example, in direct bonding processes between nonconductive materials, one or both nonconductive surfaces of the two elements are planarized and chemically prepared (e.g., activated and/or terminated) such that when the elements are brought into contact, strong chemical bonds (e.g., covalent bonds) are formed, which are stronger than Van der Waals or hydrogen bonds. In some implementations (e.g., between opposing dielectric surfaces, such as opposing silicon oxide surfaces), the chemical bonds can occur spontaneously at room temperature upon being brought into contact. In some implementations, the chemical bonds between opposing non-conductive materials can be strengthened after annealing the elements.

As noted above, hybrid bonding is a species of direct bonding in which both non-conductive features directly bond to non-conductive features, and conductive features directly bond to conductive features of the elements being bonded. The non-conductive bonding materials and interface can be as described above, while the conductive bond can be formed, for example, as a direct metal-to-metal connection. In conventional metal bonding processes. a fusible metal alloy (e.g., solder) can be provided between the conductors of two elements, heated to melt the alloy, and cooled to form the connection between the two elements. The resulting bond often evinces sharp interfaces with conductors from both elements, and is subject to reversal by reheating. By way of contrast, direct metal bonding as employed in hybrid bonding does not require melting or an intermediate fusible metal alloy, and can result in strong mechanical and electrical connections, often demonstrating interdiffusion of the bonded conductive features with grain growth across the bonding interface between the elements, even without the much higher temperatures and pressures of thermocompression bonding.

FIGS.22and23schematically illustrate cross-sectional side views of first and second elements802,804prior to and after, respectively, a process for forming a directly bonded structure, and more particularly a hybrid bonded structure, according to some embodiments. InFIG.23, a bonded structure800comprises the first and second elements802and804that are directly bonded to one another at a bond interface818without an intervening adhesive. Conductive features806aof the first element802may be electrically connected to corresponding conductive features806bof the second element804. In the illustrated hybrid bonded structure800, the conductive features806aare directly bonded to the corresponding conductive features806bwithout intervening solder or conductive adhesive.

The conductive features806aand806bof the illustrated embodiment are embedded in, and can be considered part of, a first bonding layer808aof the first element802and a second bonding layer808bof the second element804, respectively. Field regions of the bonding layers808a,808bextend between and partially or fully surround the conductive features806a,806b.The bonding layers808a,808bcan comprise layers of non-conductive materials suitable for direct bonding, as described above, and the field regions are directly bonded to one another without an adhesive. The non-conductive bonding layers808a,808bcan be disposed over respective front sides814a,814bof base substrate portions810a,810b.

The first and second elements802,804can comprise microelectronic elements, such as semiconductor elements, including, for example, integrated device dies, wafers, passive devices, discrete active devices such as power switches, MEMS, etc. In some embodiments, the base substrate portion can comprise a device portion, such as a bulk semiconductor (e.g., silicon) portion of the elements802,804, and back-end-of-line (BEOL) interconnect layers over such semiconductor portions. The bonding layers808a,808bcan be provided as part of such BEOL layers during device fabrication, as part of redistribution layers (RDL), or as specific bonding layers added to existing devices, with bond pads extending from underlying contacts. Active devices and/or circuitry can be patterned and/or otherwise disposed in or on the base substrate portions810a,810b,and can electrically communicate with at least some of the conductive features806a,806b.Active devices and/or circuitry can be disposed at or near the front sides814a,814bof the base substrate portions810a,810b. and/or at or near opposite backsides816a,816bof the base substrate portions810a,810b.In other embodiments, the base substrate portions810a,810bmay not include active circuitry, but may instead comprise dummy substrates, passive interposers, passive optical elements (e.g., glass substrates, gratings, lenses), etc. The bonding layers808a,808bare shown as being provided on the front sides of the elements, but similar bonding layers can be additionally or alternatively provided on the back sides of the elements.

In some embodiments, the base substrate portions810a,810bcan have significantly different coefficients of thermal expansion (CTEs), and bonding elements that include such different based substrate portions can form a heterogenous bonded structure. The CTE difference between the base substrate portions810aand810b,and particularly between bulk semiconductor (typically single crystal) portions of the base substrate portions810a,810b,can be greater than 5 ppm/° C. or greater than 10 ppm/° C. For example, the CTE difference between the base substrate portions810aand810bcan be in a range of 5 ppm/° C. to 100 ppm/° C. 5 ppm/° C. to 40 ppm/° C., 10 ppm/° C. to 100 ppm/° C., or 10 ppm/° C. to 40 ppm/° C.

In some embodiments, one of the base substrate portions810a,810bcan comprise optoelectronic single crystal materials, including perovskite materials, that are useful for optical piezoelectric or pyroelectric applications, and the other of the base substrate portions810a,810bcomprises a more conventional substrate material. For example, one of the base substrate portions810a,810bcomprises lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the other one of the base substrate portions810a,810bcomprises silicon (Si), quartz, fused silica glass, sapphire, or a glass. In other embodiments, one of the base substrate portions810a,810bcomprises a III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other one of the base substrate portions810a,810bcan comprise a non-III-V semiconductor material, such as silicon (Si), or can comprise other materials with similar CTE, such as quartz, fused silica glass, sapphire, or a glass. In still other embodiments, one of the base substrate portions810a,810bcomprises a semiconductor material and the other of the base substrate portions810a,810bcomprises a packaging material, such as a glass, organic or ceramic substrate.

In some arrangements, the first element802can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the first element802can comprise a carrier or substrate (e.g., a semiconductor wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, forms a plurality of integrated device dies, though in other embodiments such a carrier can be a package substrate or a passive or active interposer. Similarly, the second element804can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element804can comprise a carrier or substrate (e.g., a semiconductor wafer). The embodiments disclosed herein can accordingly apply to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In W2W processes, two or more wafers can be directly bonded to one another (e.g., direct hybrid bonded) and singulated using a suitable singulation process. After singulation, side edges of the singulated structure (e.g., the side edges of the two bonded elements) can be substantially flush (substantially aligned x-y dimensions) and/or the edges of the bonding interfaces for both bonded and singulated elements can be coextensive, and may include markings indicative of the common singulation process for the bonded structure (e.g., saw markings if a saw singulation process is used).

While only two elements802,804are shown, any suitable number of elements can be stacked in the bonded structure800. For example, a third element (not shown) can be stacked on the second element804, a fourth element (not shown) can be stacked on the third element, and so forth. In such implementations, through substrate vias (TSVs) can be formed to provide vertical electrical communication between and/or among the vertically-stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent one another along the first element802. In some embodiments, a laterally stacked additional element may be smaller than the second element. In some embodiments, the bonded structure can be encapsulated with an insulating material, such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxynitrocarbide, etc.). One or more insulating layers can be provided over the bonded structure. For example, in some implementations, a first insulating layer can be conformally deposited over the bonded structure, and a second insulating layer (which may include be the same material as the first insulating layer, or a different material) can be provided over the first insulating layer.

To effectuate direct bonding between the bonding layers808a,808b,the bonding layers808a,808bcan be prepared for direct bonding. Non-conductive bonding surfaces812a,812bat the upper or exterior surfaces of the bonding layers808a,808bcan be prepared for direct bonding by polishing, for example, by chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces812a,812bcan be less than 30 Å rms. For example, the roughness of the bonding surfaces812aand812bcan be in a range of about 0.1 Å rms to 15 Å rms, 0.5 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms. Polishing can also be tuned to leave the conductive features806a,806brecessed relative to the field regions of the bonding layers808a,808b.

Preparation for direct bonding can also include cleaning and exposing one or both of the bonding surfaces812a,812bto a plasma and/or etchants to activate at least one of the surfaces812a,812b.In some embodiments, one or both of the surfaces812a,812bcan be terminated with a species after activation or during activation (e.g., during the plasma and/or etch processes). Without being limited by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surface(s)812a,812b,and the termination process can provide additional chemical species at the bonding surface(s)812a,812bthat alters the chemical bond and/or improves the bonding energy during direct bonding. In some embodiments, the activation and termination are provided in the same step, e.g., a plasma to activate and terminate the surface(s)812a,812b.In other embodiments, one or both of the bonding surfaces812a,812bcan be terminated in a separate treatment to provide the additional species for direct bonding. In various embodiments, the terminating species can comprise nitrogen. For example, in some embodiments, the bonding surface(s)812a,812bcan be exposed to a nitrogen-containing plasma. Other terminating species can be suitable for improving bonding energy, depending upon the materials of the bonding surfaces812a,812b. Further, in some embodiments, the bonding surface(s)812a,812bcan be exposed to fluorine. For example, there may be one or multiple fluorine concentration peaks at or near a bond interface818between the first and second elements802,804. Typically, fluorine concentration peaks occur at interfaces between material layers. Additional examples of activation and/or termination treatments may be found in U.S. Pat. No. 9,391,143 at Col. 5, line 55 to Col. 7, line 3; Col. 8, line 52 to Col. 9, line 45; Col. 10, lines 24-36; Col. 11, lines 24-32, 42-47, 52-55, and 60-64; Col. 12, lines 3-14, 31-33, and 55-67; Col. 14, lines 38-40 and 44-50; and U.S. Pat. No. 10,434,749 at Col. 4, lines 41-50; Col. 5, lines 7-22, 39, 55-61; Col. 8, lines 25-31, 35-40, and 49-56; and Col. 12, lines 46-61, the activation and termination teachings of which are incorporated by reference herein.

Thus, in the directly bonded structure800, the bond interface818between two non-conductive materials (e.g., the bonding layers808a,808b) can comprise a very smooth interface with higher nitrogen (or other terminating species) content and/or fluorine concentration peaks at the bond interface818. In some embodiments, the nitrogen and/or fluorine concentration peaks may be detected using various types of inspection techniques, such as SIMS techniques. The polished bonding surfaces812aand812bcan be slightly rougher (e.g., about 1 Å rms to 30 Å rms, 3 Å rms to 20 Å rms, or possibly rougher) after an activation process. In some embodiments, activation and/or termination can result in slightly smoother surfaces prior to bonding, such as where a plasma treatment preferentially erodes high points on the bonding surface.

The non-conductive bonding layers808aand808bcan be directly bonded to one another without an adhesive. In some embodiments, the elements802,804are brought together at room temperature, without the need for application of a voltage, and without the need for application of external pressure or force beyond that used to initiate contact between the two elements802,804. Contact alone can cause direct bonding between the non-conductive surfaces of the bonding layers808a,808b(e.g., covalent dielectric bonding). Subsequent annealing of the bonded structure800can cause the conductive features806a,806bto directly bond.

In some embodiments, prior to direct bonding, the conductive features806a,806bare recessed relative to the surrounding field regions, such that a total gap between opposing contacts after dielectric bonding and prior to anneal is less than 15 nm, or less than 10 nm. Because the recess depths for the conductive features806aand806bcan vary across each element, due to process variation, the noted gap can represent a maximum or an average gap between corresponding conductive features806a,806bof two joined elements (prior to anneal). Upon annealing, the conductive features806aand806bcan expand and contact one another to form a metal-to-metal direct bond.

During annealing, the conductive features806a,806b(e.g., metallic material) can expand while the direct bonds between surrounding non-conductive materials of the bonding layers808a,808bresist separation of the elements, such that the thermal expansion increases the internal contact pressure between the opposing conductive features. Annealing can also cause metallic grain growth across the bonding interface, such that grains from one element migrate across the bonding interface at least partially into the other element, and vice versa. Thus, in some hybrid bonding embodiments, opposing conductive materials are joined without heating above the conductive materials' melting temperature, such that bonds can form with lower anneal temperatures compared to soldering or thermocompression bonding.

In various embodiments, the conductive features806a,806bcan comprise discrete pads, contacts, electrodes, or traces at least partially embedded in the non-conductive field regions of the bonding layers808a,808b.In some embodiments, the conductive features806a,806bcan comprise exposed contact surfaces of TSVs (e.g., through silicon vias).

As noted above, in some embodiments, in the elements802,804ofFIG.22prior to direct bonding, portions of the respective conductive features806aand806bcan be recessed below the non-conductive bonding surfaces812aand812b,for example, recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 10 nm. Due to process variation, both dielectric thickness and conductor recess depths can vary across an element. Accordingly, the above recess depth ranges may apply to individual conductive features806a,806bor to average depths of the recesses relative to local non-conductive field regions. Even for an individual conductive feature806a,806b,the vertical recess can vary across the feature, and so can be measured at or near the lateral middle or center of the cavity in which a given conductive feature806a,806bis formed, or can be measured at the sides of the cavity.

Beneficially, the use of hybrid bonding techniques (such as Direct Bond Interconnect, or DBI®, techniques commercially available from Adeia of San Jose, CA) can enable high density of connections between conductive features806a,806bacross the direct bond interface818(e.g., small or fine pitches for regular arrays).

In some embodiments, a pitch p of the conductive features806a,806b,such as conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or even less than 1 μm. For some applications, the ratio of the pitch of the conductive features806aand806bto one of the lateral dimensions (e.g., a diameter) of the bonding pad is less than is less than 20, or less than 10, or less than 5, or less than 3 and sometimes desirably less than 2. In various embodiments, the conductive features806aand806band/or traces can comprise copper or copper alloys, although other metals may be suitable, such as nickel, aluminum, or alloys thereof. The conductive features disclosed herein, such as the conductive features806aand806b,can comprise fine-grain metal (e.g., a fine-grain copper). Further, a major lateral dimension (e.g., a pad diameter) can be small as well, e.g., in a range of about 0.25 μm to 30 μm, in a range of about 0.25 μm to 5 μm, or in a range of about 0.5 μm to 5 μm.

For hybrid bonded elements802,804, as shown, the orientations of one or more conductive features806a,806bfrom opposite elements can be opposite to one another. As is known in the art, conductive features in general can be formed with close to vertical sidewalls, particularly where directional reactive ion etching (RIE) defines the conductor sidewalls either directly though etching the conductive material or indirectly through etching surrounding insulators in damascene processes. However, some slight taper to the conductor sidewalls can be present, wherein the conductor becomes narrower farther away from the surface initially exposed to the etch. The taper can be even more pronounced when the conductive sidewall is defined directly or indirectly with isotropic wet or dry etching. In the illustrated embodiment, at least one conductive feature806bin the bonding layer808b(and/or at least one internal conductive feature, such as a BEOL feature) of the upper element804may be tapered or narrowed upwardly, away from the bonding surface812b.By way of contrast, at least one conductive feature806ain the bonding layer808a(and/or at least one internal conductive feature, such as a BEOL feature) of the lower element802may be tapered or narrowed downwardly, away from the bonding surface812a.Similarly, any bonding layers (not shown) on the backsides816a,816bof the elements802,804may taper or narrow away from the backsides, with an opposite taper orientation relative to front side conductive features806a,806bof the same element.

As described above, in an anneal phase of hybrid bonding, the conductive features806a,806bcan expand and contact one another to form a metal-to-metal direct bond. In some embodiments, the materials of the conductive features806a,806bof opposite elements802,804can interdiffuse during the annealing process. In some embodiments, metal grains grow into each other across the bond interface818. In some embodiments, the metal is or includes copper, which can have grains oriented along the111crystal plane for improved copper diffusion across the bond interface818. In some embodiments, the conductive features806aand806bmay include nanotwinned copper grain structure, which can aid in merging the conductive features during anneal. There is substantially no gap between the non-conductive bonding layers808aand808bat or near the bonded conductive features806aand806b.In some embodiments, a barrier layer may be provided under and/or laterally surrounding the conductive features806aand806b(e.g., which may include copper). In other embodiments, however, there may be no barrier layer under the conductive features806aand806b.

In one aspect, a process is provided for preparing an element for hybrid bonding. The process includes providing a metal oxide layer over a conductive feature, where the conductive feature is at least partially embedded in a dielectric material and the conductive feature and the dielectric material form a bonding layer of a first element. The process also includes chemically reducing the metal oxide layer to form a metal layer. A bonding surface of the bonding layer of the first element is prepared for hybrid bonding to a second element.

In some embodiments, the metal oxide layer includes metal oxide grains. The metal oxide layer can include an oxide of a metal of the conductive feature, and the metal layer can include a layer of a metal of the conductive feature. In some embodiments, the metal layer is more conductive than the metal oxide layer. In some embodiments, a metal of the conductive feature and a metal in the metal oxide layer include at least one of copper, nickel, gold, indium, molybdenum, cobalt, zinc, tungsten, tantalum, titanium, aluminum, copper, nickel, chromium, gold, indium, tin, platinum, silver, ruthenium, molybdenum, palladium, cobalt, zinc, tungsten, tantalum, titanium, or aluminum. In some embodiments, the metal layer comprises nanograins, where the nanograins have an average dimension in the range of about 2 nm to 100 nm. The nanograins can have an average dimension in the range of about 8 nm to 80 nm, or the nanograins can have an average dimension in the range of about 5 nm to 60 nm.

In some embodiments, the process also includes, before providing the metal oxide layer over the conductive feature, forming a recess in the conductive feature relative to an upper surface of the bonding layer. A depth of the recess can be in the range of about 5 nm to 100 nm relative to the upper surface.

In some embodiments, providing the metal oxide layer over the conductive feature includes oxidizing a conductive material disposed over the dielectric material and oxidizing a part of the conductive feature. In some embodiments, providing the metal oxide layer over the conductive feature includes oxidizing a layer of the conductive feature. The oxidizing process can include plasma oxidation, thermal oxidation, or wet oxidation. In other embodiments, providing the metal oxide layer over the conductive feature includes sputtering the metal oxide layer onto the conductive feature, spin-coating the metal oxide layer onto the conductive feature, electrolytic or electroless deposition, or depositing the metal oxide layer by chemical vapor deposition (CVD), atomic layer deposition (ALD), or wet processing methods.

In some embodiments, chemically reducing the metal oxide layer includes exposing the first element to a reducing environment. The reducing environment can include a hydrogen-containing plasma, a water vapor plasma, or a forming gas.

In some embodiments, preparing the bonding surface includes planarizing the bonding surface. Preparing the bonding surface can also include activating a surface of the dielectric material.

In another aspect, a process for hybrid bonding is provided. The process includes providing a metal oxide layer over a first conductive feature, where the first conductive feature is at least partially embedded in a first dielectric material, and the first conductive feature and the first dielectric material forma first bonding layer of a first element. The process also includes chemically reducing the metal oxide layer to form a metal layer. A first bonding surface of the first bonding layer of the first element is prepared for hybrid bonding. The first dielectric material is directly bonded to a second dielectric material of a second element. After bonding the first dielectric material to the second dielectric material, the first element and the second element are annealed at an annealing temperature to complete a hybrid bond between the first conductive feature of the first element and a second conductive feature of the second element.

In some embodiments, the first conductive feature includes copper, and the annealing temperature is below about 250° C., below about 200° C., or below about 180° C.

In some embodiments, the first conductive feature and the second conductive feature include cobalt and/or molybdenum, where the metal oxide layer includes cobalt and/or molybdenum.

In some embodiments, the first element and the second element are dies. In other embodiments, the first element and the second element are wafers. In yet other embodiments, the first element includes at least one die and the second element is a wafer including at least one module, wherein the die and the module are aligned.

In another aspect, a process of fabricating a microelectronic element is provided. The process includes at least partially oxidizing a conductive feature in a bonding layer. The bonding layer forms part of the microelectronic element and includes a dielectric material surrounding the conductive feature. The conductive feature is exposed at an upper surface of the bonding layer. The process includes reducing the conductive feature after at least partially oxidizing the conductive feature. The process also includes planarizing the upper surface to prepare the bonding layer for hybrid bonding.

In some embodiments, after reducing the conductive feature, a surface of the conductive feature includes nanograins.

In some embodiments, before at least partially oxidizing the conductive feature, a recess is formed in the conductive feature relative to the upper surface of the bonding layer.

In still another aspect, a method is provided for fabricating a device. The method includes providing the device with a base substrate and a hybrid bonding layer disposed over the base substrate, where the hybrid bonding layer has at least one conductive feature at least partially embedded in a dielectric material. The conductive feature is exposed at an upper surface. The method also includes converting a top layer of the conductive feature to an oxidized layer. The oxidized layer is converted to a metal layer.

In some embodiments, the metal layer include nanograins.

In some embodiments, the base substrate includes single crystal semiconductor material, an interposer, a semiconductor package, a flat panel, a dielectric substrate, a MEMS device, or a passive device.

In some embodiments, the method also includes directly bonding the device to an external device to form a bonded structure. After bonding, the bonded structure is annealed at an annealing temperature.

In still another aspect, a process is provided for preparing a first element for hybrid bonding to a second element. The process includes providing or forming a metal compound layer over a conductive feature, where the conductive feature is at least partially embedded in a dielectric material, and the conductive feature and the dielectric material forms a bonding layer of the first element. The process also includes reducing the metal compound layer to form a metal layer. A bonding surface of the bonding layer is prepared for hybrid bonding.

In some embodiments, the metal compound layer includes a metal oxide, a metal nitride, a metal fluoride, a metal gluconate, or a metal amide. The metal layer can include nanograins of a metal.

Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Moreover, as used herein, when a first element is described as being “on” or “over” a second element, the first element may be directly on or over the second element, such that the first and second elements directly contact, or the first element may be indirectly on or over the second element such that one or more elements intervene between the first and second elements. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.