Nonvolatile memory devices and methods of forming the same

Nonvolatile memory devices and methods of forming the same are provided, the nonvolatile memory devices may include first regions and second regions which extend in a first direction and are alternately disposed in a semiconductor substrate along a second direction crossing the first direction. Buried doped lines are formed at the first regions respectively and extend in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. Bulk regions doped with a dopant of a second conductivity type and device isolation patterns are disposed along the second direction. The bulk regions and the device isolation patterns may be formed in the second regions. Word lines crossing the buried doped lines and the bulk regions are formed parallel to one another. Contact structures are connected to the buried doped lines and disposed between the device isolation patterns. Sidewalls of the device isolation patterns disposed in the first direction overlap with the word lines directly adjacent to the contact structures.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims the benefit of priority under 35 U.S.C. §119 from Korean Patent Application No. 10-2008-0100303, filed on Oct. 13, 2008, the entire contents of which is herein incorporated by reference in its entirety.

BACKGROUND

Example embodiments disclosed herein relate to semiconductor devices and methods of forming the same. Other example embodiments relate to nonvolatile memory devices and methods of forming the same.

2. Description of Related Art

As the integration of a semiconductor device increases, the width of patterns and spaces between the patterns are reduced. A reduction in the width of patterns, or in the spaces between the patterns, results in an increase in the costs associated with manufacturing a semiconductor device. Exposure equipment that uses a corresponding short wavelength may be necessary to form a pattern having a reduced line width. However, exposure equipment that produces a pattern having a reduced line width is costly, thereby increasing the costs associated with manufacturing the semiconductor device.

A reduction in the width of the patterns and the spaces of the patterns causes a variety of difficulties in manufacturing a semiconductor device. For example, a reduction in the space between gate patterns makes it difficult to form a source plug and a drain plug connected to a source electrode and a drain electrode, respectively, of a transistor. Because a bit line is formed to cross a source line, the bit line is not formed on the same layer as the source line. And, at least one of the bit line and the source line is connected to a drain electrode or a source electrode through plugs. In this case, a space between the gate patterns should be formed wide enough to prevent (or reduce the likelihood of) a short between a plug and a gate electrode. The necessity of wide space hinders the ability to form a more integrated semiconductor device.

In the case of a conventional NOR-type flash memory device, because the source electrodes are connected to one another through a buried source line, the number of source plugs may be reduced. Because the drain electrodes of cells are connected to a bit line through drain plugs, a NOR-type flash memory device has a lower degree of integration than a NAND-type flash memory device.

Methods that reduce the number of drain plugs have been studied.

SUMMARY

Example embodiments disclosed herein relate to semiconductor devices and methods of forming the same. Other example embodiments relate to nonvolatile memory devices and methods of forming the same.

Example embodiments provide a nonvolatile memory device including first regions and second regions extending in a first direction. The first and second regions may be alternately disposed in a semiconductor substrate along a second direction crossing the first direction. The nonvolatile memory device includes buried doped lines formed at the first regions respectively and extending in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. The non-volatile memory device includes bulk regions doped with a dopant of a second conductivity type and device isolation patterns disposed along the second direction. The bulk regions and the device isolation patterns may be formed in the second regions. Word lines crossing the buried doped lines and the bulk regions may be formed parallel to one another. Contact structures may be connected to the buried doped lines and disposed between the device isolation patterns. Sidewalls of the device isolation patterns disposed in the first direction overlap with the word lines directly adjacent to the contact structures.

Other example embodiments provide a method of forming a nonvolatile memory device. The method may include providing a semiconductor substrate including first regions and second regions extended in a first direction. The first and second regions may be alternately disposed along a second direction crossing the first direction. Bulk regions doped with a dopant of a second conductivity type, and device isolation patterns, may be formed disposed along a second direction crossing the first direction. The bulk regions and the device isolation patterns may be formed in the second regions. Buried doped lines may be formed at the first regions respectively and extend in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. Word lines crossing the buried doped lines and the bulk regions may be formed parallel to one another. Contact structures may be connected to the buried doped lines between the device isolation patterns. Sidewalls of the device isolation patterns disposed in the first direction overlap with the word lines directly adjacent to the contact structures.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. Thus, the invention may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein. Therefore, it should be understood that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the invention.

In the drawings, the thicknesses of layers and regions may be exaggerated for clarity, and like numbers refer to like elements throughout the description of the figures.

In order to more specifically describe example embodiments, various aspects will be described in detail with reference to the attached drawings. However, the present invention is not limited to example embodiments described.

Example embodiments disclosed herein relate to semiconductor devices and methods of forming the same. Other example embodiments relate to nonvolatile memory devices and methods of forming the same.

FIG. 1is a top plan view of a nonvolatile memory device according to example embodiments.FIG. 2is a cross sectional view taken along the line I-I′ ofFIG. 1.FIG. 3is a cross sectional view taken along the line II-II′ ofFIG. 1.FIG. 4is a cross sectional view taken along the line III-III′ ofFIG. 1.

Referring toFIGS. 1 and 2, first regions100aand second regions100bwhich extend parallel to each other along a first direction and alternately disposed in a second direction crossing the first direction, are provided in a semiconductor substrate100. As depicted inFIG. 1, the first direction corresponds to the direction extending along the y-axis and the second direction corresponds to the direction extending along the x-axis. Buried doped lines110are disposed on the first regions100arespectively. The buried doped lines110extend in the first direction and include a dopant of a first conductivity type. The buried doped lines110may be disposed on a surface of the semiconductor substrate100. Top surfaces of the buried doped lines110may be substantially coplanar with a top surface of the semiconductor substrate100. The first conductivity type may be an n-type impurity.

Bulk regions102and device isolation patterns105are disposed in the second regions100b. The bulk regions102may include a dopant of a second conductivity type. The device isolation patterns105are disposed along the second direction crossing the first direction. The bulk regions102are regions in which the device isolation patterns105are not disposed. The second conductivity type may be a p-type impurity. The device isolation patterns105may include a silicon oxide layer. Word lines120may cross the buried doped lines110and the bulk regions102. Contact structures135may be connected to the buried doped lines110. The contact structures135may be disposed between the device isolation patterns105.

The device isolation patterns105are disposed in the semiconductor substrate100along the second direction. The device isolation patterns105may be a silicon oxide layer. For example, the device isolation patterns105may include a HDP oxide layer formed using a high density plasma (HDP) technique, a spin-on-glass (SOG) layer, a medium temperature oxide (MTO) layer, a high temperature oxide (HTO) layer, an undoped silicon layer and/or an undoped germanium layer.

The device isolation patterns105may include a silicon oxide layer (not shown) formed in inner wall of a trench106through a thermal oxidation process. The device isolation patterns105may include a liner (not shown) covering an inner wall of the trench106. The liner may be a material (e.g., a silicon nitride layer) which prevents impurities from penetrating into the semiconductor substrate100.

A portion of the buried doped lines110is disposed between the device isolation patterns105. The other portion of the buried doped lines110is disposed between the bulk regions102. The buried doped lines110may be used as source electrodes of the word lines120, drain electrodes of the word lines120, source lines connecting the source electrodes and bit lines connecting the drain electrodes. A unit cell of the nonvolatile memory device may include two buried doped lines110. One of the two buried doped lines110may be used as a source region and a source line, and the other of the two buried doped lines110may be used as a drain region and a bit line.

A first interlayer insulating layer132covering the word lines120and the device isolation patterns105is provided. Contact structures135connected to the buried doped lines110between the device isolation patterns105may be disposed in the first interlayer insulating layer132. The width of the buried doped lines110to which the contact structures135are connected may be defined by the device isolation patterns105. The contact structures135may include a first silicide layer115which is in contact with the buried doped lines110and a metal contact130connected to the first silicide layer115. The first silicide layer115is provided for an ohmic contact of the buried doped lines110and the metal contact130.

Even if widths of the second direction of the buried doped lines110are smaller than widths of the second direction of the contact structures135, a short between the contact structures135and the semiconductor substrate100may be prevented (or the likelihood reduced) by the device isolation patterns105. As the widths of the buried doped lines110in the second direction are reduced, a scaling down may be possible. A second interlayer insulating layer142is provided onto (or on) the first interlayer insulating layer132. Global bit lines140, which are connected to the contact structures135and extend in the first direction, are provided onto (or on) the second interlayer insulating layer142.

A resistance characteristic of a nonvolatile memory device according to example embodiments increases due to the first silicide layer115. The first silicide layer115may be self-aligned on the buried doped lines110by the device isolation patterns115.

Referring toFIGS. 3 and 4, a top surface of the bulk region102of the semiconductor substrate100may be coplanar with a top surface of the buried doped line110. The word lines120may include a tunnel insulating layer121, a charge storage layer122, a dielectric layer123and a gate electrode124that are sequentially stacked on the semiconductor substrate100. The charge storage layer122may be a floating gate or a charge trap layer. For example, the charge trap layer may be a silicon nitride layer having a high charge trap density or a high dielectric layer having a high charge trap density. The dielectric layer123may be an inter-gate insulating layer if the charge storage layer122is a floating gate and may be a blocking insulating layer preventing charges from leaking into the gate electrode124if the charge storage layer122is a charge trap layer. If the gate electrode124includes polysilicon, the word lines120may further include a second silicide layer125on the gate electrode124.

The word line120directly adjacent to the contact structures135may cover a portion of the device isolation pattern105. The device isolation pattern105is disposed at one side of the adjacent word line120and the buried doped line110. The bulk region102are disposed at the other side of the adjacent word line120facing the one side. This arrangement prevents a silicide layer from being disposed between the word line120directly adjacent to the contact structure135and the device isolation pattern105. The word line120directly adjacent to the contact structure135may be used as a dummy word line. The word line120may include a spacer127. Sidewalls of the device isolation patterns disposed in the first direction overlap with the word lines directly adjacent to the contact structures. The spacer127may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or combinations thereof. The spacers127may cover the buried doped lines110and the bulk regions102between the word lines120so that the buried doped lines110and the bulk regions102are not exposed. The spacer127of the dummy word line comprises first spacers on one sidewall of the dummy word lines and second spacers on other sidewall of the dummy word lines. The first spacers may be directly adjacent to the contact structure135.

FIG. 5is a top plan view of a nonvolatile memory device according to example embodiments.FIG. 6is a cross sectional view taken along the line VI-VI′ ofFIG. 5.

Referring toFIGS. 5 and 6, unlike inFIGS. 1 and 4, word lines120adjacent to the contact structures135may not cover the device isolation patterns105and may be spaced apart from one another. The spacer127may cover a buried doped line110and a bulk region102between the adjacent word line120and the device isolation pattern105. Sidewalls of the device isolation pattern105may overlap with the first spacers of the dummy word line. The second spacers may cover the bulk region102.

This arrangement prevents a silicide layer from being disposed at the separated portion. The word lines120directly adjacent to the contact structures135may not be used as dummy word lines unlike other example embodiments.

According to example embodiments, the device isolation patterns105are disposed between the contact structures135. A first silicide layer115may be self aligned on the buried doped patterns110by the device isolation patterns105. An interconnection resistance may be reduced by a disposal of the first silicide layer115. A short between the semiconductor substrate100and the contact structures135may be prevented by the device isolation patterns105. The second silicide layer125is disposed on the gate electrode124of the word lines120to reduce a resistance between the word line120and a metal interconnection, which is connected to the word line120.

Referring toFIGS. 7athrough9c, a method of forming a nonvolatile memory device according to example embodiments will be described.FIGS. 7b,8band9bare cross sectional views taken along the line V-V′ ofFIGS. 7a,8aand9a, respectively.FIGS. 7c,8cand9care cross sectional views taken along the line VI-VI′ ofFIGS. 7a,8aand9a, respectively.

Referring toFIGS. 7a,7band7c, a semiconductor substrate100including first regions100aand second regions100bwhich extend in a first direction (e.g., along the y-axis) and alternately disposed is provided. Buried doped lines110formed in the first regions100a, extending in the first direction and doped with a dopant of a first conductivity type, are formed. The dopant of a first conductivity type may be an n-type. The buried doped lines110may be formed by performing an ion implantation process using an ion implantation mask (not shown) extending in the first direction.

Bulk regions102doped with a dopant of a second conductivity type and device isolation patterns105disposed to extend in a second direction (e.g., along the x-axis) crossing the first direction are formed in the second regions100b. The bulk region102is a region in which the device isolation patterns are not disposed. The dopant of a second conductivity type may be a p-type.

Forming the device isolation patterns105may include forming a trench106in the semiconductor substrate100and forming an insulating layer (not shown) filling the trench106. The insulating layer may, for example, be a silicon oxide layer. The device isolation patterns105may include a liner oxide layer (not shown) formed by applying a thermal oxidation process to an inner wall of the trench106. The device isolation patterns105may include a liner nitride layer (not shown) formed to cover at least the inner wall of the trench106. The liner nitride layer may prevent impurities from penetrating into the semiconductor substrate100.

The device isolation patterns105are formed, followed by forming the buried doped lines110. The device isolation patterns105are formed at regular intervals, followed by arranging the buried doped lines110between the device isolation patterns105using an ion implantation process. As such, a distance between the device isolation patterns105may define a width (W1, a width measured along a second direction crossing the first direction) of the buried doped line110between the device isolation patterns105.

Referring toFIGS. 8a,8band8c, word lines120crossing the buried doped lines110and the bulk regions102in parallel to one another are formed. The word lines120may be formed of a tunnel insulating layer121, a charge storage layer122, a dielectric layer123and a gate electrode124that are sequentially stacked on the semiconductor substrate100. The gate electrode124may be formed of polysilicon.

A spacer127is formed on a sidewall of the word line120. The spacer127may be formed of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or a combination thereof. An insulating layer is deposited using a chemical vapor deposition (CVD) process, followed by performing an anisotropic etching process. As such, the spacer127may be formed. After forming the spacer127, a first silicide layer115is formed on the buried doped lines110between the device isolation patterns105. Forming the first silicide layer115may include forming a metal layer covering the word lines120and the buried doped lines110, forming the first silicide layer115on the buried doped lines110by applying an annealing process to the metal layer and removing an unreacted metal layer. A space between the word lines120may not be exposed by the spacer127.

If the gate electrode124is formed of polysilicon, the word lines120may include a second silicide layer125on the gate electrode124. The first and second silicide layers115and125may be formed simultaneously (or at the same time).

According to example embodiments, the word line120directly adjacent to the device isolation pattern105may be formed to cover a portion of the device isolation pattern105. The word line120covering a portion of the device isolation pattern105may be used as a dummy word line. In other example embodiments, the word line120directly adjacent to the device isolation pattern105may be formed not to cover a portion of the device isolation pattern105(referring toFIGS. 5 and 6). A separated space between the word line120directly adjacent to the device isolation pattern105and the device isolation pattern105may be covered by the spacer127. This arrangement prevents a silicide layer from forming in the separated space.

Referring toFIGS. 9a,9band9c, a first interlayer insulating layer132is formed covering the word lines120. The first interlayer insulating layer132may be formed of a silicon oxide layer. A metal contact130electrically connected to the first silicide layer115is formed on the first interlayer insulating layer132. The metal contact130and the first silicide layer115may constitute contact structures135. The metal contact130and the buried doped lines110may constitute an ohmic contact by the first silicide layer115. A second interlayer insulating layer142is formed on the first interlayer insulating layer132. Global bit lines140connected to the contact structures135are formed on the second interlayer insulating layer142. The global bit lines140may extend in the first direction and may have a low interconnection resistance by the first silicide layer115.

According to example embodiments, the first silicide layer115may be formed by using the device isolation patterns105. The first silicide layer115may be self-aligned with the buried doped lines110by the device isolation patterns105. Even if the contact structures135are misaligned, the device isolation patterns105may prevent (or reduce the likelihood of) a short between the semiconductor substrate100and the contact structures135. A silicide process according to example embodiments and a silicide process of a transistor disposed at a peripheral region of the nonvolatile memory device may be performed simultaneously.

FIG. 10is a block diagram of an electronic system including a nonvolatile memory device according to example embodiments.

Referring toFIG. 10, an electronic system200may include a controller210, an input/output device220and a memory device230. The controller210, the input/output device220and the memory device230may be connected to one another through a bus250. The bus250may be a path through which data transfer. The controller210may include at least one of a micro processor, a digital signal processor, a microcontroller and a logic device having a function similar to the micro processor, the digital signal processor and the microcontroller. The input/output device220may include at least one selected from a keypad, a keyboard and a display device. The memory device230is a device storing data. The memory device230may store data and/or an instruction executed by the controller210. The memory device230may include the nonvolatile memory device disclosed in example embodiments. The electronic system200may include an interface240for transmitting data to a communication network or receiving data from a communication network. The interface240may be a wireline/wireless shape. The interface240may include an antenna or a wireline/wireless transceiver. The electronic system200may be embodied by a mobile system, a personnel computer, an industrial computer or a logic system performing a variety of functions. For example, the mobile system may be one of a personal digital assistant (PDA), a portable computer, a web tablet, a mobile phone, a wireless phone, a laptop computer, a memory card, a digital music system and a data transmission/receipt system. If the electronic system200is a device which performs a wireless communication, the electronic system200, may be used in a communication interface protocol of a third generation (e.g., CDMA, GSM, NADC, E-TDMA, CDMA 2000).

FIG. 11is a blocking diagram of a memory card including a nonvolatile memory device according to example embodiments.

Referring toFIG. 11, a memory card300may include a memory device310and a memory controller320. The memory device310stores data. The memory device310may have nonvolatile characteristics such as the ability to maintain stored data even if a power supply is interrupted. The memory device310may include the nonvolatile memory device disclosed in the described example embodiments. The memory controller320readouts data stored in the memory device310or stores data in the memory device310in response to a request of decoding/writing of a host.