Semiconductor device with recessed L-shaped spacer and method of fabricating the same

A semiconductor device with a recessed L-shaped spacer and a method for fabricating the same. A recessed L-shaped spacer includes a vertical portion and a horizontal portion. The vertical portion is disposed on lower sidewalls of a conductor pattern, exposing upper sidewalls thereof. A top spacer is on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2:1.

BACKGROUND

The present invention relates in general to semiconductor manufacturing. More particularly, it relates to a semiconductor device with improved sidewall spacers and a method for fabricating the same.

Silicides are commonly used to reduce the gate resistance and the source/drain resistance between adjacent gate electrodes. As the physical geometry of semiconductor devices shrinks, however, the spacing between gate electrodes shrinks as well. The available space for silicide formation shrinks faster than the ground rules for gate-to-gate spacing due to the finite width of the gate spacers. Thus, the formation of silicide in narrow spaces between gates becomes more difficult, leading to an elevated and variable resistance in these regions. Furthermore, dry etching of conventional sidewall spacers is difficult to control and can result in variations in spacer width between adjacent gates. These variations in spacer width further result in poor resistance uniformity.

Referring now toFIG. 1, a cross-section of a partially completed semiconductor device is shown. Two transistor gate patterns12are formed overlying the semiconductor substrate10. The gate patterns12include a gate electrode14overlying a gate dielectric16. An oxide liner layer18and a silicon nitride layer20are deposited in sequence overlying the gate patterns12and the semiconductor substrate10. Note that the silicon nitride layer20is much thicker than the oxide liner layer18. For example, for 80 nm node design rule, the thicknesses of the silicon nitride layer20and the oxide liner layer18are about 650 Å and 130 Å, respectively.

Referring toFIGS. 2 and 3, conventional spacer etching is performed to provide an L-shaped oxide spacer18aand a thicker nitride spacer20a. After formation of source/drain regions22, silicides24are formed on the exposed surface of the gate electrode14and the source/drain regions22. As the available spaced for silicide formation is determined by the spacer widths, the variations in spacer width will result in poor resistance uniformity. With the conventional spacer scheme ofFIG. 2, however, large variations in spacer width during spacer etching often necessitates complex process tuning. A novel spacer scheme with better width control is desirable. It is also desirable to reduce the spacer width to enlarge the space for silicide formation.

Another problem associated with conventional spacers is limited top loss. Referring back toFIG. 2, only a trivial sidewall portion of the gate electrode14is exposed after the spacer dry etching. With the finite exposed area, silicide is difficult to form to provide a high-performance transistor. It would be advantageous for the gate electrode to have a larger area for silicidation.

FIG. 4shows yet another problem with conventional spacers. A contact hole30is etched though an inter-level dielectric (ILD) layer28and a contact etch stop layer26to expose the source/drain regions22. As the stop layer26is typically silicon nitride, the nitride spacer20ais laterally etched during the contact etching process for removal of the stop layer26, leading to undercut30a. The lateral etch poses reliability risks especially when the contact hole30is misaligned.

SUMMARY

According to one aspect of the invention, a semiconductor device with a recessed L-shaped spacers is provided. An exemplary device comprises a conductor pattern, an L-shaped spacer comprising a vertical portion and a horizontal portion, the vertical portion disposed on the lower sidewall of the conductor pattern, exposing upper sidewalls thereof, and a top spacer on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2:1.

According to another aspect of the invention, a method for fabricating a semiconductor device with a recessed L-shaped spacer is provided. An exemplary method comprises forming a conductor pattern on a substrate, forming a first insulating layer and a second insulating layer conformally on the conductor pattern and the substrate at a thickness ratio of at least about 2:1, anisotropically etching the second insulating layer to form a top spacer, and anisotropically etching the first insulating layer to form an L-shaped spacer, wherein the top surface of the L-shaped spacer is recessed below the conductor pattern.

DESCRIPTION

In the following, a preferred embodiment of the invention will be described by referring to formation of sidewall spacers on a gate pattern of a field effect transistor. It will be appreciated, however, that the invention is applicable to any conductor pattern in an integrated circuit, for example, local interconnection or other polysilicon lines for connecting individual semiconductor elements. In this specification, expressions such as “overlying the substrate”, “above the layer”, or “on the film” simply denote a relative positional relationship with respect to the surface of the base layer, regardless of the existence of intermediate layers. Accordingly, these expressions may indicate not only the direct contact of layers, but also, a non-contact state of one or more laminated layers.

Referring now toFIG. 5, a semiconductor substrate100is provided with a transistor gate pattern102thereon. InFIG. 5, only one gate pattern is shown for the sake of clarity though adjacent gate patterns are typically present. The semiconductor substrate100is understood to possibly include silicon, strained silicon, silicon germanium (SiGe), silicon on insulator (SOI), or other suitable materials. The gate pattern102typically includes a gate electrode106overlying a gate dielectric104. The gate dielectric104typically comprises silicon oxide, and the gate electrode106typically comprises doped polysilicon, often referred to simply as polysilicon.

Lightly doped source and drain (LDD) regions (not shown) may be formed by implanting impurity ions into the semiconductor substrate100prior to forming the sidewall spacers of the invention. The implant can be performed using the gate pattern102as an implant mask as is known in the art.

Still referring toFIG. 5, an important aspect of the invention is shown. A first insulating layer108and a second insulating layer110are conformally deposited overlying the gate pattern102and the semiconductor substrate100, with the first insulating layer108being thicker than the second insulating layer110. The thickness ratio of the first insulating layer to the second insulating layer is at least 2:1, preferably 2-4:1. For example, for 80 nm node technology, the thicknesses of the first and second insulating layers108,110are about 350-450 Å and about 100-200 Å, respectively. Preferably in this embodiment, the first insulating layer is silicon oxide deposited by low pressure chemical vapor deposition (LPCVD) using tetraethoxysilane (TEOS) as the reactant gas, and the second insulating layer is silicon nitride or silicon oxynitride deposited by LPCVD. It will be appreciated, however, that the first and second insulating layers may be made of any materials having etch selectivity with respect to each other.

Referring toFIG. 6, another important feature of the invention is shown. The first and the second insulating layers108,110are fabricated into a recessed L-shaped spacer108aand a top spacer110a, respectively. First, the second insulating layer110is anisotropically etched to form the top spacer110aon sidewalls of the first insulating layer108. Next, using the spacer110aas an etch mask, the first insulating layer108is anisotropically etched to form an L-shaped spacer108apositioned between the gate pattern102and the spacer110a. In particular, the first insulating layer108is anisotropically etched down to reduce the vertical thickness thereof, thereby exposing a substantial portion of the upper sidewall102a, for example, about 200-400 Å. The L-shaped spacer108aincludes a vertical portion V between the gate pattern102and the top spacer110a, and a horizontal portion H extending under the top spacer110a. The etching process for forming the L-shaped spacer is preferably carried out by a recipe having an etch selectivity with respective to the first insulating layer108.

Compared to the conventional spacer process shown inFIGS. 1 and 2, the spacer process of the invention may provide many advantages. First, the thicker first insulating layer108enables easy removal of the top portion of the L-shaped spacer108a. The L-shaped spacer108atherefore can be recessed to expose a substantial sidewall portion102aof the gate pattern102, providing a larger silicide reaction area in a subsequent process. According to the invention, the ratio of the width X of the vertical portion V of the L-shaped spacer108ato the height Y of the exposed sidewalls102ais preferably about 1-2:1.

Second, as shown inFIGS. 5 and 6, the spacer profile is now determined by a thinner second insulating layer110. Compared to the thick nitride layer20as inFIG. 1, it can be deposited with a more uniform thickness across a process wafer, and result in a short etching time or allow a lower etching power for the spacer etching process, thereby reducing variations in spacer widths. Accordingly, the spacer widths of the invention can be better controlled, and the resistance uniformity between adjacent gates can be improved.

Third, as the spacer widths are better controlled, a lower margin is required for spacer etching. Thus, the total thickness of the spacer layers, i.e., layers108,110, can be reduced to gain more space for silicidation between adjacent gates. This is particularly desirable when the gate spacing is reduced with the design rule. For example, for silicon oxide as the first insulating layer108and silicon nitride as the second insulating layer110, the conventional approach ofFIG. 1requires a total thickness of 780 Å (oxide/nitride=130 Å/650 Å) for gate spacing of 1630 Å, while the invention only requires a total thickness of 530 Å (oxide/nitride=400 Å/130 Å) for the same design rule, saving about 30% thickness.

As shown inFIG. 6, the semiconductor device according to an embodiment of the invention therefore includes a gate pattern102on a semiconductor device10. An L-shaped spacer108ais provided adjacent to the gate pattern102, comprising a vertical portion V and a horizontal portion H. The vertical portion V is on lower sidewalls of the gate pattern102, exposing upper sidewalls102athereof. A top spacer110aabuts the L-shaped spacer108a, protruding above the same, thus providing a gap between the top spacer110aand the upper sidewalls102aof the gate pattern. The width ratio of the vertical portion V of the L-shaped spacer to the top spacer110ais at least about 2:1 (X/W), preferably about 2-4:1. The width X of the vertical portion V to the height Y of the exposed upper sidewalls102ais about 1-2:1 (X/Y).

Referring toFIG. 7, following the formation of spacers108a,110a, source/drain regions112are formed in the substrate100oppositely adjacent to the gate pattern102by ion implantation. Subsequently, a gate silicide layer116and a junction silicide layer114are formed on the gate pattern102and the source/drain regions112by methods well known in the art. The silicide layers114,116may comprise CoSi2, TiSi2, WSi2, NiSi2, MoSi2, TaSi2, or PtSi, for example. As discussed above, a sufficient silicidation area may be secured because the top surface of the L-shaped spacer108ais recessed to expose upper sidewalls102aof the gate pattern102, and also because the space between two adjacent gates is more open. As a result, the silicide layers114,116are more stably formed, and the gate silicide layer116is thicker than in the case of a non-recessed spacer18aofFIG. 1.

FIGS. 8-9illustrate another advantage provided by the preferred embodiment of the invention. Referring toFIG. 8, following the formation of the silicide layers114,116, a contact etch stop layer118and an ILD layer120are deposited covering the entire substrate. The etch stop layer118is typically silicon nitride and the ILD layer120is typically oxide or low dielectric constant materials. Referring toFIG. 9, a contact opening122is etched down to the source/drain region112by conventional anisotropic etching. During removal of the nitride stop layer118from the source/drain regions112, the horizontal portion H of the L-shaped spacer108a, if oxide has been used, functions as an etch stop and inhibits lateral etching. Accordingly, only limited undercut, if any, is present under the top spacer110a. In a preferred embodiment, the ratio of the width-U of the undercut to the height Z of the horizontal portion is less than about 0.3 (U/Z).

In view of the foregoing, it is readily appreciated that the present invention provides a simple and well-controlled spacer scheme to increase the area for silicide formation. Also, it may allow the spacer process down to the next generation design rule by reducing the spacer thickness. Further, the resulting spacer is less susceptible to undercut by lateral etching. Finally, The invention does not increase complexity of the spacer process. In the most simple way, it may merely change the thickness ratio of the spacer insulating layers of the current spacer scheme.