Single transistor driver for address lines in a phase change memory and switch (PCMS) array

The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line.

BACKGROUND OF THE INVENTION

The present disclosure relates generally to the fabrication of microelectronic memory. The microelectronic memory may be non-volatile, wherein the memory can retain stored information even when not powered.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.

FIG. 1shows a memory array100comprising, for illustration purposes, a 3×3 array of memory cells1101-1109, andFIG. 2shows a single memory cell110(analogous to any of memory cells1101-1109ofFIG. 1). Each memory cell (110and1101-1109) may include a phase change memory element120and an ovonic threshold switch130.

The memory array100may include column lines1501,1502, and1503(shown as element150inFIG. 2) and row lines1401,1402, and1403(shown as element140inFIG. 2) to select a particular memory cell of the array during a write or read operation. The column lines150,1501,1502, and1503and the row lines140,1401,1402, and1403may also be referred to as “address lines” since these lines may be used to address memory cells110,1101-1109during programming or reading. The column lines150,1501,1502, and1503may also be referred to as “bitlines”, and the row lines140,1401,1402, and1403may also be referred to as “wordlines”. Further, it is understood that the 3×3 array ofFIG. 1is merely exemplary and may be any appropriate size (i.e. any number of memory cells).

The phase change memory elements120may be connected to the column lines150,1501,1502, and1503and may be coupled to the row lines140,1401,1402, and1403through the ovonic threshold switch130. Each ovonic threshold switch130may be connected in series to each phase change memory element120and may be used to access each phase change memory element120during programming or reading of each phase change memory element120. When a particular memory cell (e.g., memory cell110ofFIG. 2) is selected, voltage potentials may be applied to its associated column line (e.g., element150ofFIG. 2) and row line (e.g., element140ofFIG. 2) to apply a voltage potential across the memory cell. It is understood that each ovonic threshold switch130could positioned between each phase change memory element120and the column lines150,1501,1502, and1503with each phase change memory element120coupled to the row lines140,1401,1402, and1403. It is also understood that more than one ovonic threshold switch130could be used within each memory cell110,1101-1109.

The phase change memory elements120operate based on the phase changing properties of a phase change material layer, which is interposed between an upper electrode and a lower electrode (with a resistive heating element between lower electrode and the phase change layer) (not shown). As a current is applied, the phase change material layer undergoes a phase change between the amorphous state and the crystalline state due to heat generated by the resistive heating element (by the Joule effect).

The specific resistance of the phase change material element120in the amorphous state is higher than the specific resistance of the phase change material element120in the crystalline state. Thus, in a read mode, sensing the current flowing through the phase change material element102determines whether the information stored has a logic value of “1” or “0”.

The phase change memory element120may be include a chalcogenide layer as a phase change element therein. The chalcogenide layer may comprise an element of the VI group of the period table (e.g. selenium (Se), tellurium (Te), etc.), usually combined with IV and V groups elements (e.g. germanium (Ge), arsenic (As), antimony (Sb), etc.).

As will be understood to those skilled in the art, the phase change memory cells (e.g.110,1101-1109) are accessed through wordline and bitline drivers generating the wordline and bitlines signals, respectively. Current phase memory arrays may include wordline drivers and bitline drivers, which each use two or more transistors to drive either an inhibit voltage or a selection voltage to the wordlines or bitlines (depending on which cross point phase change memory element is selected). However, as phase change memory arrays are scaled down for higher efficiency and cost reduction, it is necessary to shrink the drivers to keep the CMOS area under the memory structure small. With existing wordline and bitline driver designs having two or more transistors, it becomes difficult to scale transistor size down enough to keep the memory area and CMOS area at par with one another.

Embodiments of the present description relate to address line drivers and to the operation of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, at different timings, which may be achieved with the introduction of odd and even designations for the address lines (i.e. wordlines and bitlines). In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage. The adjacent inhibiting address lines may act as shielding lines to the selected address line, which may prevent misfiring due to floating conditions on some of the phase change memory cells, as will be understood to those skilled in the art.

With a reduction in the number of transistors needed for address line drivers down to a single transistor for each, according to the present disclosure, the CMOS area under the memory structure can be made smaller.

FIG. 3illustrates a wordline driver200having a two transistor configuration local wordline driver202n—m(where n is a number for a global wordline within a global wordline set for a memory array, which is illustrated as 32 global wordlines (i.e. 0-31), and m is a number for a local wordline per global wordline set in the memory array, which is illustrated as 32 local wordlines (i.e. 0-31), as known in the art. As illustrated, a local wordline NMOS (N-channel Metal Oxide Semiconductor) field effect transistor204n—mis utilized to drive a local wordline selection voltage WLSEL<31:0>and a local wordline PMOS (P-channel Metal Oxide Semiconductor) field effect transistor206n—mmay be utilized to drive a local wordline inhibit voltage Vinh—WL. As known in the art, a selection voltage is a voltage that is used for programming a memory cell, such as the phase change memory and switch memory cell110,1101-1109, as illustrated inFIGS. 1 and 2, and an inhibit voltage is a voltage that inhibits programming. The operation of the local wordline NMOS field effect transistors204n—mand a local wordline PMOS field effect transistors206n—min generating local wordlines LWLn—m, as illustrated, is well known in the art and will not be discussed herein. As will be understood to those skilled in the art, any appropriate number of global wordlines and local wordlines may be utilized in a memory array.

As further shown inFIG. 3, the wordline driver200may also include global wordline drivers212n, each comprising a global wordline NMOS field effect transistor214nand a global wordline PMOS field effect transistor216n(as well as bias NMOS field effect transistor218nand bypass NMOS field effect transistor222n). As will be understood to those skilled in the art, to select a specific wordline, both the global wordline NMOS field effect transistor214nand the local wordline NMOS field effect transistor204n—mdevice to select the specific wordline LWLn—mare turned on. The operation of the global wordline drivers212n, along an associated bias voltage Vbiasfor current limiting (current mirroring) and a bypass current mirroring voltage Vpass, in generating a global wordline GWLn, as illustrated, is well known in the art and will not be discussed herein.

In the wordline driver200ofFIG. 3, each local wordline LWLn—mneeds both a local wordline NMOS field effect transistor204n—mand a local wordline PMOS field effect transistor206n—m, which takes considerable space under a memory structure. As illustrated, each local wordline LWLn—mwould require 2.125 transistors (i.e. a local wordline NMOS field effect transistor204n—m, a local wordline PMOS field effect transistor206n—m, and 4/32 of the transistors of the global wordline driver212n.

FIG. 4illustrates a wordline driver300having a single transistor configuration to drive local wordlines LWLn—m, according to one embodiment of the present description. As illustrated, an inhibit voltage Vinh—WLor a selection voltage (either an odd wordline selection signal WLO—SEL<31:0>or an even wordline selection signal WLE—SEL<31:0>) may pass through a corresponding single field effect transistor304n—mat different timings. It is understood that although the single field effect transistors304n—mare illustrated as NMOS transistors, the single filed effect transistors304n—mmay also be PMOS transistors. It is further understood that any appropriate number of global wordlines and local wordlines may be utilized in a given memory array.

To correctly pass the inhibit voltage through the appropriate single field effect transistors304n—m, the global wordline is separated into even and odd global wordlines GWLn—eand GWLn—o, respectively, which are generated by a global wordline driver312n. Further, each global wordline driver312nmay include two transistor pairs (i.e. a first global wordline NMOS field effect transistor314npaired with a first global wordline PMOS field effect transistor316n, and a second global wordline NMOS field effect transistor324npaired with a second global wordline PMOS field effect transistor326n) to distinguish between an even selection and an odd selection for each local wordline LWLn—m, as will be understood to those skill in art by referencingFIG. 4. The global wordline drivers312nmay also include a bias NMOS field effect transistor318nand bypass NMOS field effect transistor322n; the operation of which within the global wordline drivers312will be understood to those skilled in the art. It is understood that the specific circuitry and transistor selection illustrated inFIG. 7is merely exemplary, and that any appropriate circuitry and transistor selection may be used to generate the even global bitlines GWLn—eand the odd global bitlines GWLn—o.

In the wordline driver300ofFIG. 4, each local wordline LWLn—mneeds only one local wordline field effect transistor304n—mas a driver. Thus, each local wordline LWLn—mwould only require 1.1875 transistors (i.e. a local wordline field effect transistor304n—mand 6/32 of the transistors of the global wordline driver312n.

In the case of an even wordline selection, all of the odd wordlines are inhibited by passing inhibit voltage Vinh—WLthrough the global wordline driver312nto trigger the odd global wordline GWLn—oand turning on all local field effect transistors304n—mthat the are connected to designated odd wordlines (i.e. connected to odd wordline selection signal WLO—SEL<31:0>). For the even wordlines, only the single decoded even wordline gets selected with the rest of the even wordlines kept floating (e.g. neither a selection voltage or an inhibit voltage applied).

Likewise, in the case of an odd wordline selection, all of the even wordlines are inhibited by passing inhibit voltage Vinh—WLthrough the global wordline driver312nto trigger the global even wordline GWLn—eand turning on all local field effect transistors304n—mthat the are connected to designated even wordlines (i.e. connected to even wordline selection signal WLE—SEL<31:0>). For the odd wordlines, only the single decoded odd wordline gets selected with the rest of the odd wordlines kept floating.

For example,FIG. 5illustrates a condition when an odd wordline is selected (labeled as 0) and the remainder of the odd wordlines (unselected) are floating (labeled as f1-f5). In this condition, all of the even wordlines are driven to an inhibited (or “deselected”) voltage (labeled as i1-i6). It is noted that the bitlines which run perpendicular to the wordlines inFIG. 5are simply designated as BL1-BL12and their condition is not designated for clarity, but they will be discussed and illustrated after the discussion regarding single transistor bitline drivers. In this scheme, the floating condition of the unselected wordlines does not affect the memory operation since their adjacent inhibited wordlines to the selected wordline is driven to inhibit voltage during wordline selection.

For bitline drivers according to the present description, a similar concept as described with regard to the wordline driver embodiment illustrated inFIG. 4can be utilized. Thus, bitline drivers may also be reduced from two or more transistors to a single transistor by introducing even and odd local bitline designations, and even and odd global bitlines.

FIG. 6illustrates a bitline driver400comprising a two transistor configuration to drive local bitlines LBLx—y, as known in the art. As illustrated, the local bitline drivers402x—y(where x is a number for a global bitline within a global bitline set for a memory array, which is illustrated as 64 global bitlines (i.e. 0-63), and y is a number for a local bitlines per global bitline set in the memory array, which is illustrated as 32 local bitlines (i.e. 0-31), include local bitline PMOS selection field effect transistors404x—yto drive a bitline selection voltage VBL and a local bitline PMOS inhibit field effect transistor406x—yto drive a local bitline inhibit voltage Vinh—BL. The operation of the local bitline drivers402x—y, along associated local bitline selection signals BLSEL<31:0>, the bitline selection voltage VBL, local bitline inhibit signals BLSEL—inh<31:0>, and the local bitline inhibit voltage Vinh—BL, in generating the local bitlines LBLx—y, as illustrated, is well known in the art and will not be discussed herein. It is understood that the any appropriate number of global bitlines and local bitlines may be in a memory array.

As further shown inFIG. 6, the bitline driver400may also include global bitline drivers412xcomprising a paired global wordline NMOS field effect transistors414xand a global wordline PMOS field effect transistors416x. The operation of the global bitline drivers412x, along the associated global bitline selections GBLSEL<63:0>, bitline selection voltage VBL, and global bitline inhibit voltage VPGBL, in generating global bitlines GBLx, as illustrated, is well known in the art and will not be discussed herein.

FIG. 7illustrates a bitline driver500having a single local bitline field effect transistors502x—yto drive local bitlines LBLx—yaccording to one embodiment of the present description. As illustrated, an inhibit voltage Vinh—BLor a selection voltage (either an odd bitline selection signal BLO—SEL<15:0>or an even wordline selection signal BLE—SEL<15:0>) may pass through a corresponding single field effect transistor502x—yat different timings. It is understood that although the local bitline field effect transistors502x—yare illustrated as PMOS field effect transistors, the local bitline field effect transistors502x—ymay also be NMOS field effect transistors. It is further understood that the any appropriate number of global bitlines and local bitlines may be utilized in a given memory array.

The local bitlines LBLx—ymay be designated as either “odd” or “even” in an alternating fashion based on whether they are coupled to a local bitline field effect transistors502x—ythat is coupled to an even local bitline selection signal BLE—SEL<15:0>or to an odd local bitline selection signal BLO—SEL<15:0>, respectively.

As further shown inFIG. 7, the bitline driver500may also include even global bitline drivers512x—ecomprising paired even global bitline NMOS field effect transistors514x—eand a even global bitline PMOS field effect transistors516x—e, and odd global bitline drivers512x—ocomprising paired odd global bitline NMOS field effect transistors514x—oand odd global bitline PMOS field effect transistors516x—o. The operation of the even and odd global bitline drivers512x—eand512x—o(respectively) along their associated even global bitline selection signals GBLE—SEL<63:0>and odd global bitline selection signals GBLO—SEL<63:0(respectively), bitline selection voltage VBL, and global bitline inhibit voltage Vinh—BL, in generating the even global bitlines GBLx—eand the odd global bitlines GBLx—o, as illustrated, is well known in the art and will not be discussed herein. It is understood that the specific circuitry and transistor selection illustrated inFIG. 7is merely exemplary, and that any appropriate circuitry and transistor selection may be used to generate the even global bitlines GBLx—eand the odd global bitlines GBLx—o.

In the case of even bitline selection, only one of the even field effect transistors (i.e. a local bitline field effect transistor502x—ycoupled to an even local bitline selection signal BLE—SEL<15:0>) is “on” (grounded) connecting to the selected even global bitline GBLx—e. Further, all of the odd bitline drivers (i.e. a local bitline field effect transistor502x—ycoupled to an odd local bitline selection signal BLO—SEL<15:0>) are “on” connecting to the odd global bitlines driven by an inhibit voltage (i.e., the global bitline inhibit voltage Vinh—BL). As a result, all the even bitlines other than the selected are floated, and all the odd bitlines are driven to the inhibit voltage.

FIG. 8shows inhibit and selection condition for both wordline and bitline side in the case of odd wordline and odd bitline selection, wherein the odd wordline selected is labeled as “0” and the remainder of the odd wordlines are floating (labeled as f1wl-f5wl), and the even wordlines are driven to an inhibit voltage (labeled as i1wl-i6wl), and wherein the odd bitline selected is labeled as “1” and the remainder of the odd bitlines are floating (labeled as f1bl-f5bl), and the even bitlines are properly driven to an inhibit voltage (labeled as i1bl-i6bl).

FIG. 9illustrates a flow diagram of process600of selecting an address line. As shown in block610, the address lines may be assigned alternating odd or even designations. One of the address line may be selected, as shown in block620. The address lines of the odd or even designation which is the same as the selected address line are allowed to float, as shown in block630. As shown in block640, the address lines of the odd or even designation which is different from the selected address lines are set to an inhibit voltage.

FIG. 10illustrates an example of a microelectronic system700utilizing the subject matter of the present description. The microelectronic system700may be any electronic device, including but not limited to portable devices, such as a portable computer, a mobile telephone, a digital camera, a digital music player, a web tablet, a personal digital assistant, a pager, an instant messaging device, or other devices, The microelectronic system700may be adapted to transmit and/or receive information wirelessly, such as through a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, and/or a cellular network.

The microelectronic system700may include a controller710, an input/output (I/O) device720(e.g. a keypad, display, and the like), a memory730, and a wireless interface740coupled to each other via a bus750. It is understood that the scope of the present invention is not limited to embodiments having any or all of these components.

The controller710may comprise, for example, one or more microprocessors, digital signal processors, application specific integrated circuits, microcontrollers, or the like. The memory730may be used to store messages transmitted to or by system700. The memory730may also optionally be used to store instructions that are executed by controller710during the operation of system700, and may be used to store user data. The memory730may be the provided by one or more different types of memory. For example, the memory730may comprise any type of random access memory, a volatile memory, a non-volatile memory such as a flash memory and/or a memory such as PCMS memory discussed herein, wherein the address drivers may comprise single transistors.

The I/O device720may be used by a user to generate a message. The system700may use the wireless interface740to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples of the wireless interface740may include an antenna or a wireless transceiver, although the scope of the present invention is not limited in this respect.

By referencing the microelectronic system700ofFIG. 10, one skilled in the art will understand that the microelectronic system700or a computer may include a computer program product stored on a computer readable memory or medium, wherein the computer program may be adapted to be executed within the microelectronic system700or on a computer to facilitate assigning address lines with alternating odd or even designations, selecting one address one, allowing address lines of the odd or even designation which is the same as the selected address line are allowed to float, and setting the address lines of the odd or even designation which is different from the selected address lines to an inhibit voltage, in a manner discussed herein.

Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.