USB chip and operation method thereof

A USB chip includes positive and negative data pins, first and second transceiver circuits, a switching circuit, and a control circuit. During a high-speed handshake stage, the control circuit controls the switching circuit to be in a second state to disconnect the positive and negative data pins from a first terminal impedance circuit and actuates the second transceiver circuit to transmit a second voltage signal via the positive and negative data pins alternately. During a high-speed transmission stage, the control circuit controls the switching circuit to be in a first state to connect the positive and negative data pins with the first terminal impedance circuit and actuates the first transceiver circuit to transmit a first voltage signal, which has a first voltage level lower than a voltage level of the second voltage signal, via the positive and negative data pins alternately.

CROSS-REFERENCE TO RELATED APPLICATION

This non-provisional application claims priority under 35 U.S.C. § 119(a) to Patent Application No. 111100849 filed in Taiwan, R.O.C. on Jan. 7, 2022, the entire contents of which are hereby incorporated by reference.

BACKGROUND

Technical Field

The instant disclosure relates to USB (universal serial bus) technology, especially a USB chip and an operation method thereof.

Related Art

A USB (universal serial bus) interface has advantages of hot plugging and plug-and-play. A USB interface may be provided as an interface for providing or receiving electricity. As technology progresses, USB versions continue to be updated. As of the USB 2.0 version, low-speed transmission (such as 1.5 Mbps transmission speed), full-speed transmission (such as 12 Mbps transmission speed), and high-speed transmission (such as 480 Mbps transmission speed) are all supported.

Usually, when a device that can support USB 2.0 and has a USB connector is connected to another device having a USB connector, speed identification is carried out in order to determine whether to adopt low-, full-, or high-speed transmission. The method for determining whether to adopt full- or high-speed transmission is handshake using a signal (described as a handshake signal hereinafter), and a voltage level of the handshake signal should conform to a specification. Because the circuit used to generate the handshake signal (described as a handshake circuit) may have some power loss, the voltage level of the handshake signal may not conform to the specification. For example, the power loss causes the voltage level of the handshake signal to be less than the regulated voltage. As a result, an operation voltage of the handshake circuit is usually increased to compensate for power consumption.

However, increasing the operation voltage leads to increased overall power consumption of the device having a USB connector, which is not power-saving. Furthermore, in order to increase the operation voltage, additional elements (such as a low-dropout regulator, LDO) may have to be designed, and such elements would occupy the space for circuit construction of the device having a USB connector.

SUMMARY

In view of this, the instant disclosure provides a USB (universal serial bus) chip and an operation method thereof. According to some exemplary embodiments of the instant disclosure, a voltage level of a handshake signal can conform to a regulated voltage without increased operation voltage. According to some exemplary embodiments, usable space for circuit design can be increased.

According to some exemplary embodiments of the instant disclosure, the USB chip includes a positive data pin, a negative data pin, a first transceiver circuit, a second transceiver circuit, a switching circuit, and a control circuit. The first transceiver circuit is configured to transmit a first voltage signal via the positive data pin and the negative data pin alternately when the first transceiver circuit is actuated. The second transceiver circuit is configured to transmit a second voltage signal via the positive data pin and the negative data pin alternately when the second transceiver circuit is actuated. A second voltage level of the second voltage signal is greater than a first voltage level of the first voltage signal. The switching circuit is configured to connect the positive data pin and the negative data pin with a first terminal impedance circuit in a first state and to disconnect the positive data pin and the negative data pin from the first terminal impedance circuit in a second state. The control circuit is configured to control the switching circuit to be in the second state during a high-speed handshake stage, actuate the second transceiver circuit when the switching circuit is controlled to be in the second state, control the switching circuit to be in the first state during a high-speed transmission stage, and actuate the first transceiver circuit when the switching circuit is controlled to be in the first state.

According to some exemplary embodiments of the instant disclosure, the USB chip includes a positive data pin, a negative data pin, a first transceiver circuit, a second transceiver circuit, a switching circuit, and a control circuit. An operation method of the USB chip includes: controlling, through the control circuit, the switching circuit to be in a second state during a high-speed handshake stage; actuating the second transceiver circuit when the switching circuit is controlled to be in the second state; controlling the switching circuit to be in a first state through the control circuit during a high-speed transmission stage; and actuating the first transceiver circuit when the switching circuit is controlled to be in the first state. The switching circuit connects the positive data pin and the negative data pin with a first terminal impedance circuit in the first state and disconnects the positive data pin and the negative data pin from the first terminal impedance circuit in the second state. When the first transceiver circuit is actuated, the first transceiver circuit transmits a first voltage signal via the positive data pin and the negative data pin alternately; when the second transceiver circuit is actuated, the second transceiver circuit transmits a second voltage signal via the positive data pin and the negative data pin alternately, wherein a second voltage level of the second voltage signal is greater than a first voltage level of the first voltage signal.

To summarize the above, according to some exemplary embodiments of the instant disclosure, through the two transceiver circuits respectively transmitting signals having different voltage levels, the voltage level of the handshake signal during the high-speed handshake stage can conform to a regulated voltage without increased operation voltage, and the voltage level of a signal during high-speed transmission stage (described as a post-handshake signal hereinafter) can also conform to a regulated voltage without increased operation voltage. In some exemplary embodiments, because additional elements (such as a low-dropout regulator) for increasing the operation voltage are not necessarily required, usable space for circuit design can be increased. For example, according to some exemplary embodiments of this instant disclosure, not only the overall power consumption of the USB chip can be reduced, but also the usable space for circuit design can be increased.

DETAILED DESCRIPTION

The terms such as “first” and “second” are used to differentiate one element from another and not meant for sequencing the elements or limiting the differences among the elements. As a result, the abovementioned terms cannot be used to limit the scope of the instant disclosure. Besides, the term “connect” may refer to the act of physically or electrically connecting two or more elements with each other in a direct manner, or the term “connect” may refer to the act of physically or electrically connecting two or more elements with each other in an indirect manner. For example, if a first device is connected to a second device, the first device may be directly and electrically connected to the second device, or the first device may be indirectly and electrically connected to the second device via some other device(s) or through other connection manners.

FIG.1illustrates a block application diagram of a USB (universal serial bus) chip10connected to a USB sub device100according to some exemplary embodiments of the instant disclosure. Please refer toFIG.1. The USB chip10comprises a positive data pin D+_A, a negative data pin D−_A, a first transceiver circuit21, a second transceiver circuit23, a switching circuit30, and a control circuit40. The positive data pin D+_A and the negative data pin D−_A are both connected to the first transceiver circuit21and the second transceiver circuit23. That is, in this embodiment, the positive data pin D+_A is connected to the first transceiver circuit21and the second transceiver circuit23, and the negative data pin D−_A is connected to the first transceiver circuit21and the second transceiver circuit23. The switching circuit30is connected to the positive data pin D+_A, the negative data pin D−_A, and a first terminal impedance circuit50. The control circuit40is connected to the first transceiver circuit21, the second transceiver circuit23, and the switching circuit30.

In some exemplary embodiments of the instant closure, the positive data pin D+_A and the negative data pin D−_A may be implemented using a USB connector (described as a connector60hereinafter). In some exemplary embodiments, the USB chip10may be implemented by using a USB main device and can be connected to a USB sub device100. The USB main device may be an electronic device having a USB female connector (or a type-C female connector) such as a computer, a mobile device, a digital television (such as a set-top box), or a USB hub. The USB sub device100may be an electronic device having a USB male connector (or a type-C male connector) such as a computer, a mobile device, photographic equipment, a digital television (such as a set-top box), or a gaming console.

For illustrative purposes, the USB main device will be described as the USB chip10hereinafter.

A version of the connector60of the USB chip10corresponds to a version of a connector160of the USB sub device100, and the connector60is connected to the connector160. For example, according to the definition of the version of the USB shown inFIG.1(USB 2.0 for example), the positive data pin D+_A of the connector60is connected to a positive data pin D+_B of the connector160, the negative data pin D−_A of the connector60is connected to a negative data pin D−_B of the connector160, a voltage conversion pin VBus_A of the connector60is connected to a voltage conversion pin VBus_B of the connector160, and a ground pin GND_A of the connector60is connected to a ground pin GND_B of the connector160. The voltage conversion pin VBus_A is configured to supply power from the USB chip10to the USB sub device100. For example, the voltage conversion pin VBus_A supplies a 5V voltage from a power management circuit70of the USB chip10to a power management circuit170of the USB sub device100.

The power management circuit70of the USB chip10has a power source to supply an operation voltage to the elements of the USB chip10(such as the first transceiver circuit21, the second transceiver circuit23, the switching circuit30, and the control circuit40). Similarly, the power management circuit170of the USB sub device100is configured to supply electricity to the elements of the USB sub device100so as to allow the operation of the elements of the USB sub device100. In some exemplary embodiments, the USB sub device100may acquire power from the USB chip10or other sources. For example, the USB sub device100may be designed to have a built-in power source or connected to an external power source via a power adaptor. The ground pin GND_A is configured to provide the power management circuit170of the USB sub device100with a ground potential from the power management circuit70of the USB chip10, thereby allowing the USB sub device100to have a ground potential. The ground pin GND_A acquires the ground potential from a ground of the power management circuit70. The ground of the power management circuit70is configured to provide the USB chip10with a ground potential.

In some exemplary embodiments of the instant disclosure, according to a supported USB version of the USB chip10, the USB chip10may support multiple transmission modes to support various transmission speeds. For example, if the USB chip10supports USB 2.0, the USB chip10can support a low-speed transmission mode, a full-speed transmission mode, and a high-speed transmission mode so as to support a low-speed transmission, a full-speed transmission, and a high-speed transmission. When the USB chip10is connected to the USB sub device100, the USB chip10determines which transmission modes are supported by the USB chip10and the USB sub device100respectively so as to conduct the transmission at a transmission speed supported by both the USB chip10and the USB sub device100.

For example, as shown inFIG.1, the USB chip10has a low- and full-speed transceiver module90and a high-speed transceiver module20. The USB sub device100has a low- and full-speed transceiver module190and a high-speed transceiver module120. The low- and full-speed transceiver module90provides the USB chip10with the low-speed transmission and the full-speed transmission, and the low- and full-speed transceiver module190provides the USB sub device100with the low-speed transmission and the full-speed transmission. The high-speed transceiver module20provides the USB chip10with the high-speed transmission, and the high-speed transceiver module120provides the USB sub device100with the high-speed transmission. In this embodiment, the high-speed transceiver module20may be implemented by using the first transceiver circuit21and the second transceiver circuit23.

In some exemplary embodiments of the instant disclosure, when the USB chip10detects a high voltage level at the negative data pin D−_A, the USB chip10determines that the USB sub device100is in the low-speed transmission mode, and thus the USB chip10and the USB sub device100conduct the low-speed transmission. When the USB chip10detects a high voltage level at the positive data pin D+_A, a handshake process is then conducted (illustrated later in the instant disclosure). Through the handshake process, whether the USB chip10and the USB sub device100can support the high-speed transmission mode can be determined. If both the USB chip10and the USB sub device100can support the high-speed transmission mode, the USB chip10and the USB sub device100conduct the high-speed transmission. If either or both the USB chip10and the USB sub device100cannot support the high-speed transmission mode, the USB chip10and the USB sub device100conduct the full-speed transmission.

To be specific, in this embodiment, when a pull-up resistor Rpuof the USB sub device100is connected to the negative data pin D−_B of the USB sub device100, the USB sub device100is in the low-speed transmission mode, and voltages of the negative data pin D−_B and the negative data pin D−_A are pulled up to the high voltage level (such as 3.3 V). When the pull-up resistor Rpuof the USB sub device100is connected to the positive data pin D+_B of the USB sub device100(as shown inFIG.1), the voltages of the positive data pin D+_B and the positive data pin D+_A are pulled up to the high voltage level (such as 3.3 V), meaning that the USB sub device100is not in the low-speed transmission mode. As a result, in this situation, the USB chip10has to further perform the handshake process to determine whether the transmission mode between the USB chip10and the USB sub device100is the full-speed transmission mode or the high-speed transmission mode.

FIG.2illustrates a flowchart of an operation method of the USB chip10according to some exemplary embodiment of the instant disclosure. In some exemplary embodiments, the operation method is adapted to be executed by the control circuit40. First, during a high-speed handshake stage of the handshake process, the control circuit40controls the switching circuit30to be in a second state (step S201). When the switching circuit30is controlled to be in the second state, the control circuit40actuates the second transceiver circuit23(step S203) to start the operation of the second transceiver circuit23. During a high-speed transmission stage of the handshake process, the control circuit40controls the switching circuit30to be in a first state (step S205). When the switching circuit30is controlled to be in the first state, the control circuit actuates the first transceiver circuit21(step S207) to start the operation of the first transceiver circuit21. In some exemplary embodiments, entering the high-speed transmission stage of the handshake process indicates that both the USB chip10and the USB sub device100can support the high-speed transmission mode, and, after the handshake process between the USB chip10and the USB sub device100is successful, the high-speed transmission may be initiated, and the handshake process will end.

Please refer toFIG.1. The switching circuit30connects the positive data pin D+_A and the negative data pin D−_A with a first terminal impedance circuit50in a first state. In other words, in this embodiment, in the first state, the switching circuit30connects the positive data pin D+_A with the first terminal impedance circuit50, and the switching circuit30connects the negative data pin D−_A with the first terminal impedance circuit50. The first transceiver circuit21transmits a first voltage signal (i.e., the post-handshake signal) via the positive data pin D+_A and the negative data pin D−_A alternately when the first transceiver circuit21is actuated. The switching circuit30disconnects the positive data pin D+_A and the negative data pin D−_A from the first terminal impedance circuit50in a second state. In other words, in this embodiment, in the second state, the switching circuit30disconnects the positive data pin D+_A from the first terminal impedance circuit50, and the switching circuit30disconnects the negative data pin D−_A from the first terminal impedance circuit50. The second transceiver circuit23transmits a second voltage signal (i.e., the handshake signal) via the positive data pin D+_A and the negative data pin D−_A alternately when the second transceiver circuit23is actuated.

Compared with the first voltage signal, which is generated on the condition that both the connection between the first terminal impedance circuit50and the positive data pin D+_A and the connection between the first terminal impedance circuit50and the negative data pin D−_A are established, the second voltage signal is generated on the condition that the first terminal impedance circuit50is disconnected from the positive data pin D+_A, and the first terminal impedance circuit50is disconnected from the negative data pin D−_A. Besides, compared with a headroom of the second transceiver circuit23, the headroom of the first transceiver circuit21is less sufficient. As a result, a second voltage level of the second voltage signal is greater than a first voltage level of the first voltage signal. Through the two transceiver circuits (i.e., the first transceiver circuit21and the second transceiver circuit23) transmitting signals having different voltage levels, the voltage level of the handshake signal in the high-speed handshake stage can conform to a regulated voltage without increased operation voltage, and the voltage level of the post-handshake signal in the high-speed transmission stage can also conform to a regulated voltage. The regulated voltage of the handshake signal is 0.8 V, and the regulated voltage of the post-handshake signal is 0.4 V.

In some exemplary embodiments, when the switching circuit30is controlled to be in the first state, the control circuit40also disables the second transceiver circuit23; when the switching circuit30is controlled to be in the second state, the control circuit40also disables the first transceiver circuit21. In other words, in these embodiments, only the second transceiver circuit23is actuated and in operation during the high-speed handshake stage, and only the first transceiver circuit21is actuated and in operation during the high-speed transmission stage. As a result, the first transceiver circuit21and the second transceiver circuit23do not interfere with each other, and the first voltage signal and the second voltage signal do not interfere with each other.

Please refer toFIG.1. In some exemplary embodiments, the switching circuit30comprises a first switch31and a second switch33. The first switch31and the second switch33may be implemented by using electrical switches (such as transistors). In some exemplary embodiments, the first terminal impedance circuit50comprises a first terminal impedance R1and a second terminal impedance R2. The first terminal impedance R1and the second terminal impedance R2may be formed by passive elements (such as resistors, capacitors, and inductors). Preferably, in some embodiments, the first terminal impedance R1and the second terminal impedance R2are both implemented by using resistors. For example, the first terminal impedance R1and the second terminal impedance R2are both 45Ω resistors. The first switch31is connected between the positive data pin D+_A and the first terminal impedance R1, and the second switch33is connected between the negative data pin D−_A and the second terminal impedance R2. In some exemplary embodiments, in the first state, the first switch31connects the positive data pin D+_A with the first terminal impedance R1, and the second switch33connects the negative data pin D−_A with the second terminal impedance R2. In the second state, the first switch31disconnects the positive data pin D+_A from the first terminal impedance R1, and the second switch33disconnects the negative data pin D−_A from the second terminal impedance R2.

Please refer toFIG.1. In some exemplary embodiments of the instant disclosure, the control circuit40comprises a logic controller41. The logic controller41may be a programmable logic controller (PLC). The switching between states of the switching circuit30is controlled by the logic controller41, and the first transceiver circuit21and the second transceiver circuit23are actuated by the logic controller41. For example, during the high-speed handshake stage, the logic controller41transmits a high-level switching signal (such as a logic level “1”). The switching circuit30is switched from the first state to the second state in response to the high-level switching signal, and the logic controller41transmits an actuation signal to the second transceiver circuit23to actuate the second transceiver circuit23. During the high-speed transmission stage, the logic controller41transmits a low-level switching signal (such as a logic level “0”). The switching circuit30is switched from the second state to the first state in response to the low-level switching signal, and the logic controller41transmits an actuation signal to the first transceiver circuit21to actuate the first transceiver circuit21.

FIG.3illustrates signal sequence diagrams of a handshake process according to some exemplary embodiment of the instant disclosure. Please refer toFIG.3. First, when the USB chip10is connected to the USB sub device100, and the voltages of the positive data pin D+_B and the positive data pin D+_A are pulled up to the high voltage level (such as 3.3 V, as shown in a time period T1inFIG.3), the USB chip10initiates the handshake process. In this embodiment, because the positive data pin D+_A is connected to the positive data pin D+_B, and the negative data pin D−_A is connected to the negative data pin D−_B, an identical voltage level exists at the positive data pin D+_A and the positive data pin D+_B, and another identical voltage level exists at the negative data pin D−_A and the negative data pin D−_B. For illustrative purposes,FIG.3only shows the signal sequences of the signals on the positive data pin D+_A and the negative data pin D−_A.

Next, the control circuit40of the USB chip10generates a reset signal and resets the positive data pin D+_A and the negative data pin D−_A to the low voltage level (such as 0 V or substantial 0 V, as shown in a time period T2shown inFIG.3) in response to the reset signal. In some exemplary embodiments, a duration when the positive data pin D+_A and the negative data pin D−_A are reset to the low voltage level (i.e., the time period T2) is not less than 10 ms. In some exemplary embodiments, as shown inFIG.1, the control circuit40comprises a processor43. The processor43is configured to generate the reset signal when the handshake process is initiated. The processor43may be a central processing unit. In some exemplary embodiments, when the positive data pin D+_A and the negative data pin D−_A are reset to the low voltage level (i.e., during the time period T2), the switching circuit30is in the first state. In other words, in these embodiments, during the time period T2, the positive data pin D+_A is connected to the first terminal impedance circuit50, and the negative data pin D−_A is connected to the first terminal impedance circuit50.

After the positive data pin D+_A and the negative data pin D−_A are reset to the low voltage level, if the USB sub device100can support the high-speed transmission mode, the USB sub device100inputs a current (such as 17.78 mA) into the negative data pin D−_B and the negative data pin D−_A via an internal current source (not shown in the figures). Because the pull-up resistor Rpuis not disconnected from the positive data pin D+_B, the current results in a third voltage signal at the negative data pin D−_A due to the first terminal impedance circuit50. In other words, the third voltage signal is generated by the USB sub device100, where the duration of the third voltage signal is 1-7 ms (as shown in a time period T3inFIG.3), and the voltage level of the third voltage signal is 0.8 V. In some exemplary embodiments, the third voltage signal is implemented by generating a chirped state-K signal of the USB sub device100(described as a first chirped state-K signal hereinafter). The first chirped state-K signal refers to the state where the positive data pin D+_A and the negative data pin D−_A are in a state K, or the positive data pin D+_B and the negative data pin D−_B are in the state K. The state K refers to when the positive data pin D+_A is at the low voltage level (such as 0 V or substantial 0 V) and the negative data pin D−_A is at the high voltage level (such as greater than 0 V), or when the positive data pin D+_B is at the low voltage level and the negative data pin D−_B is at the high voltage level. In some exemplary embodiments, when the third voltage signal is generated (i.e., during the time period T3), the switching circuit30is in the first state.

In some exemplary embodiments, after the positive data pin D+_A and the negative data pin D−_A are reset to the low voltage level (i.e., during the time period T2), if the USB sub device100cannot support the high-speed transmission mode, the USB sub device100does not generate the third voltage signal. If the USB chip10does not detect the third voltage signal, the USB chip10will continue operations related to the time period T2until the handshake process ends, and after the handshake process ends, the USB chip10and the USB sub device100conduct the full-speed transmission. Similarly, in some exemplary embodiments, if the USB chip10cannot support the high-speed transmission mode, the USB chip10ignores the third voltage signal from the USB sub device100and continues operations related to the time period T2until the handshake process ends, and after the handshake process ends, the USB chip10and the USB sub device100conduct the full-speed transmission.

In some exemplary embodiments, as shown inFIG.3, during the handshake process (such as after the time period T3), the control circuit40generates a switching stage signal HSTXVM so as to determine whether the control circuit is in the high-speed handshake stage or the high-speed transmission stage.

In some exemplary embodiments, when the third voltage signal from the USB sub device100exists at the negative data pin D−_A, the control circuit40generates a switching stage signal indicating the high-speed handshake stage and operates in the high-speed handshake stage. For example, as shown inFIG.1andFIG.3, when the processor43detects the third voltage signal and the USB chip10can support the high-speed transmission mode, the control circuit40generates the switching stage signal HSTXVM indicating the high-speed handshake stage T4to the logic controller41. The logic controller41then operates in the high-speed handshake stage T4in response to the switching stage signal HSTXVM indicating the high-speed handshake stage T4. The switching stage signal HSTXVM may be a high level (such as a logic level “1”) to indicate the high-speed handshake stage T4.

In some exemplary embodiments, on the condition that the USB chip10can support the high-speed transmission, when the control circuit40detects that a duration time of the third voltage signal (i.e., time period T3) is less than a time threshold, the control circuit40generates the switching stage signal HSTXVM indicating the high-speed handshake stage T4. The time threshold may be 100 μs or conform to a USB 2.0 specification. The time threshold may be pre-saved in the processor43or inputted into the processor43.

In some exemplary embodiments, as shown inFIG.3, after entering the high-speed handshake stage T4, the second transceiver circuit23transmits a second voltage signal via the positive data pin D+_A and the negative data pin D−_A alternately. In some exemplary embodiments, the second voltage level of the second voltage signal is 0.8 V. In some exemplary embodiments, the second voltage signal transmitted via the negative data pin D−_A is implemented by generating a chirped state-K signal of the second transceiver circuit23(described as a second chirped state-K signal hereinafter), and the second voltage signal transmitted via the positive data pin D+_A is implemented by generating a chirped state-J signal of the second transceiver circuit23(described as a second chirped state-J signal hereinafter). In other words, in these embodiments, during the high-speed handshake stage T4, the second transceiver circuit23transmits a signal sequence formed by alternating between the second chirped state-J signal and the second chirped state-K signal. For example, the signal sequence may be “the second chirped state-J signal, the second chirped state-K signal, the second chirped state-J signal, the second chirped state-K signal, and so on.” The second chirped state-K signal of the second transceiver circuit23is similar to the first chirped state-K signal of the USB sub device100and thus is not repeatedly described here. The second chirped state-J signal refers to the state where the positive data pin D+_A and the negative data pin D−_A are in a state J, or when the positive data pin D+_B and the negative data pin D−_B are in the state J. The state J refers to when the positive data pin D+_A is at the high voltage level (such as greater than 0 V) and the negative data pin D−_A is at the low voltage level (such as 0 V or substantial 0 V), or when the positive data pin D+_B is at the high voltage level and the negative data pin D−_B is at the low voltage level.

In some exemplary embodiments, during the high-speed handshake stage, when a number of times of the second voltage signal being transmitted via the positive data pin D+_A is not less than a threshold of the number of times, and the number of times of the second voltage signal being transmitted via the negative data pin D−_A is not less than the threshold of the number of times, the control circuit40generates the switching stage signal HSTXVM indicating the high-speed transmission stage T5and operates in the high-speed transmission stage T5. Here, as an example for description, the signal transmitted at the negative data pin D−_A is the second chirped state-K signal, and the signal transmitted at the positive data pin D+_A is the second chirped state-J signal. As shown inFIG.1andFIG.3, during the high-speed handshake stage T4, the processor43accumulates the number of times of the second chirped state-J signal being transmitted and the number of times of the second chirped state-K signal being transmitted. For example, if the number of times of the second chirped state-J signal being transmitted is less than the threshold of the number of times, and the number of times of the second chirped state-K signal being transmitted is less than the threshold of the number of times, the processor43generates a switching stage signal HSTXVM indicating the high-speed transmission stage T5to the logic controller41. The logic controller41then operates in the high-speed transmission stage T5in response to the switching stage signal HSTXVM indicating the high-speed transmission stage T5. The switching stage signal HSTXVM may be a low level (such as a logic level “0”) to indicate the high-speed transmission stage T5. In some exemplary embodiments, the threshold of the number of times may be 3 or conform to a USB 2.0 specification. The threshold of the number of times may be pre-saved in the processor43or inputted into the processor43.

In some exemplary embodiments, only on the condition that an accumulated number of times of the second chirped state-J signal being transmitted (described as a first number of times hereinafter) and an accumulated number of times of the second chirped state-K signal being transmitted (described as a second number of times hereinafter) are identical (i.e., when the first number of times is identical to the second number of times), the processor43compares the first number of times or the second number of times with the threshold of the number of times to determine whether both the first number of times and the second number of times are not less than the threshold of the number of times. For example, if the threshold of the number of times is 8, then the processor43determines whether one of the first number of times and the second number of times is not less than 8 or both the first number of times and the second number of times are not less than 8. In some exemplary embodiments, the processor43may compare the summation of the first number of times and the second number of times with the threshold of the number of times to determine whether the summation of the first number of times and the second number of times is not less than the threshold of the number of times. For example, if the threshold of the number of times is 8, the processor43first doubles the threshold of the number of times as a threshold of the number of times for comparison and then determines whether the summation of the first number of times and the second number of times is not less than the threshold of the number of times for comparison (i.e., whether the summation of the first number of times and the second number of times is not less than 16).

In some exemplary embodiments, as shown inFIG.3, after entering the high-speed transmission stage T5, the first transceiver circuit21transmits a first voltage signal via the positive data pin D+_A and the negative data pin D−_A alternately. In some exemplary embodiments, the first voltage level of the first voltage signal is 0.4 V. In some exemplary embodiments, the first voltage signal transmitted via the negative data pin D−_A is implemented by generating a chirped state-K signal of the first transceiver circuit21(described as a third chirped state-K signal hereinafter), and the first voltage signal transmitted via the positive data pin D+_A is implemented by generating a chirped state-J signal of the first transceiver circuit21(described as a third chirped state-J signal hereinafter). In other words, in these embodiments, during the high-speed transmission stage T5, the first transceiver circuit21transmits a signal sequence formed by alternating between the third chirped state-J signal and the third chirped state-K signal. For example, the sequence may be “the third chirped state-J signal, the third chirped state-K signal, the third chirped state-J signal, the third chirped state-K signal, and so on.” The difference between the third chirped state-K signal of the first transceiver circuit21and the second chirped state-K signal of the second transceiver circuit23is that, the voltage level of the third chirped state-K signal of the first transceiver circuit21is 0.4 V, while the voltage level of the second chirped state-K signal of the second transceiver circuit23is 0.8 V. The difference between the third chirped state-J signal of the first transceiver circuit21and the second chirped state-J signal of the second transceiver circuit23is that, the voltage level of the third chirped state-J signal of the first transceiver circuit21is 0.4 V, while the voltage level of the second chirped state-J signal of the second transceiver circuit23is 0.8 V.

In some exemplary embodiments, as shown inFIG.1, the USB chip10further comprises a detection circuit80. The detection circuit80is connected to the control circuit40, the positive data pin D+_A, and the negative date pin D−_A. The detection circuit80is configured to detect the voltage level at the positive data pin D+_A and the voltage level at the negative data pin D−_A. As shown inFIG.3, after the positive data pin D+_A and the negative data pin D−_A are reset to the low voltage level (i.e., during the time period T2), when the voltage level at the positive data pin D+_A and the voltage level at the negative data pin D−_A are greater than a voltage threshold, the detection circuit80generates a detection signal NSQ_HST having a high level (such as a logic level “1”); when the voltage level at the positive data pin D+_A and the voltage level at the negative data pin D−_A are not greater than the voltage threshold, the detection circuit80generates a detection signal NSQ_HST having a low level (such as a logic level “0”). Based on the level of the detection signal NSQ_HST, the control circuit40can determine in which stage (time period) of the handshake process the control circuit40is, which stage (time period) of the handshake process the control circuit40is entering, or whether the USB chip10is disconnected from the USB sub device100. In some exemplary embodiments, the voltage threshold may be 0.6 V. Preferably, in some embodiments, the voltage threshold may be 0.585 V.

For example, as shown inFIG.3, during the high-speed handshake stage T4, the detection circuit80detects the second voltage level of the second voltage signal at the positive data pin D+_A and the second voltage level of the second voltage signal at the negative data pin D−_A. When the second voltage level is not greater than the voltage threshold, the detection circuit80generates a detection signal NSQ_HST having a low level to indicate that the USB sub device100can support the high-speed transmission mode and that the handshake process is successful, and thus the USB chip10can enter the high-speed transmission stage T5. The controller circuit40then generates a switching stage signal HSTXVM indicating the high-speed transmission stage T5and operates in the high-speed transmission stage T5in response to the detection signal NSQ_HST having a low level. For example, the processor43generates a switching stage signal HSTXVM indicating the high-speed transmission stage T5in response to the detection signal NSQ_HST having a low level, so that the logic controller41operates in the high-speed transmission stage T5.

It is understood that, the USB 2.0 specification only specified that, after 3 sets of sequences formed by the chirped state-J signal and the chirped state-K signal appear (i.e., after both the chirped state-J signal and the chirped state-K signal appear three times) during the high-speed handshake stage T4, the control circuit40should enter the high-speed transmission stage T5within 500 μs. As a result, on the condition that the specification is conformed to, beside by using the processor43to determine whether the number of times of the second voltage signal being transmitted via the positive data pin D+_A and the number of times of the second voltage signal being transmitted via the negative data pin D−_A are not less than the threshold of the number of times, whether the control circuit40enters the high-speed transmission stage T5can also be determined by using the detection circuit80to detect the second voltage level of the second voltage signal.

In some exemplary embodiments, during the high-speed handshake stage T4, when the control circuit40is about to enter the high-speed transmission stage T5, the second voltage level of the second voltage signal at the positive data pin D+_A and the second voltage level of the second voltage signal at the negative data pin D−_A are pulled down to be not greater than the voltage threshold by the second terminal impedance circuit150. Specifically, in these embodiments, as shown inFIG.1, when the USB sub device100can support the high-speed transmission mode and the handshake process was successful, the USB sub device100disconnects the pull-up resistor Rpufrom the positive data pin D+_A, and the second terminal impedance circuit150of the USB sub device100is connected to the positive data pin D+_A of the USB chip10via the positive data pin D+_B, and the second terminal impedance circuit150of the USB sub device100is connected to the negative data pin D−_A of the USB chip10via the negative data pin D−_B. As a result, the second voltage level of the second voltage signal at the positive data pin D+_A and the second voltage level of the second voltage signal at the negative data pin D−_A are pulled down to be not greater than the voltage threshold by the second terminal impedance circuit150. For example, the second voltage level is pulled down from 0.8 V to 0.5 V and thus not greater than the voltage threshold.

In some exemplary embodiments, as shown inFIG.1, similar to the first terminal impedance circuit50, the second terminal impedance circuit150comprises a third terminal impedance R3and a fourth terminal impedance R4, where the third terminal impedance R3is connected to the positive data pin D+_B, and the fourth terminal impedance R4is connected to the negative data pin D−_B. The third terminal impedance R3and the fourth terminal impedance R4may be formed by passive elements (such as resistors, capacitors, inductors). Preferably, in some embodiments, the third terminal impedance R3and the fourth terminal impedance R4are both implemented by using resistors. For example, the third terminal impedance R3and the fourth terminal impedance R4are both 45Ω resistors. In some exemplary embodiments, the first terminal impedance R1, the second terminal impedance R2, the third terminal impedance R3, and the fourth terminal impedance R4are all implemented by using resistors having identical resistances.

FIG.4illustrates a schematic application diagram of the second transceiver circuit23according to some exemplary embodiments of the instant disclosure. For illustrative purposes,FIG.4only shows the positive data pin D+_A and circuits related thereto (such as the first switch31and the first terminal impedance R1) as well as the positive data pin D+_B and circuits related thereto (such as the third terminal impedance R3). According toFIG.4, during the high-speed handshake stage T4, when the control circuit40is about to enter the high-speed transmission stage T5, the second transceiver circuit23is connected to the third terminal impedance R3, and thus the second voltage level of the second voltage signal transmitted via the positive data pin D+_A of the second transceiver circuit23is pulled down by the third terminal impedance R3to be not greater than the voltage threshold.

FIG.5illustrates a schematic application diagram of the first transceiver circuit21according to some exemplary embodiments of the instant disclosure. For illustrative purposes,FIG.5only shows the positive data pin D+_A and circuits related thereto (such as the first switch31and the first terminal impedance R1) as well as the positive data pin D+_B and circuits related thereto (such as the third terminal impedance R3). In some exemplary embodiments, the first transceiver circuit21is a current-driven transceiver circuit. In order to keep the instant disclosure brief, the description here focuses on the first voltage signal at the positive data pin D+_A. As shown inFIG.5, the first transceiver circuit21has a current source I1and is driven by the current source I1. The current value of the current source I1may be 17.78 mA. During the high-speed transmission stage T5, the second terminal impedance circuit150is shunted with the first terminal impedance circuit50(in other words, in this embodiment, the third terminal impedance R3is shunted with the first terminal impedance R1). Assuming that the third terminal impedance R3and the first terminal impedance R1are both 45Ω resistors, during the high-speed transmission stage T5, the first transceiver circuit21transmits the first voltage signal having the first voltage level of 0.4 V based on the current source I1, the first terminal impedance R1, and the third terminal impedance R3. As a result, the first voltage level can conform to the regulated voltage related to the positive data pin D+_A and the negative data pin D−_A during the high-speed transmission stage T5according to the USB 2.0 specification. In some exemplary embodiments, the current source I1may be implemented by using internal circuitry.

Please refer back toFIG.4. In some exemplary embodiments, the second transceiver circuit23is a voltage-driven transceiver circuit. In order to keep the instant disclosure brief, the description here focuses on the second voltage signal at the positive data pin D+_A. Because of some manufacturing factors, a voltage value of an operation voltage VDDLis limited. For example, the voltage value of the operation voltage VDDLmay be limited at 0.8 V. The regulated voltage related to the positive data pin D+_A and the negative data pin D−_A during the high-speed transmission stage T5according to the USB 2.0 specification is 0.8 V. Because some circuit designs may consume extra power and thus lower the operation voltage, in order to allow the second voltage level to conform to the specification without increased operation voltage VDDL, the second transceiver circuit23may be designed to generate zero or close-to-zero voltage drop, so that the second voltage level of the second voltage signal of the second transceiver circuit23can conform to the regulated voltage. For example, compared with current-driven transceiver circuits, voltage-driven transceiver circuits are less likely to generate voltage drops.

As shown inFIG.4, the second transceiver circuit23is driven by the operation voltage VDDL. In some exemplary embodiments, the second transceiver circuit23may be formed by an inverter and a transistor adapted to assist the inverter (described as an auxiliary transistor hereinafter). Because the inverter and the auxiliary transistor are able to generate zero or close-to-zero voltage drop, the second transceiver circuit23can transmit the operation voltage VDDLas the second voltage signal to the positive data pin D+_A (because during the high-speed handshake stage T4, the pull-up resistor Rpuis not disconnected from the positive data pin D+_B, and the first terminal impedance R1is disconnected from the positive data pin D+_A). As a result, the second voltage level can conform to the regulated voltage related to the positive data pin D+_A and the negative data pin D−_A during the high-speed handshake stage T4according to the USB 2.0 specification.

FIG.6illustrates a schematic diagram of the USB chip10according to some exemplary embodiments of the instant disclosure. Please refer toFIG.6. In some exemplary embodiments, as shown inFIG.1, the first terminal impedance circuit50is inside the USB chip10. In some other exemplary embodiments, as shown inFIG.6, the first terminal impedance circuit50is outside the USB chip10, and the USB chip10further comprises a connection end200so as to be connected to the first terminal impedance circuit50. In other words, in these embodiments, the connection end200and the connector60are both I/O ports of the USB chip10.

To summarize the above, according to some exemplary embodiments, through the two transceiver circuits transmitting signals having different voltage levels, the voltage level can conform to the regulated voltage without increased operation voltage during the high-speed handshake stage and the high-speed transmission stage. In some exemplary embodiments, because additional elements (such as an LDO) for increasing the operation voltage are not necessarily required, usable space for circuit design can be increased. For example, according to some exemplary embodiments of this instant disclosure, not only the overall power consumption of the USB chip can be reduced, but also the usable space for circuit design can be increased.