SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of insulating layers and a plurality of conductive layers are alternately stacked above a substrate, a pillar that penetrates the stacked body while extending in a stacking direction of the stacked body, and a semiconductor layer, a first insulating layer, a charge accumulation layer, and a second insulating layer, which are stacked on a side surface of the pillar in order from the pillar, wherein the semiconductor layer has an average grain size that is larger on a side nearer to the pillar and is smaller on a side nearer to the first insulating layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority front Japanese Patent Application No. 2018-158694, filed on Aug. 27, 2018; the entire content of which are incorporated herein by reference.

FIELD

An embodiment of the present invention relates generally to a semiconductor memory device.

BACKGROUND

In a three-dimensional nonvolatile memory, there are pillars extending in the height direction, and a plurality of memory cells are arrayed in the height direction of each of the pillars, such that the memory cells share a channel layer on the side surface of each pillar. In the three-dimensional nonvolatile memory, it is desired to improve the writing characteristic.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of insulating layers and a plurality of conductive layers are alternately stacked above a substrate, a pillar that penetrates the stacked body while extending in a stacking direction of the stacked body, and a semiconductor layer, a first insulating layer, a charge accumulation layer, and a second insulating layer, which are stacked on a side surface of the pillar in order from the pillar, wherein the semiconductor layer has an average grain size that is larger on a side nearer to the pillar and is smaller on a side nearer to the first insulating layer.

The present invention will be explained below detail with reference to the accompanying drawings. The present invention is not limited to the following embodiment. The constituent elements in the following embodiment encompass those which can be easily assumed by a person skilled in the art, or which are substantially equivalent thereto.

Next, an explanation will be given of a semiconductor memory device according to an embodiment, with reference toFIGS. 1 to 11.

[Configuration Example of Semiconductor Memory Device]

FIG. 1shows a sectional view along a certain one of the conductive layers25of a semiconductor memory device1according to an embodiment, and an enlarged view near a columnar structure50. InFIG. 1, it should be noted that only two bit lines BL are illustrated.FIG. 2is a sectional view illustrating the semiconductor memory device1according to the embodiment in the stacking direction, which is taken along a line A-A′ ofFIG. 1.

As illustrated inFIGS. 1 and 2, the semiconductor memory device1according to the embodiment is formed as a NAND type flash memory that has, for example, a three-dimensional structure on a semiconductor substrate10, such as a silicon substrate. The semiconductor substrate10includes an n-well11in a surface layer part, and further includes a p-well12in the n-well11, and a plurality of n+-wells13in the p-well12. Here, the semiconductor memory device1may be formed on a conductive layer functioning as a source line, instead of being formed directly on the substrate, such as the semiconductor substrate10.

On the semiconductor substrate10, a stacked body Lm is formed, in which a plurality of conductive layers25and a plurality of insulating layers35are alternately stacked. Each of the conductive layers25is, for example, a W layer or the like, and each of the insulating layers35is, for example, an SiO2layer or the like.

In the stacked body Lm of the conductive layers25and the insulating layers35, there are a plurality of columnar structures50formed in a state of penetrating the stacked body Lm. The columnar structures50are arranged on the p-well12, at respective positions between two of the n+-wells13of the semiconductor substrate10. Each of the columnar structures50is formed, for example, substantially in a circular shape, when seen in a plan view. Here, each columnar structure50may be formed, for example, substantially in an elliptical shape, when seen in a plan view.

Each columnar structure50includes a core portion51serving as a pillar. On the sidewall of the core portion51, there are a plurality of layers formed in a state of surrounding the sidewall of the core portion51. These layers are a channel layer52serving as a semiconductor layer, a tunnel insulating layer53serving as a first insulating layer, a charge accumulation layer54, and a block insulating layer55serving as a second insulating layer, in this order from the core portion51side. The core portion51is formed of an insulator containing, for example, SiO2or the like as the main component. The channel layer52is formed of, for example, a silicon layer or the like, the charge accumulation layer54is formed of, for example, an SiN layer or the like, and each of the tunnel insulating layer53and the block insulating layer55is formed of, for example, an SiO2layer or the like. Here, the charge accumulation layer54may be formed of a floating gate that is conductive and is covered with an insulator around the outside.

The channel layer52includes at least two types of silicon layers different in crystal structure. For example, the average grain size of the channel layer52is larger the core portion51side and is smaller on the tunnel insulating layer53side. In other words, the crystallinity of the channel layer52is higher on the core portion51side and is lower on the tunnel insulating layer53side. It can also be said that, in the channel layer52, the layer on the core portion51side is a layer lower in electrical resistivity than the layer on the tunnel insulating layer53side. The layer of the channel layer52on the core portion51side has a layer thickness ratio of, for example, 40% or more and 90% or less, more preferably 50% or more and 80% or less, with respect to the entire channel layer52. Here, in the channel layer52, the crystal structure of either of the layer on the core portion51side and the layer on the tunnel insulating layer53side is not single, as the case may be. Further, there is a case where neither of these layers has a distinct interface. Incidentally, the average grain size and/or crystallinity of the channel layer52can be measured by using a nano-beam diffraction method, for example.

More specifically, in the channel layer52, the layer on the core portion51side may contain much single crystal silicon or polysilicon, and the layer on the tunnel insulating layer53side may contain much amorphous silicon. Alternatively, in the channel layer52, the layer on the core portion51side may contain much single crystal silicon, and the layer on the tunnel insulating layer53side may contain much amorphous silicon or polysilicon.

The semiconductor memory device1includes conductive layers26outside the stacked body Lm of the conductive layers25and the insulating layers35, at positions on the n+-wells13of the semiconductor substrate10. The conductive layers26are arranged in a state of sandwiching the stacked body Lm from the opposite sides, with their main surfaces facing the stacked body Lm side. An insulating layer36is interposed between each of the conductive layers26and the stacked body Lm.

Further, the semiconductor memory device includes conductive layers27above the stacked body Lm of the conductive layers25and the insulating layers35, such that the conductive layers27extend in a direction almost parallel to the main surface of the semiconductor substrate10. An insulating layer34is interposed between the conductive layers27and the stacked body Lm. The channel layer52included in each columnar structure50is connected to a conductive layer27by a contact28penetrating the insulating layer34. More specifically, a predetermined conductive layer27of the plurality of conductive layers27existing there is connected to the channel layer52of a predetermined columnar structure50.

[Function of Semiconductor Memory Device]

Next, an explanation will be given of a function of the semiconductor memory device1serving as a three-dimensional NAND type flash memory, with reference toFIGS. 1 and 2again.

The channel layer52, the tunnel insulating layer53, the charge accumulation layer54, and the block insulating layer55, which are included in each columnar structure50, function as nonvolatile memory cells MC, at least partly. The memory cells MC are arranged at the height positions of the conductive layers25that make a stacked structure. Specifically, a plurality of memory cells MC are arrayed on each columnar structure50in the height direction of the columnar structure50. These memory cells MC are electrically connected to each other in series to function as a continuous memory string present on the side surface of one core portion51.

Of the stacked conductive layers25, those portions in contact with at least the side surface of each columnar structure50, together with those portions present nearby, function as word lines WL connected to the memory cells MC. Each of the memory cells MC is arranged in association with the corresponding one of the word lines OIL present at the same height.

Of the plurality of conductive layers25, those conductive layers25at the uppermost layer and the lowermost layer function as selection gate lines SGL. The selection gate lines SGL are used to select a predetermined memory string from the memory strings connected in co to a certain one of the conductive layers27. Further, those portions of the channel layer52, the tunnel insulating layer53, the charge accumulation layer54, and the block insulating layer55, which correspond to the selection gate lines SGL, function as selection gates SG. When the selection gates SG are turned on or off, a predetermined memory string is set into a selected state or non-selected state.

Each of the conductive layers26present outside these memory cells MC arranged in a matrix format functions as a plate-like source line contact LI, which is connected to the semiconductor substrate10functioning as a source line. Further, the conductive layers27arranged above the memory cells MC function as bit lines BL.

[Operation of Semiconductor Memory Device]

Next, an explanation will be given of an operation example of the semiconductor memory device1, with reference toFIGS. 1 and 2again.

When data “0” (for example, “H” level data (is to be written into a memory cell MC, a write voltage is applied to the word line WL connected to the memory cell MC. Here, the memory cell MC includes the channel layer52, which is connected to a bit line BL and to the semiconductor substrate10serving as a source line. At this time, in the channel layer52, a channel is formed, in which, for example, the ground potential is supplied and electrons flow. As the channel is formed in the channel layer52, electrons in the channel pass through the tunnel insulating layer53and are injected into and accumulated in the charge accumulation layer54. Consequently, the threshold voltage with of the memory cell MC is raised, and data “0” is thereby written therein.

At this time, in the channel layer52, the channel in which electrons flow is formed nearer to the core portion51that is lower in electrical resistivity. Accordingly, electrons serving as carriers are unevenly distributed in the channel layer52in a state of being nearer to the core portion51. In this way, as the inside of the channel layer52has different crystal structures, the channel layer52behaves as a retrograde channel that partly includes a low resistivity layer.

When data “1” (for example, “L” level data) is to be written into a memory cell MC, the channel of the channel layer52is set into a floating state so as not to inject electrons into the charge accumulation layer54, and data “1” is thereby written.

[Manufacturing Process for Semiconductor Memory Device]

Next, an explanation will be given of a manufacturing process example for the semiconductor memory device1, with reference toFIGS. 3 to 11.FIGS. 3 to 11are flow-related diagrams illustrating examples of procedures in a manufacturing process for the semiconductor memory device1according to the embodiment. In each ofFIGS. 3 to 11, the upper side shows a plan view of the semiconductor memory device1in the middle of manufacturing, and the lower side shows a sectional view of the same. Here, in each ofFIGS. 3 to 11, the regions corresponding to the source line contacts LI and the insulating layers36are omitted.

As illustrated inFIG. 3, on the semiconductor substrate10formed with the n-well11, the p-well12, the n+-wells (not illustrated), and so forth, a stacked structure is formed on the p-well12by alternately stacking the insulating layer35and a sacrificial layer45as a number of layers. The sacrificial layer45is an insulating layer made of a material, such as SiN, different from that of the insulating layer35. The sacrificial layer45is a layer to be replaced with the conductive layer25later.

Then, as illustrated inFIG. 4, memory holes MH are formed to penetrate the stacked structure of the sacrificial layers45and the insulating layers35and to reach the semiconductor substrate10. Each of the memory holes MH is formed at a region for forming the columnar structure50.

Then, as illustrated inFIG. 5, an insulating material is deposited inside each memory hole PH to form the block insulating layer55on the inner wall of the memory hole MH. Further, an insulating material is deposited inside each memory hole MH to form the charge accumulation layer54on the block insulating layer55. Further, an insulating material is deposited inside each memory hole MH to form the tunnel insulating layer53on the charge accumulation layer54. Further, a semiconductor material is deposited inside each memory hole PH to form a channel layer52aon the tunnel insulating layer53. At this time, the channel layer52adoes not include layers different in crystal structure, but has been formed entirely as a layer made of, for example, amorphous silicon or the like.

Then, as illustrated inFIG. 6, the entire resultant structure is annealed at a temperature of 1,000° C. or lower in a hydrogen atmosphere. The hydrogen atmosphere is an atmosphere containing at least hydrogen gas, and the atmosphere may contain an inactive gas, such as nitrogen gas or a rare gas.

Consequently, amorphous silicon forming the channel layer52ais melted, in the surface layer of the channel layer52a, i.e., in that part of the channel layer52a, which is down to a predetermined depth in the depth direction from the surface opposite to the tunnel insulating layer53. The predetermined depth, to which the channel layer52ais to be melted here, reaches, for example, a depth of 40% or more and 90% or less, more preferably a depth of 50% or more and 80% or less, in the channel layer52a. Then, silicon atoms in the melted part migrate within the surface layer of the channel layer52a, and are reconstructed to form a more stable arrangement.

The part thus reconstructed is larger in average grain size and higher in crystallinity, as compared to the other part left unmelted. Accordingly, the reconstructed part contains much single crystal silicon. In this way, the channel layer52is formed that includes at least two types of silicon layers different in crystal structure.

Then, as illustrated inFIG. 7, an insulating material is deposited or applied to fill each memory hole MH almost completely, and thereby to form the core portion51in the region surrounded by the channel layer52. Consequently, the columnar structures50are formed.

Then, as illustrated inFIG. 8, the sacrificial layers45are removed through a slit ST, which has been formed around the region formed with the columnar structures50in a state of penetrating the stacked structure of the sacrificial layers45and the insulating layers35. Consequently, gaps45gare formed between the insulating layers35, from which the sacrificial layers45have been removed.

Then, as illustrated inFIG. 9, a conductive material is filled, through the slit ST around the region formed with the columnar structures50, into the gaps45gformed by removing the sacrificial layers45. Consequently, the conductive layers25are formed in a state of being alternately stacked between the insulating layers35.

The procedures illustrated inFIGS. 8 and 9are sometimes called “replacement” with the conductive layers25. For this replacement, heat at a temperature of 1,000° C. or higher is applied, in some oases. Consequently, there is a case where the layer of the channel layer52which contains much single crystal silicon is partly or entirely denatured to contain much polysilicon. Further, there is a case where the layer of the channel layer52which corresponds to the unmelted part and contains much amorphous silicon is partly or entirely denatured to contain much polysilicon.

Then, as illustrated inFIG. 10, the insulating layer34is formed on the upper surface of the stacked body of the conductive layers25and the insulating layers35. Further, through holes are formed IF the insulating layer34such that each of the through holes is at a position overlapping with the channel layer52of a predetermined columnar structure50, when seen in a plan view. Then, a conductive material is embedded into the through holes. Consequently, the contacts28are formed.

Then, as illustrated inFIG. 11, the conductive layers27are formed on the insulating layer34such that each of the conductive layers27is at a position overlapping with a predetermined contact28. Consequently, each conductive layer27is connected to the channel layer52of a predetermined columnar structure50through the corresponding contact28.

As a result, the semiconductor memory device1according to the embodiment is manufactured.

As described above, the channel layer to be shared by memory cells is formed by, for example, deposition into the corresponding memory hole. Accordingly, the channel layer becomes a poor quality layer, which is mainly made of amorphous silicon, polysilicon, or the like, and thus contains crystal defects. In memory cells including such a channel layer, there is a case where the writing characteristic is deteriorated, for example, such that a steep distribution of threshold voltage Vth can be hardly obtained because adjacent memory cells mutually affect the threshold voltages Vth of their own in a writing operation.

In the semiconductor memory device1according to the embodiment, the channel layer52includes a layer that contains much single crystal silicon or polysilicon and has a low electrical resistivity. Consequently, the channel layer52is improved in mobility of electrons serving as carriers. Further, in the channel layer52, the layer lower in electrical resistivity is formed on the core portion51side. Consequently, electrons are caused to flow in the channel layer52at a position distant from the interface with the tunnel insulating layer53and near the core portion51, while avoiding crystal defects or the like that can be easily generated near the interface with the tunnel insulating layer53. Thus, electrons can be less scattered or trapped by crystal defects. As a result, it is possible to obtain a steep distribution of threshold voltage Vth in each memory cell MC, and thereby to improve the writing characteristic.

In the semiconductor memory device1according to the embodiment, the channel layer52including the layer lower in electrical resistivity is formed by annealing at a relatively low temperature of 1,000° C. or lower. Consequently, it is possible to suppress the influence of thermal history in the manufacturing process for the semiconductor memory device1. For example, annealing at a high temperature can affect the distribution of threshold voltage Vth by denaturing SiN or the like forming the charge accumulation layer54. On the other hand, annealing at a low temperature can suppress such an influence. Further, for example, in the case of annealing at a high temperature after formation of the conductive layers to be word lines, there is a concern that corrosive degassing is caused from the conductive layers. On the other hand, the semiconductor memory device1according to the embodiment does not entail such a concern.