Method for forming isolation region in semiconductor device using trench

A method for forming an isolation region in a semiconductor device using a trench comprising the steps of forming a reaction restraining layer on a semiconductor substrate, removing a portion of the reaction restraining layer corresponding to a trench region for providing an isolation region, forming a reaction film on the entire exposed surface, heat treating the reaction film and the substrate, to form a reaction product film having a predetermined depth in a portion of the reaction film and a portion of the substrate corresponding to said trench region, etching and removing the reaction product film, to form a trench, forming an insulation film for the isolation region such that it fills sufficiently the trench, forming a surface smoothing insulation film on the insulation film for the isolation region, etching back both the insulation films such that their portions located above a predetermined height from the surface of the substrate are removed, and removing the remaining reaction restraining layer.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a method for forming an isolation region 
providing an isolation between neighboring elements in making a 
semiconductor device, and more particularly to a method for forming such 
an isolation region using a trench. 
2. Description of the Prior Art 
A method for forming an isolation region using a trench in the manufacture 
of a complementary metal oxide semiconductor (CMOS) has been known in the 
technical field and is illustrated in FIGS. 3A to 3G. Such a method will 
now be described, in conjunction with the drawings. 
As shown in FIG. 3A, on a p type silicon substrate 21, a pad oxide film 22 
and a nitride film 23 are deposited in this order, using a chemical vapor 
deposition (CVD) method. Using a photoresist 24 formed on the nitride film 
23, a trench region is defined at the nitride film 23. 
Using the photoresist 24 as a mask, the nitride film 23 and the oxide film 
22 are then subjected to a dry etching, to remove their portions 
corresponding to the trench region and thus form a trench window, as shown 
in FIG. 3B. The p type silicon substrate 21 is also subjected to the dry 
etching using the photoresist 24 as a mask, so as to form a trench at a 
region located beneath the surface of the p type silicon substrate 21. 
Following a removal of the photoresist 24, a polysilicon film 25 is 
deposited on the entire exposed surface, as shown in FIG. 3C. The 
polysilicon film 25 is made of polysilicon doped with p type impurity ions 
such as boron ions and serves as a diffusion source for n type channel 
stop ions. 
Thereafter, a photoresist 26a is formed on a desired portion of the 
polysilicon film 25, to define an n type well region in the substrate 21. 
Such an n type well region is needed for providing a p type metal oxide 
semiconductor (PMOS). Using the photoresist 26a as a mask, the polysilicon 
25 is then dry etched to remove its portion corresponding to the defined n 
type well region. using the photoresist 26a as a mask again, n type 
impurity ions are slantly implanted in the n type well region. By an 
annealing process, the implanted impurity ions are diffused to obtain an n 
type well for the PMOS. 
The photoresist 26 is then removed, as shown in FIG. 3E. The polysilicon 
film 25 remaining in an n type metal oxide semiconductor (NMOS) region is 
then subjected to an annealing process so that p type boron ions doped in 
the polysilicon film 25 are diffused, thereby forming a p type channel 
stop layer 28 at a region located beneath a surface portion of the trench 
corresponding to the NMOS region, as shown in FIG. 3F. 
As shown in FIG. 3F again, the polysilicon film 25 is then removed and an 
oxide film 29 is thermally formed in the trench. For providing an 
isolation region, an oxide film 30 is then deposited on the entire exposed 
surface, using the CVD method. This deposition is carried out such that 
the trench is completely filled with the oxide film 30. However, a groove 
is formed on the oxide film 30 above the trench. This groove is filled 
with a smoothing polymer 31, so as to make the surface of the oxide film 
30 smooth. 
Subsequently, the oxide film 30 including the polymer 31 is etched backed 
from its surface to the surface of nitride film 23 using a dry etch 
process, thereby forming a surface-smoothed element isolating region 30a, 
as shown in FIG. 3G. 
However, the above-mentioned prior art has the following problems. 
First, since the p type silicon substrate is vertically etched back using 
the dry etch process to form the trench therein, it is likely to generate 
crystal defects in the substrate at bottom and side portions of the 
trench. 
Second, the depth of trench is varied depending on the pattern size in each 
element isolating region, thereby varying the size of the groove which is 
formed when the oxide film is deposited to fill the trench. As a result, a 
step referred to as a micro loading effect occurs between neighboring 
isolation regions. 
SUMMARY OF THE INVENTION 
Therefore, an object of the invention is to provide a method for forming an 
isolation region in a semiconductor device using a trench, capable of 
avoiding occurrences of crystal defects and a micro loading effect in a 
formation of the trench for providing the isolation region. 
In one aspect, the present invention provides a method for forming an 
isolation region in a semiconductor device using a trench comprising the 
steps of: forming a reaction restraining layer on a semiconductor 
substrate; removing a portion of said reaction restraining layer 
corresponding to a trench region defined in advance, to form a trench mask 
window; forming a reaction film on the entire exposed surface; etching 
said reaction film to form side wall reaction films at opposite side walls 
of said trench mask window; heat treating said side wall reaction films 
and said substrate at a predetermined temperature, to form reaction 
product films at the side wall reaction films and portions of the 
substrate located beneath the side wall reaction films; removing said 
reaction product films and then etching a portion of the substrate located 
in said trench region, to form a trench having a predetemined depth in the 
substrate; forming an insulation film for an element isolating region on 
the entire exposed surface such that it fills sufficiently the trench 
including a recess formed by the removal of the reaction product films; 
forming a surface smoothing insulation film on said insulation film for 
the element isolating region; etching back both the insulation films such 
that their portions located above a predetermined height from the surface 
of the substrate are removed; and removing the remaining reaction 
restraining layer. 
In another aspect, the present invention also provides a method for forming 
an isolation region in a semiconductor device using a trench comprising 
the steps of: forming a reaction restraining layer on a semiconductor 
substrate; removing a portion of said reaction restraining layer 
corresponding to a trench region defined in advance, to form a trench mask 
window; forming a reaction film on the entire exposed surface; heat 
treating said reaction film and said substrate at a predetermined 
temperature, to form a reaction product film having a predetermined depth 
in a portion of the reaction film and a portion of the substrate 
corresponding to said trench region; removing said reaction product film 
and the reaction film remaining on the reaction restraining layer, to form 
a trench; forming an insulation film for an element isolating region on 
the entire exposed surface such that it sufficiently fills the trench; 
forming a surface smoothing insulation film on said insulation film for 
the element isolating region; etching back both the insulation films such 
that their portions located above a predetermined height from the surface 
of the substrate are removed; and removing the remaining reaction 
restraining layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring to FIGS. 1A to 1F, there is illustrated a method for forming an 
isolation region in a semiconductor device using a trench, in accordance 
with a first embodiment of the present invention. 
In accordance with this embodiment, first, on a silicon substrate 1 there 
is deposited a pad oxide film 2 and a nitride film 3 in this order thereby 
forming a reaction restraining layer, using a CVD method, as shown in FIG. 
1A. A photolithography process is carried out to define a trench in the 
substrate 1. As the material of substrate 1, other semiconductor materials 
may be used. 
Thereafter, the nitride film 3 and the pad oxide film 2 are dry etched such 
that their portions overlying the defined trench region are removed, 
thereby forming a trench mask window. Over the entire exposed surface, a 
reaction film 4 is deposited using either a sputtering method or the CVD 
method. 
As shown in FIG. 1B, the reaction film 4 is then subjected to an 
anisotropic dry etch process such as a reactive ion etch process, so as to 
leave side wall reaction films 4a located at opposite side walls of the 
trench mask window and remove other portions of the reaction film 4. The 
material of reaction film 4 may include a metal being reactable with the 
material of silicon substrate 1 to produce a compound or a metal having a 
certain solubility making it melt at a certain temperature and penetrate 
at an atomic state into the silicon substrate 1. 
The reaction film 4 is then heat treated at a predetermined temperature in 
an active or inert atmosphere. At this time, where the reaction film 4 is 
a metal being reactable with the material of silicon substrate 1, it 
produces a compound in the reaction product films 5 and to a predetermined 
depth in portions of the silicon substrate 1 located beneath opposite side 
wall reaction films 4a. However, where the reaction film 4 is a metal 
having a predetermined solubility making it melt at a certain temperature 
and penetrate at an atomic state into the silicon substrate 1, a proper 
amount (atom 4) thereof is the atomic state penetrates or is impregnated 
into the lattices of portions of the silicon substrate 1 located beneath 
opposite side wall reaction films 4a, to a proper thickness or depth 
determined by the heat treatment temperature. In the latter case, 
accordingly, the reaction product film 5 is not a compound produced by a 
reaction between the silicon substrate 1 and the reaction film 4, but is 
the material of reaction film 4 itself. Thus, the reaction film 4 is 
either soluble in the substrate or is capable of reacting with the 
substrate 1 not with the reaction restraining film (that is, the pad oxide 
film 2 and the nitride film 3), and the reaction restraining film is not 
capable of reacting with the substrate 1 under the processing conditions 
employed. 
Thereafter, the reaction product films 5 which were formed to have a proper 
thickness or depth penetration in respective portions of silicon substrate 
1 corresponding to opposite edges of the trench region are then removed 
using a wet etch process, as shown in FIG. 1D. The silicon substrate 1 is 
then subjected to a dry etch process, so as to form a shallow trench in 
the trench region. The shallow trench has a depth less than that of the 
reaction product film 5 into substrate 1. 
Various metals usable as the material of reaction film 4 and various 
compounds (namely, various materials of reaction product film 5) produced 
by reactions of the metals with the silicon of substrate 1 are shown in 
TABLE 1. 
TABLE 1 
______________________________________ 
Reaction Film (4) 
Reaction Product Film (5) 
______________________________________ 
Na NaSi.sub.2 
Mg Mg.sub.2 Si 
Ca CaSi.sub.2, CaSi, Ca.sub.2 Si 
Ba BaSi 
La LaSi.sub.2 
Ce CeSi.sub.2 
Pr PrSi.sub.2 
Nd NdSi.sub.2 
Sm SmSi.sub.2 
Y YSi 
Ti TiSi, SiSi.sub.2, Ti.sub.5 Si.sub.3 
Sr Sr.sub.2 Si.sub.3 
Zr ZrSi.sub.2 
Hf HfSi.sub.2 
Th ThSi.sub.2 
U USi, USi.sub.2, U.sub.3 Si.sub.2, U.sub.3 Si 
Np NpSi.sub.2 
Pu PuSi.sub.2 
V V.sub.2 Si.sub.3, VSi.sub.2, V.sub.3 Si 
Nb NbSi.sub.2, Nb.sub.5 Si.sub.3 
Ta TaSi.sub.2 
Cr Cr.sub.3 Si.sub.2, Cr.sub.3 Si, CrSi.sub.2, CrSi 
Mo MoSi.sub.2, Mo.sub.3 Si, Mo.sub.5 Si.sub.3 
W WSi.sub.2 
Mn MnSi.sub.2, MnSi, Mn.sub.5 Si.sub.3, Mn.sub.3 Si 
Re ReSi.sub.2 
Fe FeSi, Fe.sub.5 Si.sub.3, Fe.sub.3 Si 
Co CoSi, Co.sub.2 Si 
Ni NiSi.sub.2, NiSi, Ni.sub.2 Si.sub.2, Ni.sub.2 Si, Ni.sub.5 
Si.sub.2, Ni.sub.3 Si 
Ru RuSi, Ru.sub.2 Si, Ru.sub.2 Si.sub.3 
Rh RhSi, RhSi.sub.0.5, Rh.sub.2 Si, Rh.sub.5 Si.sub.3, Rh.sub.3 
Si.sub.2, RhSi.sub.2 
Pd PdSi, Pd.sub.2 Si 
Os Os.sub.2 Si.sub.3, OsSi 
Ir Ir.sub.3 Si.sub.2, IrSi.sub.0.3, IrSi.sub.3, Ir.sub.3 Si, 
Ir.sub.2 Si 
Pt PtSi, Pt.sub.2 Si 
Be--Zr Alloy 
BeZrSi 
Cu--Mg Alloy 
Cu.sub.1.6 Mg.sub.6 Si.sub.7, Cu.sub.3 SiMg.sub.2 
Al--Na Alloy 
AlNaSi.sub.4 
Al--Ni Alloy 
AlNi.sub.2 Si 
Al--Fe--Mg Alloy 
Al.sub.8 FeMg.sub.3 Si 
Al--Cu--Mg Alloy 
Al.sub.5 Cu.sub.2 Mg.sub.8 Si 
Pd--Al Alloy 
Pd.sub.4 Al.sub.3 Si 
Cu Cu.sub.3 Si, Cu.sub.1.5 Si.sub.4, Cu.sub.5 Si, Cu.sub.7 Si 
Al--Cr Alloy 
Al.sub.3 CrSi, Al.sub.13 Cr.sub.4 Si.sub.4 
Al--Mn Alloy 
Al.sub.5 (Mn, Si).sub.2, Al.sub.21 Mn.sub.3 Si.sub.5, 
Al.sub.9 Mn.sub.3 Si 
Al--Fe Alloy 
AlFeSi, Al.sub.21 Fe.sub.3 Si.sub.5, Al.sub.9 Fe.sub.2 
Si.sub.2, Al.sub.4 FeSi.sub.2 
______________________________________ 
Various metals each having a solubility which is usable as the material of 
reaction film 4, their heat treatment temperatures and their amounts (atom 
%) at the atomic state which may penetrate into the silicon substrate 1 in 
heat treatments are shown in TABLE 2. 
TABLE 2 
______________________________________ 
Heat Treatment 
Penetrated Atom 
Reaction Film (4) 
Temperature % 
______________________________________ 
A1 557.degree. C.-400.degree. C. 
below 4 at % 
Ba 1,000.degree. C.-800.degree. C. 
below 2 at % 
Cr below 1,000.degree. C. 
below 6 at % 
Cu below 555.degree. C. 
below 10 at % 
Fe below 540.degree. C. 
below 7 at % 
Ni below 700.degree. C. 
below 10 at % 
Pb below 327.degree. C. 
100 at % 
Sb below 630.degree. C. 
100 at % 
Sn below 232.degree. C. 
100 at % 
Ti below 302.degree. C. 
100 at % 
______________________________________ 
Thereafter, an oxide film 6 an insulation film for an isolation region is 
deposited over the entire exposed surface using the CVD method, so as to 
fill completely the trench formed in the silicon substrate 1, as shown in 
FIG. 1D. At this time, a recess is formed at the upper portion of trench. 
In order to fill the recess, a surface smoothing oxide film 7 as an 
insulation film is deposited on the oxide film 6 using the CVD method. 
This oxide film 7 has an etch selectivity identical to that of the oxide 
film 6, but different from that of the nitride film 3. 
Using the dry etch process, the oxide film 7 is then etched back from its 
surface to the bottom surface of the recess, as shown in FIG. 1E. At this 
time, the oxide film 6 located above the bottom surface of the recess 
together with the oxide film 7 is also etched back. However, the nitride 
film 3 is not etched back, because of having an etch selectivity different 
from that of the oxide film 7. Subsequently, a heat treatment of the 
product is performed at an oxidizing atmosphere to compensate possible 
defects liable to occur in the silicon substrate during a formation of the 
shallow trench. 
Finally, the nitride film 3 is removed using the wet etch process, as shown 
in FIG. 1F. Thus, an element isolating region is obtained. 
FIGS. 2A to 2H illustrate a method for forming an isolation region in a 
semiconductor device using a trench in accordance with a second embodiment 
of the present invention. 
In this embodiment, first, a pad oxide film 9 and a nitride film 10 are 
deposited in this order on a silicon substrate 8 using the CVD method or 
the sputtering method, as reaction restraining layers, as shown in FIG. 
2A. A photolithography process is performed to define a trench region on 
the nitride film 10. At the defined trench region, the nitride film 10 and 
the pad oxide film 9 are subjected to a dry etch process such that their 
portions presented in the defined trench region are removed, thereby 
forming a trench mask window. 
Over the entire exposed surface, a reaction film 11 is then deposited to 
have a predetermined thickness using the sputtering method or the CVD 
method and then subjected to a heat treatment at a predetermined 
temperature, as shown in FIG. 2B. At this time, where the material of 
reaction film 11 is a metal being reactable with the material of silicon 
substrate 8 to produce a new compound, a portion of the reaction film 11 
and a predetermined thickness portion of the silicon substrate 8 located 
in the trench region are changed into the compound which forms a reaction 
product film 12. However, a portion of the reaction film 11 located above 
the nitride film 10 does not change. On the other hand, where the material 
of reaction film 11 is a metal having a certain solubility, it melts upon 
being heat treated at a predetermined temperature and thus a proper amount 
(at %) thereof at the atomic state penetrates or is impregnated into a 
predetermined thickness portion of the silicon substrate 8. In the latter 
case, accordingly, the reaction product film 12 is the material of 
reaction film 11 itself. 
Kinds of metals usable as the material of reaction film 11 and kinds of 
various materials of reaction product film 12 produced by reactions of the 
metals with the silicon of substrate 8 are the same as those shown in 
TABLE 1 and thus a detailed description thereof is omitted. Also, kinds of 
various metals each having a solubility to be usable as the material of 
reaction film 11, their heat treatment temperatures and their amounts (at 
%) at the atomic state penetrated into the silicon substrate 8 in heat 
treatments are the same as those shown in TABLE 2 and thus a detailed 
description thereof is omitted. 
Thereafter, the reaction film 11 and the reaction product film 12 are 
completely removed using the wet etch process, thereby causing a trench to 
be formed in the silicon substrate 8, as shown in FIG. 2D. As has been 
explained above with reference to the first embodiment of the present 
invention, the reaction film 11 is either soluble in the substrate or is 
capable of reacting with the substrate 8 but not with the reaction 
restraining film (that is, the pad oxide film 9 and the nitride film 10), 
and the reaction restraining film is not capable of reacting with the 
substrate 8 under the processing conditions employed. An oxide film 13 as 
an insulation film for an isolation region is deposited over the entire 
exposed surface using the CVD method. The deposition of oxide film 13 is 
achieved such that the oxide film 13 covers completely not only the 
trench, but also the remaining nitride film 10, as shown in FIG. 2E. 
After the deposition of oxide film 13, a groove is generated on the upper 
portion of the trench region. At this state, the silicon substrate 8 is 
subjected to a heat treatment at a predetermined temperature, so as to 
compensate possible defects in the silicon substrate 8 during a formation 
of the trench. In order to fill the groove sufficiently, a surface 
smoothing oxide film 14 as an insulation film is then deposited on the 
oxide film 13 using the CVD method or the sputtering method, as shown in 
FIG. 2F. This oxide film 14 has an etch selectivity identical to that of 
the oxide film 13, but different from that of the nitride film 10. 
Using the dry etch process, the oxide film 14 and the oxide film 13 are 
then etched back from the surface of oxide film 14 to the surface of 
silicon substrate 8, as shown in FIG. 2G. At this time, the nitride film 
10 is not etched back, because of having an etch selectivity different 
from those of oxide films 13 and 14. 
Finally, the remaining nitride film 10 is removed using the dry etch 
process, as shown in FIG. 2H. Thus, an element isolating region is 
obtained. 
As apparent from the above description, the present invention provides the 
following effects. 
First, in case of the first embodiment, reaction product films are formed 
around a trench corresponding to an isolation region in a silicon 
substrate such that they have a depth deeper than that of the trench. 
These reaction product films are subsequently removed using a wet etch 
process. Accordingly it possible to avoid the silicon substrate from being 
damaged at side wall portions and bottom portions of the trench. Also, the 
reaction product films make it possible for the trench to have a uniform 
depth irrespective of the pattern size of the element isolating region. By 
filling the trench with an insulation film for the isolation region, there 
is no formation of a groove above the trench region. As a result, it is 
possible to avoid an occurrence of a micro loading effect. 
Second, in case of the second embodiment, a similar reaction product film 
is formed in a trench region defined in the same manner as that of the 
first embodiment and subsequently removed using a wet etch process to form 
a trench for an isolation region. Accordingly, there is no problem that 
the substrate is damaged at side wall portions and bottom portions of the 
trench, upon forming the trench using a dry etch process as in the prior 
art. 
Although the preferred embodiments of the invention have been disclosed for 
illustrative purpose, those skilled in the art will appreciated that 
various modifications, additions and substitutions are possible, without 
departing from the scope and spirit of the invention as disclosed in the 
accompanying claims.