Non-volatile memory device and operating method thereof

A non-volatile memory device includes a first floating gate unit, a second floating gate unit, a selecting gate unit and a comparator. The first floating gate unit is configured to generate a first current according to a first bit signal and a control electric potential. The second floating gate unit is connected with the first floating gate unit in parallel, and configured to generate a second current according to a second bit signal and the control electric potential. The selecting gate unit is connected to the first floating gate unit and the second floating gate unit, and configured to generate the control electric potential according to a source signal and a word signal. The comparator is electrically connected to the first floating gate unit and the second floating gate unit, and configured to compare the first current with the second current, so as to generate a data-stored state signal.

RELATED APPLICATIONS

This application claims priority to Taiwan Application Serial Number 105109702, filed Mar. 28, 2016, which is herein incorporated by reference.

BACKGROUND

Field of Invention

The present disclosure relates to a memory system. More particularly, the present disclosure relates to a non-volatile memory device adopting a differential structure and an operating method thereof.

Description of Related Art

With the rapid advance of digital technology and the release of various kinds of electronics, performance requirements of memory units (such as high density and high speed storage) become more and more stringent. The memory unit is commonly integrated with an integrated chip system into a single chip by single chip technology to decrease size of chip systems according to the current trend of manufacturing the integrated chip system. Accordingly, the memory unit is correspondingly adopted a single poly-silicon gate to achieve the requirement of decreasing the size of chip systems. However, with the size decrement of chip systems, thickness of a gate oxide layer of the memory unit is correspondingly decreases. When the thickness of the gate oxide layer is excessively small, the current leakage may be incurred in the memory unit.

Traditionally, for obtaining a storage state of the memory unit, a comparator is used for comparing an electric potential of the memory unit with a reference electric potential, so as to determine a storage state of the memory unit. However, when the size decrement of chip systems results in increment of the current leakage, the determination of the storage state of the memory unit made by the above-mentioned comparing manner may be incorrect. Furthermore, additional peripheral circuits are commonly necessary to generate an accurate reference electric potential, but this also dramatically increases area of chip systems and cost of manufacturing chip systems.

Accordingly, a significant challenge is related to ways in which to accurately determine storage states of memory units while at the same time decreasing cost of manufacturing the memory units associated with designing the memory units.

SUMMARY

An aspect of the present disclosure is directed to a non-volatile memory device. The non-volatile memory device includes a first floating gate unit, a second floating gate unit, a selecting gate unit and a comparator. The first floating gate unit is configured to generate a first current according to a first bit signal and a control electric potential. The second floating gate unit is connected with the first floating gate unit in parallel, and configured to generate a second current according to a second bit signal and the control electric potential. The selecting gate unit is connected to the first floating gate unit and the second floating gate unit, and configured to generate the control electric potential according to a source signal and a word signal. The comparator is electrically connected to the first floating gate unit and the second floating gate unit, and configured to compare the first current with the second current to generate a data-stored state signal.

Another aspect of the present disclosure is directed to an operating method applied to a non-volatile memory device. The non-volatile memory device includes a first floating gate unit, a second floating gate unit, a selecting gate unit and a comparator. The operating method includes operations as follows: generating a control electric potential via the selecting gate unit according a source signal and a word signal; generating a first current and a second current via the first floating gate unit and the second floating gate unit respectively according to the control electric potential, a first bit signal and a second bit signal; and comparing the first current with the second current via the comparator to generate a data-stored state signal.

It is to be understood that the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.

DETAILED DESCRIPTION

FIG. 1is a circuit schematic diagram of a non-volatile memory device100according to embodiments of the present disclosure. As shown inFIG. 1, the non-volatile memory device100includes a first floating gate unit102, a second floating gate unit104, a selecting gate unit106and a comparator108. The selecting gate unit106is connected to one terminal of the first floating gate unit102and one terminal of the second floating gate unit104, and the first floating gate unit102is connected with the second floating gate unit104in parallel. The comparator108is electrically connected to the other terminal of the first floating gate unit102and the other terminal of the second floating gate unit104.

The selecting gate unit106is configured to receive voltage values of a source signal SL and a word signal WL, and generate a control electric potential according to voltage values of the source signal SL and the word signal WL. The first floating gate unit102is configured to receive a first bit signal BL1and the control electric potential generated from the selecting gate unit106, and to generate a first current I1according to a voltage value of the first bit signal BL1and a voltage value of the control electric potential. The second floating gate unit104is configured to receive a second bit signal BL2and the control electric potential generated from the selecting gate unit106, and to generate a second current I2according to a voltage value of the second bit signal BL2and the voltage value of the control electric potential. After the first floating gate unit102and the second floating gate unit104respectively generate the first current I1and the second current I2, the comparator108is configured to compare the first current I1with second current I2, and to generate a data-stored state signal S1according to the comparison result.

In this embodiment, at a moment, one of the first floating gate unit102and the second floating gate unit104can be triggered. In one embodiment, when the first floating gate unit102is triggered, it is determined that the data-stored state signal S1represents that the non-volatile memory device100is configured to store a binary bit 1; when the second floating gate unit104is triggered, it is determined that the data-stored state signal S1represents that the non-volatile memory device100is configured to store a binary bit 0; when neither of the first floating gate unit102and the second floating gate unit104is triggered, it is determined that the data-stored state signal S1represents that the non-volatile memory device100is not configured for data storage. It should be noted that, the relation among the data-stored state signal S1, the first floating gate unit102and the second floating gate unit104mentioned above is for illustration, and the present disclosure is not limited thereto.

In one embodiment, the non-volatile memory device100further includes an erasing gate unit112. The erasing gate unit112is connected to the first floating gate unit102and the second floating gate unit104. The erasing gate unit112receives an erasing signal EG and erases states of electrical properties of the first floating gate unit102and the second floating gate unit104according to a voltage value of the erasing signal EG. For example, when the non-volatile memory device100executes data storage process, the non-volatile memory device100enables the erasing gate unit112by the erasing signal EG in advance, so as to erase the states of the electrical properties of the first floating gate unit102and the second floating gate unit104to ensure that neither of the first floating gate unit102and the second floating gate unit104is triggered. In another embodiments, the erasing gate unit112can be used as a writing gate which is configured to trigger the first floating gate unit102and the second floating gate unit104to generate the first current I1and the second current I2.

For example, the non-volatile memory device100can operate according to voltage values mentioned in Table 1 as shown below, and “Float” represents floating voltage.

As mentioned in Table 1, when the non-volatile memory device100is not selected for data storage, a voltage value of the word signal WL is 0V; when the non-volatile memory device100is selected for data storage, the word signal WL, the source signal SL, the first bit signal BL1, the second bit signal BL2and the erasing signal EG respectively have corresponding voltage values according to the operation mode of the non-volatile memory device100. For example, when the first floating gate unit102is selected to be triggered by the non-volatile memory device100, the voltage value of the word signal WL is 3.3V, the voltage value of the source signal SL is 0V, the voltage value of the first bit signal BL1is 7V, the voltage value of the second bit signal BL2is 0V, and the voltage value of the erasing signal EG is the floating voltage. When the states of the electrical properties of the first floating gate unit102and the second floating gate unit104are selected to be erased by the non-volatile memory device100, the voltage values of the word signal WL, the source signal SL, the first bit signal BL1, the second bit signal BL2are 0V, and the voltage value of the erasing signal EG is 9.5V. When the second floating gate unit104is selected to be triggered by the non-volatile memory device100, the analysis of the voltage values of the signals corresponding to the non-volatile memory device100are similar to the illustration mentioned above, so a detail description will not be repeated herein.

In one embodiment, the comparator108determines the states of the electrical properties of the first floating gate unit102and the second floating gate unit104according to a current difference between the first current I1and the second current I2. For example, when the first current I1is smaller than the second current I2, it is determined that the first floating gate unit102is triggered; when the first current I1is larger than the second current I2, it is determined that the second floating gate unit104is triggered; when the first current I1is equal to the second current I2, it is determined that neither of the first floating gate unit102and the second floating gate unit104is triggered. It should be noted that, the determination of triggering the first floating gate unit102and the second floating gate unit104mentioned above is for illustration, and the present disclosure is not limited thereto.

FIG. 2is a schematic diagram of the non-volatile memory device100according to embodiments of the present disclosure. As shown inFIG. 2, edges of the first floating gate unit102and the second floating gate unit104overlay the erasing gate unit212during layout. In one embodiment, when portions of the edges of the first floating gate unit102and the second floating gate unit104which overlay the erasing gate unit212are decreased, voltage differences among the first floating gate unit102, the second floating gate unit104and the erasing gate unit212can be increased, so that the erasing gate unit212can erase the states of the electrical properties of the first floating gate unit102and the second floating gate unit more efficiently.

In another embodiment, size of the first floating gate unit102and the second floating gate unit104are decreased for increasing channel resistance corresponding to the first floating gate unit102and the second floating gate unit104, and size of the selecting gate unit106is increased for decreasing channel resistance corresponding to the selecting gate unit106. Accordingly, operation efficiency of the non-volatile memory device100can be effectively enhanced. In further embodiment, an isolation section214is disposed between the different non-volatile memory devices100. The isolation section214is configured to isolate current effect between the different non-volatile memory devices100, so as to remain operation of the non-volatile memory devices100.

FIG. 3is a flow chart300of an operating method applied to a non-volatile memory device according to embodiments of the present disclosure. In one embodiment, this operating method can be executed by the non-volatile memory device100mentioned above, but the present disclosure is not limited thereto. For facilitating the understanding of the flow chart300, the non-volatile memory device100is used as an example for illustrating the flow chart300. As shown inFIG. 3, in an operation S301, firstly, it is receiving the source signal SL and the word signal WL and generating the control electric potential according to the voltage values of the source signal SL and the word signal WL via the selecting gate unit106. In an operation S302, it is receiving control electric potential, the first bit signal BL1and the second bit signal BL2and generating the first current I1and the second current I2according to the voltage values of the control electric potential, the first bit signal BL1and the second bit signal respectively via the first floating gate unit102and the second floating gate unit104. Finally, in an operation S303, after the first floating gate unit102and the second floating gate unit104generates the first current I1and the second current I2, it is comparing the first current I1with second current I2via the comparator108to generate the data-stored state signal S1.

In one embodiment, before executing the operation S301, it is enabling the erasing gate unit112by the erasing signal EG, so as to erase the states of the electrical properties of the first floating gate unit102and the second floating gate unit104to ensure that neither of the first floating gate unit102and the second floating gate unit104is triggered.

In one embodiment, in the operation S303, the states of the electrical properties of the first floating gate unit102and the second floating gate unit104is determined according to the current difference between the first current I1and the second current I2, so as to generate the data-stored state signal S1. For example, when the first current I1is smaller than the second current I2, it is determined that the first floating gate unit102is triggered; when the first current I1is larger than the second current I2, it is determined that second floating gate unit104is triggered; when the first current I1is equal to the second current I2, it is determined that neither of the first floating gate unit102and the second floating gate unit104is triggered. It should be noted that, the determination of triggering the first floating gate unit102and the second floating gate unit104mentioned above is for illustration, and the present disclosure is not limited thereto.

As mentioned above, the present disclosure implements the non-volatile memory device by a differential structure. Accordingly, the non-volatile memory device can execute a comparison procedure merely according to currents generated itself, so as to determine data-stored states. Therefore, traditionally, a peripheral circuit which is configured to generate a reference electric potential for the non-volatile memory device to determine the data-stored states can be removed, so as to dramatically decrease an area of the non-volatile memory device and cost of manufacturing the non-volatile memory device. Additionally, when a coupling portion of the edge of the floating gate unit which overlays the erasing gate unit is decreased, the voltage difference between the floating gate unit and the erasing gate unit can be increased, so as to enhance erasing effect of the erasing gate unit.