A nitride semiconductor light-emitting element includes an n-type semiconductor layer, an active layer being formed on the n-type semiconductor layer and emitting ultraviolet light, an electron blocking layer formed on the active layer, and a p-type semiconductor layer formed on the electron blocking layer. A plurality of pits are formed at least in the active layer. A ratio R=D2/D1, which is a ratio of a second density D2 to a first density D1, is less than 30%, where the first density D1 is a density of the pits on an upper surface of the active layer and the second density D2 is a density of the pits on an upper surface of the electron blocking layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based on Japanese patent application No. 2023-120526 filed on Jul. 25, 2023, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a nitride semiconductor light-emitting element.

BACKGROUND OF THE INVENTION

Patent Literature 1 discloses a nitride semiconductor light-emitting element in which V-pits, which are a type of crystal defect, are formed in a light-emitting layer. Patent Literature 1 also describes that since the V-pits are formed in the light-emitting layer, occurrence of non-luminescent recombination is suppressed and luminous efficiency is thereby improved.Citation List Patent Literature 1: JP2015-050247A

SUMMARY OF THE INVENTION

In case of the nitride semiconductor light-emitting element described in Patent Literature 1, however, there is room for improvement in terms of suppressing a decrease in light output over time and thereby extending service life.

The invention was made in view of such circumstances and it is an object of the invention to provide a nitride semiconductor light-emitting element that can achieve an extended service life.

To achieve the object described above, the invention provides a nitride semiconductor light-emitting element, comprising:an n-type semiconductor layer;an active layer being formed on the n-type semiconductor layer and emitting ultraviolet light;an electron blocking layer formed on the active layer; anda p-type semiconductor layer formed on the electron blocking layer,wherein a plurality of pits are formed at least in the active layer, andwherein a ratio R=D2/D1, which is a ratio of a second density D2to a first density D1, is less than 30%, where the first density D1is a density of the pits on an upper surface of the active layer and the second density D2is a density of the pits on an upper surface of the electron blocking layer.

Advantageous Effects of the Invention

According to the invention, it is possible to provide a nitride semiconductor light-emitting element that can achieve an extended service life.

DETAILED DESCRIPTION OF THE INVENTION

Embodiment

An embodiment of the invention will be described in reference toFIGS.1and2. The embodiment below is described as a preferred illustrative example for implementing the invention. Although some part of the embodiment specifically illustrates various technically preferable matters, the technical scope of the invention is not limited to such specific aspects.

FIG.1is a schematic diagram illustrating a configuration of a nitride semiconductor light-emitting element1. InFIG.1, the scale ratio of each semiconductor layer of the nitride semiconductor light-emitting element1(hereinafter, also simply referred to as the “light-emitting element1”) in a stacking direction is not necessarily the same as the actual scale ratio. Hereinafter, the direction of stacking each semiconductor layer of the light-emitting element1is referred to as the up-and-down direction. In addition, one side in the up-and-down direction, which is a side of a substrate2where each semiconductor layer is grown, (e.g., an upper side inFIG.1) will be referred to as the upper side, and the opposite side (e.g., a lower side inFIG.1) will be referred to as the lower side. In this regard, the terms “upper” and “lower” are used for descriptive purposes and do not limit the posture of the light-emitting element1with respect to the vertical direction when, e.g., the light-emitting element1is used.

The light-emitting element1constitutes, e.g., a light-emitting diode (LED) or a semiconductor laser (LD: laser diode). In the present embodiment, the light-emitting element1constitutes a light-emitting diode that emits light with a wavelength in an ultraviolet region. Particularly, the light-emitting element1in the present embodiment emits ultraviolet light at a central wavelength of not less than 240 nm and not more than 365 nm. The light-emitting element1can be used in fields such as, e.g., sterilization (e.g., air purification, water purification, etc.), medical treatment (e.g., light therapy, measurement/analysis, etc.), UV curing, etc.

The light-emitting element1includes a buffer layer3, an n-type semiconductor layer4, a composition gradient layer5, an active layer6, an electron blocking layer7and a p-type semiconductor layer8in this order on a substrate2. The light-emitting element1also includes an n-side electrode11provided on the n-type semiconductor layer4, and a p-side electrode12provided on the p-type semiconductor layer8.

As semiconductors constituting the light-emitting element1, it is possible to use, e.g., binary to quaternary group III nitride semiconductors expressed by AlaGabIn1-a-bN (0≤a≤1, 0≤b≤1, 0≤a+b≤1). In the present embodiment, binary or ternary group III nitride semiconductors expressed by AlcGa1-cN (0≤c≤1) are used as the semiconductors constituting the light-emitting element1. These group III elements may be partially substituted with boron (B) or thallium (TI), etc. In addition, nitrogen (N) may be partially substituted with phosphorus (P), arsenic (As), antimony (Sb) or bismuth (Bi), etc.

The substrate2is made of a material transparent to light emitted by the active layer6. The substrate2is, e.g., a sapphire (Al2O3) substrate. An upper surface of the substrate2is a c-plane. This c-plane may have an off-angle. Alternatively, e.g., an aluminum nitride (AlN) substrate or an aluminum gallium nitride (AlGaN) substrate, etc., may be used as the substrate2.

The buffer layer3is formed on the substrate2. In the present embodiment, the buffer layer3is made of aluminum nitride. When the substrate2is an aluminum nitride substrate or an aluminum gallium nitride substrate, the buffer layer3may not be necessarily included. The buffer layer3may also include a layer made of undoped AlpGa1-pN (0≤p≤1) that is formed on the layer made of aluminum nitride.

The n-type semiconductor layer4is formed on the buffer layer3. The n-type semiconductor layer4is, e.g., an n-type cladding layer made of AlqGa1-qN (0≤q≤1) doped with an n-type impurity. In the present embodiment, silicon (Si) is used as the n-type impurity. The same applies to the semiconductor layers containing an n-type impurity other than the n-type semiconductor layer4. Alternatively, germanium (Ge), selenium (Se) or tellurium (Te), etc., may be used as the n-type impurity. The n-type semiconductor layer4may be a single layer or may have a multilayer structure.

The composition gradient layer5is formed on the n-type semiconductor layer4. The composition gradient layer5is made of AlrGa1-rN (0≤r≤1). In the composition gradient layer5, an Al composition ratio at each position in the up-and-down direction is higher at an upper position. The composition gradient layer5may have, e.g., a very small region in the up-and-down direction (e.g., a region of not more than 5% of the entire composition gradient layer5in the up-and-down direction) in which the Al composition ratio does not increase toward the upper side.

The Al composition ratio of a lower end portion of the composition gradient layer5is preferably substantially the same (e.g., a difference within 5%) as an Al composition ratio of an upper portion of the n-type semiconductor layer4that is adjacent to the composition gradient layer5on the lower side. In addition, the Al composition ratio of an upper end portion of the composition gradient layer5is preferably substantially the same (e.g., a difference within 5%) as an Al composition ratio of a lower portion of a barrier layer61that is adjacent to the composition gradient layer5on the upper side.

The composition gradient layer5also serves as a trigger layer from which pits (see the reference sign10inFIG.2) originate. The details of the pits will be described later. The trigger layer is, e.g., a layer containing a high concentration of silicon. A silicon concentration in the trigger layer can be adjusted based on a density of dislocations9present in the n-type semiconductor layer4and a target density of the pits in the active layer6. In the present embodiment, the silicon concentration in the trigger layer is not less than 5.0×1018atoms/cm3and not more than 5.0×1019atoms/cm3.

The active layer6is formed on the composition gradient layer5serving as the trigger layer. The active layer6in the present embodiment has a multiple quantum well structure which includes plural well layers621,622. A band gap of the active layer6is adjusted so that ultraviolet light at a central wavelength of not less than 240 nm and not more than 365 nm can be output. When the active layer6has a multiple quantum well structure as in the present embodiment, the central wavelength of ultraviolet light emitted by the active layer6is preferably not less than 250 nm and not more than 300 nm, more preferably, not less than 260 nm and not more than 290 nm from the viewpoint of improving light output. In the present embodiment, the active layer6has three barrier layers61and three well layers621,622which are alternately stacked. In the active layer6, the barrier layer61is located at the lower end and the well layer622is located at the upper end.

Each barrier layer61is made of AlsGa1-sN (0<s≤1). An Al composition ratio of each barrier layer61is, e.g., not less than 75% and not more than 95%. Each barrier layer61has a film thickness of, e.g., not less than 2 nm and not more than 50 nm.

The well layers621,622are made of AltGa1-tN (0<t<1). An Al composition ratio t of each of the well layers621,622is smaller than the Al composition ratio s of the barrier layers61(i.e., t<s).

The three well layers621,622are configured such that the lowermost well layer621, which is the well layer arranged on the lowermost side, has a different configuration from the upper-side well layers622which are two well layers other than the lowermost well layer621. For example, a film thickness of the lowermost well layer621is not less than 1 nm greater than a film thickness of each of the two upper-side well layers622and the Al composition ratio of the lowermost well layer621is not less than 2% greater than the Al composition ratio of each of the two upper-side well layers622. In the present embodiment, the upper-side well layers622have a film thickness of not less than 2 nm and not more than 4 nm and an Al composition ratio of not less than 25% and not more than 45%, and the lowermost well layer621has a film thickness of not less than 4 nm and not more than 6 nm and an Al composition ratio of not less than 35% and not more than 55%. A difference between the film thickness of the lowermost well layer621and the film thickness of each upper-side well layer622can be not less than 2 nm and not more than 4 nm.

By increasing the Al composition ratio of the lowermost well layer621to higher than the Al composition ratio of the upper-side well layers622, crystallinity of the lowermost well layer621is improved. This is because the difference in the Al composition ratio between the lowermost well layer621and the n-type semiconductor layer4is reduced. The improved crystallinity of the lowermost well layer621improves crystallinity of each semiconductor layer formed on and above the lowermost well layer621in the active layer6. As a result, carrier mobility in the active layer6is improved and light output is improved. Such effects are more pronounced when the lowermost well layer621has a larger film thickness, but the film thickness of the lowermost well layer621is designed to be not more than a predetermined value from the viewpoint of suppressing an increase in the electrical resistance value of the entire light-emitting element1.

The lowermost well layer621contains silicon. This can also induce formation of the pits in the active layer6. In the present embodiment, a silicon concentration in the lowermost well layer621is not less than 1.0×1019atoms/cm3and not more than 6.0×1019atoms/cm3. The upper-side well layers622may also contain an n-type impurity such as silicon, and in this case, the lowermost well layer621preferably has the highest silicon concentration among the plural well layers621,622.

Although the example in which the active layer6has a multiple quantum well structure with the three well layers621,622has been described in the present embodiment, it is not limited thereto. The active layer6may have a multiple quantum well structure with two or not less than four well layers. Alternatively, the active layer6may have a single quantum well structure having only one well layer.

The electron blocking layer7is formed on the active layer6. The electron blocking layer7serves to improve efficiency of electron injection into the active layer6by suppressing occurrence of the overflow phenomenon in which electrons leak from the active layer6to the p-type semiconductor layer8side (hereinafter, also referred to as the electron blocking effect). The electron blocking layer7has a stacked structure in which a first layer71and a second layer72are stacked in this order from the lower side.

The first layer71is provided on the active layer6. The first layer71is made of, e.g., AluGa1-uN (0<u≤1). An Al composition ratio u of the first layer71is, e.g., not less than 90% and is made of aluminum nitride in the present embodiment. A film thickness of the first layer71is, e.g., not less than 0.5 nm and not more than 5.0 nm.

The second layer72is made of, e.g., AlvGa1-vN (0<v<1). An Al composition ratio v of the second layer72is smaller than the Al composition ratio t of the first layer71(i.e., v<t) and is, e.g., not less than 70% and not more than 90%. A film thickness of the second layer72is larger than the film thickness of the first layer71and is, e.g., not less than 15 nm and not more than 100 nm.

When the first layer71with a relatively high Al composition ratio has an excessively large film thickness, it causes an excessive increase in the electrical resistance value of the entire light-emitting element1since a semiconductor layer with a higher Al composition ratio has a higher electrical resistance value. For this reason, the film thickness of the first layer71is preferably small to some extent. On the other hand, if the film thickness of the first layer71is reduced, it increases the probability that electrons pass through the first layer71from the lower side to the upper side due to the tunnel effect. Therefore, in the light-emitting element1of the present embodiment, the second layer72is formed on the first layer71to suppress passage of electrons through the entire electron blocking layer7.

Each of the first layer71and the second layer72is composed of an undoped semiconductor layer or a semiconductor layer doped with a low concentration of an impurity. In the present embodiment, the electron blocking layer7is composed of undoped semiconductor layers. As will be described in detail later, a ratio of a density of the pits (see the reference sign10inFIG.2) on an upper surface70of the electron blocking layer7(i.e., the upper surface70of the second layer72) to a density of the pits on an upper surface60of the active layer6is preferably less than 30%, and from the viewpoint of reducing the density of the pits on the upper surface70of the electron blocking layer7, it is preferable that the impurity concentration in the electron blocking layer7be low, and it is more preferable that the electron blocking layer7be an undoped semiconductor layer. The electron blocking layer7may be composed of a single layer or may be composed of not less than three layers.

Silicon is included between the electron blocking layer7and the p-type semiconductor layer8. Silicon and magnesium are likely to be attracted to each other, hence, by including silicon between the electron blocking layer7and the p-type semiconductor layer8, magnesium trying to diffuse from the p-type semiconductor layer8toward the active layer6is blocked by the silicon between the electron blocking layer7and the p-type semiconductor layer8. In addition, hydrogen is likely to bond with magnesium, hence, diffusion of hydrogen from the p-type semiconductor layer8into the active layer6is also suppressed with the above-mentioned suppression of diffusion of magnesium from the p-type semiconductor layer8into the active layer6. Diffusion of magnesium and hydrogen into the active layer6may cause degradation of the active layer6and shorten the service life of the light-emitting element1, but the service life of the light-emitting element1can be extended by including silicon between the electron blocking layer7and the p-type semiconductor layer8.

Silicon between the electron blocking layer7and the p-type semiconductor layer8may be present in at least one of the following states: a solid solution state in the crystal; a cluster state; and a state in which a compound containing silicon is precipitated. The solid solution state of silicon in the crystal is a state in which silicon is doped in aluminum gallium nitride constituting a boundary portion between the electron blocking layer7and the p-type semiconductor layer8, i.e., a state in which silicon is located at lattice positions of aluminum gallium nitride. The cluster state of silicon is a state in which silicon excessively doped in aluminum gallium nitride constituting the boundary portion between the electron blocking layer7and the p-type semiconductor layer8is present at the lattice positions of aluminum gallium nitride and is also present as aggregates, etc., between the lattice positions. The state in which a compound containing silicon is precipitated is a state in which, e.g., silicon nitride, etc., is formed. In the boundary portion between the electron blocking layer7and the p-type semiconductor layer8, a silicon-containing layer may be formed or silicon-containing portions may be scattered in a plane direction orthogonal to the stacking direction.

The p-type semiconductor layer8is formed on the electron blocking layer7. The p-type semiconductor layer8has a lower Al composition ratio than that of the electron blocking layer7and is made of AlwGa1-wN (0≤w≤1) doped with a p-type impurity. Magnesium (Mg) can be used as the p-type impurity, but zinc (Zn), beryllium (Be), calcium (Ca), strontium (Sr), barium (Ba) or carbon (C), etc., may be used other than magnesium. In the present embodiment, the p-type semiconductor layer8has a p-type cladding layer81and a p-type contact layer82in this order from the lower side.

The p-type cladding layer81is provided so as to be in contact with the upper surface70of the electron blocking layer7. An Al composition ratio of the p-type cladding layer81can be set to lower than an Al composition ratio of a semiconductor layer of the electron blocking layer7adjacent to the p-type cladding layer81(i.e., lower than the Al composition ratio of the second layer72), and higher than an Al composition ratio of the p-type contact layer82. A film thickness of the p-type cladding layer81is, e.g., not less than 9 nm and not more than 105 nm.

The p-type contact layer82is a layer connected to the p-side electrode12(described later) and is doped with a high concentration of a p-type impurity. The p-type contact layer82is configured to have a low Al composition ratio (e.g., not more than 10%) to achieve an ohmic contact with the p-side electrode12, and from such a viewpoint, the p-type contact layer82is preferably made of p-type gallium nitride (GaN). Since the p-type contact layer82with a low Al composition ratio can absorb ultraviolet light emitted from the active layer6, a film thickness of the p-type contact layer82is preferably not more than 50 nm.

The n-side electrode11is formed on an exposed surface41of the n-type semiconductor layer4which is exposed from the active layer6on the upper side. The n-side electrode11can be, e.g., a multilayered film formed by sequentially stacking titanium (Ti), aluminum, titanium and gold (Au) on the n-type semiconductor layer4. When the light-emitting element1is flip-chip mounted as described below, the n-side electrode11may be composed of a material that can reflect ultraviolet light emitted by the active layer6.

The p-side electrode12is formed on an upper surface of the p-type semiconductor layer8. The p-side electrode12can be, e.g., a multilayered film formed by sequentially stacking nickel (Ni) and gold on the p-type semiconductor layer8. When the light-emitting element1is flip-chip mounted as described below, the p-side electrode12may be composed of a material that can reflect ultraviolet light emitted by the active layer6.

The light-emitting element1can be used in a state of being flip-chip mounted on a package substrate (not shown). That is, the light-emitting element1is mounted such that a side in the up-and-down direction, which is a side where the n-side electrode11and the p-side electrode12are provided, faces the package substrate and each of the n-side electrode11and the p-side electrode12is attached to the package substrate via a gold bump, etc. Light from the flip-chip mounted light-emitting element1is extracted on the substrate2side (i.e., on the lower side). However, it is not limited thereto and the light-emitting element1may be mounted on the package substrate by wire bonding, etc. In addition, although the light-emitting element1in the present embodiment is a so-called lateral light-emitting element in which both the n-side electrode11and the p-side electrode12are provided on the upper side of the light-emitting element1, the light-emitting element1is not limited thereto and may be a vertical light-emitting element. The vertical light-emitting element is a light-emitting element in which the active layer is sandwiched between the n-side electrode and the p-side electrode. In this regard, when the light-emitting element is of the vertical type, the substrate and the buffer layer are preferably removed by laser lift-off, etc.

Next, the pits10formed in the light-emitting element1in the present embodiment will be described.FIG.2is a schematic diagram illustrating an example of the pit10formed in the light-emitting element1in the present embodiment.

As shown inFIG.2, the pit10is a type of crystal defect that originates from the dislocation9propagated from the n-type semiconductor layer4side. It is considered that a growth mode of a matrix of the composition gradient layer5changes when a silicon source of not less than a predetermined concentration is supplied, during growth of the composition gradient layer5as the trigger layer, to locations where the dislocations9propagated from the n-type semiconductor layer4side are present, and the pits10are thereby formed. A portion of an upper surface of the composition gradient layer5is recessed and each semiconductor layer of the active layer6located thereon is further recessed along the recess on the upper surface of the composition gradient layer5, and the pit10is thereby formed in a multi-layered manner.

The light-emitting element1in the present embodiment is formed so that the density of the pits10observed on the upper surface70of the electron blocking layer7is lower than the density of the pits10observed on the upper surface60of the active layer6. That is, the light-emitting element1in the present embodiment has many pits10as shown inFIG.2, i.e., the pits10that are formed from the composition gradient layer5serving as the trigger layer to at least the upper surface60of the active layer6but not to the upper surface70of the electron blocking layer7.

A ratio R=D2/D1, which is a ratio of a second density D2to a first density D1, is less than 30%, more preferably less than 15%, where the first density D1is the density of the pits10on the upper surface60of the active layer6and the second density D2is the density of the pits10on the upper surface70of the electron blocking layer7. As will be described in detail later, reducing the ratio R improves the light output retention rate of the light-emitting element1and extends its service life. The light output retention rate of the light-emitting element1is a ratio of the current light output to the initial light output.

It is known that when the pits10are formed in the active layer6, occurrence of non-luminescent recombination is suppressed and the light output is improved (see, e.g., JP2019-054247 A). For this reason, it is preferable that the pits10be formed in the active layer6. From the viewpoint of improving the light output, the density of the pits10observed on the upper surface60of the active layer6is preferably not less than 1.0×109pits/cm2and not more than 5.0×109pits/cm2. The density of the pits10on the upper surface60of the active layer6can be controlled, e.g., by adjusting the density of dislocations present in the n-type semiconductor layer4and the silicon concentration in the composition gradient layer5serving as the trigger layer, etc.

There is an advantage in the formation of the pits10in the active layer6as mentioned above, but if there are many pits10which are formed up to the upper surface70of the electronic blocking layer7, the light output of the light-emitting element1is likely to decrease over time and the service life of the light-emitting element1is shortened. This is presumably because when the pits10are formed up to the upper surface70of the electron blocking layer7, magnesium, which is contained in the p-type semiconductor layer8, and hydrogen, which easily bonds to magnesium, are likely to diffuse into the active layer6through the pits10.

Therefore, by reducing the ratio R to as low as less than 30% as described above, the advantage in the formation of the pits10in the active layer6, which is improvement in the light output, and the advantage in having few pits10formed up to the upper surface70of the electron blocking layer7, which is longer service life, are obtained. From this point of view, the ratio R is preferably less than 15%.

The reduction of the second density D2can be achieved, e.g., by reducing an impurity concentration in the electron blocking layer7. Impurities such as magnesium and silicon tend to gather around the pits10. Therefore, when the electron blocking layer7is doped with an impurity such as magnesium, it is presumed that the impurity in the electron blocking layer7is attracted to the pits10, diagonal growth along the pits10in the areas where the pits10exist is promoted during deposition of the electron blocking layer7, and the pits10formed in the active layer6are transferred to the electron blocking layer7.

Therefore, from the viewpoint of reducing the ratio R, it is preferable that the impurity concentration in the electron blocking layer7be low, and it is more preferable that the electron blocking layer7be undoped. From the viewpoint of lowering the impurity concentration in the electron blocking layer7and thereby reducing the ratio R, it is preferable that the Al composition ratio of the electron blocking layer7be high. In this regard, the second density D2may be reduced by a method other than adjustment of the impurity concentration in the electron blocking layer7. For example, increasing the film thickness of the entire electron blocking layer7is considered to reduce the second density D2.

FIG.2shows an example in which the pit10is formed up to the upper surface of the first layer71of the electron blocking layer7but is buried in the second layer72and is not formed up to the upper surface70of the second layer72. In the present embodiment, it is presumed that the first layer71cannot completely fill the pits10since the film thickness of the first layer71is as very small as not less than 0.5 nm and not more than 5.0 nm as mentioned above, but the second layer72has a low impurity concentration and a film thickness which is more than the film thickness of each semiconductor layer of the active layer6, hence, the pits10are easily buried. Therefore, to reduce the ratio R, it is preferable that the electron blocking layer7include at least one semiconductor layer which is thicker than each semiconductor layer of the active layer6and has a low impurity concentration (preferably undoped). In addition, the film thickness of the entire electron blocking layer7is preferably not less than twice the film thickness of the thickest semiconductor layer among the semiconductor layers constituting the active layer6.

In the example inFIG.2, a minute depression700which appears on the upper surface70of the electron blocking layer7at the portion located above the pit10is also schematically shown. The minute depression700may appear on the upper surface70of the second layer72as a trace of burying the pit10in the second layer72of the electronic blocking layer7. The minute depression700is a depression which is minute with a depth D of less than 1 nm, and such a depression is not regarded as a pit. In other words, the second density D2is a density of depressions with the depth D of not less than 1 nm on the upper surface70of the electron blocking layer7. On the upper surface70of the electron blocking layer7, a density of relatively large pits10with the depth D of not less than 2 nm is preferably not more than 1.0×108pits/cm2.

A recessed surface101located at the uppermost position of the pit10is recessed so that a cross section parallel to the up-and-down direction has a substantially V-shape. The recessed surface101as a whole has a substantially cone or pyramid shape (e.g., a substantially cone shape, a substantially polygonal pyramid shape, an elliptic cone shape), or a substantially truncated cone or pyramid shape, with the region inside the recessed surface101becoming smaller toward the lower side. The pit10with the recessed surface101having a V-shaped cross section as described above is called a V-pit. The shape of the recessed surface101may be a circular column shape or a polygonal column shape, other than that having a V-shaped cross section. A diameter Φ of the uppermost edge of the recessed surface101of the pit10is not more than 100 nm, more specifically, not less than 20 nm and not more than 60 nm. When the recessed surface101of the pit10has a shape other than a cone, such as a polygonal pyramid, the diameter @ can be a diameter of a circle obtained when the uppermost edge of the recessed surface101is approximated by a circumscribed circle, etc. The total length L of the pit10in the up-and-down direction is, e.g., not less than 1 nm and not more than 60 nm.

Method for Manufacturing the Nitride Semiconductor Light-Emitting Element1

Next, an example of a method for manufacturing the light-emitting element1in the present embodiment will be described.

In the present embodiment, the buffer layer3, the n-type semiconductor layer4, the composition gradient layer5, the active layer6, the electron blocking layer7and the p-type semiconductor layer8are epitaxially grown on the disc-shaped substrate2in this order by the Metal Organic Chemical Vapor Deposition (MOCVD) method. That is, in the present embodiment, the disc-shaped substrate2is placed in a chamber and each semiconductor layer is formed on the substrate2by introducing source gases of each semiconductor layer to be formed on the substrate2into the chamber. As the source gases to epitaxially grow each semiconductor layer, it is possible to use trimethylaluminum (TMA) as an aluminum source, trimethylgallium (TMG) as a gallium source, ammonia (NH3) as a nitrogen source, tetramethylsilane (TMSi) as a silicon source, and biscyclopentadienylmagnesium (Cp2Mg) as a magnesium source.

In forming the composition gradient layer5, an amount of the silicon source supplied to the chamber is adjusted based on the density of the dislocations9present in the n-type cladding layer4and the target density of the pits10in the active layer6, etc.

The MOCVD method is sometimes called the Metal Organic Vapor Phase Epitaxy (MOVPE) method. To epitaxially grow each semiconductor layer on the substrate2, it is also possible to use another epitaxial growth method such as the Molecular Beam Epitaxy (MBE) method or the Hydride Vapor Phase Epitaxy (HVPE) method, etc.

After forming each semiconductor layer on the disc-shaped substrate2, a mask is formed on a portion of the p-type semiconductor layer8, i.e., a part other than the portion to be the exposed surface41of the n-type semiconductor layer4. Then, the region in which the mask is not formed is removed by etching from the upper surface of the p-type semiconductor layer8to the middle of the n-type semiconductor layer4in the up-and-down direction. The exposed surface41exposed upward is thereby formed on the n-type semiconductor layer4. After forming the exposed surface41, the mask is removed.

Subsequently, the n-side electrode11is formed on the exposed surface41of the n-type semiconductor layer4and the p-side electrode12is formed on the p-type semiconductor layer8. The n-side electrode11and the p-side electrode12may be formed by, e.g., a well-known method such as the electron beam evaporation method or the sputtering method. The object completed through the above process is cut into pieces with a desired dimension. Plural light-emitting elements1as shown inFIG.1are thereby obtained from one wafer.

Functions and Effects of the Embodiment

The ratio R=D2/D1, which is the ratio of the second density D2to the first density D1, is less than 30%, where the first density D1is the density of the pits10on the upper surface60of the active layer6and the second density D2is the density of the pits10on the upper surface70of the electron blocking layer7. Therefore, the light output retention rate of the light-emitting element1is improved and the service life of the light-emitting element1is extended.

In addition, the electron blocking layer7is composed of undoped semiconductor layers. This makes it easier to reduce the second density D2as described above.

In addition, the ratio R further satisfies less than 15%. Therefore, the service life of the light-emitting element1is further extended.

In addition, on the upper surface70of the electron blocking layer7, the density of the pits10with the depth of not less than 2 nm is not more than 1.0×108pits/cm2. Since the number of deep pits10on the upper surface70of the electron blocking layer7is small, the diffusion of magnesium, which is contained in the p-type semiconductor layer8, and hydrogen, which easily bonds to magnesium, into the active layer6through the pits10is suppressed, and the service life of the light-emitting element1is thereby further extended.

In addition, the film thickness of the p-type contact layer82made of p-type GaN is not more than 50 nm. In such a case, the service life of the light-emitting element1tends to be short, but the service life of the light-emitting element1can be extended by setting the ratio R to less than 30% as described above.

In addition, the film thickness of the electron blocking layer7is greater than the film thickness of each semiconductor layer of the active layer6. This increases the probability that the pits10are buried when depositing the electron blocking layer7, and the second density D2is thereby reduced.

As described above, according to the present embodiment, it is possible to provide a nitride semiconductor light-emitting element that can achieve an extended service life.

Experiment Example

This Experimental Example is an example in which the relationship between the ratio R and the light output retention rate was confirmed. In Experimental Example and subsequent sections, the names of components that are the same as those used in the previously described embodiment indicate the same components as those in the previously described embodiment, unless otherwise specified.

In this Experimental Example, first, wafers according to Examples A1 to A6 and wafers according to Comparative Examples A1 to A6 were made. In Examples A1 to A6, the wafers have the same stacking structure as the light-emitting element described in the embodiment, and the first layer71and the second layer72of the electron blocking layer7are both undoped. In Comparative Examples A1 to A6, the wafers have the same structure as Examples A1 to A6, except that the second layer72is doped with magnesium. In consideration of manufacturing variations, plural elements were made as Examples A1 to A6 by the same manufacturing method. Similarly, in consideration of manufacturing variations, plural elements were made as Comparative Examples A1 to A6 by the same manufacturing method. Table 1 shows the configurations of Examples A1 to A6 and Comparative Examples A1 to A6.

The film thickness of each semiconductor layer shown in Table 1 was measured by a transmission electron microscope. The A1 composition ratio of each semiconductor layer shown in Table 1 is a value estimated from secondary ion intensity of A1 measured by Secondary Ion Mass Spectrometry (SIMS). The figures in the column for “Composition gradient layer” in Table 1 show that the A1 composition ratio of the composition gradient layer5along the up-and-down direction changes from 55% to 85% from the lower end to the upper end.

The “Si concentration” and the “Mg concentration” shown in Table 1 are the silicon concentration and the magnesium concentration obtained using secondary ion mass spectrometry. The silicon concentration in the lowermost well layer621in Table 1 indicates the peak of the silicon concentration in the lowermost well layer621along the up-and-down direction. In Table 1, the “*” mark in the columns for “Si concentration” and “Mg concentration” means that the film thickness of the semiconductor layer is small and it is difficult to accurately measure the silicon concentration and the magnesium concentration. In addition, in Table 1, “BG” in the columns for “Si concentration” and “Mg concentration” means the background level. The background level is the concentration of silicon or magnesium that would be detected when not doped with silicon or magnesium.

FIG.3is a graph showing the silicon and magnesium concentration distributions in the up-and-down direction (hereinafter, also simply referred to as the “silicon concentration distribution” and the “magnesium concentration distribution”) obtained by secondary ion mass spectrometry for each of the light-emitting elements in Examples and Comparative Examples. The depth on the horizontal axis inFIG.3represents a depth in the up-and-down direction from the upper surface of the p-type semiconductor layer8. InFIG.3, the measurement result of the silicon concentration distribution in Example is represented by a thick solid line, the measurement result of the magnesium concentration distribution in Example is represented by a thick dashed line, the measurement result of the silicon concentration distribution in Comparison Example is represented by a thin solid line, and the measurement result of the magnesium concentration distribution in Comparison Example is represented by a thin dashed line. In addition, inFIG.3, the depth range of each semiconductor layer is marked with the reference sign of each semiconductor layer used in the embodiment.

First, it can be seen fromFIG.3that both the first layer71and the second layer72of the electron blocking layer7in Example are undoped. Here, when looking at the magnesium concentration distribution obtained using secondary ion mass spectrometry, even though the electron blocking layer7is undoped (i.e., even though the magnesium source is not supplied during the deposition of the electron blocking layer7), it looks as if magnesium is contained in an end portion of the electron blocking layer7on the p-type semiconductor layer8side in case that the semiconductor layer adjacent to the electron blocking layer7on the upper side is the p-type semiconductor layer8containing magnesium, but this is a problem with SIMS measurement. Therefore, when magnesium is contained in the adjoining position of the electron blocking layer7, it can be said that the electron blocking layer7does not contain magnesium if the magnesium concentration in the region of the electron blocking layer7other than the region on the adjoining position side (e.g., within a 10 nm range from such a location) is at the background level in the magnesium concentration distribution obtained by secondary ion mass spectrometry. Therefore, in Table 1, the Mg concentration in the second layer72in Example is indicated as background.

It can also be seen fromFIG.3that magnesium is contained in the second layer72of the electron blocking layer7in Comparative Example. It can be further seen fromFIG.3that magnesium in the second layer72is diffused to the active layer6in Comparative Example.

It can also be seen fromFIG.3that silicon is contained between the electron blocking layer7and the p-type semiconductor layer8. When silicon is contained between the electron blocking layer7and the p-type semiconductor layer8, a peak P of the silicon concentration appears between the electron blocking layer7and the p-type semiconductor layer8in the silicon concentration distribution. It is preferable that the value of the peak P satisfy not less than 1.0×1018atoms/cm3and not more than 1.0×1020atoms/cm3. By setting to not less than 1.0×1018atoms/cm3, it is easy to suppress diffusion of magnesium from the p-type semiconductor layer8side to the active layer6. Meanwhile, by setting to not more than 1.0×1020atoms/cm3, it is possible to suppress a decrease in crystallinity of the electron blocking layer7and the p-type semiconductor layer8which are adjacent to the position of the silicon on both sides. Furthermore, in the silicon concentration distribution in the stacking direction of the light-emitting element1, the value of the peak P more preferably satisfies not less than 3.0×1018atoms/cm3and not more than 5.0×1019atoms/cm3.

Here, when looking at the silicon concentration distribution obtained using secondary ion mass spectrometry, even though the electron blocking layer7is undoped (i.e., even though the silicon source is not supplied during the deposition of the electron blocking layer7), a tail portion, etc., of the peak P appears at the end portion of the electron blocking layer7on the p-type semiconductor layer8side and it looks as if silicon is contained in the end portion of the electron blocking layer7on the p-type semiconductor layer8side, but this is a problem with SIMS measurement. Therefore, when silicon is contained in the adjoining position of the electron blocking layer7, it can be said that the electron blocking layer7does not contain silicon if the silicon concentration in the region of the electron blocking layer7other than the region on the adjoining position side (e.g., within a 10 nm range from such a location) is at the background level in the silicon concentration distribution obtained by secondary ion mass spectrometry.

Next, for each of Examples A1 to A6 and Comparative Examples A1 to A6, the first density D1, which is the density of the pits10on the upper surface60of the active layer6, and the second density D2, which is the density of the pits10on the upper surface70of the electron blocking layer7, were obtained and the ratio R=D2/D1was calculated.

The first density D1was obtained as follow: first, each of Examples A1-A6 and Comparative Examples A1-A6, which was grown up to the active layer6, was taken out of the chamber, the upper surface60of the active layer6was photographed by an atomic force microscope, and the number of the pits10in the captured AFM image was counted.FIG.4shows an example of the AFM image of the upper surface60of the active layer6. When a 1 μm-square range of the upper surface60of the active layer6is photographed by an atomic force microscope as shown inFIG.4and if n pits10are observed in the captured image, the first density D1of the pits10observed in the captured image is calculated to be n [pits/μm2]=n×108[pits/cm2]. Regarding the first density D1, there was no significant difference between Examples and Comparative Examples as shown in Table 2 described later. In other words, in each of Examples and Comparative Examples, the state of the upper surface60of the active layer6is similar to the state shown inFIG.4.

The second density D2was obtained as follow: using different wafers, deposition was performed up to the electron blocking layer7under the same deposition conditions as those used for the wafers that are formed up to active layer6to measure the first density D1, the upper surface70of the electron blocking layer7was photographed by an atomic force microscope, and the number of the pits10in the captured image was counted. In each of Examples A1 to A6, the deposition of the wafer up to the active layer6to measure the first density D1and the deposition of the wafer up to the electron blocking layer7to measure the second density D2were performed in short intervals so that the deposition could be said to have been performed substantially simultaneously (i.e., so that the deposition conditions were the same). The same applies to each of Comparative Examples A1 to A6.FIG.5is an example AFM image showing the upper surface70of the electron blocking layer7in Example, andFIG.6is an example AFM image showing the upper surface70of the electron blocking layer7in Comparative Example. Table 2 shows the first density D1, the second density D2and the ratio R for Examples A1 to A6 and Comparative Examples A1 to A6.

It can be seen from Table 2 andFIGS.4to6that there is no significant difference in the first density D1between Examples and Comparative Examples, but the second density D2is lower in Examples than Comparative Examples. Then, it can be seen from Table 2 that the ratio R of Examples A1 to A6, in which the electron blocking layer7is undoped, is less than 30%, and the ratio R of Comparative Examples A1 to A6, in which the second layer72of the electron blocking layer7is doped with magnesium, is more than 30%. That is, in Examples A1 to A6, there are relatively many pits10which are formed at least up to the upper surface60of the active layer6but buried before reaching the upper surface70of the electron blocking layer7as shown inFIG.2. On the other hand, in Comparative Examples A1 to A6, there are relatively many pits10which are formed up to the upper surface70of the electron blocking layer7as shown in the schematic diagram ofFIG.7.

Here, the wafers in Examples A1 to A6 and Comparative Examples A1 to A6 were taken out of the chamber after growing the active layer6as well as after regrowing the electron blocking layer7to count the first density D1and the second density D2, but this action may affect the service life of the finished light-emitting element. Therefore, separately from Examples A1 to A6 and Comparative Examples A1 to A, light-emitting elements in Examples B1, B2 and Comparative Examples B1, B2 were made using wafers that were deposited without being taken out of the chamber during the deposition, and transition of light output was observed using these wafers.

Examples B1 and B2 are light-emitting elements made using wafers obtained under the same conditions as Examples A1 to A6, and Comparative Examples B1 and B2 are light-emitting elements made using wafers obtained under the same conditions as Comparative Examples A1 to A6. Since Examples B1 and B2 were made under the same conditions as Examples A1 to A6, the ratio R is expected to be similar to that of Examples A1 to A6, i.e., less than 30%. Likewise, since Comparative Examples B1 and B2 were made under the same conditions as Comparative Examples A1 to A6, the ratio R is expected to be similar to that of Comparative Examples A1 to A6, i.e., not less than 30%.

A current of 500 mA was continuously passed through each of Examples B1 and B2 and Comparative Examples B1 and B2 for 1000 hours to cause light emission, and transition of the light output was evaluated. The results of the transition of the light output for Examples B1 and B2 and Comparative Examples B1 and B2 are shown inFIGS.8and9.FIG.8is a diagram illustrating a relationship between the current supply time and the light output for Examples B1, B2 and Comparison Examples B1, B2.FIG.9is a diagram showing the light output ofFIG.8when converted into the light output retention rate.

As can be seen fromFIGS.8and9, Examples B1 and B2 with the ratio R of less than 30% show a lower rate of decrease in light output than Comparison Examples B1 and B2 with the ratio R of more than 30% and can achieve a longer service life.

Summary of the Embodiment

Technical ideas understood from the embodiment will be described below citing the reference signs, etc., used for the embodiment. However, each reference sign, etc., described below is not intended to limit the constituent elements in the claims to the members, etc., specifically described in the embodiment.

The first feature of the invention is a nitride semiconductor light-emitting element1including an n-type semiconductor layer4; an active layer6being formed on the n-type semiconductor layer4and emitting ultraviolet light; an electron blocking layer7formed on the active layer6; and a p-type semiconductor layer8formed on the electron blocking layer7, wherein a plurality of pits10are formed at least in the active layer6, and

wherein a ratio R=D2/D1, which is a ratio of a second density D2to a first density D1, is less than 30%, where the first density D1is a density of the pits10on an upper surface60of the active layer6and the second density D2is a density of the pits10on an upper surface70of the electron blocking layer7.

This improves the light output retention rate of the nitride semiconductor light-emitting element1and extends the service life of the nitride semiconductor light-emitting element1.

The second feature of the invention is that, in the first feature, the electron blocking layer7comprises an undoped semiconductor layer

This makes it easier to reduce the second density D2.

The third feature of the invention is that, in the first or second feature, the ratio R further satisfies less than 15%.

This further extends the service life of the nitride semiconductor light-emitting element1.

The fourth feature of the invention is that, in the any one of the first to third features, a density of the pits10with a depth of not less than 2 nm on the upper surface70of the electron blocking layer7is not more than 1.0×1018pits/cm2.

This further extends the service life of the nitride semiconductor light-emitting element1.

The fifth feature of the invention is that, in the any one of the first to fourth features, the p-type semiconductor layer8comprises a p-type contact layer82comprising p-type GaN, and wherein a film thickness of the p-type semiconductor layer8is not more than 50 nm.

When the film thickness of the p-type contact layer82with a low A1 composition ratio is small, the service life of the nitride semiconductor light-emitting element1tends to be short unless special measures are taken. However, even when having such a configuration, the service life of the nitride semiconductor light-emitting element1can be extended by setting the ratio R to less than 30% as described above.

The sixth feature of the invention is that, in the any one of the first to fifth features, a film thickness of the electron blocking layer7is larger than a film thickness of each semiconductor layer of the active layer6.

This makes it easier to reduce the second density D2.

Additional Note

Although the embodiment of the invention has been described, the invention according to claims is not to be limited to the embodiment described above. Further, please note that not all combinations of the features described in the embodiment are necessary to solve the problem of the invention. In addition, the invention can be appropriately modified and implemented without departing from the gist thereof.