Solid-state image capturing apparatus and electronic information device

In a three-TR configuration pixel, the solid-state image capturing apparatus according to the present invention is capable of securing an electric potential difference sufficiently between a signal voltage and a reset voltage at the transferring of a signal charge and performing complete transferring of the signal charge from a photoelectric conversion element to an FD section easily and stably. Each pixel section, constituting a pixel array, has a 3TR configuration including reset transistors, transfer transistors and amplifying transistors. In each row of the pixel array, provided are a level shifter for driving reset drain wiring connected to a drain of the reset transistor, with an electric potential higher than a power supply voltage, and another level shifter for driving a reset signal line connected to a gate of the reset transistor, with an electric potential higher than the power supply voltage.

This nonprovisional application claims priority under 35 U.S.C. §119(a) to Patent Application No. 2009-123632 filed in Japan on May 21, 2009, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a solid-state image capturing apparatus and an electronic information device, and more particularly, to an amplification type solid-state image capturing apparatus, in which a pixel section includes an amplifier circuit, with improved performance, and an electronic information device including the amplification type solid-state image capturing apparatus used therein.

2. Description of the Related Art

Typically, a common amplification type solid-state image capturing apparatus includes a pixel array section in which pixel sections (also referred to simply as pixel) with amplification function are arranged in two dimensions, and a scanning circuit disposed in the periphery of the pixel array section, where the scanning circuit reads out pixel data from each pixel.

As an example of such an amplification type solid-state image capturing apparatus, APS (Active Pixel Sensor) type image sensors are publicly known. The APS type image sensors are configured with a CMOS circuit, which is advantageous for pixels to be integrated with a peripheral driving circuit and a signal processing circuit. Among such APS type image sensors, four-transistor type image sensors, which are able to obtain high quality images, have been becoming mainstream lately.

FIG. 5is a diagram describing a conventional four-transistor amplification type solid-state image capturing apparatus, illustrating a circuit configuration of an individual pixel (unit pixel) constituting the solid-state image capturing apparatus.

As illustrated inFIG. 5, a pixel section110, which constitutes the conventional amplification type solid-state image capturing apparatus, includes: alight receiving section101for converting light to electrons; a transferring transistor102for transferring a signal charge generated in the light receiving section101to a signal charge accumulation section103; an amplifying transistor105for amplifying the signal charge transferred to the signal charge accumulation section103to generate a signal voltage corresponding thereto; a reset transistor104for resetting the signal charge accumulation section103, that is, a gate of the amplifying transistor105, to a power supply voltage Vd; and a selecting transistor106for reading out an output of the amplifying transistor105to a read-out signal line107. In the solid-state image capturing apparatus, a plurality of pixel sections with such a configuration are arranged in two dimensions, that is, in rows and columns, to constitute a pixel array. The read-out signal line107is provided for each column of a pixel section in the pixel array (hereinafter, referred to as pixel column), and all the selecting transistors of the pixel in each pixel column are connected to corresponding read-out signal lines107. In addition, each read-out signal line107is connected a corresponding constant current source load111. The constant current source load111is configured of a transistor connected between one terminal side of the read-out signal line107and a ground, and a gate of the transistor is configured to allow a control signal SW (Vc) to be input.

Herein, the light receiving section101is typically constituted of buried photodiodes (photoelectric conversion elements). The transferring transistor102is connected between the signal charge accumulation section103and a cathode of the photodiode, the signal charge accumulation section103accumulating signal charges from the light receiving section101; and its gate is connected to a transfer gate selection line123. The signal charge accumulation section103is also referred to as a floating diffusion section (FD section)103hereinafter. The transferring transistor102is turned on when a voltage level TX of the transfer gate selection line123is at its high level, and transfers a signal charge generated at the photodiode to the signal charge accumulation section103.

In addition, the reset transistor104is connected between the signal charge accumulation section103and a voltage source (power supply voltage Vd), and its gate is connected to a reset signal line122. The reset transistor104is turned on when a voltage level RST of the reset signal line122is at its high level, and resets an electric potential of the signal charge accumulation section103to the power supply voltage Vd. Further, the amplifying transistor105and selecting transistor106are connected in series between the voltage source (power supply voltage Vd) and the read-out signal line107. A gate of the amplifying transistor105on the voltage source side is connected to the signal charge accumulation section103. In addition, a gate of the selecting transistor106on the read-out signal line side is connected in series to a selection signal line121. The selecting transistor106is turned on when a voltage level SEL of the selection signal line121is at its high level, and selects a corresponding pixel so that a signal voltage of the pixel is read out to the read-out signal line107.

Next, the operation of the amplification type solid-state image capturing apparatus will be described.

In the light receiving section101, a signal charge is generated by photoelectric conversion of incident light, and the signal charge generated at the light receiving section101is transferred to the signal charge accumulation section (FD section)103by the transferring transistor102. The signal charge accumulation section103is reset to the power supply voltage Vd by the reset transistor104prior to the transferring of the signal charge from the light receiving section101. Thus, the electric potential of the signal charge accumulation section103, at each time after resetting and transferring the signal charge, is amplified by the amplifying transistor105, and is read out to the read-out signal line107through the selecting transistor106. At this stage, the read-out signal line107is supplied with an electric current from the pixel110, in accordance with the electric potential of the signal charge accumulation section103, and the supplied electric current is discharged to the ground side through the constant current source load111. Thereby, a read-out voltage is generated in the read-out signal line107in accordance with the electric current supplied from the pixel110, and the read-out voltage is output to circuits in a later part to obtain pixel data of each pixel.

In such a CMOS image sensor, as a pixel pitch is miniaturized from 2.2 μm to 1.75 μm, problems will arise such as decreasing of the signal charge amount due to the downsizing of the photoelectric conversion element, that is, the photodiode, and increasing of noise due to the miniaturization of the amplification type MOS transistors. For that reason, it is more effective to reduce the number of the transistors to decrease the area occupied by the transistors and increase the size of the photoelectric conversion element, rather than miniaturizing the size of the transistors. For achieving such a method, proposed is a three-transistor type pixel configuration (3TR configuration) in which a photoelectric conversion element and three transistors constitute a unit pixel.

FIG. 6is a diagram describing a unit pixel of the 3TR configuration (hereinafter, referred to simply as pixel), illustrating a circuit configuration of two unit pixels connected to one read-out signal line.

For example, a 3TR configuration pixel section210includes: a light receiving section201consisting of photodiodes (photoelectric conversion elements); a signal charge accumulation section203for accumulating a signal charge from the light receiving section201; a transferring transistor202connected between the signal charge accumulation section203and the light receiving section201; a reset transistor204connected between the signal charge accumulation section203and reset drain wiring225; and an amplifying transistor205connected between a voltage source (power supply voltage Vd) and a read-out signal line207.

Herein, a gate of the transferring transistor202is connected with a transfer gate selection line223, and the transferring transistor202receives a transfer pulse signal TX0from the transfer gate selection line223to transfer a signal charge generated in the light receiving section201to the signal charge accumulation section203. In addition, a gate of the reset transistor204is connected with a reset signal line222, and the reset transistor204applies a voltage Vr0of the reset drain wiring225to the signal charge accumulation section203, based on by a reset signal RST0from the reset signal line222.

Further, similar to the 3TR configuration pixel section210described above, a 3TR configuration pixel section250includes: a light receiving section251consisting of photodiodes (photoelectric conversion element), for generating a signal charge by photoelectric conversion; a transfer transistor252for transferring the signal charge to a signal charge accumulation section253on the basis of a transfer pulse signal TX1from a transfer gate selection line273; a reset transistor254for applying a voltage Vr1of reset drain wiring275to the signal charge accumulation section253on the basis of a reset signal RST1from a reset signal line272; and an amplifying transistor255for amplifying and outputting the signal voltage or the reset voltage generated in the signal charge accumulation section253to the read-out signal line207.

The pixel sections210and250are connected to the read-out signal line207together with other pixel sections in the same column, and the read-out signal line207is connected to a constant current source load211. The constant current source load211is configured of a transistor connected between one terminal side of the read-out signal line207and a ground, and a gate of the transistor is configured to allow a control signal SW (Vc) to be input.

As illustrated inFIG. 6, unlike a 4TR configuration unit pixel section, the 3TR configuration unit pixel sections210and250are not provided with a transistor that corresponds to the selecting transistor connected in series with the amplifying transistor105as illustrated inFIG. 5. Thus, it is not a selecting transistor in a 4TR configuration that performs a pixel selecting operation of selecting a certain pixel from among a large number of pixels connected to the read-out signal line207, but the operation is performed by controlling an electric potential of the FD sections203and253, which function as a signal charge accumulation section.

Next, the operation of the 3TR configuration unit pixel will be described.

FIG. 7is a timing diagram illustrating one example of timing of driving pulses for driving a 3TR configuration unit pixel.

By controlling the transfer gate selection lines223and273, reset signal lines222and272, and reset drain wirings225and275, the voltages of the FD sections203and253are changed in each pixel section, and the voltage of the read-out signal line207is changed accordingly.

For example, in the case of selecting the pixel section210, the signal levels Vr0and Vr1of the reset drain lines225and275are set to a low-level electric potential (VL), and then the signal levels RST0and RST1of the reset signal lines222and272are raised and the electric potentials of the FD sections203and253are set to a low level (low reset).

Next, the constant current source load211of the read-out signal line207, which corresponds to a pixel column including the pixel210, is operated by raising the control signal SW of the transistor211that constitutes the constant current source load211(time t0). Thereafter, the electric potential Vr0of the reset drain wiring225, which is connected to the selected pixel section210, is set to a high level (time t1), so that only the electric potential FD0of the FD section203of the selected pixel section210switches to a high level. In this stage, the voltage (VFD) of the FD section203is defined as follows:
VFD=Vd−Vth(equation 1)

Herein, Vd denotes a power supply voltage, and Vth denotes a threshold voltage of the reset transistor204. Accordingly, the voltage VFD of the FD section203becomes lower than the power supply voltage Vd, which is a disadvantage for completing electric charge transferring. With regard to this problem, a transistor with a low threshold voltage or a depletion type transistor can be used as the reset transistor204, so that the voltage of the FD section203can be increased to almost as high as the power supply voltage, at the high reset time.

Thereafter, when the signal level RST0of the reset signal line222of the selected pixel section210is dropped (time t2), an electric potential FD0of the FD section203is dropped due to coupling capacitance C1between the gate of the reset transistor204and the FD section203. Further, the change in the electric potential FD0appears in the read-out signal line207through the amplifying transistor205, so that a voltage Vout of the read-out signal line207is also dropped, and the voltage VD0of the FD section203is further dropped due to coupling capacitance C2between the read-out signal line207and the gate of the amplifying transistor205.

Owing to the effect of the two kinds of coupling capacitance, the electric potential FD0of the FD section203becomes lower than the power supply voltage Vd. The voltage (reset level) Vout of the read-out signal line207is input to a next stage circuit (not shown) connected to the read-out signal line207, the voltage Vout corresponding to the electric potential FD0of the FD section203.

Thereafter, when the transfer gate pulse (transfer pulse signal) TX0is applied to the transferring transistor202(time t3to t4), the signal charge is transferred from the light receiving section201to the FD section203, causing the electric potential FD0of the FD section203to drop and the voltage level Vout of the read-out signal line207to drop simultaneously. The voltage Vout of the read-out signal line207is again input in the next stage circuit. The next stage circuit obtains the difference between a reset level Vrst and a signal level Vsig to output it as a pixel signal of the selected pixel210.

In addition, the signal level RST0of the reset signal line222is switched to a high level (time t5) and the electric potential FD0of the FD section203is switched to a high level, then the signal level of the reset drain wiring225is switched to a low level (time t6) and the electric potential of the FD section203is switched to a low level. Thereafter, the transistor211, which constitutes the constant current source load, is turned off (time t7).

During such reading-out of pixel signals from the selected pixel, the voltage level Vr1of the reset drain wiring275of a non-selected pixel section250is at a low level, and the signal level RST1of the reset signal line272is at a high level. Thus, the electric potential of the FD section253of the non-selected pixel section250is fixed to the low level, in which the electric potential of the FD section253is not changed even if the electric potential of the read-out signal line207is changed.

However, when such driving is performed, the voltage of the FD section203after the resetting is dropped due to the coupling capacitance C1between the gate of the reset transistor204and the FD section203and the coupling capacitance C2between the read-out signal line207and the gate of the amplifying transistor205. As a result, the electric potential difference cannot be secured sufficiently between the photoelectric conversion element (light receiving section)201and the FD section203when the transferring transistor202is turned on, which causes a problem of failing the complete transferring (no afterimage).

As a method for solving such a problem, Reference 1 discloses a method for boosting an electric potential of an FD section in a 3TR configuration pixel.

In the above method, it is necessary to set the width of a reset pulse for resetting the electric potential of the FD section shorter than a time for the read-out signal line207to follow the reset voltage of the FD section203.

That is, the electric potential of the FD section203is dropped due to the coupling capacitance C1with the gate of the reset transistor when the signal level RST0of the reset signal line222is raised after the voltage Vr0of the reset drain wiring225is raised and the FD section203reaches a reset level and before the read-out signal line207starts to follow. At this point, however, the read-out signal line207is in the middle of being raised, and therefore, the FD section203is boosted due to the coupling capacitance C2between the FD section203and the read-out signal line207. Thereby, the reset level of the FD section can be set high without the dropping of the electric potential of the FD section due to the coupling capacitance.

SUMMARY OF THE INVENTION

In the above method, however, due to the variation in response time required for the read-out signal line to follow the power supply voltage with respect to the reset pulse width, the difference in the response time of the read-out signal line depending on the position of the pixels, and the like, a problem of variation occurs in the reset electric potential of the FD section, resulting in failing the complete transferring of signal charges generated in the light receiving section.

The present invention is intended to solve the conventional problems described above. The objective of the present invention is to provide: a solid-state image capturing apparatus, in which an electric potential difference can be secured sufficiently between a photoelectric conversion element and a signal charge accumulation section when an electric potential of an FD is raised and a transferring transistor is turned on at a reset operation in a 3TR configuration pixel, the solid-state image capturing apparatus capable of facilitating complete transferring of signal charges from a photoelectric conversion element to a signal charge accumulation section as well as providing stable operations; and an electronic information device including the solid-state image capturing apparatus used therein.

A solid-state image capturing apparatus according to the present invention includes: a pixel array in which a plurality of pixels are arranged in two dimensions; and a read-out signal line disposed for each pixel column of the plurality of pixels for reading out a signal charge from each of the pixels in each pixel column, wherein each of the pixels is configured to include: a photoelectric conversion element for photoelectrically converting incident light; a signal charge accumulation section for accumulating a signal charge obtained by the photoelectric conversion; a transferring transistor for transferring the signal charge from the photoelectric conversion element to the signal charge accumulation section; a reset transistor for resetting an electric potential of the signal charge accumulation section to a reference voltage; and an amplifying transistor for amplifying and reading out the electric potential of the signal charge accumulation section to the read-out signal line, and wherein a voltage supplying section supplies a voltage greater than an absolute value of a power supply voltage to the reset transistor of the pixel array, as a driving voltage thereof, so that an absolute value of a reference voltage, which is a reset electric potential of the signal charge accumulation section, becomes greater than the absolute value of the power supply voltage, thereby achieving the objective described above.

Preferably, in a solid-state image capturing apparatus according to the present invention, the reset transistor includes: a drain which is connected with reset drain wiring; and a source which is connected with the signal charge accumulation section; and the voltage supplying section includes: a wiring driver for driving the reset drain wiring; and a first boosting circuit for supplying a boosted voltage to the wiring driver, the boosted voltage being obtained by boosting the power supply voltage.

Still preferably, in a solid-state image capturing apparatus according to the present invention, the first boosting circuit is a charge pump circuit.

Still preferably, iva solid-state image capturing apparatus according to the present invention, the reset transistor is a depletion type transistor.

Still preferably, in a solid-state image capturing apparatus according to the present invention, the voltage supplying section includes: a gate driver for driving a gate electrode of the reset transistor; and a second boosting circuit for supplying a boosted voltage to the gate driver, the boosted voltage being obtained by boosting the power supply voltage.

Still preferably, in a solid-state image capturing apparatus according to the present invention, the second boosting circuit generates a voltage with an electric potential, which is equal to the voltage that is generated in the first boosting circuit and is higher than the power supply voltage.

Still preferably, in a solid-state image capturing apparatus according to the present invention, the second boosting voltage is a charge pump circuit.

Still preferably, a solid-state image capturing apparatus according to the present invention further includes a controlling section for selecting a pixel in the pixel column by controlling an electric potential of the signal charge accumulation section of the pixel to be selected in the pixel column.

Still preferably, in a solid-state image capturing apparatus according to the present invention, the controlling section selects a pixel in the pixel column by turning on the reset transistor of the pixel to be selected in the pixel column and by boosting the voltage of the reset drain wiring to be higher than the power supply voltage, the reset drain wiring being connected with the reset transistor of the pixel to be selected.

Still preferably, in a solid-state image capturing apparatus according to the present invention, the photoelectric conversion element is a buried photodiode.

Still preferably, a solid-state image capturing apparatus according to the present invention further includes a constant current source provided for each pixel column and connected with a read-out signal line of each corresponding pixel column.

Still preferably, in a solid-state image capturing apparatus according to the present invention, the constant current source includes a MOS transistor connected between the read-out signal line and a ground, the MOS transistor operating to flow a constant current to the read-out signal line in a state where a pixel column corresponding to the read-out signal line is selected.

An electronic information device according to the present invention includes an image capturing section for capturing an image of a subject, wherein the image capturing section is the solid-state image capturing apparatus according to the present invention, thereby achieving the objective described above.

The functions of the present invention will be described hereinafter.

According to the present invention, the solid-state image capturing apparatus includes a pixel array in which pixel sections are arranged in two dimensions, each pixel including at least: a photoelectric conversion element; a transferring transistor for transferring a signal charge from the photoelectric conversion element; a reset transistor for resetting an electric potential of an electric charge accumulation section; and an amplifying transistor for amplifying and reading out the electric potential of the electric charge accumulation section, source side of which is connected to a signal line. In the solid-state image capturing apparatus, a voltage supplying section is provided to supply a high voltage, which is higher than a power supply voltage, to a drain section of a reset transistor of the pixel array, thereby securing an electric potential difference sufficiently between a signal voltage and a reset voltage at the transferring of the signal charge and performing complete transferring of the signal charge from the photoelectric conversion element to an FD section easily and stably.

Further, according to the present invention, the high voltage supplying section is a charge pump circuit. Thus, the controlling of the operation of the charge pump circuit makes it possible to raise an electric potential supplied to the reset transistor of the pixel array to a desired electric potential.

Still further, according to the present invention, the reset transistor is a depletion type transistor. Thus, it becomes possible to prevent a reset voltage supplied through the reset transistor to a signal charge accumulation section from being lowered due to a threshold voltage of the reset transistor.

Still further, according to the present invention, a high voltage, which is higher than a power supply voltage, is applied to a gate electrode of the reset transistor, as to a reset drain section. Thus, it becomes possible to securely turn on the reset transistor in which an electric potential higher than the power supply voltage is supplied to a drain thereof.

Still further, according to the present invention, a constant current source is provided for each pixel column, the constant current source being connected to a read-out signal line of a corresponding pixel column. The constant current source is configured to include a MOS transistor connected between the read-out signal line and a ground, in which the MOS transistor operates to flow a constant current to the read-out signal line in a state where a pixel column corresponding to the read-out signal line is selected. Thus, it becomes possible to cut electricity that is consumed in the constant current source in a state where a pixel column corresponding to the read-out signal line is not selected.

According to the present invention with the details above, a voltage higher than a power supply voltage is applied to reset drain wiring and a gate electrode of the reset transistor, so that an electric potential difference can be secured sufficiently between the photoelectric conversion element and the FD section, thereby performing complete electric charge transferring from the photoelectric conversion element to the FD section, that is, electric charge transferring with no after image.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a diagram illustrating an amplification type solid-state image capturing apparatus according to Embodiment 1 of the present invention,FIG. 1(a) schematically illustrating an overall structure of the solid-state image capturing apparatus andFIG. 1(b) illustrating a circuit configuration of a 3TR configuration pixel in the solid-state image capturing apparatus.

An amplification type solid-state image capturing apparatus10according to Embodiment 1 includes a pixel array10ain which 3TR configuration pixel sections (hereinafter, also referred to as pixel) are arranged in two dimensions; and a controlling section10bdisposed in the periphery of the pixel array10afor controlling the pixel array10a.

As similar to a conventional pixel, a 3TR configuration pixel section410in the amplification type solid-state image capturing apparatus10includes: alight receiving section401for converting light to electrons; a transferring transistor402, in which a transfer gate selection line423is connected to a gate thereof, for transferring a signal charge generated in the light receiving section401to a signal charge accumulation section403; an amplifying transistor405for amplifying the level of the signal charge transferred to the signal charge accumulation section403to generate a signal voltage corresponding thereto; and a reset transistor404for resetting the signal charge accumulation section403to a reset electric potential Vh, which is higher than a power supply voltage Vd, and in which a reset signal line422is connected to a gate thereof.

Herein, the light receiving section401is typically constituted of a buried photodiode (photoelectric conversion element). The transferring transistor402is connected between a cathode of the photodiode and the signal charge accumulation section403. Reset drain wiring425is connected to a drain of the reset transistor404, and a source of the reset transistor404is connected to the signal charge accumulation section403. A gate of the amplifying transistor405is connected to the signal charge accumulation section403. Note that the signal charge accumulation section403is also referred to as a floating diffusion section (FD section), hereinafter.

In addition, as similar to the 3TR configuration pixel410, a 3TR configuration pixel450includes: a photodiode (photoelectric conversion element)451for generating a signal charge by photoelectric conversion; a transferring transistor452for transferring the signal charge to a signal charge accumulation section453; a reset transistor454for applying a reset voltage to the signal charge accumulation section453; and an amplifying transistor455for amplifying and outputting a signal voltage or reset voltage generated in the signal charge accumulation section453to a read-out signal line407. Herein, a transfer gate selection line473is connected to a gate of the transferring transistor452, a reset signal line472is connected to a gate of the reset transistor454, and reset drain wiring475is connected to a drain of the reset transistor454.

The pixels410and450are connected to the read-out signal line407together with other pixels in the same column, and the read-out signal line407is connected to a constant current source load411. The constant current source load411is constituted of a transistor which is connected between one terminal side of the read-out signal line407and a ground, and a gate of the transistor is configured to allow a control signal SW (Vc) to be input. In addition, the reset transistors404and454described above are desirably depletion type transistors.

Further, in Embodiment 1, a source section of the amplifying transistor405is connected to the read-out signal line407and a source section of the amplifying transistor455in the separate pixel section450is also connected to the read-out signal line407. In addition, the constant current source load411is connected to a terminal section of the read-out signal line407. Note that each drain of the amplifying transistors405and455is connected to the power supply voltage Vd through wiring430.

Additionally in Embodiment 1, an N-type MOS transistor is used for the transferring transistor, reset transistor and amplifying transistor, all of which constitute the pixel.

Further in Embodiment 1, the controlling section10bincludes a row selection circuit for selecting a pixel row in the pixel array.

FIG. 2is a diagram illustrating a specific configuration of a row selection circuit.

For example, a row selection circuit corresponding to the pixel section410includes: a level shifter521for driving the reset drain wiring425with a reset drain controlling signal VR_IN0; and a level shifter522for driving the reset signal line422with a reset controlling signal RST_IN0. The level shifters521and522are configured to be capable of receiving a voltage Vh, which is higher than the power supply voltage, from an outside boosting circuit520to apply the voltage Vh to reset drain wiring and reset wiring, the voltage Vh being higher than the power supply voltage. Herein, a circuit, such as a charge pump circuit, is used as the boosting circuit. In addition, the boosting circuit for supplying a voltage Vh higher than the power supply voltage to the level shifter521and the boosting circuit for supplying a voltage Vh higher than the power supply voltage to the level shifter522may be separate first and second boosting circuits. In such a case, a charge pump circuit may be used for the first and second boosting circuits. Further, the voltages, which are generated in the first and second boosting circuits and which are higher than the power supply voltage, may be at the same voltage level or at different voltage levels.

Next, the operation of the amplification type solid-state image capturing apparatus will be described.

FIG. 3is a timing diagram illustrating an operation of the amplification type solid-state image capturing apparatus according to Embodiment 1 of the present invention.

First, at the time t0, when the constant current source load411is operated, reset gates are turned ON and electric potentials Vr0and Vr1of the reset drains are at a low level (VL) in all the pixels, all the FD electric potentials are at a low level (VL), and the selection of a pixel section is not made for a read-out target (low reset state).

At time t1, the electric potential of the FD section (FD0) is changed from VL to Vh by changing the electric potential Vr0of the reset drain wiring425, which is connected to the selected pixel section410, from the low level to the high level. At this stage, the electric potential Vr1of the reset drain wiring475, which is connected to the non-selected pixel section450, remains to be VL.

At this stage, the voltage Vh, which is higher than the power supply voltage Vd, is applied to the drain of the reset transistor404by the level shifter521, and the voltage Vh, which is higher than the power supply voltage Vd, is applied to the gate of the reset transistor404by the level shifter522, so that the voltage of the FD section can be set to the voltage Vh.

At time t2, when an electric potential RST0of the reset signal line connected to the selected pixel section is dropped from the high level to the low level, the electric potential of the FD section is dropped lower than the Vh level due to coupling capacitance C1. In accordance with the dropping of the electric potential in the FD section, an electric potential Vout of the read-out signal line407is also dropped due to coupling capacitance C2. However, since the above Vh level is a voltage higher than the power supply voltage Vd, the electric potential of the FD section which is higher than the power supply voltage can be maintained even if the electric potential of the FD section is dropped due to the coupling capacitance C1. In addition, at this stage, the electric potential Vout of the signal line is input in a next stage circuit as a reset level Vrst.

At time t3, when the transferring transistor402is turned ON and the electric charges accumulated in the light receiving section401are transferred to the FD section403, the electric potential FD0of the FD section is dropped and the electric potential of the read-out signal line407is dropped. At this stage, the electric potential of the FD section is higher than the power supply voltage, so that the complete transferring can be easily performed.

At time t4, the transferring transistor402is turned OFF and the signal level (Vsig) is again input to the next stage circuit. The next stage circuit obtains the difference between the reset level and the signal level to output it as a pixel signal.

At time t5, the electric potential RST0of the reset gate wiring is changed from the low level to the high level, so that the electric potential FD0of the FD section is switched to the high voltage level Vh. At time t6, the reset drain wiring Vr0is switched to the low level, so that the electric potential FD0of the FD section is dropped to the VL level, which means to be a low reset level.

Thereafter, the transistor411constituting the constant current source load is turned OFF (time t7).

In the above description, a case is explained where the pixel section410is the selected pixel section and the pixel section450is the non-selected pixel section. In a case where the pixel section410is the non-selected pixel section and the pixel section450is the selected pixel section, a pixel signal is read out from the pixel section450as similar to the case where the pixel section410is selected.

In Embodiment 1 as described above, the pixel sections410and450are configured as a 3TR circuit configuration including: reset transistors404and454for resetting the electric potential of the signal charge accumulation section403; transferring transistors402and452for transferring the signal charge generated in the light receiving section401to the signal charge accumulation section403; and amplifying transistors405and455for amplifying and outputting the electric potential of the signal charge accumulation sections403and453to the read-out signal line407. At the same time, the pixel sections410and450includes: the level shifter521as a driving circuit provided for each row in the pixel array for driving the reset drain wiring; and the level shifter522as a driving circuit provided for each row in the pixel array for driving the reset wiring. Further, the voltage Vh, which is higher than the power supply voltage, is supplied to the level shifters from the boosting circuit, such as a charge pump circuit, to raise the high level electric potential of the reset drain wiring and reset signal line. As a result, it becomes possible to maintain the voltage of the FD section at the high level even if the reset voltage of the signal charge accumulation section (FD section) is dropped due to the turning off of the reset transistor. Thereby, in the 3TR configuration pixel, the reset electric potential of the FD section is maintained high and the electric potential difference is secured sufficiently between the photoelectric conversion element and the FD section, and as a result, it becomes possible to obtain an amplification type solid-state image capturing apparatus, which is capable of facilitating complete transferring of signal charges (no afterimage) from the photoelectric conversion element to the signal charge accumulation section as well as providing stable operation.

Additionally in Embodiment 1, the charge pump circuit is used for the circuit for supplying a voltage higher than the power supply voltage to the level shifters, so that it becomes possible to raise the electric potential, which is supplied to the reset transistor in the pixel array, to a desired electric potential.

Additionally in Embodiment 1, the reset transistor is set to be a depletion type transistor, so that it becomes possible to prevent the reset voltage supplied through the reset transistor to the signal charge accumulation section from being lowered due to the threshold voltage of the reset transistor.

Additionally in Embodiment 1, a high voltage, which is higher than the power supply voltage, is applied to the gate electrode of the reset transistor, as to the reset drain section, so that it becomes possible to securely turn on the reset transistor in which an electric potential higher than the power supply voltage is supplied to the drain thereof.

Additionally in Embodiment 1, the constant current source is provided for each pixel column, the constant current source being connected to the read-out signal line of a corresponding pixel column. The constant current source is configured to include the MOS transistor411connected between the read-out signal line and a ground, in which the MOS transistor411operates to flow a constant current to the read-out signal line in a state where a pixel column corresponding to the read-out signal line is selected. Thus, it becomes possible to cut electricity that is consumed in the constant current source in a state where a pixel column corresponding to the read-out signal line is not selected.

In Embodiment 1, although an N-type MOS transistor is used for the transistors constituting the pixel, the transistors constituting the pixel may also be a P-type MOS transistor. In such a case, the polarity of the voltage supplied to each transistor is a reversed polarity from the one in Embodiment 1.

Further, although not specifically described in Embodiment 1, an electronic information device having an image input device will be described hereinafter. The electronic information device, such as a digital camera (e.g., digital video camera and digital still camera), an image input camera, a scanner, a facsimile machine or a camera-equipped cell phone device, includes an image capturing section with the solid-state image capturing apparatus according to Embodiment 1 described above used therein.

FIG. 4is a block diagram schematically illustrating an exemplary configuration of an electronic information device, as Embodiment 2 of the present invention, including the solid-state image capturing apparatus according to Embodiment 1 of the present invention used in an image capturing section thereof.

The electronic information device90according to Embodiment 2 of the present invention as illustrated inFIG. 4includes the solid-state image capturing apparatus according to Embodiment 1 of the present invention as an image capturing section91for capturing a subject. The electronic information device90further includes at least any of: a memory section92(e.g., recording media) for data-recording a high-quality image data obtained by an image capturing section after a predetermined signal process is performed on the image data for recording; a display section93(e.g., liquid crystal display device) for displaying this image data on a display screen (e.g., liquid crystal display screen) after a predetermined signal process is performed for display; a communication section94(e.g., transmitting and receiving device) for communicating this image data after a predetermined signal process is performed on the image data for communication; and an image output section95for printing (typing out) and outputting (printing out) this image data.

As described above, the present invention is exemplified by the use of its preferred Embodiments 1 and 2. However, the present invention should not be interpreted solely based on Embodiments 1 and 2 described above. It is understood that the scope of the present invention should be interpreted solely based on the claims. It is also understood that those skilled in the art can implement equivalent scope of technology, based on the description of the present invention and common knowledge from the description of the detailed preferred Embodiments 1 and 2 of the present invention. Furthermore, it is understood that any patent, any patent application and any references cited in the present specification should be incorporated by reference in the present specification in the same manner as the contents are specifically described therein.

INDUSTRIAL APPLICABILITY

The present invention can be applied in the field of a solid-state image capturing apparatus and an electronic information device. According to the present invention, particularly as an amplification type solid-state image capturing apparatus including pixels with an amplification function, it is possible to provide an amplification type solid-state image capturing apparatus, which is capable of securing an electric potential difference sufficiently between a signal voltage and a reset voltage at the transferring of a signal charge, and capable of facilitating complete transferring of signal charges from a photoelectric conversion element to an FD section as well as providing stable operation. In addition, it is possible to provide an electronic information device including such a solid-state image capturing apparatus used therein.