Organic memory array with ferroelectric field-effect transistor pixels

An organic non-volatile memory array including multiple pixels and associated signal lines that are disposed on and between a substrate, a single ferroelectric dielectric layer, and a single organic dielectric layer, where each pixel includes a ferroelectric field-effect transistor (FeFET) and at least one organic thin-film field effect transistor (FET) that are connected to associated signal lines in a way that facilitates addressable reading and writing to the FeFET of a selected pixel without disturbing the data stored in adjacent pixels. Analog data storage in the FeFET array is also introduced that does not require analog-to-digital conversion of the stored data.

FIELD OF THE INVENTION

Background of the Invention

Semiconductor memories are configured as either read-only memories (ROM) such as EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable ROM), flash ROM or as volatile, random access memories (RAM) such as SRAM (Static RAM) and DRAM (Dynamic RAM). The processing required to produce these memory types are complicated and the necessary facilities are expensive due to the high temperature processing required. Ferroelectric ceramic random access memories and field effect transistor memories can be configured to be both read-write and nonvolatile, but again the processing conditions require processing at temperatures in excess of about 600° C. Furthermore, these silicon-based or ferroelectric ceramic-based memories are expensive as the inorganic raw materials used are expensive when compared to many organic materials in addition to the high costs involved in the processing.

Ferroelectric materials possess the unique properties of a spontaneous polarization which can be re-oriented with an applied field, and that the polarization state can be retained even after the removal of electric field. Hence ferroelectric materials can contain two data states (“+” and “−” polarization states) which are very stable over a variety of environmental conditions. These properties allow ferroelectric materials to be one of the best materials for production of digital computer memories. Research activities on ferroelectric-based computer memories commenced in the 1950s, just following the appearance of computers. However, because these early researches focused on using bulk ferroelectric materials which required very high applied voltages to be used to re-orient the polarization, the research activities were discontinued and no commercial products developed.

In the 1980s, with the advances of ferroelectric thin film deposition technology and integration of ferroelectric thin films with silicon microelectronics, practical ferroelectric memories were developed and commercial products were introduced in the market. These advances allowed for the manufacture of ferroelectric thin film based memories which use a standard 5V or 3V voltage to re-orient the polarization or that is, to read and write data. These ferroelectric random access memories (FRAM) combine the advantages of read-on memories (ROM) and volatile random access memories. FRAM have the same advantages of DRAM and SRAM in that they are easy to write, but are superior to DRAM and SRAM due to their nonvolatility. That is, FRAM store the data even in the absence of power. FRAM also have the same advantages of EPROM, EEPROM and Flash ROM in that they are easy to read, but are superior to EPROM and EEPROM as the write speed of FRAM is much faster than that of EPROM, EEPROM and Flash ROM as well as having a higher number of allowed write cycles. However, FRAM does have one major drawback: FRAMs exhibit destructive readout. That is, in order to determine if the polarization of the ferroelectric thin film cell is positive (e.g., representing a “0”) or negative (e.g., representing a “1”), a positive (or a negative) pulse is applied to the cell. The induced charge will be significantly different between positively and negatively polarized ferroelectric cells. However, if the original state of the ferroelectric cell was a negative polarization state, it will change to positive polarization state after reading via a positive pulse being applied to the cell. Likewise, if the original state of the ferroelectric cell was a positive polarization state, it will change to negative polarization state after reading via a negative pulse being applied to the cell. This destructive readout requires that each read access be accompanied by a pre-charge operation to restore the memory state.

In order to solve the destructive readout problem, ferroelectric thin film-based field effect transistors (FETs) have been proposed as the next-generation ferroelectric memories. The ferroelectric FETs use a ferroelectric thin film as a gate dielectric. The ferroelectric thin film is deposited on a silicon substrate, either with or without a thin dielectric layer such as silicon dioxide (SiO2) or silicon nitride (Si3N4) between the silicon substrate and the ferroelectric thin film. When a gate voltage is applied, the polarization of the ferroelectric thin film can be either positive or negative and the polarization state can be retained after the removal of gate voltage. This positive or negative polarization can affect the source-drain current or the source-drain resistance. As the source-drain current or resistance can be controlled by the polarization state of the ferroelectric thin film, a single ferroelectric FET can be used as a memory cell. It can be seen that the ferroelectric FET memory cells have all the advantages of FRAM, such as nonvolatility, easy to read and write, lower power consumption, plus the additional advantage of a nondestructive readout. Furthermore, FRAMs utilizing ferroelectric thin films have a larger remnant polarization (usually larger than 10 μC/cm2), while a remnant polarization of at the order of one-tenth μC/cm2can effectively change the source-drain current in ferroelectric FET memories.

Until recently, all ferroelectric FET memory cells used ferroelectric ceramic thin films such as lead zirconate titanate (PZT) or strontium bismuth tantalate (SrBi2Ta2O9or SBT) with Si-based semiconductors. Therefore, both to deposit the ferroelectric film and to make the FET requires high temperature processes with temperatures in excess of about 600° C. A research group in France has demonstrated (G. Velu, C. Legrand, O. Tharaud, A. Chapoton, D. Remiens, and G. Horowitz, Appl. Phys. Lett, 79, 659, 2001) the memory effect of a ferroelectric FET using PZT thin film as gate dielectric and α6T (sexithiophene) organic thin film transistor. The deposition of α6T organic thin film can be done at 100° C., but the preparation of PZT film needs a post annealing treatment at 625° C.

In contrast to ferroelectric ceramic thin films, ferroelectric polymer thin films, such as in the family of poly(vinyidiene-trifluoroethylene) (P(VDF-TrFE)) copolymers can be easily deposited on silicon or other substrates using solution spin coating, casting, evaporation or Langmuir-Blodgett (LB) growth method, with the growth temperature lower than 200° C. The remnant polarization of these polymer thin films can be higher than 40 mC/m2, or 4 μC/cm2, which is large enough to change the source-drain current and suitable for use in a ferroelectric memory device. Thus organic, nonvolatile, nondestructive readout ferroelectric memory cells can be developed by combining ferroelectric polymer thin film technology and organic thin film transistor technology.

U.S. Pat. No. 6,812,509 (Xu) discloses organic ferroelectric memory cells having field effect organic transistors that are formed using a ferroelectric thin film polymer as the gate dielectric. Xu teaches that by controlling the gate voltage to polarize the thin film ferroelectric polymer polarized in either an “up” or “down” state, the source-drain current can be controlled between two different values under the same source-drain voltage. The source-drain current thus can be used to represent either a “0” or “1” state. Xu teaches using various organic thin films and ferroelectric thin films to form his cells. As the deposition of these organic thin films can be done at temperatures below 200° C., the memory cells can be made on many kinds of substrates including plastics.

Although Xu teaches structures associated with individual cells, Xu does not address the arrangement of cells to form an array of memory cells that can be used in organic electronic devices to store large amounts of data. Thus, what is needed is a memory array including FeFET-based pixels (cells) that can be formed using low cost organic electronic fabrication techniques for applications such as radio frequency identification (RFID) devices and integrated sensor data logger devices, in which read and write operations directed to selected pixels do not disturb data stored in surrounding pixels.

SUMMARY OF THE INVENTION

The present invention is directed to a non-volatile memory array in multiple pixels and associated signal lines are disposed on and between a substrate, a single organic dielectric layer, and a single ferroelectric dielectric layer, wherein each of the pixels includes a ferroelectric field-effect transistor FeFET and at least one organic thin-film field effect transistor (FET) that are connected to associated signal lines in a way that facilitates addressable reading and writing to the FeFET of each pixel without disturbing the data stored in adjacent pixels. By forming the array utilizing only two (i.e., ferroelectric and organic) dielectric layers and utilizing well-established low cost organic electronic fabrication methods (e.g., ink jet printing), the present invention facilitates the production of low cost, low voltage organic electronic devices such as radio frequency identification (RFID) devices and integrated sensor data logger devices that require large amounts of memory.

According to an embodiment of the present invention, 2T pixels are disclosed in which an organic “write” FET is utilized to selectively pass write pulse signals to the gate electrode of the pixel's FeFET, thereby polarizing the ferroelectric material disposed in the channel of the FeFET in order to store data. Subsequent read operations are performed by supplying a read current to the source of the FeFET, and measuring the source-drain current passing through the FeFET. To isolate the selected FeFET, the read current is supplied on a “row” signal line, and the source-drain current is transmitted on a “column” signal line that is orthogonal to the row signal line. Various disclosed alternative embodiments utilize ink jet printed electrode and semiconductor structures disposed between the substrate, the ferroelectric dielectric material layer and the organic dielectric material layer to form the desired 2T structures.

According to another embodiment of the present invention, 3T pixels are disclosed in which both an organic “write” FET and an organic “read” FET is utilized to selectively write and read data stored on the pixel's FeFET. Read operations are performed by supplying a read current on a row signal line to the source of a selected FeFET by turning on that pixel's read FET, and measuring the resulting source-drain current on the row signal line. To isolate other (non-selected) FeFETs coupled to the row signal line, the read FETs associated with the non-selected pixels are turned off. Various disclosed alternative embodiments utilize ink jet printed electrode and semiconductor structures disposed between the substrate, the ferroelectric dielectric material layer and the organic dielectric material layer to form the desired 3T structures.

According to another embodiment of the present invention, the disclosed memory arrays are utilized to store analog data without using analog-to-digital circuits to store different values of input voltage, thereby facilitating the production of low-cost organic electronic devices.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention relates to an improvement in organic electronics. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. As used herein, directional terms such as “upper”, “upwards”, “lower”, “downward”, “front”, “rear”, are intended to provide relative positions for purposes of description, and are not intended to designate an absolute frame of reference. The terms “coupled” and “connected”, which are utilized herein, are defined as follows. The terms “connected” and “electrically connected” is used to describe a direct connection between two circuit elements, for example, by way of a metal line or via structure foamed in accordance with normal integrated circuit fabrication techniques. In contrast, the term “coupled” is used to describe either a direct connection or an indirect connection between two circuit elements. For example, two coupled elements may be directly connected by way of a metal line, or indirectly connected by way of an intervening circuit element (e.g., a capacitor, resistor, inductor, or by way of the source/drain terminals of a transistor). Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

FIG. 1is a simplified diagram depicting a portion of a generalized organic memory array100that is formed in accordance with an embodiment of the present invention. Memory array100is formed on a substrate101, and generally includes a first dielectric layer110disposed on the substrate, and a second dielectric layer120disposed on the first dielectric layer, and multiple memory pixels150(four shown) and associated control and interconnect structures that are formed by metal electrode and line structures and semiconductor structures, which are described in additional detail below.

According to an aspect of the invention, one of dielectric layers110and120consists entirely of a ferroelectric dielectric material, and the other of dielectric layers110and120consists entirely of an organic dielectric material. Both dielectric layer110and120are formed on using low cost blanket deposition techniques such that each layer forms a substantially continuous sheet over the entirety of substrate101. As set forth in the specific examples described below, the various TFT and interconnect structures introduced inFIG. 1are formed on or between the various material layers, and the order in which the ferroelectric and organic dielectric layers are deposited may be reversed. For example, in one set of embodiments below, first dielectric layer110consists of a ferroelectric dielectric material layer that is formed on an upper surface of substrate101, and second dielectric layer120consists of an organic dielectric material layer that is formed on an upper surface of first dielectric layer110. In other embodiments, first dielectric layer110consists of an organic dielectric material layer that is formed on an upper surface of substrate101, and second dielectric layer120consists of a ferroelectric dielectric material layer that is formed on an upper surface of first dielectric layer110.

According to an embodiment of the present invention, substrate101of organic memory array100consists of flexible polymer foil such as polycarbonate, poly(ethylene terephthalate), polyimide, and poly(ethylene naphthalate), or rigid glass having thickness in the range of 100 micron to 800 micron. Alternatively, silicon wafers and silicon oxide grown on silicon wafers have been widely used as substrates and gate dielectric to make organic thin film FETs. Organic thin film FETs have also been built using gate dielectrics such as parylene, polyimide, polyvinyl alcohol (PVA), polyvinyl chloride (PVC), and polymethylmethacrylate (PMMA) as described in X. Peng, G. Horowitz, D. Fichiou, and F. Garnier, Appl. Phys. Lett., 57, 2013, 1990; Z. Bao, Y. Fang, A. Dodabalapur, V. R. Raju, and A. J. Lovinger, Chem. Mater., 9, 1299, 1997.

According to an embodiment of the present invention, the ferroelectric dielectric material layer of organic memory array100consists of poly(vinyidiene-trifluoroethylene) (P(VDF-TrFE)) copolymers having thickness in the range of 50 nm to 1000 nm. Alternatively, several candidate ferroelectric polymer materials can be used, including but not limited to poly(vinylidene fluoride) (PVDF), odd-numbered nylons, cyanopolymers, polyureas and polythioureas. Thin films of these polymers can be produced by solution spin coating or solution casting, Langmuir-Blodgett (LB) monolayer growth method, and vapor deposition polymerization process. Typically these deposition processes can be done below 200° C. A typical process to produce P(VDF-TrFE) copolymer thin films by solution spin coating method has been described in Q. M. Zhang, H. Xu, F. Fang, Z. Y. Cheng, F. Xia, and H. You, J. Appl. Phys., 89, 2613, 2001. The steps in this typical process include first dissolving P(VDF-TrFE) copolymers in the composition range from 50/50 to 80/20 mol % in dimethylformide (DMF) or 2-butanone, with a resulting concentration ranging from 4 wt % to 12 wt %. Then the solution is used in a spin coating process to provide a film. It is well known in the art that films with various thicknesses can be obtained by controlling the spin conditions and/or using a process which uses multiple coating procedure. Finally the films are annealed at 140° C. under vacuum to remove the residual solvent and to improve the crystallization. This process can obtain films with a thickness between 50 nm to more than 1 μm and remnant polarization of more than 40 mC/m2. An alternative process uses the Langmuir-Blodgett deposition method to obtain P(VDF-TrFE) 70/30 copolymer films, with thickness of 5000 angstroms to 5 μm.

According to an embodiment of the present invention, the semiconductors of organic memory array100consists of a polythiophene polymer and a polymer blend (e.g., PQT, Flexink) having thickness in the range of 5 nm to approximately 200 nm. There are several alternative organic semiconductor thin film materials that can be used in memory array100, including but are not restricted to poly(phenylenes), thiophene oligomers, pentacene, and perfluoro copper phthalocyanine, perylene. While a wide variety of organic semiconductor thin films materials are suitable, it is believed that those materials with high mobility or high current modulation Ion/Ioffare preferred as the source-drain current of such materials is more sensitive to an applied gate voltage. It is believed that the higher sensitivity to an applied gate voltage will result in improved read/write characteristics. The thickness of the organic semiconductor thin films can be in the range of approximately 5 nm to approximately 200 nm, with preferably a thickness of approximately 50 nm.

Referring again toFIG. 1, according to an aspect of the present invention, each pixel150includes a ferroelectric field effect transistor (FeFET)160and an organic thin-film field effect transistor (organic FET)170that are connected to associated signal lines WL1-WL4and BL1-BL4. FeFET160, organic FET170and signal lines WL1-WL4and BL1-BL4are formed by thin film structures (e.g., metal and/or organic semiconductor) that are deposited by ink jet or other printing techniques on one of substrate101and layers110and120using known techniques, thereby minimizing manufacturing costs.

As indicated on layer120ofFIG. 1, ferroelectric field effect transistor (FeFET)160includes a (first) source electrode162connected to signal line WL2, a (first) drain electrode164connected to signal line BL2, and a (first) gate electrode168. As indicated in the partial perspective diagram at the upper right ofFIG. 1, FeFET160is formed on ferroelectric dielectric material layer130, which makes up one of dielectric layer110and120(shown in the structure shown at the bottom ofFIG. 1). Source electrode162and drain electrode164are formed by separate thin film metal structures that are printed onto a first (e.g., upper) surface131of ferroelectric dielectric material layer130, and gate electrode168is formed by another thin film metal structures that is disposed on a second (e.g., lower) surface132of ferroelectric dielectric material layer130(i.e., gate electrode168is either printed onto surface132, or is printed onto substrate101when ferroelectric dielectric material layer130is implemented as first dielectric layer110, or printed onto first dielectric layer110when ferroelectric dielectric material layer130is implemented as second dielectric layer120). Source electrode162and drain electrode164are separated by a gap, and a portion of ferroelectric dielectric layer130disposed under this gap defines a (first) channel region165of FeFET160. A (first) organic semiconductor portion166is disposed on surface131over channel region165, and gate electrode168is disposed on surface132below channel region165. Note that the structure depicted inFIG. 1may be reversed such that “upper” surface131faces substrate101, and “lower” surface132faces away from substrate101, whereby gate electrode168is disposed over organic semiconductor portion166.

Referring again to the lower part ofFIG. 1, organic FET170includes a (second) source electrode172connected to signal line BL1, a (second) drain electrode174connected to source region162of FeFET160, and a (second) gate electrode178that is connected to signal line WL1. As indicated in the partial perspective diagram at the upper left portion ofFIG. 1, organic FET170is formed on organic dielectric material layer140, which is implemented by one of dielectric layers110and120. Source electrode172and drain electrode174are formed by separate thin film metal structures that are printed onto a first (e.g., upper) surface141of organic dielectric material layer140, and gate electrode178is formed by another thin film metal structures that is disposed on a second surface142of organic dielectric material layer130. Source electrode172and drain electrode174are separated by a gap, and a portion of organic dielectric layer140disposed under this gap defines a (second) channel region175of organic FET170. A (second) organic semiconductor portion176is disposed on surface141over channel region175, and gate electrode178is disposed below channel region175. Note that the structure depicted inFIG. 1may be reversed.

The various electrodes (e.g., source electrodes162and172) and signal lines associated with memory array100are preferably formed by printing silver ink using an ink jet printer according to known techniques. However, in alternative embodiments, these conductive structures may be formed by evaporated or sputtered metal electrodes such as gold, platinum, or aluminum, evaporated or printed conducting oxides such as Indium-Tin oxide (ITO) and conducting polymers such as polyaniline have been used as electrodes for organic thin film FETs as described in Z. Bao, Y. Fang, A. Dodabalapur, V. R. Raju, and A. J. Lovinger, Chem. Mater., 9, 1299, 1997; G. Gustagsson, Y. Cao, G. M. Treacy, F. Klavetter, N. Colaneri, and A. J. Heeger, Nature, 357, 277, 1992. It has also been reported that conducting polymer electrodes can improve the performance of ferroelectric P(VDF-TrFE) thin films by Z. Y. Cheng, H. S. Xu, J. Su, Q. M. Zhang, P. C. Wang, and A. G. MacDiarmid, Proc. SPIE, 3669, 140, 1999.

In a preferred embodiment, organic thin film semiconductor portions166and176comprise of polythiophene PQT or polymer blend such as Flexink that is printed using low-cost ink jet printing techniques according to known techniques. Alternatively, semiconductor portions166and176can be made by well known processes such as vacuum evaporation, electrochemical polymerization, solution spin coating, screen printing, and Langmuir-Blodgett growth. For example, pentacene thin films can be produced by using vapor deposition with the substrate temperatures from room temperature to 120° C. as described in C. D. Dimitrakopoulos, B. K. Furman, T. Graham, S. Hegde, and S. Purushothaman, Synth. Met., 92, 47, 1998, or by solution spin coating method using dichloromethane as solvent and annealing temperatures of 140 to 180° C. as described in A. R. Brown, A. Pomp, D. M. de Leeuw, D. B. M. Klaassen, E. E. Having a, P. Herwig, and K. Mullen, J. Appl. Phys., 79, 2136, 1996.

According to the present invention, pixels150of array100are connected to control circuits (not shown inFIG. 1, but are discussed below) by way of signal lines WL1-WL4and BL1-BL4such that a selected FeFET160can be selected for “write” or “read” memory operations by transmitting appropriate signals on selected ones of signal lines WL1-WL4and BL1-BL4. Note that signal lines WL1-WL4and BL1-BL4are made up of parallel word lines WL1-WL4and parallel bit lines BL1-BL4. Signal lines WL1-WL4are formed on different layers from signal lines BL1-BL4to facilitate aligning bit lines BL1-BL4orthogonal to word lines WL1-WL4without generating a short circuit.

FIG. 2is a simplified circuit diagram showing a portion of organic memory array100utilized to write a predetermined data value DV to a selected FeFET160-1of a selected pixel150-1. As indicated inFIG. 2, selected FeFET160-1is addressed by transmitting a write select signal WS generated by a source211onto bit signal line BL1by way of a decoder circuit213, whereby write select signal WS is applied to gate electrode178-1, thereby turning on organic FET160-1to couple signal line WL1to gate terminal168-1of selected FeFET160-1. At the same time a data value DV is generated by a signal source (e.g., a sensor)215that is passed to a write pulse generator217by a controller (not shown), which generates a corresponding write pulse signal WP that is transmitted onto signal line WL1by way of a decoder219. With organic FET170-1turned on, write pulse signal WP is passed from signal line WP1to gate terminal168-1of selected FeFET160-1, whereby an electric field generated by gate electrode168-1in response to write pulse signal WP generates a corresponding change in the polarization of a portion of the ferroelectric dielectric material layer disposed between gate electrode168-1and the channel region of selected pixel150-1. By changing the dielectric polarization, the transistor threshold voltage associated with FeFET160-1is shifted, and the source-drain current of FeFET160-1is increased (“on” state) or decreased (“off” state). An optional capacitor155can be added in parallel with the FeFET as indicated inFIG. 2to increase the dielectric charging time to allow sufficient time for polarization switch. Bilayer dielectrics with a high-k dielectric such as Ta2O5can be used to lower the transistor operation range.

FIG. 3is a simplified circuit diagram showing a portion of organic memory array100utilized to read the data value stored in selected FeFET160-1of pixel150-1. As indicated inFIG. 3, selected FeFET160-1is addressed by transmitting a read current IREADfrom a source221onto signal line WL2by way of a decoder circuit223, whereby the read current IREADis transmitted to source electrode162-1of selected FeFET160-1. At the same time, signal line BL2is coupled to a sense amplifier225or other signal detection circuit by way of a decoder226. As set forth above, under the conditions depicted inFIG. 3, an amount IFeFETof read current IREADis passed by ferroelectric FET160-1to current detection circuit225, which includes in one example a resistor R1for converting the current IFeFETto a cell voltage VCELL, which is then compared y a comparator229with a reference voltage VREFgenerated by a reference unit227. The read value from pixel150-1is then output as a voltage signal VOUT. Thus, in the reading step, the state of selected FeFET150-1is determined by measuring its source-drain current. However, a common dataline cannot be used to transmit the IFeFETbecause the read-out will be a sum of the current from several FeFETs rather than from a single pixel. Further, a gate voltage cannot be applied to turn off the FeFETs not being read, because it will over-write the stored states of these non-selected FeFETs. The solution set forth by the embodiment ofFIG. 3is to use “row” lines to transmit the read current IREADand column lines to read out data values IFeFET. This pixel has been fabricated in practice, and experimentally measured data storage is displayed inFIG. 4. As set forth below, another approach proposed in the embodiments associated withFIGS. 11-14involves adding a second organic thin-film FET to serve as a read switch that isolates each pixel's FeFET current for read-out.

As set forth above with reference toFIG. 1, one of dielectric layers110and120includes a ferroelectric dielectric material, and the other of dielectric layers110and120includes an organic dielectric material. In the specific embodiments described below with references toFIGS. 5-9, an organic dielectric material layer140is disposed in the location associated with dielectric layer110(i.e., directly on substrate101), and a ferroelectric dielectric material layer130is disposed in the location associated with dielectric layer120(i.e., on organic dielectric layer140). In another exemplary embodiment described below with reference toFIG. 10, the order is reversed and dielectric material layer130is disposed between substrate101and organic dielectric material layer140.

FIG. 5is a simplified cross-sectional side view showing a pixel150A according to a specific embodiment of the present invention including a bottom gate FeFET transistor160A and a bottom gate write select (organic FET) transistor170A, wherein pixel150A is utilized in place of generalized pixel150ofFIG. 1to form an organic memory array according to a first specific embodiment of the present invention. Referring to the left side ofFIG. 5, organic FET170A is constructed such that source electrode172A, drain electrode174A and organic semiconductor portion176A are disposed between organic dielectric material layer140A and ferroelectric dielectric material layer130A, and gate electrode178A is disposed between substrate101and organic dielectric material layer140A below channel region175A. Similarly, FeFET transistor160A is formed such that gate electrode168A is disposed between organic dielectric material layer140A and ferroelectric dielectric material layer130A below channel region165A, and source electrode162A, drain electrode164A and organic semiconductor portion166A are disposed on ferroelectric dielectric material layer130A over drain electrode168A. According to another aspect of the present embodiment, in order to facilitate disposing orthogonal signal lines WL2(which is connected to source electrode162A) and BL2(which is connected to drain region164A), pixel150A further includes a metal via structure157A that extends through ferroelectric dielectric material layer130A between drain electrode164A and signal line BL2, which is disposed between organic dielectric material layer140A and ferroelectric dielectric material layer130A. Metal via structure157A is formed by etching such as printing solvent/etchant to remove material locally or laser ablating a portion of ferroelectric dielectric material layer130A to form the required via (opening), and then printing a conductive ink material (e.g., a silver-based ink) into the via.

FIG. 6is a flow diagram listing the sequence of steps associated with the fabrication of memory array100A according to a specific embodiment of the present invention.

Referring to the top ofFIG. 6, after selecting a suitable substrate (e.g., either rigid or flexible and made from one of silicon, metal, glass, plastic, or any other suitable material that can withstand the temperatures of approximately 200° C.), an optional dielectric layer is formed (block205). If a conducting material is used for the substrate, such as doped silicon substrates or metal substrates, then the substrate should include a thin insulating layer on the upper surface in order to isolate the gate electrodes from the substrate. For instance, a silicon wafer could have a thin layer of oxidization or nitride on the upper surface as an insulator. For a metal substrate, a thin inorganic insulating layer, such silicon oxide or silicon nitride, or a thin organic insulating layer, such as polyimide, may be used. Such thin organic insulating layers may be deposited on the surface by using well known sputtering, chemical vapor deposition, or solution deposition method. The insulating layers described above are for descriptive use only, and other insulating layers may also be used.

Gate electrode178A and associated wordlines (e.g., wordline WL1) is then preferably formed by printing a silver-based ink using ink-jet printing techniques onto the substrate (block210). Alternatively, gate electrode178A and the associate wordlines could be any patterned conductive material such as a metal thin film, for instance gold, platinum, aluminum, or titanium, a conducting oxide such as ITO, or a conducting polymer such as polyaniline, and polypyrrolon the surface of the substrate. The gate electrode could be deposited by the well known methods of evaporation, sputtering, screen printing, solution dip or spin coating depending on which process is most suitable for the electrode, material and substrate being used.

Organic (non-ferroelectric) dielectric material layer140A is then formed by depositing a poly(p-xylylene) polymer (e.g., Parylene-N™ over the substrate using well known room temperature deposition methods (block220). Alternative methods for forming organic dielectric material layer140A include solution casting or spin coating, screen printing or jet printing, Langmuir-Blodgett growth method or self assembly of layers from solution or other methods. Alternative organic dielectric materials include polyimide, polyvinyl alcohol (PVA), fluorinated polymer Cytop, and polymethylmethacrylate (PMMA).

Source electrode172A (and its associated bitline), drain electrode174A, gate electrode168A and bit line BL2are then preferably formed on organic dielectric layer140A by printing a silver-based ink using ink-jet printing techniques onto the substrate (block230). These structures may be produced utilizing the alternative metallization processes described above.

Deposition of organic semiconductor thin film portion176A in the channel region separating source electrode172A and drain electrode174A is then performed by printing polythiophene PQT, polymer blend such as Flexink, or perylene derivatives using ink-jet printing techniques (block240). Alternative organic semiconductor materials that can be used include poly(phenylenes), thiophene oligomers, pentacene, polythiophene. While the above materials are p-type semiconductors, n-type semiconductors such as perfluoro copper phthalocyanine and perylene derivatives can be used also. In addition, inorganic semiconductors that are printable at low-processing temperature such as zinc oxide are also good alternatives. Alternative methods for forming organic semiconductor thin film portion176A include deposition by vapor deposition, solution casting or spin coating, screen printing, Langmuir-Blodgett growth method or self assembly of layers from solution.

Deposition of ferroelectric dielectric material layer130A is then performed (block250) by depositing P(VDF-TrFE) using spin coating techniques. While ferroelectric polymer materials in the family of copolymers are suitable, other ferroelectric polymer materials such as PVDF, odd-numbered nylons, cyanopolymers, polyureas and polythioureas could also be used. These polymer thin films could be deposited by evaporation, solution casting or spin coating, Langmuir-Blodgett growth method, screen printing or jet printing.

Via157A is then defined through ferroelectric dielectric material layer130A (block260) by forming a via opening using locally printed solvent etchant for PVDF-TrFE and by laser ablation for parylene-N, and then filling the via opening (block270) using silver-based ink.

Source electrode162A (and its associated wordline) and drain electrode164A are then preferably formed on ferroelectric dielectric layer130A by printing a silver-based ink using ink-jet printing techniques onto the substrate (block280), followed by the deposition of organic semiconductor thin film portion166A by printing polythiophene using ink-jet printing techniques (block290). Alternative methods provided above may be used in place of these processes. Finally, an optional protective dielectric layer (block295) is formed over ferroelectric dielectric layer130A according to known techniques.

While the basic processes are described above with specific reference to the fabrication of memory array100A, there are several optional steps known to those skilled in the art that may be used. In addition, although the basic processes described above are utilized in the fabrication of the alternative embodiments described below, those skilled in the art will recognize the order in which the basic processes are performed may be varied to achieve the desired structures.

FIG. 7is a simplified cross-sectional side view showing a pixel150B according to an alternative specific embodiment of the present invention including a top gate FeFET transistor160B and a bottom gate write select (organic FET) transistor170B, wherein pixel150B is utilized in place of generalized pixel150ofFIG. 1to form an organic memory array according to a second specific embodiment of the present invention. Similar to pixel150A (discussed above), pixel150B is arranged with organic dielectric layer140B disposed on substrate101, and ferroelectric dielectric layer130B disposed on organic dielectric layer140B. Referring to the left side ofFIG. 7, organic FET170B is also similar to organic FET170A (discussed with reference toFIG. 5) in that it includes a source electrode172B, a drain electrode174B and an organic semiconductor portion176B disposed between organic dielectric material layer140B and ferroelectric dielectric material layer130B, and gate electrode178B is disposed between substrate101and organic dielectric material layer140B below channel region175B. However, FeFET transistor160B is formed such that gate electrode168B is disposed on top of ferroelectric dielectric material layer130B above channel region165B, and source electrode162B, drain electrode164B and organic semiconductor portion166B are disposed between organic dielectric material layer140B and ferroelectric dielectric material layer130B below drain electrode168B. This top-gate arrangement provides the advantages of lower contact resistance and encapsulation of environmentally sensitive semiconductors. The top-gate configuration is preferable for both organic FET and FeFET, but bottom-gate organic FET170B has the advantage of fewer via-processing steps compared to the structure inFIGS. 8 and 9. In order to connect drain electrode174B with gate electrode168B, a metal via structure157B is provided as described above that extends through ferroelectric dielectric material layer130B between drain electrode174B and gate electrode168B.

FIG. 8is a simplified cross-sectional side view showing a pixel150C according to another specific embodiment of the present invention including a bottom gate FeFET transistor160C and a top gate write select (organic FET) transistor170C, wherein pixel150C is utilized in place of generalized pixel150ofFIG. 1to form an organic memory array according to a third specific embodiment of the present invention. Similar to pixels150A and150B (discussed above), pixel150C is arranged with organic dielectric layer140C disposed on substrate101, and ferroelectric dielectric layer130C disposed on organic dielectric layer140C. Referring to the left side ofFIG. 8, organic FET170C differs from organic FETs170A and170B in that organic FET170C includes a source electrode172C, a drain electrode174C and an organic semiconductor portion176C disposed between substrate101and organic dielectric material layer140C (i.e., these structures are printed on substrate101before dielectric material layer140C is formed), and gate electrode178C is disposed between organic dielectric material layer140C and ferroelectric dielectric material layer130C above channel region175C. FeFET transistor160C is formed such that gate electrode168C is disposed between organic dielectric material layer140C and ferroelectric dielectric material layer130C below channel region165C, and source electrode162C, drain electrode164C and organic semiconductor portion166C are disposed on top of ferroelectric dielectric material layer130C below drain electrode168C. In order to connect drain electrode174C with gate electrode168C, a metal via structure157C is provided as described above that extends through organic dielectric material layer140C between drain electrode174C and gate electrode168C. In addition, in order to facilitate disposing orthogonal signal lines WL2(which is connected to source electrode162C) and BL2(which is connected to drain region164C), pixel150C further includes a second metal via structure158C that extends through ferroelectric dielectric material layer130C between drain electrode164C and signal line BL2, which is disposed between organic dielectric material layer140C and ferroelectric dielectric material layer130C. An encapsulation layer such as PMMA or parylene can be added over semiconductor166C to protect the semiconductor from oxidation. The embodiment inFIG. 8improves the organic FET with the top-gate configuration. The FeFET is left as bottom-gate structure to avoid deposition of semiconductor between the gate electrode168C and transistors electrodes162C and164C, to increase the capacitance in the optional capacitor as indicated inFIG. 2.

FIG. 9is a simplified cross-sectional side view showing a pixel150D according to another specific embodiment of the present invention including a top gate FeFET transistor160D and a top gate write select (organic FET) transistor170D. Similar to the previous examples, pixel150D is utilized in place of generalized pixel150ofFIG. 1to form an organic memory array according to a fourth specific embodiment of the present invention. In addition, similar to pixels150A-150C (discussed above), pixel150D is arranged with organic dielectric layer140D disposed on substrate101, and ferroelectric dielectric layer130D disposed on organic dielectric layer140D. Referring to the left side ofFIG. 9, organic FET170D is similar to organic FET150C in that organic FET170D includes a source electrode172D, a drain electrode174D and an organic semiconductor portion176D disposed between substrate101and organic dielectric material layer140D, and gate electrode178D is disposed between organic dielectric material layer140D and ferroelectric dielectric material layer130D above channel region175D. However, FeFET transistor160D is formed such that gate electrode168D is disposed on top of ferroelectric dielectric material layer130D above channel region165D, and source electrode162D, drain electrode164D and organic semiconductor portion166D are disposed between organic dielectric material layer140D and ferroelectric dielectric material layer130D below drain electrode168D. In order to connect drain electrode174D with gate electrode168D, a metal via structure157D is provided as described above that extends through both organic dielectric material layer140D and ferroelectric dielectric material layer130D between drain electrode174D and gate electrode168D. In addition, in order to facilitate disposing orthogonal signal lines WL2(which is connected to source electrode162D) and BL2(which is connected to drain region164D), pixel150D further includes a second metal via structure158D that extends through ferroelectric dielectric material layer130D between drain electrode164D and signal line BL2, which is disposed on ferroelectric dielectric material layer130D. The embodiment inFIG. 9improves the contact resistance of both organic FET and FeFET and provides encapsulation for the semiconductors.

FIG. 10is a simplified cross-sectional side view showing a pixel150E according to another specific embodiment of the present invention including a top gate FeFET transistor160E and a top gate write select (organic FET) transistor170E. Unlike the previous examples, pixel150E is arranged with ferroelectric dielectric layer130E disposed on substrate101, and organic dielectric layer140E disposed on ferroelectric dielectric layer130E. Referring to the left side ofFIG. 10, organic FET170E is similar to previous structures in that organic FET170E includes a source electrode172E, a drain electrode174E and an organic semiconductor portion176E disposed between ferroelectric dielectric layer130E and organic dielectric material layer140E, and gate electrode178E is disposed on top of organic dielectric material layer140E above channel region175E. FeFET transistor160E is formed such that gate electrode168E is disposed on top of ferroelectric dielectric material layer130E above channel region165E, and source electrode162E, drain electrode164E and organic semiconductor portion166E are disposed between substrate101and ferroelectric dielectric material layer130E below drain electrode168E. In order facilitate disposing orthogonal signal lines WL2(which is connected to source electrode162E) and BL2(which is connected to drain region164E), pixel150E further includes a second metal via structure158E that extends through ferroelectric dielectric material layer130E between drain electrode164E and signal line BL2, which is disposed between organic dielectric material layer140E and ferroelectric dielectric material layer130E. The embodiment inFIG. 10improves the contact resistance of both organic FET and FeFET, provides encapsulation for the semiconductors, and reduces the via-processing steps ofFIG. 9. The potential disadvantage of this embodiment is that the PVDF-TrFE is deposited early in the process flow and thus requires careful temperature monitoring throughout the fabrication to avoid disturbing the crystallinity of the PVDF-TrFE film. The data inFIG. 4demonstrates that this potential difficulty with film crystallinity has been overcome.

As set forth above, a second solution to the problem associated with the use of FeFETs (i.e., that a common dataline cannot be used to transmit the IFeFETbecause the read-out will be a sum of the current from several FeFETs rather than from a single pixel) involves adding a “read switch (i.e., a second organic thin-film FET) to each pixel that serves to isolate each pixel's FeFET current during read-out operations of other pixels connected to the common dataline. Such three-transistor (3T) pixels are described below with reference toFIGS. 11-14.

FIG. 11is a simplified diagram depicting a portion of a generalized organic memory array100F that is formed in accordance with another embodiment of the present invention, where memory array100F includes multiple 3T memory pixels150F and associated control and interconnect structures that are formed in the manner described above. In particular,FIG. 11shows 3T memory pixels150F-1and150F-2that are disposed adjacent to each other in a row of memory array100F. Other pixels of array100F are omitted for brevity, but are essentially identical to pixels150F-1and150F-2. According to an aspect of the present embodiment, each pixel150F of memory array100F includes a FeFET, a “write” (first) organic FET, and a “read” (second) organic FET that are connected to associated signal lines of array100F. For example, pixel150F-1includes an FeFET160F-1connected between a “write” (first) organic FET170F-1and a “read” (second) organic FET180F-1, and pixel150F-1includes an FeFET160F-1connected between a “write” (first) organic FET170F-1and a “read” (second) organic FET180F-1.

Similar to the 2T embodiments described above, the “write” transistor of each pixel150F is disposed to pass a write pulse signal to the gate terminal of the pixel's FeFET during write operations. For example, referring to pixel150F-1, organic FET170F-1includes a source electrode172F connected to signal line W1, a drain electrode174F connected to a gate terminal168F of FeFET160F, and a gate electrode178F connected to a signal line B1. Similarly, organic FET170F-2of pixel150F-2is connected to signal lines W2and B1. Write operations performed in memory array100F are therefore similar to those described above, with write operations involving turning on a selected “write” FET by passing a high voltage on associated signal lines (e.g., applying a high voltage on signal line B1to turn on organic FET170F-1), and passing associated write pulse signals along associated signal lines the gate terminals of addressed FeFETs (e.g., passing a write pulse signal along signal line W1, which is passed by “turned on” organic FET170F-1to gate terminal168F of FeFET160F-1).

Read operations are also performed in a manner similar to the previous embodiments, with the polarized (i.e., “up” or “down”) state of each FeFET being determined by transmitting a read current signal and measuring the source-drain current passed through the FeFET of a selected pixel. However, because signal lines are shared by pixels150F disposed along each row array100F (e.g., pixels150F-1and150F-2share dataline B2), in the absence of the read FETs, a read current passed along a given signal line (e.g., signal line B2) would simultaneously through the FeFETs of all pixels150F associated with that row (e.g., the signal would pass through both FeFETs160F-1and160F-2), and would thereby produce a sum of currents from a whole row of FeFETs rather than from a single pixel. Further, a gate voltage cannot be applied to turn off the FeFETs of non-selected pixels because, as explained above, applying a gate signal to an FeFET will over-write its stored state. The solution for avoiding the isolation problem in array100F is to add a “read” FET to each pixel150F (e.g., organic FET180F-1is provided in pixel150F-1, and organic FET180F-2is provided in pixel150F-2) in order to isolate each pixel's FeFET current for read-out. The “read” FET of each pixel150F is connected between the shared signal line and the source terminal of that pixel. For example, organic FET180F-1includes a (third) source electrode182F electrically connected to signal line B2, a (third) drain electrode184F connected to drain electrode162F, a third gate terminal186F connected to an associated signal line W2. Organic FET180F-2is similarly arranged and connected to signal lines B2and W4. Organic FETs180F-1and180F-2also include an organic semiconductor portion disposed in a channel region defined between the source and drain electrodes in a manner similar to that described above. With this arrangement, a read current passed along signal line B2is only passed through “selected” FeFET160-1if signal line W2carries a voltage sufficient to turn on “read” FET180F-1(i.e., with signal line W4maintained at a low voltage to prevent the read current from passing through “read” FET180F-2). Experimentally derived characteristics associated with 3T pixels150F are shown inFIG. 12.

FIG. 13is a simplified cross-sectional side view showing a 3T pixel150G according to another specific embodiment of the present invention. Pixel150G is arranged with a ferroelectric dielectric layer130G disposed on substrate101, and organic dielectric layer140G disposed on ferroelectric dielectric layer130G. Pixel150G includes a FeFET transistor160G, a “read” (first) organic FET170G, and a “write” organic FET180G. Organic FET170G includes a source electrode172G, a drain electrode174G and an organic semiconductor portion176G disposed between ferroelectric dielectric layer130G and organic dielectric material layer140G, and a gate electrode178G is disposed on top of substrate101below channel region175G. FeFET transistor160G includes a source electrode162G, a drain electrode164G and an organic semiconductor portion166G disposed on top of ferroelectric dielectric material layer130G, and a gate electrode168G disposed on top of organic dielectric material layer140G below channel region165G. FeFET transistor160G includes a source electrode162G, a drain electrode164G and an organic semiconductor portion166G disposed on top of ferroelectric dielectric material layer130G, and a gate electrode168G disposed on top of organic dielectric material layer140G below channel region165G. Organic FET180G includes a source electrode182G, a drain electrode184G and an organic semiconductor portion186G disposed on top of ferroelectric dielectric material layer130G, and a gate electrode188G disposed on top of organic dielectric material layer140G below channel region185G. Drain electrode184G connects to source electrode162G to facilitate read operations in the manner described above. Note that organic FET180G utilizes a portion of ferroelectric dielectric material layer130G to for channel region185G, thus utilizing the ferroelectric dielectric material as a “common” dielectric material. This embodiment ensures that pixel crosstalk is eliminated during the data read-out process compared to 2T pixel inFIG. 2. This configuration has the advantage of fewer processing steps compared to the embodiment inFIG. 14.

FIG. 14is a simplified cross-sectional side view showing a 3T pixel150H according to another specific embodiment of the present invention. Similar to pixel150G, pixel150H is arranged with a ferroelectric dielectric layer130H disposed on substrate101, and organic dielectric layer140H disposed on ferroelectric dielectric layer130H. Pixel150H also includes a bottom gate FeFET transistor160H, a bottom gate “read” FET170H, and a “write” FET180H. Organic FET170H includes a source electrode172H, a drain electrode174H and an organic semiconductor portion176H disposed between ferroelectric dielectric layer130H and organic dielectric material layer140H, and a gate electrode178H is disposed on top of substrate101below channel region175H. FeFET transistor160H includes a source electrode162H, a drain electrode164H and an organic semiconductor portion166H disposed on top of ferroelectric dielectric material layer130H, and a gate electrode168H disposed on top of organic dielectric material layer140H below channel region165H. Organic FET180H includes a source electrode182H, a drain electrode184H and an organic semiconductor portion186H disposed on top of ferroelectric dielectric material layer130H, and a gate electrode188H disposed on top of organic dielectric material layer140H below channel region185H. A metal via structure157H extends through ferroelectric dielectric material layer130H between drain electrode184H and source electrode162H to facilitate read operations in the manner described above. This embodiment allow the “read” FET180H to use the dielectric140H that makes a better interface with the semiconductor than130H for the organic FET. This has the advantage of better “read” FET performance overFIG. 13, at the expense of more processing steps.

According to another aspect of the present invention, the various organic memory array structures disclosed above use FeFETs as analog memory without analog-to-digital circuits to store different values of input voltage.FIGS. 15(A) to 15(C)are graphs illustrating that the magnitude of an input signal voltage affects the extent to which the dielectric polarization is switched, thus allowing the storage and readback of analog data by measuring the source-drain current, which is dependent on the input voltage.FIG. 15(A)shows that the difference in “on” and “off” currents in the FeFETs of the present invention depends on the input gate voltage.FIG. 15(B)shows the read-out current of the FeFETs as a function of input voltage, and in particular shows the current increased by 28 nA/20V=1.4 nA/V.FIG. 15(C)shows calibration for the signal decay with time; despite using two different semiconductors, the decay is similar in magnitude. Thus, decay in source-drain current is observed with time, and calibration of this decay is necessary if the FeFET is used in analog mode.

When using the ferroelectric transistor as analog memory, hysteresis decay will occur and a calibration scheme is needed to extract the original input voltage. The calibration is done by sweeping gate voltages with increasing range (shown inFIG. 15(A), and the resulting difference in current hysteresis can be plotted against the switching voltage (shown inFIG. 15(B), here defined as the highest voltage applied in the gate-voltage sweep. The change in current with time can be traced by this calibration method, as shown inFIGS. 15(C),16(A) and16(B).

Although the present invention has been described with respect to certain specific embodiments, it will be clear to those skilled in the art that the inventive features of the present invention are applicable to other embodiments as well, all of which are intended to fall within the scope of the present invention.