The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.

TECHNICAL FIELD

A present invention described herein relates generally to a process for fabricating an integrated circuit structure, and more specifically to an electronic memory device, a process for manufacture, and a method of use thereof.

BACKGROUND ART

Semiconductor memory devices are typically classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are subdivided into dynamic random access memories (DRAMs) and static random access memories (SRAMs). Non-volatile memory types include mask read-only memories (MROMs), programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), and electrically erasable programmable read-only memories (EEPROMs). EEPROMs are increasingly used in system programming that requires continuous update or auxiliary memory devices. Particularly, flash EEPROMs are advantageous as mass storage devices because their integration density is high compared with conventional EEPROMs.

FIG. 1shows a prior art EEPROM memory cell100. The memory cell100includes an NMOS select transistor101, an NMOS memory transistor103, a bit line terminal105, an NMOS—NMOS drain junction107, and a source terminal109. A contemporary EEPROM uses NMOSfets for both the NMOS select transistor101and the NMOS memory transistor103. Fabrication difficulties currently arise if different device types are employed. However, this same NMOS—NMOS arrangement requires a programming potential as high as 14 volts. Although the tunneling current through a typical 7 nanometer (nm) thick tunnel diode window can be injected with only 10 volts, the higher 14 volt programming potential is required due to a voltage drop across the select transistor101. This voltage drop will depend on factors such as transistor threshold voltage and body effects, but can be about 3 volts or more. For example, a 14-volt programming pulse on the bit line terminal105may produce only 11 volts at the NMOS—NMOS drain junction107.

Accordingly, what is needed is a way to provide an improved process and structure capable of programming an EEPROM device at about 10 volts, thereby allowing an integration into existing processes without adding additional or complex masks. Such a device would also, for example, allow for EEPROM integration into a 3.3 volt CMOS technology. Such a structure must be economical to manufacture and readily adaptable to contemporary integrated circuit fabrication facilities.

DISCLOSURE OF THE INVENTION

A voltage drop across an NMOS select device can be greatly reduced or eliminated by utilizing a PMOS transistor as a select device. For example, a PMOS transistor is activated (i.e., turned “on”) by lowering a gate voltage to 0 volts. In the activated state, there is essentially no voltage drop between the source and drain, thereby allowing the full source voltage to be transmitted to the drain. Therefore, the memory cell can be programmed using a reduced bit line voltage.

The present invention is a method of fabricating an electronic memory cell. The method of fabrication comprises implanting a first drain dopant region and a first source dopant region into an uppermost side of a semiconducting substrate. The semiconductor substrate may contain a p-type epitaxial layer into which the dopant regions are formed. The first drain and the first source dopant regions are doped to provide donor sites (n-type). A second drain dopant region and a second source dopant region are formed in an n-well in the epitaxial layer and are doped to provide acceptor sites (p-type). A shallow trench isolation region is formed substantially between the first drain/first source dopant regions and the second drain/second source dopant regions. The first drain dopant region is then electrically coupled to the second drain dopant region. Additional process steps, well-known to one skilled in the art, are added to fabricate a PMOS transistor from the second drain and second source dopant regions. The PMOS transistor serves as a select transistor in the memory cell and is configured to have an essentially zero voltage drop between the second source and second drain regions when the PMOS transistor is in an activated state. An NMOS transistor is fabricated from the first drain and first source dopant regions; the NMOS transistor is configured to serve as a memory transistor in the memory cell.

The present invention is also an electronic memory cell comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be coupled to a word line and is configured to be programmable with a voltage about equal to a voltage on the bit line.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 2shows an exemplary EEPROM memory cell200of the present invention. The memory cell200includes a PMOS select transistor201, an NMOS memory transistor203, a bit line terminal205, a PMOS-NMOS drain junction terminal207, and a source terminal209. The PMOS-NMOS drain junction terminal207may not necessarily be an actual physical terminal, but rather, is used herein as an abstraction to more fully discuss programming the memory cell200, infra.

When the PMOS select transistor201is activated (i.e., turned “on”) by lowering a voltage at the select gate to 0 volts, there is essentially no voltage drop between the source and drain, thereby allowing a full source voltage (e.g., 10 volts) applied at the bit line terminal205to be transmitted to the PMOS-NMOS drain junction terminal207and applied to a drain of the NMOS memory transistor203. Therefore, the memory cell can be programmed using a reduced bit line voltage.

With reference toFIGS. 3–7, an exemplary embodiment of the present invention is described in detail according to the following process steps.FIG. 3includes a cross-section of a film stack applied over a base substrate301, and an epitaxial deposition layer303. The film stack includes a pad oxide305, a nitride layer307, and a photoresist layer309. As is known in the art, the pad oxide305functions as a cushion to avoid stresses between the base substrate301and the nitride layer305. The nitride layer305serves as an etch mask for formation of a shallow trench isolation (STI) structure, described infra. In a specific exemplary embodiment, the pad oxide305is thermally grown and is 10 nm–50 nm thick, the nitride layer307, typically deposited by low-pressure chemical vapor deposition (LPCVD) techniques, is 30 nm–100 nm thick, and the photoresist layer309is spun-on and is up to 1 micrometer (μm) thick. Alternatively, a single oxide layer (not shown) may be deposited or grown and may take the place of the joint pad oxide/nitride stack305,307. In either case, the photoresist layer309is then lithographically patterned in preparation for an STI etch.

The base substrate301is frequently a silicon wafer. In this embodiment, the silicon wafer contains a p-type dopant. Alternatively, another elemental group IV semiconductor or compound semiconductor (e.g., groups III–V or II–VI) may be selected for base substrate301. For a p-type silicon base substrate301, the epitaxial deposition layer will also contain a p-type dopant.

With reference toFIG. 4, the film stack is etched by exposing and developing the photoresist layer309, and etching through the photoresist layer309, underlying nitride307, and oxide305layers, thereby producing an STI etch mask window401. The nitride307and oxide305layers are etched through various etching techniques, such as a wet etch (e.g., in hydrofluoric, such as contained in a standard buffered oxide etch, or orthophosphoric acid) or dry etch (e.g., reactive-ion etch (RIE)) techniques. Silicon (both the epitaxial layer303and the base substrate301underlying the etch mask window401) is then etched (for example, by nitric or hydrofluoric acid, potassium hydroxide (KOH), or tetra-methyl ammonium hydroxide (TMAH)). The etched silicon forms a silicon trench501(FIG. 5). In a specific embodiment, a width of the silicon trench, measured at an uppermost surface of the epitaxial deposition layer303, is at least about 2.3 μm.

The photoresist layer309is stripped and an oxide is deposited (e.g., by a chemical vapor deposition (CVD) process), filling the silicon trench501. Alternatively, an undoped silicate glass (USG) may be used to fill the silicon trench501. The nitride307and pad oxide305layers are stripped and the silicon trench501fill material is then planarized (e.g., by a chemical mechanical planarization (CMP) process), leaving the silicon trench501fill material essentially co-planar with an uppermost surface of the epitaxial deposition layer303. A final STI structure601(FIG. 6) electrically isolates subsequently implanted or diffused dopant regions.

FIG. 6includes a memory transistor source doped region605, a memory transistor gate dopant region607, a memory transistor drain dopant region609, an n-well structure611, a select transistor drain dopant region613, and a select transistor source dopant region615. All doped regions are formed by processes well-known to one of skill in the art and may be either implanted or diffused dopant regions. In a specific exemplary embodiment, the dopant regions are about 0.2 micrometers (μm) in depth. The STI structure601isolates the memory transistor drain dopant region609from the select transistor drain dopant region613.

The memory transistor source605and drain dopant regions609are implanted with an n-type dopant (n+) and the memory transistor gate dopant region607is a buried n-type (n+). The memory transistor gate dopant region607is used to form the bottom plate of a coupling capacitor and a heavily-doped region for a tunnel diode window (TDW), discussed with respect toFIG. 7, infra. A p-type epitaxial deposition layer303allows formation of the NNOS memory transistor without separate p-well implantation steps. To form the PMOS transistor201(FIG. 2) used for the select transistor, a p-type dopant is used in both the select transistor drain613and source615dopant regions. Both of the select transistor dopant regions are formed within the n-well structure611.

FIG. 7shows a cross-sectional EEPROM memory cell700after completion of major processing steps. The EEPROM memory cell700includes a gate oxide701, an NMOS polysilicon gate layer702, a metal drain coupling structure703, a PMOS polysilicon gate layer705, an NMOS source terminal707, a sense gate terminal709, a select gate terminal711, a PMOS bit line terminal713, and a tunnel diode window (TDW)715.

The gate oxide701is either thermally grown or CVD deposited. After the gate oxide growth, an opening is made to form, inter alia, the TDW715. A brief thermal oxidation is then performed to regrow a thin tunnel oxide in the TDW715. In a specific embodiment, the tunnel oxide is approximately 7 nm thick. The metal drain coupling structure703is formed to electrically couple the memory transistor drain dopant region609to the select transistor drain dopant region613. The metal drain coupling structure703is formed by processes well-known to a skilled artisan and briefly involves, for example, depositing a CVD nitride (or, alternatively, some other dielectric) layer, patterning and etching contact vias in the nitride (one above the drain dopant region309,313of each transistor), depositing a titanium nitride (TiN) or titanium (Ti) liner on interior walls of the via, and depositing a tungsten (W) or copper (Cu) plug within the lined via. Finally, an aluminum or copper interconnect is constructed to electrically couple the two vias, and the nitride layer is stripped. The polysilicon gate layers702,705are typically deposited by a CVD process.

The various transistor component terminals707,709,711,713may not necessarily be actual physical terminals, but rather, are used herein as an abstraction to more fully discuss programming the memory cell700, infra. Metallization steps (not shown), known to one of skill in the art, will provide actual connection terminals in later process steps.

Following the completion of major processing steps shown inFIG. 7, techniques well known to a skilled artisan are used to perform, for example, additional metallization, electronic-test, and packaging steps to complete the semiconductor memory cell device.

With reference to table 1, infra, exemplary programming and resulting voltages for the memory cell200ofFIG. 2are shown. Applying approximately 10 volts to the bit line terminal205, 0 volts to the select gate, and 0 volts at the sense gate allows a write operation to occur. During a write operation, an electrical potential at the PMOS-NMOS drain junction terminal207is 10 volts, indicating a 0 volt drop across the PMOS select transistor201. A voltage at the source terminal209is allowed to float. The sense gate terminal709is at zero voltage and the NMOS polysilicon gate layer702is negative with respect to memory transistor gate dopant region607. Electrons tunnel from the polysilicon gate layer702to memory gate dopant region607(i.e., the buried n+ dopant region), thereby lowering a threshold voltage of the memory transistor203.

An erase operation is effected by allowing the bit line terminal205to float, applying either 0 volts or 10 volts to the select gate, applying 0 volts at the source terminal209, and 10 volts to the sense gate. The NMOS polysilicon gate layer702is positive with respect to the memory source dopant region605and a channel is formed that links the memory source605to the memory gate dopant region607and the memory drain dopant region609. Therefore, the memory drain dopant region609, channel, and source dopant region605are all at 0 volts. The voltage across the polysilicon gate layer702and the memory gate dopant region607is approximately 10 volts. Electrons tunnel from the memory gate dopant region607to the polysilicon gate layer702, thereby increasing a threshold voltage of the memory transistor203.

A read operation is effected by applying 1 volt to the bit line terminal205, applying 0 volts to the select gate, applying 0 volts at the source terminal209, and 0 volts to the sense gate. If the memory cell200has been erased, a threshold voltage, Vt, is approximately 2.3 volts and the current flow will be negligible through the memory cell200.

To facilitate an understanding of the present invention, a process and arrangement for forming a low-voltage EEPROM memory cell has been discussed herein. However, the invented process and arrangements of layers and regions described herein may be readily modified to utilize other device types while still allowing advantages of the present invention presented herein. For example, although an embodiment depicts a PMOS-NMOS configuration for fabrication a memory cell, a skilled artisan will recognize that the present invention is readily adaptable to a PMOS—PMOS configuration while still realizing the low programming voltage advantage over the prior art.

Additionally, although process steps and techniques are shown and described in some detail, a skilled artisan will recognize that other techniques and methods may be utilized which are still included within the scope of the appended claims. For example, there are frequently several techniques used for depositing a film layer (e.g., chemical vapor deposition, plasma-enhanced vapor deposition, epitaxy, atomic layer deposition, etc.). Although not all techniques are amenable to all film types described herein, one skilled in the art will recognize that multiple methods for depositing a given layer and/or film type may be used. Further, as known to a skilled artisan, dopant regions may be either implanted or diffused.