Virtual Idle Loops

Techniques relating to virtual idle loops are described. In an embodiment, decoder circuitry decodes a single instruction. The single instruction includes a field for an identifier of a first source operand, a field for an identifier of a second source operand, a field for an identifier of a destination operand, and a field for an opcode. Execution circuitry executes the decoded instruction according to the opcode to: write the first source operand to a memory location identified by the second source operand; compute an index into a control array based at least in part on the destination operand; and determine whether to exit to a hypervisor of a Virtual Machine (VM) based at least in part on data stored at a location in the control array, wherein the location is to be identified by the computed index. Other embodiments are also disclosed and claimed.

FIELD

The present disclosure generally relates to the field of computing. More particularly, some embodiments relate to techniques to implement virtual idle loops.

BACKGROUND

Modern computing workloads often have short idle periods, for example, to wait for a reply from a network or a storage disk. In a virtualized environment example, a hypervisor (monitoring a Virtual Machine (VM)) may intercept a Halt (HLT) idle instruction to put the VM to sleep and allow other VMs to run to increase the utilization of a server. This can result in a round trip through the hypervisor and host idle loop or host scheduler.

This may, however, take longer than an expected timeout for a target short idle period. And even if it does not take longer, it may still increase the critical time from a wakeup event occurrence to code execution in a guest VM, which increases latency.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, various embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments. Further, various aspects of embodiments may be performed using various means, such as integrated semiconductor circuits (“hardware”), computer-readable instructions organized into one or more programs (“software”), or some combination of hardware and software. For the purposes of this disclosure reference to “logic” shall mean either hardware (such as logic circuitry or more generally circuitry or circuit), software, firmware, or some combination thereof.

As mentioned above, in a virtualized environment, a hypervisor (monitoring a VM) may intercept an HLT idle instruction to put the VM to sleep, resulting in a round trip through the hypervisor and host idle loop. This may, however, take up a significant portion of a short idle period and in some cases take longer than an expected timeout, and may be avoided by polling for the idle wake up event for some limited time. Such an approach may require special paravirtualization to achieve in some current implementations.

Also, the HLT instruction requires an interrupt if one Central Processing Unit (CPU) or processor in a VM wants to wake up another CPU to execute work. The interrupt typically also needs a round trip through the host. On non-virtualized systems it is possible to use a MONITOR WAIT (MWAIT) instruction which uses special hardware to monitor a memory location for a change, in addition for waiting for any other events that may interrupt the idle loop. Another CPU may wake up the idle CPU by writing to the memory location without the overhead of an interrupt. Today this cannot be efficiently implemented virtually, in part, because it is too expensive (in terms of delay, bandwidth use, and/or resource utilization) and may also be difficult to track the memory write operation from the hypervisor while a target CPU is sleeping. Instead of this tracking, virtualized guest VMs may use the older HLT instruction to put themselves to sleep.

To this end, some embodiments provide techniques to implement virtual idle loops. In an embodiment, a new Monitor Trigger (MTRIGGER) instruction is provided which allows for integration of idle polling into the virtualization architecture, e.g., making it available to all guest VMs. In one embodiment, the MTRIGGER instruction allows for virtualization of wakeup events. Hence, one or more embodiments may reduce the latency for a wakeup operation and/or reduce the overhead associated with entering or exiting an idle loop. At least one embodiment improves the performance of virtual idle loops.

Moreover, the MONITOR or MWAIT instructions cannot be easily virtualized because a sleeping guest VM cannot efficiently intercept a trigger write operation and these instruction are usually disabled in guest VMs. The changes proposed herein in accordance with one or more embodiments allow full virtualization for such tasks, which in turn enables faster wakeup of other processor cores executing guest VMs.

As discussed herein, an “MWAIT” instruction refers to an x86 instruction that provides a hint to allow a processor to stop instruction execution and enter an implementation-dependent optimized state (e.g., a sleep or low power consumption state) until the occurrence of an event. An MWAIT may be considered as a no operation (NOP) instruction architecturally. Also, “paravirtualization” generally refers to an enhancement of virtualization technology in which a guest Operating System (OS) is modified prior to installation inside a VM in order to allow all guest OSes within the system to share resources and successfully collaborate, rather than attempt to emulate an entire hardware environment. Further, an “MONITOR” instruction generally refers to an x86 instruction that sets up a linear address range to be monitored by monitoring hardware. While some embodiments are discussed with reference to an x86 Instruction Set Architecture (ISA), embodiments are not limited to an x86 ISA and other ISAs may be utilized to implement the operations discussed herein with reference to various instructions.

By contrast, some software may add a paravirtualized idle loop which would perform limited polling. Also, hypervisors generally would disable the use of MONITOR/MWAIT in guest VMs, forcing the guest VM to fall back to Inter Processor Interrupts (IPIs) for wake processor cores. Moreover, a paravirtualized idle loop requires hypervisor-aware clients. However, paravirtualized idle loops cannot be fully controlled by a hypervisor and require guest VM cooperation. And, the Monitor/MWAIT instructions are not used in guest VMs, limiting low latency wake-up from other processors, requiring a full IPI to wake up another processor core executing a guest VM. Additionally, polling in software is less energy efficient than using the snooping feature of MONITOR/MWAIT instructions.

As a result, one or more embodiments may remove a need to use hypervisor-aware guest VMs to obtain low-latency short guest VM idle periods (e.g., less than 1 milli second (ms), tens or hundreds of micro second, etc.). Rather, a hypervisor may control idle polling in the guest VM and use energy efficient wakeup operations. This may result in faster wakeup of a processor core executing a guest VM through MONITOR/MWAIT instead of requiring Inter Processor Interrupts.

FIG.1illustrates examples of computing hardware to process an MTRIGGER instruction. As illustrated, storage103stores the MTRIGGER instruction101to be executed.

The instruction101is received by decoder circuitry105. For example, the decoder circuitry105receives this instruction from fetch circuitry (not shown). The instruction may be in any suitable format, such as that describe with reference toFIG.9below. In an example, the instruction includes fields for an opcode, source identifier(s), and a destination identifier. In some examples, the sources and destination are registers, and in other examples one or more are memory locations. In some examples, one or more of the sources may be an immediate operand. In some examples, the opcode details to be performed.

More detailed examples of at least one instruction format for the instruction will be detailed later. The decoder circuitry105decodes the instruction into one or more operations. In some examples, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry109). The decoder circuitry105also decodes instruction prefixes.

In some examples, register renaming, register allocation, and/or scheduling circuitry107provides functionality for one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some examples), 2) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded instruction for execution by execution circuitry out of an instruction pool (e.g., using a reservation station in some examples).

Registers (register file) and/or memory108store data as operands of the instruction to be operated by execution circuitry109. Example register types include packed data registers, general purpose registers (GPRs), and floating-point registers.

Execution circuitry109executes the decoded instruction. Example detailed execution circuitry includes execution circuitry109shown inFIG.1, and execution cluster(s)760shown inFIG.7(B), etc. The execution of the decoded instruction causes the execution circuitry to perform the associated operations.

In some examples, retirement/write back circuitry111architecturally commits the destination register into the registers or memory108and retires the instruction.

An example of a format for an instruction is OPCODE DST, SRC1, SRC2. In some examples, OPCODE is the opcode mnemonic of the instruction. DST is a field for the destination operand, such as packed data register or memory. SRC1and SRC2are fields for the source operands, such as packed data registers and/or memory.

FIG.2illustrates an example method performed by a processor to process an instruction. For example, a processor core as shown inFIG.7(B), a pipeline as detailed below, etc., performs this method.

At201, an instance of single instruction is fetched. For example, an instruction is fetched. The instruction includes fields for an opcode, and optionally specifics of indications of particular operands and/or immediate operands. In some examples, the instruction further includes a field for a writemask. In some examples, the instruction is fetched from an instruction cache. The opcode indicates the operation(s) to perform.

The fetched instruction is decoded at203. For example, the fetched instruction is decoded by decoder circuitry such as decoder circuitry105or decode circuitry740detailed herein.

Data values associated with the source operands of the decoded instruction are retrieved when the decoded instruction is scheduled at205. For example, when one or more of the source operands are memory operands, the data from the indicated memory location is retrieved.

At207, the decoded instruction is executed by execution circuitry (hardware) such as execution circuitry109shown inFIG.1, execution circuitry109shown inFIG.1, or execution cluster(s)760shown inFIG.7(B). For the instruction, the execution will cause execution circuitry to perform the operations described in connection withFIG.1. As shown, in at least one embodiment, execution of the MTRIGGER instruction causes writing of a value to a memory location based on a memory address, computation of an index into a control array (such as the control array306ofFIG.3), and a determination of whether to exit/hand off execution to a hypervisor based at least in part on a value stored at the indexed location in the control array. Further details regarding the execution of the MTRIGGER instruction are discussed below with reference toFIG.4.

In some examples, the instruction is committed or retired at209.

FIG.3illustrates a block diagram of a VM Control Structure (VMCS)302, according to an embodiment. As shown, the VM control structure302stores information for: a pointer304to a control array306, an array limit308, a control bit for enabling/disabling MTRIGGER interception310, and a timeout configuration setting312for a virtualized MWAIT instruction. The control array306may store one or more elements314, where each element314in the control array306corresponds to a separate VCPU in that guest VM and each element314includes 64 bytes of data in an embodiment (e.g., for cacheline padding). The values stored in the elements are then used to determine whether to exit to a hypervisor as further discussed below.

FIG.4illustrates a flow diagram of a method400to improve the performance of virtual idle loops, according to an embodiment. One or more of the operations of method400may be performed by one or more components discussed herein with reference toFIGS.1-3and5-10.

In one embodiment, a new MTRIGGER instruction has three arguments: a value (or a first source operand), a memory address (or a second source operand), and an identifier (ID) (such as an Advanced Programmable Interrupt Controller (APIC) ID) of a target processor core (or a identifier of a destination operand). In an embodiment, the MTRIGGER instruction is an augmented move instruction, where the value is the choice of the guest OS and the value is stored at the supplied memory address. The stored value may be used to trigger a wakeup from an MWAIT of the target CPU if it is in guest context. But a guest OS may also check the value in other circumstances, e.g., to determine if it should check its run queue for new work to be processed. Execution of the MTRIGGER instruction causes the value to be written to the memory address and a determination of whether to exit to a hypervisor based at least in part on a value stored in an entry of the control array306based on an index to be computed per the ID of the target processor core. Moreover, in a virtualized environment multiple processor cores may be used to execute instructions. These processor cores are sometimes interchangeably referred to herein as Virtual Central Processing Units (VCPUs). Also, in some embodiments, more than one processor core/VCPU may be assigned to execute operations for a given VM.

Referring toFIGS.1to4, at an operation402, a first VCPU labeled as “VCPU1” executes an MWAIT instruction. At an operation404, it is determined whether an intercept for an MTRIGGER instruction is enabled (e.g., by reference to the status of the control bit310). In one embodiment, execution of the MWAIT instruction at operation402enables the intercept for the MTRIGGER instruction for VCPU1by updating the control bit310. If the MTRIGGER intercept is disabled, method400continues at operation406with legacy operations.

Once the MTRIGGER intercept is determined to be enabled for VCPU1, at an operation408, a second VCPU labeled as “VCPU2” executes the MTRIGGER instruction for VCPU1to indicate that it has work available as discussed herein. At an operation410, once a VM exit is detected (e.g., by the VCPU2based on the value stored at the indexed location of the control array306), the VCPU1is woken up (e.g., by a hypervisor) at an operation412; otherwise, method400resumes at operation408, After the VCPU1is woken up at operation412, VCPU1resumes execution at an operation414.

In one embodiment, once the MTRIGGER interception is determined to be enabled at operation404(e.g., per the status of the control bit310), the MTRIGGER instruction uses the ID of the target processor core/VCPU (e.g., the APIC ID) multiplied by the element size of the control array306(e.g., 64) to index into the control array306at operation408. When the value at this indexed location/address is true, an exit to a hypervisor is triggered at operation410; otherwise, an exit to the hypervisor is not triggered. This allows a hypervisor to efficiently enable/disable interception of the MTRIGGER instruction on another processor core (e.g., VCPU2) when the initial processor core (e.g., VCPU1) enters a low power consumption state (e.g., goes to sleep) in response to execution of an MWAIT instruction (e.g., at operation402) without risking performance degradation from false sharing in cachelines.

While some embodiments are discussed herein with reference to an x86 architecture, embodiments are not limited to this architecture and other cacheline sizes may be used (such as 64 bit, 128 bit, etc.). Also, instead of a padded array it is possible to use some other data structure, for example the VMCS could have a pointer to a memory structure with VCPU specific data and the control flag could be located there. This would also avoid the false sharing problems that the padding is avoiding.

Hence, when a VCPU is not currently scheduled by the host, another VCPU uses the MTRIGGER intercept to wake up the sleeping VCPU. Otherwise a VCPU executing a guest MWAIT may be woken up directly through a memory write by MONITOR/MWAIT snooping (operation406). In an embodiment, the MWAIT instruction is enhanced to wait for the configured timeout312in a low power state if enabled. After the timeout expires, the MWAIT instruction exits to the hypervisor.

In at least one embodiment, a virtualized idle loop that is woken up by an Input/Output (“IO” or “I/O”) interrupt may include the following operations:(1) hypervisor intercepts a halt (HLT) event (e.g., to stop execution);(2) hypervisor drops the processor core/VCPU by context switching to one of its own idle loops or another task;(3) once an TO interrupt or another indication that TO finished, such as polling finds a finished TO operation, occurs on a host VM, it wakes up the sleeping guest VM;(4) hypervisor enters the guest VM and injects the TO interrupt; and(5) guest VM executes its assigned tasks.

Phases (2) to (5) above may take a significant percentage of time than the total TO wait time on fast TO devices, in extreme cases even longer than the fast TO delays in some implementations.

In one embodiment, a virtualized idle loop that is woken up by another VCPU in a guest VM may include the following operations:(1) guest executes HLT;(2) hypervisor intercepts HLT;(3) hypervisor puts the processor core/VCPU to sleep by context switching to idle or to another task;(4) another VCPU in the guest VM sends an IPI wakeup interrupt through a virtualized APIC;(5) the virtualized APIC in the hypervisor wakes up the sleeping VCPU; and(6) the original VCPU is entered and continues executing.

In an embodiment, the virtualized idle loop is replaced by the following operations:(1) hypervisor configures an MWAIT instruction delay value (e.g., stored in the VMCS302) and configures a pointer (e.g., pointer304) to a cacheline padded array of wakeup pointers (one for each VCPU);(2) guest VM executes a MONITOR instruction to arm snooping hardware;(3) guest VM executes the MWAIT instruction to enter sleep;

When another VCPU tries to wake up that sleeping VCPU:(4) the other VCPU tries to wake up the original/sleeping VCPU using the MTRIGGER instruction specifying the target VCPU;(5) MTRIGGER instruction writes to the array entry of the target VCPU in memory;(6) the original VCPU detects the snoop on the array entry and wakes up, continuing guest VM execution without entering the hypervisor;

When the idle period is interrupted by an IO interrupt:(7) the IO interrupt interrupts a host CPU, and then the interrupt handler of the host CPU determines the correct VCPU to wake up and wakes up that VCPU;

When no interrupt or wakeup occurs within the configured timeout:(8) the MWAIT instruction triggers an exit to the hypervisor, and the hypervisor then puts the VCPU to sleep.

Additionally, some embodiments may be applied in computing systems that include one or more processors (e.g., where the one or more processors may include one or more processor cores), such as those discussed with reference toFIG.1et seq., including for example a desktop computer, a workstation, a computer server, a server blade, or a mobile computing device. The mobile computing device may include a smartphone, tablet, UMPC (Ultra-Mobile Personal Computer), laptop computer, Ultrabook™ computing device, wearable devices (such as a smart watch, smart ring, smart bracelet, or smart glasses), etc.

Example Computer Architectures

Detailed below are descriptions of example computer architectures. Other system designs and configurations known in the arts for laptop, desktop, and handheld personal computers (PC)s, personal digital assistants, engineering workstations, servers, disaggregated servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand-held devices, and various other electronic devices, are also suitable. In general, a variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

FIG.5illustrates an example computing system. Multiprocessor system500is an interfaced system and includes a plurality of processors or cores including a first processor570and a second processor580coupled via an interface550such as a point-to-point (P-P) interconnect, a fabric, and/or bus. In some examples, the first processor570and the second processor580are homogeneous. In some examples, first processor570and the second processor580are heterogenous. Though the example system500is shown to have two processors, the system may have three or more processors, or may be a single processor system. In some examples, the computing system is a system on a chip (SoC).

Processors570and580are shown including integrated memory controller (IMC) circuitry572and582, respectively. Processor570also includes interface circuits576and578; similarly, second processor580includes interface circuits586and588. Processors570,580may exchange information via the interface550using interface circuits578,588. IMCs572and582couple the processors570,580to respective memories, namely a memory532and a memory534, which may be portions of main memory locally attached to the respective processors.

Processors570,580may each exchange information with a network interface (NW I/F)590via individual interfaces552,554using interface circuits576,594,586,598. The network interface590(e.g., one or more of an interconnect, bus, and/or fabric, and in some examples is a chipset) may optionally exchange information with a coprocessor538via an interface circuit592. In some examples, the coprocessor538is a special-purpose processor, such as, for example, a high-throughput processor, a network or communication processor, compression engine, graphics processor, general purpose graphics processing unit (GPGPU), neural-network processing unit (NPU), embedded processor, or the like.

Network interface590may be coupled to a first interface516via interface circuit596. In some examples, first interface516may be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Express interconnect or another I/O interconnect. In some examples, first interface516is coupled to a power control unit (PCU)517, which may include circuitry, software, and/or firmware to perform power management operations with regard to the processors570,580and/or co-processor538. PCU517provides control information to a voltage regulator (not shown) to cause the voltage regulator to generate the appropriate regulated voltage. PCU517also provides control information to control the operating voltage generated. In various examples, PCU517may include a variety of power management logic units (circuitry) to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or power management source or system software).

PCU517is illustrated as being present as logic separate from the processor570and/or processor580. In other cases, PCU517may execute on a given one or more of cores (not shown) of processor570or580. In some cases, PCU517may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code, sometimes referred to as P-code. In yet other examples, power management operations to be performed by PCU517may be implemented externally to a processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other examples, power management operations to be performed by PCU517may be implemented within BIOS or other system software.

Various I/O devices514may be coupled to first interface516, along with a bus bridge518which couples first interface516to a second interface520. In some examples, one or more additional processor(s)515, such as coprocessors, high throughput many integrated core (MIC) processors, GPGPUs, accelerators (such as graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays (FPGAs), or any other processor, are coupled to first interface516. In some examples, second interface520may be a low pin count (LPC) interface. Various devices may be coupled to second interface520including, for example, a keyboard and/or mouse522, communication devices527and storage circuitry528. Storage circuitry528may be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device which may include instructions/code and data530and may implement the storage103in some examples. Further, an audio I/O524may be coupled to second interface520. Note that other architectures than the point-to-point architecture described above are possible. For example, instead of the point-to-point architecture, a system such as multiprocessor system500may implement a multi-drop interface or other such architecture.

Example Core Architectures, Processors, and Computer Architectures.

FIG.6illustrates a block diagram of an example processor and/or SoC600that may have one or more cores and an integrated memory controller. The solid lined boxes illustrate a processor600with a single core602(A), system agent unit circuitry610, and a set of one or more interface controller unit(s) circuitry616, while the optional addition of the dashed lined boxes illustrates an alternative processor600with multiple cores602(A)-(N), a set of one or more integrated memory controller unit(s) circuitry614in the system agent unit circuitry610, and special purpose logic608, as well as a set of one or more interface controller units circuitry616. Note that the processor600may be one of the processors570or580, or co-processor538or515ofFIG.5.

A memory hierarchy includes one or more levels of cache unit(s) circuitry604(A)-(N) within the cores602(A)-(N), a set of one or more shared cache unit(s) circuitry606, and external memory (not shown) coupled to the set of integrated memory controller unit(s) circuitry614. The set of one or more shared cache unit(s) circuitry606may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, such as a last level cache (LLC), and/or combinations thereof. While in some examples interface network circuitry612(e.g., a ring interconnect) interfaces the special purpose logic608(e.g., integrated graphics logic), the set of shared cache unit(s) circuitry606, and the system agent unit circuitry610, alternative examples use any number of well-known techniques for interfacing such units. In some examples, coherency is maintained between one or more of the shared cache unit(s) circuitry606and cores602(A)-(N). In some examples, interface controller units circuitry616couple the cores602to one or more other devices618such as one or more I/O devices, storage, one or more communication devices (e.g., wireless networking, wired networking, etc.), etc.

In some examples, one or more of the cores602(A)-(N) are capable of multi-threading. The system agent unit circuitry610includes those components coordinating and operating cores602(A)-(N). The system agent unit circuitry610may include, for example, power control unit (PCU) circuitry and/or display unit circuitry (not shown). The PCU may be or may include logic and components needed for regulating the power state of the cores602(A)-(N) and/or the special purpose logic608(e.g., integrated graphics logic). The display unit circuitry is for driving one or more externally connected displays.

The cores602(A)-(N) may be homogenous in terms of instruction set architecture (ISA). Alternatively, the cores602(A)-(N) may be heterogeneous in terms of ISA; that is, a subset of the cores602(A)-(N) may be capable of executing an ISA, while other cores may be capable of executing only a subset of that ISA or another ISA.

Example Core Architectures—In-Order and Out-of-Order Core Block Diagram

InFIG.7(A), a processor pipeline700includes a fetch stage702, an optional length decoding stage704, a decode stage706, an optional allocation (Alloc) stage708, an optional renaming stage710, a schedule (also known as a dispatch or issue) stage712, an optional register read/memory read stage714, an execute stage716, a write back/memory write stage718, an optional exception handling stage722, and an optional commit stage724. One or more operations can be performed in each of these processor pipeline stages. For example, during the fetch stage702, one or more instructions are fetched from instruction memory, and during the decode stage706, the one or more fetched instructions may be decoded, addresses (e.g., load store unit (LSU) addresses) using forwarded register ports may be generated, and branch forwarding (e.g., immediate offset or a link register (LR)) may be performed. In one example, the decode stage706and the register read/memory read stage714may be combined into one pipeline stage. In one example, during the execute stage716, the decoded instructions may be executed, LSU address/data pipelining to an Advanced Microcontroller Bus (AMB) interface may be performed, multiply and add operations may be performed, arithmetic operations with branch results may be performed, etc.

By way of example, the example register renaming, out-of-order issue/execution architecture core ofFIG.7(B)may implement the pipeline700as follows: 1) the instruction fetch circuitry738performs the fetch and length decoding stages702and704; 2) the decode circuitry740performs the decode stage706; 3) the rename/allocator unit circuitry752performs the allocation stage708and renaming stage710; 4) the scheduler(s) circuitry756performs the schedule stage712; 5) the physical register file(s) circuitry758and the memory unit circuitry770perform the register read/memory read stage714; the execution cluster(s)760perform the execute stage716; 6) the memory unit circuitry770and the physical register file(s) circuitry758perform the write back/memory write stage718; 7) various circuitry may be involved in the exception handling stage722; and 8) the retirement unit circuitry754and the physical register file(s) circuitry758perform the commit stage724.

FIG.7(B)shows a processor core790including front-end unit circuitry730coupled to execution engine unit circuitry750, and both are coupled to memory unit circuitry770. The core790may be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core790may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front-end unit circuitry730may include branch prediction circuitry732coupled to instruction cache circuitry734, which is coupled to an instruction translation lookaside buffer (TLB)736, which is coupled to instruction fetch circuitry738, which is coupled to decode circuitry740. In one example, the instruction cache circuitry734is included in the memory unit circuitry770rather than the front-end circuitry730. The decode circuitry740(or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode circuitry740may further include address generation unit (AGU, not shown) circuitry. In one example, the AGU generates an LSU address using forwarded register ports, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode circuitry740may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one example, the core790includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in decode circuitry740or otherwise within the front-end circuitry730). In one example, the decode circuitry740includes a micro-operation (micro-op) or operation cache (not shown) to hold/cache decoded operations, micro-tags, or micro-operations generated during the decode or other stages of the processor pipeline700. The decode circuitry740may be coupled to rename/allocator unit circuitry752in the execution engine circuitry750.

The execution engine circuitry750includes the rename/allocator unit circuitry752coupled to retirement unit circuitry754and a set of one or more scheduler(s) circuitry756. The scheduler(s) circuitry756represents any number of different schedulers, including reservations stations, central instruction window, etc. In some examples, the scheduler(s) circuitry756can include arithmetic logic unit (ALU) scheduler/scheduling circuitry, ALU queues, address generation unit (AGU) scheduler/scheduling circuitry, AGU queues, etc. The scheduler(s) circuitry756is coupled to the physical register file(s) circuitry758. Each of the physical register file(s) circuitry758represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one example, the physical register file(s) circuitry758includes vector registers unit circuitry, writemask registers unit circuitry, and scalar register unit circuitry. These register units may provide architectural vector registers, vector mask registers, general-purpose registers, etc. The physical register file(s) circuitry758is coupled to the retirement unit circuitry754(also known as a retire queue or a retirement queue) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) (ROB(s)) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit circuitry754and the physical register file(s) circuitry758are coupled to the execution cluster(s)760. The execution cluster(s)760includes a set of one or more execution unit(s) circuitry762and a set of one or more memory access circuitry764. The execution unit(s) circuitry762may perform various arithmetic, logic, floating-point or other types of operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some examples may include a number of execution units or execution unit circuitry dedicated to specific functions or sets of functions, other examples may include only one execution unit circuitry or multiple execution units/execution unit circuitry that all perform all functions. The scheduler(s) circuitry756, physical register file(s) circuitry758, and execution cluster(s)760are shown as being possibly plural because certain examples create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating-point/packed integer/packed floating-point/vector integer/vector floating-point pipeline, and/or a memory access pipeline that each have their own scheduler circuitry, physical register file(s) circuitry, and/or execution cluster—and in the case of a separate memory access pipeline, certain examples are implemented in which only the execution cluster of this pipeline has the memory access unit(s) circuitry764). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

In some examples, the execution engine unit circuitry750may perform load store unit (LSU) address/data pipelining to an Advanced Microcontroller Bus (AMB) interface (not shown), and address phase and writeback, data phase load, store, and branches.

The set of memory access circuitry764is coupled to the memory unit circuitry770, which includes data TLB circuitry772coupled to data cache circuitry774coupled to level 2 (L2) cache circuitry776. In one example, the memory access circuitry764may include load unit circuitry, store address unit circuitry, and store data unit circuitry, each of which is coupled to the data TLB circuitry772in the memory unit circuitry770. The instruction cache circuitry734is further coupled to the level 2 (L2) cache circuitry776in the memory unit circuitry770. In one example, the instruction cache734and the data cache774are combined into a single instruction and data cache (not shown) in L2 cache circuitry776, level 3 (L3) cache circuitry (not shown), and/or main memory. The L2 cache circuitry776is coupled to one or more other levels of cache and eventually to a main memory.

The core790may support one or more instructions sets (e.g., the x86 instruction set architecture (optionally with some extensions that have been added with newer versions); the MIPS instruction set architecture; the ARM instruction set architecture (optionally with optional additional extensions such as NEON)), including the instruction(s) described herein. In one example, the core790includes logic to support a packed data instruction set architecture extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.

Example Execution Unit(s) Circuitry

FIG.8illustrates examples of execution unit(s) circuitry, such as execution unit(s) circuitry762ofFIG.7(B). As illustrated, execution unit(s) circuitry762may include one or more ALU circuits801, optional vector/single instruction multiple data (SIMD) circuits803, load/store circuits805, branch/jump circuits807, and/or Floating-point unit (FPU) circuits809. ALU circuits801perform integer arithmetic and/or Boolean operations. Vector/SIMD circuits803perform vector/SIMD operations on packed data (such as SIMD/vector registers). Load/store circuits805execute load and store instructions to load data from memory into registers or store from registers to memory. Load/store circuits805may also generate addresses. Branch/jump circuits807cause a branch or jump to a memory address depending on the instruction. FPU circuits809perform floating-point arithmetic. The width of the execution unit(s) circuitry762varies depending upon the example and can range from 16-bit to 1,024-bit, for example. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

FIG.9illustrates examples of an instruction format. As illustrated, an instruction may include multiple components including, but not limited to, one or more fields for: one or more prefixes901, an opcode903, addressing information905(e.g., register identifiers, memory addressing information, etc.), a displacement value907, and/or an immediate value909. Note that some instructions utilize some or all the fields of the format whereas others may only use the field for the opcode903. In some examples, the order illustrated is the order in which these fields are to be encoded, however, it should be appreciated that in other examples these fields may be encoded in a different order, combined, etc.

The prefix(es) field(s)901, when used, modifies an instruction. In some examples, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), to provide section overrides (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), to perform bus lock operations, and/or to change operand (e.g., 0x66) and address sizes (e.g., 0x67). Certain instructions require a mandatory prefix (e.g., 0x66, 0xF2, 0xF3, etc.). Certain of these prefixes may be considered “legacy” prefixes. Other prefixes, one or more examples of which are detailed herein, indicate, and/or provide further capability, such as specifying particular registers, etc. The other prefixes typically follow the “legacy” prefixes.

The opcode field903is used to at least partially define the operation to be performed upon a decoding of the instruction. In some examples, a primary opcode encoded in the opcode field903is one, two, or three bytes in length. In other examples, a primary opcode can be a different length. An additional 3-bit opcode field is sometimes encoded in another field.

The addressing information field905is used to address one or more operands of the instruction, such as a location in memory or one or more registers.FIG.10illustrates examples of the addressing information field905. In this illustration, an optional MOD R/M byte1002and an optional Scale, Index, Base (SIB) byte1004are shown. The MOD R/M byte1002and the SIB byte1004are used to encode up to two operands of an instruction, each of which is a direct register or effective memory address. Note that both of these fields are optional in that not all instructions include one or more of these fields. The MOD R/M byte1002includes a MOD field1042, a register (reg) field1044, and R/M field1046.

The content of the MOD field1042distinguishes between memory access and non-memory access modes. In some examples, when the MOD field1042has a binary value of 11 (11b), a register-direct addressing mode is utilized, and otherwise a register-indirect addressing mode is used.

The register field1044may encode either the destination register operand or a source register operand or may encode an opcode extension and not be used to encode any instruction operand. The content of register field1044, directly or through address generation, specifies the locations of a source or destination operand (either in a register or in memory). In some examples, the register field1044is supplemented with an additional bit from a prefix (e.g., prefix901) to allow for greater addressing.

The R/M field1046may be used to encode an instruction operand that references a memory address or may be used to encode either the destination register operand or a source register operand. Note the R/M field1046may be combined with the MOD field1042to dictate an addressing mode in some examples.

The SIB byte1004includes a scale field1052, an index field1054, and a base field1056to be used in the generation of an address. The scale field1052indicates a scaling factor. The index field1054specifies an index register to use. In some examples, the index field1054is supplemented with an additional bit from a prefix (e.g., prefix901) to allow for greater addressing. The base field1056specifies a base register to use. In some examples, the base field1056is supplemented with an additional bit from a prefix (e.g., prefix901) to allow for greater addressing. In practice, the content of the scale field1052allows for the scaling of the content of the index field1054for memory address generation (e.g., for address generation that uses 2scale*index+base).

Some addressing forms utilize a displacement value to generate a memory address. For example, a memory address may be generated according to 2scale*index+base+displacement, index*scale+displacement, r/m+displacement, instruction pointer (RIP/EIP)+displacement, register+displacement, etc. The displacement may be a 1-byte, 2-byte, 4-byte, etc. value. In some examples, the displacement field907provides this value. Additionally, in some examples, a displacement factor usage is encoded in the MOD field of the addressing information field905that indicates a compressed displacement scheme for which a displacement value is calculated and stored in the displacement field907.

In some examples, the immediate value field909specifies an immediate value for the instruction. An immediate value may be encoded as a 1-byte value, a 2-byte value, a 4-byte value, etc.

In this description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of skill in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of the present embodiments.

The following examples pertain to further embodiments. Example 1 includes 1 includes an apparatus comprising: decoder circuitry to decode a single instruction, the single instruction to include a field for an identifier of a first source operand, a field for an identifier of a second source operand, a field for an identifier of a destination operand, and a field for an opcode, and execution circuitry to execute the decoded instruction according to the opcode to: write the first source operand to a memory location identified by the second source operand; compute an index into a control array based at least in part on the destination operand and an element size of the control array; and determine whether to exit to a hypervisor of a Virtual Machine (VM) based at least in part on data stored at a location in the control array, wherein the location is to be identified by the computed index.

Example 2 includes the apparatus of example 1, wherein the field for the identifier of the first source operand is to identify a value. Example 3 includes the apparatus of example 1, wherein the field for the identifier of the second source operand is to identify a memory address. Example 4 includes the apparatus of example 1, wherein a first Virtual Central Processing Unit (VCPU) is to execute a first instruction to enable execution of the single instruction and cause the first VCPU to enter a low power consumption state. Example 5 includes the apparatus of example 4, wherein the first instruction comprises a Monitor Wait (MWAIT) instruction. Example 6 includes the apparatus of example 4, wherein a second VCPU is to execute the single instruction in response to a determination that execution of the single instruction is enabled.

Example 7 includes the apparatus of example 6, wherein the second VCPU is to cause the first VCPU to exit the low power consumption state in response to detection of an exit event. Example 8 includes the apparatus of example 1, wherein the field for the identifier of the destination operand is to identify a target processor core. Example 9 includes the apparatus of example 1, wherein the field for the identifier of the destination operand is to identify an Advanced Programmable Interrupt Controller (APIC) identifier of a target processor core. Example 10 includes the apparatus of example 1, wherein a VM Control Structure (VMCS) is to store one or more of: a pointer to the control array, a control array limit, a control bit to indicate whether execution of the single instruction is enabled, and a timeout configuration setting. Example 11 includes the apparatus of example 10, wherein a first VCPU is to execute a first instruction to enable execution of the single instruction and cause the first VCPU to enter a low power consumption state, wherein the timeout configuration setting is to indicate a timeout period for the first VCPU to exit the low power consumption state.

Example 12 includes a processor comprising: decoder circuitry to decode a single instruction, the single instruction to include a first field for a value, a second field for a memory address, a third field for an identifier of a target processor core, and a fourth field for an opcode, and execution circuitry to execute the decoded instruction according to the opcode to: write the value to a memory location identified by the memory address; compute an index into a control array based at least in part on the identifier and an element size of the control array; and determine whether to exit to a hypervisor of a Virtual Machine (VM) based at least in part on data stored at a location in the control array, wherein the location is to be identified by the computed index.

Example 13 includes the processor of example 12, wherein a first Virtual Central Processing Unit (VCPU) is to execute a first instruction to enable execution of the single instruction and cause the first VCPU to enter a low power consumption state. Example 14 includes the processor of example 13, wherein the first instruction comprises a Monitor Wait (MWAIT) instruction. Example 15 includes the processor of example 13, wherein a second VCPU is to execute the single instruction in response to a determination that execution of the single instruction is enabled. Example 16 includes the processor of example 15, wherein the second VCPU is to cause the first VCPU to exit the low power consumption state in response to detection of an exit event. Example 17 includes the processor of example 13, wherein the identifier is to identify an Advanced Programmable Interrupt Controller (APIC) identifier of the target processor core. Example 18 includes the processor of example 13, wherein a VM Control Structure (VMCS) is to store one or more of: a pointer to the control array, a control array limit, a control bit to indicate whether execution of the single instruction is enabled, and a timeout configuration setting. Example 19 includes the processor of example 18, wherein a first VCPU is to execute a first instruction to enable execution of the single instruction and cause the first VCPU to enter a low power consumption state, wherein the timeout configuration setting is to indicate a timeout period for the first VCPU to exit the low power consumption state.

Example 20 includes one or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to: decode a single instruction, the single instruction to include a field for an identifier of a first source operand, a field for an identifier of a second source operand, a field for an identifier of a destination operand, and a field for an opcode, and execute the decoded instruction according to the opcode to: write the first source operand to a memory location identified by the second source operand; compute an index into a control array based at least in part on the destination operand and an element size of the control array; and determine whether to exit to a hypervisor of a Virtual Machine (VM) based at least in part on data stored at a location in the control array, wherein the location is to be identified by the computed index.

Example 21 includes the one or more computer-readable media of example 20, wherein the field for the identifier of the first source operand is to identify a value. Example 22 includes the one or more computer-readable media of example 20, wherein the field for the identifier of the second source operand is to identify a memory address. Example 23 includes the one or more computer-readable media of example 20, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause a first Virtual Central Processing Unit (VCPU) to execute a first instruction to enable execution of the single instruction and cause the first VCPU to enter a low power consumption state. Example 24 includes the one or more computer-readable media of example 20, wherein the field for the identifier of the destination operand is to identify a target processor core. Example 25 includes the one or more computer-readable media of example 20, wherein the field for the identifier of the destination operand is to identify an Advanced Programmable Interrupt Controller (APIC) identifier of a target processor core.

Example 26 includes an apparatus comprising means to perform a method as set forth in any preceding example. Example 27 includes machine-readable storage including machine-readable instructions, when executed, to implement a method or realize an apparatus as set forth in any preceding example.

In various embodiments, one or more operations discussed with reference toFIG.1et seq. may be performed by one or more components (interchangeably referred to herein as “logic”) discussed with reference to any of the figures.

Further, While various embodiments described herein use the term System-on-a-Chip or System-on-Chip (“SoC” or “SOC”) to describe a device or system having a processor and associated circuitry (e.g., Input/Output (“I/O”) circuitry, power delivery circuitry, memory circuitry, etc.) integrated monolithically into a single Integrated Circuit (“IC”) die, or chip, the present disclosure is not limited in that respect. For example, in various embodiments of the present disclosure, a device or system can have one or more processors (e.g., one or more processor cores) and associated circuitry (e.g., Input/Output (“I/O”) circuitry, power delivery circuitry, etc.) arranged in a disaggregated collection of discrete dies, tiles and/or chiplets (e.g., one or more discrete processor core die arranged adjacent to one or more other die such as memory die, I/O die, etc.). In such disaggregated devices and systems, the various dies, tiles and/or chiplets can be physically and/or electrically coupled together by a package structure including, for example, various packaging substrates, interposers, active interposers, photonic interposers, interconnect bridges, and the like. The disaggregated collection of discrete dies, tiles, and/or chiplets can also be part of a System-on-Package (“SoP”).

Additionally, such computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals provided in a carrier wave or other propagation medium via a communication link (e.g., a bus, a modem, or a network connection).

Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, and/or characteristic described in connection with the embodiment may be included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.