Almost defect-free active channel region

A FinFET includes a fin and a conductive gate surrounding a top channel region of the fin, the channel region of the fin being filled with an epitaxial semiconductor channel material extending below a bottom surface of the conductive gate. The top channel region of the fin includes epitaxial semiconductor channel material that is at least majority defect free, the at least a majority of defects associated with forming the epitaxial semiconductor material in the channel region being trapped below a top portion of the channel region. The FinFET may be achieved by a method, the method including providing a starting semiconductor structure, the starting semiconductor structure including a bulk semiconductor substrate, semiconductor fin(s) on the bulk semiconductor substrate and surrounded by a dielectric layer, and a dummy gate over a channel region of the semiconductor fin(s). The method further includes forming source and drain recesses adjacent the channel region, removing the dummy gate, recessing the semiconductor fin(s), the recessing leaving a fin opening above the recessed semiconductor fin(s), and growing epitaxial semiconductor channel material in the fin opening, such that at least a majority of defects associated with the growing are trapped at a bottom portion of the at least one fin opening.

BACKGROUND OF THE INVENTION

Technical Field

The present invention generally relates to FinFET fabrication. More particularly, the present invention relates to fabricating a FinFET with almost defect-free active channel region.

Background Information

Currently, FinFET fabrication includes many steps. For example, epitaxial semiconductor material is sometimes used atop the channel region. Defects at the interface with the fin, due to different lattice constants, can cause significant performance degradation.

SUMMARY

Thus, a need exists to minimize or eliminate defects in epitaxial semiconductor channel material.

The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a method of fabricating a semiconductor structure. The method includes providing a starting semiconductor structure, the starting semiconductor structure including a bulk semiconductor substrate, at least one semiconductor fin on the bulk semiconductor substrate that is surrounded by a dielectric layer, and a dummy gate over a channel region of the at least one semiconductor fin. The method further includes forming source and drain recesses adjacent the channel region, filling the source and drain recesses with a dielectric material, removing the dummy gate, recessing the channel region of the at least one semiconductor fin, the recessing leaving a fin opening above the recessed at least one semiconductor fin, and growing epitaxial semiconductor channel material in the fin opening, such that at least a majority of defects associated with the growing are trapped at a bottom portion of the fin opening.

In accordance with another aspect, a method is provided. The method includes providing a bulk semiconductor substrate, forming a plurality of fins on the bulk semiconductor substrate, and forming a plurality of channels, replacing channel regions of the plurality of fins, with epitaxial semiconductor channel material having at least a majority of defects associated with the forming of the plurality of channels being trapped at a bottom portion of the plurality of channels, top portions of the plurality of channels being active channel regions and almost defect-free.

In accordance with yet another aspect, a FinFET is provided. The FinFET includes a substrate, a fin on the substrate, the fin having a source region, a drain region and a channel region therebetween, the channel region having a non-epitaxial original portion on the substrate and a region of epitaxial semiconductor channel material on the non-epitaxial original portion, and a conductive gate surrounding a top portion of the region of epitaxial semiconductor channel material, the region of epitaxial semiconductor channel material extending below the conductive gate. Defects associated with forming the epitaxial semiconductor channel material in the region are trapped below the top portion of the region of epitaxial semiconductor channel material.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

As used herein, the term “connected,” when used to refer to two physical elements, means a direct connection between the two physical elements. The term “coupled,” however, can mean a direct connection or a connection through one or more intermediary elements.

As used herein, unless otherwise specified, the term “about” used with a value, such as measurement, size, etc., means a possible variation of plus or minus five percent of the value.

As used herein, the term “epitaxial channel material” refers to any silicon-containing materials, non-limiting examples including silicon, single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon on nothing, silicon on insulator and silicon germanium. The channel may also include other materials such as germanium (Ge), and compound semiconductors, such as Silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide, indium phosphide, indium arsenide or indium antimonide or other compounds from periods III and V of the periodic table, or combinations thereof.

Reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers are used throughout different figures to designate the same or similar components.

FIGS. 1A-1Cinclude two cross-sectional views (FIGS. 1B and 1C) and a top-down view (FIG. 1A) of one example of a starting semiconductor structure100, the starting semiconductor structure including a bulk semiconductor substrate102, a semiconductor fin104on the substrate and surrounded by a dielectric material105, and a dummy gate106(e.g., polysilicon) over a channel region108of the fin, in accordance with one or more aspects of the present invention.

The starting structure may be conventionally fabricated, for example, using known processes and techniques. Although only a portion is shown for simplicity, it will be understood that, in practice, many such structures are typically included on the same bulk substrate.

FIGS. 2A-2Cdepict one example of two cross-sectional views (FIGS. 2B and 2C) and a top-down view (FIG. 2A) of the structure100ofFIGS. 1A-1Cafter recessing to form source/drain openings110and112on opposite sides of the channel region108, in accordance with one or more aspects of the present invention.

At this point, a silicon etch (RIE with CF4 or SF6 for example) is used to anisotropically etch down fin104down to the bottom of the fin or approximately even with the depth of oxide layer105. The fin height is decided earlier in the process during the formation of fin104. If the fin is on SOI, for example, then the etch would continue down to the buried oxide (BOX). The fin remaining underneath the dummy gate is the channel region, and the source and drain regions of the fin are etched back and removed by this etch. They are later re-grown by epitaxy later in the process as subsequently described with regard toFIGS. 9A-9C.

FIGS. 3A-3Cdepict one example of two cross-sectional views (FIGS. 3B and 3C) and a top-down view (FIG. 3A) of the structure ofFIGS. 2A-2Cafter forming additional dielectric material114in the source and drain openings110and112, respectively, as well as forming the additional dielectric material adjacent the dummy gate106, in accordance with one or more aspects of the present invention.

Forming the additional dielectric material114(e.g., an oxide) may be accomplished, for example, using a deposition process. In another example, the additional dielectric material is overfilled, then planarized to a top of the dummy gate106, for example, using a chemical-mechanical polishing process.

FIGS. 4A-4Cdepict one example of two cross-sectional views (FIGS. 4B and 4C) and a top-down view (FIG. 4A) of the structure ofFIGS. 3A-3Cafter removing the dummy gate106and partially recessing the fin104, leaving a remaining fin portion116along with fin opening118and a gate opening120, in accordance with one or more aspects of the present invention.

The fin should be recessed substantially more than half the height of the fin. In a typical example, the total fin height can be 40 nm tall. In this case the fin would be recessed down about 30 nm, leaving about 10 nm remaining. Recessing within these parameters should leave enough remaining fin on which to grow epitaxial material, since a “template” is needed to grow from. The lowest useful remaining fin height is about 10 nm. Therefore, the fin recess leaves about 10 nm remaining, or more generally, substantially less than half the original fin height.

FIGS. 5A-5Cdepict one example of two cross-sectional views (FIGS. 5B and 5C) and a top-down view (FIG. 5A) of the structure ofFIGS. 4A-4Cafter overgrowing epitaxial semiconductor channel material122on a top surface124of remaining fin portion116in the fin opening (118,FIGS. 4B and 4C) and the gate opening (120,FIGS. 4A-4C), such that at least a majority of defects126which may occur in the epitaxial semiconductor channel material during growth as being described below, would be naturally concentrated near an interface with the remaining fin portion, leaving almost defect-free epitaxial semiconductor channel material in an active portion127of the channel opposite the defects, in accordance with one or more aspects of the present invention. The defects are due to the different lattice constants of the epitaxial semiconductor channel material and the fin.

“Defects,” as used herein, refers to crystallographic defects or regions in the semiconductor crystal where the precisely oriented atomic structure is disrupted (usually by stress or other atoms in the lattice). For example, epitaxial channel material is grown on top of the remaining fin portion116. If a channel epitaxy film of Germanium is then grown, for example, the Ge to Ge spacing of the atoms is different than the spacing of silicon to silicon atoms. This means that as the atoms of Ge try to bond and align to the silicon atoms already present, they will be under a lot of strain, since they want to have a different spacing than the silicon atoms allow. Once the growing film becomes thick enough, the strain is too much for the film to contain, so a small break or dislocation in the crystal forms. This is what is meant by “defects.” These are often long in length and the present disclosure allows for those defects to form, but then they travel far enough to terminate the dielectric material114. After those defects terminate at an interface, they cannot move any further. Therefore, the rest of the film above that area is now at least majority defect free and possibly fully defect-free since it may be 100% Ge in this case, and can grow without further defects.

FIGS. 6A-6Cdepict one example of two cross-sectional views (FIGS. 6B and 6C) and a top-down view (FIG. 6A) of the structure ofFIGS. 5A-5Cafter recessing128the epitaxial semiconductor channel material122, reestablishing gate opening120, in accordance with one or more aspects of the present invention. The recess may be accomplished, for example, using conventional processes and techniques. For example, a dry etch or RIE or plasma etch using a precursor such as CF4would etch many of the channel films. A specific wet etch, such as NH4OH, would also etch many silicon compounds. In practice, selectivity to the dielectrics surrounding the epitaxial channel is employed, such that selectivity will determine the exact chemistry or conditions used.

FIGS. 7A-7Cdepict one example of two cross-sectional views (FIGS. 7B and 7C) and a top-down view (FIG. 7A) of the structure ofFIGS. 6A-6Cafter recessing130the dielectric material105adjacent a top (active) portion127of the epitaxial semiconductor channel material122under gate opening120, in accordance with one or more aspects of the present invention.

FIGS. 8A-8Cdepict one example of two cross-sectional views (FIGS. 8B and 8C) and a top-down view (FIG. 8A) of the structure ofFIGS. 7A-7Cafter forming another dummy gate134surrounding the top (active) portion127of the epitaxial semiconductor channel material122, in accordance with one or more aspects of the present invention.

FIGS. 9A-9Cdepict one example of two cross-sectional views (FIGS. 9B and 9C) and a top-down view (FIG. 9A) of the structure ofFIGS. 8A-8Cafter recessing136dielectric material114down to a bottom of the active portion127, and growing epitaxial semiconductor material138adjacent opposite sides of the top (active) portion127of the epitaxial semiconductor channel material122, forming source140and drain142, in accordance with one or more aspects of the present invention.

In one example, the epitaxial semiconductor material138of the source140and drain142may be grown, for example, using lateral growth from the channel sidewalls.

FIGS. 10A-10Cdepict one example of two cross-sectional views (FIGS. 10B and 10C) and a top-down view (FIG. 10A) of the structure ofFIGS. 9A-9Cafter replacing the dummy gate (134, any ofFIGS. 9A-9C) with a conductive gate144and filling around the gate with additional dielectric material146(e.g., an interlayer dielectric), in accordance with one or more aspects of the present invention. In one example, the conductive gate includes a conductive metal (e.g., tungsten). In another example, just prior to forming the replacement metal gate, the gate trench may be lined with a gate dielectric material, for example, a high-k gate dielectric (i.e., k>3.9).

In a first aspect, disclosed above is a method. The method includes providing a starting semiconductor structure, the starting semiconductor structure including a bulk semiconductor substrate, a semiconductor fin(s) on the semiconductor substrate that is surrounded by a dielectric layer, and a dummy gate over a channel region of the semiconductor fin(s). The method further includes forming source and drain recesses adjacent the channel region, filling the source and drain recesses with a dielectric material, removing the dummy gate, recessing the channel region of the semiconductor fin, the recessing leaving a fin opening(s) above the recessed fin(s), and growing epitaxial semiconductor channel material in the fin opening(s), such that at least a majority of defects associated with the growing are trapped at a bottom portion of the fin opening(s).

In one example, the growing may include, for example, over-growing the epitaxial semiconductor channel material, the over-growing filling space left by removing the dummy gate, and recessing the epitaxial semiconductor channel material, the recessing reopening the space of the dummy gate and resulting in recessed epitaxial semiconductor channel material. In one example, the method may further include, for example, forming another dummy gate surrounding a top portion of the recessed epitaxial semiconductor channel material after recessing the epitaxial semiconductor channel material, removing the dielectric material of the source and drain regions, resulting in new source and drain recesses, and forming a source and drain in the new source region and drain recesses, respectively. In one example, forming another dummy gate may include, for example, recessing portions of the dielectric layer surrounding the top portion of the recessed epitaxial semiconductor channel material, the recessing of the dielectric layer forming another dummy gate opening, and filling the another dummy gate opening with dummy gate material.

In one example, the method may further include, for example, replacing the another dummy gate with a conductive gate after forming the source and drain in the new source and drain recesses.

In a second aspect, disclosed above is a method. The method includes providing a bulk semiconductor substrate, forming fins on the bulk semiconductor substrate, forming channels, replacing channel regions of the fins with epitaxial semiconductor channel material having at least a majority of defects associated with the forming of the channels being trapped at a bottom portion of the channels, top portions of the channels being active channel regions and almost defect-free.

In one example, the method of the second aspect may further include, for example, forming a dummy gate surrounding only the active channel regions. In one example, the semiconductor substrate provided may include, for example, a bulk semiconductor substrate, and forming the channels with at least a majority of defects trapped at a bottom portion of the channels may include, for example, partially recessing the channel regions of the fins, the partially recessing resulting in channel region openings, and filling the channel region openings with the epitaxial semiconductor channel material, such that the defects are trapped at a bottom portion of the filled channel region openings.

In a third aspect, disclosed above is a FinFET. The FinFET includes a fin, and a conductive gate surrounding a top portion of a channel region of the fin, the channel region of the fin being filled with an epitaxial semiconductor channel material extending below the conductive gate, at least a majority of defects associated with forming the epitaxial semiconductor channel material in the channel region being trapped below the top portion of the channel region.

In one example, the FinFET may further include, for example, a source region and a drain region on opposite sides of the top portion of the channel region.

In one example, the conductive gate of the FinFET of the third aspect may include, for example, conductive metal(s). In one example, the conductive metal(s) may include, for example, tungsten.

In one example, the FinFET of the third aspect may further include, for example, a gate dielectric between the conductive gate and the top portion of the channel region. In one example, the gate dielectric may include, for example, a high-k gate dielectric.

In one example, a lower portion of the channel region of the FinFET of the third aspect, with the majority of defects trapped therein, may be, for example, surrounded by dielectric material.