Offset correction for passive mixers

A downconversion mixer includes a configurable gate or bulk bias voltage to allow calibration and correction of device offsets. Calibration may be performed on the configurable bias voltages to minimize IM2 distortion in the mixer. The techniques have minimal impact on voltage headroom, impose no requirement for a signal path to be phase-matched with a calibration path, and are particularly well-suited for passive mixers.

TECHNICAL FIELD

The disclosure relates to communications receivers and, more particularly, to offset correction techniques for mixers in communications receivers.

BACKGROUND

In a digital communication system, a receiver receives a radio-frequency (RF) modulated signal from a transmitter. The receiver downconverts the received signal from RF to baseband, digitizes the baseband signal to generate samples, and digitally processes the samples to recover data sent by the transmitter. The receiver may use one or more downconversion mixers to downconvert the received signal from RF to baseband.

An ideal mixer simply translates an input signal from one frequency to another without distortion. In integrated circuits, however, the mixer's performance may deviate from the ideal case due to mismatch between the transistors caused by, e.g., layout or process variations. Such mismatch may introduce distortion into the output of the mixer, leading to unwanted inter-modulation products. For example, in a mixer for a direct conversion receiver, second-order inter-modulation (IM2) products in particular may especially degrade the signal-to-noise ratio (SNR) at baseband. While symmetrical layout and differential signal processing can help reduce the effects of device mismatch, there may still be residual mismatch due to process limitations.

Disclosed herein are techniques to provide for configurable parameters in a mixer to calibrate and correct for such mismatch, thereby minimizing mixer distortion.

SUMMARY

An aspect of the present disclosure provides a receiver apparatus comprising a mixer operative to mix an input radio frequency (RF) signal with a local oscillator (LO) signal to generate a baseband signal, the mixer comprising first and second RF transistors to receive the input RF signal, the mixer further comprising first and second LO transistors to receive the LO signal, at least one of the transistors having a gate bias voltage that is variable in response to a configurable control signal.

Another aspect of the disclosure provides a receiver apparatus comprising: a mixer operative to mix an input radio frequency (RF) signal with a local oscillator (LO) signal to generate a baseband signal, the mixer comprising first and second RF transistors to receive the input RF signal, the mixer further comprising first and second LO transistors to receive the LO signal, at least one of the transistors having a bulk bias voltage that is variable in response to a configurable control signal.

Yet another aspect of the disclosure provides a method for downconverting a received signal, the method comprising providing a configurable control signal to a mixer, the control signal specifying a gate bias voltage of at least one transistor in said mixer; and downconverting said received signal by mixing said received signal with a local oscillator signal.

Yet another aspect of the disclosure provides a method for downconverting a received signal, the method comprising providing a configurable control signal to a mixer, the control signal specifying a bulk bias voltage of at least one transistor in said mixer; and downconverting said received signal by mixing said received signal with a local oscillator signal.

Yet another aspect of the disclosure provides a method for calibrating a mixer, the method comprising providing a signal input to the mixer; initializing at least one gate bias voltage of the mixer, and measuring an output characteristic of the mixer associated with the at least one initialized gate bias voltage; adjusting the at least one gate bias voltage of the mixer, and measuring the output characteristic of the mixer associated with the at least one adjusted gate bias voltage; based on the measured output characteristic of the mixer, determining a preferred setting for the at least one gate bias voltage of the mixer; and storing said preferred setting for use during operation of the mixer.

Yet another aspect of the disclosure provides a method for calibrating first and second mixers in a receiver, the method comprising providing a signal input to the receiver; initializing at least one gate bias voltage of the first mixer, and measuring an output characteristic of the first mixer associated with the at least one initialized gate bias voltage; adjusting the at least one gate bias voltage of the first mixer, and measuring the output characteristic of the first mixer associated with the at least one adjusted gate bias voltage; based on the measured output characteristic of the first mixer, determining a preferred setting for the at least one gate bias voltage of the first mixer; and while setting the at least one gate bias voltage of the first mixer to the preferred setting, repeating the steps of adjusting, measuring and determining for the second mixer.

Yet another aspect of the disclosure provides a method for calibrating a mixer, the method comprising providing a signal input to the mixer; initializing at least one bulk bias voltage of the mixer, and measuring an output characteristic of the mixer associated with the at least one initialized bulk bias voltage; adjusting the at least one bulk bias voltage of the mixer, and measuring the output characteristic of the mixer associated with the at least one adjusted bulk bias voltage; based on the measured output characteristic of the mixer, determining a preferred setting for the at least one bulk bias voltage of the mixer; and storing said preferred setting for use during operation of the mixer.

Yet another aspect of the disclosure provides a method for calibrating first and second mixers in a receiver, the method comprising providing a signal input to the receiver; initializing at least one bulk bias voltage of the first mixer, and measuring an output characteristic of the first mixer associated with the at least one initialized bulk bias voltage; adjusting the at least one bulk bias voltage of the first mixer, and measuring the output characteristic of the first mixer associated with the at least one adjusted bulk bias voltage; based on the measured output characteristic of the first mixer, determining a preferred setting for the at least one bulk bias voltage of the first mixer; and while setting the at least one bulk bias voltage of the first mixer to the preferred setting, repeating the steps of adjusting, measuring and determining for the second mixer.

DETAILED DESCRIPTION

In accordance with the present disclosure, techniques are disclosed for calibrating and correcting offset in mixer devices.

FIG. 1shows a conventional circuit topology for a passive mixer. NoteFIG. 1does not show the details of DC biasing and coupling. InFIG. 1, a first differential voltage V1(V1=V1P−V1N) is mixed with a second differential voltage V2(V2=V2P−V2N) to produce a differential current output IOUT (IOUT=IOUTP−IOUTN, wherein IOUTPis defined as the current flowing out of terminal OUTP, and IOUTNis the current flowing into terminal OUTN). Assuming the transistors are matched, the output current may be approximated as:

where rdsis the resistance between the drain (D) and source (S) (representatively labeled for transistor M1inFIG. 1), μCOXrepresents the transistor device parameter, W and L represent the width and length of each transistor, VTrepresents the threshold voltage, and K represents a constant term. See, e.g., Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits,” (1998), page 341.

In actual integrated circuits, device mismatch may introduce non-linear distortion into the output of the mixer, causing deviation of the mixer's input-output characteristics from the ideal scenario of Eq (1). To address the effects of mismatch, one or more bias voltages of transistors M1-M4may be adjusted according to the present disclosure.

FIG. 2depicts an embodiment wherein the DC gate bias voltages of the transistors are made configurable to correct for mismatch in transistors M1-M4of the mixer. Voltages VGM1, VGM2, VGM3, and VGM4represent the gate bias voltages of each of transistors M1-M4, respectively. The bias voltages may be coupled to the transistor gates by resistors R1-R4, which may nominally have the same resistances. By introducing intentional offsets in the gate bias voltages, mismatch between transistors M1-M4as well as resistors R1-R4can be corrected. InFIG. 2, capacitors C1P1, C1N1, C1P2, C1N2, C2P, and C2Nserve to couple only the AC components of the signals V1and V2to the mixer.

Note thatFIG. 2shows the bulk bias voltage VB to be constant for all transistors. However, the bulk bias voltages may also be made configurable in alternative embodiments described later herein.

In an embodiment, the bias voltages VGM1, VGM2, VGM3, and VGM4may be directly set by externally supplied control signals VC1-VC4as follows:
VGM1=VC1,
VGM2=VC2,
VGM3=VC3, and
VGM4=VC4.  Equations (2)
Thus VC1-VC4allow for four degrees of freedom in configuring the four gate bias voltages.

In alternative embodiments, to simplify calibration, the degrees of freedom may be reduced by making some of the bias voltages non-configurable. In an embodiment, VGM1and VGM3can be made non-configurable, e.g., tied to on-chip voltage references, while VGM2and VGM4can be made independently configurable by control signals VC1and VC2. While this decreases the degrees of freedom in the configuration to two, it also allows for simpler calibration due to the fewer number of parameters.

In another embodiment, the gate bias voltages may be specified as follows:
VGM2=VGM1+VC1, and
VGM4=VGM3+VC2;  Equations (3)
where VGM1and VGM3are non-configurable, and VC1and VC2can be characterized as the configurable bias offset voltages between the transistors in each differential pair.

In yet another embodiment, two out of the four gate bias voltages may be specified as follows:
VGM1=VGM1—nom+VC1, and
VGM3=VGM3—nom+VC2;  Equations (4)
where VGM1—nomand VGM3—nomrepresent nominal values for VGM1and VGM3, respectively. The remaining gate bias voltages VGM2and VGM4may be made non-configurable and set at nominal voltages.

In yet another embodiment, to simplify calibration even further, only one of the four gate bias voltages need be made configurable.

In general, the bias voltages may be specified by the control signal or signals directly as in Equations (2), or indirectly by any linear or non-linear relationship, such as the relationships shown in Equations (3) and (4).

FIG. 3depicts a further embodiment wherein the bulk, rather than the gate, bias voltages of the transistors are made configurable to correct for mismatch in transistors M1-M4of a mixer. Voltages VBM1, VBM2, VBM3, and VBM4represent the bulk bias voltages of each of transistors M1-M4, respectively. By introducing intentional offsets in the bulk bias voltages, mismatch between transistors M1-M4can be corrected. Note thatFIG. 3shows the gate bias voltage VG to be non-configurable for all transistors. However, the gate bias voltages may also be made configurable according to the embodiments previously described herein.

Similar to the description for the gate bias voltages, control signals VC1-VC4may be used to control the bulk bias voltages in four degrees of freedom. The bulk bias voltages may also be configurable in fewer than four degrees of freedom to simplify calibration, as previously described for the gate bias voltages. The control signals may be related to the bulk bias voltages directly or indirectly by any predetermined transformation.

FIG. 4depicts a calibration mechanism for a receiver utilizing a mixer with configurable bias voltages as described herein. During normal operation, an antenna400is connected to a duplexer402via an antenna connector401. The duplexer402allows the antenna400to be shared between a transmit path (TX)450and a receive path (RX)451. During a calibration phase, the antenna connector401can be supplied with a signal Vs. In an embodiment, the antenna400is disconnected from the antenna connector401when Vs is supplied to the antenna connector401. In another embodiment (not shown), Vs can be supplied directly to the antenna400while connected to the antenna connector401, e.g., in the form of electromagnetic radiation. The signal Vs is input to a low-noise amplifier (LNA)404. In yet another embodiment (not shown), Vs can be supplied from the TX450.

The output of the LNA is input to a mixer406, which may support the configurable gate or bulk bias voltages previously described. The mixer406mixes the LNA output with a local oscillator LO (not shown) to generate a mixed signal. In an embodiment, the LO output corresponds to the differential signal V1inFIG. 2or3, and the LNA output corresponds to the differential signal V2. In another embodiment, the LO output and LNA output may be reversed. The output of the mixer406is provided to a baseband processor408. An output from the baseband processor408is supplied to a digital signal processor (DSP)410.

Based on the output of the baseband processor408, the DSP410outputs digital signals414. In an embodiment, the digital signals414may comprise digital representations of the control signals VC1-VC4, or any subset of the control signals previously described herein. The digital signals414may be derived according to a calibration method to minimize IM2 products, to be described later herein, or the signals414may be derived according to any other method for any other purpose, e.g., minimizing other non-IM2 distortion. The digital signals414may be converted to analog voltages416by the digital-to-analog converter (DAC)412. The analog voltages416may be used to configure the bias voltages of the mixer406as described previously herein.

The ranges over which control signals VC1and VC2are adjusted may be determined according to the mapping between the control signals and the specific bias voltage or voltages to be configured. In an embodiment, VC1and VC2adjust the offset between the gate bias voltages of the transistors in a differential pair, e.g., according to Equations (3). VC1may then be configured to range from a minimum of −Vmax—offsetto a maximum of +Vmax—offset, where Vmax—offsetis a parameter related to the full scale range of VC1. VC2can have a range identical to or different from that of VC1.

To specify a range that goes from a negative voltage offset to a positive voltage offset, the DAC412may support signed digital representations of the control signals. In an embodiment, VC1can be represented by an eight-bit value programmed by the DSP410into an eight-bit register in the DAC412. In an embodiment, bits <7:6> of the register can be a code indicating the Vmax—offsetused to determine the full scale range of VC1, and bits <5:0> can specify the signed magnitude of the control signal VC1, with bit <5> being the sign bit. In an embodiment, the mapping of bits <7:6> to Vmax—offsetcan be as follows:

Note the mechanism shown inFIG. 4is meant to illustrate only one embodiment of a calibration mechanism for the configurable mixers disclosed herein. Alternative embodiments may employ fewer or more functional blocks than shown inFIG. 4. In an embodiment, the digital signals414may be generated and supplied directly by the baseband processor408. In an alternative embodiment, they may be generated and supplied by modules not shown, e.g., by a microprocessor.

Note that the DAC412depicted inFIG. 4may support any number of digital control inputs414, and output one or more analog voltages416associated with each digital control input.

FIG. 5depicts an embodiment of a method for calibrating a configurable mixer of the present disclosure to minimize second-order inter-modulation (IM2) products. The steps inFIG. 5are described with reference to the calibration mechanism shown inFIG. 4. However, the method ofFIG. 5is equally applicable to calibration mechanisms other than the one shown inFIG. 4. For example, the method ofFIG. 5does not necessarily require an antenna400or elements other than the mixer406in the underlying calibration mechanism. For example, the method ofFIG. 5may utilize a microprocessor or other computing device in place of the DSP.

In the method ofFIG. 5, the mixer is configurable in two degrees of freedom via control signals VC1and VC2. However, the method can readily be extended to calibrate the mixer with fewer or more degrees of freedom in accordance with the principles disclosed previously herein. VC1and VC2may be used to set, for example, the gate bias voltages VGM1and VGM3as labeled inFIG. 2, or the bulk bias voltages VBM1and VBM3as labeled inFIG. 3.

Referring toFIG. 5, at step500, the calibration mechanism ofFIG. 4may be instructed to receive on a channel near the center of the frequency band of interest, such as 869-894 MHz corresponding to the cellular band, or 1930-1990 MHz corresponding to the personal communications service (PCS) band. This can be done by setting the frequency of the LO (not shown inFIG. 4) to the frequency of the desired channel. The control signals VC1and VC2are both initially set to the minimum values within their respective ranges. At step502, a signal with two frequency tones, f1and f2, is supplied to the input of the LNA as input voltage Vs. In an embodiment, the tones f1and f2lie outside the channel of interest. In an embodiment of a direct conversion receiver for the W-CDMA standard, f1and f2differ by 200 kHz, such that their IM2 product lies within a baseband channel having a 1.92 MHz bandwidth.

In the presence of second-order distortion in the mixer, the output of the mixer will contain a tone at the difference frequency |f1−f2|. At step504, the baseband408measures the power P|f1−f2|of the tone present at the difference frequency |f1−f2|, and supplies the value of P|f1−f2|to the DSP. At step506, the DSP records the value of P|f1−f2|with the associated value of VC1. At step508, the DSP determines whether the value of VC1has been increased to the maximum value within its range. If not, then the DSP increments VC1by a step size at step510, and returns to step504. If VC1has reached the maximum allowed value of VC1, then DSP proceeds to step512. At step512, the DSP analyzes the recorded values of P|f1−f2|for all swept values of VC1, and determines the value of VC1associated with the lowest measured P|f1−f2|. This value of VC1may be referred to as VC1best. Also in step512, the value of VC1may be set at VC1bestfor the remaining steps ofFIG. 5.

FIG. 5Bdepicts a hypothetical P|f1−f2|vs. VC1relationship to illustrate the parameters cited above. NoteFIG. 5Bis provided for illustrative purposes only, and is not meant to limit the disclosed techniques to devices or parameters having any particular transfer characteristics.

Note the method ofFIG. 5may be designed to optimize for parameters other than or in addition to IM2 by simply replacing the checking for minimum P|f1−f2|with checking for a desired characteristic or characteristics of some other parameter or parameters.

Returning toFIG. 5, VC2is next swept over a predetermined range while VC1is held constant at VC1best. In particular, step514initially commences with VC2set to the minimum value within its allowable range. At step514, the baseband again measures the power present at the difference frequency, and supplies the measured power value P|f1−f2|to the DSP. At step516, the DSP records the measured P|f1−f2|with the associated value of VC2. At step518, the DSP determines whether the value of VC2has been increased to the maximum within its range. If not, the DSP increments VC2at step520and returns to step514. If VC2has reached the maximum allowed value of VC2, then the DSP proceeds to step522. At step522, the DSP analyzes the recorded values of P|f1−f2|for all swept values of VC2, and determines the value of VC2associated with the lowest measured P|f1−f2|. This value of VC2may be referred to as VC2best. Once VC2bestis determined, the radio may exit calibration mode, and commence (or resume) normal operation. In an embodiment, during normal operation, the control signals VC1bestand VC2bestmay be continuously supplied to the DAC to configure the bias voltages of the mixer as previously described herein.

In an embodiment, VC1and VC2can each be incremented by a step size equal to the minimum resolution of the DAC during calibration. For example, in an embodiment wherein bits <5:0> of the DAC register specify the signed magnitude of VC1, the step size can be the voltage difference associated with the least-significant bit of bits <5:0>.

In an alternative embodiment, to speed up calibration, the step size may be larger than the minimum resolution of the DAC. In this embodiment, the setting for VC1bestcorresponding to the lowest IM2 product for the mixer may not be present in the recorded values of VC1vs. P|f1−f2|, as the best setting may have been “skipped” due to the larger step size. In this case, VC1bestmay be determined by averaging the two values of VC1corresponding to the lowest and second-lowest values of P|f1−f2|. Alternatively, a predetermined offset may be added to the determined VC1bestto derive the actual control input supplied to the mixer.

FIG. 5Adepicts an alternative embodiment of a method for calibrating a configurable mixer of the present disclosure employing a potentially abbreviated number of steps compared toFIG. 5. Steps inFIG. 5Acorrespond to similarly labeled steps inFIG. 5, with noted differences in steps508A and518A. In the embodiment ofFIG. 5A, rather than checking for whether the value of VC1has been increased to a maximum at a step508, the method at a step508A checks whether the currently measured value of P|f1−f2|is more than the previously measured value of P|f1−f2|. If so, the method advances to the calibration of VC2, without sweeping through the remaining values of VC1. The value of VC1corresponding to the P|f1−f2|measured prior to the detected increase can be taken as VC1best. A similar check can be performed for VC2at step518A. This embodiment effectively treats the local minimum for the measured P|f1−f2|as the global minimum. This may speed up the calibration, as the desired values for VC1and VC2may be determined without sweeping through the entire range of either parameter.

Note the methods depicted inFIGS. 5 and 5Acan be readily applied to calibrate mixers having more or less than two configurable degrees of freedom by, for example, providing more or fewer steps than are shown. For example, in an embodiment, wherein only one control signal VC1is used to configure a mixer, the method ofFIG. 5may be terminated after step512. In another embodiment, four control signals VC1-VC4may be determined by adding steps beyond522for determining VC3and VC4, while holding the previously optimized degrees of freedom constant at their determined optimum values.

Note the calibration described inFIGS. 5 and 5Amay be performed whenever the signal input Vs is known. In an embodiment, calibration can be done at the factory, when a chip is tested prior to shipping. In an embodiment, calibration can be done during normal operation as follows. Where full duplexing is supported (i.e., simultaneous transmission and reception by a single radio), TX450may transmit Vs, which is coupled to RX451through the residual coupling of the duplexer402. Note TX450may transmit Vs at a suitably high power level to overcome attenuation between the transmit path and receive path introduced by, for example, the duplexer402and/or TX/RX filters (not shown).

In an embodiment, steps in addition to those shown inFIG. 5may be provided to further optimize IM2 for the mixer.FIG. 6depicts one embodiment of a method that successively iterates an arbitrary number of times n to determine optimum control signals VC1best(n) and VC2best(n). At step600, n is initialized to zero, and VC1and VC2may be initialized to the minimum voltages in their respective ranges VC1minand VC2min. At step602, VC2is held constant, while VC1is swept over its range to locate a best setting VC1best(1). In an embodiment, the sweep can be done according to the method shown in eitherFIG. 5or5A. In other embodiments, other methods for determining VC1bestmay be applied. At step604, VC1is held constant at VC1best(1), and VC2is swept over its range to locate a best setting VC2best(1). At step606, n is iterated by 1 to n=1, and steps602-604may be repeated (i.e., looped).

Note the method shown inFIG. 6may generally be terminated at any arbitrary point in the loop. In an embodiment, the method is terminated when n reaches 1, i.e., only one iteration of the loop is run. In another embodiment, the method is terminated after step702with n=1, i.e., one-and-a-half iterations of the loop are run. In another embodiment, the method is terminated when the measured value of P|f1−f2|for a newly determined VC1best(n) or VC2best(n) differs from the measured value of P|f1−f2|for a previous VC1best(n−1) or VC2best(n−1), respectively, by an amount less than a predetermined threshold.

Note the method depicted inFIG. 6can be readily applied to calibrate mixers having more than two configurable degrees of freedom by, for example, adding additional steps within the loop shown.

FIG. 7depicts an embodiment of a calibration mechanism for a radio having two mixers, e.g., a mixer for the in-phase (I) path and a mixer for the quadrature-phase (Q) path.FIG. 7shows an antenna700coupled to a duplexer702via antenna connector701. The LNA704output is provided to both an I mixer706A and a Q mixer706B. Each mixer can be made configurable according to the embodiments disclosed herein. The outputs of the mixers706A and706B are provided to the baseband708, and the baseband708provides signals to the DSP710. The DSP710generates digital signals VCI and VCQ714. VCI may comprise one or more control signals to configure the I mixer706A according to the present disclosure, and VCQ may likewise comprise one or more control signals to configure the Q mixer706B. Digital signals714are supplied to the DAC712, which converts the digital signals714to two sets of analog voltages716A and716B. Analog voltages716A are used to configure the I mixer706A, while analog voltages716B are used to configure the I mixer706B according to the techniques previously disclosed herein.

FIG. 8depicts an embodiment of a method for calibrating the I/Q mixers shown inFIG. 7. At step800, VCI and VCQ are initialized. At step802, an input signal Vs containing two tones is supplied to the LNA704inFIG. 7. At step804, best control signal or signals VCIbestare determined for the I mixer706A. Step804may utilize a method previously disclosed herein, or any other method, for deriving VCIbest. At step806, best control signal or signals VCQbestare determined for the Q mixer706B, while VCI is held at VCIbest.

In an embodiment, the method ofFIG. 8may be further augmented by having step806loop back to step804, and determining a new value for VCIbestwhile holding VCQ fixed at VCQbest. This may be done an arbitrary number of times to obtain an optimal configuration for the control signals.

Note the techniques of the present disclosure need not be limited to passive mixers. Active mixers such as those employing Gilbert multipliers may also employ the techniques disclosed. The appropriate modifications will be clear to those of ordinary skill in the art, and are contemplated to be within the scope of the present disclosure.

Based on the teachings described herein, it should be apparent that an aspect disclosed herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. The techniques described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, the techniques may be realized using digital hardware, analog hardware or a combination thereof. If implemented in software, the techniques may be realized at least in part by a computer-program product that includes a computer readable medium on which one or more instructions or code is stored.

By way of example, and not limitation, such computer-readable media can comprise RAM, such as synchronous dynamic random access memory (SDRAM), read-only memory (ROM), non-volatile random access memory (NVRAM), ROM, electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), FLASH memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other tangible medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

The instructions or code associated with a computer-readable medium of the computer program product may be executed by a computer, e.g., by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuitry.

A number of aspects and examples have been described. However, various modifications to these examples are possible, and the principles presented herein may be applied to other aspects as well. These and other aspects are within the scope of the following claims.