Memory device and read processing method using read counts, first, second, and third addresses

According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, and a controller which writes a first data table including a first data group including a first logical address corresponding to a first physical and a first count value and a second data group including a second logical address corresponding to a second physical address and a second count value, to the volatile memory, reads the first data table when a third logical address is requested to be read, compares the first count value and the second count value with each other, and rewrites the first data group or the second data group to a third data group including a third logical address based on a result of the comparison.

FIELD

Embodiments described herein relate generally to a memory device and a read processing method.

BACKGROUND

In general, a memory device comprises a nonvolatile memory, and a memory controller comprising a volatile memory. The nonvolatile memory is an electrically erasable and rewritable nonvolatile memory, that is, an Electrically Erasable Programmable Read-Only Memory (EEPROM), for example, a NAND flash memory. The volatile memory is, for example, a Static RAM (SRAM) or a Dynamic RAM (DRAM). The nonvolatile memory reads or writes data page by page and erases data block by block. Thus, the nonvolatile memory requires a long time to randomly access the storage area in comparison with the volatile memory. Therefore, the memory device uses the volatile memory provided in the memory controller as a cache memory. The memory device stores system data including conversion tables between logical addresses and physical addresses (hereinafter, simply referred to as conversion tables) in the system area of the nonvolatile memory. When the power is turned on, the memory device reads part of system data from the nonvolatile memory, and stores the read data in the volatile memory provided in the memory controller. The memory controller converts a logical address accessed from a host into a physical address with reference to the conversion tables of the volatile memory. When a conversion table corresponding to the logical address accessed from the host is not stored in the volatile memory, the memory controller newly reads a conversion table from the nonvolatile memory, and updates and manages the conversion tables of the volatile memory. Thus, when the conversion tables of the volatile memory are updated at each random access from the host, the access performance of the storage device is degraded.

DETAILED DESCRIPTION

In general, according to one embodiment, a memory device comprises a nonvolatile memory; a volatile memory; and a controller which writes a first data table including a first data group comprising a first conversion table including a first logical address corresponding to a first physical address set in a first area of the nonvolatile memory and a first count value as the number of read requests for the first logical address and a second data group comprising a second conversion table including a second logical address corresponding to a second physical address set in a second area of the nonvolatile memory and a second count value as the number of read requests for the second logical address, to the volatile memory, reads the first data table when a third logical address corresponding to a third physical address set in a third area of the nonvolatile memory is requested to be read, compares the first count value and the second count value with each other if the third logical address is not detected in the first data table, and rewrites the first data group or the second data group of the first data table to a third data group comprising a third conversion table including a third logical address and a third count value as the number of read requests for the third logical address based on a result of the comparison.

First Embodiment

FIG. 1is a block diagram showing an example of the configuration of a memory device1according to a first embodiment.

The memory device (nonvolatile storage device)1comprises a nonvolatile memory10and a memory controller20. The memory device1includes, for example, a memory card such as a flash memory card, and a storage device such as an SSD. The memory device1is connected to a host system (hereinafter, simply referred to as a host)3.

The nonvolatile memory10comprises a user data area UA which can be accessed (read/written) from outside, and a system area SA. The nonvolatile memory10is, for example, a NAND flash memory. User data is written to the user data area UA. The user data area UA is divided into a plurality of storage areas (hereinafter, referred to as areas) each having a certain data capacity such that a physical address is set in each split area. System data is written to the system data area SA. The system data includes a data table NTB including a physical-logical conversion table (hereinafter, simply referred to as a conversion table) which defines the correspondence between a logical address specified by the host3and a physical address, and the number of requests to access a specific logical address from the host3, etc.

The memory controller20controls each interface (I/F) and a memory, for example, the nonvolatile memory10. InFIG. 1, the memory controller20is realized by using a large-scale integrated circuit (LSI) called a system-on-chip (SoC) in which a plurality of elements are integrated in a single chip. The memory controller20comprises a volatile memory210and a controller220.

The volatile memory210comprises a data table TB. Data table TB includes part of data of data table NTB. The volatile memory210is, for example, a Static RAM (SRAM) or a Dynamic RAM (DRAM). The volatile memory210may be provided separately from the memory controller20. In place of the volatile memory210, a Random Access Memory (RAM)210may be provided. The RAM210includes a nonvolatile memory such as a Magnetic RAM (MRAM).

The controller220includes, for example, a circuit which performs a calculation process such as a microprocessor (MPU), etc. The controller220comprises a management unit222and a counter224. The controller220performs the processes of various units on firmware.

The management unit222manages the access from the host3to each memory. For example, the management unit222writes data to the nonvolatile memory10or reads data from the nonvolatile memory10in accordance with a command from the host3. The management unit222updates the data of the nonvolatile memory10and the volatile memory210. For example, when the memory device1is turned on, the management unit222stores data table TB from the nonvolatile memory10in the volatile memory210. When the memory device1is turned off, the management unit222stores, in the nonvolatile memory10, data table TB stored in the volatile memory210. When a read request is received from the host3, the management unit222determines whether a conversion table corresponding to the logical address of the read request is stored in data table TB of the volatile memory210. When the management unit222detects that a conversion table corresponding to the logical address of the read request is not stored, the management unit222reads (obtains) a conversion table corresponding to the logical address of the read request, data related to the conversion table, etc., from data table NTB of the nonvolatile memory10. Further, the management unit222writes the read conversion table, the read data related to the conversion table, etc., to data table TB of the volatile memory210.

The counter224counts the number of read requests from the host3to a specific logical address (hereinafter, referred to as a count value). The counter224stores the count value in data tables NTB and TB. For example, when the memory device1is turned on, the counter224starts measuring the count value. The counter224measures the count value as an integrated value from when the memory device1is turned on at the first time. When the count value has reached the upper limit, the counter224may retain the count value while maintaining the upper limit.

FIG. 2shows a structural example of data table NTB stored in the nonvolatile memory10and data table TB stored in the memory controller20according to the present embodiment.

Logical addresses and physical addresses corresponding to the logical addresses are stored in data table NTB of the nonvolatile memory10. Data table NTB includes a conversion table NCTB for converting logical addresses into physical addresses, and a count value NCV corresponding to the logical address of a read request from the host3. The term “conversion table” is also used to indicate the correspondence relationship between one logical address and a physical address corresponding to the logical address.

Data table TB stored in the volatile memory210of the memory controller20includes a conversion table CTB for converting logical addresses into physical addresses, and a count value CV corresponding to the logical address of a read request from the host3. Data table TB comprises the conversion tables and count values obtained from data table NTB. For example, the capacity of data table TB is less than that of data table NTB. In the example shown in the figure, data table TB comprises eight conversion tables, and eight count values corresponding to the eight conversion tables. In the following explanation, a specific conversion table and data corresponding to the specific conversion table such as a count value may be collectively referred to as an address data item (a data group).

FIG. 3A,FIG. 3BandFIG. 3Cshow an example of a read process performed by the memory device1according to the present embodiment.FIG. 3Ashows a state in which the memory controller20receives a read request from the host3.FIG. 3Bshows a state in which an address data item corresponding to the logical address of a read request from the host3is read from data table NTB, and the address data item read from data table NTB is written to data table TB.FIG. 3Cshows a state in which the data written to an area of a physical address corresponding to the logical address of the read request from the host3is read.

As shown inFIG. 3A, the controller220receives a read request for the logical address “1” from the host3. When the read request is received from the host3, the controller220reads data table TB. The controller220determines whether a conversion table corresponding to the logical address “1” of the read request from the host3is stored in data table TB of the volatile memory210. In the example shown in the figure, the controller220determines that a conversion table corresponding to the logical address “1” is not stored in data table TB.

Subsequently, as shown inFIG. 3B, the controller220reads an address data item corresponding to the logical address “1” from data table NTB. The controller220reads the count values of the address data items stored in data table TB, and detects the address data item having the least count value in data table TB (specifically, the address data item of the logical address “16”). The controller220changes (overwrites) the address data item having the least count value of the eight address data items stored in data table TB to (with) the address data item corresponding to the logical address “1”. The controller220reads the conversion table of data table NTB, and temporarily stores, in a buffer, etc., the address data item corresponding to the logical address “1” of the read request. The controller220temporarily stores, in the buffer, etc., the address data item having the least count value of the eight address data items stored in data table TB (specifically, the address data item corresponding to the logical address “16”), erases this address data item from data table TB, and writes the address data item corresponding to the logical address “1” of the read request and temporarily stored in the buffer, etc., to data table TB. The controller220converts the logical address “1” of the read request into the physical address “PA2” with reference to the conversion table of data table TB.

Subsequently, as shown inFIG. 3C, the controller220reads the data written to the area of the physical address “PA2” of the user data area UA of the nonvolatile memory10. After this reading process is completed, the controller220outputs a read completion signal to the host3. In data tables TB and NTB, the controller220updates the count value “987” of the address data item corresponding to the logical address “1” of the read request by, for example, adding 1 (by an increment of 1), such that the count value is changed to 988.

FIG. 4AandFIG. 4Bshow an example of a read process performed by the memory device1according to the present embodiment.FIG. 4Ashows a state in which the count values of two address data items are the same in data table TB when the memory controller20receives a read request from the host3.FIG. 4Bshows a state in which an address data item corresponding to the logical address of the read request from the host3is read from data table NTB, and the read address data item is written to data table TB.

As shown inFIG. 4A, when the controller220determines that a conversion table corresponding to the logical address “1” of a read request from the host3is not stored in data table TB, the controller220detects two address data items having the least count value of the eight address data items stored in data table TB of the volatile memory210(specifically, two address data items corresponding to the logical addresses “16” and “32”).

As shown inFIG. 4B, in data table TB, the controller220changes an address data item corresponding to the logical address “16”, which is less than the logical address of the other one of the two address data items having the least count value, to an address data item corresponding to the logical address “1” of the read request.

For example, when a plurality of address data items are detected as the address data items having the least count value of the address data items stored in data table TB, the controller220replaces the address data item having the least logical address of the address data items having the least count value in data table TB. As another example, in this case, the controller220may replace the oldest address data item of the address data items having the least count value in data table TB.

FIG. 5is a flowchart showing an example of a read process performed by the memory device1according to the present embodiment.

The controller220receives a read request for data corresponding to a logical address from the host3(B501). When the read request is received from the host3, the controller220reads data table TB (B502). The controller220determines whether a conversion table corresponding to the logical address of the read request from the host3is stored in data table TB (B503).

When the controller220determines that a conversion table corresponding to the logical address of the read request is not stored in data table TB (NO in B503), the controller220reads an address data item corresponding to the logical address of the read request from data table NTB (B504). The controller220reads the count values stored in data table TB of the volatile memory210, and detects the address data item having the least count value (B505). The controller220changes the address data item having the least count value of the address data items stored in data table TB to the address data item corresponding to the logical address of the read request (8506).

When the controller220determines that a conversion table corresponding to the logical address of the read request is stored in data table TB (YES in B503), the controller220converts the logical address of the read request from the host3into a physical address with reference to the conversion table corresponding to the logical address of the read request and stored in data table TB (B507).

The controller220reads the data written to an area of the physical address corresponding to the logical address of the read request from the host3(B508). In data tables TB and NTB, the controller220adds a constant count number, for example, 1, to the count value of the address data item corresponding to the logical address of the read request from the host3(B509). The controller220outputs a read completion signal to the host3(B510).

In the present embodiment, when the memory device1determines that a conversion table corresponding to the logical address of a read request is not stored in data table TB, the memory device1changes the address data item having the least count value of the address data items stored in data table TB to an address data item corresponding to the logical address of the read request from the host3and stored in data table NTB. Thus, the memory device1is allowed to collect, in data table TB, address data items having great count values, in other words, address data items corresponding to logical addresses having many read requests from the host3, and optimize data table TB. The memory device1is allowed to reduce the number of reads (updates) of address data items corresponding to the logical addresses of read requests from the host3from data table NTB of the nonvolatile memory10when the memory device1receives the read requests from the host3. As a result, the memory device1is allowed to improve the access performance, for example, the read speed.

Now, this specification explains memory devices according to a modification example and other embodiments. In the modification example and embodiments explained below, the same structural elements as the first embodiment are denoted by like reference numbers, detailed description thereof being omitted or simplified. Structural elements different from those of the first embodiment are mainly explained in detail.

Modification Example

FIG. 6is a block diagram showing an example of the configuration of the memory device1according to a modification example of the first embodiment. The memory device1of the modification example stores some logical addresses corresponding to less count values among the logical addresses of the address data items stored in data table TB. In this respect, the memory device1of the modification example is different from the memory device1of the first embodiment.

In the memory device1of a modification example, the controller220comprises a storage unit225. The storage unit225stores at least two logical addresses in order from the logical address having the least count value of the logical addresses stored in data table TB. For example, the storage unit225reads the count values of the address data items stored in data table TB. Based on the read result, the storage unit225stores the logical address corresponding to the least count value of the logical addresses of the address data items stored in data table TB, and the logical address corresponding to the second least count value. The storage unit225preferably stores eight logical addresses in order from the logical address corresponding to the least count value of the logical addresses of the address data items stored in data table TB to the logical address corresponding to the eighth least count value.

FIG. 7A,FIG. 7BandFIG. 7Cshow an example of a read process performed by the memory device1according to the modification example.FIG. 7Ashows a state in which the memory controller20receives a plurality of read requests from the host3substantially at the same time.FIG. 7Bshows a state in which the logical addresses of the read requests from the host3are read from data table NTB, and the address data items read from data table NIB are written to data table TB.FIG. 7Cshows a state in which the data written to areas of physical addresses corresponding to the logical addresses of the read requests from the host3is read.

As shown inFIG. 7A, the controller220stores the logical address “16” corresponding to the least count value, and the logical address “35” corresponding to the second least count value. The controller220receives read requests for the logical addresses “1” and “3” from the host3. When the controller220receives the read requests from the host3, the controller220reads data table TB. The controller220determines whether conversion tables corresponding to the logical addresses “1” and “3” of the read requests from the host3are stored in data table TB of the volatile memory210. In the example shown in the figure, the controller220determines that conversion tables corresponding to the logical addresses “1” and “3” are not stored in data table TB.

Subsequently, as shown inFIG. 7B, the controller220reads two address data items corresponding to the logical addresses “1” and “3” from data table NTB. The controller220changes two address data items corresponding to the logical address “16” corresponding to the least count value of the eight address data items stored in data table TB and the logical address “35” corresponding to the second least count value to the two address data items corresponding to the logical addresses “1” and “3”. The controller220refers to data table TB, converts the logical address “1” of the read request into the physical address “PA2”, and converts the logical address “3” of the read request into the physical address “PA5”.

Subsequently, as shown inFIG. 7C, the controller220reads the data written to the area of the physical address “PA2” of the user data area UA of the nonvolatile memory10, and the data written to the area of the physical address “PA5” of the user data area UA of the nonvolatile memory10. After this reading process is completed, the controller220outputs read completion signals to the host3. In data tables TB and NTB, for example, the controller220adds 1 to the count value “987” of the address data item corresponding to the logical address “1” of the read request such that the count value “987” is changed to the count value “988”. In data table TB, for example, the controller220adds 1 to the count value “79” of the address data item corresponding to the logical address “3” of the read request such that the count value “79” is changed to the count value “79”.

After the read process is completed, the controller220reads the count values of the address data items stored in data table TB, and newly stores the logical address “32” corresponding to the least count value and the logical address “24” corresponding to the second least count value.

In the modification example, the controller220stores at least two logical addresses in order from the logical address corresponding to the least count value of the address data items stored in data table TB of the volatile memory210. With this structure, in data table TB, the controller220is allowed to always recognize whether the logical address corresponding to the least count value has been changed. When the memory device1receives a read request from the host3, the memory device1does not need to detect the logical address corresponding to the least count value from data table TB. Thus, the memory device1is capable of performing a read process without degrading the access performance. Even when the memory device1receives a plurality of read requests from the host3, the memory device1is capable of performing a read process without degrading the access performance. Thus, the access performance of this memory device1is improved in comparison with the memory device1of the embodiment explained earlier.

The controller220may be configured to store at least two address data items in order from the address data item corresponding to the least count value of the address data items stored in data table TB of the volatile memory210when there is no access request from the host3.

Second Embodiment

FIG. 8is a block diagram showing an example of the configuration of a memory device1according to a second embodiment. The memory device1of the second embodiment reads the data written to a specific area of a nonvolatile memory10, and performs a rewrite process (hereinafter, referred to as a refresh process) for the read data. In this respect, the memory device1of the second embodiment is different from the memory device of the embodiment explained earlier.

In the memory device1of the present embodiment, a controller220comprises a refresh unit226. The refresh unit226holds a threshold for the count value for performing a refresh process, and compares the threshold with the count values of the address data items stored in a data table TB of a volatile memory210. For example, the refresh unit226performs this comparison process when there is no access request from a host3. When a count value greater than the threshold is detected as a result of comparison, the refresh unit226detects a logical address corresponding to the count value greater than the threshold. The refresh unit226detects a physical address corresponding to the logical address with reference to the conversion table of data table TB. The refresh unit226confirms the data written to an area corresponding to the physical address. When the refresh unit226determines that a refresh process needs to be performed for the data written to the area, the refresh unit226performs a refresh process for the data of the area.

FIG. 9is a flowchart showing an example of a refresh process performed by the memory device1according to the present embodiment.

The controller220reads data table TB of the volatile memory210when there is no access request from the host (B901). The controller220compares the count value of a specific address data item of the address data items stored in data table TB of the volatile memory210with a threshold set in advance (B902).

In data table TB, the controller220determines whether the count value of the specific address data item is greater than the threshold set in advance (B903). When the controller220determines that the count value of the specific address data item is greater than the threshold (YES in B903), the controller220detects a logical address corresponding to the count value (B904). The controller220detects a physical address corresponding to the logical address with reference to the conversion table of data table TB (B905). The controller220confirms the data written to an area corresponding to the physical address of the nonvolatile memory10(B906). The controller220determines whether a refresh process needs to be performed for the data written to the area (B907). When the controller220determines that a refresh process needs to be performed for the data written to the area (YES in B907), the controller220performs a refresh process to the data written to the area (B908). When the controller220determines that a refresh process does not need to be performed for the data written to the area (NO in B907), the controller220terminates the process.

When the controller220determines that the count value of the specific address data item is less than the threshold (NO in B903), the controller220determines whether another address data item is present in data table TB (B909). When the controller220determines that another address data item is present in data table TB (YES in B909), the controller220proceeds to the process of step B901. When the controller220determines that another address data item is not present in data table TB (NO in B909), the controller220terminates the process.

In the present embodiment, the memory device1is allowed to confirm the data written to the area of the physical address of the address data item of a count value greater than a threshold, and perform a refresh process for the data written to the area based on the necessity. Thus, it is possible to improve the reliability of the data written to the nonvolatile memory10in comparison with the memory device1of the embodiment explained earlier.

Third Embodiment

FIG. 10is a block diagram showing an example of the configuration of a memory device1according to a third embodiment. The memory device1of the third embodiment changes a physical address corresponding to the logical address of an address data item having a great count value among the address data items stored in a data table TB to a physical address corresponding to another storage medium. In this respect, the memory device1of the third embodiment is different from the memory device of each of the embodiments explained earlier.

In the memory device1of the present embodiment, a nonvolatile memory10comprises a plurality of storage media (hereinafter, referred to as memory chips). For example, the nonvolatile memory10comprises a first memory chip11and a second memory chip12. The first memory chip11comprises a system area SA1comprising a data table NTB1, and a user data area UA1. The second memory chip12comprises a system area SA2comprising a data table NTB2, and a user data area UA2.

A controller220comprises an address changing unit227. The address changing unit227holds a threshold for the count value for changing the correspondence relationship between logical addresses and physical addresses in the conversion table. The address changing unit227compares the threshold with the count values of the address data items stored in data table TB of a volatile memory210. For example, the address changing unit227performs this comparison process when there is no access request from a host3. When a plurality of count values greater than the threshold are detected as a result of comparison, the address changing unit227detects a plurality of logical addresses corresponding to the count values greater than the threshold. The address changing unit227refers to the conversion table of data table TB, and detects physical addresses corresponding to the logical addresses, and memory chips corresponding to the physical addresses. When the address changing unit227detects that the physical addresses corresponding to the logical addresses correspond to the same memory chip, the address changing unit227changes the physical addresses corresponding to the logical addresses to physical addresses corresponding to different memory chips.

FIG. 11AandFIG. 11Bshow an example of a process for changing an address in the memory device1according to the third embodiment.FIG. 11Ashows a state in which the physical addresses of two address data items having count values greater than a threshold correspond to the same first memory chip11.FIG. 11Bshows a state in which one of the physical addresses of the two address data items having the count values greater than the threshold is changed to a physical address corresponding to the second memory chip12. InFIG. 11AandFIG. 11B, chip addresses CPA, NCPA1and NCPA2indicate memory chips corresponding to physical addresses. In chip addresses CPA, NCPA1and NCPA2, the chip address “1” indicates that the physical address corresponds to the first memory chip11. The chip address “2” indicates that the physical address corresponds to the second memory chip12. It is assumed that an address data item corresponding to the logical address “98” is the oldest address data item in the volatile memory210, specifically, the address data item firstly stored in data table TB among the eight address data items stored in data table TB.

As shown inFIG. 11A, the controller220reads data table TB of the volatile memory210when there is no access request from the host3. The controller220compares the threshold for the count value for changing the correspondence relationship between logical addresses and physical addressed in the conversion table, for example, the count value “2500”, with the count values of the eight address data items stored in data table TB. When the count values “2560” and “2678” greater than the threshold are detected as a result of comparison, the controller220detects the logical address “98” of the address data item of the count value “2560” and the logical address “564” of the address data item of the count value “2678” in the data table. The controller220refers to data table TB, and detects the physical address “PA80” and the chip address “1” corresponding to the logical address “98”, and the physical address “PA10” and the chip address “1” corresponding to the logical address “564”. In the example shown in the figure, the controller220detects that the chip address “1” of the physical address “PA80” is the same as the chip address “1” of the physical address “PA10”.

For example, the controller220changes the physical address “PA80” corresponding to the logical address “98” less than the logical address “564” to a predetermined physical address of the second memory chip12in data table TB. As another example, the controller220may change the physical address “PA80” corresponding to the logical address “98” whose data is older than that of the logical address “564” to a predetermined physical address of the second memory chip12in data table TB. For example, the predetermined physical address is the physical address “240” corresponding to the logical address “54” of the address data item having the least count value “7” in conversion table NTB2of the second memory chip12as the destination of change.

As shown inFIG. 11B, the controller220replaces the physical address “PA80” corresponding to the first memory chip11with the physical address “PA240” corresponding to the second memory chip12in the address data item corresponding to the logical address “98” of data table TB.

In data table TB, the controller220changes the physical address “PA80” corresponding to the logical address “98” to the physical address “240”. In data table TB, the controller220changes the chip address of the logical address “98” from “1” to “2”.

The controller220changes the physical address “PA240” corresponding to the logical address “54” to the physical address “PA80”. The controller220changes the chip address of the logical address “54” from “2” to “1” in data table NTB2. The controller220writes an address data item corresponding to the logical address “54” to data table NTB1. The controller220may erase the address data item corresponding to the logical address “54” from data table NTB2, or may retain the address data item.

For example, the controller220replaces the data written to the area of user data area UA1corresponding to the physical address “PA80” with the data of the area of user data area UA2corresponding to the physical address “PA240”.

In the present embodiment, the memory device1is allowed to change a physical address corresponding to a logical address of an address data item having a great count value to a physical address corresponding to another memory chip. Thus, the memory device1is allowed to cause a plurality of physical addresses corresponding to logical addresses of address data items having great count values to be distributed to a plurality of memory chips. In this way, the memory device1is capable of accessing physical addresses corresponding to logical addresses of address data items having great count values at the same time. As a result, the access performance of the memory device1can be improved in comparison with the memory device1of each of the embodiments explained earlier.

Fourth Embodiment

FIG. 12is a block diagram showing an example of the configuration of a memory device1according to a fourth embodiment. The memory device1of the fourth embodiment is allowed to access a physical address corresponding to a logical address of an address data item having a great count value at high speed. Further, the memory device1changes the physical address to a physical address corresponding to an area having a high durability. In this respect, the memory device1of the fourth embodiment is different from the memory device of each of the embodiments explained earlier.

In the memory device1of the present embodiment, a first memory chip11included in a nonvolatile memory10comprises a multi-level cell (MLC) area M11in a user data area UA2. A second memory chip12comprises an MLC area M12and a single-level cell (SLC) area S12in a user data area UA2. The SLC area is an area set to a writing system excellent at access speed and durability, in other words, an SLC system. The MLC area is an area set to a writing system in which a large amount of data can be written, in other words, an MLC system.

An address changing unit227holds a threshold for the count value for changing the correspondence relationship between logical addresses and physical addresses in a conversion table, and compares the threshold with the count values of the address data items stored in a data table TB of a volatile memory210. In the present embodiment, the threshold is used as a reference value for changing a physical address corresponding to an area set to an MLC system to a physical address corresponding to an area set to an SLC system. When a count value greater than the threshold is detected as a result of comparison, the address changing unit227detects a physical address corresponding to the logical address of the address data item having the count value greater than the threshold, and a writing system set to an area corresponding to the physical address. When the address changing unit227detects that the writing system set to the area corresponding to the physical address is an MLC system, the address conversion unit227changes the physical address corresponding to the area set to an MLC system to a physical address corresponding to an area set to an SLC system.

FIG. 13AandFIG. 13Bshow an example of a process for changing an address in the memory device1according to the fourth embodiment.FIG. 13Ashows a state in which areas corresponding to the physical addresses of two address data items having count values greater than the threshold are areas set to an MLC system.FIG. 13Bshows a state in which the physical addresses of the two address data items having the count values greater than the threshold are changed to physical addresses corresponding to areas set to an SLC system. InFIG. 13AandFIG. 13B, writing systems WS, NWS1and NWS2indicate writing systems set to areas corresponding to physical addresses.

As shown inFIG. 13A, when there is no access request from a host3, the controller220compares the threshold for changing the correspondence relationship between logical addresses and physical addresses in a conversion table, for example, the count value “2500”, with the count values of the eight address data items stored in data table TB. When the count values “2560” and “2678” greater than the threshold are detected as a result of comparison, the controller220detects the logical address “98” of the address data item of the count value “2560”, and the logical address “564” of the address data item of the count value “2678”. The controller220refers to data table TB. The controller220detects the physical address “PA80” corresponding to the logical address “98”, and the writing system “MLC” set to an area corresponding to the physical address “PA80”. Further, the controller220detects the physical address “PA10” corresponding to the logical address “564”, and the writing system “MLC” set to an area corresponding to the physical address “PA10”. In the example shown in the figure, the controller220detects that the writing system set to the physical address “PA80” and the writing system set to the physical address “PA10” are an MLC system. For example, the controller220reads a data table NTB of the memory chip12comprising the SLC area S12, and detects a plurality of physical addresses corresponding to areas set to an SLC system. The controller220detects the logical address “54” of the address data item having the least count value among the logical addresses corresponding to the physical addresses, and the logical address “90” of the address data item having the second least count value.

As shown inFIG. 13B, the controller220replaces the physical address “PA80” corresponding to the area set to an MLC system with the physical address “PA240” corresponding to the area set to an SLC system in the address data item corresponding to the logical address “98” of data table TB. The controller220replaces the physical address “PA10” corresponding to the area set to an MLC with the physical address “PA215” corresponding to the area set to an SLC system in the address data item corresponding to the logical address “564” of data table TB.

The controller220changes the physical address “PA80” corresponding to the logical address “98” to the physical address “PA240” in data table TB. The controller220changes the chip address from “1” to “2” in data table TB. The controller220changes the writing system from “MLC” to “SLC” in change table TB.

The controller220changes the physical address “PA240” corresponding to the logical address “54” to the physical address “PA80”. The controller220changes the chip address of the logical address “54” from “2” to “1”. The controller220changes the wiring system of the logical address “54” from “SLC” to “MLC”. The controller220writes an address data item corresponding to the logical address “54” to a data table NTB1. The controller220may erase the address data item corresponding to the logical address “54” from a data table NTB2, or may retain the address data item.

The controller220changes the physical address “PA10” corresponding to the logical address “564” to the physical address “PA215” in data table TB. The controller220changes the chip address from “1” to “2” in data table TB. The controller220changes the writing system from “MLC” to “SLC” in change table TB.

The controller220changes the physical address “PA215” corresponding to the logical address “90” to the physical address “PA10”. The controller220changes the chip address of the logical address “90” from “2” to “1”. The controller220changes the writing system of the logical address “90” from “SLC” to “MLC”. The controller220writes an address data item corresponding to the logical address “90” to data table NTB1. The controller220may erase the address data item corresponding to the logical address “90” from data table NTB2, or may retain the address data item.

The controller220replaces the data written to the area corresponding to the physical address “PA80” in the MLC area M11of a user data area UA1with the data of the area corresponding to the physical address “PA240” in the SLC area S12of user data area UA2. The controller220replaces the data written to the area corresponding to the physical address “PA10” in the MLC area M11of user data area UA1with the data of the area corresponding to the physical address “PA215” in the SLC area S12in user data area UA2.

In the present embodiment, the memory device1is allowed to access a physical address corresponding to a logical address having a great count value at high speed, and change the physical address to a physical address corresponding to an area having a high durability. Thus, it is possible to improve the access speed of the memory device1to an area of a physical address corresponding to a logical address having a great count value. Moreover, the reliability of data of an area of a physical address corresponding to a logical address having a great count value is improved.