Liquid crystal display device and method of manufacturing the same

A liquid crystal display, and a method of manufacturing thereof, includes providing a substrate; depositing sequentially a first metal layer and a first insulating layer on the substrate; patterning the first metal layer and the first insulating layer using a first mask to form a gate line and a first gate insulating layer; depositing sequentially a second gate insulating layer, a pure semiconductor layer, a doped semiconductor layer and a second metal layer over the whole substrate; patterning the second metal layer using a second mask to form a data line, source and drain electrodes, a capacitor electrode, the capacitor electrode overlapping a portion of the gae line; etching the doped semiconductor layer between the source and drain electrodes to form a channel region; depositing a third insulating layer over the whole substrate; patterning the third insulating layer using a third mask to form a passivation film, the passivation film having a smaller width than the data line and covering the source and drain electrodes and exposing a portion of the drain electrode and the capacitor electrode; depositing a transparent conductive material layer over the whole substrate; and patterning the transparent conductive material layer using a fourth mask to pixel electrode, the pixel electrode contacting the drain electrode.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display (LCD) device and a method of manufacturing the same.

2. Description of Related Art

FIG. 1is a cross sectional view illustrating a typical LCD device. As shown inFIG. 1, the LCD device includes lower and upper substrates2and4with a liquid crystal layer10interposed therebetween. The lower substrate2has a thin film transistor “S” (TFT) as a switching element and a pixel electrode14, and the upper substrate4has a color filter8and a common electrode12. The pixel electrode14is formed over a pixel region “P” serves to apply a voltage to the liquid crystal layer10along with the common electrode12, and the color filter8serves to implement natural colors. A sealant6seals an edge of the lower and upper substrate2and4to prevent leakage of the liquid crystal.

FIG. 2is a plan view illustrating the lower array substrate of the typical LCD device. As shown inFIG. 2, the lower array substrate2includes gate lines22arranged in a transverse direction and data lines24arranged in a longitudinal direction perpendicular to the gate lines22. The TFTs “S” are arranged near a crossing point of the gate and data lines22and24. The pixel electrodes14are arranged on a region defined by the gate and data lines22and24. Each of the TFTs “S” include a gate electrode26, a source electrode28and the drain electrode30. The gate electrode26extends from the gate line22, and the source electrode28extends from the data line24. The drain electrode30is electrically connected with the pixel electrode14through a drain contact hole30′. Data and gate pads21and23are arranged at terminal portions of the gate and data lines22and24, respectively. Storage capacitors “Cst” are formed over a portion of the gate line22.

A process for manufacturing the LCD device described above is very complex. Particularly, the lower array substrate is manufactured through several mask processes. The process of manufacturing the lower array substrate is explained below with reference withFIGS. 3Ato3E.

FIGS. 3Ato3E are cross sectional views taken long lines III—III and III′—III′ ofFIG. 2, respectively. First, as shown inFIG. 3A, a metal layer is deposited on a substrate1using a sputtering technique after removing alien substances and organic materials and cleaning the substrate to promote adhesion between the substrate1and the metal layer. Thereafter, the metal layer is patterned into a gate line22including a gate electrode26using a first mask. The gate line22is made of a low resistive material such as aluminum or molybdenum to lower RC delay. Pure aluminum has bad corrosion resistance and may cause a line defect due to a hillock in a subsequent process. Therefore, an aluminum alloy or two or three-layered aluminum is usually used. A portion of the gate line22serves as a first capacitor electrode.

As shown inFIG. 3B, a gate insulating layer50is deposited on the exposed surface of the substrate1while covering the gate line22and the gate electrode26. The gate insulating layer50has a thickness of 3000 Å and is usually made of SiNx or SiOx. A pure amorphous silicon layer52and a doped amorphous silicon layer54are sequentially deposited on the gate insulating layer50. Then, the amorphous silicon layer52and the doped amorphous silicon layer54are patterned into an active layer55and a semiconductor island53. The doped amorphous silicon layer54is called an ohmic contact layer and serves to reduce contact resistance between the active layer55and a metal layer that will be formed in a later process.

Subsequently, as shown inFIG. 3C, a metal layer is deposited on the semiconductor layers53and55and is patterned into source and drain electrodes28and30using a third mask. The source and drain electrode53and55are usually made of chromium or a chromium alloy. At the same time as the source and drain electrodes28and30are formed, the data lines24are formed. A second capacitor electrode58is formed on the gate insulating layer50and overlaps a portion of the gate line22in order to form a storage capacitor. In other words, using the third mask, the data line24, the source and drain electrodes28and30, and the second capacitor electrode58are formed. Using the source and drain electrodes28and30as a mask, a portion of the ohmic contact layer54over the gate electrode26is etched. If the portion of the ohmic contact layer54over the gate electrode26is not etched, it produces undesirable electrical characteristics and poor performance of the TFT “S”. Etching the portion of the ohmic contact layer54over the gate electrode26requires special attention. This is because the etching uniformity directly affects electrical characteristics of the TFT.

As shown inFIG. 3D, a passivation film56is formed over the substrate1using the fourth mask in order to protect the active layer55. The passivation film56may affect electrical characteristics of the TFT due to an unstable energy state of the active layer55and alien substances generated during the etching process, and therefore it is usually made of an inorganic material such as SiNx and SiO2or an organic material such as benzocyclobutene (BCB). The passivation film56also requires a high light transmittance, a high humidity resistance and a high durability. The passivation film56includes two contact holes (the drain contact hole30′ and a capacitor contact hole58′).

Therefore, as shown inFIG. 3E, a transparent conducting oxide layer is deposited on the passivation film56and is patterned into the pixel electrode14using a fifth mask. The pixel electrode14is usually made of indium tin oxide (ITO). The pixel electrode14is electrically connected with the drain electrode30through the drain contact hole30′ and with the second capacitor electrode58through the capacitor contact hole58′.

The process for manufacturing the conventional LCD device described above includes at least five masks. Further, when the gate electrode is made of aluminum, at least two masks are required to overcome an occurrence of the hillock that may be generated on the surface of the aluminum layer. Therefore, manufacturing the TFT array substrate basically requires five or six masks. Such a mask process includes various processes such as cleaning, depositing, baking, etching and the like. Therefore, even a reduction of one mask results in a shorter processing time, low production costs and high manufacturing yields.

For the foregoing reasons, there is a need for a liquid crystal display device manufactured by the mask process wherein the number of masks required is decreased.

SUMMARY OF THE INVENTION

To overcome the problems described above, preferred embodiments of the present invention provide a liquid crystal display device manufactured using a mask process wherein the number of masks are reduced and a method of manufacturing the same.

Preferred embodiments of the present invention further provide a liquid crystal display device having a short processing time and a high manufacturing yield.

In order to achieve the above object, the preferred embodiment of the present invention A method of manufacturing a liquid crystal display device, including: providing a substrate; depositing sequentially a first metal layer and a first insulating layer on the substrate; patterning the first metal layer and the first insulating layer using a first mask to form a gate line and a first gate insulating layer; depositing sequentially a second gate insulating layer, a pure semiconductor layer, a doped semiconductor layer and a second metal layer over the whole substrate; patterning the second metal layer using a second mask to form a data line, source and drain electrodes, a capacitor electrode, the capacitor electrode overlapping a portion of the gae line; etching the doped semiconductor layer between the source and drain electrodes to form a channel region; depositing a third insulating layer over the whole substrate; patterning the third insulating layer using a third mask to form a passivation film, the passivation film having a smaller width than the data line and covering the source and drain electrodes and exposing a portion of the drain electrode and the capacitor electrode; depositing a transparent conductive material layer over the whole substrate; and patterning the transparent conductive material layer using a fourth mask to pixel electrode, the pixel electrode contacting the drain electrode.

The gate line includes a gate pad formed at its terminal portion, the gate pad including at least one pad contact hole. The method further includes forming gate pad electrode using the fourth mask, the gate pad electrode contacting the gate pad through at least one pad contact hole. A crossing portion between the gate line and data line is insulated by the second insulating layer, the pure semiconductor layer and the doped semiconductor layer.

The preferred embodiment of the present invention further provides a liquid crystal display device, including: a substrate; a thin film transistor formed on the substrate, including: a gate line having a gate electrode; first and second insulating layers; an active layer; and source and drain electrodes; a pixel electrode overlapping a portion of the gate lines and contacting the drain electrode; and a storage capacitor including: a portion of the gate line as a first electrode; a second electrode overlapping the portion of the gate line; and the first and second insulating layers, the pure semiconductor layer and the doped semiconductor layer interposed between the gate line and the pixel electrode as a dielectric layer.

The LCD device according to the preferred embodiment of the present invention has the following advantages. First, since the LCD device can be manufactured using only four masks, the processing time is decreased and the manufacturing yield is high. Further, since the mask process is reduced in number, the production cost is low. Since the gate pads include a plurality of pad contact holes, contact resistance between the pixel electrode and the gate pad becomes lowered due to the side contact.

DETAILED DESCRIPTION OF PREFFERED EMBODIMENTS

Reference will now be made in detail to preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

FIG. 4is a plan view illustrating a lower array substrate of a liquid crystal display (LCD) device according to a preferred embodiment of the present invention. As shown inFIG. 4, gate lines102are arranged in a transverse direction and data lines120are arranged in a longitudinal direction perpendicular to the gate lines102. The TFTs are arranged near a crossing point of the gate and data lines102and120. The pixel electrodes118are arranged on a region defined by the gate and data lines102and120. Each of the TFT includes a gate electrode101, a source electrode112and the drain electrode114. The gate electrode101extends from the gate line102, and the source electrode112extends from the data line120. The drain electrode114is electrically connected with the pixel electrode118through a drain contact hole116. Data and gate pads106and124are arranged at terminal portions of the gate and data lines102and120, respectively. Storage capacitors are formed over a portion of the gate line102.

A process for manufacturing the LCD device according to the preferred embodiment of the present invention is explained below with reference withFIGS. 5Ato5D.

FIGS. 5Ato5D are plan views and cross sectional views taken along lines VI—VI of FIG.4. First, as shown inFIG. 5A, a first metal layer and a first insulating layer are sequentially deposited on a substrate1and is patterned into the gate line102and a gate insulating layer200using a first mask. The gate line102includes the gate electrode101. InFIG. 5A, the gate electrode101appears to be a portion of the gate line102, but the gate electrode101may extend from the gate line102. The gate line102is made of aluminum, chromium, molybdenum or aluminum alloy, for example, having the dual-layered structure of AlNd/Mo. The gate pads106are formed at a terminal portion of the gate lines102. Preferably, the gate pads106include a plurality of pad contact holes108. Through the pad contact hole108, the gate pad106is electrically connected with the transparent conductive electrode that will be formed in subsequent process. When the gate pad106includes a plurality of the pad contact holes108, contact resistance between the gate pad106and the transparent conductive electrode is lowered.

Subsequently, as shown inFIG. 5B, a semiconductor layer202and a second metal layer are sequentially deposited on the gate insulating layer200and are patterned into source and drain electrodes112and114and capacitor electrode150using a second mask. Thereafter, using the source and drain electrodes112and114as a mask, a portion of the semiconductor layer202is etched. The semiconductor layer202, even though not shown, includes a doped semiconductor layer and a pure semiconductor layer. In other words, excluding a portion of the semiconductor layer202under the patterned second metal layer, the remaining portion of the semiconductor layer202is etched in order to decrease leakage current. A second insulating layer201is formed on the gate insulating layer200. This is to prevent a possible line short at a step portion “T” between the gate line102and the data line120.

Then, as shown inFIG. 5C, a third insulating layer is deposited over the whole substrate1and is patterned into a passivation film122using a third mask. At this point, the semiconductor layer202and the second insulating layer201(excluding a portion under the patterned passivation film122) are etched at the same time (shown in FIG.5B). The gate line102including the gate pad106is protected by the gate insulating layer200. The passivation film122includes a capacitor contact hole204and a drain contact hole116. The capacitor contact hole204is formed over the capacitor electrode150, and the drain contact hole116is formed over the drain electrode114(shown in FIG.5B).

Finally, as shown inFIG. 5D, a transparent conductive material layer is deposited on the passivation film122and is patterned into the pixel electrode118using a fourth mask. The pixel electrode118is electrically connected with the drain electrode114through the drain contact hole116and with the capacitor electrode150through the capacitor contact hole203, respectively. A gate pad electrode107is formed over the gate pad106for a side-contact with the gate pad106.

FIG. 6is a cross sectional view taken along line VI—VI ofFIG. 5D, illustrating the data pad. As shown inFIG. 6, the semiconductor layer202is formed over the substrate1. The data pad105is patterned on the semiconductor layer202. the passivation film122overlaps both end portions of the data pad105. A data pad electrode109covers the passivation film122to electrically contact the data pad105. At this point, the gate and data pad electrodes107and109make contact with the external drive circuit (not shown).

FIG. 7is a cross sectional view taken along line VII—VII ofFIG. 5D, illustrating the storage capacitor. As shown inFIG. 7, the storage capacitor includes the gate line102as a first capacitor electrode and the capacitor electrode150as a second capacitor electrode. The gate insulating layer200and second insulating layer201are used as a dielectric layer. The pixel electrode118serves as an electrode for removing charges and is electrically connected with the capacitor electrode150.

As described above, a crossing portion between the gate line and the data line is insulated by the second insulating layer. When the gate lines are formed using the first mask, the gate pad contact hole is formed. Further, since the gate pads include a plurality of the pad contact holes, contact resistance between the pixel electrode and the gate pad is lowered due to the side contact.

The LCD device according to the preferred embodiment of the present invention has the following advantages. First, since the LCD device can be manufactured using only four masks, the processing time is decreased and the manufacturing yield is high. Further, since the number of masking steps process is reduced, the production cost is low. Since the gate pads include a plurality of pad contact holes, contact resistance between the pixel electrode and the gate pad is lowered due to the side contact.