Method and apparatus for reducing threshold voltage mismatch in an integrated circuit

A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.

TECHNICAL FIELD

The present invention relates to semiconductor integrated circuits. More specifically, the invention relates to reducing threshold voltage mismatch between field effect transistors of a semiconductor integrated circuit.

BACKGROUND

Threshold voltage (Vt) of a field effect transistor (FET) is the minimum gate-to-source voltage differential that is required to create a conducting path through the channel, and between the source and drain (S/D) terminals or regions of the FET. The Vt of devices within a semiconductor integrated circuit is one of the critical parameters that must be carefully controlled and matched from transistor to transistor for proper commercially reproducible operation. This is the case for such FET technologies as planar complementary metal-oxide semiconductor (CMOS) FETs or FinFETs, either of which may be manufactured on bulk semiconductor substrates or silicon-on-insulator (SOI) substrates.

The degree to which Vt will vary between adjacent transistors is known as Vt mismatch (Vtmm). With constant down-scaling of ultra-high density integrated circuits, the threshold for acceptable Vtmm is also scaled down. Therefore Vtmm becomes increasingly problematic for lower scale semiconductor technology class sizes, such as the 14 nanometers (nm) node and beyond. This is particularly the case in technologies, such as static random access memory (SRAM) technology, where transistor pairs have to be closely matched for proper operation.

Two major contributors to Vtmm in a FET are the geometry of the FET's gate stack (e,g, the critical dimensions, or gate work-function metal layer thickness) and the degree of random diffusion of dopants in the FET's channel. With regards to a FET's gate stack geometry and structure, an ideal gate stack would have a perfectly square geometry, vertical profile, and a perfectly uniform thickness of layers in the gate stack with its bottom layer being a perfectly uniformly thick high-k gate dielectric layer. The high-k dielectric layer, in turn, would be disposed flat against the FET's channel. However, this is hard to consistently achieve from device to device, especially at smaller critical dimensions (CD), wherein most gate stacks will tend to have bottom corner regions that are variously rounded from device to device. Additionally, the gate stacks of smaller CD devices tend to be variously thicker in the rounded corner regions than in the middle portions of the gate stacks. As a result, the well-known effective work function of the gate stacks (i.e., the gate dielectric layer, the gate work-function metal layer, and other gate electrode layers) of scaled devices will tend to vary across the channel regions of such devices. Because the effective work function of a device directly affects that device's Vt, than the more the effective work function varies between devices in an integrated circuit, the greater the Vtmm between those adjacent devices will be.

This is particularly the case with replacement metal gate (RMG) transistor technologies, wherein a metal gate stack (which generally includes a gate work-function metal layer and a gate electrode metal disposed over a gate dielectric layer) is used to replace a polysilicon dummy gate. More particularly, this is especially problematic with RMG FETs having titanium nitride (TiN) as a gate work-function metal layer.

With regards to the amount of random diffusion of dopants in a FET's channel, a major contributor to such random diffusion of dopants is the excessive use of annealing processes, such as rapid thermal annealing (RTA), during device formation. Other major contributors to random dopant diffusion into a FET's channel include dopant implantation within the S/D regions, lightly doped drain (LDD) implants within the channel and Halo (or pocket) implants within the channel.

However, each of the above listed features that contribute to increased diffusion of dopants into the channel are utilized to address specific problems or provide specific benefits, during the formation of a FET, making those features difficult to eliminate or replace. For example, S/D dopant implantation is often required to enhance conductivity between the source and drain terminals when a FET is in the on-state. Moreover, annealing is often required to repair damage caused by ion bombardment during dopant implantation, especially in the S/D regions. Additionally, LDD implants are used to suppress short channel effects (SCEs) such as hot carrier injection, drain induced barrier lowering or the like, which become more prevalent at scaled devices. Also, Halo implants are used to reduce punch-through leakage current between source and drain, which become increasingly problematic at lower class sizes.

Accordingly, there is a need for a method and apparatus to minimize Vtmm in transistors of an integrated circuit that can be applied to such technologies as CMOS FET and finFET on either bulk or SOI substrates. In particular, there is a need to minimize Vtmm for such technologies as SRAM, where transistor pair matching is critical.

Moreover, there is a need to minimize Vtmm even if the gate stack includes rounded corners that vary from the ideal square geometry. In particular there is need to minimize Vtmm in RMG transistors having variously rounded corners in their gate stack.

Additionally, there is a need to minimize Vtmm by reducing or eliminating such formation processes as annealing and/or S/D dopant implantation while still maintaining robust source to drain conductivity when the FET is in an on-state. Further there is a need to minimize Vtmm by eliminating LDD implants while still suppressing SCEs. Also there is a need to minimize Vtmm by eliminating Halo implants while still suppressing source to drain punch-through leakage current.

BRIEF DESCRIPTION

The present invention offers advantages and alternatives over the prior art by providing a transistor on a substrate structure and method of making the same. The transistor includes a work-function metal layer with corner regions that have a work-function tuning species implanted therein via an angled implantation process. The work-function tuning species tune the effective work function of the gate stack to be relatively uniform across the length of the transistor's channel. As a result, Vt of the transistor is more closely controlled, SCEs are minimized and the need for halo implants are eliminated, thus reducing Vtmm between the transistor and other devices associated with the structure.

Additionally, the transistor includes epitaxially grown source and drain (S/D) regions wherein n-type or p-type dopants are introduced entirely in-situ, thus avoiding any dopant implantation process during epitaxial growth of the S/D regions. As a result, random diffusion of dopant ions into the channel are minimized to further control Vt of the transistor and the need for LDD implants are eliminated, thus further reducing Vtmm between the transistor and other devices associated with the structure.

A method of making a transistor in accordance with one or more aspects of the present invention includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer includes a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.

In another aspect of the invention, a method of making a transistor includes providing a substrate. Exposed portions of the substrate are etched to form boundaries of a source region and a drain region for a transistor, the source and drain (S/D) regions being connected by a channel disposed within the substrate. The S/D regions are epitaxially grown from precursors. One of an n-type dopant and a p-type dopant is introduced entirely in-situ during the epitaxial growth of the S/D regions.

A transistor for an integrated circuit in accordance with one or more aspects of the present invention includes a source region, a drain region and a channel disposed within a substrate. The source region and drain region are connected therebetween by the channel. A gate structure is disposed over the channel and is operative to control electrical conductivity through the channel from the source region to the drain region. The gate structure includes a gate trench having gate spacers as sidewalls and a gate bottom as a top surface of the channel. The gate structure also includes a gate dielectric layer disposed within the gate trench. The gate structure further includes a gate work-function metal layer disposed on the gate dielectric layer, the work-function metal layer including corner regions proximate the trench bottom and a middle region between the corner regions. The corner regions have a work-function tuning species implanted therein which tunes an effective work function of the corner regions to be closer in value to an effective work function of the middle region.

DETAILED DESCRIPTION

Referring toFIG. 1, a cross-sectional view of a structure10including a prior art planar n-type CMOS FET12is presented. Structure10includes a substrate14into which a lightly doped p-type well16is disposed. For this exemplary embodiment, transistor12is an n-type transistor and is disposed in p-well16. However, one skilled in the art would recognize that transistor12could be a p-type transistor in an n-type well. Further transistor12could also be a finFET transistor.

Prior art transistor12includes a source terminal (or region)18and a drain terminal (or region)20, which are connected therebetween by a channel22. A gate stack structure24is disposed over the channel22and is operative to control electrical conductivity through the channel22from the source18to the drain20.

The gate stack structure24includes a gate dielectric26, a gate work-function metal layer28and a gate electrode metal30disposed in a gate trench32. The gate trench32includes a pair of vertically extending gate spacers34as sidewalls and the top surface of channel22as the bottom of the gate trench. The gate dielectric26is a high k dielectric, such as Hafinum oxide and a thin interfacial oxide layer (not shown). The gate dielectric26can be formed over channel22by using a suitable deposition process or thermal oxidation process. The gate work-function metal28may be composed of tantalum nitride (TaN), titanium nitride (TiN) or similar. The work-function metal layer28can be disposed over the gate dielectric26by such well known processes as atomic layer deposition (ALD) or a sputtering method. Finally, the gate electrode metal30may be composed of tungsten, copper or similar and can be disposed over the work-function metal layer28by such processes as chemical or physical vapor deposition, electro-less plating or the like.

During formation, the source18and drain20regions are typically epitaxially grown with dopant (in this case an n-type dopant, such as phosphorous or arsenic). Thereafter the source18and drain20are heavily doped with the same n-type dopants through an ion implantation process. However, the implantation process is an ion bombardment that damages the crystal lattice of the source and drain. Therefore an annealing process, such as rapid thermal annealing (RTA) is required to repair the damage and activate the dopants. Disadvantageously, the annealing process invariably induces a significant percentage of dopant ions36to diffuse into the channel region22, which can randomly change the Vt of the transistor12and increase Vtmm between the transistor12and other devices in the integrated circuit.

Located adjacent to the source18and drain20, and slightly overlapping the gate dielectric26, are lightly doped drain (LDD) implants38. LDD implants38are doped with the same type dopant as the source18and drain20, therefore, in this exemplary embodiment, the LDD implants are lightly doped n-type. The LDD implants38are utilized to reduce such short channel effects (SCEs) as the hot carrier effect. The hot carrier effect is when hot carriers (e.g. electrons) in the source18or drain20gain enough energy to be injected through the gate dielectric26and into the work-function metal layer28. The hot carriers that are injected as a result of the hot carrier effect can cause damage to gate structure24. Problematically however, the formation process for such LDD implants38, though beneficial in reducing SCEs, contribute to an increase in random diffusion of dopant ions36into the channel region22, which also tends to increase Vtmm.

Located adjacent the LDD implants38are halo implants40. The halo implants40are more heavily doped than the channel22with the opposite type dopant as the source18and drain20. Therefore, in this exemplary embodiment, the halo implants are heavily doped p-type. The halo implants40are utilized to reduce unwanted punch-through leakage current across the channel22when the transistor12is in the off-state. Problematically however, the formation process for such halo implants40, though beneficial in reducing leakage current, also contributes to an increase in random diffusion of dopant ions36into the channel region22, which also tends to increase Vtmm.

Referring back to the gate work-function metal layer28, it is important to note that, due to manufacturing limitations, the bottom corner regions (or bottom corners)42of the work-function metal layer28are not perfectly square. Rather the corner regions42curve away from the channel22and are thicker relative to the middle portion of the metal layer28.

The overall Vt of transistor12is dependent, among other factors, on the effective work function of the gate stack, which includes the gate dielectric26and the gate work-function metal layer28. Accordingly, the effective work function of the gate stack will change as the geometry and composition of either the gate dielectric26or gate work-function metal layer28are altered. Therefore, the overall Vt will change as the corners42become more variously rounded and/or thicker and, therefore, adversely increase threshold voltage mismatch (Vtmm) between transistor12and other devices (not shown) associated with structure10.

Further, such rounded corners can be a major contributor to short channel effects (CSE), like the hot carrier effect, since the effective control over the channel22of the gate work-function metal28decreases as it curves away from the channel22in the corner regions42. Essentially, the greater the curvature becomes in the corner regions42, the shorter the effective length of the channel becomes, which increasingly induces such short channel effects.

FIGS. 2-8illustrate various exemplary embodiments of a FinFET and method of making the FinFet in accordance with the present invention.FIGS. 2-7illustrate exemplary methods of making the FinFet.FIG. 8illustrates an exemplary embodiment of the fully formed FinFet. Though a FinFet is illustrated, one skilled in the art would recognize that other transistors, such as CMOS FETs could also be made in accordance with the present invention. Such transistors could be manufactured on a bulk substrate, a silicon on insulator (SOI) substrate or the like.

Referring toFIG. 2, a simplified perspective view of an exemplary embodiment of a structure100for an integrated circuit device in accordance with the present invention is presented at an intermediate stage of manufacturing. Structure100includes a p-well substrate102having an array104of fins106,108,110and112(i.e.,106-112) formed by well-known methods extending laterally across the substrate102. Though illustrated as a p-well substrate, an n-well substrate could also be used. Though four fins are illustrated in array104for this embodiment, any number of fins may be included in the array.

A flowable oxide (FOX) layer114is disposed over the fins106-112of array104. The FOX layer may be applied as a spin-on Si-oxide followed by an annealing process. The FOX layer is then planarized using such methods as chemical-mechanical polishing (CMP) to expose the tops of the fins.

Next the FOX layer is recessed using standard lithographic and etching processes that are well-known. The thickness116of the FOX layer114now defines an inactive region of the fins106-112and the exposed height118of the fins above the FOX layer now defines an active region of the fins.

Referring toFIG. 3, a cross sectional view ofFIG. 2taken through section line3-3after deposition of a dummy gate layer122is presented.FIG. 3includes an oxide layer120disposed over the structure100. Next a dummy gate layer122composed of a dummy gate material, such as a polysilicone material or similar, is disposed over the oxide layer120. Oxide layer120may be formed by thermally oxidizing the exposed surface of fins106-112, or may be deposited onto fins106-112using, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). The dummy gate layer122is deposited over oxide layer120using well-known processes such as chemical vapor deposition (CVD) or the like. Following the deposition, dummy gate layer122can be planarized to facilitate subsequent gate formation steps, using, for example, chemical-mechanical polishing (CMP).

Referring toFIG. 4, a top planar view ofFIG. 3taken through section line4-4after formation of dummy gates124,126,128and130(i.e.,124-130) and spacers132is presented. Dummy gates124-130are created by etching the dummy gate layer122ofFIG. 3using well-known processes such as standard lithographic processes and anisotropic dry etching.

The spacers132are located on the sidewalls of the dummy gates124-130. Spacers132are formed by disposing a conformal coat of spacer material, such as silicon nitride, over the patterned dummy gates124-130and anisotropic etching the spacer material.

Referring toFIG. 5, an expanded cross sectional view of dummy gate128disposed over fin112ofFIG. 4taken along section line5-5is presented. Dummy gate128includes a portion of the dummy gate layer122disposed between the spacers132. After dummy gate128(as well as dummy gates124,126and130) and spacers132are formed, the upper exposed portions of fin112(as well as fins106,108and110) are etched down to, in this exemplary embodiment, about the FOX layer114.

The etched down sections of fin112form the boundaries of source and drain (S/D) regions134of an n-type FinFET136in an intermediate stage of manufacturing. The region of fin112between the S/D regions134is the channel142of FinFET136. In this exemplary embodiment, the S/D regions134are epitaxially grown silicon carbide (SiC) for n-type FinFET, typically grown by such methods as selective vapor-phase epitaxy (VPE), liquid phase epitaxy (LPE) or similar. For example, in this embodiment of an n-type FinFet, a VPE process containing SiC precursors may be used. Alternatively, for a p-type FinFet the precursors may be silicon germanium (SiGe).

As discussed earlier herein, prior art source region18and drain region20of CMOS FET12receive a light in-situ doping of n-type or p-type ions during their epitaxial growth process and thereafter are subjected to a heavy dopant implantation process. In direct contrast, the S/D regions134of FinFET136are heavily doped entirely in-situ during the epitaxial growth process and not subjected to any implantation process. In this example of an n-type FinFET136, phosphorous or arsenic ions may be heavily doped in-situ into the epitaxially grown SiC of S/D regions134. Alternatively, for a p-type FinFET, boron or gallium ions may be heavily doped entirely in-situ into an epitaxially grown SiGe of S/D regions134.

By introducing dopants during the epitaxial growth process entirely in-situ, ion implantation is avoided. Advantageously, this avoids damaging the crystal lattice of S/D regions134by ion bombardment during the implantation process and, therefore, avoids the subsequent need to repair that lattice by additional annealing steps. As a result, random diffusion of ions into the channel142is suppressed and Vtmm between transistor136and other devices (not shown) that are associated with structure100is significantly reduced.

Additionally, the concentration of dopants introduced into S/D regions134by in-situ doping can be chosen such that LDD implants are not required. One way to do this is to use a uniform predetermined concentration of dopant atoms across the entire S/D regions134. In that case, the concentration of in-situ dopant atoms must be high enough to promote robust current flow when the FinFET is in the on-state, but not so high as to exacerbate the short channel effects (SCEs) that the LDD implants where designed to suppress. Preferably the uniform concentration of dopant atoms in S/D regions134should be, for example, within a range of 1021to 1022/cm3.

Alternatively, in order to avoid the use of LDD implants, the concentration of in-situ doping can be dynamically varied such that a first lighter concentration of dopant is introduced during early epitaxial growth of S/D regions134and a second heavier concentration of dopant is introduced during later epitaxial growth of the S/D regions134. In that case, the S/D region134would include a lightly doped portion138and a heavily doped portion140. The lightly doped portion138would have a dopant concentration light enough to suppress any SCEs in the region proximate the dummy gate128, therefore eliminating the need for any LDD implants. The heavily doped portion140would include the bulk of the volume (preferably greater than 80%) of the S/D regions134and have a dopant concentration heavy enough to enable low source/drain resistance for robust current flow when the FinFET136is in the on-state. Preferably the heavily doped portions140should have a concentration of dopant atoms, for example, within a range of 1021to 1022/cm3and the lightly doped portions138should have a concentration of dopant atoms, for example, within a range that is 1 to 20 percent of the heavily doped portion140.

Advantageously, by avoiding the need for LDD implants, the random diffusion of dopants into the channel region142is further reduced. As a result, Vtmm is also further minimized.

Referring toFIG. 6, a cross sectional side view of FinFET136ofFIG. 5after the dummy gate128has been removed is presented. Prior to removal of the dummy gate128, an insulating dielectric layer144, such as SiO2, was deposited over structure100and planarized using CMP to expose the top portion of dummy gates124-130(including dummy gate128). The dummy gates124-130were then removed using a wet chemical etch, such as potassium hydroxide (KOH), or a dry etch such as RIE, leaving open gate trenches146.

In the particular embodiment ofFIG. 6, the gate trench146sidewalls include the generally vertically extending spacers132. The gate trench147bottom includes the exposed portion of a top surface of channel142of fin112. The gate trench146has an aspect ratio that is equal to the width148between the spacers132divided by the spacer height150. Gate trench146also includes a vertically extending centerline164, which extends normally from the trench bottom147(i.e.,the top surface of channel142) and through a center portion of the trench146.

Once the dummy gate material, such as polysilicone, of the dummy gate128is removed, a gate dielectric layer152is then conformally coated over trench146. The gate dielectric layer152is a high k dielectric and may be coated over trench146by such means as atomic layer deposition (ALD).

Referring toFIG. 7, a cross sectional view ofFIG. 6after the deposition of a work-function metal layer154is presented. The work-function metal may be a material such as titanium nitride (TiN) (for p-type work-function), titanium aluminum carbide (TiAlC) (for n-type work-function), tantalum nitride (TaN) or similar, which can be conformally deposited over the gate dielectric152using such processes as ALD.

It is important to note that work-function metal layer154has a pair of corner regions156proximate the trench bottom147that are not consistently perfectly square. Because the corner regions156are variously rounded, they curve away from channel142and tend to be thicker relative to a middle region157of the work-function metal layer154. For purposes of clarity, the middle region157is considered herein to be that portion of the work-function metal layer154that is outside of the corner regions156and includes, at least, that portion of the work-function metal layer154through which vertical centerline164of trench146passes.

Due, in part, to the geometric differences between the corner regions156and middle region157of the work-function metal layer154, the gate stack (which includes at least the gate dielectric layer152and the work-function metal layer154) has an effective work function at its corner regions156that is potentially different from the effective work function at its middle region157. Typically, the effective work function at the corner regions156is larger than the effective work function at the middle region157. This variance in effective work function across the work-function metal layer154can potentially alter overall threshold voltage (Vt) of FinFET136. Typically, the greater the increase in the effective work function in the corner regions156over the middle region157, the greater will be the potential variation in the overall Vt of FET136. Additionally, the greater the potential difference in overall Vt of FET136relative to other devices (not shown) associated with structure100, the greater will be the potential Vtmm for structure100.

In order to offset the geometric tendency within the curved corner regions156to alter the Vt of FinFET136, the corner regions156of work-function metal layer154are subjected to an angled implantation process158. The angled implantation process158implants any of a number of predetermined work-function tuning species160at a predetermined tilt angle θ162into the corner regions156in order to modify the material composition of the work-function metal154in those regions.

By modifying the material composition, the effective work-function of the gate stack (including at least work-function metal154and gate dielectric152) in the corner regions156can be altered (or tuned). By tuning the effective work-function in the corner regions156, the value of the effective work function in the corner regions156can be adjusted (upwards or downwards) so that the Vt at the corner is closer or slightly lower to the value of the effective work function in the middle region157of layer154.

By utilizing the angled implantation process158to implant tuning work function species160into the corner regions156of layer154, the effective work function across the bottom of the work-function metal layer154can be tuned to be substantially uniform from one corner region156to the other corner region156of the work-function metal layer154. Essentially, the effective work function can be made substantially uniform across the entire length of the channel142. Preferably, a substantially uniform effective work function would be to have the corner regions156of layer154tuned within 20% of the middle region157, more preferably within 10% and most preferably within 5%.

The tilt angle θ162of the implantation process158(such as a plasma implantation process) is measured from the vertical centerline164of gate trench146and must be greater than zero. Preferably the tilt angle θ162should be greater than 5 degrees from vertical centerline164, more preferably 10 degree and most preferably 15 degrees.

However, if the tilt angle θ162is too large, the work function tuning species will not be able to reach the targeted corner regions156located proximate the bottom147of the gate trench146. More specifically, the smaller the width148(best seen inFIG. 6) between the spacers132relative to the spacer height150(best seen inFIG. 6) the smaller the tilt angle θ162from the vertical centerline164must be. As previously discussed, the gate trench146aspect ratio is equal to the width148between the spacers132divided by the spacer height150. Therefore, the aspect ratio of gate trench146would be approximately equal to the tangent of the largest tilt angle θ that the angled species implantation process could have and still be able to implant tuning species160into the corner regions156. Therefore, it is preferable that the tangent of tilt angle θ162be less than the aspect ratio of gate trench146to assure proper targeting of the corner regions156during the angled species implantation process158.

The work function tuning species can be any number of elements and/or compounds that can alter the material composition of the corner regions156of any specific work-function metal layer154. For example, an angled implant of nitrogen (N) can increase the effective work function of a p-type gate stack having a TiN work-function metal layer154, and therefore achieve a lower Vt value of the p-FET using that metal layer. Additionally, for n-type gate stacks using TiN or TiAlC as a gate (n-type) work-function metal layer, additional aluminum (Al) species may be used to tune the Vt in the corner regions156to a lower value. Other, but not all, work function tuning species that may be used for various tuning applications are boron difluoride (BF2), lanthanum (La), hydrogen (H2) and fluorine (F).

Moreover, by tuning the corner regions156through the angled species implantation process158to provide a substantially uniform effective work function across the entire bottom of the work-function metal layer154, better control across the entire channel142is established. As a result the effective channel length of channel142is increased. By increasing the effective channel length of channel142, the leakage current is greatly reduced, therefore eliminating the need for any halo implants to offset that leakage current.

Referring toFIG. 8, a cross sectional view ofFIG. 7after the deposition of gate electrode metal166to complete the formation of FinFET136is presented. The gate electrode metal may be tungsten, aluminum, cobalt, copper or similar.

In this embodiment, the insulating dielectric layer144has also been removed by an etching process to expose the S/D regions for processing. For example, the S/D regions may now be subjected to silicide and contact formation.

The now completed FinFET136includes S/D regions134that were doped n-type (or p-type of FinFET136were designed to be a p-type FET) entirely in-situ during epitaxial growth of the S/D regions. Therefore any implantation processing on those regions134was avoided and no annealing processing was necessary. Accordingly, the number of randomly diffused dopant ions168has been greatly reduced over that of the prior art. In this particular embodiment, a lightly doped portion138and a larger by volume heavily doped portion140of the S/D regions134have been dynamically doped in-situ to eliminate the need for any LDD implants.

Further, the corner regions156of work function metal layer154has had a work function tuning species160implanted therein via an angled species implantation process158. The implantation process158has tuned the corner regions156to provide a substantially uniform effective work function across the entire effective length of the channel142(i.e., from one corner region156to the other corner region156). By doing so, Vt for FinFET136is better controlled and Vtmm between FinFET136and other devices associated with structure100is reduced.

Additionally, by tuning the corner regions156, control of the channel142is enhanced at the corner regions, and the effective channel length is increased. As a result, leakage current is reduced, therefore the need for halo implants are eliminated. Eliminating any halo implants also reduces the concentration of randomly diffused dopant ions168in the channel142, further reduces Vtmm between devices.

Although the invention has been described by reference to specific embodiments, it should be understood that numerous changes may be made within the spirit and scope of the inventive concepts described. Accordingly, it is intended that the invention not be limited to the described embodiments, but that it have the full scope defined by the language of the following claims.