Semiconductor structure and manufacturing method of the same

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a stacked structure, a plurality of first conductive blocks, a plurality of first conductive layers, a plurality of second conductive layers, and a plurality of conductive damascene structures. The stacked structure, comprising a plurality of conductive strips and a plurality of insulating strips, is formed on a substrate, and the conductive strips and the insulating strips are interlaced. The first conductive blocks are formed on the stacked structure. The first conductive layers and the second conductive layers are formed on two sidewalls of the stacked structure, respectively. The conductive damascene structures are formed on two sides of the stacked structure, wherein each of the first conductive blocks is electrically connected to each of the conductive damascene structures via each of the first conductive strips and each of the second conductive strips.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The disclosure relates in general to a semiconductor structure and a manufacturing method of the same, and more particularly to a semiconductor structure and a manufacturing method of the same for a memory device.

2. Description of the Related Art

In recent years, the structures of semiconductor devices have been changed constantly, and the storage capacity of the devices has been increased continuously. Memory devices are used in storage elements for many products such as MP3 players, digital cameras, computer files, etc. As the application increases, the demand for memory devices focuses on small sizes and large memory capacities. However, as the size of memory devices is reduced, the feature sizes of memory cells are decreased as well, causing a decrease in reliability of memory devices. As such, it is desirable to develop memory devices with improved reliability.

SUMMARY OF THE INVENTION

The invention is directed to a semiconductor structure and a manufacturing method of the same, which can be used in memory devices. In the semiconductor structure, each of conductive damascene structures is formed independently on two sides of a stacked structure by a damascene process, such that the conductive damascene structures are perfectly separated from one another, there would be no residual conductive materials between the conductive damascene structures, thus, a good insulation between the conductive damascene structures is achieved, and the reliability of memory devices can be improved.

According to one embodiment of the present disclosure, a semiconductor structure is provided. The semiconductor structure comprises a stacked structure, a plurality of first conductive blocks, a plurality of first conductive layers, a plurality of second conductive layers, and a plurality of conductive damascene structures. The stacked structure is formed on a substrate, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The first conductive blocks are formed on the stacked structure. The first conductive layers and the second conductive layers are formed on two sidewalls of the stacked structure, respectively.

The conductive damascene structures are formed on two sides of the stacked structure, wherein each of the first conductive blocks is electrically connected to each of the conductive damascene structures via each of the first conductive strips and each of the second conductive strips.

According to one embodiment of the present disclosure, a method of manufacturing a semiconductor structure is provided. The method comprises the following steps. A stacked structure is formed on a substrate, wherein a plurality of conductive strips and a plurality of insulating strips are formed, and the conductive strips and the insulating strips are interlaced. A plurality of first conductive blocks is formed on the stacked structure. A plurality of first conductive layers and a plurality of second conductive layers are formed on two sidewalls of the stacked structure, respectively. A plurality of conductive damascene structures is formed on two sides of the stacked structure, wherein each of the first conductive blocks is electrically connected to each of the conductive damascene structures via each of the first conductive strips and each of the second conductive strips.

DETAILED DESCRIPTION OF THE INVENTION

In the embodiment of the present disclosure, a semiconductor structure and a manufacturing method of the same are provided. In the semiconductor structure, each of conductive damascene structures is formed independently on two sides of a stacked structure by a damascene process, such that the conductive damascene structures are perfectly separated from one another, there would be no residual conductive materials between the conductive damascene structures, thus, a good insulation between the conductive damascene structures is achieved, and the reliability of memory devices can be improved. However, the descriptions disclosed in the embodiments of the disclosure such as detailed structures, manufacturing procedures, operating procedures, and material selections are for illustration only, not for limiting the scope of protection of the disclosure.

FIG. 1Ashows a top view of a semiconductor structure according to an embodiment of the present disclosure.FIG. 1Bshow a cross-sectional view along the section line1B-1B′ inFIG. 1A.FIGS. 1C-1Dshow cross-sectional views along the section line1C-1C′ inFIG. 1A.

Please refer toFIGS. 1A-1B. Semiconductor structure100comprises a substrate110, a stacked structure120, a plurality of first conductive blocks141, a plurality of first conductive layers131, a plurality of second conductive layers133, and a plurality of conductive damascene structures150. The stacked structure120is formed on the substrate110. The stacked structure120comprises a plurality of conductive strips121and a plurality of insulating strips123, and the conductive strips121and the insulating strips123are interlaced. The first conductive blocks141are formed on the stacked structure120, and the first conductive layers131and the second conductive layers133are formed on two sidewalls120aof the stacked structure120, respectively. The conductive damascene structures150are formed on two sides of the stacked structure120, and each of the first conductive blocks141is electrically connected to each of the conductive damascene structures150via each of the first conductive strips131and each of the second conductive strips133.

In an embodiment, as shown inFIG. 1A, the semiconductor structure100can further comprise an insulating structure160formed between the conductive damascene structures150. In the embodiment, as shown inFIG. 1B, the semiconductor structure100can comprise a plurality of stacked structures120, and the insulating structure160is also formed between the stacked structures120. In the embodiment, the conductive damascene structures150are extended in a direction D1perpendicular to a direction D2which the stacked structure120is extended in. In the embodiment, the material of the insulating structure comprises, for example, nitrides.

In an embodiment, the semiconductor structure100is such as a 3D memory device, as shown inFIGS. 1A-1B, for example, the stacked structure120is a bit line, the conductive damascene structure150is the main body of a word line, and a working voltage is applied through the first conductive layer131and the second conductive layer133. Conventionally, a full metal film is etched to form separated word lines. However, the word lines may be short-circuited due to the residual metal materials between the word lines, caused by an incomplete etching between the word lines, resulting in a malfunction of the memory device. In contrast, in the embodiment of the disclosure, each of conductive damascene structures150is formed independently on two sides of the stacked structure120by a damascene process, such that the conductive damascene structures150are perfectly separated from one another. As such, there would be no residual conductive materials between the conductive damascene structures (word lines), a good insulation between the word lines is achieved, the memory device can function well, and the reliability of memory device can be improved.

In an embodiment, as shown inFIG. 1B, the semiconductor structure100can further comprise a dielectric layer170formed on the stacked structure120and the conductive damascene structures150. In the embodiment, the semiconductor structure100can further comprise an etching stop layer173, and the etching stop layer173is such as disposed between the dielectric layer170and the stacked structure120. In the embodiment, the material of the dielectric layer170such as comprises metal nitrides. However, the material selections are depending on the conditions applied and are not limited to the materials aforementioned.

In an embodiment, as shown inFIG. 1B, the semiconductor structure100can further comprise a memory materials layer180formed on the two sidewalls120aof the stacked structure120. In the embodiment, the memory material layer180is formed between the first conductive layers131and the stacked structure120and between the second conductive layers133and the stacked structure120. In the embodiment, as shown inFIG. 1B, the memory material layer180is formed on the substrate110. In another embodiment, the memory material layer180can also be only formed on the two sidewalls120aof the stacked structure120and not formed on the substrate110(not shown). In the embodiment, the memory material layer180may have a multi-layer structure, for example, which may be ONO composite layers, ONONO composite layers, or BE-SONOS composite layers, or comprise, for example, an ONO structure formed by alternately stacking silicon oxide and silicon nitride.

In an embodiment, as shown inFIG. 1B, the semiconductor structure100can further comprise an oxide layer115formed between the stacked structure120and the substrate110.

Please refer toFIG. 1C. The semiconductor structure100can further comprise a second conductive block143, a third conductive layer135, and a fourth conductive layer137. The second conductive block143is formed on the stacked structure120, and the third conductive layer135and the fourth conductive layer137are formed on the two sidewalls120aof the stacked structure120, respectively. The second conductive block143is electrically connected to the third conductive layer135and the fourth conductive layer137. In the embodiment, as shown inFIG. 1A, the second conductive block143, the third conductive layer135, and the fourth conductive layer137are formed, for example, on an end of the semiconductor structure100. In the embodiment, the material of the first conductive block141is, for example, the same as the material of the second conductive block143are the same, and the materials of the first conductive layer131, the second conductive layer133, the third conductive layer135, and the fourth conductive layer137are, for example, the same. In the embodiment, the materials for the substrate110, and conductive blocks141and143, and the conductive layers131,133,135, and137comprise, for example, silicon-containing materials, such as polysilicon. However, the material selections are depending on the conditions applied and are not limited to the materials aforementioned.

In an embodiment, the semiconductor structure100is such as a 3D memory device, as shown inFIG. 1D, the second conductive block143is such as a string select line (SSL).

In an embodiment, as shown inFIG. 1C, the semiconductor structure100can further comprise an insulating damascene structure190formed on two sides of the second conductive block143, and the insulating damascene structure190is such as connected to the second conductive block143. In the embodiment, as shown inFIG. 1C, the insulating damascene structure190covers, for example, the third conductive layer135and the fourth conductive layer137. In the embodiment, the insulating damascene structure190is extended in a direction D3parallel to the direction D1which the conductive damascene structures150are extended in.

In an embodiment, referring toFIG. 1D, the semiconductor structure100can further comprise a contact hole175formed in the dielectric layer170and electrically connected to the second conductive block143. In the embodiment, as shown inFIG. 1D, the contact hole175penetrates through the etching stop layer173to be electrically connected to the second conductive block143.

The embodiments disclosed below are for elaborating a manufacturing method of the semiconductor structures of the disclosure. However, the descriptions disclosed in the embodiments of the disclosure such as detailed manufacturing procedures are for illustration only, not for limiting the scope of protection of the disclosure. Referring toFIGS. 2A-21,FIGS. 2A-21illustrate a process for manufacturing a semiconductor structure according to one embodiment of the present disclosure.

Referring toFIGS. 2A-2B(FIG. 2Bshows a cross-sectional view along the section line2B-2B′ inFIG. 2A), a stacked structure120is formed on the substrate110. The manufacturing method of forming the stacked structure120comprises, for example: forming a plurality of conductive strips121and a plurality of insulating strips123, and the conductive strips121and the insulating strips123are interlaced. In an embodiment, a plurality of stacked structures120can also be formed on the substrate110.

Next, as shown inFIGS. 2A-11E, a plurality of first conductive blocks143are formed on the stacked structure120, and a plurality of first conductive layers131and a plurality of second conductive layers131are formed on two sidewalls120aof the stacked structure120, respectively. The manufacturing method of forming the first conductive blocks143, the first conductive layers131, and the second conductive layers133comprises, for example, the following steps.

As shown inFIGS. 2A-2B, a conductive material layer140is formed on the stacked structure120. In the embodiment, an oxide layer150can also be formed between the stacked structure120and the substrate110.

As shown inFIGS. 3A-3B(FIG. 3Bshows a cross-sectional view along the section line3B-3B′ inFIG. 3A), a memory material coating layer180ais formed on the stacked structure120. In the embodiment, the memory material coating layer180afully covers the stacked structure120, the conductive material layer140, and the substrate110. The memory material coating layer180acomprises a charge trapping material, for example, ONO composite layers, ONONO composite layers, or BE-SONOS composite layers, or comprises, for example, an ONO structure formed by alternately stacking silicon oxide and silicon nitride.

As shown inFIGS. 4A-4B(FIG. 4Bshows a cross-sectional view along the section line4B-4B′ inFIG. 4A), a sacrificial layer210is formed on the substrate110. In the embodiment, the sacrificial layer210surrounds the stacked structure120and the peripheral of the memory material coating layer180a, and at least part of the conductive material layer140and the memory material coating layer180ais exposed. In the embodiment, the sacrificial layer210comprises, for example, at least one of pure carbon, carbon-containing oxide, bottom antireflective coating (BARC), and silicon rich bulk (SHB). The sacrificial layer210may also be disposable films formed of carbon like organic materials, which are easily coated and removed. The sacrificial layer210may be formed by one etch back process which is highly selective to the memory material coating layer180afor the memory material coating layer180ato be exposed.

As shown inFIGS. 5A-5B(FIG. 5Bshows a cross-sectional view along the section line5B-5B′ inFIG. 5A), the memory material coating layer180ais etched to expose the conductive material layer140and form a memory material layer180on the two sidewalls120aof the stacked structure120. In the embodiment, the memory material coating layer180aexposed from the sacrificial layer210is etched to form the memory material layer180, and the top of the memory material layer180is substantially aligned with the upper surface of the sacrificial layer210. In the embodiment, the memory material layer180is such as formed between the sacrificial layer210and the stacked structure120.

As shown inFIGS. 6A-6B(FIG. 6Bshows a cross-sectional view along the section line6B-6B′ inFIG. 6A), the sacrificial layer210is removed to expose the memory material layer180. In the embodiment, part of the memory material layer180on the substrate110can also be removed, such that the memory material layer180is only located on the two sidewalls120aof the stacked structure120.

As shown inFIGS. 7A-7B(FIG. 7Bshows a cross-sectional view along the section line7B-7B′ inFIG. 7A), a conductive material layer130is formed on the stacked structure120and the conductive material layer140. In the embodiment, the conductive material layer130fully covers the conductive material layer140and the memory material layer180. The memory material layer180may be highly doped polysilicon or a conformal conductive film.

As shown inFIGS. 8A-8B(FIG. 8Bshows a cross-sectional view along the section line8B-8B′ inFIG. 8A), the conductive material layer130is etched to expose part of the conductive material layer140. In the embodiment, the conductive material layer130covers the memory material layer180and surrounds the stacked structure120.

As shown inFIGS. 9A-9B(FIG. 9Bshows a cross-sectional view along the section line9B-9B′ inFIG. 9A), a sacrificial layer220is formed on the substrate110. In the embodiment, the sacrificial layer220surrounds the stacked structure120and covers the conductive material layer130on the sidewalls120a, exposing an upper surface140aof the conductive material layer140. The manufacturing method of forming the sacrificial layer220comprises, for example: forming a sacrificial coating layer to fully cover the conductive material layer130, the conductive material layer140, and the substrate; and planarizing the sacrificial layer220to expose the upper surface140aof the conductive material layer140. In the embodiment, the sacrificial coating layer is planarized by such as a chemical mechanical polishing (CMP) process. In the embodiment, the material of the sacrificial layer220comprises, for example, silicon nitride (SiN).

As shown inFIGS. 10A-10E(FIGS. 10B-10Eshow cross-sectional views along the section lines10B-10B′ to10E-10E′ inFIG. 10A), patterning the sacrificial layer220to form a plurality of sacrificial strips220a, and the sacrificial strips220aare extended in a direction D4perpendicular to the direction D2which the stacked structure120is extended in. In the embodiment, the manufacturing method of forming the sacrificial strips220acomprises, for example: forming a plurality of photoresist strips PR1on the sacrificial layer220and etching the sacrificial layer220according to the pattern of the photoresist strips PR1to form the sacrificial strips220a. In the embodiment, the photoresist strips PR1are arranged by such as a self-aligned double patterning (SADP) process. In the embodiment, where the sacrificial strips220aare located are the predetermined positions for the conductive damascene structures to be formed in the following steps.

As shown inFIGS. 11A-11E(FIGS. 11B-11Eshow cross-sectional views along the section lines11B-11B′ to11E-11E′ inFIG. 11A), a region of the conductive material layer140exposed from the photoresist strips PR1is etched to form a plurality of first conductive blocks141and a second conductive block143on the stacked structure120. In the embodiment, a region of the conductive material layer130exposed from the photoresist strips PR1can also be etched to form a plurality of first conductive layers131and a second conductive layer133on the sidewalls120aof the stacked structure120. In the embodiment, each of the first conductive blocks141is spaced apart from the others, each of the first conductive layers131is spaced apart form the others, and each of the second conductive layers133is spaced apart form the others. In the embodiment, each of the first conductive blocks141is adjacent to a corresponding first conductive layer131and a corresponding second conductive layer133, and the first conductive layer131and the second conductive layer133are adjacent to a corresponding sacrificial layer220a. In the embodiment, the first conductive block141is electrically connected to the first conductive layer131and the second conductive layer133.

As shown inFIGS. 11A-11E, as the conductive material layer130and the conductive material layer140exposed from the photoresist strips PR1are removed, a second conductive block143can be also formed on the stacked structure120, and a third conductive layer135and a fourth conductive layer137(not shown) can also be formed on the two sidewalls120aof the stacked structure120. In the embodiment, the first conductive blocks141and the second conductive block143are spaced apart, the first conductive layers131and the third conductive layer135are spaced apart, and the second conductive layers133and the fourth conductive layer137are spaced apart. In the embodiment, the third conductive layer135and the fourth conductive layer137are adjacent to a corresponding sacrificial strip220a. In the embodiment, the second conductive block143is electrically connected to the third conductive layer135and the fourth conductive layer137.

Next, as shown inFIGS. 13A-13E(FIGS. 13B-13Eshow cross-sectional views along the section lines13B-13B′ to13E-13E′ inFIG. 13A), an insulating structure160can also be formed between the sacrificial strips220a(between the conductive damascene structures formed in the following steps). In the embodiment, the insulating structure160is also formed between the stacked structures120. In the embodiment, the manufacturing method of forming the insulating structure160comprises, for example: forming an insulating material layer on the stacked structure120, the first conductive blocks141, the second conductive block143, and the sacrificial strips220a; and planarizing the insulating material layer to expose the first conductive blocks141, the second conductive block143, and the sacrificial layer220a. In the embodiment, the insulating material layer is planarized by such as a CMP process.

Next, as shown inFIGS. 14A-14E(FIGS. 14B-14Eshow cross-sectional views along the section lines14B-14B′ to14E-14E′ inFIG. 14A), a cap layer230can also be formed on the second conductive block143, the third conductive layer135, the fourth conductive layer137, and adjacent to which the sacrificial strip220a. In the embodiment, the manufacturing method of forming the cap layer230comprises, for example: forming a cap material layer covering the first conductive blocks141, the second conductive block143, the first conductive layers131, the second conductive layers133, the third conductive layer135, the fourth conductive layer137, and the sacrificial strips220a; and removing part of the cap material layer not covering the second conductive block143, the third conductive layer135, the fourth conductive layer137, and adjacent to which the sacrificial strip220a. In the embodiment, the material of the cap layer230comprises such as oxides.

Next, as shown inFIGS. 15A-16E, a plurality of conductive damascene structures150are formed on two sides of the stacked structure120. Each of the first conductive blocks141is electrically connected to each of the conductive damascene structures150via each of the first conductive strips131and each of the second conductive strips133. The manufacturing method of forming the conductive damascene structures150on the two sides of the stacked structure comprises such as the following steps.

As shown inFIGS. 15A-15E(FIGS. 15B-15Eshow cross-sectional views along the section lines15B-15B′ to15E-15E′ inFIG. 15A), a plurality of trenches T are formed on the two sides of the stacked structure120. In the embodiment, the trenches T are extended in a direction D5perpendicular to the direction D2which the stacked structure120is extended in. In the embodiment, the manufacturing method of forming the trenches T comprises, for example: removing the sacrificial strips220exposed from the cap layer230. In the embodiment, the sacrificial strips220aare removed by such as an etching process, and the sacrificial layer covered by the cap layer230is not removed.

As shown inFIGS. 16A-16E(FIGS. 16B-16Eshow cross-sectional views along the section lines16B-16B′ to16E-16E′ inFIG. 16A), a conductive material is filled in the trenches T to form the conductive damascene structure150. In the embodiment, the conductive damascene structures150are formed in trenches T which are separated from one another. Therefore, a good insulation between the conductive damascene structures150is achieved. That is to say, each of conductive damascene structures150is formed independently in each of the trenches T, which are separated from one another, by a damascene process, such that the conductive damascene structures150are perfectly separated from one another. There would be no residual conductive materials between the conductive damascene structures150, thus, a good insulation between the conductive damascene structures150is achieved, and the reliability of the device to be manufactured in the following process an be improved.

Next, as shown inFIGS. 18A-19E, an insulating damascene structure190can also be formed on two sides of the second conductive block143. The insulating damascene structure190is located adjacent to the second conductive block143. The manufacturing method of forming the insulating damascene structure190on the two sides of the second conductive block143comprises such as the following steps.

As shown inFIGS. 18A-18E(FIGS. 18B-18Eshow cross-sectional views along the section lines18B-18B′ to18E-18E′ inFIG. 18A), a trench T′ is formed on the two sides of the second conductive block143. In the embodiment, the trench T′ is extended in a direction D6perpendicular to the direction D2which the stacked structure is extended in. In the embodiment, the manufacturing method of forming the trench T′ comprises, for example: removing the sacrificial strip220apreviously covered by the cap layer230. That is, the sacrificial strip220alocated adjacent to the second conductive block143, the third conductive layer135, and the fourth conductive layer137is removed. In the embodiment, the sacrificial strip220ais removed by such as an etching process.

As shown inFIGS. 19A-19F(FIGS. 19B-19Fshow cross-sectional views along the section lines19B-19B′ to19F-19F′ inFIG. 19A), an insulating material is filled in the trench T′ to form the insulating damascene structure190.

Next, as shown inFIGS. 20A-20F(FIGS. 20B-20Fshow cross-sectional views along the section lines20B-20B′ to20E-20F′ inFIG. 20A), a dielectric layer170can also be formed on the stacked structure120. In the embodiment, the dielectric layer170can also be formed on the conductive damascene structures150and the insulating damascene structure190. In the embodiment, an etching stop layer173can also be formed between the dielectric layer170and the stacked structure120.

Next, as shown inFIG. 21, a contact hole175can also be formed in the dielectric layer170. In the embodiment, the contact hole175is electrically connected to the second conductive block143.