Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device prevents a lower electrode from leaning, in a dip-out process of an interlayer insulation film forming a lower electrode. A conductive material of a lower electrode is used as a support layer instead of a conventional nitride film support layer. This prevents a crack from being generated in a nitride film support layer. A method for manufacturing the semiconductor device is also disclosed.

CROSS-REFERENCE TO RELATED APPLICATION

The priority of Korean patent application No. 10-2011-0096347 filed on 23 Sep. 2011, the disclosure of which is hereby incorporated in its entirety by reference, is claimed.

BACKGROUND OF THE INVENTION

Embodiments of the present invention relate to a method for manufacturing a semiconductor device, and more particularly to a method for forming a semiconductor device including a storage node.

In general, a Dynamic Random Access Memory (DRAM) cell includes a capacitor for storing charges indicating information to be stored and a transistor for addressing the charges stored in the capacitor. Typically, a transistor formed over a semiconductor substrate includes a gate electrode for removing a current flowing in a source/drain region. Charges stored in the capacitor can be accessed through the transistor.

Storage capacity of the charges stored in the capacitor is called capacitance. As capacitance increases, a larger amount of information can be stored in the capacitor.

The capacitance can be represented by the following equation (1).
C=εA/D(1)

In this case, ‘ε’ is permittivity (or the dielectric constant) determined by a type of a dielectric film disposed between two electrodes, ‘d’ is a distance from one electrode to the other electrode, and ‘A’ is an effective surface area of the two electrodes. As can be seen from Equation (1), as permittivity (ε) of the dielectric film is increased and the distance (d) between two electrodes is reduced, a surface area (A) of the two electrodes is increased such that capacitance of the capacitor can also be increased.

In this case, ‘ε’ is permittivity (or the dielectric constant), A is an effective surface area of an electrode, and ‘d’ is a distance from one electrode to the other electrode. Therefore, in order to increase capacitance of the capacitor, the surface area of each electrode can be increased, thickness of a dielectric thin film can be reduced, or permittivity of the dielectric thin film can be increased. In order to increase the effective area of the electrode, the electrode structure of the capacitor is modified into a three-dimensional (3D) structure, for example, a concave structure, a cylindrical structure, etc.

In order to form the concave capacitor, a hole, in which a capacitor electrode is to be formed, is formed in an interlayer insulation film, a lower electrode of the capacitor is formed on an inner surface of the hole, and a dielectric film and an upper electrode are deposited over the lower electrode, such that the concave capacitor can be formed. As the semiconductor device is highly integrated, it is difficult for the concave capacitor to guarantee sufficient capacitance required for each cell within a limited cell region. Therefore, a cylindrical capacitor capable of providing a surface area larger than that of the concave capacitor has recently been proposed.

In order to form the cylindrical capacitor, a hole, in which a capacitor electrode is to be formed, is formed in an interlayer insulation film, and a lower electrode of the capacitor is formed in the hole, the interlayer insulation film is removed, and a dielectric film and an upper electrode are deposited over the remaining lower electrode, such that the cylindrical capacitor can be formed. The cylindrical capacitor may use both of the inside and outside of the lower electrode as an effective surface area of the capacitor, such that it has higher capacitance than the concave capacitor.

A dip-out process is may be used for the formation of the cylindrical capacitor.

However, the dip-out process is carried out by a wet process including a chemical solution. The chemical solution may unavoidably generate slanting or leaning of the storage-node lower electrode. Specifically, if there is a high aspect ratio of the storage-node lower electrode due to higher integration of the semiconductor device, slanting and leaning of the lower electrode are considered to be serious problems. In recent times, in order to overcome the above-mentioned problems, a nitride film support layer between lower electrodes has been used.

However, since various kinds of materials are formed in the vicinity of the nitride film support layer, a crack occurs in the nitride film support layer due to unbalanced stress between different materials. Due to such crack, defective products continuously occur upon completion of a package fabrication, resulting in reduction in product quality.

BRIEF SUMMARY OF THE INVENTION

Various embodiments of the present invention are directed to providing a method for manufacturing a semiconductor device that substantially obviates one or more problems in the related art.

Embodiments of the present invention relate to a method for manufacturing a semiconductor device to prevent a lower electrode from leaning, in a dip-out process of an interlayer insulation film forming the lower electrode. In the semiconductor device, the conductive material of a lower electrode is used as a support layer instead of a conventional nitride film support layer. This can prevent a crack from being generated in a nitride film support layer.

In accordance with an embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a sacrificial insulation film defining a storage node region over a semiconductor substrate; forming a first conductive material over the entirety of the semiconductor substrate including the sacrificial insulation film; etching the first conductive material formed over the sacrificial insulation film and an upper part of the sacrificial insulation film so as to form a hole for exposing the sacrificial insulation film, wherein the first conductive material remains at both sides of the hole; removing the sacrificial insulation film; forming a dielectric film over the first conductive material; forming a second conductive material over the entirety of the semiconductor substrate including the dielectric film; forming a capping film pattern exposing the second conductive material of the storage node region over the first conductive material, the dielectric film, and the second conductive material; and forming a third conductive material coupled to the second conductive material over the second conductive material and the capping film pattern.

The removing of the sacrificial insulation film may be carried out using a wet process utilizing an HF or BOE-based etchant. The etchant may be received through the hole.

The method may further include planarizing the first conductive material and the second conductive material until the first conductive material located at both sides of the hole is removed, thereby forming a lower electrode.

Each of the first conductive material, the second conductive material, and the third conductive material may be formed of any one of a titanium (Ti) film, a titanium nitride (TiN) film, a ruthenium (Ru) film, and a combination thereof. The method may further include, after the formation of the third conductive material coupled to the second conductive material, forming an upper electrode by planarizing the third conductive material.

The first conductive material located at both sides of the hole may be used as a support layer in the process of removing the sacrificial insulation film. When forming the second conductive material, the second conductive material may be buried in both of the inside and outside of the first conductive material.

The capping film pattern may be formed of a material including an oxide film.

DESCRIPTION OF EMBODIMENTS

FIGS. 1 to 11are cross-sectional views illustrating a method for forming a semiconductor device according to embodiments of the present invention.

Referring toFIG. 1, an interlayer insulation film100is formed over a semiconductor substrate (not shown) which may include a lower structure such as a gate electrode, a landing plug contact, etc. The interlayer insulation film100is etched so that a storage node contact hole (not shown) exposing a lower landing plug contact is formed.

A conductive material is formed over the entire surface including a storage node contact hole (not shown) A planarization etching process is performed until the interlayer insulation film100is exposed, such that the storage node contact plug103is formed. A conductive material formed within the storage node contact hole (not shown) may include polysilicon.

Thereafter, an etch stop layer105is formed over the storage node contact plug103and the interlayer insulation film100. The etch stop layer105may be formed of a nitride film. The etch stop layer105adjusts the degree of etching in a subsequent etching process for forming a storage node region, so that it can prevent the storage node contact plug103from being damaged. In certain embodiments, an over-etch process may form the storage node region using the selection ratio between the nitride film acting as the etch stop layer105, and the polysilicon layer acting as the storage node contact plug103.

Subsequently, a sacrificial insulation film110is formed over the etch stop layer105. The sacrificial insulation film110may be formed of a material including an oxide film. The sacrificial insulation film110may be formed of any one of a Phospho-Silicate-Glass (PSG) oxide film, a Tetra-Ethyl-Ortho-Silicate (TEOS) oxide film, and a combination thereof.

Referring toFIG. 2, a photoresist pattern (not shown) defining a storage-node scheduled region is formed over the sacrificial insulation film110. The sacrificial insulation film110and the etch stop layer105are etched using the photoresist pattern (not shown) as an etch mask, so that a storage node region115exposing the storage node contact plug103is formed. In this case, the storage node region115may be wider than that of the storage node contact plug103. Thereafter, the photoresist pattern (not shown) is removed.

Referring toFIG. 3, a first conductive material120is deposited over the entirety of the sacrificial insulation film110including the storage node region115. The first conductive material120may be formed of any one of a titanium (Ti) film, a titanium nitride (TiN) film, a ruthenium (Ru) film, and a combination thereof.

Referring toFIG. 4, a passivation film (not shown) is formed using a photoresist film, with the passivation film to be buried between the first conductive materials120. A mask pattern (not shown) is formed over the passivation film (not shown) and the first conductive material120. The mask pattern (not shown) may be formed to open a portion of the first conductive material120formed over the sacrificial insulation film110.

Subsequently, upper parts of the first conductive material120and the sacrificial insulation film110are etched using the mask pattern (not shown) as an etch mask, resulting in formation of a hole125into which a wet solution can be inserted in a subsequent dip-out process. In this case, the hole125may be formed at the center part of the sacrificial insulation film110, and may be minimized in size within a range into which the wet solution can be inserted. The hole125may be smaller than a full length of the sacrificial insulation film to allow the remaining first conductive material120(See the part “A”) located at both sides of the hole125to be used as a support layer120afor supporting the first conductive material120in the dip-out process.

Referring toFIG. 5, a mask pattern (not shown) and a passivation film (not shown) are removed, and a wet solution is inserted into the hole125in such a manner that the dip-out process is performed.

The first conductive material120is thus separated from other materials by removing the sacrificial insulation film110.

The dip-out process may be carried out by a wet process based on a chemical. The dip-out process may use an HF or Buffered Oxide Etch (BOE-based) etchant. In this case, the first conductive material120is prevented from leaning as a result of the dip-out process, owing to the presence of the support layer120asuch as the part “A”.

Referring toFIG. 6, a dielectric film130is formed over the first conductive material120. The dielectric film130may be formed of any one of a TiO2film, a ZrO2film, a HFO2film, an Al2O3film, a (Ba, Sr)TiO3(BST) film, a SrBi2Ta2O9(SBT) film, and a combination thereof.

Referring toFIG. 7, a second conductive material140ais formed over the surface including the dielectric film130. The second conductive material140amay be formed to bury both of the inside and outside of the first conductive material120. In this case, the second conductive material140amay be formed of any one of a titanium (Ti) film, a titanium nitride (TiN) film, a ruthenium (Ru) film, and a combination thereof.

Referring toFIG. 8, a planarization process is performed until the support layer120aof the first conductive material120is removed, such that a second conductive material140a, a first conductive material120, and a dielectric film130are removed by the planarization process. The planarization process may be performed by a Chemical Mechanical

Polishing process or an etch-back process. In this case, the support layer120aof the first conductive material120is removed, so that the lower electrode120bof a cylindrical shape is configured in an isolated form.

Referring toFIG. 9, a capping film145is formed over the lower electrode120b, the dielectric film130, and the second conductive material140a. The capping film145may include an oxide film.

Referring toFIG. 10, the capping film145is etched so that a capping film pattern145apartially exposing the second conductive material140ain the lower cylindrical electrode120b, is formed. The capping film pattern145amay be formed at any position where the second conductive material140aformed in the lower cylindrical electrode120b, can be exposed. According to certain embodiments, the center part of the second conductive material140aformed in the lower cylindrical electrode120bis exposed.

Referring toFIG. 11, a third conductive material140bis formed over the second conductive material140aand the capping film pattern145a. The third conductive material140bmay be formed of the same materials as those of the second conductive material140a. The third conductive material140bmay be formed of any one of a titanium (Ti) film, a titanium nitride (TiN) film, a ruthenium (Ru) film, and a combination thereof. In this case, the second conductive material140aexposed by the capping film pattern145ais coupled to the third conductive material140b, so that a top or upper electrode140is formed.

As is apparent from the above description, embodiments provide methods for manufacturing a semiconductor device to prevent a lower electrode from leaning in a dip-out process of an interlayer insulation film forming the lower electrode. In the corresponding semiconductor device, a conductive material of a lower electrode is used as a support layer, instead of a conventional nitride film support layer. This prevents a crack from being generated in a nitride film support layer.

The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.