TRANSMITTER AND SIGNAL TRANSMITTING METHOD THEREOF

The transmitter includes a serializer, a main driver and an auxiliary driver. The serializer sequentially outputs, according to a clock signal, a first signal and a second signal as two consecutive data of a first output signal, and detects whether the first signal and the second signal are the same so as to generate a control signal. The main driver generates a second output signal according to the first output signal. The auxiliary driver is selectively switched according to the control signal, wherein the main driver and the auxiliary driver are powered by the same supply voltage.

This application claims the benefit of China application Serial No. CN202310083879.X, filed on Jan. 30, 2023, the subject matter of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present application relates to a transmitter, and more particularly to a transmitter having a stable voltage mechanism and a signal transmitting method thereof.

Description of the Related Art

A transmitter may be used to transmit data to another device. According to different types of data to be transmitted, a transmitter may result in different current consumptions in different periods. For example, if the type of data to be transmitted is multiple consecutive different data values, internal circuits in the transmitter are constantly switched, resulting in a larger dynamic current. Alternatively, if the type of data to be transmitted is multiple consecutive same data values, internal circuits in the transmitter do not need to be switched, resulting in a more stable current. In the cases above, a power supplied to the transmitter needs to have a better adjustment capability and/or have a larger filter capacitor, so as to adapt to requirements of high-speed data transmissions. However, with the increase in data transmission rates, the bandwidth and adjustment capability of power supplies have become insufficient for supporting existing high-speed data transmission rates (for example, in the scale of GHz). On the other hand, if the capacitance value of a filter capacitor is increased, the overall area and cost of a chip may be overly increased, similarly leading to a decrease in the bandwidth of power supplies.

SUMMARY OF THE INVENTION

In some embodiments, it is an object of the present application to provide a transmitter having a stable voltage mechanism and a signal transmitting method thereof so as to improve the issues of the prior art.

In some embodiments, the transmitter includes a serializer, a main driver and an auxiliary driver. The serializer sequentially outputs, according to a clock signal, a first signal and a second signal as two consecutive data of a first output signal, and detects whether the first signal and the second signal are the same so as to generate a control signal. The main driver generates a second output signal according to the first output signal. The auxiliary driver is selectively switched according to the control signal, wherein the main driver and the auxiliary driver are powered by the same supply voltage.

In some embodiments, the signal transmitting method includes the following operations: sequentially outputting, according to a clock signal, a first signal and a second signal as two consecutive data of a first output signal, and detecting whether the first signal and the second signal are the same so as to generate a control signal; generating a second output signal according to the first output signal by a main driver; and selectively switching an auxiliary driver according to the control signal, wherein the main driver and the auxiliary driver are powered by the same supply voltage.

Features, implementations and effects of the present application are described in detail in preferred embodiments with the accompanying drawings below.

DETAILED DESCRIPTION OF THE INVENTION

All terms used in the literature have commonly recognized meanings. Definitions of the terms in commonly used dictionaries and examples discussed in the disclosure of the present application are merely exemplary, and are not to be construed as limitations to the scope or the meanings of the present application. Similarly, the present application is not limited to the embodiments enumerated in the description of the application.

The term “coupled” or “connected” used in the literature refers to two or multiple elements being directly and physically or electrically in contact with each other, or indirectly and physically or electrically in contact with each other, and may also refer to two or more elements operating or acting with each other. As given in the literature, the term “circuit” may be a device connected by at least one transistor and/or at least one active element by a predetermined means so as to process signals.

FIG.1shows a schematic diagram of a transmitter100according to some embodiments of the present application. In some embodiments, the transmitter100may be a transmitter for wired transmissions. The transmitter100includes a serializer110, a main driver120, an auxiliary driver125, a post-driver130, a power supply140and a power supply150. The power supply140operates as a core power supply, and may provide a supply voltage VDD3to the serializer110and a supply voltage VDD1to the main driver120and the auxiliary driver125so as to power these circuits. In some embodiments, the power supply VDD3and the power supply VDD1may be the same voltage; however, the present application is not limited to the example above. The power supply150operates as a power supply for an input/output interface, and may provide a supply voltage VDD2to the post-driver130so as to power the post-driver130.

The serializer110may sequentially output, according to a clock signal CLK, a signal S1and a signal S2as two consecutive data in an output signal SO1. In other words, the serializer110may convert two parallel signals (that is, the signal S1and the signal S2) into one series output (that is, the output signal SO1). The serializer110may further detect whether the signal S1and the signal S2are the same to generate a control signal SC.

In some embodiments, the main driver120and the auxiliary driver125may be identically structured pre-drivers. In some embodiments, the main driver120operates as a main transmission path which may be used to transmit the output signal SO1, and the auxiliary driver125operates as an auxiliary transmission path which may be used to stabilize the supply voltage VDD1. More specifically, the main driver120may be coupled to the serializer110to receive the output signal SO1and generate the output signal SO2according to the output signal SO1. The auxiliary driver125may be coupled to the serializer110to receive the control signal SC and be selectively switched according to the control signal SC. For example, if the serializer110determines that the signal S1and the signal S2are the same, the auxiliary driver125is switched according to the control signal SC. Alternatively, if the serializer110determines that the signal S1and the signal S2are different, the auxiliary driver125is not switched according to the control signal SC. With the configuration above, it is ensured that both of the main driver120and the auxiliary driver125may sink approximate currents from power supply140in any given time period, so that the supply voltage VDD1may be more stable. Related operation details are to be described with reference toFIG.2andFIG.3below. The post-driver130is coupled to the main driver120so as to receive the output signal SO2. The post-driver130may generate an output signal SO3according to the output signal SO2, and transmit the output signal SO3to other devices (not shown) via a cable105.

FIG.2shows a circuit schematic diagram of the serializer110, the main driver120and the auxiliary driver125inFIG.1according to some embodiments of the present application. The serializer110includes a data capture circuit211, a buffer circuit212, a multiplexer213and a detection circuit214. The data capture circuit211outputs the signal S1and the signal S2as data D1and data D2according to the clock signal CLK. In some embodiments, the data capture circuit211may include a D-flip-flop211A and a D-flip-flop211B. The D-flip-flop211A outputs the signal S1as the data D1according to the clock signal CLK. The D-flip-flop211B outputs the signal S2as the data D2according to the clock signal CLK.

The buffer circuit212temporarily stores the data D2as data D3according to the clock signal CLK. The buffer circuit212may be, for example but not limited to, a D-latch, which may temporarily store the data D2as the data D3according to the clock signal CLK. The detection circuit214may compare the data D1with the data D3(that is, the temporarily stored data D2) to determine whether the signal S1and the signal S2are the same so as to generate the control signal SC. As described above, the signal S1and the signal S2are output as two consecutive data in the output signal SO1. For example, the signal S1may be output as even-number data in the output signal SO1, and the signal S2may be output as odd-number data in the output signal SO1. To determine whether the signal S1and the signal S2are the same, the signal S2may be delayed by the buffer circuit212to align with the signal S1in terms of time (that is, the data D1may be aligned with the data D3). As such, the detection circuit214may compare the data D1with the data D2to determine whether two consecutive data in the output signal SO1are the same.

In some embodiments, the detection circuit214may include a comparator214A and a control signal generator214B. The comparator214A may compare the data D1with the data D3to generate a signal S3. In some embodiments, the comparator124A may be, for example but not limited to, an XNOR gate, which may perform the operation above to generate the signal S3. For example, if the data D1is the same as the data D3, the comparator214A may output the signal S3having a first logical value (for example, logic 1). Alternatively, if the data D1is different from the data D3, the comparator214A may output the signal S3having a second logical value (for example, logic 0). The control signal generator214B may generate the control signal SC according to the signal S3and the clock signal CLK. In some embodiments, the control signal generator214B may be, for example but not limited to, a NAND gate, which may perform the operation above to generate the control signal SC. For example, in response to the signal S3having a first logical value, the control signal generator214B may output the clock signal CLK as the control signal SC, such that the auxiliary driver125may be switched along with the clock signal CLK. Alternatively, in response to the signal S3having a second logical value, the control signal generator214B may output the control signal CS having a fixed logical value (for example, logic 1), such that the auxiliary driver125may stay not switched.

The multiplexer213may sequentially output, according to the clock signal CLK, the data D1and D3as two consecutive data of the output signal SO1. For example, when the clock signal CLK is at a first level, the multiplexer214outputs the data D1as even-number data of the output signal SO1. Alternatively, when the clock signal CLK is at a second level different from the first level, the multiplexer214outputs the data D3as odd-number data of the output signal SO1. In equivalence, multiple parallel signals S1and S2can be converted by the data capture circuit211and the multiplexer213into multiple consecutive data (that is, serialization) in the output signal SO1.

In this example, each of the main driver120and the auxiliary driver125may be an inverter circuit, which may be powered by the supply voltage VDD1. For example, each of the main driver120and the auxiliary driver125may be implemented by a P-type transistor and an N-type transistor set with the same size. As described above, the main driver120may generate the output signal SO2according to the output signal SO1, and transmit the output signal SO2to the post-driver130inFIG.1. In some embodiments, an output terminal of the auxiliary driver125is coupled to a capacitor C, and does not transmit signals to other circuits. When the data D1and the data D3are different (that is, the signal S1captured is different from the signal S2captured), the auxiliary driver125may stay not switched in response to the control signal SC, and the main driver120consecutively outputs different data (because the data D1and the data D3are two consecutive data in the output signal SO1) and is switched. In other words, in this case, the main driver120is switched and hence consumes a dynamic current.

On the other hand, when the data D1and the data D3are the same (that is, the signal S1captured is the same as the signal S2captured), the auxiliary driver125may be switched in response to the control signal SC, and the main driver120consecutively outputs the same data and is not switched. In other words, in this case, the auxiliary driver125is switched and hence consumes a dynamic current. Accordingly, in either of the cases above, the corresponding one of the main driver120and the auxiliary driver125is switched, such that the overall consumption of the main driver120and the auxiliary driver125consume substantially equal dynamic currents. Thus, current fluctuation resulted on the power supply140that provides the supply voltage VDD1inFIG.1is reduced, hence better stabilizing the power supply VDD1. In some embodiments, to ensure that the main driver120and the auxiliary driver125may generate substantially equal currents, the capacitance value of the capacitor C may be configured according to an input capacitance (for example, the input capacitor Cin inFIG.1) of the post-driver130. For example, the capacitance value of the capacitor C may be configured to be equal to the capacitance value of the input capacitor Cin of the post-driver130. Thus, the main driver120and the auxiliary driver125are made to generate even similar dynamic currents when being switched.

FIG.3shows a dynamic waveform schematic diagram of part of signals and/or dynamic currents consumed by part of the circuits inFIG.1and/orFIG.2according to some embodiments of the present application. As shown inFIG.3, the output signal SO1includes multiple data, which may be logic 0, logic 1, logic 0, logic 1, logic 0 and logic 1 in a period T1, and multiple logic 1 in a period T2. The multiple data above may sequentially be data values of the signal S1and the signal S2at different timings.

In the period T1, since two consecutive data of the output signal SO1are different from each other (that is, one logic 0 and one logic 1), it means that the main driver120is consecutively switched and hence generates multiple different data. As such, the main driver120results in a consumption of a dynamic current while the data are switched in the period T1. On the other hand, in this case, the auxiliary driver125stays not switched in response to the control signal SC and does not result in a consumption of a dynamic current (as the waveform302inFIG.3).

In the period T2, since the two consecutive data of the output signal SO1are the same (that is, both as logic 1), it means that the main driver120is continually not switched and outputs the same data. As such, the main driver120does not generated in a dynamic current in the period T2. On the other hand, in this case, the auxiliary driver125is switched in response to the control signal SC and generates a dynamic current (as the waveform302inFIG.3). As shown inFIG.3, since a substantially equal dynamic current is generated by a corresponding driver in both of the period T1and the period T2, fluctuation in the supply voltage VDD1in the period T1and the period T2appears quite moderate (as the waveform303inFIG.3).

In contrast, if the auxiliary driver125for resulting an equivalent dynamic current in the period T2is not provided, the supply voltage VDD1(as the waveform304in a dotted line inFIG.3) bears the consumption of a dynamic current in the period T1and the level thereof gradually reduces. In the period T2, since the main driver120is likewise not switched, the power supply140regulates the supply voltage VDD1and gradually restores the level of the power supply VDD1. By comparing the waveform303and the waveform304, it is known that the supply voltage VDD1has larger fluctuation due to high-speed data transmissions when the auxiliary driver125is not provided. In other words, with the auxiliary driver125provided, stability of the power supply VDD1is effectively enhanced and better suitability is provided for high-speed transmissions.

FIG.4shows a flowchart of a signal transmitting method400according to some embodiments of the present application. In operation S410, a first signal and a second signal are sequentially output, according to a clock signal, as two consecutive data of a first output signal, and it is detected whether the first signal and the second signal are the same so as to generate a control signal. In operation S420, a second output signal is generated according to the first output signal by a main driver. In operation S430, an auxiliary driver is selectively switched according to the control signal, wherein the main driver and the auxiliary driver are powered by the same supply voltage.

Details associated with the multiple operations of the signal transmitting method400above can be referred from the details of the embodiments above, and are omitted herein. The plurality operations of the signal transmitting method400above are merely examples, and are not limited to being performed in the order specified in these examples. Without departing from the operation means and ranges of the various embodiments of the present application, additions, replacements, substitutions or omissions may be made to the operations of the signal transmitting method400, or the operations may be performed in different orders (for example, simultaneously performed or partially simultaneously performed).

In conclusion, the transmitter and the signal transmitting method according to some embodiments of the present application are capable of improving stability of a supply voltage by using an auxiliary driver. Thus, the limitation caused by a regulation capability of a power supply is eliminated and a larger filter capacitor is not required, providing better suitability for applications related to high-speed transmission and reducing overall costs of chips.

While the present application has been described by way of example and in terms of the preferred embodiments, it is to be understood that the disclosure is not limited thereto. Various modifications made be made to the technical features of the present application by a person skilled in the art on the basis of the explicit or implicit disclosures of the present application. The scope of the appended claims of the present application therefore should be accorded with the broadest interpretation so as to encompass all such modifications.