Dense, nested arrangement of multiple peripheral component interconnect express (PCIe) cards within a thin server volume

An information handling system (IHS) server volume includes at least two pairs of flexible peripheral component interconnect express (PCIe) media for connecting data signals and power supply signals via riser cards mounted against respective PCIe devices in large adjacent physical slot locations. A first PCIe device corresponding to a first riser card and a second PCIe device corresponding to a second riser card are relatively positioned to enable the second riser card to be fitted within a specified space between the first PCIe device and the first riser card while a footprint of a first PCIe connector corresponding to the first PCIe device overlaps a footprint of a second PCIe connector corresponding to the second PCIe device. First and second PCIe cards provided by the first and second PCIe devices respectively are inserted into respective PCIe connectors via the first pair of riser cards having a dense nested arrangement.

BACKGROUND

1. Technical Field

The present disclosure generally relates to information handling systems (IHS) and in particular to design and configuration of interface systems within information handling systems.

2. Description of the Related Art

Large scale IHSes are often designed using a 1 U or thin server volume to support the various requirements of the various IT gear included within the IHS. However, in a 1 U or thin server volume, standard Peripheral Component Interconnect (PCI) cards can quickly fill the available volume. In fact, the unusual shape of standard PCI brackets results in wasted space in a 1 U/thin server application. More specifically, as a result of a desire for balancing four (4) graphics processing unit (GPU) cards with 2 processors, fitting 4× Double Wide PCI cards is desired across a 1 U/thin 19″ standard server bulkhead. However, no more than 3×DW, Full PCI can fit within 1 U server volume, using standard mounting and connecting methods.

In a conventional system, the available space is used up as a result of the conventional designs of: the PCI bracket; the edge connection on interface cards; and the riser. As a result of one or more of these conventional design features associated with PCI brackets and/or PCI systems, Low Profile (LP) or Singlewide card applications which utilize some similar design features are presented with similar challenges.

BRIEF SUMMARY

Disclosed are a method and an information handling system (IHS) for providing dense and nested peripheral component interconnect express (PCIe) mounting within the IHS configured as a 1 U or thin server volume. According to one aspect, the server volume includes at least two pairs of flexible PCIe media for connecting data signals and power supply signals via riser cards mounted against respective PCIe devices in large adjacent physical slot locations. A first PCIe device corresponding to a first riser card and a second PCIe device corresponding to a second riser card are relatively positioned to enable the second riser card to be fitted within a specified space between the first PCIe device and the first riser card while a footprint of a first PCIe connector corresponding to the first PCIe device overlaps a footprint of a second PCIe connector corresponding to the second PCIe device. First and second PCIe cards provided by the first and second PCIe devices respectively are inserted into respective PCIe connectors via the first pair of riser cards having a dense nested arrangement. Similarly, third and fourth PCIe devices positioned in physical slot locations adjacent to the slot locations for the first and second PCIe devices are connected using a second pair of nested riser cards.

DETAILED DESCRIPTION

The illustrative embodiments provide a method and an information handling system (IHS) for providing a dense and nested peripheral component interconnect express (PCIe) mounting within the IHS utilizing a 1 U or thin server volume. Disclosed are a method and an information handling system (IHS) for providing dense and nested peripheral component interconnect express (PCIe) mounting within the IHS configured as a 1 U or thin server volume. According to one aspect, the server volume includes at least two pairs of flexible PCIe media for connecting data signals and power supply signals via riser cards mounted against respective PCIe devices in large adjacent physical slot locations. A first PCIe device corresponding to a first riser card and a second PCIe device corresponding to a second riser card are relatively positioned to enable the second riser card to be fitted within a specified space between the first PCIe device and the first riser card while a footprint of a first PCIe connector corresponding to the first PCIe device overlaps a footprint of a second PCIe connector corresponding to the second PCIe device. First and second PCIe cards provided by the first and second PCIe devices respectively are inserted into respective PCIe connectors via the first pair of riser cards having a dense nested arrangement. Similarly, third and fourth PCIe devices positioned in physical slot locations adjacent to the slot locations for the first and second PCIe devices are connected using a second pair of nested riser cards.

Those of ordinary skill in the art will appreciate that the hardware, firmware/software utility, and software components and basic configuration thereof depicted in the following figures may vary. For example, the illustrative components of IHS100(FIG. 1) are not intended to be exhaustive, but rather are representative to highlight some of the components that are utilized to implement certain of the described embodiments. For example, different configurations of an IHS may be provided, containing other devices/components, which may be used in addition to or in place of the hardware depicted, and may be differently configured. The depicted example is not meant to imply architectural or other limitations with respect to the presently described embodiments and/or the general invention.

FIG. 1illustrates a block diagram representation of an example information handling system (IHS)100, within which one or more of the described features of the various embodiments of the disclosure can be implemented. For purposes of this disclosure, an information handling system, such as IHS100, may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes. For example, an information handling system may be a handheld device, personal computer, a server, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory. Additional components of the information handling system may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communications between the various hardware components.

Referring specifically toFIG. 1, there is illustrated a block diagram representation of a rack-based IHS100having multiple IT gear150inserted therein. Example IT gear101, which can be individually considered a server IHS and/or a 1 U server IHS, includes one or more processor(s)102coupled to system memory106via system interconnect104. System interconnect104can be interchangeably referred to as a system bus, in one or more embodiments. Also coupled to system interconnect104is storage134within which can be stored one or more software and/or firmware modules and/or data (not specifically shown). In one embodiment, storage134can be a hard drive or a solid state drive. The one or more software and/or firmware modules within storage134can be loaded into system memory106during operation of IHS100. As shown, system memory106can include therein a plurality of modules, including Basic Input/Output System (BIOS)110, operating system (O/S)108, applications112and firmware (not shown). The various software and/or firmware modules have varying functionality when their corresponding program code is executed by processor(s)102or other processing devices within IT gear101. As illustrated, IT gear101is located/placed within a larger structure of IHS100(generally illustrated inFIG. 1as a surrounding exterior line, with specific structural details provided inFIGS. 2-10).

In one or more embodiments, BIOS110comprises additional functionality associated with unified extensible firmware interface (UEFI), and can be more completely referred to as BIOS/UEFI110in these embodiments. The various software and/or firmware modules have varying functionality when their corresponding program code is executed by processor(s)102or other processing devices within IT gear101.

IT gear101further includes one or more input/output (I/O) controllers120which support connection to and processing of signals from one or more connected input device(s)122, such as a keyboard, mouse, touch screen, or microphone. I/O controllers120also support connection to and forwarding of output signals to one or more connected output device(s)124, such as a monitor or display device or audio speaker(s). In addition, IT gear101includes universal serial bus (USB)126which is coupled to I/O controller120. In one embodiment, IT gear101represents a peripheral component interconnect express (PCIe) device and includes PCIe module138which is coupled to I/O controller120. Additionally, in one or more embodiments, one or more device interface(s)128, such as an optical reader, a universal serial bus (USB), a card reader, Personal Computer Memory Card International Association (PCMCIA) port, and/or a high-definition multimedia interface (HDMI), can be associated with IT gear101. Device interface(s)128can be utilized to enable data to be read from or stored to corresponding removable storage device(s)130, such as a compact disk (CD), digital video disk (DVD), flash drive, or flash memory card. In one or more embodiments, device interface(s)128can also provide an integration point for connecting other device(s) to IT gear101. In one implementation, IT gear101connects to remote IHS140using device interface(s)128. In such implementation, device interface(s)128can further include General Purpose I/O interfaces such as I2C, SMBus, and peripheral component interconnect express (PCIe) buses.

IT gear101comprises a network interface device (NID)132. NID132enables IHS100to communicate and/or interface with other devices, services, and components that are located external to IT gear101. These devices, services, and components can interface with IHS100via an external network, such as example network136, using one or more communication protocols. In particular, in one implementation, IHS100uses NID132to connect to remote IHS140via an external network136.

Network136can be a wired local area network, a wireless wide area network, wireless personal area network, wireless local area network, and the like, and the connection to and/or between network136and IHS100can be wired or wireless or a combination thereof. For purposes of discussion, network136is indicated as a single collective component for simplicity. However, it is appreciated that network136can comprise one or more direct connections to other devices as well as a more complex set of interconnections as can exist within a wide area network, such as the Internet.

With specific reference now toFIG. 2, there is depicted an example 1 U server volume which includes two CPUs directly coupled via Peripheral Component Interconnect Express (PCIe) links to four (4) large adjacent physical slots for information technology (IT) gear, such as PCIe devices. The PCIe devices include respective PCIe cards, which can be graphics processing units (GPUs), according to one embodiment. Server volume200represents a 1 U server volume which includes a system board/motherboard (not shown). The server volume is divided into a plurality of spaces sized according to requirements of corresponding, inserted electronic components and designed to support various mechanical and cooling attributes. For example, the four (4) large IT gear are located in a first 1 U space which includes and/or is divided into four large physical slots into which the IT gear are inserted, respectively.

Server volume200further comprises first central processing unit (CPU)202and second CPU (CPU2)222. First CPU202is coupled via first high bandwidth port “Port A X16 Link”204and second high bandwidth port “Port B X16 Link”206, using first and second flexible PCIe media210and220, to first electronic components (not shown) in first large “Physical Slot 1”214and second large “Physical Slot 2”216, respectively. An example of the first electronic component used on this PCIe bus is a PCIe device which provides a PCIe card such as a graphics processing unit (GPU). In addition, first CPU202is coupled via first lower bandwidth port “Port C X8 Link”208to a second electronic component (not shown), such as an I/O card and/or a communication card, in first smaller Input/Output (I/O) “Physical Slot 3”212. Similarly, second CPU222is coupled via third high bandwidth port “Port A X16 Link”224and fourth high bandwidth port “Port B X16 Link”226, using third and fourth flexible PCIe media238and240, to third electronic components (not shown) in third large “Physical Slot 4”232and fourth large “Physical Slot 5”234, respectively. In addition, second CPU222is coupled via second lower bandwidth port “Port C X8 Link”228to fourth electronic component (not shown), such as an I/O card and/or a communication card, in second Input/Output (I/O) “Physical Slot 3”230.

As described, server volume200includes four large physical slots in adjacent positions enabling four electronic components to be respectively inserted into the four large physical slots and to be coupled via PCIe to a corresponding CPU. In particular, CPU ports are connected to corresponding physical slot location via PCIe lanes. The PCIe lanes are routed out of a corresponding CPU to a corresponding large physical slot within the 1 U server volume using flexible signal cable routing (e.g., flexible PCIe media210,220,238,240). The flexible signal cable routing is coupled to a first riser card (not shown). The first riser card and a second riser card coupled to another PCIe link are physically arranged adjacent to each other in a joint and nested configuration within a first narrow sub-slot (e.g., sub-slot218) between adjacent physical slot locations (e.g., first large “Physical Slot 1”214and second large “Physical Slot 2”216) corresponding to the first and second IT gear, respectively, to provide a first nested pair/assembly of adjacent riser cards. Similarly, a third riser card and a fourth riser card coupled to respective PCIe links are physically arranged adjacent to each other in a joint and nested configuration within a second narrow sub-slot (e.g., sub-slot236) between adjacent physical slot locations (e.g., third large “Physical Slot 4”232and fourth large “Physical Slot 5”234) corresponding to a third and fourth IT gear, respectively, to provide a second nested pair/assembly of adjacent riser cards. The nested configuration of adjacent riser cards is further described within the following figures.

Although the disclosure is specifically described with reference to PCIe connectivity, through the use of terms such as ‘PCIe media’, ‘PCIe links’, ‘PCIe connectors’ and ‘PCIe cards’, other standards, including (conventional) PCI, for connecting selected hardware components and/or peripheral components can be utilized. In addition, more general terminology associated with other peripheral standards (i.e., in addition to ‘PCIe’) such as the term ‘peripheral’ can be substituted for ‘PCIe’ and/or can be utilized as well to cover those use cases that include these other peripheral devices or peripheral interconnects. For example, although the term ‘PCIe card’ is frequently utilized within the disclosure, a more general term such as ‘peripheral card’ can also apply.

FIG. 3illustrates an example 1 U server volume which includes two CPUs directly coupled via Peripheral Component Interconnect Express (PCIe) links to four (4) adjacent PCIe devices providing PCIe cards, e.g., graphics processing units (GPUs), in corresponding large physical slots, according to one embodiment. Server volume300comprises first central processing unit (CPU1)202and second CPU (CPU2)222. First CPU202is coupled via first high bandwidth “X16” link210and second high bandwidth “X16” link220to PCIe devices304and308, in first large “Physical Slot 1”214(FIG. 2) and second large “Physical Slot 2”216(FIG. 2), respectively. In addition, first CPU202is coupled via first lower bandwidth “X8” link312to an electronic component (not shown), such as an I/O card and/or a communication card, in first smaller, low profile “LP slot #1”306. Similarly, second CPU222is coupled via third high bandwidth “X16” link238and fourth high bandwidth “X16” link240to PCIe devices324and328, in third large “Physical Slot 4”232(FIG. 2) and fourth large “Physical Slot 5”234(FIG. 2), respectively. In addition, second CPU222is coupled via second lower bandwidth “X8” link326to an electronic component (not shown), such as an I/O card and/or a communication card, in second, smaller, low profile “LP slot #2”330.

The CPU ports are coupled to PCIe devices/components such as PCIe devices304,308,324and328, for example, positioned in a large physical slot location using a flexible peripheral component interconnect express (PCIe) media. Each of the PCIe devices/components provides a corresponding PCIe card. The flexible PCIe media includes: (i) a cable for connecting data signals and power supply signals to a specific physical slot; and (ii) a riser card (not shown) having a PCIe connector which is electrically coupled to the cable and which provides signal breakout to a standard connector. The flexible PCIe media is coupled to a mechanical mounting bracket to enable the flexible PCIe media to be positioned within a specified slot or sub-slot and be supported against a respective PCIe device. The riser card provides the data and power signals to the IT gear. For example, the riser card carries an x16 PCIe bus and 75 W of power.

FIG. 4illustrates an example 1 U server volume which includes two CPUs switchably coupled via Peripheral Component Interconnect Express (PCIe) links to four (4) adjacent PCIe devices providing PCIe cards, e.g., GPUs, in corresponding large physical slots, according to one embodiment. Server volume400comprises first central processing unit (CPU1)402and second CPU (CPU2)422. First CPU402is coupled via first high bandwidth “X16” link404to each of PCIe devices416,418,420and424via PCI Express (PCIe) switch414. In addition, first CPU402is coupled via second higher bandwidth “X16” link406to first smaller, low profile “LP slot #1”408. Additionally, first CPU402is coupled via first lower bandwidth “X8” link410to second smaller, low profile “LP slot #2”412. In one embodiment, second CPU422is similarly connected to other components using switchable PCIe links. However, in another embodiment, second CPU422is directly connected to the other components.

FIG. 5illustrates an example 1 U server volume which includes two CPUs coupled via Peripheral Component Interconnect Express (PCIe) links to four (4) adjacent PCIe devices, according to one embodiment. Server volume500comprises first CPU202and second CPU222. In addition, server volume500comprises first PCIe device304, second PCIe device308, third PCIe device324and fourth PCIe device328, which are coupled via PCIe links210,220,238and240to first CPU202and second CPU222, respectively. The PCIe links, such as first and second PCIe links210and220, are provided using flexible signal cable routing that connects a respective CPU to a desired physical slot location, such as a slot location utilized by a pair of target PCIe devices (e.g., first PCIe device304and second PCIe device308). The flexible signal cable routing is also referred to as flexible PCIe media herein. Server volume500also comprises first nested pair of riser cards504and second nested pair of riser cards510.

First PCIe flexible media210provides and/or is coupled to a first riser card corresponding to a first PCIe device304while second flexible media220provides a second riser card corresponding to a second PCIe device308that is adjacent to the first PCI device304. The first and second PCIe devices304,308are physically arranged adjacent to each other in a joint and nested configuration within a narrow, first sub-slot (e.g., sub-slot218inFIG. 2) between adjacent physical slot locations corresponding to first and second PCIe devices304,308, respectively, to provide a first nested pair/assembly of adjacent riser cards504.

As described, the first and second PCIe links are routed between the first and second PCIe devices and are coupled to first and second riser cards, respectively, which are arranged as a first nested pair of adjacent riser cards504. The first and second PCIe links respectively connect data signals and power signals to the first and second riser cards. The nested configuration of adjacent riser cards is further described usingFIG. 6.

FIG. 6illustrates a section of flexible PCIe media-riser assembly including a first riser card, according to one embodiment. First PCIe media-riser assembly600comprises first flexible PCIe media606and first riser card604coupled to first flexible PCIe media606. First riser card604includes first PCIe connector602. A second PCIe media-riser assembly (not shown) provides a second riser card which is designed so that the geometry and connector locations enable the second riser card to be positioned adjacent to the first riser card and oriented to provide the first nested pair of adjacent riser cards. The second riser card is substantially identically designed and configured similarly to first riser card604. Furthermore, third and fourth flexible PCIe media respectively provide a third riser card and a fourth riser card that are electrically coupled to third and fourth PCIe devices324,328, respectively, which provide a second pair of adjacent PCIe devices. The third and fourth riser cards are substantially identically designed and configured comparable to a design and configuration of first riser card604.

FIG. 7illustrates a server volume700having a section of flexible PCIe media including a first riser card, and a PCIe device against which the flexible PCIe media is mounted, according to one embodiment. Server volume700comprises first PCIe card702and a PCIe media-riser assembly, which includes flexible PCIe media704and riser card706. Riser card706is physically coupled to first PCIe card702. In addition, server volume700comprises mechanical mounting bracket710to which riser card706is physically coupled. Also illustrated within server volume700are horizontal space712located between the riser (e.g., first riser706) and an exterior casing of first PCIe device702, and vertical height714of a connector (affixed) section of riser card706. Vertical height714is specifically determined to enable the second PCIe connector on second riser to fit into horizontal space712, when identically designed riser cards are being nested against paired PCIe devices.

Mechanical mounting bracket710has mounting flanges that can be affixed to a chassis to secure an electronic device such as PCIe card702within a slot position without the mounting flanges extending beyond the chassis volume or the PCIe device volume. Unlike standard PCIe mounting brackets of conventional systems, mechanical mounting bracket710of server volume700provides mounting points708, by which riser card706is coupled to mounting bracket710. Mounting points708are located substantially within a corresponding nested volume and/or PCIe device and media-riser card assembly volume. Mechanical mounting bracket710enables a secure physical connection to be maintained between PCIe card706and the PCIe media-riser card assembly.

FIG. 8illustrates a pair of PCIe devices which are oriented and positioned to provide a pair of adjacent PCIe devices and a nested pair of riser cards, according to one embodiment. Server volume800comprises first PCIe device702and second PCIe device704which, in one embodiment, has a substantially identical exterior physical extent compared to first PCIe device702. Server volume800also comprises first riser card706corresponding to first PCIe device702, and second riser card810corresponding to second PCIe device704. First orientation arrow804, second orientation arrow806and third orientation arrow808collectively indicate how the PCIe devices are moved and/or positioned relative to each other to provide the pair of adjacent PCIe devices and the nested pair of riser cards (e.g., nested pair of adjacent riser cards504ofFIG. 5).

First orientation arrow804indicates that second PCIe device704is substantially rotated 180 degrees in a counter clockwise direction from a first orientation that is substantially identical to a current illustrated orientation of first PCIe device702to provide the current and second illustrated orientation of second PCIe device704. Second orientation arrow806indicates that, following the rotation of 180 degrees, second PCIe device704is moved to an adjacent position beside first PCIe device702, which enables an outer side of second riser card810of second PCIe device704to fit proximate to an exterior surface of first PCIe device702. While second riser card810of second PCIe device704is being positioned proximate to an exterior surface of first PCIe device702, an outer side of first riser card706of first PCIe device702is simultaneously being positioned proximate to an exterior surface of second PCIe device704while a first/inner side of the first riser card to be positioned facing a first/inner side of the second riser card, as indicated by third orientation arrow808. Thus, the outer side of first riser card706is closely constrained by second PCIe device704of the pair of adjacent PCIe devices. Similarly, the outer side of second riser card810is closely constrained by first PCIe device702of the pair of adjacent PCIe devices. Furthermore, the relative positioning of the PCIe devices as indicated by the orientation arrows enables second riser card810to be fitted within a specified space712that, by design, exists between first PCIe device702and first riser card706to provide a higher density nested volume of adjacent riser cards. The close constraints drive design requirements and specifications for contour/outline dimensions of the riser cards, and an allowable height of the PCIe flexible media.

FIG. 9illustrates a cross-section of an adjacent pair of PCIe devices, each providing a PCIe card, such as a GPU, inserted into PCIe connectors of a pair of nested riser cards, respectively, according to one embodiment. View900comprises first PCIe device304and second PCIe device308. In addition, view900includes first PCIe connector602and first PCIe card edge904(of first PCIe device304) inserted into first PCIe connector602. View900also shows second PCIe connector906and second PCIe card edge908inserted into second PCIe connector906. First PCIe connector602is coupled to first riser card604, and, similarly, second PCIe connector906is coupled to second riser card (not explicitly shown).

The first and second riser cards are substantially identically constructed and each PCIe connector of a riser card is located on a first/inner side of the respective riser card. However, in order to enable the first and second riser cards to be properly fitted within the first sub-slot to provide PCIe connectivity to respective IT gear, the first and second riser cards are positioned adjacent to each other in a specific orientation. In particular, as described using the illustration ofFIG. 8, the second riser card is rotated and/or oriented to enable the first side of the first riser card to be positioned facing the first side of the second riser card. As a result, first PCIe connector602is located proximate to a lower perimeter of a corresponding joint riser volume while second PCIe connector906is located proximate to an upper perimeter of the joint riser volume. In addition, a footprint of second PCIe connector906overlaps a footprint of first PCIe connector602.

The first nested pair of riser cards (504ofFIG. 5) are arranged to enable (i) first PCIe card edge604coupled to first PCIe device304to be inserted into first PCIe connector602of the first riser card and to extend horizontally below and beyond the second riser card and (ii) a second PCIe card edge908coupled to second PCIe device308to be inserted into second PCIe connector906of the second riser card and to extend horizontally above and beyond the first riser card.

In addition, the nesting of PCIe devices304,308allows the PCIe connectors906and602to be stacked in a vertical space one above the other (i.e., within a same vertical plane but different horizontal planes). Unlike conventional designs and configurations which do not position the adjacent connectors in a vertical stack (i.e., the adjacent connectors are placed in different vertical places and a substantially identical horizontal plane), the first and second riser cards are designed and secured against respective PCIe devices to provide a nested riser volume having a higher density than a lower density of a total/combined riser space allocated, within conventional systems, to two riser cards. The lower density space of conventional systems forces PCI devices to be positioned farther apart than the more closely positioned PCIe devices of the disclosed system.

FIG. 10illustrates a bird's eye view of a pair of nested riser cards located between adjacent PCIe devices, according to one embodiment. View1000comprises first PCIe device1002and second PCIe device1004. In addition, view1000comprises nested volume portion1006which further comprises first riser card706corresponding to first PCIe device1002and second riser card1008corresponding to second PCIe device1004. View1000illustrates that a size of a riser card (e.g., first riser card706) and a spacing between the riser card (e.g., first riser card706) and an exterior casing of first PCIe device1002is specifically determined to enable the identically designed riser cards to fit within the physical constraints of being nested against paired PCIe devices.

Within the nested volume, which includes nested volume portion1006, a first flexible PCIe media and a second flexible PCIe media respectively provide data signals and power signals to first and second riser cards, which are positioned adjacent to each other and are arranged as a nested pair of riser cards.

FIG. 11presents a flowchart illustrating an example method for providing dense and nested PCIe mounting within IHS100according to one or more embodiments of the disclosure. The description of the method is provided with general reference to the specific components illustrated within the preceding figures. It is appreciated that certain aspects of the described methods may be implemented via a manufacturing process that involves use of one or more processing devices and/or execution of other code/firmware. In the discussion ofFIG. 11, reference is also made to elements described inFIGS. 1-10.

Method1100begins at the start block and proceeds to block1102at which a designer/manufacturer routes first flexible peripheral links coupled to high bandwidth ports of first CPU to first sub-slot between first and second adjacent peripheral devices. In addition, the manufacturer routes second flexible peripheral links coupled to high bandwidth ports of second CPU to second sub-slot between third and fourth adjacent peripheral devices (block1104). The manufacturer couples first flexible peripheral links to first and second riser cards (block1106). Additionally, the manufacturer couples second flexible peripheral links to third and fourth riser cards (block1108). The manufacturer physically secures each riser card to a respective peripheral device using a mechanical mounting bracket (block1110). The manufacturer arranges riser cards within first and second nested configurations (block1112). The manufacturer secures peripheral cards to a rack chassis using mechanical mounting brackets (block1114). The process concludes at the end block.

In the above described flow chart, aspects of the method may be embodied in a computer readable device containing computer readable code such that a series of functional processes are performed when the computer readable code is executed on a computing device. In some implementations, certain steps of the method are combined, performed simultaneously or in a different order, or perhaps omitted, without deviating from the scope of the disclosure. Thus, while the method blocks are described and illustrated in a particular sequence, use of a specific sequence of functional processes represented by the blocks is not meant to imply any limitations on the disclosure. Changes may be made with regards to the sequence of processes without departing from the scope of the present disclosure. Use of a particular sequence is therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.