Semiconductor device and DC-to-DC converter

In general, according to one embodiment, a semiconductor device includes a device main body, a semiconductor substrate. The device main body includes a semiconductor substrate mounting part and a first conductor provided around the semiconductor substrate mounting part. The semiconductor substrate includes a DC-to-DC converter control circuit having a detector to detect at least one of a current flowing through the first conductor and a voltage supplied to the first conductor. The semiconductor substrate is disposed on the semiconductor substrate mounting part so that the detector comes close to the first conductor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2009-295981, filed on Dec. 25, 2009; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device and DC-to-DC converter.

BACKGROUND

Switching circuits having switch elements, such as a DC-to-DC converter, for example, have been employing a higher and higher switching frequency to meet the demand for fast response to load change. Further, a parasitic capacitance of a switch element which drives an inductor has been increased with the increase in output current.

In such a switching circuit, ringing tends to occur at both rising and falling edges where an output current or an output voltage changes. Therefore, a usable switching frequency is limited by the time when the ringing converges, and is thus limited by a parasitic capacitance and a parasitic inductance of wiring or the like.

Generally, a semiconductor chip provided with such a switching circuit is mounted and packaged on a lead frame. The semiconductor chip is mounted in the center of the lead frame regardless of the chip size. Further, there is also known a chip-stacked semiconductor device having multiple semiconductor chips stacked and mounted on a substrate to reduce the substrate area. In the case of a semiconductor device of this type in which first and second semiconductor chips are stacked on the substrate, the first semiconductor chip is disposed with a virtual central axis of the first semiconductor offset from the center of the substrate (for example, refer to JP-A 2005-26564 (Kokai)).

However, the package structure as described above has difficulty in reducing the parasitic inductance and the like, and is limited in increasing the usable switching frequency.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device includes a device main body, a semiconductor substrate. The device main body includes a semiconductor substrate mounting part and a first conductor provided around the semiconductor substrate mounting part. The semiconductor substrate includes a DC-to-DC converter control circuit having a detector to detect at least one of a current flowing through the first conductor and a voltage supplied to the first conductor. The semiconductor substrate is disposed on the semiconductor substrate mounting part so that the detector comes close to the first conductor.

With reference to the drawings, embodiments are described in detail below. The drawings are schematic and conceptual; and shapes of respective portions, relationships between horizontal and vertical dimensions thereof, the proportions of sizes among portions, and the like are not necessarily the same as the actual values thereof. Further, the dimensions and proportions may be illustrated differently among drawings, even for identical portions. In the specification of this application and drawings, components similar to those described previously with reference to earlier drawings are marked with like reference numerals, and a detailed description is omitted as appropriate.

FIG. 1is a schematic plan view illustrating a configuration of a semiconductor device according to the embodiment.

As shown inFIG. 1, a semiconductor device1includes a semiconductor substrate2and a device main body3.

On the semiconductor substrate2, a DC-to-DC converter control circuit30is provided. The DC-to-DC converter control circuit30has a detector16. The semiconductor substrate2has four sides.

On the semiconductor substrate2, a terminal BOOT, a power supply terminal VIN, a first terminal LX, and a ground terminal GND are provided on a first side5. Terminals VFB, COMP, EN and SS are provided on the opposite side to the first side5. The power supply terminal VIN, the first terminal LX and the ground terminal GND are connected to the detector16. The terminals BOOT, VFB, COMP, EN and SS are connected to the DC-to-DC converter control circuit30.

The device main body3includes: a semiconductor substrate mounting part4for mounting the semiconductor substrate2; and first conductors K2to K4and second conductors K1and K5to K8, which are provided around the semiconductor substrate mounting part4. The first and second conductors K1to K8have multiple pins P1to P8, wires H1, first wires H2to H4, and wires H5to H8.

The pins P2to P4of the first conductors K2to K4are portions through which at least one of a current and a voltage is supplied to the first conductors K2to K4from the opposite side to the semiconductor substrate2. Moreover, the pins P1and P5to P8of the second conductors K1and K5to K8are portions through which a signal is inputted to or outputted from the second conductors K1and K5to K8from the opposite side to the semiconductor substrate2.

A virtual center line DL of the semiconductor substrate2is disposed to be offset to the first side5by an offset amount DW with respect to a virtual center line IL of the semiconductor substrate mounting part4. Note thatFIG. 1illustrates the configuration in which the device main body3has the first and second conductors K1to K8on both sides of the semiconductor substrate mounting part4. However, first and second electrodes may be provided around the semiconductor substrate mounting part4.

The terminal BOOT and the pin P1are connected by the wire H1. The pin P1and the wire H1make up the second conductor K1. The terminal BOOT serves as a connection part between the second conductor K1and the semiconductor substrate2.

The power supply terminal VIN and the pin P2are connected by the first wire H2. The pin P2and the first wire H2make up the first conductor K2. The power supply terminal VIN serves as a connection part between the first conductor K2and the semiconductor substrate2. The first terminal LX and the pin P3are connected by the second wire H3. The pin P3and the second wire H3make up the first conductor K3. The first terminal LX serves as a connection part between the first conductor K3and the semiconductor substrate2. The ground terminal GND and the pin P4are connected by the third wire H4. The pin P4and the third wire H4make up the first conductor K4. The ground terminal GND serves as a connection part between the first conductor K4and the semiconductor substrate2.

The terminal VFB and the pin P5are connected by the wire H5. The pin P5and the wire H5make up the second conductor K5. The terminal COMP and the pin P6are connected by the wire H6. The pin P6and the wire H6make up the second conductor K6. The terminal EN and the pin P7are connected by the wire H7. The pin P7and the wire H7make up the second conductor K7. The terminal SS and the pin P8are connected by the wire H8. The pin P8and the wire H8make up the second conductor K8.

The first wires H2to H4and the wires H1and H5to H8are made of, for example, bonding wires, metal sheets or the like.

As described above, the virtual center line DL of the semiconductor substrate2is disposed to be offset to the first side5with respect to the virtual center line IL of the semiconductor substrate mounting part4. Thus, the wire H1and the first to third wires H2to H4are shorter than the wires H5to H8.

In other words, the semiconductor substrate2is disposed on the semiconductor substrate mounting part4so that the detector16comes close to the first conductors K2to K4. Accordingly, the first conductors K2to K4are shorter than they are when the semiconductor substrate2is disposed in the center of the semiconductor substrate mounting part4.

Moreover, the semiconductor substrate2is disposed on the semiconductor substrate mounting part4so that the detector16comes closer to the first conductors K2to K4than to the second conductors K5to K8.

Note thatFIG. 1shows a state of the semiconductor device1during assembly thereof, in which the pins P1to P8are connected to each other. When the semiconductor device1is used after completion of the assembly thereof, connections among the pins P1to P8are cut off.

FIG. 2is a circuit diagram illustrating a DC-to-DC converter including the semiconductor device shown inFIG. 1.

As shown inFIG. 2, a DC-to-DC converter6includes the semiconductor device1, a first inductor7, a first capacitor8, a feedback circuit9and capacitors11to13.

One end of the first inductor7is connected to the pin P3of the semiconductor device1and connected to the first terminal LX through the second wire H3. In other words, the one end of the first inductor7is connected to an output of the DC-to-DC converter control circuit30through the first conductor K3.

Between the other end of the first inductor7and the ground, the first capacitor8and the feedback circuit9are connected in parallel. Further, a load circuit10is connected between the other end of the first inductor7and the ground, and an output voltage Vout is outputted to the load circuit10. The feedback circuit9has a voltage-dividing resistor and feeds back a voltage obtained by dividing the output voltage Vout to the second conductor K5, i.e. the pin P5of the semiconductor device1. Note that while the voltage obtained by dividing the output voltage Vout is fed back to the pin P5inFIG. 2, the output voltage Vout may be fed back to the pin P5.

The capacitor11is connected between the second and first conductors K1and K3of the semiconductor device1, i.e. between the pins P1and P3thereof. The capacitor12is connected between the second conductor K6, i.e. the pin P6of the semiconductor device1and the ground. The capacitor13is connected between the second conductor K8, i.e. the pin P8of the semiconductor device1and the ground. Moreover, a power-supply voltage is supplied to the first conductor K2, i.e. the pin P2of the semiconductor device1, and the first conductor K4, i.e. the pin P4of the semiconductor device1is connected to the ground. Further, a capacitor23is connected as a bypass capacitor between the pin P2and the ground, and the pin P2is connected to the ground in respect of alternating currents. An enable signal is inputted to the second conductor K7, i.e. the pin P7of the semiconductor device1. Functions of the respective pins P1to P8of the semiconductor device1are described later.

The DC-to-DC converter6steps down the power-supply voltage supplied to the semiconductor device1to the output voltage Vout.

The DC-to-DC converter control circuit30further includes a first switch element Q1, a second switch element Q2and a controller14, which are provided on the semiconductor substrate2.

The first switch element Q1has one end connected to the power supply terminal VIN and the other end connected to the first terminal LX. The second switch element Q2has one end connected to the first terminal LX and the other end connected to the ground terminal GND.

As described above, the power supply terminal VIN, the first terminal LX and the ground terminal GND are connected to the first conductors K2to K4, respectively, i.e. connected to the pins P2to P4in the device main body3, respectively, through the first to third wires H2to H4. These first to third wires H2to H4are electrically equivalent to a parasitic inductance. Note that cross-sectional areas of the pins P2to P4are much larger than those of the first to third wires H2to H4, and inductances of the pins P2to P4are much smaller than those of the first to third wires H2to H4. Therefore, inductances of the first conductors K2to K4are approximately equal to those of the first to third wires H2to H4. The same goes for the second conductors K1and K5to K8.

The pins P2and P4are connected to an external power supply and the ground, respectively, and the power-supply voltage is supplied between the pins P2and P4as described above.

The first and second switch elements Q1and Q2are controlled between ON and OFF states by the controller14, respectively. When the first switch element Q1is in the ON state and the second switch element Q2is in the OFF state, the first terminal LX is connected electrically to the power supply terminal VIN. On the other hand, when the first switch element Q1is in the OFF state and the second switch element Q2is in the ON state, the first terminal LX is connected electrically to the ground terminal GND.

The controller14includes a driver15, the detector16, a voltage generator17, an error amplifier18, a comparator19and a current generator20.

The driver15drives the first and second switch elements Q1and Q2between the ON and OFF states so that the voltage fed back to the terminal VFB, i.e. the output voltage Vout becomes constant. The detector16is a current detector which is connected to the power supply terminal VIN, the first terminal LX and the ground terminal GND, and detects, through the first conductors K2to K4, a current flowing through the first switch element Q1. The detector16detects an output current of the DC-to-DC converter control circuit30by detecting the current flowing through the first switch element Q1. The detector16includes a detecting transistor, a resistor and a differential amplifier.

The voltage generator17is a circuit for generating a reference voltage, and is set according to the output voltage Vout. The error amplifier18amplifies an error between the voltage inputted to the terminal VFB and the reference voltage generated by the voltage generator17. The error amplifier18is connected to the terminal COMP and connected to the pin P6through the wire H6. Further, the capacitor12, for example, is connected to the pin P6for phase compensation. Note that other circuit configurations are possible for phase compensation.

The comparator19has a positive input terminal and two negative input terminals. An output of the detector16is inputted to the positive input terminal. An output of the error amplifier18is inputted to one of the negative input terminals. The other negative input terminal is connected to the current generator20and the terminal SS, and also connected to the pin P8through the wire H8. For example, the capacitor13is further connected to the pin P8. The current generator20and the capacitor13make up a soft start circuit to control the output voltage Vout at start-up.

The capacitor13in its steady state is charged to a fixed potential by the current generator20. The comparator19compares the output of the detector16with the output of the error amplifier18. The comparator19outputs a high level when the voltage inputted to the terminal VFB is lower than the reference voltage, and otherwise outputs a low level.

When the output from the comparator19is the low level, the driver15performs control to extend the ON-state period of the first switch element Q1. On the other hand, when the output from the comparator19is the high level, the driver15performs control to shorten the ON-state period of the first switch element Q1.

Moreover, the driver15is connected to the terminal EN, and connected to the pin P7through the second conductor K7, i.e. the wire H7. As described above, the enable signal is inputted to the pin P7from the outside. When the enable signal is at a high level, the driver15is set in a normal operation mode for turning on and off the first and second switch elements Q1and Q2. On the other hand, when the enable signal is at a low level, the driver15is set in a standby mode for controlling the first and second switch elements Q1and Q2to be set in the OFF state.

The driver15is also connected to the terminal BOOT, and connected to the pin P1through the second conductor K1, i.e. the wire H1. Further, the capacitor11, for example, is connected between the pins P1and P3. When the first switch element Q1is in the OFF state, a current is supplied to the pin P3through the capacitor11.

In this way, the DC-to-DC converter control circuit30of the semiconductor device1uses the controller14to control the voltage fed back to the terminal VFB to be constant by turning on and off the first and second switch elements Q1and Q2. Accordingly, the output voltage is controlled to be constant by the controller14.

Note thatFIG. 2illustrates the configuration in which the semiconductor device1has the second switch element Q2. However, the second switch element Q2may be replaced by a rectifying element connected so that a current flows in a direction from the ground terminal GND to the first terminal LX.

As described above, the semiconductor device1generates, at the output of the DC-to-DC converter control circuit30, i.e. at the first terminal LX connected to the pin P3, a voltage switched between a power supply potential and a ground potential by turning on and off the first and second switch elements Q1and Q2.

As described above, between the pin P2and the power supply terminal VIN where the power is supplied, there is a parasitic inductance generated by the first wire H2. Between the pin P3and the first terminal LX, there is a parasitic inductance generated by the second wire H3. Between the pin P4connected to the outside ground and the ground terminal GND, there is a parasitic inductance generated by the third wire H4.

Also, there is a parasitic capacitance between a drain and a back gate of each of the first and second switch elements Q1and Q2.FIG. 2equivalently shows a parasitic capacitance21connected between the first terminal LX and the ground terminal GND.

As the output current is increased, areas of the first and second switch elements Q1and Q2are increased, and a capacitance C of the parasitic capacitance21is also increased.

In the voltage generated at the first terminal LX, ringing occurs at both of a rising edge where the voltage changes from the ground potential to the power supply potential and a falling edge where the voltage changes from the power supply potential to the ground potential. Moreover, ringing also occurs in the current flowing through the first and second switch elements Q1and Q2.

A ringing frequency f0is expressed by the following formula (1) with the parasitic inductance L and the capacitance C of the parasitic capacitance21.

The larger the parasitic inductance L and the larger the capacitance C of the parasitic capacitance21, the longer the ringing cycle. Therefore, the larger the output current, the longer it takes to attenuate and stabilize the ringing of the current.

Accordingly, as the parasitic inductance L and the capacitance C of the parasitic capacitance21are increased, it takes longer to stabilize the output of the detector16.

Incidentally, the parasitic inductance L is approximately proportional to a length of a wire connecting the semiconductor substrate2to a lead frame3.

Table 1 shows, for example, a relationship between a wire length and an offset amount DW of the center DL of the semiconductor substrate2with respect to the lead frame3.

In Table 1, the first column indicates the pins P1to P8of the semiconductor device1. The second column indicates the terminal BOOT, the power supply terminal VIN, the first terminal LX, the ground terminal GND, and the terminals VFB, COMP, EN and SS on the semiconductor substrate2. The third and fourth columns indicate the wire lengths between the pins P1to P8and the respective terminals for a comparative example where the offset amount DW is 0 μm and an example where the offset amount DW is 600 μm.

As shown in Table 1, in the example where the offset amount DW of the semiconductor substrate2is 600 μm, the lengths of the wire H1and the first to third wires H2to H4are shorter than those in the comparative example where the offset amount DW is 0 μm. For example, the length of the first wire H2is 1.58 mm in the comparative example where the offset amount DW is 0 μm, and is reduced to 0.99 mm in the example where the offset amount DW is 600 μm.

Note that while the offset amount DW is set to 600 μm in the example, the offset amount DW is not limited thereto but may be set to DW>0.

The reason why the semiconductor substrate (chip or die) is disposed at the position with the offset amount DW=0 μm as in the comparative example is to mount the semiconductor substrate in the center of the lead frame regardless of the size of the chip (die). In this case, it is difficult to shorten the wires unless a new lead frame (comb) is developed to fit the size of the chip (die).

On the other hand, in the semiconductor device1according to the embodiment, the virtual center line DL of the semiconductor substrate2is disposed to be offset with respect to the virtual center line IL of the lead frame3. Therefore, the first to third wires H2to H4can be shortened, and the parasitic inductance L can be reduced.

FIGS. 3A and 3Bare current waveform diagrams of the first switch element.FIG. 3Ashows the case where the offset amount is 0 μm, andFIG. 3Bshows the case where the offset amount is 600 μm.

FIGS. 3A and 3Bshow current waveforms of the first switch element Q1when the first switch element changes from the OFF state to the ON state, with the horizontal axis indicating time and the vertical axis indicating a current flowing through the first switch element.

In the example where the offset amount DW is 600 μm, the current waveform of the first switch element Q1converges faster than that in the comparative example where the offset amount DW is 0 μm.

The semiconductor device1allows ringing to converge in less time, thereby enabling accurate current detection. For this reason, a high switching frequency is easily realized even in the case of a large current.

Moreover, even in the case of a large current, the DC-to-DC converter6can realize a high switching frequency and thus can become more responsive.

Further, the length of the third wire H4between the pin P4and the ground terminal GND is also reduced. Accordingly, a parasitic inductance between the pin P4and the ground terminal GND is also reduced, and thus common mode noise in the ground terminal GND is reduced. As a result, stability and accuracy of the output voltage Vout are improved.

Incidentally,FIG. 2illustrates the configuration of the controller14in a current mode for detecting the current flowing through the first switch element Q1and controlling the output voltage to be constant. However, the output voltage can also be controlled using a current mode for detecting a current flowing through the second switch element Q2.

FIG. 4is a circuit diagram illustrating a DC-to-DC converter according to another embodiment.

As shown inFIG. 4, a semiconductor device is has a configuration in which the semiconductor substrate2shown inFIG. 2is replaced by a semiconductor substrate2a. A device main body which is not illustrated, first conductors K2to K4and second conductors K1and K5to K8are the same as those in the semiconductor device1shown inFIG. 1. In addition, first to third wires H2to H4, wires H1and H5to H8, a first terminal LX, a power supply terminal VIN, a ground terminal GND, and terminals BOOT, VFB, COMP, EN and SS are the same as those in the semiconductor device1shown inFIGS. 1 and 2.

To be more specific, in the semiconductor device1a, a DC-to-DC converter control circuit30ais provided on the semiconductor substrate2a. The DC-to-DC converter control circuit30ahas a detector16a. Note that the terminal BOOT, the first terminal LX, the power supply terminal VIN and the ground terminal GND are provided on a first side (not shown). The terminals VFB, COMP, EN and SS are provided on the opposite side to the first side.

Further, a virtual center line of the semiconductor substrate2ais disposed to be offset to the first side with respect to a virtual center line of a semiconductor substrate mounting part.

In the DC-to-DC converter control circuit30a, first and second switch elements Q1and Q2and a controller14aare provided. The controller14ahas a configuration in which the detector16in the controller14shown inFIG. 2is replaced by the detector16a. A driver15, a voltage generator17, an error amplifier18, a comparator19, a current generator20and a parasitic capacitance21are the same as those in the controller14shown inFIG. 2.

The detector16ais a current detector which is connected to the power supply terminal VIN, the first terminal LX and the ground terminal GND, and detects, through the first conductors K2to K4, a current flowing through the second switch element Q2. The detector16adetects an output current of the DC-to-DC converter control circuit30aby detecting the current flowing through the second switch element Q2. The detector16ahas the same configuration as that of the detector16shown inFIG. 2.

Further, use of the semiconductor device1acan configure a DC-to-DC converter6ain a current mode for detecting and controlling the current flowing through the second switch element Q2.

The DC-to-DC converter6aincludes the semiconductor device1a, a first inductor7, a first capacitor8, a feedback circuit9and capacitors11to13and23. The DC-to-DC converter6ahas a configuration in which the semiconductor device1in the DC-to-DC converter6shown inFIG. 2is replaced by the semiconductor device1a. The first inductor7, the first capacitor8, the feedback circuit9and the capacitors11to13and23are the same as those in the DC-to-DC converter6.

The semiconductor device is allows ringing to converge in less time, thereby enabling accurate current detection. For this reason, even in the case of a large current, the DC-to-DC converter6acan realize a high switching frequency and thus can become more responsive.

Further, the length of the third wire H4between the first conductor K4, i.e. the pin P4and the ground terminal GND is also reduced. Accordingly, a parasitic inductance between the pin P4and the ground terminal GND is also reduced, and thus common mode noise in the ground terminal GND is reduced. As a result, one-point grounding of the ground terminal GND is ensured, and the stable ground potential improves stability and accuracy of the output voltage Vout.

Such stabilization of the potential of the ground terminal GND is effective also in the case where there is no current detector as in the semiconductor devices1and1a.

FIG. 5is a circuit diagram illustrating a DC-to-DC converter according to another embodiment.

As shown inFIG. 5, a semiconductor device1bhas a configuration in which the semiconductor substrate2shown inFIG. 2is replaced by a semiconductor substrate2b. A device main body which is not illustrated, first conductors K2to K4and second conductors K1and K5to K8are the same as those in the semiconductor device1shown inFIG. 1. In addition, first to third wires H2to H4, wires H1and H5to H8, a first terminal LX, a power supply terminal VIN, a ground terminal GND, and terminals BOOT, VFB, COMP, EN and SS are the same as those in the semiconductor device1shown inFIGS. 1 and 2.

To be more specific, in the semiconductor device1b, a DC-to-DC converter control circuit30bis provided on the semiconductor substrate2b. The DC-to-DC converter control circuit30bhas an error amplifier18. Note that the terminal BOOT, the first terminal LX, the power supply terminal VIN and the ground terminal GND are provided on a first side (not shown). The terminals VFB, COMP, EN and SS are provided on the opposite side to the first side.

Further, a virtual center line of the semiconductor substrate2bis disposed to be offset to the first side with respect to a virtual center line of a semiconductor substrate mounting part (not shown).

In the DC-to-DC converter control circuit30b, first and second switch elements Q1and Q2and a controller14bare provided. The controller14bhas a configuration in which the detector16in the controller14shown inFIG. 2is replaced by a triangle wave generator22. A driver15, a voltage generator17, the error amplifier18, a comparator19, a current generator20and a parasitic capacitance21are the same as those in the controller14shown inFIG. 2.

Here, the controller14bis connected to the ground terminal GND, to which a ground potential is supplied through the first conductor K4. The semiconductor substrate2bis disposed so that the third wire H4of the first conductor K4is shortened. As a result, one-point grounding is ensured, and thus common mode noise is reduced. Further, the error amplifier18detects and amplifies an error in a voltage fed back to the terminal VFB, and thus the output voltage is stabilized. The error amplifier18functions as a detector for detecting a voltage.

The triangle wave generator22is a circuit for generating a triangle wave synchronized with a switching frequency of the first and second switch elements Q1and Q2. An output from the triangle wave generator22is inputted to a positive input terminal of the comparator19to convert the error voltage into time.

In other words, the controller14bcontrols the first and second switch elements Q1and Q2using a PWM signal whose duty ratio varies according to the magnitude of the error voltage.

Further, use of the semiconductor device1bcan configure a DC-to-DC converter6bin a voltage mode.

The DC-to-DC converter6bincludes the semiconductor device1b, a first inductor7, a first capacitor8, a feedback circuit9and capacitors11to13and23.

The DC-to-DC converter6bhas a configuration in which the semiconductor device1in the DC-to-DC converter6shown inFIG. 2is replaced by the semiconductor device1b. The first inductor7, the first capacitor8, the feedback circuit9and the capacitors11to13and23are the same as those in the DC-to-DC converter6.

The semiconductor device1band the DC-to-DC converter6bcan reduce common mode noise, thereby improving stability. As a result, a high switching frequency can be realized.

Further, the length of the third wire H4between the ground terminal GND and the pin P4is also reduced. Accordingly, a parasitic inductance between the ground terminal GND and the pin P4is also reduced, and thus common mode noise in the ground terminal GND is reduced. As a result, stability and accuracy of the output voltage Vout are improved.