Packages with multi-thermal interface materials and methods of fabricating the same

A package includes a die on a surface of a package component. The package also includes a first die stack on the surface of the package component. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and disposed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and disposed on the die. The first thermal conductivity of the first TIM is different from the second thermal conductivity of the second TIM.

BACKGROUND

When more devices are placed in one chip, the design complexity also increases. One solution to solve the problems discussed above is to stack dies on top of one another and interconnect or route them through connections. Such a configuration is named a three-dimensional integrated circuit (3DIC). Some of the benefits of 3DIC include exhibiting a smaller footprint, reducing power consumption by reducing the lengths of signal interconnects, and improving yield and fabrication cost if individual dies are tested separately prior to assembly. Although existing methods of fabricating 3DIC packages have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

Embodiments disclosed herein relate generally to packages with multi-thermal interface materials. The multi-thermal interface materials may be dispensed on different dies or die stacks of the whole package by using different dispensers. The multi-thermal interface materials dispensed on different dies or die stacks by using different dispensers can enhance the throughput of fabricating packages. According to the embodiments of the disclosure, a thermal interface material that has a relatively high thermal conductivity is dispensed on a high-power consuming die or die stack. Therefore, the heat dissipation of the whole package is improved.

Moreover, the multi-thermal interface materials dispensed on different dies or die stacks of the whole package can avoid or reduce stress concentration phenomenon. According to the embodiments of the disclosure, a thermal interface material that has fillers with a relatively large particle size may be dispensed on dies or die stacks located at the peripheral region of the package. The whole thickness of the multi-thermal interface materials depends on the relatively large particle sized fillers in the thermal interface material and becomes thick. The warpage variation of the package is thereby decreased to reduce stress concentration phenomenon of packages. Therefore, some defects of packages, for example, die crack or low-k dielectric layer delamination are prevented. Accordingly, the reliability of the packages is enhanced.

The foregoing broadly outlines some aspects of the embodiments described herein. Some embodiments described herein are described in the context of 3DIC packages or 2.5DIC packages. Some variations of the exemplary methods and structures are described in the embodiments of the disclosure. A person having ordinary skill in the art will readily understand other modifications may be made that are contemplated within the scope of other embodiments. Although embodiments of the method may be described in a particular order, various other embodiments of the method may be performed in any logical order and may include fewer or more steps than what is described herein.

FIGS. 1A, 2A, 3A-1, 3A-2, 4A and 5Aillustrate top views of intermediate structures at various stages of an exemplary method of forming a package100, in accordance with some embodiments. The package100may be a 2D (two-dimensional) IC package, a 2.5DIC package or a 3DIC package. The 2.5DIC package is a 2DIC package incorporating with an interposer. The 3DIC package is for example a chip-on-wafer-on-substrate (CoWoS) package. In some embodiments, the package100is illustrated using a 3DIC package.FIGS. 1B, 1D, 1E, 2B, 2C, 3B, 4B, 5B-1 and 5B-2illustrate cross-sectional views of intermediate structures at various stages of an exemplary method for forming a package100, along line B-B inFIGS. 1A, 2A, 3A-1, 3A-2, 4A and 5A, in accordance with some embodiments.

FIG. 1Ais a top view of an initial package structure50at a stage of an exemplary method of forming a package100, in accordance with some embodiments. The initial package structure50includes multiple dies, multiple die stacks or a combination thereof. In some embodiments, the initial package structure50includes one die or die stack10and four die stacks12around the die or die stack10in the top view ofFIG. 1A. In some other embodiments, the initial package structure50includes one die or die stack10and four dies13around the die or die stack10in the top view ofFIG. 1A. The initial package structure50may include any number of dies and/or die stacks, and is not limited to the number of dies and/or die stacks inFIG. 1A. In addition, the layout of the dies and/or die stacks in the packages100is not limited to that ofFIG. 1A.

FIG. 1Bis a cross-sectional view of an initial package structure50along line B-B inFIG. 1A, in accordance with some embodiments. The initial package structure50may be a chip-on-wafer (CoW) package. The initial package structure50may include a die10disposed between two die stacks12(sometimes referred to as chips10and12). In some embodiments, the die10is a high-power consuming die and the die stacks12are low-power consuming die stacks. The die10may consume a relatively high amount of power, and hence generate a relatively large amount of heat, compared to the die stacks12. For example, a high-power consuming die10may consume between about 50 W and about 100 W of power. A low-power consuming die stack12may consume between about 5 W and about 10 W of power.

In some embodiments, the die10may be a single system on chip (SoC) die or a logic die, which may further be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or the like. In some embodiments, the die stacks12may be high bandwidth memory (HBM) and/or high memory cube (HMC) modules, which may include multiple memory dies12bbonded to a logic die12a, as shown inFIG. 1Bin accordance with some embodiments. In alternative embodiments, the die10and the die stacks12may be other chips having other functions.

Referring toFIGS. 1A and 1B, the die10and the die stacks12are encased in a molding compound16, in accordance with some embodiments. As shown inFIG. 1A, the molding compound16may form a full ring encircling the die10and the die stacks12, in accordance with some embodiments. In alternative embodiments, the molding compound16does not form a full ring, and may include a single piece or a plurality of discrete pieces. As shown inFIG. 1B, the top surface of the die10is coplanar with the top surface of the molding compound16, in accordance with some embodiments. Also, the top die12bin the die stacks12has a top surface that is coplanar with the top surface of the molding compound16. The top surfaces of the die10and the die stacks12are exposed through the molding compound16.

The die10and the die stacks12are bonded to a top surface of a package component such as an interposer18through a plurality of connectors14, as shown inFIG. 1Bin accordance with some embodiments. The connectors14may be micro-bumps. In alternative embodiments, the die10and the die stacks12may be bonded to a different package component such as a substrate, a printed circuit board (PCB), or the like. The interposer18may be a wafer having an interconnect structure for electrically connecting active devices (not shown) in the die10and the die stacks12to form functional circuits.

FIG. 1Cillustrates a detailed cross-sectional view of an interposer18in accordance with some embodiments. A connector14of the die10or the die stack12is electrically connected to a contact pad22on a top side of the interposer18. A passivation layer24may extend over a top surface of the interposer18and cover edge portions of the contact pad22. The contact pad22is disposed in a dielectric layer27and is electrically connected to metallization layers26. The metallization layers26may include metal lines28aand vias28bformed in multiple dielectric layers27. The dielectric layers27are made of a dielectric material, for example a low-k dielectric material having a k-value lower than about 4.0 or an extra-low-k (ELK) dielectric material having a k-value lower than about 2.8. A through-substrate via (TSV)30may electrically connect the metallization layer26to a connector20on a backside of the interposer18. The TSV30is formed to pass through a substrate29of the interposer18.

In some embodiments, the connectors20on the backside of the interposer18may be controlled collapse chip connection (C4) bumps, which include solder balls. The connectors20may have a larger critical dimension (e.g., pitch) than that of the connectors14. For example, the connectors20may have a pitch of about 100 μm while the connectors14may have a pitch of about 40 μm. The interposer18may further have an under-bump metallurgy (UBM)32connected to the connector20and a passivation layer34on the backside of the interposer18. Other configurations of the interposer18may also be used.

FIG. 1Dis a cross-sectional view of an initial package structure50at a stage of an exemplary method of forming the package100, along line B-B inFIG. 1A, in accordance with some other embodiments. The initial package structure50ofFIG. 1Dis used in a 2.5DIC package, and may include a die10disposed between two dies13(sometimes referred to as chips10and13). In some embodiments, the die10is a high-power consuming die and the dies13are low-power consuming dies. The die10may consume a relatively high amount of power, and hence generate a relatively large amount of heat, compared to the dies13. For example, a high-power consuming die10may consume between about 50 W and about 100 W of power. A low-power consuming die13may consume between about 5 W and about 10 W of power.

In some embodiments, the die10may be a single system on chip (SoC) die or a logic die, which may further be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or the like. In some embodiments, the dies13may be memory dies. In alternative embodiments, the die10and the dies13may be other chips having other functions.

Referring toFIGS. 1A and 1D, the die10and the dies13are encased in a molding compound16, in accordance with some embodiments. As shown in the top view ofFIG. 1A, the molding compound16may form a full ring encircling the die10and the dies13, in accordance with some embodiments. In alternative embodiments, the molding compound16does not form a full ring, and may include a single piece or a plurality of discrete pieces. As shown in the cross-sectional view ofFIG. 1D, the top surface of the die10is coplanar with the top surface of the molding compound16, in accordance with some embodiments. Also, the dies13have top surfaces that are coplanar with the top surface of the molding compound16. Therefore, the top surfaces of the die10and the dies13are exposed through the molding compound16.

The die10and the dies13are bonded to a top surface of a package component such as an interposer18through a plurality of connectors14, as shown inFIG. 1Din accordance with some embodiments. The connectors14may be micro-bumps. The interposer18may be a wafer having an interconnect structure for electrically connecting active devices (not shown) in the die10and the dies13to form functional circuits. The detailed structure of the interposer18may be the same as or similar to those described above with respect to the interposer18ofFIG. 1C. In alternative embodiments, the package100is a 2DIC package and the interposer18ofFIG. 1Dis omitted. The die10and the dies13are bonded to a different package component such as a substrate, a printed circuit board (PCB), or the like.

FIG. 1Eis a cross-sectional view of an initial package structure50at a stage of an exemplary method of forming the package100along line B-B inFIG. 1A, in accordance with some embodiments. The initial package structure50ofFIG. 1Eis a CoW package for a 3DIC package, and may include a die stack10disposed between two die stacks12(sometimes referred to as chips10and12).

The die stack10may be multiple stacked dies, for example a die10-1stacked on a die10-2. In some embodiments, each of the dies10-1and10-2is a high-power consuming die and the die stacks12are low-power consuming die stacks. The dies10-1and10-2may consume a relatively high amount of power, and hence generate a relatively large amount of heat, compared to the die stacks12. For example, a high-power consuming die10-1or10-2may consume between about 50 W and about 100 W of power. A low-power consuming die stack12may consume between about 5 W and about 10 W of power.

In some embodiments, each of the dies10-1and10-2may be a single system on chip (SoC) die or a logic die, which may further be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or the like. In some embodiments, the die stacks12may be high bandwidth memory (HBM) and/or high memory cube (HMC) modules, which may include multiple memory dies12bbonded to a logic die12a, as shown inFIG. 1Ein accordance with some embodiments. In alternative embodiments, the die stack10and the die stacks12may be other chips having other functions.

Referring toFIGS. 1A and 1E, the die stack10and the die stacks12are encased in a molding compound16, in accordance with some embodiments. As shown in the top view ofFIG. 1A, the molding compound16may form a full ring encircling the die stack10and the die stacks12, in accordance with some embodiments. In alternative embodiments, the molding compound16does not form a full ring, and may include a single piece or a plurality of discrete pieces. As shown in the cross-sectional view ofFIG. 1E, the top die10-1of the die stack10has a top surface that is coplanar with the top surface of the molding compound16, in accordance with some embodiments. Also, the top die12bin the die stacks12has a top surface that is coplanar with the top surface of the molding compound16. The top surfaces of the top die10-1of the die stack10and the top dies12bof the die stacks12are exposed through the molding compound16.

The die stack10and the die stacks12are bonded to a top surface of a package component such as an interposer18through a plurality of connectors14, as shown inFIG. 1Ein accordance with some embodiments. The connectors14may be micro-bumps. In alternative embodiments, the die stack10and the die stacks12may be bonded to a different package component such as a substrate, a printed circuit board (PCB), or the like. The interposer18may be a wafer having an interconnect structure for electrically connecting active devices (not shown) in the die stack10and the die stacks12to form functional circuits. The detailed structure of the interposer18may be the same as or similar to those described above with respect to the interposer18ofFIG. 1C.

Next, referring toFIGS. 2A and 2B, the initial package structure50ofFIG. 1B, such as a CoW package, is bonded to a substrate52using the connectors20for forming a package100, in accordance with some embodiments.FIG. 2Ais a top view of an intermediate structure at a stage of an exemplary method of forming the package100, andFIG. 2Bis a cross-sectional view along line B-B inFIG. 2A, in accordance with some embodiments. The package100may be a chip-on-wafer-on-substrate (CoWoS) package. In alternative embodiments, the initial package structure50ofFIG. 1D or 1Eis bonded to a substrate52using the connectors20to form another package100. A reflow process is performed to reflow and bond the connectors20to the substrate52. In the embodiments ofFIGS. 2B, 2C, 3B, 4B, 5B-1 and 5B-2, the initial package structure50ofFIG. 1Bis illustrated as an exemplary structure. In alternative embodiments, the initial package structures50ofFIGS. 1D and 1Emay be used to bond with the substrate52for forming other packages100.

In some embodiments, the substrate52may be a printed circuit board (PCB), an organic substrate, a ceramic substrate, a motherboard, or the like. The substrate52may be used to interconnect the initial package structures50with other packages and/or devices to form functional circuits. The other packages and/or devices may be multiple passive devices53, such as capacitors, resistors, inductors, varactors, and/or the like. The passive devices53may also be electrically connected to the interposer18through the substrate52and the connectors20. Alternatively, die stacks10and12and the passive devices53may be attached to an organic or ceramic substrate. As shown inFIGS. 2A and 2B, the multiple passive devices53are attached to the top surface of the substrate52and around the periphery of the initial package structures50in accordance with some embodiments. Moreover, the initial package structure50is also attached to the top surface of the substrate52.

In addition, the package100may further include contacts54disposed on the bottom surface of the substrate52, as shown inFIG. 2Bin accordance with some embodiments. The contacts54are disposed opposite to the initial package structure50and the passive devices53. The contacts54may be ball grid array (BGA) balls. The contacts54may be used to electrically connect the package100such as a CoWoS package to a motherboard (not shown) or another device component of an electrical system.

Next, an underfill material56may be dispensed between the initial package structure50and the substrate52, as shown inFIG. 2Cin accordance with some embodiments. The underfill material56may be a silica filled epoxy resin, and may be used to fill the gap space between the initial package structure50and the substrate52. The underfill material56may be injected into the gap space using a nozzle that is moved around the initial package structure50. The underfill material56may increase mechanical reliability by distributing stresses across the top surface of the substrate52rather than allowing them to become concentrated in the connectors20. In addition, the underfill material56may provide encapsulation from moisture and contaminants in the external environment. In alternative embodiments, the underfill material56may be omitted. A molding compound (not shown) may be used to fill the gap space between the initial package structure50and the substrate52.

Next, referring toFIG. 3A-1, an adhesive60is dispensed on the top surface of the substrate52, and a first thermal interface material (TIM)62is dispensed on the die stacks12of the initial package structure50, in accordance with some embodiments. The adhesive60is dispensed on the peripheral area of the substrate52to encircle the passive devices53and the initial package structure50. As shown in the top view ofFIG. 3A-1, the adhesive60does not form a full ring, and may include a plurality of discrete pieces, in accordance with some embodiments. Alternatively, the adhesive60forms a full ring to encircle the passive devices53and the initial package structure50, as shown inFIG. 3A-2in accordance with some embodiments.FIG. 3Billustrates a cross-sectional view of an intermediate structure for forming the package100along line B-B inFIGS. 3A-1 and 3A-2, in accordance with some embodiments.

In some embodiments, the first TIM62and the adhesive60are made of the same material and can be dispensed by using the same dispenser. The material of the adhesive60and the first TIM62includes a base material and fillers dispersed in the base material. The base material may be a polymer such as epoxies, urethane, polyurethane, silicone elastomers or the like. The fillers are such as particles made of aluminum oxide, boron nitride, aluminum nitride or the like. The first TIM62is dispensed on the die stacks12and/or the dies13. The die stacks12and/or the dies13consume a relatively low amount of power, and hence generate less heat than the die or die stack10.

The first TIM62may be dispensed to a pattern of a plurality of strips as shown inFIGS. 3A-1 and 3A-2in accordance with some embodiments. The width and the length of the strips, and the space between the strips of the first TIM62are determined by the area size of the dies13and/or the die stacks12. In some examples, the thickness of the dispensed strips of the second TIM64is in a range from about 5 μm to about 500 μm, for example about 100 μm. In some examples, the first TIM62may be dispensed across about 50% to about 100% of the area of the dies13and/or the die stacks12. The dispensed strips of the first TIM62do not completely occupy all area of the dies13and/or the die stacks12.

Next, referring toFIGS. 4A and 4B, a second thermal interface material (TIM)64is dispensed on the die or die stack10of the initial package structure50, in accordance with some embodiments. The die or die stack10consumes a relatively high amount of power, and hence generate a relatively large amount of heat, compared to the dies13and/or the die stacks12. The second TIM64on the high-power consuming die or die stack10has a thermal conductivity that is higher than the thermal conductivity of the first TIM62on the low-power consuming dies13or die stacks12. In some examples, the thermal conductivity of the first TIM62and the thermal conductivity of the adhesive60are in a range from about 0.5 W/mK to about 2 W/mK. The thermal conductivity of the second TIM64is in a range from about 10 W/mK to about 50 W/mK.

In some embodiments, the material of the second TIM64includes a base material and thermal conductive fillers dispersed in the base material. The base material includes a polymer such as silicone resin, epoxy resin or the like, which has a good thermal conductivity in a range from about 3 watts per meter kelvin (W/mK) to about 5 W/mK. The thermal conductive fillers in the second TIM64include particles made of aluminum oxide, boron nitride, aluminum nitride, aluminum, copper, silver, indium, nickel or a combination thereof. In other embodiments, the second TIM64includes other materials such as a metallic-based or solder-based material containing silver, indium paste, or the like.

FIG. 4Billustrates a cross-sectional view of an intermediate structure of forming the package100along line B-B inFIG. 4A, after the first TIM62and the second TIM64are dispensed on the initial package structure50, in accordance with some embodiments.FIG. 4Cis an enlarged cross-sectional view of a region C inFIG. 4B, in accordance with some embodiments. The particle size of the fillers62fin the first TIM62is larger than the particle size of the thermal conductive fillers64fin the second TIM64. In some examples, the particle size of the fillers62fin the first TIM62is in a range from about 5 times to about 20 times larger than the particle size of the thermal conductive fillers64fin the second TIM64.

The second TIM64may be also dispensed to a pattern of a plurality of strips, as shown inFIG. 4Ain accordance with some embodiments. The dispensed strips of the second TIM64may be a continuous pattern. The width and the length of the strips, and the space between the strips of the second TIM64are determined by the area size of the die or die stack10. In some examples, the thickness of the dispensed strips of the second TIM64is in a range from about 5 μm to about 500 μm, for example about 100 μm. In some examples, the second TIM64may be dispensed across about 80% to about 100% of the area of the die or die stack10. The dispensed strips of the second TIM64do not completely occupy all area of the die or die stack10.

Afterwards, referring toFIGS. 5A and 5B-1, a lid70is attached on the initial package structure50through the first TIM62and the second TIM64, and the lid70is also attached on the substrate52through the adhesive60, in accordance with some embodiments.FIG. 5Ais a top view of the lid70attached on the initial package structure50to form the package100, in accordance with some embodiments.FIG. 5B-1is a cross-sectional view of the package100along line B-B inFIG. 5A, in accordance with some embodiments. After the lid70is attached on the initial package structure50, the first TIM62and the second TIM64have the same thickness and fill the space between the lid70and the initial package structure50. Moreover, the thickness of the second TIM64depends on the particle size of the fillers62f(FIG. 4C) in the first TIM62since the particle size of the fillers62fis larger than the particle size of the thermal conductive fillers64f(FIG. 4C) in the second TIM64.

In some embodiments, the lid70is a heat dissipating lid which includes a top portion70T and a ring portion70R. The bottom surface of the top portion70T is in contact with the first TIM62and the second TIM64. The bottom surface of the ring portion70R is in contact with the adhesive60to adhere the lid70to the substrate52. The top view of the ring portion70R may form a ring encircling the die or die stack10and the dies13or the die stacks12of the initial package structure50. In alternative embodiments, the ring portion70R may form a partial ring, or may include a plurality of separated pieces. The lid70may have a high thermal conductivity, for example in a range from about 200 W/mK to about 400 W/mK or more, and may be made of a metal or a metal alloy. In some examples, the material of the lid70is such as Al, Cu, Ni, Co, alloy thereof, or a combination thereof.

After the lid70is attached on the substrate52to encapsulate the initial package structure50, the first TIM62and the second TIM64may completely occupy the space between the top portion70T of the lid70and the initial package structure50, as shown inFIG. 5B-1in accordance with some embodiments. In some other embodiments, the first TIM62and the second TIM64may partially occupy the space between the top portion70T of the lid70and the initial package structure50. There may be a gap presented in the first TIM62and the second TIM64. In addition, after the lid70is attached on the substrate52, the passive devices53are positioned between the ring portion70R of the lid70and the substrate52. Moreover, the passive devices53are disposed between the adhesive60and the initial package structure50. In the package100, the die or die stack10, the dies13and/or the die stacks12, and the passive devices53are encapsulated and protected by the lid70, the first TIM62, the second TIM64, and the adhesive60.

FIG. 5B-2illustrates a cross-sectional view of the package100along line B-B inFIG. 5A, in accordance with some embodiments. The package100includes a heat dissipating ring72attached on the substrate52using the adhesive60. Thereafter, a lid70is attached on the heat dissipating ring72using an additional adhesive66. In some instances, the adhesive60and the additional adhesive66may be made of the same material. In some other instances, the material of the adhesive60may be different from that of the additional adhesive66. The lid70is also attached on the initial package structure50using the first TIM62and the second TIM64.

In some embodiments, the lid70may be made of a metal or a metal alloy, for example Al, Cu, Ni, Co, alloy thereof, or a combination thereof. In some instances, the heat dissipating ring72may be made of a thermal conductive material that is different from the material of the lid70. The material of the heat dissipating ring72is for example silicon carbide, aluminum nitride, graphite, and the like. In some instances, the heat dissipating ring72may be made of the same material as the lid70. In the embodiments, the passive devices53are positioned between the lid70and the substrate52and encircled by the heat dissipating ring72. In addition, the passive devices53are disposed between the adhesive60and the initial package structure50.

In some embodiments, the first TIM62, the adhesive60and the additional adhesive66are made of the same material. The first TIM62and the adhesive60are dispensed by using a first dispenser in the same process step. The additional adhesive66is dispensed by using the first dispenser in another process step. Next, the second TIM64is dispensed by using a second dispenser. In some other embodiments, the first TIM62, the adhesive60and the additional adhesive66are made of the same material. The adhesive60is dispensed by using a first dispenser. The first TIM62and the additional adhesive66are dispensed by using the first dispenser in the same process step. Thereafter, the second TIM64is dispensed by using a second dispenser.

In the embodiments, after the lid70is attached on the initial package structure50, the first TIM62and the second TIM64have the same thickness. Moreover, the thickness of the second TIM64depends on the particle size of the fillers62f(FIG. 4C) in the first TIM62since the particle size of the fillers62fis larger than the particle size of the thermal conductive fillers64f(FIG. 4C) in the second TIM64. Therefore, the thickness of the second TIM64of the embodiments of the disclosure becomes thicker than using a single second TIM64dispensed on the whole area of the initial package structure50.

In the development of IC industry, the package size becomes bigger and bigger as more and more system in package (SiP) technology applications are needed. The throughput of fabricating IC packages is difficult to enhance due to a fabrication bottleneck in the TIM dispensing process on the dies or die stacks. In some embodiments, the adhesive60and the first TIM62are made of the same material and can be dispensed by using the same dispenser in the same process step. The second TIM64can be dispensed on the remaining area of the initial package structure50by using another dispenser. The bottleneck in the fabrication process that occurs in the TIM dispensing process can be eliminated, and the time it takes to fabricate the packages100is reduced. Therefore, the throughput of fabricating the packages100according the embodiments of the disclosure is higher than that of fabricating packages by using a dispenser for dispensing a single TIM on the whole area of the initial package structure.

In some other embodiments, the adhesive60and the first TIM62may be made of different materials. The adhesive60may be dispensed on the substrate52by using a first dispenser. The first TIM62may be dispensed on the dies13and/or the die stacks12by using a second dispenser. The second TIM64may be dispensed on the die or die stack10by using a third dispenser. The throughput of fabricating the packages100according the embodiments of the disclosure is still higher than that of fabricating packages by using a dispenser for dispensing a single TIM on the whole area of the initial package structure.

In some embodiments, the initial package structure50may include a first die or die stack that consumes a relatively low amount of power, and hence generate less heat. The initial package structure50may also include a second die or die stack that consumes a higher amount of power than the first die or die stack, and hence generate a larger amount of heat than the first die or die stack. The initial package structure50may further include a third die or die stack that consumes a higher amount of power than the second die or die stack, and hence generates a larger amount of heat than the second die or die stack. A first TIM may be dispensed on the first die or die stack. A second TIM may be dispensed on the second die or die stack. A third TIM may be dispensed on the third die or die stack. In some embodiments, the first TIM has a first thermal conductivity that is lower than the second thermal conductivity of the second TIM. Moreover, the second thermal conductivity of the second TIM is lower than a third thermal conductivity of the third TIM.

In some embodiments, the first TIM and the adhesive may be made of the same material and are dispensed by using a first dispenser. The second TIM and the third TIM may be dispensed by using a second dispenser and a third dispenser, respectively. According to the embodiments of the disclosure, the first, second and third TIMs on the whole area of the initial package structure50can be dispensed by using the first, second and third dispensers, respectively. Therefore, the throughput of fabricating the packages100according the embodiments of the disclosure is enhanced.

In some other embodiments, the first TIM and the adhesive may be made of the same material and are dispensed by using a first dispenser. The second TIM and the third TIM may be made of the same material and are dispensed by using a second dispenser. The throughput of fabricating the packages100according the embodiments of the disclosure is also enhanced.

In some embodiments, the dispensing patterns of the first TIM62and the second TIM64may be continuous strips as shown inFIG. 4A. In some other embodiments, the dispensing pattern of the first TIM62may be different from the dispensing pattern of the second TIM64, and those patterns are not limited to a plurality of strips. In addition, the layout of the dies or die stacks that consume different amounts of power is not limited in that ofFIG. 1A. In some embodiments, a high-power consuming die or die stack10may be positioned in the center region of the initial package structure50. A low-power consuming die13or die stack12may be positioned in the peripheral region of the initial package structure50. In some embodiments, a high-power consuming die or die stack10may be positioned in a region of the initial package structure50, such as a corner region or an edge region, and a low-power consuming die13or die stack12may be positioned in another region of the initial package structure50.

In some embodiments, the first TIM62including fillers62fof a large particle size (FIG. 4C) is dispensed on the low-power consuming die13or die stack12in the peripheral region of the initial package structure50. The second TIM64including fillers64fof a small particle size (FIG. 4C) is dispensed on the high-power consuming die or die stack10in the center region of the initial package structure50. The small particle sized fillers64fof the second TIM64can increase contact area of the fillers64fto enhance heat spreading effect. Therefore, the second TIM64having the small particle sized fillers64fcan provide a higher thermal conductivity than the first TIM62having the large particle sized fillers62f. In general, a TIM having small particle sized fillers has a thickness that is thinner than that of another TIM having large particle sized fillers. A thinner TIM between the lid70and the initial package structure50may easily cause a die crack.

According to the embodiments of the disclosure, after the lid70is attached on the substrate52(FIGS. 5B-1 and 5B-2), the thickness of the second TIM64is the same as that of the first TIM62and depends on the particle size of the fillers62fin the first TIM62. Therefore, the thickness of the second TIM64having small particle sized fillers64fis increased to avoid die crack. The reliability of the packages100is thereby improved. In addition, the thickness of the second TIM64depending on the large particle sized fillers62fin the first TIM62to become thick can reduce stress concentration phenomenon. An extra-low-k (ELK) dielectric layer delamination and an edge molded underfill crack are thereby prevented. Moreover, the first TIM62having large particle sized fillers62fpositioned in the peripheral region of the initial package structure50can prevent the second TIM64flow out during performing a high temperature process on the packages100. Therefore, the reliability of the packages100according to the embodiments of the disclosure is enhanced.

According to the embodiments of the disclosure, multiple TIMs, for example the first TIM62and the second TIM64are dispensed on different dies or die stacks of the packages100to achieve the foregoing advantages. In some embodiments, the first TIM62is dispensed on the low-power consuming dies13or die stacks12in the peripheral region of the initial package structure50. The second TIM64is dispensed on the high-power consuming die or die stack10in the center region of the initial package structure50. The first TIM62includes relatively large particle sized fillers62fand has a relatively low thermal conductivity. The second TIM64includes relatively small particle sized fillers64fand has a relatively high thermal conductivity. The first TIM62and the second TIM64used in the packages100can reduce stress concentration phenomenon and avoid die crack. Moreover, the second TIM64can be selected to enhance thermal conductivity. Therefore, the heat spreading effect and the reliability of the packages100according to the embodiments of the disclosure are enhanced.

In addition, the first TIM62and the adhesive60may be dispensed by using the same dispenser and the second TIM64may be dispensed by using another dispenser to eliminate the bottleneck in the fabrication process of IC packages. The throughput of fabricating the packages100according the embodiments of the disclosure is thereby enhanced.

In some embodiments, a package is provided. The package includes a die on a surface of a package component. The package also includes a first die stack on the surface of the package component. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and disposed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and disposed on the die. The first thermal conductivity of the first TIM is different from the second thermal conductivity of the second TIM.

In some embodiments, a package is provided. The package includes a first die stack disposed over and bonded to a surface of a substrate. The package also includes a second die stack disposed over and bonded to the surface of the substrate. The first die stack consumes a relatively low amount of power than the second die stack. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and dispensed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and dispensed on the second die stack. The first thermal conductivity of the first TIM is lower the second thermal conductivity of the second TIM.

In some embodiments, a method of fabricating a package is provided. The method includes bonding a first die on a surface of a package component, and bonding a second die on the surface of the package component. The method also includes bonding the package component on a substrate. The method further includes dispensing a first thermal interface material (TIM) on the first die, and dispensing a second thermal interface material (TIM) on the second die. In addition, the method includes dispensing an adhesive on the substrate and around the package component.