Semiconductor device and method of fabricating the same

A method of fabricating a semiconductor device according to one embodiment includes: forming a fin and a film on a semiconductor substrate, the film being located at least either on the fin or under the fin and on the semiconductor substrate; forming a gate electrode so as to sandwich both side faces of the fin via a gate insulating film; and expanding or shrinking the film, thereby generating a strain in a height direction of the fin in a channel region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2008-103850, filed on Apr. 11, 2008, the entire contents of which are incorporated herein by reference.

BACKGROUND

In a conventional fin-type transistor, there is known a technique in which, when a plane direction of a channel region formed on side faces of a fin of an n-type transistor is (110) and a direction of electrical current is <1-10>, carrier (electron) mobility in the channel region is improved by generating a compressive strain in a height direction (<001> direction) in the fin.

BRIEF SUMMARY

A method of fabricating a semiconductor device according to one embodiment includes: forming a fin and a film on a semiconductor substrate, the film being located at least either on the fin or under the fin and on the semiconductor substrate; forming a gate electrode so as to sandwich both side faces of the fin via a gate insulating film; and expanding or shrinking the film, thereby generating a strain in a height direction of the fin in a channel region.

A method of fabricating a semiconductor device according to another embodiment includes: forming a fin, a pad connected to the fin and a film on a semiconductor substrate, the film being located at least either on or under the fin and the pad; expanding or shrinking a portion of the film that is located on an interface with the fin and on a portion of outside of an interface with the pad, thereby generating a strain in a height direction of the fin in the fin; and forming a gate electrode so as to sandwich both side faces of the fin via gate insulating films.

A semiconductor device, comprising: a fin formed on a semiconductor substrate and having a strain in a height direction in a channel region therein; a gate electrode formed so as to sandwich both side faces of a portion of the fin including the channel region; and a film formed at least either on or under a portion of the fin including the channel region, the film configured to generate a strain to the portion of the fin.

DETAILED DESCRIPTION

First Embodiment

Structure of Semiconductor Device

FIG. 1is a perspective view showing a semiconductor device according to a first embodiment. In addition,FIG. 2Ais a cross sectional view when a cut surface taken on line II-II ofFIG. 1is viewed in a direction indicated by an arrow andFIG. 2Bis a partial enlarged view ofFIG. 2A.

A semiconductor device according to the present embodiment has an n-type transistor1schematically configured to have a semiconductor substrate2, an element isolation region3, a fin4formed on the semiconductor substrate2, a gate electrode5formed so as to sandwich both side faces of the fin4via gate insulating films6, an expanded film7formed on the fin4, a cap layer8formed on the expanded film7, and offset spacers9formed on side faces of the gate electrode5.

For the semiconductor substrate2, it is possible to use, e.g., a Si substrate of which plane direction of the principal surface is {100}. Note that, {100} represents (100) and a plane direction equivalent to (100).

The element isolation region3is made of, e.g., an insulating material such as SiO2, etc., and has a STI (Shallow Trench Isolation) structure.

The fin4is formed by, e.g., shaping the semiconductor substrate2. In addition, the fin4includes n-type source and drain regions (not shown). A region in the fin4, which is surrounded by the gate electrode5and is sandwiched by the source region and the drain region, functions as a channel region.

The gate electrode5is made of, e.g., a Si-based polycrystalline such as polycrystalline Si or polycrystalline SiGe, etc., containing a conductivity type impurity. An n-type impurity such as As or P, etc., is used for the conductivity type impurity. Alternatively, the gate electrode5may be a metal gate electrode made of W, Ta, Ti, Hf, Zr, Ru, Pt, Ir, Mo or Al, etc., or a compound thereof, etc. Furthermore, the gate electrode5may have a laminated structure in which Si-based polycrystalline containing a conductivity type impurity is formed on the metal gate electrode. In addition, when an upper portion of the gate electrode5is made of a Si-based polycrystalline, a silicide layer may be formed on an upper surface thereof.

The gate insulating film6is made of, e.g., SiO2, SiN, SiON, or a high-k material (e.g., an Hf-based material such as HfSiON, HfSiO or HfO, etc., a Zr-based material such as ZrSiON, ZrSiO or ZrO, etc., and a Y-based material such as Y2O3, etc.).

The expanded film7is a film of which volume is expanded by applying a predetermined treatment to a precursor film. As a precursor film of the expanded film7, it is possible to use, e.g., a material having an oxidation rate faster than that of a crystal composing the fin4, and when the fin4is made of a Si crystal, it is possible to use a material having an oxidation rate faster than that of a Si crystal such as a Si1-xGex(0<x≦1) crystal (hereinafter referred to as a SiGe crystal). In this case, the volume of the SiGe crystal is expanded by applying oxidation treatment thereto, which results in that a SiGe oxide (mixture of Si oxide and Ge oxide) film as the expanded film7is formed.

As shown inFIG. 2B, the expanded film7applies a pushing force7fto peripheral members by the expansion thereof. As a result, the fin4receives a downward external force and a compressive strain in a height direction thereof is generated.

For example, when a plane direction of a channel region formed on the side face of the fin4is {110} and a direction of electrical current is <1-10>, it is possible to improve carrier (electron) mobility in the channel region by generating a compressive strain in a height direction (<001> direction) in the fin4. Note that, in case that a p-type transistor having the same structure as the n-type transistor1is fabricated instead of the n-type transistor1, according to the knowledge of the assignee, it is possible to improve carrier (hole) mobility in the channel region by generating a compressive strain in a height direction (<001> direction) in the fin4when a plane direction of the channel region formed on the side face of the fin4is {100} and a direction of electrical current is <010>. Note that, <110> represents [110] and a direction equivalent to [110].

The expanded film7is formed for generating a compressive strain in a height direction of the fin4in the channel region, and is formed on at least a portion of the fin4including the channel region (a region sandwiched by the gate electrode5). In order to generate a strain more effectively, it is preferable that the expanded film7is formed so as to cover the whole upper surface of the fin4as shown inFIG. 1.

The cap layer8is made of an insulating material such as SiN, etc. In addition, the cap layer8is preferably formed so as to cover the whole upper surface of the expanded film7. This is because an upward force7fgenerated from the expanded film7is received by the cap layer8without being diffused, and thus, a downward force7fis effectively transmitted to the fin4.

The offset spacer9is made of, e.g., SiO2or SiN, etc. Alternatively, gate sidewalls made of an insulating material may be formed on side faces of the offset spacers9. Note that, the offset spacer9also has a function of suppressing reduction of the external force to the fin4generated by the expansion of the expanded film7.

An example of a method of fabricating a semiconductor device according to the present embodiment will be described hereinafter.

FIGS. 3A to 3Fare perspective views showing processes for fabricating the semiconductor device according to the first embodiment.

Firstly, as shown inFIG. 3A, a first film10to be a precursor film of the expanded film7and a second film11to be shaped into the cap layer8are laminated on the semiconductor substrate2.

When a SiGe crystal film is formed as the first film10, the SiGe crystal film is formed by a vapor phase epitaxial growth under temperature conditions of 700-850° C. using monosilane (SiH4), dichlorosilane (SiH2Cl2) or trichlorosilane (SiHCl3), etc., as a raw material of Si and germanium hydride (GeH4) as a raw material of Ge in an atmosphere of hydrogen gas, etc. Meanwhile, when a SiN film is formed as the second film11, a CVD (Chemical Vapor Deposition), etc., is used.

Next, as shown inFIG. 3B, the second film11, the first film10and the semiconductor substrate2are patterned by, e.g., a photolithography method and RIE (Reactive Ion Etching), thereby forming the fin4which has the first film10and the cap layer8shaped from the second film11on an upper portion thereof.

Next, as shown inFIG. 3C, the element isolation region3is formed. After depositing an insulating film made of SiO2, etc., on the semiconductor substrate2by the CVD method, etc., so as to be higher than the height of the upper surface of the cap layer8, planarizing treatment such as CMP (Chemical Mechanical Polishing), etc., is applied to the insulating film using the upper surface of the cap layer8as a stopper, and the insulating film is further etched back by the RIE, etc., which results in that the element isolation region3is formed.

Next, as shown inFIG. 3D, the gate insulating film6is formed on the exposed side face of the fin4. For example, the gate insulating film6is formed by applying oxidation treatment to the side face of the fin4when using a SiO2film as the gate insulating film6, and is formed by applying nitriding treatment or oxynitriding treatment after applying the oxidation treatment on the side face of the fin4when using a SiON film. In addition, when a SiN film or a high-k material, etc., is used as the gate insulating film6, after depositing a SiN film or a high-k material film on the whole surface of the semiconductor substrate2by the CVD method, etc., the gate insulating film6may be formed by removing an unnecessary portion of such films.

Note that, since the side face of the first film10is also oxidized in the similar way when the oxidation treatment is applied to the side face of the fin4during the formation of the gate insulating film6, an oxidation rate of the first film10is desirably slower than that of Si. At this time, it is possible to reduce the degree of oxidation of the side face of the first film10by applying radical oxidation treatment using radical oxygen.

Next, as shown inFIG. 3E, the gate electrode5having a gate capping layer12on the upper surface thereof is formed.

The gate electrode5and the gate capping layer12are formed by, e.g., following processes. Firstly, after depositing a material film of the gate electrode5such as a polycrystalline Si film, etc., on the semiconductor substrate2using the CVD method, etc., the material film is planarized by the CMP, etc. Next, a material film of the gate capping layer12such as SiN or SiO2, etc., is deposited on the planarized material film of the gate electrode5. Next, the material film of the gate electrode5and the material film of the gate capping layer12are patterned using, e.g., the photolithography method and the RIE method, which results in that the gate electrode5and the gate capping layer12are formed.

Next, as shown inFIG. 3F, the oxidation treatment is applied to the first film10for expanding the volume thereof, which results in that the expanded film7is formed. For example, when the first film10is a SiGe crystal film, the expanded film7is a SiGe oxide film. At this time, since an expansion of a portion of the first film10of which periphery is surrounded by the gate electrode5is disturbed by the gate electrode5, a force7fapplied to peripheral members becomes particularly large. Therefore, although the expanded film7can be formed before forming the gate electrode5and after forming the cap layer8, a strain generated in the fin4becomes larger when the expanded film7is formed after forming the gate electrode5.

Note that, the fin4may be connected to a pad which is a connection region of a contact plug connected to a source region and a drain region in the fin4.FIGS. 4A and 4Bare partial enlarged views showing a periphery of a pad18formed at an end of the fin4each before and after the formation of the expanded film7in such cases.FIG. 4Cis a top view schematically showing a positional relation among the fin4, the pad18and the gate electrode5. Note that, when plural fins4are formed in parallel, the plural fins4may be connected to one pad.

The pad is, e.g., formed of the same material as and integrally with the fin4. Since a width of the upper surface of the pad18is larger than that of the fin4, only the first film10which is located on the fin4and the periphery of the pad18can be oxidized and processed into the expanded film7. Here, if the entire first film10becomes the expanded film7and expands, all members above the expanded film7are lifted upward when the oxidation treatment is applied to the first film10before forming the gate electrode5, the force7fapplied to the peripheral members is reduced. However, since the first film10located on the vicinity of the center of the upper surface of the pad18is not oxidized and does not expand, even when the expanded film7is formed before forming the gate electrode5, the reduction of the force7fapplied to the peripheral members by the expansion of the expanded film7can be suppressed, and it is thus possible to generate a strain in the fin4by the expanded film7.

Note that, when the first film10is a SiGe crystal film, since it is possible to increase the oxidation rate of the SiGe crystal by applying the oxidation treatment to the first film10using burning oxidation, it is possible to form the expanded film7while suppressing the oxidation that reaches the fin4made of a Si crystal, etc., low. Here, the burning oxidation is oxidation treatment using H2O which is produced by an oxidation of H2. Alternatively, in order to facilitate the progress of the oxidation reaction of the first film10, the oxidation treatment may be applied to the first film10after removing a portion of the cap layer8not covered by the gate electrode5. Furthermore, although it is preferable that a portion of the first film10of which periphery is surrounded by the gate electrode5is entirely oxidized for effectively generating a strain in the fin4, an unreacted region may be partially remained.

For example, a portion which is apart from the exposed surface of the Fin is less oxidized than a portion near to the exposed surface of the Fin. It may be possible that a portion above the channel in the Fin may be not oxidized, since the portion is apart from the exposed surface of the Fin.

After this, the offset spacers9are formed on the side face of the gate electrode5, the gate capping layer12is removed, and a source region and a drain region are formed in the fin4. In the source region and the drain region, for example, after forming source/drain extension regions by an ion implantation procedure, etc., using the offset spacers9as a mask, gate sidewalls are formed on the side faces of the offset spacers9, and deep source/drain regions are formed using the gate sidewalls as a mask. After that, a wiring, etc., is formed in an upper layer.

According to the first embodiment, it is possible to apply an external force to the channel region in the fin4by forming the expanded film7, thereby generating a compressive strain in a height direction of the fin4in the channel region. As a result, electron mobility in the channel region is improved, hence, an operating speed of the n-type transistor1is improved.

Second Embodiment

The second embodiment is different from the first embodiment in that an operating speed of a p-type transistor is improved. Note that, the explanation will be omitted for the points same as the first embodiment.

FIG. 5Ais a cross sectional view showing a semiconductor device according to a second embodiment. In addition,FIG. 5Bis a partial enlarged view ofFIG. 5A. Note that, the cross sections shown inFIGS. 5A and 5Bcorrespond to the cross sections of the semiconductor device according to the first embodiment shown inFIGS. 2A and 2B.

A semiconductor device according to the present embodiment has a p-type transistor20schematically configured to have a semiconductor substrate2, an element isolation region3, a fin4formed on the semiconductor substrate2, a gate electrode5formed so as to sandwich both side faces of the fin4via gate insulating films6, a shrink film13formed on the fin4, a cap layer8formed on the shrink film13, and offset spacers (not shown) formed on side faces of the gate electrode5.

The p-type transistor20has a structure in which the shrink film13is formed instead of the expanded film7in the n-type transistor1according to the first embodiment.

The gate electrode5is made of, e.g., a Si-based polycrystalline such as polycrystalline Si or polycrystalline SiGe, etc., containing a conductivity type impurity. A p-type impurity such as B or BF2, etc., is used for the conductivity type impurity. Alternatively, the gate electrode5may be a metal gate electrode made of W, Ta, Ti, Hf, Zr, Ru, Pt, Ir, Mo or Al, etc., or a compound thereof, etc. Furthermore, the gate electrode5may have a laminated structure in which Si-based polycrystalline containing a conductivity type impurity is formed on the metal gate electrode. In addition, when an upper portion of the gate electrode5is made of a Si-based polycrystalline, a silicide layer may be formed on an upper surface thereof.

The shrink film13is a film of which volume is shrunk by applying a predetermined treatment to a precursor film. For example, the volume is shrunk by applying heat treatment to an ozone TEOS film, which results in that a Si oxide film as the shrink film13is formed. Here, the ozone TEOS film is a SiO2film formed by the CVD method using O3(ozone) and TEOS as a raw material gas.

As shown inFIG. 5B, the shrink film13applies a pulling force13fto peripheral members by the shrinkage thereof. As a result, the fin4receives an upward external force and a tensile strain in a height direction thereof is generated.

For example, according to the knowledge of the assignee, it is possible to improve carrier (hole) mobility in the channel region by generating a tensile strain in a height direction (<001> direction) in the fin4when a plane direction of the channel region formed on the side face of the fin4is {110} and a direction of electrical current is <1-10>.

The shrink film13is formed for generating a tensile strain in a height direction of the fin4in the channel region in the fin4, and is formed on at least a portion of the fin4including the channel region (a region sandwiched by the gate electrode5). Particularly, in order to generate a strain more effectively, it is preferable that the shrink film13is formed so as to cover the whole upper surface of the fin4.

An example of a method of fabricating a semiconductor device according to the present embodiment will be described hereinafter.

Firstly, the processes until the process, shown inFIG. 3E, for forming the gate electrode5having the gate capping layer12on the upper surface thereof are carried out in the same way as the first embodiment. In this regard, however, a precursor film of the shrink film13is formed instead of the first film10in the first embodiment.

For example, when an ozone TEOS film is formed as a precursor film of the shrink film13, the ozone TEOS film is formed by the CVD method using an O3gas and a TEOS gas.

Next, volume of the precursor film of the shrink film13is shrunk by heat treatment, which results in that the shrink film13is formed. For example, when the precursor film of the shrink film13is an ozone TEOS film, the shrink film13is a Si oxide film. Subsequent processes are same as the first embodiment.

Note that, since a shrinkage of a portion of the precursor film of the shrink film13of which periphery is surrounded by the gate electrode5is disturbed by the gate electrode5, a force applied to peripheral members becomes particularly large. Therefore, similarly to the first embodiment, the shrink film13is preferably formed after forming the gate electrode5.

However, the shrinking process may be provided before forming the gate electrode5and after forming the cap layer8.

According to the second embodiment, it is possible to apply an external force to the channel region in the fin4by forming the shrink film13, thereby generating a tensile strain in a height direction of the fin4in the channel region. As a result, hole mobility in the channel region is improved, hence, an operating speed of the p-type transistor20is improved.

Third Embodiment

The third embodiment is different from the first embodiment in that expanded films are formed on and under the fin. Note that, the explanation will be omitted for the points same as the first embodiment.

FIG. 6Ais a cross sectional view showing a semiconductor device according to a third embodiment. In addition,FIG. 6Bis a partial enlarged view ofFIG. 6A. Note that, the cross sections shown inFIGS. 6A and 6Bcorrespond to the cross sections of the semiconductor device according to the first embodiment shown inFIGS. 2A and 2B.

A semiconductor device according to the present embodiment has an n-type transistor21schematically configured to have a semiconductor substrate2, an element isolation region3, a fin4formed on the semiconductor substrate2, a gate electrode5formed so as to sandwich both side faces of the fin14via gate insulating films6, expanded films7aand7bformed on and under the fin14, a cap layer8formed on the expanded film7a, and offset spacers (not shown) formed on side faces of the gate electrode5.

The expanded films7aand7bcan be formed by the same method using the same material as the expanded film7in the first embodiment.

As shown inFIG. 6B, the expanded films7aand7bapply a pushing force7fto peripheral members by the expansion thereof. As a result, the fin14receives a downward external force from the expanded film7aand an upward external force from the expanded film7b, and a compressive strain in a height direction thereof is generated.

The expanded film7ais formed for the purpose of generating a compressive strain in a height direction of the fin14in the channel region in the fin14, and is formed on at least a portion of the fin14including the channel region (a region sandwiched by the gate electrode5). In addition, the expanded film7bis formed under at least a portion of the fin14including the channel region (a region sandwiched by the gate electrode5) for the same reason. Particularly, in order to generate a strain more effectively, it is preferable that the expanded films7aand7bare formed so as to cover the whole upper and lower surfaces of the fin14.

An example of a method of fabricating a semiconductor device according to the present embodiment will be described hereinafter.

FIGS. 7A to 7Fare perspective views showing processes for fabricating the semiconductor device according to the third embodiment.

Firstly, as shown inFIG. 7A, a third film16to be a precursor film of the expanded film7b, a semiconductor film17to be shaped into a fin14, a first film10to be a precursor film of the expanded film7aand a second film11to be shaped into the cap layer8are laminated on the semiconductor substrate2.

Next, as shown inFIG. 7B, the second film11, the first film10, the semiconductor film17, the third film16and the semiconductor substrate2are patterned by, e.g., the photolithography method and the RIE, thereby forming the fin14having the first film10and the cap layer8on an upper portion thereof as well as the third film16under a lower portion thereof.

Next, as shown inFIG. 7C, the element isolation region3is formed. Here, the element isolation region3is formed to a height with which side faces of the third film16are not covered so as not to disturb the oxidation treatment to the third film16in a posterior process.

Next, as shown inFIG. 7D, a gate insulating film15is formed on the exposed side face of the fin14. Here, the gate insulating film15can be formed by the same method as the gate insulating film6in the first embodiment.

Next, as shown inFIG. 7E, the gate electrode5having the gate capping layer12on the upper surface thereof is formed.

Next, as shown inFIG. 7F, the oxidation treatment is selectively applied to the first film10and the third film16for expanding the volume thereof, which results in that the expanded films7aand7bare formed.

Note that, similarly to the fin4according to the first embodiment, the fin14may be connected to a pad (not shown) which is a connection region of a contact plug connected to a source region and a drain region in the fin14. In such cases, since a width of the upper surface of the pad contacting with the first film10and a width of the lower surface of the pad contacting with the third film16are larger than that of the fin14, only the first film10located on the fin14and on the periphery of the pad as well as the third film16located under the fin14and under the periphery of the pad can be oxidized and processed into the expanded films7aand7b. Here, if the entire first film10and the entire third film16expand and become the expanded films7aand7b, all members above the expanded films7aand7bare lifted upward when the oxidation treatment is applied to the first film10and the third film16before forming the gate electrode5, the force applied to the peripheral members is reduced. However, since the first film10located on the vicinity of the center of the upper surface of the pad and the third film16located under the vicinity of the center of the lower surface of the pad are not oxidized and do not expand, even when the expanded films7aand7bare formed before forming the gate electrode5, the reduction of the force applied to the peripheral members by the expansion of the expanded films7aand7bcan be suppressed, and it is thus possible to generate a strain in the fin14by the expanded films7aand7b.

Subsequent processes are same as the first embodiment.

According to the third embodiment, it is possible to apply the external force to the channel region in the fin14from upward and downward directions by each forming the expanded films7aand7bon and under the fin14. Therefore, a compressive strain in a height direction of the fin14generated in the channel region of the n-type transistor21in the present embodiment is larger than a compressive strain in a height direction of the fin4generated in the channel region of the n-type transistor1in the first embodiment, and it is thus possible to further improve the operating speed of the transistor.

In addition, according to the third embodiment, since the fin14is insulated from the semiconductor substrate2by the expanded film7b, it is not necessary to form a punchthrough stopper for suppressing source-drain leakage, thereby avoiding the increase in a channel impurity concentration. In other words, without using an expensive SOI substrate, it is possible to obtain the effect similar to the case of using the SOI substrate.

Alternatively, the n-type transistor21may be configured to form only the expanded film7bwithout forming the expanded film7a.

In such case, the expanding process may be provided after shaping the fin4and before forming the gate electrode5. Furthermore, the cap layer8may be not provided on the fin4.

In addition, it is possible to combine the present embodiment with the second embodiment. In detail, shrink films are formed on and under the fin14instead of forming the expanded films7aand7b, thus, a tensile strain in a height direction of the fin14can be generated in the channel region. As a result, hole mobility in the channel region is improved, hence, an operating speed of the p-type transistor is improved.

Fourth Embodiment

The fourth embodiment is different from the other embodiments in that a transistor has a tri-gate structure. Note that, the explanation will be omitted for the points same as the other embodiments.

FIG. 8Ais a cross sectional view showing a semiconductor device according to a fourth embodiment. In addition,FIG. 8Bis a partial enlarged view ofFIG. 8A. Note that, the cross sections shown inFIGS. 8A and 8Bcorrespond to the cross sections of the semiconductor device according to the first embodiment shown inFIGS. 2A and 2B.

A semiconductor device according to the present embodiment has an n-type transistor22schematically configured to have a semiconductor substrate2, an element isolation region3, a fin14formed on the semiconductor substrate2, a gate electrode5formed so as to sandwich both side faces of the fin14via gate insulating films19, expanded films7bformed under the fin14, and offset spacers (not shown) formed on side faces of the gate electrode5. The n-type transistor22has a tri-gate structure.

The gate insulating films19are formed on both side faces and an upper surface of the fin14. In the n-type transistor22, a region in the fin14in the vicinity of the both side faces and the upper surface of the fin14, which is surrounded by the gate electrode5and is sandwiched by the source region and the drain region, functions as a channel region.

As shown inFIG. 8B, the expanded films7bapply a pushing force7fto peripheral members by the expansion thereof. As a result, the fin14receives an upward external force from the expanded film7b, and a compressive strain in a height direction thereof is generated.

In addition, shrink films are formed under the fin14instead of forming the expanded films7b, thus, a tensile strain in a height direction of the fin14can be generated in the channel region. As a result, hole mobility in the channel region is improved, hence, an operating speed of the p-type transistor is improved.

According to the fourth embodiment, similarly to a transistor having a double-gate structure in the first to third embodiment, it is possible to improve an operating speed of a transistor having a tri-gate structure.

Other Embodiments

It should be noted that the present invention is not intended to be limited to the above-mentioned first to fourth embodiments, and the various kinds of changes thereof can be implemented by those skilled in the art without departing from the gist of the invention.

Furthermore, it is possible to arbitrarily combine the configurations of the above-mentioned first to fourth embodiments without departing from the gist of the invention.