High-speed and high-resolution signal analysis system

An apparatus relating generally to signal analysis is disclosed. In such an apparatus, a first comparator is coupled to receive a signal input and a first input level. A second comparator is coupled to receive the signal input and a second input level different from the first input level. A time-to-digital converter is coupled at a first port thereof, such as a start port for example, to receive a first output from the first comparator and coupled at a second port thereof, such as a stop port for example, to receive a second output from the second comparator. The time-to-digital converter is coupled to provide digital words representing the signal input.

FIELD OF THE INVENTION

The following description relates to integrated circuit devices (“ICs”). More particularly, the following description relates to a high-speed and high resolution signal analysis system for an IC.

BACKGROUND

For a high-performance data converter, such as a digital-to-analog converter (“DAC”) (e.g., at least a 12-bit DAC for operation at least at 1.0 Giga-samples per second (“GS/s”)), spectral purity of an output tone may be a consideration. Heretofore, a conventional high-performance spectrum analyzer was used to determine performance metrics of such a DAC, such as spurious free dynamic range (“SFDR”; i.e., a strength ratio of a fundamental signal to a strongest spurious signal in an output spectrum), among other performance metrics. For high-performance data converters, SFDR better than 80 dBc at low output tone frequencies and less than 60 dBc at high output tone frequencies (decibels relative to a carrier is a power ratio of a spurious signal to a carrier signal) may be obtained. This places challenging constraints on conventional signal analysis test equipment. Moreover, such test equipment conventionally may be expensive and bulky, as well as may be incompatible with a built-in self-test (“BIST”).

Hence, it is desirable and useful to provide signal analysis which overcomes or mitigates one or more of the above-identified limitations associated with conventional signal analysis test equipment.

SUMMARY

An apparatus relates generally to signal analysis. In such an apparatus, a first comparator is coupled to receive a signal input and a first input level. A second comparator is coupled to receive the signal input and a second input level different from the first input level. A time-to-digital converter is coupled at a first port thereof to receive a first output from the first comparator and coupled at a second port thereof to receive a second output from the second comparator. The time-to-digital converter is coupled to provide digital words representing the signal input.

A method relates generally to signal analysis. In such a method, a signal input is received by each of a first comparator and a second comparator. A first input level is coupled to the first comparator. A second input level is coupled to the second comparator different from the first input level. A first output of the first comparator transitions responsive to the signal input at least reaching the first input level, and a time-to-digital converter is started in response to the first output associated with such transitioning. A second output of the second comparator transitions responsive to the signal input at least reaching the second input level, and the time-to-digital converter is stopped in response to the second output associated with such transitioning. A digital word representing a time interval for the signal input is output from the time-to-digital converter. The time interval at least approximates a transition from the first input level to the second input level of the signal input.

A system relates generally to signal analysis. In such a system, a first comparator is coupled to receive a signal input and a first input level. A second comparator is coupled to receive the signal input and a second input level different from the first input level. The signal input is obtainable from a device under test. A time-to-digital converter is coupled at a first port thereof to receive a first output from the first comparator and coupled at a second port thereof to receive a second output from the second comparator. The time-to-digital converter is coupled to provide digital words representing the signal input. A data processing sub-system is configured to store and process the digital words for the signal analysis.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth to provide a more thorough description of the specific examples described herein. It should be apparent, however, to one skilled in the art, that one or more other examples and/or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative examples the items may be different.

Before describing the examples illustratively depicted in the several figures, a general introduction is provided to further understanding.

As devices get faster and smaller, having bulky and slow test equipment to characterize signals at a high-resolution becomes more problematic. However, as described below in additional detail, an in-system signal analysis platform may be used, where short channel devices are used to sample high-frequency signals at a high throughput or bandwidth while accuracy is provided with slower devices. Such accurate devices may be slow as compared to such short channel devices; however, multiple samples may be obtained at each of a multiplicity of levels, where such levels are accurately and incrementally provided by such slow but accurate devices to provide high-resolution. Along those lines for example, output of a device being tested may be processed for signal analysis, even though such output may be at a high frequency. Such high-frequency output may be processed to provide a high-resolution in either or both amplitude increments and/or time increments for signal analysis thereof. This may be used in place of expensive and bulky test equipment, and further may be used for real-time monitoring of a signal during operation.

With the above general understanding borne in mind, various configurations for signal analysis systems are generally described below.

FIG. 1is a block diagram depicting an exemplary signal analysis system100. Signal analysis system100includes a first comparator101, a second comparator102, a time-to-digital converter (“TDC”)103, and a data processing and storage die or dies (“data processing die”)104. In this example, data processing is performed by a programmed Field Programmable Gate Array (“FPGA”)105coupled to receive M-bit data words (“words”)113output from TDC103. Such words113may be stored in random access memory (“RAM”) or other memory106coupled to FPGA105, where FPGA105provides an interface to such memory106. However, in another configuration, a data processing die104may have sufficient on-chip memory so as to avoid having to use external memory106. In another configuration, signal analysis system100may be provided as a single monolithic die. In yet another configuration, a data processing die104may include TDC103. In still yet another configuration, comparators101and102, as well as TDC103may be provided as a data converter die coupled to data processing die104. Furthermore, multiple die may be coupled on an interposer or carrier to provide signal analysis system100. For purposes of clarity by way of example and not limitation, it shall be assumed that data processing die104is provided as an FPGA105and external memory106, where programmable resources of FPGA105are programmed to provide data processing in accordance with signal analysis as described herein, including without limitation spectral analysis. Along those lines, FPGA105may provide a high-resolution signal analysis output115generated using words113, as described below in additional detail.

A first comparator101is coupled to receive a signal input110and a first input level (“reference level”)111. For purposes of clarity by way of example and not limitation, it shall be assumed that reference level111is a reference voltage level and that signal input110is an analog input waveform (“input waveform”). A second comparator102is coupled to receive input waveform110and a second input level (“data level”)112. For purposes of clarity by way of example and not limitation, it shall be assumed that data level112is a positive voltage data level. However, in other configurations data level112may be a negative voltage data level. Furthermore, it shall be assumed that even though reference level111and/or data level112may be fixed or adjusted (“swept”), reference level111is a static level and data level112is swept. Generally, there is some difference or separation between levels111and112for generating data samples corresponding to different sampling points.

Optionally, comparator output121of comparator101may be coupled to a control input start port131of TDC103through a signal conditioning circuit107, and comparator output122of comparator102may be coupled to a control input stop port132of TDC103through a signal conditioning circuit108. Even though separate start and stop ports are used in this example, other configurations may use a single port, such as an enable/disable port for example. Thus, even though for example first and second ports may be described herein, such ports may be a same port. Optional signal conditioning circuits107and108may, for example, be used to buffer outputs or output signals121and122for driving starting and stopping of TDC103. However, for purposes of clarity and not limitation, it shall be assumed that outputs121and122are provided directly to start port131and stop port132, respectively.

TDC103is coupled to provide digital words113representing input waveform110to data processing die104. A storage device, such as memory106for example, may be coupled to FPGA105to store digital words113.

Suppose for example a device under test is a digital-to-analog converter (“DAC”), and signal analysis system100is to synthesize a repetitive waveform for input waveform110output from such DAC. TDC103may be started and stopped with respect to a reference level111and a data level112of such waveform. By adjusting at least one of levels111and112and repetitively sampling input waveform110, a digital representation of such input waveform may be obtained, such as may be stored as words114from words113in memory106generated from such repetitive sampling with sweeping or otherwise adjusting at least one reference level. In this example, FPGA105is programmed with a control module141and a data processing module142. Control module141may be configured to generate at least one control adjustment or increment signal125to adjust at least one of levels111and112. Data processing module142may be configured to perform a transform, such as for example a Fourier transform including without limitation a Fast Fourier Transform (“FFT”), a wavelet transform, and/or other known signal processing operations on such a digital representation. For example, a Fourier transform on a digital representation of a signal input may be used to identify a spur in such a signal input. An FFT and/or a special purpose filter may be used to identify a particular type of signal artifact, which may be for a data eye or a spur. Furthermore, data processing module142may include a processor, whether embedded or instantiated in programmable resources or a combination thereof, to perform statistical and other mathematical processing on such digital representation, including without limitation obtaining histograms or other distributions for repetitively sampling at set levels111and112.

Signal analysis system100may be compatible with ultra-deep sub-micron (“UDSM”) technology, where comparators101and102use UDSM short channel or gate transistors for fast switching times, namely for high bandwidth or throughput. However, amplitude resolution may be set by accuracy of an adjusted input level, such as described below in additional detail, and time resolution of TDC103. Along those lines, sub-picosecond temporal resolution in excess of 18 bit amplitude resolution may be provided in an implementation of signal analysis system100. A captured waveform may be further post-processed using spectral analysis techniques, and FPGA105may be programmed to carry out such spectral analysis. As such, signal analysis system100may provide on-die a combination of capabilities of a high-performance spectrum analyzer and an oscilloscope, such as a sampling oscilloscope for example. Furthermore, signal analysis system100may be used for built-in self-test (“BIST”) applications for high performance DACs, serializer-deserializers (“SerDes”) and input/outputs (“IOs”).

FIG. 2is the block diagram ofFIG. 1, but for differential signaling. WhereFIG. 1generally depicts single-ended signaling for input waveform110, levels111and112, and comparator outputs121and122,FIG. 2generally depicts each of those signals as differential signals. Along those lines, input waveform110includes a positive rail or signal110P and a negative rail or signal110N; level111includes a positive rail or signal111P and a negative rail or signal111N; and level112includes a positive rail or signal112P and a negative rail or signal112N. Likewise, comparator outputs121and122respectively include a positive rail or signal and a negative rail or signal. Many high-speed applications use differential signaling, and comparators101and102may be configured for high-speed signaling applications. Along those lines, signal conditioning circuits107and108may optionally be configured to convert comparator outputs121and122to corresponding single-ended signals221and222to respectively drive input to start port131and stop port132of TDC103.

InFIGS. 1 and 2, signal analysis system100may be used to generate a digital representation of a repetitive waveform or a repetitive glitch in a DC signal. For example, such a repetitive waveform may be generated by a DAC, a SerDes or an IO device, and a glitch in a DC signal may be generated by a power supply.

FIG. 3is a flow diagram depicting an exemplary digital representation generation flow300, such as may be used for signal analysis system100ofFIGS. 1 and 2. Accordingly, digital representation generation flow300is further described with simultaneous reference toFIGS. 1 through 3.

At301, a signal input110may be received by each of comparators101and102. At303, a reference level111may be coupled to comparator101. At or about the same time as the operation at303, at305a data level112may be coupled to comparator102.

At307, a transitioning of an output of comparator101occurs responsive to signal input110at least reaching reference level111. Such movement of signal input110may be in a positive or a negative direction, such as a positive voltage or negative voltage direction for example. Thus, by “at least reaching” it is generally meant attaining and/or surpassing a level in a direction associated with such level. Thus, for a positive level, “at least reaching” means going from below such positive level to at least equaling such positive level without having to preclude the possibility of surpassing such positive level, and, for a negative level, “at least reaching” means going from above such negative level to at least equaling such negative level without having to preclude the possibility of going lower than such negative level. At309, a TDC103is started in response to such comparator101output transitioning in response to at least reaching reference level111.

At311, a transitioning of an output of comparator102occurs responsive to signal input110at least reaching input level112. At313, TDC103is stopped in response to such comparator102output transitioning in response to at least reaching data level112.

At315, TDC103may output a digital word representing a time interval for signal input110. This time interval may at least approximate a transition from reference level111to data level112of such signal input110. Multiple digital words may be obtained for set levels111and112in order to obtain a statistically significant sampling. Thus, operations307through315may be repeated to obtain multiple words for a reference level111and a data level112respectively coupled at303and305. At317, output words from315may be counted until a statistically sufficient number has been output for set levels111and112, after which at least one of such levels111and/or112may be adjusted for sweeping to obtain other digital words for such one or more adjusted levels111and/or112.

At321, each word output from315may be stored in memory106, and so a plurality of digital words114may provide a digital representation of signal input110. At323, such a digital representation may be data processed, such as previously described for example. At325, information may be output, where such information is regarding such signal input110obtained from such data processing at323.

To provide further understanding,FIG. 4is a graphical diagram depicting an exemplary sampling flow400, which may be associated with some operations of digital representation generation flow300ofFIG. 3. Sampling flow400is further described with simultaneous reference toFIGS. 1 through 4.

Input waveform110, which in this example is a sine wave, though other waveforms or signals may be used, is applied to input ports, such as at301, of two wide bandwidth comparators101and102. Generally, at time T1, amplitude of input waveform110exceeds a reference level111, and so sampling by comparator101trips causing output thereof to transition from low to high starting TDC103. TDC103increments its internal count until time T2, when input waveform110exceeds an inspection reference level or data level112, causing sampling by comparator102to trip causing output thereof to transition from low to high. This transition of comparator102stops counting of TDC103. Such internal count of TDC103represents an interval of time401from starting to stopping of TDC103, which likewise represents an interval of time for input waveform110to go from reference level111to data level112. This interval of time401may be output from TDC103as an M-bit word113, and such M-bit word may be stored in memory106. At times T3 and T4, comparators102and101respectively transition from high to low outputs, so TDC103is not triggered in this example for internal counting. However, at time T5, sampling is repeated, and so the above-described process begins again. Accordingly, a repetitive waveform may be reconstructed by such repetitive sampling.

In accordance with the above description, a set of TDC output codes may be built up that correspond to transition times of a signal input between reference level111and data level112crossings. Along those lines, a table of data level versus TDC code can be generated and sorted, such as by FPGA fabric105, to yield a digital representation of signal input110. Because of repetition in and/or of signal input110, multiple samples may be taken with accurate, though comparatively slow, devices with respect to operating speeds of comparators101and102. Sigma-Delta DACs may be slower for higher resolution. In other words, multiple samples with respect to reference levels generated from accurate but slow systems, such as Sigma-Delta DACs, may be taken with high-speed comparators101and102.

Amplitude resolution may be set by accuracy of references for levels111and112. These levels may be generated from low-speed, high-resolution Sigma-Delta DACs or other suitable accurate amplitude level generation devices. However, temporal resolution may be determined by accuracy of TDC103, including a clock rate at which such TDC103is clocked by an internally generated clock signal thereof (not shown for purposes of clarity and not limitation). For example, 18-bit, low-speed Sigma-Delta DACs and TDCs with sub-picosecond resolution may be implemented in advanced CMOS processes. Comparators with small input switches may offer high bandwidth leveraging UDSM CMOS technology. Any offset in comparators101and102may lead to a constant offset in TDC code, and this offset may be calibrated out if desired.

High resolution in both in amplitude and time may be provided by signal analysis system100, where such system has wide bandwidth sampling of repetitive waveforms or signals in a UDSM compatible architecture. Additionally, a digital representation of an analog waveform may be provided. Transient dynamics of a signal input, such as glitches in output of a high-performance DAC for example, may be record events. Additionally, with post data processing, such as using an FPGA or other resource, spectral information may be obtained.

Along those lines,FIG. 5is a signal diagram depicting an exemplary low-to-high signal transition500of a signal input110. Such signal transition500includes a glitch or spur or transient501. In this example, such transition500occurs within the span of approximately 100 picoseconds (“ps”) along a horizontal time axis511. Furthermore, in this example such transition goes from approximately 0 micro-volts to an apex of approximately 60 micro-volts along a vertical voltage axis512. Along those lines, a transient of less than approximately 30 ps with a transient swing502of less than approximately 20 micro-volts may be resolved by an implementation of signal analysis system100. In this example, signal transition500is of a 14-bit high-performance DAC output having glitch energy represented by glitch501; however, other signal transitions may have glitches for resolution by an implementation of signal analysis system100.

FIG. 6is a block diagram depicting a signal analysis system600. Signal analysis system600generally includes two data acquisition portions, namely two instances of portions of signal analysis system100, and these two data acquisition portions are operated in parallel though coupled to receive a common signal input110.

In this example, same components of signal analysis system have same reference numbers with the addition of either a P for positive or an N for negative for comparators and TDCs, as well as associated signals. Along those lines, a positive data acquisition portion650, which includes comparators101P,102P, and TDC103P coupled as previously described, receives a positive reference level111P, a positive data level112P, and a signal input110to provide words113P, where words113P are to provide a digital representation of a positive voltage portion of signal input110. Words113P are provided as an input to FPGA105, such as previously described.

Likewise, a negative data acquisition portion651, which includes comparators101N,102N, and TDC103N coupled as previously described, receives a negative reference level111N, a negative data level112N, and a signal input110to provide words113N, where words113N are to provide a digital representation of a negative voltage portion of signal input110. Words113N are provided as another input to FPGA105, such as previously described.

Data acquisition sub-systems or portions650and651may be operated in parallel for processing a common signal input110between them. TDC103P may be used to measure or determine positive level crossings of a D+ data level112P of signal input110for a REF+ reference level111P using TDC counts provided in words113P. Likewise, TDC103N may be used to measure or determine negative level crossings of a D− data level112N of signal input110for a REF− reference level111N using TDC counts provided in words113N.

In this example, signal input110is an output of a high-performance N-bit DAC603, which produces a repetitive waveform for signal input110in response to an N-bit digital input613. In other examples, any other repetitive signal source may be used for signal input110.

In this example, reference levels111P and111N are respectively generated by Sigma-Delta DACs601and604. Reference levels111P and111N may be independently set by independently programming Sigma-Delta DACs601and604. In this example, each of Sigma-Delta DACs601and604receive an (N+3)-bit digital input, namely digital inputs611and614, respectively. Thus, in this example, each of Sigma-Delta DACs601and604may have 3 bits more resolution than a DAC603under test or other device under test (“DUT”).

These three extra bits may provide up to 8 (i.e., 2^3) amplitude quantization levels over a least significant bit (“LSB”) transition. Such LSBs may be of DAC603. This precision is somewhat arbitrary, and may be specified on an application-by-application basis. Thus, three, fewer than three, or more than three extra bits may be used for generating quantization levels. More than eight quantization levels may be used to provide higher resolution spectrum analysis. In some applications, not all N-bits input are used, but rather a subset, such as a set of most significant bits (“MSBs”) are used, and in those applications quantization levels may be generated with N-bit or less than N-bit inputs to DACs601and604. However, for purposes of clarity by way of example and not limitation, it shall be assumed that eight quantization levels are generated.

In this example, data levels112P and112N are respectively generated by Sigma-Delta DACs602and605. Data levels may, though need not be, opposites of one another. Data levels112P and112N may be independently set by independently programming Sigma-Delta DACs602and605. In this example, each of Sigma-Delta DACs602and605receive an (N+3)-bit digital input, namely digital inputs612and615, respectively. Thus, in this example, each of Sigma-Delta DACs602and605may have 3 bits more resolution than a DAC603under test or other DUT.

For purposes of clarity, it shall be assumed that both data and reference level DACs all have the same input bit widths for generating same numbers of quantization levels for positive and negative portions of a signal input110. However, in other configurations, the number of quantization levels for positive and negative portions of a signal input110may be different. Thus, digital input611bit width may be any of equal to, greater than, or less than bit width of digital input614. Likewise, digital input612bit width may be any of equal to, greater than, or less than bit width of digital input615. However, generally, input bit widths of digital inputs611and612may be equivalent in number, and input bit widths of digital inputs614and615may likewise be equivalent in number.

For purposes of clarity by way of example and not limitation, suppose a 16-bit DAC operating at high-speed (i.e., greater than 1.5 GS/s) is DAC603, reference levels may be readily produced by low-speed (i.e., less than 1 GS/s) 19-bit Sigma-Delta DACs601,602,603, and604for signal analysis of a repetitive waveform output from DAC603. An update rate of code (i.e., change in amplitude) of Sigma-Delta DACs is slow in comparison to frequency of a signal output from DAC603, such as a sine wave having a frequency at or in excess of a Giga-hertz (“GHz”). So though a reference level and/or a data level may be changed slowly, such as for sweeping, this changing may be at slower rate due to repetition of a waveform output from a DUT, because many samples may be taken at each set of reference level settings. Through statistical data processing of such samples, such as for example determining an average, throwing out excessively high and low samples, generating data histograms, and/or other statistical data processing, a high-resolution digital representation of a signal may be generated for signal analysis, including without limitation spectral analysis. Effectively, high-frequency analog signals may be characterized using high-speed (short gate) comparators with slow changing of input levels by having multiple samples and a repetitive waveform. Along those lines, a sufficiently complete resolution (“complete picture”) for a digital representation may be generated with a sufficient number of samples at each set of input levels with sweeping of D+ and D− data levels for example. In short, accuracy may be obtained with Sigma-Delta DACs and bandwidth may be obtained with short-channel transistor comparators.

Along the above lines, high bandwidth repetitive analog signals may be measured using circuits compatible with UDSM CMOS processes, where such signals may be measured with greater than 18-bit amplitude and less than 1 ps temporal resolution. In other configurations, Sigma-Delta DAC references may be replaced with any other high precision adjustable reference. Furthermore, though a DAC is described as a DUT, such DUT may be replaced with any repetitive signal source. Along those lines, SerDes data eye openings may be measured for example.

As described, instantiation of TDCs and Sigma-Delta DACs may be in an ASIC along with an FPGA, or such TDC may be instantiated in FPGA fabric, or Sigma Delta DAC cores could be instantiated in FPGA fabric but filters therefor may be in an ASIC, or some other combination hereof. In another configuration, IO devices may be used as comparators in a low-end implementation, with a DUT output looped back through a PCB to an IO comparator. Programming information, such as a configuration bitstream for FPGA, may be used to control sweeping and post processing of data, and programmable resources programmed may be overwritten following a BIST process. Over-writing a programmed configuration bitstream may be particularly useful to protect from reverse engineering if TDC and Sigma-Delta DAC cores are instantiated in FPGA fabric. For FPGAs or other SoCs that have arrays of DACs, DACs other than a unit under test, may be multiplexed to provide input levels to further protect against reverse engineering.

FIG. 7is a signal diagram depicting an exemplary high-resolution digital representation of a sine wave signal input, for a signal input110, after processing with TDCs103P and103N of signal analysis system600ofFIG. 6.FIG. 8is a signal diagram depicting an exemplary sweeping of a data level, such as data level112P for example, for signal processing by signal analysis system600ofFIG. 6. With simultaneous reference toFIGS. 6 through 8,FIGS. 7 and 8are further described.

High-resolution signal analysis output115is a digital representation of an analog signal input110, where each reference D, namely data levels112P and112N, may be adjusted over multiple levels802to stop corresponding TDCs, namely TDCs103P and103N, at a different points in time. In this example, there are eight levels802; however, in other configurations fewer or more than eight levels may be used. Furthermore, in this example, adjusting of a data level goes from low to high, as generally indicated by arrow801, however, in other examples data level may be swept from high to low.

For purposes of clarity by way of example and not limitation, suppose data level112P is slowly swept relative to acquisition rate of signal analysis system100, then multiple samples may be taken at each of levels802for a data level transition800. In this example, at approximately time711, a reference level111P may be crossed by a signal input110to start a TDC103P counting, and at approximately time712, a data level112P may be crossed by such a signal input110to stop TDC103P's counting, which effectively may register a TDC interval701for a positive transition interval or portion of data of such a signal input. In this example, at approximately time713, a reference level111N may be crossed by such a signal input110to start a TDC103N counting, and at approximately time714, a data level112N may be crossed by such a signal input110to stop TDC103N's counting, which effectively may register TDC interval702for a negative transition interval or portion of data on such a signal input.

For this example, a DAC DUT may have an edge transition from one code to the next which may occur over approximately 100 ps. Each of such TDCs may have approximately a 1 to 10 ps resolution for such an application. For example for a 100 MHz output tone for signal input110, approximately 1 k to 10 k samples per period may be taken. For a 16-bit TDC output code or code word, on-chip memory in an FPGA105may be exclusively used for such storage to avoid having to implement memory106for such storage. If, however, a larger data set is used, for example such as by using coherently excited tones for signal input110, off-chip storage in high-speed memory106may be used. As data is acquired, it may be effectively stored in a memory stack in internal FPGA memory or external memory coupled to an FPGA. Each element of such a memory stack may include a reference code and a TDC value, which effectively may be amplitude versus time data sets. To generate more familiar time versus amplitude data sets, an insertion sort algorithm or other sorting algorithm can be applied for stack reordering of TDC codes in sequence.

Scan acquisition time may be limited by filter bandwidth in Sigma-Delta DACs601,602,604, and/or605. For example, an update rate of approximately 10 microseconds per code may be used for a scan on approximately a 100 MHz tone with approximately a 10 picosecond resolution, and such scan time may take approximately 10 milliseconds. If averaging is used, then scan time may grow linearly with the number of data sets used for such averaging. This is just one example for purposes of clarity by way of example, and various other configurations and values associated therewith may be used.

FIG. 9is the block diagram ofFIG. 6, though for differential signaling. In this example, TDCs103P and103N are configured to receive differential inputs at start and stop ports respectively thereof. Accordingly, comparators101P and102P, as well as comparators101N and102N, are respective sets of differential comparators. Additionally, DUT DAC603, as well as DACs601,602,604, and605, are respective differential DACs. Even though processing of differential signaling is described, it should be understood that each rail of a differential signal may be individually analyzed by treating each rail as a single-ended signal, as described elsewhere herein. Again, signal input is not limited to an analog signal or a sine wave, as any repetitive signal or signal with a repetition may be used. For example, a clock signal, single-ended or differential, may be used for signal input110. Furthermore, a power supply or other DC voltage with a reoccurring glitch may be used for signal input110.

Additionally, signal input110need not be a repetitive signal or a signal with a repetitive event, as by taking multiple samples for TDC outputs, a maximum and/or minimum amplitude, such as of a glitch or spur, may be determined for parameter, in contrast to waveform, determination. Along those lines, time between events or zero crossing may be determined in order to measure duty cycle and/or jitter in a signal. Such determination of a glitch or jitter may be used to set a threshold, where if such threshold is exceeded, an alarm may be initiated indicating a degradation in advance of a failure. Furthermore, such an alarm may be initiated to indicate that tampering may have been detected. As an FPGA may be coupled for remote monitoring, signal status may be remotely monitored.

Accordingly, high-resolution signal analysis may be performed, such as by a programmed FPGA, as described herein. Such signal analysis may include high-resolution spectral analysis. Effectively, an FPGA may be programmed to provide a high-resolution spectral analyzer, and thus may be coupled to a monitor or other display device (not shown) for such purpose. Furthermore, in an implementation, a system may be controlled from an FPGA for post processing data (e.g., generate FFTs and other signal analysis) to determine performance metrics, such as data converter linearity (SFDR) and/or SerDes bit error rates (i.e., eye openings), among other forms of data processing. This ability to synthesize an entire architecture within FPGA fabric, and possibly with a few external filtering components on a PCB and/or interposer as described herein, may be used in BIST of data converters coupled to FPGA fabric, including is Stacked Silicon Interposer Technology (“SSIT”) among other forms of stacked dies.

Because one or more of the examples described herein may be implemented in an FPGA, a detailed description of such an IC is provided. However, it should be understood that other types of ICs may benefit from the technology described herein.

Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.

Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.

As noted above, advanced FPGAs can include several different types of programmable logic blocks in the array. For example,FIG. 10illustrates an FPGA architecture1000that includes a large number of different programmable tiles including multi-gigabit transceivers (“MGTs”)1001, configurable logic blocks (“CLBs”)1002, random access memory blocks (“BRAMs”)1003, input/output blocks (“IOBs”)1004, configuration and clocking logic (“CONFIG/CLOCKS”)1005, digital signal processing blocks (“DSPs”)1006, specialized input/output blocks (“I/O”)1007(e.g., configuration ports and clock ports), and other programmable logic1008such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (“PROC”)1010.

For example, a CLB1002can include a configurable logic element (“CLE”)1012that can be programmed to implement user logic plus a single programmable interconnect element (“INT”)1011. A BRAM1003can include a BRAM logic element (“BRL”)1013in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile1006can include a DSP logic element (“DSPL”)1014in addition to an appropriate number of programmable interconnect elements. An IOB1004can include, for example, two instances of an input/output logic element (“IOL”)1015in addition to one instance of the programmable interconnect element1011. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element1015typically are not confined to the area of the input/output logic element1015.

Some FPGAs utilizing the architecture illustrated inFIG. 10include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, processor block1010spans several columns of CLBs and BRAMs.

While the foregoing describes exemplary apparatus(es) and/or method(s), other and further examples in accordance with the one or more aspects described herein may be devised without departing from the scope hereof, which is determined by the claims that follow and equivalents thereof. Claims listing steps do not imply any order of the steps. Trademarks are the property of their respective owners.