Embodiments herein may describe techniques for an integrated circuit including a FinFET transistor to be used as an antifuse element having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed. A FinFET transistor may include a source electrode in contact with a source area, a drain electrode in contact with a drain area, a fin area including silicon and between the source area and the drain area, and a gate electrode above the fin area and above the substrate. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. Other embodiments may be described and/or claimed.

FIELD

Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to antifuse elements and memory arrays.

BACKGROUND

An integrated circuit (IC) may include many components, e.g., transistors, resistors, capacitors, diodes, formed on a semiconductor substrate. In addition, ICs may often include one or more types of memory arrays formed by multiple memory cells, such as a CMOS memory array including multiple memory cells, an antifuse memory array including multiple antifuse elements, or a fuse memory array including multiple fuse elements. In electronics and electrical engineering, a fuse element may be an electrical safety device that operates to provide overcurrent protection of an electrical circuit. Normally, a fuse element may include a copper wire, strip, or interconnect, which may melt or break down when too much current flows through it, thereby interrupting the current. A fuse element with a copper wire may melt at a high current, and may create a void space in the fuse element after the copper wire has been melted, which may post security risks. In addition, a fuse memory array including multiple fuse elements with copper wire may occupy a large area.

DETAILED DESCRIPTION

A fuse element may be an electrical safety device that operates to provide overcurrent protection of an electrical circuit. Conventionally, a fuse element may include a copper interconnect. A copper interconnect of a fuse element may melt at a high current, e.g., around 10 milliamps (mA) to 30 mA, when a high voltage, e.g., 5 voltage, is applied to the fuse element. After the copper interconnect of the fuse element has been melted, the fuse element may include a void space that was occupied by the copper interconnect before it has been melted. Such a void space may be detectable by top-down imaging techniques, hence making the fuse element vulnerable for security reasons. In addition, a fuse memory array including multiple fuse elements having copper interconnects may occupy a large area.

An antifuse element may be an electrical device that performs operations opposite to a fuse element. Whereas a fuse element starts with a low resistance and may permanently break an electrically conductive path (typically when the current through the path exceeds a specified limit), an antifuse element starts with a high resistance and may permanently create an electrically conductive path (typically when the voltage across the antifuse element exceeds a certain level). A memory array may be formed by including multiple antifuse elements, or multiple fuse elements.

Embodiments herein may present an antifuse element including a FinFET transistor having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed. A first resistance may exist between the source electrode, the fin area, and the drain electrode. A second resistance may exist between the source electrode and the drain electrode, and the path through the fin area to couple the source electrode and the drain electrode. The first resistance may be about 102 to 104 times larger than the second resistance. The two different resistances may be used to represent a digital 0 and a digital 1 respectively. After a programming operation is performed on the FinFET transistor to form a path through a fin area to couple a source electrode and a drain electrode, no void space is created within the FinFET transistor. Therefore an antifuse element including the FinFET transistor may be safer compared to a fuse element including a copper interconnect.

Embodiments herein may present an integrated circuit (IC) including a source electrode in contact with a source area on a substrate, a drain electrode in contact with a drain area on the substrate, a fin area including silicon and between the source area and the drain area, and a gate electrode above the fin area and above the substrate. The source area, the fin area, the gate electrode, and the drain area form a FinFET transistor. A first resistance may exist between the source electrode, the fin area, and the drain electrode. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. A second resistance may exist between the source electrode and the drain electrode, and the path through the fin area to couple the source electrode and the drain electrode.

Embodiments herein may present a method for forming an IC. The method may include: forming a source area on a substrate, a drain area on the substrate, and a fin area including silicon and between the source area and the drain area. The method may also include forming a source electrode in contact with the source area, forming a drain electrode in contact with the drain area, and forming a gate electrode above the fin area and above the substrate. The source area, the fin area, the gate electrode, and the drain area may form a FinFET transistor, and a first resistance may exist between the source electrode, the fin area, and the drain electrode. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. A second resistance may exist between the source electrode and the drain electrode, and the path through the fin area to couple the source electrode and the drain electrode.

Embodiments herein may present a computing device including a circuit board and an antifuse memory array coupled to the circuit board. The antifuse memory array may include a plurality of antifuse cells. An antifuse cell of the plurality of antifuse cells may include an antifuse element and a selector. An antifuse element may include a source electrode in contact with a source area on a substrate, a drain electrode in contact with a drain area on the substrate, a fin area including silicon and between the source area and the drain area, and a gate electrode above the fin area and above the substrate. The source area, the fin area, the gate electrode, and the drain area may form a FinFET transistor. A first resistance may exist between the source electrode, the fin area, and the drain electrode. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. A second resistance may exist between the source electrode and the drain electrode, and the path through the fin area to couple the source electrode and the drain electrode. The source electrode may be coupled to a bit line of the antifuse memory array, and the drain electrode may be coupled to a first contact of the selector. The selector may further include a second contact coupled to a word line of the antifuse memory array.

In various embodiments, the phrase “a first feature formed, deposited, or otherwise disposed on a second feature” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

As used herein, the term “circuitry” may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. As used herein, “computer-implemented method” may refer to any method executed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet, a laptop computer, a set-top box, a gaming console, and so forth.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the disclosure, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonplanar transistors.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

In some implementations of the disclosure, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

FIGS. 1(a)-1(c)schematically illustrate diagrams, in three-dimensional view or in cross sectional view, of a FinFET transistor100to be used as an antifuse element having a path175through a fin area105to couple a source electrode113and a drain electrode117after a programming operation is performed, in accordance with some embodiments. For clarity, features of the FinFET transistor100, the fin area105, the source electrode113, the drain electrode117, and the path175may be described below as examples for understanding an example FinFET transistor, a fin area, a source electrode, a drain electrode, and a path. It is to be understood that there may be more or fewer components within a FinFET transistor, a fin area, a source electrode, a drain electrode, and a path. Further, it is to be understood that one or more of the components within a FinFET transistor, a fin area, a source electrode, a drain electrode, and a path may include additional and/or varying features from the description below, and may include any device that one having ordinary skill in the art would consider and/or refer to as a FinFET transistor, a fin area, a source electrode, a drain electrode, and a path.

In embodiments, as shown inFIG. 1(a), the FinFET transistor100may be a PMOS FinFET or a NMOS FinFET. The FinFET transistor100may include a substrate101, a source area103on a substrate, a drain area107on the substrate, and the fin area105including silicon and between the source area103and the drain area107on the substrate101. The substrate101may be a bulk substrate or a silicon-on-insulator (SOI) substrate. A gate electrode115may be above the fin area105and above the substrate101. The source electrode113may be in contact with the source area103. The drain electrode117may be in contact with the drain area107. The source electrode113, the gate electrode115, or the drain electrode117may include germanium (Ge), cobalt (Co), titanium (Ti), tungsten (W), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, W, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.

In embodiments, as shown inFIG. 1(b), a first resistance102may exist between the source electrode113, the fin area105and the drain electrode117. The resistance102represented by a symbol may be a symbolic view to show a resistance, not a real physical component.

In embodiments, as shown inFIG. 1(c), after a programming voltage111may be applied between the source electrode113and the drain electrode117to generate a current112flowing between the source electrode113and the drain electrode117, the path175may be formed through the fin area105to couple the source electrode113and the drain electrode117. The programming operation may be performed when the FinFET transistor100is in an on-state having a voltage between the gate electrode115and the source electrode113larger than a threshold voltage, or when the FinFET transistor100is in an off-state having a voltage between the gate electrode115and the source electrode113less than the threshold voltage. The path175may be a permanent conductive path that exists after the programming voltage111is removed. The path175may include a material migrated from the source electrode113or the drain electrode117, or amorphous silicon. A second resistance104may exist between the source electrode113, the drain electrode117, and the path175through the fin area105. The first resistance102may be about 102 to 104 times larger than the second resistance104.

In embodiments, the first resistance102and the second resistance104of the FinFET transistor100may represent a digital 0 and a digital 1, or a digital 1 and a digital 0, respectively. The FinFET transistor100may be programmed to be 0 or 1, without creating a void space within the FinFET transistor100. Hence, the FinFET transistor100may be more secure than a fuse element including a copper interconnect, which may leave a void space once the copper interconnect is melted after a programming voltage is applied to the fuse element. The FinFET transistor100may be used to store security keys on-die, and its stored content may not be able to be discovered by imaging inspection of the void spaces contained in the FinFET transistor100.

FIGS. 2(a)-2(b)schematically illustrate diagrams of FinFET transistors, e.g., a PMOS FinFET transistor210, or a NMOS FinFET transistor220, to be used as an antifuse element having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed when the FinFET transistor is in an off-state, in accordance with some embodiments. In embodiments, the PMOS FinFET transistor210, or the NMOS FinFET transistor220may be an example of the FinFET transistor100shown inFIG. 1.

In embodiments, the PMOS FinFET transistor210may include a gate electrode215, a source electrode213, and a drain source electrode217. The gate electrode215may be coupled to the source electrode213, so that the voltage between the gate electrode215and the source electrode213may be zero, which may be less than the threshold voltage for the PMOS FinFET transistor210. Hence, the PMOS FinFET transistor210is in an off-state. A programming voltage for the PMOS FinFET transistor210may be applied between the source electrode213and the drain electrode217to generate a current flowing between the source electrode213and the drain electrode217. The programming voltage may be less than 3V, and the current may be less than 100 microamperes (μA). A path275may be formed through a fin area, not shown, to couple the source electrode213and the drain electrode217.

In embodiments, the NMOS FinFET transistor220may include a gate electrode225, a source electrode223, and a drain electrode227. The gate electrode225may be coupled to the source electrode223, so that the voltage between the gate electrode225and the source electrode223may be zero, which may be less than the threshold voltage for the NMOS FinFET transistor220. Hence, the NMOS FinFET transistor220may be in an off-state. A programming voltage for the NMOS FinFET transistor220may be applied between the source electrode223and the drain electrode227to generate a current flowing between the source electrode223and the drain electrode227. The programming voltage may be less than 3V, and the current may be less than 100 μA. A path285may be formed through a fin area, not shown, to couple the source electrode223and the drain electrode227.

FIGS. 3(a)-3(d)schematically illustrate diagrams of FinFET transistors, a PMOS FinFET transistor310, or a NMOS FinFET transistor320, to be used as an antifuse element having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed when the FinFET transistor is in an on-state, and its sense and standby operations, in accordance with some embodiments. In embodiments, the PMOS FinFET transistor310, or the NMOS FinFET transistor320, may be an example of the FinFET transistor100shown inFIG. 1.

In embodiments, as shown inFIG. 3(a), the PMOS FinFET transistor310may include a gate electrode315, a source electrode313, and a drain electrode317. A programming operation may be performed when the gate electrode315may be held low to have the PMOS FinFET transistor310in an on-state. A voltage between the gate electrode315and the source electrode313may be larger than a threshold voltage so that the PMOS FinFET transistor310is in an on-state. A programming voltage for the PMOS FinFET transistor310may be applied between the source electrode313and the drain electrode317to generate a current flowing between the source electrode313and the drain electrode317. The programming voltage may be less than 2V, and the current may be less than 200 μA. A path375may be formed through a fin area, not shown, to couple the source electrode313and the drain electrode317.

In embodiments, as shown inFIG. 3(b), the gate electrode315may be held high to have the PMOS FinFET transistor310in an off-state. The resistance between the source electrode313and the drain electrode317may be sensed to read the digital content represented by the resistance. In addition, the gate electrode315may be held high to have the PMOS FinFET transistor310in an off-state during a standby operation.

In embodiments, as shown inFIG. 3(c), the NMOS FinFET transistor320may include a gate electrode325, a source electrode323, and a drain electrode327. A programming operation may be performed when the gate electrode325may be held high to have the NMOS FinFET transistor320in an on-state. A voltage between the gate electrode325and the source electrode323may be larger than a threshold voltage so that the NMOS FinFET transistor320is in an on-state. A programming voltage for the NMOS FinFET transistor320may be applied between the source electrode323and the drain electrode327to generate a current flowing between the source electrode323and the drain electrode327. The programming voltage may be less than 2V, and the current may be less than 200 μA. A path385may be formed through a fin area, not shown, to couple the source electrode323and the drain electrode327.

In embodiments, as shown inFIG. 3(d), the gate electrode325may be held low to have the NMOS FinFET transistor320in an off-state. The resistance between the source electrode323and the drain electrode327may be sensed to read the digital content represented by the resistance. In addition, the gate electrode325may be held low to have the NMOS FinFET transistor320in an off-state during a standby operation.

FIG. 4schematically illustrates a process400for forming a FinFET transistor to be used as an antifuse element by having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed, in accordance with some embodiments. In embodiments, the process400may be applied to form the FinFET transistor100inFIG. 1, the PMOS FinFET transistor210, the NMOS FinFET transistor220, inFIG. 2, the PMOS FinFET transistor310, or the NMOS FinFET transistor320inFIG. 3.

At block401, the process400may include forming a source area on a substrate, a drain area on the substrate, and a fin area including silicon and between the source area and the drain area. For example, the process400may include forming the source area103on the substrate101, the drain area107on the substrate101, and the fin area105including silicon and between the source area103and the drain area107, as shown inFIG. 1.

At block403, the process400may include forming a source electrode in contact with the source area. For example, the process400may include forming the source electrode113in contact with the source area103, as shown inFIG. 1.

At block405, the process400may include forming a drain electrode in contact with the drain area. For example, the process400may include forming the drain electrode117in contact with the drain area107, as shown inFIG. 1.

At block407, the process400may include forming a gate electrode above the fin area and above the substrate. The source area, the fin area, the gate electrode, and the drain area form a FinFET transistor. A first resistance may exist between the source electrode, the fin area, and the drain electrode. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. A second resistance may exist between the source electrode and the drain electrode, and the path through the fin area to couple the source electrode and the drain electrode. For example, the process400may include forming the gate electrode115above the fin area105and above the substrate101. The source area103, the fin area105, the gate electrode115, and the drain area107form the FinFET transistor100. A first resistance102may exist between the source electrode113, the fin area105, and the drain electrode117. After a programming operation is performed to apply a programming voltage between the source electrode113and the drain electrode117to generate a current between the source electrode113, the fin area105, and the drain electrode117, the path175may be formed through the fin area105to couple the source electrode113and the drain electrode117. A second resistance104may exist between the source electrode113and the drain electrode117, and the path175through the fin area105to couple the source electrode113and the drain electrode117.

In addition, the process400may include additional operations to form other layers, e.g., ILD layers, or encapsulation layers, insulation layers, not shown. In some embodiments, the various blocks, e.g., the block401, the block403, the block405, and the block407, may not be ordered as shown inFIG. 4. Various blocks of the process400may be performed in an order different from the one shown inFIG. 4.

FIG. 5schematically illustrates an antifuse memory array500with multiple antifuse cells, e.g., an antifuse cell502, an antifuse cell504, an antifuse cell506, and an antifuse cell508, where an antifuse cell includes an antifuse element having a FinFET transistor including a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed, in accordance with some embodiments. For example, the antifuse cell502includes an antifuse element512, the antifuse cell504includes an antifuse element522, the antifuse cell506includes an antifuse element532, and the antifuse cell508includes an antifuse element542. In embodiments, the antifuse element512, the antifuse element522, the antifuse element532, and the antifuse element542may be similar to the FinFET transistor100inFIG. 1, the PMOS FinFET transistor210, the NMOS FinFET transistor220inFIG. 2, or a FinFET transistor to be used as an antifuse element formed following the process400. In embodiments, the multiple antifuse cells may be arranged in a number of rows and columns coupled by bit lines, e.g., bit line B1and bit line B2, and word lines, e.g., word line W1and word line W2.

On the other hand, the PMOS FinFET transistor310and the NMOS FinFET transistor320may be used in an antifuse memory array different from the antifuse memory array500because the PMOS FinFET transistor310and the NMOS FinFET transistor320may be programed when the PMOS FinFET transistor310or the NMOS FinFET transistor320is in an on-state, and three signal lines may be used to control the PMOS FinFET transistor310or the NMOS FinFET transistor320.

An antifuse cell, e.g., the antifuse cell502, may be coupled in series with other antifuse cells, e.g., the antifuse cell504, of the same row, and may be coupled in parallel with the antifuse cells of other rows, e.g., the antifuse cell506and the antifuse cell508. The antifuse memory array500may include any suitable number of one or more antifuse cells. Although the antifuse memory array500is shown inFIG. 5with two rows that each includes two antifuse cells coupled in series, other embodiments may include other numbers of rows and/or numbers of antifuse cells within a row. In some embodiments, the number of rows may be different from the number of columns in an antifuse memory array. Each row of the antifuse memory array may have a same number of antifuse cells. Additionally, or alternatively, different rows may have different numbers of antifuse cells.

In embodiments, multiple antifuse cells, such as the antifuse cell502, the antifuse cell504, the antifuse cell506, and the antifuse cell508, may have a similar configuration. For example, the antifuse cell502may include a selector514and the antifuse element512. The antifuse cell502may be controlled through the selector514coupled to a bit line and a word line to read from the antifuse cell, write to the antifuse cell, and/or perform other memory operations. For example, the selector514may have an electrode501coupled to the word line W1, and the antifuse element512may have a contact509coupled to the bit line B1. In addition, the selector514and the antifuse element512may be coupled together by the electrode507. The selector514may be a transistor, e.g., a NMOS transistor or a PMOS transistor, or other selection circuit.

In embodiments, the antifuse element512may be individually controllable by the selector514to switch between a first state and a second state. When the word line W1is active, the selector514may select the antifuse element512. A signal from the word line W1may pass through the selector514, further through the antifuse element512, and reaching the other electrode, which is the bit line B1.

FIG. 6illustrates an interposer600that includes one or more embodiments of the disclosure. The interposer600may be an intervening substrate used to bridge a first substrate602to a second substrate604. The first substrate602may be, for instance, a substrate support for a FinFET transistor to be used as an antifuse element, e.g., the FinFET transistor100inFIG. 1, the PMOS FinFET transistor210, the NMOS FinFET transistor220, inFIG. 2, the PMOS FinFET transistor310, the NMOS FinFET transistor320inFIG. 3, or a FinFET transistor to be used as an antifuse element formed following the process400. The second substrate604may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. For example, the second substrate604may be a memory module including the antifuse memory array500as shown inFIG. 5. Generally, the purpose of an interposer600is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer600may couple an integrated circuit die to a ball grid array (BGA)606that can subsequently be coupled to the second substrate604. In some embodiments, the first and second substrates602/604are attached to opposing sides of the interposer600. In other embodiments, the first and second substrates602/604are attached to the same side of the interposer600. In further embodiments, three or more substrates are interconnected by way of the interposer600.

The interposer may include metal interconnects608and vias610, including but not limited to through-silicon vias (TSVs)612. The interposer600may further include embedded devices614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, antifuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer600.

In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer600.

FIG. 7illustrates a computing device700in accordance with one embodiment of the disclosure. The computing device700may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as a SoC used for mobile devices. The components in the computing device700include, but are not limited to, an integrated circuit die702and at least one communications logic unit708. In some implementations the communications logic unit708is fabricated within the integrated circuit die702while in other implementations the communications logic unit708is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die702. The integrated circuit die702may include a processor704as well as on-die memory706, often used as cache memory, which can be provided by technologies such as embedded DRAM (eDRAM), or SRAM. For example, the on-die memory706may include a FinFET transistor to be used as an antifuse element, e.g., the FinFET transistor100inFIG. 1, the PMOS FinFET transistor210, the NMOS FinFET transistor220inFIG. 2, the PMOS FinFET transistor310, the NMOS FinFET transistor320inFIG. 3, a FinFET transistor to be used as an antifuse element formed following the process400, or the antifuse memory array500shown inFIG. 5.

In embodiments, the computing device700may include a display or a touchscreen display724, and a touchscreen display controller726. A display or the touchscreen display724may include a FPD, an AMOLED display, a TFT LCD, a micro light-emitting diode (μLED) display, or others.

Computing device700may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within a SoC die. These other components include, but are not limited to, volatile memory710(e.g., dynamic random access memory (DRAM), non-volatile memory712(e.g., ROM or flash memory), a graphics processing unit714(GPU), a digital signal processor (DSP)716, a crypto processor742(e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset720, at least one antenna722(in some implementations two or more antenna may be used), a battery730or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device728, a compass, a motion coprocessor or sensors732(that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker734, a camera736, user input devices738(such as a keyboard, mouse, stylus, and touchpad), and a mass storage device740(such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device700may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device700includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device700includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.

The processor704of the computing device700includes one or more devices, such as transistors. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communications logic unit708may also include one or more devices, such as transistors.

In further embodiments, another component housed within the computing device700may contain one or more devices, such as an antifuse memory array or antifuse elements, which are formed in accordance with implementations of the current disclosure, e.g., the FinFET transistor100inFIG. 1, the PMOS FinFET transistor210, the NMOS FinFET transistor220inFIG. 2, the PMOS FinFET transistor310, the NMOS FinFET transistor320inFIG. 3, a FinFET transistor to be used as an antifuse element formed following the process400, or the antifuse memory array500shown inFIG. 5.

Some non-limiting Examples are provided below.

Example 1 may include an integrated circuit (IC), comprising: a source electrode in contact with a source area on a substrate; a drain electrode in contact with a drain area on the substrate; a fin area including silicon and between the source area and the drain area; a gate electrode above the fin area and above the substrate; wherein the source area, the fin area, the gate electrode, and the drain area form a FinFET transistor, a first resistance exists between the source electrode, the fin area, and the drain electrode, and wherein a second resistance exists between the source electrode and the drain electrode, and a path through the fin area to couple the source electrode and the drain electrode, wherein the path is formed after a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode.

Example 2 may include the integrated circuit of example 1 and/or some other examples herein, wherein the substrate is a bulk substrate or a silicon-on-insulator (SOI) substrate.

Example 3 may include the integrated circuit of example 1 and/or some other examples herein, wherein the FinFET transistor is a PMOS FinFET or a NMOS FinFET.

Example 4 may include the integrated circuit of example 1 and/or some other examples herein, wherein the programming operation is performed when the FinFET transistor is in an on-state having a voltage between the gate electrode and the source electrode larger than a threshold voltage, or when the FinFET transistor is in an off-state having a voltage between the gate electrode and the source electrode less than the threshold voltage.

Example 5 may include the integrated circuit of example 1 and/or some other examples herein, wherein the programming operation is performed when the FinFET transistor is in an off-state, the programming voltage is less than 3V, and the current is less than 100 microamperes (μA).

Example 6 may include the integrated circuit of example 1 and/or some other examples herein, wherein the programming operation is performed when the FinFET transistor is in an on-state, the programming voltage is less than 2V, and the current is less than 200 μA.

Example 7 may include the integrated circuit of example 1 and/or some other examples herein, wherein the path includes a material migrated from the source electrode or the drain electrode, or amorphous silicon.

Example 8 may include the integrated circuit of example 1 and/or some other examples herein, wherein the first resistance is about 102 to 104 times larger than the second resistance.

Example 10 may include the integrated circuit of example 1 and/or some other examples herein, wherein the gate electrode is coupled to the source electrode, and the FinFET transistor is in an off-state.

Example 11 may include the integrated circuit of example 1 and/or some other examples herein, wherein the FinFET transistor is a PMOS FinFET transistor, the gate electrode is held low to have the PMOS FinFET transistor in an on-state during the programming operation, and held high to have the PMOS FinFET transistor in an off-state during sense or standby operation.

Example 12 may include the integrated circuit of example 1 and/or some other examples herein, wherein the FinFET transistor is a NMOS FinFET transistor, the gate electrode is held high to have the NMOS FinFET transistor in an on-state during the programming operation, and held low to have the NMOS FinFET transistor in an off-state during sense or standby operation.

Example 13 may include a method for forming an integrated circuit, the method comprising: forming a source area on a substrate, a drain area on the substrate, and a fin area including silicon and between the source area and the drain area; forming a source electrode in contact with the source area; forming a drain electrode in contact with the drain area; forming a gate electrode above the fin area and above the substrate, wherein the source area, the fin area, the gate electrode, and the drain area form a FinFET transistor, a first resistance exists between the source electrode, the fin area, and the drain electrode, and wherein a second resistance exists between the source electrode and the drain electrode, and a path through the fin area to couple the source electrode and the drain electrode, wherein the path is formed after a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode.

Example 14 may include the method of example 13 and/or some other examples herein, wherein the programming operation is performed when the FinFET transistor is in an off-state, the programming voltage is less than 3V, and the current is less than 100 microamperes (μA).

Example 15 may include the method of example 13 and/or some other examples herein, wherein the programming operation is performed when the FinFET transistor is in an on-state, the programming voltage is less than 2V, and the current is less than 200 μA.

Example 16 may include the method of example 13 and/or some other examples herein, wherein the path includes a material migrated from the source electrode or the drain electrode, or amorphous silicon.

Example 17 may include the method of example 13 and/or some other examples herein, wherein the first resistance is about 102 to 104 times larger than the second resistance.

Example 19 may include the method of example 13 and/or some other examples herein, wherein the gate electrode is coupled to the source electrode, and the FinFET transistor is in an off-state.

Example 20 may include a computing device, comprising: a circuit board; and an antifuse memory array coupled to the circuit board, wherein the antifuse memory array includes a plurality of antifuse cells, an antifuse cell of the plurality of antifuse cells includes an antifuse element and a selector, and wherein the antifuse element includes: a source electrode in contact with a source area on a substrate, wherein the source electrode is coupled to a bit line of the antifuse memory array; a drain electrode in contact with a drain area on the substrate, wherein the drain electrode is coupled to a first contact of the selector, and the selector includes a second contact coupled to a word line of the antifuse memory array; a fin area including silicon and between the source area and the drain area; and a gate electrode above the fin area and above the substrate; wherein the source area, the fin area, the gate electrode, and the drain area form a FinFET transistor, a first resistance exists between the source electrode, the fin area, and the drain electrode, and wherein a second resistance exists between the source electrode and the drain electrode, and a path through the fin area to couple the source electrode and the drain electrode, wherein the path is formed after a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode.

Example 21 may include the computing device of example 20 and/or some other examples herein, wherein the path includes a material migrated from the source electrode or the drain electrode, or amorphous silicon.

Example 22 may include the computing device of example 20 and/or some other examples herein, wherein the first resistance is about 102 to 104 times larger than the second resistance.

Example 24 may include the computing device of example 20 and/or some other examples herein, wherein the antifuse element is without a void space when the path is formed after the programming operation is performed to apply the programming voltage between the source electrode and the drain electrode to generate the current between the source electrode, the fin area, and the drain electrode.

Example 25 may include the computing device of example 20 and/or some other examples herein, wherein the computing device is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a display, a battery, a processor, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the memory device.