Circuit including a resistive element, a diode, and a switch and a method of using the same

An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N− type epitaxial layer and be connected to an anode element. An N+ type diffusion layer and a P+ typed diffusion layer connected to an surrounding the N+ type diffusion layer are formed in the N− epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as an emitted, the N− type epitaxial layer as the base, and the P+ type drawing layer etc. as the collector.

BACKGROUND OF THE INVENTION

Field of the Invention

The disclosure relates to circuits that include resistive elements, diodes, and switches and method of using the circuits.

Description of the Related Art

Conventionally, for addressing ESD, various types of semiconductor devices having protection circuits for the semiconductor devices are proposed. For example, typically as shown inFIG. 7, an internal circuit56is protected by connecting a PN junction diode52between an input output terminal50and a power supply line51, connecting a PN junction diode54between the input output terminal50and a ground line53, and connecting a PN junction diode55between the power supply line51and the ground line53. The ESD is an abbreviation of Electro-Static Discharge and means the discharge of static electricity.

However, as the miniaturization of elements is enhanced for a demand for higher speed and so on, the electrostatic breakdown tolerance of a semiconductor device is decreased and thus a more proper ESD protection element is essential. Japanese Patent Application publication No. 2006-128293 discloses a BiCMOS type integrated circuit including a MOS type transistor as a high breakdown voltage element and an NPN bipolar transistor as a low breakdown voltage element, which uses the low breakdown voltage NPN transistor as the ESD protection element, its problem, and a means of solving the problem.

Furthermore, Japanese Patent Application Publication No. Hei 05-90481 discloses using an NPN bipolar transistor between a power supply line and a ground line as an ESD protection element instead of using a PN junction diode, in which the base and emitter are connected by a resistor. Japanese Patent Application Publication No. Hei 06-177328 discloses using a MOS type transistor as an ESD protection element of which the snapback voltage is decreased so as to enhance the ESD protection characteristic.

Although details will be described below, the snapback voltage means a trigger voltage to start discharging static electricity to a ground line when a surge voltage by large static electricity is applied to an input output terminal or the like. When the snapback voltage of a protection element is lower than the snapback voltage of an element to be protected, static electricity is discharged to the ground line through the protection element, and the element to be protected is protected from the static electricity.

Japanese Patent Application Publication No. Hei 05-90481 discloses an additional ESD protection element59as shown inFIG. 8in the same structure as the structure shown inFIG. 7for a case in which static electricity is applied between a highest potential terminal as a power supply line51and a lowest potential terminal as a ground line53. Conventionally, a parasitic PN junction diode55ashown by a dotted line which uses the N type epitaxial layer as the cathode and uses the P type semiconductor substrate as the anode becomes a discharge path of static electricity applied between both the terminals and protects an internal circuit56. The parasitic PN junction diode55ais a replacement of the PN junction diode55inFIG. 7.

However, since the enhancement of miniaturization and so on cause the increase of the impedance of the discharge path of static electricity and so on, the parasitic PN junction diode55adoes not effectively work and a discharge path of static electricity occurs through some junction in the internal circuit56, thereby causing a problem of breaking the junction in the internal circuit56. Therefore, for addressing static electricity, the additional ESD protection element59is provided in which an NPN bipolar transistor57of which the base and emitter are shunted by a resistor58is connected in parallel with the parasitic PN junction diode55a.

When a positive voltage by static electricity is applied from the power supply line51to the collector of the NPN bipolar transistor57connected to the power supply line51and a negative voltage is applied from the ground line53to the emitter connected to the ground line53, the NPN bipolar transistor57breaks down at the time when the voltage reaches a collector-emitter breakdown voltage BVCERor more in the state where the resistor58is connected between the base and emitter of the NPN bipolar transistor57. On the contrary, when static electricity is applied as a negative voltage to the power supply line51and as a positive voltage to the ground line53, the base-collector junction is forward-biased through the resistor58and clamped.

Therefore, the internal circuit56between the power supply line51and the ground line53is protected from static electricity by the additional ESD protection element59which is formed by the NPN bipolar transistor57and the resistor58, is connected in parallel with the conventional parasitic ESD protection PN junction diode55a, and has a lower breakdown voltage. A portion of the discharge path of static electricity lies inside the semiconductor substrate, and other portion lies on the surface of the semiconductor substrate.

However, a semiconductor device used in a mobile phone or the like which requires a lower voltage operation needs other ESD protection element which breaks down by a still lower voltage and forms a static electricity discharge path such that a more portion of the path lies inside the semiconductor substrate for heat radiation when static electricity is applied.

SUMMARY OF THE DISCLOSURE

A semiconductor device can include a semiconductor substrate of a first general conductivity type, an epitaxial layer of a second general conductivity type formed on the semiconductor substrate, a first buried layer of the second general conductivity type formed between the semiconductor substrate and the epitaxial layer, a second buried layer of the first general conductivity type connected to a peripheral edge region of the first buried layer and extending from inside the semiconductor substrate into the epitaxial layer, a drawing layer of the first general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be connected to the second buried layer, and a first diffusion layer of the second general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be surrounded by the second buried layer and the drawing layer in plan view of the semiconductor substrate. The first buried layer covers a bottom portion of the first diffusion layer. The device also includes a second diffusion layer of the first general conductivity type connected to and surrounding the first diffusion layer in the plan view, a cathode electrode connected to the first diffusion layer and the second diffusion layer, and an anode electrode connected to the drawing layer. The first buried layer and the second buried layer are configured to form a PN junction diode, the second diffusion layer, the epitaxial layer and the drawing layer are configured to form a parasitic bipolar transistor, and the PN junction diode and the parasitic bipolar transistor are configured to form an ESD protection element.

As a modification of this device, the second diffusion layer may be extended deeper than the first diffusion layer so that the second buried layer can be part of the parasitic bipolar transistor. In another modification, the polarities of the first and second diffusion layers may be switched and the first diffusion layer may be extended deeper than the second diffusion layer so that the first diffusion layer and the second buried layer can be part of the parasitic transistor.

DETAILED DESCRIPTION OF THE INVENTION

The feature of an ESD protection element37used in a semiconductor device of an embodiment will be described below referring toFIGS. 1A, 1B, 2A and 2B.FIG. 1Ais a plan view of the ESD protection element37of the embodiment.FIG. 1Bis a cross-sectional view ofFIG. 1Aalong line A-A, and also a schematic diagram of the discharge path of static electricity. It is noted that a cathode electrode9and an anode electrode10shown inFIG. 1Bare omitted inFIG. 1A.

FIG. 2Ais a circuit diagram of an ESD protection circuit in which the ESD protection element37of the embodiment is connected between a power supply line31and a ground line33. An internal circuit36is connected between the power supply line31and the ground line33. An input output terminal30is drawn from the internal circuit36, and a PN junction diode32is connected between the input output terminal30and the power supply line31and a PN junction diode34is connected between the input output terminal30and the ground line33as ESD protection elements. It is noted that the PN junction diodes32and34may be replaced by the structure of the ESD protection element37.

The ESD protection element37is formed by a PN junction diode35, a resistor39and a parasitic PNP bipolar transistor38shown by a dotted line, as shown inFIG. 2A. As shown inFIG. 1B, the PN junction diode35is formed by an N+ type buried layer2and a P+ type buried layer3. The resistor39is formed by the resistance of an N− type epitaxial layer4. The parasitic PNP bipolar transistor38is formed by a P+ type diffusion layer6as the emitter, the N− type epitaxial layer4as the base and a P+ type drawing layer5as the collector. It is noted that conductivity types such as N+, N and N− belong in one general conductivity type and conductivity types such as P+, P and P− belong in the other general conductivity type.

The structure of the ESD protection element37will be described in more detail referring toFIGS. 1A and 1B, and then the discharge path of static electricity applied to the ESD protection element37will be described.

As shown inFIG. 1B, the N+ type buried layer2and the P+ type buried layer3are connected to each other on the P type semiconductor substrate1, and form the PN junction diode35. The impurity concentration of the N+ type buried layer2at least in a region adjacent to the PN junction is higher than the concentration of the N− type epitaxial layer4, but lower than the concentrations of a high concentration N+ type buried layer as the collector layer of an ordinary NPN bipolar transistor and the P+ type buried layer3of the embodiment. This is to set the breakdown voltage of the PN junction diode35formed by the N+ type buried layer2and the P+ type buried layer3to a desired value.

The P+ type buried layer3and the P+ type drawing layer5are combined and penetrate the N− type epitaxial layer4, and are connected to the anode electrode10connected to the ground line33. An N+ type diffusion layer7and the P+ type diffusion layer6adjacent to the N+ type diffusion layer7are formed from a surface portion of the N− type epitaxial layer4surrounded by the P+ type buried layer3and the P+ type drawing layer5which are shown on the left and right sides inFIG. 1B, and the N+ type buried layer2.

As shown inFIG. 1A, in the N− type epitaxial layer4surrounded by the P+ type drawing layer5etc., the N+ type diffusion layer7is formed, and the P+ type diffusion layer6is formed adjacent to the N+ type diffusion layer7so as to surround the N+ type diffusion layer7. As shown inFIG. 1B, the P+ type diffusion layer6is formed so as to have the same depth as the N+ type diffusion layer7from the surface of the N− type epitaxial layer4.

The anode electrode10connected to the P+ type drawing layer5and the cathode electrode9connected to the N+ type diffusion layer7and the P+ type diffusion layer6are formed through the openings of an insulation film8made of a silicon oxide film or the like formed on the surface of the P type semiconductor substrate1including on the N+ type diffusion layer7. The cathode electrode9is connected to the power supply line31.

A discharge current and the discharge path of the discharge current when static electricity is applied to the ESD protection element37of the embodiment will be described hereafter referring toFIGS. 1B, 2A and 2B.

When a surge voltage by positive static electricity is applied to the power supply terminal VDDshown inFIG. 2A, the surge voltage by the positive static electricity is applied to the N+ type buried layer2from the power supply line31connected to the power supply terminal VDDthrough the cathode electrode9, the N+ type diffusion layer7and the N− type epitaxial layer4as shown inFIG. 1B. On the other hand, the anode electrode10connected to the ground line33, and the P+ type drawing layer5and the P+ type buried layer3connected to the anode electrode10have the ground potential.

Therefore, when the surge voltage by the positive static electricity is larger than the breakdown voltage of the PN junction diode35formed by the N+ buried layer2and the P+ buried layer3, the PN junction diode35breaks down. This is because the breakdown voltage of the PN junction diode35is smaller than the breakdown voltage of the device forming the internal circuit36by setting the impurity concentration of the N+ type buried layer2higher than the impurity concentration of the N− type epitaxial layer4and lower than the impurity concentration of the adjacent P+ type buried layer3.

As a result, as shown inFIG. 1B, a discharge current I1flows from the N+ type diffusion layer7into the anode electrode10through the N− type epitaxial layer4having a resistance component, the N+ type buried layer2, the P+ type buried layer3and the P+ type drawing layer5. To describe this withFIG. 2B, the PN junction diode35breaks down at the voltage a, and the discharge current I1flows with a gradient corresponding to the resistance of the N− type epitaxial layer4etc. until it reaches the voltage b.

When the discharge current I1flows through the N− type epitaxial layer4as the resistor39, a potential gradient occurs in the N− type epitaxial layer4, and the potential of the N− type epitaxial layer4becomes lower than the potential of the high potential P+ type diffusion layer6connected to the cathode electrode9. Therefore, the parasitic PNP bipolar transistor38which uses the P+ type diffusion layer6as the emitter, the N− type epitaxial layer4as the base and the P+ type drawing layer5as the collector turns on.

A large discharge current I2flows through the on-state parasitic PNP bipolar transistor38from the P+ type diffusion layer6as the emitter to the P+ type drawing layer5as the collector as shown inFIG. 1B. Therefore, by the large discharge current I2flowing through the parasitic PNP bipolar transistor38, the positive static electricity entering from the power supply line31into the cathode electrode9flows from the P+ type diffusion layer6into the ground line33through the N− type epitaxial layer4, the P+ type drawing layer5and the anode electrode10. As a result, the internal circuit36is protected from the static electricity immediately.

To describe this withFIG. 2B, at the time when the discharge current I1flows and the voltage of the cathode electrode9reaches the voltage b, i.e., at the time when the potential difference between the P+ type diffusion layer6and the N− type epitaxial layer4reaches a predetermined value, the parasitic PNP bipolar transistor38turns on. The snapback phenomenon occurs at this time, then the collector-emitter voltage VCEof the parasitic PNP bipolar transistor38decreases to the voltage c, and then the discharge current I2increases with a gradient corresponding to the collector resistance of the parasitic PNP bipolar transistor38etc. The voltage c substantially corresponds to BVCERwhich is the breakdown voltage of the parasitic bipolar transistor38when the emitter and base are shunted by a resistor R.

To describe this withFIG. 2A, in the ESD protection element37, first, the PN junction diode35breaks down due to the surge voltage by the positive static electricity applied to the PN junction diode35from the power supply line31through the cathode electrode9and the resistor39, and the discharge current I1flows between the power supply line31and the ground line33. As a result, a voltage decrease occurs at the resistor39and the base potential of the parasitic PNP bipolar transistor38decreases to become lower than the emitter potential, and thus the parasitic PNP bipolar transistor38turns on to flow the large discharge current I2from the power supply line31into the ground line33.

As described above, the feature of the ESD protection element37of the embodiment is that the internal circuit36is immediately protected from static electricity by realizing a desired breakdown voltage of the PN junction diode35by forming the PN junction diode35using the N+ type buried layer2having a predetermined impurity concentration and the P+ type buried layer3and by turning on the parasitic PNP bipolar transistor38using the discharge current I1by the breakdown of the PN junction diode35to flow the large discharge current I2.

Hereafter, a method of manufacturing the ESD protection element of the embodiment will be briefly described referring toFIGS. 1B, 3A, 3B, 3C, 4A and 4B. Basically, the method is the same as a method of manufacturing a bipolar integrated circuit.

First, as shown inFIG. 3A, the P type semiconductor substrate1is provided, and an insulation film20made of a silicon thermal oxide film or the like is formed on the surface. Then a predetermined size of opening20a is formed in the insulation film20by a predetermined photo-etching process, and an antimony (Sb) doped coating film21is formed so as to cover the P type semiconductor substrate1including the opening20aunder the same condition as the condition for forming an N+ type buried layer in an ordinary bipolar process.

Then a heat treatment is performed to form an N+ type buried deposition layer2ain the P type semiconductor substrate1. The N+ type buried deposition layer2amay be formed by ion-implanting antimony (Sb) or the like instead of using the coating film21.

Then, as shown inFIG. 3B, after the coating film21is removed, a heat treatment is performed at temperature of about 1100° C. so as to diffuse the N+ type buried deposition layer2ain the P type semiconductor substrate1in the lateral direction and in the downward direction into a deeper region, thereby forming the N+ type buried layer2. At this time, a silicon oxide film22is formed on the P type semiconductor substrate1including on the N+ type buried layer2.

Then, as shown inFIG. 3C, an opening22ais formed in the silicon oxide film22by a predetermined photo-etching process, and boron (B) or the like is ion-implanted or the like in the P type semiconductor substrate1exposed in the opening22ausing the silicon oxide film22etc. as a mask, thereby forming a P+ type buried deposition layer3a.

Then, as shown inFIG. 4A, after the silicon oxide film22is removed, the N− type epitaxial layer4is deposited on the P type semiconductor substrate1including on the N+ buried layer2etc. by a predetermined epitaxial method. Then boron (B) or the like is ion-implanted in a predetermined position of the N− type epitaxial layer4or the like using a silicon oxide film etc. formed on the surface of the N− type epitaxial layer4as a mask, and a predetermined heat treatment is performed to form the combined P+ type buried layer3and P+ type drawing layer5penetrating the N− type epitaxial layer4as shown inFIG. 4A.

By the deposition of the N− type epitaxial layer4and the heat treatment after the deposition described above, the N+ type buried layer2is thermally diffused in the N− type epitaxial layer4to extend in the upward and lateral directions. However, the width of the diffusion is small since the diffusion coefficient of antimony (Sb) or the like forming the N+ type buried layer2is small. An insulation film23made of a silicon oxide film or the like is formed on the N− type epitaxial layer4including on the P+ type drawing layer5.

The P+ type buried layer3diffused in the lateral direction at latest when the N− type epitaxial layer4is deposited or the heat treatment is performed after the deposition is connected to the end portion of the N+ type buried layer2having a low impurity concentration which is diffused in the lateral direction from the opening20ain the P type semiconductor substrate1etc. inFIG. 3A, thereby forming the PN junction diode35having a desired breakdown voltage.

In detail, in the PN junction diode35, the impurity concentration of a portion of the N+ type buried layer2adjacent to the PN junction is adjusted to a proper concentration by adjusting the distance between the end portion of the opening20ashown inFIG. 3Aand the end portion of the opening22ashown inFIG. 3C. As a result, when a reverse bias is applied to the PN junction diode35, the depletion layer extends more widely toward the N+ type buried layer2having a low impurity concentration, achieving the desired breakdown voltage.

It is also possible that the PN junction diode35is formed by the N+ type buried layer2having a low impurity concentration and the P+ type buried layer3by designing the N+ type buried layer2so as to have an impurity concentration lower than the impurity concentration of an N+ type buried layer in an ordinary bipolar process and lower than the impurity concentration of the P+ type buried layer3and by forming the N+ type buried layer2so as to overlap the P+ type buried layer3by an ion implantation process or the like. The desired breakdown voltage of the PN junction diode35is realized by setting the impurity concentration of the N+ type buried layer2having a low impurity concentration to a predetermined value, which is formed by the ion implantation process or the like in this region.

Furthermore, it is also possible to form an N+ type buried layer having a high impurity concentration equivalent to the impurity concentration of an N+ type buried layer of an ordinary bipolar process in a region away from the P+ type buried layer3, and then form the described N+ type buried layer2having a low impurity concentration between the N+ type buried layer having a high impurity concentration and the P+ type buried layer3so as to connect these, thereby forming the PN junction diode35by the N+ type buried layer2having a low impurity concentration and the P+ type buried layer3.

In the embodiment, the misalignment of the masks for forming the opening20aand the opening22amay cause a variation of the breakdown voltages of the PN junction diodes35. However, the case of forming the N+ type buried layer2overlapping the P+ type buried layer3by ion implantation or the like does not cause a phenomenon corresponding to the mask misalignment, and thus the variation of the breakdown voltages of the PN junction diodes35is moderated.

Then, as shown inFIG. 4B, the N+ type diffusion layer7and the P+ type diffusion layer6are formed sequentially by ion-implanting arsenic (As) or the like and boron (B) or the like using the insulation film23or a photoresist film as a mask by a predetermined method. This process is performed at the same time as when the emitter layer, the base contact layer, etc. of an ordinary bipolar transistor are formed. The insulation film8made of a silicon oxide film or the like is formed on the P type semiconductor substrate1including on the N+ type diffusion layer7etc.

Then, as shown inFIG. 1B, the anode electrode10connected to the P+ type drawing layer5and the cathode electrode9connected to the N+ type diffusion layer7and the P+ type diffusion layer6are formed in the insulation film8through the openings formed by a predetermined photo-etching process by performing a predetermined photo-etching process to a thin film made of aluminum (Al) or the like deposited by sputtering or the like. A multi-layer wiring structure is then formed according to need, and finally a passivation film is formed, thereby completing the semiconductor device having the ESD protection element37.

Next, an ESD protection element of a first modification of the embodiment will be described referring toFIGS. 5A and 5B. While the depth of the P+ type diffusion layer6in the N− type epitaxial layer4is almost the same as the depth of the N+ type diffusion layer7in the embodiment, a P+ type diffusion layer6ais extended to a much deeper position than the N+ type diffusion layer7in the first modification, and this is the difference between the embodiment and the first modification. InFIGS. 5A and 5B, the P+ type diffusion layer6ais formed at the same time as when the P+ type drawing layer5is formed, and is extended to the same depth as the depth of the P+ type drawing layer5. The other structure is the same as that of the embodiment.

With this structure, as shown inFIG. 5B, the discharge current I2of the parasitic PNP bipolar transistor38flows from the deeper region of the P+ type diffusion layer6ainto the P+ type buried layer3etc. through the deeper region of the N− type epitaxial layer4. This is because the potential of the N− type epitaxial layer4becomes lower around the deeper region of the P+ type diffusion layer6a, and the potential difference between the N− type epitaxial layer4and the P+ type diffusion layer6abecomes larger.

Since the large discharge current I2of the parasitic PNP bipolar transistor38flows through the deeper region of the N− type epitaxial layer4nearer the back surface of the semiconductor device, the heat radiation effect is enhanced and the thermal destruction does not easily occur, compared with the device of the embodiment. Therefore, the discharge current I2is larger and the internal circuit36is protected from static electricity more immediately. From this point of view, it is preferable that the P+ type diffusion layer6is extended to a deeper position in the N− type epitaxial layer4.

An ESD protection element of a second modification of the embodiment will be described referring toFIGS. 6A and 6B. While the N+ type diffusion layer7is surrounded by the P+ type diffusion layer6ain the first modification as shown inFIG. 5A, a P+ type diffusion layer6bis surrounded by the N+ type diffusion layer7in the second modification as shown inFIG. 6A. This is the difference between the first modification and the second modification.

With this structure, by the discharge current I1flowing from the N+ type diffusion layer7toward the N+ type buried layer2, a potential difference occurs between the P+ type diffusion layer6band the N− type epitaxial layer4adjacent to the P+ type diffusion layer6b. Since the potential difference becomes larger in the deeper region of the P+ type diffusion layer6b, the discharge current I2in the deeper region becomes larger and also the discharge current I2flows from the shallower portion of the P+ type diffusion layer6b. As a result, the total amount of the discharge current I2becomes larger than in the first modification.

In the case of the first modification shown inFIGS. 5A and 5B, too, a potential difference occurs between the P+ type diffusion layer6aand the N− type epitaxial layer4under the N+ diffusion layer7adjacent to the P+ type diffusion layer6a. Since this potential difference becomes larger in the deeper region of the P+ type diffusion layer6a, the discharge current2is larger in the deeper portion. Even in the shallower portion, too, the parasitic PNP bipolar transistor turns on.

However, the P+ type buried layer3and the P+ type drawing layer5are disposed away from the shallow portion of the N− type epitaxial layer4under the N+ type diffusion layer7where a voltage decrease occurs. Therefore, the distance from the N− type epitaxial layer4in this portion to the P+ type buried layer3etc. as the collector is long. In other words, the base width is large. Therefore, the discharge current I2from this portion is small.

Although the description of the embodiment etc. is given using one ESD protection element as shown inFIG. 1Aetc., the same structures may be formed on the front, rear, left and right sides in these figures in a grid pattern so as to form an ESD protection element of which the discharge current I2is further increased.

A semiconductor device can have an ESD protection element with a high ESD protection characteristic which breaks down by a desired breakdown voltage and flows a large discharge current.