Stretchable display panel and display device

A stretchable display panel has a plurality of island regions and a plurality of bridge regions. The island regions are arranged in an array. Every two adjacent island regions are connected with a bridge region in the bridge regions therebetween. The display panel includes a plurality of sub-pixels and a plurality of signal line groups. At least one sub-pixel is provided in each island region. The signal line groups are located in a same conductive layer. Each signal line group extends along bridge regions to island regions that are connected to the bridge regions. The signal line group includes a plurality of signal lines arranged in parallel and at intervals. Each signal line is electrically connected to sub-pixels in the island regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a national phase entry under 35 USC 371 of International Patent Application No. PCT/CN2021/077082 filed on Feb. 20, 2021, which claims priority to Chinese Patent Application No. 202010121483.6, filed on Feb. 26, 2020, which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present disclosure relates to the field of display technologies, and in particular, to a stretchable display panel and a display device.

BACKGROUND

With the development of display technologies, display devices are gradually applied to various industries. A display device includes a display panel. Traditional display panels are rigid display panels, which can no longer meet people's application requirements for display panels, so stretchable display panels emerge as the times require.

The stretchable display panels have gradually attracted people's attention because they can meet needs of various special structures.

SUMMARY

In an aspect, a stretchable display panel is provided. The display panel has a plurality of island regions and a plurality of bridge regions, the plurality of island regions are arranged in an array, and every two adjacent island regions are connected with a bridge region in the plurality of bridge regions therebetween. The display panel includes a plurality of sub-pixels and a plurality of signal line groups. At least one sub-pixel is provided in each island region. The plurality of signal line groups are located in a same conductive layer, and each signal line group extends along bridge regions to island regions that are connected to the bridge regions. The signal line group includes a plurality of signal lines arranged in parallel and at intervals. Each signal line is electrically connected to sub-pixels in the island regions.

In some embodiments, the plurality of bridge regions include a plurality of first bridge regions and a plurality of second bridge regions. A first bridge region in the plurality of first bridge regions is connected between two adjacent island regions in a first direction, and a second bridge region in the plurality of second bridge regions is connected between two adjacent island regions in a second direction. The first direction is a row direction in which the plurality of island regions are arranged in the array, and the second direction is a column direction in which the plurality of island regions are arranged in the array.

The plurality of signal line groups include a plurality of first signal line groups and a plurality of second signal line groups. Each first signal line group extends in the first direction as a whole, and the first signal line group extends along first bridge regions to island regions that are connected to the first bridge regions and is electrically connected to sub-pixels in the island regions. Each second signal line group extends in the second direction as a whole, and the second signal line group extends along second bridge regions to island regions that are connected to the second bridge regions and is electrically connected to sub-pixels in the island regions.

In some embodiments, the second signal line group includes at least one reference voltage signal line. The first signal line group includes at least one equipotential signal line. In the at least one equipotential signal line, an equipotential signal line includes a plurality of equipotential wiring segments. Every two adjacent equipotential wiring segments are electrically connected to each other. Each equipotential wiring segment extends along a first bridge region in the plurality of first bridge regions, and two ends of the equipotential wiring segment are electrically connected to reference voltage signal lines in two island regions that are connected to the first bridge region.

In some embodiments, the display panel further includes a plurality of connection pattern layers. Each island region is provided with a connection pattern layer therein. In the island region, at least one of an equipotential signal line and a reference voltage signal line is electrically connected to the connection pattern layer.

In some embodiments, the display panel further includes a base, and a first gate conductive layer, a second gate conductive layer, an interlayer dielectric layer and a source-drain conductive layer that are sequentially stacked on the base. The plurality of signal line groups are located in the source-drain conductive layer, and the plurality of connection pattern layers are located in the second gate conductive layer.

The interlayer dielectric layer is provided with a plurality of via holes therein, and the at least one of the equipotential signal line and the reference voltage signal line is electrically connected to the connection pattern layer through at least one via hole.

In some embodiments, the at least one reference voltage signal line includes at least two reference voltage signal lines. Each connection pattern layer includes a plurality of bridge portions. Two equipotential wiring segments that extend to a same island region and are electrically connected to each other are a first equipotential wiring segment and a second equipotential wiring segment. The first equipotential wiring segment is electrically connected to a reference voltage signal line in the same island region through a bridge portion in a plurality of bridge portions of a connection pattern layer in the same island region, and the second equipotential wiring segment is directly electrically connected to another reference voltage signal line in the same island region.

In some embodiments, the second signal line group further includes a plurality of data signal lines. An orthogonal projection of at least one data signal line on the base is spaced between an orthogonal projection of an end portion, electrically connected to the reference voltage signal line, of the first equipotential wiring segment on the base and an orthogonal projection of the reference voltage signal line, electrically connected to the first equipotential wiring segment, on the base. An orthogonal projection of the bridge portion on the base overlaps with the orthogonal projection of the at least one data signal line on the base.

An orthogonal projection of an end portion, electrically connected to the another reference voltage signal line, of the second equipotential wiring segment on the base overlaps with an orthogonal projection of the another reference voltage signal line, electrically connected to the second equipotential wiring segment, on the base.

In some embodiments, the first signal line group further includes a plurality of control signal lines including at least a gate scanning signal line, an initialization signal line, a light-emitting signal line, and a reset signal line. The second signal line group further includes a plurality of data signal lines.

A number of the control signal lines included in the first signal line group is less than a sum of a number of the reference voltage signal line and a number of the data signal lines included in the second signal line group. A dimension of the first bridge region in the second direction is substantially equal to a dimension of the second bridge region in the first direction.

In some embodiments, in the first signal line group, an equipotential signal line is located at a side of two opposite sides of the plurality of control signal lines in the second direction.

In some embodiments, the display panel further has a plurality of opening regions.

At least a portion of an opening region in the plurality of opening regions is disposed between two adjacent island regions in the first direction. A plurality of signal lines of a second signal line group in the plurality of second signal line groups, to which sub-pixels in the two adjacent island regions are electrically connected, are arranged substantially symmetrically with a center line in the second direction of the opening region corresponding to the two adjacent island regions as an axis of symmetry. And/or, at least a portion of another opening region in the plurality of opening regions is disposed between two adjacent island regions in the second direction. A plurality of signal lines of a first signal line group in the plurality of first signal line groups, to which sub-pixels in the two adjacent island regions are electrically connected, are arranged substantially symmetrically with a center line in the first direction of the opening region corresponding to the two adjacent island regions as an axis of symmetry.

In some embodiments, the opening regions each are in a shape of a capital H, and each include two side holes that are parallel to each other and a middle hole located between the two side holes. The middle hole is perpendicular to the two side holes, and both ends of the middle hole are communicated with the two side holes.

The plurality of opening regions include a plurality of first opening regions and a plurality of second opening regions. The plurality of first opening regions are arranged into a plurality of rows extending in the first direction, and middle holes of the first opening regions extend in the first direction. The plurality of second opening regions are arranged into a plurality of columns extending in the second direction, and middle holes of the second opening regions extend in the second direction. Two adjacent rows of first opening regions are staggered to each other, and two adjacent columns of second opening regions are staggered to each other.

The plurality of signal lines of the second signal line group, to which the sub-pixels in the two adjacent island regions in the first direction are electrically connected, are arranged substantially symmetrically with a middle hole of a second opening region corresponding to the two adjacent island regions as an axis of symmetry. And/or, the plurality of signal lines of the first signal line group, to which the sub-pixels in the two adjacent island regions in the second direction are electrically connected, are arranged substantially symmetrically with a middle hole of a first opening region corresponding to the two adjacent island regions as an axis of symmetry.

In some embodiments, in the first direction, the display panel has a first end and a second end opposite to each other. The second signal line group includes N data signal lines, and N is greater than or equal to 2. In the second bridge region, the N data signal lines are arranged in a sequence of a first data signal line to an N-th data signal line in the first direction and along a direction from the first end to the second end of the display panel.

An island region connected with the second bridge region is provided with N columns of sub-pixels. The N columns of sub-pixels are arranged in a sequence of a first column of sub-pixels to an N-th column of sub-pixels in the first direction and along the direction from the first end to the second end of the display panel.

Each column of sub-pixels is electrically connected to a data signal line, and a sum of a serial number of the column of sub-pixels and a serial number of the data signal line is equal to (N+1).

In some embodiments, the display panel further includes a plurality of pin groups. Each pin group corresponds to a second signal line group in the plurality of second signal line groups. The pin group includes N pins. The N pins are arranged in a sequence of a first pin to an N-th pin in the first direction and along the direction from the first end to the second end of the display panel. The N pins are electrically connected to N data signal lines of the corresponding second signal line group. In the pin group, an i-th pin is configured to be electrically connected to a source driver to receive data signals of an (N+1−i)-th column of sub-pixels from the source driver. i takes a value from 1 to N.

In some embodiments, the display panel further has a plurality of pin regions. Two pin groups corresponding to two second signal line groups that are arranged substantially symmetrically are provided in a same pin region.

In some embodiments, each signal line in the second signal line group is electrically connected to sub-pixels in each of the island regions after being bent twice. And/or, each signal line in the first signal line group is electrically connected to sub-pixels in each of the island regions after being bent twice.

In some embodiments, the bridge regions each are in a shape of a rectangle, a capital U, or a capital S. Each island region is connected to four bridge regions, the four bridge regions surround the island region, and a plurality of signal lines in the four bridge regions are arranged symmetrically with respect to a center of the island.

In another aspect, a display device is provided. The display device includes the display panel as described in any one of the above embodiments.

DETAILED DESCRIPTION

In the description of some embodiments, the term “electrically connected” and its extensions may be used to indicate that two or more components are in electrically contact with each other.

The phrase “applicable to” or “configured to” used herein has an open and inclusive meaning, which does not exclude devices that are applicable to or configured to perform additional tasks or steps.

The term “substantially” as used herein includes a stated value and an average value within an acceptable range of deviation of a particular value. The acceptable range of deviation is determined by a person of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

In the related art, regions for arranging signal lines inside a stretchable display panel is limited by a complex design of regions inside the display panel. In order to achieve electrical connections between signal lines and respective sub-pixels in a display area, a part of the signal lines needs to cross a conductive layer where another part of the signal lines is located (which is also referred to as a “cross-layer jumper”). Two adjacent signal lines are spaced by an insulating layer to achieve the cross-layer jumper of the signal lines and avoid a short circuit between the signal lines.

However, due to the jumper of the signal lines, there is an overlapping portion between the signal lines in a direction perpendicular to a plane on which the display panel is located, which causes a coupling phenomenon between voltage signals transmitted by different signal lines, thereby resulting in a mutual interference between the signals, and thus reducing the display quality of the display panel.

In order to solve the problems, as shown inFIGS.1and2, some embodiments of the present disclosure provide a stretchable display panel100having a plurality of island regions1and a plurality of bridge regions2. The plurality of island regions1are arranged in an array, every two adjacent island regions1are connected with a bridge region2therebetween, which achieve connections among the island regions1, thereby ensuring the structural integrity of the display panel100.

For example, every two adjacent island regions1are connected through a bridge region2.

As shown inFIGS.3and4, the display panel100includes a plurality of sub-pixels8, and each island region1is provided with at least one sub-pixel8therein.

For example, each island region1is provided with a plurality of sub-pixels8therein. The plurality of sub-pixels8may include at least first color sub-pixels, second color sub-pixels and third color sub-pixels. The first color, the second color and the third color may be three primary colors, such as red, green and blue. It will be understood that each sub-pixel8as the smallest light-emitting unit may emit light of a single primary color.

As shown inFIGS.2and3, the display panel100further includes a plurality of signal line groups9. The plurality of signal line groups9are located in a same conductive layer. Each signal line group9extends along bridge regions2to island regions1that are connected to the bridge regions2. By providing the bridge regions2, wiring regions are provided for the signal line groups9.

It will be noted that the description that “the plurality of signal line groups9are located in the same conductive layer” may mean that the plurality of signal line groups9are made of a same material and disposed in a same layer. “The same layer” means that the conductive layer used for forming the signal line groups9is formed through a same film forming process, and then the signal line groups9are formed through a single patterning process using a same mask.

Each signal line group9includes a plurality of signal lines91arranged in parallel and at intervals. Each signal line91is electrically connected to a plurality of sub-pixels8in an island region1.

It will be understood that different signal lines91are used for transmitting different voltage signals, and each signal line91is used for transmitting voltage signals to the plurality of sub-pixels8electrically connected thereto, so as to control or drive the plurality of sub-pixels8to emit light.

In the display panel100of the embodiments of the present disclosure, by arranging the plurality of signal line groups9in the same conductive layer, it is possible to avoid that there are overlapping portions among the signal lines91in a direction E (referring toFIG.4) perpendicular to a plane on which the display panel100is located, thereby weakening the coupling phenomenon between voltage signals transmitted by different signal lines91and reducing the mutual interference between the signals, and thus improving the display quality of the display panel100.

In addition, the plurality of signal lines91included in each signal line group9are in the same conductive layer, and are arranged in parallel and at intervals, so that there is a distance between two adjacent signal lines91, and distances between the two adjacent signal lines91at various positions are approximately equal. In this way, it may be possible to further weaken the coupling phenomenon between the voltage signals transmitted by different signal lines91and reduce the mutual interference between the signals.

In addition, by arranging the plurality of signal line groups9in the same conductive layer, it may be possible to avoid the cross-layer jumpers of the signal lines91, thereby avoiding the overlapping portions among the signal lines91in the direction E, which helps to reduce a dimension of the display panel100in the direction E, i.e., a thickness of the display panel100, and thus achieving the lightness and thinness of the display panel100.

In some embodiments, as shown inFIGS.1and2, a row direction in which the plurality of island regions1are arranged in the array is a first direction X, and a column direction in which the plurality of island regions1are arranged in the array is a second direction Y.

The plurality of bridge regions2includes a plurality of first bridge regions21and a plurality of second bridge regions22. A first bridge region21is connected between two adjacent island regions1in the first direction X, and a second bridge region22is connected between two adjacent island regions1in the second direction Y. For example, in the first direction X, first bridge regions21each are connected between every two adjacent island regions1; and in the second direction Y, second bridge regions22each are connected between every two adjacent island regions1.

As shown inFIGS.2and3, the plurality of signal line groups9include a plurality of first signal line groups9A and a plurality of second signal line groups9B. Each first signal line group9A extends in the first direction X as a whole, and the first signal line group9A extends along first bridge regions21to island regions1that are connected to the first bridge regions21and is electrically connected to sub-pixels8in the island regions1.

It will be noted that the description that “each first signal line group9A extends in the first direction X as a whole” means that each first signal line group9A has a tendency to extend in the first direction X as the whole. The first signal line group9A may be in a shape of a straight line, so that all parts of the first signal line group9A extend in the first direction X. The first signal line group9A may also be in a shape of a non-straight line, such as a wavy line or a polyline, so that part of the first signal line group9A may deviate from the first direction X, but the first signal line group9A has a tendency to extend in the first direction X as a whole.

By arranging in this manner, sub-pixels8in each row of island regions1in the first direction X are electrically connected to a single first signal line group9A.

Each second signal line group9B extends in the second direction Y as a whole, and the second signal line group9B extends along second bridge regions22to island regions1that are connected to the second bridge regions22and is electrically connected to sub-pixels8in the island regions1.

Same as the description that “each first signal line group9A extends in the first direction X as s whole”, the description that “each second signal line group9B extends in the second direction Y as a whole” means that each second signal line group9B has a tendency to extend in the second direction Y as a whole, which will not be repeated herein.

By arranging in this manner, sub-pixels8in each column of island regions1in to the second direction Y are electrically connected to a single second signal line group9B.

In the related art, since a signal line itself has impedance, a voltage drop phenomenon (i.e., IR-Drop) will occur during a transmission of a voltage signal on the signal line. Moreover, limited by the precision of a preparation process for signal lines, impedances of different signal lines may be different, resulting in differences in voltage signals received by sub-pixels that are electrically connected to the different signal lines. As a result, it may be possible to cause a difference in light-emitting brightness of the sub-pixels that are electrically connected to the different signal lines, which affects a display effect of a display panel.

To solve the problems, in some embodiments, as shown inFIGS.2and3, the second signal line group9B includes at least one reference voltage signal line92, and the first signal line group9A includes at least one equipotential signal line93. An equipotential signal line93includes a plurality of equipotential wiring segments94. Every two adjacent equipotential wiring segments94are electrically connected to each other. Each equipotential wiring segment94extends along a first bridge region21, and two ends of the equipotential wiring segment94are electrically connected to reference voltage signal lines92in two island regions1that are connected to the first bridge region21.

In the embodiments of the present disclosure, reference voltage signal lines92in every two adjacent island regions1are electrically connected through an equipotential wiring segment94, so that reference voltage signal lines92in all island regions1are electrically connected, and all the reference voltage signal lines92and the equipotential wiring segments94form a meshed signal line. The impedance of the meshed signal line is less than that of the reference voltage signal lines92, which are arranged independently of each other. As a result, it may improve the voltage drop phenomenon that occurs during the transmission of a reference voltage signal on the reference voltage signal line92.

In addition, the meshed signal line transmits the reference voltage signal, which makes a voltage value of the reference voltage signal transmitted by each reference voltage signal line92same or substantially same, and the reference voltage signal received by the sub-pixels8that are electrically connected to each reference voltage signal line92same or substantially same, thereby reducing the difference in the light-emitting brightness of the sub-pixels8, which is conducive to improving a display effect of the display panel100.

In some embodiments, as shown inFIG.3, the display panel100further includes a connection pattern layer10disposed in the island region1. In the island region1, at least one of the equipotential signal line93and the reference voltage signal line92is electrically connected to the connection pattern layer10.

For example, one of two adjacent equipotential wiring segments94in an equipotential signal line93that extends to a same island region1is electrically connected to the connection pattern layer10.

For example, all reference voltage signal lines92in each island region1are electrically connected to the connection pattern layer10, so that all reference voltage signal lines92in the island region1are electrically connected. All the reference voltage signal lines92and the connection pattern layer10in each island region1form a meshed signal line, so that a voltage value of the reference voltage signal transmitted by each reference voltage signal line92is same or substantially same.

For example, in the island region1, the equipotential signal line93and the reference voltage signal lines92are all electrically connected to the connection pattern layer10, and the equipotential signal line93and the reference voltage signal lines92are electrically connected through the connection pattern layer10.

In some embodiments, as shown inFIG.4, the display panel100further includes a base101, and a first gate conductive layer104, a second gate conductive layer106, an interlayer dielectric layer107and a source-drain conductive layer108that are sequentially stacked on the base101. The plurality of signal line groups9are located in the source-drain conductive layer108, and the connection pattern layer10is located in the second gate conductive layer106.

It will be understood that the plurality of signal line groups9and the source-drain conductive layer108are made of a same material, and the connection pattern layer10and the second gate conductive layer106are made of a same material.

For example, as shown inFIGS.3and5, in a case where the island region1are provided with two rows of sub-pixels8therein, the connection pattern layer10includes two planar connection pattern sub-layers10B, and a connection pattern sub-layer10B is electrically connected to a row of sub-pixels8. In addition, the second gate conductive layer106further includes two linear initialization signal line layers1061, and an initialization signal line layer1061is electrically connected to a row of sub-pixels8.

As shown inFIG.4, the interlayer dielectric layer107is provided with a plurality of via holes H therein. At least one of the equipotential signal line93and the reference voltage signal line92is electrically connected to the connection pattern layer10through at least one via hole H.

For example, the one of the two adjacent equipotential wiring segments94in the equipotential signal line93that extends to the same island region1is electrically connected to the connection pattern layer10through at least one via hole H.

For example, all the reference voltage signal lines92in the island region1are each electrically connected to the connection pattern layer10through at least one via hole H, so that all the reference voltage signal lines92in the island region1are electrically connected.

For example, the equipotential signal line93and the reference voltage signal line92are each electrically connected to the connection pattern layer10through a via hole H, and the equipotential signal line93is electrically connected to the reference voltage signal line92through the connection pattern layer10.

For example, the display panel100further includes active layers102disposed on the base101. A first gate insulating layer103is disposed between the active layers102and the first gate conductive layer104, so as to avoid a short circuit between the active layers102and the first gate conductive layer104.

The display panel100further includes a second gate insulating layer105disposed between the first gate conductive layer104and the second gate conductive layer106, so as to avoid a short circuit between the first gate conductive layer104and the second gate conductive layer106.

For example, a material of the base101includes a flexible material, such as polyimide.

For example, a material of the source-drain conductive layer108may be of a laminated structure of titanium, aluminum, and titanium.

In some embodiments, the display panel100further includes a plurality of pixel driving circuits disposed on the base101and located in the island regions1. Each pixel driving circuit includes a plurality of thin film transistors. Gates of the thin film transistors are located in the first gate conductive layer104, and sources and drains of the thin film transistors are located in the source-drain conductive layer108.

In a wiring design of the signal lines91, how to achieve the electrically connection between the equipotential signal line93and the reference voltage signal line92may depend on whether there are other signal lines therebetween in the source-drain conductive layer108where they are located.

In some embodiments, as shown inFIGS.3and4, the connection pattern layer10includes bridge portions10A. Two equipotential wiring segments94that extend to the same island region1and are electrically connected to each other are a first equipotential wiring segment94A and a second equipotential wiring segment94B. The first equipotential wiring segment94A is electrically connected to a reference voltage signal line92in the island region1through a bridge portion10A, and the second equipotential wiring segment94B is directly electrically connected to another reference voltage signal line92in the island region1.

For example, as shown inFIG.4, the second signal line group9B further includes a plurality of data signal lines95. An orthogonal projection of at least one data signal line95on the base101is spaced between an orthogonal projection of an end portion, electrically connected to the reference voltage signal line92, of the first equipotential wiring segment94A on the base101and an orthogonal projection of the reference voltage signal line92, electrically connected to the first equipotential wiring segment94A, on the base101. An orthogonal projection of the bridge portion10A on the base101overlaps with the orthogonal projection of the spaced at least one data signal line95on the base101.

It will be understood that, in a case where the at least one data signal line95is spaced between the first equipotential wiring segment94A and the reference voltage signal line92, the first equipotential wiring segment94A and the reference voltage signal line92are each electrically connected to the bridge portion10A through a via hole H, and the data signal line95is crossed by the bridge portion10A, thereby achieving an electrical connection between the first equipotential wiring segment94A and the reference voltage signal line92.

For example, referring toFIG.3, an orthogonal projection of an end portion, directly electrically connected to the reference voltage signal line92, of the second equipotential wiring segment94B on the base101overlaps with an orthogonal projection of the reference voltage signal line92, electrically connected to the second equipotential wiring segment94B, on the base101.

It will be understood that there is no other signal line spaced between the second equipotential wiring segment94B and the reference voltage signal line92. In the source-drain conductive layer108, the second equipotential wiring segment94B may be directly electrically connected to the reference voltage signal line92.

In some embodiments, as shown inFIG.3, the first signal line group9A further includes a plurality of control signal lines90, including at least at least one gate scanning signal line96, at least one initialization signal line97, at least one light-emitting signal line98, and at least one reset signal line99.

The number of the control signal lines90included in the first signal line group9A is less than a sum of the number of the reference voltage signal line(s)92and the number of the data signal lines95included in the second signal line group9B. A dimension of the first bridge region21in the second direction Y is substantially equal to a dimension of the second bridge region22in the first direction X.

It will be noted that the term “substantially” means that the dimension of the first bridge region21in the second direction Y and the dimension of the second bridge region22in the first direction X are equal, or there is a dimensional difference within an acceptable deviation range therebetween, and the dimensional difference is negligible.

According to the above, the control signal lines90included in the first signal line group9A extend along the first bridge region21, and the reference voltage signal line(s)92and the data signal lines95included in the second signal line group9B extend along the second bridge region22. In a case where the dimension of the first bridge region21in the second direction Y is substantially equal to the dimension of the second bridge region22in the first direction X, a vacant region (i.e., a region in which no signal line91is provided) in the first bridge region21is greater than that in the second bridge region22. Therefore, the equipotential signal line93and the plurality of control signal lines90may be provided in the first bridge region21. In this way, the vacant region of the first bridge region21may be used without adding additional wiring regions.

In some embodiments, as shown inFIG.3, the plurality of control signal lines90include two gate scanning signal lines96, one initialization signal line97, one light-emitting signal line98, and one reset signal line99.

The island region1is provided with two rows of sub-pixels8therein, and each gate scanning signal line96is electrically connected to a row of sub-pixels8. A gate scanning signal is transmitted to each row of sub-pixels8through a gate scanning signal line96to control the turn-on and turn-off of the row of sub-pixels. The two rows of sub-pixels8are electrically connected to the initialization signal line97to simultaneously transmit an initialization signal to the two rows of sub-pixels8. The two rows of sub-pixels8are electrically connected to the light-emitting signal line98to simultaneously transmit a light-emitting signal to the two rows of sub-pixels8. The two rows of sub-pixels8are electrically connected to the reset signal line99to simultaneously transmit a reset signal to the two rows of sub-pixels8.

In some embodiments, as shown inFIGS.2and3, in the first signal line group9A, at least one equipotential signal line93is located at a side of two opposite sides of the plurality of control signal lines90in the second direction Y, which avoids cross-layer jumpers between the equipotential signal line93and the plurality of control signal lines90, thereby facilitating the electrical connection between the equipotential signal line93and the reference voltage signal line92in the island region1.

For example, in two equipotential signal lines93in the first signal line group9A, one equipotential signal line93is located at one side of the two opposite sides of the plurality of control signal lines90in the second direction Y, and the other equipotential signal line93is located at the other side of the two opposite sides of the plurality of control signal lines90in the second direction Y.

In some embodiments, as shown inFIGS.1and2, the display panel100further has a plurality of opening regions4. At least a portion of an opening region4is located between two adjacent island regions1in the first direction X, and at least a portion of another opening region4is located between two adjacent island regions1in the second direction Y. The display panel100will be deformed during a stretching process, and the plurality of opening regions4may provide a space for deformation for the stretching of the display panel100.

A plurality of signal lines91of a second signal line group9B, to which sub-pixels8in two adjacent island regions1in the first direction X are electrically connected, are arranged substantially symmetrically with a center line F in the second direction Y of an opening region4corresponding to two adjacent island regions1in the first direction X as an axis of symmetry, which achieves a symmetrical arrangement of the plurality of signal lines91of the second signal line group9B in the first direction X, thereby facilitating the wiring of the plurality of signal lines91of the second signal line group9B. Moreover, it is avoided that there are overlapping portions among the signal lines91in the direction E perpendicular to the plane where the display panel100is located.

In some embodiments, as shown inFIGS.1and2, a plurality of signal lines91of a first signal line group9A, to which sub-pixels8in two adjacent island regions1in the second direction Y are electrically connected, are arranged substantially symmetrically with a center line G in the first direction X of an opening region4corresponding to two adjacent island regions1in the second direction Y as an axis of symmetry, which achieves a symmetrical arrangement of the plurality of signal lines91of the first signal line group9A in the second direction Y, thereby facilitating the wiring of the plurality of signal lines91of the first signal line group9A.

In some other embodiments, as shown inFIGS.1and2, a plurality of signal lines91of a second signal line group9B, to which sub-pixels8in two adjacent island regions1in the first direction X are electrically connected, are arranged substantially symmetrically with a center line F of an opening region4corresponding to the two adjacent island regions1in the first direction X as an axis of symmetry. Moreover, a plurality of signal lines91of a first signal line group9A, to which sub-pixels8in two adjacent island regions1in the second direction Y are electrically connected, are arranged substantially symmetrically with a center line G of an opening region4corresponding to the two adjacent island regions1in the second direction Y as an axis of symmetry.

By arranging in this manner, it is achieved that the plurality of signal lines91of the first signal line group9A are symmetrically arranged in the second direction Y, and the plurality of signal lines91of the second signal line group9B are symmetrically arranged in the first direction X, thereby facilitating the wiring of the pluralities of signal lines91of the first signal line group9A and the second signal line group9B.

Moreover, by arranging that the first signal line group9A is symmetrically arranged and the second signal line group9B is symmetrically arranged, a relative positional relationship of the signal lines91in the same conductive layer remains unchanged, so that a relative positional relationship of portions, electrically connected to the signal lines91, of the sub-pixels8remains unchanged, which facilitates the wiring of the sub-pixels8and also reduces the cost.

In some embodiments, as shown inFIG.1, the opening regions4each are in a shape of a capital H, and each include two side holes5that are parallel to each other and a middle hole6located between the two side holes5. The middle hole6is perpendicular to the two side holes5, and both ends of the middle hole6are communicated with the two side holes5.

It will be understood that, the side holes5of the opening region4may provide a space for stretching deformation in an extension direction of a length of the middle hole6, and the middle hole6of the opening region4may provide a space for stretching deformation in an extension direction of a length of the side holes5. Therefore, the opening region4formed by the side holes5and the middle hole6may provide a space for deformation for the display panel100in multiple stretching directions.

The plurality of opening regions4includes a plurality of first opening regions41and a plurality of second opening regions42. The plurality of first opening regions41are arranged into a plurality of rows extending in the first direction X, and middle holes6of the first opening regions41extend in the first direction X.

The plurality of second opening regions42are arranged into a plurality of column extending in the second direction Y, and middle holes6of the second opening regions42extend in the second direction Y. Two adjacent rows of first opening regions41are staggered to each other, and two adjacent columns of second opening regions42are staggered to each other.

It will be understood that, as shown inFIG.1, the two adjacent rows of first opening regions41are staggered to each other, which means that among the two adjacent rows of first opening regions41, a spacing region between two adjacent first opening regions41in one row is opposite to a middle hole6of a first opening region41in the other row; and the two adjacent columns of second opening regions42are staggered to each other, which means that among the two adjacent columns of second opening regions42, a spacing region between two adjacent second opening regions42in one column is opposite to a middle hole6of a second opening region42in the other column. As a result, a region surrounded by the two first opening regions41in the two adjacent rows and the two second opening regions42in the two adjacent columns forms an island region1.

In some embodiments, as shown inFIG.2, a plurality of signal lines91of a second signal line group9B, to which sub-pixels8in two adjacent island regions1in the first direction X are electrically connected, are arranged substantially symmetrically with a middle hole6of a second opening region42corresponding to the two adjacent island regions1in the first direction X as an axis of symmetry, which achieves a symmetrical arrangement of the plurality of signal lines91of the second signal line group9B in the first direction X, thereby facilitating the wiring of the plurality of signal lines91of the second signal line group9B.

In some other embodiments, as shown inFIG.2, a plurality of signal lines91of a first signal line group9A, to which sub-pixels8in two adjacent island regions1in the second direction Y are electrically connected, are arranged substantially symmetrically with a middle hole6of a first opening region41corresponding to the two adjacent island regions1in the second direction Y as an axis of symmetry, which achieves a symmetrical arrangement of the plurality of signal lines91of the first signal line group9A in the second direction Y, thereby facilitating the wiring of the plurality of signal lines91of the first signal line group9A.

In yet some other embodiments, as shown inFIG.2, a plurality of signal lines91of a second signal line group9B, to which sub-pixels8in two adjacent island regions1in the first direction X are electrically connected, are arranged substantially symmetrically with a middle hole6of a second opening region42corresponding to the two adjacent island regions1in the first direction X as an axis of symmetry. Moreover, a plurality of signal lines91of a first signal line group9A, to which sub-pixels8in two adjacent island regions1in the second direction Y are electrically connected, are arranged substantially symmetrically with a middle hole6of a first opening region41corresponding to the two adjacent island regions1in the second direction Y as an axis of symmetry.

By arranging in this manner, it is achieved that the plurality of signal lines91of the first signal line group9A are symmetrically arranged in the second direction Y, and the plurality of signal lines91of the second signal line group9B are symmetrically arranged in the first direction X, thereby facilitating the wiring of the pluralities of signal lines91of the first signal line group9A and the second signal line group9B.

In some embodiments, as shown inFIG.2, a bridge region2is formed between a side hole5of each opening region4and a middle hole6of another opening region4that is closest to the opening region4. Moreover, bridge regions2may be formed at both sides of the middle hole6, and the two bridge regions2at both sides of the middle hole6may be symmetrical with respect to the middle hole6, so that signal lines91in the two bridge regions2may be symmetrical with respect to the middle hole6.

In some embodiments, as shown inFIG.6, in the first direction X, the display panel100has a first end U and a second end V opposite to each other.

The second signal line group9B includes N data signal lines95, where N is greater than or equal to 2 (N≥2). In the second bridge region22, the N data signal lines95are arranged in a sequence of a first data signal line95-1to an N-th data signal line95-N in the first direction X and along a direction S from the first end U to the second end V of the display panel100.

The island region1is provided with N columns of sub-pixels8, and the N columns of sub-pixels8are arranged in a sequence of a first column of sub-pixels8C-1to an N-th column of sub-pixels8C-N in the first direction X and along the direction S from the first end U to the second end V of the display panel100.

For example, as shown inFIG.5, each island region1is provided with 4 multiply by 2 (4×2) sub-pixels8. That is, the second signal line group9B includes four data signal lines95, the island region1is provided with four columns of sub-pixels8, and each data signal line95is electrically connected to 1 multiply by 2 (1×2) sub-pixels8.

Each column of sub-pixels8is electrically connected to a data signal line95, and a sum of a serial number of the column where each pair of sub-pixels8that are electrically connected is located and a serial number of the data signal line95is equal to (N+1). That is, an i-th column of sub-pixels8is electrically connected to an (N+1−i)-th data signal line95, where i takes a value from 1 to N (i=1 to N).

For example, as shown inFIG.6, in a case where the second signal line group9B includes four data signal lines95, and the island region1is provided with four columns of sub-pixels8, N is equal to 4 (N=4). That is, the sum of the serial number of the column where each pair of sub-pixels8that are electrically connected is located and the serial number of the data signal line95is equal to 5 (i.e., N+1=5).

The first column of sub-pixels are electrically connected to a fourth data signal line, and a sum of a serial number of the column of sub-pixels8and a serial number of the data signal line95is equal to 5 (i.e., 1+4=5).

A second column of sub-pixels are electrically connected to a third data signal line, and a sum of a serial number of the column of sub-pixels8and a serial number of the data signal line95is equal to 5 (i.e., 2+3=5).

A third column of sub-pixels are electrically connected to a second data signal line, and a sum of a serial number of the column of sub-pixels8and a serial number of the data signal line95is equal to 5 (i.e., 3+2=5).

A fourth column of sub-pixels are electrically connected to a first data signal line, and a sum of a serial number of the column of sub-pixels8and a serial number of the data signal line95is equal to 5 (i.e., 4+1=5).

It will be understood that, as for each column of sub-pixels8located in the island region1and the data signal lines95located in the second bridge region22, a distance between the fourth column of sub-pixels and the first data signal line95, a distance between the third column of sub-pixels and the second data signal line95, a distance between the second column of sub-pixels and the third data signal line95, and a distance between the first column of sub-pixels and the fourth data signal line95increase sequentially. Through the electrical connection between the data signal lines95and the columns of sub-pixels8, the data signal lines95are arranged in parallel and at intervals, thereby avoiding the cross-layer jumpers between the data signal lines95.

In some embodiments, as shown inFIG.6, the display panel100further includes a plurality of pin groups70. Each pin group70corresponds to a second signal line group9B. The pin group70includes N pins71, and the N pins71are arranged in a sequence of a first pin71-1to an N-th pin71-N in the first direction X and along the direction S from the first end U to the second end V of the display panel100. The N pins71are electrically connected to N data signal lines95of the corresponding second signal line group9B.

In the pin group70, an i-th pin is configured to be electrically connected to a source driver and receive data signals of an (N+1−i)-th column of sub-pixels8from the source driver, where i takes a value from 1 to N (i=1 to N).

It will be noted that a region where the plurality of island regions1of the display panel100are located is a display area AA, and a peripheral area BB is further provided at least one side of the display area. The plurality of pin groups70are disposed in the peripheral area BB. The plurality of pins71included in each pin group70are arranged in parallel in the first direction X and along the direction S. That is, the plurality of pins71are arranged in parallel in a side of the display area AA proximate to the peripheral area BB. The plurality of pin groups70are used for bonding a flexible circuit board, so that the plurality of pin groups70are electrically connected to the source driver through the flexible circuit board.

For example, as shown inFIG.6, the second signal line group9B includes the four data signal lines95, and each pin group70includes four pins71. In the first direction X and along the direction S from the first end U to the second end V of the display panel100, the first data signal line is electrically connected to the first pin. The first pin is configured to receive data signals of the fourth column of sub-pixels8from the source driver.

The second data signal line is electrically connected to a second pin, and the second pin is configured to receive data signals of the third column of sub-pixels8from the source driver.

The third data signal line is electrically connected to a third pin, and the third pin is configured to receive data signals of the second column of sub-pixels8from the source driver.

The fourth data signal line is electrically connected to a fourth pin, and the fourth pin is configured to receive data signals of the first column of sub-pixels8from the source driver.

In some embodiments, as shown inFIG.6, the display panel100further has a plurality of pin regions7. Two pin groups70corresponding to two second signal line groups9B that are arranged substantially symmetrically are provided in a same pin region7.

For example, two pin groups70in the same pin region7are electrically connected to a same source driver. That is, every two adjacent columns of sub-pixels8receive data signals output from the same source driver.

It will be understood that the plurality of pin regions7are disposed in the peripheral area BB, and are arranged in parallel in the first direction X and along the direction S. That is, the plurality of pin regions7are arranged in parallel in the side of the display area AA proximate to the peripheral area BB.

In some embodiments, as shown inFIG.6, each signal line91of the second signal line group9B is electrically connected to sub-pixels8in an island region1after being bent twice.

For example, the signal lines91of the second signal line group9B are bent twice by 90 degrees in a clockwise direction, or bent twice by 90 degrees in a counterclockwise direction, and extend into the island region1in a way of routing around the sub-pixels8, so that the plurality of signal lines91of the second signal line group9B are arranged in parallel and at intervals in the same conductive layer.

In some other embodiments, as shown inFIG.6, each signal line91of the first signal line group9A is electrically connected to sub-pixels8in an island region1after being bent twice.

For example, the signal lines91of the first signal line group9A are bent twice by 90 degrees in a same direction, and extend into the island region1in the way of routing around the sub-pixels8, so that the plurality of signal lines91of the first signal line group9A are arranged in parallel and at intervals in the same conductive layer.

In yet some other embodiments, as shown inFIG.6, each signal line91of the second signal line group9B is electrically connected to sub-pixels8in an island region1after being bent twice, and each signal line91of the first signal line group9A is electrically connected to sub-pixels8in another island region1after being bent twice.

For example, signal lines91of both the first signal line group9A and the second signal line group9B are bent twice by 90 degrees in a same direction, and extend into the island region1in the way of routing around the sub-pixels8, so that the plurality of signal lines91of both the first signal line group9A and the second signal line group9B are arranged in parallel and at intervals in the same conductive layer.

In some embodiments, as shown inFIGS.1,7and8, the bridge region2may be in a shape of a rectangle, a capital U, or a capital S. By designing bridge regions2in different shapes, it may be possible to improve tensile properties of the bridge regions2of the display panel100.

Each island region1is connected to four bridge regions2, and the four bridge regions2surround the island region1. A center1A of the island region1serves as a center of symmetry, and a plurality of signal lines in a plurality of bridge regions2connected to each island region1are arranged symmetrically with respect to the center, so that the signal lines91may be reasonably arranged in the bridge regions2of different shapes, thus facilitating that the signal lines are arranged in parallel and at intervals in the same conductive layer.

Some embodiments of the present disclosure provide a display device200, as shown inFIG.9, including the display panel100in any one of the above embodiments. The display device200may be an organic light-emitting diode (OLED) display device, such as an active matrix organic light-emitting diode (AMOLED) display device.

The display device200may be any device that displays images whether in motion (e.g., a video) or stationary (e.g., a static image), and whether literal or graphical. More specifically, it is anticipated that the described embodiments may be implemented in or associated with a variety of electronic devices. The variety of electronic devices may be, for example (but not limited to), mobile phones, wireless devices, personal data assistants (PDAs), hand-held or portable computers, global positioning system (GPS) receivers/navigators, cameras, MPEG-4 Part 14 (MP4) video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automobile displays (e.g., odometer displays), navigators, cockpit controllers and/or displays, camera view displays (e.g., rear view camera displays in vehicles), electronic photos, electronic billboards or signs, projectors, building structures, and packaging and aesthetic structures (e.g., a display for an image of a piece of jewelry).