Chip package and manufacturing method thereof

A chip package including a circuit substrate, a chip, a B-staged adhesive layer, a leadframe, a number of first bonding wires, a number of second bonding wires, and a number of third bonding wires. The chip is disposed on the circuit substrate. The B-staged adhesive layer is disposed on the circuit substrate. The leadframe is disposed on the circuit substrate and includes a number of leads. Portions of the leads are embedded in the B-staged adhesive layer, and an end of each of the leads is exposed by the B-staged adhesive layer. The first bonding wires are electrically connected between the chip and the circuit substrate. The second bonding wires are electrically connected between the chip and the leads. The third bonding wires are electrically connected between the leads and the circuit substrate. In addition, a manufacturing method of a chip package is also provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 97145557, filed Nov. 25, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the invention relates to a chip package and a manufacturing method thereof.

2. Description of Related Art

The production of integrated circuit (IC) devices is mainly divided into three stages including IC design, IC fabrication and IC package.

During the IC fabrication, a chip is manufactured by performing steps of wafer fabrication, IC formation, wafer sawing, and so on. A wafer has an active surface, which generally refers to a surface equipped with active devices. After the IC inside the wafer is completely formed, a plurality of bonding pads are further disposed on the active surface of the wafer, such that a chip formed by sawing the wafer may be externally electrically connected to a carrier through the bonding pads. The carrier is, for example, a leadframe or a package substrate. In an alternative, the carrier is constituted by a leadframe and a package substrate. The chip can be connected to the carrier by wire bonding or by flip chip bonding, such that the bonding pads on the chip can be electrically connected to contacts of the carrier, thereby forming a chip package.

In general, tapes are used to adhere the leadframe onto a package substrate in the process of manufacturing the chip package. The tapes must be arranged on different regions of a surface of the package substrate in accordance with the shape of the leadframe, which is rather time-consuming and cost-ineffective. In addition, the costly tapes bring about an increase in manufacturing costs of the chip package.

SUMMARY OF THE INVENTION

The present invention is directed to a chip package having relatively low manufacturing costs.

The present invention is directed to a manufacturing method of a chip package. The manufacturing method is comparatively time-consuming.

In the present invention, a chip package including a circuit substrate, a chip, a B-staged adhesive layer, a leadframe, a plurality of first bonding wires, a plurality of second bonding wires, and a plurality of third bonding wires is provided. The chip is disposed on the circuit substrate. Besides, the B-staged adhesive layer is disposed on the circuit substrate. Additionally, the leadframe is disposed on the circuit substrate. Here, the leadframe includes a plurality of leads. Portions of the leads are embedded in the B-staged adhesive layer, and an end of each of the leads is exposed by the B-staged adhesive layer.

According to an embodiment of the present invention, the B-staged adhesive layer having a continuous annular pattern surrounds the chip and encapsulates portions of the leads.

According to an embodiment of the present invention, the B-staged adhesive layer has a plurality of non-continuous block patterns, and the B-staged adhesive layer having the non-continuous block patterns respectively encapsulates a portion of one of the leads.

According to an embodiment of the present invention, the leadframe is an lead-on-chip type leadframe. In another words, the leadframe does not have any die pad.

According to an embodiment of the present invention, the chip package further includes a molding compound disposed on the circuit substrate. The molding compound encapsulates the chip, the B-staged adhesive layer, the leadframe, the first bonding wires, the second bonding wires, and the third bonding wires.

In the present invention, a manufacturing method of a chip package is also provided. In the manufacturing method, first, a B-staged adhesive layer is formed on a circuit substrate, and a leadframe is adhered onto the circuit substrate through the B-staged adhesive layer. The leadframe includes a plurality of leads. Portions of the leads are embedded in the B-staged adhesive layer, and an end of each of the leads is exposed by the B-staged adhesive layer. A chip is then attached onto the circuit substrate. Next, a plurality of first bonding wires are formed, so as to electrically connect the chip and the circuit substrate; a plurality of second bonding wires are formed, so as to electrically connect the chip and the ends of the leads; and a plurality of third bonding wires are formed, so as to electrically connect the ends of the leads and the circuit substrate.

According to an embodiment of the present invention, a method of adhering the leadframe onto the circuit substrate through the B-staged adhesive layer includes first forming a two-stage adhesive layer on the circuit substrate. The two-stage adhesive layer is then B-stagized to form the B-staged adhesive layer. Next, the leadframe is pressed into the B-staged adhesive layer, and the B-staged adhesive layer is then completely cured.

According to an embodiment of the present invention, the manufacturing method of the chip package further includes forming a molding compound on the circuit substrate, such that the molding compound encapsulates the chip, the B-staged adhesive layer, the leadframe, the first bonding wires, the second bonding wires, and the third bonding wires.

In the present invention, the leadframe is adhered onto the circuit substrate through the B-staged adhesive layer. The formation of the B-staged adhesive layer is not time-consuming, and costs of fabricating the B-staged adhesive layer are relatively low. As such, the present invention is contributive to reduction of manufacturing time and costs.

In order to make the aforementioned and other features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

DESCRIPTION OF EMBODIMENTS

FIG. 1Ais a schematic cross-sectional view illustrating a chip package according to an embodiment of the present invention. Referring toFIG. 1A, the chip package100of the present embodiment includes a circuit substrate110, a chip120, and a B-staged adhesive layer130. The chip120is disposed on the circuit substrate110. The B-staged adhesive layer130is disposed on the circuit substrate110. The leadframe140is disposed on the circuit substrate110, wherein the leadframe140includes a plurality of leads142. Portions of the leads142are embedded in the B-staged adhesive layer130, and an end E of each lead142is exposed by the B-staged adhesive layer130.

A distance d between the leads142and the circuit substrate110can be changed by adjusting the embedded degree of the leads142in the B-staged adhesive layer130. According to the pertinent art, the substrate and the leads are adhered together with use of tapes. By contrast, a contact area between the leads142and the B-staged adhesive layer130is relatively large in the present invention, and thereby the bonding strength between the leads142and the circuit substrate110can be increased by using the B-staged adhesive layer130to encapsulate the leads142.

Besides, in the conventional chip package, the height of the bonding wires is frequently reduced by the die pad having a down-set design, such that the molding compound located at one side of the leadframe having the bonding wires and at the other side of the leadframe having no bonding wires can have consistent height. As such, the conventional chip package can be prevented from being warped when the problem in connection with the inconsistent height of the molding compound located at respective sides of the leadframe is resolved. Note that the height difference between the die pad and the leads in the leadframe having the down-set die pad remains unchanged and is not likely to be modified. On the contrary, in the present embodiment, the leads142and the circuit substrate110has the distance d therebetween, and therefore the same effect generated in the down-set die pad can also be achieved in the present embodiment. Moreover, in comparison with the conventional down-set die pad, the distance d between the leads142and the circuit substrate110of the present embodiment can be adjusted by controlling the embedded degree of the leads142in the B-staged adhesive layer130, thus contributing to more varieties in terms of design and arrangement.

Referring toFIG. 1A, in the present embodiment, the chip package100further includes a plurality of first bonding wires150, a plurality of second bonding wires160, and a plurality of third bonding wires170. The first bonding wires150are electrically connected between the chip120and the circuit substrate110. The second bonding wires160are electrically connected between the chip120and the ends E of the leads142. The third bonding wires170are electrically connected between the ends E of the leads142and the circuit substrate110.

To be more specific, the chip120has an active surface S1, a plurality of bonding pads P located on the active surface S1, and a back surface S2. The circuit substrate110also has a plurality of bonding pads P disposed thereon. The chip package100further includes a chip bonding layer180interposed between the back surface S2of the chip120and the circuit substrate110. The first bonding wires150are electrically connected between some of the bonding pads P of the chip120and some of the bonding pads P of the circuit substrate110. The second bonding wires160are electrically connected between some of the bonding pads P of the chip120and the ends E of the leads142.

Nonetheless, the electrical connecting manner of the chip package100is not limited in the present invention. That is to say, in addition to the above-mentioned electrical connecting manner, the chip package100of the present invention can be arranged in other ways to electrically connect various devices.

In the present embodiment, the leadframe140is not equipped with any die pad. The chip package100further includes a molding compound190disposed on the circuit substrate110. Here, the molding compound190encapsulates the chip120, the B-staged adhesive layer130, the leadframe140, the first bonding wires150, the second bonding wires160, and the third bonding wires170.

FIG. 1Bis a schematic top view illustrating the chip package ofFIG. 1A. Referring toFIG. 1B, the B-staged adhesive layer130ofFIG. 1Ahaving a continuous annular pattern surrounds the chip120and encapsulates portions of the leads142.

In the present embodiment, the bonding pads P on the chip120can be electrically connected to one of the leads142simply through the second bonding wires160. Note that the bonding pads P on the circuit substrate110can be electrically connected to one another through internal circuits (not shown) of the circuit substrate110. Thereby, the bonding pads P on the chip120can be electrically connected to one of the leads142sequentially through the first bonding wires150, one of the pads P on the circuit substrate110, the internal circuits of the circuit substrate110, another one of the bonding pads P on the circuit substrate110, and the third bonding wires170. In other words, since the arrangement of the bonding pads P on the chip120and the leads142remains unchanged and is unlikely to be modified, the bonding pads P on the chip120and the leads142disposed slightly away from the bonding pads P are apt to be electrically connected to one another through the internal circuits of the circuit substrate110.

FIG. 2is a schematic top view illustrating a chip package according to another embodiment of the present invention. Referring toFIG. 2, in comparison with the B-staged adhesive layer130of the chip package100depicted inFIG. 1B, a B-staged adhesive layer130′ of a chip package100′ in the present embodiment has a plurality of non-continuous block patterns. The B-staged adhesive layer130′ having the block patterns respectively encapsulates a portion of one of the leads142or portions of the leads142.

A manufacturing method of the chip package100depicted inFIG. 1Ais elaborated hereinafter.FIGS. 3A to 3Eare schematic cross-sectional views illustrating a manufacturing method of the chip package depicted inFIG. 1A. First, referring toFIG. 3A, a circuit substrate110having a plurality of bonding pads P is provided, and a two-stage adhesive layer X is formed on the circuit substrate110. Next, as indicated inFIG. 3B, the two-stage adhesive layer X is B-stagized to form a B-staged adhesive layer130.

Note that the two-stage adhesive layer X is made of a thermosetting adhesive material having two-stage properties (A-B stage and B-C stage), and therefore the B-staged adhesive layer130is formed after the two-stage adhesive layer X is B-stagized.

According to the present embodiment, the B-staged adhesive layer130can be model no. 8008, model no. 8008HT, model no. 6200, model no. 6201, and model no. 6202C supplied by ABLESTIK. In addition, the B-staged adhesive layer130can also be model no. SA-200-6, model no. SA-200-10 (both provided by HITACHI Chemical CO., Ltd.), or other similar B-staged adhesives, for example.

After that, referring toFIG. 3C, a leadframe140is provided. The leadframe140is pressed into the B-staged adhesive layer130, and the B-staged adhesive layer130is further cured. The leadframe140includes a plurality of leads142. Portions of the leads142are embedded in the B-staged adhesive layer130, and an end E of each lead142is exposed by the B-staged adhesive layer130.

Thereafter, referring toFIG. 3D, a chip120having an active surface S1, a back surface S2, and a plurality of bonding pads P disposed on the active surface S1is provided. A chip bonding layer180is then formed on the circuit substrate110, and the back surface S2of the chip120is adhered to the circuit substrate110through the chip bonding layer180. In the present embodiment, the chip bonding layer180can be coated onto the back surface S2of the chip120, so as to bond the chip120to the circuit substrate110.

Next, referring toFIG. 3E, first bonding wires150, second bonding wires160, and third bonding wires170are formed. One of the bonding pads P on the active surface S1of the chip120is electrically connected to one of the bonding pads P on the circuit substrate110through one of the first bonding wires150. Another one of the bonding pads P on the active surface S1of the chip120is electrically connected to an end E of one of the leads142through one of the second bonding wires160. Besides, an end E of one of the leads142is electrically connected to another one of the bonding pads P on the circuit substrate110through one of the third bonding wires170. In the present embodiment, the sequence of forming the first bonding wires150, the second bonding wires160, and the third bonding wires170is not restricted. Afterwards, referring toFIG. 1A, a molding compound190is formed on the circuit substrate110to encapsulate the chip120, the B-staged adhesive layer130, the leadframe140, the first bonding wires150, the second bonding wires160, and the third bonding wires170. Thereby, the chip package100is formed.

It should be mentioned that the number of the first bonding wires150, the second bonding wires160, and the third bonding wires170is determined upon the number of the bonding pads P on the chip120according to the present embodiment. The present invention does not pose a limitation to the number of the first bonding wires150, the second bonding wires160, and the third bonding wires170.

To sum up, the leadframe of the present invention is adhered onto the circuit substrate through the B-staged adhesive layer, while the leadframe in the conventional chip package is attached onto the circuit substrate by using tapes. The disposition of the B-staged adhesive layer is not time-consuming. Moreover, costs of fabricating the B-staged adhesive layer are lower than the costs of tapes, and the thickness of the B-staged adhesive layer is less than that of the tapes. As such, the present invention is contributive to reduction of manufacturing time, manufacturing costs, and the entire thickness of the chip package. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.