Display panel

Provided is a display panel, including: a display region having an anomaly shape; a plurality of first test transistors; a plurality of second test transistors; and test control signal supply wiring through which a control signal for turning on or off the first and second test transistors is to be supplied, in which first test transistors connected to gate lines crossing an anomaly part of the anomaly shape and second test transistors connected to data lines crossing the anomaly part are arranged in other patterns than a straight line, and in which the test control signal supply wiring includes first test control signal supply wiring, which is connected to control electrodes of the plurality of first test transistors, and second test control signal supply wiring, which is branched out from the first test control signal supply wiring and is connected to control electrodes of the plurality of second test transistors.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese application JP 2015-101963 filed on May 19, 2015, the content of which is hereby incorporated by reference into this application.

BACKGROUND

1. Technical Field

This application relates to a display panel, and more particularly, to a display panel having an anomaly shape.

2. Description of the Related Art

Display panels such as liquid crystal panels have various uses in recent years, for example, as a panel for displaying meters and similar instruments on a vehicle (an instrument panel). With the diversification of uses, display panels (or display regions) of anomaly shapes which have other outer shapes than a quadrangular one are being proposed. Examples of display panels having an anomaly shape include display panels in which at least one of the four corner portions is arc-shaped, and display panels that overall have a trapezoidal shape, an oval shape, a circular shape, or a polygonal shape. A display panel having an anomaly shape is disclosed in Japanese Patent Application Laid-open No. 2008-216894.

Hitherto, there have also been proposed display panels having a configuration for detecting a wiring defect in gate lines, data lines, and other wiring lines. For example, a display panel includes a plurality of test transistors connected to gate lines and a plurality of test transistors connected to data lines. The test transistors are turned on in a step of testing the display panel, and test signals (test gate signals and test data signals) are input to detect wiring breakage or the like based on a state in which a pixel corresponding to a test wiring line is on.

SUMMARY

In general, the test transistors and test wiring lines through which the test signals are supplied are arranged in a frame region around the display region. This makes the frame region large in size in a display panel having the configuration for conducting the test described above. In particular, employing the configuration for conducting the test in a display panel having an anomaly shape complicates the arrangement of the test transistors and the test wiring lines, which gives rise to additional problems besides the problem of a large frame region, for example, a failure to conduct an accurate test due to an unintended contact between one test wiring line and another.

The present application has been made in view of the problems described above, and an object of the present application is therefore to provide a display panel that includes a display region having an anomaly shape and test transistors and test wiring lines arranged in a frame region, and is capable of reducing the area of the frame region and also executing a test of the display panel without fail.

In order to solve the above-mentioned problems, according to one embodiment of this application, there is provided a display panel, including: a display region having an anomaly shape; a plurality of gate lines extending in a row direction; a plurality of data lines extending in a column direction; a plurality of first test transistors connected to the plurality of gate lines; a plurality of second test transistors connected to the plurality of data lines; and test control signal supply wiring through which a control signal for turning on the plurality of first test transistors and the plurality of second test transistors and a control signal for turning off the plurality of first test transistors and the plurality of second test transistors are to be supplied, in which first test transistors among the plurality of the first test transistors connected to gate lines crossing an anomaly part of the anomaly shape of the display region among the plurality of gate lines are arranged in other patterns than a straight line, and second test transistors among the plurality of the second test transistors connected to data lines crossing the anomaly part among the plurality of date lines are arranged in other patterns than a straight line, the anomaly part being formed in a non-straight line shape or a curve line shape and in which the test control signal supply wiring includes first test control signal supply wiring, which is connected to control electrodes of the plurality of first test transistors, and second test control signal supply wiring, which is branched out from the first test control signal supply wiring and is connected to control electrodes of the plurality of second test transistors.

In the display panel according to the one embodiment of this application, when the plurality of data lines are longer than the plurality of gate lines, the second test transistors among the plurality of the second test transistors connected to the data lines crossing the anomaly part may be placed closer to outside than the first test transistors among the plurality of the first test transistors connected to the gate lines crossing the anomaly part are to the outside, and, when the plurality of gate lines are longer than the plurality of data lines, the first test transistors among the plurality of the first test transistors connected to the gate lines crossing the anomaly part may be placed closer to the outside than the second test transistors among the plurality of the second test transistors connected to the data lines crossing the anomaly part are to the outside.

In the display panel according to the one embodiment of this application, the second test control signal supply wiring may be placed closer to the outside than the first test control signal supply wiring is to the outside.

In the display panel according to the one embodiment of this application, the first test control signal supply wiring may be placed closer to the outside than the second test control signal supply wiring is to the outside.

In the display panel according to the one embodiment of this application, a branching point of the first test control signal supply wiring and the second test control signal supply wiring may be located closer to outside than a first gate line, which is arranged at a far end of the display region as an outermost line among the plurality of gate lines, is to the outside.

In the display panel according to the one embodiment of this application, a branching point of the first test control signal supply wiring and the second test control signal supply wiring may be located between a first gate line, which is arranged at a far end of the display region as an outermost line among the plurality of gate lines, and a second test transistor that is closest to the first gate line among the plurality of second test transistors that are closer to the outside than the first gate line is to the outside.

In the display panel according to the one embodiment of this application, the plurality of second test transistors may be grouped into a group of at least two second test transistors, and the at least two second test transistors in each group may be aligned in a single file in the row direction, and a plurality of groups of the at least two second test transistors connected to the data lines crossing the anomaly part may be arranged in other patterns than a straight line.

In the display panel according to the one embodiment of this application, the plurality of first test transistors may be grouped into a group of at least two first test transistors, and the at least two first test transistors in each group may be aligned in a single file in the column direction, and a plurality of groups of the at least two first test transistors connected to the gate lines crossing the anomaly part may be arranged in other patterns than a straight line.

In the display panel according to the one embodiment of this application, the plurality of groups of the at least two second test transistors may each be arranged between two adjacent gate lines out of the plurality of gate lines.

In the display panel according to the one embodiment of this application, the plurality of groups of the at least two first test transistors may each be arranged between two adjacent data lines out of the plurality of data lines.

In the display panel according to the one embodiment of this application, a branching point of the first test control signal supply wiring and the second test control signal supply wiring may be located along a center line in the row direction of the display region.

The display panel according to the one embodiment of this application may further include off-voltage transmission wiring through which an off-voltage for fixing the plurality of first test transistors and the plurality of second test transistors to an off state is to be supplied to the control electrodes of the plurality of first test transistors and the plurality of second test transistors, and the off-voltage transmission wiring may be electrically connected to the first test control signal supply wiring.

In the display panel according to the one embodiment of this application, a connection point where the off-voltage transmission wiring is connected to the first test control signal supply wiring and a branching point of the first test control signal supply wiring and the second test control signal supply wiring may be located so as to be symmetrical with respect to the row direction in the display region.

In the display panel according to the one embodiment of this application, a connection point where the off-voltage transmission wiring is connected to the first test control signal supply wiring and a branching point of the first test control signal supply wiring and the second test control signal supply wiring may be located at the same position.

According to one embodiment of this application, there is provided a display panel, including: a display region having an anomaly shape; a plurality of gate lines extending in a row direction; a plurality of data lines extending in a column direction; a plurality of first test transistors connected to the plurality of gate lines; and a plurality of second test transistors connected to the plurality of data lines, in which, out of a set of first test transistors among the plurality of the first test transistors connected to gate lines crossing an anomaly part of the anomaly shape of the display region among the plurality of gate lines are arranged in other patterns than a straight line and a set of second test transistors among the plurality of the second test transistors connected to data lines crossing the anomaly part among the plurality of date lines are arranged in other patterns than a straight line, one set of the test transistors is placed closer to outside than another set of the test transistors is to the outside, and at least one test transistor out of the another set of the test transistors is arranged between two adjacent wiring lines, out of the plurality of gate lines and the plurality of data lines, that are connected to the one set of the test transistors, the anomaly part being formed in a non-straight line shape or a curve line shape.

DETAILED DESCRIPTION

An embodiment of the present application is described below with reference to the drawings. The embodiment of the present application takes a liquid crystal display device as an example of a display device of the present application. However, the present application is not limited thereto and the display device may be an organic EL display device, for example.

FIG. 1is a plan view for illustrating a schematic configuration of the liquid crystal display device according to this embodiment. A liquid crystal display device100includes a display panel10, a data line drive circuit30, a gate line drive circuit40, and a backlight unit (not shown). The data line drive circuit30may include a plurality of source driver ICs, and may be provided outside of the display panel10. The gate line drive circuit40may include a plurality of gate driver ICs, and may be provided outside of the display panel10. Although not shown, a timing controller configured to control the operation of the data line drive circuit30and the gate line drive circuit40may be provided inside or outside of the display panel10.

The display panel10is roughly divided into a display region10awhere images are displayed and a frame region10baround the display region10a. The display region10ahas four corner portions, and of the four corner portions, two upper corner portions are arc-shaped. The shape of the display region10ais not limited to the one illustrated inFIG. 1, and may be trapezoidal, oval, circular, or polygonal, for example. In short, the display region10ais formed to have an anomaly shape. The display panel10has an anomaly shape as well to accommodate the shape of the display region10a. In the liquid crystal display device100according to this embodiment, at least one of the display panel10and the display region10aneeds to have an anomaly shape. For example, the liquid crystal display device100illustrated inFIG. 2includes the display panel10in which two corner portions are arc-shaped and the display region10athat is formed into an oval shape. The liquid crystal display device100illustrated inFIG. 3includes the display panel10in which all four corner portions are arc-shaped and the display region10athat is formed into a quadrangular shape.

FIG. 4is an equivalent circuit diagram for illustrating a schematic configuration of the display device10. The display panel10includes a plurality of data lines11(DL1, DL2, . . . ) extending in a column direction, and a plurality of gate lines12(GL1, GL2, . . . ) extending in a row direction. A thin film transistor13(TFT) is formed at each intersecting portion between each data line11and each gate line12. Each data line11is connected to the data line drive circuit30. Each gate line12is connected to the gate line drive circuit40.

The display panel10includes a plurality of pixels14arranged in matrix (in the row direction and the column direction) so as to correspond to each intersecting portion between each data line11and each gate line12. Note that, although not shown, the display panel10includes a thin film transistor substrate (TFT substrate), a color filter substrate (CF substrate), and a liquid crystal layer sandwiched between both the substrates. The TFT substrate includes a plurality of pixel electrodes15arranged so as to correspond to the respective pixels14. The CF substrate includes a common electrode16common to the respective pixels14. Note that, the common electrode16may be formed on the TFT substrate.

Each data line11is supplied with a data signal (data voltage) from the line drive circuit30. Each gate line12is supplied with gate signals (a gate on-voltage and a gate off-voltage) from the gate line drive circuit40. The common electrode16is supplied with a common voltage Vcom from a common electrode drive circuit (not shown) via common wiring60. When a gate on-voltage is supplied to the gate line12, the thin film transistor13connected to the gate line12is turned on so that the data voltage is supplied to the pixel electrode15via the data line11connected to the thin film transistor13. An electric field is generated by the difference between the data voltage supplied to the pixel electrode15and the common voltage Vcom supplied to the common electrode16. This electric field is used to drive the liquid crystal and control the transmittance of light from the backlight unit. In this manner, an image is displayed. Note that, in the case of color display, the color display is realized by supplying desired data voltages to the data lines11connected to the respective pixel electrodes15of the pixels14corresponding to respective red color, green color, and blue color formed of stripe-shaped color filters.

The liquid crystal display device100has a configuration for detecting a defect in the display panel10, for example, a wiring breakage in the data lines11and the gate lines12. Details of this configuration are described below.

FIG. 5is a plan view for illustrating a detailed configuration of the display panel10. For conveniences' sake, the configuration illustrated inFIG. 5is the one that the display panel10has before the data line drive circuit30and the gate line drive circuit40are installed. The frame region10bof the display panel10includes a plurality of test transistors17(first test transistors) having one set of conducting electrodes (source/drain electrodes) connected to the gate lines12, a plurality of test transistors18(second test transistors) having one set of conducting electrodes (source/drain electrodes) connected to the data lines11, test control signal supply wiring19through which control electrodes (gate electrodes) are supplied with test control signals for controlling the turning on/off of the test transistors17and18, test gate signal supply wiring21through which test gate signals Ge (a gate on-voltage and a gate off-voltage) are supplied to the other set of the conducting electrodes of the test transistors17that are in even-numbered rows, test gate signal supply wiring22through which test gate signals Go (a gate on-voltage and a gate off-voltage) are supplied to the other set of the conducting electrodes of the test transistors17that are in odd-numbered rows, a plurality of test data signal supply wiring lines23through which a test data signal DE is supplied to the other set of the conducting electrodes of the test transistors18that are in even-numbered columns, and a plurality of test data signal supply wiring lines24through which a test data signal DO is supplied to the other set of the conducting electrodes of the test transistors18that are in odd-numbered columns. In a region next to the shorter side of the display region10aon the left (the left side), the test transistors17are arranged in straight lines along the shorter side. In a region next to the arc-shaped corner portion that extends from the shorter side toward the upper longer side (the upper side) of the display region10a, the test transistors17are arranged in a staircase pattern instead of straight lines. One test transistor17is connected to each gate line12. In a region next to the longer side of the display region10a, the test transistors18are arranged in straight lines along the longer side. In regions next to the two arc-shaped corner portions that extend from the longer side toward the left shorter side and right shorter side of the display region10a, the test transistors18are arranged in a staircase pattern instead of straight lines. One test transistor18is connected to each data line11. Details of the arrangement of the test transistors17and18are described later.

It is preferred to place the test transistors that are arranged along the shorter side of the display region10acloser to the outside than the test transistors that are arranged along the longer side of the display region10aare to the outside. InFIG. 5, the test transistors17, which are arranged along the shorter side, are placed closer to the outside than the test transistors18, which are arranged along the longer side, are to the outside. In a peripheral portion of the frame region of the display panel10(inFIG. 5, the right-hand side of the lower side of the display panel10), a terminal VOFF (an off-voltage input terminal) is provided through which a gate off-voltage Voff for turning the test transistors17and18off is input. The gate off-voltage Voff may be output from the common electrode drive circuit, which is installed in the display panel10.

The test control signal supply wiring19has one end connected to a control signal input pad TR, which is provided on the left-hand side of the lower side of the display panel10, and branches into two near a corner portion of the upper side of the display panel10. Specifically, the test control signal supply wiring19is comprised of first test control signal supply wiring19aand second test control signal supply wiring19b. The first test control signal supply wiring19aextends from the control signal input pad TR along the shape of the display region10a, i.e., along the left side of the display region10a, the upper left arc-shaped corner portion, the upper side of the display region10a, and the upper right arc-shaped corner portion. The second test control signal supply wiring19bbranches from the first test control signal supply wiring19aat a point (a branching point S1), and doubles back at the branching point S1to extend along the shape of the display region10a, i.e., along the upper left arc-shaped corner portion and the left side of the display region10a. The first test control signal supply wiring19ais connected to control electrodes of the plurality of test transistors18, which are connected to the plurality of data lines11. The second test control signal supply wiring19bis connected to control electrodes of the plurality of test transistors17, which are connected to the plurality of gate lines12. The first test control signal supply wiring19aand the second test control signal supply wiring19bare formed in the same layer.

It is preferred for the branching point S1to be located in the vicinity of the vertex of the arc-shaped corner portion (on the upper side of the display surface), specifically, a connection point between the upper side of the display region10awhich is a straight line and the arc-shaped side, for example. It is also preferred to position the branching point S1closer to the outside than the gate line12that is arranged at the far end of the display region10aas the outermost line among the plurality of gate lines12(a first gate line GL1) (here, above the topmost gate line12) is to the outside as illustrated inFIG. 5. This can prevent a contact between the second test control signal supply wiring19b, which is led out of the branching point S1, and another wiring line. The branching point S1that is preferred is located as illustrated inFIG. 5between the first gate line GL1and the test transistor18that is closest to the first gate line GL1among a plurality of test transistors18that are closer to the outside than the first gate line GL is to the outside (here, above the first gate line GL). This can minimize the length of the second test control signal supply wiring19b. The position of the branching point S1is not limited to the one described above.

When a test control signal is supplied to the test control signal supply wiring19from the outside via the control signal input pad TR, the test transistors17and18are all turned on or off at once.

The test gate signal supply wiring21is connected to a gate signal input pad GE, which is arranged in the left-hand side of the lower side of the display panel10. The test gate signal supply wiring22is connected to a gate signal input pad GO, which is arranged in the left-hand side of the lower side of the display panel10. The test gate signal supply wiring21is electrically connected via a plurality of test transistors17that are in even-numbered columns to a plurality of gate lines12that are in even-numbered columns. The test gate signal supply wiring22is electrically connected via a plurality of test transistors17that are in odd-numbered columns to a plurality of gate lines12that are in odd-numbered columns. When the test transistors17are turned on and a test gate signal is supplied to the test gate signal supply wiring21from the outside via the gate signal input pad GE, the test gate signal is supplied to the plurality of gate lines12that are in even-numbered columns via the test transistors17that are in even-numbered columns. When the test transistors17are turned on and a test gate signal is supplied to the test gate signal supply wiring22from the outside via the gate signal input pad GO, the test gate signal is supplied to the plurality of gate lines12that are in odd-numbered columns via the test transistors17that are in odd-numbered columns.

The test data signal supply wiring23is connected to a data signal input pad DE, which is provided on the left-hand side of the lower side of the display panel10. The test data signal supply wiring24is connected to a data signal input pad DO, which is provided on the left-hand side of the lower side of the display panel10. The test data signal supply wiring23is electrically connected to a plurality of data lines11that are in even-numbered columns via a plurality of test transistors18that are in even-numbered columns. The test data signal supply wiring24is electrically connected to a plurality of data lines11that are in odd-numbered columns via a plurality of test transistors18that are in odd-numbered columns. When the test transistors18are turned on and a test data signal is supplied from the outside to the test data signal supply wiring23via the data signal input pad DE, the test data signal is supplied to the plurality of data lines11that are in even-numbered columns via the test transistors18that are in even-numbered columns. When the test transistors18are turned on and a test data signal is supplied from the outside to the test data signal supply wiring24via the data signal input pad DO, the test data signal is supplied to the plurality of data lines11that are in odd-numbered columns via the test transistors18that are in odd-numbered columns.

The pads described above are included in a test signal input pad25, which is arranged in the peripheral portion of the display panel10(inFIG. 5, on the left-hand side of the lower side of the display panel10). The position of the test signal input pad25is not limited, and how many test signal input pads25are provided is not limited. Test equipment (not shown) configured to generate and output various test signals is connected to the test signal input pad25.

FIG. 6is an equivalent circuit diagram in which the upper left corner portion ofFIG. 5is enlarged. For conveniences' sake, the test control signal supply wiring19is omitted fromFIG. 6. As illustrated inFIG. 6, the plurality of test transistors17are grouped into a group of four, and the four test transistors17in each group are aligned in a single file in the column direction. A plurality of groups of test transistors17are arranged in an oblique direction in a region next to the arc-shaped corner portion of the display region10a. The plurality of test transistors18are grouped into a group of six, and the six test transistors18in each group are aligned in a single file in the row direction. A plurality of groups of test transistors18are arranged in an oblique direction in the region next to the arc-shaped corner portion of the display region10a. Four gate lines12that are associated with one group of test transistors17are arranged so as to pass through a region between two groups of test transistors18that are adjacent to each other in the column direction. One group of test transistors18is arranged in a region between two groups of test transistors17that are adjacent to each other in the column direction. Groups of test transistors17are alternated with groups of test transistors18in the column direction. The number of test transistors that are included in a group is not limited.

FIG. 7is a detailed plan view in which the upper left corner portion ofFIG. 5is enlarged. The configuration illustrated inFIG. 7differs from the configuration illustrated inFIG. 6in the arrangement of the test transistors17and18. In the configuration ofFIG. 7, one group of test transistors18(eight test transistors18constitute one group inFIG. 7) is arranged in a region between two gate lines12connected to two test transistors17that are adjacent to each other in the column direction. A plurality of gate lines12(gate lines12ato12fofFIG. 7) associated with two groups of test transistors17that are adjacent to each other in the column direction are arranged in a region between two groups of test transistors18that are adjacent to each other in the column direction.

Of the data lines and the gate lines, wiring lines connected to the test transistors that are arranged along the shorter side of the display region10aare longer than wiring lines connected to the test transistors that are arranged along the longer side of the display region10a. The size (channel width) of a transistor in this case is larger when the length of a wiring line connected to the transistor is greater. An increase in transistor size increases the chance for interference between wiring lines. It is therefore preferred in this embodiment to place the test transistors that are arranged along the shorter side of the display region10acloser to the outside than the test transistors that are arranged along the longer side of the display region10aare to the outside.

Specifically, the gate lines12, which are connected to the test transistors17arranged along the shorter side of the display region10a, are longer than the data lines11, which are connected to the test transistors18arranged on the longer side of the display region10a, in the configuration ofFIG. 5. Then, each test transistor17is greater in size (channel width) than each test transistor18as illustrated inFIG. 7. It is therefore preferred to place the test transistors17, which are arranged along the shorter side, closer to the outside than the test transistors18, which are arranged along the longer side, are to the outside. It is also preferred in the configuration ofFIG. 5to place the second test control signal supply wiring19bcloser to the outside than the first test control signal supply wiring19ais to the outside.

FIG. 8is a plan view for illustrating another configuration of the display panel10. In the configuration ofFIG. 8, the display region10ahas a vertically elongated shape, and the test transistors17are arranged along a longer side of the display region10awhile the test transistors18are arranged along a shorter side of the display region10a. The data lines11, which are connected to the test transistors18arranged along the shorter side, are accordingly longer than the gate lines12, which are connected to the test transistors17arranged along the longer side. The size (channel width) of each test transistor18in this case is greater than the size (channel width) of each test transistor17as illustrated inFIG. 9. It is therefore preferred to place the test transistors18, which are arranged along the shorter side of the display region10a, closer to the outside than the test transistors17, which are arranged along the longer side of the display region10a, are to the outside. It is also preferred in the configuration ofFIG. 8to place the first test control signal supply wiring19acloser to the outside than the second test control signal supply wiring19bis to the outside.

In the configuration ofFIG. 9, one group of test transistors17(eight test transistors17constitute one group inFIG. 9) is arranged in a region between two data lines11connected to two test transistors18that are adjacent to each other in the row direction. A plurality of data lines11(data lines11ato11fofFIG. 9) associated with two groups of test transistors18that are adjacent to each other in the row direction are arranged in a region between two groups of test transistors17that are adjacent to each other in the row direction.

FIG. 10is an equivalent circuit diagram in which a corner portion of the display region10athat has a vertically elongated shape is enlarged. As illustrated inFIG. 10, the plurality of test transistors17are grouped into a group of six, and the six test transistors17in each group are aligned in a single file in the column direction. A plurality of groups of test transistors17are arranged in an oblique direction in a region next to the arc-shaped corner portion of the display region10a. The plurality of test transistors18are grouped into a group of four, and the four test transistors18in each group are aligned in a single file in the row direction. A plurality of groups of test transistors18are arranged in an oblique direction in the region next to the arc-shaped corner portion of the display region10a. Four data lines11that are associated with one group of test transistors18are arranged so as to pass through a region between two groups of test transistors17that are adjacent to each other in the row direction. One group of test transistors17is arranged in a region between two groups of test transistors18that are adjacent to each other in the row direction. Groups of test transistors17are alternated with groups of test transistors18in the row direction. The number of test transistors that are included in a group is not limited.

With the display panel10according to this embodiment, where the test transistors17and18and various test wiring lines are arranged in a pattern that fits the shape of the display region, and the test control signal supply wiring19is branched, the area of the frame region can be minimized. In addition, the efficient arrangement of the test transistors17and18and various test wiring lines can prevent a contact between wiring lines, thereby executing a test of the display panel without fail.

To conduct a test of the display panel10, test equipment is connected to the test signal input pad25in, for example, a test step that is included in a manufacturing process of the display panel10, and test signals are supplied to the respective test signal supply wiring lines via the test signal input pad25. Specifically, the test equipment supplies test control signals for controlling the turning on/off of the test transistors17and18to the test control signal supply wiring19, supplies the test gate signals Ge to the test gate signal supply wiring21, supplies the test gate signals Go to the test gate signal supply wiring22, supplies the test data signal DE to the plurality of test data signal supply wiring lines23, and supplies the test data signal DO to the plurality of test data signal supply wiring lines24.

After the test step is finished, the test equipment is disconnected from the test signal input pad25. Disconnecting the test equipment from the display panel10puts the test transistors17and18in an electrically floating state. The test transistors17and18may therefore be turned on accidentally while the display device is in normal use (during display operation) due to, for example, the display operation, and a resultant change in pixel potential can cause display troubles. In order to avoid such display troubles, the test transistors17and18in a floating state need to be fixed to the off state without fail during display operation. The liquid crystal display device100in this embodiment clears this requirement by having a configuration that fixes the test transistors17and18to the off state without fail while the display device is in normal use.

Specifically, the display panel10includes gate off-voltage transmission wiring20(off-voltage transmission wiring) through which a control signal for turning the test transistors17and18off (a gate off-voltage) is supplied. The gate off-voltage transmission wiring20has one end electrically connected to the terminal VOFF, which is provided in the peripheral portion of the display panel10(inFIG. 5, the left-hand side of the lower side), and has the other end electrically connected to the test control signal supply wiring19(for example, the first test control signal supply wiring19a). The gate off-voltage transmission wiring20is laid along the outermost edge of the display panel10as illustrated inFIG. 5. A connection point T1, where the gate off-voltage transmission wiring20is connected to the first test control signal supply wiring19a, and the branching point S1are positioned so as to be symmetrical (left to right) with respect to the row direction in the display region10a. While the position of the connection point T1is not limited thereto, it is preferred for the connection point T1to be located above the first gate line GL1.

A gate off-voltage is applied to the terminal VOFF constantly during display operation. The display panel10is thus supplied with a gate off-voltage all the time, and the test transistors17and18can therefore be fixed to the off state during display operation. The display troubles resulting from the accidental turning on of the test transistors17and18during display operation can be prevented in this manner.

An example of a testing method in the liquid crystal display device100is briefly described next. Test equipment is connected to the test signal input pad25of the display panel10first. Next, a test control signal (a gate on-voltage) is input from the test equipment to the test control signal supply wiring19via the control signal input pad TR. This turns the test transistors17and18on. The test gate signal Go that has a gate on-voltage is next input from the test equipment to the conducting electrodes of the test transistors17that are in odd-numbered columns. The gate lines12that are in odd-numbered columns are selected as a result. Next, the test data signal DO is supplied from the test equipment via the thin film transistors13that are connected to the gate lines12in odd-numbered columns to the corresponding pixel electrodes15. The common voltage Vcom is supplied to the common electrode16. The display state of the corresponding pixels14, here, the pixels14that are in odd-numbered columns and odd-numbered rows, is thus checked, to thereby detect a wiring defect in gate lines, data lines, or other wiring lines that are associated with the checked pixels14.

The test equipment subsequently inputs the test gate signal Go that has a gate off-voltage to the conducting electrodes of the test transistors17that are in odd-numbered columns, and inputs the test gate signal Ge that has a gate on-voltage to the conducting electrodes of the test transistors17that are in even-numbered columns. As a result, the gate lines12that are in odd-numbered columns are no longer selected and the gate lines12that are in even-numbered columns are selected. The test equipment next supplies the test data signal DE via the thin film transistors13that are connected to the gate lines12in even-numbered columns to the corresponding pixel electrodes15. The common voltage Vcom is supplied to the common electrode16. The display state of the corresponding pixels14, here, the pixels14that are in even-numbered rows and even-numbered columns, is thus checked, to thereby detect a wiring defect in gate lines, data lines, or other wiring lines that are associated with the checked pixels14. After the test step is finished, the test equipment is disconnected from the test signal input pad25of the display panel10.

The display panel10is tested in the test step in this manner. The method of testing the display panel10is not limited to the one described above, and known methods can be employed.

The shape of the display region10aand the arrangement of the test transistors17and18and various wiring lines are not limited to those in the configurations described above.FIG. 11is a plan view for illustrating a configuration of the display panel10in which the entire upper side of the display region10ahas an arc shape (a semicircular shape). In the configuration ofFIG. 11, the branching point S1of the test control signal supply wiring19and the connection point T1where the gate off-voltage transmission wiring20is connected to the test control signal supply wiring19occupy the same position, here, a point along a center line in the row direction (left-to-right direction) of the display region10a.

FIG. 12is a plan view for illustrating a configuration of the display panel10in which the display region10ais formed to have a circular shape. In the configuration ofFIG. 12, similarly to the configuration ofFIG. 11, the branching point S1of the test control signal supply wiring19and the connection point T1where the gate off-voltage transmission wiring20is connected to the test control signal supply wiring19occupy the same position.

FIG. 13is a modification example of the display panel10that is illustrated inFIG. 5. In the configuration ofFIG. 13, the branching point S1of the test control signal supply wiring19is located below a shorter side (left side) of the display region10a. Specifically, the second test control signal supply wiring19bextends from the branching point S1of the first test control signal supply wiring19aalong the left side and upper left arc-shaped corner portion of the display region10a, and is connected to control electrodes of the plurality of test transistors17connected to the plurality of gate lines12.

The configurations described above with respect to the arrangement of the test transistors17and18and various wiring lines are applicable also to the display panel10that has an anomaly shape such as the one illustrated inFIG. 3.

According to the display panel10of this embodiment, in a display panel that includes a display region having an anomaly shape and test transistors and test wiring lines arranged in a frame region, it is possible to reduce the area of the frame region and also execute a test of the display panel without fail.