INTEGRATED CIRCUIT PACKAGES AND METHODS

An integrated circuit package including integrated circuit dies and a method of forming are provided. The integrated circuit package may include a first integrated circuit die and a second integrated circuit die bonded to the first integrated circuit die. The first integrated circuit die may include a first substrate, a first interconnect structure, and a first bonding layer. The first interconnect structure may be between the first bonding layer and the first substrate. The second integrated circuit die may include a second substrate, a second interconnect structure, and a second bonding layer. The second interconnect structure may be between the second bonding layer and the second substrate. A first surface of the first bonding layer may be in direct contact with a first surface of the second bonding layer. A sidewall the first bonding layer and the first surface of the second bonding layer may form a first acute angle.

BACKGROUND

The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged.

DETAILED DESCRIPTION

An integrated circuit package including integrated circuit dies singulated using laser ablation and plasma etching techniques, and the method of forming the same are provided. In accordance with some embodiments, an integrated circuit package comprises integrated circuit dies, which may be singulated from a wafer by a singulation method including a laser ablation process followed by a plasma etching process. The plasma etching process may be an anisotropic plasma etching or an isotropic plasma etching. Such a singulation method may lead to a more effective bonding between the singulated integrated circuit dies and another integrated circuit die. As a result, defects at the bonding interface are reduced or prevented, thereby leading to an improved reliability of the integrated circuit package.

FIGS.1through6are views of intermediate stages in the manufacturing of top integrated circuit dies50, in accordance with some embodiments. Referring first toFIG.1, a cross-sectional view of a wafer10is illustrated. The wafer10is supported by a tape51. The wafer10comprises top integrated circuit dies50, and the wafer10may be subsequently singulated as described below to form discrete top integrated circuit dies50. Each of the top integrated circuit dies50may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof. The top integrated circuit dies50may be the same or different.

The wafer10includes a semiconductor substrate52, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate52may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate52may have an active surface (e.g., the surface facing upwards inFIG.1), sometimes called a front side, and an inactive surface (e.g., the surface facing downwards inFIG.1), sometimes called a back side.

Devices (not separately illustrated) may be disposed at the active surface of the semiconductor substrate52. The devices may be active devices (e.g., transistors, diodes, etc.) or passive devices (e.g., capacitors, resistors, etc.). An interconnect structure54is disposed over the active surface of the semiconductor substrate52. The interconnect structure54may interconnect the devices to form an integrated circuit. The interconnect structure54may be formed of, for example, metallization patterns (not separately shown) in dielectric layers (not separately shown). The dielectric layers may be, e.g., low-k dielectric layers. The metallization patterns may include metal lines and vias, which may be formed in the dielectric layers by a damascene process, such as a single damascene process, a dual damascene process, or the like. The metallization patterns may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, a combination thereof, or the like. The metallization patterns may be electrically coupled to the devices.

A bonding layer56is over the interconnect structure54, at the front side of the top integrated circuit dies50. The bonding layer56may be formed of an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a tetraethyl orthosilicate (TEOS) based oxide, or the like; a nitride such as silicon nitride or the like; a combination thereof; or the like. The bonding layer56may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, lamination, or the like. One or more passivation layer(s) (not separately illustrated) may be disposed between the bonding layer56and the interconnect structure54.

Die connectors58extend through the bonding layer56. The die connectors58may include conductive pillars, pads, or the like, to which external connections may be made. In some embodiments, the die connectors58include bond pads (not separately illustrated) at the front side of the top integrated circuit die50, and bond pad vias (not separately illustrated) that connect the bond pads to the upper metallization pattern of the interconnect structure54. In such embodiments, the die connectors58, including the bond pads and the bond pad vias, may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. The die connectors58may be formed of a conductive material, such as a metal, such as copper, aluminum, or the like, by a technique, such as plating or the like. In some embodiments, a planarization process such as a CMP, a grinding process, an etch-back process, combinations thereof, or the like, is performed on the bonding layer56and the die connectors58. After the planarization process, surfaces of the bonding layer56and the die connectors58may be substantially coplanar (within process variations).

InFIG.2, a first protective layer60is formed on the wafer10, such as on the bonding layer56and the die connectors58, and a second protective layer62is formed on the first protective layer60. The first protective layer60and the second protective layer62may protect the underlying top integrated circuit dies50during the subsequent singulation processes. In some embodiments, the first protective layer60is formed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or the like by a technique, such as CVD, ALD, or the like. In some embodiments, the first protective layer60is formed of a non-water-soluble polymer, by a technique, such as spin coating, or the like. The first protective layer60may have a thickness in a range from about 0.02 μm to about 2 μm, such as about 0.05 μm. The second protective layer62may be formed of a water-soluble polymer, such as polyvinylpyrrolidone (PVP), polyvinyl alcohol (PVA), or the like, by a technique, such as spin coating, or the like. The second protective layer62may have a thickness in a range from about 0.5 μm to about 10 μm, such as about 5 μm.

FIG.3through6are views of intermediate stages in a singulation process which singulates the wafer10into discrete top integrated circuit dies50. The singulation method utilized during the singulation process may include a laser ablation process followed by a plasma etching process. Such a singulation method may lead to a more effective subsequent bonding process where top integrated circuit dies50are bonded to another integrated circuit die. As a result, defects at the bonding interface are reduced or prevented, thereby leading to an improved reliability of the integrated circuit package.

Referring toFIG.3, a first dicing process where a laser ablation process is applied to the wafer10in scribe line regions63. The laser ablation process may form grooves64that extend through the second protective layer62, the first protective layer60, the bonding layer56, the interconnect structure54, and into the semiconductor substrates52. The grooves64may not extend fully through the semiconductor substrates52, and may expose a surface of the semiconductor substrates52. Recast regions66may be formed on sidewalls of the grooves64, such as sidewalls of the second protective layer62, the first protective layer60, the bonding layer56, the interconnect structure54, and the semiconductor substrate52during the laser ablation process. The recast regions66may be formed as a result of re-deposition of materials of the second protective layer62, the first protective layer60, the bonding layer56, the interconnect structure54, and the semiconductor substrate52removed by laser beams during the laser ablation process. As a result, the recast regions66may comprise chemical elements (e.g., silicon) of the second protective layer62, the first protective layer60, the bonding layer56, the interconnect structure54, and the semiconductor substrate52. The recast regions66may be on opposing sidewalls of the groove64may extend above a top surface of the bonding layer56and protrude from a top surface of the second protective layer62. In some embodiments, the laser ablation process removes portions of the second protective layer62and the first protective layer60along the grooves64and exposes portions of the top surface of the bonding layer56along the grooves64.

The laser ablation process may include applying one or more laser beams to the second protective layer62, the first protective layer60, the bonding layer56, the interconnect structure54, and into the semiconductor substrates52. A position, power, number of, and/or type of each laser beam are controlled in order to achieve a desired profile of the resulting groove64. The power of the laser beams may be in a range between 1 W and 10 W, such as about 5 W.

In the embodiment illustrated inFIG.3, a horizontal distance D1between the highest points (e.g., furthest from the top surface of the second protective layer62) of the recast regions66may be in a range between about 50 μm and about 200 μm, such as about 150 μm. A vertical distance D2between the highest point of each recast region66and the top surface of the second protective layer62may be in a range between 0 μm and about 20 μm, such as about 15 μm. The recast regions66are illustrated as being symmetrical (e.g., having a same shape on opposing sidewalls of the groove64) as an example. The recast regions66may have different profiles on each sidewall of each groove64. The shape and location of the recast regions66illustrated inFIG.3is an example, other shapes and locations of the recast regions66are contemplated.

InFIG.4, a removal process is applied to the wafer10to remove at least portions of the recast regions66in order to provide a flatter surface with fewer protrusions such that a subsequent bonding process can be performed more effectively with little or no hindrance from the recast regions66. In the embodiment illustrated inFIG.4, the removal process includes an anisotropic plasma etching to partially remove the recast regions66and to recess upper surfaces of the recast regions66to below the top surface of the bonding layer56, thereby allowing a subsequent bonding process where the top surface of the bonding layer56is bonded another surface to be performed more effectively with little or no hindrance from the recast regions66. The remaining portions of the recast regions66may be on sidewalls of the bonding layer56, the interconnect structure54, and the semiconductor substrate52.

In some embodiments, upper corners or edges of the bonding layer56are removed, thereby forming chamfered or rounded corners57. The first dicing process, such as the laser ablation process discussed above, may expose portions of the top surface of the bonding layer56along the grooves64. Additionally, as the anisotropic plasma etching removes the recast regions66, the anisotropic plasma etching may also may remove portions of the bonding layer56along the grooves64. The removal of the bonding layer56may be at a slower rate than the removal of the recast regions66, which may lead to chamfered or rounded corners57on the bonding layer56along the grooves64.

The plasma used for the anisotropic plasma etching process may be a fluorine-based plasma, a chlorine-based plasma, or the like, which may be generated by a gas source including an etchant and a carrier gas. Acceptable fluorine-based etchants may include carbon tetrafluoride (CF), octafluorocyclobutane (CF), sulfur hexafluoride (SF6), or the like. Acceptable chlorine-based etchants may include chlorine (Cl2), carbon tetrachloride (CCl4), or the like. The carrier gas may be an inert gas such as Ar, He, Xe, Ne, Kr, Rn, the like, or combinations thereof. In some embodiments, the plasma is generated by a radio frequency (RF) plasma generator, or the like, with a generation power in a range from about 0.3 kW to about 1 kW, such as about 0.5 kW. In some embodiments, the plasma may be generated by a microwave plasma generator, or the like, with a generation power in a range from about 0.5 kW to about 1.5 kW, such as about 1 kW.

FIG.4further illustrates the removal of the second protective layer62and the first protective layer60, and the formation of openings68through the semiconductor substrate52by a second dicing process. In embodiments in which the second protective layer62is water soluble, the second protective layer62may be removed by water. The second dicing process is applied to form openings68through the semiconductor substrate52and to singulate the wafer10into discrete structures. In some embodiments, the openings68are formed by blade dicing or the like, which utilizes an abrasive disc or blade rotating at a high speed. In some embodiments, the openings68are formed by stealth dicing, which utilizes a laser beam, such as an infrared laser beam. The width of the openings68formed by blade dicing may be larger than the width of the openings68formed by stealth dicing. In some embodiments, the first protective layer60are removed by a suitable process, such as wet etching, dry etching, or ashing. In some embodiments, the first protective layer60is removed after the second dicing process to provide a protection to the bonding layer56during the second dicing process.

InFIG.5, the top integrated circuit dies50are removed from the tape51, whereinFIG.6shows an enlarged view of a region69of the top integrated circuit die50shown inFIG.5in accordance with some embodiments. As discussed above, the bonding layer56may have chamfered or rounded corners57along the grooves64. Sidewalls of the bonding layer56may have upper sidewalls56A and lower sidewalls56B, wherein the upper sidewalls56A may be exposed and the lower sidewalls56B may be at least partially covered by the recast regions66. The upper sidewalls56A may be slanted and the lower sidewalls56B may be substantially vertical. The recast regions66may completely cover sidewalls of the interconnect structures54. Upper portions of the semiconductor substrates52(e.g., portions of semiconductor substrates52near the interconnect structures54) may have upper sidewalls52A, which may be curved as a result of first dicing process and/or the plasma etching process. Lower portions of the semiconductor substrates52(e.g., distal portions of semiconductor substrates52from the interconnect structures54) may have lower sidewalls52B, which may be substantially straight as a result of the second dicing process. The recast regions66may partially cover the upper sidewalls52A and the lower portions of the semiconductor substrates52may laterally extend beyond the recast regions66.

Referring toFIG.6, a horizontal distance D3between the lower sidewall56B of the bonding layer56and the lower sidewall52B of the semiconductor substrate52may be in a range between about 2 μm to about 80 μm, such as about 40 μm. A vertical distance D4between a top point and a bottom point of the upper sidewall52A of the semiconductor substrate52(e.g., a thickness of the upper portion of the semiconductor substrate52) may be in a range between about 1 μm to about 20 μm, such as about 10 μm. The recast region66may have a height D5in the vertical direction in a range between about 10 μm to about 50 μm, such as about 30 μm, and a width in the horizontal direction in a range between about 1 μm to about 10 μm, such as about 5 μm.

FIGS.7through12are views of intermediate stages in the manufacturing of an integrated circuit package200(seeFIG.12), in accordance with some embodiments. Referring toFIG.7, top integrated circuit dies50(shown in e.g.,FIG.5) are bonded to a bottom integrated circuit die100. In the embodiment illustrated inFIG.7, two top integrated circuit dies50are bonded to the bottom integrated circuit die100is shown as an example, other layouts are contemplated.

The bottom integrated circuit die100may be a logic die (e.g., CPU, GPU, SoC, AP, microcontroller, etc.), a memory die (e.g., DRAM die, SRAM die, etc.), a power management die (e.g., PMIC die), a RF die, a sensor die, a MEMS die, a signal processing die (e.g., DSP die), a front-end die (e.g., AFE die), the like, or combinations thereof. The materials and manufacturing processes of the features in bottom integrated circuit die100may be the same or similar to the like features in the top integrated circuit dies50.

The bottom integrated circuit die100may include a semiconductor substrate102, which may have an active surface (e.g., the surface facing upwards inFIG.7), which may be called a front side, and an inactive surface (e.g., the surface facing downwards inFIG.7), which may be called a back side. Devices (not separately illustrated) may be disposed at the active surface of the semiconductor substrate102. The devices may be active devices (e.g., transistors, diodes, etc.) capacitors, resistors, or the like. An interconnect structure104may be disposed on the active surface of the semiconductor substrate102.

Conductive vias105may be disposed in the semiconductor substrate102. The conductive vias105may be electrically coupled to the metallization patterns of the interconnect structure104. The conductive vias105may be through-substrate vias (TSV), such as through-silicon vias. In some embodiments, the conductive vias105may be formed by a via-first process, such that the conductive vias105may extend into the semiconductor substrate102but not the interconnect structure104. The conductive vias105formed by a via-first process may be connected to a lower metallization pattern (e.g., closer to the semiconductor substrate102) of the interconnect structure104. In some embodiments, the conductive vias105may be formed by a via-middle process, such that the conductive vias105may extend through a portion of the interconnect structure104and into the semiconductor substrate102. The conductive vias105formed by a via-middle process may be connected to a middle metallization pattern of the interconnect structure104. In some embodiments, the conductive vias105may be formed by a via-last process, such that the conductive vias105may extend through an entirety of the interconnect structure104and into the semiconductor substrate102. The conductive vias105formed by a via-last process may be connected to an upper metallization pattern (e.g., further from the semiconductor substrate102) of the interconnect structure104.

A bonding layer106may be disposed on the interconnect structure104, at the front side of the bottom integrated circuit die100. One or more passivation layer(s) (not separately illustrated) may be disposed between the bonding layer106and the interconnect structure104. Die connectors108may extend through the bonding layer106may be electrically coupled to the metallization patterns of the interconnect structure104and/or the conductive vias105.

The bottom integrated circuit die100may be attached to a carrier110by an adhesive112on the inactive surface of the semiconductor substrate102. The carrier110may be a semiconductor carrier, a glass carrier, a ceramic carrier, or the like. The carrier110may be a wafer. In some embodiments, the adhesive112is a thermal-release layer, such as an epoxy-based light-to-heat-conversion (LTHC) release material, which loses its adhesive property when heated. In some embodiments, the adhesive112is a UV glue, which loses its adhesive property when exposed to UV light.

Still referring toFIG.7, the top integrated circuit dies50may be bonded to the bottom integrated circuit die100by placing the top integrated circuit dies50using a pick-and-place process or the like, then bonding the bonding layers56and the die connectors58of the top integrated circuit dies50to the bonding layer106and the die connectors108of the bottom integrated circuit die100, respectively. The bonding layers56may be directly bonded to the bonding layer106through dielectric-to-dielectric bonding, and the die connectors58may be directly bonded to respective die connectors108through metal-to-metal bonding. The bonding may include a pre-bonding and an annealing. During the pre-bonding, a small pressing force may be applied to press the top integrated circuit dies50against the bottom integrated circuit die100. The pre-bonding may be performed at a low temperature, such as room temperature. After the pre-bonding, the bonding layers56of the top integrated circuit dies50may be bonded to the bonding layer106of the bottom integrated circuit die100. The bonding strength may be then improved in a subsequent annealing step at a higher temperature. After the annealing, direct bonds such as dielectric-to-dielectric bonds may be formed, bonding the bonding layers56to the bonding layer106. The die connectors58may be bonded to the die connectors108with a one-to-one correspondence. The die connectors58may be in physical contact with the die connectors108after the pre-bonding, or may expand to be brought into physical contact with the die connectors108during the annealing. Further, during the annealing, the material of the die connectors58may intermingle or bond with the material of the die connectors108, so that metal-to-metal bonds may be formed.

FIG.7illustrates a front-to-front bonding configuration as an example, wherein the front sides of the top integrated circuit dies50face the front sides of the bottom integrated circuit die100after bonding. Other bonding configurations may be used, such as a front-to-back bonding configuration. In the front-to-back bonding configuration the front sides of the top integrated circuit dies50may face the front sides of the bottom integrated circuit die100.

InFIG.8A, a gap-fill layer114is formed over the bottom integrated circuit die100and around the top integrated circuit dies50. The gap-fill layer114may be an insulating layer, whereinFIG.8Bshows an enlarged view of a region115of the structure shown inFIG.8Atop integrated circuit die50in accordance with some embodiments. In some embodiments, the gap-fill layer114comprises a molding compound, such as an epoxy, a resin, or the like, and is formed by compression molding, transfer molding, or the like. In some embodiments, the gap-fill layer114comprises a dielectric material, such as silicon oxide, PSG, BSG, BPSG, a TEOS based oxide, or the like, and is formed by a suitable deposition process such as CVD, ALD, or the like. Initially, the gap-fill layer114may cover the back sides of the top integrated circuit dies50. A thinning process may be performed to remove portions of the gap-fill layer114to expose the semiconductor substrates52. Portions of the semiconductor substrates52may be removed during the thinning process. The thinning process may be, a chemical-mechanical polishing (CMP) process, a grinding process, an etch-back process, combinations thereof, or the like. After the thinning process, surfaces of the gap-fill layer114and the top integrated circuit dies50(including the semiconductor substrates52) are substantially coplanar (within process variations).

Referring toFIG.8B, the lower portions of the semiconductor substrates52(e.g., distal portions of semiconductor substrates52from the interconnect structures54) may overhang the interconnect structures54and the bonding layers56. A vertical distance D6between the bottom point of the upper sidewall52A of the semiconductor substrate52and a top surface of the bonding layer106of the bottom integrated circuit die100may be in a range between about 5 μm to about 40 μm, such as 20 μm. The recast region66may be spaced apart from the top surface of the bonding layer106of the bottom integrated circuit die100by a distance D7in a range between about 1 μm to about 20 μm, such as 10 μm. An intersection of the upper sidewall56A of the bonding layer56and the top surface of the bonding layer106of the bottom integrated circuit die100may form an acute angle θ2in a range between 0° to about 30°, such as about 15°. The space (e.g., recess) between the upper sidewall56A and the top surface of the bonding layer106of the bottom integrated circuit die100may be filled with the gap-fill layer114. The portion of the gap-fill layer114that extends between the upper sidewall56A and the top surface of the bonding layer106may have a width D8in the horizontal direction in a range between about 1 μm to about 15 μm, such as about 8 μm.

InFIG.9, a carrier120is bonded to the upper surfaces of the semiconductor substrates52and the gap-fill layer114, and the carrier110and the adhesive112are removed. The carrier120may be a semiconductor carrier, a glass carrier, a ceramic carrier, or the like. The carrier120may be a wafer having a same or similar size as the carrier110(shown inFIG.8). In some embodiments, the carrier120is bonded to the semiconductor substrates52and the gap-fill layer114using bonding layers116and118. The bonding layer116is formed on the semiconductor substrates52and the gap-fill layer114, and the bonding layer118is formed on the carrier120. The bonding layer116and the bonding layer118may each comprise a dielectric material, such as silicon dioxide or the like, and may be formed by a suitable deposition process such as CVD, ALD, or the like. The structure over the carrier110may be bonded to the carrier120by bonding the bonding layer116on the semiconductor substrates52and the bonding layer118on the carrier120by a same or similar process used for bonding the bonding layers56of the top integrated circuit dies50and the bonding layer106of the bottom integrated circuit die100described with respect toFIG.7. The removal of the carrier110and the adhesive112may include projecting a light beam such as a laser beam or a UV light beam on the adhesive112(shown inFIG.8) so that the adhesive112decomposes upon exposure to the light beam and the carrier110may be removed.

InFIG.10, a dielectric layer122is formed on the back sides of the bottom integrated circuit die100, under-bump metallizations (UBMs)124are formed through the dielectric layer122, and electrical connectors126are formed on the UBMs124. In some embodiments, the dielectric layer122comprises PBO, polyimide, a BCB-based polymer, or the like, and is formed by a suitable coating process such as spin coating, lamination, or the like. In some embodiments, the dielectric layer122comprises silicon dioxide, silicon nitride, or the like, and is formed by a suitable deposition process such as CVD, ALD, or the like. A redistribution structure (not separately illustrated) may be formed prior to forming the dielectric layer122to provide additional routing. The UBMs124may have portions extending along a surface of the dielectric layer122and portions extending through the dielectric layer122to physically and electrically couple to the conductive vias105. As a result, the UBMs124are electrically coupled to the bottom integrated circuit die100and/or the top integrated circuit dies50.

As an example to form the UBMs124, the dielectric layer122may be patterned to form openings exposing the underlying the conductive vias105. The patterning may be done by an acceptable photolithography and etching processes, such as forming a mask then performing an anisotropic etching. The mask may be removed after the patterning. A seed layer (not separately illustrated) may be formed on the dielectric layer122, in the openings through the dielectric layer122, and on the exposed portions of the conductive vias105. The seed layer may be a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using a suitable deposition process, such as physical vapor deposition (PVD) or the like. A photoresist may then be formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist may correspond to the UBMs124. The patterning may form openings through the photoresist to expose the seed layer. A conductive material may be formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroless plating, electroplating, or the like. The conductive material may comprise a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, the like, or combinations thereof. Then the photoresist and portions of the seed layer on which the conductive material is not formed may be removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, portions of the seed layer on which the conductive material is not formed may be removed by an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material may form the UBMs124.

Electrical connectors126may be formed on the UBMs124. The electrical connectors126may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. In some embodiments, the electrical connectors126comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. The electrical connectors126may be formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the layer of solder has been formed on the structure, a reflow may be performed to shape the solder into the desired bump shapes. In some embodiments, the electrical connectors126comprise metal pillars, such as a copper pillar, formed by a sputtering, printing, electroplating, electroless plating, CVD, or the like, which are solder free and have substantially vertical sidewalls. A metal cap layer may be formed on top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.

The processes discussed above may be performed using wafer-level processing. The carrier120may be a wafer and may include many structures (not separately illustrated) similar to the one illustrated inFIG.10. As such, the structure shown inFIG.10may be referred to as a wafer structure150and may be singulated in a subsequent process. For example, inFIG.11, the wafer structure150is singulated to form individual integrated circuit package component150′. The wafer structure150may be placed on a tape152supported by a frame154. The wafer structure150may then be singulated along scribe lines156, so that the wafer structure150may be separated into discrete integrated circuit package components150′. The singulation process may include a sawing process, a laser cutting process, or the like. A cleaning process or rinsing process may be performed after the singulation process.

InFIG.12, the integrated circuit package component150′ is bonded to a package substrate158and an underfill162is formed between the integrated circuit package component150′ and the package substrate158. The package substrate158may include comprise bond pads160. In some embodiments, the package substrate158comprise materials such as fiberglass reinforced resin, BT resin, other PCB materials, or the like. In some embodiments, the package substrate158comprise materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, or the like.

The package substrate158may include active and/or passive devices (not separately illustrated), such as transistors, capacitors, resistors, combinations thereof, or the like. The devices may be formed using any suitable methods. The package substrate158may comprise metallization layers and vias (not separately illustrated) physically and electrically coupled to the bond pads160. The metallization layers may be formed over the active and/or passive devices and may connect the various devices to form functional circuitry. The metallization layers may be formed in layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material. In some embodiments, the package substrate158is free of active and passive devices.

During the bonding process the electrical connectors126may be reflowed to bond the integrated circuit package component150′ to the bond pads160. The electrical connectors126may electrically and physically couple the package substrate158to the integrated circuit package component150′. In some embodiments, a solder resist (not separately illustrated) is formed on the package substrate158. The electrical connectors126may be disposed in openings in the solder resist to electrically and physically couple to the bond pads160. The solder resist may be used to protect areas of the package substrate158from external damage.

The underfill162may surround the electrical connectors126and protect the joints resulting from the reflowing of the electrical connectors126. The underfill162may encircle the integrated circuit package component150′ in a top-down view. The underfill162may be formed by a capillary flow process after the integrated circuit package component150′ is attached or by a suitable deposition method before the integrated circuit package component150′ is attached. The underfill162may be subsequently cured. The structure shown inFIG.12may be referred to as the integrated circuit package200.

FIGS.13through16are views of intermediate stages in the manufacturing of an integrated circuit package202(seeFIG.16), in accordance with some embodiments. The integrated circuit package202is similar to the integrated circuit package200, wherein like numerals refer to like features. As will be discussed in greater detail below, the integrated circuit package202include top integrated circuit dies50that are singulated by a singulation process including an isotropic plasma etching. The structure illustrated inFIG.13assume processes similar to those discussed above with respect toFIGS.1-3were previously performed. Accordingly, after the grooves64and the recast regions66are formed by the laser ablation process as discussed above with respect toFIGS.1-3, the manufacturing may proceed toFIG.13, where the plasma etching process is applied to the wafer10to remove or reduce the recast regions66from the bonding surface, thereby allowing a subsequent bonding process with little or no hindrance from the recast regions66. Furthermore, the second protective layer62and the first protective layer60are removed, and openings68are formed through the semiconductor substrate52by a dicing process.

In the embodiment illustrated inFIG.13, an isotropic plasma etching is applied and the recast regions66are removed. As a result, the sidewalls of the second protective layer62, the first protective layer60, the bonding layer56, the interconnect structure54, and the semiconductor substrate52are exposed. Additionally, the second protective layer62, the first protective layer60, the bonding layer56, the interconnect structure54, and the semiconductor substrate52may be further etched in the lateral directions. In some embodiments, the laser ablation process removes portions of the second protective layer62and the first protective layer60along the grooves64, and the exposes portions of the top surface of the bonding layer56along the grooves64. The isotropic plasma etching may remove the bonding layer56at a slower rate than the recast regions66, which may lead to chamfered or rounded corners57on the bonding layer56along the grooves64as will be discussed in greater detail below. In some embodiments, the isotropic plasma etching removes the semiconductor substrate52at a faster rate than the interconnect structure54to recess a portion of the semiconductor substrate52from a sidewall of the interconnect structure54and a sidewall of the bonding layer56, thereby forming recesses67. As a result, the interconnect structure54and the bonding layer56may extend laterally beyond a sidewall of the semiconductor substrate52.

The plasma used for the isotropic plasma etching process may be generated by a similar gas source described with respect toFIG.4. In some embodiments, the plasma is generated by a radio frequency (RF) plasma generator, or the like, with a generation power in a range from about 0.1 kW to about 0.3 kW, such as about 0.2 kW. In some embodiments, the plasma may be generated by a microwave plasma generator, or the like, with a generation power in a range from about 1.5 kW to about 3 kW, such as about 2 kW.

InFIG.14A, the singulated top integrated circuit dies50are removed from the tape51, whereinFIG.14Bshows an enlarged view of a region71of the top integrated circuit die50shown inFIG.14Ain accordance with some embodiments. As shown inFIGS.14A and14B, the bonding layer56along the grooves64may have chamfered or rounded corners57and may comprise upper sidewalls56A and lower sidewalls56B. The upper sidewalls56A may be slanted towards the die connectors58and the lower sidewalls56B may be slanted away from the die connectors58. The upper portions of the semiconductor substrates52(e.g., portions of semiconductor substrates52near the interconnect structures54) may have upper sidewalls52A, which may be curved from as a result of the laser ablation process and/or the plasma etching process. Upper sidewalls52A may be slanted towards the die connectors58. The lower portions of the semiconductor substrates52(e.g., distal portions of semiconductor substrates52from the interconnect structures54) may have lower sidewalls52B, which may be substantially straight from the singulation process. The recesses67may be disposed between upper sidewalls52A and a bottom surface of the interconnect structures54, and lower portions of the semiconductor substrates52may laterally extend beyond the sidewalls of the interconnect structures54.

Referring toFIG.14B, a horizontal distance D9between the lower sidewall52B of the semiconductor substrate52and a junction of the upper sidewall52A and the lower sidewall56B of the bonding layer56may be in a range between about 2 μm to about 90 μm, such as about 45 μm. A vertical distance D10between a top point and a bottom point of the upper sidewall52A of the semiconductor substrate52(e.g., a thickness of the upper portion of the semiconductor substrate52) may be in a range between about 1 μm to about 40 μm, such as about 20 μm. The recess67may have a width D11in the horizontal direction, which may be in a range between about 1 μm to about 20 μm, such as about 10 μm.

FIG.15Aillustrates the structure ofFIG.14Aafter performing processes similar to those described above with respect toFIGS.7-8Ato bond the top integrated circuit dies50to the bottom integrated circuit die100, and form the gap-fill layer114around the top integrated circuit dies50.FIG.15Bshows an enlarged view of a region117of the structure shown inFIG.15Ain accordance with some embodiments. As shown in15A, the recesses67may be filled by the gap-fill layer114, and the lower portions of the semiconductor substrates52(e.g., distal portions of semiconductor substrates52from the interconnect structures54) may overhang the interconnect structures54and the bonding layers56.

Referring toFIG.15B, a vertical distance D12between the bottom point of the upper sidewall52A (seeFIG.14B) of the semiconductor substrate52and the top surface of the bonding layer106may be in a range between about 5 μm to about 60 μm, such as 30 μm. An intersection of the upper sidewall56A of the bonding layer56and the top surface of the bonding layer106may form an acute angle θ4in a range between 0° to about 30°, such as 15°. An intersection of the lower sidewall56B of the bonding layer56and a line perpendicular to the top surface of the bonding layer106may form an acute angle θ6a range between 0° to about 45°, such as about 20°. The space (e.g., recess) between the upper sidewall56A and the top surface of the bonding layer106may be filled with the gap-fill layer114. The portion of the gap-fill layer114that extend between the upper sidewall56A and the top surface of the bonding layer106may have a width D13in the horizontal direction in a range between about 1 μm to about 15 μm, such as about 8 μm.

FIG.16illustrates the structure ofFIG.15Aafter performing processes similar to those discussed above with respect toFIGS.9through12to form or attach the carrier120, the dielectric layer122, the UBMs124, and the electrical connectors126, singulate the wafer structure150into the integrated circuit package component150′, bond the integrated circuit package component150′ to the package substrate158, and form the underfill162. The structure shown inFIG.16may be referred to as the integrated circuit package202.

Various embodiments are described above in the context of a system on integrated chips (SoIC) package configuration. It should be understood that various embodiments may also be adapted to apply to other package configurations, such as integrated fan-out on substrate (InFO), chip on wafer on substrate (CoWoS) or the like.

The embodiments may have some advantageous features. By singulating the wafer10by a singulation method including a laser ablation process followed by a plasma etching process, a more effective bonding between the top integrated circuit dies50and the bottom integrated circuit die100may be achieved. As a result, defects at the bonding interface are reduced or prevented, thereby leading to an improved reliability of the integrated circuit packages200and202.

In an embodiment, an integrated circuit package includes a first integrated circuit die including a first substrate; a first interconnect structure on a front side of the first substrate; and a first bonding layer on the first interconnect structure, the first interconnect structure being between the first bonding layer and the first substrate; an insulating layer along sidewalls of the first integrated circuit die; and a second integrated circuit die bonded to the first integrated circuit die, the second integrated circuit die including a second substrate; a second interconnect structure on a front side of the second substrate; and a second bonding layer on the second interconnect structure, the second interconnect structure being between the second bonding layer and the second substrate, wherein a first surface of the first bonding layer is in direct contact with a first surface of the second bonding layer, wherein a sidewall the first bonding layer and the first surface of the second bonding layer form a first acute angle. In an embodiment, the first acute angle is smaller than 30°. In an embodiment, a recast material is on a sidewall of the first substrate, a sidewall of the first interconnect structure, and a sidewall of the first bonding layer. In an embodiment, the recast material is spaced apart from the first surface of the second bonding layer. In an embodiment, the recast material comprises chemical elements of the first substrate, the first interconnect structure, and the first bonding layer. In an embodiment, a portion of the first substrate adjacent the front side of the first substrate is recessed from a sidewall of the first interconnect structure.

In an embodiment, an integrated circuit package includes a first integrated circuit die including: a first bonding layer; a first substrate; and a first interconnect structure between the first bonding layer and the first substrate, wherein the first interconnect structure comprises a first surface facing the first substrate; and an encapsulant along sidewalls of the first integrated circuit die, wherein the encapsulant contacts the first surface of the interconnect structure. In an embodiment, the first bonding layer extends laterally beyond a sidewall of the first substrate and wherein a distal portion of the first substrate overhangs the first bonding layer. In an embodiment, the first bonding layer comprises a sidewall adjacent to the first interconnect structure, wherein the first bonding layer comprises a second surface facing the first substrate, and wherein the sidewall of the first bonding layer and a line perpendicular to the second surface of the first bonding layer form a first acute angle. In an embodiment, the first acute angle is smaller than 45°. In an embodiment, the integrated circuit package further includes a second integrated circuit die, the second integrated circuit die including a second bonding layer in contact with the first bonding layer of the first integrated circuit die, wherein a sidewall of the first bonding layer intersects a surface of the second bonding layer to form a first acute angle. In an embodiment, the first acute angle is smaller than 30°.

In an embodiment, a method of forming an integrated circuit package includes forming one or more protective layers on a wafer; exposing the wafer to a laser beam, wherein the laser beam forms grooves in the wafer, and wherein after exposing the wafer to the laser beam recast regions are on sidewalls of the grooves; performing a plasma etching process, wherein the plasma etching process removes at least a portion of the recast regions on the sidewalls of the grooves; and dicing the wafer along the grooves to form a first integrated circuit die, wherein the first integrated circuit die comprises a first substrate, a first interconnect structure on the first substrate, and a first bonding layer on the first interconnect structure. In an embodiment, the plasma etching process performs an anisotropic etching on the wafer. In an embodiment, after performing the anisotropic etching, the recast regions are recessed below a top surface of the first bonding layer. In an embodiment, the plasma etching process performs an isotropic etching on the wafer. In an embodiment, after performing the isotropic etching, the recast regions are completely removed. In an embodiment, the isotropic etching forms a sidewall on the first bonding layer slanted in a first horizontal direction and forms a sidewall on the first substrate slanted in a second horizontal direction, the first horizontal direction being opposite to the second horizontal direction. In an embodiment, the method further includes bonding the first bonding layer of the first integrated circuit die to a second bonding layer of a second integrated circuit die; and forming a first gap-fill layer on the second integrated circuit die and along sidewalls of the first integrated circuit die, wherein the first gap-fill layer extends between the first bonding layer and the second bonding layer. In an embodiment, the first gap-fill layer extends between the first interconnect structure and the first substrate.