Color television receiver AFPC circuit

A color television receiver includes an automatic phase control circuit (which will be hereinafter referred to simply as an APC circuit) with a voltage controlled oscillator for controlling the phase of a reference carrier supplied to a color demodulator so that the phase and frequency of the reference carrier are locked to those of a color burst signal. In addition to the APC circuit, an auxiliary frequency control loop drives the frequency of the voltage controlled oscillator until its frequency falls within the lock-in range of the APC loop. The auxiliary frequency control loop includes a counter circuit for counting cycles of the output signal of the voltage controlled oscillator during a reference time interval and a decoding circuit for decoding the output of the counter circuit to produce an auxiliary control signal for frequency control of the voltage controlled oscillator.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates generally to a color television receiver, and 
is directed more particularly to a color television receiver with an 
automatic phase control (APC) circuit. 
2. Description of the Prior Art 
In a prior art color demodulating circuit for use with a color television 
receiver, an APC circuit, employs a color burst signal derived from a 
color television signal to be demodulated as a reference for the APC 
circuit. The phase of the burst signal is compared with the phase of 
signal from a voltage controlled oscillator (which will be hereinafter 
referred simply to as a VCO). The phase of the signal from VCO is 
controlled by the compared error voltage. The VCO signal is frequency 
divided fed to a demodulator as a sub-carrier signal for demodulation. 
APC circuits have a limited frequency range over which they can acquire and 
lock in the VCO signal. If the deviation of the frequency of the VCO 
exceeds the lock-in range of the APC circuit, APC operation is not 
performed. In the prior art, the VCO must be very stable using, for 
example, an expensive quartz crystal oscillator. APC circuits having wide 
lock-in range may be used, but such APC circuits generally require 
response times which are too long to be practical. 
OBJECTS AND SUMMARY OF THE INVENTION 
Accordingly, it is an object of the present invention to provide a novel 
color television receiver free from the defects inherent in the prior art. 
It is another object of the invention to provide a color television 
receiver in which a simple coarse frequency control circuit is 
additionally used with a VCO, which may be relatively unstable in 
frequency. This permits the use of an inexpensive CR oscillator for 
example instead of the more expensive quartz crystal controlled 
oscillators. Hence the cost of a color television receiver can be made 
reduced. 
These objects are accomplished by providing a reference carrier generator 
for generating at least one reference signal having a frequency and phase 
controlled to the frequency and phase of a color burst component of a 
color television signal comprising: automatic phase control means having 
an output signal relatd to the at least one reference signal and means for 
controlling the phase of the output signal in relation to the phase 
difference between the output signal and the colorburst component; coarse 
frequency control means for producing a frequency control signal for 
application to the automatic phase control means which is variable in 
dependence upon a difference between the frequency of a second output of 
the automatic phase control means and a predetermined frequency, the 
frequency control signal being operative to vary the frequency of the 
output signal toward coincidence with the frequency of the color burst 
component. 
The coarse frequency control circuit gates pulses of a first frequency into 
a counter using an output frequency derived from a VCO gated with another 
signal having a known frequency. At the end of a predetermined number of 
cylces of one of the two frequencies, the content of the counter is 
examined to determine whether too many or too few pulses are counted. If 
too many or too few pulses are counted, a voltage is generated which 
adjusts the VCO frequency upward or downward until it arrives within the 
lock-in range of the APC employing the color burst signal as a reference. 
The APC thereupon assumes control of the VCO and phase locks the VCO to 
the color burst signal. 
According to a feature of the invention, the output of the VCO, which is 
suitably 4 times the color burst frequency counted down by 2, is gated 
into a divide-by-91 counter over a period of four horizontal line 
intervals. If the VCO frequency is exactly correct, exactly 20 cycles of 
the divide-by-91 counter are completed in the four horizontal intervals. 
The divide-by-91 counter, initially reset to zero, should therefore again 
be reset to zero at the end of the 20th cycle. If the divide-by-91 counter 
has been advanced into its 21st cycle because of too many pulses, or has 
not completed its 20the cycle because of too few pulses, the residue in 
the divide-by-91 counter causes an appropriate correction signal to be 
generated by a current converting circuit which is integrated in an 
integrating circuit to provide a correction voltage tending to drive the 
output derived from the VCO frequency into coincidence with the frequency 
of the color burst signal. 
The VCO signal may optionally be divided down by 2 or more and gated into a 
divide-by-n counter with a higher frequency signal of known frequency. For 
example, the video intermediate frequency, stabilized by automatic fine 
tuning in a television receiver, may be used as the signal with a known 
frequency. Thus a number of cylces of the video intermediate frequency 
signal are gated into the divide-by-n counter over a fixed number of VCO 
cycles. At the end of the fixed number of VCO cycles, counting is stopped 
and the number stored in the divide-by-n counter is used as before to 
determine whether the VCO signal is too high, too low or within range. 
According to a further feature of the present invention, there is provided 
a reference carrier generator for a color television receiver having a 
color demodulator comprising a voltage controlled oscillator, operative to 
supply a reference carrier to the color demodulator, phase comparator 
means for comparing phases of an output of the voltage controlled 
oscillator and a color burst signal in a color television signal, an 
output of the phase comparator being supplied to the voltage controlled 
oscillator as a first control signal, gating means for gating an output of 
the voltage controlled oscillator with a reference signal which has a 
known frequency substantially different from said output, reset signal 
generator means for generating a reset signal during part of one cycle of 
the reference signal, counter means for counting an output of the gating 
means and being reset by the reset signal, and decoding means responsive 
to an output of the counter means for generating a second control signal 
supplied to the voltage controlled oscillator said second signal being 
effective to change the frequency of the voltage controlled oscillator. 
The above, and other objects, features and advantages of the present 
invention will become apparent from the following description read in 
conjunction with the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring to FIG. 1, a color television signal at terminal 54 is applied to 
a band pass amplifier 1. Band pass amplifier 1 passes the band of 
frequencies centered on 3.58 MHz containing the color information and the 
color burst signal. The signal from band pass amplifier 1 is applied to an 
automatic phase control circuit 50, a R-Y demodulator 2 and B-Y 
demodulator 3. APC circuit 50 generates first and second quadrature 
signals S.sub.R and S.sub.B phase locked to the color burst signal from 
band pass amplifier 1. First and second quadrature signals S.sub.R and 
S.sub.B are connected to R-Y and B-Y demodulators 2 and 3 respectively 
where they are used to demodulate the color difference signal R-Y and B-Y. 
A pulse signal S.sub.X which is related to the signals S.sub.R and S.sub.B 
is coupled from automatic phase control circuit 50 to a coarse frequency 
control circuit 52. The horizontal synchronizing pulses P.sub.H are also 
applied to coarse frequency control circuit 52. The number of pulses 
S.sub.X which occur over a predetermined number of pulses P.sub.H are 
counted in divide-by-91 counter 25. At the end of the predetermined number 
of horizontal synchronizing pulses P.sub.H, counting is stopped and the 
number then existing in the divide-by-91 counter 25 is examined to 
determine whether the stored number is too high to too low. If the stored 
number is too high or too low, a frequency correction signal 56 is applied 
to automatic phase control circuit 50 to adjust the frequency downward or 
upward as required to bring the frequency of S.sub.X into the capture 
range of automatic phase control circuit 50. Once signal S.sub.X has been 
adjusted into the capture range, APC circuit 50 controls the frequency and 
phase of signal S.sub.X according to the frequency and phase of the color 
burst signal. As a result of signal S.sub.X being frequency and phase 
controlled to the color burst signal, the first and second quadrature 
signals S.sub.R and S.sub.B derived therefrom are also phase controlled in 
relation to the color burst signal. 
A VCO 11 in APC circuit 50 produces a signal S.sub.C (refer to FIG. 2A) 
having a frequency of 4 f.sub.SC =910 f.sub.H, where the color sub-carrier 
frequency is taken as f.sub.SC (=3.58MH.sub.z) and the horizontal 
frequency is taken as f.sub.H, respectively. The signal S.sub.C from VCO 
11 is applied to a flip-flop circuit 12 to trigger the latter at the 
negative going trailing edge of the signal S.sub.C. Flip-flop circuit 12 
produces signals S.sub.X and S.sub.Y whose frequency is 2 f.sub.SC =455 
f.sub.H which are opposite in the phase as shown in FIGS. 2B and 2C, 
respectively. Signals S.sub.X and S.sub.Y are applied to flip-flop 
circuits 13 and 14 to trigger the latter at the trailing edges of the 
signals S.sub.X and S.sub.Y, respectively. Flip-flop circuits 13 and 14 
produce signals S.sub.R and S.sub.B whose frequency is f.sub.SC and which 
are shifted in phase by 90.degree. as shown in FIGS. 2D and 2E, 
respectively. Signals S.sub.Y and S.sub.R are fed to a NAND gate 15 so 
that NAND gate 15 produces a signal S.sub.Z shown in FIG. 2F. Signal 
S.sub.Z is applied to flip-flop circuit 14 to control the latter, so that 
the signal S.sub.B therefrom is delayed by 90.degree. from the signal 
S.sub.R from flip-flop circuit 13. Signals S.sub.R and S.sub.B are fed to 
the demodulators 2 and 3 as demodulating signals, respectively. 
The color television signal from band pass amplifier 1 is also fed to a 
burst gate circuit 16 which then passes therethrough a color burst signal 
contained in the color television signal. This color burst signal is fed 
to a phase comparator 17 to be phase-compared at the appropriate time with 
signal S.sub.R from flip-flop circuit 13. An error voltage from phase 
comparator 17, proportional to the phase error between signals at its 
inputs, is applied through a loop filter 18 and an adder 19 to VCO 11 to 
control the oscillation frequency of the latter until signal S.sub.R 
agrees in frequency and phase with the color burst signal. When thus 
properly phase controlled, signal S.sub.R from flip-flop circuit 13 
becomes a demodulating signal for the R-Y axis and signal S.sub.B from 
flip-flop circuit 14 becomes a demodulating signal for the B-Y axis, 
respectively. 
The pulse signal S.sub.X from flip-flop circuit 12 is also fed to one input 
of an AND gate 21 at the input of coarse frequency control circuit 52. 
Horizontal synchronizing signal P.sub.H (refer to FIG. 3A) is applied to a 
flip-flop circuit 22 which then produces a signal P.sub.B which is 
triggered every horizontal interval as shown in FIG. 3B. Thus signal 
P.sub.B is fed to a flip-flop circuit 23 which then produces a signal 
P.sub.C which is triggered every two horizontal interval as shown in FIG. 
3C. This signal P.sub.C is applied to a flip-flop circuit 24 which is 
triggered every four horizontal intervals to produce signals P.sub.D and 
P.sub.E which are opposite in phase as shown in FIGS. 3D and 3E, 
respectively. Signal P.sub.E is applied to a second input of AND gate 21. 
And gate 21 produces a pulse signal S.sub.XG which is the pulse signal 
S.sub.X from flip-flop circuit 12 during the interval when signal P.sub.E 
is "1". Thus, signal S.sub.XG occurs during the first four horizontal 
intervals in every set of 8 horizontal intervals as shown in FIG. 3F. 
Pulse signal S.sub.XG derived from AND gate 21 is counted in a divide-by-91 
counter 25. Signals P.sub.C and P.sub.C from flip-flop circuits 23 and 24 
respectively are fed to a NAND gate 26 which produces a reset signal 
P.sub.R which is 37 0" in the last two horizontal intervals in the above 8 
horizontal intervals as shown in FIG. 3G. Reset signal P.sub.R is fed to 
divide-by-91 counter 25 to reset it while signal P.sub.R is "0". The 
output from divide-by-91 counter 25 is fed to logic circuits 27 and 28 for 
discrimination. 
Logic circuit 27 generates a signal S.sub.P which is "1" during the fifth 
and sixth horizontal intervals if the number remaining in divide-by-91 
counter 25 when stopped at the end of the first four horizontal intervals 
indicates that the frequency of the VCO is too high. Similarly, logic 
circuit 28 generates a signal S.sub.Q which is "1" during the fifth and 
sixth horizontal intervals if the VCO frequency is too low. 
A current converting circuit 31 is responsive to signal S.sub.P to S.sub.Q 
to generate a current signal -I.sub.O or +I.sub.O respectively which is 
integrated in integrating circuit 41 from cycle to cycle to eventually 
correct the VCO frequency into a range where both S.sub.P and S.sub.Q are 
0. This occurs when divide-by-91 counter 25 is within two input pulses of 
being reset by the last pulse of S.sub.XG and thus contains 89, 90, 0, 1, 
or 2 during the fifth and sixth horizontal intervals. 
Current converting circuit 31 includes a pair of transistors 32 and 33. The 
emitters of transistors 32 and 33 are connected together to a current 
source transistor 34. The collector of transistor 32 is connected to the 
collector of a transistor 35 which also serves as a current source. The 
output S.sub.P from logic circuit 27 is applied to the base of transistor 
32, while the output S.sub.Q from the other logic circuit 28 is applied to 
the base of transistor 33, respectively. The signal P.sub.D from flip-flop 
circuit 24 fed to the base of transistor 34, enables the operation of 
current converting circuit 31. Transistor 34 becomes ON only when the 
signal P.sub.D is "1". Transistor 34 is enabled to pass a constant current 
I.sub.O only during the last four horizontal intervals in the set of 8 
horizontal intervals after the pulse signal S.sub.XG is derived from AND 
gate 21. However, a "1" on signal S.sub.P or S.sub.Q is also required 
before the constant current I.sub.O can flow. 
Integrating circuit 41 has an integrating capacitor 42 connected to the 
collector of transistor 32 in current converting circuit 31. Integrating 
capacitor 42 is also connected to adder 19 through a parallel circuit 
consisting of oppositely polarized diodes 43, 44 oppositely polarized and 
a resistor 45 of high resistance value. 
Divide-by-91 counter 25 can count input 90 pulses before being reset to 
zero on the 91st input pulse. Divide-by-91 counter 25 is reset to be zero 
during the last two horizontal intervals in the above unit of 8 horizontal 
intervals in preparation for the next set of 8 horizontal intervals. 
Accordingly, when the pulse S.sub.XG is fed from AND gate 21 to 
divide-by-91 counter 25 at the beginning of the first of the 8 horizontal 
intervals as shown in FIG. 3, the divide-by-91 counter 25 begins at zero 
and counts 1, 2, 3, . . . at every pulse S.sub.XG. When divide-by-91 
counter 25 reaches a count of 90, it resets on the next input pulse and 
continues to count 0, 1, 2, . . . . 
Logic circuits 27 and 28 are arranged so that the output S.sub.P from logic 
circuit 27 is "1" when the content of divide-by-91 counter 25 is 3, 4, . . 
. 45, and it is "0" when the content of divide-by-91 counter 25 is 46, 47, 
. . . 89, 90, 0, 1, 2, as shown in FIGS. 4A and 4B. The output S.sub.Q 
from logic circuit 28 is "1" when the content of divide-by-91 counter 25 
is 46, 47, . . . 88, and it is "0" when the content of divide-by-91 
counter 25 is 89, 90, 0, 1, 2, . . . 45, as shown in FIGS. 4A and 4C. 
Accordingly, when the content of divide-by-91 counter 25 is 89, 90, 0, 1, 
2, the outputs S.sub.P and S.sub.Q from logic circuits 27 and 28 are both 
"0" , but when the content of divide-by-91 counter 25 is 3, 4, . . . 45, 
output S.sub.P from the logic circuit 27 is "1" and that S.sub.Q from the 
logic circuit 28 is "0". When the content of divide-by-91 counter 25 is 
46, 47, . . . 88, the output S.sub.P from logic circuit 27 is "0" and 
S.sub.Q from logic circuit 28 is "1". 
As described above, the pulse S.sub.XG is applied to divide-by-91 counter 
25 from AND gate 21 during the first four horizontal intervals in the set 
of 8 horizontal intervals. The outputs S.sub.P and S.sub.Q are ineffective 
during the first four horizontal intervals because the signal P.sub.D is 
"0" during this time and inhibits current converting circuit 31. During 
the fifth and sixth horizontal intervals, counting is stopped and signal 
P.sub.D is "1" thus making current converting circuit 31 responsive to a 
"1" on output S.sub.P or S.sub.Q. At the start of the seventh horizontal 
interval, divide-by-91 counter 25 is reset by reset pulse P.sub.R. Thus 
the number in divide-by-91 counter 25 is zero during the seventh and 
eighth horizontal intervals. Thus S.sub.P and S.sub.Q are both "0"during 
these intervals. 
Accordingly, when the oscillation frequency of VCO 11 is exactly 4f.sub.SC 
=910f.sub.H and the frequency f.sub.X of the pulse S.sub.X from flip-flop 
circuit 12 is exactly 2f.sub.SC =455f.sub.H, 1820 pulses S.sub.XG are 
applied to divide-by-91 counter 25 during the first four horizontal 
intervals. Therefore, during these four horizontal intervals, divide-by-91 
counter 25 becomes filled exactly 20 times, and at time t.sub.1, when the 
supply of the pulse S.sub.XG from AND gate 21 to divide-by-91 counter 25 
is stopped, the content thereof is zero. When the oscillation frequency of 
VCO 11 is (910+1/2)f.sub.H and the frequency f.sub.X of the pulse S.sub.X 
from flip-flop circuit 12 is (455+1/4)f.sub.H, exactly 1821 pulses 
S.sub.XG are applied to divide-by-91 counter 25 during the first four 
horizontal intervals. Thus, when counting is stopped at time t.sub.1, 
divide-by-91 counter 25 contains the count of 1. 
As described above, the content of divide-by-91 counter 25 when stopped at 
time t.sub.1 is related to the difference between the frequency of VCO 11 
and the desired frequency and hence is similarly related to the frequency 
f.sub.X of the pulse S.sub.X. Accordingly, the state of divide-by-91 
counter 25 at the time t.sub.1 is related to error in the frequency 
f.sub.S of the demodulating signals S.sub.R and S.sub.B which are fed from 
flip-flop circuits 13 and 14 to demodulators 2 and 3, respectively. 
The following table shows the relation among the frequency F.sub.X of pulse 
S.sub.X from flip-flop circuit 12, the frequency f.sub.S (=1/2f.sub.X) of 
demodulating signals S.sub.R and S.sub.B, the state of divide-by-91 
counter 25 at time t.sub.1, and the states of outputs S.sub.P and S.sub.Q 
from logic circuits 27 and 28 at time t.sub.1. 
__________________________________________________________________________ 
444 455 
455 
455 455 
455 
455 466 
f.sub.X (f.sub.H) 
-- 455 -- 
S.sub.X 
-1/4 -3/4 
-2/4 
-1/4 +1/4 
+2/4 
+3/4 +1/4 
f.sub.S (f.sub.H) 
444 455 
455 
455 
455 
455 
455 
455 466 
2 2 2 2 2 2 2 2 2 
-- -- 
S.sub.R, S.sub.B 
-1/8 -3/8 
-2/8 
-1/8 
(=f.sub.sc) 
+1/8 
+2/8 
+3/8 +1/8 
counter 
25 46 -- 
88 89 90 0 1 2 3 -- 
45 
S.sub.P 
(Decrease) 
"0" 
-- 
"0" 
"0" 
"0" 
"0" 
"0" 
"0" 
"1" 
-- 
"1" 
S.sub.O 
(Increase) 
"1" 
-- 
"1" 
"0" 
"0" 
"0" 
"0" 
"0" 
"0" 
-- 
"0" 
__________________________________________________________________________ 
After time t.sub.1, no further pulses S.sub.XG are applied to divide-by-91 
counter 25, during the two horizontal intervals from time t.sub.1 to time 
t.sub.2. Divide-by-91, the counter 25 and the outputs S.sub.P and S.sub.Q 
from the logic circuits 27 and 28 are in the appropriate states shown in 
the above table according to the content of divide-by-91 counter 25. At 
time t.sub.2, divide-by-91 counter is reset by signal P.sub.R. 
When the frequency f.sub.S of the demodulating signals S.sub.R and S.sub.B 
is within a frequency range of from ((455/2)-1/4)f.sub.H to 
((455/2)+1/4)f.sub.H, namely within the frequency range of .+-.1/4 f.sub.H 
.apprxeq.3.93 KH.sub.z centered on f.sub.SC =3.58 MHz, the outputs S.sub.P 
and S.sub.Q from logic circuits 27 and 28 in two horizontal intervals from 
time t.sub.1 to time t.sub.2 both remain "0". This frequency range is 
within the lock-in range of automatic phase control circuit 50. Therefore, 
transistors 32, 33 and 35 in current converting circuit 31 remain OFF. 
Thus no current is applied to integrating circuit 41 by current converting 
circuit 31. Accordingly, at this time the voltage applied from integrating 
circuit 41 through adder 19 to VCO 11 is not changed. That is, when the 
oscillation frequency of VCO 11 is in the range of .+-.f.sub.H =.+-.15.734 
KH.sub.z centered on 4 f.sub.SC =910 f.sub.H =14.32 MH.sub.z and the 
frequency f.sub.S of the demodulating signals S.sub.R and S.sub.B is in 
the range of .+-.1/4 f.sub.H .apprxeq.3.93 KH.sub.z centered on f.sub.SC 
=3.58 MH.sub.z, the oscillation frequency of VCO 11 and accordingly the 
frequency f.sub.s of the demodulating signals S.sub.R and S.sub.B are 
drawn into a predetermined value by the error voltage from phase 
comparator 17 alone and hence synchronization between demodulation signals 
S.sub.R and the color burst signal is established. 
When the frequency f.sub.S of the demodulating signals S.sub.R and S.sub.B 
is lower than ((455/8)-3/8)f.sub.H, the output S.sub.P from logic circuit 
27 remains "0" during two horizontal intervals from time t.sub.1 to time 
t.sub.2, but the output S.sub.Q from logic circuit 28 is "1" during this 
time. In this condition, transistor 32 in current converting circuit 31 
remains in the OFF condition but transistors 33 and 35 are turned ON. As a 
result, a constant current +I.sub.0 is fed from current converting circuit 
31 to integrating capacitor 42 in integrating circuit 41. The charge 
stored in integrating capacitor 42 increases during the time from t.sub.1 
to t.sub.2 at a rate determined by the magnitude of I.sub.0 and thus the 
voltage at the junction of integrating capacitor 42 and parallel diodes 43 
and 44 increases. Accordingly, at this time the voltage applied from 
integrating circuit 41 through adder 19 to VCO 11 becomes high increases 
and hence the oscillation frequency thereof is raised such that the 
frequency f.sub.s of the demodulating signals S.sub.R and S.sub.B is moved 
toward the lock-in frequency range. After one or more cycles of correction 
during which the voltage across integrating capacitor 42 increases, the 
VCO frequency is raised to within the lock-in range of the APC circuit. 
When the frequency f.sub.s of the demodulating signals S.sub.R and S.sub.B 
becomes higher than ((455/2)+3/8)f.sub.H, during two horizontal intervals 
from time t.sub.1 to t.sub.2, the output S.sub.P from logic circuit 27 is 
"1" and the output S.sub.Q from logic circuit 28 remains "0". Thus, 
transistor 32 in current converting circuit 31 is turned ON while 
transistors 33 and 35 remain OFF. As a result, a negative current -I.sub.0 
is fed from current converting circuit 31 to integrating circuit 41. The 
negative constant current -I.sub.0 flows from integrating capacitor 42 
through transistor 32 partially discharging integrating capacitor 42. 
Accordingly, at this time the voltage applied from integrating circuit 41 
through adder 19 to VCO 11 decreases and hence the oscillation frequency 
thereof is lowered such that the frequency f.sub.s is drawn toward the APC 
lock-in frequency range. 
During two horizontal intervals after time t.sub.2, as described above, 
divide-by-91 counter 25 is reset and the outputs S.sub.P and S.sub.Q from 
logic circuits 27 and 28 are both "0", so that no current is fed to 
integrating circuit 41 and hence the voltage delivered therefrom is not 
changed. 
The above operation is repeated sequentially every 8 horizontal intervals. 
According to the above embodiment of the invention, when the oscillation 
frequency of VCO 11 is within a frequency range of .+-.(45/2) f.sub.H 
.apprxeq.0.354 MH.sub.z centered on 4 f.sub.SC =14.32 MH.sub.z and the 
frequency f.sub.s of the demodulating signals S.sub.R and S.sub.B is 
within the frequency range of .+-.(45/8) f.sub.H .apprxeq.0.0885 MH.sub.z 
centered on f.sub.SC =3.58 MH.sub.z, proper synchronization is achieved. 
That is, if the frequency variation of VCO 11 is within 
.+-.(0.354/14.32).apprxeq..+-.2.5%, of the desired frequency lock-in of 
APC circuit 50 is achievable. It is, of course, clear that if the 
frequency dividing ratio of divide-by-91 counter 25 is higher than 91, the 
lock-in range can be furtherwidened. That is, in the above example, 
divide-by-91 counter 25 is changed to give it a greater capacity and as, 
for example, a divide-by-182 counter, the capture range can be doubled to 
.+-.5%. Accordingly, depending upon the accuracy of VCO 11, the frequency 
dividing ratio of divide-by-91 counter 25 can be selected to compensate 
for the maximum expected range of deviation of VCO 11 from the desired 
frequency. 
Various modifications can be made in the embodiment shown in FIG. 1 without 
departing from the scope of the invention. For example, gating signals for 
the pulse S.sub.X through AND gate 21 and the time when the current is fed 
to integrating circuit 41 may be formed and timed in a different manner 
from the above example. Also, the construction of divide-by-91 counter 25 
can be changed in accordance with the capacity required. Further, the 
construction of logic circuits 27 and 28 can be determined in accordance 
with the construction of divide-by-91 counter 25 and the lock-in frequency 
range of the APC circuit. 
Instead of using the relatively low-frequency horizontal synchronizing 
pulses P.sub.H to gate a number of VCO pulses into divide-by-91 counter 
25, a known frequency higher than the VCO frequency may be gated into 
divide-by-91 counter 25 by the signal S.sub.XG. For example, a picture 
intermediate frequency signal, controlled to a known frequency by 
automatic fine tuning may be substituted for the signal S.sub.X at the 
input of AND gate 21. 
The above pulses including P.sub.E and P.sub.R are produced in response to 
the output pulse S.sub.X from VCO 11 which may be substituted for the 
pulse P.sub.H at the input of flip-flop circuit 22. The pulse P.sub.E 
gates a picture intermediate frequency into divide-by-91 counter 25 for a 
time period that depends on the frequency of S.sub.X. Thus the time 
interval from time t.sub.1 to t.sub.2 is varied, while the frequency of 
the gated video intermediate frequency signal is constant. Therefore, the 
number stored in the counter at time t.sub.2 again varies in 
correspondence with the oscillation frequency of VCO 11, and hence 
discrimination and control of the frequency of VCO 11 in a manner similar 
to the above example is performed. 
According to the present invention, the deviation of the oscillation 
frequecny of VCO 11 in APC circuit 50 may be allowed to extend the lock-in 
range of APC circuit 59 by any reasonable amount such as, for example, 
.+-.2.5%. Therefore expensive quartz crystal oscillators are not required 
in VCO 11. It is possible to therefore use inexpensive CR oscillators or 
the like. The circuits which are added in the present invention are all 
digital circuits which can be made as an integrated circuit at very low 
cost. Therefore the entire circuit including the low-cost VCO and the 
added digital circuits can be made inexpensively. 
Although the above description is given on a single preferred embodiment of 
the present invention, it will be apparent that many modifications and 
variations could be effected by one skilled in the art without departing 
from the spirits or scope of the novel concepts of the invention. 
Therefore, the scope or spirits of the invention should be determined by 
the appended claims.