Semiconductor device including input/output circuit

Disclosed here is an apparatus that comprises a data terminal, a data output circuit including a plurality of output buffers coupled in common to the data terminal, and an impedance control circuit coupled to the data output circuit, wherein the impedance control circuit is configured to generate first impedance code and second impedance code different from the first impedance code and to apply a selected one of the first impedance code and the second impedance code to at least one of the output buffers.

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-123344 filed on Jun. 16, 2014, the disclosure of which are incorporated herein in its entirely by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and particularly to a semiconductor device including an output buffer capable of impedance adjustment.

2. Description of Related Art

A semiconductor device, such as DRAM (Dynamic Random Access Memory), includes an output buffer for outputting data to the outside. The output buffer is so designed that it has a desired impedance when activated. However, the output buffer does not always have the design-based desired impedance because process irregularities and temperature changes affect the output buffer's impedance. For this reason, a semiconductor device required to precisely control the impedance of its output buffer has a built-in impedance adjusting circuit, which is called calibration circuit.

The calibration circuit is configured such that a replica unit identical in circuit configuration with a pull-up unit included in the output buffer is connected to a calibration terminal. The calibration circuit performs calibration by controlling the impedance of the replica unit so that a potential at the calibration terminal matches a desired voltage level and reflecting the controlled impedance on the pull-up unit of the output buffer.

The output buffer may be used as a termination resistor when a write operation is carried out. When the output buffer functions as the termination resistor, the impedance adjusted by the calibration operation is used as the impedance of the output buffer (Japanese Patent Application Laid Open No. 2008-228276, also published as U.S. Pat. Pub. No. 2008-0219068).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be realized using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.

The semiconductor device10of this embodiment is a DDR4 (Double Data Rate 4) DRAM packaged in a single semiconductor chip, and is mounted on an external substrate2. The external substrate2is a memory module substrate or motherboard, and is provided with a reference resistance RZQ. The reference resistance RZQ is connected to a calibration terminal ZQ of the semiconductor device10, and the impedance of the reference resistance RZQ is used as a reference impedance to a calibration circuit50. The reference resistance RZQ is supplied with a ground voltage VSSQ in this embodiment.

Referring now toFIG. 1, the semiconductor device10according to a first embodiment of the present invention includes a memory cell array11. The memory cell array11has multiple word lines WL, multiple bit lines BL and /BL, and memory cells MC arranged at the intersections of the word lines WL and the bit lines BL and /BL. A word line WL is selected by a row decoder12, while a bit line BL is selected by a column decoder13.

Paired bit lines BL and /BL are connected to a sense amplifier SAMP disposed in the memory cell array11. The sense amplifier SAMP amplifies a potential difference created between the bit line BL and the bit line /BL and supplies read data obtained by amplifying the potential difference to a complementary local data line LIOT/LIOB. The read data supplied to the local data line LIOT/LIOB is transferred to a complementary main data line MIOT/MIOB via a switch circuit TG. The read data on the main data line MIOT/MIOB is then converted into a single-ended signal by a main amplifier15and is supplied to a data input/output circuit40via a read/write bus RWBS.

The semiconductor device10also includes an address terminal21, a command terminal22, a clock terminal23, power terminals24and25, a data input/output terminal DQ, and the calibration terminal ZQ, which serve as external terminals.

The address terminal21is a terminal that receives an address signal ADD that is an incoming external signal. The address signal ADD input to the address terminal21is supplied to an address control circuit32via an address input circuit31. Among address signals ADD supplied to the address control circuit32, an address signal ADD representing a row address XADD is supplied to the row decoder12, an address signal ADD representing a column address YADD is supplied to the column decoder13, and an address signal ADD representing a mode signal MADD is supplied to a mode register14.

The mode register14is a circuit with which parameters indicative of an operation mode of the semiconductor device10are registered. The mode register14outputs mode signals, such as impedance selection signals RonA, RonB, and ODTA to ODTC, which are supplied to the data input/output circuit40. The impedance selection signals RonA and RonB are signals for selecting an output impedance at execution of a read operation, and the impedance selection signals ODTA to ODTC are signals for selecting a termination impedance at execution of a termination operation. The termination operation is executed during execution of a write operation.

The command terminal22is a terminal that receives an incoming external command signal COM. The command signal COM input to the command terminal22is supplied to a command decoder34via a command input circuit33. The command decoder34is a circuit that generates various internal commands by decoding the command signal COM. Internal commands include an active signal ACT, a read signal READ, a write signal WRITE, a mode register setting signal MRS, and a calibration signal ZQC.

The active signal ACT is a signal that is activated when the command signal COM indicates a row-accessing command (active command). When the active signal ACT is activated, the row address XADD latched by the address control circuit32is supplied to the row decoder12. As a result, a word line WL specified by the row address XADD is selected.

The read signal READ and the write signal WRITE are activated when the command signals COM indicate a read command and a write command, respectively. When the read signal READ or write signal WRITE is activated, the column address YADD latched by the address control circuit32is supplied to the column decoder13. As a result, a bit line BL specified by the column address YADD is selected.

When the active command and read command are input and the row address XADD and column address YADD are also input in synchronization with input of the active command and read command, therefore, read data is read from the memory cell MC specified by the row address XADD and column address YADD. The read data is transferred to the data input/output terminal DQ via the main amplifier15and the data input/output circuit40and is output from the data input/output terminal DQ to the outside

When the active command and write command are input, and the row address XADD and column address YADD are also input in synchronization with input of the active command and write command, and then write data is input to the data input/output terminal DQ, the write data is supplied to the memory cell array11via the data input/output circuit40and the main amplifier15and is written to the memory cell MC specified by the row address XADD and column address YADD.

The mode register setting signal MRS is a signal that is activated when the command signal COM indicates a mode register setting command. When the mode register setting command is input and the mode signal MADD is input through the address terminal21in synchronization with input of the mode register setting command, therefore, a preset value in the mode register14can be rewritten.

The calibration signal ZQC is a signal that is activated when the command signal COM indicates a calibration command. When the calibration signal ZQC is activated, the calibration circuit50executes a calibration operation, thereby generates impedance codes ZQCODE1and ZQCODE2.

The write signal WRITE is supplied to the data input/output circuit40, where the write signal WRITE dynamically changes the impedances of individual output buffers included in the data input/output circuit40. This process will be described later.

The external terminals included in the semiconductor device10will be described again. The clock terminal23receives incoming external clock signals CK and /CK. The external dock signal CK and the external clock signal /CK are complementary to each other, and are supplied to a dock input circuit35. Receiving the incoming external clock signals CK and /CK, the dock input circuit35generates an internal clock signal PCLK, which is supplied to an internal clock generator36, which then generates a phase-controlled internal dock signal LCLK out of the internal clock signal PCLK. The internal clock generator36is provided as, for example, a DLL circuit, which is, however, not the only circuit used as the internal clock generator36. The internal dock signal LCLK is supplied to the data input/output circuit40, which uses the internal clock signal LCLK as a timing signal for determining timing of outputting read data.

The internal clock signal PCLK is supplied also to a timing generator37, which generates various internal clock signals ICLK based on the internal clock signal PCLK. The internal dock signals ICLK generated by the timing generator37are supplied to such circuit blocks as the address control circuit32and command decoder34, where the internal clock signals ICLK regulate the operation timing of the circuit blocks.

The power terminal24is a terminal supplied with the source voltages VDD and VSS. The source voltages VDD and VSS supplied to the power terminal24are supplied to an internal voltage generator38, which generates various internal voltages VPP, VOD, VARY, and VPERI and a reference voltage ZQVREF, based on the source voltages VDD and VSS. The internal voltage VPP is a voltage used mainly by the row decoder12, the internal voltages VOD and VARY are voltages used by the sense amplifier SAMP in the memory cell array11, and the internal voltage VPERI is a voltage used by a number of other circuit blocks. The reference voltage ZQVREF is a reference voltage used by the calibration circuit50.

The power terminal25is a terminal supplied with source voltages VDDQ and VSSQ. The source voltages VDDQ and VSSQ supplied to the power terminal25are supplied to the data input/output circuit40. The source voltages VDDQ and VSSQ are identical in potential with the source voltages VDD and VSS supplied to the power terminal24, respectively. To prevent power noise generated by the data input/output circuit40from propagating to other circuit blocks, the source voltages VDDQ and VSSQ are used exclusively as source voltages to the data input/output circuit40.

The calibration terminal ZQ is connected to the calibration circuit50. When activated by the calibration signal ZQC, the calibration circuit50carries out the calibration operation, referring to the impedance of the reference resistance RZQ and to the reference voltage ZQVREF. The impedance codes ZQCODE1and ZQCODE2acquired by the calibration operation are supplied to the data input/output circuit40, where the impedance of an output buffer included in the data input/output circuit40is specified according to the impedance codes ZQCODE1and ZQCODE2.

FIG. 2is a circuit diagram showing a part of the data input/output circuit40.

As shown inFIG. 2, the data input/output circuit40includes a FIFO circuit41, a data output circuit42, and an input buffer IB. The FIFO circuit41has latch circuits LT1to LT3that convert parallel read data DATAO and DATAE, which are transferred to the FIFO circuit41via the read/write bus RWBS, into serial data in synchronization with the internal clock signal LCLK. The read data DATAO and DATAE Input as parallel data via the read/write bus RWBS are thus converted into serial read data DATA, which is supplied to the data output circuit42.

The data output circuit42has seven output buffers OB1to OB7connected in parallel between the FIFO circuit41and the data input/output terminal DQ. These output buffers OB1to OB7are identical in circuit configuration with each other, and their impedances for read data output from the data input/output terminal DQ are changed by selecting the number of the output buffers OB1to OB7to be activated. Hereinafter, when distinguishing the output buffers OB1to OB7from each other is not particularly necessary, each of the output buffers OB1to OB7may be simply referred to as “output buffer OB”. Seven output buffers OB1to OB7are used in this embodiment. It is obvious, however, that the present invention does not limit the number of the output buffers OB1to OB7to seven.

According to this embodiment, seven output buffers OB1to OB7are classified into three groups. A first group consists of four output buffers OB1to OB4and is connected to the FIFO circuit41via a logic circuit43and a selector46that are common to the output buffers OB1to OB4. A second group consists of two output buffers OB5to OB6and is connected to the FIFO circuit41via a logic circuit44and a selector47that are common to the output buffers OB5and OB6. A third group consists of one output buffer OB7and is connected to the FIFO circuit41via a logic circuit45and a selector48.

The selectors46to48generate enable signals PUEN and PDEN, based on the read data DATA and the impedance signals RonA, RonB, and ODTA to ODTC, and selectively determine whether or not to activate the output buffers OB1to OB7included in the groups corresponding to the selectors48to48, respectively. The impedance signals RonA and RonB are signals for selecting an output impedance at execution of the read operation, and the impedance signals ODTA to ODTC are signals for selecting a termination impedance at execution of the termination operation.

The termination operation is executed during execution of the write operation. When the write operation is executed, the input buffer IB is activated, so that external data input to the data input/output circuit40via the data input/output terminal DQ is received by the input buffer IB and is transferred to the amplifier15via the read/write bus RWBS. When the input buffer IB receives the data, the output buffer OB carries out the termination operation, which causes the data input/output terminal DQ to function as a termination resistor, thus preventing signal reflection. The output buffer OB is, therefore, activated not only at execution of the read operation but also at execution of the write operation.

According to this embodiment, the impedance selection signals RonA and RonB are supplied to the selectors47and48, respectively, and the impedance selection signals ODTA to ODTC are supplied to the selectors46to48, respectively. An impedance selection signal for impedance selection at execution of the read operation is not input to the selector46. As a result, the output buffers OB1to084are kept activated during execution of the read operation.

Each output buffer OB is so designed that its impedance at execution of the read operation is adjusted to, for example, 240Ω. When the impedance selection signals RonA and RonB are activated so that all the output buffers OB1to OB7are activated, therefore, the overall impedance for read data is 34.3Ω (=240Ω/7). When only the impedance selection signal RonA is activated so that six output buffers OB1to OB6are activated, the overall impedance for read data is 40Ω (=240Ω/6). When only the impedance selection signal RonB is activated so that five output buffers OB1to OB4and OB7are activated, the overall impedance for read data is 48Ω (=240Ω/5). When the impedance selection signals RonA and RonB are deactivated so that four output buffers OB1to OB4are left activated, the overall impedance for read data is 60Ω (=240Ω/4).

Such impedance selection can be performed also at execution of the termination operation in the same manner as described above, using the impedance selection signals ODTA to ODTC. However, by impedance switching, the impedance of the output buffer OB at execution of the termination operation is determined to be different from the impedance of the output buffer OB at execution of the read operation. This impedance switching will be described later.

The impedance of the output buffer OB is not always set to the design-based impedance of 240Ω because process irregularities and temperature changes affects the output buffer's impedance. To correct such an impedance shift, the output buffer OB is provided with an impedance-adjustable pull-up unit PU and an impedance-adjustable pull-down unit PD. Adjustment of the impedance of the output buffer OB is performed by one of the logic circuits43to45corresponding to the output buffer OB.

The logic circuits43to45are each supplied with the enable signals PUEN and PDEN from the corresponding selectors46to48and with a common impedance code ZQCODE3from a selector49. Each of the logic circuits43to45carries out logical calculation using the incoming enable signals PUEN and PDEN and impedance code ZQCODE3to generate impedance codes DCODEPU and DCODEPD, and supplies the generated impedance codes DCODEPU and DCODEPD to the output buffer OB. Hence the impedance of the output buffer OB is adjusted to a desired impedance. The impedance code ZQCODE3is composed of a pull-up impedance code CODEUP and a pull-down impedance code CODEPD, which will be described later.

The selector49selects one of the impedance codes ZQCODE1and ZQCODE2supplied from the calibration circuit50and outputs the selected impedance code as the impedance code ZQCODE3, to the logic circuits43to45. The selector49selects one of the impedance codes ZQCODE1and ZQCODE2based on the write signal WRITE. Specifically, when the write signal WRITE is not activated, that is, when the read operation is carried out, the impedance code ZQCODE1is selected and is output as the impedance code ZQCODE3. When the write signal WRITE is activated, that is, when the write operation is carried out, the impedance code ZQCODE2is selected and is output as the impedance code ZQCODE3.

The impedance code ZQCODE3includes the impedance code CODEPU that adjusts the impedance of the pull-up unit PU and the impedance code CODEPD that adjusts the impedance of the pull-down unit PD. According to this embodiment, each of the impedance codes CODEPU and CODEPD is a 5-bit signal.

FIG. 3is a circuit diagram of the output buffer OB.

As shown inFIG. 3, the output buffer OB is configured such that a resistor RW is interposed between the data input/output terminal DQ and the pull-up unit PU and between the data input/output terminal DQ and the pull-down unit PD. The pull-up unit PU is supplied with the impedance code DCODEPU by which the impedance of the pull-up unit PU is adjusted. The pull-down unit PD is supplied with the impedance code DCODEPD by which the impedance of the pull-down unit PD is adjusted. The resistor RW has a resistance value of, for example, about 40Ω and is made of a tungsten wire, etc.

FIG. 4is a circuit diagram of the pull-up unit PU.

As shown inFIG. 4, the pull-up unit PU is composed of five n-channel MOS transistors TNU0to TNU4connected in parallel. The drains of the transistors TNU0to TNU4are connected in common to a voltage line VL through which the source voltage VDDQ is supplied, while the sources of the transistors TNU0to TNU4are connected to the data input/output terminal DQ via the resistor RW.

The gate electrodes of the transistors TNU0to TNU4are supplied with bits DCODEPU0to DCODEPU4, respectively, the bits DCODEPU0to DCODEPU4making up the impedance code DCODEPU. As a result, five transistors TNU0to TNU4are separately switched on and off based on a value for the impedance code DCODEPU. As shown inFIG. 4, the impedance code DCODEPU is a signal generated by each of the logic circuits43to45in such a way that each bit of the impedance code CODEPU and the enable signal PUEN are logically synthesized through an AND gate circuit.

When the enable signal PUEN is deactivated to its low-voltage level, therefore, the bits DCODEPU0to DCODEPU4making up the impedance code DCODEPU are all put in their low-voltage state regardless of what value the impedance code CODEPU takes, in which case the transistors TNU0to TNU4are all switched off. When the enable signal PUEN is activated to its high-voltage level, on the other hand, a value for the impedance code CODEPU is used directly as a value for the impedance code DCODEPU, in which case some of the transistors TNU0to TNU4are switched on.

The channel width (W)/channel length (L) ratio (W/L ratio), i.e., the current supply capacity of each of the transistors TNU0to TNU4is weighted with a factor of the second power of 2. Specifically, the transistors TNU0to TNU4are designed such that when the W/L ratio of the transistor TNU0is 1WLnu, the W/L ratio of a transistor TNUk (k=0 to 4) is 2K×WLnu. This allows the impedance of the pull-up unit PU to be adjusted in 32 stages at maximum.FIG. 5is a circuit diagram of the pull-down unit PD.

As shown inFIG. 5, the pull-down unit PD is composed of five n-channel MOS transistors TND0to TND4connected in parallel. The sources of the transistors TND0to TND4are connected in common to a voltage line SL through which the source voltage VSSQ is supplied, while the drains of the transistors TND0to TND4are connected to the data input/output terminal DQ via the resistor RW.

The gate electrodes of the transistors TND0to TND4are supplied with bits DCODEPD0to DCODEPD4, respectively, the bits DCODEPD0to DCODEPD4making up the impedance code DCODEPD. As a result, five transistors TND0to TND4are separately switched on and off based on a value for the impedance code DCODEPD. As shown inFIG. 5, the impedance code DCODEPD is a signal generated by each of the logic circuits43to45in such a way that each bit of the impedance code CODEPD and the enable signal PUED are logically synthesized through an AND gate circuit.

When the enable signal PDEN is deactivated to its low-voltage level, therefore, the bits DCODEPD0to DCODEPD4making up the impedance code DCODEPD are all put in their low-voltage state regardless of what value the impedance code CODEPD takes, in which case the transistors TND0to TND4are all switched off. When the enable signal PDEN is activated to its high-voltage level, on the other hand, a value for the impedance code CODEPD is used directly as a value for the impedance code DCODEPD, in which case some of the transistors TND0to TND4are switched on.

The channel width (W)/channel length (L) ratio (W/L ratio), i.e., the current supply capacity of each of the transistors TND0to TND4is weighted with a factor of the second power of 2. Specifically, the transistors TND0to TND4are designed such that when the W/L ratio of the transistor TND0is 1WLnd, the W/L ratio of a transistor TNDk (k=0 to 4) is 2K×WLnd. This allows the impedance of the pull-down unit PD to be adjusted also in 32 stages at maximum.

In this manner, the impedances of the pull-up unit PU and the pull-down unit PD can be adjusted by the impedance codes CODEPU and CODEPD, respectively. As a result, the impedance of the output buffer OB can be adjusted to a desired impedance at execution of the read operation or write operation. In the above example, the pull-up unit PU is composed of five n-channel MOS transistors TNU0to TNU4and the pull-down unit PD is composed of five n-channel MOS transistors TND0to TND4. It is however obvious that the configuration of the pull-up unit and pull-down unit of the present invention is not limited to the above configuration. For example, each of the pull-up unit PU and pull-down unit PD may be composed of six transistors. In such a case, the impedance of each of the pull-up unit PU and pull-down unit PD can be adjusted in 64 stages at maximum. In this manner, the configuration of the pull-up unit PU and pull-down unit PD can be changed properly according to impedance precision that the product is required to have.

At execution of the read operation, either the enable signal PUEN or PDEN is activated to its high-voltage level based on the logical level of the read data DATA. At execution of the read operation, therefore, either the pull-up unit PU or pull-down unit PD is activated based on the logical level of the read data DATA. As a result, the data input/output terminal DQ is put in its high-voltage state or low-voltage state. At execution of the write operation, on the other hand, the enable signal PUEN is activated to its high-voltage level. As a result, the data input/output terminal DQ terminates at the source voltage VDDQ.

FIG. 6is a block diagram of the calibration circuit50.

As shown inFIG. 6, the calibration circuit50has a pull-up replica unit51connected to the calibration terminal ZQ, and a pull-up replica unit52and a pull-down replica unit53that are connected to a node N. The pull-up replica units51and52are replicas of the pull-up unit PU ofFIG. 4and therefore have their impedances adjusted by the impedance code CODEPU. The pull-down replica unit53is a replica of the pull-down unit PD ofFIG. 5and therefore has its impedance adjusted by the impedance code CODEPD. These replica units51to53and control circuits54and55(which will be described later) are properly put in activated state or deactivated state, based on the calibration signal ZQC. Resistors RW are connected in series to the replica units51to53, respectively.

The calibration circuit50operates in the following manner.

As the pull-up replica unit51is put in activated state, a voltage appearing at the calibration terminal ZQ is compared with the reference voltage ZQVREF through the control circuit54. By this comparison, the impedance of the pull-up replica unit51is compared with the impedance of the reference resistance RZQ. Based on the result of this impedance comparison, the impedance code CODEPU is updated. The updated impedance code CODEPU is supplied to the pull-up replica unit51. As a result, the impedance of the pull-up replica unit51is adjusted to an impedance almost equal to the impedance of the reference resistance RZQ. The impedance of the pull-up replica unit51is also reflected on the pull-up replica unit52.

Subsequently, as the pull-up replica unit52and the pull-down replica unit53are put in activated state, a voltage appearing at the node N is compared with the reference voltage ZQVREF through the control circuit55. By this comparison, the impedance of the pull-up replica unit52is compared with the impedance of the pull-down replica unit53. Based on the result of this impedance comparison, the impedance code CODEPD is updated. The updated impedance code CODEPD is supplied to the pull-down replica unit53. As a result, the impedance of the pull-down replica unit53is adjusted to an impedance almost equal to the impedance of the reference resistance RZQ.

By such a calibration operation, the impedance code ZQCODE1composed of the impedance codes CODEPU and CODEPD is generated. The impedance code CODEPU is input to a conversion circuit56that changes a value for the impedance code CODEPU. Thus, the impedance code CODEPU having a changed value and the impedance code CODEPD makes up the impedance code ZQCODE2.

The conversion circuit56changes a value for the impedance code CODEPU by subtracting a given value from the value for the impedance code CODEPU so that the impedance of the pull-up unit PU becomes higher. A subtraction value is not particularly specified. It is nevertheless preferable that the subtraction value be determined to be a value by which the value for the impedance code CODEPU is reduced within a range of specified impedance so that signal integrity at execution of the write operation is improved. For example, when the subtraction value is “100b” and the value for the input impedance code CODEPU is “10101b”, the changed value for the impedance code CODEPU given by the conversion circuit56is “10001b”.

As described above, the Impedance codes ZQCODE1and ZQCODE2generated in such a manner are input to the selector49included in the data input/output circuit40. The impedance code ZQCODE1is selected when the read operation is carried out, and the impedance code ZQCODE2is selected when the write operation including execution of the termination operation is carried out.

As a result, the impedance of the pull-up unit PU becomes higher at execution of the write operation than at execution of the read operation. For example, when a high-level signal is output at execution of the read operation, the impedance of each output buffer OB is 240Ω, which is equal to the impedance of the reference resistance RZQ. When the termination operation is executed during execution of the write operation, the impedance of each output buffer OB is, for example, 280Ω, which is higher than the impedance of the reference resistance RZQ. An impedance difference (40Ω in this case) is defined by the subtraction value for subtraction made by the conversion circuit56. To obtain a desired impedance difference, therefore, the subtraction value for subtraction made by the conversion circuit56is determined to be a proper value.

FIG. 7depicts signal waveforms appearing at the data input/output terminal DQ, includingFIG. 7(A)showing a signal waveform appearing at execution of the read operation andFIG. 7(B)showing a signal waveform appearing at execution of the write operation.

As shown inFIG. 7(A), when the impedance of the output buffer OB is adjusted to 240Ω at execution of the read operation, the amplitude VR1of read data is obtained as a desired amplitude. Similarly, when the impedance of the output buffer OB is adjusted to 240Ω at execution of the write operation, as shown inFIG. 7(B)the amplitude VW1of write data is obtained as a desired amplitude. According to this embodiment, however, the impedance of the output buffer OB is changed to, for example, 280Ω at execution of the write operation, as a result of which the amplitude VW1of the write data increases to an amplitude VW2. This is because that the higher output buffer impedance suppresses termination performance to the source voltage VDDQ, which leads to a drop in the low-voltage level VIL of the write data.

If the impedance of the output buffer OB is adjusted to 280Ω also at execution of the read operation, the amplitude VR1of the read data decreases to an amplitude VR2. This is because that the higher output buffer impedance at execution of the read operation reduces drive performance, which leads to a rise in the low-voltage level VOL of the read data.

According to this embodiment, the impedance of the output buffer OB is determined to be a default impedance (e.g., 240Ω) at execution of the read operation and to be an impedance (e.g., 280Ω) higher than the default impedance at execution of the write operation. Hence the impedances at execution of the read operation and write operation are switched dynamically. As a result, the amplitude of the write date can be increased to the amplitude VW2at execution of the write operation without decreasing the amplitude VR1of the read data at execution of the read operation.

FIG. 8is a block diagram of a configuration of an information processing system according to a second embodiment.

As shown inFIG. 8, the information processing system according to the second embodiment is configured such that multiple semiconductor devices10A and10B are connected to a controller4. The controller4is connected to the semiconductor devices10A and10B via a common command address bus5and via a common data bus6. An address signal ADD and command signal COM output from the controller4are, therefore, input to both semiconductor devices10A and10B. Write data DQ output from the controller4is also input to both semiconductor devices10A and10B.

In contrast, separate chip select signals CSB are assigned to the semiconductor devices10A and10B, respectively. Specifically, a chip select signal CSB0is supplied to the semiconductor device10A via a control bus7A, while a chip select signal CSB1is supplied to the semiconductor device10B via a control bus78. The chip select signals CSB0and CSB1are signals for selecting the semiconductor devices10A and10B, respectively. This configuration allows the controller4to exclusively select one of the semiconductor devices10A and10B.

The information processing system having such a configuration can cause an unselected one of the semiconductor devices10A and10B to execute the termination operation. For example, when the write operation is executed on the semiconductor devices10A, four output buffers OB of the selected semiconductor device10A are activated to execute the termination operation as one output buffer OB of the unselected semiconductor device10B is activated to execute the termination operation, as shown inFIG. 9(A). In contrast, when the write operation is executed on the semiconductor devices10B, four output buffers OB of the selected semiconductor device10B are activated to execute the termination operation as one output buffer OB of the unselected semiconductor device10A is activated to execute the termination operation, as shown inFIG. 9(B).

According to this embodiment, the impedance of the output buffer OB is made higher than the default impedance not only at execution of the termination operation by the semiconductor device10A or10B that executes the write operation but also at execution of the termination operation by the semiconductor device10A or10B that is not selected for executing the write operation. As a result, the synthesized impedance of the semiconductor device10A and10B is enhanced. This allows the amplitude of write data to be increased at execution of the write operation.

To realize the above operation, the system should be configured such that even if the chip select signal CSB is deactivated, impedance code switching by the selector49can be executed through recognition of a write command. For example, when a write command is issued as the chip select signal CSB0is activated and the chip select signal CSB1is deactivated, the semiconductor device10A executes the write operation while the semiconductor device10B executes the termination operation and the impedance of the output buffer OB at that point is adjusted based on the impedance code ZQCODE2.

In addition to impedance control according to the above embodiment, the number of output buffers OB to be activated may be changed dynamically for execution of the read operation or write operation. For example, four output buffers OB may be activated at execution of the read operation and two output buffers OB may be activated at execution of the write operation. In such a case, the overall impedance of the data input/output circuit42relative to the data input/output terminal DQ is 60Ω (=240Ω/4) at execution of the read operation and is 140Ω (=280Ω/2) at execution of the write operation.

As described above, an apparatus comprises a data terminal DQ, a data output circuit42including a plurality of output buffers OB1˜OB7coupled in common to the data terminal DQ, and an impedance control circuit (a calibration circuit)50coupled to the data output circuit42. The impedance control circuit50is configured to generate a first impedance code ZQCODE1and a second impedance code ZQCODE2different from the first impedance code ZQCODE1, and to apply a selected one of the first impedance code ZQCODE1and the second impedance code ZQCODE2to at least one of the output buffers OB1˜OB7.

The impedance control circuit50is configured to apply the selected one of the first impedance code ZQCODE1and the second impedance code ZQCODE2through a selector49. The selector49is configured to receive the first impedance code ZQCODE1and the second impedance code ZQCODE2and output the selected one of the first impedance code ZQCODE1and the second impedance code ZQCODE2. The selector49is configured to select the first impedance code ZQCODE1during a read mode and select the second impedance code ZQCODE2during a write mode.

The apparatus further comprises a plurality of bit lines, a plurality of word lines, and a plurality of memory cells arranged at intersections of the bit lines and the word lines, respectively. Data is read from at least one of the plurality of memory cells during the read mode, data is written into at least one of the plurality of memory cells during the write mode.

The impedance control circuit50is configured to generate the first impedance code ZQCODE1and the second impedance code ZQCODE2responsive to a calibration command. The impedance control circuit50is configured to apply the first impedance code ZQCODE1to at least one of the output buffers OB1˜OB7responsive to a read command, and to apply the second impedance code ZQCODE2to at least one of the output buffers OB1˜OB7responsive to a write command different from the read command.

The apparatus further comprises a conversion circuit56configured to convert the first impedance code ZQCODE1into the second impedance code ZQCODE2. The second impedance code ZQCODE2comprises a plurality of bits of which one or more bits are converted from corresponding one or more bits of a plurality of bits of the first impedance code ZQCODE1.

A method comprises generating a first impedance code ZQCODE1and a second impedance code ZQCODE2different from the first impedance code ZQCODE1, selecting the first impedance code ZQCODE1during a read mode, applying the first impedance code ZQCODE1which is selected to a data output circuit42during the read mode, selecting the second impedance code ZQCODE2during a write mode, applying the second impedance code ZQCODE2which is selected to the data output circuit42during the write mode, reading data from at least one of a plurality of memory cells during the read mode, and writing data into at least one of the plurality of memory cells during the write mode.

The applying the first impedance code ZQCODE1includes set the data output circuit42to have a first impedance and the applying the second impedance code ZQCODE2includes setting the data output circuit42to have a second impedance. The second impedance is larger than the first impedance.

An apparatus comprises a data terminal DQ, a data input buffer IB coupled to the data terminal DQ to receive write data in a write mode, and a data output circuit42coupled to the data terminal DQ. The data output circuit42includes a plurality of output buffers OB1˜OB7of which at least one output buffer being configured to output read data to the data terminal DQ with a first impedance in a read mode and configured to be a termination resistor with a second impedance in the write mode. Another of the plurality of output buffers OB1˜OB7is configured to output the read data to the data terminal DQ with the first impedance in the read mode.

Each of the plurality of output buffers OB1˜OB7includes a pull-up unit and a pull-down unit. At least one of the pull-up unit and the pull-down unit of the at least one output buffer is configured to take different impedances in the read mode and the write mode.

The apparatus further comprises an impedance control circuit (a calibration circuit)50coupled to the data output circuit42. The impedance control circuit50is configured to generate a first impedance code ZQCODE1and a second impedance code ZQCODE2, and to provide the at least one output buffer with the first impedance code ZQCODE1in the read mode and provide the at least one output buffer with the second impedance code ZQCODE2in the write mode. The impedance control circuit50is configured to convert a part of the first impedance code ZQCODE1to generate the second impedance code ZQCODE2.