Method for identifying a fault at a device output and system therefor

A method includes receiving a first signal at an input of a device driver included at an electronic device, the first signal representing first information. A second signal representing the first information is provided at an output of the device driver. The output of the device driver, under normal operating conditions, is coupled to an output terminal of the electronic device. A third signal at the output terminal is received at feedback circuitry of the electronic device. The feedback circuitry identifies a fault at the output terminal based on the third signal and the first signal.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application is related to co-pending U.S. patent application Ser. No. 15/790,192, entitled “METHOD FOR IDENTIFYING A FAULT AT A DEVICE OUTPUT AND SYSTEM THEREFOR” filed on Oct. 23, 2017, the entirety of which is herein incorporated by reference.

FIELD OF THE DISCLOSURE

This disclosure relates generally to integrated circuits, and more particularly to identifying a fault at a device output.

BACKGROUND

An electronic system can include multiple devices, such as integrated circuits. An electronic device can include circuitry to interface with another device. For example, an integrated circuit can include an output terminal and an associated output driver for transmitting information to another integrated circuit. The information can be encoded and transmitted using a voltage or a current signal. For example, an output driver can include push-pull circuitry to provide a signal where the information to be transmitted is encoded using discrete voltage levels corresponding to a logic-high or a logic-low state. Alternatively, an output driver can selectively enabled to sink current provided by external pull-up circuitry, where particular levels of the sink current corresponding to individual logic states. Furthermore, an output driver can provide an analog interface, in which case the output driver provides a continuously range of voltage or current instead of discrete levels. Many failures that can occur within an electronic device can be detected using testing protocols and associated test circuitry. For example, the logic state of latch devices can be evaluated using test-scan technology. Other forms of built-in self-test can validate the operation of a functional block by providing diagnostic stimulus and evaluating how the functional block responds to the stimulus. Faults associated with output drive circuits can be difficult to identify, especially while the electronic system is functioning in its normal operating mode. Faults associated with an output driver can include defective transistors in the driver circuit, broken or shorted bonding wires, damaged cables or connectors that couple the output signal to the receiving device, failed electrostatic-discharge protection components, defective printed circuit board conductors, and the like. Undetected faults can have serious implications. For example, a fault in an automotive emergency braking system can result in a collision.

DETAILED DESCRIPTION OF THE DRAWINGS

FIGS. 1-7illustrate techniques for detecting a fault condition at an output driver of an electronic system. Faults can include open circuit conditions and short circuit conditions. For example, a bond wire used to connect a terminal of an integrated circuit (IC) die to a corresponding IC package can fail, typically resulting in an open circuit condition. IC interfaces typically include electrostatic-discharge (ESD) devices that can fail creating a short circuit to a power or ground supply rail. In an automotive environment, the driving and receiving devices are likely coupled using cables and one or more electrical connectors, where a fault usually results in an open circuit condition. Techniques disclosed herein provide a feedback signal at an output driver that can be used to detect open circuit and short circuit faults, as well as faults that cause other anomalous load characteristics. For example, the feedback signal can monitor the transition time of an output signal and determine if the transition time is faster or slower than expected. The disclosed techniques can be utilized for either voltage or current based interfaces. While the techniques are described in the context of an interface between individual integrated circuits, the techniques can be utilized at any functional boundary, such as the interface of intellectual property (IP) blocks included at a system on chip (SOC) device.

FIG. 1is a schematic diagram illustrating output driver circuitry100to detect a fault condition at a device interface according to a specific embodiment of the present disclosure. For example, output driver circuitry100can be included at an application-specific integrated circuit (ASIC) or at another type of electronic device. The output driver circuitry100includes an output driver110, ESD protection devices112, an output terminal114coupled to an output load119via a bond wire118, feedback circuit116, and an error flag latch120. Also illustrated are latches102,104, and108, and logic106that are included to represent portions of a functional block that generates state information represented by signal BI. Output driver110is configured to propagate the state information to terminal114. Feedback circuit116includes a first input to receive signal BI from the input of output driver110, a second input to receive a signal VOUTpresent at output terminal114, and an output to provide a signal labeled ERROR. Error latch120includes an input to capture the logic state of signal ERROR and an output to provide signal ERROR FLAG.

Latches102,104, and108include a clock input terminal to receive a clock signal, CLK. Error flag latch120includes a clock input terminal that can be configured to receive clock signal CLK, however in the embodiment illustrated, the clock input terminal of error flag latch120receives a clock signal from delay circuit122. Delay circuit122is configured to generate a delayed version of clock signal CLK, as described below. Latches102,104,108, and error flag latch120are interconnected to provide a scan chain124. Scan chain124provides a means to store and retrieve state information at each latch, including error information stored at error flag latch120. Scan chain124includes an input labeled Scan_in, and an output labeled Scan_out.

During operation, state information encoded by signal BI is provided to an input terminal of output driver110. State information can be represented by a logic-high voltage signal or a logic-low voltage signal. In an embodiment, output driver110is configured to communicate state information represented by signal BI to output terminal114, also in the form of a logic-high voltage signal or a logic-low voltage signal. Output terminal114can be coupled to an input of another device, represented by output load capacitor119that is intended to receive the state information. Because a total capacitive load associated with terminal114and the receiving device can be greater than latch108is capable of driving, output driver110can include a buffer that provides greater drive capability. If there is not a fault associated with output terminal114, signal VOUTwill represent the same state information represented by signal BI that is provided to the input of output driver110. However, if there is a fault associated with output terminal114, signal VOUTcan be corrupted. For example, signal VOUTcan be stuck at a logic-low level, stuck at a logic-high level, fail to fully transition to a legal logic level, or transition from one logic state to another logic state to quickly or too slowly. Feedback circuit116is configured to identify these corruptions.

In another embodiment, output driver110can be configured to provide a current-based interface, often referred to as an open-collector interface. During operation, output driver110converts state information represented by signal BI as described above into a corresponding sink current. A pull-up resistor or a transistor-based current source, that can be included in the receiving device, is configured to elevate a voltage at terminal114unless countered by the sink current provided by output driver110. For example, if signal BI is at a logic-low level, output driver110can be configured to sink a first amount of current, such as seven milliamps, and if signal BI is at a logic-high level, output driver110can be configured to sink a second amount of current, such as fourteen milliamps. The receiving device coupled to output terminal114can interpret the variation in sink current to represent the original state information represented by signal BI.

During operation, feedback circuit116is configured to identify one or more fault conditions associated with output terminal114. If a fault condition is identified, feedback circuit116can assert signal Error, which can subsequently be latched by error flag latch120. In particular, feedback circuit116is configured to compare a voltage level of signal BI at the input of output driver110with a voltage level of signal VOUTat the output of output driver110. The voltage level of signal VOUTis influenced by the characteristics of output driver110and of the external load119. For example, output driver110can be damaged, preventing state information BI from being properly propagated to the external load. For another example, ESD protection devices112can be damaged, resulting in a short circuit of signal VOUTto the power or ground nodes. Other circuit failures include a break in bond wire118or an open or short circuit in conductors at the device receiving signal VOUT. Other circuit failures can result in the load impedance represented by external load119being too low or too high, which can result in kick-back noise, signal ringing, and the like. Feedback circuitry116can include error logic which may be adapted by the designer for special needs of error detection to provide functional safety. Because error flag latch120is configured within scan chain124, an error identified by feedback circuit116can be detected by internal built-in self test circuitry. Operation of feedback circuit116can be better understood with reference toFIG. 2, below.

FIG. 2is a schematic diagram illustrating feedback circuit116ofFIG. 1according to a specific embodiment of the present disclosure. Feedback circuit116includes a variable resistor202, a variable resistor204, a voltage comparator204, a voltage comparator206, logic gates208,210, and212, and error logic216. Logic gate208provides an AND function, logic gate210provides an XOR function, and logic gate212provides an OR function. Feedback circuit116receives signal VOUTfrom output terminal114. Signal VOUTis connected to a non-inverting input of comparator204and to a non-inverting input of comparator206. Variable resistors202and204are connected in series. A remaining terminal of variable resistor202is connected to a supply voltage reference, Vdd, and a remaining terminal of variable resistor204is connected to a ground voltage reference, Vss. A variable tap at resistor202is configured to provide a reference voltage VKto an inverting input of comparator204, and a variable tap at resistor204is configured to provide a reference voltage VMto an inverting input of comparator206. One of skill will appreciate that while variable resistors202and204are illustrated, voltage references VKand VMcan be generated by other means, such as using one or more digital to analog converters, a band-gap voltage reference, and the like.

Comparator204has an output to generate signal K+, which is connected to a first input of logic gate208, a first input of logic gate210, and a first input of logic gate212. Similarly, comparator206has an output to generate signal M+, which is connected to a second input of logic gate208, a second input of logic gate210, and a second input of logic gate212. Logic gate208has an output to generate a signal, H, logic gate210has an output to generate a signal, XOR, and logic gate212has an output to generate signal, L. Error logic216includes a first input to receive signal H, a second input to receive signal XOR, a third input to receive signal L, a fourth input to receive signal BI, and an output to provide a signal, ERROR.

During operation, signal M+ is asserted if a voltage level of signal VOUTexceeds threshold voltage VMand signal K+ is asserted if a voltage level of signal VOUTexceeds threshold voltage VK. For example, reference voltages VMand VKcan be selected so that signal K+ is asserted if signal VOUTrepresents a valid logic-high level, and M+ is not asserted if signal VOUTrepresents a valid logic-low level. Signal H is asserted if both signals K+ and M+ are asserted, signal XOR is asserted only if signals K+ and M+ represent opposite logic states, and signal L is asserted if either signals K+ or M+ are asserted.

Error logic216is configured to determine that a fault is associated with output terminal114. For example, if signals H, L, and XOR are each at a logic-low level, this can be indicative of a short circuit between terminal114and a ground reference voltage. If signals H and L are each at a logic-high level and signal XOR is at a logic-low level, this can be indicative of a short circuit between terminal114and a supply reference voltage. Signal XOR is asserted if a voltage level of signal VOUTis between the levels of reference voltages VMand VK. Accordingly, if signal XOR is asserted, a duration (pulse width) of the assertion is representative of a transition time of signal VOUT. In an embodiment, error logic216can determine whether the transition time of signal VOUTas indicated by signal XOR is less than a first predetermined value or greater than a second predetermined value. For example, if the transition time of signal VOUTis too fast, this can be indicative of an open circuit fault at terminal114. If the transition time of signal VOUTis too slow, this can be indicative of excessive resistive or capacitive load at terminal114. The duration of the assertion of signal XOR can be determined using a counter, and analog to digital converter, or another suitable technique. In an embodiment, error logic216can determine a propagation delay of output driver110, which can be indicative of a fault. For example, error logic216can measure a period of time between the assertion or de-assertion of signal BI and a corresponding assertion/de-assertion of signal VOUT.

FIG. 3is a timing diagram300illustrating the operation of feedback circuit116ofFIGS. 1 and 2according to a specific embodiment of the present disclosure. Timing diagram300includes a horizontal axis representing time and a vertical axis representing voltage. Timing diagram300further includes waveform301representing signal BI, waveform302representing signal VOUT; threshold voltage M,304; threshold voltage K,306; signal H,310; signal XOR,312; signal L,314; and time references350,351,352,353, and354. Waveform301illustrates a transition of signal BI from a logic low level to a logic high level. In response to the transition of signal BI, signal VOUT(waveform302) begins transitioning at time reference351and completes transitioning at time reference354. At time reference352, a voltage level of signal VOUThas reached threshold voltage M304; and at time reference353, the voltage level of signal VOUThas reached threshold voltage K306. The period of time from time reference350to time reference352can be referred to as the reaction delay of output driver110, and the period of time from time reference350to time reference353can be referred to as the propagation delay of output driver110. As described above, signal H is asserted by AND gate208at time reference353when a voltage level of signal VOUTexceeds threshold voltage K. Signal XOR is asserted at time reference352when the voltage level of signal VOUTexceeds threshold voltage M, and is de-asserted when the voltage level of signal VOUTfurther rises and exceeds threshold voltage K. Signal L is asserted when the voltage level of signal VOUTexceeds threshold voltage M. One of skill will appreciate that while waveform302is illustrated as a piece-wise-linear form, waveform302is like exponential in shape as would be expected when driving a load having resistance and capacitance characteristics. Furthermore, while output driver110and signal VOUT are described in the context of a digital logic interface, one of skill will be appreciated that compare logic116and the concepts described above can be applied to an analog interface.

Returning toFIG. 2, error logic216can assert signal ERROR if a fault associated with output terminal114is detected. As described above, signal ERROR can be latched by error flag latch120ofFIG. 1. In an embodiment, a delay provided by delay circuit122can be adjusted to control when signal ERROR is latched at error flag latch120. For example, delay circuit122can include selectable buffer delays, a delay-locked-loop, and the like, to delay the generation of signal CLK_D relative to signal CLK. A digital data processing device, such as an ASIC device, can include a clock circuit to generate one or more internal clock signals. For example, latch108includes an input to receive a clock signal, CLK, which controls the timing of signal BI. Output driver110and feedback circuit116each introduce delay. Signal ERROR is captured by latch120based on the delayed clock signal CLK_D. Accordingly, the propagation delay of signal VOUTrelative to signal BI (and clock signal CLK) can be measured by adjusting the delay of clock signal CLK_D.

FIG. 4is a schematic diagram illustrating an output driver circuit400to detect a fault condition at a device interface that operates in a current domain, according to a specific aspect of the present disclosure. Similar to output driver circuit100ofFIG. 1, output driver circuit400is configured to communicate information from an electronic device, which includes output driver circuit400, to another device. The information is encoded using two or more discrete current sink values. For example, a first logic state can be represented by one particular sink current, while another logic state can be represented by a different sink current. A current is received at an output terminal441from a source that is external to driver circuit400. For example, a current source can be provided by a pull-up resistor or transistor circuit included at the receiving device, or pull-up circuitry external to both the transmitting and receiving devices. Output driver circuit400is configured to selectively sink predefined current values corresponding to each of two or more logic states. The selective sink current and external current source, together, form a voltage divider. Accordingly, a voltage, VOUT, at an output terminal441will vary depending on the amount of current sunk by output driver circuit400. The sink current is labeled, IOUT, atFIG. 4.

Output driver circuit400includes transistors401,402,403,404,405,406,407,408,409,411,412,413,414,416,417,432,433,434,436, and437; resistors421,422,425, and426; capacitors423,424, and427; a current source410; a diode444; inverters451and452; and the output terminal441. The external current source and receiving device are represented by resistor443, Rload, and parasitic capacitor442, which are coupled to output driver circuit400via a bond wire444to output terminal441. Resistor443and parasitic capacitor442are coupled to a power supply Vext, indicated by the diagonal supply symbol, that is associated with the device receiving information from output driver circuitry100. Output driver circuit400is best described by partitioning the circuit into functional blocks. The functional blocks include a high voltage output circuit481, a current sink mirror482, a feedback current mirror483, a reference current circuit484, a current level switch485, and a current comparator486, which are described below.

Circuit400provides a current path480from the output terminal441to a ground reference voltage, Vss. Current path480conducts the selected sink current, IOUT, and includes a series connection of current electrodes of transistors405,402, and404. As used herein, current electrodes of a transistor include drain/source terminals of a field-effect transistor, collector/emitter terminals of a bipolar transistor, and the like. A gate or base terminal of a transistor is herein referred to as a control electrode. During operation, a voltage at the control electrode of transistor402determines how much current is permitted to flow in current path480. For example, the control electrode of transistor402is used to selectively control the magnitude of a sink current provided at output terminal441.

High voltage output circuit481includes output terminal441, transistor405, diode444, capacitor442, and resistor443. Diode444represents an electrostatic discharge protection circuit. Output driver circuit400can support communication with a receiving device that operates at a supply voltage, Vext, that is greater than a supply voltage, Vdd, of the transmitting device that includes driver circuit400. Accordingly, transistor405is a high voltage transistor configured to isolate transistors402and404from Vext. In particular, the drain of transistor405is fabricated to withstand the maximum specified external supply voltage Vext. In an embodiment, the control electrode of transistor405is coupled to a supply voltage, Vcas, that is greater than the supply voltage Vdd so that transistor405does not further limit the amount of current that can flow at current path480. Supply voltage Vcas can be generated using a charge pump based on supply voltage Vdd.

Reference current circuit484includes current source410and transistor411. Current source410provides a reference current, Ir, to a current electrode and a control electrode of transistor411. Current source410can be external or internal to output driver400, and can be provided by a bandgap circuit, or another type of current source. In an embodiment, current source410provides a small but highly accurate current, and can include features to support trimming the value of reference current Ir. For example, a current value provided by current source410can be regulated or calibrated using laser-trimming at the die level, fuse programming, programmable digital to analog converter circuitry, and the like. Transistor411is configured as a source device of a plurality of current mirrors. Transistor412,413,414,416, and417are each configured to mirror reference current Ir. A current mirror is a circuit configuration where a transistor is biased to conduct an amount of current that is proportional to a current conducted in another transistor. As used herein, the phrase mirroring a current conducted at a first transistor at a second transistor is intended to mean that the second transistor is biased to conduct a maximum current that is proportional to a current conducted at the first transistor. One of skill will appreciate that the actual current conducted at the second transistor may be less than the maximum value. As described below, each current mirror can be configured to provide gain, wherein the mirrored current is an integer or non-integer multiple of the reference current Ir.

Capacitor427is a fabricated capacitor to stabilize operation of the current mirror. For example, capacitor427can be a gate-oxide capacitor, a metal plate capacitor, and the like. Current level switch485includes transistor412,413,414,432,433, and434. Control electrodes of each of transistors412,413, and414are connected to the control electrode of transistor411so that a current at the drain terminals of each of transistors412,413, and414provides a current that mirrors reference current Ir. Furthermore, the effective width of transistors412,413, and414are configured to provide specific currents, IrH, IrL, and IrS, that are each a multiple of reference current Ir. For example, the effective width of transistor412can be three times the effective width of transistor411so that a value of current IrS is three times the value of reference current Ir; the effective width of transistor413can be seven times the effective width of transistor411so that a value of current IrL is seven times the value of reference current Ir; and the effective width of transistor414can be fourteen times the effective width of transistor411so that a value of current IrH is fourteen times the value of reference current Ir. One of skill will appreciate that other multiplicative values can be selected. Furthermore, while three mirror devices are illustrated, the current level switch can include as few as two mirror devices, or can include greater than three mirror devices.

The effective width of a transistor refers to the total current carrying capacity of the transistor, or plurality of transistors, when activated. The current carrying capacity of a transistor is determined based on a width and length of a channel formed when the transistor is activated. As used herein, an effective width of a transistor can be provided by fabricating a single transistor with a desired channel width, or by providing two or more transistor that provide a parallel path for current to travel. For example, an effective width of ten microns can be provided by a single transistor have a channel width of ten microns, by two transistors having a channel width of approximately five microns that are connected in parallel, and the like.

Transistors432,433, and434are configured as switches that can be activated by signals Sw_S, Sw_L, and Sw_H, respectively. During operation, one or more of transistors432,433, and434can be activated by asserting a corresponding one or more of signals Sw_S, Sw_L, and Sw_H to adjust a value of output current IrO that is generated by the current level switch. For example, based on the exemplary values described above, asserting signals Sw_S and Sw_L simultaneously would result in output current IrO having a value equal to the sum of currents IrS (3×Ir) and IrL (7×Ir), or ten times the value of reference current Ir. During operation, switches Sw_S, Sw_L, and Sw_H are activated and deactivated to control a sink current provided by output driver400at output terminal441, the activation and deactivation determined based on state information being transmitted to the receiving device. For example, a logic-high state may correspond to a sink current corresponding to the assertion of signal Sw_H and a logic-low state may correspond to a sink current corresponding to the assertion of signal Sw_L. For another example, a logic-high state may correspond to a sink current corresponding to the assertion of signal Sw_H and signal Sw_L, and a logic-low state may correspond to a sink current corresponding to the assertion of signal Sw_L; or other switch configurations that provide discrete values of sink current at output terminal441that correspond to logic respective state values.

Current sink mirror482includes transistor401and transistor402. The control electrode of transistor401is connected to the control electrode of transistor402, and this circuit node is labeled Vr. During operation, current IrO selected by the current level switch485and conducted by transistor401is mirrored by transistor402. In an embodiment, the effective width of transistor402is greater than the effective width of transistor401so that the mirrored current conducted by transistor402is an integer or non-integer multiple of current IrO. The ratio of the effective width of transistor402to the effective width of transistor401, and accordingly the current gain provided by the current sink mirror, will be referred to herein as current gain J. In other words, transistor402is configured to conduct a current equal to J×IrO. For example, a current gain of ten can be provided by selecting an effective width of transistor402that is ten times the effective width of transistor401. Providing gain at current sink mirror482reduces current consumption and associated power dissipation of current level switch485, current comparator486, and reference current circuit484. The current gain J can be a fixed value by design. Alternatively, transistor402can be replaced with multiple output transistors and the gain J can be made adjustable by switches operable to select one or more of the output transistors. Capacitor424is a fabricated capacitor to stabilize operation of current sink mirror482. For example, capacitor424can be a gate-oxide capacitor, a metal plate capacitor, and the like

When output driver400and associated receiver circuitry is operating correctly, current, IOUT, conducted by current path480provided by transistors402,404, and405is J×IrO, where current IrO is adjusted by the current level switch. However, if there is a fault associated with output terminal441, current IOUTcan be different than the desired value, J×IrO. For example, if an open circuit fault isolates output terminal441from the external pullup current source, e.g. if bond wire444is broken, Rload, current IOUTwill be zero. Other faults can result in current IOUTbeing less than the desired value, J×IrO. Fault detection is described below in greater detail.

Feedback current mirror483is configured to monitor the actual current being conducted in current path480. Feedback current mirror483includes transistor404and transistor403, which together provide another current mirror. The control electrode of transistor404is connected to the control electrode of transistor403, and this circuit node is labeled Vf. In particular, transistor403is configured to mirror a current conducted at transistor404. In an embodiment, this feedback current mirror is configured to provide a current gain of 1/J. For example, the effective width of transistor404can be ten times the effective width of transistor403. The effective width of transistor404can be the same as the effective width of transistor402, and the effective width of transistor403can be the same as the effective width of transistor401. Feedback current mirror483measures the actual current conducted at current path480and mirrors it back, by a current gain of 1/J, to current comparator486. It is desired that feedback current mirror follow output current IOUTquickly, so parasitic gate capacitance423should be small. It is further desired that transistor403does not limit current IrO significantly. Resistors421and422are selected to provide a voltage drop of approximately one hundred millivolts. Accordingly, a resistance provided by resistor421is approximately one tenth the resistance provided by resistor422.

Current comparator486is configured to compare the actual current IOUTconducted at current path480with the intended value, IrO×J. Current comparator486includes transistors416,417,437,437,406,407,408, and409. Current comparator486includes two controllable reference currents, IrM and IrK, which define current thresholds. Current comparator486is configured to compare current IOUT/J (current IOUTdivided by current gain J) with each reference current. Transistors416and417can represent two or more current mirror transistors that mirror reference current Ir. Transistors436and437can represent two or more switch transistors that are controlled to select corresponding current mirror transistors so as to provide the desired values of references currents IrM and IrK. In an embodiment, transistor416,417,436, and437provide a current-based digital-to-analog converter that is similar to current level switch485.

Control electrodes of transistors406and407are connected to node Vr and thus implement current mirrors, which mirror current IrO conducted by transistor401. The effective width of transistors406and407can be the same as the effective width of transistor401. Control electrodes of transistors408and409are connected to node Vf and thus implement current mirrors, which mirror current IOUTconducted by transistor404. The effective width of transistors408and409can be the same as the effective width of transistor403, and the impedance of resistor425and resistor426can be the same as the impedance of resistor422.

During operation, a voltage at node A will correspond to a logic-low state if output current IOUT/J is greater than current IrM, and node B will correspond to a logic-low state if current IOUT/J is greater than current IrK. Inverters452and451invert the logic state at nodes A and B, respectively. Accordingly, output M+ will be asserted with a logic high level if output current IOUT/J is greater than current IrM, and output K+ will be asserted with a logic high level if output current IOUT/J is greater than current IrK. For example, a current threshold represented by current IrM can be selected to correspond to a value equal to ten percent of a maximum value of output current IOUT/J, and a current threshold represented by current IrK can be selected to correspond to a value equal to ninety percent of a maximum value of output current IOUT/J.

FIG. 5is a schematic diagram illustrating fault detection logic500according to a specific embodiment of the present disclosure. Fault detection logic500includes logic gates508,510,512, and error logic516. Operation of fault detection logic500is similar to operation of portions of feedback logic ofFIG. 2. Fault detection logic500receives signals K+ and M+ from current comparator486ofFIG. 4and signal BI, and generates signal ERROR. Logic gates508,510, and512each have inputs to receive signals K+ and M+, and outputs to generate signals H, XOR, and L, respectively. Error logic516includes a first input to receive signal H, a second input to receive signal XOR, a third input to receive signal L, a fourth input to receive signal BI, and an output to provide a signal, ERROR. Signal BI represents an intended current sink value, as encoded by signal Sw_H, Sw_L, and Sw_S.

During operation, signal H is asserted if both signals K+ and M+ are asserted, signal XOR is asserted only if signals K+ and M+ represent opposite logic states, and signal L is asserted if either signals K+ or M+ are asserted. In an embodiment, error logic516can determine whether the transition time of signal IOUT/J as indicated by signal XOR is less than a first predetermined value or greater than a second predetermined value. Fault detection logic500is configured to detect a fault associated with output terminal441. For example, if output terminal is shorted to ground reference voltage Vss, or if there is an open circuit fault at output terminal441, output current IOUTwill be zero, and signals H, L, and XOR will each be at a logic-low level. If output driver circuit400is configured to sink a high current level, but a fault causes output current IOUT/J to be less than a corresponding high current level represented by current IrK, signal H will not be asserted. If output terminal is shorted to external voltage Vext, the duration of an assertion of signal XOR will be less than expected, because the time constant associated with capacitor442and resistor443will be nearly zero.

FIG. 6is a timing diagram600illustrating the operation of the output driver circuit400ofFIG. 4and fault detection logic500ofFIG. 5according to a specific embodiment of the present disclosure. Timing diagram600includes a horizontal axis representing time and a vertical axis representing current. Timing diagram600further includes waveform602representing current IOUT/J; threshold current IrM,604; threshold current IrK,606; signal H,610; signal XOR,612; signal L,614; and time references650,652,654, and656. Waveform602illustrates a transition of current IOUT/J from a current level representing logic low level, such as IrL, to a current representing a logic high level, such as IrH. Waveform602begins transitioning at time reference650and completes transitioning at time reference656. At time reference652, current IOUT/J has reached threshold current IrM,604; and at time reference654, current IOUT/J has reached threshold current IrK,606. As described above, signal H is asserted by AND gate508at time reference654when current IOUT/J exceeds threshold current IrK. Signal XOR is asserted at time reference652when current IOUT/J exceeds threshold current IrM, and is de-asserted when the current IOUT/J further rises and exceeds threshold current IrK. Signal L is asserted when current IOUT/J exceeds threshold current IrM. One of skill will appreciate that while waveform602is illustrated as a piece-wise-linear form, waveform602is likely exponential in shape as would be expected when driving a load having resistance and capacitance characteristics. Furthermore, while output driver400and signals VOUTand IOUTare described in the context of a digital logic interface, one of skill will appreciated that fault detection logic500and the concepts described above can be applied to an analog current interface.

FIG. 7is a schematic diagram illustrating an output driver circuit700to detect a fault condition at a device interface that operates in a current domain, according to another aspect of the present disclosure. Output driver circuit700is substantially similar to output driver circuit400with one exception. Each reference number, 7xx, ofFIG. 7corresponds to the similarly numbered references, 4xx, ofFIG. 4. For example, capacitor442ofFIG. 4corresponds to capacitor742ofFIG. 7. Furthermore, the operation of the functional blocks of output driver circuit700is substantially the same as the operation of the functional blocks of output driver circuit400. Accordingly, reference numbers ofFIG. 7that do not appear below correspond to elements ofFIG. 4that function substantially the same as described above with reference toFIG. 4. The difference between circuit700and circuit400is the configuration of the current sink mirror782and feedback current mirror783. Specifically, the series connected order of transistors704and702of a current path780are switched relative to the series connected order of transistors402and404of current path480ofFIG. 4. The series connected order of transistors703and701are similarly reversed relative to transistor401and403. Output driver circuit400uses a Wilson current mirror that generates a voltage drop of greater than two threshold voltages of transistor401and transistor403. Accordingly, output driver circuit400requires a supply voltage that is greater than approximately 1.8 v for some integrated circuit process technologies. Instead, output driver circuit700uses a cascode current mirror that generates a voltage drop that is less than that of circuit400. Therefore, circuit700can operate using a supply voltage that is lower than that required by circuit400, for a particular process technology.

Current sink mirror782includes transistor701and transistor702. The control electrode of transistor701is connected to the control electrode of transistor702, and this circuit node is labeled Vr. During operation, current IrO selected by current level switch785and conducted by transistor701, is mirrored by transistor702. In an embodiment, the effective width of transistor702is greater than the effective width of transistor701so that the mirrored current conducted by transistor702is an integer or non-integer multiple of current IrO. The ratio of the effective width of transistor702to the effective width of transistor701, and accordingly the current gain provided by current sink mirror782, will be referred to herein as current gain J. In other words, transistor702is configured to conduct a current equal to J×IrO. Capacitor724is a fabricated capacitor to stabilize operation of current sink mirror782. For example, capacitor724can be a gate-oxide capacitor, a metal plate capacitor, and the like

Feedback current mirror783is configured to monitor the actual current being conducted in current path780. Feedback current mirror783includes transistor704and transistor703, which together provide another current mirror. The control electrode of transistor704is connected to the control electrode of transistor703, and this circuit node is labeled Vf. In particular, transistor703is configured to mirror a current conducted at transistor704. Transistor703is in a cascode configuration. In an embodiment, this feedback current mirror is configured to provide a current gain of 1/J. For example, the effective width of transistor704can be J times the effective width of transistors706and707of current comparator786. The effective width of transistor704can be the same as the effective width of transistor702, and the effective width of transistor703can be the same as the effective width of transistor701. It is desired that feedback current mirror follow output current IOUTquickly, so parasitic gate capacitance723should be small. It is further desired that transistor703not limit current IrO significantly. Resistors721and722are selected to provide a voltage drop of approximately one hundred millivolts. Accordingly, a resistance provided by resistor721should be approximately one tenth the resistance provided by resistor722.

In a first aspect, a device includes an output terminal; a driver including an input and an output, the driver configured to receive at the input a first signal representing first information and to provide at the output a second signal representing the first information, the output coupled to the output terminal; and a feedback circuit to receive a third signal from the output terminal; identify a fault at the output terminal based on the third signal and the first signal; and generate an error indicator in response to identifying the fault. In an embodiment of the first aspect, the feedback circuit is further to store the error indicator at a latch, the latch included at a scan path, the scan path to communicate the error indicator to test logic. In another embodiment of the first aspect, the feedback circuit is further to receive the first signal; compare a logic state of the first signal with a logic state of the third signal; and identify the fault based on the comparison. In yet another embodiment of the first aspect, the feedback circuit further includes a first comparator to generate a first indicator in response to determining that a voltage level of the third signal exceeds a first threshold voltage; and a second comparator to generate a second indicator in response to determining that the voltage level of the third signal exceeds a second threshold voltage.

In an embodiment of the first aspect, the feedback circuit is further to determine a first transition time of the third signal based on the first indicator and the second indicator; and identify the fault based on the first transition time. In another embodiment of the first aspect, the feedback circuit is further to identify the fault in response to determining that the first transition time is less than a first predetermined value, the fault corresponding to a load impedance at the output terminal that is greater than an expected load impedance. In yet another embodiment of the first aspect, the feedback circuit is further to identify the fault in response to determining that the first transition time is greater than a second predetermined value, the fault corresponding to a load impedance at the output terminal that is less than an expected load impedance. In still another embodiment of the first aspect, the feedback circuit is further to receive the first signal; and identify the fault in response to determining that a propagation delay of the third signal relative to the first signal exceeds a predetermined propagation value. In another embodiment of the first aspect, the fault is selected from a group consisting of a short circuit between the output terminal and an external reference voltage; a short circuit between the output terminal and an external logic signal; a malfunction of an electrostatic discharge protection circuit; and an open circuit between the driver and a receiver external to the device. In still another embodiment of the first aspect, the feedback circuit is further to identify the fault while the device is functioning in a normal operating mode, the normal operating exclusive of a test mode.

In a second aspect, a method includes receiving a first signal at an input of a device driver included at an electronic device, the first signal representing first information; providing a second signal representing the first information at an output of the device driver, the output of the device driver, under normal operating conditions, coupled to an output terminal of the electronic device; receiving, at feedback circuitry of the electronic device, a third signal at the output terminal; and identifying, at the feedback circuitry, a fault at the output terminal based on the third signal and the first signal. In an embodiment of the second aspect, the method includes comparing, at the feedback circuitry, the first signal to the third signal; and identifying a fault at the output terminal based on the third signal. In another embodiment of the second aspect, the method includes generating, at the feedback circuitry, an error indicator in response to identifying the fault; and storing the error indicator a latch, the latch included at a scan path, the scan path for communicating the error indicator to test circuitry. In yet another embodiment of the second aspect, the method includes generating a first indicator in response to determining at a first comparator of the feedback circuitry that a voltage level of the third signal exceeds a first threshold voltage; and generating a second indicator in response to determining at a second comparator of the feedback circuitry that a voltage level of the third signal exceeds a second threshold voltage.

In still another embodiment of the second aspect, the method includes determining a first transition time of the third signal based on the first indicator and the second indicator; and identifying the fault based on the first transition time. In still another embodiment of the second aspect, the method includes identifying the fault in response to determining that the first transition time is less than a first predetermined value, the fault corresponding to a load impedance at the output terminal that is greater than an expected load impedance. In another embodiment of the second aspect, the method includes identifying the fault in response to determining that the first transition time is greater than a second predetermined value, the fault corresponding to a load impedance at the output terminal that is less than an expected load impedance. In yet another embodiment of the second aspect, the method includes receiving, at the feedback circuitry, the first signal; and identifying the fault in response to determining that a propagation delay of the third signal relative to the first signal exceeds a predetermined propagation value. In still another embodiment of the second aspect, the method includes identifying the fault while the electronic device is functioning in a normal operating mode that is exclusive of test operating mode.

In a third aspect, an automotive control system includes an electronic device having an output terminal; a driver at the electronic device, the driver including an input and an output, the driver configured to receive at the input a first signal representing first information and to provide at the output a second signal representing the first information, the output coupled to the output terminal; and a feedback circuit at the first electronic device. The feedback circuit receives a third signal from the output terminal; and identifies a fault at the output terminal based on the third signal and the first signal.

The preceding description in combination with the Figures was provided to assist in understanding the teachings disclosed herein. The discussion focused on specific implementations and embodiments of the teachings. This focus was provided to assist in describing the teachings, and should not be interpreted as a limitation on the scope or applicability of the teachings. However, other teachings can certainly be used in this application. The teachings can also be used in other applications, and with several different types of architectures.

Other embodiments, uses, and advantages of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. The specification and drawings should be considered exemplary only, and the scope of the disclosure is accordingly intended to be limited only by the following claims and equivalents thereof.

Note that not all of the activities or elements described above in the general description are required, that a portion of a specific activity or device may not be required, and that one or more further activities may be performed, or elements included, in addition to those described. Still further, the order in which activities are listed is not necessarily the order in which they are performed.