Active Inductor Peaking Buffer with Output Common Mode Control

An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a current-mode logic differential amplifier and a common mode control circuit coupled to the current-mode logic differential amplifier. The common mode control circuit includes a replica circuit replicating a portion of the current-mode logic differential amplifier and a comparator circuit. The comparator circuit is configured to compare a voltage at a sense node in the replica circuit and a reference voltage and to provide to the current-mode logic differential amplifier and, via a feedback loop, to the replica circuit, an output that drives the sense node toward the reference voltage.

BACKGROUND OF THE INVENTION

This disclosure relates to buffer circuits and, in particular, to an active inductor peaking buffer circuit with output common mode control.

Buffer circuits can be configured to provide a target gain at a desired bandwidth. The bandwidth can be determined from an operating frequency range over which the gain of the buffer circuit is within a desired range. One common type of buffer circuit is a current mode logic (CML) buffer that can be utilized to communicate high-frequency signals, for example, in high-performance computing systems, wireless communication systems, serial data protocols, and other high-speed signaling environments.

In current mode logic, the proper operation of circuits downstream of the buffer circuit can be sensitive to the buffer circuit's output signal amplitude and the common mode voltage of the buffer circuit. In integrated circuitry, the buffer circuit can be sensitive to process, voltage, and/or temperature (PVT) variations, potentially rendering satisfaction of output amplitude and common mode voltage specifications of the buffer circuit difficult. Consequently, the present disclosure appreciates that it would be useful and desirable to provide a buffer circuit having a tightly controlled common mode output voltage regardless of expected PVT variations.

BRIEF SUMMARY

An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a current-mode logic differential amplifier and a common mode control circuit coupled to the current-mode logic differential amplifier. The common mode control circuit includes a replica circuit replicating a portion of the current-mode logic differential amplifier and a comparator circuit. The comparator circuit is configured to compare a voltage at a sense node in the replica circuit and a reference voltage and to provide to the current-mode logic differential amplifier and, via a feedback loop, to the replica circuit, an output that drives the sense node toward the reference voltage.

DETAILED DESCRIPTION

With reference to the figures and with particular reference toFIG.1, there is illustrated a high-level block diagram of an exemplary integrated circuit100including a buffer circuit in accordance with one or more embodiments. In this example, integrated circuit100can be, for example, a processor, a programmable logic device, a digital signal processor, a memory controller, a bus or network interface, etc. Integrated circuit100includes a functional logic circuit102configured to perform one or more functions, such as data processing, data storage, and/or data communication. In addition, integrated circuit100includes one or more lane receiver circuits104and one or more lane transmitter circuits106that respectively receive data from and transmit data to a communication channel108, such as an interconnect or network.

In the example ofFIG.1, lane receiver104includes a sampling circuit110that samples data on communication channel108based on clock signals112provided by a clocking circuit120. Clocking circuit120receives a clock signal from clock distribution network108at a clock input114. The clock signal present at clock input114is received and buffered by buffer circuit130, an embodiment of which is described in greater detail below with reference toFIG.2. Buffer circuit130in turn provides a buffered CML-level clock signal to downstream current mode circuitry including a frequency divider132, a phase rotator134(controlled by clock and data recovery (CDR) signals136supplied by sampling circuit110), a multi-phase generator138, and amplifiers140. Amplifiers140convert eight clock signals of various phases output by multi-phase generator138into eight full-rail complementary metal-oxide-semiconductor (CMOS) clock signals112provided to sampling circuit110.

AlthoughFIG.1illustrates one exemplary environment in which a buffer circuit130may be employed, those skilled in the art will appreciate that such use is merely exemplary and that buffer circuit130is not restricted in use to current mode clocking circuits. Rather, buffer circuit130can be employed in a wide variety of integrated circuits in which common mode control is useful and/or desirable.

Referring now toFIG.2, there is depicted a more detailed block diagram of an exemplary embodiment of a buffer circuit200with common mode control that can be utilized, for example, to implement buffer circuit130in integrated circuit100ofFIG.1. Buffer circuit200includes one or more current-mode logic differential amplifiers (or drivers)202, each of which is configured as an active inductor peaking buffer and each of which is coupled to a common mode control circuit220at control node240. In embodiments in which buffer circuit200includes two or more amplifiers202, the amplifiers can be coupled together in parallel. By controlling the voltage at common mode control node240, common mode control circuit220ensures that the common mode voltage at the differential output of each amplifier202is tightly controlled within a desired range despite any process, voltage, and/or temperature (PVT) effects.

Each amplifier202has a mirrored differential architecture schematically represented by a positive “half” or “side” denoted by component names including the subscript “P” and a negative “half” or “side” denoted by component names including the subscript “N.” In the depicted embodiment, amplifier202includes a differential input including a positive input (INP) node201aand a negative input (INN) node201b. Positive input node201ais connected to the gate of NMOS input transistor MP212a, and negative input node201bis connected to the gate of NMOS input transistor MN212b. The drain of each of input transistors212a,212bis coupled to a respective one of negative output (OUTN) node211aand positive output (OUTP) node211b. The source of each of input transistors212a,212bis coupled to a respective constant current source216a,216b, which is in turn coupled to a lower voltage reference (e.g., ground). Each of constant current sources216a,216bcan be implemented, for example, with a properly biased current source transistor, in order to provide a tail current that provides input-independent biasing for amplifier202. The sources of input transistors212a,212bare additionally coupled together by a capacitive source degeneration capacitor CDEG214, which is sized to cause amplifier202to amplify a higher frequency portion of the differential input while rejecting the lower frequency (and DC) portion of the differential input.

Amplifier202additionally includes inductor transistors (or active inductors) MINDP206aand MINDN206b, each of which has a drain coupled to a respective one of output nodes211a,211band a source coupled to an upper voltage reference (VDD). As is known in the art, inclusion of these peaking inductor transistors MINDP206aand MINDN206bincreases the bandwidth (reduces the propagation delay) of amplifier202. The drain of each of inductor transistors MINDP206aand MINDN206b(and thus a respective one of output nodes211a,211b) is respectively coupled to the gate205b,205aof the other of inductor transistors MINDN206bor MINDP206a. In the embodiment ofFIG.2, this coupling is implemented via respective transistors (e.g., PMOS transistors), which are configured, by having their source and drain tied together, to operate as capacitors CINDP210aand CINDN210b. The gate205a,205band drain of each of inductor transistors MINDP206aand MINDN206bis also coupled by a variable resistor RINDP208aor RINDN208b. The gate205a,205bof each of inductor transistors MINDP206aand MINDN206bis provided an input current by a respective transconductance circuit (Gm)204aor204b, which generates a current having a magnitude dependent upon the voltage present at common mode control node240.

Still referring toFIG.2, common mode control circuit220includes a replica circuit250including components selected and coupled together to substantially replicate one “half” or “side” of the differential architecture of amplifier202. Thus, for example, replica circuit250includes a tail current source236corresponding to constant current source216b, a NMOS input transistor MN_REPcorresponding to input transistor MN212b, a sense node231corresponding to positive output (OUTP) node211b, an inductor transistor (active inductor) MIND_REP226corresponding to transistor MINDN206b, a gate-drain resistance RIND_REP228corresponding to RINDN228b, and a Gmblock224corresponding to Gmblock204b. In this example, replica circuit250omits a capacitor corresponding to capacitor CINDN210b. Input transistor MN_REP232is biased to an active state by connection of its gate to upper voltage reference VDD. The sizes of the components of replica circuit250may not be identical to those of the corresponding components of amplifier202, but can instead be scaled to any desired size.

Common mode control circuit220additionally includes a comparator circuit, such as an operational amplifier (op amp)222, coupled to replica circuit250in a feedback configuration. In this example, op amp222has a first input coupled to a reference voltage (VREF) generator221and a second input coupled to sense node231of replica circuit250. The output of op amp222is connected to common mode control node240, and common mode control node240is further coupled by a feedback loop225to the input of the Gmblock224within replica circuit250. Common mode control circuit220also includes a capacitor232coupled between common mode control node240and a clean reference (ground).

In operation, VREFgenerator221provides a constant reference voltage to op amp222, which sets the voltage of common mode control node240based on the closed loop gain of op amp222and the difference between the constant reference voltage and the voltage present at the sense node231modeling the corresponding amplifier output node211b. The output voltage of op amp222present on common mode control node240is converted into a corresponding current by Gmblock224. The current produced by Gmblock224is injected into gate node225of inductor transistor226and develops an I×R voltage drop across the gate-drain path due to the associated resistance RIND_REP228. As a result, the common mode voltage of sense node231is driven to the reference voltage. The voltage of common mode control node240is stabilized by capacitor232, which has the effect of passing only the DC component of the control signal on common mode control node240to amplifier(s)202. Because replica circuit250substantially replicates the design and response of amplifier(s)202, op amp222setting the voltage of common mode control node240causes Gmblocks204a,204bof amplifier202to likewise inject the appropriate current into gates205a,205bto drive the common mode voltage present at output nodes211a,211bto the reference common mode voltage.

It should be noted that common mode control circuit220can, in some embodiments, be utilized to control the common mode output voltage of multiple amplifiers202. In such cases, variable resistance RIND_REP228of inductor transistor226is preferably controlled to account for the aggregate resistance of the active inductors of amplifiers202and the targeted operating frequency of amplifiers202.

Exemplary buffer circuit200provides a number of advantages. First, the disclosed buffer circuit200is capable of implementing tight control of the common mode voltage at the differential output nodes211a,211bof amplifier(s)202, ensuring that downstream circuits receive a signal having the full voltage swing of amplifier(s)202. Second, the common mode voltage on differential output nodes211a,211bis independent of the gate-source voltage (VGS) of the transistors of amplifier202. Third, buffer circuit200has a fast response time and is suitable for use in high frequency (e.g., multiple GHz) applications. One reason that buffer circuit200has such a fast response time is that common mode control circuit220does not load input nodes201a,201bor output nodes211a,211b. Instead, common mode control circuit220only loads low frequency gate nodes205a,205b. Fourth, the design of buffer circuit200employs few components and therefore has reduced complexity, low power dissipation, and requires only a small chip area. As a result, the components of common mode control circuit220can be fabricated with larger device sizes to promote tighter control of the common mode output voltage and reduce the impact of process variability on the effectiveness of the feedback control. Fifth, a single common mode control circuit220can provide common mode control for multiple amplifiers202, providing further savings in chip area, power, and complexity. Sixth, amplifier(s)202can operate without hindrance even if common mode control circuit220is selectively disabled (e.g., to reduce power dissipation).

Design flow300may vary depending on the type of representation being designed. For example, a design flow300for building an application specific IC (ASIC) may differ from a design flow300for designing a standard component or from a design flow300for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.

FIG.3illustrates multiple such design structures including an input design structure320that is preferably processed by a design process310. Design structure320may be a logical simulation design structure generated and processed by design process310to produce a logically equivalent functional representation of a hardware device. Design structure320may also or alternatively comprise data and/or program instructions that when processed by design process310, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure320may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure320may be accessed and processed by one or more hardware and/or software modules within design process310to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown herein. As such, design structure320may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

Design process310preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown herein to generate a netlist380which may contain design structures such as design structure320. Netlist380may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist380may be synthesized using an iterative process in which netlist380is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist380may be recorded on a machine-readable storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, or buffer space.

Design process310may include hardware and software modules for processing a variety of input data structure types including netlist380. Such data structure types may reside, for example, within library elements330and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 10 nm, 20 nm, 30 nm, etc.). The data structure types may further include design specifications340, characterization data350, verification data360, design rules370, and test data files385which may include input test patterns, output test results, and other testing information. Design process310may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process310without deviating from the scope and spirit of the invention. Design process310may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.

As has been described, in at least one embodiment, an integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a current-mode logic differential amplifier and a common mode control circuit coupled to the current-mode logic differential amplifier. The common mode control circuit includes a replica circuit replicating a portion of the current-mode logic differential amplifier and a comparator circuit. The comparator circuit is configured to compare a voltage at a sense node in the replica circuit and a reference voltage and to provide to the current-mode logic differential amplifier and, via a feedback loop, to the replica circuit, an output that drives the sense node toward the reference voltage.

While various embodiments have been particularly shown and described, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims and these alternate implementations all fall within the scope of the appended claims. For example, although aspects have been described with respect to a computer system executing program code that directs the functions of the present invention, it should be understood that present invention may alternatively be implemented as a program product including a computer-readable storage device storing program code that can be processed by a processor of a data processing system to cause the data processing system to perform the described functions. The computer-readable storage device can include volatile or non-volatile memory, an optical or magnetic disk, or the like, but excludes non-statutory subject matter, such as propagating signals per se, transmission media per se, and forms of energy per se.

As an example, the program product may include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, or otherwise functionally equivalent representation (including a simulation model) of hardware components, circuits, devices, or systems disclosed herein. Such data and/or instructions may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++. Furthermore, the data and/or instructions may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures).