Image reading apparatus

An image reading apparatus comprises a first reading unit configured to output an analog signal by reading an original, a second reading unit different from the first reading unit, a conversion unit configured to convert analog signals outputted from the first reading unit and the second reading unit to digital signals, a wire connection control unit configured to control wire connection between the first reading unit and the second reading unit, and the conversion unit, and an output control unit configured to control an output of an analog signal from the first reading unit.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an image reading apparatus for reading an image of an original.

Description of the Related Art

In recent years, there has been a demand for an increase in reading speed in an image reading apparatus. Japanese Patent Laid-Open No. 2017-147513 discloses a configuration for increasing the speed at the time of single-sided reading by controlling the number of output channels for image sensor ICs in an image reading apparatus that supports simultaneous double-sided reading.

SUMMARY OF THE INVENTION

The present invention provides, with regard to image reading apparatuses capable of executing a plurality of reading modes, an image reading apparatus for improving reading efficiency with a simple configuration.

The present invention in one aspect provides an image reading apparatus comprising: a first reading unit configured to output an analog signal by reading an original; a second reading unit different from the first reading unit; a conversion unit configured to convert analog signals outputted from the first reading unit and the second reading unit to digital signals; a wire connection control unit configured to control a wire connection between the first reading unit and the second reading unit and the conversion unit; an output control unit configured to control an output of an analog signal from the first reading unit, wherein, in a first reading mode, the wire connection control unit is configured to control the wire connection such that analog signals outputted from a plurality of output channels of the first reading unit are respectively inputted to a plurality of input channels of the conversion unit, in a second reading mode different from the first reading mode, the wire connection control unit is configured to control the wire connection such that the analog signals outputted from the plurality of output channels of the first reading unit and analog signals outputted from a plurality of output channels of the second reading unit are inputted to the plurality of input channels of the conversion unit, and in the second reading mode, the output control unit is configured to control an output of analog signals such that a timing of an output of an analog signal from each of the plurality of output channels of the first reading unit to be inputted to one input channel of the conversion unit is shifted.

According to the present invention, it is possible to improve reading efficiency with a simple configuration in an image reading apparatus capable of executing a plurality of reading modes.

DESCRIPTION OF THE EMBODIMENTS

In Japanese Patent Laid-Open No. 2017-147513, it is necessary to provide image sensor ICs with a function for controlling the number of output channels for analog image data.

According to one aspect of the present invention, it is possible to improve reading efficiency with a simple configuration in an image reading apparatus capable of executing a plurality of reading modes.

First Embodiment

[Overall Configuration of Image Reading Apparatus]

FIG.1is a lateral cross-sectional view of an image reading apparatus100in the present embodiment. The image reading apparatus100will be described to have a configuration capable of simultaneously reading both sides of an original, which is a reading target. Incidentally, to be capable of simultaneous reading is not limited to cases where reading timings are strictly simultaneous (parallel) in the image reading apparatus100. That is, it includes cases where in the image reading apparatus100, it is possible to perform processing for reading the front side of an original, which is a reading target, and processing for reading the back side, which is on the back surface, of the original in a single conveyance of the original.

As illustrated inFIG.1, the image reading apparatus100reads originals using contact image sensors (hereinafter, referred to as CISs), and includes a front side CIS201, a back side CIS202, and conveyance rollers220to225for conveying originals. The front side CIS201is a device for reading an image recorded on the front side of originals, and the back side CIS202is a device for reading an image recorded on the back side of originals. When performing double-sided reading of originals, the image reading apparatus100conveys an original, which is a reading target, in the direction of arrows A by the conveyance rollers220to225. When the conveyed original reaches the reading position of the front side CIS201, the front side CIS201reads an image. For example, emission light from an LED, which is a light source for illuminating originals, provided inside the front side CIS201is emitted onto the original, and by the front side CIS201reading the reflected light thereof, analog image data (hereinafter, also referred to as “analog signal”) is generated. When the original reaches the reading position of the back side CIS202, the back side CIS202reads an image. For example, emission light from an LED, which is a light source for illuminating originals, provided inside the back side CIS202is emitted onto the original, and by the back side CIS202reading the reflected light thereof, analog image data is generated.

The front side CIS201and the back side CIS202have a read width corresponding to the width of originals. The direction of the read width is the direction perpendicular to an arrow A. Hereinafter, this perpendicular direction is referred to as a main scanning direction, and the direction of conveyance originals indicated by the arrow A is referred to as a sub-scanning direction. In the present embodiment, by arranging the front side CIS201and the back side CIS202to face each other and conveying an original in the direction of the arrows A, images on both sides of the original can be read in parallel. Note that although description is given assuming that the front side and the back side of an original are read simultaneously, the positions of the front side CIS201and the back side CIS202do not need to be perfectly opposite to each other. That is, it is only necessary that the read surface of one CIS is arranged so as to partially face the read surface of the other CIS. Even with such a configuration, it is possible to perform the reading processing of the front side and the reading processing of the back side in parallel in one conveyance path. Further, each of the front side CIS201and the back side CIS202is provided with a blue LED, a red LED, and a green LED in order to read color images.

Light emitted by LEDs provided in the front side CIS201is reflected by an original, and the reflected light is imaged via a lens (not illustrated) onto the image sensor that the front side CIS201has. Then, the imaged reflected light is photoelectrically converted, and analog image data is generated. Meanwhile, light emitted by LEDs provided in the back side CIS202is reflected by an original, and the reflected light is imaged via a lens (not illustrated) onto the image sensor that the back side CIS202has. Then, the imaged reflected light is photoelectrically converted, and analog image data is generated.

FIG.2is a view illustrating an example of an internal configuration of a control circuit of the image reading apparatus100. InFIG.2, an example in which the image reading apparatus100is configured in a multi-function peripheral (hereinafter, referred to as MFP) having a read function and a print function will be described. An MFP110has a printhead control circuit502, a motor control circuit509, a sensor508, an ASIC510, a ROM512, a DRAM513, an operation unit104, and an I/F519, and each is connected so as to be able communicate with each other via a system bus. The ASIC510includes an image processing unit300, a timing signal generation unit301, an LED control unit304, and a CPU511, and performs control of the entire MFP110, such as image reading and printing.

The CPU511is a central processing unit in the form of a microprocessor (microcomputer), and controls the operation of the entire MFP110by executing programs and starting up hardware. The ROM512is a non-volatile storage region and stores programs that support processing procedures executed by the CPU511. The DRAM513is a volatile storage region that is used as a work area for the CPU511or temporarily stores parameters and image data for the CPU511to perform processing procedures.

The operation unit104can accept various operations of the user, and includes, for example, a hard key, a display unit for presenting (notifying) various information to the user, and the like. The operation unit104has an LCD105as a display unit. The display unit may be configured as a touch panel, for example. Further, configuration may be taken such that the operation unit104includes a voice generator or the like and is capable of outputting sound (buzzer, voice, etc.) based on sound information. The I/F519is an interface for communicating with an external apparatus520. For example, a personal computer (PC) as the external apparatus520is connected via the I/F519with the MFP110to be able to perform communication. The external apparatus520is not limited to a PC, and may be another form of apparatus such as a portable terminal. For example, it is possible to perform input/output of image data between the MFP110and the external apparatus520via the I/F519.

A printhead402and a motor506are controlled by the ASIC510via the printhead control circuit502and the motor control circuit509, respectively. The printhead402has a mechanism for discharging ink droplets from nozzles. Further, the motor506includes a motor for driving rollers for conveying an original for reading and rollers for conveying sheets for printing.

The MFP110has, as a configuration of a read function, a front side CIS308(hereinafter, simply referred to as CIS308), a back side CIS309(hereinafter, simply referred to as CIS309), an analog front-end310(AFE310), and an analog front-end311(AFE311). The CIS308corresponds to the front side CIS201ofFIG.1, and the CIS309corresponds to the back side CIS202ofFIG.1. Analog image data outputted from the CIS308and the CIS309is inputted to the AFE310and the AFE311via a wire connection control unit321. The wire connection control unit321is configured to include switching gates315to319. Each switching gate is configured to select either one of input signals inputted from the two input terminals as an output target, and output it from one output terminal.

Each of the AFE310and the AFE311has two input channels. The AFE310and the AFE311are connected to the ASIC510. The CIS308has four output channels for analog image data, and the output timing of analog image data can be switched by an output control unit320. Details of the output timing will be described later. The CIS309has two output channel for analog image data. By the CPU511writing setting values to a register (not illustrated), the timing signal generation unit301supplies the CIS308and the CIS309with a horizontal synchronization signal SH and a clock signal required to drive each of these. Furthermore, the timing signal generation unit301supplies the output control unit320and the wire connection control unit321with a MODE selection signal.

MODE selection signals are generated by the CPU511writing setting values in the register (not illustrated) in accordance with a single-sided reading mode or a double-sided reading mode that can be selected by the user via the operation unit104or the external apparatus520. For example, for the single-sided reading mode, by the CPU511writing 1 in the register (not illustrated), a High level signal is outputted as a MODE selection signal. For the double-sided reading mode, by the CPU511writing 0 in the register (not illustrated), a Low level signal is outputted as a MODE selection signal. In the present embodiment, the output timing of analog image data from the CIS308is switched by the output control unit320in accordance with the logic state of the MODE selection signal, that is, the reading mode. Furthermore, the input channels for analog image data to be inputted to the AFE310and the AFE311are switched by the wire connection control unit321.

The LED control unit304performs lighting control of the LEDs (not illustrated) with which the CISs308and309are provided. Lighting control is performed by PWM control synchronized with the horizontal synchronization signal SH. Details will be described later for the CIS308, the CIS309, the output control unit320, the wire connection control unit321, the AFE310, and the AFE311. Note that although in the present embodiment, two AFEs having two input channels are used, the present invention may be configured with one AFE having four input channels.

FIG.3is a view illustrating a configuration of an image sensor IC312, andFIG.4is a view illustrating a timing chart of image sensor ICs312.FIG.5is a view illustrating a configuration of connection of image sensor ICs for selectively switching the output timing of analog image data in a substrate of the CIS308. As illustrated inFIG.5, 12 image sensor ICs312(hereinafter, referred to as Chip1to Chip12) are arranged on a substrate so that light reflected from an A4-sized (about 21 cm) reading target (original) can be read at once. The read and generated analog image data is outputted from four output channels (Vout1to Vout4). As illustrated inFIG.5, a plurality of image sensor ICs312are grouped so as to correspond to the respective output channels.

Description will be given for the configuration of the image sensor IC312ofFIG.3. A photodiode330has a plurality of photoelectric conversion elements arranged in a linear pattern, and photoelectrically converts received light. An accumulation unit331is arranged in parallel with the photodiode330, and has a plurality of charge accumulation elements for accumulating signal charge, and a memory (not illustrated) for holding a voltage value obtained by voltage conversion of the accumulated charge. When the horizontal synchronization signal SH has risen, the electric charge of all the lines accumulated in the accumulation unit331is transferred to a switching gate332, the accumulation unit331is reset, and light receiving in the photodiode330and charge accumulation in the accumulation unit331are started. Incidentally, the accumulation of charge is performed until the horizontal synchronization signal SH of the next line is inputted. The switching gate332holds the electric charge accumulated in the accumulation unit331, and after a start signal (hereinafter, st signal) is inputted to an st terminal, the voltage value held in the memory is sequentially transferred one pixel at a time to an output circuit (Amp)333as analog image data. A counter334is caused to count up in synchronization with a pixel clock CLK. When all the pixels are outputted, a pulse signal is outputted from a next terminal as an output termination signal (hereinafter, referred to as next signal) for notifying the subsequent image sensor IC of the end of output. For example, when the next signal of the Chip1is inputted to the st terminal of Chip2, the output of analog image data of Chip2is started. Detailed timing will be described later.

Description will be given for an operation timing chart of the image sensor ICs312ofFIG.4. Description will be given for the image sensor ICs312using the operations of the Chip1and the Chip2adjacent to each other illustrated inFIG.5as an example. When the horizontal synchronization signal SH generated by the timing signal generation unit301is inputted, the accumulation of charge is started in the Chip1and the Chip2as described above. Then, the count up of the counter334is started in synchronization with the pixel clock CLK generated by the timing signal generation unit301. In the image sensor ICs312, if the count value is 100 or more, the output of analog image data is started when an st signal is inputted. That is, in the Chip1, when the count value is 100, a High state is entered, and the output of analog image data is started from out. That is, in the Chip1, the output of analog image data is started when the count value reaches 100. For example, when reading at a resolution of 300 dpi, 216 pixels that the image sensor IC312has are sequentially outputted over count values=101 to 316. Then, when the last pixel of the Chip1is outputted (count value=316), a next signal is outputted from the Chip1. The next signal outputted from the Chip1is inputted to the st terminal of the Chip2, and the output of analog image data of the Chip2is started from the next count value (count value=317). For example, when reading at a resolution of 300 dpi, 216 pixels that the image sensor IC312has are sequentially outputted over count values=317 to 632.

InFIG.5, a region to be read by the Chip1to the Chip3is A1. The read analog image data of A1 is sequentially outputted from Vout1among the output channels that the CIS308has. Also, a region to be read by the Chip4to the Chip6is A2. The read analog image data of A2 is sequentially outputted from Vout2among the output channels that the CIS308has. Also, a region to be read by the Chip7to the Chip9is A3. The read analog image data of A3 is sequentially outputted from Vout3among the output channels that the CIS308has. Also, a region to be read by the Chip10to the Chip12is A4. The read analog image data of A4 is sequentially outputted from Vout4among the output channels that the CIS308has.

On the substrate, OR gates313and314are configured as the output control unit320. The OR gate313takes a MODE selection signal outputted from the timing signal generation unit301and a next signal outputted from the Chip3as inputs, and outputs a logical sum thereof. The outputted signal is inputted to the Chip4, that is, to the st terminal of the Chip4, which is at the start of the adjacent group. If MODE=High, High is inputted to the st terminal of the Chip4. That is, the output of the pixels of the Chip4is started using the horizontal synchronization signal SH as a trigger. If MODE=Low, the output of the pixels of the Chip4is started at the timing at which the next signal of the Chip3is inputted to the st terminal of the Chip4, that is, after all pixels have been outputted from the Chip3.

The OR gate314takes a MODE selection signal outputted from the timing signal generation unit301and a next signal outputted from the Chip9as inputs, and outputs a logical sum thereof. The outputted signal is inputted to the st terminal of the Chip10. If MODE=High, High is inputted to the st terminal of the Chip10. That is, the output of the pixels of the Chip10is started using the horizontal synchronization signal SH as a trigger. If MODE=Low, the output of the pixels of the Chip10is started at the timing at which the next signal of the Chip9is inputted to the st terminal of the Chip10, that is, after all pixels have been outputted from the Chip9.

Note that the output control unit320is not limited to OR gates. For example, instead of the OR gate313, a switch may be used such that when MODE=High, High is outputted, and when MODE=Low, a next signal of the Chip3is outputted. The st terminals of the Chip1and the Chip7are fixed at High.

FIG.6is a view illustrating a configuration of connection of image sensor ICs in a substrate of the CIS309. 12 image sensor ICs312(hereinafter, referred to as Chip13to Chip24) are arranged on a substrate so that light reflected from an A4-sized (about 21 cm) reading target (original) can be read at once. The read analog image data is outputted from two output channels (Vout5to Vout6).

InFIG.6, a region to be read by the Chip13to the Chip18is B1. The read analog image data of B1 is sequentially outputted from Vout5among the output channels that the CIS309has. Also, a region to be read by the Chip19to the Chip24is B2. The read analog image data of B2 is sequentially outputted from Vout6among the output channels that the CIS309has. The st terminals of the Chip13and the Chip19are fixed at High.

[Operation of Each Reading Mode]

The operation of the single-sided reading mode will be described.FIG.7is a view illustrating a timing chart of analog image data outputs of the CIS308and the CIS309and the analog image data inputs to the AFEs in the single-sided reading mode.FIG.8is a view illustrating wire connection in which the analog image data outputted from the CIS308and the CIS309in the single-sided reading mode is inputted to the AFE310and the AFE311via the switching gates315to319. InFIG.8, the configurations illustrated inFIGS.5and6have each been simplified for the CIS308and the CIS309. The AFE310has two input channels, which are Vin1and Vin2, respectively. The AFE311has two input channels, which are Vin3and Vin4, respectively.

The output of analog image data of the CIS308in the single-sided reading mode will be described. In the single-sided reading mode, the timing signal generation unit301outputs a MODE selection signal fixed at High. When the horizontal synchronization signal SH is inputted, the output of analog image data of the Chip1and the Chip7whose st terminals are fixed to High is started. Since High is inputted to the st terminals of the Chip4and the Chip10by the respective outputs of the OR gates313and314, the output of analog image data of the Chip4and the Chip10are started. When the output of analog image data is completed, the next signals of the Chip1, the Chip4, the Chip7, and the Chip10are inputted to the st terminals of the Chip2, the Chip5, the Chip8, and the Chip11, respectively. Then, the output of analog image data of the Chip2, the Chip5, the Chip8, and the Chip11is started. When the output of analog image data of the Chip2, the Chip5, the Chip8, and the Chip11is completed, next signals of the Chip2, the Chip5, the Chip8, and the Chip11are inputted to the st terminals of the Chip3, the Chip6, the Chip9, and the Chip12, respectively. Then, the output of analog image data of the Chip3, the Chip6, the Chip9, and the Chip12is started. When the output of analog image data of the Chip3, the Chip6, the Chip9, and the Chip12is completed, next signals of the Chip3, the Chip6, the Chip9, and the Chip12are outputted (connection destinations are open circuits), and Vout1to Vout4become Hi-z. Vout1to Vout4ofFIG.7indicate the above outputs of analog image data.

The output of analog image data of the CIS309in the single-sided reading mode will be described. Since the CIS309is not used in the single-sided reading mode, a control signal such as a horizontal synchronization signal SH from the timing signal generation unit301is not supplied to the CIS309. As a result, as illustrated inFIG.7, the outputs of Vout5and Vout6become Hi-z.

Note that output channels (Vout2, Vout4) whose output timings are switched by the output control unit320are referred to as variable channels, and the others are referred to as fixed channels.

The input of analog image data to the AFE310and the AFE311in the single-sided reading mode will be described. Analog image data outputted from the CIS308and the CIS309is inputted to the AFE310and the AFE311via switching gates315to319. Each of the switching gates315to319has two input terminals, and selects a signal to be outputted by a MODE selection signal outputted from the timing signal generation unit301. Vin1of the AFE310takes only the analog image data of the A1 region as input when the switching gate315blocks the analog image data of the A2 region. Vin2of the AFE310takes the analog image data of the A2 region as input when the analog image data of the A2 region is allowed to pass by the switching gate317.

Vin3of the AFE311takes the analog image data of the A3 region as input when the switching gate316blocks the analog image data of the A4 region, and only the analog image data of the A3 region is allowed to pass by the switching gate318. Vin4of the AFE311takes the analog image data of the A4 region as input when the analog image data of the A4 region is allowed to pass by the switching gate319. Vout1to Vout4ofFIG.7indicate the above inputs of analog image data.

Next, the operation of the double-sided reading mode will be described.FIG.9is a view illustrating a timing chart of analog image data outputs of the CIS308and the CIS309and the analog image data inputs to the AFEs in the double-sided reading mode.FIG.10is a view illustrating wire connection in which the analog image data outputted from the CIS308and the CIS309in the double-sided reading mode is inputted to the AFE310and the AFE311via the switching gates315to319. InFIG.10, the configurations illustrated inFIGS.5and6have each been simplified for the CIS308and the CIS309. The AFE310has two input channels, which are Vin1and Vin2, respectively. The AFE311has two input channels, which are Vin3and Vin4, respectively.

The output of analog image data of the CIS308in the double-sided reading mode will be described. In the double-sided reading mode, the timing signal generation unit301outputs a MODE selection signal fixed at Low. When the horizontal synchronization signal SH is inputted, the output of analog image data of the Chip1and the Chip7whose st terminals are fixed to High is started. Note that, the next signals of the Chip3and the Chip9are respectively inputted to the st terminals of the Chip4and the Chip10as the respective outputs of the OR gates313and314. Therefore, the output is not started at this point in time, and Vout2and Vout4become Hi-z as illustrated inFIG.9. When the output of analog image data is completed, the next signals of the Chip1and the Chip7are inputted to the st terminals of the Chip2and the Chip8, respectively, and the output of analog image data of the Chip2and the Chip8is started. When the output of analog image data is completed, the next signals of the Chip2and the Chip8are inputted to the st terminals of the Chip3and the Chip9, respectively, and the output of analog image data of the Chip3and the Chip9is started.

When the output of analog image data is completed, Vout1and Vout3become Hi-z, and the next signals of the Chip3and the Chip9are inputted to the st terminals of the Chip4and the Chip10via the OR gates313and314, respectively. Then, the output of analog image data of the Chip4and the Chip10is started. That is, the output will be transmitted on the signal line, where the output start timings of the Chip4and the Chip10(in other words, the output start timings of Vout2and Vout4) are delayed by three chips with respect to the single-sided reading. When the output of analog image data is completed, the next signals of the Chip4and the Chip10are inputted to the st terminals of the Chip5and the Chip11, respectively, and the output of analog image data of the Chip5and the Chip11is started. When the output of analog image data is completed, the next signals of the Chip5and the Chip11are inputted to the st terminals of the Chip6and the Chip12, respectively, and the output of analog image data of the Chip6and the Chip12is started. When the output of analog image data is completed, the next signals of the Chip6and the Chip12are outputted (connection destinations are open circuits), and Vout2and Vout4become Hi-z. Vout1to Vout4ofFIG.9indicate the above outputs of analog image data.

The output of analog image data of the CIS309in the double-sided reading mode will be described. When the horizontal synchronization signal SH is inputted, the output of analog image data of the Chip13and the Chip19whose st terminals are fixed to High is started. When the output of analog image data is completed, the next signals of the Chip13and the Chip19are inputted to the st terminals of the Chip14and the Chip20, respectively, and the output of analog image data of the Chip14and the Chip20is started. When the output of analog image data is completed, the next signals of the Chip14and the Chip20are inputted to the st terminals of the Chip15and the Chip21, respectively, and the output of analog image data of the Chip15and the Chip21is started. When the output of analog image data is completed, the next signals of the Chip15and the Chip21are inputted to the st terminals of the Chip16and the Chip22, respectively, and the output of analog image data of the Chip16and the Chip22is started. When the output of analog image data is completed, the next signals of the Chip16and the Chip22are inputted to the st terminals of the Chip17and the Chip23, respectively, and the output of analog image data of the Chip17and the Chip23is started. When the output of analog image data is completed, the next signals of the Chip17and the Chip23are inputted to the st terminals of the Chip18and the Chip24, respectively, and the output of analog image data of the Chip18and the Chip24is started. When the output of analog image data is completed, the next signals of the Chip18and the Chip24are outputted (connection destinations are open circuits), and Vout5and Vout6become Hi-z. Vout5and Vout6ofFIG.9indicate the above outputs of analog image data.

The input of analog image data to the AFE310and the AFE311in the double-sided reading mode will be described. Vin1of the AFE310takes the analog image data of the A1 region and the analog image data of the A2 region as input in time series by wired-OR by allowing the analog image data of the A2 region to pass by the switching gate315. Regarding Vin2of the AFE310, the analog image data of the A3 region and the analog image data of the A4 region are configured to be in a wired-OR by allowing the analog image data of the A4 region to pass by the switching gate316. Then, Vin2of the AFE310takes as input a wired-OR of the analog image data of the A3 region and the analog image data of the A4 region as input in time series by the wired-ORed analog image data being allowed to pass by the switching gate317.

Vin3of the AFE311takes the analog image data of the B1 region as input by the analog image data of the B1 region being allowed to pass by the switching gate318. Vin4of the AFE311takes the analog image data of the B2 region as input by the analog image data of the B2 region being allowed to pass by the switching gate319. Vout1to Vout4ofFIG.9indicate the above inputs of analog image data.

Further, in the present embodiment, the switching gates315and316may be arranged on the CIS substrate of the CIS308. Note that although the switching gates315and316use a switch with two inputs and one output, it may be a switch with one input and one output. Also, the CIS309has two output channels for analog image data, but may be configured to have four output channels for analog image data as in the CIS308, and may be able to switch output timings.

FIG.11is a flowchart illustrating a reading operation of the image reading apparatus100in the present embodiment. The processing ofFIG.11is realized, for example, by the CPU511reading a program stored in the ROM512to the DRAM513and executing it. In step S100, the ASIC510accepts a single-sided reading or simultaneous double-sided reading job (hereinafter, double-sided reading) inputted by the user via the operation unit104or the external apparatus520. The job here may include copying in which a scanned image is printed. In step S101, the ASIC510determines, based on the accepted job, which reading mode (the single-sided reading or the double-sided reading) is selected. If it is determined that single-sided reading is selected (YES in step S101), the processing proceeds to step S102, and if it is determined that double-sided reading is selected (NO in step S101), the processing proceeds to step S104.

If it is determined that single-sided reading is selected, the CPU511, in step S102, writes “1” to the mode register (not illustrated) of the ASIC510. In step S103, the ASIC510outputs High as the MODE selection signal based on the setting of the mode register and, in step S106, starts the reading operation. Meanwhile, if it is determined that double-sided reading is selected, the CPU511, in step S104, writes “0” to the mode register (not illustrated) of the ASIC510. In step S105, the ASIC510outputs Low as the MODE selection signal based on the setting of the mode register and, in step S106, starts the reading operation.

In step S107, the CIS308and the CIS309output the analog image data corresponding to the respective reading modes in accordance with the set signal, and the processing proceeds to step S108. Note that the output in step S107is executed as described inFIGS.7and9.

In step S108, the ASIC510determines, based on the accepted job, which reading mode (the single-sided reading or the double-sided reading) is selected. When it is determined that single-sided reading is selected (YES in step S108), the MODE selection signal is inputted to the switching gates315and316as High in step S109. Consequently, as illustrated inFIG.8, the analog image data of the variable channels are blocked by the switching gates315,316and the processing proceeds to step S111. Meanwhile, when it is determined that double-sided reading is selected (NO in step S108), the MODE selection signal is inputted to the switching gates315and316as Low in step S110. Consequently, as illustrated inFIG.10, the analog image data of the variable channels respectively passes through the switching gates315and316and the processing proceeds to step S111.

In step S111, the switching gates317to319select analog image data to be inputted to the AFE310and the AFE311in accordance with the input value of the MODE selection signal inputted to the switching gates317to319. Then, the selected analog image data is inputted to the AFE310and the AFE311, and the processing proceeds to step S112. Note that in steps S109to S111, operations as described inFIGS.7to10are performed.

In step S112, the ASIC510converts analog image data outputted from the CIS308and the CIS309into digital image data (also called digital signals). In step S113, the ASIC510performs image processing corresponding to the respective reading modes using the digital image data converted in step S112, and ends the reading operation in step S114. Thereafter, the processing ofFIG.11ends.

As described above, even when the image sensor ICs having no dedicated switching function in the single-sided reading mode is used in the image reading apparatus100that supports simultaneous double-sided reading, the output channels of the CISs can be assigned to all the input channels that the AFEs have. As a result, the analog image data outputted from the respective output channels of the CISs can be inputted to the input channels of the AFEs in parallel, and as illustrated inFIGS.7and9, the reading speed in single-sided reading can be increased in comparison to the double-sided reading.

Note that in the present embodiment, the output of the CIS308for the front side is configured by four channels, and the output of the CIS309for the back side is configured by two channels, but the present invention is not limited to this. For example, the present invention may be configured by another number of channels in accordance with the size of the sheet that the image reading apparatus100handles and the like.

Second Embodiment

[Overall Configuration of Image Reading Apparatus]

Hereinafter, a second embodiment will be described regarding points of difference from the first embodiment. In the first embodiment, it has been described that the processing efficiency in single-sided reading can be improved in the image reading apparatus100that simultaneously reads the front side and the back side of an original using two CISs. In the present embodiment, in the image reading apparatus100, such as a large-format scanner, that reads wide originals by a plurality of arrays of a plurality of CISs in the main scanning direction, it is possible to improve the processing efficiency of reading a region that is narrower than (an original of a size smaller than) a region that can be read by the CISs.

FIG.12is a view illustrating an arrangement of CISs of the image reading apparatus100and an original in the second embodiment. CISs1300to1303are configured by arranging, in the main scanning direction, 12 image sensor ICs1325whose number of read pixels are 224 pixels at a resolution of 300 dpi. The read length of each CIS is, for example, about 22.7 mm. Each CIS is arranged side by side in the main scanning direction, but in the joint portions of each CIS, a staggered array is formed by an overlap in the sub-scanning direction as illustrated inFIG.12in consideration of variations in assembly. Then, by the conveyance of an original in the direction of an arrow B, the original, which is A0 size (about 84 cm) is read with the CISs1300to1303. In the present embodiment, as illustrated inFIG.12, it is also possible to read the A2 size (about 42 cm) using only the CIS1301and the CIS1302, and the reading speed can be made faster than the reading speed of the A0 size.

FIG.13is a view illustrating an example of an internal configuration of a control circuit of the image reading apparatus100in the present embodiment. InFIG.13, an example in which the image reading apparatus100is configured in a multi-function peripheral (hereinafter, referred to as MFP) having a read function and a print function will be described. Since the functions other than the read function are the same as those ofFIG.2, description thereof is omitted, and only the read function will be described. Also, the image reading apparatus100is not limited to the configuration illustrated inFIG.13, and may be an image reading apparatus having only a read function, or may further include a FAX function or the like.

The analog image data outputted from the CIS1300to the CIS1303is inputted to an analog front-end1304(AFE1304) to an analog front-end1307(AFE1307) via a wire connection control unit1324. The wire connection control unit1324is configured to include switching gates1312to1321. Each switching gate is configured to select either one of the two input terminals, and output it from one output terminal.

Each of the AFE1304to the AFE1307has two input channels. The AFE1304to the AFE1307are connected to the ASIC510. The CIS1301and the CIS1302have four output channels for analog image data, and the output timing of analog image data can be switched by the output control units1322and1323, respectively. Details of the timing will be described later. The CIS1300and the CIS1303have two output channel for analog image data. By the CPU511writing setting values to a register (not illustrated), the timing signal generation unit301supplies the CIS1300and the CIS1303with a horizontal synchronization signal SH and a clock signal required to drive each of these. Furthermore, the timing signal generation unit301supplies the output control units1322and1323and the wire connection control unit1324with a MODE selection signal.

MODE selection signals are generated by the CPU511writing setting values in the register (not illustrated) in accordance with an A2-size reading mode or an A0-size reading mode that can be selected by the user via the operation unit104or the external apparatus520. For example, for the A2-size reading mode, by the CPU511writing 1 in the register (not illustrated), a High level signal is outputted as a MODE selection signal. For the A0-size reading mode, by the CPU511writing 0 in the register (not illustrated), a Low level signal is outputted as a MODE selection signal. In the present embodiment, the output timing of analog image data from the CIS1301and the CIS1302is switched by the output control units1322and1323in accordance with the logic state of the MODE selection signal, that is, the reading mode. Furthermore, the input channels for analog image data to be inputted to the AFE1304to the AFE1307are switched by the wire connection control unit1324.

The LED control unit304performs lighting control of the LEDs (not illustrated) with which the CISs1300to the CIS1303are provided. Lighting control is performed by PWM control synchronized with the horizontal synchronization signal SH. Details will be described later for the CIS1300to the CIS1303, the output control units1322and1323, the wire connection control unit1324, and the AFE1304to the AFE1307. Note that although in the present embodiment, four AFEs having two input channels are used, the present invention may be configured with two AFE having four input channels.

FIG.14is a view illustrating a configuration of connection of image sensor ICs in a substrate of the CIS1300. Twelve image sensor ICs1325(hereinafter, referred to as Chip1to Chip12) are arranged on a substrate so that light reflected from a reading target (original) of about 22.7 cm can be read at once. The read and generated analog image data is outputted from two output channels (Vout1, Vout2). In the operation of the image sensor ICs1325, other than that the number of pixels differs from the image sensor ICs312is the same as the description in the first embodiment.

InFIG.14, a region to be read by the Chip1to the Chip6is B1. The read analog image data of B1 is sequentially outputted from Vout1among the output channels that the CIS1300has. Also, a region to be read by the Chip7to the Chip12is B2. The read analog image data of B2 is sequentially outputted from Vout2among the output channels that the CIS1300has.

FIG.15is a view illustrating a configuration of connection of image sensor ICs for selectively switching the output timing of analog image data in a substrate of the CIS1301. 12 image sensor ICs1325(hereinafter, referred to as Chip13to Chip24) are arranged on a substrate so that light reflected from a reading target (original) of about 22.7 cm can be read at once. The read and generated analog image data is outputted from four output channels (Vout3to Vout6).

InFIG.15, a region to be read by the Chip13to the Chip15is A1. The read analog image data of A1 is sequentially outputted from Vout3among the output channels that the CIS1301has. Also, a region to be read by the Chip16to the Chip18is A2. The read analog image data of A2 is sequentially outputted from Vout4among the output channels that the CIS1301has. Also, a region to be read by the Chip19to the Chip21is A3. The read analog image data of A3 is sequentially outputted from Vout5among the output channels that the CIS1301has. Assuming that the region to be read by the Chip22to the Chip24is A4, the read analog image data of A4 is sequentially outputted from Vout6among the output channels that the CIS1301has.

On the substrate, OR gates1308and1309are configured as the output control unit1322. The OR gate1308takes a MODE selection signal outputted from the timing signal generation unit301and a next signal outputted from the Chip15as inputs, and outputs a logical sum thereof. The outputted signal is inputted to the st terminal of the Chip16. If MODE=High, High is inputted to the st terminal of the Chip16. That is, the output of the pixels of the Chip16is started using the horizontal synchronization signal SH as a trigger. If MODE=Low, the output of the pixels of the Chip16is started at the timing at which the next signal of the Chip15is inputted to the st terminal of the Chip16, that is, after all pixels have been outputted from the Chip15.

The OR gate1309takes a MODE selection signal outputted from the timing signal generation unit301and a next signal outputted from the Chip21as inputs, and outputs a logical sum thereof. The outputted signal is inputted to the st terminal of the Chip22. If MODE=High, High is inputted to the st terminal of the Chip22. That is, the output of the pixels of the Chip22is started using the horizontal synchronization signal SH as a trigger. If MODE=Low, the output of the pixels of the Chip22is started at the timing at which the next signal of the Chip21is inputted to the st terminal of the Chip22, that is, after all pixels have been outputted from the Chip21.

FIG.16is a view illustrating a configuration of connection of image sensor ICs for selectively switching the output timing of analog image data in a substrate of the CIS1302. 12 image sensor ICs1325(hereinafter, referred to as Chip25to Chip36) are arranged on a substrate so that light reflected from a reading target (original) of about 22.7 cm can be read at once. The read and generated analog image data is outputted from four output channels (Vout7to Vout10).

InFIG.16, a region to be read by the Chip25to the Chip27is A5. The read analog image data of A5 is sequentially outputted from Vout7among the output channels that the CIS1302has. Also, a region to be read by the Chip28to the Chip30is A6. The read analog image data of A6 is sequentially outputted from Vout8among the output channels that the CIS1302has. Also, a region to be read by the Chip31to the Chip33is A7. The read analog image data of A7 is sequentially outputted from Vout9among the output channels that the CIS1302has. Also, a region to be read by the Chip34to the Chip36is A8. The read analog image data of A8 is sequentially outputted from Vout10among the output channels that the CIS1302has.

On the substrate, OR gates1310and1311are configured as the output control unit1323. The OR gate1310takes a MODE selection signal outputted from the timing signal generation unit301and a next signal outputted from the Chip27as inputs, and outputs a logical sum thereof. The outputted signal is inputted to the st terminal of the Chip28. If MODE=High, High is inputted to the st terminal of the Chip28. That is, the output of the pixels of the Chip28is started using the horizontal synchronization signal SH as a trigger. If MODE=Low, the output of the pixels of the Chip28is started at the timing at which the next signal of the Chip27is inputted to the st terminal of the Chip28, that is, after all pixels have been outputted from the Chip27.

The OR gate1311takes a MODE selection signal outputted from the timing signal generation unit301and a next signal outputted from the Chip33as inputs, and outputs a logical sum thereof. The outputted signal is inputted to the st terminal of the Chip34. If MODE=High, High is inputted to the st terminal of the Chip34. That is, the output of the pixels of the Chip34is started using the horizontal synchronization signal SH as a trigger. If MODE=Low, the output of the pixels of the Chip34is started at the timing at which the next signal of the Chip33is inputted to the st terminal of the Chip34, that is, after all pixels have been outputted from the Chip33.

FIG.17is a view illustrating a configuration of connection of image sensor ICs in a substrate of the CIS1303. Twelve image sensor ICs1325(hereinafter, referred to as Chip37to Chip48) are arranged on a substrate so that light reflected from a reading target (original) of about 22.7 cm can be read at once. The read and generated analog image data is outputted from two output channels (Vout11, Vout12).

InFIG.17, a region to be read by the Chip37to the Chip42is B3. The read analog image data of B3 is sequentially outputted from Vout11among the output channels that the CIS1303has. Also, a region to be read by the Chip43to the Chip48is B4. The read analog image data of B4 is sequentially outputted from Vout12among the output channels that the CIS1303has.

Note that the output control units1322and1323are not limited to OR gates. For example, instead of the OR gate1308, a switch may be used such that when MODE=High, High is outputted, and when MODE=Low, a next signal of the Chip15is outputted.

[Operation of Each Reading Mode]

The operation of the A2-size reading mode will be described.FIG.18is a view illustrating a timing chart of an analog image data output of the CIS1300to the CIS1303in the A2-size reading mode.FIG.19is a view illustrating a timing chart for inputting analog image data to the AFEs.FIG.20is a view illustrating wire connection in which the analog image data outputted from the CIS1300to the CIS1303in the A2-size reading mode is inputted to the AFE1304to the AFE1307via the switching gates1312to1321. InFIG.20, the configurations illustrated inFIGS.14to17have each been simplified for the CIS1300to the CIS1303. The AFE1304has two input channels, which are Vin1and Vin2, respectively. The AFE1305has two input channels, which are Vin3and Vin4, respectively. The AFE1306has two input channels, which are Vin5and Vin6, respectively. The AFE1307has two input channels, which are Vin7and Vin8, respectively.

The output of analog image data of the CIS1300in the A2-size reading mode will be described. Since the CIS1300is not used in the A2-size reading mode, a control signal such as a horizontal synchronization signal SH from the timing signal generation unit301is not supplied to the CIS1300. As a result, as illustrated inFIG.18, the outputs of Vout1and Vout2become Hi-z.

The output of analog image data of the CIS1301in the A2-size reading mode will be described. In the A2-size reading mode, the timing signal generation unit301outputs a MODE selection signal fixed at High. When the horizontal synchronization signal SH is inputted, the output of analog image data of the Chip13and the Chip19whose st terminals are fixed to High is started. Meanwhile, since High is inputted to the st terminals of the Chip16and the Chip22by the respective outputs of the OR gates1308and1309, the output of analog image data of the Chip16and the Chip22are started. When the output of analog image data is completed, the next signals of the Chip13, the Chip16, the Chip19, and the Chip22are inputted to the st terminals of the Chip14, the Chip17, the Chip20, and the Chip23, respectively. Then, the output of analog image data of the Chip14, the Chip17, the Chip20, and the Chip23is started. When the output of analog image data is completed, the next signals of the Chip14, the Chip17, the Chip20, and the Chip23are inputted to the st terminals of the Chip15, the Chip18, the Chip21, and the Chip24, respectively. Then, the output of analog image data of the Chip15, the Chip18, the Chip21, and the Chip24is started. When the output of analog image data is completed, the next signals of the Chip15, the Chip18, the Chip21, and the Chip24are outputted (connection destinations are open circuits), and Vout3to Vout6become Hi-z. Vout3to Vout6ofFIG.18indicate the above outputs of analog image data.

The output of analog image data of the CIS1302in the A2-size reading mode will be described. In the A2-size reading mode, the timing signal generation unit301outputs a MODE selection signal fixed at High. When the horizontal synchronization signal SH is inputted, the output of analog image data of the Chip25and the Chip31whose st terminals are fixed to High is started. Meanwhile, since High is inputted to the st terminals of the Chip28and the Chip34by the respective outputs of the OR gates1310and1311, the output of analog image data of the Chip28and the Chip34are started. When the output of analog image data is completed, the next signals of the Chip25, the Chip28, the Chip31, and the Chip34are inputted to the st terminals of the Chip26, the Chip29, the Chip32, and the Chip35, respectively. Then, the output of analog image data of the Chip26, the Chip29, the Chip32, and the Chip35is started. When the output of analog image data is completed, the next signals of the Chip26, the Chip29, the Chip32, and the Chip35are inputted to the st terminals of the Chip27, the Chip30, the Chip33, and the Chip36, respectively. Then, the output of analog image data of the Chip27, the Chip30, the Chip33, and the Chip36is started. When the output of analog image data is completed, the next signals of the Chip27, the Chip30, the Chip33, and the Chip36are outputted (connection destinations are open circuits), and Vout7to Vout10become Hi-z. Vout7to Vout10ofFIG.18indicate the above outputs of analog image data.

The output of analog image data of the CIS1303in the A2-size reading mode will be described. Since the CIS1303is not used in the A2-size reading mode, a control signal such as a horizontal synchronization signal SH from the timing signal generation unit301is not supplied to the CIS1303. As a result, as illustrated inFIG.18, the outputs of Vout11and Vout12become Hi-z.

Note that channels (Vout4, Vout6, Vout8, Vout10) whose output timings are switched by the output control units1322and1323are referred to as variable channels, and others are referred to as fixed channels.

The input of analog image data to the AFE1304and the AFE1307in the A2-size reading mode will be described. Analog image data outputted from the CIS1300and the CIS1303is inputted to the AFE1304to the AFE1307via switching gates1312to1321. Each of the switching gates1312to1321has two input terminals, and selects a signal to be outputted by a MODE selection signal outputted from the timing signal generation unit301. Vin1of the AFE1304takes only the analog image data of the A1 region as input by the analog image data of the A1 region being allowed to pass by the switching gate1316. Vin2of the AFE1304takes the analog image data of the A2 region as input when the switching gate1312blocks the analog image data of the A1 region, and only the analog image data of the A2 region is allowed to pass by the switching gate1317.

Vin3of the AFE1305takes only the analog image data of the A3 region as input when the analog image data of the A3 region to allowed to pass by the switching gate1318. Vin4of the AFE1305takes only the analog image data of the A4 region as input when the switching gate1313blocks the analog image data of the A3 region.

Vin5of the AFE1306takes only the analog image data of the A5 region as input when the switching gate1314blocks the analog image data of the A6 region. Vin6of the AFE1306takes only the analog image data of the A6 region as input by the analog image data of the A6 region being allowed to pass by the switching gate1319.

Vin7of the AFE1307takes the analog image data of the A7 region as input when the switching gate1315blocks the analog image data of the A8 region, and only the analog image data of the A7 region is allowed to pass by the switching gate1320. Vin8of the AFE1307takes only the analog image data of the A8 region as input when the analog image data of the A8 region is allowed to pass by the switching gate1321.

Next, the operation of the A0-size reading mode will be described.FIG.21is a view illustrating a timing chart of an analog image data output of the CIS1300to the CIS1303in the A0-size reading mode.FIG.22is a view illustrating a timing chart for inputting analog image data to the AFEs.FIGS.23A and23Bare views illustrating wire connection in which the analog image data outputted from the CIS1300to the CIS1303in the A0-size reading mode is inputted to the AFE1304to the AFE1307via the switching gates1312to1321. InFIGS.23A and23B, the configurations illustrated inFIGS.14to17have each been simplified for the CIS1300to the CIS1303. The AFE1304has two input channels, which are Vin1and Vin2, respectively. The AFE1305has two input channels, which are Vin3and Vin4, respectively. The AFE1306has two input channels, which are Vin5and Vin6, respectively. The AFE1307has two input channels, which are Vin7and Vin8, respectively.

The output of analog image data of the CIS1300in the A0-size reading mode will be described. When the horizontal synchronization signal SH is inputted, the output of analog image data of the Chip1and the Chip7whose st terminals are fixed to High is started. When the output of analog image data is completed, the next signals of the Chip1and the Chip7are inputted to the st terminals of the Chip2and the Chip8, respectively, and the output of analog image data of the Chip2and the Chip8is started. When the output of analog image data is completed, the next signals of the Chip2and the Chip8are inputted to the st terminals of the Chip3and the Chip9, respectively, and the output of analog image data of the Chip3and the Chip9is started. When the output of analog image data is completed, the next signals of the Chip3and the Chip9are inputted to the st terminals of the Chip4and the Chip10, respectively, and the output of analog image data of the Chip4and the Chip10is started. When the output of analog image data is completed, the next signals of the Chip4and the Chip10are inputted to the st terminals of the Chip5and the Chip11, respectively, and the output of analog image data of the Chip5and the Chip11is started. When the output of analog image data is completed, the next signals of the Chip5and the Chip11are inputted to the st terminals of the Chip6and the Chip12, respectively, and the output of analog image data of the Chip6and the Chip12is started. When the output of analog image data is completed, the next signals of the Chip6and the Chip12are outputted (connection destinations are open circuits), and Vout1and Vout2become Hi-z. Vout1to Vout2ofFIG.21indicate the above outputs of analog image data.

The output of analog image data of the CIS1301in the A0-size reading mode will be described. In the A0-size reading mode, the timing signal generation unit301outputs a MODE selection signal fixed at Low. When the horizontal synchronization signal SH is inputted, the output of analog image data of the Chip13and the Chip19whose st terminals are fixed to High is started. Note that, the next signals of the Chip15and the Chip21are respectively inputted to the st terminals of the Chip16and the Chip22by the respective outputs of the OR gates1308and1309. Therefore, the output is not started at this point in time, and Vout4and Vout6become Hi-z as illustrated inFIG.21. When the output of analog image data is completed, the next signals of the Chip13and the Chip19are inputted to the st terminals of the Chip14and the Chip20, respectively, and the output of analog image data of the Chip14and the Chip20is started. When the output of analog image data is completed, the next signals of the Chip14and the Chip20are inputted to the st terminals of the Chip15and the Chip21, respectively, and the output of analog image data of the Chip15and the Chip21is started. When the output of analog image data is completed, Vout3and Vout5become Hi-z, and the next signals of the Chip15and the Chip21are inputted to the st terminals of the Chip16and the Chip22via the OR gates1308and1309, respectively. Then, the output of analog image data of the Chip16and the Chip22is started. That is, the output will be transmitted on the signal line, where the output start timings of the Chip16and the Chip22(in other words, the output start timings of Vout4and Vout6) are delayed by three chips with respect to the A2-size reading. When the output of analog image data is completed, the next signals of the Chip16and the Chip22are inputted to the st terminals of the Chip17and the Chip23, respectively, and the output of analog image data of the Chip17and the Chip23is started. When the output of analog image data is completed, the next signals of the Chip17and the Chip23are inputted to the st terminals of the Chip18and the Chip24, respectively, and the output of analog image data of the Chip18and the Chip24is started. When the output of analog image data is completed, the next signals of the Chip18and the Chip24are outputted (connection destinations are open circuits), and Vout4and Vout6become Hi-z. Vout3to Vout6ofFIG.21indicate the above outputs of analog image data.

The output of analog image data of the CIS1302in the A0-size reading mode will be described. In the A0-size reading mode, the timing signal generation unit301outputs a MODE selection signal fixed at Low. When the horizontal synchronization signal SH is inputted, the output of analog image data of the Chip25and the Chip31whose st terminals are fixed to High is started. Note that, the next signals of the Chip27and the Chip33are respectively inputted to the st terminals of the Chip28and the Chip34by the respective outputs of the OR gates1310and1311. Therefore, the output is not started at this point in time, and Vout8and Vout10become Hi-z as illustrated inFIG.21. When the output of analog image data is completed, the next signals of the Chip25and the Chip31are inputted to the st terminals of the Chip26and the Chip32, respectively, and the output of analog image data of the Chip26and the Chip32is started. When the output of analog image data is completed, the next signals of the Chip26and the Chip32are inputted to the st terminals of the Chip27and the Chip33, respectively, and the output of analog image data of the Chip27and the Chip33is started. When the output of analog image data is completed, Vout7and Vout9become Hi-z, and the next signals of the Chip27and the Chip33are inputted to the st terminals of the Chip28and the Chip34via the OR gates1310and1311, respectively. Then, the output of analog image data of the Chip28and the Chip34is started. That is, the output start timings of the Chip28and the Chip34(in other words, the output start timings of Vout8and Vout10) are delayed by three chips with respect to the A2-size reading. When the output of analog image data is completed, the next signals of the Chip28and the Chip34are inputted to the st terminals of the Chip29and the Chip35, respectively, and the output of analog image data of the Chip29and the Chip35is started. When the output of analog image data is completed, the next signals of the Chip29and the Chip35are inputted to the st terminals of the Chip30and the Chip36, respectively, and the output of analog image data of the Chip30and the Chip36is started. When the output of analog image data is completed, the next signals of the Chip30and the Chip36are outputted (connection destinations are open circuits), and Vout8and Vout10become Hi-z. Vout7to Vout10ofFIG.21indicate the above outputs of analog image data.

The output of analog image data of the CIS1303in the A0-size reading mode will be described. When the horizontal synchronization signal SH is inputted, the output of analog image data of the Chip37and the Chip43whose st terminals are fixed to High is started. When the output of analog image data is completed, the next signals of the Chip37and the Chip43are inputted to the st terminals of the Chip38and the Chip44, respectively, and the output of analog image data of the Chip38and the Chip44is started. When the output of analog image data is completed, the next signals of the Chip38and the Chip44are inputted to the st terminals of the Chip39and the Chip45, respectively, and the output of analog image data of the Chip39and the Chip45is started. When the output of analog image data is completed, the next signals of the Chip39and the Chip45are inputted to the st terminals of the Chip40and the Chip46, respectively, and the output of analog image data of the Chip40and the Chip46is started. When the output of analog image data is completed, the next signals of the Chip40and the Chip46are inputted to the st terminals of the Chip41and the Chip47, respectively, and the output of analog image data of the Chip41and the Chip47is started. When the output of analog image data is completed, the next signals of the Chip41and the Chip47are inputted to the st terminals of the Chip42and the Chip48, respectively, and the output of analog image data of the Chip42and the Chip48is started. When the output of analog image data is completed, the next signals of the Chip42and the Chip48are outputted (connection destinations are open circuits), and Vout7and Vout8become Hi-z. Vout11to Vout12ofFIG.21indicate the above outputs of analog image data.

The input of analog image data to the AFE1to AFE4in the A0-size reading mode will be described.

Vin1of the AFE1304takes only the analog image data of the B1 region as input when the analog image data of the B1 region is allowed to pass by the switching gate1316. Vin2of the AFE1304takes only the analog image data of the B2 region as input when the analog image data of the B2 region is allowed to pass by the switching gate1317.

Regarding Vin3of the AFE1305, the analog image data of the A1 region and the analog image data of the A2 region are configured to be in a wired-OR by the analog image data of the A1 region being allowed to pass by the switching gate1312. Then, Vin3of the AFE1305takes the analog image data of the A1 region and the A2 region as input in time series by the wired-ORed analog image data being allowed to pass by the switching gate1318. Regarding Vin4of the AFE1305, the analog image data of the A3 region and the analog image data of the A4 region are wired-ORed by the analog image data of the A3 region being allowed to pass by the switching gate1313. Then, Vin4of AFE1305takes the analog image data of the A3 region and the A4 region as inputs in time series.

Regarding Vin5of the AFE1306, the analog image data of the A6 region and the analog image data of the A5 region are wired-ORed by the analog image data of the A6 region being allowed to pass by the switching gate1314. Then, Vin5of AFE1306takes the analog image data of the A5 region and the A6 region as inputs in time series. Regarding Vin6of the AFE1306, the analog image data of the A7 region and the analog image data of the A8 region are configured to be in a wired-OR by the analog image data of the A8 region being allowed to pass by the switching gate1315. Then, Vin6of the AFE1306takes the analog image data of the A7 region and the A8 region as input in time series by the wired-ORed analog image data being allowed to pass by the switching gate1319.

Vin7of the AFE1307takes only the analog image data of the B3 region as input by the analog image data of the B3 region being allowed to pass by the switching gate1320. Vin8of the AFE1307takes only the analog image data of the B4 region as input by the analog image data of the B4 region being allowed to pass by the switching gate1321.

Further, in the present embodiment, the switching gates1312and1313may be arranged on the CIS substrate of the CIS1301, and the switching gates1314and1315may be arranged on the CIS substrate of the CIS1302. Note that although the switching gates1312to1315use a switch with two inputs and one output, it may be a switch with one input and one output. Further, the CIS1300and the CIS1303have two output channels for analog image data, but may be configured to have four output channels for analog image data as in the CIS1301or the CIS1302, and be able to switch output timings.

FIG.24is a flowchart illustrating a scan operation of the image reading apparatus100in the present embodiment. The processing ofFIG.24is realized, for example, by the CPU511reading the programs stored in the ROM512to the DRAM513and executing it. In step S200, the CPU511accepts a job regarding the size of an original to be read, which was inputted by the user via the operation unit104of the image reading apparatus100or the external apparatus520. The job here may include copying of a scanned image. In step S201, the CPU511determines, based on the accepted job, which reading mode of the A2-size reading and the A0-size reading is selected. If it is determined that A2-size reading is selected (YES in step S201), the processing proceeds to step S202, and if it is determined that A0-size reading is selected (NO in step S201), the processing proceeds to step S204.

If it is determined that A2-size reading is selected, the CPU511, in step S202, writes “1” to the mode register (not illustrated) of the ASIC510. In step S203, the ASIC510outputs High as the MODE selection signal based on the setting of the mode register and, in step S206, starts the reading operation. Meanwhile, if it is determined that A0-size reading is selected, the CPU511, in step S204, writes “0” to the mode register (not illustrated) of the ASIC510. In step S205, the ASIC510outputs Low as the MODE selection signal based on the setting of the mode register of the ASIC510and, in step S206, starts the reading operation.

In step S207, the CIS1300, the CIS1301, the CIS1302, and the CIS1303output the analog image data corresponding to the respective reading modes in accordance with the set signal, and the processing proceeds to step S208. Note that the output in step S207is executed as described inFIGS.18and21.

In step S208, the CPU511determines, based on the accepted job, which reading mode of the A2-size reading and the A0-size reading is selected. When it is determined that A2-size reading is selected (YES in step S208), the MODE selection signal is inputted to the switching gates1312to1321as High in step S209. As a result of that, as illustrated inFIG.20, the analog image data of the fixed channels Vout3and Vout5is blocked at the switching gates1312and1313. Then, the analog image data of the variable channels Vout8and Vout10is blocked at the switching gates1314and1315, and the processing proceeds to step S211. Meanwhile, when it is determined that A2-size reading is not selected (NO in step S208), the MODE selection signal is inputted to the switching gates1312to1321as Low in step S210. As a result of that, as illustrated inFIGS.23A and23B, the analog image data of the fixed channels Vout3and Vout5respectively passes through the switching gates1312and1313. Then, the analog image data of the variable channels Vout8and Vout10respectively passes through the switching gates1314and1315, and the processing proceeds to step S211.

In step S211, the switching gates1316to1321select analog image data to be inputted to the AFE1304and the AFE1307in accordance with the input value of the MODE selection signal inputted to the switching gates1316to1321. Then, the analog image data is inputted to the AFE1304to the AFE1307, and the processing proceeds to step S212. Note that in steps209to S211, operations as described inFIGS.18to23Bare performed.

In step S212, the CPU511converts analog image data outputted from the CIS1300to1303into digital image data. In step S213, the ASIC510performs image processing corresponding to the respective reading modes using the digital image data converted in step S212, and ends the reading operation in step S214. Thereafter, the processing ofFIG.24ends.

As described above, even when the image sensor ICs having no dedicated switching function are used in the image reading apparatus100that supports reading of large-format originals, the output channels of the CISs can be assigned to all the input channels that the AFEs have. As a result, the analog image data outputted from the respective output channels of the CISs can be inputted to the input channels of the AFEs in parallel. Then, as illustrated inFIG.18,FIG.19,FIG.21, andFIG.22, the reading speed at the time of reading an original of a size (e.g., A2 size) narrower than the read width (e.g., A0 size) of the CISs can be increased in comparison to the reading of an original of a larger size.

Note that in the present embodiment, two CISs of four channels and two CISs of two channels are configured, but the present invention is not limited thereto. For example, the number of CISs and the number of channels may be changed in accordance with the size and the like of a sheet that can be handled by the image reading apparatus100.

The present invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the claims are appended hereto in order to make the scope of the invention public.

Other Embodiments

This application claims the benefit of Japanese Patent Application No. 2020-163884, filed Sep. 29, 2020, which is hereby incorporated by reference herein in its entirety.