Variable breakdown transient voltage suppressor

A semiconductor die includes a substrate comprising a first layer of a first wide band gap semiconductor material having a first conductivity, a second layer of a second wide band gap semiconductor material having a second conductivity different from the first conductivity, in electrical contact with the first layer, a third layer of a third wide band gap semiconductor material having a third conductivity different from the first conductivity and second conductivity, in electrical contact with the second layer, a fourth layer of a fourth wide band gap semiconductor material having the second conductivity, in electrical contact with the third layer, and a fifth layer of a fifth wide band gap semiconductor material having the first conductivity and in electrical contact with the fourth layer, wherein the first layer, the second layer, the third layer, the fourth layer, and the fifth layer are sequentially arranged to form a structure.

BACKGROUND

The present application relates generally to transient voltage suppression devices or surge protection devices for protecting electronic circuitry.

A transient voltage suppressor (TVS) device, more popularly known as a surge protector, is an electronic component that is utilized for protecting sensitive electronics from damage such as voltage spikes. A transient or excess voltage (or current) is a momentary or fleeting surge in the voltage (or current) that may harm the sensitive electronic circuitry. In general, a transient voltage suppressor device operates on two principles: attenuating excess current or transient current thereby limiting residual current, or diverting a transient or an excess current from the sensitive electronic components.

Attenuating a transient current is typically achieved by ensuring that the transient current does not reach or impact the sensitive electronic components, often by using filters inserted in series with the electronic components. Diverting a transient current is typically achieved by using a voltage clamping device or a crowbar type device. In operation, the voltage clamping device has variable impedance that varies in response to the current flowing through the voltage clamping device.

Silicon based TVS devices have conventionally been used for preventing sensitive electronic components from being subjected to current or voltage transients caused by lightning strikes or electromagnetic interferences. However, silicon based TVS devices are more vulnerable to generate high leakage currents as the temperatures are increased. Particularly, when the ambient temperature reaches unacceptably high values, for example 225 degrees Celsius, the silicon based TVS devices become unsuitable for the operation due to the excessive leakage current. For example, the silicon based TVS devices are typically incapable of providing sufficient protection to the electronic components used in a distributed control system in an aircraft especially from the voltage surges due to lightning strikes.

Thus, there is an increasing need for TVS devices that can operate in high temperatures, with minimum leakage current and maximum efficiency.

BRIEF DESCRIPTION

In accordance with aspects of the present disclosure, a semiconductor die for a transient voltage suppressor is disclosed. The semiconductor die includes a substrate comprising a first layer of a first wide band gap semiconductor material having a first conductivity, a second layer of a second wide band gap semiconductor material having a second conductivity different from the first conductivity, in electrical contact with the first layer, a third layer of a third wide band gap semiconductor material having a third conductivity different from the first conductivity and second conductivity, in electrical contact with the second layer, a fourth layer of a fourth wide band gap semiconductor material having the second conductivity, in electrical contact with the third layer, and a fifth layer of a fifth wide band gap semiconductor material having the first conductivity, in electrical contact with the fourth layer, wherein the first layer, the second layer, the third layer, the fourth layer, and the fifth layer are sequentially arranged to form a structure.

In accordance with another aspect of the present disclosure, a method for suppressing a transient voltage is disclosed. The method includes detecting an applied voltage greater than a threshold voltage across a semiconductor die, wherein the semiconductor die includes a first layer of a first conductivity, a second layer of a second conductivity, a third layer of a third conductivity, a fourth layer of the second conductivity, and a fifth layer of the first conductivity. The method further includes detecting a reverse breakdown voltage across the first layer and the second layer in response to detecting the applied voltage, generating a first plurality of charge carriers at a junction between the first layer and the second in response to detecting the reverse breakdown voltage, moving a first set of charge carriers among the first plurality of charge carriers towards the fifth layer, detecting a forward bias voltage across the fourth layer and the fifth layer, moving a second set of charge carriers from the fifth layer towards the first layer in response to detecting the forward bias, and absorbing the first set of charge carriers and the second set of charge carriers in at least one of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer; wherein the first layer, the second layer, the third layer, the fourth layer, and the fifth layer are disposed sequentially to form a structure.

In accordance with yet another aspect of the present disclosure, a method for forming a transient voltage suppressor is disclosed. The method includes providing a substrate comprising a first wide band gap semiconductor material, diffusing a dopant of a first conductivity type into the substrate to obtain a first layer of a first conductivity, forming a second layer of a second wide band gap semiconductor material having a second conductivity over at least a portion of the first layer, forming a third layer of a third wide band gap semiconductor material having a third conductivity over at least a portion of the second layer, forming a fourth layer of a fourth wide band gap semiconductor material having the second conductivity over at least a portion of the third layer, and forming a fifth layer of a fifth wide band gap semiconductor material having the first conductivity over at least a portion of the fourth layer.

In accordance with yet another aspect of the present disclosure, an electronic system is disclosed. The electronic system includes at least one electronic unit and a protection device electrically coupled to the at least one electronic unit. The protective device includes a semiconductor die having a structure. The semiconductor die includes a substrate comprising a first layer of a first wide band gap semiconductor material having a first conductivity, a second layer of a second wide band gap semiconductor material having a second conductivity different from the first conductivity, in electrical contact with the first layer, a third layer of a third wide band gap semiconductor material having a third conductivity different from the first conductivity and the second conductivity, in electrical contact with the second layer, a fourth layer of a fourth wide band gap semiconductor material having the second conductivity in electrical contact with the third layer, and a fifth layer of a fifth wide band gap semiconductor material having the first conductivity in electrical contact with the fourth layer, wherein a first terminal of the protection device is electrically coupled to the substrate and a second terminal of the protection device is electrically coupled to the fifth layer.

DESCRIPTION

Embodiments disclosed herein are generally directed towards protection of electronic units in a system. According to one embodiment, the disclosure describes a transient voltage protection device or a surge protector that may be used in combination with sensitive electronic units to protect the electronic units from voltage surges, or current surges, or transient currents or transient voltages in the system. In one example, the transient voltage protection is provided at substantially high temperatures, for example, temperatures greater than 200 degrees Celsius, and in other examples for temperatures at or above 300 degrees Celsius. Hereinafter, the terms “voltage surge” and “transient voltage” may be used interchangeably to indicate an unexpected or excessive increase in voltage compared to an average voltage across the system. Similarly, the terms “current surge” and “transient current” may be used interchangeably to indicate an unexpected increase in the current compared to an average current transmitted through the system. Hereinafter, the term “transients” may be used to generically refer to transient voltage or transient current. Although certain embodiments of the present invention are discussed herein with reference to systems operating at high temperatures, it should be noted herein that the application of embodiments of the present system may also be suitable for other systems that require protection from voltage or current surges. This includes but not limited to various power distribution systems that require installing expensive cooling systems or moving the electronic units in the power distribution system away from the sensors or actuators to prevent any damage due to excessive voltage or voltage surges.

FIG. 1is a simplified block diagram of a system100in accordance with an exemplary embodiment of the present system. In an exemplary embodiment, the system100may include but is not limited to an aircraft or probes sent deep into bore wells used for exploration and monitoring of petroleum and geothermal wells. In certain applications this may be in environments where temperatures may reach as high as 200 to 300 degrees Celsius or even greater. In one example, the system100includes a power supply bus102, a communication channel104, and a plurality of electronic units located within the component106of the system100. In an exemplary embodiment, the component106may be a gas turbine engine including a fan and/or a core engine of an aircraft. In another embodiment, the component106may be one of a piston driven internal combustion engine, a compressor, a generator, and a pump. Further, the plurality of electronic units may include electronic units (EU)108,110operated at normal ambient temperatures, and electronic units capable of operating at temperatures as high as 200 degrees Celsius, 300 degrees Celsius, and greater than 300 degrees Celsius, herein referred to as “high temperature electronic units” (HT-EU)112,114,116. It should be understood that the electronic units108,110and high temperature electronic units112,114,116can be disposed as a co-located unit that could include disposing the electronic units away from the higher temperature regions or with some insulation to protect the electronic units. In other applications the electronic units108,110are physically located away from the high temperature electronic units112,114,116and the high temperature regions.

The system100further includes a power module118for providing power to the component106. The component106may further transmit the received power to the electronic units108,110and high temperature electronic units112,114,116via the power supply bus102. Similarly, communication among various electronic units108,110and high temperature electronic units112,114,116are transmitted via the communication channel104. In one example the communication channel104is further coupled to a communication module120that transmits, processes, and receives all communication to and from the component106of the system100. It should be noted herein that in other embodiments, configuration of the system100may vary depending on the application. For example, the communication module120and/or power module118can be co-located or integrated within the component106as well as positioned apart from the component106and operatively coupled by wiring. In another example, the communication module120is decentralized and integrated into the electronic units108,110and high temperature electronic units112,114,116such as employing transceivers that communicate to a central processing system (not shown).

During an operation of the system100according to one embodiment, when an electromagnetic interference or lightning impacts the system100, transient voltage spikes are typically induced onto the power module118that is coupled to the power supply bus102. The transient voltages may therefore damage the electronic units108,110and high temperature electronic units112,114,116. In order to prevent such damage, an exemplary protection devices (not shown) such as one or more transient voltage suppressors or surge protectors are coupled to the electronic units108,110, and the high temperature electronic units112,114,116. The protection device such as the transient voltage suppressor may be disposed in parallel or in series with the electronic units108,110and high temperature electronic units112,114,116. It should be noted herein that the configuration illustrated inFIG. 1is an exemplary embodiment and should not in any way be construed as limiting the scope. The arrangement of the various components, number of components, integration of components, and relative positions may vary depending on the application. The protection device is explained in greater detail below with reference to subsequent figures.

FIG. 2is an exemplary schematic block diagram representing the electronic unit108, the power module118, the communication module120, a transient voltage suppressor206, and a transient voltage suppressor assembly208according to an exemplary embodiment. The illustrated electronic unit108in this example further includes but not limited to a processor202and a data repository204. The processor202is an electronic circuit capable of processing instructions and performing various tasks such as computations etc. The processor202in one aspect is one or more processors, controllers, microcontrollers and the like. The data repository204, such as a memory storage unit including random access memory, read only memory, flash memory, or the like is used for storage of various types of information associated with the electronic unit108. The power module118is coupled to a voltage supply source (not shown) and is configured to distributed power through the electronic unit108. In an exemplary embodiment, the power module118is coupled to the power supply bus102and distributes power through the electronic unit108. Further, in one embodiment, the communications module120is coupled to the communications channel104. The communication module120and the power module118of the electronic unit108are at risk of being damaged due to any transients resulting from lightning strikes, solar flares, electromagnetic pulse (EMP), or other electromagnetic interferences in the system100, since the communication module120and the power module118are coupled to the communication channel104and power supply bus102respectively. In accordance with the embodiments of the present system, in order to prevent transients from being transmitted to the electronic unit108via the communication module120and/or the power module118via the bus102, and the channel104, one or more transient voltage suppressors (TVS)206or an assembly of transient voltage suppressors208are coupled to the communication channel104and the power supply bus102respectively. It should be noted herein that although the exemplary voltage suppressor are discussed specifically with reference to the electronic unit108, in other embodiments, the voltage suppressor206may be used for other electronic units including the high temperature electronics units. The TVS206is further explained in greater detail with reference to the subsequent figures. The TVS assembly208in one example refers to a plurality of TVS devices206. For example, the TVS assembly208may include one or more of a series arrangement of TVS206or one or more of a parallel arrangement of TVS206or combinations thereof. It should be noted herein that the configuration illustrated inFIG. 2is an exemplary embodiment and should not in any way be construed as limiting the scope. The arrangement of the various components, number of components, integration of components, and relative positions may vary depending on the application. Specifically, the number and relative positions of TVS may vary depending on the application.

FIGS. 3,4,5illustrate schematic block diagrams of various configurations in which one or more transient voltage suppressor (TVS) can be coupled to form an assembly208that may be coupled to an electronic unit, such as the electronic unit108ofFIG. 1, for preventing damage to the electronic unit108. In an exemplary embodiment illustrated inFIG. 3, the transient voltage suppressor assembly208includes two TVS206coupled in series. Similarly, in the exemplary embodiment illustrated inFIG. 4, a transient voltage suppressor assembly208includes two transient voltage suppressors206coupled in series combination, while a third transient voltage suppressor206is coupled in parallel across the series combination. Similarly, in the exemplary embodiment illustrated inFIG. 5, a transient voltage suppressor assembly208includes two transient voltage suppressors206in a parallel configuration disposed in series with a third transient voltage suppressor206. The transient voltage suppressor assembly208shown inFIG. 3,FIG. 4, andFIG. 5may be placed in parallel with an electronic unit (such as electronic unit108) under protection. Various other combinations of individual transient voltage suppressors206maybe envisaged to provide sufficient current transmitting capacity and voltage performance for different applications.

FIG. 6is a schematic block diagram of a conventional transient voltage suppressor600. As shown inFIG. 6, the conventional transient voltage suppressor600includes a first semiconductor layer610, a second semiconductor layer612, and a third semiconductor layer614and two junctions616,618among the layers610,612,614. The semiconductor layers610,612,614may include any semiconductor material such as silicon. Further, each of the semiconductor layers610,612,614possesses a specific conductivity. It should be noted herein that the conductivity of a semiconductor material is indicative of the majority and minority charge carriers in the semiconductor material. For example, an n-type semiconductor material includes “negative charge carriers” as majority charge carriers and “positive charge carriers” as minority charge carriers. For example, a p-type semiconductor material includes “negative charge carriers” as minority charge carriers and “positive charge carriers” as majority charge carriers. As is understood by one of ordinary skilled in the art, a “negative charge carrier” refers to electrons whereas a “positive charge carriers” refers to holes.FIG. 6shows a first layer610having a conductivity of type n, a second layer612having a conductivity of type p, and a third layer614having a conductivity of type n.

FIG. 7shows a graphical representation of current (I) versus voltage (V) for the conventional transient voltage suppressor600shown inFIG. 6. The graph shown inFIG. 7shows a voltage (V) applied across the conventional transient voltage suppressor600, represented by the x-axis and the current (I) conducted through the conventional transient voltage suppressor600, represented by the y-axis. Further, a reverse breakdown voltage is shown to occur at a voltage UBDat a reverse biased junction J2, where J2may be one of the junctions616,618(shown inFIG. 6). Similarly, a forward biased voltage is shown to occur at a voltage UBDat a junction J1, where J1is the other of the junctions616,618(i. e. the junction other than a reversed biased junction). The conventional transient voltage suppressor600conducts current when one of the junctions616,618is reverse biased while the other junction616,618is forward biased in response to detecting a voltage supply that is greater than a threshold value. A reverse bias is described as a condition where a cathode end (herein, n type layers610,614) is coupled to a positive bias of the voltage supply source, whereas an anode end (herein, p type layer612) is coupled to a negative bias of the voltage supply source. Further, a forward bias is described as a condition when a cathode end (herein n type layers610,612) is coupled to a negative bias of the voltage supply source, whereas an anode end (herein p type layer612) is coupled to a positive bias of the voltage supply source. However, in the conventional transient voltage suppressor600, a peak electric field is experienced at the edges of the transient voltage suppressor600due to a field crowding effect. As known in the art, an electric field at the edges usually becomes larger than in the middle of the transient voltage suppressor600(termed as the “field crowding effect”), leading to a reduction of the breakdown voltage. Even if the edges of the conventional transient voltage suppressor600are beveled, under reverse bias conditions for a junction, the depletion of p-layer (such as layers610,614) would occur primarily along the edges (or the side walls) leading to an increase in the leakage current. As a result, soft breakdown characteristic as shown inFIG. 7occurs at voltage UBD(shows us UBD(J1) and UBD(J2)), leading to a decrease in the reverse breakdown voltage.

FIG. 8shows a cross sectional view of the transient voltage suppressor (TVS)206, in accordance with an embodiment. The TVS206ofFIG. 8includes a semiconductor die820which further includes a first layer804, a second layer806, a third layer808, a fourth layer810, and a fifth layer812and two metal contacts layers802,814. The TVS206may further include a substrate material (not shown) on which the first layer804is formed. In other words, the substrate material is a foundation layer or material on which the first layer804, the second layer806, the third layer808, the fourth layer810, and the fifth layer812are sequentially disposed to form a structure. In one embodiment, the first layer804, the second layer806, the third layer808, the fourth layer810, and the fifth layer812are disposed to form a mesa structure with beveled walls inclined at an angle α with respect to an interface between adjacent layers among the first layer804, the second layer806, the third layer808, the fourth layer810, and the fifth layer812. In this case, the angle α ranges from about 2 degrees to less than 90 degrees. For example, in one particular example, the angle α is about 20 degrees. In another embodiment, the first layer804, the second layer806, the third layer808, the fourth layer810, and the fifth layer812are disposed to form a structure with walls inclined at an angle of about 90 degrees with respect to an interface between adjacent layers among the first layer804, the second layer806, the third layer808, the fourth layer810, and the fifth layer812, as shown inFIG. 9where angle α is equal to 90 degrees. In yet another embodiment, two or more layers among the layers804,806,808,810,812may be inclined at different angles with respect to an interface between adjacent layers among the first layer804, the second layer806, the third layer808, the fourth layer810, and the fifth layer812.

Returning again toFIG. 8, the metal contact layers802and814are formed on the opposing ends of the semiconductor die820in order to provide ohmic contacts for the first layer804and the fifth layer812. The first layer804may be coupled to a metal electrode (not shown) via the metal contact layer802. Similarly, the fifth layer812may be coupled to a metal electrode (not shown) via the metal contact layer814.

The semiconductor die820of the TVS206in one example is a block of a semiconducting material on which a functional circuit is fabricated. Further, each of the first layer804, the second layer806, the third layer808, the fourth layer810, and the fifth layer812is constituted of a semiconductor material having an associated conductivity according to one embodiment. In one embodiment, the substrate of the semiconductor die820as well as the layers804,806,808,810,812are constituted of a semiconductor material such as a wide band gap semiconductor material. In general, a wide band gap semiconductor is a semiconductor material with electronic band gaps larger than one or two electronvolts (eV). For example, some of the high band gap materials may include diamond, silicon carbide, aluminum nitride, gallium nitride, boron nitride etc. In one exemplary embodiment, the first layer804is of a first wide band semiconductor material, the second layer806is of a second wide band semiconductor material, the third layer808is of a third wide band semiconductor material, the fourth layer810is of a fourth wide band semiconductor material, and the fifth layer812is of a fifth wide band semiconductor material. In one such embodiment, each of the first wide band gap semiconductor material, the second wide band gap semiconductor material, the third wide band gap semiconductor material, the fourth wide band gap semiconductor material, and the fifth wide band gap semiconductor material is a distinct material. In one exemplary embodiment, the first wide band gap semiconductor material, the second wide band gap semiconductor material, the third wide band gap semiconductor material, the fourth wide band gap semiconductor material, and the fifth wide band gap semiconductor material have some materials that are similar and some materials that are different. In yet another exemplary embodiment, the first wide band gap semiconductor material, the second wide band gap semiconductor material, the third wide band gap semiconductor material, the fourth wide band gap semiconductor material, and the fifth wide band gap semiconductor material are the same materials. In one specific exemplary embodiment, each of the first wide band gap semiconductor material, the second wide band gap semiconductor material, the third wide band gap semiconductor material, the fourth wide band gap semiconductor material, and the fifth wide band gap semiconductor material includes silicon carbide (SiC).

Further, the conductivity of the layers804,806,808,810,812is a function of the type of semiconductor material of the layers804,806,808,810,812and a concentration of dopants in the respective semiconductor material in each of the layers804,806,808,810,812. According to the exemplary embodiment illustrated inFIG. 8, the first layer804and the fifth layer812have a conductivity of n+(n plus) type, the second layer806and the fourth layer810have a conductivity of p−(p minus) type, and the third layer808has a conductivity of one of a p type or p+(p plus) type. An n type semiconductor material includes an semiconductor material with a larger concentration of negative charge carriers than positive charge carriers, i.e., an n type semiconductor has a larger electron concentration relative to hole concentration. Therefore, in n type semiconductors, electrons are the majority carriers and holes are the minority carriers. In general, the n type semiconductors are created by doping a semiconductor material with donor impurities. Donor impurities also referred to herein as donor atoms, have more valence electrons than the atoms that the donor atoms replace in the intrinsic semiconductor material during doping. In this way, the donor atoms provide excess electrons to the semiconductor material. Excess electrons increase the negative carrier concentration or electron concentration of the semiconductor material resulting in an n type semiconductor material. For example, an n type semiconductor may be obtained by doping an intrinsic semiconductor material such as a group IV element, for example, silicon (Si) with a group V element such as phosphorous (P), arsenic (As) etc.

Similarly, a p type semiconductor material includes a larger concentration of positive charge carriers, hereon referred to as “holes”, than the negative charge carriers. A p type semiconductor material is obtained by doping a semiconductor material with acceptor impurities. Acceptor impurities have less valence electrons than the atoms that the impurities replace in the semiconductor material, thereby providing excess holes and creating a p type semiconductor material. For example, a p type semiconductor may be obtained by doping an extrinsic semiconductor material such as a group IV element, for example, silicon (Si) with a group III element for example, boron (B), aluminum (Al) etc.

Further, a doping concentration of an intrinsic semiconductor material may be relative, generating an n+or n−and similarly p+or p−semiconductor. The superscripts plus (+) and minus (−) denote the relative level of doping. For example, an n+type semiconductor material is heavily doped with semiconductor impurities compared to an n−semiconductor material (or an n type semiconductor material) that is relatively lightly doped. Similarly, a p+type semiconductor is heavily doped with donor impurities compared to a p type or p−type semiconductor material. For example, in crystalline intrinsic silicon, there are approximately 5×1022atoms/cm3and the intrinsic charge carrier concentration is approximately 1e10 cm−3. Heavily doped silicon includes a proportion of impurity (donor or acceptor) to silicon of the order of 1e18 cm−3. On the other hand, lightly doped silicon contains a proportion of impurity (donor or acceptor) to silicon of the order of 1e16 cm−3.

Referring again to the illustrated embodiment ofFIG. 8, as previously noted, each layer804,806,808,810,812is associated with a wide band gap semiconductor material having an associated conductivity. The first layer804of conductivity n+type may be obtained by a suitable process such as diffusion or epitaxial growth of impurities on a semiconductor substrate. As previously explained, the n+layer has an excess concentration of negative charge carriers (electrons) as compared to the semiconductor substrate. The excess concentration of negative charge carriers in the first layer804may be attributed to the heavy doping of the first layer804with donor impurities. In an exemplary embodiment, the first layer804is a silicon carbide (SiC) based semiconductor layer. The first layer804is disposed between the metal contact layer802and the second layer806.

The second layer806has a conductivity of p−type and is disposed on the first layer804. The second layer806is a lightly doped p layer, i.e., the second layer806is lightly doped with acceptor impurities compared to a p type layer. Therefore, the second layer806has a relatively lower concentration of positive charge carriers as compared to a concentration of positive charge carriers in a layer of p type. However, in comparison to the first layer804which is an n+type layer, the second layer806has a larger concentration of positive charge carriers. The second layer806is disposed between the first layer804and the third layer808. In one embodiment, the second layer806is disposed epitaxially on the first layer804. In another embodiment, the second layer806is formed on the first layer804using an ion implantation technique.

The third layer808has a conductivity of either p+type or p type and is heavily doped with acceptor impurities. The third layer808has a higher concentration of positive charge carriers compared to the second layer806(p−type) and the first layer804(n+type). The third layer808is disposed between the second layer806and the fourth layer810. The third layer808is formed on the second layer806by using one or more semiconductor fabrication techniques such as epitaxial growth, ion implantation, or similar fabrication techniques.

The fourth layer810has a conductivity of p−type, i.e., the fourth layer810has a lower concentration of positive charge carriers compared to the third layer808, which is one of a p type or p+type layer. The fourth layer810is relatively lightly doped with acceptor impurities. In one embodiment, the doping concentration of the fourth layer810may be similar to the doping concentration of the second layer806. In another embodiment, the doping concentration of the fourth layer810is slightly lower than the doping concentration of the second layer806, resulting in less positive charge carriers in the fourth layer810than in the second layer806. In yet another embodiment, the doping concentration of the fourth layer810is slightly greater than the doping concentration of the second layer806, resulting in more positive charge carriers in the fourth layer810than in the second layer806. Similar to the earlier discussed layers, the fourth layer810is disposed between the third layer808and the fifth layer812.

The fifth layer812has a conductivity of n+type, i.e., the fifth layer812is a heavily doped n layer. The fifth layer812is heavily doped with donor impurities. In other words, the fifth layer812has more negative charge carriers compared to each of the second layer806, the third layer808, and the fourth layer810. However, in comparison to the first layer804, the fifth layer812may be relatively equivalently doped, or relatively lightly doped, or relatively heavily doped, depending upon the application.

It should be noted herein that a breakdown voltage of a junction formed between mutually adjoining layers is determined based on a concentration of dopants in one or more of an adjoining p type (p+type or p−type) and n type (n+type or n−type) layer and the thickness of the corresponding layer. In the absence of an external applied voltage supply source, an equilibrium condition is obtained across the junction by diffusion of free charge carriers between the adjoining layers across the junction leading to a creation of a “potential barrier” or a “potential difference” or a “depletion region”. The breakdown voltage of a junction may be referred to as a maximum voltage that can be applied across the junction (also referred to as “depletion region”) before the junction collapses.

In the illustrated exemplary embodiment ofFIG. 8, a breakdown voltage across a first junction816between the first layer804and the second layer806is determined based on a concentration of dopants in the first layer804, and the second layer806, and a thickness of the first layer804, and the second layer806. Similarly, a breakdown voltage for a second junction818between the fourth layer810and the fifth layer812is determined based on a concentration of dopants in the fourth layer810, and the fifth layer812, and a thickness of the fourth layer810, and the fifth layer812. In one embodiment, the breakdown voltage of the first junction816and the breakdown voltage of the second junction818may be similar, leading to a symmetrical transient voltage suppressor208. In another embodiment, the breakdown voltage of the first junction816and the breakdown voltage of the second junction818may be different leading to an asymmetrical transient voltage suppressor208.

Further, according to one exemplary embodiment of the present device, a transient voltage suppressor may be a mirror image of the transient voltage suppressor206illustrated inFIG. 8. In such an embodiment, the mirror-image transient voltage suppressor constitutes of a first layer of a first wide band semiconductor material having a conductivity of p+type, a second layer of a second wide band semiconductor material having a conductivity of n−type, a third layer of a third wide band semiconductor material having a conductivity of either an n type or an n+ type, a fourth layer of a fourth wide band semiconductor material having a conductivity of n−type, and a fifth layer of a fifth wide band semiconductor having a conductivity of p+type. The working of the transient voltage suppressor206is explained in greater detail with reference to subsequent figures. The mirror-image transient voltage suppressor operates in a similar fashion as the transient voltage suppressor206using its minority and majority charge carriers in various layers.

FIG. 10is an exemplary representation of an electronic system100having a symmetrical transient voltage suppressor206coupled to the electronic unit108and the voltage supply source904. The transient voltage suppressor206having a semiconductor die820is configured to protect the electronic unit108from voltage transients or voltage spikes. In one embodiment, the transient voltage suppressor206may be coupled in parallel with the electronic unit108. In other embodiments, any suitable orientation may be used for coupling the transient voltage suppressor206to the electronic unit108to protect the electronic unit108. The electronic unit108may be operated at ambient temperature or at a substantially higher temperature, for example, in the range of 150° C. to 300° C., or greater.

In the illustrated embodiment, the transient voltage suppressor206has a symmetrical semiconductor die820with a same reverse breakdown voltage for both the junctions816,818. In other words, a reverse breakdown voltage for the first junction816between the first layer804and the second layer806is the same as the reverse breakdown voltage for the second junction818between the fourth layer810and the fifth layer812. That is, a concentration of dopants and a thickness of the second layer806is equivalent to a concentration of dopants and a thickness of fourth layer810to achieve a symmetrical semiconductor die820. Further, the voltage supply source904is coupled across the semiconductor die820such that a positive terminal (bias)906of the voltage supply source904is coupled to one end of the transient voltage suppressor206and a negative terminal (bias)908is coupled to an opposite end of the transient voltage suppressor206. In the illustrated exemplary embodiment, the positive terminal906is coupled via the metal layer802to the first layer804of the transient voltage suppressor208. The negative terminal908is coupled via the metal layer814to the fifth layer812of the transient voltage suppressor206.

In response to applying the voltage supply source904in the above described manner, the transient voltage suppressor206determines an electric potential difference between the first layer804and the fifth layer812, i.e., across the semiconductor die820. When the electric potential difference across the first layer804and the fifth layer812is greater than a threshold value, such as in case of an occurrence of a voltage transient, the semiconductor die820starts to conduct electric current. In particular, the voltage thus created causes the semiconductor die820to be more conducting compared to the electronic unit108by providing a lower resistance path to the flow of current. Thus, when a voltage spike or transient is encountered, the excess current is borne by the transient voltage suppressor206while protecting the electronic unit108. It should be noted herein that the voltage threshold value is a function of the concentration of dopants in the mutually adjacent layers and thickness of the corresponding mutually adjacent layers. A detailed explanation for the working of the transient voltage suppressor206in response to experiencing a voltage transient is described in further detail herein.

Under certain transient conditions, a high voltage of the order of 1500 or more volts from the voltage supply source904is generated between the first layer804and the fifth layer812. When the generated voltage is higher than a threshold voltage, a reverse biasing of the first layer804and the second layer806occurs. The threshold voltage supply is a function of the semiconductor material of the layers804,806,808,810,812and a doping concentration of each of the layers804,806,808,810,812. It should be noted herein that a reverse bias is a condition when a cathode end (n type semiconductor) is coupled to a positive bias (such as positive bias906), whereas an anode end (p type semiconductor) is coupled to a negative bias (such as negative bias908) of the voltage supply source904. With an increase in the electric potential difference across the transient voltage suppressor206, the reverse biasing across the first layer804, and the second layer806also increases, leading to a generation of a large number of high energy charge carriers at the first junction816between the first layer804and the second layer806. These high energy charge carriers knock down other charge carriers from the nearby atoms at the first junction816. Such multiplication of charge carriers eventually results in an “avalanche breakdown” at the first junction816between the first layer804and the second layer806due to the excess of the charge carriers, resulting in increase of the current flow.

It is to be noted that each of the charge carriers possesses specific charge conductivity. The charge conductivity may be either positive charge conductivity or a negative charge conductivity. In the illustrated embodiment, some of the charge carriers possess a negative charge conductivity and are thereon referred to as negative charge carriers or electrons. Similarly, some of the charge carriers possess positive charge conductivity and are referred to as positive charge carriers or holes.

Further, the negative charge carriers among the generated charge carriers at the first junction816due to avalanche breakdown move towards the first layer804. On the other hand, the positive charge carriers among the charge carriers generated at the first junction816move towards the second layer806. At the same time, the second junction618between the fourth layer810and the fifth layer812experiences a forward bias. A forward bias is a condition when the cathode end (n type semiconductor) is coupled to a negative bias while the anode end (p type semiconductor) is coupled to a positive bias. Under the forward bias condition, negative charge carriers at the second junction818are forced to move towards the fourth layer810.

As a result, eventually, a movement of the negative charge carriers occurs from the fifth layer812towards the first layer804. Simultaneously, the positive charge carriers move from the first layer804towards the fifth layer812. While travelling from the first layer804towards the fifth layer812, some of the positive charge carriers recombine with the charge carriers of opposing charge conductivity, i.e., the negative charge carriers in each of the second layer806, third layer808, fourth layer810, and the fifth layer812. The remaining positive charge carriers move towards the fifth layer612under the influence of the voltage supply source904.

During the movement of the charge carriers between the first layer804and the fifth layer812, the heavily doped p+ third layer808enables reduction in leakage current from the transient voltage suppressor206. The leakage current is a relatively small electric current that flows through the first junction816of the semiconductor die820, when the first junction816experiences reverse biasing. In the absence of a grounding connection, the leakage current could flow from any conductive part or surface of non-conductive parts to ground if a conductive path was available (such as a human body). The heavily doped p+third layer808reduces the leakage current by preventing a plurality of charge carriers from an edge of a depletion region or within the first junction816from travelling into the fourth layer810(p−layer). The heavily doped p+layer808provides a plurality of positive charge carriers, leading to a recombination with the plurality of negative charge carriers, especially along the edges of the semiconductor die820. Thus, the heavily doped third (p+) layer808functions as a field stop layer, preventing the electric field from entering into the fourth lightly doped (p−) layer810. In this way, the third layer808prevents a generation of excess charge carrier generation in the fourth (p−) layer810which leads to a reduction in the overall leakage current of the semiconductor die820.

A crowding of an electric field at peripheries, i.e., edges of a semiconductor die820(due to sawing through semiconductor wafers to produce the semiconductor die820) may lead to additional leakage current as well as premature voltage breakdown, which adversely affects the breakdown voltage capability of the semiconductor die820. To minimize premature voltage breakdown at peripheries of the semiconductor die820, edges of the semiconductor die820are shown as beveled in order to reduce or prevent the electric field crowding at the peripheries of the semiconductor die820. The process of beveling includes a removal of semiconductor material at the edges of the wafer at a precisely controlled angle, herein shown as angle α. The beveling of the edges enhances the breakdown voltage by reducing the electric field at the edges, thereby preventing any leakage current.

The semiconductor die820described inFIG. 10is a symmetrical semiconductor die, i.e., the reverse breakdown voltage for the first junction816is same as the reverse breakdown voltage of the second junction818of the semiconductor die820. In other words, a concentration of dopants and a thickness of the second layer806is approximately equivalent to a concentration of dopants and a thickness of the fourth layer810leading to the symmetrical semiconductor die820. An operation of the semiconductor die820with a reverse polarity of the voltage supply source is now described. A reverse polarity of the voltage supply source904refers to changing the positive and negative bias of the voltage supply source. In this embodiment, the positive bias906is applied to the fifth layer812and the negative bias908is applied to the first layer804. It is to be noted that this combination of positive906and negative bias908is opposite to the combination described above where a positive bias906is connected to the first layer804and the negative bias908is connected to the fifth layer812.

In such an embodiment, however, under the effect of the biasing, the second junction818between the fourth layer810and the fifth layer812is reverse biased, and therefore, suffers an avalanche breakdown, when the semiconductor die820experiences a transient voltage surge from the voltage supply source904. A plurality of free charge carriers, including negative charge carriers as well as positive charge carriers, are generated at the second junction818due to the avalanche breakdown. The negative charge carriers thus generated move towards the fifth layer812under the influence of the positive bias906. The positive charge carriers thus generated move towards the fourth layer810.

Simultaneously, the first junction816experiences a forward bias. Hence, the negative charge carriers from the first layer804of n+type move towards the second layer806of p+type and eventually towards the fifth layer812. Some of the negative charge carriers recombine with the positive charge carriers in the second layer806, the third layer808, the fourth layer810, and the fifth layer812.

Similarly, the positive charge carriers generated at the second junction818due to the avalanche breakdown, travel towards the first layer804under the influence of the negative bias908. Some of the positive charge carriers recombine with the charge carriers of opposite charge conductivity, herein negative charge carriers, in the fourth layer810, the third layer808, the second layer806, and the first layer804. Thus, the semiconductor die820provides a low resistance path to the current flow in case of a voltage surge condition.

In the illustrated embodiment, the semiconductor die820is a symmetrical die, as described above. Therefore, even on reversing a polarity of the voltage supply source904, the second junction818experiences an avalanche breakdown at the same voltage as the first junction816. However, in case of the semiconductor die820is an asymmetrical die, the first junction816experiences a breakdown at a different voltage relative to the second junction818.

Further, consider the following scenario when the semiconductor die820is an asymmetrical semiconductor die: In a first orientation, the polarity of the voltage supply source904is such that the positive bias906is coupled to the first layer804and the negative bias908is coupled to the fifth layer812. Further, the first junction816is designed to break down at a voltage V1and the second junction818is designed to break down at a voltage V2, where V2is greater than V1. Assuming that in the presence of a voltage V, the first junction816experiences a reverse breakdown voltage V1, while the second junction818, being forward biased, conducts current, enabling the transient voltage suppressor206to provide a low resistance path for the current flow.

In a second orientation, the polarity of the voltage supply source904is reversed. In other words, the positive bias906is coupled to the fifth layer812and the negative bias908is coupled to the first layer804. Now, in the presence of voltage V, the second junction818experiences a voltage of V1which is less than the reverse breakdown voltage V2of second junction816. In this case, the transient voltage suppressor206does not provide a conduction path for the current flow. For the transient voltage suppressor206to be conducting in such a circumstance, a voltage (spike) experienced by the junction818should be greater than V1. In other words, such an orientation of the transient voltage suppressor206may be used for protection only against higher voltage transients compared to the first orientation.

The asymmetrical transient voltage suppressor(s)206are particularly helpful in scenarios when the transient voltage suppressor(s)206are required to conduct current only during a particular polarity of the voltage supply source904or conduct at different voltages under different polarities of the voltage supply source904. As noted above, under these circumstances, a second junction (other than a first junction), is designed to possess a higher breakdown voltage compared to the first junction.

FIG. 11shows a distribution of an electric field822in the semiconductor die820of the transient voltage suppressor206when the first junction816between the first layer804and the second layer806is reverse biased, and the second junction818between the fourth layer810and the fifth layer812is forward biased. The x-axis represents a thickness of each of the layers804,806,808,810,812, whereas the y-axis represents a doping concentration in the layers804,806,808,810,812. It should be noted herein that any variation in the doping concentration and the thickness in mutually adjacent layers will affect a breakdown voltage of a junction between the mutually adjacent layers. As shown in theFIG. 11, the third layer808of the p+type acts as a field stop layer by constraining an electric field to the third layer808, thereby preventing a generation of excess charge carriers in the fourth layer810and the fifth layer812.

FIG. 12shows a distribution of an electric field824in the semiconductor die820of the transient voltage suppressor206when the first junction816between the first layer804and the second layer806is forward biased and the second junction818between the fourth layer810and the fifth layer812is reverse biased. The x-axis represents a thickness of each of the layers804,806,808,810,812, whereas the y-axis represents a doping concentration in the layers804,806,808,810,812. As shown in theFIG. 12, the third layer808of the p+type acts as a field stop layer by constraining an electric field to the third layer808, thereby preventing a generation of excess charge carriers in the second layer806and the first layer804.

FIG. 13shows a transient voltage suppressor1000in accordance with another embodiment of the present invention. In the illustrated embodiment, the transient voltage suppressor1000includes a semiconductor die1220having a first layer1204, a second layer1206, a third layer1208, a fourth layer1210, a fifth layer1212, and two metal layers1202,1214. The layers1204,1206,1208,1210,1212may be constituted of any semiconductor material such as a wide band semiconductor material. Further, the first layer1204has a conductivity of n+type. The second layer1206is stacked between the first layer1204and the third layer1208and has a conductivity of p+type. The third layer1208is stacked between the second layer1206and the fourth layer1210and has a conductivity of p−type. The fourth layer1210is stacked between the third layer1208and the fifth layer1212and has a conductivity of p+type. The fifth layer1212is stacked above the fourth layer1210and has a conductivity of n+type.

The semiconductor die1220of the transient voltage suppressor1000further includes a first junction1216formed between the heavily doped n+type first layer1204and a heavily doped p+type second layer1206. A second junction1218exists between the heavily doped p+type fourth layer1210and the heavily doped n+type fifth layer1212. The semiconductor die1220may be a symmetrical device with similar breakdown voltages for both the first junction1216and the second junction1218or an asymmetrical device with different breakdown voltages for the first junction1216and the second junction1218.

In one particular embodiment, a semiconductor die is a mirror-image of the semiconductor die1220illustrated inFIG. 13. That is, the mirror-image semi-conductor die includes a first layer and a fifth layer constituted of a p+type conductivity layer, a second layer and a fourth layer constituted of an n+type conductivity layer, and a third layer constituted of a n−type conductivity layer. Similar to the semiconductor die1220, the mirror-image of the semiconductor die1220has the first layer, the second layer, the third layer, the fourth layer, and the fifth layer arranged sequentially to form a structure.

Further, an operation of the semiconductor die1220of the transient voltage suppressor1000is similar to the operation described with reference toFIG. 10. It is to be noted that an operation of the mirror-image of the semiconductor die1220may be similar to the operation of the semiconductor die1220. In particular, in the semiconductor die1220, in the presence of a voltage surge, one of the first junction1216or the second junction1218experiences a reverse bias resulting in a break down and generation of an avalanche current, whereas the other junction is forward biased.

However, in this particular embodiment, the first layer1204and the second layer1206are heavily doped n and p layers, respectively. Therefore, the first junction1216between the layers1204,1206, has a smaller width requiring a lower breakdown voltage. Similarly, the fourth layer1210and the fifth layer1212are heavily doped p and n layers respectively. Therefore, the second junction1218between the layers1210,1212, has a smaller width requiring a lower breakdown voltage.

When the suppressor1000is subjected to a reverse breakdown voltage, one of the junctions1216,1218experience an avalanche current leading to a generation of a large number of charge carriers (both positive and negative carriers). Under the influence of the biasing, the positive and negative charge carriers thus generated move in mutually opposing directions. Simultaneously, the other junction experiences a forward bias condition.

In view of these junction biasing, the charge carriers of one charge conductivity move from the first layer1204towards the fifth layer1212. While moving, these charge carriers may combine with the charge carriers of opposite charge conductivity in the intervening layers, for example, the second layer1206, the third layer1208, and the fourth layer1210, before reaching the fifth layer1212. Owing to the low breakdown voltage(s) of the junctions1216,1218, the suppressor1000provides a low resistance path for the flow of current, thus providing protection against minor voltage spikes or transients.

The third layer1208(lightly doped p layer) helps to reduce the leakage current by acting as a trap for the charge carriers. The third layer1208provides positive charge carriers for the recombination of a large number of electrons generated at the forward biased junction of the transient voltage suppressor1000. In particular, side walls of the third layer1208act as a recombination region, where a majority of negative charge carriers recombine leading to a reduction in the leakage current. The transient voltage suppressor1000described inFIG. 13is typically suitable for systems where even small voltage transients may be harmful for the operation of the system.

FIG. 14shows a plot illustrating variation of doping concentration versus layer thickness for the transient voltage suppressor1000ofFIG. 13, having a symmetrical structure. The x-axis represents a thickness of each of the layers1204,1206,1208,1210,1212. The y-axis represents a doping concentration in each of the layers1204,1206,1208,1210,1212. In the illustrated example, the first layer1204, the second layer1206, the fourth layer1210, and the fifth layer1212have the same thickness (for example, 0.5 units) whereas the third layer has an exemplary thickness of 1 unit. Further,FIG. 14shows each of the layers1204,1206,1208,1210as bars labeled as n+, p+, p−, p+, and n+respectively. A doping concentration of each layer amongst the layers1204,1206,1208,1210,1212may be determined by extrapolating a height of each bar corresponding to each layer1204,1206,1208,1210,1212on the y-axis. For example, the bars corresponding to the first layer1204and the fifth layer1212have the height h1, the bars corresponding to the second layer1206and the fourth layer1210have the height h2, and the bar corresponding to the third layer1208has a height h3. Accordingly, a doping concentration for the first layer1204and fifth layer1212is same. In one embodiment, a doping concentration of the first layer1204and the fifth layer1210is 2e19/cm3, the doping concentration of the second layer1206and the fourth layer1208is 4e18/cm3, the doping concentration of the third layer is 1e16/cm3. As evident, the doping concentrations of the second layer1206and the fourth layer1210are the same. Such a configuration with same layer thickness and doping concentration of the second layer1206and the fourth layer1210has identical breakdown voltages for the junctions between the first layer1204and the second layer1206, and between the fourth layer1210and the fifth layer1212.

Further,FIG. 15shows a plot illustrating variation of doping concentration versus layer thickness for the transient voltage suppressor1000ofFIG. 13having an asymmetrical structure. The x-axis represents a thickness of each of the layers1204,1206,1208,1210,1212. The y-axis represents a doping concentration in each of the layers1204,1206,1208,1210,1212. In the exemplary illustrated embodiment, the first layer1204and the second layer1206have the same thickness of 0.5 micrometers, the third layer1208is shown to have a thickness of 1 micrometer, the fourth layer is shown to have a thickness of 0.8 micrometers, and the fifth layer1212is shown to have a thickness of 3-4 micrometers. Similar toFIG. 14,FIG. 15shows each of the layers1204,1206,1208,1210as bars labeled as n+, p+, p−, p+, and n+respectively. A doping concentration of each layer amongst the layers1204,1206,1208,1210,1212may be determined by extrapolating a height of each bar corresponding to each layer1204,1206,1208,1210,1212on the y-axis. For example, the bars corresponding to the first layer1204and the fifth layer1212have the height h1, the bars corresponding to the second layer1206has a height h2, the bar corresponding to the third layer1208has a height h3, and the bar corresponding to the fourth layer1210has a height h4. In one embodiment, a doping concentration of the first layer1204and the fifth layer1210is 2e19/cm3, the doping concentration of the second layer1206is 4e18/cm3, the doping concentration of the third layer is 1e16/cm3, and the doping concentration of the fourth layer 4e19/cm3. Accordingly, the doping concentrations of the second layer1206and the fourth layer1210are different, as represented by the height of the respective vertical bars corresponding to the second layer1206(having a height h2) and the fourth layer1210(having a height h4). The above described configuration with one or more of a different thickness and a different doping concentrations for the second layer1206and the fourth layer1210leads to different breakdown voltages for the junctions between the first layer1204and the second layer1206, and between the fourth layer1210and the fifth layer1212.

FIG. 16shows a graph associated with determining a doping concentration of the lightly doped p layers1206,1210for the transient voltage suppressor1000(shown inFIG. 13) for determining a breakdown voltage for the respective junctions1216,1218(shown inFIG. 13) associated with these layers1206,1210.FIG. 16graphically represents relation between a concentration of dopants ND(UBD) in a second layer1206or fourth layer1210of the semiconductor die1220ofFIG. 13on the left y-axis, and a breakdown voltage [UBD] of a junction corresponding to the layers1206,1210on x-axis, and a width of the junction (or the depletion layer) [W(UBD)/10−4] for which breakdown voltage is being determined on the right y-axis. As is indicated by the graph, a doping concentration of the second layer1206or the fourth layer1210(of the lightly doped p type) of the transient voltage suppressor1000is always greater than a width of the first junction.

For the transient voltage suppressor having a semiconductor layer structure as described forFIG. 13, a doping concentration for obtaining a particular junction breakdown voltage is determined as follows:

ND(UBD)=(3×1015/UBD)4/3, where ND(UBD), represents a concentration of dopants in the second layer1206or the fourth layer1210depending upon the junction for which breakdown voltage is being determined, and UBDrepresents a breakdown voltage corresponding to the concentration of dopants. It is understood by one of ordinary skill in the art that the above equation for determining a doping concentration corresponding to a breakdown voltage is only exemplary and not limiting. Any other suitable method for determining a doping concentration relative to a breakdown voltage may be employed.

FIG. 17represent a graphical comparison of a current (I) versus voltage (V) graph for an ideal transient voltage suppressor. The x-axis represents a supply voltage across the voltage suppressor, while the y-axis represents a current flowing through the voltage suppressor in response to experiencing the supply voltage.

As shown inFIG. 17, an ideal transient voltage suppressor experiences a sharp forward bias current on reaching a forward breakdown voltage UBD(J1) at a first junction J1. Further, the ideal transient voltage suppressor experiences a sharp reverse bias current on experiencing a reverse breakdown voltage UBD(J2) at a second junction J2. As such, an ideal transient voltage suppressor is shown to have no leakage currents.

Turning now toFIG. 18, a current (I) versus voltage (V) graph for a symmetrical transient voltage suppressor in accordance with the present invention is shown. As previously described with reference toFIG. 8, a symmetrical transient voltage suppressor such as the transient voltage suppressor206has the same doping concentration and thickness for the second layer806and the fourth layer810. As shown, the I-V graph possesses almost ideal characteristics for the forward bias voltage UBD(J1) as well as at reversed bias voltage UBD(J2), where sharp avalanching curve is obtained. This is because the field stop layer of the transient voltage suppressor reduces the leakage current, thereby preventing any soft breakdown of the transient voltage suppressor. Similarly, the lightly doped p layer of the transient voltage suppressor also reduced the field crowding effect, preventing leakage current to obtain sharp avalanching current at reverse bias. Thus, the transient voltage suppressor device present more ideal I-V characteristics compared to the conventional transient voltage suppressor device. Also, because of the proposed material of the semiconductor layers as well as the layout of the semiconductor layers in the transient voltage suppressor device, these may be utilized at temperatures as high as 250 degree Celsius to 300 degree Celsius or even greater.

Turning now toFIG. 19, a current (I) versus voltage (V) graph for an asymmetrical transient voltage suppressor in accordance with the present invention is shown. Asymmetrical transient voltage suppressor such as the transient voltage suppressor1000shown inFIG. 15has a different doping concentration and thickness for the second layer806and the fourth layer810. As shown inFIG. 19, a sharp avalanching curve is obtained at the reverse breakdown voltage UBD(J2) as well as the forward breakdown voltage UBD(J1). Again, the asymmetrical transient voltage suppressor1000presents more ideal I-V characteristics compared to the conventional transient voltage suppressor.

Furthermore, the skilled artisan will recognize the interchangeability of various features from different embodiments. Similarly, the various method steps and features described, as well as other known equivalents for each such methods and feature, can be mixed and matched by one of ordinary skill in this art to construct additional systems and techniques in accordance with principles of this disclosure. Of course, it is to be understood that not necessarily all such objects or advantages described above may be achieved in accordance with any particular embodiment. Thus, for example, those skilled in the art will recognize that the systems and techniques described herein may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.