FIDUCIAL FOR AN ELECTRONIC DEVICE

A substrate for an electronic device may include one or more layers. The substrate may include a cavity defined in the substrate. The cavity may be adapted to receive a semiconductor die. The substrate may include a fiducial mark positioned proximate the cavity. The fiducial mark may be exposed on a first surface of the substrate. The fiducial mark may include a first region including a dielectric filler material. The fiducial mark may include a second region including a conductive filler material. In an example, the second region surrounds the first region. In another example, the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.

TECHNICAL FIELD

This document pertains generally, but not by way of limitation, to an electronic device including a fiducial mark.

BACKGROUND

A fiducial mark is utilized as a reference point to determine the positional relationship between a first object and a second object, such as a positional relationship between a first component of an electronic device and a second component of the electronic device.

DETAILED DESCRIPTION

The present inventors have recognized, among other things, that a problem to be solved may include determining the position of a first object (e.g., a substrate) with respect to a second object (e.g., a semiconductor die, for instance an interconnect bridge). Additionally, the present inventors have recognized, among other things, that a problem to be solved may include increasing the accuracy and precision of positioning the second object (e.g., the semiconductor die) with respect to the first object (e.g., a cavity defined in the substrate). Further, the present inventors have recognized, among other things, that a problem to be solved may include distinguishing a fiducial mark from other structures of an electronic device (e.g., a via or an electrical trace).

The present subject matter may help provide a solution to these problems, for example with a substrate for an electronic device. The substrate may include one or more layers. For instance, the one or more layers may include a dielectric material and one or more electrical traces. In another example, a cavity may be defined in the substrate. The cavity may be adapted to receive a semiconductor die.

The electronic device includes one or more fiducial marks. The fiducial marks help determine a positional relationship between components of the electronic device. For instance, the fiducial marks help position a first component of the electronic device relative to a second component of the electronic device. In an example, a semiconductor die may be positioned proximate the cavity of the substrate. For instance, the cavity may receive the semiconductor die, for example to embed the die within the substrate.

The substrate may include a fiducial exposed on a first surface of the substrate. The semiconductor die may include a fiducial mark on a first surface of the die. The fiducial mark may include a first region having a dielectric filler material. The fiducial mark may include a second region having a conductive material. In an example, the second region surrounds the first region. For example, the second region encircles the first region. In yet another example, the dielectric filler material of the first region has a lower reflectivity in comparison to the conductive material of the second region to provide a contrast between the first region and the second region. In another example, contrast between regions of the fiducial mark enhances the detectability of the fiducial mark. For instance, the contrast between the first region and the second region helps distinguish the fiducial mark from other structures of the electronic device.

This overview is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description continues and provides further information about the present patent application.

FIG.1illustrates a schematic, cross-sectional view of one example of an electronic device100, in accordance with an example of the present subject matter. The electronic device100includes a substrate110. The substrate110may include one or more layers, and the one or more layers may include a dielectric material120and electrical traces (e.g., the electrical traces210ofFIG.2). The electronic device100may include a via130, and the via130may facilitate the electrical communication between the one or more layers of the substrate110.

In some examples, the substrate110defines a cavity140in the substrate110. For example, a photoresist may be applied to the substrate110, and the photoresist may be cured. The dielectric material120may be coupled to the substrate110, and the cured photoresist may be removed from the substrate110(e.g., by dissolving the cured photoresist). The removal of the photoresist from the substrate110may create the cavity140in the substrate110. In another example, the dielectric material120is removed (e.g., ablated, for instance with a laser) and the removal of the dielectric material120from the substrate110creates the cavity140.

As shown inFIG.1, the cavity140may extend partially through the substrate110. In an example, the cavity140extends from a top surface of the substrate110, and extends into a thickness of the substrate110. For instance, the cavity140extends through the thickness of the substrate110, and additional layers (e.g., including dielectric material and electrical traces) are coupled to the substrate110. In another example, a bottom of the cavity140is defined by a conductive material. The cavity140may have a rectangular periphery, but the present subject matter is not so limited. The periphery of the cavity140may have a variety of shapes (e.g., square, circular, triangular, other polygonal shapes, or amorphous in shape).

The electronic device100may include a semiconductor die150, including but not limited to a passive die, an interconnect bridge, a logic die, a memory die, a TSV die, or the like. In an example, the semiconductor die150is coupled to a surface of the substrate110(e.g., a top surface of the substrate110). The semiconductor die150may be encapsulated in a dielectric material (e.g., the dielectric material120, or the like).

In another example, the cavity140may be adapted to (e.g., sized and shaped) to receive the semiconductor die150. In an example, the semiconductor die150is a first semiconductor die150, and the first semiconductor die150may facilitate the electrical communication of components of the electronic device100(e.g., the electrical communication between a second semiconductor die and a third semiconductor die). The semiconductor die150may be coupled to a surface (e.g., a bottom surface or wall) of the substrate110that defines a portion of the cavity140. For instance, the semiconductor die150may be positioned in the cavity140of the substrate110, and the semiconductor die150may be coupled to a bottom surface (e.g., a copper layer) that defines a portion of the cavity140. The semiconductor die150may include a semiconductor material.

As described herein, the semiconductor die150may be a first semiconductor die150and the die150may facilitate the electrical communication between components of the electronic device100(e.g., the communication between a second die and a third die). The first semiconductor die150may include die contacts160. The die contacts160may include conductive pins, pads, sockets, or the like. The die contacts160may facilitate the electrical communication of the semiconductor die150with additional structures of the electronic device (e.g., the via130or the electrical traces210shown inFIG.2).

For instance, additional layers (e.g., of the first dielectric material120and electrical traces) may be coupled to the substrate110, and the additional layers may encapsulate (e.g., enclose, surround, or the like) the semiconductor die150in the substrate110. The electrical traces may be coupled to the die contacts160, and the electrical traces may route electrical signals to and from the semiconductor die150. Additionally, the electrical traces may be coupled to a second die and a third die (or additional die), and the electrical signals may be transmitted from the second die, through the first semiconductor die150, and to the third die (or from the third die to the second die). The first semiconductor die150may electrically interconnect two or more die (e.g., the second die and the third die).

FIG.2illustrates a schematic, planar view of one example of the electronic device100, in accordance with an example of the present subject matter. As described herein, the substrate110may define the cavity140. In an example, the semiconductor die150is coupled to a surface (e.g., a top surface) of the substrate110. In another example, the semiconductor die150may be positioned in the cavity140of the substrate110, and the semiconductor die150may be coupled to the substrate110.

The electronic device100may include a surface layer200. The surface layer200may include a dielectric material (e.g., the dielectric material120shown inFIG.1, or the like). The surface layer200may include conductive material (e.g., copper, gold, aluminum, or the like). The surface layer200may be coupled to the substrate110. The surface layer200may include electrical traces210. For example, conductive material may be plated to a surface (e.g., a top surface) of the substrate110. The first dielectric material120(shown inFIG.1), may electrically isolate individual electrical traces210.

The surface layer200may define a void220in the surface layer200. For instance, a photoresist is applied to the substrate110, and the photoresist is cured (e.g., by exposure to light) and the photoresist hardens in a desired shape, including but not limited to the shape of void220. The layer200is coupled to the substrate110(e.g., by a plating operation, curing operation, or the like) and the layer200is coupled with (e.g., surrounds, or envelops) the cured photoresist. The cured photoresist is removed (e.g., with a solvent), and the void220will remain in the surface layer. A person having ordinary skill in the art will appreciate other additive operations or subtractive operations may be utilized to define the void220in the surface layer200.

The electronic device100may include one or more fiducial marks230. For example, one or more of the substrate110or the semiconductor die150may include the fiducial marks230.FIG.2shows a first fiducial mark230A exposed on a surface202of the substrate110. The surface202may be included in the layer200. In another example,FIG.2shows a second fiducial mark230B exposed on a surface204of the semiconductor die150. For instance, the second fiducial mark230B may be adjacent a perimeter edge152of the semiconductor die150. Thus, in an example, the fiducial marks230A,230B are simultaneously observable from a side (e.g., top side, or the like) of the electronic device100with the semiconductor die150received in the cavity140.

The fiducial mark230may include a filler material, including (but not limited to) the first dielectric material120(shown inFIG.1), a second dielectric material, or a conductive material. The first dielectric material and the second dielectric material may be different. The void220in the surface layer200may have various configurations (e.g., corresponding to the design of the fiducial marks shown inFIGS.3-7).

The fiducial mark230may be positioned in the void220that may be defined by the surface layer200. In an example, the surface layer200includes an exposed surface of the substrate110, and the surface layer200defines the void220in the exposed surface of the substrate110. In another example, the fiducial mark230may be optionally positioned proximate a corner240of the cavity140(e.g., in an area near the cavity140).

As described herein, the fiducial mark230may include the filler material, and the filler material may be coupled to the surface layer200of the substrate110. In an example, the filler material includes the first dielectric material120or conductive material, and the filler material is positioned in (e.g., deposited into) the void220defined in the surface layer200. For example, excess first dielectric material120may be removed from the electronic device100, and the first dielectric material120positioned in the void220is cured. The filler material positioned in the void220may be coupled to the surface layer200and/or the substrate110(e.g., by a curing operation, plating operation, or the like). In an example, the fiducial mark230includes the first dielectric material120or conductive material that is positioned in the void220.

A person having ordinary skill in the art will appreciate that other operations are possible to create the electronic device100including the fiducial mark230. For instance, the filler material may be cured (e.g., in the configurations shown inFIGS.3-6) to form the fiducial mark230, and the surface layer200may be coupled to (e.g., surround, or envelop) the fiducial mark230. Additionally, the filler material may substantially fill the void220(e.g., if the filler material does not flow to the bottom of, and completely fill, the void220).

The fiducial mark230may include one or more regions232, for example a first region232A and a second region232B. In an example, the filler material of the first region232A includes a dielectric material. The filler material of the second region232B includes a conductive material. In yet another example, the regions232enhance contrast of the fiducial mark230with respect to other structures of the electronic device100. For example, the dielectric material of the first region232A may have a lower reflectivity in comparison to the conductive material of the second region232B. In an example, the conductive material of the second region232B may reflect light with a greater intensity (e.g., have a higher reflectance) than the dielectric material120of the first region232A. In a further example, the first region232A may absorb (e.g., trap, capture, or refract) light, and the second region232B is brighter in contrast (to an observer, such as a pick and place apparatus, technician, or the like) to the first region232A. In yet another example, the fiducial mark230includes the first dielectric material120(shown inFIG.1) and the first dielectric material120absorbs more light in comparison to conductive material (e.g., copper, or the like) of the second region232B. The dissimilar reflectivity between regions232of the fiducial mark230(and the surface layer200) may help improve the contrast between the fiducial mark230and the surface layer200. In still yet another example, the surface roughness of the second region232B is lower than the surface roughness of other portions of the fiducial mark230(or the surface layer200). For instance, the surface layer200may include a conductive material, and the conductive material of the second region232B of the fiducial mark230may be polished, while the surface layer200is unaffected by the polishing operation. The dissimilar surface roughness may help improve the contrast between the fiducial mark230and the surface layer200.

Improving the contrast between the fiducial mark230and the surface layer200may help improve the detectability of the fiducial mark230(e.g., when an observer is attempting to locate the fiducial mark230included in the electronic device100). Improving the detectability of the fiducial mark230helps reduce labor associated with locating the fiducial mark230, and may help reduce the costs associated with manufacturing the electronic device100. In another example, and as discussed in greater detail herein, improving the detectability of the fiducial mark230helps improve the accuracy and precision associated with using the fiducial mark230as a reference point. For instance, the fiducial mark230may be utilized (e.g., referenced by a user or by a machine) as a reference point in a positioning operation to position the semiconductor die150in the cavity140, shown inFIGS.1and2).

In yet another example, the fiducial mark230is utilized to position (e.g., align) and couple the semiconductor die150with a surface (e.g., a top surface) of the substrate110. In still yet another example, the fiducial mark230is utilized to position (and couple) electrical components (e.g., resistors, capacitors, inductors, or the like) with respect to the substrate110. Improving the accuracy and precision associated with using the fiducial mark230may improve the performance of the electronic device100, and may help reduce the waste associated with manufacturing the electronic device100. For instance, the fiducial230helps reduce waste during manufacturing of the electronic device100, such as by reducing positional misalignment between components of the device100. Additionally, the fiducial mark230may help improve the performance of the electronic device100because the increase in accuracy and precision of positioning the semiconductor die150with respect to the substrate110allows for structures of the semiconductor die150(e.g., the die contacts160ofFIG.1) to have a tighter density (e.g., pitch, or the like) and thereby provide additional electrical communication pathways for the semiconductor die150(e.g., enhanced I/O density, or the like).

As described herein, the fiducial mark230may be utilized as a reference point. For instance, the fiducial mark230may be adapted to locate the semiconductor die150with respect to the cavity140defined in the substrate110. The fiducial mark230may help determine the geometric properties of the electronic device100. The fiducial mark230may help determine the amount of translation or rotation (or other degrees of freedom) necessary to accurately and precisely position the semiconductor die150with respect to the substrate110, for example to position the semiconductor die150in the cavity140.

The fiducial mark230may be electrically isolated form the traces210of the substrate110. For instance, the conductive material included in the fiducial mark230may refrain from electrical communication with the electrical traces210. In yet another example, the fiducial mark230refrains from electrical communication with the semiconductor die150. Accordingly, the fiducial mark230is distinguishable with respect to other structures in the electronic device100(e.g., a via, pad, or the like). For example, cross-sectioning of the substrate110would show the fiducial mark230electrically isolated from the traces250, or the like.

FIG.3illustrates a detailed schematic view at the line3-3of the electronic device ofFIG.2, including one example of the fiducial mark230, in accordance with an example of the present subject matter.FIGS.4-7show additional examples of the fiducial mark230, in accordance with examples of the present subject matter.FIG.3shows the surface layer200of the substrate110and the regions232of the fiducial mark230. The second region232B may surround (e.g., encircles, encloses, bands, bounds, encompasses, rings, or the like) the first region232A. The regions232of the fiducial mark are exposed on a surface of the substrate110(or the semiconductor die150). For example, the first region232A and the second region232B are observable on a surface of the substrate110(or on a surface of the semiconductor die150). Accordingly, the second region232B surrounds the first region232A while allowing the first region232A to be observable on a surface of the substrate110(or on a surface of the semiconductor die150).

The regions of the fiducial mark230may have a circular profile (e.g., one or more of cross-section, shape, size, dimensions, contour, radius, perimeter, circumference, outline, boundary, configuration, pattern, arrangement, thickness, or the like). For example,FIG.3shows the first region232A of the fiducial mark230may have a first circular profile304. The second region232B may have a second circular profile306(larger than the first circular profile304). The second region232B may have an annular shape. The second region232B may ring about the first region232A. In another example, a center of the first region232A may be coincident with a center of the second region232B. For instance, the second region232B may be concentrically aligned with the first region232A. The regions of the fiducial mark230may have other profiles, such as a square, polygon, cross, or amorphous in shape.

FIG.3shows the first region232A may have a first fiducial dimension300. The second region232B may have a second fiducial dimension302. In an example, the fiducial dimension corresponds to a size of a region of the fiducial mark230. For instance, the fiducial dimension may correspond to a dimension (e.g., measurement, distance, width, thickness, or the like) between a center of the fiducial mark230and a perimeter of a region of the fiducial mark230. For example, the first fiducial dimension300may correspond to a radial dimension between a center of the fiducial mark230and a perimeter of the of the first region232A. In another example, the fiducial dimension corresponds to a dimension between edges of a region of the fiducial mark. For example, 302 may correspond to a radial dimension between edges of the second region232B (e.g., a distance between an edge of the first region232A and the surface layer200).

FIGS.4-7illustrate additional examples of the fiducial mark230. For example,FIG.4shows the first region232A having a third fiducial dimension400. The first region232A having the third fiducial dimension400is larger than the first region232A having the first fiducial dimension300(shown inFIG.3). Accordingly, the size of the first region232A may vary relative to the size of the second region232B. For instance, the second region232B has a fourth fiducial dimension402inFIG.4. The fourth fiducial dimension402is less than the second fiducial dimension302. The second region232B may decrease in area in correspondence with an increase in area of the first region232A.

FIG.5illustrates yet another example of the fiducial mark230. The fiducial mark230includes the first fiducial region232A and the second fiducial region232B. In another example, the fiducial mark230may include a third fiducial region232C. For instance, the third fiducial region232C may surround the second fiducial region232B (and accordingly surround the first fiducial region232A). In an example, the filler material of the first region232A includes dielectric material. Still further, the fiducial mark230may include a fourth fiducial region232D. For instance, the filler material of the fourth fiducial region232D includes conductive material. The fourth fiducial region232D may be adjacent the surface layer200. In another example, the fourth fiducial region232D is the outermost region of the one or more regions232of the fiducial mark230.

In another example,FIG.5shows the first fiducial region232A may have a fifth fiducial dimension500. The second fiducial region232B may have a sixth fiducial dimension502. The third fiducial region232C may have a seventh fiducial dimension504. The fourth fiducial region232D may have an eighth fiducial dimension506.

FIG.6illustrates still yet another example of the fiducial mark230. As described herein, the regions232of the fiducial mark230may have varying sizes.FIG.6shows the first fiducial region232A may have a ninth fiducial dimension600. The ninth fiducial dimension600may be larger than the fifth fiducial dimension500(shown inFIG.5). Accordingly, the size of the first fiducial region232A may be larger inFIG.5than inFIG.6. The second fiducial region232B may have a tenth fiducial dimension602. The tenth fiducial dimension602may be larger than the sixth fiducial dimension502. Thus, the second fiducial region232B inFIG.6may be smaller in size than the size of the second fiducial region232B inFIG.5. The third fiducial region232C may have an eleventh fiducial dimension604. The eleventh fiducial dimension604may be larger than the seventh fiducial dimension504(shown inFIG.5). Accordingly, the third fiducial region232C inFIG.6may be larger in size than the third fiducial region shown inFIG.5. The fourth fiducial region232D may have a twelfth fiducial dimension606. The twelfth fiducial dimension606may be less than the eighth fiducial dimension506(shown inFIG.5). Thus, the fourth fiducial region232D inFIG.6may be smaller in size than the fourth fiducial region232D inFIG.5.

FIG.7illustrates another example of the substrate110. As described herein, the substrate110may include a surface layer200.FIG.7shows the surface layer200may include conductive material, such as one or more of copper, gold, or aluminum. For example, the fiducial mark230includes the first fiducial region232A, the second fiducial region232B, and the third fiducial region232C. The filler material of the third fiducial region232C may include dielectric material. The third fiducial region232C may be adjacent the conductive material of the surface layer200. The outermost region of the fiducial mark (e.g., the third fiducial region232C) may include a material dissimilar to the material of the surface layer200, such as to enhance contrast between the fiducial mark230and the surface layer200.

FIG.8illustrates a schematic view of another example of the electronic device100. As described herein, the substrate110helps transmit electrical signals between components of the electronic device100. In an example, the substrate110may facilitate electrical communication between a first package die800and a second package die802. For instance, the first package die800may transmit an electrical signal to the second package die802. The semiconductor die150may help route electrical signals between the first package die800and the second package die802.

FIG.9illustrates a system level diagram, depicting an example of an electronic device (e.g., system) including the electronic device100as described in the present disclosure.FIG.9is included to show an example of a higher level device application for the electronic device100. In one embodiment, system900includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system900is a system on a chip (SOC) system.

In one embodiment, processor910has one or more processor cores912and912N, where912N represents the Nth processor core inside processor910where N is a positive integer. In one embodiment, system900includes multiple processors including 910 and 905, where processor905has logic similar or identical to the logic of processor910. In some embodiments, processing core912includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor910has a cache memory916to cache instructions and/or data for system900. Cache memory916may be organized into a hierarchal structure including one or more levels of cache memory.

In some embodiments, processor910includes a memory controller914, which is operable to perform functions that enable the processor910to access and communicate with memory930that includes a volatile memory932and/or a non-volatile memory934. In some embodiments, processor910is coupled with memory930and chipset920. Processor910may also be coupled to a wireless antenna978to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, an interface for wireless antenna978operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

Memory930stores information and instructions to be executed by processor910. In one embodiment, memory930may also store temporary variables or other intermediate information while processor910is executing instructions. In the illustrated embodiment, chipset920connects with processor910via Point-to-Point (PtP or P-P) interfaces917and922. Chipset920enables processor910to connect to other elements in system900. In some embodiments of the example system, interfaces917and922operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In some embodiments, chipset920is operable to communicate with processor910,905N, display device940, and other devices, including a bus bridge972, a smart TV976, I/O devices974, nonvolatile memory960, a storage medium (such as one or more mass storage devices)962, a keyboard/mouse964, a network interface966, and various forms of consumer electronics977(such as a PDA, smart phone, tablet etc.), etc. In one embodiment, chipset920couples with these devices through an interface924. Chipset920may also be coupled to a wireless antenna978to communicate with any device configured to transmit and/or receive wireless signals.

Chipset920connects to display device940via interface926. Display940may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the example system, processor910and chipset920are merged into a single SOC. In addition, chipset920connects to one or more buses950and955that interconnect various system elements, such as I/O devices974, nonvolatile memory960, storage medium962, a keyboard/mouse964, and network interface966. Buses950and955may be interconnected together via a bus bridge972.

While the modules shown inFIG.9are depicted as separate blocks within the system900, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory916is depicted as a separate block within processor910, cache memory916(or selected aspects of916) can be incorporated into processor core912.

FIG.10illustrates an example of a method1000for manufacturing an electronic device, including one or more of the electronic device100described herein. In describing the method1000, reference is made to one or more components, features, functions and operations previously described herein. Where convenient, reference is made to the components, features, operations and the like with reference numerals. The reference numerals provided are exemplary and are not exclusive. For instance, components, features, functions, operations and the like described in the method1000include, but are not limited to, the corresponding numbered elements provided herein and other corresponding elements described herein (both numbered and unnumbered) as well as their equivalents.

The method1000includes at1002that a first fiducial mark230A is observed, for example by a pick and place apparatus, a technician, or the like. The first fiducial mark230A may be included in a semiconductor die150. At1004, the method1000includes observing a second fiducial mark230B. The second fiducial mark230B may be included in a substrate110. The substrate110may include a cavity140configured to receive the semiconductor die150. The method1000includes at1006aligning the first fiducial mark230A with respect to the second fiducial mark230B.

Several options for the method1000follow. For instance, aligning the first fiducial mark230A with respect to the second fiducial mark230B may include adjusting a position of the semiconductor die150relative to the substrate110. For instance, the position of the semiconductor die150may be adjusted based on a comparison of the position of the semiconductor die150with respect to the second fiducial mark230B (in this example included in the substrate110). In another example, the semiconductor die150is located within the cavity140in the substrate110.

Various Notes & Aspects

Example 1 is a substrate for an electronic device, comprising: one or more layers including a dielectric material and one or more electrical traces; a cavity defined in the substrate, wherein the cavity is adapted to receive a semiconductor die; a fiducial mark positioned proximate the cavity, and the fiducial mark is exposed on a first surface of the substrate, the fiducial mark including: a first region including a dielectric filler material; a second region including a conductive filler material, wherein the second region surrounds the first region; and wherein the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.

In Example 2, the subject matter of Example 1 optionally includes wherein: the first region has a circular profile with a first footprint; the second region has a circular profile with a second footprint; and the second region surrounds the first region such that the first footprint is within the second footprint.

In Example 3, the subject matter of any one or more of Examples 1-2 optionally include wherein the substrate includes a surface layer including a dielectric material, and the second region is adjacent the surface layer.

In Example 4, the subject matter of any one or more of Examples 1-3 optionally include wherein the first region is concentrically aligned with the second region.

In Example 5, the subject matter of any one or more of Examples 1˜4 optionally include a third region surrounding both the first region and the second region, the third region including the dielectric filler material.

In Example 6, the subject matter of Example 5 optionally includes wherein each of the first region, the second region, and the third region have a circular profile.

In Example 7, the subject matter of Example 6 optionally includes wherein: the first region has a first radial size; the second region has a second radial size; the third region has a third radial size; and the third radial size is different than the second radial size.

In Example 8, the subject matter of any one or more of Examples 5-7 optionally include a fourth region surrounding each of the first region, the second region, and the third region; and wherein the fourth region includes the conductive filler material.

In Example 9, the subject matter of any one or more of Examples 1-8 optionally include wherein the conductive filler material of the second region of the fiducial mark is electrically isolated from the one or more electrical traces of the substrate.

In Example 10, the subject matter of any one or more of Examples 1-9 optionally include the semiconductor die located in the cavity.

In Example 11, the subject matter of Example 10 optionally includes wherein the semiconductor die includes a die fiducial mark located proximate to an edge of the semiconductor die.

Example 12 is an electronic device, comprising: a semiconductor die, including: a perimeter edge; and a die fiducial mark exposed on a first surface of the die proximate to the perimeter edge of the die, wherein the die fiducial mark includes: a first die fiducial region having a circular profile, the first die fiducial region including a dielectric filler material; a second die fiducial region having a circular profile, the second die fiducial region including a conductive filler material, wherein the second region surrounds the first region; and wherein the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region; and a substrate including one or more layers, the substrate having a cavity configured to receive the semiconductor die.

In Example 13, the subject matter of any one or more of Examples 1-12 optionally include wherein: the first die fiducial region has a first footprint; the second die fiducial region has a second footprint; and the second die fiducial region surrounds the first region such that the first footprint is within the second footprint.

In Example 14, the subject matter of any one or more of Examples 12-13 optionally include a third die fiducial region surrounding both the first die fiducial region and the second die fiducial region, the third die fiducial region including the dielectric filler material.

In Example 15, the subject matter of Example 14 optionally includes wherein each of the first die fiducial region, the second die fiducial region, and the third die fiducial region have a circular profile.

In Example 16, the subject matter of Example 15 optionally includes wherein: the first die fiducial region has a first radial size; the second die fiducial region has a second radial size; the third die fiducial region has a third radial size; and the third radial size is different than the second radial size.

In Example 17, the subject matter of any one or more of Examples 14-16 optionally include a fourth die fiducial region surrounding each of the first die fiducial region, the second die fiducial region, and the third die fiducial region; and wherein the fourth die fiducial region includes the conductive filler material.

In Example 18, the subject matter of any one or more of Examples 12-17 optionally include wherein the substrate includes: a substrate fiducial mark positioned proximate the cavity, and the substrate fiducial mark is exposed on a first surface of the substrate, the fiducial mark including: a first substrate fiducial region including a dielectric filler material; a second substrate fiducial region including a conductive filler material, wherein the second substrate fiducial region surrounds the first region; and wherein the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.

In Example 19, the subject matter of Example 18 optionally includes wherein the semiconductor die is located in the cavity.

In Example 20, the subject matter of Example 19 optionally includes wherein the first surface of the substrate is aligned with the first surface of the die.

Example 21 is a method for manufacturing an electronic device, comprising: observing a first fiducial mark included in a semiconductor die; observing a second fiducial mark included in a substrate having a cavity configured to receive the semiconductor die; and aligning the first fiducial mark with respect to the second fiducial mark.

In Example 22, the subject matter of Example 21 optionally includes wherein aligning the first fiducial mark with respect to the second fiducial mark includes adjusting a position of the semiconductor die relative to the substrate.

In Example 23, the subject matter of any one or more of Examples 21-22 optionally include locating the semiconductor die within the cavity in the substrate.

In Example 24, the subject matter of Example 23 optionally includes wherein one or more of the first fiducial mark or the second fiducial mark includes: a first region including a dielectric filler material; a second region including a conductive filler material, wherein the second region surrounds the first region; and wherein the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.