Interconnect structure having reduced resistance variation and method of forming same

An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.

TECHNICAL FIELD

The subject matter disclosed herein relates to an interconnect structure of an integrated circuit (IC) having reduced resistance variation. More specifically, various aspects described herein relate to an interconnect structure of an IC that includes a hardmask layer between metal lines and has reduced resistance variation, and method of forming the same.

BACKGROUND

As integrated circuits (ICs) continue to scale downward in size, transistors and interconnects have also had to become smaller and smaller. However, in scaled down sizes such as at the 7 nanometer (nm) technology node and beyond, scaling faces the so-called “RC challenge” (R=electrical resistance, C=capacitance). While transistor speeds continue to improve with scaling, the challenge for interconnect scaling is to not become a bottleneck and lose that performance improvement. Thus, the product of resistance and capacitance (RC) needs to remain low during interconnect scaling in order to create fast chips since device speed is inversely proportional to RC.

BRIEF SUMMARY

Interconnect structures including a hardmask layer between metal lines and having reduced resistance variation, and methods of forming the same are disclosed. In a first aspect of the disclosure, an interconnect structure includes: at least two metal lines laterally spaced from one another in a dielectric layer, the at least two metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the at least two metal lines, the hardmask layer having a portion extending between the at least two metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line of the at least two metal lines.

In a second aspect of the disclosure, a method of forming an interconnect structure includes: forming a metal line layer having at least two metal lines laterally spaced from one another in a first dielectric layer; recessing the first dielectric layer to have a top surface of the first dielectric layer below a top surface of the at least two metal lines; forming a hardmask layer on the top surface of the first dielectric layer, on sidewalls of the at least two metal lines exposed above the top surface of the first dielectric layer, and on the top surface of the at least two metal lines; depositing a second dielectric layer on the hardmask layer, the second dielectric layer having a top surface substantially coplanar with a top surface of the hardmask layer located on the top surface of the at least two metal lines; removing the hardmask layer located on the top surface of the at least two metal lines; and forming at least one fully aligned via on the top surface of a given metal line of the at least two metal lines.

DETAILED DESCRIPTION

The subject matter disclosed herein relates to an interconnect structure of an integrated circuit (IC) having reduced resistance variation. More specifically, various aspects described herein relate to an interconnect structure of an IC that includes a hardmask layer between metal lines and has reduced resistance variation, and a method of forming the same.

As noted above, as conventional ICs continue to scale down (such as to the 7 nm technology node and beyond), interconnect scaling continues downward as well. However, as also noted above, one challenge for such interconnect scaling is to keep RC low so as to not hinder transistor speed improvement that comes along with scaling down. Various aspects of the disclosure include methods of forming interconnect structures which prevent degradation of resistance performance and thereby reduce variability of interconnect resistance, thus keeping interconnect RC low. In other aspects of the disclosure, interconnect structures are formed that have reduced resistance variation which in turn allows for low RC and improved device performance.

FIG. 1depicts a schematic cross-section of a partial interconnect structure including at least two metal lines110laterally spaced from one another in a first dielectric layer100. First dielectric layer100may include a first dielectric material such as, but not limited to, silicon dioxide (SiO2), a low dielectric constant (<3.9) material (“low-k material”), or an ultra-low dielectric constant (<2.5) material (“ultra-low-k material”). The low-k and ultra-low k materials may be comprised of a combination of Si, O, C, N, and H. First dielectric layer100may be formed by any suitable semiconductor fabrication process. For example, first dielectric layer100may be formed by deposition. It is understood that first dielectric layer100may be formed over a large variety of integrated circuit (IC) structures, e.g., transistors, resistors, capacitors, etc. Metal lines110and fully aligned vias1100, as described herein, may be used to electrically interconnect such IC structures.

As used herein, the term “depositing” or “deposition” may include any now known or later developed technique appropriate for deposition, including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD), high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and evaporation.

As shown in the cross-sectional view ofFIG. 1, first dielectric layer100may include two or more spaced metal lines110. Metal lines110may include a metal such as, but not limited to, copper (Cu), cobalt (Co), ruthenium (Ru) or tungsten (W). Metal lines110may be formed by any suitable semiconductor fabrication process. For example, metal lines110may be formed by forming trenches (not shown) in first dielectric layer100followed by filling of the trenches with metal by way of deposition and then planarizing a top surface thereof. Planarization refers to various processes that make a surface more planar (that is, more flat and/or smooth). Chemical-mechanical-polishing (CMP) is one currently conventional planarization process which planarizes surfaces with a combination of chemical reactions and mechanical forces. CMP uses slurry including abrasive and corrosive chemical components along with a polishing pad and retaining ring, typically of a greater diameter than the wafer. The pad and wafer are pressed together by a dynamic polishing head and held in place by a plastic retaining ring. The dynamic polishing head is rotated with different axes of rotation (that is, not concentric). This process removes material and tends to even out any “topography,” making the wafer flat and planar. Any necessary liner and/or barrier material (not shown) may also be provided at the interface of metal lines110and first dielectric layer100. The liner and barrier material may include a material such as, but not limited to, cobalt (Co), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), and titanium nitride (TiN).

FIG. 2depicts first dielectric layer100after recessing. The recessing of first dielectric layer100may be performed by any suitable semiconductor fabrication process, for example, by etching. In an embodiment wherein first dielectric layer100includes a low-k or ultra-low-k material, a form of etching called reactive-ion etching (RIE) (described below) may be preferable in order to minimize damage to first dielectric layer100. As can be seen inFIG. 2, the noted recessing results in a top surface200of first dielectric layer100being below a top surface210of metal lines110.

As used herein, “etching” generally refers to the removal of material from a substrate or structures formed on the substrate by wet or dry chemical means. In some instances, it may be desirable to selectively remove material from certain areas of the substrate. In such an instance, a mask may be used to prevent the removal of material from certain areas of the substrate. There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etching may be used to selectively dissolve a given material and leave another material relatively intact. Wet etching is typically performed with a solvent, such as an acid. Dry etching may be performed using a plasma which may produce energetic free radicals, or species neutrally charged, that react or impinge at the surface of the wafer. Neutral particles may attack the wafer from all angles, and thus, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases from a single direction, and thus, this process is highly anisotropic. A reactive-ion etch (RIE) operates under conditions intermediate between sputter etching and plasma etching and may be used to produce deep, narrow features, such as trenches.

FIG. 3depicts formation of a hardmask layer300on top surface200of first dielectric layer100, on sidewalls of metal lines110that are above top surface200, and on top surface210of metal lines110. As depicted inFIG. 3, hardmask layer300is semi-conformal in nature in that it mimics the profile of the structure thereunder but is not truly conformal since the thickness on top surface210of metal lines110is greater than the thickness on top surface200of first dielectric layer100and on sidewalls of metal lines110. Hardmask layer300may include a material such as, but not limited to, silicon nitride (SiN), silicon dioxide (SiO2), boron-doped silicon oxycarbonitride (SiOCBN), an aluminum oxide (e.g., AlO, Al2O, Al2O3), or aluminum nitride (AlN). Hardmask layer300may be formed by any suitable semiconductor fabrication process. For example, hardmask layer300may be formed by deposition. A physical vapor deposition (PVD) technique may be utilized in the deposition of hardmask layer300since it is non-conformal by its nature, or a chemical vapor deposition (CVD) technique may be utilized so long as the processing parameter(s) (e.g., pressure) are tuned for non-conformality.

FIG. 4depicts an alternate hardmask layer300embodiment toFIG. 3. In this alternate embodiment, hardmask layer300present on sidewalls of metal lines110and on top surface200of first dielectric layer100as shown inFIG. 3is removed. Such removal of hardmask layer300as depicted inFIG. 4may be accomplished by atomic layer etching wherein precise control of an etching target can be achieved. This alternative embodiment ofFIG. 4may be desirable when the k-value of hardmask layer300is higher than the k-value of first dielectric layer100, and may be even more desirable when the k-value of hardmask layer300is greater than 4.0.

FIG. 5depicts deposition of a second dielectric layer500on hardmask layer300. The deposition of second dielectric layer500may include chemical vapor deposition (CVD) or flowable chemical vapor deposition (FCVD). The deposition of second dielectric layer500may be followed by planarization (e.g., CMP), if needed, to ensure the top surface of second dielectric layer500is substantially coplanar with the top surface of hardmask layer300. Similar to the first dielectric layer100, second dielectric layer500may include a second dielectric material such as, but not limited to, silicon dioxide (SiO2), a low dielectric constant (<3.9) material (“low-k material”), or an ultra-low dielectric constant (<2.5) material (“ultra-low-k material”). The low-k and ultra-low k materials may be comprised of a combination of Si, O, C, N, and H. The second dielectric material of second dielectric layer500may be the same material as the first dielectric material of first dielectric layer100.

FIG. 6depicts selective removal of hardmask layer300portions located on top surface210of metal lines110(see also,FIG. 5). The noted removal may be performed by wet etch or dry RIE of hardmask layer300material. This removal allows for a resulting structure with recessed metal lines110wherein top surface210of metal lines110is below the top surface of second dielectric layer500. By forming the recessed metal lines110according to the disclosure, each top surface210of metal lines110are coplanar and uniformly flat which reduces the variability of interconnect resistance and capacitance. In contrast, conventional techniques of forming recessed metal lines, for instance, recessed copper lines, include directly recessing the top surface of the copper metal by wet etching. Such direct wet etching of the copper metal does not produce a uniformly flat top surface of the copper which in turn results in an undesirable variability of the ultimate interconnect resistance and capacitance and may also possibly damage the interconnect itself.

FIG. 7depicts formation of a conformal etch stop layer700. Etch stop layer700may include a material such as, but not limited to, silicon carbonitride (SiCN), nitrogen-doped silicon carbide, aluminum nitride (AlN), or an aluminum oxide (e.g., AlO, Al2O, Al2O3). Etch stop layer700may be formed by any suitable semiconductor fabrication process. For example, etch stop layer700may be formed by conformal deposition on exposed surfaces of second dielectric layer500(FIG. 6) and on each top surface210of metal lines110. Etch stop layer700may include a single layer or etch stop layer700may include multiple layers including an optional conformal dielectric cap layer (not shown).

FIG. 8depicts formation of an inter-layer dielectric (ILD)800on etch stop layer700. ILD800may be composed of any suitable low-k dielectric or isolation material, for example, SiO2or SiN, or a combination of low-k isolation/dielectric materials such as the combination of SiN and SiO2. ILD800may be formed by any suitable semiconductor fabrication process. For instance, ILD800may be formed by deposition, for example, flowable CVD. ILD800may include the same material as first dielectric layer100and/or second dielectric layer500.

FIG. 9depicts removal of one or more portions of ILD800to form one or more corresponding via openings900. More specifically and as depicted inFIG. 9, a portion of ILD800located above a given metal line110is removed and thereby forms a given via opening900over the given metal line110. As shown inFIG. 9, the removal of the portion of ILD800to form the given via opening900results in exposure of a portion of etch stop layer700that is located under the given via opening900. The removal of the one or more portions of ILD800may be performed by any suitable semiconductor fabrication process, for example, patterning a mask followed by etching, as is known in the art. Any necessary mask (not shown) may be employed to direct the etching. As shown inFIG. 9, the etching of the one or more portions of ILD800stops at etch stop layer700thereunder due to a difference in etch sensitivities between ILD800and etch stop layer700.

FIG. 10depicts etch stop layer700break-through. The exposed portions of etch stop layer700(FIG. 9) at the bottom of via openings900may be removed by wet etch or dry RIE. This removal of etch stop layer700located at the bottom of via openings900re-exposes the uniformly flat top surface210of metal line110thereunder in preparation for via formation thereover (FIG. 11). As shown inFIGS. 9 and 10, the etching of the one or more portions of ILD800is performed such that via opening900is wider than the given metal line110thereunder (FIG. 9) but does not extend into the second dielectric layer500during etch stop layer700break-through (FIG. 10).

FIG. 11depicts forming a fully aligned via (FAV)1100in each via opening900(FIG. 10). FAV1100may be formed by any suitable semiconductor fabrication process. For instance, FAV1100may be formed by deposition of a metal such as, but not limited to, copper (Cu), cobalt (Co), ruthenium (Ru) and tungsten (W). Any necessary liner and/or barrier material (not shown) may also be provided, e.g., a refractory metal liner.

As shown inFIG. 11, each FAV1100is located directly on top surface210of a given metal line110. As noted above, each top surface210of metal lines110is coplanar and uniformly flat, thus allowing for improved contact between a given metal line110and a given FAV1100which in turn allows for reduced variability of the resulting interconnect resistance and capacitance. Again, this reduced RC variability of interconnect structures of the disclosure is in contrast to conventional interconnect structure formation techniques that directly recess the top surface of the metal (e.g., Cu) lines by wet etch which fails to produce a uniformly flat top surface for the subsequent FAV formation thereon, resulting in undesirable variability of the ultimate interconnect resistance and capacitance.

In addition, and as shown inFIG. 11, each FAV1100is wider than a given metal line110thereunder but does not extend into second dielectric layer500, thus having a shape with an elevated overhang (i.e., a portion of FAV1100extending over part of second portion500). This overhang-like topography at the bottom portions of FAVs1100allow for a needed distance between a given FAV1100and an adjacent metal line110(see double headed arrow) in order to prevent electrical shorting and maintain reliability of the device. This shorting/reliability benefit is in addition to the above-described benefit of reduced variability of the interconnect resistance and capacitance of the interconnect structures of the disclosure.

FIG. 12depicts an alternate embodiment toFIG. 11. In this alternate embodiment, hardmask layer300is not present on sidewalls of metal lines110and on top surface200of first dielectric layer100as shown inFIG. 11. The alternate embodiment ofFIG. 12flows from the alternate embodiment ofFIG. 4discussed above. In other words, if the process of the disclosure as described with reference toFIGS. 5-11were performed utilizing the alternate embodiment ofFIG. 4(rather thanFIG. 3),FIG. 12would be the result thereof (rather thanFIG. 11). The alternate embodiment ofFIG. 12shares all of the above-discussed benefits with the embodiment ofFIG. 11since FAVs1100ofFIG. 12have the same overhang-like topography as FAVs1100ofFIG. 11, and since each top surface210of metal lines110inFIG. 12is coplanar and uniformly flat like that ofFIG. 11due to the same protection afforded by hardmask layer300present on each top surface210of metal lines110.