Flash memory device

A non-volatile memory device includes a substrate, an insulating layer, a fin structure, a floating gate, an inter-gate dielectric and a control gate. The insulating layer is formed on the substrate and the fin structure is formed on the insulating layer. The fin structure may include a strained layer formed on a non-strained layer.

TECHNICAL FIELD

The present invention relates to memory devices and methods of manufacturing memory devices. The present invention has particular applicability to non-volatile memory devices.

BACKGROUND ART

The escalating demands for high density and performance associated with non-volatile memory devices require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology. For example, the reduction of design features makes it difficult for the memory device to meet its expected data retention requirement, e.g., a ten year data retention requirement.

DISCLOSURE OF THE INVENTION

Implementations consistent with the present invention provide a non-volatile memory device that includes a floating gate formed over a fin structure. The fin structure may comprise a strained layer over a relaxed layer. A control gate may be formed over the floating gate, with the control gate being separated from the floating gate by a dielectric layer.

According to the present invention, the foregoing and other advantages are achieved in part by a memory device that includes a substrate, an insulating layer, a fin structure, a semiconducting layer, a dielectric layer and a control gate. The insulating layer is formed on the substrate and the fin structure is formed on the insulating layer. The fin structure includes a first portion comprising a first material and a second portion comprising a second material disposed on the first portion, where the second material is different than the first material. The semiconducting layer is formed over the fin structure and acts as a floating gate for the memory device. The dielectric layer is formed on the semiconducting layer and acts as an inter-gate dielectric for the memory device. The control gate is formed on the gate dielectric layer.

According to another aspect of the invention, a method of manufacturing a non-volatile memory device is provided. The method includes forming a fin structure on an insulating layer, where the fin structure includes a first portion and a second portion formed on the first portion. The second portion comprises a strained conductive material. The method also includes forming a floating gate over the fin structure, forming an inter-gate dielectric over the floating gate and depositing a gate material over the inter-gate dielectric. The method further includes patterning and etching the gate material to form at least one control gate.

According to another aspect of the invention, a memory device that includes a substrate, an insulating layer, a fin structure, a floating gate, a dielectric layer and a control gate is provided. The insulating layer is formed on the substrate and the fin structure is formed on the insulating layer. The fin structure includes a strained material. The floating gate is formed above the fin structure and the dielectric layer is formed on the floating gate. The dielectric layer acts as an inter-gate dielectric for the memory device. The control gate is formed on the dielectric layer.

Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.

BEST MODE FOR CARRYING OUT THE INVENTION

Implementations consistent with the present invention provide non-volatile memory devices, such as flash memory devices, and methods of manufacturing such devices. The flash memory devices may include a fin structure that includes a strained layer over a relaxed layer. A floating gate and control gate may be formed over the fin structure, separated by an inter-gate dielectric.

FIG. 1illustrates the cross-section of a semiconductor device100formed in accordance with an embodiment of the present invention. Referring toFIG. 1, semiconductor device100may include a silicon-germanium on insulator (SGOI) structure that includes a silicon-germanium substrate110, a buried oxide layer120, a silicon-germanium layer130on the buried oxide layer120and a silicon layer140formed on the silicon-germanium layer130.

Buried oxide layer120, silicon-germanium layer130and silicon layer140may be formed on substrate110in a conventional manner. In an exemplary implementation, buried oxide layer120may include a silicon oxide, such as SiO2, and may have a thickness ranging from about 1500 Å to about 3000 Å. Silicon-germanium layer130may have a thickness ranging from, for example, about 300 Å to about 500 Å. Silicon layer140may include monocrystalline or polycrystalline silicon having a thickness ranging from, for example, about 150 Å to about 250 Å. Silicon-germanium layer130and silicon layer140may be used to form a fin structure, as described in more detail below.

Silicon layer140may also be a strained layer due to lattice mismatch and silicon-germanium layer130may be a relaxed (i.e., non-strained) layer. A dielectric layer (not shown), such as a silicon nitride layer or a silicon oxide layer, may be formed over silicon layer140to act as a protective cap during subsequent etching processes.

In alternative implementations consistent with the present invention, substrate110and layer130may comprise other semiconducting materials, such as silicon or germanium, as opposed to silicon-germanium. Buried oxide layer120may also include other dielectric materials.

Referring back toFIG. 1, a photoresist material may be deposited and patterned to form a photoresist mask150for subsequent processing. The photoresist may be deposited and patterned in any conventional manner.

Semiconductor device100may then be etched. In an exemplary implementation, silicon layer140and silicon-germanium layer130may be etched in a conventional manner, with the etching terminating on buried oxide layer120, as illustrated inFIG. 2A. Referring toFIG. 2A, silicon layer140and silicon-germanium layer130have been etched to form a fin200comprising a relaxed silicon-germanium portion/layer210with a strained silicon portion/layer22bformed thereon. In an exemplary implementation, the width of fin200ranges from about 100 Å to about 1000 Å. The bandgap of strained silicon is smaller than non-strained silicon. This enables hot carriers in the subsequently formed memory device, described in more detail below, to be more easily generated and enables lower supply voltages to be used for the memory device.

After the formation of fin200, source and drain regions may be formed adjacent the respective ends of fin200. For example, in an exemplary embodiment, a layer of silicon, germanium or combination of silicon and germanium may be deposited, patterned and etched in a conventional manner to form source and drain regions. Alternatively, the silicon-germanium layer130and/or silicon layer140(FIG. 1) may be patterned and etched to form source and drain regions.FIG. 2Billustrates a top view of semiconductor100including source region230and drain region240formed adjacent fin200on buried oxide layer120, according to an exemplary embodiment of the present invention.

The photoresist mask150may be removed and a dielectric layer may then be formed on fin200. For example, a thin oxide layer310may be thermally grown on fin200, as illustrated inFIG. 3. The cross-sectional view ofFIG. 3is taken along line AA inFIG. 2B. Oxide layer310may be grown to a thickness of about 15 Å to about 30 Å and may be formed on the exposed surfaces of silicon-germanium layer210and silicon layer220. Oxide layer310may act as a tunnel oxide layer for semiconductor device100.

A conductive layer410, such as undoped polycrystalline silicon, may then be deposited over semiconductor device100, as illustrated inFIG. 4. The thickness of conductive layer410may range from about 150 Å to about 400 Å. Alternatively, conductive layer410may comprise another conductive material, such as germanium or combinations of silicon and germanium. Conductive layer410may act as a floating gate electrode for semiconductor device100.

Next, a dielectric layer510may be formed on conductive layer410. For example, a dielectric, such as SiO2, an oxide-nitride-oxide (ONO) stack or some high-K dielectric material, such as HfO2or ZrO2, may be deposited or thermally grown on layer410, as illustrated inFIG. 5. Dielectric layer510may have a thickness ranging from about 200 Å to about 800 Å and may act as an inter-gate dielectric.

A silicon layer610may then be deposited over semiconductor100, as illustrated inFIG. 6. Silicon layer610may be used as the gate material for the subsequently formed control gate electrode(s). In an exemplary implementation, silicon layer610may comprise polysilicon deposited using conventional chemical vapor deposition (CVD) to a thickness ranging from about 200 Å to about 1000 Å. Alternatively, other semiconducting materials, such as germanium or combinations of silicon and germanium, or various metals may be used as the gate material.

Semiconductor device100may then be patterned and etched to form the control gates for semiconductor device100. For example,FIG. 7illustrates a top view of semiconductor device100consistent with the present invention after the control gate electrodes are formed. As illustrated, semiconductor device100may include a double gate structure with gates710and720disposed on either side of fin200. The gate dielectric layers310and510are not shown inFIG. 7for simplicity. Gates710and720may include gate electrodes or contacts712and722formed at the respective ends of gates710and720, as illustrated inFIG. 7.

The source/drain regions230and240may then be doped. For example, n-type or p-type impurities may be implanted in source/drain regions230and240. For example, an n-type dopant, such as phosphorous, may be implanted at a dosage of about 10×1015atoms/cm2to about 10×1016atoms/cm2and an implantation energy of about 5 KeV to about 50 KeV. Alternatively, a p-type dopant, such as boron, may be implanted at similar dosages and implantation energies. The particular implantation dosages and energies may be selected based on the particular end device requirements. One of ordinary skill in this art would be able to optimize the source/drain implantation process based on the circuit requirements. In addition, sidewall spacers may optionally be formed prior to the source/drain ion implantation to control the location of the source/drain junctions based on the particular circuit requirements. Activation annealing may then be performed to activate the source/drain regions230and240.

The resulting semiconductor device100illustrated inFIG. 7includes a first gate710and a second gate720and can operate as a non-volatile memory device, such as a flash electrically erasable programmable read only memory (EEPROM). Each of gates710and720functions as control gates for the flash memory device100and layer410(FIG. 4) functions as the floating gate electrode. Programming of semiconductor device100may be accomplished by applying a bias of, for example, about 5 volts to about 15 volts to control gate710or720. For example, if the bias is applied to control gate710, electrons may tunnel from the fin200into floating gate410via oxide layer310. A similar process may occur if the bias is applied to control gate720. That is, electrons may tunnel into floating gate410.

Erasing may be accomplished by applying a bias of, for example, about 5 volts to about 15 volts to control gate710or720. During erasing, electrons may tunnel from the floating gate410into the source/drain regions230and240via oxide layer310and fin200.

Thus, in accordance with the present invention, a flash memory device is formed with a strained fin. The main channel of semiconductor device100is formed on the top portion of fin200(e.g., layer220), which is the strained silicon layer. Advantageously, the bandgap of strained silicon is smaller than non-strained silicon. This makes it easier for hot carriers to be generated. In other words, lower supply voltages may be used to make the resulting flash memory device work properly. The present invention can also be easily integrated into conventional semiconductor fabrication processing.

Other Embodiments

In other embodiments of the invention, a flash memory with a fully silicided floating gate may be formed.FIG. 8Aillustrates a semiconductor device800including a fin820with a dielectric cap830formed over a buried oxide layer810, in accordance with another embodiment consistent with the invention. Buried oxide layer810may be formed on a substrate (not shown). The fin820may comprise polycrystalline silicon, germanium or silicon-germanium.

After the fin structure820is formed, an oxide may be deposited or thermally grown on the side surfaces of fin820. For example, an oxide material840may be formed on the exposed side surfaces of fin820, as illustrated inFIG. 8B. Next, a semiconducting material850, such as polycrystalline silicon, may be formed over the fin structure820, as illustrated inFIG. 8B. Semiconducting layer850may function as a floating gate electrode for semiconductor device800.

A metal layer, such as titanium, may be deposited over semiconducting layer850, followed by a thermal annealing to turn the semiconducting material into metal-silicide layer860, as illustrated inFIG. 8C. Metal-silicide layer860may be used to form the floating gate for semiconductor device800and may be fully silicided. That is, metal-silicide layer860may be silicided throughout to buried oxide layer810.

An intergate dielectric870may be formed over layer860, followed by the formation of a control gate layer880. Semiconductor800may then be patterned and etched to form control gates. The resulting semiconductor device800may include one or more control gates with a fully silicided floating gate.

In another exemplary embodiment, a dual gate flash memory device may be formed. In this embodiment, a semiconductor device900that includes fins920and925, separated by silicon oxide structure930may be formed on buried oxide layer910, as illustrated inFIG. 9A. Buried oxide layer910may be formed on a substrate (not shown). Fins920and925may be formed by forming amorphous silicon spacers adjacent oxide structure930followed by a metal-induced crystallization (MIC) process using, for example, nickel. For example, nickel may be deposited on the amorphous silicon spacers followed by a thermal annealing to convert the amorphous silicon into a crystalline silicon.

An oxide layer935may be formed on the exposed surfaces of fins920and925, as illustrated inFIG. 9B. Next, a floating gate layer940may be formed over fins920and925, as also illustrated inFIG. 9B. The floating gate layer940may include, for example, polysilicon.

An intergate dielectric layer950may be formed over floating gate layer940, followed by the formation of control gate layer960, as illustrated inFIG. 9C. Source/drain regions may be formed at the respective ends of fins920and925. Semiconductor device900may then be patterned and etched to form two control gates. The resulting semiconductor device900includes a dual gate structure with two gates and two fins.

In the previous descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the present invention. However, the present invention can be practiced without resorting to the specific details set forth herein. In other instances, well known processing structures have not been described in detail, in order not to unnecessarily obscure the thrust of the present invention.

The dielectric and conductive layers used in manufacturing a semiconductor device in accordance with the present invention can be deposited by conventional deposition techniques. For example, metallization techniques, such as various types of CVD processes, including low pressure CVD (LPCVD) and enhanced CVD (ECVD) can be employed.

The present invention is applicable in the manufacturing of semiconductor devices and particularly in FinFET memory devices with design features of 100 nm and below. The present invention is applicable to the formation of any of various types of semiconductor devices, and hence, details have not been set forth in order to avoid obscuring the thrust of the present invention. In practicing the present invention, conventional photolithographic and etching techniques are employed and, hence, the details of such techniques have not been set forth herein in detail. In addition, while series of processes for forming the semiconductor devices consistent with the present invention have been described, it should be understood that the order of the process steps may be varied in other implementations consistent with the present invention.

Only the preferred embodiments of the invention and a few examples of its versatility are shown and described in the present disclosure. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of modifications within the scope of the inventive concept as expressed herein.