Frequency synthesis with low resolution rational division

A method is provided for synthesizing signal frequencies using low resolution rational division. A reference frequency value and synthesized frequency value are accepted. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (n) and an integer value denominator (d) are determined, with n/d=I(N/D)=I+N/D=(I+1)−(D−N)/D), and where N/D<1. An accumulator creates a sum of (D−N) and a count from a previous cycle, and creates a difference between the sum and the denominator. The sum is compared with the denominator, and a first carry bit is generated. The complement of the first carry bit is added to a first binary sequence, and the first binary sequence is used to generate a k-bit quotient. The k-bit quotient is subtracted from (I+1) to generate a divisor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention generally relates to a phase-locked loop (PLL) frequency synthesis system and, more particularly, to a frequency synthesis, low resolution, rational number frequency division system, such as might be used in a PLL.

2. Description of the Related Art

Conventional fractional-N frequency synthesizers use fractional number decimal values in their PLL architectures. Even synthesizers that are conventionally referred to as “rational” frequency synthesizers operate by converting a rational number, with an integer numerator and integer denominator, into resolvable or approximated fractional numbers. These frequency synthesizers do not perform well because of the inherent fractional spurs that are generated in response to the lack of resolution of the number of bits representing the divisor in the feedback path of the frequency synthesizer.

FIG. 1is a schematic block diagram depicting an accumulator circuit capable of performing a division operation (prior art). As noted in “A Pipelined Noise Shaping Coder for Fractional-N Frequency Synthesis”, by Kozak et al., IEEE Trans. on Instrumentation and Measurement, Vol. 50, No. 5, October 2001, the depicted 4thorder device can be used to determine a division ratio using an integer sequence.

The carry outs from the 4 accumulators are cascaded to accumulate the fractional number. The carry outs are combined to reduce quantization noise by adding their contributions are follows:

where n is equal to a current time, and (n−1) is the previous time, Cx[n] is equal to a current value, and Cx[n−1] is equal to a previous value.

FIG. 2shows the contributions made by the accumulator depicted inFIG. 1with respect to order (prior art). A fractional number or fraction is a number that expresses a ratio of a numerator divided by a denominator. Some fractional numbers are rational—meaning that the numerator and denominator are both integers. With an irrational number, either the numerator or denominator is not an integer (e.g., n). Some rational numbers cannot be resolved (e.g., 10/3), while other rational numbers may only be resolved using a large number of decimal (or bit) places. In these cases, or if the fractional number is irrational, a long-term mean of the integer sequence must be used as an approximation.

The above-mentioned resolution problems are addressed with the use of a flexible accumulator, as described in parent application Ser. No. 11/954,325. The flexible accumulator is capable of performing rational division, or fractional division if the fraction cannot be sufficiently resolved, or if the fraction is irrational. The determination of whether a fraction is a rational number may be trivial in a system that transmits at a single frequency, especially if the user is permitted to select a convenient reference clock frequency. However, modern communication systems are expected to work at a number of different synthesized frequencies using a single reference clock. Further, the systems must be easily reprogrammable for different synthesized frequencies, without changing the single reference clock frequency.

While it may be possible to resolve almost any fraction using rational division, practically, there are limits to the size of registers. That is, given the number of bit positions carried in a register, or series or registers, the numerator of some fractions may be resolved with more bits than there are bit positions. In that case, even a rational division system must truncate bits or make approximations, which result in PLL frequency jitter.

It would be advantageous if a means existed for determining a divisor in response to knowing the reference clock frequency and the desired synthesized frequency value. It would be advantageous if this means could determine if the divisor is a rational number. Further, it would be advantageous if the means could calculate the divisor in the form of a fraction that can be input into a flexible accumulator. Finally, it would be advantageous if a means existing for resolving rational division numerators with a minimum number of bits.

SUMMARY OF THE INVENTION

In frequency synthesis applications, there is often a need to use a single reference clock frequency to create multiple output frequencies, where the ratio between output frequency and reference frequency includes a fractional number. The present invention accumulator permits the use of a true rational number as the dividend and divisor, to avoid the use of approximations when the rational number can only be resolved (forming a repeating sequence) using a large number of bit places. The system provides a solution to PLL frequency synthesis by calculating the divisor needed for utilizing these flexible accumulators to perform either rational or fractional division in the feedback path of the PLL. The system disclosed herein also compares the number of bits in the numerator calculated for rational division to a threshold. If the threshold is exceeded, the system uses complementing functions to reduce the bit resolution needed to achieve the identical result.

Accordingly, a method is provided for synthesizing signal frequencies using low resolution rational division in a frequency synthesis device. The frequency synthesis device accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (n) and an integer value denominator (d) are determined. The ratio of n/d is reduced to an integer (I) and a ratio of N/D, where n/d=I(N/D)=I+N/D=(I+1)−(D−N)/D), and where N/D<1. In a low resolution (complement) mode, a first flexible accumulator creates a binary first sum of (D−N) and a binary first count from a previous cycle, and creates a binary first difference between the first sum and the denominator. The first sum is compared with the denominator, and in response to the comparing, a first carry bit is generated. In the low resolution mode, the complement of the first carry bit is added to a first binary sequence, and the first binary sequence is used to generate a k-bit quotient. In the low resolution mode the k-bit quotient is subtracted from (I+1) to generate a divisor.

Initially, a resolution threshold of X bits is established. The steps of creating the first sum of (D−N) and the first count, adding the complement of the first carry bit, and subtracting the k-bit quotient from (I+1) are performed if N is resolved with greater than X bits. Alternatively, if N is resolved with X or fewer bits, a binary first sum of N and the binary first count from the previous cycle is created, the first carry bit is added to a first binary sequence, and the k-bit quotient is added to I to generate the divisor.

Additional details of the above-described method and frequency synthesis system for low resolution rational division are presented below.

DETAILED DESCRIPTION

Various embodiments will be presented in terms of systems that may include a number of components, modules, and the like. It is to be understood and appreciated that the various systems may include additional components, modules, etc. and/or may not include all of the components, modules etc. discussed in connection with the figures. A combination of these approaches may also be used.

FIG. 3is a schematic block diagram depicting a system for synthesizing signal frequencies using rational division. The system100comprises a calculator102having an input on line104to accept a reference frequency value and an input on line106to accept a synthesized frequency value. The calculator102divides the synthesized frequency value by the reference frequency value, and determines an integer value numerator (dp) and an integer value denominator (dq). The calculator102reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q<1 (decimal). The calculator102supplies N(p/q), where p is a numerator and q is a denominator, at an output on line108. A flexible accumulator module110has an input on line108to accept N(p/q) and an output on line112to supply a divisor. For example, the calculator102may supply an n-bit binary numerator and an (n+1)-bit binary denominator. The divisor may be stored in a tangible memory medium (e.g., random access memory (RAM) or non-volatile memory) for subsequent use, as described below. Note: in the context ofFIGS. 10 through 13described below, N(p/q)=I(N/D).

FIG. 4is a schematic block diagram depicting the system ofFIG. 3is the context of a phase-locked loop (PLL)200. The PLL200includes a phase/frequency detector (PFD)202, a frequency synthesizer204, and a feedback loop divider206. Typically, a PLL may also include a loop filer and charge pump207. The PFD202accepts a reference signal on line208having a frequency equal to the reference frequency value. The frequency synthesizer204generates a synthesized signal on line210having a frequency equal to the synthesized frequency value. The flexible accumulator module110sums N with a k-bit quotient, creates the divisor, and supplies the divisor to the feedback loop divider206on line112.

FIG. 5is a schematic block diagram depicting a first flexible accumulator of the flexible accumulator module. A flexible accumulator is capable of either rational or fractional division. As explained in more detail below, rational division relies upon the use of a numerator (dividend) and a denominator (divisor) that are used to form a true rational number. That is, the numerator and denominator are integer inputs to the flexible accumulator. Alternately stated, the input need not be a quotient derived from a numerator and denominator. The first flexible accumulator302includes a first summer304having an input on line306to accept a binary numerator (p). Summer304has an input on line308to accept a binary first count from a previous cycle and an output on line310to supply a binary first sum of the numerator and the first count.

A first subtractor312has an input on line314to accept a binary denominator (q), an input on line310to accept the first sum, and an output on line316to supply a binary first difference between the first sum and the denominator. Note: the numerator (p) and denominator (q) on lines306and314, respectively, are components of the information supplied by the calculator on line108. A first comparator318has an input on line310to accept the first sum, an input on line314to accept the denominator, and an output on line320to supply a first comparator signal. A first multiplexer (MUX)322has an input to accept carry bits. A “1” carry bit is supplied on line324and a “0” carry bit is supplied on line326. The MUX322has a control input on line320to accept the first comparator signal, and an output on line328to supply a first carry bit in response to the first comparator signal.

More explicitly, the first MUX322supplies a binary “1” first carry bit on line328if the first comparator signal on line320indicates that the first sum is greater than the denominator. The MUX322supplies a binary “0” first carry bit if the first comparator signal indicates that the first sum is less than or equal to the denominator. The first MUX322has an input on line310to accept the first sum, an input on line316to accept the first difference, and an output on line330to supply the first count in response to the comparator signal. Note: the first count from first MUX322on line330becomes the first count from a subsequent cycle on line308after passing through clocked register or delay circuit332. As explained in more detail below, line308may also connected as an output port (count) to another, higher order flexible accumulator.

The first MUX322supplies the first difference as the first count on line308for the subsequent cycle if the first comparator signal indicates that the first sum is greater than the denominator. The first MUX322supplies the first sum as the first count in the subsequent cycle if the first comparator signal indicates that first sum is less than or equal to the denominator. Alternately but not shown, the accumulator may be comprised of two MUX devices, one for selecting the carry bit and one for selecting the first count.

In one aspect, the first summer accepts an n-bit binary numerator on line306, an n-bit first count on line308from the previous cycle, and supplies an (n+1)-bit first sum on line310. The first subtractor312accepts an (n+1)-bit binary denominator on line314and supplies an n-bit first difference on line316.

Typically, first summer304accepts the numerator with a value, and the first subtractor312accepts the denominator with a value larger than the numerator value. In one aspect, the combination of the numerator and denominator form a rational number. That is, both the numerator and denominator are integers. However, the numerator and denominator need not necessarily form a rational number. Alternately expressed, the first summer304may accept an n-bit numerator that is a repeating sequence of binary values, or the numerator may be the most significant bits of a non-repeating sequence. The non-repeating sequence may be represented by r, an irrational number or a rational number that cannot be resolved (does not repeat) within a span of n bits. In this aspect, the first subtractor312accepts an (n+1)-bit denominator with a value equal to decimal 2(n+1). Additional details of the flexible accumulator module can be found in parent application Ser. No. 11/954,325.

FIG. 6is a schematic block diagram depicting the flexible accumulator module as a plurality of series-connected flexible accumulators. Generally, the flexible accumulator module generates a binary sequence from each flexible accumulator and uses a plurality of binary sequences to generate the k-bit quotient.

A quotientizer424has an input on line328to accept the first binary sequence, an input on line422to accept the second binary sequence, and an output on line426to supply a k-bit quotient generated from the first and second binary sequences. In total, the flexible accumulator module110comprises m flexible accumulators, including an (m−1)th accumulator440and an mth accumulator436. In this example, m=4. However, the module110is not limited to any particular number of flexible accumulators. Thus, the quotientizer has inputs328,422,432, and434to accept m=4 binary sequences and the output426supplies a k-bit quotient generated from the m binary sequences. In one aspect, the quotientizer424derives the quotient as shown inFIGS. 1 and 2, and as explained below. Circuit438sums the k-bit quotient on line426with the integer N to supply the divisor on line112.

A fourth order system, using four series-connected accumulators has been depicted as an example. However, it should be understood that the system is not limited to any particular number of accumulators. Although the above-described values have been defined as binary values, the system could alternately be explained in the context of hexadecimal or decimal numbers.

FIG. 7is a schematic block diagram depicting the quotientizer ofFIG. 6in greater detail. Returning to the calculation of the quotient, the number of bits required from each contribution block is different. FromFIG. 2it can see that each order requires a different number of bits. For example, the first contribution (contribution 1) has only two values: 0 and 1. So, only 1 bit is needed. There is no need for a sign bit, as the value is always positive. The second contribution has possible 4 values: −1, 0, 1, and 2. So, 3 bits are needed, including 1 sign bit. The third contribution has 7 values: −3 to 4. So, 4 bits are required, including 1 sign bit. The fourth contribution has 15 values: −7 to 8. So, 5 bits are required, including 1 sign bit.

To generalize for “k” (the k-bit quotient), Pascal's formula may be used to explain how many bits is necessary for each contribution (or order). For an m-order calculator, there are m flexible accumulators and in binary sequences. Each binary sequence (or carry bit) is connected to the input of one of the m sequences of shift registers. Thus, there are m signals combined from the m shift register sequences, corresponding to the m-binary sequences (or m-th carry bit) found using Pascal's formula. A 4-order calculator is shown inFIG. 7, with 4 shift register (delay) sequences, with each shift register sequence including 4 shift registers.

As a simplified alternative, each contribution may be comprised of the same number of bits, k, which is the total contribution (or order) for all contributions. These k-bit contributions are 2 complement numbers. InFIG. 2, k is equal to 5 bits [4:0].

The accumulator does not generate a sign bit. However, the carry outs from the accumulators are modulated in the calculator and the sign bit is generated. For example, the 2ndorder contribution=c2[n]−c2[n−1]. If c2[n]=0 and c2[n−1]=1, then the 2ndorder contribution=0-1=−1. Similarly, the third order contribution=c3[n]−2c3[n−1]+c3[n−2]. If c3[n]=0, c3[n−1]=1, and c3[n−2]=0, then the 3rdorder contribution=0−2×1+0=−2. For the 4thorder contribution=c4[n]−3c4[n−1]+3c4[n−2]−c4[n−3]. If c4[n]=0, c4[n−1]=1, c4[n−2]=0, and c4[n−3]=1, then the 4thorder contribution=0−3×1+3×0−1=−4. These contributions are added together in the “order sum circuit”502on the basis of order, and the order is chosen using MUX504and the select signal on line500.FIG. 7depicts one device and method for generating a quotient from accumulator carry bits. However, the system ofFIG. 6might also be enabled using a quotientizer that manipulates the accumulator carry bits in an alternate methodology.

Returning toFIG. 4, in one aspect the calculator102defines a resolution limit of j radix places, sets q=dq, and determines p. The calculator102supplies p and q to a flexible accumulator module110enabled for rational division when p can be represented as an integer using j, or less, radix places. Alternately, the calculator102supplies N(r/q) to a flexible accumulator module enabled for fractional division, where r is a non-resolvable number, when p cannot be represented as an integer using j radix places. When enabled for fractional division, r is supplied as the “numerator” on line306(seeFIG. 5). Then, the “denominator” on line314is represented as an integer with a value larger than the fractional number. For example, the fractional number of line306may be an unresolved 31-bit binary number and the integer on line314may be a 32-bit number where the highest order radix place is “1” and all the lower orders are “0”. Alternately stated, r may be a 31-bit non-resolvable numerator, and q a 32-bit denominator with a value equal to decimal 232. In one aspect, r is “rounded-off” to a resolvable value.

In one aspect, the PLL200ofFIG. 4includes a feedforward divider212to accept the synthesized signal on line210and an output on line214to supply an output signal having a frequency=(synthesized signal frequency)/M. In this aspect, the flexible accumulator module110creates the divisor by summing N, the k-bit quotient, and M. Likewise, the calculator102reduces to ratio M(dp/dq)=N(p/q)).

FIG. 8is a schematic block diagram depicting the feedback loop divider ofFIG. 4is greater detail. The feedback loop divider206includes a high-speed division module800and a low-speed division module802. The high-speed module800includes a divider804having an input on line210to accept the synthesized signal and an output on line806to supply a first clock signal having a frequency equal to the (synthesized signal frequency)/J. A phase module808has an input on line806to accept the first clock and an output on lines810athrough810nto supply a plurality of phase outputs, each having the first clock frequency. Typically, the phase module808generates a first clock with a first number of equally-spaced phase outputs. For example, n may be equal to 8, meaning that 8 first clock signals are supplied, offset from the nearest adjacent phase by 45 degrees. A phase selection multiplexer812has an input on lines810a-810nto accept the plurality of first clock phase outputs, an input on line814to accept a control signal for selecting a first clock signal phase, and an output on line816to supply a prescalar clock with a frequency equal to the (synthesized signal frequency)/R, where R=J·S.

A daisy-chain register controller818has an input on line820to accept the pre-divisor value R and an output on line814to supply the control signal for selecting the first clock phase outputs. A low-speed module822has an input on line816to accept the prescalar clock and an output on line216to supply a divided prescalar clock with a frequency equal to the (divisor/R). A scaler822accepts the divisor on line112, supplies the R value of line820, and supplies division information to the low speed divider802on line824. Returning briefly toFIG. 4, the PFD202compares the divided prescalar clock frequency on line216to the reference clock frequency and generates a synthesized signal correction voltage on line218. In some aspects, the divided prescalar clock signal on line216is feedback to the flexible accumulator module110.

FIG. 9is a block diagram depicting the daisy-chain controller ofFIG. 8in greater detail. The daisy-chain register controller818accepts the prescalar clock on line816as a clock signal to registers900through914having outputs connected in a daisy-chain. The controller818generates a sequence of register output pulses814athrough814hin response to the clock signals, and uses the generated register output pulses to select the first clock phase outputs.

The daisy-chain register controller818iteratively selects sequences of register output pulses until a first pattern of register output pulses is generated. Then, the phase selection multiplexer (816, seeFIG. 8) supplies phase output pulses having a non-varying first period, generating a prescalar clock frequency equal to the (first clock frequency)·S, where S is either an integer or non-integer number. Additional details of the high speed divider and daisy-chain controller may be found in parent application Ser. No. 11/717,261.

FIG. 10is a schematic block diagram of a device for synthesizing signal frequencies using low resolution rational division. The device1000comprises a calculator module or calculator102having inputs to accept a reference frequency value on line104and a synthesized frequency value on line106. The calculator module102divides the synthesized frequency value by the reference frequency value and determines an integer value numerator (n) and an integer value denominator (d). The calculator module102reduces the ratio of n/d to an integer (I) and a ratio of N/D, where n/d=I(N/D)=I+N/D=(I+1)−(D−N)/D), and where N/D<1. The calculator module102has an output on line108to supply a low resolution ratio and the integer. More explicitly, line108is separated into different lines, with the numerator supplied on line306, the denominator on line314, and the integer on line1003. As explained in more detail below, the numerator on line306may either be N, or if the resolution of N is too great, (D−N). The calculator module102also has an output to supply a complement mode (or non-complement mode) signal on line1004.

A first flexible accumulator302has an input on lines306and314to accept the low resolution ratio and an input on line1004to accept the complement mode signal. In the low resolution or complement mode, the first flexible accumulator302creates a binary first sum on line310, of (D−N) on line306(the numerator) and a binary first count from a previous cycle on line308. The first flexible accumulator creates a binary first difference on line316between the first sum on line310and the denominator on line314. Comparator318compares the first sum on line310with the denominator on line314, and a first carry bit is generated in response to the comparing. In response to the complement mode signal on line1004, the complement of the first carry bit is added to a first binary sequence on line328. A quotientizer424has an input on line328to accept the first binary sequence and an output on line426to supply a k-bit quotient.

A complement summing module1006has an input on line426to accept the k-bit quotient, an input on line1003to accept the integer, and an input on line1004to accept the complement mode signal. The complement summing module1006subtracts the k-bit quotient from (I+1) to supply a divisor at an output on line112, in response to the complement mode signal on line1004.

In one aspect, the calculator module102has an input on line1008to accept a resolution signal for establishing a resolution threshold of X bits. The calculator module102supplies the complement mode signal on line1004in response to the numerator being resolved with greater than X bits. In contrast, the calculator module102supplies a non-complement mode signal on line1004in response to the numerator being resolved with X, or fewer bits. In the non-complement mode, the low resolution ratio is N instead of (D−N). That is, N is the numerator instead of (D−N). The first flexible accumulator302creates a binary first sum on line310of N (line306) and the binary first count from a previous cycle on line308, and acids the first carry bit to the first binary sequence on line328in response to the non-complement signal. The complement summing module1006adds the k-bit quotient on line426to I (line1003), to generate the divisor on line112, in response to the non-complement signal. In the non-complement mode, the low resolution rational division device1000operates essential the same as the system described inFIG. 6, above.

FIG. 11is a schematic block diagram of a phase-locked loop (PLL) using the low resolution rational decision device1000ofFIG. 10. The PLL1100includes a phase/frequency detector (PFD)202, frequency synthesizer204, and feedback loop divider206. The PFD202accepts a reference signal on line208having a frequency equal to the reference frequency value. The frequency synthesizer204generates a synthesized signal on line210having a frequency nominally equal to the synthesized frequency value on line106. The feedback loop divider206has an input on line210to accept the synthesized signal and an input on line112to accept the divisor. The feedback loop divider206divides the synthesizer signal on line210by the divisor on line112(I+N/D=(I+1)−(D−N)/D) to supply a clock signal on line216. The PFD202compares the clock signal frequency to the reference frequency on line208, and in response to the comparison, locks the synthesizer signal on line210to the reference signal on line208.

Returning toFIG. 10, the first flexible accumulator302includes a first summer304having an input to accept a binary numerator (N or (D−N)), an input on line308to accept the first count from a previous cycle, and an output on line310to supply the first sum of the numerator and the first count. A first subtractor312has an input on line314to accept a binary denominator, and input on line310to accept the first sum, and an output on line316to supply the first difference between the first sum and the denominator. A first comparator318has an input on line310to accept the first sum, an input on line314to accept the denominator, and an output on line320to supply a first comparator signal. A first multiplexer (MUX)322has an input to accept carry bits (“0” on line324and “1” on line326). a control input on line320to accept the first comparator signal, and an output on line1010to supply the first carry bit in response to the first comparator signal. A second MUX1012has an input on line1010to accept the first carry bit, an input on line1014to accept the complement of the first carry bit, and a control input on line1004to accept the complement mode (or non-complement mode) signal. The second MUX1012adds the complement of the first carry bit to the first binary sequence on line328in response to a complement mode signal on line1004, or adds the first carry bit to the first binary sequence in response to the non-complement signal on line1004.

As in the first flexible accumulator described above in the explanation ofFIG. 5, the first flexible accumulator302generates a binary “1” first carry bit if the first sum is greater than the denominator, or generates a binary “0” first carry bit if the first sum is less than or equal to the denominator. The first flexible accumulator302uses the first difference as the first count if the first sum is greater than the denominator, or uses the first sum as the first count if the first sum is less than or equal to the denominator.

The calculator module102generates an n-bit binary numerator on line306and an (n+1)-bit binary denominator on line314. The n-bit numerator (N or (D−N)) is resolved with X or fewer bits. The first flexible accumulator302creates an (n+1)-bit first sum of the numerator on line310, an n-bit first count from the previous cycle on line308, and an n-bit first difference on line316.

Typically, the device1000includes a plurality of flexible accumulators. Shown is a chain of (m−1) flexible accumulators400,436, and440, linked to the first flexible accumulator302. “m” is a variable integer not limited to any particular value. Each ith flexible accumulator in the chain accepts an (ith−1) count from a previous cycle and an ith count from the previous cycle. Each ith flexible accumulator creates a binary ith sum of the (ith−1) count and the ith count, creates a binary ith difference between ith sum and the denominator, and compares the ith sum with the denominator. If the ith sum is greater than the denominator, a binary “1” ith carry bit is generated and the ith difference is used as the ith count for a subsequent cycle. If the ith sum is less than or equal to the denominator, a binary “0” ith carry bit is generated and the ith sum is used as the ith count for the subsequent cycle. Finally, either the ith carry bit or the complement of the ith carry bit is added to the ith binary sequence, depending upon whether a complement mode or non-complement mode signal is received. The quotientizer424accepts m iteratively generated binary sequences and uses the m binary sequences to generate the k-bit quotient.

Although the above-described systems have been depicted as a combination of connected hardware elements, some aspects parts of the system may be enabled using software instructions stored in memory that are called and performed by a processor or logic-coded state machine device (not shown).

Functional Description

The low resolution rational division device described above is a type of Sigma-Delta modulator, and can be described as:
ΣΔ[I,N,D], withN<D

where I: Integer part, N: Numerator part, and D: Denominator. In combination with reference frequency fr, an output frequency, focan be generated as follows:

If the operation produces

and a Complement Sigma-Delta Modulator can be defined as:
ΣΔ[(1+I),(D−N),D]

When the Integer part is (I+1), the Nominator part is (D−N), the Denominator part is D, and when the complement mode signal (C) is asserted, then the Complement Sigma-Delta Modulator can be denoted as:
CΣΔ[I,N,D]=ΣΔ[(1+I),(D−N),D]

Therefore, the Complement Sigma-Delta Modulator, as described above inFIG. 10, can be programmed to perform the same function as the system described inFIG. 6by deasserting the complement mode signal.

FIG. 12is a more detailed depiction of the complement summing module ofFIG. 10. A summing module1210accepts the integer (I) on line1003, sums integer (I) with “1”, and supplies the sum (I+1) on line1212. MUX1214selects between line1212(I+1) and line1003(I) in response to the complement mode signal on line1004, and supplies the output on line1216. Summing module1200accepts the integer selection on line1216, and the k-bit quotient on line426, and supplies a sum of the 2 inputs on line1202. A subtraction module1204accepts the integer selection on line1216, and the k-bit quotient on line426, and supplies a difference the 2 inputs on line1206. MUX1208accepts the sum and difference and supplies one of the 2 inputs as the divisor on line112, in response to the complement mode signal on line1004.

Below is an example calculation.

Assuming that I=62, N=613, D=617, and X (Nmax)=512.

Since N>X, the complement operation is required.

Here, the numerator (D−N) is 4, which is less than 512 (X), and
ΣΔ[62,613,617]=CΣΔ[63,4,617].

FIGS. 13A and 13Bare flowcharts illustrating a method for synthesizing signal frequencies using low resolution rational division in a frequency synthesis device. Although the method is depicted as a sequence of numbered steps for clarity, the numbering does not necessarily dictate the order of the steps. It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of maintaining a strict order of sequence. Generally, however, the steps are performed in numerical order. The method starts at Step1300.

Step1302accepts a reference frequency value. Step1304accepts a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, Step1306determines an integer value numerator (n) and an integer value denominator (d). Step1308reduces the ratio of n/d to an integer (I) and a ratio of N/D, where n/d=I(N/D)=I+N/D=(I+1)−(D−N)/D), and where N/D<1. In a first flexible accumulator, Step1310creates a binary first sum of (D−N) and a binary first count from a previous cycle in a low resolution mode. Step1312creates a binary first difference between the first sum and the denominator. Step1314compares the first sum with the denominator. In response to the comparing, Step1316generates a first carry bit. In the low resolution mode, Step1318adds the complement of the first carry bit to a first binary sequence. Step1320uses the first binary sequence to generate a k-bit quotient, and Step1322subtracts the k-bit quotient from (I+1), in the low resolution mode, to generate a divisor.

Initially, the method may begin by establishing a resolution threshold of X bits (Nmax) in Step1301. Then, Step1310sums (D−N) with the first count, Step1318adds the complement of the first carry bit to the first binary sequence, and Step1320subtracts the k-bit quotient from (I+1) if N is resolved with greater than X bits. Alternatively, if N is resolved with X or fewer bits, Step1311creates a binary first sum of N and the binary first count from the previous cycle, Step1319aadds the first carry bit to a first binary sequence, and Step1321adds the k-bit quotient to I to generate the divisor.

In one aspect, Step1322accepts a synthesizer signal having the nominal synthesized frequency. Step1324divides the synthesizer signal by the divisor to generate a clock signal. Step1326compares the clock signal frequency to a reference signal having the reference frequency. In response to the comparison, Step1328frequency locks and/or phase locks the synthesizer signal to the reference signal.

In another aspect, generating the first carry bit in Step1316includes the following substeps. Step1316agenerates a binary “1” first carry bit if the first sum is greater than the denominator. Alternatively, Step1316bgenerates a binary “0” first carry bit if the first sum is less than or equal to the denominator. In response to comparing the first sum to the denominator, Step1314uses the first difference as the first count if the first sum is greater than the denominator. Alternatively, Step1314uses the first sum as the first count if the first sum is less than or equal to the denominator.

In one aspect, reducing the ratio of n/d to the integer (I) and the ratio of N/D in Step1308includes generating an n-bit binary numerator and an (n+1)-bit binary denominator. Alternately stated, (n) is the resolution threshold X. Then, creating the first sum in Steps1310or1311includes creating an (n+1)-bit first sum of the numerator and an n-bit first count from the previous cycle. Creating the first difference in Step1312includes creating an n-bit first difference.

One aspect includes a chain of (m−1) flexible accumulators linked to the first flexible accumulator. Then, in Step1319beach ith flexible accumulator in the chain accepts an (ith−1) count from a previous cycle and an ith count from the previous cycle. Step1319ccreates a binary ith sum of the (ith−1) count and the ith count. Step1319dcreates a binary ith difference between ith sum and the denominator. Step1319ecompares the ith sum with the denominator. If the ith sum is greater than the denominator, Step1319fgenerates a binary “1” ith carry bit, and uses the ith difference as the ith count for a subsequent cycle. Alternatively, if the ith sum is less than or equal to the denominator, Step1319fgenerates a binary “0” ith carry bit, and uses the ith sum as the ith count for the subsequent cycle. Step1319gacids the ith carry bit to an ith binary sequence if N is resolved with X or fewer bits, or adds the complement of the ith carry bit to the ith binary sequence if N is resolved with greater than X bits. Step1319hiteratively generates m binary sequences, and Step1320uses the in binary sequences to generate the k-bit quotient.

A system and method have been provided that permit a frequency synthesis based upon either rational division using a low resolution nominator. Some examples of circuitry and methodology steps have been given as examples to illustrate the invention. However, the invention is not limited to merely these examples. Likewise, the invention has been described in the context of binary numbers. However, the invention is not limited to any particular number base. Other variations and embodiments of the invention will occur to those skilled in the art.