Information processing system, image processing apparatus, and communication control method

Information processing systems including a plurality of integrated circuit chips have had problems such as an increased cost due to an increase in the number of terminals related to settings of an interface between the chips and delayed program transfer. An information processing system is provided in which a plurality of integrated circuit chips each include a plurality of communication units to be initialized by a common setting terminal. A processing execution unit of a first integrated circuit chip set to a first mode starts establishing a communication connection through one of the initialized communication units to one of the communication units of a second integrated circuit chip set to a second mode.

FIELD OF THE DISCLOSURE

The present disclosure relates to an information processing system configured by using two or more integrated circuit chips.

DESCRIPTION OF THE RELATED ART

As apparatuses have become increasingly complicated in recent years, more and more apparatuses are configured with a plurality of integrated circuit chips. A challenge in such a situation is to reduce the number of constituent parts of the apparatus for cost reduction. To address this, a technique has been studied in which a program is transferred from one integrated circuit chip to another integrated circuit chip, thereby eliminating the need of an external ROM to be connected to this other integrated circuit chip (see Japanese Patent Laid-Open No. 2002-099517, for example).

Also, a method has been disclosed in which chips to serve respectively as a master and a slave are configured with identical chips in order to reduce the cost and man-hours for developing integrated circuit chips (see Japanese Patent Laid-Open No. 2016-218976, for example). In this method, setting terminals for, for example, setting a CPU boot mode and setting a communication mode setting are provided. With the CPU boot mode setting terminal, the boot of a CPU is stopped. A setting of the communication mode setting terminal, on the other hand, enables an interface unit to access the slave chip from the master chip. With these functions, the master chip can boot the CPU of the slave chip after transferring a program to the slave chip.

However, before the boot of the CPU of the slave chip, communication through the interface unit needs to be established. Hence, settings related to interface conditions between the master chip and the slave chip need to be set in advance before the communication is established. The interface conditions are settings related to signal quality such as signal amplitude and de-emphasis, for example. In conventional methods, the settings are set through an interface between the chips in a route other than that for the above-mentioned interface unit. However, a problem with this method is, for example, that the number of terminals of the integrated circuit chips increases according to the number of interfaces between the chips in other routes. For the development of integrated circuit chips in recent years, reducing the number of terminals is an important issue since an increase in the number of terminals leads to a higher cost.

Meanwhile, a method has also been employed in which no interface is provided between chips in another route and instead a program is transferred at a communication speed lowered to such an extent as not to be affected by settings related to signal quality. With this method, however, a large amount of program data must be communicated at a low speed, which leads to a problem such as requiring an extra time for the program transfer.

SUMMARY

An information processing system according to the present disclosure to solve the above-mentioned problem includes: a plurality of integrated circuit chips each including a processing execution unit that executes information processing in accordance with a program, and a communication unit that is caused by the processing execution unit to communicate with another one of the integrated circuit chips; and a mode setting unit capable of setting each of the integrated circuit chips to at least a first mode or a second mode. Here, each of the plurality of integrated circuit chips includes a plurality of the communication units to be initialized by a common setting terminal. The processing execution unit of a first integrated circuit chip set to the first mode starts establishing a communication connection through one of the initialized communication units to one of the communication units of a second integrated circuit chip set to the second mode.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present disclosure will be described in detail below with reference to the drawings.

First Embodiment

FIGS.1A and1Bare block diagrams illustrating an example configuration of an information processing system with a 2-chip configuration in a first embodiment. The information processing system includes a first integrated circuit chip110and a second integrated circuit chip120. A ROM113and a RAM115are connected to the first integrated circuit chip110. To reduce the number of parts for cost reduction, no ROM is connected to the second integrated circuit chip120, and only a RAM125is connected to it. The first integrated circuit chip110and the second integrated circuit chip120are connected through an interface150for performing communication.

The first integrated circuit chip110and the second integrated circuit chip120are integrated circuit chips having the same internal configuration with different memories connected thereto. Regarding functionality, on the other hand, the first integrated circuit chip110is an integrated circuit chip that operates in a first mode to serve as a master whereas the second integrated circuit chip120is an integrated circuit chip that operates in a second mode to serve as a slave. A mode setting unit for setting the mode to the first mode or the second mode will be described later.

The ROM113of the first integrated circuit chip110stores pieces of program data for causing the first integrated circuit chip110and the second integrated circuit chip120to operate. The first integrated circuit chip110sends the piece of program data of the second integrated circuit chip120stored in the ROM113through the interface150. The second integrated circuit chip120, in turn, receives the piece of program data through the interface150and stores it in the RAM125. After that, the second integrated circuit chip120operates in accordance with this piece of program data.

Next, a configuration of the first integrated circuit chip110will be described. A CPU111is a processing execution unit that executes information processing in accordance with a program. The CPU111is connected through a main bus118to a ROM controller unit112connected to the ROM113and a RAM controller unit114connected to the RAM115. The ROM113is a storage unit that stores the piece of program data to be executed by the CPU111and the like. The ROM controller unit112is capable of reading out the piece of program data and the like stored in the ROM113. The RAM115is a storage unit that, for example, stores a piece of program data being executed and stores temporary data, such as image data, being executed. The RAM controller unit114is capable of reading and writing data from and to the RAM115.

The CPU111is connected further to two interface units116and117through the main bus118. The interface units116and117are responsible for the integrated circuit chip's external communication. InFIG.1A, the interface unit117communicates with the second integrated circuit chip120through the interface150. The main bus118is accessible from the CPU111and is also accessible from the CPUs of other integrated circuit chips after the interface units116and117establish communication connections.

A signal amplitude setting terminal161and a de-emphasis setting terminal162are connected to the interface units116and117. Other settings related to the interface conditions at the interface units116and117include a pre-emphasis setting, an equalizer setting, and so on (hereinafter referred to collectively as “signal quality settings”). The present embodiment will be described taking the above two signal quality settings as an example.

With the signal amplitude setting terminal161, an initial value of the magnitude of the signal amplitude at the interface150is set according to the input state of the terminal (hereinafter this will be expressed to as “initialized”). The “initial value” here means a setting value at a stage before the CPU starts operating after the integrated circuit chip is released from reset. With the de-emphasis setting terminal162, whether to enable or disable a de-emphasis function on the signal at the interface150is initialized according to the input state of the terminal. From the viewpoint of reducing the terminal cost, the signal amplitude setting terminal161and the de-emphasis setting terminal162are each a single terminal given per integrated circuit chip. Specifically, an input signal into a common setting terminal is split within the integrated circuit chip to give a common initial setting to registers in the two interface units116and117.

The signal quality settings are collectively set from a control unit on a circuit board on which the integrated circuit chips are mounted. Specifically, the control unit releases each integrated circuit chip from reset, and then configures the settings of the signal amplitude setting terminal and the de-emphasis setting terminal. In each integrated circuit chip, an initial value is set to a register in each interface unit according to the input signal into the corresponding setting terminal.

The interface units116and117of the first integrated circuit chip110are given a common signal amplitude setting and de-emphasis setting. Note that the interface unit116is not used and only the interface unit117is used. Thus, the input states of the signal amplitude setting terminal161and the de-emphasis setting terminal162are set to be states that enable proper communication between the interface unit117and the second integrated circuit chip120through the interface150(master-slave communication). Here, the “states that enable proper communication” refer to, for example, states where stable communication can be performed with good signal quality and fewer errors. Specifically, the “states that enable proper communication” refer to states where the signal's AC characteristics, DC characteristics, eye pattern, and so on meet specifications in the interface's communication standard or are sufficient with respect to the specifications.

As an initial setting (first initial value) for the master-slave communication, +Vcc is connected to the signal amplitude setting terminal161of the first integrated circuit chip110, so that the logic of the terminal input becomes high (=1). Accordingly, the signal amplitude is initialized to be full. Also, +Vcc is connected to the de-emphasis setting terminal162, so that the logic of the terminal input becomes high (=1). Accordingly, the de-emphasis function is initialized to be enabled. Note that the input voltages and input logics of the setting terminals are mere examples, and one or both may be low (=0).

Next, a configuration of the second integrated circuit chip120will be described. A CPU121is a processing execution unit that executes information processing in accordance with a program. The CPU121is connected through a main bus128to a ROM controller unit122and a RAM controller unit124connected to the RAM125. The ROM controller unit122of the second integrated circuit chip120has no ROM connected thereto and does not read out a program. The RAM125is a storage unit that, for example, stores a piece of program data being executed and stores temporary data, such as image data, being executed. The RAM controller unit124is capable of reading and writing data from and to the RAM125.

The CPU121is connected further to two interface units126and127through the main bus128. The interface units126and127are responsible for the integrated circuit chip's external communication. InFIG.1B, the interface unit126communicates with the first integrated circuit chip110through the interface150. The main bus128is accessible from the CPU121and is also accessible from the CPUs of other integrated circuit chips after the interface units126and127establish communication connections.

A signal amplitude setting terminal163and a de-emphasis setting terminal164for signal quality settings are connected to the interface units126and127. With the signal amplitude setting terminal163, the signal amplitude at the interface150is initialized according to the input state of the terminal. With the de-emphasis setting terminal164, whether to enable or disable a de-emphasis function on the signal at the interface150is initialized according to the input state of the terminal. From the viewpoint of reducing the terminal cost, the signal amplitude setting terminal163and the de-emphasis setting terminal164are each a single terminal given per integrated circuit chip. Specifically, an input signal into a common setting terminal is split within the integrated circuit chip to give a common initial setting to the two interface units126and127.

The signal quality settings are collectively set from a control unit on a circuit board on which the integrated circuit chips are mounted. Specifically, the control unit releases each integrated circuit chip from reset, and then configures the settings of the signal amplitude setting terminal and the de-emphasis setting terminal. In each integrated circuit chip, an initial value is set to a register in each interface unit according to the input signal into the corresponding setting terminal.

The interface units126and127in the second integrated circuit chip120are given a common signal amplitude setting and de-emphasis setting. Note that the interface unit127is not used and only the interface unit126is used. Thus, the input states of the signal amplitude setting terminal163and the de-emphasis setting terminal164are set to be states that enable proper communication between the interface unit126and the first integrated circuit chip110through the interface150(master-slave communication). As an initial setting (first initial value) for the master-slave communication, +Vcc is connected to the signal amplitude setting terminal163of the second integrated circuit chip120, so that the logic of the terminal input becomes high (=1). Accordingly, the signal amplitude is initialized to be full. Also, +Vcc is connected to the de-emphasis setting terminal164, so that the logic of the terminal input becomes high (=1). Accordingly, the de-emphasis function is initialized to be enabled.

With such a configuration, the control unit on the circuit board on which the integrated circuit chips are mounted configures the signal quality settings. In this way, the settings of each interface unit can be brought into a state in advance that enables proper communication. This makes it possible to send a piece of program data from the first integrated circuit chip110to the second integrated circuit chip120in the proper communication state. As described above, although the two interface units of each integrated circuit chip are given common values as their initial settings, the interface units can be in a state where they can perform proper communication before they start communication. This eliminates the need to provide a setting terminal for initialization for each interface unit of each integrated circuit chip and thus reduces the number of terminals of the integrated circuit chip. Also, only a setting terminal is provided for each individual signal quality setting, and no interface needs to be provided between the chips in a route other than that for the above interface unit. This can reduce the cost of the integrated circuit chips.

As an example in which an interface unit needs initialization as above, Peripheral Component Interconnect Express (PCI-E) has been known. In PCI-E, in a root complex (hereinafter RC) mode, a chip serves as a master to control communication through an interface. On the other hand, in an end point (hereinafter EP) mode, the chip is controlled as a slave. Ina case of booting the information processing system, it operates as below according to the mode.

The first integrated circuit chip110is set to the first mode (RC mode) to serve as a master. Specifically, at the time of the boot, a mode setting unit not illustrated releases the CPU111from reset through the setting terminals of the first integrated circuit chip110, and selects an address in the ROM113as a boot vector address. The second integrated circuit chip120is set to the second mode (EP mode) to serve as a slave. Specifically, at the time of the boot, the mode setting unit brings the CPU121into a reset state through the setting terminals of the second integrated circuit chip120, and selects an address in the RAM125as a boot vector address.

At the time of the boot, in the first integrated circuit chip110in the RC mode, the CPU111is released from reset and starts executing a program. The first integrated circuit chip110has the initiative on communication control, and starts establishing a connection for communication through the interface150as the CPU111executes the program. Specifically, the first integrated circuit chip110performs operations such as setting the communication speed and configuring settings related to the communication procedure. Here, before the start of communication, the initial settings related to the signal quality at the interface150are set based on the configuration in the first embodiment described above. The first integrated circuit chip110configures settings for execution of processing by the CPU121, such as releasing the second integrated circuit chip120from reset, setting a base address, and converting addresses.

On the other hand, the second integrated circuit chip120in the EP mode is in a state of waiting for settings for executing processing from the first integrated circuit chip110. After the settings for executing processing are configured, communication is started through the interface150, so that the first integrated circuit chip110sends the piece of program data of the second integrated circuit chip120stored in the ROM113through the interface150. After the received piece of program data is stored in the RAM125, an address in the RAM125is set as a boot vector address. The CPU121gets released from reset and executes the program. As a result, the second integrated circuit chip120starts operating.

Second Embodiment

FIGS.2A,2B and2Care block diagrams illustrating an example configuration of an information processing system with a 3-chip configuration using a plurality of slave chips in a second embodiment. The information processing system includes the first integrated circuit chip110and the second integrated circuit chip120in the first embodiment and additionally a third integrated circuit chip130. The ROM113and the RAM115are connected to the first integrated circuit chip110. To reduce the number of parts for cost reduction, no ROM is connected to the second integrated circuit chip120or the third integrated circuit chip130, and only the RAM125and a RAM135are connected to them, respectively. The second integrated circuit chip120and the third integrated circuit chip130are connected through an interface250for performing communication.

The first integrated circuit chip110, the second integrated circuit chip120, and the third integrated circuit chip130are integrated circuit chips having the same internal configuration with different memories connected thereto. On the other hand, the first integrated circuit chip110is an integrated circuit chip that operates in a first mode to serve as a master whereas the second integrated circuit chip120and the third integrated circuit chip130is an integrated circuit chip that operates in a second mode to serve as a slave.

The ROM113of the first integrated circuit chip110stores pieces of program data for causing the integrated circuit chips to operate. The first integrated circuit chip110sends the piece of program data of the second integrated circuit chip120stored in the ROM113through the interface150. Moreover, the first integrated circuit chip110sends the piece of program data of the third integrated circuit chip130stored in the ROM113through the interfaces150and250. The second integrated circuit chip120and the third integrated circuit chip130, in turn, store the received pieces of program data in the respective RAMs. After that, the second integrated circuit chip120and the third integrated circuit chip130operate in accordance with these pieces of program data.

Next, a configuration of the third integrated circuit chip130will be described. A CPU131is a processing execution unit that executes information processing in accordance with a program. The CPU131is connected through a main bus138to a ROM controller unit132and a RAM controller unit134connected to the RAM135. The ROM controller unit132of the third integrated circuit chip130has no ROM connected thereto and does not read out a program. The RAM135is a storage unit that, for example, stores a piece of program data being executed and stores temporary data, such as image data, being executed. The RAM controller unit134is capable of reading and writing data from and to the RAM135.

The CPU131is connected further to two interface units136and137through the main bus138. The interface units136and137are responsible for the integrated circuit chip's external communication. InFIG.2C, the interface unit136communicates with the second integrated circuit chip120through the interface250. The main bus138is accessible from the CPU131and is also accessible from the CPUs of other integrated circuit chips after the interface units136and137establish communication connections.

A signal amplitude setting terminal165and a de-emphasis setting terminal166for signal quality settings are connected to the interface units136and137. With the signal amplitude setting terminal165, the signal amplitude at the interface250is initialized according to the input state of the terminal. With the de-emphasis setting terminal166, whether to enable or disable a de-emphasis function on the signal at the interface250is initialized according to the input state of the terminal. From the viewpoint of reducing the terminal cost, the signal amplitude setting terminal165and the de-emphasis setting terminal166are each a single terminal given per integrated circuit chip. Specifically, an input signal into a common setting terminal is split within the integrated circuit chip to give a common initial setting to registers in the two interface units136and137.

The signal quality settings are collectively set from a control unit on a circuit board on which the integrated circuit chips are mounted. Specifically, the control unit releases each integrated circuit chip from reset, and then configures the settings of the signal amplitude setting terminal and the de-emphasis setting terminal. In each integrated circuit chip, an initial value is set to a register in each interface unit according to the input signal into the corresponding setting terminal.

The interface units136and137in the third integrated circuit chip130are given a common signal amplitude setting and de-emphasis setting. Note that the interface unit137is not used and only the interface unit136is used. Thus, the input states of the signal amplitude setting terminal165and the de-emphasis setting terminal166are set to be states that enable proper communication between the interface unit136and the second integrated circuit chip120serving as a slave through the interface250(inter-slave communication). As an initial setting (second initial value) for the inter-slave communication, GND is connected to the signal amplitude setting terminal165of the third integrated circuit chip130, so that the logic of the terminal input becomes low (=0). Accordingly, the signal amplitude is initialized to be half. Also, GND is connected to the de-emphasis setting terminal166, so that the logic of the terminal input becomes low (=0). Accordingly, the de-emphasis function is initialized to be disabled.

In the second embodiment, a 3-chip configuration is employed. Thus, the interface unit127of the second integrated circuit chip120, which is not used in the first embodiment, is used for communication with the third integrated circuit chip130. The signal amplitude setting terminal163and the de-emphasis setting terminal164of the second integrated circuit chip120are each given a common initial setting for the interface units126and127. Thus, a logic that enables proper communication with the first integrated circuit chip110, which is the master, through the interface150(master-slave communication), i.e., the first initial value, is set. Note that this logic is not necessarily a logic that enables proper communication through the interface250. The logic that enables proper communication may be different between the interfaces150and250due to differences in the layout on the circuit board and the conditions of wirings and the like.

Since communication through the interface150has already been established, the CPU111rewrites the values of the signal amplitude setting and de-emphasis setting registers in the interface unit127through the interface150. Specifically, a method in which the values of the registers in the interface unit127are rewritten to proper setting values for the interface250is conceivable. A method also is conceivable in which, if the CPU121is ready to operate, the CPU121rewrites the values of the signal amplitude setting and de-emphasis setting registers in the interface unit127through the main bus128to proper setting values for the interface250.

FIG.3illustrates an example flow of control performed in a case where the CPU111rewrites the values of the signal amplitude setting and de-emphasis setting registers in the interface unit127through the interface150. The control unit on the circuit board on which the integrated circuit chips are mounted releases each integrated circuit chip from reset. Thereafter, the CPU111of the first integrated circuit chip110is booted. With the mode setting unit not illustrated, the CPU111recognizes that it is the CPU of an integrated circuit chip in the first mode serving as a master. Moreover, a point when initial values are set to the registers in the interface units of each integrated circuit chip and communication through the interface150(master-slave communication) is established is set as a start point. Note that the symbols “S” in the following description represent steps.

In S311, the CPU111of the first integrated circuit chip110sends the piece of program data of the second integrated circuit chip120to the RAM125through the interface150. The second integrated circuit chip120receives the piece of program data through the interface150and stores it in the RAM125(S321).

In S312, the CPU111of the first integrated circuit chip110reads the setting values of the signal amplitude setting and de-emphasis setting registers in the interface unit127of the second integrated circuit chip120through the interface150.

In S313, the CPU111of the first integrated circuit chip110determines whether it is necessary to change the read setting values. Here, the interface units126and127are set to logics (first initial value) that enable proper communication with the first integrated circuit chip110, which is the master, through the interface150(master-slave communication), as, the common initial setting. Specifically, the signal amplitude is initialized to be full through the signal amplitude setting terminal163of the second integrated circuit chip120, and the de-emphasis function is initialized to be enabled through the de-emphasis setting terminal164.

On the other hand, the interface unit127is used for communication with the third integrated circuit chip130serving as a slave through the interface250(inter-slave communication). As mentioned above, for the third integrated circuit chip130, the signal amplitude is initialized to be half through the signal amplitude setting terminal165, and the de-emphasis function is initialized to be disabled through the de-emphasis setting terminal166. The CPU111therefore determines that it is necessary to change the setting values of the interface unit127to logics (second initial value) which enable proper communication with the third integrated circuit chip130serving as a slave (inter-slave communication).

If it is determined in S313that it is necessary to change the setting values, the processing proceeds to S314. The CPU111of the first integrated circuit chip110writes the proper setting values to the signal amplitude setting and de-emphasis setting registers in the interface unit127the through the interface150. Specifically, the signal amplitude setting of the interface unit127is updated to be half, and the de-emphasis setting is updated to be disabled (S322).

Then, in S315, the logics are such that proper communication can be performed through the interface250. The CPU111of the first integrated circuit chip110sends the piece of program data of the third integrated circuit chip130to the RAM135through the interfaces150and250. The third integrated circuit chip130receives the piece of program data through the interface250and stores it in the RAM135(S331).

FIG.4illustrates an example flow of control performed in a case where the CPU121rewrites the values of the signal amplitude setting and de-emphasis setting registers in the interface unit127. The control unit on the circuit board on which the integrated circuit chips are mounted releases each integrated circuit chip from reset. Thereafter, the CPU111of the first integrated circuit chip110is booted. With the mode setting unit not illustrated, the CPU111recognizes that it is the CPU of an integrated circuit chip in the first mode serving as a master. Moreover, a point when initial values are set to the registers in the interface units of each integrated circuit chip and communication through the interface150(master-slave communication) is established is set as a start point.

In S411, the CPU111of the first integrated circuit chip110sends the piece of program data of the second integrated circuit chip120to the RAM125through the interface150. The second integrated circuit chip120receives the piece of program data through the interface150and stores it in the RAM125(S421).

In S422, the CPU121of the second integrated circuit chip120is released from reset. The CPU121is now ready to operate.

In S423, the CPU121of the second integrated circuit chip120reads the setting values of the signal amplitude setting and de-emphasis setting registers in the interface unit127through the main bus128.

In S424, the CPU121of the second integrated circuit chip120determines whether it is necessary to change the read setting values. Here, as in the control flow illustrated inFIG.3, the CPU121determines that it is necessary to change the setting values of the interface unit127to logics (second initial value) which enable proper communication through the interface250(inter-slave communication).

If it is determined in S424that it is necessary to change the setting values, the processing proceeds to S425. The CPU121of the second integrated circuit chip120writes the proper setting values to the signal amplitude setting and de-emphasis setting registers in the interface unit127the through the main bus128.

In S426, the CPU121of the second integrated circuit chip120notifies the CPU111of the first integrated circuit chip110that the setting values of the signal amplitude setting and de-emphasis setting registers in the interface unit127are now proper values.

Then, in S412, the logics are such that proper communication can be performed through the interface250. The CPU111of the first integrated circuit chip110sends the piece of program data of the third integrated circuit chip130to the RAM135through the interfaces150and250. The third integrated circuit chip130receives the piece of program data through the interface250and stores it in the RAM135(S431).

With such a configuration, the settings of each interface unit can be brought into a state in advance that enables proper communication. This makes it possible to send a piece of program data from the first integrated circuit chip110to the second integrated circuit chip120and a piece of program data from the first integrated circuit chip110to the third integrated circuit chip130in the proper communication state. As described above, although the two interface units of each integrated circuit chip are given common values as their initial settings, the interface units can be in a state where they can perform proper communication before they start communication. This eliminates the need to provide a setting terminal for initialization for each interface unit of each integrated circuit chip and thus reduces the number of terminals of the integrated circuit chip. Also, only a setting terminal is provided for each individual signal quality setting, and no interface needs to be provided between the chips in a route other than those for the above interface units. This can reduce the cost of the integrated circuit chips.

Third Embodiment

A third embodiment is the same as the second embodiment in that a 3-chip configuration with a plurality of slave chips is used, but is different in that the second integrated circuit chip120and the third integrated circuit chip130are connected through an interface cable.

FIGS.5A,5B and5Care block diagrams illustrating an example configuration of an information processing system in the third embodiment in which integrated circuit chips are connected through an interface cable. The same portions as those in the second embodiment are denoted by the same reference signs, and description thereof is omitted. The third embodiment differs from the second embodiment is that the first integrated circuit chip110and the second integrated circuit chip120are mounted on a first circuit board501and the third integrated circuit chip130is mounted on a second circuit board502. Thus, the second integrated circuit chip120on the first circuit board501and the third integrated circuit chip130on the second circuit board502are connected by an interface cable503. The interface cable503accommodates therein wirings of the interface250between the interface unit127of the second integrated circuit chip120and the interface unit136of the third integrated circuit chip130.

The control flow is the same as the control flow presented in the second embodiment.

In the case of a configuration as described above in which different circuit boards are connected through an interface cable, the interface conditions are different from those in the case where the integrated circuit chips are wired on the same circuit board. Also, the communication path between the integrated circuit chips is longer in distance, which makes communication more easily affected by an impedance mismatch and the like. In particular, in a case where the interface cable is installed in a movable portion, changes in the interface conditions have a significant impact. Thus, even for inter-slave communication through the same interface250, the signal quality settings such as the signal amplitude setting and the de-emphasis setting are each set to a plurality of setting values corresponding to the interface conditions. According to the control flow presented in the second embodiment, the setting values of the interface units of the integrated circuit chips can be updated in advance such that proper communication can be performed between the interface units.

In the first and second embodiments, the setting values of the initial settings are different between master-slave communication and inter-slave communication. According to the present disclosure, it is possible to set desired setting values by, for example, changing the setting values according to whether communication is to be performed within a circuit board or between circuit boards, as in the third embodiment, or changing the setting values according to the type of communication through the interface or the type of the communication path. According to the present disclosure, it is possible not only to reduce the number of terminals of integrated circuit chips to reduce the cost of the integrated circuit chips, but also to achieve stable communication quality between the integrated circuit chips.

Fourth Embodiment

FIGS.6A,6B and6Care block diagrams illustrating an example configuration of an information processing system with a 3-chip configuration using a plurality of slave chips in a fourth embodiment. The fourth embodiment differs from the second embodiment in that the second integrated circuit chip120operates in the first mode to serve as a master, and the first integrated circuit chip110and the third integrated circuit chip130operate in the second mode to serve as slaves. The second integrated circuit chip120serving as the master uses a plurality of interface units. The same portions as those in the second embodiment are denoted by the same reference signs, and description thereof is omitted. Thus, a ROM123is connected to the ROM controller unit122of the second integrated circuit chip120. On the other hand, no ROM is connected to the first integrated circuit chip110or the third integrated circuit chip130in order to reduce the number of parts for cost reduction.

The ROM123of the second integrated circuit chip120stores pieces of program data for causing the integrated circuit chips to operate. The second integrated circuit chip120sends the piece of program data of the first integrated circuit chip110stored in the ROM123through the interface150. Moreover, the second integrated circuit chip120sends the piece of program data of the third integrated circuit chip130stored in the ROM123through the interface250. The first integrated circuit chip110and the third integrated circuit chip130, in turn, store the received pieces of program data in the respective RAMs. After that, the first integrated circuit chip110and the third integrated circuit chip130operate in accordance with these pieces of program data.

A signal amplitude setting terminal163and a de-emphasis setting terminal164for signal quality settings are connected to the interface units126and127in the second integrated circuit chip120. With the signal amplitude setting terminal163, initial values of the magnitude of the signal amplitude at the interfaces150and250is initialized according to the input state of the terminal. With the de-emphasis setting terminal164, whether to enable or disable a de-emphasis function on the signals at the interfaces150and250is initialized according to the input state of the terminal.

The signal quality settings are collectively set from a control unit on a circuit board on which the integrated circuit chips are mounted. Specifically, the control unit releases each integrated circuit chip from reset, and then configures the settings of the signal amplitude setting terminal and the de-emphasis setting terminal. In each integrated circuit chip, an initial value is set to a register in each interface unit according to the input signal into the corresponding setting terminal.

The interface units126and127in the second integrated circuit chip120are given a common signal amplitude setting and de-emphasis setting. In the fourth embodiment, both of the interface units126and127are used. Thus, the input states of the signal amplitude setting terminal163and the de-emphasis setting terminal164are set to be states which enable one of the interface units126and127to perform proper communication. The interface unit to be brought into the state of being capable of performing proper communication may be determined, for example, based on a preset order of program transfer such that the interface unit to be connected to the first integrated circuit chip to transfer a program is selected.

Here, the input states of the signal amplitude setting terminal163and the de-emphasis setting terminal164are set to be states which enable proper communication with the interface unit117of the first integrated circuit chip110through the interface150(master-slave communication). As an initial setting (first initial value) for the master-slave communication, +Vcc is connected to the signal amplitude setting terminal163of the second integrated circuit chip120, so that the logic of the terminal input becomes high (=1). Accordingly, the signal amplitude is initialized to be full. Also, +Vcc is connected to the de-emphasis setting terminal164, so that the logic of the terminal input becomes high (=1). Accordingly, the de-emphasis function is initialized to be enabled. Note that the settings may be different if the interface unit126is in a state of being capable of performing proper communication.

With the above settings, the logics may not necessarily enable the interface unit127to perform proper communication. Thus, as in the second embodiment, the CPU121is required to update the setting values of the signal amplitude setting and de-emphasis setting registers in the interface unit127through the main bus128. Here, the setting values are updated to the second initial value so that proper communication can be performed with the third integrated circuit chip130serving as a slave through the interface250(master-slave communication).

With such a configuration, the settings of each interface unit can be brought into a state in advance that enables proper communication. This makes it possible to send a piece of program data from the second integrated circuit chip120to the first integrated circuit chip110and a piece of program data from the second integrated circuit chip120to the third integrated circuit chip130in the proper communication state. As described above, although the two interface units of each integrated circuit chip are given common values as their initial settings, the interface units can be in a state where they can perform proper communication before they start communication. This eliminates the need to provide a setting terminal for initialization for each interface unit of each integrated circuit chip and thus reduces the number of terminals of the integrated circuit chip. Also, only a setting terminal is provided for each individual signal quality setting, and no interface needs to be provided between the chips in a route other than those for the above interface units. This can reduce the cost of the integrated circuit chips.

In the first to fourth embodiments, configurations including two interface units in each single integrated circuit chip have been exemplarily described. Even in a case where each single integrated circuit chip includes three or more interface units, it is only necessary to set the signal quality settings of the signal amplitude setting terminal, the de-emphasis setting terminal, and so on in common to all interface units. It suffices that the integrated circuit chip serving as the master uses one of the plurality of interface units as an interface unit for transferring program data, and configure settings such that this one interface unit can perform proper communication (master-slave communication). The effect of reducing the number of terminals is expected to be greater the larger the number of interface units.

Fifth Embodiment

FIG.7illustrates an example configuration of an image processing apparatus in a fifth embodiment. An image processing apparatus1500includes a controller chip1510and a printing control chip1520as integrated circuit chips. A ROM1511and a RAM1512are connected to the controller chip1510. No ROM is connected to the printing control chip1520, and only a RAM1522is connected to it. The controller chip1510and the printing control chip1520are connected through an interface1530for performing communication.

Also, the controller chip1510is connected through a host interface to a host PC1550that sends print jobs and the like, and is connected through a LAN to an external network1560. A printing unit1523that performs head and paper conveyance and so on is connected to the printing control chip1520.

The controller chip1510serves as the first integrated circuit chip110in the first to fourth embodiments, and the printing control chip1520serves as the second integrated circuit chip120in the first to fourth embodiments. In a case where the image processing apparatus1500further includes a different printing control chip or an integrated circuit chip with another function, it serves as the third integrated circuit chip130. Applying the configurations in the first to fourth embodiments as above can reduce the number of terminals of the integrated circuit chips, which can in turn reduce the cost of the integrated circuit chips and the cost of the image processing apparatus1500.

Other Embodiment

Note that the information processing systems are not limited to image processing apparatuses. The configurations according to the present disclosure are applicable to, for example, information processing apparatuses such as personal computers, industrial equipment, and so on if they are apparatuses including a plurality of integrated circuit chips.

In the present disclosure, integrated circuit chips with the same configuration are used as a master and a slave(s). However, the present disclosure is not limited to this configuration. Specifically, the configurations according to the present disclosure are applicable systems with integrated circuit chips that can be selected and configured as a master and a slave by an information processing system, if the integrated circuit chips include a plurality of interface units.

According to the present disclosure, an information processing system including a plurality of integrated circuit chips can use fewer terminals to set initial settings of communication units for communication between the integrated circuit chips. This can reduce the cost of the integrated circuit chips.

This application claims the benefit of Japanese Patent Application No. 2021-183410, filed Nov. 10, 2021 which is hereby incorporated by reference wherein in its entirety.