Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem

A memory system is disclosed. The memory system includes first and second memory devices, and a memory controller configured to selectively enable one of the memory devices, the memory controller having a first line coupled to the first and second memory devices and a second line coupled to the first and second memory devices. The first memory device is configured to provide a notification to the memory controller on the first line and the second memory device is configured to provide a notification to the memory controller on the second line. The first memory device is further configured not to load the first line and the second memory device is further configured not to load the second line when the memory controller is writing to the enabled memory device.

FIELD

The present disclosure relates generally to memory systems, and more specifically, to signaling between a memory controller and memory in a memory system.

BACKGROUND

Memory systems are used extensively today in processing systems to store data needed by various processing entities. A memory system generally includes a memory controller that manages access to the memory. The memory is typically configured in a matrix structure formed by rows and columns of memory cells, with each memory cell being capable of storing a bit of data. A block of memory cells may be accessed by a processing entity, or other source, by providing the appropriate address to the memory controller. The address from the processing entity may be sent to the memory controller over a bus with the row address occupying the higher-order bits and the starting column address occupying the lower-order bits. The memory controller uses a multiplexing scheme to send the row address to the memory followed by the starting column address.

When a processing entity requires access to a block of memory, it sends a read or write command to the memory controller. Each read and write command includes an address. The manner in which the memory controller executes each command depends on whether the processing entity is attempting to access an open page in the memory. A “page” is normally associated with a row of memory, and an “open page” means that the memory is pointing to a row of memory and requires only the starting column address and a column access strobe (CAS) to access the block of memory. To access an unopened page of memory, the memory controller must present the row address and a row access strobe (RAS) to the memory to move the pointer before presenting the starting column address and the CAS to the memory.

Various memories are used today in memory systems. A Synchronous Dynamic Random Access Memory (SDRAM) is just one example. When a processing entity is writing to a SDRAM, or other memory device, data is transmitted over a data bus between the memory controller and the memory. A data mask may be used by the memory controller to mask data on the data bus. When the data mask is deasserted, the data on the data bus will be written to the memory. When the data mask is asserted, the data on the data bus will be ignored, and the write operation will not be performed.

The data mask is only used during write operations. When a processing entity is not writing to the SDRAM, or other memory device, the memory controller tri-states the data mask. Thus, there exists an opportunity to use the data mask for other purposes when the processing entity is not performing a write operation. By utilizing the data mask in this way, additional communications can occur between the memory controller and the memory without increasing the number of pins on the memory device.

SUMMARY

One aspect of a memory system is disclosed. The memory system includes first and second memory devices, and a memory controller configured to selectively enable one of the memory devices, the memory controller having a first line coupled to the first and second memory devices and a second line coupled to the first and second memory devices. The first memory device is configured to provide a notification to the memory controller on the first line and the second memory device is configured to provide a notification to the memory controller on the second line. The first memory device is further configured not to load the first line and the second memory device is further configured not to load the second line when the memory controller is writing to the enabled memory device.

Another aspect of a memory system is disclosed. The memory system includes first and second memory ranks, each of the memory ranks having a memory device, and a memory controller configured to selectively enable one of the memory ranks and write data to the enabled memory rank, the memory controller having first and second lines, each being coupled to the first and second memory ranks, the first and second lines being configured to provide a data mask relating to the data. The memory device in the first memory rank is configured to provide a notification to the memory controller on the first line and the memory device in the second memory rank is configured to provide a notification to the memory controller on the second line.

One aspect of a method of communicating between a memory controller and a memory having first and second memory devices is disclosed. The memory controller includes a line coupled to the first and second memory devices. The method includes providing a notification from the first memory device to the memory controller on the first line, enabling the second memory device in order for the memory controller to write to the second memory device, and placing the first memory device into a state that does not load the line when the memory controller is writing to the second memory device.

Another aspect of a method of communicating between a memory controller and memory having first and second memory ranks is disclosed. Each of the memory ranks includes a memory device. The memory controller includes a first line coupled to the memory device in the first rank and a second line coupled to the memory device in the second rank. The method includes providing a notification from the memory device in the first memory rank to the memory controller on the first line, enabling the second memory rank in order for the memory controller to write to the second memory rank, providing a data mask from the memory controller to the second memory rank on the first and second lines when the memory controller is writing to the second memory device.

A further aspect of a memory system is disclosed. The memory system includes first and second memory devices, and memory controller configured to selectively enable one of the memory devices, the memory controller having a first line coupled to the first and second memory devices and a second line coupled to the first and second memory devices. The first memory device further includes means for providing a notification to the memory controller on the first line and the second memory device includes means for providing a notification to the memory controller on the second line. The means for providing notification to the memory controller on the first line and the means for providing notification to the memory controller on the second line are each configured not to load its respective line when the memory controller is writing to the enabled memory device.

Another aspect of a memory system is disclosed. The memory system includes first and second memory ranks, each of the memory ranks having a memory device, and a memory controller configured to selectively enable one of the memory ranks and write data to the enabled memory rank. The memory controller having first and second lines, each being coupled to the first and second memory ranks, the first and second lines being configured to output a data mask relating to the data. The memory device in the first memory rank includes means for providing a notification to the memory controller on the first line and the memory device in the second memory rank includes means for providing a notification to the memory controller on the second line.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appended drawings is intended as a description of various embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention.

FIG. 1is a conceptual block diagram illustrating an example of a processing system. The processing system100may be a collection of devices that cooperate to perform one or more processing functions. Typical applications for the processing system100include, but are not limited to, desktop computers, laptop computers, servers, cellular phones, personal digital assistants (PDA), game consoles, pagers, modems, audio equipment, medical devices, automotive, video equipment, industrial equipment, or any other machine or device capable of processing, retrieving and storing information.

The processing system100is shown with a memory system104that may be accessed by any number of processing entities. In the configuration shown inFIG. 1, three processors102are shown in communication with the memory system104. Each processor102may be a general purpose processor, such as a microprocessor, a special purpose processor, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a direct memory access (DMA) controller, a bridge, a programmable logic component, or any other entity that requires access to the memory system104.

FIG. 2is a conceptual block diagram of a memory system. The memory system104includes a memory controller202that manages access to memory204. The memory204is shown inFIG. 2as a multiple-bank memory device with four banks204a-204d, but may have any number of banks depending on the particular application. A multiple-bank memory device may be thought of as a series of separate memories integrated into a single piece of silicon. In alternative embodiments of the memory system104, the memory controller202may be configured to manage access to multiple memory devices, with each memory device being a single-bank or multiple-bank device. Those skilled in the art will readily appreciate that the various concepts described throughout this disclosure may be applied to memory systems with different configurations.

The memory controller202may be any entity that controls the operation of one or more memory devices including a dedicated memory controller chip, a processor that directly controls the memory, controller circuitry on the memory device, or any other suitable arrangement. Each memory device may be any type of temporary storage device such as a SDRAM, DRAM, or RAM, or a longer term storage device such as flash memory, ROM memory, EPROM memory, EEPROM memory, etc. In this example, the memory devices will be described in the context of a SDRAM, however, the various concepts described throughout this disclosure may be extended to other memory devices.

An example of a write operation to the memory device will be described with the reference to timing diagram ofFIG. 3. The memory device is enabled by asserting the chip select (CS)301. Before a read or write operation can be performed to a bank within the memory device, a row in that bank must be opened. This is accomplished by sending both the bank address308and the row address310to the memory device and asserting the CS301and the RAS302by driving it into a logic “0” state at time320. In this example, all control signals, except for the data mask, are “asserted” with a logic “0” state, however, the polarities may be switched in practice.

Once a row is opened in a memory device, the memory controller may read from or write to that row. At time322, the memory controller initiates a write operation by sending the bank address308and the starting column address312to the memory device and asserting the CS301, the CAS304and the write enable (WE)306. After a predetermined delay following the assertion of the WE306, the memory controller begins transmitting the data to be written to the memory device on the data bus316(see time324). The memory device will ignore the data on the bus316, and not perform a write operation, when the data mask is asserted. In this example, the data mask is asserted (i.e., driven into a logic “1” state) during the first data tenure326. As a result, that data is not written to the memory device. During the second328and third330data tenures, the data mask is deaserted, and the data transmitted on the bus316is written to the memory device. As pointed out earlier, the polarity of an asserted data mask is chosen in this example for convenience of explanation, but may be any polarity in practice. Prior to such as time332, and following, the write operation, the data bus316and data mask318are not loaded, for example, driven into a high impedance state or tri-stated.

FIG. 4is a functional block diagram illustrating an example of a memory device400. The memory device400includes control logic401that receives a CS, RAS, CAS and WE from the memory controller (not shown) and generates the appropriate triggers to perform read and write operations.

The memory device400also includes an address register402which receives an address from the memory controller. The address register402separates the addresses, sending the bank address to bank control logic403, the row address to a multiplexer404, and the starting column address to a column address counter405. The bank control logic403selects the decoders from the row and column address decoders408,410based on the bank address. The multiplexer404multiplexes the row address from the address register402with the output from a refresh counter406to the selected decoder in the row address decoder408. The refresh counter406is used to generate a series of row addresses during a refresh period. The selected decoder in the row address decoder408decodes the row address when it receives a trigger from the control logic401. The decoded row address is provided to the memory array414to open a row in the memory bank controlled by the selected decoder in the row address decoder408.

Once the row is opened in the memory bank, the starting column address is output from the column address counter405when it receives a trigger from the control logic401. Subsequent triggers from the control logic401are used to increment the column address counter405to create a series of column addresses sufficient to access a block of memory in the memory bank row to complete the read or write operation. The column address is provided to the decoder in the column address decoder410selected by the bank control logic405. The selected decoder decodes the column address and provides the decoded address to an I/O and data mask logic unit416. A signal from the control logic401is also provided to the I/O and data mask logic416to indicate whether the bus transaction is a read or write operation. In the case of a read operation, the contents of the memory array414specified by the bank, row, and column address is read into the I/O and data mask logic416before being transmitted to the memory controller by a data bus driver423via a bus driver418. In the case of a write operation, the data on the data bus418is provided to the I/O and data mask logic416by a bus receiver422. The data mask430is also provided to the I/O and data mask logic416by a data mask receiver428. If the data mask is deasserted, the I/O and data mask logic416writes the data to the specified address in the memory array414. If, on the other hand, the data mask is asserted, the data is ignored and the write operation is not performed.

As explained earlier, the data mask is tri-stated except when the memory controller is writing to the memory device400. During that time, the data mask may be used to provide information or some type of notification to the memory controller. In one configuration of the memory device400, the data mask may be used to indicate to the memory controller that there has been a change in status of the memory device400. This concept may be used to eliminate the need of the memory controller to poll the status of the memory device400and provide the memory controller to be event driven. By way of example, and without limitation, the memory device400may use the data mask to indicate a change in temperature. Alternatively, or in addition to, the data mask may be used to indicate a timing error, such as a refresh error. The data mask may also be used to indicate an ECC (error-correcting code) error. Those skill in the art will be readily able to determine the information or the types of notifications best suited for any particular application.

A state machine426, or other entity, is used to monitor changes in the status of the memory device400. When a change is detected, a signal or interrupt is output from the state machine426and provided to the input of a data mask driver424. The state machine426also provides an enable signal470to the data mask driver424. The enable signal470is disabled from the data mask driver424when a write operation is being performed. By disabling the enable signal, the data mask driver424is forced into a tri-state condition, which allows the memory controller to use the data mask during the write operation. In one embodiment, the state machine426includes an internal timer (not shown) whose output controls the enable signal. The internal timer (not shown) is triggered or activated when the WE is asserted and remains activated for a time period sufficient to complete the write operation. The enable signal is removed from the data mask driver424while the internal timer (not shown) is activated.

FIG. 5is a conceptual block diagram illustrating another example of a memory system. In this example, a memory controller502is shown in communication with a two rank memory504over a 32-bit data bus506. The first rank508includes two 16-bit wide memory devices508a-508bconnected together to support a 32-bit bus connection. By way of example, the memory device508amay be used for the lower-order bits and the memory device508bmay be used for the higher-order bits of any bus transaction. The second rank510also includes two 16-bit wide memory devices510a-510bconnected together in a similar fashion. Each memory device508a-508b,510a-510bmay be a single-bank or multiple-bank device.

The signaling and addressing scheme between the memory controller502and the memory504is similar to that described in connection withFIG. 3with the a common CS for each memory device in a rank. This common CS may be referred to as a rank select (RS) because it selects all the memory devices in a rank. In this example, the memory controller502sends an address over the data bus506to the memory devices in the selected rank, and asserts a RAS to open a row in a bank of a memory device and asserts a CAS to read from or write to that row. In the case of a write operation, the memory controller also asserts a WE.

FIG. 6is a conceptual block diagram illustrating an example of the data mask signaling in the memory system ofFIG. 5. A data mask may be provided for each byte lane on the data bus506(seeFIG. 5). Since there are four byte lanes on the bus (i.e., 32-bits), there are four data masks601-604. The memory devices508a,510aconnected to the two byte lanes carrying the lower-order bits receive two data masks601,602. The memory devices508b,510bconnected the two byte lanes carrying the higher-order bits receive the other two data masks603,604. The four data masks601-604are utilized to facilitate the transmission of data between the memory controller502and the memory504when only a portion of the data bus is used. By way of example, a bus transaction may require only the writing of a single byte to the memory504. The memory controller502may perform this bus transaction by transmitting the data on a single byte lane of the data bus and asserting the data masks for the other byte lanes. The data masks are used by the memory rank with the asserted RS to determine which byte lane the data is being transmitted on.

The data masks601-604may also be used by the memory504to indicate a change of status as discussed earlier in connection withFIG. 4. A different data mask may be assigned to each memory device508a-508b,510a-510bto provide a signal or interrupt to the memory controller when a write operation is not being performed. By way of example, the first data mask601may be assigned to the memory device508ahandling the lower-order bits in the first rank508, the second data mask602may be assigned to the memory device510ahandling the lower-order bits in the second rank510, the third data mask603may be assigned to the memory device508bhandling the higher-order bits in the first rank508, and the fourth data mask601may be assigned to the memory device510bhandling the higher-order bits in the second rank510. The memory controller can determine which of the four memory devices508a-508b,510a-510bis sending information or a notification based on the particular data mask carrying the signal or interrupt. All four data masks601-604may not be loaded by the memory devices508a,508b,510a,510bduring a write operation to any of the memory devices. Various methods may be used to ensure that the data masks601-604are not loaded by the memory devices508a,508b,510a,510bduring a write operation including tri-stating the lines, terminating the lines, switching techniques, etc.

FIG. 7is a functional block diagram of a memory device ofFIG. 6. In this example, control logic701receives the RAS, CAS, and WE from the memory controller (not shown). With the RS asserted, the control logic701generates the appropriate triggers to perform read and write operations. The control logic701does not generate any triggers if the RS is deasserted.

The RAS, CAS, and WE are provided to the state machine726regardless of the state of the RS. As explained earlier in connection withFIG. 4, the WE may be used to trigger an internal timer (not shown) that removes the enable signal from the data mask driver728while the internal timer is activated. The internal timer is activated for a period of time sufficient to complete a write operation to a memory device in any rank of the memory system. When the internal timer is not activated, the data mask driver728may be used to send an interrupt or a signal to the memory controller to provide a notification of a change in status.

In one embodiment, the data mask used by the memory device700to indicate a change in status is programmable. In this embodiment, a data mask driver, either data mask driver728or729, are provided for each change in status. As shown inFIG. 7, an equipment manufacturer, distributor, and/or user can select one of the two data mask drivers to act as an interrupt through a program input to the state machine726. In response to the program input, the state machine726may select the data mask driver728by enabling enable signal770to drive data mask730. In particular, the state machine726enables the data mask driver728as long as the internal time (not shown) is activated. By disabling enable signal775, the other data mask driver729is disabled by the state machine726, forcing that data mask driver729into a tri-state condition. A programming change can be made to select the other data mask driver by connecting the internal timer to the other data mask driver729and disabling the original data mask driver728.