Circuit and method to enhance efficiency of semiconductor device

A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

BACKGROUND

The pulse width generator is a control system which is configured to output a narrow and periodical pulse signal. Conventionally, generating an accuracy pulse signal requires to measure the properties of device, which is depend on the pressure, voltage and temperature. Therefore, users should spend a lot of time setting the pulse width generator before generating the accuracy pulse signal.

DETAILED DESCRIPTION

Referring to the figures, wherein like numerals indicate like parts throughout the several views.FIG. 1illustrates a pulse width generator in accordance with some embodiments of the present disclosure. Referring toFIG. 1, a pulse width generator10includes a converter20, a period calculator30, an auto-calibration unit40, a pulse selecting unit51and an output generation unit52. The pulse width generator10may be configured to generate a tunable pulse width output signal53. The pulse width output signal53may be tunable.

In accordance with some embodiments of the present disclosure, the pulse width calculator10further includes a multiplexer11. The multiplexer11is configured to receive a first predetermined clock signal111, a second predetermined clock signal112and a feedback signal113. The first predetermined clock signal111is different from the second predetermined clock signal112. The first predetermined clock signal111has a first predetermined period value T, and the second predetermined clock signal112has a second predetermined period value UT, where U>1. The multiplexer11is controlled by a control signal114from the auto-calibration unit40. The control signal114is used to switch one of the first predetermined clock signal111, the second predetermined clock signal112and the feedback signal113connecting to an output of the multiplexer11. The output of the multiplexer11is connected to an input of the converter20. Therefore, one of the first predetermined clock signal111, the second predetermined clock signal112and the feedback signal113may be inputted to the converter20.

The converter20may be configured for converting a clock signal21to a digital code22, the clock signal21may be one of the three clock signals, the first predetermined clock signal111, the second predetermined clock signal112or the feedback signal113from the multiplexer11. Therefore, the converter20may convert the first predetermined clock signal111to a first predetermined digital code221, and convert the second predetermined clock signal112to a second predetermined digital code, and convert the feedback signal113to a feedback digital code223. Therefore, the digital code22may be the first predetermined digital code221, the second predetermined digital code222, or the feedback digital code223. For brevity, the following paragraphs only describe the first predetermined digital code221and the second predetermined digital code222.

In accordance with some embodiments of the present disclosure, the period calculator30is configured for calculating a period value P according to the digital code22from the converter20. The converter20may convert the first predetermined clock signal111to the first predetermined digital code221, and convert the second predetermined clock signal112to the second predetermined digital code. The period calculator30may receive the first predetermined digital code221and the second predetermined digital code222from the converter20. In accordance with some embodiments of the present disclosure, the period calculator30may calculate a first calculated period value D1according to the first predetermined digital code221, and calculating a second calculated period value D2according to the second predetermined digital code222. The period value P calculated by the period calculator30may be the first calculated period value D1or the second calculated period value D2.

In accordance with some embodiments of the present disclosure, the auto-calibration unit40may be configured for receiving a predetermined pulse width y, and calculating a first pulse width code V corresponding to the predetermined pulse width y according to the first predetermined period value T, the second predetermined period value UT, the first calculated period value D1, the second calculated period value D2and the predetermined pulse width y. The first predetermined period value T and the second predetermined period value UT may be inputted to the auto-calibration unit40, or be transmitted to the auto-calibration unit40by the period calculator30. The first calculated period value D1and the second calculated period value D2are calculated by the period calculator30, then transmitted to the auto-calibration unit40.

In accordance with some embodiments of the present disclosure, the pulse selecting unit51and the output generation unit52are configured for generating the pulse width output signal53according to the first pulse width code V. Since the first pulse width code V is calculated according to the first predetermined period value T, the second predetermined period value UT, the first calculated period value D1, the second calculated period value D2and the predetermined pulse width y, the first pulse width code V may be relative to the factors of the first predetermined period value T, the second predetermined period value UT, the first calculated period value D1, the second calculated period value D2and the predetermined pulse width y. Therefore, the first pulse width code V may be adjusted by the above factors, and the pulse width output signal53may be adjusted by the first pulse width code V.

In accordance with some embodiments of the present disclosure, the feedback signal113is connected to the pulse width output signal53and inputted to the converter20by the multiplexer11. The feedback signal113may be used to further adjust the first pulse width code V and the pulse width output signal53,

FIG. 2illustrates a converter in accordance with some embodiments of the present disclosure. Referring toFIG. 1andFIG. 2, in accordance with some embodiments of the present disclosure, the converter20may be a delayline-based time-to-digital converter (TDC). The converter20is configured for converting the clock signal21to the digital code22. In accordance with some embodiments of the present disclosure, the clock signal21may be the first predetermined clock signal111or the second predetermined clock signal112from the multiplexer11as shown inFIG. 1. Thus, the converter20may convert the first predetermined clock signal111to the first predetermined digital code221, and convert the second predetermined clock signal112to the second predetermined digital code222. Therefore, the digital code22may be the first predetermined digital code221or the second predetermined digital code222after the converter20converts the first predetermined clock signal111or the second predetermined clock signal112.

FIG. 3is a waveform diagram of exemplary sampling signals and digital code in accordance with some embodiments of the present disclosure. Referring toFIG. 2andFIG. 3, in accordance with some embodiments of the present disclosure, the converter20includes a delay line23and a plurality of sampling units24. The delay line23is configured for generating a delay time, and the sampling units24are configured for generating a plurality of sampling signals S0-S9with the delay time. For example, comparing the sampling signal S0and the sampling signal S1, the sampling signal S1is delayed by a delay time than the sampling signal S0. The other sampling signals are similar to the sampling signal S0and the sampling signal S1. In accordance with some embodiments of the present disclosure, the digital code22is generated according to the sampling signals S0-S9and a sampling clock signal25. When the sampling clock signal25is at a high level to sample, the level of the sampling signals S0-S9are obtained to be the digital code22. The digital code includes a plurality of bits, for example, . . . 0111100001. Thus, the period value of the digital code22is 8.

In accordance with some embodiments of the present disclosure, the delay line23is configured for generating the delay time. However, the delay time of the delay line23is various due to pressure, voltage and temperature factors, which may result in errors of the digital code22.

FIG. 4illustrates a converter in accordance with some embodiments of the present disclosure. Referring toFIG. 4, in accordance with some embodiments of the present disclosure, the converter20may be a delayline-based time-to-digital converter (TDC). The converter20includes a plurality of delay units26and a plurality of sense amplifiers27. The delay units26are configured for generating a plurality of delay time, and the sense amplifiers27are configured for generating a plurality of sampling signals with the delay times. Similarly, the converter20inFIG. 4may also generate the digital code22as shown inFIG. 3.

FIG. 5is a waveform diagram of exemplary sampling signals of the sense amplifiers in accordance with some embodiments of the present disclosure. Referring toFIG. 4andFIG. 5, in accordance with some embodiments of the present disclosure, the sense amplifiers24may be used to distinguish the difference when the time difference between the start signal and the stop signal is small.

FIG. 6illustrates a period calculator in accordance with some embodiments of the present disclosure. Referring toFIG. 6, in accordance with some embodiments of the present disclosure, the period calculator30is configured for calculating the period value according to the digital code22from the converter20. In accordance with some embodiments of the present disclosure, since the converter20may convert the first predetermined clock signal111to the first predetermined digital code221, and convert the second predetermined clock signal112to the second predetermined digital code222, the period calculator30may receive the first predetermined digital code221and the second predetermined digital code222from the converter20. In accordance with some embodiments of the present disclosure, the period calculator30may calculate the first calculated period value D1according to the first predetermined digital code221, and calculating the second calculated period value D2according to the second predetermined digital code222. The period value P calculated by the period calculator30may be the first calculated period value D1or the second calculated period value D2.

In accordance with some embodiments of the present disclosure, the period calculator30may include a plurality of input registers31, a gradient descent calculator32, and a comparator33. The input registers31are configured for storing the digital code22and outputting to the gradient descent calculator32.

FIG. 7illustrates a gradient descent calculator in accordance with some embodiments of the present disclosure. Referring toFIG. 6andFIG. 7, the gradient descent calculator32is configured for receiving the digital code22, and shifting the digital code to be a shifted digital code for a plurality of times, and comparing the shifted digital code and a previous shifted digital code before shifting to obtain a plurality of difference values for representing the number of the difference between the shifted digital code and the previous shifted digital code. In accordance with some embodiments of the present disclosure, the gradient descent calculator32includes a plurality of shift registers321, a plurality of comparing elements322, and a sum calculator323. The shift registers321is configured for shifting the digital code for a plurality of times. In accordance with some embodiments of the present disclosure, the digital code is shifted a bit to a right hand side, and a zero bit is filled to the digital code at the first bit of a left hand side. For example, the digital code includes a plurality of bits, and the bits are 11110000. After shifting one time, the bits of the shifted digital code are 01111000.

The comparing elements322are configured for comparing the shifted digital code and the previous shifted digital code. For example, the comparing element322is an XOR element. The shifted digital code has a plurality of bits, and the previous shifted digital code having a plurality of bits. According to the above example, the bits of the shifted digital code are 01111000, and the bits of the previous shifted digital code are 11110000. After comparing the bits of the shifted digital code and those of the previous shifted digital code, the value one is outputted for representing the difference between bits of the shifted digital code and those of the previous shifted digital code, and the value zero is outputted for representing the same bits of the shifted digital code and the previous shifted digital code. According to the above example, since the first bit of the shifted digital code is 0, and the first bit of the previous shifted digital code is 1, the first comparing element322outputs the value one. Furthermore, the fifth bit of the shifted digital code is 1, and the fifth bit of the previous shifted digital code is 0, the fifth comparing element322outputs the value one. The other comparing elements322output the value zero. The sum calculator323is configured for adding the outputs from the comparing elements322to obtain the difference values. According to the above example, for the first shifting, the difference value is two (one plus one). For the plurality shiftings, the difference values may be F(x).

FIG. 8is a diagram illustrating a first simulation result of the difference values. Referring toFIG. 6, andFIG. 8, the comparator33is configured for receiving the difference values and obtaining a first high value M1and a first low value M2from the difference values, and outputting the period value P according to the first high value M1and the first low value M2. In accordance with some embodiments of the present disclosure, if the first low value M2is found, the period value P may be obtained. Therefore, the period value P may be obtained according to the first low value M2.

In accordance with some embodiments of the present disclosure, the difference values F(x) are expressed as:

where N is the length of the digital code, x is the number of clock shift (N≥x≥0), and C[j] is the digital code.

In accordance with some embodiments of the present disclosure, the period calculator30further includes a correlation factor R, the correlation factor R≤N. The correlation factor R may be used for reducing the element in the sum calculator323so as to reduce the cost of the sum calculator323.

FIG. 9illustrates an auto-calibration unit in accordance with some embodiments of the present disclosure. Referring toFIG. 9, the auto-calibration unit40includes a pulse width calculator41. The pulse width calculator41is configured for receiving the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and a predetermined pulse width y, and calculating a first pulse width code V corresponding to the predetermined pulse width y. The first pulse width code V may be calculated according to the first predetermined period value T, the second predetermined period value UT, the first calculated period value D1, the second calculated period value D2and the predetermined pulse width y. The first predetermined period value T and the second predetermined period value UT may be inputted to the pulse width calculator41, or be transmitted to the pulse width calculator41by the period calculator30. The first calculated period value D1and the second calculated period value D1are calculated by the period calculator30, then transmitted to the pulse width calculator41. Therefore, the first pulse width code V may be calculated according to the first predetermined period value T, the second predetermined period value UT, the first calculated period value D1, the second calculated period value D2and the predetermined pulse width y by pulse width calculator41.

FIG. 10is a diagram illustrating simulation results of a transfer curve in accordance with some embodiments of the present disclosure. Referring toFIG. 9andFIG. 10, the pulse width calculator41is configured for calculating an offset value k, the offset value k is expressed as:

where T is the first predetermined period value. UT is the second predetermined period value, and U>1, D1is the first calculated period value, and D2is the second calculated period value. For example, the first predetermined period value T is 200, and the second predetermined period value UT is 250, where U is 1.25. After calculating, the first calculated period value D1is 25, and the second calculated period value D2is 31. Then, the offset value k is

In accordance with some embodiments of the present disclosure, the delay time of the delay line23is calculated by the converter20as shown inFIG. 2. However, the delay time of the delay line23is various due to pressure, voltage and temperature factors, which may not synchronize with PLL (Phase Loop Lock) to generate an absolute wanted value. Moreover, the first calculated period value D1calculated by the converter20and the period calculator30according to the first predetermined clock signal may not be equal to the first predetermined period value T of the first predetermined clock signal, and the second calculated period value D2calculated by the converter20and the period calculator30according to the second predetermined clock signal may not be equal to the second predetermined period value UT of the second predetermined clock signal.

In accordance with some embodiments of the present disclosure, the pulse width calculator41is configured for calculating a linear extrapolation equation of a transfer curve45, the linear extrapolation equation is expressed as:

where y is the predetermined pulse width, and is user wanted pulse width, V is the first pulse width code.

Based on the linear extrapolation equation of the transfer curve45, the first pulse width code V is expressed as:

Where the value y/T is the ratio of the predetermined pulse width y to the first predetermined period value T. Therefore, the linear extrapolation equation of the transfer curve45may be used to compensate the various delay time due to pressure, voltage and temperature factors so as to obtain an exact pulse width generation. Further, the linear extrapolation equation of a transfer curve45may be performed each time to calculate the first pulse width code V instead of one shoot only for each condition in the prior art. For example, the predetermined pulse width y is 50. According to the above example, the first pulse width code V is

In accordance with some embodiments of the present disclosure, the auto-calibration unit40further includes a first operator for comparing the first pulse width code and a check value. The check value E is the number of 1 of bits of the feedback signal113. The auto-calibration unit40further includes a second operator for calculating a modified value M, wherein the modified value is equal to the first pulse width code V minus the check value E, M=V−E.

In accordance with some embodiments of the present disclosure, the pulse width calculator41is configured for calculating a second pulse width code W, the second pulse width code W is expressed as:

where M is the modified value. For example, the modified value M is 1. According to the above example, the second pulse width code W is 8 (7+1).

Referring toFIG. 9andFIG. 1, in accordance with some embodiments of the present disclosure, the pulse selecting unit51and the output generation unit52are configured for generating the pulse width output signal53according to the first pulse width code V or the second pulse width code W. The feedback signal113is connected to the pulse width output signal53and inputted to the converter20by the multiplexer11.

FIG. 11is a flow diagram showing a method of generating a pulse width output signal in accordance with some embodiments of the present disclosure. Referring toFIG. 1andFIG. 12, in step S61, the first predetermined clock signal111and the second predetermined clock signal112is inputted to the converter20. The first predetermined clock signal111and the second predetermined clock signal112may be inputted to the multiplexer11, then by the control signal114, the first predetermined clock signal111and the second predetermined clock signal112are inputted to the converter20.

In step S62, using the converter20the first predetermined clock signal111is converted to the first predetermined digital code221, and the second predetermined clock signal112is converting to the second predetermined digital code222. The first predetermined digital code has the first predetermined period value T, and the second predetermined digital code has the second predetermined period value UT.

In step S63, using the period calculator30the first calculated period value is calculated according to the first predetermined digital code221and a second calculated period value is calculated according to the second predetermined digital code222.

In step S64, using the auto-calibration unit40the first pulse width code V is calculated according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and a predetermined pulse width y.

In step S65, using the pulse selecting unit51and an output generation unit52the pulse width output signal53is generated according to the first pulse width code.

In some embodiments, a circuit is disclosed, including: a gradient descent calculator and a comparator. The gradient descent calculator is configured for receiving a digital code, and shifting the digital code to be a shifted digital code for a plurality of times, and comparing the shifted digital code and a digital code to obtain a plurality of difference values for representing the number of the difference between the shifted digital code and the previous shifted digital code. The comparator is configured for receiving the difference values and obtaining a first low value from the difference values, and outputting a period value according to the first low value.

In some embodiments, a circuit is disclosed, including: a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

In some embodiments, a method is disclosed, including: inputting a first predetermined clock signal and a second predetermined clock signal in sequence; converting the first predetermined clock signal to a first predetermined digital code, and converting the second predetermined clock signal to a second predetermined digital code, the first predetermined digital code having a first predetermined period value, and the second predetermined digital code having a second predetermined period value; calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code; calculating a first pulse width code according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and an predetermined pulse width and generating a pulse width output signal according to the first pulse width code.