Averaging overcurrent protection

In some embodiments, a power amplification system can comprise a current source configured to provide a bias current, a current mirror configured to mirror the bias current, a comparator configured to compare the mirrored bias current to a threshold current, and a transistor at an output of the comparator. The transistor can be configured to be activated in response to the mirrored bias current exceeding the threshold current.

BACKGROUND

Field

The present disclosure relates to power amplifier circuits, related devices, and related methods for radio-frequency (RF) applications.

Description of the Related Art

Some power amplifier circuits include integrated duplex filters. Often, duplex filters and/or other components of power amplifier circuits can be sensitive to damage from various factors such as process variation and temperature in such a way as to decrease the overall performance of the circuit.

SUMMARY

In accordance with some implementations, the present disclosure relates to a power amplification system comprising a current source configured to provide a bias current, a current mirror configured to mirror the bias current, a comparator configured to compare the mirrored bias current to a threshold current, and a transistor at an output of the comparator. The transistor is configured to be activated in response to the mirrored bias current exceeding the threshold current.

In some embodiments, the bias current can represent an average current received at the power amplification system. In some embodiments, the threshold current can be temperature-compensated to correct for current gain variation. In some embodiments, the current source can be configured to trim the threshold current value independently for each band of the power amplification system. In some embodiments, the current mirror can include a first current mirror providing a 50:1 current ratio, a second current mirror providing a 2:1 current ratio, and a third current mirror providing a 2:1 current ratio. In some embodiments, the power amplification system can further comprise a converter configured to generate the threshold current.

In some embodiments, the power amplification system can further comprise a capacitor configured to integrate error current from the comparator. The capacitor can be configured to build charge in response to the mirrored bias current exceeding the threshold current value. In some embodiments, the capacitor can be configured to reset when there is a mode change. In some embodiments, the capacitor can be in series with a switch to ground. In some embodiments, the power amplification system can further comprise an edge counter. In some embodiments, each of the comparator, the transistor, the edge counter, and the capacitor can be integrated on a first circuit die.

In some embodiments, the current source can be a regulator. In some embodiments, the current source can provide the bias current to an output stage of the power amplification system.

In some teachings, the present disclosure relates to a method of managing current in a power amplifier. The method comprises providing a bias current to the power amplifier, mirroring the bias current at an output stage of the power amplifier, applying the mirrored bias current to a filter network to create a filtered voltage waveform, comparing a sensed voltage to a threshold voltage, and, in response to the sensed voltage exceeding the threshold voltage, activating a transistor to redirect at least a portion of the bias current away from the power amplifier.

In some embodiments, redirecting the bias current can cause reduction of a gain value of the power amplifier. Reduction of the gain value can cause reduction of output power of the power amplifier and reduction of output power can cause reduction of final stage base current of the power amplifier. In some embodiments, the bias current can represent an average current received at the power amplifier. In some embodiments, the threshold voltage can be temperature-compensated to correct for gain variation. In some embodiments, mirroring the bias current can include applying the bias current to a current mirror having a first current mirror providing a 50:1 current ratio, a second current mirror providing a 2:1 current ratio, and a third current mirror providing a 2:1 current ratio.

In some embodiments, the method can further comprise integrating error current to build a charge on capacitor in response to the sensed voltage exceeding the threshold voltage. In some embodiments, the capacitor can be configured to reset when there is a mode change. In some embodiments, the capacitor can be in series with a switch to ground.

In some embodiments, the method can further comprise providing the bias current to an output stage of the power amplifier. In some embodiments, the method can further comprise, in response to the sensed voltage exceeding the threshold voltage, providing a feedback signal to a driver stage of the power amplifier to limit the bias current.

In some implementations, the present disclosure relates to a circuit comprising a current source configured to provide a bias current, a current mirror configured to mirror the bias current, a comparator configured to compare the mirrored bias current to a threshold current, and a transistor at an output of the comparator. The transistor is configured to be activated in response to the mirrored bias current exceeding the threshold current.

DESCRIPTION

There is increasing demand for both higher transmission powers and lower size/cost of computing devices, including front-end module devices (e.g., smartphones, laptop/desktop computers, tablets, etc.). Some computing devices integrate duplex filters (i.e., duplexers) in a signal path between a power amplifier and an antenna of the device. However, duplex filters (e.g., temperature-compensated surface acoustic wave (TC-SAW) devices) have a finite amount of power handling and generally have lower ruggedness characteristics than other components of a signal path. The issue of duplex filter ruggedness is of particular concern for devices incorporating Carrier Aggregation, which may drive higher insertion loss and higher transmission power levels than other devices. When a device having an integrated duplex filter is subjected to excessively high powers (especially at high temperatures), the power dissipation of the device can lead to physical damage of the filter structure of the device. In order to protect the filter, some devices deliver only a limited amount of power to the filter.

Some methods for protecting filters involve utilizing a current limiting function to establish a peak (i.e., maximum) current and/or power limit. However, limiting peak current values may be less effective in protecting duplex filters than limiting average current values. This may be particularly true in the case of complex waveforms having relatively high modulation. For example, complex waveforms supported by Long-Term Evolution (LTE) and 5G standards may have a difference of over 6 dB between peak and average power levels while the margin between average power operation and potential damage conditions of modern duplex filters can be less than 6 dB. For a peak limiting function to be effective, a relatively low peak limit must be set, which may cause distortion in the waveform. Accordingly, solutions which respond to peak power levels may be challenged to maintain normal operating performance while protecting the duplex filter. A solution providing an ability to control average power while allowing for relatively high peak-to-average waveform characteristics is needed.

Insertion loss can increase at the high end of a frequency range for a filter (e.g., near the transition band). Increased insertion loss in a filter can cause more power dissipation within the filter, which can lead to higher temperatures. For some filters (e.g., surface acoustic wave devices), frequency response tends to shift down in frequency as the device temperature increases. Moreover, as the temperature of a device increases, more insertion loss is introduced which in turn translates to more power dissipation and more heating. In this way, some filters may experience positive feedback which may cause significant dissipation of energy and damage to the filter.

Some devices (e.g., cell phones) may frequently operate at power levels that may cause damage to filters in the devices if sustained for an extended period of time. For example, high power levels may be needed for calibration as well as to support peak-to-average waveforms. A filter may have a certain stress level such that extended application of power levels above the certain stress level may damage the filter. In some cases, periods of high stress (e.g., above a filter's stress level) that are approximately 300 ms or longer may cause damage to the filter. Accordingly, some embodiments described herein may be capable of operating at power levels above a filter's stress level while preventing extended operation (e.g., 300 ms) above the stress level in order to prevent damage to the filter. Calibration process periods may vary device-to-device. In some embodiments, high stress periods (e.g., operating above a filter's stress level) may be limited to approximately 10 ms.

In some embodiments, power delivered to a filter may be detected via forward power detection at the filter. However, forward power detection may require a radio frequency (RF) filter that is much more complex and expensive in terms of die area and current drain than other filters which may be used. In some embodiments, power may be detected using collector current (e.g., total output current) of the power amplifier because collector current is directly related to power. However, using collector current may require insertion of an element in series with the high current flow path, which can impact gain and efficiency.

Some embodiments described herein provide low-cost methods for autonomously limiting power delivered to filters and thereby protecting the filter from damage, particularly in extreme (e.g., high power) operation conditions. Some embodiments involve indirectly detecting average output power and providing a feedback signal into a driver stage device which may be capable of limiting the average power delivered to the filter. Because transmit power of a power amplifier may be correlated to bias current within the power amplifier, by limiting the bias current in the power amplifier, the power delivered to the load of the power amplifier can be effectively limited.

Some embodiments provide, through use of a relatively long time constant, a capability of driving high powers for several milliseconds before internally reducing gain to protect the filter from damage. The time constant for a filter comprising a resistor and capacitor network is the product of the resistance and capacitance of the network. If a step function is applied to the filter, the output voltage follows the equation VOUT=VIN*(1−e(t/RC)). A relatively large RF signal can act as a step function for the network and it can take time for the output of the filter to charge a capacitor of the network and engage the protection loop. The charging time is defined by the network time constant. A capacitor may charge to 95% of a final charge value in a period of time equivalent to three successive time constant periods. For a low-pass filter, a 3 dB bandwidth can be found using the following formula for cutoff frequency (FC): FC=1/(2*πRC). Accordingly, any signal content at frequencies greater than FCcan be attenuated and any signals lower than FCcan pass through. The DC value is lower than FCand therefore passes through to deliver the average value of the signal. In this way, the time constant can provide an averaging function which can allow a feedback loop to respond to average power, thereby supporting high peak-to-average ratios of complex waveforms.

Utilizing the indirect relationship between heterojunction bipolar transistor (HBT) power amplifier output power and final stage (e.g., output stage) base current, an analog buffer circuit can be used to source the base bias current to the amplifier final stage and sense the current by means of mirroring it at a ratio of 200:1 on a CMOS companion die. The mirrored current can then be compared against a current limit threshold current through current subtraction. Resulting error current can be integrated with a large value capacitance. During extreme operating conditions, the base current can exceed the threshold and cause the feedback circuitry to reduce the reference bias current for the driver stage amplifier. Reduction of the bias current results in reduced gain which reduces the output power and likewise the final stage base current. Given that the relationship between power and base current is a function of HBT device current gain (i.e., beta), radio frequency signal loss can vary between devices and operating bands, and on-die resistance can vary with process. The threshold can be trimmed at a final test. The threshold can be temperature-compensated to correct for HBT beta variation over ambient temperature.

By allowing a limiting circuit to respond to average power rather that peak power, system margin may be increased, particularly for waveforms having a high peak-to-average characteristic. Some embodiments may utilize simple direct current (DC) sensing technologies, thereby avoiding use of complex radio frequency detectors (which can drive more complex silicon process technologies) and increased input/output and interfacing between the HBT and silicon control die.

In certain embodiments, a device may include an HBT. In some cases, there can be a relationship between collector current (i.e., total output current) and the base current of an HBT. Therefore, the base current may be used to indirectly detect forward power (which is related to current). The relationship between base current and collector current is a function of beta (i.e., current gain). Beta varies with temperature and process. Accordingly, in order to use base current detection, it is necessary to compensate for temperature and also perform process trimming to obtain accurate device-to-device detection.

With respect to detector current, the base current (or collector current) is a representation of the instantaneous envelope power. A peak-to-average characteristic or a crest factor for many waveforms may be around 4 decibels.

FIG. 1provides a graph showing output power as a function of input power for an example power amplifier. A typical power amplifier may have approximately 26-28 decibel-milliwatts (dBm) gain. In order for linear operation, it may be required to operate below the compression characteristic of the amplifier. As shown inFIG. 1, operation may be backed off approximately 4-6 dBm below the compression characteristic to cause an approximately 4 dBm peak-to-average characteristic of the waveform. Accordingly, the waveform may transition along the 4 dBm peak-to-average on the gain profile.

FIG. 2provides a graph showing base bias current values as a function of output power over a power window. As shown inFIG. 2, operating along 24-28 dBm power may correlate to 4-6 mA of base bias current. As the amplifier moves beyond the target operation range (e.g., to 31 or 32 dBm), a base current of 8-12 mA may be reached.

FIG. 3illustrates a power amplifier circuit30for providing a peak base current limiting function. The circuit30comprises an HBT32including a power transistor34and an emitter follower36. The collector of the emitter follower36receives a limiting current (“llimit”) that is representative of the base current for the final stage of the power amplifier circuit30. If the power amplifier circuit30draws more base current than the limiting current, the bias in the emitter follower36may collapse and the current of the power amplifier circuit30may no longer increase with increased power. By modifying the limiting current, it can be determined how the limiting current impacts the power amplifier waveform characteristics in terms of linearity and gain and also whether there are ruggedness improvements in the filter.

In some cases, gain characteristics may be a function of current limiting. For example, by lowering the limiting current, there may be an effective limit of power (e.g. at 29 dBm). Conversely, as the limiting current increases, a power amplifier may be capable of delivering higher and higher power levels.

When current limiting is used, an effective current (e.g., base current) may level out when it exceeds a limiting value (e.g., 9.5 mA). When current limiting is disabled, the effective current may continue well above the limiting value. For a device including a filter, a current limiting function can cause drastic changes in power (and possibly filter failure) when a given phase angle is reached. However, a current limiting function that includes components for limiting forward power may provide relatively high ruggedness performance. In some cases, focusing on average current may provide for better prediction of average power delivered to a device.

FIG. 4provides a schematic diagram of a circuit40comprising a power amplifier42. The power amplifier42includes an emitter follower44connected to a filter system46which transfers base current to a voltage across a 150 killi-ohm (kΩ) resistor and then applies a resistor-capacitor (RC) filter comprising a 10 kΩ resistor and a 0.1 μF capacitor.

FIG. 5provides a schematic diagram of a circuit50comprising a power amplifier bias interface. As shown inFIG. 5, a battery voltage source (“Vbatt”)54may provide a collector voltage to an emitter follower56. The emitter follower56may provide a base current to a power amplifier52. By providing a regulated voltage to the Vbatt54signal, the amount of current being sourced to the Vbatt54from the regulator can be monitored. A reference current (IREF) signal may set up a quiescent bias for the power amplifier52. If the IREF is stolen away from the power amplifier52, the quiescent current and gain of the power amplifier52may be reduced. By reducing the gain, the output power and the sensed base current may be reduced.

FIG. 6provides a schematic diagram of a power amplifier60for limiting average base current. The power amplifier60includes a regulator62providing a bias to the power amplifier60. In some cases, the regulator62may provide a 2.5 volt (V) bias to the power amplifier60. The current of the power amplifier60may be mirrored through use of one or more current mirrors. As shown inFIG. 6, the power amplifier60may include a first current mirror64a(e.g., providing a 50:1 current ratio), a second current mirror (e.g., providing a 2:1 current ratio), and a third current mirror (e.g., providing a 2:1 current ratio), creating an effective ratio of 200:1 for the power amplifier60. For example, if a base current for the power amplifier60is 5 mA, a nominal 20 μA sense signal may be processed. The 20 μA sense signal may be used to either generate and filter a voltage or perform an integration on a current comparison circuit.

In one embodiment, the mirrored current may be applied to a 50 kΩ resistor66in parallel with a large value capacitance68(e.g., a 0.1 μF capacitor) to create a filtered voltage waveform. The sensed voltage may be compared through use of a comparator63to a threshold voltage (“Vthresh”). If the sensed voltage exceeds the threshold voltage, a transistor65at the output of the comparator63can be activated, thereby redirecting at least a portion of the bias current from the power amplifier60to reduce the gain of the power amplifier60.

Current may be sourced to the base, sensed, and compared against a threshold. If the threshold is exceeded, reference current is taken which in turn reduces the base current and drops the sensed voltage below the threshold voltage.

Because beta is temperature-varying, in some embodiments, a threshold value may be temperature-compensated. For example, as temperature increases, the threshold may increase (e.g., a base current threshold may increase) because beta decreases with increasing temperature. A threshold may have multiple settings. For example, each band of a power amplifier can have different gain characteristics and there may be different matching characteristics in the output match to a duplexer, and/or the duplexer filter itself may have different ruggedness levels. Accordingly, some embodiments may be configured to trim a threshold value to set the threshold independently for each of the bands. As the power amplifier is configured for a first band, a first threshold associated with the first band may be used and as the power amplifier is changed for a different band, a different threshold may be used.

In some cases, there may be a delay period for detecting that a threshold is exceeded. For example, for a power amplifier having a 0.1 μF capacitance, it may take approximately 10 ms before a device detects that the threshold is exceeded and the device begins trimming the output power. Different capacitance values may result in different response times.

FIG. 7shows a schematic diagram of a current comparison device70. The device70comprises a comparator73that may be configured to compare a sensed current to a current reference. The current reference/threshold may be generated by a temperature-compensated current digital-to-analog converter (DAC)75. A capacitor78(e.g., a 0.1 μF capacitor) may effectively integrate an error current. If the sensed current exceeds the threshold current then charge can build on the capacitor78and eventually the sensed current may exceed the threshold current at the comparator73and the current may be reduced. The DAC current may be temperature-compensated and selectable between multiple band settings.

FIG. 8provides a schematic diagram of a circuit80for averaging overcurrent protection. A capacitor may require a period of time (e.g., approximately 10 ms) to charge. In some power amplifiers, a charge stored at a capacitor (e.g., the capacitor78inFIG. 7) can impact operation of the power amplifier when the state of the amplifier is changed. For example, if operation is changed to a different band, any charge stored on the capacitor could potentially impact operation of the new band. In some embodiments, a provision may be utilized to reset the capacitor when there is a mode change in the power amplifier. As shown inFIG. 8, the power amplifier80may comprise a switch85to ground on the capacitor88so that when a mode change or bias change occurs, any charge on the capacitor88is removed and the system80is reset to allow for operating from a known starting point in the new mode.

FIG. 9provides a schematic diagram representing a current monitoring device90with reduced capacitor magnitude. In some embodiments, due to the size of the capacitor (e.g., a 0.1 μF or 0.01 μF capacitance), the capacitor must be discrete and may be situated external to the integrated circuit of the device. However, through use of an edge counter92, capacitance may be integrated on the circuit die. For example, as shown inFIG. 9, the device90may comprise a 250 kΩ resistor94and a 100 pF capacitor96. Using an edge counter92, it can be determined how many times the reference current charges up to the threshold. By setting the number of edge counts, the time constant can be multiplied by the number of edge counts. A time constant of the reference current may be multiplied.

FIG. 10shows a schematic diagram of an interface between a control die101and an HBT103. The control die101comprises a filter/trim circuit105that provides a base bias current (“Ibias”) to the final stage of the HBT103. An error current at a capacitor107may be integrated and when an error voltage exceeds the band gap in a comparator109, a reference current (“IRef1”) in the power amplifier is reduced. The closed loop system works to reduce gain of the driver stage of the amplifier based on the sensed current in the final stage.

In some embodiments, the power amplifier may be adjusted to a target power threshold based on the needs of the system. Threshold bits in the current clamp architecture may be adjusted until output power is reduced, indicating that the power that the amplifier is set to is equivalent to the threshold of the loop. The target power threshold may be written and/or burned into the die and a calibrated threshold may be set for each band.

FIG. 11shows a process1100for limiting average current values at a power amplifier that can be implemented with embodiments herein. Steps of the process1100may be performed in any order and in some cases steps may be removed and/or added as needed.

In block1102, a bias current may be generated. In some embodiments, the bias current may represent an average current value of the power amplifier.

In block1104, the bias current may be mirrored. In some embodiments, mirroring may involve delivering the bias current to multiple current mirrors. For example, the power amplifier may comprise three current mirrors providing variable current ratios.

In block1106, the mirrored bias current may be compared to a threshold current. The comparison may be performed at a comparator. In some embodiments, the threshold current may be temperature-compensated and/or may be individually set for each band of the power amplifier.

In decision block1108, it is determined whether the mirrored bias current exceeds the threshold current. If the threshold is exceeded, in block1110the bias current may be reduced. In some embodiments, bias current may be redirected to reduce the bias current of the power amplifier. If the threshold is not exceeded, in block1112the bias current level may be maintained.

FIG. 12shows that in some embodiments, some or all of a front-end architecture having one or more features as described herein can be implemented in a module. Such a module can be, for example, a front-end module (FEM). In the example ofFIG. 12, a module300can include a packaging substrate302, and a number of components can be mounted on such a packaging substrate. For example, a control component102, a power amplifier assembly104, an antenna tuner component106, and a duplexer assembly108can be mounted and/or implemented on and/or within the packaging substrate302. Other components such as a number of SMT devices304and an antenna switch module (ASM)306can also be mounted on the packaging substrate302. Although all of the various components are depicted as being laid out on the packaging substrate302, it will be understood that some component(s) can be implemented over other component(s).

In some implementations, a device and/or a circuit having one or more features described herein can be included in an RF device such as a wireless device. Such a device and/or a circuit can be implemented directly in the wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, etc.

FIG. 13depicts an example wireless device400having one or more advantageous features described herein. In the context of a module having one or more features as described herein, such a module can be generally depicted by a dashed box300, and can be implemented as, for example, a front-end module (FEM).

Referring toFIG. 13, power amplifiers420can receive their respective RF signals from a transceiver410that can be configured and operated in known manners to generate RF signals to be amplified and transmitted, and to process received signals. The transceiver410is shown to interact with a baseband sub-system408that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver410. The transceiver410can also be in communication with a power management component406that is configured to manage power for the operation of the wireless device400. Such power management can also control operations of the baseband sub-system408and the module300.

The baseband sub-system408is shown to be connected to a user interface402to facilitate various input and output of voice and/or data provided to and received from the user. The baseband sub-system408can also be connected to a memory404that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user.

In the example wireless device400, outputs of the PAs420are shown to be routed to their respective duplexers420. Such amplified and filtered signals can be routed to an antenna416through an antenna switch414for transmission. In some embodiments, the duplexers420can allow transmit and receive operations to be performed simultaneously using a common antenna (e.g.,416). InFIG. 13, received signals are shown to be routed to “Rx” paths (not shown) that can include, for example, a low-noise amplifier (LNA).

As described herein, one or more features of the present disclosure can provide a number of advantages when implemented in systems such as those involving the wireless device ofFIG. 13. For example, a controller102, which may or may not be part of the module300, can monitor base currents associated with at least some of the power amplifiers420. Based on such monitored base currents, an antenna tuner106(which may or may not be part of the module300), can be adjusted to provide a desired impedance to the corresponding power amplifier.

Some aspects of the systems and methods described herein can advantageously be implemented using, for example, computer software, hardware, firmware, or any combination of computer software, hardware, and firmware. Computer software can comprise computer executable code stored in a computer readable medium (e.g., non-transitory computer readable medium) that, when executed, performs the functions described herein. In some embodiments, computer-executable code is executed by one or more general purpose computer processors. A skilled artisan will appreciate, in light of this disclosure, that any feature or function that can be implemented using software to be executed on a general purpose computer can also be implemented using a different combination of hardware, software, or firmware. For example, such a module can be implemented completely in hardware using a combination of integrated circuits. Alternatively or additionally, such a feature or function can be implemented completely or partially using specialized computers designed to perform the particular functions described herein rather than by general purpose computers.

Multiple distributed computing devices can be substituted for any one computing device described herein. In such distributed embodiments, the functions of the one computing device are distributed (e.g., over a network) such that some functions are performed on each of the distributed computing devices.

Some embodiments may be described with reference to equations, algorithms, and/or flowchart illustrations. These methods may be implemented using computer program instructions executable on one or more computers. These methods may also be implemented as computer program products either separately, or as a component of an apparatus or system. In this regard, each equation, algorithm, block, or step of a flowchart, and combinations thereof, may be implemented by hardware, firmware, and/or software including one or more computer program instructions embodied in computer-readable program code logic. As will be appreciated, any such computer program instructions may be loaded onto one or more computers, including without limitation a general purpose computer or special purpose computer, or other programmable processing apparatus to produce a machine, such that the computer program instructions which execute on the computer(s) or other programmable processing device(s) implement the functions specified in the equations, algorithms, and/or flowcharts. It will also be understood that each equation, algorithm, and/or block in flowchart illustrations, and combinations thereof, may be implemented by special purpose hardware-based computer systems which perform the specified functions or steps, or combinations of special purpose hardware and computer-readable program code logic means.

Furthermore, computer program instructions, such as embodied in computer-readable program code logic, may also be stored in a computer readable memory (e.g., a non-transitory computer readable medium) that can direct one or more computers or other programmable processing devices to function in a particular manner, such that the instructions stored in the computer-readable memory implement the function(s) specified in the block(s) of the flowchart(s). The computer program instructions may also be loaded onto one or more computers or other programmable computing devices to cause a series of operational steps to be performed on the one or more computers or other programmable computing devices to produce a computer-implemented process such that the instructions which execute on the computer or other programmable processing apparatus provide steps for implementing the functions specified in the equation(s), algorithm(s), and/or block(s) of the flowchart(s).