Adjustable phase shifter

A method includes determining a phase error for a first clock signal and a second clock signal and determining an offset based on the phase error for the first clock signal and the second clock signal. The method also includes adding the offset to a phase of the first clock signal to produce a first adjusted clock signal and subtracting the offset from a phase of the second clock signal to produce a second adjusted clock signal. A phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.

The following disclosure(s) are submitted under 35 U.S.C. 102(b)(1)(A):

BACKGROUND

The present invention relates to phase shifting, and more specifically, to an adjustable phase shifter.

SUMMARY

According to an embodiment, a method includes determining a phase error for a first clock signal and a second clock signal and determining an offset based on the phase error for the first clock signal and the second clock signal. The method also includes adding the offset to a phase of the first clock signal to produce a first adjusted clock signal and subtracting the offset from a phase of the second clock signal to produce a second adjusted clock signal. A phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.

According to another embodiment, a phase adjustor includes first adjustor, a second adjustor, and a control line connected to the first adjustor and the second adjustor. The first adjustor produces a first adjusted clock signal by adding an offset to a phase of a first clock signal if a control signal on the control line is high and subtracting the offset from the phase of the first clock signal if the control signal is low. The second adjustor produces a second adjusted clock signal by subtracting the offset from a phase of a second clock signal if the control signal is high and adding the offset to the phase of the second clock signal if the control signal is low. The offset is determined based on a phase error for the first clock signal and the second clock signal.

According to another embodiment, a method includes determining an offset based on a phase error for a first clock signal and a second clock signal, toggling a first switch such that the offset is added to a phase of the first clock signal to produce a first adjusted clock signal, and toggling a second switch such that the offset is subtracted from a phase of the second clock signal to produce a second adjusted clock signal. A phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.

DETAILED DESCRIPTION

Phase adjustors may be used to adjust the phases of signals (e.g., to shift the phases of clock signals). Adjusting the phases of these signals may correct phase errors in these signals. Different signals, however, may have a relative phase error that results from delay in the different signal paths or component mismatches in these signal paths. Due to these relative phase errors, adjusting the phase of one signal may introduce phase errors in other signals.

This disclosure describes a phase adjustor that shifts the phases of two signals by the same amount but in different directions. For example, the phase adjustor may add an offset to the phase of a first signal and subtract the offset from the phase of a second signal. In this manner, phase error (including relative phase error) for these two signals may be corrected by adjusting the phases of both signals, rather than adjusting the phase of only one of the signals.

FIG.1illustrates an example system100. As seen inFIG.1, the system100includes a sampler102, a phase adjustor104, and a controller106. Generally, the sampler102samples a data signal according to one or more clock signals provided to the sampler102. The phase adjustor104and the controller106work together to adjust one or more clock signals to correct phase errors for those clock signals. In particular embodiments, the phase adjustor104and/or the controller106correct relative phase errors for clock signals by adjusting the phases of the clock signals by the same amount, but in different directions. The phase adjustor104provides the adjusted clock signals to the sampler102.

The sampler102samples a data signal118to produce one or more sampled data signals120. The sampler102samples the data signal118according to one or more received clock signals. For example, the sampler102may sample the data signal118on edges (e.g., rising or falling edges) of a received clock signal to produce a sampled data signal120. The sampler102may produce a sampled data signal120for each received clock signal. If the received clock signals have different phases, then the sampled data signals120may be staggered in time based on the phase differences between or amongst the received clock signals. The sampled data signals120may then be combined to produce a representation of the data signal118. For example, the sampled data signals120may be combined to produce a digital representation of the data signal118. The sampler102may sample the data signal118according to any number of clock signals to produce any number of sampled data signals120.

The phase differences between or amongst the received clock signals may be controlled or coordinated, such that the sampler102samples the data signal118at particular points in time. For example, the received clock signals may be controlled or coordinated, such that the received clock signals are 90 degrees out of phase. The sampler102then samples the data signal118during the rising or falling edges of the received clock signals. Due to the controlled phase differences between or amongst the received clock signals, the sampler102samples the data signal118at particular points in time to produce the sample data signals120.

Due to delays in the signal path or component mismatches in the clock generation circuitry, the received clock signals may include phase errors. Additionally, the received clock signals may have relative phase errors that affect the sampling of the data signal118. These phase errors, if uncorrected, may cause the sampler102to sample the data signal118at less than optimal times, which may result in the sampled data signals120having less signal strength or signal quality.

The phase adjustor104and the controller106operate together to adjust the phases of received clock signals108. The phase adjustor104produces one or more adjusted clock signals110that are then communicated to the sampler102. The sampler102then samples the data signal118according to the adjusted clock signals110. The phase adjustor104and the controller106may adjust the phases of the one or more clock signals108to correct phase errors for the clock signals108. In this manner, the adjusted clock signals110have corrected phases so that the sampler102samples the data signal118at the appropriate times, in particular embodiments.

The phase adjustor104receives one or more clock signals108. In the example ofFIG.1, the phase adjustor104receives clock signals108A,108B,108C, and108D. The clock signals108may have been generated by a clock generation circuit. The phase adjustor104adjusts the phases of one or more of the clock signals108to produce the adjusted clock signals110. Generally, the phase adjustor104adjusts the phases of the clock signals108in pairs. The phase adjustor104may add an offset to the phase of a clock signal108while subtracting the offset from the phase of another clock signal108. As a result, the phase adjustor104shifts the phases of the two clock signals108by the same amount in different directions. In this manner, the phase adjustor104may adjust the phases of the clock signals108while accounting for relative phase error between the two clock signals108.

The controller106receives the adjusted clock signals110and detects phase errors and relative phase errors in the adjusted clock signals110. The controller106then determines one or more offsets to be added to or subtracted from the phases of one or more clock signals108. The controller106then generates control bits112that are communicated to the phase adjustor104. The phase adjustor104then interprets the control bits112to adjust the phases of one or more clock signals108using the offset determined by the controller106. For example, the controller106may determine that the clock signals108A and108C should be 180 degrees out of phase with one another and that the clock signals108B and108D should be 180 degrees out of phase with one another. The controller106analyzes the clock signals108B and108D to determine that they are 178 degrees out of phase with one another. The controller106then adjusts the control bits112so that the phase adjustor104shifts the phases of the clock signals108B and108D by the same amount in different directions. For example, the phase adjustor104may add an offset (e.g., 1 degree) to the phase of the clock signal108B and subtract the offset from the phase of the clock signal108D. In this manner, the controller106brings the clock signals108B and108D closer to being 180 degrees out of phase with one another. As seen inFIG.1, the controller106includes a processor114and a memory116, which are configured to perform any of the functions of the controller106described herein.

The processor114is any electronic circuitry, including, but not limited to one or a combination of microprocessors, microcontrollers, application specific integrated circuits (ASIC), application specific instruction set processor (ASIP), and/or state machines, that communicatively couples to memory116and controls the operation of the controller106. The processor114may be 8-bit, 16-bit, 32-bit, 64-bit or of any other suitable architecture. The processor114may include an arithmetic logic unit (ALU) for performing arithmetic and logic operations, processor registers that supply operands to the ALU and store the results of ALU operations, and a control unit that fetches instructions from memory and executes them by directing the coordinated operations of the ALU, registers and other components. The processor114may include other hardware that operates software to control and process information. The processor114executes software stored on the memory116to perform any of the functions described herein. The processor114controls the operation and administration of the controller106by processing information (e.g., information received from the phase adjustor104and the memory116). The processor114is not limited to a single processing device and may encompass multiple processing devices.

FIG.2illustrates an example phase adjustor104in the system100ofFIG.1.

As seen inFIG.4, the phase adjustor104includes resistors201A and201B, a plurality of switches202, a plurality of inverters204, and a plurality of capacitors C1P, C1N, C2P, C2N, CNP, CNN. These components operate according to one or more control bits112to adjust the phases of one or more clock signals108to produce one or more adjusted clock signals110. In particular embodiments, the phase adjustor104adjusts the phases of two clock signals108relative to each other to correct phase errors for the clock signals108. In some embodiments, the phase adjustor104includes additional components (e.g., transistors, switches, current sources, etc.) that are not illustrated inFIG.2to implement an inverter-based programmable delay line or current-mode logic (CIVIL)-based delay structure.

Generally, the switches202couple one or more of the capacitors to a resistor201A or201B to introduce RC delay to a corresponding clock signal108, which adjusts the phase of the clock signal108to produce an adjusted clock signal110. In the example ofFIG.2, the phase adjustor104adjusts the phases of clock signals108B and108D relative to each other to produce the adjusted clock signals110B and110D. The phase adjustor104may adjust the phases of any number of clock signals108.

As seen inFIG.2, each of the switches202is connected to a capacitor to form an adjustor. Each switch202can open or close to disconnect or connect its corresponding capacitor to a resistor201A or201B, which adjusts an RC delay introduced into a corresponding clock signal108to produce an adjusted clock signal110. Additionally, each switch202is paired with another switch202that is connected to another capacitor and that can open or close to produce the other adjusted clock signal110. As seen inFIG.2, the switches202A,202C, and202E can open or close to disconnect or connect their corresponding capacitors to the resistor201A to adjust the RC delay introduced into the clock signal108B to produce the adjusted clock signal110B. The switches202B,202D, and202F can open or close to disconnect or connect their corresponding capacitors to the resistor201B to adjust the RC delay introduced into the clock signal108D to produce the adjusted clock signal110D. The switch202A is paired with the switch202B. The switch202C is paired with the switch202D. The switch202E is paired with the switch202F. The phase adjustor104may include any suitable number of switches202and capacitors.

Each pair of switches202is controlled by a control bit112. One switch202in the pair is connected with an inverter204to invert the control bit112. As a result, when one switch202in the pair is opened, the other switch202in the pair is closed. In the example ofFIG.2, the switches202A and202B are controlled by the control bit112A. An inverter204A inverts the control bit112A for the switch202A. The switches202C and202D are controlled by the control bit112B. An inverter204B inverts the control bit112B for the switch202C. The switches202E and202F are controlled by the control bit112C. An inverter204C inverts the control bit112C for the switch202E.

Each switch202is connected to a capacitor. When a switch202is closed, the switch202connects the capacitor to a resistor201A or201B to adjust the RC delay introduced to a clock signal108to produce the corresponding adjusted clock signal110. In the example ofFIG.2, the switch202A is connected to a capacitor C1P. The switch202B is connected with a capacitor C1N. The switch202C is connected with a capacitor C2P. The switch202D is connected with a capacitor C2N. The switch202E is connected with a capacitor CNP. The switch202F is connected with a capacitor CNN. The phase adjustor104may include any suitable number of switches202and capacitors. When the switch202is open, the switch202disconnects its corresponding capacitor from the corresponding resistor201A or201B and adjusted clock signal110. Each pair of switches202and their corresponding capacitors may be connected or disconnected from their corresponding resistors201A and201B and adjusted clock signals110to adjust the phases of the clock signals108by a step size. The step size may depend on the size of the capacitors.

Using the control bits112, a number of capacitors may be connected to or disconnected from the resistors201A and201B to adjust the phases of the clock signals108by a certain number of steps. For example, the controller106may analyze the adjusted clock signals110to determine a phase error for the adjusted clock signals110. The controller106may then determine an offset that should be used to adjust the phases of the adjusted clock signals110to correct the phase error. The controller106then sets the control bits112for the phase adjustor104so that a certain number of capacitors are connected to or disconnected from the resistors201A and201B. The phase adjustor104then connects or disconnects the capacitors from the resistors201A and201B based on the control bits112to adjust the RC delay introduced into the phases of the clock signals108. As discussed previously, because a pair of switches202and their corresponding capacitors are controlled to operate opposite each other, when a capacitor in a pair is connected to a resistor201A or201B, the other capacitor in the pair is disconnected from the resistor201B or201A. For example, as seen inFIG.2, when the switch202A is closed to connect the capacitor C1P to the resistor201A, the switch202B is opened to disconnect the capacitor C1N from the resistor201B. As a result, the phases of both clock signals108B and108D are adjusted by one step in opposite directions. In this manner, when a certain number of steps are added to the phase of the clock signal108B, the same number of steps are subtracted from the phase of the clock signal108D. As a result, the phase adjustor104increases the time delay of a clock signal108while decreasing the time delay of the other clock signal108by the same amount. Thus, the phases of the clock signals108are adjusted relative to each other, which may correct relative phase error for the clock signals108.

In particular embodiments, the controller106may determine the offset for the phase adjustor104iteratively. For example, the controller106may determine, based on the adjusted clock signals110, that there is a phase error for the clock signals108B and108D. In response, the controller106may set a control bit112A to adjust the phases of the clock signals108B and108D by one step. After adjusting the phases by one step, the controller106analyzes the adjusted clock signals110B and110D to determine whether there still is a phase error greater than the step size of the phase adjustor104. If there is still a phase error that exceeds the step size, the controller106sets the control bit112B to further adjust the phases by another step. This process continues until the phase error is reduced below the step size of the phase adjustor104. In this manner, the controller106and the phase adjustor104iteratively adjust the phases for the clock signals108to correct the phase error.

In some embodiments, the controller106determines the offset using a binary search process. For example, the controller106may analyze the adjusted clock signals110to determine that there is a phase error for the clock signals108B and108D. The controller106then sets a number of control bits112to add an offset to the phase of the clock signal108B and to subtract the offset from the phase of the clock signal108D. The controller106then analyzes the adjusted clock signals110B and110D to determine that there still is a phase error. The controller106then determines a second offset to be subtracted from the phase of the clock signal108B and to be added to the phase of the clock signal108D. The second offset may be smaller than the initial offset. The controller106then sets the control bits112to subtract the second offset from the phase of the clock signal108B and to add the second offset to the phase of the clock signal108D. The controller106and the phase adjustor104may continue this process of adjusting the phases of the clock signals108B and108D using smaller offsets until the phase error for the adjusted clock signals110B and110D is below a step size of the phase adjustor104. In this manner, the controller106and the phase adjustor104may correct the phase error more quickly than if the offset had been determined incrementally.

As discussed previously, the phase adjustor104may adjust the phases of any number of clock signals108. The phase adjustor may include a set of switches202and capacitors for any pair of clock signals110. Thus, the example shown inFIG.2represents only a portion of the switches202and capacitors in the phase adjustor104.

This disclosure contemplates the phase adjustor104adjusting the phase of clock signals using any suitable circuit or mechanism. In other words, the phase adjustor104is not limited to the resistors201, switches202, and capacitors as arranged in the example ofFIG.2to introduce RC delay into the clock signals. For example, the phase adjustor104may be implemented as an inverter-based programmable delay line or current-mode logic (CIVIL)-based delay structure. The phase adjustor104may include additional transistors and/or switches and a current source connected to the resistors that can further adjust the phase of the clock signals. By controlling the parameters of the transistors and/or switches, delay can be introduced into the clock signals.

FIGS.3A and3Billustrate an example phase adjustment using the system100ofFIG.1. As seen inFIG.3A, a data signal118is sampled according to the clock signals108A,108B,108C, and108D. As discussed previously, the data signal118may be sampled according to any number of clock signals108. The clock signal108B (90 degree phase) is 90 degrees out of phase with the clock signal108A (0 degree phase). The clock signal108C (180 degree phase) is 90 degrees out of phase with the clock signal108B. The clock signal108D (270 degree phase) is 90 degrees out of phase with the clock signal108C. The clock signal108A is 90 degrees out of phase with the clock signal108D. The data signal118is sampled on the rising edges of the clock signals108A,108B,108C, and108D, respectively.108A and108C are used to sample the edge of the data signal118, while108B and108D are used to sample the data content of the data signal118. Ideally, the data signal118should be sampled by108B and108D rising edges at the midpoint of a data block. As seen inFIG.3A, each data block has a width W, so the ideal sampling location is at a point W/2. It is intended that the rising edges of the clock signals108B and108D are positioned at the midpoint of a data block. However, because there is a phase error ϕEfor the clock signals108B and108D, the rising edges of the clock signals108B and108D are positioned off the midpoint of the data blocks by ϕE/2. T indicates the cycle time of clock108. If this phase error is not corrected, then the data signal118is sampled closer to the edges of the data block, which may reduce the signal quality or strength of the sampled data signal.

FIG.3Bshows the correction made by the phase adjustor104and the controller106. As seen inFIG.3B, an offset (e.g., ϕE/2) is added to the phase of the clock signal110B, and the same offset is subtracted from the phase of the clock signal110D. As a result, the rising edge of the clock signal110B is shifted later in time such that the rising edge falls on the midpoint of the data block. Additionally, the rising edge of the clock signal110D is shifted such that the rising edge of the clock signal110D is on the midpoint of a data block. By making these adjustments to the clock signals110B and110E, the data signal118may be sampled at the midpoints of the data blocks, which improves the signal strength and quality of the sampled data signal120.

The offset that is added to the phase of the clock signal110B and subtracted from the phase of the clock signal110D may be determined by the controller106. For example, the controller106may calculate a difference between the edge of a data block and the rising edge of a clock signal (e.g., the clock signal110B). The controller106then compares this difference with the width of the data block to determine the phase error. In the examples ofFIGS.3A and3B, the controller106may determine that the phase error is ϕE, and that the offset should be ϕE/2. The controller106may then set one or more control bits112to toggle a number of switches202to connect or disconnect a certain number of capacitors from the clock signals110B and110D. As a result, the phase adjustor104adds the offset to the phase of the clock signal110B and subtracts the offset from the phase of the clock signal110D.

In some embodiments, the controller106determines the offset incrementally. The controller106continues incrementing the phase of the clock signal110B and decrementing the phase of the clock signal110D by a step size of the phase adjustor104until the rising edges of the clock signals110B and110D are within a step size of the midpoint of a data block. In certain embodiments, the controller106adjusts the phases of the clock signals110B and110D using a binary search process to bring the rising edges of the clock signals110B and110D closer to the midpoint of the data blocks. The controller106may add and subtract decreasing offsets to the phases of the clock signals110B and110D until the rising edges are within a step size of the midpoint of the data block.

FIG.4is a flowchart of an example method400in the system100ofFIG.1. The controller106and/or the phase adjustor104may perform the method400. In particular embodiments, by performing the method400, the phase adjustor104adjusts the phases of two clock signals108relative to each other.

In block402, the controller106and/or the phase adjustor104determine a phase error for a first clock signal108and a second clock signal108. The controller106may determine the phase error by analyzing the adjusted clock signals110produced by the phase adjustor104based on these clock signals108. For example, the phase adjustor104and/or the controller106may determine that the first clock signal108and the second clock signal108should be 180 degrees out of phase with one another. However, the controller106may determine that the adjusted clock signals110produced by the phase adjustor104based on these clock signals108are not 180 degrees out of phase with one another. The controller106may then calculate the phase error based on how much the adjusted clock signals110are out of phase with one another.

In block404, the controller106determines an offset based on the phase error. For example, the controller106may determine that the offset is the phase error divided by two. In block406, the phase adjustor104and/or the controller106adds the offset to the first clock signal108. In some embodiments, the controller106sets one or more control bits112to toggle one or more switches202in the phase adjustor104to connect or disconnect certain capacitors from the first clock signal110. As a result of connecting and disconnecting these capacitors, the offset is added to the phase of the first clock signal108. In block408, the phase adjustor104and/or the controller106subtract the offset from the second clock signal108. For example, the controller106may set one or more control bits112to toggle one or more switches202in the phase adjustor104. These switches202may be paired with the switches that were toggled for the first clock signal108in block406. By toggling the switches, the phase adjustor104connects or disconnects certain capacitors from the second clock signal110, which results in the offset being subtracted from the phase of the second clock signal108. As a result, the phases of the first clock signal108and the second clock signal108are adjusted by the same offset but in different directions. In this manner, the phases of the first clock signal108and the second clock signal108are adjusted relative to each other.

FIG.5is a flowchart of an example method500in the system100ofFIG.1. The phase adjustor104and/or the controller106may perform the method500. In particular embodiments, by performing the method500, the phase of a clock signal108is incrementally adjusted. The method500may be performed after the method400.

In block502, the controller106determines whether the phase error for a first clock signal108and a second clock signal108exceeds a step size of the phase adjustor104. The step size may be based on the size of the capacitors within the phase adjustor104. If the phase error502for the clock signals108exceeds the step size, then the controller106and/or the phase adjustor104may determine an offset in block504. The offset may be the step size.

In block506, the phase adjustor104and/or the controller106add the offset to the first clock signal108. In block508, the phase adjustor104and/or the controller106subtract the offset from the second clock signal108. If the offset is a step size, then the controller106and/or the phase adjustor104incremented the phase of the first clock signal108by the step size and decremented the phase of the second clock signal108by the step size. The controller106and/or the phase adjustor104may increment or decrement the phase by setting a control bit112to toggle a pair of switches202in the phase adjustor104.

The phase adjustor104and/or the controller106then return to block502to determine if the phase error for the clock signals108still exceeds the step size. If the phase error still exceeds the step size, then the phase adjustor104and/or the controller106may perform blocks504,506and508again. If the phase error no longer exceeds the step size, then the phase adjustor104and/or the controller106may end the method500.

FIG.6is a flowchart of an example method600in the system100ofFIG.1. The phase adjustor104and/or the controller106may perform the method600. In particular embodiments, by performing the method600, the phase adjustor104and/or the controller106determine an offset using a binary search process. The method600may be performed after the method400.

In block602, the phase adjustor104and/or the controller106determine whether a phase error for clock signals108exceeds a step size of the phase adjustor104. If the phase error exceeds the step size, then the phase adjustor104and/or the controller106determine an offset in block604. The offset determined in block604may be smaller than the offset determined in block404. In block606, the phase adjustor104and/or the controller106subtract the offset from the phase of a first clock signal108. In block608, the phase adjustor104and/or the controller106add the offset to the phase of a second clock signal108. In this manner, the phase adjustor104and/or the controller106shift the phases of the first and second clock signals108in a direction opposite to the direction the phases were shifted in the method400. However, because the offset determined in block604is smaller than the offset determined in the method400, the phases of the first and second clock signals108are adjusted less than they were adjusted in the method400.

The phase adjustor104and the controller106may then move back to block602to determine if the phase error for the clock signals108still exceeds the step size. If the phase error still exceeds the step size, the phase adjustor104and the controller106perform block604,606and608again. If the phase error does not exceed the step size, then the phase adjustor104and/or the controller106end the method600.