Serial self-adaptable transmission line

A self-adaptable transmission line (SATL) according to the present invention is implemented as a single signal path coupled between an SATL transmitter and an SATL receiver. The SATL transmitter controls the process of transmission in an SATL architecture. Data to be sent by the SATL transmitter are first encoded to the appropriate symbol before being serialized and transmitted on the SATL. A symbol transfer starts with an event known as a start-of-symbol (SOS) event, which can be, for example, a low-to-high transition. The SATL receiver samples and deserializes the incoming bitstream, and then decodes the symbol thus received. Upon detection of an SOS by the SATL receiver, the SATL receiver's logic is reset to its initial state, ready to receive the next symbol.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the field of data communications, and more particularly to a method and system for operating a serial self-adaptable transmission line that provides communications between devices.

2. Description of the Related Art

Today's integrated circuits (ICs) are typically implemented using hundreds of input, output, input/output (I/O), power and ground pins, generically referred to as simply “pins”. As will be appreciated, the larger number of pins, the greater complexity in the design, manufacture and use of such ICs. IC designers therefore often go to great lengths to minimize the number of pins required by the various modules of a given design, in order to reduce the overall number of pins required to implement the given IC.

Moreover, ICs sometimes required alternate paths of communication that can be called into service in the event of a failure or other situation. For example, the internal states of today's ICs are typically programmed using a processor interface. Such a processor interface can include, for example, a 32-bit data bus, a 16-bit address bus and various control signals. However, it is often desirable to program certain internal registers prior to an IC's processor interface becoming operational. For example, a PLL generating the IC's core clock may be programmed in different ways (changing bias values, frequency ratios and so on). However, that same clock may be used to operate the processor interface. Thus, the processor interface cannot be used to program the PLL, because the processor interface cannot be used until the PLL is programmed. Instead, the PLL needs to be programmed via another interface. This alternate interface should be independent from the PLL itself, and should, as noted, employ a low pin-count technique.

Another application of such a low-pin-count interface is as an output to drive a set of 16-bit LEDs. As will be appreciated, it is desirable to employ an interface can drive such LEDs without the IC being required to generate and output 16 different signals, due to the number of pins that would be required by such an approach. As will be appreciated, then, the need for low-pin count interfaces appears in many situations in today's devices. This need has led to the development of a variety of interface standards, such as asynchronous serial communications (e.g., RS-232) and other such approaches (e.g., the inter-IC (I2C) bus).

Unfortunately, such interfaces are not without their infirmities. Such interfaces may require a certain frequency relationship between the receiver and the transmitter for proper operation, potentially limiting the devices that are able to communicate with one another. Moreover, such interfaces are sometimes proprietary in nature. Often, such interfaces require more than one input or output pin on an IC implementing the given technique. More specifically, a communications link between ICs typically requires a minimum of two signal lines, one signal line for the clock signal, and one signal line for the serialized datastream, although other solutions require many more signal lines (e.g., RS-232). The I2C-bus is an example of a serial protocol that employs two wires. Such techniques provide a relatively low-pin count solution, and so are very attractive in pin-limited designs. However, it is desirable to allow flexibility in clocking relationships, as well as to further reduce the pin-count required and to avoid proprietary technology.

What is desired, then, is to reduce the number of communication lines to a single communications line, in order to further reduce the pin count of ICs employing such a technique, as well as the area consumed by printed circuit board layouts in such designs. It is also desirable to keep the logic used to implement such a communications protocol simple, in order to minimize the area required on the integrated circuit. Moreover, as noted, such a technique should allow flexibility in the relationship between the transmitter and receiver clocks.

SUMMARY OF THE INVENTION

In one embodiment, a receiver is disclosed. This receiver includes a symbol decoder and a start-of-symbol detector. The start-of-symbol detector is coupled to receive a start-of-symbol signal from the symbol decoder

In another embodiment, a transmitter is disclosed. This transmitter includes an encoder. The encoder is configured to generate a symbol based on a value of information received by the encoder. The symbol comprises a plurality of symbol elements. The encoder is further configured to set each of a first number of the symbol elements to a first logical value, if the value is equal to a first value. The encoder is further configured to set each of a second number of the symbol elements to the first logical value, if the value is equal to a second value. The encoder is further configured to set each of a third number of the symbol elements to the first logical value, if the encoder is to generate a synchronization symbol. The first number is greater than the second number, the third number is not equal to the first number, and the third number is not equal to the second number.

In yet another embodiment, a method is disclosed. This method includes receiving a symbol, incrementing a count in response to the symbol, decrementing the count in response to the symbol, comparing the count to a first limit, and generating a data value. The generating thus performed is based on comparing the count to the first limit.

In still another embodiment, a method is disclosed. This method includes generating a first number of a first number of symbol elements of a first symbol and generating a second number of a second number of symbol elements of a second symbol. The first symbol is a synchronization symbol, and each of the first number of the first number of symbol elements have a first logical value. The second symbol represents a data value of data encoded in the second symbol. Each of the second number of the second number of symbol elements have the first logical value, and the first number is not equal to the second number. The second number is equal to a third number, if the data value is equal to a first value, and the second number is equal to a fourth number, if the data value is equal to a second value. The third number is greater than the fourth number.

DETAILED DESCRIPTION

Introduction

A self-adaptable transmission line (SATL) according to the present invention is implemented as a single signal path (e.g., wire) coupled between an SATL transmitter and an SATL receiver. The SATL transmitter controls the process of transmission in an SATL architecture. Data to be sent by the SATL transmitter are first encoded to the appropriate symbol before being serialized and transmitted on the SATL. A symbol transfer starts with an event known as a start-of-symbol (SOS) event, which can be, for example, a low-to-high transition. The SATL receiver samples and deserializes the incoming bitstream, and then decodes the symbol thus received. Upon detection of an SOS by the SATL receiver, the SATL receiver's logic is reset to its initial state, ready to receive the next symbol.

An Example Architecture Employing a Self-Adaptable Transmission Line

FIG. 1is a block diagram illustrating the use of a self-adaptable transmission line (SATL) according to the present invention. Shown inFIG. 1is an SATL signal100coupling a transmitting device110and a receiving device120. Transmitting device110receives a transmit clock (TCLK)130, which is used to time the data transmitted by transmitting device110as SATL signal100. In a similar fashion, receiving device120receives a receive clock (RCLK)140, which is used to time the receipt of the signal carried by SATL signal100. Also shown are the power (VCC) and ground connections for transmitting device110and receiving device120. It will be appreciated that, while multiple SATL lines can be used in conjunction with one another, a primary advantages are the reduction in pin count and circuit complexity.

FIG. 2is a block diagram showing an example of the components within transmitting device110and receiving device120in one embodiment of the present invention. In this embodiment, transmitting device110receives outgoing data200. Outgoing data200is typically presented to transmitting device110as a bus (i.e., a word of parallel bits of some appropriate width). Because SATL signal100is typically a single serial channel, a word width of some number of bits requires that a parallel-to-serial conversion be performed. Thus, transmitting device110includes, in the embodiment depicted inFIG. 2, a shift register210that receives and stores the outgoing data word received as outgoing data200. Shift register210which receives and stores the outgoing data word (received as outgoing data200). Shift register210provides this outgoing data word to an encoder220by shifting out the bits of the outgoing data word, in a serial fashion. Encoder220encodes the outgoing data word as per the protocol described subsequently in connection withFIGS. 11,12, and13.

Encoder220thus creates a symbol for each bit of outgoing data200, and presents the symbols thus created to a serializer230, which takes in each symbol and outputs the symbol elements of each symbol (typically, the bits of each symbol) in a serial fashion. Thus, as will be appreciated, two parallel-to-serial conversions are performed by the elements of transmitting device110, the first being within shift register210and the second being within serializer230. In the former case, serializer230serializes the parallel bits of each symbol generated by encoder220into a bitstream for transmission as SATL signal100.

In corresponding fashion, receiving device120receives SATL signal100at a deserializer240, which performs a serial-to-parallel conversion on the bits of SATL signal100. Deserializer240provides the symbols thus generated to a decoder250. Decoder250generates an incoming data stream260by decoding the symbols received from deserializer240from symbols into the actual data bits those symbols represent. As will be appreciated, incoming data stream260is a bitstream, and so corresponds to the output of shift register210. In the typical case, outgoing data200has a word width of some number of bits, and so incoming data stream260is deserialized to reconstruct the counterpart of outgoing data200. This serial-to-parallel conversion is performed by a shift register270, which generates incoming data280. Thus, in the manner of transmitting device110, receiving device120performs two serial-to-parallel conversions (corresponding to the two parallel-to-serial conversions performed by the elements of transmitting device110). As a result, incoming data280has a word width of some number of bits, and typically, the same number of bits as outgoing data200. As will be appreciated, this need not be the case, and a different number of bits can therefore be used for incoming data280, if such is desirable.

A protocol compatible with the present invention sets the default parameters:1) Number of symbols;2) Maximum clock ratio between the transmitter and the receiver(1≦RCLK/TCLK≦X); and3) Serial bit margin (serialBitMargin) between symbols.

In an embodiment of the present invention, each symbol has a value indicating how long the SATL signal is set to a logic “1” after an SOS, using the following notation:

where A indicates the length of SATL=1 for that symbol, and±1represents the asynchronous interface between the transmitter and receiver clocks (one SATL=1 or SATL=0 may not be latched properly by the receiver). The lowest symbol starts at 2±1instead of 1±1, because the receiver needs to detect a low-to-high transition (signifying an SOS event).

As will be appreciated, keeping both serialBitMargin and the serial-bit length (serialBitLength) to power-of-two values simplifies implementation of this embodiment in hardware by allowing the use of shift registers, rather than multipliers and dividers.

One embodiment of the present invention employs three symbols with a serialBitMargin of 2. The transmitter-to-receiver clock ratio ranges from 1 to 20. Each symbol is 16 bits long, and is represented as shown in Table 1 below.

FIG. 3is a graph depicting a waveform representation of the above scheme is employed. As can be seen, each symbol (here, the symbols being “0”, “SYNC”, and “1”, as in Table 1) consumes 16 bit times. As can also be seen, the symbol “0” includes four bit times (the first four) of logic ones (in contrast to the “1” symbol), followed by 12 bit times of logic zeroes (in contrast to the “0” symbol). Similarly, the synchronization (“SYNC”) symbol includes eight bit times of logic ones, followed by eight bit times of logic zeroes. Finally the symbol “1” includes 12 bit times of logic ones and four bit times of logic zeroes.

As will be appreciated, the encoding scheme presented in connection withFIG. 3, and elsewhere herein, is but one example of an encoding scheme according to the present invention. The data values represented by each symbol need not be encoded as noted herein, but can be encoded using other representations. For example, the graph ofFIG. 3might be interpreted as representing another sequence of symbols, such as “0”-“1”-“SYNC”, “SYNC”-“0”-“1”, or some other sequence. Moreover, the sequences of bits representing each symbol need not be evenly distributed. For example, a bit pattern of 11111111—11111100 could be used for a “1” symbol, once again a bit pattern of 11111111—00000000 could be used for a “SYNC” symbol, and a bit pattern of 11000000—00000000 could be used for a “0” symbol.

In fact, as will be appreciated, any number of variants of the basic concepts presented herein can be implemented according to the present invention. For example, the sequences of bits representing each symbol need not be contiguous. Because the main goals are to use a certain overall count (within certain bounds, at least) to represent a given symbol and to examine/reset that count at a certain point in time (e.g., at SOS) in order to determine the current symbol and prepare for the next symbol, any approach that employs bit patterns that provide such information are acceptable. For example, a bit pattern of 11111100—11111100 could be used for a “1” symbol, once again a bit pattern of 11110000—11110000 could be used for a “SYNC” symbol, and a bit pattern of 11000000—11000000 could be used for a “0” symbol. In such an implementation, a mechanism is provided to distinguish an SOS from a similar transition that occurs within a symbol (e.g., using a predefined sequence of symbols at the start of a transmission, comparing the first and second halves of the current symbol or the like), although the counting would still be performed as described elsewhere herein (e.g., a sample of logic “1” would cause the count to increase, and a sample of logic “0” would cause the count to decrease).

It will be appreciated that the minimum clock ratio may affect the bit patterns that can be successfully employed. For example, the fewer samples/bit time that are taken by the receiver, the longer the string of logic “1'”s (or logic “0'”s) needs to be, in order for the symbol to be correctly identified by the receiver. It will be further appreciated that these and other variations will be apparent to one of skill in the art, in light of the present description, and so are considered to be within the scope of the present invention.

The serialBitLength is determined for this example based on the following default parameters, in the manner described previously:1) Number of symbols=32) Minimum clock ratio=13) SerialBitMargin=2

The minimum encoding scheme is determined by the following calculations:symbol[0]=2±1symbol[1]min=symbol[0]max+serialBitMargin=3+2=5symbol[1]=6±1symbol[2]min=symbol[1]max+serialBitMargin=7+2=9symbol[2]=10±1

Thus, the minimum serialBitLength is equal to 11 plus the serialBitMargin. As will be appreciated, using a serialBitLength of 16 bits in this case meets these requirements, while simplifying the design and implementation of the hardware employed in realizing a system according to the present invention. It will also be appreciated that, for a given serialBitLength (e.g., 16 bits), several different numbers of symbols may be able to be implemented (e.g., for a serialBitLength of 16 bits, the number of symbols can be 3, 5 or 7, for example). Again, if a non-contiguous bit pattern is used, some mechanism for distinguishing between an SOS and a similar transition within a symbol is mandated.

FIG. 4is an illustration of a bitstream that reflects symbols encoded according to the present invention. As can be seen, interspersed among the symbols representing the data are periodic “SYNC” symbols, which are sent regularly, to ensure synchronization of the receiver. Thus, in the example depicted inFIG. 4, a “SYNC” symbol is sent followed by the symbols for “0110” (depicted inFIG. 4as “0”, “1”, “1”, and “0”). After the four symbols are sent, another “SYNC” symbol is sent and the process repeats with the symbols for the next four data bits (the first two of which are shown inFIG. 4; “1” and “0”). As will be appreciated, a “SYNC” symbol allows an SATL receiver to synchronize itself with the incoming bitstream by providing a symbol that, nominally, will result in the same number of logic ones and logic zeroes being sampled from the incoming symbol's bitstream (although, given the potential for sampling noise, some sort of noise margin is typically employed that allows some acceptable deviation from this ideal, while still identifying the symbol as a “SYNC” symbol). Thus, the logic-one-to-logic-zero transition (in contrast to an SOS, which is just the opposite (a logic-zero-to-logic-one transition), in the embodiment discussed here) is centered between SOS events. This basically provides a 50% duty cycle signal at the transmit clock's frequency divided by the serialBitLength (here, 16 bits), providing the maximum distance between the logic-one-to-logic-zero transition, and the preceding/following SOSs (logic-zero-to-logic-one transitions).

Logic designed to implement the present invention requires a few parameters, counters and variables to deserialize and decode the data stream. Parameters are typically a hard-coded value, which determine the working range of the transmitter-receiver pair. As will be appreciated (and as described subsequently), such information can also be programmed into registers, allowing a transmitter-receiver pair according to the present invention to be reconfigured, as desired. These parameters, counters and variables, as well as their meaning and their values, are given in Table 2.

A protocol according to the present invention is scalable in a number of ways, including changes to:1) Number of symbols (by increasing the serial-bit length: bitPerSymbol),2) Maximum clock ratio (by increasing sample counter size: sampleSetCnt), and3) Minimum clock ratio (by increasing both the serial-bit length and the sample counter size: bitPerSymbol and sampleSetCnt).

All three of these variables (clockRatio, lowWaterMark and highWaterMark) allow the receiver to self-adjust to the incoming data stream, and in fact, allow such adjustment to occur on every SOS event. The watermarks for the current symbol can actually be based on the result of the previous symbol and SOS.

The present invention's self-adaptability is advantageous in several respects. As will be appreciated, the present invention largely decouples the receive clock (RCLK) from the transmit clock (TCLK) by employing a sampling technique that requires only the identification of certain points in the incoming SATL signal. In fact, in certain embodiments, only one point need be identified: the SOS, which is used both to identify the point at which the count is to be evaluated and to reset the count in preparation for decoding the next symbol. The only information regarding the relationship between TCLKand RCLKthat is needed is the maximum ratio of TCLKto RCLK(i.e., maxClockRatio, from Table 2).

As will be appreciated, the theoretical lower limit of the range of ratios of TCLKto RCLKis 1:1, which is the minimum needed to ensure that the SATL receiver generates a bit for each bit transmitted by the SATL transmitter. However, this assumes that the SATL signal generated using TCLK, is sampled at a point at which aliasing is not an issue. To ensure this is the case, one would have to employ some mechanism that would allow the SATL receiver to know when to sample (i.e., some mechanism that defines the phase relationship between TCLKand RCLK(as the frequency relationship would already be known, that being 1:1)).

Thus, in implementing a communications system according to the present invention, it is desirable to employ a minimum ratio of TCLKto RCLKof more than 1:1 (i.e., RCLK>TCLK). In so doing, the SATL signal is effectively over-sampled, thus allowing such a system to tolerate an erroneous sample. By selecting a minimum ratio of more than 1:1, the SATL receiver is thus able to generate the correct symbol. The parameter serialBitMargin, noted above, is related to this concept, in that serialBitMargin defines the system's tolerance for “sampling noise”. This sampling noise is the number of samples that such a system can count in the case of a synchronization symbol, above or below the middlePoint, and still decode the symbol being sampled as a synchronization symbol (“Sync” symbol). Thus, the watermarks are set using the serialBitMargin, and allow such a system to tolerate a given amount of noise.

This is also advantageous because no synchronization circuitry is required. By avoiding the need for phase-locked loops (PLLs) and the like, implementation of a SATL transmitter and receiver is simplified. Moreover, the resulting receiver design is smaller, thus consuming less IC area and reducing IC cost. The area requirements of such a design are also minimized by limiting the size of the counter used in the SATL receiver (for setSampleCount) to S bits, where:
2(S−1)>middlePoint
middlePoint>maxSampleSetCnt+(serialBitMargin*maxClockRatio)

The above calculation can be taken to imply that S is an integer, such that the size of the setSampleCnt counter is sized to some power of 2. As will also be appreciated from the above calculation, S is therefore proportionally related to the maxClockRatio. Once the maxClockRatio is selected, the size of the setSampleCnt counter can then be set. This allows the IC designer to use their judgment as to the tradeoff between the IC area consumed by the design, and the clock ratios to be supported. In a converse sense, RCLKand/or TCLK(and so maxClockRatio) can be set to avoid sampling the SATL signal at a rate that could overflow the SATL receiver's setSampleCnt counter. This allows a circuit designer to choose appropriate values for RCLKand/or TCLKin light of the architectural choices made by the IC designer. Thus, TCLKcan be, and typically is, completely independent of RCLK, and vice versa. It will

This ability to tolerate variations in the frequency and phase relationship between TCLKand RCLKis also advantageous because their relationship can vary dynamically. Once a range of clock ratios is determined, a system according to the present invention can be programmed to use any clock ratio within that range, by properly selecting serialBitLength, maxClockRatio and serialBitMargin. This information can be changed dynamically, at each data word, or even at each symbol, in order to account for changes in clock frequencies, environmental effects (e.g., altering the maximum transmission frequency) and other such conditions.

FIG. 5is a graph illustrating the value of sampleSetCnt as an SATL data stream is received and converted. As can be seen inFIG. 5, sampleSetCnt begins at a middlePoint and is incremented as logical 1's are detected by the SATL receiver. This continues until logical 0's are detected, at which point sampleSetCnt is decremented for each 0 received by the SATL receiver. This continues until a start-of-symbol (SOS) is detected, that being a logical 0 to logical 1 transition, in the implementation described herein. Upon the detection of an SOS, the SATL receiver determines the value of the sampleSetCnt, and how it compares with the HighWaterMark (HWM) and LowWaterMark (LWM). If the sampleSetCnt is greater than the HighWaterMark, a symbol “1” has been detected; if the sampleSetCnt is below the LowWaterMark, a “0” symbol has been detected; and if the sampleSetCnt is between the LowWaterMark and the HighWaterMark, a “SYNC” symbol has been detected. Thus, the example depicted inFIG. 5, the first starter symbol results in the detection of a “SYNC” symbol, the second starter symbol results in the detection of a “0” symbol, and the detection of the third starter symbol results in the detection of a “1” symbol.

The variables, counters and parameters discussed above are best illustrated by an example. Table 3 provides a configuration example for the receiver for TCLK=20 MHz and RCLK=200 MHz.

It is to be understood that the serialBitMargin is 2, in this example, as a result of MIN(symbol[1]=6±1)−MAX(symbol[0]=2±1)=5−3=2.

FIG. 6is a block diagram of an SATL transmitter600according to the present invention. As before (inFIG. 1), the SATL transmitter (SATL transmitter600) receives a transmit clock (TCLK)610. SATL transmitter600also receives data620, which corresponds to outgoing data200ofFIG. 2. In order to put SATL transmitter600into a known state, SATL transmitter600also receives a reset signal630. In turn, SATL transmitter600generates and transmits an SATL signal640that corresponds to SATL signal100ofFIG. 1.

FIG. 7is a block diagram illustrating SATL transmitter600in greater detail. As before, SATL transmitter600receives transmit clock610, data620, and reset signal630, and generates SATL signals640. As depicted inFIG. 7, SATL transmitter600includes a transmit controller700, which is configured to control the various elements of SATL transmitter600and in so doing, effect the protocol according to the present invention. Transmit controller700receives reset signal630, and in turn, resets the elements of SATL transmitter600. Transmit controller700also distributes clocking signals to the various elements of SATL transmitter600, having received transmit clock610.

Data620is received by a register710, which stores the value of the data value (e.g., a data word of one or more data bits) presented as data620. Register710then presents this data to a multiplexer720. Multiplexer720, under the control of transmit controller700selects bits from the data held in register710for presentation to an encoder730. As part of implementing a protocol according to the present invention, transmit controller700generates a sendSync signal740. Transmit controller700provides sendSync signal740to encoder730in order to indicate to encoder730that encoder730should not encode a data bit during the current symbol time, but should instead encode the symbol for a “SYNC” symbol. Thus, transmit controller700controls the stream of symbols generated by encoder730. Encoder730provides these symbols to a shift register750, which serializes the bits of the given symbol, under the control of transmit controller700and in a manner synchronous with transmit clock610. In so doing, shift register750creates the bitstream that is presented as SATL signal640.

FIG. 8is a block diagram illustrating an SATL receiver800according to the prevent invention. SATL receiver800receives an SATL signal810, which corresponds to the SATL signal generated by an SATL transmitter such as SATL transmitter600(e.g., SATL signal640). SATL receiver800also receives a receive clock (RCLK)820, which is used to clock the elements of SATL receiver800and to sample SATL signal810at the appropriate times. By sampling SATL signal810at the appropriate times and processing the information thus received, SATL receiver800is able to recover the data thus transmitted, which appears at an output of SATL receiver800as data830. SATL receiver800also receives a reset signal840, which allows SATL receiver800to be initialized.

FIG. 9is a block diagram illustrating the elements of SATL receiver800in greater detail. As before, SATL receiver800receives SATL signal810, and detects and decodes the data in SATL signal810by sampling SATL signal810using receive clock820, thus generating data830. In a manner similar to that transmitter600, SATL receiver800includes a receive controller900, which controls various aspects of the operation of the SATL receiver800. Under the control of receive controller900, a dual-rank synchronizer910receives SATL signal810and synchronizes SATL signal810to be sampled using receive clock820. Dual-rank synchronizer910provides this synchronized signal to both a start-of-symbol (SOS) detector920and a symbol decoder930. As its name implies, SOS detector920detects the start of a given symbol. For example, SOS detector920can be configured to detect a low-to-high transition in the synchronized signal generated by dual-rank synchronizer910. SOS detector920provides this indication to symbol decoder930, in order to allow symbol decoder930to recognize the point at which the current symbol begins.

Symbol decoder930then consumes an appropriate number of bits (i.e., the number of bits used to represent a symbol), and generates an output bit corresponding to the data bit represented by the symbol received. This decoded symbol (i.e., data bit) is presented as BitLine signal940. BitLine signal940is received by a parallel unit950, which converts the data bits received via bit line signal940into a data word, which can then be output as data830. It will be understood that, in fact, parallel unit950need not perform parallel-to-serial conversion, so long as the data input to the corresponding SATL transmitter is also a serial bitstream.

As will be appreciated, one approach to implementing parallel unit950is through the use of a shift register. Symbol decoder930, in order to synchronize its operations with those of parallel unit950, also provides other signals than enable parallel unit950to discern when its operations should be performed. Symbol decoder930thus generates a DataValid960in order to indicate to parallel unit950that the data bit presented as BitLine signal940is valid, and can be shifted into parallel unit950. Symbol decoder930also provides a SyncDetect signal970to parallel unit950, to indicate the boundary between data words. Thus, at the point at which symbol decoder930decodes a “SYNC” symbol, symbol decoder930generates SyncDetect signal970to re-initialize parallel unit950. This also indicates to parallel unit950that the bit available on BitLine signal940is complete and can be shifted into parallel unit950. Once a sufficient number of bits is shifted into parallel unit950, the resulting data word is output as data830, and parallel unit950shifts in the bits of the next data word.

FIG. 10is a block diagram illustrating symbol encoder930in greater detail. As before, symbol decoder930provides a data value (e.g., one or more data bits) at BitLine signal940, and provides DataValid signal960and SyncDetect signal970to parallel unit950in order to allow parallel unit950to determine the various extents of the data received by parallel unit950. Symbol decoder930is controlled by a symbol decoder controller1000, which provides control and clocking signals to various elements of symbol decoder930. Symbol decoder controller1000, among other tasks, is responsible for setting various parameters within symbol decoder930, to allow for the proper operation of symbol decoder930, and thus provide for the proper decoding of the symbols received thereby. In configuring symbol decoder930, symbol decoder controller1000receives control signals (control signals1005) that determine the manner in which symbol decoder controller1000programs symbol decoder930for operation.

Thus, under the control of control signals1005, symbol decoder controller1000stores a LowWaterMark value in a LowWaterMark register1010and a HighWaterMark value in a HighWaterMark register1015. As will be appreciated, LowWaterMark register1010and HighWaterMark register1015can, in fact, be implemented using any suitable type of storage unit. Symbol decoder controller1000receives control signals1005from receive controller900(as shown inFIG. 9). Symbol decoder controller1000also receives an SOS signal1020from the SOS detector of SATL receiver800(depicted as SOS detector920inFIG. 9). As noted, SOS signal1020indicates to symbol decoder930(and, more particularly, symbol decoder controller1000) that a start-of-symbol has been received. In certain embodiments of the present invention, this function is performed by detecting a low-to-high transition in SATL signal810. This event has a number of effects.

Upon receipt of an SOS, symbol decoder controller1000resets a sample set counter1030to an initial value (e.g., middlePoint). Sample set counter1030maintains a count of the values of samples of the signal received by symbol decoder930(depicted inFIG. 10as a synchronized SATL signal1040). Upon the receipt of an SOS indication via SOS signal1020, symbol decoder controller1000also causes a HighWaterMark (HWM) comparator1050to compare the value (or count) held in sample set counter1030with the HighWaterMark value held in HWM register1015. More specifically, HWM comparator1050determines if the count (in fact, setSampleCnt) is greater than the HWM held in HWM comparator1050. Similarly, symbol decoder controller1000, upon the receipt of an SOS indication, causes an LWM comparator1060to compare the value (count) held in sample set counter1030with the LWM held in LWM register1010. More specifically, LWM comparator1060determines if the count (setSampleCnt) is greater than the LWM. As will be appreciated, the actual value of the HWM and/or the actual value of the LWM can be included or excluded from the range of values that generate a logic “1” or logic “0” on BitLine signal940, as well as those that assert SyncDetect signal970, by choosing an appropriate comparison to make (e.g., selecting a relationship such as greater than, greater than or equal to, less than, less than or equal to, or the like).

The results of the foregoing comparisons are then provided to signal logic1070, which in turn generates BitLine signal940and SyncDetect signal970. Signal logic1070includes an inverter1072, an AND gate1074and an AND gate1076. Inverter1072and AND gate1074combine the outputs from HWM comparator1050and LWM comparator1060in order to generate SyncDetect signal970. SyncDetect signal970indicates to parallel unit950that a “SYNC” symbol was received, and that the data word being shifted into parallel unit950is now complete and can be presented as data830. SyncDetect signal970can also be used to re-align (i.e., synchronize) parallel unit950, in the case where SATL receiver800has lost synchronization with SATL signal810.

In a similar fashion, AND gate1076performs a logical AND between the output of HWM comparator1050and LWM comparator1060in order to generate BitLine signal940. BitLine signal940provides the value of the current data bit for shifting into parallel unit950. Symbol decoder controller1000also generates a DataValid signal960, which indicates a point in time at which BitLine signal940presents a valid data bit. It will be appreciated that if DataValid signal960is not asserted, BitLine signal940is ignored. This can also be characterized in terms of BitLine signal940being ignored if SyncDetect signal970is asserted.

The foregoing signals and their values, in terms of the earlier example, are given in Table 4, which reflects the states of SATL receiver800during normal operation, in which SATL receiver800synchronized with SATL signal810.

FIG. 11is a flow diagram illustrating a process of transmitting a data word according to the present invention. The process begins with an SATL transmitter such as SATL transmitter600receiving a data word (step1100). The SATL transmitter then serializes the data word (as is performed inFIG. 7by register710and multiplexer720) (step1110). Next, a “SYNC” symbol is generated by the SATL transmitter's transmit controller sending a SendSync signal to the SATL transmitter's encoder (step1120). The encoder inserts the “SYNC” symbol in the datastream, as the bits that represent the “SYNC” symbol are generated (step1130). The SATL transmitter sends the “SYNC” symbol by transmitting those bits (depicted inFIG. 7via a shift register (shift register750) being loaded with, and then shifting out, the requisite bits) (step1140).

The process of transmitting the data word received by the SATL transmitter is then begun. This portion of the process begins with the encoding of a bit of the data word into a symbol representing the bit's value (step1150). Next, the symbol for that bit is inserted into the datastream (step1160). The bits that make up the symbol for the bit of the data word are transmitted serially (step1170). A determination is then made as to whether bits of the data word remain to be encoded and transmitted in the manner just described (step1180). If further bits of the data word remain, those bits are encoded (step1150), the bits of the symbol representing the bit of the data word are then inserted into the datastream (step1160) and those bits transmitted (step1170). If the current data word's bits have been encoded and transmitted, the SATL transmitter is then ready to accept the next data word (step1100).

As will be appreciated, the process of encoding and transmitting the bits of the current data word can be repeated any number of times, although it may be desirable to send a “SYNC” symbol with greater frequency than one “SYNC” symbol per data word, if the length of the data word becomes relatively large (e.g., in the case where the period between “SYNC” symbols becomes so great as to make the probability of losing synchronization unacceptably high). Moreover, it will be appreciated that the operations of encoding and transmitting a data word can be overlapped with the receipt (and, optionally, storage) of another data word, as is possible with others of the operations described herein.

FIG. 12is a flow diagram of a process reflecting one example of the operations performed by a symbol decoder, such as symbol decoder930of SATL receiver800inFIG. 9, according the present invention. As noted, symbol decoder930is shown in greater detail inFIG. 10, and the operations now discussed are best understood with reference to the elements ofFIG. 10. The process begins with the detection of a start-of-symbol (step1200). So long as a start-of-symbol (SOS) is not detected, the process loops, awaiting an SOS. Once an SOS is detected, the sample set counter (e.g., sample set counter1030) is loaded with a value equal to the middlepoint value (step1210). This prepares the sample set counter to count the samples of the zeroes and ones that make up the symbols received by the SATL receiver.

Next, the incoming signal is sampled (step1220). A determination is then made as to the sample's value (step1230). If the sample indicates that the value of the incoming signal is a logic “1,” the sample set counter (represented by the variable sampleSetCnt) is incremented (step1240). Alternatively, if the logical value of the incoming signal is “0” at the sampling point, the sample set counter is decremented (step1250). A determination is then made as to whether another SOS has been detected (step1260). If an SOS has not been detected, indicating that the current symbol is not yet complete, the process loops to again sample the incoming symbol (step1220), and determine whether the sample set counter should be incremented or decremented (steps1230,1240, and1250). If an SOS is detected, the received symbol's value is then determined (step1270), and the process of receiving the next symbol begins (step1210). The process of determining the value of the received symbol (step1270) is discussed in greater detail in connection withFIG. 13, below.

As will be appreciated, in one embodiment, sampleSetCnt first undergoes a number of increment operations, followed by number of decrement operations (as demonstrated in the example previously discussed). Thus, the branch in the flow diagram containing step1240is taken some number of times, followed by the branch in the flow diagram containing step1250being taken some number of times. The number of times each is taken reflects the symbol received.

As will also be appreciated, in another embodiment, such a process is implemented by starting with the detection of an SOS (which can be equated with the first sampling of a logic 1). Next, the value of sampleSetCnt is incremented on each clock cycle of RCLK, until a logic 0 is detected (ideally, this is co-incident with the high-to-low transition in the SATL signal, but more likely, is simply the first sample that indicates a logic 0). The value of sampleSetCnt is then decremented on each clock cycle of RCLK, until the next SOS. Sampling in this case is only used to determine when the sampled value changes. This could also be implemented using two counters, one configured to count only when the sample value indicates a logic 1 and the other configured to count only when the sample value indicates a logic 0, although greater resources might be consumed by such an implementation.

FIG. 13is a flow diagram illustrating a process for decoding a symbol according to the present invention. As will be appreciated, the process depicted inFIG. 13is an example of a process according to the present invention that can be carried out by the symbol decoder ofFIG. 10(symbol decoder930). The process begins with a comparison of setSampleCnt with the HWM (step1300). A similar comparison is made between setSampleCnt and the LWM value held in LWM register1010by LWM comparator1060. As will be appreciated, if setSampleCnt is greater than HWM, setSampleCnt will also be greater than LWM. Thus, if setSampleCnt is greater than HWM, the symbol received is taken to be a “1” (step1310). This indicates that the number by which setSampleCnt is incremented from the middlePoint, less the number by which setSampleCnt is decremented, is above the middlePoint by at least the serialBitMargin.

Otherwise, the value of setSampleCnt is compared to the LWM (step1320) in a manner similar to the previous comparison. If setSampleCnt is greater than the LWM, setSampleCnt is between the LWM and the HWM (step1320). If such is the case, the symbol decoded is a “SYNC” symbol (step1330). Otherwise, if setSampleCnt is less than the LWM (it being axiomatic that if setSampleCnt is less than the LWM, setSampleCnt will be less than the HWM), the symbol is a “0” (step1340).

As will be appreciated, the process ofFIG. 13can also be discussed in terms of the symbol decoder ofFIG. 10(symbol decoder930). The comparison of the value held in sample set counter1030(setSampleCnt) with the HWM value stored in HWM register1015is performed by HWM comparator1050(step1300). As noted, a similar comparison, between setSampleCnt and the LWM value held in LWM register1010, is made by LWM comparator1060(step1320). The results of these comparisons are then combined by signal logic1070, in order to identify the symbol indicated by these comparisons (steps1310,1330and1340).

More specifically, if setSampleCnt is greater than the HWM (and so greater than the LWM), the output of HWM comparator1050is a logical “1”, as is the output of LWM comparator1060. Alternatively, if setSampleCnt is not greater than the LWM (and so not greater the HWM), the output of LWM comparator1060is a logical “0”, as is the output of HWM comparator1050. The outputs of HWM comparator1050and LWM comparator1060are then AND'ed together by AND gate1076to produce BitLine signal940, which indicates a logic “1” in the former case, and a logic “0” in the latter case. As noted previously, DataValid signal960indicates the point in time at which the value indicated of BitLine signal940is valid.

If, however, setSampleCnt is not greater than the HWM, but is greater than the LWM, the output of HWM comparator1050is a logical “0”, while the output of LWM comparator1060is a logical “1”. The output of HWM comparator1050is thus inverted by inverter1072, in order to properly detect this case. The output of inverter1072(the inverted output of HWM comparator1050) and the output of LWM comparator1060are then AND'ed together by AND gate1074to produce SyncDetect signal970, which indicates a logic “1” in the case where a “SYNC” symbol is detected, and a logic “0” otherwise. In the former case, setSampleCnt is between the LWM and the HWM (step1320), and the symbol decoded is a “SYNC” symbol (step1330).

While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that, based upon the teachings herein, changes and modifications may be made without departing from this invention and its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of this invention. Moreover, while the invention has been particularly shown and described with reference to these specific embodiments, it will be understood by those skilled in the art that the foregoing and other changes in the form and details may be made therein without departing from the spirit or scope of the invention.