Semiconductor device including deep trench isolation structure comprising dielectric structure and copper structure and method of making the same

A semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure.

BACKGROUND

Semiconductor devices are used in a multitude of electronic devices, such as mobile phones, laptops, desktops, tablets, watches, gaming systems, and various other industrial, commercial, and consumer electronics. Semiconductor devices generally comprise semiconductor portions and wiring portions formed inside the semiconductor portions.

DETAILED DESCRIPTION

A semiconductor device has a first deep trench isolation (DTI) structure in a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure. In some embodiments, the first DTI structure is laterally offset from a first component, such as a first photodiode in the substrate. The first DTI structure reflects an increased amount of radiation, such as near-infrared (NIR) radiation, traveling away from the first component back towards the first component, as compared to DTI structures without the copper structure. Implementing the semiconductor device with the first DTI structure thereby reduces an amount of crosstalk between components of the semiconductor device, as compared to semiconductor devices without DTI structures that have the copper structure, where a lower amount of crosstalk provides for, among other things, improved resolution of an image generated based upon light detected by components in the substrate.

FIGS.1-18Billustrate a semiconductor device100at various stages of fabrication, in accordance with some embodiments.FIGS.1,2,3,4,5,6A,6B,7A,7B,8,9,10,12,13,14,15A,15B,15C,16,17,18A, and18B illustrate cross-sectional views of the semiconductor device100.FIG.11Aillustrates a top view of the semiconductor device100, andFIG.11Billustrates a cross-sectional view of the semiconductor device100taken along line B-B ofFIG.11A.

In some embodiments, a sensor is implemented via the semiconductor device100. The sensor comprises at least one of an image sensor, a proximity sensor, a time of flight (ToF) sensor, an indirect ToF (iToF) sensor, a backside illumination (BSI) sensor, a complementary metal-oxide-semiconductor (CMOS) image sensor, a backside CMOS image sensor, or another type of sensor. Other structures and/or configurations of the semiconductor device100and/or the sensor are within the scope of the present disclosure.

FIG.1illustrates the semiconductor device100according to some embodiments. The semiconductor device100comprises a first substrate102, an interconnect structure122, and a second substrate118. In some embodiments, the first substrate102corresponds to a device wafer of the semiconductor device100and the second substrate118corresponds to a carrier wafer of the semiconductor device100. The first substrate102has a first side126and a second side124, where the first side126corresponds to a back side of the first substrate102and the second side124corresponds to a front side of the first substrate102.

The first substrate102comprises at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. The first substrate102comprises at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or other suitable material. The first substrate102comprises at least one of monocrystalline silicon, crystalline silicon with a <100> crystallographic orientation, crystalline silicon with a <110> crystallographic orientation, crystalline silicon with a <111> crystallographic orientation or other suitable material. The first substrate102has at least one doped region. Other structures and/or configurations of the first substrate102are within the scope of the present disclosure.

In some embodiments, the semiconductor device100comprises components104in the first substrate102. The components104are formed by at least one of doping, ion implantation, molecular diffusion, or other suitable techniques. In some embodiments, the components104comprise at least one of photodiodes, such as pinned layer photodiodes, phototransistors, or photogates, or other suitable components. At least some of the components104can vary from one another to have at least one of different heights, thicknesses, widths, material compositions, etc. Any number of components104in the first substrate102are contemplated.

At least some of the components104comprise at least one of germanium, indium, phosphorous, BF2, arsenic, antimony, fluorine, InAs, InSb, GaSb, GaAs, InP, a silicide, or other suitable material. The components104are configured to sense radiation, such as incident light, which is projected towards the first substrate102. At least some of the components104can comprise a material that is relatively highly absorptive to NIR radiation, such as radiation having a wavelength between about 700 nanometers to about 2500 nanometers. Other structures and/or configurations of the components104are within the scope of the present disclosure.

The interconnect structure122comprises one or more interconnect layers, such as at least one of a first interconnect layer106, a second interconnect layer108, a third interconnect layer110, or a fourth interconnect layer112. The one or more interconnect layers of the interconnect structure122comprise patterned dielectric layers and/or conductive layers that provide interconnections, such as wiring, between at least one of various doped features, circuitry, input/output, etc. of the semiconductor device100. In some embodiments, the interconnect structure122comprises an interlayer dielectric and multilayer interconnect structures, such as at least one of contacts, vias, metal lines, or other type of structure. Other structures and configurations of the interconnect structure122are within the scope of the present disclosure. For purposes of illustration, the interconnect structure122comprises conductive lines120, where the positioning and configuration of such conductive lines might vary depending upon design needs. The interconnect structure122at least one of overlies the first substrate102, is in direct contact with the first substrate102, or is in indirect contact with the first substrate102.

The second substrate118comprises at least one of an epitaxial layer, a SOI structure, a wafer, or a die formed from a wafer. The second substrate118comprises at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or other suitable material. The second substrate118comprises at least one of monocrystalline silicon, crystalline silicon with a <100> crystallographic orientation, crystalline silicon with a <110> crystallographic orientation, crystalline silicon with a <111> crystallographic orientation or other suitable material. The second substrate118has at least one doped region. Other structures and/or configurations of the second substrate118are within the scope of the present disclosure.

In some embodiments, the second substrate118is bonded with the interconnect structure122, such as by at least one of one or more bonding layers, an adhesive, a bonding process, or other suitable techniques. In some embodiments where the second substrate118is bonded with the interconnect structure122using the one or more bonding layers, the one or more bonding layers are between the second substrate118and the interconnect structure122. The second substrate118at least one of overlies the interconnect structure122, is in direct contact with the interconnect structure122, or is in indirect contact with the interconnect structure122.

FIG.2illustrates the semiconductor device100inverted according to some embodiments. An inversion operation is performed such that the first substrate102overlies at least one of the interconnect structure122or the second substrate118. As illustrated inFIG.2, a top surface of the first substrate102corresponds to the back or first side126of the first substrate102, and a bottom surface of the first substrate102corresponds to the front or second side124of the first substrate102. In some embodiments, a portion of the first substrate102on the first side126of the first substrate102is removed, such as after the inversion operation, to reduce a thickness of the first substrate102. The components104are configured to sense radiation, such as incident light, which is projected towards the first substrate102along direction202.

FIG.3illustrates a mask layer302formed over the first substrate102, according to some embodiments. The mask layer302at least one of overlies the first substrate102, is in direct contact with the first substrate102, or is in indirect contact with the first substrate102. In some embodiments, the mask layer302is a hard mask layer. The mask layer302comprises at least one of oxide, nitride, a metal, or other suitable material. The mask layer302is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin on, growth, or other suitable techniques. Other structures and/or configurations of the mask layer302are within the scope of the present disclosure.

FIG.4illustrates the mask layer302patterned to form a patterned mask layer402over the first substrate102, according to some embodiments. According to some embodiments, a photoresist (not shown) is used to form the patterned mask layer402. The photoresist is formed over the mask layer302by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, growth, or other suitable techniques. The photoresist comprises a light-sensitive material, where properties, such as solubility, of the photoresist are affected by light. The photoresist is a negative photoresist or a positive photoresist. With respect to a negative photoresist, regions of the negative photoresist become insoluble when illuminated by a light source, such that application of a solvent to the negative photoresist during a subsequent development stage removes non-illuminated regions of the negative photoresist. A pattern formed in the negative photoresist is thus a negative image of a pattern defined by opaque regions of a template, such as a mask, between the light source and the negative photoresist. In a positive photoresist, illuminated regions of the positive photoresist become soluble and are removed via application of a solvent during development. Thus, a pattern formed in the positive photoresist is a positive image of opaque regions of the template, such as a mask, between the light source and the positive photoresist. One or more etchants have a selectivity such that the one or more etchants remove or etch away one or more layers exposed or not covered by the photoresist at a greater rate than the one or more etchants remove or etch away the photoresist. Accordingly, an opening in the photoresist allows the one or more etchants to form a corresponding opening in the one or more layers under the photoresist, and thereby transfer a pattern in the photoresist to the one or more layers under the photoresist. The photoresist is stripped or washed away after the pattern transfer.

An etching process used to remove portions of the mask layer302to form the patterned mask layer402is at least one of a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process or another suitable etching process. The etching process uses at least one of HF, diluted HF, HCl2, H2S, or other suitable material. In some embodiments, the etching process performed to remove portions of the mask layer302and form the patterned mask layer402also removes at least some of the first substrate102, such as portions of the first substrate102underlying openings in the patterned mask layer402. Other processes and/or techniques for forming the patterned mask layer402are within the scope of the present disclosure.

FIG.5illustrates use of the patterned mask layer402to form recesses502in the first substrate102, according to some embodiments. In some embodiments, an etching process is performed to form the recesses502, where openings in the patterned mask layer402allow one or more etchants applied during the etching process to remove portions of the first substrate102while the patterned mask layer402protects or shields portions of the first substrate102that are covered by the patterned mask layer402. The etching process is at least one of a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process, or another suitable etching process. The etching process uses at least one of HF, diluted HF, HCl2, H2S, or other suitable material. Other processes and/or techniques for forming the recesses502are within the scope of the present disclosure.

One or more recesses overlie a component104. Any number of recesses502over a component104are contemplated. A portion of the first substrate102remains over the component104to separate the recess502from the component104. Other structures and/or configurations of the recesses502are within the scope of the present disclosure.

FIG.6Aillustrates removal of the patterned mask layer402, according to some embodiments. The patterned mask layer402is removed after the recesses502are formed. The patterned mask layer402is removed by at least one of chemical-mechanical polishing (CMP), etching, or other suitable techniques. The etching process is at least one of a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process, or another suitable etching process. The etching process uses at least one of HF, diluted HF, HCl2, H2S, or other suitable material. Other processes and/or techniques for removing the patterned mask layer402are within the scope of the present disclosure.

A portion of the first substrate102defining a recess502has at least one of a first tapered sidewall604or a second tapered sidewall606. At least one of the first tapered sidewall604has a first slope, such as a negative slope, or the second tapered sidewall606has a second slope, such as a positive slope. In some embodiments, the second slope is opposite in polarity relative to the first slope. In some embodiments, a recess502has a triangular shape. In some embodiments, a cross-sectional area of a recess502decreases along the direction202, such that a width of an upper portion of the recess502is greater than a width of a lower portion of the recess502. Other structures and/or configurations of the recesses502are within the scope of the present disclosure.

In some embodiments, the first substrate102having a specific crystallographic orientation, such as crystalline silicon with at least one of a <100> crystallographic orientation, a <110> crystallographic orientation, or a <111> crystallographic orientation, enables an etching process to form the first tapered sidewall604and the second tapered sidewall606. In some embodiments, portions of the first substrate102have different crystallographic orientations, such as at least one of a <100> crystallographic orientation, a <110> crystallographic orientation, or a <111> crystallographic orientation, where etch rates of the etching process differ between the different crystallographic orientations at least due to different densities of the different crystallographic orientations, resulting in the first tapered sidewall604and the second tapered sidewall606being formed by the etching process.

In some embodiments, a first portion of the first substrate102having the first tapered sidewall604and the second tapered sidewall606has a first crystallographic orientation such as <111> crystallographic orientation, and a second portion of the first substrate102that is removed to form the recess502has a second crystallographic orientation such as <100> crystallographic orientation. In some embodiments, a density, such as a surface density, of the first crystallographic orientation is greater than a density, such as a surface density, of the second crystallographic orientation, such that the etching process removes the second portion of the first substrate102while removing little to none of the first portion of the first substrate102due to an etch rate of the second portion of the first substrate102being higher than an etch rate of the first portion of the first substrate102. Other processes and/or techniques for forming the sidewalls defining the recesses502are within the scope of the present disclosure.

A distance602between a top surface of a component104and at least one of an uppermost portion of the recess502or the top surface of the first substrate102is less than or equal to about 40,000 angstroms. A distance608between two adjacent recesses502is between about zero angstroms to about 20,000 angstroms. Other structures and/or configurations of a recess502relative to other elements, features, etc. are within the scope of the present disclosure.FIG.6Billustrates a cross-sectional view of the semiconductor device100, according to some embodiments where at least some recesses502are directly adjacent each other. In some embodiments, recesses, of a set of recesses502a, are directly adjacent each other, such as in a saw tooth configuration. In some embodiments, at least some recesses of one or more sets of recesses502aoverlie a component104.

FIG.7Aillustrates a first dielectric layer702formed over the first substrate102, according to some embodiments. In some embodiments, the first dielectric layer702is in direct contact with the top surface of the first substrate102and/or sidewalls defined in the first substrate102, such as sidewalls defining the recesses502. In some embodiments, the first dielectric layer702is in indirect contact with the top surface of the first substrate102and/or sidewalls defined in the first substrate102. Other structures and/or configurations of the first dielectric layer702are within the scope of the present disclosure.

In some embodiments, the semiconductor device100comprises a buffer layer (not shown) between the first substrate102and the first dielectric layer702, such as formed over the first substrate102prior to forming the first dielectric layer702. The buffer layer is in direct contact with the top surface of the first substrate102and/or sidewalls defined in the first substrate102, such as sidewalls defining the recesses502, or is in indirect contact with the top surface of the first substrate102and/or sidewalls defined in the first substrate102.

The buffer layer comprises at least one of an anti-reflection coating, SiO2, HfSiON, HfSiOx, HfAlOx, HfO2, ZrO2, La2O3, Y2O3, or other suitable material. The buffer layer is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, growth, or other suitable techniques. In some embodiments, the buffer layer comprises a single layer that is configured to provide adhesion between the first dielectric layer702and the first substrate102. According to some embodiments, the buffer layer comprises multiple layers, where an outer layer of the multiple layers is configured to provide adhesion with the first dielectric layer702. When the semiconductor device100comprises the buffer layer, the first dielectric layer702at least one of overlies the buffer layer, is in direct contact with a top surface of the buffer layer, or is in indirect contact with the top surface of the buffer layer. Other structures and/or configurations of the buffer layer are within the scope of the present disclosure.

The first dielectric layer702comprises at least one of SiO, SiO2, SiN, Si3N4, MgO, Al2O3, Yb2O3, ZnO, Ta2O5, ZrO2, HfO2, TeO2, TiO2, or other suitable material. The first dielectric layer702is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, growth, or other suitable techniques. The first dielectric layer702is formed at least one of in the recesses502or over the top surface of the first substrate102. A distance708between a top surface of the first dielectric layer702and the top surface of the first substrate102is less than or equal to about 10,000 angstroms.

A first portion702aof the first dielectric layer702is in a recess502. The first portion702aof the first dielectric layer702has a third tapered sidewall704with which the first tapered sidewall604of the first substrate102aligns. When the semiconductor device100comprises the buffer layer over the first substrate102, a portion of the buffer layer separates the third tapered sidewall704of the first portion702aof the first dielectric layer702from the first tapered sidewall604of the first substrate102.

The first portion702aof the first dielectric layer702has a fourth tapered sidewall706with which the second tapered sidewall606of the first substrate102aligns. When the semiconductor device100comprises the buffer layer over the first substrate102, a portion of the buffer layer separates the fourth tapered sidewall706of the first portion702aof the first dielectric layer702from the second tapered sidewall606of the first substrate102. The first portion702aof the first dielectric layer702overlies a component104. At least one of a portion of the buffer layer or a first portion102aof the first substrate102separate the first portion702aof the first dielectric layer702from the component104.

The first portion702aof the first dielectric layer702in the recess502is a high absorption (HA) structure710, such as due, at least in part, to at least one of the third tapered sidewall704, the first tapered sidewall604, the fourth tapered sidewall706, or the second tapered sidewall606. The HA structure710directs more radiation to the component104underlying the first portion702aof the first dielectric layer702as compared to a portion of the first dielectric layer702and a portion of the first substrate102that do not have one or more tapered sidewalls. One or more additional portions of the first dielectric layer702in recesses502in the first substrate102are similarly constructed HA structures710that overlie a component104. Other structures and/or configurations of the HA structures710are within the scope of the present disclosure.

A distance712between two adjacent HA structures710is between about zero angstroms to about 20,000 angstroms. Other structures and/or configurations of a HA structure710relative to other elements, features, etc. are within the scope of the present disclosure.FIG.7Billustrates a cross-sectional view of the semiconductor device100, according to some embodiments where at least some HA structures710are directly adjacent each other. In some embodiments, HA structures, of a set of HA structures710a, are directly adjacent each other, such as in a saw tooth configuration. In some embodiments, at least some HA structures of one or more sets of HA structures710aoverlie a component104.

FIG.8illustrates a photoresist802formed over the first dielectric layer702, according to some embodiments. The photoresist802at least one of overlies the first dielectric layer702, is in direct contact with the first dielectric layer702, or is in indirect contact with the first dielectric layer702. The photoresist802is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, growth, or other suitable techniques. The photoresist802comprises a light-sensitive material, where properties, such as solubility, of the photoresist802are affected by light. The photoresist802is a negative photoresist or a positive photoresist.

FIG.9illustrates the photoresist802patterned to form a patterned photoresist902over the first dielectric layer702, according to some embodiments. The patterned photoresist902has openings exposing portions of the first dielectric layer702. In some embodiments, the openings in the patterned photoresist902are between the components104, such that the openings do not overlie or are laterally offset from the components104. In some embodiments, an opening in the patterned photoresist902is between two adjacent components104, such that the opening overlies a portion of the first substrate102between the two adjacent components104. According to some embodiments, an opening in the patterned photoresist902overlies a portion of a component104.

FIG.10illustrates trenches1002formed using the patterned photoresist902, according to some embodiments. The trenches1002extend through the first dielectric layer702and into the first substrate102. The trenches1002are at least one of laterally offset from a component104or between two components104. In some embodiments, a trench1002is between two adjacent components104, a second portion102bof the first substrate102separates the trench1002from a first component of the two adjacent components104, and a third portion102cof the first substrate102separates the trench1002from a second component of the two adjacent components104. In some embodiments, an etching process is performed to form the trenches1002, where openings in the patterned photoresist902allow one or more etchants applied during the etching process to remove portions of the first dielectric layer702and/or the first substrate102while the patterned photoresist902protects or shields portions of the first dielectric layer702and/or the first substrate102that are covered by the patterned photoresist902. The etching process is at least one of a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process, or another suitable etching process. The etching process uses at least one of HF, diluted HF, HCl2, H2S, or other suitable material. Other processes and/or techniques for forming the trenches1002are within the scope of the present disclosure.

FIGS.11A-11Billustrate removal of the patterned photoresist902, according to some embodiments. The patterned photoresist902is removed after the trenches1002are formed. The patterned photoresist902is removed by at least one of CMP, etching, or other suitable techniques. In some embodiments, removal of the patterned photoresist902exposes the top surface of the first dielectric layer702(shown inFIG.11A).

A portion of the first substrate102defining a trench1002has a first sidewall1004and a second sidewall1006(shown inFIG.11B). In some embodiments, at least some of the first sidewall1004is tapered and/or at least some of the second sidewall1006is tapered. The first sidewall1004has a first slope, such as a negative slope, and/or the second sidewall1006has a second slope, such as a positive slope. In some embodiments, the second slope is opposite in polarity relative to the first slope.

A portion of the first dielectric layer702defining a trench1002has a third sidewall1008and a fourth sidewall1010. In some embodiments, at least some of the third sidewall1008is tapered and/or at least some of the fourth sidewall1010is tapered. The third sidewall1008has a first slope, such as a negative slope, and/or the fourth sidewall1010has a second slope, such as a positive slope. In some embodiments, the second slope is opposite in polarity relative to the first slope. In some embodiments, a cross-sectional area of a trench1002decreases along the direction202, such that a width of an upper portion of the trench1002is greater than a width of a lower portion of the trench1002.

According to some embodiments, at least some of a sidewall defining a trench1002, such as at least some of the first sidewall1004, at least some of the second sidewall1006, at least some of the third sidewall1008, and/or at least some of the fourth sidewall1010, extend vertically, such as in a direction parallel to the direction202. Other structures and/or configurations of the trenches1002are within the scope of the present disclosure.

In some embodiments, a lowermost portion of a trench1002is lower than an uppermost portion of a component104. According to some embodiments, the lowermost portion of the trench1002is higher than a lowermost portion of the component104. According to some embodiments, the lowermost portion of the trench1002is lower than the lowermost portion of the component104. According to some embodiments, the lowermost portion of the trench1002is level or coplanar with the lowermost portion of the component104. Other structures and/or configurations of the trenches1002relative to the components104, other elements, features, etc. are within the scope of the present disclosure.

FIG.12illustrates a first barrier layer1202formed over the first dielectric layer702and in the trenches1002, according to some embodiments. In some embodiments, the first barrier layer1202is in direct contact with the top surface of the first dielectric layer702and/or sidewalls defined in the first substrate102and/or the first dielectric layer702, such as sidewalls defining the trenches1002. In some embodiments, the first barrier layer1202is in indirect contact with the top surface of the first dielectric layer702and/or sidewalls defined in the first substrate102and/or the first dielectric layer702. Other structures and/or configurations of the first barrier layer1202relative to other elements, features, etc. are within the scope of the present disclosure.

The first barrier layer1202comprises at least one of aluminum oxide, Al2O3, hafnium oxide, tantalum nitride, or other suitable material. The first barrier layer1202is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, growth, or other suitable techniques.

A first portion of the first barrier layer1202is in a trench1002. The first portion of the first barrier layer1202has a fifth sidewall1204with which at least one of the first sidewall1004of the first substrate102or the third sidewall1008of the first dielectric layer702aligns. The first portion of the first barrier layer1202in the trench1002has a sixth sidewall1206with which at least one of the second sidewall1006of the first substrate102or the fourth sidewall1010of the first dielectric layer702aligns. Other structures and/or configurations of the first barrier layer1202relative to other elements, features, etc. are within the scope of the present disclosure.

FIG.13illustrates a second dielectric layer1302formed over the first barrier layer1202and in the trenches1002, according to some embodiments. In some embodiments, the second dielectric layer1302is in direct contact with the first barrier layer1202. In some embodiments, the second dielectric layer1302is in indirect contact with the first barrier layer1202. The first barrier layer1202is between the second dielectric layer1302and at least one of the first substrate102or the first dielectric layer702. Other structures and/or configurations of the second dielectric layer1302relative to other elements, features, etc. are within the scope of the present disclosure.

The second dielectric layer1302comprises at least one of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, fluorinated silica glass (FSG), or other suitable material. The second dielectric layer1302is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, growth, or other suitable techniques. A coefficient of thermal expansion of the second dielectric layer1302is between about 1 to about 20 (such as between about 2.5 to about 16). Other structures and/or configurations of the second dielectric layer1302are within the scope of the present disclosure.

A first portion of the second dielectric layer1302is in a trench1002. The first portion of the second dielectric layer1302has a seventh sidewall1304with which a ninth sidewall1308of the first portion of the first barrier layer1202aligns. The first portion of the second dielectric layer1302in the trench1002has an eighth sidewall1306with which a tenth sidewall1310of the first portion of the first barrier layer1202aligns. Other structures and/or configurations of the second dielectric layer1302relative to other elements, features, etc. are within the scope of the present disclosure.

FIG.14illustrates a first copper layer1402formed over the second dielectric layer1302and in the trenches1002, according to some embodiments. In some embodiments, the first copper layer1402is in direct contact with the second dielectric layer1302. In some embodiments, the first copper layer1402is in indirect contact with the second dielectric layer1302. The second dielectric layer1302is between the first copper layer1402and the first barrier layer1202. Other structures and/or configurations of the first copper layer1402relative to other elements, features, etc. are within the scope of the present disclosure.

The first copper layer1402is formed by at least one of a plating process, PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, growth, or other suitable techniques. In some embodiments, the plating process is performed with a current density of at least about 3 milli-amperes per square centimeter (such as at least about 5 milli-amperes per square centimeter). In some embodiments, an initial current density of the plating process is at least about 3 milli-amperes per square centimeter (such as at least about 5 milli-amperes per square centimeter). In some embodiments, the current density of the plating process increases to at least about 3 milli-amperes per square centimeter (such as least about 5 milli-amperes per square centimeter) within a threshold duration of time after the plating process is started. The threshold duration of time is less than or equal to at least one of about 5 milliseconds, about 10 milliseconds, about 100 milliseconds, about 1 second, or other suitable duration of time. Performing the plating process with the current density and/or the initial current density of at least about 3 milli-amperes per square centimeter (such as at least about 5 milli-amperes per square centimeter) inhibits formation of voids in the first copper layer1402. Accordingly, the plating process with the current density and/or the initial current density of at least about 3 milli-amperes per square centimeter (such as at least about 5 milli-amperes per square centimeter) provides for a reduction in a porosity of the first copper layer1402as compared to other copper layers and/or structures formed with a current density and/or an initial current density of less than 3 milli-amperes per square centimeter (and/or less than 5 milli-amperes per square centimeter). In some embodiments, a seed layer (not shown) is formed, over the second dielectric layer1302and in the trenches1002, prior to performing the plating process. The seed layer comprises at least one of copper or other suitable material. Other processes and/or techniques for forming the first copper layer1402are within the scope of the present disclosure.

The second dielectric layer1302protects the first barrier layer1202from damage, such as during formation of the first copper layer1402. In some embodiments, the second dielectric layer1302inhibits damage to the first barrier layer1202during the plating process and/or prevents plating solution, used in the plating process, from dissolving the first barrier layer1202.

A first portion1402aof the first copper layer1402is in a trench1002. The first portion1402aof the first copper layer1402has an eleventh sidewall1404with which a thirteenth sidewall1408of the first portion of the second dielectric layer1302aligns. The first portion1402aof the first copper layer1402in the trench1002has a twelfth sidewall1406with which a fourteenth sidewall1410of the first portion of the second dielectric layer1302aligns. Other structures and/or configurations of the first copper layer1402relative to other elements, features, etc. are within the scope of the present disclosure.

In some embodiments, the first portion of the first barrier layer1202in the trench1002, the first portion of the second dielectric layer1302in the trench1002, and the first portion1402aof the first copper layer1402in the trench1002form a DTI structure1502(shown inFIG.15A) that extends through the first dielectric layer702and/or into the first substrate102. The DTI structure1502is a backside DTI (BDTI) structure or a different type of DTI structure. The semiconductor device100comprises one or more DTI structures1502. Any number of DTI structures1502are contemplated. The DTI structures1502are at least one of laterally offset from a component104or between two components104. In some embodiments, a DTI structure1502is between two adjacent components104, the second portion102bof the first substrate102separates the DTI structure1502from a first component of the two adjacent components104, and the third portion102cof the first substrate102separates the DTI structure1502from a second component of the two adjacent components104.

FIGS.15A-15Billustrates removal of a first section of the semiconductor device100, according to some embodiments. In some embodiments, the first section is removed by at least one of CMP, etching, or other suitable techniques. The first section comprises a top section of the semiconductor device100that is over the first dielectric layer702, such as comprising at least one of a portion of the first barrier layer1202that is over the first dielectric layer702, a portion of the second dielectric layer1302that is over the first dielectric layer702, or a portion of the first copper layer1402that is over the first dielectric layer702. In some embodiments, removal of the first section of the semiconductor device100exposes at least one of a top surface1504of the first dielectric layer702or a top surface1506of a DTI structure1502.

A width1508of a DTI structure1502is between about 600 angstroms to about 67,000 angstroms. A length1510of the DTI structure1502is between about 3,000 angstroms to about 200,000 angstroms. The length1510of the DTI structure1502is at least about 3 times (such as at least about 5 times) the width1508of the DTI structure1502, such that the DTI structure1502has a relatively high aspect ratio. Other structures and/or configurations of the DTI structures1502are within the scope of the present disclosure.

FIG.15Billustrates an enlarged view of section1502a(depicted inFIG.15A) of the semiconductor device100, according to some embodiments. The section1502acomprises at least a portion of a DTI structure1502. The DTI structure1502comprises at least one of a barrier structure1512, a dielectric structure1514, or a copper structure1516. The barrier structure1512comprises a portion of the first barrier layer1202. The dielectric structure1514comprises a portion of the second dielectric layer1302. The copper structure1516comprises a portion of the first copper layer1402. The dielectric structure1514is between the barrier structure1512and the copper structure1516. The barrier structure1512is between the dielectric structure1514and the first substrate102. A thickness1518of the barrier structure1512is at least about 0.01 times (such as at least about 0.02 times) the width1508(FIG.15A) of the DTI structure1502. A thickness1520of the dielectric structure1514is at least about 0.005 times (such as at least about 0.01 times) the width1508(FIG.15A) of the DTI structure1502. Other structures and/or configurations of the DTI structures1502are within the scope of the present disclosure.

FIG.15Cillustrates an enlarged view of the section1502aof the semiconductor device100, according to some embodiments where the dielectric structure1514is a multi-layer structure. The dielectric structure1514comprises any number of dielectric layers such that an interface is defined between the layers. In some embodiments, each layer of the dielectric structure1514, such as at least one of a layer1514a, a layer1514bbetween the layer1514aand the copper structure1516, etc., has a coefficient of thermal expansion between about 1 to about 20 (such as between about 2.5 to about 16). Each layer of the dielectric structure1514comprises at least one of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, FSG, or other suitable material. In some embodiments, the layer1514ais different than the layer1514b. In some embodiments, the layer1514acomprises a portion of the second dielectric layer1302and the layer1514bcomprises a portion of another dielectric layer that is formed over the second dielectric layer1302prior to forming the first copper layer1402. Other structures and/or configurations of the DTI structures1502are within the scope of the present disclosure.

In some embodiments, the dielectric structure1514protects the first substrate102from being damaged by expansion of the copper structure1516, and thereby improves performance of the semiconductor device100and/or reduces an amount of dark current in the semiconductor device100. In some embodiments, the dielectric structure1514acts as a stress release layer to release stress induced as a result of a coefficient of thermal expansion difference between the first substrate102and the copper structure1516.

FIG.16illustrates a third dielectric layer1602formed over the first dielectric layer702, according to some embodiments. The third dielectric layer1602at least one of overlies top surfaces1506of the DTI structures1502, is in direct contact with top surfaces1506of the DTI structures1502, or is in indirect contact with top surfaces1506of the DTI structures1502. The third dielectric layer1602at least one of overlies the top surface1504of the first dielectric layer702, is in direct contact with the top surface1504of the first dielectric layer702, or is in indirect contact with the top surface1504of the first dielectric layer702. The third dielectric layer1602comprises at least one of SiO, SiO2, SiN, Si3N4, MgO, Al2O3, Yb2O3, ZnO, Ta2O5, ZrO2, HfO2, TeO2, TiO2, or other suitable material. The third dielectric layer1602is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, growth, or other suitable techniques. Other structures and/or configurations of the third dielectric layer1602are within the scope of the present disclosure.

FIG.17illustrates a color filter layer1702formed over the third dielectric layer1602, according to some embodiments. The color filter layer1702at least one of overlies the third dielectric layer1602, is in direct contact with a top surface of the third dielectric layer1602, or is in indirect contact with the top surface of the third dielectric layer1602. The color filter layer1702comprises at least one of a pigment-dispersed color resist (PDCR) material, a photosensitive substance, a photoinitiator substance, a multifunctional monomer, one or more additives, a leveling agent, an adhesion promotor, resin, polymer soluble in alkaline solution, color paste, pigment, dispersant, solvent, or other suitable material. The color filter layer1702filters certain wavelengths of radiation. In some embodiments, different portions of the color filter layer1702have different material compositions to enable different wavelengths to be filtered. A first portion1702aof the color filter layer1702overlies a first component104, has a first material composition, and filters first wavelengths. A second portion1702bof the color filter layer1702overlies a second component104, has a second material composition, and filters second wavelengths different than the first wavelengths. A third portion1702cof the color filter layer1702overlies a third component104, has a third material composition, and filters third wavelengths different than the first wavelengths and/or the second wavelengths. The color filter layer1702is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin on, growth, or other suitable techniques. Other structures and/or configurations of the color filter layer1702are within the scope of the present disclosure.

FIG.18Aillustrates a lens array1802formed over the color filter layer1702, according to some embodiments. In some embodiments, the lens array1802at least one of overlies the color filter layer1702, is in direct contact with a top surface of the color filter layer1702, or is in indirect contact with the top surface of the color filter layer1702. In some embodiments, the lens array1802is formed by at least one of thermal reflow, microplastic embossing, microdroplet jetting, photolithography, reactive ion etching, machining, or other suitable techniques. Lenses of the lens array1802are at least one of micro-lenses or other suitable lenses. The lens array1802comprises at least one of a first lens1802aover a first component104, a second lens1802bover a second component104, or a third lens1802cover a third component104. In some embodiments, one or more lenses of the lens array1802overlie one or more portions of the first dielectric layer702having tapered sidewalls, such as one or more HA structures710. Other structures and/or configurations of the lens array1802are within the scope of the present disclosure.

In some embodiments, radiation is projected towards the semiconductor device100, such as at least one of in the direction202or in a different direction. At least some of the radiation passes through at least one of the lens array1802, the color filter layer1702, the third dielectric layer1602, the first dielectric layer702, or some of the first substrate102, and is at least one of sensed, detected, or converted to electrons by the components104. HA structures710provide for an increase in an amount of radiation that is at least one of sensed, detected or converted by the components104, as compared to other sensors that do not implement the HA structures710. Implementing the HA structures710mitigates reflection or deflection by the first substrate102of radiation, projected towards a component104, away from the component104. In some embodiments, the radiation comprises NIR radiation, such as radiation with a wavelength between about 700 nanometers to about 2500 nanometers. Other wavelengths of radiation directed to the components104by the HA structures710are within the scope of the present disclosure.

In some embodiments, DTI structures1502prevent and/or mitigate crosstalk between components104. The DTI structures1502prevent and/or mitigate radiation from traveling from one component104to an adjacent component104, or simply away from one component104when there is no adjacent the component104. Radiation traveling away from the component104is reflected by a DTI structure1502back towards the component104. Generally, much more radiation is detected by a component104when the radiation is redirected back towards the component104. Implementing the DTI structures1502with copper structures, such as the copper structure1516, provides for an increase in an amount of radiation that is reflected by a DTI structure1502back towards a component104, as compared to other sensors that do not implement the DTI structures1502with the copper structures. The increase in the amount of radiation reflected by DTI structures1502is due at least to an improved reflectivity of the DTI structures1502with copper as compared to other DTI structures that do not comprise copper and/or to a reduced porosity of the DTI structures1502as compared to other DTI structures with higher porosities. In some embodiments, a copper structure of a DTI structure1502can reflect at least about 95% of radiation, such as NIR radiation, flowing towards the DTI structure1502. In some embodiments, the reduced porosity of the DTI structures1502is due at least to forming the DTI structures1502with copper. The reduced porosity of the DTI structures1502is due at least to performing the plating process to form the first copper layer1402(with which the DTI structures1502are formed) with at least one of the current density or the initial current density of at least about 3 milli-amperes per square centimeter (such as at least about 5 milli-amperes per square centimeter). Implementing the DTI structures1502with the copper structures, such as the copper structure1516, provides for a reduction in crosstalk between components104, such as a reduction of about 40% in NIR crosstalk between components104(such as components104that are configured to detect NIR radiation), as compared to other sensors that do not implement the DTI structures1502with the copper structures.

FIG.18Billustrates a cross-sectional view of the semiconductor device100, according to some embodiments where HA structures710are directly adjacent each other. In some embodiments, at least some HA structures of a set of HA structures710that are between two adjacent DTI structures1502are directly adjacent each other, such as in a saw tooth configuration.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure.

In some embodiments, a coefficient of thermal expansion of the dielectric structure is between about 2.5 to about 16.

In some embodiments, the dielectric structure includes at least one of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, or fluorinated silica glass.

In some embodiments, the barrier structure includes at least one of aluminum oxide, hafnium oxide, or tantalum nitride.

In some embodiments, the semiconductor device includes a first dielectric layer overlying the substrate, wherein a first portion of the first dielectric layer has a first sidewall that aligns with a first portion of a first sidewall of the barrier structure.

In some embodiments, a second portion of the first dielectric layer has a tapered sidewall that aligns with a tapered sidewall of a first portion of the substrate.

In some embodiments, the semiconductor device includes a photodiode within the substrate, wherein the first DTI structure is laterally offset from the photodiode.

In some embodiments, the semiconductor device includes a second DTI structure within the substrate and laterally offset from the photodiode, wherein the photodiode is between the first DTI structure and the second DTI structure.

In some embodiments, the second DTI structure includes a second barrier structure, a second dielectric structure, and a second copper structure. The second dielectric structure is between the second barrier structure and the second copper structure, and the second barrier structure is between the substrate and the second dielectric structure.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a photodiode within a substrate. The semiconductor device includes a first dielectric layer overlying the substrate. A first portion of the first dielectric layer overlies the photodiode. The first portion of the first dielectric layer has a tapered sidewall. A first portion of the substrate separates the first portion of the first dielectric layer from the photodiode. The semiconductor device includes a first deep trench isolation (DTI) structure. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure.

In some embodiments, the first portion of the substrate has a first tapered sidewall that aligns with the tapered sidewall of the first portion of the first dielectric layer.

In some embodiments, a second portion of the first dielectric layer overlies the photodiode, the second portion of the first dielectric layer has a tapered sidewall; and the first portion of the substrate has a second tapered sidewall that aligns with the tapered sidewall of the second portion of the first dielectric layer.

In some embodiments, the first tapered sidewall of the first portion of the substrate has a first slope, the second tapered sidewall of the first portion of the substrate has a second slope, and the second slope is opposite in polarity relative to the first slope.

In some embodiments, the first DTI structure is laterally offset from the photodiode.

In some embodiments, a second portion of the substrate separates the first DTI structure from the photodiode.

In some embodiments, the semiconductor device includes a second DTI structure laterally offset from the photodiode. The photodiode is between the first DTI structure and the second DTI structure, the second DTI structure includes a second barrier structure, a second dielectric structure, and a second copper structure, the second dielectric structure is between the second barrier structure and the second copper structure, and the second barrier structure is between the substrate and the second dielectric structure.

In some embodiments, the semiconductor device includes a lens array, wherein a first lens of the lens array overlies the first portion of the first dielectric layer.

In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a first dielectric layer over a substrate. The method includes forming a first trench extending through the first dielectric layer and into the substrate. The method includes forming a first barrier layer over the first dielectric layer and in the first trench. The method includes forming a second dielectric layer over the first barrier layer and in the first trench. The method includes forming a first copper layer over the second dielectric layer and in the first trench.

In some embodiments, forming the first copper layer includes performing a plating process with a current density of at least about 5 milli-amperes per square centimeter.

In some embodiments, the method includes forming a first recess within the substrate, wherein forming the first dielectric layer includes forming a first portion of the first dielectric layer in the first recess, and the first portion of the first dielectric layer overlies a photodiode within the substrate.

It will be appreciated that layers, features, elements, etc. depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments. Additionally, a variety of techniques exist for forming the layers, regions, features, elements, etc. mentioned herein, such as at least one of etching techniques, planarization techniques, implanting techniques, doping techniques, spin-on techniques, sputtering techniques, growth techniques, or deposition techniques such as chemical vapor deposition (CVD), for example.