System for reducing noise induced from reference plane currents

A method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path for the electrical trace on the circuit board such that the second path references a ground plane whereby the second path is substantially similar to the first path. The method further includes electrically coupling the first path to the second path at each of the ends of the first and second paths such that noise induced into the electrical trace is reduced.

TECHNICAL FIELD

This disclosure relates in general to the field of computers, and more particularly to a method of reducing noise induced from reference plane currents in a computer system.

BACKGROUND

One type of information handling system is a computer system. Examples of the computer system include, but are not limited to, mainframes, workstations, servers, personal computers, notebook computers, laptop computers, and personal digital assistants (PDA). Each computer system may include a processor, memory, and storage media such as a hard drive.

As consumer demand has increased for smaller and more compact computer systems, manufacturers strive to implement new methods to meet these demands. One of these methods includes manufacturing circuit boards with narrow copper traces. Given the smaller and more compact size, the traces are typically routed in close proximity (usually above or below) to a voltage or ground plane.

Voltage planes or ground planes on a circuit board are commonly referred to and serve as “reference planes” for traces routed on either side of them. These reference planes can also function to distribute power by carrying current between power sources, such as voltage regulators, and their associated loads, such as processors and chips. Some reference planes will serve as voltage planes (e.g., a plane with a non-zero voltage) and other planes will serve as ground planes. As such, current loads are drawn from a voltage plane and returned to a ground plane to complete an electrical circuit.

However, any large or fast current carried on a plane can cause “noise” to couple to a trace that is routed near the plane. Generally, the noise is most evident when the trace is routed parallel to the direction of the current change. Manufacturers who have attempted to correct this problem typically have installed filters, such as a capacitor or a low-pass filter made from a capacitor and a resistor, on the trace.

Unfortunately, with some circuit boards, the size of filter needed to remove the noise from the trace also blocks some of or the entire signal on the trace. Moreover, the use of series resistors in low-pass filters can change the voltage drop across a diode. Thus, in some instances, the filter will introduce signal errors into the trace.

Other attempts to correct the noise problem include physical modifications to the circuit board or to the information handling system. Modifications include relocating components such that traces avoid routes over high current densities or routing traces perpendicular to current densities. Given the current mechanical or size constraints of some information handling systems, the relocation of components is simply not an option.

In one particular correction attempt, manufacturers routed sensitive traces near ground planes instead of current planes to reduce the amount of induced noise. Because the amount of induced noise is related to the density of current in the plane, this correction assumes that the ground planes in the circuit board have a lower current density than the voltage planes (e.g., there are more ground planes than current planes).

SUMMARY

Thus, a need has arisen for a method of reducing noise induced from reference plane currents.

In accordance with the teachings of the present invention, the disadvantages and problems associated with a method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path for the electrical trace on the circuit board such that the second path references a ground plane whereby the second path is substantially similar to the first path. The method further includes electrically coupling the first path to the second path at each of the ends of the first and second paths such that noise induced into the electrical trace is reduced.

In another embodiment, a circuit board includes a voltage plane forming a first layer of the circuit board. The voltage plane provides an electrical current. The circuit board further includes a ground plane forming a second layer of the circuit board. The ground plane provides a ground for the electrical current. The circuit board further includes an electrical trace routed over a portion of the circuit board. The electrical trace includes a first path and a second path such that the first path references the ground plane and the second path references the voltage plane whereby the first path is substantially similar to the second path. The first path is electrically coupled to the second path at each of the ends of the paths such that noise induced into the electrical trace is reduced.

In further embodiments, an information handling system includes a processor, a memory communicatively coupled to the processor and a circuit board having an electrical trace. The circuit board reduces noise on the electrical trace induced from a reference plane. The circuit board includes a voltage plane forming a first layer of the circuit board. The voltage plane provides an electrical current. The circuit board further includes a ground plane forming a second layer of the circuit board. The ground plane provides a ground for the electrical current. The circuit board further includes an electrical trace routed over a portion of the circuit board. The electrical trace includes a first path and a second path such that the first path references the ground plane and the second path references the voltage plane whereby the first path is substantially similar to the second path. The first path is electrically coupled to the second path at each of the ends of the paths such that noise induced into the electrical trace is reduced.

All, some, or none of these technical advantages may be present in various embodiments of the present invention. Other technical advantages will be apparent to one skilled in the art from the following figures, descriptions, and claims.

DETAILED DESCRIPTION

Preferred embodiments of the present disclosure and their advantages are best understood by reference toFIGS. 1 through 4, where like numbers are used to indicate like and corresponding parts.

Referring first toFIG. 1, a block diagram of information handling system10is shown, according to teachings of the present disclosure. Information handling system10or computer system preferably includes at least one microprocessor or central processing unit (CPU)12. CPU12may include processor14for handling integer operations and coprocessor16for handling floating point operations. CPU12is preferably coupled to cache18and memory controller20via CPU bus22. System controller I/O trap24preferably couples CPU bus22to local bus26and may be generally characterized as part of a system controller.

Main memory28of dynamic random access memory (DRAM) modules is preferably coupled to CPU bus22by a memory controller20. Main memory28may be divided into one or more areas such as system management mode (SMM) memory area (not expressly shown).

Basic input/output system (BIOS) memory30is also preferably coupled to local bus26. FLASH memory or other nonvolatile memory may be used as BIOS memory30. A BIOS program (not expressly shown) is typically stored in BIOS memory30. The BIOS program preferably includes software which facilitates interaction with and between information handling system10devices such as a keyboard (not expressly shown), a mouse (not expressly shown), or one or more I/O devices. BIOS memory30may also store system code (note expressly shown) operable to control a plurality of basic information handling system10operations.

Graphics controller32is preferably coupled to local bus26and to video memory34. Video memory34is preferably operable to store information to be displayed on one or more display36. Display36may be an active matrix or passive matrix liquid crystal display (LCD), a cathode ray tube (CRT) display or other display technology. In selected applications, uses or instances, graphics controller32may also be coupled to an integrated display, such as in a portable information handling system implementation.

Bus interface controller or expansion bus controller38preferably couples local bus26to expansion bus40. In one embodiment, expansion bus40may be configured as an Industry Standard Architecture (“ISA”) bus. Other buses, for example, a Peripheral Component Interconnect (“PCI”) bus, may also be used.

In certain information handling system embodiments, expansion card controller42may also be included and is preferably coupled to expansion bus40as shown. Expansion card controller42is preferably coupled to a plurality of information handling system expansion slots44. Expansion slots44may be configured to receive one or more expansion cards such as modems, fax cards, communications cards, and other input/output (I/O) devices.

Interrupt request generator46is also preferably coupled to expansion bus40. Interrupt request generator46is preferably operable to issue an interrupt service request over a predetermined interrupt request line in response to receipt of a request to issue interrupt instruction from CPU12.

I/O controller48, often referred to as a super I/O controller, is also preferably coupled to expansion bus40. I/O controller48preferably interfaces to an integrated drive electronics (IDE) hard drive drive (HDD)50, CD-ROM (compact disk-read only memory) drive52and/or a floppy disk drive (FDD)54. Other disk drive devices (not expressly shown) that may interface to the I/O controller include a removable hard drive, a zip drive, a CD-RW (compact disk-read/write) drive, and a CD-DVD (compact disk—digital versatile disk) drive.

Communication controller56is preferably provided and enables information handling system10to communicate with communication network58, e.g., an Ethernet network. Communication network58may include a local area network (LAN), wide area network (WAN), Internet, Intranet, wireless broadband or the like. Communication controller56may be employed to form a network interface for communicating with other information handling systems (not expressly shown) coupled to communication network58.

As illustrated, information handling system10preferably includes power supply60, which provides power to the many components and/or devices that form information handling system10. Power supply60may be a rechargeable battery, such as a nickel metal hydride (“NiMH”) or lithium ion battery, when information handling system10is embodied as a portable or notebook computer, an A/C (alternating current) power source, an uninterruptible power supply (UPS) or other power source.

Power management microcontroller62preferably monitors a charge level of an attached battery or UPS to determine when and when not to charge the battery or UPS. Power management microcontroller62is preferably also coupled to main power switch68, which the user may actuate to turn information handling system10on and off. While power management microcontroller62powers down one or more portions or components of information handling system10, e.g., CPU12, display36, or HDD50, etc., when not in use to conserve power, power management microcontroller62itself is preferably substantially always coupled to a source of power, preferably power supply60.

Power supply60is preferably coupled to power management microcontroller62. Power management microcontroller62preferably controls the distribution of power from power supply60. More specifically, power management microcontroller62preferably includes power output64coupled to main power plane66which may supply power to CPU12as well as other information handling system components. Power management microcontroller62may also be coupled to a power plane (not expressly shown) operable to supply power to an integrated panel display (not expressly shown), as well as to additional power delivery planes preferably included in information handling system10.

Computer system10may also include power management chip set72. Power management chip set72is preferably coupled to CPU12via local bus26so that power management chip set72may receive power management and control commands from CPU12. Power management chip set72is preferably connected to a plurality of individual power planes operable to supply power to respective components of information handling system10, e.g., HDD50, FDD54, etc. In this manner, power management chip set72preferably acts under the direction of CPU12to control the power supplied to the various power planes and components of a system.

Real-time clock (RTC)74may also be coupled to I/O controller48and power management chip set72. Inclusion of RTC74permits timed events or alarms to be transmitted to power management chip set72. Real-time clock74may be programmed to generate an alarm signal at a predetermined time as well as to perform other operations.

Referring toFIG. 2, a cross-sectional view of circuit board100is shown, according to an example embodiment of the present disclosure. Circuit board100may include voltage plane101and ground plane102. Voltage plane101, is typically formed from a layer of copper but can also be formed from any other suitable material that conducts electricity. The copper layer permits voltage plane101to provide an electrical current to components associated with circuit board100. Generally, voltage plane101includes any layer or plane that has a non-zero voltage.

Ground plane102is similarly formed from a copper layer but can also be formed from any other suitable material that conducts electricity. Ground plane102serves to provide a ground or ground path for the electrical current provided by voltage plane101or other electrical source. As such, voltage plane101and ground plane102may form part of an electrical circuit that supplies an electrical current to components associated with circuit board100. In some embodiments of the present disclosure, voltage plane101and ground plane102are formed close together on circuit board100.

Circuit board100also includes signal planes103and104. Signal planes103,104are layers that contain electrical traces or traces105, which can be used to carry electrical current or signals such as data and information. Typically, each signal plane103,104is set or placed closer to either voltage plane101or ground plane102and, as such, is said to “reference” a particular plane. For example, signal plane103is set closer to voltage plane101than to ground plane102, thus signal plane103references voltage plane101. Hence, voltage plane101and ground plane102are commonly referred to as reference planes.

Trace105, formed and routed within a portion of circuit board100, may include two or more separate paths. First path106may be formed in signal plane103that references voltage plane101. Second path108may be formed in signal plane104that references ground plane102. Generally, one path will reference voltage plane101and the other path will reference ground path102.

First path106is electrically coupled to second path108at vias110. Vias110are formed by routing electrical connections from the ends of first path106to the ends of second path108. As each via110passes through ground plane102or voltage plane101, opening112may be formed to provide an electrically isolated opening for via110to pass therethrough.

By forming trace105with first path106and second path108, the amount of induced noise into trace105coupled from the reference planes, namely voltage plane101and/or ground plane102, is reduced. For example, when a large or fast moving current I (illustrated for clarity only) travels on voltage plane101, noise N+ may be induced into first path106given the proximity of the path to the reference plane. Returning current IR (illustrated for clarity only) that is traveling in the opposite direction of current I moves through ground plane102. In doing so, ground plane102may induce an approximately equal but opposite noise N− in second path108. Generally, each noise is substantially similar to the other noise but in opposite direction. Thus, when noise N+ induced on first path106is combined with opposite noise N− induced on second path108, the “resultant” noise on trace105is reduced or even cancelled.

Referring toFIG. 3, a perspective view of circuit board100ofFIG. 2is shown, according to an example embodiment of the present disclosure. The perspective view is shown without illustrating signal planes103,104in order to provide clarity of the disclosure. Trace105including first path106and second path108is routed on a portion of circuit board100.

Because the amount of noise induced from a reference plane depends on the orientation of trace105to the direction of the current in the reference plane, first path106and second path108typically follow a substantially similar path in their respective signal layers. For example, first path106may be routed from point A to point A′, while second path108follows a similar route or path that extends from B to B′ with each path formed within their respective signal layer (not shown for clarity).

Therefore, by combining the noise from any two substantially similar paths formed on different signal layers that reference different planes (e.g., voltage plane101and ground plane102) such that induced noise on each path is substantially similar but opposite of the other, the resultant noise on trace105is reduced or cancelled.

Referring toFIG. 4, a cross-sectional view of circuit board115having an equal number of ground planes102,122as voltage planes101,121is shown, according to example embodiments of the present disclosure. Circuit board115illustrates an example of a typical computer board that includes several layers including six signal planes103,104and124, two voltage planes101,121and two ground planes102,122.

Circuit board115may be viewed as formed about centerline120. From centerline120, voltage plane101and ground plane102are formed close together with each plane being approximately equal distance from centerline120such that the planes are symmetrically oriented with respect to circuit board115.

Extending further from centerline120, signal planes103and104are formed near their respective reference planes being approximately equal distance from centerline120such that signal planes103and104, and first path106and second path108are symmetrically oriented with respect to circuit board115about centerline120. Formed on signal plane103, first path106of trace105references voltage plane101. Likewise, second path108of trace105formed on signal plane104references ground plane102. First path106and second path108are electrically coupled at each of the ends of the paths with vias110.

In certain embodiments, first path105is located at a distance from voltage plane101that is substantially equal to the distance second path108is located from ground plane102. In some embodiments, the symmetry of first path106to second path108with respect to centerline120creates a mirror image of the paths. Additionally, in other embodiments, the symmetrical arrangement of first path106and voltage plane101creates a mirror image of second path108and ground plane102with respect to centerline120.

Mirror imaging of the paths facilitates inducing a substantially similar amount of noise in each path but in opposite directions. Therefore, having paths with a symmetrical arrangement allows for the resultant noise in trace105to be substantially reduced or even cancelled.

Although the present disclosure has been described with respect to a specific embodiment, various changes and modifications will be readily apparent to one skilled in the art. The present disclosure is not limited to the illustrated embodiment, but encompasses such changes and modifications that fall within the scope of the appended claims.