Electrostatic discharge protection circuit

An electrostatic discharge (ESD) protection circuit includes a substrate, and a plurality of unit bipolar transistors formed in the substrate. Each of the plurality of unit bipolar transistors may include a first-conductivity-type buried layer formed in the substrate, a first-conductivity-type well formed over the first-conductivity-type buried layer, a second-conductivity-type well formed in the first-conductivity-type well, a first-conductivity-type vertical doping layer vertically formed from the surface of the substrate to the first-conductivity-type buried layer so as to surround the first-conductivity-type well, and a first-conductivity-type doping layer and a second conductivity-type doping layer formed in the second-conductivity-type well. The first-conductivity-type doping layer of any one of the adjacent unit bipolar transistors and the first-conductivity-type vertical doping layer of another one of the adjacent unit bipolar transistors may be connected to each other.

The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2008-0081275 (filed on Aug. 20, 2008), which is hereby incorporated by reference in its entirety.

BACKGROUND

To protect an integrated circuit (IC) from static electricity, an electrostatic discharge (ESD) protection circuit may be used. A high-voltage IC which uses a high driving voltage and operates in an environment sensitive to static electricity requires a higher level of ESD protection than that of a general logic IC.

FIG. 1Ashows the configuration of an ESD protection circuit using a general Laterally Diffused Metal Oxide Semiconductor (LDMOS) device. Referring toFIG. 1A, an ESD circuit110and an internal circuit120are connected in parallel between a first pad105, to which a driving voltage VDDis applied from an external device, and a second pad107, to which a ground voltage VSSis applied. The ESD circuit110is a grounded-gate LDMOS device.

FIG. 1Bshows a current-voltage curve of the grounded-gate LDMOS110shown inFIG. 1A. The current-voltage curve S1represents characteristics when static electricity is applied to the first pad105or the second pad107. Referring toFIG. 1B, noise or glitches due to static electricity are introduced from an external device into the first pad105. Therefore, when the grounded-gate LDMOS110is operated, a latch-up phenomenon, wherein the grounded-gate LDMOS110is not turned off even when the static electricity is no longer present, is generated.

This is because the sustaining voltage or the snapback voltage Vsp of the grounded-gate LDMOS110is lower than the driving voltage VDDof the internal circuit120, as shown inFIG. 1B. Due to the latch-up phenomenon, the grounded-gate LDMOS110breaks down. As a result, this may lead to breakdown of the internal circuit120.

A high-voltage diode may be used as the ESD protection circuit. The high-voltage diode does not generate the above-described latch-up phenomenon, but occupies a large area. Thus, the high-voltage diode is not suitable for an IC.

SUMMARY

Embodiments relate to a semiconductor device, and more particularly, to an electrostatic discharge (ESD) protection circuit for protecting a semiconductor device from static electricity. Embodiments relate to an ESD protection circuit which is capable of being implemented even in a small area without generating a latch-up phenomenon.

Embodiments relate to an electrostatic discharge (ESD) protection circuit which includes a substrate, and a plurality of unit bipolar transistors formed in the substrate. Each of the plurality of unit bipolar transistors includes a first-conductivity-type buried layer formed in the substrate, a first-conductivity-type well formed over the first-conductivity-type buried layer, a second-conductivity-type well formed in the first-conductivity-type well, a first-conductivity-type vertical doping layer vertically formed from the surface of the substrate to the first-conductivity-type buried layer so as to surround the first-conductivity-type well, and a first-conductivity-type doping layer and a second conductivity-type doping layer formed in the second-conductivity-type well. The first-conductivity-type doping layer of any one of the adjacent unit bipolar transistors and the first-conductivity-type vertical doping layer of another one of the adjacent unit bipolar transistors are connected to each other.

Embodiments relate to a method for forming an electrostatic discharge protection circuit which includes forming a substrate, and forming a plurality of unit bipolar transistors in the substrate. The forming of each of the plurality of unit bipolar transistors includes forming a first-conductivity-type buried layer in the substrate, forming a first-conductivity-type well over the first-conductivity-type buried layer, forming a second-conductivity-type well in the first-conductivity-type well, forming a first-conductivity-type vertical doping layer vertically from the surface of the substrate to the first-conductivity-type buried layer so as to surround the first-conductivity-type well, and forming a first-conductivity-type doping layer and a second conductivity-type doping layer in the second-conductivity-type well. The first-conductivity-type doping layer of any one of the adjacent unit bipolar transistors and the first-conductivity-type vertical doping layer of another one of the adjacent unit bipolar transistors are formed to be connected to each other.

According to the ESD protection circuit according to embodiments, it is possible to prevent a latch-up phenomenon by setting the sustaining voltage to be larger than the driving voltage, and improve area efficiency by increasing current amount per unit area.

DESCRIPTION

ExampleFIG. 2is a circuit diagram of an electrostatic discharge (ESD) protection circuit210according to embodiments. Referring to exampleFIG. 2, the ESD protection circuit210and an internal circuit220may be connected in parallel between a first pad205, to which a driving voltage VDDis applied from an external device, and a second pad207, to which a ground voltage VSSis applied. The ESD protection circuit210serves to protect the internal circuit220from static electricity introduced through the first pad205.

That is, the ESD protection circuit210operates only when static electricity is introduced thorough the first pad205. The ESD protection circuit210is turned off in a normal state in which static electricity is not introduced, and is turned on by impact ionization due to static electricity when static electricity is introduced. The ESD protection circuit210serves to pass the introduced electrostatic current to the second pad207so as to prevent the internal circuit220from being damaged due to electrostatic current.

The ESD circuit210may include a plurality of unit bipolar transistors (e.g.,212,214and216) and a plurality of resistors R1, R2and R3. The plurality of unit bipolar transistors212,214and216may be connected in series between the first pad205and the second pad207. For example, as shown in exampleFIG. 2, three bipolar transistors212,214and216may be connected in series between the first pad205and the second pad207.

That is, the collector of the first bipolar transistor212may be connected to the first pad205, and the emitter of the first bipolar transistor212is connected to a first node N1. The first resistor R1may be connected between the base of the first bipolar transistor212and the first node N1. The collector of the second bipolar transistor214may be connected to the first node N1and the emitter of the second bipolar transistor214may be connected to a second node N2. The second resistor R2may be connected between the base of the second bipolar transistor214and the second node N2. Similarly, the collector of the third bipolar transistor216may be connected to the second node N2. The emitter of the third bipolar transistor216may be connected to the second pad207. The third resistor R3may be connected between the base of the third bipolar transistor216and the second pad207.

A method for forming an electrostatic discharge protection circuit includes forming a substrate310, and forming a plurality of unit bipolar transistors212,214and216in the substrate310. The forming of each of the plurality of unit bipolar transistors212,214and216includes forming a first-conductivity-type buried layer (315,317,319) in the substrate, forming a first-conductivity-type well (322,324,326) over the first-conductivity-type buried layer (315,317,319), forming a second-conductivity-type well (322-1,324-1,326-1) in the first-conductivity-type well (322,324,326), forming a first-conductivity-type vertical doping layer (332,334,336) vertically from the surface of the substrate310to the first-conductivity-type buried layer (315,317,319) so as to surround the first-conductivity-type well (322,324,326), and forming a first-conductivity-type doping layer (344,354,364) and a second conductivity-type doping layer (346,356,366) in the second-conductivity-type well. The first-conductivity-type doping layer (344,354,364) of any one of the adjacent unit bipolar transistors and the first-conductivity-type vertical doping layer (332,334,336) of another one of the adjacent unit bipolar transistors are formed to be connected to each other.

Each of the plurality of unit bipolar transistors212,214and216may be implemented by an NPN-type bipolar transistor. Hereinafter, the detailed structure of each of the unit bipolar transistors will be described.

ExampleFIG. 3is a cross-sectional view of the ESD protection circuit210shown in exampleFIG. 2. For convenience of description, the first pad205, the second pad207, the resistors R1, R2and R3, and wires are denoted by symbols.

Referring to exampleFIGS. 2 and 3, the ESD protection circuit210may include a semiconductor substrate310, the plurality of unit bipolar transistors212,214and216formed in the semiconductor substrate310, the plurality of resistors R1, R2and R3and a second-conductivity-type guard ring372. A device isolation film311defining a device isolation region and an active region may be formed in the semiconductor substrate310.

For example, the first bipolar transistor212includes the N-type buried layer315, the N-type deep well322, the P-type well322-1, the N-type vertical doping layer332, the P-type doping layer344and the N-type doping layer346.

The first-conductivity-type buried layer (e.g.,315) may be formed by selectively doping impurity ions (e.g., N-type impurity ions) into the semiconductor substrate310. The first-conductivity-type deep well (e.g.,322) may be formed adjacent to the upper side of the first-conductivity-type buried layer (e.g.,315).

The second-conductivity-type well (e.g.,322-1) may be formed in the upper surface of the first-conductivity-type deep well (e.g.,322). The second-conductivity-type doping layer344and the first-conductivity-type doping layer346may be formed in the second-conductivity-type well (e.g.,322-1) so as to be isolated from each other.

The first-conductive-layer vertical doping layer (e.g.,332) may be vertically formed from the surface of the semiconductor substrate310to the first-conductivity-type buried layer (e.g.,315) so as to surround the first-conductivity-type deep well (e.g.,322). Therefore, since the first-conductivity-type deep well (e.g.,322) is surrounded by the first-conductivity-type buried layer (e.g.,315) and the first-conductivity-type vertical doping layer (e.g.,332), the first-conductivity-type deep well (e.g.,322) may be isolated from the semiconductor substrate (e.g., the P-type substrate310) by the first-conductivity-type vertical doping layer (e.g.,332).

The electrons and holes in the first-conductivity-type deep well (e.g.,322) are not discharged to the semiconductor substrate310. This is because the vertical doping layer (e.g.,332) and the first-conductivity-type buried layer (e.g.,315) surrounding the first-conductivity-type (e.g., N-type) deep well (e.g.,322) are reverse biased with respect to the semiconductor substrate (e.g., P-type substrate), by applying the high voltage (e.g., VDD) thereto. As a result, the plurality of unit bipolar transistors212,214and216may be isolated from the semiconductor substrate310, and the plurality of unit bipolar transistors212,214and216may be isolated from each other.

The second-conductivity-type doping layer344and the first-conductive doping layer346may be formed in the second-conductivity-type well (e.g.,322-1) so as to be isolated from each other. The second-conductivity-type doping layer344becomes the second-conductivity-type base of the bipolar transistor212, and the first-conductivity-type doping layer346becomes the first-conductivity-type emitter of the bipolar transistor212. In addition, the first-conductivity-type vertical doping layer (e.g.,332) becomes the first-conductivity-type collector of the bipolar transistor212. The first-conductivity-type doping layer (e.g.,346), the second-conductivity-type doping layer (e.g.,344) and the first-conductivity-type doping layer (e.g.,332) may form the NPN-type bipolar transistor.

Any one of the plurality of resistors R1, R2and R3may be connected between the first-conductivity-type doping layer and the second-conductivity-type doping layer of each of the plurality of unit bipolar transistors. For example, the first resistor R1of the plurality of resistors R1, R2and R3is connected between the second-conductivity-type base344and the first-conductive-emitter346of the first bipolar transistor.

The first-conductivity-type doping layer of any one of the unit bipolar transistors and the first-conductivity-type vertical doping layer of another unit bipolar transistor may be connected to each other. For example, the first-conductivity-type doping layer346of the first bipolar transistor212and the first-conductivity-type vertical doping layer352of the second bipolar transistor214may be connected to each other. The first-conductivity-type doping layer356of the second bipolar transistor214may be connected to the first-conductivity-type vertical doping layer362of the third bipolar transistor216.

The first-conductivity-type vertical doping layer of any one of the plurality of unit bipolar transistors (e.g.,212,214and216) may be connected to the first pad205. The first-conductivity-type doping layer of another one of the plurality of unit bipolar transistors (e.g.,212,214and216) may be connected to the second pad207.

For example, the first-conductivity-type vertical doping layer342of the first bipolar transistor212may be connected to the first pad205, and the first-conductivity-type doping layer366of the third bipolar transistor214may be connected to the second pad207. The second-conductivity-type guard ring372may be connected to the second pad207.

The high-concentration first-conductivity-type impurities may be doped into the upper sides of the first-conductivity-type vertical doping layers (e.g.,332,334and336) of the plurality of unit bipolar transistors (e.g.,212,214and216), for ohmic contact. For example, the first-conductivity-type impurities having higher concentration than that of impurities implanted when forming the first-conductivity-type vertical doping layer may be doped into the upper sides of the first-conductivity-type vertical doping layers (e.g.,332,334and336), for ohmic contact. Similarly, the second-conductivity-type impurities, that are present at a higher concentration than the impurities of the semiconductor substrate (e.g., P-type substrate), may be doped into the second-conductivity-type guard ring372, for ohmic contact.

ExampleFIG. 4Ais a graph G1showing the current-voltage characteristics of the unit bipolar transistor212shown in exampleFIG. 3upon the introduction of static electricity. The current refers to the collector-emitter current of the unit bipolar transistor212and the voltage refers to the collector-emitter voltage.

As shown in the graph g1of exampleFIG. 4A, since the bipolar transistor used in the ESD protection circuit uses a snapback region but does not have a Double Diffused Drain (DDD) structure like a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device, a snapback phenomenon is not generated and the sustaining voltage of the bipolar transistor is relatively higher than that of the LDMOS device. When static electricity is introduced into the first pad205, the sustaining voltage Vsp of the unit bipolar transistor (e.g.,212) manufactured in a 0.35-mm 60-V Bipolar CMOS-DMOS (BCD) process is 23 V, which is at least twice the sustaining voltage, 10 V or less, of the LDMOS device. Since the sustaining voltage of the unit bipolar transistor is lower than the operation voltage, 60 V, of the internal circuit, the ESD protection circuit210according to embodiments has a structure in which the plurality of unit bipolar transistors are connected, for example, a structure in which three unit bipolar transistors shown in exampleFIG. 3are connected in series, in order to eliminate the snapback phenomenon.

ExampleFIG. 4Bis a graph G2showing the current-voltage characteristics of the ESD protection circuit210shown in exampleFIG. 3upon the introduction of static electricity. For example, in order to operate the internal circuit220shown in exampleFIG. 2, the driving voltage VDD applied to the first pad205is 60 V. An initial maximum voltage is referred to as a triggering voltage Vt1and an initial minimum voltage which appears after the triggering voltage Vt1is referred to as a sustaining voltage Vsp. A region between the triggering voltage Vt1and the sustaining voltage Vsp is referred to as a snapback region.

As shown in the graph of exampleFIG. 4B, the sustaining voltage Vsp of the ESD protection circuit210is 69 V. The sustaining voltage Vsp of the ESD protection circuit is three times the sustaining voltage (23 V) of the unit bipolar transistor shown in exampleFIG. 4A.

As shown in exampleFIG. 3, the first-conductivity-type deep well (e.g.,322) of each of the unit bipolar transistors212,214and216is isolated from the semiconductor substrate (e.g., P-type substrate) by the first-conductivity-type buried layer (e.g.,315) and the first-conductivity-type vertical doping layer (e.g.,332).

The sustaining voltage Vsp of the ESD protection circuit210in which the three unit bipolar transistors212,214and216having the structure shown in exampleFIG. 3are connected in series is equal to a value (Vsp=69 V) obtained by summing the sustaining voltages (23 V) of the unit bipolar transistors212,214and216. Accordingly, the ESD protection circuit having the sustaining voltage (e.g., Vsp=69 V) higher than the driving voltage (VDD=60 V) may be configured by connecting the unit bipolar transistors212,214and216having the structure shown in exampleFIG. 3.

If the unit bipolar transistors212,214and216share the P-type semiconductor substrate310without isolation, it is impossible to obtain a sustaining voltage higher than the driving voltage. This is because the unit bipolar transistors are not sequentially triggered but are simultaneously triggered by the current of the substrate. Accordingly, the bipolar transistors212,214and216need to be isolated by the first-conductivity-type buried layer315,317and319.

To protect the semiconductor device using the driving voltage VDD of 60 V, the sustaining voltage of the ESD protection circuit210, in which the three unit bipolar transistors connected in series as shown in exampleFIG. 3and having the sustaining voltage characteristics of 23 V, becomes 69 V.

Therefore, since the sustaining voltage Vsp of the ESD protection circuit210is greater than the driving voltage (VDD=60 V), after static electricity is introduced into the first pad205so as to operate the ESD protection circuit210, a latch-up phenomenon is not generated.

The triggering voltages Vt1of the unit bipolar transistors may be set by the resistors R1, R2and R3connected between the second-conductivity-type bases344,354and364and the first-conductivity-type emitters346,356and366of the unit bipolar transistors212,214and216. That is, the triggering voltage Vt1of the ESD protection circuit210is also equal to a value obtained by summing the triggering voltages of the unit bipolar transistors212,214and216. Accordingly, the triggering voltage Vt1of the ESD protection circuit210may be set by the resistors R1, R2and R3.

For example, the triggering voltage Vt1of the ESD protection circuit210may be set to be smaller than the breakdown voltage of the internal circuit220by the resistors R1, R2and R3. This is because, if the triggering voltage Vt1of the ESD protection circuit210is greater than the breakdown voltage of the internal circuit, the internal circuit may break down.

If static electricity is introduced into the second pad207, the unit bipolar transistors212,214and216of the ESD protection circuit210operate so as to have forward diode characteristics. This is because the second-conductivity-type guard ring372connected to the second pad207forms parasitic diodes D1, D2and D3in association with the plurality of unit bipolar transistors212,214and216.

For example, the first PN junction parasitic diode D1may be formed between the guard ring372and the buried layer315and the first-conductivity-type vertical doping layer332of the first bipolar transistor212, the second PN junction parasitic diode D2may be formed between the guard ring372and the buried layer317and the first-conductivity-type vertical doping layer334of the second bipolar transistor214, and the third PN junction parasitic diode D3may be formed between the guard ring372and the buried layer319and the first-conductivity-type vertical doping layer336of the third bipolar transistor216. The first to third PN junction parasitic diodes D1, D2and D3correspond to the parasitic diodes236,234and232shown in exampleFIG. 2, respectively.

Accordingly, if static electricity is introduced into the second pad207, since the first, second third PN junction diodes have the forward bias characteristics, static electricity introduced into the second pad207is discharged to the first pad205through the first, second and third PN junction diodes D1, D2and D3and, in particular, is mostly discharged through the first PN junction diode D1.

ExampleFIG. 5is a table for comparison of the performance of an ESD protection circuit using a high-voltage diode and the performance of the ESD protection circuit shown in exampleFIG. 3. The ESD protection circuit using the high-voltage diode is referred to as the former circuit and the ESD protection circuit210shown in exampleFIG. 3is denoted by “stacked bipolar” and is referred to as the latter circuit.

Referring to exampleFIG. 5, the sustaining voltage (VDD=10 V) of the former circuit is smaller than the driving voltage (VDD=60 V), but the sustaining voltage (VDD=69 V) of the latter circuit is larger than the driving voltage (VDD=60 V). In addition, the current amount per unit area (314 (nA/mm2)) of the latter circuit is significantly larger than current amount per unit area (37 (nA/mm2)) of the former circuit. In addition, in view of a Human Body Level (HBM) which is a general ESD robustness criterion, the HBM (12 kV) of the latter circuit is six times the HBM (2 kV) of the former circuit. In addition, the latter circuit is better than the former circuit in terms of area.

According to the ESD protection circuit having the structure shown in exampleFIG. 3, it is possible to prevent the latch-up phenomenon by setting the sustaining voltage to be larger than the driving voltage and improve area efficiency by increasing the current amount per unit area.

It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.