Patterning for substrate fabrication

Various examples of a technique for forming a pattern for substrate fabrication are disclosed herein. In an example, a method includes receiving a substrate. A patterned resist is formed on the substrate and has a trench defined therein. A dielectric is deposited on the patterned resist and within the trench such that the dielectric narrows a width of the trench to further define the trench. A fabrication process is performed on a region of the substrate underlying the trench defined by the dielectric.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, such scaling down has also been accompanied by increased complexity in design and manufacturing of devices incorporating these ICs. Parallel advances in manufacturing have allowed these increasingly complex designs to be fabricated with precision and reliability.

As merely one example, advances in lithography have reduced the sizes of circuit devices and enabled the formation of increasingly complex structures. In general, lithography is the formation of a pattern on a target. In one type of lithography, referred to as photolithography, radiation such as ultraviolet light passes through or reflects off a mask before striking a photoresist coating on the target. The photoresist includes one or more components that undergo a chemical transition when exposed to radiation. A resultant change in property allows either the exposed or the unexposed portions of the photoresist to be selectively removed. In this way, photolithography transfers a pattern from the mask onto the photoresist, which is then selectively removed to reveal the pattern. The target then undergoes processing steps that take advantage of the shape of the remaining photoresist to create features on the target.

DETAILED DESCRIPTION

Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features.

As semiconductor fabrication technologies continue to evolve, device sizes continue to shrink, thereby pushing the limits of optics, chemistry, and physics. For example, device features may be formed on a substrate by first applying a resist material and lithographically exposing portions of the resist. A resultant change in property allows either the exposed or the unexposed portions of the resist to be selectively removed. A number of factors determine the minimum feature size that may be formed including capillary forces acting on the semisolid resist material. Capillary forces may draw portions of a developed resist together and cause the resist to collapse. This problem is exacerbated when a resist pattern has a tall and narrow (i.e., high aspect ratio) trench disposed in between resist features. Other properties of the lithographic system, the resist, and the developing process may also affect the quality of the resist at the trench boundaries. In turn, the quality of the resist boundaries determines the precision and uniformity of the features formed using the resist. In contrast, collapsed resist may lead to narrowing, necking, bridging, and other defects in the circuit. In this way and others, resist performance directly affects the critical dimension (CD) of integrated circuits and other aspects of circuit size and quality.

As described below, the present disclosure provides a technique to address these issues and to improve resist performance. However, unless otherwise noted, no embodiment is required to provide any particular advantage or to resolve any particular aspect of resist collapse.

Some examples of the technique are described with reference toFIGS. 1-6B. In that regard,FIG. 1is a flow diagram of a method100of fabricating a workpiece according to various aspects of the present disclosure. Additional steps can be provided before, during, and after the method100, and some of the steps described can be replaced or eliminated for other embodiments of the method100.FIGS. 2A, 3A, 4A, 5A, 5C, and 6Aare top-view diagrams of the workpiece200at various stages of the method100of fabricating the workpiece200according to various aspects of the present disclosure.FIGS. 2B, 3B, 4B, 5B, 5D, and 6Bare cross-sectional diagrams of the workpiece200at various stages of the method100of fabricating the workpiece200according to various aspects of the present disclosure. In particular,FIGS. 2B, 3B, 4B, 5B, 5D, and 6Bare cross-sections taken along line202of the corresponding top-view diagrams.

Referring first to block102ofFIG. 1and toFIGS. 2A and 2B, a workpiece200is received that includes a substrate204that is to undergo a fabrication process. The manufacture of integrated circuits includes a wide array of fabrication processes including implantation processes, etching processes, deposition processes, and epitaxy processes, and any number of these processes and others may be performed on the substrate204. In order to selectively process portions of the substrate204, a resist and/or masking materials may be deposited on the substrate and patterned to expose only the portions to be processed (e.g., implanted, etched, etc.), as explained in further detail below.

With respect to the substrate204itself, in various examples, the substrate204comprises an elementary (single element) semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; a non-semiconductor material, such as soda-lime glass, fused silica, fused quartz, and/or calcium fluoride (CaF2); and/or combinations thereof. The substrate204may include one or more layers of varying composition, such as a Silicon-On-Insulator (SOI) substrate204that includes a semiconductor layer disposed on an insulator layer that is disposed on another semiconductor layer.

Referring to block104ofFIG. 1and referring still toFIGS. 2A and 2B, a resist206is formed on the substrate204. The resist206represents any resist material, and in many embodiments, the resist206includes a photoresist material sensitive to radiation such as UV light, deep ultraviolet (DUV) radiation, and/or EUV radiation. However, the principles of the present disclosure apply equally to e-beam resists and other direct-write resist materials. The resist206may be applied by any suitable technique, and an exemplary embodiment, the resist206is applied in a liquid form using a spin coating (i.e., spin-on) technique. Spin coating may use centrifugal force to disperse the resist206in a liquid form across the surface of the substrate204in a substantially uniform thickness. To facilitate application, the resist206may include a solvent, which when removed, leaves the resist206in a solid or semisolid form. The solvent may be driven off as part of the spin coating, during a settling process, and/or during a post-application/pre-exposure baking (i.e., prebake) process.

Regarding its composition, the resist206may include one or more photosensitive materials. For example, the resist206may include a photo-acid generator (PAG) that, as the name implies, generates an acid within those portions of the resist206exposed to radiation. A polymer within the resist206, such as an acid-cleavable polymer or acid-cross-linkable polymer, is sensitive to this generated acid, causing the portion of the polymer in the exposed regions to undergo a chemical reaction. The resist206may also include a photobase generator (PBG) and/or photo-decomposable quencher (PDQ) to reduce acid concentration in unexposed or marginally-exposed regions of the resist206and thereby inhibit the chemical reaction of the polymer in these regions. In some embodiments, the resist206also includes one or more chromophores, solvents, and/or surfactants.

Referring to block106ofFIG. 1, a lithographic exposure is performed on the workpiece200that exposes selected regions of the resist206to radiation. Suitable radiation includes UV light, deep ultraviolet (DUV) radiation, and/or EUV radiation. In further examples, the selected regions are exposed to an e-beam or ion beam. In these cases and others, the exposure of block106causes a chemical reaction to occur in the exposed regions of the resist206.

Referring to block108ofFIG. 1and toFIGS. 3A and 3B, a developing process is performed on the workpiece200to form a patterned resist206. The developing process may begin with a post-exposure bake. Following the post-exposure bake, a developer is applied to the workpiece200. The developer dissolves or otherwise removes either the exposed regions in the case of a positive resist development process or the unexposed regions in the case of a negative resist development process. Suitable positive developers include TMAH (tetramethyl ammonium hydroxide), KOH, and NaOH, and suitable negative developers include solvents such as n-butyl acetate, ethanol, hexane, benzene, and toluene.

After the developer is applied to the workpiece200, the patterned resist206may be rinsed, and a hard bake may be performed on the workpiece200to further stabilize the pattern of the resist206.

The pattern of the resist206after developing may have any suitable shape and structure and may include features of resist206separated by trenches302. In some embodiments, the pattern is governed by the stability of the resist206, limitations of a lithographic system used to pattern the resist206, fabrication processes to be performed using the resist206, and/or other factors. For example, capillary action and other forces may cause the features of the resist206to collapse if a narrow trench is formed between the features. Accordingly, in some such embodiments, the pattern is structured to limit the ratio of trench height (as indicated by marker304) to trench width (as indicated by marker306) to a particular threshold (e.g., a ratio of ≤10). The particular threshold may depend on a number of factors including resist stability and other properties of the resist206, properties of the substrate204, and/or properties of a subsequent fabrication processes that may induce the resist206to collapse, such as processing temperature.

While the ratio threshold may seem to imply that a narrower trench may be formed by simply thinning the resist206, in some applications, a fabrication process that follows relies on a particular minimum thickness of the resist206. For example, an ion implantation process may rely on the resist206having at least a minimum thickness to block the ions from reaching the substrate204. Likewise, an etching process may rely on the resist206having at least a minimum thickness to withstand an etchant long enough to etch the exposed portions of the substrate204.

Accordingly, to produce a narrow aspect ratio, in some embodiments, a wider trench is formed and then narrowed by conformally depositing a material within the trench. Referring to block110ofFIG. 1and toFIGS. 4A and 4B, a dielectric material402is deposited on the developed resist206and within the trenches302between the features of the resist206. The dielectric material402may include a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and/or other suitable insulator materials, and may be formed to any suitable thickness. In some examples, the dielectric material402includes silicon oxide and is formed to a vertical thickness404and a horizontal vertical thickness406of between about 50 nm and about 100 nm. The dielectric material402may be deposited conformally such that the vertical thickness404and horizontal vertical thickness406are substantially equivalent, or non-conformally. As can be seen, forming the dielectric material402with a given thickness in a trench reduces the width of the trench by about twice the horizontal thickness406of the dielectric material402. Thus, in some embodiments, the deposition of the dielectric material402allows for forming trenches with a height/width ratio greater than using the resist206alone. In one such embodiment, deposition of the dielectric material402creates suitable trenches302with a ratio of trench height to trench width that is ≥13.

The dielectric material402may be deposited using any suitable technique. In some examples, the dielectric material402is deposited using a catalyst deposition process such as Catalyst Enhanced Chemical Vapor Deposition (CECVD). In some examples, the dielectric material402is deposited using Plasma Enhanced CVD (PECVD). The deposition technique may be tuned to produce any suitable deposition rate, and in various examples, the deposition rate for the dielectric material402is between about 1 Å and about 10 Å per minute. The deposition process may be performed at any suitable temperature. In some examples, the dielectric material402is deposited at a temperature between about 50° C. and about 100° C. or between about room temperature (˜20° C.) and about 100° C. Regarding the lower bound, these ranges have been determined to be sufficiently warm to promote deposition of the dielectric material402, which may be inhibited by temperatures below these ranges. Regarding the upper bound, some resist206materials deform at deposition temperatures exceeding 100° C. Accordingly, performing deposition at the above temperature ranges allows the dielectric material402to be deposited without risk to the resist206material.

Referring to block112ofFIG. 1and toFIGS. 5A, 5B, 5C, and 5D, a fabrication process is performed on the workpiece200. The fabrication process may be any suitable process and may utilize the patterned resist206to processes exposed portions of the substrate204differently from those portions covered by the resist206. For example, the fabrication process may include an ion implantation process to form a junction isolation structure502in the substrate204. The junction isolation structure502is suitable to isolate pixel regions504of an image sensor or devices of other integrated circuits. A junction isolation structure502isolates circuit elements by creating a reverse biased p-n junction between the elements. Accordingly, the implantation process may implant ions of p-type dopants, such as boron or BF2, into a substrate204that contains n-type dopants, such as phosphorus or arsenic, or may implant ions of n-type dopants into a substrate204that contains p-type dopants.

The implantation process may be performed using any suitable implantation energy, and the thickness and composition of the resist206and the dielectric material402may be configured such that the ions have sufficient energy that they are implanted through the single thickness of the dielectric material402at the bottom of the trench302but not enough to implant through the resist206or through the dielectric material402on the sidewalls of the trench302. Additionally or in the alternative, the dielectric material402at the bottom of the trench302may be removed prior to the implantation. Referring toFIGS. 5A and 5B, in an example, an anisotropic (directional) etching is performed to remove the dielectric material402from the bottom of the trench302while leaving the dielectric material402on the side surfaces of the resist206. The anisotropic etching may also remove the dielectric material402from the top surface of the resist206. Any suitable anisotropic etching technique may be used such as a dry or plasma etching technique. With the dielectric material402removed from the bottom of the trench302, the above implantation process may be performed on the substrate204with enough implantation energy to form the junction isolation structure502but not enough to implant through the resist206or through the dielectric material402on the sidewalls of the trench302, as shown inFIGS. 5C and 5D.

In further embodiments, the fabrication process includes an ion implantation process to produce other types of features such as source/drain regions. In yet further embodiments, the fabrication process of block112includes etching processes, deposition processes, epitaxy processes, and/or other suitable processes. In these embodiments and others, the patterned resist206and dielectric material402are used to fabricate a gate stack, to fabricate an interconnect structure, to form non-planar devices by etching to expose a fin or by epitaxially growing fin material, and/or to form other suitable features.

Referring to block114ofFIG. 1and toFIGS. 6A and 6B, the dielectric material402is removed and the resist206is stripped. These materials may be removed by any suitable etching and/or stripping technique such as dry etching, wet etching, and/or other etching methods (e.g., Reactive Ion Etching (RIE), Chemical Mechanical Polishing/Planarization (CMP), etc.), and the dielectric material402and resist206may be removed concurrently or in multiple steps with different chemistries targeting different materials.

Referring to block116, the workpiece200is provided for further fabrication processes. For example, the workpiece200may be used to fabricate an image sensor, other integrated circuit chip, a System-On-a-Chip (SOC), and/or a portion thereof, and thus the subsequent fabrication processes may form various passive and active microelectronic devices such as sensors, resistors, capacitors, inductors, diodes, Metal-Oxide Semiconductor Field Effect Transistors (MOSFET), Complementary Metal-Oxide Semiconductor (CMOS) transistors, Bipolar Junction Transistors (BJT), Laterally Diffused MOS (LDMOS) transistors, high power MOS transistors, other types of transistors, and/or other circuit elements.

Further examples of the technique are described with reference toFIGS. 7A-22B. In that regard,FIGS. 7A and 7Bare flow diagrams of a method700of fabricating a workpiece using orthogonal features according to various aspects of the present disclosure. Additional steps can be provided before, during, and after the method700, and some of the steps described can be replaced or eliminated for other embodiments of the method700.FIGS. 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, and 22Aare top-view diagrams of the workpiece800at various stages of the method700of fabricating the workpiece800according to various aspects of the present disclosure.FIGS. 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, and 22Bare cross-sectional diagrams of the workpiece800at various stages of the method700of fabricating the workpiece800according to various aspects of the present disclosure. In particular,FIGS. 8B, 9B, 10B, 11B, 12B, 13B, and 14Bare cross-sections taken along line802of the corresponding top-view diagrams, whileFIGS. 15B, 16B, 17B, 18B, 19B, 20B, 21B, and 22Bare cross-sections taken along line1502of the corresponding top-view diagrams.

In contrast to some of the above examples, method700divides an area of the workpiece800into orthogonal sets of parallel stripes. Stripes running in a first direction are fabricated first, and perpendicular stripes are fabricated thereafter.

Referring first to block702ofFIG. 7Aand toFIGS. 8A and 8B, a workpiece800is received that includes a substrate804that is to undergo a fabrication process. The substrate804may be substantially similar to the substrate204ofFIGS. 2A-6B. In various examples, the substrate804includes an elementary (single element) semiconductor, a compound semiconductor, a non-semiconductor material, and/or combinations thereof.

Referring to block704ofFIG. 7A, a first resist804is applied to the substrate. This may be performed substantially as described in block104ofFIG. 1. The first resist804may be substantially similar to the resist206ofFIGS. 2A-6B. In various examples, the first resist804includes a photoresist material, an e-beam resist material, and/or other suitable resist material and is applied by spin coating or other suitable technique.

Referring to block706ofFIG. 7A, a lithographic exposure is performed on the workpiece800that exposes selected regions of the first resist804to radiation. This may be performed substantially as described in block106ofFIG. 1.

Referring to block708ofFIG. 7Aand toFIGS. 9A and 9B, a developing process is performed on the workpiece800to form a patterned first resist804. This may be performed substantially as described in block108ofFIG. 1. The developing process may begin with a post-exposure bake. Following the post-exposure bake, a developer is applied to the workpiece800. The developer dissolves or otherwise removes either the exposed regions of the first resist804in the case of a positive resist development process or the unexposed regions of the first resist804in the case of a negative resist development process. After the developer is applied to the workpiece800, the patterned first resist804may be rinsed, and a hard bake may be performed on the workpiece800to further stabilize the pattern of the first resist804.

The pattern of the resist804after developing may have any suitable shape and structure. In some embodiments, the pattern is governed by the stability of the resist804, limitations of a lithographic system used to pattern the resist804, fabrication processes to be performed using the resist804, and/or other factors. In some examples, the patterned resist includes sets of substantially parallel features of the first resist804extending in a first direction902. The features of the first resist804may have any suitable aspect ratio, and in some such embodiments, the pattern is structured to limit the ratio of trench height (as indicated by marker904) to trench width (as indicated by marker906) to a particular threshold (e.g., a ratio of ≤5).

Referring to block710ofFIG. 7Aand toFIGS. 10A and 10B, a first dielectric material1002is deposited on the patterned first resist804and particularly on the side surfaces of the resist804. This may be performed substantially as described in block110ofFIG. 1. The first dielectric material1002may be substantially similar to the dielectric material402ofFIGS. 4A-6B. The first dielectric material1002may include a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and/or other suitable insulator materials, and may be formed to any suitable thickness. The first dielectric material1002may be selected to have a different etchant sensitivity than the first resist804. In some examples, the first dielectric material1002includes silicon oxide and is formed to a thickness1004of between about 20 nm and about 50 nm.

The first dielectric material1002may be deposited by any suitable technique or combination of techniques such as CECVD and/or PECVD. In some examples, the first dielectric material1002is deposited at a temperature between about 50° C. and about 100° C. or between about room temperature (˜20° C.) and about 100° C. These ranges have been determined to be sufficiently warm to promote deposition of the dielectric material1002without risk of deforming the first resist806. In contrast, deposition temperatures below these ranges may not allow proper deposition, and deposition temperatures above these ranges may cause the first resist806to deform.

Referring to block712ofFIG. 7Aand toFIGS. 11A and 11B, a second resist1102is deposited on the first resist804and the first dielectric material1002. The second resist1102may be substantially similar to the first resist804and may include a photoresist material, an e-beam resist material, and/or other suitable resist material. Alternately, the second resist1102may be a lithographically inert dielectric (e.g., some spin-on dielectrics) or other suitable resist material. In some embodiments, the second resist1102is selected to have different etchant sensitivity than the first dielectric material1002.

The second resist1102may be applied by any suitable technique, such as spin coating, and may be cured using heat, radiation, e-beam exposure, and/or plasma exposure. In embodiments where the second resist1102includes a photoresist material, the second resist1102may be exposed using a flood exposure to stabilize the photosensitive components.

Referring to block714ofFIG. 7Aand toFIGS. 12A and 12B, the second resist1102is planarized to expose the first dielectric material1002. This may be performed by any suitable technique, and in some examples, the second resist1102is planarized by a CMP process. In addition to the second resist1102, the CMP process may planarize the first resist804and the first dielectric material1002. By exposing the first dielectric material1002, the planarization creates features of the first resist804and features of the second resist1102separated by the first dielectric material1002.

The planarization of block714exposes the vertical channels of the first dielectric material1002, and referring to block716ofFIG. 7Aand toFIGS. 13A and 13B, the vertical channels of the first dielectric material1002are selectively removed by an etching process such as dry etching, wet etching, and/or other etching methods. The etchant chemistries, temperature, duration, and other parameters may be configured to spare the first resist804and the second resist1102from significant etching. The removal of the first dielectric material1002leaves trenches1302extending in the first direction902between the features of the first resist804and the features of the second resist1102. The trenches1302formed by the removal of the first dielectric material1002may be significantly narrower than those formed using resist material(s) alone, and in some embodiments, the ratio of trench height to trench width exceeds 50.

Referring to block718ofFIG. 7Aand toFIGS. 14A and 14B, a fabrication process is performed on the workpiece800. This may be performed substantially as described in block112ofFIG. 1. The fabrication process may be any suitable process and may utilize the patterned resists to processes exposed portions of the substrate804differently from those portions covered by the first resist804and second resist1102. For example, the fabrication process may include an ion implantation process to form a junction isolation structure1402in the substrate804, other ion implantation processes, etching processes, deposition processes, epitaxy processes, and/or other suitable processes.

Referring to block720ofFIG. 7A, any remaining portion of the first resist804, the second resist1102, and/or the first dielectric material1002is removed. This may be performed substantially as described in block114ofFIG. 1. These materials may be removed by any suitable etching and/or stripping technique such as dry etching, wet etching, and/or other etching methods.

As the process of blocks704-720may be performed on stripes of the substrate804running in the first direction902, in some embodiments, the processes are then repeated in a second direction1504perpendicular to the first. Referring to block722ofFIG. 7Band toFIGS. 15A and 15B, a third resist1506is applied to the substrate. This may be performed substantially as described in block704ofFIG. 7A, and the third resist1506may be substantially similar to the first resist804and/or the second resist1102. In various examples, the third resist1506includes a photoresist material, an e-beam resist material, and/or other suitable resist material and is applied using by spin coating or other suitable technique.

Referring to block724ofFIG. 7B, a lithographic exposure is performed on the workpiece800that exposes selected regions of the third resist1506to radiation, and referring to block726ofFIG. 7Band toFIGS. 16A and 16B, a developing process is performed on the workpiece800. This may be performed substantially as described in blocks706and708, respectively. The developing process may begin with a post-exposure bake. Following the post-exposure bake, a developer is applied to the workpiece800. The developer dissolves or otherwise removes either the exposed regions of the third resist1506in the case of a positive resist development process or the unexposed regions of the third resist1506in the case of a negative resist development process. After the developer is applied to the workpiece800, the patterned third resist1506may be rinsed, and a hard bake may be performed on the workpiece800to further stabilize the pattern of the resist1506.

The pattern of the third resist1506after developing may have any suitable shape and structure. In some embodiments, the pattern is governed by the stability of the third resist1506, by limitations of a lithographic system used to pattern the third resist1506, by the fabrication process to be performed using the patterned third resist1506, and/or by other factors. In some examples, the patterned resist includes sets of substantially parallel features of the third resist1506extending in a second direction1504substantially perpendicular to the previous features of the first resist804.

Referring to block728ofFIG. 7Band toFIGS. 17A and 17B, a second dielectric material1702is deposited on the developed third resist1506and particularly on the side surfaces of the resist1506. This may be performed substantially as described in block710ofFIG. 7A. The second dielectric material1702may be substantially similar to the first dielectric material1002and may include a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and/or other suitable insulator materials. The second dielectric material1702may be selected to have a different etchant sensitivity than the third resist1506and may be formed to any suitable thickness. In some examples, the second dielectric material1702includes silicon oxide and is formed to a thickness1704of between about 20 nm and about 50 nm.

The second dielectric material1702may be deposited by any suitable technique or combination of techniques such as CECVD and/or PECVD. In some examples, the second dielectric material1702is deposited at a temperature between about 50° C. and about 100° C. or between about room temperature (˜20° C.) and about 100° C. These ranges have been determined to be sufficiently warm to promote deposition of the second dielectric material1702without risk of deforming the third resist1506. In contrast, deposition temperatures below these ranges may not allow proper deposition, and deposition temperatures above these ranges may cause the third resist1506to deform.

Referring to block730ofFIG. 7Band toFIGS. 18A and 18B, a fourth resist1802is deposited on the third resist1506and the second dielectric material1702. The fourth resist1802may be substantially similar to the third resist1506and may include a photoresist material, an e-beam resist material, and/or other suitable resist material. Alternately, the fourth resist1802may be a lithographically inert dielectric (e.g., some spin-on dielectrics) or other suitable resist material. In some embodiments, the fourth resist1802is selected to have different etchant sensitivity than the second dielectric material1702.

The fourth resist1802may be applied by any suitable technique, such as spin coating, and may be cured using heat, radiation, e-beam exposure, and/or plasma exposure. In embodiments where the fourth resist1802includes a photoresist material, the fourth resist1802may be exposed using a flood exposure to stabilize the photosensitive components.

Referring to block732ofFIG. 7Band toFIGS. 19A and 19B, the fourth resist1802is planarized to expose the second dielectric material1702. This may be performed substantially as described in block714ofFIG. 7A, and in some examples, the fourth resist1802is planarized by a CMP process. In addition to the fourth resist1802, the CMP process may planarize the third resist1506and the second dielectric material1702. By exposing the second dielectric material1702, the planarization creates features of the third resist1506and features of the fourth resist1802separated by the second dielectric material1702.

The planarization of block732exposes the vertical channels of the second dielectric material1702, and referring to block734ofFIG. 7Band toFIGS. 20A and 20B, the vertical channels of the second dielectric material1702are selectively removed by an etching process such as dry etching, wet etching, and/or other etching methods. The etchant chemistries, temperature, duration, and other parameters may be configured to spare the third resist1506and the fourth resist1802from significant etching. The removal of the first dielectric material1002leaves trenches2002extending in the second direction1504between the third resist1506and the fourth resist1802. The trenches2002formed by the removal of the second dielectric material1702may be significantly narrower than those formed using resist material(s) alone, and in some embodiments, the ratio of trench height to trench width exceeds 50.

Referring to block736ofFIG. 7Band toFIGS. 21A and 22B, a fabrication process is performed on the workpiece800. This may be performed substantially as described in block718ofFIG. 7A. The fabrication process may be any suitable process and may utilize the patterned resists to processes exposed portions of the substrate804differently from those portions covered by the third resist1506and fourth resist1802. For example, the fabrication process may include an ion implantation process to further form a junction isolation structure1402in the substrate804, other ion implantation processes, etching processes, deposition processes, epitaxy processes, and/or other suitable processes.

Referring to block738ofFIG. 7Band toFIGS. 22A and 22B, any remaining portion of the third resist1506, the fourth resist1802, and/or the second dielectric material1702is removed. This may be performed substantially as described in block720ofFIG. 7. These materials may be removed by any suitable etching and/or stripping technique such as dry etching, wet etching, and/or other etching methods.

Referring to block740, the workpiece800is provided for further fabrication processes. For example, the workpiece800may be used to fabricate an image sensor, other integrated circuit chip, a system on a chip (SOC), and/or a portion thereof, and thus the subsequent fabrication processes may form various passive and active microelectronic devices such as sensors, resistors, capacitors, inductors, diodes, metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), laterally diffused MOS (LDMOS) transistors, high power MOS transistors, other types of transistors, and/or other circuit elements.

Thus, the present disclosure provides examples of forming a pattern for integrated circuit fabrication. In some examples, a method includes receiving a substrate. A patterned resist is formed on the substrate and has a trench defined therein. A dielectric material is deposited on the patterned resist and within the trench such that the dielectric narrows a width of the trench to further define the trench. A fabrication process is performed on a region of the substrate underlying the trench defined by the dielectric. In some such examples, the fabrication process includes an ion-implantation process, and a thickness of the dielectric at a bottom of the trench permits the ion-implantation process to implant the region of the substrate through the dielectric. In some such examples, the ion-implantation process forms a junction isolation region within the substrate. In some such examples, the junction isolation region isolates a set of pixel regions of an image sensor. In some such examples, the depositing of the dielectric is performed at a temperature between about 20° C. and about 100° C. In some such examples, the depositing of the dielectric includes a technique from a group consisting of catalyst enhanced chemical vapor deposition and plasma enhanced chemical vapor deposition. In some such examples, the depositing of the dielectric is configured to deposit the dielectric substantially conformally within the trench. In some such examples, the trench having the narrowed width has a height-to-width ratio of greater than or equal to 13. In some such examples, the trench prior to the depositing of the dielectric has a height-to-width ratio of less than or equal to 10.

In further examples, a method includes receiving a substrate and depositing a resist material on the substrate. The resist material is patterned to form a first feature and a second feature with a trench disposed therebetween. A dielectric is deposited within the trench, and a fabrication process is performed on the substrate using the trench having the dielectric deposited therein. In some such examples, the fabrication process is performed on a first region of the substrate, and the resist and a first portion of the dielectric on a sidewall of the trench are configured to protect a second region of the substrate from the fabrication process. In some such examples, the fabrication process includes an ion-implantation process, and a second portion of the dielectric on a bottom of the trench above the first region of the substrate is configured to implant the first region of the substrate through the dielectric. In some such examples, the fabrication process includes an ion-implantation process, and the ion-implantation process forms a junction isolation region within the substrate. In some such examples, the junction isolation region isolates a set of pixel regions of an image sensor. In some such examples, the depositing of the dielectric is performed at a temperature between about 20° C. and about 100° C. In some such examples, the depositing of the dielectric includes a technique from a group consisting of catalyst enhanced chemical vapor deposition and plasma enhanced chemical vapor deposition. In some such examples, the trench after the depositing of the dielectric has a height-to-width ratio of greater than or equal to 13.

In yet further examples, a method includes receiving a substrate, and patterning a first resist on the substrate to form a first feature. A dielectric is deposited on a side surface of the first feature, and a second resist is deposited on the substrate to form a second feature separated from the first feature by the dielectric. The dielectric is selectively removed to form a trench between the first feature and the second feature, and the substrate exposed by the trench is selectively processed. In some such examples, the dielectric is a first dielectric, the trench is a first trench, and the first trench extends in a first direction. A third resist on the substrate is patterned to form a third feature. A second dielectric is deposited on a side surface of the third feature, and a fourth resist is deposited on the substrate to form a fourth feature separated from the third feature by the second dielectric. The second dielectric is selectively removed to form a second trench between the third feature and the fourth feature that extends in a second direction substantially perpendicular to the first direction. The substrate exposed by the second trench is selectively processed. In some such examples, the processing of the substrate exposed by the trench includes an ion implantation to form a junction isolation region within the substrate.