Semiconductor storage device

A semiconductor storage device according to one embodiment includes a memory cell. A first latch is selectively coupled to the memory cell. A first bus coupled to the first latch and a second latch. A first charger charges the first bus. A second bus transmits a signal of the same value both when first data is output and when second data is output from the first or second latch A second charger raises a voltage of the second bus from a first value to a second value. A controller whose input is coupled to the second bus controls the first charger to stop charging of the first bus based on the voltage of the second bus having reached the second value.

FIELD

Embodiments relate generally to a semiconductor storage device.

BACKGROUND

As a semiconductor storage device, for example, a NAND flash memory is known.

DETAILED DESCRIPTION

A semiconductor storage device, such as a NAND flash memory, includes, for example, a plurality of data latches. Each data latch temporarily stores data relating to a memory cell. Such data may be transferred from one data latch to another data latch.

The time that is needed for data transfer may vary among a plurality of semiconductor storage devices, or within one semiconductor storage device. Thus, the transfer time is set, for example, in accordance with a longest time of such variance. However, in a case in which the time required for actual transfer is relatively short, a useless wait time occurs.

A semiconductor storage device according to one embodiment includes a memory cell. A first latch is selectively coupled to the memory cell. A first bus coupled to the first latch and a second latch. A first charger charges the first bus. A second bus transmits a signal of the same value both when first data is output and when second data is output from the first or second latch A second charger raises a voltage of the second bus from a first value to a second value. A controller whose input is coupled to the second bus controls the first charger to stop charging of the first bus based on the voltage of the second bus having reached the second value.

Embodiments will be described hereinafter with reference to the accompanying drawings. In the drawings, the same parts are denoted by like reference numerals.

A semiconductor storage device according to the embodiment will be described below. The semiconductor storage device according to the embodiment is, for example, a NAND flash memory.

(1) Configuration Example of Semiconductor Storage Device.

Referring toFIG. 1, a description is given of a configuration example of a NAND flash memory1as the semiconductor storage device according to the embodiment.FIG. 1illustrates an example of functional blocks of the NAND flash memory1.

As illustrated inFIG. 1, the NAND flash memory1includes a memory cell array10, a row decoder19, a sense amplifier module11, a page buffer12, a column decoder13, a core driver14, a register15, an input/output circuit16, a voltage generation circuit (generator)17, and a control circuit (controller)18. The NAND flash memory1includes at least one set of the memory cell array10, sense amplifier module11and page buffer12. The NAND flash memory1may include a plurality of such sets.

The memory cell array10includes bit lines BL, source lines SL, and word lines WL. The bit lines BL and source lines SL extend in a column direction, and the word lines WL extend in a row direction. NAND strings, which are arranged in the row direction, are connected between respective bit lines BL and the source line SL. Each NAND string includes series-connected memory cell transistors MT, and a pair of select transistors ST which are connected in series to both ends of these memory cell transistors MT. The NAND strings are connected to the bit lines BL and the source line SL via the select transistors ST at the both ends. Each word line WL is connected to the gates of the memory cell transistors MT which are arranged in the row direction. A select gate line SG is connected to the gates of the select transistors ST which are arranged in the row direction. In the NAND flash memory1, the memory cell transistors MT function as memory cells.

A memory cell transistor MT includes, for example, a multilayer structure of a control gate electrode and a floating gate electrode. In this multilayer structure, an electric charge is injected in the floating gate electrode. The threshold of the memory cell transistor MT varies by the injected charge amount, and thereby the memory cell transistor MT stores single-level data or multi-level data. The memory cell transistor MT may include a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure in place of the above-described multilayer structure. In the MONOS structure, electrons are trapped in the nitride film.

The row decoder19selects one of the word lines at a time of write and read of data. In addition, the row decoder19applies necessary voltages to the selected word line WL and non-selected word lines WL.

The sense amplifier module11includes sense amplifier units SAU and a dummy unit DMU. The sense amplifier units SAU are provided in association with the bit lines BL. The dummy unit DMU does not correspond to any bit line BL and, for example, a smaller number of dummy units DMU than the number of sense amplifier units SALT are provided. During data read, the sense amplifier module11executes sense of data which was read out to the bit lines BL. During data write, the sense amplifier module11executes transfer of write data to the bit lines BL.

The page buffer12includes data latches XDL and a dummy latch XDLd. For example, the same number of data latches XDL as the number of the sense amplifier units SAU are provided. For example, the same number of dummy latches XDLd as the number of dummy units DMU are provided. The page buffer12temporarily stores read data and write data in a data unit called “page”.

The column decoder13selects one of the sense amplifier units SAU in transfer of write data and read data.

The voltage generator17generates voltages which are necessary for data write, data read, data transfer which is involved in these operations, and data erase, for example, in response to an instruction of the controller18. The voltage generator17supplies generated voltages to the core driver14.

For example, responding to an instruction of the controller18, the core driver14supplies necessary voltages, among the voltages supplied from the voltage generator17, to the row decoder19, sense amplifier module11and page buffer12. The voltages supplied from the core driver14are transferred to the word lines WL by the row decoder19, and are applied to the bit lines BL by the sense amplifier module11. The voltage supplied from the core driver14is also used for data transfer by the page buffer12.

The input/output circuit16controls input/output of signals from/to a controller or a host device, which accesses the NAND flash memory1.

The register15stores commands, addresses, etc. which are received from the memory controller or host device. In addition, the register15transfers, for example, row addresses to the row decoder19, and column addresses to the column decoder13.

The controller18controls the operation of the entirety of the NAND flash memory1in accordance with commands received from the memory controller or host device. Various signals in the description below are generated, for example, by the controller18.

(2) Configuration Example of Sense Amplifier Module and Page Buffer

Referring toFIG. 2toFIG. 5, a description is given of a configuration example of the sense amplifier module11and page buffer12of the NAND flash memory1.

FIG. 2illustrates an example of functional blocks of the sense amplifier module11and page buffer12.

As illustrated inFIG. 2, the sense amplifier module11includes sense amplifier units SAU and dummy units DMU. The page buffer12includes data latches XDL and dummy latches XDLd. The numbers of these components SAU, DMU, XDL and XDLd, which will be described below, are merely examples, and are not limited to these examples.

A sense amplifier unit SAU is provided in association with each bit line BL, and senses data which was read out to the associated bit line BL. In addition, a sense amplifier unit SAU transfers write data to the associated bit line BL. For example, a set of sixteen sense amplifier units SAU is arranged in one column along the bit lines BL (sense amplifier units SAU0to SAU15).

A data latch XDL is provided in association with each bit line BL, and temporarily stores data relating to the associated bit line BL. The data latches XDL are used for input/output of data from/to the sense amplifier units SAU, and enable a cache operation of the NAND flash memory1. For example, a set of sixteen data latches XDL is arranged in one column such that the set of 16 data latches XDL is continuous on a column with the sixteen sense amplifier units SAU that are arranged in one column (data latches XDL0to XDL15).

A dummy unit DMU includes a configuration corresponding to a sense amplifier unit SAU. Specifically, for example, a set of sixteen dummy units DMU is arranged near the sense amplifier units SAU, in juxtaposition with the column of the sense amplifier units SAU (dummy units DMU0to DMU15). However, the dummy units DMU are not associated with the bit lines BL, and handle pseudo-data.

A dummy latch XDLd includes a configuration corresponding to a data latch XDL. Specifically, for example, a set of sixteen dummy latches XDLd is arranged near the data latches XDL, in juxtaposition with the column of the data latches XDL (dummy latches XDLd0to XDLd15). However, the dummy latches XDLd are not associated with the bit lines BL, and temporarily store pseudo-data.

For example, one column of dummy units DMU and dummy latches XDLd is provided for a plurality of columns of sense amplifier units SAU and data latches XDL.

Referring toFIG. 3, a description is given of a more detailed configuration example of the sense amplifier units SAU and data laches XDL.FIG. 3illustrates a state in which the sense amplifier units SAU and data laches XDL are arranged in one column.

As illustrated inFIG. 3, each of the sense amplifier units SAU includes a sense amplifier SA and, for example, three data latches SDL, UDL and LDL. In a sense amplifier unit SAU, it is the sense amplifier SA that relates to the control of potential of the bit line BL. Specifically, as described above, the sense amplifier SA senses the bit line BL, or applies a voltage to the bit line BL. The data latch SDL, UDL and LDL temporarily store data. In data write, the potential of the bit line BL is varied by the sense amplifier SA, for example, in accordance with the data which is stored by the data latch SDL. The other data latches UDL and LDL are used as a cache, for example, in executing a multi-level operation in which each memory cell transistor MT stores data of two bits or more, or in executing an arithmetic process on read data or write data.

In each sense amplifier unit SAU, the sense amplifier SA, and data latches SDL, UDL and LDL are mutually connected by a bus LBUS. In the example ofFIG. 3, the bus LBUS is disposed in a manner to cross two sense amplifier units SAU, which neighbor in a bit line BL direction, in a direction along the bit line BL.

The sense amplifier units SAU and the data latches XDL are connected by a bus DBUS. In the example ofFIG. 3, sixteen sense amplifier units SAU, which are arranged in one column, and sixteen data latches XDL, which are arranged in one column, share one bus DBUS. This enables data transmission and reception between a sense amplifier unit SAUx (x: an integer of 0 to 15) and a data latch XDLx corresponding to the sense amplifier unit SAUx. To the bus DEUS, a voltage controller24is connected.

The voltage controller24includes a precharge circuit (precharger)20and a discharge circuit (discharger)22.

The precharger20precharges the bus DBUS. The precharger20includes a transistor21. The transistor21is, for example, a p-channel MOS transistor. One end of the current path of the transistor21is connected to the bus DBUS, the other end of the current path is connected to a node of a power supply voltage VDD, and the gate of the transistor21receives a signal DPCn.

The discharger22discharges the bus DBUS. The discharger22includes a transistor23. The transistor23is, for example, an n-channel MOS transistor. One end of the current path of the transistor23is connected to the bus DBUS, the other end of the current path is connected to a node of a ground voltage VSS, and the gate of the transistor23receives a signal DDS.

The voltage value of the bus DBUS varies between a voltage value of “H” level, which is indicative of a charged state, and a voltage value of “L” level, which is indicative of a discharged state. The voltage value of the bus DBUS varies, for example, in accordance with precharge by the precharger20, and discharge by the discharger22. In addition, the voltage value of the bus DBUS varies in accordance with data transfer between the sense amplifier unit SAU and data latch XDL.

With the sense amplifier units SAU, data latches XDL, voltage controller24and bus DBUS, data is written, read out, or subjected to an arithmetic process. Specifically, the set of sense amplifier SA, data latches SDL, UDL, LDL and XDL, precharger20, discharger22and bus DBUS is configured as a data processing circuit2which processes data.

Referring toFIG. 4, a description is given of a more detailed configuration example of the dummy units DMU and dummy latches XDLd.FIG. 4illustrates a view in which the dummy units DMU and dummy latches XDLd are arranged in one column.

As illustrated inFIG. 4, each of the dummy units DMU includes, for example, three dummy latches SDLd, UDLd and LDLd. In the dummy unit DMU, no structure corresponding to the sense amplifier SA of the sense amplifier unit SAU is provided. Alternatively, the dummy unit DMU may include a structure which is not involved in the variation in potential of the bit line BL, that is, a dummy structure like a sense amplifier, which is not connected to the bit line BL. Accordingly, the dummy latches SDLd, UDLd, and LDLd are also a dummy structure which does not include a function as the ordinary data latches SDL, UDL, and LDL. The dummy latches SDLd, UDLd, and LDLd temporarily store pseudo-data, and not real data such as so-called user data.

In each dummy unit DMU, the dummy latches SDLd, UDLd and LDLd are mutually connected by a bus LBUSd. In the example ofFIG. 4, the bus LBUSd is disposed in a manner to cross two dummy units DMU in the direction along the sense amplifier unit SAU column, the two dummy units DMU neighboring in the direction along the sense amplifier unit SAU column.

The dummy units DMU and the dummy latches XDLd are connected by a bus DBUSd. In the example ofFIG. 4, sixteen dummy units DMU, which are arranged in one column, and sixteen dummy latches XDLd, which are arranged in one column, share one bus DBUSd. This enables data transmission and reception between a dummy unit DMUy (y: an integer of 0˜15) and a dummy latch XDLdy corresponding to the dummy unit DMUy. However, the data which is handled by the dummy latch XDLd is not real data, but pseudo-data. To the bus DBUSd, a voltage controller24dand a charge and discharge detection circuit (detector)30are connected. The charge and discharge detector30is included in the controller18. Specifically, at least a part of the controller18functions as the charge and discharge detector30.

The voltage controller24dincludes a precharger20dand a discharger22d.

The precharger20dprecharges the bus DBUSd. The precharger20dincludes a transistor21d. The transistor21dis, for example, a p-channel MOS transistor. One end of the current path of the transistor21dis connected to the bus DBUSd, the other end of the current path is connected to a node of a power supply voltage VDD, and the gate of the transistor21dreceives a signal dDPCn. In this manner, the transistor21dof the precharger20dis controlled by the signal dDPCn, which is different from the signal by which the transistor21of the precharger20in the data processing circuit2is controlled.

The discharger22ddischarges the bus DBUSd. The discharger22dincludes a transistor23d. The transistor23dis, for example, an n-channel MOS transistor. One end of the current path of the transistor23dis connected to the bus DBUSd, the other end of the current path is connected to a node of a ground voltage VSS, and the gate of the transistor23dreceives a signal dDDS. In this manner, the transistor23dof the discharger22dis controlled by the signal dDDS, which is different from the signal by which the transistor23of the discharger22in the data processing circuit2is controlled.

The voltage value of the bus DBUSd varies between a voltage value of “H” level, which is indicative of a charged state, and a voltage value of “L” level, which is indicative of a discharged state. The voltage value of the bus DBUSd varies, for example, in accordance with precharge by the precharger20d, and discharge by the discharger22d. In addition, the voltage value of the bus DBUSd varies in accordance with data transfer between the dummy unit DMU and dummy latch XDLd.

The charge and discharge detector30detects the voltage value of the bus DBUSd, and sends the detection result to the core driver14. The core driver14sends to the above-described data processing circuit2signals DPCn, LTL and XTL based on the detection result of the charge and discharge detector30. In accordance with the states of these signals DPCn, LTL and XTL, the timings of precharge, discharge and of the bus DBUS and data transfer in the data processing circuit2are controlled.

With the dummy units DMU, dummy latches XDLd, voltage controller24dand bus DBUSd, pseudo-data is temporarily stored, or is transferred between the dummy latches SDLd, UDLd, LDLd and XDLd. In this manner, the dummy latches SDLd, UDLd, LDLd and XDLd, precharger20d, discharger22dand bus DBUSd are configured as a dummy circuit2dincluding a configuration corresponding to the data processing circuit2. The charge and discharge detector30may be included in the dummy circuit2d. For example, one dummy circuit2dis provided for a plurality of data processing circuits2.

As described above, the dummy circuit2dis disposed, for example, near the data processing circuit2. The components included in the dummy circuit2d, such as the dummy latches SDLd, UDLd, LDLd and XDLd, voltage controller24dand bus DBUSd, include substantially the same configurations as the corresponding components in the data processing circuit2, such as the data latches SDL, UDL, LDL and XDL, voltage controller24and bus DBUS, and these components are formed, for example, in the same process steps.

The operations of the dummy circuit2d, such as precharge, discharge and data transfer, are executed, for example, in interlock with the similar operations of the data processing circuit2. In these operations, the charge and discharge detector30detects the voltage value of the bus DBUSd, and feeds the detection result back to the data processing circuit2.

Referring toFIG. 5, a more detailed configuration example of the charge and discharge detector30is described.FIG. 5illustrates a detailed example of the charge and discharge detector30together with peripheral circuits thereof.

InFIG. 5, data latches LDL0, LDL11, XDL0and XDL11are illustrated as representatives of data latches SDL, UDL, LDL and XDL. However, the data latches XDL0and XDL11are depicted as one data latch.

The data latch LDL0belongs to the sense amplifier unit SAU0. The data latch LDL11belongs to the sense amplifier unit SAU11. The data latch XDL0executes data input and output to and from the data latch LDL0. The data latch XDL11executes data input and output to and from the data latch LDL11.

Each of the data latches LDL0, LDL11, XDL0and XDL11includes a configuration in which, for example, two inverters INV1and INV2are combined. An input of the inverter INV1is connected to an output of the inverter INV2. An output of the inverter INV1is connected to an input of the inverter INV2. In addition, the input of the inverter INV1and the output of the inverter INV2are connected to the bus DBUS. When data is stored in one of the data latches LDL0, LDL11, XDL0and XDL11, this data is stored as a potential at a node between the input of the inverter INV1and the output of the inverter INV2.

The data latch LDL0is connected to the bus DBUS via a transistor LGT0. The gate of the transistor LGT0receives a signal LTL0. The data latch LDL11is connected to the bus DBUS via a transistor LGT11. The gate of the transistor LGT11receives a signal LTL11. The data latch XDL0is connected to the bus DBUS via a transistor XGT0. The gate of the transistor XGT0receives a signal XTL0. The data latch XDL11is connected to the bus DBUS via a transistor XGT11. The gate of the transistor XGT11receives a signal XTL11. Each of the transistors LGT0, LGT11, XGT0and XGT11is, for example, an n-channel MOS transistor.

These transistors LGT0, LGT11, XGT0and XGT11function as gates for data transfer (data transfer transistors). When the transistors of data latches of a transfer source and a transfer destination are turned on, data is transferred via the bus DBUS. In this manner, each data latch is selectively connected to the bus DBUS by turn-on and turn-off of the data transfer transistor which the data latch includes.

The dummy latch LDLd0belongs to the dummy unit DMU0. The dummy latch LDLd11belongs to the dummy unit DMU11. The dummy latch XDLd0executes data input/output for the dummy latch LDLd0. The dummy latch XDLd11executes data input/output for the dummy latch LDLd11.

Each of the dummy latches LDLd0, LDLd11, XDLd0and XDLd11includes a configuration in which, for example, two inverters INV1and INV2are combined.

The dummy latch LDLd0is connected to the bus DBUSd via a transistor LGTd0. The gate of the transistor LGTd0receives a signal LTLd0. The dummy latch LDLd11is connected to the bus DBUS via a transistor LGTd11. The gate of the transistor LGTd11receives a signal LTLd11. The dummy latch XDLd0is connected to the bus DBUSd via a transistor XGTd0. The gate of the transistor XGTd0receives a signal XTLd0. The dummy latch XDLd11is connected to the bus DBUSd via a transistor XGTd11. The gate of the transistor XGTd11receives a signal XDLd11. In this manner, the transistors LGTd0, LGTd11, XGTd0and XGTd11are controlled by the signals LTLd0, LTLd11, XTLd0and XTLd11, which are different from the signals by which the transistors LGT0, LGT11, XGT0and XGT11of the data processing circuit2are controlled. Each of the transistors LGTd0, LGTd11, XGTd0and XGTd11is, for example, an n-channel MOS transistor.

These transistors LGTd0, LGTd11, XGTd0and XGTd11function as gates for data transfer (data transfer transistors). Each dummy latch is selectively connected to the bus DBUSd by turn-on and turn-off of the data transfer transistor which the dummy latch includes.

All of the data latches SDL, UDL, LDL and XDL and dummy latches SDLd, UDLd, LDLd and XDLd, including those not illustrated inFIG. 5, have the same configurations as described above.

The charge and discharge detector30includes an inverter INV3and a logic circuit LGC. The charge and discharge detector30is included, for example, in the controller18although it is not always necessary that the inverter INV3be included in the controller18. For example, the inverter INV3may be provided anywhere between the controller18and page buffer12.

Signals from the charge and discharge detector30, which will be described below, are processed by the core driver14, and are distributed to the sense amplifier module11and page buffer12. As components for executing such functions, the core driver14includes buffers BFP, BFLx and BFXx (x: an integer of 0˜15). In this manner, the same number of buffers BFL, BFX, as the number of data latches LDL, XDL, that is, sixteen buffers BFL and sixteen buffers BFX, are prepared in the example of the present embodiment. Incidentally, as regards the data latches SDL and UDL not illustrated inFIG. 5, too, the same number of corresponding buffers as the number of these data laches are prepared.

An input of the inverter INV3is connected to the bus DBUSd. Based on the voltage value of the bus DBUSd, the inverter INV3outputs a signal DBUS_MON to the logic circuit LGC. Based on the signal DBUS_MON, the logic circuit LGC outputs signals DPCn_PRE, LTL_PREx and XTL_PREx to the buffers BFP, BFLx and BFXx. The logic circuit LGC is a circuit which generates and outputs DPCn_PRE, LTL_PREx and XTL_PREx of certain states (“L” level or “H” level) in accordance with the state (“L” level or “H” level) of the signal DBUS_MON.

The signal DPCn_PRE is output to the buffer BFP. The buffer BFP amplifies the signal DPCn_PRE and generates a signal DPCn. The signal DPCn is output to the transistor21of the precharger20. The signal DPCn_PRE, DPCn is in “L” level when the signal DBUS_MON is in “H” level, and turns on the transistor21. The signal DPCn_PRE, DPCn is in “H” level when the signal DBUS_MON is in “L” level, and turns off the transistor21.

The signal LTL_PREx is output to the corresponding buffer BFLx. The buffer BFLx amplifies the signal LTL_PREx and generates a signal LTLx. The signal LTLx is output to the transistor LGTx of the data latch LDLx of the operation target. The signal LTL_PREx and LTLx are in “H” level when the signal DBUS_MON is in “L” level, and turn on the transistor LGTx of the corresponding data latch LDLx. The signal LTL_PREx and LTLx are in “L” level when the signal DBUS_MON is in “H” level, and turn off the transistor LGTx of the corresponding data latch LDLx. As regards the data latches SDL, UDL, which are not illustrated inFIG. 5, signals corresponding to these signals LTL_PREx, LTLx are prepared.

The signal XTL_PREx is output to the corresponding buffer BFXx. The buffer BFXx amplifies the signal XTL_PREx and generates a signal XTLx. The signal XTLx is output to the transistor XGTx of the data latch XDLx of the operation target. The signal XTL_PREx and XTLx are in “H” level when the signal DBUS_MON is in “L” level, and turn on the transistor XGTx of the corresponding data latch XDLx. The signal XTL_PREx and XTLx are in “L” level when the signal DBUS_MON is in “H” level, and turn off the transistor XGTx of the corresponding data latch XDLx.

(3) Operation Example of Sense Amplifier Module and Page Buffer

[Operation Example of Data Transfer]

Now, referring toFIG. 5and alsoFIGS. 6 and 7, a description is given of an operation example of data transfer between the sense amplifier module11and page buffer12.

Data transfer between the sense amplifier module11and page buffer12is executed, for example, between data latches LDLx and XDLx (x: an integer of 0˜15). Data to be transferred is, for example, either “0” data or “1” data.

“0” data is stored in the data latch LDL and XDL, for example, as a voltage (potential) of “L” level. When “0” data is output to the bus DBUS of “H” level, the bus DBUS changes to “L” level. “1” data is stored in the data latch LDL and XDL, for example, as a voltage (potential) of “H” level. When “1” data is output to the bus DBUS of “H” level, the bus DBUS keeps “H” level.

In the present embodiment, in data transfer between the data latches LDLx and XDLx, data transfer is also executed between, for example, dummy latches LDLdy and XDLdy (y: an integer of 0˜15, which is identical to or different from x). Between the dummy latches LDLdy and XDLdy, for example, “0” data is transferred, regardless of data that is transferred between the data latches LDLx and XDLx. Also in the dummy latches LDLd and XDLd, “0” data is stored, for example, as a voltage (potential) of “L” level. By the output of “0” data, the bus DBUSd of “H” level changes to “L” level. The operation between the dummy latches LDLdy and XDLdy is fed back to the operation between the data latches LDLx and XDLx by the charge and discharge detector30.

Hereinafter, a description is given of an example of the case in which “0” data is transferred from the data latch LDLx to the data latch XDLx. In addition, it is assumed that the data latch XDLx stores “1” data at a time of the start of data transfer.

To begin with, referring toFIG. 6, an operation of data transfer between the data latches LDLx and XDLx is described.FIG. 6illustrates an example of a flowchart of a data transfer method in the NAND flash memory1.

As illustrated inFIG. 6, at a time of starting data transfer, the transistor21of the precharger20is first turned on, and the bus DBUS is precharged (step S10). Thereby, the bus DBUS goes to “H” level. Next, the gate of the data latch LDLx of the transfer source and the gate of the data latch XDLx of the transfer destination are opened. Specifically, the transistors LGTx and XGTx are turned on (step S20). Thereby, “0” data of the data latch LDLx is output to the bus DBUS, and the bus DBUS and data latch XDLx are discharged. Specifically, the bus DBUS changes to “L” level, and a voltage of “L” level is stored in the data latch XDLx (step S30). In the meantime, as regards the data latch XDLx, when “1” data was originally stored in the data latch XDLx, a voltage of “H” level is discharged, and when “0” data was originally stored, a voltage of “L” level is maintained. Thereafter, the gates of the gate latches LDLx and XDLx are closed (step S40).

By the above, the transfer of “0” data from the data latch LDLx to the data latch XDLx is completed.

Based on the voltage value of the bus DBUSd of the dummy circuit2d, the charge and discharge detector30controls the timings (step S10) of the start and end of precharge of the bus DBUS. In addition, based on the voltage value of the bus DBUSd of the dummy circuit2d, the charge and discharge detector30controls the timings (step S20, S30) of the start of discharge and the end of discharge of the bus DBUS and data latch XDLx.

This operation timings of the components of the data processing circuit2, which are controlled by the charge and discharge detector30are illustrated inFIG. 7.FIG. 7illustrates an example of a timing chart of each of signals in data transfer of the NAND flash memory1.

As illustrated inFIG. 7, the controller18first supplies the signal dDPCn of “L” level to the gate of the transistor21dof the precharger20dto turn on the transistor21d, and starts precharge of the bus DBUSd of the dummy circuit2d. The controller keeps the signal dDPCn at “L” level for a period over which the bus DBUSd should be precharged. The charge and discharge detector30starts detection of the voltage value of the bus DBUSd.

At the time of the start of precharge, the bus DBUSd is, for example, in “L” level. Accordingly, a signal DBUS_MON of “H” level is input to the logic circuit LGC of the charge and discharge detector30. The logic circuit LGC outputs a signal DPCn_PRE of “L” level and a signal DPCn is produced from the signal DPCn_PRE while the logic circuit LGC is receiving the signal dDPCn of “L” level and the signal DBUS_MON of “H” level. The signal DPCn of “L” level is input to the gate of the transistor21of the precharger20. Thereby, the transistor21is turned on, and the precharge of the bus DBUS is started (time instant t1).

When the bus DBUSd goes to “H” level by the precharge (time instant t2), a signal DBUS_MON of “L” level is input to the logic circuit LGC. With the transition of the signal DBUS_MON to “L” level, the logic circuit LGC outputs a signal DPCn_PRE of “H” level, and a signal DPCn is produced from the signal DPCn_PRE. By the signal DPCn of “H” level, the transistor21is turned off with a little delay from time instant t2, and the precharge of the bus DBUS is completed (time instant t3). The signal dDPCn is made back “H” level based on the signal DBUS_MON having transitioned to “L” level.

In addition, when the bus DBUSd changes to “H” level and a signal DBUS_MON of “L” level is input, the logic circuit LGC outputs signals LTL_PREx and XTL_PREx of “H” level, and signals LTLx and XTLx are produced from these signals LTL_PREx and XTL_PREx. The signal LTLx of “H” level is input to the gate of the transistor LGTx of the data latch LDLx of the transfer source. The signal XTLx of “H” level is input to the gate of the transistor XGTx of the data latch XDLx of the transfer destination.

Thereby, the transistor LGTx is turned on, and discharge of the bus DBUS is started by “0” data which was output from the data latch LDLx to the bus DBUS (time instant t4). In addition, the transistor XGTx is turned on, and, with the discharge of the bus DBUS, discharge of the voltage stored in the data latch XDLx is started. The voltage stored in the data latch XDLx properly lowers after the voltage of the bus DBUS sufficiently lowered (time instant t5). Since the capacitance of the data latch XDLx is much smaller than the capacitance of the bus DBUS, the data latch XDLx changes to “L” level earlier than the bus DBUS.

On the other hand, at the timing of the start of discharge of the bus DBUS and data latch XDLx, the controller18starts discharge of the bus DBUSd and dummy latch XDLdy (time instant t4). Specifically, the controller18turns on the transistors LGTdy and XGTdty of the dummy latches LDLdy and XDLdy, and causes “0” data, which is stored in the dummy latch LDLdy, to be output (not illustrated). To this end, the controller18keeps the signals LTLd0and XTLd at “H” level while the controller18is receiving the signal dDPCn of “H” level and the signal DBUS_MON of “L” level.

By the above-described discharge, when the bus DBUSd changes to “L” level (time instant t6), a signal DBUS_MON of “H” level is input to the logic circuit LGC. The logic circuit LGC outputs signals LTL_PREx and XTL_PREx of “L” level, and signals LTLx and XTLx are produced from these signals LTL_PREx and XTL_PREx. Thereby, the transistors LGTx and XGTx are turned off, with a little delay from time instant t6, and the data transfer is completed (time instant t7).

Incidentally, the transfer of “0” data from the data latch XDLx to the data latch LDLx is executed, basically, by the same flow as inFIGS. 6 and 7, with only the transfer source and transfer destination being interchanged.

In the transfer of “1” data between the data latches LDLx and XDLx, in step S30inFIG. 6, data transfer is executed, with the bus DBUS being kept in “H” level, without the bus DBUS and the data latch *DLx (*=L, or X) of the transfer destination being discharged. In this case, too, as described above, “0” data is transferred in the dummy circuit2d. Thus, the charge and discharge detector30terminates the data transfer in the data processing circuit2, based on the fact that the bus DBUSd and the dummy latch *DLdy of the transfer destination were discharged and the bus DBUSd changed to “L” level.

The above description also applies to the data transfer between the data latches SDLx and XDLx and between the dummy latches SDLdy and XDLdy, and the data transfer between the data latches UDLx and XDLx and between the dummy latches UDLdy and XDLdy.

[Example of “0” Data Set Operation to Dummy Latch]

As described above, in data transfer between the data latches LDLx and XDLx, for example, “0” data is transferred from the dummy latch LDLd to the dummy latch XDLd. Accordingly, “0” data has to be stored in the dummy latch LDLd of the transfer source, prior to the data transfer between the data latches LDLx and XDLx. Thus, “0” data is set in advance in the dummy latch LDLd.

Hereinafter, referring toFIGS. 8 and 9, a description is given of an example of a set operation of “0” data to the dummy latch LDLd.

FIG. 8illustrates an example of a timing chart of each of signals in “0” data set in the dummy latch LDLd of the NAND flash memory1.FIG. 9schematically illustrates a state of the dummy latch LDLd and XDLd in “0” data set in the dummy latch LDLd of the NAND flash memory1.

As illustrated inFIGS. 8 and 9, the controller18outputs a signal dDDS of “H” level to the gate of the transistor23dof the discharger22d, and turns on the transistor23d. In addition, the controller18outputs a signal LDLd of “H” level to the gate of the transistor LGTd of the dummy latch LDLd, and turns on the transistor LGTd.

In this manner, by the transistor23dbeing turned on, the bus DBUSd is discharged. In accordance with this, the dummy latch LDLd is also discharged. Thus, “0” data is set in the dummy latch LDLd.

It should suffice if the set operation of “0” data to the dummy latch LDLd is, at the least, executed prior to the start of data transfer between the data latches LDL and XDL. Thus, the controller18executes the “0” data set operation in advance during a period in which data transfer is not executed, such as when the NAND flash memory1is in an idle state. The transistors23dand LGTd are controlled by the signals dDDS and LTLd, which are different from the signals by which the corresponding transistors23and LGT in the data processing circuit2are controlled. Therefore, the controller18can execute the above-described “0” data set operation, separately from the operation of the data processing circuit2.

In the meantime, although the above description has been given of the example in which the dummy latch LDLd is the transfer source, the embodiment is not limited to this example. For example, in the case in which the dummy latch XDLd is the transfer source, the controller18sets “0” data in the dummy latch XDLd by the same procedure as described above.

(4) Advantageous Effects of the Present Embodiment

According to the present embodiment, one or more of advantageous effects, which will be described below, can be obtained based on the following configuration (A) to configuration (G).

(A) According to the present embodiment, the NAND flash memory1includes the data processing circuit2and dummy circuit2d(and charge and discharge detector30).

(B) According to the present embodiment, for example, when data transfer is executed between the data latches LDL and XDL, the precharger20of voltage controller24and the precharger20dof voltage controller24dstart control such that the bus DBUS and DBUSd changes to “H” level.

(C) According to the present embodiment, in data transfer, when the charge and discharge detector30detects that the bus DBUSd has changed to “H” level, the precharger20of the voltage controller24stops control. To be more specific, the charge and discharge detector30transmits, as needed, a signal DPCn of “L” level or “H” level to the precharger20via the core driver14. Based on the signal DPCn, the precharger20executes control to set the bus DBUS at “H” level, or stops the control.

By the above configurations (A), (B) and (C), the time for which precharge of the bus DBUS is executed can be optimized.

This point is described with reference toFIGS. 10 and 11.FIG. 10illustrates an example of a timing chart of each of signals at a time of the start of data transfer of a NAND flash memory according to a comparative example.FIG. 10is based on comparison with a part ofFIG. 7which illustrates the present embodiment.FIG. 11illustrates a part ofFIG. 7.

As illustrated inFIG. 10, for example, the time for executing precharge is fixed in advance because the NAND flash memory of the comparative example does not include, for example, the dummy circuit2dand charge and discharge detector30. On the other hand, a variance may occur in line width of bus DBUScomp and characteristics of data transfer transistors of data latches LDLcomp and XDLcomp among NAND flash memories. Consequently, a variance may occur in time that is actually needed for precharge of the bus DBUScomp among NAND flash memories. In one NAND flash memory, too, a variance may occur in output voltage of the precharger due to the state of a power supply during operation, and a variance may occur in actual precharge time.

Thus, for example, as illustrated inFIG. 10, it is necessary to set the time of execution of precharge in accordance with a longest time of the variance in actual precharge time among the NAND flash memories and within the NAND flash memory. However, in many cases, the actual precharge time is shorter than the set time, and a useless wait time occurs. This wait time corresponds to, for example, a period of time instant t2to t3inFIG. 10.FIG. 10illustrates a state in which the period of time instant t2to t3is set to be longer.

In the present embodiment, in data transfer, the controller18interlocks the data processing circuit2and the dummy circuit2dwith each other. The data processing circuit2and dummy circuit2dare disposed near each other and have substantially the same configuration. Thus, the difference in line width of buses DBUS and DBUSd and the difference in characteristics of various transistors included in the data processing circuit2and dummy circuit2dare small. The influence from the power supply, etc. is also substantially equal between the data processing circuit2and dummy circuit2d.

From the above, the voltage value of the bus DBUSd corresponds to the voltage value of the bus DBUS. Specifically, for example, when the bus DBUSd has changed to “H” level, it can be determined that the bus DBUS has also changed to “H” level. To be more specific, based on the voltage value of the bus DBUSd, the time of execution of precharge of the bus DBUS can be adjusted. Accordingly, as illustrated inFIG. 11, by only providing a small margin (time instant t2to t3) to the operation time of the transistor21, the precharge execution time of the bus DBUS can be optimized to be a relatively close time to an actual necessary precharge time. Therefore, the useless time in the precharge of the bus DBUS can be reduced.

(D) According to the present embodiment, for example, when data transfer is executed between the data latches LDL and XDL, data is transferred between the dummy latches LDLd and XDLd in accordance with the change of the bus DBUSd to “L” level.

(E) According to the present embodiment, in the above data transfer, when the charge and discharge detector30has detected that the bus DBUSd changed to “L” level, the data transfer between the data latches LDL and XDL is completed. To be more specific, the charge and discharge detector30transmits, as needed, the signals LTL and XTL of “L” level or “H” level to the transistors LGT and XGT of the data latches LDL and XDL via the core driver14. The transistors LGT and XGT are turned on or turned off in accordance with the signals LTL and XTL.

By the above configurations (A), (D) and (E), the timing of the end of data transfer between the data latches LDL and XDL can be optimized.

This point is described with reference toFIGS. 12 and 13.FIG. 12illustrates an example of a timing chart of each of signals at a time of the end of data transfer of the NAND flash memory of the comparative example.FIG. 12is based on comparison with a part ofFIG. 7, which illustrates the present embodiment.FIG. 13illustrate a part ofFIG. 7. Hereinafter, to begin with, the problem of the NAND flash memory of the comparative example is described, and then, based on this, a description is given ofFIGS. 12 and 13.

In the comparative example, a variance may occur in timing of the end of data transfer, due to the above-described differences in the structures, characteristics and conditions at times of operations of the individual NAND flash memories. Specifically, a variance may occur in the necessary time until data is stored in the data latch *DLcomp (*=L, or X) of the transfer destination, after the end of precharge of the bus DBUScomp.

Thus, for example, as illustrated inFIG. 12, it is necessary to preset the time for which the transistor LGTcomp of data latch LDLcomp of the transfer source and the transistor XGTcomp of data latch XDLcomp of the transfer destination are ON, in accordance with the longest time of the variation of the time up to storage of data. However, in many cases, the actual time until storage of data is shorter than the set ON time of the transistors LGTcomp and XGTcomp, and a useless wait time occurs. This wait time corresponds to, for example, a period of time instant t6to t7inFIG. 12.FIG. 12illustrates a state in which the period of time instant t6to t7is set to be longer.

In the present embodiment, the controller18executes data transfer between the dummy latches LDLd and XDLd. The charge and discharge detector30adjusts the time for which the transistors LGT and XGT are ON, based on the voltage value of the bus DBUSd at this time. Thus, as illustrated inFIG. 13, by only providing a small margin (time instant t6to t7), the time for which the transistors LGT and XGT are ON can be optimized to be a relatively close time to an actual necessary time up to storage of data. Therefore, the useless time in the storage of data can be reduced.

(F) According to the present embodiment, when data is transferred between the data latches LDL and XDL, “0” data or “1” data is transferred. When data is transferred between the dummy latches LDLd and XDLd, “0” data is transferred.

By the above configuration (F), the charge and discharge detector30can terminate the data transfer between the data latches LDL and XDL, with a sufficient allowance being provided.

In the present embodiment, “0” data is transferred between the dummy latches LDLd and XDLd. “0” data is transferred by the discharge of the bus DBUSd. Thus, compared to the transfer of “1” data, in which the bus DBUSd is kept at “H” level, the transfer of “0” data, which requires discharge of the bus DBUSd, takes a longer time. Thus, no matter which data is transferred between the data latches LDL and XDL, it can be determined that the data transfer between the data latches LDL and XDL was terminated, when the data transfer of “0” data between the dummy latches LDLd and XDLd was terminated. In this manner, since the end of data transfer between the data latches LDL and XDL is determined with reference to the data transfer which requires a longer time, a margin can be provided to the timing of the end of the data transfer.

By the above configuration (F), the charge and discharge detector30can determine whether the data transfer between the dummy latches LDLd and XDLd has been terminated, based on whether the bus DBUSd has changed to “L” level. Therefore, the charge and discharge detector30can easily determine the timing of the end of data transfer between the data latches LDL and XDL.

(G) According to the present embodiment, for example, when data is transferred between the data latches LDL and XDL, the discharger22dof the voltage controller24dchanges the bus DBUSd to “L” level, and “0” data is set in the dummy latch LDLd. Thereafter, “0” data is transferred from the dummy latch LDLd to the dummy latch XDLd.

By the above configuration (G), it is possible to realize the above-described configuration in which “0” data is transferred between the dummy latches LDLd and XDLd, when data is transferred between the data latches LDL and XDL.

(5) Modification According to the Embodiment

A modification according to the present embodiment is described with reference toFIG. 14toFIG. 16.

[Operation Example of Data Transfer]

When data transfer between the dummy latches LDLdy and XDLdy is interlocked with data transfer between the data latches LDLx and XDLx, some methods are possible. They are a case in which the dummy latches LDLdy and XDLdy are selected such that x=y, and a case in which the dummy latches LDLdy and XDLdy are selected such that x≠y.

If a description is given with reference to the example ofFIG. 5, the case of x=y is such a case that, in data transfer between the data latches LDL0and XDL0, data transfer is executed between the dummy latches LDLdy and XDLdy, and, in data transfer between the data latches LDL11and XDL11, data transfer is executed between the dummy latches LDLd11and XDLd11. Such selection of the dummy latches LDLdy and XDLdy is executed, for example, by the controller18. The positions of the dummy latches LDLd0and XDLd0on the bus DBUSd have a relation of correspondency to the positions of the data latches LDL0and XDL0on the bus DBUS. Specifically, the distance of the bus DBUSd between the dummy latches LDLd0and XDLd0is substantially equal to the distance of the bus DBUS between the data latches LDL0and XDL0. The same applies to the data latches LDL11and XDL11and the dummy latches LDLd11and XDLd11. In this manner, the case of x=y is the case in which the controller18interlocks the data latches LDLx and XDLx and the dummy latches LDLdy and XDLdy, which have mutually corresponding positions on the buses DBUS and DBUSd.

FIG. 14illustrates various signals in the case in which data transfer between the data latches LDL11and XDL11is executed subsequently to data transfer between the data latches LDL0and XDL0.

As illustrated inFIG. 14, in data transfer (time instant t11to t12) between the data latches LDL0and XDL0, the signals LTL0and XTL0to the transistors LGT0and XGT0are set at “H” level. In data transfer (time instant t13to t14) between the data latches LDL11and XDL11, the signals LTL11and XTL11to the transistors LGT11and XGT11are set at “H” level.

FIG. 15illustrates various signals in the case in which, in the operation ofFIG. 14, the controller18interlocks the dummy latches LDLdy and XDLdy in the case of x=y.

As illustrated inFIG. 15, the controller18executes such control that data transfer is executed between the dummy latches LDLd0and XDLd0in data transfer between the data latches LDL0and XDL0(time instant t11to t12). Specifically, the controller18sets the signals LTLd0and XTLd0to the transistors LGTd0and XGTd0at “H” level. The controller18executes such control that data transfer is executed between the dummy latches LDLd11and XTLd11in data transfer between the data latches LDL11and XDL11(time instant t13to t14). Specifically, the controller18sets the signals LTLd11and XTLd11to the transistors LGTd11and XGTd11at “H” level.

On the other hand, the case of x≠y is such a case that data transfer is executed, for example, between the same dummy latches LDLdy and XDLdy (y=fixed), even in data transfer between the data latches LDL0and XDL0, or in data transfer between the data latches LDL11and XDL11. Specifically, for example, the controller18selects the dummy latches LDLdy and XDLd0so that the distance of the bus DBUSd between the dummy latches LDLdy and XDLdy becomes longest. In this manner, the case of x≠y is the case in which the controller18interlocks the dummy latches LDLdy and XDLdy, between which the distance of the bus DBUSd is longest, with the data latches LDLx and XDLx.

FIG. 16illustrates various signals in the case in which, in the above-described operation ofFIG. 14, the controller18interlocks the dummy latches LDLdy and XDLdy in the case of x≠y.

As illustrated inFIG. 16, the controller18executes such control that data transfer is executed between the dummy latches LDLd0and XDLd0, both in data transfer between the data latches LDL0and XDL0and in data transfer between the data latches LDL11and XDL11(time instant t11to t12, and time instant t13to t14). Specifically, the controller18sets the signals LTLd0and XTLd0to the transistors LGTd0and XGTd0at “H” level, both in data transfer between the data latches LDL0and XDL0and in data transfer between the data latches LDL11and XDL11.

[Advantageous Effects of the Present Modification]

According to the present modification, one or more of advantageous effects, which will be described below, can be obtained in addition to the advantageous effects of the above-described embodiment.

(A) According to the present modification, when data transfer is executed between the data latches LDL0and XDL0, data transfer is executed between the dummy latches LDLd0and XDLd0. When data transfer is executed between the data latches LDL11and XDL11, data transfer is executed between the dummy latches LDLd11and XDLd11.

The necessary time for data transfer varies depending on the length of the distance of the bus DBUS between the data latches LDL and XDL, between which the data transfer is executed. For example, the longer the distance of the bus DBUS, the greater the capacitance of the bus DBUS over this length, and the longer the necessary time for data transfer.

In the present embodiment, the controller18interlocks the data latches LDLx and XDLx and the dummy latches LDLdy and XDLdy, which have mutually corresponding positions on the buses DBUS and DBUSd. Thereby, the actual data transfer time between the data latches LDLx and XDLx and the actual data transfer time between the dummy latches LDLdy and XDLdy tend to be more easily equalized. Therefore, the charge and discharge detector30can more exactly determine the timing of the end of data transfer between the data latches LDLx and XDLs.

(B) According to the present modification, when data transfer is executed between the data latches LDL0and XDL0and when data transfer is executed between the data latches LDL11and XDL11, data transfer is executed between the dummy latches LDLd0and XDLd0.

In this modification, the controller18interlocks the dummy latches LDLdy and XDLd0, between which the distance of the bus DBUSd is longest, with the data latches LDLx and XDLx. Thereby, even in any combination of the data latches LDLx and XDLx between which data transfer is executed, the actual data transfer time between the dummy latches LDLd0and XDLd0becomes equal to or longer than the actual data transfer time between the data latches LDLx and XDLx. Therefore, the charge and discharge detectort30can provide a sufficient allowance to the timing of the end of data transfer between the data latches LDL and XDL.

In the above-described embodiment and modification, the description has been given of the example in which the charge and discharge detector30controls both the timing of the end of precharge of the bus DBUS and the timing of the end of discharge of the bus DBUS and data latch XDLx. However, there is no restriction to this example. The charge and discharge detector30may control only either of them. In this case, too, if consideration is given to the data transfer as a whole, the total time can be optimized.

In the above-described embodiment and modification, the description has been given of the example in which the charge and discharge detector30includes the configuration as illustrated inFIG. 5. However, there is no restriction to this example. The charge and discharge detector may have any configuration as long as the detection result of the voltage value of the bus LBUSd can be fed back to the operations of the precharger20of the data processing circuit2and the data latches SDL, UDL, and LDL.

In the above-described embodiment and modification, the description has been given of the example in which the charge and discharge detector30is applied to the data transfer between the sense amplifier11and page buffer12. However, there is no restriction to this example. The charge and discharge detector may be applied to, for example, data transfer within the sense amplifier unit SAU. Each sense amplifier unit SAU includes, for example, a precharger which executes precharge of the bus LBUS. The dummy unit DMU may also be provided with a precharger which executes precharge of the bus LBUSd. Thereby, the charge and discharge detector may control the precharge time of the bus LBUS, based on the voltage value of the bus LBUSd. In addition, the charge and discharge detector may control the timing of the end of data transfer between the data latches SDL, UDL, and LDL, based on the voltage value of the bus LBUSd.

In the above-described embodiment and modification, the description has been given of the example in which the NAND flash memory1is a planar NAND. However, there is no restriction to this example. The NAND flash memory may be a three-dimensional NAND in which memory cells are arranged in a three-dimensional fashion.

In the above-described embodiment and modification, the description has been given of the example in which the semiconductor storage device is the NAND flash memory1. However, there is no restriction to this example. The semiconductor storage device may not be a flash memory, but may be, for example, some other DRAM (Dynamic Random Access Memory).