FORMING LINE END VIAS

An integrated circuit structure includes a metal line that has an upper surface defining a periphery; a dielectric spacer that is formed around the periphery of the upper surface of the metal line; and a metal via that contacts the metal line and the dielectric spacer adjacent to the periphery of the upper surface. A method for making a semiconductor structure includes depositing a spacer around the periphery of an upper surface of a metal line; and depositing a via onto the metal line, so that a part of the via overlaps the spacer.

BACKGROUND

The present invention relates to the electrical, electronic, and computer arts, and more specifically, to fabrication of integrated circuits.

In building an integrated circuit, especially at modern process nodes (components of very small size and spacing), it can be difficult to prevent inadvertent electrical connections that can arise from manufacturing process errors. One sort of electrical short that can occur is a line-to-line short when the tips of two metal lines touch in the back-end-of-line (BEOL) layers. To prevent such shorts, circuit designers impose a constraint (herein referred to as “tip to tip,” and marked in the accompanying drawings as “T2T”), which is a minimum permissible distance between line ends in a circuit's mechanical design. T2T limits how closely lines and components can be packed in an integrated circuit design.

One issue that can lead to violations of T2T constraints is that the alignment of vias to lines can be difficult to control. Sometimes vias do not perfectly line up with their intended locations in the design. In order to comply with the T2T constraint, despite the known variability of via location, another constraint (herein referred to as “via enclosure,” and marked in the accompanying drawings as “VE”) sets a minimum permissible offset from a line end inward (along the line) to a via position. Via enclosure can impact how many vias can be fit into a layer.

SUMMARY

Principles of the invention provide techniques for forming line end vias. In one aspect, an exemplary integrated circuit structure includes a metal line that has an upper surface defining a periphery; a dielectric spacer around the periphery of the upper surface of the metal line; and a metal via that contacts the metal line and the dielectric spacer adjacent to the periphery of the upper surface.

According to another aspect, an exemplary method for making a semiconductor structure includes depositing a spacer around the periphery of an upper surface of a metal line; and depositing a via onto the metal line, so that a part of the via overlaps the spacer.

In view of the foregoing, techniques of the present invention can provide substantial beneficial technical effects. For example, one or more embodiments provide one or more of:

Fabrication of line end vias without violating tip to tip constraint and without requiring via enclosure constraint.

Etch stop layer is confined only on metal line surface and inner surface of dielectric spacer.

Higher component density for same process node.

Some embodiments may not have these potential advantages and these potential advantages are not necessarily required of all embodiments. These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

DETAILED DESCRIPTION

In building an integrated circuit, especially at modern process nodes (components of very small size and spacing), it can be difficult to prevent inadvertent electrical connections that can arise from manufacturing process errors. One sort of electrical short that can occur is a line-to-line short when the tips of two metal lines touch in the back-end-of-line (BEOL) layers. To prevent such shorts, circuit designers impose a constraint (herein referred to as “tip to tip,” and marked in the accompanying drawings as “T2T”), which is a minimum permissible distance between line ends in a circuit's mechanical design. T2T limits how closely lines and components can be packed in an integrated circuit design.

One issue that can lead to violations of T2T constraints is that the alignment of vias to lines can be difficult to control. Sometimes, vias do not perfectly line up with their intended locations in the design. In order to comply with the T2T constraint, despite the known variability of via location, another constraint (herein referred to as “via enclosure,” and marked in the accompanying drawings as “VE”) sets a minimum permissible offset, from a line end, inward (along the line), to a via position. Via enclosure can impact how many vias can be fit into a layer.

FIG.1depicts a plan view of an array100of metal lines102,104,106,108,110,112and vias114,116,118. In the array100, the above-mentioned tip-to-tip constraint T2T is implemented in lines102,104,106,108, where the vias114and116do not overhang into the prescribed gaps between the lines. Via enclosure constraint VE is implemented in line104only, where via114is offset inward by the distance VE from the tip of line104. The T2T constraint is violated in lines110,112, where via118protrudes over the tip113of line112so that it is too close to line110. VE is violated in line108, where via116is right at the tip of line108rather than being offset inward from the tip by the appropriate distance VE. VE also is violated in line112, where via118actually overhangs the tip of the line toward line110. Violations of VE (and consequently, violations of T2T) can occur frequently when using photolithographic processes in modern process nodes, e.g., sub-20 nm technology nodes.

FIG.2throughFIG.4depict plan and section views of a structure200that comprises an array of lower level metal lines202,204,206,208,210,212, upper level lines214,216, and vias224,230,232, which are built on a substrate218with dielectric layers220and222separating the conductive components. The fabrication process for the structure200mitigates VE and T2T violations by providing dielectric spacers (e.g.,226,234,236) that surround the upper surfaces of lines210,202, and206, respectively, in order to isolate, from the adjoining lines, those portions of the respective vias224,230,232that would otherwise overhang the edges of the lines and infringe T2T when VE is violated. For example, inFIG.3, the spacer226“contains” the overhanging portion225of via224by providing additional isolation between the overhang225and the adjacent tip of the line204. An additional dielectric spacer238surrounds the top of line204.

As a relic of fabrication processes, further discussed below, an etch stop layer240covers the lines and inner surfaces of the spacers facing the lines, except where vias are present. A barrier metal layer and a liner metal layer, between the lines and the dielectric, are not shown for convenience of illustration; the skillful worker is familiar with those layers and with methods for their fabrication. Exemplary materials for the metal lines and vias include copper, aluminum, tungsten, ruthenium, and tantalum. Commonly used materials for the substrate include silicon and silicon-germanium alloys. Exemplary materials for the dielectric layers include silicon oxides, silicon nitrides, titanium oxides, titanium nitrides. Commonly used etch stop materials include silicon nitride, silicon carbide, silicon carbonitride, and the like. Exemplary materials for a diffusion barrier layer include, in one or more embodiments, tantalum nitride, titanium nitride, indium oxide, copper silicide, tungsten nitride.

FIG.5depicts a flow chart of steps in a process500for forming the structure200that is shown inFIG.2throughFIG.4, according to exemplary embodiments.FIG.6throughFIG.38depict plan and sectioned views of intermediate structures formed by selected steps ofFIG.5.

At502, form a precursor structure600(as shown inFIG.6throughFIG.8), by methods known to the skillful worker, in which lines202,204,206,208,210,212are metallized in low-k dielectric layer220on substrate218.

At504, form an intermediate structure900(as shown inFIG.9throughFIG.11) by recessing the metal lines. A metal/liner/barrier recess process is well known to the skillful worker. Exemplary materials for these layers, in one or more embodiments, include copper (Cu) metal with a cobalt (Co) barrier and a tantalum nitride (TaN) liner,

At506, form an intermediate structure1200(as shown inFIG.12throughFIG.14) by depositing the etch stop layer240. In one or more embodiments, the etch stop layer240may comprise aluminum oxide (AlOx), zirconium oxide (ZrOx), or hafnium oxide (HfOx), with a thickness of about 1 to about 5 nanometers (nm).

At508, form an intermediate structure1500(as shown inFIG.15throughFIG.17) by depositing a layer of sacrificial material1502, then planarizing. In one or more embodiments, the sacrificial material can be metal, semiconductor, or dielectric. An appropriate sacrificial material can be removed (at step516) selective to the low-k dielectric and spacer materials by a given etch process. For example, in one or more embodiments, the sacrificial material can be amorphous silicon germanium (SiGe) with between 0 to 100 percent germanium; silicon dioxide; titanium nitride; or tungsten.

At510, form an intermediate structure1800(as shown inFIG.18throughFIG.20) by removing exposed portions of the etch stop layer240. Etch stop layer removal can be done by a wet or dry etch process according to the material of the etch stop layer. Selective removal can be accomplished by the skillful worker. Step510can be combined with step508, i.e. the etch stop layer240can be removed during planarization by, for example, chemical-mechanical polishing.

At512, form an intermediate structure2100(as shown inFIG.21throughFIG.23) by recessing the low-k dielectric220. The sacrificial material1502protects the metal lines and the etch stop layer during recess process. A target depth of the recess process is, in one or more embodiments, close to the top surface of the recessed metal lines.

At514, form an intermediate structure2400(as shown inFIG.24throughFIG.26) by depositing spacers226,234,236,238as well as additional spacers (not shown) around the peripheries of upper surfaces of other lines. In one or more embodiments, a suitable spacer material comprises a nitride that has good etch selectivity to low-k dielectric. Exemplary suitable spacer materials include plain silicon nitride (SiN, dielectric constant about 7.5), silicon carbonitride (SiCN, dielectric constant about 4.8˜4.9), silicon borocarbonitride (SiBCN, dielectric constant about 3.7˜4.2), or silicon oxycarbonitride (SiOCN, dielectric constant about 2.8˜3.5). Advantageously, spacers with smaller dielectric constants will provide a smaller increase of parasitic capacitance between the lines, compared to spacers with larger dielectric constants.

At516, form an intermediate structure2700(as shown inFIG.27throughFIG.29) by removing the sacrificial material1502(last shown inFIG.26). The resultant structure has just the substrate218, lines202,204,206,208,210,212, dielectric220, spacers226,234,236,238, and etch stop240.

At518, form an intermediate structure3000(as shown inFIG.30throughFIG.32) by depositing the low-k interlayer dielectric222. The interlayer dielectric222provides support for subsequently forming a new layer of lines and vias.

At520, form an intermediate structure3300(as shown inFIG.33throughFIG.35) by etching trenches3302,3304and vias3306,3308,3310. Via etching stops on the etch stop layer240and on the spacers226,234,236,238. Assuming overlay error is 3 nm, as long as the spacer is thicker than 3 nm, the via contact edge will not be outside of the spacer. Therefore, the T2T rule will be complied with even if the via edge is outside of the line end. This enables compliance with T2T with a reduced or zero value for VE.

At522, form an intermediate structure3600(as shown inFIG.36throughFIG.38) by removing exposed portions of the etch stop layer240from the bottoms of the vias. For example, a wet removal process can be used that is selective between the etch stop layer240and the other materials.

At524, form the structure200(as shown inFIG.2throughFIG.4) by metallizing the trenches and vias. Metallization is a process that the skillful worker understands how to perform.

FIG.39throughFIG.41depict plan and section views of an array3900of lower level metal lines202,204,206,208,210,212, upper level metal lines214,216, and vias224,230,232, which are built on a substrate218with dielectric layers220and222separating the conductive components. Components inFIG.39throughFIG.41that are similar to those ofFIG.2are similarly numbered and are not described in detail below.

In the array3900, VE is violated without infringing T2T because spacers226,234,236surround the tops of lines210,202, and206, respectively, and isolate from the adjoining lines those portions225,231,233of the respective vias224,230,232that would otherwise violate T2T. An additional spacer238surrounds the top of line204. As relics of fabrication processes, further discussed below, an etch stop layer240covers the lines and inner surfaces of the spacers facing the lines, except where vias are present; and an etch stop layer3902underlies the spacers226,234,236,238. A barrier metal layer and a liner metal layer, between the lines and the dielectric, are not shown for convenience of illustration; the skillful worker is familiar with those layers and with methods for their fabrication.

FIG.42depicts a flow chart of steps in a process4200for forming the array of metal lines3900that is shown inFIG.39throughFIG.41, according to exemplary embodiments.FIG.43throughFIG.57depict plan and sectioned views of intermediate structures formed by selected steps ofFIG.42. Components inFIG.43throughFIG.57that are similar to those ofFIG.2are similarly numbered and are not described in detail below.

At4202, produce a preliminary structure4300(as shown inFIG.43throughFIG.45) that has a substrate218covered by a first low-k dielectric layer220, the etch stop layer3902, and a second dielectric layer4304. The skillful worker will appreciate methods and processes for producing such a structure.

At4204, form an intermediate structure4600(as shown inFIG.46throughFIG.48) by etching and metallizing lines202,204,206,208,210, and212. The intermediate structure4600differs from the structure600principally in the presence of the etch stop layer3902and the second dielectric layer4304.

At4206, form an intermediate structure4900(as shown inFIG.49throughFIG.51) by performing steps504,506,508,510,512on the intermediate structure4600, as will be apparent to the skillful worker.

At4208, form an intermediate structure5200(as shown inFIG.52throughFIG.54) by depositing spacers226,234,236,238and other spacers.

At4210, form an intermediate structure5500(as shown inFIG.55throughFIG.57) by removing portions of the etch stop layer3902that are exposed between the spacers.

Then at4212, complete the structure3900in a manner that will be apparent to the skillful worker, in view of steps516,518,520,522,524ofFIG.5.

Given the discussion thus far, it will be appreciated that, in general terms, an exemplary integrated circuit structure200, according to an aspect of the invention, includes a metal line202that has an upper surface defining a periphery; a dielectric spacer234around the periphery of the upper surface of the metal line; and a metal via230that contacts the metal line and the dielectric spacer adjacent to the periphery of the upper surface.

In one or more embodiments, the dielectric spacer extends laterally at least 3 nanometers outward from the periphery of the upper surface of the metal line. In one or more embodiments, a portion of the metal via overlies a portion of the dielectric spacer that is outward from the periphery of the upper surface of the metal line.

In one or more embodiments, the structure200also includes a second metal line204that is adjacent to the metal line202, and but for the portion of the dielectric spacer underlying the metal via, the metal via would violate a minimum distance between vias design constraint.

In one or more embodiments, the structure200also includes an etch stop layer240covering and contacting an upper surface of the metal line around where the via contacts the line. In one or more embodiments, the etch stop layer covers a part of the dielectric spacer around where the via contacts the line.

In one or more embodiments, the structure also includes an etch stop layer3902underlying and contacting a part of the dielectric spacer that protrudes beyond the periphery of the upper surface of the metal line.

In one or more embodiments, the dielectric spacer comprises a low-k silicon nitride. In one or more embodiments, the dielectric spacer has k less than 5. In one or more embodiments, the dielectric spacer comprises a silicon carbonitride. In one or more embodiments, the dielectric spacer comprises silicon oxycarbonitride (SiOCN).

In one or more embodiments, the dielectric spacer is located above the upper surface of the metal line.

According to another aspect, an exemplary method for making a semiconductor structure includes, at514, depositing a spacer around the periphery of an upper surface of a metal line; and, at524, depositing a via onto the metal line, so that a part of the via overlaps the spacer. In one or more embodiments, a part of the spacer overhangs outside the periphery of the metal line. In one or more embodiments, the part of the via that overlaps the spacer includes a portion that overlaps the part of the spacer that overhangs outside the periphery of the metal line.

In one or more embodiments, the method also includes, before depositing the spacer, preparing for the deposition of the spacer by: at504, recessing the metal line into a low-k dielectric layer; at506, depositing an etch stop layer that covers the metal line and the low-k dielectric layer; at508, filling a recessed portion of the etch stop layer with a sacrificial material, then planarizing to remove portions of the etch stop layer that are not covered by the sacrificial material; and, at512, forming a ledge for deposition of the spacer by recessing the low-k dielectric layer selective to the sacrificial material.

In one or more embodiments, the exemplary method also includes, after deposition of the spacer, then at516, removing the sacrificial material. In one or more embodiments, the exemplary method also includes, at518, filling with a further layer of low-k dielectric. In one or more embodiments, the method also includes, before depositing the via, etching the via into the further layer of low-k dielectric at520. In one or more embodiments, the etched via overlaps the spacer and the metal line.

Semiconductor device manufacturing includes various steps of device patterning processes. For example, the manufacturing of a semiconductor chip may start with, for example, a plurality of CAD (computer aided design) generated device patterns, which is then followed by effort to replicate these device patterns in a substrate. The replication process may involve the use of various exposing techniques and a variety of subtractive (etching) and/or additive (deposition) material processing procedures.

A number of different precursors may be used for the epitaxial deposition of the in situ doped semiconductor material. In some embodiments, the gas source for the deposition of an epitaxially formed in situ doped semiconductor material may include silicon (Si) deposited from silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, disilane and combinations thereof. In other examples, when the in situ doped semiconductor material includes germanium, a germanium gas source may be selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. Examples of other epitaxial growth processes that can be employed in growing semiconductor layers described herein include rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE).

By “in-situ” it is meant that the dopant that dictates the conductivity type of doped layer is introduced during the process step, for example epitaxial deposition, that forms the doped layer. The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown,” mean the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), in which the semiconductor material being grown (crystalline over layer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled, and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move about on the surface such that the depositing atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxially grown semiconductor material has substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed.

As used herein, the term “conductivity type” denotes a dopant region being p-type or n-type. As further used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing substrate, examples of p-type dopants, i.e., impurities include but are not limited to: boron, aluminum, gallium and indium. As used herein, “n-type” refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. Examples of n-type dopants, i.e., impurities in a silicon-containing substrate include but are not limited to antimony, arsenic and phosphorous.

As an exemplary subtractive process, in a photolithographic process, a layer of photo-resist material may first be applied on top of a substrate, and then be exposed selectively according to a pre-determined device pattern or patterns. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to certain solutions. The photo-resist may then be developed in a developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern or photo-mask. The photo-resist pattern or photo-mask may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.

There are numerous techniques used by those skilled in the art to remove material at various stages of creating a semiconductor structure. As used herein, these processes are referred to generically as “etching”. For example, etching includes techniques of wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (ME), which are all known techniques to remove select material(s) when forming a semiconductor structure. The Standard Clean1(SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. The SC2contains a strong acid such as hydrochloric acid and hydrogen peroxide. The techniques and application of etching is well understood by those skilled in the art and, as such, a more detailed description of such processes is not presented herein.

Although the overall fabrication method and the structures formed thereby are novel, certain individual processing steps required to implement the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to one having ordinary skill in the relevant arts given the teachings herein. Moreover, one or more of the processing steps and tooling used to fabricate semiconductor devices are also described in a number of readily available publications, including, for example: James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001 and P. H. Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, which are both hereby incorporated by reference herein. It is emphasized that while some individual processing steps are set forth herein, those steps are merely illustrative, and one skilled in the art may be familiar with several equally suitable alternatives that would be applicable.

It is to be appreciated that the various layers and/or regions shown in the accompanying figures may not be drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for ease of explanation. This does not imply that the semiconductor layer(s) not explicitly shown are omitted in the actual integrated circuit device.