Switching DC-DC converter and oscillator

A switching DC-DC converter includes: an output voltage detecting unit configured to detect a DC output voltage; an error amplifying unit configured to compare the detected output voltage and a reference voltage and configured to supply an amplified error signal between the detected output voltage and the reference voltage to the pulse width modulating unit; and a single oscillating unit connected to an output of the output voltage detecting unit and an output of the error amplifying unit and operable on a first oscillating mode and a second oscillation mode. The oscillating unit on the first oscillating mode controls a switching frequency of the power switch based on the detected output voltage. The oscillating unit on the second oscillating mode controls the switching frequency of the power switch based on the amplified error signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims priority from Japanese Patent Application No. 2007-275436 filed on Oct. 23, 2007, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates to a switching DC-DC converter (hereinafter referred to as a DC-DC converter) which has a overcurrent protection feature and generates an output voltage by the constant voltage control of changing the frequency according to a load condition.

2. Description of the Related Art

A DC-DC converter reduces an output voltage when the DC-DC converter enters an overcurrent operation due to an increase in a load current. When the output voltage has lowered greatly, the DC-DC converter lowers the switching frequency to prevent the overcurrent value from increasing. An example of the DC-DC converter is disclosed in JP-A-10-229674.

In order to improve the efficiency when the load is low, another DC-DC converter lowers the switching frequency, thereby reducing the loss of a power switch due to switching. An example of another DC-DC converter is disclosed in JP-A-9-98571.

BRIEF SUMMARY OF THE INVENTION

The above DC-DC converters respectively include dedicated circuits to perform the above respective two features. Therefore, in order to realize a combination of the former and the latter of the above features, different control circuits corresponding to both features are required and the outputs from the control circuits must be unified into a single output. This requires a complicate circuit for selecting a lower one of two oscillating frequencies.

Further, in order that a single oscillator is provided to have the above respective features, since both oscillation frequencies are changed by different methods, it is difficult to combine these features as they are. Therefore, the circuit is more complicate than only the addition of both devices. Further, the above DC-DC converters do not serve both features. If an integrated circuit of semiconductor devices is formed, the above circuit is complicated, thereby increasing the chip area and leading to a cost increase.

In view of the above circumstance, an object of an aspect of the invention is to provide an DC-DC converter in a simple configuration at low cost, which can collectively control in a single circuit the operation common to the function of lowering the frequency during overcurrent control conditions and function of lowering the frequency during low load conditions, thus reducing the size of the control circuit and reducing the chip area in an integrated circuit of semiconductor devices thereby to make both functions compatible.

According to a first aspect of the invention, there is provided a switching DC-DC converter comprising: at least one power switch; a pulse width modulating unit configured to control on/off timing of the power switch; an inductor having one end connected to the power switch; a smoothing unit connected to the other end of the inductor and configured to produce a smoothed DC output voltage; an output voltage detecting unit configured to detect the DC output voltage; an error amplifying unit configured to compare the detected output voltage and a reference voltage and configured to supply an amplified error signal between the detected output voltage and the reference voltage to the pulse width modulating unit; and a single oscillating unit connected to an output of the output voltage detecting unit and an output of the error amplifying unit and operable on a first oscillating mode and a second oscillation mode, wherein the oscillating unit on the first oscillating mode controls a switching frequency of the power switch based on the detected output voltage, and wherein the oscillating unit on the second oscillating mode controls the switching frequency of the power switch based on the amplified error signal.

According to a second aspect of the invention, there is provided a switching DC-DC converter comprising: a switching transistor; an inductor having a first end and a second end, the first end being connected to an output of the switching transistor; a smoothing circuit connected to the second end of the inductor and configured to smooth an output voltage; a output voltage detecting unit configured to detect a voltage corresponding to the output voltage to output a detected voltage; an error amplifying unit configured to compare the detected voltage and a reference voltage to produce an error signal corresponding to a difference between the detected voltage and the reference voltage; a clamping unit configured to clamp an output of the error amplifying unit to a predetermined voltage; a first voltage-current converting unit connected to an output of the error amplifying unit; a low load detecting unit connected to the first voltage-current converting unit; a current sensing unit configured to sense a current flowing through the switching transistor; a second voltage-current converting unit connected to the current detecting unit; a current detecting unit configured to produce a signal corresponding to a value of the current flowing through the switching transistor; a pulse width modulating unit connected to the current detecting unit and configured to turn on or off the switching transistor; and an oscillating unit connected to the pulse width modulating unit, wherein an output from the low load detecting unit and a signal from the output voltage detecting unit are supplied to the oscillating unit, and wherein the switching transistor is switched based on a frequency of the oscillating unit.

According to a third aspect of the invention, there is provided an oscillator for use in a switching DC-DC converter, the oscillator comprising: an oscillating unit configured to generate a pulse signal; an selecting unit configured to select one of an output voltage of the DC-DC converter and an error signal corresponding to an error between the output voltage and a reference voltage; and a frequency control unit configured to compare the signal selected by the input selecting unit and a predetermined voltage to output a frequency setting signal to the oscillating unit, wherein a frequency of the pulse signal is controlled based on the frequency setting signal.

DETAILED DESCRIPTION OF THE EMBODIMENT

A DC-DC converter according to an embodiment of this invention will be described with reference to the drawings.

FIG. 1is a view showing the configuration of a DC-DC converter according to the embodiment of this invention.FIG. 2is a circuit block diagram of the interior of an oscillator.FIG. 3is a view showing the specific circuit configuration of the interior of an oscillator.FIGS. 4A and 4Bare timing charts for explaining the embodiment of invention.

First, referring toFIG. 1, an explanation will be given of the configuration of the DC-DC converter according to this embodiment. InFIG. 1, a power source voltage Vcc (hereinafter referred to as a power source voltage) serving as a DC input voltage is supplied through a first terminal P1to a control semiconductor integrated circuit12for the DC-DC converter. The power source voltage Vcc is turned on or off according to a base control current Ib by a switching transistor Q1and outputted from a second terminal P2. The switching transistor Q1is an NPN type bipolar transistor constituting a switching circuit. In this embodiment, as long as particularly not noted, the voltage is represented as a voltage relative to a ground potential. The output from the second terminal P2is smoothed by an energy storage coil L1, a smoothing capacitor C1and a Schottky barrier diode D1thereby supply an output voltage Vo and an output current Io to an external load (not shown). The output voltage Vo is voltage-divided by dividing resistors Ro1and Ro2. The voltage-divided signal, i.e., an detected signal FB is supplied to the control semiconductor integrated circuit12through a third terminal P3. The control semiconductor integrated circuit12includes: an error amplifier11; a voltage-current conversion circuit8which converts the error signal Vcomp being an output from the error amplifier11into a current; a voltage control circuit including an oscillator1; and a current detecting switching transistor Q2, in addition to the switching transistor Q1. The control semiconductor integrated circuit12further includes a comparator6; a pulse width modulating circuit2including an R-S flip-flop3and an NOR circuit4; and a driving circuit5. The control semiconductor integrated circuit12further includes an OCP clamping circuit10for setting an upper limit value of the current for performing overcurrent protection and a low load detecting signal creating circuit7for converting an output signal Icomp2from the voltage-current converting circuit8. The error signal Vcomp is connected to the OCP clamping circuit10. The low load detecting signal creating circuit7produces an Vi1. The error amplifier11is supplied with an output reference voltage Vref1and the detected signal FB to produce the error signal Vcomp according to a difference between these two inputs. The oscillator1produces a pulse signal CLK at a predetermined period. The oscillator1is supplied with the detected signal FB and the Vi1signal from the low load detecting signal creating circuit7. In the oscillator1, lower one of the detected signal FB and the Vi1signal is compared with a period changing reference voltage Vref2(hereinafter referred to as a prescribed voltage). The prescribed voltage Vref2is set to a voltage lower than the voltage of the Vi1signal and detected signal FB during the normal operation. When either one of the detected signal FB and Vi1signal is lower than the predetermined voltage Vref2, the period of the clock signal CLK is changed from the predetermined period into a longer period. The pulse signal CLK at a predetermined period created by the oscillator1is supplied to the setting input S of the R-S flip-flop3contained in the pulse width modulating circuit2. The Qbar output signal from the R-S flip-flop3produces a switching control signal PWM through the NOR circuit4. The switching control signal PWM becomes a base current control signal Ib through a driving circuit5, which is supplied to the bases of the switching transistor Q1and the current detecting switching transistor Q2. The output of the comparator6(reset signal RST) is connected to the reset input R of the R-S flip-flop3. The error signal Vcomp is connected to the input of the voltage-current converter circuit8. Further, by the voltage-current converting circuit8, the error signal Vcomp is converted from a voltage into a current, thereby creating a signal Icomp1and a signal Icomp2. The signals Icomp1and Icomp2are changed in the same manner. The current detecting switching transistor Q2is an NPN bipolar transistor and connected to the collector of the switching transistor Q1, i.e. between the second terminal P2and non-inverting terminal of the comparator6. The base of the current detecting switching transistor Q2is common to the base of the switching transistor Q1and supplied with the base current control signal Ib. The current detecting switching transistor Q2is turned on or off in synchronism with the switching transistor Q1. The current Ic2flowing through the current detecting switching transistor Q2increases with an increase in the current Ic1flowing through the switching transistor Q1. The voltage signal Vs3voltage-converted from the current value flowing through the current detecting switching transistor Q2at a current detecting resistor Rs3is inputted to the non-inverting input terminal of the comparator6. The voltage signal Vs2voltage-converted from the signal Icomp1at a resistor Rs2is inputted to the inverting input of the comparator6. If the voltage signal Vs3≧the voltage signal Vs2is satisfied in the comparator6, a reset signal RST resets the R-S flip-flop3. Then, the switching transistor Q1and the current detecting switching transistor Q2are turned off.

Next, an explanation will be given of the operation of the DC-DC converter explained referring toFIG. 1. First, an overcurrent protected state will be described. Generally, the DC-DC converter, during the operation of the overcurrent protection, forcibly narrows the on-time of switching to decrease the on-duty, thereby lowering the output voltage Vo to limit the output current Io. However, since there is a limit for the detecting speed, the on-time cannot be reduced to a certain value or less. Thus, as the output voltage Vo lowers, the output current Io becomes incapable of being limited. For this reason, by lowering the switching frequency, the on-duty is decreased thereby to limit the output current Io. In this way, the switching transistor Q1is prevented from being broken. The OCP clamping circuit10sets the upper limit of the current for the overcurrent protection. The clamped voltage value in the OCP clamping circuit10serves as an overcurrent detecting point. While the constant voltage control is done, the error signal Vcomp serving as an output from the error amplifier11is lower than the clamped voltage in the OCP clamping circuit10. Further, the error signal Vcomp is linearly changed with an increase in the load current Io. In this case, the external load becomes high load. When the load current Io increases such that the error signal Vcomp reaches the clamped voltage value, the DC-DC converter enters the overcurrent protecting operation. Namely, the reset signal RST is created such that the switching transistor Q1and current detecting switching transistor Q2are turned off. Thus, the on-time is forcibly decreased to lower the output voltage Vo, thereby controlling the output current Io not to be a predetermined value or larger. In this case, since the output voltage Vo lowers, the detected signal FB also lowers. When the detected signal FB≦a prescribed voltage Vref2is satisfied, the oscillator1changes the period of the clock signal CLK from a prescribed period from a longer period so that the switching frequency is lowered. In this way, when the output voltage Vo is low, the output current Io is surely limited, thereby preventing the switching transistor Q1from being broken.

Next, the operation during low load conditions will be explained. Generally, during low load conditions, lowering the switching frequency reduces the switching loss and improves the efficiency. When the conditions of low load are entered, the detected signal FB is increased so that the error signal Vcomp is lowered. Thus, the signal Icomp2is similarly lowered. As a result, the output Vi1signal from the low load detecting signal creating circuit7is lowered. When the Vi1signal≦the prescribed voltage Vref2is satisfied, the oscillator1changes the period of the clock signal CLK from a prescribed period to a longer period such that the switching frequency is lowered. When the switching frequency is lowered, the switching loss is reduced thereby to improve the efficiency. As understood from the description, it is not necessary to provide two separate oscillators, one of which lowers the frequency during overcurrent conditions and the other of which lowers the frequency during low load conditions. That is, a single oscillator1allows lowering the frequency both during overcurrent conditions and during low load conditions. Accordingly, the circuit size can be also reduced.

Now referring toFIG. 2, an explanation will be given of the configuration of the oscillator1in the DC-DC converter according to the embodiment.

FIG. 2is a block diagram showing the configuration of the oscillator1in the DC-DC converter according to this embodiment. As shown inFIG. 2, in the oscillator1in the DC-DC converter according to this embodiment, the detected signal FB and signal Vi1are inputted to an input selecting block21. The detected signal FB is the same as the detected signal FB inputted through the third terminal P3shown inFIG. 1. The signal Vi1is the same as the signal Vi1outputted from the low load detecting signal creating circuit7shown inFIG. 1. The input selecting block21outputs a select signal200and inputted to a frequency control block23. Further, the frequency control block23receives the prescribed voltage Vref2from a reference current setting block22during overcurrent/low load conditions. A frequency setting signal201from the frequency control block23is inputted to an oscillating block24. The oscillating block24outputs the clock signal CLK. Next, referring toFIG. 2, the operation of the oscillator1in the DC-DC converter will be explained. When the detected signal FB lowers to be relatively lower than the signal Vi1, the input selecting block21outputs the signal corresponding to the detected signal FB as the select signal200. The frequency control block23compares the select signal200and the prescribed voltage Vref2. When the detected signal FB≦the prescribed voltage Vref2is satisfied, an operation circuit provided in the frequency control block23operates such that a frequency setting signal201is supplied to the oscillating block24so as to lower the switching frequency. The oscillating block24generates the clock signal CLK having a period longer than the prescribed period. On the other hand, when the signal Vi1lowers to be relatively lower than the detected signal FB, the subsequent operation is the same manner as in a case where the detected signal FB lowers. Namely, when the signal Vi1≦the prescribed voltage Vref2is satisfied, the operation circuit provided in the frequency block23operates such that a frequency setting signal201is supplied to the oscillating block24so as to lower the switching frequency. Further, as a general operation, since the overcurrent gives high load, the detected signal FB and signal Vi1will not be lowered simultaneously and will not be interfered with each other. However, even when the detected signal FB and signal Vi1are lowered simultaneously due to malfunction, the oscillator1operates so as to lower the frequency. As a result, breakage of the switching transistor Q1due to an increase in the output current Io does not occur.

Next, referring toFIG. 3, a specific configuration for lowering the switching frequency of the oscillator1in the DC-DC converter according to the embodiment will be explained.FIG. 3shows an embodiment using bipolar transistors. As shown inFIG. 3, the detected signal FB and the signal Vi1are supplied to the input selecting block21such that the detected signal FB is inputted to the base terminal (hereinafter the base terminal will be referred to as “B”) of a transistor Q3and the signal Vi1is inputted to B of a transistor Q4. The emitter terminal (hereinafter, the emitter terminal will be referred to as “E”) of the transistor Q3and E of the transistor Q4are connected to each other. Further, the output of the select signal200, which is connected to a constant current circuit from an internal regulator output Vreg, is connected to B of a transistor Q5of the frequency control block23. The collector terminal (hereinafter the collector terminal will be referred to as “C”) of the transistor Q3and C of the transistor Q4are connected to a ground potential, respectively. The internal regulator output Vreg is connected to the frequency control block23. Connected to the internal regulator output Vreg are E of a transistor Q7, E of a transistor Q8, E of a transistor Q10, E of a transistor Q11, C of a transistor Q12, C of a transistor Q13, E of a transistor Q17, E of a transistor Q18, E of a transistor Q25and E of a transistor Q26. C and B of the transistor Q7connected to each other are connected to C of the transistor Q5and B of the transistor Q8. E of the transistor Q5is connected to the one terminal of a voltage-current converting resistor R1, and another terminal of the voltage-current converting resistor R1is connected to the ground potential. Connected to C of the transistor Q8are C of a transistor Q6and B of the transistor Q10and B of the transistor Q11. E of the transistor Q6is connected to the one terminal of a voltage-current converting resistor R2and another terminal of the voltage-current converting resistor R2is connected to the ground potential. B of the transistor Q6and E of the transistor Q9are connected to each other and further connected to the constant current circuit of the internal regulator output Vreg. C of the transistor Q9is connected to the ground potential. B of the transistor Q9and B of a transistor Q20are connected to each other and further connected to the prescribed voltage Vref2. C of the transistor Q20is connected to the ground potential. Connected to C of the transistor Q11are B of the transistor Q12, B of the transistor Q13and C of a transistor Q14. E of the transistor Q14is connected to the ground potential. B of the transistor Q14is connected to E of the transistor Q12and further connected to the ground potential through the constant current circuit100. Connected to E of the transistor Q13are C of a transistor Q15and B of a transistor Q21. Connected to B of the transistor Q15are B and C of a transistor Q16, C and B of a transistor Q17and B of a transistor Q18. E of the transistor Q15and E of the transistor Q16are connected to the ground potential. C of the transistor Q18is connected to C of a transistor Q19. The one terminal of a voltage-current converting resistor R3is connected to E of the transistor Q19and another terminal of the voltage-current converting resistor R3is connected to the ground potential. B of the transistor Q19and E of the transistor Q20are connected to each other and further connected to a constant current circuit from the internal regulator output Vreg.

C of the transistor Q21and C and B of a transistor Q22are connected to each other and further connected to the constant current circuit from the internal regulator output Vreg. E of the transistor Q21is connected to the ground potential. Connected to E of the transistor Q22are C and B of a transistor Q23, B of a transistor Q24and the constant current circuit from the internal regulator output Vreg. E of the transistor Q23and E of the transistor Q24are connected to the ground potential. Connected to C of the transistor Q24are C and B of a transistor Q25and B of a transistor Q26. C of the transistor Q26which produces the frequency setting signal201is connected to the oscillating block24. The frequency setting signal201is connected to the one terminal of a frequency setting capacitor Cosc and further connected to C of a transistor Q27and the non-inverting input terminal of a comparator30. Another terminal of the frequency setting capacitor Cosc is connected to the ground potential. Connected to the inverting input terminal of the comparator30are the one terminal of a resistor Rosc3, the one terminal of a resistor Rosc1connected to the internal regulator output Vreg and the one terminal of a resistor Rosc2connected to the ground potential. C of a transistor Q28is connected to another terminal of the resistor Rosc3. The output of the comparator30is connected to B of the transistor Q28and B of a transistor Q29. Connected to C of the transistor Q29are B of a transistor Q31, an input to the an inverter32and a constant current circuit from the internal regulator output Vreg. The output form the inverter32serves as the clock signal CLK. C of the transistor Q31is connected to C and B of a transistor Q30and B of the transistor Q27and further connected to a constant current circuit31from the internal regulator output Vreg. E of the transistor Q27, E of the transistor Q28, E of the transistor Q29, E of the transistor Q30and E of the transistor Q31are connected to the ground potential.

Next, referring toFIGS. 1,2,3and4A and4B, an explanation will be given of the operation of lowering the switching frequency in this embodiment.FIG. 4Aillustrates the operation during low load conditions.FIG. 4Billustrates the operation during overcurrent conditions. “A” inFIGS. 4A and 4Bis a graph showing changes in the waveforms of the signal Vi1, detected signal FB and prescribed voltage Vref2during low load conditions, normal operation conditions and overcurrent conditions. “B” inFIGS. 4A and 4Bis a graph showing changes in the waveform of the error signal Vcomp during low load conditions, normal operation conditions and overcurrent conditions. “C” inFIGS. 4A and 4Bis a graph showing changes in the waveform of a charging current Iosc of the frequency setting signal201during low load conditions, normal operation conditions and overcurrent conditions. “D” inFIGS. 4A and 4Bis a graph showing changes in the waveform of a charging voltage (Vosc) of the frequency setting signal201during low load conditions, normal operation conditions and overcurrent conditions. “E” inFIGS. 4A and 4Bis a graph showing changes in the waveforms of the voltage signal Vs2being an input to the non-inverting input terminal of the comparator6and the voltage signal Vs3being an input to the inverting input terminal of the comparator6during low load conditions, normal operation conditions and overcurrent conditions. “F” inFIGS. 4A and 4Bis a graph showing changes in the waveform of the clock signal CLK during low load conditions, normal operation conditions and overcurrent conditions. “G” inFIGS. 4A and 4Bis a graph showing changes in the waveform of the switching control signal PWM inFIG. 1during low load conditions, normal operation conditions and overcurrent conditions.

First, the operation during low load conditions will be explained.

When the operation condition is shifted from the normal operation conditions to the low load conditions, the error signal Vcomp gradually lowers (“B” inFIG. 4A).

Correspondingly, the signal Vi1starts to lower and eventually becomes lower than the detected signal FB and prescribed voltage Vref2(dotted line400inFIG. 4A“A”). Then, the transistor Q4operates so that the voltage added to the signal Vi1by the base-emitter voltage VBE (hereinafter referred to as VBE) of the transistor Q4is applied to the select signal200. The signal Vi1is therefore selected. Thus, the voltage subtracted from the selected signal200by VBE of the transistor Q5is applied to the voltage-current converting resistor R1. Because VBE of the transistor Q4and VBE of the transistor Q5are approximately equal, the voltage equal to the signal Vi1is applied to the voltage-current converting resistor R1. Accordingly, because the base current of the transistor Q5is substantially negligible, the current I1flowing through C of the transistor Q5can be expressed by
I1=Vi1/R1   (1)

The current I1flows through C of the transistor Q7. Since the transistor Q7and the transistor Q8constitute a current mirror, the same current as the current I1flows through C of the transistor Q8. On the other hand, since the prescribed voltage Vref2is applied to B of the transistor Q9, the voltage added to the prescribed voltage Vref2by VBE of the transistor Q9(signal202) is applied to B of the transistor Q6. Thus, the voltage subtracted from the signal202by VBE of the transistor Q6is applied to the voltage-current converting resistor R2. Since VBE of the transistor Q6are VBE of the transistor Q9are approximately equal, the voltage having a value equal to the prescribed voltage Vref2is applied to the voltage-current converting resistor R2. Thus, because the base current of the transistor Q6is substantially negligible, the current I2flowing through C of the transistor Q6can be expressed by
I2=Vref2/R2   (2)

Accordingly, the current subtracted from I2by I1flows through C of the transistor Q10. Further, since the transistor Q10and the transistor Q11constitute the current mirror, the current I3flowing through C of the transistor Q11can be expressed by
I3=I2−I1   (3)

It should be noted that R1and R2must have equal resistances. By substituting Equations (1) and (2) into Equation (3), I3=(Vref2−Vi1)/R1. This is identical to direct voltage comparison between the prescribed voltage Vref2and the signal Vi1. Further, I4is equal to Iconst. Namely,
I4=Iconst   (4)

Further, the prescribed voltage Vref2is applied to B of the transistor Q20. Thus, the voltage added to the prescribed voltage Vref2by VBE of the transistor Q20is applied to B of the transistor Q19. Accordingly, the voltage lowered from voltage at B of the transistor Q19by VBE of the transistor Q20is applied to the voltage-current converting resistor R3. Since VBE of the transistor Q19and VBE of the transistor Q20are nearly equal to each other, the voltage equal to the prescribed voltage Vref2is applied to the voltage-current converting resistor R3. Further, since the transistor Q17and the transistor Q18constitutes the current mirror, the current flowing through C of the transistor Q17and the current flowing through C of the transistor Q18are equal to each other. Further, since the transistor Q15and the transistor Q16constitute the current mirror, the current flowing through C of the transistor Q16and the current I6flowing through C of the transistor Q15are equal to each other. Therefore, the current flowing through C of the transistor Q18is equal to I6. Further, as apparent fromFIG. 3, the current flowing through C of the transistor Q18is equal to the current flowing through C of the transistor Q19. Therefore, the current flowing through C of the transistor Q19is equal to I6. Accordingly,
I6=Vref2/R3   (5)

Since the current flowing through B of the transistor Q21is negligible,
I5=I6   (6)

The block33inFIG. 3constitutes a current multiplication/division operating circuit. Therefore, the current Ifdn flowing through C of the transistor Q21is expressed by the following equation:
Ifdn=I3*I4/I5   (7)

Next, an equation for computing the charging current Iosc will be described. First, the current subtracted from the I11by Ifdn flows through C of the transistor Q22. Further, the current added to I12by the current flowing through C of the transistor Q22flows through C of the transistor Q23. Since the transistor Q23and the transistor Q24constitute the current mirror, the current flowing through C of the transistor Q23and the current Iosc flowing through C of the transistor Q24are equal to each other. Further, since a transistor Q25and a transistor Q26constitute the current mirror, the current flowing through C of the transistor Q25is equal to the current Iosc flowing through C of the transistor Q26. As apparent fromFIG. 3, the current flowing through C of the transistor Q24and the current flowing through C of the transistor Q25are equal to each other. Therefore,
Iosc=I12+(I11−Ifdn)   (8)

Thus, if Ifdn increases, (I11−Ifdn) decreases. Therefore, Iosc decreases. Further, even if Ifdn becomes larger than I11, the transistor Q22, which is a diode configuration, will not be extracted from I12. So, the minimum value of Iosc is I12. Namely, Iosc becomes constant like period Q inFIG. 4A“C” so that the lower limit of the oscillating frequency can be set.

Now, during the normal operation conditions, since the signal Vi1>the prescribed voltage Vref2, I1becomes larger than I2(R1=R2is set). If I1≧I2, in the circuit operation, the voltage at C of the transistor Q8becomes approximately equal to the internal regulator output Vreg, I3≅0. Then, Iosc=I12+I11. When shifted to the low load conditions, I1becomes I1<I2, and I3starts to flow. Thus, since {I11−(I2−I1)*I4/I5} in Equation (10) becomes smaller than I11, the charging current Iosc of the frequency setting signal201starts to fall (period R inFIG. 4A“C”).

Accordingly, the rising time of the charging voltage Vosc of the frequency setting capacitor Cosc in the oscillating block24inFIG. 3is lengthened. When the charging voltage Vosc reaches an upper threshold value (Vr1), the clock signal CLK becomes a High voltage (hereinafter referred to as H voltage) (FIG. 4A“F”). At this time, since a Low voltage is applied to B of the transistor Q31, the transistor Q31is turned off, and the current mirror circuit including the transistor Q30and the transistor Q27operates. Thus, the current equal the having a current value in the constant current circuit31is passed from the frequency setting signal201to the ground terminal through C of the transistor Q27. At this time, since the charging voltage Vosc must be lowered, the current value in the constant current circuit31must be made larger than that of the charging current Iosc. This is because the falling time (hereinafter referred to as a fall time) of the charging voltage Vosc becomes the length of the H voltage of the clock signal CLK. Further, since the clock signal CLK is supplied to the R-S flip-flop of the pulse signal modulating circuit2at the subsequent stage, the length of the H voltage of the clock signal CLK is not required to be lengthened. For this reason, the current value in the constant current circuit31is set for about ten times as large as the current value of the charging current Iosc. When the charging voltage Vosc reaches a lower threshold value (Vr2), the clock signal CLK becomes a Low voltage (hereinafter referred to as L voltage) (FIG. 4A“F”). Thus, the output from the comparator30becomes the Low level so that the transistor Q28is turned off. Further, the transistor Q31is turned on so that the current mirror including the transistor Q27and the transistor Q30becomes non-operational. Thus, the frequency setting capacitor Cosc starts to be charged with the charging current Iosc. Therefore, if the charging current Iosc is decreased, the rise time of the charging voltage Vosc is lengthened so that the shifting time of the subsequent clock signal CLK from the L voltage to the H voltage (time holding the L voltage) is lengthened, thereby lowering the frequency.

Next, the operation during overcurrent current conditions will be explained. When the operation condition is shifted from the normal operation conditions to the overcurrent conditions, the output voltage Vo lowers so that the detected signal FB gradually lowers (“A” inFIG. 4B) and becomes lower than the prescribed voltage Vref2(dotted line401inFIG. 4B“A”). The transistor Q4operates so that the voltage added to the detected signal FB by VBE of the transistor Q4is applied to the select signal200. Accordingly, the detected signal FB is selected. Thus, the voltage lowered from the select signal200by VBE of the transistor Q5is applied to the voltage-current converting resistor R1. Since VBE of the transistor Q3and VBE of the transistor Q5are approximately equal to each other, the voltage with a value equal to the detected signal FB is applied to the voltage-current converting resistor R1. Thus, since the base current of the transistor Q5is substantially negligible, the current I1flowing through C of the transistor Q5is expressed by
I1=FB/R1   (11)

The subsequent operation is the same as that during the low load conditions. Therefore, from Equation (10), when shifted to the low load conditions so that the detected signal FB lowers, I1becomes I1<I2, and I3starts to flow. Therefore, {I11−(I2−I1)*I4/I5} in Equation (10) becomes smaller than I11, the charging current Iosc of the frequency setting signal201starts to fall (period T inFIG. 4B“C”).

Even if Ifdn becomes larger than I11, the transistor Q22, which is a diode configuration, will not be extracted from I12. Therefore, the minimum value of Iosc is I12. Namely, Iosc becomes constant like period U inFIG. 4B“C” so that the lower limit of the oscillating frequency can be set. Accordingly, by providing the input selecting block21shown inFIG. 2, the single frequency control block23permits two different frequency control operations during the low load condition and during the overcurrent conditions. It is needless to say that it is not necessary to provide the frequency control block for the low load conditions and the frequency control block for the overcurrent conditions separately, thereby simplifying the circuit configuration. Further, if the circuit configuration is realized in a semiconductor integrated circuit, the circuit scale can be reduced and the chip size can be reduced, which contributes to cost reduction of the DC-DC converter and power saving during the low conditions.

Further, as described above, since R1=R2, Equation (12) can be arranged as follows:
Iosc=I12+{I11−(Vref2−Vi1)*Iconst/Vref2}*R3/R1   (13)

As understood from Equation (13), I11, I12an Iconst are a constant, respectively, and R1and R3are in a relationship of ratio as a denominator and a numerator, respectively. For this reason, by using the current converting resistors R1, R2and R3of the same kind of resistor, their temperature characteristics and variations can be cancelled. Thus, the charging current Iosc has no temperature characteristic and variation. Accordingly, the frequency control operation with no temperature characteristic and variation can be realized.

As understood from the above description, the switching DC-DC converter according to this embodiment, two different frequency control operations during the low load conditions and overcurrent conditions can be realized by the single oscillator, which contributes to cost reduction of the DC-DC converter and power saving during the low conditions. Further, the frequency control operation with no temperature characteristic and variation can be realized.