Indexing Operations In Neural Network Processor

Embodiments of the present disclosure relate to indexing in a neural processor circuit. The neural processor circuit includes multiple neural engine circuits and a data processor circuit directly coupled to at least one of the neural engine circuits. The at least one neural engine circuit performs a convolution operation on input data to generate output data. The data processor circuit includes a buffer memory and an indexing circuit coupled to the buffer memory. The buffer memory stores an index tensor and the output data as a source tensor. The indexing circuit fetches a portion of the source tensor from the buffer memory by referencing the index tensor representing indexing information into the portion of the source tensor.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to a circuit for performing operations related to neural networks, and more specifically to a circuit for performing indexing operations in a neural network processor.

2. Description of the Related Arts

An artificial neural network (ANN) is a computing system or model that uses a collection of connected nodes to process input data. The ANN is typically organized into layers where different layers perform different types of transformation on their input. Extensions or variants of ANN such as convolution neural network (CNN), recurrent neural networks (RNN) and deep belief networks (DBN) have come to receive much attention. These computing systems or models often involve extensive computing operations including multiplication and accumulation. For example, CNN is a class of machine learning technique that primarily uses convolution between input data and kernel data, which can be decomposed into multiplication and accumulation operations.

Depending on the types of input data and operations to be performed, these machine learning systems or models can be configured differently. Such varying configuration would include, for example, pre-processing operations, the number of channels in input data, kernel data to be used, non-linear function to be applied to convolution result, and applying of various post-processing operations. Using a central processing unit (CPU) and its main memory to instantiate and execute machine learning systems or models of various configuration is relatively easy because such systems or models can be instantiated with mere updates to code. However, relying solely on the CPU for various operations of these machine learning systems or models would consume significant bandwidth of the CPU as well as increase the overall power consumption.

SUMMARY

Embodiments relate to indexing operations in a neural processor circuit. The neural processor circuit includes multiple neural engine circuits and a data processor circuit directly coupled to at least one of the neural engine circuits. The at least one neural engine circuit performs a convolution operation on input data to generate output data. The data processor circuit includes a buffer memory and an indexing circuit coupled to the buffer memory. The buffer memory stores an index tensor and the output data as a source tensor. The indexing circuit fetches a portion of the source tensor from the buffer memory by referencing the index tensor representing indexing information into the portion of the source tensor.

The figures depict, and the detail description describes, various non-limiting embodiments for purposes of illustration only.

DETAILED DESCRIPTION

Embodiments of the present disclosure relate to indexing operations in a neural processor circuit. An indexing operation can be used for dynamic slicing and data indirection, and enables indirect access of elements in one axis or along one dimension of a source tensor stored in a data processor circuit of the neural processor circuit. The indexing operation allows the data processor circuit to decide which elements in the source tensor to fetch and send to a planar engine circuit or to at least one neural engine circuit for further processing, based on a result of a previous operation (e.g., a reduction operation by the planar engine circuit). Indexing and data indirection can be utilized in various algorithms, such as in the non-maximum suppression algorithm where a single box of pixel data (out of multiple boxes of pixel data stored in the buffer memory) is indexed and fetched from the buffer memory based on a result of a reduction operation (e.g., ArgMax/Min operation) and broadcasted to neural engine circuits for further processing. The data processor circuit includes a buffer memory and an indexing circuit coupled to the buffer memory for performing indexing operations on data (e.g., source tensors) stored in the buffer memory. The buffer memory may also store an index tensor generated by, e.g., the planar engine circuit. Components of the index tensor may be results of a reduction operation performed by the planar engine circuit. The indexing circuit may fetch a portion of a source tensor from the buffer memory (e.g., elements of the source tensor along one axis or dimension) by referencing the index tensor that represents indexing information into the portion of the source tensor. The indexing circuit may provide the fetched portion of the source tensor as input data to the at least one neural engine circuit or the planar engine circuit.

Exemplary Electronic Device

Embodiments of electronic devices, user interfaces for such devices, and associated processes for using such devices are described. In some embodiments, the device is a portable communications device, such as a mobile telephone, that also contains other functions, such as personal digital assistant (PDA) and/or music player functions. Exemplary embodiments of portable multifunction devices include, without limitation, the iPhone®, iPod Touch®, Apple Watch®, and iPad® devices from Apple Inc. of Cupertino, Calif. Other portable electronic devices, such as wearables, laptops or tablet computers, are optionally used. In some embodiments, the device is not a portable communication device, but is a desktop computer or other computing device that is not designed for portable use. In some embodiments, the disclosed electronic device may include a touch-sensitive surface (e.g., a touch screen display and/or a touchpad). An example electronic device described below in conjunction with Figure (FIG.1(e.g., device100) may include a touch-sensitive surface for receiving user input. The electronic device may also include one or more other physical user-interface devices, such as a physical keyboard, a mouse and/or a joystick.

FIG.1is a high-level diagram of an electronic device100, according to one embodiment. Device100may include one or more physical buttons, such as a “home” or menu button104. Menu button104is, for example, used to navigate to any application in a set of applications that are executed on device100. In some embodiments, menu button104includes a fingerprint sensor that identifies a fingerprint on menu button104. The fingerprint sensor may be used to determine whether a finger on menu button104has a fingerprint that matches a fingerprint stored for unlocking device100. Alternatively, in some embodiments, menu button104is implemented as a soft key in a graphical user interface (GUI) displayed on a touch screen.

In some embodiments, device100includes touch screen150, menu button104, push button106for powering the device on/off and locking the device, volume adjustment buttons108, Subscriber Identity Module (SIM) card slot110, headset jack112, and docking/charging external port124. Push button106may be used to turn the power on/off on the device by depressing the button and holding the button in the depressed state for a predefined time interval; to lock the device by depressing the button and releasing the button before the predefined time interval has elapsed; and/or to unlock the device or initiate an unlock process. In an alternative embodiment, device100also accepts verbal input for activation or deactivation of some functions through microphone113. Device100includes various components including, but not limited to, a memory (which may include one or more computer readable storage mediums), a memory controller, one or more central processing units (CPUs), a peripherals interface, an RF circuitry, an audio circuitry, speaker111, microphone113, input/output (I/O) subsystem, and other input or control devices. Device100may include one or more image sensors164, one or more proximity sensors166, and one or more accelerometers168. Device100may include more than one type of image sensors164. Each type may include more than one image sensor164. For example, one type of image sensors164may be cameras and another type of image sensors164may be infrared sensors for facial recognition that is performed by one or more machine learning models stored in device100. Device100may include components not shown inFIG.1such as an ambient light sensor, a dot projector and a flood illuminator that is to support facial recognition.

Device100is only one example of an electronic device, and device100may have more or fewer components than listed above, some of which may be combined into a component or have a different configuration or arrangement. The various components of device100listed above are embodied in hardware, software, firmware or a combination thereof, including one or more signal processing and/or application-specific integrated circuits (ASICs).

FIG.2is a block diagram illustrating components in device100, according to one embodiment. Device100may perform various operations including implementing one or more machine learning models. For this and other purposes, device100may include, among other components, image sensors202, a system-on-a chip (SOC) component204, a system memory230, a persistent storage (e.g., flash memory)228, a motion sensor234, and a display216. The components as illustrated inFIG.2are merely illustrative. For example, device100may include other components (such as speaker or microphone) that are not illustrated inFIG.2. Further, some components (such as motion sensor234) may be omitted from device100.

An image sensor202is a component for capturing image data and may be embodied, for example, as a complementary metal-oxide-semiconductor (CMOS) active-pixel sensor) a camera, video camera, or other devices. Image sensor202generates raw image data that is sent to SOC component204for further processing. In some embodiments, the image data processed by SOC component204is displayed on display216, stored in system memory230, persistent storage228or sent to a remote computing device via network connection. The raw image data generated by image sensor202may be in a Bayer color kernel array (CFA) pattern.

Motion sensor234is a component or a set of components for sensing motion of device100. Motion sensor234may generate sensor signals indicative of orientation and/or acceleration of device100. The sensor signals are sent to SOC component204for various operations such as turning on device100or rotating images displayed on display216.

Display216is a component for displaying images as generated by SOC component204. Display216may include, for example, liquid crystal display (LCD) device or an organic light-emitting diode (OLED) device. Based on data received from SOC component204, display116may display various images, such as menus, selected operating parameters, images captured by image sensor202and processed by SOC component204, and/or other information received from a user interface of device100(not shown).

System memory230is a component for storing instructions for execution by SOC component204and for storing data processed by SOC component204. System memory230may be embodied as any type of memory including, for example, dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) RAMBUS DRAM (RDRAM), static RAM (SRAM) or a combination thereof.

Persistent storage228is a component for storing data in a non-volatile manner. Persistent storage228retains data even when power is not available. Persistent storage228may be embodied as read-only memory (ROM), flash memory or other non-volatile random access memory devices. Persistent storage228stores an operating system of device100and various software applications. Persistent storage228may also store one or more machine learning models, such as regression models, random forest models, support vector machines (SVMs) such as kernel SVMs, and artificial neural networks (ANNs) such as convolutional network networks (CNNs), recurrent network networks (RNNs), autoencoders, and long short term memory (LSTM). A machine learning model may be an independent model that works with the neural processor circuit218and various software applications or sensors of device100. A machine learning model may also be part of a software application. The machine learning models may perform various tasks such as facial recognition, image classification, object, concept, and information classification, speech recognition, machine translation, voice recognition, voice command recognition, text recognition, text and context analysis, other natural language processing, predictions, and recommendations.

Various machine learning models stored in device100may be fully trained, untrained, or partially trained to allow device100to reinforce or continue to train the machine learning models as device100is used. Operations of the machine learning models include various computation used in training the models and determining results in runtime using the models. For example, in one case, device100captures facial images of the user and uses the images to continue to improve a machine learning model that is used to lock or unlock the device100.

SOC component204is embodied as one or more integrated circuit (IC) chip and performs various data processing processes. SOC component204may include, among other subcomponents, image signal processor (ISP)206, a central processor unit (CPU)208, a network interface210, sensor interface212, display controller214, neural processor circuit218, graphics processor (GPU)220, memory controller222, video encoder224, storage controller226, and bus232connecting these subcomponents. SOC component204may include more or fewer subcomponents than those shown inFIG.2.

ISP206is a circuit that performs various stages of an image processing pipeline. In some embodiments, ISP206may receive raw image data from image sensor202, and process the raw image data into a form that is usable by other subcomponents of SOC component204or components of device100. ISP206may perform various image-manipulation operations such as image translation operations, horizontal and vertical scaling, color space conversion and/or image stabilization transformations.

CPU208may be embodied using any suitable instruction set architecture, and may be configured to execute instructions defined in that instruction set architecture. CPU208may be general-purpose or embedded processors using any of a variety of instruction set architectures (ISAs), such as the x86, PowerPC, SPARC, RISC, ARM or MIPS ISAs, or any other suitable ISA. Although a single CPU is illustrated inFIG.2, SOC component204may include multiple CPUs. In multiprocessor systems, each of the CPUs may commonly, but not necessarily, implement the same ISA.

Graphics processing unit (GPU)220is graphics processing circuitry for performing graphical data. For example, GPU220may render objects to be displayed into a frame buffer (e.g., one that includes pixel data for an entire frame). GPU220may include one or more graphics processors that may execute graphics software to perform a part or all of the graphics operation, or hardware acceleration of certain graphics operations.

Neural processor circuit218is a circuit that performs various machine learning operations based on computation including multiplication, addition, and accumulation. Such computation may be arranged to perform, for example, various types of tensor multiplications such as tensor product and convolution of input data and kernel data. Neural processor circuit218is a configurable circuit that performs these operations in a fast and power-efficient manner while relieving CPU208of resource-intensive operations associated with neural network operations. Neural processor circuit218may receive the input data from sensor interface212, ISP206, persistent storage228, system memory230or other sources such as network interface210or GPU220. The output of neural processor circuit218may be provided to various components of device100such as ISP206, system memory230or CPU208for various operations. The structure and operation of neural processor circuit218are described below in detail with reference toFIG.3.

Network interface210is a subcomponent that enables data to be exchanged between devices100and other devices via one or more networks (e.g., carrier or agent devices). For example, video or other image data may be received from other devices via network interface210and be stored in system memory230for subsequent processing (e.g., via a back-end interface to ISP206) and display. The networks may include, but are not limited to, Local Area Networks (LANs) (e.g., an Ethernet or corporate network) and Wide Area Networks (WANs). The image data received via network interface210may undergo image processing processes by ISP206.

Sensor interface212is circuitry for interfacing with motion sensor234. Sensor interface212receives sensor information from motion sensor234and processes the sensor information to determine the orientation or movement of device100.

Display controller214is circuitry for sending image data to be displayed on display216. Display controller214receives the image data from ISP206, CPU208, graphic processor or system memory230and processes the image data into a format suitable for display on display216.

Memory controller222is circuitry for communicating with system memory230. Memory controller222may read data from system memory230for processing by ISP206, CPU208, GPU220or other subcomponents of SOC component204. Memory controller222may also write data to system memory230received from various subcomponents of SOC component204.

Video encoder224is hardware, software, firmware or a combination thereof for encoding video data into a format suitable for storing in persistent storage228or for passing the data to network interface210for transmission over a network to another device.

In some embodiments, one or more subcomponents of SOC component204or some functionality of these subcomponents may be performed by software components executed on neural processor circuit218, ISP206, CPU208or GPU220. Such software components may be stored in system memory230, persistent storage228or another device communicating with device100via network interface210.

Example Neural Processor Circuit

Neural processor circuit218is a programmable circuit that performs machine learning operations on the input data of neural processor circuit218. Machine learning operations may include different computations for training of a machine learning model and for performing inference or prediction based on the trained machine learning model.

Taking an example of a CNN as the machine learning model, training of the CNN may include forward propagation and backpropagation. A neural network may include an input layer, an output layer, and one or more intermediate layers that may be referred to as hidden layers. Each layer may include one or more nodes, which may be fully or partially connected to other nodes in adjacent layers. In forward propagation, the neural network performs computation in the forward direction based on outputs of a preceding layer. The operation of a node may be defined by one or more functions. The functions that define the operation of a node may include various computation operation such as convolution of data with one or more kernels, pooling of layers, tensor multiplication, etc. The functions may also include an activation function that adjusts the weight of the output of the node. Nodes in different layers may be associated with different functions. For example, a CNN may include one or more convolutional layers that are mixed with pooling layers and are followed by one or more fully connected layers.

Each of the functions, including kernels, in a machine learning model may be associated with different coefficients that are adjustable during training. In addition, some of the nodes in a neural network each may also be associated with an activation function that decides the weight of the output of the node in a forward propagation. Common activation functions may include step functions, linear functions, sigmoid functions, hyperbolic tangent functions (tanh), and rectified linear unit functions (ReLU). After a batch of data of training samples passes through a neural network in the forward propagation, the results may be compared to the training labels of the training samples to compute the network's loss function, which represents the performance of the network. In turn, the neural network performs backpropagation by using coordinate descent such as stochastic coordinate descent (SGD) to adjust the coefficients in various functions to improve the value of the loss function.

In training, device100may use neural processor circuit218to perform all or some of the operations in the forward propagation and backpropagation. Multiple rounds of forward propagation and backpropagation may be performed by neural processor circuit218, solely or in coordination with other processors such as CPU208, GPU220, and ISP206. Training may be completed when the loss function no longer improves (e.g., the machine learning model has converged) or after a predetermined number of rounds for a particular set of training samples. As device100is used, device100may continue to collect additional training samples for the neural network.

For prediction or inference, device100may receive one or more input samples. Neural processor circuit218may take the input samples to perform forward propagation to determine one or more results. The input samples may be images, speeches, text files, sensor data, or other data.

Data and functions (e.g., input data, kernels, functions, layers outputs, gradient data) in machine learning may be saved and represented by one or more tensors. Common operations related to training and runtime of a machine learning model may include tensor product, tensor transpose, tensor elementwise operation, convolution, application of an activation function, automatic differentiation to determine gradient, statistics and aggregation of values in tensors (e.g., average, variance, standard deviation), tensor rank and size manipulation, etc.

While the training and runtime of a neural network is discussed as an example, neural processor circuit218may also be used for the operations of other types of machine learning models, such as a kernel SVM.

Referring toFIG.3, an example neural processor circuit218may include, among other components, a neural task manager310, neural engines314A through314N (hereinafter collectively referred as “neural engines314” and individually also referred to as “neural engine314”), a kernel direct memory access (DMA)324, a data processor circuit318, a data processor DMA320, and a planar engine340. Neural processor circuit218may include fewer or additional components not illustrated inFIG.3.

Each of neural engines314performs computing operations for machine learning in parallel. Depending on the load of operation, the entire set of neural engines314may be operating or only a subset of the neural engines314may be operating while the remaining neural engines314are placed in a power-saving mode to conserve power. Each of neural engines314includes components for storing one or more kernels, for performing multiply-accumulate operations, and for post-processing to generate an output data328, as described below in detail with reference toFIG.4. Neural engines314may specialize in performing computation heavy operations such as convolution operations and tensor product operations. Convolution operations may include different kinds of convolutions, such as cross-channel convolutions (a convolution that accumulates values from different channels), channel-wise convolutions, and transposed convolutions.

Planar engine340may specialize in performing simpler computing operations whose speed may primarily depend on the input and output (I/O) speed of the data transmission instead of the computation speed within planar engine340. Those computing operations may be referred to as I/O bound computations. In contrast, neural engines314may focus on complex computation whose speed may primarily depend on the computation speed within each neural engine314. For example, planar engine340is efficient at performing operations within a single channel while neural engines314are efficient at performing operations across multiple channels that may involve heavy accumulation of data. The use of neural engine314to compute I/O bound computations may not be efficient in terms of both speed and power consumption. In one embodiment, input data may be a tensor whose rank is larger than three (e.g., having three or more dimensions). A set of dimensions (two or more) in the tensor may be referred to as a plane while another dimension may be referred to as a channel. Neural engines314may convolve data of a plane in the tensor with a kernel and accumulate results of the convolution of different planes across different channels. On the other hand, planar engine340may specialize in operations within the plane.

The circuitry of planar engine340may be programmed for operation in one of multiple modes, including a pooling mode, an elementwise mode, and a reduction mode. In the pooling mode, planar engine340reduces a spatial size of input data. In the elementwise mode, planar engine340generates an output that is derived from elementwise operations of one or more inputs. In the reduction mode, planar engine340reduces the rank of a tensor. For example, a rank 5 tensor may be reduced to a rank 2 tensor, or a rank 3 tensor may be reduced to a rank 0 tensor (e.g., a scalar). The operations of planar engine340will be discussed in further detail below with reference toFIG.5.

Neural task manager310manages the overall operation of neural processor circuit218. Neural task manager310may receive a task list from a compiler executed by CPU208, store tasks in its task queues, choose a task to perform, and send task commands to other components of neural processor circuit218for performing the chosen task. Data may be associated with a task command that indicates the types of operations to be performed on the data. Data of neural processor circuit218includes input data that is transmitted from another source such as system memory230, and data generated by neural processor circuit218in a previous operating cycle. Each dataset may be associated with a task command that specifies the type of operations to be performed on the data. Neural task manager310may also perform switching of tasks on detection of events such as receiving instructions from CPU208. In one or more embodiments, neural task manager310sends rasterizer information to the components of neural processor circuit218to enable each of the components to track, retrieve or process appropriate segments of the input data and kernel data. For example, neural task manager310may include registers that stores the information regarding the size and rank of a dataset for processing by neural processor circuit218. Although neural task manager310is illustrated inFIG.3as part of neural processor circuit218, neural task manager310may be a component outside neural processor circuit218.

Kernel DMA324is a read circuit that fetches kernel data from a source (e.g., system memory230) and sends kernel data326A through326N to each of neural engines314. Kernel data represents information from which kernel elements can be extracted. In one embodiment, the kernel data may be in a compressed format which is decompressed at each of neural engines314. Although kernel data provided to each of neural engines314may be the same in some instances, the kernel data provided to each of neural engines314is different in most instances. In one embodiment, the direct memory access nature of kernel DMA324may allow kernel DMA324to fetch and write data directly from the source without the involvement of CPU208.

Data processor circuit318manages data traffic and task performance of neural processor circuit218. Data processor circuit318may include a flow control circuit332, a buffer memory334, an indexing circuit336coupled to buffer memory334, and a formatting circuit338coupled to indexing circuit336. Buffer memory334is temporary storage for storing data associated with operations of neural processor circuit218and planar engine340, such as input data that is transmitted from system memory230(e.g., data from a machine learning model) and other data that is generated within neural processor circuit218or planar engine340. The data stored in data processor circuit318may include different subsets that are sent to various downstream components, such as neural engines314and planar engine340.

In one embodiment, buffer memory334is embodied as a non-transitory memory that can be accessed by neural engines314and planar engine340. Buffer memory334may be a direct memory access buffer that stores data of a machine learning model of device100without involvement of CPU208. Buffer memory334may store input data322A through322N for feeding to corresponding neural engines314A through314N or planar engine340, as well as output data328A through328N from each of neural engines314A through314N or planar engine340for feeding back into one or more neural engines314or planar engine340, or sending to a target circuit (e.g., system memory230). Buffer memory334may also store input data342and output data344of planar engine340and allow the exchange of data between neural engine314and planar engine340. For example, one or more output data328A through328N of neural engines314are used as input data342to planar engine340. Likewise, output data344of planar engine340may be used as input data322A through322N of neural engines314. The inputs of neural engines314or planar engine340may be any data stored in buffer memory334. For example, in various operating cycles, the source datasets from which one of the engines fetches as inputs may be different. The input of an engine may be an output of the same engine in previous operating cycles, outputs of different engines, or any other suitable source datasets stored in buffer memory334. Also, a dataset in buffer memory334may be divided and sent to different engines for different operations in the next operating cycle. Two datasets in buffer memory334may also be joined for the next operation.

Flow control circuit332of data processor circuit318may control the exchange of data between neural engines314and planar engine340. The operations of data processor circuit318and other components of neural processor circuit218are coordinated so that the input data and intermediate data stored in data processor circuit318may be reused across multiple operations at neural engines314and planar engine340, thereby reducing data transfer to and from system memory230. Flow control circuit332may perform one or more of the following operations: (i) monitor the size and rank of data (e.g. data may be one or more tensors) that are being processed by neural engines314and planar engine340, (ii) determine which subsets of data are transmitted to neural engines314or to planar engine340based on the task commands associated with different subsets of data, (iii) determine the manner in which data is transmitted to neural engines314and planar engine340(e.g., data processor circuit318may operate in a broadcast mode where the same data is fed to multiple input channels of neural engines314so that multiple or all neural engines314receive the same data or in a unicast mode where different neural engines314receives different data), and (iv) transmit a configuration command to planar engine340to direct planar engine340to program itself for operating in one of multiple operation modes.

Indexing circuit336may perform indexing operations in neural processor circuit218. Indexing circuit336may fetch a portion of a source tensor from buffer memory334(e.g., elements of one axis or dimension of the source tensor) by referencing an index tensor in buffer memory334representing indexing information into the portion of the source tensor. The source tensor may be generated by neural engine314and written into buffer memory334as part of output data328. Alternatively, the source tensor may be generated by planar engine340and written into buffer memory334as part of output data344. In one or more embodiments, the index tensor is generated by planar engine340and written into buffer memory334as part of output data344. An indexing operation performed by indexing circuit336may allow a source of planar engine340(e.g., input data342) to be offset by a scalar value that is also fetched from buffer memory334(e.g., as part of the index tensor). Formatting circuit338may receive the fetched portion of the source tensor from indexing circuit336, and perform formatting and/or aligning of the fetched portion of the source tensor to generate an aligned version of the source tensor for, e.g., at least one neural engine314or planar engine340. Indexing operations may be applied to reads of planar engine340(e.g., input data342) for all operations at planar engine340except pooling and ternary operations. A structure and operations of indexing circuit336and formatting circuit338will be discussed in further detail below with reference toFIG.6andFIG.7.

The data of neural processor circuit218stored in buffer memory334may be part of, among others, image data, histogram of oriented gradients (HOG) data, audio data, metadata, output data328of a previous operating cycle of neural engine314, and other processed data received from other components of SOC component204.

Tensor access operation circuit320is a circuit that directly access system memory320for fetching input data from system memory and writing output data into system memory230. Tensor access operation circuit320may include a read circuit that receives a segment of the input data (e.g., tensor) from system memory230for further storage into buffer memory334. Tensor access operation circuit320may further include a write circuit that forwards data from buffer memory334to system memory230. In one embodiment, the direct memory access nature of tensor access operation circuit320allows tensor access operation circuit320to fetch and write data directly from system memory230without the involvement of CPU208. Tensor access operation circuit320includes a texture unit circuit330for fetching the segment of the input data (e.g., tensor) from system memory230and for processing the tensor before sending the tensor to buffer memory334.

Example Neural Engine Architecture

FIG.4is a block diagram of neural engine314, according to one embodiment. Neural engine314performs various operations to facilitate machine learning such as convolution, tensor product, and other operations may involve heavy computation. For this purpose, neural engine314receives input data322, performs multiply-accumulate operations (e.g., convolution operations) on input data322based on stored kernel data, performs further post-processing operations on the result of the multiply-accumulate operations, and generates output data328. Input data322and/or output data328of neural engine314may be of a single channel or span across multiple channels.

Neural engine314may include, among other components, input buffer circuit402, computation core416, neural engine (NE) control418, kernel extract circuit432, accumulator circuit414and output circuit424. Neural engine314may include fewer components than what is illustrated inFIG.4or include further components not illustrated inFIG.4.

Input buffer circuit402is a circuit that stores a subset of the data of neural processor circuit218as the subset of data is received from a source. The source may be data processor circuit318, planar engine340, or another suitable component. Input buffer circuit402sends an appropriate segment408of data for a current task or process loop to computation core416for processing. Input buffer circuit402may include a shifter410that shifts read locations of input buffer circuit402to change segment408of data sent to computation core416. By changing segments of input data provided to computation core416via shifting, neural engine314can perform multiply-accumulate for different segments of input data based on a fewer number of read operations. In one or more embodiments, the data of neural processor circuit218includes data of difference convolution groups and/or input channels.

Kernel extract circuit432is a circuit that receives kernel data326from kernel DMA324and extracts kernel coefficients422. In one embodiment, kernel extract circuit432references a lookup table (LUT) and uses a mask to reconstruct a kernel from compressed kernel data326based on the LUT. The mask indicates locations in the reconstructed kernel to be padded with zero and remaining locations to be filled with numbers. Kernel coefficients422of the reconstructed kernel are sent to computation core416to populate register in multiply-add (MAD) circuits of computation core416. In other embodiments, kernel extract circuit432receives kernel data in an uncompressed format and the kernel coefficients are determined without referencing a LUT or using a mask.

Computation core416is a programmable circuit that performs computation operations. For this purpose, computation core416may include MAD circuits MAD0through MADN and a post-processor428. Each of MAD circuits MAD0through MADN may store an input value in segment408of the input data and a corresponding kernel coefficient in kernel coefficients422. The input value and the corresponding kernel coefficient are multiplied in each of MAD circuits to generate a processed value412.

Accumulator circuit414is a memory circuit that receives and stores processed values412from MAD circuits. The processed values stored in accumulator circuit414may be sent back as feedback information419for further multiply and add operations at MAD circuits or sent to post-processor428for post-processing. Accumulator circuit414in combination with MAD circuits form a multiply-accumulator (MAC)404. In one or more embodiments, accumulator circuit414may have subunits (or batches) where each subunit sends data to different components of neural engine314. For example, during an operating cycle, data stored in a first subunit of accumulator circuit414is sent to MAC404while data stored in a second subunit of accumulator circuit414is sent to post-processor428.

Post-processor428is a circuit that performs further processing of values412received from accumulator circuit414. Post-processor428may perform operations including, but not limited to, applying linear functions (e.g., Rectified Linear Unit (ReLU)), normalized cross-correlation (NCC), merging the results of performing neural operations on 8-bit data into 16-bit data, and local response normalization (LRN). The result of such operations is output from post-processor428as processed values417to output circuit424. In some embodiments, the processing at post-processor428is bypassed. For example, the data in accumulator circuit414may be sent directly to output circuit424for access by other components of neural processor circuit218.

NE control418controls operations of other components of neural engine314based on the operation modes and parameters of neural processor circuit218. Depending on different modes of operation (e.g., group convolution mode or non-group convolution mode) or parameters (e.g., the number of input channels and the number of output channels), neural engine314may operate on different input data in different sequences, return different values from accumulator circuit414to MAD circuits, and perform different types of post-processing operations at post-processor428. To configure components of neural engine314to operate in a desired manner, NE control418sends task commands that may be included in information419to components of neural engine314. NE control418may include a rasterizer430that tracks the current task or process loop being processed at neural engine314.

Input data is typically split into smaller pieces of data for parallel processing at multiple neural engines314or neural engines314and planar engine340. A set of data used for a convolution operation may be referred to as a convolution group, which can be split into multiple smaller units. The hierarchy of smaller units (segments) may be convolution groups, slices, tiles, work units, output channel groups, input channels (Cin), sub-Cins for input stride, etc. For example, a convolution group may be split into several slices; a slice may be split into several tiles; a tile may be split into several work units; and so forth. In the context of neural engine314, a work unit may be a segment of the input data, such as data processed by planar engine340or data processed during a prior operating cycle of neural engines314having a size that produces output values that fit into accumulator circuit414of neural engine314during a single operating cycle of computation core416. In one case, the size of each work unit is 256 bytes. In such embodiments, for example, work units can be shaped to one of 16×16, 32×8, 64×4, 128×2 or 256×1 datasets. In the context of planar engine340, a work unit may be (i) a segment of input data, (ii) data from neural engine314or (iii) data from a prior operating cycle of planar engine340that can be processed simultaneously at planar engine340.

Rasterizer430may perform the operations associated with dividing the input data into smaller units (segments) and regulate the processing of the smaller units through MACs404and accumulator circuit414. Rasterizer430keeps track of sizes and ranks of segments of the input/output data (e.g., groups, work units, input channels, output channels) and instructs the components of a neural processor circuit218for proper handling of the segments of the input data. For example, rasterizer430operates shifters410in input buffer circuits402to forward correct segments408of input data to MAC404and send the finished output data328to data buffer memory334. Other components of neural processor circuit218(e.g., kernel DMA324, buffer DMA320, buffer memory334, planar engine340) may also have their corresponding rasterizers to monitor the division of input data and the parallel computation of various segments of input data in different components.

Output circuit424receives processed values417from post-processor428and interfaces with data processor circuit318to store processed values417in data processor circuit318. For this purpose, output circuit424may send out output data328in a sequence or a format that is different from the sequence or format in which the processed values417are processed in post-processor428.

The components in neural engine314may be configured during a configuration period by NE control418and neural task manager310. For this purpose, neural task manager310sends configuration information to neural engine314during the configuration period. The configurable parameters and modes may include, but are not limited to, mapping between input data elements and kernel elements, the number of input channels, the number of output channels, performing of output strides, and enabling/selection of post-processing operations at post-processor428.

Example Planar Engine

FIG.5is a block diagram of planar engine340, according to one embodiment. Planar engine340is a circuit that is separated from neural engines314and can be programmed to perform in different modes of operations. For example, planar engine340may operate in a pooling mode that reduces the spatial size of data, in a reduction mode that reduces the rank of a tensor, in a gain-and-bias mode that provides a single-pass addition of bias and scaling by a scale factor, and in an elementwise mode that includes elementwise operations. For this purpose, planar engine340may include, among other components, a first format converter502, a first filter506(also referred to herein as “multi-mode horizontal filter506”), a line buffer510, a second filter514(also referred to herein as “multi-mode vertical filter514”), a post-processor518, a second format converter522, and a planar engine (PE) control530(includes rasterizer540). Planar engine340may include fewer components or further components not illustrated inFIG.5. Each component in planar engine340may be embodied as a circuit or a circuit in combination with firmware or software.

Input data342of planar engine340may be fetched from one or more source datasets that are saved in data processor circuit318. If a dataset to be processed by planar engine340is larger than a work unit of data that can be simultaneously processed by planar engine340, such dataset may be segmented into multiple work units for reading as input data342to planar engine340. Depending on the mode of planar engine340, input data342may include data from one or more source datasets. The source dataset described herein refers to different data saved in neural processor circuit218for processing. Different components of neural processor circuit218may generate or transmit data that is saved in data processor circuit318. For example, neural engines314, planar engine340(which generated data in a previous operation cycle), and system memory230may generate or transmit different datasets that are saved in different memory locations of data processor circuit318. Various source datasets may represent different tensors. In an operation cycle of planar engine340, different source datasets may be fetched together as input data342. For example, in an elementwise mode that involves the addition of two different tensors to derive a resultant tensor, the input data342may include data from two different source datasets, each providing a separate tensor. In other modes, a single source dataset may provide input data342. For example, in a pooling mode, input data342may be fetched from a single source dataset.

First format converter502is a circuit that performs one or more format conversions on input data342in one format (e.g., a format used for storing in buffer memory334) to another format for processing in subsequent components of planar engine340. Such format conversions may include, among others, the following: applying a ReLU function to one or more values of input data342, converting one or more values of input data342to their absolute values, transposing a tensor included in the sources, applying gain to one or more values of input data342, biasing one or more values of input data342, normalizing or de-normalizing one or more values of input data342, converting floating-point numbers to signed or unsigned numbers (or vice versa), quantizing numbers, and changing the size of a tensor such as by broadcasting a value of a tensor in one or more dimensions to expand the rank of the tensor. The converted input data342and unconverted input data342to planar engine340are collectively referred to herein as “a version of the input data.”

First filter506is a circuit that performs a filtering operation in one direction. For this purpose, first filter506may include, among other components, adders, comparators, and multipliers. The filtering performed by first filter506may be, for example, averaging, choosing a maximum value or choosing a minimum value. When averaging, adders are used to sum the values of input data342and a weighting factor may be applied to the sum using a multiplier to obtain the average as the resultant values. When selecting maximum and minimum values, the comparators may be used in place of the adders and the multipliers to select the values.

Line buffer510is a memory circuit for storing the result such as one or more intermediate data obtained from first filter506or second filter514. Line buffer510may store values of different lines and allows access from second filter514or other downstream components to fetch the intermediate data for further processing. In some modes, line buffer510is bypassed. Line buffer510may also include logic circuits to perform additional operations other than merely storing the intermediate data. For example, line buffer510includes adder circuits512, which in combination with memory component, enables line buffer510to function as an accumulator that aggregates data generated from the results of first filter506or second filter514to separately store aggregated data of a dimension not to be reduced.

Similar to first filter506, second filter514performs filtering operations but in a direction different from first filter506. For this purpose, second filter514may include, among other components, adders, comparators, and multipliers. In the pooling mode, first filter506performs filtering operation in a first dimension, while second filter514performs filtering operation in a second dimension. In other modes, first filter506and second filter514may operate differently. In a reduction mode, for example, first filter506performs elementwise operations while second filter514functions as a reduction tree to aggregate values of data.

Post-processor518is a circuit that performs further processing of values fetched from other upstream components. Post-processor518may include specialized circuits that are efficient at performing certain types of mathematical computations that might be inefficient to perform using a general computation circuit. Operations performed by post-processor518may include, among others, performing square root operations and inverse of values in a reduction mode. Post-processor518may be bypassed in other operation modes.

Second format converter522is a circuit that converts the results of preceding components in planar engine340from one format to another format for output data344. Such format conversions may include, among others, the following: applying a ReLU function to the results, transposing a resultant tensor, normalizing or de-normalizing one or more values of the results, and other number format conversions. Output data344may be stored in data processor circuit318as the output of neural processor circuit218or as inputs to other components of neural processor circuit218(e.g., neural engine314).

PE control530is a circuit that controls operations of other components in planar engine340based on the operation mode of planar engine340. Depending on the different modes of operation, PE control530programs register associated with the different components in planar engine340so that the programmed components operate in a certain manner. The pipeline of components or connections between the components in planar engine340may also be reconfigured. In the pooling mode, for example, data processed at by first filter506may be stored in line buffer510and then be read by second filter514for further filtering. In the reduction mode, however, data is processed by first filter506, then processed at second filter514and then accumulated in line buffer510that is programmed as an accumulator. In the elementwise mode, line buffer510may be bypassed.

PE control530also includes a rasterizer540that tracks the current task or process loop being processed at planar engine340. Rasterizer540is a circuit that tracks units or segments of input data and/or loops for processing the input data in planar engine340. Rasterizer540may control the fetch of segments to planar engine340in each operation cycle and may monitor the size and rank of each segment being processed by planar engine340. For example, smaller segments of a dataset may be fetched as input data342in a raster order for processing at planar engine340until all segments of the source dataset are processed. In fetching the segments, rasterizer540monitors the coordinate of the segment in the dataset. The manner in which a dataset is segmented into input data342for processing at planar engine340may be different compared to how a dataset is segmented into input data328for processing at neural engines314.

The dataset for processing at planar engine340may be larger than the capacity of planar engine340that can be processed in a single operation cycle. In such case, planar engine340fetches different segments of the dataset as input data342in multiple operating cycles. The fetched segment may partly overlap with a previously fetched segment and/or a next segment to be fetched. In one embodiment, the portion of overlapping data is fetched only once and reused to reduce the time and power consumption cost of planar engine340in fetching data.

Example Indexing Circuit in Data Processor Circuit

FIG.6is a block diagram of indexing circuit336in data processor circuit318for fetching a portion of a source tensor from buffer memory334, according to one embodiment. Indexing circuit336may include, among other components, a rasterizer602, an index tensor fetching circuit606coupled to rasterizer602, and a source tensor fetching circuit612coupled to index tensor fetching circuit606.

Rasterizer602is a task descriptor circuit that generates one or more index values604for referencing an index tensor610previously stored in buffer memory334. One or more index values604generated by rasterizer602may be passed onto index tensor fetching circuit606. In data processor circuit, a rasterizer would track the data being written to or written out of buffer memory334. In addition to tracking data (e.g., work units, slices, tensors, etc.) being stored and read from data processor circuit318, rasterizer602may track the data being written to or written out of buffer memory334. Rasterizer602may be part of indexing circuit336(as shown inFIG.6), or may be a standalone circuit of data processor circuit318. Alternatively or additionally, rasterizer602may be implemented as a software component or a firmware component.

Index tensor fetching circuit606is a circuit that fetches index tensor610from buffer memory334. Index tensor fetching circuit606may receive one or more index values604from rasterizer602, and produce one or more address values608for referencing index tensor610in buffer memory334. Index tensor fetching circuit606may fetch one or more index components of index tensor610from buffer memory334using one or more address values608. Index tensor610may be a multi-dimensional (e.g., five-dimensional) tuple with index components representing, e.g., width, height, channel, depth, and group of the source tensor in buffer memory334. Each index component in index tensor610may represent indexing information for referencing a corresponding portion (axis or dimension) of the source tensor in buffer memory334. Each index component in index tensor610may be, e.g., U16 (unsigned 16-bit) value, stored as a 16-bit quantity in buffer memory334. Index components in index tensor610may be produced from FP16 (16-bit floating-point) data by, e.g., scaling integers in the range 0, 1, . . . , 2048 by 2−14. Alternatively, index components in index tensor610may be directly produced by planar engine340as a result of a reduction operation (e.g., ArgMax/Min operation) applied on at least a portion of input data342. Once one or more index components of index tensor610are fetched from buffer memory334, index tensor fetching circuit606may pass the fetched one or more index components of index tensor610onto source tensor fetching circuit612.

Source tensor fetching circuit612is a circuit that fetches a portion of the source tensor from buffer memory334as a source surface616by referencing at least one index component614in index tensor610(e.g., stored locally in source tensor fetching circuit612) representing indexing information into the portion (e.g., axis or dimension) of the source tensor. In a first indexing mode (e.g., as defined by a first value of indexing mode bits618generated by rasterizer602), source tensor fetching circuit612may perform a straight indirection in order to fetch source surface616from buffer memory334. In the first indexing mode, source tensor fetching circuit612may fetch elements of the source tensor along an axis (dimension) of the source tensor as source surface616that are indexed by at least one index component614in index tensor610. Source surface616fetched from buffer memory334may represent a version of the source tensor scrambled along the indexed axis. Source surface616may be passed onto formatting circuit338for further processing.

In a second indexing mode (e.g., as defined by a second value of indexing mode bits618generated by rasterizer602), source tensor fetching circuit612may perform a slicing operation on the source tensor in buffer memory334when fetching source surface616. In the second indexing mode, source tensor fetching circuit612may fetch source surface616by fetching a slice of the source tensor in buffer memory334along an axis (dimension) of the source tensor starting from an offset value (e.g., scalar value) obtained from index tensor610(e.g., index component614in index tensor610), where the slice is of a size that fits into buffer memory334. The offset value may be used as a dynamic offset to fetch a particular set of samples from an axis of the source tensor in buffer memory334.

In the second indexing mode, a per-batch scalar value from index tensor610may be applied as an offset to the source tensor in buffer memory334along an axis of the source tensor that is specified by, e.g., indexing mode bits618. Instead of fetching elements y=0, 1, . . . , Hin−1 of the source tensor, source tensor fetching circuit612may fetch elements y=Val, Val+1, . . . , Val+Hin−1 as a fetched slice of the source tensor, where indexing mode bits618enable slicing along Y (height) dimension and Val is an offset value fetched from index tensor610. The fetched slice of source tensor may be passed onto formatting circuit338as source surface616for further processing.

A maximum value of index component614(e.g., MaxIndex) that can be read from index tensor610may be configurable. The effect of configuring MaxIndex can be to clamp a value of index component614read from index tensor610. This can limit an extent of the source tensor in the event that index tensor610contains out-of-bound index components (indexes). In the first indexing mode, out-of-range index components614in index tensor610may cause source tensor fetching circuit612to fetch a value from buffer memory334at Src[MaxIndex]. Thus, if index tensor610was initialized with a series of numbers that eventually exceeded MaxIndex, then edge values in source surface616fetched from buffer memory334would be replicated to be e.g., MaxIndex−1, MaxIndex, MaxIndex, MaxIndex, etc., while index tensor610may have arbitrary values of index components614. In the second indexing mode, instead of performing edge-replication along a slice of the source tensor in buffer memory334, an origin of the slice may be constrained so that the entire slice is constrained to be inside index tensor610. For example, if a value of Idx[0] index component in index tensor610is larger than MaxIndex, then the slice of the source tensor fetched from buffer memory334may start at, e.g., MaxIndex and end at MaxIndex+Hin−1.

Formatting circuit338is a circuit that applies certain processing onto source surface616fetched from buffer memory334. Formatting circuit338may perform a transpose operation on elements of source surface616to generate a processed (transposed) version of source tensor620. Alternatively or additionally, formatting circuit338may perform formatting and aligning of source surface616to generate processed (aligned) version of source tensor620. Processed version of source tensor620generated by formatting circuit338may be passed onto demultiplexer622.

Demultiplexer622may broadcast processed version of source tensor620as a portion of input data322to neural engines314in accordance to a first value of a select bit624generated, e.g., by rasterizer602. Alternatively, demultiplexer622may send processed version of source tensor620as a portion of input data322to a specific neural engine314. At least one neural engine314may receive input data322that include processed version of source tensor620, and perform at least one convolution operation on at least a portion of processed version of source tensor620to generate output data328that may be written back into buffer memory334. Furthermore, demultiplexer622may send processed version of source tensor620as a portion of input data342to planar engine340based on a second value of select bit624generated, e.g., by rasterizer602. Planar engine340may receive input data342that include processed version of source tensor620, and perform a planar operation on at least a portion of processed version of source tensor620to generate a planar version of source tensor. Planar engine340may then write back the planar version of source tensor into buffer memory334as output data344.

Indexing mode bits618may include at least two types of bits that can be set independently—index broadcasting bits and source broadcasting bits, thus providing three different indexing modes: indirection, slicing and broadcasting. In the case of source broadcasting mode, a single value may be fetched from the source tensor in buffer memory334, which is then replicated to an output extent, e.g., to source surface616fetched by source tensor fetching circuit612. In the case of index broadcasting mode, a single index value i may be fetched from index tensor610in buffer memory334, which may be then replicated as a sequence of index values614, e.g., i, i+1, i+2, i+3, etc. used for fetching source surface616from buffer memory334. Index components in index tensor610may be batched by, e.g., group and depth dimensions. Thus, index tensor610may be, e.g., a NumGroups×1×1×Dout×Cout tensor, where NumGroups is a number of convolution groups, Dout is a surface depth (in planes) and Cout is a number of output channels per group. Index tensor610may be also broadcasted in Z (depth) dimension or C (channel) dimension, as defined and controlled by corresponding values of indexing mode bits618. Additionally or alternatively, a transpose operation (e.g., width-to-channel transpose operation) may be applied to index tensor610resulting into, e.g., a NumGroups×Cout×1×Dout×1 tensor, as defined and controlled by corresponding values of indexing mode bits618. Broadcasting and/or transpose of source surface616fetched from buffer memory334may occur after indexing, e.g., at formatting circuit338. Thus, if the source broadcasting bits of indexing mode bits618also enable source broadcasting in Y (height) dimension, then source surface616fetched from buffer memory334would have Hin copies of elements of the source tensor at y=Val coordinate, where Val is the previously defined offset value.

As aforementioned, indexing mode bits618may control various indexing modes and indexing operations. Indexing mode bits618may indicate an axis (dimension) of the source tensor on which to apply an indexing offset. Also, indexing mode bits618may be used to disable indexing. Indexing mode bits618may further enable broadcasting of index tensor610in the Z (depth) dimension, or may enable broadcasting of index tensor610in the C (channel) dimension. Indexing mode bits618may also enable vector transpose applied on index tensor610, e.g., conversion from a channel vector to a width vector. Additionally or alternatively, indexing mode bits618may set a maximum value of the indexing offset (e.g., represented with 16 bits).

Index broadcasting may set an index component in index tensor610(e.g., five-dimensional tuple I) for a specific axis to 0. When indexing mode bits618corresponding to broadcasting in C and Z dimensions are set to 0, index tensor fetching circuit606may fetch an index component from I[g, z, 0, 0, c], where g is an index component for a group dimension, z is an index component for a depth dimension and c is an index component for a channel dimension. Setting indexing mode bits618corresponding to broadcasting in C and Z dimensions to 1 causes index tensor fetching circuit606to fetch an index component from I[g, 0, 0, 0, 0]. Thus, the extent of index tensor610may be reduced in the broadcasted dimension(s) to one. The X (width) and Y (height) axes of index tensor610may be implicitly broadcasted.

Index tensor fetching circuit606may fetch non-broadcasted index components of index tensor610along a back-projected input dimension, with g=0, 1, . . . , NumGroups-1, z=0, 1, . . . , Din−1 and c=0, 1, . . . , Cin−1. If the fetched portion of source tensor (e.g., source surface616) is itself broadcasted (e.g., if indexing mode bits618corresponding to source broadcasting along C or Z dimension are set), then Din or Cin may be reduced to one, and the extent of index tensor610in that dimension is reduced to one. Setting the source broadcasting (e.g., by the source broadcasting bits of indexing mode bits618) causes that a single index component614from index tensor610is generated and replicated for fetching source surface616. Setting the index broadcasting (e.g., by the index broadcasting bits of indexing mode bits618) causes choosing whether a single index component614from index tensor610is going to be used as an origin of a slice of the source tensor in buffer memory334, or whether a different index component614of index tensor610for each row is fetched from buffer memory334. In the case of source broadcasting, one row of the source tensor may be fetched from buffer memory334as source surface616. Note that C and Z axes may be fully general, and can be configured for multiple indexing modes (e.g., index broadcasting, source broadcasting, and/or indirection). X and Y axes may be configured only for the index broadcasting mode. G (group) axis may possess neither source broadcasting control nor index broadcasting control, and this G axis may be configured only for the indirection mode of operation. G axis may be implicitly non-broadcasted (e.g., for both the source tensor and the index tensor610), although broadcasting can be simulated for either source tensor or index tensor610by explicitly setting indexing mode bits618corresponding to a group stride to 0. Setting the group stride to 0 may result into a normal source broadcasting.

Indexing along an index-broadcasted axis (e.g., X, Y, or optionally C or Z dimension) may shift a source range from x=0, 1, . . . , Win−1 by a value of Offset to x′=Offset, Offset+1, . . . , Offset+Win−1), where Offset is a smaller of the fetched index components (I[g, z, 0, 0, c]) or a maximum value of the indexing offset (MaxIndex). As aforementioned, the slicing may be required in X and Y axes, while the slicing may be optional for C and Z axes, and not available for G axis, whereas the result may be clamped to MaxIndex. In the case of indexing mode bits618defining source broadcast along X axis, source surface616fetched from buffer memory334may be reduced to x′=MaxIndex, MaxIndex+1, . . . MaxIndex+Win−1. MaxIndex may constrain the origin of the slice. If the fetched index component614in index tensor610was larger than MaxIndex, Offset may be clamped to MaxIndex and hence the slice would now become x′=MaxIndex, MaxIndex+1, . . . MaxIndex+Win−1. The extent of the underlying source tensor in the indexing axis may become Win′=Win+MaxIndex, assuming indexing along X axis is set by corresponding values of indexing mode bits618. The extent of the source tensor may become MaxIndex+Win since the origin of the slice is clamped to MaxIndex. However, the extent of the slice may remain Win.

Indexing along a non-index-broadcasted axis (e.g., G, or optionally C or Z dimension) may be specially-treated to cause an indirection for each component, e.g., making c′=I[g, z, 0, 0, c]. In the case of source broadcasting in C axis, this type of indexing may produce c′=I[g, z, 0, 0, 0], which is the same result as in the case of index broadcasting. The extent of the underlying source tensor in the indexing axis may become Cin′=MaxIndex+1, assuming indexing along C axis is set by corresponding values of indexing mode bits618.

Different indexing modes and indexing operations can be applied to different axes. While the index broadcasting may be implicitly set for the X and Y axes, the index broadcasting may be forbidden for the G axis. The index broadcasting may be configurable for the Z and C axes, e.g., based on corresponding values of indexing mode bits618. Similarly as for the index broadcasting, the source broadcasting may be forbidden for the G axis. The source broadcasting may be configurable for the Z, X, Y and C axes, e.g., based on corresponding values of indexing mode bits618. For each of C and Z axes, the type of indexing can be programmable, and the type of indirection can be indirection, slicing or broadcasting. For each of X and Y axes, the type of indexing can be broadcasting, and the type of indirection may be either slicing or broadcasting. For G axis, the type of indexing is non-broadcasting (e.g., indirection or slicing), and the type of indirection may be either indirection or broadcasting, e.g., if the group stride equals zero.

Planar engine340may support unary indexed operations. If indexing is enabled for a unary operation at planar engine340or for a unary reduction operation at planar engine340, a first source may be fetched from buffer memory334as a portion of input data342using an indexing operation performed by indexing circuit336. Registers in buffer memory334storing the first source may be resident or cached. Registers in buffer memory334storing a second source are resident and may be used for index components of index tensor610. If index tensor610in buffer memory334is produced by a previous operation of planar engine340as output data342that are written back into buffer memory334, then an alias may be used to enforce serialization between that previous operation and a next operation of planar engine340that uses index components of index tensor610to fetch input data344from buffer memory334.

Alternatively or additionally, planar engine340may support binary indexed operations. If indexing is enabled for a binary operation at planar engine340or for a binary reduction operation at planar engine340, a first source (Src1) may be fetched from buffer memory334as source surface616using an indexing operation performed by indexing circuit336to become a portion of input data342passed onto planar engine340. A second source (Src2) may be fetched from buffer memory334as source surface616without an indexing operation, except that the second source may use addressing registers of the first source. In other words, the binary indexed operation may become Src1[Src2] OP Src1, where the first source is offset by index tensor610, but the second source is not offset by index tensor610. Each individual source may be associated with its own source broadcasting bits that may be part of, e.g., indexing mode bits618.

In the case of binary indexed operations performed at planar engine340, the addressing information may be shared for the two sources. A binary operation with indexing at planar engine340may be at least a three-source operation, e.g., a binary add between an indexed first source and a non-indexed second source: Src1[Idx[y]]+Src2[y], where Idx[y] is a corresponding index component614in index tensor610. Thus, the binary operation with indexing may require three sources from buffer memory334—the two sources Src1, Src2, and the index tensor Idx. In the case of two-port buffer memory334, a binary operation with indexing may be instead implemented as, e.g., Src1[Idx[y]]+Src1[y] by sharing base pointers between the first source Src1 and the second source Src2. Alternatively or additionally, a binary operation with indexing may be implemented by utilizing indexing on both first and second sources, which would be a four-source operation, e.g., Src1[Idx1[y]]+Src2[Idx2[y]], where Idx1 is index tensor610for a first source Src1, Idx1[y] is a corresponding index component614in index tensor610for the first source, Idx2 is index tensor610for a second source Src1, and Idx2[y] is a corresponding index component614in index tensor610for the second source.

Example Processes at Neural Engine Architecture

FIG.7is a flowchart illustrating a method of performing an indexing operation in a neural processor circuit, according to one embodiment. The neural processor circuit operates702at least one of neural engine circuits (e.g., at least one neural engine314) in the neural processor circuit to perform a convolution operation on input data (e.g., input data322) to generate output data (e.g., output data328).

The neural processor circuit stores704an index tensor and the output data as a source tensor in a buffer memory (e.g., buffer memory334) of a data processor circuit (e.g., data processor circuit318) directly coupled to the at least one neural engine circuit. The index tensor may be generated by a planar engine circuit (e.g., planar engine340) as a result of a reduction operation applied on at least a portion of the input data.

The neural processor circuit fetches706, by an indexing circuit (e.g., indexing circuit336) of the data processor circuit coupled to the buffer memory, a portion of the source tensor from the buffer memory by referencing the index tensor representing indexing information into the portion of the source tensor. In one or more embodiments, the neural processor circuit fetches, via the indexing circuit, elements of the source tensor along a dimension of the source tensor using a corresponding value in the index tensor. In one or more other embodiments, the neural processor circuit fetches, via the indexing circuit, a slice of the source tensor along a dimension of the source tensor starting from an offset value obtained from the index tensor, the slice being of a size that fits into the buffer memory.

Embodiments of the process as described above with reference toFIG.7are merely illustrative. Moreover, sequence of the process may be modified or omitted.