Device

A one-chip igniter is formed by a convenient manufacturing process and at a low cost. A device to switch a power semiconductor switch is provided, the device comprising a first semiconductor switch which is turned on or turned off in response to a first control signal input to a gate and, if turned on, provides a high voltage to a gate of the power semiconductor switch, and a voltage boosting circuit which boosts a voltage of the first control signal that turns the first semiconductor switch on. As one example, the voltage boosting circuit boosts a voltage of the first control signal which turns the first semiconductor switch on to a higher voltage than a high voltage.

The contents of the following Japanese patent application are incorporated herein by reference:

BACKGROUND

1. Technical Field

The present invention relates to a device.

2. Related Art

Conventionally, a semiconductor device used for ignition of an internal combustion engine and the like has been formed as a one-chip igniter by integrating a power semiconductor device which handles a large power with an integrated circuit of a CMOS (Complementary Metal Oxide Semiconductor) circuit (for example, refer to Patent Documents 1 to 3).Patent Document 1: Japanese Patent Application Publication No. 2002-9602Patent Document 2: Japanese Patent Application Publication No. 2000-299927Patent Document 3: Japanese Unexamined Patent Application Publication No. 2014-522612

However, when forming such a one-chip igniter, different types of transistor elements such as an N channel MOS FET (Field Effect Transistor) and a P channel MOS FET on a semiconductor substrate are to be performed, a manufacturing process has become complicated and also, the cost has been increased. Therefore, it has been desired to form a one-chip igniter by a convenient manufacturing process and at a low cost.

SUMMARY

Accordingly, in one aspect of a technical innovation included in the present specification, a purpose is to provide a device which can solve the above-described problem. This purpose can be achieved by a combination of features described in claims. That is, in a first embodiment of the present invention, a device to switch a power semiconductor switch is provided, the device comprising a first semiconductor switch which is turned on or turned off in response to a first control signal input to a gate and, if turned on, provides a high voltage to a gate of the power semiconductor switch, and a voltage boosting circuit which boosts a voltage of the first control signal that turns the first semiconductor switch on.

It should be noted that the above-described invention summary clause does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a sub-combination of the features described above.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, some embodiments of the present invention will be described. The embodiments for the invention do not limit the invention according to the claims, and all the combinations of the features described in the embodiments are not necessarily essential to solving means provided by aspects of the invention.

FIG. 1shows a configurational example of the ignition device1000according to the present embodiment. The ignition device1000ignites an ignition plug used in such as an internal combustion engine of an automobile and the like. In the present embodiment, an example of the ignition device1000equipped on an engine of an automobile will be described. The ignition device1000comprises a control signal generating section10, an ignition plug20, an ignition coil30, a power source40, a power semiconductor switch50and a device100.

The control signal generating section10generates and supplies to the device100a switching control signal that controls an ON/OFF switching of the power semiconductor switch50. The control signal generating section10is, for example, one part of or the whole engine control unit (ECU) of an automobile where the ignition device1000is equipped. The control signal generating section10supplies the switching control signal to the device100; thereby, the ignition device1000starts an igniting operation of the ignition plug20.

The ignition plug20electrically generates sparks by discharge. The ignition plug20may be arranged in the internal combustion engine; in this case, the ignition plug20ignites a combustion gas such as a mixed gas in a combustion chamber. For example, the ignition plug20is arranged in a through hole which penetrates from the outside of the cylinder to a combustion chamber inside a cylinder and is fixed so as to seal the through hole. In this case, one end of the ignition plug20is exposed to the inside of the combustion chamber and the other end receives an electrical signal from the outside of the cylinder.

The ignition coil30supplies the electrical signal to the ignition plug. The ignition coil30supplies a high voltage that discharges the ignition plug20as the electrical signal. The ignition coil30may function as a transformer, for example, being an ignition coil having a primary coil32and a secondary coil34. The primary coil32and the secondary coil34are electrically connected to each other by one end of the primary coil32and one end of the secondary coil34. The primary coil32has the number of turns of winding not greater than that of the secondary coil34, and shares a core with the secondary coil34. The secondary coil34generates an electromotive force (a mutual induced electromotive force) in response to an electromotive force generated at the primary coil32. The secondary coil34is connected to the ignition plug20at the other end and supplies the generated electromotive force to the ignition plug20to discharge the ignition plug20.

The power source40supplies a voltage to the ignition coil30. For example, the power source40supplies a predetermined constant voltage to one end of the primary coil32and one end of the secondary coil34.

The power semiconductor switch50switches between conduction and non-conduction between the other end of the primary coil32of the ignition coil30and a reference potential, and generates an electromotive force (a self-induced electromotive force) to the primary coil32. For example, the power semiconductor switch50electrically connects the primary coil32and the reference potential in response to an ON voltage provided from the device100and makes non-conduction between the primary coil32and the reference potential in response to an OFF voltage provided from the device100. As one example, the power semiconductor switch50is an insulated gate bipolar transistor (IGBT). In this case, the device100is to provide a gate voltage to the power semiconductor switch50.

The device100switches the power semiconductor switch50on or off. The device100has an input terminal102, an output terminal104, a reference potential terminal106, a drive circuit110, a diagnosis circuit120and a resistor130. The input terminal102is connected to the control signal generating section10, the output terminal104is connected to the power semiconductor switch50, and the reference potential terminal106is connected to the reference potential. Here, the reference potential may be a reference potential in a control system of an automobile, or may be a reference potential corresponding to the device100within the automobile. The reference potential may also be a low voltage that turns the power semiconductor switch50off, and, as one example, is 0V.

The drive circuit110provides either an ON voltage or an OFF voltage to the power semiconductor switch50. For example, the drive circuit110supplies the ON voltage to the power semiconductor switch50in response to the high voltage of the switching control signal input from the control signal generating section10. Also, the drive circuit110provides the OFF voltage to the power semiconductor switch50in response to the low voltage of the switching control signal. Also, the drive circuit110may provide the OFF voltage to the power semiconductor switch50in response to the OFF voltage received from the diagnosis circuit120. The drive circuit110includes an NAND circuit112, a first semiconductor switch114and a second semiconductor switch116.

The NAND circuit112executes NAND to output the low voltage when two input signals are at the high voltage and to output the high voltage when at least one of the two input signals is at the low voltage.FIG. 1shows an example that the NAND circuit112inputs the switching control signal input from the input terminal102as one input signal and inputs an output signal of the diagnosis circuit120as the other input signal. The NAND circuit112supplies the output signals corresponding to the two input signals as control signals for the first semiconductor switch114and the second semiconductor switch116.

The first semiconductor switch114switches between being electrically connect or not between the input terminal102and the output terminal104in response to the control signals received from the NAND circuit112.FIG. 1shows an example that the first semiconductor switch114is configured with a PMOS transistor which forms a P type channel (a majority carrier, that is, a hole). In this case, the first semiconductor switch114has a collector terminal connected to the input terminal102and an emitter terminal connected to the output terminal104via the resistor130, and electrically connects (disconnects) the input terminal102and the output terminal104in response to a low voltage (a high voltage) input to the gate.

The second semiconductor switch116is switched ON or OFF in response to the control signal received from the NAND circuit112.FIG. 1shows an example that the second semiconductor switch116is configured with an NMOS transistor which forms an N type channel (that is, an electron). In this case, the second semiconductor switch116has a collector terminal connected to the emitter terminal of the first semiconductor switch114and an emitter terminal connected to the reference potential terminal106via the diagnosis circuit120, and electrically disconnects (connects) between the emitter terminal of the first semiconductor switch114and the reference potential terminal106in response to a low voltage (a high voltage) input to the gate.

That is, the second semiconductor switch116is turned on or turned off in response to the control signal input to the gate and is turned off (on) if the first semiconductor switch114is turned on (off). In this way, in response to a condition that the control signal is at the high voltage, the first semiconductor switch114is switched on and the second semiconductor switch116is switched off respectively, and the drive circuit110provides the high voltage of the switching control signal to the gate of the power semiconductor switch50. Also, in response to a condition that the control signal is at the low voltage, the first semiconductor switch114is switched off and, also, the second semiconductor switch116is switched on respectively, and the drive circuit110provides the low voltage of the reference potential to the gate of the power semiconductor switch50.

The diagnosis circuit120diagnoses the switching control signal input to the input terminal102and turns the power semiconductor switch50off in response to a condition that the diagnosis result is abnormal. Also, when turning the power semiconductor switch50off, the diagnosis circuit120gradually decreases a collector current of the power semiconductor switch50to the extent without generating at the secondary coil34any electromotive force that discharges the ignition plug20. The diagnosis circuit120includes an interruption circuit122, a third semiconductor switch124and a resistor126.

The interruption circuit122detects a continuation period of time of a high voltage of the switching control signal, and when the high voltage is switched to an OFF voltage in the continuation period of time which is not greater than a reference period of time or a predetermined period of time, the interruption circuit122diagnoses that the switching control signal is normal and continues the operation of the drive circuit110. For example, when the diagnosis result of the interruption circuit122is normal, the interrupting circuit122provides the high voltage as the other input signal of the NAND circuit112. Accordingly, when the switching control signal being one input signal is at the high voltage (the low voltage, the NAND circuit112outputs the low voltage (the high voltage). That is, when the switching control signal is diagnosed with normality, the interruption circuit122makes the drive circuit110execute an operation of turning the power semiconductor switch50on or off in response to the switching control signal.

Also, the interruption circuit122detects the continuation period of time of the high voltage of the switching control signal and diagnoses that the switching control signal is abnormal in response to a condition that the high voltage continues for a period of time exceeding the reference period of time or the predetermined period of time. For example, when the diagnosis result of the interruption circuit122is abnormal, the interrupting circuit122provides the low voltage as the other input signal of the NAND circuit112. Accordingly, since the NAND circuit112outputs the high voltage even if the switching control signal being one input signal is at either the high voltage or the low voltage, the interruption circuit122can turn the power semiconductor switch50off. Also, the interruption circuit122provides to the third semiconductor switch124the high voltage and the low voltage corresponding to the diagnosis result. It should be noted that the interruption circuit122includes an NOT circuit at a final stage, as one example.

The third semiconductor switch124is switched on or off in response to the ON voltage and the OFF voltage received from the interruption circuit122.FIG. 1shows an example that the third semiconductor switch124is configured with an NMOS transistor. In this case, the third semiconductor switch124has a collector terminal connected to the emitter terminal of the second semiconductor switch116and an emitter terminal connected to the reference potential terminal106, and electrically disconnects (connects) the emitter terminal of the second semiconductor switch116and the reference potential terminal106in response to the low voltage (the high voltage) input to the gate.

That is, when the diagnosis result of the interruption circuit122is normal, the third semiconductor switch124receives the high voltage from the interrupting circuit122and electrically connects the emitter terminal of the second semiconductor switch116and the reference potential terminal106. Accordingly, when the diagnosis result is normal, the third semiconductor switch124makes the drive circuit110execute the operation corresponding to the switching control signal.

Also, when the diagnosis result of the interruption circuit122is abnormal, the third semiconductor switch124receives the low voltage from the interrupting circuit122and electrically disconnects the emitter terminal of the second semiconductor switch116and the reference potential terminal106. Accordingly, even if the interruption circuit122turns the power semiconductor switch50off in response to a condition that the diagnosis result is abnormal, the third semiconductor switch124prevents the charges of the gate of the power semiconductor switch50from directly passing toward the reference potential via the second semiconductor switch116.

The resistor126is connected to the output terminal104at one end via the resistor130and is connected to the reference potential terminal106at the other end. That is, when the interruption circuit122turns the power semiconductor switch50off, the resistor126makes the charges accumulated in the gate of the power semiconductor switch50flow toward the reference potential via the resistor130. Here, the charges accumulated in the gate of the power semiconductor switch50flow toward the reference potential with a time constant which is determined by a gate capacity of the power semiconductor switch50and the resistor126and the resistor130.

It should be noted that if the charges suddenly flow, an electromotive force is generated at the secondary coil34to discharge the ignition plug20; therefore, the resistor126has a resistor value equal to or higher than a predetermined value and makes the charges flow gradually with a time constant to the extent that prevents the ignition plug20from discharging. In this way, the resistor126makes the charges accumulated in the gate of the power semiconductor switch50flow gradually toward the reference potential to gradually transit the power semiconductor switch50to the OFF state.

The resistor130is connected to the emitter terminal of the first semiconductor switch114at one end and is connected to the output terminal104at the other end. The resistor130has a lower resistor value than that of the resistor126. The resistor130provides the ON voltage from the first semiconductor switch114to the gate of the power semiconductor switch50when transiting the power semiconductor switch50to the ON state.

Also, when transiting the power semiconductor switch50to the OFF state, the resistor30makes the charges accumulated in the gate of the power semiconductor switch50flow toward the reference potential. When the second semiconductor switch116and the third semiconductor switch124are in the ON state, the resistor130makes the charges flow immediately toward the reference potential and generates at the secondary coil34the electromotive force that discharges the ignition plug20. Also, when the second semiconductor switch116and the third semiconductor switch124are in the OFF state, the resistor130makes the charges flow toward the reference potential via the resistor126.

The device100according to the present embodiment above provides either an ON voltage or an OFF voltage appropriate for the power semiconductor switch50from the output terminal104to the power semiconductor switch50in response to the switching control signal input from the input terminal102. Operations of the ignition device1000comprising such a device100will be described next.

FIG. 2shows one example of operation waveforms of the ignition device1000according to the present embodiment. InFIG. 2, a horizontal axis indicates a period of time and a longitudinal axis indicates a voltage value or a current value. InFIG. 2, a waveform indicated as Vin shows the switching control signal output by the control signal generating section10.FIG. 2shows an example that the switching control signal Vin has two normal operation waveforms indicated as “normal” and has an abnormal operation waveform indicated as “ON fixed” between the two normal operation waveforms.

Also,FIG. 2shows one example of time waveforms of a gate voltage indicated as Vg, a collector current indicated as Ic and a collector voltage indicated as Vc, of the power semiconductor switch50respectively. Also,FIG. 2shows one example of time waveforms of an input voltage of an NOT circuit indicated as “interruption output” and an output voltage of the NOT circuit indicated as “NOT output” respectively, when the interruption circuit122includes the NOT circuit (an inverter circuit) at an output stage. Also,FIG. 2shows one example of time waveforms of an output voltage of the NAND circuit112indicated as NAND, ON and OFF states of the first semiconductor switch114indicated as M1, ON and OFF states of the second semiconductor switch116indicated as M2, and ON and OFF states of the third semiconductor switch124indicated as M3respectively.

When the switching control signal Vin turns to the high voltage and is in a range of normal operation, the output (NOT output) of the interruption circuit122is at the high voltage and the third semiconductor switch124receiving the high voltage turns to the ON state. Also, the NAND circuit112that receives the high voltage of the switching control signal Vin and the high voltage of the interruption circuit122outputs the low voltage. Also, by the low voltage of the NAND circuit112, the first semiconductor switch114turns to the ON state and the second semiconductor switch116turns to the OFF state.

Accordingly, the ON voltage is provided to the gate of the power semiconductor switch50and the collector current Ic flows from the power source40via the primary coil32of the ignition coil30. It should be noted that a time change dIc/dt of the collector current Ic is determined in response to an inductance of the primary coil32and the providing voltage of the power source40and is increased to a predetermined (or preset) current value. For example, the collector current Ic is increased approximately to several A, a dozen of A or several tens of A.

Then, if the switching control signal Vin turns to the low voltage, the NAND circuit112outputs the high voltage. By the high voltage of the NAND circuit112, the first semiconductor switch114turns to the OFF state and the second semiconductor switch116turns to the ON state. That is, the gate of the power semiconductor switch50is provided with the OFF voltage, and the charges accumulated in the gate of the power semiconductor switch50flow to the reference potential via the second semiconductor switch116and the third semiconductor switch124; thereby, the collector current Ic is drastically decreased.

By the drastic decrease of the collector current Ic, a both-end voltage of the primary coil32is drastically increased by a self-induced electromotive force, and generates an induced electromotive force of about several tens of kV at a both-end voltage of the secondary coil34. The ignition device1000discharges the ignition plug20to ignite the combustion gas by providing such a voltage of the secondary coil34to the ignition plug20. As the above, the device100according to the present embodiment can provide an appropriate ON voltage and OFF voltage to the power semiconductor switch50in response to the switching control signal input from the input terminal102, and the ignition device1000can execute the igniting operation of the ignition plug20by the switching control signal diagnosed with the normal operation.

On the other hand, if the switching control signal Vin does not switch to the low voltage and the high voltage is continued, the ON voltage is continuously provided to the gate of the power semiconductor switch50and the collector current Ic is further increased. Depending on the power semiconductor switch50, the collector current Ic is increased to a saturated region in some cases. The operation waveforms ofFIG. 2show an example that the saturation occurred. Then, if the high voltage of the switching control signal Vin continues for a period of time exceeding the reference period of time, the interruption circuit122diagnoses that the switching control signal is abnormal and outputs the low voltage (NOT output).

Accordingly, the NAND circuit112that receives the high voltage of the switching control signal Vin and the low voltage of the interruption circuit122outputs the high voltage. By the high voltage of the NAND circuit112, the first semiconductor switch114turns to the OFF state and the second semiconductor switch116turns to the ON state. Also, the third semiconductor switch124that receives the low voltage of the interruption circuit122turns to the OFF state. That is, the OFF voltage is provided to the gate of the power semiconductor switch50and the charges accumulated in the gate of the power semiconductor switch50flow to the reference potential via the resistor130and the resistor126; thereby, the collector current Ic is gradually decreased.

Therefore, when the switching control signal is diagnosed with the abnormality, the device100according to the present embodiment can gradually decrease the collector current Ic to prevent the ignition plug20from discharging even if the collector current Ic is increased to the extent of saturation. That is, the device100can provide an appropriate ON voltage and OFF voltage to the power semiconductor switch50in response to the switching control signal input from the input terminal102, and the ignition device1000can stop the igniting operation of the ignition plug20by the switching control signal diagnosed with the abnormal operation.

As the above, an example has been described that the device100according to the present embodiment described has the first semiconductor switch114which is the PMOS transistor and the second semiconductor switch116and the third semiconductor switch124which are the NMOS transistors. Alternatively, the device100operates in principle even if having the first semiconductor switch114which is the NMOS transistor and the second semiconductor switch116and the third semiconductor switch124which are the PMOS transistors.

However, in any of the configurations, since the different types of transistors are included, in a case where the device100is to be made as one chip, the manufacturing process becomes complicated and the cost becomes increased. Also, for example, in the device100, if using a plurality of transistors of the same type only, the ON voltage is decreased by the threshold voltages of the transistors and it becomes difficult to provide an appropriate ON voltage to the power semiconductor switch50.

Accordingly, a device200according to the present embodiment executes the similar operation to the operation of the device100described inFIG. 1andFIG. 2by having a voltage boosting circuit and a plurality of transistors of the same type. An ignition device2000comprising such a device200will be described by usingFIG. 3.

FIG. 3shows a configurational example of the ignition device2000according to the present embodiment. In the ignition device2000shown inFIG. 3, the same reference signs are given to approximately the same operations as that of the ignition device1000according to the present embodiment shown inFIG. 1and the description is omitted. The ignition device2000comprises a control signal generating section10, an ignition plug20, an ignition coil30, a power source40, a power semiconductor switch50and a device200. It should be noted that the descriptions for the control signal generating section10, the ignition plug20, the ignition coil30, the power source40and the power semiconductor switch50are omitted.

The device200switches the power semiconductor switch50on or off. The device200has an input terminal202, an output terminal204, a reference potential terminal206, a drive circuit210and a diagnosis circuit220. The input terminal202is connected to the control signal generating section10, the output terminal204is connected to the power semiconductor switch50, and the reference potential terminal206is connected to the reference potential.

The drive circuit210provides either an ON voltage or an OFF voltage to the power semiconductor switch50. For example, the drive circuit210provides the ON voltage to the power semiconductor switch50in response to the high voltage of the switching control signal input from the control signal generating section10. Also, the drive circuit210provides the OFF voltage to the power semiconductor switch50in response to the low voltage of the switching control signal. Also, the drive circuit210may also provide the OFF voltage to the power semiconductor switch50in response to the OFF voltage received from the diagnosis circuit220. The drive circuit210includes an NAND circuit212, a first semiconductor switch214, a second semiconductor switch216, a voltage boosting circuit230, a control circuit240and a diode250.

The NAND circuit212executes NAND to output the low voltage when two input signals are at the high voltage and to output the high voltage when at least one of the two input signals is at the L low voltage.FIG. 3shows an example that the NAND circuit212inputs the switching control signal input from the input terminal202as one input signal and inputs an output signal of the diagnosis circuit220as the other input signal. The NAND circuit212supplies the output signals corresponding to the two input signals as the control signals for the first semiconductor switch214and the second semiconductor switch216.

The first semiconductor switch214switches between being electrically connect or not between the input terminal202and the output terminal204in response to the first control signal received from the control circuit240. Here, the first control signal is the signal resulting from processing by the control circuit240the control signal to the first semiconductor switch214that the NAND circuit212outputs. It should be noted that, as one example, a logical value of the first control signal is a logical value resulting from inverting a logical value of the control signals that the NAND circuit212outputs.

FIG. 3shows an example that the first semiconductor switch214is configured with an NMOS transistor (NMOS semiconductor switch). In this case, the first semiconductor switch214has a collector terminal connected to the input terminal202and an emitter terminal connected to the output terminal204and electrically connects (disconnects) the input terminal202and the output terminal204in response to the high voltage (the low voltage) input to the gate. That is, the first semiconductor switch214is turned on or turned off in response to the first control signal input to the gate and, if turned on, provides the high voltage to the gate of the power semiconductor switch50.

The second semiconductor switch216is switched on or off in response to the second control signal received from the NAND circuit212. Here, the control signal to the second semiconductor switch216that the NAND circuit212outputs is the second control signal.FIG. 3shows an example that the second semiconductor switch216is configured with an NMOS transistor.

In this case, the second semiconductor switch216has a collector terminal connected to the emitter terminal of the first semiconductor switch214and an emitter terminal connected to the reference potential terminal206via the diagnosis circuit220and electrically disconnects (connects) between the emitter terminal of the first semiconductor switch214and the reference potential terminal206in response to the low voltage (the high voltage) input to the gate. That is, the second semiconductor switch216is turned on or off in response to the second control signal input to the gate and, if turned on, provides the low voltage to the gate of the power semiconductor switch50.

The voltage boosting circuit230boosts the voltage of the first control signal that turns the first semiconductor switch214on.FIG. 3shows an example that the voltage boosting circuit230is connected to the input terminal202where the switching control signal is input and boosts the high voltage input from the input terminal202. For example, the voltage boosting circuit230boosts the voltage of the first control signal that turns the first semiconductor switch214on to a higher voltage than the high voltage provided to the power semiconductor switch50. As one example, the voltage boosting circuit230boosts to a high voltage equal to or higher than a voltage resulting from adding the threshold voltage of the first semiconductor switch214to the high voltage of the switching control signal. As one example, the voltage boosting circuit230supplies the signal with the boosted voltage as the power source voltage of the control circuit240and boosts the voltage of the first control signal being an output of the control circuit240.

The control circuit240supplies the first control signal with the boosted voltage by the voltage boosting circuit230to the first semiconductor switch214in response to a condition that the switching control signal which controls switching of the power semiconductor switch50turns to the high voltage. The control circuit240supplies the first control signal to the first semiconductor switch214in response to the second control signal received from the NAND circuit212. Here, as one example, the control circuit240receives the high voltage of the switching control signal with the boosted voltage from the voltage boosting circuit230as the power source voltage and outputs the first control signal of an amplitude value corresponding to the voltage value of the power source voltage. The control circuit240includes a first logical inversion element242.

The first logical inversion element242inverts the logical value of the second control signal to output the first control signal. That is, the first logical inversion element242has a logical value resulting from inverting the logical value of the second control signal that the NAND circuit212outputs and supplies the control signal whose high voltage is boosted to be higher than the high voltage of the switching control signal to the first semiconductor switch214as the first control signal. For example, the first logical inversion element242outputs the high voltage boosted by the voltage boosting circuit230as the first control signal in response to a condition that the second control signal at the low voltage is input.

In this way, the control circuit240provides, to the gate of the first semiconductor switch214, the high voltage voltage-boosted to a high voltage that is equal to or higher than the voltage resulting from adding the threshold voltage of the first semiconductor switch214to the high voltage of the switching control signal. Therefore, even if the first semiconductor switch214is the NMOS transistor, since the voltage-boosted high voltage is provided to the gate of the first semiconductor switch214, the drive circuit210can switch the first semiconductor switch214to the ON state. Then, since the logical value of the first control signal is the logical value resulting from inverting the logical value of the second control signal, the second semiconductor switch216is turned on or turned off in response to the control signal input to the gate, and is turned off (on) if the first semiconductor switch214is turned on (off).

That is, similar to the device100described inFIG. 1, in response to a condition that the first control signal turns to the high voltage, the first semiconductor switch214is turned on and, also, the second semiconductor switch216is turned off, and the drive circuit210can provide the high voltage of the switching control signal to the gate of the power semiconductor switch50. Also, in response to a condition that the first control signal turns to the low voltage, the first semiconductor switch214is switched off and the second semiconductor switch216is switched on respectively, and the drive circuit210can provide the low voltage of the reference potential to the gate of the power semiconductor switch50.

When the power semiconductor switch50transits to the OFF state, the diode250makes the charges accumulated in the gate of the power semiconductor switch50flow toward the outside.FIG. 3shows an example that the diode250is connected to the input terminal202at one end and is connected to the output terminal204at the other end. The diode250makes the charges flow toward the control signal generating section10and/or the diagnosis circuit220under a condition that the power semiconductor switch50turns to the OFF state and the gate voltage of the power semiconductor switch50becomes equal to or higher than the threshold voltage of the diode250. For example, if the charges are excessively accumulated in the gate of the power semiconductor switch50, the diode250makes some of the accumulated charges flow toward the outside to adjust the current rate flowing from the gate.

Similar to the diagnosis circuit120described inFIG. 1, the diagnosis circuit220diagnoses the switching control signal input to the input terminal202and supplies to the power semiconductor switch50the OFF voltage to turn the power semiconductor switch50OFF in response to a condition that the diagnosis result is abnormal. The description for the operation of the diagnosis circuit220is omitted since it has been described inFIG. 1. The diagnosis circuit220includes an interruption circuit222, a third semiconductor switch224and a resistor226.

The interruption circuit222turns the power semiconductor switch50OFF when the switching control signal which controls switching of the power semiconductor switch50is a logical value which indicates that the power semiconductor switch50is turned on for a period of time until the reference period elapses. That is, the interruption circuit222, the third semiconductor switch224and the resistor226perform the similar operations to those of the interruption circuit122, the third semiconductor switch124and the resistor126described inFIG. 1; thereby, the descriptions for them are omitted.

The device200according to the present embodiment above provides either an ON voltage or an OFF voltage appropriate for the power semiconductor switch50from the output terminal204to the power semiconductor switch50in response to the switching control signal input from the input terminal202. Further, a more specific configurational example of the voltage boosting circuit230that the drive circuit210has and the interruption circuit222that the diagnosis circuit220has will be shown next.

FIG. 4shows a configurational example of the voltage boosting circuit230according to the present embodiment. The voltage boosting circuit230has an oscillator300and a charge pump circuit400. The oscillator300oscillates at a predetermined frequency and outputs an oscillated frequency signal. As one example, the oscillator300is a ring oscillator connecting an odd number of inverter circuits in a ring shape.FIG. 4shows an example of a ring oscillator connecting an inverter circuit312, an inverter circuit314and an inverter circuit316in a ring shape.

In the oscillator300as shown inFIG. 4, if a delay period of time for each stage at the inverter circuits is set as Td and the number of the inverter circuits is set as m, an oscillation cycle T is 2m*Td. Also, as one example, the oscillator300oscillates approximately the same amplitude value as that of the voltage value (the high voltage) of the input signal. Further,FIG. 4shows an example that a condenser322, a condenser324, condenser326and a condenser328are connected between the ring connection and the reference potential. In this way, a waveform of the frequency signal may also be adjusted to a shape near a sine wave by adding capacity components. The oscillator300supplies the generated frequency signal to the charge pump circuit400.

The charge pump circuit400boosts the voltage of the frequency signal received from the oscillator300, and boosts the voltage of the input signal based on the input signal. Here, an example will be described that the frequency signal received from the oscillator300repeats the high voltage in a first phase and the low voltage in a second phase, and the high voltage is input as the input signal. The charge pump circuit400has a first stage circuit including an inverter circuit410, a condenser412, a diode414, a diode416and a condenser418, and a second stage circuit including an inverter circuit420, a condenser422, a diode424, a diode426and a condenser428.

In the first phase, the inverter circuit410outputs the low voltage and the condenser412charges the high voltage input via the diode414. Then, in the second phase, since the inverter circuit410outputs the high voltage, the condenser412discharges a sum of the charged high voltage and the high voltage input via the diode414. In contrast to such a first stage circuit, the second stage circuit has operations in opposite phases. That is, in the second phase, the inverter circuit420outputs the low voltage and the condenser422charges the high voltage input via the diode424. Then, in the first phase, since the inverter circuit420outputs the high voltage, the condenser422discharges a sum of the charged high voltage and the high voltage input via the diode424.

Therefore, the charge pump circuit400outputs, respectively via the diode426, the sum of the high voltages of the first stage circuit in the first phase and the sum of the high voltages of the second stage circuit in the second phase. Accordingly, the charge pump circuit400can output signals at a voltage twice the high voltage. It should be noted that, more correctly, since the charge pump circuit400boosts voltages by using two diodes (for example, the diode414and the diode416), a voltage resulting from subtracting the threshold voltages of the two diodes is to be output. Therefore, as one example, if the high voltage is 5V and the threshold voltage of one diode is 0.7V, the above voltage boosting circuit230outputs a voltage of about 8.6V as a boosted voltage.

It should be noted thatFIG. 4merely shows one example of the voltage boosting circuit230and is not limited to this. For example, the oscillator300may also be another known circuit if it is a circuit that generates a frequency signal of a predetermined frequency. Also, the charge pump circuit400may also be another known circuit such as a circuit using a switch capacitor and the like, for example.

FIG. 5shows a configurational example of the interruption circuit222according to the present embodiment. The interruption circuit222has a voltage dividing resistor510, a voltage dividing resistor512, a second logical inversion element520, an interruption signal generating circuit530and an inverter circuit540. The voltage dividing resistor510and the voltage dividing resistor512divide voltages of voltage differences between the switching control signal and the reference voltage. Here, the reference voltage may be 0V, and in this case, the voltage dividing resistor510and the voltage dividing resistor512are to divide voltages of amplitude voltages of the switching control signal.

The second logical inversion element520outputs voltages resulting from logically inverting voltages that the voltage dividing resistor510and the voltage dividing resistor512output, where the switching control signal is used as the power source voltage. That is, in the second logical inversion element520, if the switching control signal is at a low voltage, since the power source voltage becomes the low voltage, the output voltage becomes 0V (the low voltage). Also, in the second logical inversion element520, if the switching control signal is at the high voltage, the output voltage becomes the high voltage under a condition that the voltages that the voltage dividing resistor510and the voltage dividing resistor512output are the low voltages. That is, for example, when the high voltage of the switching control signal is at a normal voltage level, resistor values of the voltage dividing resistor510and the voltage dividing resistor512adjust so as to output the divided voltages as the low voltages.

The interruption signal generating circuit530generates an interruption signal based on an elapsed period of time since the output of the second logical inversion element520turns to the high voltage. For example, the interruption signal generating circuit530generates the interruption signal when the elapsed period of time is beyond the predetermined period of time or the reference period of time. As one example, the interruption signal generating circuit530has a delay circuit.

The delay circuit outputs the interruption signal for turning the power semiconductor switch50off after the lapse of the reference period since the voltage that the second logical inversion element520outputs exceeds the threshold voltage (that is, becomes the high voltage). As one example, when the output signal of the second logical inversion element520and the signal that delayed the output of the second logical inversion element520for the reference period of time only are both at the high voltages if comparing the two signals, the delay circuit outputs the interruption signal for turning the power semiconductor switch50off. It should be noted that the interruption signal for turning the power semiconductor switch50off is at the high voltage, as one example.

The inverter circuit540outputs the voltage resulting from logically inverting the voltages of the output signal of the interruption signal generating circuit530. For example, the inverter circuit540outputs the high voltage when the interruption signal generating circuit530does not generate the interruption signal (a case of the low voltage). Also, the inverter circuit540outputs the low voltage when the interruption signal generating circuit530generates the interruption signal (a case of the high voltage).

Accordingly, the interruption circuit222can determine whether the switching control signal is normal or not (whether or not the high voltage changes to the low voltage before the lapse of the reference period) and can output the interruption signal for turning the power semiconductor switch50off if abnormal. It should be noted that the configuration of the interruption circuit222shown inFIG. 5is merely one example and is not limited to this. For example, the interruption circuit222may count the output of the oscillator300having the voltage boosting circuit230described inFIG. 4and detect the lapse of the reference period. Also, the interruption circuit222may also include a circuit combining a delay element, a latching circuit and the like.

Operations of the ignition device2000described above by usingFIGS. 3 to 5will be described next.FIG. 6shows one example of operation waveforms of the ignition device2000according to the present embodiment.

InFIG. 6, a horizontal axis indicates a period of time and a longitudinal axis indicates a voltage value or a current value. InFIG. 6, a waveform indicated as Vin shows the switching control signal that the control signal generating section10outputs.FIG. 6shows an example that the switching control signal Vin has two normal operation waveforms indicated as “normal” and has an abnormal operation waveform indicated as “ON fixed” between the two normal operation waveforms.

Also,FIG. 6shows one example of time waveforms of a gate voltage indicated as Vg, a collector current indicated as Ic and a collector voltage indicated as Vc of the power semiconductor switch50respectively. Also,FIG. 6shows one example of time waveforms of the first control signal that the first logical inversion element242supplies to the gate of the first semiconductor switch214indicated as “NOT1 output” respectively, and, when the interruption circuit222includes an NOT circuit at an output stage, an input voltage of the NOT circuit indicated as “interruption output” and an output voltage of the NOT circuit indicated as “NOT2 output”. Also,FIG. 6shows one example of time waveforms of an output voltage of the NAND circuit212indicated as NAND, ON and OFF states of the first semiconductor switch214indicated as M1, ON and OFF states of the second semiconductor switch216indicated as M2, and ON and OFF states of the third semiconductor switch224indicated as M3respectively.

When the switching control signal Vin turns to the high voltage and is in a range of normal operation, the output (NOT2 output) of the interruption circuit222is at the high voltage and the third semiconductor switch224which receives the high voltage turns to the ON state. Also, the NAND circuit212that receives the High voltage of the switching control signal Vin and the high voltage of the interruption circuit222outputs the low voltage. Also, by the low voltage of the NAND circuit112, the output (NOT1 output) of the first logical inversion element242turns to the high voltage. It should be noted that the high voltage of the first logical inversion element242is the voltage of the first control signal by the result that the voltage boosting circuit230boosted the voltage of the high voltage of the switching control signal; thereby, the first semiconductor switch114turns to the ON state. If the first semiconductor switch114is turned on, the first semiconductor switch114provides the high voltage of the switching control signal to the gate of the power semiconductor switch50. Also, the low voltage of the NAND circuit112is that of the second control signal, and the second semiconductor switch116turns to the OFF state.

According to the above, the ON voltage is provided to the gate of the power semiconductor switch50and the collector current Ic flows from the power source40via the primary coil32of the ignition coil30. It should be noted that a time change dIc/dt of the collector current Ic is determined in response to an inductance of the primary coil32and the providing voltage of the power source40and is increased to a predetermined (or preset) current value. For example, the collector current Ic is increased approximately to several A, a dozen of A or several tens of A.

Then, if the switching control signal Vin turns to the low voltage, the NAND circuit212outputs the high voltage. By the high voltage of the NAND circuit212, the output (NOT1 output) of the first logical inversion element242turns to the low voltage and the first semiconductor switch214turns to the OFF state. Also, the second semiconductor switch216turns to the ON state. That is, since the OFF voltage is provided to the gate of the power semiconductor switch50and the charges accumulated in the gate of the power semiconductor switch50flow to the reference potential via the second semiconductor switch216and the third semiconductor switch224, the collector current Ic is drastically decreased. It should be noted that if the charges accumulated in the gate of the power semiconductor switch50are excessive, the charges may also be discharged via the diode250.

Due to the drastic decrease of the collector current Ic, the both-end voltage of the primary coil32is drastically increased by the self-induced electromotive force and causes the induced electromotive force of about several tens of kV to be generated at the both-end voltage of the secondary coil34. The ignition device2000discharges the ignition plug20to ignite the combustion gas by providing such a voltage of the secondary coil34to the ignition plug20. As the above, the device200according to the present embodiment can provide an appropriate ON voltage and OFF voltage to the power semiconductor switch50in response to the switching control signal input from the input terminal202, and the ignition device2000can execute the igniting operation of the ignition plug20by the switching control signal diagnosed with the normal operation.

On the other hand, when the switching control signal Vin continues being at the high voltage without being switched to the low voltage, the ON voltage is continuously provided to the gate of the power semiconductor switch50and the collector current Ic is further increased. Depending on the power semiconductor switch50, the collector current Ic is increased to a saturated region in some cases. The operation waveforms inFIG. 6show an example that the saturation occurred. Then, if the high voltage of the switching control signal Vin continues for a period of time exceeding the reference period of time, the interruption circuit222diagnoses that the switching control signal is abnormal and outputs the low voltage (the NOT2 output).

Accordingly, the NAND circuit212that receives the high voltage of the switching control signal Vin and the low voltage of the interruption circuit222outputs the high voltage. By the high voltage of the NAND circuit212, the first semiconductor switch214turns to the OFF state and the second semiconductor switch216turns to the ON state. Also, the third semiconductor switch224that receives the low voltage of the interruption circuit222turns to the OFF state. That is, since the OFF voltage is provided to the gate of the power semiconductor switch50and the charges accumulated in the gate of the power semiconductor switch50flow to the reference potential via the resistor226, the collector current Ic is gradually decreased. It should be noted that if the charges accumulated in the gate of the power semiconductor switch50are excessive, the charges may also be discharged via the diode250.

Therefore, when the switching control signal is diagnosed with the abnormality, the device200according to the present embodiment can gradually decrease the collector current Ic to prevent the ignition plug20from discharging even if the collector current Ic is increased to the extent of saturation. That is, the device200can provide an appropriate ON voltage and OFF voltage to the power semiconductor switch50in response to the switching control signal input from the input terminal202, and the ignition device2000can stop the igniting operation of the ignition plug20by the switching control signal diagnosed with the abnormal operation.

The example that the device200according to the present embodiment above is a separate device from the power semiconductor switch50has described. Alternatively, the device200may also further comprise the power semiconductor switch50. The following shows a one-chip device in the device200, the one-chip device in which the power semiconductor switch50is integrated.

FIG. 7andFIG. 8show a configurational example of the one-chip device500according to the present embodiment.FIG. 7shows a plane view andFIG. 8shows one example of a cross-sectional view from an X-Y line ofFIG. 7.FIG. 7andFIG. 8describe an example that the power semiconductor switch50is IGBT of N channel type and the transistors configuring the device200are all NMOS transistors.

The power semiconductor switch50and the device200are formed within a semiconductor substrate where an n+buffer layer26and an n base layer27are sequentially formed epitaxially growing on a p+substrate25. A withstand voltage region18is arranged in a periphery surrounding an active region22where a main current of the power semiconductor switch50flows. The withstand voltage region18is arranged surrounding the active region22and the device200. The active region22includes a p base region6formed in a front surface layer of the n base layer27, an n+emitter region7formed in a front surface layer of the p base region6, an emitter electrode3connecting the p base region6and the n+emitter region7, a gate-insulating film13formed on a front surface of the p base region6between the n+emitter region7and the n base layer27, and a gate electrode14formed on the gate-insulating film13.

The device200comprises a p region9formed in the front surface layer of the n base layer27and a p region8surrounding the p region9and conductively connected to the emitter electrode3. The first semiconductor switch214, the second semiconductor switch216and the third semiconductor switch224which are configured with all NMOS transistors are arranged in a front surface layer of the p region9. Furthermore, the transistors which configure the NAND circuit212, the interruption circuit222, the voltage boosting circuit230and the control circuit240are all NMOS transistors (only one NMOS is described in the drawing). The diode250is formed of polysilicon which dopes impurities on an insulating film42formed on the p region9. An anode electrode and a cathode electrode are formed respectively on a p+region251and an n+region252. Although not shown in the drawing, a capacitor or resistor element configuring each circuit is also configured with polysilicon and the like on an insulating film formed on the p region9.

In this way, the device200is formed by a convenient manufacturing process and at a low cost and can function as a one-chip igniter.

As the above, the example that in the described device200according to the present embodiment any of the first semiconductor switch214, the second semiconductor switch216and the third semiconductor switch224is the NMOS transistor has been described. It should be noted that, alternatively, in the device200, any of the first semiconductor switch214, the second semiconductor switch216and the third semiconductor switch224may also be the PMOS transistor, and even if in this case, the device200operates in principle.