Sampling front-end for analog to digital converter

A sampling front-end for analog to digital converter is presented that shares a high speed N-bit ADC at front-end and interleaves the pipelined residue amplification with shared amplifier, which achieves high speed, low power and compact area with high density capacitive DAC structure.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a sampling front-end with capacitive digital to analog converter, and in particular, to a time-interleaved front-end for analog to digital converter.

2. Description of the Related Art

Low power consumption and high speed analog to digital converters (ADCs) are highly demanded for battery-powered mobile applications. For the application of high speed, the time-interleaved scheme is commonly used, which usually suffers from sampling mismatches between different channels. Furthermore, the capacitive DAC structure utilizes in the ADC also affect the speed of the conversion in each ADC channels. A good architecture of ADC front-end will facilitate the timing issue, and a well design capacitive DAC can enhance the conversion speed of each channel.

SUMMARY OF THE INVENTION

The present invention is directed to a sampling front-end for analog to digital converter. The sampling front-end includes an N-bit ADC, the number of i Time-Interleaved (TI) residue amplification units and an amplifier.

According to an embodiment of the invention, the N-bit ADC samples an analog input signal; converts the input signal into N-bit digit and generates the residue. The N-bit ADC is shared by i TI residue amplification units.

According to an embodiment of the invention, the residue amplification units hold the residue from N-bit ADC to the amplifier, which are interleaved to i channels.

According to an embodiment of the invention, the amplifier amplifies the residue from one of the residue amplification units to 2ndstage.

Accordingly, the present invention provides a sampling front-end for analog to digital converter having one N-bit ADC and one amplifier shared by i TI residue amplification units. Since the sampling front-end of N-bit ADC is shared by i residue amplification units, there exists no sampling mismatches. The time interleaving operation is performed only during the residue amplification, and the residues on the each residue amplification units are static. Thus, the timing mismatches are avoided.

According to the present invention, the capacitive digital-to-analog converter structure with low parasitic and high density layout structure can reduce the power and increase the speed of the conversion.

Further features and aspects of the present invention will become apparent from the following detailed description of embodiments with reference to the attached drawings.

DESCRIPTION OF THE EMBODIMENTS

Various exemplary embodiments, features, and aspects of the invention will be described in detail below with reference to the drawings. For the drawings below, the same or the similar numbers and symbols are referred to the same or the similar elements.

FIG. 1shows a schematic view of function block of a sampling front-end100according to an embodiment of the invention. Referring toFIG. 1, the sampling front-end100includes an N-bit ADC110, i TI residue amplification units RAC(1) to RAC(i)120(1)-120(i) and an amplifier130.

According to an embodiment of the invention, the N bit ADC unit110receives an input analog signal Vin; samples and shares the input analog signal Vin to the 1stresidue sampling unit RAC(1)120(1) via switch SC1. Then, the N bit ADC unit110converts the sampled input analog signal Vin into e.g. an N-bits digit and generates the residue voltage R1at output. Since the switch SC1keeps on during the conversion, the residue R1at the output of the N-bit ADC110is shared to the output of residue amplification unit120(1). Therefore, the residue R1can be also generated at the output of residue amplification unit120(1). After the conversion, the N-bit ADC unit110disconnects to residue amplification unit120(1) and connects to the 2ndresidue amplification unit120(2) via switch SC2to start a new sampling and conversion. In the meantime, the 1stresidue amplification unit120(1) connects to the amplifier130via switch SR1to amplify the residue R1to 2ndstage140. The previous operation repeats i times. In addition, since the number of i TI residue amplification units120(1)-120(i) share the same N-bit ADC110for the sampling, the time interleaved operation happens only in the residue amplification, the sampling mismatches are avoided.

The N-bit high speed ADC110can be a multi-bit per-cycle SAR ADC or an N-bit flash ADC. The architecture of the N-bit ADC110is prior art and we will not explain it deeply.

FIG. 2shows a further detailed schematic view of the sampling front-end100according to an embodiment of the invention. Referring toFIG. 2, a part of the N-bit ADC110is shown. The N-bit ADC110includes an N-bit DAC array210, a comparator220and a successive approximation register (SAR) controller230. The DAC array210includes a plurality of capacitors C0to Cnconnected in parallel. Only two of the TI residue amplification units120(1) to120(i) inFIG. 1are shown inFIG. 2. Each residue amplification unit120(1)/120(2) includes two capacitors (e.g. Ca1and Ca2in120(1) or Cb1and Cb2in120(2)) connected in parallel.

According to an embodiment of the invention, during the sampling phase (φs=1 and φ1=1), the switches Ss and SC1are both on. The analog input signal is sampled onto the DAC array210and shared to the 1stresidue amplification unit120(1) via switch SC1. According to an embodiment of the invention, during the conversion phase (φ1=1) the switch Ss is off and the switch SC1keeps on. The SAR controller230controls the switches S1, S2. . . Sn at the bottom-plate of the DAC array210according to the output of the comparator220. The residue R1at the top-plate of the DAC array210is successively approximated to the sampled input signal. The residue R1is shared to the top-plate of the Ca1and Ca2via switch SC1. The SAR controller may perform the multi-bit/per-cycle searching algorithm. The function how a SAR controller230works by cooperating with DAC array210and comparator220is prior art and we will not explain it deeply. According to an embodiment of the invention, during the next sampling phase (φs=1 and φ2=1), the switch SC1is off and the switch Ss, SR1SC2are one. The DAC array210is disconnected with the 1stresidue amplification unit120(1) and connected to the 2ndresidue amplification unit120(2) via switch SC2to start a new sampling. Simultaneously, the 1stresidue amplification unit120(1) connects to the input of the amplifier130via switching SR1to amplify the residue R1to the 2ndstage.

The amplifier130amplifies the residue signal R1and R2from the residue amplification unit120(1) and120(2) respectively in two time-interleaved phases (φ1and φ2). The inter stage gain of the amplifier130is decided according to how many capacitors are feedback to the output of the amplifier. For example, the inter-stage gain can be calculated as (Ca1+Ca2)/Ca2.

For good understanding, it is assumed that the DAC array210includes 4 capacitors C0to C3(i.e. n=3). The exemplary capacitances of the Capacitors C0to C3are provided as C0=C0, C1=3C0, C2=12C0, and C3=48C0, wherein C0is referred to a specific value. It also assuming that the capacitors in RAC. The exemplary capacitance of Ca1, Ca2, Cb1and Cb2are provided as Ca1=Cb1=48C0, and Ca2=Cb2=16C0. The input signal is pre-charged at top-plate of entire array (DAC array210) via switch Ss, which is bootstrapped and controlled by Φs. Since the time-interleaved switches (SC1and SC2) are kept on until its corresponding conversion is completed, thereby no timing mismatches happen between two channels. During bit cycling, 1stresidue amplification unit120(1) is involved in conversion in the N-bit ADC110and grounded to scale down the reference voltage (Vref) by 2, while another one 2ndresidue amplification unit120(2) serves as a flip-around MDAC (multiplying digital-to-analog converter) that feeds back the Cb2(16C0) to the output of the amplifier130for the ×4 residue amplification. The DAC array210is assigned as a segment thermometer-code array (a kind of capacitive array according to prior art) instead of the binary-weighted one to avoid the extra decode logic in the SAR controller230that reduces the loop delay. The DAC array210and each residue amplification unit120contain the same total units of capacitance (e.g. 64C0) that is determined by the thermal noise.

Since there are capacitor arrays used in the design of the sampling front-end100such as the N-bit DAC array210and the residue amplification units120, a compact design for the capacitor arrays is adaptive to the sampling front-end100of the present invention. Preferably, the capacitor arrays may be implemented in one semiconductor chip.FIG. 3ashows a schematic layout view of a compact capacitor array300according to an embodiment of the invention. Referring toFIG. 3a, the compact capacitor array300includes a plurality of capacitors310. For avoiding unnecessary coupling, the compact capacitor array300further includes metal shields. According to an embodiment ofFIG. 3a, there are two metal shields321,323disposed two different sides of the compact capacitor array300.

Specifically, the capacitors can be multilayer devices (e.g. a first layer, a second layer, and a third layer) and one of the capacitors310includes three parallel pairs of metals M1, M2, M3 wherein each pair of metals (M1-3) are disposed in parallel on different semiconductor layers respectively. In other words, one metal of each pair of metals (M1-3) may be disposed on the first layer and the other metal of each pair of metals M1-3 may be disposed on the second layer. In addition, the three pairs of metals M1-3 may be parallel to one another. Two metal stubs M4 and a cross metal M5 may be disposed in the third layer interposed between the first layer and the second layer. Wherein, the two metal stubs M4 are disposed at two ends of the metal M2 respectively and the two metal stubs M4 are electrically connected to the pair of metals M2 through contacts VA. Moreover, the cross metal M5 in the third layer is substantially intersected with the three pairs of metals M1-3 and the cross metal M5 is stretched across the three pairs of metals M1-3 in the center. Additionally, the cross metal M5 is electrically connected to the pairs of metals M1 and M3 through contacts VA.

It is noticeable that each of the capacitors310includes two terminals, wherein one terminal (e.g. M4) of each of the capacitors310may be connected to a different connection point of multiple connection points (e.g. B1 or B2) and the other terminal of each of the capacitors310shares the same terminal (e.g. M5). Therefore, the cross metal M5 is not only connected to the metal M1 and the metal M3 in one capacitor, but the cross metal M5 is connected to all the metals M1 and all the metals M3 throughout all the capacitors of the capacitor array300. In other words, the metal M5 is a common shared connection point to which all the capacitors (310) are connected. Since the implemented capacitor array300has one terminal (M5) shared, the plurality of the capacitors (310) can be a compact capacitor array by nature through the shared terminal (M5) without additional routing. Thus, the capacitor array300with the plurality of capacitors310has the characteristic of one terminal shared, and this structure allows high capacitive density with reduced undesired parasitic effects.

FIG. 3bshows a cross section view of a capacitor310ofFIG. 3aalong the line A-A′ according to an embodiment of the invention. As shown inFIG. 3b, the capacitance of one capacitor310may be formed of several parasitic capacitances which are obtained from lateral fields and vertical fields between metals or contacts or the combination thereof. For example, a parasitic capacitance (e.g. Cp1) may parasite between top surfaces of the metals (e.g. M1, M2, M3) on the same layer, a parasitic capacitance (e.g. Cp2) may parasite between side surfaces of the metals (e.g. M1, M2, M3) on the same layer, a parasitic capacitance (e.g. Cp3) may parasite between side surfaces of the metals (e.g. M1, M2, M3) and the contacts VA, a parasitic capacitance (e.g. Cp4) may parasite between bottom surfaces of the metals (e.g. M1, M3) and side surfaces of the metal stubs (e.g. M4), and a parasitic capacitance (e.g. Cp5) may parasite between bottom surfaces of the metals (e.g. M2) and top surfaces of the metal stubs (e.g. M4). Accordingly, the entire capacitance of the capacitor410may be substantially formed of the capacitances e.g. Cp1to Cp5.

For a practical example, while a connection point B1 is required to be connected to a capacitor with a capacitance C0, the connection point B1 is connected to a capacitor310through one contact and one metal. For another example, while a connection point B2 is required to be connected to a capacitor with a capacitance 2C0, the connection point B2 is connected to two capacitors310through two contacts and two metals. As described above, if the connection points B1 and B2 are connected to the same capacitor array, an equivalent circuit is formed as shown inFIG. 3c, wherein a capacitor CU1is connected to the connection point B1 with a capacitance C0and a capacitor CU2is connected to the connection point B2 with a capacitance 2C0. In addition, since pairs of metals M1-3 of the capacitor310are disposed on two layers, the metal shields may also be disposed in the first layer or the second layer.

In summary, the present invention presents a sampling front-end for analog to digital converter which includes an N-bit ADC, the number of i residue amplification units and an amplifier. While the N-bit ADC is used to convert a sampled input signal and share the residue to the time-interleaved residue amplifier units. The sampling front-end is implemented with an N-bit high-speed ADC, while only the residue amplification is time-interleaved. Thus, the sampling mismatches are prevented. Moreover, the signals (the residue R1-Ri) at the TI residue amplification units are static, there are no timing mismatches between i channels. In addition, a compact capacitor array design is applied to the sampling front-end for analog to digital converter of the invention. In this way, the present invention achieves high resolution, high speed, low power dissipation and compact area.