Multilayer chip capacitor

There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units; and first to fourth outer electrodes, wherein the first capacitor unit includes at least one pair of first and second inner electrodes, the second capacitor unit includes at least one pair of third and fourth inner electrodes, an alternate laminated portion is formed in one area within the capacitor body, the alternate laminated portion having the first to fourth inner electrodes sequentially laminated therein, and a capacitance adjusting portion is formed in another area within the capacitor body, the capacitance adjusting portion having at least one of the one pair of first and second inner electrodes and the one pair of third and fourth inner electrodes laminated repeatedly.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Korean Patent Application No. 2008-0077428 filed on Aug. 7, 2008, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multilayer chip capacitor, and more particularly, to a multilayer chip capacitor suitably used as a decoupling capacitor of a power distribution network of a microprocessor unit (MPU) and capable of reducing a power distribution network impedance to a target impedance or less in a broad frequency range as a single capacitor.

2. Description of the Related Art

A power distribution network (PDN) of a micro processor unit (MPU) is designed with increasing difficulty due to higher speed and more integration of the MPU. Notably, a decrease in a power voltage and an increase in an MPU consumption current resulting from more integration of the MPU has been gradually lowering a target impedance Ztarget, as represented by following

where Vp is a power voltage, AR is an allowed ripple, I is an MPU consumption current, an Vr is an allowed ripple voltage.

A general ripple voltage Vr is a value equal to 5-10% of the power voltage. The target impedance Ztargetshould be satisfied not only in a direct current (DC) but also in all frequencies where a transient current is present. A personal computer (PC) or a laptop computer undergoes a transient current even in a very high frequency range due to higher speed of a central processing unit (CPU), i.e., MPU chip and thus should satisfy a target impedance even in a broad frequency range. To satisfy the target impedance in each frequency range, the PDN employs a voltage regulator module (VRM), a bulk capacitor, a general two-terminal MLCC and a low equivalent series inductance (ESL) MLCC. This PDN is referred to as a multi-stage PDN (seeFIG. 23B).

The VRM, bulk capacitor and general two-terminal multilayer chip capacitor (MLCC) supply a current in a frequency range of several kHz, several kHz to hundreds of kHz, hundreds of kHz to several MHz, respectively and serve to lower impedance of the PDN. Unlike the bulk capacitor or general two-terminal MLCC directly installed on a motherboard, the low ESL MLCC is typically installed on a CPU package to supply a current in a frequency range of at least several MHz and reduce impedance. Finally, a die capacitor within the CPU supplies a current and lowers impedance of the PDN in a frequency higher than an effective frequency of the low ESL MLCC. The plurality of bulk capacitors, general two-terminal MLCC and low ESL MLCC are connected in parallel to one another.

FIG. 1is a schematic graph illustrating magnitude of impedance Z with respect to frequency of a general multi-stage PDN. In each stage, the VRM, bulk capacitor, general two-terminal MLCC, low ESL MLCC and die capacitor have respective impedances ZREG, ZBLK, ZMF, ZPKG, and ZDIEdetermining the impedance of an entire PDN. Accordingly, as shown, impedance of an individual capacitor greatly affects an impedance profile of the entire PDN. Also, an impedance of a previous stage capacitor is associated with an impedance of a next stage capacitor to determine the impedance of the entire PDN. In designing the PDN, an impedance at the each stage cannot be determined independently but the impedance of the entire PDN should be considered. A general two terminal MLCC which has a relatively higher ESL is installed on a motherboard or CPU package for mid-frequency decoupling. Also, a low ESL MLCC is installed in the CPU package for high-frequency decoupling. In a case where the PDN is designed to satisfy impedance characteristics in a wider frequency range, a greater number of decoupling capacitors may be utilized to cover wide frequency ranges (seeFIG. 23B).

FIG. 2schematically illustrates a conventional motherboard apparatus having decoupling capacitors connected thereto by MPU power circuits. Referring toFIG. 2, a CPU, i.e., MPU chip51is surface-mounted on a package board53to form CPU packages51and53. Theses CPU packages51and53are surface-mounted onto a motherboard55. Circuit conductors such as power (PWR) planes, ground (GND) planes, vias are provided inside and on an outer surface of the motherboard55and the package board53to configure a power circuit. Also, bumps or pins15are utilized to electrically connect the components53and55. Decoupling capacitors10and20of different types according to the frequency range are connected to this power circuit to form a multi-stage PDN. The low ESL MLCC10for high-frequency decoupling, for example, a low inductance ceramic capacitor (LICC) or an interdigital capacitor (IDC) may be disposed on a bottom of the CPU package53. The general MLCC20for mid-frequency decoupling may be directly disposed on a top or bottom of the motherboard55in the vicinity of the CPU packages51and53, or installed on the bottom of the CPU package53.

As described above, to form the multi-stage PDN, the capacitors10and20of different structures according to each frequency range should be employed. Accordingly, mounting surfaces or mounting positions of the capacitor need to be different according to the each frequency range. Moreover, a greater number of the chip capacitors10and20are required to lower total impedance of the PDN to a target impedance or less.

SUMMARY OF THE INVENTION

An aspect of the present invention provides a multilayer chip capacitor capable of reducing a power distribution network (PDN) impedance to a target impedance or less in a broad frequency range of hundreds of kHz to hundreds of MHz with a smaller number of capacitors.

According to an aspect of the present invention, there is provided a multilayer chip capacitor including: a capacitor body having a plurality of dielectric layers laminated therein, the capacitor body including first and second capacitor units having capacitances different from each other; and first to fourth outer electrodes formed on an outer surface of the capacitor body, wherein the first capacitor unit includes at least one pair of first and second inner electrodes opposing each other while interposing a corresponding one of the dielectric layers, the first and second inner electrodes connected to the first and second outer electrodes, respectively to have polarities different from each other, the second capacitor unit includes at least one pair of third and fourth inner electrodes opposing each other while interposing another corresponding one of the dielectric layers, the third and fourth inner electrodes connected to the third and fourth outer electrodes, respectively to have polarity identical to the first and second inner electrodes, an alternate laminated portion is formed in one area within the capacitor body, the alternate laminated portion having the first to fourth inner electrodes sequentially laminated therein, and a capacitance adjusting portion is formed in another area within the capacitor body, the capacitance adjusting portion having at least one of the one pair of first and second inner electrodes and the one pair of third and fourth inner electrodes laminated repeatedly.

The alternate laminated portion may be disposed in a lower part of the capacitor body and the capacitance adjusting portion is disposed above the alternate laminated portion.

The alternate laminated portion may include two alternate laminated portions disposed on upper and lower parts of the capacitor body, respectively and the capacitance adjusting portion is disposed between the alternate laminated portions. The alternate laminated portions disposed in the upper and lower parts of the capacitor body may be symmetrical to each other about a center of the capacitor body.

The capacitance adjusting portion may include the at least one pair of third and fourth inner electrodes laminated repeatedly. The second capacitor unit may have a capacitance greater than a capacitance of the first capacitor unit.

The one pair of first and second inner electrodes in the first capacitor unit may define one layer, and the one pair of third and fourth inner electrodes in the second capacitor unit may define another layer, wherein an equivalent series inductance (ESL) per layer of the first and second inner electrodes is smaller than an equivalent series inductance per layer of the third and fourth inner electrodes. The one pair of the first and second inner electrodes may be disposed in a lowermost part of the alternate laminated portion.

The first to fourth inner electrodes may include leads for connecting the first to fourth outer electrodes thereto, respectively, wherein the leads of the first and second inner electrodes have widths greater than widths of the leads of the third and fourth inner electrodes.

The first to fourth inner electrodes may include leads for connecting the first to fourth outer electrodes thereto, respectively, wherein the leads of the first and second inner electrodes have widths identical to each other and the leads of the third and fourth inner electrodes have widths identical to each other.

The first and second capacitor units may be electrically insulated from each other.

Adjacent ones of the first to fourth inner electrodes of the alternate laminated portion may have a distance identical to a distance between the alternate laminated portion and the capacitance adjusting portion. This can lead to an increase in capacitance.

The multilayer chip capacitor may include a four-terminal capacitor including a respective one of the first to fourth outer electrodes. The first to fourth inner electrodes may be connected to the first to fourth outer electrodes through one lead, respectively. The first and second outer electrodes may be formed on opposing first and second longer side surfaces of the capacitor body, respectively and the third and fourth outer electrodes may be formed on opposing first and second shorter side surfaces of the capacitor body, respectively.

The first and second outer electrodes may be formed on a first longer side surface and a first shorter side surface adjacent to each other in the capacitor body, respectively, and the third outer electrode may be formed on a second longer side surface opposing the first longer side surface and the fourth outer electrode may be formed on a second shorter side surface opposing the first shorter side surface.

Each of the third and fourth outer electrodes may include two outer electrodes, and the first and second outer electrodes may be formed on opposing first and second longer side surfaces of the capacitor body and the respective two third and fourth outer electrodes may be formed on the first and second longer side surfaces, respectively. The first outer electrode is formed between the two third outer electrodes and the second outer electrode is formed between the two fourth outer electrodes. Each of the first and second outer electrodes may include two outer electrodes.

Each of the third and fourth outer electrodes may include two outer electrodes, the first and second outer electrodes may be formed on opposing first and second longer side surfaces of the capacitor body, respectively and the respective two third and fourth outer electrodes may be formed on the second and first longer side surfaces, respectively. The first outer electrode may be formed between the two fourth outer electrodes and the second outer electrode may be formed between the two third outer electrodes.

Each of the first and second outer electrodes may include two outer electrodes, wherein respective single ones of the first and second outer electrodes are formed on opposing first and second longer side surfaces of the capacitor body, respectively, and each of the third and fourth outer electrodes may include two outer electrodes, wherein respective single ones of the third and fourth outer electrodes are formed on the opposing first and second longer side surfaces of the capacitor body, respectively. On each of the first and second longer side surfaces, the first and second outer electrodes may be disposed between the third and fourth outer electrodes. Corresponding ones of the outer electrodes adjacent to each other on the first and second longer side surfaces, respectively may have polarities different form each other.

Each of the first and second outer electrodes may include four outer electrodes and respective two of the first and second outer electrodes may be formed on opposing first and second longer side surfaces, respectively, and the third and fourth outer electrodes may be formed on opposing first and second shorter side surfaces of the capacitor body. The first and second outer electrodes may be arranged alternately on the first and second longer side surfaces, respectively.

Each of the first and second inner electrodes may include four leads through which the first and second outer electrodes are connected thereto, the leads of the first inner electrodes may be arranged adjacent to the leads of the second inner electrodes in an interdigitated configuration to be connected to corresponding ones of the outer electrodes having identical polarity.

Each of the first and second inner electrodes may include two leads led out to the first and second longer side surfaces, respectively and connected to the first and second outer electrodes, respectively, in the each of the first and second inner electrodes, a corresponding one of the leads led out to the first longer side surface may be arranged shifted to a position corresponding to the outer electrode immediately adjacent thereto, with respect to another corresponding lead led out to the second longer side surface, and in the first capacitor unit, the leads led out to each of the first and second longer side surfaces may be arranged in a zigzag shape with respect to each other along a laminated direction from the longer side surface.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 3is a perspective view illustrating an appearance of a multilayer chip capacitor according to an exemplary embodiment of the invention.FIG. 4is a cross-sectional view of the multilayer chip capacitor ofFIG. 3, taken along the line X-X′.FIG. 5is a cross-sectional view of the multilayer chip capacitor ofFIG. 3, taken along the line Y-Y′.FIG. 6is a plan view illustrating an inner electrode structure of the capacitor shown inFIG. 3

Referring toFIGS. 3 to 6, the capacitor100includes a capacitor body110shaped as a rectangular parallelepiped, and first to fourth outer electrodes131,132,134, and134formed on side surfaces of the body. The capacitor body110has a plurality of dielectric layers (140ofFIG. 5) laminated therein, and first to fourth inner electrodes121,122,123, and124are arranged alternately while interposing a corresponding one of the dielectric layers. The first and second outer electrodes131and132are disposed on opposing longer ones of the side surfaces Lf1and Lf2of the body110. The third and fourth outer electrodes133and134are disposed on opposing shorter ones of the side surfaces Sf1and Sf2.

Here, as shown inFIG. 3, the first and third outer electrodes131and133have positive (+) polarity and the second and fourth outer electrodes132and134have negative (−) polarity. The first and second inner electrodes121and122constitute a first capacitor unit CR1and the third and fourth inner electrodes123and124constitute a second capacitor unit CR2. Meanwhile, the multilayer chip capacitor100is formed of a four terminal multilayer chip capacitor (MLCC) having the four outer electrodes in total but the present invention is not limited thereto.

As shown inFIGS. 4 and 5, the capacitor body110includes two portions P1and P2arranged in a laminated direction, i.e. z axis direction. Hereinafter, the two portions P1and P2are referred to as an alternate laminated portion P1and a capacitance adjusting portion P2. First, the alternate laminated portion P1includes the first and second inner electrodes121and122of different polarities arranged while interposing a corresponding one of the dielectric layers140and the third and fourth inner electrodes123and124of different polarities arranged while interposing another one of the dielectric layers140. Here, the first and second inner electrodes121and122are connected to only first and second outer electrodes131and132, respectively. The third and fourth inner electrodes123and124are connected to only third and fourth outer electrodes133and134, respectively. This allows the first and second capacitor units CR1and CR2to be electrically insulated from each other in the multilayer chip capacitor100. That is, before the multilayer chip capacitor100is mounted on a circuit board, the first and second capacitor units CR1and CR2are not electrically connected to each other.

Referring toFIG. 6, the first to fourth inner electrodes121to124are connected to corresponding ones of the outer electrodes131to134by leads R1to R4, respectively. The lead R1of the first inner electrode has a width identical to a width of the lead R2of the second inner electrode. The lead R3of the third inner electrode has a width identical to a width of the lead R4of the fourth inner electrode. Meanwhile, in the alternate laminated portion P1, the first to fourth inner electrodes121to124are sequentially and alternately arranged. That is, in the alternate laminated portion P1, the first to fourth inner electrodes121to124are laminated from a bottom of the capacitor body110in an order of121-122-123-124-121-122-123-124. . . .

The capacitance adjusting portion P2is disposed above the alternate laminated portion P1and has the third and fourth inner electrodes123and124laminated alternately and repeatedly. The third and fourth inner electrodes123and124of the capacitance adjusting portion P2constitute the second capacitor unit CR2together with the third and fourth inner electrodes123and124of the alternate laminated portion P1. The first and second inner electrodes121and122of the alternate laminated portion P1constitute the first capacitor unit CR1. In the present embodiment, the capacitance adjusting portion P2is additionally employed to ensure that the first and second capacitor units CR1and CR2have different capacitances. This configuration is designed to assure that two or more capacitor units with different capacitances are included in one capacitor body110. Here, the second capacitor unit CR2having a greater lamination number of the inner electrodes through the capacitance adjusting portion P2may have a capacitance greater than a capacitance of the first capacitor unit CR1. However, in place of the third and fourth inner electrodes123and124constituting the second capacitor unit CR2, the first and second inner electrodes121and122constituting the first capacitor CR1may be laminated repeatedly to form the capacitance adjusting portion P1. Furthermore, all of the first to fourth inner electrodes121to124may be employed to form the capacitance adjusting portion.

As described above, in the alternate laminated portion P1, the first and second inner electrodes121and122of the first capacitor CR1and the third and fourth inner electrodes123and123of the second capacitor CR2are arranged alternately. This allows a current path to occur additionally in each of the inner electrodes121to124to thereby reduce equivalent series inductance (ESL).FIG. 7illustrates a current flow in inner electrodes in a multilayer chip capacitor having first and second capacitor units arranged alternately.FIG. 8illustrates a current flow in inner electrodes in a multilayer chip capacitor having first and second capacitor units arranged at a distance from each other.

First, referring toFIG. 8, in a case where the first and second capacitor units are spaced at a distance from each other, i.e., in a lamination configuration of (121-122-121-122. . . )/(123-124-123-124. . . ), a current path of one direction is formed in each of inner electrodes. On the contrary, referring toFIG. 7, in a case where the first and second capacitor units are arranged alternately, an inner electrode of negative polarity in the second capacitor unit is disposed adjacent to an inner electrode of positive polarity in the first capacitor unit. This allows a current path (Lf1→Sf2) other than the current path (Lf→Lf2) to be additionally formed in the each of the inner electrodes. This current path additionally formed leads to a reduction in ESL per layer, for example, ESL formed by a pair of the first and second inner electrodes121and122.

Moreover, the capacitance adjusting portion P2enables the second capacitor unit CR2with a relatively bigger capacitance to be disposed farther away from a mounting surface than the first capacitor unit CR1, thereby ensuring less increase in ESL. Furthermore, in the present embodiment, the capacitor body110includes the first and second capacitor units CR1and CR2with different capacitances while capable of being prevented from a decrease in capacitance. In a case where the first and second capacitor units CR1and CR2are connected to identical ones of the outer electrodes, the first and second capacitor units CR1and CR2need to be spatially separated from each other to ensure different capacitances. In the present embodiment, the first and second capacitor units CR1and CR2are electrically insulated from each other, thereby precluding a need for arranging the first and second capacitor units CR1and CR2at a predetermined distance in a laminated direction. Accordingly, this increases the number of the inner electrodes included in the capacitor body110and subsequently a capacitance of an entire capacitor. As described above, adjacent ones of the first to fourth inner electrodes121to124in the alternate laminated portion P1have a distance equal to a distance between the alternate laminated portion P1and the capacitance adjusting portion P2to improve capacitance.

Referring toFIG. 6, in the first capacitor unit CR1, the leads R1and R2of the inner electrodes121and122vertically adjacent to each other and having different polarities have a small distance from each other. Meanwhile, in the second capacitor unit CR2, the leads R3and R4of the inner electrodes123and124vertically adjacent to each other and having different polarities have a relatively greater distance from each other. This allows the first capacitor unit CR1to have an ESL per layer lower than an ESL per layer of the second capacitor unit CR2. Here, the ESL per layer denotes an ESL provided by a pair of the opposing inner electrodes adjacent to each other and having different polarities.

Accordingly, as shown inFIG. 4, the first capacitor unit CR1including the inner electrode having a short current path and leads of great widths and thus ensuring relatively low ESL is disposed in the greater vicinity of a bottom of the capacitor body110than the second capacitor unit CR2. This allows a current flowing in the capacitor at a high frequency to concentrate on the inner electrodes121and122with a relatively low ESL. This shortens a current path defined by a substantial current loop to maintain an overall ESL at a lower level.

Mostly, a low ESL multilayer chip capacitor (MLCC) has a capacitance smaller than a capacitance of a general two-terminal MLCC employed in an identical motherboard apparatus. Therefore, the laminated number of the inner electrodes121and122of the first capacitor CR1may be smaller than the laminated number of the inner electrodes123and124of the second capacitor CR2. To this end, in the present embodiment, the capacitance adjusting portion P2is employed to additionally laminate the second capacitor unit CR2requiring a greater capacitance. This may allow the first capacitor CR1to have a serial resonant frequency (SRF) higher than a resonant frequency of the second capacitor unit CR2.

In the capacitor100described above, the first capacitor unit CR1serves as a conventional low ESL two-terminal MLCC, i.e., low inductance chip capacitor (LICC). Also, the second capacitor unit CR2serves as a conventional two terminal MLCC. Therefore, the capacitor100integrates the conventional two-terminal MLCC and the low ESL LICC into one chip. Consequently, this single capacitor can reduce a PDN impedance to a target impedance or less in a wide frequency range, for example, hundreds of kHz to hundreds of MHz range. Particularly, as described above, the first and second capacitor units electrically insulated from each other are employed in the one chip. This results in no substantial change in the number of capacitors although the two capacitor units CR1and CR2are joined into one chip. This ensures the PND to be easily designed to satisfy target impedance and allows target impedance to be further satisfied.

Moreover, when the decoupling two terminal MLCC mounted on the motherboard and the decoupling low ESL MLCC mounted on the CPU package are integrated into the aforesaid capacitor100, the number of the decoupling capacitors used in the PDN of the CPU can be significantly decreased. That is, since the second capacitor unit CR2of the capacitor100performs mid-frequency decoupling, an additional two-terminal MLCC is not required for mid-frequency decoupling or the necessary number of the two terminal MLCC can be diminished.

FIG. 9is across-sectional view illustrating a modified example of the multilayer chip capacitor shown inFIG. 3. The multilayer chip capacitor100′ ofFIG. 9is shaped identically to the capacitor ofFIG. 3and can be compared with a cross-sectional view ofFIG. 4. Referring toFIG. 9, the multilayer chip capacitor100′ is mounted on a circuit board150. In the present embodiment, the capacitor body110′ includes two alternate laminated portions P1and P3and one capacitance adjusting portion P2. The alternate laminated portions P1and P3are disposed in upper and lower parts of the capacitor body110′ while interposing the capacitance adjusting portion P2. Here, a first capacitor unit includes first and second inner electrodes121and122which have been described with reference toFIG. 3. Also, a second capacitor includes third and fourth inner electrodes123and124which have been described with reference toFIG. 3. From a corresponding one of the inner electrodes closest to a mounting surface, the inner electrodes are laminated in an order of (121-122-123-124- . . . )/(123-124-123-124- . . . )/(121-122-123-124- . . . ). Moreover, the alternate laminated portions P1and P3are disposed symmetrically with respect to the capacitance adjusting portion P2in a laminated direction. That is, the upper and lower parts of the multilayer chip capacitor100′ are symmetrical to each other. This ensures the multilayer chip capacitor100′ to be mounted in symmetry, thereby allowing the capacitor to be mounted on the circuit board150without a need for distinguishing top and bottom surfaces thereof.

FIG. 10is a perspective view illustrating a multilayer chip capacitor according to another exemplary embodiment of the invention.FIG. 11is a plan view illustrating an electrode structure and a current flow of the multilayer chip capacitor shown inFIG. 10. First, referring toFIG. 10, the multilayer chip capacitor200of the present embodiment is shaped identically to the capacitor100ofFIG. 3but different in terms of the arrangement of outer electrodes. As for first and second outer electrodes231and232connected to a first capacitor unit CR1, the first outer electrode231of positive (+) polarity is formed on a first longer side surface Lf1of the capacitor body210and the second outer electrode of negative (−) polarity is formed on a second shorter side surface Sf2. As for third and fourth outer electrodes233and234connected to a second capacitor unit CR2, the third outer electrode233of positive (+) polarity is formed on a second longer side surface Lf2of the capacitor body210and a fourth outer electrode234of negative (−) polarity is formed on a first shorter side surface Sf1. This leads to a different configuration of the inner electrodes from the previous embodiment.

That is, referring toFIG. 11, the first and second inner electrodes221and222of the first capacitor CR1are connected to the first and second outer electrodes231and232, respectively. The first and second inner electrodes221and222of the first capacitor CR1are configured identically to those ofFIG. 11due to the first and second outer electrodes231and232formed on the first longer side surface and the second shorter side surface of the capacitor body210, respectively as described above. Likewise, third and fourth inner electrodes223and224of the second capacitor CR2are disposed as depicted in a lower part ofFIG. 11. In the present embodiment, a current flows in each of the inner electrodes221to224on a shorter path than a current flowing as shown inFIG. 7. Accordingly, this ensures a further decrease in ESL.

FIG. 12is a simulation graph for comparing impedance characteristics between the multilayer chip capacitor (solid line) ofFIG. 10and a conventional multilayer chip capacitor (dotted line). Here, the conventional multilayer chip capacitor has a structure such that first and second capacitor units are not laminated alternately but separated from each other. Referring toFIG. 12, the multilayer chip capacitor having a structure ofFIG. 10exhibits low impedance at a high frequency, particularly, a resonant frequency or more compared with the conventional multilayer chip capacitor.

FIG. 13is a perspective view illustrating a multilayer chip capacitor according to still another exemplary embodiment of the invention.FIG. 14is a plan view illustrating an inner electrode structure of the multilayer chip capacitor shown inFIG. 13.

Referring toFIG. 13, in the multilayer chip capacitor300of the present embodiment, a first outer electrode331with positive (+) polarity and two third outer electrodes333with positive (+) polarity are formed on a first longer side surface Lf1of a capacitor body310. Also, a second outer electrode332with negative (−) polarity and two fourth outer electrodes334with negative (−) polarity are formed on a second longer side surface Lf2. That is, in the present embodiment, the first and fourth outer electrodes331to334are formed only on the longer side surfaces Lf1and Lf2of the capacitor body310, respectively. Here, the first outer electrode331is disposed between the two third outer electrodes333and the second outer electrode332is disposed between the two fourth outer electrodes334. Also, as shown inFIG. 14, the first to fourth inner electrodes321to324include leads through which the first to fourth outer electrodes331to334are connected thereto, respectively. This arrangement of the outer electrodes and inner electrodes according to the present embodiment ensures the chip to be vertically symmetrical to each other. Meanwhile, the first and second capacitor units CR1and CR2are slightly different in terms of ESL, and thus unlike the previous embodiment, any of the first and second capacitor units CR1and CR2may be disposed first on the capacitor body310. The multilayer chip capacitor300is a six terminal multilayer chip capacitor having the outer electrodes formed only on the first and second longer side surfaces Lf1and Lf2to ensure higher mounting density. The present embodiment is different from the previous embodiment in the arrangement configuration of the outer electrodes and inner electrodes. The first to fourth inner electrodes321to324may be laminated identically to the previous embodiments. That is, the capacitor is divided into the first and second capacitor units CR1and CR2having different capacitances, and the inner electrodes are laminated in a different configuration for the alternate laminated portion (first and second capacitor units) and for the capacitance adjusting portion (first or second capacitor unit). This is equally applied to embodiments ofFIGS. 15 to 26which will be described below.

FIG. 15is a perspective view illustrating a multilayer chip capacitor according to a further exemplary embodiment of the invention.FIG. 16is a plan view illustrating an inner electrode structure of the multilayer chip capacitor shown inFIG. 15.

Referring toFIG. 15, in the multilayer chip capacitor400of the present embodiment, two first outer electrodes431having positive (+) polarity and two third outer electrodes433having positive (+) polarity are formed on a first longer side surface Lf1of the capacitor body410. Also, two second outer electrodes432having negative (−) polarity and two fourth outer electrodes434having negative (−) polarity are formed on a second longer side surface Lf2, thereby providing an eight terminal multilayer chip capacitor (MLCC). At this time, the first outer electrodes431are disposed between the two third outer electrodes433. The second outer electrodes432are disposed between the two fourth outer electrodes434. Accordingly, this ensures the chip to be in vertical symmetry in the same manner asFIG. 13. Moreover, as shown inFIG. 16, first to fourth inner electrodes421to424include leads for connecting the first to fourth outer electrodes431to334thereto, respectively. Here, the first and second capacitor units CR1and CR2are connected to the outer electrodes formed on the longer side surfaces Lf1and Lf2of the capacitor body410and exhibit little difference in ESL. Thus, any one of the first and second capacitor units CR1and CR2may be disposed first in the alternate laminated portion.

FIG. 17is a perspective view illustrating a multilayer chip capacitor according to a further exemplary embodiment of the invention.FIG. 18is a plan view illustrating an inner electrode structure of the multilayer chip capacitor shown inFIG. 17.

In the present embodiment, the multilayer chip capacitor is shaped identically to the multilayer chip capacitor ofFIG. 13but different in the arrangement of outer electrodes and the configuration of inner electrodes. Referring toFIG. 17, in the multilayer chip capacitor500of the present embodiment, a second outer electrode532having negative (−) polarity and two third outer electrodes533having positive (+) polarity are formed on a first longer side surface Lf1of a capacitor body510. A first outer electrode531having positive (+) polarity and two fourth outer electrodes534having negative (−) polarity are formed on a second longer side surface Lf2. Here, the second outer electrode532is disposed between the two third outer electrodes533and the first outer electrode531is disposed between the two fourth outer electrodes534. That is, the outer electrodes with different polarities are arranged alternately on the longer side surfaces Lf1and Lf2of the capacitor body510, respectively. As shown inFIG. 18, first to fourth inner electrodes521to524include leads for connecting the first to fourth outer electrodes531to534thereto, respectively. In the same manner as the previous embodiments, this allows the chip to be in vertical symmetry. Particularly, referring toFIG. 18, currents flow through adjacent ones of the inner electrodes521to524in opposite directions to cancel magnet flux out, thereby reducing ELS. Also, first and second capacitor units CR1and CR2are slightly different in ESL and thus either of them can be disposed first in the alternate laminated portion.

FIG. 19is a perspective view illustrating a multilayer chip capacitor according to a further exemplary embodiment of the invention.FIG. 20is a plan view illustrating an inner electrode structure of the multilayer chip capacitor shown inFIG. 19.

In the present embodiment, the multilayer chip capacitor is shaped identically to the multilayer chip capacitor ofFIG. 15but different in the arrangement of outer electrodes and the configuration of inner electrodes. Referring toFIG. 19, the multilayer chip capacitor600of the present embodiment includes respective two first to fourth outer electrodes631to634. Respective single ones of the first to fourth outer electrodes631and634are formed on a first longer side surface Lf1of the capacitor body and the other ones of the first to fourth outer electrodes631and634are formed on a second longer side surface Lf2of the capacitor body610. Here, the first and second outer electrodes631and632are disposed between the third and fourth outer electrodes633and634but the outer electrodes of different polarities are arranged alternately to ensure the chip is in vertical symmetry. Also, as shown inFIG. 20, the first to fourth inner electrodes621to624include leads for connecting the first to fourth outer electrodes631to634thereto, respectively. Currents flow in adjacent ones of the inner electrodes621to624in opposite directions to cancel magnetic flux out, thereby reducing ESL. Here, the first and second capacitor units CR1and CR2are slightly different in ESL and thus any one of the first and second capacitor units CR1and CR2may be disposed first in an alternate laminated portion.

FIG. 21is a perspective view illustrating a multilayer chip capacitor according to a further exemplary embodiment of the invention.FIG. 22is a plan view illustrating an inner electrode structure of the multilayer chip capacitor shown inFIG. 21.FIG. 23is a plan view illustrating an inner electrode structure of the multilayer chip capacitor shown inFIG. 21.

Referring toFIG. 21, the multilayer chip capacitor700of the present embodiment includes respective four first and second outer electrodes731and732. Two of the first outer electrodes731and two of the second outer electrodes732are formed alternately on a first longer side surface Lf1of a capacitor body710and the other two first outer electrodes731and the other two second outer electrodes732are formed alternately on a second longer side surface Lf2of the capacitor body710. Also, third and fourth outer electrodes733and734are formed on first and second shorter side surfaces Sf1and Sf2of the capacitor body710, respectively to constitute a ten-terminal multilayer chip capacitor (MLCC). As shown inFIG. 22, the first and second inner electrodes721and722each include four leads. The leads of the first inner electrode721are arranged adjacent to the leads of the inner electrodes722in an interdigitated configuration, and connected to the outer electrodes731and732of identical polarity through the leads. With this interdigitated configuration, in the first capacitor unit CR1, magnetic fluxes are cancelled out in adjacent ones of the inner electrodes to further reduce ESL.

Meanwhile, in the first capacitor unit, inner electrodes may be configured as shown inFIG. 23. Referring toFIG. 23, the first capacitor unit CR1′ includes three first inner electrodes721ato721cof positive (+) polarity and three second inner electrodes722ato722cof negative (−) polarity arranged alternately on each of first and second longer side surfaces. Here, the first and second inner electrodes721ato721c;722ato722care connected to outer electrodes of identical polarity by a respective one lead. Here, the inner electrodes of identical polarity are electrically connected to one another. As shown inFIG. 23, the leads of the first and second inner electrodes721ato721c;722ato722care arranged in a zigzag shape in a laminated direction. This zigzag configuration can reduce mutual inductance of the leads adjacent to each other in a laminated direction and having identical polarity.

In the inner electrodes721ato721c;722ato722c, a corresponding one of the leads led out to the first longer side surface Lf1is arranged shifted to a position corresponding to the outer electrode immediately adjacent thereto, with respect to another corresponding lead led out to the second longer side surface Lf2. This zigzag arrangement and shifted arrangement of the leads allow the inner electrodes of identical polarity in the first capacitor unit CR1to be electrically connected to one another. Also, according to the present embodiment, in the first capacitor unit CR1, the leads of the first and second inner electrodes, for example,721aand722aadjacent to each other in a laminated direction are disposed adjacent to each other in a laminated direction.

FIG. 24is a perspective view illustrating a multilayer chip capacitor according to a further exemplary embodiment of the invention.FIG. 25is a plan view illustrating an inner electrode structure of the multilayer chip capacitor shown inFIG. 24.FIG. 26is a plan view illustrating an inner electrode structure of the multilayer chip capacitor shown inFIG. 24.

Referring toFIG. 24, the multilayer chip capacitor800of the present embodiment includes respective five first and second outer electrodes831and832. The first and second outer electrodes831and832are arranged alternately on each of first and second longer side surfaces Lf1and Lf2of a capacitor body810. Also, a respective one of third and fourth outer electrodes833and834is formed on each of first and second shorter side surfaces Sf1and Sf2of the capacitor body810to constitute a fourteen-terminal multilayer chip capacitor (MLCC). As shown inFIG. 25, five leads of the first inner electrode821are arranged adjacent to five leads of the second inner electrode822in an interdigitated configuration, and the first and second inner electrodes821and822are connected to the outer electrodes831and832of identical polarity through the leads.

With this interdigitated configuration, in the first capacitor unit CR1, magnetic fluxes are cancelled out each other in adjacent ones of the inner electrodes to further reduce ESL. Meanwhile, as shown inFIG. 26, the first and second inner electrodes821′ and822′ of the first capacitor unit CR1′ may be connected to the longer side surface and shorter side surface, respectively. Also, the third and fourth inner electrodes823′ and824′ of the second capacitor unit CR2′ may be connected only to the longer side surface.

As set forth above, according to exemplary embodiments of the invention, a single capacitor is employed to reduce a PDN impedance to a target impedance or less in a wide frequency range from hundreds of kHz to hundreds of MHz. Thus significantly reduces the number of decoupling capacitors utilized in a digital switching circuit such as a high speed MPU and ensures the decoupling capacitors to be effectively mounted in a less space and at a lower cost. Also, the multilayer chip capacitor including capacitor units with different capacitances as a single chip is prevented from a decline in capacitance.