Method of making gate turn off switch with anode short and buried base

A GTO switch is provided in which the upper base layer (gate) is formed by a diffusion step. An epitaxial layer grown over the upper base layer contains cathode and gate diffusions which are separated by an undiffused gap. This "buried base" technique provides precise control over the resistivity of the base. The cathode-gate gap provides increased reverse gate voltage capacity. Other features include a large anode short area and a double-layer-metal; contact structure on the cathode-gate surface.

FIELD OF THE INVENTION 
The present invention relates, in general, to gate turn-off semiconductor 
switches. More particularly, the invention relates to an improved gate 
turn off switch design and a method for the manufacture of such devices. 
BACKGROUND OF THE INVENTION 
Gate turn-off (GTO) switches are widely known semiconductor devices capable 
of controlling a load current in response to a control signal. Such 
devices are often referred to as thyristors. Currently, it is desired to 
increase the capacity of such devices to handle greater currents and 
voltages. In doing so, however the turn off characteristics of the device 
must be maintained to as great a degree as possible. Typically, a GTO 
switch is a 4-layer vertical structure having a P-type (anode) layer on 
the bottom followed by N-type and P-type inner (base) layers and an N-type 
upper (cathode) layer. Recently, N-type shorts have been utilized 
extending up through the anode layer to the N-type base layer. The P-type 
base layer is brought to the upper surface of the device at some point to 
allow contact. This contact is commonly referred to as the gate. The upper 
two layers of the device have most commonly been manufactured by means of 
a double diffused process flow. That is, the P-type base is first defined 
by diffusion of a P-type dopant and then the N-type cathode is defined by 
the diffusion of an N-type dopant into the previously diffused P-type 
region. 
In order to control the turn-off characteristics of a GTO switch it is 
necessary to carefully control the sheet resistance of the P-type base 
region. It has been found that this is relatively difficult to do using a 
double diffused process. This problem has become increasingly severe as 
the current and voltage capacities of the device are increased. A further 
requirement for GTO switches is the capacity to withstand a relatively 
high reverse gate voltage. The prior art double diffused method of forming 
the gate and cathode regions is not reliably capable of producing a 
reverse gate voltage capacity significantly in excess of 15 volts. 
SUMMARY OF THE INVENTION 
Accordingly, it is an object of the present invention to provide an 
improved GTO switch and method for the manufacture thereof. 
A further object of the present invention is to provide a GTO switch having 
a precisely controlled base sheet resistance. 
A further object of the present invention is provide an improved GTO switch 
having a relatively high reverse gate voltage capacity. 
These and other objects and advantages of the present invention are 
provided by defining the sheet resistivity of the base region to a 
relatively low value by a diffusion step, growing a relatively lightly 
doped N-type epitaxial layer overlying the P-type base region and defining 
cathode and gate regions within the epitaxial layer by the diffusion of 
N-type and P-type dopants, respectively. The gate and cathode diffusions 
in the epitaxial layer are separated by a region which is left at the 
doping concentration of the epitaxial layer to provide an increased 
reverse gate voltage capacity. Other features of a preferred embodiment of 
the present invention include a unique layer with a relatively large anode 
short area and a two layer metallization pattern on the gate-cathode 
surface.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT 
FIGS. 1A-1D illustrate, in partial cross-sectional views, various 
intermediate steps in the manufacture of a GTO switch according to the 
principles of the present invention, As will be apparent from the 
description of the various mask steps below, a cross-section of the entire 
device would be unnecessarily confusing. Therefore, FIGS. 1A-1D illustrate 
only one "arm" of the involute spiral pattern which comprises the entire 
device. 
FIG. 1A illustrates the results of the first several process steps. A 
single crystal silicon wafer 10 has a first major surface 11 and a second 
major surface 12. In the preferred embodiment of the invention described 
herein the starting wafer 10 is an N-type wafer having a resistivity in 
the range of 50-70 ohm centimeters and a thickness in the range of 12-13 
mils. In the initial process steps an initial oxide layer 13 is grown on 
both first major surface 11 and second major surface 12 of wafer 10. 
Conventional photoresist and etch steps are used to remove initial oxide 
layer 13 from first major surface 11. Next, a P-type dopant such as boron 
is deposited on first major surface 11 and driven in to produce a P-type 
region 14 underlying first major surface 11 of wafer 10. The remainder 15 
of wafer 10 remains N-type. P-type region 14 is preferably in the range of 
30-50 microns thick and has a sheet resistance in the range of 40-100 ohms 
per square. It has been found that best results are achieved with a sheet 
resistance in the range of 40-60 ohms per square. 
The process steps described above defines the resistivities of what will 
eventually become the N-type base region (region 15) and the P-type base 
region (region 14) of the finished GTO switch. In this manner, it is 
possible to control very accurately the resistivity of the P-type base 
region 14. 
FIG. 1B illustrates the result of the next several process steps. First, 
several standard cleaning steps are applied to first major surface 11 of 
wafer 10 to remove the result of the P-type dopant deposition and drive 
in. Next, an N.sup.- epitaxial layer 18 is grown overlaying first major 
surface 11 of wafer 10. Epitaxial layer 18 preferably has a resistivity in 
the range of 50-200 ohm centimeters and a thickness in the range 20-40 
microns. Epitaxial layer 18 may be grown by any of a number of 
conventional processes, such as liquid phase epitaxy (LPE). Finally, an 
oxide layer 19 is grown overlaying epitaxial layer 18. Oxide layer 19 will 
serve as diffusion mask for the various diffusions to be placed in 
epitaxial layer 18. 
FIG. 1C illustrates the result of the next several process steps. The 
purpose of these process steps is to define the P-type diffusions in 
epitaxial layer 18 and N-type base region 15 which will eventually form 
the gate and anode, respectively, of the finished GTO switch. Using 
conventional photoresist and oxide etching steps, appropriate openings are 
made in oxide layer 19 and oxide layer 13. The details of the masks used 
to produce these openings will be discussed below. The openings in oxide 
layers 19 and 13 are not shown in FIG. 1C since the succeeding process 
steps regrow the oxide layers in those regions. Once the appropriate 
openings in oxide layers 19 and 13 are produced a P-type dopant, such as 
boron, is deposited over the surfaces and is driven into epitaxial layer 
18 and to N-type region 15, respectively. This produces a pair of spaced 
apart P-type regions 21 in epitaxial layer 18 and a pair of spaced apart 
P-type regions 22 in N-type region 15. As will be discussed in detail 
below, P-type regions 22 directly underlie the portion of epitaxial layer 
18 between P-type regions 21. As will be apparent, the resistivity and 
thickness of P-type regions 21 and 22 will be substantially identical, 
since they are produced simultaneously. It is important that P-type 
regions 21 be diffused sufficiently deeply so that they extend entirely 
through epitaxial layer 18 to reach P-type base region 14. The sheet 
resistance of P-type regions 21 and 22 may advantageously be in the range 
of 20-30 ohms per square. By means of the process steps just described, 
contact to P-type base region 14 is made available at the surface of 
epitaxial layer 18, which will form the upper active surface of the 
device. Thus, P-type regions 21 form the gate of the device. 
Simultaneously, the anode of the device has been formed by P-type 
diffusions 22. 
FIG. 1D illustrates the results of the next several steps in the process. 
After these steps are complete, the basic GTO switch is finished but for 
the steps of separating each die from the overall wafer and defining the 
various contacts and passivations. The next several process steps involve 
the definition of N.sup.+ diffusions in epitaxial layer 18 and N-type 
region 15. To this end, conventional photoresist and oxide etch steps are 
used to produce appropriate openings in oxide layers 19 and 13, 
respectively. Again, the details of the masks used will discussed below. 
Next, an N-type dopant, such as phosphorus, is deposited over the surfaces 
and driven in to the exposed semiconductor material. This produces an 
N.sup.+ cathode region 24 in epitaxial layer 18 and an N.sup.+ anode 
short region 25 in N-type region 15. N.sup.+ regions 24 and 25 may 
advantageously have a sheet resistivity in the range of 0.5 to 2.0 ohms 
per square. Once again, regions 24 and 25 are produced simultaneously and 
will therefore have approximately identical characteristics. It is 
important that the thickness of N.sup.+ region 24 be approximately 5 
microns less than that of epitaxial layer 18 so that an N.sup.- region 
separates it from P-type base region 14. 
N.sup.+ cathode region 24 is placed in epitaxial layer 18 between P-type 
gate regions 21. The masks used are such that a gap 26 is left between the 
outer edges of cathode 24 and the inner edges of gates 21. Gap 26 may 
advantageously be approximately 1.25 mils wide. A range of 0.5-2 mils is 
believed to be acceptable. Gap 26 remains relatively lightly doped and 
serves to allow the gate/cathode reverse blocking field to spread. This 
serves to increase the reverse gate voltage capacity of the GTO switch. 
N.sup.+ anode short 25 is relatively large compared to P-type anode region 
22. In addition, anode short region 25 fills the gap between the 
relatively closely spaced P-type anode regions 22. This feature is found 
to be optional. 
FIG. 1D illustrates many features of the GTO switch according to the 
principles of the present invention. P-type base region 14 is a "buried" 
region. This provides for more accurate control over the resistivity of 
base region 14 than was provided by prior art double diffused processes. 
The low base sheet resistivity chosen provides excellent turn-off 
characteristics for the finished device. Further, the two-step diffusion 
process used to define cathode 24 and gate 21 is readily adaptable to 
produce a very lightly doped gap 26 between these regions. This provides a 
greater reverse gate voltage capacity than was provided with prior art 
devices. 
The remainder of the detailed description and the drawings are devoted to a 
description of the mask steps used in the process of making a GTO switch 
according to the principles of the present invention. Due to the 
relatively complex pattern of the masks, cross sectional views 
illustrating these masks would be unduly complicated. The basic pattern of 
the masks, which may be referred to as an involute spiral is discussed in 
some detail in U.S. Pat. No. 4,529,999 issued on July 16, 1985 and 
assigned to the assignee of the present invention. 
FIGS. 2A and 2B illustrate the masks used to open the oxide layers prior to 
the forming of P-type diffusions 21 and 22, respectively of FIG. 1C. As 
will be the convention used throughout, FIGS. 2A and 2B are shaded to 
indicate those areas in which oxide or other material remains after the 
patterning steps. Therefore, the P-type dopant is deposited in the 
unshaded regions of FIGS. 2A and 2B. 
In plan view, a GTO device according to the preferred embodiment occupies a 
square area approximately 210 mils on a side. FIG. 2A illustrates the gate 
pattern of the device. The gate (the unshaded region) comprises a central 
roughly circular region 30 from which a plurality of arms 31 extend in an 
involute spiral pattern. The outer edges 32 of the device also form a part 
of the gate. In the preferred embodiment of the invention, central region 
30 is approximately roughly 50 mils in diameter. Arms 31 are approximately 
9 mils wide. Arms 33, which separate arms 31 and will eventually form the 
cathode and gate-cathode gaps, are approximately 13 mils wide. Arms 33 are 
laid out to substantially fill a square region approximately 190 mils on a 
side centered of the die. The remainder of the upper surface of the die 
will be removed by the moat etch (FIG. 4). FIG. 2B illustrates the mask 
used to define anode diffusion 22 of FIG. 1C. It should be noted that the 
sense of rotation of the involute spiral pattern of FIG. 2B is reversed 
from that of FIG. 2A. Thus, when mask 2B is used on the reverse side of 
the wafer from the mask of FIG. 1A, the respective spiral patterns will 
coincide. The unshaded portions of the mask of FIG. 2B comprises a 
plurality of arms 34. In the preferred embodiment of the invention, arms 
34 are approximately 12 mils wide. Each arm 34 is broken up by regions 35 
in which the P-type dopant is prevented from being deposited on the 
semiconductor surface. This corresponds to the relatively small gap 
between P-type regions 22 in FIG. 1C. In the preferred embodiment of the 
present invention regions 35 run down the center of arms 34 and are 
approximately 4 mils wide. However, it has been found that the 
characteristics of the device are not significantly altered if regions 35 
are not included, that is, if arms 34 are solid. As noted above with 
respect to FIG. 1C, arms 34 are arranged to lie directly beneath arms 33 
in the pattern of FIG. 2A. This provides that the anode of the finished 
device directly underlies its cathode. 
Referring now to FIGS. 3A and 3B, the masks used to produce the cathode 24 
and anode short 25 diffusions of FIG. 1D are described. The cathode 
pattern, which comprises the unshaded portions of FIG. 3A, consists of a 
plurality of arms 38. Arms 38 are arranged to coincide with arms 33 of 
FIG. 2A. In the preferred embodiment, arms 38 are approximately 8 mils 
wide. This correspondence between arms 33 of FIG. 2A and arm 38 of FIG. 3A 
and the fact that arms 38 are narrower than arms 33 provide the 
cathode-gate relationship illustrated in cross-section in FIG. 1D. That 
is, each N.sup.+ cathode arm (arms 38) lies between and is spaced from 
two P-type gate arms (arms 31). 
The N.sup.+ anode short pattern, which corresponds to the unshaded 
portions of FIG. 3B, comprises the entire lower surface of the device but 
for the anode. The anode short region comprises a roughly circular central 
area 40, a plurality of involute spiral arms 41 extending from central 
area 40 and the entire outer edges 42 of the device. Arms 43, which define 
the areas in which oxide is left to protect the prior anode diffusion, are 
identical but for size with arms 34 of FIG. 2B. Arms 43 are approximately 
8 mils wide. Gaps 44 in arms 43, which correspond to areas 35 in FIG. 2B, 
are approximately 2 mils wide. Of course, if solid anode arms are used, 
arms 43 will similarly be solid. 
Referring now to FIG. 4, a mask is described which is used to etch the moat 
which surrounds each GTO switch. This moat is a well known device which 
serves to separate each device on the wafer. The moat typically extends 
from the upper surface of the device down to a point at which the N-type 
base region (region 15 of FIG. 1D) is exposed. The unshaded portion of 
FIG. 4 sets out the area in which the etchant is allowed to attack the 
semiconductor material and define the moat. The shaded central portion of 
the corresponds to the upper active surface of the finished device. Of 
course, the back side (the anode side) of the wafer is completely 
protected from the moat etch process. 
Referring now to FIG. 5, the mask used to pattern an isolation oxide layer 
is described. The isolation oxide layer to be patterned with the mask of 
FIG. 5. lies on the gate-cathode surface of the device. The goal is to 
place a band of isolation oxide on this surface around each of the cathode 
arms to provide isolation between the gate metallization and the cathode 
metallization. The shaded portion of the mask of FIG. 5 corresponds to 
those areas in which the oxide is left on the surface of the device after 
the patterning step. The mask of FIG. 5 comprises a plurality of inner 
arms 48 which correspond precisely in size and location to arms 38 of FIG. 
3A and a plurality of outer arms 49. Each outer arm 49 surrounds an inner 
arm 48. Outer arms 49 are approximately 14 mils wide. It is the space 
between each inner arm 48 and its corresponding outer arm 49 in which the 
isolation oxide is undisturbed by the patterning process. Once again the 
anode side of the wafer is not altered in this process step. 
Referring now to FIG. 6 a mask which is used to pattern a photoglass 
isolation layer is described. The mask of FIG. 6 is used to pattern a 
layer of photoglass which is used to passivate the edges of the various 
semiconductor layers which are exposed by the moat etch described above 
with regard to FIG. 4. The shaded area of the mask of FIG. 6 correspond to 
those areas of the photoglass layer which are undisturbed by the 
patterning process. As is apparent from a comparison of FIGS. 4 and 6, the 
photoglass layer is merely allowed to remain around the exposed edges of 
the device. This passivation technique is widely used in making GTO 
devices. 
The next step in the process used in the preferred embodiment of the 
present invention does not involve the use of a mask. This step in the 
process involves the gold doping of the device. Gold doping is a widely 
used process which acts to decrease the lifetime of mobile carriers in the 
semiconductor material so doped. It is widely known that gold doping may 
improve the performance of a GTO device. In the preferred embodiment of 
the present invention the gold doping takes place immediately after the 
passivation glass around the edges of the device has been patterned and 
fired. The gold is deposited by immersion plating over both surfaces of 
the wafer and diffused at a temperature of 875.degree. C. for a period of 
1 hour. Of course, it may be desirable in some circumstances to eliminate 
the gold doping step. In addition, diffusion temperatures in the range of 
750.degree. C. to 900.degree. C. may be appropriate. The next step in the 
process after gold doping is illustrated with respect to the mask of FIG. 
7. The mask of FIG. 7 is used to pattern the first of two metal layers 
used to make contact to the gate and cathode on the top of the device. 
This first metallization layer is also applied to the bottom surface of 
the device, but it not patterned there. A single metal layer on the bottom 
surface makes contact to both the anode and the anode short. 
In the preferred embodiment of the present invention the first 
metallization layer is aluminum which is deposited over the surface of the 
wafer and patterned on the top surface by means of the mask of FIG. 7. The 
shaded portions of FIG. 7 correspond to the portions of the aluminum layer 
remaining after the patterning step. The mask of FIG. 7 is identical to 
the mask of FIG. 5 but for the fact that one may be considered the 
negative of the other. Mask 7 comprises a plurality of inner arms 50 which 
have a width of approximately 8 mils and overlie the cathode diffusions 
and a plurality of outer arms 51 which have a width of approximately 14 
mils and surround inner arms 50. The aluminum layer is left on the surface 
of the device everywhere except between each inner arm 50 and its 
corresponding outer arm 51 (thus corresponding to the area of the 
isolation oxide patterned with the mask of FIG. 5) and around the edges of 
the device overlying the passivation photoglass. 
The next step in the process according to the preferred embodiment of the 
present invention comprises the deposition and patterning of a layer of 
polyimide overlaying the first metal layer. The polyimide is deposited by 
conventional means and patterned with the mask of FIG. 8. The shaded 
portions of the mask of FIG. 8 correspond to those areas in which the 
polyimide layer is unaffected by the patterning process. The unshaded 
portions of FIG. 8 correspond to openings in the polyimide layer through 
which contact may be made to the first metal layer. These openings 
comprise a plurality of arms 55 which have a width of approximately 8 mils 
and are arranged to overlie arms 50 of FIG. 7 and a central circular area 
56 which has a diameter of approximately 50 mils and overlie the central 
gate region 30 of FIG. 2A. Thus, the opening in the polyimide layer 
corresponding to central region 56 provides contact to the gate of the 
device and the openings corresponding to arms 55 allow contact to the 
cathode of the device. It should be noted that the inner end of each arm 
55 is separated from the outer edge of central region 56 by a distance of 
approximately 3 mils. 
The final step in the process according to the preferred embodiment of the 
present invention comprises the deposition and patterning of a second 
metal layer. The mask used to perform this patterning is illustrated in 
FIG. 9. The shaded portions of FIG. 9 correspond to those areas of the 
second metal layer which are unaffected by the patterning process. In the 
preferred embodiment of the present invention the second metal layer 
comprises a layer of Ti-Ni-Ag which is first evaporated over the entire 
surface of the device and then patterned with the mask of FIG. 9. As will 
be apparent from FIG. 9 two contact areas are thus defined by the second 
metal layer. A first contact area 57 overlies the majority of the device 
and provides contact through the polyimide layer to those portions of the 
first metal layer which overlie the cathode arms of the device. Second 
contact region 58 comprises a disk approximately 50 mils in diameter 
located in the center of the device and isolated from the first contact 
region by a gap of approximately 3 mils. Second contact 58 provides 
contact through the polyimide layer to the portion of the first metal 
layer overlaying the central region of the gate of the device. Thus are 
provided the necessary gate and cathode connections to the device. The 
Ti-Ni-Ag is also deposited over the Al layer on the back (anode) surface 
of the device, although no patterning takes place on the back side. The 
purpose is to enhance solderability to the anode surface. 
With reference to FIGS. 2A and 2B above, it should be noted that the width 
of arms 38 (the cathode diffusion) should be made as small as possible in 
order to increase the turn-off performance of the device. A range of 4-16 
mils may be appropriate for the particular device disclosed hereinabove. 
As will be apparent, up to this point an improved GTO switch and a method 
for the manufacture thereof have been disclosed. The method provides a 
ready means for precisely determining the base sheet resistance of such a 
GTO switch. In addition, a GTO switch having a relatively high reverse 
gate voltage capacity is provided.