Solid-state imaging device, method for driving solid-state imaging device and imaging apparatus

A solid state imaging device with pixels in a two-dimensional array, a controller which performs window cutting on signals read out of the pixel array in multiple column units on a column-address basis, and a selector which, when the cutting window overlaps with a multiple column unit, holds signals in a present multiple column unit and in a previous column unit, and then outputs selected consecutive signals.

CROSS REFERENCES TO RELATED APPLICATIONS

The present invention contains subject matter related to Japanese Patent Application JP 2006-019990 filed in the Japanese Patent Office on Jan. 30, 2006, the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a solid-state imaging device, a method for driving the solid-state imaging device and an imaging apparatus.

2. Description of the Related Art

In an solid-state imaging device of related art, such as a CMOS image sensor, to increase the signal output rate and reduce power consumption, when pixel data read from pixels are horizontally transferred, a plurality of columns in the pixel matrix array are used as a unit and the signals of the pixels in the plurality of columns are horizontally transferred and outputted in parallel on a row basis (see JP-A-2000-32344, for example).

In a CMOS image sensor configured to perform parallel transfer and output, for example, when the number of the plurality of columns is four, the number of outputs in horizontal transfer is four, that is, four outputs1,2,3and4. The signal of each column will be outputted according to the order of the columns to be transferred, 4n+1, 4n+2, 4n+3 and 4n+4 (n is an integer).

SUMMARY OF THE INVENTION

However, in the related art, when so-called window cutting, in which signals are read from the pixels in a specific area in the pixel matrix array, is performed, and the signal of the first pixel in the thus cut window is outputted as the output1in order to simplify signal processing in a downstream signal processing system, the cutting unit may be always limited to a multiple of 4, so that the pixel unit of the window to be cut becomes disadvantageously coarse.

Thus, it is desirable to provide a solid-state imaging device that is configured to perform parallel transfer and output and can achieve window cutting using a unit smaller than a multiple-column unit independent of the parallel output start position and the number of parallel outputs. It is also desirable to provide a method for driving the solid-state imaging device and an imaging apparatus.

According to an embodiment of the invention, there is provided a solid-state imaging device including: a pixel array unit formed of pixels two-dimensionally arranged in a matrix, each having a photoelectric converter, and outputs the signals read from the pixels in the pixel array unit in parallel on a multiple-column basis. When window cutting, in which signals are read from the pixels in a specific area in the pixel array unit, is performed on a column-address basis such that the window overlaps with the multiple-column unit, the signals read from the pixels in the present column-address unit and the signals read from the pixels in the preceding column-address unit are held, from which consecutive signals on the multiple-column basis are selected and outputted.

In the solid-state imaging device that outputs the signals of pixels in parallel on a multiple-column basis, since consecutive signals on the multiple-column basis can be selected from the signals of the present column-address unit and the preceding column-address unit, window cutting can be performed on a column-address basis such that the window overlaps with the multiple-column unit even when the cutting unit is not a multiple of the multiple-column unit.

According to an embodiment of the invention, since the window cutting can be performed without limiting the cutting unit to a multiple of a multiple-column unit, the window cutting can be performed using a unit smaller than the multiple-column unit independent of the parallel output start position and the number of parallel outputs.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the invention will be described below in detail with reference to the drawings.

FIG. 1is a schematic block diagram showing the solid-state imaging device according to one embodiment of the invention. In this embodiment, the solid-state imaging device will be described with reference to a CMOS image sensor.

As shown inFIG. 1, the solid-state imaging device according to this embodiment includes a pixel array unit11, a row scan circuit12, a column signal processing circuit13, a column scan circuit14, bus lines15, a hold circuit16and a selector unit17. These components are mounted on a single semiconductor substrate (chip)18.

The pixel array unit11includes pixels20two-dimensionally arranged in a matrix, each having a photoelectric converter. A vertical signal line111is wired to each column in the matrix pixel arrangement, and one or more drive control lines are wired to each row. The configuration of the pixel20will not be described in detail because it is not associated with the feature of the invention.FIG. 1only shows pixels in eight columns H1to H8in a certain row for clarity of the figure.

In the solid-state imaging device according to this embodiment, in order to increase the signal output rate and reduce power consumption, the pixel array unit11is configured such that when pixel data read from pixels20are horizontally transferred, a plurality of columns of the pixel matrix arrangement, for example, four columns, are used as a unit and the signals of the pixels in the four columns are horizontally transferred and outputted in parallel on a row basis (four parallel outputs).

The row scan circuit12includes a shift register, an address decoder or the like, and selects and scans each pixel20in the pixel array unit11on a row basis. The column signal processing circuit13includes a plurality of column circuits131, for example, arranged for each pixel column in the pixel array unit11, that is, arranged such that one column circuit131corresponds to one pixel column, performs a predetermined signal processing on the signal outputted via the vertical signal line111from each pixel20in the row selected when the row scan circuit12performs a scan, and temporarily holds the pixel signal that underwent the signal processing.

More specifically, the column circuits131receive analog signals outputted from the pixels20in one row selected by the row scan circuit12in such a way that each column circuit131receives the analog signal for each pixel column, simultaneously convert the analog signals from that one row into digital signals, and perform signal processing, such as CDS (Correlated Double Sampling) for removing pixel-specific fixed pattern noise and signal amplification.

The digital signals that underwent the signal processing are outputted out of the semiconductor substrate18by a horizontal transfer operation performed by the column scan circuit14, the four bus lines15-1to15-4corresponding to the four parallel outputs, the hold circuit16and the selector unit17. From the outside of the semiconductor substrate18, the upper bits of a column selection address that specify column addresses are inputted to the column scan circuit14and the lower bits of the column selection address are inputted to the selector unit17.

The upper bits of the column selection address select four columns as one unit corresponding to the four parallel outputs, while the lower bits of the column selection address select individual columns in the four columns selected by the upper bits.

The column scan circuit14includes, for example, an address decoder and uses the upper bits of the column selection address inputted from a controller (not shown) external to the semiconductor substrate18to select the column circuits131in the corresponding columns. In this example, since the digital data that underwent the signal processing in the column signal processing circuit13are transferred and outputted in the four-parallel fashion, the column scan circuit14selects and scans four column circuits131as a unit.

When the column scan circuit14selects and scans four column circuits131, these four column circuits131output digital data onto the four bus lines15-1to15-4corresponding to the four parallel outputs. The upper bits of the column selection address are incremented for each unit clock for the transfer operation in which digital data are outputted. As a result, the column scan circuit14performs the selection and scan operation for each unit clock, and the selected four column circuits131output digital data onto the bus lines15-1to15-4.

The hold circuit16has a two-stage configuration in which four front flip-flops FF1to FF4and four subsequent flip-flops FF5to FF8that are provided to support the four-parallel operation and are connected in a tandem manner, respectively. The front flip-flops FF1to FF4and the subsequent flip-flops FF5to FF8sequentially hold digital data outputted onto the bus lines15-1to15-4in synchronization with the transfer unit clock.

As a result, the front flip-flops FF1to FF4hold the digital data outputted from the column signal processing circuit13in the selection and scan operation performed by the column scan circuit14using the preceding column-address unit, while the subsequent flip-flops FF5to FF8hold the digital data outputted from the column signal processing circuit13in the selection and scan operation performed by the column scan circuit14using the present column-address unit. That is, the hold circuit16holds 8-column digital data, which correspond to 2 unit clocks, that is, 8-pixel digital data.

The selector unit17receives the outputs from the front flip-flops FF1to FF4and the subsequent flip-flops FF5to FF8, and among the digital data held in the flip-flops FF1to FF8, outputs the digital data held in the flip-flops selected by the lower bits of the column selection address as the outputs1to4.

FIG. 2is a block diagram showing one example of the specific configuration of the selector unit17. As shown inFIG. 2, the selector unit17includes a group of ascending-order selectors17A, a group of descending-order selectors17B and a switch17C that selectively provides the lower bits of the column selection address either to the group of ascending-order selectors17A or the group of descending-order selectors17B based on an ascending order/descending order switch signal provided from outside.

The group of ascending-order selectors17A includes four selectors171to174provided to support the four-parallel operation. The selector171receives the digital data held in the flip-flops FF1to FF4as four inputs HSS1to HSS4and outputs one input from the four inputs HSS1to HSS4selected by the lower bits of the column selection address, that is, any one of the digital data in the flip-flops FF1to FF4, as the output1.

The selector172receives the digital data held in the flip-flops FF2to FF5as four inputs HSS1to HSS4and outputs one input from the four inputs HSS1to HSS4selected by the lower bits of the column selection address, that is, any one of the digital data in the flip-flops FF2to FF5, as the output2.

The selector173receives the digital data held in the flip-flops FF3to FF6as four inputs HSS1to HSS4and outputs one input from the four inputs HSS1to HSS4selected by the lower bits of the column selection address, that is, any one of the digital data in the flip-flops FF3to FF6, as the output3.

The selector174receives the digital data held in the flip-flops FF4to FF7as four inputs HSS1to HSS4and outputs one input from the four inputs HSS1to HSS4selected by the lower bits of the column selection address, that is, any one of the digital data in the flip-flops FF4to FF7, as the output4.

In the group of ascending-order selectors17A configured as described above, when the lower bits of the column selection address provided via the switch17C select the inputs HSS1of the selectors171to174, the digital data in the flip-flops FF1to FF4are outputted from the selectors171to174as the outputs1to4.

Similarly, when the lower bits of the column selection address select the inputs HSS2, the digital data in the flip-flops FF2to FF5are outputted from the selectors171to174as the outputs1to4. When the inputs HSS3are selected, the digital data in the flip-flops FF3to FF6are outputted from the selectors171to174as the outputs1to4. When the inputs HSS4are selected, the digital data in the flip-flops FF4to FF7are outputted from the selectors171to174as the outputs1to4.

That is, when the lower bits of the column selection address select the same inputs from the four inputs HSS1to HSS4, the selectors171to174output the digital data in the flip-flops FF1to FF7that hold digital data of the consecutive pixels in the ascending order in the direction the columns are arranged as the outputs1to4. The four inputs HSS1to HSS4of the selectors171to174corresponding to the outputs1to4are arranged such that the digital data in the flip-flops FF1to FF7that hold digital data of the consecutive pixels in the ascending order can be sequentially selected.

More specifically, consider now that pixel data are outputted in parallel on a four-column (four-pixel) basis in the ascending-order scan in the direction the columns are arranged (the left-to-right scan inFIG. 1) and let1,2,3,4,5,6,7, . . . be the signals of the pixels from the left in a certain row in the figure. Pixel data are selectively outputted in parallel not only on a four-column basis but also on a column-address basis in which the column address overlaps with the four-column unit, that is, when the inputs HSS1are selected, “1,2,3,4”, “5,6,7,8”, . . . are outputted; when the inputs HSS2are selected, “2,3,4,5”, “6,7,8,9”, . . . are outputted; when the inputs HSS3are selected, “3,4,5,6”, “7,8,9,10”, . . . are outputted; and when the inputs HSS4are selected, “4,5,6,7”, “8,9,10,11”, . . . are outputted.

The group of descending-order selectors17B includes four selectors175to178provided to support the four-parallel operation. The selector175receives the digital data held in the flip-flops FF8to FF5as the four inputs HSS1to HSS4and outputs one input from the four inputs HSS1to HSS4selected by the lower bits of the column selection address, that is, any one of the digital data in the flip-flops FF8to FF5, as the output1.

The selector176receives the digital data held in the flip-flops FF7to FF4as the four inputs HSS1to HSS4and outputs one input from the four inputs HSS1to HSS4selected by the lower bits of the column selection address, that is, any one of the digital data in the flip-flops FF7to FF4, as the output2.

The selector177receives the digital data held in the flip-flops FF6to FF3as the four inputs HSS1to HSS4and outputs one input from the four inputs HSS1to HSS4selected by the lower bits of the column selection address, that is, any one of the digital data in the flip-flops FF6to FF3, as the output3.

The selector178receives the digital data held in the flip-flops FF5to FF2as the four inputs HSS1to HSS4and outputs one input from the four inputs HSS1to HSS4selected by the lower bits of the column selection address, that is, any one of the digital data in the flip-flops FF5to FF2, as the output4.

In the group of descending-order selectors17B configured as described above, when the lower bits of the column selection address provided via the switch17C select the inputs HSS1of the selectors175to178, the digital data in the flip-flops FF8to FF5are outputted from the selectors175to178as the outputs1to4.

Similarly, when the lower bits of the column selection address select the inputs HSS2, the digital data in the flip-flops FF7to FF4are outputted from the selectors175to178as the outputs1to4. When the inputs HSS3are selected, the digital data in the flip-flops FF6to FF3are outputted from the selectors175to178as the outputs1to4. When the inputs HSS4are selected, the digital data in the flip-flops FF5to FF2are outputted from the selectors175to178as the outputs1to4.

That is, when the lower bits of the column selection address select the same inputs from the four inputs HSS1to HSS4, the selectors175to178output the digital data in the flip-flops FF1to FF7that hold digital data of the consecutive pixels in the descending order in the direction the columns are arranged as the outputs1to4. The four inputs HSS1to HSS4of the selectors175to178corresponding to the outputs1to4are arranged such that the digital data in the flip-flops FF1to FF7that hold digital data of the consecutive pixels in the descending order can be sequentially selected.

More specifically, consider now that pixel data are outputted in parallel on a four-column basis in the descending-order scan in the direction the columns are arranged (the right-to-left scan inFIG. 1) and let16,15,14,13,12,11,10, . . . be the signals of the pixels from the right in a certain row in the figure. Pixel data are selectively outputted in parallel not only on a four-column basis but also on a column-address basis in which the column address overlaps with the four-column unit, that is, when the inputs HSS1are selected, “16,15,14,13”, “12,11,10,9”, . . . are outputted; when the inputs HSS2are selected, “15,14,13,12”, “11,10,9,8”, . . . are outputted; when the inputs HSS3are selected, “14,13,12,11”, “10,9,8,7”, . . . are outputted; and when the inputs HSS4are selected, “13,12,11,10”, “9,8,7,6”, . . . are outputted.

A solid-state imaging device according to this embodiment configured as described above is designed to perform window cutting in which the signals of the pixels20are read from a specific area in the pixel array unit11. To specify a window area to be cut, the row scan circuit12and the column scan circuit14specify the row address and the column address, respectively. That is, the row scan circuit12and the column scan circuit14form a control unit (control means set forth in the claims) for performing window cutting.

The hold circuit16and the selector unit17form a selection unit (selection means set forth in the claims) for, when the window cutting is performed on a column-address basis in which the column address overlaps with the multiple-column unit (four-column unit, in this example), holding the pixel data read from pixels in the present column-address unit and the pixel data read from pixels in the preceding column-address unit, and selecting and outputting consecutive pixel data on a four-column basis from the thus held pixel data of the present column-address unit and the preceding column-address unit.

By way of example, in the solid-state imaging device that outputs pixel data in parallel on a four-column basis, a description will be made of the operation in which window cutting is performed on a column-address basis in which the column address overlaps with the four-column unit so as to perform horizontal transfer-based parallel output in the ascending-order scan (forward scan) starting from the pixel in the column H3.

Firstly, when the upper bits of the column selection address are inputted to turn the output HSM1of the column scan circuit14active, the pixel data of the columns H1to H4that form a unit are outputted onto the bus lines15-1to15-4, respectively.

Next, when the upper bits of the column selection address are incremented at the timing of the unit clock for the next transfer so as to turn the output HSM2of the column scan circuit14active, the pixel data of the columns H5to H8that form the next unit are outputted onto the data buses15-1to15-4, respectively, and at the same time, the pixel data of the columns H1to H4outputted onto the bus lines15-1to15-4at the preceding unit clock are held in the subsequent flip-flops FF5to FF8in the hold circuit16.

At the timing of the unit clock for the next transfer, the pixel data of the columns H1to H4held in the subsequent flip-flops FF5to FF8, that is, the pixel data of the preceding column-address unit, are moved to the front flip-flops FF1to FF4, and the pixel data of the columns H5to H8, that is, the pixel data of the present column-address unit, are newly held in the subsequent flip-flops FF5to FF8.

In this description, since the horizontal transfer direction corresponds to the ascending order, inFIG. 2, the switch17C delivers the lower bits of the column selection address inputted from outside to the group of ascending-order selectors17A. Prior to this operation, the address that selects the inputs HSS3of the selectors171to174in the group of ascending-order selectors17A is outputted to the lower bits of the column selection address.

Then, the selector171outputs the pixel data held in the flip-flop FF3, that is, the pixel data of the column H3, as the output1. The selectors172,173and174output the pixel data of the column H4as the output2, the pixel data of the column H5as the output3and the pixel data of the column H6as the output4, respectively.

Consequently, window cutting is performed on a column-address basis in which the column address overlaps with the four-column unit in the ascending-order scan (forward scan) starting from the pixel in the column H3. Once the cutting address is fixed, it is not necessary to change the lower bits of the column selection address for each unit clock.

Thus, in the solid-state imaging device that outputs pixel data in parallel on a multiple-column basis (four-column basis, in this example), the hold circuit16holds pixel data read from pixels in the present column-address unit and pixel data read from pixels in the preceding column-address unit, and the group of ascending-order selectors17A selects and outputs consecutive pixel data on a multiple-column basis from the thus held pixel data of the present column-address unit and the preceding column-address unit, so that window cutting can be performed on a column-address basis in which the column address overlaps with the multiple-column unit without limiting the cutting unit to a multiple of the multiple-column unit, allowing window cutting using a unit smaller than the multiple-column unit independent of the parallel output start position and the number of parallel outputs.

In this example, although the description has been made with reference to the case where the cutting is performed on a column-address basis in which the column address overlaps with the multiple-column unit, when the cutting is performed such that the column address does not overlap with the multiple-column unit, the window cutting can be achieved by using only the pixel data held in the front flip-flops FF1to FF4provided that the selectors171to174in the group of selectors17A are connected to the flip-flops FF1to FF8as shown inFIG. 2.

It should be noted thatFIG. 2shows only one example of how the selectors171to174are connected. By changing the form of connection, it is also possible to perform window cutting by using only the pixel data held in the subsequent flip-flops FF5to FF8.

In the solid-state imaging device that outputs pixel data in parallel on a four-column basis, a description will now be made of the operation in which the window cutting is performed to carry out horizontal transfer-based parallel output in the descending-order scan (backward scan) starting from the pixel in the column H8.

Since the window cutting in this case is performed such that the window does not overlap with the multiple-column unit, the window cutting is achieved by using only the pixel data held in the subsequent flip-flops FF5to FF8provided that the selectors175to178in the group of selectors17B are connected to the flip-flops FF1to FF8as shown inFIG. 2.

It should be noted thatFIG. 2shows only one example of how the selectors175to178are connected. By changing the form of connection, it is also possible to perform window cutting by using only the pixel data held in the front flip-flops FF1to FF4.

Firstly, when the upper bits of the column selection address are inputted to turn the output HSM2of the column scan circuit14active, the pixel data of the columns H5to H8that form a unit are outputted onto the bus lines15-1to15-4, respectively, and held in the subsequent flip-flops FF5to FF8in the hold circuit16via the bus lines15-1to15-4.

In this description, since the horizontal transfer direction corresponds to the descending order, inFIG. 2, the switch17C delivers the lower bits of the column selection address inputted from outside to the group of descending-order selectors17B. Prior to this operation, the address that selects the inputs HSS1of the selectors175to178in the group of descending-order selectors17B is outputted to the lower bits of the column selection address.

Then, the selector175outputs the pixel data held in the flip-flop FF8, that is, the pixel data of the column H8, as the output1. The selectors176,177and178output the pixel data of the column H7as the output2, the pixel data of the column H6as the output3and the pixel data of the column H5as the output4, respectively.

Next, when the upper bits of the column selection address are incremented at the timing of the unit clock for the next transfer so as to turn the output HSM1of the column scan circuit14active, the pixel data of the columns H1to H4that form the next unit are outputted onto the data buses15-1to15-4, respectively, and held in the subsequent flip-flops FF5to FF8in the hold circuit16via the bus lines15-1to15-4.

Then, when the selectors175to178select the inputs HSS1, the selector175outputs the pixel data held in the flip-flop FF8, that is, the pixel data of the column H4, as the output1. The selectors176,177and178output the pixel data of the column H3as the output2, the pixel data of the column H2as the output3and the pixel data of the column H1as the output4, respectively.

Consequently, window cutting is performed on a column-address basis in which the column address does not overlap with the four-column unit in the descending-order scan (backward scan) starting from the pixel in the column H8. Once the cutting address is fixed, it is not necessary to change the lower bits of the column selection address for each unit clock, as in the ascending-order scan.

In related art in which the group of descending-order selectors17B is not incorporated, when the pixel in the column H8is used as the starting point to perform window cutting in the descending-order scan, pixel data are outputted on an ascending-order transfer basis although it is intended to perform descending-order transfer, because the columns corresponding to the outputs1to4are fixed, that is, the pixel data of the columns5,6,7and8are first outputted as the outputs1to4, and the pixel data of the columns1,2,3and4are then outputted.

Although the above description was made of the case where the window cutting is performed such that the window does not overlap with the multiple-column unit, when the window cutting is performed on a column-address basis in which the column address overlaps with the multiple-column unit, the pixel data held in the front flip-flops FF1to FF4and the subsequent flip-flops FF5to FF8may be used and the group of descending-order selectors17B is used to select and output consecutive pixel data on a multiple-column basis from the thus held pixel data of the present column-address unit and the preceding column-address unit, as in the ascending-order scan.

As described above, by using the selectors175to178in the group of descending-order selectors17B to invert the order of the pixel data of the present column-address unit held in the subsequent flip-flops FF5to FF8(or the pixel data of the preceding column-address unit held in the front flip-flops FF1to FF4), the pixel data can be outputted on the descending-order transfer basis as the outputs1to4. Therefore, when window cutting is performed in the descending-order scan, pixel data can be outputted in parallel in the order in which the pixels arranged in the pixel array unit11are scanned, as in the window cutting in the ascending-order scan.

Thus, in the solid-state imaging device that outputs pixel data in parallel on a multiple-column basis (four-column basis, in this example), when window cutting is performed in the descending-order scan, pixel data can be outputted in parallel in the scanning order of the pixel arrangement. Therefore, it is not necessary sort the order of the signals according to the pixel arrangement in the following signal processing system, thereby contributing to reduced burden on the following signal processing system and a simplified configuration of the following signal processing system.

Particularly, the hold circuit16and the selector unit17are mounted on the same semiconductor substrate (chip)18as the pixel array unit11, the row scan circuit12, the column signal processing circuit13, the column scan circuit14, the bus lines15and the like, and pixel data can be outputted in parallel in the order in which pixels arranged in the pixel array unit11are scanned, so that even when window cutting is performed in the descending-order scan, the ascending order scan-based existing IC corresponding to parallel outputs can be advantageously used without any modification as a signal processing IC that forms the signal processing system external to the substrate.

As shown inFIG. 3, the pixel array unit11typically includes not only an effective pixel area (open pixel area)11A in which the signal from each pixel20is used as an imaging signal but also an optical black area11B, disposed at the periphery of the effective pixel area11A, in which the pixels are shielded and signals from the pixels are not used as imaging signals but are used to determine the reference level of imaging signals.

Pixel signals are regularly read from the optical black area11B whether or not window cutting is performed in a horizontal transfer operation. Therefore, when window cutting is performed, signals are first read from pixels in the optical black area11B, and signals are then read from the pixels in the window cutting area.

FIG. 4is a block diagram showing the main portion of the configuration designed to read signals from pixels in the optical black area11B. The selector17shown inFIG. 4corresponds to the selector17shown inFIG. 1.

The configuration shown inFIG. 4is characterized by a specific configuration of an address control circuit30that controls the lower bits of the column selection address to be provided to the selector unit17. Specifically, the address control circuit30includes an optical black output counter31, an optical black area information setting section32, a comparator33and a selector34.

The optical black output counter31receives a horizontal transfer start signal when horizontal transfer is initiated for each row. The optical black output counter31performs a count operation on a pixel basis when pixel data in the optical black area11B is read out. The optical black area information setting section32sets the number of pixels in the direction in which the columns are arranged (horizontal direction) in the optical black area11B.

The comparator33receives the count value of the optical black output counter31as comparative input, receives the number of pixels set by the optical black area information setting section32as comparative reference input, and determines that the readout of the pixels (horizontal transfer output) in the optical black area11B is completed when the count value of the optical black output counter31exceeds the number of pixels set by the optical black area information setting section32.

The selector34selects zero input for the optical black area11B and supplies it to the selector unit17. In this way, the readout of the optical black area11B, which is a fixed area, is performed. When the comparator33determines that the readout of the pixels in the optical black area11B has been completed, the comparator33selects the lower bits of the column selection address and supplies them to the selector unit17in response to the determination result. In this way, the window cutting operation described above can be performed.

Thus, in the solid-state imaging device having the optical black area11B in the pixel array unit11, an identification unit formed of the optical black output counter31and the comparator33automatically identifies whether the readout is from pixels inside the optical black area11B or pixels outside the optical black area11B, and window cutting is performed after the pixels in the optical black area11B are read out. Therefore, window cutting can be performed without using an external control system to count the internal timing of the sensor (solid-state imaging device), thereby reducing the burden on the external control system.

In the above embodiment, although the description has been made with reference to the case where the group of ascending-order selectors17A and the group of descending-order selectors17B are provided to support the ascending-order and descending-order scans, it is possible to employ a configuration in which only one of the group of ascending-order selectors17A and the group of descending-order selectors17B is provided to support only the ascending-order scan or the descending-order scan.

In the above embodiment, although the description has been made with reference to the case where the invention is applied to a CMOS image sensor, the invention is not limited thereto. The invention can be similarly applied to other X-Y addressing-type solid-state imaging devices different from CMOS image sensors, as well as charge coupled-type solid-state imaging devices represented by a CCD (Charge Coupled Device) image sensor.

When the invention is applied to a charge coupled-type solid-state imaging device, such as a CCD image sensor, the invention can be implemented by providing a plurality of horizontal transfer sections corresponding to the number of columns for parallel outputs and assigning the functions of the hold circuit16and the selector unit17(seeFIG. 1) to the output stages of the plurality of horizontal transfer sections, or assigning the functions of the hold circuit16and the selector unit17to the subsequent stages of a plurality of charge detectors that convert signal charges transferred by the plurality of the horizontal transfer sections into electric signals.

The solid-state imaging device according to the above embodiment is suitable when used as an imaging device in an imaging apparatus, such as a digital still camera and video camcorder.

The imaging apparatus used herein refers to a camera module including a solid-state imaging device as the imaging device, an optical system that focuses image light from a subject onto the imaging plane (light reception plane) of the solid-state imaging device and a signal processing circuit of the solid-state imaging device, as well as a camera system, such as a digital still camera and a video camcorder equipped with the camera module.

FIG. 5is a block diagram showing an exemplary configuration of the imaging apparatus according to an embodiment of the invention. As shown inFIG. 5, the imaging apparatus according to this example includes an optical system having a lens41, an imaging device42and a camera signal processing circuit43.

The lens41focuses image light from a subject onto the imaging plane of the imaging device42. The imaging device42converts the image light focused on the imaging plane by the lens41into an electric signal on a pixel basis and outputs the resultant image signal. The solid-state imaging device according to the embodiment described above is used as the imaging device42. The camera signal processing circuit43performs various types of signal processing on the image signal outputted from the imaging device42.

As described above, in an imaging apparatus, such as a video camcorder and an electronic still camera as well as a camera module for a mobile instrument, such as a mobile phone, by using the solid-state imaging device according to the embodiment described above as the imaging device42, window cutting can be performed in the solid-state imaging device on a column-address basis in which the column address overlaps with the multiple-column unit without limiting the cutting unit to a multiple of the multiple-column unit, advantageously allowing window cutting using a unit smaller than the multiple-column unit.

In the solid-state imaging device according to the embodiment described above, when window cutting is performed in the descending-order scan, pixel data can be outputted in parallel in the scanning order of the pixel arrangement. Therefore, it is not necessary to sort the order of the signals according to the pixel arrangement outside the device, providing another advantage of reduced burden on the camera signal processing circuit43and a simplified configuration of the camera signal processing circuit43.