3D HIGH DENSITY SELF-ALIGNED NANOSHEET DEVICE FORMATION WITH EFFICIENT LAYOUT AND DESIGN

A method of microfabrication includes forming an initial stack of semiconductor layers by epitaxial growth over a substrate. The initial stack of semiconductor layers is surrounded by a sidewall structure. The initial stack of semiconductor layers includes channel structures and sacrificial gate layers stacked alternatingly in a vertical direction substantially perpendicular to a working surface of the substrate. The channel structures include a first channel structure and a second channel structure positioned above the first channel structure. First portions of the sidewall structure are removed to uncover first sides of the initial stack. Source/drain (S/D) regions are formed on uncovered side surfaces of the channel structures from the first sides of the initial stack. Second portions of the sidewall structure are removed to uncover second sides of the initial stack. The sacrificial gate layers are replaced with gate structures from the second sides of the initial stack.

FIELD OF THE INVENTION

This disclosure relates to microelectronic devices including semiconductor devices, transistors, and integrated circuits, and methods of microfabrication.

BACKGROUND

In the manufacture of a semiconductor device (especially on the microscopic scale), various fabrication processes are executed such as film-forming depositions, etch mask creation, patterning, material etching and removal, and doping treatments. These processes are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, with microfabrication, transistors have been created in one plane, with wiring/metallization formed above the active device plane, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes. Semiconductor device fabricators have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other.

SUMMARY

The present disclosure relates to a semiconductor device and a method of microfabrication.

Aspect (1) includes a method of microfabrication. The method includes forming an initial stack of semiconductor layers by epitaxial growth over a substrate. The initial stack of semiconductor layers includes channel structures and sacrificial gate layers stacked alternatingly in a vertical direction substantially perpendicular to a working surface of the substrate. The channel structures include a first channel structure and a second channel structure positioned above the first channel structure. The initial stack of semiconductor layers is surrounded by a sidewall structure. First portions of the sidewall structure are removed to uncover first sides of the initial stack. Source/drain (S/D) regions are formed on uncovered side surfaces of the channel structures from the first sides of the initial stack. Second portions of the sidewall structure are removed to uncover second sides of the initial stack. The sacrificial gate layers are replaced with gate structures from the second sides of the initial stack.

Aspect (2) includes the method of Aspect (1), wherein the forming the S/D regions includes forming a protective structure to cover respective side surfaces of the second channel structure from the first sides of the initial stack. First S/D regions of the S/D regions are formed on respective side surfaces of the first channel structure.

Aspect (3) includes the method of Aspect (1), further including depositing a first filler material to cover the respective side surfaces of the first channel structure from the first sides of the initial stack. The protective structure is formed over the first filler material while leaving the first filler material partially uncovered. The first filler material is selectively etched to uncover the respective side surfaces of the first channel structure.

Aspect (4) includes the method of Aspect (1), wherein the forming the protective structure includes depositing a second filler material over the first filler material to cover the respective side surfaces of the second channel structure. The first filler material and the second filler material are etch selective to each other. The second filler material is directionally etched to partially uncover the first filler material such that a remaining portion of the second filler material forms the protective structure.

Aspect (5) includes the method of Aspect (1), further including removing the protective structure and forming second S/D regions of the S/D regions on the respective side surfaces of the second channel structure.

Aspect (6) includes the method of Aspect (1), wherein the sacrificial gate layers include one or more first sacrificial gate layers in direct contact with the first channel structure and one or more second sacrificial gate layers in direct contact with the second channel structure. The replacing the sacrificial gate layers with the gate structures includes forming a protective structure to cover respective side surfaces of the one or more second sacrificial gate layers from the second sides of the initial stack. The one or more first sacrificial gate layers are replaced with one or more first gate structures.

Aspect (7) includes the method of Aspect (6), further including removing the protective structure and replacing the one or more second sacrificial gate layers with one or more second gate structures.

Aspect (8) includes the method of Aspect (7), further including forming an isolation structure between the one or more first gate structures and the one or more second gate structures.

Aspect (9) includes the method of Aspect (6), wherein the removing the second portions of the sidewall structure includes removing upper parts of the second portions of the sidewall structure before the forming the protective structure. Lower parts of the second portions of the sidewall structure are removed after the forming the protective structure.

Aspect (10) includes the method of Aspect (1), further including forming indentations by removing end portions of the sacrificial gate layers from the first sides of the initial stack. Inner spacers are formed in the indentations.

Aspect (11) includes the method of Aspect (1), wherein the replacing the sacrificial gate layers with the gate structures includes forming gate structures all around respective channel structures.

Aspect (12) includes the method of Aspect (1), wherein the replacing the sacrificial gate layers with the gate structures includes forming at least one gate dielectric of the gate structures over uncovered portions of the channel structures. At least one work function metal (WFM) of the gate structures is formed over the at least one gate dielectric.

Aspect (13) includes the method of Aspect (12), wherein the forming the at least one gate dielectric of the gate structures includes selectively depositing the at least one dielectric on the uncovered portions of the channel structures.

Aspect (14) includes the method of Aspect (1), wherein the forming the initial stack of semiconductor layers includes forming a first layer of a first dielectric material on a surface of a first semiconductor material over the substrate. An initial opening is formed within the first layer. The initial opening uncovers the first semiconductor material. The sidewall structure is formed within the initial opening such that the first semiconductor material is uncovered by an inner opening through the sidewall structure. The sidewall structure includes a second dielectric material. The initial stack of semiconductor layers is formed within the inner opening.

Aspect (15) includes the method of Aspect (1), wherein the S/D regions are formed on the uncovered side surfaces of the channel structures by epitaxial growth.

Aspect (16) includes a semiconductor device. The semiconductor device includes a stack of transistors stacked over a substrate in a direction substantially perpendicular to a working surface of the substrate. Each transistor includes a respective channel structure, respective source/drain (S/D) regions positioned on ends of the respective channel structure, and a respective gate structure disposed all around the respective channel structure. Respective channel structures of at least two transistors include different chemical compositions.

Aspect (17) includes the semiconductor device of Aspect (16), wherein at least one transistor includes a plurality of channel structures. Respective S/D regions of the at least one transistor are configured to electrically connect to the plurality of channel structures.

Aspect (18) includes the semiconductor device of Aspect (16), wherein at least one transistor includes a plurality of channel structures. A respective gate structure of the at least one transistor is disposed all around the plurality of channel structures.

Aspect (19) includes the semiconductor device of Aspect (16), further including inner spacers disposed between the gate structures and respective S/D regions.

Aspect (20) includes the semiconductor device of Aspect (19), wherein at least one gate structure includes a work function metal (WFM) and a gate dielectric. The WFM is separated from an adjacent respective S/D region, in a direction substantially parallel to the working surface of the substrate, by a respective inner spacer alone or by the respective inner spacer and the gate dielectric.

Note that this summary section does not specify every embodiment and/or incrementally novel aspect of the present disclosure or claimed invention. Instead, this summary only provides a preliminary discussion of different embodiments and corresponding points of novelty. For additional details and/or possible perspectives of the invention and embodiments, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

3D integration, i.e. the vertical stacking of multiple devices, aims to overcome scaling limitations experienced in planar devices by increasing transistor density in volume rather than area. Although device stacking has been successfully demonstrated and implemented by the flash memory industry with the adoption of 3D NAND, application to random logic designs is substantially more difficult. 3D integration for logic chips (CPU (central processing unit), GPU (graphics processing unit), FPGA (field programmable gate array, SoC (System on a chip)) is being pursued.

Techniques herein provide methods and designs for self-aligned nanosheets that enable higher density circuits to be produced at reduced cost. Techniques include starting with isolation first, which is prior to nanosheet growth that provides for compact and efficient 3D nanosheet devices. This process eliminates a need for the dummy gate process, and also provides a 3D device with reduced process steps.

Techniques herein enable spacers to be placed adjacent to the channel to maximize the performance of the 3D transistors. In some embodiments, two sides of the top view have one dielectric that is selective to the perpendicular two sides. This feature enables both channel release and S/D formation to be achieved with reduced masking layers as well as being self-aligned. Examples in the illustrations show a N=4 nanosheet stack (i.e. a stack including 4 nanosheets) with the S/D regions combined for the stacked NMOS and PMOS regions, and side by side NMOS/PMOS flows. Note, however, that embodiments can be N tall with any device order. Embodiments also cover a single channel with one epitaxial S/D regions as a device.

FIG.1Ashows a top view of a semiconductor device100A, in accordance with one embodiment of the present disclosure.FIGS.1B and1Crespectively show vertical cross-sectional views taken along the line cuts AA′ and BB′ inFIG.1A, in accordance with some embodiments of the present disclosure.

The semiconductor device100A includes at least one stack140A of transistors (e.g.110A and120A) stacked over a substrate101in a direction (e.g. the Z direction) substantially perpendicular to a working surface of the substrate101. Each transistor can include at least one respective channel structure (e.g.111and121), respective source/drain (S/D) regions (e.g.115and125) positioned on respective ends of the at least one respective channel structure, and at least one respective gate structure (e.g.113and123) disposed all around the at least one respective channel structure.

In a non-limiting example, the semiconductor device100A can include a first transistor110A and a second transistor120A. Specifically, the first transistor110A includes one or more (e.g. two) first channel structures111, first S/D regions115and at least one first gate structure113while the second transistor120A includes one or more (e.g. two) second channel structures121, second S/D regions125and at least one second gate structure123. Since the first transistor110A is similar to the second transistor120A, consider the first transistor110A for example. In the examples ofFIGS.1A-1Cthe first S/D regions115are in direct contact with both of the first channel structures111so that each of the first S/D regions115is configured to function as a common S/D region for the first transistor110A. The first gate structure113can also be in direct contact with both of the first channel structures111and configured to function as a common gate structure. As a result, the first transistor110A and the second transistor120A each include a gate-all-around (GAA) multi-channel transistor. Of course it should be understood that the semiconductor device100A can include any number of stacks140A arranged in the XY plane over the substrate101. The stack140A can include any number of transistors arranged in the Z direction. Each transistor may include any number of channel structures arranged in the Z direction, while respective S/D regions and gate structures can be configured to electrically connect to any number of channel structures.

Note that the channel structures can include different chemical compositions from one another. That is, the channel structures can include different semiconductor materials, different dopants and/or different dopant concentration profiles. For instance, the first channel structures111may include a different chemical composition from the second channel structures121. In one example, the first channel structures111include n-type silicon while the second channel structures121include p-type silicon. In another example, the first channel structures111include p-type silicon while the second channel structures121include n-type silicon. Additionally, the channel structures can have various shapes or geometry. For example, the channel structures can be nanosheets.

In some embodiments, the gate structures (e.g.113and123) each include at least one work function metal (WFM) (e.g.114and124) and at least one gate dielectric (e.g.112and122). As can be appreciated, the WFMs114and124which function as the gate conductors may be different from each other, and the gate dielectrics112and122may also be different from each other, depending on respective channel structures (i.e.111and121), design requirements (e.g. gate threshold voltage), etc. In this example, the WFM114is disposed all around the first channel structures111while the WFM124is disposed all around the second channel structures121. Therefore, the first gate structure113and the second gate structure123can both be configured to function as common gate structures for multiple channel structures. In other examples (not shown), the first gate structures113and/or the second gate structures123may be disposed all around a single channel structure. While the WFM114and124are shown as a single material, they may each be made up of two or more layers of metals having different work functions. Similarly, the gate dielectric112and122may be made up of two or more layers of dielectric materials.

In the example ofFIG.1B, the first S/D regions115and the second S/D regions125are configured to electrically connect to a plurality of (e.g. two) channel structures. In alternative embodiments, the first S/D regions115and/or the second S/D regions125may be in direct contact with only one respective channel structure. Accordingly, the semiconductor device100can include one or more single-channel transistors.

Further, inner spacers (e.g.119and129) can be disposed on ends of the gate structures (e.g.113and123). The inner spacers (e.g.119) are insulating and therefore can separate the gate structures (e.g.113) from respective S/D regions (e.g.115). Particularly in this example, the WFM114is separated from a respective first S/D region115by a respective inner spacer119and the gate dielectric112in a direction (e.g. the X direction) substantially parallel to the working surface of the substrate101. In other words, a portion of the gate dielectric112forms part of a gate spacer that is disposed between the WFM114and the respective first S/D region115in the X direction to isolate the gate from the S/D region.

Additionally, the substrate101can include a semiconductor material. In some embodiments, the substrate101is positioned over an insulator disposed on a substrate (not shown). That is, an epitaxial layer of the semiconductor material is grown on a substrate having a dielectric layer disposed thereon. Thus, the stack140A can be disposed over an SOI (silicon-on-insulator), a GeOI (Germanium-on-insulator), an SGOI (SiGe-on-insulator) or the like. In some embodiments, the substrate101can include completed devices with isolated silicon on top. In some embodiments, the substrate101includes single crystal silicon at a top surface of the substrate101. The single crystal silicon can function as a seed layer for epitaxially growing a semiconductor layer thereon.

In some embodiments, the semiconductor device100can include dielectric materials, e.g. as shown by103,105,112,122,131,133,135,137,119and129. The dielectric materials may also be referred to as isolation structures, isolation layers, diffusion breaks, inner spacers, gate dielectrics, etc. depending on functions thereof. For example, the dielectric material133can be used to separate the first S/D regions115from the second S/D regions125and thus be referred to as an isolation structure133or a diffusion break133. Similarly, the dielectric material137can separate the first gate structure113from the second gate structure123and thus be referred to as vertical isolation structure137. Additionally, some of the dielectric materials may include identical materials or may include different materials. For example, the dielectric material131and the inner spacers119and129may include a same material.

FIG.1Dshows a top view of a semiconductor device100B, in accordance with another embodiment of the present disclosure.FIGS.1E and1Frespectively show vertical cross-sectional views taken along the line cuts CC′ and DD′ inFIG.1D, in accordance with some embodiments of the present disclosure. Since the embodiment of the semiconductor device100B is similar to the embodiment of the semiconductor device100A, descriptions herein will be provided with emphasis placed on difference. Note that similar or identical components are labeled with the same numerals, such as the substrate101inFIGS.1A-1F.

As illustrated, the semiconductor device100B can include a stack140B having gate structures (e.g.117and127), each of which includes at least one WFM (e.g.118and128) and at least one gate dielectric (e.g.116and126). Since first gate structures117and second gate structures127are similar to each other, consider the first gate structure117for example. In this embodiment, the first gate structure117is disposed all around the first channel structures111and can be configured to function as a common gate structure. In an alternative embodiment (not shown), the first gate structure117may be disposed all around a single channel structure. Note that different from the first gate structure113inFIGS.1A-1C, the WFM118herein can be separated from a respective first S/D region115by a respective inner spacer119alone in the X direction. In other words, the WFM118is in direct contact with the inner spacers119in the X direction (without the gate dielectric116disposed in between). That is, in the embodiment ofFIGS.1D-1F, the gate spacer includes only the inner spacer119, and does not include the gate dielectric material. In addition, the WFM118may be in direct contact with the dielectric materials103,105and131(without the gate dielectric116disposed in between) as illustrated inFIG.1F.

Note that the presence or absence of a respective gate dielectric to form part of the gate spacer between the WFM and a respective S/D region can be used to control the distance between the WFM and the respective S/D region, which may further be used to tune some electrical and/or chemical properties. In one example, junction resistance between the WFM and the respective S/D region is determined by the distance and materials in between. In a design limited by space, a relatively short distance (e.g. the semiconductor device100B inFIGS.1D-1F) may be preferred. In another example, a respective inner spacer (with or without the respective gate dielectric) can act as a barrier for preventing unwanted diffusion between the WFM and the respective S/D region.

FIG.2Ashows a top view of a semiconductor device200, in accordance with yet another embodiment of the present disclosure.FIGS.2B and2Crespectively show vertical cross-sectional views taken along the line cuts EE′ and FF′ inFIG.2A, in accordance with some embodiments of the present disclosure. Since the embodiment of the semiconductor device200is similar to the embodiment of the semiconductor device100A, descriptions herein will be provided with emphasis places on difference.

Note that similar or identical components are labeled with similar numerals unless specified otherwise. Specifically, first transistors210can correspond to the first transistor110A. Second transistors220can correspond to the second transistor120A. Channel structures (e.g.211and221) can correspond to the channel structures (e.g.111and121). Gate structures (e.g.213and223) can correspond to the gate structures (e.g.113and123). WFMs (e.g.214and224) can correspond to the WFMs (e.g.114and124). Gate dielectrics (e.g.212and222) can correspond to the gate dielectrics (e.g.112and122). S/D regions (e.g.215and225) can correspond to the S/D regions (e.g.115and125). Inner spacers (e.g.219and229) can correspond to the inner spacers (e.g.119and129). A substrate201can correspond to the substrate101. A dielectric material203can correspond to the dielectric material103.

Herein, a first stack240A includes first channel structures211and first gate structures213while a second stack240B includes second channel structures221and second gate structures223. Consider the first stack240A for example. As illustrated, the first stack240A may include two first transistors210arranged in the Z direction because the first channel structures211include a same chemical composition as each other. For example, the first transistors210can be n-type or p-type. As a result, the first transistors210can share a common gate structure213. That is, the WFM214can be disposed all around the first channel structures211with the gate dielectric212disposed in between. In the embodiment ofFIG.2C, an isolation structure (e.g.137inFIG.1C) is not used to divide (or separate) the gate structure of the upper transistor from the gate structure of the lower transistor. Therefore, the WFM inFIG.2Cserves as a common gate to the upper and lower transistors. Of course it should be understood that the first stack240A can include any number of transistors, each of which may include any number of channel structures, arranged in the Z direction.

The second stack240B is similar to the first stack240A. However, second channel structures221may include a different chemical composition from the first channel structures211. Accordingly, the second gate structures223may include a different chemical composition from the first gate structures213, and second S/D regions225may include a different chemical composition from first S/D regions215. As a result, second transistors220may be different from the first transistors210. In one embodiment, the first transistors210are n-type while the second transistors220are p-type. In another embodiment, the first transistors210are p-type while the second transistors220are n-type. In yet another embodiment, the first transistors210and the second transistors220are both n-type or are both p-type, while the first channel structures211and the second channel structures221may include different dopants and/or different dopant concentration profiles. Further, it should be understood that the semiconductor device200can include any number of stacks (e.g.210and220) arranged in the XY plane over the substrate201.

Further, the semiconductor device200can include contact structures (e.g.261a,261b,262aand262b). Specifically, contact structures261aand262aare configured to electrically connect to the first S/D regions215and the second S/D regions225respectively. Contact structures261band262bare configured to electrically connect to the first gate structures213and the second gate structures223respectively.

In addition, the semiconductor device200can include dielectric materials, e.g. as shown by203,212,222,232,234,219and229. The dielectric materials may also be referred to as isolation structures, isolation layers, diffusion breaks, inner spacers, gate dielectrics, etc. depending on functions thereof. The dielectric materials may or may include different materials. For example, the dielectric material232and the inner spacers219may include a same material. The dielectric material234and the inner spacers229may include a same material.

While not shown, in an alternative embodiment, the semiconductor device200can include gate structures similar to the first gate structures117and the second gate structures127as shown inFIGS.1D-1F. That is, at least one WFM can be separated from a respective S/D region by a respective inner spacer alone in the X direction. In other words, the at least one WFM is in direct contact with the inner spacers in the X direction (with no gate dielectric disposed in between).

FIG.3shows a flow chart of a process300for manufacturing a semiconductor device, such as the semiconductor device100A,100B,200or the like, in accordance with exemplary embodiments of the present disclosure. The process300starts with Step S310where an initial stack of semiconductor layers is formed by epitaxial growth over a substrate. The initial stack of semiconductor layers is surrounded by a sidewall structure. The initial stack of semiconductor layers includes channel structures and sacrificial gate layers stacked alternatingly in a vertical direction substantially perpendicular to a working surface of the substrate. The channel structures include at least one first channel structure and at least one second channel structure positioned above the first channel structure.

In some embodiments, in order to form the initial stack of semiconductor layers, a first layer of a first dielectric material is formed on a surface of a first semiconductor material over the substrate. An initial opening is formed within the first layer. The initial opening uncovers the first semiconductor material. The sidewall structure is formed within the initial opening such that the first semiconductor material is uncovered by an inner opening through the sidewall structure. The sidewall structure includes a second dielectric material. The initial stack of semiconductor layers is formed within the inner opening.

The process300then proceeds to Step S320by removing first portions of the sidewall structure to uncover first sides of the initial stack. For example, removal of the first portions can expose opposite end surfaces of a nanosheet from which the source and drain regions may be epitaxially grown.

At Step S330, source/drain (S/D) regions are formed, for example by epitaxial growth, on uncovered side surfaces of the channel structures from the first sides of the initial stack. In some embodiments, a protective structure is formed to cover respective side surfaces of the second channel structure from the first sides of the initial stack. First S/D regions of the S/D regions are formed on respective side surfaces of the first channel structure. The protective structure is removed. Second S/D regions of the S/D regions are formed on the respective side surfaces of the second channel structure.

At Step S340, second portions of the sidewall structure are removed to uncover second sides of the initial stack. For example, removal of the second portions can expose opposite side surfaces of a nanosheet around which a gate all around (GAA) structure will be formed.

At Step S350, the sacrificial gate layers are replaced with gate structures from the second sides of the initial stack. In some embodiments, the sacrificial gate layers include one or more first sacrificial gate layers in direct contact with the first channel structure and one or more second sacrificial gate layers in direct contact with the second channel structure. The replacing the sacrificial gate layers with the gate structures includes forming a protective structure to cover respective side surfaces of the one or more second sacrificial gate layers from the second sides of the initial stack. The one or more first sacrificial gate layers are replaced with one or more first gate structures. The protective structure is removed. The one or more second sacrificial gate layers are replaced with one or more second gate structures.

Several process flows will be described. According to some aspects of the present disclosure, a core flow starts with a semiconductor substrate, and then a uniform dielectric is deposited on the entire wafer surface. Openings are made to grow epitaxial nanosheets, some of which will also serve as a diffusion break between devices. Other selective dielectrics, spacers, innovations can also be integrated and shown to create a robust self-aligned 3D nanosheet device flow. There are various options and alternative embodiments. In one option (e.g.FIGS.4A-4I), different channel structures (e.g. p-type and n-type epitaxial nanosheets) can be formed in a same stack or on a same vertical plain. A self-aligned scheme can thus be formed, and only a single lithography may be required to finish whole p-n nano-sheet fabrication. In another option (e.g.FIGS.5A-5E), channel structures including a same chemical composition can be formed in a same stack or on a same vertical plain, allowing for another self-aligned scheme which needs only one lithography for each nanosheet device. In yet another option, at least one gate dielectric can be selectively deposited on a channel structure, for example selective high-k dielectric deposition on silicon (including the doped regions).

FIGS.4A,4B,4C,4D,4E,4F,4G,4H and4Ishow vertical cross-sectional views of a semiconductor device400at various intermediate steps of a manufacturing process, such as the process300, in accordance with some embodiments of the present disclosure. In some embodiments,FIGS.4A,4B,4D and4Frespectively show vertical cross-sectional views (e.g. in the XZ plane) taken along the line cuts GG′, HH′, II′ and Jr inFIGS.4A′,4B′,4D′ and4F′ whileFIGS.4F″ and4G respectively show vertical cross-sectional views (e.g. in the YZ plane) taken along the line cuts KK′ and LL′ inFIGS.4F′ and4G′. In some embodiments, the semiconductor device400can eventually become the semiconductor device100A,100B or the like.

As shown inFIGS.4A and4A′, the semiconductor device400includes a substrate401and an initial stack440′ of semiconductor layers (e.g. as shown by411,421,442a,442b,444aand444b) formed thereon. The initial stack440′ of semiconductor layers is surrounded by a sidewall structure405, which can be further surrounded by a first dielectric material403. The sidewall structure405can, for example, include a second dielectric material.

Specifically, the initial stack440′ of semiconductor layers can include channel structures (e.g. as shown by411and421) and sacrificial gate layers444(e.g. as shown by444aand444b) stacked alternatingly in a vertical direction (e.g. the Z direction) substantially perpendicular to a working surface of the substrate401. In a non-limiting example, the channel structures can include one or more (e.g. two) first channel structures411and one or more (e.g. two) second channel structures421. Accordingly, the sacrificial gate layers444can include first sacrificial gate layers444a, which are in direct contact with the first channel structures411, and second sacrificial gate layers444bwhich are in direct contact with the second channel structures421. The initial stack440′ of semiconductor layers can further include sacrificial isolation layers442(e.g. as shown by442aand442b).

Note that the channel structures, the sacrificial gate layers444and the sacrificial isolation layers442can be configured to be etch selective to each other. In a non-limiting example, the channel structures include silicon (e.g. n-type Si, p-type Si or intrinsic Si). The sacrificial gate layers444include silicon germanium (noted as SiGe1) while the sacrificial isolation layers442include silicon germanium (noted as SiGe2). SiGe1 and SiGe2 can have different ratios of Si to Ge so as to have etch selectivity. For instance, SiGe1 can include 75 mol % of Si and 25 mol % of Ge, while SiGe2 can include 10 mol % of Si and 90 mol % of Ge.

In some embodiments, the first channel structures411can correspond to the first channel structures111. The second channel structures421can correspond to the second channel structures121. The first sacrificial gate layers444acan be used to form a first gate structure, which corresponds to the first gate structure113or117, as well as form inner spacers, which correspond to the inner spacers119. The second sacrificial gate layers444bcan be used to form a second gate structure, which corresponds to the second gate structure123or127, as well as form inner spacers, which correspond to the inner spacers129. The sacrificial isolation layers442can be replaced with dielectric materials, which correspond to the dielectric materials131,133and/or137, to form isolation, for example between transistors (e.g.442b) or between a transistor and the substrate401(e.g.442a). Additionally, the substrate401can correspond to the substrate101. The first dielectric material403can correspond to the dielectric material103.

As a result, the initial stack440′ can eventually become the stack140A,140B or the like. Accordingly, it should be understood that any number of the initial stacks440′ can be formed over the substrate401. Each initial stack440′ of semiconductor layers can include any number of first channel structures411and second channel structures421. Each initial stack440′ of semiconductor layers can include any number of sacrificial isolation layers442(for forming future isolation between transistors).

In some embodiments, in order to form the semiconductor device400shown inFIGS.4A and4A′, firstly, a first layer of the first dielectric material403can be formed on the substrate401which includes a surface of a first semiconductor material. Secondly, an initial opening (not shown) can be formed within the first layer (for example by patterning with a trench rectangular mask), and the initial opening uncovers the first semiconductor material, or rather the substrate401. Thirdly, the sidewall structure405of the second dielectric material is formed within the initial opening such that the first semiconductor material is uncovered by an inner opening (not shown) through the sidewall structure405. For example, the second dielectric material can be deposited by ALD to fill the opening before directionally etched (for example similar to a spacer open etch) to form the inner opening within the second dielectric material while a remaining portion of the second dielectric material forms the sidewall structure405. Fourthly, the initial stack440′ of semiconductor layers can be formed within the inner opening, for example by epitaxial growth over the surface of the first semiconductor material. Further, a capping layer446may optionally be formed over the initial stack440′.

“Epitaxial growth”, “epitaxial deposition”, “epitaxially grown”, “epitaxially formed” or “epitaxy” as used herein generally refers to a type of crystal growth or material deposition in which a crystalline layer is formed over a seed layer that is crystalline. Crystalline characteristics (e.g. crystal orientation) of the crystalline layer are related to or dictated by crystalline characteristics of the seed layer. Particularly, a semiconductor material can be epitaxially grown on a surface of another semiconductor layer that is crystalline. In some embodiments, epitaxial growth can be selective such that a semiconductor material may only be epitaxially grown on another semiconductor surface and generally do not deposit on exposed surfaces of non-semiconductor materials, such as silicon oxide, silicon nitride, and the like. Epitaxial growth can be accomplished by molecular beam epitaxy, vapor-phase epitaxy, liquid-phase epitaxy, or the like. Si, SiGe, Ge and other semiconductor materials can be doped during epitaxial growth (in situ) by addition of dopants. For example in vapor-phase epitaxy, a dopant vapor can be added to the gas source.

InFIGS.4B and4B′, first portions405aof the sidewall structure405are removed to uncover one or more first sides (e.g. the −X and +X sides) of the initial stack440′. A mask is used to remove only the first portions405a, while preserving the second portions405b. Then, indentations448are formed by removing end portions of the sacrificial gate layers444from the first sides of the initial stack440′. In the embodiment described, the sacrificial isolation layers442are also removed from the first sides of the initial stack440′. Specifically, different etch rates of the sacrificial gate layers444and the sacrificial isolation layers442permits the same etch process step to form indentations448while completely removing the sacrificial isolation layers442.

InFIG.4C, a first filler material431(or a third dielectric material431) is deposited and optionally planarized, for example by chemical mechanical polishing (CMP), to cover the first sides of the initial stack440′. In some embodiments, the third dielectric material431can eventually become the dielectric material131.

InFIGS.4D and4D′, a first protective structure451is formed to cover side surfaces of the second channel structures421from the first sides of the initial stack440′. Specifically, the first filler material431can be etched back to uncover the side surfaces of the second channel structures421while still leaving side surfaces of the first channel structures411covered. Subsequently, a second filler material (e.g. as partially shown by451), which is etch selective to the first filler material431, can be formed (for example by atomic layer deposition) over the first filler material431to cover the side surfaces of the second channel structures421(and optionally planarized). Next, the second filler material can be directionally etched to partially uncover the first filler material431, for example by forming an opening452, such that a remaining portion of the second filler material forms the first protective structure451.

Note that inner spacers429, which can correspond to the inner spacers129, are formed as a result of etching back the first filler material431. Further, the first protective structure451has a shape of a hollow rectangle in the top view in theFIG.4D′ example. It should be understood that the first protective structure451can have any suitable shape as long as the first protective structure451includes a portion451athat covers the first sides of the initial stack440′.

InFIG.4E, the first filler material431is further etched back by selectively etching through the opening452, which may for example include a first directional etching process and a second isotropic etching process. Consequently, inner spacers419, which can correspond to the inner spacers119, are formed. Moreover, the side surfaces of the first channel structures411are uncovered so that first S/D regions415(e.g. p-type silicon) can be formed thereon, for example by epitaxial growth (e.g. selectively from the side surfaces of the first channel structures411). The first S/D regions415can correspond to the first S/D regions115. Note that a remaining portion of the first filler material431can function to maintain isolation of the first S/D regions415from the substrate401.

InFIGS.4F,4F′ and4F″, the first protective structure451is removed to uncover the side surfaces of the second channel structures421from the first sides of the initial stack440′ so that second S/D regions425(e.g. n-type silicon) can be formed thereon, for example by epitaxial growth (e.g. selectively from the side surfaces of the second channel structures421). Dielectric materials433and435can also be deposited (and optionally planarized). The second S/D regions425can correspond to the second S/D regions125. The dielectric materials433and435can correspond to the dielectric materials133and135respectively. Note that the vertical cross-sectional view (e.g. in the YZ plane) inFIG.4F″ is perpendicular to the vertical cross-sectional view (e.g. in the XZ plane) inFIG.4F.

InFIGS.4G and4G′, second portions405bof the sidewall structure405are etched back (for example to a separation point at the first filler material431) to uncover side surfaces of the second channel structures421from one or more second sides (e.g. the −Y and +Y sides) of the initial stack440′. A second protective structure453can then be formed to cover the side surfaces of the second channel structures421and the second sacrificial gate layers444b, while leaving the second portions405bof the sidewall structure405at least partially uncovered.

InFIG.4H, the second portions405bof the sidewall structure405are further etched back to uncover side surfaces of the first sacrificial gate layers444afrom the second sides of the initial stack440′ so that the first sacrificial gate layers444acan be replaced with gate structures. In one embodiment, the first sacrificial gate layers444aare removed (for example by selective etching) after the second portions405bof the sidewall structure405are further etched back. Then, the second protective structure453is optionally removed. Next, at least one gate dielectric412can be formed on uncovered surfaces, e.g. uncovered surfaces of the first channel structures411, the second channel structures421, the second sacrificial gate layers444b, the first dielectric material403, etc. The at least one gate dielectric412can be formed by atomic layer deposition (ALD) for example. Subsequently, at least one WFM414is formed on the at least one gate dielectric412and optionally planarized by CMP. In another embodiment, the second protective structure453may be removed later, for example in a same etching process that etches back the gate dielectric412and the WFM414(e.g. as shown inFIG.4I). Note that the at least one WFM414can eventually become the (at least one) WFM114. The at least one gate dielectric412can eventually become the (at least one) gate dielectric112.

InFIG.4I, the gate dielectric412and the WFM414is etched back to uncover the side surfaces of the second channel structures421so that the second sacrificial gate layers444bare uncovered and can be replaced with one or more second gate structures423(e.g. as shown by at least one gate dielectric422and at least one WFM424). As a result, one or more first gate structures413are also formed (e.g. as shown by the at least one gate dielectric412and the at least one WFM414). The at least one gate dielectric422can be formed by ALD for example while the at least one WFM424can be deposited and optionally planarized by CMP. An isolation structure437can be formed to separate the WFM414from the gate dielectric422and the WFM424.

Herein, the one or more first gate structures413can correspond to the first gate structure113. The one or more second gate structures423can correspond to the second gate structure123. The at least one WFM424can correspond to the (at least one) WFM124. The at least one gate dielectric422can correspond to the at least one gate dielectric122. The isolation structure437can correspond to the isolation structure137. Moreover, the semiconductor device400inFIG.4Ican correspond to the semiconductor device100A inFIGS.1A-1C. That is, the semiconductor device ofFIG.4Iprovides a stack of two transistors having gates vertically isolated from one another, with each transistor having a gate spacer that includes inner spacer and gate dielectric material.

Referring back toFIG.4H, the gate dielectric412can be formed non-selectively on uncovered surfaces, e.g. the uncovered surfaces of the first channel structures411, the second channel structures421, the second sacrificial gate layers444b, the first dielectric material403, etc. In an alternative embodiment, the gate dielectric412can be selectively formed on the uncovered surfaces of the first channel structures411(and optionally the second channel structures421as well) by selective deposition. Similarly, in an alternative embodiment ofFIG.4I, the gate dielectric422can be selectively formed on the uncovered surfaces of the second channel structures421. As a result, the semiconductor device400can become the semiconductor device100B inFIGS.1D-1F. That is, with selective deposition of the gate dielectric, the gate spacer includes only the inner spacer material.

FIGS.5A,5B,5C,5D and5Eshow vertical cross-sectional views of a semiconductor device500at various intermediate steps of a manufacturing process, such as the process300, in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor device500can eventually become the semiconductor device200or the like.

As shown inFIG.5A, the semiconductor device500includes a substrate501and initial stacks of semiconductor layers formed thereon, such as a first initial stack540A′ of semiconductor layers (e.g. as shown by511and544) and a second initial stack540B′ of semiconductor layers (e.g. as shown by521and544). The first initial stack540A′ of semiconductor layers and the second initial stack540B′ of semiconductor layers are surrounded by sidewall structures505and507respectively. The sidewall structures505and507can be further surrounded by a first dielectric material503. The sidewall structures505and507can, for example, both include a second dielectric material (or include different dielectric materials from each other).

Specifically, the first initial stack540A′ of semiconductor layers can include first channel structures511and sacrificial gate layers544stacked alternatingly in a vertical direction (e.g. the Z direction) substantially perpendicular to a working surface of the substrate501. The first channel structures511and the sacrificial gate layers544are configured to be etch selective to each other. Similarly, the second initial stack540B′ of semiconductor layers can include second channel structures521and sacrificial gate layers544stacked alternatingly in the Z direction. The second channel structures521and the sacrificial gate layers544are also configured to be etch selective to each other. For example, the first channel structures511and the second channel structures521can include silicon while the sacrificial gate layers544include silicon germanium (noted as SiGe3).

In some embodiments, the first channel structures511can correspond to the first channel structures211. The second channel structures521can correspond to the second channel structures221. The sacrificial gate layers544can be used to form gate structures, which correspond to the first gate structures213and/or the second gate structures223, as well as form inner spacers, which correspond to the inner spacers219and/or229. As a result, the first initial stack540A′ can eventually become the first stack510. The second initial stack540B′ can eventually become the second stack520. Accordingly, it should be understood that the semiconductor device500can include any number of first initial stacks540A′, second initial stacks540B′ or the like over the substrate501. Each initial stack of semiconductor layers can include any number of channel structures. Additionally, the substrate501can correspond to the substrate201. The first dielectric material503can correspond to the dielectric material203. The sidewall structures505and507can both correspond to the sidewall structure405.

In some embodiments, the semiconductor device500inFIG.5Acan be formed in a process similar to what has been described for the semiconductor device400inFIGS.4A and4A′, for example including forming a first layer of the first dielectric material503, forming initial openings, forming the sidewall structures505and507and forming the initial stacks. In one example, the sidewall structures505and507are formed in a same deposition and etching process so that the sidewall structures505and507include a same material. In another example, the sidewall structures505and507are formed in separate processes and may therefore include different materials. In one embodiment, the first initial stack540A′ and the second initial stack540B′ are formed simultaneously or concurrently. Accordingly, each of the first channel structures511includes a same chemical composition and a same thickness as a respective second channel structure521. In another embodiment, the first initial stack540A′ and the second initial stack540B′ are formed in separate processes. Consequently, the first channel structures511and the second channel structures521may include different chemical compositions and/or different thicknesses.

InFIG.5B, inner spacers529, which can correspond to the inner spacers229, are formed on ends of the sacrificial gate layers544in the second initial stack540B′. Moreover, the second channel structures521are uncovered from the −X and +X sides while a filler material534(or a third dielectric material534) can function to isolate future structures (e.g. S/D regions) from the substrate501.

Firstly, similar toFIGS.4B and4B′, first portions507aof the sidewall structure507can be directionally etched to uncover one or more first sides (e.g. the −X and +X sides) of the second initial stack540B′ before end portions of the sacrificial gate layers544in the second initial stack540B′ are removed to form indentations. Secondly, similar toFIG.4C, the filler material534can be deposited (and optionally planarized) to cover the first sides of the second initial stack540B′. The filler material534also fills space of the (empty) indentations. Thirdly, the filler material534can be directionally etched back. The filler material534which remains in the indentations forms the inner spacers529. Accordingly, the filler material534and the inner spacers529can include a same dielectric material. Note the filler material534can correspond to the dielectric material234.

InFIG.5C, second S/D regions525(e.g. n-type silicon), which can correspond to the second S/D regions225, are formed on ends of the second channel structures521from the first sides of the second initial stack540B′, for example by epitaxial growth (e.g. selectively from the ends of the second channel structures521). In this example, the second S/D regions525are each in direct contact with two channel structures. In another example, the second S/D regions525can each be in direct contact with any number of channel structures. A thickness of a sacrificial gate layer544acan be configured to separate the second S/D regions525from each other in the Z directions. Similarly, a thickness of another sacrificial gate layer (e.g.544b) can also be configured to separate (or divide) the second S/D regions525in the Z directions.

InFIG.5D, first S/D regions515(e.g. p-type silicon) and inner spacers519are formed, for example in a process similar toFIGS.5B and5C. The first S/D regions515can correspond to the first S/D regions215. The inner spacers519can correspond to the inner spacers219. A dielectric material532can correspond to the dielectric material232.

InFIG.5E, the sacrificial gate layers544are replaced with first gate structures513and second gate structures523. The first gate structures513can correspond to the first gate structures213while the second gate structures523can correspond to the second gate structures223. Specifically, WFMs514and524can correspond to the WFMs214and224respectively. Gate dielectrics512and522can correspond to the gate dielectrics212and222respectively.

In one embodiment, the first gate structures513and the second gate structures523are formed in a same etching and deposition process. That is, second portions (not shown) of the sidewall structures505and second portions (not shown) of the sidewall structure507are removed to uncover one or more second sides (e.g. the −Y and +Y sides) of the first initial stack540A′ and uncover one or more second sides (e.g. the −Y and +Y sides) of the second initial stack540B′ respectively. The sacrificial gate layers544can then be removed from the second sides of the first initial stack540A′ and from the second sides of the second initial stack540B′. Subsequently, the gate dielectrics512and522, which can include one or more same dielectric materials, are formed on uncovered surfaces, particularly on uncovered surfaces of the first channel structures511and the second channel structures521respectively. For example, the gate dielectrics512and522can be formed by ALD. Next, the WFMs514and524, which can include one or more same metal materials, are formed on the gate dielectrics512and522respectively and optionally planarized by CMP. In another embodiment, the first gate structures513and the second gate structures523are formed in separate processes. Accordingly, the gate dielectrics512and522may include different materials. The WFMs514and524may include different materials.

In yet another embodiment (not shown), the gate dielectrics512and522can be selectively deposited on uncovered surfaces of the first channel structures511and the second channel structures521respectively. As a result, the gate structures can correspond to the first gate structures117and the second gate structures127. That is, at least one WFM can be separated from a respective S/D region by a respective inner spacer alone in the X direction. In other words, the at least one WFM is in direct contact with the inner spacers in the X direction (with no gate dielectric disposed in between).

Referring back toFIG.5E, in some embodiments, a dielectric material, such as the first dielectric material503can be deposited, patterned (for example with a connector mask) and etched to open desired contact surfaces (e.g. the first S/D regions515, the second S/D regions525and the WFMs514and524). Then, contact structures, which correspond to the contact structures261a,261b,262aand262b, can be formed, for example by depositing a metal and planarized. The semiconductor device500can thus become the semiconductor device200.

The substrate can be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and/or a silicon-on-insulator (SOI) substrate. The substrate may include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate may be a bulk wafer or an epitaxial layer.