Semiconductor packages with shortened talking path

Semiconductor packages are disclosed. A semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. A first portion of the first seal ring is disposed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring.

BACKGROUND

In recent years, the semiconductor industry has experienced rapid growth due to continuous improvement in integration density of various electronic components, e.g., transistors, diodes, resistors, capacitors, etc. For the most part, this improvement in integration density has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area.

These smaller electronic components also require smaller packages that occupy less area than previous packages. Examples of the type of packages for semiconductors include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chips (FC), three-dimensional integrated circuits (3DICs), wafer level packages (WLPs), and package on package (PoP) devices. Some 3DICs are prepared by placing chips over chips on a semiconductor wafer level. The 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked chips. However, there are many challenges related to 3DICs.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below for the purposes of conveying the present disclosure in a simplified manner. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the same reference numerals and/or letters may be used to refer to the same or similar parts in the various examples the present disclosure. The repeated use of the reference numerals is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

FIG. 1Ais a top view of a semiconductor package in accordance with some embodiments, andFIG. 1Bis a cross-sectional view of a semiconductor package along the line I-I ofFIG. 1Ain accordance with some embodiments. For simplicity and clarity of illustration, only few elements such as first and second dies, an integrated circuit, seal rings, bonding structures and conductive features are shown in the simplified top view ofFIG. 1A, and these elements are not necessarily in the same plane.

Referring toFIGS. 1A and 1B, a first die100A and a second die100B are mounted onto the integrated circuit200. The first and second dies100A,100B may be the same type of dies or different types of dies. The first and second dies100A,100B may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory chip, for example. In some embodiments, the first and second dies100A,100B may be an active component or a passive component. In some embodiments, the first and second dies100A,100B include a semiconductor substrate104, an interconnect structure110and a plurality of bonding structures120,120A,120B.

In some embodiments, the first and second dies100A,100B may be rectangular-shaped, and has four sides102a,102b,102c,102d, for example. The sides102a,102b,102c,102dare connected to one another. The sides102a,102care longer sides, and the sides102b,102dare shorter sides. The side102ais opposite to and parallel to the side102c, and the side102bis opposite to and parallel to the side102d. In some embodiments, a length of the sides102a,102cis 0.5 mm to 55 mm, for example. A length of the sides102b,102dis 0.5 mm to 55 mm, for example. In some embodiments, the side102aof the first die100A faces to the side102aof the second die100B. In some embodiments, the shortest distance DABbetween the die100A and the die100B is formed between the side102aof the first die100A and the side102aof the second die100B, which is also referred to as a die-to-die spacing. In some embodiments, the distance DABmay be in a range of 10 μm to 100 μm, for example.

In some embodiments, the semiconductor substrate104includes an elementary semiconductor such as silicon or germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide. In some embodiments, the semiconductor substrate104is a semiconductor-on-insulator (SOI) substrate. In some alternative embodiments, the semiconductor substrate104may take the form of a planar substrate, a substrate with multiple fins, nanowires, or other forms known to people having ordinary skill in the art. Depending on the requirements of design, the semiconductor substrate104may be a P-type substrate or an N-type substrate and may have doped regions therein. The doped regions may be configured for an N-type device or a P-type device.

In some embodiments, the semiconductor substrate104includes isolation structures defining at least one active area, and a device layer is disposed on/in the active area. The device layer includes a variety of devices. In some embodiments, the devices include active components, passive components, or a combination thereof. In some embodiments, the devices may include integrated circuits devices. The devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. In some embodiments, the device layer includes a gate structure, source/drain regions, spacers, and the like.

In some embodiments, a through substrate via106may be disposed in the semiconductor substrate104. In some embodiments, the through substrate via106is called “a through silicon via” when the semiconductor substrate104is a silicon-containing substrate. The through substrate via106is electrically connected to the interconnect structure110and the to-be-formed redistribution layer structure304. In some embodiments, the through substrate via106includes a conductive via. The conductive via includes copper, a copper alloy, aluminum, an aluminum alloy or a combination thereof. In some embodiments, the through substrate via106further includes a diffusion barrier layer between the conductive via and the semiconductor substrate104. The diffusion barrier layer includes Ta, TaN, Ti, TiN, CoW or a combination thereof. The through substrate via106penetrates the semiconductor substrate104, in other words, the through substrate via106is extended between two opposite surfaces of the semiconductor substrate104. In some embodiments, a dielectric layer108may be further formed over a surface (i.e., the back surface) of the semiconductor substrate104. The through substrate via106is extended into the dielectric layer108and exposed through the dielectric layer108. In some embodiments, a surface of the through substrate via106may be substantially coplanar with a surface of the dielectric layer108, for example.

The interconnect structure110is disposed over a surface (e.g., front surface) of the semiconductor substrate104. Specifically, the interconnect structure110is disposed over and electrically connected to the device layer. In some embodiments, the interconnect structure110includes at least one insulating layer112and a plurality of conductive features114,116. The conductive features114,116are disposed in the insulating layer112and electrically connected with each other. In some embodiments, the insulating layer112includes an inter-layer dielectric (ILD) layer on the semiconductor substrate104, and at least one inter-metal dielectric (IMD) layer over the inter-layer dielectric layer. In some embodiments, the insulating layer112includes silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material or a combination thereof. The insulating layer112may be a single layer or a multiple-layer structure. In some embodiments, the conductive features114,116include plugs and metal lines. The plugs may include contacts formed in the inter-layer dielectric layer, and vias formed in the inter-metal dielectric layer. The contacts are formed between and in contact with a metal line and the device layer. The vias are formed between and in contact with two metal lines. The conductive features114,116may include tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy or a combination thereof. In some embodiments, a barrier layer may be disposed between the conductive features114,116and the insulating layer112to prevent the material of the conductive features114,116from migrating to the underlying device layer. The barrier layer includes Ta, TaN, Ti, TiN, CoW or a combination thereof, for example. In some embodiments, the interconnect structure110is formed by a dual damascene process. In alternative embodiments, the interconnect structure110is formed by multiple single damascene processes. In yet alternative embodiments, the interconnect structure110is formed by an electroplating process. It is noted that although the interconnector structure110is shown asFIG. 1B, however, the disclosure is not limited thereto, in other words, the interconnector structure110may have other suitable configuration.

The bonding structures120,120A,120B are disposed over the surface (e.g., front surface) of the interconnect structure110and disposed in at least one bonding dielectric layer122. In some embodiments, the bonding structures120A,120B are disposed along the side102a, and the bonding structures120may be arranged along the sides102b,102c,102d. A distance between the adjacent two bonding structures120,120A,120B may be the same or different. In some embodiments, the bonding structure120,120A,120B includes a bonding conductive feature such as a bonding pad124aand/or a bonding via124b. The bonding via124bis electrically connected to the interconnect structure110, and the bonding pad124ais electrically connected to the bonding via124b. In some embodiments, the bonding dielectric layer122includes silicon oxide, silicon nitride, a polymer or a combination thereof. The bonding conductive feature may include tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy or a combination thereof. In some embodiments, a barrier layer may be disposed between the bonding conductive feature and the bonding dielectric layer122. The barrier layer includes Ta, TaN, Ti, TiN, CoW or a combination thereof, for example. In some embodiments, the bonding structure120,120A,120B is formed by a dual damascene process. In some alternative embodiments, the bonding structure120,120A,120B is formed by multiple single damascene processes. In some alternative embodiments, the bonding structure120,120A,120B is formed by an electroplating process.

In some embodiments, the conductive feature116is physically and electrically connected to the bonding structure120A,120B. Specifically, the conductive feature116is in contact with the bonding via124bof the bonding structure120A,120B, and the bonding via124bis disposed between the bonding pad124aand the conductive feature116. In some embodiments, the bonding structure120A,120B may be extended in a first direction (i.e., a stack direction of the first and second dies100A,100B onto the integrated circuit200), and the conductive feature116may be extended in a second direction (i.e., a arranging direction of the first die100A and the second die100A) substantially perpendicular to the first direction. In some embodiments, the conductive feature116further electrically connects the bonding structures120,120A or the bonding structures120,120B. In some embodiments, the conductive feature116are included in the interconnect structure110, however, the invention is not limited thereto. For example, in some alternative embodiments, the conductive feature116may be other conductive feature disposed in the semiconductor substrate104, the bonding dielectric layer122or other suitable sites and in direct contact with the bonding structure120A,120B.

In some embodiments, the first and second dies100A,100B further include seal rings130A,130B. The seal ring130A,130B is disposed over the surface (e.g., front surface) of the semiconductor substrate104. Specifically, the seal ring130A,130B is disposed over and electrically insulated from the device layer, and located aside the interconnect structure110. In some embodiments, the seal ring130A,130B is continuously disposed at the sides102a,102b,102c,102d, for example. As shown inFIG. 1A, the seal ring130A,130B has a ring shape or any suitable shape from a top view. In some embodiments, the bonding structures120A,120B are disposed within and surrounded by the seal ring130A,130B.

In some embodiments, the seal ring130A of the first die100A has a portion132A and a portion134A, and the portion132A and the portion134A are physically connected. Similarly, the seal ring130B of the second die100B has a portion132B and a portion134B, and the portion132B and the portion134B are physically connected. In some embodiments, the portion132A,132B is disposed at the side102a, and the portion134A,134B is disposed at the sides102b,102c,102d. In some embodiments, the portion132A,132B may be line-shaped and elongated along the side102a. The portion134A,134B may be U-shaped and continuously disposed along the sides102b,102c,102d. The first portion132A of the first die100A is disposed adjacent to the side102a.

In some embodiments, the shortest distance D1A, D1Bbetween the bonding structure120A,120B and the portion132A,132B is the distance between the outermost edge of the bonding pad124aand the innermost edge of the portion132A,132B. In some embodiments, the distance D1A, D1Bmay be in a range of 20 μm to 100 μm, for example. In some embodiments, the shortest distance D2A, D2Bbetween the portion132A,132B and the side102amay be in a range of 5 μm to 100 μm, for example. In some embodiments, the distance D2A, D2Bis also the width of the remained silicon after silicon singulation. In some embodiments, the shortest distance (not shown) between the seal ring130A,130B and each side102a,102b,102c,102dmay be substantially the same, for example.

In some embodiments, the portion132A,132B has a uniform width W1A, W1B, and the portion134A,134B has a uniform width W2A, W2B. The width W1A, W1Bof the portion132A,132B is smaller than the width W2A, W2Bof the portion134A,134B. That is, a portion of the seal ring130A,130B (i.e., the portion132A,132B) is narrowed at the side102a. In some embodiments, the width W1Ais smaller than the width W2Aby at least 5 μm, and the width W1Bis smaller than the width W2Bby at least 5 μm, for example. In some embodiments, the width W1A, W1Bmay be in a range of 5 μm to 45 μm, and the width W2A, W2Bmay be in a range of 10 μm to 50 μm. In some embodiments, the portion132A,132B and the portion134A,134B may be formed simultaneously.

Herein, when elements are described as “at substantially the same level”, the elements are formed at substantially the same height in the same layer, or having the same positions embedded by the same layer. In some embodiments, the elements at substantially the same level are formed from the same material(s) with the same process step(s). In some embodiments, the surfaces of the elements at substantially the same level are substantially coplanar. For example, as shown inFIG. 1B, the seal ring130A,130B is at substantially the same level with the interconnect structure110. In detail, the seal ring130A,130B may include a plurality of conductive features136such as conductive lines and plugs between the conductive lines. The conductive features136of the seal ring130A,130B are at substantially the same level with the conductive features114,116of the interconnect structure110.

In some embodiments, a region RA, RBis defined as being between the side102aand the outermost edge of the interconnect structure110(i.e., the outermost edge of the conductive features114,116). When an element (such as the portion132A,132B of the seal ring130A,130B) is disposed in the region RA, RB, a space for the element is required, and a distance between the conductive feature116and the side102ais increased. Furthermore, since the bonding structure120A,120B is physically connected to and disposed over the conductive feature116, a distance between the bonding structure120A,120B (i.e., the outermost edge of the bonding pad124a) and the side102ais also increased.

Still referring toFIGS. 1A and 1B, the integrated circuit200may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory chip, for example. The integrated circuit200and the first and second dies100A,100B may be the same type of dies or different types of dies. In some embodiments, the integrated circuit200may be an active component or a passive component. In some embodiments, the integrated circuit200is larger than a total area of the first and second dies100A,100B. In some embodiments, the size of the integrated circuit200is larger than the size of the first and second dies100A,100B. Herein, the term “size” is referred to the length, width and/or area.

In some embodiments, the integrated circuit200includes a semiconductor substrate204, an interconnect structure210, a plurality of bonding structures220and a plurality of conductive features216.

The interconnect structure210is similar to the interconnect structure110. Similarly, the interconnect structure210is disposed over a surface (e.g., front surface) of the semiconductor substrate204. Specifically, the interconnect structure210is disposed over and electrically connected to the device layer. In some embodiments, the interconnect structure210includes at least one insulating layer212and a plurality of conductive features214,216. The conductive features214,216are disposed in the insulating layer212and electrically connected with each other. A portion of the conductive features, such as the outermost conductive features216, are exposed by the insulating layer212.

The bonding structure220is similar to the bonding structure120A,120B. Similarly, the bonding structure220is disposed over the surface (e.g., front surface) of the interconnect structure210. In some embodiments, the bonding structure220is disposed in at least one bonding dielectric layer222and includes a bonding conductive feature such as a bonding pad224aand/or a bonding via224b. The bonding via224bis electrically connected to the interconnect structure210, and the bonding pad224ais electrically connected to the bonding via224b.

In some embodiments, the first and second dies100A,100B and the integrated circuit200are face-to-face bonded together with the bonding structures120A,120B and the bonding structures220. In some embodiments, before the first and second dies100A,100B are bonded to the integrated circuit200, the bonding structures120A,120B and the bonding structures220are aligned, such that the bonding pads124aare bonded to the bonding pads224aand the bonding dielectric layer122is bonded to the bonding dielectric layer222. In some embodiments, the alignment of the bonding structure120A,120B and the bonding structure220may be achieved by using an optical sensing method. After the alignment is achieved, the bonding structure120A,120B and the bonding structure220are bonded together by a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding.

After the first and second dies100A,100B are bonded to the integrated circuit200, the first and second dies100A,100B are electrically connected to the integrated circuit200, respectively. In addition, the conductive feature216electrically connects the first die100A and the second die100B directly. Specifically, the conductive feature216electrically and physically connects the bonding structure220bonded to the bonding structure120A of the first die100A and the bonding structure220bonded to the bonding structure120B of the second die100B. In some embodiments, the terminals of the conductive feature216are physically connected to the bonding vias224bbonded to the bonding structures120A,120B of the first and second dies100A,100B. The bonding via224bis disposed between the bonding pads224aand the conductive feature216. The conductive feature216is elongated between the bonding structure120A of the first die100A and the bonding structure120B of the second die100B. In some embodiments, the bonding structure220may be extended in a first direction (i.e., a stack direction of the first and second dies100A,100B onto the integrated circuit200), and the conductive feature216may be extended in a second direction (i.e., a arranging direction of the first die100A and the second die100B) substantially perpendicular to the first direction. In some embodiments, the conductive feature216are the outermost conductive feature of the interconnect structure210, however, the invention is not limited thereto. For example, in some alternative embodiments, the conductive feature216may be other conductive feature disposed in the semiconductor substrate204, the bonding dielectric layer222or other suitable sites. In addition, the conductive feature216may be also referred to as a connecting feature or a bridge structure.

In some embodiments, the portion132A,132B of the seal ring130A,130B may be extended in a first direction parallel to the side102a, and the conductive feature216may be extended in a second direction substantially perpendicular to the side102a, for example. Accordingly, as shown inFIG. 1A, from a top view, the conductive feature216may be partially overlapped with the portion132A,132B of the seal ring130A,130B, to form an overlapped region OPRA, OPRB. In some embodiments, the conductive features216are substantially parallel to one another, for example. In some embodiments, the conductive features216may be parallel to the sides102a,102c(such as short sides) of the first and second dies100A,100B, for example.

In some embodiments, the conductive feature216may be line-shaped, for example. A pitch of the conductive feature216may be in a range of 0.04 μm to 5 μm, for example. In some embodiments, the conductive feature216may include tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy or a combination thereof. In some embodiments, a barrier layer may be disposed between the conductive feature216and the insulating layer212. The barrier layer includes Ta, TaN, Ti, TiN, CoW or a combination thereof, for example. In some embodiments, the conductive feature216is formed by a dual damascene process. In some alternative embodiments, the conductive feature216is formed by multiple single damascene processes. In some alternative embodiments, the conductive feature216is formed by an electroplating process.

In some embodiments, the conductive feature216electrically connects the bonding structures120A,120B which are nearest to each other. Therefore, the conductive feature216provides the shortest conductive path between the corresponding bonding structures120A,120B. Accordingly, the first die100A and the second die100B may be talked to each other efficiently, that is, the conductive feature216provides a die-to-die talking path TP. In some embodiments, the conductive feature216is disposed across the portion132A of the seal ring130A, the spacing between the first die100A and the second die100B, and the portion132B of the seal ring130B. Therefore, a length of the die-to-die talking path TP is substantially equal to a total of the distance D1A between the portion132A and the bonding structure120A of the first die100A, the width W1A of the portion132A, the distance D2A between the portion132A and the side102aof the first die100A, the distance DAB between the sides102aof the first and second dies100A,100B, the distance D1B between the portion132B and the side102aof the second die100B, the width W1B of the portion132B and the distance D2B between the portion132B and the bonding structure120B of the second die100B. In some embodiments, the distance D1A, D2A may depend on the process window of the photolithography or the requirement of insulation between the conductive elements. The distance DAB may depend on the gap-filling capacity of the encapsulant. In some embodiments, by narrowing the portion132A,132B of the seal ring130A,130B, the width W1A, W1B is reduced. Accordingly, the die-to-die talking path TP may be shortened. In some embodiments, the length of the die-to-die talking path TP may be equal to or less than 70 μm, for example. Furthermore, since the width W1A, W1B of the portion132A,132B of the seal ring130A,130B at the side102ais smaller than the width W2A, W2B of the portion134A,134B of the seal ring130A,130E at other side102b,102c,102d, the distance between the bonding structure120A and the side102ais smaller than a distance between the bonding structure120and other side102b,102c,102d. For example, the distance (i.e., a total of the distance D1A, the width W1A and the distance D2A) between the bonding structure120A and the side102ais smaller than a distance D3between the bonding structure120and the side102a.

In some embodiments, since the outermost edge of the bonding pad124aof the bonding structure120A,120B is disposed inside the outermost edge of the conductive feature116, an additional distance is formed between the outermost edge of the bonding pad124aand the outermost edge of the conductive feature116. Therefore, the shortest distance D1A, D1Bbetween the bonding structure120A,120B and the portion132A,132B is larger than the shortest distance D4between the conductive feature116and the portion132A,132B. In some embodiments, the distance D4is in a range of 20 μm to 100 μm. However, in some alternative embodiments, the bonding structure120A,120B may be disposed closer to the portion132A,132B, for example, the outermost edge of the bonding structure120A,120B may be substantially flush with the outermost edge of the conductive feature116. Thus, the additional distance is not required. Accordingly, the shortest distance D1A, D1Bmay be reduced, and the length of the die-to-die talking path TP is shortened.

In some embodiments, an encapsulant302, a redistribution layer structure304, a plurality of pads310and a passivation layer312are further included in a semiconductor package1ofFIG. 1B. In some embodiments, the semiconductor package1may be a high performance multi-die package which requires extremely short talking path, for example.

The encapsulant302is disposed over the integrated circuit200and aside the first and second dies100A,100B. Specifically, the encapsulant302surrounds sides102a,102b,102c,102dof the first and second dies100A,100B, exposes tops of the first and second dies100A,100B and overlays the surface (e.g., front surface) of the integrated circuit200. In some embodiments, the surfaces (e.g., back surfaces) of the first and second dies100A,100B are substantially coplanar with the top surface of the encapsulant302. In some embodiments, the encapsulant302includes a molding compound. The molding compound may include a resin and a filler. In alternative embodiments, the encapsulant302includes silicon oxide, silicon nitride or a combination thereof. The encapsulant302may be formed by spin-coating, lamination, deposition or the like.

In some alternative embodiments, a plurality of through dielectric vias may be disposed in the encapsulant302and electrically connected with the interconnect structure210and the to-be-formed redistribution layer structure304. In some embodiments, the through dielectric vias include conductive vias. The conductive vias include copper, a copper alloy, aluminum, an aluminum alloy or a combination thereof. In some embodiments, the through dielectric vias further include a diffusion barrier layer between the conductive vias and the encapsulant302. The diffusion barrier layer includes Ta, TaN, Ti, TiN, CoW or a combination thereof.

The redistribution layer structure304is disposed over the surfaces (e.g., back surfaces) of the first and second dies100A,100B and over the encapsulant302. The redistribution layer structure304includes at least one dielectric layer306and at least one conductive layer308stacked alternately. In some embodiments, a portion of the redistribution layer structure304is electrically connected to the through silicon vias106. In some embodiments, another portion of the redistribution layer structure304may be electrically connected to the through dielectric vias, to electrically connect the integrated circuit200. In some embodiments, the dielectric layer306includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. In some embodiments, the conductive layer308includes copper, nickel, titanium, a combination thereof or the like.

The pads310are disposed over the redistribution layer structure304. In some embodiments, the pads310are under bump metallization (UBM) pads. The pads310include a metal or a metal alloy. The pads310includes aluminum, copper, nickel, or an alloy thereof.

The passivation layer312covers the dielectric layer306and edge portions of the pads310, and exposes the center portions of the pads310. In some embodiments, the passivation layer312includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO) or a combination thereof.

The conductive connectors314are mounted to the pads310. In some embodiments, the conductive connectors314may be ball grid array (BGA) connectors, solder balls, metal pillars, and/or the like. The conductive connectors314may be formed by a mounting process and a reflow process, for example.

In some embodiments, a portion of the seal ring adjacent to another die has a narrower width than other portions of the seal ring. Therefore, the space for the portion of the seal ring may be reduced, and the bonding structure may become closer to another die. Therefore, the talking path between the bonding structures of the adjacent dies may be shortened, and the performance of the semiconductor package may be improved.

FIG. 2Ais a top view of a semiconductor package in accordance with some embodiments, andFIG. 2Bis a cross-sectional view of a semiconductor package along the line I-I ofFIG. 2Ain accordance with some embodiments. For simplicity and clarity of illustration, only few elements such as first and second dies, an integrated circuit, seal rings, bonding structures and conductive features are shown in the simplified top view ofFIG. 2A, and these elements are not necessarily in the same plane.

The semiconductor package2ofFIGS. 2A and 2Bis similar to the semiconductor package1ofFIGS. 1A and 1B. Thus, the difference between the semiconductor package2and the semiconductor package1is illustrated in details below and the similarity between them is not iterated herein.

Referring toFIGS. 2A and 2B, the semiconductor package2includes a first die100A, a second die100B and an integrated circuit200. The first die100A and the second die100B are bonded to the integrated circuit200. In some embodiments, bonding structures120A of the first die100A are bonded to bonding structures220of the integrated circuit200, and bonding structures120B of the second die100B are bonded to bonding structure220of the integrated circuit200. In addition, a conductive feature216of the integrated circuit200electrically connects the bonding structures220, so as to electrically connect the first die100A and the second die100B.

In some embodiments, the first and second dies100A,100B have seal rings130A,130B. In some embodiments, the seal ring130A,130B is merely disposed at the sides102b,102c,102d, for example. The seal ring130A,130B may be continuously disposed along the sides102b,102c,102d. In other words, no seal ring is disposed at the side102a. Specifically, no seal ring is disposed in a region RA, RBbetween the side102aand the conductive feature116connected to the bonding structure120A,120B. In other words, the region RA, RBis a seal ring-free region. Therefore, as shown inFIG. 2A, from a top view, the seal ring130A,130B is not overlapped with the conductive feature216. In some embodiments, the seal ring130A,130B may be U-shaped, for example.

In some embodiments, since no seal ring or any other component of the die is disposed in the region RA, RB between the side102aand the conductive feature116connected to the bonding structure120A,120B, the space for the seal ring or any other component is not required. In some embodiments, there is merely dielectric layer (i.e., the insulating layer112) in the region RA, RB, for example. Accordingly, a die-to-die talking path TP is substantially equal to a total of a distance DA between the bonding structure120A and the side102aof the first die100A, a distance DAB between the first die100A and the second die100B and a distance DB between the bonding structure120B and the side102aof the second die100B. The distance DA, DB between the bonding structure120A,120B and the side102ais smaller than a distance (such as a distance D3) between the bonding structure120and other side102b,102c,102d. In some embodiments, the distance DA, DB between the bonding structure120A,120B and the side102aof the first and second dies100A,100B depends on the process window of the photolithography or singulation or placement process of the first and second dies100A,100B. In some embodiments, the distance DA, DB may be in a range of 25 μm to 200 μm, for example. In some embodiments, the distance DAB may be in a range of 10 μm to 100 μm, for example. In some embodiments, the length of the die-to-die talking path may be reduced to 60 μm or more, for example. In some embodiments, by removing a portion of the seal ring between the bonding structure and the side adjacent to another die, the talking path between the dies may be shortened.

In some alternative embodiments, the bonding structure120A,120B may be disposed closer to the outermost edge of the conductive feature116, for example, the outermost edge of the bonding structure120A,120B may be substantially flush with the outermost edge of the conductive feature116. Accordingly, the distance DA, DBmay be further reduced, and the length of the die-to-die talking path TP may be shorter.

FIG. 3Ais a top view of a semiconductor package in accordance with some embodiments, andFIG. 3Bis a cross-sectional view of a semiconductor package along the line I-I ofFIG. 3Ain accordance with some embodiments. For simplicity and clarity of illustration, only few elements such as first and second dies, an integrated circuit, bonding structures and conductive features are shown in the simplified top view ofFIG. 3A, and these elements are not necessarily in the same plane.

The semiconductor package3ofFIGS. 3A and 3Bis similar to the semiconductor package1ofFIGS. 1A and 1B. Thus, the difference between the semiconductor package3and the semiconductor package1is illustrated in details below and the similarity between them is not iterated herein.

Referring toFIGS. 3A and 3B, the semiconductor package3includes a first die100A, a second die100B and an integrated circuit200. The first die100A and the second die100B are bonded to the integrated circuit200. In some embodiments, bonding structures120A of the first die100A are bonded to bonding structures220of the integrated circuit200, and bonding structures120B of the second die100B are bonded to bonding structure220of the integrated circuit200. In addition, a conductive feature216of the integrated circuit200electrically connects the bonding structures220, so as to electrically connect the first die100A and the second die100B.

In some embodiments, there is no seal ring in the first and second dies100A,100B. In other words, the region RA, RBis a seal ring-free region, and the first and second dies100A,100B may be seal ring-free dies. Accordingly, no seal ring is disposed in a region RA, RBbetween the side102aand a conductive feature116connected to the bonding structure120A,120B.

In some embodiments, since no seal ring or any other component of the die is disposed in the region RA, RB between the side102aand the conductive feature116, the space for the seal ring or any other component is not required. In some embodiments, there is merely dielectric layer (i.e., the insulating layer112) in the region RA, RB, for example. Accordingly, a die-to-die talking path TP is substantially equal to a total of a distance DA between the bonding structure120A and the side102aof the first die100A, a distance DAB between the first die100A and the second die100B and a distance DB between the bonding structure120B and the side102aof the second die100B. The distance DA, DB between the bonding structure120A,120B and the side102ais substantially equal to a distance (such as a distance D3) between the bonding structure120and other side102b,102c,102d.

In some embodiments, the distance DA, DBbetween the bonding structure120A,120B and the side102aof the first and second dies100A,100B depends on the process window of the photolithography or singulation or placement process of the first and second dies100A,100B. In some embodiments, the distance DA, DBmay be in a range of 25 μm to 200 μm, for example. In some embodiments, the distance DABmay be in a range of 10 μm to 100 μm, for example. In some embodiments, the length of the die-to-die talking path may be reduced to 60 μm or more, for example. In some embodiments, by providing the seal ring-free dies, the talking path between the dies may be shortened.

In some alternative embodiments, the bonding structure120A,120B may be disposed closer to the outermost edge of the conductive feature116, for example, the outermost edge of the bonding structure120A,120B may be substantially flush with the outermost edge of the conductive feature116. Accordingly, the distance DA, DBmay be further reduced, and the length of the die-to-die talking path TP may be shorter.

In above embodiments, the first die100A and the second die100B adopt the same technique to reduce the distance between the bonding structure120A,120B and the side102a, however, the invention is not limited thereto. In some alternative embodiments, the first die100A and the second die100B may adopt different technique to reduce the distance between the bonding structure120A,120B and the side102a. For example, in some alternative embodiments, a first die may be selected from the first dies100A inFIGS. 1A to 3Bor the like, and a second die may be selected from the second dies100B inFIGS. 1A to 3Bor the like. In addition, although there are two adjacent dies (i.e., the first die and the second die) illustrated, more than two dies may be bonded to the integrated circuit.

In view of the above, the space for the element may be reduced or eliminated by narrowing the width of the element (such as a seal ring), removing a portion of the element (such as a seal ring) or totally removing the element (such as a seal ring) from the die. Therefore, the bonding structure of one die may become closer to the bonding structure of another die. Accordingly, the talking path between the bonding structures of the adjacent dies may be shortened, and the performance of the semiconductor package may be improved.

In accordance with some embodiments of the present disclosure, a semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. A first portion of the first seal ring is disposed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring.

In accordance with alternative embodiments of the present disclosure, a semiconductor package includes an integrated circuit, a first die and a second die. The integrated circuit includes a conductive feature. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. The conductive feature is disposed between and electrically connected to the first bonding structure and the second bonding structure, and the first seal ring is not overlapped with the conductive feature from a top view.

In accordance with yet alternative embodiments of the present disclosure, a semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first conductive feature at a first side of the first die. The first bonding structure is bonded to the integrated circuit and disposed between the integrated circuit and the first conductive feature. The first conductive feature is physically connected to the first bonding structure. The second die includes a second bonding structure at a first side of the second die. The second bonding structure is bonded to the integrated circuit, and the first side of the first die faces the first side of the second die. A region between the first conductive feature and the first side of the first die is a seal ring-free region.