Semiconductor structure comprising pillar

A semiconductor structure comprises a substrate and a metal layer disposed over the substrate. The metal layer comprises a first electrical trace and a second electrical trace. The semiconductor structure comprises a conductive pillar disposed directly on and in electrical contact with the first electrical trace; and a dielectric layer selectively disposed between the metal layer and the conductive pillar. The dielectric layer electrically isolates the second electrical trace from the pillar.

BACKGROUND

Packaging of semiconductor devices has lead to the implementation of various techniques to effect electrical connections to the semiconductor devices as well as to effect paths to dissipate heat. One known technique to provide electrical connections includes selectively bonding wires to the semiconductor device. This technique referred to as ‘wire-bonding’ has certain drawbacks. For example, wire bonds add parasitic inductance, which can impact the performance of the semiconductor device especially at comparatively high frequency operation. In addition, wire bonds do not efficiently dissipate heat away from the semiconductor device. These and other drawbacks to wire-bonding have led to the implementation of so-called pillars as an alternate method of effecting electrical and thermal connections to semiconductor devices.

FIG. 1shows a known semiconductor structure100. The semiconductor structure100comprises a substrate101. The substrate101is GaAs and includes a collector layer102formed therein by known methods. A base layer103is provided over the collector layer102, and an emitter layer104is provided over the collector layer102to provide a heterojunction bipolar transistor (HBT).

Contacts105are made to the base layer103and the collector layer102. A first metal layer106is provided on the contacts105and the emitter layer104. A second metal layer107is provided on the first metal layer106. The first metal layer106and the second metal layer107are used for routing signals to and from the HBT. A third metal layer108is provided on the second metal layer107. The third metal layer108provides a planar surface for attachment of a pillar109thereover. The pillar109provides a thermal dissipation path and electrical ground through the third metal layer108. A layer110of benzocyclobutene (BCB) or polyimide is provided beneath the third metal layer108and provides a planar surface on which the third metal layer108is formed.

Because each successive metal layer must fit within the ‘footprint’ of the last metal layer, the feature size of each successive metal layer must be smaller than the feature size of the previous metal layer. For example, second metal layer107has narrower line-widths than the first metal layer106. However, with each successive metal layer, photolithographic resolution is reduced. This reduction in photolithographic resolution results in an overall increase in the feature size of each successive metal layer, and ultimately an increase in the size of the die of the semiconductor structure. Moreover, in the semiconductor structure100, the upper-most metal layer (third metal layer108) is comparatively thick, but cannot be used for signal routing under the pillar109. Thus, the current-handling capability of the upper-most metal layer is not efficiently utilized in the semiconductor structure100.

There is a need, therefore, for a semiconductor structure that supports a minimum number of metal layers to be used while overcoming at least the shortcomings of known semiconductor interconnect structures discussed above.

SUMMARY

In a representative embodiment, a semiconductor structure comprises a substrate and a metal layer disposed over the substrate. The metal layer comprises a first electrical trace and a second electrical trace. The semiconductor structure comprises a conductive pillar disposed directly on and in electrical contact with the first electrical trace; and a dielectric layer selectively disposed between the metal layer and the conductive pillar. The dielectric layer electrically isolates the second electrical trace from the pillar.

In another representative embodiment, a semiconductor structure comprises a substrate and a first metal layer disposed over the semiconductor device. The first metal layer comprises a first electrical signal trace. The semiconductor structure comprises a second metal layer disposed over the first metal layer. The second metal layer comprises a second electrical signal trace and an electrical ground trace. The semiconductor structure comprises a conductive pillar disposed directly on and in electrical contact with the electrical ground trace; and a dielectric layer selectively disposed between the first metal layer, the second metal layer and the conductive pillar. The dielectric layer electrically isolates the second electrical signal trace from the pillar.

DETAILED DESCRIPTION

In the following detailed description, for purposes of explanation and not limitation, representative embodiments disclosing specific details are set forth in order to provide a thorough understanding of the present teachings. Descriptions of known devices, materials and manufacturing methods may be omitted so as to avoid obscuring the description of the example embodiments. Nonetheless, such devices, materials and methods that are within the purview of one of ordinary skill in the art may be used in accordance with the representative embodiments.

FIG. 2Ashows a cross-sectional view of a semiconductor structure200in accordance with a representative embodiment. The semiconductor structure200comprises a substrate201which may be selected based on the active semiconductor device fabricated thereon. In certain embodiments, the substrate201comprises a semiconductor material. Illustrative semiconductor materials for the substrate201include binary semiconductor materials (e.g., Group III-IV and Group IV-VI semiconductor materials), ternary semiconductor materials, silicon (Si) and silicon-germanium (SiGe). Moreover, the present teachings contemplate the use of synthetic diamond for the substrate201fabricated by a known chemical vapor deposition (CVD) method.

As should be appreciated, the selection of the active semiconductor device and the material for the substrate201dictates the processing techniques and materials selected for fabricating the active semiconductor device and other components of the semiconductor structure200. Such techniques and materials are within the purview of one of ordinary skill in the art of semiconductor processing and are generally not detailed herein to avoid obscuring the description of the representative embodiments.

For ease of description, the substrate201comprises GaAs, and the active semiconductor device is a heterojunction bipolar transistor (HBT). It is emphasized that the selection of GaAs for the substrate201and the selection of the HBT device are merely illustrative, and other substrate materials and active devices are contemplated. Illustratively, the active device may be a pseudomorphic high electron mobility transistor (pHEMT). Alternatively, the substrate may comprise silicon and the active device may comprise a metal oxide semiconductor (MOS) device such as a MOS field effect transistor (MOSFET) or complementary MOS (CMOS) device. Additionally, a combination of a plurality of the different active devices may be provided over the substrate201to provide a desired circuit. Furthermore, the active devices of the semiconductor structure200may provide power amplifiers and other devices that require heat dissipation. While such power devices are illustrative, other active semiconductor devices that do not require the same degree of heat dissipation as power devices (e.g., power amplifiers) are contemplated to be included in the semiconductor structure200.

It is noted that the semiconductor structure200may comprise passive electrical components (not shown inFIG. 2A) formed in or over the substrate201and in addition to active semiconductor devices referenced above. The combination of active semiconductor devices and passive electrical components provides electrical circuits of the semiconductor structure200. Passive electrical components include for example, resistors, capacitors, signal transmission lines (transmission lines), and inductors. These passive electrical components may be selectively electrically connected to the active semiconductor device(s) to provide a desired circuit. The passive electrical components may be fabricated using known methods and materials. Notably, the various current-carrying traces of the semiconductor structure200can function as transmission lines and inductors. In certain embodiments, only passive electrical components are provided, rather than a semiconductor material, the substrate201comprises an insulator such as a suitable glass material or sapphire.

The HBT comprises a collector202, a base203and an emitter204formed in/over the substrate201with known materials and by known methods. Ohmic contacts (‘contacts’)205are selectively provided to the base203and the collector202as shown. Contacts205are generally gold (Au) and are formed by known methods. In the representative embodiment, a first metal layer206is selectively disposed over the contacts205to the base203and the collector202, and over the emitter204. Illustratively, the first metal layer206comprises gold. Alternatively, the first metal layer206may comprise aluminum or copper

The first metal layer206comprises signal traces for carrying electrical signals to and from the emitter204, the base203and the collector202of the HBT. As discussed more fully below, the first metal layer206also comprises electrical ground traces and thermal paths for heat dissipation. Trace widths of the signal and ground traces of the first metal layer206can be less than approximately 1.0 μm to greater than approximately 100 μm. Typically, however, the trace widths of the signal and ground traces of the first metal layer206are in the range of approximately 2.0 μm to approximately 20.0 μm. Moreover, the thickness of the signal and ground traces of the first metal layer206is illustratively in the range of approximately 0.2 μm to approximately 2.0 μm.

The semiconductor structure200also comprises a second metal layer207selectively disposed over the first metal layer206. In the representative embodiment, the second metal layer207comprises signal traces for carrying electrical signals to and from the collector202, electrical ground traces for connection to the emitter204, and provides thermal paths for heat dissipation. Illustratively, the second metal layer207comprises gold. Alternatively, the second metal layer207may comprise aluminum or copper

Trace widths of the signal and ground traces of the second metal layer207are typically in the range of approximately 3.0 μm to approximately 50.0 μm. Moreover, the thickness of the signal and ground traces of the second metal layer207is illustratively in the range of approximately 1.0 μm to approximately 4.0 μm.

The semiconductor structure200also comprises a dielectric layer208selectively disposed over the HBT (or other active semiconductor device(s)), the contacts205, the first metal layer206, and the second metal layer207. As described more fully below, the dielectric layer208provides electrical isolation of certain traces of the first metal layer206and of the second metal layer207, and mechanical support of layers disposed over the dielectric layer208. In certain representative embodiments, the dielectric layer208comprises one of silicon nitride (Si3N4), silicon dioxide (SiO2), aluminum nitride (AlN) or an oxynitride (e.g., aluminum oxynitride). As discussed more fully below, the selection of one of these dielectric materials provides the advantage of improved thermal conductivity for heat dissipation, as well as selective electrical isolation of the contacts205, and the respective traces of the first metal layer206, the second metal layer207. Alternatively, the dielectric layer208may comprise a known spun-on dielectric such as BCB or polyimide or a combination of BCB or polyimide, and silicon oxide, silicon nitride or silicon oxynitride. For example, in a representative embodiment, the dielectric layer208may comprise a layer of BCB that is ‘spun on’, and subsequently covered with a layer of silicon nitride by a known technique.

The semiconductor structure200also comprises an electrically conductive pillar (‘pillar’)209. The pillar209provides a thermal path to transfer heat from the HBT (or other active semiconductor device of the semiconductor structure200), passive electrical components, and provides selective electrical connections to the second metal layer207. Notably, the pillar209is in direct contact with and is disposed directly on certain traces of the second metal layer207to selectively provide electrical connections (a ground connection or a signal connection) and to provide paths for thermal dissipation of heat. As described more fully below, the semiconductor structure200generally comprises more than one pillar209, with each pillar209being connected to different active semiconductor devices, or passive electrical components, or both located in/over different areas of the substrate201. As further described below, the pillar(s)209are connected to a second substrate (not shown inFIG. 2A), which comprises external circuitry (not shown) to include active semiconductor devices, passive electrical components and ground connections (e.g., conductive vias). The external circuitry of the second substrate in turn may be connected to further external circuitry (also not shown), which also may include active semiconductor devices, passive electrical components and ground connections. Depending on the selected connection of the pillar209to external circuitry (not shown), the pillar209can provide signal connections or ground connections between active semiconductor devices, or passive electrical components, or both, of the semiconductor structure200. Selective electrical connection of ground traces of the second metal layer207to one of the pillars209results in a ‘ground pillar.’ Selective electrical connection of signal traces of the second metal layer207to another of the pillars209results in a ‘signal pillar.’ Other traces of the second metal layer207are electrically isolated from the pillar209, but heat is dissipated from the second metal layer207through the dielectric layer208.

Illustratively, the pillar209is in direct contact with and is disposed directly on trace207A of the second metal layer207. Thus, trace207A of the second metal layer207electrically connects the pillar209to the first metal layer206, and ultimately to the emitter of the HBT as shown. Depending on the connection of the pillar209to the external circuitry, the electrical connection between the metal trace207A and the pillar209will be either an electrical signal connection or an electrical ground connection. Trace207A of the second metal layer207provides both an electrical conduction path and a thermal conduction path from the emitter204of the HBT. By contrast, trace207B of the second metal layer207is mechanically connected to the pillar209, but is electrically isolated from the pillar209by the dielectric layer208. Thus, the pillar209is not in direct contact with trace207B, but instead is in direct contact with and is disposed on the dielectric layer208. As such, the collector202of the HBT is electrically isolated from the pillar209. However, the mechanical connection between the collector202, the dielectric layer208and the pillar209provides a thermal path for conduction of heat from the collector202of the HBT via the trace207B of the second metal layer207to the pillar209through the dielectric layer208.

The pillar209illustratively comprises copper (Cu) formed by a known method such as evaporation or plating. The pillar209has sufficient thickness for providing both current carrying capability from the second metal layer207(e.g., through trace207A) and heat dissipation from the second metal layer (e.g., through traces207A and207B). Typically, the pillar209comprises copper having a thickness in the range of approximately 10 μm to approximately 100 μm and greater than 100 μm. The thermal and electrical conductivity of copper are advantageous over other conductors such as gold. However, other electrically and thermally conductive materials are contemplated for use as the pillar209. Illustratively, the pillar209may comprise silver (Ag) or a solder material such as tin (Sn). The silver may be deposited by a known method, and solder may be applied using known solder bump deposition methods.

In certain embodiments, the pillar209comprises a single layer of the selected conductive material (e.g., copper). It is emphasized that this is merely illustrative, and the pillar209may comprise more than one layer of the selected conductive material (e.g., multiple layers of copper). Alternatively, the pillar209may comprise layers of different materials. For example, in certain embodiments the pillar209comprises a comparatively thick (e.g., 45 μm) layer of copper and a layer of solder (e.g., 30 μm), such as SnAg or SnCu solder disposed over the layer of copper. Still alternatively, the pillar209may comprise a first layer of copper having a thickness of approximately 10 μm disposed immediately over the upper-most metal layer (second metal layer207in the illustrative embodiment) and making selective electrical contact therewith; a second layer of copper having a thickness of approximately 35 μm disposed over the first layer of copper; and a layer of solder (e.g., SnAg or SnCu) having a thickness of approximately 35 μm disposed over the second layer of copper.

The selective electrical and thermal connections between the pillar209and the second metal layer207provide certain advantages over known structures. For example, discontinuous electrical and mechanical connections are provided between the second metal layer207and the pillar209. This allows the elimination of a continuous metal layer between the pillar209and the second metal layer207. As should be appreciated by one of ordinary skill in the art, the elimination of this additional metal layer accords finer features at the upper-most metal layer of the semiconductor structure200. Ultimately, this allows for comparatively reduced pitch of the metal traces of the semiconductor structure200. Moreover, because the features of the upper-most metal layer (second metal layer207in the present embodiment) can be made comparatively small, the thickness of the upper-most metal layer can be made comparatively large. This increased thickness improves the current-carrying capability of the traces (e.g., trace207A) of the upper-most metal layer (e.g., second metal layer207) of the semiconductor structure200. Beneficially, by connecting the pillar209directly to the upper-most metal layer (the second metal layer207in this embodiment) comprising signal traces or ground traces, a comparatively thick trace can be used for current routing under the pillar209than if the upper-most metal layer was used for attaching the pillar209and a lower (and thinner) metal layer was used for current routing.

The dielectric layer208is deposited conformally over the HBT, the contacts205, the first metal layer206and the second metal layer207by a known deposition method. Selective etching by known masking and plasma etching techniques removes the dielectric from the upper surfaces of the selected traces (e.g., trace207A) of the second metal layer207to allow for selective electrical connection between the pillar209and the second metal layer207. By not removing the dielectric layer208from selected traces (e.g., trace207B) and the pillar209, the dielectric layer208provides selective electrical isolation of second metal layer207and the pillar209.

As noted, in certain embodiments, the dielectric layer208comprises a material having comparatively good thermal conductivity, which improves the dissipation of heat from the underlying active semiconductor device (e.g., the HBT), through the contacts205, the first metal layer206, and the second metal layer207. Moreover, Applicants have discovered an improved mechanical adhesion of the pillar209to the dielectric layer208can be realized by selection of dielectric layers that have a lesser degree of planarity upon deposition. For example, the use of silicon nitride provides a lesser degree of planarity at the interface of the dielectric layer208and the pillar209. This reduced planarity has been found to result in an improved mechanical adhesion of the pillar209to the dielectric layer208, and as a result, in an improved mechanical robustness of the semiconductor structure200.

FIG. 2Bshows a cross-sectional view of a semiconductor structure210in accordance with a representative embodiment. Many of the features of semiconductor structure200are common to the semiconductor structure210. Details of these common features may not be repeated so as to avoid obscuring the details of the presently described embodiments.

The semiconductor structure210comprises substrate201which is selected based on the active semiconductor device fabricated thereon. In certain embodiments, the substrate201comprises a semiconductor material. Illustrative semiconductor materials for the substrate201include binary semiconductor materials (e.g., Group III-IV and Group IV-VI semiconductor materials), ternary semiconductor materials, silicon (Si) and silicon-germanium (SiGe). Moreover, the present teachings contemplate the use of synthetic diamond for the substrate201fabricated by a known chemical vapor deposition (CVD) method.

Again, for ease of description, the substrate201comprises GaAs, and the active semiconductor device is a heterojunction bipolar transistor (HBT). It is emphasized that the selection of GaAs for the substrate201and the selection of the HBT device are merely illustrative, and other substrate materials and active devices are contemplated. Illustratively, the active device may be a pseudomorphic high electron mobility transistor (pHEMT). Alternatively, the substrate may comprise silicon and the active device may comprise a metal oxide semiconductor (MOS) device such as a MOS field effect transistor (MOSFET) or complementary MOS (CMOS) device. Additionally, a combination of active devices may be provided over the substrate201to provide a desired circuit. Furthermore, the active devices of the semiconductor structure210may provide power amplifiers and other devices that require heat dissipation. While such power devices are illustrative, other active semiconductor devices that do not require the same degree of heat dissipation as power devices (e.g., power amplifiers) are contemplated to be included in the semiconductor structure210.

It is noted that the semiconductor structure210may comprise passive electrical components (not shown inFIG. 2B) formed in or over the substrate201and in addition to active semiconductor devices referenced above. The combination of active semiconductor devices and passive electrical components provides electrical circuits of the semiconductor structure210. Passive electrical components include for example, resistors, capacitors, signal transmission lines (transmission lines), and inductors. These passive electrical components may be selectively electrically connected to the active semiconductor device to provide a desired circuit. The passive electrical components may be fabricated using known methods and materials. Notably, the various current-carrying traces of the semiconductor structure210can function as transmission lines and inductors. In certain embodiments, only passive electrical elements are provided, rather than a semiconductor material, the substrate201comprises an insulator such as a suitable glass material or sapphire.

The HBT comprises collector202, base203and emitter204. Ohmic contacts (‘contacts’)205are selectively provided to the base203and collector202as shown. Contacts205are generally gold (Au) and are formed by known methods. In the representative embodiment, first metal layer206is selectively disposed over the contacts205to the base203and the collector202, and over the emitter204. Illustratively, the first metal layer206comprises gold. Alternatively, the first metal layer206may comprise aluminum, or copper

The first metal layer206comprises electrical signal traces for carrying electrical signals to and from the emitter204, the base203and the collector202of the HBT. As discussed more fully below, the first metal layer206also comprises electrical ground traces and thermal paths for heat dissipation. Trace widths of the signal and ground traces of the first metal layer206can be less than approximately 1.0 μm to greater than approximately 100 μm. Typically, however, the trace widths of the signal and ground traces of the first metal layer206are in the range of approximately 2.0 μm to approximately 20.0 μm. Moreover, the thickness of the signal and ground traces of the first metal layer206is illustratively in the range of approximately 0.2 μm to approximately 2.0 μm.

The semiconductor structure210also comprises second metal layer207selectively disposed over the first metal layer206. The second metal layer207comprises signal traces for carrying electrical signals to and from the collector202, electrical ground traces for connection to the emitter204, and thermal paths for heat dissipation. Illustratively, the second metal layer207comprises gold. Alternatively, the second metal layer207may comprise aluminum or copper

Trace widths of the signal and ground traces of the second metal layer207are typically in the range of approximately 3.0 μm to approximately 50.0 μm. Moreover, the thickness of the signal and ground traces of the second metal layer207is illustratively in the range of approximately 1.0 μm to approximately 4.0 μm.

The semiconductor structure210also comprises dielectric layer208selectively disposed over the HBT (or other active semiconductor device), the contacts205, the first metal layer206, and the second metal layer207. As described more fully below, the dielectric layer208provides electrical isolation of certain traces of the first metal layer206and of the second metal layer207, and mechanical support of layers disposed over the dielectric layer208. In certain representative embodiments, the dielectric layer208comprises one of silicon nitride (Si3N4), silicon dioxide (SiO2), aluminum nitride (AlN) or an oxynitride (e.g., aluminum oxynitride). Alternatively, the dielectric layer208may comprise a known spun-on dielectric such as BCB or polyimide or a combination of BCB or polyimide, and silicon oxide, silicon nitride or silicon oxynitride. For example, in a representative embodiment, a layer of BCB may be spun on, and subsequently covered with a layer of silicon nitride to provide the dielectric layer208.

The semiconductor structure210also comprises electrically conductive pillar (‘pillar’)209. The pillar209provides a thermal path to transfer heat from the HBT (or other active semiconductor devices of the semiconductor structure210), from passive electrical components, and provides selective electrical connection to the second metal layer207. As noted previously, the semiconductor structure210generally comprises more than one pillar209, with each pillar209being connected to different areas of the substrate201. As further described below, the pillar(s)209are connected to a second substrate (not shown inFIG. 2B), which comprises external circuitry (not shown) to include active semiconductor devices and passive electrical components. The external circuitry of the second substrate in turn may be connected to further external circuitry (also not shown), which also may include active semiconductor devices and passive electrical components.

In the representative embodiment depicted inFIG. 2B, the pillar209is in direct contact with and is disposed directly on the second metal layer207. As such, the pillar209is in direct contact with collectors202of the HBTs of the semiconductor structure210via second metal layer207to selectively provide electrical signal connections thereto from external circuitry (not shown) such as from a second substrate (not shown inFIG. 2B) to which the pillar209is connected. For example, the pillar209is disposed directly on and is in direct contact with trace207C of the second metal layer207. Thus, trace207C of the second metal layer207electrically connects the pillar209to the first metal layer206, and ultimately to the collector202of the HBT as shown. In such a configuration, the pillar209functions as a ‘signal pillar.’

Moreover, the pillar209provides paths for thermal dissipation of heat from active semiconductor devices, or passive electrical components, or both, disposed on the substrate201. Trace207C of the second metal layer207provides both an electrical conduction path and a thermal conduction path from the collector202of the HBT. Other traces of the second metal layer207of the semiconductor structure210are electrically isolated from the pillar209, but heat is dissipated from the second metal layer207through the dielectric layer208. For example, trace207D of the second metal layer207is mechanically connected to the pillar209, but is electrically isolated from the pillar209by the dielectric layer208. Thus, the pillar209is not in direct contact with trace207D, but instead is in direct contact with and is disposed on the dielectric layer208. As such, the emitter204of the HBT is electrically isolated from the pillar209. However, the mechanical connection between provides a thermal path for conduction of heat from the emitter204of the HBT via the trace207D of the second metal layer207to the pillar209through the dielectric layer208. Similarly, the base203is separated from the pillar209by the dielectric layer208and is electrically isolated from the pillar209. However, the mechanical connection between provides a thermal path for conduction of heat from the emitter204of the HBT. The pillar(s)209are generally connected to a second substrate (not shown inFIG. 2B), which comprises external circuitry (not shown).

FIG. 2Cshows a simplified schematic diagram of an HBT of the semiconductor structure210depicted inFIG. 2B. Notably, the collector202of the HBT is connected to the pillar209, and thus the pillar209is a ‘signal pillar.’ The disposition of the dielectric layer208between the pillar209and the base203and the emitter204result in the ‘isolated bases’ and ‘isolated emitters’ as depicted in the simplified schematic diagram.

FIG. 3shows a top view of the semiconductor structure200ofFIG. 2Abefore disposition of the pillar209. As should be appreciated by one of ordinary skill in the art, the fabrication sequence that results in the semiconductor structure depicted inFIG. 3is the so-called ‘front-end’ processing of the semiconductor structure200. A subsequent fabrication sequence to provide the pillar209and, as described below, to provide attachment to subsequent substrates (not shown inFIG. 3) and structures is the so-called ‘back-end’ processing of the semiconductor structure200.

Notably, trace207A is shown with the second metal layer207shown generally. As should be appreciated, each exposed trace (e.g.,207A) of the second metal layer207provides an electrical and mechanical connection to the first metal layer206(not shown inFIG. 3) and the selected components of the underlying HBT. For example, in the presently described embodiment, the exposed traces of the second metal layer207make electrical contact to the emitter204(not shown inFIG. 3). By contrast, other metal traces of the second metal layer207(e.g., trace207B (not shown inFIG. 3)) are covered by the dielectric layer208and are thus electrically isolated from the pillar209(not shown inFIG. 3). For example, in the presently described embodiment, electrically isolated traces of the second metal layer207provide electrical isolation of the collector202and the pillar209. However, the mechanical connection between the pillar209and the electrically isolated traces of the second metal layer is provided. This provides a thermal path for heat dissipation from the collector202, for example. As noted above, the elimination of this additional metal layer accords finer features at the upper-most metal layer of the semiconductor structure200. Ultimately, this allows for a comparatively reduced pitch of the metal traces of the second metal layer207of the semiconductor structure200. Notably, the pitch between the exposed metal traces of the second metal layer207(e.g., trace207A) is approximately 22.0 μm.

FIG. 4shows a cross-sectional view of a semiconductor structure400in accordance with a representative embodiment. Many of the details of the representative embodiments described in connection withFIGS. 2A˜3are common to the presently described representative embodiment. Many of the common details are not repeated in order to avoid obscuring the description of the present embodiment. For example, details of representative materials and methods of fabricating features of the semiconductor structure400are generally not repeated.

The semiconductor structure400comprises a substrate401and a passive electrical component layer402provided thereover. The passive electrical component layer402comprises passive electrical components disposed thereover, or formed therein, or both, to provide the passive electrical components of the semiconductor structure400. It is contemplated that the passive electrical component layer402not be a separate and distinct layer from the substrate401, but rather may be a portion of the substrate401over which or in which passive electrical (or both) components are provided. The passive electrical components may be resistors, capacitors, transmission lines, and inductors, such as described above and fabricated using known methods and materials.

A metal layer403is provided over the passive electrical component layer402. Notably, the metal layer403is the only metal layer of the semiconductor structure400and provides all current handling requirements for the underlying passive electrical components. The metal layer403provides selective electrical connection to the passive electrical components. Illustratively, the metal layer403comprises gold and has a thickness of approximately 2.0 μm. With such a thickness, the features size of the traces of the metal layer403is approximately 2.0 μm; and the pitch of adjacent features is approximately 4.0 μm.

A dielectric layer404is provided over the metal layer403as shown. Illustratively, the dielectric layer comprises silicon nitride as has a thickness of approximately 0.8 μm. An electrically conductive pillar (‘pillar’)405is provided over the dielectric layer404and the metal layer403. The electrical connection between the passive electrical components of the passive electrical component layer402, the metal layer403and the pillar405may provide a signal connection or a ground connection, depending on the connection of the pillar405to external circuitry (not shown). As noted above, the present teachings contemplate a plurality of pillars405selectively connected (electrically or thermally, or both) to different areas of the substrate401, and to passive electrical components disposed thereover and formed therein.

Illustratively, the pillar405comprises copper and has a thickness of approximately 55 μm to approximately 60 μm. The pillar405may comprise multiple layers of the same or different materials as described above. An optional solder bump406is provided over the pillar405. The solder bump406illustratively comprises an alloy of copper and tin and has a thickness of approximately 25 μm to approximately 30 μm.

The dielectric layer404is provided over a surface407of a trace403A of the metal layer403and between the metal layer403and the pillar405. Thus, the pillar405is not in direct contact with trace403A, but instead is in direct contact with and is disposed on the dielectric layer404. The dielectric layer404thereby electrically isolates the trace403A from the pillar405. However, the dielectric layer404provides a mechanical connection between the trace403A and the pillar405. As described above, this mechanical connection fosters heat dissipation from the trace403A to the pillar405, and thereby heat from the underlying active semiconductor device can be dissipated through the pillar405.

By contrast, the dielectric layer404is removed (e.g., by etching) from a surface408of a trace403B of the metal layer403. As such, the pillar405is in direct contact with and is disposed directly on trace403B of the metal layer403. Thus, trace403B of the metal layer403electrically connects the pillar405to the passive electrical components. Depending on the connection of the pillar405to the external circuitry (not shown), the electrical connection between the metal trace403B and the pillar405will be either an electrical signal connection or an electrical ground connection. Accordingly, the removal of the dielectric layer404from surface408provides an electrical connection (signal or ground) and a mechanical connection between the trace403B of the metal layer403and the pillar405. Thereby, electrical and thermal connection can be made from underlying active semiconductor device through the metal layer403to the pillar405.

FIG. 5shows a cross-sectional view of a semiconductor structure500in accordance with a representative embodiment. Many of the details of the representative embodiments described in connection withFIGS. 2A˜4are common to the presently described representative embodiment. Many of the common details are not repeated in order to avoid obscuring the description of the present embodiment. For example, details of representative materials and methods of fabricating features of the semiconductor structure500are generally not repeated.

The semiconductor structure500comprises a first substrate501, which illustratively comprises a semiconductor material. The semiconductor structure500comprises an active semiconductor device502and a passive electrical component503. Illustratively, the active semiconductor device502comprises an HBT and the passive electrical component503comprises a resistor. It is emphasized that these are merely illustrative, and that other active semiconductor devices and other passive electrical components are contemplated. As noted above in the description of the embodiments ofFIGS. 2A˜4, the selection of the semiconductor material of the first substrate501is generally dictated by the active semiconductor device(s) to be implemented thereon.

A transmission line504is provided over the first substrate501and is electrically connected to the passive electrical component503. The active semiconductor device502comprises emitter traces505, base traces506and collector traces507. In keeping with the convention set forth in connection with the embodiments ofFIG. 2A, the emitter traces505are components of the second (upper-most) metal layer of the semiconductor structure500.

Dielectric layer508is selectively provided over the base traces506and the collector traces507as shown. The dielectric layer508is also selectively disposed over the transmission line504and the passive electrical component503. The selective disposition of the dielectric provides electrical isolation of selected traces and electrical passive components as described more fully below.

The semiconductor structure500comprises a first pillar509and a second pillar510disposed over the first substrate501. Because of the selection of electrical connections to the first pillar509, the first pillar509comprises a ‘ground pillar.’ By contrast, because of the selection of the electrical connections to the second pillar510, the second pillar510comprises a ‘signal pillar.’

In the representative embodiment shown inFIG. 5, the first pillar509comprises a first solder bump511, and the second pillar510comprises a second solder bump512. As noted above, the present teachings contemplate a plurality of ground pillars (e.g., first pillar509) and a plurality of signal pillars (e.g., second pillar510) selectively connected (electrically or thermally, or both) to different areas of the first substrate501, and to active semiconductor devices and passive electrical components disposed thereover and formed therein.

A signal trace513electrically connects the passive electrical component503to the second pillar510. This electrical connection is effected by selectively removing the dielectric layer508over the signal trace513. Similarly, the emitter traces505are electrically connected to the first pillar509. In the representative embodiment, the first pillar509is disposed directly on and in direct contact with the emitter traces505of the upper-most metal layer of the semiconductor structure500. As such, the emitters of the active semiconductor device502are electrically connected to the first pillar509. By contrast, the dielectric layer508is provided between the base traces506, the collector traces507and the transmission line504. Thus, the first pillar509is not in direct contact with base traces506or collector traces507, but instead is in direct contact with and is disposed on the dielectric layer508. As such, the bases and the collectors of the active semiconductor device502are electrically isolated from the first pillar509and the transmission line504is electrically isolated from both the first pillar509and the second pillar510. However, and as described above in detail in connection with representative embodiments, the dielectric layer508provides a mechanical connection to the isolated traces, contacts, passive electrical components and portions of the active semiconductor devices of the semiconductor structure500. This mechanical connection provides a thermal path for dissipating heat from the semiconductor structure500as well as provides a more robust mechanical structure.

The first and second pillars509,510are connected to a second substrate514. The second substrate514is illustratively a printed circuit board or similar substrate that connects the active semiconductor devices and passive electrical components disposed over or in the first substrate501to electrical circuits (not shown) disposed over the second substrate514, or formed therein, or connected thereto, or a combination thereof. Illustratively, known substrates including FR4, FR5, epoxy laminate, High Density Interconnect (HDI) substrates, Low Temperature Cofired Ceramic (LTCC) substrates, Thin Film on Ceramic substrates and Thick Film on Ceramic substrates are contemplated. The second substrate514comprises electrical circuitry comprising active semiconductor devices (not shown), or passive electrical components (not shown), or both, provided thereon or thereover. This electrical circuitry comprises the ‘external circuitry’ alluded to above, and can be connected to additional electrical circuitry (not shown) connected to the electrical circuitry of the second substrate514.

A printed circuit ground trace515is provided between the first pillar509and the second substrate514. A printed circuit signal trace516is provided between the second pillar510and the second substrate514. A via517is in contact with the printed circuit ground trace515and provides a thermal path for dissipation of heat as well as an electrical ground for connection to the first pillar509.

The semiconductor structure500of the representative embodiment provides two pillars (first pillar509and second pillar510) over a common substrate (first substrate501), which provide selective electrical and thermal connections to another substrate (second substrate514). The configuration allows for the connection of electrical signals traces and electrical ground traces to be selectively connected to the printed circuit ground trace515and the printed circuit signal trace516as shown. Moreover, the first pillar509and the second pillar510foster dissipation of heat from the active semiconductor devices and passive electrical components provided over the first substrate501.

It is emphasized that the configuration of the semiconductor structure500is merely illustrative. Notably, rather than connecting the emitter traces505of the active device (e.g., the HBT) electrically to ground through the connection of the first pillar509to the printed circuit ground trace515, the emitter traces505could be connected to the printed circuit signal trace516. Such connections would result from the variation of the connection of the first pillar509and the second pillar510to the respective signal and ground traces. Similarly, the passive electrical component503could be connected electrically to ground through the connection of the second pillar510to the printed circuit signal trace516. Moreover, the present teachings contemplate that both the first pillar509and the second pillar510are electrically connected to the printed circuit ground trace515or both are connected to the printed circuit signal trace516. In this manner the connection of the passive electrical components and active semiconductor devices provided over the first substrate501can be electrically connected as desired to the second substrate514and the circuitry thereon or connected thereto.

Regardless of the electrical connections of the first pillar509and the second pillar510, both pillars provide a thermal path for heat dissipation. This path of heat dissipation may be provided through the dielectric layer508in instances where the dielectric layer508provides electrical isolation of underlying signal traces (e.g., base traces506and collector traces507); and directly to the pillars where the dielectric layer508is removed from over the underlying signal trace (e.g., emitter traces505).

Additionally, it is again emphasized that the semiconductor structure500may comprise a plurality of pillars configured to connect the first substrate501to the second substrate514in order to selectively effect electrical connections, or ground connections, or both, and to provide thermal paths for heat dissipation between active semiconductor devices, or passive electrical components, or both. As such, by providing a plurality of pillars between the first substrate501and the second substrate514, a packaged semiconductor structure comprising active semiconductor devices and passive electrical components disposed over, or in or on a first substrate is realized in accordance with the present teachings.

In view of this disclosure it is noted that the various semiconductor structures and active semiconductor devices can be implemented in a variety of materials and variant structures. Further, the various materials, structures and parameters are included by way of example only and not in any limiting sense. In view of this disclosure, those skilled in the art can implement the present teachings in determining their own applications and needed materials and equipment to implement these applications, while remaining within the scope of the appended claims.